[
  {
    "path": ".gitignore",
    "content": "# Object files\n*.o\n*.ko\n*.obj\n*.elf\n\n# Libraries\n*.lib\n*.a\n\n# Shared objects (inc. Windows DLLs)\n*.dll\n*.so\n*.so.*\n*.dylib\n\n# Executables\n*.exe\n*.out\n*.app\n*.i*86\n*.x86_64\n*.hex\n*.dis\n*.0\n*.img\n\nMakefile.user\n"
  },
  {
    "path": "LICENSE",
    "content": "Copyright (c) 2020-2026 DiscoBSD\nCopyright (c) 2014, RetroBSD\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n* Redistributions of source code must retain the above copyright notice, this\n  list of conditions and the following disclaimer.\n\n* Redistributions in binary form must reproduce the above copyright notice,\n  this list of conditions and the following disclaimer in the documentation\n  and/or other materials provided with the distribution.\n\n* Neither the name of the {organization} nor the names of its\n  contributors may be used to endorse or promote products derived from\n  this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\nFOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\nDAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\nSERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\nCAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\nOR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\nOF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n"
  },
  {
    "path": "Makefile",
    "content": "# Copyright (c) 1986 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n# This makefile is designed to be run as:\n#\tmake\n#\n# The `make' will compile everything, including a kernel, utilities\n# and a root filesystem image.\n\nTOPSRC!=\tpwd\n\n# Override the default port with:\n# $ make MACHINE=pic32 MACHINE_ARCH=mips\n#\nMACHINE=\tstm32\nMACHINE_ARCH=\tarm\n\nDESTDIR?=\t${TOPSRC}/distrib/obj/destdir.${MACHINE}\nRELEASEDIR?=\t${TOPSRC}/distrib/obj/releasedir\n\n# Filesystem and swap sizes.\nFS_MBYTES       = 200\nU_MBYTES        = 200\nSWAP_MBYTES     = 2\n\n# SD card filesystem image for ${MACHINE}.\nFSIMG=\t\t${TOPSRC}/distrib/${MACHINE}/sdcard.img\n\n# Set this to the device name for your SD card.  With this\n# enabled you can use \"make installfs\" to copy the sdcard.img\n# to the SD card.\n\n#SDCARD          = /dev/sdb\n\n#\n# C library options: passed to libc makefile.\n# See lib/libc/Makefile for explanation.\n#\nDEFS\t\t=\n\nFSUTIL=\t\t${TOPSRC}/tools/bin/fsutil\n\n-include Makefile.user\n\nSUBDIR=\t\tshare lib bin sbin libexec usr.bin usr.sbin games\n\nall:\t\tbuild\n\nbuild:\t\tsymlinks tools\n\t\t$(MAKE) kernel\n\t\t$(MAKE) -C etc DESTDIR=${DESTDIR} distrib-dirs\n\t\t$(MAKE) -C include includes\n\t\tfor dir in ${SUBDIR} ; do \\\n\t\t\t${MAKE} -C $$dir ; done\n\t\tfor dir in ${SUBDIR} ; do \\\n\t\t\t${MAKE} -C $$dir DESTDIR=${DESTDIR} install ; done\n\ndistribution:\tbuild\n\t\t${MAKE} -C etc DESTDIR=${DESTDIR} distribution\n\t\t$(MAKE) fs\n\ntools:\n\t\t${MAKE} -C tools MACHINE=${MACHINE} install\n\nkernel:\t\ttools\n\t\t${MAKE} -C sys/arch/${MACHINE}/compile all\n\nfs:\t\t$(FSIMG)\n\n${FSIMG}:\tdistrib/${MACHINE}/md.${MACHINE} distrib/base/mi.home\n\t\trm -f $@ distrib/$(MACHINE)/_manifest\n\t\tcat distrib/base/mi distrib/$(MACHINE)/md.$(MACHINE) > distrib/$(MACHINE)/_manifest\n\t\t$(FSUTIL) --repartition=fs=$(FS_MBYTES)M:swap=$(SWAP_MBYTES)M:fs=$(U_MBYTES)M $@\n\t\t${FSUTIL} --new --partition=1 --manifest=distrib/${MACHINE}/_manifest $@ ${DESTDIR}\n# In case you need a separate /home partition,\n# uncomment the following line.\n\t\t$(FSUTIL) --new --partition=3 --manifest=distrib/base/mi.home $@ distrib/home\n\nrelease:\n\t\t${MAKE} -C etc MACHINE=${MACHINE} RELEASEDIR=${RELEASEDIR} release\n\nclean:\n\t\trm -f *~\n\t\trm -f include/machine\n\t\tfor dir in ${SUBDIR} ; do \\\n\t\t\t$(MAKE) -C $$dir -k clean; done\n\ncleantools:\n\t\t${MAKE} -C tools clean\n\ncleankernel:\n\t\t${MAKE} -C sys/arch/${MACHINE}/compile -k clean\n\ncleanfs:\n\t\trm -f distrib/$(MACHINE)/_manifest\n\t\trm -f $(FSIMG)\n\ncleanall:\tcleantools clean cleankernel\n\nsymlinks:\n\t\trm -f include/machine\n\t\tln -s $(MACHINE) include/machine\n\ninstallfs:\n\t\t@[ -n \"${SDCARD}\" ] || (echo \"SDCARD not defined.\" && exit 1)\n\t\t@[ -f $(FSIMG) ] || $(MAKE) $(FSIMG)\n\t\tsudo dd bs=1M if=${FSIMG} of=${SDCARD}\n\n.PHONY:\t\tall build distribution release tools kernel symlinks \\\n\t\t${FSIMG} fs installfs \\\n\t\tclean cleantools cleanfs cleanall\n\n# Architecture-specific debugging and loading.\n-include sys/arch/${MACHINE}/conf/Makefile.inc\n"
  },
  {
    "path": "README.md",
    "content": "DiscoBSD\n========\n\n2.11BSD-based UNIX-like Operating System for STM32 and PIC32 Microcontrollers\n-----------------------------------------------------------------------------\n\nDiscoBSD is a 2.11BSD-based UNIX-like operating system for microcontrollers,\nwith a focus on high portability to memory constrained devices without a\nmemory management unit.\n\nThe current and seventh official release of DiscoBSD is [DiscoBSD 2.6][1],\nreleased on February 11, 2026.\n\nThis microcontroller-focused operating system is an independent continuation\nof RetroBSD, a 2.11BSD-based OS targeting the MIPS-based PIC32MX7.\nDiscoBSD is multi-platform, as it also supports Arm Cortex-M4 STM32F4 devices.\n\nSource code to the system is freely available under a BSD-like license.\n\nHistory\n-------\n\n[DiscoBSD][2] began as an undergraduate [Directed Study][3] in the winter of\n2020 at the University of Victoria, Canada, as a case study of [RetroBSD][4]\nto port the operating system to the Arm Cortex-M4 architecture, and to enable\nportability in the hosting environment and target architectures and platforms.\nThe paper [*Porting the Unix Kernel*][5] details this initial porting effort.\n\nWork on DiscoBSD has progressed in earnest since the completion of the\nDirected Study, with the `DiscoBSD/stm32` port booting multi-user in\nAugust 2022. The system is quite usable on supported development boards.\n\nAnd work continues...\n\n[1]: https://github.com/chettrick/discobsd/releases/tag/DISCOBSD_2_6\n[2]: http://DiscoBSD.org\n[3]: https://github.com/chettrick/CSC490\n[4]: https://RetroBSD.org\n[5]: https://github.com/chettrick/CSC490/raw/master/project_outputs/Porting_the_Unix_Kernel-CSC490-Christopher_Hettrick.pdf\n\nDiscoBSD Resource Requirements\n------------------------------\n\nA basic, minimal system uses 128 Kbytes of flash and 128 Kbytes of RAM.\n\nThe kernel is loaded into the flash and only uses 32 Kbytes of RAM.\nUser programs each use the remaining 96 Kbytes of RAM, via swapping.\nDevices with more RAM can be used to run larger user programs.\n\nAn SD card, at least 512 Mbytes in size, is required for the root file system.\n\nInstalling and Running\n----------------------\n\nInstallation consists of loading the kernel into the microcontroller's flash\nmemory, and imaging the SD card with the file `sdcard.img`.\n\nOn Windows host systems use a disk imaging utility such as [Rufus][6].\n\nOn Unix-like host systems with `dd` run:\n\n    $ dd bs=1M if=sdcard.img of=/path/to/SD/card\n\nThe board-specific kernel `unix` must be loaded into the MCU's flash memory.\nFormats are ELF `unix.elf`, binary `unix.bin`, and Intel HEX `unix.hex`.\n\n#### Loading a `DiscoBSD/stm32` kernel firmware into board's flash memory:\n\nOn Windows host systems use [STM32CubeProgrammer][7] for flash programming.\n\nOn Unix-like host systems use `st-flash` from the [stlink-org project][8] to\nload the binary-formatted kernel `unix.bin` into flash memory at 0x08000000.\n\n    $ st-flash --reset write unix.bin 0x08000000\n\n#### Loading a `DiscoBSD/pic32` kernel firmware into board's flash memory:\n\nOn all supported host systems use [pic32prog][9] for flash programming.\n\n    $ pic32prog unix.hex\n\nCommunication with the DiscoBSD console requires a serial port. A USB to TTL\ndevice or the built-in VCP USB serial port on development boards can be used.\n\n    $ cu -l /dev/cuaU0 -s 115200\n\nDepending on the host system, other serial port utilities such as `screen`,\n`minicom`, `putty`, or `teraterm` may be used.\n\nLog in to DiscoBSD with user `root` and a blank password.\nShutdown DiscoBSD with the `halt`, `shutdown`, or `reboot` commands.\n\nManual pages on DiscoBSD are available through the `man` command.\n\n[6]: https://github.com/pbatard/rufus\n[7]: https://www.st.com/en/development-tools/stm32cubeprog.html\n[8]: https://github.com/stlink-org/stlink\n[9]: https://github.com/majenkotech/pic32prog-autotools\n\nBuilding\n--------\n\nDiscoBSD is cross-built on UNIX-like host operating systems.\n\nCurrently supported host operating systems: OpenBSD, Linux, FreeBSD.\n\n### Instructions to configure a supported host development environment:\n* [OpenBSD][10]\n* [Debian-based Linux][27]\n\nThe build system fully supports both BSD make and GNU make.\n\nFrom the source tree root, run:\n\n    $ make build\n\nor just:\n\n    $ make\n\nwhich builds `sys/arch/stm32/compile/${BOARD}/unix` ELF-formatted kernels\nand builds and populates a whole file system userland in `DESTDIR`.\n\nRunning:\n\n    $ make distribution\n\nwill build everything from a `make build`, plus generate a file system\nimage in the file `distrib/stm32/sdcard.img` for imaging to an SD card.\n\n`DiscoBSD/stm32` is the default port, but `DiscoBSD/pic32` may be built via:\n\n    $ make clean\n    $ make MACHINE=pic32 MACHINE_ARCH=mips distribution\n\nto generate a file system image in the file `distrib/pic32/sdcard.img`\nfor imaging to an SD card, `sys/arch/pic32/compile/${BOARD}/unix`\nELF-formatted kernels, and `sys/arch/pic32/compile/${BOARD}/unix.hex`\nIntel HEX-formatted kernels.\n\nPut the generated file system image `sdcard.img` onto an SD card.\n\nThe `make` target `installfs` uses the `dd` utility to image `sdcard.img`\nto the SD card attached to the host operating system at `SDCARD`, such as\n`/dev/rsdXc`, `/dev/daX`, `/dev/mmcblkX`, `/dev/sdX`, or `/dev/rdiskX`,\nreplacing `X` with the actual drive number or letter, as the case may be.\n\nFor example, imaging an SD card attached at `sd2` on an OpenBSD host\noperating system through the raw i/o device:\n\n    $ make SDCARD=/dev/rsd2c installfs\n\nNote that using BSD make on a FreeBSD host requires the system makefile\ninclude directory to be specified on the command line or via the\n`MAKESYSPATH` environment variable. For example:\n\n    $ make -m /usr/share/mk\n\nor\n\n    $ MAKESYSPATH=/usr/share/mk\n    $ export MAKESYSPATH\n\n    $ make\n\n[10]: tools/openbsd/README.md\n[27]: tools/linux/README.md\n\nBuilding a DiscoBSD Release\n---------------------------\n\nA DiscoBSD release consists of, for each supported architecture:\n\n* a file system image that contains the full base system\n* kernels, in various file formats, for each supported development board\n* the ANNOUNCEMENT.md file\n* the README.md file for the architecture\n* this README.md file\n\nBefore making a release, first create a distribution in `DESTDIR`\nwith kernels in `sys/arch/${MACHINE}/compile/${BOARD}` by following\nthe steps in [Building](#building):\n\n    $ make distribution\n\nOnce all the distribution source objects exist then a release can\nbe created; one release for each architecture.\n\nA `DiscoBSD/stm32` release, as the default architecture, is created by:\n\n    $ make release\n\nA `DiscoBSD/pic32` release is created by:\n\n    $ make MACHINE=pic32 MACHINE_ARCH=mips release\n\nA DiscoBSD release is created from an already-populated `DESTDIR`,\nand it is placed in `RELEASEDIR`, `distrib/obj/releasedir` by default.\n\n[Releases are available][11], for each architecture, as a `.tar.gz`\ngzip-compressed tar archive and as a `.zip` zip-compressed archive.\n\n[11]: https://github.com/chettrick/discobsd/releases\n\nDebugging\n---------\n\n`DiscoBSD/stm32` is debugged through OpenOCD and GDB. The `make` targets for\ndebugging are `ocd` and `gdb-ocd`.\n\nDebug a particular development board via:\n\n    $ make BOARD=F412GDISCO ocd\n\nin one terminal, and:\n\n    $ make BOARD=F412GDISCO gdb-ocd\n\nin another terminal.\n\nAdditional Information\n----------------------\n\nPort-specific information can be found in `distrib/${MACHINE}/README.md`\nfor [DiscoBSD/stm32][12] and [DiscoBSD/pic32][13].\n\n[12]: distrib/stm32/README.md\n[13]: distrib/pic32/README.md\n\nReferences and Resources\n------------------------\n\n* The [RetroBSD wiki][14] has a wealth of PIC32 architecture information.\n* [The Design and Implementation of the 4.3BSD UNIX Operating System][15].\n* [Lions' Commentary on UNIX 6th Edition][16] and [recreations of it][17].\n* [Advanced Programming in the UNIX Environment][18] 1st Edition.\n* [The Design of the UNIX Operating System][19].\n* [OpenBSD's curated list of books][20] relevant to BSD Operating Systems.\n* The paper [*Porting the Unix Kernel*][5] details DiscoBSD's inception.\n* The Unix Heritage Society's [Unix Archive][21] and [Source Tree][22].\n* STMicroelectronics [Reference Manual][23] and [Programming Manual][24].\n* [The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors][25].\n* [ARMv7-M Architecture Reference Manual][26].\n\n[14]: https://github.com/RetroBSD/retrobsd/wiki\n[15]: https://archive.org/details/designimplementa0000unse\n[16]: https://www.peerllc.com/peer-to-peer-books/lions-commentary-on-unix/\n[17]: http://www.lemis.com/grog/Documentation/Lions/\n[18]: http://www.kohala.com/start/apue.html\n[19]: https://archive.org/details/DesignUNIXOperatingSystem\n[20]: https://www.openbsd.org/books.html\n[21]: https://www.tuhs.org/Archive/Distributions/UCB/\n[22]: https://www.tuhs.org/cgi-bin/utree.pl\n[23]: https://www.st.com/resource/en/reference_manual/dm00031020-stm32f405-415-stm32f407-417-stm32f427-437-and-stm32f429-439-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf\n[24]: https://www.st.com/resource/en/programming_manual/pm0214-stm32-cortexm4-mcus-and-mpus-programming-manual-stmicroelectronics.pdf\n[25]: https://booksite.elsevier.com/9780124080829/\n[26]: https://developer.arm.com/documentation/ddi0403\n\nSource Tree Roadmap\n-------------------\n\n    bin         User utilities in both single and multi-user environments.\n    distrib     System distributions and releases.\n    etc         Templates for system configuration files and scripts in /etc.\n    games       Useful and semi-frivolous programs. The important stuff.\n    include     Standard C include files.\n    lib         System libraries.\n    libexec     System daemons and utilities (executed by other programs).\n    sbin        System administration utilities in both single and\n                multi-user environments.\n    share       Architecture-independent shared resource data files.\n    sys         Kernel sources.\n    tools       Build tools and simulators.\n    usr.bin     User utilities in multi-user environments.\n    usr.sbin    System administration utilities in multi-user environments.\n\n`DiscoBSD/stm32` dmesg\n--------------------\n\n```\nDiscoBSD 2.6 (F412GDISCO) #1 755: Wed Feb 11 11:11:11 MST 2026\n     chris@stm32.discobsd.org:/sys/arch/stm32/compile/F412GDISCO\ncpu: STM32F412xE/G rev 1/C, 100 MHz, bus 50 MHz\noscillator: phase-locked loop, clock source: high speed external\nuart2: pins tx=PA2/rx=PA3, af=7, console\nsd0: port sdio0\nsd0: type SDHC, size 31178752 kbytes\nsd0a: partition type b7, sector 2, size 204800 kbytes\nsd0b: partition type b8, sector 409602, size 2048 kbytes\nsd0c: partition type b7, sector 413698, size 204800 kbytes\nphys mem  = 256 kbytes\nuser mem  = 96 kbytes\nroot dev  = (0,1)\nswap dev  = (0,2)\nroot size = 204800 kbytes\nswap size = 2048 kbytes\nAutomatic boot in progress: starting file system checks.\n/dev/sd0a: 1475 files, 12210 used, 191789 free\n/dev/sd0c: 3 files, 3 used, 203996 free\nUpdating motd... done\nStarting daemons: update cron \nWed Feb 11 11:11:11 MST 2026\n\n\n2.11 BSD UNIX (name.my.domain) (console)\n\nlogin: root\nPassword:\nDiscoBSD 2.6 (F412GDISCO) #1 755: Wed Feb 11 11:11:11 MST 2026\n\nWelcome to DiscoBSD.\n\nerase ^?, kill ^U, intr ^C\n# \n```\n\n`DiscoBSD/pic32` dmesg\n--------------------\n\n```\nDiscoBSD 2.6 (MAX32) #1 755: Wed Feb 11 11:11:11 MST 2026\n     chris@pic32.discobsd.org:/sys/arch/pic32/compile/MAX32\ncpu: 795F512L 80 MHz, bus 80 MHz\noscillator: HS crystal, PLL div 1:2 mult x20\nspi2: pins sdi=RG7/sdo=RG8/sck=RG6\nuart1: pins rx=RF2/tx=RF8, interrupts 26/27/28, console\nuart2: pins rx=RF4/tx=RF5, interrupts 40/41/42\nuart4: pins rx=RD14/tx=RD15, interrupts 67/68/69\nsd0: port spi2, pin cs=RC14\ngpio0: portA, pins ii---ii-iiiioiii\ngpio1: portB, pins iiiiiiiiiiiiiiii\ngpio2: portC, pins i-ii-------iiii-\ngpio3: portD, pins --iiiiiiiiiiiiii\ngpio4: portE, pins ------iiiiiiiiii\ngpio5: portF, pins --ii--------i-ii\ngpio6: portG, pins iiii--i-----iiii\nadc: 15 channels\npwm: 5 channels\nsd0: type I, size 524288 kbytes, speed 10 Mbit/sec\nsd0a: partition type b7, sector 2, size 204800 kbytes\nsd0b: partition type b8, sector 409602, size 2048 kbytes\nsd0c: partition type b7, sector 413698, size 204800 kbytes\nphys mem  = 128 kbytes\nuser mem  = 96 kbytes\nroot dev  = (0,1)\nswap dev  = (0,2)\nroot size = 204800 kbytes\nswap size = 2048 kbytes\nAutomatic boot in progress: starting file system checks.\n/dev/sd0a: 1468 files, 13581 used, 190418 free\n/dev/sd0c: 3 files, 3 used, 203996 free\nUpdating motd... done\nStarting daemons: update cron \nWed Feb 11 11:11:11 MST 2026\n\n\n2.11 BSD UNIX (name.my.domain) (console)\n\nlogin: root\nPassword:\nDiscoBSD 2.6 (MAX32) #1 755: Wed Feb 11 11:11:11 MST 2026\n\nWelcome to DiscoBSD.\n\nerase ^?, kill ^U, intr ^C\n# \n```\n"
  },
  {
    "path": "bin/Makefile",
    "content": "#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\nTOPSRC!=cd ..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nSUBDIR=\t\tdate2 hostname ls md5 sh stty test \\\n\t\tcat chgrp chmod cp dd df echo ed expr kill ln mkdir mv ps \\\n\t\tpwd rm rmail rmdir sleep sync tar\n\n# TODO: csh\n\nall:\t\t${SUBDIR}\n\n${SUBDIR}:\tFRC\n\t\t${MAKE} -C $@ ${MFLAGS}\n\nFRC:\n\ninstall:\n\t\t-for i in ${SUBDIR}; do \\\n\t\t\t${MAKE} -C $$i ${MFLAGS} DESTDIR=${DESTDIR} install; done\n\nclean:\n\t\t/bin/rm -f a.out core *.s *.o *.dis *.elf *~ y.tab.[ch] errs\n\t\tfor i in ${SUBDIR}; do (cd $$i; ${MAKE} ${MFLAGS} clean); done\n"
  },
  {
    "path": "bin/csh/Makefile",
    "content": "#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley Software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n# C Shell with process control; VM/UNIX VAX Makefile\n# Bill Joy UC Berkeley; Jim Kulp IIASA, Austria\n#\n# To profile, put -DPROF in DEFS and -pg in CFLAGS, and recompile.\n#\nTOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS          += -DTELL -DVFORK -DFILEC -DNOLIMITS -Os\n\nOBJS            = alloc.o printf.o sh.char.o sh.dir.o sh.dol.o \\\n                  sh.err.o sh.exp.o sh.file.o sh.func.o sh.glob.o sh.hist.o \\\n                  sh.init.o sh.lex.o sh.misc.o sh.parse.o sh.print.o sh.proc.o sh.sem.o \\\n                  sh.set.o sh.o sh.exec.o sh.time.o sh.exec2.o\n\nall:\t\tcsh\n\ncsh:\t\t${OBJS}\n\t\t${CC} ${CFLAGS} ${LDFLAGS} -o csh.elf ${OBJS} ${LIBS}\n\t\t${OBJDUMP} -S csh.elf > csh.dis\n\t\t${SIZE} csh.elf\n\t\t${ELF2AOUT} csh.elf $@ && rm csh.elf\n\ninstall:\tall\n\t\t${INSTALL} csh ${DESTDIR}/bin/\nclean:\n\t\trm -f csh *.o *~ *.elf *.dis\n\nsh.o: sh.h sh.local.h sh.char.h\nsh.char.o: sh.char.h\nsh.dir.o: sh.h sh.local.h sh.dir.h\nsh.dol.o: sh.h sh.local.h sh.char.h\nsh.err.o: sh.h sh.local.h sh.char.h\nsh.exec.o: sh.h sh.local.h sh.char.h\nsh.exec2.o: sh.h sh.local.h sh.char.h\nsh.exp.o: sh.h sh.local.h sh.char.h\nsh.file.o: sh.h sh.local.h sh.char.h\nsh.func.o: sh.h sh.local.h sh.char.h\nsh.glob.o: sh.h sh.local.h sh.char.h\nsh.hist.o: sh.h sh.local.h sh.char.h\nsh.init.o: sh.local.h\nsh.lex.o: sh.h sh.local.h sh.char.h\nsh.misc.o: sh.h sh.local.h sh.char.h\nsh.parse.o: sh.h sh.local.h sh.char.h\nsh.print.o: sh.h sh.local.h sh.char.h\nsh.proc.o: sh.h sh.local.h sh.dir.h sh.proc.h sh.char.h\nsh.sem.o: sh.h sh.local.h sh.proc.h sh.char.h\nsh.set.o: sh.h sh.local.h sh.char.h\nsh.time.o: sh.h sh.local.h sh.char.h\n"
  },
  {
    "path": "bin/csh/alloc.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * malloc.c (Caltech) 2/21/82\n * Chris Kingsley, kingsley@cit-20.\n *\n * This is a very fast storage allocator.  It allocates blocks of a small\n * number of different sizes, and keeps free lists of each size.  Blocks that\n * don't exactly fit are passed up to the next larger size.  In this\n * implementation, the available sizes are 2^n-4 (or 2^n-10) bytes long.\n * This is designed for use in a virtual memory environment.\n */\n#include <sys/types.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <strings.h>\n\n#ifndef\tNULL\n#define\tNULL 0\n#endif\n\n/*\n * The overhead on a block is at least 4 bytes.  When free, this space\n * contains a pointer to the next free block, and the bottom two bits must\n * be zero.  When in use, the first byte is set to MAGIC, and the second\n * byte is the size index.  The remaining bytes are for alignment.\n * If range checking is enabled then a second word holds the size of the\n * requested block, less 1, rounded up to a multiple of sizeof(RMAGIC).\n * The order of elements is critical: ov_magic must overlay the low order\n * bits of ov_next, and ov_magic can not be a valid ov_next bit pattern.\n */\nunion\toverhead {\n\tunion\toverhead *ov_next;\t/* when free */\n\tstruct {\n\t\tu_char\tovu_magic;\t/* magic number */\n\t\tu_char\tovu_index;\t/* bucket # */\n#ifdef RCHECK\n\t\tu_short\tovu_rmagic;\t/* range magic number */\n\t\tu_int\tovu_size;\t/* actual block size */\n#endif\n\t} ovu;\n#define\tov_magic\tovu.ovu_magic\n#define\tov_index\tovu.ovu_index\n#define\tov_rmagic\tovu.ovu_rmagic\n#define\tov_size\t\tovu.ovu_size\n};\n\n#define\tMAGIC\t\t0xef\t\t/* magic # on accounting info */\n#define RMAGIC\t\t0x5555\t\t/* magic # on range info */\n\n#ifdef RCHECK\n#define\tRSLOP\t\tsizeof (u_short)\n#else\n#define\tRSLOP\t\t0\n#endif\n\n/*\n * nextf[i] is the pointer to the next free block of size 2^(i+3).  The\n * smallest allocatable block is 8 bytes.  The overhead information\n * precedes the data area returned to the user.\n */\n#define\tNBUCKETS 30\nstatic\tunion overhead *nextf[NBUCKETS];\nextern\tchar *sbrk();\n\nstatic\tint pagesz;\t\t\t/* page size */\nstatic\tint pagebucket;\t\t\t/* page size bucket */\n\n/*\n * nmalloc[i] is the difference between the number of mallocs and frees\n * for a given block size.\n */\nstatic\tu_int nmalloc[NBUCKETS];\n\n#if defined(DEBUG) || defined(RCHECK)\n#define\tASSERT(p)   if (!(p)) botch(\"p\")\nstatic\nbotch(s)\n\tchar *s;\n{\n\tprintf(\"\\r\\nassertion botched: %s\\r\\n\", s);\n\tabort();\n}\n#else\n#define\tASSERT(p)\n#endif\n\nvoid *\nmalloc(nbytes)\n\tsize_t nbytes;\n{\n  \tregister union overhead *op;\n  \tregister int bucket;\n\tregister unsigned amt, n;\n\n\t/*\n\t * First time malloc is called, setup page size and\n\t * align break pointer so all data will be page aligned.\n\t */\n\tif (pagesz == 0) {\n\t\tpagesz = n = getpagesize();\n\t\top = (union overhead *)sbrk(0);\n  \t\tn = n - sizeof (*op) - ((int)op & (n - 1));\n\t\tif (n < 0)\n\t\t\tn += pagesz;\n  \t\tif (n) {\n  \t\t\tif (sbrk(n) == (char *)-1)\n\t\t\t\treturn (NULL);\n\t\t}\n\t\tbucket = 0;\n\t\tamt = 8;\n\t\twhile (pagesz > amt) {\n\t\t\tamt <<= 1;\n\t\t\tbucket++;\n\t\t}\n\t\tpagebucket = bucket;\n\t}\n\t/*\n\t * Convert amount of memory requested into closest block size\n\t * stored in hash buckets which satisfies request.\n\t * Account for space used per block for accounting.\n\t */\n\tif (nbytes <= (n = pagesz - sizeof (*op) - RSLOP)) {\n#ifndef RCHECK\n\t\tamt = 8;\t/* size of first bucket */\n\t\tbucket = 0;\n#else\n\t\tamt = 16;\t/* size of first bucket */\n\t\tbucket = 1;\n#endif\n\t\tn = -(sizeof (*op) + RSLOP);\n\t} else {\n\t\tamt = pagesz;\n\t\tbucket = pagebucket;\n\t}\n\twhile (nbytes > amt + n) {\n\t\tamt <<= 1;\n\t\tif (amt == 0)\n\t\t\treturn (NULL);\n\t\tbucket++;\n\t}\n\t/*\n\t * If nothing in hash bucket right now,\n\t * request more memory from the system.\n\t */\n  \tif ((op = nextf[bucket]) == NULL) {\n  \t\tmorecore(bucket);\n  \t\tif ((op = nextf[bucket]) == NULL)\n  \t\t\treturn (NULL);\n\t}\n\t/* remove from linked list */\n  \tnextf[bucket] = op->ov_next;\n\top->ov_magic = MAGIC;\n\top->ov_index = bucket;\n  \tnmalloc[bucket]++;\n#ifdef RCHECK\n\t/*\n\t * Record allocated size of block and\n\t * bound space with magic numbers.\n\t */\n\top->ov_size = (nbytes + RSLOP - 1) & ~(RSLOP - 1);\n\top->ov_rmagic = RMAGIC;\n  \t*(u_short *)((caddr_t)(op + 1) + op->ov_size) = RMAGIC;\n#endif\n  \treturn ((char *)(op + 1));\n}\n\n/*\n * Allocate more memory to the indicated bucket.\n */\nmorecore(bucket)\n\tint bucket;\n{\n  \tregister union overhead *op;\n\tregister int sz;\t\t/* size of desired block */\n  \tint amt;\t\t\t/* amount to allocate */\n  \tint nblks;\t\t\t/* how many blocks we get */\n\n\t/*\n\t * sbrk_size <= 0 only for big, FLUFFY, requests (about\n\t * 2^30 bytes on a VAX, I think) or for a negative arg.\n\t */\n\tsz = 1 << (bucket + 3);\n#ifdef DEBUG\n\tASSERT(sz > 0);\n#else\n\tif (sz <= 0)\n\t\treturn;\n#endif\n\tif (sz < pagesz) {\n\t\tamt = pagesz;\n  \t\tnblks = amt / sz;\n\t} else {\n\t\tamt = sz + pagesz;\n\t\tnblks = 1;\n\t}\n\top = (union overhead *)sbrk(amt);\n\t/* no more room! */\n  \tif ((int)op == -1)\n  \t\treturn;\n\t/*\n\t * Add new memory allocated to that on\n\t * free list for this hash bucket.\n\t */\n  \tnextf[bucket] = op;\n  \twhile (--nblks > 0) {\n\t\top->ov_next = (union overhead *)((caddr_t)op + sz);\n\t\top = (union overhead *)((caddr_t)op + sz);\n  \t}\n}\n\nvoid free(cp)\n\tvoid *cp;\n{\n  \tregister int size;\n\tregister union overhead *op;\n\n  \tif (cp == NULL)\n  \t\treturn;\n\top = (union overhead *)((caddr_t)cp - sizeof (union overhead));\n\t/*\n\t * The following botch is because csh tries to free a free block\n\t * when processing the =~ or !~ operators. -- layer@ucbmonet\n\t*/\n#ifdef CSHbotch /* was DEBUG */\n  \tASSERT(op->ov_magic == MAGIC);\t\t/* make sure it was in use */\n#else\n\tif (op->ov_magic != MAGIC)\n\t\treturn;\t\t\t\t/* sanity */\n#endif\n#ifdef RCHECK\n  \tASSERT(op->ov_rmagic == RMAGIC);\n\tASSERT(*(u_short *)((caddr_t)(op + 1) + op->ov_size) == RMAGIC);\n#endif\n  \tsize = op->ov_index;\n  \tASSERT(size < NBUCKETS);\n\top->ov_next = nextf[size];\t/* also clobbers ov_magic */\n  \tnextf[size] = op;\n  \tnmalloc[size]--;\n}\n\n/*\n * Search ``srchlen'' elements of each free list for a block whose\n * header starts at ``freep''.  If srchlen is -1 search the whole list.\n * Return bucket number, or -1 if not found.\n */\nstatic\nfindbucket(freep, srchlen)\n\tunion overhead *freep;\n\tint srchlen;\n{\n\tregister union overhead *p;\n\tregister int i, j;\n\n\tfor (i = 0; i < NBUCKETS; i++) {\n\t\tj = 0;\n\t\tfor (p = nextf[i]; p && j != srchlen; p = p->ov_next) {\n\t\t\tif (p == freep)\n\t\t\t\treturn (i);\n\t\t\tj++;\n\t\t}\n\t}\n\treturn (-1);\n}\n\n/*\n * When a program attempts \"storage compaction\" as mentioned in the\n * old malloc man page, it realloc's an already freed block.  Usually\n * this is the last block it freed; occasionally it might be farther\n * back.  We have to search all the free lists for the block in order\n * to determine its bucket: 1st we make one pass thru the lists\n * checking only the first block in each; if that fails we search\n * ``realloc_srchlen'' blocks in each list for a match (the variable\n * is extern so the caller can modify it).  If that fails we just copy\n * however many bytes was given to realloc() and hope it's not huge.\n */\nint realloc_srchlen = 4;\t/* 4 should be plenty, -1 =>'s whole list */\n\nvoid *\nrealloc(cp, nbytes)\n\tvoid *cp;\n\tsize_t nbytes;\n{\n  \tregister u_int onb, i;\n\tunion overhead *op;\n  \tchar *res;\n\tint was_alloced = 0;\n\n  \tif (cp == NULL)\n  \t\treturn (malloc(nbytes));\n\top = (union overhead *)((caddr_t)cp - sizeof (union overhead));\n\tif (op->ov_magic == MAGIC) {\n\t\twas_alloced++;\n\t\ti = op->ov_index;\n\t} else {\n\t\t/*\n\t\t * Already free, doing \"compaction\".\n\t\t *\n\t\t * Search for the old block of memory on the\n\t\t * free list.  First, check the most common\n\t\t * case (last element free'd), then (this failing)\n\t\t * the last ``realloc_srchlen'' items free'd.\n\t\t * If all lookups fail, then assume the size of\n\t\t * the memory block being realloc'd is the\n\t\t * largest possible (so that all \"nbytes\" of new\n\t\t * memory are copied into).  Note that this could cause\n\t\t * a memory fault if the old area was tiny, and the moon\n\t\t * is gibbous.  However, that is very unlikely.\n\t\t */\n\t\tif ((i = findbucket(op, 1)) < 0 &&\n\t\t    (i = findbucket(op, realloc_srchlen)) < 0)\n\t\t\ti = NBUCKETS;\n\t}\n\tonb = 1 << (i + 3);\n\tif (onb < pagesz)\n\t\tonb -= sizeof (*op) + RSLOP;\n\telse\n\t\tonb += pagesz - sizeof (*op) - RSLOP;\n\t/* avoid the copy if same size block */\n\tif (was_alloced) {\n\t\tif (i) {\n\t\t\ti = 1 << (i + 2);\n\t\t\tif (i < pagesz)\n\t\t\t\ti -= sizeof (*op) + RSLOP;\n\t\t\telse\n\t\t\t\ti += pagesz - sizeof (*op) - RSLOP;\n\t\t}\n\t\tif (nbytes <= onb && nbytes > i) {\n#ifdef RCHECK\n\t\t\top->ov_size = (nbytes + RSLOP - 1) & ~(RSLOP - 1);\n\t\t\t*(u_short *)((caddr_t)(op + 1) + op->ov_size) = RMAGIC;\n#endif\n\t\t\treturn(cp);\n\t\t} else\n\t\t\tfree(cp);\n\t}\n  \tif ((res = malloc(nbytes)) == NULL)\n  \t\treturn (NULL);\n  \tif (cp != res)\t\t/* common optimization if \"compacting\" */\n\t\tbcopy(cp, res, (nbytes < onb) ? nbytes : onb);\n  \treturn (res);\n}\n\n/*\n * mstats - print out statistics about malloc\n *\n * Prints two lines of numbers, one showing the length of the free list\n * for each size category, the second showing the number of mallocs -\n * frees for each size category.\n */\nshowall(s)\nchar **s;\n{\n\tregister int i, j;\n\tregister union overhead *p;\n\tint totfree = 0,\n\ttotused = 0;\n\n\tif (s[1])\n\t\tprintf(\"Memory allocation statistics %s\\nfree:\", s[1]);\n\tfor (i = 0; i < NBUCKETS; i++) {\n\t\tfor (j = 0, p = nextf[i]; p; p = p->ov_next, j++)\n\t\t\t;\n\t\tif (s[1])\n\t\t\tprintf(\" %d\", j);\n\t\ttotfree += j * (1 << (i + 3));\n\t}\n\tif (s[1])\n\t\tprintf(\"\\nused:\");\n\tfor (i = 0; i < NBUCKETS; i++) {\n\t\tif (s[1])\n\t\t\tprintf(\" %d\", nmalloc[i]);\n\t\ttotused += nmalloc[i] * (1 << (i + 3));\n\t}\n\tif (s[1])\n\t\tprintf(\"\\n\");\n\tprintf(\"Total in use: %d, total free: %d\\n\", totused, totfree);\n}\n"
  },
  {
    "path": "bin/csh/printf.c",
    "content": "/*\n * Scaled down version of printf(3).\n * Based on FreeBSD sources, heavily rewritten.\n *\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdarg.h>\n#include <unistd.h>\n\n/* Max number conversion buffer length: a long in base 2, plus NUL byte. */\n#define MAXNBUF\t(sizeof(long) * 8 + 1)\n\nstatic unsigned char *ksprintn (unsigned char *buf, unsigned long v, unsigned char base,\n\tint width, unsigned char *lp);\nstatic unsigned char mkhex (unsigned char ch);\n\nint\nshprintf (char const *fmt, ...)\n{\n#define PUTC(c) { putchr (c); ++retval; }\n\tunsigned char nbuf [MAXNBUF], padding, *q;\n\tconst unsigned char *s;\n\tunsigned char c, base, lflag, ladjust, sharpflag, neg, dot, size;\n\tint n, width, dwidth, retval, uppercase, extrazeros, sign;\n\tunsigned long ul;\n\tva_list ap;\n\n\tva_start (ap, fmt);\n\tif (! fmt)\n\t\tfmt = \"(null)\\n\";\n\n\tretval = 0;\n\tfor (;;) {\n\t\twhile ((c = *fmt++) != '%') {\n\t\t\tif (! c) {\n                                va_end (ap);\n\t\t\t\treturn retval;\n                        }\n\t\t\tPUTC (c);\n\t\t}\n\t\tpadding = ' ';\n\t\twidth = 0; extrazeros = 0;\n\t\tlflag = 0; ladjust = 0; sharpflag = 0; neg = 0;\n\t\tsign = 0; dot = 0; uppercase = 0; dwidth = -1;\nreswitch:\tswitch (c = *fmt++) {\n\t\tcase '.':\n\t\t\tdot = 1;\n\t\t\tpadding = ' ';\n\t\t\tdwidth = 0;\n\t\t\tgoto reswitch;\n\n\t\tcase '#':\n\t\t\tsharpflag = 1;\n\t\t\tgoto reswitch;\n\n\t\tcase '+':\n\t\t\tsign = -1;\n\t\t\tgoto reswitch;\n\n\t\tcase '-':\n\t\t\tladjust = 1;\n\t\t\tgoto reswitch;\n\n\t\tcase '%':\n\t\t\tPUTC (c);\n\t\t\tbreak;\n\n\t\tcase '*':\n\t\t\tif (! dot) {\n\t\t\t\twidth = va_arg (ap, int);\n\t\t\t\tif (width < 0) {\n\t\t\t\t\tladjust = !ladjust;\n\t\t\t\t\twidth = -width;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tdwidth = va_arg (ap, int);\n\t\t\t}\n\t\t\tgoto reswitch;\n\n\t\tcase '0':\n\t\t\tif (! dot) {\n\t\t\t\tpadding = '0';\n\t\t\t\tgoto reswitch;\n\t\t\t}\n\t\tcase '1': case '2': case '3': case '4':\n\t\tcase '5': case '6': case '7': case '8': case '9':\n\t\t\tfor (n=0; ; ++fmt) {\n\t\t\t\tn = n * 10 + c - '0';\n\t\t\t\tc = *fmt;\n\t\t\t\tif (c < '0' || c > '9')\n\t\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (dot)\n\t\t\t\tdwidth = n;\n\t\t\telse\n\t\t\t\twidth = n;\n\t\t\tgoto reswitch;\n\n\t\tcase 'c':\n\t\t\tif (! ladjust && width > 0)\n\t\t\t\twhile (width--)\n\t\t\t\t\tPUTC (' ');\n\n\t\t\tPUTC (va_arg (ap, int));\n\n\t\t\tif (ladjust && width > 0)\n\t\t\t\twhile (width--)\n\t\t\t\t\tPUTC (' ');\n\t\t\tbreak;\n\n\t\tcase 'd':\n\t\t\tul = lflag ? va_arg (ap, long) : va_arg (ap, int);\n\t\t\tif (! sign) sign = 1;\n\t\t\tbase = 10;\n\t\t\tgoto number;\n\n\t\tcase 'l':\n\t\t\tlflag = 1;\n\t\t\tgoto reswitch;\n\n\t\tcase 'o':\n\t\t\tul = lflag ? va_arg (ap, unsigned long) :\n\t\t\t\tva_arg (ap, unsigned int);\n\t\t\tbase = 8;\n\t\t\tgoto nosign;\n\n\t\tcase 'p':\n\t\t\tul = (size_t) va_arg (ap, void*);\n\t\t\tif (! ul) {\n\t\t\t\ts = (const unsigned char*) \"(nil)\";\n\t\t\t\tgoto string;\n\t\t\t}\n\t\t\tbase = 16;\n\t\t\tsharpflag = (width == 0);\n\t\t\tgoto nosign;\n\n\t\tcase 'n':\n\t\t\tul = lflag ? va_arg (ap, unsigned long) :\n\t\t\t\tsign ? (unsigned long) va_arg (ap, int) :\n\t\t\t\tva_arg (ap, unsigned int);\n\t\t\tbase = 10;\n\t\t\tgoto number;\n\n\t\tcase 's':\n\t\t\ts = va_arg (ap, unsigned char*);\n\t\t\tif (! s)\n\t\t\t\ts = (const unsigned char*) \"(null)\";\nstring:\t\t\tif (! dot)\n\t\t\t\tn = strlen (s);\n\t\t\telse\n\t\t\t\tfor (n=0; n<dwidth && s[n]; n++)\n\t\t\t\t\tcontinue;\n\n\t\t\twidth -= n;\n\n\t\t\tif (! ladjust && width > 0)\n\t\t\t\twhile (width--)\n\t\t\t\t\tPUTC (' ');\n\t\t\twhile (n--)\n\t\t\t\tPUTC (*s++);\n\t\t\tif (ladjust && width > 0)\n\t\t\t\twhile (width--)\n\t\t\t\t\tPUTC (' ');\n\t\t\tbreak;\n\n\t\tcase 'u':\n\t\t\tul = lflag ? va_arg (ap, unsigned long) :\n\t\t\t\tva_arg (ap, unsigned int);\n\t\t\tbase = 10;\n\t\t\tgoto nosign;\n\n\t\tcase 'x':\n\t\tcase 'X':\n\t\t\tul = lflag ? va_arg (ap, unsigned long) :\n\t\t\t\tva_arg (ap, unsigned int);\n\t\t\tbase = 16;\n\t\t\tuppercase = (c == 'X');\n\t\t\tgoto nosign;\n\t\tcase 'z':\n\t\tcase 'Z':\n\t\t\tul = lflag ? va_arg (ap, unsigned long) :\n\t\t\t\tsign ? (unsigned long) va_arg (ap, int) :\n\t\t\t\tva_arg (ap, unsigned int);\n\t\t\tbase = 16;\n\t\t\tuppercase = (c == 'Z');\n\t\t\tgoto number;\n\nnosign:\t\t\tsign = 0;\nnumber:\t\tif (sign && ((long) ul != 0L)) {\n\t\t\t\tif ((long) ul < 0L) {\n\t\t\t\t\tneg = '-';\n\t\t\t\t\tul = -(long) ul;\n\t\t\t\t} else if (sign < 0)\n\t\t\t\t\tneg = '+';\n\t\t\t}\n\t\t\tif (dwidth >= (int) sizeof(nbuf)) {\n\t\t\t\textrazeros = dwidth - sizeof(nbuf) + 1;\n\t\t\t\tdwidth = sizeof(nbuf) - 1;\n\t\t\t}\n\t\t\ts = ksprintn (nbuf, ul, base, dwidth, &size);\n\t\t\tif (sharpflag && ul != 0) {\n\t\t\t\tif (base == 8)\n\t\t\t\t\tsize++;\n\t\t\t\telse if (base == 16)\n\t\t\t\t\tsize += 2;\n\t\t\t}\n\t\t\tif (neg)\n\t\t\t\tsize++;\n\n\t\t\tif (! ladjust && width && padding == ' ' &&\n\t\t\t    (width -= size) > 0)\n\t\t\t\tdo {\n\t\t\t\t\tPUTC (' ');\n\t\t\t\t} while (--width > 0);\n\n\t\t\tif (neg)\n\t\t\t\tPUTC (neg);\n\n\t\t\tif (sharpflag && ul != 0) {\n\t\t\t\tif (base == 8) {\n\t\t\t\t\tPUTC ('0');\n\t\t\t\t} else if (base == 16) {\n\t\t\t\t\tPUTC ('0');\n\t\t\t\t\tPUTC (uppercase ? 'X' : 'x');\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (extrazeros)\n\t\t\t\tdo {\n\t\t\t\t\tPUTC ('0');\n\t\t\t\t} while (--extrazeros > 0);\n\n\t\t\tif (! ladjust && width && (width -= size) > 0)\n\t\t\t\tdo {\n\t\t\t\t\tPUTC (padding);\n\t\t\t\t} while (--width > 0);\n\n\t\t\tfor (; *s; --s) {\n\t\t\t\tif (uppercase && *s>='a' && *s<='z') {\n\t\t\t\t\tPUTC (*s + 'A' - 'a');\n\t\t\t\t} else {\n\t\t\t\t\tPUTC (*s);\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (ladjust && width && (width -= size) > 0)\n\t\t\t\tdo {\n\t\t\t\t\tPUTC (' ');\n\t\t\t\t} while (--width > 0);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tPUTC ('%');\n\t\t\tif (lflag)\n\t\t\t\tPUTC ('l');\n\t\t\tPUTC (c);\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\n/*\n * Put a NUL-terminated ASCII number (base <= 16) in a buffer in reverse\n * order; return an optional length and a pointer to the last character\n * written in the buffer (i.e., the first character of the string).\n * The buffer pointed to by `nbuf' must have length >= MAXNBUF.\n */\nstatic unsigned char *\nksprintn (unsigned char *nbuf, unsigned long ul, unsigned char base, int width,\n\tunsigned char *lenp)\n{\n\tunsigned char *p;\n\n\tp = nbuf;\n\t*p = 0;\n\tfor (;;) {\n\t\t*++p = mkhex (ul % base);\n\t\tul /= base;\n\t\tif (--width > 0)\n\t\t\tcontinue;\n\t\tif (! ul)\n\t\t\tbreak;\n\t}\n\tif (lenp)\n\t\t*lenp = p - nbuf;\n\treturn (p);\n}\n\nstatic unsigned char\nmkhex (unsigned char ch)\n{\n\tch &= 15;\n\tif (ch > 9)\n\t\treturn ch + 'a' - 10;\n\treturn ch + '0';\n}\n"
  },
  {
    "path": "bin/csh/sh.c",
    "content": "/*\n * C Shell\n *\n * Bill Joy, UC Berkeley, California, USA\n * October 1978, May 1980\n *\n * Jim Kulp, IIASA, Laxenburg, Austria\n * April 1980\n *\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"sh.h\"\n#include <sys/ioctl.h>\n\nchar\t*pathlist[] =\t{ \"/bin\", 0 };\nchar\t*dumphist[] =\t{ \"history\", \"-h\", 0, 0 };\nchar\t*loadhist[] =\t{ \"source\", \"-h\", \"~/.history\", 0 };\nchar\tHIST = '!';\nchar\tHISTSUB = '^';\nbool\tnofile;\nbool\treenter;\nbool\tnverbose;\nbool\tnexececho;\nbool\tquitit;\nbool\tfast;\nbool\tbatch;\nbool\tprompt = 1;\nbool\tenterhist = 0;\n\nextern\tgid_t getegid(), getgid();\nextern\tuid_t geteuid(), getuid();\n\n/*\n * in the event of a HUP we want to save the history\n */\nvoid phup(int sig)\n{\n\trechist();\n\texit(1);\n}\n\n/*\n * Catch an interrupt, e.g. during lexical input.\n * If we are an interactive shell, we reset the interrupt catch\n * immediately.  In any case we drain the shell output,\n * and finally go through the normal error mechanism, which\n * gets a chance to make the shell go away.\n */\nvoid pintr(int sig)\n{\n\tpintr1(1);\n}\n\nint main(c, av)\n\tint c;\n\tchar **av;\n{\n\tregister char **v, *cp;\n\tregister int f;\n\tstruct sigvec osv;\n\n\tsettimes();\t\t\t/* Immed. estab. timing base */\n\tv = av;\n\tif (eq(v[0], \"a.out\"))\t\t/* A.out's are quittable */\n\t\tquitit = 1;\n\tuid = getuid();\n\tloginsh = **v == '-' && c == 1;\n\tif (loginsh)\n\t\t(void) time(&chktim);\n\n\t/*\n\t * Move the descriptors to safe places.\n\t * The variable didfds is 0 while we have only FSH* to work with.\n\t * When didfds is true, we have 0,1,2 and prefer to use these.\n\t */\n\tinitdesc();\n\n\t/*\n\t * Initialize the shell variables.\n\t * ARGV and PROMPT are initialized later.\n\t * STATUS is also munged in several places.\n\t * CHILD is munged when forking/waiting\n\t */\n\n\tset(\"status\", \"0\");\n\tdinit(cp = getenv(\"HOME\"));\t/* dinit thinks that HOME == cwd in a\n\t\t\t\t\t * login shell */\n\tif (cp == NOSTR)\n\t\tfast++;\t\t\t/* No home -> can't read scripts */\n\telse\n\t\tset(\"home\", savestr(cp));\n\t/*\n\t * Grab other useful things from the environment.\n\t * Should we grab everything??\n\t */\n\tif ((cp = getenv(\"USER\")) != NOSTR)\n\t\tset(\"user\", savestr(cp));\n\tif ((cp = getenv(\"TERM\")) != NOSTR)\n\t\tset(\"term\", savestr(cp));\n\t/*\n\t * Re-initialize path if set in environment\n\t */\n\tif ((cp = getenv(\"PATH\")) == NOSTR)\n\t\tset1(\"path\", saveblk(pathlist), &shvhed);\n\telse\n\t\timportpath(cp);\n\tset(\"shell\", SHELLPATH);\n\n\tdoldol = putn(getpid());\t\t/* For $$ */\n\tshtemp = strspl(\"/tmp/sh\", doldol);\t/* For << */\n\n\t/*\n\t * Record the interrupt states from the parent process.\n\t * If the parent is non-interruptible our hand must be forced\n\t * or we (and our children) won't be either.\n\t * Our children inherit termination from our parent.\n\t * We catch it only if we are the login shell.\n\t */\n\t\t/* parents interruptibility */\n\t(void) sigvec(SIGINT, (struct sigvec *)0, &osv);\n\tparintr = osv.sv_handler;\n\t\t/* parents terminability */\n\t(void) sigvec(SIGTERM, (struct sigvec *)0, &osv);\n\tparterm = osv.sv_handler;\n\tif (loginsh) {\n\t\t(void) signal(SIGHUP, phup);\t/* exit processing on HUP */\n\t\t(void) signal(SIGXCPU, phup);\t/* ...and on XCPU */\n\t\t(void) signal(SIGXFSZ, phup);\t/* ...and on XFSZ */\n\t}\n\n\t/*\n\t * Process the arguments.\n\t *\n\t * Note that processing of -v/-x is actually delayed till after\n\t * script processing.\n\t */\n\tc--, v++;\n\twhile (c > 0 && (cp = v[0])[0] == '-' && *++cp != '\\0' && !batch) {\n\t\tdo switch (*cp++) {\n\n\t\tcase 'b':\t\t/* -b\tNext arg is input file */\n\t\t\tbatch++;\n\t\t\tbreak;\n\n\t\tcase 'c':\t\t/* -c\tCommand input from arg */\n\t\t\tif (c == 1)\n\t\t\t\texit(0);\n\t\t\tc--, v++;\n\t\t\targinp = v[0];\n\t\t\tprompt = 0;\n\t\t\tnofile++;\n\t\t\tbreak;\n\n\t\tcase 'e':\t\t/* -e\tExit on any error */\n\t\t\texiterr++;\n\t\t\tbreak;\n\n\t\tcase 'f':\t\t/* -f\tFast start */\n\t\t\tfast++;\n\t\t\tbreak;\n\n\t\tcase 'i':\t\t/* -i\tInteractive, even if !intty */\n\t\t\tintact++;\n\t\t\tnofile++;\n\t\t\tbreak;\n\n\t\tcase 'n':\t\t/* -n\tDon't execute */\n\t\t\tnoexec++;\n\t\t\tbreak;\n\n\t\tcase 'q':\t\t/* -q\t(Undoc'd) ... die on quit */\n\t\t\tquitit = 1;\n\t\t\tbreak;\n\n\t\tcase 's':\t\t/* -s\tRead from std input */\n\t\t\tnofile++;\n\t\t\tbreak;\n\n\t\tcase 't':\t\t/* -t\tRead one line from input */\n\t\t\tonelflg = 2;\n\t\t\tprompt = 0;\n\t\t\tnofile++;\n\t\t\tbreak;\n\n\t\tcase 'v':\t\t/* -v\tEcho hist expanded input */\n\t\t\tnverbose = 1;\t\t\t/* ... later */\n\t\t\tbreak;\n\n\t\tcase 'x':\t\t/* -x\tEcho just before execution */\n\t\t\tnexececho = 1;\t\t\t/* ... later */\n\t\t\tbreak;\n\n\t\tcase 'V':\t\t/* -V\tEcho hist expanded input */\n\t\t\tsetNS(\"verbose\");\t\t/* NOW! */\n\t\t\tbreak;\n\n\t\tcase 'X':\t\t/* -X\tEcho just before execution */\n\t\t\tsetNS(\"echo\");\t\t\t/* NOW! */\n\t\t\tbreak;\n\n\t\t} while (*cp);\n\t\tv++, c--;\n\t}\n\n\tif (quitit)\t\t\t/* With all due haste, for debugging */\n\t\t(void) signal(SIGQUIT, SIG_DFL);\n\n\t/*\n\t * Unless prevented by -c, -i, -s, or -t, if there\n\t * are remaining arguments the first of them is the name\n\t * of a shell file from which to read commands.\n\t */\n\tif (nofile == 0 && c > 0) {\n\t\tnofile = open(v[0], 0);\n\t\tif (nofile < 0) {\n\t\t\tchild++;\t\t/* So this ... */\n\t\t\tPerror(v[0]);\t\t/* ... doesn't return */\n\t\t}\n\t\tfile = v[0];\n\t\tSHIN = dmove(nofile, FSHIN);\t/* Replace FSHIN */\n\t\t(void) ioctl(SHIN, FIOCLEX, (char *)0);\n\t\tprompt = 0;\n\t\tc--, v++;\n\t}\n\tif (!batch && (uid != geteuid() || getgid() != getegid())) {\n\t\terrno = EACCES;\n\t\tchild++;\t\t\t/* So this ... */\n\t\tPerror(\"csh\");\t\t\t/* ... doesn't return */\n\t}\n\t/*\n\t * Consider input a tty if it really is or we are interactive.\n\t */\n\tintty = intact || isatty(SHIN);\n\t/*\n\t * Decide whether we should play with signals or not.\n\t * If we are explicitly told (via -i, or -) or we are a login\n\t * shell (arg0 starts with -) or the input and output are both\n\t * the ttys(\"csh\", or \"csh</dev/ttyx>/dev/ttyx\")\n\t * Note that in only the login shell is it likely that parent\n\t * may have set signals to be ignored\n\t */\n\tif (loginsh || intact || intty && isatty(SHOUT))\n\t\tsetintr = 1;\n#ifdef TELL\n\tsettell();\n#endif\n\t/*\n\t * Save the remaining arguments in argv.\n\t */\n\tsetq(\"argv\", v, &shvhed);\n\n\t/*\n\t * Set up the prompt.\n\t */\n\tif (prompt)\n\t\tset(\"prompt\", uid == 0 ? \"# \" : \"% \");\n\n\t/*\n\t * If we are an interactive shell, then start fiddling\n\t * with the signals; this is a tricky game.\n\t */\n\tshpgrp = getpgrp(0);\n\topgrp = tpgrp = -1;\n\toldisc = -1;\n\tif (setintr) {\n\t\t**av = '-';\n\t\tif (!quitit)\t\t/* Wary! */\n\t\t\t(void) signal(SIGQUIT, SIG_IGN);\n\t\t(void) signal(SIGINT, pintr);\n\t\t(void) sigblock(sigmask(SIGINT));\n\t\t(void) signal(SIGTERM, SIG_IGN);\n\t\tif (quitit == 0 && arginp == 0) {\n\t\t\t(void) signal(SIGTSTP, SIG_IGN);\n\t\t\t(void) signal(SIGTTIN, SIG_IGN);\n\t\t\t(void) signal(SIGTTOU, SIG_IGN);\n\t\t\t/*\n\t\t\t * Wait till in foreground, in case someone\n\t\t\t * stupidly runs\n\t\t\t *\tcsh &\n\t\t\t * dont want to try to grab away the tty.\n\t\t\t */\n\t\t\tif (isatty(FSHDIAG))\n\t\t\t\tf = FSHDIAG;\n\t\t\telse if (isatty(FSHOUT))\n\t\t\t\tf = FSHOUT;\n\t\t\telse if (isatty(OLDSTD))\n\t\t\t\tf = OLDSTD;\n\t\t\telse\n\t\t\t\tf = -1;\nretry:\n\t\t\tif (ioctl(f, TIOCGPGRP, (char *)&tpgrp) == 0 &&\n\t\t\t    tpgrp != -1) {\n\t\t\t\tint ldisc;\n\t\t\t\tif (tpgrp != shpgrp) {\n\t\t\t\t\tvoid (*old)(int) = signal(SIGTTIN, SIG_DFL);\n\t\t\t\t\t(void) kill(0, SIGTTIN);\n\t\t\t\t\t(void) signal(SIGTTIN, old);\n\t\t\t\t\tgoto retry;\n\t\t\t\t}\n\t\t\t\tif (ioctl(f, TIOCGETD, (char *)&oldisc) != 0)\n\t\t\t\t\tgoto notty;\n\t\t\t\tif (oldisc != NTTYDISC) {\n#ifdef DEBUG\n\t\t\t\t\tprintf(\"Switching to new tty driver...\\n\");\n#endif\n\t\t\t\t\tldisc = NTTYDISC;\n\t\t\t\t\t(void) ioctl(f, TIOCSETD,\n\t\t\t\t\t\t(char *)&ldisc);\n\t\t\t\t} else\n\t\t\t\t\toldisc = -1;\n\t\t\t\topgrp = shpgrp;\n\t\t\t\tshpgrp = getpid();\n\t\t\t\ttpgrp = shpgrp;\n\t\t\t\t(void) ioctl(f, TIOCSPGRP, (char *)&shpgrp);\n\t\t\t\t(void) setpgrp(0, shpgrp);\n\t\t\t\t(void) ioctl(dcopy(f, FSHTTY), FIOCLEX,\n\t\t\t\t\t(char *)0);\n\t\t\t} else {\nnotty:\n  printf(\"Warning: no access to tty; thus no job control in this shell...\\n\");\n\t\t\t\ttpgrp = -1;\n\t\t\t}\n\t\t}\n\t}\n\tif (setintr == 0 && parintr == SIG_DFL)\n\t\tsetintr++;\n\t(void) signal(SIGCHLD, pchild);\t/* while signals not ready */\n\n\t/*\n\t * Set an exit here in case of an interrupt or error reading\n\t * the shell start-up scripts.\n\t */\n\tsetexit();\n\thaderr = 0;\t\t/* In case second time through */\n\tif (!fast && reenter == 0) {\n\t\treenter++;\n\t\t/* Will have value(\"home\") here because set fast if don't */\n\t\tsrccat(value(\"home\"), \"/.cshrc\");\n\t\tif (!fast && !arginp && !onelflg && !havhash)\n\t\t\tdohash();\n\t\tif (loginsh) {\n\t\t\tsrccat(value(\"home\"), \"/.login\");\n\t\t}\n\t\tdosource(loadhist);\n\t}\n\n\t/*\n\t * Now are ready for the -v and -x flags\n\t */\n\tif (nverbose)\n\t\tsetNS(\"verbose\");\n\tif (nexececho)\n\t\tsetNS(\"echo\");\n\n\t/*\n\t * All the rest of the world is inside this call.\n\t * The argument to process indicates whether it should\n\t * catch \"error unwinds\".  Thus if we are a interactive shell\n\t * our call here will never return by being blown past on an error.\n\t */\n\tprocess(setintr);\n\n\t/*\n\t * Mop-up.\n\t */\n\tif (loginsh) {\n\t\tprintf(\"logout\\n\");\n\t\t(void) close(SHIN);\n\t\tchild++;\n\t\tgoodbye();\n\t}\n\trechist();\n\texitstat();\n}\n\nuntty()\n{\n\n\tif (tpgrp > 0) {\n\t\t(void) setpgrp(0, opgrp);\n\t\t(void) ioctl(FSHTTY, TIOCSPGRP, (char *)&opgrp);\n\t\tif (oldisc != -1 && oldisc != NTTYDISC) {\n#ifdef DEBUG\n\t\t\tprintf(\"\\nReverting to old tty driver...\\n\");\n#endif\n\t\t\t(void) ioctl(FSHTTY, TIOCSETD, (char *)&oldisc);\n\t\t}\n\t}\n}\n\nimportpath(cp)\n\tchar *cp;\n{\n\tregister int i = 0;\n\tregister char *dp;\n\tregister char **pv;\n\tint c;\n\tstatic char dot[2] = {'.', 0};\n\n\tfor (dp = cp; *dp; dp++)\n\t\tif (*dp == ':')\n\t\t\ti++;\n\t/*\n\t * i+2 where i is the number of colons in the path.\n\t * There are i+1 directories in the path plus we need\n\t * room for a zero terminator.\n\t */\n\tpv = (char **) calloc((unsigned) (i + 2), sizeof (char **));\n\tdp = cp;\n\ti = 0;\n\tif (*dp)\n\tfor (;;) {\n\t\tif ((c = *dp) == ':' || c == 0) {\n\t\t\t*dp = 0;\n\t\t\tpv[i++] = savestr(*cp ? cp : dot);\n\t\t\tif (c) {\n\t\t\t\tcp = dp + 1;\n\t\t\t\t*dp = ':';\n\t\t\t} else\n\t\t\t\tbreak;\n\t\t}\n\t\tdp++;\n\t}\n\tpv[i] = 0;\n\tset1(\"path\", pv, &shvhed);\n}\n\n/*\n * Source to the file which is the catenation of the argument names.\n */\nsrccat(cp, dp)\n\tchar *cp, *dp;\n{\n\tregister char *ep = strspl(cp, dp);\n\tregister int unit = dmove(open(ep, 0), -1);\n\n\t(void) ioctl(unit, FIOCLEX, (char *)0);\n\txfree(ep);\n#ifdef INGRES\n\tsrcunit(unit, 0, 0);\n#else\n\tsrcunit(unit, 1, 0);\n#endif\n}\n\n/*\n * Source to a unit.  If onlyown it must be our file or our group or\n * we don't chance it.\tThis occurs on \".cshrc\"s and the like.\n */\nsrcunit(unit, onlyown, hflg)\n\tregister int unit;\n\tbool onlyown;\n\tbool hflg;\n{\n\t/* We have to push down a lot of state here */\n\t/* All this could go into a structure */\n\tint oSHIN = -1, oldintty = intty;\n\tstruct whyle *oldwhyl = whyles;\n\tchar *ogointr = gointr, *oarginp = arginp;\n\tchar *oevalp = evalp, **oevalvec = evalvec;\n\tint oonelflg = onelflg;\n\tbool oenterhist = enterhist;\n\tchar OHIST = HIST;\n#ifdef TELL\n\tbool otell = cantell;\n#endif\n\tstruct Bin saveB;\n\n\t/* The (few) real local variables */\n\tjmp_buf oldexit;\n\tint reenter;\n\tlong omask;\n\n\tif (unit < 0)\n\t\treturn;\n\tif (didfds)\n\t\tdonefds();\n\tif (onlyown) {\n\t\tstruct stat stb;\n\n\t\tif (fstat(unit, &stb) < 0 ||\n\t\t    (stb.st_uid != uid && stb.st_gid != getgid())) {\n\t\t\t(void) close(unit);\n\t\t\treturn;\n\t\t}\n\t}\n\n\t/*\n\t * There is a critical section here while we are pushing down the\n\t * input stream since we have stuff in different structures.\n\t * If we weren't careful an interrupt could corrupt SHIN's Bin\n\t * structure and kill the shell.\n\t *\n\t * We could avoid the critical region by grouping all the stuff\n\t * in a single structure and pointing at it to move it all at\n\t * once.  This is less efficient globally on many variable references\n\t * however.\n\t */\n\tgetexit(oldexit);\n\treenter = 0;\n\tif (setintr)\n\t\tomask = sigblock(sigmask(SIGINT));\n\tsetexit();\n\treenter++;\n\tif (reenter == 1) {\n\t\t/* Setup the new values of the state stuff saved above */\n\t\tmemcpy((char *)&saveB, (char *)&B, sizeof saveB);\n\t\tfbuf = (char **) 0;\n\t\tfseekp = feobp = fblocks = 0;\n\t\toSHIN = SHIN, SHIN = unit, arginp = 0, onelflg = 0;\n\t\tintty = isatty(SHIN), whyles = 0, gointr = 0;\n\t\tevalvec = 0; evalp = 0;\n\t\tenterhist = hflg;\n\t\tif (enterhist)\n\t\t\tHIST = '\\0';\n\t\t/*\n\t\t * Now if we are allowing commands to be interrupted,\n\t\t * we let ourselves be interrupted.\n\t\t */\n\t\tif (setintr)\n\t\t\t(void) sigsetmask(omask);\n#ifdef TELL\n\t\tsettell();\n#endif\n\t\tprocess(0);\t\t/* 0 -> blow away on errors */\n\t}\n\tif (setintr)\n\t\t(void) sigsetmask(omask);\n\tif (oSHIN >= 0) {\n\t\tregister int i;\n\n\t\t/* We made it to the new state... free up its storage */\n\t\t/* This code could get run twice but xfree doesn't care */\n\t\tfor (i = 0; i < fblocks; i++)\n\t\t\txfree(fbuf[i]);\n\t\txfree((char *)fbuf);\n\n\t\t/* Reset input arena */\n\t\tmemcpy((char *)&B, (char *)&saveB, sizeof B);\n\n\t\t(void) close(SHIN), SHIN = oSHIN;\n\t\targinp = oarginp, onelflg = oonelflg;\n\t\tevalp = oevalp, evalvec = oevalvec;\n\t\tintty = oldintty, whyles = oldwhyl, gointr = ogointr;\n\t\tif (enterhist)\n\t\t\tHIST = OHIST;\n\t\tenterhist = oenterhist;\n#ifdef TELL\n\t\tcantell = otell;\n#endif\n\t}\n\n\tresexit(oldexit);\n\t/*\n\t * If process reset() (effectively an unwind) then\n\t * we must also unwind.\n\t */\n\tif (reenter >= 2)\n\t\terror(NOSTR);\n}\n\nrechist()\n{\n\tchar buf[BUFSIZ];\n\tint fp, ftmp, oldidfds;\n\n\tif (!fast) {\n\t\tif (value(\"savehist\")[0] == '\\0')\n\t\t\treturn;\n\t\t(void) strcpy(buf, value(\"home\"));\n\t\t(void) strcat(buf, \"/.history\");\n\t\tfp = creat(buf, 0666);\n\t\tif (fp == -1)\n\t\t\treturn;\n\t\toldidfds = didfds;\n\t\tdidfds = 0;\n\t\tftmp = SHOUT;\n\t\tSHOUT = fp;\n\t\t(void) strcpy(buf, value(\"savehist\"));\n\t\tdumphist[2] = buf;\n\t\tdohist(dumphist);\n\t\t(void) close(fp);\n\t\tSHOUT = ftmp;\n\t\tdidfds = oldidfds;\n\t}\n}\n\ngoodbye()\n{\n\tif (loginsh) {\n\t\t(void) signal(SIGQUIT, SIG_IGN);\n\t\t(void) signal(SIGINT, SIG_IGN);\n\t\t(void) signal(SIGTERM, SIG_IGN);\n\t\tsetintr = 0;\t\t/* No interrupts after \"logout\" */\n\t\tif (adrof(\"home\"))\n\t\t\tsrccat(value(\"home\"), \"/.logout\");\n\t}\n\trechist();\n\texitstat();\n}\n\nexitstat()\n{\n\n#ifdef PROF\n\tmonitor(0);\n#endif\n\t/*\n\t * Note that if STATUS is corrupted (i.e. getn bombs)\n\t * then error will exit directly because we poke child here.\n\t * Otherwise we might continue unwarrantedly (sic).\n\t */\n\tchild++;\n\texit(getn(value(\"status\")));\n}\n\nchar\t*jobargv[2] = { \"jobs\", 0 };\n\npintr1(wantnl)\n\tbool wantnl;\n{\n\tregister char **v;\n\tlong omask;\n\n\tomask = sigblock(0L);\n\tif (setintr) {\n\t\t(void) sigsetmask(omask & ~sigmask(SIGINT));\n\t\tif (pjobs) {\n\t\t\tpjobs = 0;\n\t\t\tprintf(\"\\n\");\n\t\t\tdojobs(jobargv);\n\t\t\tbferr(\"Interrupted\");\n\t\t}\n\t}\n\t(void) sigsetmask(omask & ~sigmask(SIGCHLD));\n\tdraino();\n\n\t/*\n\t * If we have an active \"onintr\" then we search for the label.\n\t * Note that if one does \"onintr -\" then we shan't be interruptible\n\t * so we needn't worry about that here.\n\t */\n\tif (gointr) {\n\t\tsearch(ZGOTO, 0, gointr);\n\t\ttimflg = 0;\n\t\tif (v = pargv)\n\t\t\tpargv = 0, blkfree(v);\n\t\tif (v = gargv)\n\t\t\tgargv = 0, blkfree(v);\n\t\treset();\n\t} else if (intty && wantnl)\n\t\tprintf(\"\\n\");\t\t/* Some like this, others don't */\n\terror(NOSTR);\n}\n\n/*\n * Process is the main driving routine for the shell.\n * It runs all command processing, except for those within { ... }\n * in expressions (which is run by a routine evalav in sh.exp.c which\n * is a stripped down process), and `...` evaluation which is run\n * also by a subset of this code in sh.glob.c in the routine backeval.\n *\n * The code here is a little strange because part of it is interruptible\n * and hence freeing of structures appears to occur when none is necessary\n * if this is ignored.\n *\n * Note that if catch is not set then we will unwind on any error.\n * If an end-of-file occurs, we return.\n */\nprocess(catch)\n\tbool catch;\n{\n\tjmp_buf osetexit;\n\tregister struct command *t;\n\n\tgetexit(osetexit);\n\tfor (;;) {\n\t\tpendjob();\n\t\tparaml.next = paraml.prev = &paraml;\n\t\tparaml.word = \"\";\n\t\tt = 0;\n\t\tsetexit();\n\t\tjustpr = enterhist;\t/* execute if not entering history */\n\n\t\t/*\n\t\t * Interruptible during interactive reads\n\t\t */\n\t\tif (setintr)\n\t\t\t(void) sigsetmask(sigblock(0L) & ~sigmask(SIGINT));\n\n\t\t/*\n\t\t * For the sake of reset()\n\t\t */\n\t\tfreelex(&paraml), freesyn(t), t = 0;\n\n\t\tif (haderr) {\n\t\t\tif (!catch) {\n\t\t\t\t/* unwind */\n\t\t\t\tdoneinp = 0;\n\t\t\t\tresexit(osetexit);\n\t\t\t\treset();\n\t\t\t}\n\t\t\thaderr = 0;\n\t\t\t/*\n\t\t\t * Every error is eventually caught here or\n\t\t\t * the shell dies.  It is at this\n\t\t\t * point that we clean up any left-over open\n\t\t\t * files, by closing all but a fixed number\n\t\t\t * of pre-defined files.  Thus routines don't\n\t\t\t * have to worry about leaving files open due\n\t\t\t * to deeper errors... they will get closed here.\n\t\t\t */\n\t\t\tclosem();\n\t\t\tcontinue;\n\t\t}\n\t\tif (doneinp) {\n\t\t\tdoneinp = 0;\n\t\t\tbreak;\n\t\t}\n\t\tif (chkstop)\n\t\t\tchkstop--;\n\t\tif (neednote)\n\t\t\tpnote();\n\t\tif (intty && prompt && evalvec == 0) {\n\t\t\tmailchk();\n\t\t\t/*\n\t\t\t * If we are at the end of the input buffer\n\t\t\t * then we are going to read fresh stuff.\n\t\t\t * Otherwise, we are rereading input and don't\n\t\t\t * need or want to prompt.\n\t\t\t */\n\t\t\tif (fseekp == feobp)\n\t\t\t\tprintprompt();\n\t\t}\n\t\tparserr = 0;\n\n\t\t/*\n\t\t * Echo not only on VERBOSE, but also with history expansion.\n\t\t * If there is a lexical error then we forego history echo.\n\t\t */\n\t\tif (lex(&paraml) && !parserr && intty ||\n\t\t    adrof(\"verbose\")) {\n\t\t\thaderr = 1;\n\t\t\tprlex(&paraml);\n\t\t\thaderr = 0;\n\t\t}\n\n\t\t/*\n\t\t * The parser may lose space if interrupted.\n\t\t */\n\t\tif (setintr)\n\t\t\t(void) sigblock(sigmask(SIGINT));\n\n\t\t/*\n\t\t * Save input text on the history list if\n\t\t * reading in old history, or it\n\t\t * is from the terminal at the top level and not\n\t\t * in a loop.\n\t\t */\n\t\tif (enterhist || catch && intty && !whyles)\n\t\t\tsavehist(&paraml);\n\n\t\t/*\n\t\t * Print lexical error messages, except when sourcing\n\t\t * history lists.\n\t\t */\n\t\tif (!enterhist && parserr)\n\t\t\terror(parserr);\n\n\t\t/*\n\t\t * If had a history command :p modifier then\n\t\t * this is as far as we should go\n\t\t */\n\t\tif (justpr)\n\t\t\treset();\n\n\t\talias(&paraml);\n\n\t\t/*\n\t\t * Parse the words of the input into a parse tree.\n\t\t */\n\t\tt = syntax(paraml.next, &paraml, 0);\n\t\tif (parserr)\n\t\t\terror(parserr);\n\n\t\t/*\n\t\t * Execute the parse tree\n\t\t */\n\t\texecute(t, tpgrp);\n\n\t\t/*\n\t\t * Made it!\n\t\t */\n\t\tfreelex(&paraml), freesyn(t);\n\t}\n\tresexit(osetexit);\n}\n\ndosource(t)\n\tregister char **t;\n{\n\tregister char *f;\n\tregister int u;\n\tbool hflg = 0;\n\tchar buf[BUFSIZ];\n\n\tt++;\n\tif (*t && eq(*t, \"-h\")) {\n\t\tt++;\n\t\thflg++;\n\t}\n\t(void) strcpy(buf, *t);\n\tf = globone(buf);\n\tu = dmove(open(f, 0), -1);\n\txfree(f);\n\tif (u < 0 && !hflg)\n\t\tPerror(f);\n\t(void) ioctl(u, FIOCLEX, (char *)0);\n\tsrcunit(u, 0, hflg);\n}\n\n/*\n * Check for mail.\n * If we are a login shell, then we don't want to tell\n * about any mail file unless its been modified\n * after the time we started.\n * This prevents us from telling the user things he already\n * knows, since the login program insists on saying\n * \"You have mail.\"\n */\nmailchk()\n{\n\tregister struct varent *v;\n\tregister char **vp;\n\ttime_t t;\n\tint intvl, cnt;\n\tstruct stat stb;\n\tbool new;\n\n\tv = adrof(\"mail\");\n\tif (v == 0)\n\t\treturn;\n\t(void) time(&t);\n\tvp = v->vec;\n\tcnt = blklen(vp);\n\tintvl = (cnt && number(*vp)) ? (--cnt, getn(*vp++)) : MAILINTVL;\n\tif (intvl < 1)\n\t\tintvl = 1;\n\tif (chktim + intvl > t)\n\t\treturn;\n\tfor (; *vp; vp++) {\n\t\tif (stat(*vp, &stb) < 0)\n\t\t\tcontinue;\n\t\tnew = stb.st_mtime > time0.tv_sec;\n\t\tif (stb.st_size == 0 || stb.st_atime > stb.st_mtime ||\n\t\t    (stb.st_atime < chktim && stb.st_mtime < chktim) ||\n\t\t    loginsh && !new)\n\t\t\tcontinue;\n\t\tif (cnt == 1)\n\t\t\tprintf(\"You have %smail.\\n\", new ? \"new \" : \"\");\n\t\telse\n\t\t\tprintf(\"%s in %s.\\n\", new ? \"New mail\" : \"Mail\", *vp);\n\t}\n\tchktim = t;\n}\n\n#include <pwd.h>\n/*\n * Extract a home directory from the password file\n * The argument points to a buffer where the name of the\n * user whose home directory is sought is currently.\n * We write the home directory of the user back there.\n */\ngethdir(home)\n\tchar *home;\n{\n\tregister struct passwd *pp = getpwnam(home);\n\n\tif (pp == 0)\n\t\treturn (1);\n\t(void) strcpy(home, pp->pw_dir);\n\treturn (0);\n}\n\n/*\n * Move the initial descriptors to their eventual\n * resting places, closin all other units.\n */\ninitdesc()\n{\n\tdidfds = 0;\t\t\t/* 0, 1, 2 aren't set up */\n\t(void) ioctl(SHIN = dcopy(0, FSHIN), FIOCLEX, (char *)0);\n\t(void) ioctl(SHOUT = dcopy(1, FSHOUT), FIOCLEX, (char *)0);\n\t(void) ioctl(SHDIAG = dcopy(2, FSHDIAG), FIOCLEX, (char *)0);\n\t(void) ioctl(OLDSTD = dcopy(SHIN, FOLDSTD), FIOCLEX, (char *)0);\n\tclosem();\n}\n\n#ifdef PROF\nvoid done(i)\n#else\nvoid exit(i)\n#endif\n\tint i;\n{\n\tuntty();\n\t_exit(i);\n}\n\nprintprompt()\n{\n\tregister char *cp;\n\n\tif (!whyles) {\n\t\tfor (cp = value(\"prompt\"); *cp; cp++)\n\t\t\tif (*cp == HIST)\n\t\t\t\tprintf(\"%d\", eventno + 1);\n\t\t\telse {\n\t\t\t\tif (*cp == '\\\\' && cp[1] == HIST)\n\t\t\t\t\tcp++;\n\t\t\t\tputchar(*cp | QUOTE);\n\t\t\t}\n\t} else\n\t\t/*\n\t\t * Prompt for forward reading loop\n\t\t * body content.\n\t\t */\n\t\tprintf(\"? \");\n\tflush();\n}\n"
  },
  {
    "path": "bin/csh/sh.char.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if\t!defined(lint) && defined(DOSCCS)\nstatic char *sccsid = \"@(#)sh.char.c\t5.3 (Berkeley) 3/29/86\";\n#endif\n\n#include \"sh.char.h\"\n\nunsigned short _cmap[256] = {\n/*\tnul\t\tsoh\t\tstx\t\tetx\t*/\n\t0,\t\t0,\t\t0,\t\t0,\n\n/*\teot\t\tenq\t\tack\t\tbel\t*/\n\t0,\t\t0,\t\t0,\t\t0,\n\n/*\tbs\t\tht\t\tnl\t\tvt\t*/\n\t0,\t\t_SP|_META,\t_NL|_META,\t0,\n\n/*\tnp\t\tcr\t\tso\t\tsi\t*/\n\t0,\t\t0,\t\t0,\t\t0,\n\n/*\tdle\t\tdc1\t\tdc2\t\tdc3\t*/\n\t0,\t\t0,\t\t0,\t\t0,\n\n/*\tdc4\t\tnak\t\tsyn\t\tetb\t*/\n\t0,\t\t0,\t\t0,\t\t0,\n\n/*\tcan\t\tem\t\tsub\t\tesc\t*/\n\t0,\t\t0,\t\t0,\t\t0,\n\n/*\tfs\t\tgs\t\trs\t\tus\t*/\n\t0,\t\t0,\t\t0,\t\t0,\n\n/*\tsp\t\t!\t\t\"\t\t#\t*/\n\t_SP|_META,\t0,\t\t_Q,\t\t_META,\n\n/*\t$\t\t%\t\t&\t\t'\t*/\n\t_DOL,\t\t0,\t\t_META,\t\t_Q,\n\n/*\t(\t\t)\t\t*\t\t+\t*/\n\t_META,\t\t_META,\t\t_GLOB,\t\t0,\n\n/*\t,\t\t-\t\t.\t\t/\t*/\n\t0,\t\t0,\t\t0,\t\t0,\n\n/*\t0\t\t1\t\t2\t\t3\t*/\n\t_DIG,\t\t_DIG,\t\t_DIG,\t\t_DIG,\n\n/*\t4\t\t5\t\t6\t\t7\t*/\n\t_DIG,\t\t_DIG,\t\t_DIG,\t\t_DIG,\n\n/*\t8\t\t9\t\t:\t\t;\t*/\n\t_DIG,\t\t_DIG,\t\t0,\t\t_META,\n\n/*\t<\t\t=\t\t>\t\t?\t*/\n\t_META,\t\t0,\t\t_META,\t\t_GLOB,\n\n/*\t@\t\tA\t\tB\t\tC\t*/\n\t0,\t\t_LET,\t\t_LET,\t\t_LET,\n\n/*\tD\t\tE\t\tF\t\tG\t*/\n\t_LET,\t\t_LET,\t\t_LET,\t\t_LET,\n\n/*\tH\t\tI\t\tJ\t\tK\t*/\n\t_LET,\t\t_LET,\t\t_LET,\t\t_LET,\n\n/*\tL\t\tM\t\tN\t\tO\t*/\n\t_LET,\t\t_LET,\t\t_LET,\t\t_LET,\n\n/*\tP\t\tQ\t\tR\t\tS\t*/\n\t_LET,\t\t_LET,\t\t_LET,\t\t_LET,\n\n/*\tT\t\tU\t\tV\t\tW\t*/\n\t_LET,\t\t_LET,\t\t_LET,\t\t_LET,\n\n/*\tX\t\tY\t\tZ\t\t[\t*/\n\t_LET,\t\t_LET,\t\t_LET,\t\t_GLOB,\n\n/*\t\\\t\t]\t\t^\t\t_\t*/\n\t_ESC,\t\t0,\t\t0,\t\t_LET,\n\n/*\t`\t\ta\t\tb\t\tc\t*/\n\t_Q1|_GLOB,\t_LET,\t\t_LET,\t\t_LET,\n\n/*\td\t\te\t\tf\t\tg\t*/\n\t_LET,\t\t_LET,\t\t_LET,\t\t_LET,\n\n/*\th\t\ti\t\tj\t\tk\t*/\n\t_LET,\t\t_LET,\t\t_LET,\t\t_LET,\n\n/*\tl\t\tm\t\tn\t\to\t*/\n\t_LET,\t\t_LET,\t\t_LET,\t\t_LET,\n\n/*\tp\t\tq\t\tr\t\ts\t*/\n\t_LET,\t\t_LET,\t\t_LET,\t\t_LET,\n\n/*\tt\t\tu\t\tv\t\tw\t*/\n\t_LET,\t\t_LET,\t\t_LET,\t\t_LET,\n\n/*\tx\t\ty\t\tz\t\t{\t*/\n\t_LET,\t\t_LET,\t\t_LET,\t\t_GLOB,\n\n/*\t|\t\t}\t\t~\t\tdel\t*/\n\t_META,\t\t0,\t\t0,\t\t0,\n};\n"
  },
  {
    "path": "bin/csh/sh.char.h",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)sh.char.h\t5.3 (Berkeley) 3/29/86\n */\n\n/*\n * Table for spotting special characters quickly\n *\n * Makes for very obscure but efficient coding.\n */\n\nextern unsigned short _cmap[];\n\n#define _Q\t0x01\t\t/* '\" */\n#define _Q1\t0x02\t\t/* ` */\n#define _SP\t0x04\t\t/* space and tab */\n#define _NL\t0x08\t\t/* \\n */\n#define _META\t0x10\t\t/* lex meta characters, sp #'`\";&<>()|\\t\\n */\n#define _GLOB\t0x20\t\t/* glob characters, *?{[` */\n#define _ESC\t0x40\t\t/* \\ */\n#define _DOL\t0x80\t\t/* $ */\n#define _DIG   0x100\t\t/* 0-9 */\n#define _LET   0x200\t\t/* a-z, A-Z, _ */\n\n#define cmap(c, bits)\t(_cmap[(unsigned char)(c)] & (bits))\n\n#define isglob(c)\tcmap(c, _GLOB)\n#define isspace(c)\tcmap(c, _SP)\n#define isspnl(c)\tcmap(c, _SP|_NL)\n#define ismeta(c)\tcmap(c, _META)\n#define digit(c)\tcmap(c, _DIG)\n#define letter(c)\tcmap(c, _LET)\n#define alnum(c)\t(digit(c) || letter(c))\n"
  },
  {
    "path": "bin/csh/sh.dir.c",
    "content": "/*\n * C Shell - directory management\n *\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"sh.h\"\n#include \"sh.dir.h\"\n\nstruct\tdirectory *dfind();\nchar\t*dfollow();\nchar\t*dcanon();\nstruct\tdirectory dhead;\t\t/* \"head\" of loop */\nint\tprintd;\t\t\t\t/* force name to be printed */\nstatic\tchar *fakev[] = { \"dirs\", NOSTR };\n\n/*\n * dinit - initialize current working directory\n */\ndinit(hp)\n\tchar *hp;\n{\n\tregister char *cp;\n\tregister struct directory *dp;\n\tchar path[MAXPATHLEN];\n\n\tif (loginsh && hp)\n\t\tcp = hp;\n\telse {\n\t\tcp = getwd(path);\n\t\tif (cp == NULL) {\n\t\t\tif (write(2, path, strlen(path)) < 0)\n\t\t\t        ;\n\t\t\texit(1);\n\t\t}\n\t}\n\tdp = (struct directory *)calloc(sizeof (struct directory), 1);\n\tdp->di_name = savestr(cp);\n\tdp->di_count = 0;\n\tdhead.di_next = dhead.di_prev = dp;\n\tdp->di_next = dp->di_prev = &dhead;\n\tprintd = 0;\n\tdnewcwd(dp);\n}\n\n/*\n * dodirs - list all directories in directory loop\n */\ndodirs(v)\n\tchar **v;\n{\n\tregister struct directory *dp;\n\tbool lflag;\n\tchar *hp = value(\"home\");\n\n\tif (*hp == '\\0')\n\t\thp = NOSTR;\n\tif (*++v != NOSTR)\n\t\tif (eq(*v, \"-l\") && *++v == NOSTR)\n\t\t\tlflag = 1;\n\t\telse\n\t\t\terror(\"Usage: dirs [ -l ]\");\n\telse\n\t\tlflag = 0;\n\tdp = dcwd;\n\tdo {\n\t\tif (dp == &dhead)\n\t\t\tcontinue;\n\t\tif (!lflag && hp != NOSTR) {\n\t\t\tdtildepr(hp, dp->di_name);\n\t\t} else\n\t\t\tprintf(\"%s\", dp->di_name);\n\t\tprintf(\" \");\n\t} while ((dp = dp->di_prev) != dcwd);\n\tprintf(\"\\n\");\n}\n\ndtildepr(home, dir)\n\tregister char *home, *dir;\n{\n\n\tif (!eq(home, \"/\") && prefix(home, dir))\n\t\tprintf(\"~%s\", dir + strlen(home));\n\telse\n\t\tprintf(\"%s\", dir);\n}\n\n/*\n * dochngd - implement chdir command.\n */\ndochngd(v)\n\tchar **v;\n{\n\tregister char *cp;\n\tregister struct directory *dp;\n\n\tprintd = 0;\n\tif (*++v == NOSTR) {\n\t\tif ((cp = value(\"home\")) == NOSTR || *cp == 0)\n\t\t\tbferr(\"No home directory\");\n\t\tif (chdir(cp) < 0)\n\t\t\tbferr(\"Can't change to home directory\");\n\t\tcp = savestr(cp);\n\t} else if ((dp = dfind(*v)) != 0) {\n\t\tprintd = 1;\n\t\tif (chdir(dp->di_name) < 0)\n\t\t\tPerror(dp->di_name);\n\t\tdcwd->di_prev->di_next = dcwd->di_next;\n\t\tdcwd->di_next->di_prev = dcwd->di_prev;\n\t\tgoto flushcwd;\n\t} else\n\t\tcp = dfollow(*v);\n\tdp = (struct directory *)calloc(sizeof (struct directory), 1);\n\tdp->di_name = cp;\n\tdp->di_count = 0;\n\tdp->di_next = dcwd->di_next;\n\tdp->di_prev = dcwd->di_prev;\n\tdp->di_prev->di_next = dp;\n\tdp->di_next->di_prev = dp;\nflushcwd:\n\tdfree(dcwd);\n\tdnewcwd(dp);\n}\n\n/*\n * dfollow - change to arg directory; fall back on cdpath if not valid\n */\nchar *\ndfollow(cp)\n\tregister char *cp;\n{\n\tregister char *dp;\n\tstruct varent *c;\n\n\tcp = globone(cp);\n\tif (chdir(cp) >= 0)\n\t\tgoto gotcha;\n\tif (cp[0] != '/' && !prefix(\"./\", cp) && !prefix(\"../\", cp)\n\t    && (c = adrof(\"cdpath\"))) {\n\t\tchar **cdp;\n\t\tregister char *p;\n\t\tchar buf[MAXPATHLEN];\n\n\t\tfor (cdp = c->vec; *cdp; cdp++) {\n\t\t\tfor (dp = buf, p = *cdp; *dp++ = *p++;)\n\t\t\t\t;\n\t\t\tdp[-1] = '/';\n\t\t\tfor (p = cp; *dp++ = *p++;)\n\t\t\t\t;\n\t\t\tif (chdir(buf) >= 0) {\n\t\t\t\tprintd = 1;\n\t\t\t\txfree(cp);\n\t\t\t\tcp = savestr(buf);\n\t\t\t\tgoto gotcha;\n\t\t\t}\n\t\t}\n\t}\n\tdp = value(cp);\n\tif ((dp[0] == '/' || dp[0] == '.') && chdir(dp) >= 0) {\n\t\txfree(cp);\n\t\tcp = savestr(dp);\n\t\tprintd = 1;\n\t\tgoto gotcha;\n\t}\n\txfree(cp);\t\t\t/* XXX, use after free */\n\tPerror(cp);\n\ngotcha:\n\tif (*cp != '/') {\n\t\tregister char *p, *q;\n\t\tint cwdlen;\n\n\t\t/*\n\t\t * All in the name of efficiency?\n\t\t */\n\t\tfor (p = dcwd->di_name; *p++;)\n\t\t\t;\n\t\tif ((cwdlen = p - dcwd->di_name - 1) == 1)\t/* root */\n\t\t\tcwdlen = 0;\n\t\tfor (p = cp; *p++;)\n\t\t\t;\n\t\tdp = xalloc((unsigned) (cwdlen + (p - cp) + 1));\n\t\tfor (p = dp, q = dcwd->di_name; *p++ = *q++;)\n\t\t\t;\n\t\tif (cwdlen)\n\t\t\tp[-1] = '/';\n\t\telse\n\t\t\tp--;\t\t\t/* don't add a / after root */\n\t\tfor (q = cp; *p++ = *q++;)\n\t\t\t;\n\t\txfree(cp);\n\t\tcp = dp;\n\t\tdp += cwdlen;\n\t} else\n\t\tdp = cp;\n\treturn dcanon(cp, dp);\n}\n\n/*\n * dopushd - push new directory onto directory stack.\n *\twith no arguments exchange top and second.\n *\twith numeric argument (+n) bring it to top.\n */\ndopushd(v)\n\tchar **v;\n{\n\tregister struct directory *dp;\n\n\tprintd = 1;\n\tif (*++v == NOSTR) {\n\t\tif ((dp = dcwd->di_prev) == &dhead)\n\t\t\tdp = dhead.di_prev;\n\t\tif (dp == dcwd)\n\t\t\tbferr(\"No other directory\");\n\t\tif (chdir(dp->di_name) < 0)\n\t\t\tPerror(dp->di_name);\n\t\tdp->di_prev->di_next = dp->di_next;\n\t\tdp->di_next->di_prev = dp->di_prev;\n\t\tdp->di_next = dcwd->di_next;\n\t\tdp->di_prev = dcwd;\n\t\tdcwd->di_next->di_prev = dp;\n\t\tdcwd->di_next = dp;\n\t} else if (dp = dfind(*v)) {\n\t\tif (chdir(dp->di_name) < 0)\n\t\t\tPerror(dp->di_name);\n\t} else {\n\t\tregister char *cp;\n\n\t\tcp = dfollow(*v);\n\t\tdp = (struct directory *)calloc(sizeof (struct directory), 1);\n\t\tdp->di_name = cp;\n\t\tdp->di_count = 0;\n\t\tdp->di_prev = dcwd;\n\t\tdp->di_next = dcwd->di_next;\n\t\tdcwd->di_next = dp;\n\t\tdp->di_next->di_prev = dp;\n\t}\n\tdnewcwd(dp);\n}\n\n/*\n * dfind - find a directory if specified by numeric (+n) argument\n */\nstruct directory *\ndfind(cp)\n\tregister char *cp;\n{\n\tregister struct directory *dp;\n\tregister int i;\n\tregister char *ep;\n\n\tif (*cp++ != '+')\n\t\treturn (0);\n\tfor (ep = cp; digit(*ep); ep++)\n\t\tcontinue;\n\tif (*ep)\n\t\treturn (0);\n\ti = getn(cp);\n\tif (i <= 0)\n\t\treturn (0);\n\tfor (dp = dcwd; i != 0; i--) {\n\t\tif ((dp = dp->di_prev) == &dhead)\n\t\t\tdp = dp->di_prev;\n\t\tif (dp == dcwd)\n\t\t\tbferr(\"Directory stack not that deep\");\n\t}\n\treturn (dp);\n}\n\n/*\n * dopopd - pop a directory out of the directory stack\n *\twith a numeric argument just discard it.\n */\ndopopd(v)\n\tchar **v;\n{\n\tregister struct directory *dp, *p;\n\n\tprintd = 1;\n\tif (*++v == NOSTR)\n\t\tdp = dcwd;\n\telse if ((dp = dfind(*v)) == 0)\n\t\tbferr(\"Bad directory\");\n\tif (dp->di_prev == &dhead && dp->di_next == &dhead)\n\t\tbferr(\"Directory stack empty\");\n\tif (dp == dcwd) {\n\t\tif ((p = dp->di_prev) == &dhead)\n\t\t\tp = dhead.di_prev;\n\t\tif (chdir(p->di_name) < 0)\n\t\t\tPerror(p->di_name);\n\t}\n\tdp->di_prev->di_next = dp->di_next;\n\tdp->di_next->di_prev = dp->di_prev;\n\tif (dp == dcwd)\n\t\tdnewcwd(p);\n\telse\n\t\tdodirs(fakev);\n\tdfree(dp);\n}\n\n/*\n * dfree - free the directory (or keep it if it still has ref count)\n */\ndfree(dp)\n\tregister struct directory *dp;\n{\n\n\tif (dp->di_count != 0)\n\t\tdp->di_next = dp->di_prev = 0;\n\telse\n\t\txfree(dp->di_name), xfree((char *)dp);\n}\n\n/*\n * dcanon - canonicalize the pathname, removing excess ./ and ../ etc.\n *\twe are of course assuming that the file system is standardly\n *\tconstructed (always have ..'s, directories have links)\n */\nchar *\ndcanon(cp, p)\n\tregister char *cp, *p;\n{\n\tregister char *sp;\n\tregister char *p1, *p2;\t\t/* general purpose */\n\tbool slash;\n\n\tif (*cp != '/')\n\t\tabort();\n\twhile (*p) {\t\t\t/* for each component */\n\t\tsp = p;\t\t\t/* save slash address */\n\t\twhile (*++p == '/')\t/* flush extra slashes */\n\t\t\t;\n\t\tif (p != ++sp)\n\t\t\tfor (p1 = sp, p2 = p; *p1++ = *p2++;)\n\t\t\t\t;\n\t\tp = sp;\t\t\t/* save start of component */\n\t\tslash = 0;\n\t\twhile (*++p)\t\t/* find next slash or end of path */\n\t\t\tif (*p == '/') {\n\t\t\t\tslash = 1;\n\t\t\t\t*p = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\tif (*sp == '\\0')\t/* if component is null */\n\t\t\tif (--sp == cp)\t/* if path is one char (i.e. /) */\n\t\t\t\tbreak;\n\t\t\telse\n\t\t\t\t*sp = '\\0';\n\t\telse if (sp[0] == '.' && sp[1] == 0) {\n\t\t\tif (slash) {\n\t\t\t\tfor (p1 = sp, p2 = p + 1; *p1++ = *p2++;)\n\t\t\t\t\t;\n\t\t\t\tp = --sp;\n\t\t\t} else if (--sp != cp)\n\t\t\t\t*sp = '\\0';\n\t\t} else if (sp[0] == '.' && sp[1] == '.' && sp[2] == 0) {\n\t\t\tchar link[MAXPATHLEN];\n\t\t\tint cc;\n\t\t\tchar *newcp;\n\n\t\t\t/*\n\t\t\t * We have something like \"yyy/xxx/..\", where \"yyy\"\n\t\t\t * can be null or a path starting at /, and \"xxx\"\n\t\t\t * is a single component.\n\t\t\t * Before compressing \"xxx/..\", we want to expand\n\t\t\t * \"yyy/xxx\", if it is a symbolic link.\n\t\t\t */\n\t\t\t*--sp = 0;\t/* form the pathname for readlink */\n\t\t\tif (sp != cp &&\n\t\t\t    (cc = readlink(cp, link, sizeof link)) >= 0) {\n\t\t\t\tlink[cc] = '\\0';\n\t\t\t\tif (slash)\n\t\t\t\t\t*p = '/';\n\t\t\t\t/*\n\t\t\t\t * Point p to the '/' in \"/..\", and restore\n\t\t\t\t * the '/'.\n\t\t\t\t */\n\t\t\t\t*(p = sp) = '/';\n\t\t\t\t/*\n\t\t\t\t * find length of p\n\t\t\t\t */\n\t\t\t\tfor (p1 = p; *p1++;)\n\t\t\t\t\t;\n\t\t\t\tif (*link != '/') {\n\t\t\t\t\t/*\n\t\t\t\t\t * Relative path, expand it between\n\t\t\t\t\t * the \"yyy/\" and the \"/..\".\n\t\t\t\t\t * First, back sp up to the character\n\t\t\t\t\t * past \"yyy/\".\n\t\t\t\t\t */\n\t\t\t\t\twhile (*--sp != '/')\n\t\t\t\t\t\t;\n\t\t\t\t\tsp++;\n\t\t\t\t\t*sp = 0;\n\t\t\t\t\t/*\n\t\t\t\t\t * New length is\n\t\t\t\t\t * \"yyy/\" + link + \"/..\" and rest\n\t\t\t\t\t */\n\t\t\t\t\tp1 = newcp = xalloc((unsigned)\n\t\t\t\t\t\t((sp - cp) + cc + (p1 - p)));\n\t\t\t\t\t/*\n\t\t\t\t\t * Copy new path into newcp\n\t\t\t\t\t */\n\t\t\t\t\tfor (p2 = cp; *p1++ = *p2++;)\n\t\t\t\t\t\t;\n\t\t\t\t\tfor (p1--, p2 = link; *p1++ = *p2++;)\n\t\t\t\t\t\t;\n\t\t\t\t\tfor (p1--, p2 = p; *p1++ = *p2++;)\n\t\t\t\t\t\t;\n\t\t\t\t\t/*\n\t\t\t\t\t * Restart canonicalization at\n\t\t\t\t\t * expanded \"/xxx\".\n\t\t\t\t\t */\n\t\t\t\t\tp = sp - cp - 1 + newcp;\n\t\t\t\t} else {\n\t\t\t\t\t/*\n\t\t\t\t\t * New length is link + \"/..\" and rest\n\t\t\t\t\t */\n\t\t\t\t\tp1 = newcp = xalloc((unsigned)\n\t\t\t\t\t\t(cc + (p1 - p)));\n\t\t\t\t\t/*\n\t\t\t\t\t * Copy new path into newcp\n\t\t\t\t\t */\n\t\t\t\t\tfor (p2 = link; *p1++ = *p2++;)\n\t\t\t\t\t\t;\n\t\t\t\t\tfor (p1--, p2 = p; *p1++ = *p2++;)\n\t\t\t\t\t\t;\n\t\t\t\t\t/*\n\t\t\t\t\t * Restart canonicalization at beginning\n\t\t\t\t\t */\n\t\t\t\t\tp = newcp;\n\t\t\t\t}\n\t\t\t\txfree(cp);\n\t\t\t\tcp = newcp;\n\t\t\t\tcontinue;\t/* canonicalize the link */\n\t\t\t}\n\t\t\t*sp = '/';\n\t\t\tif (sp != cp)\n\t\t\t\twhile (*--sp != '/')\n\t\t\t\t\t;\n\t\t\tif (slash) {\n\t\t\t\tfor (p1 = sp + 1, p2 = p + 1; *p1++ = *p2++;)\n\t\t\t\t\t;\n\t\t\t\tp = sp;\n\t\t\t} else if (cp == sp)\n\t\t\t\t*++sp = '\\0';\n\t\t\telse\n\t\t\t\t*sp = '\\0';\n\t\t} else if (slash)\n\t\t\t*p = '/';\n\t}\n\treturn cp;\n}\n\n/*\n * dnewcwd - make a new directory in the loop the current one\n */\ndnewcwd(dp)\n\tregister struct directory *dp;\n{\n\n\tdcwd = dp;\n\tset(\"cwd\", savestr(dcwd->di_name));\n\tif (printd)\n\t\tdodirs(fakev);\n}\n"
  },
  {
    "path": "bin/csh/sh.dir.h",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)sh.dir.h\t5.2 (Berkeley) 6/6/85\n */\n\n/*\n * Structure for entries in directory stack.\n */\nstruct\tdirectory\t{\n\tstruct\tdirectory *di_next;\t/* next in loop */\n\tstruct\tdirectory *di_prev;\t/* prev in loop */\n\tunsigned short *di_count;\t/* refcount of processes */\n\tchar\t*di_name;\t\t/* actual name */\n};\nstruct directory *dcwd;\t\t/* the one we are in now */\n"
  },
  {
    "path": "bin/csh/sh.dol.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if\t!defined(lint) && defined(DOSCCS)\nstatic char *sccsid = \"@(#)sh.dol.c\t5.3 (Berkeley) 3/29/86\";\n#endif\n\n#include \"sh.h\"\n\n/*\n * C shell\n */\n\n/*\n * These routines perform variable substitution and quoting via ' and \".\n * To this point these constructs have been preserved in the divided\n * input words.  Here we expand variables and turn quoting via ' and \" into\n * QUOTE bits on characters (which prevent further interpretation).\n * If the `:q' modifier was applied during history expansion, then\n * some QUOTEing may have occurred already, so we dont \"trim()\" here.\n */\n\nint\tDpeekc, Dpeekrd;\t\t/* Peeks for DgetC and Dreadc */\nchar\t*Dcp, **Dvp;\t\t\t/* Input vector for Dreadc */\n\n#define\tDEOF\t-1\n\n#define\tunDgetC(c)\tDpeekc = c\n\n#define QUOTES\t\t(_Q|_Q1|_ESC)\t/* \\ ' \" ` */\n\n/*\n * The following variables give the information about the current\n * $ expansion, recording the current word position, the remaining\n * words within this expansion, the count of remaining words, and the\n * information about any : modifier which is being applied.\n */\nchar\t*dolp;\t\t\t/* Remaining chars from this word */\nchar\t**dolnxt;\t\t/* Further words */\nint\tdolcnt;\t\t\t/* Count of further words */\nchar\tdolmod;\t\t\t/* : modifier character */\nint\tdolmcnt;\t\t/* :gx -> 10000, else 1 */\n\n/*\n * Fix up the $ expansions and quotations in the\n * argument list to command t.\n */\nDfix(t)\n\tregister struct command *t;\n{\n\tregister char **pp;\n\tregister char *p;\n\n\tif (noexec)\n\t\treturn;\n\t/* Note that t_dcom isn't trimmed thus !...:q's aren't lost */\n\tfor (pp = t->t_dcom; p = *pp++;)\n\t\twhile (*p)\n\t\t\tif (cmap(*p++, _DOL|QUOTES)) {\t/* $, \\, ', \", ` */\n\t\t\t\tDfix2(t->t_dcom);\t/* found one */\n\t\t\t\tblkfree(t->t_dcom);\n\t\t\t\tt->t_dcom = gargv;\n\t\t\t\tgargv = 0;\n\t\t\t\treturn;\n\t\t\t}\n}\n\n/*\n * $ substitute one word, for i/o redirection\n */\nchar *\nDfix1(cp)\n\tregister char *cp;\n{\n\tchar *Dv[2];\n\n\tif (noexec)\n\t\treturn (0);\n\tDv[0] = cp; Dv[1] = NOSTR;\n\tDfix2(Dv);\n\tif (gargc != 1) {\n\t\tsetname(cp);\n\t\tbferr(\"Ambiguous\");\n\t}\n\tcp = savestr(gargv[0]);\n\tblkfree(gargv), gargv = 0;\n\treturn (cp);\n}\n\n/*\n * Subroutine to do actual fixing after state initialization.\n */\nDfix2(v)\n\tchar **v;\n{\n\tchar *agargv[GAVSIZ];\n\n\tginit(agargv);\t\t\t/* Initialize glob's area pointers */\n\tDvp = v; Dcp = \"\";\t\t/* Setup input vector for Dreadc */\n\tunDgetC(0); unDredc(0);\t\t/* Clear out any old peeks (at error) */\n\tdolp = 0; dolcnt = 0;\t\t/* Clear out residual $ expands (...) */\n\twhile (Dword())\n\t\tcontinue;\n\tgargv = copyblk(gargv);\n}\n\n/*\n * Get a word.  This routine is analogous to the routine\n * word() in sh.lex.c for the main lexical input.  One difference\n * here is that we don't get a newline to terminate our expansion.\n * Rather, DgetC will return a DEOF when we hit the end-of-input.\n */\nDword()\n{\n\tregister int c, c1;\n\tchar wbuf[BUFSIZ];\n\tregister char *wp = wbuf;\n\tregister int i = BUFSIZ - 4;\n\tregister bool dolflg;\n\tbool sofar = 0;\n\nloop:\n\tc = DgetC(DODOL);\n\tswitch (c) {\n\n\tcase DEOF:\ndeof:\n\t\tif (sofar == 0)\n\t\t\treturn (0);\n\t\t/* finish this word and catch the code above the next time */\n\t\tunDredc(c);\n\t\t/* fall into ... */\n\n\tcase '\\n':\n\t\t*wp = 0;\n\t\tgoto ret;\n\n\tcase ' ':\n\tcase '\\t':\n\t\tgoto loop;\n\n\tcase '`':\n\t\t/* We preserve ` quotations which are done yet later */\n\t\t*wp++ = c, --i;\n\tcase '\\'':\n\tcase '\"':\n\t\t/*\n\t\t * Note that DgetC never returns a QUOTES character\n\t\t * from an expansion, so only true input quotes will\n\t\t * get us here or out.\n\t\t */\n\t\tc1 = c;\n\t\tdolflg = c1 == '\"' ? DODOL : 0;\n\t\tfor (;;) {\n\t\t\tc = DgetC(dolflg);\n\t\t\tif (c == c1)\n\t\t\t\tbreak;\n\t\t\tif (c == '\\n' || c == DEOF)\n\t\t\t\terror(\"Unmatched %c\", c1);\n\t\t\tif ((c & (QUOTE|TRIM)) == ('\\n' | QUOTE))\n\t\t\t\t--wp, ++i;\n\t\t\tif (--i <= 0)\n\t\t\t\tgoto toochars;\n\t\t\tswitch (c1) {\n\n\t\t\tcase '\"':\n\t\t\t\t/*\n\t\t\t\t * Leave any `s alone for later.\n\t\t\t\t * Other chars are all quoted, thus `...`\n\t\t\t\t * can tell it was within \"...\".\n\t\t\t\t */\n\t\t\t\t*wp++ = c == '`' ? '`' : c | QUOTE;\n\t\t\t\tbreak;\n\n\t\t\tcase '\\'':\n\t\t\t\t/* Prevent all further interpretation */\n\t\t\t\t*wp++ = c | QUOTE;\n\t\t\t\tbreak;\n\n\t\t\tcase '`':\n\t\t\t\t/* Leave all text alone for later */\n\t\t\t\t*wp++ = c;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (c1 == '`')\n\t\t\t*wp++ = '`', --i;\n\t\tgoto pack;\t\t/* continue the word */\n\n\tcase '\\\\':\n\t\tc = DgetC(0);\t\t/* No $ subst! */\n\t\tif (c == '\\n' || c == DEOF)\n\t\t\tgoto loop;\n\t\tc |= QUOTE;\n\t\tbreak;\n\t}\n\tunDgetC(c);\npack:\n\tsofar = 1;\n\t/* pack up more characters in this word */\n\tfor (;;) {\n\t\tc = DgetC(DODOL);\n\t\tif (c == '\\\\') {\n\t\t\tc = DgetC(0);\n\t\t\tif (c == DEOF)\n\t\t\t\tgoto deof;\n\t\t\tif (c == '\\n')\n\t\t\t\tc = ' ';\n\t\t\telse\n\t\t\t\tc |= QUOTE;\n\t\t}\n\t\tif (c == DEOF)\n\t\t\tgoto deof;\n\t\tif (cmap(c, _SP|_NL|_Q|_Q1)) {\t\t/* sp \\t\\n'\"` */\n\t\t\tunDgetC(c);\n\t\t\tif (cmap(c, QUOTES))\n\t\t\t\tgoto loop;\n\t\t\t*wp++ = 0;\n\t\t\tgoto ret;\n\t\t}\n\t\tif (--i <= 0)\ntoochars:\n\t\t\terror(\"Word too long\");\n\t\t*wp++ = c;\n\t}\nret:\n\tGcat(\"\", wbuf);\n\treturn (1);\n}\n\n/*\n * Get a character, performing $ substitution unless flag is 0.\n * Any QUOTES character which is returned from a $ expansion is\n * QUOTEd so that it will not be recognized above.\n */\nDgetC(flag)\n\tregister int flag;\n{\n\tregister int c;\n\ntop:\n\tif (c = Dpeekc) {\n\t\tDpeekc = 0;\n\t\treturn (c);\n\t}\n\tif (lap) {\n\t\tc = *lap++ & (QUOTE|TRIM);\n\t\tif (c == 0) {\n\t\t\tlap = 0;\n\t\t\tgoto top;\n\t\t}\nquotspec:\n\t\tif (cmap(c, QUOTES))\n\t\t\treturn (c | QUOTE);\n\t\treturn (c);\n\t}\n\tif (dolp) {\n\t\tif (c = *dolp++ & (QUOTE|TRIM))\n\t\t\tgoto quotspec;\n\t\tif (dolcnt > 0) {\n\t\t\tsetDolp(*dolnxt++);\n\t\t\t--dolcnt;\n\t\t\treturn (' ');\n\t\t}\n\t\tdolp = 0;\n\t}\n\tif (dolcnt > 0) {\n\t\tsetDolp(*dolnxt++);\n\t\t--dolcnt;\n\t\tgoto top;\n\t}\n\tc = Dredc();\n\tif (c == '$' && flag) {\n\t\tDgetdol();\n\t\tgoto top;\n\t}\n\treturn (c);\n}\n\nchar\t*nulvec[] = { 0 };\nstruct\tvarent nulargv = { nulvec, \"argv\", 0 };\n\n/*\n * Handle the multitudinous $ expansion forms.\n * Ugh.\n */\nDgetdol()\n{\n\tregister char *np;\n\tregister struct varent *vp;\n\tchar name[20];\n\tint c, sc;\n\tint subscr = 0, lwb = 1, upb = 0;\n\tbool dimen = 0, bitset = 0;\n\tchar wbuf[BUFSIZ];\n\n\tdolmod = dolmcnt = 0;\n\tc = sc = DgetC(0);\n\tif (c == '{')\n\t\tc = DgetC(0);\t\t/* sc is { to take } later */\n\tif ((c & TRIM) == '#')\n\t\tdimen++, c = DgetC(0);\t\t/* $# takes dimension */\n\telse if (c == '?')\n\t\tbitset++, c = DgetC(0);\t\t/* $? tests existence */\n\tswitch (c) {\n\n\tcase '$':\n\t\tif (dimen || bitset)\n\t\t\tgoto syntax;\t\t/* No $?$, $#$ */\n\t\tsetDolp(doldol);\n\t\tgoto eatbrac;\n\n\tcase '<'|QUOTE:\n\t\tif (dimen || bitset)\n\t\t\tgoto syntax;\t\t/* No $?<, $#< */\n\t\tfor (np = wbuf; read(OLDSTD, np, 1) == 1; np++) {\n\t\t\tif (np >= &wbuf[BUFSIZ-1])\n\t\t\t\terror(\"$< line too long\");\n\t\t\tif (*np <= 0 || *np == '\\n')\n\t\t\t\tbreak;\n\t\t}\n\t\t*np = 0;\n\t\t/*\n\t\t * KLUDGE: dolmod is set here because it will\n\t\t * cause setDolp to call domod and thus to copy wbuf.\n\t\t * Otherwise setDolp would use it directly. If we saved\n\t\t * it ourselves, no one would know when to free it.\n\t\t * The actual function of the 'q' causes filename\n\t\t * expansion not to be done on the interpolated value.\n\t\t */\n\t\tdolmod = 'q';\n\t\tdolmcnt = 10000;\n\t\tsetDolp(wbuf);\n\t\tgoto eatbrac;\n\n\tcase DEOF:\n\tcase '\\n':\n\t\tgoto syntax;\n\n\tcase '*':\n\t\t(void) strcpy(name, \"argv\");\n\t\tvp = adrof(\"argv\");\n\t\tsubscr = -1;\t\t\t/* Prevent eating [...] */\n\t\tbreak;\n\n\tdefault:\n\t\tnp = name;\n\t\tif (digit(c)) {\n\t\t\tif (dimen)\n\t\t\t\tgoto syntax;\t/* No $#1, e.g. */\n\t\t\tsubscr = 0;\n\t\t\tdo {\n\t\t\t\tsubscr = subscr * 10 + c - '0';\n\t\t\t\tc = DgetC(0);\n\t\t\t} while (digit(c));\n\t\t\tunDredc(c);\n\t\t\tif (subscr < 0)\n\t\t\t\tgoto oob;\n\t\t\tif (subscr == 0) {\n\t\t\t\tif (bitset) {\n\t\t\t\t\tdolp = file ? \"1\" : \"0\";\n\t\t\t\t\tgoto eatbrac;\n\t\t\t\t}\n\t\t\t\tif (file == 0)\n\t\t\t\t\terror(\"No file for $0\");\n\t\t\t\tsetDolp(file);\n\t\t\t\tgoto eatbrac;\n\t\t\t}\n\t\t\tif (bitset)\n\t\t\t\tgoto syntax;\n\t\t\tvp = adrof(\"argv\");\n\t\t\tif (vp == 0) {\n\t\t\t\tvp = &nulargv;\n\t\t\t\tgoto eatmod;\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t\tif (!alnum(c))\n\t\t\tgoto syntax;\n\t\tfor (;;) {\n\t\t\t*np++ = c;\n\t\t\tc = DgetC(0);\n\t\t\tif (!alnum(c))\n\t\t\t\tbreak;\n\t\t\tif (np >= &name[sizeof name - 2])\nsyntax:\n\t\t\t\terror(\"Variable syntax\");\n\t\t}\n\t\t*np++ = 0;\n\t\tunDredc(c);\n\t\tvp = adrof(name);\n\t}\n\tif (bitset) {\n\t\tdolp = (vp || getenv(name)) ? \"1\" : \"0\";\n\t\tgoto eatbrac;\n\t}\n\tif (vp == 0) {\n\t\tnp = getenv(name);\n\t\tif (np) {\n\t\t\taddla(np);\n\t\t\tgoto eatbrac;\n\t\t}\n\t\tudvar(name);\n\t\t/*NOTREACHED*/\n\t}\n\tc = DgetC(0);\n\tupb = blklen(vp->vec);\n\tif (dimen == 0 && subscr == 0 && c == '[') {\n\t\tnp = name;\n\t\tfor (;;) {\n\t\t\tc = DgetC(DODOL);\t/* Allow $ expand within [ ] */\n\t\t\tif (c == ']')\n\t\t\t\tbreak;\n\t\t\tif (c == '\\n' || c == DEOF)\n\t\t\t\tgoto syntax;\n\t\t\tif (np >= &name[sizeof name - 2])\n\t\t\t\tgoto syntax;\n\t\t\t*np++ = c;\n\t\t}\n\t\t*np = 0, np = name;\n\t\tif (dolp || dolcnt)\t\t/* $ exp must end before ] */\n\t\t\tgoto syntax;\n\t\tif (!*np)\n\t\t\tgoto syntax;\n\t\tif (digit(*np)) {\n\t\t\tregister int i = 0;\n\n\t\t\twhile (digit(*np))\n\t\t\t\ti = i * 10 + *np++ - '0';\n\t\t\tif ((i < 0 || i > upb) && !any(*np, \"-*\")) {\noob:\n\t\t\t\tsetname(vp->v_name);\n\t\t\t\terror(\"Subscript out of range\");\n\t\t\t}\n\t\t\tlwb = i;\n\t\t\tif (!*np)\n\t\t\t\tupb = lwb, np = \"*\";\n\t\t}\n\t\tif (*np == '*')\n\t\t\tnp++;\n\t\telse if (*np != '-')\n\t\t\tgoto syntax;\n\t\telse {\n\t\t\tregister int i = upb;\n\n\t\t\tnp++;\n\t\t\tif (digit(*np)) {\n\t\t\t\ti = 0;\n\t\t\t\twhile (digit(*np))\n\t\t\t\t\ti = i * 10 + *np++ - '0';\n\t\t\t\tif (i < 0 || i > upb)\n\t\t\t\t\tgoto oob;\n\t\t\t}\n\t\t\tif (i < lwb)\n\t\t\t\tupb = lwb - 1;\n\t\t\telse\n\t\t\t\tupb = i;\n\t\t}\n\t\tif (lwb == 0) {\n\t\t\tif (upb != 0)\n\t\t\t\tgoto oob;\n\t\t\tupb = -1;\n\t\t}\n\t\tif (*np)\n\t\t\tgoto syntax;\n\t} else {\n\t\tif (subscr > 0)\n\t\t\tif (subscr > upb)\n\t\t\t\tlwb = 1, upb = 0;\n\t\t\telse\n\t\t\t\tlwb = upb = subscr;\n\t\tunDredc(c);\n\t}\n\tif (dimen) {\n\t\tchar *cp = putn(upb - lwb + 1);\n\n\t\taddla(cp);\n\t\txfree(cp);\n\t} else {\neatmod:\n\t\tc = DgetC(0);\n\t\tif (c == ':') {\n\t\t\tc = DgetC(0), dolmcnt = 1;\n\t\t\tif (c == 'g')\n\t\t\t\tc = DgetC(0), dolmcnt = 10000;\n\t\t\tif (!any(c, \"htrqxe\"))\n\t\t\t\terror(\"Bad : mod in $\");\n\t\t\tdolmod = c;\n\t\t\tif (c == 'q')\n\t\t\t\tdolmcnt = 10000;\n\t\t} else\n\t\t\tunDredc(c);\n\t\tdolnxt = &vp->vec[lwb - 1];\n\t\tdolcnt = upb - lwb + 1;\n\t}\neatbrac:\n\tif (sc == '{') {\n\t\tc = Dredc();\n\t\tif (c != '}')\n\t\t\tgoto syntax;\n\t}\n}\n\nsetDolp(cp)\n\tregister char *cp;\n{\n\tregister char *dp;\n\n\tif (dolmod == 0 || dolmcnt == 0) {\n\t\tdolp = cp;\n\t\treturn;\n\t}\n\tdp = domod(cp, dolmod);\n\tif (dp) {\n\t\tdolmcnt--;\n\t\taddla(dp);\n\t\txfree(dp);\n\t} else\n\t\taddla(cp);\n\tdolp = \"\";\n}\n\nunDredc(c)\n\tint c;\n{\n\n\tDpeekrd = c;\n}\n\nDredc()\n{\n\tregister int c;\n\n\tif (c = Dpeekrd) {\n\t\tDpeekrd = 0;\n\t\treturn (c);\n\t}\n\tif (Dcp && (c = *Dcp++))\n\t\treturn (c&(QUOTE|TRIM));\n\tif (*Dvp == 0) {\n\t\tDcp = 0;\n\t\treturn (DEOF);\n\t}\n\tDcp = *Dvp++;\n\treturn (' ');\n}\n\nDtestq(c)\n\tregister int c;\n{\n\n\tif (cmap(c, QUOTES))\n\t\tgflag = 1;\n}\n\n/*\n * Form a shell temporary file (in unit 0) from the words\n * of the shell input up to a line the same as \"term\".\n * Unit 0 should have been closed before this call.\n */\nheredoc(term)\n\tchar *term;\n{\n\tregister int c;\n\tchar *Dv[2];\n\tchar obuf[BUFSIZ], lbuf[BUFSIZ], mbuf[BUFSIZ];\n\tint ocnt, lcnt, mcnt;\n\tregister char *lbp, *obp, *mbp;\n\tchar **vp;\n\tbool quoted;\n\n\tif (creat(shtemp, 0600) < 0)\n\t\tPerror(shtemp);\n\t(void) close(0);\n\tif (open(shtemp, 2) < 0) {\n\t\tint oerrno = errno;\n\n\t\t(void) unlink(shtemp);\n\t\terrno = oerrno;\n\t\tPerror(shtemp);\n\t}\n\t(void) unlink(shtemp);\t\t\t/* 0 0 inode! */\n\tDv[0] = term; Dv[1] = NOSTR; gflag = 0;\n\ttrim(Dv); rscan(Dv, Dtestq); quoted = gflag;\n\tocnt = BUFSIZ; obp = obuf;\n\tfor (;;) {\n\t\t/*\n\t\t * Read up a line\n\t\t */\n\t\tlbp = lbuf; lcnt = BUFSIZ - 4;\n\t\tfor (;;) {\n\t\t\tc = readc(1);\t\t/* 1 -> Want EOF returns */\n\t\t\tif (c < 0) {\n\t\t\t\tsetname(term);\n\t\t\t\tbferr(\"<< terminator not found\");\n\t\t\t}\n\t\t\tif (c == '\\n')\n\t\t\t\tbreak;\n\t\t\tif (c &= TRIM) {\n\t\t\t\t*lbp++ = c;\n\t\t\t\tif (--lcnt < 0) {\n\t\t\t\t\tsetname(\"<<\");\n\t\t\t\t\terror(\"Line overflow\");\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\t*lbp = 0;\n\n\t\t/*\n\t\t * Compare to terminator -- before expansion\n\t\t */\n\t\tif (eq(lbuf, term)) {\n\t\t\tif (write(0, obuf, BUFSIZ - ocnt) < 0)\n\t\t\t        ;\n\t\t\t(void) lseek(0, (off_t)0, 0);\n\t\t\treturn;\n\t\t}\n\n\t\t/*\n\t\t * If term was quoted or -n just pass it on\n\t\t */\n\t\tif (quoted || noexec) {\n\t\t\t*lbp++ = '\\n'; *lbp = 0;\n\t\t\tfor (lbp = lbuf; c = *lbp++;) {\n\t\t\t\t*obp++ = c;\n\t\t\t\tif (--ocnt == 0) {\n\t\t\t\t\tif (write(0, obuf, BUFSIZ) < 0)\n\t\t\t\t\t        ;\n\t\t\t\t\tobp = obuf; ocnt = BUFSIZ;\n\t\t\t\t}\n\t\t\t}\n\t\t\tcontinue;\n\t\t}\n\n\t\t/*\n\t\t * Term wasn't quoted so variable and then command\n\t\t * expand the input line\n\t\t */\n\t\tDcp = lbuf; Dvp = Dv + 1; mbp = mbuf; mcnt = BUFSIZ - 4;\n\t\tfor (;;) {\n\t\t\tc = DgetC(DODOL);\n\t\t\tif (c == DEOF)\n\t\t\t\tbreak;\n\t\t\tif ((c &= TRIM) == 0)\n\t\t\t\tcontinue;\n\t\t\t/* \\ quotes \\ $ ` here */\n\t\t\tif (c =='\\\\') {\n\t\t\t\tc = DgetC(0);\n\t\t\t\tif (!any(c, \"$\\\\`\"))\n\t\t\t\t\tunDgetC(c | QUOTE), c = '\\\\';\n\t\t\t\telse\n\t\t\t\t\tc |= QUOTE;\n\t\t\t}\n\t\t\t*mbp++ = c;\n\t\t\tif (--mcnt == 0) {\n\t\t\t\tsetname(\"<<\");\n\t\t\t\tbferr(\"Line overflow\");\n\t\t\t}\n\t\t}\n\t\t*mbp++ = 0;\n\n\t\t/*\n\t\t * If any ` in line do command substitution\n\t\t */\n\t\tmbp = mbuf;\n\t\tif (any('`', mbp)) {\n\t\t\t/*\n\t\t\t * 1 arg to dobackp causes substitution to be literal.\n\t\t\t * Words are broken only at newlines so that all blanks\n\t\t\t * and tabs are preserved.  Blank lines (null words)\n\t\t\t * are not discarded.\n\t\t\t */\n\t\t\tvp = dobackp(mbuf, 1);\n\t\t} else\n\t\t\t/* Setup trivial vector similar to return of dobackp */\n\t\t\tDv[0] = mbp, Dv[1] = NOSTR, vp = Dv;\n\n\t\t/*\n\t\t * Resurrect the words from the command substitution\n\t\t * each separated by a newline.  Note that the last\n\t\t * newline of a command substitution will have been\n\t\t * discarded, but we put a newline after the last word\n\t\t * because this represents the newline after the last\n\t\t * input line!\n\t\t */\n\t\tfor (; *vp; vp++) {\n\t\t\tfor (mbp = *vp; *mbp; mbp++) {\n\t\t\t\t*obp++ = *mbp & TRIM;\n\t\t\t\tif (--ocnt == 0) {\n\t\t\t\t\tif (write(0, obuf, BUFSIZ) < 0)\n                                                ;\n\t\t\t\t\tobp = obuf; ocnt = BUFSIZ;\n\t\t\t\t}\n\t\t\t}\n\t\t\t*obp++ = '\\n';\n\t\t\tif (--ocnt == 0) {\n\t\t\t\tif (write(0, obuf, BUFSIZ) < 0)\n\t\t\t\t        ;\n\t\t\t\tobp = obuf; ocnt = BUFSIZ;\n\t\t\t}\n\t\t}\n\t\tif (pargv)\n\t\t\tblkfree(pargv), pargv = 0;\n\t}\n}\n"
  },
  {
    "path": "bin/csh/sh.err.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"sh.h\"\n#include <sys/ioctl.h>\n\n/*\n * C Shell\n */\n\nbool\terrspl;\t\t\t/* Argument to error was spliced by seterr2 */\nchar\tone[2] = { '1', 0 };\nchar\t*onev[2] = { one, NOSTR };\n/*\n * Print error string s with optional argument arg.\n * This routine always resets or exits.  The flag haderr\n * is set so the routine who catches the unwind can propogate\n * it if they want.\n *\n * Note that any open files at the point of error will eventually\n * be closed in the routine process in sh.c which is the only\n * place error unwinds are ever caught.\n */\n/*VARARGS1*/\nerror(s, arg)\n\tchar *s;\n{\n\tregister char **v;\n\tregister char *ep;\n\n\t/*\n\t * Must flush before we print as we wish output before the error\n\t * to go on (some form of) standard output, while output after\n\t * goes on (some form of) diagnostic output.\n\t * If didfds then output will go to 1/2 else to FSHOUT/FSHDIAG.\n\t * See flush in sh.print.c.\n\t */\n\tflush();\n\thaderr = 1;\t\t/* Now to diagnostic output */\n\ttimflg = 0;\t\t/* This isn't otherwise reset */\n\tif (v = pargv)\n\t\tpargv = 0, blkfree(v);\n\tif (v = gargv)\n\t\tgargv = 0, blkfree(v);\n\n\t/*\n\t * A zero arguments causes no printing, else print\n\t * an error diagnostic here.\n\t */\n\tif (s)\n\t\tprintf(s, arg), printf(\".\\n\");\n\n\tdidfds = 0;\t\t/* Forget about 0,1,2 */\n\tif ((ep = parserr) && errspl) {\n\t\terrspl = 0;\n\t\txfree(ep);\n\t}\n\terrspl = 0;\n\n\t/*\n\t * Go away if -e or we are a child shell\n\t */\n\tif (exiterr || child)\n\t\texit(1);\n\n\t/*\n\t * Reset the state of the input.\n\t * This buffered seek to end of file will also\n\t * clear the while/foreach stack.\n\t */\n\tbtoeof();\n\n\tsetq(\"status\", onev, &shvhed);\n\tif (tpgrp > 0)\n\t\t(void) ioctl(FSHTTY, TIOCSPGRP, (char *)&tpgrp);\n\treset();\t\t/* Unwind */\n}\n\n/*\n * Perror is the shells version of perror which should otherwise\n * never be called.\n */\nPerror(s)\n\tchar *s;\n{\n\n\t/*\n\t * Perror uses unit 2, thus if we didn't set up the fd's\n\t * we must set up unit 2 now else the diagnostic will disappear\n\t */\n\tif (!didfds) {\n\t\tregister int oerrno = errno;\n\n\t\t(void) dcopy(SHDIAG, 2);\n\t\terrno = oerrno;\n\t}\n\tperror(s);\n\terror(NOSTR);\t\t/* To exit or unwind */\n}\n\nbferr(cp)\n\tchar *cp;\n{\n\n\tflush();\n\thaderr = 1;\n\tprintf(\"%s: \", bname);\n\terror(cp);\n}\n\n/*\n * The parser and scanner set up errors for later by calling seterr,\n * which sets the variable parserr as a side effect; later to be tested,\n * e.g. in process.\n */\nseterr(s)\n\tchar *s;\n{\n\tif (parserr == 0)\n\t\tparserr = s, errspl = 0;\n}\n\n/* Set parserr to a splice of cp and dp, to be freed later in error() */\nseterr2(cp, dp)\n\tchar *cp, *dp;\n{\n\tif (parserr)\n\t\treturn;\n\tparserr = strspl(cp, dp);\n\terrspl++;\n}\n\n/* Set parserr to a splice of cp with a string form of character d */\nseterrc(cp, d)\n\tchar *cp, d;\n{\n\tchar chbuf[2];\n\n\tchbuf[0] = d;\n\tchbuf[1] = 0;\n\tseterr2(cp, chbuf);\n}\n"
  },
  {
    "path": "bin/csh/sh.exec.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if\t!defined(lint) && defined(DOSCCS)\nstatic char *sccsid = \"@(#)sh.exec.c\t5.2.2 (2.11BSD) 1996/9/20\";\n#endif\n\n#include \"sh.h\"\n#include <string.h>\n#include <sys/dir.h>\n\n/*\n * C shell\n */\n\n/*\n * System level search and execute of a command.\n * We look in each directory for the specified command name.\n * If the name contains a '/' then we execute only the full path name.\n * If there is no search path then we execute only full path names.\n */\n\n/*\n * As we search for the command we note the first non-trivial error\n * message for presentation to the user.  This allows us often\n * to show that a file has the wrong mode/no access when the file\n * is not in the last component of the search path, so we must\n * go on after first detecting the error.\n */\nconst char *exerr;\t\t/* Execution error message */\nchar\t*expath;\t\t/* Path for exerr */\n\n#include \"sh.exec.h\"\n\n/* Dummy search path for just absolute search when no path */\nchar\t*justabs[] =\t{ \"\", 0 };\n\ndoexec(t)\n\tregister struct command *t;\n{\n\tchar *sav;\n\tregister char *dp, **pv, **av;\n\tregister struct varent *v;\n\tbool slash = any('/', t->t_dcom[0]);\n\tint hashval, hashval1, i;\n\tchar *blk[2];\n\n\t/*\n\t * Glob the command name.  If this does anything, then we\n\t * will execute the command only relative to \".\".  One special\n\t * case: if there is no PATH, then we execute only commands\n\t * which start with '/'.\n\t */\n\tdp = globone(t->t_dcom[0]);\n\tsav = t->t_dcom[0];\n\texerr = 0;\n        expath = t->t_dcom[0] = dp;\n\txfree(sav);\n\tv = adrof(\"path\");\n\tif (v == 0 && expath[0] != '/')\n\t\tpexerr();\n\tslash |= gflag;\n\n\t/*\n\t * Glob the argument list, if necessary.\n\t * Otherwise trim off the quote bits.\n\t */\n\tgflag = 0; av = &t->t_dcom[1];\n\ttglob(av);\n\tif (gflag) {\n\t\tav = glob(av);\n\t\tif (av == 0)\n\t\t\terror(\"No match\");\n\t}\n\tblk[0] = t->t_dcom[0];\n\tblk[1] = 0;\n\tav = blkspl(blk, av);\n#ifdef VFORK\n\tVav = av;\n#endif\n\ttrim(av);\n\n\txechoit(av);\t\t/* Echo command if -x */\n\t/*\n\t * Since all internal file descriptors are set to close on exec,\n\t * we don't need to close them explicitly here.  Just reorient\n\t * ourselves for error messages.\n\t */\n\tSHIN = 0; SHOUT = 1; SHDIAG = 2; OLDSTD = 0;\n\n\t/*\n\t * We must do this AFTER any possible forking (like `foo`\n\t * in glob) so that this shell can still do subprocesses.\n\t */\n\t(void) sigsetmask(0L);\n\n\t/*\n\t * If no path, no words in path, or a / in the filename\n\t * then restrict the command search.\n\t */\n\tif (v == 0 || v->vec[0] == 0 || slash)\n\t\tpv = justabs;\n\telse\n\t\tpv = v->vec;\n\tsav = strspl(\"/\", *av);\t\t/* / command name for postpending */\n#ifdef VFORK\n\tVsav = sav;\n#endif\n\tif (havhash)\n\t\thashval = hashname(*av);\n\ti = 0;\n#ifdef VFORK\n\thits++;\n#endif\n\tdo {\n\t\tif (!slash && pv[0][0] == '/' && havhash) {\n\t\t\thashval1 = hash(hashval, i);\n\t\t\tif (!bit(xhash, hashval1))\n\t\t\t\tgoto cont;\n\t\t}\n\t\tif (pv[0][0] == 0 || eq(pv[0], \".\"))\t/* don't make ./xxx */\n\t\t\ttexec(*av, av);\n\t\telse {\n\t\t\tdp = strspl(*pv, sav);\n#ifdef VFORK\n\t\t\tVdp = dp;\n#endif\n\t\t\ttexec(dp, av);\n#ifdef VFORK\n\t\t\tVdp = 0;\n#endif\n\t\t\txfree(dp);\n\t\t}\n#ifdef VFORK\n\t\tmisses++;\n#endif\ncont:\n\t\tpv++;\n\t\ti++;\n\t} while (*pv);\n#ifdef VFORK\n\thits--;\n#endif\n#ifdef VFORK\n\tVsav = 0;\n\tVav = 0;\n#endif\n\txfree(sav);\n\txfree((char *)av);\n\tpexerr();\n}\n\npexerr()\n{\n\t/* Couldn't find the damn thing */\n\tsetname(expath);\n\t/* xfree(expath); */\n\tif (exerr)\n\t\tbferr(exerr);\n\tbferr(\"Command not found\");\n}\n\n/*\n * Execute command f, arg list t.\n * Record error message if not found.\n * Also do shell scripts here.\n */\ntexec(f, t)\n\tchar *f;\n\tregister char **t;\n{\n\tregister struct varent *v;\n\tregister char **vp;\n\tchar *lastsh[2];\n\n\texecv(f, t);\n\tswitch (errno) {\n\n\tcase ENOEXEC:\n\t\t/*\n\t\t * If there is an alias for shell, then\n\t\t * put the words of the alias in front of the\n\t\t * argument list replacing the command name.\n\t\t * Note no interpretation of the words at this point.\n\t\t */\n\t\tv = adrof1(\"shell\", &aliases);\n\t\tif (v == 0) {\n#ifdef OTHERSH\n\t\t\tregister int ff = open(f, 0);\n\t\t\tchar ch;\n#endif\n\n\t\t\tvp = lastsh;\n\t\t\tvp[0] = adrof(\"shell\") ? value(\"shell\") : SHELLPATH;\n\t\t\tvp[1] = (char *) NULL;\n#ifdef OTHERSH\n\t\t\tif (ff != -1 && read(ff, &ch, 1) == 1 && ch != '#')\n\t\t\t\tvp[0] = OTHERSH;\n\t\t\t(void) close(ff);\n#endif\n\t\t} else\n\t\t\tvp = v->vec;\n\t\tt[0] = f;\n\t\tt = blkspl(vp, t);\t\t/* Splice up the new arglst */\n\t\tf = *t;\n\t\txfree((char *)t);\n\t\texecv(f, t);\n\t\t/* The sky is falling, the sky is falling! */\n\n\tcase ENOMEM:\n\t\tPerror(f);\n\n\tcase ENOENT:\n\t\tbreak;\n\n\tdefault:\n\t\tif (exerr == 0) {\n\t\t\texerr = strerror(errno);\n\t\t\texpath = savestr(f);\n\t\t}\n\t}\n}\n\n/*ARGSUSED*/\nexecash(t, kp)\n\tchar **t;\n\tregister struct command *kp;\n{\n\n\trechist();\n\t(void) signal(SIGINT, parintr);\n\t(void) signal(SIGQUIT, parintr);\n\t(void) signal(SIGTERM, parterm);\t/* if doexec loses, screw */\n\tlshift(kp->t_dcom, 1);\n\texiterr++;\n\tdoexec(kp);\n\t/*NOTREACHED*/\n}\n\nxechoit(t)\n\tchar **t;\n{\n\n\tif (adrof(\"echo\")) {\n\t\tflush();\n\t\thaderr = 1;\n\t\tblkpr(t), putchar('\\n');\n\t\thaderr = 0;\n\t}\n}\n\n/*VARARGS0*//*ARGSUSED*/\nint dohash()\n{\n\tstruct stat stb;\n\tDIR *dirp;\n\tregister struct direct *dp;\n\tregister int cnt;\n\tint i = 0;\n\tstruct varent *v = adrof(\"path\");\n\tchar **pv;\n\tint hashval;\n\n\thavhash = 1;\n\tfor (cnt = 0; cnt < sizeof xhash; cnt++)\n\t\txhash[cnt] = 0;\n\tif (v == 0)\n\t\treturn 0;\n\tfor (pv = v->vec; *pv; pv++, i++) {\n\t\tif (pv[0][0] != '/')\n\t\t\tcontinue;\nprintf (\"dohash: %s\\n\", *pv);\n\t\tif (stat(*pv, &stb) < 0) {\nprintf (\"    ---cannot stat dir %s: %s\\n\", *pv, strerror(errno));\n\t\t\tcontinue;\n\t\t}\n                if (! S_ISDIR(stb.st_mode)) {\nprintf (\"    ---not a directory %s, mode = %#o\\n\", *pv, stb.st_mode);\n\t\t\tcontinue;\n                }\n\t\tdirp = opendir(*pv);\n\t\tif (dirp == NULL) {\nprintf (\"    ---cannot open dir %s\\n\", *pv);\n\t\t\tcontinue;\n                }\n\t\twhile ((dp = readdir(dirp)) != NULL) {\n\t\t\tif (dp->d_ino == 0)\n\t\t\t\tcontinue;\n\t\t\tif (dp->d_name[0] == '.' &&\n\t\t\t    (dp->d_name[1] == '\\0' ||\n\t\t\t     dp->d_name[1] == '.' && dp->d_name[2] == '\\0'))\n\t\t\t\tcontinue;\n\t\t\thashval = hash(hashname(dp->d_name), i);\n\t\t\tbis(xhash, hashval);\n\t\t}\n\t\tclosedir(dirp);\nprintf (\"    ---done %s\\n\", *pv);\n\t}\n\treturn 0;\n}\n\ndounhash()\n{\n\n\thavhash = 0;\n}\n\n#ifdef VFORK\nhashstat()\n{\n\n\tif (hits+misses)\n\t\tprintf(\"%d hits, %d misses, %d%%\\n\",\n\t\t\thits, misses,\n\t\t\t(int)(100L * hits / (hits + misses)));\n}\n#endif\n\n/*\n * Hash a command name.\n */\nhashname(cp)\n\tregister char *cp;\n{\n\tregister long h = 0;\n\n\twhile (*cp)\n\t\th = hash(h, *cp++);\n\treturn ((int) h);\n}\n"
  },
  {
    "path": "bin/csh/sh.exec.h",
    "content": "/*\n * Xhash is an array of HSHSIZ bits (HSHSIZ / 8 chars), which are used\n * to hash execs.  If it is allocated (havhash true), then to tell\n * whether ``name'' is (possibly) present in the i'th component\n * of the variable path, you look at the bit in xhash indexed by\n * hash(hashname(\"name\"), i).  This is setup automatically\n * after .login is executed, and recomputed whenever ``path'' is\n * changed.\n * The two part hash function is designed to let texec() call the\n * more expensive hashname() only once and the simple hash() several\n * times (once for each path component checked).\n * Byte size is assumed to be 8.\n */\n#define\tHSHSIZ\t\t8192\t\t\t/* 1k bytes */\n#define HSHMASK\t\t(HSHSIZ - 1)\n#define HSHMUL\t\t243\nchar\txhash[HSHSIZ / 8];\n#define hash(a, b)\t((a) * HSHMUL + (b) & HSHMASK)\n#define bit(h, b)\t((h)[(b) >> 3] & 1 << ((b) & 7))\t/* bit test */\n#define bis(h, b)\t((h)[(b) >> 3] |= 1 << ((b) & 7))\t/* bit set */\n#ifdef VFORK\nint\thits, misses;\n#endif\n"
  },
  {
    "path": "bin/csh/sh.exec2.c",
    "content": "/*\n * From the 4.4-Lite2 CD's csh sources and modified appropriately.\n*/\n#include \"sh.h\"\n#include <string.h>\n#include <sys/file.h>\n#include <sys/stat.h>\n#include <sys/dir.h>\n#include \"sh.exec.h\"\n\nextern\tchar\t*justabs[];\t/* in sh.exec.c */\n\n/* Also by:\n *  Andreas Luik <luik@isaak.isa.de>\n *  I S A  GmbH - Informationssysteme fuer computerintegrierte Automatisierung\n *  Azenberstr. 35\n *  D-7000 Stuttgart 1\n *  West-Germany\n * is the executable() routine below and changes to iscommand().\n * Thanks again!!\n */\n\n/*\n * executable() examines the pathname obtained by concatenating dir and name\n * (dir may be NULL), and returns 1 either if it is executable by us, or\n * if dir_ok is set and the pathname refers to a directory.\n * This is a bit kludgy, but in the name of optimization...\n */\nstatic int\nexecutable(dir, name, dir_ok)\n    char   *dir, *name;\n    bool    dir_ok;\n{\n    struct stat stbuf;\n    char    path[MAXPATHLEN + 1];\n    register char *dp, *sp;\n    char   *strname;\n\n    if (dir && *dir) {\n\tfor (dp = path, sp = dir; *sp; *dp++ = *sp++)\n\t    if (dp == &path[MAXPATHLEN + 1]) {\n\t\t*--dp = '\\0';\n\t\tbreak;\n\t    }\n\tfor (sp = name; *sp; *dp++ = *sp++)\n\t    if (dp == &path[MAXPATHLEN + 1]) {\n\t\t*--dp = '\\0';\n\t\tbreak;\n\t    }\n\t*dp = '\\0';\n\tstrname = path;\n    }\n    else\n\tstrname = name;\n    return (stat(strname, &stbuf) != -1 &&\n\t    ((S_ISREG(stbuf.st_mode) &&\n    /* save time by not calling access() in the hopeless case */\n\t      (stbuf.st_mode & (S_IXOTH | S_IXGRP | S_IXUSR)) &&\n\t      access(strname, X_OK) == 0) ||\n\t     (dir_ok && S_ISDIR(stbuf.st_mode))));\n}\n\nstatic int\niscommand(name)\n    char   *name;\n{\n    register char **pv;\n    register char *sav;\n    register struct varent *v;\n    bool slash = any(name, '/');\n    int hashval = 0, hashval1, i;\n\n    v = adrof(\"path\");\n    if (v == 0 || v->vec[0] == 0 || slash)\n\tpv = justabs;\n    else\n\tpv = v->vec;\n    sav = strspl(\"/\", name);\t/* / command name for postpending */\n    if (havhash)\n\thashval = hashname(name);\n    i = 0;\n    do {\n\tif (!slash && pv[0][0] == '/' && havhash) {\n\t    hashval1 = hash(hashval, i);\n\t    if (!bit(xhash, hashval1))\n\t\tgoto cont;\n\t}\n\tif (pv[0][0] == 0 || eq(pv[0], \".\")) {\t/* don't make ./xxx */\n\t    if (executable(NULL, name, 0)) {\n\t\txfree(sav);\n\t\treturn i + 1;\n\t    }\n\t}\n\telse {\n\t    if (executable(*pv, sav, 0)) {\n\t\txfree(sav);\n\t\treturn i + 1;\n\t    }\n\t}\ncont:\n\tpv++;\n\ti++;\n    } while (*pv);\n    xfree(sav);\n    return 0;\n}\n\nstatic void\ntellmewhat(lex)\n    struct wordent *lex;\n{\n    int i;\n    struct biltins *bptr;\n    register struct wordent *sp = lex->next;\n    bool    aliased = 0;\n    register char   *s2;\n    char *s0, *s1, *cmd;\n    char    qc;\n\n    if (adrof1(sp->word, &aliases)) {\n\talias(lex);\n\tsp = lex->next;\n\taliased = 1;\n    }\n\n    s0 = sp->word;\t\t/* to get the memory freeing right... */\n\n    /* handle quoted alias hack */\n    if ((*(sp->word) & (QUOTE | TRIM)) == QUOTE)\n\t(sp->word)++;\n\n    /* do quoting, if it hasn't been done */\n    s1 = s2 = sp->word;\n    while (*s2)\n\tswitch (*s2) {\n\tcase '\\'':\n\tcase '\"':\n\t    qc = *s2++;\n\t    while (*s2 && *s2 != qc)\n\t\t*s1++ = *s2++ | QUOTE;\n\t    if (*s2)\n\t\ts2++;\n\t    break;\n\tcase '\\\\':\n\t    if (*++s2)\n\t\t*s1++ = *s2++ | QUOTE;\n\t    break;\n\tdefault:\n\t    *s1++ = *s2++;\n\t}\n    *s1 = '\\0';\n\n    for (bptr = bfunc; bptr < &bfunc[nbfunc]; bptr++) {\n\tif (eq(sp->word, bptr->bname)) {\n\t    if (aliased)\n\t\tprlex(lex);\n\t    (void) printf(\"%s: shell built-in command.\\n\", sp->word);\n\t    sp->word = s0;\t/* we save and then restore this */\n\t    return;\n\t}\n    }\n\n    sp->word = cmd = globone(sp->word);\n\n    if ((i = iscommand(strip(sp->word))) != 0) {\n\tregister char **pv;\n\tregister struct varent *v;\n\tbool    slash = any(sp->word, '/');\n\n\tv = adrof(\"path\");\n\tif (v == 0 || v->vec[0] == 0 || slash)\n\t    pv = justabs;\n\telse\n\t    pv = v->vec;\n\n\twhile (--i)\n\t    pv++;\n\tif (pv[0][0] == 0 || eq(pv[0], \".\")) {\n\t    if (!slash) {\n\t\tsp->word = strspl(\"./\", sp->word);\n\t\tprlex(lex);\n\t\txfree(sp->word);\n\t    }\n\t    else\n\t\tprlex(lex);\n\t    sp->word = s0;\t/* we save and then restore this */\n\t    xfree(cmd);\n\t    return;\n\t}\n\ts1 = strspl(*pv, \"/\");\n\tsp->word = strspl(s1, sp->word);\n\txfree(s1);\n\tprlex(lex);\n\txfree(sp->word);\n    }\n    else {\n\tif (aliased)\n\t    prlex(lex);\n\t(void) printf(\"%s: Command not found.\\n\", sp->word);\n    }\n    sp->word = s0;\t\t/* we save and then restore this */\n    xfree(cmd);\n}\n\n/* The dowhich() is by:\n *  Andreas Luik <luik@isaak.isa.de>\n *  I S A  GmbH - Informationssysteme fuer computerintegrierte Automatisierung\n *  Azenberstr. 35\n *  D-7000 Stuttgart 1\n *  West-Germany\n * Thanks!!\n */\n/*ARGSUSED*/\nvoid\ndowhich(v, c)\n    register char **v;\n    struct command *c;\n{\n    struct wordent lex[3];\n    struct varent *vp;\n\n    lex[0].next = &lex[1];\n    lex[1].next = &lex[2];\n    lex[2].next = &lex[0];\n\n    lex[0].prev = &lex[2];\n    lex[1].prev = &lex[0];\n    lex[2].prev = &lex[1];\n\n    lex[0].word = \"\";\n    lex[2].word = \"\\n\";\n\n    while (*++v) {\n\tif ((vp = adrof1(*v, &aliases)) != NULL) {\n\t    (void) printf(\"%s: \\t aliased to \", *v);\n\t    blkpr(vp->vec);\n\t    (void) putchar('\\n');\n\t}\n\telse {\n\t    lex[1].word = *v;\n\t    tellmewhat(lex);\n\t}\n    }\n}\n"
  },
  {
    "path": "bin/csh/sh.exp.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"sh.h\"\n\n/*\n * C shell\n */\n\n#define IGNORE\t1\t/* in ignore, it means to ignore value, just parse */\n#define NOGLOB\t2\t/* in ignore, it means not to globone */\n\n#define\tADDOP\t1\n#define\tMULOP\t2\n#define\tEQOP\t4\n#define\tRELOP\t8\n#define\tRESTOP\t16\n#define\tANYOP\t31\n\n#define\tEQEQ\t1\n#define\tGTR\t2\n#define\tLSS\t4\n#define\tNOTEQ\t6\n#define EQMATCH 7\n#define NOTEQMATCH 8\n\nexpr(vp)\n\tregister char ***vp;\n{\n\n\treturn (exp0(vp, 0));\n}\n\nexp0(vp, ignore)\n\tregister char ***vp;\n\tbool ignore;\n{\n\tregister int p1 = exp1(vp, ignore);\n\n#ifdef EDEBUG\n\tetraci(\"exp0 p1\", p1, vp);\n#endif\n\tif (**vp && eq(**vp, \"||\")) {\n\t\tregister int p2;\n\n\t\t(*vp)++;\n\t\tp2 = exp0(vp, (ignore&IGNORE) || p1);\n#ifdef EDEBUG\n\t\tetraci(\"exp0 p2\", p2, vp);\n#endif\n\t\treturn (p1 || p2);\n\t}\n\treturn (p1);\n}\n\nexp1(vp, ignore)\n\tregister char ***vp;\n{\n\tregister int p1 = expr2(vp, ignore);\n\n#ifdef EDEBUG\n\tetraci(\"exp1 p1\", p1, vp);\n#endif\n\tif (**vp && eq(**vp, \"&&\")) {\n\t\tregister int p2;\n\n\t\t(*vp)++;\n\t\tp2 = exp1(vp, (ignore&IGNORE) || !p1);\n#ifdef EDEBUG\n\t\tetraci(\"exp1 p2\", p2, vp);\n#endif\n\t\treturn (p1 && p2);\n\t}\n\treturn (p1);\n}\n\nexpr2(vp, ignore)\n\tregister char ***vp;\n\tbool ignore;\n{\n\tregister int p1 = exp2a(vp, ignore);\n\n#ifdef EDEBUG\n\tetraci(\"exp3 p1\", p1, vp);\n#endif\n\tif (**vp && eq(**vp, \"|\")) {\n\t\tregister int p2;\n\n\t\t(*vp)++;\n\t\tp2 = expr2(vp, ignore);\n#ifdef EDEBUG\n\t\tetraci(\"exp3 p2\", p2, vp);\n#endif\n\t\treturn (p1 | p2);\n\t}\n\treturn (p1);\n}\n\nexp2a(vp, ignore)\n\tregister char ***vp;\n\tbool ignore;\n{\n\tregister int p1 = exp2b(vp, ignore);\n\n#ifdef EDEBUG\n\tetraci(\"exp2a p1\", p1, vp);\n#endif\n\tif (**vp && eq(**vp, \"^\")) {\n\t\tregister int p2;\n\n\t\t(*vp)++;\n\t\tp2 = exp2a(vp, ignore);\n#ifdef EDEBUG\n\t\tetraci(\"exp2a p2\", p2, vp);\n#endif\n\t\treturn (p1 ^ p2);\n\t}\n\treturn (p1);\n}\n\nexp2b(vp, ignore)\n\tregister char ***vp;\n\tbool ignore;\n{\n\tregister int p1 = exp2c(vp, ignore);\n\n#ifdef EDEBUG\n\tetraci(\"exp2b p1\", p1, vp);\n#endif\n\tif (**vp && eq(**vp, \"&\")) {\n\t\tregister int p2;\n\n\t\t(*vp)++;\n\t\tp2 = exp2b(vp, ignore);\n#ifdef EDEBUG\n\t\tetraci(\"exp2b p2\", p2, vp);\n#endif\n\t\treturn (p1 & p2);\n\t}\n\treturn (p1);\n}\n\nexp2c(vp, ignore)\n\tregister char ***vp;\n\tbool ignore;\n{\n\tregister char *p1 = exp3(vp, ignore);\n\tregister char *p2;\n\tregister int i;\n\n#ifdef EDEBUG\n\tetracc(\"exp2c p1\", p1, vp);\n#endif\n\tif (i = isa(**vp, EQOP)) {\n\t\t(*vp)++;\n\t\tif (i == EQMATCH || i == NOTEQMATCH)\n\t\t\tignore |= NOGLOB;\n\t\tp2 = exp3(vp, ignore);\n#ifdef EDEBUG\n\t\tetracc(\"exp2c p2\", p2, vp);\n#endif\n\t\tif (!(ignore&IGNORE)) switch (i) {\n\n\t\tcase EQEQ:\n\t\t\ti = eq(p1, p2);\n\t\t\tbreak;\n\n\t\tcase NOTEQ:\n\t\t\ti = !eq(p1, p2);\n\t\t\tbreak;\n\n\t\tcase EQMATCH:\n\t\t\ti = Gmatch(p1, p2);\n\t\t\tbreak;\n\n\t\tcase NOTEQMATCH:\n\t\t\ti = !Gmatch(p1, p2);\n\t\t\tbreak;\n\t\t}\n\t\txfree(p1), xfree(p2);\n\t\treturn (i);\n\t}\n\ti = egetn(p1);\n\txfree(p1);\n\treturn (i);\n}\n\nchar *\nexp3(vp, ignore)\n\tregister char ***vp;\n\tbool ignore;\n{\n\tregister char *p1, *p2;\n\tregister int i;\n\n\tp1 = exp3a(vp, ignore);\n#ifdef EDEBUG\n\tetracc(\"exp3 p1\", p1, vp);\n#endif\n\tif (i = isa(**vp, RELOP)) {\n\t\t(*vp)++;\n\t\tif (**vp && eq(**vp, \"=\"))\n\t\t\ti |= 1, (*vp)++;\n\t\tp2 = exp3(vp, ignore);\n#ifdef EDEBUG\n\t\tetracc(\"exp3 p2\", p2, vp);\n#endif\n\t\tif (!(ignore&IGNORE)) switch (i) {\n\n\t\tcase GTR:\n\t\t\ti = egetn(p1) > egetn(p2);\n\t\t\tbreak;\n\n\t\tcase GTR|1:\n\t\t\ti = egetn(p1) >= egetn(p2);\n\t\t\tbreak;\n\n\t\tcase LSS:\n\t\t\ti = egetn(p1) < egetn(p2);\n\t\t\tbreak;\n\n\t\tcase LSS|1:\n\t\t\ti = egetn(p1) <= egetn(p2);\n\t\t\tbreak;\n\t\t}\n\t\txfree(p1), xfree(p2);\n\t\treturn (putn(i));\n\t}\n\treturn (p1);\n}\n\nchar *\nexp3a(vp, ignore)\n\tregister char ***vp;\n\tbool ignore;\n{\n\tregister char *p1, *p2, *op;\n\tregister int i;\n\n\tp1 = exp4(vp, ignore);\n#ifdef EDEBUG\n\tetracc(\"exp3a p1\", p1, vp);\n#endif\n\top = **vp;\n\tif (op && any(op[0], \"<>\") && op[0] == op[1]) {\n\t\t(*vp)++;\n\t\tp2 = exp3a(vp, ignore);\n#ifdef EDEBUG\n\t\tetracc(\"exp3a p2\", p2, vp);\n#endif\n\t\tif (op[0] == '<')\n\t\t\ti = egetn(p1) << egetn(p2);\n\t\telse\n\t\t\ti = egetn(p1) >> egetn(p2);\n\t\txfree(p1), xfree(p2);\n\t\treturn (putn(i));\n\t}\n\treturn (p1);\n}\n\nchar *\nexp4(vp, ignore)\n\tregister char ***vp;\n\tbool ignore;\n{\n\tregister char *p1, *p2;\n\tregister int i = 0;\n\n\tp1 = exp5(vp, ignore);\n#ifdef EDEBUG\n\tetracc(\"exp4 p1\", p1, vp);\n#endif\n\tif (isa(**vp, ADDOP)) {\n\t\tregister char *op = *(*vp)++;\n\n\t\tp2 = exp4(vp, ignore);\n#ifdef EDEBUG\n\t\tetracc(\"exp4 p2\", p2, vp);\n#endif\n\t\tif (!(ignore&IGNORE)) switch (op[0]) {\n\n\t\tcase '+':\n\t\t\ti = egetn(p1) + egetn(p2);\n\t\t\tbreak;\n\n\t\tcase '-':\n\t\t\ti = egetn(p1) - egetn(p2);\n\t\t\tbreak;\n\t\t}\n\t\txfree(p1), xfree(p2);\n\t\treturn (putn(i));\n\t}\n\treturn (p1);\n}\n\nchar *\nexp5(vp, ignore)\n\tregister char ***vp;\n\tbool ignore;\n{\n\tregister char *p1, *p2;\n\tregister int i = 0;\n\n\tp1 = exp6(vp, ignore);\n#ifdef EDEBUG\n\tetracc(\"exp5 p1\", p1, vp);\n#endif\n\tif (isa(**vp, MULOP)) {\n\t\tregister char *op = *(*vp)++;\n\n\t\tp2 = exp5(vp, ignore);\n#ifdef EDEBUG\n\t\tetracc(\"exp5 p2\", p2, vp);\n#endif\n\t\tif (!(ignore&IGNORE)) switch (op[0]) {\n\n\t\tcase '*':\n\t\t\ti = egetn(p1) * egetn(p2);\n\t\t\tbreak;\n\n\t\tcase '/':\n\t\t\ti = egetn(p2);\n\t\t\tif (i == 0)\n\t\t\t\terror(\"Divide by 0\");\n\t\t\ti = egetn(p1) / i;\n\t\t\tbreak;\n\n\t\tcase '%':\n\t\t\ti = egetn(p2);\n\t\t\tif (i == 0)\n\t\t\t\terror(\"Mod by 0\");\n\t\t\ti = egetn(p1) % i;\n\t\t\tbreak;\n\t\t}\n\t\txfree(p1), xfree(p2);\n\t\treturn (putn(i));\n\t}\n\treturn (p1);\n}\n\nchar *\nexp6(vp, ignore)\n\tregister char ***vp;\n{\n\tint ccode, i;\n\tregister char *cp, *dp, *ep;\n\n\tif (**vp == 0)\n\t\tbferr(\"Expression syntax\");\n\tif (eq(**vp, \"!\")) {\n\t\t(*vp)++;\n\t\tcp = exp6(vp, ignore);\n#ifdef EDEBUG\n\t\tetracc(\"exp6 ! cp\", cp, vp);\n#endif\n\t\ti = egetn(cp);\n\t\txfree(cp);\n\t\treturn (putn(!i));\n\t}\n\tif (eq(**vp, \"~\")) {\n\t\t(*vp)++;\n\t\tcp = exp6(vp, ignore);\n#ifdef EDEBUG\n\t\tetracc(\"exp6 ~ cp\", cp, vp);\n#endif\n\t\ti = egetn(cp);\n\t\txfree(cp);\n\t\treturn (putn(~i));\n\t}\n\tif (eq(**vp, \"(\")) {\n\t\t(*vp)++;\n\t\tccode = exp0(vp, ignore);\n#ifdef EDEBUG\n\t\tetraci(\"exp6 () ccode\", ccode, vp);\n#endif\n\t\tif (*vp == 0 || **vp == 0 || ***vp != ')')\n\t\t\tbferr(\"Expression syntax\");\n\t\t(*vp)++;\n\t\treturn (putn(ccode));\n\t}\n\tif (eq(**vp, \"{\")) {\n\t\tregister char **v;\n\t\tstruct command faket;\n\t\tchar *fakecom[2];\n\n\t\tfaket.t_dtyp = TCOM;\n\t\tfaket.t_dflg = 0;\n\t\tfaket.t_dcar = faket.t_dcdr = faket.t_dspr = (struct command *)0;\n\t\tfaket.t_dcom = fakecom;\n\t\tfakecom[0] = \"{ ... }\";\n\t\tfakecom[1] = NOSTR;\n\t\t(*vp)++;\n\t\tv = *vp;\n\t\tfor (;;) {\n\t\t\tif (!**vp)\n\t\t\t\tbferr(\"Missing }\");\n\t\t\tif (eq(*(*vp)++, \"}\"))\n\t\t\t\tbreak;\n\t\t}\n\t\tif (ignore&IGNORE)\n\t\t\treturn (\"\");\n\t\tpsavejob();\n\t\tif (pfork(&faket, -1) == 0) {\n\t\t\t*--(*vp) = 0;\n\t\t\tevalav(v);\n\t\t\texitstat();\n\t\t}\n\t\tpwait();\n\t\tprestjob();\n#ifdef EDEBUG\n\t\tetraci(\"exp6 {} status\", egetn(value(\"status\")), vp);\n#endif\n\t\treturn (putn(egetn(value(\"status\")) == 0));\n\t}\n\tif (isa(**vp, ANYOP))\n\t\treturn (\"\");\n\tcp = *(*vp)++;\n\tif (*cp == '-' && any(cp[1], \"erwxfdzo\")) {\n\t\tstruct stat stb;\n\n\t\tif (isa(**vp, ANYOP))\n\t\t\tbferr(\"Missing file name\");\n\t\tdp = *(*vp)++;\n\t\tif (ignore&IGNORE)\n\t\t\treturn (\"\");\n\t\tep = globone(dp);\n\t\tswitch (cp[1]) {\n\n\t\tcase 'r':\n\t\t\ti = !access(ep, 4);\n\t\t\tbreak;\n\n\t\tcase 'w':\n\t\t\ti = !access(ep, 2);\n\t\t\tbreak;\n\n\t\tcase 'x':\n\t\t\ti = !access(ep, 1);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tif (stat(ep, &stb)) {\n\t\t\t\txfree(ep);\n\t\t\t\treturn (\"0\");\n\t\t\t}\n\t\t\tswitch (cp[1]) {\n\n\t\t\tcase 'f':\n\t\t\t\ti = (stb.st_mode & S_IFMT) == S_IFREG;\n\t\t\t\tbreak;\n\n\t\t\tcase 'd':\n\t\t\t\ti = (stb.st_mode & S_IFMT) == S_IFDIR;\n\t\t\t\tbreak;\n\n\t\t\tcase 'z':\n\t\t\t\ti = stb.st_size == 0;\n\t\t\t\tbreak;\n\n\t\t\tcase 'e':\n\t\t\t\ti = 1;\n\t\t\t\tbreak;\n\n\t\t\tcase 'o':\n\t\t\t\ti = stb.st_uid == uid;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n#ifdef EDEBUG\n\t\tetraci(\"exp6 -? i\", i, vp);\n#endif\n\t\txfree(ep);\n\t\treturn (putn(i));\n\t}\n#ifdef EDEBUG\n\tetracc(\"exp6 default\", cp, vp);\n#endif\n\treturn (ignore&NOGLOB ? savestr(cp) : globone(cp));\n}\n\nevalav(v)\n\tregister char **v;\n{\n\tstruct wordent paraml;\n\tregister struct wordent *hp = &paraml;\n\tstruct command *t;\n\tregister struct wordent *wdp = hp;\n\n\tset(\"status\", \"0\");\n\thp->prev = hp->next = hp;\n\thp->word = \"\";\n\twhile (*v) {\n\t\tregister struct wordent *new = (struct wordent *) calloc(1, sizeof *wdp);\n\n\t\tnew->prev = wdp;\n\t\tnew->next = hp;\n\t\twdp->next = new;\n\t\twdp = new;\n\t\twdp->word = savestr(*v++);\n\t}\n\thp->prev = wdp;\n\talias(&paraml);\n\tt = syntax(paraml.next, &paraml, 0);\n\tif (parserr)\n\t\terror(parserr);\n\texecute(t, -1);\n\tfreelex(&paraml), freesyn(t);\n}\n\nisa(cp, what)\n\tregister char *cp;\n\tregister int what;\n{\n\n\tif (cp == 0)\n\t\treturn ((what & RESTOP) != 0);\n\tif (cp[1] == 0) {\n\t\tif (what & ADDOP && (*cp == '+' || *cp == '-'))\n\t\t\treturn (1);\n\t\tif (what & MULOP && (*cp == '*' || *cp == '/' || *cp == '%'))\n\t\t\treturn (1);\n\t\tif (what & RESTOP && (*cp == '(' || *cp == ')' || *cp == '!' ||\n\t\t\t\t      *cp == '~' || *cp == '^' || *cp == '\"'))\n\t\t\treturn (1);\n\t} else if (cp[2] == 0) {\n\t\tif (what & RESTOP) {\n\t\t\tif (cp[0] == '|' && cp[1] == '&')\n\t\t\t\treturn (1);\n\t\t\tif (cp[0] == '<' && cp[1] == '<')\n\t\t\t\treturn (1);\n\t\t\tif (cp[0] == '>' && cp[1] == '>')\n\t\t\t\treturn (1);\n\t\t}\n\t\tif (what & EQOP) {\n\t\t\tif (cp[0] == '=') {\n\t\t\t\tif (cp[1] == '=')\n\t\t\t\t\treturn (EQEQ);\n\t\t\t\tif (cp[1] == '~')\n\t\t\t\t\treturn (EQMATCH);\n\t\t\t} else if (cp[0] == '!') {\n\t\t\t\tif (cp[1] == '=')\n\t\t\t\t\treturn (NOTEQ);\n\t\t\t\tif (cp[1] == '~')\n\t\t\t\t\treturn (NOTEQMATCH);\n\t\t\t}\n\t\t}\n\t}\n\tif (what & RELOP) {\n\t\tif (*cp == '<')\n\t\t\treturn (LSS);\n\t\tif (*cp == '>')\n\t\t\treturn (GTR);\n\t}\n\treturn (0);\n}\n\negetn(cp)\n\tregister char *cp;\n{\n\n\tif (*cp && *cp != '-' && !digit(*cp))\n\t\tbferr(\"Expression syntax\");\n\treturn (getn(cp));\n}\n\n/* Phew! */\n\n#ifdef EDEBUG\netraci(str, i, vp)\n\tchar *str;\n\tint i;\n\tchar ***vp;\n{\n\n\tprintf(\"%s=%d\\t\", str, i);\n\tblkpr(*vp);\n\tprintf(\"\\n\");\n}\n\netracc(str, cp, vp)\n\tchar *str, *cp;\n\tchar ***vp;\n{\n\n\tprintf(\"%s=%s\\t\", str, cp);\n\tblkpr(*vp);\n\tprintf(\"\\n\");\n}\n#endif\n"
  },
  {
    "path": "bin/csh/sh.file.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#ifdef FILEC\n/*\n * Tenex style file name recognition, .. and more.\n * History:\n *\tAuthor: Ken Greer, Sept. 1975, CMU.\n *\tFinally got around to adding to the Cshell., Ken Greer, Dec. 1981.\n */\n\n#include \"sh.h\"\n#include <sgtty.h>\n#include <sys/dir.h>\n#include <pwd.h>\n\n#define TRUE\t1\n#define FALSE\t0\n#define ON\t1\n#define OFF\t0\n\n#define ESC\t'\\033'\n\ntypedef enum {LIST, RECOGNIZE} COMMAND;\n\nint\tsortscmp();\t\t\t/* defined in sh.glob.c */\n\n/*\n * Put this here so the binary can be patched with adb to enable file\n * completion by default.  Filec controls completion, nobeep controls\n * ringing the terminal bell on incomplete expansions.\n */\nbool filec = 0;\n\nstatic\nsetup_tty(on)\n\tint on;\n{\n\tstruct sgttyb sgtty;\n\tstatic struct tchars tchars;\t/* INT, QUIT, XON, XOFF, EOF, BRK */\n\n\tif (on) {\n\t\t(void) ioctl(SHIN, TIOCGETC, (char *)&tchars);\n\t\ttchars.t_brkc = ESC;\n\t\t(void) ioctl(SHIN, TIOCSETC, (char *)&tchars);\n\t\t/*\n\t\t * This must be done after every command: if\n\t\t * the tty gets into raw or cbreak mode the user\n\t\t * can't even type 'reset'.\n\t\t */\n\t\t(void) ioctl(SHIN, TIOCGETP, (char *)&sgtty);\n\t\tif (sgtty.sg_flags & (RAW|CBREAK)) {\n\t\t\t sgtty.sg_flags &= ~(RAW|CBREAK);\n\t\t\t (void) ioctl(SHIN, TIOCSETP, (char *)&sgtty);\n\t\t}\n\t} else {\n\t\ttchars.t_brkc = -1;\n\t\t(void) ioctl(SHIN, TIOCSETC, (char *)&tchars);\n\t}\n}\n\n/*\n * Move back to beginning of current line\n */\nstatic\nback_to_col_1()\n{\n\tstruct sgttyb tty, tty_normal;\n\tlong omask;\n\n\tomask = sigblock(sigmask(SIGINT));\n\t(void) ioctl(SHIN, TIOCGETP, (char *)&tty);\n\ttty_normal = tty;\n\ttty.sg_flags &= ~CRMOD;\n\t(void) ioctl(SHIN, TIOCSETN, (char *)&tty);\n\t(void) write(SHOUT, \"\\r\", 1);\n\t(void) ioctl(SHIN, TIOCSETN, (char *)&tty_normal);\n\t(void) sigsetmask(omask);\n}\n\n/*\n * Push string contents back into tty queue\n */\nstatic\npushback(string)\n\tchar *string;\n{\n\tregister char *p;\n\tstruct sgttyb tty, tty_normal;\n\tlong omask;\n\n\tomask = sigblock(sigmask(SIGINT));\n\t(void) ioctl(SHOUT, TIOCGETP, (char *)&tty);\n\ttty_normal = tty;\n\ttty.sg_flags &= ~ECHO;\n\t(void) ioctl(SHOUT, TIOCSETN, (char *)&tty);\n\n\tfor (p = string; *p; p++)\n\t\t(void) ioctl(SHOUT, TIOCSTI, p);\n\t(void) ioctl(SHOUT, TIOCSETN, (char *)&tty_normal);\n\t(void) sigsetmask(omask);\n}\n\n/*\n * Concatenate src onto tail of des.\n * Des is a string whose maximum length is count.\n * Always null terminate.\n */\nstatic\ncatn(des, src, count)\n\tregister char *des, *src;\n\tregister count;\n{\n\n\twhile (--count >= 0 && *des)\n\t\tdes++;\n\twhile (--count >= 0)\n\t\tif ((*des++ = *src++) == 0)\n\t\t\t return;\n\t*des = '\\0';\n}\n\n/*\n * Like strncpy but always leave room for trailing \\0\n * and always null terminate.\n */\nstatic\ncopyn(des, src, count)\n\tregister char *des, *src;\n\tregister count;\n{\n\n\twhile (--count >= 0)\n\t\tif ((*des++ = *src++) == 0)\n\t\t\treturn;\n\t*des = '\\0';\n}\n\nstatic char\nfiletype(dir, file)\n\tchar *dir, *file;\n{\n\tchar path[MAXPATHLEN];\n\tstruct stat statb;\n\n\tcatn(strcpy(path, dir), file, sizeof path);\n\tif (lstat(path, &statb) == 0) {\n\t\tswitch(statb.st_mode & S_IFMT) {\n\t\t    case S_IFDIR:\n\t\t\treturn ('/');\n\n\t\t    case S_IFLNK:\n\t\t\tif (stat(path, &statb) == 0 &&\t    /* follow it out */\n\t\t\t   (statb.st_mode & S_IFMT) == S_IFDIR)\n\t\t\t\treturn ('>');\n\t\t\telse\n\t\t\t\treturn ('@');\n\n\t\t    case S_IFSOCK:\n\t\t\treturn ('=');\n\n\t\t    default:\n\t\t\tif (statb.st_mode & 0111)\n\t\t\t\treturn ('*');\n\t\t}\n\t}\n\treturn (' ');\n}\n\nstatic struct winsize win;\n\n/*\n * Print sorted down columns\n */\nstatic\nprint_by_column(dir, items, count)\n\tchar *dir, *items[];\n{\n\tregister int i, rows, r, c, maxwidth = 0, columns;\n\n\tif (ioctl(SHOUT, TIOCGWINSZ, (char *)&win) < 0 || win.ws_col == 0)\n\t\twin.ws_col = 80;\n\tfor (i = 0; i < count; i++)\n\t\tmaxwidth = maxwidth > (r = strlen(items[i])) ? maxwidth : r;\n\tmaxwidth += 2;\t\t\t/* for the file tag and space */\n\tcolumns = win.ws_col / maxwidth;\n\tif (columns == 0)\n\t\tcolumns = 1;\n\trows = (count + (columns - 1)) / columns;\n\tfor (r = 0; r < rows; r++) {\n\t\tfor (c = 0; c < columns; c++) {\n\t\t\ti = c * rows + r;\n\t\t\tif (i < count) {\n\t\t\t\tregister int w;\n\n\t\t\t\tprintf(\"%s\", items[i]);\n\t\t\t\tputchar(dir ? filetype(dir, items[i]) : ' ');\n\t\t\t\tif (c < columns - 1) {\t/* last column? */\n\t\t\t\t\tw = strlen(items[i]) + 1;\n\t\t\t\t\tfor (; w < maxwidth; w++)\n\t\t\t\t\t\tputchar(' ');\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tputchar('\\n');\n\t}\n}\n\n/*\n * Expand file name with possible tilde usage\n *\t~person/mumble\n * expands to\n *\thome_directory_of_person/mumble\n */\nstatic char *\ntilde(new, old)\n\tchar *new, *old;\n{\n\tregister char *o, *p;\n\tregister struct passwd *pw;\n\tstatic char person[40];\n\n\tif (old[0] != '~')\n\t\treturn (strcpy(new, old));\n\n\tfor (p = person, o = &old[1]; *o && *o != '/'; *p++ = *o++)\n\t\t;\n\t*p = '\\0';\n\tif (person[0] == '\\0')\n\t\t(void) strcpy(new, value(\"home\"));\n\telse {\n\t\tpw = getpwnam(person);\n\t\tif (pw == NULL)\n\t\t\treturn (NULL);\n\t\t(void) strcpy(new, pw->pw_dir);\n\t}\n\t(void) strcat(new, o);\n\treturn (new);\n}\n\n/*\n * Cause pending line to be printed\n */\nstatic\nretype()\n{\n\tint pending_input = LPENDIN;\n\n\t(void) ioctl(SHOUT, TIOCLBIS, (char *)&pending_input);\n}\n\nstatic\nbeep()\n{\n\n\tif (adrof(\"nobeep\") == 0)\n\t\t(void) write(SHOUT, \"\\007\", 1);\n}\n\n/*\n * Erase that silly ^[ and\n * print the recognized part of the string\n */\nstatic\nprint_recognized_stuff(recognized_part)\n\tchar *recognized_part;\n{\n\n\t/* An optimized erasing of that silly ^[ */\n\tswitch (strlen(recognized_part)) {\n\n\tcase 0:\t\t\t\t/* erase two characters: ^[ */\n\t\tprintf(\"\\210\\210  \\210\\210\");\n\t\tbreak;\n\n\tcase 1:\t\t\t\t/* overstrike the ^, erase the [ */\n\t\tprintf(\"\\210\\210%s \\210\", recognized_part);\n\t\tbreak;\n\n\tdefault:\t\t\t/* overstrike both characters ^[ */\n\t\tprintf(\"\\210\\210%s\", recognized_part);\n\t\tbreak;\n\t}\n\tflush();\n}\n\n/*\n * Parse full path in file into 2 parts: directory and file names\n * Should leave final slash (/) at end of dir.\n */\nstatic\nextract_dir_and_name(path, dir, name)\n\tchar *path, *dir, *name;\n{\n\tregister char  *p;\n\n\tp = rindex(path, '/');\n\tif (p == NULL) {\n\t\tcopyn(name, path, MAXNAMLEN);\n\t\tdir[0] = '\\0';\n\t} else {\n\t\tcopyn(name, ++p, MAXNAMLEN);\n\t\tcopyn(dir, path, p - path);\n\t}\n}\n\nstatic char *\ngetentry(dir_fd, looking_for_lognames)\n\tDIR *dir_fd;\n{\n\tregister struct passwd *pw;\n\tregister struct direct *dirp;\n\n\tif (looking_for_lognames) {\n\t\tif ((pw = getpwent()) == NULL)\n\t\t\treturn (NULL);\n\t\treturn (pw->pw_name);\n\t}\n\tif (dirp = readdir(dir_fd))\n\t\treturn (dirp->d_name);\n\treturn (NULL);\n}\n\nstatic\nfree_items(items)\n\tregister char **items;\n{\n\tregister int i;\n\n\tfor (i = 0; items[i]; i++)\n\t\tfree(items[i]);\n\tfree((char *)items);\n}\n\n#define FREE_ITEMS(items) { \\\n\tlong omask;\\\n\\\n\tomask = sigblock(sigmask(SIGINT));\\\n\tfree_items(items);\\\n\titems = NULL;\\\n\t(void) sigsetmask(omask);\\\n}\n\n/*\n * Object: extend what user typed up to an ambiguity.\n * Algorithm:\n * On first match, copy full entry (assume it'll be the only match)\n * On subsequent matches, shorten extended_name to the first\n * character mismatch between extended_name and entry.\n * If we shorten it back to the prefix length, stop searching.\n */\nstatic\nrecognize(extended_name, entry, name_length, numitems)\n\tchar *extended_name, *entry;\n{\n\n\tif (numitems == 1)\t\t\t/* 1st match */\n\t\tcopyn(extended_name, entry, MAXNAMLEN);\n\telse {\t\t\t\t\t/* 2nd & subsequent matches */\n\t\tregister char *x, *ent;\n\t\tregister int len = 0;\n\n\t\tx = extended_name;\n\t\tfor (ent = entry; *x && *x == *ent++; x++, len++)\n\t\t\t;\n\t\t*x = '\\0';\t\t\t/* Shorten at 1st char diff */\n\t\tif (len == name_length)\t\t/* Ambiguous to prefix? */\n\t\t\treturn (-1);\t\t/* So stop now and save time */\n\t}\n\treturn (0);\n}\n\n/*\n * Return true if check matches initial chars in template.\n * This differs from PWB imatch in that if check is null\n * it matches anything.\n */\nstatic\nis_prefix(check, template)\n\tregister char *check, *template;\n{\n\n\tdo\n\t\tif (*check == 0)\n\t\t\treturn (TRUE);\n\twhile (*check++ == *template++);\n\treturn (FALSE);\n}\n\n/*\n *  Return true if the chars in template appear at the\n *  end of check, I.e., are it's suffix.\n */\nstatic\nis_suffix(check, template)\n\tchar *check, *template;\n{\n\tregister char *c, *t;\n\n\tfor (c = check; *c++;)\n\t\t;\n\tfor (t = template; *t++;)\n\t\t;\n\tfor (;;) {\n\t\tif (t == template)\n\t\t\treturn 1;\n\t\tif (c == check || *--t != *--c)\n\t\t\treturn 0;\n\t}\n}\n\nstatic\nignored(entry)\n\tregister char *entry;\n{\n\tstruct varent *vp;\n\tregister char **cp;\n\n\tif ((vp = adrof(\"fignore\")) == NULL || (cp = vp->vec) == NULL)\n\t\treturn (FALSE);\n\tfor (; *cp != NULL; cp++)\n\t\tif (is_suffix(entry, *cp))\n\t\t\treturn (TRUE);\n\treturn (FALSE);\n}\n\n/*\n * Perform a RECOGNIZE or LIST command on string \"word\".\n */\nstatic\nsearch(word, command, max_word_length)\n\tchar *word;\n\tCOMMAND command;\n{\n\tstatic char **items = NULL;\n\tregister DIR *dir_fd;\n\tregister numitems = 0, ignoring = TRUE, nignored = 0;\n\tregister name_length, looking_for_lognames;\n\tchar tilded_dir[MAXPATHLEN + 1], dir[MAXPATHLEN + 1];\n\tchar name[MAXNAMLEN + 1], extended_name[MAXNAMLEN+1];\n\tchar *entry;\n#define MAXITEMS 1024\n\n\tif (items != NULL)\n\t\tFREE_ITEMS(items);\n\n\tlooking_for_lognames = (*word == '~') && (index(word, '/') == NULL);\n\tif (looking_for_lognames) {\n\t\t(void) setpwent();\n\t\tcopyn(name, &word[1], MAXNAMLEN);\t/* name sans ~ */\n\t} else {\n\t\textract_dir_and_name(word, dir, name);\n\t\tif (tilde(tilded_dir, dir) == 0)\n\t\t\treturn (0);\n\t\tdir_fd = opendir(*tilded_dir ? tilded_dir : \".\");\n\t\tif (dir_fd == NULL)\n\t\t\treturn (0);\n\t}\n\nagain:\t/* search for matches */\n\tname_length = strlen(name);\n\tfor (numitems = 0; entry = getentry(dir_fd, looking_for_lognames); ) {\n\t\tif (!is_prefix(name, entry))\n\t\t\tcontinue;\n\t\t/* Don't match . files on null prefix match */\n\t\tif (name_length == 0 && entry[0] == '.' &&\n\t\t    !looking_for_lognames)\n\t\t\tcontinue;\n\t\tif (command == LIST) {\n\t\t\tif (numitems >= MAXITEMS) {\n\t\t\t\tprintf (\"\\nYikes!! Too many %s!!\\n\",\n\t\t\t\t    looking_for_lognames ?\n\t\t\t\t\t\"names in password file\":\"files\");\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (items == NULL)\n\t\t\t\titems = (char **) calloc(sizeof (items[1]),\n\t\t\t\t    MAXITEMS);\n\t\t\titems[numitems] = xalloc((unsigned)strlen(entry) + 1);\n\t\t\tcopyn(items[numitems], entry, MAXNAMLEN);\n\t\t\tnumitems++;\n\t\t} else {\t\t\t/* RECOGNIZE command */\n\t\t\tif (ignoring && ignored(entry))\n\t\t\t\tnignored++;\n\t\t\telse if (recognize(extended_name,\n\t\t\t    entry, name_length, ++numitems))\n\t\t\t\tbreak;\n\t\t}\n\t}\n\tif (ignoring && numitems == 0 && nignored > 0) {\n\t\tignoring = FALSE;\n\t\tnignored = 0;\n\t\tif (looking_for_lognames)\n\t\t\t(void) setpwent();\n\t\telse\n\t\t\trewinddir(dir_fd);\n\t\tgoto again;\n\t}\n\n\tif (looking_for_lognames)\n\t\t(void) endpwent();\n\telse\n\t\tclosedir(dir_fd);\n\tif (numitems == 0)\n\t\treturn (0);\n\tif (command == RECOGNIZE) {\n\t\tif (looking_for_lognames)\n\t\t\t copyn(word, \"~\", 1);\n\t\telse\n\t\t\t/* put back dir part */\n\t\t\tcopyn(word, dir, max_word_length);\n\t\t/* add extended name */\n\t\tcatn(word, extended_name, max_word_length);\n\t\treturn (numitems);\n\t}\n\telse { \t\t\t\t/* LIST */\n\t\tqsort((char *)items, numitems, sizeof(items[1]), sortscmp);\n\t\tprint_by_column(looking_for_lognames ? NULL : tilded_dir,\n\t\t    items, numitems);\n\t\tif (items != NULL)\n\t\t\tFREE_ITEMS(items);\n\t}\n\treturn (0);\n}\n\ntenex(inputline, inputline_size)\n\tchar *inputline;\n\tint inputline_size;\n{\n\tregister int numitems, num_read;\n\n\tsetup_tty(ON);\n\twhile ((num_read = read(SHIN, inputline, inputline_size)) > 0) {\n\t\tstatic char *delims = \" '\\\"\\t;&<>()|^%\";\n\t\tregister char *str_end, *word_start, last_char, should_retype;\n\t\tregister int space_left;\n\t\tCOMMAND command;\n\n\t\tlast_char = inputline[num_read - 1] & 0177;\n\n\t\tif (last_char == '\\n' || num_read == inputline_size)\n\t\t\tbreak;\n\t\tcommand = (last_char == ESC) ? RECOGNIZE : LIST;\n\t\tif (command == LIST)\n\t\t\tputchar('\\n');\n\t\tstr_end = &inputline[num_read];\n\t\tif (last_char == ESC)\n\t\t\t--str_end;\t\t/* wipeout trailing cmd char */\n\t\t*str_end = '\\0';\n\t\t/*\n\t\t * Find LAST occurence of a delimiter in the inputline.\n\t\t * The word start is one character past it.\n\t\t */\n\t\tfor (word_start = str_end; word_start > inputline; --word_start)\n\t\t\tif (index(delims, word_start[-1]))\n\t\t\t\tbreak;\n\t\tspace_left = inputline_size - (word_start - inputline) - 1;\n\t\tnumitems = search(word_start, command, space_left);\n\n\t\tif (command == RECOGNIZE) {\n\t\t\t/* print from str_end on */\n\t\t\tprint_recognized_stuff(str_end);\n\t\t\tif (numitems != 1)\t/* Beep = No match/ambiguous */\n\t\t\t\tbeep();\n\t\t}\n\n\t\t/*\n\t\t * Tabs in the input line cause trouble after a pushback.\n\t\t * tty driver won't backspace over them because column\n\t\t * positions are now incorrect. This is solved by retyping\n\t\t * over current line.\n\t\t */\n\t\tshould_retype = FALSE;\n\t\tif (index(inputline, '\\t')) {\t/* tab char in input line? */\n\t\t\tback_to_col_1();\n\t\t\tshould_retype = TRUE;\n\t\t}\n\t\tif (command == LIST)\t\t/* Always retype after a LIST */\n\t\t\tshould_retype = TRUE;\n\t\tif (should_retype)\n\t\t\tprintprompt();\n\t\tpushback(inputline);\n\t\tif (should_retype)\n\t\t\tretype();\n\t}\n\tsetup_tty(OFF);\n\treturn (num_read);\n}\n#endif /* FILEC */\n"
  },
  {
    "path": "bin/csh/sh.func.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"sh.h\"\n#include <sys/ioctl.h>\n\n/*\n * C shell\n */\n\nstruct biltins *\nisbfunc(t)\n\tstruct command *t;\n{\n\tregister char *cp = t->t_dcom[0];\n\tregister struct biltins *bp, *bp1, *bp2;\n\tint dolabel(), dofg1(), dobg1();\n\tstatic struct biltins label = { \"\", dolabel, 0, 0 };\n\tstatic struct biltins foregnd = { \"%job\", dofg1, 0, 0 };\n\tstatic struct biltins backgnd = { \"%job &\", dobg1, 0, 0 };\n\n\tif (lastchr(cp) == ':') {\n\t\tlabel.bname = cp;\n\t\treturn (&label);\n\t}\n\tif (*cp == '%') {\n\t\tif (t->t_dflg & FAND) {\n\t\t\tt->t_dflg &= ~FAND;\n\t\t\tbackgnd.bname = cp;\n\t\t\treturn (&backgnd);\n\t\t}\n\t\tforegnd.bname = cp;\n\t\treturn (&foregnd);\n\t}\n\t/*\n\t * Binary search\n\t * Bp1 is the beginning of the current search range.\n\t * Bp2 is one past the end.\n\t */\n\tfor (bp1 = bfunc, bp2 = bfunc + nbfunc; bp1 < bp2;) {\n\t\tregister i;\n\n\t\tbp = bp1 + (bp2 - bp1 >> 1);\n\t\tif ((i = *cp - *bp->bname) == 0 &&\n\t\t    (i = strcmp(cp, bp->bname)) == 0)\n\t\t\treturn bp;\n\t\tif (i < 0)\n\t\t\tbp2 = bp;\n\t\telse\n\t\t\tbp1 = bp + 1;\n\t}\n\treturn (0);\n}\n\nfunc(t, bp)\n\tregister struct command *t;\n\tregister struct biltins *bp;\n{\n\tint i;\n\n\txechoit(t->t_dcom);\n\tsetname(bp->bname);\n\ti = blklen(t->t_dcom) - 1;\n\tif (i < bp->minargs)\n\t\tbferr(\"Too few arguments\");\n\tif (i > bp->maxargs)\n\t\tbferr(\"Too many arguments\");\n\t(*bp->bfunct)(t->t_dcom, t);\n}\n\ndolabel()\n{\n}\n\ndoonintr(v)\n\tchar **v;\n{\n\tregister char *cp;\n\tregister char *vv = v[1];\n\n\tif (parintr == SIG_IGN)\n\t\treturn;\n\tif (setintr && intty)\n\t\tbferr(\"Can't from terminal\");\n\tcp = gointr, gointr = 0, xfree(cp);\n\tif (vv == 0) {\n\t\tif (setintr)\n\t\t\t(void) sigblock(sigmask(SIGINT));\n\t\telse\n\t\t\t(void) signal(SIGINT, SIG_DFL);\n\t\tgointr = 0;\n\t} else if (eq((vv = strip(vv)), \"-\")) {\n\t\t(void) signal(SIGINT, SIG_IGN);\n\t\tgointr = \"-\";\n\t} else {\n\t\tgointr = savestr(vv);\n\t\t(void) signal(SIGINT, pintr);\n\t}\n}\n\ndonohup()\n{\n\tif (intty)\n\t\tbferr(\"Can't from terminal\");\n\tif (setintr == 0) {\n\t\t(void) signal(SIGHUP, SIG_IGN);\n#ifdef CC\n\t\tsubmit(getpid());\n#endif\n\t}\n}\n\ndozip()\n{\n\t;\n}\n\nprvars()\n{\n\tplist(&shvhed);\n}\n\ndoalias(v)\n\tregister char **v;\n{\n\tregister struct varent *vp;\n\tregister char *p;\n\n\tv++;\n\tp = *v++;\n\tif (p == 0)\n\t\tplist(&aliases);\n\telse if (*v == 0) {\n\t\tvp = adrof1(strip(p), &aliases);\n\t\tif (vp)\n\t\t\tblkpr(vp->vec), printf(\"\\n\");\n\t} else {\n\t\tif (eq(p, \"alias\") || eq(p, \"unalias\")) {\n\t\t\tsetname(p);\n\t\t\tbferr(\"Too dangerous to alias that\");\n\t\t}\n\t\tset1(strip(p), saveblk(v), &aliases);\n\t}\n}\n\nunalias(v)\n\tchar **v;\n{\n\tunset1(v, &aliases);\n}\n\ndologout()\n{\n\n\tislogin();\n\tgoodbye();\n}\n\ndologin(v)\n\tchar **v;\n{\n\tislogin();\n\trechist();\n\t(void) signal(SIGTERM, parterm);\n\texecl(\"/usr/bin/login\", \"login\", v[1], (char*)0);\n\tuntty();\n\texit(1);\n}\n\n#ifdef NEWGRP\ndonewgrp(v)\n\tchar **v;\n{\n\tif (chkstop == 0 && setintr)\n\t\tpanystop(0);\n\t(void) signal(SIGTERM, parterm);\n\texecl(\"/bin/newgrp\", \"newgrp\", v[1], (char*)0);\n\tuntty();\n\texit(1);\n}\n#endif\n\nislogin()\n{\n\tif (chkstop == 0 && setintr)\n\t\tpanystop(0);\n\tif (loginsh)\n\t\treturn;\n\terror(\"Not login shell\");\n}\n\ndoif(v, kp)\n\tchar **v;\n\tstruct command *kp;\n{\n\tregister int i;\n\tregister char **vv;\n\n\tv++;\n\ti = expr(&v);\n\tvv = v;\n\tif (*vv == NOSTR)\n\t\tbferr(\"Empty if\");\n\tif (eq(*vv, \"then\")) {\n\t\tif (*++vv)\n\t\t\tbferr(\"Improper then\");\n\t\tsetname(\"then\");\n\t\t/*\n\t\t * If expression was zero, then scan to else,\n\t\t * otherwise just fall into following code.\n\t\t */\n\t\tif (!i)\n\t\t\tsearch(ZIF, 0);\n\t\treturn;\n\t}\n\t/*\n\t * Simple command attached to this if.\n\t * Left shift the node in this tree, munging it\n\t * so we can reexecute it.\n\t */\n\tif (i) {\n\t\tlshift(kp->t_dcom, vv - kp->t_dcom);\n\t\treexecute(kp);\n\t\tdonefds();\n\t}\n}\n\n/*\n * Reexecute a command, being careful not\n * to redo i/o redirection, which is already set up.\n */\nreexecute(kp)\n\tregister struct command *kp;\n{\n\n\tkp->t_dflg &= FSAVE;\n\tkp->t_dflg |= FREDO;\n\t/*\n\t * If tty is still ours to arbitrate, arbitrate it;\n\t * otherwise dont even set pgrp's as the jobs would\n\t * then have no way to get the tty (we can't give it\n\t * to them, and our parent wouldn't know their pgrp, etc.\n\t */\n\texecute(kp, tpgrp > 0 ? tpgrp : -1);\n}\n\ndoelse()\n{\n\n\tsearch(ZELSE, 0);\n}\n\ndogoto(v)\n\tchar **v;\n{\n\tregister struct whyle *wp;\n\tchar *lp;\n\n\t/*\n\t * While we still can, locate any unknown ends of existing loops.\n\t * This obscure code is the WORST result of the fact that we\n\t * don't really parse.\n\t */\n\tfor (wp = whyles; wp; wp = wp->w_next)\n\t\tif (wp->w_end == 0) {\n\t\t\tsearch(ZBREAK, 0);\n\t\t\twp->w_end = btell();\n\t\t} else\n\t\t\tbseek(wp->w_end);\n\tsearch(ZGOTO, 0, lp = globone(v[1]));\n\txfree(lp);\n\t/*\n\t * Eliminate loops which were exited.\n\t */\n\twfree();\n}\n\ndoswitch(v)\n\tregister char **v;\n{\n\tregister char *cp, *lp;\n\n\tv++;\n\tif (!*v || *(*v++) != '(')\n\t\tgoto syntax;\n\tcp = **v == ')' ? \"\" : *v++;\n\tif (*(*v++) != ')')\n\t\tv--;\n\tif (*v)\nsyntax:\n\t\terror(\"Syntax error\");\n\tsearch(ZSWITCH, 0, lp = globone(cp));\n\txfree(lp);\n}\n\ndobreak()\n{\n\n\tif (whyles)\n\t\ttoend();\n\telse\n\t\tbferr(\"Not in while/foreach\");\n}\n\ndoexit(v)\n\tchar **v;\n{\n\n\tif (chkstop == 0)\n\t\tpanystop(0);\n\t/*\n\t * Don't DEMAND parentheses here either.\n\t */\n\tv++;\n\tif (*v) {\n\t\tset(\"status\", putn(expr(&v)));\n\t\tif (*v)\n\t\t\tbferr(\"Expression syntax\");\n\t}\n\tbtoeof();\n\tif (intty)\n\t\t(void) close(SHIN);\n}\n\ndoforeach(v)\n\tregister char **v;\n{\n\tregister char *cp;\n\tregister struct whyle *nwp;\n\n\tv++;\n\tcp = strip(*v);\n\twhile (*cp && letter(*cp))\n\t\tcp++;\n\tif (*cp || strlen(*v) >= 20)\n\t\tbferr(\"Invalid variable\");\n\tcp = *v++;\n\tif (v[0][0] != '(' || v[blklen(v) - 1][0] != ')')\n\t\tbferr(\"Words not ()'ed\");\n\tv++;\n\tgflag = 0, tglob(v);\n\tv = glob(v);\n\tif (v == 0)\n\t\tbferr(\"No match\");\n\tnwp = (struct whyle *) calloc(1, sizeof *nwp);\n\tnwp->w_fe = nwp->w_fe0 = v; gargv = 0;\n\tnwp->w_start = btell();\n\tnwp->w_fename = savestr(cp);\n\tnwp->w_next = whyles;\n\twhyles = nwp;\n\t/*\n\t * Pre-read the loop so as to be more\n\t * comprehensible to a terminal user.\n\t */\n\tif (intty)\n\t\tpreread();\n\tdoagain();\n}\n\ndowhile(v)\n\tchar **v;\n{\n\tregister int status;\n\tregister bool again = whyles != 0 && whyles->w_start == lineloc &&\n\t    whyles->w_fename == 0;\n\n\tv++;\n\t/*\n\t * Implement prereading here also, taking care not to\n\t * evaluate the expression before the loop has been read up\n\t * from a terminal.\n\t */\n\tif (intty && !again)\n\t\tstatus = !exp0(&v, 1);\n\telse\n\t\tstatus = !expr(&v);\n\tif (*v)\n\t\tbferr(\"Expression syntax\");\n\tif (!again) {\n\t\tregister struct whyle *nwp = (struct whyle *) calloc(1, sizeof (*nwp));\n\n\t\tnwp->w_start = lineloc;\n\t\tnwp->w_end = 0;\n\t\tnwp->w_next = whyles;\n\t\twhyles = nwp;\n\t\tif (intty) {\n\t\t\t/*\n\t\t\t * The tty preread\n\t\t\t */\n\t\t\tpreread();\n\t\t\tdoagain();\n\t\t\treturn;\n\t\t}\n\t}\n\tif (status)\n\t\t/* We ain't gonna loop no more, no more! */\n\t\ttoend();\n}\n\npreread()\n{\n\n\twhyles->w_end = -1;\n\tif (setintr)\n\t\t(void) sigsetmask(sigblock(0L) & ~sigmask(SIGINT));\n\tsearch(ZBREAK, 0);\n\tif (setintr)\n\t\t(void) sigblock(sigmask(SIGINT));\n\twhyles->w_end = btell();\n}\n\ndoend()\n{\n\n\tif (!whyles)\n\t\tbferr(\"Not in while/foreach\");\n\twhyles->w_end = btell();\n\tdoagain();\n}\n\ndocontin()\n{\n\n\tif (!whyles)\n\t\tbferr(\"Not in while/foreach\");\n\tdoagain();\n}\n\ndoagain()\n{\n\n\t/* Repeating a while is simple */\n\tif (whyles->w_fename == 0) {\n\t\tbseek(whyles->w_start);\n\t\treturn;\n\t}\n\t/*\n\t * The foreach variable list actually has a spurious word\n\t * \")\" at the end of the w_fe list.  Thus we are at the\n\t * of the list if one word beyond this is 0.\n\t */\n\tif (!whyles->w_fe[1]) {\n\t\tdobreak();\n\t\treturn;\n\t}\n\tset(whyles->w_fename, savestr(*whyles->w_fe++));\n\tbseek(whyles->w_start);\n}\n\ndorepeat(v, kp)\n\tchar **v;\n\tstruct command *kp;\n{\n\tregister int i;\n\tregister long omask;\n\n\ti = getn(v[1]);\n\tif (setintr)\n\t\tomask = sigblock(sigmask(SIGINT)) & ~sigmask(SIGINT);\n\tlshift(v, 2);\n\twhile (i > 0) {\n\t\tif (setintr)\n\t\t\t(void) sigsetmask(omask);\n\t\treexecute(kp);\n\t\t--i;\n\t}\n\tdonefds();\n\tif (setintr)\n\t\t(void) sigsetmask(omask);\n}\n\ndoswbrk()\n{\n\n\tsearch(ZBRKSW, 0);\n}\n\nsrchx(cp)\n\tregister char *cp;\n{\n\tregister struct srch *sp, *sp1, *sp2;\n\tregister i;\n\n\t/*\n\t * Binary search\n\t * Sp1 is the beginning of the current search range.\n\t * Sp2 is one past the end.\n\t */\n\tfor (sp1 = srchn, sp2 = srchn + nsrchn; sp1 < sp2;) {\n\t\tsp = sp1 + (sp2 - sp1 >> 1);\n\t\tif ((i = *cp - *sp->s_name) == 0 &&\n\t\t    (i = strcmp(cp, sp->s_name)) == 0)\n\t\t\treturn sp->s_value;\n\t\tif (i < 0)\n\t\t\tsp2 = sp;\n\t\telse\n\t\t\tsp1 = sp + 1;\n\t}\n\treturn (-1);\n}\n\nchar\tStype;\nchar\t*Sgoal;\n\n/*VARARGS2*/\nsearch(type, level, goal)\n\tint type;\n\tregister int level;\n\tchar *goal;\n{\n\tchar wordbuf[BUFSIZ];\n\tregister char *aword = wordbuf;\n\tregister char *cp;\n\n\tStype = type; Sgoal = goal;\n\tif (type == ZGOTO)\n\t\tbseek((off_t)0);\n\tdo {\n\t\tif (intty && fseekp == feobp)\n\t\t\tprintf(\"? \"), flush();\n\t\taword[0] = 0;\n\t\t(void) getword(aword);\n\t\tswitch (srchx(aword)) {\n\n\t\tcase ZELSE:\n\t\t\tif (level == 0 && type == ZIF)\n\t\t\t\treturn;\n\t\t\tbreak;\n\n\t\tcase ZIF:\n\t\t\twhile (getword(aword))\n\t\t\t\tcontinue;\n\t\t\tif ((type == ZIF || type == ZELSE) && eq(aword, \"then\"))\n\t\t\t\tlevel++;\n\t\t\tbreak;\n\n\t\tcase ZENDIF:\n\t\t\tif (type == ZIF || type == ZELSE)\n\t\t\t\tlevel--;\n\t\t\tbreak;\n\n\t\tcase ZFOREACH:\n\t\tcase ZWHILE:\n\t\t\tif (type == ZBREAK)\n\t\t\t\tlevel++;\n\t\t\tbreak;\n\n\t\tcase ZEND:\n\t\t\tif (type == ZBREAK)\n\t\t\t\tlevel--;\n\t\t\tbreak;\n\n\t\tcase ZSWITCH:\n\t\t\tif (type == ZSWITCH || type == ZBRKSW)\n\t\t\t\tlevel++;\n\t\t\tbreak;\n\n\t\tcase ZENDSW:\n\t\t\tif (type == ZSWITCH || type == ZBRKSW)\n\t\t\t\tlevel--;\n\t\t\tbreak;\n\n\t\tcase ZLABEL:\n\t\t\tif (type == ZGOTO && getword(aword) && eq(aword, goal))\n\t\t\t\tlevel = -1;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tif (type != ZGOTO && (type != ZSWITCH || level != 0))\n\t\t\t\tbreak;\n\t\t\tif (lastchr(aword) != ':')\n\t\t\t\tbreak;\n\t\t\taword[strlen(aword) - 1] = 0;\n\t\t\tif (type == ZGOTO && eq(aword, goal) || type == ZSWITCH && eq(aword, \"default\"))\n\t\t\t\tlevel = -1;\n\t\t\tbreak;\n\n\t\tcase ZCASE:\n\t\t\tif (type != ZSWITCH || level != 0)\n\t\t\t\tbreak;\n\t\t\t(void) getword(aword);\n\t\t\tif (lastchr(aword) == ':')\n\t\t\t\taword[strlen(aword) - 1] = 0;\n\t\t\tcp = strip(Dfix1(aword));\n\t\t\tif (Gmatch(goal, cp))\n\t\t\t\tlevel = -1;\n\t\t\txfree(cp);\n\t\t\tbreak;\n\n\t\tcase ZDEFAULT:\n\t\t\tif (type == ZSWITCH && level == 0)\n\t\t\t\tlevel = -1;\n\t\t\tbreak;\n\t\t}\n\t\t(void) getword(NOSTR);\n\t} while (level >= 0);\n}\n\ngetword(wp)\n\tregister char *wp;\n{\n\tregister int found = 0;\n\tregister int c, d;\n\n\tc = readc(1);\n\td = 0;\n\tdo {\n\t\twhile (c == ' ' || c == '\\t')\n\t\t\tc = readc(1);\n\t\tif (c == '#')\n\t\t\tdo\n\t\t\t\tc = readc(1);\n\t\t\twhile (c >= 0 && c != '\\n');\n\t\tif (c < 0)\n\t\t\tgoto past;\n\t\tif (c == '\\n') {\n\t\t\tif (wp)\n\t\t\t\tbreak;\n\t\t\treturn (0);\n\t\t}\n\t\tunreadc(c);\n\t\tfound = 1;\n\t\tdo {\n\t\t\tc = readc(1);\n\t\t\tif (c == '\\\\' && (c = readc(1)) == '\\n')\n\t\t\t\tc = ' ';\n\t\t\tif (c == '\\'' || c == '\"')\n\t\t\t\tif (d == 0)\n\t\t\t\t\td = c;\n\t\t\t\telse if (d == c)\n\t\t\t\t\td = 0;\n\t\t\tif (c < 0)\n\t\t\t\tgoto past;\n\t\t\tif (wp)\n\t\t\t\t*wp++ = c;\n\t\t} while ((d || c != ' ' && c != '\\t') && c != '\\n');\n\t} while (wp == 0);\n\tunreadc(c);\n\tif (found)\n\t\t*--wp = 0;\n\treturn (found);\n\npast:\n\tswitch (Stype) {\n\n\tcase ZIF:\n\t\tbferr(\"then/endif not found\");\n\n\tcase ZELSE:\n\t\tbferr(\"endif not found\");\n\n\tcase ZBRKSW:\n\tcase ZSWITCH:\n\t\tbferr(\"endsw not found\");\n\n\tcase ZBREAK:\n\t\tbferr(\"end not found\");\n\n\tcase ZGOTO:\n\t\tsetname(Sgoal);\n\t\tbferr(\"label not found\");\n\t}\n\t/*NOTREACHED*/\n}\n\ntoend()\n{\n\n\tif (whyles->w_end == 0) {\n\t\tsearch(ZBREAK, 0);\n\t\twhyles->w_end = btell() - 1;\n\t} else\n\t\tbseek(whyles->w_end);\n\twfree();\n}\n\nwfree()\n{\n\tlong o = btell();\n\n\twhile (whyles) {\n\t\tregister struct whyle *wp = whyles;\n\t\tregister struct whyle *nwp = wp->w_next;\n\n\t\tif (o >= wp->w_start && (wp->w_end == 0 || o < wp->w_end))\n\t\t\tbreak;\n\t\tif (wp->w_fe0)\n\t\t\tblkfree(wp->w_fe0);\n\t\tif (wp->w_fename)\n\t\t\txfree(wp->w_fename);\n\t\txfree((char *)wp);\n\t\twhyles = nwp;\n\t}\n}\n\ndoecho(v)\n\tchar **v;\n{\n\n\techo(' ', v);\n}\n\ndoglob(v)\n\tchar **v;\n{\n\n\techo(0, v);\n\tflush();\n}\n\necho(sep, v)\n\tchar sep;\n\tregister char **v;\n{\n\tregister char *cp;\n\tint nonl = 0;\n\n\tif (setintr)\n\t\t(void) sigsetmask(sigblock(0L) & ~sigmask(SIGINT));\n\tv++;\n\tif (*v == 0)\n\t\treturn;\n\tgflag = 0, tglob(v);\n\tif (gflag) {\n\t\tv = glob(v);\n\t\tif (v == 0)\n\t\t\tbferr(\"No match\");\n\t} else\n\t\ttrim(v);\n\tif (sep == ' ' && *v && !strcmp(*v, \"-n\"))\n\t\tnonl++, v++;\n\twhile (cp = *v++) {\n\t\tregister int c;\n\n\t\twhile (c = *cp++)\n\t\t\tputchar(c | QUOTE);\n\t\tif (*v)\n\t\t\tputchar(sep | QUOTE);\n\t}\n\tif (sep && nonl == 0)\n\t\tputchar('\\n');\n\telse\n\t\tflush();\n\tif (setintr)\n\t\t(void) sigblock(sigmask(SIGINT));\n\tif (gargv)\n\t\tblkfree(gargv), gargv = 0;\n}\n\nchar\t**environ;\n\ndosetenv(v)\n\tregister char **v;\n{\n\tchar *vp, *lp;\n\n\tv++;\n\tif ((vp = *v++) == 0) {\n\t\tregister char **ep;\n\n\t\tif (setintr)\n\t\t\t(void) sigsetmask(sigblock(0L) & ~ sigmask(SIGINT));\n\t\tfor (ep = environ; *ep; ep++)\n\t\t\tprintf(\"%s\\n\", *ep);\n\t\treturn;\n\t}\n\tif ((lp = *v++) == 0)\n\t\tlp = \"\";\n\tsetenvv(vp, lp = globone(lp));\n\tif (eq(vp, \"PATH\")) {\n\t\timportpath(lp);\n\t\tdohash();\n\t}\n\txfree(lp);\n}\n\ndounsetenv(v)\n\tregister char **v;\n{\n\tv++;\n\tdo\n\t\tunsetenvv(*v++);\n\twhile (*v);\n}\n\nsetenvv(name, val)\n\tchar *name, *val;\n{\n\tregister char **ep = environ;\n\tregister char *cp, *dp;\n\tchar *blk[2], **oep = ep;\n\n\tfor (; *ep; ep++) {\n\t\tfor (cp = name, dp = *ep; *cp && *cp == *dp; cp++, dp++)\n\t\t\tcontinue;\n\t\tif (*cp != 0 || *dp != '=')\n\t\t\tcontinue;\n\t\tcp = strspl(\"=\", val);\n\t\txfree(*ep);\n\t\t*ep = strspl(name, cp);\n\t\txfree(cp);\n\t\ttrim(ep);\n\t\treturn;\n\t}\n\tblk[0] = strspl(name, \"=\"); blk[1] = 0;\n\tenviron = blkspl(environ, blk);\n\txfree((char *)oep);\n\tsetenvv(name, val);\n}\n\nunsetenvv(name)\n\tchar *name;\n{\n\tregister char **ep = environ;\n\tregister char *cp, *dp;\n\tchar **oep = ep;\n\n\tfor (; *ep; ep++) {\n\t\tfor (cp = name, dp = *ep; *cp && *cp == *dp; cp++, dp++)\n\t\t\tcontinue;\n\t\tif (*cp != 0 || *dp != '=')\n\t\t\tcontinue;\n\t\tcp = *ep;\n\t\t*ep = 0;\n\t\tenviron = blkspl(environ, ep+1);\n\t\t*ep = cp;\n\t\txfree(cp);\n\t\txfree((char *)oep);\n\t\treturn;\n\t}\n}\n\ndoumask(v)\n\tregister char **v;\n{\n\tregister char *cp = v[1];\n\tregister int i;\n\n\tif (cp == 0) {\n\t\ti = umask(0);\n\t\t(void) umask(i);\n\t\tprintf(\"%o\\n\", i);\n\t\treturn;\n\t}\n\ti = 0;\n\twhile (digit(*cp) && *cp != '8' && *cp != '9')\n\t\ti = i * 8 + *cp++ - '0';\n\tif (*cp || i < 0 || i > 0777)\n\t\tbferr(\"Improper mask\");\n\t(void) umask(i);\n}\n\n\n#ifndef NOLIMITS\nstruct limits {\n\tint\tlimconst;\n\tchar\t*limname;\n\tint\tlimdiv;\n\tchar\t*limscale;\n} limits[] = {\n\tRLIMIT_CPU,\t\"cputime\",\t1,\t\"seconds\",\n\tRLIMIT_FSIZE,\t\"filesize\",\t1024,\t\"kbytes\",\n\tRLIMIT_DATA,\t\"datasize\",\t1024,\t\"kbytes\",\n\tRLIMIT_STACK,\t\"stacksize\",\t1024,\t\"kbytes\",\n\tRLIMIT_CORE,\t\"coredumpsize\",\t1024,\t\"kbytes\",\n\tRLIMIT_RSS,\t\"memoryuse\",\t1024,\t\"kbytes\",\n\t-1,\t\t0,\n};\n\nstruct limits *\nfindlim(cp)\n\tchar *cp;\n{\n\tregister struct limits *lp, *res;\n\n\tres = 0;\n\tfor (lp = limits; lp->limconst >= 0; lp++)\n\t\tif (prefix(cp, lp->limname)) {\n\t\t\tif (res)\n\t\t\t\tbferr(\"Ambiguous\");\n\t\t\tres = lp;\n\t\t}\n\tif (res)\n\t\treturn (res);\n\tbferr(\"No such limit\");\n\t/*NOTREACHED*/\n}\n\ndolimit(v)\n\tregister char **v;\n{\n\tregister struct limits *lp;\n\tregister long limit;\n\tlong getval();\n\tchar hard = 0;\n\n\tv++;\n\tif (*v && eq(*v, \"-h\")) {\n\t\thard = 1;\n\t\tv++;\n\t}\n\tif (*v == 0) {\n\t\tfor (lp = limits; lp->limconst >= 0; lp++)\n\t\t\tplim(lp, hard);\n\t\treturn;\n\t}\n\tlp = findlim(v[0]);\n\tif (v[1] == 0) {\n\t\tplim(lp,  hard);\n\t\treturn;\n\t}\n\tlimit = getval(lp, v+1);\n\tif (setlim(lp, hard, limit) < 0)\n\t\terror(NOSTR);\n}\n\nlong\ngetval(lp, v)\n\tregister struct limits *lp;\n\tchar **v;\n{\n\tregister float f;\n\tdouble atof();\n\tchar *cp = *v++;\n\n\tf = atof(cp);\n\twhile (digit(*cp) || *cp == '.' || *cp == 'e' || *cp == 'E')\n\t\tcp++;\n\tif (*cp == 0) {\n\t\tif (*v == 0)\n\t\t\treturn ((long)(f+0.5) * lp->limdiv);\n\t\tcp = *v;\n\t}\n\tswitch (*cp) {\n\n\tcase ':':\n\t\tif (lp->limconst != RLIMIT_CPU)\n\t\t\tgoto badscal;\n\t\treturn ((long)(f * 60.0 + atof(cp+1)));\n\n\tcase 'h':\n\t\tif (lp->limconst != RLIMIT_CPU)\n\t\t\tgoto badscal;\n\t\tlimtail(cp, \"hours\");\n\t\tf *= 3600.;\n\t\tbreak;\n\n\tcase 'm':\n\t\tif (lp->limconst == RLIMIT_CPU) {\n\t\t\tlimtail(cp, \"minutes\");\n\t\t\tf *= 60.;\n\t\t\tbreak;\n\t\t}\n\tcase 'M':\n\t\tif (lp->limconst == RLIMIT_CPU)\n\t\t\tgoto badscal;\n\t\t*cp = 'm';\n\t\tlimtail(cp, \"megabytes\");\n\t\tf *= 1024.*1024.;\n\t\tbreak;\n\n\tcase 's':\n\t\tif (lp->limconst != RLIMIT_CPU)\n\t\t\tgoto badscal;\n\t\tlimtail(cp, \"seconds\");\n\t\tbreak;\n\n\tcase 'k':\n\t\tif (lp->limconst == RLIMIT_CPU)\n\t\t\tgoto badscal;\n\t\tlimtail(cp, \"kbytes\");\n\t\tf *= 1024;\n\t\tbreak;\n\n\tcase 'u':\n\t\tlimtail(cp, \"unlimited\");\n\t\treturn (RLIM_INFINITY);\n\n\tdefault:\nbadscal:\n\t\tbferr(\"Improper or unknown scale factor\");\n\t}\n\treturn ((long)(f+0.5));\n}\n\nlimtail(cp, str0)\n\tchar *cp, *str0;\n{\n\tregister char *str = str0;\n\n\twhile (*cp && *cp == *str)\n\t\tcp++, str++;\n\tif (*cp)\n\t\terror(\"Bad scaling; did you mean ``%s''?\", str0);\n}\n\nplim(lp, hard)\n\tregister struct limits *lp;\n\tchar hard;\n{\n\tstruct rlimit rlim;\n\tlong limit;\n\n\tprintf(\"%s \\t\", lp->limname);\n\t(void) getrlimit(lp->limconst, &rlim);\n\tlimit = hard ? rlim.rlim_max : rlim.rlim_cur;\n\tif (limit == RLIM_INFINITY)\n\t\tprintf(\"unlimited\");\n\telse if (lp->limconst == RLIMIT_CPU)\n\t\tpsecs((long)limit);\n\telse\n\t\tprintf(\"%ld %s\", limit / lp->limdiv, lp->limscale);\n\tprintf(\"\\n\");\n}\n\ndounlimit(v)\n\tregister char **v;\n{\n\tregister struct limits *lp;\n\tint parserr = 0;\n\tchar hard = 0;\n\n\tv++;\n\tif (*v && eq(*v, \"-h\")) {\n\t\thard = 1;\n\t\tv++;\n\t}\n\tif (*v == 0) {\n\t\tfor (lp = limits; lp->limconst >= 0; lp++)\n\t\t\tif (setlim(lp, hard, (long)RLIM_INFINITY) < 0)\n\t\t\t\tparserr++;\n\t\tif (parserr)\n\t\t\terror(NOSTR);\n\t\treturn;\n\t}\n\twhile (*v) {\n\t\tlp = findlim(*v++);\n\t\tif (setlim(lp, hard, (long)RLIM_INFINITY) < 0)\n\t\t\terror(NOSTR);\n\t}\n}\n\nsetlim(lp, hard, limit)\n\tregister struct limits *lp;\n\tchar hard;\n\tlong limit;\n{\n\tstruct rlimit rlim;\n\n\t(void) getrlimit(lp->limconst, &rlim);\n\tif (hard)\n\t\trlim.rlim_max = limit;\n  \telse if (limit == RLIM_INFINITY && geteuid() != 0)\n \t\trlim.rlim_cur = rlim.rlim_max;\n \telse\n \t\trlim.rlim_cur = limit;\n\tif (setrlimit(lp->limconst, &rlim) < 0) {\n\t\tprintf(\"%s: %s: Can't %s%s limit\\n\", bname, lp->limname,\n\t\t    limit == RLIM_INFINITY ? \"remove\" : \"set\",\n\t\t    hard ? \" hard\" : \"\");\n\t\treturn (-1);\n\t}\n\treturn (0);\n}\n#endif /* !NOLIMITS */\n\ndosuspend()\n{\n\tint ldisc, ctpgrp;\n\tvoid (*old)(int);\n\n\tif (loginsh)\n\t\terror(\"Can't suspend a login shell (yet)\");\n\tuntty();\n\told = signal(SIGTSTP, SIG_DFL);\n\t(void) kill(0, SIGTSTP);\n\t/* the shell stops here */\n\t(void) signal(SIGTSTP, old);\n\tif (tpgrp != -1) {\nretry:\n\t\t(void) ioctl(FSHTTY, TIOCGPGRP, (char *)&ctpgrp);\n\t\tif (ctpgrp != opgrp) {\n\t\t\told = signal(SIGTTIN, SIG_DFL);\n\t\t\t(void) kill(0, SIGTTIN);\n\t\t\t(void) signal(SIGTTIN, old);\n\t\t\tgoto retry;\n\t\t}\n\t\t(void) ioctl(FSHTTY, TIOCSPGRP, (char *)&shpgrp);\n\t\t(void) setpgrp(0, shpgrp);\n\t}\n\t(void) ioctl(FSHTTY, TIOCGETD, (char *)&oldisc);\n\tif (oldisc != NTTYDISC) {\n\t\tprintf(\"Switching to new tty driver...\\n\");\n\t\tldisc = NTTYDISC;\n\t\t(void) ioctl(FSHTTY, TIOCSETD, (char *)&ldisc);\n\t}\n}\n\ndoeval(v)\n\tchar **v;\n{\n\tchar **oevalvec = evalvec;\n\tchar *oevalp = evalp;\n\tjmp_buf osetexit;\n\tint reenter;\n\tchar **gv = 0;\n\n\tv++;\n\tif (*v == 0)\n\t\treturn;\n\tgflag = 0, tglob(v);\n\tif (gflag) {\n\t\tgv = v = glob(v);\n\t\tgargv = 0;\n\t\tif (v == 0)\n\t\t\terror(\"No match\");\n\t\tv = copyblk(v);\n\t} else\n\t\ttrim(v);\n\tgetexit(osetexit);\n\treenter = 0;\n\tsetexit();\n\treenter++;\n\tif (reenter == 1) {\n\t\tevalvec = v;\n\t\tevalp = 0;\n\t\tprocess(0);\n\t}\n\tevalvec = oevalvec;\n\tevalp = oevalp;\n\tdoneinp = 0;\n\tif (gv)\n\t\tblkfree(gv);\n\tresexit(osetexit);\n\tif (reenter >= 2)\n\t\terror(NOSTR);\n}\n"
  },
  {
    "path": "bin/csh/sh.glob.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"sh.h\"\n#include <sys/dir.h>\n\n/*\n * C Shell\n */\n\nint\tglobcnt;\n\nchar\t*gpath, *gpathp, *lastgpathp;\nint\tglobbed;\nbool\tnoglob;\nbool\tnonomatch;\nchar\t*entp;\nchar\t**sortbas;\nint\tsortscmp();\n\n#define sort()\tqsort((char *)sortbas, &gargv[gargc] - sortbas, \\\n\t\t      sizeof(*sortbas), sortscmp), sortbas = &gargv[gargc]\n\n\nchar **\nglob(v)\n\tregister char **v;\n{\n\tchar agpath[BUFSIZ];\n\tchar *agargv[GAVSIZ];\n\n\tgpath = agpath; gpathp = gpath; *gpathp = 0;\n\tlastgpathp = &gpath[sizeof agpath - 2];\n\tginit(agargv); globcnt = 0;\n#ifdef GDEBUG\n\tprintf(\"glob entered: \"); blkpr(v); printf(\"\\n\");\n#endif\n\tnoglob = adrof(\"noglob\") != 0;\n\tnonomatch = adrof(\"nonomatch\") != 0;\n\tglobcnt = noglob | nonomatch;\n\twhile (*v)\n\t\tcollect(*v++);\n#ifdef GDEBUG\n\tprintf(\"glob done, globcnt=%d, gflag=%d: \", globcnt, gflag); blkpr(gargv); printf(\"\\n\");\n#endif\n\tif (globcnt == 0 && (gflag&1)) {\n\t\tblkfree(gargv), gargv = 0;\n\t\treturn (0);\n\t} else\n\t\treturn (gargv = copyblk(gargv));\n}\n\nginit(agargv)\n\tchar **agargv;\n{\n\n\tagargv[0] = 0; gargv = agargv; sortbas = agargv; gargc = 0;\n\tgnleft = NCARGS - 4;\n}\n\ncollect(as)\n\tregister char *as;\n{\n\tregister int i;\n\n\tif (any('`', as)) {\n#ifdef GDEBUG\n\t\tprintf(\"doing backp of %s\\n\", as);\n#endif\n\t\t(void) dobackp(as, 0);\n#ifdef GDEBUG\n\t\tprintf(\"backp done, acollect'ing\\n\");\n#endif\n\t\tfor (i = 0; i < pargc; i++)\n\t\t\tif (noglob) {\n\t\t\t\tGcat(pargv[i], \"\");\n\t\t\t\tsortbas = &gargv[gargc];\n\t\t\t} else\n\t\t\t\tacollect(pargv[i]);\n\t\tif (pargv)\n\t\t\tblkfree(pargv), pargv = 0;\n#ifdef GDEBUG\n\t\tprintf(\"acollect done\\n\");\n#endif\n\t} else if (noglob || eq(as, \"{\") || eq(as, \"{}\")) {\n\t\tGcat(as, \"\");\n\t\tsort();\n\t} else\n\t\tacollect(as);\n}\n\nacollect(as)\n\tregister char *as;\n{\n\tregister int ogargc = gargc;\n\n\tgpathp = gpath; *gpathp = 0; globbed = 0;\n\texpand(as);\n\tif (gargc == ogargc) {\n\t\tif (nonomatch) {\n\t\t\tGcat(as, \"\");\n\t\t\tsort();\n\t\t}\n\t} else\n\t\tsort();\n}\n\n/*\n * String compare for qsort.  Also used by filec code in sh.file.c.\n */\nsortscmp(a1, a2)\n\tchar **a1, **a2;\n{\n\n\t return (strcmp(*a1, *a2));\n}\n\nexpand(as)\n\tchar *as;\n{\n\tregister char *cs;\n\tregister char *sgpathp, *oldcs;\n\tstruct stat stb;\n\n\tsgpathp = gpathp;\n\tcs = as;\n\tif (*cs == '~' && gpathp == gpath) {\n\t\taddpath('~');\n\t\tfor (cs++; letter(*cs) || digit(*cs) || *cs == '-';)\n\t\t\taddpath(*cs++);\n\t\tif (!*cs || *cs == '/') {\n\t\t\tif (gpathp != gpath + 1) {\n\t\t\t\t*gpathp = 0;\n\t\t\t\tif (gethdir(gpath + 1))\n\t\t\t\t\terror(\"Unknown user: %s\", gpath + 1);\n\t\t\t\t(void) strcpy(gpath, gpath + 1);\n\t\t\t} else\n\t\t\t\t(void) strcpy(gpath, value(\"home\"));\n\t\t\tgpathp = strend(gpath);\n\t\t}\n\t}\n\twhile (!isglob(*cs)) {\n\t\tif (*cs == 0) {\n\t\t\tif (!globbed)\n\t\t\t\tGcat(gpath, \"\");\n\t\t\telse if (stat(gpath, &stb) >= 0) {\n\t\t\t\tGcat(gpath, \"\");\n\t\t\t\tglobcnt++;\n\t\t\t}\n\t\t\tgoto endit;\n\t\t}\n\t\taddpath(*cs++);\n\t}\n\toldcs = cs;\n\twhile (cs > as && *cs != '/')\n\t\tcs--, gpathp--;\n\tif (*cs == '/')\n\t\tcs++, gpathp++;\n\t*gpathp = 0;\n\tif (*oldcs == '{') {\n\t\t(void) execbrc(cs, NOSTR);\n\t\treturn;\n\t}\n\tmatchdir(cs);\nendit:\n\tgpathp = sgpathp;\n\t*gpathp = 0;\n}\n\nmatchdir(pattern)\n\tchar *pattern;\n{\n\tstruct stat stb;\n\tregister struct direct *dp;\n\tregister DIR *dirp;\n\n\tdirp = opendir(gpath);\n\tif (dirp == NULL) {\n\t\tif (globbed)\n\t\t\treturn;\n\t\tgoto patherr2;\n\t}\n\tif (fstat(dirfd(dirp), &stb) < 0)\n\t\tgoto patherr1;\n\tif (!S_ISDIR(stb.st_mode)) {\n\t\terrno = ENOTDIR;\n\t\tgoto patherr1;\n\t}\n\twhile ((dp = readdir(dirp)) != NULL) {\n\t\tif (dp->d_ino == 0)\n\t\t\tcontinue;\n\t\tif (match(dp->d_name, pattern)) {\n\t\t\tGcat(gpath, dp->d_name);\n\t\t\tglobcnt++;\n\t\t}\n\t}\n\tclosedir(dirp);\n\treturn;\n\npatherr1:\n\tclosedir(dirp);\npatherr2:\n\tPerror(gpath);\n}\n\nexecbrc(p, s)\n\tchar *p, *s;\n{\n\tchar restbuf[BUFSIZ + 2];\n\tregister char *pe, *pm, *pl;\n\tint brclev = 0;\n\tchar *lm, savec, *sgpathp;\n\n\tfor (lm = restbuf; *p != '{'; *lm++ = *p++)\n\t\tcontinue;\n\tfor (pe = ++p; *pe; pe++)\n\tswitch (*pe) {\n\n\tcase '{':\n\t\tbrclev++;\n\t\tcontinue;\n\n\tcase '}':\n\t\tif (brclev == 0)\n\t\t\tgoto pend;\n\t\tbrclev--;\n\t\tcontinue;\n\n\tcase '[':\n\t\tfor (pe++; *pe && *pe != ']'; pe++)\n\t\t\tcontinue;\n\t\tif (!*pe)\n\t\t\terror(\"Missing ]\");\n\t\tcontinue;\n\t}\npend:\n\tif (brclev || !*pe)\n\t\terror(\"Missing }\");\n\tfor (pl = pm = p; pm <= pe; pm++)\n\tswitch (*pm & (QUOTE|TRIM)) {\n\n\tcase '{':\n\t\tbrclev++;\n\t\tcontinue;\n\n\tcase '}':\n\t\tif (brclev) {\n\t\t\tbrclev--;\n\t\t\tcontinue;\n\t\t}\n\t\tgoto doit;\n\n\tcase ','|QUOTE:\n\tcase ',':\n\t\tif (brclev)\n\t\t\tcontinue;\ndoit:\n\t\tsavec = *pm;\n\t\t*pm = 0;\n\t\t(void) strcpy(lm, pl);\n\t\t(void) strcat(restbuf, pe + 1);\n\t\t*pm = savec;\n\t\tif (s == 0) {\n\t\t\tsgpathp = gpathp;\n\t\t\texpand(restbuf);\n\t\t\tgpathp = sgpathp;\n\t\t\t*gpathp = 0;\n\t\t} else if (amatch(s, restbuf))\n\t\t\treturn (1);\n\t\tsort();\n\t\tpl = pm + 1;\n\t\tcontinue;\n\n\tcase '[':\n\t\tfor (pm++; *pm && *pm != ']'; pm++)\n\t\t\tcontinue;\n\t\tif (!*pm)\n\t\t\terror(\"Missing ]\");\n\t\tcontinue;\n\t}\n\treturn (0);\n}\n\nmatch(s, p)\n\tchar *s, *p;\n{\n\tregister int c;\n\tregister char *sentp;\n\tchar sglobbed = globbed;\n\n\tif (*s == '.' && *p != '.')\n\t\treturn (0);\n\tsentp = entp;\n\tentp = s;\n\tc = amatch(s, p);\n\tentp = sentp;\n\tglobbed = sglobbed;\n\treturn (c);\n}\n\namatch(s, p)\n\tregister char *s, *p;\n{\n\tregister int scc;\n\tint ok, lc;\n\tchar *sgpathp;\n\tstruct stat stb;\n\tint c, cc;\n\n\tglobbed = 1;\n\tfor (;;) {\n\t\tscc = *s++ & TRIM;\n\t\tswitch (c = *p++) {\n\n\t\tcase '{':\n\t\t\treturn (execbrc(p - 1, s - 1));\n\n\t\tcase '[':\n\t\t\tok = 0;\n\t\t\tlc = 077777;\n\t\t\twhile (cc = *p++) {\n\t\t\t\tif (cc == ']') {\n\t\t\t\t\tif (ok)\n\t\t\t\t\t\tbreak;\n\t\t\t\t\treturn (0);\n\t\t\t\t}\n\t\t\t\tif (cc == '-') {\n\t\t\t\t\tif (lc <= scc && scc <= *p++)\n\t\t\t\t\t\tok++;\n\t\t\t\t} else\n\t\t\t\t\tif (scc == (lc = cc))\n\t\t\t\t\t\tok++;\n\t\t\t}\n\t\t\tif (cc == 0)\n\t\t\t\terror(\"Missing ]\");\n\t\t\tcontinue;\n\n\t\tcase '*':\n\t\t\tif (!*p)\n\t\t\t\treturn (1);\n\t\t\tif (*p == '/') {\n\t\t\t\tp++;\n\t\t\t\tgoto slash;\n\t\t\t}\n\t\t\tfor (s--; *s; s++)\n\t\t\t\tif (amatch(s, p))\n\t\t\t\t\treturn (1);\n\t\t\treturn (0);\n\n\t\tcase 0:\n\t\t\treturn (scc == 0);\n\n\t\tdefault:\n\t\t\tif ((c & TRIM) != scc)\n\t\t\t\treturn (0);\n\t\t\tcontinue;\n\n\t\tcase '?':\n\t\t\tif (scc == 0)\n\t\t\t\treturn (0);\n\t\t\tcontinue;\n\n\t\tcase '/':\n\t\t\tif (scc)\n\t\t\t\treturn (0);\nslash:\n\t\t\ts = entp;\n\t\t\tsgpathp = gpathp;\n\t\t\twhile (*s)\n\t\t\t\taddpath(*s++);\n\t\t\taddpath('/');\n\t\t\tif (stat(gpath, &stb) == 0 && S_ISDIR(stb.st_mode))\n\t\t\t\tif (*p == 0) {\n\t\t\t\t\tGcat(gpath, \"\");\n\t\t\t\t\tglobcnt++;\n\t\t\t\t} else\n\t\t\t\t\texpand(p);\n\t\t\tgpathp = sgpathp;\n\t\t\t*gpathp = 0;\n\t\t\treturn (0);\n\t\t}\n\t}\n}\n\nGmatch(s, p)\n\tregister char *s, *p;\n{\n\tregister int scc;\n\tint ok, lc;\n\tint c, cc;\n\n\tfor (;;) {\n\t\tscc = *s++ & TRIM;\n\t\tswitch (c = *p++) {\n\n\t\tcase '[':\n\t\t\tok = 0;\n\t\t\tlc = 077777;\n\t\t\twhile (cc = *p++) {\n\t\t\t\tif (cc == ']') {\n\t\t\t\t\tif (ok)\n\t\t\t\t\t\tbreak;\n\t\t\t\t\treturn (0);\n\t\t\t\t}\n\t\t\t\tif (cc == '-') {\n\t\t\t\t\tif (lc <= scc && scc <= *p++)\n\t\t\t\t\t\tok++;\n\t\t\t\t} else\n\t\t\t\t\tif (scc == (lc = cc))\n\t\t\t\t\t\tok++;\n\t\t\t}\n\t\t\tif (cc == 0)\n\t\t\t\tbferr(\"Missing ]\");\n\t\t\tcontinue;\n\n\t\tcase '*':\n\t\t\tif (!*p)\n\t\t\t\treturn (1);\n\t\t\tfor (s--; *s; s++)\n\t\t\t\tif (Gmatch(s, p))\n\t\t\t\t\treturn (1);\n\t\t\treturn (0);\n\n\t\tcase 0:\n\t\t\treturn (scc == 0);\n\n\t\tdefault:\n\t\t\tif ((c & TRIM) != scc)\n\t\t\t\treturn (0);\n\t\t\tcontinue;\n\n\t\tcase '?':\n\t\t\tif (scc == 0)\n\t\t\t\treturn (0);\n\t\t\tcontinue;\n\n\t\t}\n\t}\n}\n\nGcat(s1, s2)\n\tchar *s1, *s2;\n{\n\tregister char *p, *q;\n\tint n;\n\n\tfor (p = s1; *p++;)\n\t\t;\n\tfor (q = s2; *q++;)\n\t\t;\n\tgnleft -= (n = (p - s1) + (q - s2) - 1);\n\tif (gnleft <= 0 || ++gargc >= GAVSIZ)\n\t\terror(\"Arguments too long\");\n\tgargv[gargc] = 0;\n\tp = gargv[gargc - 1] = xalloc((unsigned)n);\n\tfor (q = s1; *p++ = *q++;)\n\t\t;\n\tfor (p--, q = s2; *p++ = *q++;)\n\t\t;\n}\n\naddpath(c)\n\tchar c;\n{\n\n\tif (gpathp >= lastgpathp)\n\t\terror(\"Pathname too long\");\n\t*gpathp++ = c & TRIM;\n\t*gpathp = 0;\n}\n\nrscan(t, f)\n\tregister char **t;\n\tint (*f)();\n{\n\tregister char *p;\n\n\twhile (p = *t++)\n\t\twhile (*p)\n\t\t\t(*f)(*p++);\n}\n\ntrim(t)\n\tregister char **t;\n{\n\tregister char *p;\n\n\twhile (p = *t++)\n\t\twhile (*p)\n\t\t\t*p++ &= TRIM;\n}\n\ntglob(t)\n\tregister char **t;\n{\n\tregister char *p, c;\n\n\twhile (p = *t++) {\n\t\tif (*p == '~')\n\t\t\tgflag |= 2;\n\t\telse if (*p == '{' && (p[1] == '\\0' || p[1] == '}' && p[2] == '\\0'))\n\t\t\tcontinue;\n\t\twhile (c = *p++)\n\t\t\tif (isglob(c))\n\t\t\t\tgflag |= c == '{' ? 2 : 1;\n\t}\n}\n\nchar *\nglobone(str)\n\tregister char *str;\n{\n\tchar *gv[2];\n\tregister char **gvp;\n\tregister char *cp;\n\n\tgv[0] = str;\n\tgv[1] = 0;\n\tgflag = 0;\n\ttglob(gv);\n\tif (gflag) {\n\t\tgvp = glob(gv);\n\t\tif (gvp == 0) {\n\t\t\tsetname(str);\n\t\t\tbferr(\"No match\");\n\t\t}\n\t\tcp = *gvp++;\n\t\tif (cp == 0)\n\t\t\tcp = \"\";\n\t\telse if (*gvp) {\n\t\t\tsetname(str);\n\t\t\tbferr(\"Ambiguous\");\n\t\t} else\n\t\t\tcp = strip(cp);\n/*\n\t\tif (cp == 0 || *gvp) {\n\t\t\tsetname(str);\n\t\t\tbferr(cp ? \"Ambiguous\" : \"No output\");\n\t\t}\n*/\n\t\txfree((char *)gargv); gargv = 0;\n\t} else {\n\t\ttrim(gv);\n\t\tcp = savestr(gv[0]);\n\t}\n\treturn (cp);\n}\n\n/*\n * Command substitute cp.  If literal, then this is\n * a substitution from a << redirection, and so we should\n * not crunch blanks and tabs, separating words only at newlines.\n */\nchar **\ndobackp(cp, literal)\n\tchar *cp;\n\tbool literal;\n{\n\tregister char *lp, *rp;\n\tchar *ep;\n\tchar word[BUFSIZ];\n\tchar *apargv[GAVSIZ + 2];\n\n\tif (pargv) {\n\t\tabort();\n\t\tblkfree(pargv);\n\t}\n\tpargv = apargv;\n\tpargv[0] = NOSTR;\n\tpargcp = pargs = word;\n\tpargc = 0;\n\tpnleft = BUFSIZ - 4;\n\tfor (;;) {\n\t\tfor (lp = cp; *lp != '`'; lp++) {\n\t\t\tif (*lp == 0) {\n\t\t\t\tif (pargcp != pargs)\n\t\t\t\t\tpword();\n#ifdef GDEBUG\n\t\t\t\tprintf(\"leaving dobackp\\n\");\n#endif\n\t\t\t\treturn (pargv = copyblk(pargv));\n\t\t\t}\n\t\t\tpsave(*lp);\n\t\t}\n\t\tlp++;\n\t\tfor (rp = lp; *rp && *rp != '`'; rp++)\n\t\t\tif (*rp == '\\\\') {\n\t\t\t\trp++;\n\t\t\t\tif (!*rp)\n\t\t\t\t\tgoto oops;\n\t\t\t}\n\t\tif (!*rp)\noops:\n\t\t\terror(\"Unmatched `\");\n\t\tep = savestr(lp);\n\t\tep[rp - lp] = 0;\n\t\tbackeval(ep, literal);\n#ifdef GDEBUG\n\t\tprintf(\"back from backeval\\n\");\n#endif\n\t\tcp = rp + 1;\n\t}\n}\n\nbackeval(cp, literal)\n\tchar *cp;\n\tbool literal;\n{\n\tint pvec[2];\n\tint quoted = (literal || (cp[0] & QUOTE)) ? QUOTE : 0;\n\tchar ibuf[BUFSIZ];\n\tregister int icnt = 0, c;\n\tregister char *ip;\n\tbool hadnl = 0;\n\tchar *fakecom[2];\n\tstruct command faket;\n\n\tfaket.t_dtyp = TCOM;\n\tfaket.t_dflg = 0;\n\tfaket.t_dlef = 0;\n\tfaket.t_drit = 0;\n\tfaket.t_dspr = 0;\n\tfaket.t_dcom = fakecom;\n\tfakecom[0] = \"` ... `\";\n\tfakecom[1] = 0;\n\t/*\n\t * We do the psave job to temporarily change the current job\n\t * so that the following fork is considered a separate job.\n\t * This is so that when backquotes are used in a\n\t * builtin function that calls glob the \"current job\" is not corrupted.\n\t * We only need one level of pushed jobs as long as we are sure to\n\t * fork here.\n\t */\n\tpsavejob();\n\t/*\n\t * It would be nicer if we could integrate this redirection more\n\t * with the routines in sh.sem.c by doing a fake execute on a builtin\n\t * function that was piped out.\n\t */\n\tmypipe(pvec);\n\tif (pfork(&faket, -1) == 0) {\n\t\tstruct wordent paraml;\n\t\tstruct command *t;\n\n\t\t(void) close(pvec[0]);\n\t\t(void) dmove(pvec[1], 1);\n\t\t(void) dmove(SHDIAG, 2);\n\t\tinitdesc();\n\t\targinp = cp;\n\t\twhile (*cp)\n\t\t\t*cp++ &= TRIM;\n\t\t(void) lex(&paraml);\n\t\tif (parserr)\n\t\t\terror(parserr);\n\t\talias(&paraml);\n\t\tt = syntax(paraml.next, &paraml, 0);\n\t\tif (parserr)\n\t\t\terror(parserr);\n\t\tif (t)\n\t\t\tt->t_dflg |= FPAR;\n\t\t(void) signal(SIGTSTP, SIG_IGN);\n\t\t(void) signal(SIGTTIN, SIG_IGN);\n\t\t(void) signal(SIGTTOU, SIG_IGN);\n\t\texecute(t, -1);\n\t\texitstat();\n\t}\n\txfree(cp);\n\t(void) close(pvec[1]);\n\tdo {\n\t\tint cnt = 0;\n\t\tfor (;;) {\n\t\t\tif (icnt == 0) {\n\t\t\t\tip = ibuf;\n\t\t\t\ticnt = read(pvec[0], ip, BUFSIZ);\n\t\t\t\tif (icnt <= 0) {\n\t\t\t\t\tc = -1;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (hadnl)\n\t\t\t\tbreak;\n\t\t\t--icnt;\n\t\t\tc = (*ip++ & TRIM);\n\t\t\tif (c == 0)\n\t\t\t\tbreak;\n\t\t\tif (c == '\\n') {\n\t\t\t\t/*\n\t\t\t\t * Continue around the loop one\n\t\t\t\t * more time, so that we can eat\n\t\t\t\t * the last newline without terminating\n\t\t\t\t * this word.\n\t\t\t\t */\n\t\t\t\thadnl = 1;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (!quoted && (c == ' ' || c == '\\t'))\n\t\t\t\tbreak;\n\t\t\tcnt++;\n\t\t\tpsave(c | quoted);\n\t\t}\n\t\t/*\n\t\t * Unless at end-of-file, we will form a new word\n\t\t * here if there were characters in the word, or in\n\t\t * any case when we take text literally.  If\n\t\t * we didn't make empty words here when literal was\n\t\t * set then we would lose blank lines.\n\t\t */\n\t\tif (c != -1 && (cnt || literal))\n\t\t\tpword();\n\t\thadnl = 0;\n\t} while (c >= 0);\n#ifdef GDEBUG\n\tprintf(\"done in backeval, pvec: %d %d\\n\", pvec[0], pvec[1]);\n\tprintf(\"also c = %c <%o>\\n\", c, c);\n#endif\n\t(void) close(pvec[0]);\n\tpwait();\n\tprestjob();\n}\n\npsave(c)\n\tchar c;\n{\n\n\tif (--pnleft <= 0)\n\t\terror(\"Word too long\");\n\t*pargcp++ = c;\n}\n\npword()\n{\n\n\tpsave(0);\n\tif (pargc == GAVSIZ)\n\t\terror(\"Too many words from ``\");\n\tpargv[pargc++] = savestr(pargs);\n\tpargv[pargc] = NOSTR;\n#ifdef GDEBUG\n\tprintf(\"got word %s\\n\", pargv[pargc-1]);\n#endif\n\tpargcp = pargs;\n\tpnleft = BUFSIZ - 4;\n}\n"
  },
  {
    "path": "bin/csh/sh.h",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)sh.h\t5.3.2 (2.11BSD GTE) 1996/9/20\n */\n#include <sys/time.h>\n#include <sys/resource.h>\n#include <sys/param.h>\n#include <sys/stat.h>\n#include <sys/signal.h>\n#include <errno.h>\n#include <setjmp.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n#include \"sh.local.h\"\n#include \"sh.char.h\"\n\n/*\n * C shell\n *\n * Bill Joy, UC Berkeley\n * October, 1978; May 1980\n *\n * Jim Kulp, IIASA, Laxenburg Austria\n * April, 1980\n */\n\ntypedef\tint\tbool;\n\n#define\teq(a, b)\t(strcmp(a, b) == 0)\n\n#define printf          shprintf\n\n/*\n * Global flags\n */\nbool\tchkstop;\t\t/* Warned of stopped jobs... allow exit */\nbool\tdidfds;\t\t\t/* Have setup i/o fd's for child */\nbool\tdoneinp;\t\t/* EOF indicator after reset from readc */\nbool\texiterr;\t\t/* Exit if error or non-zero exit status */\nbool\tchild;\t\t\t/* Child shell ... errors cause exit */\nbool\thaderr;\t\t\t/* Reset was because of an error */\nbool\tintty;\t\t\t/* Input is a tty */\nbool\tintact;\t\t\t/* We are interactive... therefore prompt */\nbool\tjustpr;\t\t\t/* Just print because of :p hist mod */\nbool\tloginsh;\t\t/* We are a loginsh -> .login/.logout */\nbool\tneednote;\t\t/* Need to pnotify() */\nbool\tnoexec;\t\t\t/* Don't execute, just syntax check */\nbool\tpjobs;\t\t\t/* want to print jobs if interrupted */\nbool\tsetintr;\t\t/* Set interrupts on/off -> Wait intr... */\nbool\ttimflg;\t\t\t/* Time the next waited for command */\nbool\thavhash;\t\t/* path hashing is available */\n#ifdef FILEC\nbool\tfilec;\t\t\t/* doing filename expansion */\n#endif\n\n/*\n * Global i/o info\n */\nchar\t*arginp;\t\t/* Argument input for sh -c and internal `xx` */\nint\tonelflg;\t\t/* 2 -> need line for -t, 1 -> exit on read */\nchar\t*file;\t\t\t/* Name of shell file for $0 */\n\nchar\t*parserr;\t\t/* Error message from scanner/parser */\nint\terrno;\t\t\t/* Error from C library routines */\nchar\t*shtemp;\t\t/* Temp name for << shell files in /tmp */\nstruct\ttimeval time0;\t\t/* Time at which the shell started */\nstruct\trusage ru0;\n\n/*\n * Miscellany\n */\nchar\t*doldol;\t\t/* Character pid for $$ */\nint\tuid;\t\t\t/* Invokers uid */\ntime_t\tchktim;\t\t\t/* Time mail last checked */\nint\tshpgrp;\t\t\t/* Pgrp of shell */\nint\ttpgrp;\t\t\t/* Terminal process group */\n/* If tpgrp is -1, leave tty alone! */\nint\topgrp;\t\t\t/* Initial pgrp and tty pgrp */\nint\toldisc;\t\t\t/* Initial line discipline or -1 */\n\n/*\n * These are declared here because they want to be\n * initialized in sh.init.c (to allow them to be made readonly)\n */\nstruct\tbiltins {\n\tchar\t*bname;\n\tint\t(*bfunct)();\n\tint\tminargs, maxargs;\n};\nextern struct biltins bfunc[];\nextern int nbfunc;\n\nstruct srch {\n\tchar\t*s_name;\n\tint\ts_value;\n};\nextern struct srch srchn[];\nextern int nsrchn;\n\n/*\n * To be able to redirect i/o for builtins easily, the shell moves the i/o\n * descriptors it uses away from 0,1,2.\n * Ideally these should be in units which are closed across exec's\n * (this saves work) but for version 6, this is not usually possible.\n * The desired initial values for these descriptors are defined in\n * sh.local.h.\n */\nint\tSHIN;\t\t\t/* Current shell input (script) */\nint\tSHOUT;\t\t\t/* Shell output */\nint\tSHDIAG;\t\t\t/* Diagnostic output... shell errs go here */\nint\tOLDSTD;\t\t\t/* Old standard input (def for cmds) */\n\n/*\n * Error control\n *\n * Errors in scanning and parsing set up an error message to be printed\n * at the end and complete.  Other errors always cause a reset.\n * Because of source commands and .cshrc we need nested error catches.\n */\n\njmp_buf\treslab;\n\n#define\tsetexit()\t((void) setjmp(reslab))\n#define\treset()\t\tlongjmp(reslab, 0)\n\t/* Should use structure assignment here */\n#define\tgetexit(a)\tmemcpy((char *)(a), (char *)reslab, sizeof reslab)\n#define\tresexit(a)\tmemcpy((char *)reslab, ((char *)(a)), sizeof reslab)\n\nchar\t*gointr;\t\t/* Label for an onintr transfer */\nvoid\t(*parintr)(int);\t/* Parents interrupt catch */\nvoid\t(*parterm)(int);\t/* Parents terminate catch */\n\n/*\n * Lexical definitions.\n *\n * All lexical space is allocated dynamically.\n * The eighth bit of characters is used to prevent recognition,\n * and eventually stripped.\n */\n#define\tQUOTE \t0200\t\t/* Eighth char bit used internally for 'ing */\n#define\tTRIM\t0177\t\t/* Mask to strip quote bit */\n\n/*\n * Each level of input has a buffered input structure.\n * There are one or more blocks of buffered input for each level,\n * exactly one if the input is seekable and tell is available.\n * In other cases, the shell buffers enough blocks to keep all loops\n * in the buffer.\n */\nstruct\tBin {\n\toff_t\tBfseekp;\t\t/* Seek pointer */\n\toff_t\tBfbobp;\t\t\t/* Seekp of beginning of buffers */\n\toff_t\tBfeobp;\t\t\t/* Seekp of end of buffers */\n\tint\tBfblocks;\t\t/* Number of buffer blocks */\n\tchar\t**Bfbuf;\t\t/* The array of buffer blocks */\n} B;\n\n#define\tfseekp\tB.Bfseekp\n#define\tfbobp\tB.Bfbobp\n#define\tfeobp\tB.Bfeobp\n#define\tfblocks\tB.Bfblocks\n#define\tfbuf\tB.Bfbuf\n\n#define btell()\tfseekp\n\n#ifndef btell\noff_t\tbtell();\n#endif\n\n/*\n * The shell finds commands in loops by reseeking the input\n * For whiles, in particular, it reseeks to the beginning of the\n * line the while was on; hence the while placement restrictions.\n */\noff_t\tlineloc;\n\n#ifdef\tTELL\nbool\tcantell;\t\t\t/* Is current source tellable ? */\n#endif\n\n/*\n * Input lines are parsed into doubly linked circular\n * lists of words of the following form.\n */\nstruct\twordent {\n\tchar\t*word;\n\tstruct\twordent *prev;\n\tstruct\twordent *next;\n};\n\n/*\n * During word building, both in the initial lexical phase and\n * when expanding $ variable substitutions, expansion by `!' and `$'\n * must be inhibited when reading ahead in routines which are themselves\n * processing `!' and `$' expansion or after characters such as `\\' or in\n * quotations.  The following flags are passed to the getC routines\n * telling them which of these substitutions are appropriate for the\n * next character to be returned.\n */\n#define\tDODOL\t1\n#define\tDOEXCL\t2\n#define\tDOALL\tDODOL|DOEXCL\n\n/*\n * Labuf implements a general buffer for lookahead during lexical operations.\n * Text which is to be placed in the input stream can be stuck here.\n * We stick parsed ahead $ constructs during initial input,\n * process id's from `$$', and modified variable values (from qualifiers\n * during expansion in sh.dol.c) here.\n */\nchar\tlabuf[BUFSIZ];\n\nchar\t*lap;\n\n/*\n * Parser structure\n *\n * Each command is parsed to a tree of command structures and\n * flags are set bottom up during this process, to be propagated down\n * as needed during the semantics/exeuction pass (sh.sem.c).\n */\nstruct\tcommand {\n\tint\tt_dtyp;\t\t\t\t/* Type of node */\n\tint\tt_dflg;\t\t\t\t/* Flags, e.g. FAND|... */\n\tunion {\n\t\tchar\t*T_dlef;\t\t/* Input redirect word */\n\t\tstruct\tcommand *T_dcar;\t/* Left part of list/pipe */\n\t} L;\n\tunion {\n\t\tchar\t*T_drit;\t\t/* Output redirect word */\n\t\tstruct\tcommand *T_dcdr;\t/* Right part of list/pipe */\n\t} R;\n#define\tt_dlef\tL.T_dlef\n#define\tt_dcar\tL.T_dcar\n#define\tt_drit\tR.T_drit\n#define\tt_dcdr\tR.T_dcdr\n\tchar\t**t_dcom;\t\t\t/* Command/argument vector */\n\tstruct\tcommand *t_dspr;\t\t/* Pointer to ()'d subtree */\n\tint\tt_nice;\n};\n\n#define\tTCOM\t1\t\t/* t_dcom <t_dlef >t_drit\t*/\n#define\tTPAR\t2\t\t/* ( t_dspr ) <t_dlef >t_drit\t*/\n#define\tTFIL\t3\t\t/* t_dlef | t_drit\t\t*/\n#define\tTLST\t4\t\t/* t_dlef ; t_drit\t\t*/\n#define\tTOR\t5\t\t/* t_dlef || t_drit\t\t*/\n#define\tTAND\t6\t\t/* t_dlef && t_drit\t\t*/\n\n#define\tFSAVE\t(FNICE|FTIME|FNOHUP)\t/* save these when re-doing */\n\n#define\tFAND\t(1<<0)\t\t/* executes in background\t*/\n#define\tFCAT\t(1<<1)\t\t/* output is redirected >>\t*/\n#define\tFPIN\t(1<<2)\t\t/* input is a pipe\t\t*/\n#define\tFPOU\t(1<<3)\t\t/* output is a pipe\t\t*/\n#define\tFPAR\t(1<<4)\t\t/* don't fork, last ()ized cmd\t*/\n#define\tFINT\t(1<<5)\t\t/* should be immune from intr's */\n/* spare */\n#define\tFDIAG\t(1<<7)\t\t/* redirect unit 2 with unit 1\t*/\n#define\tFANY\t(1<<8)\t\t/* output was !\t\t\t*/\n#define\tFHERE\t(1<<9)\t\t/* input redirection is <<\t*/\n#define\tFREDO\t(1<<10)\t\t/* reexec aft if, repeat,...\t*/\n#define\tFNICE\t(1<<11)\t\t/* t_nice is meaningful */\n#define\tFNOHUP\t(1<<12)\t\t/* nohup this command */\n#define\tFTIME\t(1<<13)\t\t/* time this command */\n\n/*\n * The keywords for the parser\n */\n#define\tZBREAK\t\t0\n#define\tZBRKSW\t\t1\n#define\tZCASE\t\t2\n#define\tZDEFAULT \t3\n#define\tZELSE\t\t4\n#define\tZEND\t\t5\n#define\tZENDIF\t\t6\n#define\tZENDSW\t\t7\n#define\tZEXIT\t\t8\n#define\tZFOREACH\t9\n#define\tZGOTO\t\t10\n#define\tZIF\t\t11\n#define\tZLABEL\t\t12\n#define\tZLET\t\t13\n#define\tZSET\t\t14\n#define\tZSWITCH\t\t15\n#define\tZTEST\t\t16\n#define\tZTHEN\t\t17\n#define\tZWHILE\t\t18\n\n/*\n * Structure defining the existing while/foreach loops at this\n * source level.  Loops are implemented by seeking back in the\n * input.  For foreach (fe), the word list is attached here.\n */\nstruct\twhyle {\n\toff_t\tw_start;\t\t/* Point to restart loop */\n\toff_t\tw_end;\t\t\t/* End of loop (0 if unknown) */\n\tchar\t**w_fe, **w_fe0;\t/* Current/initial wordlist for fe */\n\tchar\t*w_fename;\t\t/* Name for fe */\n\tstruct\twhyle *w_next;\t\t/* Next (more outer) loop */\n} *whyles;\n\n/*\n * Variable structure\n *\n * Aliases and variables are stored in AVL balanced binary trees.\n */\nstruct\tvarent {\n\tchar\t**vec;\t\t/* Array of words which is the value */\n\tchar\t*v_name;\t/* Name of variable/alias */\n\tstruct\tvarent *v_link[3];\t/* The links, see below */\n\tint\tv_bal;\t\t/* Balance factor */\n} shvhed, aliases;\n#define v_left\t\tv_link[0]\n#define v_right\t\tv_link[1]\n#define v_parent\tv_link[2]\n\nstruct varent *adrof1();\n#define adrof(v)\tadrof1(v, &shvhed)\n#define value(v)\tvalue1(v, &shvhed)\n\n/*\n * The following are for interfacing redo substitution in\n * aliases to the lexical routines.\n */\nstruct\twordent *alhistp;\t\t/* Argument list (first) */\nstruct\twordent *alhistt;\t\t/* Node after last in arg list */\nchar\t**alvec;\t\t\t/* The (remnants of) alias vector */\n\n/*\n * Filename/command name expansion variables\n */\nint\tgflag;\t\t\t\t/* After tglob -> is globbing needed? */\n\n/*\n * A reasonable limit on number of arguments would seem to be\n * the maximum number of characters in an arg list / 6.\n */\n#ifdef pdp11\n#define\tGAVSIZ\tNCARGS / 12\n#else\n#define\tGAVSIZ\tNCARGS / 6\n#endif\n\n/*\n * Variables for filename expansion\n */\nchar\t**gargv;\t\t\t/* Pointer to the (stack) arglist */\nint\tgargc;\t\t\t\t/* Number args in gargv */\nint\tgnleft;\n\n/*\n * Variables for command expansion.\n */\nchar\t**pargv;\t\t\t/* Pointer to the argv list space */\nchar\t*pargs;\t\t\t\t/* Pointer to start current word */\nint\tpargc;\t\t\t\t/* Count of arguments in pargv */\nint\tpnleft;\t\t\t\t/* Number of chars left in pargs */\nchar\t*pargcp;\t\t\t/* Current index into pargs */\n\n/*\n * History list\n *\n * Each history list entry contains an embedded wordlist\n * from the scanner, a number for the event, and a reference count\n * to aid in discarding old entries.\n *\n * Essentially \"invisible\" entries are put on the history list\n * when history substitution includes modifiers, and thrown away\n * at the next discarding since their event numbers are very negative.\n */\nstruct\tHist {\n\tstruct\twordent Hlex;\n\tint\tHnum;\n\tint\tHref;\n\tstruct\tHist *Hnext;\n} Histlist;\n\nstruct\twordent\tparaml;\t\t\t/* Current lexical word list */\nint\teventno;\t\t\t/* Next events number */\nint\tlastev;\t\t\t\t/* Last event reference (default) */\n\nchar\tHIST;\t\t\t\t/* history invocation character */\nchar\tHISTSUB;\t\t\t/* auto-substitute character */\n\n/*\n * In lines for frequently called functions\n */\n#define XFREE(cp) { \\\n\textern char end[]; \\\n\tchar stack; \\\n\tif ((cp) >= end && (cp) < &stack) \\\n\t\tfree(cp); \\\n}\nchar\t*alloctmp;\n#define xalloc(i) ((alloctmp = malloc(i)) ? alloctmp : (char *)nomem(i))\n\nchar\t*Dfix1();\nchar\t**blkcat();\nchar\t**blkcpy();\nchar\t**blkend();\nchar\t**blkspl();\nchar\t*cname();\nchar\t**copyblk();\nchar\t**dobackp();\nchar\t*domod();\nstruct\twordent *dosub();\nchar\t*exp3();\nchar\t*exp3a();\nchar\t*exp4();\nchar\t*exp5();\nchar\t*exp6();\nstruct\tHist *enthist();\nstruct\tHist *findev();\nstruct\twordent *freenod();\nchar\t*getenv();\nchar\t*getinx();\nstruct\tvarent *getvx();\nstruct\tpasswd *getpwnam();\nstruct\twordent *gethent();\nstruct\twordent *getsub();\nchar\t*getwd();\nchar\t**glob();\nchar\t*globone();\nchar\t*index();\nstruct\tbiltins *isbfunc();\noff_t\tlseek();\nchar\t*operate();\nvoid\tpchild(int);\nvoid    pintr(int);\nint     printf(const char *format, ...);\nchar\t*putn();\nchar\t*rindex();\nchar\t**saveblk();\nchar\t*savestr();\nchar\t*strcat();\nchar\t*strcpy();\nchar\t*strend();\nchar\t*strings();\nchar\t*strip();\nchar\t*strspl();\nchar\t*subword();\nstruct\tcommand *syntax();\nstruct\tcommand *syn0();\nstruct\tcommand *syn1();\nstruct\tcommand *syn1a();\nstruct\tcommand *syn1b();\nstruct\tcommand *syn2();\nstruct\tcommand *syn3();\nchar\t*value1();\nchar\t*xhome();\nchar\t*xname();\nchar\t*xset();\n\n#define\tNOSTR\t((char *) 0)\n\n/*\n * setname is a macro to save space (see sh.err.c)\n */\nchar\t*bname;\n#define\tsetname(a)\t(bname = (a))\n\n#ifdef VFORK\nchar\t*Vsav;\nchar\t**Vav;\nchar\t*Vdp;\n#endif\n\nchar\t**evalvec;\nchar\t*evalp;\n\nstruct\tmesg {\n\tchar\t*iname;\t\t/* name from /usr/include */\n\tchar\t*pname;\t\t/* print name */\n};\nextern struct mesg mesg[];\n"
  },
  {
    "path": "bin/csh/sh.hist.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if\t!defined(lint) && defined(DOSCCS)\nstatic char *sccsid = \"@(#)sh.hist.c\t5.2 (Berkeley) 6/6/85\";\n#endif\n\n#include \"sh.h\"\n\n/*\n * C shell\n */\n\nsavehist(sp)\n\tstruct wordent *sp;\n{\n\tregister struct Hist *hp, *np;\n\tregister int histlen = 0;\n\tchar *cp;\n\n\t/* throw away null lines */\n\tif (sp->next->word[0] == '\\n')\n\t\treturn;\n\tcp = value(\"history\");\n\tif (*cp) {\n\t\tregister char *p = cp;\n\n\t\twhile (*p) {\n\t\t\tif (!digit(*p)) {\n\t\t\t\thistlen = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\thistlen = histlen * 10 + *p++ - '0';\n\t\t}\n\t}\n\tfor (hp = &Histlist; np = hp->Hnext;)\n\t\tif (eventno - np->Href >= histlen || histlen == 0)\n\t\t\thp->Hnext = np->Hnext, hfree(np);\n\t\telse\n\t\t\thp = np;\n\t(void) enthist(++eventno, sp, 1);\n}\n\nstruct Hist *\nenthist(event, lp, docopy)\n\tint event;\n\tregister struct wordent *lp;\n\tbool docopy;\n{\n\tregister struct Hist *np;\n\n\tnp = (struct Hist *) xalloc(sizeof *np);\n\tnp->Hnum = np->Href = event;\n\tif (docopy)\n\t\tcopylex(&np->Hlex, lp);\n\telse {\n\t\tnp->Hlex.next = lp->next;\n\t\tlp->next->prev = &np->Hlex;\n\t\tnp->Hlex.prev = lp->prev;\n\t\tlp->prev->next = &np->Hlex;\n\t}\n\tnp->Hnext = Histlist.Hnext;\n\tHistlist.Hnext = np;\n\treturn (np);\n}\n\nhfree(hp)\n\tregister struct Hist *hp;\n{\n\n\tfreelex(&hp->Hlex);\n\txfree((char *)hp);\n}\n\ndohist(vp)\n\tchar **vp;\n{\n\tint n, rflg = 0, hflg = 0;\n\tif (getn(value(\"history\")) == 0)\n\t\treturn;\n\tif (setintr)\n\t\t(void) sigsetmask(sigblock(0L) & ~sigmask(SIGINT));\n \twhile (*++vp && **vp == '-') {\n \t\tchar *vp2 = *vp;\n \n \t\twhile (*++vp2)\n \t\t\tswitch (*vp2) {\n \t\t\tcase 'h':\n \t\t\t\thflg++;\n \t\t\t\tbreak;\n \t\t\tcase 'r':\n \t\t\t\trflg++;\n \t\t\t\tbreak;\n \t\t\tcase '-':\t/* ignore multiple '-'s */\n \t\t\t\tbreak;\n \t\t\tdefault:\n \t\t\t\tprintf(\"Unknown flag: -%c\\n\", *vp2);\n \t\t\t\terror(\"Usage: history [-rh] [# number of events]\");\n\t\t\t}\n\t}\n\tif (*vp)\n\t\tn = getn(*vp);\n\telse {\n\t\tn = getn(value(\"history\"));\n\t}\n\tdohist1(Histlist.Hnext, &n, rflg, hflg);\n}\n\ndohist1(hp, np, rflg, hflg)\n\tstruct Hist *hp;\n\tint *np, rflg, hflg;\n{\n\tbool print = (*np) > 0;\ntop:\n\tif (hp == 0)\n\t\treturn;\n\t(*np)--;\n\thp->Href++;\n\tif (rflg == 0) {\n\t\tdohist1(hp->Hnext, np, rflg, hflg);\n\t\tif (print)\n\t\t\tphist(hp, hflg);\n\t\treturn;\n\t}\n\tif (*np >= 0)\n\t\tphist(hp, hflg);\n\thp = hp->Hnext;\n\tgoto top;\n}\n\nphist(hp, hflg)\n\tregister struct Hist *hp;\n\tint hflg;\n{\n\n\tif (hflg == 0)\n\t\tprintf(\"%6d\\t\", hp->Hnum);\n\tprlex(&hp->Hlex);\n}\n"
  },
  {
    "path": "bin/csh/sh.init.c",
    "content": "/*\n * C shell\n *\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"sh.local.h\"\n\nextern\tint doalias();\nextern\tint dobg();\nextern\tint dobreak();\nextern\tint dochngd();\nextern\tint docontin();\nextern\tint dodirs();\nextern\tint doecho();\nextern\tint doelse();\nextern\tint doend();\nextern\tint doendif();\nextern\tint doendsw();\nextern\tint doeval();\nextern\tint doexit();\nextern\tint dofg();\nextern\tint doforeach();\nextern\tint doglob();\nextern\tint dogoto();\nextern  int dohash();\nextern\tint dohist();\nextern\tint doif();\nextern\tint dojobs();\nextern\tint dokill();\nextern\tint dolet();\n#ifndef NOLIMITS\nextern\tint dolimit();\n#endif\nextern\tint dologin();\nextern\tint dologout();\n#ifdef NEWGRP\nextern\tint donewgrp();\n#endif\nextern\tint donice();\nextern\tint donotify();\nextern\tint donohup();\nextern\tint doonintr();\nextern\tint dopopd();\nextern\tint dopushd();\nextern\tint dorepeat();\nextern\tint doset();\nextern\tint dosetenv();\nextern\tint dosource();\nextern\tint dostop();\nextern\tint dosuspend();\nextern\tint doswbrk();\nextern\tint doswitch();\nextern\tint dotime();\n#ifndef NOLIMITS\nextern\tint dounlimit();\n#endif\nextern\tint doumask();\nextern\tint dowait();\nextern\tint dowhile();\nextern\tint dowhich();\nextern\tint dozip();\nextern\tint execash();\nextern\tint goodbye();\n#ifdef VFORK\nextern\tint hashstat();\n#endif\nextern\tint shift();\nextern\tint showall();\nextern\tint unalias();\nextern\tint dounhash();\nextern\tint unset();\nextern\tint dounsetenv();\n\n#define\tINF\t1000\n\nstruct\tbiltins {\n\tchar\t*bname;\n\tint\t(*bfunct)();\n\tshort\tminargs, maxargs;\n} bfunc[] = {\n\t\"@\",\t\tdolet,\t\t0,\tINF,\n\t\"alias\",\tdoalias,\t0,\tINF,\n\t\"alloc\",\tshowall,\t0,\t1,\n\t\"bg\",\t\tdobg,\t\t0,\tINF,\n\t\"break\",\tdobreak,\t0,\t0,\n\t\"breaksw\",\tdoswbrk,\t0,\t0,\n#ifdef IIASA\n\t\"bye\",\t\tgoodbye,\t0,\t0,\n#endif\n\t\"case\",\t\tdozip,\t\t0,\t1,\n\t\"cd\",\t\tdochngd,\t0,\t1,\n\t\"chdir\",\tdochngd,\t0,\t1,\n\t\"continue\",\tdocontin,\t0,\t0,\n\t\"default\",\tdozip,\t\t0,\t0,\n\t\"dirs\",\t\tdodirs,\t\t0,\t1,\n\t\"echo\",\t\tdoecho,\t\t0,\tINF,\n\t\"else\",\t\tdoelse,\t\t0,\tINF,\n\t\"end\",\t\tdoend,\t\t0,\t0,\n\t\"endif\",\tdozip,\t\t0,\t0,\n\t\"endsw\",\tdozip,\t\t0,\t0,\n\t\"eval\",\t\tdoeval,\t\t0,\tINF,\n\t\"exec\",\t\texecash,\t1,\tINF,\n\t\"exit\",\t\tdoexit,\t\t0,\tINF,\n\t\"fg\",\t\tdofg,\t\t0,\tINF,\n\t\"foreach\",\tdoforeach,\t3,\tINF,\n#ifdef IIASA\n\t\"gd\",\t\tdopushd,\t0,\t1,\n#endif\n\t\"glob\",\t\tdoglob,\t\t0,\tINF,\n\t\"goto\",\t\tdogoto,\t\t1,\t1,\n#ifdef VFORK\n\t\"hashstat\",\thashstat,\t0,\t0,\n#endif\n\t\"history\",\tdohist,\t\t0,\t2,\n\t\"if\",\t\tdoif,\t\t1,\tINF,\n\t\"jobs\",\t\tdojobs,\t\t0,\t1,\n\t\"kill\",\t\tdokill,\t\t1,\tINF,\n#ifndef NOLIMITS\n\t\"limit\",\tdolimit,\t0,\t3,\n#endif\n\t\"login\",\tdologin,\t0,\t1,\n\t\"logout\",\tdologout,\t0,\t0,\n#ifdef NEWGRP\n\t\"newgrp\",\tdonewgrp,\t1,\t1,\n#endif\n\t\"nice\",\t\tdonice,\t\t0,\tINF,\n\t\"nohup\",\tdonohup,\t0,\tINF,\n\t\"notify\",\tdonotify,\t0,\tINF,\n\t\"onintr\",\tdoonintr,\t0,\t2,\n\t\"popd\",\t\tdopopd,\t\t0,\t1,\n\t\"pushd\",\tdopushd,\t0,\t1,\n#ifdef IIASA\n\t\"rd\",\t\tdopopd,\t\t0,\t1,\n#endif\n\t\"rehash\",\tdohash,\t\t0,\t0,\n\t\"repeat\",\tdorepeat,\t2,\tINF,\n\t\"set\",\t\tdoset,\t\t0,\tINF,\n\t\"setenv\",\tdosetenv,\t0,\t2,\n\t\"shift\",\tshift,\t\t0,\t1,\n\t\"source\",\tdosource,\t1,\t2,\n\t\"stop\",\t\tdostop,\t\t1,\tINF,\n\t\"suspend\",\tdosuspend,\t0,\t0,\n\t\"switch\",\tdoswitch,\t1,\tINF,\n\t\"time\",\t\tdotime,\t\t0,\tINF,\n\t\"umask\",\tdoumask,\t0,\t1,\n\t\"unalias\",\tunalias,\t1,\tINF,\n\t\"unhash\",\tdounhash,\t0,\t0,\n#ifndef NOLIMITS\n\t\"unlimit\",\tdounlimit,\t0,\tINF,\n#endif\n\t\"unset\",\tunset,\t\t1,\tINF,\n\t\"unsetenv\",\tdounsetenv,\t1,\tINF,\n\t\"wait\",\t\tdowait,\t\t0,\t0,\n\t\"which\",\tdowhich,\t1,\tINF,\n\t\"while\",\tdowhile,\t1,\tINF,\n};\nint nbfunc = sizeof bfunc / sizeof *bfunc;\n\n#define\tZBREAK\t\t0\n#define\tZBRKSW\t\t1\n#define\tZCASE\t\t2\n#define\tZDEFAULT \t3\n#define\tZELSE\t\t4\n#define\tZEND\t\t5\n#define\tZENDIF\t\t6\n#define\tZENDSW\t\t7\n#define\tZEXIT\t\t8\n#define\tZFOREACH\t9\n#define\tZGOTO\t\t10\n#define\tZIF\t\t11\n#define\tZLABEL\t\t12\n#define\tZLET\t\t13\n#define\tZSET\t\t14\n#define\tZSWITCH\t\t15\n#define\tZTEST\t\t16\n#define\tZTHEN\t\t17\n#define\tZWHILE\t\t18\n\nstruct srch {\n\tchar\t*s_name;\n\tshort\ts_value;\n} srchn[] = {\n\t\"@\",\t\tZLET,\n\t\"break\",\tZBREAK,\n\t\"breaksw\",\tZBRKSW,\n\t\"case\",\t\tZCASE,\n\t\"default\", \tZDEFAULT,\n\t\"else\",\t\tZELSE,\n\t\"end\",\t\tZEND,\n\t\"endif\",\tZENDIF,\n\t\"endsw\",\tZENDSW,\n\t\"exit\",\t\tZEXIT,\n\t\"foreach\", \tZFOREACH,\n\t\"goto\",\t\tZGOTO,\n\t\"if\",\t\tZIF,\n\t\"label\",\tZLABEL,\n\t\"set\",\t\tZSET,\n\t\"switch\",\tZSWITCH,\n\t\"while\",\tZWHILE,\n};\nint nsrchn = sizeof srchn / sizeof *srchn;\n\nstruct\tmesg {\n\tchar\t*iname;\n\tchar\t*pname;\n} mesg[] = {\n\t0,\t0,\n\t\"HUP\",\t\"Hangup\",\n\t\"INT\",\t\"Interrupt\",\n\t\"QUIT\",\t\"Quit\",\n\t\"ILL\",\t\"Illegal instruction\",\n\t\"TRAP\",\t\"Trace/BPT trap\",\n\t\"IOT\",\t\"IOT trap\",\n\t\"EMT\",\t\"EMT trap\",\n\t\"FPE\",\t\"Floating exception\",\n\t\"KILL\",\t\"Killed\",\n\t\"BUS\",\t\"Bus error\",\n\t\"SEGV\",\t\"Segmentation fault\",\n\t\"SYS\",\t\"Bad system call\",\n\t\"PIPE\",\t\"Broken pipe\",\n\t\"ALRM\",\t\"Alarm clock\",\n\t\"TERM\",\t\"Terminated\",\n\t\"URG\",\t\"Urgent I/O condition\",\n\t\"STOP\",\t\"Stopped (signal)\",\n\t\"TSTP\",\t\"Stopped\",\n\t\"CONT\",\t\"Continued\",\n\t\"CHLD\",\t\"Child exited\",\n\t\"TTIN\", \"Stopped (tty input)\",\n\t\"TTOU\", \"Stopped (tty output)\",\n\t\"IO\",\t\"I/O possible\",\n\t\"XCPU\",\t\"Cputime limit exceeded\",\n\t\"XFSZ\", \"Filesize limit exceeded\",\n\t\"VTALRM\",\"Virtual timer expired\",\n\t\"PROF\",\t\"Profiling timer expired\",\n\t\"WINCH\",\"Window size changed\",\n\t0,\t\"Signal 29\",\n\t\"USR1\",\t\"User defined signal 1\",\n\t\"USR2\",\t\"User defined signal 2\",\n\t0,\t\"Signal 32\"\n};\n"
  },
  {
    "path": "bin/csh/sh.lex.c",
    "content": "/*\n * C shell\n *\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"sh.h\"\n#include <sgtty.h>\n\n/*\n * These lexical routines read input and form lists of words.\n * There is some involved processing here, because of the complications\n * of input buffering, and especially because of history substitution.\n */\n\nchar\t*word();\n\n/*\n * Peekc is a peek characer for getC, peekread for readc.\n * There is a subtlety here in many places... history routines\n * will read ahead and then insert stuff into the input stream.\n * If they push back a character then they must push it behind\n * the text substituted by the history substitution.  On the other\n * hand in several places we need 2 peek characters.  To make this\n * all work, the history routines read with getC, and make use both\n * of ungetC and unreadc.  The key observation is that the state\n * of getC at the call of a history reference is such that calls\n * to getC from the history routines will always yield calls of\n * readc, unless this peeking is involved.  That is to say that during\n * getexcl the variables lap, exclp, and exclnxt are all zero.\n *\n * Getdol invokes history substitution, hence the extra peek, peekd,\n * which it can ungetD to be before history substitutions.\n */\nchar\tpeekc, peekd;\nchar\tpeekread;\n\nchar\t*exclp;\t\t\t/* (Tail of) current word from ! subst */\nstruct\twordent *exclnxt;\t/* The rest of the ! subst words */\nint\texclc;\t\t\t/* Count of remainig words in ! subst */\nchar\t*alvecp;\t\t/* \"Globp\" for alias resubstitution */\n\n/*\n * Lex returns to its caller not only a wordlist (as a \"var\" parameter)\n * but also whether a history substitution occurred.  This is used in\n * the main (process) routine to determine whether to echo, and also\n * when called by the alias routine to determine whether to keep the\n * argument list.\n */\nbool\thadhist;\n\nchar getCtmp;\n#define getC(f)\t\t((getCtmp = peekc) ? (peekc = 0, getCtmp) : getC1(f))\n#define\tungetC(c)\tpeekc = c\n#define\tungetD(c)\tpeekd = c\n\nlex(hp)\n\tregister struct wordent *hp;\n{\n\tregister struct wordent *wdp;\n\tint c;\n\n\tlineloc = btell();\n\thp->next = hp->prev = hp;\n\thp->word = \"\";\n\talvecp = 0, hadhist = 0;\n\tdo\n\t\tc = readc(0);\n\twhile (c == ' ' || c == '\\t');\n\tif (c == HISTSUB && intty)\n\t\t/* ^lef^rit\tfrom tty is short !:s^lef^rit */\n\t\tgetexcl(c);\n\telse\n\t\tunreadc(c);\n\twdp = hp;\n\t/*\n\t * The following loop is written so that the links needed\n\t * by freelex will be ready and rarin to go even if it is\n\t * interrupted.\n\t */\n\tdo {\n\t\tregister struct wordent *new = (struct wordent *) xalloc(sizeof *wdp);\n\n\t\tnew->word = 0;\n\t\tnew->prev = wdp;\n\t\tnew->next = hp;\n\t\twdp->next = new;\n\t\twdp = new;\n\t\twdp->word = word();\n\t} while (wdp->word[0] != '\\n');\n\thp->prev = wdp;\n\treturn (hadhist);\n}\n\nprlex(sp0)\n\tstruct wordent *sp0;\n{\n\tregister struct wordent *sp = sp0->next;\n\n\tfor (;;) {\n\t\tprintf(\"%s\", sp->word);\n\t\tsp = sp->next;\n\t\tif (sp == sp0)\n\t\t\tbreak;\n\t\tif (sp->word[0] != '\\n')\n\t\t\tputchar(' ');\n\t}\n}\n\ncopylex(hp, fp)\n\tregister struct wordent *hp;\n\tregister struct wordent *fp;\n{\n\tregister struct wordent *wdp;\n\n\twdp = hp;\n\tfp = fp->next;\n\tdo {\n\t\tregister struct wordent *new = (struct wordent *) xalloc(sizeof *wdp);\n\n\t\tnew->prev = wdp;\n\t\tnew->next = hp;\n\t\twdp->next = new;\n\t\twdp = new;\n\t\twdp->word = savestr(fp->word);\n\t\tfp = fp->next;\n\t} while (wdp->word[0] != '\\n');\n\thp->prev = wdp;\n}\n\nfreelex(vp)\n\tregister struct wordent *vp;\n{\n\tregister struct wordent *fp;\n\n\twhile (vp->next != vp) {\n\t\tfp = vp->next;\n\t\tvp->next = fp->next;\n\t\tXFREE(fp->word)\n\t\tXFREE((char *)fp)\n\t}\n\tvp->prev = vp;\n}\n\nchar *\nword()\n{\n\tregister char c, c1;\n\tregister char *wp;\n\tchar wbuf[BUFSIZ];\n\tregister bool dolflg;\n\tregister int i;\n\n\twp = wbuf;\n\ti = BUFSIZ - 4;\nloop:\n\twhile ((c = getC(DOALL)) == ' ' || c == '\\t')\n\t\t;\n\tif (cmap(c, _META|_ESC))\n\t\tswitch (c) {\n\t\tcase '&':\n\t\tcase '|':\n\t\tcase '<':\n\t\tcase '>':\n\t\t\t*wp++ = c;\n\t\t\tc1 = getC(DOALL);\n\t\t\tif (c1 == c)\n\t\t\t\t*wp++ = c1;\n\t\t\telse\n\t\t\t\tungetC(c1);\n\t\t\tgoto ret;\n\n\t\tcase '#':\n\t\t\tif (intty)\n\t\t\t\tbreak;\n\t\t\tc = 0;\n\t\t\tdo {\n\t\t\t\tc1 = c;\n\t\t\t\tc = getC(0);\n\t\t\t} while (c != '\\n');\n\t\t\tif (c1 == '\\\\')\n\t\t\t\tgoto loop;\n\t\t\t/* fall into ... */\n\n\t\tcase ';':\n\t\tcase '(':\n\t\tcase ')':\n\t\tcase '\\n':\n\t\t\t*wp++ = c;\n\t\t\tgoto ret;\n\n\t\tcase '\\\\':\n\t\t\tc = getC(0);\n\t\t\tif (c == '\\n') {\n\t\t\t\tif (onelflg == 1)\n\t\t\t\t\tonelflg = 2;\n\t\t\t\tgoto loop;\n\t\t\t}\n\t\t\tif (c != HIST)\n\t\t\t\t*wp++ = '\\\\', --i;\n\t\t\tc |= QUOTE;\n\t\t}\n\tc1 = 0;\n\tdolflg = DOALL;\n\tfor (;;) {\n\t\tif (c1) {\n\t\t\tif (c == c1) {\n\t\t\t\tc1 = 0;\n\t\t\t\tdolflg = DOALL;\n\t\t\t} else if (c == '\\\\') {\n\t\t\t\tc = getC(0);\n\t\t\t\tif (c == HIST)\n\t\t\t\t\tc |= QUOTE;\n\t\t\t\telse {\n\t\t\t\t\tif (c == '\\n')\n\t\t\t\t\t\t/*\n\t\t\t\t\t\tif (c1 == '`')\n\t\t\t\t\t\t\tc = ' ';\n\t\t\t\t\t\telse\n\t\t\t\t\t\t*/\n\t\t\t\t\t\t\tc |= QUOTE;\n\t\t\t\t\tungetC(c);\n\t\t\t\t\tc = '\\\\';\n\t\t\t\t}\n\t\t\t} else if (c == '\\n') {\n\t\t\t\tseterrc(\"Unmatched \", c1);\n\t\t\t\tungetC(c);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t} else if (cmap(c, _META|_Q|_Q1|_ESC)) {\n\t\t\tif (c == '\\\\') {\n\t\t\t\tc = getC(0);\n\t\t\t\tif (c == '\\n') {\n\t\t\t\t\tif (onelflg == 1)\n\t\t\t\t\t\tonelflg = 2;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tif (c != HIST)\n\t\t\t\t\t*wp++ = '\\\\', --i;\n\t\t\t\tc |= QUOTE;\n\t\t\t} else if (cmap(c, _Q|_Q1)) {\t\t/* '\"` */\n\t\t\t\tc1 = c;\n\t\t\t\tdolflg = c == '\"' ? DOALL : DOEXCL;\n\t\t\t} else if (c != '#' || !intty) {\n\t\t\t\tungetC(c);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (--i > 0) {\n\t\t\t*wp++ = c;\n\t\t\tc = getC(dolflg);\n\t\t} else {\n\t\t\tseterr(\"Word too long\");\n\t\t\twp = &wbuf[1];\n\t\t\tbreak;\n\t\t}\n\t}\nret:\n\t*wp = 0;\n\treturn (savestr(wbuf));\n}\n\ngetC1(flag)\n\tregister int flag;\n{\n\tregister char c;\n\ntop:\n\tif (c = peekc) {\n\t\tpeekc = 0;\n\t\treturn (c);\n\t}\n\tif (lap) {\n\t\tif ((c = *lap++) == 0)\n\t\t\tlap = 0;\n\t\telse {\n\t\t\tif (cmap(c, _META|_Q|_Q1))\n\t\t\t\tc |= QUOTE;\n\t\t\treturn (c);\n\t\t}\n\t}\n\tif (c = peekd) {\n\t\tpeekd = 0;\n\t\treturn (c);\n\t}\n\tif (exclp) {\n\t\tif (c = *exclp++)\n\t\t\treturn (c);\n\t\tif (exclnxt && --exclc >= 0) {\n\t\t\texclnxt = exclnxt->next;\n\t\t\tsetexclp(exclnxt->word);\n\t\t\treturn (' ');\n\t\t}\n\t\texclp = 0;\n\t\texclnxt = 0;\n\t}\n\tif (exclnxt) {\n\t\texclnxt = exclnxt->next;\n\t\tif (--exclc < 0)\n\t\t\texclnxt = 0;\n\t\telse\n\t\t\tsetexclp(exclnxt->word);\n\t\tgoto top;\n\t}\n\tc = readc(0);\n\tif (c == '$' && (flag & DODOL)) {\n\t\tgetdol();\n\t\tgoto top;\n\t}\n\tif (c == HIST && (flag & DOEXCL)) {\n\t\tgetexcl(0);\n\t\tgoto top;\n\t}\n\treturn (c);\n}\n\ngetdol()\n{\n\tregister char *np;\n\tchar name[40];\n\tregister int c;\n\tint sc;\n\tbool special = 0;\n\n\tnp = name, *np++ = '$';\n\tc = sc = getC(DOEXCL);\n\tif (any(c, \"\\t \\n\")) {\n\t\tungetD(c);\n\t\tungetC('$' | QUOTE);\n\t\treturn;\n\t}\n\tif (c == '{')\n\t\t*np++ = c, c = getC(DOEXCL);\n\tif (c == '#' || c == '?')\n\t\tspecial++, *np++ = c, c = getC(DOEXCL);\n\t*np++ = c;\n\tswitch (c) {\n\n\tcase '<':\n\tcase '$':\n\t\tif (special)\n\t\t\tgoto vsyn;\n\t\tgoto ret;\n\n\tcase '\\n':\n\t\tungetD(c);\n\t\tnp--;\n\t\tgoto vsyn;\n\n\tcase '*':\n\t\tif (special)\n\t\t\tgoto vsyn;\n\t\tgoto ret;\n\n\tdefault:\n\t\tif (digit(c)) {\n/*\n * let $?0 pass for now\n\t\t\tif (special)\n\t\t\t\tgoto vsyn;\n*/\n\t\t\twhile (digit(c = getC(DOEXCL))) {\n\t\t\t\tif (np < &name[sizeof name / 2])\n\t\t\t\t\t*np++ = c;\n\t\t\t}\n\t\t} else if (letter(c))\n\t\t\twhile (letter(c = getC(DOEXCL))) {\n\t\t\t\tif (np < &name[sizeof name / 2])\n\t\t\t\t\t*np++ = c;\n\t\t\t}\n\t\telse\n\t\t\tgoto vsyn;\n\t}\n\tif (c == '[') {\n\t\t*np++ = c;\n\t\tdo {\n\t\t\tc = getC(DOEXCL);\n\t\t\tif (c == '\\n') {\n\t\t\t\tungetD(c);\n\t\t\t\tnp--;\n\t\t\t\tgoto vsyn;\n\t\t\t}\n\t\t\tif (np >= &name[sizeof name - 8])\n\t\t\t\tgoto vsyn;\n\t\t\t*np++ = c;\n\t\t} while (c != ']');\n\t\tc = getC(DOEXCL);\n\t}\n\tif (c == ':') {\n\t\t*np++ = c, c = getC(DOEXCL);\n\t\tif (c == 'g')\n\t\t\t*np++ = c, c = getC(DOEXCL);\n\t\t*np++ = c;\n\t\tif (!any(c, \"htrqxe\"))\n\t\t\tgoto vsyn;\n\t} else\n\t\tungetD(c);\n\tif (sc == '{') {\n\t\tc = getC(DOEXCL);\n\t\tif (c != '}') {\n\t\t\tungetC(c);\n\t\t\tgoto vsyn;\n\t\t}\n\t\t*np++ = c;\n\t}\nret:\n\t*np = 0;\n\taddla(name);\n\treturn;\n\nvsyn:\n\tseterr(\"Variable syntax\");\n\tgoto ret;\n}\n\naddla(cp)\n\tchar *cp;\n{\n\tchar buf[BUFSIZ];\n\n\tif (lap != 0 && strlen(cp) + strlen(lap) >= sizeof (labuf) - 4) {\n\t\tseterr(\"Expansion buf ovflo\");\n\t\treturn;\n\t}\n\tif (lap)\n\t\t(void) strcpy(buf, lap);\n\t(void) strcpy(labuf, cp);\n\tif (lap)\n\t\t(void) strcat(labuf, buf);\n\tlap = labuf;\n}\n\nchar\tlhsb[32];\nchar\tslhs[32];\nchar\trhsb[64];\nint\tquesarg;\n\ngetexcl(sc)\n\tchar sc;\n{\n\tregister struct wordent *hp, *ip;\n\tint left, right, dol;\n\tregister int c;\n\n\tif (sc == 0) {\n\t\tsc = getC(0);\n\t\tif (sc != '{') {\n\t\t\tungetC(sc);\n\t\t\tsc = 0;\n\t\t}\n\t}\n\tquesarg = -1;\n\tlastev = eventno;\n\thp = gethent(sc);\n\tif (hp == 0)\n\t\treturn;\n\thadhist = 1;\n\tdol = 0;\n\tif (hp == alhistp)\n\t\tfor (ip = hp->next->next; ip != alhistt; ip = ip->next)\n\t\t\tdol++;\n\telse\n\t\tfor (ip = hp->next->next; ip != hp->prev; ip = ip->next)\n\t\t\tdol++;\n\tleft = 0, right = dol;\n\tif (sc == HISTSUB) {\n\t\tungetC('s'), unreadc(HISTSUB), c = ':';\n\t\tgoto subst;\n\t}\n\tc = getC(0);\n\tif (!any(c, \":^$*-%\"))\n\t\tgoto subst;\n\tleft = right = -1;\n\tif (c == ':') {\n\t\tc = getC(0);\n\t\tunreadc(c);\n\t\tif (letter(c) || c == '&') {\n\t\t\tc = ':';\n\t\t\tleft = 0, right = dol;\n\t\t\tgoto subst;\n\t\t}\n\t} else\n\t\tungetC(c);\n\tif (!getsel(&left, &right, dol))\n\t\treturn;\n\tc = getC(0);\n\tif (c == '*')\n\t\tungetC(c), c = '-';\n\tif (c == '-') {\n\t\tif (!getsel(&left, &right, dol))\n\t\t\treturn;\n\t\tc = getC(0);\n\t}\nsubst:\n\texclc = right - left + 1;\n\twhile (--left >= 0)\n\t\thp = hp->next;\n\tif (sc == HISTSUB || c == ':') {\n\t\tdo {\n\t\t\thp = getsub(hp);\n\t\t\tc = getC(0);\n\t\t} while (c == ':');\n\t}\n\tunreadc(c);\n\tif (sc == '{') {\n\t\tc = getC(0);\n\t\tif (c != '}')\n\t\t\tseterr(\"Bad ! form\");\n\t}\n\texclnxt = hp;\n}\n\nstruct wordent *\ngetsub(en)\n\tstruct wordent *en;\n{\n\tregister char *cp;\n\tint delim;\n\tregister int c;\n\tint sc;\n\tbool global = 0;\n\tchar orhsb[sizeof rhsb];\n\n\texclnxt = 0;\n\tsc = c = getC(0);\n\tif (c == 'g')\n\t\tglobal++, c = getC(0);\n\tswitch (c) {\n\n\tcase 'p':\n\t\tjustpr++;\n\t\tgoto ret;\n\n\tcase 'x':\n\tcase 'q':\n\t\tglobal++;\n\t\t/* fall into ... */\n\n\tcase 'h':\n\tcase 'r':\n\tcase 't':\n\tcase 'e':\n\t\tbreak;\n\n\tcase '&':\n\t\tif (slhs[0] == 0) {\n\t\t\tseterr(\"No prev sub\");\n\t\t\tgoto ret;\n\t\t}\n\t\t(void) strcpy(lhsb, slhs);\n\t\tbreak;\n\n/*\n\tcase '~':\n\t\tif (lhsb[0] == 0)\n\t\t\tgoto badlhs;\n\t\tbreak;\n*/\n\n\tcase 's':\n\t\tdelim = getC(0);\n\t\tif (letter(delim) || digit(delim) || any(delim, \" \\t\\n\")) {\n\t\t\tunreadc(delim);\nbads:\n\t\t\tlhsb[0] = 0;\n\t\t\tseterr(\"Bad substitute\");\n\t\t\tgoto ret;\n\t\t}\n\t\tcp = lhsb;\n\t\tfor (;;) {\n\t\t\tc = getC(0);\n\t\t\tif (c == '\\n') {\n\t\t\t\tunreadc(c);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (c == delim)\n\t\t\t\tbreak;\n\t\t\tif (cp > &lhsb[sizeof lhsb - 2])\n\t\t\t\tgoto bads;\n\t\t\tif (c == '\\\\') {\n\t\t\t\tc = getC(0);\n\t\t\t\tif (c != delim && c != '\\\\')\n\t\t\t\t\t*cp++ = '\\\\';\n\t\t\t}\n\t\t\t*cp++ = c;\n\t\t}\n\t\tif (cp != lhsb)\n\t\t\t*cp++ = 0;\n\t\telse if (lhsb[0] == 0) {\n/*badlhs:*/\n\t\t\tseterr(\"No prev lhs\");\n\t\t\tgoto ret;\n\t\t}\n\t\tcp = rhsb;\n\t\t(void) strcpy(orhsb, cp);\n\t\tfor (;;) {\n\t\t\tc = getC(0);\n\t\t\tif (c == '\\n') {\n\t\t\t\tunreadc(c);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (c == delim)\n\t\t\t\tbreak;\n/*\n\t\t\tif (c == '~') {\n\t\t\t\tif (&cp[strlen(orhsb)] > &rhsb[sizeof rhsb - 2])\n\t\t\t\t\tgoto toorhs;\n\t\t\t\t(void) strcpy(cp, orhsb);\n\t\t\t\tcp = strend(cp);\n\t\t\t\tcontinue;\n\t\t\t}\n*/\n\t\t\tif (cp > &rhsb[sizeof rhsb - 2]) {\n/*toorhs:*/\n\t\t\t\tseterr(\"Rhs too long\");\n\t\t\t\tgoto ret;\n\t\t\t}\n\t\t\tif (c == '\\\\') {\n\t\t\t\tc = getC(0);\n\t\t\t\tif (c != delim /* && c != '~' */)\n\t\t\t\t\t*cp++ = '\\\\';\n\t\t\t}\n\t\t\t*cp++ = c;\n\t\t}\n\t\t*cp++ = 0;\n\t\tbreak;\n\n\tdefault:\n\t\tif (c == '\\n')\n\t\t\tunreadc(c);\n\t\tseterrc(\"Bad ! modifier: \", c);\n\t\tgoto ret;\n\t}\n\t(void) strcpy(slhs, lhsb);\n\tif (exclc)\n\t\ten = dosub(sc, en, global);\nret:\n\treturn (en);\n}\n\nstruct wordent *\ndosub(sc, en, global)\n\tint sc;\n\tstruct wordent *en;\n\tbool global;\n{\n\tstruct wordent lex;\n\tbool didsub = 0;\n\tstruct wordent *hp = &lex;\n\tregister struct wordent *wdp;\n\tregister int i = exclc;\n\n\twdp = hp;\n\twhile (--i >= 0) {\n\t\tregister struct wordent *new = (struct wordent *) calloc(1, sizeof *wdp);\n\n\t\tnew->prev = wdp;\n\t\tnew->next = hp;\n\t\twdp->next = new;\n\t\twdp = new;\n\t\ten = en->next;\n\t\twdp->word = global || didsub == 0 ?\n\t\t    subword(en->word, sc, &didsub) : savestr(en->word);\n\t}\n\tif (didsub == 0)\n\t\tseterr(\"Modifier failed\");\n\thp->prev = wdp;\n\treturn (&enthist(-1000, &lex, 0)->Hlex);\n}\n\nchar *\nsubword(cp, type, adid)\n\tchar *cp;\n\tint type;\n\tbool *adid;\n{\n\tchar wbuf[BUFSIZ];\n\tregister char *wp, *mp, *np;\n\tregister int i;\n\n\tswitch (type) {\n\n\tcase 'r':\n\tcase 'e':\n\tcase 'h':\n\tcase 't':\n\tcase 'q':\n\tcase 'x':\n\t\twp = domod(cp, type);\n\t\tif (wp == 0)\n\t\t\treturn (savestr(cp));\n\t\t*adid = 1;\n\t\treturn (wp);\n\n\tdefault:\n\t\twp = wbuf;\n\t\ti = BUFSIZ - 4;\n\t\tfor (mp = cp; *mp; mp++)\n\t\t\tif (matchs(mp, lhsb)) {\n\t\t\t\tfor (np = cp; np < mp;)\n\t\t\t\t\t*wp++ = *np++, --i;\n\t\t\t\tfor (np = rhsb; *np; np++) switch (*np) {\n\n\t\t\t\tcase '\\\\':\n\t\t\t\t\tif (np[1] == '&')\n\t\t\t\t\t\tnp++;\n\t\t\t\t\t/* fall into ... */\n\n\t\t\t\tdefault:\n\t\t\t\t\tif (--i < 0)\n\t\t\t\t\t\tgoto ovflo;\n\t\t\t\t\t*wp++ = *np;\n\t\t\t\t\tcontinue;\n\n\t\t\t\tcase '&':\n\t\t\t\t\ti -= strlen(lhsb);\n\t\t\t\t\tif (i < 0)\n\t\t\t\t\t\tgoto ovflo;\n\t\t\t\t\t*wp = 0;\n\t\t\t\t\t(void) strcat(wp, lhsb);\n\t\t\t\t\twp = strend(wp);\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t\tmp += strlen(lhsb);\n\t\t\t\ti -= strlen(mp);\n\t\t\t\tif (i < 0) {\novflo:\n\t\t\t\t\tseterr(\"Subst buf ovflo\");\n\t\t\t\t\treturn (\"\");\n\t\t\t\t}\n\t\t\t\t*wp = 0;\n\t\t\t\t(void) strcat(wp, mp);\n\t\t\t\t*adid = 1;\n\t\t\t\treturn (savestr(wbuf));\n\t\t\t}\n\t\treturn (savestr(cp));\n\t}\n}\n\nchar *\ndomod(cp, type)\n\tchar *cp;\n\tint type;\n{\n\tregister char *wp, *xp;\n\tregister int c;\n\n\tswitch (type) {\n\n\tcase 'x':\n\tcase 'q':\n\t\twp = savestr(cp);\n\t\tfor (xp = wp; c = *xp; xp++)\n\t\t\tif ((c != ' ' && c != '\\t') || type == 'q')\n\t\t\t\t*xp |= QUOTE;\n\t\treturn (wp);\n\n\tcase 'h':\n\tcase 't':\n\t\tif (!any('/', cp))\n\t\t\treturn (type == 't' ? savestr(cp) : 0);\n\t\twp = strend(cp);\n\t\twhile (*--wp != '/')\n\t\t\tcontinue;\n\t\tif (type == 'h')\n\t\t\txp = savestr(cp), xp[wp - cp] = 0;\n\t\telse\n\t\t\txp = savestr(wp + 1);\n\t\treturn (xp);\n\n\tcase 'e':\n\tcase 'r':\n\t\twp = strend(cp);\n\t\tfor (wp--; wp >= cp && *wp != '/'; wp--)\n\t\t\tif (*wp == '.') {\n\t\t\t\tif (type == 'e')\n\t\t\t\t\txp = savestr(wp + 1);\n\t\t\t\telse\n\t\t\t\t\txp = savestr(cp), xp[wp - cp] = 0;\n\t\t\t\treturn (xp);\n\t\t\t}\n\t\treturn (savestr(type == 'e' ? \"\" : cp));\n\t}\n\treturn (0);\n}\n\nmatchs(str, pat)\n\tregister char *str, *pat;\n{\n\n\twhile (*str && *pat && *str == *pat)\n\t\tstr++, pat++;\n\treturn (*pat == 0);\n}\n\ngetsel(al, ar, dol)\n\tregister int *al, *ar;\n\tint dol;\n{\n\tregister int c = getC(0);\n\tregister int i;\n\tbool first = *al < 0;\n\n\tswitch (c) {\n\n\tcase '%':\n\t\tif (quesarg == -1)\n\t\t\tgoto bad;\n\t\tif (*al < 0)\n\t\t\t*al = quesarg;\n\t\t*ar = quesarg;\n\t\tbreak;\n\n\tcase '-':\n\t\tif (*al < 0) {\n\t\t\t*al = 0;\n\t\t\t*ar = dol - 1;\n\t\t\tunreadc(c);\n\t\t}\n\t\treturn (1);\n\n\tcase '^':\n\t\tif (*al < 0)\n\t\t\t*al = 1;\n\t\t*ar = 1;\n\t\tbreak;\n\n\tcase '$':\n\t\tif (*al < 0)\n\t\t\t*al = dol;\n\t\t*ar = dol;\n\t\tbreak;\n\n\tcase '*':\n\t\tif (*al < 0)\n\t\t\t*al = 1;\n\t\t*ar = dol;\n\t\tif (*ar < *al) {\n\t\t\t*ar = 0;\n\t\t\t*al = 1;\n\t\t\treturn (1);\n\t\t}\n\t\tbreak;\n\n\tdefault:\n\t\tif (digit(c)) {\n\t\t\ti = 0;\n\t\t\twhile (digit(c)) {\n\t\t\t\ti = i * 10 + c - '0';\n\t\t\t\tc = getC(0);\n\t\t\t}\n\t\t\tif (i < 0)\n\t\t\t\ti = dol + 1;\n\t\t\tif (*al < 0)\n\t\t\t\t*al = i;\n\t\t\t*ar = i;\n\t\t} else\n\t\t\tif (*al < 0)\n\t\t\t\t*al = 0, *ar = dol;\n\t\t\telse\n\t\t\t\t*ar = dol - 1;\n\t\tunreadc(c);\n\t\tbreak;\n\t}\n\tif (first) {\n\t\tc = getC(0);\n\t\tunreadc(c);\n\t\tif (any(c, \"-$*\"))\n\t\t\treturn (1);\n\t}\n\tif (*al > *ar || *ar > dol) {\nbad:\n\t\tseterr(\"Bad ! arg selector\");\n\t\treturn (0);\n\t}\n\treturn (1);\n\n}\n\nstruct wordent *\ngethent(sc)\n\tint sc;\n{\n\tregister struct Hist *hp;\n\tregister char *np;\n\tregister int c;\n\tint event;\n\tbool back = 0;\n\n\tc = sc == HISTSUB ? HIST : getC(0);\n\tif (c == HIST) {\n\t\tif (alhistp)\n\t\t\treturn (alhistp);\n\t\tevent = eventno;\n\t\tgoto skip;\n\t}\n\tswitch (c) {\n\n\tcase ':':\n\tcase '^':\n\tcase '$':\n\tcase '*':\n\tcase '%':\n\t\tungetC(c);\n\t\tif (lastev == eventno && alhistp)\n\t\t\treturn (alhistp);\n\t\tevent = lastev;\n\t\tbreak;\n\n\tcase '-':\n\t\tback = 1;\n\t\tc = getC(0);\n\t\tgoto number;\n\n\tcase '#':\t\t\t/* !# is command being typed in (mrh) */\n\t\treturn(&paraml);\n\n\tdefault:\n\t\tif (any(c, \"(=~\")) {\n\t\t\tunreadc(c);\n\t\t\tungetC(HIST);\n\t\t\treturn (0);\n\t\t}\n\t\tif (digit(c))\n\t\t\tgoto number;\n\t\tnp = lhsb;\n\t\twhile (!any(c, \": \\t\\\\\\n}\")) {\n\t\t\tif (np < &lhsb[sizeof lhsb - 2])\n\t\t\t\t*np++ = c;\n\t\t\tc = getC(0);\n\t\t}\n\t\tunreadc(c);\n\t\tif (np == lhsb) {\n\t\t\tungetC(HIST);\n\t\t\treturn (0);\n\t\t}\n\t\t*np++ = 0;\n\t\thp = findev(lhsb, 0);\n\t\tif (hp)\n\t\t\tlastev = hp->Hnum;\n\t\treturn (&hp->Hlex);\n\n\tcase '?':\n\t\tnp = lhsb;\n\t\tfor (;;) {\n\t\t\tc = getC(0);\n\t\t\tif (c == '\\n') {\n\t\t\t\tunreadc(c);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (c == '?')\n\t\t\t\tbreak;\n\t\t\tif (np < &lhsb[sizeof lhsb - 2])\n\t\t\t\t*np++ = c;\n\t\t}\n\t\tif (np == lhsb) {\n\t\t\tif (lhsb[0] == 0) {\n\t\t\t\tseterr(\"No prev search\");\n\t\t\t\treturn (0);\n\t\t\t}\n\t\t} else\n\t\t\t*np++ = 0;\n\t\thp = findev(lhsb, 1);\n\t\tif (hp)\n\t\t\tlastev = hp->Hnum;\n\t\treturn (&hp->Hlex);\n\n\tnumber:\n\t\tevent = 0;\n\t\twhile (digit(c)) {\n\t\t\tevent = event * 10 + c - '0';\n\t\t\tc = getC(0);\n\t\t}\n\t\tif (back)\n\t\t\tevent = eventno + (alhistp == 0) - (event ? event : 0);\n\t\tunreadc(c);\n\t\tbreak;\n\t}\nskip:\n\tfor (hp = Histlist.Hnext; hp; hp = hp->Hnext)\n\t\tif (hp->Hnum == event) {\n\t\t\thp->Href = eventno;\n\t\t\tlastev = hp->Hnum;\n\t\t\treturn (&hp->Hlex);\n\t\t}\n\tnp = putn(event);\n\tnoev(np);\n\treturn (0);\n}\n\nstruct Hist *\nfindev(cp, anyarg)\n\tchar *cp;\n\tbool anyarg;\n{\n\tregister struct Hist *hp;\n\n\tfor (hp = Histlist.Hnext; hp; hp = hp->Hnext) {\n\t\tchar *dp;\n\t\tregister char *p, *q;\n\t\tregister struct wordent *lp = hp->Hlex.next;\n\t\tint argno = 0;\n\n\t\tif (lp->word[0] == '\\n')\n\t\t\tcontinue;\n\t\tif (!anyarg) {\n\t\t\tp = cp;\n\t\t\tq = lp->word;\n\t\t\tdo\n\t\t\t\tif (!*p)\n\t\t\t\t\treturn (hp);\n\t\t\twhile (*p++ == *q++);\n\t\t\tcontinue;\n\t\t}\n\t\tdo {\n\t\t\tfor (dp = lp->word; *dp; dp++) {\n\t\t\t\tp = cp;\n\t\t\t\tq = dp;\n\t\t\t\tdo\n\t\t\t\t\tif (!*p) {\n\t\t\t\t\t\tquesarg = argno;\n\t\t\t\t\t\treturn (hp);\n\t\t\t\t\t}\n\t\t\t\twhile (*p++ == *q++);\n\t\t\t}\n\t\t\tlp = lp->next;\n\t\t\targno++;\n\t\t} while (lp->word[0] != '\\n');\n\t}\n\tnoev(cp);\n\treturn (0);\n}\n\nnoev(cp)\n\tchar *cp;\n{\n\n\tseterr2(cp, \": Event not found\");\n}\n\nsetexclp(cp)\n\tregister char *cp;\n{\n\n\tif (cp && cp[0] == '\\n')\n\t\treturn;\n\texclp = cp;\n}\n\nunreadc(c)\n\tchar c;\n{\n\n\tpeekread = c;\n}\n\nreadc(wanteof)\n\tbool wanteof;\n{\n\tregister int c;\n\tstatic sincereal;\n\n\tif (c = peekread) {\n\t\tpeekread = 0;\n\t\treturn (c);\n\t}\ntop:\n\tif (alvecp) {\n\t\tif (c = *alvecp++)\n\t\t\treturn (c);\n\t\tif (*alvec) {\n\t\t\talvecp = *alvec++;\n\t\t\treturn (' ');\n\t\t}\n\t}\n\tif (alvec) {\n\t\tif (alvecp = *alvec) {\n\t\t\talvec++;\n\t\t\tgoto top;\n\t\t}\n\t\t/* Infinite source! */\n\t\treturn ('\\n');\n\t}\n\tif (evalp) {\n\t\tif (c = *evalp++)\n\t\t\treturn (c);\n\t\tif (*evalvec) {\n\t\t\tevalp = *evalvec++;\n\t\t\treturn (' ');\n\t\t}\n\t\tevalp = 0;\n\t}\n\tif (evalvec) {\n\t\tif (evalvec == (char **)1) {\n\t\t\tdoneinp = 1;\n\t\t\treset();\n\t\t}\n\t\tif (evalp = *evalvec) {\n\t\t\tevalvec++;\n\t\t\tgoto top;\n\t\t}\n\t\tevalvec = (char **)1;\n\t\treturn ('\\n');\n\t}\n\tdo {\n\t\tif (arginp == (char *) 1 || onelflg == 1) {\n\t\t\tif (wanteof)\n\t\t\t\treturn (-1);\n\t\t\texitstat();\n\t\t}\n\t\tif (arginp) {\n\t\t\tif ((c = *arginp++) == 0) {\n\t\t\t\targinp = (char *) 1;\n\t\t\t\treturn ('\\n');\n\t\t\t}\n\t\t\treturn (c);\n\t\t}\nreread:\n\t\tc = bgetc();\n\t\tif (c < 0) {\n\t\t\tstruct sgttyb tty;\n\n\t\t\tif (wanteof)\n\t\t\t\treturn (-1);\n\t\t\t/* was isatty but raw with ignoreeof yields problems */\n\t\t\tif (ioctl(SHIN, TIOCGETP, (char *)&tty) == 0 &&\n\t\t\t    (tty.sg_flags & RAW) == 0) {\n\t\t\t\t/* was 'short' for FILEC */\n\t\t\t\tint ctpgrp;\n\n\t\t\t\tif (++sincereal > 25)\n\t\t\t\t\tgoto oops;\n\t\t\t\tif (tpgrp != -1 &&\n\t\t\t\t    ioctl(FSHTTY, TIOCGPGRP, (char *)&ctpgrp) == 0 &&\n\t\t\t\t    tpgrp != ctpgrp) {\n\t\t\t\t\t(void) ioctl(FSHTTY, TIOCSPGRP,\n\t\t\t\t\t\t(char *)&tpgrp);\n\t\t\t\t\t(void) killpg(ctpgrp, SIGHUP);\nprintf(\"Reset tty pgrp from %d to %d\\n\", ctpgrp, tpgrp);\n\t\t\t\t\tgoto reread;\n\t\t\t\t}\n\t\t\t\tif (adrof(\"ignoreeof\")) {\n\t\t\t\t\tif (loginsh)\n\t\t\t\t\t\tprintf(\"\\nUse \\\"logout\\\" to logout.\\n\");\n\t\t\t\t\telse\n\t\t\t\t\t\tprintf(\"\\nUse \\\"exit\\\" to leave csh.\\n\");\n\t\t\t\t\treset();\n\t\t\t\t}\n\t\t\t\tif (chkstop == 0)\n\t\t\t\t\tpanystop(1);\n\t\t\t}\noops:\n\t\t\tdoneinp = 1;\n\t\t\treset();\n\t\t}\n\t\tsincereal = 0;\n\t\tif (c == '\\n' && onelflg)\n\t\t\tonelflg--;\n\t} while (c == 0);\n\treturn (c);\n}\n\nbgetc()\n{\n\tregister int buf, off, c;\n#ifdef FILEC\n\tchar ttyline[BUFSIZ];\n\tregister int numleft = 0, roomleft;\n#endif\n\n#ifdef TELL\n\tif (cantell) {\n\t\tif (fseekp < fbobp || fseekp > feobp) {\n\t\t\tfbobp = feobp = fseekp;\n\t\t\t(void) lseek(SHIN, fseekp, 0);\n\t\t}\n\t\tif (fseekp == feobp) {\n\t\t\tfbobp = feobp;\n\t\t\tdo\n\t\t\t\tc = read(SHIN, fbuf[0], BUFSIZ);\n\t\t\twhile (c < 0 && errno == EINTR);\n\t\t\tif (c <= 0)\n\t\t\t\treturn (-1);\n\t\t\tfeobp += c;\n\t\t}\n\t\tc = fbuf[0][fseekp - fbobp];\n\t\tfseekp++;\n\t\treturn (c & 0377);\n\t}\n#endif\nagain:\n\tbuf = (int) fseekp / BUFSIZ;\n\tif (buf >= fblocks) {\n\t\tregister char **nfbuf =\n\t\t\t(char **) calloc((unsigned) (fblocks + 2),\n\t\t\t\tsizeof (char **));\n\n\t\tif (fbuf) {\n\t\t\t(void) blkcpy(nfbuf, fbuf);\n\t\t\txfree((char *)fbuf);\n\t\t}\n\t\tfbuf = nfbuf;\n\t\tfbuf[fblocks] = calloc(BUFSIZ, sizeof (char));\n\t\tfblocks++;\n\t\tgoto again;\n\t}\n\tif (fseekp >= feobp) {\n\t\tbuf = (int) feobp / BUFSIZ;\n\t\toff = (int) feobp % BUFSIZ;\n#ifndef FILEC\n\t\tfor (;;) {\n\t\t\tc = read(SHIN, fbuf[buf] + off, BUFSIZ - off);\n#else\n\t\troomleft = BUFSIZ - off;\n\t\tfor (;;) {\n\t\t\tif (filec && intty) {\n\t\t\t\tc = numleft ? numleft : tenex(ttyline, BUFSIZ);\n\t\t\t\tif (c > roomleft) {\n\t\t\t\t\t/* start with fresh buffer */\n\t\t\t\t\tfeobp = fseekp = fblocks * BUFSIZ;\n\t\t\t\t\tnumleft = c;\n\t\t\t\t\tgoto again;\n\t\t\t\t}\n\t\t\t\tif (c > 0)\n\t\t\t\t\tmemcpy(fbuf[buf] + off, ttyline, c);\n\t\t\t\tnumleft = 0;\n\t\t\t} else\n\t\t\t\tc = read(SHIN, fbuf[buf] + off, roomleft);\n#endif\n\t\t\tif (c >= 0)\n\t\t\t\tbreak;\n\t\t\tif (errno == EWOULDBLOCK) {\n\t\t\t\tint off = 0;\n\n\t\t\t\t(void) ioctl(SHIN, FIONBIO, (char *)&off);\n\t\t\t} else if (errno != EINTR)\n\t\t\t\tbreak;\n\t\t}\n\t\tif (c <= 0)\n\t\t\treturn (-1);\n\t\tfeobp += c;\n#ifndef FILEC\n\t\tgoto again;\n#else\n\t\tif (filec && !intty)\n\t\t\tgoto again;\n#endif\n\t}\n\tc = fbuf[buf][(int) fseekp % BUFSIZ];\n\tfseekp++;\n\treturn (c & 0377);\n}\n\nbfree()\n{\n\tregister int sb, i;\n\n#ifdef TELL\n\tif (cantell)\n\t\treturn;\n#endif\n\tif (whyles)\n\t\treturn;\n\tsb = (int) (fseekp - 1) / BUFSIZ;\n\tif (sb > 0) {\n\t\tfor (i = 0; i < sb; i++)\n\t\t\txfree(fbuf[i]);\n\t\t(void) blkcpy(fbuf, &fbuf[sb]);\n\t\tfseekp -= BUFSIZ * sb;\n\t\tfeobp -= BUFSIZ * sb;\n\t\tfblocks -= sb;\n\t}\n}\n\nbseek(l)\n\toff_t l;\n{\n\tregister struct whyle *wp;\n\n\tfseekp = l;\n#ifdef TELL\n\tif (!cantell) {\n#endif\n\t\tif (!whyles)\n\t\t\treturn;\n\t\tfor (wp = whyles; wp->w_next; wp = wp->w_next)\n\t\t\tcontinue;\n\t\tif (wp->w_start > l)\n\t\t\tl = wp->w_start;\n#ifdef TELL\n\t}\n#endif\n}\n\n/* any similarity to bell telephone is purely accidental */\n#ifndef btell\noff_t\nbtell()\n{\n\n\treturn (fseekp);\n}\n#endif\n\nbtoeof()\n{\n\n\t(void) lseek(SHIN, (off_t)0, 2);\n\tfseekp = feobp;\n\twfree();\n\tbfree();\n}\n\n#ifdef TELL\nsettell()\n{\n\n\tcantell = 0;\n\tif (arginp || onelflg || intty)\n\t\treturn;\n\tif (lseek(SHIN, (off_t)0, 1) < 0 || errno == ESPIPE)\n\t\treturn;\n\tfbuf = (char **) calloc(2, sizeof (char **));\n\tfblocks = 1;\n\tfbuf[0] = calloc(BUFSIZ, sizeof (char));\n\tfseekp = fbobp = feobp = lseek(SHIN, (off_t)0, 1);\n\tcantell = 1;\n}\n#endif\n"
  },
  {
    "path": "bin/csh/sh.local.h",
    "content": "/*\n * This file defines certain local parameters\n * A symbol should be defined in Makefile for local conditional\n * compilation, e.g. IIASA or ERNIE, to be tested here and elsewhere.\n *\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * Fundamental definitions which may vary from system to system.\n *\n *\tBUFSIZ\t\tThe i/o buffering size; also limits word size\n *\tSHELLPATH\tWhere the shell will live; initalizes $shell\n *\tMAILINTVL\tHow often to mailcheck; more often is more expensive\n *\tOTHERSH\t\tShell for scripts which don't start with #\n */\n#define\tBUFSIZ          1024\t/* default buffer size */\n#define\tSHELLPATH\t\"/bin/csh\"\n#define\tOTHERSH\t\t\"/bin/sh\"\n#define FORKSLEEP\t10\t/* delay loop on non-interactive fork failure */\n#define\tMAILINTVL\t600\t/* 10 minutes */\n\n/*\n * The shell moves std in/out/diag and the old std input away from units\n * 0, 1, and 2 so that it is easy to set up these standards for invoked\n * commands.\n */\n#define\tFSHTTY\t15\t\t/* /dev/tty when manip pgrps */\n#define\tFSHIN\t16\t\t/* Preferred desc for shell input */\n#define\tFSHOUT\t17\t\t/* ... shell output */\n#define\tFSHDIAG\t18\t\t/* ... shell diagnostics */\n#define\tFOLDSTD\t19\t\t/* ... old std input */\n\n#ifdef PROF\n#define\texit(n)\tdone(n)\n#endif\n"
  },
  {
    "path": "bin/csh/sh.misc.c",
    "content": "/*\n * C Shell\n *\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"sh.h\"\n\nany(c, s)\n\tregister int c;\n\tregister char *s;\n{\n\n\twhile (*s)\n\t\tif (*s++ == c)\n\t\t\treturn(1);\n\treturn(0);\n}\n\nonlyread(cp)\n\tchar *cp;\n{\n\textern char end[];\n\n\treturn (cp < end);\n}\n\nxfree(cp)\n\tchar *cp;\n{\n\textern char end[];\n\n\tif (cp >= end && cp < (char *) &cp)\n\t\tfree(cp);\n}\n\nchar *\nsavestr(s)\n\tregister char *s;\n{\n\tchar *n;\n\tregister char *p;\n\n\tif (s == 0)\n\t\ts = \"\";\n\tfor (p = s; *p++;)\n\t\t;\n\tn = p = xalloc((unsigned) (p - s));\n\twhile (*p++ = *s++)\n\t\t;\n\treturn (n);\n}\n\n#if 0\nchar *\ncalloc(i, j)\n\tregister unsigned i;\n\tunsigned j;\n{\n\tchar *cp;\n\n\ti *= j;\n\tcp = xalloc(i);\n\tbzero(cp, (int)i);\n\treturn (cp);\n}\n#endif\n\nnomem(i)\n\tunsigned i;\n{\n#ifdef debug\n\tstatic char *av[2] = {0, 0};\n#endif\n\n\tchild++;\n#ifndef debug\n\terror(\"Out of memory\");\n#ifdef lint\n\ti = i;\n#endif\n#else\n\tshowall(av);\n\tprintf(\"i=%d: Out of memory\\n\", i);\n\tchdir(\"/tmp\");\n\tabort();\n#endif\n\treturn 0;\t\t/* fool lint */\n}\n\nchar **\nblkend(up)\n\tregister char **up;\n{\n\n\twhile (*up)\n\t\tup++;\n\treturn (up);\n}\n\nblkpr(av)\n\tregister char **av;\n{\n\n\tfor (; *av; av++) {\n\t\tprintf(\"%s\", *av);\n\t\tif (av[1])\n\t\t\tprintf(\" \");\n\t}\n}\n\nblklen(av)\n\tregister char **av;\n{\n\tregister int i = 0;\n\n\twhile (*av++)\n\t\ti++;\n\treturn (i);\n}\n\nchar **\nblkcpy(oav, bv)\n\tchar **oav;\n\tregister char **bv;\n{\n\tregister char **av = oav;\n\n\twhile (*av++ = *bv++)\n\t\tcontinue;\n\treturn (oav);\n}\n\nchar **\nblkcat(up, vp)\n\tchar **up, **vp;\n{\n\n\t(void) blkcpy(blkend(up), vp);\n\treturn (up);\n}\n\nblkfree(av0)\n\tchar **av0;\n{\n\tregister char **av = av0;\n\n\tfor (; *av; av++)\n\t\tXFREE(*av)\n\tXFREE((char *)av0)\n}\n\nchar **\nsaveblk(v)\n\tregister char **v;\n{\n\tregister char **newv =\n\t\t(char **) calloc((unsigned) (blklen(v) + 1), sizeof (char **));\n\tchar **onewv = newv;\n\n\twhile (*v)\n\t\t*newv++ = savestr(*v++);\n\treturn (onewv);\n}\n\nchar *\nstrspl(cp, dp)\n\tchar *cp, *dp;\n{\n\tchar *ep;\n\tregister char *p, *q;\n\n\tfor (p = cp; *p++;)\n\t\t;\n\tfor (q = dp; *q++;)\n\t\t;\n\tep = xalloc((unsigned) ((p - cp) + (q - dp) - 1));\n\tfor (p = ep, q = cp; *p++ = *q++;)\n\t\t;\n\tfor (p--, q = dp; *p++ = *q++;)\n\t\t;\n\treturn (ep);\n}\n\nchar **\nblkspl(up, vp)\n\tregister char **up, **vp;\n{\n\tregister char **wp =\n\t\t(char **) calloc((unsigned) (blklen(up) + blklen(vp) + 1),\n\t\t\tsizeof (char **));\n\n\t(void) blkcpy(wp, up);\n\treturn (blkcat(wp, vp));\n}\n\nlastchr(cp)\n\tregister char *cp;\n{\n\n\tif (!*cp)\n\t\treturn (0);\n\twhile (cp[1])\n\t\tcp++;\n\treturn (*cp);\n}\n\n/*\n * This routine is called after an error to close up\n * any units which may have been left open accidentally.\n */\nclosem()\n{\n\tregister int f;\n\n\tfor (f = 0; f < NOFILE; f++)\n\t\tif (f != SHIN && f != SHOUT && f != SHDIAG && f != OLDSTD &&\n\t\t    f != FSHTTY)\n\t\t\t(void) close(f);\n}\n\ndonefds()\n{\n\n\t(void) close(0);\n\t(void) close(1);\n\t(void) close(2);\n\tdidfds = 0;\n}\n\n/*\n * Move descriptor i to j.\n * If j is -1 then we just want to get i to a safe place,\n * i.e. to a unit > 2.  This also happens in dcopy.\n */\ndmove(i, j)\n\tregister int i, j;\n{\n\n\tif (i == j || i < 0)\n\t\treturn (i);\n\tif (j >= 0) {\n\t\t(void) dup2(i, j);\n\t\treturn (j);\n\t}\n\tj = dcopy(i, j);\n\tif (j != i)\n\t\t(void) close(i);\n\treturn (j);\n}\n\ndcopy(i, j)\n\tregister int i, j;\n{\n\n\tif (i == j || i < 0 || j < 0 && i > 2)\n\t\treturn (i);\n\tif (j >= 0) {\n\t\t(void) dup2(i, j);\n\t\treturn (j);\n\t}\n\t(void) close(j);\n\treturn (renum(i, j));\n}\n\nrenum(i, j)\n\tregister int i, j;\n{\n\tregister int k = dup(i);\n\n\tif (k < 0)\n\t\treturn (-1);\n\tif (j == -1 && k > 2)\n\t\treturn (k);\n\tif (k != j) {\n\t\tj = renum(k, j);\n\t\t(void) close(k);\n\t\treturn (j);\n\t}\n\treturn (k);\n}\n\n#ifndef copy\ncopy(to, from, size)\n\tregister char *to, *from;\n\tregister int size;\n{\n\n\tif (size)\n\t\tdo\n\t\t\t*to++ = *from++;\n\t\twhile (--size != 0);\n}\n#endif\n\n/*\n * Left shift a command argument list, discarding\n * the first c arguments.  Used in \"shift\" commands\n * as well as by commands like \"repeat\".\n */\nlshift(v, c)\n\tregister char **v;\n\tregister int c;\n{\n\tregister char **u = v;\n\n\twhile (*u && --c >= 0)\n\t\txfree(*u++);\n\t(void) blkcpy(v, u);\n}\n\nnumber(cp)\n\tchar *cp;\n{\n\n\tif (*cp == '-') {\n\t\tcp++;\n\t\tif (!digit(*cp++))\n\t\t\treturn (0);\n\t}\n\twhile (*cp && digit(*cp))\n\t\tcp++;\n\treturn (*cp == 0);\n}\n\nchar **\ncopyblk(v)\n\tregister char **v;\n{\n\tregister char **nv =\n\t\t(char **) calloc((unsigned) (blklen(v) + 1), sizeof (char **));\n\n\treturn (blkcpy(nv, v));\n}\n\nchar *\nstrend(cp)\n\tregister char *cp;\n{\n\n\twhile (*cp)\n\t\tcp++;\n\treturn (cp);\n}\n\nchar *\nstrip(cp)\n\tchar *cp;\n{\n\tregister char *dp = cp;\n\n\twhile (*dp++ &= TRIM)\n\t\tcontinue;\n\treturn (cp);\n}\n\nudvar(name)\n\tchar *name;\n{\n\n\tsetname(name);\n\tbferr(\"Undefined variable\");\n}\n\nprefix(sub, str)\n\tregister char *sub, *str;\n{\n\n\tfor (;;) {\n\t\tif (*sub == 0)\n\t\t\treturn (1);\n\t\tif (*str == 0)\n\t\t\treturn (0);\n\t\tif (*sub++ != *str++)\n\t\t\treturn (0);\n\t}\n}\n"
  },
  {
    "path": "bin/csh/sh.parse.c",
    "content": "/*\n * C shell\n *\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"sh.h\"\n\n/*\n * Perform aliasing on the word list lex\n * Do a (very rudimentary) parse to separate into commands.\n * If word 0 of a command has an alias, do it.\n * Repeat a maximum of 20 times.\n */\nalias(lex)\n\tregister struct wordent *lex;\n{\n\tint aleft = 21;\n\tjmp_buf osetexit;\n\n\tgetexit(osetexit);\n\tsetexit();\n\tif (haderr) {\n\t\tresexit(osetexit);\n\t\treset();\n\t}\n\tif (--aleft == 0)\n\t\terror(\"Alias loop\");\n\tasyntax(lex->next, lex);\n\tresexit(osetexit);\n}\n\nasyntax(p1, p2)\n\tregister struct wordent *p1, *p2;\n{\n\n\twhile (p1 != p2)\n\t\tif (any(p1->word[0], \";&\\n\"))\n\t\t\tp1 = p1->next;\n\t\telse {\n\t\t\tasyn0(p1, p2);\n\t\t\treturn;\n\t\t}\n}\n\nasyn0(p1, p2)\n\tstruct wordent *p1;\n\tregister struct wordent *p2;\n{\n\tregister struct wordent *p;\n\tregister int l = 0;\n\n\tfor (p = p1; p != p2; p = p->next)\n\t\tswitch (p->word[0]) {\n\n\t\tcase '(':\n\t\t\tl++;\n\t\t\tcontinue;\n\n\t\tcase ')':\n\t\t\tl--;\n\t\t\tif (l < 0)\n\t\t\t\terror(\"Too many )'s\");\n\t\t\tcontinue;\n\n\t\tcase '>':\n\t\t\tif (p->next != p2 && eq(p->next->word, \"&\"))\n\t\t\t\tp = p->next;\n\t\t\tcontinue;\n\n\t\tcase '&':\n\t\tcase '|':\n\t\tcase ';':\n\t\tcase '\\n':\n\t\t\tif (l != 0)\n\t\t\t\tcontinue;\n\t\t\tasyn3(p1, p);\n\t\t\tasyntax(p->next, p2);\n\t\t\treturn;\n\t\t}\n\tif (l == 0)\n\t\tasyn3(p1, p2);\n}\n\nasyn3(p1, p2)\n\tstruct wordent *p1;\n\tregister struct wordent *p2;\n{\n\tregister struct varent *ap;\n\tstruct wordent alout;\n\tregister bool redid;\n\n\tif (p1 == p2)\n\t\treturn;\n\tif (p1->word[0] == '(') {\n\t\tfor (p2 = p2->prev; p2->word[0] != ')'; p2 = p2->prev)\n\t\t\tif (p2 == p1)\n\t\t\t\treturn;\n\t\tif (p2 == p1->next)\n\t\t\treturn;\n\t\tasyn0(p1->next, p2);\n\t\treturn;\n\t}\n\tap = adrof1(p1->word, &aliases);\n\tif (ap == 0)\n\t\treturn;\n\talhistp = p1->prev;\n\talhistt = p2;\n\talvec = ap->vec;\n\tredid = lex(&alout);\n\talhistp = alhistt = 0;\n\talvec = 0;\n\tif (parserr) {\n\t\tfreelex(&alout);\n\t\terror(parserr);\n\t}\n\tif (p1->word[0] && eq(p1->word, alout.next->word)) {\n\t\tchar *cp = alout.next->word;\n\n\t\talout.next->word = strspl(\"\\200\", cp);\n\t\tXFREE(cp)\n\t}\n\tp1 = freenod(p1, redid ? p2 : p1->next);\n\tif (alout.next != &alout) {\n\t\tp1->next->prev = alout.prev->prev;\n\t\talout.prev->prev->next = p1->next;\n\t\talout.next->prev = p1;\n\t\tp1->next = alout.next;\n\t\tXFREE(alout.prev->word)\n\t\tXFREE((char *)alout.prev)\n\t}\n\treset();\t\t/* throw! */\n}\n\nstruct wordent *\nfreenod(p1, p2)\n\tregister struct wordent *p1, *p2;\n{\n\tregister struct wordent *retp = p1->prev;\n\n\twhile (p1 != p2) {\n\t\tXFREE(p1->word)\n\t\tp1 = p1->next;\n\t\tXFREE((char *)p1->prev)\n\t}\n\tretp->next = p2;\n\tp2->prev = retp;\n\treturn (retp);\n}\n\n#define\tPHERE\t1\n#define\tPIN\t2\n#define\tPOUT\t4\n#define\tPDIAG\t8\n\n/*\n * syntax\n *\tempty\n *\tsyn0\n */\nstruct command *\nsyntax(p1, p2, flags)\n\tregister struct wordent *p1, *p2;\n\tint flags;\n{\n\n\twhile (p1 != p2)\n\t\tif (any(p1->word[0], \";&\\n\"))\n\t\t\tp1 = p1->next;\n\t\telse\n\t\t\treturn (syn0(p1, p2, flags));\n\treturn (0);\n}\n\n/*\n * syn0\n *\tsyn1\n *\tsyn1 & syntax\n */\nstruct command *\nsyn0(p1, p2, flags)\n\tstruct wordent *p1, *p2;\n\tint flags;\n{\n\tregister struct wordent *p;\n\tregister struct command *t, *t1;\n\tint l;\n\n\tl = 0;\n\tfor (p = p1; p != p2; p = p->next)\n\t\tswitch (p->word[0]) {\n\n\t\tcase '(':\n\t\t\tl++;\n\t\t\tcontinue;\n\n\t\tcase ')':\n\t\t\tl--;\n\t\t\tif (l < 0)\n\t\t\t\tseterr(\"Too many )'s\");\n\t\t\tcontinue;\n\n\t\tcase '|':\n\t\t\tif (p->word[1] == '|')\n\t\t\t\tcontinue;\n\t\t\t/* fall into ... */\n\n\t\tcase '>':\n\t\t\tif (p->next != p2 && eq(p->next->word, \"&\"))\n\t\t\t\tp = p->next;\n\t\t\tcontinue;\n\n\t\tcase '&':\n\t\t\tif (l != 0)\n\t\t\t\tbreak;\n\t\t\tif (p->word[1] == '&')\n\t\t\t\tcontinue;\n\t\t\tt1 = syn1(p1, p, flags);\n    \t\t\tif (t1->t_dtyp == TLST ||\n    \t\t\t    t1->t_dtyp == TAND ||\n    \t\t\t    t1->t_dtyp == TOR) {\n\t\t\t\tt = (struct command *) calloc(1, sizeof (*t));\n\t\t\t\tt->t_dtyp = TPAR;\n\t\t\t\tt->t_dflg = FAND|FINT;\n\t\t\t\tt->t_dspr = t1;\n\t\t\t\tt1 = t;\n\t\t\t} else\n\t\t\t\tt1->t_dflg |= FAND|FINT;\n\t\t\tt = (struct command *) calloc(1, sizeof (*t));\n\t\t\tt->t_dtyp = TLST;\n\t\t\tt->t_dflg = 0;\n\t\t\tt->t_dcar = t1;\n\t\t\tt->t_dcdr = syntax(p, p2, flags);\n\t\t\treturn(t);\n\t\t}\n\tif (l == 0)\n\t\treturn (syn1(p1, p2, flags));\n\tseterr(\"Too many ('s\");\n\treturn (0);\n}\n\n/*\n * syn1\n *\tsyn1a\n *\tsyn1a ; syntax\n */\nstruct command *\nsyn1(p1, p2, flags)\n\tstruct wordent *p1, *p2;\n\tint flags;\n{\n\tregister struct wordent *p;\n\tregister struct command *t;\n\tint l;\n\n\tl = 0;\n\tfor (p = p1; p != p2; p = p->next)\n\t\tswitch (p->word[0]) {\n\n\t\tcase '(':\n\t\t\tl++;\n\t\t\tcontinue;\n\n\t\tcase ')':\n\t\t\tl--;\n\t\t\tcontinue;\n\n\t\tcase ';':\n\t\tcase '\\n':\n\t\t\tif (l != 0)\n\t\t\t\tbreak;\n\t\t\tt = (struct command *) calloc(1, sizeof (*t));\n\t\t\tt->t_dtyp = TLST;\n\t\t\tt->t_dcar = syn1a(p1, p, flags);\n\t\t\tt->t_dcdr = syntax(p->next, p2, flags);\n\t\t\tif (t->t_dcdr == 0)\n\t\t\t\tt->t_dcdr = t->t_dcar, t->t_dcar = 0;\n\t\t\treturn (t);\n\t\t}\n\treturn (syn1a(p1, p2, flags));\n}\n\n/*\n * syn1a\n *\tsyn1b\n *\tsyn1b || syn1a\n */\nstruct command *\nsyn1a(p1, p2, flags)\n\tstruct wordent *p1, *p2;\n\tint flags;\n{\n\tregister struct wordent *p;\n\tregister struct command *t;\n\tregister int l = 0;\n\n\tfor (p = p1; p != p2; p = p->next)\n\t\tswitch (p->word[0]) {\n\n\t\tcase '(':\n\t\t\tl++;\n\t\t\tcontinue;\n\n\t\tcase ')':\n\t\t\tl--;\n\t\t\tcontinue;\n\n\t\tcase '|':\n\t\t\tif (p->word[1] != '|')\n\t\t\t\tcontinue;\n\t\t\tif (l == 0) {\n\t\t\t\tt = (struct command *) calloc(1, sizeof (*t));\n\t\t\t\tt->t_dtyp = TOR;\n\t\t\t\tt->t_dcar = syn1b(p1, p, flags);\n\t\t\t\tt->t_dcdr = syn1a(p->next, p2, flags);\n\t\t\t\tt->t_dflg = 0;\n\t\t\t\treturn (t);\n\t\t\t}\n\t\t\tcontinue;\n\t\t}\n\treturn (syn1b(p1, p2, flags));\n}\n\n/*\n * syn1b\n *\tsyn2\n *\tsyn2 && syn1b\n */\nstruct command *\nsyn1b(p1, p2, flags)\n\tstruct wordent *p1, *p2;\n\tint flags;\n{\n\tregister struct wordent *p;\n\tregister struct command *t;\n\tregister int l = 0;\n\n\tl = 0;\n\tfor (p = p1; p != p2; p = p->next)\n\t\tswitch (p->word[0]) {\n\n\t\tcase '(':\n\t\t\tl++;\n\t\t\tcontinue;\n\n\t\tcase ')':\n\t\t\tl--;\n\t\t\tcontinue;\n\n\t\tcase '&':\n\t\t\tif (p->word[1] == '&' && l == 0) {\n\t\t\t\tt = (struct command *) calloc(1, sizeof (*t));\n\t\t\t\tt->t_dtyp = TAND;\n\t\t\t\tt->t_dcar = syn2(p1, p, flags);\n\t\t\t\tt->t_dcdr = syn1b(p->next, p2, flags);\n\t\t\t\tt->t_dflg = 0;\n\t\t\t\treturn (t);\n\t\t\t}\n\t\t\tcontinue;\n\t\t}\n\treturn (syn2(p1, p2, flags));\n}\n\n/*\n * syn2\n *\tsyn3\n *\tsyn3 | syn2\n *\tsyn3 |& syn2\n */\nstruct command *\nsyn2(p1, p2, flags)\n\tstruct wordent *p1, *p2;\n\tint flags;\n{\n\tregister struct wordent *p, *pn;\n\tregister struct command *t;\n\tregister int l = 0;\n\tint f;\n\n\tfor (p = p1; p != p2; p = p->next)\n\t\tswitch (p->word[0]) {\n\n\t\tcase '(':\n\t\t\tl++;\n\t\t\tcontinue;\n\n\t\tcase ')':\n\t\t\tl--;\n\t\t\tcontinue;\n\n\t\tcase '|':\n\t\t\tif (l != 0)\n\t\t\t\tcontinue;\n\t\t\tt = (struct command *) calloc(1, sizeof (*t));\n\t\t\tf = flags | POUT;\n\t\t\tpn = p->next;\n\t\t\tif (pn != p2 && pn->word[0] == '&') {\n\t\t\t\tf |= PDIAG;\n\t\t\t\tt->t_dflg |= FDIAG;\n\t\t\t}\n\t\t\tt->t_dtyp = TFIL;\n\t\t\tt->t_dcar = syn3(p1, p, f);\n\t\t\tif (pn != p2 && pn->word[0] == '&')\n\t\t\t\tp = pn;\n\t\t\tt->t_dcdr = syn2(p->next, p2, flags | PIN);\n\t\t\treturn (t);\n\t\t}\n\treturn (syn3(p1, p2, flags));\n}\n\nchar\t*RELPAR =\t\"<>()\";\n\n/*\n * syn3\n *\t( syn0 ) [ < in  ] [ > out ]\n *\tword word* [ < in ] [ > out ]\n *\tKEYWORD ( word* ) word* [ < in ] [ > out ]\n *\n *\tKEYWORD = (@ exit foreach if set switch test while)\n */\nstruct command *\nsyn3(p1, p2, flags)\n\tstruct wordent *p1, *p2;\n\tint flags;\n{\n\tregister struct wordent *p;\n\tstruct wordent *lp, *rp;\n\tregister struct command *t;\n\tregister int l;\n\tchar **av;\n\tint n, c;\n\tbool specp = 0;\n\n\tif (p1 != p2) {\n\t\tp = p1;\nagain:\n\t\tswitch (srchx(p->word)) {\n\n\t\tcase ZELSE:\n\t\t\tp = p->next;\n\t\t\tif (p != p2)\n\t\t\t\tgoto again;\n\t\t\tbreak;\n\n\t\tcase ZEXIT:\n\t\tcase ZFOREACH:\n\t\tcase ZIF:\n\t\tcase ZLET:\n\t\tcase ZSET:\n\t\tcase ZSWITCH:\n\t\tcase ZWHILE:\n\t\t\tspecp = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\tn = 0;\n\tl = 0;\n\tfor (p = p1; p != p2; p = p->next)\n\t\tswitch (p->word[0]) {\n\n\t\tcase '(':\n\t\t\tif (specp)\n\t\t\t\tn++;\n\t\t\tl++;\n\t\t\tcontinue;\n\n\t\tcase ')':\n\t\t\tif (specp)\n\t\t\t\tn++;\n\t\t\tl--;\n\t\t\tcontinue;\n\n\t\tcase '>':\n\t\tcase '<':\n\t\t\tif (l != 0) {\n\t\t\t\tif (specp)\n\t\t\t\t\tn++;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (p->next == p2)\n\t\t\t\tcontinue;\n\t\t\tif (any(p->next->word[0], RELPAR))\n\t\t\t\tcontinue;\n\t\t\tn--;\n\t\t\tcontinue;\n\n\t\tdefault:\n\t\t\tif (!specp && l != 0)\n\t\t\t\tcontinue;\n\t\t\tn++;\n\t\t\tcontinue;\n\t\t}\n\tif (n < 0)\n\t\tn = 0;\n\tt = (struct command *) calloc(1, sizeof (*t));\n\tav = (char **) calloc((unsigned) (n + 1), sizeof (char **));\n\tt->t_dcom = av;\n\tn = 0;\n\tif (p2->word[0] == ')')\n\t\tt->t_dflg = FPAR;\n\tlp = 0;\n\trp = 0;\n\tl = 0;\n\tfor (p = p1; p != p2; p = p->next) {\n\t\tc = p->word[0];\n\t\tswitch (c) {\n\n\t\tcase '(':\n\t\t\tif (l == 0) {\n\t\t\t\tif (lp != 0 && !specp)\n\t\t\t\t\tseterr(\"Badly placed (\");\n\t\t\t\tlp = p->next;\n\t\t\t}\n\t\t\tl++;\n\t\t\tgoto savep;\n\n\t\tcase ')':\n\t\t\tl--;\n\t\t\tif (l == 0)\n\t\t\t\trp = p;\n\t\t\tgoto savep;\n\n\t\tcase '>':\n\t\t\tif (l != 0)\n\t\t\t\tgoto savep;\n\t\t\tif (p->word[1] == '>')\n\t\t\t\tt->t_dflg |= FCAT;\n\t\t\tif (p->next != p2 && eq(p->next->word, \"&\")) {\n\t\t\t\tt->t_dflg |= FDIAG, p = p->next;\n\t\t\t\tif (flags & (POUT|PDIAG))\n\t\t\t\t\tgoto badout;\n\t\t\t}\n\t\t\tif (p->next != p2 && eq(p->next->word, \"!\"))\n\t\t\t\tt->t_dflg |= FANY, p = p->next;\n\t\t\tif (p->next == p2) {\nmissfile:\n\t\t\t\tseterr(\"Missing name for redirect\");\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tp = p->next;\n\t\t\tif (any(p->word[0], RELPAR))\n\t\t\t\tgoto missfile;\n\t\t\tif ((flags & POUT) && (flags & PDIAG) == 0 || t->t_drit)\nbadout:\n\t\t\t\tseterr(\"Ambiguous output redirect\");\n\t\t\telse\n\t\t\t\tt->t_drit = savestr(p->word);\n\t\t\tcontinue;\n\n\t\tcase '<':\n\t\t\tif (l != 0)\n\t\t\t\tgoto savep;\n\t\t\tif (p->word[1] == '<')\n\t\t\t\tt->t_dflg |= FHERE;\n\t\t\tif (p->next == p2)\n\t\t\t\tgoto missfile;\n\t\t\tp = p->next;\n\t\t\tif (any(p->word[0], RELPAR))\n\t\t\t\tgoto missfile;\n\t\t\tif ((flags & PHERE) && (t->t_dflg & FHERE))\n\t\t\t\tseterr(\"Can't << within ()'s\");\n\t\t\telse if ((flags & PIN) || t->t_dlef)\n\t\t\t\tseterr(\"Ambiguous input redirect\");\n\t\t\telse\n\t\t\t\tt->t_dlef = savestr(p->word);\n\t\t\tcontinue;\n\nsavep:\n\t\t\tif (!specp)\n\t\t\t\tcontinue;\n\t\tdefault:\n\t\t\tif (l != 0 && !specp)\n\t\t\t\tcontinue;\n\t\t\tif (parserr == 0)\n\t\t\t\tav[n] = savestr(p->word);\n\t\t\tn++;\n\t\t\tcontinue;\n\t\t}\n\t}\n\tif (lp != 0 && !specp) {\n\t\tif (n != 0)\n\t\t\tseterr(\"Badly placed ()'s\");\n\t\tt->t_dtyp = TPAR;\n\t\tt->t_dspr = syn0(lp, rp, PHERE);\n\t} else {\n\t\tif (n == 0)\n\t\t\tseterr(\"Invalid null command\");\n\t\tt->t_dtyp = TCOM;\n\t}\n\treturn (t);\n}\n\nfreesyn(t)\n\tregister struct command *t;\n{\n\tregister char **v;\n\n\tif (t == 0)\n\t\treturn;\n\tswitch (t->t_dtyp) {\n\n\tcase TCOM:\n\t\tfor (v = t->t_dcom; *v; v++)\n\t\t\tXFREE(*v)\n\t\tXFREE((char *)t->t_dcom)\n\t\tgoto lr;\n\n\tcase TPAR:\n\t\tfreesyn(t->t_dspr);\n\t\t/* fall into ... */\n\nlr:\n\t\tXFREE(t->t_dlef)\n\t\tXFREE(t->t_drit)\n\t\tbreak;\n\n\tcase TAND:\n\tcase TOR:\n\tcase TFIL:\n\tcase TLST:\n\t\tfreesyn(t->t_dcar), freesyn(t->t_dcdr);\n\t\tbreak;\n\t}\n\tXFREE((char *)t)\n}\n"
  },
  {
    "path": "bin/csh/sh.print.c",
    "content": "/*\n * C Shell\n *\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"sh.h\"\n#include <sys/ioctl.h>\n\npsecs(l)\n\tlong l;\n{\n\tregister int i;\n\n\ti = l / 3600;\n\tif (i) {\n\t\tprintf(\"%d:\", i);\n\t\ti = l % 3600;\n\t\tp2dig(i / 60);\n\t\tgoto minsec;\n\t}\n\ti = l;\n\tprintf(\"%d\", i / 60);\nminsec:\n\ti %= 60;\n\tprintf(\":\");\n\tp2dig(i);\n}\n\np2dig(i)\n\tregister int i;\n{\n\n\tprintf(\"%d%d\", i / 10, i % 10);\n}\n\nchar\tlinbuf[128];\nchar\t*linp = linbuf;\n\nvoid putchr(c)\n\tregister int c;\n{\n\tif ((c & QUOTE) == 0 && (c == 0177 || c < ' ' && c != '\\t' && c != '\\n')) {\n\t\tputchar('^');\n\t\tif (c == 0177)\n\t\t\tc = '?';\n\t\telse\n\t\t\tc |= 'A' - 1;\n\t}\n\tc &= TRIM;\n\t*linp++ = c;\n\tif (c == '\\n' || linp >= &linbuf[sizeof linbuf - 2])\n\t\tflush();\n}\n\ndraino()\n{\n\n\tlinp = linbuf;\n}\n\nflush()\n{\n\tregister int unit;\n\tint lmode;\n\n\tif (linp == linbuf)\n\t\treturn;\n\tif (haderr)\n\t\tunit = didfds ? 2 : SHDIAG;\n\telse\n\t\tunit = didfds ? 1 : SHOUT;\n#ifdef TIOCLGET\n\tif (didfds == 0 && ioctl(unit, TIOCLGET, (char *)&lmode) == 0 &&\n\t    lmode&LFLUSHO) {\n\t\tlmode = LFLUSHO;\n\t\t(void) ioctl(unit, TIOCLBIC, (char *)&lmode);\n\t\t(void) write(unit, \"\\n\", 1);\n\t}\n#endif\n\t(void) write(unit, linbuf, linp - linbuf);\n\tlinp = linbuf;\n}\n"
  },
  {
    "path": "bin/csh/sh.proc.c",
    "content": "/*\n * C Shell - functions that manage processes, handling hanging, termination\n *\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"sh.h\"\n#include \"sh.dir.h\"\n#include \"sh.proc.h\"\n#include <string.h>\n#include <sys/wait.h>\n#include <sys/ioctl.h>\n\n#define BIGINDEX\t9\t/* largest desirable job index */\n\n/*\n * pchild - called at interrupt level by the SIGCHLD signal\n *\tindicating that at least one child has terminated or stopped\n *\tthus at least one wait system call will definitely return a\n *\tchilds status.  Top level routines (like pwait) must be sure\n *\tto mask interrupts when playing with the proclist data structures!\n */\nvoid pchild(int sig)\n{\n\tregister struct process *pp;\n\tregister struct process\t*fp;\n\tregister int pid;\n\tunion wait w;\n\tint jobflags;\n\tstruct rusage ru;\n\nloop:\n\tpid = wait3((int*) &w, (setintr ? WNOHANG|WUNTRACED:WNOHANG), &ru);\n\tif (pid <= 0) {\n\t\tif (errno == EINTR) {\n\t\t\terrno = 0;\n\t\t\tgoto loop;\n\t\t}\n\t\tpnoprocesses = pid == -1;\n\t\treturn;\n\t}\n\tfor (pp = proclist.p_next; pp != PNULL; pp = pp->p_next)\n\t\tif (pid == pp->p_pid)\n\t\t\tgoto found;\n\tgoto loop;\nfound:\n\tif (pid == atoi(value(\"child\")))\n\t\tunsetv(\"child\");\n\tpp->p_flags &= ~(PRUNNING|PSTOPPED|PREPORTED);\n\tif (WIFSTOPPED(w)) {\n\t\tpp->p_flags |= PSTOPPED;\n\t\tpp->p_reason = w.w_stopsig;\n\t} else {\n\t\tif (pp->p_flags & (PTIME|PPTIME) || adrof(\"time\"))\n\t\t\t(void) gettimeofday(&pp->p_etime, (struct timezone *)0);\n\t\tpp->p_rusage = ru;\n\t\tif (WIFSIGNALED(w)) {\n\t\t\tif (w.w_termsig == SIGINT)\n\t\t\t\tpp->p_flags |= PINTERRUPTED;\n\t\t\telse\n\t\t\t\tpp->p_flags |= PSIGNALED;\n\t\t\tif (w.w_coredump)\n\t\t\t\tpp->p_flags |= PDUMPED;\n\t\t\tpp->p_reason = w.w_termsig;\n\t\t} else {\n\t\t\tpp->p_reason = w.w_retcode;\n\t\t\tif (pp->p_reason != 0)\n\t\t\t\tpp->p_flags |= PAEXITED;\n\t\t\telse\n\t\t\t\tpp->p_flags |= PNEXITED;\n\t\t}\n\t}\n\tjobflags = 0;\n\tfp = pp;\n\tdo {\n\t\tif ((fp->p_flags & (PPTIME|PRUNNING|PSTOPPED)) == 0 &&\n\t\t    !child && adrof(\"time\") &&\n\t\t    fp->p_rusage.ru_utime.tv_sec+fp->p_rusage.ru_stime.tv_sec >=\n\t\t     atoi(value(\"time\")))\n\t\t\tfp->p_flags |= PTIME;\n\t\tjobflags |= fp->p_flags;\n\t} while ((fp = fp->p_friends) != pp);\n\tpp->p_flags &= ~PFOREGND;\n\tif (pp == pp->p_friends && (pp->p_flags & PPTIME)) {\n\t\tpp->p_flags &= ~PPTIME;\n\t\tpp->p_flags |= PTIME;\n\t}\n\tif ((jobflags & (PRUNNING|PREPORTED)) == 0) {\n\t\tfp = pp;\n\t\tdo {\n\t\t\tif (fp->p_flags&PSTOPPED)\n\t\t\t\tfp->p_flags |= PREPORTED;\n\t\t} while((fp = fp->p_friends) != pp);\n\t\twhile(fp->p_pid != fp->p_jobid)\n\t\t\tfp = fp->p_friends;\n\t\tif (jobflags&PSTOPPED) {\n\t\t\tif (pcurrent && pcurrent != fp)\n\t\t\t\tpprevious = pcurrent;\n\t\t\tpcurrent = fp;\n\t\t} else\n\t\t\tpclrcurr(fp);\n\t\tif (jobflags&PFOREGND) {\n\t\t\tif (jobflags & (PSIGNALED|PSTOPPED|PPTIME) ||\n#ifdef IIASA\n\t\t\t    jobflags & PAEXITED ||\n#endif\n\t\t\t    !eq(dcwd->di_name, fp->p_cwd->di_name)) {\n\t\t\t\t;\t/* print in pjwait */\n\t\t\t}\n/*\n\t\telse if ((jobflags & (PTIME|PSTOPPED)) == PTIME)\n\t\t\t\tptprint(fp);\n*/\n\t\t} else {\n\t\t\tif (jobflags&PNOTIFY || adrof(\"notify\")) {\n\t\t\t\tprintf(\"\\215\\n\");\n\t\t\t\t(void) pprint(pp, NUMBER|NAME|REASON);\n\t\t\t\tif ((jobflags&PSTOPPED) == 0)\n\t\t\t\t\tpflush(pp);\n\t\t\t} else {\n\t\t\t\tfp->p_flags |= PNEEDNOTE;\n\t\t\t\tneednote++;\n\t\t\t}\n\t\t}\n\t}\n\tgoto loop;\n}\n\npnote()\n{\n\tregister struct process *pp;\n\tint flags;\n\tlong omask;\n\n\tneednote = 0;\n\tfor (pp = proclist.p_next; pp != PNULL; pp = pp->p_next) {\n\t\tif (pp->p_flags & PNEEDNOTE) {\n\t\t\tomask = sigblock(sigmask(SIGCHLD));\n\t\t\tpp->p_flags &= ~PNEEDNOTE;\n\t\t\tflags = pprint(pp, NUMBER|NAME|REASON);\n\t\t\tif ((flags&(PRUNNING|PSTOPPED)) == 0)\n\t\t\t\tpflush(pp);\n\t\t\t(void) sigsetmask(omask);\n\t\t}\n\t}\n}\n\n/*\n * pwait - wait for current job to terminate, maintaining integrity\n *\tof current and previous job indicators.\n */\npwait()\n{\n\tregister struct process *fp, *pp;\n\tlong omask;\n\n\t/*\n\t * Here's where dead procs get flushed.\n\t */\n\tomask = sigblock(sigmask(SIGCHLD));\n\tfor (pp = (fp = &proclist)->p_next; pp != PNULL; pp = (fp = pp)->p_next)\n\t\tif (pp->p_pid == 0) {\n\t\t\tfp->p_next = pp->p_next;\n\t\t\txfree(pp->p_command);\n\t\t\tif (pp->p_cwd && --pp->p_cwd->di_count == 0)\n\t\t\t\tif (pp->p_cwd->di_next == 0)\n\t\t\t\t\tdfree(pp->p_cwd);\n\t\t\txfree((char *)pp);\n\t\t\tpp = fp;\n\t\t}\n\t(void) sigsetmask(omask);\n\tpjwait(pcurrjob);\n}\n\n/*\n * pjwait - wait for a job to finish or become stopped\n *\tIt is assumed to be in the foreground state (PFOREGND)\n */\npjwait(pp)\n\tregister struct process *pp;\n{\n\tregister struct process *fp;\n\tint jobflags, reason;\n\tlong omask;\n\n\twhile (pp->p_pid != pp->p_jobid)\n\t\tpp = pp->p_friends;\n\tfp = pp;\n\tdo {\n\t\tif ((fp->p_flags&(PFOREGND|PRUNNING)) == PRUNNING)\n\t\t\tprintf(\"BUG: waiting for background job!\\n\");\n\t} while ((fp = fp->p_friends) != pp);\n\t/*\n\t * Now keep pausing as long as we are not interrupted (SIGINT),\n\t * and the target process, or any of its friends, are running\n\t */\n\tfp = pp;\n\tomask = sigblock(sigmask(SIGCHLD));\n\tfor (;;) {\n\t\tjobflags = 0;\n\t\tdo\n\t\t\tjobflags |= fp->p_flags;\n\t\twhile ((fp = (fp->p_friends)) != pp);\n\t\tif ((jobflags & PRUNNING) == 0)\n\t\t\tbreak;\n\t\tsigpause(sigblock(0L) &~ sigmask(SIGCHLD));\n\t}\n\t(void) sigsetmask(omask);\n\tif (tpgrp > 0)\t\t\t/* get tty back */\n\t\t(void) ioctl(FSHTTY, TIOCSPGRP, (char *)&tpgrp);\n\tif ((jobflags&(PSIGNALED|PSTOPPED|PTIME)) ||\n\t     !eq(dcwd->di_name, fp->p_cwd->di_name)) {\n\t\tif (jobflags&PSTOPPED)\n\t\t\tprintf(\"\\n\");\n\t\t(void) pprint(pp, AREASON|SHELLDIR);\n\t}\n\tif ((jobflags&(PINTERRUPTED|PSTOPPED)) && setintr &&\n\t    (!gointr || !eq(gointr, \"-\"))) {\n\t\tif ((jobflags & PSTOPPED) == 0)\n\t\t\tpflush(pp);\n\t\tpintr1(0);\n\t\t/*NOTREACHED*/\n\t}\n\treason = 0;\n\tfp = pp;\n\tdo {\n\t\tif (fp->p_reason)\n\t\t\treason = fp->p_flags & (PSIGNALED|PINTERRUPTED) ?\n\t\t\t\tfp->p_reason | QUOTE : fp->p_reason;\n\t} while ((fp = fp->p_friends) != pp);\n\tset(\"status\", putn(reason));\n\tif (reason && exiterr)\n\t\texitstat();\n\tpflush(pp);\n}\n\n/*\n * dowait - wait for all processes to finish\n */\ndowait()\n{\n\tregister struct process *pp;\n\tlong omask;\n\n\tpjobs++;\n\tomask = sigblock(sigmask(SIGCHLD));\nloop:\n\tfor (pp = proclist.p_next; pp; pp = pp->p_next)\n\t\tif (pp->p_pid && /* pp->p_pid == pp->p_jobid && */\n\t\t    pp->p_flags&PRUNNING) {\n\t\t\tsigpause(0L);\n\t\t\tgoto loop;\n\t\t}\n\t(void) sigsetmask(omask);\n\tpjobs = 0;\n}\n\n/*\n * pflushall - flush all jobs from list (e.g. at fork())\n */\npflushall()\n{\n\tregister struct process\t*pp;\n\n\tfor (pp = proclist.p_next; pp != PNULL; pp = pp->p_next)\n\t\tif (pp->p_pid)\n\t\t\tpflush(pp);\n}\n\n/*\n * pflush - flag all process structures in the same job as the\n *\tthe argument process for deletion.  The actual free of the\n *\tspace is not done here since pflush is called at interrupt level.\n */\npflush(pp)\n\tregister struct process\t*pp;\n{\n\tregister struct process *np;\n\tregister int index;\n\n\tif (pp->p_pid == 0) {\n\t\tprintf(\"BUG: process flushed twice\");\n\t\treturn;\n\t}\n\twhile (pp->p_pid != pp->p_jobid)\n\t\tpp = pp->p_friends;\n\tpclrcurr(pp);\n\tif (pp == pcurrjob)\n\t\tpcurrjob = 0;\n\tindex = pp->p_index;\n\tnp = pp;\n\tdo {\n\t\tnp->p_index = np->p_pid = 0;\n\t\tnp->p_flags &= ~PNEEDNOTE;\n\t} while ((np = np->p_friends) != pp);\n\tif (index == pmaxindex) {\n\t\tfor (np = proclist.p_next, index = 0; np; np = np->p_next)\n\t\t\tif (np->p_index > index)\n\t\t\t\tindex = np->p_index;\n\t\tpmaxindex = index;\n\t}\n}\n\n/*\n * pclrcurr - make sure the given job is not the current or previous job;\n *\tpp MUST be the job leader\n */\npclrcurr(pp)\n\tregister struct process *pp;\n{\n\n\tif (pp == pcurrent)\n\t\tif (pprevious != PNULL) {\n\t\t\tpcurrent = pprevious;\n\t\t\tpprevious = pgetcurr(pp);\n\t\t} else {\n\t\t\tpcurrent = pgetcurr(pp);\n\t\t\tpprevious = pgetcurr(pp);\n\t\t}\n\telse if (pp == pprevious)\n\t\tpprevious = pgetcurr(pp);\n}\n\n/* +4 here is 1 for '\\0', 1 ea for << >& >> */\nchar\tcommand[PMAXLEN+4];\nint\tcmdlen;\nchar\t*cmdp;\n/*\n * palloc - allocate a process structure and fill it up.\n *\tan important assumption is made that the process is running.\n */\npalloc(pid, t)\n\tint pid;\n\tregister struct command *t;\n{\n\tregister struct process\t*pp;\n\tint i;\n\n\tpp = (struct process *)calloc(1, sizeof(struct process));\n\tpp->p_pid = pid;\n\tpp->p_flags = t->t_dflg & FAND ? PRUNNING : PRUNNING|PFOREGND;\n\tif (t->t_dflg & FTIME)\n\t\tpp->p_flags |= PPTIME;\n\tcmdp = command;\n\tcmdlen = 0;\n\tpadd(t);\n\t*cmdp++ = 0;\n\tif (t->t_dflg & FPOU) {\n\t\tpp->p_flags |= PPOU;\n\t\tif (t->t_dflg & FDIAG)\n\t\t\tpp->p_flags |= PDIAG;\n\t}\n\tpp->p_command = savestr(command);\n\tif (pcurrjob) {\n\t\tstruct process *fp;\n\t\t/* careful here with interrupt level */\n\t\tpp->p_cwd = 0;\n\t\tpp->p_index = pcurrjob->p_index;\n\t\tpp->p_friends = pcurrjob;\n\t\tpp->p_jobid = pcurrjob->p_pid;\n\t\tfor (fp = pcurrjob; fp->p_friends != pcurrjob; fp = fp->p_friends)\n\t\t\t;\n\t\tfp->p_friends = pp;\n\t} else {\n\t\tpcurrjob = pp;\n\t\tpp->p_jobid = pid;\n\t\tpp->p_friends = pp;\n\t\tpp->p_cwd = dcwd;\n\t\tdcwd->di_count++;\n\t\tif (pmaxindex < BIGINDEX)\n\t\t\tpp->p_index = ++pmaxindex;\n\t\telse {\n\t\t\tstruct process *np;\n\n\t\t\tfor (i = 1; ; i++) {\n\t\t\t\tfor (np = proclist.p_next; np; np = np->p_next)\n\t\t\t\t\tif (np->p_index == i)\n\t\t\t\t\t\tgoto tryagain;\n\t\t\t\tpp->p_index = i;\n\t\t\t\tif (i > pmaxindex)\n\t\t\t\t\tpmaxindex = i;\n\t\t\t\tbreak;\n\t\t\ttryagain:;\n\t\t\t}\n\t\t}\n\t\tif (pcurrent == PNULL)\n\t\t\tpcurrent = pp;\n\t\telse if (pprevious == PNULL)\n\t\t\tpprevious = pp;\n\t}\n\tpp->p_next = proclist.p_next;\n\tproclist.p_next = pp;\n\t(void) gettimeofday(&pp->p_btime, (struct timezone *)0);\n}\n\npadd(t)\n\tregister struct command *t;\n{\n\tchar **argp;\n\n\tif (t == 0)\n\t\treturn;\n\tswitch (t->t_dtyp) {\n\n\tcase TPAR:\n\t\tpads(\"( \");\n\t\tpadd(t->t_dspr);\n\t\tpads(\" )\");\n\t\tbreak;\n\n\tcase TCOM:\n\t\tfor (argp = t->t_dcom; *argp; argp++) {\n\t\t\tpads(*argp);\n\t\t\tif (argp[1])\n\t\t\t\tpads(\" \");\n\t\t}\n\t\tbreak;\n\n\tcase TOR:\n\tcase TAND:\n\tcase TFIL:\n\tcase TLST:\n\t\tpadd(t->t_dcar);\n\t\tswitch (t->t_dtyp) {\n\t\tcase TOR:\n\t\t\tpads(\" || \");\n\t\t\tbreak;\n\t\tcase TAND:\n\t\t\tpads(\" && \");\n\t\t\tbreak;\n\t\tcase TFIL:\n\t\t\tpads(\" | \");\n\t\t\tbreak;\n\t\tcase TLST:\n\t\t\tpads(\"; \");\n\t\t\tbreak;\n\t\t}\n\t\tpadd(t->t_dcdr);\n\t\treturn;\n\t}\n\tif ((t->t_dflg & FPIN) == 0 && t->t_dlef) {\n\t\tpads((t->t_dflg & FHERE) ? \" << \" : \" < \");\n\t\tpads(t->t_dlef);\n\t}\n\tif ((t->t_dflg & FPOU) == 0 && t->t_drit) {\n\t\tpads((t->t_dflg & FCAT) ? \" >>\" : \" >\");\n\t\tif (t->t_dflg & FDIAG)\n\t\t\tpads(\"&\");\n\t\tpads(\" \");\n\t\tpads(t->t_drit);\n\t}\n}\n\npads(cp)\n\tchar *cp;\n{\n\tregister int i = strlen(cp);\n\n\tif (cmdlen >= PMAXLEN)\n\t\treturn;\n\tif (cmdlen + i >= PMAXLEN) {\n\t\t(void) strcpy(cmdp, \" ...\");\n\t\tcmdlen = PMAXLEN;\n\t\tcmdp += 4;\n\t\treturn;\n\t}\n\t(void) strcpy(cmdp, cp);\n\tcmdp += i;\n\tcmdlen += i;\n}\n\n/*\n * psavejob - temporarily save the current job on a one level stack\n *\tso another job can be created.  Used for { } in exp6\n *\tand `` in globbing.\n */\npsavejob()\n{\n\n\tpholdjob = pcurrjob;\n\tpcurrjob = PNULL;\n}\n\n/*\n * prestjob - opposite of psavejob.  This may be missed if we are interrupted\n *\tsomewhere, but pendjob cleans up anyway.\n */\nprestjob()\n{\n\n\tpcurrjob = pholdjob;\n\tpholdjob = PNULL;\n}\n\n/*\n * pendjob - indicate that a job (set of commands) has been completed\n *\tor is about to begin.\n */\npendjob()\n{\n\tregister struct process *pp, *tp;\n\n\tif (pcurrjob && (pcurrjob->p_flags&(PFOREGND|PSTOPPED)) == 0) {\n\t\tpp = pcurrjob;\n\t\twhile (pp->p_pid != pp->p_jobid)\n\t\t\tpp = pp->p_friends;\n\t\tprintf(\"[%d]\", pp->p_index);\n\t\ttp = pp;\n\t\tdo {\n\t\t\tprintf(\" %d\", pp->p_pid);\n\t\t\tpp = pp->p_friends;\n\t\t} while (pp != tp);\n\t\tprintf(\"\\n\");\n\t}\n\tpholdjob = pcurrjob = 0;\n}\n\n/*\n * pprint - print a job\n */\npprint(pp, flag)\n\tregister struct process\t*pp;\n{\n\tregister status, reason;\n\tstruct process *tp;\n\textern char *linp, linbuf[];\n\tint jobflags, pstatus;\n\tchar *format;\n\n\twhile (pp->p_pid != pp->p_jobid)\n\t\tpp = pp->p_friends;\n\tif (pp == pp->p_friends && (pp->p_flags & PPTIME)) {\n\t\tpp->p_flags &= ~PPTIME;\n\t\tpp->p_flags |= PTIME;\n\t}\n\ttp = pp;\n\tstatus = reason = -1;\n\tjobflags = 0;\n\tdo {\n\t\tjobflags |= pp->p_flags;\n\t\tpstatus = pp->p_flags & PALLSTATES;\n\t\tif (tp != pp && linp != linbuf && !(flag&FANCY) &&\n\t\t    (pstatus == status && pp->p_reason == reason ||\n\t\t     !(flag&REASON)))\n\t\t\tprintf(\" \");\n\t\telse {\n\t\t\tif (tp != pp && linp != linbuf)\n\t\t\t\tprintf(\"\\n\");\n\t\t\tif(flag&NUMBER)\n\t\t\t\tif (pp == tp)\n\t\t\t\t\tprintf(\"[%d]%s %c \", pp->p_index,\n\t\t\t\t\t    pp->p_index < 10 ? \" \" : \"\",\n\t\t\t\t\t    pp==pcurrent ? '+' :\n\t\t\t\t\t\t(pp == pprevious ? '-' : ' '));\n\t\t\t\telse\n\t\t\t\t\tprintf(\"       \");\n\t\t\tif (flag&FANCY)\n\t\t\t\tprintf(\"%5d \", pp->p_pid);\n\t\t\tif (flag&(REASON|AREASON)) {\n\t\t\t\tif (flag&NAME)\n\t\t\t\t\tformat = \"%-21s\";\n\t\t\t\telse\n\t\t\t\t\tformat = \"%s\";\n\t\t\t\tif (pstatus == status)\n\t\t\t\t\tif (pp->p_reason == reason) {\n\t\t\t\t\t\tprintf(format, \"\");\n\t\t\t\t\t\tgoto prcomd;\n\t\t\t\t\t} else\n\t\t\t\t\t\treason = pp->p_reason;\n\t\t\t\telse {\n\t\t\t\t\tstatus = pstatus;\n\t\t\t\t\treason = pp->p_reason;\n\t\t\t\t}\n\t\t\t\tswitch (status) {\n\n\t\t\t\tcase PRUNNING:\n\t\t\t\t\tprintf(format, \"Running \");\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase PINTERRUPTED:\n\t\t\t\tcase PSTOPPED:\n\t\t\t\tcase PSIGNALED:\n\t\t\t\t\tif ((flag&(REASON|AREASON))\n\t\t\t\t\t    && reason != SIGINT\n\t\t\t\t\t    && reason != SIGPIPE)\n\t\t\t\t\t\tprintf(format, mesg[pp->p_reason].pname);\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase PNEXITED:\n\t\t\t\tcase PAEXITED:\n\t\t\t\t\tif (flag & REASON)\n\t\t\t\t\t\tif (pp->p_reason)\n\t\t\t\t\t\t\tprintf(\"Exit %-16d\", pp->p_reason);\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\tprintf(format, \"Done\");\n\t\t\t\t\tbreak;\n\n\t\t\t\tdefault:\n\t\t\t\t\tprintf(\"BUG: status=%-9o\", status);\n\t\t\t\t}\n\t\t\t}\n\t\t}\nprcomd:\n\t\tif (flag&NAME) {\n\t\t\tprintf(\"%s\", pp->p_command);\n\t\t\tif (pp->p_flags & PPOU)\n\t\t\t\tprintf(\" |\");\n\t\t\tif (pp->p_flags & PDIAG)\n\t\t\t\tprintf(\"&\");\n\t\t}\n\t\tif (flag&(REASON|AREASON) && pp->p_flags&PDUMPED)\n\t\t\tprintf(\" (core dumped)\");\n\t\tif (tp == pp->p_friends) {\n\t\t\tif (flag&AMPERSAND)\n\t\t\t\tprintf(\" &\");\n\t\t\tif (flag&JOBDIR &&\n\t\t\t    !eq(tp->p_cwd->di_name, dcwd->di_name)) {\n\t\t\t\tprintf(\" (wd: \");\n\t\t\t\tdtildepr(value(\"home\"), tp->p_cwd->di_name);\n\t\t\t\tprintf(\")\");\n\t\t\t}\n\t\t}\n\t\tif (pp->p_flags&PPTIME && !(status&(PSTOPPED|PRUNNING))) {\n\t\t\tif (linp != linbuf)\n\t\t\t\tprintf(\"\\n\\t\");\n\t\t\t{ static struct rusage zru;\n\t\t\t  prusage(&zru, &pp->p_rusage, &pp->p_etime,\n\t\t\t    &pp->p_btime);\n\t\t\t}\n\t\t}\n\t\tif (tp == pp->p_friends) {\n\t\t\tif (linp != linbuf)\n\t\t\t\tprintf(\"\\n\");\n\t\t\tif (flag&SHELLDIR && !eq(tp->p_cwd->di_name, dcwd->di_name)) {\n\t\t\t\tprintf(\"(wd now: \");\n\t\t\t\tdtildepr(value(\"home\"), dcwd->di_name);\n\t\t\t\tprintf(\")\\n\");\n\t\t\t}\n\t\t}\n\t} while ((pp = pp->p_friends) != tp);\n\tif (jobflags&PTIME && (jobflags&(PSTOPPED|PRUNNING)) == 0) {\n\t\tif (jobflags & NUMBER)\n\t\t\tprintf(\"       \");\n\t\tptprint(tp);\n\t}\n\treturn (jobflags);\n}\n\nptprint(tp)\n\tregister struct process *tp;\n{\n\tstruct timeval tetime, diff;\n\tstatic struct timeval ztime;\n\tstruct rusage ru;\n\tstatic struct rusage zru;\n\tregister struct process *pp = tp;\n\n\tru = zru;\n\ttetime = ztime;\n\tdo {\n\t\truadd(&ru, &pp->p_rusage);\n\t\ttvsub(&diff, &pp->p_etime, &pp->p_btime);\n\t\tif (timercmp(&diff, &tetime, >))\n\t\t\ttetime = diff;\n\t} while ((pp = pp->p_friends) != tp);\n\tprusage(&zru, &ru, &tetime, &ztime);\n}\n\n/*\n * dojobs - print all jobs\n */\ndojobs(v)\n\tchar **v;\n{\n\tregister struct process *pp;\n\tregister int flag = NUMBER|NAME|REASON;\n\tint i;\n\n\tif (chkstop)\n\t\tchkstop = 2;\n\tif (*++v) {\n\t\tif (v[1] || !eq(*v, \"-l\"))\n\t\t\terror(\"Usage: jobs [ -l ]\");\n\t\tflag |= FANCY|JOBDIR;\n\t}\n\tfor (i = 1; i <= pmaxindex; i++)\n\t\tfor (pp = proclist.p_next; pp; pp = pp->p_next)\n\t\t\tif (pp->p_index == i && pp->p_pid == pp->p_jobid) {\n\t\t\t\tpp->p_flags &= ~PNEEDNOTE;\n\t\t\t\tif (!(pprint(pp, flag) & (PRUNNING|PSTOPPED)))\n\t\t\t\t\tpflush(pp);\n\t\t\t\tbreak;\n\t\t\t}\n}\n\n/*\n * dofg - builtin - put the job into the foreground\n */\ndofg(v)\n\tchar **v;\n{\n\tregister struct process *pp;\n\n\tokpcntl();\n\t++v;\n\tdo {\n\t\tpp = pfind(*v);\n\t\tpstart(pp, 1);\n\t\tpjwait(pp);\n\t} while (*v && *++v);\n}\n\n/*\n * %... - builtin - put the job into the foreground\n */\ndofg1(v)\n\tchar **v;\n{\n\tregister struct process *pp;\n\n\tokpcntl();\n\tpp = pfind(v[0]);\n\tpstart(pp, 1);\n\tpjwait(pp);\n}\n\n/*\n * dobg - builtin - put the job into the background\n */\ndobg(v)\n\tchar **v;\n{\n\tregister struct process *pp;\n\n\tokpcntl();\n\t++v;\n\tdo {\n\t\tpp = pfind(*v);\n\t\tpstart(pp, 0);\n\t} while (*v && *++v);\n}\n\n/*\n * %... & - builtin - put the job into the background\n */\ndobg1(v)\n\tchar **v;\n{\n\tregister struct process *pp;\n\n\tpp = pfind(v[0]);\n\tpstart(pp, 0);\n}\n\n/*\n * dostop - builtin - stop the job\n */\ndostop(v)\n\tchar **v;\n{\n\n\tpkill(++v, SIGSTOP);\n}\n\n/*\n * dokill - builtin - superset of kill (1)\n */\ndokill(v)\n\tchar **v;\n{\n\tregister int signum;\n\tregister char *name;\n\n\tv++;\n\tif (v[0] && v[0][0] == '-') {\n\t\tif (v[0][1] == 'l') {\n\t\t\tfor (signum = 1; signum <= NSIG; signum++) {\n\t\t\t\tif (name = mesg[signum].iname)\n\t\t\t\t\tprintf(\"%s \", name);\n\t\t\t\tif (signum == 16)\n\t\t\t\t\tputchar('\\n');\n\t\t\t}\n\t\t\tputchar('\\n');\n\t\t\treturn;\n\t\t}\n\t\tif (digit(v[0][1])) {\n\t\t\tsignum = atoi(v[0]+1);\n\t\t\tif (signum < 0 || signum > NSIG)\n\t\t\t\tbferr(\"Bad signal number\");\n\t\t} else {\n\t\t\tname = &v[0][1];\n\t\t\tfor (signum = 1; signum <= NSIG; signum++)\n\t\t\tif (mesg[signum].iname &&\n\t\t\t    eq(name, mesg[signum].iname))\n\t\t\t\tgoto gotsig;\n\t\t\tsetname(name);\n\t\t\tbferr(\"Unknown signal; kill -l lists signals\");\n\t\t}\ngotsig:\n\t\tv++;\n\t} else\n\t\tsignum = SIGTERM;\n\tpkill(v, signum);\n}\n\npkill(v, signum)\n\tchar **v;\n\tint signum;\n{\n\tregister struct process *pp, *np;\n\tregister int jobflags = 0;\n\tint pid, parserr = 0;\n\tlong omask;\n\tchar *cp;\n\n\tomask = sigmask(SIGCHLD);\n\tif (setintr)\n\t\tomask |= sigmask(SIGINT);\n\tomask = sigblock(omask) & ~omask;\n\twhile (*v) {\n\t\tcp = globone(*v);\n\t\tif (*cp == '%') {\n\t\t\tnp = pp = pfind(cp);\n\t\t\tdo\n\t\t\t\tjobflags |= np->p_flags;\n\t\t\twhile ((np = np->p_friends) != pp);\n\t\t\tswitch (signum) {\n\n\t\t\tcase SIGSTOP:\n\t\t\tcase SIGTSTP:\n\t\t\tcase SIGTTIN:\n\t\t\tcase SIGTTOU:\n\t\t\t\tif ((jobflags & PRUNNING) == 0) {\n\t\t\t\t\tprintf(\"%s: Already stopped\\n\", cp);\n\t\t\t\t\tparserr++;\n\t\t\t\t\tgoto cont;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (killpg(pp->p_jobid, signum) < 0) {\n\t\t\t\tprintf(\"%s: \", cp);\n\t\t\t\tprintf(\"%s\\n\", strerror(errno));\n\t\t\t\tparserr++;\n\t\t\t}\n\t\t\tif (signum == SIGTERM || signum == SIGHUP)\n\t\t\t\t(void) killpg(pp->p_jobid, SIGCONT);\n\t\t} else if (!(digit(*cp) || *cp == '-'))\n\t\t\tbferr(\"Arguments should be jobs or process id's\");\n\t\telse {\n\t\t\tpid = atoi(cp);\n\t\t\tif (kill(pid, signum) < 0) {\n\t\t\t\tprintf(\"%d: \", pid);\n\t\t\t\tprintf(\"%s\\n\", strerror(errno));\n\t\t\t\tparserr++;\n\t\t\t\tgoto cont;\n\t\t\t}\n\t\t\tif (signum == SIGTERM || signum == SIGHUP)\n\t\t\t\t(void) kill(pid, SIGCONT);\n\t\t}\ncont:\n\t\txfree(cp);\n\t\tv++;\n\t}\n\t(void) sigsetmask(omask);\n\tif (parserr)\n\t\terror(NOSTR);\n}\n\n/*\n * pstart - start the job in foreground/background\n */\npstart(pp, foregnd)\n\tregister struct process *pp;\n\tint foregnd;\n{\n\tregister struct process *np;\n\tint jobflags = 0;\n\tlong omask;\n\n\tomask = sigblock(sigmask(SIGCHLD));\n\tnp = pp;\n\tdo {\n\t\tjobflags |= np->p_flags;\n\t\tif (np->p_flags&(PRUNNING|PSTOPPED)) {\n\t\t\tnp->p_flags |= PRUNNING;\n\t\t\tnp->p_flags &= ~PSTOPPED;\n\t\t\tif (foregnd)\n\t\t\t\tnp->p_flags |= PFOREGND;\n\t\t\telse\n\t\t\t\tnp->p_flags &= ~PFOREGND;\n\t\t}\n\t} while((np = np->p_friends) != pp);\n\tif (!foregnd)\n\t\tpclrcurr(pp);\n\t(void) pprint(pp, foregnd ? NAME|JOBDIR : NUMBER|NAME|AMPERSAND);\n\tif (foregnd)\n\t\t(void) ioctl(FSHTTY, TIOCSPGRP, (char *)&pp->p_jobid);\n\tif (jobflags&PSTOPPED)\n\t\t(void) killpg(pp->p_jobid, SIGCONT);\n\t(void) sigsetmask(omask);\n}\n\npanystop(neednl)\n{\n\tregister struct process *pp;\n\n\tchkstop = 2;\n\tfor (pp = proclist.p_next; pp; pp = pp->p_next)\n\t\tif (pp->p_flags & PSTOPPED)\n\t\t\terror(\"\\nThere are stopped jobs\" + 1 - neednl);\n}\n\nstruct process *\npfind(cp)\n\tchar *cp;\n{\n\tregister struct process *pp, *np;\n\n\tif (cp == 0 || cp[1] == 0 || eq(cp, \"%%\") || eq(cp, \"%+\")) {\n\t\tif (pcurrent == PNULL)\n\t\t\tbferr(\"No current job\");\n\t\treturn (pcurrent);\n\t}\n\tif (eq(cp, \"%-\") || eq(cp, \"%#\")) {\n\t\tif (pprevious == PNULL)\n\t\t\tbferr(\"No previous job\");\n\t\treturn (pprevious);\n\t}\n\tif (digit(cp[1])) {\n\t\tint index = atoi(cp+1);\n\t\tfor (pp = proclist.p_next; pp; pp = pp->p_next)\n\t\t\tif (pp->p_index == index && pp->p_pid == pp->p_jobid)\n\t\t\t\treturn (pp);\n\t\tbferr(\"No such job\");\n\t}\n\tnp = PNULL;\n\tfor (pp = proclist.p_next; pp; pp = pp->p_next)\n\t\tif (pp->p_pid == pp->p_jobid) {\n\t\t\tif (cp[1] == '?') {\n\t\t\t\tregister char *dp;\n\t\t\t\tfor (dp = pp->p_command; *dp; dp++) {\n\t\t\t\t\tif (*dp != cp[2])\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\tif (prefix(cp+2, dp))\n\t\t\t\t\t\tgoto match;\n\t\t\t\t}\n\t\t\t} else if (prefix(cp+1, pp->p_command)) {\nmatch:\n\t\t\t\tif (np)\n\t\t\t\t\tbferr(\"Ambiguous\");\n\t\t\t\tnp = pp;\n\t\t\t}\n\t\t}\n\tif (np)\n\t\treturn (np);\n\tif (cp[1] == '?')\n\t\tbferr(\"No job matches pattern\");\n\telse\n\t\tbferr(\"No such job\");\n\t/*NOTREACHED*/\n}\n\n/*\n * pgetcurr - find most recent job that is not pp, preferably stopped\n */\nstruct process *\npgetcurr(pp)\n\tregister struct process *pp;\n{\n\tregister struct process *np;\n\tregister struct process *xp = PNULL;\n\n\tfor (np = proclist.p_next; np; np = np->p_next)\n\t\tif (np != pcurrent && np != pp && np->p_pid &&\n\t\t    np->p_pid == np->p_jobid) {\n\t\t\tif (np->p_flags & PSTOPPED)\n\t\t\t\treturn (np);\n\t\t\tif (xp == PNULL)\n\t\t\t\txp = np;\n\t\t}\n\treturn (xp);\n}\n\n/*\n * donotify - flag the job so as to report termination asynchronously\n */\ndonotify(v)\n\tchar **v;\n{\n\tregister struct process *pp;\n\n\tpp = pfind(*++v);\n\tpp->p_flags |= PNOTIFY;\n}\n\n/*\n * Do the fork and whatever should be done in the child side that\n * should not be done if we are not forking at all (like for simple builtin's)\n * Also do everything that needs any signals fiddled with in the parent side\n *\n * Wanttty tells whether process and/or tty pgrps are to be manipulated:\n *\t-1:\tleave tty alone; inherit pgrp from parent\n *\t 0:\talready have tty; manipulate process pgrps only\n *\t 1:\twant to claim tty; manipulate process and tty pgrps\n * It is usually just the value of tpgrp.\n */\npfork(t, wanttty)\n\tstruct command *t;\t/* command we are forking for */\n\tint wanttty;\n{\n\tregister int pid;\n\tbool ignint = 0;\n\tint pgrp;\n\tlong omask;\n\n\t/*\n\t * A child will be uninterruptible only under very special\n\t * conditions. Remember that the semantics of '&' is\n\t * implemented by disconnecting the process from the tty so\n\t * signals do not need to ignored just for '&'.\n\t * Thus signals are set to default action for children unless:\n\t *\twe have had an \"onintr -\" (then specifically ignored)\n\t *\twe are not playing with signals (inherit action)\n\t */\n\tif (setintr)\n\t\tignint = (tpgrp == -1 && (t->t_dflg&FINT))\n\t\t    || (gointr && eq(gointr, \"-\"));\n\t/*\n\t * Hold SIGCHLD until we have the process installed in our table.\n\t */\n\tomask = sigblock(sigmask(SIGCHLD));\n\twhile ((pid = fork()) < 0)\n\t\tif (setintr == 0)\n\t\t\tsleep(FORKSLEEP);\n\t\telse {\n\t\t\t(void) sigsetmask(omask);\n\t\t\terror(\"No more processes\");\n\t\t}\n\tif (pid == 0) {\n\t\tsettimes();\n\t\tpgrp = pcurrjob ? pcurrjob->p_jobid : getpid();\n\t\tpflushall();\n\t\tpcurrjob = PNULL;\n\t\tchild++;\n\t\tif (setintr) {\n\t\t\tsetintr = 0;\t\t/* until I think otherwise */\n\t\t\t/*\n\t\t\t * Children just get blown away on SIGINT, SIGQUIT\n\t\t\t * unless \"onintr -\" seen.\n\t\t\t */\n\t\t\t(void) signal(SIGINT, ignint ? SIG_IGN : SIG_DFL);\n\t\t\t(void) signal(SIGQUIT, ignint ? SIG_IGN : SIG_DFL);\n\t\t\tif (wanttty >= 0) {\n\t\t\t\t/* make stoppable */\n\t\t\t\t(void) signal(SIGTSTP, SIG_DFL);\n\t\t\t\t(void) signal(SIGTTIN, SIG_DFL);\n\t\t\t\t(void) signal(SIGTTOU, SIG_DFL);\n\t\t\t}\n\t\t\t(void) signal(SIGTERM, parterm);\n\t\t} else if (tpgrp == -1 && (t->t_dflg&FINT)) {\n\t\t\t(void) signal(SIGINT, SIG_IGN);\n\t\t\t(void) signal(SIGQUIT, SIG_IGN);\n\t\t}\n\t\tif (wanttty > 0)\n\t\t\t(void) ioctl(FSHTTY, TIOCSPGRP, (char *)&pgrp);\n\t\tif (wanttty >= 0 && tpgrp >= 0)\n\t\t\t(void) setpgrp(0, pgrp);\n\t\tif (tpgrp > 0)\n\t\t\ttpgrp = 0;\t\t/* gave tty away */\n\t\t/*\n\t\t * Nohup and nice apply only to TCOM's but it would be\n\t\t * nice (?!?) if you could say \"nohup (foo;bar)\"\n\t\t * Then the parser would have to know about nice/nohup/time\n\t\t */\n\t\tif (t->t_dflg & FNOHUP)\n\t\t\t(void) signal(SIGHUP, SIG_IGN);\n\t\tif (t->t_dflg & FNICE)\n\t\t\t(void) setpriority(PRIO_PROCESS, 0, t->t_nice);\n\t} else {\n\t\tpalloc(pid, t);\n\t\t(void) sigsetmask(omask);\n\t}\n\n\treturn (pid);\n}\n\nokpcntl()\n{\n\n\tif (tpgrp == -1)\n\t\terror(\"No job control in this shell\");\n\tif (tpgrp == 0)\n\t\terror(\"No job control in subshells\");\n}\n"
  },
  {
    "path": "bin/csh/sh.proc.h",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)sh.proc.h\t5.2 (Berkeley) 6/6/85\n */\n\n/*\n * C shell - process structure declarations\n */\n\n/*\n * Structure for each process the shell knows about:\n *\tallocated and filled by pcreate.\n *\tflushed by pflush; freeing always happens at top level\n *\t    so the interrupt level has less to worry about.\n *\tprocesses are related to \"friends\" when in a pipeline;\n *\t    p_friends links makes a circular list of such jobs\n */\nstruct process\t{\n\tstruct\tprocess *p_next;\t/* next in global \"proclist\" */\n\tstruct\tprocess\t*p_friends;\t/* next in job list (or self) */\n\tstruct\tdirectory *p_cwd;\t/* cwd of the job (only in head) */\n\tshort\tunsigned p_flags;\t/* various job status flags */\n\tchar\tp_reason;\t\t/* reason for entering this state */\n\tchar\tp_index;\t\t/* shorthand job index */\n\tint\tp_pid;\n\tint\tp_jobid;\t\t/* pid of job leader */\n\t/* if a job is stopped/background p_jobid gives its pgrp */\n\tstruct\ttimeval p_btime;\t/* begin time */\n\tstruct\ttimeval p_etime;\t/* end time */\n\tstruct\trusage p_rusage;\n\tchar\t*p_command;\t\t/* first PMAXLEN chars of command */\n};\n\n/* flag values for p_flags */\n#define\tPRUNNING\t(1<<0)\t\t/* running */\n#define\tPSTOPPED\t(1<<1)\t\t/* stopped */\n#define\tPNEXITED\t(1<<2)\t\t/* normally exited */\n#define\tPAEXITED\t(1<<3)\t\t/* abnormally exited */\n#define\tPSIGNALED\t(1<<4)\t\t/* terminated by a signal != SIGINT */\n\n#define\tPALLSTATES\t(PRUNNING|PSTOPPED|PNEXITED|PAEXITED|PSIGNALED|PINTERRUPTED)\n#define\tPNOTIFY\t\t(1<<5)\t\t/* notify async when done */\n#define\tPTIME\t\t(1<<6)\t\t/* job times should be printed */\n#define\tPAWAITED\t(1<<7)\t\t/* top level is waiting for it */\n#define\tPFOREGND\t(1<<8)\t\t/* started in shells pgrp */\n#define\tPDUMPED\t\t(1<<9)\t\t/* process dumped core */\n#define\tPDIAG\t\t(1<<10)\t\t/* diagnostic output also piped out */\n#define\tPPOU\t\t(1<<11)\t\t/* piped output */\n#define\tPREPORTED\t(1<<12)\t\t/* status has been reported */\n#define\tPINTERRUPTED\t(1<<13)\t\t/* job stopped via interrupt signal */\n#define\tPPTIME\t\t(1<<14)\t\t/* time individual process */\n#define\tPNEEDNOTE\t(1<<15)\t\t/* notify as soon as practical */\n\n#define\tPNULL\t\t(struct process *)0\n#define\tPMAXLEN\t\t80\n\n/* defines for arguments to pprint */\n#define\tNUMBER\t\t01\n#define\tNAME\t\t02\n#define\tREASON\t\t04\n#define\tAMPERSAND\t010\n#define\tFANCY\t\t020\n#define\tSHELLDIR\t040\t\t/* print shell's dir if not the same */\n#define\tJOBDIR\t\t0100\t\t/* print job's dir if not the same */\n#define\tAREASON\t\t0200\n\nstruct\tprocess\tproclist;\t\t/* list head of all processes */\nbool\tpnoprocesses;\t\t\t/* pchild found nothing to wait for */\n\nstruct\tprocess *pholdjob;\t\t/* one level stack of current jobs */\n\nstruct\tprocess *pcurrjob;\t\t/* current job */\nstruct\tprocess\t*pcurrent;\t\t/* current job in table */\nstruct\tprocess *pprevious;\t\t/* previous job in table */\n\nshort\tpmaxindex;\t\t\t/* current maximum job index */\n\nint\tpsigint();\nstruct\tprocess\t*pgetcurr();\nstruct\tprocess\t*plookup();\nstruct\tprocess *pfind();\n"
  },
  {
    "path": "bin/csh/sh.sem.c",
    "content": "/*\n * C shell\n *\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"sh.h\"\n#include \"sh.proc.h\"\n#include <fcntl.h>\n#include <sys/ioctl.h>\n\n#ifdef VFORK\nvoid vffree(int sig)\n{\n\tregister char **v;\n\n\tif (v = gargv)\n\t\tgargv = 0, blkfree(v);\n\tif (v = pargv)\n\t\tpargv = 0, blkfree(v);\n\t_exit(1);\n}\n#endif\n\n/*VARARGS 1*/\nexecute(t, wanttty, pipein, pipeout)\n\tregister struct command *t;\n\tint wanttty, *pipein, *pipeout;\n{\n\tbool forked = 0;\n\tstruct biltins *bifunc;\n\tint pid = 0;\n\tint pv[2];\n\n\tif (t == 0)\n\t\treturn;\n\tif ((t->t_dflg & FAND) && wanttty > 0)\n\t\twanttty = 0;\n\tswitch (t->t_dtyp) {\n\n\tcase TCOM:\n\t\tif ((t->t_dcom[0][0] & (QUOTE|TRIM)) == QUOTE)\n\t\t\t(void) strcpy(t->t_dcom[0], t->t_dcom[0] + 1);\n\t\tif ((t->t_dflg & FREDO) == 0)\n\t\t\tDfix(t);\t\t/* $ \" ' \\ */\n\t\tif (t->t_dcom[0] == 0)\n\t\t\treturn;\n\t\t/* fall into... */\n\n\tcase TPAR:\n\t\tif (t->t_dflg & FPOU)\n\t\t\tmypipe(pipeout);\n\t\t/*\n\t\t * Must do << early so parent will know\n\t\t * where input pointer should be.\n\t\t * If noexec then this is all we do.\n\t\t */\n\t\tif (t->t_dflg & FHERE) {\n\t\t\t(void) close(0);\n\t\t\theredoc(t->t_dlef);\n\t\t\tif (noexec)\n\t\t\t\t(void) close(0);\n\t\t}\n\t\tif (noexec)\n\t\t\tbreak;\n\n\t\tset(\"status\", \"0\");\n\n\t\t/*\n\t\t * This mess is the necessary kludge to handle the prefix\n\t\t * builtins: nice, nohup, time.  These commands can also\n\t\t * be used by themselves, and this is not handled here.\n\t\t * This will also work when loops are parsed.\n\t\t */\n\t\twhile (t->t_dtyp == TCOM)\n\t\t\tif (eq(t->t_dcom[0], \"nice\"))\n\t\t\t\tif (t->t_dcom[1])\n\t\t\t\t\tif (any(t->t_dcom[1][0], \"+-\"))\n\t\t\t\t\t\tif (t->t_dcom[2]) {\n\t\t\t\t\t\t\tsetname(\"nice\");\n\t\t\t\t\t\t\tt->t_nice = getn(t->t_dcom[1]);\n\t\t\t\t\t\t\tlshift(t->t_dcom, 2);\n\t\t\t\t\t\t\tt->t_dflg |= FNICE;\n\t\t\t\t\t\t} else\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\telse {\n\t\t\t\t\t\tt->t_nice = 4;\n\t\t\t\t\t\tlshift(t->t_dcom, 1);\n\t\t\t\t\t\tt->t_dflg |= FNICE;\n\t\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t\tbreak;\n\t\t\telse if (eq(t->t_dcom[0], \"nohup\"))\n\t\t\t\tif (t->t_dcom[1]) {\n\t\t\t\t\tt->t_dflg |= FNOHUP;\n\t\t\t\t\tlshift(t->t_dcom, 1);\n\t\t\t\t} else\n\t\t\t\t\tbreak;\n\t\t\telse if (eq(t->t_dcom[0], \"time\"))\n\t\t\t\tif (t->t_dcom[1]) {\n\t\t\t\t\tt->t_dflg |= FTIME;\n\t\t\t\t\tlshift(t->t_dcom, 1);\n\t\t\t\t} else\n\t\t\t\t\tbreak;\n\t\t\telse\n\t\t\t\tbreak;\n\t\t/*\n\t\t * Check if we have a builtin function and remember which one.\n\t\t */\n\t\tbifunc = t->t_dtyp == TCOM ? isbfunc(t) : (struct biltins *) 0;\n\n\t\t/*\n\t\t * We fork only if we are timed, or are not the end of\n\t\t * a parenthesized list and not a simple builtin function.\n\t\t * Simple meaning one that is not pipedout, niced, nohupped,\n\t\t * or &'d.\n\t\t * It would be nice(?) to not fork in some of these cases.\n\t\t */\n\t\tif (((t->t_dflg & FTIME) || (t->t_dflg & FPAR) == 0 &&\n\t\t     (!bifunc || t->t_dflg & (FPOU|FAND|FNICE|FNOHUP))))\n#ifdef VFORK\n\t\t    if (t->t_dtyp == TPAR || t->t_dflg&(FREDO|FAND) || bifunc)\n#endif\n\t\t\t{ forked++; pid = pfork(t, wanttty); }\n#ifdef VFORK\n\t\t    else {\n\t\t\tint ochild, osetintr, ohaderr, odidfds;\n\t\t\tint oSHIN, oSHOUT, oSHDIAG, oOLDSTD, otpgrp;\n\t\t\tlong omask;\n\n\t\t\t/*\n\t\t\t * Prepare for the vfork by saving everything\n\t\t\t * that the child corrupts before it exec's.\n\t\t\t * Note that in some signal implementations\n\t\t\t * which keep the signal info in user space\n\t\t\t * (e.g. Sun's) it will also be necessary to\n \t\t\t * save and restore the current sigvec's for\n\t\t\t * the signals the child touches before it\n\t\t\t * exec's.\n\t\t\t */\n\t\t\tomask = sigblock(sigmask(SIGCHLD));\n\t\t\tochild = child; osetintr = setintr;\n\t\t\tohaderr = haderr; odidfds = didfds;\n\t\t\toSHIN = SHIN; oSHOUT = SHOUT;\n\t\t\toSHDIAG = SHDIAG; oOLDSTD = OLDSTD; otpgrp = tpgrp;\n\t\t\tVsav = Vdp = 0; Vav = 0;\n\t\t\tpid = vfork();\n\t\t\tif (pid < 0) {\n\t\t\t\t(void) sigsetmask(omask);\n\t\t\t\terror(\"No more processes\");\n\t\t\t}\n\t\t\tforked++;\n\t\t\tif (pid) {\t/* parent */\n\t\t\t\tregister char **v;\n\n\t\t\t\tchild = ochild; setintr = osetintr;\n\t\t\t\thaderr = ohaderr; didfds = odidfds;\n\t\t\t\tSHIN = oSHIN;\n\t\t\t\tSHOUT = oSHOUT; SHDIAG = oSHDIAG;\n\t\t\t\tOLDSTD = oOLDSTD; tpgrp = otpgrp;\n\t\t\t\txfree(Vsav); Vsav = 0;\n\t\t\t\txfree(Vdp); Vdp = 0;\n\t\t\t\txfree((char *)Vav); Vav = 0;\n\t\t\t\tif (v = gargv)\n\t\t\t\t\tgargv = 0, blkfree(v);\n\t\t\t\tif (v = pargv)\n\t\t\t\t\tpargv = 0, blkfree(v);\n\t\t\t\t/* this is from pfork() */\n\t\t\t\tpalloc(pid, t);\n\t\t\t\t(void) sigsetmask(omask);\n\t\t\t} else {\t/* child */\n\t\t\t\t/* this is from pfork() */\n\t\t\t\tint pgrp;\n\t\t\t\tbool ignint = 0;\n\n\t\t\t\tif (setintr)\n\t\t\t\t\tignint =\n\t\t\t\t\t    (tpgrp == -1 && (t->t_dflg&FINT))\n\t\t\t\t\t    || gointr && eq(gointr, \"-\");\n\t\t\t\tpgrp = pcurrjob ? pcurrjob->p_jobid : getpid();\n\t\t\t\tchild++;\n\t\t\t\tif (setintr) {\n\t\t\t\t\tsetintr = 0;\n#ifdef notdef\n\t\t\t\t\t(void) signal(SIGCHLD, SIG_DFL);\n#endif\n\t\t\t\t\t(void) signal(SIGINT, ignint ?\n\t\t\t\t\t\tSIG_IGN : vffree);\n\t\t\t\t\t(void) signal(SIGQUIT, ignint ?\n\t\t\t\t\t\tSIG_IGN : SIG_DFL);\n\t\t\t\t\tif (wanttty >= 0) {\n\t\t\t\t\t\t(void) signal(SIGTSTP, SIG_DFL);\n\t\t\t\t\t\t(void) signal(SIGTTIN, SIG_DFL);\n\t\t\t\t\t\t(void) signal(SIGTTOU, SIG_DFL);\n\t\t\t\t\t}\n\t\t\t\t\t(void) signal(SIGTERM, parterm);\n\t\t\t\t} else if (tpgrp == -1 && (t->t_dflg&FINT)) {\n\t\t\t\t\t(void) signal(SIGINT, SIG_IGN);\n\t\t\t\t\t(void) signal(SIGQUIT, SIG_IGN);\n\t\t\t\t}\n\t\t\t\tif (wanttty > 0)\n\t\t\t\t\t(void) ioctl(FSHTTY, TIOCSPGRP,\n\t\t\t\t\t\t(char *)&pgrp);\n\t\t\t\tif (wanttty >= 0 && tpgrp >= 0)\n\t\t\t\t\t(void) setpgrp(0, pgrp);\n\t\t\t\tif (tpgrp > 0)\n\t\t\t\t\ttpgrp = 0;\n\t\t\t\tif (t->t_dflg & FNOHUP)\n\t\t\t\t\t(void) signal(SIGHUP, SIG_IGN);\n\t\t\t\tif (t->t_dflg & FNICE)\n\t\t\t\t\t(void) setpriority(PRIO_PROCESS,\n\t\t\t\t\t\t0, t->t_nice);\n\t\t\t}\n\n\t\t    }\n#endif\n\t\tif (pid != 0) {\n\t\t\t/*\n\t\t\t * It would be better if we could wait for the\n\t\t\t * whole job when we knew the last process\n\t\t\t * had been started.  Pwait, in fact, does\n\t\t\t * wait for the whole job anyway, but this test\n\t\t\t * doesn't really express our intentions.\n\t\t\t */\n\t\t\tif (didfds==0 && t->t_dflg&FPIN) {\n\t\t\t\t(void) close(pipein[0]);\n\t\t\t\t(void) close(pipein[1]);\n\t\t\t}\n\t\t\tif ((t->t_dflg & (FPOU|FAND)) == 0)\n\t\t\t\tpwait();\n\t\t\tbreak;\n\t\t}\n\t\tdoio(t, pipein, pipeout);\n\t\tif (t->t_dflg & FPOU) {\n\t\t\t(void) close(pipeout[0]);\n\t\t\t(void) close(pipeout[1]);\n\t\t}\n\n\t\t/*\n\t\t * Perform a builtin function.\n\t\t * If we are not forked, arrange for possible stopping\n\t\t */\n\t\tif (bifunc) {\n\t\t\tfunc(t, bifunc);\n\t\t\tif (forked)\n\t\t\t\texitstat();\n\t\t\tbreak;\n\t\t}\n\t\tif (t->t_dtyp != TPAR) {\n\t\t\tdoexec(t);\n\t\t\t/*NOTREACHED*/\n\t\t}\n\t\t/*\n\t\t * For () commands must put new 0,1,2 in FSH* and recurse\n\t\t */\n\t\tOLDSTD = dcopy(0, FOLDSTD);\n\t\tSHOUT = dcopy(1, FSHOUT);\n\t\tSHDIAG = dcopy(2, FSHDIAG);\n\t\t(void) close(SHIN);\n\t\tSHIN = -1;\n\t\tdidfds = 0;\n\t\twanttty = -1;\n\t\tt->t_dspr->t_dflg |= t->t_dflg & FINT;\n\t\texecute(t->t_dspr, wanttty);\n\t\texitstat();\n\n\tcase TFIL:\n\t\tt->t_dcar->t_dflg |= FPOU |\n\t\t    (t->t_dflg & (FPIN|FAND|FDIAG|FINT));\n\t\texecute(t->t_dcar, wanttty, pipein, pv);\n\t\tt->t_dcdr->t_dflg |= FPIN |\n\t\t    (t->t_dflg & (FPOU|FAND|FPAR|FINT));\n\t\tif (wanttty > 0)\n\t\t\twanttty = 0;\t\t/* got tty already */\n\t\texecute(t->t_dcdr, wanttty, pv, pipeout);\n\t\tbreak;\n\n\tcase TLST:\n\t\tif (t->t_dcar) {\n\t\t\tt->t_dcar->t_dflg |= t->t_dflg & FINT;\n\t\t\texecute(t->t_dcar, wanttty);\n\t\t\t/*\n\t\t\t * In strange case of A&B make a new job after A\n\t\t\t */\n\t\t\tif (t->t_dcar->t_dflg&FAND && t->t_dcdr &&\n\t\t\t    (t->t_dcdr->t_dflg&FAND) == 0)\n\t\t\t\tpendjob();\n\t\t}\n\t\tif (t->t_dcdr) {\n\t\t\tt->t_dcdr->t_dflg |= t->t_dflg & (FPAR|FINT);\n\t\t\texecute(t->t_dcdr, wanttty);\n\t\t}\n\t\tbreak;\n\n\tcase TOR:\n\tcase TAND:\n\t\tif (t->t_dcar) {\n\t\t\tt->t_dcar->t_dflg |= t->t_dflg & FINT;\n\t\t\texecute(t->t_dcar, wanttty);\n\t\t\tif ((getn(value(\"status\")) == 0) != (t->t_dtyp == TAND))\n\t\t\t\treturn;\n\t\t}\n\t\tif (t->t_dcdr) {\n\t\t\tt->t_dcdr->t_dflg |= t->t_dflg & (FPAR|FINT);\n\t\t\texecute(t->t_dcdr, wanttty);\n\t\t}\n\t\tbreak;\n\t}\n\t/*\n\t * Fall through for all breaks from switch\n\t *\n\t * If there will be no more executions of this\n\t * command, flush all file descriptors.\n\t * Places that turn on the FREDO bit are responsible\n\t * for doing donefds after the last re-execution\n\t */\n\tif (didfds && !(t->t_dflg & FREDO))\n\t\tdonefds();\n}\n\n/*\n * Perform io redirection.\n * We may or maynot be forked here.\n */\ndoio(t, pipein, pipeout)\n\tregister struct command *t;\n\tint *pipein, *pipeout;\n{\n\tregister char *cp;\n\tregister int flags = t->t_dflg;\n\n\tif (didfds || (flags & FREDO))\n\t\treturn;\n\tif ((flags & FHERE) == 0) {\t/* FHERE already done */\n\t\t(void) close(0);\n\t\tif (cp = t->t_dlef) {\n\t\t\tcp = globone(Dfix1(cp));\n\t\t\txfree(cp);\n\t\t\tif (open(cp, 0) < 0)\n\t\t\t\tPerror(cp);\n\t\t} else if (flags & FPIN) {\n\t\t\t(void) dup(pipein[0]);\n\t\t\t(void) close(pipein[0]);\n\t\t\t(void) close(pipein[1]);\n\t\t} else if ((flags & FINT) && tpgrp == -1) {\n\t\t\t(void) close(0);\n\t\t\t(void) open(\"/dev/null\", 0);\n\t\t} else\n\t\t\t(void) dup(OLDSTD);\n\t}\n\t(void) close(1);\n\tif (cp = t->t_drit) {\n\t\tcp = globone(Dfix1(cp));\n\t\txfree(cp);\n\t\tif ((flags & FCAT) && open(cp, O_WRONLY | O_APPEND) >= 0)\n\t\t\t;\n\t\telse {\n\t\t\tif (!(flags & FANY) && adrof(\"noclobber\")) {\n\t\t\t\tif (flags & FCAT)\n\t\t\t\t\tPerror(cp);\n\t\t\t\tchkclob(cp);\n\t\t\t}\n\t\t\tif (creat(cp, 0666) < 0)\n\t\t\t\tPerror(cp);\n\t\t}\n\t} else if (flags & FPOU)\n\t\t(void) dup(pipeout[1]);\n\telse\n\t\t(void) dup(SHOUT);\n\n\t(void) close(2);\n\tif (flags & FDIAG)\n\t\t(void) dup(1);\n\telse\n\t\t(void) dup(SHDIAG);\n\tdidfds = 1;\n}\n\nmypipe(pv)\n\tregister int *pv;\n{\n\n\tif (pipe(pv) < 0)\n\t\tgoto oops;\n\tpv[0] = dmove(pv[0], -1);\n\tpv[1] = dmove(pv[1], -1);\n\tif (pv[0] >= 0 && pv[1] >= 0)\n\t\treturn;\noops:\n\terror(\"Can't make pipe\");\n}\n\nchkclob(cp)\n\tregister char *cp;\n{\n\tstruct stat stb;\n\n\tif (stat(cp, &stb) < 0)\n\t\treturn;\n\tif ((stb.st_mode & S_IFMT) == S_IFCHR)\n\t\treturn;\n\terror(\"%s: File exists\", cp);\n}\n"
  },
  {
    "path": "bin/csh/sh.set.c",
    "content": "/*\n * C Shell\n *\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"sh.h\"\n\ndoset(v)\n\tregister char **v;\n{\n\tregister char *p;\n\tchar *vp, op;\n\tchar **vecp;\n\tbool hadsub;\n\tint subscr;\n\n\tv++;\n\tp = *v++;\n\tif (p == 0) {\n\t\tprvars();\n\t\treturn;\n\t}\n\tdo {\n\t\thadsub = 0;\n\t\tfor (vp = p; alnum(*p); p++)\n\t\t\tcontinue;\n\t\tif (vp == p || !letter(*vp))\n\t\t\tgoto setsyn;\n\t\tif (*p == '[') {\n\t\t\thadsub++;\n\t\t\tp = getinx(p, &subscr);\n\t\t}\n\t\tif (op = *p) {\n\t\t\t*p++ = 0;\n\t\t\tif (*p == 0 && *v && **v == '(')\n\t\t\t\tp = *v++;\n\t\t} else if (*v && eq(*v, \"=\")) {\n\t\t\top = '=', v++;\n\t\t\tif (*v)\n\t\t\t\tp = *v++;\n\t\t}\n\t\tif (op && op != '=')\nsetsyn:\n\t\t\tbferr(\"Syntax error\");\n\t\tif (eq(p, \"(\")) {\n\t\t\tregister char **e = v;\n\n\t\t\tif (hadsub)\n\t\t\t\tgoto setsyn;\n\t\t\tfor (;;) {\n\t\t\t\tif (!*e)\n\t\t\t\t\tbferr(\"Missing )\");\n\t\t\t\tif (**e == ')')\n\t\t\t\t\tbreak;\n\t\t\t\te++;\n\t\t\t}\n\t\t\tp = *e;\n\t\t\t*e = 0;\n\t\t\tvecp = saveblk(v);\n\t\t\tset1(vp, vecp, &shvhed);\n\t\t\t*e = p;\n\t\t\tv = e + 1;\n\t\t} else if (hadsub)\n\t\t\tasx(vp, subscr, savestr(p));\n\t\telse\n\t\t\tset(vp, savestr(p));\n\t\tif (eq(vp, \"path\")) {\n\t\t\texportpath(adrof(\"path\")->vec);\n\t\t\tdohash();\n\t\t} else if (eq(vp, \"histchars\")) {\n\t\t\tregister char *p = value(\"histchars\");\n\n\t\t\tHIST = *p++;\n\t\t\tHISTSUB = *p;\n\t\t} else if (eq(vp, \"user\"))\n\t\t\tsetenvv(\"USER\", value(vp));\n\t\telse if (eq(vp, \"term\"))\n\t\t\tsetenvv(\"TERM\", value(vp));\n\t\telse if (eq(vp, \"home\"))\n\t\t\tsetenvv(\"HOME\", value(vp));\n#ifdef FILEC\n\t\telse if (eq(vp, \"filec\"))\n\t\t\tfilec = 1;\n#endif\n\t} while (p = *v++);\n}\n\nchar *\ngetinx(cp, ip)\n\tregister char *cp;\n\tregister int *ip;\n{\n\t*ip = 0;\n\t*cp++ = 0;\n\twhile (*cp && digit(*cp))\n\t\t*ip = *ip * 10 + *cp++ - '0';\n\tif (*cp++ != ']')\n\t\tbferr(\"Subscript error\");\n\treturn (cp);\n}\n\nasx(vp, subscr, p)\n\tchar *vp;\n\tint subscr;\n\tchar *p;\n{\n\tregister struct varent *v = getvx(vp, subscr);\n\n\txfree(v->vec[subscr - 1]);\n\tv->vec[subscr - 1] = globone(p);\n}\n\nstruct varent *\ngetvx(vp, subscr)\n\tchar *vp;\n{\n\tregister struct varent *v = adrof(vp);\n\n\tif (v == 0)\n\t\tudvar(vp);\n\tif (subscr < 1 || subscr > blklen(v->vec))\n\t\tbferr(\"Subscript out of range\");\n\treturn (v);\n}\n\nchar\tplusplus[2] = { '1', 0 };\n\ndolet(v)\n\tchar **v;\n{\n\tregister char *p;\n\tchar *vp, c, op;\n\tbool hadsub;\n\tint subscr;\n\n\tv++;\n\tp = *v++;\n\tif (p == 0) {\n\t\tprvars();\n\t\treturn;\n\t}\n\tdo {\n\t\thadsub = 0;\n\t\tfor (vp = p; alnum(*p); p++)\n\t\t\tcontinue;\n\t\tif (vp == p || !letter(*vp))\n\t\t\tgoto letsyn;\n\t\tif (*p == '[') {\n\t\t\thadsub++;\n\t\t\tp = getinx(p, &subscr);\n\t\t}\n\t\tif (*p == 0 && *v)\n\t\t\tp = *v++;\n\t\tif (op = *p)\n\t\t\t*p++ = 0;\n\t\telse\n\t\t\tgoto letsyn;\n\t\tvp = savestr(vp);\n\t\tif (op == '=') {\n\t\t\tc = '=';\n\t\t\tp = xset(p, &v);\n\t\t} else {\n\t\t\tc = *p++;\n\t\t\tif (any(c, \"+-\")) {\n\t\t\t\tif (c != op || *p)\n\t\t\t\t\tgoto letsyn;\n\t\t\t\tp = plusplus;\n\t\t\t} else {\n\t\t\t\tif (any(op, \"<>\")) {\n\t\t\t\t\tif (c != op)\n\t\t\t\t\t\tgoto letsyn;\n\t\t\t\t\tc = *p++;\nletsyn:\n\t\t\t\t\tbferr(\"Syntax error\");\n\t\t\t\t}\n\t\t\t\tif (c != '=')\n\t\t\t\t\tgoto letsyn;\n\t\t\t\tp = xset(p, &v);\n\t\t\t}\n\t\t}\n\t\tif (op == '=')\n\t\t\tif (hadsub)\n\t\t\t\tasx(vp, subscr, p);\n\t\t\telse\n\t\t\t\tset(vp, p);\n\t\telse\n\t\t\tif (hadsub)\n#ifndef V6\n\t\t\t\t/* avoid bug in vax CC */\n\t\t\t\t{\n\t\t\t\t\tstruct varent *gv = getvx(vp, subscr);\n\n\t\t\t\t\tasx(vp, subscr, operate(op, gv->vec[subscr - 1], p));\n\t\t\t\t}\n#else\n\t\t\t\tasx(vp, subscr, operate(op, getvx(vp, subscr)->vec[subscr - 1], p));\n#endif\n\t\t\telse\n\t\t\t\tset(vp, operate(op, value(vp), p));\n\t\tif (eq(vp, \"path\")) {\n\t\t\texportpath(adrof(\"path\")->vec);\n\t\t\tdohash();\n\t\t}\n\t\tXFREE(vp)\n\t\tif (c != '=')\n\t\t\tXFREE(p)\n\t} while (p = *v++);\n}\n\nchar *\nxset(cp, vp)\n\tchar *cp, ***vp;\n{\n\tregister char *dp;\n\n\tif (*cp) {\n\t\tdp = savestr(cp);\n\t\t--(*vp);\n\t\txfree(**vp);\n\t\t**vp = dp;\n\t}\n\treturn (putn(expr(vp)));\n}\n\nchar *\noperate(op, vp, p)\n\tchar op, *vp, *p;\n{\n\tchar opr[2];\n\tchar *vec[5];\n\tregister char **v = vec;\n\tchar **vecp = v;\n\tregister int i;\n\n\tif (op != '=') {\n\t\tif (*vp)\n\t\t\t*v++ = vp;\n\t\topr[0] = op;\n\t\topr[1] = 0;\n\t\t*v++ = opr;\n\t\tif (op == '<' || op == '>')\n\t\t\t*v++ = opr;\n\t}\n\t*v++ = p;\n\t*v++ = 0;\n\ti = expr(&vecp);\n\tif (*vecp)\n\t\tbferr(\"Expression syntax\");\n\treturn (putn(i));\n}\n\nstatic\tchar *putp;\n\nchar *\nputn(n)\n\tregister int n;\n{\n\tstatic char number[15];\n\n\tputp = number;\n\tif (n < 0) {\n\t\tn = -n;\n\t\t*putp++ = '-';\n\t}\n\tif (sizeof (int) == 2 && n == -32768) {\n\t\t*putp++ = '3';\n\t\tn = 2768;\n#ifndef pdp11\n\t} else if (sizeof (int) == 4 && n == -2147483648U) {\n\t\t*putp++ = '2';\n\t\tn = 147483648;\n#endif\n\t}\n\tputn1(n);\n\t*putp = 0;\n\treturn (savestr(number));\n}\n\nputn1(n)\n\tregister int n;\n{\n\tif (n > 9)\n\t\tputn1(n / 10);\n\t*putp++ = n % 10 + '0';\n}\n\ngetn(cp)\n\tregister char *cp;\n{\n\tregister int n;\n\tint sign;\n\n\tsign = 0;\n\tif (cp[0] == '+' && cp[1])\n\t\tcp++;\n\tif (*cp == '-') {\n\t\tsign++;\n\t\tcp++;\n\t\tif (!digit(*cp))\n\t\t\tgoto badnum;\n\t}\n\tn = 0;\n\twhile (digit(*cp))\n\t\tn = n * 10 + *cp++ - '0';\n\tif (*cp)\n\t\tgoto badnum;\n\treturn (sign ? -n : n);\nbadnum:\n\tbferr(\"Badly formed number\");\n\treturn (0);\n}\n\nchar *\nvalue1(var, head)\n\tchar *var;\n\tstruct varent *head;\n{\n\tregister struct varent *vp;\n\n\tvp = adrof1(var, head);\n\treturn (vp == 0 || vp->vec[0] == 0 ? \"\" : vp->vec[0]);\n}\n\nstruct varent *\nmadrof(pat, vp)\n\tchar *pat;\n\tregister struct varent *vp;\n{\n\tregister struct varent *vp1;\n\n\tfor (; vp; vp = vp->v_right) {\n\t\tif (vp->v_left && (vp1 = madrof(pat, vp->v_left)))\n\t\t\treturn vp1;\n\t\tif (Gmatch(vp->v_name, pat))\n\t\t\treturn vp;\n\t}\n\treturn vp;\n}\n\nstruct varent *\nadrof1(name, v)\n\tregister char *name;\n\tregister struct varent *v;\n{\n\tregister cmp;\n\n\tv = v->v_left;\n\twhile (v && ((cmp = *name - *v->v_name) ||\n\t\t     (cmp = strcmp(name, v->v_name))))\n\t\tif (cmp < 0)\n\t\t\tv = v->v_left;\n\t\telse\n\t\t\tv = v->v_right;\n\treturn v;\n}\n\n/*\n * The caller is responsible for putting value in a safe place\n */\nset(var, val)\n\tchar *var, *val;\n{\n\tregister char **vec = (char **) xalloc(2 * sizeof (char **));\n\n\tvec[0] = onlyread(val) ? savestr(val) : val;\n\tvec[1] = 0;\n\tset1(var, vec, &shvhed);\n}\n\nset1(var, vec, head)\n\tchar *var, **vec;\n\tstruct varent *head;\n{\n\tregister char **oldv = vec;\n\n\tgflag = 0; tglob(oldv);\n\tif (gflag) {\n\t\tvec = glob(oldv);\n\t\tif (vec == 0) {\n\t\t\tbferr(\"No match\");\n\t\t\tblkfree(oldv);\n\t\t\treturn;\n\t\t}\n\t\tblkfree(oldv);\n\t\tgargv = 0;\n\t}\n\tsetq(var, vec, head);\n}\n\nsetq(name, vec, p)\n\tchar *name, **vec;\n\tregister struct varent *p;\n{\n\tregister struct varent *c;\n\tregister f;\n\n\tf = 0;\t\t\t/* tree hangs off the header's left link */\n\twhile (c = p->v_link[f]) {\n\t\tif ((f = *name - *c->v_name) == 0 &&\n\t\t    (f = strcmp(name, c->v_name)) == 0) {\n\t\t\tblkfree(c->vec);\n\t\t\tgoto found;\n\t\t}\n\t\tp = c;\n\t\tf = f > 0;\n\t}\n\tp->v_link[f] = c = (struct varent *)xalloc(sizeof (struct varent));\n\tc->v_name = savestr(name);\n\tc->v_bal = 0;\n\tc->v_left = c->v_right = 0;\n\tc->v_parent = p;\n\tbalance(p, f, 0);\nfound:\n\ttrim(c->vec = vec);\n}\n\nunset(v)\n\tchar *v[];\n{\n\n\tunset1(v, &shvhed);\n\tif (adrof(\"histchars\") == 0) {\n\t\tHIST = '!';\n\t\tHISTSUB = '^';\n\t}\n#ifdef FILEC\n\tif (adrof(\"filec\") == 0)\n\t\tfilec = 0;\n#endif\n}\n\nunset1(v, head)\n\tregister char *v[];\n\tstruct varent *head;\n{\n\tregister struct varent *vp;\n\tregister int cnt;\n\n\twhile (*++v) {\n\t\tcnt = 0;\n\t\twhile (vp = madrof(*v, head->v_left))\n\t\t\tunsetv1(vp), cnt++;\n\t\tif (cnt == 0)\n\t\t\tsetname(*v);\n\t}\n}\n\nunsetv(var)\n\tchar *var;\n{\n\tregister struct varent *vp;\n\n\tif ((vp = adrof1(var, &shvhed)) == 0)\n\t\tudvar(var);\n\tunsetv1(vp);\n}\n\nunsetv1(p)\n\tregister struct varent *p;\n{\n\tregister struct varent *c, *pp;\n\tregister f;\n\n\t/*\n\t * Free associated memory first to avoid complications.\n\t */\n\tblkfree(p->vec);\n\tXFREE(p->v_name);\n\t/*\n\t * If p is missing one child, then we can move the other\n\t * into where p is.  Otherwise, we find the predecessor\n\t * of p, which is guaranteed to have no right child, copy\n\t * it into p, and move it's left child into it.\n\t */\n\tif (p->v_right == 0)\n\t\tc = p->v_left;\n\telse if (p->v_left == 0)\n\t\tc = p->v_right;\n\telse {\n\t\tfor (c = p->v_left; c->v_right; c = c->v_right)\n\t\t\t;\n\t\tp->v_name = c->v_name;\n\t\tp->vec = c->vec;\n\t\tp = c;\n\t\tc = p->v_left;\n\t}\n\t/*\n\t * Move c into where p is.\n\t */\n\tpp = p->v_parent;\n\tf = pp->v_right == p;\n\tif (pp->v_link[f] = c)\n\t\tc->v_parent = pp;\n\t/*\n\t * Free the deleted node, and rebalance.\n\t */\n\tXFREE((char *)p);\n\tbalance(pp, f, 1);\n}\n\nsetNS(cp)\n\tchar *cp;\n{\n\n\tset(cp, \"\");\n}\n\nshift(v)\n\tregister char **v;\n{\n\tregister struct varent *argv;\n\tregister char *name;\n\n\tv++;\n\tname = *v;\n\tif (name == 0)\n\t\tname = \"argv\";\n\telse\n\t\t(void) strip(name);\n\targv = adrof(name);\n\tif (argv == 0)\n\t\tudvar(name);\n\tif (argv->vec[0] == 0)\n\t\tbferr(\"No more words\");\n\tlshift(argv->vec, 1);\n}\n\nexportpath(val)\nchar **val;\n{\n\tchar exppath[BUFSIZ];\n\n\texppath[0] = 0;\n\tif (val)\n\t\twhile (*val) {\n\t\t\tif (strlen(*val) + strlen(exppath) + 2 > BUFSIZ) {\n\t\t\t\tprintf(\"Warning: ridiculously long PATH truncated\\n\");\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\t(void) strcat(exppath, *val++);\n\t\t\tif (*val == 0 || eq(*val, \")\"))\n\t\t\t\tbreak;\n\t\t\t(void) strcat(exppath, \":\");\n\t\t}\n\tsetenvv(\"PATH\", exppath);\n}\n\n\t/* macros to do single rotations on node p */\n#define rright(p) (\\\n\tt = (p)->v_left,\\\n\t(t)->v_parent = (p)->v_parent,\\\n\t((p)->v_left = t->v_right) ? (t->v_right->v_parent = (p)) : 0,\\\n\t(t->v_right = (p))->v_parent = t,\\\n\t(p) = t)\n#define rleft(p) (\\\n\tt = (p)->v_right,\\\n\t(t)->v_parent = (p)->v_parent,\\\n\t((p)->v_right = t->v_left) ? (t->v_left->v_parent = (p)) : 0,\\\n\t(t->v_left = (p))->v_parent = t,\\\n\t(p) = t)\n\n/*\n * Rebalance a tree, starting at p and up.\n * F == 0 means we've come from p's left child.\n * D == 1 means we've just done a delete, otherwise an insert.\n */\nbalance(p, f, d)\n\tregister struct varent *p;\n\tregister f;\n{\n\tregister struct varent *pp;\n\tregister struct varent *t;\t\t/* used by the rotate macros */\n\tregister ff;\n\n\t/*\n\t * Ok, from here on, p is the node we're operating on;\n\t * pp is it's parent; f is the branch of p from which we have come;\n\t * ff is the branch of pp which is p.\n\t */\n\tfor (; pp = p->v_parent; p = pp, f = ff) {\n\t\tff = pp->v_right == p;\n\t\tif (f ^ d) {\t\t/* right heavy */\n\t\t\tswitch (p->v_bal) {\n\t\t\tcase -1:\t\t/* was left heavy */\n\t\t\t\tp->v_bal = 0;\n\t\t\t\tbreak;\n\t\t\tcase 0:\t\t\t/* was balanced */\n\t\t\t\tp->v_bal = 1;\n\t\t\t\tbreak;\n\t\t\tcase 1:\t\t\t/* was already right heavy */\n\t\t\t\tswitch (p->v_right->v_bal) {\n\t\t\t\tcase 1:\t\t\t/* sigle rotate */\n\t\t\t\t\tpp->v_link[ff] = rleft(p);\n\t\t\t\t\tp->v_left->v_bal = 0;\n\t\t\t\t\tp->v_bal = 0;\n\t\t\t\t\tbreak;\n\t\t\t\tcase 0:\t\t\t/* single rotate */\n\t\t\t\t\tpp->v_link[ff] = rleft(p);\n\t\t\t\t\tp->v_left->v_bal = 1;\n\t\t\t\t\tp->v_bal = -1;\n\t\t\t\t\tbreak;\n\t\t\t\tcase -1:\t\t/* double rotate */\n\t\t\t\t\trright(p->v_right);\n\t\t\t\t\tpp->v_link[ff] = rleft(p);\n\t\t\t\t\tp->v_left->v_bal =\n\t\t\t\t\t\tp->v_bal < 1 ? 0 : -1;\n\t\t\t\t\tp->v_right->v_bal =\n\t\t\t\t\t\tp->v_bal > -1 ? 0 : 1;\n\t\t\t\t\tp->v_bal = 0;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t} else {\t\t/* left heavy */\n\t\t\tswitch (p->v_bal) {\n\t\t\tcase 1:\t\t\t/* was right heavy */\n\t\t\t\tp->v_bal = 0;\n\t\t\t\tbreak;\n\t\t\tcase 0:\t\t\t/* was balanced */\n\t\t\t\tp->v_bal = -1;\n\t\t\t\tbreak;\n\t\t\tcase -1:\t\t/* was already left heavy */\n\t\t\t\tswitch (p->v_left->v_bal) {\n\t\t\t\tcase -1:\t\t/* single rotate */\n\t\t\t\t\tpp->v_link[ff] = rright(p);\n\t\t\t\t\tp->v_right->v_bal = 0;\n\t\t\t\t\tp->v_bal = 0;\n\t\t\t\t\tbreak;\n\t\t\t\tcase 0:\t\t\t/* signle rotate */\n\t\t\t\t\tpp->v_link[ff] = rright(p);\n\t\t\t\t\tp->v_right->v_bal = -1;\n\t\t\t\t\tp->v_bal = 1;\n\t\t\t\t\tbreak;\n\t\t\t\tcase 1:\t\t\t/* double rotate */\n\t\t\t\t\trleft(p->v_left);\n\t\t\t\t\tpp->v_link[ff] = rright(p);\n\t\t\t\t\tp->v_left->v_bal =\n\t\t\t\t\t\tp->v_bal < 1 ? 0 : -1;\n\t\t\t\t\tp->v_right->v_bal =\n\t\t\t\t\t\tp->v_bal > -1 ? 0 : 1;\n\t\t\t\t\tp->v_bal = 0;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/*\n\t\t * If from insert, then we terminate when p is balanced.\n\t\t * If from delete, then we terminate when p is unbalanced.\n\t\t */\n\t\tif ((p->v_bal == 0) ^ d)\n\t\t\tbreak;\n\t}\n}\n\nplist(p)\n\tregister struct varent *p;\n{\n\tregister struct varent *c;\n\tregister len;\n\n\tif (setintr)\n\t\t(void) sigsetmask(sigblock(0L) & ~ sigmask(SIGINT));\n\tfor (;;) {\n\t\twhile (p->v_left)\n\t\t\tp = p->v_left;\n\tx:\n\t\tif (p->v_parent == 0)\t\t/* is it the header? */\n\t\t\treturn;\n\t\tlen = blklen(p->vec);\n\t\tprintf(\"%s\", p->v_name);\n\t\tputchar('\\t');\n\t\tif (len != 1)\n\t\t\tputchar('(');\n\t\tblkpr(p->vec);\n\t\tif (len != 1)\n\t\t\tputchar(')');\n\t\tputchar('\\n');\n\t\tif (p->v_right) {\n\t\t\tp = p->v_right;\n\t\t\tcontinue;\n\t\t}\n\t\tdo {\n\t\t\tc = p;\n\t\t\tp = p->v_parent;\n\t\t} while (p->v_right == c);\n\t\tgoto x;\n\t}\n}\n"
  },
  {
    "path": "bin/csh/sh.time.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley Software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if\t!defined(lint) && defined(DOSCCS)\nstatic char *sccsid = \"@(#)sh.time.c\t5.4.1 (2.11BSD GTE) 12/31/93\";\n#endif\n\n#include \"sh.h\"\n\n/*\n * C Shell - routines handling process timing and niceing\n */\n\nsettimes()\n{\n\tstruct rusage ruch;\n\n\t(void) gettimeofday(&time0, (struct timezone *)0);\n\t(void) getrusage(RUSAGE_SELF, &ru0);\n\t(void) getrusage(RUSAGE_CHILDREN, &ruch);\n\truadd(&ru0, &ruch);\n}\n\n/*\n * dotime is only called if it is truly a builtin function and not a\n * prefix to another command\n */\ndotime()\n{\n\tstruct timeval timedol;\n\tstruct rusage ru1, ruch;\n\n\t(void) getrusage(RUSAGE_SELF, &ru1);\n\t(void) getrusage(RUSAGE_CHILDREN, &ruch);\n\truadd(&ru1, &ruch);\n\t(void) gettimeofday(&timedol, (struct timezone *)0);\n\tprusage(&ru0, &ru1, &timedol, &time0);\n}\n\n/*\n * donice is only called when it on the line by itself or with a +- value\n */\ndonice(v)\n\tregister char **v;\n{\n\tregister char *cp;\n\tint nval;\n\n\tv++, cp = *v++;\n\tif (cp == 0)\n\t\tnval = 4;\n\telse if (*v == 0 && any(cp[0], \"+-\"))\n\t\tnval = getn(cp);\n\t(void) setpriority(PRIO_PROCESS, 0, nval);\n}\n\nruadd(ru, ru2)\n\tregister struct rusage *ru, *ru2;\n{\n\tregister long *lp, *lp2;\n\tregister int cnt;\n\n\ttvadd(&ru->ru_utime, &ru2->ru_utime);\n\ttvadd(&ru->ru_stime, &ru2->ru_stime);\n\tif (ru2->ru_maxrss > ru->ru_maxrss)\n\t\tru->ru_maxrss = ru2->ru_maxrss;\n\tcnt = &ru->ru_last - &ru->ru_first + 1;\n\tlp = &ru->ru_first; lp2 = &ru2->ru_first;\n\tdo\n\t\t*lp++ += *lp2++;\n\twhile (--cnt > 0);\n}\n\nprusage(r0, r1, e, b)\n\tregister struct rusage *r0, *r1;\n\tstruct timeval *e, *b;\n{\n\tregister time_t t =\n\t    (r1->ru_utime.tv_sec-r0->ru_utime.tv_sec)*100+\n\t    (r1->ru_utime.tv_usec-r0->ru_utime.tv_usec)/10000+\n\t    (r1->ru_stime.tv_sec-r0->ru_stime.tv_sec)*100+\n\t    (r1->ru_stime.tv_usec-r0->ru_stime.tv_usec)/10000;\n\tregister char *cp;\n\tregister long i;\n\tregister struct varent *vp = adrof(\"time\");\n\tlong ms =\n\t    (e->tv_sec-b->tv_sec)*100 + (e->tv_usec-b->tv_usec)/10000;\n\n#ifdef pdp11\n\tcp = \"%Uu %Ss %E %P %I+%Oio %Vov %Wsw\";\n#else\n\tcp = \"%Uu %Ss %E %P %X+%Dk %I+%Oio %Fpf+%Ww\";\n#endif\n\tif (vp && vp->vec[0] && vp->vec[1])\n\t\tcp = vp->vec[1];\n\tfor (; *cp; cp++)\n\tif (*cp != '%')\n\t\tputchar(*cp);\n\telse if (cp[1]) switch(*++cp) {\n\n\tcase 'U':\n\t\tpdeltat(&r1->ru_utime, &r0->ru_utime);\n\t\tbreak;\n\n\tcase 'S':\n\t\tpdeltat(&r1->ru_stime, &r0->ru_stime);\n\t\tbreak;\n\n\tcase 'E':\n\t\tpsecs(ms / 100);\n\t\tbreak;\n\n\tcase 'P':\n\t\tprintf(\"%d%%\", (int) (t*100 / ((ms ? ms : 1))));\n\t\tbreak;\n\n#ifdef pdp11\n\tcase 'V':\n\t\tprintf(\"%ld\", r1->ru_ovly - r0->ru_ovly);\n\t\tbreak;\n#endif\n\n\tcase 'W':\n\t\ti = r1->ru_nswap - r0->ru_nswap;\n\t\tprintf(\"%ld\", i);\n\t\tbreak;\n\n\tcase 'X':\n\t\tprintf(\"%ld\", t == 0 ? 0L : (r1->ru_ixrss-r0->ru_ixrss)/t);\n\t\tbreak;\n\n\tcase 'D':\n\t\tprintf(\"%ld\", t == 0 ? 0L :\n\t\t    (r1->ru_idrss+r1->ru_isrss-(r0->ru_idrss+r0->ru_isrss))/t);\n\t\tbreak;\n\n\tcase 'K':\n\t\tprintf(\"%ld\", t == 0 ? 0L :\n\t\t    ((r1->ru_ixrss+r1->ru_isrss+r1->ru_idrss) -\n\t\t    (r0->ru_ixrss+r0->ru_idrss+r0->ru_isrss))/t);\n\t\tbreak;\n\n\tcase 'M':\n\t\tprintf(\"%ld\", r1->ru_maxrss/2);\n\t\tbreak;\n\n\tcase 'F':\n\t\tprintf(\"%ld\", r1->ru_majflt-r0->ru_majflt);\n\t\tbreak;\n\n\tcase 'R':\n\t\tprintf(\"%ld\", r1->ru_minflt-r0->ru_minflt);\n\t\tbreak;\n\n\tcase 'I':\n\t\tprintf(\"%ld\", r1->ru_inblock-r0->ru_inblock);\n\t\tbreak;\n\n\tcase 'O':\n\t\tprintf(\"%ld\", r1->ru_oublock-r0->ru_oublock);\n\t\tbreak;\n\t}\n\tputchar('\\n');\n}\n\npdeltat(t1, t0)\n\tstruct timeval *t1, *t0;\n{\n\tstruct timeval td;\n\n\ttvsub(&td, t1, t0);\n\tprintf(\"%ld.%01ld\", td.tv_sec, td.tv_usec/100000);\n}\n\ntvadd(tsum, t0)\n\tstruct timeval *tsum, *t0;\n{\n\n\ttsum->tv_sec += t0->tv_sec;\n\ttsum->tv_usec += t0->tv_usec;\n\tif (tsum->tv_usec > 1000000)\n\t\ttsum->tv_sec++, tsum->tv_usec -= 1000000;\n}\n\ntvsub(tdiff, t1, t0)\n\tstruct timeval *tdiff, *t1, *t0;\n{\n\n\ttdiff->tv_sec = t1->tv_sec - t0->tv_sec;\n\ttdiff->tv_usec = t1->tv_usec - t0->tv_usec;\n\tif (tdiff->tv_usec < 0)\n\t\ttdiff->tv_sec--, tdiff->tv_usec += 1000000;\n}\n"
  },
  {
    "path": "bin/date/date.c",
    "content": "/*\n * Copyright (c) 1985 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * Date - print and set date\n */\n#include <sys/param.h>\n#include <sys/time.h>\n#include <sys/file.h>\n#include <errno.h>\n#include <syslog.h>\n#include <utmp.h>\n#include <paths.h>\n#include <tzfile.h>\n#include <stdio.h>\n#include <ctype.h>\n#include <strings.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n\n#define ATOI2(ar)   (ar[0] - '0') * 10 + (ar[1] - '0'); ar += 2;\n\nstatic struct timeval   tv;\nstatic int  retval;\n\nstatic int  dmsize[] =\n    { -1, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };\n\nstatic struct utmp  wtmp[2] = {\n    { \"|\", \"\", \"\", 0 },\n    { \"{\", \"\", \"\", 0 }\n};\n\n/*\n * gtime --\n *  convert user's time into number of seconds\n */\nstatic\ngtime(ap)\n    register char   *ap;        /* user argument */\n{\n    register int    year, month;\n    register char   *C;     /* pointer into time argument */\n    struct tm   *L;\n    int day, hour, mins, secs;\n\n    for (secs = 0, C = ap;*C;++C) {\n        if (*C == '.') {        /* seconds provided */\n            if (strlen(C) != 3)\n                return(1);\n            *C = NULL;\n            secs = (C[1] - '0') * 10 + (C[2] - '0');\n            break;\n        }\n        if (!isdigit(*C))\n            return(-1);\n    }\n\n    L = localtime((time_t *)&tv.tv_sec);\n    year = L->tm_year;          /* defaults */\n    month = L->tm_mon + 1;\n    day = L->tm_mday;\n\n    switch ((int)(C - ap)) {        /* length */\n        case 10:            /* yymmddhhmm */\n            year = ATOI2(ap);\n        case 8:             /* mmddhhmm */\n            month = ATOI2(ap);\n        case 6:             /* ddhhmm */\n            day = ATOI2(ap);\n        case 4:             /* hhmm */\n            hour = ATOI2(ap);\n            mins = ATOI2(ap);\n            break;\n        default:\n            return(1);\n    }\n\n    if (*ap || month < 1 || month > 12 || day < 1 || day > 31 ||\n         mins < 0 || mins > 59 || secs < 0 || secs > 59)\n        return(1);\n    if (hour == 24) {\n        ++day;\n        hour = 0;\n    }\n    else if (hour < 0 || hour > 23)\n        return(1);\n\n    tv.tv_sec = 0;\n    year += TM_YEAR_BASE;\n/* If year < EPOCH_YEAR, assume it's in the next century and\n   the system has not yet been patched to move TM_YEAR_BASE up yet */\n    if (year < EPOCH_YEAR)\n        year += 100;\n    if (isleap(year) && month > 2)\n        ++tv.tv_sec;\n    for (--year;year >= EPOCH_YEAR;--year)\n        tv.tv_sec += isleap(year) ? DAYS_PER_LYEAR : DAYS_PER_NYEAR;\n    while (--month)\n        tv.tv_sec += dmsize[month];\n    tv.tv_sec += day - 1;\n    tv.tv_sec = HOURS_PER_DAY * tv.tv_sec + hour;\n    tv.tv_sec = MINS_PER_HOUR * tv.tv_sec + mins;\n    tv.tv_sec = SECS_PER_MIN * tv.tv_sec + secs;\n    return(0);\n}\n\nmain(argc,argv)\n    int argc;\n    char    **argv;\n{\n    static char usage[] = \"usage: date [-nu] [-d dst] [-t timezone] [yymmddhhmm[.ss]]\\n\";\n    struct timezone tz;\n    char    *ap,            /* time string */\n        *tzn;           /* time zone */\n    int ch,         /* getopts char */\n        uflag,          /* do it in GMT */\n        nflag,          /* only set time locally */\n        wf;         /* wtmp file descriptor */\n    char    *username;\n    char    do_update = 0;\n\n    nflag = uflag = 0;\n    tz.tz_dsttime = tz.tz_minuteswest = 0;\n    while ((ch = getopt(argc,argv,\"d:nut:\")) != EOF)\n        switch((char)ch) {\n        case 'd':\n            tz.tz_dsttime = atoi(optarg) ? 1 : 0;\n            do_update = 1;\n            break;\n        case 'n':\n            nflag = 1;\n            break;\n        case 't':\n            tz.tz_minuteswest = atoi(optarg);\n            do_update = 1;\n            break;\n        case 'u':\n            uflag = 1;\n            break;\n        default:\n            fputs(usage,stderr);\n            exit(1);\n        }\n    argc -= optind;\n    argv += optind;\n\n    if (argc > 1) {\n        fputs(usage,stderr);\n        exit(1);\n    }\n\n    if ((do_update==1) &&\n        settimeofday((struct timeval *)NULL,&tz)) {\n        perror(\"settimeofday\");\n        retval = 1;\n        goto display;\n    }\n\n    if (gettimeofday(&tv,&tz)) {\n        perror(\"gettimeofday\");\n        exit(1);\n    }\n\n    if (!argc)\n        goto display;\n\n    wtmp[0].ut_time = tv.tv_sec;\n    if (gtime(*argv)) {\n        fputs(usage,stderr);\n        retval = 1;\n        goto display;\n    }\n\n    if (!uflag) {       /* convert to GMT assuming local time */\n        tv.tv_sec += (long)tz.tz_minuteswest * SECS_PER_MIN;\n                /* now fix up local daylight time */\n        if (localtime((time_t *)&tv.tv_sec)->tm_isdst)\n            tv.tv_sec -= SECS_PER_HOUR;\n    }\n    if (nflag || 1 /*!netsettime(tv)*/) {\n        if (settimeofday(&tv,(struct timezone *)0)) {\n            perror(\"settimeofday\");\n            retval = 1;\n            goto display;\n        }\n        if ((wf = open(_PATH_WTMP, O_WRONLY | O_APPEND)) < 0)\n            fputs(\"date: can't write wtmp file.\\n\",stderr);\n        else {\n            (void)time((time_t *)&wtmp[1].ut_time);\n            /*NOSTRICT*/\n            (void)write(wf,(char *)wtmp,sizeof(wtmp));\n            (void)close(wf);\n        }\n    }\n\n    username = getlogin();\n    if (!username || *username == '\\0') /* single-user or no tty */\n        username = \"root\";\n    syslog(LOG_AUTH | LOG_NOTICE,\"date set by %s\",username);\n\ndisplay:\n    if (gettimeofday(&tv,(struct timezone *)0)) {\n        perror(\"gettimeofday\");\n        exit(1);\n    }\n    if (uflag) {\n        ap = asctime(gmtime((time_t *)&tv.tv_sec));\n        tzn = \"GMT\";\n    }\n    else {\n        struct tm   *tp;\n\n        tp = localtime((time_t *)&tv.tv_sec);\n        ap = asctime(tp);\n        tzn = tp->tm_zone;\n    }\n    printf(\"%.20s%s%s\",ap,tzn,ap + 19);\n    exit(retval);\n}\n"
  },
  {
    "path": "bin/date2/.gitignore",
    "content": "date\n"
  },
  {
    "path": "bin/date2/Makefile",
    "content": "#\n# Public Domain.  1995/03/13 - Steven Schultz\n#\nTOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nBIN\t\t= date\nSRCS            = $(BIN).c\nOBJS            = $(BIN).o\n\nall:            $(BIN)\n\n$(BIN):    ${OBJS}\n\t\t${CC} ${CFLAGS} ${LDFLAGS} -o $@.elf ${OBJS} ${LIBS}\n\t\t${OBJDUMP} -S $@.elf > $@.dis\n\t\t${SIZE} $@.elf\n\t\t${ELF2AOUT} $@.elf $@\n\n.SUFFIXES:      .0 .1\n\nclean:\n\t\trm -f *.o *.elf ${MAN} *.elf *.dis tags *~ $(BIN)\n\ndepend:         ${SRCS}\n\t\tmkdep ${CFLAGS} ${SRCS}\n\ninstall:        all\n\t\t${INSTALL} -m 755 ${BIN} ${DESTDIR}/bin\n\nlint:           ${SRCS}\n\t\tlint -hax ${SRCS}\n\ntags:           ${SRCS}\n\t\tctags ${SRCS}\n"
  },
  {
    "path": "bin/date2/date.c",
    "content": "/*\n * Copyright (c) 1985 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * Date - print and set date\n */\n#include <sys/param.h>\n#include <sys/time.h>\n#include <sys/file.h>\n#include <errno.h>\n#include <syslog.h>\n#include <utmp.h>\n#include <paths.h>\n#include <tzfile.h>\n#include <stdio.h>\n#include <ctype.h>\n#include <strings.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n#include <fcntl.h>\n\n#define\tATOI2(ar)\t(ar[0] - '0') * 10 + (ar[1] - '0'); ar += 2;\n\nstatic struct timeval\ttv;\nstatic int\tretval;\n\nstatic int\tdmsize[] =\n\t{ -1, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };\n\nstatic struct utmp\twtmp[2] = {\n\t{ \"|\", \"\", \"\", 0 },\n\t{ \"{\", \"\", \"\", 0 }\n};\n\n/*\n * gtime --\n *\tconvert user's time into number of seconds\n */\nstatic int\ngtime(ap)\n\tregister char\t*ap;\t\t/* user argument */\n{\n\tregister int\tyear, month;\n\tregister char\t*C;\t\t/* pointer into time argument */\n\tstruct tm\t*L;\n\tint\tday, hour, mins, secs;\n\n\tfor (secs = 0, C = ap;*C;++C) {\n\t\tif (*C == '.') {\t\t/* seconds provided */\n\t\t\tif (strlen(C) != 3)\n\t\t\t\treturn(1);\n\t\t\t*C = NULL;\n\t\t\tsecs = (C[1] - '0') * 10 + (C[2] - '0');\n\t\t\tbreak;\n\t\t}\n\t\tif (!isdigit(*C))\n\t\t\treturn(-1);\n\t}\n\n\tL = localtime((time_t *)&tv.tv_sec);\n\tyear = L->tm_year;\t\t\t/* defaults */\n\tmonth = L->tm_mon + 1;\n\tday = L->tm_mday;\n\n\tswitch ((int)(C - ap)) {\t\t/* length */\n\t\tcase 10:\t\t\t/* yymmddhhmm */\n\t\t\tyear = ATOI2(ap);\n\t\tcase 8:\t\t\t\t/* mmddhhmm */\n\t\t\tmonth = ATOI2(ap);\n\t\tcase 6:\t\t\t\t/* ddhhmm */\n\t\t\tday = ATOI2(ap);\n\t\tcase 4:\t\t\t\t/* hhmm */\n\t\t\thour = ATOI2(ap);\n\t\t\tmins = ATOI2(ap);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treturn(1);\n\t}\n\n\tif (*ap || month < 1 || month > 12 || day < 1 || day > 31 ||\n\t     mins < 0 || mins > 59 || secs < 0 || secs > 59)\n\t\treturn(1);\n\tif (hour == 24) {\n\t\t++day;\n\t\thour = 0;\n\t}\n\telse if (hour < 0 || hour > 23)\n\t\treturn(1);\n\n\ttv.tv_sec = 0;\n\tyear += TM_YEAR_BASE;\n/* If year < EPOCH_YEAR, assume it's in the next century and\n   the system has not yet been patched to move TM_YEAR_BASE up yet */\n\tif (year < EPOCH_YEAR)\n\t\tyear += 100;\n\tif (isleap(year) && month > 2)\n\t\t++tv.tv_sec;\n\tfor (--year;year >= EPOCH_YEAR;--year)\n\t\ttv.tv_sec += isleap(year) ? DAYS_PER_LYEAR : DAYS_PER_NYEAR;\n\twhile (--month)\n\t\ttv.tv_sec += dmsize[month];\n\ttv.tv_sec += day - 1;\n\ttv.tv_sec = HOURS_PER_DAY * tv.tv_sec + hour;\n\ttv.tv_sec = MINS_PER_HOUR * tv.tv_sec + mins;\n\ttv.tv_sec = SECS_PER_MIN * tv.tv_sec + secs;\n\treturn(0);\n}\n\nconst char *wday_s[] = {\"Sun\",\"Mon\",\"Tue\",\"Wed\",\"Thu\",\"Fri\",\"Sat\",0};\nconst char *wday_l[] = {\"Sunday\",\"Monday\",\"Tuesday\",\"Wednesday\",\"Thursday\",\"Friday\",\"Saturday\",0};\nconst char *month_l[] = {\"January\",\"February\",\"March\",\"April\",\"May\",\"June\",\"July\",\"August\",\"September\",\"October\",\"November\",\"December\",0};\nconst char *month_s[] = {\"Jan\",\"Feb\",\"Mar\",\"Apr\",\"May\",\"Jun\",\"Jul\",\"Aug\",\"Sep\",\"Oct\",\"Nov\",\"Dec\",0};\n\nvoid fmttime(char *fmt, struct tm *tm)\n{\n\tchar *p;\n\tchar temp[10];\n\n\tfor(p=fmt; *p; p++)\n\t{\n\t\tswitch(*p)\n\t\t{\n\t\t\tcase '%':\n\t\t\t\tp++;\n\t\t\t\tswitch(*p)\n\t\t\t\t{\n\t\t\t\t\tcase 'd':\t// Day of the month, 2 digits, leading 0 - 01-31\n\t\t\t\t\t\tprintf(\"%02d\",tm->tm_mday);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'D':\n\t\t\t\t\t\tprintf(\"%s\",wday_s[tm->tm_wday]);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'j':\n\t\t\t\t\t\tprintf(\"%d\",tm->tm_mday);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'l':\n\t\t\t\t\t\tprintf(\"%s\",wday_l[tm->tm_wday]);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'N':\n\t\t\t\t\t\tprintf(\"%d\",tm->tm_wday == 0 ? 7 : tm->tm_wday);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'S':\n\t\t\t\t\t\tswitch(tm->tm_mday)\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tcase 1:\n\t\t\t\t\t\t\tcase 21:\n\t\t\t\t\t\t\tcase 31:\n\t\t\t\t\t\t\t\tprintf(\"st\");\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\tcase 2:\n\t\t\t\t\t\t\tcase 22:\n\t\t\t\t\t\t\tprintf(\"nd\");\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\tcase 3:\n\t\t\t\t\t\t\tcase 23:\n\t\t\t\t\t\t\t\tprintf(\"rd\");\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\tdefault:\n\t\t\t\t\t\t\t\tprintf(\"th\");\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t}\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'w':\n\t\t\t\t\t\tprintf(\"%d\",tm->tm_wday);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'z':\n\t\t\t\t\t\tprintf(\"%d\",tm->tm_yday);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'F':\n\t\t\t\t\t\tprintf(\"%s\",month_l[tm->tm_mon]);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'm':\n\t\t\t\t\t\tprintf(\"%02d\",tm->tm_mon+1);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'M':\n\t\t\t\t\t\tprintf(\"%s\",month_s[tm->tm_mon]);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'n':\n\t\t\t\t\t\tprintf(\"%d\",tm->tm_mon+1);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 't':\n\t\t\t\t\t\tswitch(tm->tm_mon)\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tcase 0:\t\tprintf(\"%d\",31); break;\t// Jan\n\t\t\t\t\t\t\tcase 1:\t\tprintf(\"%d\",((tm->tm_year+1900) % 4 == 0) ? 29 : 28); break;\t// Feb\n\t\t\t\t\t\t\tcase 2:\t\tprintf(\"%d\",31); break;\t// Mar\n\t\t\t\t\t\t\tcase 3:\t\tprintf(\"%d\",30); break;\t// Apr\n\t\t\t\t\t\t\tcase 4:\t\tprintf(\"%d\",31); break; // May\n\t\t\t\t\t\t\tcase 5:\t\tprintf(\"%d\",30); break; // Jun\n\t\t\t\t\t\t\tcase 6:\t\tprintf(\"%d\",31); break; // Jul\n\t\t\t\t\t\t\tcase 7:\t\tprintf(\"%d\",31); break; // Aug\n\t\t\t\t\t\t\tcase 8:\t\tprintf(\"%d\",30); break; // Sep\n\t\t\t\t\t\t\tcase 9:\t\tprintf(\"%d\",31); break; // Oct\n\t\t\t\t\t\t\tcase 10:\tprintf(\"%d\",30); break; // Nov\n\t\t\t\t\t\t\tcase 11:\tprintf(\"%d\",31); break; // Dec\n\t\t\t\t\t\t}\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'L':\n\t\t\t\t\t\tprintf(\"%d\",((tm->tm_year+1900) % 4 == 0) ? 1 : 0);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'o':\n\t\t\t\t\tcase 'Y':\n\t\t\t\t\t\tprintf(\"%04d\",tm->tm_year+1900);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'y':\n\t\t\t\t\t\tprintf(\"%02d\",(tm->tm_year+1900) % 100);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'a':\n\t\t\t\t\t\tprintf(\"%s\",(tm->tm_hour<12) ? \"am\" : \"pm\");\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'A':\n\t\t\t\t\t\tprintf(\"%s\",(tm->tm_hour<12) ? \"AM\" : \"PM\");\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'g':\n\t\t\t\t\t\tprintf(\"%d\",tm->tm_hour % 12);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'G':\n\t\t\t\t\t\tprintf(\"%d\",tm->tm_hour);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'h':\n\t\t\t\t\t\tprintf(\"%02d\",tm->tm_hour % 12);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'H':\n\t\t\t\t\t\tprintf(\"%02d\",tm->tm_hour);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'i':\n\t\t\t\t\t\tprintf(\"%02d\",tm->tm_min);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 's':\n\t\t\t\t\t\tprintf(\"%02d\",tm->tm_sec);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'u':\n\t\t\t\t\t\tprintf(\"000000\");\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'e':\n\t\t\t\t\t\tprintf(\"%s\",tm->tm_zone);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'I':\n\t\t\t\t\t\tprintf(\"%d\",tm->tm_isdst);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'O':\n\t\t\t\t\t\tprintf(\"%02d%02d\",tm->tm_gmtoff/60,tm->tm_gmtoff%60);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'P':\n\t\t\t\t\t\tprintf(\"%02d:%02d\",tm->tm_gmtoff/60,tm->tm_gmtoff%60);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'T':\n\t\t\t\t\t\tprintf(\"%s\",tm->tm_zone);\n\t\t\t\t\tbreak;\n\t\t\t\t\t\n/*\n        int     tm_sec;\n        int     tm_min;\n        int     tm_hour;\n        int     tm_mday;\n        int     tm_mon;\n        int     tm_year;\n        int     tm_wday;\n        int     tm_yday;\n        int     tm_isdst;\n        long    tm_gmtoff;\n        char    *tm_zone;\n*/\n\n\t\t\t\t\tdefault:\n\t\t\t\t\t\tprintf(\"%c\",*p);\n\t\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase '\\\\':\n\t\t\t\tp++;\n\t\t\t\tswitch(*p)\n\t\t\t\t{\n\t\t\t\t\tcase 'n':\n\t\t\t\t\t\tprintf(\"\\n\");\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 'r':\n\t\t\t\t\t\tprintf(\"\\r\");\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 't':\n\t\t\t\t\t\tprintf(\"\\t\");\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tdefault:\n\t\t\t\t\t\tprintf(\"%c\",*p);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tprintf(\"%c\",*p);\n\t\t\t\tbreak;\n\t\t}\n\t}\n\t\n}\n\nint\nmain(argc,argv)\n\tint\targc;\n\tchar\t**argv;\n{\n\tstatic char\tusage[] = \"usage: date [-nu] [-d dst] [-t timezone] [yymmddhhmm[.ss]]\\n\";\n\tstruct timezone\ttz;\n\tchar\t*ap,\t\t\t/* time string */\n\t\t*tzn;\t\t\t/* time zone */\n\tint\tch,\t\t\t/* getopts char */\n\t\tuflag,\t\t\t/* do it in GMT */\n\t\tnflag,\t\t\t/* only set time locally */\n\t\twf;\t\t\t/* wtmp file descriptor */\n        char    *username;\n        char    do_update = 0;\n\n\tchar \t*fmt = \"%D %M %d %H:%i:%s %T %Y\\n\";\n\n\tnflag = uflag = 0;\n\ttz.tz_dsttime = tz.tz_minuteswest = 0;\n\twhile ((ch = getopt(argc,argv,\"d:nut:f:\")) != EOF)\n\t\tswitch((char)ch) {\n\t\tcase 'd':\n\t\t\ttz.tz_dsttime = atoi(optarg) ? 1 : 0;\n\t\t\tdo_update = 1;\n\t\t\tbreak;\n\t\tcase 'n':\n\t\t\tnflag = 1;\n\t\t\tbreak;\n\t\tcase 't':\n\t\t\ttz.tz_minuteswest = atoi(optarg);\n\t\t\tdo_update = 1;\n\t\t\tbreak;\n\t\tcase 'u':\n\t\t\tuflag = 1;\n\t\t\tbreak;\n\t\tcase 'f':\n\t\t\tfmt = optarg;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tfputs(usage,stderr);\n\t\t\texit(1);\n\t\t}\n\targc -= optind;\n\targv += optind;\n\n\tif (argc > 1) {\n\t\tfputs(usage,stderr);\n\t\texit(1);\n\t}\n\n\tif ((do_update==1) &&\n\t    settimeofday((struct timeval *)NULL,&tz)) {\n\t\tperror(\"settimeofday\");\n\t\tretval = 1;\n\t\tgoto display;\n\t}\n\n\tif (gettimeofday(&tv,&tz)) {\n\t\tperror(\"gettimeofday\");\n\t\texit(1);\n\t}\n\n\tif (!argc)\n\t\tgoto display;\n\n\twtmp[0].ut_time = tv.tv_sec;\n\tif (gtime(*argv)) {\n\t\tfputs(usage,stderr);\n\t\tretval = 1;\n\t\tgoto display;\n\t}\n\n\tif (!uflag) {\t\t/* convert to GMT assuming local time */\n\t\ttv.tv_sec += (long)tz.tz_minuteswest * SECS_PER_MIN;\n\t\t\t\t/* now fix up local daylight time */\n\t\tif (localtime((time_t *)&tv.tv_sec)->tm_isdst)\n\t\t\ttv.tv_sec -= SECS_PER_HOUR;\n\t}\n\tif (nflag || 1 /*!netsettime(tv)*/) {\n\t\tif (settimeofday(&tv,(struct timezone *)0)) {\n\t\t\tperror(\"settimeofday\");\n\t\t\tretval = 1;\n\t\t\tgoto display;\n\t\t}\n\t\tif ((wf = open(_PATH_WTMP, O_WRONLY | O_APPEND)) < 0)\n\t\t\tfputs(\"date: can't write wtmp file.\\n\",stderr);\n\t\telse {\n\t\t\t(void)time((time_t *)&wtmp[1].ut_time);\n\t\t\t/*NOSTRICT*/\n\t\t\t(void)write(wf,(char *)wtmp,sizeof(wtmp));\n\t\t\t(void)close(wf);\n\t\t}\n\t}\n\n\tusername = getlogin();\n\tif (!username || *username == '\\0')\t/* single-user or no tty */\n\t\tusername = \"root\";\n\tsyslog(LOG_AUTH | LOG_NOTICE,\"date set by %s\",username);\n\ndisplay:\n\tif (gettimeofday(&tv,(struct timezone *)0)) {\n\t\tperror(\"gettimeofday\");\n\t\texit(1);\n\t}\n\tif (uflag) {\n\t\tfmttime(fmt,gmtime((time_t *)&tv.tv_sec));\n\t}\n\telse {\n\t\tstruct tm\t*tp;\n\n\t\ttp = localtime((time_t *)&tv.tv_sec);\n\t\tfmttime(fmt,tp);\n\t}\n\texit(retval);\n}\n"
  },
  {
    "path": "distrib/.gitignore",
    "content": "obj\n"
  },
  {
    "path": "distrib/base/mi",
    "content": "#\n# Machine independent root file system manifest file.\n#\ndefault\nowner 0\ngroup 0\ndirmode 0775\nfilemode 0664\n\n#\n# Directories.\n#\ndir /bin\ndir /dev\ndir /etc\ndir /sbin\ndir /tmp\ndir /usr\ndir /home\ndir /usr/bin\ndir /usr/sbin\ndir /usr/libexec\n\n#\n# Block devices.\n#\n# Major Minor Name  Device\n# -------------------------\n#   0     0   sd0   Main SD card\n#   0     1   sd0a  Partition 1: root file system\n#   0     2   sd0b  Partition 2: swap space\n#   0     3   sd0c  Partition 3\n#   0     4   sd0d  Partition 4\n#   0     8   sd1   Second SD card\n#   0     9   sd1a  Partition 1\n#   0     10  sd1b  Partition 2\n#   0     11  sd1c  Partition 3\n#   0     12  sd1d  Partition 4\n#   1     0   rc0   Volatile disk - SRAM connected via CPLD (sramc)\n#   1     1   rc0a  Partition 1: filesystem\n#   1     2   rc0b  Partition 2: swap space\n#   2     0   dr0   Volatile disk - SDRAM on external memory bus (sdramp)\n#   2     1   dr0a  Partition 1: filesystem\n#   2     2   dr0b  Partition 2: swap space\n#   3     0   mr0   Volatile disk - MRAM on SPI port (mrams)\n#   4     64  swap  Virtual swap device, mapped to real swap partition\n#   4     0   swap0 Virtual i/o area, allocated from swap space\n#   4     1   swap1 Virtual i/o area, allocated from swap space\n#   4     2   swap2 Virtual i/o area, allocated from swap space\n#   5     0   sr0   Volatile disk - serial RAM on SPI port (spirams)\n#\nbdev /dev/sd0\nmajor 0             # Main SD card\nminor 0\nbdev /dev/sd0a\nmajor 0\nminor 1\nbdev /dev/sd0b\nmajor 0\nminor 2\nbdev /dev/sd0c\nmajor 0\nminor 3\nbdev /dev/sd0d\nmajor 0\nminor 4\nbdev /dev/sd1\nmajor 0             # Second SD card\nminor 8\nbdev /dev/sd1a\nmajor 0\nminor 9\nbdev /dev/sd1b\nmajor 0\nminor 10\nbdev /dev/sd1c\nmajor 0\nminor 11\nbdev /dev/sd1d\nmajor 0\nminor 12\nbdev /dev/rc0\nmajor 1             # Volatile disk - SRAM connected via CPLD (sramc)\nminor 0\nbdev /dev/rc0a\nmajor 1\nminor 1\nbdev /dev/rc0b\nmajor 1\nminor 2\nbdev /dev/dr0\nmajor 2             # Volatile disk - SDRAM on external memory bus (sdramp)\nminor 0\nbdev /dev/dr0a\nmajor 2\nminor 1\nbdev /dev/dr0b\nmajor 2\nminor 2\nbdev /dev/mr0\nmajor 3             # Volatile disk - MRAM on SPI port (mrams)\nminor 0\nbdev /dev/swap\nmajor 4             # Virtual swap device, mapped to real swap partition\nminor 64\nbdev /dev/swap0\nmajor 4\nminor 0\nbdev /dev/swap1\nmajor 4\nminor 1\nbdev /dev/swap2\nmajor 4\nminor 2\nbdev /dev/sr0\nmajor 5             # Volatile disk - serial RAM on SPI port (spirams)\nminor 0\n\n#\n# Character devices.\n#\ncdev /dev/console\nmajor 0\nminor 0\ncdev /dev/mem\nmajor 1\nminor 0\ncdev /dev/kmem\nmajor 1\nminor 1\ncdev /dev/null\nmajor 1\nminor 2\nmode 666\ncdev /dev/zero\nmajor 1\nminor 3\nmode 666\ncdev /dev/tty\nmajor 2\nminor 0\nmode 666\ncdev /dev/stdin\nmajor 3\nminor 0\ncdev /dev/stdout\nmajor 3\nminor 1\ncdev /dev/stderr\nmajor 3\nminor 2\ncdev /dev/temp0\nmajor 4\nminor 0\ncdev /dev/temp1\nmajor 4\nminor 1\ncdev /dev/temp2\nmajor 4\nminor 2\ncdev /dev/klog\nmajor 5\nminor 0\n\n#\n# UART driver.\n#\ncdev /dev/tty0\nmajor 6\nminor 0\ncdev /dev/tty1\nmajor 6\nminor 1\ncdev /dev/tty2\nmajor 6\nminor 2\ncdev /dev/tty3\nmajor 6\nminor 3\ncdev /dev/tty4\nmajor 6\nminor 4\ncdev /dev/tty5\nmajor 6\nminor 5\n\n#\n# USB serial driver.\n#\ncdev /dev/ttyUSB0\nmajor 7\nminor 0\n\n#\n# Pseudo-terminals.\n#\ncdev /dev/ttyp0\nmajor 8\nminor 0\ncdev /dev/ttyp1\nmajor 8\nminor 1\ncdev /dev/ttyp2\nmajor 8\nminor 2\ncdev /dev/ttyp3\nmajor 8\nminor 3\ncdev /dev/ptyp0\nmajor 9\nminor 0\ncdev /dev/ptyp1\nmajor 9\nminor 1\ncdev /dev/ptyp2\nmajor 9\nminor 2\ncdev /dev/ptyp3\nmajor 9\nminor 3\n\n#\n# GPIO driver.\n#\ncdev /dev/porta\nmajor 10\nminor 0\ncdev /dev/portb\nmajor 10\nminor 1\ncdev /dev/portc\nmajor 10\nminor 2\ncdev /dev/portd\nmajor 10\nminor 3\ncdev /dev/porte\nmajor 10\nminor 4\ncdev /dev/portf\nmajor 10\nminor 5\ncdev /dev/portg\nmajor 10\nminor 6\ncdev /dev/confa\nmajor 10\nminor 64\ncdev /dev/confb\nmajor 10\nminor 65\ncdev /dev/confc\nmajor 10\nminor 66\ncdev /dev/confd\nmajor 10\nminor 67\ncdev /dev/confe\nmajor 10\nminor 68\ncdev /dev/conff\nmajor 10\nminor 69\ncdev /dev/confg\nmajor 10\nminor 70\n\n#\n# ADC driver.\n#\ncdev /dev/adc0\nmajor 11\nminor 0\ncdev /dev/adc1\nmajor 11\nminor 1\ncdev /dev/adc2\nmajor 11\nminor 2\ncdev /dev/adc3\nmajor 11\nminor 3\ncdev /dev/adc4\nmajor 11\nminor 4\ncdev /dev/adc5\nmajor 11\nminor 5\ncdev /dev/adc6\nmajor 11\nminor 6\ncdev /dev/adc7\nmajor 11\nminor 7\ncdev /dev/adc8\nmajor 11\nminor 8\ncdev /dev/adc9\nmajor 11\nminor 9\ncdev /dev/adc10\nmajor 11\nminor 10\ncdev /dev/adc11\nmajor 11\nminor 11\ncdev /dev/adc12\nmajor 11\nminor 12\ncdev /dev/adc13\nmajor 11\nminor 13\ncdev /dev/adc14\nmajor 11\nminor 14\ncdev /dev/adc15\nmajor 11\nminor 15\n\n#\n# SPI driver.\n#\ncdev /dev/spi1\nmajor 12\nminor 0\ncdev /dev/spi2\nmajor 12\nminor 1\ncdev /dev/spi3\nmajor 12\nminor 2\ncdev /dev/spi4\nmajor 12\nminor 3\n\n#\n# GLCD driver.\n#\ncdev /dev/glcd0\nmajor 13\nminor 0\n\n#\n# PWM driver.\n#\ncdev /dev/pwm1\nmajor 14\nminor 0\ncdev /dev/pwm2\nmajor 14\nminor 1\ncdev /dev/pwm3\nmajor 14\nminor 2\ncdev /dev/pwm4\nmajor 14\nminor 3\ncdev /dev/pwm5\nmajor 14\nminor 4\n\n#\n# PICGA driver.\n#\ncdev /dev/picga0\nmajor 15\nminor 0\n\n#\n# TFT display driver.\n#\ncdev /dev/tft0\nmajor 16\nminor 0\ncdev /dev/tftin0\nmajor 16\nminor 1\n\n#\n# Skeleton driver.\n#\ncdev /dev/skel1\nmajor 17\nminor 0\ncdev /dev/skel2\nmajor 17\nminor 1\ncdev /dev/skel3\nmajor 17\nminor 2\ncdev /dev/skel4\nmajor 17\nminor 3\ncdev /dev/skel5\nmajor 17\nminor 4\n\n#\n# Files: /root\n#\ndir /root\nfile /root/.profile\n\nsymlink /.profile\ntarget root/.profile\n\n#\n# Files: /etc\n#\nfile /etc/fstab\nfile /etc/gettytab\nfile /etc/group\nfile /etc/MAKEDEV\nmode 0775\nfile /etc/motd\nfile /etc/passwd\nfile /etc/phones\nfile /etc/rc\nmode 0775\nfile /etc/rc.local\nmode 0775\nfile /etc/remote\nfile /etc/shadow\nfile /etc/shells\nfile /etc/termcap\nmode 0444\nfile /etc/ttys\n\nsymlink /etc/localtime\ntarget /usr/share/zoneinfo/Canada/Mountain\n\n#\n# Files: /bin\n#\ndefault\nfilemode 0775\nfile /usr/bin/aout\nfile /usr/bin/apropos\nfile /usr/bin/ar\nfile /usr/bin/arch\nfile /usr/bin/as\nfile /usr/bin/awk\nfile /usr/bin/basename\nfile /usr/bin/basic\nfile /usr/bin/bc\nfile /usr/bin/cal\nfile /usr/bin/calendar\nfile /bin/cat\nfile /usr/bin/cb\nfile /usr/bin/cc\nfile /usr/bin/chat-server\nfile /usr/bin/chflags\nfile /bin/chgrp\nfile /bin/chmod\nfile /usr/bin/chpass\nmode 04755\nfile /usr/bin/cmp\nfile /usr/bin/col\nfile /usr/bin/comm\nfile /usr/bin/compress\nfile /bin/cp\nfile /usr/bin/cpp\nfile /usr/bin/crontab\nfile /bin/date\nfile /usr/bin/dc\nfile /bin/dd\nfile /bin/df\nmode 02755\nfile /usr/bin/diff\nfile /usr/bin/diskspeed\nfile /usr/bin/du\nfile /bin/echo\nfile /bin/ed\nfile /usr/bin/egrep\nfile /usr/bin/emg\nfile /usr/bin/env\nfile /bin/expr\nfile /usr/bin/false\nfile /usr/bin/fgrep\nfile /usr/bin/file\nfile /usr/bin/find\nfile /usr/bin/fold\nfile /usr/bin/forth\nfile /usr/bin/fstat\nmode 02755\nfile /usr/bin/glcdtest\nfile /usr/bin/globdump\nfile /usr/bin/globread\nfile /usr/bin/globwrite\nfile /usr/bin/grep\nfile /usr/bin/groups\nfile /usr/bin/head\nfile /usr/bin/hostid\nfile /bin/hostname\nfile /usr/bin/id\nfile /usr/bin/install\nfile /usr/sbin/iostat\nmode 02755\nfile /usr/bin/join\nfile /bin/kill\nfile /usr/bin/la\nfile /usr/bin/last\nfile /usr/bin/lcc\nfile /usr/bin/lcpp\nfile /usr/bin/ld\nfile /bin/ln\nfile /usr/bin/login\nmode 04755\nfile /usr/bin/lol\nfile /bin/ls\nfile /usr/bin/m4\nfile /usr/bin/mail\nmode 04755\nfile /usr/bin/make\nfile /usr/bin/man\nfile /bin/md5\nfile /usr/bin/med\nfile /usr/bin/mesg\nfile /bin/mkdir\nfile /usr/bin/more\nfile /usr/bin/msec\nfile /bin/mv\nfile /usr/bin/nice\nfile /usr/bin/nm\nfile /usr/bin/nohup\nfile /usr/bin/ntpdate\nfile /usr/bin/od\nfile /usr/bin/pagesize\nfile /usr/bin/passwd\nmode 04755\nfile /usr/bin/pdc\nfile /usr/bin/picoc\nfile /usr/bin/portio\nfile /usr/bin/pr\nfile /usr/bin/printenv\nfile /usr/bin/printf\nfile /bin/ps\nmode 02755\nfile /bin/pwd\nfile /usr/bin/pwm\nfile /usr/bin/ranlib\nfile /usr/bin/re\nfile /usr/bin/renice\nfile /usr/bin/renumber\nfile /usr/bin/retroforth\nfile /usr/bin/rev\nfile /bin/rm\nfile /bin/rmail\nfile /bin/rmdir\nfile /usr/bin/rz\nfile /usr/bin/scc\nfile /usr/bin/scm\nfile /usr/bin/sed\nfile /usr/bin/setty\nfile /bin/sh\nfile /usr/bin/size\nfile /usr/bin/sl\nfile /bin/sleep\nfile /usr/bin/smux\nfile /usr/bin/sort\nfile /usr/bin/split\nfile /usr/bin/strip\nfile /bin/stty\nfile /usr/bin/su\nmode 04755\nfile /usr/bin/sum\nfile /bin/sync\nfile /sbin/sysctl\nfile /usr/bin/sz\nfile /usr/bin/tail\nfile /bin/tar\nfile /usr/bin/tclsh\nfile /usr/bin/tee\nfile /usr/bin/telnet\nfile /bin/test\nfile /usr/bin/time\nfile /usr/bin/tip\nfile /usr/bin/touch\nfile /usr/bin/tr\nfile /usr/bin/true\nfile /usr/bin/tsort\nfile /usr/bin/tty\nfile /usr/bin/uname\nfile /usr/bin/uncompress\nfile /usr/bin/uniq\nfile /usr/bin/uucico\nfile /usr/bin/uuclean\nfile /usr/bin/uucp\nfile /usr/bin/uudecode\nfile /usr/bin/uuencode\nfile /usr/bin/uulog\nfile /usr/bin/uuname\nfile /usr/bin/uupoll\nfile /usr/bin/uuq\nfile /usr/bin/uusend\nfile /usr/bin/uusnap\nfile /usr/bin/uux\nfile /usr/bin/uuxqt\nfile /usr/bin/vi\nfile /usr/bin/vmstat\nmode 02755\nfile /usr/bin/w\nfile /usr/bin/wall\nmode 02755\nfile /usr/bin/wc\nfile /usr/bin/web-client\nfile /usr/bin/web-server\nfile /usr/bin/whereis\nfile /usr/bin/who\nfile /usr/bin/whoami\nfile /usr/bin/write\nmode 02755\nfile /usr/bin/xargs\nfile /usr/bin/yacc\nfile /usr/bin/zcat\n\nlink /bin/[\ntarget /bin/test\n\nlink /usr/bin/whatis\ntarget /usr/bin/apropos\n\nlink /usr/bin/chfn\ntarget /usr/bin/chpass\nlink /usr/bin/chsh\ntarget /usr/bin/chpass\n\nlink /usr/bin/rb\ntarget /usr/bin/rz\nlink /usr/bin/rx\ntarget /usr/bin/rz\n\nlink /usr/bin/sb\ntarget /usr/bin/sz\nlink /usr/bin/sx\ntarget /usr/bin/sz\n\nlink /usr/bin/machine\ntarget /usr/bin/arch\n\nlink /usr/bin/uptime\ntarget /usr/bin/w\n\n#\n# Files: /sbin\n#\nfile /sbin/chown\nfile /usr/sbin/chroot\nmode 04755\nfile /usr/sbin/cron\nfile /usr/sbin/disktool\nfile /sbin/fdisk\nfile /sbin/fsck\nfile /sbin/init\nmode 0700\nfile /sbin/mkfs\nfile /sbin/mknod\nfile /usr/sbin/mkpasswd\nfile /sbin/mount\nfile /usr/sbin/pstat\nmode 02755\nfile /sbin/reboot\nfile /sbin/shutdown\nmode 04750\nfile /usr/sbin/talloc\nfile /sbin/umount\nfile /usr/sbin/update\nfile /usr/libexec/updatedb\nfile /usr/sbin/vipw\n\nlink /sbin/bootloader\ntarget /sbin/reboot\nlink /sbin/fastboot\ntarget /sbin/reboot\nlink /sbin/halt\ntarget /sbin/reboot\nlink /sbin/poweroff\ntarget /sbin/reboot\n\n#\n# Files: /usr/games\n#\ndefault\nfilemode 0775\ndir /usr/games\nfile /usr/games/adventure\nfile /usr/games/aclock\nfile /usr/games/arithmetic\nfile /usr/games/atc\nfile /usr/games/backgammon\nfile /usr/games/banner\nfile /usr/games/battlestar\nfile /usr/games/bcd\nfile /usr/games/boggle\nfile /usr/games/btlgammon\nfile /usr/games/caesar\nfile /usr/games/canfield\nfile /usr/games/cfscores\nfile /usr/games/cribbage\nfile /usr/games/factor\nfile /usr/games/fish\nfile /usr/games/fortune\nfile /usr/games/hangman\nfile /usr/games/mille\nfile /usr/games/monop\nfile /usr/games/morse\nfile /usr/games/number\nfile /usr/games/pig\nfile /usr/games/pom\nfile /usr/games/ppt\nfile /usr/games/primes\nfile /usr/games/quiz\nfile /usr/games/rain\nfile /usr/games/robots\nfile /usr/games/rogue\nfile /usr/games/sail\nfile /usr/games/snake\nfile /usr/games/snscore\nfile /usr/games/teachgammon\nfile /usr/games/trek\nfile /usr/games/worm\nfile /usr/games/worms\nfile /usr/games/wump\n\n#\n# Files: /usr/games/lib\n#\ndefault\nfilemode 0444\ndir /usr/games/lib\nfile /usr/games/lib/adventure.dat\nfile /usr/games/lib/battle_strings\nfile /usr/games/lib/backrules\nfile /usr/games/lib/bogdict\nfile /usr/games/lib/cfscores\nfile /usr/games/lib/crib.instr\nmode 0666\nfile /usr/games/lib/fortunes.dat\nfile /usr/games/lib/cards.pck\nfile /usr/games/lib/robots_roll\nmode 0666\nfile /usr/games/lib/snakerawscores\nmode 0666\ndir /usr/games/lib/atc\nfile /usr/games/lib/atc/ATC_scores\nfile /usr/games/lib/atc/crossover\nfile /usr/games/lib/atc/default\nfile /usr/games/lib/atc/easy\nfile /usr/games/lib/atc/game_2\nfile /usr/games/lib/atc/Game_List\nfile /usr/games/lib/atc/Killer\ndir /usr/games/lib/quiz.k\nfile /usr/games/lib/quiz.k/africa\nfile /usr/games/lib/quiz.k/america\nfile /usr/games/lib/quiz.k/areas\nfile /usr/games/lib/quiz.k/arith\nfile /usr/games/lib/quiz.k/asia\nfile /usr/games/lib/quiz.k/babies\nfile /usr/games/lib/quiz.k/bard\nfile /usr/games/lib/quiz.k/chinese\nfile /usr/games/lib/quiz.k/collectives\nfile /usr/games/lib/quiz.k/ed\nfile /usr/games/lib/quiz.k/elements\nfile /usr/games/lib/quiz.k/europe\nfile /usr/games/lib/quiz.k/greek\nfile /usr/games/lib/quiz.k/inca\nfile /usr/games/lib/quiz.k/index\nfile /usr/games/lib/quiz.k/latin\nfile /usr/games/lib/quiz.k/locomotive\nfile /usr/games/lib/quiz.k/midearth\nfile /usr/games/lib/quiz.k/morse\nfile /usr/games/lib/quiz.k/murders\nfile /usr/games/lib/quiz.k/poetry\nfile /usr/games/lib/quiz.k/posneg\nfile /usr/games/lib/quiz.k/pres\nfile /usr/games/lib/quiz.k/province\nfile /usr/games/lib/quiz.k/seq-easy\nfile /usr/games/lib/quiz.k/seq-hard\nfile /usr/games/lib/quiz.k/sexes\nfile /usr/games/lib/quiz.k/sov\nfile /usr/games/lib/quiz.k/spell\nfile /usr/games/lib/quiz.k/state\nfile /usr/games/lib/quiz.k/trek\nfile /usr/games/lib/quiz.k/ucc\n\n#\n# Files: /usr/include\n#\ndefault\nfilemode 0664\ndir /usr/include\ndir /usr/include/arpa\ndir /usr/include/machine\ndir /usr/include/readline\ndir /usr/include/smallc\ndir /usr/include/smallc/sys\ndir /usr/include/sys\nfile /usr/include/alloca.h\nfile /usr/include/a.out.h\nfile /usr/include/ar.h\nfile /usr/include/arpa/inet.h\nfile /usr/include/assert.h\nfile /usr/include/ctype.h\nfile /usr/include/curses.h\nfile /usr/include/fcntl.h\nfile /usr/include/float.h\nfile /usr/include/fstab.h\nfile /usr/include/grp.h\nfile /usr/include/kmem.h\nfile /usr/include/lastlog.h\nfile /usr/include/libgen.h\nfile /usr/include/limits.h\nfile /usr/include/math.h\nfile /usr/include/mtab.h\nfile /usr/include/ndbm.h\nfile /usr/include/nlist.h\nfile /usr/include/paths.h\nfile /usr/include/psout.h\nfile /usr/include/pwd.h\nfile /usr/include/ranlib.h\nfile /usr/include/readline/history.h\nfile /usr/include/readline/readline.h\nfile /usr/include/regexp.h\nfile /usr/include/setjmp.h\nfile /usr/include/sgtty.h\nfile /usr/include/smallc/curses.h\nfile /usr/include/smallc/fcntl.h\nfile /usr/include/smallc/signal.h\nfile /usr/include/smallc/stdio.h\nfile /usr/include/smallc/sys/gpio.h\nfile /usr/include/smallc/sys/spi.h\nfile /usr/include/smallc/wiznet.h\nfile /usr/include/stdarg.h\nfile /usr/include/stdbool.h\nfile /usr/include/stddef.h\nfile /usr/include/stdio.h\nfile /usr/include/stdlib.h\nfile /usr/include/string.h\nfile /usr/include/strings.h\nfile /usr/include/struct.h\nfile /usr/include/sys/buf.h\nfile /usr/include/syscall.h\nfile /usr/include/sys/callout.h\nfile /usr/include/sys/clist.h\nfile /usr/include/sys/conf.h\nfile /usr/include/sys/dir.h\nfile /usr/include/sys/disk.h\nfile /usr/include/sys/dkbad.h\nfile /usr/include/sys/dk.h\nfile /usr/include/sys/errno.h\nfile /usr/include/sys/exec_aout.h\nfile /usr/include/sys/exec_elf.h\nfile /usr/include/sys/exec.h\nfile /usr/include/sysexits.h\nfile /usr/include/sys/fcntl.h\nfile /usr/include/sys/file.h\nfile /usr/include/sys/fs.h\nfile /usr/include/sys/glcd.h\nfile /usr/include/sys/glob.h\nfile /usr/include/sys/gpanel.h\nfile /usr/include/sys/gpio.h\nfile /usr/include/sys/inode.h\nfile /usr/include/sys/ioctl.h\nfile /usr/include/sys/kernel.h\nfile /usr/include/sys/map.h\nfile /usr/include/sys/mount.h\nfile /usr/include/sys/msgbuf.h\nfile /usr/include/sys/mtio.h\nfile /usr/include/sys/namei.h\nfile /usr/include/sys/pwm.h\nfile /usr/include/sys/param.h\nfile /usr/include/sys/picga.h\nfile /usr/include/sys/proc.h\nfile /usr/include/sys/ptrace.h\nfile /usr/include/sys/pty.h\nfile /usr/include/sys/reboot.h\nfile /usr/include/sys/resource.h\nfile /usr/include/sys/select.h\nfile /usr/include/sys/signal.h\nfile /usr/include/sys/signalvar.h\nfile /usr/include/sys/spi.h\nfile /usr/include/sys/stat.h\nfile /usr/include/sys/stdint.h\nfile /usr/include/sys/swap.h\nfile /usr/include/sys/sysctl.h\nfile /usr/include/sys/syslimits.h\nfile /usr/include/sys/syslog.h\nfile /usr/include/sys/systm.h\nfile /usr/include/sys/time.h\nfile /usr/include/sys/times.h\nfile /usr/include/sys/ttychars.h\nfile /usr/include/sys/ttydev.h\nfile /usr/include/sys/tty.h\nfile /usr/include/sys/types.h\nfile /usr/include/sys/uio.h\nfile /usr/include/sys/user.h\nfile /usr/include/sys/utsname.h\nfile /usr/include/sys/vm.h\nfile /usr/include/sys/vmmac.h\nfile /usr/include/sys/vmmeter.h\nfile /usr/include/sys/vmparam.h\nfile /usr/include/sys/vmsystm.h\nfile /usr/include/sys/wait.h\nfile /usr/include/term.h\nfile /usr/include/time.h\nfile /usr/include/ttyent.h\nfile /usr/include/tzfile.h\nfile /usr/include/unistd.h\nfile /usr/include/utmp.h\nfile /usr/include/vmf.h\n\nsymlink /usr/include/errno.h\ntarget sys/errno.h\n\nsymlink /usr/include/signal.h\ntarget sys/signal.h\n\nsymlink /usr/include/stdint.h\ntarget sys/stdint.h\n\nsymlink /usr/include/syslog.h\ntarget sys/syslog.h\n\n#\n# Files: /usr/lib\n#\ndir /usr/lib\nfile /usr/lib/crt0.o\nfile /usr/lib/libc.a\nfile /usr/lib/libm.a\nfile /usr/lib/libcurses.a\nfile /usr/lib/libgpanel.a\nfile /usr/lib/libreadline.a\nfile /usr/lib/libtermlib.a\nfile /usr/lib/libwiznet.a\nfile /usr/lib/retroImage\n\n#\n# Files: /usr/libexec\n#\ndefault\nfilemode 0775\ndir /usr/libexec\nfile /usr/libexec/bigram\nfile /usr/libexec/code\nfile /usr/libexec/diffh\nfile /usr/libexec/getty\nfile /usr/libexec/smallc\n\n#\n# Files: /usr/share\n#\ndefault\nfilemode 0444\ndir /usr/share\ndir /usr/share/calendar\ndir /usr/share/dict\ndir /usr/share/misc\ndir /usr/share/zoneinfo\ndir /usr/share/zoneinfo/Australia\ndir /usr/share/zoneinfo/Canada\ndir /usr/share/zoneinfo/SystemV\ndir /usr/share/zoneinfo/US\nfile /usr/share/calendar/calendar.birthday\nfile /usr/share/calendar/calendar.christian\nfile /usr/share/calendar/calendar.computer\nfile /usr/share/calendar/calendar.history\nfile /usr/share/calendar/calendar.holiday\nfile /usr/share/calendar/calendar.judaic\nfile /usr/share/calendar/calendar.music\nfile /usr/share/calendar/calendar.usholiday\nfile /usr/share/misc/emg.keys\nfile /usr/share/misc/re.help\nfile /usr/share/dict/words\nfile /usr/share/misc/lib.b\nfile /usr/share/misc/more.help\nfile /usr/share/misc/termcap\nmode 0444\nfile /usr/share/misc/yaccpar\nfile /usr/share/zoneinfo/Australia/North\nfile /usr/share/zoneinfo/Australia/NSW\nfile /usr/share/zoneinfo/Australia/Queensland\nfile /usr/share/zoneinfo/Australia/South\nfile /usr/share/zoneinfo/Australia/Tasmania\nfile /usr/share/zoneinfo/Australia/Victoria\nfile /usr/share/zoneinfo/Australia/West\nfile /usr/share/zoneinfo/Canada/Atlantic\nfile /usr/share/zoneinfo/Canada/Central\nfile /usr/share/zoneinfo/Canada/Eastern\nfile /usr/share/zoneinfo/Canada/Mountain\nfile /usr/share/zoneinfo/Canada/Newfoundland\nfile /usr/share/zoneinfo/Canada/Pacific\nfile /usr/share/zoneinfo/Canada/Yukon\nfile /usr/share/zoneinfo/CET\nfile /usr/share/zoneinfo/CST6CDT\nfile /usr/share/zoneinfo/EET\nfile /usr/share/zoneinfo/EST\nfile /usr/share/zoneinfo/EST5EDT\nfile /usr/share/zoneinfo/GMT-12\nfile /usr/share/zoneinfo/GMT-11\nfile /usr/share/zoneinfo/GMT-10\nfile /usr/share/zoneinfo/GMT-9\nfile /usr/share/zoneinfo/GMT-8\nfile /usr/share/zoneinfo/GMT-7\nfile /usr/share/zoneinfo/GMT-6\nfile /usr/share/zoneinfo/GMT-5\nfile /usr/share/zoneinfo/GMT-4\nfile /usr/share/zoneinfo/GMT-3\nfile /usr/share/zoneinfo/GMT-2\nfile /usr/share/zoneinfo/GMT-1\nfile /usr/share/zoneinfo/GMT\nfile /usr/share/zoneinfo/GMT+1\nfile /usr/share/zoneinfo/GMT+2\nfile /usr/share/zoneinfo/GMT+3\nfile /usr/share/zoneinfo/GMT+4\nfile /usr/share/zoneinfo/GMT+5\nfile /usr/share/zoneinfo/GMT+6\nfile /usr/share/zoneinfo/GMT+7\nfile /usr/share/zoneinfo/GMT+8\nfile /usr/share/zoneinfo/GMT+9\nfile /usr/share/zoneinfo/GMT+10\nfile /usr/share/zoneinfo/GMT+11\nfile /usr/share/zoneinfo/GMT+12\nfile /usr/share/zoneinfo/GMT+13\nfile /usr/share/zoneinfo/Greenwich\nfile /usr/share/zoneinfo/HST\nfile /usr/share/zoneinfo/Japan\nfile /usr/share/zoneinfo/MST\nfile /usr/share/zoneinfo/MST7MDT\nfile /usr/share/zoneinfo/NZ\nfile /usr/share/zoneinfo/PST8PDT\nfile /usr/share/zoneinfo/Singapore\nfile /usr/share/zoneinfo/SystemV/AST4\nfile /usr/share/zoneinfo/SystemV/AST4ADT\nfile /usr/share/zoneinfo/SystemV/CST6\nfile /usr/share/zoneinfo/SystemV/CST6CDT\nfile /usr/share/zoneinfo/SystemV/EST5\nfile /usr/share/zoneinfo/SystemV/EST5EDT\nfile /usr/share/zoneinfo/SystemV/HST10\nfile /usr/share/zoneinfo/SystemV/MST7\nfile /usr/share/zoneinfo/SystemV/MST7MDT\nfile /usr/share/zoneinfo/SystemV/PST8\nfile /usr/share/zoneinfo/SystemV/PST8PDT\nfile /usr/share/zoneinfo/SystemV/YST9\nfile /usr/share/zoneinfo/SystemV/YST9YDT\nfile /usr/share/zoneinfo/Turkey\nfile /usr/share/zoneinfo/UCT\nfile /usr/share/zoneinfo/Universal\nfile /usr/share/zoneinfo/US/Arizona\nfile /usr/share/zoneinfo/US/Central\nfile /usr/share/zoneinfo/US/Eastern\nfile /usr/share/zoneinfo/US/East-Indiana\nfile /usr/share/zoneinfo/US/Hawaii\nfile /usr/share/zoneinfo/US/Mountain\nfile /usr/share/zoneinfo/US/Pacific\nfile /usr/share/zoneinfo/US/Pacific-New\nfile /usr/share/zoneinfo/US/Yukon\nfile /usr/share/zoneinfo/UTC\nfile /usr/share/zoneinfo/WET\nfile /usr/share/zoneinfo/W-SU\n\n#\n# Files: /usr/share/examples/asm\n#\ndefault\nfilemode 0664\ndir /usr/share/examples\ndir /usr/share/examples/asm\nfile /usr/share/examples/asm/Makefile\nfile /usr/share/examples/asm/ashello.S\nfile /usr/share/examples/asm/echo.S\n\n#\n# Files: /usr/share/examples/basic\n#\ndir /usr/share/examples/basic\nfile /usr/share/examples/basic/blkjack.bas\nfile /usr/share/examples/basic/hilow.bas\nfile /usr/share/examples/basic/stars.bas\n\n#\n# Files: /usr/share/examples/forth\n#\ndir /usr/share/examples/forth\nfile /usr/share/examples/forth/fact.fth\n\n#\n# Files: /usr/share/examples/scheme\n#\ndir /usr/share/examples/scheme\nfile /usr/share/examples/scheme/prime.scm\n\n#\n# Files: /usr/share/examples/c\n#\ndir /usr/share/examples/c\nfile /usr/share/examples/c/Makefile\nfile /usr/share/examples/c/adc.c\nfile /usr/share/examples/c/gpio.c\nfile /usr/share/examples/c/hello.c\nfile /usr/share/examples/c/lcd6.c\nfile /usr/share/examples/c/primelist.c\nfile /usr/share/examples/c/primesum.c\nfile /usr/share/examples/c/q8.c\nfile /usr/share/examples/c/rain.c\nfile /usr/share/examples/c/skeleton.c\nfile /usr/share/examples/c/stdarg.c\nfile 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  },
  {
    "path": "distrib/base/mi.home",
    "content": "#\n# Machine independent user file system manifest file.\n#\ndefault\nowner 0\ngroup 0\ndirmode 0775\nfilemode 0664\n\nfile README.txt\n"
  },
  {
    "path": "distrib/home/.gitignore",
    "content": ""
  },
  {
    "path": "distrib/home/README.txt",
    "content": "User filesystem.\n"
  },
  {
    "path": "distrib/notes/ANNOUNCEMENT.md",
    "content": "--- DiscoBSD 2.6 RELEASED ---\n\n# DiscoBSD 2.6 Released\n\nFebruary 11, 2026\n\nDiscoBSD 2.6 is released.\n\nThis is the seventh official release of DiscoBSD, the multi-platform\n2.11BSD-based Unix-like operating system for microcontrollers.\n\nDiscoBSD 2.6 offers ports to two different microcontroller platforms:\n* DiscoBSD/stm32 - STM32F4 family of 32-bit Arm Cortex-M4\n  microcontrollers from STMicroelectronics\n* DiscoBSD/pic32 - PIC32MX7 family of 32-bit MIPS32 M4K\n  microcontrollers from Microchip\n\nDiscoBSD/stm32, unique only to DiscoBSD, offers a familiar BSD\nenvironment on the many available STM32F4 development boards. \n\nDiscoBSD/pic32, inherited from RetroBSD, offers a familiar BSD\nenvironment on the many available PIC32MX7 development boards,\nas well as full use with the included VirtualMIPS PIC32 simulator.\n\nA nearly-complete development environment is included in DiscoBSD.\n\nThere are: various text editors and compilers, a MIPS assembler and\nMIPS linker, and many more programming languages in addition to C\nand asm, such as Scheme, BASIC, Forth, RetroForth, lex, yacc, and TCL.\nExamples are provided in the file system at /usr/share/examples.\n\nAs a descendant of 2.11BSD, DiscoBSD inherits its strong BSD heritage.\nThe userland is powerful, full-featured, and comfortable to competent\nUNIX users, as it is derived from the rich 4.3BSD-Tahoe userland, modern\nimplementations of classic utilities, and improvements along the way.\n\nInstall, build, and debug instructions can be found in the README files.\n\n\n## Significant Changes and Improvements\n\n### New Features in this Release\n\n* Kernel source tree follows 4.4BSD hierarchy, to facilitate future ports.\n* Separate out console and {,k}mem drivers to be machine-independent.\n* Refresh of kernel compile Configs and Makefiles for pic32 and stm32.\n* Many improvements and cleanup of sysctl(8) and kernel-side sysctl code.\n* KNF style(9) and ANSI cleanup in kernel, ports, and userland.\n* Clarity, bugfixes, and improvements in documentation.\n\n### Filesystem\n\n* Hard link uptime(1) to w(1); uptime(1) now enabled.\n* Properly symlink /etc/localtime with DiscoBSD zone files.\n* Update libc bzero(3) to take a size_t, not unsigned int or long.\n* FD_ZERO(2) in libc now uses memset(3) instead of bzero(3).\n* Many instances in tree of replacing bzero(3) with memset(3).\n\n### Build System\n\nContinuing the overhaul of the build system.\n* Rename kconfig(8) back to config(8), in line with all BSDs.\n* 4.4BSD names for kernel files locore.S, conf.c, and sig_machdep.c.\n* Both BSD make and GNU make are fully supported.\n* FreeBSD's version of BSD make requires `MAKESYSPATH` set.\n* Speed up in imaging SD card with DiscoBSD file system.\n* Speed up in `make release`, up to 5x faster.\n* Releases now include ANNOUNCEMENT.md, maintained in tree.\n* Add back many SCCS version tags from 2.11BSD.\n\n### DiscoBSD/stm32 Specific Improvements\n\n* Support for STM32F413H-DISCO development board.\n* Extensions to HAL library for the Memory Protection Unit (MPU).\n* MPU sysctls for Enabled, num of Regions, and CTRL register.\n* Add sysctl(8) support to read and display MPU information.\n* Clean structure for SDIO GPIO pins; extensible to new boards.\n* Separate nulldev() into nullopen(), nullclose(), and nullstop().\n\n### DiscoBSD/pic32 Specific Improvements\n\n* Refactor and normalize kernel compile options with stm32.\n* Consolidate compiler tools and paths under pic32/conf/compiler.mk.\n* Separate nulldev() into nullopen(), nullclose(), and nullstop().\n\n### Documentation, Bugfixes, and Corrections\n\n* Documentation to set up a Linux host development environment.\n* Releases are documented in ANNOUNCEMENT.md, maintained in tree.\n* Steady improvements and corrections in documentation.\n* Manual page fixes and improvements.\n\n\n## Host Development Environment\n\nWhile DiscoBSD is primarily developed and tested on OpenBSD,\nLinux and FreeBSD are also supported as host environments.\n\nThese host development environments have been tested:\n\n### OpenBSD 7.6\n* Host compiler Clang 16.0.6\n* Host compiler GCC 11.2.0\n* Host compiler Clang 17.0.6\n* BSD make and GNU make\n* DiscoBSD/stm32\n  * Custom port of arm-none-eabi-gcc 12.2.0 (rmprofile)\n  * OpenBSD package of arm-none-eabi-binutils 2.40\n  * Custom port of arm-none-eabi-gdb 12.1\n  * OpenBSD package of OpenOCD 0.11.0\n  * Custom port of ST-Link 1.8.0\n* DiscoBSD/pic32\n  * Custom port of mips-elf-gcc 12.2.0\n  * Custom port of mips-elf-binutils 2.40\n\n### Ubuntu 24.04 (Zorin OS 18 Core)\n* Host compiler GCC 13.2.0\n* Host compiler Clang 18.1.3\n* BSD make and GNU make\n* DiscoBSD/stm32\n  * arm-none-eabi-gcc 13.2.1\n  * arm-none-eabi-binutils 2.42\n* DiscoBSD/pic32\n  * Untested\n\n### Ubuntu 23.04\n* Host compiler GCC 12.3.0\n* Host compiler Clang 15.0.7\n* BSD make and GNU make\n* DiscoBSD/stm32\n  * arm-none-eabi-gcc 12.2.1\n  * arm-none-eabi-binutils 2.39\n* DiscoBSD/pic32\n  * Untested\n\n### FreeBSD 13.2\n* Host compiler GCC 12.2.0\n* Host compiler Clang 14.0.5\n* BSD make (with MAKESYSPATH set) and GNU make\n* DiscoBSD/stm32\n  * arm-none-eabi-gcc 10.3.1 (gcc-arm-embedded)\n  * arm-none-eabi-binutils 2.40\n* DiscoBSD/pic32\n  * Untested\n\n\n## Release Build Environment\n\nDiscoBSD distribution releases are cross-built on OpenBSD.\n\nThe release build environment is configured as below:\n\n### OpenBSD 7.6\n* Host compiler Clang 16.0.6\n* BSD make\n* DiscoBSD/stm32\n  * Custom port of arm-none-eabi-gcc 12.2.0 (rmprofile)\n  * OpenBSD package of arm-none-eabi-binutils 2.40\n* DiscoBSD/pic32\n  * Custom port of mips-elf-gcc 12.2.0\n  * Custom port of mips-elf-binutils 2.40\n\n\n## Developers and Contributors this Release\n* @chettrick\n\n## Full Changelog\nhttps://github.com/chettrick/discobsd/compare/DISCOBSD_2_5...DISCOBSD_2_6\n"
  },
  {
    "path": "distrib/pic32/.gitignore",
    "content": "*.img\n_manifest\n"
  },
  {
    "path": "distrib/pic32/README.md",
    "content": "# DiscoBSD/pic32 - 2.11BSD-based OS for PIC32MX7 MIPS MCUs\n\n## Currently supported hardware\n\n * [Fubarino SD][1] board.\n * [Olimex Duinomite][2], [Duinomite-Mini][3], [Duinomite-Mega][4] and\n   [Duinomite-eMega][5] boards.\n * [Olimex Pinguino-Micro][6] board with PIC32MX795F512H microcontroller.\n * [Maximite][7] and [Colour Maximite][8] computers.\n * [Majenko SDXL][9] board.\n * [4D Systems Picadillo-35T][10] board.\n * [MikroElektronika MultiMedia Board][11] for PIC32MX7.\n * [chipKIT Max32][12] board with SD card shield.\n * [chipKIT WF32][13] board with 2.4\" LCD TFT display shield.\n * [Sparkfun UBW32][14] board with SD card slot.\n * [Microchip Explorer 16][15] board,\n   with PIC32 CAN-USB plug-in module and SD & MMC pictail.\n * [Microchip PIC32 USB][16] or [Ethernet Starter Kit][17],\n   with I/O Expansion board and SD & MMC pictail.\n * [Pontech Quick240][18] Quick Universal Industrial Control Kard\n   system based on the chipKIT platform.\n\n[1]: https://www.fubarino.org/sd/\n[2]: https://www.olimex.com/Products/Duino/Duinomite/DUINOMITE/\n[3]: https://www.olimex.com/Products/Duino/Duinomite/DUINOMITE-MINI/\n[4]: https://www.olimex.com/Products/Duino/Duinomite/DUINOMITE-MEGA/\n[5]: https://www.olimex.com/Products/Duino/Duinomite/DUINOMITE-eMEGA/\n[6]: https://www.olimex.com/Products/Duino/PIC32/PIC32-RETROBSD/\n[7]: https://geoffg.net/MonoMaximite.html\n[8]: https://geoffg.net/OriginalColourMaximite.html\n[9]: https://wiki.kewl.org/boards:sdxl\n[10]: https://resources.4dsystems.com.au/datasheets/legacy/Picadillo-35T_datasheet_R_1_5.pdf\n[11]: https://web.archive.org/web/20160815090501/http://www.mikroe.com/multimedia/pic32mx7/\n[12]: https://chipkit.net/wiki/index.php?title=chipKIT_Max32\n[13]: https://chipkit.net/wiki/index.php?title=chipKIT_WF32\n[14]: https://www.schmalzhaus.com/UBW32/\n[15]: https://www.microchip.com/en-us/development-tool/dm240001\n[16]: https://www.microchip.com/en-us/development-tool/dm320003-2\n[17]: https://www.microchip.com/en-us/development-tool/dm320004\n[18]: https://quick240.com\n\n## Build\n\nA few packages are required to compile everything from source.\nUnder Ubuntu installation can be done by the commands:\n\n```sh\n$ apt install bison byacc flex git groff-base libbsd-dev\n$ apt install libelf-dev libfuse-dev sudo unzip zip\n```\nIf a mips-elf-gcc compiler package is not available from the host distribution,\nthen the compiler toolchain must be built following [these instructions][19].\n\n[19]: https://web.archive.org/web/20200126100825/http://retrobsd.org/wiki/doku.php/doc/toolchain-mips\n\nThe desired filesystem size and swap area size can be changed, as required.\nDefault is:\n```Makefile\nFS_MBYTES   = 200\nU_MBYTES    = 200\nSWAP_MBYTES = 2\n```\nTo compile the kernel and build a filesystem image, run:\n\n```sh\n$ make MACHINE=pic32 MACHINE_ARCH=mips distribution\n```\n\nA resulting root filesystem image is in the file `sdcard.img`.\nKernel files are named `unix.hex` and are in target board subdirectories.\n\n### Filesystem image\n\nThe file system image `sdcard.img` needs to be imaged onto an SD card.\n\nOn Windows host systems use a disk imaging utility such as [Rufus][20].\n\nOn Unix-like host systems with `dd` run:\n```sh\n$ dd bs=1M if=sdcard.img of=/path/to/SD/card\n```\n\nThe target `installfs` can be used to image the SD card on Unix-like systems.\nProvide the path to the SD card via the command line:\n```sh\n$ make MACHINE=pic32 SDCARD=/path/to/SD/card installfs\n```\n\n[20]: https://github.com/pbatard/rufus\n\n### Install kernel\n\nThe kernel image must be written to the PIC32 flash memory.\nThe specific procedure depends on the target development board.\n\n#### PIC32-RETROBSD board:\nUse the [pic32prog][21] utility and a USB cable to install the kernel:\n\n```sh\n$ pic32prog sys/arch/pic32/compile/PINGUINO_MICRO/unix.hex\n```\n\n#### Max32 board:\nUse the [pic32prog][21] utility and a USB cable to install the kernel:\n\n```sh\n$ pic32prog -d /dev/ttyUSB0 sys/arch/pic32/compile/MAX32/unix.hex\n```\n\n#### UBW32 board:\nUse the [pic32prog][21] utility and a USB cable to install the kernel:\n\n```sh\n$ pic32prog sys/arch/pic32/compile/UBW32/unix.hex\n```\n\n#### Maximite:\nUse the bootload program for Windows, download links are available here:\nhttps://geoffg.net/MonoMaximite.html#Downloads\n\n#### Explorer 16 board:\nThere is an auxiliary PIC18 chip on the Explorer 16 board, which can be\nused as a built-in programmer device.  A PICkit 2 adapter is needed to\ninstall the required firmware, as described in [this article][22] in the\nsection \"Hack #2: Lose the PICkit 2, Save $35\".\nThis should be done only once.\n\nThen, use the [pic32prog][21] utility and a USB cable to install the kernel:\n\n``` sh\n$ pic32prog sys/arch/pic32/compile/EXPLORER16/unix.hex\n```\n\n#### PIC32 Starter Kit:\nUse the PICkit 2 adapter and software to install a boot loader from the file\n[starter-kit/bootloader.hex][23] in the [pic32-usb-bootloader][24] repository.\nThis should be done only once.\n\nThen, use the [pic32prog][21] utility and a USB cable to install the kernel:\n\n```sh\n$ pic32prog sys/arch/pic32/compile/STARTER_KIT/unix.hex\n```\n\n[21]: https://github.com/majenkotech/pic32prog-autotools/archive/refs/tags/2.1.57.zip\n[22]: https://web.archive.org/web/20160506100841/http://www.paintyourdragon.com/?p=51\n[23]: https://github.com/sergev/pic32-usb-bootloader/blob/master/starter-kit/bootloader.hex\n[24]: https://github.com/sergev/pic32-usb-bootloader\n\n## Simulator\n\nUse the VirtualMIPS MIPS32 simulator to develop and debug DiscoBSD/pic32\nwithout the need for a hardware development board.\nBy default, the simulator is configured to imitate a Max32 board.\nTo build it:\n\n```sh\n$ cd tools/virtualmips\n$ make\n```\n\nRun it:\n\n```sh\n$ ./pic32\n```\n\nConfiguration of the simulated board is stored in the file `pic32_max32.conf`.\n"
  },
  {
    "path": "distrib/pic32/md.pic32",
    "content": "#\n# Machine dependent PIC32 root file system manifest file.\n#\ndefault\nowner 0\ngroup 0\ndirmode 0775\nfilemode 0664\n\n#\n# Directories.\n#\ndir /bin\ndir /dev\ndir /etc\ndir /sbin\ndir /tmp\ndir /usr\ndir /home\n\n#\n# Files: /usr/bin\n#\ndefault\nfilemode 0775\ndir /usr/bin\nfile /usr/bin/adb\n# XXX file /usr/bin/adc-demo\n\n#\n# Files: /usr/include\n#\ndefault\nfilemode 0664\ndir /usr/include\ndir /usr/include/machine\nfile /usr/include/machine/_float.h\nfile /usr/include/machine/cpu.h\nfile /usr/include/machine/debug.h\nfile /usr/include/machine/elf_machdep.h\nfile /usr/include/machine/frame.h\nfile /usr/include/machine/io.h\nfile /usr/include/machine/limits.h\nfile /usr/include/machine/machparam.h\nfile /usr/include/machine/pic32mx.h\nfile /usr/include/machine/setjmp.h\nfile /usr/include/machine/signal.h\nfile /usr/include/machine/types.h\n\n#\n# Files: /usr/libexec\n#\ndefault\nfilemode 0775\ndir /usr/libexec\nfile /usr/libexec/smlrc\n\n#\n# Files: /usr/share/man\n#\ndefault\ndirmode 0775\ndir /usr/share/man\ndir /usr/share/man/cat1\n\n#\n# Single pages\n#\nfile /usr/share/man/cat1/adb.0\n"
  },
  {
    "path": "distrib/stm32/.gitignore",
    "content": "*.img\n_manifest\n"
  },
  {
    "path": "distrib/stm32/README.md",
    "content": "# DiscoBSD/stm32 - 2.11BSD-based OS for Arm Cortex-M4 MCUs\n\n## Currently supported hardware\n\n * [WeAct Studio STM32F405RGT6 Core board][1]\n * [STMicroelectronics NUCLEO-F411RE][2]\n * [STMicroelectronics STM32F412G-DISCO][3]\n * [WeAct Studio STM32F412RET6 Core board][1]\n * [STMicroelectronics STM32F413H-DISCO][4]\n * [STMicroelectronics NUCLEO-F446RE][5]\n * [WeAct Studio STM32F446RET6 Core board][1]\n * [STMicroelectronics STM32F469I-DISCO][6]\n * [STMicroelectronics STM32F4DISCOVERY][7]\n * [DevEBox STM32F407VET6 STM32F4VE][8]\n\n[1]: https://github.com/WeActStudio/WeActStudio.STM32F4_64Pin_CoreBoard\n[2]: https://www.st.com/en/evaluation-tools/nucleo-f411re.html\n[3]: https://www.st.com/en/evaluation-tools/32f412gdiscovery.html\n[4]: https://www.st.com/en/evaluation-tools/32f413hdiscovery.html\n[5]: https://www.st.com/en/evaluation-tools/nucleo-f446re.html\n[6]: https://www.st.com/en/evaluation-tools/32f469idiscovery.html\n[7]: https://www.st.com/en/evaluation-tools/stm32f4discovery.html\n[8]: https://stm32-base.org/boards/STM32F407VET6-STM32-F4VE-V2.0.html\n\n## DiscoBSD/stm32 Up and Running\n\nThe file system image `sdcard.img` needs to be imaged onto an SD card.\n\nOn Windows host systems use a disk imaging utility such as [Rufus][20].\n\nOn Unix-like host systems with `dd` run:\n  ```sh\n    $ dd bs=1M if=sdcard.img of=/path/to/SD/card\n  ```\n\nThe target `installfs` can be used to image the SD card on Unix-like systems.\nProvide the path to the SD card via the command line:\n  ```sh\n    $ make SDCARD=/path/to/SD/card installfs\n  ```\n\nThe board-specific kernel `unix` must be loaded into the MCU's flash memory.\nFormats are ELF `unix.elf`, binary `unix.bin`, and Intel HEX `unix.hex`.\n\nOn Windows host systems use [STM32CubeProgrammer][21] for flash programming.\n\nOn Unix-like host systems use `st-flash` from the [stlink-org project][22] to\nload the binary-formatted kernel `unix.bin` into flash memory at 0x08000000.\n  ```sh\n    $ st-flash --reset write unix.bin 0x08000000\n  ```\n\n[20]: https://github.com/pbatard/rufus\n[21]: https://www.st.com/en/development-tools/stm32cubeprog.html\n[22]: https://github.com/stlink-org/stlink\n\n## Logging in to DiscoBSD\n\nFirst, connect to the development board via the serial port.\nThe STM32 Disco and Nucleo boards offer a USB VCP serial port.\n  ```sh\n    $ cu -l /dev/cuaU0 -s 115200\n  ```\nOther systems may use serial port utilities such as `screen`, `minicom`,\n`putty`, or `teraterm`.\n\nLog in to DiscoBSD with user `root` and a blank password.\n\nShutdown DiscoBSD with:\n  ```sh\n    $ shutdown -h now\n  ```\n`halt` and `reboot` also bring down the system.\n\n## Building the DiscoBSD/stm32 kernel and operating system on a Unix-like host\n  ```sh\n    $ make distribution\n  ```\n\nThe kernel (for the F412GDISCO board) can be built independently by:\n  ```sh\n    $ cd sys/arch/stm32/compile/F412GDISCO\n    $ make\n  ```\nNote: Building the kernel requires the `tools/config` config utility.\n\n## Debugging DiscoBSD/stm32 on a development board via OpenOCD and GDB\n  ```sh\n    $ make BOARD=F412GDISCO ocd\n  ```\n\nIn a separate terminal, run `gdb` with:\n  ```sh\n    $ make BOARD=F412GDISCO gdb-ocd\n  ```\n\nRunning `make help` lists targets to debug DiscoBSD/stm32 with OpenOCD and GDB.\n"
  },
  {
    "path": "distrib/stm32/md.stm32",
    "content": "#\n# Machine dependent STM32 root file system manifest file.\n#\ndefault\nowner 0\ngroup 0\ndirmode 0775\nfilemode 0664\n\n#\n# Directories.\n#\ndir /bin\ndir /dev\ndir /etc\ndir /sbin\ndir /tmp\ndir /usr\ndir /home\n\n#\n# Files: /usr/bin\n#\ndefault\nfilemode 0775\ndir /usr/bin\nfile /usr/bin/lex\n\n#\n# Files: /usr/include\n#\ndefault\nfilemode 0664\ndir /usr/include\ndir /usr/include/machine\nfile /usr/include/machine/_float.h\nfile /usr/include/machine/cpu.h\nfile /usr/include/machine/debug.h\nfile /usr/include/machine/elf_machdep.h\nfile /usr/include/machine/fault.h\nfile /usr/include/machine/frame.h\nfile /usr/include/machine/intr.h\nfile /usr/include/machine/io.h\nfile /usr/include/machine/limits.h\nfile /usr/include/machine/machparam.h\nfile /usr/include/machine/mpuvar.h\nfile /usr/include/machine/setjmp.h\nfile /usr/include/machine/signal.h\nfile /usr/include/machine/types.h\n\n#\n# Files: /usr/share\n#\ndefault\nfilemode 0444\ndir /usr/share\ndir /usr/share/misc\nfile /usr/share/misc/ncform\n\n#\n# Files: /usr/share/examples/lex\n#\ndefault\nfilemode 0644\ndir /usr/share/examples\ndir /usr/share/examples/lex\nfile /usr/share/examples/lex/Makefile\nfile /usr/share/examples/lex/awk.lx.l\nfile /usr/share/examples/lex/example.l\nfile /usr/share/examples/lex/scan.l\nfile /usr/share/examples/lex/scanner.l\n"
  },
  {
    "path": "etc/MAKEDEV",
    "content": "#!/bin/sh -\n#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n# Device \"make\" file.  Valid arguments:\n#       std     standard devices\n#       local   configuration specific devices\n#       fd      file descriptor driver\n# Disks:\n#       sd*     flash cards SecureDigital\n# Pseudo terminals:\n#       pty*    set of 16 master and slave pseudo terminals\n\nPATH=/etc:/sbin:/usr/sbin:/bin:/usr/bin\numask 77\nfor i\ndo\ncase $i in\n\nstd)\n\tmknod console\t\tc 0 0\n\tmknod mem\t\tc 1 0\t; chmod 640 mem ; chgrp kmem mem\n\tmknod kmem\t\tc 1 1\t; chmod 640 kmem ; chgrp kmem kmem\n\tmknod null\t\tc 1 2\t; chmod 666 null\n\tmknod zero\t\tc 1 3\t; chmod 444 zero\n\tmknod tty\t\tc 2 0\t; chmod 666 tty\n \tmknod klog\t\tc 3 0\t; chmod 600 klog\n\t;;\n\nfd)\n\tumask 0\n\trm -rf fd\n\trm -f stdin stdout stderr\n\tmkdir fd\n\tchmod 755 fd\n\tmknod stdin c 4 0\n\tmknod stdout c 4 1\n\tmknod stderr c 4 2\n\teval `echo \"\" | awk '{ for (i = 0; i < 32; i++)\n\t\t\tprintf(\"mknod fd/%d c 4 %d; \",i,i); }'`\n\t;;\n\nrd)\n\tumask 2\n\trm -f rd[0123] rd[0123][abcd]\n\tmknod rd0  b 0 0\n\tmknod rd0a b 0 1\n\tmknod rd0b b 0 2\n\tmknod rd0c b 0 2\n\tmknod rd0d b 0 2\n\tmknod rd1  b 1 0\n\tmknod rd1a b 1 1\n\tmknod rd1b b 1 2\n\tmknod rd1c b 1 2\n\tmknod rd1d b 1 2\n\tmknod rd2  b 2 0\n\tmknod rd2a b 2 1\n\tmknod rd2b b 2 2\n\tmknod rd2c b 2 2\n\tmknod rd2d b 2 2\n\tmknod rd3  b 3 0\n\tmknod rd3a b 3 1\n\tmknod rd3b b 3 2\n\tmknod rd3c b 3 2\n\tmknod rd3d b 3 2\n\tchgrp operator rd[0123]\n\tchgrp operator rd[0123][abcd]\n\tchmod 640 rd[0123][abcd]\n\tchmod 640 rd[0123]\n\t;;\n\ngpio)\n\tumask 0\n\trm -f port[abcdefg] conf[abcdef]\n\tmknod\tporta\tc 5 0\n\tmknod\tportb\tc 5 1\n\tmknod\tportc\tc 5 2\n\tmknod\tportd\tc 5 3\n\tmknod\tporte\tc 5 4\n\tmknod\tportf\tc 5 5\n\tmknod\tportg\tc 5 6\n\tmknod\tconfa\tc 5 64\n\tmknod\tconfb\tc 5 65\n\tmknod\tconfc\tc 5 66\n\tmknod\tconfd\tc 5 67\n\tmknod\tconfe\tc 5 68\n\tmknod\tconff\tc 5 69\n\tmknod\tconfg\tc 5 70\n\t;;\n\nadc)\n\tumask 0\n\trm -f adc[0123456789] adc1[012345]\n\tmknod\tadc0\tc 6 0\n\tmknod\tadc1\tc 6 1\n\tmknod\tadc2\tc 6 2\n\tmknod\tadc3\tc 6 3\n\tmknod\tadc4\tc 6 4\n\tmknod\tadc5\tc 6 5\n\tmknod\tadc6\tc 6 6\n\tmknod\tadc7\tc 6 7\n\tmknod\tadc8\tc 6 8\n\tmknod\tadc9\tc 6 9\n\tmknod\tadc10\tc 6 10\n\tmknod\tadc11\tc 6 11\n\tmknod\tadc12\tc 6 12\n\tmknod\tadc13\tc 6 13\n\tmknod\tadc14\tc 6 14\n\tmknod\tadc15\tc 6 15\n\t;;\n\nspi)\n\tumask 0\n\trm -f spi[1234]\n\tmknod\tspi1\tc 7 0\n\tmknod\tspi2\tc 7 1\n\tmknod\tspi3\tc 7 2\n\tmknod\tspi4\tc 7 3\n\t;;\n\nglcd)\n\tumask 0\n\trm -f glcd0\n\tmknod glcd0\tc 8 0\n\t;;\n\noc)\n\tumask 0\n\trm -f oc[12345]\n\tmknod\toc1\tc 9 0\n\tmknod\toc2\tc 9 1\n\tmknod\toc3\tc 9 2\n\tmknod\toc4\tc 9 3\n\tmknod\toc5\tc 9 4\n\t;;\n\nlocal)\n\tsh MAKEDEV.local\n\t;;\nesac\ndone\n"
  },
  {
    "path": "etc/MAKEDEV.local",
    "content": "rm -f swap\nln ra0a swap\nchgrp kmem swap\nchmod 640 swap\n\nrm -f ttyi6 ttyd0;\tmknod ttyd0 c 3 22\nrm -f ttyi7 ttyd1;\tmknod ttyd1 c 3 23\nrm -f ttyi8 ttyd2;\tmknod ttyd2 c 3 24\nrm -f ttyi9 ttyd3;\tmknod ttyd3 c 3 25\nrm -f ttyia ttyd4;\tmknod ttyd4 c 3 26\nrm -f ttyic ttyd5;\tmknod ttyd5 c 3 156\n\nrm -f ttyh1 dir-shasta;\tmknod dir-shasta c 3 1\nrm -f ttyh6 dir-rose;\tmknod dir-rose   c 3 6\nrm -f ttyh7 dir-namsan;\tmknod dir-namsan c 3 7\nrm -f ttyid dir-ps;\tmknod dir-ps     c 3 157\nrm -f ttyie cua0;\tmknod cua0       c 3 158\nrm -f ttyif dir-scgl;\tmknod dir-scgl   c 3 159\nchown uucp dir-*\nchmod 660 dir-*\n# Cua* can't be owned by anyone real who wants to use the dialer if the mode\n# 060 below and the dialer group is to work.  Note that the uucp programs\n# must be in the dialer group.\nchown 32767 cua*\nchgrp dialer cua*\nchmod 060 cua*\n"
  },
  {
    "path": "etc/Makefile",
    "content": "#\n# Public domain - 1997/1/10 - sms\n#\n#\t@(#)Makefile\t1.0 (2.11BSD) 1997/1/10\n#\n# DESTDIR is defined here to be something which does *NOT* exist - it must be\n#  specified on the command line when doing a \"make DESTDIR=/mnt distribution\".\n#  This is aimed at avoiding overwriting the system disk's /etc files.\n#\n# Example:\n#\tmount /dev/ra1a /mnt\n#\tmake DESTDIR=/mnt distribution\n\nTOPSRC!=cd ..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nDESTDIR=\t/foobar\nRELEASEDIR=\t/foobaz\nOWN=\t\troot\nGRP=\t\twheel\n\nTZDIR=\t\t/usr/share/zoneinfo\nLOCALTIME=\tCanada/Mountain\n\nFILES=\t\tfstab gettytab group motd passwd rc rc.local shells ttys\n\nall install depend lint tags:\n\nclean:\n\trm -f *~\n\ndistribution: distribution-etc-root-var\n\ndistribution-etc-root-var: distrib-dirs\n\t${INSTALL} -d -o ${OWN} -g ${GRP} -m 755 ${DESTDIR}/dev\n\t${INSTALL} -d -o ${OWN} -g ${GRP} -m 755 ${DESTDIR}/etc\n\n\t${INSTALL} -c -o ${OWN} -g ${GRP} -m 644 ${FILES} ${DESTDIR}/etc\n\t${INSTALL} -c -o root -g wheel -m 600 shadow ${DESTDIR}/etc\n#\t${INSTALL} -c -o root -g wheel -m 600 master.passwd ${DESTDIR}/etc\n#\t${INSTALL} -c -o ${OWN} -g ${GRP} -m 555 MAKEDEV.local MAKEDEV \\\n#\t    ${DESTDIR}/dev\n\t${INSTALL} -c -o ${OWN} -g ${GRP} -m 555 MAKEDEV \\\n\t    ${DESTDIR}/etc\n\tcd root; \\\n\t\t${INSTALL} -c -o root -g wheel -m 644 dot.profile \\\n\t\t    ${DESTDIR}/root/.profile; \\\n\t\t${INSTALL} -c -o root -g wheel -m 644 dot.profile \\\n\t\t    ${DESTDIR}/.profile\n\tln -sf ${TZDIR}/${LOCALTIME} ${DESTDIR}/etc/localtime\n\t${INSTALL} -c -m 444 ${DESTDIR}/usr/share/misc/termcap \\\n\t    ${DESTDIR}/etc/termcap\n#\t${INSTALL} -c -o ${OWN} -g operator -m 664 /dev/null \\\n#\t    ${DESTDIR}/etc/dumpdates\n\t${INSTALL} -d -o ${OWN} -g ${GRP} -m 655 ${DESTDIR}/var/run\n\t${INSTALL} -c -o ${OWN} -g wheel -m 644 /dev/null \\\n\t    ${DESTDIR}/var/log/messages\n#\t${INSTALL} -c -o ${OWN} -g ${GRP} -m 644 /dev/null \\\n#\t    ${DESTDIR}/usr/adm/daemonlog\n#\t${INSTALL} -c -o ${OWN} -g operator -m 664 /dev/null \\\n#\t    ${DESTDIR}/usr/adm/shutdownlog\n#\t${INSTALL} -c -o ${OWN} -g ${GRP} -m 644 /dev/null \\\n#\t    ${DESTDIR}/var/run/utmp\n#\t${INSTALL} -c -o nobody -g ${GRP} -m 644 /dev/null \\\n#\t    ${DESTDIR}/var/db/find.codes\n#\t${INSTALL} -c -o ${OWN} -g wheel -m 644 /dev/null \\\n#\t    ${DESTDIR}/usr/adm/lastlog\n\t${INSTALL} -c -o ${OWN} -g wheel -m 644 /dev/null \\\n\t    ${DESTDIR}/var/log/wtmp\n#\t${INSTALL} -c -o uucp -g daemon -m 600 /dev/null \\\n#\t    ${DESTDIR}/usr/adm/aculog\n\nDIRS_DISTRIB=\tbin sbin dev etc var/log var/run root usr usr/bin usr/sbin \\\n\t\tusr/include usr/lib usr/libexec usr/share usr/games/lib\nMDIRS_DISTRIB=\tcat1 cat2 cat3 cat4 cat5 cat6 cat7 cat8 cat9\n\n# XXX Keep in sync with SUBDIR in sys/arch/${MACHINE}/compile/Makefile\nDIRS_RELEASE!=if [ x\"${MACHINE}\" = x\"stm32\" ] ; then \\\n\t\techo \"F405WEACTCORE F411RENUCLEO F412GDISCO F412WEACTCORE \\\n\t\t\tF413HDISCO F446RENUCLEO F446WEACTCORE F469IDISCO \\\n\t\t\tF4DISCOVERY F4VEDEVEBOX\" ; \\\n\telif [ x\"${MACHINE}\" = x\"pic32\" ] ; then \\\n\t\techo \"BAREMETAL DUINOMITE DUINOMITE_EMEGA EXPLORER16 \\\n\t\t\tFUBARINO MAX32 MAXIMITE MAXIMITE_COLOR MMB_MX7 \\\n\t\t\tPICADILLO PINGUINO_MICRO QUICK240 \\\n\t\t\tSDXL SNADPIC STARTER_KIT UBW32 WF32\" ; \\\n\telse \\\n\t\techo \"FAIL\" ; \\\n\tfi\n\n# Creates an empty DiscoBSD directory tree in DESTDIR.\ndistrib-dirs:\n\tif [ ! -d ${DESTDIR}/. ]; then \\\n\t\t${INSTALL} -d -m 755 ${DESTDIR}; \\\n\tfi\n\tfor dir in ${DIRS_DISTRIB}; do \\\n\t\tmkdir -p ${DESTDIR}/$$dir; \\\n\tdone\n\tfor dir in ${MDIRS_DISTRIB}; do \\\n\t\tmkdir -p ${DESTDIR}/usr/share/man/$$dir; \\\n\tdone\n\n# Creates and populates a DiscoBSD release directory tree in RELEASEDIR.\nrelease-dirs:\n\tif [ ! -d ${RELEASEDIR}/. ]; then \\\n\t\t${INSTALL} -d -m 755 ${RELEASEDIR}; \\\n\tfi\n\t${INSTALL} -d -m 755 ${RELEASEDIR}/${MACHINE}\n\tcd ${RELEASEDIR}/${MACHINE} && \\\n\tfor dir in ${DIRS_RELEASE}; do \\\n\t\tmkdir -p $$dir; \\\n\t\tcp ${TOPSRC}/sys/arch/${MACHINE}/compile/$$dir/unix* $$dir; \\\n\tdone\n\tcp -f ${TOPSRC}/distrib/${MACHINE}/sdcard.img ${RELEASEDIR}/${MACHINE}\n\tcp -f ${TOPSRC}/distrib/${MACHINE}/README.md ${RELEASEDIR}/${MACHINE}\n\tcp -f ${TOPSRC}/distrib/notes/ANNOUNCEMENT.md ${RELEASEDIR}\n\tcp -f ${TOPSRC}/README.md ${RELEASEDIR}\n\nrelease: release-dirs\n\tcd ${RELEASEDIR} && \\\n\ttar czvf DiscoBSD_${OSRev}_${MACHINE}.tar.gz ${MACHINE} && \\\n\tzip -r DiscoBSD_${OSRev}_${MACHINE}.zip ${MACHINE}\n\n.PHONY:\tall distribution distribution-etc-root-var \\\n\tdistrib-dirs release-dirs release clean\n"
  },
  {
    "path": "etc/fstab",
    "content": "/dev/sd0a\t/\tufs\trw,async\t1\t1\n/dev/sd0c\t/home\tufs\trw,async\t1\t2\n"
  },
  {
    "path": "etc/gettytab",
    "content": "# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n#\t@(#)gettytab\t5.7.2 (2.11BSD GTE) 1997/3/28\n#\n#\n# Most of the table entries here are just copies of the\n# old getty table, it is by no means certain, or even likely,\n# then any of them are optimal for any purpose whatever.\n# Nor is it likely that more than a couple are even correct\n#\n\n#\n# The default gettytab entry, used to set defaults for all other\n# entries, and in cases where getty is called with no table name\n#\ndefault:\\\n\t:ap:im=\\r\\n\\r\\n2.11 BSD UNIX (%h) (%t)\\r\\n\\r\\r\\n\\r:sp#1200:\n\n#\n# Fixed speed entries\n#\n#\tThe \"std.NNN\" names are known to the special case\n#\tportselector code in getty, however they can\n#\tbe assigned to any table desired.\n#\tThe \"NNN-baud\" names are known to the special case\n#\tautobaud code in getty, and likewise can\n#\tbe assigned to any table desired (hopefully the same speed).\n#\na|std.50|50-baud:\\\n\t:sp#50:\nb|std.75|75-baud:\\\n\t:ep:sp#75:ht:nl:\n1|std.150|150-baud:\\\n\t:ep:sp#150:ht:nl:lm=\\E\\72\\6\\6\\17login\\72 :\nc|std.300|300-baud:\\\n\t:sp#300:\nd|std.600|600-baud:\\\n\t:sp#600:\nf|std.1200|1200-baud:\\\n\t:sp#1200:\n6|std.2400|2400-baud:\\\n\t:sp#2400:ht:\n7|std.4800|4800-baud:\\\n\t:sp#4800:ht:\n2|std.9600|9600-baud:\\\n\t:sp#9600:\ng|std.19200|19200-baud:\\\n\t:sp#19200:\nh|std.38400|38400-baud:\\\n\t:sp#38400:\ni|std.57600|57600-baud:\\\n\t:sp#57600:\nj|std.115200|115200-baud:\\\n\t:sp#115200:\nk|std.230400|230400-baud:\\\n\t:sp#230400:\nl|std.460800|460800-baud:\\\n\t:sp#460800:\nm|std.500000|500000-baud:\\\n        :sp#500000:\nn|std.576000|576000-baud:\\\n        :sp#576000:\no|std.921600|921600-baud:\\\n        :sp#921600:\np|std.1000000|1000000-baud:\\\n        :sp#1000000:\nq|std.1152000|1152000-baud:\\\n        :sp#1152000:\nr|std.1500000|1500000-baud:\\\n        :sp#1500000:\ns|std.2000000|2000000-baud:\\\n        :sp#2000000:\nt|std.2500000|2500000-baud:\\\n        :sp#2500000:\nu|std.3000000|3000000-baud:\\\n        :sp#3000000:\nv|std.3500000|3500000-baud:\\\n        :sp#3500000:\nw|std.4000000|4000000-baud:\\\n        :sp#4000000:\nx|std.default|default-baud:\\\n    :sp#0:\n\n\n#\n# Hardware flow control lines\n#\nt9600-hf:hf:sp#9600\nt19200-hf:hf:sp#19200\nt38400-hf:hf:sp#38400\n\n#\n# Dial in rotary tables, speed selection via 'break'\n#\n0|d300|Dial-300:\\\n\t:nx=d1200:sp#300:\nd1200|Dial-1200:\\\n\t:nx=d150:sp#1200:\nd150|Dial-150:\\\n\t:nx=d110:lm@:tc=150-baud:\nd110|Dial-110:\\\n\t:nx=d300:tc=300-baud:\n\n#\n# Odd special case terminals\n#\n-|tty33|asr33|Pity the poor user of this beast:\\\n\t:tc=110-baud:\n\n4|Console|Console Decwriter II:\\\n\t:rw:tc=300-baud:\n\ne|Console-1200|Console Decwriter III:\\\n\t:rw:tc=1200-baud:\n\nl|lsi chess terminal:\\\n\t:sp#300:\n\nX|Xwindow|X window system:\\\n\t:rw:sp#9600:\n\n#\n# Fast dialup terminals, 2400/1200/300 rotary (can start either way)\n#\nD2400|Fast-Dial-2400:\\\n\t:nx=D1200:tc=2400-baud:\n3|D1200|Fast-Dial-1200:\\\n\t:nx=D300:tc=1200-baud:\n5|D300|Fast-Dial-300:\\\n\t:nx=D2400:tc=300-baud:\n\n#\n# Wierdo special case for fast crt's with hardcopy devices\n#\n8|T9600|CRT with hardcopy:\\\n\t:nx=T300:tc=9600-baud:\n9|T300|CRT with hardcopy (300):\\\n\t:nx=T9600:tc=300-baud:\n\n#\n# Plugboard, and misc other terminals\n#\np|P9600|Plugboard-9600:\\\n\t:nx=P300:tc=9600-baud:\nq|P300|Plugboard-300:\\\n\t:nx=P1200:tc=300-baud:\nr|P1200|Plugboard-1200:\\\n\t:nx=P9600:tc=1200-baud:\n\n#\n# XXXX Port selector\n#\ns|DSW|Port Selector:\\\n\t:ps:sp#2400:\n\n#\n# Auto-baud speed detect entry for Micom 600.\n# Special code in getty will switch this out\n# to one of the NNN-baud entries.\n#\nA|Auto-baud:\\\n\t:ab:sp#2400:f0#040:\n"
  },
  {
    "path": "etc/group",
    "content": "wheel:*:0:root\ndaemon:*:1:daemon\nkmem:*:2:\nsys:*:3:\ntty:*:4:\noperator:*:5:\nstaff:*:10:\nbin:*:20:\nguest:*:31:\ningres:*:74:\n"
  },
  {
    "path": "etc/motd",
    "content": "DiscoBSD ?.? (UNKNOWN)\n\nWelcome to DiscoBSD.\n\n"
  },
  {
    "path": "etc/passwd",
    "content": "root:5:0:1:The Man:/root:/bin/sh\ndaemon:*:1:1:The devil himself:/root:/bin/sh\nsys:*:4:2:Operating System:/tmp:nologin\noperator:*:2:5:System &:/operator:/bin/sh\nbin:*:3:20:Binaries Commands and Source:/root:/bin/sh\nnobody:*:32767:31:Nobody:/nonexistent:/bin/sh\nuucp:*:66:1:UNIX-to-UNIX Copy:/spool/uucppublic:/usr/bin/uucico\n"
  },
  {
    "path": "etc/rc",
    "content": "#!/bin/sh\nHOME=/; export HOME\nPATH=/sbin:/bin:/usr/sbin:/usr/bin; export PATH\nexec >/dev/console 2>&1\n\nif test \"$1\" != \"autoboot\"; then\n    #\n    # Switch from single-user to multi-user mode.\n    #\n    echo\n\n    # Halt the processor.\n    #reboot -l -h\n    exit 0\nfi\n\n#\n# Entering multiuser mode: check filesystems\n#\n# This will *only* work if fsck can do your root file system\n# without a temporary file, and if the root file system is\n# checked alone in a pass by itself -- be careful!  This can\n# *seriously* mess you up.\n#\necho \"Automatic boot in progress: starting file system checks.\"\n\nfsck -p\ncase $? in\n0)\n    # Filesystems are clean\n    ;;\n2)\n    echo \"--- Critical errors detected: run fsck to repair manually\"\n    exit 1 ;;\n4)\n    # Root filesystem modified: NO SYNC!\n    echo \"--- Errors repaired, rebooting...\"\n    reboot -n ;;\n8)\n    echo \"--- Filesystem check failed... help!\"\n    exit 1 ;;\n12)\n    echo \"--- Interrupted by user\"\n    exit 1 ;;\n*)\n    echo \"--- Unknown error in fsck\"\n    exit 1 ;;\nesac\n\nhostname \"name.my.domain\"\n\n#\n# First umount everything in case the system is going back into multiuser\n# mode.  If the system is being booted for the first time nothing is mounted\n# except the root filesystem and umount ignores attempts to unmount /.\n#\numount -a\n\n#\n# Now mount everything mentioned in /etc/fstab *except* filesystems with the\n# 'na' (noauto) option.\n#\nmount -a\n\nrm -f /etc/nologin\n\n# Patch /etc/motd.\necho -n \"Updating motd...\"\nif [ ! -f /etc/motd ]; then\n    echo \"\" >/etc/motd && chmod 664 /etc/motd && chown root.wheel /etc/motd\nfi\nT=/tmp/_motd\nsysctl -n kern.version | sed 1q >$T\nsed -n '/^$/,$p' </etc/motd >>$T\ncmp -s $T /etc/motd || cp $T /etc/motd\nrm -f $T\necho \"done\"\n\necho -n \"Starting daemons:\"\nupdate && echo -n \"update\"\ncron && echo -n \"cron\"\necho\n\n#/etc/rc.local\n\ndate\nexit 0\n"
  },
  {
    "path": "etc/rc.local",
    "content": "#! /bin/sh -\n# site-specific startup actions, daemons\n"
  },
  {
    "path": "etc/root/dot.profile",
    "content": "echo 'erase ^?, kill ^U, intr ^C'\nstty dec\nPATH=/sbin:/usr/sbin:/bin:/usr/bin\nexport PATH\nHOME=/\nexport HOME\nexport TERM\n"
  },
  {
    "path": "etc/shadow",
    "content": "root:ro46DZg1ViGBs:0:1:The Man:/root:/bin/sh\ndaemon:*:1:1:The devil himself:/root:/bin/sh\nsys:*:4:2:Operating System:/tmp:nologin\noperator:*:2:5:System &:/operator:/bin/sh\nbin:*:3:20:Binaries Commands and Source:/root:/bin/sh\nnobody:*:32767:31:Nobody:/nonexistent:/bin/sh\nuucp:*:66:1:UNIX-to-UNIX Copy:/spool/uucppublic:/usr/bin/uucico\n"
  },
  {
    "path": "etc/shells",
    "content": "# List of acceptable shells for chsh/passwd -s\n# Ftpd will not allow users to connect who do not have one of these shells\n#\n/bin/sh\n/bin/csh\n"
  },
  {
    "path": "etc/syslog.conf",
    "content": "local7.debug\t\t\t\t\t\t/dev/null\n*.crit;*.err;kern.debug;auth.notice,local7.none\t\t/dev/console\n\n*.err;auth.notice;*.info;kern.debug;local3,local7,mail,daemon,lpr.none\t/usr/adm/messages\n\ncron.debug\t\t\t\t\t/usr/adm/cron\nlpr.debug\t\t\t\t\t/usr/adm/lpd-errs\nmail.debug\t\t\t\t\t/usr/spool/mqueue/syslog\nmark.debug;daemon.debug\t\t\t\t/usr/adm/daemonlog\nuser.debug\t\t\t\t\t/usr/adm/debuglog\n\n*.alert;kern.err\t\t\t\toperator,root\n\n*.emerg\t\t\t\t\t\t*\n"
  },
  {
    "path": "etc/ttys",
    "content": "#\n# name\tgetty\t\t\t\t\ttype\tstatus\t\tcomments\n#\nconsole\t\"/usr/libexec/getty std.default\"\txterm\ton secure\t#special\n\n# Enable some of these for additional logins.  Do NOT enable the same one as the\n# console port, or strange things will happen.  You can turn off the console port\n# if you would rather use the getty on the real tty - it's up to you.\n\ntty0\t\"/usr/libexec/getty std.default\"\txterm\toff secure\ntty1\t\"/usr/libexec/getty std.default\"\txterm\toff secure\ntty2\t\"/usr/libexec/getty std.default\"\txterm\toff secure\ntty3\t\"/usr/libexec/getty std.default\"\txterm\toff secure\ntty4\t\"/usr/libexec/getty std.default\"\txterm\toff secure\ntty5\t\"/usr/libexec/getty std.default\"\txterm\toff secure\nttyUSB0\t\"/usr/libexec/getty std.default\"\txterm\toff secure\n"
  },
  {
    "path": "games/Makefile",
    "content": "#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\nTOPSRC!=cd ..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nSUBDIR          = adventure atc backgammon battlestar boggle btlgammon \\\n                  caesar cribbage fortune hangman mille monop pom pig quiz \\\n                  robots rogue sail snake trek \\\n                  banner aclock arithmetic bcd factor fish morse \\\n                  number ppt wump primes rain worm worms canfield\n\nall:            $(SUBDIR)\n\n$(SUBDIR):      FRC\n\t\t$(MAKE) -C $@ $(MFLAGS)\n\nFRC:\n\ninstall:\n\t\t-for i in $(SUBDIR); do \\\n\t\t\t${MAKE} -C $$i $(MFLAGS) DESTDIR=$(DESTDIR) install; done\n\nclean:\n\t\trm -f a.out core *.s *.o *.dis *.elf\n\t\t-for i in $(SUBDIR); do ${MAKE} -C $$i $(MFLAGS) clean; done\n"
  },
  {
    "path": "games/hunt/Makefile",
    "content": "#\n#  Hunt\n#  Copyright (c) 1985 Conrad C. Huang, Gregory S. Couch, Kenneth C.R.C. Arnold\n#  San Francisco, California\n#\n#  Copyright (c) 1985 Regents of the University of California.\n#  All rights reserved.  The Berkeley software License Agreement\n#  specifies the terms and conditions for redistribution.\n#\nHDR=\t\thunt.h\nDSRC=\t\tanswer.c driver.c draw.c execute.c expl.c makemaze.c \\\n\t\tshots.c terminal.c extern.c pathname.c\nDOBJ=\t\tanswer.o driver.o draw.o execute.o expl.o makemaze.o \\\n\t\tshots.o terminal.o extern.o\nPSRC=\t\thunt.c connect.c playit.c pathname.c\nPOBJ=\t\thunt.o connect.o playit.o\n\n#\n# Flags are:\n#\tDEBUG\tDon't trust everything in the code\n#\tINTERNET\tUse the Internet domain IPC instead of UNIX domain\n#\tBROADCAST\tUse internet broadcasting code when looking for driver\n#\tOLDIPC\t\tUse 4.1a internet system calls (must also define\n#\t\t\tINTERNET but not BROADCAST)\n#\tRANDOM\tInclude doors which disperse shots randomly\n#\tREFLECT\tInclude diagonal walls that reflect shots\n#\tMONITOR\tInclude code for watching the game from the sidelines\n#\tOOZE\tInclude slime shots\n#\tFLY\tMake people fly when walls regenerate under them\n#\tSTART_FLYING\tPlayers enter flying (FLY must also be defined)\n#\tVOLCANO\tInclude occasional large slime explosions\n#\n# NOTE: if you change the domain (INTERNET vs UNIX) then \"make newdomain\"\n#\nDEFS=\t\t-I. -DBROADCAST -DRANDOM -DREFLECT -DMONITOR -DINTERNET \\\n\t\t-DOOZE -DFLY -DVOLCANO\nCFLAGS=\t\t-O $(DEFS)\nLDFLAGS=\nSEPFLAG= -i\nPROFLAGS=\nLD=\t\t/usr/bin/ld\n.SUFFIXES:\t.uu .obj .c,v\n\n.obj.uu:\n\tuuencode $*.obj < $*.obj > $*.uu\n\n.c,v.c:\n\tco $*.c\n\nstandard:\thunt hunt.driver\n\n#\n# For testing\n#\ndebug:\thunt.dbg hunt.driver.dbg\n\nhunt.dbg:\t$(POBJ) pathname.dbg.o\n\t$(CC) ${SEPFLAG} $(LDFLAGS) -o hunt.dbg \\\n\t\t$(POBJ) pathname.dbg.o -lcurses -ltermlib\n\nhunt.driver.dbg: $(DOBJ) pathname.dbg.o\n\t$(CC) ${SEPFLAG} $(PROFLAGS) $(LDFLAGS) -o hunt.driver.dbg \\\n\t\t$(DOBJ) pathname.dbg.o\n\n#\n# Binary distribution to other sites\n#\ndistribution:\thunt.uu hunt.driver.uu README pathname.c Makefile.dist hunt.6\n\t@ln Makefile.dist makefile\n\tshar -a README makefile pathname.c hunt.uu hunt.driver.uu hunt.6\\\n\t\t> distribution\n\t@rm -f makefile hunt.uu hunt.driver.uu hunt.obj hunt.driver.obj\n\nhunt.driver.obj:\t$(DOBJ) pathname.o\n\t$(LD) -r -x -o hunt.driver.obj $(DOBJ)\n\tsymstrip hunt.driver.obj pathname.o -lcurses -ltermcap\n\nhunt.obj:\t$(POBJ) pathname.o\n\t$(LD) -r -x -o hunt.obj $(POBJ)\n\tsymstrip hunt.obj pathname.o -lcurses -ltermcap\n\n#\n# System installation\n#\ninstall:\tstandard\n\t${INSTALL} -s hunt.driver ${DESTDIR}/usr/games/lib/hunt.driver\n\t${INSTALL} -s hunt ${DESTDIR}/usr/games/hunt\n\nhunt:\t$(POBJ) pathname.o\n\t$(CC) ${SEPFLAG} $(LDFLAGS) -o hunt $(POBJ) \\\n\t\tpathname.o -lcurses -ltermlib\n\nhunt.driver:\t$(DOBJ) pathname.o\n\t$(CC) ${SEPFLAG} $(PROFLAGS) $(LDFLAGS) -o hunt.driver \\\n\t\t$(DOBJ) pathname.o\n\n#\n# Object file dependencies\n#\n$(POBJ): $(HDR)\n\n$(DOBJ): $(HDR)\n\t$(CC) $(CFLAGS) $(PROFLAGS) -c $*.c\n\npathname.dbg.o: pathname.c\n\t@echo $(CC) $(CFLAGS) -DDEBUG -c pathname.c -o pathname.dbg.o\n\t@rm -f x.c\n\t@ln pathname.c x.c\n\t@$(CC) $(CFLAGS) -DDEBUG -c x.c\n\t@mv x.o pathname.dbg.o\n\t@rm -f x.c\n\n#\n# Miscellaneous functions\n#\nlint:\t$(DSRC) $(PSRC)\n\tlint $(DEFS) -DSTANDARD $(DSRC) 2>&1 > driver.lint\n\tlint $(DEFS) -DSTANDARD $(PSRC) -lcurses 2>&1 > hunt.lint\n\ntags:\t$(DSRC) $(PSRC)\n\tctags $(DSRC) $(PSRC)\n\nnewdomain:\n\trm -f hunt.o extern.o driver.o\n\nclean:\n\trm -f hunt hunt.driver *.o tags errs\n"
  },
  {
    "path": "games/hunt/README",
    "content": "If you have an old tcp/ip you might have to turn off the BROADCAST\noption; see the Makefile.\n\nHunt is not officially supported by anyone anywhere; however, bug\nreports will be read and bug fixes/enhancements may be sent out at\nirregular intervals. Enjoy.\n\n\tucbvax!ucsfcgl!conrad\n\tucsfcgl!conrad@berkeley.edu\n"
  },
  {
    "path": "games/hunt/answer.c",
    "content": "/*\n *  Hunt\n *  Copyright (c) 1985 Conrad C. Huang, Gregory S. Couch, Kenneth C.R.C. Arnold\n *  San Francisco, California\n *\n *  Copyright (c) 1985 Regents of the University of California.\n *  All rights reserved.  The Berkeley software License Agreement\n *  specifies the terms and conditions for redistribution.\n *\n * \t@(#) answer.c 1.1 (2.11BSD) 96/7/10\n */\n\n# include\t\"hunt.h\"\n# include\t<errno.h>\n# include\t<unistd.h>\t\t/* for gethostid() */\n\n# define\tMAXPERMACH\t3\t/* Max player/monitor per machine */\n\nstatic char\tTtyname[NAMELEN];\n\nanswer()\n{\n\tregister PLAYER\t\t*pp;\n\tregister int\t\tnewsock;\n\tregister FILE\t\t*tmpfd;\n# ifdef MONITOR\n\tstatic FLAG\t\tmonitor;\n# endif MONITOR\n\tstatic char\t\tname[NAMELEN];\n\tstatic int\t\tsocklen;\n\tstatic u_long\t\tmachine;\n\tstatic u_long\t\tuid;\n\tstatic SOCKET\t\tsockstruct;\n# ifdef OLDIPC\n\textern SOCKET\t\tDaemon;\n# endif OLDIPC\n\n# ifdef INTERNET\n\tsocklen = sizeof sockstruct;\n# else\n\tsocklen = sizeof sockstruct - 1;\n# endif INTERNET\n\terrno = 0;\n# ifndef OLDIPC\n\tif ((newsock = accept(Socket, &sockstruct, &socklen)) < 0)\n# else OLDIPC\n\tif (accept(Socket, &sockstruct) < 0)\n# endif OLDIPC\n\t{\n\t\tif (errno == EINTR)\n\t\t\treturn;\n\t\tperror(\"accept\");\n\t\tcleanup(1);\n\t}\n# ifdef OLDIPC\n\tnewsock = Socket;\n\tSocket = socket(SOCK_STREAM, 0, (struct sockaddr *) &Daemon,\n\t\tSO_ACCEPTCONN);\n\tif (Socket < 0) {\n\t\tperror(\"new accept socket\");\n\t\tcleanup(1);\n\t}\n\tSock_mask = (1 << Socket);\n\tFds_mask |= Sock_mask;\n\tif (Socket >= Num_fds)\n\t\tNum_fds = Socket + 1;\n# endif OLDIPC\n\n\ttmpfd = fdopen(newsock, \"w\");\n\n# ifdef INTERNET\n\tmachine = ntohl(((struct sockaddr_in *) &sockstruct)->sin_addr.s_addr);\n# else INTERNET\n\tif (machine == 0)\n\t\tmachine = gethostid();\n# endif INTERNET\n\t(void) putw(getpid(), tmpfd);\n\t(void) read(newsock, (char *) &uid, sizeof uid);\n\tuid = ntohl(uid);\n\t(void) read(newsock, name, NAMELEN);\n\t(void) read(newsock, Ttyname, NAMELEN);\n# ifdef MONITOR\n\t(void) read(newsock, (char *) &monitor, sizeof monitor);\n# endif MONITOR\n\n\tif (reached_limit(machine)) {\n\t\tsocklen = 0;\n\t\t(void) write(newsock, (char *) &socklen, sizeof socklen);\n\t\t(void) close(newsock);\n# ifdef OLDIPC\n\t\tFds_mask &= ~(1 << newsock);\n# endif OLDIPC\n\t\treturn;\n\t}\n\n# ifdef MONITOR\n\tif (monitor)\n\t\tif (End_monitor < &Monitor[MAXMON])\n\t\t\tpp = End_monitor++;\n\t\telse {\n\t\t\tsocklen = 0;\n\t\t\t(void) write(newsock, (char *) &socklen,\n\t\t\t\tsizeof socklen);\n\t\t\t(void) close(newsock);\n\t\t\treturn;\n\t\t}\n\telse\n# endif MONITOR\n\t\tif (End_player < &Player[MAXPL])\n\t\t\tpp = End_player++;\n\t\telse {\n\t\t\tsocklen = 0;\n\t\t\t(void) write(newsock, (char *) &socklen,\n\t\t\t\tsizeof socklen);\n\t\t\t(void) close(newsock);\n\t\t\treturn;\n\t\t}\n\n\tpp->p_ident = get_ident(machine, uid, name);\n\tpp->p_output = tmpfd;\n\tpp->p_death[0] = '\\0';\n\tpp->p_fd = newsock;\n\tpp->p_mask = (1 << pp->p_fd);\n# ifndef OLDIPC\n\tFds_mask |= pp->p_mask;\n\tif (pp->p_fd >= Num_fds)\n\t\tNum_fds = pp->p_fd + 1;\n# endif OLDIPC\n\n\tpp->p_y = 0;\n\tpp->p_x = 0;\n\n# ifdef MONITOR\n\tif (monitor)\n\t\tstmonitor(pp);\n\telse\n# endif MONITOR\n\t\tstplayer(pp);\n}\n\n# ifdef MONITOR\nstmonitor(pp)\nregister PLAYER\t*pp;\n{\n\tregister int\tline;\n\tregister PLAYER\t*npp;\n\n\tbcopy((char *) Maze, (char *) pp->p_maze, sizeof Maze);\n\n\tdrawmaze(pp);\n\n\t(void) sprintf(Buf, \"%5.5s%c%-10.10s\", \" \", stat_char(pp),\n\t\tpp->p_ident->i_name);\n\tline = STAT_MON_ROW + 1 + (pp - Monitor);\n\tfor (npp = Player; npp < End_player; npp++) {\n\t\tcgoto(npp, line, STAT_NAME_COL);\n\t\toutstr(npp, Buf, STAT_NAME_LEN);\n\t}\n\tfor (npp = Monitor; npp < End_monitor; npp++) {\n\t\tcgoto(npp, line, STAT_NAME_COL);\n\t\toutstr(npp, Buf, STAT_NAME_LEN);\n\t}\n\n\tsendcom(pp, REFRESH);\n\tsendcom(pp, READY, 0);\n\t(void) fflush(pp->p_output);\n}\n# endif MONITOR\n\nstplayer(newpp)\nregister PLAYER\t*newpp;\n{\n\tregister int\tx, y;\n\tregister PLAYER\t*pp;\n\n\tNplayer++;\n\n\tfor (y = 0; y < UBOUND; y++)\n\t\tfor (x = 0; x < WIDTH; x++)\n\t\t\tnewpp->p_maze[y][x] = Maze[y][x];\n\tfor (     ; y < DBOUND; y++) {\n\t\tfor (x = 0; x < LBOUND; x++)\n\t\t\tnewpp->p_maze[y][x] = Maze[y][x];\n\t\tfor (     ; x < RBOUND; x++)\n\t\t\tnewpp->p_maze[y][x] = SPACE;\n\t\tfor (     ; x < WIDTH;  x++)\n\t\t\tnewpp->p_maze[y][x] = Maze[y][x];\n\t}\n\tfor (     ; y < HEIGHT; y++)\n\t\tfor (x = 0; x < WIDTH; x++)\n\t\t\tnewpp->p_maze[y][x] = Maze[y][x];\n\n\tdo {\n\t\tx = rand_num(WIDTH - 1) + 1;\n\t\ty = rand_num(HEIGHT - 1) + 1;\n\t} while (Maze[y][x] != SPACE);\n\tnewpp->p_over = SPACE;\n\tnewpp->p_x = x;\n\tnewpp->p_y = y;\n\tnewpp->p_undershot = FALSE;\n\n# ifdef\tSTART_FLYING\n\t/* This is only for debugging */\n\tnewpp->p_flying = rand_num(20);\n\tnewpp->p_flyx = 2 * rand_num(6) - 5;\n\tnewpp->p_flyy = 2 * rand_num(6) - 5;\n\tnewpp->p_face = FLYER;\n# else START_FLYING\n\tnewpp->p_flying = -1;\n\trand_face(newpp);\n# endif START_FLYING\n\tnewpp->p_damage = 0;\n\tnewpp->p_damcap = MAXDAM;\n\tnewpp->p_nchar = 0;\n\tnewpp->p_ncount = 0;\n\tnewpp->p_nexec = 0;\n\tnewpp->p_ammo = ISHOTS;\n\tnewpp->p_scan = -1;\n\tnewpp->p_cloak = CLOAKLEN;\n\tnewpp->p_ncshot = 0;\n\n\tdo {\n\t\tx = rand_num(WIDTH - 1) + 1;\n\t\ty = rand_num(HEIGHT - 1) + 1;\n\t} while (Maze[y][x] != SPACE);\n\tMaze[y][x] = GMINE;\n# ifdef MONITOR\n\tfor (pp = Monitor; pp < End_monitor; pp++)\n\t\tcheck(pp, y, x);\n# endif MONITOR\n\n\tdo {\n\t\tx = rand_num(WIDTH - 1) + 1;\n\t\ty = rand_num(HEIGHT - 1) + 1;\n\t} while (Maze[y][x] != SPACE);\n\tMaze[y][x] = MINE;\n# ifdef MONITOR\n\tfor (pp = Monitor; pp < End_monitor; pp++)\n\t\tcheck(pp, y, x);\n# endif MONITOR\n\n\t(void) sprintf(Buf, \"%5.2f%c%-10.10s\", newpp->p_ident->i_score,\n\t\tstat_char(newpp), newpp->p_ident->i_name);\n\ty = STAT_PLAY_ROW + 1 + (newpp - Player);\n\tfor (pp = Player; pp < End_player; pp++) {\n\t\tif (pp != newpp) {\n\t\t\tchar\tsmallbuf[10];\n\n\t\t\tpp->p_ammo += NSHOTS;\n\t\t\tnewpp->p_ammo += NSHOTS;\n\t\t\tcgoto(pp, y, STAT_NAME_COL);\n\t\t\toutstr(pp, Buf, STAT_NAME_LEN);\n\t\t\t(void) sprintf(smallbuf, \"%3d\", pp->p_ammo);\n\t\t\tcgoto(pp, STAT_AMMO_ROW, STAT_VALUE_COL);\n\t\t\toutstr(pp, smallbuf, 3);\n\t\t}\n\t}\n# ifdef MONITOR\n\tfor (pp = Monitor; pp < End_monitor; pp++) {\n\t\tcgoto(pp, y, STAT_NAME_COL);\n\t\toutstr(pp, Buf, STAT_NAME_LEN);\n\t}\n# endif MONITOR\n\n\tdrawmaze(newpp);\n\tdrawplayer(newpp, TRUE);\n\tlook(newpp);\n# ifdef START_FLYING\n\t/* Make sure that the position you enter in will be erased */\n\tshowexpl(newpp->p_y, newpp->p_x, FLYER);\n# endif START_FLYING\n\tsendcom(newpp, REFRESH);\n\tsendcom(newpp, READY, 0);\n\t(void) fflush(newpp->p_output);\n}\n\n/*\n * rand_face:\n *\tGive the player a random facing direction\n */\nrand_face(pp)\nregister PLAYER\t*pp;\n{\n\tswitch (rand_num(4)) {\n\t  case 0:\n\t\tpp->p_face = LEFTS;\n\t\tbreak;\n\t  case 1:\n\t\tpp->p_face = RIGHT;\n\t\tbreak;\n\t  case 2:\n\t\tpp->p_face = BELOW;\n\t\tbreak;\n\t  case 3:\n\t\tpp->p_face = ABOVE;\n\t\tbreak;\n\t}\n}\n\n/*\n * get_ident:\n *\tGet the score structure of a player\n */\nIDENT *\nget_ident(machine, uid, name)\nu_long\tmachine;\nu_long\tuid;\nchar\t*name;\n{\n\tregister IDENT\t*ip;\n\tstatic IDENT\tpunt;\n\n\tfor (ip = Scores; ip != NULL; ip = ip->i_next)\n\t\tif (ip->i_machine == machine && ip->i_uid == uid &&\n\t\t    strncmp(ip->i_name, name, NAMELEN) == 0)\n\t\t\tbreak;\n\n\tif (ip != NULL) {\n\t\tip->i_entries++;\n\t\tip->i_score = ip->i_kills / (double) ip->i_entries;\n\t}\n\telse {\n\t\tip = (IDENT *) malloc(sizeof (IDENT));\n\t\tif (ip == NULL) {\n\t\t\t/* Fourth down, time to punt */\n\t\t\tip = &punt;\n\t\t}\n\t\tip->i_machine = machine;\n\t\tip->i_uid = uid;\n\t\tstrncpy(ip->i_name, name, NAMELEN);\n\t\tip->i_kills = 0;\n\t\tip->i_entries = 1;\n\t\tip->i_score = 0;\n\t\tip->i_next = Scores;\n\t\tScores = ip;\n\t}\n\n\treturn ip;\n}\n\n/*\n * reached_limit:\n *\tReturns whether the limit of x persons per machine has been reached\n */\nreached_limit(machine)\nu_long\tmachine;\n{\n\tregister PLAYER\t*pp;\n\tregister int\tcount;\n\n\tcount = 0;\n\tfor (pp = Player; pp < End_player; pp++)\n\t\tif (pp->p_ident->i_machine == machine)\n\t\t\tcount++;\n\tfor (pp = Monitor; pp < End_monitor; pp++)\n\t\tif (pp->p_ident->i_machine == machine)\n\t\t\tcount++;\n\treturn count >= MAXPERMACH;\n}\n"
  },
  {
    "path": "games/hunt/connect.c",
    "content": "/*\n *  Hunt\n *  Copyright (c) 1985 Conrad C. Huang, Gregory S. Couch, Kenneth C.R.C. Arnold\n *  San Francisco, California\n *\n *  Copyright (c) 1985 Regents of the University of California.\n *  All rights reserved.  The Berkeley software License Agreement\n *  specifies the terms and conditions for redistribution.\n */\n\n# include\t\"hunt.h\"\n# include\t<signal.h>\n\ndo_connect(name)\nchar\t*name;\n{\n\tstatic long\tuid;\n\textern char\t*ttyname();\n\n\tuid = htonl(getuid());\n\t(void) write(Socket, (char *) &uid, sizeof uid);\n\t(void) write(Socket, name, NAMELEN);\n\t(void) strcpy(Buf, ttyname(fileno(stderr)));\n\t(void) write(Socket, Buf, NAMELEN);\n# ifdef MONITOR\n\t(void) write(Socket, (char *) &Am_monitor, sizeof Am_monitor);\n# endif MONITOR\n}\n"
  },
  {
    "path": "games/hunt/draw.c",
    "content": "/*\n *  Hunt\n *  Copyright (c) 1985 Conrad C. Huang, Gregory S. Couch, Kenneth C.R.C. Arnold\n *  San Francisco, California\n *\n *  Copyright (c) 1985 Regents of the University of California.\n *  All rights reserved.  The Berkeley software License Agreement\n *  specifies the terms and conditions for redistribution.\n */\n\n# include\t\"hunt.h\"\n\ndrawmaze(pp)\nregister PLAYER\t*pp;\n{\n\tregister int\tx;\n\tregister char\t*sp;\n\tregister int\ty;\n\tregister char\t*endp;\n\n\tclrscr(pp);\n\toutstr(pp, pp->p_maze[0], WIDTH);\n\tfor (y = 1; y < HEIGHT - 1; y++) {\n\t\tendp = &pp->p_maze[y][WIDTH];\n\t\tfor (x = 0, sp = pp->p_maze[y]; sp < endp; x++, sp++)\n\t\t\tif (*sp != SPACE) {\n\t\t\t\tcgoto(pp, y, x);\n\t\t\t\tif (pp->p_x == x && pp->p_y == y)\n\t\t\t\t\toutch(pp, translate(*sp));\n\t\t\t\telse\n\t\t\t\t\toutch(pp, *sp);\n\t\t\t}\n\t}\n\tcgoto(pp, HEIGHT - 1, 0);\n\toutstr(pp, pp->p_maze[HEIGHT - 1], WIDTH);\n\tdrawstatus(pp);\n}\n\n/*\n * drawstatus - put up the status lines (this assumes the screen\n *\t\tsize is 80x24 with the maze being 64x24)\n */\ndrawstatus(pp)\nregister PLAYER\t*pp;\n{\n\tregister int\ti;\n\tregister PLAYER\t*np;\n\n\t(void) sprintf(Buf, \"%-13.13s\", pp->p_ident->i_name);\n\tcgoto(pp, STAT_NAME_ROW, STAT_LABEL_COL);\n\toutstr(pp, Buf, 13);\n\n\tcgoto(pp, STAT_AMMO_ROW, STAT_LABEL_COL);\n\toutstr(pp, \"Ammo:\", 5);\n\t(void) sprintf(Buf, \"%3d\", pp->p_ammo);\n\tcgoto(pp, STAT_AMMO_ROW, STAT_VALUE_COL);\n\toutstr(pp, Buf, 3);\n\n\tcgoto(pp, STAT_CLOAK_ROW, STAT_LABEL_COL);\n\toutstr(pp, \"Cloak:\", 6);\n\tcgoto(pp, STAT_CLOAK_ROW, STAT_VALUE_COL);\n\toutstr(pp, (pp->p_cloak < 0) ? \"   \" : \" on\", 3);\n\n\tcgoto(pp, STAT_SCAN_ROW, STAT_LABEL_COL);\n\toutstr(pp, \"Scan:\", 5);\n\tcgoto(pp, STAT_SCAN_ROW, STAT_VALUE_COL);\n\toutstr(pp, (pp->p_scan < 0) ? \"   \" : \" on\", 3);\n\n\tcgoto(pp, STAT_GUN_ROW, STAT_LABEL_COL);\n\toutstr(pp, \"Gun:\", 4);\n\tcgoto(pp, STAT_GUN_ROW, STAT_VALUE_COL);\n\toutstr(pp, (pp->p_ncshot < MAXNCSHOT) ? \" ok\" : \"   \", 3);\n\n\tcgoto(pp, STAT_DAM_ROW, STAT_LABEL_COL);\n\toutstr(pp, \"Damage:\", 7);\n\t(void) sprintf(Buf, \"%2d/%2d\", pp->p_damage, pp->p_damcap);\n\tcgoto(pp, STAT_DAM_ROW, STAT_VALUE_COL);\n\toutstr(pp, Buf, 5);\n\n\tcgoto(pp, STAT_KILL_ROW, STAT_LABEL_COL);\n\toutstr(pp, \"Kills:\", 6);\n\t(void) sprintf(Buf, \"%3d\", (pp->p_damcap - MAXDAM) / 2);\n\tcgoto(pp, STAT_KILL_ROW, STAT_VALUE_COL);\n\toutstr(pp, Buf, 3);\n\n\tcgoto(pp, STAT_PLAY_ROW, STAT_LABEL_COL);\n\toutstr(pp, \"Player:\", 7);\n\tfor (i = STAT_PLAY_ROW + 1, np = Player; np < End_player; np++) {\n\t\t(void) sprintf(Buf, \"%5.2f%c%-10.10s\", np->p_ident->i_score,\n\t\t\tstat_char(np), np->p_ident->i_name);\n\t\tcgoto(pp, i++, STAT_NAME_COL);\n\t\toutstr(pp, Buf, STAT_NAME_LEN);\n\t}\n\n# ifdef MONITOR\n\tcgoto(pp, STAT_MON_ROW, STAT_LABEL_COL);\n\toutstr(pp, \"Monitor:\", 8);\n\tfor (i = STAT_MON_ROW + 1, np = Monitor; np < End_monitor; np++) {\n\t\t(void) sprintf(Buf, \"%5.5s %-10.10s\", \" \", np->p_ident->i_name);\n\t\tcgoto(pp, i++, STAT_NAME_COL);\n\t\toutstr(pp, Buf, STAT_NAME_LEN);\n\t}\n# endif MONITOR\n}\n\n# ifndef CPUHOG\nlook(pp)\nregister PLAYER\t*pp;\n{\n\tregister int\tx, y;\n\n\tx = pp->p_x;\n\ty = pp->p_y;\n\n\tcheck(pp, y - 1, x - 1);\n\tcheck(pp, y - 1, x    );\n\tcheck(pp, y - 1, x + 1);\n\tcheck(pp, y    , x - 1);\n\tcheck(pp, y    , x    );\n\tcheck(pp, y    , x + 1);\n\tcheck(pp, y + 1, x - 1);\n\tcheck(pp, y + 1, x    );\n\tcheck(pp, y + 1, x + 1);\n\n\tswitch (pp->p_face) {\n\t  case LEFTS:\n\t\tsee(pp, LEFTS);\n\t\tsee(pp, ABOVE);\n\t\tsee(pp, BELOW);\n\t\tbreak;\n\t  case RIGHT:\n\t\tsee(pp, RIGHT);\n\t\tsee(pp, ABOVE);\n\t\tsee(pp, BELOW);\n\t\tbreak;\n\t  case ABOVE:\n\t\tsee(pp, ABOVE);\n\t\tsee(pp, LEFTS);\n\t\tsee(pp, RIGHT);\n\t\tbreak;\n\t  case BELOW:\n\t\tsee(pp, BELOW);\n\t\tsee(pp, LEFTS);\n\t\tsee(pp, RIGHT);\n\t\tbreak;\n# ifdef FLY\n\t  case FLYER:\n\t\tbreak;\n# endif FLY\n\t}\n\tcgoto(pp, y, x);\n}\n\nsee(pp, face)\nregister PLAYER\t*pp;\nint\t\tface;\n{\n\tregister char\t*sp;\n\tregister int\ty, x, i, cnt;\n\n\tx = pp->p_x;\n\ty = pp->p_y;\n\n\tswitch (face) {\n\t  case LEFTS:\n\t\tsp = &Maze[y][x];\n\t\tfor (i = 0; See_over[*--sp]; i++)\n\t\t\tcontinue;\n\n\t\tif (i == 0)\n\t\t\tbreak;\n\n\t\tcnt = i;\n\t\tx = pp->p_x - 1;\n\t\t--y;\n\t\twhile (i--)\n\t\t\tcheck(pp, y, --x);\n\t\ti = cnt;\n\t\tx = pp->p_x - 1;\n\t\t++y;\n\t\twhile (i--)\n\t\t\tcheck(pp, y, --x);\n\t\ti = cnt;\n\t\tx = pp->p_x - 1;\n\t\t++y;\n\t\twhile (i--)\n\t\t\tcheck(pp, y, --x);\n\t\tbreak;\n\t  case RIGHT:\n\t\tsp = &Maze[y][++x];\n\t\tfor (i = 0; See_over[*sp++]; i++)\n\t\t\tcontinue;\n\n\t\tif (i == 0)\n\t\t\tbreak;\n\n\t\tcnt = i;\n\t\tx = pp->p_x + 1;\n\t\t--y;\n\t\twhile (i--)\n\t\t\tcheck(pp, y, ++x);\n\t\ti = cnt;\n\t\tx = pp->p_x + 1;\n\t\t++y;\n\t\twhile (i--)\n\t\t\tcheck(pp, y, ++x);\n\t\ti = cnt;\n\t\tx = pp->p_x + 1;\n\t\t++y;\n\t\twhile (i--)\n\t\t\tcheck(pp, y, ++x);\n\t\tbreak;\n\t  case ABOVE:\n\t\tsp = &Maze[--y][x];\n\t\tif (!See_over[*sp])\n\t\t\tbreak;\n\t\tdo {\n\t\t\t--y;\n\t\t\tsp -= sizeof Maze[0];\n\t\t\tcheck(pp, y, x - 1);\n\t\t\tcheck(pp, y, x    );\n\t\t\tcheck(pp, y, x + 1);\n\t\t} while (See_over[*sp]);\n\t\tbreak;\n\t  case BELOW:\n\t\tsp = &Maze[++y][x];\n\t\tif (!See_over[*sp])\n\t\t\tbreak;\n\t\tdo {\n\t\t\ty++;\n\t\t\tsp += sizeof Maze[0];\n\t\t\tcheck(pp, y, x - 1);\n\t\t\tcheck(pp, y, x    );\n\t\t\tcheck(pp, y, x + 1);\n\t\t} while (See_over[*sp]);\n\t\tbreak;\n\t}\n}\n\n# else CPUHOG\n\nlook(pp)\nregister PLAYER\t*pp;\n{\n\tswitch (pp->p_face) {\n\t  case LEFTS:\n\t\tlookquad2(pp, pp->p_y, pp->p_x);\n\t\tlookquad3(pp, pp->p_y, pp->p_x);\n\t\tbreak;\n\t  case RIGHT:\n\t\tlookquad1(pp, pp->p_y, pp->p_x);\n\t\tlookquad4(pp, pp->p_y, pp->p_x);\n\t\tbreak;\n\t  case ABOVE:\n\t\tlookquad3(pp, pp->p_y, pp->p_x);\n\t\tlookquad4(pp, pp->p_y, pp->p_x);\n\t\tbreak;\n\t  case BELOW:\n\t\tlookquad1(pp, pp->p_y, pp->p_x);\n\t\tlookquad2(pp, pp->p_y, pp->p_x);\n\t\tbreak;\n\t}\n\tcgoto(pp, pp->p_y, pp->p_x);\n}\n# endif CPUHOG\n\ncheck(pp, y, x)\nPLAYER\t*pp;\nint\ty, x;\n{\n\tregister int\tindex;\n\tregister int\tch;\n\tregister PLAYER\t*rpp;\n\n\tindex = y * sizeof Maze[0] + x;\n\tch = ((char *) Maze)[index];\n\tif (ch != ((char *) pp->p_maze)[index]) {\n\t\trpp = pp;\n\t\tcgoto(rpp, y, x);\n\t\tif (x == rpp->p_x && y == rpp->p_y)\n\t\t\toutch(rpp, translate(ch));\n\t\telse\n\t\t\toutch(rpp, ch);\n\t\t((char *) rpp->p_maze)[index] = ch;\n\t}\n}\n\n/*\n * showstat\n *\tUpdate the status of players\n */\nshowstat(pp)\nregister PLAYER\t*pp;\n{\n\tregister PLAYER\t*np;\n\tregister int\ty;\n\tregister char\tc;\n\n\ty = STAT_PLAY_ROW + 1 + (pp - Player);\n\tc = stat_char(pp);\n# ifdef MONITOR\n\tfor (np = Monitor; np < End_monitor; np++) {\n\t\tcgoto(np, y, STAT_SCAN_COL);\n\t\toutch(np, c);\n\t}\n# endif MONITOR\n\tfor (np = Player; np < End_player; np++) {\n\t\tcgoto(np, y, STAT_SCAN_COL);\n\t\toutch(np, c);\n\t}\n}\n\n/*\n * drawplayer:\n *\tDraw the player on the screen and show him to everyone who's scanning\n *\tunless he is cloaked.\n */\ndrawplayer(pp, draw)\nPLAYER\t*pp;\nFLAG\tdraw;\n{\n\tregister PLAYER\t*newp;\n\tregister int\tx, y;\n\n\tx = pp->p_x;\n\ty = pp->p_y;\n\tMaze[y][x] = draw ? pp->p_face : pp->p_over;\n\n# ifdef MONITOR\n\tfor (newp = Monitor; newp < End_monitor; newp++)\n\t\tcheck(newp, y, x);\n# endif MONITOR\n\n\tfor (newp = Player; newp < End_player; newp++) {\n\t\tif (!draw || newp == pp) {\n\t\t\tcheck(newp, y, x);\n\t\t\tcontinue;\n\t\t}\n\t\tif (newp->p_scan == 0) {\n\t\t\tcgoto(newp, STAT_SCAN_ROW, STAT_VALUE_COL);\n\t\t\toutstr(newp, \"   \", 3);\n\t\t\tnewp->p_scan--;\n\t\t\tshowstat(newp);\n\t\t}\n\t\telse if (newp->p_scan > 0) {\n\t\t\tif (pp->p_cloak < 0)\n\t\t\t\tcheck(newp, y, x);\n\t\t\tnewp->p_scan--;\n\t\t}\n\t}\n\tif (!draw || pp->p_cloak < 0)\n\t\treturn;\n\tif (pp->p_cloak-- == 0) {\n\t\tcgoto(pp, STAT_CLOAK_ROW, STAT_VALUE_COL);\n\t\toutstr(pp, \"   \", 3);\n\t\tshowstat(pp);\n\t}\n}\n\nmessage(pp, s)\nregister PLAYER\t*pp;\nchar\t\t*s;\n{\n\tcgoto(pp, HEIGHT, 0);\n\toutstr(pp, s, strlen(s));\n\tce(pp);\n}\n\n/*\n * translate:\n *\tTurn a charcter into the right direction character if we are\n *\tlooking at the current player.\n */\ntranslate(ch)\nchar\tch;\n{\n\tswitch (ch) {\n\t  case LEFTS:\n\t\treturn '<';\n\t  case RIGHT:\n\t\treturn '>';\n\t  case ABOVE:\n\t\treturn '^';\n\t  case BELOW:\n\t\treturn 'v';\n\t}\n\treturn ch;\n}\n"
  },
  {
    "path": "games/hunt/driver.c",
    "content": "/*\n *  Hunt\n *  Copyright (c) 1985 Conrad C. Huang, Gregory S. Couch, Kenneth C.R.C. Arnold\n *  San Francisco, California\n *\n *  Copyright (c) 1985 Regents of the University of California.\n *  All rights reserved.  The Berkeley software License Agreement\n *  specifies the terms and conditions for redistribution.\n *\n * 1997/9/9 - updated to use sigprocmask (and compute the alarm mask correctly)\n */\n\n# include\t\"hunt.h\"\n# include\t<signal.h>\n# include\t<errno.h>\n# include\t<sys/ioctl.h>\n# include\t<sys/time.h>\n\n# ifndef pdp11\n# define\tRN\t(((Seed = Seed * 11109 + 13849) >> 16) & 0xffff)\n# else pdp11\n# define\tRN\t((Seed = Seed * 11109 + 13849) & 0x7fff)\n# endif pdp11\n\nint\tSeed = 0;\n\n# ifdef CONSTANT_MOVE\nstatic struct itimerval\tTiming;\n# endif CONSTANT_MOVE\n\nSOCKET\tDaemon;\n# ifdef\tINTERNET\nint\tTest_socket;\t\t/* test socket to answer datagrams */\n# define\tDAEMON_SIZE\t(sizeof Daemon)\n# else INTERNET\n# define\tDAEMON_SIZE\t(sizeof Daemon - 1)\n# endif\tINTERNET\n\n/*\n * main:\n *\tThe main program.\n */\nmain()\n{\n\tregister PLAYER\t*pp;\n\tregister int\thad_char;\n# ifdef INTERNET\n\tregister long\ttest_mask;\n\tint\t\tmsg;\n\tint\t\tnamelen;\n\tSOCKET\t\ttest;\n# endif INTERNET\n# ifdef CONSTANT_MOVE\n\tsigset_t\talarm_sigset;\n# endif CONSTANT_MOVE\n\tstatic long\tread_fds;\n\n\tinit();\n\tSock_mask = (1 << Socket);\n# ifdef INTERNET\n\ttest_mask = (1 << Test_socket);\n# endif INTERNET\n\n# ifdef CONSTANT_MOVE\n\t(void) sigemptyset(&alarm_sigset);\n\t(void) sigaddset(&alarm_sigset, SIGALRM);\n\t(void) sigprocmask(SIG_BLOCK, &alarm_sigset, NULL);\n\t(void) signal(SIGALRM, moveshots);\n# endif CONSTANT_MOVE\n\n\twhile (Nplayer > 0) {\n# ifdef CONSTANT_MOVE\n\t\t(void) sigprocmask(SIG_UNBLOCK, &alarm_sigset, NULL);\n# endif CONSTANT_MOVE\n\t\tread_fds = Fds_mask;\n\t\terrno = 0;\n# ifndef OLDIPC\n\t\twhile (select(Num_fds, &read_fds, (int *) NULL,\n\t\t    (int *) NULL, (struct timeval *) NULL) < 0)\n# else OLDIPC\n\t\twhile (select(20, &read_fds, NULL, 32767) < 0)\n# endif OLDIPC\n\t\t{\n\t\t\tif (errno != EINTR)\n\t\t\t\tperror(\"select\");\n\t\t\tif (Nplayer == 0)\n\t\t\t\tgoto out;\n\t\t\terrno = 0;\n\t\t}\n\t\tHave_inp = read_fds;\n# ifdef CONSTANT_MOVE\n\t\t(void) sigprocmask(SIG_BLOCK, &alarm_sigset, NULL);\n# endif CONSTANT_MOVE\n# ifdef INTERNET\n\t\tif (read_fds & test_mask) {\n\t\t\tnamelen = DAEMON_SIZE;\n# ifndef OLDIPC\n\t\t\t(void) recvfrom(Test_socket, (char *) &msg, sizeof msg,\n\t\t\t\t0, (struct sockaddr *) &test, &namelen);\n\t\t\t(void) sendto(Test_socket, (char *) &msg, sizeof msg,\n\t\t\t\t0, (struct sockaddr *) &test, DAEMON_SIZE);\n# else OLDIPC\n\t\t\t(void) receive(Test_socket, (struct sockaddr *) &test,\n\t\t\t\t(char *) &msg, sizeof msg);\n\t\t\t(void) send(Test_socket, (struct sockaddr *) &test,\n\t\t\t\t(char *) &msg, sizeof msg);\n# endif OLDIPC\n\t\t}\n# endif INTERNET\n\t\tfor (;;) {\n\t\t\thad_char = FALSE;\n\t\t\tfor (pp = Player; pp < End_player; pp++)\n\t\t\t\tif (havechar(pp)) {\n\t\t\t\t\texecute(pp);\n\t\t\t\t\tpp->p_nexec++;\n\t\t\t\t\thad_char++;\n\t\t\t\t}\n# ifdef MONITOR\n\t\t\tfor (pp = Monitor; pp < End_monitor; pp++)\n\t\t\t\tif (havechar(pp)) {\n\t\t\t\t\tmon_execute(pp);\n\t\t\t\t\tpp->p_nexec++;\n\t\t\t\t\thad_char++;\n\t\t\t\t}\n# endif MONITOR\n\t\t\tif (!had_char)\n\t\t\t\tbreak;\n# ifdef CONSTANT_MOVE\n\t\t\tfor (pp = Player; pp < End_player; pp++) {\n\t\t\t\tlook(pp);\n\t\t\t\tsendcom(pp, REFRESH);\n\t\t\t}\n# ifdef MONITOR\n\t\t\tfor (pp = Monitor; pp < End_monitor; pp++)\n\t\t\t\tsendcom(pp, REFRESH);\n# endif MONITOR\n# else CONSTANT_MOVE\n\t\t\tmoveshots();\n# endif CONSTANT_MOVE\n\t\t\tfor (pp = Player; pp < End_player; )\n\t\t\t\tif (pp->p_death[0] != '\\0')\n\t\t\t\t\tzap(pp, TRUE);\n\t\t\t\telse\n\t\t\t\t\tpp++;\n# ifdef MONITOR\n\t\t\tfor (pp = Monitor; pp < End_monitor; )\n\t\t\t\tif (pp->p_death[0] != '\\0')\n\t\t\t\t\tzap(pp, FALSE);\n\t\t\t\telse\n\t\t\t\t\tpp++;\n# endif MONITOR\n\t\t}\n\t\tif (read_fds & Sock_mask)\n\t\t\tanswer();\n\t\tfor (pp = Player; pp < End_player; pp++) {\n\t\t\tif (read_fds & pp->p_mask)\n\t\t\t\tsendcom(pp, READY, pp->p_nexec);\n\t\t\tpp->p_nexec = 0;\n\t\t\t(void) fflush(pp->p_output);\n\t\t}\n# ifdef MONITOR\n\t\tfor (pp = Monitor; pp < End_monitor; pp++) {\n\t\t\tif (read_fds & pp->p_mask)\n\t\t\t\tsendcom(pp, READY, pp->p_nexec);\n\t\t\tpp->p_nexec = 0;\n\t\t\t(void) fflush(pp->p_output);\n\t\t}\n# endif MONITOR\n\t}\nout:\n# ifdef\tCONSTANT_MOVE\n\tbul_alarm(0);\n# endif\tCONSTANT_MOVE\n\n# ifdef MONITOR\n\tfor (pp = Monitor; pp < End_monitor; )\n\t\tzap(pp, FALSE);\n# endif MONITOR\n\tcleanup(0);\n}\n\n/*\n * init:\n *\tInitialize the global parameters.\n */\ninit()\n{\n\tregister int\ti;\n# ifdef\tINTERNET\n\tSOCKET\t\ttest_port;\n\tauto int\tmsg;\n# endif\tINTERNET\n\tint cleanup();\n\n# ifndef DEBUG\n\t(void) ioctl(fileno(stdout), TIOCNOTTY, NULL);\n\t(void) setpgrp(getpid(), getpid());\n\t(void) signal(SIGHUP, SIG_IGN);\n\t(void) signal(SIGINT, SIG_IGN);\n\t(void) signal(SIGQUIT, SIG_IGN);\n\t(void) signal(SIGTERM, cleanup);\n# endif DEBUG\n\n\t(void) chdir(\"/usr/tmp\");\t/* just in case it core dumps */\n\t(void) signal(SIGPIPE, SIG_IGN);\n\n# ifdef\tINTERNET\n\tDaemon.sin_family = SOCK_FAMILY;\n# ifdef OLD\n\tif (gethostname(local_name, sizeof local_name) < 0) {\n\t\tperror(\"gethostname\");\n\t\texit(1);\n\t}\n\tif ((hp = gethostbyname(local_name)) == NULL) {\n\t\tfprintf(stderr, \"Unknown host %s\\n\", local_name);\n\t\texit(1);\n\t}\n\tbcopy(hp->h_addr, &(Daemon.sin_addr.s_addr), hp->h_length);\n# else\n\tDaemon.sin_addr.s_addr = INADDR_ANY;\n# endif OLD\n\tDaemon.sin_port = htons(Sock_port);\n# else INTERNET\n\tDaemon.sun_family = SOCK_FAMILY;\n\t(void) strcpy(Daemon.sun_path, Sock_name);\n# endif INTERNET\n\n# ifndef OLDIPC\n\tSocket = socket(SOCK_FAMILY, SOCK_STREAM, 0);\n# else OLDIPC\n\tSocket = socket(SOCK_STREAM, 0, (struct sockaddr *) &Daemon,\n\t\tSO_ACCEPTCONN);\n# endif OLDIPC\n# if defined(INTERNET) && !defined(OLDIPC)\n\tif (setsockopt(Socket, SOL_SOCKET, SO_USELOOPBACK, &msg, sizeof msg)<0)\n\t\tperror(\"setsockopt loopback\");\n# endif INTERNET\n# ifndef OLDIPC\n\tif (bind(Socket, (struct sockaddr *) &Daemon, DAEMON_SIZE) < 0) {\n\t\tif (errno == EADDRINUSE)\n\t\t\texit(0);\n\t\telse {\n\t\t\tperror(\"bind\");\n\t\t\tcleanup(1);\n\t\t}\n\t}\n\t(void) listen(Socket, 5);\n# endif OLDIPC\n\tFds_mask = (1 << Socket);\n\tNum_fds = Socket + 1;\n\n# ifdef INTERNET\n\ttest_port = Daemon;\n\ttest_port.sin_port = htons(Test_port);\n\n# ifndef OLDIPC\n\tTest_socket = socket(SOCK_FAMILY, SOCK_DGRAM, 0);\n\tif (bind(Test_socket, (struct sockaddr *) &test_port,\n\t    DAEMON_SIZE) < 0) {\n\t\tperror(\"bind\");\n\t\texit(1);\n\t}\n\t(void) listen(Test_socket, 5);\n# else OLDIPC\n\tTest_socket = socket(SOCK_DGRAM, 0, (struct sockaddr *) &test_port, 0);\n# endif OLDIPC\n\tFds_mask |= (1 << Test_socket);\n\tif (Test_socket > Socket)\n\t\tNum_fds = Test_socket + 1;\n# endif\tINTERNET\n\n\tSeed = getpid() + time((time_t *) NULL);\n\tmakemaze();\n\n\tfor (i = 0; i < NASCII; i++)\n\t\tSee_over[i] = TRUE;\n\tSee_over[DOOR] = FALSE;\n\tSee_over[WALL1] = FALSE;\n\tSee_over[WALL2] = FALSE;\n\tSee_over[WALL3] = FALSE;\n# ifdef REFLECT\n\tSee_over[WALL4] = FALSE;\n\tSee_over[WALL5] = FALSE;\n# endif REFLECT\n\n# ifdef CONSTANT_MOVE\n\tgetitimer(ITIMER_REAL, &Timing);\n\tTiming.it_interval.tv_sec = 0;\n\tTiming.it_interval.tv_usec = 500;\n\tTiming.it_value.tv_sec = 0;\n\tTiming.it_value.tv_usec = 0;\n\tsetitimer(ITIMER_REAL, &Timing, NULL);\n# endif CONSTANT_MOVE\n\n\tanswer();\n}\n\n# ifdef CONSTANT_MOVE\n/*\n * bul_alarm:\n *\tSet up the alarm for the bullets\n */\nbul_alarm(val)\nint\tval;\n{\n\tTiming.it_value.tv_usec = val * Timing.it_interval.tv_usec;\n\tsetitimer(ITIMER_REAL, &Timing, NULL);\n}\n# endif CONSTANT_MOVE\n\n/*\n * checkdam:\n *\tCheck the damage to the given player, and see if s/he is killed\n */\ncheckdam(ouch, gotcha, credit, amt, shot_type)\nregister PLAYER\t*ouch, *gotcha;\nregister IDENT\t*credit;\nint\t\tamt;\nchar\t\tshot_type;\n{\n\tregister char\t*cp;\n\n\tif (ouch->p_death[0] != '\\0')\n\t\treturn;\n\tif (rand_num(100) < 5) {\n\t\tmessage(ouch, \"Missed you by a hair\");\n\t\tif (gotcha != NULL)\n\t\t\tmessage(gotcha, \"Missed him\");\n\t\treturn;\n\t}\n\touch->p_damage += amt;\n\tif (ouch->p_damage <= ouch->p_damcap) {\n\t\t(void) sprintf(Buf, \"%2d\", ouch->p_damage);\n\t\tcgoto(ouch, STAT_DAM_ROW, STAT_VALUE_COL);\n\t\toutstr(ouch, Buf, 2);\n\t\treturn;\n\t}\n\n\t/* Someone DIED */\n\tswitch (shot_type) {\n\t  default:\n\t\tcp = \"Killed\";\n\t\tbreak;\n# ifdef FLY\n\t  case FALL:\n\t\tcp = \"Killed on impact\";\n\t\tbreak;\n# endif FLY\n\t  case KNIFE:\n\t\tcp = \"Stabbed to death\";\n\t\tbreak;\n\t  case SHOT:\n\t\tcp = \"Shot to death\";\n\t\tbreak;\n\t  case GRENADE:\n\t  case SATCHEL:\n\t  case BOMB:\n\t\tcp = \"Bombed\";\n\t\tbreak;\n\t  case MINE:\n\t  case GMINE:\n\t\tcp = \"Blown apart\";\n\t\tbreak;\n# ifdef\tOOZE\n\t  case SLIME:\n\t\tcp = \"Slimed\";\n\t\tbreak;\n# endif OOZE\n# ifdef\tVOLCANO\n\t  case LAVA:\n\t\tcp = \"Baked\";\n\t\tbreak;\n# endif VOLCANO\n\t}\n\tif (credit == NULL) {\n\t\t(void) sprintf(ouch->p_death, \"| %s by %s |\", cp,\n\t\t\t(shot_type == MINE || shot_type == GMINE) ?\n\t\t\t\"a mine\" : \"act of God\");\n\t\treturn;\n\t}\n\n\t(void) sprintf(ouch->p_death, \"| %s by %s |\", cp, credit->i_name);\n\n\tcredit->i_kills++;\n\tcredit->i_score = credit->i_kills / (double) credit->i_entries;\n\tif (gotcha == NULL)\n\t\treturn;\n\tgotcha->p_damcap += STABDAM;\n\tgotcha->p_damage -= STABDAM;\n\tif (gotcha->p_damage < 0)\n\t\tgotcha->p_damage = 0;\n\t(void) sprintf(Buf, \"%2d/%2d\", gotcha->p_damage, gotcha->p_damcap);\n\tcgoto(gotcha, STAT_DAM_ROW, STAT_VALUE_COL);\n\toutstr(gotcha, Buf, 5);\n\t(void) sprintf(Buf, \"%3d\", (gotcha->p_damcap - MAXDAM) / 2);\n\tcgoto(gotcha, STAT_KILL_ROW, STAT_VALUE_COL);\n\toutstr(gotcha, Buf, 3);\n\t(void) sprintf(Buf, \"%5.2f\", gotcha->p_ident->i_score);\n\tfor (ouch = Player; ouch < End_player; ouch++) {\n\t\tcgoto(ouch, STAT_PLAY_ROW + 1 + (gotcha - Player),\n\t\t\tSTAT_NAME_COL);\n\t\toutstr(ouch, Buf, 5);\n\t}\n}\n\n/*\n * zap:\n *\tKill off a player and take him out of the game.\n */\nzap(pp, was_player)\nregister PLAYER\t*pp;\nFLAG\t\twas_player;\n{\n\tregister int\ti, len;\n\tregister BULLET\t*bp;\n\tregister PLAYER\t*np;\n\tregister int\tx, y;\n\tint\t\tsavefd, savemask;\n\n\tif (was_player) {\n\t\tdrawplayer(pp, FALSE);\n\t\tNplayer--;\n\t}\n\n\tlen = strlen(pp->p_death);\t/* Display the cause of death */\n\tx = (WIDTH - len) / 2;\n\tcgoto(pp, HEIGHT / 2, x);\n\toutstr(pp, pp->p_death, len);\n\tfor (i = 1; i < len; i++)\n\t\tpp->p_death[i] = '-';\n\tpp->p_death[0] = '+';\n\tpp->p_death[len - 1] = '+';\n\tcgoto(pp, HEIGHT / 2 - 1, x);\n\toutstr(pp, pp->p_death, len);\n\tcgoto(pp, HEIGHT / 2 + 1, x);\n\toutstr(pp, pp->p_death, len);\n\tcgoto(pp, HEIGHT, 0);\n\n\tif (Nplayer == 0) {\n# ifdef CONSTANT_MOVE\n\t\tbul_alarm(0);\n# endif CONSTANT_MOVE\n\t\tcleanup(0);\n\t\t/* NOTREACHED */\n\t}\n\n\tsavefd = pp->p_fd;\n\tsavemask = pp->p_mask;\n\n# ifdef MONITOR\n\tif (was_player) {\n# endif MONITOR\n\t\tfor (bp = Bullets; bp != NULL; bp = bp->b_next) {\n\t\t\tif (bp->b_owner == pp)\n\t\t\t\tbp->b_owner = NULL;\n\t\t\tif (bp->b_x == pp->p_x && bp->b_y == pp->p_y)\n\t\t\t\tbp->b_over = SPACE;\n\t\t}\n\n\t\ti = rand_num(pp->p_ammo);\n\t\tif (i == pp->p_ammo - 1) {\n\t\t\tx = pp->p_ammo;\n\t\t\tlen = SLIME;\n\t\t}\n\t\telse if (i >= BOMBREQ) {\n\t\t\tx = BOMBREQ;\n\t\t\tlen = BOMB;\n\t\t}\n\t\telse if (i >= SSLIMEREQ) {\n\t\t\tx = SSLIMEREQ;\n\t\t\tlen = SLIME;\n\t\t}\n\t\telse if (i >= SATREQ) {\n\t\t\tx = SATREQ;\n\t\t\tlen = SATCHEL;\n\t\t}\n\t\telse if (i >= SLIMEREQ) {\n\t\t\tx = SLIMEREQ;\n\t\t\tlen = SLIME;\n\t\t}\n\t\telse if (i >= GRENREQ) {\n\t\t\tx = GRENREQ;\n\t\t\tlen = GRENADE;\n\t\t}\n\t\telse\n\t\t\tx = 0;\n\t\tif (x > 0) {\n\t\t\tadd_shot(len, pp->p_y, pp->p_x, pp->p_face, x,\n\t\t\t\t(PLAYER *) NULL, TRUE, SPACE);\n\t\t\t(void) sprintf(Buf, \"%s detonated.\",\n\t\t\t\tpp->p_ident->i_name);\n\t\t\tfor (np = Player; np < End_player; np++)\n\t\t\t\tmessage(np, Buf);\n# ifdef MONITOR\n\t\t\tfor (np = Monitor; np < End_monitor; np++)\n\t\t\t\tmessage(np, Buf);\n# endif MONITOR\n\t\t}\n\n# ifdef VOLCANO\n\t\tvolcano += pp->p_ammo - x;\n\t\tif (rand_num(100) < volcano / 50) {\n\t\t\tdo {\n\t\t\t\tx = rand_num(WIDTH / 2) + WIDTH / 4;\n\t\t\t\ty = rand_num(HEIGHT / 2) + HEIGHT / 4;\n\t\t\t} while (Maze[y][x] != SPACE);\n\t\t\tadd_shot(LAVA, y, x, LEFTS, volcano,\n\t\t\t\t(PLAYER *) NULL, TRUE, SPACE);\n\t\t\tfor (np = Player; np < End_player; np++)\n\t\t\t\tmessage(np, \"Volcano eruption.\");\n\t\t\tvolcano = 0;\n\t\t}\n# endif VOLCANO\n\n\t\tsendcom(pp, ENDWIN);\n\t\t(void) fclose(pp->p_output);\n\n\t\tEnd_player--;\n\t\tif (pp != End_player) {\n\t\t\tbcopy((char *) End_player, (char *) pp,\n\t\t\t\tsizeof (PLAYER));\n\t\t\t(void) sprintf(Buf, \"%5.2f%c%-10.10s\",\n\t\t\t\tpp->p_ident->i_score, stat_char(pp),\n\t\t\t\tpp->p_ident->i_name);\n\t\t\ti = STAT_PLAY_ROW + 1 + (pp - Player);\n\t\t\tfor (np = Player; np < End_player; np++) {\n\t\t\t\tcgoto(np, i, STAT_NAME_COL);\n\t\t\t\toutstr(np, Buf, STAT_NAME_LEN);\n\t\t\t}\n# ifdef MONITOR\n\t\t\tfor (np = Monitor; np < End_monitor; np++) {\n\t\t\t\tcgoto(np, i, STAT_NAME_COL);\n\t\t\t\toutstr(np, Buf, STAT_NAME_LEN);\n\t\t\t}\n# endif MONITOR\n\t\t}\n\n\t\t/* Erase the last player */\n\t\ti = STAT_PLAY_ROW + 1 + Nplayer;\n\t\tfor (np = Player; np < End_player; np++) {\n\t\t\tcgoto(np, i, STAT_NAME_COL);\n\t\t\tce(np);\n\t\t}\n# ifdef MONITOR\n\t\tfor (np = Monitor; np < End_monitor; np++) {\n\t\t\tcgoto(np, i, STAT_NAME_COL);\n\t\t\tce(np);\n\t\t}\n\t}\n\telse {\n\t\tsendcom(pp, ENDWIN);\n\t\t(void) putc(LAST_PLAYER, pp->p_output);\n\t\t(void) fclose(pp->p_output);\n\n\t\tEnd_monitor--;\n\t\tif (pp != End_monitor) {\n\t\t\tbcopy((char *) End_monitor, (char *) pp,\n\t\t\t\tsizeof (PLAYER));\n\t\t\t(void) sprintf(Buf, \"%5.5s %-10.10s\", \" \",\n\t\t\t\tpp->p_ident->i_name);\n\t\t\ti = STAT_MON_ROW + 1 + (pp - Player);\n\t\t\tfor (np = Player; np < End_player; np++) {\n\t\t\t\tcgoto(np, i, STAT_NAME_COL);\n\t\t\t\toutstr(np, Buf, STAT_NAME_LEN);\n\t\t\t}\n\t\t\tfor (np = Monitor; np < End_monitor; np++) {\n\t\t\t\tcgoto(np, i, STAT_NAME_COL);\n\t\t\t\toutstr(np, Buf, STAT_NAME_LEN);\n\t\t\t}\n\t\t}\n\n\t\t/* Erase the last monitor */\n\t\ti = STAT_MON_ROW + 1 + (End_monitor - Monitor);\n\t\tfor (np = Player; np < End_player; np++) {\n\t\t\tcgoto(np, i, STAT_NAME_COL);\n\t\t\tce(np);\n\t\t}\n\t\tfor (np = Monitor; np < End_monitor; np++) {\n\t\t\tcgoto(np, i, STAT_NAME_COL);\n\t\t\tce(np);\n\t\t}\n\n\t}\n# endif MONITOR\n\n\tFds_mask &= ~savemask;\n\tif (Num_fds == savefd + 1) {\n\t\tNum_fds = Socket;\n# ifdef INTERNET\n\t\tif (Test_socket > Socket)\n\t\t\tNum_fds = Test_socket;\n# endif INTERNET\n\t\tfor (np = Player; np < End_player; np++)\n\t\t\tif (np->p_fd > Num_fds)\n\t\t\t\tNum_fds = np->p_fd;\n# ifdef MONITOR\n\t\tfor (np = Monitor; np < End_monitor; np++)\n\t\t\tif (np->p_fd > Num_fds)\n\t\t\t\tNum_fds = np->p_fd;\n# endif MONITOR\n\t\tNum_fds++;\n\t}\n}\n\n/*\n * rand_num:\n *\tReturn a random number in a given range.\n */\nrand_num(range)\nint\trange;\n{\n\treturn (range == 0 ? 0 : RN % range);\n}\n\n/*\n * havechar:\n *\tCheck to see if we have any characters in the input queue; if\n *\twe do, read them, stash them away, and return TRUE; else return\n *\tFALSE.\n */\nhavechar(pp)\nregister PLAYER\t*pp;\n{\n\textern int\terrno;\n\n\tif (pp->p_ncount < pp->p_nchar)\n\t\treturn TRUE;\n\tif (!(Have_inp & pp->p_mask))\n\t\treturn FALSE;\n\tHave_inp &= ~pp->p_mask;\ncheck_again:\n\terrno = 0;\n\tif ((pp->p_nchar = read(pp->p_fd, pp->p_cbuf, sizeof pp->p_cbuf)) <= 0)\n\t{\n\t\tif (errno == EINTR)\n\t\t\tgoto check_again;\n\t\tpp->p_cbuf[0] = 'q';\n\t}\n\tpp->p_ncount = 0;\n\treturn TRUE;\n}\n\n/*\n * cleanup:\n *\tExit with the given value, cleaning up any droppings lying around\n */\ncleanup(eval)\nint\teval;\n{\n\tregister PLAYER\t*pp;\n\n\tfor (pp = Player; pp < End_player; pp++) {\n\t\tcgoto(pp, HEIGHT, 0);\n\t\tsendcom(pp, ENDWIN);\n\t\t(void) putc(LAST_PLAYER, pp->p_output);\n\t\t(void) fclose(pp->p_output);\n\t}\n# ifdef MONITOR\n\tfor (pp = Monitor; pp < End_monitor; pp++) {\n\t\tcgoto(pp, HEIGHT, 0);\n\t\tsendcom(pp, ENDWIN);\n\t\t(void) putc(LAST_PLAYER, pp->p_output);\n\t\t(void) fclose(pp->p_output);\n\t}\n# endif MONITOR\n\t(void) close(Socket);\n# ifdef AF_UNIX_HACK\n\t(void) unlink(Sock_name);\n# endif AF_UNIX_HACK\n\texit(eval);\n}\n"
  },
  {
    "path": "games/hunt/execute.c",
    "content": "/*\n *  Hunt\n *  Copyright (c) 1985 Conrad C. Huang, Gregory S. Couch, Kenneth C.R.C. Arnold\n *  San Francisco, California\n *\n *  Copyright (c) 1985 Regents of the University of California.\n *  All rights reserved.  The Berkeley software License Agreement\n *  specifies the terms and conditions for redistribution.\n */\n\n# include\t\"hunt.h\"\n\n# undef CTRL\n# define\tCTRL(x)\t('x' & 037)\n\n# ifdef MONITOR\n/*\n * mon_execute:\n *\tExecute a single monitor command\n */\nmon_execute(pp)\nregister PLAYER\t*pp;\n{\n\tregister char\tch;\n\n\tch = pp->p_cbuf[pp->p_ncount++];\n\tswitch (ch) {\n\t  case CTRL(L):\n\t\tsendcom(pp, REDRAW);\n\t\tbreak;\n\t  case 'q':\n\t\t(void) strcpy(pp->p_death, \"| Quit |\");\n\t\tbreak;\n\t}\n}\n# endif MONITOR\n\n/*\n * execute:\n *\tExecute a single command\n */\nexecute(pp)\nregister PLAYER\t*pp;\n{\n\tregister char\tch;\n\n\tch = pp->p_cbuf[pp->p_ncount++];\n\n# ifdef\tFLY\n\tif (pp->p_flying >= 0) {\n\t\tswitch (ch) {\n\t\t  case CTRL(L):\n\t\t\tsendcom(pp, REDRAW);\n\t\t\tbreak;\n\t\t  case 'q':\n\t\t\t(void) strcpy(pp->p_death, \"| Quit |\");\n\t\t\tbreak;\n\t\t}\n\t\treturn;\n\t}\n# endif\tFLY\n\n\tswitch (ch) {\n\t  case CTRL(L):\n\t\tsendcom(pp, REDRAW);\n\t\tbreak;\n\t  case 'h':\n\t\tmove(pp, LEFTS);\n\t\tbreak;\n\t  case 'H':\n\t\tface(pp, LEFTS);\n\t\tbreak;\n\t  case 'j':\n\t\tmove(pp, BELOW);\n\t\tbreak;\n\t  case 'J':\n\t\tface(pp, BELOW);\n\t\tbreak;\n\t  case 'k':\n\t\tmove(pp, ABOVE);\n\t\tbreak;\n\t  case 'K':\n\t\tface(pp, ABOVE);\n\t\tbreak;\n\t  case 'l':\n\t\tmove(pp, RIGHT);\n\t\tbreak;\n\t  case 'L':\n\t\tface(pp, RIGHT);\n\t\tbreak;\n\t  case 'f':\n\t\tfire(pp, SHOT);\n\t\tbreak;\n\t  case 'g':\n\t\tfire(pp, GRENADE);\n\t\tbreak;\n\t  case 'F':\n\t\tfire(pp, SATCHEL);\n\t\tbreak;\n\t  case 'G':\n\t\tfire(pp, BOMB);\n\t\tbreak;\n# ifdef\tOOZE\n\t  case 'o':\n\t\tfire_slime(pp, SLIMEREQ);\n\t\tbreak;\n\t  case 'O':\n\t\tfire_slime(pp, SSLIMEREQ);\n\t\tbreak;\n# endif\tOOZE\n\t  case 's':\n\t\tscan(pp);\n\t\tbreak;\n\t  case 'c':\n\t\tcloak(pp);\n\t\tbreak;\n\t  case 'q':\n\t\t(void) strcpy(pp->p_death, \"| Quit |\");\n\t\tbreak;\n\t}\n}\n\n/*\n * move:\n *\tExecute a move in the given direction\n */\nmove(pp, dir)\nregister PLAYER\t*pp;\nint\t\tdir;\n{\n\tregister PLAYER\t*newp;\n\tregister int\tx, y;\n\tregister FLAG\tmoved;\n\tregister BULLET\t*bp;\n\n\ty = pp->p_y;\n\tx = pp->p_x;\n\n\tswitch (dir) {\n\t  case LEFTS:\n\t\tx--;\n\t\tbreak;\n\t  case RIGHT:\n\t\tx++;\n\t\tbreak;\n\t  case ABOVE:\n\t\ty--;\n\t\tbreak;\n\t  case BELOW:\n\t\ty++;\n\t\tbreak;\n\t}\n\n\tmoved = FALSE;\n\tswitch (Maze[y][x]) {\n\t  case SPACE:\n# ifdef RANDOM\n\t  case DOOR:\n# endif RANDOM\n\t\tmoved = TRUE;\n\t\tbreak;\n\t  case WALL1:\n\t  case WALL2:\n\t  case WALL3:\n# ifdef REFLECT\n\t  case WALL4:\n\t  case WALL5:\n# endif REFLECT\n\t\tbreak;\n\t  case MINE:\n\t  case GMINE:\n\t\tif (dir == pp->p_face)\n\t\t\tpickup(pp, y, x, 5, Maze[y][x]);\n\t\telse if (opposite(dir, pp->p_face))\n\t\t\tpickup(pp, y, x, 95, Maze[y][x]);\n\t\telse\n\t\t\tpickup(pp, y, x, 50, Maze[y][x]);\n\t\tMaze[y][x] = SPACE;\n\t\tmoved = TRUE;\n\t\tbreak;\n\t  case SHOT:\n\t  case GRENADE:\n\t  case SATCHEL:\n\t  case BOMB:\n\t\tbp = is_bullet(y, x);\n\t\tif (bp != NULL)\n\t\t\tbp->b_expl = TRUE;\n\t\tMaze[y][x] = SPACE;\n\t\tmoved = TRUE;\n\t\tbreak;\n\t  case LEFTS:\n\t  case RIGHT:\n\t  case ABOVE:\n\t  case BELOW:\n# ifdef FLY\n\t  case FLYER:\n# endif FLY\n\t\tif (dir != pp->p_face)\n\t\t\tsendcom(pp, BELL);\n\t\telse {\n\t\t\tnewp = play_at(y, x);\n\t\t\tcheckdam(newp, pp, pp->p_ident, STABDAM, KNIFE);\n\t\t}\n\t\tbreak;\n\t}\n\tif (moved) {\n\t\tif (pp->p_ncshot > 0)\n\t\t\tif (--pp->p_ncshot == MAXNCSHOT) {\n\t\t\t\tcgoto(pp, STAT_GUN_ROW, STAT_VALUE_COL);\n\t\t\t\toutstr(pp, \" ok\", 3);\n\t\t\t}\n\t\tif (pp->p_undershot) {\n\t\t\tfixshots(pp->p_y, pp->p_x, pp->p_over);\n\t\t\tpp->p_undershot = FALSE;\n\t\t}\n\t\tdrawplayer(pp, FALSE);\n\t\tpp->p_over = Maze[y][x];\n\t\tpp->p_y = y;\n\t\tpp->p_x = x;\n\t\tdrawplayer(pp, TRUE);\n\t}\n}\n\n/*\n * face:\n *\tChange the direction the player is facing\n */\nface(pp, dir)\nregister PLAYER\t*pp;\nregister int\tdir;\n{\n\tif (pp->p_face != dir) {\n\t\tpp->p_face = dir;\n\t\tdrawplayer(pp, TRUE);\n\t}\n}\n\n/*\n * fire:\n *\tFire a shot of the given type in the given direction\n */\nfire(pp, type)\nregister PLAYER\t*pp;\nregister char\ttype;\n{\n\tregister int\treq_index;\n\tstatic int\treq[4] = { BULREQ, GRENREQ, SATREQ, BOMBREQ };\n\tstatic int\tshot_type[4] = { SHOT, GRENADE, SATCHEL, BOMB };\n\n\tif (pp == NULL)\n\t\treturn;\n\tif (pp->p_ammo == 0) {\n\t\tmessage(pp, \"No more charges.\");\n\t\treturn;\n\t}\n\tif (pp->p_ncshot > MAXNCSHOT)\n\t\treturn;\n\tif (pp->p_ncshot++ == MAXNCSHOT) {\n\t\tcgoto(pp, STAT_GUN_ROW, STAT_VALUE_COL);\n\t\toutstr(pp, \"   \", 3);\n\t}\n\tswitch (type) {\n\t  case SHOT:\n\t\treq_index = 0;\n\t\tbreak;\n\t  case GRENADE:\n\t\treq_index = 1;\n\t\tbreak;\n\t  case SATCHEL:\n\t\treq_index = 2;\n\t\tbreak;\n\t  case BOMB:\n\t\treq_index = 3;\n\t\tbreak;\n# ifdef DEBUG\n\t  default:\n\t\tmessage(pp, \"What you do!!!\");\n\t\treturn;\n# endif DEBUG\n\t}\n\twhile (pp->p_ammo < req[req_index])\n\t\treq_index--;\n\tpp->p_ammo -= req[req_index];\n\t(void) sprintf(Buf, \"%3d\", pp->p_ammo);\n\tcgoto(pp, STAT_AMMO_ROW, STAT_VALUE_COL);\n\toutstr(pp, Buf, 3);\n\n\tadd_shot(shot_type[req_index], pp->p_y, pp->p_x, pp->p_face,\n\t\treq[req_index], pp, FALSE, pp->p_face);\n\tpp->p_undershot = TRUE;\n\n\t/*\n\t * Show the object to everyone\n\t */\n\tshowexpl(pp->p_y, pp->p_x, shot_type[req_index]);\n\tfor (pp = Player; pp < End_player; pp++)\n\t\tsendcom(pp, REFRESH);\n# ifdef MONITOR\n\tfor (pp = Monitor; pp < End_monitor; pp++)\n\t\tsendcom(pp, REFRESH);\n# endif MONITOR\n}\n\n# ifdef\tOOZE\n/*\n * fire_slime:\n *\tFire a slime shot in the given direction\n */\nfire_slime(pp, req)\nregister PLAYER\t*pp;\nregister int\treq;\n{\n\tif (pp == NULL)\n\t\treturn;\n\tif (pp->p_ammo < req) {\n\t\tmessage(pp, \"Not enough charges.\");\n\t\treturn;\n\t}\n\tif (pp->p_ncshot > MAXNCSHOT)\n\t\treturn;\n\tif (pp->p_ncshot++ == MAXNCSHOT) {\n\t\tcgoto(pp, STAT_GUN_ROW, STAT_VALUE_COL);\n\t\toutstr(pp, \"   \", 3);\n\t}\n\tpp->p_ammo -= req;\n\t(void) sprintf(Buf, \"%3d\", pp->p_ammo);\n\tcgoto(pp, STAT_AMMO_ROW, STAT_VALUE_COL);\n\toutstr(pp, Buf, 3);\n\n\tadd_shot(SLIME, pp->p_y, pp->p_x, pp->p_face, req, pp, FALSE,\n\t\tpp->p_face);\n\n\t/*\n\t * Show the object to everyone\n\t */\n\tshowexpl(pp->p_y, pp->p_x, SLIME);\n\tfor (pp = Player; pp < End_player; pp++)\n\t\tsendcom(pp, REFRESH);\n# ifdef MONITOR\n\tfor (pp = Monitor; pp < End_monitor; pp++)\n\t\tsendcom(pp, REFRESH);\n# endif MONITOR\n}\n# endif\tOOZE\n\n/*\n * create_shot:\n *\tCreate a shot with the given properties\n */\nadd_shot(type, y, x, face, charge, owner, expl, over)\nint\ttype;\nint\ty, x;\nchar\tface;\nint\tcharge;\nPLAYER\t*owner;\nint\texpl;\nchar\tover;\n{\n\tregister BULLET\t*bp;\n\n# ifdef CONSTANT_MOVE\n\t/*\n\t * if there are no bullets in flight, set up the alarm\n\t */\n\n\tif (Bullets == NULL)\n\t\tbul_alarm(1);\n# endif CONSTANT_MOVE\n\n\tbp = create_shot(type, y, x, face, charge, owner,\n\t\t(owner == NULL) ? NULL : owner->p_ident, expl, over);\n\tbp->b_next = Bullets;\n\tBullets = bp;\n}\n\nBULLET *\ncreate_shot(type, y, x, face, charge, owner, score, expl, over)\nint\ttype;\nint\ty, x;\nchar\tface;\nint\tcharge;\nPLAYER\t*owner;\nIDENT\t*score;\nint\texpl;\nchar\tover;\n{\n\tregister BULLET\t*bp;\n\n\tbp = (BULLET *) malloc(sizeof (BULLET));\t/* NOSTRICT */\n\tif (bp == NULL) {\n\t\tif (owner != NULL)\n\t\t\tmessage(owner, \"Out of memory\");\n\t\treturn NULL;\n\t}\n\n\tbp->b_face = face;\n\tbp->b_x = x;\n\tbp->b_y = y;\n\tbp->b_charge = charge;\n\tbp->b_owner = owner;\n\tbp->b_score = score;\n\tbp->b_type = type;\n\tbp->b_expl = expl;\n\tbp->b_over = over;\n\tbp->b_next = NULL;\n\n\treturn bp;\n}\n\n/*\n * cloak:\n *\tTurn on or increase length of a cloak\n */\ncloak(pp)\nregister PLAYER\t*pp;\n{\n\tif (pp->p_ammo <= 0) {\n\t\tmessage(pp, \"No more charges\");\n\t\treturn;\n\t}\n\t(void) sprintf(Buf, \"%3d\", --pp->p_ammo);\n\tcgoto(pp, STAT_AMMO_ROW, STAT_VALUE_COL);\n\toutstr(pp, Buf, 3);\n\n\tpp->p_cloak += CLOAKLEN;\n\tcgoto(pp, STAT_CLOAK_ROW, STAT_VALUE_COL);\n\toutstr(pp, \" on\", 3);\n\n\tif (pp->p_scan >= 0) {\n\t\tpp->p_scan = -1;\n\t\tcgoto(pp, STAT_SCAN_ROW, STAT_VALUE_COL);\n\t\toutstr(pp, \"   \", 3);\n\t}\n\n\tshowstat(pp);\n}\n\n/*\n * scan:\n *\tTurn on or increase length of a scan\n */\nscan(pp)\nregister PLAYER\t*pp;\n{\n\tif (pp->p_ammo <= 0) {\n\t\tmessage(pp, \"No more charges\");\n\t\treturn;\n\t}\n\t(void) sprintf(Buf, \"%3d\", --pp->p_ammo);\n\tcgoto(pp, STAT_AMMO_ROW, STAT_VALUE_COL);\n\toutstr(pp, Buf, 3);\n\n\tpp->p_scan += SCANLEN;\n\tcgoto(pp, STAT_SCAN_ROW, STAT_VALUE_COL);\n\toutstr(pp, \" on\", 3);\n\n\tif (pp->p_cloak >= 0) {\n\t\tpp->p_cloak = -1;\n\t\tcgoto(pp, STAT_CLOAK_ROW, STAT_VALUE_COL);\n\t\toutstr(pp, \"   \", 3);\n\t}\n\n\tshowstat(pp);\n}\n\n/*\n * pickup:\n *\tcheck whether the object blew up or whether he picked it up\n */\npickup(pp, y, x, prob, obj)\nregister PLAYER\t*pp;\nregister int\ty, x;\nint\t\tprob;\nint\t\tobj;\n{\n\tregister int\treq;\n\n\tswitch (obj) {\n\t  case MINE:\n\t\treq = BULREQ;\n\t\tbreak;\n\t  case GMINE:\n\t\treq = GRENREQ;\n\t\tbreak;\n\t  default:\n\t\tabort();\n\t}\n\tif (rand_num(100) < prob)\n\t\tadd_shot(obj, y, x, LEFTS, req, (PLAYER *) NULL,\n\t\t\tTRUE, pp->p_face);\n\telse {\n\t\tpp->p_ammo += req;\n\t\t(void) sprintf(Buf, \"%3d\", pp->p_ammo);\n\t\tcgoto(pp, STAT_AMMO_ROW, STAT_VALUE_COL);\n\t\toutstr(pp, Buf, 3);\n\t}\n}\n"
  },
  {
    "path": "games/hunt/expl.c",
    "content": "/*\n *  Hunt\n *  Copyright (c) 1985 Conrad C. Huang, Gregory S. Couch, Kenneth C.R.C. Arnold\n *  San Francisco, California\n *\n *  Copyright (c) 1985 Regents of the University of California.\n *  All rights reserved.  The Berkeley software License Agreement\n *  specifies the terms and conditions for redistribution.\n */\n\n# include\t\"hunt.h\"\n\n/*\n * showexpl:\n *\tShow the explosions as they currently are\n */\nshowexpl(y, x, type)\nregister int\ty, x;\nchar\t\ttype;\n{\n\tregister PLAYER\t*pp;\n\tregister EXPL\t*ep;\n\n\tif (y < 0 || y >= HEIGHT)\n\t\treturn;\n\tif (x < 0 || x >= WIDTH)\n\t\treturn;\n\tep = (EXPL *) malloc(sizeof (EXPL));\t/* NOSTRICT */\n\tep->e_y = y;\n\tep->e_x = x;\n\tep->e_char = type;\n\tep->e_next = Expl[0];\n\tExpl[0] = ep;\n\tfor (pp = Player; pp < End_player; pp++) {\n\t\tif (pp->p_maze[y][x] == type)\n\t\t\tcontinue;\n\t\tpp->p_maze[y][x] = type;\n\t\tcgoto(pp, y, x);\n\t\toutch(pp, type);\n\t}\n# ifdef MONITOR\n\tfor (pp = Monitor; pp < End_monitor; pp++) {\n\t\tif (pp->p_maze[y][x] == type)\n\t\t\tcontinue;\n\t\tpp->p_maze[y][x] = type;\n\t\tcgoto(pp, y, x);\n\t\toutch(pp, type);\n\t}\n# endif MONITOR\n\tswitch (Maze[y][x]) {\n\t  case WALL1:\n\t  case WALL2:\n\t  case WALL3:\n# ifdef RANDOM\n\t  case DOOR:\n# endif RANDOM\n# ifdef REFLECT\n\t  case WALL4:\n\t  case WALL5:\n# endif REFLECT\n\t\tif (y >= UBOUND && y < DBOUND && x >= LBOUND && x < RBOUND)\n\t\t\tremove_wall(y, x);\n\t\tbreak;\n\t}\n}\n\n/*\n * rollexpl:\n *\tRoll the explosions over, so the next one in the list is at the\n *\ttop\n */\nrollexpl()\n{\n\tregister EXPL\t*ep;\n\tregister PLAYER\t*pp;\n\tregister int\ty, x;\n\tregister char\tc;\n\tregister EXPL\t*nextep;\n\n\tfor (ep = Expl[EXPLEN - 1]; ep != NULL; ep = nextep) {\n\t\tnextep = ep->e_next;\n\t\ty = ep->e_y;\n\t\tx = ep->e_x;\n\t\tif (y < UBOUND || y >= DBOUND || x < LBOUND || x >= RBOUND)\n\t\t\tc = Maze[y][x];\n\t\telse\n\t\t\tc = SPACE;\n\t\tfor (pp = Player; pp < End_player; pp++)\n\t\t\tif (pp->p_maze[y][x] == ep->e_char) {\n\t\t\t\tpp->p_maze[y][x] = c;\n\t\t\t\tcgoto(pp, y, x);\n\t\t\t\toutch(pp, c);\n\t\t\t}\n# ifdef MONITOR\n\t\tfor (pp = Monitor; pp < End_monitor; pp++)\n\t\t\tcheck(pp, y, x);\n# endif MONITOR\n\t\tfree((char *) ep);\n\t}\n\tfor (x = EXPLEN - 1; x > 0; x--)\n\t\tExpl[x] = Expl[x - 1];\n\tExpl[0] = NULL;\n}\n\n/* There's about 700 walls in the initial maze.  So we pick a number\n * that keeps the maze relatively full. */\n# define MAXREMOVE\t40\n\nstatic\tREGEN\tremoved[MAXREMOVE];\nstatic\tREGEN\t*rem_index = removed;\n\n/*\n * remove_wall - add a location where the wall was blown away.\n *\t\t if there is no space left over, put the a wall at\n *\t\t the location currently pointed at.\n */\nremove_wall(y, x)\nint\ty, x;\n{\n\tregister REGEN\t*r;\n# if defined(MONITOR) || defined(FLY)\n\tregister PLAYER\t*pp;\n# endif MONITOR || FLY\n# ifdef\tFLY\n\tregister char\tsave_char;\n# endif\tFLY\n\n\tr = rem_index;\n\twhile (r->r_y != 0) {\n# ifdef FLY\n\t\tswitch (Maze[r->r_y][r->r_x]) {\n\t\t  case SPACE:\n\t\t  case LEFTS:\n\t\t  case RIGHT:\n\t\t  case ABOVE:\n\t\t  case BELOW:\n\t\t  case FLYER:\n\t\t\tsave_char = Maze[r->r_y][r->r_x];\n\t\t\tgoto found;\n\t\t}\n# else FLY\n\t\tif (Maze[r->r_y][r->r_x] == SPACE)\n\t\t\tbreak;\n# endif FLY\n\t\tif (++r >= &removed[MAXREMOVE])\n\t\t\tr = removed;\n\t}\n\nfound:\n\tif (r->r_y != 0) {\n\t\t/* Slot being used, put back this wall */\n# ifdef FLY\n\t\tif (save_char == SPACE)\n\t\t\tMaze[r->r_y][r->r_x] = Orig_maze[r->r_y][r->r_x];\n\t\telse {\n\t\t\tpp = play_at(r->r_y, r->r_x);\n\t\t\tif (pp->p_flying >= 0)\n\t\t\t\tpp->p_flying += rand_num(10);\n\t\t\telse {\n\t\t\t\tpp->p_flying = rand_num(20);\n\t\t\t\tpp->p_flyx = 2 * rand_num(6) - 5;\n\t\t\t\tpp->p_flyy = 2 * rand_num(6) - 5;\n\t\t\t}\n\t\t\tpp->p_over = Orig_maze[r->r_y][r->r_x];\n\t\t\tpp->p_face = FLYER;\n\t\t\tMaze[r->r_y][r->r_x] = FLYER;\n\t\t\tshowexpl(r->r_y, r->r_x, FLYER);\n\t\t}\n# else FLY\n\t\tMaze[r->r_y][r->r_x] = Orig_maze[r->r_y][r->r_x];\n# endif FLY\n# ifdef RANDOM\n\t\tif (rand_num(100) == 0)\n\t\t\tMaze[r->r_y][r->r_x] = DOOR;\n# endif RANDOM\n# ifdef REFLECT\n\t\tif (rand_num(100) == 0)\t\t/* one percent of the time */\n\t\t\tMaze[r->r_y][r->r_x] = WALL4;\n# endif REFLECT\n# ifdef MONITOR\n\t\tfor (pp = Monitor; pp < End_monitor; pp++)\n\t\t\tcheck(pp, r->r_y, r->r_x);\n# endif MONITOR\n\t}\n\n\tr->r_y = y;\n\tr->r_x = x;\n\tif (++r >= &removed[MAXREMOVE])\n\t\trem_index = removed;\n\telse\n\t\trem_index = r;\n\n\tMaze[y][x] = SPACE;\n# ifdef MONITOR\n\tfor (pp = Monitor; pp < End_monitor; pp++)\n\t\tcheck(pp, y, x);\n# endif MONITOR\n}\n"
  },
  {
    "path": "games/hunt/extern.c",
    "content": "/*\n *  Hunt\n *  Copyright (c) 1985 Conrad C. Huang, Gregory S. Couch, Kenneth C.R.C. Arnold\n *  San Francisco, California\n *\n *  Copyright (c) 1985 Regents of the University of California.\n *  All rights reserved.  The Berkeley software License Agreement\n *  specifies the terms and conditions for redistribution.\n */\n\n# include\t\"hunt.h\"\n\n# ifdef MONITOR\nFLAG\tAm_monitor = FALSE;\t\t/* current process is a monitor */\n# endif MONITOR\n\nchar\tBuf[BUFSIZ];\t\t\t/* general scribbling buffer */\nchar\tMaze[HEIGHT][WIDTH2];\t\t/* the maze */\nchar\tOrig_maze[HEIGHT][WIDTH2];\t/* the original maze */\n\nlong\tFds_mask;\t\t\t/* mask for the file descriptors */\nint\tHave_inp;\t\t\t/* which file descriptors have input */\nint\tNplayer = 0;\t\t\t/* number of players */\nint\tNum_fds;\t\t\t/* number of maximum file descriptor */\nint\tSocket;\t\t\t\t/* main socket */\nlong\tSock_mask;\t\t\t/* select mask for main socket */\nint\tSee_over[NASCII];\t\t/* lookup table for determining whether\n\t\t\t\t\t * character represents \"transparent\"\n\t\t\t\t\t * item */\n\nBULLET\t*Bullets = NULL;\t\t/* linked list of bullets */\n\nEXPL\t*Expl[EXPLEN];\t\t\t/* explosion lists */\n\nPLAYER\tPlayer[MAXPL];\t\t\t/* all the players */\nPLAYER\t*End_player = Player;\t\t/* last active player slot */\nIDENT\t*Scores;\t\t\t/* score cache */\n# ifdef MONITOR\nPLAYER\tMonitor[MAXMON];\t\t/* all the monitors */\nPLAYER\t*End_monitor = Monitor;\t\t/* last active monitor slot */\n# endif MONITOR\n\n# ifdef VOLCANO\nint\tvolcano = 0;\t\t\t/* Explosion size */\n# endif VOLCANO\n"
  },
  {
    "path": "games/hunt/hunt.6",
    "content": ".\\\" Hunt\n.\\\" Copyright (c) 1985 Conrad C. Huang, Gregory S. Couch, Kenneth C.R.C. Arnold\n.\\\" San Francisco, California\n.\\\"\n.\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)hunt.6\t6.3 (Berkeley) 1/9/86\n.\\\"\n.TH HUNT 6 \"January 9, 1986\"\n.UC 6\n.SH NAME\nhunt \\- a multi-player multi-terminal game\n.SH SYNOPSIS\n\\fB/usr/games/hunt\\fP [-q] [\\fB-m\\fP] [hostname] [\\fB-l\\fP name]\n.SH DESCRIPTION\nThe object of the game\n.I hunt\nis to kill off the other players.\nThere are no rooms, no treasures, and no monsters.\nInstead, you wander around a maze, find grenades, trip mines, and shoot down\nwalls and players.\nThe more players you kill before you die, the better your score is.\nIf the\n.B \\-m\nflag is given,\nyou enter the game as a monitor\n(you can see the action but you cannot play).\n.PP\n.I Hunt\nnormally looks for an active game on the local network; if none is found,\nit starts one up on the local host.  One may specify the location of the\ngame by giving the \\fIhostname\\fP argument.  The player name may be specified\non the command line by using the \\fB-l\\fP option.  This command syntax was\nchosen for \\fIrlogin/rsh\\fP compatibility.\nIf the\n.B \\-q\nflag is given,\n.I hunt\nqueries the network and reports if an active game were found.\nThis is useful for .login scripts.\n.PP\n.I Hunt\nonly works on crt (vdt) terminals with at least 24 lines, 80 columns, and\ncursor addressing.\nThe screen is divided in to 3 areas.\nOn the right hand side is the status area.\nIt shows you how much damage you've sustained,\nhow many charges you have left,\nwho's in the game,\nwho's scanning (the asterisk in front of the name),\nwho's cloaked (the plus sign in front of the name),\nand other players' scores.\nMost of the rest of the screen is taken up by your map of the maze,\nexcept for the 24th line,\nwhich is used for longer messages that don't fit in the status area.\n.PP\n.I Hunt\nuses the same keys to move as\n.I vi\ndoes,\n.IR i.e. ,\n.BR h , j , k ,\nand\n.B l\nfor left, down, up, right respectively.\nTo change which direction you're facing in the maze,\nuse the upper case version of the movement key (\\c\n.IR i.e. ,\nHJKL).\n.TP\nOther commands are:\n.sp\n.nf\n.ta\n.ta \\w'>\\|<\\|^\\|v\\ \\ 'u\nf\t\\- Fire (in the direction you're facing) (Takes 1 charge)\ng\t\\- Throw grenade (in the direction you're facing) (Takes 9 charges)\nF\t\\- Throw satchel charge (Takes 25 charges)\nG\t\\- Throw bomb (Takes 49 charges)\no\t\\- Throw small slime bomb (Takes 15 charges)\nO\t\\- Throw big slime bomb (Takes 30 charges)\ns\t\\- Scan (show where other players are) (Takes 1 charge)\nc\t\\- Cloak (hide from scanners) (Takes 1 charge)\n\n^L\t\\- Redraw screen\nq\t\\- Quit\n.fi\n.TP\nKnowing what the symbols on the screen often helps:\n.sp\n.nf\n.ta\n.ta \\w'>\\|<\\|^\\|v\\ \\ 'u\n\\-\\||\\|+\t\\- walls\n/\\|\\\\\t\\- diagonal (deflecting) walls\n#\t\\- doors (dispersion walls)\n;\t\\- small mine\ng\t\\- large mine\n:\t\\- shot\no\t\\- grenade\nO\t\\- satchel charge\n@\t\\- bomb\ns\t\\- small slime bomb\n$\t\\- big slime bomb\n>\\|<\\|^\\|v\t\\- you facing right, left, up, or down\n}\\|{\\|i\\|!\t\\- other players facing right, left, up, or down\n\\(**\t\\- explosion\n.ne 3\n.cs R 24\n.cs I 24\n\\fR\\\\|/\\fP\n.cs R\n\\fI\\-\\(**\\-\\fP\t\\- grenade and large mine explosion\n.fl\n.cs R 24\n\\fR/|\\\\\\fP\n.cs R\n.cs I\n.fi\n.TP\nSatchel and bomb explosions are larger than grenades (5x5, 7x7,\nand 3x3 respectively).\n.LP\nOther helpful hints:\n.sp\n.ie n .ds b []\n.el .ds b \\(bu\n.ta\n.ta \\w'\\*b\\ \\|'u\n.nr In \\n(.i\n.de MP\n.br\n.in \\n(Inu+\\w'\\*b\\ \\|'u\n.ti \\n(Inu\n\\*b\t\\c\n..\n.MP\nYou can only fire in the direction you are facing.\n.MP\nYou can only fire three shots in a row, then the gun must cool.\n.MP\nA shot only affects the square it hits.\n.MP\nShots and grenades move 5 times faster than you do.\n.MP\nTo stab someone,\nyou must face that player and move at them.\n.MP\nStabbing does 2 points worth of damage and shooting does 5 points.\n.MP\nSlime does 5 points of damage each time it hits.\n.MP\nYou start with 15 charges and get 5 more for every new player.\n.MP\nA grenade affects the nine squares centered about the square it hits.\n.MP\nA satchel affects the twenty-five squares centered about the square it hits.\n.MP\nA bomb affects the forty-nine squares centered about the square it hits.\n.MP\nSlime affects all squares it oozes over (15 or 30 respectively).\n.MP\nOne small mine and one large mine is placed in the maze for every new player.\nA mine has a 5% probability of tripping when you walk directly at it;\n50% when going sideways on to it;\n95% when backing up on to it.\nTripping a mine costs you 5 points or 10 points respectively.\nDefusing a mine is worth 1 charge or 9 charges respectively.\n.MP\nYou cannot see behind you.\n.MP\nScanning lasts for (20 times the number of players) turns.\nScanning takes 1 ammo charge,\nso don't waste all your charges scanning.\n.MP\nCloaking lasts for 20 turns.\n.MP\nWhenever you kill someone,\nyou get 2 more damage capacity points and 2 damage points taken away.\n.MP\nMaximum typeahead is 5 characters.\n.MP\nA shot destroys normal (\\c\n.IR i.e., \nnon-diagonal, non-door) walls.\n.MP\nDiagonal walls deflect shots and change orientation.\n.MP\nDoors disperse shots in random directions (up, down, left, right).\n.MP\nDiagonal walls and doors cannot be destroyed by direct shots but may\nbe destroyed by an adjacent grenade explosion.\n.MP\nSlime goes around walls, not through them.\n.MP\nWalls regenerate, reappearing in the order they were destroyed.\nOne percent of the regenerated walls will be diagonal walls or doors.\nWhen a wall is generated directly beneath a player, he is thrown in\na random direction for a random period of time.  When he lands, he\nsustains damage (up to 20 percent of the amount of damage he had before\nimpact); that is, the less damage he had, the more nimble he is and\ntherefore less likely to hurt himself on landing.\n\\\".MP\n\\\"There is a volcano close to the center of the maze which goes off\n\\\"close to every 100 deaths.\n.MP\nThe environment variable\n.B HUNT\nis checked to get the player name.\nIf you don't have this variable set,\n.I hunt\nwill ask you what name you want to play under.\nIf it is set,\nyou may also set up a single character keyboard map, but then you have to\nenumerate the options:\n.br\n.ti +1i\n\\fIe.g.\\fP setenv HUNT ``name=Sneaky,mapkey=zoFfGg1f2g3F4G''\n.br\nsets the player name to Sneaky,\nand the maps \\fBz\\fP to \\fBo\\fP, \\fBF\\fP to \\fBf\\fP, \\fBG\\fP to \\fBg\\fP,\n\\fB1\\fP to \\fBf\\fP,\n\\fB2\\fP to \\fBg\\fP, \\fB3\\fP to \\fBF\\fP, and \\fB4\\fP to \\fBG\\fP.\nThe \\fImapkey\\fP option must be last.\n.MP\nIt's a boring game if you're the only one playing.\n.PP\nYour score is the ratio of number of kills to number\nof times you entered the game and is only kept for the duration\nof a single session of \\fIhunt\\fP.\n.PP\n.I Hunt\nnormally drives up the load average to be about\n(number_of_players + 0.5) greater than it would be without a\n.I hunt \ngame executing.  A limit of three players per host and nine players\ntotal is enforced by \\fIhunt\\fP.\n.SH FILES\n.nf\n.ta\n.ta \\w'/usr/games/lib/hunt.driver\\ \\ \\ 'u\n/usr/games/lib/hunt.driver\tgame coordinator\n.DT\n.fi\n.SH AUTHORS\nConrad Huang,\nKen Arnold,\nand Greg Couch;\nUniversity of California, San Francisco, Computer Graphics Lab\n.SH ACKNOWLEDGEMENTS\nWe thank Don Kneller,\nJohn Thomason, Eric Pettersen,\nand Scott Weiner for providing\nendless hours of play-testing to improve the character of the game.\nWe hope their significant others will forgive them;\nwe certainly don't.\n.SH BUGS\nTo keep up the pace, not everything is as realistic as possible.\n.PP\nThere were some bugs in early releases of 4.2 BSD that\n.I hunt\nhelped discover;\n.I hunt\nwill crash your system if those bugs haven't been fixed.\n"
  },
  {
    "path": "games/hunt/hunt.c",
    "content": "/*\n *  Hunt\n *  Copyright (c) 1985 Conrad C. Huang, Gregory S. Couch, Kenneth C.R.C. Arnold\n *  San Francisco, California\n *\n *  Copyright (c) 1985 Regents of the University of California.\n *  All rights reserved.  The Berkeley software License Agreement\n *  specifies the terms and conditions for redistribution.\n */\n\n# include\t<errno.h>\n# include\t<curses.h>\n# include\t\"hunt.h\"\n# include\t<signal.h>\n# include\t<ctype.h>\n# include\t<sys/stat.h>\n\nFLAG\tLast_player = FALSE;\n# ifdef MONITOR\nFLAG\tAm_monitor = FALSE;\n# endif MONITOR\nFLAG\tQuery_driver = FALSE;\n\nchar\tBuf[BUFSIZ];\n\nint\tMaster_pid;\nint\tSocket;\n# ifdef INTERNET\nchar\t*Sock_host;\n# endif INTERNET\n\nSOCKET\tDaemon;\n# ifdef\tINTERNET\n# define\tDAEMON_SIZE\t(sizeof Daemon)\n# else\tINTERNET\n# define\tDAEMON_SIZE\t(sizeof Daemon - 1)\n# endif\tINTERNET\n\nchar\tmap_key[256];\t\t\t/* what to map keys to */\n\nstatic char\tname[NAMELEN];\n\nextern int\tcur_row, cur_col, _putchar();\nextern char\t*tgoto();\n\n/*\n * main:\n *\tMain program for local process\n */\nmain(ac, av)\nint\tac;\nchar\t**av;\n{\n\tchar\t\t*term;\n\textern int\terrno;\n\textern int\tOtto_mode;\n\tint\t\tdumpit(), intr(), sigterm(), sigemt(), tstp();\n\n\tfor (ac--, av++; ac > 0 && av[0][0] == '-'; ac--, av++) {\n\t\tswitch (av[0][1]) {\n\n\t\tcase 'l':\t/* rsh compatibility */\n\t\tcase 'n':\n\t\t\tif (ac <= 1)\n\t\t\t\tgoto usage;\n\t\t\tac--, av++;\n\t\t\t(void) strcpy(name, av[0]);\n\t\t\tbreak;\n\t\tcase 'o':\n# ifndef OTTO\n\t\t\tfputs(\"The -o flag is reserved for future use.\\n\",\n\t\t\t\tstderr);\n\t\t\tgoto usage;\n# else OTTO\n\t\t\tOtto_mode = TRUE;\n\t\t\tbreak;\n# endif OTTO\n# ifdef MONITOR\n\t\tcase 'm':\n\t\t\tAm_monitor = TRUE;\n\t\t\tbreak;\n# endif MONITOR\n# ifdef INTERNET\n\t\tcase 'q':\t/* query whether hunt is running */\n\t\t\tQuery_driver = TRUE;\n\t\t\tbreak;\n\t\tcase 'h':\n\t\t\tif (ac <= 1)\n\t\t\t\tgoto usage;\n\t\t\tac--, av++;\n\t\t\tSock_host = av[0];\n\t\t\tbreak;\n# endif INTERNET\n\t\tdefault:\n\t\tusage:\n# ifdef INTERNET\n#  ifdef MONITOR\n#   define\tUSAGE\t\"usage: hunt [-q] [-n name] [-h host] [-m]\\n\"\n#  else MONITOR\n#   define\tUSAGE\t\"usage: hunt [-q] [-n name] [-h host]\\n\"\n#  endif MONITOR\n# else INTERNET\n#  ifdef MONITOR\n#   define\tUSAGE\t\"usage: hunt [-n name] [-m]\\n\"\n#  else MONITOR\n#   define\tUSAGE\t\"usage: hunt [-n name]\\n\"\n#  endif MONITOR\n# endif INTERNET\n\t\t\tfputs(USAGE, stderr);\n# undef USAGE\n\t\t\texit(1);\n\t\t}\n\t}\n# ifdef INTERNET\n\tif (ac > 1)\n\t\tgoto usage;\n\telse if (ac > 0)\n\t\tSock_host = av[0];\n# else INTERNET\n\tif (ac > 0)\n\t\tgoto usage;\n# endif INTERNET\t\n\n# ifdef INTERNET\n\tif (Query_driver) {\n\t\tfind_driver(FALSE);\n\t\tif (Daemon.sin_port != 0) {\n\t\t\tstruct\thostent\t*hp;\n\n\t\t\thp = gethostbyaddr(&Daemon.sin_addr,\n\t\t\t\tsizeof Daemon.sin_addr, AF_INET);\n\t\t\tfprintf(stderr, \"HUNT!! found on %s\\n\", hp != NULL\n\t\t\t\t? hp->h_name : inet_ntoa(Daemon.sin_addr));\n\t\t}\n\t\texit(Daemon.sin_port == 0);\n\t}\n# endif INTERNET\n# ifdef OTTO\n\tif (Otto_mode)\n\t\t(void) strcpy(name, \"otto\");\n\telse\n# endif OTTO\n\tenv_init();\n\n\t(void) fflush(stdout);\n\tif (!isatty(0) || (term = getenv(\"TERM\")) == NULL) {\n\t\tfprintf(stderr, \"no terminal type\\n\");\n\t\texit(1);\n\t}\n\t_tty_ch = 0;\n\tgettmode();\n\tsetterm(term);\n\tnoecho();\n\tcbreak();\n\t_puts(TI);\n\t_puts(VS);\n\tclear_screen();\n\t(void) signal(SIGINT, intr);\n\t(void) signal(SIGTERM, sigterm);\n\t(void) signal(SIGEMT, sigemt);\n\t(void) signal(SIGQUIT, dumpit);\n\t(void) signal(SIGPIPE, SIG_IGN);\n\t(void) signal(SIGTSTP, tstp);\n\n\tdo {\n# ifdef\tINTERNET\n\t\tfind_driver(TRUE);\n\n\t\tdo {\n\t\t\tint\tmsg;\n\n# ifndef OLDIPC\n\t\t\tSocket = socket(SOCK_FAMILY, SOCK_STREAM, 0);\n# else OLDIPC\n\t\t\tSocket = socket(SOCK_STREAM, 0, 0, 0);\n# endif OLDIPC\n\t\t\tif (Socket < 0) {\n\t\t\t\tperror(\"socket\");\n\t\t\t\texit(1);\n\t\t\t}\n# ifndef OLDIPC\n\t\t\tmsg = 1;\n\t\t\tif (setsockopt(Socket, SOL_SOCKET, SO_USELOOPBACK,\n\t\t\t    &msg, sizeof msg) < 0)\n\t\t\t\tperror(\"setsockopt loopback\");\n# endif OLDIPC\n\t\t\terrno = 0;\n\t\t\tif (connect(Socket, (struct sockaddr *) &Daemon,\n\t\t\t    DAEMON_SIZE) < 0) {\n\t\t\t\tif (errno != ECONNREFUSED) {\n\t\t\t\t\tperror(\"connect\");\n\t\t\t\t\tleave(1, \"connect\");\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t\tbreak;\n\t\t\tsleep(1);\n\t\t} while (close(Socket) == 0);\n# else\tINTERNET\n\t\t/*\n\t\t * set up a socket\n\t\t */\n\n\t\tif ((Socket = socket(SOCK_FAMILY, SOCK_STREAM, 0)) < 0) {\n\t\t\tperror(\"socket\");\n\t\t\texit(1);\n\t\t}\n\n\t\t/*\n\t\t * attempt to connect the socket to a name; if it fails that\n\t\t * usually means that the driver isn't running, so we start\n\t\t * up the driver.\n\t\t */\n\n\t\tDaemon.sun_family = SOCK_FAMILY;\n\t\t(void) strcpy(Daemon.sun_path, Sock_name);\n\t\tif (connect(Socket, &Daemon, DAEMON_SIZE) < 0) {\n\t\t\tif (errno != ENOENT) {\n\t\t\t\tperror(\"connect\");\n\t\t\t\tleave(1, \"connect2\");\n\t\t\t}\n\t\t\tstart_driver();\n\n\t\t\tdo {\n\t\t\t\t(void) close(Socket);\n\t\t\t\tif ((Socket = socket(SOCK_FAMILY, SOCK_STREAM, 0)) < 0) {\n\t\t\t\t\tperror(\"socket\");\n\t\t\t\t\texit(1);\n\t\t\t\t}\n\t\t\t\tsleep(2);\n\t\t\t} while (connect(Socket, &Daemon, DAEMON_SIZE) < 0);\n\t\t}\n# endif INTERNET\n\n\t\tdo_connect(name);\n\t\tplayit();\n\t} while (!quit());\n\tleave(0, NULL);\n\t/* NOTREACHED */\n}\n\n# ifdef INTERNET\n# ifdef BROADCAST\nbroadcast_vec(s, vector)\n\tint\t\t\ts;\t\t/* socket */\n\tstruct\tsockaddr\t**vector;\n{\n\tchar\t\t\tif_buf[BUFSIZ];\n\tstruct\tifconf\t\tifc;\n\tstruct\tifreq\t\t*ifr;\n\tint\t\t\tn;\n\tint\t\t\tvec_cnt;\n\n\t*vector = NULL;\n\tifc.ifc_len = sizeof if_buf;\n\tifc.ifc_buf = if_buf;\n\tif (ioctl(s, SIOCGIFCONF, (char *) &ifc) < 0)\n\t\treturn 0;\n\tvec_cnt = 0;\n\tn = ifc.ifc_len / sizeof (struct ifreq);\n\t*vector = (struct sockaddr *) malloc(n * sizeof (struct sockaddr));\n\tfor (ifr = ifc.ifc_req; n > 0; n--, ifr++)\n\t\tif (ioctl(s, SIOCGIFBRDADDR, ifr) >= 0)\n\t\t\tbcopy(&ifr->ifr_addr, &(*vector)[vec_cnt++],\n\t\t\t\t\t\tsizeof (struct sockaddr));\n\treturn vec_cnt;\n}\n# endif BROADCAST\n\nfind_driver(do_startup)\nFLAG\tdo_startup;\n{\n\tint\t\t\tmsg;\n\tstatic SOCKET\t\ttest;\n\tint\t\t\ttest_socket;\n\tint\t\t\tnamelen;\n\tchar\t\t\tlocal_name[80];\n\tstatic\t\t\tinitial = TRUE;\n\tstatic struct in_addr\tlocal_address;\n\tregister struct hostent\t*hp;\n\tint\t\t\t(*oldsigalrm)(), sigalrm();\n\textern int\t\terrno;\n# ifdef BROADCAST\n\tstatic\tint\t\tbrdc;\n\tstatic\tSOCKET\t\t*brdv;\n\tint\t\t\ti;\n# endif BROADCAST\n\n\tif (Sock_host != NULL) {\n\t\tif (!initial)\n\t\t\treturn;\t\t/* Daemon address already valid */\n\t\tinitial = FALSE;\n\t\tif ((hp = gethostbyname(Sock_host)) == NULL) {\n\t\t\tleave(1, \"Unknown host\");\n\t\t\t/* NOTREACHED */\n\t\t}\n\t\tDaemon.sin_family = SOCK_FAMILY;\n\t\tDaemon.sin_port = htons(Sock_port);\n\t\tDaemon.sin_addr = *((struct in_addr *) hp->h_addr);\n\t\tif (!Query_driver)\n\t\t\treturn;\n\t}\n\n\n\tif (initial) {\t\t\t/* do one time initialization */\n# ifndef BROADCAST\n\t\tsethostent(1);\t\t/* don't bother to close host file */\n# endif BROADCAST\n\t\tif (gethostname(local_name, sizeof local_name) < 0) {\n\t\t\tleave(1, \"Sorry, I have no name.\");\n\t\t\t/* NOTREACHED */\n\t\t}\n\t\tif ((hp = gethostbyname(local_name)) == NULL) {\n\t\t\tleave(1, \"Can't find myself.\");\n\t\t\t/* NOTREACHED */\n\t\t}\n\t\tlocal_address = * ((struct in_addr *) hp->h_addr);\n\n\t\ttest.sin_family = SOCK_FAMILY;\n\t\ttest.sin_addr = local_address;\n\t\ttest.sin_port = htons(Test_port);\n\t}\n\n# ifndef OLDIPC\n\ttest_socket = socket(SOCK_FAMILY, SOCK_DGRAM, 0);\n# else OLDIPC\n\ttest_socket = socket(SOCK_DGRAM, 0, 0, 0);\n# endif OLCIPC\n\tif (test_socket < 0) {\n\t\tperror(\"socket\");\n\t\tleave(1, \"socket system call failed\");\n\t\t/* NOTREACHED */\n\t}\n\n\tmsg = 1;\n\tif (Query_driver && Sock_host != NULL) {\n\t\ttest.sin_family = SOCK_FAMILY;\n\t\ttest.sin_addr = Daemon.sin_addr;\n\t\ttest.sin_port = htons(Test_port);\n# ifndef OLDIPC\n\t\t(void) sendto(test_socket, (char *) &msg, sizeof msg, 0,\n\t\t    (struct sockaddr *) &test, DAEMON_SIZE);\n# else OLDIPC\n\t\t(void) send(test_socket, (struct sockaddr *) &test,\n\t\t\t(char *) &msg, sizeof msg);\n# endif OLDIPC\n\t\tgoto get_response;\n\t}\n\n\tif (!initial) {\n\t\t/* favor host of previous session by broadcasting to it first */\n\t\ttest.sin_addr = Daemon.sin_addr;\n\t\ttest.sin_port = htons(Test_port);\n\t\t(void) sendto(test_socket, (char *) &msg, sizeof msg, 0,\n\t\t    (struct sockaddr *) &test, DAEMON_SIZE);\n\t}\n\n\n# ifdef BROADCAST\n\tif (initial)\n\t\tbrdc = broadcast_vec(test_socket, &brdv);\n\n\tif (brdc <= 0) {\n\t\tDaemon.sin_family = SOCK_FAMILY;\n\t\tDaemon.sin_addr = local_address;\n\t\tDaemon.sin_port = htons(Sock_port);\n\t\tinitial = FALSE;\n\t\treturn;\n\t}\n\n\tif (setsockopt(test_socket, SOL_SOCKET, SO_BROADCAST,\n\t    (int) &msg, sizeof msg) < 0) {\n\t\tperror(\"setsockopt broadcast\");\n\t\tleave(1, \"setsockopt broadcast\");\n\t\t/* NOTREACHED */\n\t}\n\n\t/* send broadcast packets on all interfaces */\n\tfor (i = 0; i < brdc; i++) {\n\t\tbcopy(&brdv[i], &test, sizeof (SOCKET));\n\t\ttest.sin_port = htons(Test_port);\n\t\tif (sendto(test_socket, (char *) &msg, sizeof msg, 0,\n\t\t    (struct sockaddr *) &test, DAEMON_SIZE) < 0) {\n\t\t\tperror(\"sendto\");\n\t\t\tleave(1, \"sendto\");\n\t\t\t/* NOTREACHED */\n\t\t}\n\t}\n# else BROADCAST\n\t/* loop thru all hosts on local net and send msg to them. */\n\tsethostent(0);\t\t/* rewind host file */\n\twhile (hp = gethostent()) {\n\t\tif (inet_netof(test.sin_addr)\n\t\t== inet_netof(* ((struct in_addr *) hp->h_addr))) {\n\t\t\ttest.sin_addr = * ((struct in_addr *) hp->h_addr);\n# ifndef OLDIPC\n\t\t\t(void) sendto(test_socket, (char *) &msg, sizeof msg, 0,\n\t\t\t    (struct sockaddr *) &test, DAEMON_SIZE);\n# else OLDIPC\n\t\t\t(void) send(test_socket, (struct sockaddr *) &test,\n\t\t\t\t(char *) &msg, sizeof msg);\n# endif OLDIPC\n\t\t}\n\t}\n# endif BROADCAST\n\nget_response:\n\tnamelen = DAEMON_SIZE;\n\toldsigalrm = signal(SIGALRM, sigalrm);\n\terrno = 0;\n\t(void) alarm(1);\n# ifndef OLDIPC\n\tif (recvfrom(test_socket, (char *) &msg, sizeof msg, 0,\n\t    (struct sockaddr *) &Daemon, &namelen) < 0)\n# else OLDIPC\n\tif (receive(test_socket, (struct sockaddr *) &Daemon, &msg,\n\t    sizeof msg) < 0)\n# endif OLDIPC\n\t{\n\t\tif (errno != EINTR) {\n\t\t\tperror(\"recvfrom\");\n\t\t\tleave(1, \"recvfrom\");\n\t\t\t/* NOTREACHED */\n\t\t}\n\t\t(void) alarm(0);\n\t\t(void) signal(SIGALRM, oldsigalrm);\n\t\tDaemon.sin_family = SOCK_FAMILY;\n\t\tDaemon.sin_port = htons(Sock_port);\n\t\tDaemon.sin_addr = local_address;\n\t\tif (!do_startup)\n\t\t\tDaemon.sin_port = 0;\n\t\telse\n\t\t\tstart_driver();\n\t}\n\telse {\n\t\t(void) alarm(0);\n\t\t(void) signal(SIGALRM, oldsigalrm);\n\t\tDaemon.sin_port = htons(Sock_port);\n\t}\n\t(void) close(test_socket);\n\tinitial = FALSE;\n}\n# endif INTERNET\n\nstart_driver()\n{\n\tregister int\tprocid;\n\n# ifdef MONITOR\n\tif (Am_monitor) {\n\t\tleave(1, \"No one playing.\");\n\t\t/* NOTREACHED */\n\t}\n# endif MONITOR\n\n# ifdef INTERNET\n\tif (Sock_host != NULL) {\n\t\tsleep(3);\n\t\treturn 0;\n\t}\n# endif INTERNET\n\n\tmvcur(cur_row, cur_col, 23, 0);\n\tcur_row = 23;\n\tcur_col = 0;\n\tput_str(\"Starting...\");\n\tfflush(stdout);\n\tprocid = vfork();\n\tif (procid == -1) {\n\t\tperror(\"fork\");\n\t\tleave(1, \"fork failed.\");\n\t}\n\tif (procid == 0) {\n\t\t(void) signal(SIGINT, SIG_IGN);\n\t\t(void) close(Socket);\n\t\texecl(Driver, \"HUNT\", NULL);\n\t\t/* only get here if exec failed */\n\t\tkill(getppid(), SIGEMT);\t/* tell mom */\n\t\t_exit(1);\n\t}\n\tmvcur(cur_row, cur_col, 23, 0);\n\tcur_row = 23;\n\tcur_col = 0;\n\tput_str(\"Connecting...\");\n\tfflush(stdout);\n\treturn 0;\n}\n\n/*\n * bad_con:\n *\tWe had a bad connection.  For the moment we assume that this\n *\tmeans the game is full.\n */\nbad_con()\n{\n\tleave(1, \"The game is full.  Sorry.\");\n\t/* NOTREACHED */\n}\n\n/*\n * dumpit:\n *\tHandle a core dump signal by not dumping core, just leaving,\n *\tso we end up with a core dump from the driver\n */\ndumpit()\n{\n\t(void) kill(Master_pid, SIGQUIT);\n\t(void) chdir(\"coredump\");\n\tabort();\n}\n\n/*\n * sigterm:\n *\tHandle a terminate signal\n */\nsigterm()\n{\n\tleave(0, NULL);\n\t/* NOTREACHED */\n}\n\n\n/*\n * sigemt:\n *\tHandle a emt signal - shouldn't happen on vaxes(?)\n */\nsigemt()\n{\n\tleave(1, \"Unable to start driver.  Try again.\");\n\t/* NOTREACHED */\n}\n\n# ifdef INTERNET\n/*\n * sigalrm:\n *\tHandle an alarm signal\n */\nsigalrm()\n{\n\treturn;\n}\n# endif INTERNET\n\n/*\n * rmnl:\n *\tRemove a '\\n' at the end of a string if there is one\n */\nrmnl(s)\nchar\t*s;\n{\n\tregister char\t*cp;\n\tchar\t\t*rindex();\n\n\tcp = rindex(s, '\\n');\n\tif (cp != NULL)\n\t\t*cp = '\\0';\n}\n\n/*\n * intr:\n *\tHandle a interrupt signal\n */\nintr()\n{\n\tregister int\tch;\n\tregister int\texplained;\n\tregister int\ty, x;\n\n\t(void) signal(SIGINT, SIG_IGN);\n\ty = cur_row;\n\tx = cur_col;\n\tmvcur(cur_row, cur_col, 23, 0);\n\tcur_row = 23;\n\tcur_col = 0;\n\tput_str(\"Really quit? \");\n\tclear_eol();\n\tfflush(stdout);\n\texplained = FALSE;\n\tfor (;;) {\n\t\tch = getchar();\n\t\tif (isupper(ch))\n\t\t\tch = tolower(ch);\n\t\tif (ch == 'y') {\n\t\t\t(void) write(Socket, \"q\", 1);\n\t\t\t(void) close(Socket);\n\t\t\tleave(0, NULL);\n\t\t}\n\t\telse if (ch == 'n') {\n\t\t\t(void) signal(SIGINT, intr);\n\t\t\tmvcur(cur_row, cur_col, y, x);\n\t\t\tcur_row = y;\n\t\t\tcur_col = x;\n\t\t\tfflush(stdout);\n\t\t\treturn;\n\t\t}\n\t\tif (!explained) {\n\t\t\tput_str(\"(Y or N) \");\n\t\t\tfflush(stdout);\n\t\t\texplained = TRUE;\n\t\t}\n\t\t(void) putchar(CTRL(G));\n\t\t(void) fflush(stdout);\n\t}\n}\n\n/*\n * leave:\n *\tLeave the game somewhat gracefully, restoring all current\n *\ttty stats.\n */\nleave(eval, mesg)\nint\teval;\nchar\t*mesg;\n{\n\tmvcur(cur_row, cur_col, 23, 0);\n\tif (mesg == NULL)\n\t\tclear_eol();\n\telse {\n\t\tput_str(mesg);\n\t\tclear_eol();\n\t\tputchar('\\n');\n\t\tfflush(stdout);\t\t/* flush in case VE changes pages */\n\t} \n\tresetty();\n\t_puts(VE);\n\t_puts(TE);\n\texit(eval);\n}\n\n/*\n * tstp:\n *\tHandle stop and start signals\n */\ntstp()\n{\n\tstatic struct sgttyb\ttty;\n\tint\ty, x;\n\n\ttty = _tty;\n\ty = cur_row;\n\tx = cur_col;\n\tmvcur(cur_row, cur_col, 23, 0);\n\tcur_row = 23;\n\tcur_col = 0;\n\t_puts(VE);\n\t_puts(TE);\n\t(void) fflush(stdout);\n\tresetty();\n\t(void) kill(getpid(), SIGSTOP);\n\t(void) signal(SIGTSTP, tstp);\n\t_tty = tty;\n\t(void) stty(_tty_ch, &_tty);\n\t_puts(TI);\n\t_puts(VS);\n\tcur_row = y;\n\tcur_col = x;\n\t_puts(tgoto(CM, cur_row, cur_col));\n\tredraw_screen();\n\tfflush(stdout);\n}\n\nenv_init()\n{\n\tregister int\ti;\n\tchar\t*envp, *envname, *s, *index();\n\n\tfor (i = 0; i < 256; i++)\n\t\tmap_key[i] = (char) i;\n\n\tenvname = NULL;\n\tif ((envp = getenv(\"HUNT\")) != NULL) {\n\t\twhile ((s = index(envp, '=')) != NULL) {\n\t\t\tif (strncmp(envp, \"name=\", s - envp + 1) == 0) {\n\t\t\t\tenvname = s + 1;\n\t\t\t\tif ((s = index(envp, ',')) == NULL) {\n\t\t\t\t\t*envp = '\\0';\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\t*s = '\\0';\n\t\t\t\tenvp = s + 1;\n\t\t\t}\t\t\t/* must be last option */\n\t\t\telse if (strncmp(envp, \"mapkey=\", s - envp + 1) == 0) {\n\t\t\t\tfor (s = s + 1; *s != '\\0'; s += 2) {\n\t\t\t\t\tmap_key[(unsigned int) *s] = *(s + 1);\n\t\t\t\t\tif (*(s + 1) == '\\0') {\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t*envp = '\\0';\n\t\t\t\tbreak;\n\t\t\t} else {\n\t\t\t\t*s = '\\0';\n\t\t\t\tprintf(\"unknown option %s\\n\", envp);\n\t\t\t\tif ((s = index(envp, ',')) == NULL) {\n\t\t\t\t\t*envp = '\\0';\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tenvp = s + 1;\n\t\t\t}\n\t\t}\n\t\tif (*envp != '\\0')\n\t\t\tif (envname == NULL)\n\t\t\t\tenvname = envp;\n\t\t\telse\n\t\t\t\tprintf(\"unknown option %s\\n\", envp);\n\t}\n\tif (envname != NULL) {\n\t\t(void) strcpy(name, envname);\n\t\tprintf(\"Entering as '%s'\\n\", envname);\n\t}\n\telse if (name[0] == '\\0') {\n\t\tprintf(\"Enter your code name: \");\n\t\tif (fgets(name, sizeof name, stdin) == NULL)\n\t\t\texit(1);\n\t}\n\trmnl(name);\n}\n"
  },
  {
    "path": "games/hunt/hunt.h",
    "content": "/*\n *  Hunt\n *  Copyright (c) 1985 Conrad C. Huang, Gregory S. Couch, Kenneth C.R.C. Arnold\n *  San Francisco, California\n *\n *  Copyright (c) 1985 Regents of the University of California.\n *  All rights reserved.  The Berkeley software License Agreement\n *  specifies the terms and conditions for redistribution.\n */\n\n# include\t<stdio.h>\n# ifndef OLDIPC\n# include\t<sgtty.h>\n# include\t<sys/types.h>\n# include\t<sys/uio.h>\n# else OLDIPC\n# include\t<sys/localopts.h>\n# include\t<sys/types.h>\n# include\t<sys/netltoshort.h>\n# endif OLDIPC\n# include\t<sys/socket.h>\n# ifdef\tINTERNET\n# include\t<netinet/in.h>\n# include\t<netdb.h>\n# ifndef OLDIPC\n# include\t<arpa/inet.h>\n# endif !OLDIPC\n# ifdef BROADCAST\n# include\t<net/if.h>\n# endif BROADCAST\n# else\tINTERNET\n# include\t<sys/un.h>\n# endif\tINTERNET\n\n# ifdef\tINTERNET\n# define\tSOCK_FAMILY\tAF_INET\n# else\tINTERNET\n# define\tSOCK_FAMILY\tAF_UNIX\n# define\tAF_UNIX_HACK\t\t/* 4.2 hack; leaves files around */\n# endif\tINTERNET\n\n# define\tADDCH\t\t('a' | 0200)\n# define\tMOVE\t\t('m' | 0200)\n# define\tREFRESH\t\t('r' | 0200)\n# define\tCLRTOEOL\t('c' | 0200)\n# define\tENDWIN\t\t('e' | 0200)\n# define\tCLEAR\t\t('C' | 0200)\n# define\tREDRAW\t\t('R' | 0200)\n# define\tLAST_PLAYER\t('l' | 0200)\n# define\tBELL\t\t('b' | 0200)\n# define\tREADY\t\t('g' | 0200)\n\n/*\n * Choose MAXPL and MAXMON carefully.  The screen is assumed to be\n * 23 lines high and will only tolerate (MAXPL == 12 && MAXMON == 0)\n * or (MAXPL + MAXMON <= 10).\n */\n# define\tMAXPL\t\t9\n# ifdef MONITOR\n# define\tMAXMON\t\t1\n# endif MONITOR\n# define\tNAMELEN\t\t20\n# define\tMSGLEN\t\t80\n# define\tDECAY\t\t50.0\n\n# define\tNASCII\t\t128\n\n# ifndef REFLECT\n# ifndef RANDOM\n# define RANDOM\n# endif RANDOM\n# endif REFLECT\n\n# define\tWIDTH\t59\n# define\tWIDTH2\t64\t/* Next power of 2 >= WIDTH (for fast access) */\n# define\tHEIGHT\t23\n# define\tUBOUND\t1\n# define\tDBOUND\t22\n# define\tLBOUND\t1\n# define\tRBOUND\t(WIDTH - 1)\n\n# define\tSTAT_LABEL_COL\t60\n# define\tSTAT_VALUE_COL\t74\n# define\tSTAT_NAME_COL\t61\n# define\tSTAT_SCAN_COL\t(STAT_NAME_COL + 5)\n# define\tSTAT_NAME_ROW\t0\n# define\tSTAT_AMMO_ROW\t2\n# define\tSTAT_SCAN_ROW\t3\n# define\tSTAT_CLOAK_ROW\t4\n# define\tSTAT_GUN_ROW\t5\n# define\tSTAT_DAM_ROW\t7\n# define\tSTAT_KILL_ROW\t8\n# define\tSTAT_PLAY_ROW\t10\n# ifdef MONITOR\n# define\tSTAT_MON_ROW\t(STAT_PLAY_ROW + MAXPL + 1)\n# endif MONITOR\n# define\tSTAT_NAME_LEN\t16\n\n# define\tDOOR\t'#'\n# define\tWALL1\t'-'\n# define\tWALL2\t'|'\n# define\tWALL3\t'+'\n# ifdef REFLECT\n# define\tWALL4\t'/'\n# define\tWALL5\t'\\\\'\n# endif REFLECT\n# define\tKNIFE\t'K'\n# define\tSHOT\t':'\n# define\tGRENADE\t'o'\n# define\tSATCHEL\t'O'\n# define\tBOMB\t'@'\n# define\tMINE\t';'\n# define\tGMINE\t'g'\n# ifdef\tOOZE\n# define\tSLIME\t'$'\n# endif\tOOZE\n# ifdef\tVOLCANO\n# define\tLAVA\t'~'\n# endif\tVOLCANO\n# ifdef FLY\n# define\tFALL\t'F'\n# endif FLY\n# define\tSPACE\t' '\n\n# define\tABOVE\t'i'\n# define\tBELOW\t'!'\n# define\tRIGHT\t'}'\n# define\tLEFTS\t'{'\n# ifdef FLY\n# define\tFLYER\t'&'\n# endif FLY\n\n# define\tNORTH\t01\n# define\tSOUTH\t02\n# define\tEAST\t010\n# define\tWEST\t020\n\n# ifndef TRUE\n# define\tTRUE\t1\n# define\tFALSE\t0\n# endif TRUE\n# ifndef CTRL\n# define\tCTRL(x)\t('x' & 037)\n# endif CTRL\n\n# define\tBULSPD\t\t5\t\t/* bullets movement speed */\n# define\tISHOTS\t\t15\n# define\tNSHOTS\t\t5\n# define\tMAXNCSHOT\t2\n# define\tMAXDAM\t\t10\n# define\tMINDAM\t\t5\n# define\tSTABDAM\t\t2\n\n# define\tBULREQ\t\t1\n# define\tGRENREQ\t\t9\n# define\tSATREQ\t\t25\n# define\tBOMBREQ\t\t49\n# ifdef\tOOZE\n# define\tSLIMEREQ\t15\n# define\tSSLIMEREQ\t30\n# define\tSLIMESPEED\t5\n# endif\tOOZE\n# ifdef\tVOLCANO\n# define\tLAVASPEED\t2\n# endif VOLCANO\n\n# define\tCLOAKLEN\t20\n# define\tSCANLEN\t\t(Nplayer * 20)\n# define\tEXPLEN\t\t4\n\n# ifdef FLY\n# define\t_cloak_char(pp)\t(((pp)->p_cloak < 0) ? ' ' : '+')\n# define\t_scan_char(pp)\t(((pp)->p_scan < 0) ? _cloak_char(pp) : '*')\n# define\tstat_char(pp)\t(((pp)->p_flying < 0) ? _scan_char(pp) : FLYER)\n# else FLY\n# define\t_cloak_char(pp)\t(((pp)->p_cloak < 0) ? ' ' : '+')\n# define\tstat_char(pp)\t(((pp)->p_scan < 0) ? _cloak_char(pp) : '*')\n# endif FLY\n\ntypedef int\t\t\tFLAG;\ntypedef struct bullet_def\tBULLET;\ntypedef struct expl_def\t\tEXPL;\ntypedef struct player_def\tPLAYER;\ntypedef struct ident_def\tIDENT;\ntypedef struct regen_def\tREGEN;\n# ifdef\tINTERNET\ntypedef struct sockaddr_in\tSOCKET;\n# else\tINTERNET\ntypedef struct sockaddr_un\tSOCKET;\n# endif\tINTERNET\ntypedef struct sgttyb\t\tTTYB;\n\nstruct ident_def {\n\tchar\ti_name[NAMELEN];\n\tlong\ti_machine;\n\tlong\ti_uid;\n\tint\ti_kills;\n\tint\ti_entries;\n\tfloat\ti_score;\n\tIDENT\t*i_next;\n};\n\nstruct player_def {\n\tIDENT\t*p_ident;\n\tint\tp_face;\n\tchar\tp_over;\n\tint\tp_undershot;\n# ifdef\tFLY\n\tint\tp_flying;\n\tint\tp_flyx, p_flyy;\n# endif FLY\n\tFILE\t*p_output;\n\tint\tp_fd;\n\tint\tp_mask;\n\tint\tp_damage;\n\tint\tp_damcap;\n\tint\tp_ammo;\n\tint\tp_ncshot;\n\tint\tp_scan;\n\tint\tp_cloak;\n\tint\tp_x, p_y;\n\tint\tp_ncount;\n\tint\tp_nexec;\n\tlong\tp_nchar;\n\tchar\tp_death[MSGLEN];\n\tchar\tp_maze[HEIGHT][WIDTH2];\n\tint\tp_curx, p_cury;\n\tint\tp_lastx, p_lasty;\n\tint\tp_changed;\n\tchar\tp_cbuf[BUFSIZ];\n};\n\nstruct bullet_def {\n\tint\tb_x, b_y;\n\tint\tb_face;\n\tint\tb_charge;\n\tchar\tb_type;\n\tchar\tb_over;\n\tPLAYER\t*b_owner;\n\tIDENT\t*b_score;\n\tFLAG\tb_expl;\n\tBULLET\t*b_next;\n};\n\nstruct expl_def {\n\tint\te_x, e_y;\n\tchar\te_char;\n\tEXPL\t*e_next;\n};\n\nstruct regen_def {\n\tint\tr_x, r_y;\n\tREGEN\t*r_next;\n};\n\n/*\n * external variables\n */\n\nextern FLAG\tLast_player;\n\nextern char\tBuf[BUFSIZ], Maze[HEIGHT][WIDTH2], Orig_maze[HEIGHT][WIDTH2];\n\nextern char\t*Sock_name, *Driver;\n\nextern int\terrno, Have_inp, Nplayer, Num_fds, Socket;\nextern long\tFds_mask, Sock_mask;\n\n# ifdef INTERNET\nextern int\tTest_port;\nextern int\tSock_port;\n# else INTERNET\nextern char\t*Sock_name;\n# endif INTERNET\n\n# ifdef VOLCANO\nextern int\tvolcano;\n# endif\tVOLCANO\n\nextern int\tSee_over[NASCII];\n\nextern BULLET\t*Bullets;\n\nextern EXPL\t*Expl[EXPLEN];\n\nextern IDENT\t*Scores;\n\nextern PLAYER\tPlayer[MAXPL], *End_player;\n\n# ifdef MONITOR\nextern FLAG\tAm_monitor;\nextern PLAYER\tMonitor[MAXMON], *End_monitor;\n# endif MONITOR\n\n/*\n * function types\n */\n\nchar\t*getenv(), *malloc(), *sprintf(), *strcpy(), *strncpy();\n\nIDENT\t*get_ident();\n\nint\tmoveshots();\n\nBULLET\t*is_bullet(), *create_shot();\n\nPLAYER\t*play_at();\n"
  },
  {
    "path": "games/hunt/makemaze.c",
    "content": "/*\n *  Hunt\n *  Copyright (c) 1985 Conrad C. Huang, Gregory S. Couch, Kenneth C.R.C. Arnold\n *  San Francisco, California\n *\n *  Copyright (c) 1985 Regents of the University of California.\n *  All rights reserved.  The Berkeley software License Agreement\n *  specifies the terms and conditions for redistribution.\n */\n\n# include\t\"hunt.h\"\n\n# define\tISCLEAR(y,x)\t(Maze[y][x] == SPACE)\n# define\tODD(n)\t\t((n) & 01)\n\nmakemaze()\n{\n\tregister char\t*sp;\n\tregister int\ty, x;\n\n\t/*\n\t * fill maze with walls\n\t */\n\tsp = &Maze[0][0];\n\twhile (sp < &Maze[HEIGHT - 1][WIDTH])\n\t\t*sp++ = DOOR;\n\n\ty = rand_num(DBOUND - UBOUND) + UBOUND;\n\tx = rand_num(RBOUND - LBOUND) + LBOUND;\n\tdig(y, x);\t\t\t\t/* Dig out the maze */\n\tremap();\n}\n\n# define\tNPERM\t24\n# define\tNDIR\t4\n\nint\tdirs[NPERM][NDIR] = {\n\t\t{0,1,2,3},\t{3,0,1,2},\t{0,2,3,1},\t{0,3,2,1},\n\t\t{1,0,2,3},\t{2,3,0,1},\t{0,2,1,3},\t{2,3,1,0},\n\t\t{1,0,3,2},\t{1,2,0,3},\t{3,1,2,0},\t{2,0,3,1},\n\t\t{1,3,0,2},\t{0,3,1,2},\t{1,3,2,0},\t{2,0,1,3},\n\t\t{0,1,3,2},\t{3,1,0,2},\t{2,1,0,3},\t{1,2,3,0},\n\t\t{2,1,3,0},\t{3,0,2,1},\t{3,2,0,1},\t{3,2,1,0}\n\t};\n\nint\tincr[NDIR][2] = {\n\t\t{0, 1}, {1, 0}, {0, -1}, {-1, 0}\n\t};\n\ndig(y, x)\nint\ty, x;\n{\n\tregister int\t*dp;\n\tregister int\t*ip;\n\tregister int\tny, nx;\n\tregister int\t*endp;\n\n\tMaze[y][x] = SPACE;\t\t\t/* Clear this spot */\n\tdp = dirs[rand_num(NPERM)];\n\tendp = &dp[NDIR];\n\twhile (dp < endp) {\n\t\tip = &incr[*dp++][0];\n\t\tny = y + *ip++;\n\t\tnx = x + *ip;\n\t\tif (candig(ny, nx))\n\t\t\tdig(ny, nx);\n\t}\n}\n\n/*\n * candig:\n *\tIs it legal to clear this spot?\n */\ncandig(y, x)\nregister int\ty, x;\n{\n\tregister int\ti;\n\n\tif (ODD(x) && ODD(y))\n\t\treturn FALSE;\t\t/* can't touch ODD spots */\n\n\tif (y < UBOUND || y >= DBOUND)\n\t\treturn FALSE;\t\t/* Beyond vertical bounds, NO */\n\tif (x < LBOUND || x >= RBOUND)\n\t\treturn FALSE;\t\t/* Beyond horizontal bounds, NO */\n\n\tif (ISCLEAR(y, x))\n\t\treturn FALSE;\t\t/* Already clear, NO */\n\n\ti = ISCLEAR(y, x + 1);\n\ti += ISCLEAR(y, x - 1);\n\tif (i > 1)\n\t\treturn FALSE;\t\t/* Introduces cycle, NO */\n\ti += ISCLEAR(y + 1, x);\n\tif (i > 1)\n\t\treturn FALSE;\t\t/* Introduces cycle, NO */\n\ti += ISCLEAR(y - 1, x);\n\tif (i > 1)\n\t\treturn FALSE;\t\t/* Introduces cycle, NO */\n\n\treturn TRUE;\t\t\t/* OK */\n}\n\nremap()\n{\n\tregister int\ty, x;\n\tregister char\t*sp;\n\tregister int\tstat;\n\n\tfor (y = 0; y < HEIGHT; y++)\n\t\tfor (x = 0; x < WIDTH; x++) {\n\t\t\tsp = &Maze[y][x];\n\t\t\tif (*sp == SPACE)\n\t\t\t\tcontinue;\n\t\t\tstat = 0;\n\t\t\tif (y - 1 >= 0 && Maze[y - 1][x] != SPACE)\n\t\t\t\tstat |= NORTH;\n\t\t\tif (y + 1 < HEIGHT && Maze[y + 1][x] != SPACE)\n\t\t\t\tstat |= SOUTH;\n\t\t\tif (x + 1 < WIDTH && Maze[y][x + 1] != SPACE)\n\t\t\t\tstat |= EAST;\n\t\t\tif (x - 1 >= 0 && Maze[y][x - 1] != SPACE)\n\t\t\t\tstat |= WEST;\n\t\t\tswitch (stat) {\n\t\t\t  case WEST | EAST:\n\t\t\t\t*sp = WALL1;\n\t\t\t\tbreak;\n\t\t\t  case NORTH | SOUTH:\n\t\t\t\t*sp = WALL2;\n\t\t\t\tbreak;\n\t\t\t  case 0:\n# ifdef RANDOM\n\t\t\t\t*sp = DOOR;\n# endif RANDOM\n# ifdef REFLECT\n\t\t\t\t*sp = rand_num(2) ? WALL4 : WALL5;\n# endif REFLECT\n\t\t\t\tbreak;\n\t\t\t  default:\n\t\t\t\t*sp = WALL3;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\tbcopy((char *) Maze, (char *) Orig_maze, sizeof Maze);\n}\n"
  },
  {
    "path": "games/hunt/pathname.c",
    "content": "/*\n *  Hunt\n *  Copyright (c) 1985 Conrad C. Huang, Gregory S. Couch, Kenneth C.R.C. Arnold\n *  San Francisco, California\n *\n *  Copyright (c) 1985 Regents of the University of California.\n *  All rights reserved.  The Berkeley software License Agreement\n *  specifies the terms and conditions for redistribution.\n */\n\n/*\n * There is no particular significance to the numbers assigned\n * to Test_port and Sock_port.  They're just random numbers greater\n * than then range reserved for privileged sockets.\n */\n\n# ifdef DEBUG\n\nchar\t*Driver =\t\"/va/conrad/games/src/hunt/hunt.driver.dbg\";\n# ifdef INTERNET\nint\tTest_port =\t('h' << 8) | 't';\nint\tSock_port =\t('h' << 8) | 's';\n# else INTERNET\nchar\t*Sock_name =\t\"/tmp/hunt\";\n# endif INTERNET\n\n# else DEBUG\n\nchar\t*Driver =\t\"/usr/games/lib/hunt.driver\";\n# ifdef INTERNET\nint\tTest_port =\t('h' << 8) | 't';\nint\tSock_port =\t('h' << 8) | 's';\n# else INTERNET\nchar\t*Sock_name =\t\"/tmp/hunt\";\n# endif INTERNET\n\n# endif DEBUG\n"
  },
  {
    "path": "games/hunt/playit.c",
    "content": "/*\n *  Hunt\n *  Copyright (c) 1985 Conrad C. Huang, Gregory S. Couch, Kenneth C.R.C. Arnold\n *  San Francisco, California\n *\n *  Copyright (c) 1985 Regents of the University of California.\n *  All rights reserved.  The Berkeley software License Agreement\n *  specifies the terms and conditions for redistribution.\n */\n\n# include\t<curses.h>\n# include\t<ctype.h>\n# include\t<signal.h>\n# include\t<errno.h>\n# include\t\"hunt.h\"\n# include\t<sys/file.h>\n\n# undef  CTRL\n# define CTRL(x)\t('x' & 037)\n\nint\t\tinput();\nstatic int\tnchar_send;\nstatic int\tin\t= FREAD;\nchar\t\tscreen[24][80], blanks[80];\nint\t\tcur_row, cur_col;\n# ifdef OTTO\nint\t\tOtto_count;\nint\t\tOtto_mode;\nstatic int\totto_y, otto_x;\nstatic char\totto_face;\n# endif OTTO\n\n# define\tMAX_SEND\t5\n\n/*\n * ibuf is the input buffer used for the stream from the driver.\n * It is small because we do not check for user input when there\n * are characters in the input buffer.\n */\nstatic char\tibuf[20];\n\n#define\tGETCHR(fd)\t(--(fd)->_cnt >= 0 ? *(fd)->_ptr++&0377 : getchr(fd))\n\n/*\n * playit:\n *\tPlay a given game, handling all the curses commands from\n *\tthe driver.\n */\nplayit()\n{\n\tregister FILE\t\t*inf;\n\tregister int\t\tch;\n\tregister unsigned int\ty, x;\n\textern int\t\tMaster_pid;\n\textern int\t\terrno;\n\textern int\t\t_putchar();\n\n\terrno = 0;\n\twhile ((inf = fdopen(Socket, \"r\")) == NULL)\n\t\tif (errno == EINTR)\n\t\t\terrno = 0;\n\t\telse {\n\t\t\tperror(\"fdopen of socket\");\n\t\t\texit(1);\n\t\t}\n\tsetbuffer(inf, ibuf, sizeof ibuf);\n\tMaster_pid = getw(inf);\n\tif (Master_pid == 0 || Master_pid == EOF) {\n\t\tbad_con();\n\t\t/* NOTREACHED */\n\t}\n# ifdef OTTO\n\tOtto_count = 0;\n# endif OTTO\n\tnchar_send = MAX_SEND;\n\twhile ((ch = GETCHR(inf)) != EOF) {\n# ifdef DEBUG\n\t\tfputc(ch, stderr);\n# endif DEBUG\n\t\tswitch (ch & 0377) {\n\t\t  case MOVE:\n\t\t\ty = GETCHR(inf);\n\t\t\tx = GETCHR(inf);\n\t\t\tmvcur(cur_row, cur_col, y, x);\n\t\t\tcur_row = y;\n\t\t\tcur_col = x;\n\t\t\tbreak;\n\t\t  case ADDCH:\n\t\t\tch = GETCHR(inf);\n# ifdef OTTO\n\t\t\tswitch (ch) {\n\n\t\t\tcase '<':\n\t\t\tcase '>':\n\t\t\tcase '^':\n\t\t\tcase 'v':\n\t\t\t\totto_face = ch;\n\t\t\t\tgetyx(stdscr, otto_y, otto_x);\n\t\t\t\tbreak;\n\t\t\t}\n# endif OTTO\n\t\t\tput_ch(ch);\n\t\t\tbreak;\n\t\t  case CLRTOEOL:\n\t\t\tclear_eol();\n\t\t\tbreak;\n\t\t  case CLEAR:\n\t\t\tclear_screen();\n\t\t\tbreak;\n\t\t  case REFRESH:\n\t\t\tfflush(stdout);\n\t\t\tbreak;\n\t\t  case REDRAW:\n\t\t\tredraw_screen();\n\t\t\tfflush(stdout);\n\t\t\tbreak;\n\t\t  case ENDWIN:\n\t\t\tfflush(stdout);\n\t\t\tif ((ch = GETCHR(inf)) == LAST_PLAYER)\n\t\t\t\tLast_player = TRUE;\n\t\t\tch = EOF;\n\t\t\tgoto out;\n\t\t  case BELL:\n\t\t\tputchar(CTRL(G));\n\t\t\tbreak;\n\t\t  case READY:\n\t\t\t(void) fflush(stdout);\n\t\t\tif (nchar_send < 0)\n\t\t\t\t(void) ioctl(fileno(stdin), TIOCFLUSH, &in);\n\t\t\tnchar_send = MAX_SEND;\n# ifndef OTTO\n\t\t\t(void) GETCHR(inf);\n# else OTTO\n\t\t\tOtto_count -= (GETCHR(inf) & 255);\n\t\t\tif (!Am_monitor) {\n# ifdef DEBUG\n\t\t\t\tfputc('0' + Otto_count, stderr);\n# endif DEBUG\n\t\t\t\tif (Otto_count == 0 && Otto_mode)\n\t\t\t\t\totto(otto_y, otto_x, otto_face);\n\t\t\t}\n# endif OTTO\n\t\t\tbreak;\n\t\t  default:\n# ifdef OTTO\n\t\t\tswitch (ch) {\n\n\t\t\tcase '<':\n\t\t\tcase '>':\n\t\t\tcase '^':\n\t\t\tcase 'v':\n\t\t\t\totto_face = ch;\n\t\t\t\tgetyx(stdscr, otto_y, otto_x);\n\t\t\t\tbreak;\n\t\t\t}\n# endif OTTO\n\t\t\tput_ch(ch);\n\t\t\tbreak;\n\t\t}\n\t}\nout:\n\t(void) fclose(inf);\n}\n\n/*\n * getchr:\n *\tGrab input and pass it along to the driver\n *\tReturn any characters from the driver\n *\tWhen this routine is called by GETCHR, we already know there are\n *\tno characters in the input buffer.\n */\ngetchr(fd)\nregister FILE\t*fd;\n{\n\tlong\tnchar;\n\tlong\treadfds, s_readfds;\n\tint\tdriver_mask, stdin_mask;\n\tint\tnfds, s_nfds;\n\n\tdriver_mask = 1L << fileno(fd);\n\tstdin_mask = 1L << fileno(stdin);\n\ts_readfds = driver_mask | stdin_mask;\n\ts_nfds = (driver_mask > stdin_mask) ? driver_mask : stdin_mask;\n\ts_nfds++;\n\none_more_time:\n\tdo {\n\t\terrno = 0;\n\t\treadfds = s_readfds;\n\t\tnfds = s_nfds;\n# ifndef OLDIPC\n\t\tnfds = select(nfds, &readfds, NULL, NULL, NULL);\n# else OLDIPC\n\t\tnfds = select(nfds, &readfds, (int *) NULL, 32767);\n# endif OLDIPC\n\t} while (nfds <= 0 && errno == EINTR);\n\n\tif (readfds & stdin_mask)\n\t\tsend_stuff();\n\tif ((readfds & driver_mask) == 0)\n\t\tgoto one_more_time;\n\treturn _filbuf(fd);\n}\n\n/*\n * send_stuff:\n *\tSend standard input characters to the driver\n */\nsend_stuff()\n{\n\tregister int\tcount;\n\tregister char\t*sp, *nsp;\n\tstatic char\tinp[sizeof Buf];\n\textern char\tmap_key[256];\n\n\tcount = read(fileno(stdin), Buf, sizeof Buf);\n\tif (count <= 0)\n\t\treturn;\n\tif (nchar_send <= 0) {\n\t\t(void) write(1, \"\\7\", 1);\n\t\treturn;\n\t}\n\n\t/*\n\t * look for 'q'uit commands; if we find one,\n\t * confirm it.  If it is not confirmed, strip\n\t * it out of the input\n\t */\n\tBuf[count] = '\\0';\n\tnsp = inp;\n\tfor (sp = Buf; *sp != '\\0'; sp++)\n\t\tif ((*nsp = map_key[*sp]) == 'q')\n\t\t\tintr();\n# ifdef OTTO\n\t\telse if (*nsp == CTRL(O))\n\t\t\tOtto_mode = !Otto_mode;\n# endif OTTO\n\t\telse\n\t\t\tnsp++;\n\tcount = nsp - inp;\n\tif (count) {\n# ifdef OTTO\n\t\tOtto_count += count;\n# endif OTTO\n\t\tnchar_send -= count;\n\t\tif (nchar_send < 0)\n\t\t\tcount += nchar_send;\n\t\t(void) write(Socket, inp, count);\n\t}\n}\n\n/*\n * quit:\n *\tHandle the end of the game when the player dies\n */\nquit()\n{\n\tregister int\texplain, ch;\n\n\tif (Last_player)\n\t\treturn TRUE;\n# ifdef OTTO\n\tif (Otto_mode)\n\t\treturn FALSE;\n# endif OTTO\n\tmvcur(cur_row, cur_col, HEIGHT, 0);\n\tcur_row = HEIGHT;\n\tcur_col = 0;\n\tput_str(\"Re-enter game? \");\n\tclear_eol();\n\tfflush(stdout);\n\texplain = FALSE;\n\tfor (;;) {\n\t\tif (isupper(ch = getchar()))\n\t\t\tch = tolower(ch);\n\t\tif (ch == 'y') {\n\t\t\tsleep(2);\n\t\t\treturn FALSE;\n\t\t}\n\t\telse if (ch == 'n')\n\t\t\treturn TRUE;\n\t\t(void) putchar(CTRL(G));\n\t\tif (!explain) {\n\t\t\tput_str(\"(Y or N) \");\n\t\t\texplain = TRUE;\n\t\t}\n\t\tfflush(stdout);\n\t}\n}\n\nput_ch(ch)\n\tchar\tch;\n{\n\tif (!isprint(ch)) {\n\t\tfprintf(stderr, \"r,c,ch: %d,%d,%d\", cur_row, cur_col, ch);\n\t\treturn;\n\t}\n\tscreen[cur_row][cur_col] = ch;\n\tputchar(ch);\n\tif (++cur_col >= COLS) {\n\t\tif (!AM || XN)\n\t\t\tputchar('\\n');\n\t\tcur_col = 0;\n\t\tif (++cur_row >= LINES)\n\t\t\tcur_row = LINES;\n\t}\n}\n\nput_str(s)\n\tchar\t*s;\n{\n\twhile (*s)\n\t\tput_ch(*s++);\n}\n\nclear_screen()\n{\n\tregister int\ti;\n\tint _putchar();\n\n\tif (blanks[0] == '\\0')\n\t\tfor (i = 0; i < 80; i++)\n\t\t\tblanks[i] = ' ';\n\n\tif (CL != NULL) {\n\t\ttputs(CL, LINES, _putchar);\n\t\tfor (i = 0; i < 24; i++)\n\t\t\tbcopy(blanks, screen[i], 80);\n\t} else {\n\t\tfor (i = 0; i < 24; i++) {\n\t\t\tmvcur(cur_row, cur_col, i, 0);\n\t\t\tcur_row = i;\n\t\t\tcur_col = 0;\n\t\t\tclear_eol();\n\t\t}\n\t\tmvcur(cur_row, cur_col, 0, 0);\n\t}\n\tcur_row = cur_col = 0;\n}\n\nclear_eol()\n{\n\tint _putchar();\n\n\tif (CE != NULL)\n\t\ttputs(CE, 1, _putchar);\n\telse {\n\t\tfwrite(blanks, sizeof (char), 80 - cur_col, stdout);\n\t\tif (COLS != 80)\n\t\t\tmvcur(cur_row, 80, cur_row, cur_col);\n\t\telse if (AM)\n\t\t\tmvcur(cur_row + 1, 0, cur_row, cur_col);\n\t\telse\n\t\t\tmvcur(cur_row, 79, cur_row, cur_col);\n\t}\n\tbcopy(blanks, &screen[cur_row][cur_col], 80 - cur_col);\n}\n\nredraw_screen()\n{\n\tregister int\ti;\n\tstatic int\tfirst = 1;\n\n\tif (first) {\n\t\tif ((curscr = newwin(24, 80, 0, 0)) == NULL) {\n\t\t\tfprintf(stderr, \"Can't create curscr\\n\");\n\t\t\texit(1);\n\t\t}\n\t\tfor (i = 0; i < 24; i++)\n\t\t\tcurscr->_y[i] = screen[i];\n\t\tfirst = 0;\n\t}\n\tcurscr->_cury = cur_row;\n\tcurscr->_curx = cur_col;\n\twrefresh(curscr);\n#ifdef\tNOCURSES\n\tmvcur(cur_row, cur_col, 0, 0);\n\tfor (i = 0; i < 23; i++) {\n\t\tfwrite(screen[i], sizeof (char), 80, stdout);\n\t\tif (COLS > 80 || (COLS == 80 && !AM))\n\t\t\tputchar('\\n');\n\t}\n\tfwrite(screen[23], sizeof (char), 79, stdout);\n\tmvcur(23, 79, cur_row, cur_col);\n#endif\n}\n"
  },
  {
    "path": "games/hunt/shots.c",
    "content": "/*\n *  Hunt\n *  Copyright (c) 1985 Conrad C. Huang, Gregory S. Couch, Kenneth C.R.C. Arnold\n *  San Francisco, California\n *\n *  Copyright (c) 1985 Regents of the University of California.\n *  All rights reserved.  The Berkeley software License Agreement\n *  specifies the terms and conditions for redistribution.\n */\n\n# include\t\"hunt.h\"\n# include\t<signal.h>\n\n# define\tPLUS_DELTA(x, max)\tif (x < max) x++; else x--\n# define\tMINUS_DELTA(x, min)\tif (x > min) x--; else x++\n\n/*\n * moveshots:\n *\tMove the shots already in the air, taking explosions into account\n */\nmoveshots()\n{\n\tregister BULLET\t*bp, *next;\n\tregister PLAYER\t*pp;\n\tregister int\tx, y;\n\tregister BULLET\t*blist;\n\tregister int\ti;\n\n\trollexpl();\n\tif (Bullets == NULL)\n\t\tgoto ret;\n\n\t/*\n\t * First we move through the bullet list BULSPD times, looking\n\t * for things we may have run into.  If we do run into\n\t * something, we set up the explosion and disappear, checking\n\t * for damage to any player who got in the way.\n\t */\n\n\tblist = Bullets;\n\tBullets = NULL;\n\tfor (bp = blist; bp != NULL; bp = next) {\n\t\tnext = bp->b_next;\n\t\tx = bp->b_x;\n\t\ty = bp->b_y;\n\t\tMaze[y][x] = bp->b_over;\n\t\tfor (pp = Player; pp < End_player; pp++)\n\t\t\tcheck(pp, y, x);\n# ifdef MONITOR\n\t\tfor (pp = Monitor; pp < End_monitor; pp++)\n\t\t\tcheck(pp, y, x);\n# endif MONITOR\n\n\t\tfor (i = 0; i < BULSPD; i++) {\n\t\t\tif (bp->b_expl)\n\t\t\t\tbreak;\n\n\t\t\tx = bp->b_x;\n\t\t\ty = bp->b_y;\n\n\t\t\tswitch (bp->b_face) {\n\t\t\t  case LEFTS:\n\t\t\t\tx--;\n\t\t\t\tbreak;\n\t\t\t  case RIGHT:\n\t\t\t\tx++;\n\t\t\t\tbreak;\n\t\t\t  case ABOVE:\n\t\t\t\ty--;\n\t\t\t\tbreak;\n\t\t\t  case BELOW:\n\t\t\t\ty++;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tswitch (Maze[y][x]) {\n\t\t\t  case SHOT:\n\t\t\t\tif (rand_num(100) < 5) {\n\t\t\t\t\tzapshot(Bullets, bp);\n\t\t\t\t\tzapshot(next, bp);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t  case GRENADE:\n\t\t\t\tif (rand_num(100) < 10) {\n\t\t\t\t\tzapshot(Bullets, bp);\n\t\t\t\t\tzapshot(next, bp);\n\t\t\t\t}\n\t\t\t\tbreak;\n# ifdef\tREFLECT\n\t\t\t  case WALL4:\t/* reflecting walls */\n\t\t\t\tswitch (bp->b_face) {\n\t\t\t\t  case LEFTS:\n\t\t\t\t\tbp->b_face = BELOW;\n\t\t\t\t\tbreak;\n\t\t\t\t  case RIGHT:\n\t\t\t\t\tbp->b_face = ABOVE;\n\t\t\t\t\tbreak;\n\t\t\t\t  case ABOVE:\n\t\t\t\t\tbp->b_face = RIGHT;\n\t\t\t\t\tbreak;\n\t\t\t\t  case BELOW:\n\t\t\t\t\tbp->b_face = LEFTS;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tMaze[y][x] = WALL5;\n# ifdef MONITOR\n\t\t\t\tfor (pp = Monitor; pp < End_monitor; pp++)\n\t\t\t\t\tcheck(pp, y, x);\n# endif MONITOR\n\t\t\t\tbreak;\n\t\t\t  case WALL5:\n\t\t\t\tswitch (bp->b_face) {\n\t\t\t\t  case LEFTS:\n\t\t\t\t\tbp->b_face = ABOVE;\n\t\t\t\t\tbreak;\n\t\t\t\t  case RIGHT:\n\t\t\t\t\tbp->b_face = BELOW;\n\t\t\t\t\tbreak;\n\t\t\t\t  case ABOVE:\n\t\t\t\t\tbp->b_face = LEFTS;\n\t\t\t\t\tbreak;\n\t\t\t\t  case BELOW:\n\t\t\t\t\tbp->b_face = RIGHT;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tMaze[y][x] = WALL4;\n# ifdef MONITOR\n\t\t\t\tfor (pp = Monitor; pp < End_monitor; pp++)\n\t\t\t\t\tcheck(pp, y, x);\n# endif MONITOR\n\t\t\t\tbreak;\n# endif REFLECT\n# ifdef RANDOM\n\t\t\t  case DOOR:\n\t\t\t\tswitch (rand_num(4)) {\n\t\t\t\t  case 0:\n\t\t\t\t\tbp->b_face = ABOVE;\n\t\t\t\t\tbreak;\n\t\t\t\t  case 1:\n\t\t\t\t\tbp->b_face = BELOW;\n\t\t\t\t\tbreak;\n\t\t\t\t  case 2:\n\t\t\t\t\tbp->b_face = LEFTS;\n\t\t\t\t\tbreak;\n\t\t\t\t  case 3:\n\t\t\t\t\tbp->b_face = RIGHT;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tbreak;\n# endif RANDOM\n\t\t\t  case LEFTS:\n\t\t\t  case RIGHT:\n\t\t\t  case BELOW:\n\t\t\t  case ABOVE:\n# ifdef FLY\n\t\t\t  case FLYER:\n# endif FLY\n\t\t\t\t/*\n\t\t\t\t * give the person a chance to catch a\n\t\t\t\t * grenade if s/he is facing it\n\t\t\t\t */\n\t\t\t\tif (rand_num(100) < 10\n\t\t\t\t    && opposite(bp->b_face, Maze[y][x])) {\n\t\t\t\t\tif (bp->b_owner != NULL)\n\t\t\t\t\t\tmessage(bp->b_owner,\n\t\t\t\t\t\t\"Your charge was absorbed!\");\n\t\t\t\t\tpp = play_at(y, x);\n\t\t\t\t\tpp->p_ammo += bp->b_charge;\n\t\t\t\t\t(void) sprintf(Buf,\n\t\t\t\t\t\t\"Absorbed charge (good shield!)\");\n\t\t\t\t\tmessage(pp, Buf);\n\t\t\t\t\tfree((char *) bp);\n\t\t\t\t\t(void) sprintf(Buf, \"%3d\", pp->p_ammo);\n\t\t\t\t\tcgoto(pp, STAT_AMMO_ROW, STAT_VALUE_COL);\n\t\t\t\t\toutstr(pp, Buf, 3);\n\t\t\t\t\tgoto next_bullet;\n\t\t\t\t}\n\t\t\t\t/* FALLTHROUGH */\n# ifndef RANDOM\n\t\t\t  case DOOR:\n# endif RANDOM\n\t\t\t  case WALL1:\n\t\t\t  case WALL2:\n\t\t\t  case WALL3:\n\t\t\t\tbp->b_expl = TRUE;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tbp->b_x = x;\n\t\t\tbp->b_y = y;\n\t\t}\n\n\t\tbp->b_next = Bullets;\n\t\tBullets = bp;\nnext_bullet:\n\t\t;\n\t}\n\n\tblist = Bullets;\n\tBullets = NULL;\n\tfor (bp = blist; bp != NULL; bp = next) {\n\t\tnext = bp->b_next;\n\t\tif (!bp->b_expl) {\n\t\t\tsave_bullet(bp);\n# ifdef MONITOR\n\t\t\tfor (pp = Monitor; pp < End_monitor; pp++)\n\t\t\t\tcheck(pp, bp->b_y, bp->b_x);\n# endif MONITOR\n\t\t\tcontinue;\n\t\t}\n\n\t\tchkshot(bp);\n\t\tfree((char *) bp);\n\t}\n\tfor (pp = Player; pp < End_player; pp++)\n\t\tMaze[pp->p_y][pp->p_x] = pp->p_face;\nret:\n\tfor (pp = Player; pp < End_player; pp++) {\n# ifdef FLY\n\t\tif (pp->p_flying >= 0) {\n\t\t\tMaze[pp->p_y][pp->p_x] = pp->p_over;\n\t\t\tx = pp->p_x + pp->p_flyx;\n\t\t\ty = pp->p_y + pp->p_flyy;\n\t\t\tif (x < 1) {\n\t\t\t\tx = 1 - x;\n\t\t\t\tpp->p_flyx = -pp->p_flyx;\n\t\t\t}\n\t\t\telse if (x > WIDTH - 2) {\n\t\t\t\tx = (WIDTH - 2) - (x - (WIDTH - 2));\n\t\t\t\tpp->p_flyx = -pp->p_flyx;\n\t\t\t}\n\t\t\tif (y < 1) {\n\t\t\t\ty = 1 - y;\n\t\t\t\tpp->p_flyy = -pp->p_flyy;\n\t\t\t}\n\t\t\telse if (y > HEIGHT - 2) {\n\t\t\t\ty = (HEIGHT - 2) - (y - (HEIGHT - 2));\n\t\t\t\tpp->p_flyy = -pp->p_flyy;\n\t\t\t}\nagain:\t\t\tswitch (Maze[y][x]) {\n\t\t\t  case LEFTS:\n\t\t\t  case RIGHT:\n\t\t\t  case ABOVE:\n\t\t\t  case BELOW:\n\t\t\t  case FLYER:\n\t\t\t\tswitch (rand_num(4)) {\n\t\t\t\t  case 0:\n\t\t\t\t\tPLUS_DELTA(x, WIDTH - 2);\n\t\t\t\t\tbreak;\n\t\t\t\t  case 1:\n\t\t\t\t\tMINUS_DELTA(x, 1);\n\t\t\t\t\tbreak;\n\t\t\t\t  case 2:\n\t\t\t\t\tPLUS_DELTA(y, HEIGHT - 2);\n\t\t\t\t\tbreak;\n\t\t\t\t  case 3:\n\t\t\t\t\tMINUS_DELTA(y, 1);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tgoto again;\n\t\t\t  case WALL1:\n\t\t\t  case WALL2:\n\t\t\t  case WALL3:\n# ifdef\tREFLECT\n\t\t\t  case WALL4:\n\t\t\t  case WALL5:\n# endif REFLECT\n# ifdef\tRANDOM\n\t\t\t  case DOOR:\n# endif\tRANDOM\n\t\t\t\tif (pp->p_flying == 0)\n\t\t\t\t\tpp->p_flying++;\n\t\t\t\tbreak;\n\t\t\t  case MINE:\n\t\t\t\tcheckdam(pp, NULL, NULL, MINDAM, MINE);\n\t\t\t\tMaze[y][x] = SPACE;\n\t\t\t\tbreak;\n\t\t\t  case GMINE:\n\t\t\t\tcheckdam(pp, NULL, NULL, MINDAM, GMINE);\n\t\t\t\tcheckdam(pp, NULL, NULL, MINDAM, GMINE);\n\t\t\t\tMaze[y][x] = SPACE;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tpp->p_y = y;\n\t\t\tpp->p_x = x;\n\t\t\tpp->p_over = Maze[y][x];\n\t\t\tif (pp->p_flying-- == 0) {\n\t\t\t\tcheckdam(pp, NULL, NULL,\n\t\t\t\t\trand_num(pp->p_damage / 5), FALL);\n\t\t\t\trand_face(pp);\n\t\t\t\tshowstat(pp);\n\t\t\t}\n\t\t\tMaze[y][x] = pp->p_face;\n\t\t\tshowexpl(y, x, pp->p_face);\n\t\t}\n# endif FLY\n\t\tsendcom(pp, REFRESH);\t/* Flush out the explosions */\n\t\tlook(pp);\n\t\tsendcom(pp, REFRESH);\n\t}\n# ifdef MONITOR\n\tfor (pp = Monitor; pp < End_monitor; pp++)\n\t\tsendcom(pp, REFRESH);\n# endif MONITOR\n\n# ifdef CONSTANT_MOVE\n\tif (Bullets != NULL) {\n\t\tbul_alarm(1);\n\t\treturn;\n\t}\n\tfor (i = 0; i < EXPLEN; i++)\n\t\tif (Expl[i] != NULL) {\n\t\t\tbul_alarm(1);\n\t\t\treturn;\n\t\t}\n\tbul_alarm(0);\n# endif CONSTANT_MOVE\n\n\treturn;\n}\n\nsave_bullet(bp)\nregister BULLET\t*bp;\n{\n\tbp->b_over = Maze[bp->b_y][bp->b_x];\n\tswitch (bp->b_over) {\n\t  case SHOT:\n\t  case GRENADE:\n\t  case SATCHEL:\n\t  case BOMB:\n# ifdef OOZE\n\t  case SLIME:\n# ifdef VOLCANO\n\t  case LAVA:\n# endif VOLCANO\n# endif OOZE\n\t\tfind_under(Bullets, bp);\n\t\tbreak;\n\t}\n\n\tswitch (bp->b_over) {\n\t  case LEFTS:\n\t  case RIGHT:\n\t  case ABOVE:\n\t  case BELOW:\n# ifdef FLY\n\t  case FLYER:\n# endif FLY\n\t\tmark_player(bp);\n\t\tbreak;\n\t\t\n\t  default:\n\t\tMaze[bp->b_y][bp->b_x] = bp->b_type;\n\t\tbreak;\n\t}\n\n\tbp->b_next = Bullets;\n\tBullets = bp;\n}\n\n/*\n * chkshot\n *\tHandle explosions\n */\nchkshot(bp)\nregister BULLET\t*bp;\n{\n\tregister int\ty, x;\n\tregister int\tdy, dx, absdy;\n\tregister int\tdelta, damage;\n\tregister char\texpl;\n\tregister PLAYER\t*pp;\n\n\tswitch (bp->b_type) {\n\t  case SHOT:\n\t  case MINE:\n\t\tdelta = 0;\n\t\tbreak;\n\t  case GRENADE:\n\t  case GMINE:\n\t\tdelta = 1;\n\t\tbreak;\n\t  case SATCHEL:\n\t\tdelta = 2;\n\t\tbreak;\n\t  case BOMB:\n\t\tdelta = 3;\n\t\tbreak;\n# ifdef\tOOZE\n\t  case SLIME:\n# ifdef VOLCANO\n\t  case LAVA:\n# endif VOLCANO\n\t\tchkslime(bp);\n\t\treturn;\n# endif\tOOZE\n\t}\n\tfor (y = bp->b_y - delta; y <= bp->b_y + delta; y++) {\n\t\tif (y < 0 || y >= HEIGHT)\n\t\t\tcontinue;\n\t\tdy = y - bp->b_y;\n\t\tabsdy = (dy < 0) ? -dy : dy;\n\t\tfor (x = bp->b_x - delta; x <= bp->b_x + delta; x++) {\n\t\t\tif (x < 0 || x >= WIDTH)\n\t\t\t\tcontinue;\n\t\t\tdx = x - bp->b_x;\n\t\t\tif (dx == 0)\n\t\t\t\texpl = (dy == 0) ? '*' : '|';\n\t\t\telse if (dy == 0)\n\t\t\t\texpl = '-';\n\t\t\telse if (dx == dy)\n\t\t\t\texpl = '\\\\';\n\t\t\telse if (dx == -dy)\n\t\t\t\texpl = '/';\n\t\t\telse\n\t\t\t\texpl = '*';\n\t\t\tshowexpl(y, x, expl);\n\t\t\tswitch (Maze[y][x]) {\n\t\t\t  case LEFTS:\n\t\t\t  case RIGHT:\n\t\t\t  case ABOVE:\n\t\t\t  case BELOW:\n# ifdef FLY\n\t\t\t  case FLYER:\n# endif FLY\n\t\t\t\tif (dx < 0)\n\t\t\t\t\tdx = -dx;\n\t\t\t\tif (absdy > dx)\n\t\t\t\t\tdamage = delta - absdy + 1;\n\t\t\t\telse\n\t\t\t\t\tdamage = delta - dx + 1;\n\t\t\t\tpp = play_at(y, x);\n\t\t\t\twhile (damage-- > 0)\n\t\t\t\t\tcheckdam(pp, bp->b_owner, bp->b_score,\n\t\t\t\t\t\tMINDAM, bp->b_type);\n\t\t\t\tbreak;\n\t\t\t  case GMINE:\n\t\t\t  case MINE:\n\t\t\t\tadd_shot((Maze[y][x] == GMINE) ?\n\t\t\t\t\tGRENADE : SHOT,\n\t\t\t\t\ty, x, LEFTS,\n\t\t\t\t\t(Maze[y][x] == GMINE) ?\n\t\t\t\t\tGRENREQ : BULREQ,\n\t\t\t\t\t(PLAYER *) NULL, TRUE, SPACE);\n\t\t\t\tMaze[y][x] = SPACE;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n}\n\n# ifdef\tOOZE\n/*\n * chkslime:\n *\thandle slime shot exploding\n */\nchkslime(bp)\nregister BULLET\t*bp;\n{\n\tregister BULLET\t*nbp;\n\n\tswitch (Maze[bp->b_y][bp->b_x]) {\n\t  case WALL1:\n\t  case WALL2:\n\t  case WALL3:\n# ifdef\tREFLECT\n\t  case WALL4:\n\t  case WALL5:\n# endif REFLECT\n# ifdef\tRANDOM\n\t  case DOOR:\n# endif\tRANDOM\n\t\tswitch (bp->b_face) {\n\t\t  case LEFTS:\n\t\t\tbp->b_x++;\n\t\t\tbreak;\n\t\t  case RIGHT:\n\t\t\tbp->b_x--;\n\t\t\tbreak;\n\t\t  case ABOVE:\n\t\t\tbp->b_y++;\n\t\t\tbreak;\n\t\t  case BELOW:\n\t\t\tbp->b_y--;\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\t}\n\tnbp = (BULLET *) malloc(sizeof (BULLET));\n\t*nbp = *bp;\n# ifdef VOLCANO\n\tmoveslime(nbp, nbp->b_type == SLIME ? SLIMESPEED : LAVASPEED);\n# else VOLCANO\n\tmoveslime(nbp, SLIMESPEED);\n# endif VOLCANO\n}\n\n/*\n * moveslime:\n *\tmove the given slime shot speed times and add it back if\n *\tit hasn't fizzled yet\n */\nmoveslime(bp, speed)\nregister BULLET\t*bp;\nregister int\tspeed;\n{\n\tregister int\ti, j, dirmask, count;\n\tregister PLAYER\t*pp;\n\tregister BULLET\t*nbp;\n\n\tif (speed == 0) {\n\t\tif (bp->b_charge <= 0)\n\t\t\tfree((char *) bp);\n\t\telse\n\t\t\tsave_bullet(bp);\n\t\treturn;\n\t}\n\n# ifdef VOLCANO\n\tshowexpl(bp->b_y, bp->b_x, bp->b_type == LAVA ? LAVA : '*');\n# else VOLCANO\n\tshowexpl(bp->b_y, bp->b_x, '*');\n# endif VOLCANO\n\tswitch (Maze[bp->b_y][bp->b_x]) {\n\t  case LEFTS:\n\t  case RIGHT:\n\t  case ABOVE:\n\t  case BELOW:\n# ifdef FLY\n\t  case FLYER:\n# endif FLY\n\t\tpp = play_at(bp->b_y, bp->b_x);\n\t\tmessage(pp, \"You've been slimed.\");\n\t\tcheckdam(pp, bp->b_owner, bp->b_score, MINDAM, bp->b_type);\n\t\tbreak;\n\t}\n\n\tif (--bp->b_charge <= 0) {\n\t\tfree((char *) bp);\n\t\treturn;\n\t}\n\n\tdirmask = 0;\n\tcount = 0;\n\tswitch (bp->b_face) {\n\t  case LEFTS:\n\t\tif (!iswall(bp->b_y, bp->b_x - 1))\n\t\t\tdirmask |= WEST, count++;\n\t\tif (!iswall(bp->b_y - 1, bp->b_x))\n\t\t\tdirmask |= NORTH, count++;\n\t\tif (!iswall(bp->b_y + 1, bp->b_x))\n\t\t\tdirmask |= SOUTH, count++;\n\t\tif (dirmask == 0)\n\t\t\tif (!iswall(bp->b_y, bp->b_x + 1))\n\t\t\t\tdirmask |= EAST, count++;\n\t\tbreak;\n\t  case RIGHT:\n\t\tif (!iswall(bp->b_y, bp->b_x + 1))\n\t\t\tdirmask |= EAST, count++;\n\t\tif (!iswall(bp->b_y - 1, bp->b_x))\n\t\t\tdirmask |= NORTH, count++;\n\t\tif (!iswall(bp->b_y + 1, bp->b_x))\n\t\t\tdirmask |= SOUTH, count++;\n\t\tif (dirmask == 0)\n\t\t\tif (!iswall(bp->b_y, bp->b_x - 1))\n\t\t\t\tdirmask |= WEST, count++;\n\t\tbreak;\n\t  case ABOVE:\n\t\tif (!iswall(bp->b_y - 1, bp->b_x))\n\t\t\tdirmask |= NORTH, count++;\n\t\tif (!iswall(bp->b_y, bp->b_x - 1))\n\t\t\tdirmask |= WEST, count++;\n\t\tif (!iswall(bp->b_y, bp->b_x + 1))\n\t\t\tdirmask |= EAST, count++;\n\t\tif (dirmask == 0)\n\t\t\tif (!iswall(bp->b_y + 1, bp->b_x))\n\t\t\t\tdirmask |= SOUTH, count++;\n\t\tbreak;\n\t  case BELOW:\n\t\tif (!iswall(bp->b_y + 1, bp->b_x))\n\t\t\tdirmask |= SOUTH, count++;\n\t\tif (!iswall(bp->b_y, bp->b_x - 1))\n\t\t\tdirmask |= WEST, count++;\n\t\tif (!iswall(bp->b_y, bp->b_x + 1))\n\t\t\tdirmask |= EAST, count++;\n\t\tif (dirmask == 0)\n\t\t\tif (!iswall(bp->b_y - 1, bp->b_x))\n\t\t\t\tdirmask |= NORTH, count++;\n\t\tbreak;\n\t}\n\tif (count == 0) {\n\t\t/*\n\t\t * No place to go.  Just sit here for a while and wait\n\t\t * for adjacent squares to clear out.\n\t\t */\n\t\tsave_bullet(bp);\n\t\treturn;\n\t}\n\tif (bp->b_charge < count) {\n\t\t/* Only bp->b_charge paths may be taken */\n\t\twhile (count > bp->b_charge) {\n\t\t\tif (dirmask & WEST)\n\t\t\t\tdirmask &= ~WEST;\n\t\t\telse if (dirmask & EAST)\n\t\t\t\tdirmask &= ~EAST;\n\t\t\telse if (dirmask & NORTH)\n\t\t\t\tdirmask &= ~NORTH;\n\t\t\telse if (dirmask & SOUTH)\n\t\t\t\tdirmask &= ~SOUTH;\n\t\t\tcount--;\n\t\t}\n\t}\n\n\ti = bp->b_charge / count;\n\tj = bp->b_charge % count;\n\tif (dirmask & WEST) {\n\t\tcount--;\n\t\tnbp = create_shot(bp->b_type, bp->b_y, bp->b_x - 1, LEFTS,\n\t\t\ti, bp->b_owner, bp->b_score, TRUE, SPACE);\n\t\tmoveslime(nbp, speed - 1);\n\t}\n\tif (dirmask & EAST) {\n\t\tcount--;\n\t\tnbp = create_shot(bp->b_type, bp->b_y, bp->b_x + 1, RIGHT,\n\t\t\t(count < j) ? i + 1 : i, bp->b_owner, bp->b_score,\n\t\t\tTRUE, SPACE);\n\t\tmoveslime(nbp, speed - 1);\n\t}\n\tif (dirmask & NORTH) {\n\t\tcount--;\n\t\tnbp = create_shot(bp->b_type, bp->b_y - 1, bp->b_x, ABOVE,\n\t\t\t(count < j) ? i + 1 : i, bp->b_owner, bp->b_score,\n\t\t\tTRUE, SPACE);\n\t\tmoveslime(nbp, speed - 1);\n\t}\n\tif (dirmask & SOUTH) {\n\t\tcount--;\n\t\tnbp = create_shot(bp->b_type, bp->b_y + 1, bp->b_x, BELOW,\n\t\t\t(count < j) ? i + 1 : i, bp->b_owner, bp->b_score,\n\t\t\tTRUE, SPACE);\n\t\tmoveslime(nbp, speed - 1);\n\t}\n\n\tfree((char *) bp);\n}\n\n/*\n * iswall:\n *\treturns whether the given location is a wall\n */\niswall(y, x)\nregister int\ty, x;\n{\n\tif (y < 0 || x < 0 || y >= HEIGHT || x >= WIDTH)\n\t\treturn TRUE;\n\tswitch (Maze[y][x]) {\n\t  case WALL1:\n\t  case WALL2:\n\t  case WALL3:\n# ifdef\tREFLECT\n\t  case WALL4:\n\t  case WALL5:\n# endif\tREFLECT\n# ifdef\tRANDOM\n\t  case DOOR:\n# endif\tRANDOM\n# ifdef VOLCANO\n\t  case LAVA:\n# endif VOLCANO\n\t\treturn TRUE;\n\t}\n\treturn FALSE;\n}\n# endif\tOOZE\n\n/*\n * zapshot:\n *\tTake a shot out of the air.\n */\nzapshot(blist, obp)\nregister BULLET\t*blist, *obp;\n{\n\tregister BULLET\t*bp;\n\tregister FLAG\texplode;\n\n\texplode = FALSE;\n\tfor (bp = blist; bp != NULL; bp = bp->b_next) {\n\t\tif (bp->b_x != obp->b_x || bp->b_y != obp->b_y)\n\t\t\tcontinue;\n\t\tif (bp->b_face == obp->b_face)\n\t\t\tcontinue;\n\t\texplode = TRUE;\n\t\tbreak;\n\t}\n\tif (!explode)\n\t\treturn;\n\texplshot(blist, obp->b_y, obp->b_x);\n}\n\n/*\n * explshot -\n *\tMake all shots at this location blow up\n */\nexplshot(blist, y, x)\nregister BULLET\t*blist;\nregister int\ty, x;\n{\n\tregister BULLET\t*bp;\n\n\tfor (bp = blist; bp != NULL; bp = bp->b_next)\n\t\tif (bp->b_x == x && bp->b_y == y) {\n\t\t\tbp->b_expl = TRUE;\n\t\t\tif (bp->b_owner != NULL)\n\t\t\t\tmessage(bp->b_owner, \"Shot intercepted\");\n\t\t}\n}\n\n/*\n * play_at:\n *\tReturn a pointer to the player at the given location\n */\nPLAYER *\nplay_at(y, x)\nregister int\ty, x;\n{\n\tregister PLAYER\t*pp;\n\n\tfor (pp = Player; pp < End_player; pp++)\n\t\tif (pp->p_x == x && pp->p_y == y)\n\t\t\treturn pp;\n\tfprintf(stderr, \"driver: couldn't find player at (%d,%d)\\n\", x, y);\n\tabort();\n\t/* NOTREACHED */\n}\n\n/*\n * opposite:\n *\tReturn TRUE if the bullet direction faces the opposite direction\n *\tof the player in the maze\n */\nopposite(face, dir)\nint\tface;\nchar\tdir;\n{\n\tswitch (face) {\n\t  case LEFTS:\n\t\treturn (dir == RIGHT);\n\t  case RIGHT:\n\t\treturn (dir == LEFTS);\n\t  case ABOVE:\n\t\treturn (dir == BELOW);\n\t  case BELOW:\n\t\treturn (dir == ABOVE);\n\t  default:\n\t\treturn FALSE;\n\t}\n}\n\n/*\n * is_bullet:\n *\tIs there a bullet at the given coordinates?  If so, return\n *\ta pointer to the bullet, otherwise return NULL\n */\nBULLET *\nis_bullet(y, x)\nregister int\ty, x;\n{\n\tregister BULLET\t*bp;\n\n\tfor (bp = Bullets; bp != NULL; bp = bp->b_next)\n\t\tif (bp->b_y == y && bp->b_x == x)\n\t\t\treturn bp;\n\treturn NULL;\n}\n\n/*\n * fixshots:\n *\tchange the underlying character of the shots at a location\n *\tto the given character.\n */\nfixshots(y, x, over)\nregister int\ty, x;\nchar\t\tover;\n{\n\tregister BULLET\t*bp;\n\n\tfor (bp = Bullets; bp != NULL; bp = bp->b_next)\n\t\tif (bp->b_y == y && bp->b_x == x)\n\t\t\tbp->b_over = over;\n}\n\n/*\n * find_under:\n *\tfind the underlying character for a bullet when it lands\n *\ton another bullet.\n */\nfind_under(blist, bp)\nregister BULLET\t*blist, *bp;\n{\n\tregister BULLET\t*nbp;\n\n\tfor (nbp = blist; nbp != NULL; nbp = nbp->b_next)\n\t\tif (bp->b_y == nbp->b_y && bp->b_x == nbp->b_x) {\n\t\t\tbp->b_over = nbp->b_over;\n\t\t\tbreak;\n\t\t}\n}\n\n/*\n * mark_player:\n *\tmark a player as under a shot\n */\nmark_player(bp)\nregister BULLET\t*bp;\n{\n\tregister PLAYER\t*pp;\n\n\tfor (pp = Player; pp < End_player; pp++)\n\t\tif (pp->p_y == bp->b_y && pp->p_x == bp->b_x) {\n\t\t\tpp->p_undershot = TRUE;\n\t\t\tbreak;\n\t\t}\n}\n"
  },
  {
    "path": "games/hunt/terminal.c",
    "content": "/*\n *  Hunt\n *  Copyright (c) 1985 Conrad C. Huang, Gregory S. Couch, Kenneth C.R.C. Arnold\n *  San Francisco, California\n *\n *  Copyright (c) 1985 Regents of the University of California.\n *  All rights reserved.  The Berkeley software License Agreement\n *  specifies the terms and conditions for redistribution.\n */\n\n# include\t\"hunt.h\"\n# define\tTERM_WIDTH\t80\t/* Assume terminals are 80-char wide */\n\n/*\n * cgoto:\n *\tMove the cursor to the given position on the given player's\n *\tterminal.\n */\ncgoto(pp, y, x)\nregister PLAYER\t*pp;\nregister int\ty, x;\n{\n\tif (x == pp->p_curx && y == pp->p_cury)\n\t\treturn;\n\tsendcom(pp, MOVE, y, x);\n\tpp->p_cury = y;\n\tpp->p_curx = x;\n}\n\n/*\n * outch:\n *\tPut out a single character.\n */\noutch(pp, ch)\nregister PLAYER\t*pp;\nchar\t\tch;\n{\n\tif (++pp->p_curx >= TERM_WIDTH) {\n\t\tpp->p_curx = 0;\n\t\tpp->p_cury++;\n\t}\n\t(void) putc(ch, pp->p_output);\n}\n\n/*\n * outstr:\n *\tPut out a string of the given length.\n */\noutstr(pp, str, len)\nregister PLAYER\t*pp;\nregister char\t*str;\nregister int\tlen;\n{\n\tpp->p_curx += len;\n\tpp->p_cury += (pp->p_curx / TERM_WIDTH);\n\tpp->p_curx %= TERM_WIDTH;\n\twhile (len--)\n\t\t(void) putc(*str++, pp->p_output);\n}\n\n/*\n * clrscr:\n *\tClear the screen, and reset the current position on the screen.\n */\nclrscr(pp)\nregister PLAYER\t*pp;\n{\n\tsendcom(pp, CLEAR);\n\tpp->p_cury = 0;\n\tpp->p_curx = 0;\n}\n\n/*\n * ce:\n *\tClear to the end of the line\n */\nce(pp)\nPLAYER\t*pp;\n{\n\tsendcom(pp, CLRTOEOL);\n}\n\n/*\n * ref;\n *\tRefresh the screen\n */\nref(pp)\nregister PLAYER\t*pp;\n{\n\tsendcom(pp, REFRESH);\n}\n\n/*\n * sendcom:\n *\tSend a command to the given user\n */\n/* VARARGS2 */\nsendcom(pp, command, arg1, arg2)\nregister PLAYER\t\t*pp;\nregister int\tcommand;\nint\t\t\targ1, arg2;\n{\n\t(void) putc(command, pp->p_output);\n\tswitch (command & 0377) {\n\t  case MOVE:\n\t\t(void) putc(arg1, pp->p_output);\n\t\t(void) putc(arg2, pp->p_output);\n\t\tbreak;\n\t  case ADDCH:\n\t  case READY:\n\t\t(void) putc(arg1, pp->p_output);\n\t\tbreak;\n\t}\n}\n"
  },
  {
    "path": "games/phantasia/Makefile",
    "content": "#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\nTOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS          += -DPATH=\\\"${DEST}\\\" -DWIZARD=\\\"daemon\\\" -DUID=1 \\\n                   -DRAND=32768.0 -DACCESS=\\\"r+\\\" -DENEMY -DBSD42 -O\n\nOBJS            = main.o func0.o func1.o func2.o fight.o\nLIBS            = -lm -lcurses -ltermcap\nMAN\t\t= phantasia.0\nMANSRC\t\t= phant.nr\n\nall:            phantasia $(MAN)\n\nphantasia:      ${OBJS}\n\t\t${CC} ${CFLAGS} ${LDFLAGS} -o phantasia.elf ${OBJS} ${LIBS}\n\t\t${OBJDUMP} -S phantasia.elf > phantasia.dis\n\t\t${SIZE} phantasia.elf\n\t\t${ELF2AOUT} phantasia.elf $@ && rm phantasia.elf\n\n${MAN}:         ${MANSRC}\n\t\ttbl -TX ${MANSRC} | ${MANROFF} > $@\n\nclean:\n\t\trm -f *.o *.0 *.elf ${MAN} phantasia setfiles phant.help *.elf *.dis tags *~\n\ninstall:        all\n\t\t${INSTALL} phantasia ${DESTDIR}/usr/games/\n\t\tcp ${MAN} ${DESTDIR}/usr/share/man/cat6/\n"
  },
  {
    "path": "games/phantasia/Makefile-linux",
    "content": "# Makefile for Phantasia 3.2 (1.2 2.11BSD - 1997/9/22)\n#\n# MODIFIED TO COMPILE WITHOUT 'XSTR'.\n#\n# To create game:\n#\n# 1)  Set up a directory where the game and its support files will live.\n#        (It is suggested that the source be kept somewhere else.)\n# 2)  Set up the variables in Makefile to reflect your particular situation.\n# 3)  Check out ok_to_play() at the end of main.c if you want to include\n#        code to restrict access at certain times.\n# 4)  'make install' and watch it fly.\n\nLIBS =\t\t-lm -lcurses -ltermcap\n\n# DEST is where the program and its support files reside\n#   If this changes then the symbolic link in the 'install' target must change.\nDEST =\t\t/usr/games/lib/phantasia\n\n# The following are program constants which are implementation dependent.\n#\n# PATH is the same as $DEST.\n# WIZARD is the login of the one who will clean up things.\n# UID is the uid of game wizard.\n# RAND is one more than the largest number generated by rand().\n#\tPossible values for this are:\n#\t\t32768.0\t\t(for 15 bit rand())\n#\t\t65536.0\t\t(for 16 bit rand())\n#\t\t2147483648.0\t(for 31 bit rand())\n# ACCESS is fopen() access to open a file for writing, but no\n#\tclearing the file,  e.g. \"a\", or \"r+\".  (Use \"r+\" if you have it.)\n# define OK_TO_PLAY to restrict playing access.  Also see function ok_to_play()\n#\tin main.c, and tailor to your own needs.\n# define ENEMY to include code for checking of a 'hit list' of resricted\n#\taccounts.  The list of logins goes in the file 'enemy'.\n# define BSD41 for 4.1bsd\n# define BSD42 for 4.2bsd\n# define USG3 for System III, or similar\n# define USG5 for System V\nCFLAGS = \t-DPATH=\\\"${DEST}\\\" \\\n\t\t-DWIZARD=\\\"daemon\\\" \\\n\t\t-DUID=1 \\\n\t\t-DRAND=32768.0 \\\n\t\t-DACCESS=\\\"r+\\\" \\\n\t\t-DENEMY \\\n\t\t-DBSD42 -O\n\nOFILES          = main.o func0.o func1.o func2.o fight.o\n\nall:\t\tphantasia setfiles phant.help phantasia.0\n\nphantasia:\t${OFILES}\n\t\t${CC} ${OFILES} ${LIBS} -o phantasia\n\nsetfiles:\tphant.h setfiles.c\n\t\t${CC} ${CFLAGS} setfiles.c -o setfiles -lm\n\n# the flags below on tbl and nroff are to make a line printable version\nphant.help:\tphant.nr\n\t\ttbl -TX phant.nr | nroff -man -Ttn300 > phant.help\n\n# DO NOT use an absolute pathname in the symbolic link below.  Figure out\n#   what the relative path is.\n\ninstall:\tall phantasia.0\n\trm -f ${DESTDIR}/usr/games/phantasia\n\tln -s lib/phantasia/phantasia ${DESTDIR}/usr/games/phantasia\n\t-mkdir ${DESTDIR}${DEST}\n\tcp phantasia monsters phant.help ${DESTDIR}${DEST}\n\tchmod 755 ${DESTDIR}${DEST}\n\tchmod 4711 ${DESTDIR}${DEST}/phantasia\n\tchmod 644 ${DESTDIR}${DEST}/phant.help\n\t./setfiles\n\tinstall -m 444 -o bin -g bin  phantasia.0 ${DESTDIR}/usr/share/man/cat6\n\nphantasia.0: phant.nr\n\ttbl -TX phant.nr | nroff -man -h -Tascii > phantasia.0\n\nclean:\n\trm -f *.o phantasia phant.help setfiles phantasia.0\n"
  },
  {
    "path": "games/phantasia/fight.c",
    "content": "/*\n * fight.c   Phantasia monster fighting routine\n *\n *\t1.1\t(2.11BSD) 1996/10/26\n */\n\n/*\n * The code exists here for fight to the finish.  Simply add code to\n * set 'fgttofin = TRUE' as an option.\tEverything else is here.\n */\n#include \"phant.h\"\n\nvoid\tfight(stat,particular)\t\t\t/* monster fighting routine */\n        register struct\tstats\t*stat;\n        int\tparticular;\n{\n        bool\tfghttofin = FALSE, luckout = FALSE;\n        char\taline[80];\n        double\tmonhit, mdamage, sdamage, monspd, maxspd, inflict, monstr, temp, shield;\n        int\tch;\n        register int\twhichm, size, hwmany, lines;\n        struct\tmstats\tmonster;\n\n\tfghting = changed = TRUE;\n\tshield = 0.0;\n\tif (setjmp(fightenv) == 2)\n\t\tshield = roll(100 + (stat->mxn + stat->shd)*6.2,3000);\n\thwmany = 0;\n\tsize = (valhala) ? stat->lvl/5 : circ(stat->x,stat->y);\n\tif (particular >= 0)\n\t\twhichm = particular;\n\telse if (marsh)\n\t\twhichm = roll(0,15);\n\telse if (size > 24)\n\t\twhichm = roll(14,86);\n\telse if (size > 15)\n\t\twhichm = roll(0,50) + roll(14,37);\n\telse if (size > 8)\n\t\twhichm = roll(0,50) + roll(14,26);\n\telse if (size > 3)\n\t\twhichm = roll(14,50);\n\telse\n\t\twhichm = roll(14,25);\n\nCALL:\tmove(3,0);\n\tclrtobot();\n\tmove(5,0);\n\tlines = 6;\n\tcallmonster(whichm,size,&monster);\n\tif (stat->blind)\n\t\tstrcpy(monster.name,\"a monster\");\n\t++hwmany;\n\tif (monster.typ == 1)\t/* unicorn */\n\t\tif (stat->vrg)\n\t\t\t{\n\t\t\tprintw(\"You just subdued %s, thanx to the virgin.\",monster.name);\n\t\t\tstat->vrg = FALSE;\n\t\t\tgoto FINISH;\n\t\t\t}\n\t\telse\n\t\t\t{\n\t\t\tprintw(\"You just saw %s running away!\",monster.name);\n\t\t\tgoto LEAVE;\n\t\t\t}\n\tif (monster.typ == 2 && stat->typ > 20)\n\t\t{\n\t\tstrcpy(monster.name,\"Morgoth\");\n\t\tmonster.str = rnd()*(stat->mxn + stat->shd)/1.4 + rnd()*(stat->mxn + stat->shd)/1.5;\n\t\tmonster.brn = stat->brn;\n\t\tmonster.hit = stat->str*30;\n\t\tmonster.typ = 23;\n\t\tmonster.spd = speed*1.1 + speed*(stat->typ == 90);\n\t\tmonster.flk = monster.trs = monster.exp = 0;\n\t\tmvprintw(4,0,\"You've encountered %s, Bane of the Council and Valar.\",monster.name);\n\t\t}\n\tfghttofin = luckout = FALSE;\n\tmonstr = monster.str;\n\tmonhit = monster.hit;\n\tmdamage = sdamage = 0;\n\tmonspd = maxspd = monster.spd;\n\t*monster.name = toupper(*monster.name);\n\nTOP:\tmvprintw(5,0,\"You are being attacked by %s,   EXP: %.0f   (Size: %d)\",monster.name,monster.exp,size);\n\tprintstats(stat);\n\tmvprintw(1,26,\"%20.0f\",stat->nrg + shield);\n\tif (monster.typ == 4 && stat->bls && stat->chm)\n\t\t{\n\t\tmvprintw(6,0,\"You just overpowered %s!\",monster.name);\n\t\tlines = 7;\n\t\tstat->bls = FALSE;\n\t\t--stat->chm;\n\t\tgoto FINISH;\n\t\t}\n\tmonster.spd = min(monster.spd + 1,maxspd);\n\tif (rnd()*monster.spd > rnd()*speed && monster.typ != 4 && monster.typ != 16)\n\t\t{\n\t\tif (monster.typ)\n\t\t\tswitch (monster.typ)\t/* do special things */\n\t\t\t\t{\n\t\t\t\tcase 5: /* Leanan-Sidhe */\n\t\t\t\t\tif (rnd() > 0.25)\n\t\t\t\t\t\tgoto NORMALHIT;\n\t\t\t\t\tinflict = roll(1,(size - 1)/2);\n\t\t\t\t\tinflict = min(stat->str,inflict);\n\t\t\t\t\tmvprintw(lines++,0,\"%s sapped %0.f of your strength!\",monster.name,inflict);\n\t\t\t\t\tstat->str -= inflict;\n\t\t\t\t\tstrength -= inflict;\n\t\t\t\t\tbreak;\n\t\t\t\tcase 6: /* Saruman */\n\t\t\t\t\tif (stat->pal)\n\t\t\t\t\t\t{\n\t\t\t\t\t\tmvprintw(lines++,0,\"Wormtongue stole your palantir!\");\n\t\t\t\t\t\tstat->pal = FALSE;\n\t\t\t\t\t\t}\n\t\t\t\t\telse if (rnd() > 0.2)\n\t\t\t\t\t\tgoto NORMALHIT;\n\t\t\t\t\telse if (rnd() > 0.5)\n\t\t\t\t\t\t{\n\t\t\t\t\t\tmvprintw(lines++,0,\"%s transformed your gems into gold!\",monster.name);\n\t\t\t\t\t\tstat->gld += stat->gem;\n\t\t\t\t\t\tstat->gem = 0.0;\n\t\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\tmvprintw(lines++,0,\"%s scrambled your stats!\",monster.name);\n\t\t\t\t\t\tscramble(stat);\n\t\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t\tcase 7: /* Thaumaturgist */\n\t\t\t\t\tif (rnd() > 0.15)\n\t\t\t\t\t\tgoto NORMALHIT;\n\t\t\t\t\tmvprintw(lines++,0,\"%s transported you!\",monster.name);\n\t\t\t\t\tstat->x += sgn(stat->x)*roll(50*size,250*size);\n\t\t\t\t\tstat->y += sgn(stat->y)*roll(50*size,250*size);\n\t\t\t\t\tgoto LEAVE;\n\t\t\t\tcase 8: /* Balrog */\n\t\t\t\t\tinflict = roll(10,monster.str);\n\t\t\t\t\tinflict = min(stat->exp,inflict);\n\t\t\t\t\tmvprintw(lines++,0,\"%s took away %0.f experience points.\",monster.name,inflict);\n\t\t\t\t\tstat->exp -= inflict;\n\t\t\t\t\tbreak;\n\t\t\t\tcase 9: /* Vortex */\n\t\t\t\t\tif (rnd() > 0.2)\n\t\t\t\t\t\tgoto NORMALHIT;\n\t\t\t\t\tinflict = roll(0,7.5*size);\n\t\t\t\t\tinflict = min(stat->man,floor(inflict));\n\t\t\t\t\tmvprintw(lines++,0,\"%s sucked up %.0f of your manna!\",monster.name,inflict);\n\t\t\t\t\tstat->man -= inflict;\n\t\t\t\t\tbreak;\n\t\t\t\tcase 10:\t/* Nazgul */\n\t\t\t\t\tif (rnd() > 0.3)\n\t\t\t\t\t\tgoto NORMALHIT;\n\t\t\t\t\tif (stat->rng.type && stat->rng.type < 10)\n\t\t\t\t\t\t{\n\t\t\t\t\t\tmvaddstr(lines++,0,\"Will you relinguish your ring ? \");\n\t\t\t\t\t\tch = rgetch();\n\t\t\t\t\t\tif (toupper(ch) == 'Y')\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tstat->rng.type = NONE;\n\t\t\t\t\t\t\tgoto LEAVE;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\tmvprintw(lines++,0,\"%s neutralized 1/5 of your brain!\",monster.name);\n\t\t\t\t\tstat->brn *= 0.8;\n\t\t\t\t\tbreak;\n\t\t\t\tcase 11:\t/* Tiamat */\n\t\t\t\t\tif (rnd() > 0.6)\n\t\t\t\t\t\tgoto NORMALHIT;\n\t\t\t\t\tmvprintw(lines++,0,\"%s took half your gold and gems and flew off.\",monster.name);\n\t\t\t\t\tstat->gld = floor(stat->gld/2);\n\t\t\t\t\tstat->gem = floor(stat->gem/2);\n\t\t\t\t\tgoto LEAVE;\n\t\t\t\tcase 12:\t/* Kobold */\n\t\t\t\t\tif (rnd() >.7)\n\t\t\t\t\t\tgoto NORMALHIT;\n\t\t\t\t\tmvprintw(lines++,0,\"%s stole one gold piece and ran away.\",monster.name);\n\t\t\t\t\tstat->gld = max(0,stat->gld-1);\n\t\t\t\t\tgoto LEAVE;\n\t\t\t\tcase 13:\t/* Shelob */\n\t\t\t\t\tif (rnd() > 0.5)\n\t\t\t\t\t\tgoto NORMALHIT;\n\t\t\t\t\tmvprintw(lines++,0,\"%s has bitten and poisoned you!\",monster.name);\n\t\t\t\t\t++stat->psn;\n\t\t\t\t\tbreak;\n\t\t\t\tcase 14:\t/* Faeries */\n\t\t\t\t\tif (!stat->hw)\n\t\t\t\t\t\tgoto NORMALHIT;\n\t\t\t\t\tmvprintw(lines++,0,\"Your holy water killed it!\");\n\t\t\t\t\t--stat->hw;\n\t\t\t\t\tgoto FINISH;\n\t\t\t\tcase 15:\t/* Lamprey */\n\t\t\t\t\tif (rnd() > 0.7)\n\t\t\t\t\t\tgoto NORMALHIT;\n\t\t\t\t\tmvprintw(lines++,0,\"%s bit and poisoned you!\",monster.name);\n\t\t\t\t\tstat->psn += 0.25;\n\t\t\t\t\tbreak;\n\t\t\t\tcase 17:\t/* Bonnacon */\n\t\t\t\t\tif (rnd() > 0.1)\n\t\t\t\t\t\tgoto NORMALHIT;\n\t\t\t\t\tmvprintw(lines++,0,\"%s farted and scampered off.\",monster.name);\n\t\t\t\t\tstat->nrg /= 2;\n\t\t\t\t\tgoto LEAVE;\n\t\t\t\tcase 18:\t/* Smeagol */\n\t\t\t\t\tif (rnd() > 0.5 || !stat->rng.type)\n\t\t\t\t\t\tgoto NORMALHIT;\n\t\t\t\t\tmvprintw(lines++,0,\"%s tried to steal your ring, \",monster.name);\n\t\t\t\t\tif (rnd() > 0.1)\n\t\t\t\t\t\taddstr(\"but was unsuccessful.\");\n\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\taddstr(\"and ran away with it!\");\n\t\t\t\t\t\tstat->rng.type = NONE;\n\t\t\t\t\t\tgoto LEAVE;\n\t\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t\tcase 19:\t/* Succubus */\n\t\t\t\t\tif (rnd() > 0.3)\n\t\t\t\t\t\tgoto NORMALHIT;\n\t\t\t\t\tinflict = roll(15,size*10);\n\t\t\t\t\tinflict = min(inflict,stat->nrg);\n\t\t\t\t\tmvprintw(lines++,0,\"%s sapped %0.f of your energy.\",monster.name,inflict);\n\t\t\t\t\tstat->nrg -= inflict;\n\t\t\t\t\tbreak;\n\t\t\t\tcase 20:\t/* Cerberus */\n\t\t\t\t\tif (rnd() > 0.25)\n\t\t\t\t\t\tgoto NORMALHIT;\n\t\t\t\t\tmvprintw(lines++,0,\"%s took all your metal treasures!\",monster.name);\n\t\t\t\t\tstat->swd = stat->shd =stat->gld = stat->crn = 0;\n\t\t\t\t\tgoto LEAVE;\n\t\t\t\tcase 21:\t/* Ungoliant */\n\t\t\t\t\tif (rnd() > 0.1)\n\t\t\t\t\t\tgoto NORMALHIT;\n\t\t\t\t\tmvprintw(lines++,0,\"%s poisoned you, and took one quik.\",monster.name);\n\t\t\t\t\tstat->psn += 5;\n\t\t\t\t\t--stat->quk;\n\t\t\t\t\tbreak;\n\t\t\t\tcase 22:\t/* Jabberwock */\n\t\t\t\t\tif (rnd() > 0.1)\n\t\t\t\t\t\tgoto NORMALHIT;\n\t\t\t\t\tmvprintw(lines++,0,\"%s flew away, and left you to contend with one of its friends.\",monster.name);\n\t\t\t\t\twhichm = 55 + 22*(rnd() > 0.5);\n\t\t\t\t\tgoto CALL;\n\t\t\t\tcase 24:\t/* Troll */\n\t\t\t\t\tif (rnd() > 0.5)\n\t\t\t\t\t\tgoto NORMALHIT;\n\t\t\t\t\tmvprintw(lines++,0,\"%s partially regenerated his energy.!\",monster.name);\n\t\t\t\t\tmonster.hit += floor((monhit*size - monster.hit)/2);\n\t\t\t\t\tmonster.str = monstr;\n\t\t\t\t\tmdamage = sdamage = 0;\n\t\t\t\t\tmaxspd = monspd;\n\t\t\t\t\tbreak;\n\t\t\t\tcase 25:\t/* wraith */\n\t\t\t\t\tif (rnd() > 0.3 || stat->blind)\n\t\t\t\t\t\tgoto NORMALHIT;\n\t\t\t\t\tmvprintw(lines++,0,\"%s blindeed you!\",monster.name);\n\t\t\t\t\tstat->blind = TRUE;\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tgoto NORMALHIT;\n\t\t\t\t}\n\t\telse\nNORMALHIT:\t\t{\n\t\t\tinflict = rnd()*monster.str + 0.5;\n\t\t\tmvprintw(lines++,0,\"%s hit you %.0f times!\",monster.name,inflict);\nSPECIALHIT:\t\tif ((shield -= inflict) < 0)\n\t\t\t\t{\n\t\t\t\tstat->nrg += shield;\n\t\t\t\tshield = 0;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\telse\n\t\t{\n\t\tif (fghttofin)\n\t\t\tgoto MELEE;\n\t\tmvaddstr(3,0,\"1:Melee  2:Skirmish  3:Evade  4:Spell  5:Nick  \");\n\t\tif (!luckout)\n\t\t\tif (monster.typ == 23)\n\t\t\t\taddstr(\"6:Ally  \");\n\t\t\telse\n\t\t\t\taddstr(\"6:Luckout  \");\n\t\tif (stat->rng.type > 0)\n\t\t\taddstr(\"7:Use Ring  \");\n\t\telse\n\t\t\tclrtoeol();\n\t\tch = gch(stat->rng.type);\n\t\tmove(lines = 6,0);\n\t\tclrtobot();\n\t\tswitch (ch)\n\t\t\t{\n\t\t\tdefault:\n\t\t\tcase '1':\t/* melee */\nMELEE:\t\t\t\tinflict = roll(strength/2 + 5,1.3*strength) + (stat->rng.type < 0 ? strength : 0);\n\t\t\t\tmdamage += inflict;\n\t\t\t\tmonster.str = monstr - mdamage/monhit*monstr/4;\n\t\t\t\tgoto HITMONSTER;\n\t\t\tcase '2':\t/* skirmish */\n\t\t\t\tinflict = roll(strength/3 + 3,1.1*strength) + (stat->rng.type < 0 ? strength : 0);\n\t\t\t\tsdamage += inflict;\n\t\t\t\tmaxspd = monspd - sdamage/monhit*monspd/4;\n\t\t\t\tgoto HITMONSTER;\n\t\t\tcase '3':\t/* evade */\n\t\t\t\tif ((monster.typ == 4 || monster.typ == 16\n\t\t\t\t|| rnd()*speed*stat->brn > rnd()*monster.spd*monster.brn)\n\t\t\t\t&& (monster.typ != 23))\n\t\t\t\t\t{\n\t\t\t\t\tmvaddstr(lines++,0,\"You got away!\");\n\t\t\t\t\tstat->x += roll(-2,5);\n\t\t\t\t\tstat->y += roll(-2,5);\n\t\t\t\t\tgoto LEAVE;\n\t\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t\tmvprintw(lines++,0,\"%s is still after you!\",monster.name);\n\t\t\t\tbreak;\n\t\t\tcase '4':\t/* spell */\n\t\t\t\tlines = 7;\n\t\t\t\tmvaddstr(3,0,\"\\n\\n\");\n\t\t\t\tmvaddstr(3,0,\"1:All or Nothing\");\n\t\t\t\tif (stat->mag >= 3)\n\t\t\t\t\tmvaddstr(3,18,\"2:Magic Bolt\");\n\t\t\t\tif (stat->mag >= 7)\n\t\t\t\t\tmvaddstr(3,32,\"3:Force Field\");\n\t\t\t\tif (stat->mag >= 10)\n\t\t\t\t\tmvaddstr(3,47,\"4:Transform\");\n\t\t\t\tif(stat->mag >= 15)\n\t\t\t\t\tmvaddstr(3,60,\"5:Increase Might\\n\");\n\t\t\t\tif (stat->mag >= 20)\n\t\t\t\t\tmvaddstr(4,0,\"6:Invisibility\");\n\t\t\t\tif (stat->mag >= 25)\n\t\t\t\t\tmvaddstr(4,18,\"7:Transport\");\n\t\t\t\tif (stat->mag >= 30)\n\t\t\t\t\tmvaddstr(4,32,\"8:Paralyze\");\n\t\t\t\tif (stat->typ > 20)\n\t\t\t\t\tmvaddstr(4,52,\"9:Specify\");\n\t\t\t\tmvaddstr(6,0,\"Spell ? \");\n\t\t\t\tch = rgetch();\n\t\t\t\tmvaddstr(3,0,\"\\n\\n\");\n\t\t\t\tif (monster.typ == 23 && ch != '4')\n\t\t\t\t\tillspell();\n\t\t\t\telse\n\t\t\t\t\tswitch (ch)\n\t\t\t\t\t\t{\n\t\t\t\t\t\tcase '1':\t/* all or nothing */\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tinflict = (rnd() < 0.25) ? (monster.hit*1.0001 + 1) : 0;\n\t\t\t\t\t\t\tif (monster.typ == 4)\n\t\t\t\t\t\t\t\tinflict *= .9;\n\t\t\t\t\t\t\tif (stat->man)\n\t\t\t\t\t\t\t\t--stat->man;\n\t\t\t\t\t\t\tmaxspd *= 2;\n\t\t\t\t\t\t\tmonspd *= 2;\n\t\t\t\t\t\t\tmonster.spd = max(1,monster.spd * 2);\n\t\t\t\t\t\t\tmonstr = monster.str *= 2;\n\t\t\t\t\t\t\tgoto HITMONSTER;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tcase '2':\t/* magic bolt */\n\t\t\t\t\t\t\tif (stat->mag < 3)\n\t\t\t\t\t\t\t\tillspell();\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tdo\n\t\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\tmvaddstr(6,0,\"How much manna for bolt? \");\n\t\t\t\t\t\t\t\t\tgetstring(aline,80);\n\t\t\t\t\t\t\t\t\tsscanf(aline,\"%lf\",&temp);\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\twhile (temp < 0 || temp > stat->man);\n\t\t\t\t\t\t\t\tstat->man -= floor(temp);\n\t\t\t\t\t\t\t\tinflict = temp*roll(10,sqrt(stat->mag/3.0 + 1.0));\n\t\t\t\t\t\t\t\tmvaddstr(6,0,\"Magic Bolt fired!\\n\");\n\t\t\t\t\t\t\t\tif (monster.typ == 4)\n\t\t\t\t\t\t\t\t\tinflict = 0.0;\n\t\t\t\t\t\t\t\tgoto HITMONSTER;\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\tcase '5':\t/* increase might */\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tif (stat->mag < 15)\n\t\t\t\t\t\t\t\tillspell();\n\t\t\t\t\t\t\telse if (stat->man < 55)\n\t\t\t\t\t\t\t\tnomanna();\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tstat->man -= 55;\n\t\t\t\t\t\t\t\tstrength += (1.2*(stat->str+stat->swd)+5-strength)/2;\n\t\t\t\t\t\t\t\tmvprintw(6,0,\"New strength:  %.0f\\n\",strength);\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tcase '3':\t/* force field */\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tif (stat->mag < 7)\n\t\t\t\t\t\t\t\tillspell();\n\t\t\t\t\t\t\telse if (stat->man < 20)\n\t\t\t\t\t\t\t\tnomanna();\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tshield = (stat->mxn + stat->shd)*4.2 + 45;\n\t\t\t\t\t\t\t\tstat->man -= 20;\n\t\t\t\t\t\t\t\tmvaddstr(6,0,\"Force Field up.\\n\");\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tcase '4':\t/* transform */\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tif (stat->mag < 10)\n\t\t\t\t\t\t\t\tillspell();\n\t\t\t\t\t\t\telse if (stat->man < 35)\n\t\t\t\t\t\t\t\tnomanna();\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tstat->man -= 35;\n\t\t\t\t\t\t\t\twhichm = roll(0,100);\n\t\t\t\t\t\t\t\tgoto CALL;\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tcase '6':\t/* invisible */\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tif (stat->mag < 20)\n\t\t\t\t\t\t\t\tillspell();\n\t\t\t\t\t\t\telse if (stat->man < 45)\n\t\t\t\t\t\t\t\tnomanna();\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tstat->man -= 45;\n\t\t\t\t\t\t\t\tspeed += (1.2*(stat->quk+stat->quks)+5-speed)/2;\n\t\t\t\t\t\t\t\tmvprintw(6,0,\"New quik :  %.0f\\n\",speed);\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tcase '7':\t/* transport */\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tif (stat->mag < 25)\n\t\t\t\t\t\t\t\tillspell();\n\t\t\t\t\t\t\telse if (stat->man < 50)\n\t\t\t\t\t\t\t\tnomanna();\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tstat->man -= 50;\n\t\t\t\t\t\t\t\tif (stat->brn + stat->mag < monster.exp/300*rnd())\n\t\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\tmvaddstr(6,0,\"Transport backfired!\\n\");\n\t\t\t\t\t\t\t\t\tstat->x += (250*size*rnd() + 50*size)*sgn(stat->x);\n\t\t\t\t\t\t\t\t\tstat->y += (250*size*rnd() + 50*size)*sgn(stat->y);\n\t\t\t\t\t\t\t\t\tgoto LEAVE;\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\tmvprintw(6,0,\"%s is transported.\\n\",monster.name);\n\t\t\t\t\t\t\t\t\tmonster.trs *= (rnd() > 0.3);\n\t\t\t\t\t\t\t\t\tgoto FINISH;\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tcase '8':\t/* paralyze */\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tif (stat->mag < 30)\n\t\t\t\t\t\t\t\t\tillspell();\n\t\t\t\t\t\t\telse if (stat->man < 60)\n\t\t\t\t\t\t\t\tnomanna();\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tstat->man -= 60;\n\t\t\t\t\t\t\t\tif (stat->mag > monster.exp/1000*rnd())\n\t\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\tmvprintw(6,0,\"%s is held.\\n\",monster.name);\n\t\t\t\t\t\t\t\t\tmonster.spd = -2;\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\tmvaddstr(6,0,\"Monster unaffected.\\n\");\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tcase '9':\t/* specify */\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tif (stat->typ < 20)\n\t\t\t\t\t\t\t\tillspell();\n\t\t\t\t\t\t\telse if (stat->man < 1000)\n\t\t\t\t\t\t\t\tnomanna();\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tmvaddstr(6,0,\"Which monster do you want [0-99] ? \");\n\t\t\t\t\t\t\t\twhichm = inflt();\n\t\t\t\t\t\t\t\twhichm = max(0,min(99,whichm));\n\t\t\t\t\t\t\t\tstat->man -= 1000;\n\t\t\t\t\t\t\t\tgoto CALL;\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase '5':\n\t\t\t\tinflict = 1 + stat->swd;\n\t\t\t\tstat->exp += floor(monster.exp/10);\n\t\t\t\tmonster.exp *= 0.92;\n\t\t\t\tmaxspd += 2;\n\t\t\t\tmonster.spd = (monster.spd < 0) ? 0 : monster.spd + 2;\n\t\t\t\tif (monster.typ == 4)\n\t\t\t\t\t{\n\t\t\t\t\tmvprintw(lines++,0,\"You hit %s %.0f times, and made him mad!\",monster.name,inflict);\n\t\t\t\t\tstat->quk /= 2;\n\t\t\t\t\tstat->x += sgn(stat->x)*roll(50*size,250*size);\n\t\t\t\t\tstat->y += sgn(stat->y)*roll(50*size,250*size);\n\t\t\t\t\tstat->y += (250*size*rnd() + 50*size)*sgn(stat->y);\n\t\t\t\t\tgoto LEAVE;\n\t\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t\tgoto HITMONSTER;\n\t\t\tcase '6':\t/* luckout */\n\t\t\t\tif (luckout)\n\t\t\t\t\tmvaddstr(lines++,0,\"You already tried that.\");\n\t\t\t\telse\n\t\t\t\t\tif (monster.typ == 23)\n\t\t\t\t\t\tif (rnd() < stat->sin/100)\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmvprintw(lines++,0,\"%s accepted!\",monster.name);\n\t\t\t\t\t\t\tgoto LEAVE;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tluckout = TRUE;\n\t\t\t\t\t\t\tmvaddstr(lines++,0,\"Nope, he's not interested.\");\n\t\t\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t\tif ((rnd() + .333)*stat->brn < (rnd() + .333)*monster.brn)\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tluckout = TRUE;\n\t\t\t\t\t\t\tmvprintw(lines++,0,\"You blew it, %s.\",stat->name);\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmvaddstr(lines++,0,\"You made it!\");\n\t\t\t\t\t\t\tgoto FINISH;\n\t\t\t\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase '\\014':\t/* clear screen */\n\t\t\t\tclear();\n\t\t\t\tbreak;\n\t\t\tcase '7':\t/* use ring */\n\t\t\t\tif (stat->rng.type > 0)\n\t\t\t\t\t{\n\t\t\t\t\tmvaddstr(lines++,0,\"Now using ring.\");\n\t\t\t\t\t\tstat->rng.type = -stat->rng.type;\n\t\t\t\t\t\tif (abs(stat->rng.type) != DLREG)\n\t\t\t\t\t\t\t--stat->rng.duration;\n\t\t\t\t\t\tgoto NORMALHIT;\n\t\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\tgoto BOT;\nHITMONSTER:\t\t{\n\t\t\tinflict = floor(inflict);\n\t\t\tmvprintw(lines++,0,\"You hit %s %.0f times!\",monster.name,inflict);\n\t\t\tif ((monster.hit -= inflict) >0)\n\t\t\t\tswitch (monster.typ)\n\t\t\t\t\t{\n\t\t\t\t\tcase 4: /* dark lord */\n\t\t\t\t\t\tinflict = stat->nrg + shield +1;\n\t\t\t\t\t\tgoto SPECIALHIT;\n\t\t\t\t\tcase 16:\t/* shrieker */\n\t\t\t\t\t\tmvaddstr(lines++,0,\"Shreeeek!!  You scared it, and it called one of its friends.\");\n\t\t\t\t\t\tpaws(lines);\n\t\t\t\t\t\twhichm = roll(70,30);\n\t\t\t\t\t\tgoto CALL;\n\t\t\t\t\t}\n\t\t\telse\n\t\t\t\t{\n\t\t\t\tif (monster.typ == 23)\t/* morgoth */\n\t\t\t\t\tmvaddstr(lines++,0,\"You have defeated Morgoth, but he may return. . .\");\n\t\t\t\telse\n\t\t\t\t\tmvprintw(lines++,0,\"You killed it.  Good work, %s.\",stat->name);\n\t\t\t\tgoto FINISH;\n\t\t\t\t}\n\t\t\t}\n\t\t}\nBOT:\trefresh();\n\tif (lines == 23)\n\t\t{\n\t\tpaws(23);\n\t\tmove(lines = 6,0);\n\t\tclrtobot();\n\t\t}\n\tif (stat->nrg <= 0)\n\t\t{\n\t\tpaws(lines);\n\t\tdeath(stat);\n\t\tgoto LEAVE;\n\t\t}\n\tgoto TOP;\nFINISH:\tstat->exp += monster.exp;\n\tif (rnd() < monster.flk/100.0)\t/* flock monster */\n\t\t{\n\t\tpaws(lines);\n\t\tfghttofin = FALSE;\n\t\tgoto CALL;\n\t\t}\n\telse if (size > 1 && monster.trs && rnd() > pow(0.6,(double) (hwmany/3 + size/3)))\t/* this takes # of flocks and size into account */\n\t\t{\n\t\tpaws(lines);\n\t\ttreasure(stat,monster.trs,size);\n\t\t}\nLEAVE:\tstat->rng.type = abs(stat->rng.type);\n\tpaws(lines+3);\n\tmove(4,0);\n\tclrtobot();\n\tfghting = FALSE;\n}\n"
  },
  {
    "path": "games/phantasia/func0.c",
    "content": "/*\n * func0.c\tPhantasia support routines\n */\n\n#include \"phant.h\"\n\nvoid\ttreasure(stat,treastyp,size)\t\t/* select a treasure */\nregister struct\tstats\t*stat;\nshort\ttreastyp;\nregister int\tsize;\n{\nregister int\twhich;\nint\tch;\ndouble\ttemp, temp2;\nchar\taline[35];\nFILE\t*fp;\n\n\twhich = roll(1,3);\n\tmove(3,0);\n\tclrtobot();\n\tmove(5,0);\n\tif (rnd() > 0.65)\t/* gold and gems */\n\t\tif (treastyp > 7)\t/* gems */\n\t\t\t{\n\t\t\ttemp = roll(1,(treastyp - 7)*(treastyp - 7)*(size - 1)/4);\n\t\t\tprintw(\"You have discovered %.0f gems!  Will you pick them up ? \",temp);\n\t\t\tch = rgetch();\n\t\t\taddch('\\n');\n\t\t\tif (toupper(ch) == 'Y')\n\t\t\t\tif (rnd() < treastyp/40 + 0.05)\t/* cursed */\n\t\t\t\t\t{\n\t\t\t\t\taddstr(\"They were cursed!\\n\");\n\t\t\t\t\tgoto CURSE;\n\t\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t\tstat->gem += temp;\n\t\t\treturn;\n\t\t\t}\n\t\telse\t/* gold */\n\t\t\t{\n\t\t\ttemp = roll(treastyp*10,treastyp*treastyp*10*(size - 1));\n\t\t\tprintw(\"You have found %.0f gold pieces.  Do you want to pick them up ? \",temp);\n\t\t\tch = rgetch();\n\t\t\taddch('\\n');\n\t\t\tif (toupper(ch) == 'Y')\n\t\t\t\tif (rnd() < treastyp/35 + 0.04)\t/* cursed */\n\t\t\t\t\t{\n\t\t\t\t\taddstr(\"They were cursed!\\n\");\n\t\t\t\t\tgoto CURSE;\n\t\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\tstat->gld += floor(0.9 * temp);\n\t\t\t\t\tfp = fopen(goldfile,\"r\");\n\t\t\t\t\tif (fread((char *) &temp2,sizeof(double),1,fp) != 1)\n\t\t\t\t\t        /*ignore*/;\n\t\t\t\t\tfclose(fp);\n\t\t\t\t\tfp = fopen(goldfile,\"w\");\n\t\t\t\t\ttemp2 += floor(temp/10);\n\t\t\t\t\tfwrite((char *) &temp2,sizeof(double),1,fp);\n\t\t\t\t\tfclose(fp);\n\t\t\t\t\t}\n\t\t\treturn;\n\t\t\t}\n\telse\t/* other treasures */\n\t\t{\n\t\taddstr(\"You have found some treasure.  Do you want to inspect it ? \");\n\t\tch = rgetch();\n\t\taddch('\\n');\n\t\tif (toupper(ch) != 'Y')\n\t\t\treturn;\n\t\telse\n\t\t\tif (rnd() < 0.08 && treastyp != 4)\n\t\t\t\t{\n\t\t\t\taddstr(\"It was cursed!\\n\");\n\t\t\t\tgoto CURSE;\n\t\t\t\t}\n\t\t\telse\n\t\t\t\tswitch(treastyp)\n\t\t\t\t\t{\n\t\t\t\t\tcase 1:\n\t\t\t\t\t\tswitch(which)\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tcase 1:\n\t\t\t\t\t\t\t\taddstr(\"You've discovered a power booster!\\n\");\n\t\t\t\t\t\t\t\tstat->man += roll(size*4,size*30);\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\tcase 2:\n\t\t\t\t\t\t\t\taddstr(\"You have encountered a druid.\\n\");\n\t\t\t\t\t\t\t\tstat->exp += roll(0,2000 + size*400);\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\tcase 3:\n\t\t\t\t\t\t\t\taddstr(\"You have found a holy orb.\\n\");\n\t\t\t\t\t\t\t\tstat->sin = max(0,stat->sin - 0.25);\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 2:\n\t\t\t\t\t\tswitch (which)\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tcase 1:\n\t\t\t\t\t\t\t\taddstr(\"You have found an amulet.\\n\");\n\t\t\t\t\t\t\t\t++stat->amu;\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\tcase 2:\n\t\t\t\t\t\t\t\taddstr(\"You've found some holy water!\\n\");\n\t\t\t\t\t\t\t\t++stat->hw;\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\tcase 3:\n\t\t\t\t\t\t\t\taddstr(\"You've met a hermit!\\n\");\n\t\t\t\t\t\t\t\tstat->sin *= 0.75;\n\t\t\t\t\t\t\t\tstat->man += 12*size;\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 3:\n\t\t\t\t\t\tswitch (which)\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tcase 1:\n\t\t\t\t\t\t\t\ttemp = roll(7,30 + size/10);\n\t\t\t\t\t\t\t\tprintw(\"You've found a +%.0f shield!\\n\",temp);\n\t\t\t\t\t\t\t\tif (temp >= stat->shd)\n\t\t\t\t\t\t\t\t\tstat->shd = temp;\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\tsomebetter();\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\tcase 2:\n\t\t\t\t\t\t\t\taddstr(\"You have rescued a virgin.  Will you be honorable ? \");\n\t\t\t\t\t\t\t\tch = rgetch();\n\t\t\t\t\t\t\t\tif (toupper(ch) == 'Y')\n\t\t\t\t\t\t\t\t\tstat->vrg = TRUE;\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\tstat->exp += 2000*size;\n\t\t\t\t\t\t\t\t\t++stat->sin;\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\tcase 3:\n\t\t\t\t\t\t\t\taddstr(\"You've discovered some athelas!\\n\");\n\t\t\t\t\t\t\t\t--stat->psn;\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 4:\n\t\t\t\t\t\taddstr(\"You've found a scroll.  Will you read it ? \");\n\t\t\t\t\t\tch = rgetch();\n\t\t\t\t\t\taddch('\\n');\n\t\t\t\t\t\tif (toupper(ch) == 'Y')\n\t\t\t\t\t\t\tswitch ((int) roll(1,6))\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tcase 1:\n\t\t\t\t\t\t\t\t\taddstr(\"It throws up a shield for you next monster.\\n\");\n\t\t\t\t\t\t\t\t\tpaws(8);\n\t\t\t\t\t\t\t\t\tlongjmp(fightenv,2);\n\t\t\t\t\t\t\t\t\t/*NOTREACHED*/\n\t\t\t\t\t\t\t\tcase 2:\n\t\t\t\t\t\t\t\t\taddstr(\"It makes you invisible for you next monster.\\n\");\n\t\t\t\t\t\t\t\t\tpaws(8);\n\t\t\t\t\t\t\t\t\tspeed = 1e6;\n\t\t\t\t\t\t\t\t\tlongjmp(fightenv,0);\n\t\t\t\t\t\t\t\t\t/*NOTREACHED*/\n\t\t\t\t\t\t\t\tcase 3:\n\t\t\t\t\t\t\t\t\taddstr(\"It increases your strength ten fold to fight your next monster.\\n\");\n\t\t\t\t\t\t\t\t\tpaws(8);\n\t\t\t\t\t\t\t\t\tstrength *= 10;\n\t\t\t\t\t\t\t\t\tlongjmp(fightenv,0);\n\t\t\t\t\t\t\t\t\t/*NOTREACHED*/\n\t\t\t\t\t\t\t\tcase 4:\n\t\t\t\t\t\t\t\t\taddstr(\"It is a general knowledge scroll.\\n\");\n\t\t\t\t\t\t\t\t\tstat->brn += roll(2,size);\n\t\t\t\t\t\t\t\t\tstat->mag += roll(1,size/2);\n\t\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\tcase 5:\n\t\t\t\t\t\t\t\taddstr(\"It tells you how to pick your next monster.\\n\");\n\t\t\t\t\t\t\t\taddstr(\"Which monster do you want [0-99] ? \");\n\t\t\t\t\t\t\t\twhich = inflt();\n\t\t\t\t\t\t\t\twhich = min(99,max(0,which));\n\t\t\t\t\t\t\t\tfight(stat,which);\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\tcase 6:\n\t\t\t\t\t\t\t\taddstr(\"It was cursed!\\n\");\n\t\t\t\t\t\t\t\tgoto CURSE;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 5:\n\t\t\t\t\t\tswitch (which)\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tcase 1:\n\t\t\t\t\t\t\t\ttemp = roll(size/4+5,size/2 + 9);\n\t\t\t\t\t\t\t\tprintw(\"You've discovered a +%.0f dagger.\\n\",temp);\n\t\t\t\t\t\t\t\tif (temp >= stat->swd)\n\t\t\t\t\t\t\t\t\tstat->swd = temp;\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\tsomebetter();\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\tcase 2:\n\t\t\t\t\t\t\t\ttemp = roll(7.5 + size*3,size * 2 + 160);\n\t\t\t\t\t\t\t\tprintw(\"You have found some +%.0f armour!\\n\",temp);\n\t\t\t\t\t\t\t\tif (temp >= stat->shd)\n\t\t\t\t\t\t\t\t\tstat->shd = temp;\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\tsomebetter();\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\tcase 3:\n\t\t\t\t\t\t\t\taddstr(\"You've found a tablet.\\n\");\n\t\t\t\t\t\t\t\tstat->brn += 4.5*size;\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 6:\n\t\t\t\t\t\tswitch (which)\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tcase 1:\n\t\t\t\t\t\t\t\taddstr(\"You've found a priest.\\n\");\n\t\t\t\t\t\t\t\tstat->nrg = stat->mxn + stat->shd;\n\t\t\t\t\t\t\t\tstat->sin /= 2;\n\t\t\t\t\t\t\t\tstat->man += 24*size;\n\t\t\t\t\t\t\t\tstat->brn += size;\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\tcase 2:\n\t\t\t\t\t\t\t\taddstr(\"You have come upon Robin Hood!\\n\");\n\t\t\t\t\t\t\t\tstat->shd += size*2;\n\t\t\t\t\t\t\t\tstat->str += size/2.5 + 1;\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\tcase 3:\n\t\t\t\t\t\t\t\t\ttemp = roll(2 + size/4,size/1.2 + 10);\n\t\t\t\t\t\t\t\tprintw(\"You have found a +%.0f axe!\\n\",temp);\n\t\t\t\t\t\t\t\tif (temp >= stat->swd)\n\t\t\t\t\t\t\t\t\tstat->swd = temp;\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\tsomebetter();\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 7:\n\t\t\t\t\t\tswitch (which)\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tcase 1:\n\t\t\t\t\t\t\t\taddstr(\"You've discovered a charm!\\n\");\n\t\t\t\t\t\t\t\t++stat->chm;\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\tcase 2:\n\t\t\t\t\t\t\t\taddstr(\"You have encountered Merlyn!\\n\");\n\t\t\t\t\t\t\t\tstat->brn += size + 5;\n\t\t\t\t\t\t\t\tstat->mag += size/3 + 5;\n\t\t\t\t\t\t\t\tstat->man += size*10;\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\tcase 3:\n\t\t\t\t\t\t\t\ttemp = roll(5+size/3,size/1.5 + 20);\n\t\t\t\t\t\t\t\tprintw(\"You have found a +%.0f war hammer!\\n\",temp);\n\t\t\t\t\t\t\t\tif (temp >= stat->swd)\n\t\t\t\t\t\t\t\t\tstat->swd = temp;\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\tsomebetter();\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 8:\n\t\t\t\t\t\tswitch (which)\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tcase 1:\n\t\t\t\t\t\t\t\taddstr(\"You have found a healing potion.\\n\");\n\t\t\t\t\t\t\t\tstat->psn = min(-2,stat->psn-2);\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\tcase 2:\n\t\t\t\t\t\t\t\taddstr(\"You have discovered a transporter.  Do you wish to go anywhere ? \");\n\t\t\t\t\t\t\t\tch = rgetch();\n\t\t\t\t\t\t\t\taddch('\\n');\n\t\t\t\t\t\t\t\tif (toupper(ch) == 'Y')\n\t\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\taddstr(\"X Y Coordinates ? \");\n\t\t\t\t\t\t\t\t\tgetstring(aline,80);\n\t\t\t\t\t\t\t\t\tsscanf(aline,\"%lf %lf\",&stat->x,&stat->y);\n\t\t\t\t\t\t\t\t\tstat->x = floor(stat->x);\n\t\t\t\t\t\t\t\t\tstat->y = floor(stat->y);\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\tcase 3:\n\t\t\t\t\t\t\t\ttemp = roll(10 + size/1.2,size*3 + 30);\n\t\t\t\t\t\t\t\tprintw(\"You've found a +%.0f sword!\\n\",temp);\n\t\t\t\t\t\t\t\tif (temp >= stat->swd)\n\t\t\t\t\t\t\t\t\tstat->swd = temp;\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\tsomebetter();\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase 10:\n\t\t\t\t\tcase 11:\n\t\t\t\t\tcase 12:\n\t\t\t\t\tcase 13:\n\t\t\t\t\t\tif (rnd() < 0.33)\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tif (treastyp == 10)\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\taddstr(\"You've found a pair of elven boots!\\n\");\n\t\t\t\t\t\t\t\tstat->quk += 2;\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\telse if (treastyp == 11 && !stat->pal)\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\taddstr(\"You've acquired Saruman's palantir.\\n\");\n\t\t\t\t\t\t\t\tstat->pal = TRUE;\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\telse if (!stat->rng.type && stat->typ < 20 && (treastyp == 12 || treastyp == 13))\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tif (treastyp == 12)\n\t\t\t\t\t\t\t\t\tif (rnd() < 0.8)\n\t\t\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\t\twhich = NAZREG;\n\t\t\t\t\t\t\t\t\t\ttemp = 15;\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\t\twhich = NAZBAD;\n\t\t\t\t\t\t\t\t\t\ttemp = 10 + rngcalc(stat->typ) + roll(0,5);\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\tif (rnd() > 0.9)\n\t\t\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\t\twhich = DLREG;\n\t\t\t\t\t\t\t\t\t\ttemp = 0;\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\t\twhich = DLBAD;\n\t\t\t\t\t\t\t\t\t\ttemp = 15 + rngcalc(stat->typ) + roll(0,5);\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t\taddstr(\"You've discovered a ring.  Will you pick it up ? \");\n\t\t\t\t\t\t\t\t\tch = rgetch();\n\t\t\t\t\t\t\t\t\taddch('\\n');\n\t\t\t\t\t\t\t\t\tif (toupper(ch) == 'Y')\n\t\t\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\t\tstat->rng.type = which;\n\t\t\t\t\t\t\t\t\t\tstat->rng.duration = temp;\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tcase 9:\n\t\t\t\t\t\t\tswitch (which)\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tcase 1:\n\t\t\t\t\t\t\t\t\tif (!(stat->lvl > 1000 || stat->crn > floor((double) stat->lvl/100)\n\t\t\t\t\t\t\t\t\t\t\t|| stat->lvl < 10))\n\t\t\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\t\taddstr(\"You have found a golden crown!\\n\");\n\t\t\t\t\t\t\t\t\t\t++stat->crn;\n\t\t\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\tcase 2:\n\t\t\t\t\t\t\t\t\taddstr(\"You've been blessed!\\n\");\n\t\t\t\t\t\t\t\t\tstat->bls = TRUE;\n\t\t\t\t\t\t\t\t\tstat->sin /=3;\n\t\t\t\t\t\t\t\t\tstat->nrg = stat->mxn + stat->shd;\n\t\t\t\t\t\t\t\t\tstat->man += 100*size;\n\t\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t\tcase 3:\n\t\t\t\t\t\t\t\t\ttemp = roll(1,size/5+5);\n\t\t\t\t\t\t\t\t\ttemp = min(temp,99);\n\t\t\t\t\t\t\t\t\tprintw(\"You have discovered some +%.0f quicksilver!\\n\",temp);\n\t\t\t\t\t\t\t\t\tif (temp >= stat->quks)\n\t\t\t\t\t\t\t\t\t\tstat->quks = temp;\n\t\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\t\tsomebetter();\n\t\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t}\n\t\trefresh();\n\t\treturn;\n\t\t}\nCURSE:\tif (stat->chm)\n\t\t{\n\t\taddstr(\"But your charm saved you!\\n\");\n\t\t--stat->chm;\n\t\t}\n\telse if (stat->amu)\n\t\t{\n\t\taddstr(\"But your amulet saved you!\\n\");\n\t\t--stat->amu;\n\t\t}\n\telse\n\t\t{\n\t\tstat->nrg = (stat->mxn + stat->shd)/10;\n\t\tstat->psn += 0.25;\n\t\t}\n}\n\nvoid\tcallmonster(which,size,mons)\t\t/* fill a structure with monster 'which' of size 'size' */\nregister int\twhich, size;\nregister struct\tmstats\t*mons;\n{\nFILE\t*fp;\nchar\tinstr[100];\n\n\twhich = min(which,99);\n\tfp = fopen(monsterfile,\"r\");\n\tfor (++which; which; --which) {\n\t\tif (fgets(instr,100,fp) == 0)\n\t\t        /*ignore*/;\n        }\n\tstrncpy(mons->name,instr,24);\n\tmons->name[24] = '\\0';\n\tsscanf(instr + 24,\"%lf%lf%lf%lf%lf%d%d%d\",&mons->str,&mons->brn,&mons->spd,&mons->hit,\n\t\t&mons->exp,&mons->trs,&mons->typ,&mons->flk);\n\tif (mons->typ == 2)\t/* Modnar */\n\t\t{\n\t\tmons->str *= rnd() + 0.5;\n\t\tmons->brn *= rnd() + 0.5;\n\t\tmons->spd *= rnd() + 0.5;\n\t\tmons->hit *= rnd() + 0.5;\n\t\tmons->exp *= rnd() + 0.5;\n\t\tmons->trs *= rnd();\n\t\t}\n\telse if (mons->typ == 3)\t/* mimic */\n\t\t{\n\t\tfseek(fp,0L,0);\n\t\tfor (which = roll(0,100); which; --which) {\n\t\t\tif (fgets(instr,100,fp) == 0)\n\t\t\t        /*ignore*/;\n                }\n\t\tstrncpy(mons->name,instr,24);\n\t\t}\n\tstrunc(mons->name);\n\tmons->str += (size-1)*mons->str/2;\n\tmons->brn *= size;\n\tmons->spd += size * 1.e-9;\n\tmons->hit *= size;\n\tmons->exp *= size;\n\tfclose(fp);\n}\n\nstruct\t/* lookup table for rolling stats and making increases upon gaining levels */\n\t{\n\tstruct\n\t\t{\n\t\tint\tbase;\n\t\tint\tinterval;\n\t\tfloat\tincrease;\n\t\t} quick,      strength,      manna,\t    energy,\t   brains,\t  magic;\n\t} table[7] =\n\t\t{\n/* mag. usr: */ 30, 6, 0.0,   20, 6, 2.0,    50,51,75.0,    30,16,20.0,    60,26, 6.0,\t  5, 5,2.75,\n/* fighter:  */ 30, 6, 0.0,   40,16, 3.0,    30,21,40.0,    45,26,30.0,    25,21, 3.0,\t  3, 4, 1.5,\n/* elf:      */ 32, 7, 0.0,   35,11, 2.5,    45,46,65.0,    30,21,25.0,    40,26, 4.0,\t  4, 4, 2.0,\n/* dwarf:    */ 25, 6, 0.0,   45,21, 5.0,    25,21,30.0,    60,41,35.0,    20,21, 2.5,\t  2, 4, 1.0,\n/* halfling: */ 34, 0, 0.0,   20, 6, 2.0,    25,21,30.0,    55,36,30.0,    40,36, 4.5,\t  1, 4, 1.0,\n/* exprmnto: */ 27, 0, 0.0,   25, 0, 0.0,    100,0, 0.0,    35, 0, 0.0,    25, 0, 0.0,\t  2, 0, 0.0,\n/* super:    */ 38, 0, 0.0,   65, 0, 0.0,    100,0, 0.0,    80, 0, 0.0,    85, 0, 0.0,\t  9, 0, 0.0\n\t\t};\n\nvoid\tgenchar(res,type)\t\t\t\t/* init a charac struct */\nint\ttype;\nregister struct\tstats\t*res;\n{\nregister int\tsubscript;\n\n\tif (type < '1' || type > '6')\n\t\tif (type != '7' || !su)\n\t\t\ttype = '2';\t/* fighter is default */\n\tsubscript = type - '1';\n\tres->quk = roll(table[subscript].quick.base,table[subscript].quick.interval);\n\tres->str = roll(table[subscript].strength.base,table[subscript].strength.interval);\n\tres->man = roll(table[subscript].manna.base,table[subscript].manna.interval);\n\tres->mxn = res->nrg = roll(table[subscript].energy.base,table[subscript].energy.interval);\n\tres->brn = roll(table[subscript].brains.base,table[subscript].brains.interval);\n\tres->mag = roll(table[subscript].magic.base,table[subscript].magic.interval);\n\tres->typ = subscript;\n\tif (subscript < 6)\n\t\t++res->typ;\n\tif (type == '5')\n\t\tres->exp = roll(600,200);\t/* give halfling some exp. */\n}\n\nvoid\tmovelvl(stat)\t\t\t\t/* update stats for new level */\nregister struct\tstats\t*stat;\n{\nregister int\ttype;\nregister unsigned new;\ndouble\tinc;\n\n\tchanged = TRUE;\n\ttype = abs(stat->typ);\n\tif (type < 6)\n\t\t;\t/* normal */\n\telse if (type < 10)\n\t\ttype = roll(1,5);\t/* experimento */\n\telse if (type < 20)\n\t\t{\n\t\ttype -= 10;\t/* king */\n\t\tif (type > 5)\n\t\t\ttype = roll(1,5);\t/* experimento */\n\t\t}\n\telse if (type < 26)\n\t\ttype -= 20;\t/* council of wise */\n\telse\n\t\ttype = roll(1,5);\t/* everything else */\n\tnew = level(stat->exp);\n\tinc = new - stat->lvl;\n\t--type; \t\t/* set up for subscripting into table */\n\tstat->str += table[type].strength.increase * inc;\n\tstat->man += table[type].manna.increase * inc;\n\tstat->brn += table[type].brains.increase * inc;\n\tstat->mag += table[type].magic.increase * inc;\n\tstat->mxn += table[type].energy.increase * inc;\n\tstat->nrg = stat->mxn + stat->shd;\n\tif ((stat->lvl = min(10000,new)) >= 1000)\n\t\t{\t/* no longer able to be king */\n\t\tstat->gld += stat->crn * 5000;\n\t\tstat->crn = 0;\n\t\tstat->typ = abs(stat->typ);\n\t\t}\n\tif (stat->lvl >= 3000 && stat->typ < 20)\n\t\t{\t/* make a member of the council */\n\t\tmvaddstr(6,0,\"You have made it to the Council of the Wise.\\nGood Luck on your search for the Holy Grail.\\n\");\n\t\tstat->rng.type = 0;\n\t\tstat->rng.duration = 3;\n\t\tstat->typ = abs(stat->typ) + (stat->typ > 10 ? 10 :20);\n\t\t}\n}\n\nchar\t*printloc(x,y)\t\t\t/* return a pointer to a string specifying location */\ndouble\tx,y;\t\t/* also, set some global flags */\n{\nregister int\tsize, loc;\nregister char\t*label;\nstatic\tchar\tres[80],\n\t\t*nametable[4][4] =\t /* names of places */\n\t\t{\n\t\t\"Anorien\",\t\"Ithilien\",\t\"Rohan\",\t\"Lorien\",\n\t\t\"Gondor\",\t\"Mordor\",\t\"Dunland\",\t\"Rovanion\",\n\t\t\"South Gondor\", \"Khand\",\t\"Eriador\",\t\"The Iron Hills\",\n\t\t\"Far Harad\",\t\"Near Harad\",\t\"The Northern Waste\", \"Rhun\"\n\t\t};\n\n\tthrone = beyond = marsh = FALSE;\n\tif (wmhl)\n\t\treturn (strcpy(res,\" is in the Wormholes\"));\n\telse if (valhala)\n\t\treturn (strcpy(res,\" is in Valhala\"));\n\telse if ((size = circ(x,y)) >= 1000)\n\t\t{\n\t\tif (max(abs(x),abs(y)) > 1100000)\n\t\t\t{\n\t\t\tlabel = \"The Point of No Return\";\n\t\t\tbeyond = TRUE;\n\t\t\t}\n\t\telse\n\t\t\tlabel = \"The Ashen Mountains\";\n\t\t}\n\telse if (size >= 55)\n\t\tlabel = \"Morannon\";\n\telse if (size >= 35)\n\t\tlabel = \"Kennaquahair\";\n\telse if (size >= 20)\n\t\t{\n\t\tlabel = \"The Dead Marshes\";\n\t\tmarsh = TRUE;\n\t\t}\n\telse if (size >= 9)\n\t\tlabel = \"The Outer Waste\";\n\telse if (size >= 5)\n\t\tlabel = \"The Moors Adventurous\";\n\telse\n\t\t{\n\t\tif (!x && !y)\n\t\t\t{\n\t\t\tlabel = \"The Lord's Chamber\";\n\t\t\tthrone = TRUE;\n\t\t\t}\n\t\telse\n\t\t\t{\n\t\t\tloc = (x > 0) + 2 * (y >= 0);\n\t\t\tlabel = nametable[size-1][loc];\n\t\t\t}\n\t\t}\n\tsprintf(res,\" is in %s  (%.0f,%.0f)\",label,x,y);\n\treturn (res);\n}\n\nvoid\tinitchar(stat)\t\t\t\t/* put in some default values */\nregister struct\tstats\t*stat;\n{\n\tstat->x = roll(-125,251);\n\tstat->y = roll(-125,251);\n\tstat->exp = stat->lvl = stat->sin = 0;\n\tstat->crn = stat->psn = 0;\n\tstat->rng.type = NONE;\n\tstat->rng.duration = 0;\n\tstat->blind = stat->vrg = stat->pal = FALSE;\n\tstat->hw = stat->amu = stat->bls = 0;\n\tstat->chm = 0;\n\tstat->gem = 0.1;\n\tstat->gld = roll(25,50) + roll(0,25) + 0.1;\n\tstat->quks = stat->swd = stat->shd = 0;\n\tstat->typ = 0;\n\tstat->status = stat->tampered = OFF;\n\tstat->scratch1 = stat->scratch2 = 0.0;\n\tstat->wormhole = 0;\n\tstat->age = 0;\n\tstat->degen = 1;\n}\n\nvoid\ttrade(stat)\t\t\t\t/* trading post */\nregister struct\tstats\t*stat;\n{\nstatic\tstruct\n\t\t{\n\t\tchar\t*item;\n\t\tint\tcost;\n\t\t}\tmenu[] =\n\t\t\t{\n\t\t\t\"Manna\",1,\n\t\t\t\"Shield\",5,\n\t\t\t\"Book\",200,\n\t\t\t\"Sword\",500,\n\t\t\t\"Charm\",1000,\n\t\t\t\"Quiksilver\",2500,\n\t\t\t\"Blessing\",7000,\n\t\t\t\"Gem\",1000\t/* this is only to ease changing the value of gems */\n\t\t\t};\ndouble\ttemp;\nint\tch;\nregister int\tsize, loop;\nbool\tcheat = FALSE;\n\n\tchanged = TRUE;\n\tclear();\n\taddstr(\"You are at a trading post. All purchases must be made with gold.\");\n\tsize = sqrt(abs(stat->x/100)) + 1;\n\tsize = min(7,size);\n\tmvprintw(4,0,\"L:Leave  P:Purchase  S:Sell Gems ? \");\n\tmove(6,0);\n\tfor (loop = 0; loop < size; ++loop)\n\t\tprintw(\"(%d) %-10s: %6d\\n\",loop+1,menu[loop].item,menu[loop].cost);\nPROMPT:\tmvprintw(1,0,\"Gold:  %9.0f  Gems:  %9.0f  Level:   %6u  Charms: %6d\\n\",stat->gld,stat->gem,stat->lvl,stat->chm);\n\tprintw(\"Shield:%9.0f  Sword: %9.0f  Quicksilver:%3d  Blessed: %s\",\n\t\tstat->shd,stat->swd,stat->quks,(stat->bls ? \" True\" : \"False\"));\n\tmove(4,36);\n\tch = rgetch();\n\tmove(15,0);\n\tclrtobot();\n\tswitch(toupper(ch))\n\t\t{\n\t\tcase 'L':\n\t\tcase '\\n':\n\t\t\tstat->x -= floor(stat->x/10);\n\t\t\tstat->y -= floor(stat->y/10);\n\t\t\treturn;\n\t\tcase 'P':\n\t\t\tmvaddstr(15,0,\"What what would you like to buy ? \");\n\t\t\tch = rgetch();\n\t\t\tmove(15,0);\n\t\t\tclrtoeol();\n\t\t\tif (ch - '0' > size)\n\t\t\t\taddstr(\"Sorry, this merchant doesn't have that.\");\n\t\t\telse\n\t\t\t\tswitch (toupper(ch))\n\t\t\t\t\t{\n\t\t\t\t\tcase '1':\n\t\t\t\t\t\tprintw(\"Manna is one per %d gold piece.  How many do you want (%.0f max) ? \",menu[0].cost,floor(stat->gld/menu[0].cost));\n\t\t\t\t\t\ttemp = inflt();\n\t\t\t\t\t\tif (temp * menu[0].cost > stat->gld || temp < 0)\n\t\t\t\t\t\t\tgoto CHEAT;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tstat->gld -= floor(temp) * menu[0].cost;\n\t\t\t\t\t\t\tif (rnd() < 0.02)\n\t\t\t\t\t\t\t\tgoto DISHON;\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tstat->man += floor(temp);\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase '2':\n\t\t\t\t\t\tprintw(\"Shields are %d per +1.  How many do you want (%.0f max) ? \",menu[1].cost,floor(stat->gld/menu[1].cost));\n\t\t\t\t\t\ttemp = inflt();\n\t\t\t\t\t\tif (!temp)\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tif (temp * menu[1].cost > stat->gld || temp < 0)\n\t\t\t\t\t\t\tgoto CHEAT;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tstat->gld -= floor(temp) * menu[1].cost;\n\t\t\t\t\t\t\tif (rnd() < 0.02)\n\t\t\t\t\t\t\t\tgoto DISHON;\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tstat->shd = floor(temp);\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase '3':\n\t\t\t\t\t\tprintw(\"A book costs %d gp.  How many do you want (%.0f max) ? \",menu[2].cost,floor(stat->gld/menu[2].cost));\n\t\t\t\t\t\ttemp = inflt();\n\t\t\t\t\t\tif (temp * menu[2].cost > stat->gld || temp < 0)\n\t\t\t\t\t\t\tgoto CHEAT;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tstat->gld -= floor(temp) * menu[2].cost;\n\t\t\t\t\t\t\tif (rnd() < 0.02)\n\t\t\t\t\t\t\t\tgoto DISHON;\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tif (rnd()*temp > stat->lvl/10 && temp != 1)\n\t\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\tprintw(\"\\nYou blew your mind!\\n\");\n\t\t\t\t\t\t\t\t\tstat->brn /= 5;\n\t\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\tstat->brn += floor(temp)*roll(25,10);\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase '4':\n\t\t\t\t\t\tprintw(\"Swords are %d gp per +1.  How many + do you want (%.0f max) ? \",menu[3].cost,floor(stat->gld/menu[3].cost));\n\t\t\t\t\t\ttemp = inflt();\n\t\t\t\t\t\tif (!temp)\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tif (temp * menu[3].cost > stat->gld || temp < 0)\n\t\t\t\t\t\t\tgoto CHEAT;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tstat->gld -= floor(temp) * menu[3].cost;\n\t\t\t\t\t\t\tif (rnd() < 0.02)\n\t\t\t\t\t\t\t\tgoto DISHON;\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tstat->swd = floor(temp);\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase '5':\n\t\t\t\t\t\tprintw(\"A charm costs %d gp.  How many do you want (%.0f max) ? \",menu[4].cost,floor(stat->gld/menu[4].cost));\n\t\t\t\t\t\ttemp = inflt();\n\t\t\t\t\t\tif (temp * menu[4].cost > stat->gld || temp < 0)\n\t\t\t\t\t\t\tgoto CHEAT;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tstat->gld -= floor(temp) * menu[4].cost;\n\t\t\t\t\t\t\tif (rnd() < 0.02)\n\t\t\t\t\t\t\t\tgoto DISHON;\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tstat->chm += floor(temp);\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase '6':\n\t\t\t\t\t\tprintw(\"Quicksilver is %d gp per +1.  How many + do you want (%.0f max) ? \",menu[5].cost,floor(stat->gld/menu[5].cost));\n\t\t\t\t\t\ttemp = inflt();\n\t\t\t\t\t\tif (!temp)\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tif (temp * menu[5].cost > stat->gld || temp < 0)\n\t\t\t\t\t\t\tgoto CHEAT;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tstat->gld -= floor(temp) * menu[5].cost;\n\t\t\t\t\t\t\tif (rnd() < 0.02)\n\t\t\t\t\t\t\t\tgoto DISHON;\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tstat->quks = min(99,floor(temp));\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tcase '7':\n\t\t\t\t\t\tprintw(\"A blessing requires a %d gp donation.  Still want one ? \",menu[6].cost);\n\t\t\t\t\t\tch = rgetch();\n\t\t\t\t\t\tif (toupper(ch) == 'Y')\n\t\t\t\t\t\t\tif (stat->gld < menu[6].cost)\n\t\t\t\t\t\t\t\tgoto CHEAT;\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tstat->gld -= menu[6].cost;\n\t\t\t\t\t\t\t\tif (rnd() < 0.02)\n\t\t\t\t\t\t\t\t\tgoto DISHON;\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t\tstat->bls = TRUE;\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\tbreak;\n\t\tcase 'S':\n\t\t\tmvprintw(15,0,\"A gem is worth %d gp.  How many do you want to sell (%.0f max) ? \",menu[7].cost,stat->gem);\n\t\t\ttemp = inflt();\n\t\t\tif (temp > stat->gem || temp < 0)\n\t\t\t\tgoto CHEAT;\n\t\t\telse\n\t\t\t\t{\n\t\t\t\tstat->gem -= floor(temp);\n\t\t\t\tstat->gld += floor(temp) * menu[7].cost;\n\t\t\t\t}\n\t\t}\n\tgoto PROMPT;\n\nCHEAT:\tmove(17,0);\n\tif (!cheat)\n\t\t{\n\t\taddstr(\"Come on, merchants aren't stupid.  Stop cheating.\\n\");\n\t\tcheat = TRUE;\n\t\tgoto PROMPT;\n\t\t}\n\telse\n\t\t{\n\t\taddstr(\"You had your chance.  This merchant happens to be\\n\");\n\t\tprintw(\"a %.0f level magic user, and you made %s mad!\\n\",roll(size*10,size*20),(rnd() < 0.5) ? \"him\" : \"her\");\n\t\tstat->x += roll(-250,500)*size;\n\t\tstat->y += roll(-250,500)*size;\n\t\tstat->nrg = min(size*20,stat->mxn);\n\t\t++stat->sin;\n\t\tpaws(23);\n\t\t}\n\treturn;\n\nDISHON:\tmvaddstr(17,0,\"The merchant stole your money!\");\n\trefresh();\n\tstat->x -= floor(stat->x/10);\n\tstat->y -= floor(stat->y/10);\n\tsleep(2);\n}\n\nvoid\tprintstats(stat)\t\t\t\t/* show characteristics */\nregister struct\tstats\t*stat;\n{\n\tmvprintw(0,0,\"%s%s\\n\",stat->name,printloc(stat->x,stat->y));\n\tmvprintw(1,0,\"Level :%7u   Energy  :%9.0f(%9.0f)  Manna:%9.0f  Users:%3d\\n\",\n\t\tstat->lvl,stat->nrg,stat->mxn + stat->shd,stat->man,users);\n\tmvprintw(2,0,\"Quick :%3.0f(%3d)  Strength:%9.0f(%9.0f)  Gold :%9.0f    \",\n\t\tspeed,stat->quk + stat->quks,strength,stat->str + stat->swd,stat->gld);\n\tswitch (stat->status)\n\t\t{\n\t\tcase PLAYING:\n\t\t\tif (stat->nrg < 0.2 * (stat->mxn + stat->shd))\n\t\t\t\taddstr(\"Low Energy\\n\");\n\t\t\telse if (stat->blind)\n\t\t\t\taddstr(\"Blind\\n\");\n\t\t\telse\n\t\t\t\tclrtoeol();\n\t\t\tbreak;\n\t\tcase CLOAKED:\n\t\t\taddstr(\"Cloaked\\n\");\n\t\t\tbreak;\n\t\tcase INBATTLE:\n\t\t\taddstr(\"In Battle\\n\");\n\t\t\tbreak;\n\t\tcase OFF:\n\t\t\taddstr(\"Off\\n\");\n\t\t}\n}\n\nvoid\tshowall(stat)\t\t\t\t/* show special items */\nregister struct\tstats\t*stat;\n{\nstatic\tchar\t*flags[] =\n\t\t\t{\n\t\t\t\"False\",\n\t\t\t\" True\"\n\t\t\t};\n\n\tmvprintw(6,0,\"Type: %3d  --  \",stat->typ);\n\tswitch (abs(stat->typ))\n\t\t{\n\t\tcase 1:\n\t\tcase 11:\n\t\tcase 21:\n\t\t\taddstr(\"Magic User\");\n\t\t\tbreak;\n\t\tcase 2:\n\t\tcase 12:\n\t\tcase 22:\n\t\t\taddstr(\"Fighter\");\n\t\t\tbreak;\n\t\tcase 3:\n\t\tcase 13:\n\t\tcase 23:\n\t\t\taddstr(\"Elf\");\n\t\t\tbreak;\n\t\tcase 4:\n\t\tcase 14:\n\t\tcase 24:\n\t\t\taddstr(\"Dwarf\");\n\t\t\tbreak;\n\t\tcase 5:\n\t\tcase 15:\n\t\tcase 25:\n\t\t\taddstr(\"Halfling\");\n\t\t\tbreak;\n\t\tcase 6:\n\t\tcase 16:\n\t\tcase 26:\n\t\t\taddstr(\"Experimento\");\n\t\t\tbreak;\n\t\tcase 90:\n\t\t\taddstr(\"Ex-Valar\");\n\t\t\tbreak;\n\t\tcase 99:\n\t\t\taddstr(\"Valar\");\n\t\t}\n\tif (stat->typ > 10 && stat->typ < 90)\n\t\tif (stat->typ > 20)\n\t\t\taddstr(\" (Council of Wise)\");\n\t\telse\n\t\t\taddstr(\" (King)\");\n\t\taddch('\\n');\n\tmvprintw(7,0,\"Experience: %9.0f\",stat->exp);\n\tmvprintw(8,0,\"Brains    : %9.0f\",stat->brn);\n\tmvprintw(9,0,\"Magic Lvl : %9.0f\",stat->mag);\n\tmvprintw(10,0,\"Sin       : %9.5f\",stat->sin);\n\tmvprintw(11,0,\"Poison    : %9.5f\",stat->psn);\n\tmvprintw(12,0,\"Gems      : %9.0f\",stat->gem);\n\tmvprintw(13,0,\"Age       : %9d\",stat->age);\n\tmvprintw(7,40,\"Holy Water: %9d\",stat->hw);\n\tmvprintw(8,40,\"Amulets   : %9d\",stat->amu);\n\tmvprintw(9,40,\"Charms    : %9d\",stat->chm);\n\tmvprintw(10,40,\"Crowns    : %9d\",stat->crn);\n\tmvprintw(11,40,\"Shield    : %9.0f\",stat->shd);\n\tmvprintw(12,40,\"Sword     : %9.0f\",stat->swd);\n\tmvprintw(13,40,\"Quickslver: %9d\",stat->quks);\n\n\tmvprintw(14,0,\"Blessing: %s   Ring: %s   Virgin: %s   Palantir: %s\",\n\t\tflags[stat->bls],flags[stat->rng.type != 0],flags[stat->vrg],flags[stat->pal]);\n}\n\nvoid\tneatstuff(stat) \t\t\t/* random things */\nregister struct\tstats\t*stat;\n{\ndouble\ttemp;\nint\tch;\n\n\tswitch ((int) roll(0,100))\n\t\t{\n\t\tcase 1:\n\t\tcase 2:\n\t\t\tif (stat->psn > 0)\n\t\t\t\t{\n\t\t\t\tmvaddstr(5,0,\"You've found a medic!  How much will you offer to be cured ? \");\n\t\t\t\ttemp = inflt();\n\t\t\t\tif (temp < 0 || temp > stat->gld)\n\t\t\t\t\t{\n\t\t\t\t\tmvaddstr(6,0,\"He was not amused, and made you worse.\\n\");\n\t\t\t\t\t++stat->psn;\n\t\t\t\t\t}\n\t\t\t\telse if (rnd()/2.0 > (temp + 1)/max(stat->gld,1))\n\t\t\t\t\tmvaddstr(6,0,\"Sorry, he wasn't interested.\\n\");\n\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\tmvaddstr(6,0,\"He accepted.\");\n\t\t\t\t\tstat->psn = max(0,stat->psn-1);\n\t\t\t\t\tstat->gld -= floor(temp);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\tmvaddstr(6,0,\"You've been caught raping and pillaging!\\n\");\n\t\t\tstat->exp += 4000;\n\t\t\tstat->sin += 0.5;\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\ttemp = roll(6,50);\n\t\t\tmvprintw(5,0,\"You've found %.0f gold pieces, want them ? \",temp);\n\t\t\tclrtoeol();\n\t\t\tch = rgetch();\n\t\t\tif (toupper(ch) == 'Y')\n\t\t\t\tstat->gld += temp;\n\t\t\tbreak;\n\t\tcase 5:\n\t\t\tif (stat->sin > 1)\n\t\t\t\t{\n\t\t\t\tmvaddstr(6,0,\"You've found a Holy Orb!\\n\");\n\t\t\t\tstat->sin -= 0.25;\n\t\t\t\t}\n\t\t\tbreak;\n\t\tcase 6:\n\t\t\tif (stat->psn < 1)\n\t\t\t\t{\n\t\t\t\tmvaddstr(6,0,\"You've been hit with a plague!\\n\");\n\t\t\t\t++stat->psn;\n\t\t\t\t}\n\t\t\tbreak;\n\t\tcase 7:\n\t\t\tmvaddstr(6,0,\"You've found some holy water.\\n\");\n\t\t\t++stat->hw;\n\t\t\tbreak;\n\t\tcase 8:\n\t\t\tmvaddstr(6,0,\"You've met a Guru. . .\");\n\t\t\tif (rnd()*stat->sin > 1)\n\t\t\t\taddstr(\"You disgusted him with your sins!\\n\");\n\t\t\telse if (stat->psn > 0)\n\t\t\t\t{\n\t\t\t\taddstr(\"He looked kindly upon you, and cured you.\\n\");\n\t\t\t\tstat->psn = 0;\n\t\t\t\t}\n\t\t\telse\n\t\t\t\t{\n\t\t\t\taddstr(\"He rewarded you for your virtue.\\n\");\n\t\t\t\tstat->man += 50;\n\t\t\t\tstat->shd += 2;\n\t\t\t\t}\n\t\t\tbreak;\n\t\tcase 9:\n\t\t\tmvaddstr(6,0,\"You've found an amulet.\\n\");\n\t\t\t++stat->amu;\n\t\t\tbreak;\n\t\tcase 10:\n\t\t\tif (stat->blind)\n\t\t\t\t{\n\t\t\t\tmvaddstr(6,0,\"You've regained your sight!\\n\");\n\t\t\t\tstat->blind = FALSE;\n\t\t\t\t}\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tif (stat->psn > 0)\n\t\t\t\tstat->nrg -= min(stat->psn*stat->mxn/45,0.9*stat->mxn);\n\t\t\tstat->nrg = max(stat->nrg,floor(stat->mxn/11));\n\t\t}\n}\n"
  },
  {
    "path": "games/phantasia/func1.c",
    "content": "/*\n * func1.c\tPhantasia support routines\n */\n\n#include \"phant.h\"\n\nbool\tfindname(name)\t\t\t\t/* return TRUE if name in use */\nregister char\t*name;\n{\nFILE\t*fp;\nstruct\tstats\tbuf;\n\n\tfp = fopen(peoplefile,\"r\");\n\twhile (fread((char *) &buf,sizeof(buf),1,fp))\n\t\tif (!strcmp(buf.name,name))\n\t\t\t{\n\t\t\tfclose(fp);\n\t\t\tmvaddstr(21,0,\"Name already in use.\\n\");\n\t\t\trefresh();\n\t\t\treturn (TRUE);\n\t\t\t}\n\tfclose(fp);\n\treturn (FALSE);\n}\n\nint\tfindspace()\t\t\t\t/* allocate space for a character in peoplefile */\n{\nFILE\t*fp;\nstruct\tstats\tbuf;\nregister int\tloc;\n\n\tloc = 0;\n\tfp = fopen(peoplefile,\"r\");\n\twhile (fread((char *) &buf,sizeof(buf),1,fp))\n\t\t{\n\t\tif (!strcmp(buf.name,\"<null>\"))\n\t\t\t{\n\t\t\tfclose(fp);\n\t\t\treturn (loc);\n\t\t\t}\n\t\telse\n\t\t\t++loc;\n\t\t}\n\tfclose(fp);\n\tfp = fopen(peoplefile,ACCESS);\n\tfseek(fp,(long) loc * sizeof(buf),0);\n\tinitchar(&buf);\n\tstrcpy(buf.name,\"inuse\");\n\tfwrite((char *) &buf,sizeof(buf),1,fp);\n\tfclose(fp);\n\treturn (loc);\n}\n\nint\tfindchar(stat)\t\t\t\t/* retrieve a character from file */\nregister struct\tstats\t*stat;\n{\nregister int\tloc = 0, loop;\nchar\tname[21];\nFILE\t*fp;\n\n\tif (fp = fopen(peoplefile,\"r\"))\n\t\t{\n\t\tclear();\n\t\tmvprintw(10,0,\"What was your character's name ? \");\n\t\tgetstring(name,21);\n\t\tstrunc(name);\n\t\twhile (fread((char *) stat,sizeof(*stat),1,fp))\n\t\t\t{\n\t\t\tif (!strcmp(stat->name,name))\n\t\t\t\t{\n\t\t\t\tmove(11,0);\n\t\t\t\trefresh();\n\t\t\t\tfclose(fp);\n\t\t\t\tnocrmode();\n\t\t\t\tfor (loop = 0; loop < 2; ++loop)\n\t\t\t\t\tif (!strcmp(getpass(\"Password ? \"),stat->pswd))\n\t\t\t\t\t\t{\n\t\t\t\t\t\tcrmode();\n\t\t\t\t\t\treturn (loc);\n\t\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t\tprintf(\"No good.\\n\");\n\t\t\t\texit1();\n\t\t\t\t/*NOTREACHED*/\n\t\t\t\t}\n\t\t\t++loc;\n\t\t\t}\n\t\t}\n\tfclose(fp);\n\taddstr(\"\\n\\nNot found.\\n\");\n\texit1();\n/*NOTREACHED*/\n}\n\nvoid\tleave(stat)\t\t\t\t/* save character in file */\nregister struct\tstats\t*stat;\n{\nlong\tltemp;\n\n\tif (!stat->lvl)\n\t\tstrcpy(stat->name,\"<null>\");\n\tstat->status = OFF;\n\ttime(&ltemp);\n\tstat->age += ltemp - secs;\n\tupdate(stat,fileloc);\n\texit1();\n\t/*NOTREACHED*/\n}\n\nvoid\ttalk(name)\t\t\t\t/* send message to all players */\nregister char\t*name;\n{\nFILE\t*fp;\nchar\taline[160];\n\n\tmvaddstr(5,0,\"Message ? \");\n\tgetstring(aline,160);\n\tfp = fopen(messfile,\"w\");\n\tif (*aline)\n\t\tfprintf(fp,\"%s:  %s\",name,aline);\n\tfclose(fp);\n}\n\nvoid\tdeath(stat)\t\t\t\t/* remove a player after dying */\nregister struct\tstats\t*stat;\n{\nFILE\t*fp;\nchar\taline[100];\nint\tch;\nregister int\tloop;\nlong\tltemp;\n\n\tclear();\n\tif (stat->typ == 99)\n\t\tif (stat->rng.duration)\n\t\t\t{\n\t\t\taddstr(\"Valar should be more cautious.  You've been killed.\\n\");\n\t\t\tprintw(\"You only have %d more chance(s).\\n\",--stat->rng.duration);\n\t\t\tpaws(3);\n\t\t\tstat->nrg = stat->mxn;\n\t\t\treturn;\n\t\t\t}\n\t\telse\n\t\t\t{\n\t\t\taddstr(\"You had your chances, but Valar aren't totally\\n\");\n\t\t\taddstr(\"immortal.  You are now left to wither and die . . .\\n\");\n\t\t\tpaws(3);\n\t\t\tstat->brn = stat->lvl /25;\n\t\t\tstat->nrg = stat->mxn;\n\t\t\tstat->quks = stat->swd = 0;\n\t\t\tstat->typ = 90;\n\t\t\treturn;\n\t\t\t}\n\tif (stat->lvl > 9999)\n\t\taddstr(\"Characters greater than level 10K must be retired.  Sorry.\");\n\tswitch(stat->rng.type)\n\t\t{\n\t\tcase -DLREG:\n\t\tcase -NAZREG:\n\t\t\tmvaddstr(4,0,\"Your ring saved you from death!\\n\");\n\t\t\trefresh();\n\t\t\tstat->rng.type = NONE;\n\t\t\tstat->nrg = stat->mxn/12+1;\n\t\t\tstat->crn -= (stat->crn > 0);\n\t\t\treturn;\n\t\tcase DLBAD:\n\t\tcase -DLBAD:\n\t\tcase NAZBAD:\n\t\tcase -NAZBAD:\n\t\tcase -SPOILED:\n\t\tcase SPOILED:\n\t\t\tmvaddstr(4,0,\"Your ring has taken control of you and turned you into a monster!\\n\");\n\t\t\tfp = fopen(monsterfile,\"r\");\n\t\t\tfor (loop = 0; loop <= 13; ++loop) {\n\t\t\t\tif (! fgets(aline,100,fp))\n\t\t\t\t        /*ignore*/;\n                        }\n\t\t\tltemp = ftell(fp);\n\t\t\tfclose(fp);\n\t\t\tfp = fopen(monsterfile,ACCESS);\n\t\t\tfseek(fp,ltemp,0);\n\t\t\tfprintf(fp,\"%-20s\",stat->name);\n\t\t\tfclose(fp);\n\t\t}\n\tinitchar(stat);\n\tfp = fopen(lastdead,\"w\");\n\tfprintf(fp,\"%s   Login:  %s\",stat->name,stat->login);\n\tfclose(fp);\n\tstrcpy(stat->name,\"<null>\");\n\tupdate(stat,fileloc);\n\tclear();\n\tmove(10,0);\n\tswitch ((int) roll(1,5))\n\t\t{\n\t\tcase 1:\n\t\t\taddstr(\"You've crapped out!  \");\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\taddstr(\"You have been disemboweled.  \");\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\taddstr(\"You've been mashed, mauled, and spit upon.  (You're dead.)\\n\");\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\taddstr(\"You died!  \");\n\t\t\tbreak;\n\t\tcase 5:\n\t\t\taddstr(\"You're a complete failure -- you've died!!\\n\");\n\t\t}\n\taddstr(\"Care to give it another try ? \");\n\tch = rgetch();\n\tif (toupper(ch) == 'Y') {\n\t\tendwin();\n\t\texecl(gameprog, \"phantasia\", \"-s\", (char*)0);\n\t}\n\texit1();\n\t/*NOTREACHED*/\n}\n\nvoid\nupdate(stat,place)\t\t\t/* update charac file */\n        register struct\tstats\t*stat;\n        register int\tplace;\n{\n        FILE\t*fp;\n\n\tfp = fopen(peoplefile,ACCESS);\n\tfseek(fp,(long) place*sizeof(*stat),0);\n\tfwrite((char *) stat,sizeof(*stat),1,fp);\n\tfclose(fp);\n}\n\nvoid\tprintplayers(stat)\t\t\t/* show users */\nregister struct\tstats\t*stat;\n{\nFILE\t*fp;\nstruct\tstats\tbuf;\nregister int\tloop = 0;\ndouble\tloc;\nlong\tltmp;\nint\tch;\n\n\tif (stat->blind)\n\t\t{\n\t\tmvaddstr(6,0,\"You can't see anyone.\\n\");\n\t\treturn;\n\t\t}\n\tloc = circ(stat->x,stat->y);\n\tmvaddstr(6,0,\"Name                         X         Y       Lvl  Type  Login\\n\");\n\tfp = fopen(peoplefile,\"r\");\n\twhile (fread((char *) &buf,sizeof(buf),1,fp))\n\t\t{\n\t\tif (buf.status)\n\t\t\t{\n\t\t\tch = (buf.status == CLOAKED) ? '?' : 'W';\n\t\t\tif (stat->typ > 10 || buf.typ > 10 || loc >= circ(buf.x,buf.y) || stat->pal)\n\t\t\t\tif (buf.status != CLOAKED || (stat->typ == 99 && stat->pal))\n\t\t\t\t\tif (buf.typ == 99)\n\t\t\t\t\t\taddstr(\"The Valar is watching you. . .\\n\");\n\t\t\t\t\telse if (buf.wormhole)\n\t\t\t\t\t\tprintw(\"%-20s         %c         %c    %6u  %3d   %-9s\\n\",\n\t\t\t\t\t\t\tbuf.name,ch,ch,buf.lvl,buf.typ,buf.login);\n\t\t\t\t\telse\n\t\t\t\t\t\tprintw(\"%-20s  %8.0f  %8.0f    %6u  %3d   %-9s\\n\",\n\t\t\t\t\t\t\tbuf.name,buf.x,buf.y,buf.lvl,buf.typ,buf.login);\n\t\t\t\telse\n\t\t\t\t\tif (buf.typ == 99)\n\t\t\t\t\t\t--loop;\n\t\t\t\t\telse\n\t\t\t\t\t\tprintw(\"%-20s         ?         ?    %6u  %3d   %-9s\\n\",\n\t\t\t\t\t\t\tbuf.name,buf.lvl,buf.typ,buf.login);\n\t\t\t++loop;\n\t\t\t}\n\t\t}\n\tfclose(fp);\n\ttime(&ltmp);\n\tprintw(\"Total users = %d    %s\\n\",loop,ctime(&ltmp));\n\trefresh();\n}\n\n\nvoid\tprinthelp()\t\t\t\t/* print help file */\n{\nFILE\t*fp;\nchar\tinstr[100];\n\n\tfp = fopen(helpfile,\"r\");\n\twhile (fgets(instr,100,fp))\n\t\tfputs(instr,stdout);\n\tfclose(fp);\n}\n\nvoid\ttitlestuff()\t\t\t\t/* print out a header */\n{\nFILE\t*fp;\nchar\tinstr[80], hiname[21], nxtname[21], aline[80];\nbool\tcowfound = FALSE, kingfound = FALSE;\nstruct\tstats\tbuf;\ndouble\thiexp, nxtexp;\nunsigned\thilvl, nxtlvl;\nregister int\tloop;\n\n\tmvaddstr(0,15,\"W e l c o m e   t o   P h a n t a s i a (vers. 3.2)!\");\n\tfp = fopen(motd,\"r\");\n\tif (fgets(instr,80,fp))\n\t\tmvaddstr(2,40 - strlen(instr)/2,instr);\n\tfclose(fp);\n\tfp = fopen(peoplefile,\"r\");\n\twhile (fread((char *) &buf,sizeof(buf),1,fp))\n\t\tif (buf.typ > 10 && buf.typ < 20)\n\t\t\t{\n\t\t\tsprintf(instr,\"The present ruler is %s  Level:%d\",buf.name,buf.lvl);\n\t\t\tmvaddstr(4,40 - strlen(instr)/2,instr);\n\t\t\tkingfound = TRUE;\n\t\t\tbreak;\n\t\t\t}\n\tif (!kingfound)\n\t\tmvaddstr(4,24,\"There is no ruler at this time.\");\n\tfseek(fp,0L,0);\n\twhile (fread((char *) &buf,sizeof(buf),1,fp))\n\t\tif (buf.typ == 99)\n\t\t\t{\n\t\t\tsprintf(instr,\"The Valar is %s   Login:  %s\",buf.name,buf.login);\n\t\t\tmvaddstr(6,40 - strlen(instr)/2,instr);\n\t\t\tbreak;\n\t\t\t}\n\tfseek(fp,0L,0);\n\twhile (fread((char *) &buf,sizeof(buf),1,fp))\n\t\tif (buf.typ > 20 && buf.typ < 90)\n\t\t\t{\n\t\t\tif (!cowfound)\n\t\t\t\t{\n\t\t\t\tmvaddstr(8,30,\"Council of the Wise:\");\n\t\t\t\tloop = 10;\n\t\t\t\tcowfound = TRUE;\n\t\t\t\t}\n\t\t\t/* This assumes a finite (<=7) number of C.O.W.: */\n\t\t\tsprintf(instr,\"%s   Login:  %s\",buf.name,buf.login);\n\t\t\tmvaddstr(loop++,40 - strlen(instr)/2,instr);\n\t\t\t}\n\tfseek(fp,0L,0);\n\t*nxtname = *hiname = '\\0';\n\thiexp = 0.0;\n\tnxtlvl = hilvl = 0;\n\twhile (fread((char *) &buf,sizeof(buf),1,fp))\n\t\tif (buf.exp > hiexp && buf.typ < 20)\n\t\t\t{\n\t\t\tnxtexp = hiexp;\n\t\t\thiexp = buf.exp;\n\t\t\tnxtlvl = hilvl;\n\t\t\thilvl = buf.lvl;\n\t\t\tstrcpy(nxtname,hiname);\n\t\t\tstrcpy(hiname,buf.name);\n\t\t\t}\n\t\telse if (buf.exp > nxtexp && buf.typ < 20)\n\t\t\t{\n\t\t\tnxtexp = buf.exp;\n\t\t\tnxtlvl = buf.lvl;\n\t\t\tstrcpy(nxtname,buf.name);\n\t\t\t}\n\tfclose(fp);\n\tmvaddstr(17,28,\"Highest characters are:\");\n\tsprintf(instr,\"%s  Level:%d   and   %s  Level:%d\",hiname,hilvl,nxtname,nxtlvl);\n\tmvaddstr(19,40 - strlen(instr)/2,instr);\n\tfp = fopen(lastdead,\"r\");\n\tif (! fgets(aline,80,fp))\n\t        /*ignore*/;\n\tsprintf(instr,\"The last character to die is %s\",aline);\n\tmvaddstr(21,40 - strlen(instr)/2,instr);\n\tfclose(fp);\n\trefresh();\n}\n\n\n\nvoid\tprintmonster()\t\t\t\t/* do a monster list on the terminal */\n{\nFILE\t*fp;\nregister int\tcount = 0;\nchar\tinstr[100];\n\n\tputs(\" #  Name                    Str     Brains  Quick   Hits    Exp     Treas   Type    Flock%\\n\");\n\tfp = fopen(monsterfile,\"r\");\n\twhile (fgets(instr,100,fp))\n\t\tprintf(\"%2d  %s\",count++,instr);\n\tfclose(fp);\n}\n\nvoid\nexit1() \t\t\t\t/* exit, but cleanup */\n{\n\tmove(23,0);\n\trefresh();\n\tnocrmode();\n\tendwin();\n\texit(0);\n\t/*NOTREACHED*/\n}\n\nvoid\tinit1() \t\t\t\t/* set up for screen updating */\n{\n\t\t/* catch/ingnore signals */\n\tsignal(SIGQUIT,SIG_IGN);\n\tsignal(SIGALRM,SIG_IGN);\n\tsignal(SIGTERM,SIG_IGN);\n\tsignal(SIGTSTP,SIG_IGN);\n\tsignal(SIGTTIN,SIG_IGN);\n\tsignal(SIGTTOU,SIG_IGN);\n\tsignal(SIGINT,SIG_IGN);\n\n\tsrand((unsigned) time((long *) NULL));\t/* prime random numbers */\n\tinitscr();\n\tnoecho();\n\tcrmode();\n\tclear();\n\trefresh();\n}\n\nvoid\ngetstring(cp,mx)\t\t\t\t/* get a string from the stdscr at current y,x */\n        register char\t*cp;\n        register int\tmx;\n{\n        register int\tloop = 0, x, y, xorig;\n        int\tch;\n\n\tgetyx(stdscr,y,xorig);\n\tclrtoeol();\n\trefresh();\n\twhile((ch = getch()) != '\\n' && loop < mx - 1)\n\t\tswitch (ch)\n\t\t\t{\n\t\t\tcase '\\033':\t/* escape */\n\t\t\tcase '\\010':\t/* backspace */\n\t\t\t\tif (loop)\n\t\t\t\t\t{\n\t\t\t\t\t--loop;\n\t\t\t\t\tgetyx(stdscr,y,x);\n\t\t\t\t\tmvaddch(y,x-1,' ');\n\t\t\t\t\tmove(y,x-1);\n\t\t\t\t\trefresh();\n\t\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase '\\030':\t/* ctrl-x */\n\t\t\t\tloop = 0;\n\t\t\t\tmove(y,xorig);\n\t\t\t\tclrtoeol();\n\t\t\t\trefresh();\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tif (ch >= ' ') /* printing char */\n\t\t\t\t\t{\n\t\t\t\t\taddch(ch);\n\t\t\t\t\tcp[loop++] = ch;\n\t\t\t\t\trefresh();\n\t\t\t\t\t}\n\t\t\t}\n\tcp[loop] = '\\0';\n}\n\n\nvoid\tshowusers()\t\t\t\t/* print a list of all characters */\n{\nstruct\tstats\tbuf;\nFILE\t*fp;\n\n\tif (fp = fopen(peoplefile,\"r\"))\n\t\t{\n\t\tputs(\"Current characters on file are:\\n\");\n\t\twhile (fread((char *) &buf,sizeof(buf),1,fp))\n\t\t\tif (strcmp(\"<null>\",buf.name))\n\t\t\t\tprintf(\"%-20s   Login: %-9s  Level: %6u\\n\",buf.name,buf.login,buf.lvl);\n\t\tfclose(fp);\n\t\t}\n}\n\nvoid\tkingstuff(stat) \t\t\t/* stuff upon entering throne */\nregister struct \tstats\t*stat;\n{\nFILE\t*fp;\nstruct\tstats\tbuf;\nstruct\tnrgvoid\tvbuf;\nregister int\tloc = 0;\n\n\tif (stat->typ < 10)\t/* check to see if king -- assumes crown */\n\t\t{\n\t\tfp = fopen(peoplefile,\"r\");\n\t\twhile (fread((char *) &buf,sizeof(buf),1,fp))\n\t\t\tif (buf.typ > 10 && buf.typ < 20)\t/* found old king */\n\t\t\t\tif (buf.status != OFF)\n\t\t\t\t\t{\n\t\t\t\t\tmvaddstr(6,0,\"The king is playing, so you cannot steal his throne\\n\");\n\t\t\t\t\tstat->x = stat->y = 9;\n\t\t\t\t\tmove(3,0);\n\t\t\t\t\tfclose(fp);\n\t\t\t\t\treturn;\n\t\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\tbuf.typ -= 10;\n\t\t\t\t\tif (buf.crn)\n\t\t\t\t\t\t--buf.crn;\n\t\t\t\t\tfclose(fp);\n\t\t\t\t\tupdate(&buf,loc);\nKING:\t\t\t\tstat->typ = abs(stat->typ) + 10;\n\t\t\t\t\tmvaddstr(6,0,\"You have become king!\\n\");\n\t\t\t\t\tfp = fopen(messfile,\"w\");\n\t\t\t\t\tfprintf(fp,\"All hail the new king!\");\n\t\t\t\t\tfclose(fp);\n\t\t\t\t\t/* clear all energy voids */\n\t\t\t\t\tfp = fopen(voidfile,\"r\");\n\t\t\t\t\tif (fread((char *) &vbuf,sizeof(vbuf),1,fp) != 1)\n\t\t\t\t\t        /*ignore*/;\n\t\t\t\t\tfclose(fp);\n\t\t\t\t\tfp = fopen(voidfile,\"w\");\n\t\t\t\t\tfwrite((char *) &vbuf,sizeof(vbuf),1,fp);\n\t\t\t\t\tfclose(fp);\n\t\t\t\t\tgoto EXIT;\n\t\t\t\t\t}\n\t\t\telse\n\t\t\t\t++loc;\n\t\tfclose(fp);\t  /* old king not found -- install new one */\n\t\tgoto KING;\n\t\t}\nEXIT:\tmvaddstr(3,0,\"0:Decree  \");\n}\n\nvoid\npaws(where)\t\t\t\t/* wait for input to continue */\n        int\twhere;\n{\n\tmvaddstr(where,0,\"-- more --\");\n\trgetch();\n}\n\nvoid\tcstat() \t\t\t\t/* examine/change stats of a character */\n{\nstruct\tstats charac;\nchar\ts[60], flag[2];\nFILE\t*fp;\nregister int\tloc = 0;\nint\tc, temp, today;\nlong\tltemp;\ndouble\tdtemp;\n\n\tflag[0] = 'F';\tflag[1] = 'T';\n\tmvaddstr(10,0,\"Which character do you want to look at ? \");\n\tgetstring(s,60);\n\tif (fp = fopen(peoplefile,\"r\"))\n\t\twhile (fread((char *) &charac,sizeof(charac),1,fp))\n\t\t\tif (!strcmp(s,charac.name))\n\t\t\t\tgoto FOUND;\n\t\t\telse\n\t\t\t\t++loc;\n\tmvaddstr(11,0,\"Not found.\");\n\texit1();\n\t/*NOTREACHED*/\n\nFOUND:\tfclose(fp);\n\ttime(&ltemp);\n\ttoday = localtime(&ltemp)->tm_yday;\n\tif (!su)\n\t\tstrcpy(charac.pswd,\"XXXXXXXX\");\n\tclear();\nTOP:\tmvprintw(0,0,\"a:Name         %s\\n\",charac.name);\n\tprintw(\"b:Password     %s\\n\",charac.pswd);\n\tprintw(\" :Login        %s\\n\",charac.login);\n\ttemp = today - charac.lastused;\n\tif (temp < 0)\n\t\ttemp += 365;\n\tprintw(\"c:Used         %d\\n\",temp);\n\tmvprintw(5,0,\"d:Experience   %.0f\\n\",charac.exp);\n\tprintw(\"e:Level        %d\\n\",charac.lvl);\n\tprintw(\"f:Strength     %.0f\\n\",charac.str);\n\tprintw(\"g:Sword        %.0f\\n\",charac.swd);\n\tprintw(\"h:Quickness    %d\\n\",charac.quk);\n\tprintw(\"i:Quikslvr     %d\\n\",charac.quks);\n\tprintw(\"j:Energy       %.0f\\n\",charac.nrg);\n\tprintw(\"k:Max-Nrg      %.0f\\n\",charac.mxn);\n\tprintw(\"l:Shield       %.0f\\n\",charac.shd);\n\tprintw(\"m:Magic        %.0f\\n\",charac.mag);\n\tprintw(\"n:Manna        %.0f\\n\",charac.man);\n\tprintw(\"o:Brains       %.0f\\n\",charac.brn);\n\tmvprintw(0,40,\"p:X-coord      %.0f\\n\",charac.x);\n\tmvprintw(1,40,\"q:Y-coord      %.0f\\n\",charac.y);\n\tif (su)\n\t\tmvprintw(2,40,\"r:Wormhole     %d\\n\",charac.wormhole);\n\telse\n\t\tmvprintw(2,40,\"r:Wormhole     %c\\n\",flag[charac.wormhole != 0]);\n\tmvprintw(3,40,\"s:Type         %d\\n\",charac.typ);\n\tmvprintw(5,40,\"t:Sin          %0.3f\\n\",charac.sin);\n\tmvprintw(6,40,\"u:Poison       %0.3f\\n\",charac.psn);\n\tmvprintw(7,40,\"v:Gold         %.0f\\n\",charac.gld);\n\tmvprintw(8,40,\"w:Gem          %.0f\\n\",charac.gem);\n\tmvprintw(9,40,\"x:Holy Water   %d\\n\",charac.hw);\n\tmvprintw(10,40,\"y:Charms       %d\\n\",charac.chm);\n\tmvprintw(11,40,\"z:Crowns       %d\\n\",charac.crn);\n\tmvprintw(12,40,\"1:Amulets      %d\\n\",charac.amu);\n\tmvprintw(13,40,\"2:Age          %d\\n\",charac.age);\n\tmvprintw(18,5,\"3:Virgin %c  4:Blessed %c  5:Ring %c  6:Blind %c  7:Palantir %c\",\n\t\tflag[charac.vrg],flag[charac.bls],flag[charac.rng.type != 0],flag[charac.blind],flag[charac.pal]);\n\tif (!su)\n\t\texit1();\n\tmvaddstr(15,40,\"!:Quit\");\n\tmvaddstr(16,40,\"?:Delete\");\n\tmvaddstr(19,30,\"8:Duration\");\n\tmvaddstr(21,0,\"What would you like to change? \");\n\tc = rgetch();\n\tswitch(c)\n\t\t{\n\t\tcase 'p':\t/* change x coord */\n\t\t\tmvprintw(23,0,\"x = %f; x = \",charac.x);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.x = dtemp;\n\t\t\tbreak;\n\t\tcase 'q':\t/* change y coord */\n\t\t\tmvprintw(23,0,\"y = %f; y = \",charac.y);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.y = dtemp;\n\t\t\tbreak;\n\t\tcase 'd':\t/* change Experience */\n\t\t\tmvprintw(23,0,\"exp = %f; exp = \",charac.exp);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.exp = dtemp;\n\t\t\tbreak;\n\t\tcase 'e':\t/* change level */\n\t\t\tmvprintw(23,0,\"lvl = %d; lvl;= \",charac.lvl);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.lvl = dtemp;\n\t\t\tbreak;\n\t\tcase 'h':\t/* change quickness */\n\t\t\tmvprintw(23,0,\"quk = %d; quk;= \",charac.quk);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.quk = dtemp;\n\t\t\tbreak;\n\t\tcase 'f':\t/* change strength */\n\t\t\tmvprintw(23,0,\"str = %f; str;= \",charac.str);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.str = dtemp;\n\t\t\tbreak;\n\t\tcase 't':\t/* change Sin */\n\t\t\tmvprintw(23,0,\"sin = %f; sin;= \",charac.sin);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.sin = dtemp;\n\t\t\tbreak;\n\t\tcase 'n':\t/* change manna */\n\t\t\tmvprintw(23,0,\"man = %f; man;= \",charac.man);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.man = dtemp;\n\t\t\tbreak;\n\t\tcase 'v':\t/* change gold */\n\t\t\tmvprintw(23,0,\"gld = %f; gld;= \",charac.gld);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.gld = dtemp;\n\t\t\tbreak;\n\t\tcase 'j':\t/* change energy */\n\t\t\tmvprintw(23,0,\"nrg = %f; nrg;= \",charac.nrg);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.nrg = dtemp;\n\t\t\tbreak;\n\t\tcase 'k':\t/* change Maximum energy */\n\t\t\tmvprintw(23,0,\"mxn = %f; mxn;= \",charac.mxn);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.mxn = dtemp;\n\t\t\tbreak;\n\t\tcase 'm':\t/* change magic */\n\t\t\tmvprintw(23,0,\"mag = %f; mag;= \",charac.mag);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.mag = dtemp;\n\t\t\tbreak;\n\t\tcase 'o':\t/* change brains */\n\t\t\tmvprintw(23,0,\"brn = %f; brn;= \",charac.brn);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.brn = dtemp;\n\t\t\tbreak;\n\t\tcase 'z':\t/* change crowns */\n\t\t\tmvprintw(23,0,\"crn = %d; crn;= \",charac.crn);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.crn = dtemp;\n\t\t\tbreak;\n\t\tcase '5':\t/* change ring type */\n\t\t\tmvprintw(23,0,\"rng-type = %d; rng-type;= \",charac.rng.type);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.rng.type = dtemp;\n\t\t\tbreak;\n\t\tcase '8':\t/* change ring duration */\n\t\t\tmvprintw(23,0,\"rng-duration = %d; rng-duration;= \",charac.rng.duration);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.rng.duration = dtemp;\n\t\t\tbreak;\n\t\tcase '7':\t/* change palantir */\n\t\t\tmvprintw(23,0,\"pal = %d; pal;= \",charac.pal);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\t{\n\t\t\t\tcharac.pal = dtemp;\n\t\t\t\tcharac.pal = (charac.pal != 0);\n\t\t\t\t}\n\t\t\tbreak;\n\t\tcase 'u':\t/* change poison */\n\t\t\tmvprintw(23,0,\"psn = %f; psn;= \",charac.psn);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.psn = dtemp;\n\t\t\tbreak;\n\t\tcase 'x':\t/* change holy water */\n\t\t\tmvprintw(23,0,\"hw = %d; hw;= \",charac.hw);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.hw = dtemp;\n\t\t\tbreak;\n\t\tcase '1':\t/* change amulet */\n\t\t\tmvprintw(23,0,\"amu = %d; amu;= \",charac.amu);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.amu = dtemp;\n\t\t\tbreak;\n\t\tcase '4':\t/* change Blessing */\n\t\t\tmvprintw(23,0,\"bls = %d; bls;= \",charac.bls);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\t{\n\t\t\t\tcharac.bls = dtemp;\n\t\t\t\tcharac.bls = (charac.bls != 0);\n\t\t\t\t}\n\t\t\tbreak;\n\t\tcase 'y':\t/* change Charm */\n\t\t\tmvprintw(23,0,\"chm = %d; chm;= \",charac.chm);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.chm = dtemp;\n\t\t\tbreak;\n\t\tcase 'w':\t/* change Gems */\n\t\t\tmvprintw(23,0,\"gem = %f; gem;= \",charac.gem);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.gem = dtemp;\n\t\t\tbreak;\n\t\tcase 'i':\t/* change Quicksilver */\n\t\t\tmvprintw(23,0,\"quks = %d; quks;= \",charac.quks);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.quks = dtemp;\n\t\t\tbreak;\n\t\tcase 'g':\t/* change swords */\n\t\t\tmvprintw(23,0,\"swd = %f; swd;= \",charac.swd);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.swd = dtemp;\n\t\t\tbreak;\n\t\tcase 'l':\t/* change shields */\n\t\t\tmvprintw(23,0,\"shd = %f; shd;= \",charac.shd);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.shd = dtemp;\n\t\t\tbreak;\n\t\tcase 's':\t/* change type */\n\t\t\tmvprintw(23,0,\"typ = %d; typ;= \",charac.typ);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.typ = dtemp;\n\t\t\tbreak;\n\t\tcase '3':\t/* change virgin */\n\t\t\tmvprintw(23,0,\"vrg = %d; vrg;= \",charac.vrg);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\t{\n\t\t\t\tcharac.vrg = dtemp;\n\t\t\t\tcharac.vrg = (charac.vrg != 0);\n\t\t\t\t}\n\t\t\tbreak;\n\t\tcase 'c':\t/* change last-used */\n\t\t\tmvprintw(23,0,\"last-used = %d; last-used;= \",charac.lastused);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.lastused = dtemp;\n\t\t\tbreak;\n\t\tcase 'b':\t\t/* change password */\n\t\t\tmvaddstr(23,0,\"New password: \");\n\t\t\tgetstring(s,60);\n\t\t\tif (*s)\n\t\t\t\tstrcpy(charac.pswd,s);\n\t\t\tbreak;\n\t\tcase 'a':\t\t/* change name */\n\t\t\tmvaddstr(23,0,\"New name: \");\n\t\t\tgetstring(s,60);\n\t\t\tif (*s)\n\t\t\t\tstrcpy(charac.name,s);\n\t\t\tbreak;\n\t\tcase 'r':\t/* change wormhole */\n\t\t\tmvprintw(23,0,\"wormhole = %d; wormhole;= \",charac.wormhole);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.wormhole = dtemp;\n\t\t\tbreak;\n\t\tcase '2':\t/* change age */\n\t\t\tmvprintw(23,0,\"age = %d; age;= \",charac.age);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\tcharac.age = dtemp;\n\t\t\tbreak;\n\t\tcase '6':\t/* change blindness */\n\t\t\tmvprintw(23,0,\"blind = %d; blind;= \",charac.blind);\n\t\t\tdtemp = inflt();\n\t\t\tif (dtemp != 0.0)\n\t\t\t\t{\n\t\t\t\tcharac.blind = dtemp;\n\t\t\t\tcharac.blind = (charac.blind != 0);\n\t\t\t\t}\n\t\t\tbreak;\n\t\tcase '!':\t/* quit, update */\n\t\t\tgoto LEAVE;\n\t\tcase '?':\t/* delete char */\n\t\t\tstrcpy(charac.name,\"<null>\");\n\t\t\tinitchar(&charac);\n\t\t\tgoto LEAVE;\n\t\t}\n\tgoto TOP;\nLEAVE:\tcharac.status = OFF;\n\tupdate(&charac,loc);\n}\n\nunsigned level(expr)\t\t\t/* calculate level */\ndouble\texpr;\n{\n\tif (expr < 1.1e+7)\n\t\treturn (pow((expr/1000.0), 0.4875));\n\telse\n\t\treturn (pow((expr/1250.0), 0.4865));\n}\n\nvoid\tstrunc(str)\t\t\t\t/* remove blank spaces at the end of str[] */\nregister char\t*str;\n{\nregister int\tloop;\n\tloop = strlen(str) - 1;\n\twhile (str[--loop] == ' ')\n\t\tstr[loop] = '\\0';\n}\n\ndouble\ninflt()\t\t\t\t/* get a floating point # from the terminal */\n{\n        char\taline[80];\n        double\tres;\n\n\tgetstring(aline,80);\n\tif (sscanf(aline, \"%lf\", &res) < 1)\n\t\tres = 0;\n\treturn (res);\n}\n\nvoid\tcheckmov(stat)\t\t\t\t/* see if beyond PONR */\nregister struct\tstats\t*stat;\n{\n\tif (beyond)\n\t\t{\n\t\tstat->x = sgn(stat->x) * max(abs(stat->x),1.1e+6);\n\t\tstat->y = sgn(stat->y) * max(abs(stat->y),1.1e+6);\n\t\t}\n}\nvoid\tscramble(stat)\t\t\t/* mix up some stats */\nregister struct\tstats\t*stat;\n{\ndouble\tbuf[5],\ttemp;\nregister int\tfirst, second;\nregister double\t*bp;\n\n\tbp = buf;\n\t*bp++ = stat->str;\n\t*bp++ = stat->man;\n\t*bp++ = stat->brn;\n\t*bp++ = stat->mag;\n\t*bp++ = stat->nrg;\n\n\tbp = buf;\n\tfirst = roll(0,5);\n\tsecond = roll(0,5);\n\ttemp = bp[first];\n\tbp[first] = bp[second];\n\tbp[second] = temp;\n\n\tstat->str = *bp++;\n\tstat->man = *bp++;\n\tstat->brn = *bp++;\n\tstat->mag = *bp++;\n\tstat->nrg = *bp++;\n}\n"
  },
  {
    "path": "games/phantasia/func2.c",
    "content": "/*\n * func2.c\tPhantasia support routines\n */\n\n#include \"phant.h\"\n\nstatic void\nvoidupdate(vp,loc)\t\t\t/* update an energy void */\n        register struct nrgvoid\t*vp;\n        register int\tloc;\n{\n        FILE\t*fp;\n\n\tfp = fopen(voidfile,ACCESS);\n\tfseek(fp,(long) loc*sizeof(*vp),0);\n\tfwrite((char *) vp,sizeof(*vp),1,fp);\n\tfclose(fp);\n}\n\nstatic void\nstatread(stat,loc)\t\t\t/* read a charac. structure */\n        register struct\tstats\t*stat;\n        register int\tloc;\n{\n        FILE\t*fp;\n\n\tfp = fopen(peoplefile,\"r\");\n\tfseek(fp,(long) loc * sizeof(*stat),0);\n\tif (fread((char *) stat,sizeof(*stat),1,fp) != 1)\n\t        /*ignore*/;\n\tfclose(fp);\n}\n\nstatic void\ntampered(stat,what,bufp)\t\t\t/* decree'd, intervened, etc. */\n        register struct\tstats\t*stat, *bufp;\n        int\twhat;\n{\n        struct\tnrgvoid\tvbuf;\n        register int\tloc;\n        struct\tstats\tsbuf;\n        FILE\t*fp;\n\n\tchanged = TRUE;\n\tmove(6,0);\n\tstat->tampered = OFF;\n\tswitch ((int) what)\n\t\t{\n\t\tcase NRGVOID:\n\t\t\taddstr(\"You've hit an energy void !\\n\");\n\t\t\tstat->man /= 3;\n\t\t\tstat->nrg /= 2;\n\t\t\tstat->gld = floor(stat->gld/1.25) + 0.1;\n\t\t\tstat->x += 10;\n\t\t\tbreak;\n\t\tcase TRANSPORT:\n\t\t\taddstr(\"The king transported you !  \");\n\t\t\tif (stat->chm)\n\t\t\t\t{\n\t\t\t\taddstr(\"But your charm save you. . .\\n\");\n\t\t\t\t--stat->chm;\n\t\t\t\t}\n\t\t\telse\n\t\t\t\t{\n\t\t\t\tstat->x += roll(-50,100) * circ(stat->x,stat->y);\n\t\t\t\tstat->y += roll(-50,100) * circ(stat->x,stat->y);\n\t\t\t\taddch('\\n');\n\t\t\t\t}\n\t\t\tbreak;\n\t\tcase GOLD:\n\t\t\tprintw(\"The king has bestowed %.0f gold pieces on you !\\n\",bufp->scratch1);\n\t\t\tstat->gld += bufp->scratch1;\n\t\t\tbreak;\n\t\tcase CURSED:\n\t\t\taddstr(\"You've been cursed !  \");\n\t\t\tif (stat->bls)\n\t\t\t\t{\n\t\t\t\taddstr(\"But your blessing saved you. . .\\n\");\n\t\t\t\tstat->bls = FALSE;\n\t\t\t\t}\n\t\t\telse\n\t\t\t\t{\n\t\t\t\taddch('\\n');\n\t\t\t\tstat->psn += 2;\n\t\t\t\tstat->nrg = 10;\n\t\t\t\tstat->mxn  *= 0.95;\n\t\t\t\tstat->status = PLAYING;\n\t\t\t\t}\n\t\t\tbreak;\n\t\tcase VAPORIZED:\n\t\t\taddstr(\"Woops!  You've been vaporized!\\n\");\n\t\t\tdeath(stat);\n\t\t\tbreak;\n\t\tcase MONSTER:\n\t\t\taddstr(\"The Valar zapped you with a monster!\\n\");\n\t\t\tpaws(7);\n\t\t\tfight(stat,(int) bufp->scratch1);\n\t\t\treturn;\n\t\tcase BLESS:\n\t\t\taddstr(\"The Valar has blessed you!\\n\");\n\t\t\tstat->nrg = (stat->mxn *= 1.05) + stat->shd;\n\t\t\tstat->man += 500;\n\t\t\tstat->str += 0.5;\n\t\t\tstat->brn += 0.5;\n\t\t\tstat->mag += 0.5;\n\t\t\tstat->psn = min(0.5,stat->psn);\n\t\t\tbreak;\n\t\tcase MOVED:\n\t\t\taddstr(\"You've been relocated. . .\\n\");\n\t\t\tstat->x = bufp->scratch1;\n\t\t\tstat->y = bufp->scratch2;\n\t\t\tbreak;\n\t\tcase HEAL:\n\t\t\taddstr(\"You've been healed!\\n\");\n\t\t\tstat->psn -=  0.25;\n\t\t\tstat->nrg = stat->mxn + stat->shd;\n\t\t\tbreak;\n\t\tcase STOLEN:\n\t\t\taddstr(\"You'Ve been bumped off as Valar!\\n\");\n\t\t\tstat->typ = 20 + roll(1,6);\n\t\t\tbreak;\n\t\tcase GRAIL:\n\t\t\taddstr(\"You have found The Holy Grail!!\\n\");\n\t\t\tif (stat->typ < 20)\n\t\t\t\t{\n\t\t\t\taddstr(\"However, you are not experienced enough to behold it.\\n\");\n\t\t\t\tstat->sin *= stat->sin;\n\t\t\t\tstat->man +=  1000;\n\t\t\t\t}\n\t\t\telse if (stat->typ == 99 || stat->typ == 90)\n\t\t\t\t{\n\t\t\t\taddstr(\"You have made it to the position of Valar once already.\\n\");\n\t\t\t\taddstr(\"The Grail is of no more use to you now.\\n\");\n\t\t\t\t}\n\t\t\telse\n\t\t\t\t{\n\t\t\t\taddstr(\"It is now time to see if you are worthy to behold it. . .\\n\");\n\t\t\t\trefresh();\n\t\t\t\tsleep(4);\n\t\t\t\tif (rnd() / 2.0 < stat->sin)\n\t\t\t\t\t{\n\t\t\t\t\taddstr(\"You blew this one!\\n\");\n\t\t\t\t\tstat->str = stat->man = stat->quk = stat->nrg = stat->mxn = stat->x = stat->y =\n\t\t\t\t\t\tstat->mag = stat->brn = stat->exp =1;\n\t\t\t\t\tstat->lvl = 0;\n\t\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\taddstr(\"You made to position of Valar!\\n\");\n\t\t\t\t\tstat->typ = 99;\n\t\t\t\t\tfp = fopen(peoplefile,\"r\");\n\t\t\t\t\tloc = 0;\n\t\t\t\t\twhile (fread((char *) &sbuf,sizeof(sbuf),1,fp))\n\t\t\t\t\t\tif (sbuf.typ == 99)\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tsbuf.tampered = STOLEN;\n\t\t\t\t\t\t\tupdate(&sbuf,loc);\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\t++loc;\n\t\t\t\t\tfclose(fp);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\tvbuf.active = TRUE;\n\t\t\tvbuf.x = roll(-1e6,2e6);\n\t\t\tvbuf.y = roll(-1e6,2e6);\n\t\t\tvoidupdate(&vbuf,0);\n\t\t\tbreak;\n\t\t}\n}\n\nvoid\nchecktampered(stat)\t\t\t/* see if decree'd etc. */\n        register struct\tstats\t*stat;\n{\n        struct\tnrgvoid\tvbuf;\n        struct\tstats sbuf;\n        FILE\t*fp;\n        register int\tloc = 0;\n\n\t/* first check for energy voids */\n\tfp = fopen(voidfile,\"r\");\n\twhile (fread((char *) &vbuf,sizeof(vbuf),1,fp))\n\t\tif (vbuf.active && vbuf.x == stat->x && vbuf.y == stat->y)\n\t\t\t{\n\t\t\tfclose(fp);\n\t\t\tif (loc)\n\t\t\t\t{\n\t\t\t\tvbuf.active = FALSE;\n\t\t\t\tvoidupdate(&vbuf,loc);\n\t\t\t\ttampered(stat,NRGVOID,&sbuf);\n\t\t\t\t}\n\t\t\telse if (stat->status != CLOAKED)\n\t\t\t\ttampered(stat,GRAIL,&sbuf);\n\t\t\tbreak;\n\t\t\t}\n\t\telse\n\t\t\t++loc;\n\tfclose(fp);\n\t/* now check for other things */\n\tstatread(&sbuf,fileloc);\n\tif (sbuf.tampered)\n\t\ttampered(stat,sbuf.tampered,&sbuf);\n}\n\nvoid\ndecree(stat)\t\t\t\t/* king and valar stuff */\n        register struct\tstats\t*stat;\n{\n        FILE\t*fp;\n        short\targ;\n        char\taline[80], *cp;\n        struct\tstats\tsbuf;\n        struct\tnrgvoid\tvbuf;\n        double\ttemp1 = 0.0, temp2 = 0.0;\n        int\tch;\n        register int\tloc = 0;\n\n\tmove(3,0);\n\tclrtoeol();\n\tif (stat->typ < 20 && !su)\t/* king */\n\t\t{\n\t\taddstr(\"1:Transport  2:Curse  3:Energy Void  4:Bestow  5:Collect Taxes  \");\n\t\tch = rgetch();\n\t\tmove(3,0);\n\t\tclrtoeol();\n\t\tswitch (ch)\n\t\t\t{\n\t\t\tcase '1':\n\t\t\t\targ = TRANSPORT;\n\t\t\t\tcp = \"transport\";\n\t\t\t\tbreak;\n\t\t\tcase '2':\n\t\t\t\targ = CURSED;\n\t\t\t\tcp = \"curse\";\n\t\t\t\tbreak;\n\t\t\tcase '3':\n\t\t\t\taddstr(\"Enter the X Y coordinates of void ? \");\n\t\t\t\tgetstring(aline,30);\n\t\t\t\tsscanf(aline,\"%lf %lf\",&temp1,&temp2);\n\t\t\t\tvbuf.x = floor(temp1);\n\t\t\t\tvbuf.y = floor(temp2);\n\t\t\t\tvbuf.active = TRUE;\n\t\t\t\tvoidupdate(&vbuf,allocvoid());\n\t\t\t\tgoto EXIT;\n\t\t\tcase '4':\n\t\t\t\targ = GOLD;\n\t\t\t\taddstr(\"How much gold to bestow ? \");\n\t\t\t\ttemp1 = inflt();\n\t\t\t\tif (temp1 > stat->gld || temp1 < 0)\n\t\t\t\t\t{\n\t\t\t\t\tmvaddstr(6,0,\"You don't have that !\\n\");\n\t\t\t\t\treturn;\n\t\t\t\t\t}\n\t\t\t\tstat->gld -= floor(temp1);\n\t\t\t\tcp = \"give gold to\";\n\t\t\t\tbreak;\n\t\t\tcase '5':\n\t\t\t\tfp = fopen(goldfile,\"r\");\n\t\t\t\tif (fread((char *) &temp1,sizeof(double),1,fp) != 1)\n\t\t\t\t        /*ignore*/;\n\t\t\t\tfclose(fp);\n\t\t\t\tmvprintw(6,0,\"You have collected %.0f in gold.\\n\",temp1);\n\t\t\t\tstat->gld += floor(temp1);\n\t\t\t\tfp = fopen(goldfile,\"w\");\n\t\t\t\ttemp1 = 0.0;\n\t\t\t\tfwrite((char *) &temp1,sizeof(double),1,fp);\n\t\t\t\tfclose(fp);\n\t\t\t\treturn;\n\t\t\tdefault:\n\t\t\t\treturn;\n\t\t\t}\n\t\t}\n\telse\t/* council of wise, valar, etc. */\n\t\t{\n\t\taddstr(\"1:Heal  \");\n\t\tif (stat->pal || su)\n\t\t\taddstr(\"2:Seek Grail  \");\n\t\tif (stat->typ == 99 || su)\n\t\t\taddstr(\"3:Throw Monster  4:Relocate  5:Bless  \");\n\t\tif (su)\n\t\t\taddstr(\"6:Vaporize  \");\n\t\tch = rgetch();\n\t\tif (!su && ch > '2' && stat->typ != 99)\n\t\t\t{\n\t\t\tillcmd();\n\t\t\treturn;\n\t\t\t}\n\t\tswitch (ch)\n\t\t\t{\n\t\t\tcase '1':\n\t\t\t\targ = HEAL;\n\t\t\t\tcp = \"heal\";\n\t\t\t\tbreak;\n\t\t\tcase '2':\n\t\t\t\tif (stat->pal)\n\t\t\t\t\t{\n\t\t\t\t\tfp = fopen(voidfile,\"r\");\n\t\t\t\t\tif (fread((char *) &vbuf,sizeof(vbuf),1,fp) != 1)\n\t\t\t\t\t        /*ignore*/;\n\t\t\t\t\tfclose(fp);\n\t\t\t\t\ttemp1 = hypot(stat->x - vbuf.x,stat->y - vbuf.y);\n\t\t\t\t\ttemp1 = floor(temp1 + roll(-temp1/10.0,temp1/5.0));\n\t\t\t\t\tmvprintw(6,0,\"The palantir says the Grail is about %.0f away.\\n\",temp1);\n\t\t\t\t\treturn;\n\t\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\tmvaddstr(6,0,\"You need a palantir to seek the Grail.\\n\");\n\t\t\t\t\treturn;\n\t\t\t\t\t}\n\t\t\tcase '3':\n\t\t\t\tmvaddstr(3,0,\"Which monster [0-99] ? \");\n\t\t\t\ttemp1 = inflt();\n\t\t\t\ttemp1 = max(0,min(99,temp1));\n\t\t\t\tcp = \"throw a monster at\";\n\t\t\t\targ = MONSTER;\n\t\t\t\tbreak;\n\t\t\tcase '4':\n\t\t\t\tmvaddstr(3,0,\"New X Y coordinates ? \");\n\t\t\t\tgetstring(aline,30);\n\t\t\t\tsscanf(aline,\"%lf %lf\",&temp1,&temp2);\n\t\t\t\tcp = \"relocate\";\n\t\t\t\targ = MOVED;\n\t\t\t\tbreak;\n\t\t\tcase '5':\n\t\t\t\targ = BLESS;\n\t\t\t\tcp = \"bless\";\n\t\t\t\tbreak;\n\t\t\tcase '6':\n\t\t\t\tif (su)\n\t\t\t\t\t{\n\t\t\t\t\tcp = \"vaporize\";\n\t\t\t\t\targ = VAPORIZED;\n\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\tdefault:\n\t\t\t\treturn;\n\t\t\t}\n\t\t}\n\tmvprintw(3,0,\"Who do you want to %s ? \",cp);\n\tgetstring(aline,21);\n\tstrunc(aline);\n\tif (strcmp(stat->name,aline))\n\t\t{\n\t\tfp = fopen(peoplefile,\"r\");\n\t\twhile (fread((char *) &sbuf,sizeof(sbuf),1,fp))\n\t\t\tif (strcmp(aline,sbuf.name))\n\t\t\t\t++loc;\n\t\t\telse\n\t\t\t\t{\n\t\t\t\tfclose(fp);\n\t\t\t\tif (sbuf.tampered)\n\t\t\t\t\t{\n\t\t\t\t\tmvaddstr(6,0,\"That person has something pending already.\\n\");\n\t\t\t\t\treturn;\n\t\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\tsbuf.tampered = arg;\n\t\t\t\t\tsbuf.scratch1 = floor(temp1);\n\t\t\t\t\tsbuf.scratch2 = floor(temp2);\n\t\t\t\t\tupdate(&sbuf,loc);\nEXIT:\t\t\t\t\tmvaddstr(6,0,\"It is done.\\n\");\n\t\t\t\t\treturn;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\tfclose(fp);\n\t\tmvaddstr(6,0,\"There is no one by that name.\\n\");\n\t\t}\n\telse\n\t\tmvaddstr(6,0,\"You may not do it to yourself!\\n\");\n}\n\nint\nallocvoid()\t\t\t\t/* find a space to put an energy void */\n{\n        FILE\t*fp;\n        register int\tloc = 0;\n        struct\tnrgvoid\tvbuf;\n\n\tfp = fopen(voidfile,\"r\");\n\twhile (fread((char *) &vbuf,sizeof(vbuf),1,fp))\n\t\tif (vbuf.active)\n\t\t\t++loc;\n\t\telse\n\t\t\t{\n\t\t\tfclose(fp);\n\t\t\treturn (loc);\n\t\t\t}\n\tfclose(fp);\n\treturn (loc);\n}\n\nvoid\nadjuststats(stat)\t\t\t\t/* make sure things are within limits, etc. */\n        register struct\tstats\t*stat;\n{\n        long\tltemp;\n        register int\ttemp;\n\n\tstat->x = floor(stat->x);\n\tstat->y = floor(stat->y);\n\tvalhala = (stat->typ == 99);\n\tthrone = (stat->x == 0.0 && stat->y == 0.0);\n\ttemp = abs(stat->x)/400;\n\tif (temp > 16)\n\t\ttemp = 0;\n\tif (stat->y == 0.0 && !throne && !valhala && temp == abs(stat->x)/400 && sgn(stat->x) == (int) pow(-1.0, (double) temp))\n\t\t{\n\t\tif (!wmhl)\n\t\t\tstat->wormhole = temp;\n\t\twmhl = TRUE;\n\t\t}\n\telse\n\t\twmhl = FALSE;\n\tspeed = stat->quk + stat->quks - spdcalc(stat->lvl,stat->gld,stat->gem);\n\tstrength = stat->str + stat->swd - strcalc(stat->str,stat->psn);\n\ttime(&ltemp);\n\tstat->age += ltemp - secs;\n\tsecs = ltemp;\n\tstat->quks = min(99,stat->quks);\n\tstat->man = min(stat->man,stat->lvl*15 + 5000);\n\tstat->chm = min(stat->chm,stat->lvl + 10);\n\tstat->typ = (stat->crn && stat->typ < 10) ? -abs(stat->typ) : abs(stat->typ);\n\tif (level(stat->exp) > stat->lvl)\n\t\tmovelvl(stat);\n\tstat->gld = floor(stat->gld) + 0.1;\n\tstat->gem = floor(stat->gem) + 0.1;\n\tif (stat->rng.type)\n\t\tstat->nrg = stat->mxn + stat->shd;\n\tif (stat->rng.type && stat->rng.duration <= 0)\t/* clean up rings */\n\t\tswitch (stat->rng.type)\n\t\t\t{\n\t\t\tcase DLBAD:\n\t\t\tcase NAZBAD:\n\t\t\t\tstat->rng.type = SPOILED;\n\t\t\t\tstat->rng.duration = roll(10,25);\n\t\t\t\tbreak;\n\t\t\tcase NAZREG:\n\t\t\t\tstat->rng.type = NONE;\n\t\t\t\tbreak;\n\t\t\tcase SPOILED:\n\t\t\t\tdeath(stat);\n\t\t\t\tbreak;\n\t\t\t}\t/* DLREG is ok, so do nothing with it */\n\tstat->nrg += (stat->mxn+stat->shd)/15+stat->lvl/3+2;\n\tstat->nrg = min(stat->nrg,stat->mxn + stat->shd);\n\tif (stat->age > stat->degen * 2500)\n\t\t{\n\t\t++stat->degen;\n\t\tif (stat->quk > 23)\n\t\t\t--stat->quk;\n\t\tstat->str *= 0.97;\n\t\tstat->brn *= 0.95;\n\t\tstat->mag *= 0.97;\n\t\tstat->mxn *= 0.95;\n\t\tif (stat->quks)\n\t\t\t--stat->quks;\n\t\tstat->swd *= 0.93;\n\t\tstat->shd *= 0.95;\n\t\t}\n}\n\nstatic void\ninterm(stat,who)\t\t\t\t/* interterminal battle routine */\n        register struct\tstats\t*stat;\n        int\twho;\n{\n#define\tMAXWAIT\t20\n#define\tBLOCK\tsizeof(struct stats)\n#define\tRAN\t1\n#define\tSTUCK\t2\n#define\tBLEWIT\t3\n#define\tKILLED\t4\n#define readfoe()\tfseek(fin,foeplace,0);  \\\n\t\t\tif (fread((char *) foe,BLOCK,1,fin) != 1) /*ignore*/\n#define updateme()\tfseek(fout,myplace,0);  \\\n\t\t\tfwrite((char *) stat,BLOCK,1,fout);  \\\n\t\t\tfflush(fout)\n\n        FILE\t*fin, *fout;\t/* pointers for input, output */\n        double\ttemp, foespeed, oldhits = 0.0, myhits;\n        struct\tstats\tsbuf;\n        register struct\tstats *foe;\n        register int\tloop, lines = 5;\n        int\tch;\n        long\tmyplace, foeplace;\n        int\toldtags;\n        bool\tluckout = FALSE;\n        char\tfoename[21];\n\n\tfghting = TRUE;\n\tmvaddstr(4,0,\"Preparing for battle!\\n\");\n\trefresh();\n\t\t/* set up variables, file, etc. */\n\tmyplace = fileloc * BLOCK;\n\tfoeplace = who * BLOCK;\n\tfin = fopen(peoplefile,\"r\");\n\tsetbuf(fin, (char *) NULL);\n\tfout = fopen(peoplefile,ACCESS);\n\tstat->status = INBATTLE;\n\tmyhits = stat->nrg;\n\tstat->tampered = oldtags = 1;\t/* this must be non-zero to prevent a king or valar from trashing it */\n\tstat->scratch1 = stat->scratch2 = 0.0;\n\tupdateme();\n\tfoe = &sbuf;\n\treadfoe();\n\tfoespeed = foe->quk + foe->quks - spdcalc(foe->lvl,foe->gld,foe->gem);\n\tif (abs(stat->lvl - foe->lvl) > 20)\t\t/* see if greatly mismatched */\n\t\t{\n\t\ttemp = ((double) (stat->lvl - foe->lvl))/((double) max(stat->lvl,foe->lvl));\n\t\tif (temp > 0.5)\t\t/* this one outweighs his/her foe */\n\t\t\tfoespeed *= 2.0;\n\t\telse if (temp < -0.5)\t/* foe outweighs this one */\n\t\t\tspeed *= 2.0;\n\t\t}\n\tif (stat->blind)\n\t\tstrcpy(foename,\"someone\");\n\telse\n\t\tstrcpy(foename,foe->name);\n\tmvprintw(3,0,\"You have encountered %s   Level: %d\\n\",foename,foe->lvl);\n\trefresh();\n\t\t/* now wait for foe to respond */\n\tfor (loop = 1.5*MAXWAIT; foe->status != INBATTLE && loop; --loop)\n\t\t{\n\t\treadfoe();\n\t\tsleep(1);\n\t\t}\n\tif (foe->status != INBATTLE)\n\t\t{\n\t\tmvprintw(4,0,\"%s is not responding.\\n\",foename);\n\t\tgoto LEAVE;\n\t\t}\n\n\t/* otherwise, everything is set to go */\n\tmove(4,0);\n\tclrtoeol();\n\t\t/* check to see who goes first */\n\tif (speed > foespeed)\n\t\tgoto HITFOE;\n\telse if (foespeed > speed)\n\t\tgoto WAIT;\n\telse if (stat->lvl > foe->lvl)\n\t\tgoto HITFOE;\n\telse if (foe->lvl > stat->lvl)\n\t\tgoto WAIT;\n\telse\t/* no one is faster */\n\t\t{\n\t\tprintw(\"You can't fight %s yet.\",foename);\n\t\tgoto LEAVE;\n\t\t}\n\n/* routine to hit, etc */\nHITFOE:\tprintstats(stat);\n\tmvprintw(1,26,\"%20.0f\",myhits);\n\tmvaddstr(4,0,\"1:Fight  2:Run Away!  3:Power Blast  \");\n\tif (luckout)\n\t\tclrtoeol();\n\telse\n\t\taddstr(\"4:Luckout  \");\n\tch = gch(stat->rng.type);\n\tmove(lines = 5,0);\n\tclrtobot();\n\tswitch (ch)\n\t\t{\n\t\tdefault:\t/* fight */\n\t\t\ttemp = roll(2,strength);\nHIT:\t\t\tmvprintw(lines++,0,\"You hit %s %.0f times!\",foename,temp);\n\t\t\tstat->sin += 0.5;\n\t\t\tstat->scratch1 += temp;\n\t\t\tstat->scratch2 = FALSE;\n\t\t\tbreak;\n\t\tcase '2':\t/* run away */\n\t\t\t--stat->scratch1;\t/* this value changes to indicate action */\n\t\t\tif (rnd() > 0.25)\n\t\t\t\t{\n\t\t\t\tmvaddstr(lines++,0,\"You got away!\");\n\t\t\t\tstat->scratch2 = RAN;\n\t\t\t\tgoto LEAVE;\n\t\t\t\t}\n\t\t\tmvprintw(lines++,0,\"%s is still after you!\",foename);\n\t\t\tstat->scratch2 = STUCK;\n\t\t\tbreak;\n\t\tcase '3':\t/* power blast */\n\t\t\ttemp = min(stat->man,stat->lvl*5);\n\t\t\tstat->man -= temp;\n\t\t\ttemp = (rnd() + 0.5) * temp * stat->mag * 0.2 + 2;\n\t\t\tmvprintw(lines++,0,\"You blasted %s !\",foename);\n\t\t\tgoto HIT;\n\t\tcase '4':\t/* luckout */\n\t\t\tif (luckout || rnd() > 0.1)\n\t\t\t\t{\n\t\t\t\tluckout = TRUE;\n\t\t\t\tmvaddstr(lines++,0,\"Not this time...\");\n\t\t\t\t--stat->scratch1;\n\t\t\t\tstat->scratch2 = BLEWIT;\n\t\t\t\t}\n\t\t\telse\n\t\t\t\t{\n\t\t\t\tmvaddstr(lines++,0,\"You just lucked out!\");\n\t\t\t\tstat->scratch1 = foe->nrg + 5;\n\t\t\t\t}\n\t\t\tbreak;\n\t\t}\n\trefresh();\n\tstat->scratch1 = floor(stat->scratch1);\t\t/* clean up any mess */\n\tif (stat->scratch1 > foe->nrg)\n\t\tstat->scratch2 = KILLED;\n\telse if (rnd() * speed < rnd() * foespeed)\n\t\t{\t\t/* foe's turn */\n\t\t++stat->tampered;\n\t\tupdateme();\n\t\tgoto WAIT;\n\t\t}\n\tupdateme();\n\n\tif (((int) stat->scratch2) == KILLED)\n\t\t{\n\t\tmvprintw(lines++,0,\"You killed %s!\",foename);\n\t\tstat->exp += foe->exp;\n\t\tstat->crn += (stat->lvl < 1000) ? foe->crn : 0;\n\t\tstat->amu += foe->amu;\n\t\tstat->chm += foe->chm;\n\t\tstat->gld += foe->gld;\n\t\tstat->gem += foe->gem;\n\t\tstat->swd = max(stat->swd,foe->swd);\n\t\tstat->shd = max(stat->shd,foe->shd);\n\t\tstat->quks = max(stat->quks,foe->quks);\n\t\tsleep(3);\t  /* give other person time to die */\n\t\tgoto LEAVE;\n\t\t}\n\tgoto HITFOE;\t/* otherwise, my turn again */\n\n/* routine to wait for foe to do something */\nWAIT:\tprintstats(stat);\n\tmvprintw(1,26,\"%20.0f\",myhits);\n\tmvaddstr(4,0,\"Waiting...\\n\");\n\trefresh();\n\tfor (loop = MAXWAIT; loop; --loop)\n\t\t{\n\t\treadfoe();\n\t\tif (foe->scratch1 != oldhits)\n\t\t\tswitch ((int) foe->scratch2)\n\t\t\t\t{\n\t\t\t\tcase RAN:\n\t\t\t\t\tmvprintw(lines++,0,\"%s ran away!\",foename);\n\t\t\t\t\tgoto LEAVE;\n\t\t\t\tcase STUCK:\n\t\t\t\t\tmvprintw(lines++,0,\"%s tried to run away.\",foename);\n\t\t\t\t\tgoto BOT;\n\t\t\t\tcase BLEWIT:\n\t\t\t\t\tmvprintw(lines++,0,\"%s tried to luckout!\",foename);\n\t\t\t\t\tgoto BOT;\n\t\t\t\tdefault:\n\t\t\t\t\ttemp = foe->scratch1 - oldhits;\n\t\t\t\t\tmvprintw(lines++,0,\"%s hit you %.0f times!\",foename,temp);\n\t\t\t\t\tmyhits -= temp;\n\t\t\t\t\tgoto BOT;\n\t\t\t\t}\n\t\tsleep(1);\n\t\t}\n\t/* timeout */\n\tmvaddstr(23,0,\"Timeout: waiting for response.  Do you want to wait ? \");\n\trefresh();\n\tch = getch();\n\tmove(23,0);\n\tclrtoeol();\n\tif (toupper(ch) == 'Y')\n\t\tgoto WAIT;\n\tgoto LEAVE;\n\n/* routine to decide what happens next */\nBOT:\trefresh();\n\tif (lines > 21)\n\t\t{\n\t\tpaws(lines);\n\t\tmove(lines = 5,0);\n\t\tclrtobot();\n\t\t}\n\tif (((int) foe->scratch2) == KILLED || myhits < 0.0)\n\t\t{\n\t\tmyhits = -2;\n\t\tgoto LEAVE;\t\t/* main will pick up death */\n\t\t}\n\toldhits = foe->scratch1;\n\tif (foe->tampered != oldtags)\n\t\t{\n\t\toldtags = foe->tampered;\n\t\tgoto HITFOE;\n\t\t}\n\tgoto WAIT;\n\n/* routine to clean up things and leave */\nLEAVE:\tupdateme();\n\tfclose(fin);\n\tfclose(fout);\n\tstat->x += roll(5,-10);\n\tstat->y += roll(5,-10);\n\tstat->nrg = myhits;\n\tstat->tampered = OFF;\n\tstat->status = PLAYING;\n\tchanged = TRUE;\n\tpaws(lines);\n\tmove(3,0);\n\tclrtobot();\n}\n\nvoid\ncheckinterm(stat)\t\t\t\t/* see if other person on same x,y */\n        register struct\tstats\t*stat;\n{\n        FILE\t*fp;\n        struct\tstats\tsbuf;\n        register int\tfoeloc = 0;\n\n\tusers = 0;\n\tfp = fopen(peoplefile,\"r\");\n\twhile (fread((char *) &sbuf,sizeof(sbuf),1,fp))\n\t\t{\n\t\tif (sbuf.status && (sbuf.status != CLOAKED || sbuf.typ != 99))\n\t\t\t{\n\t\t\t++users;\n\t\t\tif (stat->x == sbuf.x && stat->y == sbuf.y\n\t\t\t   && foeloc != fileloc && sbuf.typ != 99\n\t\t\t   && stat->typ !=99 && !stat->wormhole && !sbuf.wormhole)\n\t\t\t\t{\n\t\t\t\tfclose(fp);\n\t\t\t\tinterm(stat,foeloc);\n\t\t\t\treturn;\n\t\t\t\t}\n\t\t\t}\n\t\t++foeloc;\n\t\t}\n\tfclose(fp);\n}\n\nint\ngch(rngtyp)\t\t\t/* get a character from terminal, but check ring if crazy */\n        int\trngtyp;\n{\n\trefresh();\n\tif (abs(rngtyp) != SPOILED)\n\t\treturn (getch());\n\telse\n\t\t{\n\t\tgetch();\n\t\treturn (roll(0,5) + '0');\n\t\t}\n}\n\nint\nrngcalc(chartyp)\t\t\t\t/* pick a duration of a ring */\n        int\tchartyp;\n{\n        static\tint\trngtab[] = { 0, 10, 20, 13, 25, 40, 20};\n\n\tif (chartyp > 10)\n\t\tchartyp -= 10;\n\treturn (rngtab[chartyp - 1]);\n}\n\nvoid\ninterrupt(int sig)\t\t\t\t/* call when break key is hit */\n{\n        char\tline[81];\n        register int\tloop;\n        int\tx, y, ch;\n\n#ifdef USG3\n\tsignal(SIGINT,SIG_IGN);\n#endif\n#ifdef USG5\n\tsignal(SIGINT,SIG_IGN);\n#endif\n\tgetyx(stdscr,y,x);\n\tfor (loop = 79; loop >= 0; --loop)\t/* snarf line */\n\t\t{\n\t\tmove(4,loop);\n\t\tline[loop] = inch();\n\t\t}\n\tline[80] = '\\0';\n\tclrtoeol();\n\tif (fghting)\n\t\t{\n\t\tmove(4,0);\n\t\tclrtoeol();\n\t\taddstr(\"Quitting now will automatically kill your character.  Still want to ? \");\n\t\tch = rgetch();\n\t\tif (toupper(ch) == 'Y')\n\t\t\tlongjmp(mainenv,DIE);\n\t\t}\n\telse\n\t\t{\n\t\tmove(4,0);\n\t\tclrtoeol();\n\t\taddstr(\"Do you really want to quit ? \");\n\t\tch = rgetch();\n\t\tif (toupper(ch) == 'Y')\n\t\t\tlongjmp(mainenv,QUIT);\n\t\t}\n\tmvaddstr(4,0,line);\t/* return screen to previous state */\n\tmove(y,x);\n\trefresh();\n#ifdef USG3\n\tsignal(SIGINT,interrupt);\n#endif\n#ifdef USG5\n\tsignal(SIGINT,interrupt);\n#endif\n}\n\nint\nrgetch()\t\t/* refresh, then get a char. */\n{\n\trefresh();\n\treturn (getch());\n}\n\nvoid\npurge() \t/* remove old players */\n{\n        FILE\t*fin, *fout;\n        struct\tstats\tsbuf;\n        register int\tloc, today, temp;\n        long\tltime;\n\n\tloc = 0;\n\ttime(&ltime);\n\ttoday = localtime(&ltime)->tm_yday;\n\tfin = fopen(peoplefile,\"r\");\n\tfout = fopen(peoplefile,ACCESS);\n\twhile(fread((char *) &sbuf,sizeof(sbuf),1,fin))\n\t\t{\n\t\ttemp = today - sbuf.lastused;\n\t\tif (temp < 0)\n\t\t\ttemp += 365;\n\t\tif (temp > 9)\t\t/* ten days old --> delete */\n\t\t\t{\n\t\t\tinitchar(&sbuf);\n\t\t\tstrcpy(sbuf.name,\"<null>\");\n\t\t\tfseek(fout,(long) loc * sizeof(sbuf),0);\n\t\t\tfwrite((char *) &sbuf,sizeof(sbuf),1,fout);\n\t\t\t}\n\t\t++loc;\n\t\t}\n\tfclose(fin);\n\tfclose(fout);\n}\n"
  },
  {
    "path": "games/phantasia/main.c",
    "content": "/*\n * Phantasia 3.2 -- Interterminal fantasy game\n *\n * Edward A. Estes\n * AT&T Teletype Corp., September 4, 1984\n */\n\n/*\n * This is the program which drives the whole mess.  Hopefully, you will be\n * able to wade throught the garbage if you have to fix something.\n * several undocumented items exist.  The program checks uid and sets the\n * boolean flag 'su' (super user) if the person is allowed special powers.\n * The 'su' may execute any of the valar/council options.  Also,\n * a 'vaporize' option exists to kill anybody at will.  The 'su' can select\n * character type 7, which starts out with the maximum possible in each\n * category.  (The resulting character is an experimento.)  The 'su' may\n * also change the stats of other characters with the -x option.\n */\n\n/*\n * The program allocates as much file space as it needs to store characters,\n * so the possibility exists for the character file to grow without bound.\n * The file is purged upon normal entry to try to avoid that problem.\n * A similar problem exists for energy voids.  To alleviate the problem here,\n * the void file is cleared with every new king.\n */\n\n/*\n * The support functions are split between various files with no apparent\n * order.  Use of 'ctags' is recommended to find a particular function.\n */\n\n/*\n * Put one line of text into the file 'motd' for announcements, etc.\n */\n\n/*\n * If ENEMY is defined, a list of restricted login names is checked\n * in the file 'enemy'.  These names are listed, one per line, with\n * no trailing blanks.\n */\n\n#include \"phant.h\"\n\ndouble\tstrength, speed;\nbool\tbeyond, marsh, throne, valhala, changed, fghting, su, wmhl;\nint\tfileloc, users;\njmp_buf\tfightenv, mainenv;\nlong\tsecs;\n/*\n * worm hole map -- This table is carefully set up so that one can always\n * return the way he/she came by inverting the initial path.\n */\nstruct\tworm_hole\tw_h[] =\n\t{\n\t0,0,0,0,\t35,22,2,0,\t2,2,0,1,\t59,34,64,0,\n\t54,47,0,60,\t50,62,0,56,\t19,31,25,0,\t0,35,41,41,\n\t0,46,40,23,\t24,0,29,30,\t44,57,56,0,\t0,44,39,40,\n\t61,41,0,42,\t32,0,17,18,\t57,0,63,64,\t0,33,26,34,\n\t48,0,54,55,\t28,23,22,13,\t63,25,13,19,\t34,6,18,20,\n\t27,26,19,21,\t15,27,20,27,\t1,28,34,17,\t17,29,8,24,\n\t29,9,23,25,\t18,30,24,6,\t20,32,27,15,\t21,20,21,26,\n\t22,17,46,29,\t23,24,28,9,\t25,38,9,31,\t6,39,30,32,\n\t26,13,31,33,\t15,40,32,35,\t3,19,15,22,\t7,1,33,36,\n\t37,37,35,37,\t36,36,36,38,\t30,42,37,39,\t31,43,38,11,\n\t33,45,11,8,\t12,48,7,7,\t38,49,12,43,\t39,51,42,44,\n\t11,10,43,45,\t40,52,44,46,\t8,53,45,28,\t4,54,51,48,\n\t41,16,47,49,\t42,55,48,50,\t62,5,49,51,\t43,56,50,47,\n\t45,58,53,53,\t46,59,52,52,\t47,4,55,16,\t49,61,16,54,\n\t51,63,5,10,\t10,14,59,58,\t52,64,57,59,\t53,3,58,57,\n\t60,60,4,61,\t55,12,60,62,\t5,50,61,63,\t56,18,62,14,\n\t58,33,14,3\n\t};\n\nint\nmain(argc,argv)\t\t\t\t/* Phantasia main routine */\n        int\targc;\n        char\t*argv[];\n{\n        struct\tstats\tcharac;\n        char\taline[200], *login = NULL;\n        double\tx = 0.0, y = 0.0;\n        int\tch, ch2;\n        register int\tloop, temp;\n        FILE\t*fp;\n        bool\tshrt = FALSE, examine = FALSE, header = FALSE;\n\n        login = getlogin();\n\tif (! login)\n\t\tlogin = getpwuid(getuid())->pw_name;\n#ifdef ENEMY\n\t/* check hit list of restricted accounts */\n\tif ((fp = fopen(enemyfile, \"r\")) != NULL)\n\t\t{\n\t\tchar\tenemy[20];\n\n\t\twhile (fscanf(fp, \"%s\", enemy) != EOF)\n\t\t\tif (!strcmp(login,enemy))\n\t\t\t\t{\n\t\t\t\tprintf (\"The Phantasia privileges for the account \\\"%s\\\" have been revoked.\\n\", login);\n\t\t\t\tprintf (\"Mail comments to %s.\\n\", WIZARD);\n\t\t\t\texit (0);\n\t\t\t\t}\n\t\tfclose (fp);\n\t\t}\n#endif\n\tsetbuf(stdin, (char *) NULL);\t/* this may or may not be necessary */\n\tsu = (getuid() == UID);\n\tfghting = FALSE;\n\tusers = 0;\n\tif (argc > 1 && (*++argv)[0] == '-')\n\t\tswitch ((*argv)[1])\n\t\t\t{\n\t\t\tcase 'h':\t\t/* help */\n\t\t\t\tprinthelp();\n\t\t\t\texit(0);\n\t\t\t\t/*NOTREACHED*/\n\t\t\tcase 's':\t\t/* short */\n\t\t\t\tshrt = TRUE;\n\t\t\t\tbreak;\n\t\t\tcase 'x':\t\t/* examine */\n\t\t\t\texamine = TRUE;\n\t\t\t\tbreak;\n\t\t\tcase 'H':\t\t/* Header */\n\t\t\t\theader = TRUE;\n\t\t\t\tbreak;\n\t\t\tcase 'm':\t\t/* monsters */\n\t\t\t\tprintmonster();\n\t\t\t\texit(0);\n\t\t\t\t/*NOTREACHED*/\n\t\t\tcase 'a':\t\t/* all users */\n\t\t\t\tshowusers();\n\t\t\t\texit(0);\n\t\t\t\t/*NOTREACHED*/\n\t\t\tcase 'p':\t\t/* purge old players */\n\t\t\t\tpurge();\n\t\t\t\texit(0);\n\t\t\t\t/*NOTREACHED*/\n\t\t\t}\n\tif (!isatty(0))\t/* don't let non-tty's play */\n\t\texit(0);\n\tinit1();\t/* set up for screen stuff */\n\tif (examine)\n\t\t{\n\t\tcstat();\n\t\texit1();\n\t\t/*NOTREACHED*/\n\t\t}\n\tif (!shrt)\n\t\t{\n\t\ttitlestuff();\n\t\tpurge();\t/* clean up old characters */\n\t\t}\n\tif (header)\n\t\t{\n\t\texit1();\n\t\t/*NOTREACHED*/\n\t\t}\n#ifdef OK_TO_PLAY\n\tif (!ok_to_play())\n\t\t{\n\t\tmvaddstr(23,27,\"Sorry, you can't play now.\\n\");\n\t\texit1();\n\t\t/*NOTREACHED*/\n\t\t}\n#endif\n\tmvaddstr(23,24,\"Do you have a character to run? \");\n\tch = rgetch();\n\tif (toupper(ch) == 'Y')\n\t\tfileloc = findchar(&charac);\n\telse\n\t\t{\n\t\tinitchar(&charac);\n\t\tclear();\n\t\tmvaddstr(5,21,\"Which type of character do you want:\");\n\t\tmvaddstr(10,4,\"1:Magic User  2:Fighter  3:Elf  4:Dwarf  5:Halfling  6:Experimento  ? \");\n\t\tch = rgetch();\n\t\tdo\n\t\t\t{\n\t\t\tgenchar(&charac,ch);\n\t\t\tmvprintw(15,14,\"Strength:  %2.0f  Manna      : %3.0f  Quickness   :  %2d\",\n\t\t\t\tcharac.str,charac.man,charac.quk);\n\t\t\tmvprintw(16,14,\"Brains  :  %2.0f  Magic Level:  %2.0f  Energy Level:  %2.0f\",\n\t\t\t\tcharac.brn,charac.mag,charac.nrg);\n\t\t\tif (charac.typ != 6)\n\t\t\t\t{\n\t\t\t\tmvaddstr(17,14,\"Type '1' to keep >\");\n\t\t\t\tch2 = rgetch();\n\t\t\t\t}\n\t\t\telse\n\t\t\t\tbreak;\n\t\t\t}\n\t\twhile (ch2 != '1');\n\t\tif (charac.typ == 6)\n\t\t\t{\n\t\t\tmvaddstr(19,0,\"Enter the X Y coordinates of your experimento ? \");\n\t\t\tgetstring(aline,80);\n\t\t\tsscanf(aline,\"%lf %lf\",&x,&y);\n\t\t\tcharac.x = (abs(x) > 1.2e+6) ? sgn(x)*1.2e+6 : floor(x);\n\t\t\tcharac.y = (abs(y) > 1.2e+6) ? sgn(y)*1.2e+6 : floor(y);\n\t\t\t}\n\t\tdo\n\t\t\t{\n\t\t\tmvaddstr(20,0,\"Give your character a name [up to 20 characters] ?  \");\n\t\t\tgetstring(aline,80);\n\t\t\tstrncpy(charac.name,aline,20);\n\t\t\tcharac.name[20] = '\\0';\n\t\t\t}\n\t\twhile (findname(charac.name));\n\t\tputchar('\\n');\n\t\tfflush(stdout);\n\t\tnocrmode();\n\t\tdo\n\t\t\t{\n\t\t\tstrcpy(charac.pswd,getpass(\"Give your character a password [up to 8 characters] ? \"));\n\t\t\tputchar('\\n');\n\t\t\tstrcpy(aline,getpass(\"One more time to verify ? \"));\n\t\t\t}\n\t\twhile (strcmp(charac.pswd,aline));\n\t\tfileloc = findspace();\n\t\t}\n\tcrmode();\n\tif (charac.status)\n\t\t{\n\t\tclear();\n\t\taddstr(\"Your character did not exit normally last time.\\n\");\n\t\taddstr(\"If you think you have good cause to have you character saved,\\n\");\n\t\tprintw(\"you may quit and mail your reason to '%s'.\\n\",WIZARD);\n\t\taddstr(\"Do you want to quit ? \");\n\t\tch = rgetch();\n\t\tif (toupper(ch) == 'Y')\n\t\t\t{\n\t\t\tcharac.quk = -100;\n\t\t\tleave(&charac);\n\t\t\t/*NOTREACHED*/\n\t\t\t}\n\t\tdeath(&charac);\n\t\t}\n\tcharac.status = PLAYING;\n\tstrcpy(charac.login,login);\n\ttime(&secs);\n\tcharac.lastused = localtime(&secs)->tm_yday;\n\tupdate(&charac,fileloc);\n\tclear();\n\tsignal(SIGINT,interrupt);\n\n/* all set for now */\n\nTOP:\tswitch (setjmp(mainenv))\n\t\t{\n\t\tcase QUIT:\n\t\t\tsignal(SIGINT,interrupt);\n\t\t\tleave(&charac);\n\t\t\t/*NOTREACHED*/\n\t\tcase DIE:\n\t\t\tsignal(SIGINT,interrupt);\n\t\t\tdeath(&charac);\n\t\t\tbreak;\n\t\t}\n#ifdef OK_TO_PLAY\n\tif (!ok_to_play())\n\t\t{\n\t\tmvaddstr(6,0,\"Whoops!  Can't play now.\\n\");\n\t\tleave(&charac);\n\t\t/*NOTREACHED*/\n\t\t}\n#endif\n\tfghting = FALSE;\n\tadjuststats(&charac);\n\tif (throne && !charac.crn && (charac.typ < 10 || charac.typ > 20))\n\t\t{\n\t\tmvaddstr(6,0,\"You're not allowed in the Lord's Chamber without a crown.\\n\");\n\t\tchanged = TRUE;\n\t\tcharac.x = charac.y = 10;\n\t\t}\n\tif (charac.status != CLOAKED && abs(charac.x) == abs(charac.y)\n\t\t && floor(sqrt(fabs(charac.x/100.0))) == sqrt(fabs(charac.x/100.0)) && !throne)\n\t\t{\n\t\ttrade(&charac);\n\t\tclear();\n\t\t}\n\tchecktampered(&charac);\n\tcheckinterm(&charac);\n\tif (charac.nrg < 0 || (charac.lvl >= 10000 && charac.typ != 99))\n\t\tdeath(&charac);\n\tneatstuff(&charac);\n\tif (changed)\n\t\t{\n\t\tupdate(&charac,fileloc);\n\t\tchanged = FALSE;\n\t\tgoto TOP;\n\t\t}\n\tmove(5,0);\n\tclrtoeol();\n\tfp = fopen(messfile,\"r\");\n\tif (fgets(aline,160,fp))\n\t\taddstr(aline);\n\tfclose(fp);\n\tprintstats(&charac);\n\tmove(3,0);\n\tclrtoeol();\n\tif (!wmhl)\n\t\t{\n\t\tif (throne)\n\t\t\tkingstuff(&charac);\n\t\taddstr(\"1:Move  2:Players  3:Talk  4:Stats  5:Quit  \");\n\t\tif (charac.lvl >= 5 && charac.mag >= 15)\n\t\t\taddstr(\"6:Cloak  \");\n\t\tif (charac.lvl >= 10 && charac.mag >= 25)\n\t\t\taddstr(\"7:Teleport  \");\n\t\tif (charac.typ > 20)\n\t\t\taddstr(\"8:Intervention\");\n\t\tch = gch(charac.rng.type);\n\t\tclrtoeol();\n\t\tmove(6,0);\n\t\tclrtobot();\n\t\tif (charac.typ == 99 && (ch == '1' || ch == '7'))\n\t\t\tch = ' ';\n\t\tswitch (ch2 = toupper(ch))\n\t\t\t{\n\t\t\tcase 'N':\n\t\t\t\tcharac.y += maxmove;\n\t\t\t\tbreak;\n\t\t\tcase 'S':\n\t\t\t\tcharac.y -= maxmove;\n\t\t\t\tbreak;\n\t\t\tcase 'E':\n\t\t\t\tcharac.x += maxmove;\n\t\t\t\tbreak;\n\t\t\tcase 'W':\n\t\t\t\tcharac.x -= maxmove;\n\t\t\t\tbreak;\n\t\t\tdefault:\t/* rest */\n\t\t\t\tif (charac.status == CLOAKED)\n\t\t\t\t\tif (charac.man > 3.0)\n\t\t\t\t\t\tcharac.man -= 3;\n\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\tcharac.status = PLAYING;\n\t\t\t\t\t\tchanged = TRUE;\n\t\t\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\tcharac.man += circ(charac.x,charac.y)/3+0.5;\n\t\t\t\t\tcharac.man += charac.lvl/5+0.5;\n\t\t\t\t\t}\n\t\t\t\trndattack();\n\t\t\t\tbreak;\n\t\t\tcase '1':\t/* move */\n\t\t\t\tfor (loop = 3; loop; --loop)\n\t\t\t\t\t{\n\t\t\t\t\tmvaddstr(5,0,\"X Y Coordinates ? \");\n\t\t\t\t\tgetstring(aline,80);\n\t\t\t\t\tif (sscanf(aline,\"%lf %lf\",&x,&y) < 2)\n\t\t\t\t\t\t;\n\t\t\t\t\telse\n\t\t\t\t\t\tif (hypot((double) charac.x - x, (double) charac.y - y) > maxmove)\n\t\t\t\t\t\t\tillmove();\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\tcharac.x = x;\n\t\t\t\t\t\t\tcharac.y = y;\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase '2':\t/* players */\n\t\t\t\tprintplayers(&charac);\n\t\t\t\tbreak;\n\t\t\tcase '3':\t/* message */\n\t\t\t\ttalk(charac.name);\n\t\t\t\tbreak;\n\t\t\tcase '4':\t/* stats */\n\t\t\t\tshowall(&charac);\n\t\t\t\tbreak;\n\t\t\tcase '5':\t/* good-bye */\n\t\t\t\tleave(&charac);\n\t\t\t\t/*NOTREACHED*/\n\t\t\tcase '6':\t/* cloak */\n\t\t\t\tif (charac.lvl < 5 || charac.mag < 15)\n\t\t\t\t\tillcmd();\n\t\t\t\telse if (charac.status == CLOAKED)\n\t\t\t\t\tcharac.status = PLAYING;\n\t\t\t\telse if (charac.man < 35)\n\t\t\t\t\t{\n\t\t\t\t\tmvaddstr(6,0,\"No power left.\\n\");\n\t\t\t\t\trefresh();\n\t\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\tchanged = TRUE;\n\t\t\t\t\tcharac.man -= 35;\n\t\t\t\t\tcharac.status = CLOAKED;\n\t\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase '7':\t/* teleport */\n\t\t\t\tif (charac.lvl < 10 || charac.mag < 25)\n\t\t\t\t\tillcmd();\n\t\t\t\telse\n\t\t\t\t\tfor (loop = 3; loop; --loop)\n\t\t\t\t\t\t{\n\t\t\t\t\t\tmvaddstr(5,0,\"X Y Coordinates ? \");\n\t\t\t\t\t\tgetstring(aline,80);\n\t\t\t\t\t\tif (sscanf(aline,\"%lf %lf\",&x,&y) == 2)\n\t\t\t\t\t\t\tif ((temp = hypot(charac.x-x,charac.y-y))\n\t\t\t\t\t\t\t\t\t> (charac.lvl+charac.mag)*5+((charac.typ > 20) ? 1e+6 : 0)\n\t\t\t\t\t\t\t\t\t&& !throne)\n\t\t\t\t\t\t\t\tillmove();\n\t\t\t\t\t\t\telse if ((temp = (temp/75+1)*20) > charac.man && !throne)\n\t\t\t\t\t\t\t\tmvaddstr(6,0,\"Not enough power for that distance.\\n\");\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tcharac.x = x;\n\t\t\t\t\t\t\t\tcharac.y = y;\n\t\t\t\t\t\t\t\tif (!throne)\n\t\t\t\t\t\t\t\t\tcharac.man -= temp;\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase '9':\t/* monster */\n\t\t\t\tif (throne)\n\t\t\t\t\tmvaddstr(6,0,\"No monsters in the chamber!\\n\");\n\t\t\t\telse if (charac.typ != 99)\n\t\t\t\t\t{\n\t\t\t\t\tcharac.status = PLAYING;\n\t\t\t\t\tchanged = TRUE;\n\t\t\t\t\tcharac.sin += 1e-6;\n\t\t\t\t\tfight(&charac,-1);\n\t\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase '0':\t/* decree */\n\t\t\t\tif (su || charac.typ > 10 && charac.typ < 20 && throne)\n\t\t\t\t\tdecree(&charac);\n\t\t\t\telse\n\t\t\t\t\tillcmd();\n\t\t\t\tbreak;\n\t\t\tcase '8':\t/* intervention */\n\t\t\t\tif (su || charac.typ > 20)\n\t\t\t\t\tvalarstuff(&charac);\n\t\t\t\telse\n\t\t\t\t\tillcmd();\n\t\t\t\tbreak;\n\t\t\tcase '\\014':\t/* redo screen */\n\t\t\t\tclear();\n\t\t\t}\n\t\tif (ch2 == 'E' || ch2 == 'W' || ch2 == 'N' || ch2 == 'S'\n\t\t\t|| ch2 == '1' || ch2 == '7')\n\t\t\t{\n\t\t\tcheckmov(&charac);\n\t\t\trndattack();\n\t\t\tchanged = TRUE;\n\t\t\t}\n\t\t}\n\telse\n\t\t{\n\t\taddstr(\"F:Forward  B:Back  R:Right  L:Left  Q:Quit  T:Talk  P:Players  S:Stats  \");\n\t\tch = rgetch();\n\t\tmove(6,0);\n\t\tclrtobot();\n\t\tswitch (toupper(ch))\n\t\t\t{\n\t\t\tdefault:\n\t\t\t\tif (charac.status == CLOAKED)\n\t\t\t\t\tif (charac.man > 3.0)\n\t\t\t\t\t\tcharac.man -= 3;\n\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\tcharac.status = PLAYING;\n\t\t\t\t\t\tchanged = TRUE;\n\t\t\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t\tcharac.man += charac.lvl/5+0.5;\n\t\t\t\tbreak;\n\t\t\tcase 'F':\n\t\t\t\ttemp = (int) w_h[charac.wormhole].f;\n\t\t\t\tgoto CHKMOVE;\n\t\t\tcase 'B':\n\t\t\t\ttemp = (int) w_h[charac.wormhole].b;\n\t\t\t\tgoto CHKMOVE;\n\t\t\tcase 'R':\n\t\t\t\ttemp = (int) w_h[charac.wormhole].r;\n\t\t\t\tgoto CHKMOVE;\n\t\t\tcase 'L':\n\t\t\t\ttemp = (int) w_h[charac.wormhole].l;\n\t\t\t\tgoto CHKMOVE;\n\t\t\tcase 'Q':\n\t\t\t\tleave(&charac);\n\t\t\t\t/*NOTREACHED*/\n\t\t\tcase 'T':\n\t\t\t\ttalk(charac.name);\n\t\t\t\tbreak;\n\t\t\tcase 'P':\n\t\t\t\tprintplayers(&charac);\n\t\t\t\tbreak;\n\t\t\tcase 'S':\n\t\t\t\tshowall(&charac);\n\t\t\t\tbreak;\n\t\t\tcase '\\014':\t/* redo screen */\n\t\t\t\tclear();\n\t\t\t}\n\t\tgoto TOP;\nCHKMOVE:\tif (!temp)\n\t\t\t\t{\n\t\t\t\tcharac.y = 0.0;\n\t\t\t\tcharac.x = pow(-1.0,(double) charac.wormhole) * charac.wormhole * 400 - 1.0;\n\t\t\t\tcharac.wormhole = 0;\n\t\t\t\tchanged = TRUE;\n\t\t\t\t}\n\t\t\telse\n\t\t\t\tcharac.wormhole = temp;\n\t\t}\n\tgoto TOP;\n}\n\n/*\n * This function is provided to allow one to restrict access to the game.\n * Tailor this routine as appropriate.\n */\n\n#ifdef\tOK_TO_PLAY\n#include <sys/types.h>\n#include <utmp.h>\t/* used for counting users on system */\n\nbool\tok_to_play()\t\t/* return FALSE if playing is not allowed at this time */\n{\n#define\tMAXUSERS\t8\t/* max. number of people on system */\n        register struct\ttm\t*tp;\n        register int\tnumusers = 0;\n        FILE\t*fp;\n        long\tnow;\n        struct\tutmp\tubuf;\n\n\tif (su)\n\t\treturn (TRUE);\n\t/* check time of day */\n\ttime(&now);\n\tif (((tp = localtime(&now))->tm_hour > 8 && tp->tm_hour < 12)\t/* 8-noon */\n\t\t|| (tp->tm_hour > 13 && tp->tm_hour < 16))\t\t/* 1-4 pm */\n\t\treturn (FALSE);\n\t/* check # of users */\n\tfp = fopen(_PATH_UTMP,\"r\");\n\twhile (fread((char *) &ubuf,sizeof(ubuf),1,fp))\n#ifdef\tUSG5\n\t\tif (ubuf.ut_type == USER_PROCESS)\n#else\n\tif (*ubuf.ut_name)\n#endif\n\t\t\t++numusers;\n\tfclose(fp);\n\tif (numusers > MAXUSERS)\n\t\treturn (FALSE);\n\treturn (TRUE);\n}\n#endif\n"
  },
  {
    "path": "games/phantasia/monsters",
    "content": "a Water Leaper          12      14      16      24      59      0       0       62\na Leech                 4       19      29      30      66      0       0       73\na Urisk                 13      30      15      46      127     1       0       3\nShellycoat              28      21      18      63      226     2       0       0\na Naiad                 21      62      27      58      378     2       0       11\na Nixie                 22      58      28      108     604     3       0       6\na Glaistig              21      106     25      127     1002    3       0       0\na Mermaid               18      116     22      108     809     3       0       0\na Merman                24      115     23      109     808     4       0       0\na Siren                 22      128     31      89      915     4       0       24\na Lamprey               14      67      33      156     1562    4       15      37\na Kopoacinth            26      36      26      206     2006    5       0       20\na Kelpie                61      25      24      223     4025    5       0       0\nan Aspidchelone         114     104     19      898     10041   7       0       2\nan Idiot                13      14      16      28      49      0       0       0\nsome Green Slime        1       5       45      100     57      0       0       26\na Pixie                 11      29      23      26      64      0       0       32\na Serpent               10      18      25      25      79      0       0       10\na Cluricaun             12      27      20      30      81      0       14      5\nan Imp                  22      30      14      40      92      0       0       1\na Centipede             3       8       18      15      33      0       0       61\na Beetle                2       11      21      26      44      0       0       48\na Fir Darrig            18      22      17      35      107     0       14      1\nModnar                  15      23      20      40      101     7       2       12\na Gnome                 7       45      26      23      111     0       0       21\na Sprite                9       37      25      31      132     1       0       43\na Mimic                 11      55      29      47      213     1       3       2\na Kobold                13      10      14      21      121     1       12      68\na Spider                6       11      28      28      124     1       0       57\nan Uldra                14      37      21      32      93      1       0       6\na Gnoll                 20      25      15      40      166     1       0       61\na Bogie                 23      28      19      57      189     1       0       57\na Fachan                9       40      15      45      139     1       14      10\na Moron                 3       1       10      10      28      0       0       100\nan Orc                  25      13      16      26      141     1       0       92\na Ghillie Dhu           12      16      13      28      104     2       14      2\na Bogle                 19      15      16      35      157     2       14      15\na Shrieker              2       62      27      9       213     2       16      0\na Carrion Crawler       12      20      20      65      142     2       0       42\na Trow                  15      17      23      51      136     2       0       36\na Warg                  20      10      17      45      152     2       0       88\na Stirge                2       6       35      25      153     2       0       95\na Crebain               5       11      31      31      82      2       0       81\na Killmoulis            30      19      8       75      175     3       14      22\na Hob-goblin            35      20      15      72      246     3       0       18\na Unicorn               27      57      27      57      627     3       1       0\na Fenoderee             16      6       21      65      222     3       0       42\nan Ogre                 42      14      16      115     409     3       0       19\na Dodo                  62      12      11      76      563     3       0       3\na Hydra                 14      27      33      99      599     3       0       27\na Hamadryad             23      47      26      62      426     3       0       12\na Bwca                  21      17      19      55      387     3       14      1\nan Owlbear              35      16      18      100     623     4       0       22\nBlack Annis             37      52      15      65      786     4       0       2\na Jello Blob            45      23      12      114     1191    4       0       0\na Wichtlein             13      40      25      61      800     4       0       8\na Cocodrill             39      28      24      206     1438    4       0       38\na Troll                 75      12      20      185     1013    4       24      29\na Bonnacon              89      26      9       255     1661    4       17      14\na Gargoyle              22      21      29      200     1753    5       0       7\na Chaladrius            8       49      37      172     1929    5       0       20\na Gwyllion              27      73      20      65      1888    5       0       4\na Cinomulgus            23      2       10      199     263     5       0       18\na Peridexion            26      32      24      98      1300    5       0       2\nSmeagol                 41      33      27      373     2487    5       18      0\na Wraith                52      102     22      200     3112    5       25      13\na Snotgurgle            143     19      26      525     4752    6       0       3\na Phooka                42      63      21      300     4125    5       0       12\na Vortex                101     30      31      500     6992    6       9       4\nShelob                  147     64      28      628     5003    7       13      0\na Thaumaturgist         35      200     23      400     7628    6       7       0\nSmaug                   251     76      26      1022    9877    7       0       0\na Cold-drake            301     102     24      1222    10888   7       0       0\na Red Dragon            342     141     23      1299    11649   8       0       0\nScatha the Worm         406     208     20      1790    11999   8       0       0\nTiamat                  506     381     29      2000    13001   9       11      0\na Bandersnatch          105     98      22      450     7981    6       0       3\na Harpy                 103     49      24      263     7582    6       0       2\na Tigris                182     38      17      809     7777    6       0       3\na Gryphon               201     45      19      813     8888    7       0       1\na Coblynau              205     46      18      585     8333    6       0       2\na Chimaera              173     109     28      947     12006   7       0       0\na Jack-in-Irons         222     36      12      1000    9119    7       0       0\nSaruman                 55      373     17      1500    17101   11      6       0\na Balrog                500     100     25      705     8103    7       8       0\nArgus                   201     87      14      1500    10010   8       0       0\na Titan                 302     1483    12      1625    11011   8       0       0\nCacus                   256     43      19      1750    12012   8       0       0\nBegion                  403     154     10      1875    13013   8       0       0\nGrendel                 197     262     23      2000    14014   8       0       0\na Nazgul                250     251     26      1011    9988    12      10      9\na Succubus              186     1049    27      2007    19984   9       19      0\nRed Cap                 143     50      35      1965    23456   9       0       0\na Nuckelavee            300     75      20      2185    11111   8       0       0\nCerberus                236     96      29      2600    25862   9       20      0\na Jabberwock            185     136     25      2265    23256   9       22      0\nUngoliant               399     2398    37      2784    27849   10      21      0\nLeanan-Sidhe            486     5432    46      3000    30004   9       5       0\nthe Dark Lord           9999    9999    31      19999   30005   13      4       0\n"
  },
  {
    "path": "games/phantasia/phant.h",
    "content": "/*\n * phant.h\tInclude file for Phantasia\n */\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n#include <setjmp.h>\n#include <curses.h>\n#include <time.h>\n#include <pwd.h>\n#include <signal.h>\n#include <math.h>\n\n/* ring constants */\n#define NONE\t0\n#define NAZBAD\t1\n#define NAZREG\t2\n#define DLREG\t3\n#define DLBAD\t4\n#define SPOILED 5\n\n/* some functions and pseudo-functions */\n#define toupper(CH)\t((CH) > 96 ? (CH) ^ 32 : (CH))\t/* may be upper or lower */\n#define tolower(CH)\t((CH) | 32)\t\t\t/* must be upper */\n#define rnd()\t\t(((double) rand()) / RAND)\n#define roll(BASE,INTERVAL)\tfloor((BASE) + (INTERVAL) * rnd())\n#define sgn(x)\t(-(x < 0) + (x > 0))\n#define abs(x)\t((x) < 0 ? -(x) : (x))\n#define circ(x,y)\tfloor(sqrt((double) ((x) * (x) + (y) * (y))) / 125 + 1)\n#define max(A,B)\t((A) > (B) ? (A) : (B))\n#define min(A,B)\t((A) < (B) ? (A) : (B))\n#define valarstuff(ARG)\tdecree(ARG)\n#define illcmd()\tmvaddstr(6,0,\"Illegal command.\\n\")\n#define maxmove \tfloor(charac.lvl * 1.5 + 1)\n#define illmove()\tmvaddstr(6,0,\"Too far.\\n\")\n#define rndattack()\tif (rnd() < 0.2 && charac.status == PLAYING && !throne) \\\n\t\t\t\tfight(&charac,-1)\n#define strcalc(STR,SICK)\tmax(0,min(0.9 * STR, SICK * STR/20))\n#define spdcalc(LVL,GLD,GEM)\tmax(0,((GLD + GEM/2) - 1000)/200.0 - LVL)\n#define illspell()\tmvaddstr(6,0,\"Illegal spell.\\n\")\n#define nomanna()\tmvaddstr(6,0,\"Not enough manna for that spell.\\n\")\n#define somebetter()\taddstr(\"But you already have something better.\\n\")\n\n/* status constants */\n#define OFF\t0\n#define PLAYING 1\n#define CLOAKED 2\n#define INBATTLE\t3\n#define DIE\t4\n#define QUIT\t5\n\n/* tampered constants */\n#define NRGVOID 1\n#define GRAIL\t2\n#define TRANSPORT\t3\n#define GOLD\t4\n#define CURSED\t5\n#define MONSTER 6\n#define BLESS\t7\n#define MOVED\t8\n#define HEAL\t9\n#define VAPORIZED\t10\n#define STOLEN\t11\n\n/* structure definitions */\nstruct\tstats\t\t/* player stats */\n\t{\n\tchar\tname[21];\t/* name */\n\tchar\tpswd[9];\t/* password */\n\tchar\tlogin[10];\t/* login */\n\tdouble\tx;\t\t/* x coord */\n\tdouble\ty;\t\t/* y coord */\n\tdouble\texp;\t\t/* experience */\n\tint\tlvl;\t\t/* level */\n\tshort\tquk;\t\t/* quick */\n\tdouble\tstr;\t\t/* strength */\n\tdouble\tsin;\t\t/* sin */\n\tdouble\tman;\t\t/* manna */\n\tdouble\tgld;\t\t/* gold */\n\tdouble\tnrg;\t\t/* energy */\n\tdouble\tmxn;\t\t/* max. energy */\n\tdouble\tmag;\t\t/* magic level */\n\tdouble\tbrn;\t\t/* brains */\n\tshort\tcrn;\t\t/* crowns */\n\tstruct\n\t\t{\n\t\tshort\ttype;\n\t\tshort\tduration;\n\t\t}\trng;\t/* ring stuff */\n\tbool\tpal;\t\t/* palantir */\n\tdouble\tpsn;\t\t/* poison */\n\tshort\thw;\t\t/* holy water */\n\tshort\tamu;\t\t/* amulets */\n\tbool\tbls;\t\t/* blessing */\n\tshort\tchm;\t\t/* charms */\n\tdouble\tgem;\t\t/* gems */\n\tshort\tquks;\t\t/* quicksilver */\n\tdouble\tswd;\t\t/* sword */\n\tdouble\tshd;\t\t/* shield */\n\tshort\ttyp;\t\t/* character type */\n\tbool\tvrg;\t\t/* virgin */\n\tshort\tlastused;\t/* day of year last used */\n\tshort\tstatus; \t/* playing, cloaked, etc. */\n\tshort\ttampered;\t/* decree'd, etc. flag */\n\tdouble\tscratch1, scratch2;\t/* var's for above */\n\tbool\tblind;\t\t/* blindness */\n\tint\twormhole;\t/* # of wormhole, 0 = none */\n\tlong\tage;\t\t/* age in seconds */\n\tshort\tdegen;\t\t/* age/2500 last degenerated */\n\t};\n\nstruct\tmstats\t\t/* monster stats */\n\t{\n\tchar\tname[26];\t/* name */\n\tdouble\tstr;\t\t/* strength */\n\tdouble\tbrn;\t\t/* brains */\n\tdouble\tspd;\t\t/* speed */\n\tdouble\thit;\t\t/* hits (energy) */\n\tdouble\texp;\t\t/* experience */\n\tint\ttrs;\t\t/* treasure type */\n\tint\ttyp;\t\t/* special type */\n\tint\tflk;\t\t/* % flock */\n\t};\n\nstruct\tnrgvoid \t/* energy void */\n\t{\n\tbool\tactive; \t/* active or not */\n\tdouble\tx,y;\t\t/* coordinates */\n\t};\n\nstruct\tworm_hole\t/* worm hole */\n\t{\n\tchar\tf, b, l, r;\t/* forward, back, left, right */\n\t};\n\n/* files */\n#define monsterfile\tPATH\"/monsters\"\n#define peoplefile\tPATH\"/characs\"\n#define gameprog\tPATH\"/phantasia\"\n#define messfile\tPATH\"/mess\"\n#define lastdead\tPATH\"/lastdead\"\n#define helpfile\tPATH\"/phant.help\"\n#define motd\t\tPATH\"/motd\"\n#define goldfile\tPATH\"/gold\"\n#define voidfile\tPATH\"/void\"\n#define\tenemyfile\tPATH\"/enemy\"\n\nextern\tjmp_buf fightenv, mainenv;\nextern\tdouble\tstrength, speed;\nextern\tbool\tbeyond, marsh, throne, valhala, changed, fghting, su, wmhl;\nextern\tstruct worm_hole\tw_h[];\nextern\tlong\tsecs;\nextern\tint\tfileloc, users;\n\nvoid interrupt(int sig);\nvoid strunc(char *str);\nvoid update(struct stats *stat, int place);\nvoid exit1(void);\nvoid getstring(char *cp, int mx);\nvoid paws(int where);\n\ndouble inflt(void);\n"
  },
  {
    "path": "games/phantasia/phant.nr",
    "content": ".de sh\n.br\n.ne 5\n.PP\n\\fB\\\\$1\\fR\n.PP\n..\n.TH PHANTASIA 6 \"May 20, 1986\"\n.UC 4\n.SH NAME\nphantasia \\- an interterminal fantasy game\n.SH SYNOPSIS\n.B phantasia\n[\n.B \\-s\n] [\n.B \\-m\n] [\n.B \\-a\n] [\n.B \\-x\n] [\n.B \\-h\n] [\n.B \\-H\n] [\n.B \\-p\n]\n.SH DESCRIPTION\n.I Phantasia\nis a role playing game vaguely similar to dungeons and dragons.\nIt allows players to roll up characters of various types to fight\nmonsters and other players.\nProgression of characters is based upon gaining experience from fighting\nmonsters (and other players).\n.PP\nMost of the game is menu driven and self-explanatory (more or less).\nThe screen is cursor updated, so be sure to set up the\n.B TERM\nvariable in your environment.\n.PP\nThe options provide for a variety of functions to support the game.\nThey are:\n.PP\n.TP .5i\n.B \\-s\nInvokes \n.I phantasia\nwithout header information.\n.TP .5i\n.B \\-m\nGet a monster listing.\n.TP .5i\n.B \\-a\nGet a listing of all character names on file.\n.TP .5i\n.B \\-x\nExamine/change a particular character on file.\n.TP .5i\n.B \\-h\nGet a help listing (this message).\n.TP .5i\n.B \\-H\nGet header listing only.\n.TP .5i\n.B \\-p\nPurge old characters.\n.PP\nThe characters are saved on a common file, in order to make the game\ninteractive between players.  The characters are given a password\nin order to retrieve them later.  Only characters above\n.B level\nzero are saved.  Characters unused for more than nine days will be\npurged.\n.SH AUTHOR\nEdward Estes, AT&T Teletype Corp.\n.SH PARTICULARS\n.sh \"Playing in General\"\nCertain of the player's more important statistics are almost always\ndisplyed on the screen, with maximums (where applicable) in\nparentheses.\n.PP\nThe character is placed randomly near the center of a cartesian\nsystem.  One may move by hitting\n.B E, W, N,\nor\n.B S\n(lower case may also be used, at no time is the game case dependent).\nTo move to a particular (x,y) coordinate, use the\n.B move\n('1') command.\tThe distance a character can move is calculated by\n1 plus 1.5 per\n.B level.\nMoving in a particular compass direction will move the player the maximum\nallowed distance in that direction.\n.PP\nA player may at any time see who else is playing with a\n.B players\n('2') option.  One may see only those who are the same distance or closer\nto the origin as he/she.\n.B Kings,\nand\n.B council of the wise\ncan see and can be seen by everyone.  A\n.B palantir\nremoves these retrictions.\n.PP\nOne can talk to other players with the\n.B talk\n('3') option.  In general, this is a line or so of text.  To remove a current\nmessage, just type <return> when prompted for a message.\n.PP\nThe\n.B stats\n('4') option shows a players characteristics in more detail.\n.PP\nOne may leave the game either with the\n.B quit\n('5') option, or by hitting interrupt.\tQuitting during battle results\nin death for obvious reasons.\n.PP\nOne may rest by default.  Resting lets one regain maximum\n.B energy level,\nand also lets one find\n.B manna\n(more is found for larger levels and further distances from the origin).\n.PP\nOne may call a monster by hitting '9'.\n.PP\nSeveral other options become available as the player progress in\n.B level\nand\n.B magic,\nor to other positions in the game (\n.B valar, council of the wise, king\n).\nThese are described elsewhere.\nIn general, a control-L will force the redrawing of the screen.\n.PP\nOther things which may happen are more or less self-explanatory.\n.sh \"Fighting Monsters\"\nA player has several options while fighting monsters.  They are as follows:\n.TP 1.5i\n.B melee\nInflicts damage on the monster, based upon\n.B strength.\nAlso decreases the monster's\n.B strength\nsome.\n.TP 1.5i\n.B skirmish\nInflicts a little less damage than\n.B melee,\nbut decreases the monster's\n.B quickness\ninstead.\n.TP 1.5i\n.B evade\nAttempt to run away.  Success is based upon both the player's and\nthe monster's\n.B brains\nand\n.B quickness.\n.TP 1.5i\n.B spell\nSeveral options for throwing spells (described elsewhere).\n.TP 1.5i\n.B nick\nHits the monster one plus the player's\n.B sword,\nand gives the player 10% of the monster's\n.B experience.\nDecreases the monster's\n.B experience\nan amount proportional to the amount granted.\nThis also increases the monster's quickness.\nParalyzed monsters wake up very fast when nicked.\n.TP 1.5i\n.B luckout\nThis is essentially a battle of wits with the monster.\tSuccess is based\nupon the player's and the monster's\n.B brains.\nThe player gets credit for slaying the monster if he/she succeeds.\nOtherwise, nothing happens, and the chance to\n.B luckout\nis lost.\n.sh \"Character Statistics\"\n.TP 1.5i\n.B strength\ndetermines how much damage a character can inflict.\n.TP 1.5i\n.B quickness\ndetermines how many chances a character gets to make decisions while\nfighting.\n.TP 1.5i\n.B energy level\nspecifies how much damage a character may endure before dying.\n.TP 1.5i\n.B magic level\ndetermines which spells a character may throw, and how effective those\nspells will be.\n.TP 1.5i\n.B brains\nbasically, the character's intelligence; used for various fighting options\nand spells.\n.TP 1.5i\n.B manna\nused as a power source for throwing spells.\n.TP 1.5i\n.B experience\ngained by fighting monsters and other characters.\n.TP 1.5i\n.B level\nindicative of how much experience a character has accumulated; progresses\ngeometrically as\n.B experience\nincreases.\n.TP 1.5i\n.B poison\nsickness which degrades a character's performance (affects\n.B energy level\nand\n.B strength\n).\n.TP 1.5i\n.B sin\naccumulated as a character does certain nasty things; used only rarely\nin normal play of the game.\n.TP 1.5i\n.B age\nnumber of seconds of playing time for the character.\nAs\n.B age\nincreases, many personal statistics degenerate.\n.sh \"Character Types\"\nCharacter statistics are rolled randomly from the above list, according\nto character type.  The types are as follows:\n.TP 1.5i\n.B magic user\nstrong in\n.B magic level\nand\n.B brains\n, weak in other areas.\tMust rely on wits and magic to survive.\n.TP 1.5i\n.B fighter\ngood in\n.B strength\nand\n.B energy level\n, fairly good in other areas.  This adds up to a well-equipped fighter.\n.TP 1.5i\n.B elf\nvery high\n.B quickness\nand above average\n.B magic level\nare\n.B elves\nselling points.\n.TP 1.5i\n.B dwarf\nvery high\n.B strength\nand\n.B energy level\n, but with a tendency to be rather slow and not too bright.\n.TP 1.5i\n.B halfling\nrather quick and smart, with high\n.B energy level\n, but poor in\n.B magic\nand\n.B strength.\nBorn with some\n.B experience.\n.TP 1.5i\n.B experimento\nvery mediocre in all areas.  However, the\n.B experimento\nmay be placed almost anywhere within the playing grid.\n.PP\nThe possible ranges for starting statistics are summarized in\nthe following table.\n.PP\n.TS\nl c c c c c c\nl c c c c c c.\nType\tStrength\tQuick\tManna\tEnergy\tBrains\tMagic\n_\nMag. User\t20-25\t30-35\t50-100\t30-45\t60-85\t5-9\nFighter\t40-55\t30-35\t30-50\t45-70\t25-45\t3-6\nElf\t35-45\t28-38\t45-90\t30-50\t40-65\t4-7\nDwarf\t50-70\t25-30\t25-45\t60-100\t20-40\t2-5\nHalfling\t20-25\t34\t25-45\t55-90\t40-75\t1-4\nExperimento\t25\t27\t100\t35\t25\t2\n.TE\n.PP\nNot only are the starting characteristics different for the different\ncharacter types, the characteristics progress at different rates for the\ndifferent types as the character goes up in\n.B level.  Experimentoes'\ncharacteristics progress randomly as one of the other types.\nThe progression as characters increase in\n.B level\nis summarized in the following table.\n.PP\n.TS\nl c c c c c\nl n n n n n.\nType\tStrength\tManna\tEnergy\tBrains\tMagic\n_\nMag. User\t2.0\t75\t20\t6\t2.75\nFighter\t3.0\t40\t30\t3.0\t1.5\nElf\t2.5\t65\t25\t4.0\t2.0\nDwarf\t5\t30\t35\t2.5\t1\nHalfling\t2.0\t30\t30\t4.5\t1\n.TE\n.PP\nCharacter types are identified by certain numeric values as follows:\n.br\n1:\n.B Magic User\n2:\n.B Fighter\n3:\n.B Elf\n4:\n.B Dwarf\n5:\n.B Halfling\n6:\n.B Experimento\n.PP\nCharacters with one or more\n.B crowns\nare designated as a negative type.\n.B Kings\nhave ten added to their type; members of the\n.B council of the wise\nhave twenty added to their type.\n.B Valar\nare type 99, and\n.B ex-valar\nare type 90.\n.sh \"Spells\"\nDuring the course of the game, the player may exercise his/her particular\nmagic powers.  These cases are described below.\n.TP 1.5i\n.B cloak\n.I magic level necessary:\n15 (plus level 5)\n.br\n.I manna used:\n35 plus 3 per rest period\n.br\nUsed during normal play.  Prevents monsters from finding the character,\nas well as hiding the player from other players.  His/her coordinates\nshow up as '?' in the\n.B players\noption.  Players cannot collect\n.B manna,\nfind trading posts, or discover the\n.B grail\nwhile cloaked.\tCalling a monster uncloaks, as well as choosing\nthis option while cloaked.\n.br\n.TP 1.5i\n.B teleport\n.I magic level necessary:\n25 (plus level 10)\n.br\n.I manna used:\n20 per 75 moved\n.br\nUsed during normal play.  Allows the player too move with much more freedom\nthan with the\n.B move\noption, at the price of expending manna.  The maximum distance possible\nto move is based upon\n.B level\nand\n.B magic level.\n.TP 1.5i\n.B power blast\n.I magic level necessary:\nnone\n.br\n.I manna used:\n5 times\n.B level\n.br\nUsed during inter-terminal battle.  Damage is based upon\n.B magic level\nand\n.B strength.\nHits much harder than a normal hit.\n.TP 1.5i\n.B all or nothing\n.I magic level necessary:\nnone\n.br\n.I manna used:\n1\n.br\nUsed while combatting monsters.\nHas a 25% chance of working.  If it works it hits the monster just enough\nto kill it.  If it fails, it doesn't hit the monster, and doubles the\nmonster's\n.B quickness\nand\n.B strength.\nParalyzed monsters wake up much quicker as a result of this spell.\n.TP 1.5i\n.B magic bolt\n.I magic level necessary:\n3\n.br\n.I manna used:\nvariable\n.br\nUsed while combatting monsters.  Hits the monster based upon the amount\nof\n.B manna\nexpended and\n.B magic level.\nGuaranteed to hit at least 10 per\n.B manna.\n.TP 1.5i\n.B force field\n.I magic level necessary:\n7\n.br\n.I manna used:\n20\n.br\nUsed during monster combat.  Throws up a shield to protect from damage.\nThe shield is added to actual energy level, and is a fixed number, based\nupon maximum energy.  Normally, damage occurs first to the shield, and\nthen to the players actual\n.B energy level.\n.TP 1.5i\n.B transform\n.I magic level necessary:\n10\n.br\n.I manna used:\n35\n.br\nUsed during monster combat.  Transforms the monster randomly into one\nof the other 100 monsters from the monster file.\n.TP 1.5i\n.B increase might\n.I magic level necessary:\n15\n.br\n.I manna used:\n55\n.br\nUsed during combat with monsters.  Increases strength up to a certain maximum.\n.TP 1.5i\n.B invisibility\n.I magic level necessary:\n20\n.br\n.I manna used:\n45\n.br\nUsed while fighting monsters.  Makes it harder for the monster to hit,\nby temporarily increasing the player's\n.B quickness.\nThis spell may be thrown several times, but a maximum level will be reached.\n.TP 1.5i\n.B transport\n.I magic level necessary:\n25\n.br\n.I manna used:\n50\n.br\nUsed during monster combat.  Transports the monster away from the\nplayer.  Success is base upon player's\n.B magic\nand\n.B brains,\nand the monster's\n.B experience.\nIf it fails the player is transported instead.\t60% of the time, the monster\nwill drop any treasure it was carrying.\n.TP 1.5i\n.B paralyze\n.I magic level necessary:\n30\n.br\n.I manna used:\n60\n.br\nUsed during monster combat.  \"Freezes\" the monster by putting its\n.B quickness\nslightly negative.  The monster will slowly wake up.  Success is based\nupon player's\n.B magic\nand the monster's\n.B experience.\nIf it fails, nothing happens.\n.TP 1.5i\n.B specify\n.I magic level necessary:\nnone\n.br\n.I manna used:\n1000\n.br\nUsed during monster combat only by\n.B valar\nor\n.B council of the wise.\nAllows the player to pick which monster to fight.\n.sh \"Monsters\"\nMonsters get bigger as one moves farther from the origin (0,0).  Rings of\ndistance 125 from the origin determine the size.  A monster's\n.B experience, energy level,\nand\n.B brains\nare multiplied by the size.\n.B Strength\nis increase 50% per size over one, and\n.B quickness\nremains the same, regardless of size.\n.PP\nAlso, meaner monsters are to be found as one progress farther out\nfrom the origin.  Monsters also may flock.  The percent chance of that\nhappening is designated as\n.B flock%\nin the monster listing.  Monsters outside the first ring\nmay carry treasure, as determined by their treasure type.\nFlocking monsters, and bigger monsters increase the chances of treasure.\n.PP\nCertain monsters have special abilities; they are as follows:\n.TP 1.5i\n.B Unicorn\ncan only be subdued if the player is in possession of a\n.B virgin.\n.TP 1.5i\n.B Modnar\nhas random characteristics, including treasure type.\n.TP 1.5i\n.B Mimic\nwill pick another name from the list of monsters in order to\nconfuse.\n.TP 1.5i\n.B Dark Lord\nvery nasty person.  Does not like to be hit (especially nicked),\nand many spells do not work well against him.\nOne can always\n.B evade\nfrom the\n.B Dark Lord.\n.TP 1.5i\n.B Leanan-Sidhe\nalso a very nasty person.  She will permanently sap\n.B strength\nfrom someone.\n.TP 1.5i\n.B Saruman\nwanders around with\n.B Wormtongue\n, who can steal a\n.B palantir.\nAlso,\n.B Saruman\nmay turn a player's gems into gold pieces,\nor scramble her/his stats.\n.TP 1.5i\n.B Thaumaturgist\ncan transport a player.\n.TP 1.5i\n.B Balrog\ninflicts damage by taking away\n.B experience\n, not\n.B energy.\n.TP 1.5i\n.B Vortex\nmay take some\n.B manna.\n.TP 1.5i\n.B Nazgul\nmay try to steal a\n.B ring\nor neutralize part of one's\n.B brains.\n.TP 1.5i\n.B Tiamat\nmay take half a players\n.B gold\nand\n.B gems\nand escape.\n.TP 1.5i\n.B Kobold\nmay get nasty and steal one gold piece and run away.\n.TP 1.5i\n.B Shelob\nmay bite, inflicting the equivalent of one\n.B poison.\n.TP 1.5i\n.B Assorted Faeries\nThese are killed if attacking someone carrying\n.B holy water.\nThese are\n.B Cluricaun, Fir Darrig, Fachan,\n.B Ghille Dhu, Bogle, Killmoulis,\nand\n.B Bwca.\n.TP 1.5i\n.B Lamprey\nmay bite, inflicting 1/2 of a\n.B poison.\n.TP 1.5i\n.B Shrieker\nwill call one of its (much bigger) buddies if picked upon.\n.TP 1.5i\n.B Bonnacon\nwill become bored with battle, fart, and run off.\n.TP 1.5i\n.B Smeagol\nwill try to steal a\n.B ring\nfrom a player, if given the chance.\n.TP 1.5i\n.B Succubus\nmay inflict damage through a\n.B force field.\nThis subtracts from\n.B energy level\ninstead of any shield the player may have thrown up.\nThis is a very easy way to die.\n.TP 1.5i\n.B Cerberus\nloves metal and will steal all the metal treasures from\na player if able.\n.TP 1.5i\n.B Ungoliant\ncan bite and poison.  This inflicts five\n.B poisons\n, and also takes one from the player's\n.B quickness.\n.TP 1.5i\n.B Jabberwock\nmay tire of battle, and leave after calling one of his friends\n(\n.B Jubjub Bird\nor\n.B Bandersnatch\n).\n.TP 1.5i\n.B Morgoth\nactually\n.B Modnar\n, but reserved for\n.B council of the wise, valar,\nand\n.B ex-valar.\nFights with\n.B Morgoth\nend when either he or the player dies.\tHis characteristics\nare calculated based upon the player's.  The player is given\nthe chance to ally with him.  No magic, except\n.B force field\nworks when battling\n.B Morgoth.\n.TP 1.5i\n.B Troll\nmay regenerate its\n.B energy\nand\n.B strength\nwhile in battle.\n.TP 1.5i\n.B Wraith\nmay make a player blind.\n.sh \"Treasures\"\nVarious treasure types are as follows:\n.TP 1.5i\n.B Type zero\n.I none\n.TP 1.5i\n.B Type one\n.I power booster\n\\- adds manna.\n.br\n.I druid\n\\- adds experience.\n.br\n.I holy orb\n\\- subtracts 0.25 sin.\n.TP 1.5i\n.B Type two\n.I amulet\n\\- protects from cursed treasure.\n.br\n.I holy water\n\\- kills\n.B assorted faeries.\n.br\n.I hermit\n\\- reduces sin by 25% and adds some manna.\n.TP 1.5i\n.B Type three\n.I shield\n\\- adds to maximum\n.B energy level\n.br\n.I virgin\n\\- used to subdue a\n.B unicorn\n, or to give much\n.B experience\n(and some\n.B sin\n).\n.br\n.I athelas\n\\- subtracts one\n.B poison.\n.TP 1.5i\n.B Type four (scrolls)\n.I shield\n* \\- throws a bigger than normal\n.B force field.\n.br\n.I invisible\n* \\- puts the finder's\n.B quickness\nto one million.\n.br\n.I ten fold strength\n* \\- multiplies finder's strength by ten.\n.br\n.I pick monster\n\\- allows finder to pick next monster to battle.\n.br\n.I general knowledge\n\\- adds to finder's\n.B brains\nand\n.B magic level.\n.PP\nAll the scrolls except\n.B general knowledge\nautomatically call a monster.  Those that are marked with a * preserve any\nspells that were already in effect.  Those that call monsters are only in\neffect while in battle.\n.TP 1.5i\n.B Type five\n.I dagger\n\\- adds to\n.B strength.\n.br\n.I armour\n\\- same as a\n.B shield,\nbut bigger.\n.br\n.I tablet\n\\- adds brains.\n.TP 1.5i\n.B Type six\n.I priest\n\\- rests to maximum; adds \n.B manna, brains;\nand halves\n.B sin.\n.br\n.I Robin Hood\n\\- increases\n.B shield\nand adds permanently to\n.B strength.\n.br\n.I axe\n\\- like\n.B dagger,\nbut bigger.\n.TP 1.5i\n.B Type seven\n.I charm\n\\- protects from cursed treasure (used before\n.B amulet\n); used in conjunction with\n.B blessing\nto battle\n.B Dark Lord.\n.br\n.I Merlyn\n\\- adds\n.B brains, magic,\nand\n.B manna.\n.br\n.I war hammer\n\\- like an\n.B axe,\nbut bigger.\n.TP 1.5i\n.B Type eight\n.I healing potion\n\\- sets\n.B poison\nto -2, or subtracts two from\n.B poison,\nwhichever is better.\n.br\n.I transporter\n\\- allows finder to move anywhere.\n.br\n.I sword\n\\- like a\n.B war hammer\n, but bigger.\n.TP 1.5i\n.B Type nine\n.I golden crown\n\\- allows the player to become\n.B king,\nby going to (0,0).\n.br\n.I blessing\n\\- cuts\n.B sin\nto 1/3, adds\n.B manna,\nrests to max., and kills\n.B Dark Lord\nwith a\n.B charm.\n.br\n.I quicksilver\n\\- adds to \n.B quickness.\n.TP 1.5i\n.B Type ten\n.I elven boots\n\\- adds permanently to\n.B quickness.\n.TP 1.5i\n.B Type eleven\n.I palantir\n\\- allows one to see all the other players; used by\n.B council of the wise\nto seek the\n.B grail.\n.TP 1.5i\n.B Type twelve/thirteen\n.I ring\n\\- allows one to hit much harder in battle, etc.\n.PP\nAny treasure type 10-13 monsters may instead carry a type nine treasure.\n.PP\nA monster may also be carrying\n.B gold\nor\n.B gems.\nThese are used at\n.B trading posts\nto buy things.\tA\n.B gem\nis worth 1000 gold pieces.  Too much\n.B gold\nwill slow a player down.  One may carry 1000 plus 200 per\n.B level\nof\n.B gold.\nA\n.B gem\nweighs one half a gold piece.\nMonsters of treasure type 7 or higher may carry\n.B gems.\n.PP\nThe chance of a cursed treasure is based upon treasure type.\nThe more valuable treasures have a greater chance of being cursed.\nA cursed treasure knocks\n.B energy level\nvery low, and adds 0.25\n.B poison.\n.sh \"Rings\"\n.B Rings\nare only carried by\n.B nazguls\nand\n.B Dark Lord.\nThey come in four different flavors.\nAll\n.B rings\nrest the player to maximum and cause him/her to hit much harder\nin battle with monsters (assuming one has chosen to use the\n.B ring\nfor battle.)\n.PP\nTwo types of\n.B rings\nare cursed and come either from\n.B nazguls\nor\n.B Dark Lord.\nAfter a few times of using these types, the player falls\nunder the control of the\n.B ring,\nand strange, random things will occur.\nEventually, the player dies, and gives his/her name to a monster\non the file.\nDying before the\n.B ring\nis used up also renames the monster.\n.PP\nThe two remaining types of\n.B rings\nare much more benign.\nThe one from a\n.B nazgul\nis good for a limited number of battle rounds, and will save\nthe player from death if it was being used when he/she died.\nThe one from\n.B Dark Lord\nis the same, except that it never is used up.\n.B rings\ndisappear after saving someone from death.\nIn general, cursed\n.B rings\noccur much more often than normal ones.\nIt is usually not a good idea to pick one up.\nThe only way to get rid of a\n.B ring\nis to have a monster steal it.\n.sh \"King\"\nA player may become\n.B king by finding a\n.I crown\nand going to (0,0).  Players must have a\n.B level\nin the range of 10 to 1000 to be able to find a\n.I crown.\n.PP\nOnce a player is king, he/she may do certain things while in \nthe Lord's Chamber (0,0).  These fall under the\n.B decree\n('0') option.\n.TP 1.5i\n.I transport\nThis is done to another player.  It randomly moves the affected\nplayer about.  A\n.B charm\nprotects from transports.\n.TP 1.5i\n.I curse\nThis is done to another player.  It is analogous to cursed treasure,\nbut worse.  It inflicts two\n.B poison,\nknocks\n.B energy level\nvery low, and degrades the maximum energy.  It also\nremoves a\n.B cloak.\nA\n.B blessing\nprotects from king's curses.\n.TP 1.5i\n.I energy void\nThe king may put as many of these (within reason) scattered about\nhis/her kingdom as he/she pleases.\nIf a player hits one, he/she loses\n.B manna, energy,\nand\n.B gold.\nThe energy void disappears after being hit.\n.TP 1.5i\n.I bestow\nThis is also done to another player.  The king may\nwish to reward one or more loyal subjects by sharing his/her\nriches (\n.B gold\n).  Or it is a convenient way to dispose of some unwanted\ndeadweight.\n.TP 1.5i\n.I collect taxes\nEveryone pays 10% tax on all\n.B gold\ncollected, regardless of the existence of a\n.B king.\nThe king may collect this amount with this option.\n.PP\nThe\n.B king\nmay also \n.B teleport\nanywhere for free by using the origin as a starting place.\n.sh \"Special Places\"\nCertain regions of the playing grid have different names.\nIn general, this is only to give the player some idea of\nhis/her present location.  Some special places do exist.\n.TP 1.5i\n.I Trading Posts\nThese are located at |x| == |y| == n*n*100 for n = 1, 2...1000.\nTrading posts farther out have more things for sale.\nBe careful about cheating merchants there, as they have short\ntempers.\nMerchants are dishonest about 5% of the time.\n.TP 1.5i\n.I Lord's Chamber\nThis is located at (0,0).  Only players with\n.B crowns\nmay enter.\n.TP 1.5i\n.I Point of No Return\nThis is located beyond 1.2e+6 in any direction.\nThe only way to return from here is a\n.B transporter\nor to have a\n.B valar\nrelocate the player.\n.TP 1.5i\n.I Dead Marshes\nThis is a band located fairly distant from the origin.\tThe first\nfourteen monsters (water monsters) can normally only be found here.\n.TP 1.5i\n.I Valhala\nThis place is where the\n.B valar\nresides.  It is associated with no particular coordinate on the\nplaying grid.\n.TP 1.5i\n.I Wormholes\nAt fixed locations on the grid are several holes to underground\ndefects in the playing area.\nSixty-four chambers exist; sixteen of which open to the outside\nworld.\nWhile in the wormholes, one move by going forward, backward,\nleft, or right.\nOne can always undo a move by going in the opposite direction.\nThe wormholes are mappable.\nFor example, to move from the first wormhole {at (-400,0)} to\nthe second wormhole, type 'LL'.\n.sh \"Miscellaneous\"\nThere are several bits of trivial knowledge which fall under this category.\n.PP\nA\n.I guru\nwill never be disgusted with your\n.B sins\nif they are less than one.\n.PP\nA\n.I medic\nwants half of a player's\n.B gold\nto be happy.  Offering more than one has, or a negative amount\nwill anger the\n.I medic,\nwho will make the player worse (add one\n.B poison\n).\n.PP\nThe\n.B Holy Grail\ndoes little for those who are not ready to behold it.\nWhenever anyone finds it, it moves.\nIt is always located within 1e+6 in any compass direction of the origin.\n.PP\nThere is a maximum amount of\n.B manna\nand\n.B charms\na player may posses, based upon\n.B level.\n.I Quicksilver\nis always limited to to a maximum of 99.\n.PP\n.I Books\nbought at a\n.B trading post\nincrease \n.B brains,\nbased upon the number bought.\nIt is unwise, however to buy more than 1/10 of one's\n.B level\nin books at a time.\n.PP\nPlayers over level 10000 are automatically retired.\n.PP\nA\n.I blindness\ngoes away in random time.\n.sh \"Inter-terminal Battle\"\nWhen two player's coordinates correspond, they may engage in battle.\nIn general, the player with the highest\n.B quickness\ngets the first hit.\nIf the two players are severely mis-matched, the stronger player\nis drastically handicapped for the battle.\nIn order to protect from being stuck in an infinite loop,\nthe player waiting for response may time out.  Options for battle are:\n.TP 1.5i\n.I fight\nInflicts damage upon other person.\n.TP 1.5i\n.I run away\nEscape from battle.  Has a 75% chance of working.\n.TP 1.5i\n.I power blast\nBattle spell.\n.TP 1.5i\n.I luckout\nOne-time chance to try to win against the foe.\tHas a 10% chance of working.\n.PP\nSometimes waits for the other player may be excessive, because\nhe/she may be battling a monster.  Upon slaying a player in battle\nthe winner gets the other's\n.B experience\nand treasures.\n.B Rings\ndo not work for inter-terminal battle.\n.sh \"Council of the Wise, Valar\"\nA player automatically becomes a member of the\n.B council of the wise\nupon reaching level 3000.  Members of the council cannot have\n.B rings.\nMembers of the council have a few extra options which they can exercise.\nThese fall under the\n.B intervention\n('8') option.\nOne is to\n.I heal\nanother player.  This is just a quick way for that player to be rested\nto maximum and lose a little\n.B poison.\nThe main purpose in life for members of the council is to seek the\n.B Holy Grail.\nThis is done with a\n.B palantir\nunder the\n.I seek grail\noption.  The distance cited by the seek is accurate within 10%, in order\nnot to make it too easy to find the grail.  Seeking costs 1000\n.B manna.\nA player must have infintesimally small\n.B sin,\nor else it's all over upon finding the grail.\nIn order to help members of the council on their quest, they\nmay\n.I teleport\nwith greater ease.\n.PP\nUpon finding the grail, the player advance to position of\n.B valar.\nHe/she may then exercise more and niftier options under\n.I intervention.\nThese include all of the council members' option plus the\nability to move other players about, bless them, and throw monsters at\nthem.\n.B Valar\nare essentially immortal, but are actually given five lives.\nIf these are used up, the player is left to die, and becomes an\n.B ex-valar.\n.B Valar\ncannot\n.I move, teleport,\nor call monsters.\nAny monsters which a\n.B valar\nencounters are based upon his/her size.\nOnly one valar may exists at a time.\nA player replaces the exiting valar upon finding the grail.\nThe valar is then bumped back to the council of the wise.\n.SH BUGS\nMany.  The whole program is a hack.  The handling of incorrectly\nexitted characters is a kludge.  The screen is set up assuming a 24 by 80\ncharacter screen; no attempt was made to provide otherwise.\nIf the program is not set uid, it crashes on the first attempt to open a\ndata file.\nIf any of the data items get too big for the allotted space on the screen,\nno guarantees are made about what will happen.\nThere should be a way to change a character's name.\n"
  },
  {
    "path": "games/phantasia/phant_run.c",
    "content": "/*\n\tThis is a program to run phantasia\n\n\tDavid Wells, May, 1986\n*/\n\nmain(argc, argv)\n\tint argc;\n\tchar **argv;\n{\n\tchar tmp[160];\n\tstrcat(tmp,\"exec nice /usr/games/lib/phantasia/phantasia \");\n\tif (argc > 1)\n\t\tstrcat(tmp,argv[1]);\n\tsystem(tmp);\n}\n"
  },
  {
    "path": "games/phantasia/setfiles.c",
    "content": "/*\n * setfiles.c\tProgram to set up all files for Phantasia\n *\n *\t\tThis program tries to verify the parameters specified in\n *\t\tthe Makefile.  Since Phantasia assumes its files exist,\n *\t\tsimple errors can result in core dumps.\n *\n *\t\tThis program tries to check against this.\n */\n\n#include \"phant.h\"\n#include <sys/types.h>\n#include <sys/stat.h>\n\nint\nmain(argc,argv)\t\t\t\t\t/* program to init. files for Phantasia */\n        int\targc;\n        char\t**argv;\n{\n        FILE\t*fp;\n        struct\tstats\tsbuf;\n        struct\tnrgvoid\tgrail;\n        struct\tstat\tfbuf;\n        register\tint\tloop;\n        int\tfoo;\n        char\tstbuf[128];\n\n#ifdef notdef\n\tsrand((int) time(NULL));\t/* prime random numbers */\n\t/* try to check RAND definition */\n\tfor (loop = 1000; loop; loop--) {\n\t\tif ((foo = rand()) > ((int) RAND)) {\n\t\t\tsprintf(stbuf,\"%f %f\",(double) RAND, (double) foo);\n\t\t\tError(\"%s is a bad value for RAND.\\n\",stbuf);\n\t\t}\n\t}\n#endif\n\tumask(077);\n\n\t/* check where Phantasia lives */\n\tif (stat(PATH, &fbuf) < 0) {\n\t\tperror(PATH);\n\t\texit(1);\n\t\t/*NOTREACHED*/\n\t}\n\tif (fbuf.st_mode & S_IFDIR == 0)\n\t\tError(\"%s is not a directory.\\n\", PATH);\n\n\t/* try to create data files */\n\tif ((fp = fopen(goldfile,\"w\")) == NULL)\n\t\tError(\"cannot create %s.\\n\",goldfile);\n\telse\n\t\tfclose(fp);\n\n\tif ((fp = fopen(motd,\"w\")) == NULL)\n\t\tError(\"cannot create %s.\\n\",motd);\n\telse\n\t\tfclose(fp);\n\n\tif ((fp = fopen(messfile,\"w\")) == NULL)\n\t\tError(\"cannot create %s.\\n\",messfile);\n\telse\n\t\tfclose(fp);\n\n\t/* do not reset character file if it already exists */\n\tif (stat(peoplefile,&fbuf) < 0) {\n\t\tbuildchar(&sbuf);\n\t\tstrcpy(sbuf.name,\"<null>\");\n\t\tif ((fp = fopen(peoplefile,\"w\")) == NULL)\n\t\t\tError(\"cannot create %s.\\n\",peoplefile);\n\t\telse {\n\t\t\tfwrite(&sbuf,sizeof(sbuf),1,fp);\n\t\t\tfclose(fp);\n\t\t}\n\t}\n\tgrail.active = TRUE;\n\tgrail.x = roll(-1.0e6,2.0e6);\n\tgrail.y = roll(-1.0e6,2.0e6);\n\tif ((fp = fopen(voidfile,\"w\")) == NULL)\n\t\tError(\"cannot create %s.\\n\",voidfile);\n\telse {\n\t\tfwrite(&grail,sizeof(grail),1,fp);\n\t\tfclose(fp);\n\t}\n\tif ((fp = fopen(lastdead,\"w\")) == NULL)\n\t\tError(\"cannot create %s.\\n\",lastdead);\n\telse {\n\t\tfputs(\" \",fp);\n\t\tfclose(fp);\n\t}\n#ifdef ENEMY\n\tif ((fp = fopen(enemyfile,\"w\")) == NULL)\n\t\tError(\"cannot create %s.\\n\",enemyfile);\n\telse {\n\t\t/* comment this out for now\n\t\tfprintf(fp,\"# Use this file to restrict access from obnoxious users.\\n\");\n\t\tfprintf(fp,\"# Just put the login names of those restricted, one per\\n\");\n\t\tfprintf(fp,\"# line, below.\\n\");\n\t\t*/\n\t\tfclose(fp);\n\t}\n#endif\n\tif (getuid() != UID)\n\t\tfprintf(stderr,\"Warning: UID (%d) is not equal to current uid.\\n\",UID);\n}\n\n/*\n * Note that this function is almost the same as initchar().\n * t is used to insure that unexpected values will not be found in a\n * new character file.\n */\nbuildchar(stat)\t\t\t\t/* put in some default values */\n        struct\tstats\t*stat;\n{\n\tstat->x = roll(-125,251);\n\tstat->y = roll(-125,251);\n\tstat->exp = stat->lvl = stat->sin = 0;\n\tstat->crn = stat->psn = 0;\n\tstat->rng.type = NONE;\n\tstat->rng.duration = 0;\n\tstat->pal = FALSE;\n\tstat->hw = stat->amu = stat->bls = 0;\n\tstat->chm = 0;\n\tstat->gem = 0.1;\n\tstat->gld = roll(25,50) + roll(0,25) + 0.1;\n\tstat->quks = stat->swd = stat->shd = 0;\n\tstat->vrg = FALSE;\n\tstat->typ = 0;\n}\n\nError(str,file)\t\t/* print an error message, and exit */\n        char\t*str, *file;\n{\n\tfprintf(stderr,\"Error: \");\n\tfprintf(stderr,str,file);\n\texit(1);\n\t/*NOTREACHED*/\n}\n"
  },
  {
    "path": "games/phantasia/test.c",
    "content": "main()\n{\ndouble Too_Big = 987654321;\n\ntemp = Too_Big;\nprintf(\"Too_Big = %f, temp = %d/n\",&Too_Big, &temp);\n}\n"
  },
  {
    "path": "games/warp/.gitignore",
    "content": "!smp.0\n"
  },
  {
    "path": "games/warp/EXTERN.h",
    "content": "/* $Header: EXTERN.h,v 7.0.1.1 86/12/12 16:46:50 lwall Exp $\n *\n * $Log:\tEXTERN.h,v $\n * Revision 7.0.1.1  86/12/12  16:46:50  lwall\n * Guarded the undefs.\n * \n * Revision 7.0  86/10/08  15:11:31  lwall\n * Split into separate files.  Added amoebas and pirates.\n * \n */\n\n#ifdef EXT\n#undef EXT\n#endif\n#define EXT extern\n\n#ifdef INIT\n#undef INIT\n#endif\n#define INIT(x)\n\n#ifdef DOINIT\n#undef DOINIT\n#endif\n"
  },
  {
    "path": "games/warp/INTERN.h",
    "content": "/* $Header: INTERN.h,v 7.0.1.1 86/12/12 16:51:45 lwall Exp $\n *\n * $Log:\tINTERN.h,v $\n * Revision 7.0.1.1  86/12/12  16:51:45  lwall\n * Guarded the undefs.\n * \n * Revision 7.0  86/10/08  15:11:37  lwall\n * Split into separate files.  Added amoebas and pirates.\n * \n */\n\n#ifdef EXT\n#undef EXT\n#endif\n#define EXT\n\n#ifdef INIT\n#undef INIT\n#endif\n#define INIT(x) = x\n\n#define DOINIT\n"
  },
  {
    "path": "games/warp/MANIFEST",
    "content": "After all the warp kits are run you should have the following files:\n\nFilename\t\tKit Description\n--------\t\t--- -----------\nConfigure                1  An entertaining little shell script\nEXTERN.h                 6  Set up for external .h files\nINTERN.h                 6  Set up for internal .h files\nMANIFEST                 1  This file\nMakefile.SH              5  Makefile for warp\nREADME                   5  Instructions--please read\nbang.c                   5  Routines having to do with blast propagation\nbang.h                   6  Visible declarations for above\nconfig.H                 4  Sample config.h for if you can't Configure\ninit.c                   3  Initialization for a wave.\ninit.h                   2  Visible declarations for above\nintrp.c                  4  Code to interpret % substitutions\nintrp.h                  6  Visible declarations for above\nmakedepend.SH            6  Generates makefile dependencies\nmakedir.SH               6  Makes multilevel directories\nmove.c                   3  Object movement and display\nmove.h                   6  Visible declarations for above\nndir.c                   5  Directory manipulation routines\nndir.h                   5  Visible declarations for above\nobject.c                 6  Object management\nobject.h                 6  Visible declarations for above\npatchlevel.h             4  How patched the kit is\nplay.c                   5  What to do each second\nplay.h                   6  Visible declarations for above\nscore.c                  2  Scoring and saving\nscore.h                  6  Visible declarations for above\nsig.c                    5  Signal handling\nsig.h                    6  Visible declarations for above\nsm.c                     6  Starmap translator\nsmp.0                    3  \"Straight Grid\" scenario\nsmp.1                    6  \"Offset Grid\" scenario\nsmp.2                    6  \"Shooting Gallery\" scenario\nsmp.3                    6  \"Superfortress\" scenario\nsmp.4                    6  \"Blocks\" scenario\nsmp.5                    6  \"Microfortress\" scenario\nsmp.6                    6  \"Passage\" scenario\nsmp.7                    6  \"Wall\" scenario\nterm.c                   2  Terminal handling\nterm.h                   5  Visible declarations for above\nthem.c                   5  Smarts for enemies\nthem.h                   6  Visible declarations for above\nus.c                     4  Smarts for us\nus.h                     6  Visible declarations for above\nutil.c                   1  Utility routines\nutil.h                   5  Visible declarations for above\nversion.c                6  Prints version number.\nversion.h                1  Visible declarations for above\nwarp.c                   2  Main loop\nwarp.doc                 4  How to play warp\nwarp.h                   4  Visible declarations for everyone\nwarp.man                 5  How to start warp\nwarp.news                5  Sample startup message\nweapon.c                 3  Our firepower\nweapon.h                 6  Visible declarations for above\n"
  },
  {
    "path": "games/warp/Makefile",
    "content": "TOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS\t\t+= -Os -Wall\n\nOBJS            = bang.o init.o intrp.o move.o \\\n                  object.o play.o score.o \\\n                  sig.o term.o them.o us.o \\\n                  util.o version.o warp.o weapon.o\nLIBS            = -ltermcap -lm\nMAN\t\t= warp.0\nMANSRC\t\t= warp.man\nPRIVATE         = warp.doc smap.0 smap.1 smap.2 smap.3 smap.4 smap.5 smap.6 smap.7\nPRIVLIB         = ${DESTDIR}/usr/games/lib/warp\n\nall:            warp $(MAN) $(PRIVATE)\n\nwarp:           ${OBJS}\n\t\t${CC} ${CFLAGS} ${LDFLAGS} -o warp.elf ${OBJS} ${LIBS}\n\t\t${OBJDUMP} -S warp.elf > warp.dis\n\t\t${SIZE} warp.elf\n\t\t${ELF2AOUT} warp.elf $@ && rm warp.elf\n\nsmap.0:         smp.0 sm\n\t\t./sm <smp.0 >smap.0\nsmap.1:         smp.1 sm\n\t\t./sm <smp.1 >smap.1\nsmap.2:         smp.2 sm\n\t\t./sm <smp.2 >smap.2\nsmap.3:         smp.3 sm\n\t\t./sm <smp.3 >smap.3\nsmap.4:         smp.4 sm\n\t\t./sm <smp.4 >smap.4\nsmap.5:         smp.5 sm\n\t\t./sm <smp.5 >smap.5\nsmap.6:         smp.6 sm\n\t\t./sm <smp.6 >smap.6\nsmap.7:         smp.7 sm\n\t\t./sm <smp.7 >smap.7\nsm:             sm.c\n\t\t${HOST_CC} -O -Wall sm.c -o sm\n\n${MAN}:         ${MANSRC}\n\t\t${MANROFF} ${MANSRC} > $@\n\nclean:\n\t\trm -f *.o *.elf ${MAN} warp *.elf *.dis tags *~ smap.* sm\n\ninstall:        warp $(PRIVATE)\n\t\t${INSTALL} warp ${DESTDIR}/usr/games/\n\t\tcp ${MAN} ${DESTDIR}/usr/share/man/cat6/\n\t\tmkdir -p $(PRIVLIB)\n\t\tcp $(PRIVATE) $(PRIVLIB)\n\t\tcp /dev/null $(PRIVLIB)/save.blurfl\n\t\t[ -f $(PRIVLIB)/warp.news ] || cp warp.news $(PRIVLIB)\n"
  },
  {
    "path": "games/warp/Makefile-linux",
    "content": "# $Header: Makefile.SH,v 1.1 87/07/03 01:45:30 games Exp $\n#\n# Revision 7.0.1.1a 87/26/08  03:45:03\tgames\n# Fix minor shell continuation bug and put in a pdp-11 overlay scheme.\n#\n# Revision 7.0.1.1  86/12/12  16:54:03  lwall\n# Frozen for net release.\n#\n# Revision 7.0  86/10/08  15:11:42  lwall\n# Split into separate files.  Added amoebas and pirates.\n#\n#\nCFLAGS          = -g -O -DTERMIO #-Wall\nLDFLAGS         =\nPRIVLIB         = /usr/games/lib/warp\nLIBS            = -ltermcap -lm\n\nPRIVATE         = warp.doc smap.0 smap.1 smap.2 smap.3 smap.4 smap.5 smap.6 smap.7\n\nOBJ             = bang.o init.o intrp.o move.o \\\n                  object.o play.o score.o \\\n                  sig.o term.o them.o us.o \\\n                  util.o version.o warp.o weapon.o\n\nall:    warp $(PRIVATE)\n\nwarp:   $(OBJ)\n\t$(CC) $(LDFLAGS) $(OBJ) $(LIBS) -o warp\n\ninstall: warp $(PRIVATE)\n\tinstall warp $(bin)\n\tmkdir -p $(PRIVLIB)\n\tcp $(PRIVATE) $(PRIVLIB)\n\tcp /dev/null $(PRIVLIB)/save.blurfl\n\t[ -f $(PRIVLIB)/warp.news ] || cp warp.news $(PRIVLIB)\n\nclean:\n\trm -f core *.o warp smap.* sm\n\nsmap.0: smp.0 sm\n\t./sm <smp.0 >smap.0\nsmap.1: smp.1 sm\n\t./sm <smp.1 >smap.1\nsmap.2: smp.2 sm\n\t./sm <smp.2 >smap.2\nsmap.3: smp.3 sm\n\t./sm <smp.3 >smap.3\nsmap.4: smp.4 sm\n\t./sm <smp.4 >smap.4\nsmap.5: smp.5 sm\n\t./sm <smp.5 >smap.5\nsmap.6: smp.6 sm\n\t./sm <smp.6 >smap.6\nsmap.7: smp.7 sm\n\t./sm <smp.7 >smap.7\nsm: sm.c\n\tcc -O -Wall sm.c -o sm\n"
  },
  {
    "path": "games/warp/README",
    "content": "\t\t\tWarp Kit, Version 7.0\n\n\t\t    Copyright (c) 1986, Larry Wall\n\nYou may copy the warp kit in whole or in part as long as you don't try to\nmake money off it, or pretend that you wrote it.\n--------------------------------------------------------------------------\n\nWarp is a real-time space war game that doesn't get boring very quickly.\nRead warp.doc and the manual page for more information.\n\nWarp will probably not run on V7 systems that don't have a non-blocking read,\nor on machines with a small address space like the PDP-11.  Caveat Emptor.\n\nPlease read all the directions below before you proceed any further, and\nthen follow them carefully.  Failure to do so may void your warranty. :-)\n\nAfter you have unpacked your kit, you should have all the files listed\nin MANIFEST.\n\n\t\t\t    IMPORTANT\n\nYou must choose the uid that you want warp to run under, since warp runs\nsetuid to protect its files.  Choose a uid (not root) that is used only\nby trustworthy persons.  If you do your make install as root, the installed\nversion will be chowned to this uid.  Otherwise, you should login to your\nselected uid before proceeding.  The Configure script will ask you which\nuid you want warp to run under.\n\nInstallation\n\n1)  Run Configure.  This will figure out various things about your system.\n    Some things Configure will figure out for itself, other things it will\n    ask you about.  It will then proceed to make config.h, config.sh, and\n    Makefile.\n\n    You might possibly have to trim # comments from the front of Configure\n    if your sh doesn't handle them, but all other # comments will be taken\n    care of.\n\n    (If you don't have sh, you'll have to copy the sample file config.H to\n    config.h and edit the config.h to reflect your system's peculiarities.)\n\n2)  Glance through config.h to make sure system dependencies are correct.\n    Most of them should have been taken care of by running the Configure script.\n\n    If you have any additional changes to make to the C definitions, they\n    can be done in the Makefile, or in config.h.  Bear in mind that they will\n    get undone next time you run Configure.\n\n3)  make depend\n\n    This will look for all the includes and modify Makefile accordingly.\n    Configure will offer to do this for you.\n\n4)  make\n\n    This will attempt to make warp in the current directory.\n\n5)  make install\n\n    This will put warp into a public directory (normally /usr/games).\n    It will also try to put the man pages in a reasonable place.  It will not\n    nroff the man page, however.  You may need to be root to do this.  If\n    you are not root, you must own the directories in question and you should\n    ignore any messages about chown not working.\n\n6)  Read the manual entry before running warp.\n\n7)  Feel free to edit warp.news.\n\n8)  IMPORTANT!  Help save the world!  Communicate any problems and\n    suggested patches to me, lwall@sdcrdcf.UUCP (Larry Wall), so we can\n    keep the world in sync.  If you have a problem, there's someone else\n    out there who either has had or will have the same problem.\n\n    If possible, send in patches such that the patch program will apply them.\n    Context diffs are the best, then normal diffs.  Don't send ed scripts--\n    I've probably changed my copy since the version you have.\n\n    Watch for warp patches in comp.sources.bugs.  Patches will generally be\n    in a form usable by the patch program.  If you are just now bringing up\n    warp and aren't sure how many patches there are, write to me and I'll\n    send any you don't have.  Your current patch level is shown in patchlevel.h.\n\n\nNEW FEATURES IN THIS RELEASE\n\nUses a Configure script for greater portability.\nSpace Amoebas!!!\nPirates\nFriendly Freighters\nHarry Mudd\nDamage\nKeyboard mapping\n"
  },
  {
    "path": "games/warp/bang.c",
    "content": "/* $Header: bang.c,v 7.0.1.3 86/12/12 16:57:00 lwall Exp $ */\n\n/* $Log:\tbang.c,v $\n * Revision 7.0.1.3  86/12/12  16:57:00  lwall\n * Made circular explosions.\n *\n * Revision 7.0.1.2  86/10/20  14:36:02  lwall\n * Picked some lint.\n *\n * Revision 7.0.1.1  86/10/16  10:49:45  lwall\n * Added Damage.  Fixed random bugs.\n *\n * Revision 7.0  86/10/08  15:11:57  lwall\n * Split into separate files.  Added amoebas and pirates.\n *\n */\n\n#include \"EXTERN.h\"\n#include \"warp.h\"\n#include \"object.h\"\n#include \"move.h\"\n#include \"sig.h\"\n#include \"term.h\"\n#include \"them.h\"\n#include \"INTERN.h\"\n#include \"bang.h\"\n\nvoid\nbang_init()\n{\n    ;\n}\n\nvoid\nmake_plink(y,x)\nregister int x;\nregister int y;\n{\n    register OBJECT *obj;\n\n    move(y+1,x*2,0);\n    beg_qwrite();\n    *filler = '@';\n    qwrite();\n    obj = occupant[y][x];\n    if (obj) {\n\tif (numamoebas && obj->image == ' ')\n\t    qaddc(amb[y][x]);\n\telse\n\t    qaddc(obj->image);\n    }\n    else if (numamoebas)\n\tqaddc(amb[y][x]);\n    else\n\tqaddspace();\n    end_qwrite();\n}\n\nvoid\nmake_blast(y,x,mass,size)\nregister int x;\nregister int y;\nint size;\nlong mass;\n{\n    bangy[nxtbang] = y;\n    bangx[nxtbang] = x;\n    bangm[nxtbang] = mass;\n    bangs[nxtbang++] = size;\n    assert(nxtbang <= XSIZE * YSIZE);\n    if (numamoebas && amb[y][x] == '~') {\n\tif (mass > 10000)\n\t    modify_amoeba(y,x,1,'~', 10);\n\telse if (mass > 100)\n\t    modify_amoeba(y,x,1,'~', 5);\n\tbangs[nxtbang-1] = 0;\t\t/* don't propagate */\n\treturn;\n    }\n    else if (mass >= 0) {\n\tregister OBJECT *obj;\n\n\tmove(y+1,x*2,0);\n\tbeg_qwrite();\n\t*filler = '@';\n\tqwrite();\n\t*filler = '#';\n\tqwrite();\n\t*filler = '@';\n\tqwrite();\n\t*filler = '#';\n\tqwrite();\n\t*filler = '@';\n\tqwrite();\n\tobj = occupant[y][x];\n\tif (obj) {\n\t    if (numamoebas && obj->image == ' ')\n\t\tqaddc(amb[y][x]);\n\t    else\n\t\tqaddc(obj->image);\n\t}\n\telse if (numamoebas)\n\t    qaddc(amb[y][x]);\n\telse\n\t    qaddspace();\n\tend_qwrite();\n    }\n}\n\nvoid\ndo_bangs()\n{\n    register int x;\n    register int y;\n    register int i;\n    register int j;\n    register int k;\n    register int lastxy;\n    register OBJECT *obj;\n\n    /* read blast list and update blast array */\n    assert(nxtbang >= 0 && nxtbang <= XSIZE * YSIZE);\n    for (i=0; i<nxtbang; i++) {\n\tif (bangm[i] != 32767)\n\t    bangm[i] *= 4;\n\tlastxy = bangs[i] << 1;\n\tif (lastxy >= MAXBDIST)\n\t    lastxy = MAXBDIST - 1;\n\tfor (y=bangy[i]-bangs[i],x=bangx[i]-bangs[i],j=lastxy;\n\t  j>=0;\n\t  y++,x++,--j) {\n\t    yblasted[yy[j] = (y+YSIZE00) % YSIZE] |= 1;\n\t    xblasted[xx[j] = (x+XSIZE00) % XSIZE] |= 1;\n\t}\n\tblasted = TRUE;\n\tfor (y=lastxy;y>=0;--y) {\n\t    for (x=lastxy;x>=0;--x) {\n\t\tif (lastxy > 2) {\n\t\t    j = abs(y-bangs[i]);\n\t\t    k = abs(x-bangs[i]);\n\t\t    if (j < k)\t\t/* distance is long + 1/2 short */\n\t\t\tj += k + k;\n\t\t    else\n\t\t\tj += j + k;\n\t\t    if (--j > lastxy)\n\t\t\tcontinue;\n\t\t}\n\t\tif (bangm[i] != 32767 ||\n\t\t  !(obj=occupant[yy[y]][xx[x]]) || obj->type != Web)\n\t\t    blast[yy[y]][xx[x]] += bangm[i];\n\t    }\n\t}\n    }\n}\n"
  },
  {
    "path": "games/warp/bang.h",
    "content": "/* $Header: bang.h,v 7.0 86/10/08 15:12:03 lwall Exp $ */\n\n/* $Log:\tbang.h,v $\n * Revision 7.0  86/10/08  15:12:03  lwall\n * Split into separate files.  Added amoebas and pirates.\n * \n */\n\nEXT long blast[YSIZE][XSIZE];\nEXT bool blasted;\nEXT bool xblasted[XSIZE];\nEXT bool yblasted[YSIZE];\n\nEXT char bangy[YSIZE*XSIZE];\nEXT char bangx[YSIZE*XSIZE];\nEXT char bangs[YSIZE*XSIZE];\n\nEXT long bangm[YSIZE*XSIZE];\n\n#define MAXBDIST 40\nEXT int xx[MAXBDIST];\nEXT int yy[MAXBDIST];\n\nEXT int nxtbang;\nEXT bool banging;\n\nvoid make_plink();\nvoid make_blast();\nvoid do_bangs();\nvoid bang_init();\n"
  },
  {
    "path": "games/warp/init.c",
    "content": "/* $Header: init.c,v 7.0.1.4 86/12/12 16:58:03 lwall Exp $ */\n\n/* $Log:\tinit.c,v $\n * Revision 7.0.1.4  86/12/12  16:58:03  lwall\n * Baseline for net release.\n *\n * Revision 7.0.1.3  86/10/20  14:35:31  lwall\n * Picked some lint.\n *\n * Revision 7.0.1.2  86/10/17  15:53:30  lwall\n * Added random walk star fields.\n *\n * Revision 7.0.1.1  86/10/16  10:51:19  lwall\n * Added Damage.  Fixed random bugs.\n *\n * Revision 7.0  86/10/08  15:12:10  lwall\n * Split into separate files.  Added amoebas and pirates.\n *\n */\n\n#include \"EXTERN.h\"\n#include \"warp.h\"\n#include \"bang.h\"\n#include \"object.h\"\n#include \"move.h\"\n#include \"play.h\"\n#include \"score.h\"\n#include \"term.h\"\n#include \"them.h\"\n#include \"us.h\"\n#include \"util.h\"\n#include \"weapon.h\"\n#include \"INTERN.h\"\n#include \"init.h\"\n\nvoid\ninitialize()\n{\n    register int i;\n    register int x;\n    register int y;\n    register int dist;\n    register int ydist;\n    register int xdist;\n    long e;\n    int yoff, xoff, ypred, xpred;\n    register OBJECT *obj;\n    char ch;\n    FILE *mapfp = NULL;\n    bool tmptholspec;\n    int inhabjackpot;\n    long inhenergy;\n    int walksplit = 200;\n    static char *distname[] =\n\t{\" #\",\" -\",\" \\\\\",\" /\",\n\t \" |\",\" *\",\" `\",\" '\"};\n\n    cloaking = madgorns = FALSE;\n    deados = madfriends = 0;\n    curscore = possiblescore = 0L;\n    yamblast = xamblast = ambsize = 0;\n    if (smarts > 90)\n\tmassacre = TRUE;\n    scandist = (massacre?20:15);\n    antibase = (smarts>60?1:(smarts>40?2:(smarts>25?4:100)));\n    sm35 = (smarts>35?35:smarts);\n    sm45 = (smarts>45?45:smarts);\n    sm50 = (smarts>50?50:smarts);\n    sm55 = (smarts>55?55:smarts);\n    sm80 = (smarts>80?80:smarts);\n    sm95 = (smarts>95?95:smarts);\n    super = (smarts>50?smarts-50:0);\n    enemshields = 10 + super/2;\t\t/* (scaled by 10) 1 @ 50 .. 3 @ 90 */\n    if (smarts>90)\n\tenemshields += (smarts-90)*10;\t/* lay it on thick: ~13 @ 99 */\n    entmax = (smarts>=75?5000:(smarts>=50?4000:(smarts>=40?3000:2000)));\n    basemax = (smarts>=75?20000:(smarts>=50?15000:(smarts>=40?12500:10000)));\n\n    clear();\n    while (root.next != &root) {\n\troot.next = root.next->next;\n\tfree_object(root.next->prev);\n    }\n    root.prev = &root;\n    enemies = movers = NULL;\n    numos = numxes = 0;\n    for (y=0;y<YSIZE;y++)\n\tfor (x=0;x<XSIZE;x++) {\n\t    occupant[y][x] = 0;\n\t    blast[y][x] = 0;\n\t    amb[y][x] = ' ';\n\t}\n    for (y=0; y<YSIZE; y++)\n\tyblasted[y] = 0;\n    for (x=0; x<XSIZE; x++)\n\txblasted[x] = 0;\n    blasted = FALSE;\n    if (!starspec)\n\tif (smarts < 15)\n\t    inumstars = 50 + rand_mod(50);\n\telse if (smarts < 50 || smarts > 85)\n\t    inumstars = exdis(800) + rand_mod(100) + 1;\n\telse /* too few stars makes 50..85 too hard */\n\t    inumstars = exdis(700) + rand_mod(150-super*2) + 50+super*2;\n    tmptholspec = (smarts > 15 && inumstars < 450 && ! rand_mod(90-sm80));\n    if (!klingspec) {\n\tinumenemies = rand_mod((smarts+1)/2) + 1;\n\tif (massacre || tmptholspec)\n\t    inumenemies += 10;\n    }\n    if (!friendspec)\n\tinumfriends = rand_mod(smarts/8+1);\n    if (!piratespec)\n\tinumpirates = rand_mod(inumfriends/2+1);\n    if (inumfriends+inumenemies+inumstars > YSIZE*XSIZE-20)\n\tinumstars = YSIZE*XSIZE-20 - inumenemies - inumfriends;\n    if (inumstars < 0) {\n\tinumfriends += inumstars;\n\tinumstars = 0;\n    }\n    if (inumfriends < 0) {\n\tinumenemies += inumfriends;\n\tinumfriends = 0;\n    }\n    if (inumenemies < 0)\n\tinumenemies = 0;\n    numstars = inumstars;\n    inuminhab = numinhab = 0;\n    inumroms = inumthols = inumgorns = 0;\n    numapollos = apolspec || massacre ? 1 :\n       ((!numstars || rand_mod(2) || smarts < 10) ? 0 : 1);\n    inumapollos = apolloflag = 0;\n    realapollo = NULL;\n    inumcrushes = numcrushes =\n\tcrushspec||massacre?1:(rand_mod(2000) < inumstars);\n    inumenemies += inumcrushes;\n    inumamoebas = numamoebas = (amoebaspec ? 1 :\n\t!rand_mod(inumcrushes?3-massacre:8) );\t/* < and & are fun together */\n    inumenemies += inumamoebas;\n    if (!rand_mod(40)) {\n\tinhabjackpot = 32767;\n\tinumfriends += rand_mod(10);\n\tinumpirates += rand_mod(10);\n    }\n    else\n\tinhabjackpot = inumpirates;\n    inhenergy = 30000-super*150;\n    if (!rand_mod(10))\n\tinhenergy = 50000;\n    if (!rand_mod(4))\n\tinhenergy += rand_mod(3500+super*150);\n    numfriends = inumfriends;\n    numpirates = inumpirates;\n    numenemies = inumenemies;\n    deadmudds = 0;\n\n    /* do stars */\n\nstars_again:\n    if (prespec)\n\tdist = 4;\n    else if (numstars > 750)\n\tdist = 0;\n    else\n\tdist = rand_mod(starspec||smarts<=5?3:5);\n    if (debugging) {\n\treal_y = real_x = -100;\n\tprintf(\"\\r\\n\");\n    }\n    switch (dist) {\n    case 0:\t\t\t\t/* uniform random */\n\tydist = xdist = 0;\n\tif (inumstars < 700 && !rand_mod(3-(inumstars<50))) {\n\t    ydist = xdist = 6;\t\t/* well, maybe not so random */\n\t    y = rand_mod(YSIZE);\n\t    x = rand_mod(XSIZE);\n\t    if (rand_mod(2))\n\t\twalksplit = inumstars/(exdis(40)+1);\n\t}\n\tif (debugging)\n\t    printf(\" R\\r\\n\");\n\tbreak;\n    case 1: case 2:\t/* clumped, maybe skewed, maybe superposed */\n\tydist = rand_mod(4);\n\txdist = rand_mod(2);\n\tif (debugging)\n\t    printf(\"%s\\r\\n\",distname[ydist+4*xdist]);\n\tyoff = rand_mod(YSIZE);\n\txoff = rand_mod(XSIZE);\n\tif (dist == 2)\n\t    dist = numstars/2 + exdis(numstars/2) - exdis(numstars/2);\n\telse\n\t    dist = 0;\n\tbreak;\n    case 3: case 4:\t\t\t/* predefined or residual */\n      scenario_again:\n\tif (debugging)\n\t    printf(\" P\\r\\n\");\n\tdist = 0;\n\tSprintf(spbuf,\"smap.%d\",\n\t    (prescene>=0?prescene:rand_mod(MAPS)) );\n\tif ((mapfp = fopen(spbuf,\"r\")) != NULL &&\n\t    fgets(spbuf,10,mapfp) != NULL ) {\n\t    inumstars = numstars = atoi(spbuf);\n\t    if (inumenemies+inumstars > YSIZE*XSIZE-20)\n\t\tinumstars = numstars = YSIZE*XSIZE-20 - inumenemies;\n\t    ydist = rand_mod(2) + 4;\t/* flip y axis? */\n\t    xdist = rand_mod(2) + 4;\t/* flip x axis? */\n\t    yoff = rand_mod(YSIZE);\t/* how much to shift y */\n\t    xoff = rand_mod(XSIZE);\t/* how much to shift x */\n\t}\n\telse {\n\t    prespec = FALSE;\n\t    prescene = -1;\n\t    if (rand_mod(2))\n\t\tgoto scenario_again;\n\t    goto stars_again;\n\t}\n\tbreak;\n    }\n    for (i = 1; i <= numstars; i++) {\n\tif (dist && i == dist) {\t/* flip to another skewing? */\n\t    ydist = rand_mod(4);\n\t    xdist = rand_mod(2);\n\t    if (!rand_mod(4)) {\n\t\tydist = xdist = 6;\n\t\tif (debugging)\n\t\t    printf(\"&\\r\\n\");\n\t    }\n\t    else if (debugging)\n\t\tprintf(\"%s\\r\\n\",distname[ydist+4*xdist]);\n\t    yoff = rand_mod(YSIZE);\n\t    xoff = rand_mod(XSIZE);\n\t    dist = 0;\n\t}\n\tdo {\t\t\t\t/* until an open spot found */\n\t    switch (xdist) {\n\t    case 0:\n\t\tx = rand_mod(XSIZE);\t/* pick from 0..39, uniform */\n\t\tbreak;\n\t    case 1: case 2: case 3:\n\t\tx = (int)((((double)(myrand()-HALFRAND)) *\n\t\t           ((double)(myrand()-HALFRAND))/RANDRAND)\n\t\t\t  * 20.0) + xoff;\t/* pick from -20..20, clumped */\n\t\tbreak;\n\t    case 4:\n\t\tif (fscanf(mapfp,\"%d %d\\n\",&ypred,&xpred) == EOF)\n\t\t    ydist = xdist = 0;\n\t\tx = xpred + xoff;\n\t\tbreak;\n\t    case 5:\n\t\tif (fscanf(mapfp,\"%d %d\\n\",&ypred,&xpred) == EOF)\n\t\t    ydist = xdist = 0;\n\t\tx = -xpred + xoff;\n\t\tbreak;\n\t    case 6:\n\t\tx += rand_mod(3) - 1;\n\t\tbreak;\n\t    }\n\t    switch (ydist) {\n\t    case 0:\n\t\ty = rand_mod(YSIZE);\n\t\tbreak;\n\t    case 1:\n\t\ty = (int)((((double)(myrand()-HALFRAND)) *\n\t\t           ((double)(myrand()-HALFRAND))/RANDRAND)\n\t\t\t  * 12.0) + yoff;\t/* pick from -12..12, clumped */\n\t\tbreak;\n\t    case 2:\n\t\ty = (int)((((double)(myrand()-HALFRAND)) *\n\t\t           ((double)(myrand()-HALFRAND))/RANDRAND)\n\t\t\t  * 12.0) + yoff + x*YSIZE/XSIZE;\n\t\t\t\t \t\t/* clumped & skewed */\n\t\tbreak;\n\t    case 3:\n\t\ty = (int)((((double)(myrand()-HALFRAND)) *\n\t\t           ((double)(myrand()-HALFRAND))/RANDRAND)\n\t\t\t  * 12.0) + yoff - x*YSIZE/XSIZE;\n\t\t\t\t\t\t/* clumped & skewed */\n\t\tbreak;\n\t    case 4:\n\t\ty = ypred + yoff;\n\t\tbreak;\n\t    case 5:\n\t\ty = -ypred + yoff;\n\t\tbreak;\n\t    case 6:\n\t\ty += rand_mod(3) - 1;\n\t\tif (!rand_mod(walksplit)) {\n\t\t    y = rand_mod(YSIZE);\n\t\t    x = rand_mod(XSIZE);\n\t\t}\n\t\tbreak;\n\t    }\n\t    while (x<0) x += XSIZE00;\n\t    while (y<0) y += YSIZE00;\n\t    x %= XSIZE;\n\t    y %= YSIZE;\n\t} while (occupant[y][x]);\n\te = rand_mod(32768);\n\tif (--inhabjackpot > 0 || e >= inhenergy) {\n\t    ch = '@';\n\t    if (inhabjackpot && e < 10000)\n\t\te += 10000;\n\t    inuminhab = ++numinhab;\n\t}\n\telse {\n\t    ch = '*';\n\t}\n\tobj = make_object(Star,ch,y,x,0,0,e+rand_mod(super*100+1),e/4,&root);\n\tobj->flags |= STATIC;\n    }\n    if (inumstars > 30 && inhabjackpot <= 0 &&\n\t !rand_mod(3 - (inumstars > 400) - (inhenergy > 32768)) ) {\n\tint initx;\n\tint inity;\n\n\tx = initx = obj->posx;\n\ty = inity = obj->posy;\n\twhile (rand_mod(2) && inuminhab < inumstars/2) {\n\t    for (i=rand_mod(smarts)*2+20; i; i--) {\n\t\tif ((obj = occupant[y][x]) && obj->image == '*') {\n\t\t    setimage(obj,'@');\n\t\t    if (obj->energy < 10000)\n\t\t\tobj->energy += 20000; /* the benefits of civilization */\n\t\t    inuminhab = ++numinhab;\n\t\t}\n\t\tif (i&15) {\n\t\t    y = (y + rand_mod(3) + YSIZE99) % YSIZE;\n\t\t    x = (x + rand_mod(3) + XSIZE99) % XSIZE;\n\t\t}\n\t\telse {\t\t\t/* don't wander too far */\n\t\t    y = inity;\n\t\t    x = initx;\n\t\t}\n\t    }\n\t    x = initx = rand_mod(XSIZE);\n\t    y = inity = rand_mod(YSIZE);\n\t}\n    }\n    if (mapfp != NULL)\n\tFclose(mapfp);\n    if (numcrushes) {\n\tdo {\n\t    x = rand_mod(XSIZE);\n\t    y = rand_mod(YSIZE);\n\t} while (occupant[y][x]);\n\tmovers = make_object(Crusher,'<',y,x,0,1,32767L,32768L,&root);\n\tpossiblescore += 10000;\n    }\n    ient = (numents != 0);\n    if (ient) {\n\tdo {\n\t    x = rand_mod(XSIZE);\n\t    y = rand_mod(YSIZE);\n\t} while (occupant[y][x]);\n\te = entmax;\n\tent = make_object(Enterprise,'E',y,x,0,0,e,e/2,&root);\n\tif (!movers)\n\t    movers = ent;\n    }\n    ibase = (numbases != 0);\n    if (ibase) {\n\te = 52-super;\n\tdo {\n\t    x = rand_mod(XSIZE);\n\t    y = rand_mod(YSIZE);\n\t} while (occupant[y][x] || lookaround(y,x,Star) * 7 < e--);\n\te = basemax;\n\tbase = make_object(Base, 'B',y,x,0,0,e,e/4,&root);\n\tif (!movers)\n\t    movers = base;\n    }\n    if (numamoebas) {\n\tdo {\n\t    x = rand_mod(XSIZE);\n\t    y = rand_mod(YSIZE);\n\t} while (occupant[y][x]);\n\tnuke = make_object(Enemy,'&',y,x,0,0,32767L,\n\t  (long)entmax+entmax+rand_mod(entmax),&root);\n\tpossiblescore += 10000;\n\tamb[y][x] = '~';\n\tif (rand_mod(2))\n\t    modify_amoeba(y,x,2,'~',(int)rand_mod(smarts<<1));/* just make blob */\n\telse {\n\t    for (i=smarts/10+1; i; i--) {\n\t\tnuke->strategy = rand_mod(256);\t\t/* random direction */\n\t\tmodify_amoeba(y,x,2,'~',(int)rand_mod(5));\n\t\tmodify_amoeba(y,x,2,'~',(int)rand_mod(5));\n\t\tmodify_amoeba(y,x,2,'~',(int)rand_mod(5));\n\t\tmodify_amoeba(y,x,2,'~',(int)rand_mod(5));\t/* extend pseudopod */\n\t    }\n\t}\n\tif (!enemies)\n\t    enemies = nuke;\n\tif (!movers)\n\t    movers = nuke;\n    }\n    if (rand_mod(27-sm50/2) && !romspec && !gornspec)\n\tdist = 27-sm50/2;\n    else\n\tdist = rand_mod(4) + 1;\n    for (i = 1+inumcrushes+inumamoebas; i <= numenemies; i++) {\n\tdo {\n\t    x = rand_mod(XSIZE);\n\t    y = rand_mod(YSIZE);\n\t} while (occupant[y][x]);\n\tif (rand_mod(dist)) {\n\t    if (!tholspec && !tmptholspec && rand_mod((inumstars*3)/sm50+2))\n\t\tch = 'K';\n\t    else {\n\t\tch = 'T';\n\t\tinumthols++;\n\t    }\n\t}\n\telse {\n\t    if (romspec == gornspec)\n\t\te = 50;\n\t    else if (gornspec)\n\t\te = 10;\n\t    else\n\t\te = 90;\n\t    if (rand_mod(100) < e) {\n\t\tch = 'R';\n\t\tinumroms++;\n\t    }\n\t    else {\n\t\tch = 'G';\n\t\tinumgorns++;\n\t    }\n\t}\n\tif (possiblescore > ENTBOUNDARY - 10000)\n\t    e = (ENTBOUNDARY - possiblescore) / 5;\n\telse\n\t    e = 250 + (sm50-1) * 30 * 20 / numenemies+1;\n\te = exdis((int)e) + e - exdis((int)e);\n\tobj = make_object(Enemy,ch,y,x,0,0,\n\t    e + rand_mod(super*200+2) + 10000*massacre,e/4,&root);\n\te /= 4;\n\tswitch (ch) {\n\tcase 'K':\n\t    possiblescore += e;\n\t    break;\n\tcase 'T':\n\t    possiblescore += e*3/2;\n\t    break;\n\tcase 'G':\n\t    possiblescore += e*2;\n\t    break;\n\tcase 'R':\n\t    possiblescore += e*3;\n\t    obj->flags |= CLOAKS;\n\t    break;\n\t}\n\tif (!enemies)\n\t    enemies = obj;\n\tif (!movers)\n\t    movers = obj;\n    }\n    numgorns = inumgorns;\n    for (i=0; i<numfriends; i++) {\n\tdo {\n\t    x = rand_mod(XSIZE);\n\t    y = rand_mod(YSIZE);\n\t} while (occupant[y][x]);\n\te = 250 + (sm50-1) * 30 * 20 / numenemies+1;\n\te = exdis((int)e) + e - exdis((int)e);\n\t{\n\t    static char let[] = \"QWYUISDHJLZVMFFFFFFFFF\";\n\n\t    dist = rand_mod(20);\n\t    ch = let[dist];\n\t}\t\t/* grr, venix doesn't like indexing into string */\n\tobj = make_object(Enemy,ch,y,x,0,0,\n\t    e + rand_mod(super*200+2),e/4,&root);\n\tif (numpirates-- > 0) {\n\t    obj->flags |= PIRATE;\n\t    if (smarts >= 20 && !rand_mod(10-smarts/10))\n\t\tobj->flags |= CLOAKS;\n\t}\n\tobj->flags |= FRIENDLY;\n\tif (!enemies)\n\t    enemies = obj;\n\tif (!movers)\n\t    movers = obj;\n    }\n    if (!movers)\n\tmovers = &root;\n    if (!enemies)\n\tenemies = &root;\n    if (ent)\n\tmvaddch(ent->posy+1, ent->posx*2, ent->image);\n    if (base)\n\tmvaddch(base->posy+1, base->posx*2, base->image);\n    sleep(2);\n    {\n\tregister OBJECT *curobj;\n\n\tfor (curobj = root.next; curobj != &root; curobj = curobj->next) {\n\t    mvaddch(curobj->posy+1, curobj->posx*2, curobj->image);\n\t}\n    }\n\n    for (i=0;i<2;i++) for (y=0;y<3;y++) for (x=0;x<3;x++)\n    isatorp[i][y][x]=0;\n\n    whenok = 0;\n    timer = 0;\n    finish = 0;\n    bombed_out = FALSE;\n    if (ent)\n\tentmode = status = 0;\n    else\n\tif (base)\n\t    status = 2;\n\telse\n\t    status = 3;\n\n    Sprintf(spbuf,\n    \"%-4s E: %4d %2d B: %5d %3d Enemies: %-3d Stars: %-3d Stardate%5d.%1d %9ld\",\n\t\"   \", 0, 0, 0, 0, 0, 0, smarts * 100, 0, 0L);\n    mvaddstr(0,0,spbuf);\n    oldeenergy = oldbenergy = oldcurscore =\n    oldstatus = oldetorp = oldbtorp = oldstrs = oldenemies = -1;\n\t\t\t\t\t/* force everything to fill in */\n    damage = olddamage = 0;\n    for (i=0; i<MAXDAMAGE; i++)\n\tdamflag[i] = 0;\n    btorp = 500;\n    etorp = 50;\n}\n"
  },
  {
    "path": "games/warp/init.h",
    "content": "/* $Header: init.h,v 7.0 86/10/08 15:12:17 lwall Exp $ */\n\n/* $Log:\tinit.h,v $\n * Revision 7.0  86/10/08  15:12:17  lwall\n * Split into separate files.  Added amoebas and pirates.\n * \n */\n\nvoid initialize();\n"
  },
  {
    "path": "games/warp/intrp.c",
    "content": "/* $Header: /usr/src/games/warp/RCS/intrp.c,v 1.3.2 97/10/2 22:40:37 games Exp $\n *\n * $Log:\tintrp.c,v $\n * Revision 7.0.2  93/12/31  23:40:37  games\n * Removed shortnames.h for new version of 2.11BSD\n *\n * Revision 7.0.1.2a  87/07/03  00:56:37  games\n * Included shortnames.h for 2.10BSD\n *\n * Revision 7.0.1.2  86/12/12  16:59:04  lwall\n * Baseline for net release.\n *\n * Revision 7.0.1.1  86/10/16  10:51:43  lwall\n * Added Damage.  Fixed random bugs.\n *\n * Revision 7.0  86/10/08  15:12:19  lwall\n * Split into separate files.  Added amoebas and pirates.\n *\n */\n\n#include \"EXTERN.h\"\n#include \"warp.h\"\n#include \"sig.h\"\n#include \"util.h\"\n#include \"term.h\"\n#include \"INTERN.h\"\n#include \"intrp.h\"\n#include <unistd.h>\n#include <sys/utsname.h>\n\n/* name of this host */\nstruct utsname uts;\n\n#ifdef TILDENAME\nstatic char *tildename = Nullch;\nstatic char *tildedir = Nullch;\n#endif\n\nchar *dointerp();\nchar *getrealname();\n#ifdef CONDSUB\nchar *skipinterp();\n#endif\n\nstatic void abort_interp();\n\nvoid\nintrp_init(tcbuf)\nchar *tcbuf;\n{\n\n    /* get environmental stuff */\n\n    /* get home directory */\n\n    homedir = getenv(\"HOME\");\n    if (homedir == Nullch)\n\thomedir = getenv(\"LOGDIR\");\n\n    dotdir = getval(\"DOTDIR\",homedir);\n\n    /* get login name */\n\n    logname = getenv(\"USER\");\n    if (logname == Nullch)\n\tlogname = getenv(\"LOGNAME\");\n#ifdef GETLOGIN\n    if (logname == Nullch)\n\tlogname = savestr(getlogin());\n#endif\n\n    /* get the real name of the person (%N) */\n    /* Must be done after logname is read in */\n\n    strcpy(tcbuf,getrealname(getuid()));\n    realname = savestr(tcbuf);\n\n    /* name of this host (%H) */\n    /* get sysname */\n    uname(&uts);\n    hostname = savestr(uts.nodename);\n\n    warplib = savestr(filexp(WARPLIB));\n\n    if (scorespec)\t\t\t/* that getwd below takes ~1/3 sec. */\n\treturn;\t\t\t\t/* and we do not need it for -s */\n    if (! getwd(tcbuf)) {               /* find working directory name */\n        perror(\"getcwd\");\n        exit(1);\n    }\n    origdir = savestr(tcbuf);\t\t/* and remember it */\n}\n\n/* expand filename via %, ~, and $ interpretation */\n/* returns pointer to static area */\n/* Note that there is a 1-deep cache of ~name interpretation */\n\nchar *\nfilexp(s)\nregister char *s;\n{\n    static char filename[CBUFLEN];\n    char scrbuf[CBUFLEN];\n    register char *d;\n\n#ifdef DEBUGGING\n    if (debug & DEB_FILEXP)\n\tprintf(\"< %s\\r\\n\",s);\n#endif\n    interp(filename, (sizeof filename), s);\t\t\t/* interpret any % escapes */\n#ifdef DEBUGGING\n    if (debug & DEB_FILEXP)\n\tprintf(\"%% %s\\r\\n\",filename);\n#endif\n    s = filename;\n    if (*s == '~') {\t/* does destination start with ~? */\n\tif (!*(++s) || *s == '/') {\n\t    Sprintf(scrbuf,\"%s%s\",homedir,s);\n\t\t\t\t/* swap $HOME for it */\n#ifdef DEBUGGING\n    if (debug & DEB_FILEXP)\n\tprintf(\"~ %s\\r\\n\",scrbuf);\n#endif\n\t    strcpy(filename,scrbuf);\n\t}\n\telse {\n#ifdef TILDENAME\n\t    for (d=scrbuf; isalnum(*s); s++,d++)\n\t\t*d = *s;\n\t    *d = '\\0';\n\t    if (tildedir && strEQ(tildename,scrbuf)) {\n\t\tstrcpy(scrbuf,tildedir);\n\t\tstrcat(scrbuf, s);\n\t\tstrcpy(filename, scrbuf);\n#ifdef DEBUGGING\n\t\tif (debug & DEB_FILEXP)\n\t\t    printf(\"r %s %s\\r\\n\",tildename,tildedir);\n#endif\n\t    }\n\t    else {\n\t\tif (tildename) {\n\t\t    free(tildename);\n\t\t    free(tildedir);\n\t\t}\n\t\ttildedir = Nullch;\n\t\ttildename = savestr(scrbuf);\n\t\t{\n\t\t    struct passwd *pwd = getpwnam(tildename);\n\n\t\t    Sprintf(scrbuf,\"%s%s\",pwd->pw_dir,s);\n\t\t    tildedir = savestr(pwd->pw_dir);\n\t\t    strcpy(filename,scrbuf);\n\t\t    endpwent();\n\t\t}\n\t    }\n#else /* !TILDENAME */\n#ifdef VERBOSE\n\t    IF(verbose)\n\t\tfputs(\"~loginname not implemented.\\r\\n\",stdout);\n\t    ELSE\n#endif\n#ifdef TERSE\n\t\tfputs(\"~login not impl.\\r\\n\",stdout);\n#endif\n#endif\n\t}\n    }\n    else if (*s == '$') {\t/* starts with some env variable? */\n\td = scrbuf;\n\t*d++ = '%';\n\tif (s[1] == '{')\n\t    strcpy(d,s+2);\n\telse {\n\t    *d++ = '{';\n\t    for (s++; isalnum(*s); s++) *d++ = *s;\n\t\t\t\t/* skip over token */\n\t    *d++ = '}';\n\t    strcpy(d,s);\n\t}\n#ifdef DEBUGGING\n\tif (debug & DEB_FILEXP)\n\t    printf(\"$ %s\\r\\n\",scrbuf);\n#endif\n\tinterp(filename, (sizeof filename), scrbuf);\n\t\t\t\t\t/* this might do some extra '%'s but */\n\t\t\t\t\t/* that is how the Mercedes Benz */\n    }\n#ifdef DEBUGGING\n    if (debug & DEB_FILEXP)\n\tprintf(\"> %s\\r\\n\",filename);\n#endif\n    return filename;\n}\n\n#ifdef CONDSUB\n/* skip interpolations */\n\nchar *\nskipinterp(pattern,stoppers)\nregister char *pattern;\nchar *stoppers;\n{\n\n    while (*pattern && (!stoppers || !strchr(stoppers,*pattern))) {\n#ifdef DEBUGGING\n\tif (debug & 8)\n\t    printf(\"skipinterp till %s at %s\\r\\n\",stoppers?stoppers:\"\",pattern);\n#endif\n\tif (*pattern == '%' && pattern[1]) {\n\t    switch (*++pattern) {\n\t    case '{':\n\t\tfor (pattern++; *pattern && *pattern != '}'; pattern++)\n\t\t    if (*pattern == '\\\\')\n\t\t\tpattern++;\n\t\tbreak;\n#ifdef CONDSUB\n\t    case '(': {\n\t\tpattern = skipinterp(pattern+1,\"!=\");\n\t\tif (!*pattern)\n\t\t    goto getout;\n\t\tfor (pattern++; *pattern && *pattern != '?'; pattern++)\n\t\t    if (*pattern == '\\\\')\n\t\t\tpattern++;\n\t\tif (!*pattern)\n\t\t    goto getout;\n\t\tpattern = skipinterp(pattern+1,\":)\");\n\t\tif (*pattern == ':')\n\t\t    pattern = skipinterp(pattern+1,\")\");\n\t\tbreak;\n\t    }\n#endif\n#ifdef BACKTICK\n\t    case '`': {\n\t\tpattern = skipinterp(pattern+1,\"`\");\n\t\tbreak;\n\t    }\n#endif\n#ifdef PROMPTTTY\n\t    case '\"':\n\t\tpattern = skipinterp(pattern+1,\"\\\"\");\n\t\tbreak;\n#endif\n\t    default:\n\t\tbreak;\n\t    }\n\t    pattern++;\n\t}\n\telse {\n\t    if (*pattern == '^' && pattern[1])\n\t\tpattern += 2;\n\t    else if (*pattern == '\\\\' && pattern[1])\n\t\tpattern += 2;\n\t    else\n\t\tpattern++;\n\t}\n    }\ngetout:\n    return pattern;\t\t\t/* where we left off */\n}\n#endif\n\n/* interpret interpolations */\n\nchar *\ndointerp(dest,destsize,pattern,stoppers)\nregister char *dest;\nregister int destsize;\nregister char *pattern;\nchar *stoppers;\n{\n    register char *s;\n    register int i;\n    char scrbuf[512];\n    bool upper = FALSE;\n    bool lastcomp = FALSE;\n    int metabit = 0;\n\n    while (*pattern && (!stoppers || !strchr(stoppers,*pattern))) {\n#ifdef DEBUGGING\n\tif (debug & 8)\n\t    printf(\"dointerp till %s at %s\\r\\n\",stoppers?stoppers:\"\",pattern);\n#endif\n\tif (*pattern == '%' && pattern[1]) {\n\t    upper = FALSE;\n\t    lastcomp = FALSE;\n\t    for (s=Nullch; !s; ) {\n\t\tswitch (*++pattern) {\n\t\tcase '^':\n\t\t    upper = TRUE;\n\t\t    break;\n\t\tcase '_':\n\t\t    lastcomp = TRUE;\n\t\t    break;\n\t\tcase '{':\n\t\t    pattern = cpytill(scrbuf,pattern+1,'}');\n\t\t    if (s = strchr(scrbuf,'-'))\n\t\t\t*s++ = '\\0';\n\t\t    else\n\t\t\ts = nullstr;\n\t\t    s = getval(scrbuf,s);\n\t\t    break;\n#ifdef CONDSUB\n\t\tcase '(': {\n\t\t    char rch;\n\t\t    bool matched;\n\n\t\t    pattern = dointerp(dest,destsize,pattern+1,\"!=\");\n\t\t    rch = *pattern;\n\t\t    if (rch == '!')\n\t\t\tpattern++;\n\t\t    if (*pattern != '=')\n\t\t\tgoto getout;\n\t\t    pattern = cpytill(scrbuf,pattern+1,'?');\n\t\t    if (!*pattern)\n\t\t\tgoto getout;\n\t\t    if (*scrbuf == '^' && scrbuf[strlen(scrbuf)-1] == '$') {\n\t\t\tscrbuf[strlen(scrbuf)-1] = '\\0';\n\t\t\tmatched = strEQ(scrbuf+1,dest);\n\t\t    }\n\t\t    else\n\t\t\tmatched = instr(dest,scrbuf) != Nullch;\n\t\t    if (matched==(rch == '=')) {\n\t\t\tpattern = dointerp(dest,destsize,pattern+1,\":)\");\n\t\t\tif (*pattern == ':')\n\t\t\t    pattern = skipinterp(pattern+1,\")\");\n\t\t    }\n\t\t    else {\n\t\t\tpattern = skipinterp(pattern+1,\":)\");\n\t\t\tif (*pattern == ':')\n\t\t\t    pattern++;\n\t\t\tpattern = dointerp(dest,destsize,pattern,\")\");\n\t\t    }\n\t\t    s = dest;\n\t\t    break;\n\t\t}\n#endif\n#ifdef BACKTICK\n\t\tcase '`': {\n\t\t    FILE *pipefp, *popen();\n\n\t\t    pattern = dointerp(scrbuf,(sizeof scrbuf),pattern+1,\"`\");\n\t\t    pipefp = popen(scrbuf,\"r\");\n\t\t    if (pipefp != Nullfp) {\n\t\t\tint len;\n\n\t\t\tlen = fread(scrbuf,sizeof(char),(sizeof scrbuf)-1,\n\t\t\t    pipefp);\n\t\t\tscrbuf[len] = '\\0';\n\t\t\tpclose(pipefp);\n\t\t    }\n\t\t    else {\n\t\t\tprintf(\"\\r\\nCan't run %s\\r\\n\",scrbuf);\n\t\t\t*scrbuf = '\\0';\n\t\t    }\n\t\t    for (s=scrbuf; *s; s++) {\n\t\t\tif (*s == '\\n') {\n\t\t\t    if (s[1])\n\t\t\t\t*s = ' ';\n\t\t\t    else\n\t\t\t\t*s = '\\0';\n\t\t\t}\n\t\t    }\n\t\t    s = scrbuf;\n\t\t    break;\n\t\t}\n#endif\n#ifdef PROMPTTTY\n\t\tcase '\"':\n\t\t    pattern = dointerp(scrbuf,(sizeof scrbuf),pattern+1,\"\\\"\");\n\t\t    fputs(scrbuf,stdout);\n\t\t    resetty();\n\t\t    if (! gets(scrbuf))\n\t\t        /* ignore */;\n\t\t    crmode();\n\t\t    raw();\n\t\t    noecho();\n\t\t    nonl();\n\t\t    s = scrbuf;\n\t\t    break;\n#endif\n\t\tcase '~':\n\t\t    s = homedir;\n\t\t    break;\n\t\tcase '.':\n\t\t    s = dotdir;\n\t\t    break;\n\t\tcase '$':\n\t\t    s = scrbuf;\n\t\t    Sprintf(s,\"%d\",getpid());\n\t\t    break;\n\t\tcase 'H':\t\t\t/* host name */\n\t\t    s = hostname;\n\t\t    break;\n\t\tcase 'L':\t\t\t/* login id */\n\t\t    s = logname;\n\t\t    break;\n\t\tcase 'N':\t\t\t/* full name */\n\t\t    s = getval(\"NAME\",realname);\n\t\t    break;\n\t\tcase 'O':\n\t\t    s = origdir;\n\t\t    break;\n\t\tcase 'p':\n\t\t    s = cwd;\n\t\t    break;\n\t\tcase 'X':\t\t\t/* warp library */\n\t\t    s = warplib;\n\t\t    break;\n\t\tdefault:\n\t\t    if (--destsize <= 0)\n\t\t\tabort_interp();\n\t\t    *dest++ = *pattern | metabit;\n\t\t    s = nullstr;\n\t\t    break;\n\t\t}\n\t    }\n\t    if (!s)\n\t\ts = nullstr;\n\t    pattern++;\n\t    if (upper || lastcomp) {\n\t\tchar *t;\n\n\t\tif (s != scrbuf) {\n\t\t    Safecpy(scrbuf,s,(sizeof scrbuf));\n\t\t    s = scrbuf;\n\t\t}\n\t\tif (upper || !(t=strrchr(s,'/')))\n\t\t    t = s;\n\t\twhile (*t && !isalpha(*t))\n\t\t    t++;\n\t\tif (islower(*t))\n\t\t    *t = toupper(*t);\n\t    }\n\t    i = metabit;\t\t/* maybe get into register */\n\t    if (s == dest) {\n\t\twhile (*dest) {\n\t\t    if (--destsize <= 0)\n\t\t\tabort_interp();\n\t\t    *dest++ |= i;\n\t\t}\n\t    }\n\t    else {\n\t\twhile (*s) {\n\t\t    if (--destsize <= 0)\n\t\t\tabort_interp();\n\t\t    *dest++ = *s++ | i;\n\t\t}\n\t    }\n\t}\n\telse {\n\t    if (--destsize <= 0)\n\t\tabort_interp();\n\t    if (*pattern == '^' && pattern[1]) {\n\t\t++pattern;\t\t\t/* skip uparrow */\n\t\ti = *pattern;\t\t/* get char into a register */\n\t\tif (i == '?')\n\t\t    *dest++ = '\\177' | metabit;\n\t\telse if (i == '(') {\n\t\t    metabit = 0200;\n\t\t    destsize++;\n\t\t}\n\t\telse if (i == ')') {\n\t\t    metabit = 0;\n\t\t    destsize++;\n\t\t}\n\t\telse\n\t\t    *dest++ = i & 037 | metabit;\n\t\tpattern++;\n\t    }\n\t    else if (*pattern == '\\\\' && pattern[1]) {\n\t\t++pattern;\t\t\t/* skip backslash */\n\t\ti = *pattern;\t\t/* get char into a register */\n\n\t\t/* this used to be a switch but the if may save space */\n\n\t\tif (i >= '0' && i <= '7') {\n\t\t    i = 1;\n\t\t    while (i < 01000 && *pattern >= '0' && *pattern <= '7') {\n\t\t\ti <<= 3;\n\t\t\ti += *pattern++ - '0';\n\t\t    }\n\t\t    *dest++ = i & 0377 | metabit;\n\t\t    --pattern;\n\t\t}\n\t\telse if (i == 'b')\n\t\t    *dest++ = '\\b' | metabit;\n\t\telse if (i == 'f')\n\t\t    *dest++ = '\\f' | metabit;\n\t\telse if (i == 'n')\n\t\t    *dest++ = '\\n' | metabit;\n\t\telse if (i == 'r')\n\t\t    *dest++ = '\\r' | metabit;\n\t\telse if (i == 't')\n\t\t    *dest++ = '\\t' | metabit;\n\t\telse\n\t\t    *dest++ = i | metabit;\n\t\tpattern++;\n\t    }\n\t    else\n\t\t*dest++ = *pattern++ | metabit;\n\t}\n    }\n    *dest = '\\0';\ngetout:\n    return pattern;\t\t\t/* where we left off */\n}\n\nvoid\ninterp(dest,destsize,pattern)\nchar *dest;\nint destsize;\nchar *pattern;\n{\n    (void) dointerp(dest,destsize,pattern,Nullch);\n#ifdef DEBUGGING\n    if (debug & DEB_FILEXP)\n\tfputs(dest,stdout);\n#endif\n}\n\n/* get the person's real name from /etc/passwd */\n/* (string is overwritten, so it must be copied) */\n\nchar *\ngetrealname(uid)\nint uid;\n{\n    char *s, *c;\n\n    struct passwd *pwd = getpwuid(uid);\n\n    s = pwd->pw_gecos;\n    if ((c = strchr(s, ',')) != Nullch)\n\t*c = '\\0';\n    if ((c = strchr(s, ';')) != Nullch)\n\t*c = '\\0';\n    s = cpytill(buf,s,'&');\n    if (*s == '&') {\t\t\t/* whoever thought this one up was */\n\tc = buf + strlen(buf);\t\t/* in the middle of the night */\n\tstrcat(c,logname);\t\t/* before the morning after */\n\tstrcat(c,s+1);\n\tif (islower(*c))\n\t    *c = toupper(*c);\t\t/* gack and double gack */\n    }\n    endpwent();\n    return buf;\t\t\t\t/* return something static */\n}\n\nstatic void\nabort_interp()\n{\n    fputs(\"\\r\\n% interp buffer overflow!\\r\\n\",stdout);\n    sig_catcher(0);\n}\n"
  },
  {
    "path": "games/warp/intrp.h",
    "content": "/* $Header: intrp.h,v 7.0.1.1 86/12/12 16:59:45 lwall Exp $\n *\n * $Log:\tintrp.h,v $\n * Revision 7.0.1.1  86/12/12  16:59:45  lwall\n * Baseline for net release.\n * \n * Revision 7.0  86/10/08  15:12:27  lwall\n * Split into separate files.  Added amoebas and pirates.\n * \n */\n\nEXT char *origdir INIT(Nullch);\t\t/* cwd when warp invoked */\nEXT char *homedir INIT(Nullch);\t\t/* login directory */\nEXT char *dotdir INIT(Nullch);\t\t/* where . files go */\nEXT char *logname INIT(Nullch);\t\t/* login id */\nEXT char *hostname INIT(Nullch);\t/* host name */\nEXT char *realname INIT(Nullch);\t/* real name from /etc/passwd */\n\nvoid    intrp_init();\nchar\t*filexp();\nchar\t*dointerp();\nvoid\tinterp();\nchar\t*getrealname();\n"
  },
  {
    "path": "games/warp/move.c",
    "content": "/* $Header: move.c,v 7.0.1.2 86/10/20 14:37:06 lwall Exp $ */\n\n/* $Log:\tmove.c,v $\n * Revision 7.0.1.2  86/10/20  14:37:06  lwall\n * Picked some lint.\n *\n * Revision 7.0.1.1  86/10/16  10:52:09  lwall\n * Added Damage.  Fixed random bugs.\n *\n * Revision 7.0  86/10/08  15:12:40  lwall\n * Split into separate files.  Added amoebas and pirates.\n *\n */\n\n#include \"EXTERN.h\"\n#include \"warp.h\"\n#include \"bang.h\"\n#include \"object.h\"\n#include \"move.h\"\n#include \"play.h\"\n#include \"score.h\"\n#include \"term.h\"\n#include \"them.h\"\n#include \"us.h\"\n#include \"util.h\"\n#include \"weapon.h\"\n#include \"INTERN.h\"\n#include \"move.h\"\n\nvoid\nmove_init()\n{\n    ;\n}\n\nvoid\nbounce(obj)\nregister OBJECT *obj;\n{\n    register int x;\n    register int y;\n    register int count=0;\n\n    y = (obj->posy - sgn(obj->vely) + YSIZE00) % YSIZE;\n    x = (obj->posx - sgn(obj->velx) + XSIZE00) % XSIZE;\n    while (occupant[y][x]) {\n\ty = (y + rand_mod(3) - 1 + YSIZE00) % YSIZE;\n\tx = (x + rand_mod(3) - 1 + XSIZE00) % XSIZE;\n\tif (++count > 10000) {     /* if universe full, get out of it fast */\n\t    unmake_object(obj);\n\t    if (ent) unmake_object(ent);\n\t    if (base) unmake_object(base);\n\t    finish = 1;\n\t    return;\n\t}\n    }\n    obj->posy = y;\n    obj->posx = x;\n    obj->vely = 0;\n    obj->velx = 0;\n    occupant[y][x] = obj;\n    if (numamoebas && obj->image == ' ')\n\tmvaddc(y+1, x*2, amb[y][x]);\n    else\n\tmvaddc(y+1, x*2, obj->image);\n}\n\nvoid\nmove_universe()\n{\n    register OBJECT *curobj;\n    register int x;\n    register int y;\n    register OBJECT *temp;\n    OBJECT *thenext;\n\n    for (curobj = movers; curobj != &root; curobj = curobj->next) {\n\tx = curobj->posx;\n\ty = curobj->posy;\n\tif (curobj == occupant[y][x]) {\n\t    occupant[y][x] = 0;\n\t}\n\telse if (curobj->type != Torp && curobj->type != Web) {\n\t    resetty();\n\t    abort();\n\t}\n    }\n    for (curobj = movers; curobj != &root; curobj = thenext) {\n\tthenext = curobj->next;\n\tif (curobj->vely || curobj->velx) {\n\t    y = curobj->posy;\n\t    x = curobj->posx;\n\t    if (curobj->image != ' ' &&\n\t      (!(temp=occupant[y][x]) || temp->image==' ') ) {\n\t\tmove(y+1, x*2, numamoebas ? amb[y][x] : ' ');\n\t    }\n\t    y = (y + curobj->vely + YSIZE00) % YSIZE;\n\t    x = (x + curobj->velx + XSIZE00) % XSIZE;\n\t    if (!(temp=occupant[y][x]) || temp->type != Star ||\n\t      curobj->type != Torp || curobj->image == '+' ||\n\t      curobj->image == 'x') {\n\t\tcurobj->posy = y;\n\t\tcurobj->posx = x;\n\t    }\n\t    else {\n\t\tif (curobj->image == '0') {\n\t\t    curobj->vely = rand_mod(3)-1;\n\t\t    curobj->velx = rand_mod(3)-1;\n\t\t}\n\t\telse\n\t\t    curobj->vely = curobj->velx = 0;\n\t\ty = curobj->posy;\n\t\tx = curobj->posx;\n\t    }\n\t}\n\telse {\t\t\t/* not moving */\n\t    y = curobj->posy;\n\t    x = curobj->posx;\n\t    if (curobj->type == Torp ||\n\t\tcurobj->type == Star ||\n\t\tcurobj->type == Web) {\n\t\tcurobj->flags |= STATIC;\n\t\tcurobj->next->prev = curobj->prev;\n\t\tcurobj->prev->next = curobj->next;\n\t\tcurobj->prev = movers->prev;\n\t\tcurobj->next = movers;\n\t\tmovers->prev->next = curobj;\n\t\tmovers->prev = curobj;\n\t    }\n\t}\n\tif (temp = occupant[y][x]) {\t\t/* already occupied? */\n\t    if (!temp->contend) {\n\t\tif (temp->type == Torp) {\n\t\t    if (temp->image == '+')\n\t\t\tblast[y][x] += 1250;\n\t\t    else if (temp->image == 'o' && (base||ent))\n\t\t\tblast[y][x] += 500+super*20;\n\t\t    else if (temp->image == 'O' && (base||ent))\n\t\t\tblast[y][x] += 5000+super*100;\n\t\t}\n\t    }\n\t    yblasted[y] |= 1;\n\t    xblasted[x] |= 1;\n\t    blasted = TRUE;\n\t    curobj->contend = temp;\n\t    occupant[y][x] = curobj;\n\t    switch (curobj->type) {\n\t    case Enemy:\n\t\tif (numamoebas && curobj == nuke && temp->image == '+')\n\t\t    blast[y][x] += 80000;\n\t\telse if (temp->type == Enemy)\n\t\t    blast[y][x] += 10;\n\t\telse\n\t\t    goto defblast;\n\t\tbreak;\n\t    case Crusher:\n\t\tif (curobj->velx)\n\t\t    blast[y][x] += 100000;\n\t\telse\n\t\t    goto defblast;\n\t\tbreak;\n\t    case Torp:\n\t\tif (curobj->image == '+')\n\t\t    blast[y][x] += (temp==nuke ? 80000 : 1250);\n\t\telse if (curobj->image == 'o')\n\t\t    blast[y][x] += 500+super*20;\n\t\telse if (curobj->image == 'O')\n\t\t    blast[y][x] += 5000+super*100;\n\t\tgoto defblast;\n\t    case Star:\n\t\tif (temp == ent)\n\t\t    goto damshield;\n\t\tgoto defblast;\n\t    case Enterprise:\n\t\tif (temp->type == Star) {\n\t      damshield:\n\t\t    if (!rand_mod(10)) {\n\t\t\tif (!damflag[NOSHIELDS])\n\t\t\t    damage++;\n\t\t\tif (damflag[NOSHIELDS] < 100)\n\t\t\t    damflag[NOSHIELDS] += rand_mod(smarts)/5+2;\n\t\t    }\n\t\t}\n\t\tgoto defblast;\n\t    default:\n\t      defblast:\n\t\tblast[y][x] += rand_mod(751)+1;\n\t\tbreak;\n\t    }\n\t}\n\telse {\n\t    occupant[y][x] = curobj;\n\t    if (curobj->image != ' ' &&\n\t        (curobj->velx || curobj->vely ||\n\t\t curobj->type == Torp || curobj->type == Web) ) {\n\t\tmvaddc(y+1, x*2, curobj->image);\n\t    }\n\t    if (curobj->type == Crusher && curobj->velx) {\n\t\tblast[y][x] += 100000;\n\t\tyblasted[y] |= 1;\n\t\txblasted[x] |= 1;\n\t\tblasted = TRUE;\n\t    }\n\t}\n    }\n    if (blasted) {\n\tregister int minxblast = -1;\n\tregister int maxxblast = -2;\n\tregister long tmpblast;\n\n\tblasted = numamoebas;\n\tfor (x=0; x<XSIZE; x++) {\n\t    if (xblasted[x]) {\n\t\txblasted[x] = 0;\n\t\tmaxxblast = x;\n\t\tif (minxblast < 0)\n\t\t    minxblast = x;\n\t    }\n\t}\n\tfor (y=0; y<YSIZE; y++) {\n\t    if (yblasted[y]) {\n\t\tyblasted[y] = 0;\n\t\tfor (x=minxblast; x<=maxxblast; x++) {\n\t\t    tmpblast = blast[y][x];\n\t\t    if (numamoebas && amb[y][x] == '~') {\n\t\t\tif (temp = occupant[y][x]) {\n\t\t\t    if (temp->image == '&')\n\t\t\t\ttmpblast >>= 1;\n\t\t\t    else if (temp->type == Web)\n\t\t\t\ttmpblast = 100000;\n\t\t\t    else\n\t\t\t\ttmpblast += 50 + temp->energy/100;\n\t\t\t    if (tmpblast > 250 && !rand_mod(5+(inumstars>>4)))\n\t\t\t\tmodify_amoeba(y,x,1,'~',5);\n\t\t\t}\n\t\t\txblasted[x] = 2;\n\t\t\tyblasted[y] = 2;\n\t\t    }\n\t\t    if (tmpblast) {\n\t\t\tregister OBJECT *biggie = 0;\n\n\t\t\tblast[y][x] = 0;\n\t\t\ttemp = occupant[y][x];\n\t\t\tif (tmpblast < 0) {\n\t\t\t    if (numamoebas && tmpblast < -1000000 &&\n\t\t\t\tamb[y][x] == '~' && temp != nuke) {\n\t\t\t\tamb[y][x] = ' ';\n\t\t\t\tif (!temp)\n\t\t\t\t    make_plink(y,x);\n\t\t\t\tambsize--;\n\t\t\t    }\n\t\t\t    tmpblast = 0;\n\t\t\t}\n\t\t\tif (temp) {\n\t\t\t    if ((!numamoebas || amb[y][x]==' ') &&\n\t\t\t      tmpblast < 100000)\n\t\t\t\tmake_plink(y,x);\n\t\t\t    for ( ;temp;\n\t\t\t      temp = curobj->contend,curobj->contend = 0){\n\t\t\t\tcurobj = temp;\n\t\t\t\tswitch (curobj->type) {\n\t\t\t\tcase Enterprise: {\n\t\t\t\t    long tmp = curobj->energy;\n\n\t\t\t\t    if (ent->energy>500 || apolloflag & 1)\n\t\t\t\t\tcurobj->energy -= tmpblast /\n\t\t\t\t\t   ((apolloflag & 1)\n\t\t\t\t\t    ? 20\n\t\t\t\t\t    : (5+abs(ent->velx)+abs(ent->vely))\n\t\t\t\t\t       / ((damflag[NOSHIELDS]>>3)+1)+1);\n\t\t\t\t    else\n\t\t\t\t\tcurobj->energy -= tmpblast;\n\t\t\t\t    if (rand_mod(1 + tmp - curobj->energy) > 100\n\t\t\t\t\t|| ent->energy < (entmax>>1)) {\n\t\t\t\t\tif (debug & 128 ||\n\t\t\t\t\t  (damage <= smarts/10 &&\n\t\t\t\t\t   !rand_mod(6-smarts/20-massacre) )) {\n\t\t\t\t\t    tmp = rand_mod(MAXDAMAGE);\n\t\t\t\t\t    if (damflag[tmp]) {\n\t\t\t\t\t\tif (damflag[tmp] < 60)\n\t\t\t\t\t\t  damflag[tmp] += rand_mod(60);\n\t\t\t\t\t    }\n\t\t\t\t\t    else {\n\t\t\t\t\t\tdamflag[tmp] =\n\t\t\t\t\t\t  rand_mod(smarts+10)+2;\n\t\t\t\t\t\tdamage++;\n\t\t\t\t\t    }\n\t\t\t\t\t}\n\t\t\t\t    }\n\t\t\t\t    break;\n\t\t\t\t}\n\t\t\t\tcase Base:\n\t\t\t\t    if (base->energy > 1000 || apolloflag & 2)\n\t\t\t\t\tcurobj->energy -= tmpblast /\n\t\t\t\t\t   ((apolloflag & 2)?20:5);\n\t\t\t\t    else\n\t\t\t\t\tcurobj->energy -= tmpblast;\n\t\t\t\t    break;\n\t\t\t\tcase Crusher:\n\t\t\t\t    if (tmpblast > 132767)\n\t\t\t\t\tcurobj->energy -= (tmpblast - 100000);\n\t\t\t\t    else if (tmpblast >= 100000) {\n\t\t\t\t\tcurobj->energy += (tmpblast - 100000);\n\t\t\t\t\tif (curobj->energy > 32767)\n\t\t\t\t\t    curobj->energy = 32767;\n\t\t\t\t    }\n\t\t\t\t    else\t/* vulnerable while feeding */\n\t\t\t\t\tcurobj->energy -= tmpblast;\n\t\t\t\t    break;\n\t\t\t\tcase Enemy:\n\t\t\t\t    curobj->energy -= tmpblast*10/enemshields;\n\t\t\t\t    break;\n\t\t\t\tdefault:\n\t\t\t\t    curobj->energy -= tmpblast;\n\t\t\t\t    break;\n\t\t\t\t}\n\t\t\t\tif (curobj->energy < 0) {\t/* killed it? */\n\t\t\t\t    switch (curobj->image) {\n\t\t\t\t    case 'A':\n\t\t\t\t\ttmpblast = 100000;\n\t\t\t\t\tmake_blast(y,x,8192L,1);\n\t\t\t\t\tnumapollos = apolloflag = 0;\n\t\t\t\t\tnumstars--;\n\t\t\t\t\tnumenemies--;\n\t\t\t\t\tcurscore += 5000;\n\t\t\t\t\tdeados = 0;\n\t\t\t\t\tbreak;\n\t\t\t\t    case 'E': case 'e': case 'C': case 'c':\n\t\t\t\t\tent = 0;\n\t\t\t\t\tnuments--;\n\t\t\t\t\tif (base)\n\t\t\t\t\t    status = 2;\n\t\t\t\t\telse\n\t\t\t\t\t    status = 3;\n\t\t\t\t\tdeados = 0;\n\t\t\t\t\tbreak;\n\t\t\t\t    case 'B': case 'b':\n\t\t\t\t\tbase = 0;\n\t\t\t\t\tnumbases--;\n\t\t\t\t\tif (ent)\n\t\t\t\t\t    status = entmode;\n\t\t\t\t\telse\n\t\t\t\t\t    status = 3;\n\t\t\t\t\tdeados = 0;\n\t\t\t\t\tbreak;\n\t\t\t\t    case '&': {\n\t\t\t\t\tint i, xxx, yyy;\n\n\t\t\t\t\tfor (i = 0; i < YSIZE; i++)\n\t\t\t\t\t    yblasted[i] &= 1;\n\t\t\t\t\tfor (i = 0; i < XSIZE; i++)\n\t\t\t\t\t    xblasted[i] &= 1;\n\t\t\t\t\tnumamoebas = 0;\t/* ignore amb[][] now */\n\t\t\t\t\tfor (yyy = 0; yyy < YSIZE; yyy++) {\n\t\t\t\t\t    for (xxx = 0; xxx < XSIZE; xxx++) {\n\t\t\t\t\t\tif (amb[yyy][xxx] == '~' &&\n\t\t\t\t\t\t    !occupant[yyy][xxx]) {\n\t\t\t\t\t\t    mvaddch(yyy+1,xxx*2,' ');\n\t\t\t\t\t\t}\n\t\t\t\t\t    }\n\t\t\t\t\t}\n\t\t\t\t\tnumenemies--;\n\t\t\t\t\tcurscore += 10000;\n\t\t\t\t\tif (curobj == enemies)\n\t\t\t\t\t    enemies = curobj->next;\n\t\t\t\t\tdeados = 0;\n\t\t\t\t\tbreak;\n\t\t\t\t    }\n\t\t\t\t    case '<': case '>': {\n\t\t\t\t\tint i;\n\n\t\t\t\t\tnumenemies--;\n\t\t\t\t\tnumcrushes = 0;\n\t\t\t\t\tcurscore += 10000;\n\t\t\t\t\tif (curobj == movers)\n\t\t\t\t\t    movers = curobj->next;\n\t\t\t\t\tif (curobj == enemies)\n\t\t\t\t\t    enemies = curobj->next;\n\t\t\t\t\tdeados = 0;\n\n\t\t\t\t\ttmpblast = 100000;\n\t\t\t\t\tmake_blast(y,(x+XSIZE00)%XSIZE,10000L,0);\n\t\t\t\t\tif (curobj->image == '<') {\n\t\t\t\t\t    for (i=XSIZE00; i<=XSIZE01; i++)\n\t\t\t\t\t\tmake_blast(y,(x+i)%XSIZE,\n\t\t\t\t\t\t    10000L,0);\n\t\t\t\t\t    for (i=XSIZE00; i<=XSIZE02; i++)\n\t\t\t\t\t\tmake_blast(y,(x+i)%XSIZE,\n\t\t\t\t\t\t    10000L,0);\n\t\t\t\t\t    make_blast(y,(x+XSIZE03)%XSIZE,\n\t\t\t\t\t\t10000L,1);\n\t\t\t\t\t    for (i=XSIZE00; i<=XSIZE08; i++)\n\t\t\t\t\t\tmake_blast(y,(x+i)%XSIZE,\n\t\t\t\t\t\t    10000L,0);\n\t\t\t\t\t}\n\t\t\t\t\telse {\n\t\t\t\t\t    for (i=XSIZE00; i>=XSIZE99; i--)\n\t\t\t\t\t\tmake_blast(y,(x+i)%XSIZE,\n\t\t\t\t\t\t    10000L,0);\n\t\t\t\t\t    for (i=XSIZE00; i>=XSIZE98; i--)\n\t\t\t\t\t\tmake_blast(y,(x+i)%XSIZE,\n\t\t\t\t\t\t    10000L,0);\n\t\t\t\t\t    make_blast(y,(x+XSIZE97)%XSIZE,\n\t\t\t\t\t\t10000L,1);\n\t\t\t\t\t    for (i=XSIZE00; i>=XSIZE92; i--)\n\t\t\t\t\t\tmake_blast(y,(x+i)%XSIZE,\n\t\t\t\t\t\t    10000L,0);\n\t\t\t\t\t}\n\t\t\t\t    }\n\t\t\t\t    break;\n\t\t\t\t    case 'K':\n\t\t\t\t\tnumenemies--;\n\t\t\t\t\tcurscore += curobj->mass;\n\t\t\t\t\tif (curobj == enemies)\n\t\t\t\t\t    enemies = curobj->next;\n\t\t\t\t\tdeados = 0;\n\t\t\t\t\tbreak;\n\t\t\t\t    case 'T':\n\t\t\t\t\tnumenemies--;\n\t\t\t\t\tcurscore += curobj->mass*3/2;\n\t\t\t\t\tif (curobj == enemies)\n\t\t\t\t\t    enemies = curobj->next;\n\t\t\t\t\tdeados = 0;\n\t\t\t\t\tbreak;\n\t\t\t\t    case 'R': case ' ': case 'P':\n\t\t\t\t\tnumenemies--;\n\t\t\t\t\tif (curobj->flags & PIRATE)\n\t\t\t\t\t    curscore += curobj->mass;\n\t\t\t\t\telse\n\t\t\t\t\t    curscore += curobj->mass*3;\n\t\t\t\t\tif (curobj == enemies)\n\t\t\t\t\t    enemies = curobj->next;\n\t\t\t\t\tdeados = 0;\n\t\t\t\t\tbreak;\n\t\t\t\t    case 'G':\n\t\t\t\t\tnumenemies--;\n\t\t\t\t\tnumgorns--;\n\t\t\t\t\ttmpblast = 100000;\n\t\t\t\t\tif (madgorns)\n\t\t\t\t\t    curscore += curobj->mass/2;\n\t\t\t\t\telse\n\t\t\t\t\t    curscore += curobj->mass*2;\n\t\t\t\t\tif (curobj == enemies)\n\t\t\t\t\t    enemies = curobj->next;\n\t\t\t\t\t{\n\t\t\t\t\t    int xxx,yyy;\n\n\t\t\t\t\t    for (xxx = -1; xxx<=1; xxx++)\n\t\t\t\t\t\tfor (yyy = -1; yyy<=1; yyy++)\n\t\t\t\t\t\t    if (rand_mod(2+massacre))\n\t\t\t\t\t\t\tfire_torp(curobj,\n\t\t\t\t\t\t\t    yyy,xxx);\n\t\t\t\t\t}\n\t\t\t\t\tdeados = 0;\n\t\t\t\t\tbreak;\n\t\t\t\t    case '@':\n\t\t\t\t\tnuminhab--;\n\t\t\t\t\t/* FALL THROUGH */\n\t\t\t\t    case '*':\n\t\t\t\t\tbanging = TRUE;\n\t\t\t\t\tnumstars--;\n\t\t\t\t\tbreak;\n\t\t\t\t    case '|': case '-': case '/': case '\\\\':\n\t\t\t\t\ttmpblast = 100000;\n\t\t\t\t\tmake_blast(y,x,curobj->mass,1);\n\t\t\t\t\tbanging = TRUE;\n\t\t\t\t\tdeados = 0;\n\t\t\t\t\tbreak;\n\t\t\t\t    case 'x':\n\t\t\t\t\tcurscore += 10;\n\t\t\t\t\tdeados = 0;\n\t\t\t\t\tbreak;\n\t\t\t\t    case 'X':\n\t\t\t\t\tcurscore += 100;\n\t\t\t\t\tnumxes--;\n\t\t\t\t\tdeados = 0;\n\t\t\t\t\tbreak;\n\t\t\t\t    case '0':\n\t\t\t\t\tcurscore += 35;\n\t\t\t\t\tnumos--;\n\t\t\t\t\tdeados += 3;\n\t\t\t\t\tbreak;\n\t\t\t\t    case 'o':\n\t\t\t\t\tcurscore += 100;\n\t\t\t\t\tnumos--;\n\t\t\t\t\tdeados++;\n\t\t\t\t\tbreak;\n\t\t\t\t    case 'O':\n\t\t\t\t\tcurscore += 200;\n\t\t\t\t\tnumos--;\n\t\t\t\t\tdeados += 2;\n\t\t\t\t\tbreak;\n\t\t\t\t    case 'M':\n\t\t\t\t\tdeadmudds++;\n\t\t\t\t\tinumfriends--;\n\t\t\t\t\tnumfriends--;\n\t\t\t\t\tif (curobj == enemies)\n\t\t\t\t\t    enemies = curobj->next;\n\t\t\t\t\tbreak;\n\t\t\t\t    case 'Q': case 'W': case 'Y': case 'U':\n\t\t\t\t    case 'I': case 'S': case 'D': case 'H':\n\t\t\t\t    case 'J': case 'L': case 'Z': case 'V':\n\t\t\t\t    case 'F':\n\t\t\t\t\tnumfriends--;\n\t\t\t\t\tif (curobj == enemies)\n\t\t\t\t\t    enemies = curobj->next;\n\t\t\t\t\tif (inumfriends < 10)\n\t\t\t\t\t    madfriends += 500;\n\t\t\t\t\telse\n\t\t\t\t\t    madfriends += 10000/inumfriends;\n\t\t\t\t\tbreak;\n\t\t\t\t    }\n\t\t\t\t    if (tmpblast < 100000)\n\t\t\t\t\tmake_blast(y,x,curobj->mass,1);\n\t\t\t\t    unmake_object(curobj);\n\t\t\t\t}\n\t\t\t\telse {\t\t/* didn't kill anything */\n\t\t\t\t    if (!biggie)\n\t\t\t\t\tbiggie = curobj;\n\t\t\t\t    else {\n\t\t\t\t\tif (biggie->mass > curobj->mass)\n\t\t\t\t\t    bounce(curobj);\n\t\t\t\t\telse {\n\t\t\t\t\t    bounce(biggie);\n\t\t\t\t\t    biggie = curobj;\n\t\t\t\t\t}\n\t\t\t\t    }\n\t\t\t\t}\n\t\t\t    }\n\t\t\t    if (biggie) {\n\t\t\t\toccupant[y][x] = biggie;\n\t\t\t\tif (numamoebas && biggie->image == ' ')\n\t\t\t\t    mvaddch(y+1,x*2, amb[y][x]);\n\t\t\t\telse\n\t\t\t\t    mvaddch(y+1,x*2, biggie->image);\n\t\t\t    }\n\t\t\t    else {\n\t\t\t\toccupant[y][x] = 0;\n\t\t\t\tmvaddch(y+1, x*2, numamoebas ? amb[y][x] : ' ');\n\t\t\t    }\n\t\t\t}\n\t\t    }\n\t\t}\n\t    }\n\t}\n    }\n    do_bangs();\n    if (numcrushes && movers->type == Crusher)\n\tmovers->vely = 0;\n    if (curobj = base) {\n\tchar ch;\n\n\tcurobj->velx = 0;\n\tcurobj->vely = 0;\n\tcurobj->energy += 25*lookaround(curobj->posy,curobj->posx,Star);\n\tif (curobj->energy > basemax)\n\t    curobj->energy = basemax;\n\tif (curobj->energy >= 1000)\n\t    ch = 'B';\n\telse\n\t    ch = 'b';\n\tif (ch != curobj->image) {\n\t    setimage(curobj, ch);\n\t}\n    }\n    if (curobj = ent) {\n\tchar ch;\n\n\tif (entmode == 0) {\n\t    curobj->velx = 0;\n\t    curobj->vely = 0;\n\t}\n\tif (base && !cloaking && !curobj->velx && !curobj->vely &&\n\t  lookfor(curobj->posy,curobj->posx,Base)) {\n\t    int tmp;\n\n\t    tmp = (int) (base->energy - 1000 < entmax - curobj->energy ?\n\t\t         base->energy - 1000 : entmax - curobj->energy);\n\t    if (tmp < 0)\n\t\ttmp = 0;\n\t    curobj->energy += tmp;\n\t    base->energy -= tmp;\n\t    tmp = (btorp < 50 - etorp ?\n\t\t   btorp : 50 - etorp);\n\t    etorp += tmp;\n\t    btorp -= tmp;\n\t    if (damage) {\n\t\ttmp = rand_mod(MAXDAMAGE);\n\t\tif (damflag[tmp] > 5) {\n\t\t    damflag[tmp] = rand_mod(5)+1;\n\t\t}\n\t    }\n\t}\n\tif (curobj->energy >= 500 && (!damage || !damflag[NOSHIELDS]))\n\t    ch = cloaked?'C':'E';\n\telse\n\t    ch = cloaked?'c':'e';\n\tif (ch != curobj->image) {\n\t    setimage(curobj, ch);\n\t}\n    }\n}\n\nint\nlookaround(y, x, what)\nregister int y;\nregister int x;\nregister char what;\n{\n    register OBJECT *obj;\n    register int count=0;\n    register int xp;\n    register int xm;\n\n    if ((obj=occupant[y][xp=(x+XSIZE01)%XSIZE])&&obj->type == what) /* 0, 1 */\n\tcount++;\n    if ((obj=occupant[y][xm=(x+XSIZE99)%XSIZE])&&obj->type == what) /* 0, -1 */\n\tcount++;\n    if ((obj=occupant[y=(y+YSIZE99)%YSIZE][xp])&&obj->type == what) /* -1, 1 */\n\tcount++;\n    if ((obj=occupant[y][x])&&obj->type == what)                    /* -1, 0 */\n\tcount++;\n    if ((obj=occupant[y][xm])&&obj->type == what)                   /* -1, -1 */\n\tcount++;\n    if ((obj=occupant[y=(y+2)%YSIZE][xp])&&obj->type == what)       /* 1, 1 */\n\tcount++;\n    if ((obj=occupant[y][x])&&obj->type == what)                    /* 1, 0 */\n\tcount++;\n    if ((obj=occupant[y][xm])&&obj->type == what)                   /* 1, -1 */\n\tcount++;\n    return (count);\n}\n\nint\nlookfor(y, x, what)\nregister int y;\nregister int x;\nregister char what;\n{\n    register OBJECT *obj;\n    register int xp;\n    register int xm;\n\n    if ((obj=occupant[y][xp=(x+XSIZE01)%XSIZE])&&obj->type == what ||/* 0, 1 */\n        (obj=occupant[y][xm=(x+XSIZE99)%XSIZE])&&obj->type == what ||/* 0, -1 */\n        (obj=occupant[y=(y+YSIZE99)%YSIZE][xp])&&obj->type == what ||/* -1, 1 */\n        (obj=occupant[y][x])&&obj->type == what                    ||/* -1, 0 */\n        (obj=occupant[y][xm])&&obj->type == what                   ||/* -1,-1 */\n        (obj=occupant[y=(y+2)%YSIZE][xp])&&obj->type == what       ||/* 1, 1 */\n        (obj=occupant[y][x])&&obj->type == what                    ||/* 1, 0 */\n        (obj=occupant[y][xm])&&obj->type == what)                    /* 1, -1 */\n\treturn(1);\n    return (0);\n}\n\nOBJECT*\nlookimg(y, x, what)\nregister int y;\nregister int x;\nregister char what;\n{\n    register OBJECT *obj;\n    register int xp;\n    register int xm;\n\n    if ((obj=occupant[y][xp=(x+XSIZE01)%XSIZE])&&obj->image==what ||/* 0, 1 */\n        (obj=occupant[y][xm=(x+XSIZE99)%XSIZE])&&obj->image==what ||/* 0, -1 */\n        (obj=occupant[y=(y+YSIZE99)%YSIZE][xp])&&obj->image==what ||/* -1, 1 */\n        (obj=occupant[y][x])&&obj->image==what                    ||/* -1, 0 */\n        (obj=occupant[y][xm])&&obj->image==what                   ||/* -1,-1 */\n        (obj=occupant[y=(y+2)%YSIZE][xp])&&obj->image==what       ||/* 1, 1 */\n        (obj=occupant[y][x])&&obj->image==what                    ||/* 1, 0 */\n        (obj=occupant[y][xm])&&obj->image==what)                    /* 1, -1 */\n\treturn obj;\n    return Null(OBJECT*);\n}\n"
  },
  {
    "path": "games/warp/move.h",
    "content": "/* $Header: move.h,v 7.0 86/10/08 15:12:46 lwall Exp $ */\n\n/* $Log:\tmove.h,v $\n * Revision 7.0  86/10/08  15:12:46  lwall\n * Split into separate files.  Added amoebas and pirates.\n * \n */\n\nvoid bounce();\nvoid move_universe();\nint lookaround();\nint lookfor();\nOBJECT *lookimg();\nvoid move_init();\n"
  },
  {
    "path": "games/warp/object.c",
    "content": "/* $Header: object.c,v 7.0 86/10/08 15:12:55 lwall Exp $ */\n\n/* $Log:\tobject.c,v $\n * Revision 7.0  86/10/08  15:12:55  lwall\n * Split into separate files.  Added amoebas and pirates.\n *\n */\n\n#include \"EXTERN.h\"\n#include \"warp.h\"\n#include \"INTERN.h\"\n#include \"object.h\"\n\nvoid\nobject_init()\n{\n    ;\n}\n\nOBJECT *\nmake_object(typ, img, py, px, vy, vx, energ, mas, where)\nchar typ;\nchar img;\nint px, py, vx, vy;\nlong energ, mas;\nOBJECT *where;\n{\n    register OBJECT *obj;\n\n    if (free_root.next == &free_root)\n\tobj = (OBJECT *) malloc(sizeof root);\n    else {\n\tobj = free_root.next;\n\tfree_root.next = obj->next;\n\tobj->next->prev = &free_root;\n    }\n    obj->type = typ;\n    obj->image = img;\n    obj->next = where;\n    obj->prev = where->prev;\n    where->prev = obj;\n    obj->prev->next = obj;\n    obj->velx = vx;\n    obj->vely = vy;\n    obj->contend = 0;\n    obj->strategy = 0;\n    obj->flags = 0;\n    obj->posx = px;\n    obj->posy = py;\n    if (typ != Torp && typ != Web) {\n\toccupant[py][px] = obj;\n    }\n    obj->energy = energ;\n    obj->mass = mas;\n    return(obj);\n}\n\nvoid\nunmake_object(curobj)\nregister OBJECT *curobj;\n{\n    curobj->prev->next = curobj->next;\n    curobj->next->prev = curobj->prev;\n    if (curobj == movers) {\n\tmovers = curobj->next;\n    }\n    free_object(curobj);\n}\n\nvoid\nfree_object(curobj)\nregister OBJECT *curobj;\n{\n    curobj->next = free_root.next;\n    curobj->prev = &free_root;\n    free_root.next->prev = curobj;\n    free_root.next = curobj;\n}\n"
  },
  {
    "path": "games/warp/object.h",
    "content": "/* $Header: object.h,v 7.0.1.2 86/12/12 17:01:38 lwall Exp $ */\n\n/* $Log:\tobject.h,v $\n * Revision 7.0.1.2  86/12/12  17:01:38  lwall\n * Baseline for net release.\n *\n * Revision 7.0.1.1  86/10/16  10:52:30  lwall\n * Added Damage.  Fixed random bugs.\n *\n * Revision 7.0  86/10/08  15:13:04  lwall\n * Split into separate files.  Added amoebas and pirates.\n *\n */\n\n#define Root 0\n#define Base 1\n#define Enterprise 2\n#define Star 3\n#define Torp 4\n#define Enemy 5\n#define Web 6\n#define Crusher 7\n\ntypedef struct object {\n    char posx, posy;\n    char velx, vely;\n    struct object *next, *prev, *contend;\n    long energy;\n    long mass;\n    char type;\n    char image;\n    char strategy;\n    char flags;\n} OBJECT;\n\n#define PIRATE 1\t/* we may mutiny */\n#define FRIENDLY 2\t/* we aren't really an enemy, for now */\n#define STATIC 4\t/* we are not in the movers list at the moment */\n#define COUNTDOWN 8\t/* we are counting down for something */\n#define CLOAKS 16\t/* we can cloak */\n\n#ifdef DOINIT\nOBJECT root = {0, 0, 0, 0, &root, &root, 0, 0, 0, Root, '?', 0, 0};\n#else\nEXT OBJECT root;\n#endif\n\n#ifdef DOINIT\nOBJECT free_root = {0, 0, 0, 0, &free_root, &free_root, 0, 0, 0, Root, '?', 0, 0};\n#else\nEXT OBJECT free_root;\n#endif\n\nEXT OBJECT *ent;\nEXT OBJECT *base;\nEXT OBJECT *enemies;\nEXT OBJECT *movers;\nEXT OBJECT *realapollo;\nEXT OBJECT *nuke;\n\nEXT OBJECT *occupant[YSIZE][XSIZE];\n\nOBJECT *make_object();\n\nvoid unmake_object();\nvoid free_object();\nvoid object_init();\n"
  },
  {
    "path": "games/warp/patchlevel.h",
    "content": "#define PATCHLEVEL 3\n"
  },
  {
    "path": "games/warp/play.c",
    "content": "/* $Header: play.c,v 7.0.1.1 86/10/16 10:52:39 lwall Exp $ */\n\n/* $Log:\tplay.c,v $\n * Revision 7.0.1.1  86/10/16  10:52:39  lwall\n * Added Damage.  Fixed random bugs.\n *\n * Revision 7.0  86/10/08  15:13:09  lwall\n * Split into separate files.  Added amoebas and pirates.\n *\n */\n\n#include \"EXTERN.h\"\n#include \"warp.h\"\n#include \"bang.h\"\n#include \"score.h\"\n#include \"object.h\"\n#include \"move.h\"\n#include \"term.h\"\n#include \"them.h\"\n#include \"us.h\"\n#include \"util.h\"\n#include \"weapon.h\"\n#include \"INTERN.h\"\n#include \"play.h\"\n\nvoid\nplay_init()\n{\n    ;\n}\n\nvoid\nplay()\n{\n    bool done = FALSE;\n    register OBJECT *curobj;\n    register OBJECT *to;\n    register int i;\n    register int x;\n    register int y;\n\n    display_status();\n#ifdef TIOCOUTQ\n    while (output_pending() > charsperhalfsec)\n\tsleep(1);\t\t\t /* allow buffers to empty */\n#endif\n    sleep(3);\n    do {\n\ttimer++;\n\tnxtbang = 0;\n\tbanging = FALSE;\n\tdisplay_status();\n#ifdef TIOCOUTQ\n\twhile (output_pending() > charsperhalfsec)\n\t    sleep(1);\n#endif\n\tif (lowspeed)\n\t    roundsleep(2);\n\telse\n\t    roundsleep(1);\n\tif (ent) {\n\t    evely = ent->vely;\n\t    evelx = ent->velx;\n\t    if (cloaking && ent->energy >= 250 && !damflag[NOCLOAKING]) {\n\t\tif (!rand_mod(300)) {\n\t\t    damage++;\n\t\t    damflag[NOCLOAKING] = rand_mod(smarts+1)+2;\n\t\t}\n\t\tent->energy -= ent->energy/40;\n\t    }\n\t    else\n\t\tcloaking = FALSE;\n\t    cloaked = cloaking;\n\t}\n\tif (base) {\n\t    bvely = base->vely;\n\t    bvelx = base->velx;\n\t}\n\tget_commands(&done);\n\tif (done)\n\t    break;\n\ttheir_smarts();\n\tapolloflag = 0;\n\tif (ent) {\n\t    if (numapollos) {\n\t\tif (numstars) {\n\t\t    if (realapollo) {\n\t\t\tif (lookfor(realapollo->posy,realapollo->posx,\n\t\t\t    Enterprise)) {\n\t\t\t    apolloflag = 1;\n\t\t\t}\n\t\t    }\n\t\t    else if (lookfor(root.next->posy,root.next->posx,\n\t\t\tEnterprise)) {\n\t\t\tapolloflag = 1;\n\t\t\trealapollo = root.next;\n\t\t\tmvaddch(realapollo->posy+1,realapollo->posx*2,\n\t\t\t    'A');\n\t\t\trealapollo->image = 'A';\n\t\t\trealapollo->mass = 6000;\n\t\t\tinumapollos = 1;\n\t\t\tnumenemies++;\n\t\t\tinumenemies++;\n\t\t\tpossiblescore += 5000;\n\t\t    }\n\t\t    if (apolloflag) {\n\t\t\tif (blast[realapollo->posy][realapollo->posx] <= 32000)\n\t\t\t    evely = evelx = 0;\n\t\t\trealapollo->energy = 32000;\n\t\t    }\n\t\t}\n\t\telse\n\t\t    numapollos = 0;\n\t    }\n\t    ent->vely = evely;\n\t    ent->velx = evelx;\n\t}\n\tif (base) {\n\t    if (numapollos) {\n\t\tif (numstars) {\n\t\t    if (realapollo) {\n\t\t\tif (lookfor(realapollo->posy,realapollo->posx,\n\t\t\t    Base)) {\n\t\t\t    apolloflag |= 2;\n\t\t\t}\n\t\t    }\n\t\t    else if (lookfor(root.next->posy,root.next->posx,\n\t\t\tBase)) {\n\t\t\tapolloflag |= 2;\n\t\t\trealapollo = root.next;\n\t\t\tmvaddch(realapollo->posy+1,realapollo->posx*2,\n\t\t\t    'A');\n\t\t\trealapollo->image = 'A';\n\t\t\trealapollo->mass = 6000;\n\t\t\tinumapollos = 1;\n\t\t\tnumenemies++;\n\t\t\tinumenemies++;\n\t\t\tpossiblescore += 5000;\n\t\t    }\n\t\t    if (apolloflag & 2) {\n\t\t\tif (blast[realapollo->posy][realapollo->posx] <= 32000)\n\t\t\t    bvely = bvelx = 0;\n\t\t\trealapollo->energy = 32000;\n\t\t    }\n\t\t}\n\t\telse\n\t\t    numapollos = 0;\n\t    }\n\t    base->vely = bvely;\n\t    base->velx = bvelx;\n\t}\n\tif (aretorps) {\n\t    aretorps = 0;\n\t    for (i=0;i<2;i++) for (y=0;y<3;y++) for (x=0;x<3;x++) {\n\t\tif (curobj = isatorp[i][y][x]) {\n\t\t    to = occupant[(curobj->posy+curobj->vely+YSIZE00)%YSIZE]\n\t\t\t\t [(curobj->posx+curobj->velx+XSIZE00)%XSIZE];\n\t\t    if (to && !to->vely && !to->velx) {\n\t\t\tunmake_object(curobj);\n\t\t\tif (i)\n\t\t\t    btorp++;\n\t\t\telse\n\t\t\t    etorp++;\n\t\t    }\n\t\t    isatorp[i][y][x]=0;\n\t\t}\n\t    }\n\t}\n\tmove_universe();\n\tif (finish) {\n\t    finish--;\n\t    if (!finish && (!(numenemies || numos) || (!ent && !base))) {\n\t\tdone = TRUE;\n\t\ttimer -= 5;\n\t    }\n\t}\n\telse if (!banging && (!(numenemies || numos) || (!ent && !base)))\n\t    finish = 5;\n    } while (!done);\n}\n"
  },
  {
    "path": "games/warp/play.h",
    "content": "/* $Header: play.h,v 7.0 86/10/08 15:13:12 lwall Exp $ */\n\n/* $Log:\tplay.h,v $\n * Revision 7.0  86/10/08  15:13:12  lwall\n * Split into separate files.  Added amoebas and pirates.\n * \n */\n\nEXT int finish INIT(0);\nEXT int timer;\n\nvoid play();\nvoid play_init();\n"
  },
  {
    "path": "games/warp/score.c",
    "content": "/* $Header: /usr/src/games/warp/RCS/score.c,v 1.1.1 95/01/21 02:13:26 games Exp $ */\n\n/* $Log:\tscore.c,v $\n * Revision 7.0.1.2a  87/07/03  02:13:26  games\n * Fixed numerous long vs. int bugs in printfs, etc.\n *\n * Revision 7.0.1.2  86/10/20  12:06:56  lwall\n * Made all exits reset tty.\n *\n * Revision 7.0.1.1  86/10/16  10:52:47  lwall\n * Added Damage.  Fixed random bugs.\n *\n * Revision 7.0  86/10/08  15:13:14  lwall\n * Split into separate files.  Added amoebas and pirates.\n *\n */\n\n#include \"EXTERN.h\"\n#include \"warp.h\"\n#include \"intrp.h\"\n#include \"object.h\"\n#include \"play.h\"\n#include \"sig.h\"\n#include \"term.h\"\n#include \"us.h\"\n#include \"util.h\"\n#include \"weapon.h\"\n#include \"INTERN.h\"\n#include \"score.h\"\n#include <unistd.h>\n#include <time.h>\n#include <math.h>\n\nvoid\nscore_init()\n{\n    register char *s;\n    register int i;\n    FILE *savfil;\n\n    if (stat(SAVEDIR,&filestat)) {\n\tprintf(\"Cannot access %s\\r\\n\",SAVEDIR);\n\tfinalize(1);\n    }\n    if (filestat.st_uid != geteuid()) {\n\tprintf(\"Warp will not run right without being setuid.\\r\\n\");\n\tfinalize(1);\n    }\n    if ((filestat.st_mode & 0605) != 0605) {\n\tprintf(\"%s is not protected correctly (must be u+rw o+rx).\\r\\n\",SAVEDIR);\n\tfinalize(1);\n    }\n\n    interp(longlognam, sizeof longlognam, \"%L\");\n    for (i=strlen(longlognam); i<8; i++)\n\tlonglognam[i] = ' ';\t/* make sure it is 8 long for strncmp */\n    longlognam[8] = '\\0';\n\n    if (scorespec)\n\twscore();\n\n    Sprintf(savefilename, \"save.%s\", logname);\n\n    savfil = experimenting ? NULL : fopen(savefilename,\"r\");\n    if (savfil != NULL && fgets(spbuf,100,savfil) != NULL) {\n\tchar tmpbuf[80];\n\n\tspbuf[strlen(spbuf)-1] = '\\0';\n\tif (fgets(tmpbuf,80,savfil) != NULL) {\n\t    int processnum;\n\n\t    tmpbuf[strlen(tmpbuf)-1] = '\\0';\n\t    printf(\"You seem to have left a game %s.\\r\\n\",tmpbuf+9);\n\t    s = strchr(tmpbuf+9, ',');\n\t    *s = '\\0';\n\t    processnum = atoi(s+11);\n\t    if (kill(processnum, SIGINT)) {\n\t\t\t\t\t/* does process not exist? */\n\t\t\t\t\t/* (warp ignores SIGINT) */\n\t\tprintf(\"\\r\\n\\\nThat process does not seem to exist anymore, so you'll have to start the\\r\\n\");\n\t\tprintf(\n\"last wave over.\\r\\n\\n\");\n\t\tprintf(\n\"                      [type anything to continue]\");\n\t\tFflush(stdout);\n\t\teat_typeahead();\n\t\tgetcmd(tmpbuf);\n\t\tif (*tmpbuf == INTRCH)\n\t\t    finalize(0);\n\t\tprintf(\"\\r\\n\");\n\t    }\n\t    else {\n\t\tif (strcmp(term+8,tmpbuf+23)) {\n\t\t    printf(\n\"That is not your current terminal--you are on %s.\\r\\n\", term+5);\n\t\t    printf(\"\\r\\nYour options:\\r\\n\");\n\t\t    printf(\"   1) Exit and find the terminal it's running on\\r\\n\");\n\t\t}\n\t\telse {\n\t\t    printf(\"\\r\\nYour options:\\r\\n\");\n\t\t    printf(\"   1) Exit and try to foreground it\\r\\n\");\n\t\t}\n\t\tprintf(\"   2) Let me terminate the other game\\r\\n\\n\");\n\t\tprintf(\"What do you want to do? \");\n\t\tFflush(stdout);\n\t\teat_typeahead();\n\t\tgetcmd(tmpbuf);\n\t\tprintf(\"\\r\\n\");\n\t\tif (*tmpbuf == INTRCH)\n\t\t    finalize(0);\n\t\tif (*tmpbuf == '1') {\n\t\t    printf(\n\"If you don't succeed, come back and do option 2 instead.  Good luck.\\r\\n\");\n\t\t    finalize(0);\n\t\t}\n\t\tprintf(\n\"Ok, hang on a few moments \\r\\n\");\n\t\tFclose(savfil);\n\t\tif (kill(processnum, SIGQUIT)) {\n\t\t    printf(\"Unable to kill process #%d!\\r\\n\",processnum);\n\t\t    roundsleep(2);\n\t\t}\n\t\telse {\n#ifdef SIGCONT\n\t\t    kill(processnum, SIGCONT);\n#endif\n\t\t    for (i=15; i; --i) {\n\t\t\tsleep(1);\n\t\t\tif (kill(processnum,SIGINT))\n\t\t\t\t\t/* does process not exist? */\n\t\t\t\t\t/* (warp ignores SIGINT) */\n\t\t\t    break;\n\t\t    }\n\t\t    didkill++;\n\t\t}\n\t\tsavfil = fopen(savefilename,\"r\");\n\t\tif (savfil != NULL) {\n\t\t    if (fgets(spbuf,100,savfil) == 0)\n\t\t        /*ignore*/;\n\t\t}\n\t    }\n\t}\n    }\n    else\n\tsavfil = NULL;\n    if (savfil == NULL) {\n\ttotalscore = smarts = cumsmarts = wave = 0;\n\tnuments = 5;\n\tnumbases = 3;\n    }\n    else {\n\ttotalscore = atol(spbuf+9);\n\tsmarts = atoi(spbuf+20);\n\tcumsmarts = atoi(spbuf+24);\n\tnuments = atoi(spbuf+30);\n\tnumbases = atoi(spbuf+33);\n\twave = atoi(spbuf+36);\n\tapolspec = (spbuf[40] == 'a');\n\tbeginner   = (spbuf[41] == 'b');\n\tcrushspec  = (spbuf[42] == 'c');\n\tgornspec   = (spbuf[43] == 'g');\n\tmassacre   = (spbuf[44] == 'm');\n\tromspec    = (spbuf[45] == 'r');\n\ttholspec   = (spbuf[46] == 't');\n\tlowspeed   = (spbuf[47] == 'l') || lowspeed;\n\tamoebaspec = (spbuf[48] == '&');\n\tFclose(savfil);\n    }\n\n    if (!ismarts) {\n\tismarts = 1;\n\tclear();\n\tpage(NEWSFILE,FALSE);\n\tif (smarts) {\n\t    printf(\"\\r\\nSaved game: SCORE DIFF CUMDIFF ENTERPRISES BASES WAVE\");\n\t    printf(\"\\r\\n          %7ld  %2d   %4d        %1d        %1d   %3d\",\n\t\ttotalscore,smarts,cumsmarts,numents,numbases,wave);\n\t}\n\tprintf(\"\\r\\nWould you like instructions? \");\n\tFflush(stdout);\n\teat_typeahead();\n\tgetcmd(buf);\n\tprintf(\"\\r\\n\");\n\tif (*buf == INTRCH)\n\t    finalize(0);\n\tif (*buf == 'Y' || *buf == 'y') {\n\t    page(HELPFILE,FALSE);\n\t    printf(\"\\r\\nWould you like to play easy games for a while? \");\n\t    Fflush(stdout);\n\t    eat_typeahead();\n\t    getcmd(buf);\n\t    printf(\"\\r\\n\");\n\t    if (*buf == 'Y' || *buf == 'y') {\n\t\tbeginner = TRUE;\n\t\tlowspeed = TRUE;\n\t    }\n\t}\n    }\n    if (!smarts)\n\tsmarts = ismarts;\n}\n\nvoid\nwscore()\n{\n    clear();\n    printf(\"                             TOP WARPISTS\\r\\n\\n\");\n    printf(\"RANK  WHO                     AKA        SCORE DIFF  CUMDIFF  WHEN\\r\\n\");\n    page(SCOREBOARD,TRUE);\n    printf(\"                     [Type anything to continue]\");\n    Fflush(stdout);\n    getcmd(spbuf);\n    if (*spbuf == INTRCH)\n\tfinalize(0);\n    clear();\n    printf(\"                        TOP LOW-SPEED WARPISTS\\r\\n\\n\");\n    printf(\"RANK  WHO                     AKA        SCORE DIFF  CUMDIFF  WHEN\\r\\n\");\n    page(LSCOREBOARD,TRUE);\n    printf(\"                     [Type anything to continue]\");\n    Fflush(stdout);\n    getcmd(spbuf);\n    if (*spbuf == INTRCH)\n\tfinalize(0);\n    clear();\n    printf(\"                          TOP FUNNY WARPISTS\\r\\n\\n\");\n    printf(\"RANK  WHO                     AKA        SCORE DIFF  CUMDIFF  WHEN\\r\\n\");\n    page(FSCOREBOARD,TRUE);\n    printf(\"                     [Type anything to continue]\");\n    Fflush(stdout);\n    getcmd(spbuf);\n    if (*spbuf == INTRCH)\n\tfinalize(0);\n    clear();\n    printf(\"          GAMES SAVED OR IN PROGRESS\\r\\n\\n\");\n    printf(\"WHO           SCORE  DF   CDF  E  B  WV  FLAGS\\r\\n\");\n    resetty();\n    Sprintf(spbuf,\"/bin/cat %ssave.*\",SAVEDIR);\n    execl(\"/bin/sh\", \"sh\", \"-c\", spbuf, (char*)0);\n    finalize(1);\n}\n\n\nvoid\ndisplay_status()\n{\n    register int tmp;\n    static char *status_names[] = {\"Impl\", \"Warp\", \"Base\", \"****\" };\n\n    if (oldstatus != status) {\n\tSprintf(spbuf,\"%-4s\",status_names[status]);\n\tmvaddstr(0,0, spbuf);\n\toldstatus = status;\n    }\n    if (ent) {\n\tif (ent->energy != oldeenergy) {\n\t    oldeenergy = ent->energy;\n\t    Sprintf(spbuf,\"%4ld\",oldeenergy);\n\t    mvaddstr(0,8, spbuf);\n\t}\n\tif (etorp != oldetorp) {\n\t    Sprintf(spbuf,\"%2d\",etorp);\n\t    mvaddstr(0,13, spbuf);\n\t    oldetorp = etorp;\n\t}\n    }\n    else {\n\tif (etorp >= 0) {\n\t    etorp = -1;\n\t    mvaddstr(0,8,\"*******\");\n\t    damage = 0;\n\t}\n    }\n    if (base) {\n\tif (base->energy != oldbenergy) {\n\t    oldbenergy = base->energy;\n\t    Sprintf(spbuf,\"%5ld\",oldbenergy);\n\t    mvaddstr(0,19, spbuf);\n\t}\n\tif (btorp != oldbtorp) {\n\t    Sprintf(spbuf,\"%3d\",btorp);\n\t    mvaddstr(0,25, spbuf);\n\t    oldbtorp = btorp;\n\t}\n    }\n    else {\n\tif (btorp >= 0) {\n\t    btorp = -1;\n\t    mvaddstr(0,19,\"*********\");\n\t}\n    }\n    if (damage) {\n\tif (!olddamage)\n\t    mvaddstr(0,42,\"*** \");\n\tif (damage > 1 || !damflag[dam]) {\n\t    do {\n\t\tif (++dam == MAXDAMAGE)\n\t\t    dam = 0;\n\t    } while (!damflag[dam]);\n\t}\n\tif (!--damflag[dam]) {\n\t    olddamage = damage;\n\t    damage--;\n\t    Sprintf(spbuf,\"%s OK ***       \",dammess[dam]);\n\t    spbuf[15] = '\\0';\n\t    mvaddstr(0,46,spbuf);\n\t}\n\telse if (dam == NOSHIELDS) {\n\t    olddamage = damage;\n\t    tmp = (34 - damflag[dam]) * 3 - rand_mod(3);\n\t    if (tmp < 0)\n\t\ttmp = 0;\n\t    Sprintf(spbuf,\"%d%% %s ***       \",tmp,dammess[dam]);\n\t    spbuf[15] = '\\0';\n\t    mvaddstr(0,46,spbuf);\n\t}\n\telse if (dam != lastdam || !olddamage) {\n\t    olddamage = damage;\n\t    Sprintf(spbuf,\"NO %s ***       \",dammess[dam]);\n\t    spbuf[15] = '\\0';\n\t    mvaddstr(0,46,spbuf);\n\t}\n\tif (status < 2) {\n\t    if (dam == NOIMPULSE && !entmode)\n\t\tstatus = entmode = 1;\n\t    if (dam == NOWARP && entmode)\n\t\tstatus = entmode = 0;\n\t}\n\ttmp = damflag[dam] * damage;\n\tSprintf(spbuf,\"%3d.%1d ETR\",tmp/10,tmp%10);\n\tmvaddstr(0,69,spbuf);\n\tlastdam = dam;\n    }\n    else {\n\tif (olddamage) {\n\t    Sprintf(spbuf,\"Stars: %-3d Stardate\",numstars);\n\t    mvaddstr(0,42,spbuf);\n\t    lastdam = -1;\n\t    olddamage = 0;\n\t    oldcurscore = -1;\n\t}\n\telse if (numstars != oldstrs) {\n\t    Sprintf(spbuf,\"%-3d\",numstars);\n\t    mvaddstr(0,49, spbuf);\n\t}\n\toldstrs = numstars;\n    }\n    if (numenemies != oldenemies) {\n\tSprintf(spbuf,\"%-3d\",numenemies);\n\tmvaddstr(0,38, spbuf);\n\toldenemies = numenemies;\n    }\n    if (tmp = timer%10) {\n\tSprintf(spbuf,\"%1d\",tmp);\n\tmvaddstr(0,67, spbuf);\n    }\n    else {\n\tSprintf(spbuf,\"%5d.%1d\",timer/10+smarts*100,tmp);\n\tmvaddstr(0,61, spbuf);\n    }\n    if ((!damage || !damflag[dam]) && curscore != oldcurscore) {\n\tSprintf(spbuf,\"%9ld\",curscore);\n\tmvaddstr(0,69, spbuf);\n\toldcurscore = curscore;\n    }\n}\n\nvoid\nwavescore()\n{\n    double power, effectscore, starscore, pi_over_2;\n    long bonuses;\n    long tmp;\n    FILE *mapfp;\n    int row;\n\n    clear();\n    if (curscore > possiblescore)\n\tcurscore = possiblescore;\n    pi_over_2 = 3.14159265 / 2.0;\n    power = pow((double)inumenemies+     /* total number of enemies */\n\t\t\tinumroms*2+      /* count roms 3 times */\n\t\t\tinumgorns+       /* count gorns 2 times */\n\t\t\tinumthols+       /* count thols 2 times */\n\t\t\tinumapollos*4+   /* count apollo 5 times */\n\t\t\tinumcrushes*3+   /* count crushers 4 times */\n\t\t\tinumamoebas*5\t /* count amoebas 6 times */\n\t    , 0.50) *                    /* skew it a little */\n\t    (double)smarts;              /* average energy and intelligence */\n    if (inumstars < 350 && inumenemies > 5)\n\t    power += (350.0 - (double)inumstars) * ((double)inumenemies - 5.0);\n    if (inumstars > 850 && inumenemies > 2)\n\t    power += ((double)inumstars - 850.0) * ((double)inumenemies - 2.0);\n    effectscore = ((double)curscore / possiblescore) *\n\tatan2(power, (double) timer + 1.0) / pi_over_2;\n    if (inumstars)\n\tstarscore = (double) numstars / (double) inumstars;\n    else\n\tstarscore = 1.0;\n    wave++;\n    Sprintf(spbuf,\"Wave = %d, Difficulty = %d, cumulative difficulty = %d\",\n\t wave, smarts, cumsmarts);\n    mvaddstr(1, 13+(smarts<10), spbuf);\n    mvaddstr( 4, 68, \" BONUS\");\n    Sprintf(spbuf,\"Efficiency rating:       %1.8f (diff=%0.2f,time=%d)\",\n\t effectscore, power, timer + 1);\n    mvaddstr( 5,5, spbuf);\n    if (effectscore < 0.8)\n\tbonuses = tmp = 0;\n    else\n\tbonuses = tmp = (long) ((effectscore-0.8) * smarts * 1000);\n    Sprintf(spbuf, \"%6ld\", tmp);\n    mvaddstr( 5, 68, spbuf);\n    Sprintf(spbuf,\"Star save ratio:         %1.8f (%d/%d)\",\n\tstarscore, numstars, inumstars);\n    mvaddstr( 6,5, spbuf);\n    bonuses += tmp = (long) (((double)curscore / possiblescore) *\n\t(starscore*starscore) * smarts * 20);\n    Sprintf(spbuf, \"%6ld\", tmp);\n    mvaddstr( 6, 68, spbuf);\n    row = 7;\n    if (inuminhab != numinhab) {\n\tSprintf(spbuf, \"Inhabited stars depopulated:  %5d\", inuminhab-numinhab);\n\tmvaddstr(row,5, spbuf);\n\tbonuses += tmp = (long) (inuminhab-numinhab) * -500;\n\tSprintf(spbuf, \"%6ld\", tmp);\n\tmvaddstr(row, 68, spbuf);\n\trow++;\n    }\n    if (inumfriends != numfriends) {\n\tSprintf(spbuf, \"Friendly craft destroyed:     %5d\",\n\t    inumfriends-numfriends);\n\tmvaddstr(row,5, spbuf);\n\tbonuses += tmp = (long) (inumfriends-numfriends) * -250;\n\tSprintf(spbuf, \"%6ld\", tmp);\n\tmvaddstr(row, 68, spbuf);\n\trow++;\n    }\n    if (deadmudds) {\n\tmvaddstr(row,5,\"For destroying Harry Mudd:\");\n\tbonuses += tmp = (long) rand_mod(deadmudds * 20 + 1) - deadmudds*10;\n\tSprintf(spbuf, \"%6ld\", tmp);\n\tmvaddstr(row, 68, spbuf);\n\trow++;\n    }\n    if (bombed_out) {\n\tmvaddstr(row,5, \"For running away from reality:\");\n\tbonuses += tmp = (long) -possiblescore/2;\n\tSprintf(spbuf, \"%6ld\", tmp);\n\tmvaddstr(row, 68,  spbuf);\n\trow++;\n    }\n    if (row < 9)\n\trow++;\n    Sprintf(spbuf, \"Enterprise: %-9s%5d remaining\",\n\t!ient?\"\":ent?\"saved\":\"destroyed\", numents);\n    mvaddstr(row,5, spbuf);\n    bonuses += tmp = ent && !bombed_out ? (smarts+1)*15 : 0;\n    Sprintf(spbuf, \"%6ld\", tmp);\n    mvaddstr(row, 68, spbuf);\n    row++;\n    Sprintf(spbuf, \"Base: %-9s      %5d remaining\",\n\t!ibase?\"\":base?\"saved\":\"destroyed\", numbases);\n    mvaddstr(row,5, spbuf);\n    bonuses += tmp = base && !bombed_out ? (smarts+1)*10 : 0;\n    Sprintf(spbuf, \"%6ld\", tmp);\n    mvaddstr(row, 68,  spbuf);\n    if (beginner) {\n\tmvaddstr(13+(row>11),19, \"(Special games count only a tenth as much)\");\n\tcurscore /= 10;\n\tbonuses /= 10;\n    }\n    Sprintf(spbuf, \"Previous point total:%10ld\",lastscore);\n    mvaddstr(15,24, spbuf);\n    Sprintf(spbuf, \"Points this round:   %10ld\",curscore);\n    mvaddstr(16,24, spbuf);\n    Sprintf(spbuf, \"Bonuses:             %10ld\",bonuses);\n    mvaddstr(17,24, spbuf);\n    totalscore = lastscore + curscore + bonuses;\n    Sprintf(spbuf, \"New point total:     %10ld\",totalscore);\n    mvaddstr(18,24, spbuf);\n    if (lastscore / ENTBOUNDARY < totalscore / ENTBOUNDARY) {\n\tmvaddstr(row-1,42,\"+ 1 new\");\n\tnuments++;\n    }\n    else if (numents>0 &&\n\tlastscore / ENTBOUNDARY > totalscore / ENTBOUNDARY) {\n\tmvaddstr(row-1,42,\"- 1 obsolete\");\n\tnuments--;\n    }\n    if (lastscore / BASEBOUNDARY < totalscore / BASEBOUNDARY) {\n\tmvaddstr(row,42,\"+ 1 new\");\n\tnumbases++;\n    }\n    else if (numbases>0 &&\n\tlastscore / BASEBOUNDARY > totalscore / BASEBOUNDARY) {\n\tmvaddstr(row,42,\"- 1 obsolete\");\n\tnumbases--;\n    }\n    if (starscore < 0.8 && inumstars > 200 && numstars > 50) {\n\tSprintf(spbuf, \"smap.%d\",rand_mod(MAPS-PERMMAPS)+PERMMAPS);\n\tif ((mapfp = fopen(spbuf,\"w\")) != NULL) {\n\t    register OBJECT *obj;\n\n\t    fprintf(mapfp,\"%d\\n\",numstars);\n\t    for (obj = root.next; obj != &root; obj = obj->next) {\n\t\tif (obj->type == Star) {\n\t\t    fprintf(mapfp,\"%d %d\\n\",obj->posy,obj->posx);\n\t\t}\n\t    }\n\t    Fclose(mapfp);\n\t}\n    }\n}\n\nvoid\nscore()\n{\n    char tmp, *retval, cdate[30];\n    register FILE *logfd;\n    register FILE *outfd;\n    register int i;\n    long nowtime;\n    char *scoreboard;\n\n    for (i=0; link(LOGFILE, LOCKFILE) == -1 && i<10; i++)\n\tsleep(1);\n    nowtime = time((long *)0);\n    strcpy(cdate,ctime(&nowtime));\n    if ((logfd = fopen(LOGFILE,\"a\")) != NULL) {\n\tfprintf(logfd,\n\t    \"%-24s%-9s%7ld%c%2d %4d %s\",\n\t    realname, logname, totalscore, c,smarts, cumsmarts, cdate);\n\tFclose(logfd);\n    }\n    strcpy(cdate+11,cdate+20);\n    if (beginner)\n\tscoreboard = FSCOREBOARD;\n    else if (lowspeed)\n\tscoreboard = LSCOREBOARD;\n    else\n\tscoreboard = SCOREBOARD;\n    if (eaccess(scoreboard,0)) {\n\tif ((logfd = fopen(scoreboard,\"w\")) != NULL)\n\t    Fclose(logfd);\n    }\n    if ((logfd = fopen(scoreboard,\"r\")) != NULL &&\n\t(outfd = fopen(TMPSCOREBOARD,\"w\")) != NULL) {\n\tfor (i=0; i<20; i++) {\n\t    if ((retval = fgets(buf, 100, logfd)) == NULL)\n\t\tbreak;\n\t    if (atol(buf+32) < totalscore)\n\t\tbreak;\n\t    if (strnEQ(buf+COMPOFF,COMPNAME,COMPLEN)) {\n\t\ti = 100;\n\t\tbreak;\n\t    }\n\t    fprintf(outfd, \"%s\", buf);\n\t}\n\tif (i == 100) {\n\t    mvaddstr(20,21, \"You did not better your previous score\");\n\t    Fclose(outfd);\n\t    unlink(TMPSCOREBOARD);\n\t}\n\telse if (i < 20) {\n\t    fprintf(outfd, \"%-24s%-8s%8ld%c %2d    %4d    %s\",\n\t\trealname, logname, totalscore, c,smarts, cumsmarts, cdate);\n\t    i++;\n\t    Sprintf(spbuf, \"    Congratulations--you've placed %d%s\",\n\t      i, i==1?\"st\":(i==2?\"nd\":(i==3?\"rd\":\"th\")));\n\t    if (retval != NULL) {\n\t\tif (strnNE(buf+COMPOFF,COMPNAME,COMPLEN)) {\n\t\t    fprintf(outfd, \"%s\", buf);\n\t\t    i++;\n\t\t}\n\t\telse\n\t\t    strcpy(spbuf,\"Congratulations--you've bettered your score\");\n\t\twhile (i<20) {\n\t\t    if (fgets(buf, 100, logfd) == NULL)\n\t\t\tbreak;\n\t\t    if (strnNE(buf+COMPOFF,COMPNAME,COMPLEN)) {\n\t\t\tfprintf(outfd, \"%s\", buf);\n\t\t\ti++;\n\t\t    }\n\t\t}\n\t    }\n\t    mvaddstr(20,19, spbuf);\n\t    Fclose(logfd);\n\t    Fclose(outfd);\n\t    while (unlink(scoreboard) == 0)\n\t\t;\n\t    link(TMPSCOREBOARD,scoreboard) >= 0;\n\t    unlink(TMPSCOREBOARD);\n\t    logfd = fopen(scoreboard,\"r\");\n\t}\n\telse {\n\t    mvaddstr(20,22,\"You did not place within the top 20\");\n\t    Fclose(outfd);\n\t}\n    }\n    else {\n\tSprintf(spbuf,\"(Cannot access %s file, error %d)\",\n\t    (logfd==NULL?\"log\":\"tmp\"),errno);\n\tmvaddstr(20,22,spbuf);\n    }\n    move(23,0,0);\n    erase_eol();\n    mvaddstr(23,11,\n\t\"[Hit space for scoreboard, 'r' for new game, 'q' to quit]\");\n    unlink(LOCKFILE);\n    Fflush(stdout);\n    eat_typeahead();\n    do {\n\tgetcmd(&tmp);\n    } while (tmp != INTRCH && tmp != BREAKCH && !strchr(\" rqQ\",tmp));\n    if (strchr(\"qQr\",tmp)) {\n\tjustonemoretime = (tmp == 'r');\n\tif (logfd != NULL)\n\t    Fclose(logfd);\n    }\n    else {\n\tclear();\n\tif (logfd != NULL) {\n\t    fseek(logfd, 0L, 0);\n\t    if (beginner)\n\t\tmvaddstr(0,31,\"TOP FUNNY WARPISTS\");\n\t    else if (lowspeed)\n\t\tmvaddstr(0,29,\"TOP LOW-SPEED WARPISTS\");\n\t    else\n\t\tmvaddstr(0,33,\"TOP WARPISTS\");\n\t    mvaddstr(2,0,\"RANK  WHO                     AKA        SCORE DIFF  CUMDIFF  WHEN\");\n\t    for (i=1; i<=20; i++) {\n\t\tif (fgets(buf, 100, logfd) == NULL)\n\t\t    break;\n\t\tbuf[strlen(buf)-1] = '\\0';\n\t\tSprintf(spbuf, \" %2d   %s\", i, buf);\n\t\tmvaddstr(i+2,0, spbuf);\n\t    }\n\t    Fclose(logfd);\n\t}\n\troundsleep(1);\n\tmvaddstr(23,25,\"Would you like to play again?\");\n\teat_typeahead();\n\tdo {\n\t    getcmd(&tmp);\n\t} while (tmp != INTRCH && tmp != BREAKCH && !strchr(\"nNyY \\n\\r\",tmp));\n\tif (tmp == 'n' || tmp == 'N' || tmp == INTRCH || tmp == BREAKCH)\n\t    justonemoretime = FALSE;\n    }\n\n    smarts = ismarts;\n    totalscore = cumsmarts = wave = 0;\n    numents = 5;\n    numbases = 3;\n    apolspec = FALSE;\n    beginner   = FALSE;\n    crushspec  = FALSE;\n    gornspec   = FALSE;\n    massacre   = (ismarts >= 40);\n    romspec    = FALSE;\n    tholspec   = FALSE;\n}\n\nvoid\nsave_game()\n{\n    FILE *savfil;\n\n    if (experimenting)\n\treturn;\n    if ((savfil = fopen(savefilename,\"w\")) == NULL) {\n\tresetty();\n\tprintf(\"Cannot save game\\r\\n\");\n\tfinalize(1);\n    }\n    fprintf(savfil, \"%-8s %10ld, %2d,%5d,%2d,%2d,%3d %c%c%c%c%c%c%c%c\\n\",\n\tlogname, totalscore, smarts, cumsmarts, numents, numbases, wave,\n\tapolspec ? 'a' : ' ',\n\tbeginner   ? 'b' : ' ',\n\tcrushspec  ? 'c' : ' ',\n\tgornspec   ? 'g' : ' ',\n\tmassacre   ? 'm' : ' ',\n\tromspec    ? 'r' : ' ',\n\ttholspec   ? 't' : ' ',\n\tlowspeed   ? 'l' : ' ',\n\tamoebaspec ? '&' : ' '\n    );\n    Fclose(savfil);\n    resetty();\n    if (panic)\n\tfinalize(0);\n    clear();\n    finalize(0);\n}\n"
  },
  {
    "path": "games/warp/score.h",
    "content": "/* $Header: score.h,v 7.0 86/10/08 15:13:21 lwall Exp $ */\n\n/* $Log:\tscore.h,v $\n * Revision 7.0  86/10/08  15:13:21  lwall\n * Split into separate files.  Added amoebas and pirates.\n * \n */\n\n#define ENTBOUNDARY 100000\t/*  point boundary across which a new E is\n\t\t\t\t\tawarded */\n\n#define BASEBOUNDARY 250000\t/*  point boundary across which a new B is\n\t\t\t\t\tawarded */\n\nEXT int oldstatus;\nEXT int oldetorp;\nEXT int oldbtorp;\nEXT int oldstrs;\nEXT int oldenemies;\n\nEXT long totalscore;\nEXT long lastscore INIT(0);\nEXT long curscore;\nEXT long possiblescore;\nEXT long oldeenergy;\nEXT long oldbenergy;\nEXT long oldcurscore;\n\nEXT char savefilename[40];\n\n#ifdef SCOREFULL\n#define COMPOFF 0\n#define COMPNAME longlognam\n#define COMPLEN 24\n#else\n#define COMPOFF 24\n#define COMPNAME longlognam\n#define COMPLEN 8\n#endif\nEXT char longlognam[128];\n\nEXT char c INIT(' ');\n\nvoid score_init();\nvoid wscore();\nvoid display_status();\nvoid wavescore();\nvoid score();\nvoid save_game();\n"
  },
  {
    "path": "games/warp/sig.c",
    "content": "/* $Header: /usr/src/games/warp/RCS/sig.c,v 1.1 87/07/03 01:47:11 games Exp $ */\n\n/* $Log:\tsig.c,v $\n * Revision 7.0.1.2   99/10/24\n * Update to sigprocmask.\n *\n * Revision 7.0.1.1a  87/07/03  01:47:11  games\n * Changed sigsetmask to use sigmask instead of calculating it (incorrectly)\n * by hand.\n *\n * Revision 7.0.1.1  86/12/12  17:02:44  lwall\n * Baseline for net release.\n *\n * Revision 7.0  86/10/08  15:13:24  lwall\n * Split into separate files.  Added amoebas and pirates.\n *\n */\n\n#include \"EXTERN.h\"\n#include \"warp.h\"\n#include \"play.h\"\n#include \"score.h\"\n#include \"term.h\"\n#include \"util.h\"\n#include \"INTERN.h\"\n#include \"sig.h\"\n\nvoid\nsig_init()\n{\n    sigignore(SIGINT);  /* for inquiry of existence via kill call */\n#ifdef SIGTTOU\n    sigignore(SIGTTOU);\n#endif\n\n    sigset(SIGHUP, sig_catcher);\n    if (!debugging) {\n\tsigset(SIGQUIT, sig_catcher);\n\tsigset(SIGILL, sig_catcher);\n\tsigset(SIGFPE, sig_catcher);\n\tsigset(SIGBUS, sig_catcher);\n\tsigset(SIGSEGV, sig_catcher);\n\tsigset(SIGSYS, sig_catcher);\n\tsigset(SIGTERM, sig_catcher);\n    }\n#ifdef SIGXCPU\n    sigset(SIGXCPU, sig_catcher);\n#endif\n#ifdef SIGCONT\n    sigset(SIGCONT, cont_catcher);\n#endif\n#ifdef SIGTSTP\n    sigset(SIGTSTP, stop_catcher);\n    sigset(SIGSTOP, stop_catcher);\n#endif\n}\n\n#ifdef SIGTSTP\nvoid\ncont_catcher()\n{\n    sigset(SIGCONT,cont_catcher);\n    savetty();\n    crmode();\n    raw();\n    noecho();\n    nonl();\n}\n#endif\n\nvoid\nmytstp()\n{\n    resetty();\n#ifdef SIGTSTP\n    kill(0,SIGTSTP);\n#else\n    if (fork())\n\twait(0);\n    else {\n\tchar *shell = getenv(\"SHELL\");\n\n\tsetuid(getuid());\n\tif (!*shell)\n\t    shell = \"/bin/sh\";\n\texecl(shell,shell,0);\n\texit(1);\n    }\n#endif\n    rewrite();\n}\n\nvoid\t\t\t\t\t/* very much void */\nfinalize(status)\nint status;\n{\n    if (bizarre)\n\tresetty();\n    if (status < 0) {\n\tchdir(\"/usr/tmp\");\n\tsigset(SIGILL,SIG_DFL);\n\tabort();\n    }\n    exit(status);\n}\n\n/* come here on signal other than interrupt, stop, or cont */\n\nvoid\nsig_catcher(signo)\n{\n#ifdef VERBOSE\n    static char *signame[] = {\n\t\"\",\n\t\"HUP\",\n\t\"INT\",\n\t\"QUIT\",\n\t\"ILL\",\n\t\"TRAP\",\n\t\"IOT\",\n\t\"EMT\",\n\t\"FPE\",\n\t\"KILL\",\n\t\"BUS\",\n\t\"SEGV\",\n\t\"SYS\",\n\t\"PIPE\",\n\t\"ALRM\",\n\t\"TERM\",\n\t\"???\"\n#ifdef SIGTSTP\n\t,\"STOP\",\n\t\"TSTP\",\n\t\"CONT\",\n\t\"CHLD\",\n\t\"TTIN\",\n\t\"TTOU\",\n\t\"TINT\",\n\t\"XCPU\",\n\t\"XFSZ\"\n#ifdef SIGPROF\n\t,\"VTALARM\",\n\t\"PROF\"\n#endif\n#endif\n\t};\n#endif\n\n#ifdef SIGTTOU\n    sigignore(SIGTTOU);\n#endif\n#ifdef DEBUGGING\n    if (debug) {\n\tprintf(\"\\r\\nSIG%s--game not saved in debug\\r\\n\",signame[signo]);\n\tfinalize(-1);\n    }\n#endif\n    panic++;\n    if (panic >= 2) {\n\tif (panic >= 3)\n\t    abort();\n\tchdir(SAVEDIR);\n\tkill(0,SIGIOT);\n    }\n    (void) sigset(SIGILL,SIG_DFL);\n    if (signo == SIGHUP && (timer < 10 || didkill))\n\tsigno = SIGQUIT;\n    if (signo == SIGQUIT) {\t/* can't let them bomb out without penalty */\n\tif (smarts < 20)\n\t    smarts += 4;\n\telse if (smarts < 35)\n\t    smarts += 2;\n\telse\n\t    smarts++;\n\ttotalscore -= possiblescore / 2;\n    }\n    save_game();\n    if (signo != SIGHUP && signo != SIGQUIT)\n#ifdef VERBOSE\n\tIF(verbose)\n\t    printf(\"\\r\\nCaught %s%s--%s\\r\\n\",\n\t\tsigno ? \"a SIG\" : \"an internal error\", signame[signo],\n\t\texperimenting ? \"game saved\" : \"bye bye\");\n\tELSE\n#endif\n#ifdef TERSE\n\t    printf(\"\\r\\nSignal %d--bye bye\\r\\n\",signo);\n#endif\n    switch (signo) {\n    case SIGBUS:\n    case SIGILL:\n    case SIGSEGV:\n\tfinalize(-signo);\n    }\n    finalize(1);\t\t\t\t/* and blow up */\n}\n\n#ifdef SIGTSTP\n/* come here on stop signal */\n\nvoid\nstop_catcher()\n{\n    sigset_t set;\n\n    if (!waiting) {\n\tresetty();\t\t\t/* this is the point of all this */\n#ifdef DEBUGGING\n\tif (debug)\n\t    write(2,\"stop_catcher\\r\\n\",13);\n#endif\n\tsigset(SIGTSTP,SIG_DFL);\t/* enable stop */\n\t(void)sigemptyset(&set);\n\t(void)sigaddset(&set, SIGTSTP);\n\t(void)sigprocmask(SIG_UNBLOCK, &set, NULL);\n\tkill(0,SIGTSTP);\t\t/* and do the stop */\n    }\n    sigset(SIGTSTP,stop_catcher);\t/* unenable the stop */\n}\n#endif\n"
  },
  {
    "path": "games/warp/sig.h",
    "content": "/* $Header: sig.h,v 7.0 86/10/08 15:13:32 lwall Exp $ */\n\n/* $Log:\tsig.h,v $\n * Revision 7.0  86/10/08  15:13:32  lwall\n * Split into separate files.  Added amoebas and pirates.\n * \n */\n\nvoid sig_catcher();\n#ifdef SIGTSTP\nvoid cont_catcher();\nvoid stop_catcher();\n#endif\nvoid mytstp();\nvoid sig_init();\nvoid finalize();\n"
  },
  {
    "path": "games/warp/sm.c",
    "content": "/* $Header: sm.c,v 7.0 86/10/08 15:13:35 lwall Exp $ */\n\n/* $Log:\tsm.c,v $\n * Revision 7.0  86/10/08  15:13:35  lwall\n * Split into separate files.  Added amoebas and pirates.\n *\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <ctype.h>\n\nint main()\n{\n    char screen[23][90];\n    register int y;\n    register int x;\n    int tmpy, tmpx;\n\n    for (x=0; x<79; x++)\n\tscreen[0][x] = ' ';\n    screen[0][79] = '\\0';\n\n    if (fgets(screen[0], 90, stdin) == 0) {\n        perror(\"stdin\");\n        return 1;\n    }\n    if (isdigit(screen[0][0])) {\n\tint numstars = atoi(screen[0]);\n\n\tfor (y=0; y<23; y++) {\n\t    for (x=0; x<79; x++)\n\t\tscreen[y][x] = ' ';\n\t    screen[y][79] = '\\0';\n\t}\n\n\tfor ( ; numstars; numstars--) {\n\t    if (scanf(\"%d %d\\n\", &tmpy, &tmpx) != 2) {\n                perror(\"two numbers expected\");\n                return 1;\n            }\n\n\t    y = tmpy;\n\t    x = tmpx;\n\t    screen[y][x+x] = '*';\n\t}\n\n\tfor (y=0; y<23; y++) {\n\t    printf(\"%s\\n\",screen[y]);\n\t}\n    }\n    else {\n\tregister int numstars = 0;\n\n\tfor (y=1; y<23; y++) {\n\t    for (x=0; x<79; x++)\n\t\tscreen[y][x] = ' ';\n\t    screen[y][79] = '\\0';\n\t}\n\n\tfor (y=1; y<23; y++) {\n\t    if (fgets(screen[y], 90, stdin) == 0) {\n                perror(\"stdin\");\n                return 1;\n            }\n\t}\n\n\tfor (y=0; y<23; y++) {\n\t    for (x=0; x<80; x += 2) {\n\t\tif (screen[y][x] == '*') {\n\t\t    numstars++;\n\t\t}\n\t\telse if (screen[y][x] == '\\t' || screen[y][x+1] == '\\t') {\n\t\t    fprintf(stderr,\"Cannot have tabs in starmap--please expand.\\n\");\n\t\t    exit(1);\n\t\t}\n\t    }\n\t}\n\n\tprintf(\"%d\\n\",numstars);\n\n\tfor (y=0; y<23; y++) {\n\t    for (x=0; x<80; x += 2) {\n\t\tif (screen[y][x] == '*') {\n\t\t    printf(\"%d %d\\n\",y,x/2);\n\t\t}\n\t    }\n\t}\n    }\n    exit(0);\n}\n"
  },
  {
    "path": "games/warp/smp.0",
    "content": "*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n"
  },
  {
    "path": "games/warp/smp.1",
    "content": "  *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *\n  *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *\n  *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *\n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n  *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *\n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n*   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *  \n  *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *\n  *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *\n  *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *   *\n"
  },
  {
    "path": "games/warp/smp.2",
    "content": "* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n*   * * * *   *                       \n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n*   * * * *   *                       \n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n*   * * * *   *                       \n*   * * * *   *                       \n*   * * * *   *                       \n*   * * * *   *                       \n*   * * * *   *                       \n*   * * * *   *                       \n*   * * * *   *                       \n*   * * * *   *                       \n*   * * * *   *                       \n*   * * * *   *                       \n*   * * * *   *                       \n*   * * * *   *                       \n*   * * * *   *                       \n*   * * * *   *                       \n*   * * * *   *                       \n"
  },
  {
    "path": "games/warp/smp.3",
    "content": "        * * * *        \n    * * *     * * *    \n  * * *   * *   * * *  \n  * *   * * * *   * *  \n* *   * *     * *   * *\n*   * *   * *   * *   *\n*   * *   * *   * *   *\n* *   * *     * *   * *\n  * *   * * * *   * * \n  * * *   * *   * * * \n    * * *     * * * \n        * * * * \n\n\n\n\n\n\n\n\n\n\n\n"
  },
  {
    "path": "games/warp/smp.4",
    "content": "* * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *\n* * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *\n* * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *\n* * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *\n\n* * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *\n* * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *\n* * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *\n* * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *\n\n* * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *\n* * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *\n* * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *\n\n* * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *\n* * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *\n* * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *\n* * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *\n\n* * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *\n* * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *\n* * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *   * * * *\n\n"
  },
  {
    "path": "games/warp/smp.5",
    "content": "* * *\n*   *\n* * *\n\n\n\n\n\n\n\n\n                                        * * *\n                                        *   *\n                                        * * *\n\n\n\n\n\n\n\n\n\n"
  },
  {
    "path": "games/warp/smp.6",
    "content": "      * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n              * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n* * *               * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n* * * * * *             * * * * * * * * * * *           * * * * * * * * * * * *\n* * * * * * * * *         * * * * * * * *                   * * * * * * * * * *\n* * * * * * * * * *       * * * * * * *         * * *       * * * * * * * * * *\n* * * * * * * * * *       * * * * * *       * * * * * * *     * * * * * * * * *\n* * * * * * * * *         * * * * * *     * * * * * * * *       * * * * * * * *\n* * * * * * * * *       * * * * * * *   * * * * * * * * *       * * * * * * * *\n* * * * * * * *       * * * * * * * *   * * * * * * * * * *         * * * * * *\n* * * * * *         * * * * * * * * *   * * * * * * * * * * *       * * * * * *\n* * * * *       * * * * * * * * * * *   * * * * * * * * * * * *     * * * * * *\n* * * * *     * * * * * * * *       *   * * * * * * * * * * * *     * * * * * *\n* * * * *     * * * * * * *         *   * * * * * * * * * * *       * * * * * *\n* * * * *     * * * * * *           *   * * * * * * * * * *       * * * * * * *\n* * * * * *     * * * *     * * *       * * * * * * * * * *     * * * * * * * *\n* * * * * * *             * * * *       * * * * * * * * *         * * * * * * *\n* * * * * * * * * * * * * * * * * * * * * * * * * * * *       * * * * * * * * *\n* * * * * * * * * * * * * * * * * * * * * * * * * * * *       * * * * * * * * *\n* * * * * * * * * * * * * * * * * * * * * * * * * * * *       * * * * * * * * *\n* * * * * * * * * * * * * * * * * * * * * * * * * * * *           * * * * * * *\n* * * * * * * * * * * * * * * * * * * * * * * * * * * * *                   * *\n* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *\n"
  },
  {
    "path": "games/warp/smp.7",
    "content": "* * *                                                                     * * *\n* * * * * * *\n      * * * * * * *\n            * * * * * *                       * * * * *\n                  * * * *                 * * * * * * * * *\n                    * * *               * * * *       * * *\n                    * * *             * * *               * *\n                  * * * *             * *                 * * *\n                  * * *               *                   * * *\n                * * *                 *                     * * * *\n            * * * *                   *                       * * *\n          * * *                       *                         * *\n          * *                 * * *   *                         * *\n          * *               * * * *   *                       * * *\n          * *             * * * * *   *                     * * *\n            * *         * *       * * *                     * *\n              * * * * * *         * * *                   * * * *\n                                                        * * *\n                                                        * * *\n                                                        * * *\n                                                        * * * * *\n                                                          * * * * * * * * *\n                                                                          * * *\n"
  },
  {
    "path": "games/warp/term.c",
    "content": "/* $Header: term.c,v 7.0.1.2 86/12/12 17:04:09 lwall Exp $ */\n\n/* $Log:\tterm.c,v $\n * Revision 7.0.1.2  86/12/12  17:04:09  lwall\n * Baseline for net release.\n *\n * Revision 7.0.1.1  86/10/16  10:53:20  lwall\n * Added Damage.  Fixed random bugs.\n *\n * Revision 7.0  86/10/08  15:14:02  lwall\n * Split into separate files.  Added amoebas and pirates.\n *\n */\n\n#include \"EXTERN.h\"\n#include \"warp.h\"\n#include \"bang.h\"\n#include \"intrp.h\"\n#include \"object.h\"\n#include \"play.h\"\n#include \"score.h\"\n#include \"sig.h\"\n#include \"us.h\"\n#include \"util.h\"\n#include \"weapon.h\"\n#include \"INTERN.h\"\n#include \"term.h\"\n#include <unistd.h>\n\nint typeahead = FALSE;\n\nchar tcarea[TCSIZE];\t/* area for \"compiled\" termcap strings */\n\n/* guarantee capability pointer != Nullch */\n/* (I believe terminfo will ignore the &tmpaddr argument.) */\n\n#define Tgetstr(key) ((tstr = tgetstr(key,&tmpaddr)) ? tstr : nullstr)\n\n#ifdef PUSHBACK\nstruct keymap {\n    char km_type[128];\n    union km_union {\n\tstruct keymap *km_km;\n\tchar *km_str;\n    } km_ptr[128];\n};\n\n#define KM_NOTHIN 0\n#define KM_STRING 1\n#define KM_KEYMAP 2\n#define KM_BOGUS 3\n\n#define KM_TMASK 3\n#define KM_GSHIFT 4\n#define KM_GMASK 7\n\ntypedef struct keymap KEYMAP;\n\nKEYMAP *topmap INIT(Null(KEYMAP*));\n\nvoid mac_init();\nKEYMAP *newkeymap();\nvoid pushstring();\n#endif\n\n/* terminal initialization */\n\nvoid\nterm_init()\n{\n    savetty();\t\t\t\t/* remember current tty state */\n\n#ifdef TERMIO\n    ospeed = _tty.c_cflag & CBAUD;\t/* for tputs() */\n    ERASECH = _tty.c_cc[VERASE];\t/* for finish_command() */\n    KILLCH = _tty.c_cc[VKILL];\t\t/* for finish_command() */\n#else\n    ospeed = _tty.sg_ospeed;\t\t/* for tputs() */\n    ERASECH = _tty.sg_erase;\t\t/* for finish_command() */\n    KILLCH = _tty.sg_kill;\t\t/* for finish_command() */\n#endif\n}\n\n/* set terminal characteristics */\n\nvoid\nterm_set(tcbuf)\nchar *tcbuf;\t\t/* temp area for \"uncompiled\" termcap entry */\n{\n    char *tmpaddr;\t\t\t/* must not be register */\n    register char *tstr;\n    char *tgetstr();\n    char *s;\n    int retval;\n\n#ifdef PENDING\n#ifndef FIONREAD\n    /* do no delay reads on something that always gets closed on exit */\n\n    devtty = open(\"/dev/tty\",0);\n    if (devtty < 0) {\n\tprintf(cantopen,\"/dev/tty\");\n\tfinalize(1);\n    }\n    fcntl(devtty,F_SETFL,O_NDELAY);\n#endif\n#endif\n\n    /* get all that good termcap stuff */\n\n    retval = tgetent(tcbuf,getenv(\"TERM\"));\t/* get termcap entry */\n    if (retval < 1) {\n#ifdef VERBOSE\n\tprintf(\"No termcap %s found.\\n\", retval ? \"file\" : \"entry\");\n#else\n\tfputs(\"Termcap botch\\n\",stdout);\n#endif\n\tfinalize(1);\n    }\n    tmpaddr = tcarea;\t\t\t/* set up strange tgetstr pointer */\n    s = Tgetstr(\"pc\");\t\t\t/* get pad character */\n    PC = *s;\t\t\t\t/* get it where tputs wants it */\n    if (!tgetflag(\"bs\")) {\t\t/* is backspace not used? */\n\tBC = Tgetstr(\"bc\");\t\t/* find out what is */\n\tif (BC == nullstr) \t\t/* terminfo grok's 'bs' but not 'bc' */\n\t    BC = Tgetstr(\"le\");\n    } else\n\tBC = \"\\b\";\t\t\t/* make a backspace handy */\n    UP = Tgetstr(\"up\");\t\t\t/* move up a line */\n    ND = Tgetstr(\"nd\");\t\t\t/* non-destructive move cursor right */\n    DO = Tgetstr(\"do\");\t\t\t/* move cursor down */\n    if (!*DO)\n\tDO = Tgetstr(\"nl\");\n    CL = Tgetstr(\"cl\");\t\t\t/* get clear string */\n    CE = Tgetstr(\"ce\");\t\t\t/* clear to end of line string */\n    CM = Tgetstr(\"cm\");\t\t\t/* cursor motion - PWP */\n    HO = Tgetstr(\"ho\");\t\t\t/* home cursor if no CM - PWP */\n    CD = Tgetstr(\"cd\");\t\t\t/* clear to end of display - PWP */\n    SO = Tgetstr(\"so\");\t\t\t/* begin standout */\n    SE = Tgetstr(\"se\");\t\t\t/* end standout */\n    if ((SG = tgetnum(\"sg\"))<0)\n\tSG = 0;\t\t\t\t/* blanks left by SG, SE */\n    US = Tgetstr(\"us\");\t\t\t/* start underline */\n    UE = Tgetstr(\"ue\");\t\t\t/* end underline */\n    if ((UG = tgetnum(\"ug\"))<0)\n\tUG = 0;\t\t\t\t/* blanks left by US, UE */\n    if (*US)\n\tUC = nullstr;\t\t\t/* UC must not be NULL */\n    else\n\tUC = Tgetstr(\"uc\");\t\t/* underline a character */\n    if (!*US && !*UC) {\t\t\t/* no underline mode? */\n\tUS = SO;\t\t\t/* substitute standout mode */\n\tUE = SE;\n\tUG = SG;\n    }\n    LINES = tgetnum(\"li\");\t\t/* lines per page */\n    COLS = tgetnum(\"co\");\t\t/* columns on page */\n    AM = tgetflag(\"am\");\t\t/* terminal wraps automatically? */\n    XN = tgetflag(\"xn\");\t\t/* then eats next newline? */\n    VB = Tgetstr(\"vb\");\n    if (!*VB)\n\tVB = \"\\007\";\n    CR = Tgetstr(\"cr\");\n    if (!*CR) {\n\tif (tgetflag(\"nc\") && *UP) {\n\t    CR = safemalloc((MEM_SIZE)strlen(UP)+2);\n\t    Sprintf(CR,\"%s\\r\",UP);\n\t}\n\telse\n\t    CR = \"\\r\";\n    }\n    if (LINES <= 0)\n\tLINES = 24;\n    if (COLS <= 0)\n\tCOLS = 80;\n\n    BCsize = comp_tc(bsptr,BC,1);\n    BC = bsptr;\n\n    if (!*ND)\t\t\t\t/* not defined? */\n\tNDsize = 1000;\t\t\t/* force cursor addressing */\n    else {\n\tNDsize = comp_tc(cmbuffer,ND,1);\n\tmyND = malloc((unsigned)NDsize);\n\tmovc3(NDsize,cmbuffer,myND);\n\tif (debugging) {\n\t    int scr;\n\n\t    printf(\"ND\");\n\t    for (scr=0; scr<NDsize; scr++)\n\t\tprintf(\" %d\",myND[scr]);\n\t    printf(\"\\n\");\n\t}\n    }\n\n    if (!*UP)\t\t\t\t/* not defined? */\n\tUPsize = 1000;\t\t\t/* force cursor addressing */\n    else {\n\tUPsize = comp_tc(cmbuffer,UP,1);\n\tmyUP = malloc((unsigned)UPsize);\n\tmovc3(UPsize,cmbuffer,myUP);\n\tif (debugging) {\n\t    int scr;\n\n\t    printf(\"UP\");\n\t    for (scr=0; scr<UPsize; scr++)\n\t\tprintf(\" %d\",myUP[scr]);\n\t    printf(\"\\n\");\n\t}\n    }\n\n    if (!*DO) {\t\t\t\t/* not defined? */\n\tmyDO = DO = \"\\n\";\t\t/* assume a newline */\n\tDOsize = 1;\n    }\n    else {\n\tDOsize = comp_tc(cmbuffer,DO,1);\n\tmyDO = malloc((unsigned)DOsize);\n\tmovc3(DOsize,cmbuffer,myDO);\n\tif (debugging) {\n\t    int scr;\n\n\t    printf(\"DO\");\n\t    for (scr=0; scr<DOsize; scr++)\n\t\tprintf(\" %d\",myDO[scr]);\n\t    printf(\"\\n\");\n\t}\n    }\n    if (debugging)\n\tif (fgets(cmbuffer,(sizeof cmbuffer),stdin) == 0)\n\t    /*ignore*/;\n\n    CMsize = comp_tc(cmbuffer,tgoto(CM,20,20),0);\n    if (PC != '\\0') {\n\tchar *p;\n\n\tfor (p=filler+(sizeof filler)-1;!*p;--p)\n\t    *p = PC;\n    }\n    charsperhalfsec = ospeed >= B9600 ? 480 :\n\t\t      ospeed == B4800 ? 240 :\n\t\t      ospeed == B2400 ? 120 :\n\t\t      ospeed == B1200 ? 60 :\n\t\t      ospeed == B600 ? 30 :\n\t      /* speed is 300 (?) */   15;\n\n    gfillen = ospeed >= B9600 ? (sizeof filler) :\n\t      ospeed == B4800 ? 13 :\n\t      ospeed == B2400 ? 7 :\n\t      ospeed == B1200 ? 4 :\n\t\t\t\t1+BCsize;\n    if (ospeed < B2400)\n\tlowspeed = TRUE;\n\n    strcpy(term,ttyname(2));\n\n    if (!*CM || !BCsize)\n\tno_can_do(\"dumb\");\n    if (!scorespec && (LINES < 24 || COLS < 80))\n\tno_can_do(\"puny\");\n\n    crmode();\n    raw();\n    noecho();\t\t\t\t/* turn off echo */\n    nonl();\n\n#ifdef PUSHBACK\n    mac_init(tcbuf);\n#endif\n}\n\n#ifdef PUSHBACK\nvoid\nmac_init(tcbuf)\nchar *tcbuf;\n{\n    char tmpbuf[1024];\n\n    tmpfp = fopen(filexp(getval(\"WARPMACRO\",WARPMACRO)),\"r\");\n    if (tmpfp != Nullfp) {\n\twhile (fgets(tcbuf,1024,tmpfp) != Nullch) {\n\t    mac_line(tcbuf,tmpbuf,(sizeof tmpbuf));\n\t}\n\tFclose(tmpfp);\n    }\n}\n\nvoid\nmac_line(line,tmpbuf,tbsize)\nchar *line;\nchar *tmpbuf;\nint tbsize;\n{\n    register char *s;\n    register char *m;\n    register KEYMAP *curmap;\n    register int ch;\n    register int garbage = 0;\n    static char override[] = \"\\r\\nkeymap overrides string\\r\\n\";\n\n    if (topmap == Null(KEYMAP*))\n\ttopmap = newkeymap();\n    if (*line == '#' || *line == '\\n')\n\treturn;\n    if (line[ch = strlen(line)-1] == '\\n')\n\tline[ch] = '\\0';\n    m = dointerp(tmpbuf,tbsize,line,\" \\t\");\n    if (!*m)\n\treturn;\n    while (*m == ' ' || *m == '\\t') m++;\n    for (s=tmpbuf,curmap=topmap; *s; s++) {\n\tch = *s & 0177;\n\tif (s[1] == '+' && isdigit(s[2])) {\n\t    s += 2;\n\t    garbage = (*s & KM_GMASK) << KM_GSHIFT;\n\t}\n\telse\n\t    garbage = 0;\n\tif (s[1]) {\n\t    if ((curmap->km_type[ch] & KM_TMASK) == KM_STRING) {\n\t\tputs(override);\n\t\tfree(curmap->km_ptr[ch].km_str);\n\t\tcurmap->km_ptr[ch].km_str = Nullch;\n\t    }\n\t    curmap->km_type[ch] = KM_KEYMAP + garbage;\n\t    if (curmap->km_ptr[ch].km_km == Null(KEYMAP*))\n\t\tcurmap->km_ptr[ch].km_km = newkeymap();\n\t    curmap = curmap->km_ptr[ch].km_km;\n\t}\n\telse {\n\t    if ((curmap->km_type[ch] & KM_TMASK) == KM_KEYMAP)\n\t\tputs(override);\n\t    else {\n\t\tcurmap->km_type[ch] = KM_STRING + garbage;\n\t\tcurmap->km_ptr[ch].km_str = savestr(m);\n\t    }\n\t}\n    }\n}\n\nKEYMAP*\nnewkeymap()\n{\n    register int i;\n    register KEYMAP *map;\n\n    map = (KEYMAP*)safemalloc(sizeof(KEYMAP));\n    for (i=127; i>=0; --i) {\n\tmap->km_ptr[i].km_km = Null(KEYMAP*);\n\tmap->km_type[i] = KM_NOTHIN;\n    }\n    return map;\n}\n\n#endif\n\n/* print out a file, stopping at form feeds */\n\nvoid\npage(filename,num)\nchar *filename;\nbool num;\n{\n    int linenum = 1;\n\n    tmpfp = fopen(filename,\"r\");\n    if (tmpfp != NULL) {\n\twhile (fgets(spbuf,(sizeof spbuf),tmpfp) != NULL) {\n\t    if (*spbuf == '\\f') {\n\t\tprintf(\"[Type anything to continue] \");\n\t\tFflush(stdout);\n\t\tgetcmd(spbuf);\n\t\tprintf(\"\\r\\n\");\n\t\tif (*spbuf == INTRCH)\n\t\t    finalize(0);\n\t\tif (*spbuf == 'q' || *spbuf == 'Q')\n\t\t    break;\n\t    }\n\t    else {\n\t\tif (num)\n\t\t    printf(\"%3d   %s\\r\",linenum++,spbuf);\n\t\telse\n\t\t    printf(\"%s\\r\",spbuf);\n\t    }\n\t}\n\tFclose(tmpfp);\n    }\n}\n\nvoid\nmove(y, x, chadd)\nint y, x;\nint chadd;\n{\n    register int ydist;\n    register int xdist;\n    register int i;\n    register char *s;\n\n    ydist = y - real_y;\n    xdist = x - real_x;\n    i = ydist * (ydist < 0 ? -UPsize : DOsize) +\n        xdist * (xdist < 0 ? -BCsize : NDsize);\n    beg_qwrite();\n    if (i <= CMsize) {\n\tif (ydist < 0)\n\t    for (; ydist; ydist++)\n\t\tfor (i=UPsize,s=myUP; i; i--)\n\t\t    qaddch(*s++);\n\telse\n\t    for (; ydist; ydist--)\n\t\tfor (i=DOsize,s=myDO; i; i--)\n\t\t    qaddch(*s++);\n\tif (xdist < 0)\n\t    for (; xdist; xdist++)\n\t\tfor (i=BCsize,s=BC; i; i--)\n\t\t    qaddch(*s++);\n\telse\n\t    for (; xdist; xdist--)\n\t\tfor (i=NDsize,s=myND; i; i--)\n\t\t    qaddch(*s++);\n    }\n    else {\n\ttputs(tgoto(CM,x,y),0,cmstore);\n    }\n    real_y = y;\n    real_x = x;\n    if (chadd) {\n\tqaddch(chadd);\n    }\n    if (maxcmstring != cmbuffer)\n\tend_qwrite();\n}\n\nvoid\ndo_tc(s,l)\nchar *s;\nint l;\n{\n    beg_qwrite();\n    tputs(s,l,cmstore);\n    end_qwrite();\n}\n\nint\ncomp_tc(dest,s,l)\nchar *dest;\nchar *s;\nint l;\n{\n    maxcmstring = dest;\n    tputs(s,l,cmstore);\n    return(maxcmstring-dest);\n}\n\nvoid\nhelper()\n{\n    clear();\n    mvaddstr(0,4,\"h or 4          left\");\n    mvaddstr(1,4,\"j or 2          down                Use with SHIFT to fire torpedoes.\");\n    mvaddstr(2,4,\"k or 8          up                  Use with CTRL or FUNCT to fire\");\n    mvaddstr(3,4,\"l or 6          right                   phasers or turbolasers.\");\n    mvaddstr(4,4,\"b or 1          down and left       Use preceded by 'a' or 'r' for\");\n    mvaddstr(5,4,\"n or 3          down and right          attractors or repulsors.\");\n    mvaddstr(6,4,\"y or 7          up and left         Use normally for E or B motion.\");\n    mvaddstr(7,4,\"u or 9          up and right\");\n    mvaddstr(8,4,\"\");\n    mvaddstr(9,4,\"del or %        fire photon torpedoes in every (reasonable) direction.\");\n    mvaddstr(10,4,\"s               stop all torpedoes.\");\n    mvaddstr(11,4,\"S or 0          stop the Enterprise when in warp mode.\");\n    mvaddstr(12,4,\"d/D             destruct all torpedoes/current vessel.\");\n    mvaddstr(13,4,\"i/w             switch to Enterprise & put into impulse/warp mode.\");\n    mvaddstr(14,4,\"c/v             switch to Enterprise & make cloaked/visible.\");\n    mvaddstr(15,4,\"p               switch to Base.\");\n    mvaddstr(16,4,\"o               toggle to other vessel (from E to B, or vice versa.)\");\n    mvaddstr(17,4,\"z               zap (suppress) blasts near Enterprise next cycle\");\n    mvaddstr(18,4,\"\");\n    mvaddstr(19,4,\"^R      refresh the screen.              ^Z      suspend the game.\");\n    mvaddstr(20,4,\"q       exit this round (if you haven't typed q within 10 cycles).\");\n    mvaddstr(21,4,\"Q       exit this game.\");\n    mvaddstr(22,4,\"\");\n    mvaddstr(23,4,\"                   [Hit space to continue]\");\n    Fflush(stdout);\n    do {\n\tgetcmd(spbuf);\n    } while (*spbuf != ' ');\n    rewrite();\n\n}\n\nvoid\nrewrite()\n{\n    register int x;\n    register int y;\n    register OBJECT *obj;\n\n    clear();\n    for (y=0; y<YSIZE; y++) {\n\tfor (x=0; x<XSIZE; x++) {\n\t    if (numamoebas && amb[y][x] != ' ')\n\t\tmvaddc(y+1,x*2,amb[y][x]);\n\t    if (obj=occupant[y][x]) {\n\t\tif (obj->image != ' ')\n\t\t    mvaddc(y+1,x*2,obj->image);\n\t    }\n\t}\n    }\n    Sprintf(spbuf,\n    \"%-4s E: %4d %2d B: %5d %3d Enemies: %-3d Stars: %-3d Stardate%5d.%1d %9ld\",\n\t\"   \", 0, 0, 0, 0, 0, 0, timer/10+smarts*100, timer%10, 0L);\n    mvaddstr(0,0,spbuf);\n    oldeenergy = oldbenergy = oldcurscore =\n    oldstatus = oldetorp = oldbtorp = oldstrs = oldenemies = -1;\n\t\t\t\t\t/* force everything to fill in */\n    if (damage)\n\tolddamage = 0;\n    if (!ent)\n\tetorp = 0;\n    if (!base)\n\tbtorp = 0;\n    display_status();\n}\n\nchar\ncmstore(ch)\nregister char ch;\n{\n    *maxcmstring++ = ch;\n}\n\n/* discard any characters typed ahead */\n\nvoid\neat_typeahead()\n{\n#ifdef PUSHBACK\n    if (!typeahead && nextin==nextout)\t/* cancel only keyboard stuff */\n#else\n    if (!typeahead)\n#endif\n    {\n#ifdef PENDING\n\twhile (input_pending())\n\t    Read_tty(buf,sizeof(buf));\n#else /* this is probably v7, with no rdchk() */\n\tioctl(_tty_ch,TIOCSETP,&_tty);\n#endif\n    }\n}\n\nvoid\nsettle_down()\n{\n    dingaling();\n    Fflush(stdout);\n    sleep(1);\n#ifdef PUSHBACK\n    nextout = nextin;\t\t\t/* empty circlebuf */\n#endif\n    eat_typeahead();\n}\n\n#ifdef PUSHBACK\n/* read a character from the terminal, with multi-character pushback */\n\nint\nread_tty(addr,size)\nchar *addr;\nint size;\t/* ignored for now */\n{\n    if (nextout != nextin) {\n\t*addr = circlebuf[nextout++];\n\tnextout %= PUSHSIZE;\n\treturn 1;\n    }\n    else {\n\tsize = read(0,addr,1);\n\tif (size < 0)\n\t    sig_catcher(SIGHUP);\n\tif (metakey) {\n\t    if (*addr & 0200) {\n\t\tpushchar(*addr & 0177);\n\t\t*addr = '\\001';\n\t    }\n\t}\n\telse\n\t    *addr &= 0177;\n\treturn 1;\n    }\n}\n\n#ifdef PENDING\n#ifndef FIONREAD\nint\ncircfill()\n{\n    register int howmany;\n    register int i;\n\n    assert (nextin == nextout);\n    howmany = read(devtty,circlebuf+nextin,metakey?1:PUSHSIZE-nextin);\n    if (howmany > 0) {\n\tif (metakey) {\n\t    if (circlebuf[nextin] & 0200) {\n\t\tcirclebuf[nextin] &= 0177;\n\t\tpushchar('\\001');\n\t    }\n\t}\n\telse\n\t    for (i = howmany+nextin-1; i >= nextin; i--)\n\t\tcirclebuf[i] &= 0177;\n\tnextin += howmany;\n\tnextin %= PUSHSIZE;\t/* may end up 1 if metakey */\n    }\n    return howmany;\n}\n#endif /* FIONREAD */\n#endif /* PENDING */\n\nvoid\npushchar(ch)\nchar ch;\n{\n    nextout--;\n    if (nextout < 0)\n\tnextout = PUSHSIZE - 1;\n    if (nextout == nextin) {\n\tfputs(\"\\r\\npushback buffer overflow\\r\\n\",stdout);\n\tsig_catcher(0);\n    }\n    circlebuf[nextout] = ch;\n}\n\n#else /* PUSHBACK */\n#ifndef read_tty\n/* read a character from the terminal, with hacks for O_NDELAY reads */\n\nint\nread_tty(addr,size)\nchar *addr;\nint size;\n{\n    if (is_input) {\n\t*addr = pending_ch;\n\tis_input = FALSE;\n\treturn 1;\n    }\n    else {\n\tsize = read(0,addr,size);\n\tif (size < 0)\n\t    sig_catcher(SIGHUP);\n\tif (metakey) {\n\t    if (*addr & 0200) {\n\t\tpending_ch = *addr & 0177;\n\t\tis_input = TRUE;\n\t\t*addr = '\\001';\n\t    }\n\t}\n\telse\n\t    *addr &= 0177;\n\treturn size;\n    }\n}\n#endif /* read_tty */\n#endif /* PUSHBACK */\n\nint\nread_nd(buff, siz)\nchar *buff;\nint siz;\n{\n    if (!input_pending())\n\treturn 0;\n\n    getcmd(buff);\n    return 1;\n}\n\n/* get a character into a buffer */\n\nvoid\ngetcmd(whatbuf)\nregister char *whatbuf;\n{\n#ifdef PUSHBACK\n    register KEYMAP *curmap;\n    register int i;\n    bool no_macros;\n    int times = 0;\t\t\t/* loop detector */\n    char scrchar;\n\ntryagain:\n    curmap = topmap;\n/*    no_macros = (whatbuf != buf && nextin == nextout);  */\n    no_macros = FALSE;\n#endif\n    for (;;) {\n\terrno = 0;\n\tif (read_tty(whatbuf,1) < 0 && !errno)\n\t    errno = EINTR;\n#ifdef read_tty\n\tif (metakey) {\n\t    if (*whatbuf & 0200) {\n\t\t*what_buf &= 037;\t/* punt and hope they don't notice */\n\t    }\n\t}\n\telse\n\t    *whatbuf &= 0177;\n#endif /* read_tty */\n\tif (errno && errno != EINTR) {\n\t    perror(readerr);\n\t    sig_catcher(0);\n\t}\n#ifdef PUSHBACK\n\tif (*whatbuf & 0200 || no_macros) {\n\t    *whatbuf &= 0177;\n\t    goto got_canonical;\n\t}\n\tif (curmap == Null(KEYMAP*))\n\t    goto got_canonical;\n\tfor (i = (curmap->km_type[*whatbuf] >> KM_GSHIFT) & KM_GMASK; i; --i){\n\t    Read_tty(&scrchar,1);\n\t}\n\tswitch (curmap->km_type[*whatbuf] & KM_TMASK) {\n\tcase KM_NOTHIN:\t\t\t/* no entry? */\n\t    if (curmap == topmap)\t/* unmapped canonical */\n\t\tgoto got_canonical;\n\t    settle_down();\n\t    goto tryagain;\n\tcase KM_KEYMAP:\t\t\t/* another keymap? */\n\t    curmap = curmap->km_ptr[*whatbuf].km_km;\n\t    assert(curmap != Null(KEYMAP*));\n\t    break;\n\tcase KM_STRING:\t\t\t/* a string? */\n\t    pushstring(curmap->km_ptr[*whatbuf].km_str);\n\t    if (++times > 20) {\t\t/* loop? */\n\t\tfputs(\"\\r\\nmacro loop?\\r\\n\",stdout);\n\t\tsettle_down();\n\t    }\n\t    no_macros = FALSE;\n\t    goto tryagain;\n\t}\n#else\n\t*whatbuf &= 0177;\n\tbreak;\n#endif\n    }\n\ngot_canonical:\n#ifndef TERMIO\n    if (*whatbuf == '\\r')\n\t*whatbuf = '\\n';\n#endif\n    if (whatbuf == buf)\n\twhatbuf[1] = FINISHCMD;\t\t/* tell finish_command to work */\n}\n\n#ifdef PUSHBACK\nvoid\npushstring(str)\nchar *str;\n{\n    register int i;\n    char tmpbuf[PUSHSIZE];\n    register char *s = tmpbuf;\n\n    assert(str != Nullch);\n    interp(s,PUSHSIZE,str);\n    for (i = strlen(s)-1; i >= 0; --i) {\n\ts[i] ^= 0200;\n\tpushchar(s[i]);\n    }\n}\n#endif\n"
  },
  {
    "path": "games/warp/term.h",
    "content": "/* $Header: term.h,v 7.0.1.2 86/12/12 17:05:15 lwall Exp $ */\n\n/* $Log:\tterm.h,v $\n * Revision 7.0.1.2  86/12/12  17:05:15  lwall\n * Baseline for net release.\n *\n * Revision 7.0.1.1  86/10/16  10:53:33  lwall\n * Added Damage.  Fixed random bugs.\n *\n * Revision 7.0  86/10/08  15:14:07  lwall\n * Split into separate files.  Added amoebas and pirates.\n *\n */\n\n/* warp will still work without the following, but may get ahead at low speed */\n#ifdef TIOCOUTQ\t\t/* chars left in output queue */\n#define output_pending() (ioctl(1, TIOCOUTQ, &iocount),iocount)\n#endif\n\n/* If some of the following look something like curses calls, it is because\n * warp used to use curses but doesn't now.  Warp was neither as efficient nor\n * as portable with curses, and since the program had to cheat on curses all\n * over the place anyway, we ripped it out.\n */\n#define setimage(of,to) (mvaddch(of->posy+1,of->posx*2,of->image=(to)))\n\n#define mvaddch(y,x,ch) move((y),(x),(ch))\n/* #define addch(ch) (tmpchr=(ch), write(1,&tmpchr,1), real_x++) */\n#define mvaddc(y,x,ch) move((y),(x),(ch))\n#define addc(ch) (write(1,&(ch),1), real_x++)\n#define addspace() (write(1,\" \",1), real_x++)\n#define mvaddstr(y,x,s) (move((y),(x),0), tmpstr = (s), \\\n     tmplen = strlen(tmpstr), write(1, tmpstr, tmplen) >= 0, real_x += tmplen)\n\nEXT int tmplen;\nEXT char *tmpstr;\n/* EXT char tmpchr; */\n\n/* The following macros are like the pseudo-curses macros above, but do\n * certain amount of controlled output buffering.\n *\n * NOTE: a beg_qwrite()..end_qwrite() sequence must NOT contain a cursor\n * movement (move), because the move() routine uses beg_qwrite()..end_qwrite()\n * itself.\n */\n\n#define beg_qwrite() (maxcmstring = cmbuffer)\n#define qwrite() (movc3(gfillen,filler,maxcmstring), maxcmstring += gfillen)\n#define qaddc(ch) (*maxcmstring++ = (ch), real_x++)\n#define qaddch(ch) (*maxcmstring++ = (ch), real_x++)\n#define qaddspace() (*maxcmstring++ = ' ', real_x++)\n#define end_qwrite() (write(1,cmbuffer,maxcmstring-cmbuffer) > 0)\n\n/* setting a ??size to infinity forces cursor addressing in that direction */\n\nEXT int CMsize;\nEXT int BCsize INIT(1);\nEXT int DOsize INIT(1000);\nEXT int UPsize INIT(1000);\nEXT int NDsize INIT(1000);\n\nEXT int charsperhalfsec;\n\nEXT int real_y INIT(-100);\nEXT int real_x INIT(-100);\n\n#ifdef DOINIT\nchar filler[] = {0,'\\b',0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};\n#else\nEXT char filler[];\n#endif\n\nEXT char *bsptr INIT(filler+1);\n\nEXT char term[12];\n\nEXT char gfillen INIT(25);\n\nEXT char *maxcmstring;\nEXT char cmbuffer[512];\n\n#define BREAKCH '\\0'\n\nEXT char INTRCH INIT('\\03');\n\n#ifdef PUSHBACK\n    EXT char circlebuf[PUSHSIZE];\n    EXT int nextin INIT(0);\n    EXT int nextout INIT(0);\n#   ifdef PENDING\n#\tifdef FIONREAD\n\t    EXT long iocount INIT(0);\n#           define input_pending() (nextin!=nextout || (ioctl(0, FIONREAD, &iocount),(int)iocount))\n#\telse /* FIONREAD */\n\t    int circfill();\n#           ifndef O_NDELAY\t/* assert O_NDELAY */\n#               error PENDING is not defined correctly in warp.h\n#           endif\n            EXT int devtty INIT(0);\n#           define input_pending() (nextin!=nextout || circfill())\n#\tendif /* FIONREAD */\n#   else /* PENDING */\n#\terror warp wont work without PENDING\n#\tdefine input_pending() (nextin!=nextout)\n#   endif /* PENDING */\n#else /* PUSHBACK */\n#   ifdef PENDING\n#\tifdef FIONREAD /* must have FIONREAD or O_NDELAY for input_pending() */\n#\t    define read_tty(addr,size) read(0,addr,size)\n#           define input_pending() (ioctl(0, FIONREAD, &iocount), (int)iocount)\n\t    EXT long iocount INIT(0);\n#\telse /* FIONREAD */\n#\t    ifdef RDCHK\t\t/* actually, they can have rdchk() too */\n#\t    define read_tty(addr,size) read(0,addr,size)\n#\t\tdefine input_pending() rdchk(0)\n#\t    else /* RDCHK */\n#\t\tifndef O_NDELAY\t/* assert O_NDELAY */\n#\t\t    error PENDING is not defined correctly in warp.h\n#\t\tendif\n\t\tEXT int devtty INIT(0);\n\t\tEXT bool is_input INIT(FALSE);\n\t\tEXT char pending_ch INIT(0);\n#\t\tdefine input_pending() (is_input || (is_input=read(devtty,&pending_ch,1)))\n#\t    endif /* RDCHK */\n#\tendif /* FIONREAD */\n#   else /* PENDING */\n#\terror warp wont work without PENDING\n#\tdefine read_tty(addr,size) read(0,addr,size)\n#\tdefine input_pending() (FALSE)\n#   endif /* PENDING */\n#endif /* PUSHBACK */\n\n/* stuff wanted by terminal mode diddling routines */\n\n#ifdef TERMIO\nEXT struct termio _tty, _oldtty;\n#else\nEXT struct sgttyb _tty;\nEXT int _res_flg INIT(0);\n#endif\n\nEXT int _tty_ch INIT(2);\nEXT bool bizarre INIT(FALSE);\t\t\t/* do we need to restore terminal? */\n\n/* terminal mode diddling routines */\n\n#ifdef TERMIO\n\n#define raw() ((bizarre=1),_tty.c_lflag &=~ISIG,_tty.c_cc[VMIN] = 1,ioctl(_tty_ch,TCSETAF,&_tty))\n#define noraw() ((bizarre=1),_tty.c_lflag |= ISIG,_tty.c_cc[VEOF] = CEOF,ioctl(_tty_ch,TCSETAF,&_tty))\n#define crmode() ((bizarre=1),_tty.c_lflag &=~ICANON,_tty.c_cc[VMIN] = 1,ioctl(_tty_ch,TCSETAF,&_tty))\n#define nocrmode() ((bizarre=1),_tty.c_lflag |= ICANON,_tty.c_cc[VEOF] = CEOF,ioctl(_tty_ch,TCSETAF,&_tty))\n#define echo()\t ((bizarre=1),_tty.c_lflag |= ECHO, ioctl(_tty_ch, TCSETAW, &_tty))\n#define noecho() ((bizarre=1),_tty.c_lflag &=~ECHO, ioctl(_tty_ch, TCSETAW, &_tty))\n#define nl()\t ((bizarre=1),_tty.c_iflag |= ICRNL,_tty.c_oflag |= ONLCR,ioctl(_tty_ch, TCSETAW, &_tty))\n#define nonl()\t ((bizarre=1),_tty.c_iflag &=~ICRNL,_tty.c_oflag &=~ONLCR,ioctl(_tty_ch, TCSETAW, &_tty))\n#define\tsavetty() (ioctl(_tty_ch, TCGETA, &_oldtty),ioctl(_tty_ch, TCGETA, &_tty))\n#define\tresetty() ((bizarre=0),ioctl(_tty_ch, TCSETAF, &_oldtty))\n#define unflush_output()\n\n#else\n\n#define raw()\t ((bizarre=1),_tty.sg_flags|=RAW, stty(_tty_ch,&_tty))\n#define noraw()\t ((bizarre=1),_tty.sg_flags&=~RAW,stty(_tty_ch,&_tty))\n#define crmode() ((bizarre=1),_tty.sg_flags |= CBREAK, stty(_tty_ch,&_tty))\n#define nocrmode() ((bizarre=1),_tty.sg_flags &= ~CBREAK,stty(_tty_ch,&_tty))\n#define echo()\t ((bizarre=1),_tty.sg_flags |= ECHO, stty(_tty_ch, &_tty))\n#define noecho() ((bizarre=1),_tty.sg_flags &= ~ECHO, stty(_tty_ch, &_tty))\n#define nl()\t ((bizarre=1),_tty.sg_flags |= CRMOD,stty(_tty_ch, &_tty))\n#define nonl()\t ((bizarre=1),_tty.sg_flags &= ~CRMOD, stty(_tty_ch, &_tty))\n#define\tsavetty() (gtty(_tty_ch, &_tty), _res_flg = _tty.sg_flags)\n#define\tresetty() ((bizarre=0),_tty.sg_flags = _res_flg, stty(_tty_ch, &_tty))\n#endif /* TERMIO */\n\n#ifdef TIOCSTI\n#define forceme(c) ioctl(_tty_ch,TIOCSTI,c) /* pass character in \" \" */\n#else\n#define forceme(c)\n#endif\n\n/* termcap stuff */\n\n/*\n * NOTE: if you don't have termlib you'll have to define these strings,\n *    the tputs routine, and the tgoto routine.\n * The tgoto routine simply produces a cursor addressing string for a given\n * x and y.  The 1st argument is a generic string to be interpreted.\n * If you are hardwiring it you might just ignore the 1st argument.\n * The tputs routine interprets any leading number as a padding factor, possibly\n * scaled by the number of lines (2nd argument), puts out the string (1st arg)\n * and the padding using the routine specified as the 3rd argument.\n */\nEXT char *BC INIT(Nullch);\t\t/* backspace character */\nEXT char *UP INIT(Nullch);\t\t/* move cursor up one line */\nEXT char *myUP;\nEXT char *ND INIT(Nullch);\t\t/* non-destructive cursor right */\nEXT char *myND;\nEXT char *DO INIT(Nullch);\t\t/* move cursor down one line */\nEXT char *myDO;\nEXT char *CR INIT(Nullch);\t\t/* get to left margin, somehow */\nEXT char *VB INIT(Nullch);\t\t/* visible bell */\nEXT char *CL INIT(Nullch);\t\t/* home and clear screen */\nEXT char *CE INIT(Nullch);\t\t/* clear to end of line */\nEXT char *CM INIT(Nullch);\t\t/* cursor motion -- PWP */\nEXT char *HO INIT(Nullch);\t\t/* home cursor -- PWP */\nEXT char *CD INIT(Nullch);\t\t/* clear to end of display -- PWP */\nEXT char *SO INIT(Nullch);\t\t/* begin standout mode */\nEXT char *SE INIT(Nullch);\t\t/* end standout mode */\nEXT int SG INIT(0);\t\t/* blanks left by SO and SE */\nEXT char *US INIT(Nullch);\t\t/* start underline mode */\nEXT char *UE INIT(Nullch);\t\t/* end underline mode */\nEXT char *UC INIT(Nullch);\t\t/* underline a character, if that's how it's done */\nEXT int UG INIT(0);\t\t/* blanks left by US and UE */\nEXT bool AM INIT(FALSE);\t\t/* does terminal have automatic margins? */\nEXT bool XN INIT(FALSE);\t\t/* does it eat 1st newline after automatic wrap? */\nEXT char PC INIT(0);\t\t/* pad character for use by tputs() */\nEXT short ospeed INIT(0);\t/* terminal output speed, for use by tputs() */\nEXT int LINES INIT(0), COLS INIT(0);\t/* size of screen */\n\t\t\t\t\t/* (number of nulls) */\nEXT char ERASECH;\t\t/* rubout character */\nEXT char KILLCH;\t\t/* line delete character */\n\n/* define a few handy macros */\n\n#define clear() (do_tc(CL,LINES),real_y=real_x=0)\n#define erase_eol() do_tc(CE,1)\n#define backspace() (do_tc(BC,0),real_x--)\n#define clear_rest() do_tc(CD,LINES)\n#define underline() do_tc(US,1)\n#define un_underline() do_tc(UE,1)\n#define underchar() do_tc(UC,0)\n#define standout() do_tc(SO,1)\n#define un_standout() do_tc(SE,1)\n#define up_line() do_tc(UP,1)\n#define carriage_return() do_tc(CR,1)\n#define dingaling() do_tc(VB,1)\n\nvoid\tterm_init();\nvoid\tterm_set();\n#ifdef PUSHBACK\nvoid\tpushchar();\nvoid\tmac_init();\nvoid\tmac_line();\n#endif\nvoid\teat_typeahead();\nvoid\tsettle_down();\n#ifndef read_tty\n    int\t\tread_tty();\n#endif\nvoid\tgetcmd();\n\nint read_nd();\nvoid page();\nvoid move();\nvoid do_tc();\nint comp_tc();\nvoid helper();\nvoid rewrite();\nchar cmstore();\n"
  },
  {
    "path": "games/warp/them.c",
    "content": "/* $Header: them.c,v 7.0.1.5 86/12/12 17:05:41 lwall Exp $ */\n\n/* $Log:\tthem.c,v $\n * Revision 7.0.1.5  86/12/12  17:05:41  lwall\n * Baseline for net release.\n *\n * Revision 7.0.1.4  86/10/20  12:32:38  lwall\n * Wasn't clearing FRIENDLY flag on pirate creation.\n *\n * Revision 7.0.1.3  86/10/20  12:15:33  lwall\n * Was trying to create pirates from cloaked pirates.\n *\n * Revision 7.0.1.2  86/10/17  10:03:44  lwall\n * Fixed Romulan writing spaces while cloaked.\n *\n * Revision 7.0.1.1  86/10/16  10:53:39  lwall\n * Added Damage.  Fixed random bugs.\n *\n * Revision 7.0  86/10/08  15:14:15  lwall\n * Split into separate files.  Added amoebas and pirates.\n *\n */\n\n#include \"EXTERN.h\"\n#include \"warp.h\"\n#include \"bang.h\"\n#include \"object.h\"\n#include \"move.h\"\n#include \"score.h\"\n#include \"term.h\"\n#include \"us.h\"\n#include \"util.h\"\n#include \"weapon.h\"\n#include \"INTERN.h\"\n#include \"them.h\"\n\nvoid\nthem_init()\n{\n    ;\n}\n\nvoid\ntheir_smarts()\n{\n    register OBJECT *curkl;\n    register OBJECT *obj;\n    register int prob;\n    register int count;\n    register int y;\n    register int x;\n\n    if (numcrushes && (obj=movers)->type == Crusher) {\n\tif (numamoebas) {\n\t    y = obj->posy;\n\t    x = (obj->posx+(obj->image=='<'?1:-1)+XSIZE00)%XSIZE;\n\t    if (amb[y][x] == '~') {\n\t\tobj->velx = 0;\t\t/* stop and munch amoeba */\n\t\tmodify_amoeba(y,x,1,' ',(int)rand_mod(5+ambsize/10)+1);\n\t\tif (occupant[y][x] == nuke)\t/* except go for nucleus */\n\t\t    obj->velx = (obj->image=='<' ? 1 : -1);\n\t    }\n\t    else if (!obj->velx) {\n\t\tif (!rand_mod(4))\n\t\t    obj->image = rand_mod(2) ? '<' : '>';\n\t\tobj->velx = obj->image == '<' ? 1 : -1;\n\t    }\n\t}\n\tobj->vely += (rand_mod(222) - 111) / 100;\n\tif (!(rand_mod(100))) {\n\t    setimage(obj, (obj->velx *= -1) < 0 ? '>' : '<');\n\t}\n    }\n    if (numamoebas) {\n\tif (!rand_mod(3))\n\t    nuke->velx = nuke->vely = 0;\n\tif (nuke->strategy && ambsize < 90 && !rand_mod(200-smarts))\n\t    modify_amoeba(0,0,0,'~',(int)rand_mod(10));\n\tif (ambsize > 200 || (ambsize > 100 && !rand_mod(15)))\n\t    modify_amoeba(yamblast,xamblast,2,' ',(ambsize-100)/5);\n    }\n    for (curkl = enemies; curkl->type == Enemy; curkl = curkl->next) {\n\tif ((curkl->flags & (CLOAKS|FRIENDLY)) == CLOAKS &&\n\t    (curkl->image != ' ') &&\n\t    (curkl->energy > 300 || massacre) ) {\n\t    setimage(curkl, ' ');\n\t}\n\tif (madgorns)\n\t    prob = 3;\n\telse if (curkl->vely || curkl->velx)\n\t    prob = massacre?10:20;\n\telse if ((curkl->flags & (PIRATE|FRIENDLY)) == PIRATE) {\n\t\t\t\t/* pirates want to sit sometimes */\n\t    if (curkl->strategy) {\n\t\tif ((obj = lookimg(curkl->posy, curkl->posx, '@')) ||\n\t\t    (obj = lookimg(curkl->posy, curkl->posx, 'B')) ) {\n\t\t    make_plink(obj->posy, obj->posx);\n\t\t    if (!--curkl->strategy) {\t/* clock ran down */\n\t\t\tif (obj->image == '@') {\n\t\t\t    obj->image = '*';\n\t\t\t    numinhab--;\n\t\t\t    if (obj->flags & STATIC)\n\t\t\t\tmvaddch(obj->posy+1,obj->posx*2,obj->image);\n\t\t\t    if (curkl->energy < 20000)\n\t\t\t\tcurkl->energy += 5000;\n\t\t\t}\n\t\t\tprob = 2;\t/* our work here is done */\n\t\t    }\n\t\t    else if (obj->image == 'B') {\n\t\t\tbtorp -= rand_mod(50);\n\t\t\tif (btorp < 0)\n\t\t\t    btorp = 0;\n\t\t\tobj->energy -= rand_mod(500);\n\t\t\tif (obj->energy < 0)\n\t\t\t    obj->energy = 0;\n\t\t\tprob = 10000;\t\t/* stay here */\n\t\t    }\n\t\t    else\n\t\t\tprob = 10000;\n\t\t}\n\t\telse {\t\t/* it went away--go elsewhere */\n\t\t    prob = 4;\n\t\t    curkl->strategy = 0;\n\t\t}\n\t    }\n\t    else if (lookimg(curkl->posy, curkl->posx, '@') ||\n\t\t     lookimg(curkl->posy, curkl->posx, 'B')) {\n\t\tcurkl->strategy = rand_mod(15)+5;\n\t\tprob = 10000;\n\t    }\n\t    else\n\t\tprob = 4;\n\t}\n\telse if (curkl->image == 'M') {\t/* Mudd wants to sit sometimes */\n\t    if ((obj = lookimg(curkl->posy, curkl->posx, 'E')) ||\n\t\t(obj = lookimg(curkl->posy, curkl->posx, 'B')) ) {\n\t\tif (obj->image == 'B') {\n\t\t    btorp -= rand_mod(40);\n\t\t    if (btorp < 0)\n\t\t\tbtorp = 0;\n\t\t    obj->energy -= rand_mod(100);\n\t\t    if (obj->energy < 0)\n\t\t\tobj->energy = 0;\n\t\t}\n\t\telse if (!obj->vely && !obj->velx) {\n\t\t    etorp -= rand_mod(10);\n\t\t    if (etorp < 0)\n\t\t\tetorp = 0;\n\t\t    obj->energy -= rand_mod(20);\n\t\t    if (obj->energy < 0)\n\t\t\tobj->energy = 0;\n\t\t}\n\t\tprob = 10000;\t\t/* stay here */\n\t    }\n\t    else\t\t/* it went away--go elsewhere */\n\t\tprob = 4;\n\t}\n\telse if (curkl->flags & FRIENDLY) {\n\t    if (curkl->energy < 10000 &&\n\t      lookimg(curkl->posy, curkl->posx, '@') ) {\n\t\tcurkl->energy += 100;\n\t\tprob = 20;\t/* do some loading */\n\t    }\n\t    else\n\t\tprob = 4;\n\t}\n\telse if (curkl->image == '&') {\n\t    if (curkl->flags & COUNTDOWN) {\n\t\tif (curkl->strategy)\n\t\t    curkl->strategy--;\n\t\telse\n\t\t    curkl->flags &= ~COUNTDOWN;\n\t\tprob = 100;\t/* someone's feeding us, so sit still */\n\t    }\n\t    else\n\t\tprob = 4;\n\t}\n\telse\n\t    prob = 4;\t\t\t/* don't sit still too long */\n\tcount = 11;\n\tfor (;;) {\n\t    if (--count <= 0)\t\t/* no opening, just ram something */\n\t\tbreak;\n\n\t    if (!(rand_mod(prob)))\t/* turn randomly occasionally */\n\t\tgoto accell;\n\n\t    y=(curkl->posy+curkl->vely+YSIZE00)%YSIZE;\t/* find prospective */\n\t    x=(curkl->posx+curkl->velx+XSIZE00)%XSIZE;\t/*   new position */\n\n\t    if (numamoebas) {\n\t\tif (curkl == nuke) {\n\t\t    if (amb[y][x] != '~')\n\t\t\tgoto accell;\t/* never move nucleus from protoplasm */\n\t\t}\n\t\telse {\n\t\t    if (amb[y][x] == '~' && rand_mod(2)) {\n\t\t\tyamblast = y;\n\t\t\txamblast = x;\n\t\t\tgoto accell;\n\t\t    }\n\t\t}\n\t    }\n\n\t    obj = occupant[y][x];\n\t    if (!obj) break;\t\t/* is anyone there? */\n\n\t    switch (obj->type) {\n\t    case Star:\n\t\tif (obj->image == '@' && (curkl->flags & PIRATE)) {\n\t\t    if (curkl->image != 'P' && curkl->image != ' ') {\n\t\t\tif (curkl->flags & FRIENDLY) {\n\t\t\t    curkl->flags &= ~FRIENDLY;\n\t\t\t    curkl->energy += 1000;\n\t\t\t    possiblescore += curkl->mass;\n\t\t\t    inumfriends--;\n\t\t\t    numfriends--;\n\t\t\t    inumenemies++;\n\t\t\t    numenemies++;\n\t\t\t}\n\t\t\tcurkl->image = 'P';\n\t\t    }\n\t\t    break;\t\t/* go ahead and ram the star */\n\t\t}\n\t\tgoto accell;\t\t/* try not to ram stars */\n\t    case Torp:\n\t\tif (!obj->vely && !obj->velx && (rand_mod(100) <= smarts) &&\n\t\t  (obj->image == 'o' || obj->image == 'O' || obj->image == 'X'))\n\t\t    goto accell;\t/* try not to ram \"friendly\" torps */\n\t\tbreak;\n\t    case Web:\n\t\tif (curkl->image != 'T')\n\t\t    goto accell;\t/* non-Tholians shouldn't ram web */\n\t\tif (count <= 5)\n\t\t    break;\t\t/* Tholians retrace web if desperate */\n\t\tif (obj->image ==\n\t\t    (curkl->vely?\n\t\t     (curkl->velx?\n\t\t      (curkl->velx==curkl->vely?\n\t\t       '\\\\'\n\t\t      :\n\t\t       '/'\n\t\t      )\n\t\t     :\n\t\t      '|'\n\t\t     )\n\t\t    :\n\t\t     '-'\n\t\t    )\n\t\t   ) goto accell;\t/* Tholians try not to retrace web */\n\t\tbreak;\t\t\t/* No problem with crossing web */\n\t    }\n\t    break;\t\t\t/* okay to move over object */\n\n\taccell:\n\t    /* determine maximum velocity */\n\t    if (massacre && curkl->image != 'T') {\n\t\tcurkl->vely = rand_mod(7) - 3;\n\t\tcurkl->velx = rand_mod(7) - 3;\n\t    }\n\t    else if (curkl->image == '&') {\n\t\tif (rand_mod(2)) {\n\t\t    curkl->vely = rand_mod(3) - 1;\n\t\t    curkl->velx = rand_mod(3) - 1;\n\t\t}\n\t\telse {\n\t\t    curkl->vely = curkl->strategy & 3;\n\t\t    if (curkl->vely & 2)\n\t\t\tcurkl->vely = -1;\n\t\t    curkl->velx = (curkl->strategy >> 2) & 3;\n\t\t    if (curkl->velx & 2)\n\t\t\tcurkl->velx = -1;\n\t\t}\n\t    }\n\t    else if (curkl->energy >= 2500 && curkl->image != 'T') {\n\t\tcurkl->vely = rand_mod(5) - 2;\n\t\tcurkl->velx = rand_mod(5) - 2;\n\t    }\n\t    else {\n\t\tcurkl->vely = rand_mod(3) - 1;\n\t\tcurkl->velx = rand_mod(3) - 1;\n\t    }\n\t}\n\tif (count != 10) {\n\t    if (curkl->image == ' ') {\n\t\tsetimage(curkl, curkl->flags & PIRATE ? 'P' : 'R');\n\t    }\n\t    if (!count) {\n\t\tcurkl->vely = 0;\n\t\tcurkl->velx = 0;\n\t    }\n\t}\n\tif (curkl->image == 'G' && (base||ent) &&\n\t    !rand_mod((103-smarts)*10) ) {\n\t    int xxx,yyy;\n\n\t    for (xxx = -1; xxx<=1; xxx++)\n\t\tfor (yyy = -1; yyy<=1; yyy++)\n\t\t    if ((xxx||yyy) && rand_mod(2))\n\t\t\tfire_torp(curkl,yyy,xxx);\n\t}\n\telse if (curkl->image == 'T' && (curkl->velx || curkl->vely)) {\n\t    Make_object(Web,\n            curkl->vely?\n\t     (curkl->velx?\n\t      (curkl->velx==curkl->vely?\n\t       '\\\\'\n\t      :\n\t       '/'\n\t      )\n\t     :\n\t      '|'\n\t     )\n\t    :\n\t     '-',\n\t    curkl->posy,curkl->posx,0,0,32767L,32767L,&root);\n\t    if (obj && obj->type == Web) {\n\t\tunmake_object(obj);\n\t\toccupant[y][x] = Null(OBJECT*);\n\t    }\n\t}\n    }\n    /* klingon-style fighting */\n    if (numamoebas)\n\tattack(nuke);\n    attack(base);\n    if (ent && (!cloaked || ent->image=='E' || ent->image=='e'))\n\tattack(ent);\n}\n\nvoid\nmodify_amoeba(y,x,where,ch,quant)\nregister int y;\nregister int x;\nint where;\nregister int ch;\nregister int quant;\n{\n    register int dy;\n    register int dx;\n    register int count = 15;\n\n    if (!numamoebas)\n\treturn;\n    if (!where || (where==1 && rand_mod(2))) {\n\ty = nuke->posy;\n\tx = nuke->posx;\n    }\n    if (nuke->strategy && rand_mod(3)) {\n\tdy = nuke->strategy & 3;\n\tif (dy & 2)\n\t    dy = -1;\n\tdx = (nuke->strategy >> 2) & 3;\n\tif (dx & 2)\n\t    dx = -1;\n\tif (ch == ' ') {\t\t/* take from the tail */\n\t    dy = -dy;\n\t    dx = -dx;\n\t}\n\tif (!rand_mod(100))\n\t    nuke->strategy = rand_mod(256);\n    }\n    else {\n\tdy = rand_mod(3) - 1;\n\tdx = rand_mod(3) - 1;\n    }\n    if (!dy && !dx)\n\treturn;\n    do {\n\tif (--count < 0)\n\t    return;\n\ty = (y + dy + YSIZE00) % YSIZE;\n\tx = (x + dx + XSIZE00) % XSIZE;\n    } while (amb[y][x] != ' ');\n    if (ch == ' ') {\n\ty = (y - dy + YSIZE00) % YSIZE;\n\tx = (x - dx + XSIZE00) % XSIZE;\n    }\n    if (ambsize > 100 && quant > 2) {\n\tquant >>= (ambsize/100);\n    }\n    if ((nuke->energy += quant << 6) > 32767)\n\tnuke->energy = 32767;\n    count = quant << 3;\t\t/* endless loop catcher */\n    while (count-- > 0 && quant > 0) {\n\tif (amb[y][x] != ch) {\n\t    quant--;\n\t    amb[y][x] = ch;\n\t    if (ch == '~') {\n\t\tambsize++;\n\t\tyblasted[y] |= 2;\n\t\txblasted[x] |= 2;\n\t\tblasted = TRUE;\n\t    }\n\t    else\n\t\tambsize--;\n\t    if (!occupant[y][x])\n\t\tmvaddch(y+1,x*2,ch);\n\t}\n\ty = (y + rand_mod(3) + YSIZE99) % YSIZE;\n\tx = (x + rand_mod(3) + XSIZE99) % XSIZE;\n    }\n}\n"
  },
  {
    "path": "games/warp/them.h",
    "content": "/* $Header: them.h,v 7.0 86/10/08 15:14:19 lwall Exp $ */\n\n/* $Log:\tthem.h,v $\n * Revision 7.0  86/10/08  15:14:19  lwall\n * Split into separate files.  Added amoebas and pirates.\n * \n */\n\nvoid their_smarts();\nvoid modify_amoeba();\nvoid them_init();\n"
  },
  {
    "path": "games/warp/us.c",
    "content": "/* $Header: us.c,v 7.0.1.3 87/01/13 17:13:21 lwall Exp $ */\n\n/* $Log:\tus.c,v $\n * Revision 7.0.1.3  87/01/13  17:13:21  lwall\n * Partially fixed ^S behavior.  It now just ignores ^S.\n *\n * Revision 7.0.1.2  86/12/12  17:06:09  lwall\n * Baseline for net release.\n *\n * Revision 7.0.1.1  86/10/16  10:53:50  lwall\n * Added Damage.  Fixed random bugs.\n *\n * Revision 7.0  86/10/08  15:14:21  lwall\n * Split into separate files.  Added amoebas and pirates.\n *\n */\n\n#include \"EXTERN.h\"\n#include \"warp.h\"\n#include \"bang.h\"\n#include \"object.h\"\n#include \"play.h\"\n#include \"sig.h\"\n#include \"term.h\"\n#include \"util.h\"\n#include \"weapon.h\"\n#include \"INTERN.h\"\n#include \"us.h\"\n\nvoid\nus_init()\n{\n    ;\n}\n\nvoid\ndo_direction(dy,dx)\nint dy, dx;\n{\n    register int decr;\n    register OBJECT *obj;\n\n    if (status < 2) {\n\tif (cloaking) {\n\t    char ch;\n\n\t    cloaked = FALSE;\n\t    ch = (ent->energy >= 500?'E':'e');\n\t    if (ch != ent->image) {\n\t\tsetimage(ent, ch);\n\t    }\n\t}\n\tdecr = 5+abs(evely)+abs(evelx)+tractor*tractor;\n\tif (ent->energy >= decr) {\n\t    ent->energy -= decr;\n\t    if (tractor) {\n\t\tif (!damage || !damflag[NOTRACTORS]) {\n\t\t    if (!rand_mod(50)) {\n\t\t\tdamage++;\n\t\t\tdamflag[NOTRACTORS] = rand_mod(smarts+10)+2;\n\t\t    }\n\t\t    if (tract(ent,dy,dx,tractor)) {\n\t\t\tevely += tractor*dy;\n\t\t\tevelx += tractor*dx;\n\t\t    }\n\t\t}\n\t    }\n\t    else if (!damage ||\n\t      (!entmode && !damflag[NOIMPULSE]) ||\n\t      (entmode && !damflag[NOWARP]) ) {\n\t\tif (!rand_mod(30+500/(abs(evely)+abs(evelx)+1))) {\n\t\t    damage++;\n\t\t    damflag[entmode?NOWARP:NOIMPULSE] = rand_mod(smarts+10)+2;\n\t\t}\n\t\tevely += dy;\n\t\tevelx += dx;\n\t    }\n\t    if (inumthols &&\n\t      (obj=occupant[(ent->posy+evely+YSIZE00)%YSIZE]\n\t\t\t   [(ent->posx+evelx+XSIZE00)%XSIZE] ) &&\n\t      obj->type == Web)\n\t\tevely = evelx = 0;\n\t}\n    }\n    else if (status == 2) {\n\tdecr = 500+abs(bvely)*5+abs(bvelx)*5+tractor*tractor*100;\n\tif (base->energy >= decr) {\n\t    base->energy -= decr;\n\t    if (tractor) {\n\t\tif (tract(base,dy,dx,tractor)) {\n\t\t    bvely += tractor*dy;\n\t\t    bvelx += tractor*dx;\n\t\t}\n\t    }\n\t    else {\n\t\tbvely += dy;\n\t\tbvelx += dx;\n\t    }\n\t    if (inumthols &&\n\t      (obj=occupant[(base->posy+bvely+YSIZE00)%YSIZE]\n\t\t\t   [(base->posx+bvelx+XSIZE00)%XSIZE] ) &&\n\t      obj->type == Web)\n\t\tbvely = bvelx = 0;\n\t}\n    }\n    tractor = 0;\n}\n\nvoid\nctrl_direction(dy,dx)\nint dy, dx;\n{\n    if (status < 2) {\n\tif (cloaking) {\n\t    char ch;\n\n\t    cloaked = FALSE;\n\t    ch = (ent->energy >= 500?'E':'e');\n\t    if (ch != ent->image) {\n\t\tsetimage(ent, ch);\n\t    }\n\t}\n\tif (!damage || !damflag[NOPHASERS]) {\n\t    if (!rand_mod(200)) {\n\t\tdamage++;\n\t\tdamflag[NOPHASERS] = rand_mod(smarts+10)+2;\n\t    }\n\t    fire_phaser(ent, dy, dx);\n\t}\n    }\n    else if (status == 2)\n\tfire_phaser(base, dy, dx);\n}\n\nvoid\nshift_direction(dy,dx)\nint dy, dx;\n{\n    if (status < 2) {\n\tif (cloaking) {\n\t    char ch;\n\n\t    cloaked = FALSE;\n\t    ch = (ent->energy >= 500?'E':'e');\n\t    if (ch != ent->image) {\n\t\tsetimage(ent, ch);\n\t    }\n\t}\n\tif (!damage || !damflag[NOTORPS]) {\n\t    if (!rand_mod(300)) {\n\t\tdamage++;\n\t\tdamflag[NOTORPS] = rand_mod(smarts+10)+2;\n\t    }\n\t    fire_torp(ent, dy, dx);\n\t}\n    }\n    else if (status == 2)\n\tfire_torp(base, dy, dx);\n}\n\nvoid\nget_commands(done)\nbool *done;\n{\n    static char ch[80];\n    register int i;\n    register int count;\n    register bool ctrla = FALSE;\n    char numdestructs = 0, numzaps = 0;\n\ntop:\n    while (count = read_nd(ch,(sizeof ch))) {\n\tfor (i=0; i<count; i++) {\n\t    if (ch[i] == 'Q') {\n\t\tbombed_out = TRUE;\n\t\t*done = TRUE;\n\t\tkeepgoing = FALSE;\n\t\treturn;\n\t    }\n\t    if (ch[i] == 'q' || ch[i] == BREAKCH || ch[i] == INTRCH) {\n\t\tint x;\n\t\tstatic char quest[] = \"Do you wish to escape from reality? \";\n\n\t\tif (timer >= whenok) {\n\t\t    mvaddstr(12,22,quest);\n\t\t    do {\n\t\t\tgetcmd(&ch[i]);\n\t\t    } while (ch[i] != 'y' && ch[i] != 'n');\n\t\t    if (ch[i] == 'y') {\n\t\t\tbombed_out = TRUE;\n\t\t\t*done = TRUE;\n\t\t\treturn;\n\t\t    }\n\t\t    else {\n\t\t\tfor (x=11; x<=28; x++) {\n\t\t\t    mvaddch(12,x*2,\n\t\t\t\toccupant[11][x]\n\t\t\t\t   ? occupant[11][x]->image\n\t\t\t\t   : numamoebas\n\t\t\t\t      ? amb[11][x]\n\t\t\t\t      : ' ');\n\t\t\t    addspace();\n\t\t\t}\n\t\t\troundsleep(2);\n\t\t\twhenok = timer + 10;\n\t\t\tgoto top;\n\t\t    }\n\t\t}\n\t\telse {\n\t\t    write(1,\"\\07\",1);\n\t\t    goto top;\n\t\t}\n\t    }\n\t}\n\tfor (i=0; i<count; i++) {\n\t    if (ctrla) {\n\t\tswitch (ch[i]) {\n\t\tcase '1': case 'b':\n\t\t    ctrl_direction(1, -1);\n\t\t    break;\n\t\tcase '2': case 'j':\n\t\t    ctrl_direction(1, 0);\n\t\t    break;\n\t\tcase '3': case 'n':\n\t\t    ctrl_direction(1, 1);\n\t\t    break;\n\t\tcase '4': case 'h':\n\t\t    ctrl_direction(0, -1);\n\t\t    break;\n\t\tcase '6': case 'l':\n\t\t    ctrl_direction(0, 1);\n\t\t    break;\n\t\tcase '7': case 'y':\n\t\t    ctrl_direction(-1, -1);\n\t\t    break;\n\t\tcase '8': case 'k':\n\t\t    ctrl_direction(-1, 0);\n\t\t    break;\n\t\tcase '9': case 'u':\n\t\t    ctrl_direction(-1, 1);\n\t\t    break;\n\t\tcase 'r':\n\t\t    rewrite();\n\t\t    roundsleep(3);\n\t\t    ctrla = FALSE;\n\t\t    goto top;\n\t\tcase 'w':\n\t\t    clear();\n\t\t    while (!input_pending())\n\t\t\tsleep(1);\n\t\t    rewrite();\n\t\t    roundsleep(3);\n\t\t    ctrla = FALSE;\n\t\t    goto top;\n#ifdef SIGTSTP\n\t\tcase 'z':\n\t\t    clear();\n\t\t    mytstp();\n\t\t    sleep(4);\n\t\t    ctrla = FALSE;\n\t\t    goto top;\n#endif\n\t\tdefault:\n\t\t    break;\n\t\t}\n\t\tctrla = FALSE;\n\t    }\n\t    else {\n\t\tswitch (ch[i]) {\n\t\tcase 'Z':\n\t\t    clear();\n\t\t    mytstp();\n\t\t    sleep(4);\n\t\t    goto top;\n\t\tcase 'i':\n\t\t    if (ent && (!damage || !damflag[NOIMPULSE])) {\n\t\t\tentmode = 0;\n\t\t\tstatus = 0;\n\t\t    }\n\t\t    break;\n\t\tcase 'w':\n\t\t    if (ent && (!damage || !damflag[NOWARP])) {\n\t\t\tentmode = 1;\n\t\t\tstatus = 1;\n\t\t    }\n\t\t    break;\n\t\tcase 'p':\n\t\t    if (base) {\n\t\t\tstatus = 2;\n\t\t    }\n\t\t    break;\n\t\tcase 'o':\n\t\t    if (status < 2) {\n\t\t\tif (base)\n\t\t\t    status = 2;\n\t\t    }\n\t\t    else if (status == 2) {\n\t\t\tif (ent)\n\t\t\t    status = entmode;\n\t\t    }\n\t\t    break;\n\t\tcase 'v':\n\t\t    if (ent) {\n\t\t\tstatus = entmode;\n\t\t    }\n\t\t    cloaking=FALSE;\n\t\t    cloaked=FALSE;\n\t\t    break;\n\t\tcase 'c':\n\t\t    if (ent) {\n\t\t\tstatus = entmode;\n\t\t\tif (ent->energy >= 250)\n\t\t\t    cloaking = TRUE;\n\t\t    }\n\t\t    break;\n\t\tcase 'z':\n\t\t    if (ent && (!damage || !damflag[NOZAPPER])) {\n\t\t\t++numzaps;\n\t\t\tif (!rand_mod(100/numzaps)) {\n\t\t\t    damage++;\n\t\t\t    damflag[NOZAPPER] = rand_mod(smarts+10)+2;\n\t\t\t}\n\t\t\tif (nxtbang && bangm[nxtbang-1] < 0)\n\t\t\t    --nxtbang;\t/* consolidate zaps */\n\t\t\tmake_blast(evely*2+ent->posy,evelx*2+ent->posx,\n\t\t\t    -5000000L, 3*numzaps);\n\t\t\tent->energy /= 2;\n\t\t    }\n\t\t    break;\n\t\tcase 'D':\n\t\t    if (status < 2 && (!damage || !damflag[NODESTRUCT])) {\n\t\t\tif (ent && !rand_mod(10)) {\n\t\t\t    damage++;\n\t\t\t    damflag[NODESTRUCT] = rand_mod(smarts+10)+2;\n\t\t\t}\n\t\t\tif (++numdestructs <= 2)\n\t\t\t    make_blast(evely*2+ent->posy,evelx*2+ent->posx,\n\t\t\t\t15000L, 3);\n\t\t\tent->energy /= 4;\n\t\t    }\n\t\t    else if (status == 2) {\n\t\t\tif (numdestructs)\n\t\t\t    base->energy = base->energy / 2;\n\t\t\tif (++numdestructs <= 2)\n\t\t\t    make_blast(base->posy, base->posx, 15000L, 5);\n\t\t    }\n\t\t    break;\n\t\tcase 'd':\n\t\t    if ((!damage || !damflag[NODESTRUCT]) && (base||ent)) {\n\t\t\tregister OBJECT *obj;\n\t\t\tint x, y;\n\n\t\t\tif (ent && !rand_mod(200)) {\n\t\t\t    damage++;\n\t\t\t    damflag[NODESTRUCT] = rand_mod(smarts+10)+2;\n\t\t\t}\n\t\t\tfor (obj = root.prev;\n\t\t\t  obj != &root;\n\t\t\t  obj = obj->prev) {\n\t\t\t    if (obj->image == '+') {\n\t\t\t\tblast[y=(obj->posy+obj->vely+YSIZE00)%YSIZE]\n\t\t\t\t     [x=(obj->posx+obj->velx+XSIZE00)%XSIZE]\n\t\t\t\t     += 1;\n\t\t\t\tyblasted[y] |= 1;\n\t\t\t\txblasted[x] |= 1;\n\t\t\t\tblasted = TRUE;\n\t\t\t\tobj->mass = (massacre?3000:4000);\n\t\t\t    }\n\t\t\t}\n\t\t    }\n\t\t    break;\n\t\tcase 's':\n\t\t    if ((!damage || !damflag[NODESTRUCT]) && (base||ent)) {\n\t\t\tregister OBJECT *obj;\n\t\t\tif (ent && !rand_mod(200)) {\n\t\t\t    damage++;\n\t\t\t    damflag[NODESTRUCT] = rand_mod(smarts+10)+2;\n\t\t\t}\n\t\t\tfor (obj = root.prev;\n\t\t\t  obj->type == Torp || obj->type == Web ||\n\t\t\t  obj->type == Star;\n\t\t\t  obj = obj->prev) {\n\t\t\t    if (obj->image == '+')\n\t\t\t\tobj->vely = obj->velx = 0;\n\t\t\t}\n\t\t    }\n\t\t    break;\n\t\tcase '\\001':\n\t\t    ctrla = TRUE;\n\t\t    break;\n\t\tcase '\\002':\n\t\tcase '\\003':\n\t\tcase '\\004':\n\t\tcase '\\005':\n\t\tcase '\\006':\n\t\tcase '\\007':\n\t\tcase '\\010':\n\t\tcase '\\011':\n\t\tcase '\\012':\n\t\tcase '\\013':\n\t\tcase '\\014':\n\t\tcase '\\015':\n\t\tcase '\\016':\n\t\tcase '\\017':\n\t\tcase '\\020':\n\t\tcase '\\021':\n\t\tcase '\\022':\n\t\tcase '\\023':\n\t\tcase '\\024':\n\t\tcase '\\025':\n\t\tcase '\\026':\n\t\tcase '\\027':\n\t\tcase '\\030':\n\t\tcase '\\031':\n\t\tcase '\\032':\n\t\t    ch[i] += 96;\n\t\t    i--;\n\t\t    ctrla = TRUE;\n\t\t    break;\n\t\tcase '\\033':\n\t\t    tractor = 0;\n\t\t    break;\n\t\tcase 'a':\n\t\t    tractor++;\n\t\t    break;\n\t\tcase 'r':\n\t\t    tractor--;\n\t\t    break;\n\t\tcase '1': case 'b':\n\t\t    do_direction(1,-1);\n\t\t    break;\n\t\tcase '2': case 'j':\n\t\t    do_direction(1,0);\n\t\t    break;\n\t\tcase '3': case 'n':\n\t\t    do_direction(1,1);\n\t\t    break;\n\t\tcase '4': case 'h':\n\t\t    do_direction(0,-1);\n\t\t    break;\n\t\tcase '6': case 'l':\n\t\t    do_direction(0,1);\n\t\t    break;\n\t\tcase '7': case 'y':\n\t\t    do_direction(-1,-1);\n\t\t    break;\n\t\tcase '8': case 'k':\n\t\t    do_direction(-1,0);\n\t\t    break;\n\t\tcase '9': case 'u':\n\t\t    do_direction(-1,1);\n\t\t    break;\n\t\tcase '0': case 'S':\n\t\t    if (status < 2) {\n\t\t\tevely = 0;\n\t\t\tevelx = 0;\n\t\t    }\n\t\t    break;\n\t\tcase '-':\n\t\t    if (status < 2 && ent->energy >= 10) {\n\t\t\tevely *= -1;\n\t\t\tevelx *= -1;\n\t\t\tent->energy -= 10;\n\t\t    }\n\t\t    break;\n\t\tcase '%': case '\\177': case '_':\n\t\t    shift_direction(0, -1);\n\t\t    shift_direction(0, 1);\n\t\t    shift_direction(-1, 0);\n\t\t    shift_direction(1, 0);\n\t\t    shift_direction(-1, -1);\n\t\t    shift_direction(-1, 1);\n\t\t    shift_direction(1, -1);\n\t\t    shift_direction(1, 1);\n\t\t    break;\n\t\tcase '!': case 'B':\n\t\t    shift_direction(1, -1);\n\t\t    break;\n\t\tcase '@': case 'J':\n\t\t    shift_direction(1, 0);\n\t\t    break;\n\t\tcase '#': case 'N':\n\t\t    shift_direction(1, 1);\n\t\t    break;\n\t\tcase '$': case 'H':\n\t\t    shift_direction(0, -1);\n\t\t    break;\n\t\tcase '^': case 'L':\n\t\t    shift_direction(0, 1);\n\t\t    break;\n\t\tcase '&': case 'Y':\n\t\t    shift_direction(-1, -1);\n\t\t    break;\n\t\tcase '*': case 'K':\n\t\t    shift_direction(-1, 0);\n\t\t    break;\n\t\tcase '(': case 'U':\n\t\t    shift_direction(-1, 1);\n\t\t    break;\n\t\tcase '?':\n\t\t    helper();\n\t\t    roundsleep(3);\n\t\t    goto top;\n\t\tdefault:\n\t\t    break;\n\t\t}\n\t    }\n\t}\n    }\n}\n"
  },
  {
    "path": "games/warp/us.h",
    "content": "/* $Header: us.h,v 7.0.1.1 86/10/16 10:53:58 lwall Exp $ */\n\n/* $Log:\tus.h,v $\n * Revision 7.0.1.1  86/10/16  10:53:58  lwall\n * Added Damage.  Fixed random bugs.\n * \n * Revision 7.0  86/10/08  15:14:27  lwall\n * Split into separate files.  Added amoebas and pirates.\n * \n */\n\nEXT bool cloaking;\nEXT bool cloaked;\n\nEXT int status;\nEXT int entmode;\n\nEXT int evely;\nEXT int evelx;\nEXT int bvely;\nEXT int bvelx;\n\n#define MAXDAMAGE 9\n#define NOWARP 0\n#define NOIMPULSE 1\n#define NOPHASERS 2\n#define NOTORPS 3\n#define NOCLOAKING 4\n#define NOSHIELDS 5\n#define NOZAPPER 6\n#define NODESTRUCT 7\n#define NOTRACTORS 8\n\nEXT int dam INIT(0);\nEXT int lastdam INIT(-1);\nEXT int damage INIT(0);\nEXT int olddamage INIT(-1);\n\n#ifdef DOINIT\nchar *dammess[MAXDAMAGE] = {\n    \"WARP\",\n    \"IMPULSE\",\n    \"PHASERS\",\n    \"TORPS\",\n    \"CLOAKING\",\n    \"SHIELDS\",\n    \"ZAPPER\",\n    \"DESTRUCT\",\n    \"TRACTORS\"\n};\nchar damflag[MAXDAMAGE] = {0,0,0,0,0,0,0,0,0};\n#else\nextern char *dammess[];\nextern char damflag[];\n#endif\n\nvoid do_direction();\nvoid ctrl_direction();\nvoid shift_direction();\nvoid get_commands();\nvoid us_init();\n"
  },
  {
    "path": "games/warp/util.c",
    "content": "/* $Header: util.c,v 7.0.1.2 86/10/20 12:07:46 lwall Exp $ */\n\n/* $Log:\tutil.c,v $\n * Revision 7.0.1.2  86/10/20  12:07:46  lwall\n * Made all exits reset tty.\n *\n * Revision 7.0.1.1  86/10/16  10:54:02  lwall\n * Added Damage.  Fixed random bugs.\n *\n * Revision 7.0  86/10/08  15:14:31  lwall\n * Split into separate files.  Added amoebas and pirates.\n *\n */\n\n#include \"EXTERN.h\"\n#include \"warp.h\"\n#include \"object.h\"\n#include \"sig.h\"\n#include \"term.h\"\n#include \"INTERN.h\"\n#include \"util.h\"\n\nvoid\nutil_init()\n{\n    ;\n}\n\nvoid\nmovc3(len,src,dest)\nregister char *dest;\nregister char *src;\nregister int len;\n{\n    if (dest <= src) {\n\tfor (; len; len--) {\n\t    *dest++ = *src++;\n\t}\n    }\n    else {\n\tdest += len;\n\tsrc += len;\n\tfor (; len; len--) {\n\t    *--dest = *--src;\n\t}\n    }\n}\n\nvoid\nno_can_do(what)\nchar *what;\n{\n    fprintf(stderr,\"Sorry, your terminal is too %s to play warp.\\r\\n\",what);\n    finalize(1);\n}\n\nint\nexdis(maxnum)\nint maxnum;\n{\n    double temp, temp2;\n    double exp();\n    double log();\n\n    temp = (double) maxnum;\n    temp2 = (double) myrand();\n    return (int) exp(temp2 * log(temp)/0x7fff);\n}\n\nstatic char nomem[] = \"warp: out of memory!\\r\\n\";\n\n/* paranoid version of malloc */\n\nchar *\nsafemalloc(size)\nMEM_SIZE size;\n{\n    char *ptr;\n\n    ptr = malloc(size?size:1);\t/* malloc(0) is NASTY on our system */\n    if (ptr != Nullch)\n\treturn ptr;\n    else {\n\tfputs(nomem,stdout);\n\tsig_catcher(0);\n    }\n    /*NOTREACHED*/\n}\n\n/* safe version of string copy */\n\nchar *\nsafecpy(to,from,len)\nchar *to;\nregister char *from;\nregister int len;\n{\n    register char *dest = to;\n\n    if (from != Nullch)\n\tfor (len--; len && (*dest++ = *from++); len--) ;\n    *dest = '\\0';\n    return to;\n}\n\n/* copy a string up to some (non-backslashed) delimiter, if any */\n\nchar *\ncpytill(to,from,delim)\nregister char *to;\nregister char *from;\nregister int delim;\n{\n    for (; *from; from++,to++) {\n\tif (*from == '\\\\' && from[1] == delim)\n\t    from++;\n\telse if (*from == delim)\n\t    break;\n\t*to = *from;\n    }\n    *to = '\\0';\n    return from;\n}\n\n/* return ptr to little string in big string, NULL if not found */\n\nchar *\ninstr(big, little)\nchar *big, *little;\n\n{\n    register char *t;\n    register char *s;\n    register char *x;\n\n    for (t = big; *t; t++) {\n\tfor (x=t,s=little; *s; x++,s++) {\n\t    if (!*x)\n\t\treturn Nullch;\n\t    if (*s != *x)\n\t\tbreak;\n\t}\n\tif (!*s)\n\t    return t;\n    }\n    return Nullch;\n}\n\n/* effective access */\n\n#ifdef SETUIDGID\nint\neaccess(filename, mod)\nchar *filename;\nint mod;\n{\n    int protection, euid;\n\n    mod &= 7;\t\t\t\t/* remove extraneous garbage */\n    if (stat(filename, &filestat) < 0)\n\treturn -1;\n    euid = geteuid();\n    if (euid == 0)\n\treturn 0;\n    protection = 7 & (filestat.st_mode >>\n      (filestat.st_uid == euid ? 6 :\n        (filestat.st_gid == getegid() ? 3 : 0)\n      ));\n    if ((mod & protection) == mod)\n\treturn 0;\n    errno = EACCES;\n    return -1;\n}\n#endif\n\n/* copy a string to a safe spot */\n\nchar *\nsavestr(str)\nchar *str;\n{\n    register char *newaddr = safemalloc((MEM_SIZE)(strlen(str)+1));\n\n    strcpy(newaddr,str);\n    return newaddr;\n}\n\nchar *\ngetval(nam,def)\nchar *nam,*def;\n{\n    char *val;\n\n    if ((val = getenv(nam)) == Nullch || !*val)\n\tval = def;\n    return val;\n}\n"
  },
  {
    "path": "games/warp/util.h",
    "content": "/* $Header: util.h,v 7.0 86/10/08 15:14:37 lwall Exp $ */\n\n/* $Log:\tutil.h,v $\n * Revision 7.0  86/10/08  15:14:37  lwall\n * Split into separate files.  Added amoebas and pirates.\n *\n */\n\n#define RANDRAND 268435456.0 /* that's 2**28 */\n#define HALFRAND 0x4000 /* that's 2**14 */\nint rand();\n#define myrand() (rand()&32767)\n#define rand_mod(m) ((int)((double)myrand() / 32768.0 * ((double)(m))))\n/* pick number in 0..m-1 */\n\n#define roundsleep(x) sleep(x)\n\nvoid movc3();\nvoid no_can_do();\nint exdis();\n\nEXT bool waiting INIT(FALSE);\t\t/* are we waiting for subprocess (in doshell)? */\n\nvoid util_init();\nchar *safemalloc();\nchar *safecpy();\nchar *cpytill();\nchar *instr();\n#ifdef SETUIDGID\n    int eaccess();\n#endif\nchar *savestr();\nchar *getval();\n"
  },
  {
    "path": "games/warp/version.c",
    "content": "/* $Header: version.c,v 7.0 86/10/08 15:14:39 lwall Exp $\n *\n * $Log:\tversion.c,v $\n * Revision 7.0  86/10/08  15:14:39  lwall\n * Split into separate files.  Added amoebas and pirates.\n *\n */\n\n#include \"patchlevel.h\"\n#include \"INTERN.h\"\n#include \"version.h\"\n#include <stdio.h>\n\n/* Print out the version number. */\n\nvoid\nversion()\n{\n    extern char rcsid[];\n\n    printf(\"%s\\r\\nPatch level: %d\\r\\n\", rcsid, PATCHLEVEL);\n}\n"
  },
  {
    "path": "games/warp/version.h",
    "content": "/* $Header: version.h,v 7.0 86/10/08 15:14:43 lwall Exp $\n *\n * $Log:\tversion.h,v $\n * Revision 7.0  86/10/08  15:14:43  lwall\n * Split into separate files.  Added amoebas and pirates.\n * \n */\n\nvoid version();\n"
  },
  {
    "path": "games/warp/warp.6",
    "content": ".TH WARP 6 \"June 20, 1987\"\n.SH NAME\nwarp - a real-time space war game\n.SH SYNOPSIS\n.B warp [options]\n.SH DESCRIPTION\n.I Warp\nis a real-time space war game that requires skill and quick thinking.\n\"Real-time\" in this context means that the enemies keep moving (and shooting)\neven if you don't.\nA unique feature of\n.I warp\nis that blast propagates; it is unhealthy to remain near things that are\nin the process of blowing up.\nIf a given universe is above a critical density it may chain react.\nScoring is like many popular arcade games--there are multiple waves which\nget harder and harder as you go along.\nNobody has ever maxed out the scoreboard without cheating.\n.PP\nUnlike many space-war games,\n.I warp\nis not simply a shooting gallery.\nAlong with phasers and photon torpedoes, you have tractor beams and a cloaking\ndevice.\nSkill in navigation is important.\nIt helps to be schizophrenic, because you must manage an Enterprise and a Base\nsimultaneously.\nAnd enemies do not simply shoot back.\nYou can get tailed, absorbed, snuck up upon, hemmed in, rammed, loved to death,\nreprimanded for destroying civilized life, dragged around, robbed, damaged\nand eaten.\nAnd if you should happen to get bored by the enemies (a trifle unlikely),\nyou can always watch the interesting star patterns.\nIn fact, you'll have to, since your tactics will depend upon what kind of\nuniverse you find yourself in.\n.PP\n.I Warp\nis played in a double wraparound universe, i.e. the bottom is connected to the\ntop, and the right is connected to the left.\nYou need a crt with random cursor addressing and at least 24 lines by 80\ncolumns.\nFor more information about about how to play, simply run\n.I warp\nand say \"y\" when it asks if you want to see the instructions.\nThere is also a single-page command summary that you can get while playing\nby typing a \"?\".\n.PP\nCommand line options include:\n.TP 5\n.B -b\nPut\n.I warp\ninto beginner mode.\nMakes the difficulty increase more slowly, but penalizes you for it.\n.TP 5\n.B -d<n>\nSets the initial difficulty to\n.BR n .\n.TP 5\n.B -l\nPlay a low-speed game.\nChanges the basic cycle time from 1 second to 2 seconds.\nThis switch is automatically set at baud rates below 2400.\nYou may want to set it at higher speeds if your terminal cannot keep up\nwith the output.\n(This should never happen on BSD systems, which have an IOCTL call to\ndetermine output queue length.)\nBecause this makes the game easier, a separate scoreboard is kept for\nlow-speed games.\n.TP 5\n.B -m\nTerminal has a meta key which turns on the eighth bit.  Ordinarily the\neighth bit is stripped in order to ignore parity.\nMetacharacters will appear to the keymap as prefixed with a ^A, and will\nsubsequently have the same effect as a control character, unless otherwise\nmapped.\n.TP 5\n.B -s\nJust prints out the scoreboards and saved games and then exits.\n.TP 5\n.B -v\nPrints out the version number.\n.TP 5\n.B -x\nPlay an experimental game.\nThis causes\n.I warp\nto ignore any saved game, and disables the ability to save\nthe current game.\nThus you can play around with something or show\n.I warp\nto someone without jeopardizing a currently saved game.\n.SH ENVIRONMENT\n.TP 5\n.B WARPMACRO\nIf defined, names a file containing keyboard mappings and macros.\nIf not defined, the value %X/Kbmap.%{TERM} is assumed.\nThe macro file contains lines of the following form:\n.sp\n<keystroke-sequence> <whitespace> <canonical-keystroke-sequence>\n.sp\nYou may use certain % interpolations and ^<letter> control characters.\nFor possible % interpolations see warp.h.\nSequences in the canonical-keystroke-sequence bounded by ^(...^) are\nsubject to reinterpretation via the keymap.\nThis file has two major uses.\nFirst, you can set up your commands to use any kind of prefix key your terminal\nmight have, or change the key bindings in any other way you choose.\nSecond, you can define arbitrary macros, such as this:\n.sp\n# define Corbamite maneuver\n=\tDDllllll\n.SH AUTHOR\nLarry Wall <lwall@sdcrdcf.UUCP>\n.SH FILES\n~/.fullname, if full names aren't in /etc/passwd\n.SH DIAGNOSTICS\nGenerally self-documenting, as they say.\n.SH BUGS\nAddicting.\nAt the end of a wave, all you have to do to keep going is hit a space.\nYou see the message \"Hit space to continue\" and automatically hit space.\nAbout 2 seconds later you remember you wanted to go home, but by then\nit's too late to escape without penalty.\n.PP\nYou can't kill a backgrounded\n.I warp\nprocess directly, because it is running setuid.\nYou have to use the killer built in to\n.IR warp .\n.PP\nNow that there is a space amoeba, there ought to be tribbles.\nBut it might be too much trouble...\n"
  },
  {
    "path": "games/warp/warp.c",
    "content": "char rcsid[] = \"@(#)$Header: warp.c,v 7.0.1.3 86/12/12 17:07:44 lwall Exp $\";\n\n/*\twarp -- a real-time space war program\n *\tauthor: Larry Wall\n *\thelpers: Jonathan and Mark Biggar, and Dan Faigin\n *\tspecial thanks to my sweetie Gloria who suggested the Planet Crusher\n *\n *\tCopyright (C) 1986, Larry Wall\n *\n *\tThis program may be copied as long as this copyright notice is\n *\tincluded, and as long as it is not being copied for purposes\n *\tof profit.  If you want to modify this program in any way other\n *\tthan normal configuration changes, common decency would suggest\n *\tthat you also modify the name of the program so that my good name\n *\t(what there is of it) is not impugned.  (Calling it something like\n *\t\"warpx\" or \"superwarp\" would be fine.)  Also, give it another\n *\tWARPDIR so that the scoreboards don't get confused.\n *\n * version 5.0  04/20/83\n *         5.1  05/05/83\tvarious tidbits\n *\t   5.2  05/12/83\tVAX -> vax, ifdef'ed a SIGCONT\n *\t   5.3  05/24/83\tRCS\n *\n * $Log:\twarp.c,v $\n * Revision 7.0.1.3  86/12/12  17:07:44  lwall\n * Baseline for net release.\n *\n * Revision 7.0.1.2  86/10/20  12:08:00  lwall\n * Made all exits reset tty.\n *\n * Revision 7.0.1.1  86/10/16  10:54:13  lwall\n * Added Damage.  Fixed random bugs.\n *\n * Revision 7.0  86/10/08  15:14:47  lwall\n * Split into separate files.  Added amoebas and pirates.\n *\n * Revision 6.4  83/12/16  13:11:45  lwall\n * Handled 15 bit random number generators.\n *\n * Fixed array overflow bug on multiple zaps.\n *\n * Multiple zaps now consolidated to minimize output.\n *\n * Tholian jackpot games outlawed under difficulty 15.\n *\n * Revision 6.3  83/08/24  11:17:49  lwall\n * Fixed array overflow bug on multiple zap.\n *\n * Revision 6.2  83/08/23  18:06:37  lwall\n * Added zap command.\n * Warp -s should now work on dumb terminals\n * Specifying difficulty >= 40 now just makes it a special game.\n * SIGTTOU #ifdef'ed.\n * No-delay read provided as alternative to FIONREAD.\n * Warp won't report \"-1 obsolete\" when there are no Enterprises left.\n * Some high-difficulty tuning.\n *\n * Revision 6.1  83/08/17  08:49:03  lwall\n * Fixed obscure bug in storing UP that caused a %. in CM to occasionally\n * foist garbage onto the screen.\n *\n * Revision 6.0  83/08/08  17:09:26  lwall\n * New baseline version for net release.\n *\n * Revision 5.5  83/08/01  10:59:56  lwall\n * Cloaking for the Enterprise.\n * Difficulty now goes to 99, and many activities depending on difficulty\n *     have been adjusted in frequency.\n * Simplified exit sequence, and reduced dependencies on control\n *     characters.  You needn't see the scoreboard if you don't want to.\n * Hitting i,w,c, or v switches to Enterprise.  Hitting p switches to Base.\n * Excessive use of q is not allowed.\n * Excessive use of D is not allowed.\n * Scoreboard may depend on either full name or login name.\n * Integrated scoreboard lister.  Login name now shows up on scoreboard.\n * \"Hidden\" startup options are now upper case.\n * Checks upon startup for no cursor movement, or screen too small.\n * Checks upon startup that WARPDIR is correctly protected, and that warp\n *     is running setuid.  As an additional bonus this prevents root from\n *     running warp, which mucks things up, UN*X be blessed.\n * All gets's turned into fgets's for safety.\n * Bonus Enterprises and Bases.\n * Escalating bonuses for saving Base and Enterprise.\n * Escalating Enterprise energy.\n * Turbolasers decrease with distance.\n * Really smart enemies can see through stars occasionally.\n * Occasional Tholian jackpot waves.  Tholians are a trifle nastier.\n * Choleric Gorns.\n * An O or o can miss seeing you.  Enemies can avoid a stationary O, o, or X.\n * Warp 3 enemies and other nastinesses are possible in massacre mode.\n * Enemies that decide to navigate when they see you can do other things than\n *     just come toward you.\n * Gorns occasionally launch a salvo for the fun of it.\n * Only star and enemy explosions can keep the round going now.\n * Bounces don't always go back to starting spot now.\n * Better full name processing.  USG quirks handled.  & substitution also\n *     handled now (whoever dreamed up that one must have been in the middle\n *     of the night before the morning after).\n * Catch ^D on fgets.\n * Version number printer.\n * Less signal catching during debugging.\n *\n * Revision 5.4  83/06/24  09:28:38  lwall\n * 16 bit random number generators are now supported.\n * Made warp not blow up on a null save file.\n * Warp now prints E and B before the stars.\n * Fixed bug which caused torp count to get decremented even when no torp\n *     was launched because of an obstacle.\n * Put %<n>ld formats where appropriate.\n * Fixed E: 0  0 bug on refresh.\n *\n * Revision 5.3  83/05/24  14:03:10  lwall\n * Starting RCS\n *\n */\n\n#include \"INTERN.h\"\n#include \"warp.h\"\n#include \"EXTERN.h\"\n#include \"bang.h\"\n#include \"init.h\"\n#include \"intrp.h\"\n#include \"object.h\"\n#include \"move.h\"\n#include \"play.h\"\n#include \"score.h\"\n#include \"sig.h\"\n#include \"term.h\"\n#include \"them.h\"\n#include \"us.h\"\n#include \"util.h\"\n#include \"version.h\"\n#include \"weapon.h\"\n\nmain(argc,argv)\nint argc;\nchar *argv[];\n{\n    char tmp, *s, *tcbuf;\n\n    int i;\n\n    FILE *savfil;\n\nrand_ok:\n\n    while (--argc > 0 && (*++argv)[0] == '-')\n\tfor (s = argv[0]+1; *s != '\\0'; s++)\n\t    switch (*s) {\n\t    case '&':\n\t\tamoebaspec = TRUE;\n\t\tbeginner = TRUE;\n\t\tbreak;\n\t    case 'A':\n\t\tapolspec = TRUE;\n\t\tbeginner = TRUE;\n\t\tbreak;\n\t    case 'b':\n\t\tbeginner = TRUE;\n\t\tbreak;\n\t    case 'C':\n\t\tcrushspec = TRUE;\n\t\tbeginner = TRUE;\n\t\tbreak;\n\t    case 'D':\n\t\tdebugging = TRUE;\n#ifdef DEBUGGING\n\t\tdebug = atoi(++s);\n#endif\n\t\ts += strlen(s)-1;\n\t\tbreak;\n\t    case 'd':\n\t\ts++;\n\t\tif (*s == '=') s++;\n\t\tismarts = atoi(s);\n\t\tif (ismarts <= 0)\n\t\t    ismarts = 1;\n\t\tif (ismarts > 99)\n\t\t    ismarts = 99;\n\t\tif (ismarts > 40)\n\t\t    beginner = TRUE;\n\t\ts += strlen(s)-1;\n\t\tbreak;\n\t    case 'E':\n\t\tklingspec = TRUE;\n\t\tbeginner = TRUE;\n\t\ts++;\n\t\tif (*s == '=') s++;\n\t\tinumenemies = atoi(s);\n\t\ts += strlen(s)-1;\n\t\tbreak;\n\t    case 'F':\n\t\tfriendspec = TRUE;\n\t\tbeginner = TRUE;\n\t\ts++;\n\t\tif (*s == '=') s++;\n\t\tinumfriends = atoi(s);\n\t\ts += strlen(s)-1;\n\t\tbreak;\n\t    case 'G':\n\t\tgornspec = TRUE;\n\t\tbeginner = TRUE;\n\t\tbreak;\n\t    case 'l':\n\t\tlowspeed = TRUE;\n\t\tbreak;\n\t    case 'm':\n\t\tmetakey = TRUE;\n\t\tbreak;\n\t    case 'M':\n\t\tmassacre = TRUE;\n\t\tbreak;\n\t    case 'P':\n\t\tpiratespec = TRUE;\n\t\tbeginner = TRUE;\n\t\ts++;\n\t\tif (*s == '=') s++;\n\t\tinumpirates = atoi(s);\n\t\ts += strlen(s)-1;\n\t\tbreak;\n\t    case 'S':\n\t\tprespec = TRUE;\n\t\tbeginner = TRUE;\n\t\ts++;\n\t\tif (*s == '=') s++;\n\t\tif (*s)\n\t\t    prescene = atoi(s);\n\t\telse\n\t\t    prescene = -1;\n\t\ts += strlen(s)-1;\n\t\tbreak;\n\t    case 'R':\n\t\tromspec = TRUE;\n\t\tbeginner = TRUE;\n\t\tbreak;\n\t    case '*':\n\t\tstarspec = TRUE;\n\t\tbeginner = TRUE;\n\t\ts++;\n\t\tif (*s == '=') s++;\n\t\tinumstars = atoi(s);\n\t\ts += strlen(s)-1;\n\t\tbreak;\n\t    case 's':\n\t\tscorespec = TRUE;\n\t\tbreak;\n\t    case 'T':\n\t\ttholspec = TRUE;\n\t\tbeginner = TRUE;\n\t\tbreak;\n\t    case 'x':\n\t\texperimenting = TRUE;\n\t\tbreak;\n\t    case 'v':\n\t\tversion();\n\t\texit(0);\n\t\tbreak;\n\t    default:\n\t\tfprintf(stderr,\"warp: illegal option %c\\n\", *s);\n\t\tfprintf(stderr, \"Usage: warp -dn -b -x -v -s\\n\");\n\t\texit(1);\n\t    }\n    if (argc != 0) {\n\tfprintf(stderr, \"Usage: warp -dn -b -x -v -s\\n\");\n\texit(1);\n    }\n    bang_init();\n    move_init();\n    object_init();\n    play_init();\n    them_init();\n    us_init();\n    util_init();\n    weapon_init();\n\n    tcbuf = malloc(1024);\n    intrp_init(tcbuf);\n\n    if (chdir(warplib) < 0)\n\tfprintf(stderr,nocd,warplib);\n\n    term_init();\n\n    term_set(tcbuf);\n    free(tcbuf);\n\n    umask(022);     /* mustn't rely on incoming umask--could be 033 which */\n\t\t    /* would disable people from running wscore */\n\n    score_init();\n\n    sig_init();\n\n    if (totalscore) {\n\tclear();\n\tmvaddstr(12,25,\"*** restoring saved game ***\");\n\troundsleep(1);\n    }\n\n    srand(getpid());\n\n    do {\n\tfor (keepgoing = TRUE;;) {\n\t    if (!experimenting) {\n\t\tif ((savfil = fopen(savefilename,\"w\")) == NULL) {\n\t\t    resetty();\n\t\t    printf(\"Can't open savefile\\r\\n\");\n\t\t    finalize(1);\n\t\t}\n\t\tfprintf(savfil,\n\t\t    \"%-8s %10ld, %2d,%5d,%2d,%2d,%3d %c%c%c%c%c%c%c%c%c\\n\",\n\t\t    logname, totalscore, smarts, cumsmarts,\n\t\t    numents, numbases, wave,\n\t\t    apolspec ? 'a' : ' ',\n\t\t    beginner   ? 'b' : ' ',\n\t\t    crushspec  ? 'c' : ' ',\n\t\t    gornspec   ? 'g' : ' ',\n\t\t    massacre   ? 'm' : ' ',\n\t\t    romspec    ? 'r' : ' ',\n\t\t    tholspec   ? 't' : ' ',\n\t\t    lowspeed   ? 'l' : ' ',\n\t\t    amoebaspec ? '&' : ' '\n\t\t);\n\t\tfprintf(savfil,\"         running on %s, process #%d\\n\",\n\t\t    term+5,getpid());\n\t\tFclose(savfil);\n\t    }\n\n\t    lastscore = totalscore;\n\t    initialize();\n\t    play();\n\t    cumsmarts += smarts;\n\t    wavescore();\n\t    if (numents<=0 && numbases<=0)\n\t\tkeepgoing = FALSE;\n\t  if (!keepgoing) break;\n\t    do {\n\t\tif (experimenting) {\n\t\t    mvaddstr(23,15,\n\t\t      \"      [Hit space to continue, 'q' to quit]       \");\n\t\t}\n\t\telse {\n\t\t    mvaddstr(23,15,\n\t\t      \"[Hit space to continue, 's' to save, 'q' to quit]\");\n\t\t}\n\t\tsleep(1);\n\t\tFflush(stdout);\n\t\teat_typeahead();\n\t\tgetcmd(&tmp);\n\t\tif (tmp == BREAKCH || tmp == INTRCH) {\n\t\t    mvaddstr(23,15,\n\t\t      \"                                                 \");\n\t\t    mvaddstr(23,33,\n\t\t      \"Really quit? \");\n\t\t    getcmd(&tmp);\n\t\t    if (tmp == 'y' || tmp == 'Y')\n\t\t\ttmp = 'q';\n\t\t    else\n\t\t\ttmp = 1;\n\t\t}\n\t    } while (tmp != INTRCH && tmp != BREAKCH && !strchr(\" qQs\",tmp));\n\t  if (tmp != ' ' && tmp != 's') break;\n\t    if (!beginner && smarts < 20)\n\t\tsmarts += 4;\n\t    else if (!beginner && smarts < 35)\n\t\tsmarts += 2;\n\t    else if (smarts < 99)\n\t\tsmarts++;\n\t  if (tmp == 's') save_game();\n\t}\n\tscore();\n\n    } while (justonemoretime);\n\n    if (!experimenting)\n\tunlink(savefilename);\n\n    clear();\n    resetty();\n    exit(0);\n}\n"
  },
  {
    "path": "games/warp/warp.doc",
    "content": "Warp is a real-time space war game.  This means that the enemies will keep\nplaying even when you sit still.  Another peculiarity is that things which\nblow up can damage other things around them.  Universes above a critical\ndensity may chain react.\n\nThe game starts at difficulty 1, and gets more difficult with each\nsucceeding wave, up to difficulty 99.  You're not likely to get that far.\n(Invoking warp with a -b switch causes the difficulty to increase more\nslowly, but games count only a tenth as much.)  The game starts with\n5 Enterprises and 3 Bases, and you get more for surviving long enough.\nThe game is over when you run out of Enterprises and Bases.\n\nThe object of the game is to get as many points as possible.  This is done\nby destroying as many enemies as possible.  This is not a trivial task.\nEach wave starts with one Enterprise and one Base, and continues until\neither both the Enterprise and Base are destroyed, or all the enemies\n(including any homing torpedoes) are destroyed.  It is possible to abort a\nwave, but you will be penalized for it.  The game may be saved between waves.\n\nA -x switch causes any saved game to be ignored, and causes the new game\nnot to be saveable.  Hence it is possible to run test games without\ninvalidating a currently saved game.\n\f\nThe game is played in a 23 x 40 double wrap-around universe.  Everybody\n(both you and the enemies) gets the chance to move once every second,\nunless a -l (low-speed) switch was given or you are under 2400 baud, in\nwhich case it's every two seconds.  The following symbols are displayed:\n\n\t\t\t\tFRIENDS\nE\tEnterprise with shields\t\te\tEnterprise without shields\nC\tCloaked E with shields\t\tc\tCloaked E without shields\nB\tBase with shields\t\tb\tBase without shields\n+\tFriendly torpedo\t\tM\tHarry Mudd\n\n\t\t\t\tENEMIES\nK\tKlingon\t\t\t\tG\tGorn\nR\tRomulan\t\t\t\tA\tApollo\n\tRomulan with cloaking device!\t&\tSpace Amoeba Nucleus\nT\tTholian\t\t\t\t>,<\tPlanet crusher\nx,X\tHostile torpedo\t\t\to,O\tHoming torpedo\nP\tPirate\t\t\t\tM\tHarry Mudd\n\n\t\t\t    MISCELLANEOUS\n*\tStar\t\t\t\t@\tInhabited star\n|,-,/,\\\tWeb\t\t\t\t~\tProtoplasm\nother\tFriendly Freighter, for now...\n\f\nThe following keys control the DIRECTION of your various actions:\n\n\th or 4          left\n\tj or 2          down\n\tk or 8          up\n\tl or 6          right\n\tb or 1          down and left\n\tn or 3          down and right\n\ty or 7          up and left\n\tu or 9          up and right\n\n(You will note that the letters are the same as other visual games, and the\nnumbers are for use with a keypad.)  By themselves, these keys move either\nthe Enterprise or the Base, whichever is the current vessel.  When shifted,\nthey fire photon torpedoes in the specified direction from the current\nvessel.  When used with either the CTRL key or the FUNCT key, phasers\n(turbo-lasers for the Base) are fired in the specified direction.  (CTRL\nwon't work with numbers, and FUNCT probably doesn't exist on non-TVI\nterminals.)  When preceded by an 'a', an attractor beam is fired in the\nspecified direction, and when preceded by an 'r', a repulsor beam is fired.\n\f\nThese keys have special functions:\n\n\tdel or %        fire photon torpedoes in every (reasonable) direction\n\ts               stop all friendly torpedoes\n\tS or 0          stop the Enterprise when in warp mode\n\td               destruct all friendly torpedoes (quite useful)\n\tD               destruct the current vessel (commit suicide)\n\ti/w             switch to Enterprise and put into impulse/warp mode\n\tc/v             switch to Enterprise and put into cloaking/visible mode\n\tp\t\tswitch to Base (not very mnemonic, but 'b' is taken)\n\to               switch from Enterprise to Base, or vice versa\n\tz\t\tzap explosions (multiple zaps extend further) (E only)\n\n\t^R              refresh the screen\n\t^Z              suspend the game (on a bsd system)\n\tq               asks if you want to exit this wave (will not work\n\t\t\t    within 10 cycles of previous q command)\n\tQ\t\texit this game (not wave)\n\t?               display a summary of these commands\n\nThere may be additional commands listed in your terminal's keymap file.\nUnrecognized keystrokes are ignored.  IF YOU FORGET ALL THE OTHER COMMANDS,\nREMEMBER \"?\", which gives you help.\n\f\nCommands for moving the Enterprise may operate in one of two ways.  If it\nis in impulse mode, movement commands affect the position of the ship;\nif it is in warp mode, movement commands affect the velocity instead.\nThe Base always moves in impulse mode.  Since multiple commands may be\nentered in one turn (if you can type fast enough), it is possible to jump\nover things even in impulse mode.  In a crowded universe this may be the\nonly way to go.\n\n(Actually, motion commands always change the velocity--the actual motion\ndoes not occur until the next turn.  Impulse mode simply causes the\nvelocity to be zeroed out at the end of every turn.  Phaser commands, on\nthe other hand, are executed immediately.  If you want to move and fire a\nphaser, you must wait for the motion to actually occur before typing the\nphaser command, or the phaser fires from your old position.  This is a\nfeature, not a bug, and is intended to reflect reality.  Really.)\n\nIf multiple torpedo launching commands are given in a turn, a single torpedo\nis launched with extra velocity.  You can thus launch photon torpedoes over\nobjects in the way, and get them where you want them quickly.  This feature\nworks well with the destruct button.  Variations on this may be useful\nagainst the Space Amoeba.\n\f\nNOTE:  Phasers destroy the target by blasting the projected next location of\nthe object hit.  This means that if the object hit, be it Klingon, Romulan or\nEnterprise, changes velocity in the same turn, it can elude the effect of\nthe phaser!  (Note that this also means that if you phaser a Klingon or\ntorpedo that is about to ram you, you will be phasered as well as he/she/it.\nThis can be embarrassing, not to mention deadly.)  Smart players move\nimmediately upon phasering something at short range, or whenever they\nthink they might get phasered (in other words, most of the time).\n\nObjects with larger mass can bounce objects with smaller mass out of the way.\nIn a crowded universe the bouncee can bounce quite a way before finding an\nempty place to land.  If you let the Tholians fill up the universe with web,\nso that there is no place to bounce to, the Tholians win that wave.\n\nThe status line across the top gives the current mode, the number of\npoints accumulated this wave, the Enterprise's energy and torpedoes, the\nBase's energy and torpedoes, the number of stars, the number of enemies,\nand the stardate.  You will note that nice things happen to your energy levels\nwhen you put the Enterprise next to the Base, or the Base next to some stars.\nBad things happen inside an Amoeba.\n\f\nAn object is destroyed when its energy goes negative, either from a direct\nhit, or from the blast of the previous turn's explosions.  Enemies and\nstars start with random amounts of energy.  High energy enemies can go warp\n2.  A Romulan with sufficient energy maintains a cloaking device.  Tholians\nspin web, Gorns shoot homing torpedoes, and the Planet Crusher munches\nanything in its way, even Apollo.  Apollo won't let you go unless you kill\nhim, but he loves you very much and beefs up your shields considerably.\nBoth Apollo and the Planet Crusher recharge themselves, so you must hit\nthem hard in a single turn to do them in. (Yes, the Planet Crusher must be\nshot in the mouth--he can only die of gluttony--and he blasts out of his\nmouth when he dies.)  Tholian web may be crossed only by coasting across it\nin warp mode, or by blasting it (but web blasts extend twice as far as\nnormal blasts, so keep your distance).  The Space Amoeba sucks energy and\ngrows, and you must destroy the nucleus.  Somehow.  There are at least four\nways.  Phasers won't work on the big ones.\n\nPirates turn inhabited star systems into uninhabited ones.  Even Friendly\nFreighters will take potshots at you if you get them mad enough.\n\f\nNote that because of the size of the Base's turbo-lasers (the Base does not\nhave phasers) they cannot shoot anything next to the Base.  (This is why the\nDeath Star died!)  In part, this is to protect the Enterprise.  It also lets\nyou shoot over one adjacent star.  The Enterprise's phasers will shoot over\na arbitrary number of adjacent, contiguous stars, including inhabited ones.\nPhasers die away with distance, so don't expect them to kill everything with\none blow.\n\nWhile the Enterprise's shields are up (when it is displayed as \"E\" rather\nthan \"e\"), hits on it count only a fifth as much (or even less if you are\nmoving in warp mode).  The shields are automatically maintained as long as\nthere are more than 500 units of energy for the Enterprise.  The Base also\nhas shields, which stay up as long as it has at least 1000 units of energy.\n\nAside from losing energy, the Enterprise can also take damage, either random\ndamage from getting blasted, or specific damage when a system is in use\nand breaks down under the load.  In place of the score you will see the\nEstimated Time to Repair.  Sometimes docking helps to get things fixed faster.\nIf you lose both your warp and impulse engines, try the tractors.  The\nBase doesn't take damage because it has much more redundancy than the\nEnterprise.\n\f\nYou get points for destroying enemies and hostile torpedoes.  At the end of\na wave, you also get bonus points for saving stars, saving the Enterprise\nand Base, and for having an efficiency rating higher that 0.8.  You get\nNEGATIVE bonus points for letting friendly life forms get blown up, and for\ngiving up.  Bonuses tend to be scaled by the ratio of the number of points\nyou got over the number of points you could have got.  If you think you are\ndone with a wave, but it won't quit, there may be homing torpedoes that you\nhaven't destroyed--you must make the universe safe for posterity, you know.\n\nWhen you have used up your Enterprises and Bases (or quit), your score will\nbe posted to the scoreboard.  You may see the scoreboard outside of the game\nsimply by giving the command \"warp -s\".\n\nIf you get bored, you can always play with some of the undocumented switches\nthat are used to test warp.  Such funny games go on their own scoreboard.\nFor kicks try \"warp -x -d50 -C -\\& -G -T -E400 -S5\" and then go hide.  Quick.\n\f\n"
  },
  {
    "path": "games/warp/warp.h",
    "content": "/* $Header: warp.h,v 7.0.1.3 95/21/1 17:08:42 lwall Exp $ */\n\n/* $Log:\twarp.h,v $\n * Revision 7.0.1.3 95/21/1 18:40:00 sms\n * Remove ifdefs around pwd.h\n *\n * Revision 7.0.1.2  86/12/12  17:08:42  lwall\n * Baseline for net release.\n *\n * Revision 7.0.1.1  86/10/16  10:54:26  lwall\n * Added Damage.  Fixed random bugs.\n *\n * Revision 7.0  86/10/08  15:17:55  lwall\n * Split into separate files.  Added amoebas and pirates.\n *\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <signal.h>\n#include <ctype.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <errno.h>\n\n/* WARPLIB must be readable and writeable by warp, but not by anyone who you\n * don't trust.  In other words, to set up warp so everyone can play and\n * no one can cheat, give warp a uid of its own and make warp setuid to\n * that uid.  WARPLIB must then NOT be made writeable by the world,\n * since no attempt is made to encrypt saved games or anything.\n * (It must be readable by the world, however, due to a strangeness in\n * access.)\n */\n\n#define SAVEDIR \"./\"\n#define NEWSFILE \"warp.news\"\n#define HELPFILE \"warp.doc\"\n#define LOCKFILE \".warp.lock\"\n#define LOGFILE \"warp.log\"\n#define SCOREBOARD \"warp.top\"\n#define LSCOREBOARD \"warp.lowtop\"\n#define FSCOREBOARD \"warp.funtop\"\n#define TMPSCOREBOARD \"warp.topnew\"\n#define WARPMACRO \"%X/Kbmap.%{TERM}\"\n\n/* warp library */\n#ifndef WARPLIB\t\t/* ~ and %l only (\"~%l\" is permissable) */\n#   define WARPLIB \"/usr/games/warp\"\n#endif\n\nEXT char *warplib;\n\n#define PERMMAPS 8\t/* how many starmaps are permanent */\n#define MAPS 20\t\t/* how many starmaps to choose from */\n\t\t\t/* (MAPS - PERMMAPS is # of half-gone universes) */\n\n/*\n * Screen size info, minimum screen size is 23x40 (actually 24x80).\n * YSIZE and XSIZE should be relatively prime so that a torpedo launched\n * at an angle will eventually cover the whole screen.\n * To calculate a new position for something:\n * new_position = (current_position + delta + ?SIZE00) % ?SIZE\n * This allows for negative deltas of up to ?SIZE00 (% doesn't work right\n * on negative numbers).\n * ?SIZE01, etc. are fudges for efficiency--they already include a delta.\n */\n\n#define XYSIZE 920\n#define XYSIZEx4 3680\n\n#define YSIZE   23\n#define YSIZE00 2300\n#define YSIZE01 2301\n#define YSIZE99 2299\n\n#define XSIZE   40\n#define XSIZE00 4000\n#define XSIZE01 4001\n#define XSIZE99 3999\n#define XSIZE02 4002\n#define XSIZE98 3998\n#define XSIZE03 4003\n#define XSIZE97 3997\n#define XSIZE08 4008\n#define XSIZE92 3992\n\nEXT char amb[YSIZE][XSIZE];\n\n#ifndef isalnum\n#   define isalnum(c) (isalpha(c) || isdigit(c))\n#endif\n\n#include <sys/ioctl.h>\n#include <fcntl.h>\n#include <pwd.h>\n\n#ifdef TERMIO\n#   include <termio.h>\n#else\n#   include <sgtty.h>\n#endif\n\n#define BITSPERBYTE 8\n#define LBUFLEN 512\t/* line buffer length */\n\n#define CBUFLEN 256\t/* command buffer length */\n#define PUSHSIZE 128\n#define MAXFILENAME 128\n#define FINISHCMD 0177\n\n/* some handy defs */\n\n#define bool char\n#define TRUE (1)\n#define FALSE (0)\n#define Null(t) ((t)0)\n#define Nullch Null(char *)\n#define Nullfp Null(FILE *)\n\n#define Ctl(ch) (ch & 037)\n\n#define strNE(s1,s2) (strcmp(s1,s2))\n#define strEQ(s1,s2) (!strcmp(s1,s2))\n#define strnNE(s1,s2,l) (strncmp(s1,s2,l))\n#define strnEQ(s1,s2,l) (!strncmp(s1,s2,l))\n\n#define sgn(x) ((x) < 0 ? -1 : (x) > 0)\n\n/* Things we can figure out ourselves */\n\n#ifdef SIGPROF\n#   define BSD42\t\t/* do we have Berkeley 4.2? */\n#endif\n\n#ifdef FIONREAD\n#   define PENDING\n#else\n#   ifdef O_NDELAY\n#\tdefine PENDING\n#   endif\n#endif\n\n#ifdef EUNICE\n#   define UNLINK(victim) while (!unlink(victim))\n#else\n#   define UNLINK(victim) unlink(victim)\n#endif\n\n/* Valid substitutions for strings marked with % comment are:\n *\t%H\tHost name (yours)\n *\t%L\tLogin name (yours)\n *\t%N\tFull name (yours)\n *\t%O\tOriginal working directory (where you ran warp from)\n *\t%X\tWarp library directory\n *\t%~\tHome directory\n *\t%.\tDirectory containing . files\n *\t%$\tcurrent process number\n *\t%{name} Environment variable \"name\".  %{name-default} form allowed.\n *\t%\"prompt\"\n *\t\tPrint prompt and insert what is typed.\n *\t%`command`\n *\t\tInsert output of command.\n *\t%(test_text=pattern?if_text:else_text)\n *\t\tSubstitute if_text if test_text matches pattern, otherwise\n *\t\tsubstitute else_text.  Use != for negated match.\n *\t\t% substitutions are done on test_text, if_text, and else_text.\n *\t\t(Note: %() only works if CONDSUB defined.)\n */\n\n/* *** System Dependent Stuff *** */\n\n/* NOTE: many of these are defined in the config.h file */\n\n#ifndef LOGDIRFIELD\n#   define LOGDIRFIELD 6\t\t/* Which field (origin 1) is the */\n\t\t\t\t\t/* login directory in /etc/passwd? */\n\t\t\t\t\t/* (If it is not kept in passwd, */\n\t\t\t\t\t/* but getpwnam() returns it, */\n\t\t\t\t\t/* define the symbol GETPWENT) */\n#endif\n#ifndef GCOSFIELD\n#   define GCOSFIELD 5\n#endif\n\n/* Undefine any of the following features to save both I and D space */\n/* In general, earlier ones are easier to get along without */\n/* Pdp11's without split I and D may have to undefine them all */\n#define DEBUGGING\t/* include debugging code */\n#define PUSHBACK\t/* macros and keymaps using pushback buffer */\n#define CONDSUB\t\t/* allow %(cond?text:text) */\n#define BACKTICK\t/* allow %`command` */\n#define PROMPTTTY\t/* allow %\"prompt\" */\n#define GETLOGIN\t/* use getlogin() routine as backup to environment */\n\t\t\t/* variables USER or LOGNAME */\n#define TILDENAME\t/* allow ~logname expansion */\n#define SETUIDGID\t/* substitute eaccess() for access() so that rn */\n\t\t\t/* can run setuid or setgid */\n\t\t\t/* if not setuid or setgid, you don't need it */\n#define VERBOSE\t\t/* compile in more informative messages */\n#define TERSE\t\t/* compile in shorter messages */\n\n/* some dependencies among options */\n\n#ifndef SETUIDGID\n#   define eaccess access\n#endif\n\n#ifdef VERBOSE\n#   ifdef TERSE\n#\tdefine IF(c) if (c)\n#\tdefine ELSE else\n#   else /* !TERSE */\n#\tdefine IF(c)\n#\tdefine ELSE\n#   endif\n#else /* !VERBOSE */\n#   ifndef TERSE\n#\tdefine TERSE\n#   endif\n#   define IF(c) \"IF\" outside of VERBOSE???\n#   define ELSE \"ELSE\" outside of VERBOSE???\n#endif\n\n#ifdef DEBUGGING\n#   define assert(ex) {if (!(ex)){fprintf(stderr,\"Assertion failed: file %s, line %d\\r\\n\", __FILE__, __LINE__);sig_catcher(0);}}\n#else\n#   define assert(ex) ;\n#endif\n\n#define TCSIZE 512\t/* capacity for termcap strings */\n\n/* End of Space Conservation Section */\n\n/* More System Dependencies */\n#define sigset signal\n#define sigignore(sig) signal(sig,SIG_IGN)\n\n/* preferred shell for use in doshell routine */\n/*  ksh or sh would be okay here */\n#ifndef PREFSHELL\n#   define PREFSHELL \"/bin/csh\"\n#endif\n\n/* path to fastest starting shell */\n#ifndef SH\n#   define SH \"/bin/sh\"\n#endif\n\n/* location of macro file */\n#ifndef WARPMACRO\n#   ifdef PUSHBACK\n#\tdefine WARPMACRO \"%./.warpmac\"\n#   endif\n#endif\n\n/* a motd-like file for warp */\n#ifndef WARPNEWSNAME\t\t/* % and ~ */\n#   define WARPNEWSNAME \"%X/warp.news\"\n#endif\n\n/* typedefs */\n\ntypedef unsigned int\tMEM_SIZE;\t/* for passing to malloc */\n\n/* *** end of the machine dependent stuff *** */\n\n/* GLOBAL THINGS */\n\n/* file statistics area */\n\nEXT struct stat filestat;\n\nEXT char buf[LBUFLEN+1];\t/* general purpose line buffer */\n\nEXT char *cwd INIT(Nullch);\t\t/* current working directory */\n\n/* switches */\n\n#ifdef DEBUGGING\n    EXT int debug INIT(0);\t\t\t\t/* -D */\n#   define DEB_FILEXP 64\n#endif\n\n#ifdef VERBOSE\n#   ifdef TERSE\n\tEXT bool verbose INIT(TRUE);\t\t\t/* +t */\n#   endif\n#endif\n\n/* miscellania */\n\nEXT FILE *tmpfp INIT(Nullfp);\t/* scratch fp */\n\n#define NOMARKING 0\n#define STANDOUT 1\n#define UNDERLINE 2\n\n/* Factored strings */\n\nEXT char nullstr[] INIT(\"\");\nEXT char readerr[] INIT(\"warp read error\");\nEXT char cantopen[] INIT(\"Can't open %s\\r\\n\");\n\n#ifdef VERBOSE\n    EXT char nocd[] INIT(\"Can't chdir to directory %s\\r\\n\");\n#else\n    EXT char nocd[] INIT(\"Can't find %s\\r\\n\");\n#endif\n\nextern int errno;\n\nEXT bool justonemoretime INIT(TRUE);\nEXT bool keepgoing INIT(TRUE);\n\nEXT bool friendspec INIT(FALSE);\nEXT bool piratespec INIT(FALSE);\nEXT bool amoebaspec INIT(FALSE);\nEXT bool starspec INIT(FALSE);\nEXT bool klingspec INIT(FALSE);\nEXT bool apolspec INIT(FALSE);\nEXT bool crushspec INIT(FALSE);\nEXT bool romspec INIT(FALSE);\nEXT bool prespec INIT(FALSE);\nEXT bool tholspec INIT(FALSE);\nEXT bool gornspec INIT(FALSE);\nEXT bool beginner INIT(FALSE);\nEXT bool massacre INIT(FALSE);\nEXT bool lowspeed INIT(FALSE);\nEXT bool debugging INIT(FALSE);\nEXT bool didkill INIT(FALSE);\nEXT bool experimenting INIT(FALSE);\nEXT bool scorespec INIT(FALSE);\nEXT bool metakey INIT(FALSE);\n\nEXT bool bombed_out;\nEXT bool panic INIT(FALSE);\nEXT bool madgorns;\n\nEXT int madfriends;\n\nEXT int inumpirates;\nEXT int numpirates;\nEXT int inumfriends;\nEXT int numfriends;\nEXT int inumamoebas;\nEXT int numamoebas;\nEXT int inumstars;\nEXT int numstars;\nEXT int inumenemies;\nEXT int numenemies;\nEXT int inumroms;\nEXT int inumthols;\nEXT int inumapollos;\nEXT int numapollos;\nEXT int apolloflag;\nEXT int inumcrushes;\nEXT int numcrushes;\nEXT int inumgorns;\nEXT int numgorns;\nEXT int deados;\nEXT int deadmudds;\nEXT int smarts;\nEXT int ismarts INIT(0);\nEXT int numos INIT(0);\nEXT int numxes INIT(0);\nEXT int ient;\nEXT int numents;\nEXT int ibase;\nEXT int numbases;\nEXT int inuminhab;\nEXT int numinhab;\nEXT int wave;\nEXT int cumsmarts;\nEXT int prescene INIT(-1);\nEXT int scandist;\nEXT int antibase;\nEXT int sm35;\nEXT int sm45;\nEXT int sm50;\nEXT int sm55;\nEXT int sm80;\nEXT int sm95;\nEXT int entmax;\nEXT int basemax;\nEXT int enemshields;\nEXT int super;\nEXT int whenok;\nEXT int yamblast;\nEXT int xamblast;\nEXT int ambsize;\n\nEXT char spbuf[512];\n\n#define Fclose (void)fclose\n#define Fflush (void)fflush\n#define Sprintf (void)sprintf\n#define Signal (void)signal\n#define Safecpy (void)safecpy\n#define Cpytill (void)cpytill\n#define Tract (void)tract\n#define Make_object (void)make_object\n#define Read_tty (void)read_tty\n"
  },
  {
    "path": "games/warp/warp.man",
    "content": ".TH WARP 6 \"June 20, 1987\"\n.SH NAME\nwarp - a real-time space war game\n.SH SYNOPSIS\n.B warp [options]\n.SH DESCRIPTION\n.I Warp\nis a real-time space war game that requires skill and quick thinking.\n\"Real-time\" in this context means that the enemies keep moving (and shooting)\neven if you don't.\nA unique feature of\n.I warp\nis that blast propagates; it is unhealthy to remain near things that are\nin the process of blowing up.\nIf a given universe is above a critical density it may chain react.\nScoring is like many popular arcade games--there are multiple waves which\nget harder and harder as you go along.\nNobody has ever maxed out the scoreboard without cheating.\n.PP\nUnlike many space-war games,\n.I warp\nis not simply a shooting gallery.\nAlong with phasers and photon torpedoes, you have tractor beams and a cloaking\ndevice.\nSkill in navigation is important.\nIt helps to be schizophrenic, because you must manage an Enterprise and a Base\nsimultaneously.\nAnd enemies do not simply shoot back.\nYou can get tailed, absorbed, snuck up upon, hemmed in, rammed, loved to death,\nreprimanded for destroying civilized life, dragged around, robbed, damaged\nand eaten.\nAnd if you should happen to get bored by the enemies (a trifle unlikely),\nyou can always watch the interesting star patterns.\nIn fact, you'll have to, since your tactics will depend upon what kind of\nuniverse you find yourself in.\n.PP\n.I Warp\nis played in a double wraparound universe, i.e. the bottom is connected to the\ntop, and the right is connected to the left.\nYou need a crt with random cursor addressing and at least 24 lines by 80\ncolumns.\nFor more information about about how to play, simply run\n.I warp\nand say \"y\" when it asks if you want to see the instructions.\nThere is also a single-page command summary that you can get while playing\nby typing a \"?\".\n.PP\nCommand line options include:\n.TP 5\n.B -b\nPut\n.I warp\ninto beginner mode.\nMakes the difficulty increase more slowly, but penalizes you for it.\n.TP 5\n.B -d<n>\nSets the initial difficulty to\n.BR n .\n.TP 5\n.B -l\nPlay a low-speed game.\nChanges the basic cycle time from 1 second to 2 seconds.\nThis switch is automatically set at baud rates below 2400.\nYou may want to set it at higher speeds if your terminal cannot keep up\nwith the output.\n(This should never happen on BSD systems, which have an IOCTL call to\ndetermine output queue length.)\nBecause this makes the game easier, a separate scoreboard is kept for\nlow-speed games.\n.TP 5\n.B -m\nTerminal has a meta key which turns on the eighth bit.  Ordinarily the\neighth bit is stripped in order to ignore parity.\nMetacharacters will appear to the keymap as prefixed with a ^A, and will\nsubsequently have the same effect as a control character, unless otherwise\nmapped.\n.TP 5\n.B -s\nJust prints out the scoreboards and saved games and then exits.\n.TP 5\n.B -v\nPrints out the version number.\n.TP 5\n.B -x\nPlay an experimental game.\nThis causes\n.I warp\nto ignore any saved game, and disables the ability to save\nthe current game.\nThus you can play around with something or show\n.I warp\nto someone without jeopardizing a currently saved game.\n.SH ENVIRONMENT\n.TP 5\n.B WARPMACRO\nIf defined, names a file containing keyboard mappings and macros.\nIf not defined, the value %X/Kbmap.%{TERM} is assumed.\nThe macro file contains lines of the following form:\n.sp\n<keystroke-sequence> <whitespace> <canonical-keystroke-sequence>\n.sp\nYou may use certain % interpolations and ^<letter> control characters.\nFor possible % interpolations see warp.h.\nSequences in the canonical-keystroke-sequence bounded by ^(...^) are\nsubject to reinterpretation via the keymap.\nThis file has two major uses.\nFirst, you can set up your commands to use any kind of prefix key your terminal\nmight have, or change the key bindings in any other way you choose.\nSecond, you can define arbitrary macros, such as this:\n.sp\n# define Corbamite maneuver\n=\tDDllllll\n.SH AUTHOR\nLarry Wall <lwall@sdcrdcf.UUCP>\n.SH FILES\n~/.fullname, if full names aren't in /etc/passwd\n.SH DIAGNOSTICS\nGenerally self-documenting, as they say.\n.SH BUGS\nAddicting.\nAt the end of a wave, all you have to do to keep going is hit a space.\nYou see the message \"Hit space to continue\" and automatically hit space.\nAbout 2 seconds later you remember you wanted to go home, but by then\nit's too late to escape without penalty.\n.PP\nYou can't kill a backgrounded\n.I warp\nprocess directly, because it is running setuid.\nYou have to use the killer built in to\n.IR warp .\n.PP\nNow that there is a space amoeba, there ought to be tribbles.\nBut it might be too much trouble...\n"
  },
  {
    "path": "games/warp/warp.news",
    "content": "\t\t\t  ***  WARP NEWS  ***\n\nWelcome to warp!  Please send any gripes, comments, fantastic ideas, etc.\nto lwall@sdcrdcf.uucp (Larry Wall).\n"
  },
  {
    "path": "games/warp/weapon.c",
    "content": "/* $Header: weapon.c,v 7.0.1.2 86/10/20 14:36:33 lwall Exp $ */\n\n/* $Log:\tweapon.c,v $\n * Revision 7.0.1.2  86/10/20  14:36:33  lwall\n * Picked some lint.\n *\n * Revision 7.0.1.1  86/10/16  10:54:42  lwall\n * Added Damage.  Fixed random bugs.\n *\n * Revision 7.0  86/10/08  15:18:08  lwall\n * Split into separate files.  Added amoebas and pirates.\n *\n */\n\n#include \"EXTERN.h\"\n#include \"warp.h\"\n#include \"bang.h\"\n#include \"object.h\"\n#include \"move.h\"\n#include \"score.h\"\n#include \"sig.h\"\n#include \"term.h\"\n#include \"them.h\"\n#include \"us.h\"\n#include \"util.h\"\n#include \"INTERN.h\"\n#include \"weapon.h\"\n\nvoid\nweapon_init()\n{\n    ;\n}\n\nvoid\nfire_torp(from, ydir, xdir)\nregister OBJECT *from;\nregister int ydir;\nregister int xdir;\n{\n    register OBJECT *to;\n\n    if (from->type == Enemy ||\n       (from == ent && etorp > 0) ||\n       (from == base && btorp > 0)) {\n\tto = occupant[(from->posy+from->vely+ydir+YSIZE00)%YSIZE]\n\t\t     [(from->posx+from->velx+xdir+XSIZE00)%XSIZE];\n\tif (from->type != Enemy || !to || to->vely || to->velx) {\n\t    if (from->type != Enemy &&\n\t\t (to = isatorp[from==base][ydir+1][xdir+1])) {\n\t\tto->vely += ydir;\n\t\tto->velx += xdir;\n\t    }\n\t    else {\n\t\tif (from == ent) {\n\t\t    to = make_object(Torp, '+', from->posy,from->posx,\n\t\t\tfrom->vely+ydir,from->velx+xdir, 0L, 1L,&root);\n\t\t    aretorps++;\n\t\t    isatorp[0][ydir+1][xdir+1] = to;\n\t\t    etorp--;\n\t\t}\n\t\telse if (from == base) {\n\t\t    to = make_object(Torp, '+', from->posy,from->posx,\n\t\t\tfrom->vely+ydir,from->velx+xdir, 0L, 1L,&root);\n\t\t    aretorps++;\n\t\t    isatorp[1][ydir+1][xdir+1] = to;\n\t\t    btorp--;\n\t\t}\n\t\telse if (from->image == 'G') {\n\t\t    numos++;\n\t\t    to = make_object(Torp, 'o', from->posy,from->posx,\n\t\t\tfrom->vely+ydir,from->velx+xdir, 100L, 1L,&root);\n\t\t    if (madgorns) {\n\t\t\tpossiblescore += 35;\n\t\t\tto->image = '0';\n\t\t\tto->mass = 2000;\n\t\t\tto->energy = 2000;\n\t\t    }\n\t\t    else if (rand_mod(120)+10 > smarts)\n\t\t\tpossiblescore += 100;\n\t\t    else {\n\t\t\tpossiblescore += 200;\n\t\t\tto->image = 'O';\n\t\t    }\n\t\t}\n\t\telse {\n\t\t    to = make_object(Torp, 'x', from->posy,from->posx,\n\t\t\tfrom->vely+ydir,from->velx+xdir, 0L, 1L,&root);\n\t\t    if (rand_mod(160)+10 > smarts)\n\t\t\tpossiblescore += 10;\n\t\t    else {\n\t\t\tpossiblescore += 100;\n\t\t\tto->image = 'X';\n\t\t\tto->mass = 1000+super*20;\n\t\t\tnumxes++;\n\t\t    }\n\t\t}\n\t    }\n\t}\n    }\n}\n\nvoid\nattack(attackee)\nregister OBJECT *attackee;\n{\n    register int dx;\n    register int dy;\n    register int curx;\n    register int cury;\n    register int prob;\n    register OBJECT *obj;\n    register bool torps;\n    register bool webnear = FALSE;\n    register bool thru_stars;\n    int nukey;\n    int nukex;\n    int nukedist;\n\n    if (attackee) {\n\tif (attackee == nuke) {\n\t    if (amb[attackee->posy][attackee->posx] != '~')\n\t\treturn;\n\t    nukey = nukex = 0;\n\t    nukedist = 100;\n\t}\n\tfor (dx= -1; dx<=1 ; dx++) {\n\t    for (dy= -1; dy<=1; dy++) {\n\t\tif (dx||dy) {\n\t\t    cury = attackee->posy;\n\t\t    curx = attackee->posx;\n\t\t    torps = thru_stars = FALSE;\n\t\t    if (massacre || madgorns || !rand_mod(53-super) )\n\t\t\twebnear += rand_mod(2);\n\t\t    else\n\t\t\twebnear = FALSE;\n\t\t    for (prob = scandist;prob;prob--) {\n\t\t\tcury = (cury + dy + YSIZE00) % YSIZE;\n\t\t\tcurx = (curx + dx + XSIZE00) % XSIZE;\n\t\t\tif (obj = occupant[cury][curx]) {\n\t\t\t    switch (obj->image) {\n\t\t\t    case 'P': case 'K': case 'R': case ' ':\n\t\tpot_shot:\n\t\t\t\tif (attackee == nuke) {\n\t\t\t\t    if (rand_mod(2+scandist-prob) <\n\t\t\t\t      rand_mod(smarts/40+1))\n\t\t\t\t\tTract(nuke,dy,dx,rand_mod(3)?1:-1);\n\t\t\t\t}\n\t\t\t\tif (rand_mod(51 - sm50) <= prob) {\n\t\t\t\t    switch (obj->strategy||thru_stars?0:\n\t\t\t\t\t  rand_mod(ent?4:2)) {\n\t\t\t\t    case 1: case 2:\n\t\t\t\t\tif (-dy + attackee->vely == obj->vely\n\t\t\t\t\t && -dx + attackee->velx == obj->velx)\n\t\t\t\t\t    fire_torp(obj,\n\t\t\t\t\t     -dy + attackee->vely,\n\t\t\t\t\t     -dx + attackee->velx);\n\t\t\t\t\telse\n\t\t\t\t\t    fire_torp(obj,\n\t\t\t\t\t     -dy + attackee->vely - obj->vely,\n\t\t\t\t\t     -dx + attackee->velx - obj->velx);\n\t\t\t\t\tif (obj->image == ' ')\n\t\t\t\t\t    setimage(obj,\n\t\t\t\t\t      obj->flags & PIRATE ? 'P' : 'R');\n\t\t\t\t\tbreak;\n\t\t\t\t    case 3: {\n\t\t\t\t\tint newspeed =\n\t\t\t\t\t    rand_mod(prob<5&&smarts>70?4:3)-1;\n\n\t\t\t\t\tobj->vely = -dy * newspeed;\n\t\t\t\t\tobj->velx = -dx * newspeed;\n\t\t\t\t\tif (newspeed >= 0 &&\n\t\t\t\t\t    !rand_mod(82-sm80)) {\n\t\t\t\t\t    obj->vely += attackee->vely;\n\t\t\t\t\t    obj->velx += attackee->velx;\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t\t    }\n\t\t\t\t    case 0:\n\t\t\t\t\tif (!torps && obj->energy > 1000) {\n\t\t\t\t\t    fire_phaser(obj, -dy, -dx);\n\t\t\t\t\t    if (smarts > 40 &&\n\t\t\t\t\t       (scandist-prob > 5\n\t\t\t\t\t\t|| attackee==base) &&\n\t\t\t\t\t       (massacre || obj->strategy ||\n\t\t\t\t\t        rand_mod(2)))\n\t\t\t\t\t\twhile (rand_mod(2))\n\t\t\t\t\t\t    fire_phaser(obj, -dy, -dx);\n\t\t\t\t\t    if (obj->image == ' ')\n\t\t\t\t\t\tsetimage(obj,\n\t\t\t\t\t\t  obj->flags&PIRATE ? 'P':'R');\n\t\t\t\t\t}\n\t\t\t\t\tif (obj->strategy) {\n\t\t\t\t\t    obj->velx = obj->vely = 0;\n\t\t\t\t\t    if (obj->energy < 1000 ||\n\t\t\t\t\t\t  bvely || bvelx)\n\t\t\t\t\t\tobj->strategy = 0;\n\t\t\t\t\t}\n\t\t\t\t\telse if ((attackee==base ||\n\t\t\t\t\t\t  (cloaking && attackee==ent)\n\t\t\t\t\t\t ) &&\n\t\t\t\t\t\t scandist-prob > 5 &&\n\t\t\t\t\t         !(rand_mod(\n\t\t\t\t\t\t   ent?antibase*2:antibase)) )\n\t\t\t\t\t    obj->strategy = 1;\n\t\t\t\t\tbreak;\n\t\t\t\t    }\n\t\t\t\t}\n\t\t\t\tgoto bombout;\n\t\t\t    case 'G':\n\t\t\t\tif (thru_stars && obj->strategy < 7)\n\t\t\t\t    goto bombout;\n\t\t\t\tif (attackee == nuke) {\n\t\t\t\t    if (rand_mod(2+scandist-prob) <\n\t\t\t\t      rand_mod(smarts/40+1))\n\t\t\t\t\tTract(nuke,dy,dx,rand_mod(3)?1:-1);\n\t\t\t\t    goto bombout;\n\t\t\t\t}\n\t\t\t\tif (obj->strategy) {\n\t\t\t\t    if (madgorns || !rand_mod(4)) {\n\t\t\t\t\tobj->vely = attackee->vely;\n\t\t\t\t\tobj->velx = attackee->velx;\n\t\t\t\t    }\n\t\t\t\t    obj->strategy += (!torps && deados > 10);\n\t\t\t\t    if (obj->strategy > 4)\n\t\t\t\t\tmadgorns = TRUE;\n\t\t\t\t    if (!torps && obj->strategy > 5) {\n\t\t\t\t\tdo {\n\t\t\t\t\t    fire_phaser(obj, -dy, -dx);\n\t\t\t\t\t} while (rand_mod(2));\n\t\t\t\t    }\n\t\t\t\t}\n\t\t\t\telse if (numgorns >= numenemies-1 &&\n\t\t\t\t    deados > 15+numgorns*5)\n\t\t\t\t    obj->strategy = 1;\n\t\t\t\tif (madgorns || rand_mod(51 - sm50) <= prob) {\n\t\t\t\t    if (-dy + attackee->vely == obj->vely\n\t\t\t\t     && -dx + attackee->velx == obj->velx)\n\t\t\t\t\tfire_torp(obj,\n\t\t\t\t\t -dy + attackee->vely,\n\t\t\t\t\t -dx + attackee->velx);\n\t\t\t\t    else\n\t\t\t\t\tfire_torp(obj,\n\t\t\t\t\t -dy + attackee->vely - obj->vely,\n\t\t\t\t\t -dx + attackee->velx - obj->velx);\n\t\t\t\t}\n\t\t\t\tgoto bombout;\n\t\t\t    case 'T':\n\t\t\t\tif (attackee == nuke) {\n\t\t\t\t    if (rand_mod(2+scandist-prob) <\n\t\t\t\t      rand_mod(smarts/40+1))\n\t\t\t\t\tTract(nuke,dy,dx,rand_mod(3)?1:-1);\n\t\t\t\t}\n\t\t\t\tif (thru_stars)\n\t\t\t\t    goto bombout;\n\t\t\t\tif (webnear && scandist-prob > 5) {\n\t\t\t\t    if (massacre || rand_mod(50) < super) {\n\t\t\t\t\tif (!torps && obj->energy > 1000) {\n\t\t\t\t\t    fire_phaser(obj, -dy, -dx);\n\t\t\t\t\t    while (!rand_mod(57-sm55))\n\t\t\t\t\t\tfire_phaser(obj, -dy, -dx);\n\t\t\t\t\t}\n\t\t\t\t    }\n\t\t\t\t}\n\t\t\t\tgoto bombout;\n\t\t\t    case 'C': case 'c':\n\t\t\t\tif (thru_stars)\n\t\t\t\t    goto bombout;\n\t\t\t\tbreak;\n\t\t\t    case 'Q': case 'W': case 'Y': case 'U':\n\t\t\t    case 'I': case 'S': case 'D': case 'H': case 'J':\n\t\t\t    case 'L': case 'Z': case 'V': case 'M': case 'F':\n\t\t\t\tif (attackee == nuke) {\n\t\t\t\t    if (rand_mod(2+scandist-prob) <\n\t\t\t\t      rand_mod(smarts/40+1))\n\t\t\t\t\tTract(nuke,dy,dx,rand_mod(3)?1:-1);\n\t\t\t\t    if (rand_mod(2))\n\t\t\t\t\tgoto pot_shot;\n\t\t\t\t}\n\t\t\t\tif (madfriends > 1000) {\n\t\t\t\t    madfriends -= 200;\n\t\t\t\t    goto pot_shot;\n\t\t\t\t}\n\t\t\t\t/* FALL THROUGH */\n\t\t\t    case '+':\n\t\t\t\tif (attackee == nuke) {\n\t\t\t\t    if (smarts > 70) {\n\t\t\t\t\tif (\n\t\t\t\t\t (obj->posx + obj->velx + XSIZE00)%XSIZE\n\t\t\t\t\t    == attackee->posx &&\n\t\t\t\t\t (obj->posy + obj->vely + YSIZE00)%YSIZE\n\t\t\t\t\t    == attackee->posy ) {\n\t\t\t\t\t    Tract(nuke,dy,dx,-1);\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t    while (!rand_mod(82-sm80))\n\t\t\t\t\t\tTract(nuke,dy,dx,-1);\n\t\t\t\t    }\n\t\t\t\t    else if (smarts > 60 ||\n\t\t\t\t      rand_mod(2+scandist-prob) <\n\t\t\t\t      rand_mod(smarts/20+1))\n\t\t\t\t\tTract(nuke,dy,dx,rand_mod(3)?1:-1);\n\t\t\t\t}\n\t\t\t\ttorps = FALSE;\n\t\t\t\tthru_stars = FALSE;\n\t\t\t\tbreak;\n\t\t\t    case '|': case '-': case '/': case '\\\\':\n\t\t\t\tif (thru_stars)\n\t\t\t\t    goto bombout;\n\t\t\t\twebnear = (scandist-prob < 3);\n\t\t\t\ttorps = FALSE;\n\t\t\t\tbreak;\n\t\t\t    case 'x':\n\t\t\t\tif (attackee == nuke) {\n\t\t\t\t    if (rand_mod(2+scandist-prob) <\n\t\t\t\t      rand_mod(smarts/20+1))\n\t\t\t\t\tTract(nuke,dy,dx,rand_mod(3)?1:-1);\n\t\t\t\t}\n\t\t\t\tif (thru_stars)\n\t\t\t\t    goto bombout;\n\t\t\t\ttorps = TRUE;\n\t\t\t\tbreak;\n\t\t\t    case 'o': case 'O': case '0':\n\t\t\t\tif (attackee == nuke) {\n\t\t\t\t    if (rand_mod(2+scandist-prob) <\n\t\t\t\t      rand_mod(smarts/20+1))\n\t\t\t\t\tTract(nuke,dy,dx,rand_mod(3)?1:-1);\n\t\t\t\t}\n\t\t\t\tif (thru_stars)\n\t\t\t\t    goto bombout;\n\t\t\t\ttorps = TRUE;\n\t\t\t\tif (rand_mod(99+3*scandist) < smarts+3*prob) {\n\t\t\t\t    obj->vely = -dy + attackee->vely;\n\t\t\t\t    obj->velx = -dx + attackee->velx;\n\t\t\t\t    if (obj->flags & STATIC) {/* not a mover? */\n\t\t\t\t\tobj->flags &= ~STATIC;\n\t\t\t\t\tobj->prev->next = obj->next;\n\t\t\t\t\tobj->next->prev = obj->prev;\n\t\t\t\t\troot.prev->next = obj;\n\t\t\t\t\tobj->prev = root.prev;\n\t\t\t\t\troot.prev = obj;\n\t\t\t\t\tobj->next = &root;\n\t\t\t\t    }\n\t\t\t\t}\n\t\t\t\tif (obj->image != '0')\n\t\t\t\t    break;\n\t\t\t    /* DROP THROUGH! */\n\t\t\t    case 'X':\n\t\t\t\tif (attackee == nuke) {\n\t\t\t\t    if (rand_mod(2+scandist-prob) <\n\t\t\t\t      rand_mod(smarts/20+1))\n\t\t\t\t\tTract(nuke,dy,dx,rand_mod(3)?1:-1);\n\t\t\t\t}\n\t\t\t\ttorps = TRUE;\n\t\t\t\tif (thru_stars)\n\t\t\t\t    goto bombout;\n\t\t\t\tif (prob == scandist) {\n\t\t\t\t    int y, x;\n\n\t\t\t\t    blast[y=(obj->posy+obj->vely+YSIZE00)%YSIZE]\n\t\t\t\t\t [x=(obj->posx+obj->velx+XSIZE00)%XSIZE]\n\t\t\t\t      += (obj->image == '0' ? 2000 : 200);\n\t\t\t\t    yblasted[y] |= 1;\n\t\t\t\t    xblasted[x] |= 1;\n\t\t\t\t    blasted = TRUE;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t    case 'A':\n\t\t\t\tif (attackee != nuke) {\n\t\t\t\t    if (scandist-prob>1 && !rand_mod(51-super))\n\t\t\t\t\tTract(obj,-dy,-dx,1);\n\t\t\t\t}\n\t\t\t\t/* FALL THROUGH */\n\t\t\t    case '*': case '@':\n\t\t\t\tif (attackee == nuke) {\n\t\t\t\t    if (amb[cury][curx] != '~') {\n\t\t\t\t\tif (scandist-prob < nukedist) {\n\t\t\t\t\t    nukedist = scandist-prob;\n\t\t\t\t\t    nukey = dy;\t/* nearest food in */\n\t\t\t\t\t    nukex = dx;\t/*   this direction */\n\t\t\t\t\t}\n\t\t\t\t\tif (smarts > 55 && scandist-prob > 8) {\n\t\t\t\t\t    if (rand_mod(30+scandist-prob) <\n\t\t\t\t\t      rand_mod(smarts/20+1))\n\t\t\t\t\t\tTract(nuke,dy,dx,1);\n\t\t\t\t\t}\n\t\t\t\t    }\n\t\t\t\t    else if (obj->vely || obj->velx) {\n\t\t\t\t\tTract(nuke,dy,dx,1); /* for looks */\n\t\t\t\t\tobj->vely = obj->velx = 0;\n\t\t\t\t    }\n\t\t\t\t}\n\t\t\t\tif (!thru_stars)\n\t\t\t\t    if (rand_mod(97-sm95))\n\t\t\t\t\tgoto bombout;\n\t\t\t\t    else\n\t\t\t\t\tthru_stars = TRUE;\n\t\t\t\tbreak;\n\t\t\t    case '<': case '>':\n\t\t\t\tif (attackee == nuke) {\n\t\t\t\t    if ((!dy && scandist-prob < 8) ||\n\t\t\t\t      rand_mod(2+scandist-prob) <\n\t\t\t\t      rand_mod(smarts/20+1) ) {\n\t\t\t\t\tnuke->mass += 10000;\n\t\t\t\t\tTract(nuke,dy,dx,-1);\n\t\t\t\t\tnuke->mass -= 10000;\n\t\t\t\t    }\n\t\t\t\t}\n\t\t\t\tgoto bombout;\n\t\t\t    case 'E': case 'B':\n\t\t\t\tif (attackee == nuke) {\n\t\t\t\t    if (rand_mod(2+scandist-prob) <\n\t\t\t\t      rand_mod(smarts/40+1))\n\t\t\t\t\tTract(nuke,dy,dx,rand_mod(3)?1:-1);\n\t\t\t\t}\n\t\t\t\tgoto bombout;\n\t\t\t    default:\n\t\t\t\tgoto bombout;\n\t\t\t    }\n\t\t\t}\n\t\t\telse {\n\t\t\t    if (thru_stars)\n\t\t\t\tgoto bombout;\n\t\t\t}\n\t\t    }\nbombout:            ; /* end of loop */\n\t\t}\n\t    }\n\t}\n\tif (attackee == nuke && nukedist < 100) {/* aim amoeba at nearest */\n\t    if (nukey < 0)\t\t\t/*   free star */\n\t\tnukey = 2;\n\t    if (nukex < 0)\n\t\tnukex = 2;\n\t    nuke->strategy = nukey + (nukex << 2);\n\t}\n    }\n}\n\nvoid\nfire_phaser(obj, dy, dx)\nregister OBJECT *obj;\nregister int dy;\nregister int dx;\n{\n    register int y;\n    register int x;\n    register int skipping;\n    register int size=5000;\n    int decr = 50, oldy, oldx;\n    static char curchar[] = \"@* \";\n\n    if (obj == ent)\n\tdecr = 100;\n    else if (obj == base) {\n\tdecr = 1000;\n\tsize = 200;\n    }\n    if (!dy)\n\tcurchar[2] = '-';\n    else if (!dx)\n\tcurchar[2] = '!';\n    else if (dy == dx)\n\tcurchar[2] = '\\\\';\n    else\n\tcurchar[2] = '/';\n    if (obj->energy >= decr) {\n\tobj->energy -= decr;\n\tfor (\n\t  /* initialize */\n\t  skipping = (obj != base),\n\t  y = (obj->posy+(obj==base?dy*2:dy)+YSIZE00)%YSIZE,\n\t  x = (obj->posx+(obj==base?dx*2:dx)+XSIZE00)%XSIZE;\n\t  /* while */\n\t  size && (!occupant[y][x]||(skipping && occupant[y][x]->type==Star));\n\t  /* at end of loop */\n\t  y = (y+dy+YSIZE00) % YSIZE,\n\t  x = (x+dx+XSIZE00) % XSIZE,\n\t  size = size * 3 / 4 ) {\n\t    move(y+1,x*2,0);\n\t    beg_qwrite();\n\t    if (obj == base || obj->image == 'T') {\n\t\t*filler = '@';\n\t\tqwrite();\n\t\t*filler = '#';\n\t\tqwrite();\n\t\t*filler = '~';\n\t\tqwrite();\n\t\t*filler = '%';\n\t\tqwrite();\n\t\t*filler = ':';\n\t\tqwrite();\n\t\t*filler = '@';\n\t    }\n\t    else {\n\t\t*filler = size >= 500 ?\n\t\t\t  *curchar : (size >= 50 ?\n\t\t\t\t     curchar[1] :\n\t\t\t\t     curchar[2]);\n\t    }\n\t    qwrite();\n\t    if (occupant[y][x])\n\t\tqaddc(occupant[y][x]->image);\n\t    else {\n\t\tif (numamoebas)\n\t\t    qaddc(amb[y][x]);\n\t\telse\n\t\t    qaddspace();\n\t\tif (skipping)\n\t\t    skipping = 0;\n\t    }\n\t    end_qwrite();\n\t}\n\tif (size) {\n\t    char img;\n\n\t    assert(occupant[y][x]);\n\t    img = occupant[y][x]->image;\n\t    if (occupant[y][x]->type == Crusher) {\n\t\tif (dy)\n\t\t    return;\n\t        if (dx==(img == '<' ? 1 : -1) ) {\n\t\t    occupant[y][x]->image =\n\t\t\t(occupant[y][x]->velx *= -1) < 0 ? '>' : '<';\n\t\t    return;\n\t\t}\n\t    }\n\t    else if (occupant[y][x]->flags & FRIENDLY)\n\t\tmadfriends += 200;\n\t    if (numamoebas && amb[y][x] == '~' && smarts % 3 &&\n\t\t(smarts > 70 || rand_mod(smarts) > rand_mod(20)) ) {\n\t\tif (size > 10000)\n\t\t    modify_amoeba(y,x,1,'~',10);\n\t\telse if (size > 1000)\n\t\t    modify_amoeba(y,x,1,'~',7);\n\t\telse if (size > 50)\n\t\t    modify_amoeba(y,x,1,'~',5);\n\t\telse\n\t\t    modify_amoeba(y,x,1,'~',2);\n\t\tif (occupant[y][x] == nuke) {\n\t\t    nuke->strategy = rand_mod(30);\n\t\t    nuke->flags |= COUNTDOWN;\n\t\t}\n\t\treturn;\n\t    }\n\t    else {\n\t\tmove(y+1,x*2,0);\n\t\tbeg_qwrite();\n\t\tif (img == ' ') {\n\t\t    *filler = occupant[y][x]->flags & PIRATE ? 'P' : 'R';\n\t\t    occupant[y][x]->image = *filler;\n\t\t    occupant[y][x]->strategy = 0;\n\t\t    qwrite();\n\t\t    qwrite();\n\t\t}\n\t\telse if (img == 'C' || img == 'c') {\n\t\t    cloaked = 0;\n\t\t    img += 2;\n\t\t    occupant[y][x]->image = img;\n\t\t    *filler = img;\n\t\t    qwrite();\n\t\t    qwrite();\n\t\t}\n\t\telse if (img == 'K' && size > 50)\n\t\t    occupant[y][x]->strategy = 0;\n\t\t*filler = '@';\n\t\tqwrite();\n\t\t*filler = '#';\n\t\tqwrite();\n\t\t*filler = '@';\n\t\tqwrite();\n\t\t*filler = '#';\n\t\tqwrite();\n\t\t*filler = '@';\n\t\tqwrite();\n\t\tqaddc(img);\n\t\tend_qwrite();\n\t\toldy = y;\n\t\toldx = x;\n\t\ty = (occupant[oldy][oldx]->posy + occupant[oldy][oldx]->vely +\n\t\t\tYSIZE00) % YSIZE;\n\t\tx = (occupant[oldy][oldx]->posx + occupant[oldy][oldx]->velx +\n\t\t\tXSIZE00) % XSIZE;\n\t\tif (occupant[y][x] && occupant[y][x]->type == Star) {\n\t\t    y = occupant[oldy][oldx]->posy;\n\t\t    x = occupant[oldy][oldx]->posx;\n\t\t}\n\t\tif (obj==base)\n\t\t    blast[y][x] += size>50 ? 15000 : (size>15 ? 1500 : 150);\n\t\telse if (obj==ent)\n\t\t    blast[y][x] += size*4;\n\t\telse if (obj->image=='T')\n\t\t    blast[y][x] += 15000;\n\t\telse\n\t\t    blast[y][x] += size*smarts/25;\n\t\tyblasted[y] |= 1;\n\t\txblasted[x] |= 1;\n\t\tblasted = TRUE;\n\t    }\n\t}\n    }\n}\n\nint\ntract(obj, dy, dx, to_or_fro)\nregister OBJECT *obj;\nregister int dy;\nregister int dx;\nint to_or_fro;\n{\n    register int y;\n    register int x;\n    register int size=10;\n    static char ch;\n    register OBJECT *tractee;\n\n    if (!dy)\n\tch = '|';\n    else if (!dx)\n\tch = '-';\n    else if (dy == dx)\n\tch = '/';\n    else\n\tch = '\\\\';\n    {\n\tfor (\n\t  y = (obj->posy+dy+YSIZE00)%YSIZE,\n\t  x = (obj->posx+dx+XSIZE00)%XSIZE;\n\t  size && (!occupant[y][x]);\n\t  y = (y+dy+YSIZE00) % YSIZE, x = (x+dx+XSIZE00) % XSIZE, size--) {\n\t    move(y+1,x*2,0);\n\t    beg_qwrite();\n\t    *filler = ch;\n\t    qwrite();\n\t    qwrite();\n\t    if (numamoebas)\n\t\tqaddch(amb[y][x]);\n\t    else\n\t\tqaddspace();\n\t    end_qwrite();\n\t}\n\ttractee = occupant[y][x];\n\tif (size) {\n\t    assert(tractee);\n\t    if (numamoebas && obj != nuke && amb[y][x] == '~') {\n\t\tif (to_or_fro > 0)\n\t\t    modify_amoeba(y,x,2,'~',size);\n\t\telse\n\t\t    modify_amoeba(y,x,1,' ',size);\n\t    }\n\t    if (tractee->type != Web &&\n\t\t(tractee->mass < obj->mass * 5 ||\n\t\t (tractee->type == Crusher && !dx) ) ) {\n\t\tif (tractee == ent) {\n\t\t    evely -= dy * to_or_fro;\n\t\t    evelx -= dx * to_or_fro;\n\t\t}\n\t\telse if (tractee == base) {\n\t\t    bvely -= dy * to_or_fro;\n\t\t    bvelx -= dx * to_or_fro;\n\t\t}\n\t\telse {\n\t\t    tractee->vely -= dy * to_or_fro;\n\t\t    tractee->velx -= dx * to_or_fro;\n\t\t}\n\t\tif (tractee->type == Torp ||\n\t\t    tractee->type == Star) {\n\t\t    if (tractee->flags & STATIC) {  /* not a mover? */\n\t\t\ttractee->flags &= ~STATIC;\n\t\t\ttractee->prev->next = tractee->next;\n\t\t\ttractee->next->prev = tractee->prev;\n\t\t\troot.prev->next = tractee;\n\t\t\ttractee->prev = root.prev;\n\t\t\troot.prev = tractee;\n\t\t\ttractee->next = &root;\n\t\t    }\n\t\t}\n\t    }\n\t    else if (tractee->type == Crusher && !dy &&\n\t      dx==(tractee->image == '<' ? 1 : -1) ) {\n\t\tsetimage(tractee, (tractee->velx *= -1) < 0 ? '>' : '<');\n\t    }\n\t    if (tractee->mass * 5 > obj->mass)\n\t\treturn(1);\n\t}\n    }\n    return(0);\n}\n"
  },
  {
    "path": "games/warp/weapon.h",
    "content": "/* $Header: weapon.h,v 7.0 86/10/08 15:18:20 lwall Exp $ */\n\n/* $Log:\tweapon.h,v $\n * Revision 7.0  86/10/08  15:18:20  lwall\n * Split into separate files.  Added amoebas and pirates.\n * \n */\n\nEXT int tractor INIT(0);\n\nEXT int etorp;\nEXT int btorp;\n\nEXT OBJECT *isatorp[2][3][3];\n\nEXT int aretorps;\n\nvoid fire_torp();\nvoid attack();\nvoid fire_phaser();\nint tract();\nvoid weapon_init();\n"
  },
  {
    "path": "include/.gitignore",
    "content": "machine\n"
  },
  {
    "path": "include/Makefile",
    "content": "#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n#\t@(#)Makefile\t5.16.1 (2.11BSD GTE) 1997/9/22\n#\n# Doing a ``make includes'' builds ${DESTDIR}/usr/include\n#\n# Define SHARED to indicate whether you want\n# symbolic links to the system source (``symlinks''),\n# or a separate copy (``copies'').\n# (latter useful in environments where it's\n# not possible to keep /sys publicly readable)\n#\n# The ``rm -rf''s used below are safe because rm doesn't\n# follow symbolic links.\n#\nTOPSRC!=cd ..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nSTD=\ta.out.h alloca.h ar.h assert.h \\\n\tctype.h curses.h \\\n\tfcntl.h float.h fstab.h \\\n\tgrp.h kmem.h lastlog.h libgen.h limits.h \\\n\tmath.h mtab.h ndbm.h nlist.h \\\n\tpaths.h psout.h pwd.h \\\n\tranlib.h regexp.h \\\n\tsetjmp.h sgtty.h \\\n\tstdarg.h stdbool.h stddef.h stdint.h stdio.h stdlib.h \\\n\tstring.h strings.h struct.h syscall.h sysexits.h \\\n\tterm.h time.h ttyent.h tzfile.h \\\n\tunistd.h utmp.h vmf.h\n\nLINKS=\terrno.h signal.h stdint.h syslog.h\n\nSUBDIRS=arpa\n\n# XXX This is temporary\nSUBDIRS+=smallc smallc/sys\n\nMACHDEP=${MACHINE}\nNETDIRS=netinet\nSYSDIRS=${NETDIRS} ${MACHDEP}\n\n#SHARED=\tsymlinks\nSHARED=\tcopies\nTAGSFILE=tags\n\nall:\n\nincludes: ${SHARED}\n\t-for i in ${STD}; do \\\n\t\tcmp -s $$i ${DESTDIR}/usr/include/$$i || \\\n\t\t    ${INSTALL} -c -m 444 $$i ${DESTDIR}/usr/include/$$i; \\\n\tdone\n\t-for i in ${SUBDIRS}; do \\\n\t\tif [ ! -d ${DESTDIR}/usr/include/$$i ]; \\\n\t\tthen \\\n\t\t\tmkdir ${DESTDIR}/usr/include/$$i; \\\n\t\tfi; \\\n\t\t(cd $$i; for j in *.[ih]; do \\\n\t\t\tcmp -s $$j ${DESTDIR}/usr/include/$$i/$$j || \\\n\t\t\t${INSTALL} -c -m 444 $$j ${DESTDIR}/usr/include/$$i/$$j; \\\n\t\tdone); \\\n\tdone\n# XXX\t-cmp -s Makefile.install ${DESTDIR}/usr/include/Makefile || \\\n# XXX\t    ${INSTALL} -c -m 444 Makefile.install ${DESTDIR}/usr/include/Makefile\n\t-for i in ${LINKS}; do \\\n\t\trm -f ${DESTDIR}/usr/include/$$i; \\\n\t\tln -s sys/$$i ${DESTDIR}/usr/include/$$i; \\\n\tdone\n\trm -f ${DESTDIR}/usr/include/machine\n\tln -s ${MACHINE} ${DESTDIR}/usr/include/machine\n# XXX\trm -f ${DESTDIR}/usr/include/frame.h\n# XXX\tln -s machine/frame.h ${DESTDIR}/usr/include/frame.h\n\n# XXX symlinks:\n# XXX \t-for i in ${SYSDIRS}; do \\\n# XXX \t\trm -rf ${DESTDIR}/usr/include/$$i; \\\n# XXX \t\tif [ ! -s ${DESTDIR}/usr/include/$$i ]; \\\n# XXX \t\tthen \\\n# XXX \t\t\tln -s ../../sys/$$i ${DESTDIR}/usr/include/$$i; \\\n# XXX \t\telse \\\n# XXX \t\t\techo ${DESTDIR}/usr/include/$$i not removed; \\\n# XXX \t\tfi; \\\n# XXX \tdone\n# XXX \trm -rf ${DESTDIR}/usr/include/sys\n# XXX \t-if [ ! -s ${DESTDIR}/usr/include/sys ]; \\\n# XXX \tthen \\\n# XXX \t\tln -s ../../sys/h ${DESTDIR}/usr/include/sys; \\\n# XXX \telse \\\n# XXX \t\techo ${DESTDIR}/usr/include/sys not removed; \\\n# XXX \tfi\n\ncopies:\n\tif [ -z \"${DESTDIR}\" ] || [ \"${DESTDIR}\" = \"/\" ]; \\\n\tthen \\\n\t\techo \"DESTDIR must be set and must not be /\"; \\\n\t\texit 1; \\\n\tfi; \\\n\tif [ -z \"${DESTDIR}\" ] || [ \"${DESTDIR}\" = \"${TOPSRC}\" ]; \\\n\tthen \\\n\t\techo \"DESTDIR is same as TOPSRC: skip copying SYSDIRS\"; \\\n\telse \\\n\t\tif [ ! -d ${DESTDIR}/usr/include ]; \\\n\t\tthen \\\n\t\t\tmkdir ${DESTDIR}/usr/include; \\\n\t\tfi; \\\n\t\tfor i in ${SYSDIRS}; do \\\n\t\t\trm -rf ${DESTDIR}/usr/include/$$i; \\\n\t\t\ttar cf - $$i/*.h | \\\n\t\t\t    (cd ${DESTDIR}/usr/include; tar xpf -); \\\n\t\tdone; \\\n\t\trm -rf ${DESTDIR}/usr/include/sys; \\\n\t\tmkdir ${DESTDIR}/usr/include/sys; \\\n\t\tchmod 775 ${DESTDIR}/usr/include/sys; \\\n\t\t(cd ../sys/sys; tar cf - *.h | \\\n\t\t    (cd ${DESTDIR}/usr/include/sys; tar xpf -)); \\\n\tfi\n\n# XXX tags:\n# XXX \tcwd=${TOPSRC}/include; \\\n# XXX \tfor i in ${STD} ${LINKS}; do \\\n# XXX \t\tctags -a -f ${TAGSFILE} $$cwd/$$i; \\\n# XXX \tdone\n\nclean:\n\trm -f tags\n"
  },
  {
    "path": "include/Makefile.install",
    "content": "#\n# Copyright (c) 1983,1986 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n#\t@(#)Makefile.install\t5.3 (Berkeley) 10/13/86\n#\n# Makefile for /usr/include, used to convert system include subdirectories\n# between symbolic links and copies of kernel headers.\n# May also be used to update copies from kernel header files.\n#\n# The ``rm -rf''s used below are safe because rm doesn't\n# follow symbolic links.\n#\nDESTDIR=\n#ifdef vax\n#MACHINE=vax\n#MACHDEP=${MACHINE} vaxif vaxmba vaxuba\n#endif\nMACHINE=pdp\nMACHDEP=${MACHINE} pdpmba pdpuba stand vaxif vaxuba\nNETDIRS=net netimp netinet netns netpup\nSYSDIRS=${NETDIRS} ${MACHDEP}\nSYS=/sys\n\nall:\n\t@echo \"\\\"make symlinks\\\", \\\"make copies\\\", or \\\"make update\\\" only\"\n\t@false\n\nsymlinks:\n\tfor i in ${SYSDIRS}; do \\\n\t\trm -rf $$i; \\\n\t\tln -s ../../${SYS}/$$i $$i; \\\n\tdone\n\trm -rf sys\n\tln -s ../../${SYS}/h sys\n\ncopies:\n\t-for i in ${SYSDIRS}; do \\\n\t\trm -rf $$i; \\\n\t\t(cd ${SYS}; tar cf - $$i/*.h) | tar xpfB -; \\\n\tdone\n\trm -rf sys;\n\tmkdir sys; \n\tchmod 775 sys;\n\t-(cd ${SYS}/h; tar cf - *.h) | (cd sys; tar xpfB -)\n\nupdate:\n\t-for i in ${SYSDIRS}; do \\\n\t\tif [ ! -d $$i ]; \\\n\t\tthen \\\n\t\t\tmkdir $$i; \\\n\t\tfi; \\\n\t\tfor j in `cd ${SYS}/$$i; echo *.[ih]`; do \\\n\t\t\tcmp -s ${SYS}/$$i/$$j $$i/$$j || \\\n\t\t\tinstall -c -m 444 ${SYS}/$$i/$$j $$i/$$j; \\\n\t\tdone; \\\n\tdone\n\tfor j in `cd ${SYS}/h; echo *.[ih]`; do \\\n\t\tcmp -s ${SYS}/h/$$j sys/$$j || \\\n\t\t{ echo \"install -c -m 444 ${SYS}/h/$$j sys/$$j\"; \\\n\t\tinstall -c -m 444 ${SYS}/h/$$j sys/$$j; } \\\n\tdone;\n"
  },
  {
    "path": "include/a.out.h",
    "content": "/*-\n * Copyright (c) 1991 The Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *      This product includes software developed by the University of\n *      California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#ifndef _AOUT_H_\n#define _AOUT_H_\n\n#include <sys/exec_aout.h>\n\n#define _AOUT_INCLUDE_\n#include <nlist.h>\n\n/* Relocations */\nstruct reloc {\n    unsigned flags;\n#define RSMASK  0x70            /* bitmask for segments */\n#define RABS        0\n#define RTEXT       0x20\n#define RDATA       0x30\n#define RBSS        0x40\n#define RSTRNG      0x60        /* for assembler */\n#define REXT        0x70        /* externals and bitmask */\n\n#define RGPREL  0x08            /* gp relative */\n\n#define RFMASK  0x07            /* bitmask for format */\n#define RBYTE16     0x00        /* low part of byte address: bits 15:0 */\n#define RBYTE32     0x01        /* 32-bit byte address */\n#define RHIGH16     0x02        /* upper part of byte address: bits 31:16 */\n#define RHIGH16S    0x03        /* upper part of address with signed offset */\n#define RWORD16     0x04        /* word address: bits 17:2 */\n#define RWORD26     0x05        /* word address: bits 27:2 */\n\n    unsigned index;             /* 24-bit index in symbol table,\n                                 * for REXT */\n    unsigned offset;            /* 16-bit offset,\n                                 * for RIGH16 and RIGH16S */\n};\n\n#endif /* !_AOUT_H_ */\n"
  },
  {
    "path": "include/alloca.h",
    "content": "/* alloca.h - Allocate memory on stack */\n\n#ifndef ALLOCA_H\n#define ALLOCA_H\n\n#undef alloca\n\n#ifdef __GNUC__\n#define alloca(size) __builtin_alloca(size)\n#else\n#include <sys/types.h>\nvoid *alloca(size_t);\n#endif\n\n#endif\n"
  },
  {
    "path": "include/ar.h",
    "content": "/*-\n * Copyright (c) 1991 The Regents of the University of California.\n * All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Hugh Smith at The University of Guelph.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *  This product includes software developed by the University of\n *  California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n#ifndef _AR_H_\n#define _AR_H_\n\n#define ARMAG       \"!<arch>\\n\" /* ar \"magic number\" */\n#define SARMAG      8           /* strlen(ARMAG); */\n\n#define AR_EFMT1    \"#1/\"       /* extended format #1 */\n\nstruct ar_hdr {\n    char ar_name[16];           /* name */\n    char ar_date[12];           /* modification time */\n    char ar_uid[6];             /* user id */\n    char ar_gid[6];             /* group id */\n    char ar_mode[8];            /* octal file permissions */\n    char ar_size[10];           /* size in bytes */\n#define ARFMAG      \"`\\n\"\n    char ar_fmag[2];            /* consistency check */\n};\n\n#define ARHDRSZ     60\n\n#endif /* !_AR_H_ */\n"
  },
  {
    "path": "include/arpa/inet.h",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that the above copyright notice and this paragraph are\n * duplicated in all such forms and that any documentation,\n * advertising materials, and other materials related to such\n * distribution and use acknowledge that the software was developed\n * by the University of California, Berkeley.  The name of the\n * University may not be used to endorse or promote products derived\n * from this software without specific prior written permission.\n * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n */\n\n/*\n * External definitions for\n * functions in inet(3N)\n */\nstruct  in_addr;\n\nunsigned long inet_addr (char *);\nchar    *inet_ntoa (struct in_addr);\nstruct  in_addr inet_makeaddr (long, long);\nunsigned long inet_network (char *);\nunsigned long inet_netof (struct in_addr);\nunsigned long inet_lnaof (struct in_addr);\n\n/*\n * Macros for number representation conversion.\n */\nunsigned htonl (unsigned hostlong);\nunsigned htons (unsigned hostshort);\nunsigned ntohl (unsigned netlong);\nunsigned ntohs (unsigned netshort);\n"
  },
  {
    "path": "include/assert.h",
    "content": "# ifndef NDEBUG\n# define _assert(ex)    {if (!(ex)){fprintf(stderr,\"Assertion failed: file \\\"%s\\\", line %d\\n\", __FILE__, __LINE__);exit(1);}}\n# define assert(ex)     _assert(ex)\n# else\n# define _assert(ex)\n# define assert(ex)\n# endif\n"
  },
  {
    "path": "include/ctype.h",
    "content": "#define _U      01\n#define _L      02\n#define _N      04\n#define _S      010\n#define _P      020\n#define _C      040\n#define _X      0100\n#define _B      0200\n\nextern char _ctype_[];\n\n#define isalpha(c)      ((_ctype_+1)[(int)(c)]&(_U|_L))\n#define isupper(c)      ((_ctype_+1)[(int)(c)]&_U)\n#define islower(c)      ((_ctype_+1)[(int)(c)]&_L)\n#define isdigit(c)      ((_ctype_+1)[(int)(c)]&_N)\n#define isxdigit(c)     ((_ctype_+1)[(int)(c)]&(_N|_X))\n#define isspace(c)      ((_ctype_+1)[(int)(c)]&_S)\n#define ispunct(c)      ((_ctype_+1)[(int)(c)]&_P)\n#define isalnum(c)      ((_ctype_+1)[(int)(c)]&(_U|_L|_N))\n#define isprint(c)      ((_ctype_+1)[(int)(c)]&(_P|_U|_L|_N|_B))\n#define isgraph(c)      ((_ctype_+1)[(int)(c)]&(_P|_U|_L|_N))\n#define iscntrl(c)      ((_ctype_+1)[(int)(c)]&_C)\n#define isascii(c)      ((unsigned)(c)<=0177)\n#define toupper(c)      ((c)-'a'+'A')\n#define tolower(c)      ((c)-'A'+'a')\n#define toascii(c)      ((c)&0177)\n"
  },
  {
    "path": "include/curses.h",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#ifndef CURSES_H\n\n#include <stdio.h>\n#include <sgtty.h>\n#include <term.h>\n\n#define bool        int\n\n#define TRUE        (1)\n#define FALSE       (0)\n#define ERR         (0)\n#define OK          (1)\n\n#define _ENDLINE    001\n#define _FULLWIN    002\n#define _SCROLLWIN  004\n#define _FLUSH      010\n#define _FULLLINE   020\n#define _IDLINE     040\n#define _STANDOUT   0200\n#define _NOCHANGE   -1\n\n#define _puts(s)    tputs(s, 0, _putchar)\n\ntypedef struct sgttyb SGTTY;\n\n/*\n * Capabilities from termcap\n */\nextern bool AM, BS, CA, DA, DB, EO, HC, HZ, IN, MI, MS, NC, NS, OS, UL,\n            XB, XN, XT, XS, XX;\nextern char *AL, *BC, *BT, *CD, *CE, *CL, *CM, *CR, *CS, *DC, *DL,\n            *DM, *DO, *ED, *EI, *K0, *K1, *K2, *K3, *K4, *K5, *K6,\n            *K7, *K8, *K9, *HO, *IC, *IM, *IP, *KD, *KE, *KH, *KL,\n            *KR, *KS, *KU, *LL, *MA, *ND, *NL, *RC, *SC, *SE, *SF,\n            *SO, *SR, *TA, *TE, *TI, *UC, *UE, *UP, *US, *VB, *VS,\n            *VE, *AL_PARM, *DL_PARM, *UP_PARM, *DOWN_PARM,\n            *LEFT_PARM, *RIGHT_PARM;\nextern char PC;\n\n/*\n * From the tty modes...\n */\n\nextern bool GT, NONL, UPPERCASE, normtty, _pfast;\n\nstruct _win_st {\n    short       _cury, _curx;\n    short       _maxy, _maxx;\n    short       _begy, _begx;\n    short       _flags;\n    short       _ch_off;\n    bool        _clear;\n    bool        _leave;\n    bool        _scroll;\n    char        **_y;\n    short       *_firstch;\n    short       *_lastch;\n    struct _win_st *_nextp, *_orig;\n};\n\n#define WINDOW      struct _win_st\n\nextern bool     My_term, _echoit, _rawmode, _endwin;\n\nextern char     *Def_term, ttytype[];\n\nextern int      LINES, COLS, _tty_ch, _res_flg;\n\nextern SGTTY    _tty;\n\nextern WINDOW   *stdscr, *curscr;\n\n/*\n *  Define VOID to stop lint from generating \"null effect\"\n * comments.\n */\n#ifdef lint\nint __void__;\n#define VOID(x)     (__void__ = (int) (x))\n#else\n#define VOID(x)     (x)\n#endif\n\n/*\n * psuedo functions for standard screen\n */\n#define addch(ch)   VOID(waddch(stdscr, ch))\n#define getch()     VOID(wgetch(stdscr))\n#define addstr(str) VOID(waddstr(stdscr, str))\n#define getstr(str) VOID(wgetstr(stdscr, str))\n#define move(y, x)  VOID(wmove(stdscr, y, x))\n#define clear()     VOID(wclear(stdscr))\n#define erase()     VOID(werase(stdscr))\n#define clrtobot()  VOID(wclrtobot(stdscr))\n#define clrtoeol()  VOID(wclrtoeol(stdscr))\n#define insertln()  VOID(winsertln(stdscr))\n#define deleteln()  VOID(wdeleteln(stdscr))\n#define refresh()   VOID(wrefresh(stdscr))\n#define inch()      VOID(winch(stdscr))\n#define insch(c)    VOID(winsch(stdscr,c))\n#define delch()     VOID(wdelch(stdscr))\n#define standout()  VOID(wstandout(stdscr))\n#define standend()  VOID(wstandend(stdscr))\n\n/*\n * mv functions\n */\n#define mvwaddch(win,y,x,ch)    VOID(wmove(win,y,x)==ERR?ERR:waddch(win,ch))\n#define mvwgetch(win,y,x)       VOID(wmove(win,y,x)==ERR?ERR:wgetch(win))\n#define mvwaddstr(win,y,x,str)  VOID(wmove(win,y,x)==ERR?ERR:waddstr(win,str))\n#define mvwgetstr(win,y,x,str)  VOID(wmove(win,y,x)==ERR?ERR:wgetstr(win,str))\n#define mvwinch(win,y,x)        VOID(wmove(win,y,x) == ERR ? ERR : winch(win))\n#define mvwdelch(win,y,x)       VOID(wmove(win,y,x) == ERR ? ERR : wdelch(win))\n#define mvwinsch(win,y,x,c)     VOID(wmove(win,y,x) == ERR ? ERR:winsch(win,c))\n#define mvaddch(y,x,ch)         mvwaddch(stdscr,y,x,ch)\n#define mvgetch(y,x)            mvwgetch(stdscr,y,x)\n#define mvaddstr(y,x,str)       mvwaddstr(stdscr,y,x,str)\n#define mvgetstr(y,x,str)       mvwgetstr(stdscr,y,x,str)\n#define mvinch(y,x)             mvwinch(stdscr,y,x)\n#define mvdelch(y,x)            mvwdelch(stdscr,y,x)\n#define mvinsch(y,x,c)          mvwinsch(stdscr,y,x,c)\n\n/*\n * psuedo functions\n */\n#define clearok(win,bf)  (win->_clear = bf)\n#define leaveok(win,bf)  (win->_leave = bf)\n#define scrollok(win,bf) (win->_scroll = bf)\n#define flushok(win,bf)  (bf ? (win->_flags |= _FLUSH):(win->_flags &= ~_FLUSH))\n#define getyx(win,y,x)   y = win->_cury, x = win->_curx\n#define winch(win)      (win->_y[win->_cury][win->_curx] & 0177)\n\n#define raw()       (_tty.sg_flags|=RAW, _pfast=_rawmode=TRUE, ioctl(_tty_ch,TIOCSETP,&_tty))\n#define noraw()     (_tty.sg_flags&=~RAW,_rawmode=FALSE,_pfast=!(_tty.sg_flags&CRMOD),ioctl(_tty_ch,TIOCSETP,&_tty))\n#define cbreak()    (_tty.sg_flags |= CBREAK, _rawmode = TRUE, ioctl(_tty_ch,TIOCSETP,&_tty))\n#define nocbreak()  (_tty.sg_flags &= ~CBREAK,_rawmode=FALSE,ioctl(_tty_ch,TIOCSETP,&_tty))\n#define crmode()    cbreak()   /* backwards compatability */\n#define nocrmode()  nocbreak()   /* backwards compatability */\n#define echo()      (_tty.sg_flags |= ECHO,  _echoit = TRUE,    ioctl(_tty_ch, TIOCSETP, &_tty))\n#define noecho()    (_tty.sg_flags &= ~ECHO, _echoit = FALSE,   ioctl(_tty_ch, TIOCSETP, &_tty))\n#define nl()        (_tty.sg_flags |= CRMOD, _pfast  = _rawmode,ioctl(_tty_ch, TIOCSETP, &_tty))\n#define nonl()      (_tty.sg_flags &= ~CRMOD,_pfast  = TRUE,    ioctl(_tty_ch, TIOCSETP,&_tty))\n#define savetty()   ((void) ioctl(_tty_ch, TIOCGETP, &_tty), _res_flg = _tty.sg_flags)\n#define resetty()   (_tty.sg_flags = _res_flg, (void) ioctl(_tty_ch, TIOCSETP, &_tty))\n\n#define erasechar() (_tty.sg_erase)\n#define killchar()  (_tty.sg_kill)\n#define baudrate()  (_tty.sg_ospeed)\n\nWINDOW  *initscr(), *newwin(), *subwin();\nchar    *longname(), *getcap();\n\nint     wmove (WINDOW *, int, int);\nint     wrefresh (WINDOW *);\nint     wclear (WINDOW *);\nint     waddch (WINDOW *, char);\nint     wgetch (WINDOW *);\nchar    *wstandout (WINDOW *);\nchar    *wstandend (WINDOW *);\nint     touchwin (WINDOW *);\nint     touchline (WINDOW *, int, int, int);\nvoid    box (WINDOW *, char, char);\nvoid    endwin (void);\nint     printw (char *, ...);\nint     wprintw (WINDOW *, char *, ...);\nint     scroll (WINDOW *);\nvoid    wclrtoeol (WINDOW *);\nvoid    werase (WINDOW *);\nint     setterm (char *);\nint     delwin (WINDOW *);\nint     waddstr (WINDOW *, char *);\nint     wgetstr (WINDOW *, char *);\nint     wdeleteln (WINDOW *);\nvoid    mvcur(int ly, int lx, int y, int x);\nvoid    overwrite(WINDOW *win1, WINDOW *win2);\nvoid    wclrtobot(WINDOW *win);\nint     mvprintw(int y, int x, char *fmt, ...);\nint     mvwprintw(WINDOW *win, int y, int x, char *fmt, ...);\n\n/*\n * Used to be in unctrl.h.\n */\n#define unctrl(c)   _unctrl[(c) & 0177]\nextern char *_unctrl[];\n\n#endif\n"
  },
  {
    "path": "include/fcntl.h",
    "content": "/*-\n * Copyright (c) 1983, 1990, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n * (c) UNIX System Laboratories, Inc.\n * All or some portions of this file are derived from material licensed\n * to the University of California by American Telephone and Telegraph\n * Co. or Unix System Laboratories, Inc. and are reproduced herein with\n * the permission of UNIX System Laboratories, Inc.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n *\t@(#)fcntl.h\t8.3.1 (2.11BSD GTE) 11/25/94\n *\n * Copied from 4.4-Lite and modified for 2.11BSD.  The modifications consisted\n * of removing: function prototypes (I don't like them, the compiler does not\n * support them, and it would mean dragging in cdefs.h to leave them in here),\n * #ifndef _POSIX_SOURCE lines (silly) and record locking related definitions\n * If anyone adds any of the above it will be easy enough to modify this file.\n * In the meantime why bog down (or blow up) cpp any further?\n */\n#include <sys/fcntl.h>\n\nint open (const char *path, int oflag, ...);\nint creat (const char *path, mode_t mode);\nint fcntl (int fildes, int cmd, ...);\n"
  },
  {
    "path": "include/float.h",
    "content": "#ifndef _FLOAT_H_\n#define _FLOAT_H_\n\n#include <machine/_float.h>\n\n#endif /* _FLOAT_H_ */\n"
  },
  {
    "path": "include/fstab.h",
    "content": "/*\n * Copyright (c) 1980, 1993\n *  The Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *  This product includes software developed by the University of\n *  California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n *  @(#)fstab.h 8.1.1 (2.11BSD) 1996/1/15\n */\n\n#ifndef _FSTAB_H_\n#define _FSTAB_H_\n\n/*\n * File system table, see fstab(5).\n *\n * Used by dump, mount, umount, swapon, fsck, df, ...\n *\n * For ufs fs_spec field is the block special name.  Programs that want to\n * use the character special name must create that name by prepending a 'r'\n * after the right most slash.  Quota files are always named \"quotas\", so\n * if type is \"rq\", then use concatenation of fs_file and \"quotas\" to locate\n * quota file.\n */\n#define FSTAB_RW    \"rw\"    /* read/write device */\n#define FSTAB_RQ    \"rq\"    /* read/write with quotas */\n#define FSTAB_RO    \"ro\"    /* read-only device */\n#define FSTAB_SW    \"sw\"    /* swap device */\n#define FSTAB_XX    \"xx\"    /* ignore totally */\n\nstruct fstab {\n    char    *fs_spec;       /* block special device name */\n    char    *fs_file;       /* file system path prefix */\n    char    *fs_vfstype;    /* File system type, ufs, nfs */\n    char    *fs_mntops;     /* Mount options ala -o */\n    char    *fs_type;       /* FSTAB_* from fs_mntops */\n    int     fs_freq;        /* dump frequency, in days */\n    int     fs_passno;      /* pass number on parallel dump */\n};\n\nstruct fstab *getfsent();\nstruct fstab *getfsspec();\nstruct fstab *getfsfile();\nint setfsent();\nvoid endfsent();\n\n#endif /* !_FSTAB_H_ */\n"
  },
  {
    "path": "include/grp.h",
    "content": "/*  grp.h   4.1 83/05/03    */\n\nstruct  group {         /* see getgrent(3) */\n    char    *gr_name;\n    char    *gr_passwd;\n    int     gr_gid;\n    char    **gr_mem;\n};\n\nstruct group *getgrent(void);\nstruct group *getgrnam(const char *name);\nstruct group *getgrgid(gid_t gid);\nvoid setgrent(void);\nvoid endgrent(void);\nint setgroups(size_t size, const gid_t *list);\n"
  },
  {
    "path": "include/kmem.h",
    "content": "#ifndef _KMEM_H\n#define _KMEM_H\n\nextern dev_t kmemdev();\n\n#endif\n"
  },
  {
    "path": "include/lastlog.h",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *  @(#)lastlog.h   5.1 (Berkeley) 5/30/85\n */\n\nstruct lastlog {\n    time_t  ll_time;\n    char    ll_line[8];\n    char    ll_host[16];        /* same as in utmp */\n};\n"
  },
  {
    "path": "include/libgen.h",
    "content": "/*\t$OpenBSD: libgen.h,v 1.10 2020/10/20 19:30:14 naddy Exp $\t*/\n\n/*\n * Copyright (c) 1997 Todd C. Miller <millert@openbsd.org>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#ifndef _LIBGEN_H_\n#define _LIBGEN_H_\n\nchar\t*basename(char *);\nchar\t*dirname(char *);\n\n#endif /* _LIBGEN_H_ */\n"
  },
  {
    "path": "include/limits.h",
    "content": "/*\n * Copyright (c) 1988, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n *\t@(#)limits.h\t8.2.1 (2.11BSD) 1996/1/11\n */\n\n#ifndef _LIMITS_H_\n#define\t_LIMITS_H_\n\n#include <machine/limits.h>\n\n#include <sys/syslimits.h>\n\n#endif /* !_LIMITS_H_ */\n"
  },
  {
    "path": "include/math.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\ndouble  fabs(double), floor(double), ceil(double);\ndouble  sqrt(double), hypot(double, double);\ndouble  sin(double), cos(double), tan(double);\ndouble  asin(double), acos(double), atan(double), atan2(double, double);\ndouble  exp(double), log(double), log10(double), pow(double, double);\ndouble  sinh(double), cosh(double), tanh(double);\ndouble  j0(double), j1(double), jn(int, double);\ndouble  y0(double), y1(double), yn(int, double);\n\n#define HUGE_VAL    3.40282347e+38 /* TBD??? use infinity? */\n\nint isnanf(float x);\nint isnan(double x);\n\nint isinff(float x);\nint isinf(double x);\n\nfloat modff(float x, float *iptr);\ndouble modf(double x, double *iptr);\n\nfloat frexpf(float x, int *exp);\ndouble frexp(double x, int *exp);\n\nfloat ldexpf(float x, int exp);\ndouble ldexp(double x, int exp);\n\ndouble fmod(double x, double y);\n\n#if !defined(_ANSI_SOURCE) && !defined(_POSIX_SOURCE)\n\n#define M_E             2.7182818284590452354   /* e */\n#define M_LOG2E         1.4426950408889634074   /* log 2e */\n#define M_LOG10E        0.43429448190325182765  /* log 10e */\n#define M_LN2           0.69314718055994530942  /* log e2 */\n#define M_LN10          2.30258509299404568402  /* log e10 */\n#define M_PI            3.14159265358979323846  /* pi */\n#define M_PI_2          1.57079632679489661923  /* pi/2 */\n#define M_PI_4          0.78539816339744830962  /* pi/4 */\n#define M_1_PI          0.31830988618379067154  /* 1/pi */\n#define M_2_PI          0.63661977236758134308  /* 2/pi */\n#define M_2_SQRTPI      1.12837916709551257390  /* 2/sqrt(pi) */\n#define M_SQRT2         1.41421356237309504880  /* sqrt(2) */\n#define M_SQRT1_2       0.70710678118654752440  /* 1/sqrt(2) */\n\n#endif /* !_ANSI_SOURCE && !_POSIX_SOURCE */\n"
  },
  {
    "path": "include/mtab.h",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *  @(#)mtab.h  5.1 (Berkeley) 5/30/85\n */\n\n/*\n * Mounted device accounting file.\n */\nstruct mtab {\n    char    m_path[32];     /* mounted on pathname */\n    char    m_dname[32];    /* block device pathname */\n    char    m_type[4];      /* read-only, quotas */\n};\n"
  },
  {
    "path": "include/ndbm.h",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *  @(#)ndbm.h  5.1.1 (2.11BSD GTE) 12/31/93\n */\n\n/*\n * Hashed key data base library.\n */\n#define PBLKSIZ             1024\n#define DBLKSIZ             1024\n\ntypedef struct {\n    int     dbm_dirf;               /* open directory file */\n    int     dbm_pagf;               /* open page file */\n    int     dbm_flags;              /* flags, see below */\n    long    dbm_maxbno;             /* last ``bit'' in dir file */\n    long    dbm_bitno;              /* current bit number */\n    long    dbm_hmask;              /* hash mask */\n    long    dbm_blkptr;             /* current block for dbm_nextkey */\n    int     dbm_keyptr;             /* current key for dbm_nextkey */\n    long    dbm_blkno;              /* current page to read/write */\n    long    dbm_pagbno;             /* current page in pagbuf */\n    char    dbm_pagbuf[PBLKSIZ];    /* page file block buffer */\n    long    dbm_dirbno;             /* current block in dirbuf */\n    char    dbm_dirbuf[DBLKSIZ];    /* directory file block buffer */\n} DBM;\n\n#define _DBM_RDONLY         0x1     /* data base open read-only */\n#define _DBM_IOERR          0x2     /* data base I/O error */\n\n#define dbm_rdonly(db)      ((db)->dbm_flags & _DBM_RDONLY)\n\n#define dbm_error(db)       ((db)->dbm_flags & _DBM_IOERR)\n    /* use this one at your own risk! */\n#define dbm_clearerr(db)    ((db)->dbm_flags &= ~_DBM_IOERR)\n\n/* for flock(2) and fstat(2) */\n#define dbm_dirfno(db)      ((db)->dbm_dirf)\n#define dbm_pagfno(db)      ((db)->dbm_pagf)\n\ntypedef struct {\n    char    *dptr;\n    int     dsize;\n} datum;\n\n/*\n * flags to dbm_store()\n */\n#define DBM_INSERT  0\n#define DBM_REPLACE 1\n\nDBM     *dbm_open();\nvoid    dbm_close();\ndatum   dbm_fetch();\ndatum   dbm_firstkey();\ndatum   dbm_nextkey();\nlong    dbm_forder();\nint     dbm_delete();\nint     dbm_store();\n"
  },
  {
    "path": "include/netinet/in.h",
    "content": "/*\n * Copyright (c) 1982, 1986 Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that this notice is preserved and that due credit is given\n * to the University of California at Berkeley. The name of the University\n * may not be used to endorse or promote products derived from this\n * software without specific prior written permission. This software\n * is provided ``as is'' without express or implied warranty.\n */\n\n/*\n * Constants and structures defined by the internet system,\n * Per RFC 790, September 1981.\n */\n\n/*\n * Protocols\n */\n#define IPPROTO_IP          0       /* dummy for IP */\n#define IPPROTO_ICMP        1       /* control message protocol */\n#define IPPROTO_GGP         3       /* gateway^2 (deprecated) */\n#define IPPROTO_TCP         6       /* tcp */\n#define IPPROTO_EGP         8       /* exterior gateway protocol */\n#define IPPROTO_PUP         12      /* pup */\n#define IPPROTO_UDP         17      /* user datagram protocol */\n#define IPPROTO_IDP         22      /* xns idp */\n\n#define IPPROTO_RAW         255     /* raw IP packet */\n#define IPPROTO_MAX         256\n\n\n/*\n * Ports < IPPORT_RESERVED are reserved for\n * privileged processes (e.g. root).\n * Ports > IPPORT_USERRESERVED are reserved\n * for servers, not necessarily privileged.\n */\n#define IPPORT_RESERVED     1024\n#define IPPORT_USERRESERVED 5000\n\n/*\n * Link numbers\n */\n#define IMPLINK_IP          155\n#define IMPLINK_LOWEXPER    156\n#define IMPLINK_HIGHEXPER   158\n\n/*\n * Internet address (a structure for historical reasons)\n */\nstruct in_addr {\n    u_long s_addr;\n};\n\n/*\n * Definitions of bits in internet address integers.\n * On subnets, the decomposition of addresses to host and net parts\n * is done according to subnet mask, not the masks here.\n */\n#define IN_CLASSA(i)        (((long)(i) & 0x80000000L) == 0)\n#define IN_CLASSA_NET       0xff000000L\n#define IN_CLASSA_NSHIFT    24\n#define IN_CLASSA_HOST      0x00ffffffL\n#define IN_CLASSA_MAX       128\n\n#define IN_CLASSB(i)        (((long)(i) & 0xc0000000L) == 0x80000000L)\n#define IN_CLASSB_NET       0xffff0000L\n#define IN_CLASSB_NSHIFT    16\n#define IN_CLASSB_HOST      0x0000ffffL\n#define IN_CLASSB_MAX       65536\n\n#define IN_CLASSC(i)        (((long)(i) & 0xe0000000L) == 0xc0000000L)\n#define IN_CLASSC_NET       0xffffff00L\n#define IN_CLASSC_NSHIFT    8\n#define IN_CLASSC_HOST      0x000000ffL\n\n#define IN_CLASSD(i)        (((long)(i) & 0xf0000000L) == 0xe0000000L)\n#define IN_MULTICAST(i)     IN_CLASSD(i)\n\n#define IN_EXPERIMENTAL(i)  (((long)(i) & 0xe0000000L) == 0xe0000000L)\n#define IN_BADCLASS(i)      (((long)(i) & 0xf0000000L) == 0xf0000000L)\n\n#define INADDR_ANY          0x00000000L\n#define INADDR_BROADCAST    0xffffffffL /* must be masked */\n#ifndef KERNEL\n#define INADDR_NONE         0xffffffffL /* -1 return */\n#endif\n\n#define IN_LOOPBACKNET      127     /* official! */\n\n/*\n * Socket address, internet style.\n */\nstruct sockaddr_in {\n    short   sin_family;\n    u_short sin_port;\n    struct  in_addr sin_addr;\n    char    sin_zero[8];\n};\n\n/*\n * Options for use with [gs]etsockopt at the IP level.\n */\n#define IP_OPTIONS          1       /* set/get IP per-packet options */\n\n/*\n * Definitions for inet sysctl operations.\n *\n * Third level is protocol number.\n * Fourth level is desired variable within that protocol.\n */\n#define IPPROTO_MAXID       (IPPROTO_IDP + 1)   /* don't list to IPPROTO_MAX */\n\n#ifndef KERNEL\n#define CTL_IPPROTO_NAMES { \\\n    { \"ip\", CTLTYPE_NODE }, \\\n    { \"icmp\", CTLTYPE_NODE }, \\\n    { \"igmp\", CTLTYPE_NODE }, \\\n    { 0, 0 }, \\\n    { 0, 0 }, \\\n    { 0, 0 }, \\\n    { \"tcp\", CTLTYPE_NODE }, \\\n    { 0, 0 }, \\\n    { 0, 0 }, \\\n    { 0, 0 }, \\\n    { 0, 0 }, \\\n    { 0, 0 }, \\\n    { 0, 0 }, \\\n    { 0, 0 }, \\\n    { 0, 0 }, \\\n    { 0, 0 }, \\\n    { 0, 0 }, \\\n    { \"udp\", CTLTYPE_NODE }, \\\n    { 0, 0 }, \\\n    { 0, 0 }, \\\n    { 0, 0 }, \\\n    { 0, 0 }, \\\n    { \"idp\", CTLTYPE_NODE }, \\\n}\n#endif /* KERNEL */\n\n/*\n * Names for IP sysctl objects\n */\n#define IPCTL_FORWARDING    1   /* act as router */\n#define IPCTL_SENDREDIRECTS 2   /* may send redirects when forwarding */\n#define IPCTL_DEFTTL        3   /* default TTL */\n#ifdef notyet\n#define IPCTL_DEFMTU        4   /* default MTU */\n#endif\n#define IPCTL_FORWSRCRT     5   /* forward source-routed dgrams */\n#define IPCTL_MAXID         6\n\n#ifndef KERNEL\n#define IPCTL_NAMES { \\\n    { 0, 0 }, \\\n    { \"forwarding\", CTLTYPE_INT }, \\\n    { \"redirect\", CTLTYPE_INT }, \\\n    { \"ttl\", CTLTYPE_INT }, \\\n    { \"mtu\", CTLTYPE_INT }, \\\n    { \"forwsrcrt\", CTLTYPE_INT }, \\\n}\n#endif /* KERNEL */\n"
  },
  {
    "path": "include/nlist.h",
    "content": "/*-\n * Copyright (c) 1991 The Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *  This product includes software developed by the University of\n *  California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#ifndef _NLIST_H_\n#define _NLIST_H_\n#include <sys/types.h>\n\n/*\n * Symbol table entry format.\n */\nstruct  nlist {\n    char    *n_name;        /* In memory address of symbol name,\n                             * or string table offset (file) */\n    u_short n_len;          /* Length of name in bytes */\n    u_short n_type;         /* Type of symbol - see below */\n    u_int   n_value;        /* Symbol value */\n};\n\n/*\n * Simple values for n_type.\n */\n#define N_UNDF  0x00        /* undefined */\n#define N_ABS   0x01        /* absolute */\n#define N_TEXT  0x02        /* text segment */\n#define N_DATA  0x03        /* data segment */\n#define N_BSS   0x04        /* bss segment */\n#define N_STRNG 0x05        /* string segment (for assembler) */\n#define N_COMM  0x06        /* .comm segment (for assembler) */\n#define N_FN    0x1f        /* file name */\n\n#define N_TYPE  0x1f        /* mask for all the type bits */\n#define N_EXT   0x20        /* external (global) bit, OR'ed in */\n#define N_WEAK  0x40        /* weak reference bit, OR'ed in */\n#define N_LOC   0x80        /* local, for assembler */\n\n/*\n * Get symbols from a file.\n */\nint nlist (char *name, struct nlist *list);\n\n/*\n * Get kernel symbols.\n */\nint knlist (struct nlist *list);\n\n#endif  /* !_NLIST_H_ */\n"
  },
  {
    "path": "include/paths.h",
    "content": "/*\n * Copyright (c) 1989 The Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that the above copyright notice and this paragraph are\n * duplicated in all such forms and that any documentation,\n * advertising materials, and other materials related to such\n * distribution and use acknowledge that the software was developed\n * by the University of California, Berkeley.  The name of the\n * University may not be used to endorse or promote products derived\n * from this software without specific prior written permission.\n * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n */\n#define _PATH_BSHELL    \"/bin/sh\"\n#define _PATH_CSHELL    \"/bin/csh\"\n#define _PATH_CP        \"/bin/cp\"\n#define _PATH_ECHO      \"/bin/echo\"\n#define _PATH_MORE      \"/usr/bin/more\"\n#define _PATH_RSH       \"/bin/rsh\"\n#define _PATH_VI        \"/usr/bin/vi\"\n#define _PATH_CORE      \"/core\"\n#define _PATH_DEV       \"/dev/\"\n#define _PATH_CONSOLE   \"/dev/console\"\n#define _PATH_LOG       \"/dev/log\"\n#define _PATH_DEVNULL   \"/dev/null\"\n#define _PATH_TTY       \"/dev/tty\"\n#define _PATH_MEM       \"/dev/mem\"\n#define _PATH_SWAP      \"/dev/swap\"\n#define _PATH_FSTAB     \"/etc/fstab\"\n#define _PATH_LOCALTIME \"/etc/localtime\"\n#define _PATH_MOTD      \"/etc/motd\"\n#define _PATH_NOLOGIN   \"/etc/nologin\"\n#define _PATH_PASSWD    \"/etc/passwd\"\n#define _PATH_PTMP      \"/etc/ptmp\"\n#define _PATH_SHADOW    \"/etc/shadow\"\n#define _PATH_TERMCAP   \"/etc/termcap\"\n#define _PATH_USRLIB    \"/usr/lib/\"\n#define _PATH_CTIMED    \"/usr/libexec/ctimed\"\n#define _PATH_LOCALLIB  \"/local/lib/\"\n#define _PATH_SBIN      \"/sbin/\"\n#define _PATH_USRSBIN   \"/usr/sbin/\"\n#define _PATH_MKPASSWD  \"/usr/sbin/mkpasswd\"\n#define _PATH_SENDMAIL  \"/sbin/sendmail\"\n#define _PATH_SHARE     \"/usr/share/\"\n#define _PATH_ZONEINFO  \"/usr/share/zoneinfo\"   /* Time zone object file directory */\n#define _PATH_TMP       \"/tmp/\"\n#define _PATH_USRTMP    \"/tmp/\"\n#define _PATH_LASTLOG   \"/var/log/lastlog\"\n#define _PATH_MESSAGES  \"/var/log/messages\"\n#define _PATH_WTMP      \"/var/log/wtmp\"\n#define _PATH_MAIL      \"/var/mail/\"\n#define _PATH_VARRUN    \"/var/run/\"\n#define _PATH_DEVDB     \"/var/run/dev\"\n#define _PATH_UTMP      \"/var/run/utmp\"\n#define _PATH_ARTMP     \"/tmp/ar.XXXXXX\"\n#define _PATH_RANTMP    \"/tmp/ranlib.XXXXXX\"\n\n#define _PATH_STDPATH   \"/usr/bin:/bin:/usr/sbin:/sbin\"\n#define _PATH_SYSPATH   \"/usr/bin:/bin:/usr/sbin:/sbin:/local\"\n#define _PATH_MAN       \"/usr/share/man\"\n#define _PATH_LOCALMAN  \"/local/man\"\n\n#define _PATH_HUSHLOGIN \".hushlogin\"\n"
  },
  {
    "path": "include/psout.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * psout: structure output by 'ps -U'.\n * Mostly the pre-processed /dev directory.\n */\n\n#ifndef makedev\n#include <sys/types.h>\n#endif\n\nstruct psout {\n    dev_t   o_ttyd;                 /* u_ttyd */\n    int     o_flag;                 /* p_flag */\n    short   o_pid;                  /* p_pid */\n    char    o_tty[3];               /* 1st 2 chars of tty after 'tty' */\n    char    o_stat;                 /* p_stat */\n    short   o_uid;                  /* p_uid */\n    char    o_uname[UT_NAMESIZE];   /* login name of process owner */\n    short   o_ppid;                 /* p_ppid */\n    char    o_cpu;                  /* p_cpu */\n    char    o_pri;                  /* p_pri */\n    char    o_nice;                 /* p_nice */\n    short   o_addr0;                /* p_addr[0] */\n    short   o_size;                 /* p_size */\n    caddr_t o_wchan;                /* p_wchan */\n    time_t  o_utime;                /* u_utime */\n    time_t  o_stime;                /* u_stime */\n    time_t  o_cutime;               /* u_cutime */\n    time_t  o_cstime;               /* u_cstime */\n    short   o_pgrp;                 /* p_pgrp */\n    int     o_sigs;                 /* sum of SIGINT & SIGQUIT,\n                                     * if == 2 proc is ignoring both.*/\n    char    o_comm[MAXCOMLEN+1];    /* u_comm */\n    char    o_args[64];             /* best guess at args to process */\n};\n"
  },
  {
    "path": "include/pwd.h",
    "content": "/*\n * Copyright (c) 1988 The Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that the above copyright notice and this paragraph are\n * duplicated in all such forms and that any documentation,\n * advertising materials, and other materials related to such\n * distribution and use acknowledge that the software was developed\n * by the University of California, Berkeley.  The name of the\n * University may not be used to endorse or promote products derived\n * from this software without specific prior written permission.\n * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n */\n\n#define _PW_KEYBYNAME       '0'\n#define _PW_KEYBYUID        '1'\n\nstruct passwd {\n    char    *pw_name;           /* user name */\n    char    *pw_passwd;         /* encrypted password */\n    int     pw_uid;             /* user uid */\n    int     pw_gid;             /* user gid */\n    char    *pw_gecos;          /* real name */\n    char    *pw_dir;            /* home directory */\n    char    *pw_shell;          /* default shell */\n};\n\nstruct passwd *getpwent(), *getpwuid(), *getpwnam();\nvoid endpwent(), setpwfile();\nint setpwent();\nint setpassent (int);\n"
  },
  {
    "path": "include/ranlib.h",
    "content": "/*-\n * Copyright (c) 1990 The Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *  This product includes software developed by the University of\n *  California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n#ifndef _RANLIB_H_\n#define _RANLIB_H_\n\n#define RANLIBMAG   \"__.SYMDEF\" /* archive file name */\n#define RANLIBSKEW  3           /* creation time offset */\n\nstruct ranlib {\n    int     ran_len;            /* 1 byte - name length in bytes */\n    unsigned ran_off;           /* 4 bytes - file offset */\n    char    *ran_name;          /* in memory symbol name */\n};\n\n#endif /* !_RANLIB_H_ */\n"
  },
  {
    "path": "include/regexp.h",
    "content": "/*\n * Definitions etc. for regexp(3) routines.\n *\n * Caveat:  this is V8 regexp(3) [actually, a reimplementation thereof],\n * not the System V one.\n */\n#define NSUBEXP  10\n\ntypedef struct regexp {\n    char    *startp[NSUBEXP];\n    char    *endp[NSUBEXP];\n    char    regstart;       /* Internal use only. */\n    char    reganch;        /* Internal use only. */\n    char    *regmust;       /* Internal use only. */\n    int     regmlen;        /* Internal use only. */\n    char    program[1];     /* Unwarranted chumminess with compiler. */\n} regexp;\n\nextern regexp *regcomp();\nextern int regexec();\nextern void regsub();\nextern void regerror();\n"
  },
  {
    "path": "include/setjmp.h",
    "content": "#ifndef _SETJMP_H\n#define _SETJMP_H\n\n#include <machine/setjmp.h>\n\ntypedef int jmp_buf[_JBLEN];\ntypedef jmp_buf sigjmp_buf;\n\n/*\n * Save and restore only CPU state.\n * Signal mask is not saved.\n */\nint _setjmp (jmp_buf env);\nvoid _longjmp (jmp_buf env, int val);\n\n/*\n * Save and restore CPU state and signal mask.\n */\nint setjmp (jmp_buf env);\nvoid longjmp (jmp_buf env, int val);\n\n/*\n * Save and restore CPU state and optionally a signal mask.\n * Signal mask is saved only when savesigs is nonzero.\n */\nint sigsetjmp (sigjmp_buf env, int savesigs);\nvoid siglongjmp (sigjmp_buf env, int val);\n\n#endif /* !_SETJMP_H */\n"
  },
  {
    "path": "include/sgtty.h",
    "content": "/*\tsgtty.h\t4.2\t85/01/03\t*/\n\n#ifndef\t_IOCTL_\n#include <sys/ioctl.h>\n#endif\n"
  },
  {
    "path": "include/smallc/curses.h",
    "content": "/*\n * SmallC: interface to curses library.\n */\n#define WINDOW int\n\nextern WINDOW *stdscr, *curscr;\n\nextern int LINES, COLS;\n\n/*\n * pseudo functions for standard screen\n */\n#define addch(ch)       waddch(stdscr, ch)\n#define getch()         wgetch(stdscr)\n#define addstr(str)     waddstr(stdscr, str)\n#define getstr(str)     wgetstr(stdscr, str)\n#define move(y, x)      wmove(stdscr, y, x)\n#define clear()         wclear(stdscr)\n#define erase()         werase(stdscr)\n#define clrtobot()      wclrtobot(stdscr)\n#define clrtoeol()      wclrtoeol(stdscr)\n#define insertln()      winsertln(stdscr)\n#define deleteln()      wdeleteln(stdscr)\n#define refresh()       wrefresh(stdscr)\n#define inch()          winch(stdscr)\n#define insch(c)        winsch(stdscr,c)\n#define delch()         wdelch(stdscr)\n#define standout()      wstandout(stdscr)\n#define standend()      wstandend(stdscr)\n\n/*\n * mv functions\n */\n#define mvwaddch(win,y,x,ch)    wmove(win,y,x) == 0 ? 0 : waddch(win,ch)\n#define mvwgetch(win,y,x)       wmove(win,y,x) == 0 ? 0 : wgetch(win)\n#define mvwaddstr(win,y,x,str)  wmove(win,y,x) == 0 ? 0 : waddstr(win,str)\n#define mvwgetstr(win,y,x,str)  wmove(win,y,x) == 0 ? 0 : wgetstr(win,str)\n#define mvwinch(win,y,x)        wmove(win,y,x) == 0 ? 0 : winch(win)\n#define mvwdelch(win,y,x)       wmove(win,y,x) == 0 ? 0 : wdelch(win)\n#define mvwinsch(win,y,x,c)     wmove(win,y,x) == 0 ? 0 : winsch(win,c)\n#define mvaddch(y,x,ch)         mvwaddch(stdscr,y,x,ch)\n#define mvgetch(y,x)            mvwgetch(stdscr,y,x)\n#define mvaddstr(y,x,str)       mvwaddstr(stdscr,y,x,str)\n#define mvgetstr(y,x,str)       mvwgetstr(stdscr,y,x,str)\n#define mvinch(y,x)             mvwinch(stdscr,y,x)\n#define mvdelch(y,x)            mvwdelch(stdscr,y,x)\n#define mvinsch(y,x,c)          mvwinsch(stdscr,y,x,c)\n\n#ifdef TODO\n\n#define TRUE    (1)\n#define FALSE   (0)\n#define ERR     (0)\n#define OK      (1)\n\n/*\n * Capabilities from termcap\n */\nextern int     AM, BS, CA, DA, DB, EO, HC, HZ, IN, MI, MS, NC, NS, OS, UL,\n                XB, XN, XT, XS, XX;\nextern char     *AL, *BC, *BT, *CD, *CE, *CL, *CM, *CR, *CS, *DC, *DL,\n                *DM, *DO, *ED, *EI, *K0, *K1, *K2, *K3, *K4, *K5, *K6,\n                *K7, *K8, *K9, *HO, *IC, *IM, *IP, *KD, *KE, *KH, *KL,\n                *KR, *KS, *KU, *LL, *MA, *ND, *NL, *RC, *SC, *SE, *SF,\n                *SO, *SR, *TA, *TE, *TI, *UC, *UE, *UP, *US, *VB, *VS,\n                *VE, *AL_PARM, *DL_PARM, *UP_PARM, *DOWN_PARM,\n                *LEFT_PARM, *RIGHT_PARM;\nextern char     PC;\n\n/*\n * From the tty modes...\n */\nextern int      GT, NONL, UPPERCASE, normtty, _pfast;\n\nextern int      My_term, _echoit, _rawmode, _endwin;\n\nextern char     *Def_term, ttytype[];\n\nextern int      _tty_ch, _res_flg;\n\nextern SGTTY    _tty;\n\n/*\n * pseudo functions\n */\n#define clearok(win,bf)  (win->_clear = bf)\n#define leaveok(win,bf)  (win->_leave = bf)\n#define scrollok(win,bf) (win->_scroll = bf)\n#define flushok(win,bf)  (bf ? (win->_flags |= _FLUSH):(win->_flags &= ~_FLUSH))\n#define getyx(win,y,x)   y = win->_cury, x = win->_curx\n#define winch(win)       (win->_y[win->_cury][win->_curx] & 0177)\n\n#define raw()    (_tty.sg_flags|=RAW, _pfast=_rawmode=TRUE, ioctl(_tty_ch,TIOCSETP,&_tty))\n#define noraw()  (_tty.sg_flags&=~RAW,_rawmode=FALSE,_pfast=!(_tty.sg_flags&CRMOD),ioctl(_tty_ch,TIOCSETP,&_tty))\n#define cbreak() (_tty.sg_flags |= CBREAK, _rawmode = TRUE, ioctl(_tty_ch,TIOCSETP,&_tty))\n#define nocbreak() (_tty.sg_flags &= ~CBREAK,_rawmode=FALSE,ioctl(_tty_ch,TIOCSETP,&_tty))\n#define echo()   (_tty.sg_flags |= ECHO,  _echoit = TRUE,    ioctl(_tty_ch, TIOCSETP, &_tty))\n#define noecho() (_tty.sg_flags &= ~ECHO, _echoit = FALSE,   ioctl(_tty_ch, TIOCSETP, &_tty))\n#define nl()     (_tty.sg_flags |= CRMOD, _pfast  = _rawmode,ioctl(_tty_ch, TIOCSETP, &_tty))\n#define nonl()   (_tty.sg_flags &= ~CRMOD,_pfast  = TRUE,    ioctl(_tty_ch, TIOCSETP,&_tty))\n#define savetty() ((void) ioctl(_tty_ch, TIOCGETP, &_tty), _res_flg = _tty.sg_flags)\n#define resetty() (_tty.sg_flags = _res_flg, (void) ioctl(_tty_ch, TIOCSETP, &_tty))\n\n#define erasechar()     (_tty.sg_erase)\n#define killchar()      (_tty.sg_kill)\n#define baudrate()      (_tty.sg_ospeed)\n\n/*\n * Used to be in unctrl.h.\n */\n#define unctrl(c)       _unctrl[(c) & 0177]\nextern char *_unctrl[];\n\n#endif\n"
  },
  {
    "path": "include/smallc/fcntl.h",
    "content": "\n/* open-only flags */\n#define O_RDONLY        0x0000          /* open for reading only */\n#define O_WRONLY        0x0001          /* open for writing only */\n#define O_RDWR          0x0002          /* open for reading and writing */\n#define O_ACCMODE       0x0003          /* mask for above modes */\n\n#define O_NONBLOCK      0x0004          /* no delay */\n#define O_APPEND        0x0008          /* set append mode */\n#define O_SHLOCK        0x0010          /* open with shared file lock */\n#define O_EXLOCK        0x0020          /* open with exclusive file lock */\n#define O_ASYNC         0x0040          /* signal pgrp when data ready */\n#define O_FSYNC         0x0080          /* synchronous writes */\n#define O_CREAT         0x0200          /* create if nonexistant */\n#define O_TRUNC         0x0400          /* truncate to zero length */\n#define O_EXCL          0x0800          /* error if already exists */\n\n/*\n * Constants used for fcntl(2)\n */\n\n/* command values */\n#define F_DUPFD         0               /* duplicate file descriptor */\n#define F_GETFD         1               /* get file descriptor flags */\n#define F_SETFD         2               /* set file descriptor flags */\n#define F_GETFL         3               /* get file status flags */\n#define F_SETFL         4               /* set file status flags */\n#define F_GETOWN        5               /* get SIGIO/SIGURG proc/pgrp */\n#define F_SETOWN        6               /* set SIGIO/SIGURG proc/pgrp */\n\n/* file descriptor flags (F_GETFD, F_SETFD) */\n#define FD_CLOEXEC      1               /* close-on-exec flag */\n\n/* lock operations for flock() */\n#define LOCK_SH         1               /* shared file lock */\n#define LOCK_EX         2               /* exclusive file lock */\n#define LOCK_NB         4               /* don't block when locking */\n#define LOCK_UN         8               /* unlock file */\n"
  },
  {
    "path": "include/smallc/signal.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#ifndef NSIG\n\n#define NSIG    32\n\n#define SIGHUP  1       /* hangup */\n#define SIGINT  2       /* interrupt */\n#define SIGQUIT 3       /* quit */\n#define SIGILL  4       /* illegal instruction (not reset when caught) */\n#define SIGTRAP 5       /* trace trap (not reset when caught) */\n#define SIGIOT  6       /* IOT instruction */\n#define SIGABRT SIGIOT  /* compatibility */\n#define SIGEMT  7       /* EMT instruction */\n#define SIGFPE  8       /* floating point exception */\n#define SIGKILL 9       /* kill (cannot be caught or ignored) */\n#define SIGBUS  10      /* bus error */\n#define SIGSEGV 11      /* segmentation violation */\n#define SIGSYS  12      /* bad argument to system call */\n#define SIGPIPE 13      /* write on a pipe with no one to read it */\n#define SIGALRM 14      /* alarm clock */\n#define SIGTERM 15      /* software termination signal from kill */\n#define SIGURG  16      /* urgent condition on IO channel */\n#define SIGSTOP 17      /* sendable stop signal not from tty */\n#define SIGTSTP 18      /* stop signal from tty */\n#define SIGCONT 19      /* continue a stopped process */\n#define SIGCHLD 20      /* to parent on child stop or exit */\n#define SIGCLD  SIGCHLD /* compatibility */\n#define SIGTTIN 21      /* to readers pgrp upon background tty read */\n#define SIGTTOU 22      /* like TTIN for output if (tp->t_local&LTOSTOP) */\n#define SIGIO   23      /* input/output possible signal */\n#define SIGXCPU 24      /* exceeded CPU time limit */\n#define SIGXFSZ 25      /* exceeded file size limit */\n#define SIGVTALRM 26    /* virtual time alarm */\n#define SIGPROF 27      /* profiling time alarm */\n#define SIGWINCH 28     /* window size changes */\n#define SIGUSR1 30      /* user defined signal 1 */\n#define SIGUSR2 31      /* user defined signal 2 */\n\n#define SIG_ERR         -1\n#define SIG_DFL         0\n#define SIG_IGN         1\n#define BADSIG          SIG_ERR\n\n#define SA_ONSTACK      0x0001  /* take signal on signal stack */\n#define SA_RESTART      0x0002  /* restart system on signal return */\n#define SA_DISABLE      0x0004  /* disable taking signals on alternate stack */\n#define SA_NOCLDSTOP    0x0008  /* do not generate SIGCHLD on child stop */\n\n/*\n * Flags for sigprocmask:\n */\n#define SIG_BLOCK       1       /* block specified signal set */\n#define SIG_UNBLOCK     2       /* unblock specified signal set */\n#define SIG_SETMASK     3       /* set specified signal set */\n\n#define MINSIGSTKSZ     128                     /* minimum allowable stack */\n#define SIGSTKSZ        (MINSIGSTKSZ + 384)     /* recommended stack size */\n\n#define SV_ONSTACK      SA_ONSTACK      /* take signal on signal stack */\n#define SV_INTERRUPT    SA_RESTART      /* same bit, opposite sense */\n\n/*\n * Macro for converting signal number to a mask suitable for\n * sigblock().\n */\n#define sigmask(m)              (1L << ((m)-1))\n#define sigaddset(set, signo)   (*(set) |= 1L << ((signo) - 1), 0)\n#define sigdelset(set, signo)   (*(set) &= ~(1L << ((signo) - 1)), 0)\n#define sigemptyset(set)        (*(set) = (sigset_t)0, (int)0)\n#define sigfillset(set)         (*(set) = ~(sigset_t)0, (int)0)\n#define sigismember(set, signo) ((*(set) & (1L << ((signo) - 1))) != 0)\n\n#endif /* NSIG */\n"
  },
  {
    "path": "include/smallc/stdio.h",
    "content": "/*\n * SmallC: interface to stdio library.\n */\n#define BUFSIZ  1024\n\n#ifndef NULL\n#define NULL    0\n#endif\n\n#define FILE    int\n#define EOF     (-1)\n\nextern int _iob[];\n\n#define stdin   (&_iob[0])\n#define stdout  (&_iob[5])\n#define stderr  (&_iob[10])\n\n#define SEEK_SET 0      /* set file offset to offset */\n#define SEEK_CUR 1      /* set file offset to current plus offset */\n#define SEEK_END 2      /* set file offset to EOF plus offset */\n\n#define getc fgetc\n#define putc fputc\n"
  },
  {
    "path": "include/smallc/sys/gpio.h",
    "content": "/*\n * Ioctl definitions for GPIO driver.\n */\n#define GPIO_PORT(n)    (n)         /* port number */\n#define GPIO_PORTA      0\n#define GPIO_PORTB      1\n#define GPIO_PORTC      2\n#define GPIO_PORTD      3\n#define GPIO_PORTE      4\n#define GPIO_PORTF      5\n#define GPIO_PORTG      6\n\n#define GPIO_CONFIN     0x20016700  /* configure as input */\n#define GPIO_CONFOUT    0x20026700  /* configure as output */\n#define GPIO_CONFOD     0x20046700  /* configure as open drain */\n#define GPIO_DECONF     0x20086700  /* deconfigure */\n#define GPIO_STORE      0x20106700  /* store all outputs */\n#define GPIO_SET        0x20206700  /* set to 1 by mask */\n#define GPIO_CLEAR      0x20406700  /* set to 0 by mask */\n#define GPIO_INVERT     0x20806700  /* invert by mask */\n#define GPIO_POLL       0x21006700  /* poll */\n#define GPIO_LOL        0x82006700  /* display lol picture */\n"
  },
  {
    "path": "include/smallc/sys/spi.h",
    "content": "/*\n * Ioctl definitions for SPI driver.\n */\n#define SPICTL_SETMODE      0x20007000              /* set SPI mode */\n#define SPICTL_SETRATE      0x20007001              /* set clock rate, kHz */\n#define SPICTL_SETSELPIN    0x20007002              /* set select pin */\n#define SPICTL_IO8(n)      (0xc0007003 | (n)<<16)   /* transfer n*8 bits */\n#define SPICTL_IO16(n)     (0xc0007004 | (n)<<16)   /* transfer n*16 bits */\n#define SPICTL_IO32(n)     (0xc0007005 | (n)<<16)   /* transfer n*32 bits */\n"
  },
  {
    "path": "include/smallc/wiznet.h",
    "content": "/*\n * SmallC: interface to wiznet library.\n */\n#define MAX_SOCK_NUM            4   /* Max number of sockets per chip */\n#define CLIENT_SIZE             3   /* Size of client structure in words */\n#define UDP_SIZE                2   /* Size of UDP structure in words */\n\nextern unsigned _socket_port[];\n\nextern unsigned _client_srcport;\n\nextern unsigned _server_port;\n"
  },
  {
    "path": "include/stdarg.h",
    "content": "/*\n * ISO C Standard:  7.15  Variable arguments  <stdarg.h>\n */\n#ifndef _STDARG_H\n#define _STDARG_H\n\n/*\n * Define va_start, va_arg, va_end, va_copy.\n */\n#if defined(__GNUC__)           /* Gnu C */\n# define va_start(ap, last)     __builtin_va_start((ap), last)\n# define va_arg(ap, type)       __builtin_va_arg((ap), type)\n# define va_end(ap)             __builtin_va_end((ap))\n# define va_copy(dest, src)     __builtin_va_copy((dest), (src))\n\n#elif defined(__PCC__)          /* PCC */\n# define va_start(ap, last)     __builtin_stdarg_start((ap), last)\n# define va_arg(ap, type)       __builtin_va_arg((ap), type)\n# define va_end(ap)             __builtin_va_end((ap))\n# define va_copy(dest, src)     __builtin_va_copy((dest), (src))\n\n#else                           /* SmallerC, LCC */\n# define va_start(ap, last)     (ap = ((char*)&(last) + \\\n        (((sizeof(last) + sizeof(int) - 1) / sizeof(int)) * sizeof(int))))\n# define va_arg(ap, type)       ((type*)(ap += \\\n        sizeof(type) == sizeof(int) ? sizeof(type) : \\\n        (-(int)(ap) & (sizeof(type) - 1)) + sizeof(type)))[-1]\n# define va_end(ap)\n# define va_copy(dest, src)     (dest = (src))\n#endif\n\n/*\n * Define va_list.\n */\n#ifndef _VA_LIST_T\n# define _VA_LIST_T\n# if defined(__GNUC__) || defined(__PCC__)\n    typedef __builtin_va_list va_list;\n# else\n    typedef char *va_list;\n# endif\n#endif\n\n/*\n * Define __gnuc_va_list.\n */\n#if defined(__GNUC__) && !defined(__GNUC_VA_LIST)\n# define __GNUC_VA_LIST\n    typedef __builtin_va_list __gnuc_va_list;\n#endif\n\n#endif /* not _STDARG_H */\n"
  },
  {
    "path": "include/stdbool.h",
    "content": "/* $OpenBSD: stdbool.h,v 1.7 2015/09/04 23:47:09 daniel Exp $ */\n\n/*\n * Written by Marc Espie, September 25, 1999\n * Public domain.\n */\n\n#ifndef\t_STDBOOL_H_\n#define\t_STDBOOL_H_\n\n#ifndef __cplusplus\n\n#if defined(__GNUC__) || \\\n\t(defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901)\n/* Support for C99: type _Bool is already built-in. */\n#define\tfalse\t0\n#define\ttrue\t1\n\n#else\n/* `_Bool' type must promote to `int' or `unsigned int'. */\ntypedef enum {\n\tfalse = 0,\n\ttrue = 1\n} _Bool;\n\n/* And those constants must also be available as macros. */\n#define\tfalse\tfalse\n#define\ttrue\ttrue\n\n#endif\n\n/* User visible type `bool' is provided as a macro which may be redefined. */\n#define\tbool\t_Bool\n\n#else /* __cplusplus */\n#define\t_Bool \tbool\n#define\tbool \tbool\n#define\tfalse \tfalse\n#define\ttrue \ttrue\n#endif /* __cplusplus */\n\n/* Inform that everything is fine. */\n#define\t__bool_true_false_are_defined\t1\n\n#endif /* _STDBOOL_H_ */\n"
  },
  {
    "path": "include/stddef.h",
    "content": "#ifndef _STDDEF_H_\n#define _STDDEF_H_\n\ntypedef int ptrdiff_t;\n\n#ifndef _SIZE_T\n#define _SIZE_T\ntypedef unsigned size_t;\n#endif\n\n#ifndef NULL\n#define NULL    0\n#endif\n\n/* Offset of member MEMBER in a struct of type TYPE. */\n#if defined(__GNUC__) && __GNUC__ > 3\n#define offsetof(TYPE, MEMBER) __builtin_offsetof (TYPE, MEMBER)\n#else\n#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE*)0)->MEMBER)\n#endif\n\n#endif /* _STDDEF_H_ */\n"
  },
  {
    "path": "include/stdio.h",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#ifndef FILE\n\n#define BUFSIZ  1024\nextern  struct  _iobuf {\n    int     _cnt;\n    char    *_ptr;      /* should be unsigned char */\n    char    *_base;     /* ditto */\n    int     _bufsiz;\n    short   _flag;\n    short   _file;\n} _iob[];\n\n#define _IOREAD     01\n#define _IOWRT      02\n#define _IONBF      04\n#define _IOMYBUF    010\n#define _IOEOF      020\n#define _IOERR      040\n#define _IOSTRG     0100\n#define _IOLBF      0200\n#define _IORW       0400\n\n/*\n * The following definition is for ANSI C, which took them\n * from System V, which brilliantly took internal interface macros and\n * made them official arguments to setvbuf(), without renaming them.\n * Hence, these ugly _IOxxx names are *supposed* to appear in user code.\n*/\n#define _IOFBF      0   /* setvbuf should set fully buffered */\n                        /* _IONBF and _IOLBF are used from the flags above */\n\n#ifndef NULL\n#define NULL        0\n#endif\n\n#ifndef _SIZE_T\n#define _SIZE_T\ntypedef unsigned size_t;\n#endif\n\n#define FILE        struct _iobuf\n#define EOF         (-1)\n\n#define stdin       (&_iob[0])\n#define stdout      (&_iob[1])\n#define stderr      (&_iob[2])\n\n#define SEEK_SET    0   /* set file offset to offset */\n#define SEEK_CUR    1   /* set file offset to current plus offset */\n#define SEEK_END    2   /* set file offset to EOF plus offset */\n\nvoid    clearerr(FILE *);\nint     feof(FILE *);\nint     ferror(FILE *);\nint     fileno(FILE *);\n\nFILE    *fopen (const char *, const char *);\nFILE    *fdopen (int, const char *);\nFILE    *freopen (const char *, const char *, FILE *);\nFILE    *popen (const char *, const char *);\nint     pclose (FILE *);\nFILE    *tmpfile (void);\nint     fclose (FILE *);\nlong    ftell (FILE *);\nint     fflush (FILE *);\nint     fgetc (FILE *);\nint     ungetc (int, FILE *);\nint     fputc (int, FILE *);\nint     fputs (const char *, FILE *);\nint     puts (const char *);\nchar    *fgets (char *, int, FILE *);\nchar    *gets (char *);\nFILE    *_findiop (void);\nint     _filbuf (FILE *);\nint     _flsbuf (unsigned char, FILE *);\nvoid    setbuf (FILE *, char *);\nvoid    setbuffer (FILE *, char *, size_t);\nvoid    setlinebuf (FILE *);\nint     setvbuf (FILE *, char *, int, size_t);\nint     fseek (FILE *, long, int);\nvoid    rewind (FILE *);\nint     remove (const char *);\nint     rename (const char *, const char *);\nint     getw(FILE *stream);\nint     putw(int w, FILE *stream);\n\nsize_t  fread (void *, size_t, size_t, FILE *);\nsize_t  fwrite (const void *, size_t, size_t, FILE *);\n\nint     fprintf (FILE *, const char *, ...);\nint     printf (const char *, ...);\nint     sprintf (char *, const char *, ...);\nint     snprintf (char *, size_t, const char *, ...);\n\nint     fscanf (FILE *, const char *, ...);\nint     scanf (const char *, ...);\nint     sscanf (const char *, const char *, ...);\n\n#ifndef _VA_LIST_\n# ifdef __GNUC__\n#  define va_list   __builtin_va_list   /* For Gnu C */\n# endif\n# ifdef __SMALLER_C__\n#  define va_list   char *              /* For Smaller C */\n# endif\n#endif\n\nint     vfprintf (FILE *, const char *, va_list);\nint     vprintf (const char *, va_list);\nint     vsprintf (char *, const char *, va_list);\nint     vsnprintf (char *, size_t, const char *, va_list);\n\nint     vfscanf (FILE *, const char *, va_list);\nint     vscanf (const char *, va_list);\nint     vsscanf (const char *, const char *, va_list);\n\nint     _doprnt (const char *, va_list, FILE *);\nint     _doscan (FILE *, const char *, va_list);\n\n#ifndef _VA_LIST_\n# undef va_list\n#endif\n\nvoid    perror (const char *);\n\n#ifndef lint\n#define getc(p)     (--(p)->_cnt>=0? (int)(*(unsigned char *)(p)->_ptr++):_filbuf(p))\n#define putc(x, p)  (--(p)->_cnt >= 0 ?\\\n    (int)(*(unsigned char *)(p)->_ptr++ = (x)) :\\\n    (((p)->_flag & _IOLBF) && -(p)->_cnt < (p)->_bufsiz ?\\\n        ((*(p)->_ptr = (x)) != '\\n' ?\\\n            (int)(*(unsigned char *)(p)->_ptr++) :\\\n            _flsbuf(*(unsigned char *)(p)->_ptr, p)) :\\\n        _flsbuf((unsigned char)(x), p)))\n#endif /* not lint */\n\n#define getchar()       getc(stdin)\n#define putchar(x)      putc(x,stdout)\n#define __sfeof(p)      (((p)->_flag&_IOEOF)!=0)\n#define __sferror(p)    (((p)->_flag&_IOERR)!=0)\n#define __sfileno(p)    ((p)->_file)\n#define __sclearerr(p)  ((p)->_flag &= ~(_IOERR|_IOEOF))\n\n#define feof(p)         __sfeof(p)\n#define ferror(p)       __sferror(p)\n#define fileno(p)       __sfileno(p)\n#define clearerr(p)     __sclearerr(p)\n\n#endif /* _FILE */\n"
  },
  {
    "path": "include/stdlib.h",
    "content": "/*-\n * Copyright (c) 1990, 1993\n *      The Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *      This product includes software developed by the University of\n *      California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n *      @(#)stdlib.h    8.3.2 (2.11BSD) 1996/1/12\n *\n * Adapted from the 4.4-Lite CD.  The odds of a ANSI C compiler for 2.11BSD\n * being slipped under the door are not distinguishable from 0 - so the\n * prototypes and ANSI ifdefs have been removed from this file.\n *\n * Some functions (strtoul for example) do not exist yet but are retained in\n * this file because additions to libc.a are anticipated shortly.\n */\n\n#ifndef _STDLIB_H_\n#define _STDLIB_H_\n\n#ifndef NULL\n#define NULL            0\n#endif\n\n#define EXIT_FAILURE    1\n#define EXIT_SUCCESS    0\n\n#define RAND_MAX        0x7fff\n\n#ifndef _SIZE_T\n#define _SIZE_T\ntypedef unsigned size_t;\n#endif\n\nvoid    abort (void);\nint     abs (int);\nint     atexit (void (*)(void));\nint     atoi (const char *);\nlong    atol (const char *);\nvoid    *calloc (size_t, size_t);\nvoid    exit (int);\nvoid    free (void *);\nchar    *getenv (const char *);\nlong    labs (long);\nvoid    *malloc (size_t);\nchar    *mktemp (char *);\nint     mkstemp (char *);\nvoid    qsort (void *, size_t, size_t, int (*)(const void *, const void *));\nint     rand (void);\nvoid    *realloc (void*, size_t);\nvoid    srand (unsigned);\nlong    strtol (const char *, char **, int);\nunsigned long strtoul (const char *, char **, int);\nint     system (const char *);\n\nint     putenv (char *string);\nint     setenv (const char *name, const char *value, int overwrite);\nint     unsetenv (const char *name);\nchar    *_findenv (const char *name, int *offset);\n\nvoid    *alloca (size_t size);\n\nint     daemon (int, int);\nchar    *devname (int dev, int type);\nint     getloadavg (unsigned loadavg[], int nelem);\n\nextern char *suboptarg;                 /* getsubopt(3) external variable */\nint     getsubopt (char **, char **, char **);\n\nlong    random (void);\nchar    *setstate (char *);\nvoid    srandom (unsigned);\n\ndouble  atof (const char *);\ndouble  strtod (const char *, char **);\nchar    *ecvt (double, int, int *, int *);\nchar    *fcvt (double, int, int *, int *);\nchar    *gcvt (double, int, char *);\n\nint\tttyslot (void);\n\n#endif /* _STDLIB_H_ */\n"
  },
  {
    "path": "include/string.h",
    "content": "/*\n * Copyright (c) 1985 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)string.h\t5.1.3 (2.11BSD) 1996/3/20\n */\n\n#ifndef\tNULL\n#define\tNULL\t0\n#endif\n\n#ifndef\t_SIZE_T\n#define\t_SIZE_T\ntypedef\tunsigned int\tsize_t;\n#endif\n\nchar\t\t*strcat(char *, const char *);\nchar\t\t*strncat(char *, const char *, size_t);\nsize_t\t\t strlcat(char *, const char *, size_t);\nchar\t\t*strcpy(char *, const char *);\nchar\t\t*strncpy(char *, const char *, size_t);\nsize_t\t\t strlcpy(char *, const char *, size_t);\n\nchar\t\t*strstr(const char *, const char *);\n\nint\t\t strcmp(const char *, const char *);\nint\t\t strncmp(const char *, const char *, size_t);\nsize_t\t\t strlen(const char *);\n\nint\t\t memcmp(const void *, const void *, size_t);\n\nvoid\t\t*memmove(void *, const void *, size_t);\nvoid\t\t*memccpy(void *, const void *, int, size_t);\nvoid\t\t*memchr(const void *, int, size_t);\nvoid\t\t*memcpy(void *, const void *, size_t);\nvoid\t\t*memset(void *, int, size_t);\nchar\t\t*strchr(const char *, int);\n\nchar\t\t*strdup(const char *);\nchar\t\t*strpbrk(const char *, const char *);\nchar\t\t*strrchr(const char *, int);\nchar\t\t*strsep(char **, const char *);\nchar\t\t*strtok(char *, const char *);\nchar\t\t*strtok_r(char *, const char *, char **);\n\nsize_t\t\t strcspn(const char *, const char *);\nsize_t\t\t strspn(const char *, const char *);\n\nchar\t\t*strerror(int);\nconst char\t*syserrlst(int);\n"
  },
  {
    "path": "include/strings.h",
    "content": "/*-\n * Copyright (c) 1990, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n *\t@(#)strings.h\t8.1 (Berkeley) 6/2/93\n */\n\n#ifndef\t_SIZE_T\n#define\t_SIZE_T\ntypedef\tunsigned int\tsize_t;\n#endif\n\nint\t bcmp(const void *, const void *, size_t);\nvoid\t bcopy(const void *, void *, size_t);\nvoid\t bzero(void *, size_t);\nint\t ffs(int);\nchar\t*index(const char *, int);\nchar\t*rindex(const char *, int);\nint\t strcasecmp(const char *, const char *);\nint\t strncasecmp(const char *, const char *, size_t);\n"
  },
  {
    "path": "include/struct.h",
    "content": "/*      struct.h        4.1     83/05/03        */\n\n/*\n * access to information relating to the fields of a structure\n */\n\n#define fldoff(str, fld)        ((int)&(((struct str *)0)->fld))\n#define fldsiz(str, fld)        (sizeof(((struct str *)0)->fld))\n#define strbase(str, ptr, fld)  ((struct str *)((char *)(ptr)-fldoff(str, fld)))\n"
  },
  {
    "path": "include/syscall.h",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * DO NOT place any comments on the same line as a SYS_* definition.  This\n * causes cpp to leave a trailing tab when expanding macros in pdp/sys/SYS.h\n */\n\n#define SYS_exit        1\n#define SYS_fork        2\n#define SYS_read        3\n#define SYS_write       4\n#define SYS_open        5\n#define SYS_close       6\n#define SYS_wait4       7\n                                /* 8 is old; creat */\n#define SYS_link        9\n#define SYS_unlink      10\n#define SYS_execv       11\n#define SYS_chdir       12\n#define SYS_fchdir      13\n#define SYS_mknod       14\n#define SYS_chmod       15\n#define SYS_chown       16\n#define SYS_chflags     17\n#define SYS_fchflags    18\n#define SYS_lseek       19\n#define SYS_getpid      20\n#define SYS_mount       21\n#define SYS_umount      22\n#define SYS___sysctl    23\n#define SYS_getuid      24\n#define SYS_geteuid     25\n#define SYS_ptrace      26\n#define SYS_getppid     27\n#define SYS_statfs      28\n#define SYS_fstatfs     29\n#define SYS_getfsstat   30\n#define SYS_sigaction   31\n#define SYS_sigprocmask 32\n#define SYS_access      33\n#define SYS_sigpending  34\n#define SYS_sigaltstack 35\n#define SYS_sync        36\n#define SYS_kill        37\n#define SYS_stat        38\n                                /* 39 was getlogin */\n#define SYS_lstat       40\n#define SYS_dup         41\n#define SYS_pipe        42\n                                /* 43 was setlogin */\n#define SYS_profil      44\n#define SYS_setuid      45\n#define SYS_seteuid     46\n#define SYS_getgid      47\n#define SYS_getegid     48\n#define SYS_setgid      49\n#define SYS_setegid     50\n#define SYS_kmemdev 51\n#define SYS_phys        52\n#define SYS_lock        53\n#define SYS_ioctl       54\n#define SYS_reboot      55\n#define SYS_sigwait     56\n#define SYS_symlink     57\n#define SYS_readlink    58\n#define SYS_execve      59\n#define SYS_umask       60\n#define SYS_chroot      61\n#define SYS_fstat       62\n                                /* 63 is unused */\n                                /* 64 is old; getpagesize */\n#define SYS_pselect     65\n#define SYS_vfork       2       /* 66 - not fixed yet */\n                                /* 67 is old; vread */\n                                /* 68 is old; vwrite */\n#define SYS_sbrk        69\n#define SYS_rdglob      70\n#define SYS_wrglob      71\n                                /* 71 is unused 4.3: mmap */\n#define SYS_msec        72      /* 72 is unused 4.3: vadvise */\n                                /* 73 is unused 4.3: munmap */\n                                /* 74 is unused 4.3: mprotect */\n                                /* 75 is unused 4.3: madvise */\n#define SYS_vhangup     76\n                                /* 77 is old; vlimit */\n                                /* 78 is unused 4.3: mincore */\n#define SYS_getgroups   79\n#define SYS_setgroups   80\n#define SYS_getpgrp     81\n#define SYS_setpgrp     82\n#define SYS_setitimer   83\n                                /* 84 is old; wait,wait3 */\n#define SYS_swapon      85\n#define SYS_getitimer   86\n                                /* 87 is old; gethostname */\n                                /* 88 is old; sethostname */\n#define SYS_getdtablesize 89\n#define SYS_dup2        90\n                                /* 91 is unused 4.3: getdopt */\n#define SYS_fcntl       92\n#define SYS_select      93\n                                /* 94 is unused 4.3: setdopt */\n#define SYS_fsync       95\n#define SYS_setpriority 96\n#define SYS_socket      97\n#define SYS_connect     98\n#define SYS_accept      99\n#define SYS_getpriority 100\n#define SYS_send        101\n#define SYS_recv        102\n#define SYS_sigreturn   103\n#define SYS_bind        104\n#define SYS_setsockopt  105\n#define SYS_listen      106\n#define SYS_sigsuspend  107\n/*\n * 108 thru 112 are 4.3BSD compatibility syscalls.  sigstack has to remain\n * defined because no replacement routine exists.  Sigh.\n*/\n                                /* 108 is old; sigvec */\n                                /* 109 is old; sigblock */\n                                /* 110 is old; sigsetmask */\n                                /* 111 is old; sigpause */\n#define SYS_sigstack    112\n\n#define SYS_recvmsg     113\n#define SYS_sendmsg     114\n                                /* 115 is old; vtrace */\n#define SYS_gettimeofday 116\n#define SYS_getrusage   117\n#define SYS_getsockopt  118\n                                /* 119 is old; resuba */\n#define SYS_readv       120\n#define SYS_writev      121\n#define SYS_settimeofday 122\n#define SYS_fchown      123\n#define SYS_fchmod      124\n#define SYS_recvfrom    125\n                                /* 126 is old; setreuid */\n                                /* 127 is old; setregid */\n#define SYS_rename      128\n#define SYS_truncate    129\n#define SYS_ftruncate   130\n#define SYS_flock       131\n                                /* 132 is unused */\n#define SYS_sendto      133\n#define SYS_shutdown    134\n#define SYS_socketpair  135\n#define SYS_mkdir       136\n#define SYS_rmdir       137\n#define SYS_utimes      138\n                                /* 139 is unused */\n#define SYS_adjtime     140\n#define SYS_getpeername 141\n                                /* 142 is old; gethostid */\n                                /* 143 is old; sethostid */\n#define SYS_getrlimit   144\n#define SYS_setrlimit   145\n#define SYS_killpg      146\n                                /* 147 is unused */\n#define SYS_setquota    148\n#define SYS_quota       149\n#define SYS_getsockname 150\n\n/*\n * 2BSD special calls\n */\n                                /* 151 is unused */\n#define SYS_ustore      152\n#define SYS_ufetch      153\n#define SYS_ucall       154\n                                /* 155 is unused */\n"
  },
  {
    "path": "include/sysexits.h",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that this notice is preserved and that due credit is given\n * to the University of California at Berkeley. The name of the University\n * may not be used to endorse or promote products derived from this\n * software without specific prior written permission. This software\n * is provided ``as is'' without express or implied warranty.\n *\n *      @(#)sysexits.h  4.4.1 (2.11BSD) 1996/11/29\n */\n\n/*\n**  SYSEXITS.H -- Exit status codes for system programs.\n**\n**      This include file attempts to categorize possible error\n**      exit statuses for system programs, notably delivermail\n**      and the Berkeley network.\n**\n**      Error numbers begin at EX__BASE to reduce the possibility of\n**      clashing with other exit statuses that random programs may\n**      already return.  The meaning of the codes is approximately\n**      as follows:\n**\n**      EX_USAGE -- The command was used incorrectly, e.g., with\n**              the wrong number of arguments, a bad flag, a bad\n**              syntax in a parameter, or whatever.\n**      EX_DATAERR -- The input data was incorrect in some way.\n**              This should only be used for user's data & not\n**              system files.\n**      EX_NOINPUT -- An input file (not a system file) did not\n**              exist or was not readable.  This could also include\n**              errors like \"No message\" to a mailer (if it cared\n**              to catch it).\n**      EX_NOUSER -- The user specified did not exist.  This might\n**              be used for mail addresses or remote logins.\n**      EX_NOHOST -- The host specified did not exist.  This is used\n**              in mail addresses or network requests.\n**      EX_UNAVAILABLE -- A service is unavailable.  This can occur\n**              if a support program or file does not exist.  This\n**              can also be used as a catchall message when something\n**              you wanted to do doesn't work, but you don't know\n**              why.\n**      EX_SOFTWARE -- An internal software error has been detected.\n**              This should be limited to non-operating system related\n**              errors as possible.\n**      EX_OSERR -- An operating system error has been detected.\n**              This is intended to be used for such things as \"cannot\n**              fork\", \"cannot create pipe\", or the like.  It includes\n**              things like getuid returning a user that does not\n**              exist in the passwd file.\n**      EX_OSFILE -- Some system file (e.g., /etc/passwd, /var/run/utmp,\n**              etc.) does not exist, cannot be opened, or has some\n**              sort of error (e.g., syntax error).\n**      EX_CANTCREAT -- A (user specified) output file cannot be\n**              created.\n**      EX_IOERR -- An error occurred while doing I/O on some file.\n**      EX_TEMPFAIL -- temporary failure, indicating something that\n**              is not really an error.  In sendmail, this means\n**              that a mailer (e.g.) could not create a connection,\n**              and the request should be reattempted later.\n**      EX_PROTOCOL -- the remote system returned something that\n**              was \"not possible\" during a protocol exchange.\n**      EX_NOPERM -- You did not have sufficient permission to\n**              perform the operation.  This is not intended for\n**              file system problems, which should use NOINPUT or\n**              CANTCREAT, but rather for higher level permissions.\n**              For example, kre uses this to restrict who students\n**              can send mail to.\n**\n**      Maintained by Eric Allman (eric@berkeley, ucbvax!eric) --\n**              please mail changes to me.\n**\n**                      @(#)sysexits.h  4.4             3/24/88\n*/\n\n# define EX_OK          0       /* successful termination */\n\n# define EX__BASE       64      /* base value for error messages */\n\n# define EX_USAGE       64      /* command line usage error */\n# define EX_DATAERR     65      /* data format error */\n# define EX_NOINPUT     66      /* cannot open input */\n# define EX_NOUSER      67      /* addressee unknown */\n# define EX_NOHOST      68      /* host name unknown */\n# define EX_UNAVAILABLE 69      /* service unavailable */\n# define EX_SOFTWARE    70      /* internal software error */\n# define EX_OSERR       71      /* system error (e.g., can't fork) */\n# define EX_OSFILE      72      /* critical OS file missing */\n# define EX_CANTCREAT   73      /* can't create (user) output file */\n# define EX_IOERR       74      /* input/output error */\n# define EX_TEMPFAIL    75      /* temp failure; user is invited to retry */\n# define EX_PROTOCOL    76      /* remote error in protocol */\n# define EX_NOPERM      77      /* permission denied */\n# define EX_CONFIG      78      /* configuration error */\n"
  },
  {
    "path": "include/tcl/tcl.h",
    "content": "/*\n * tcl.h --\n *\n *      This header file describes the externally-visible facilities\n *      of the Tcl interpreter.\n *\n * Copyright 1987-1991 Regents of the University of California\n * Permission to use, copy, modify, and distribute this\n * software and its documentation for any purpose and without\n * fee is hereby granted, provided that the above copyright\n * notice appear in all copies.  The University of California\n * makes no representations about the suitability of this\n * software for any purpose.  It is provided \"as is\" without\n * express or implied warranty.\n */\n#ifndef _TCL\n#define _TCL\n\n#define TCL_VERSION             \"6.7\"\n#define TCL_MAJOR_VERSION       6\n#define TCL_MINOR_VERSION       7\n\n/*\n * Data structures defined opaquely in this module.  The definitions\n * below just provide dummy types.  A few fields are made visible in\n * Tcl_Interp structures, namely those for returning string values.\n * Note:  any change to the Tcl_Interp definition below must be mirrored\n * in the \"real\" definition in tclInt.h.\n */\ntypedef struct Tcl_Interp {\n    unsigned char *result;      /* Points to result string returned by last\n                                 * command. */\n    void (*freeProc) (unsigned char *blockPtr);\n                                /* Zero means result is statically allocated.\n                                 * If non-zero, gives address of procedure\n                                 * to invoke to free the result.  Must be\n                                 * freed by Tcl_Eval before executing next\n                                 * command. */\n    unsigned short errorLine;   /* When TCL_ERROR is returned, this gives\n                                 * the line number within the command where\n                                 * the error occurred (1 means first line). */\n} Tcl_Interp;\n\ntypedef void *Tcl_Trace;\ntypedef void *Tcl_CmdBuf;\n\n/*\n * When a TCL command returns, the string pointer interp->result points to\n * a string containing return information from the command.  In addition,\n * the command procedure returns an integer value, which is one of the\n * following:\n *\n * TCL_OK               Command completed normally;  interp->result contains\n *                      the command's result.\n * TCL_ERROR            The command couldn't be completed successfully;\n *                      interp->result describes what went wrong.\n * TCL_RETURN           The command requests that the current procedure\n *                      return;  interp->result contains the procedure's\n *                      return value.\n * TCL_BREAK            The command requests that the innermost loop\n *                      be exited;  interp->result is meaningless.\n * TCL_CONTINUE         Go on to the next iteration of the current loop;\n *                      interp->result is meaninless.\n */\n#define TCL_OK          0\n#define TCL_ERROR       1\n#define TCL_RETURN      2\n#define TCL_BREAK       3\n#define TCL_CONTINUE    4\n\n#define TCL_RESULT_SIZE 199\n\n/*\n * Procedure types defined by Tcl:\n */\ntypedef void (Tcl_CmdDeleteProc) (void *clientData);\ntypedef int (Tcl_CmdProc) (void *clientData,\n        Tcl_Interp *interp, int argc, unsigned char *argv[]);\ntypedef void (Tcl_CmdTraceProc) (void *clientData,\n        Tcl_Interp *interp, int level, unsigned char *command, Tcl_CmdProc *proc,\n        void *cmdClientData, int argc, unsigned char *argv[]);\ntypedef void (Tcl_FreeProc) (unsigned char *blockPtr);\ntypedef unsigned char *(Tcl_VarTraceProc) (void *clientData,\n        Tcl_Interp *interp, unsigned char *part1, unsigned char *part2, int flags);\n\n/*\n * Flag values passed to Tcl_Eval (see the man page for details;  also\n * see tclInt.h for additional flags that are only used internally by\n * Tcl):\n */\n#define TCL_BRACKET_TERM        1\n\n/*\n * Flag that may be passed to Tcl_ConvertElement to force it not to\n * output braces (careful!  if you change this flag be sure to change\n * the definitions at the front of tclUtil.c).\n */\n#define TCL_DONT_USE_BRACES     1\n\n/*\n * Flag value passed to Tcl_RecordAndEval to request no evaluation\n * (record only).\n */\n#define TCL_NO_EVAL             -1\n\n/*\n * Specil freeProc values that may be passed to Tcl_SetResult (see\n * the man page for details):\n */\n#define TCL_STATIC      ((Tcl_FreeProc *) 0)\n#define TCL_VOLATILE    ((Tcl_FreeProc *) -1)\n#define TCL_DYNAMIC     ((Tcl_FreeProc *) -2)\n\n/*\n * Flag values passed to variable-related procedures.\n */\n#define TCL_GLOBAL_ONLY         1\n#define TCL_APPEND_VALUE        2\n#define TCL_LIST_ELEMENT        4\n#define TCL_NO_SPACE            8\n#define TCL_TRACE_READS         0x10\n#define TCL_TRACE_WRITES        0x20\n#define TCL_TRACE_UNSETS        0x40\n#define TCL_TRACE_DESTROYED     0x80\n#define TCL_INTERP_DESTROYED    0x100\n#define TCL_LEAVE_ERR_MSG       0x200\n\n/*\n * Additional flag passed back to variable watchers.  This flag must\n * not overlap any of the TCL_TRACE_* flags defined above or the\n * TRACE_* flags defined in tclInt.h.\n */\n#define TCL_VARIABLE_UNDEFINED  8\n\n/*\n * Exported Tcl procedures:\n */\nextern void             Tcl_AppendElement (Tcl_Interp *interp, unsigned char *string,\n                                int noSep);\nextern void             Tcl_AppendResult (Tcl_Interp *interp, ...);\nextern unsigned char *  Tcl_AssembleCmd (Tcl_CmdBuf buffer, unsigned char *string);\nextern void             Tcl_AddErrorInfo (Tcl_Interp *interp, unsigned char *message);\nextern char             Tcl_Backslash (unsigned char *src, int *readPtr);\nextern int              Tcl_CommandComplete (unsigned char *cmd);\nextern unsigned char *  Tcl_Concat (int argc, unsigned char **argv);\nextern int              Tcl_ConvertElement (unsigned char *src, unsigned char *dst, int flags);\nextern Tcl_CmdBuf       Tcl_CreateCmdBuf (void);\nextern void             Tcl_CreateCommand (Tcl_Interp *interp, unsigned char *cmdName,\n                                Tcl_CmdProc *proc, void *clientData,\n                                Tcl_CmdDeleteProc *deleteProc);\nextern Tcl_Interp *     Tcl_CreateInterp (void);\nextern int              Tcl_CreatePipeline (Tcl_Interp *interp, int argc,\n                                unsigned char **argv, int **pidArrayPtr,\n                                int *inPipePtr, int *outPipePtr,\n                                int *errFilePtr);\nextern Tcl_Trace        Tcl_CreateTrace (Tcl_Interp *interp,\n                            int level, Tcl_CmdTraceProc *proc,\n                            void *clientData);\nextern void             Tcl_DeleteCmdBuf (Tcl_CmdBuf buffer);\nextern int              Tcl_DeleteCommand (Tcl_Interp *interp,\n                            unsigned char *cmdName);\nextern void             Tcl_DeleteInterp (Tcl_Interp *interp);\nextern void             Tcl_DeleteTrace (Tcl_Interp *interp,\n                            Tcl_Trace trace);\nextern void             Tcl_DetachPids (int numPids, int *pidPtr);\nextern unsigned char *  Tcl_ErrnoId (void);\nextern int              Tcl_Eval (Tcl_Interp *interp, unsigned char *cmd,\n                            int flags, unsigned char **termPtr);\nextern int              Tcl_EvalFile (Tcl_Interp *interp,\n                            unsigned char *fileName);\nextern int              Tcl_ExprBoolean (Tcl_Interp *interp, unsigned char *string,\n                                int *ptr);\nextern int              Tcl_ExprLong (Tcl_Interp *interp, unsigned char *string,\n                                long *ptr);\nextern int              Tcl_ExprString (Tcl_Interp *interp, unsigned char *string);\nextern int              Tcl_Fork (void);\nextern void             Tcl_FreeResult (Tcl_Interp *interp);\nextern int              Tcl_GetBoolean (Tcl_Interp *interp,\n                            unsigned char *string, int *boolPtr);\nextern int              Tcl_GetInt (Tcl_Interp *interp,\n                            char *string, int *intPtr);\nextern unsigned char *  Tcl_GetVar (Tcl_Interp *interp,\n                            unsigned char *varName, int flags);\nextern unsigned char *  Tcl_GetVar2 (Tcl_Interp *interp,\n                            unsigned char *part1, unsigned char *part2, int flags);\nextern int              Tcl_GlobalEval (Tcl_Interp *interp,\n                            unsigned char *command);\nextern void             Tcl_InitHistory (Tcl_Interp *interp);\nextern void             Tcl_InitMemory (Tcl_Interp *interp);\nextern unsigned char *  Tcl_Merge (int argc, unsigned char **argv);\nextern unsigned char *  Tcl_ParseVar (Tcl_Interp *interp,\n                            unsigned char *string, unsigned char **termPtr);\nextern int              Tcl_RecordAndEval (Tcl_Interp *interp,\n                            unsigned char *cmd, int flags);\nextern void             Tcl_ResetResult (Tcl_Interp *interp);\nextern int              Tcl_ScanElement (unsigned char *string,\n                            int *flagPtr);\nextern void             Tcl_SetErrorCode (Tcl_Interp *interp, ...);\nextern void             Tcl_SetResult (Tcl_Interp *interp,\n                            unsigned char *string, Tcl_FreeProc *freeProc);\nextern unsigned char *  Tcl_SetVar (Tcl_Interp *interp,\n                            unsigned char *varName, unsigned char *newValue, int flags);\nextern unsigned char *  Tcl_SetVar2 (Tcl_Interp *interp,\n                            unsigned char *part1, unsigned char *part2,\n                            unsigned char *newValue, int flags);\nextern unsigned char *  Tcl_SignalId (int sig);\nextern unsigned char *  Tcl_SignalMsg (int sig);\nextern int              Tcl_SplitList (Tcl_Interp *interp,\n                            unsigned char *list, int *argcPtr, unsigned char ***argvPtr);\nextern int              Tcl_StringMatch (unsigned char *string,\n                            unsigned char *pattern);\nextern unsigned char *  Tcl_TildeSubst (Tcl_Interp *interp,\n                            unsigned char *name);\nextern int              Tcl_TraceVar (Tcl_Interp *interp,\n                            unsigned char *varName, int flags, Tcl_VarTraceProc *proc,\n                            void *clientData);\nextern int              Tcl_TraceVar2 (Tcl_Interp *interp,\n                            unsigned char *part1, unsigned char *part2, int flags,\n                            Tcl_VarTraceProc *proc, void *clientData);\nextern int              Tcl_UnsetVar (Tcl_Interp *interp,\n                            unsigned char *varName, int flags);\nextern int              Tcl_UnsetVar2 (Tcl_Interp *interp,\n                            unsigned char *part1, unsigned char *part2, int flags);\nextern void             Tcl_UntraceVar (Tcl_Interp *interp,\n                            unsigned char *varName, int flags, Tcl_VarTraceProc *proc,\n                            void *clientData);\nextern void             Tcl_UntraceVar2 (Tcl_Interp *interp,\n                            unsigned char *part1, unsigned char *part2, int flags,\n                            Tcl_VarTraceProc *proc, void *clientData);\nextern int              Tcl_VarEval (Tcl_Interp *interp, ...);\nextern void *           Tcl_VarTraceInfo (Tcl_Interp *interp,\n                            unsigned char *varName, int flags,\n                            Tcl_VarTraceProc *procPtr,\n                            void *prevClientData);\nextern void *           Tcl_VarTraceInfo2 (Tcl_Interp *interp,\n                            unsigned char *part1, unsigned char *part2, int flags,\n                            Tcl_VarTraceProc *procPtr,\n                            void *prevClientData);\nextern int              Tcl_WaitPids (int numPids, int *pidPtr,\n                            int *statusPtr);\n\n#endif /* _TCL */\n"
  },
  {
    "path": "include/term.h",
    "content": "#ifndef _TERM_H\n#define _TERM_H\n\nextern int tgetent(char *, char *);\nextern int tgetnum(char *);\nextern int tgetflag(char *);\nextern char *tgetstr(char *, char **);\nextern char *tgoto(char *, int, int);\nextern int tputs(register char *, int, int (*)());\n\n#endif\n"
  },
  {
    "path": "include/termios-todo.h",
    "content": "#ifndef _TERMIOS_H\n#define _TERMIOS_H\n\n#include <sys/ioctl.h>\n#include <stdint.h>\n\ntypedef unsigned char   cc_t;\ntypedef unsigned int    speed_t;\ntypedef unsigned int    tcflag_t;\n\n#define NCCS 32\nstruct termios\n  {\n    tcflag_t c_iflag;           /* input mode flags */\n    tcflag_t c_oflag;           /* output mode flags */\n    tcflag_t c_cflag;           /* control mode flags */\n    tcflag_t c_lflag;           /* local mode flags */\n    cc_t c_line;                /* line discipline */\n    cc_t c_cc[NCCS];            /* control characters */\n    speed_t c_ispeed;           /* input speed */\n    speed_t c_ospeed;           /* output speed */\n#define _HAVE_STRUCT_TERMIOS_C_ISPEED 1\n#define _HAVE_STRUCT_TERMIOS_C_OSPEED 1\n  };\n\nextern int tcgetattr(int, struct termios *);\nextern int tcsetattr(int, int, struct termios *);\n\n/* c_cc characters */\n#define VINTR 0\n#define VQUIT 1\n#define VERASE 2\n#define VKILL 3\n#define VEOF 4\n#define VTIME 5\n#define VMIN 6\n#define VSWTC 7\n#define VSTART 8\n#define VSTOP 9\n#define VSUSP 10\n#define VEOL 11\n#define VREPRINT 12\n#define VDISCARD 13\n#define VWERASE 14\n#define VLNEXT 15\n#define VEOL2 16\n\n/* c_iflag bits */\n#define IGNBRK  0000001\n#define BRKINT  0000002\n#define IGNPAR  0000004\n#define PARMRK  0000010\n#define INPCK   0000020\n#define ISTRIP  0000040\n#define INLCR   0000100\n#define IGNCR   0000200\n#define ICRNL   0000400\n#define IUCLC   0001000\n#define IXON    0002000\n#define IXANY   0004000\n#define IXOFF   0010000\n#define IMAXBEL 0020000\n#define IUTF8   0040000\n\n/* c_oflag bits */\n#define OPOST   0000001\n#define OLCUC   0000002\n#define ONLCR   0000004\n#define OCRNL   0000010\n#define ONOCR   0000020\n#define ONLRET  0000040\n#define OFILL   0000100\n#define OFDEL   0000200\n#if defined __USE_MISC || defined __USE_XOPEN\n# define NLDLY  0000400\n# define   NL0  0000000\n# define   NL1  0000400\n# define CRDLY  0003000\n# define   CR0  0000000\n# define   CR1  0001000\n# define   CR2  0002000\n# define   CR3  0003000\n# define TABDLY 0014000\n# define   TAB0 0000000\n# define   TAB1 0004000\n# define   TAB2 0010000\n# define   TAB3 0014000\n# define BSDLY  0020000\n# define   BS0  0000000\n# define   BS1  0020000\n# define FFDLY  0100000\n# define   FF0  0000000\n# define   FF1  0100000\n#endif\n\n#define VTDLY   0040000\n#define   VT0   0000000\n#define   VT1   0040000\n\n#ifdef __USE_MISC\n# define XTABS  0014000\n#endif\n\n/* c_lflag bits */\n#define ISIG    0000001\n#define ICANON  0000002\n\n#define CSIZE   0000060\n#define   CS5   0000000\n#define   CS6   0000020\n#define   CS7   0000040\n#define   CS8   0000060\n#define CSTOPB  0000100\n#define CREAD   0000200\n#define PARENB  0000400\n#define PARODD  0001000\n#define HUPCL   0002000\n#define CLOCAL  0004000\n\n#define IEXTEN  0100000\n\n/* tcflow() and TCXONC use these */\n#define TCOOFF          0\n#define TCOON           1\n#define TCIOFF          2\n#define TCION           3\n\n/* tcflush() and TCFLSH use these */\n#define TCIFLUSH        0\n#define TCOFLUSH        1\n#define TCIOFLUSH       2\n\n/* tcsetattr uses these */\n#define TCSANOW         0\n#define TCSADRAIN       1\n#define TCSAFLUSH       2\n\n#define TCSASOFT        0x10\n#define CIGNORE         0x00000001\n\n#define TIOCGETA    _IOR(i, 92, struct termios)\n#define TIOCSETA    _IOW(i, 92, struct termios)\n#define TIOCSETAW   _IOW(i, 92, struct termios)\n#define TIOCSETAF   _IOW(i, 92, struct termios)\n\n#endif\n"
  },
  {
    "path": "include/time.h",
    "content": "/*\n * Copyright (c) 1983, 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#ifndef _TIME_H\n#define _TIME_H\n\n#ifndef NULL\n#define NULL    0\n#endif\n\n#ifndef _TIME_T\n#define _TIME_T\ntypedef long time_t;\n#endif\n\n#ifndef _SIZE_T\n#define _SIZE_T\ntypedef unsigned size_t;\n#endif\n\n/*\n * Structure returned by gmtime and localtime calls (see ctime(3)).\n */\nstruct tm {\n    int     tm_sec;\n    int     tm_min;\n    int     tm_hour;\n    int     tm_mday;\n    int     tm_mon;\n    int     tm_year;\n    int     tm_wday;\n    int     tm_yday;\n    int     tm_isdst;\n    long    tm_gmtoff;\n    char    *tm_zone;\n};\n\nstruct tm *gmtime(const time_t *);\nstruct tm *localtime(const time_t *);\nchar *asctime(const struct tm *);\nchar *ctime(const time_t *);\ntime_t time(time_t *);\n\nsize_t strftime (char *s, size_t maxsize, const char *format,\n    const struct tm *timeptr);\n\n#endif\n"
  },
  {
    "path": "include/ttyent.h",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\nstruct ttyent {             /* see getttyent(3) */\n    char    *ty_name;       /* terminal device name */\n    char    *ty_getty;      /* command to execute, usually getty */\n    char    *ty_type;       /* terminal type for termcap (3X) */\n    int     ty_status;      /* status flags (see below for defines) */\n    char    *ty_window;     /* command to start up window manager */\n    char    *ty_comment;    /* usually the location of the terminal */\n};\n\n#define TTY_ON      0x1     /* enable logins (startup getty) */\n#define TTY_SECURE  0x2     /* allow root to login */\n\nstruct ttyent *getttyent (void);\nstruct ttyent *getttynam (const char *name);\nvoid setttyent (void);\nvoid endttyent (void);\n"
  },
  {
    "path": "include/tzfile.h",
    "content": "/*\n *  @(#)tzfile.h    5.2.1 (2.11BSD) 1996/11/29\n */\n\n/*\n** Information about time zone files.\n*/\n            /* Time zone object file directory */\n#define TZDIR       \"/usr/share/zoneinfo\"\n#define TZDEFAULT   \"/etc/localtime\"\n\n/*\n** Each file begins with. . .\n*/\nstruct tzhead {\n    char    tzh_reserved[32];   /* reserved for future use */\n    char    tzh_timecnt[4];     /* coded number of transition times */\n    char    tzh_typecnt[4];     /* coded number of local time types */\n    char    tzh_charcnt[4];     /* coded number of abbr. chars */\n};\n\n/*\n** . . .followed by. . .\n**\n**  tzh_timecnt (char [4])s         coded transition times a la time(2)\n**  tzh_timecnt (unsigned char)s    types of local time starting at above\n**  tzh_typecnt repetitions of\n**      one (char [4])              coded GMT offset in seconds\n**      one (unsigned char)         used to set tm_isdt\n**      one (unsigned char)         that's an abbreviation list index\n**  tzh_charcnt (char)s             '\\0'-terminated zone abbreviaton strings\n*/\n\n/*\n** In the current implementation, \"tzset()\" refuses to deal with files that\n** exceed any of the limits below.\n*/\n\n/*\n** The TZ_MAX_TIMES value below is enough to handle a bit more than a\n** year's worth of solar time (corrected daily to the nearest second) or\n** 138 years of Pacific Presidential Election time\n** (where there are three time zone transitions every fourth year).\n*/\n#define TZ_MAX_TIMES    370\n\n#define NOSOLAR             /* We currently don't handle solar time */\n\n#ifndef NOSOLAR\n#define TZ_MAX_TYPES    256 /* Limited by what (unsigned char)'s can hold */\n#else /* !NOSOLAR */\n#define TZ_MAX_TYPES    10  /* Maximum number of local time types */\n#endif /* !NOSOLAR */\n\n#define TZ_MAX_CHARS    50  /* Maximum number of abbreviation characters */\n\n#define SECS_PER_MIN    60\n#define MINS_PER_HOUR   60\n#define HOURS_PER_DAY   24\n#define DAYS_PER_WEEK   7\n#define DAYS_PER_NYEAR  365\n#define DAYS_PER_LYEAR  366\n#define SECS_PER_HOUR   (SECS_PER_MIN * MINS_PER_HOUR)\n#define SECS_PER_DAY    ((long) SECS_PER_HOUR * HOURS_PER_DAY)\n#define MONS_PER_YEAR   12\n\n#define TM_SUNDAY       0\n#define TM_MONDAY       1\n#define TM_TUESDAY      2\n#define TM_WEDNESDAY    3\n#define TM_THURSDAY     4\n#define TM_FRIDAY       5\n#define TM_SATURDAY     6\n\n#define TM_JANUARY      0\n#define TM_FEBRUARY     1\n#define TM_MARCH        2\n#define TM_APRIL        3\n#define TM_MAY          4\n#define TM_JUNE         5\n#define TM_JULY         6\n#define TM_AUGUST       7\n#define TM_SEPTEMBER    8\n#define TM_OCTOBER      9\n#define TM_NOVEMBER     10\n#define TM_DECEMBER     11\n#define TM_SUNDAY       0\n\n#define TM_YEAR_BASE    1900\n\n#define EPOCH_YEAR      1970\n#define EPOCH_WDAY      TM_THURSDAY\n\n/*\n** Accurate only for the past couple of centuries;\n** that will probably do.\n*/\n#define isleap(y)   ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0)\n"
  },
  {
    "path": "include/unistd.h",
    "content": "/*-\n * Copyright (c) 1991, 1993, 1994\n *      The Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *      This product includes software developed by the University of\n *      California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n/*\n * Modified for 2.11BSD by removing prototypes.  To save time and space\n * functions not returning 'int' and functions not present in the system\n * are not listed.\n*/\n\n#ifndef _UNISTD_H_\n#define _UNISTD_H_\n\n#include <sys/types.h>\n\n#define STDIN_FILENO    0       /* standard input file descriptor */\n#define STDOUT_FILENO   1       /* standard output file descriptor */\n#define STDERR_FILENO   2       /* standard error file descriptor */\n\n#ifndef NULL\n#define NULL            0       /* null pointer constant */\n#endif\n\n/* Values for the second argument to access.\n   These may be OR'd together.  */\n#define R_OK            4       /* Test for read permission.  */\n#define W_OK            2       /* Test for write permission.  */\n#define X_OK            1       /* Test for execute permission.  */\n#define F_OK            0       /* Test for existence.  */\n\nvoid    _exit (int);\nint     access();\nunsigned int alarm();\npid_t   fork();\ngid_t   getegid();\nuid_t   geteuid();\ngid_t   getgid();\nchar    *getlogin();\npid_t   getpgrp();\npid_t   getpid();\npid_t   getppid();\nuid_t   getuid();\noff_t   lseek();\nssize_t read();\nunsigned int    sleep();\nchar    *ttyname();\nssize_t write (int fd, const void *buf, size_t count);\nint     truncate (const char *path, off_t length);\nint     ftruncate (int fd, off_t length);\n\nvoid    *brk (const void *addr);\nint     _brk (const void *addr);\nchar    *crypt();\nvoid    endusershell();\nlong    gethostid();\nchar    *getpass();\nchar    *getusershell();\nchar    *getwd();\nvoid    psignal();\nextern  char    *sys_siglist[];\nchar    *re_comp();\nvoid    *sbrk (int incr);\nint     sethostid();\nint     sethostname(char *name, int namelen);\nint     setlogin(const char *name);\nvoid    setusershell();\nvoid    sync();\nint     fsync(int fd);\nunsigned int    ualarm();\nvoid    usleep();\nint     pause (void);\npid_t   vfork();\n\nint     pipe (int pipefd[2]);\nint     close (int fd);\nint     dup (int oldfd);\nint     dup2 (int oldfd, int newfd);\nint     unlink (const char *pathname);\nint     link (const char *oldpath, const char *newpath);\nint     symlink (const char *, const char *);\nssize_t readlink (const char *path, char *buf, size_t bufsiz);\nint     chown (const char *path, uid_t owner, gid_t group);\nint     nice (int inc);\nint     setuid (uid_t uid);\nint     setgid (gid_t gid);\nint     seteuid (uid_t euid);\nint     setegid (gid_t egid);\nint     setreuid (uid_t ruid, uid_t euid);\nint     setregid (gid_t rgid, gid_t egid);\nint     setpgrp (pid_t pid, pid_t pgrp);\nint     isatty (int fd);\nint     chdir (const char *path);\nint     fchdir (int fd);\nint     fchown (int fd, uid_t owner, gid_t group);\nint     chflags (const char *path, u_long flags);\nint     chroot (const char *);\nint     fchflags (int fd, u_long flags);\nint     getgroups (int size, gid_t list[]);\nint     getgrouplist (char *name, gid_t basegid, gid_t *groups, int *ngroups);\nint     initgroups (const char *, gid_t);\nint     gethostname (char *name, size_t namelen);\nint     getdtablesize (void);\nint     getpagesize (void);\nint     rmdir (const char *pathname);\nint     reboot(int howto);\nmode_t  getmode(void *set, mode_t mode);\nvoid    *setmode(char *mode_str);\n\nstruct stat;\nint     stat (const char *path, struct stat *buf);\nint     fstat (int fd, struct stat *buf);\nint     lstat (const char *path, struct stat *buf);\n\nint     execl (const char *path, const char *arg0, ... /* NULL */);\nint     execle (const char *path, const char *arg0, ... /* NULL, char *envp[] */);\nint     execlp (const char *file, const char *arg0, ... /* NULL */);\n\nint     execv (const char *path, char *const argv[]);\nint     execve (const char *path, char *const arg0[], char *const envp[]);\nint     execvp (const char *file, char *const argv[]);\n\nextern  char    **environ;              /* Environment, from crt0. */\nextern  const char *__progname;         /* Program name, from crt0. */\n\nint     getopt (int argc, char * const argv[], const char *optstring);\n\nextern  char    *optarg;                /* getopt(3) external variables */\nextern  int     opterr, optind, optopt;\n\n#ifndef _VA_LIST_\n# ifdef __GNUC__\n#  define va_list   __builtin_va_list   /* For Gnu C */\n# endif\n# ifdef __SMALLER_C__\n#  define va_list   char *              /* For Smaller C */\n# endif\n#endif\n\nvoid    err (int eval, const char *fmt, ...);\nvoid    errx (int eval, const char *fmt, ...);\nvoid    warn (const char *fmt, ...);\nvoid    warnx (const char *fmt, ...);\nvoid    verr (int eval, const char *fmt, va_list ap);\nvoid    verrx (int eval, const char *fmt, va_list ap);\nvoid    vwarn (const char *fmt, va_list ap);\nvoid    vwarnx (const char *fmt, va_list ap);\n\n#ifndef _VA_LIST_\n# undef va_list\n#endif\n#endif /* !_UNISTD_H_ */\n"
  },
  {
    "path": "include/utmp.h",
    "content": "/*\n * Copyright (c) 1988 The Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that the above copyright notice and this paragraph are\n * duplicated in all such forms and that any documentation,\n * advertising materials, and other materials related to such\n * distribution and use acknowledge that the software was developed\n * by the University of California, Berkeley.  The name of the\n * University may not be used to endorse or promote products derived\n * from this software without specific prior written permission.\n * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n */\n\n#define UT_NAMESIZE 15\n#define UT_LINESIZE 8\n#define UT_HOSTSIZE 16\n\nstruct utmp {\n    char    ut_line[UT_LINESIZE];\n    char    ut_name[UT_NAMESIZE];\n    char    ut_host[UT_HOSTSIZE];\n    long    ut_time;\n};\n"
  },
  {
    "path": "include/vmf.h",
    "content": "/*      Program Name:   vmf.h\n *      Author:  S.M. Schultz\n *\n *      -----------   Modification History   ------------\n *      Version Date        Reason For Modification\n *      1.0     01Jan80     1. Initial release.\n *      2.0     31Mar83     2. Cleanup.\n *      3.0     08Sep93     3. Change v_foffset to off_t instead of int.\n *      3.1     21Oct93     4. Create union member of structure to\n *                             make 'int' or 'char' access to data easy.\n *                             Define segment+offset and modified macros.\n *                             Place into the public domain.\n *      --------------------------------------------------\n */\n#include <sys/types.h>\n\n#define MAXSEGNO    16384       /* max number of segments in a space */\n#define BYTESPERSEG 1024        /* must be power of two! */\n#define LOG2BPS     10          /* log2(BYTESPERSEG) */\n#define WORDSPERSEG (BYTESPERSEG/sizeof (int))\n\nstruct vspace {\n    int     v_fd;               /* file for swapping */\n    off_t   v_foffset;          /* offset for computing file addresses */\n    int     v_maxsegno;         /* number of segments in this space */\n};\n\nstruct dlink {                  /* general double link structure */\n    struct dlink *fwd;          /* forward link */\n    struct dlink *back;         /* back link */\n};\n\nstruct  vseg {                  /* structure of a segment in memory */\n    struct  dlink   s_link;     /* for linking into lru list */\n    int     s_segno;            /* segment number */\n    struct  vspace  *s_vspace;  /* which virtual space */\n    int     s_lock_count;\n    int     s_flags;\n    union {\n        int     _winfo[WORDSPERSEG];    /* the actual segment */\n        char    _cinfo[BYTESPERSEG];\n    } v_un;\n};\n\n#define s_winfo v_un._winfo\n#define s_cinfo v_un._cinfo\n\n/* masks for s_flags */\n#define S_DIRTY     01          /* segment has been modified */\n\nlong    nswaps;                 /* number of swaps */\nlong    nmapsegs;               /* number of mapseg calls */\n\nint vminit(), vmopen();\nstruct  vseg    *vmmapseg();\nvoid    vmlock(), vmunlock(), vmclrseg(), vmmodify();\nvoid    vmflush(), vmclose();\n\ntypedef long    VADDR;\n\n#define VMMODIFY(seg) (seg->s_flags |= S_DIRTY)\n#define VSEG(va) ((short)(va >> LOG2BPS))\n#define VOFF(va) ((u_short)va % BYTESPERSEG)\n"
  },
  {
    "path": "include/wiznet/client.h",
    "content": "#ifndef client_h\n#define client_h\n\nstruct _client_t {\n    unsigned sock;\n    uint8_t *ip;\n    unsigned port;\n};\ntypedef struct _client_t client_t;\n\nextern unsigned _client_srcport;\n\nvoid client_init (client_t *c, uint8_t *ip, unsigned port);\nvoid client_init_sock (client_t *c, unsigned sock);\n\nunsigned client_status (client_t *);\nint client_connect (client_t *);\nvoid client_putc (client_t *, uint8_t);\nvoid client_puts (client_t *c, const char *str);\nvoid client_write (client_t *c, const uint8_t *buf, unsigned size);\nint client_available (client_t *);\nint client_getc (client_t *);\nint client_read (client_t *c, uint8_t *buf, unsigned size);\nint client_peek (client_t *);\nvoid client_flush (client_t *);\nvoid client_stop (client_t *);\nint client_connected (client_t *);\n\n#endif\n"
  },
  {
    "path": "include/wiznet/ethernet.h",
    "content": "#ifndef ethernet_h\n#define ethernet_h\n\n#include <stdint.h>\n#include \"client.h\"\n#include \"server.h\"\n\n#define MAX_SOCK_NUM 4\n\nvoid ethernet_init (void);\n\n#endif\n"
  },
  {
    "path": "include/wiznet/server.h",
    "content": "#ifndef server_h\n#define server_h\n\n#include \"client.h\"\n\nextern unsigned _server_port;\n\nvoid server_init (unsigned port);\n\nint server_available (client_t *);\nvoid server_accept (void);\nvoid server_putc (uint8_t byte);\nvoid server_puts (const char *str);\nvoid server_write (const uint8_t *buf, unsigned size);\n\n#endif\n"
  },
  {
    "path": "include/wiznet/socket.h",
    "content": "#ifndef _SOCKET_H_\n#define _SOCKET_H_\n\n#include \"w5100.h\"\n\nextern unsigned _socket_port [MAX_SOCK_NUM];\n\n/*\n * Opens a socket(TCP or UDP or IP_RAW mode)\n */\nunsigned socket_init (unsigned sock, unsigned protocol, unsigned port, unsigned flag);\n\n/*\n * Close socket\n */\nvoid socket_close (unsigned sock);\n\n/*\n * Establish TCP connection (Active connection)\n */\nunsigned socket_connect (unsigned sock, uint8_t *addr, unsigned port);\n\n/*\n * disconnect the connection\n */\nvoid socket_disconnect (unsigned sock);\n\n/*\n * Establish TCP connection (Passive connection)\n */\nunsigned socket_listen (unsigned sock);\n\n/*\n * Send data (TCP)\n */\nunsigned socket_send (unsigned sock, const uint8_t *buf, unsigned len);\n\n/*\n * Receive data (TCP)\n */\nunsigned socket_recv (unsigned sock, uint8_t *buf, unsigned len);\nunsigned socket_peek (unsigned sock);\n\n/*\n * Send data (UDP/IP RAW)\n */\nunsigned socket_sendto (unsigned sock, const uint8_t *buf, unsigned len, uint8_t *addr, unsigned port);\n\n/*\n * Receive data (UDP/IP RAW)\n */\nunsigned socket_recvfrom (unsigned sock, uint8_t *buf, unsigned len, uint8_t *addr, unsigned *port);\n\nunsigned socket_igmpsend (unsigned sock, const uint8_t *buf, unsigned len);\n\n#endif /* _SOCKET_H_ */\n"
  },
  {
    "path": "include/wiznet/udp.h",
    "content": "/*\n * Udp.cpp: Library to send/receive UDP packets with the Arduino ethernet shield.\n * This version only offers minimal wrapping of socket.c/socket.h\n *\n * NOTE: UDP is fast, but has some important limitations (thanks to Warren Gray for mentioning these)\n * 1) UDP does not guarantee the order in which assembled UDP packets are received. This\n * might not happen often in practice, but in larger network topologies, a UDP\n * packet can be received out of sequence.\n * 2) UDP does not guard against lost packets - so packets *can* disappear without the sender being\n * aware of it. Again, this may not be a concern in practice on small local networks.\n * For more information, see http://www.cafeaulait.org/course/week12/35.html\n *\n * MIT License:\n * Copyright (c) 2008 Bjoern Hartmann\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\n * bjoern@cs.stanford.edu 12/30/2008\n */\n#ifndef udp_h\n#define udp_h\n\n#define UDP_TX_PACKET_MAX_SIZE 24\n\nstruct _udp_t {\n    unsigned port;      // local port to listen on\n    unsigned sock;      // socket ID for Wiz5100\n};\ntypedef struct _udp_t udp_t;\n\n/*\n * Initialize, start listening on specified port.\n * Returns 1 if successful, 0 if there are no sockets available to use.\n */\nint udp_init (udp_t *u, unsigned port);\n\n/*\n * Has data been received?\n */\nunsigned udp_available (udp_t *u);\n\n/*\n * Finish with the UDP socket.\n */\nvoid udp_stop (udp_t *u);\n\n/*\n * Send a packet to specified peer.\n */\nunsigned udp_send_packet (udp_t *u, const uint8_t *data, unsigned len,\n                          uint8_t *ip, unsigned port);\n\n/*\n * Send a zero-terminated string to specified peer.\n */\nunsigned udp_send_string (udp_t *u, const char *data,\n                          uint8_t *ip, unsigned port);\n\n/*\n * Read a received packet, also return sender's ip and port.\n */\nint udp_read_packet (udp_t *u, uint8_t *buf, unsigned len, uint8_t *ip, unsigned *port);\n\n#endif\n"
  },
  {
    "path": "include/wiznet/w5100.h",
    "content": "/*\n * Copyright (c) 2010 by Cristian Maglie <c.maglie@bug.st>\n *\n * This file is free software; you can redistribute it and/or modify\n * it under the terms of either the GNU General Public License version 2\n * or the GNU Lesser General Public License version 2.1, both as\n * published by the Free Software Foundation.\n *\n * Updated  August/3/2011 by Lowell Scott Hanson to be compatable with chipKIT boards\n * Updated  April/13/2012 by Serge Vakulenko for RetroBSD project\n */\n#ifndef W5100_H_INCLUDED\n#define W5100_H_INCLUDED\n\n#include <stdint.h>\n\n#define MAX_SOCK_NUM    4\n\n/*\n * Common Mode Register.\n */\n#define MR_IND          0x01    /* Indirect bus interface mode */\n#define MR_AI           0x02    /* Address auto-increment for indirect mode */\n#define MR_PPPoE        0x08    /* PPPoE mode */\n#define MR_PB           0x10    /* Ping block mode */\n#define MR_RST          0x80    /* Software reset */\n\n/*\n * Socket Mode Register.\n */\n#define SnMR_CLOSE      0x00\n#define SnMR_TCP        0x01\n#define SnMR_UDP        0x02\n#define SnMR_IPRAW      0x03\n#define SnMR_MACRAW     0x04\n#define SnMR_PPPOE      0x05\n#define SnMR_ND         0x20    /* No delayed ACK */\n#define SnMR_MULTI      0x80    /* Enable multicasting */\n\n/*\n * Socket Command Register.\n */\n#define Sock_OPEN       0x01\n#define Sock_LISTEN     0x02\n#define Sock_CONNECT    0x04\n#define Sock_DISCON     0x08\n#define Sock_CLOSE      0x10\n#define Sock_SEND       0x20\n#define Sock_SEND_MAC   0x21\n#define Sock_SEND_KEEP  0x22\n#define Sock_RECV       0x40\n\n/*\n * Socket Interrupt Register.\n */\n#define SnIR_SEND_OK    0x10\n#define SnIR_TIMEOUT    0x08\n#define SnIR_RECV       0x04\n#define SnIR_DISCON     0x02\n#define SnIR_CON        0x01\n\n/*\n * Socket Status Register.\n */\n#define SnSR_CLOSED     0x00\n#define SnSR_INIT       0x13\n#define SnSR_LISTEN     0x14\n#define SnSR_SYNSENT    0x15\n#define SnSR_SYNRECV    0x16\n#define SnSR_ESTABLISHED 0x17\n#define SnSR_FIN_WAIT   0x18\n#define SnSR_CLOSING    0x1A\n#define SnSR_TIME_WAIT  0x1B\n#define SnSR_CLOSE_WAIT 0x1C\n#define SnSR_LAST_ACK   0x1D\n#define SnSR_UDP        0x22\n#define SnSR_IPRAW      0x32\n#define SnSR_MACRAW     0x42\n#define SnSR_PPPOE      0x5F\n\n#define TXBUF_SIZE      2048    // Max Tx buffer size\n#define RXBUF_SIZE      2048    // Max Rx buffer size\n\n#define CH_BASE         0x0400\n#define CH_SIZE         0x0100\n\n/*----------------------------------------------\n * W5100 Registers\n */\nunsigned w5100_write_byte (unsigned addr, int byte);\nunsigned w5100_write (unsigned addr, const uint8_t *buf, unsigned len);\nunsigned w5100_read_byte (unsigned addr);\nunsigned w5100_read (unsigned addr, uint8_t *buf, unsigned len);\n\n#define __GP_REGISTER8(name, address)                           \\\n    static inline void w5100_write##name (unsigned data) {      \\\n        w5100_write_byte (address, data);                       \\\n    }                                                           \\\n    static inline unsigned w5100_read##name() {                 \\\n        return w5100_read_byte (address);                       \\\n    }\n#define __GP_REGISTER16(name, address)                          \\\n    static inline void w5100_write##name(unsigned data) {       \\\n        w5100_write_byte (address,   data >> 8);                \\\n        w5100_write_byte (address+1, data & 0xFF);              \\\n    }                                                           \\\n    static inline unsigned w5100_read##name() {                 \\\n        unsigned res = w5100_read_byte (address);               \\\n        res = (res << 8) + w5100_read_byte (address + 1);       \\\n        return res;                                             \\\n    }\n#define __GP_REGISTER_N(name, address, size)                    \\\n    static inline unsigned w5100_write##name(uint8_t *buff) {   \\\n        return w5100_write(address, buff, size);                \\\n    }                                                           \\\n    static inline unsigned w5100_read##name(uint8_t *buff) {    \\\n        return w5100_read(address, buff, size);                 \\\n    }\n\n__GP_REGISTER8 (MR,     0x0000);    // Mode\n__GP_REGISTER_N(GAR,    0x0001, 4); // Gateway IP address\n__GP_REGISTER_N(SUBR,   0x0005, 4); // Subnet mask address\n__GP_REGISTER_N(SHAR,   0x0009, 6); // Source MAC address\n__GP_REGISTER_N(SIPR,   0x000F, 4); // Source IP address\n__GP_REGISTER8 (IR,     0x0015);    // Interrupt\n__GP_REGISTER8 (IMR,    0x0016);    // Interrupt Mask\n__GP_REGISTER16(RTR,    0x0017);    // Timeout address\n__GP_REGISTER8 (RCR,    0x0019);    // Retry count\n__GP_REGISTER8 (RMSR,   0x001A);    // Receive memory size\n__GP_REGISTER8 (TMSR,   0x001B);    // Transmit memory size\n__GP_REGISTER8 (PATR,   0x001C);    // Authentication type address in PPPoE mode\n__GP_REGISTER8 (PTIMER, 0x0028);    // PPP LCP Request Timer\n__GP_REGISTER8 (PMAGIC, 0x0029);    // PPP LCP Magic Number\n__GP_REGISTER_N(UIPR,   0x002A, 4); // Unreachable IP address in UDP mode\n__GP_REGISTER16(UPORT,  0x002E);    // Unreachable Port address in UDP mode\n\n#undef __GP_REGISTER8\n#undef __GP_REGISTER16\n#undef __GP_REGISTER_N\n\n/*----------------------------------------------\n * W5100 Socket registers\n */\nstatic inline unsigned\nw5100_readSn_byte (unsigned sock, unsigned addr)\n{\n    return w5100_read_byte (CH_BASE + sock*CH_SIZE + addr);\n}\n\nstatic inline unsigned\nw5100_writeSn_byte (unsigned sock, unsigned addr, unsigned data)\n{\n    return w5100_write_byte (CH_BASE + sock*CH_SIZE + addr, data);\n}\n\nstatic inline unsigned\nw5100_readSn (unsigned sock, unsigned addr, uint8_t *buf, unsigned len)\n{\n    return w5100_read (CH_BASE + sock*CH_SIZE + addr, buf, len);\n}\n\nstatic inline unsigned\nw5100_writeSn (unsigned sock, unsigned addr, uint8_t *buf, unsigned len)\n{\n    return w5100_write (CH_BASE + sock*CH_SIZE + addr, buf, len);\n}\n\n#define __SOCKET_REGISTER8(name, address)                                   \\\n    static inline void w5100_write##name (unsigned sock, unsigned data) {   \\\n        w5100_writeSn_byte (sock, address, data);                           \\\n    }                                                                       \\\n    static inline unsigned w5100_read##name (unsigned sock) {               \\\n        return w5100_readSn_byte (sock, address);                           \\\n    }\n#define __SOCKET_REGISTER16(name, address)                                  \\\n    static inline void w5100_write##name (unsigned sock, unsigned data) {   \\\n        w5100_writeSn_byte (sock, address,   data >> 8);                    \\\n        w5100_writeSn_byte (sock, address+1, data & 0xFF);                  \\\n    }                                                                       \\\n    static inline unsigned w5100_read##name (unsigned sock) {               \\\n        unsigned res = w5100_readSn_byte (sock, address);                   \\\n        res = (res << 8) + w5100_readSn_byte (sock, address + 1);           \\\n        return res;                                                         \\\n    }\n#define __SOCKET_REGISTER_N(name, address, size)                            \\\n    static inline unsigned w5100_write##name (unsigned sock, uint8_t *buf) { \\\n        return w5100_writeSn (sock, address, buf, size);                    \\\n    }                                                                       \\\n    static inline unsigned read##name (unsigned sock, uint8_t *buf) {       \\\n        return w5100_readSn (sock, address, buf, size);                     \\\n    }\n\n__SOCKET_REGISTER8(SnMR,        0x0000)     // Mode\n__SOCKET_REGISTER8(SnCR,        0x0001)     // Command\n__SOCKET_REGISTER8(SnIR,        0x0002)     // Interrupt\n__SOCKET_REGISTER8(SnSR,        0x0003)     // Status\n__SOCKET_REGISTER16(SnPORT,     0x0004)     // Source Port\n__SOCKET_REGISTER_N(SnDHAR,     0x0006, 6)  // Destination Hardw Addr\n__SOCKET_REGISTER_N(SnDIPR,     0x000C, 4)  // Destination IP Addr\n__SOCKET_REGISTER16(SnDPORT,    0x0010)     // Destination Port\n__SOCKET_REGISTER16(SnMSSR,     0x0012)     // Max Segment Size\n__SOCKET_REGISTER8(SnPROTO,     0x0014)     // Protocol in IP RAW Mode\n__SOCKET_REGISTER8(SnTOS,       0x0015)     // IP TOS\n__SOCKET_REGISTER8(SnTTL,       0x0016)     // IP TTL\n__SOCKET_REGISTER16(SnTX_FSR,   0x0020)     // TX Free Size\n__SOCKET_REGISTER16(SnTX_RD,    0x0022)     // TX Read Pointer\n__SOCKET_REGISTER16(SnTX_WR,    0x0024)     // TX Write Pointer\n__SOCKET_REGISTER16(SnRX_RSR,   0x0026)     // RX Free Size\n__SOCKET_REGISTER16(SnRX_RD,    0x0028)     // RX Read Pointer\n__SOCKET_REGISTER16(SnRX_WR,    0x002A)     // RX Write Pointer (supported?)\n\n#undef __SOCKET_REGISTER8\n#undef __SOCKET_REGISTER16\n#undef __SOCKET_REGISTER_N\n\n/*----------------------------------------------\n * W5100 functions\n */\nvoid w5100_init();\n\n/*\n * This function is being used for copy the data form Receive buffer\n * of the chip to application buffer.\n *\n * It calculate the actual physical address where one has to read\n * the data from Receive buffer. Here also take care of the condition\n * while it exceed the Rx memory uper-bound of socket.\n */\nvoid w5100_read_data (unsigned sock, unsigned src, uint8_t *dst, unsigned len);\n\n/*\n * This function is being called by send() and sendto() function also.\n *\n * This function read the Tx write pointer register and after copy the data\n * in buffer update the Tx write pointer register.\n */\nvoid w5100_send_chunk (unsigned sock, const uint8_t *data, unsigned len);\n\n/*\n * This function is being called by recv() also.\n *\n * This function read the Rx read pointer register and after copy\n * the data from receive buffer update the Rx write pointer register.\n */\nvoid w5100_recv_chunk (unsigned sock, uint8_t *data, unsigned len);\n\nunsigned w5100_recv_peek (unsigned sock);\n\nvoid w5100_socket_cmd (unsigned sock, int cmd);\n\nunsigned w5100_getTXFreeSize (unsigned sock);\nunsigned w5100_getRXReceivedSize (unsigned sock);\n\n/*\n * Debug output.\n */\n//#define W5100_DEBUG printf\n#ifndef W5100_DEBUG\n#   define W5100_DEBUG(...) /* empty */\n#endif\n\n#endif\n"
  },
  {
    "path": "lib/Makefile",
    "content": "#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\nTOPSRC!=cd ..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nSUBDIR=\tlibc_aout \\\n\tstartup-${MACHINE_ARCH} libc libm libcurses libtermlib \\\n\tlibutil libvmf libtcl libreadline libgpanel libwiznet\n\nall:\t\t$(SUBDIR)\n\n$(SUBDIR):\tFRC\n\t\t$(MAKE) -C $@\n\nFRC:\n\ninstall:        elf32-$(MACHINE_ARCH).ld\n\t\t-for i in $(SUBDIR); do \\\n\t\t\t${MAKE} -C $$i DESTDIR=${DESTDIR} install; done\n#\t\tcp -p elf32-$(MACHINE_ARCH).ld $(DESTDIR)/usr/lib/elf32-$(MACHINE_ARCH).ld\n\nclean:\n\t\trm -f a.out core *.s *.o *.a *~\n\t\t-for i in $(SUBDIR); do $(MAKE) -C $$i clean; done\n"
  },
  {
    "path": "lib/elf32-arm.ld",
    "content": "/* Script for -z combreloc: combine and sort reloc sections */\n/* Copyright (C) 2014-2016 Free Software Foundation, Inc.\n   Copying and distribution of this script, with or without modification,\n   are permitted in any medium without royalty provided the copyright\n   notice and this notice are preserved.  */\n/*\n * Linker script for user executables.\n */\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-bigarm\",\n\t      \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_start)\nSEARCH_DIR(\"/usr/local/arm-none-eabi/lib\");\nSECTIONS\n{\n  /* Read-only sections, merged into text segment: */\n/* XXX PROVIDE (__executable_start = SEGMENT_START(\"text-segment\", 0x8000)); . = SEGMENT_START(\"text-segment\", 0x8000); */\n  PROVIDE (__executable_start = 0x20000000); . = 0x20000000;\n  .interp         : { *(.interp) }\n  .note.gnu.build-id : { *(.note.gnu.build-id) }\n  .hash           : { *(.hash) }\n  .gnu.hash       : { *(.gnu.hash) }\n  .dynsym         : { *(.dynsym) }\n  .dynstr         : { *(.dynstr) }\n  .gnu.version    : { *(.gnu.version) }\n  .gnu.version_d  : { *(.gnu.version_d) }\n  .gnu.version_r  : { *(.gnu.version_r) }\n  .rel.dyn        :\n    {\n      *(.rel.init)\n      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)\n      *(.rel.fini)\n      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)\n      *(.rel.data.rel.ro .rel.data.rel.ro.* .rel.gnu.linkonce.d.rel.ro.*)\n      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)\n      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)\n      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)\n      *(.rel.ctors)\n      *(.rel.dtors)\n      *(.rel.got)\n      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)\n      PROVIDE_HIDDEN (__rel_iplt_start = .);\n      *(.rel.iplt)\n      PROVIDE_HIDDEN (__rel_iplt_end = .);\n    }\n  .rela.dyn       :\n    {\n      *(.rela.init)\n      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)\n      *(.rela.fini)\n      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)\n      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)\n      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)\n      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)\n      *(.rela.ctors)\n      *(.rela.dtors)\n      *(.rela.got)\n      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)\n      PROVIDE_HIDDEN (__rela_iplt_start = .);\n      *(.rela.iplt)\n      PROVIDE_HIDDEN (__rela_iplt_end = .);\n    }\n  .rel.plt        :\n    {\n      *(.rel.plt)\n    }\n  .rela.plt       :\n    {\n      *(.rela.plt)\n    }\n  .init           :\n  {\n    KEEP (*(SORT_NONE(.init)))\n  }\n  .plt            : { *(.plt) }\n  .iplt           : { *(.iplt) }\n  .text           :\n  {\n    *(.text.unlikely .text.*_unlikely .text.unlikely.*)\n    *(.text.exit .text.exit.*)\n    *(.text.startup .text.startup.*)\n    *(.text.hot .text.hot.*)\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    /* .gnu.warning sections are handled specially by elf32.em.  */\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)\n  }\n  .fini           :\n  {\n    KEEP (*(SORT_NONE(.fini)))\n  }\n  PROVIDE (__etext = .);\n  PROVIDE (_etext = .);\n  PROVIDE (etext = .);\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\n  .rodata1        : { *(.rodata1) }\n/* XXX elf2aout cannot handle these optional sections.\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) }\n   PROVIDE_HIDDEN (__exidx_start = .);\n  .ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }\n   PROVIDE_HIDDEN (__exidx_end = .);\nXXX */\n  .eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) }\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) }\n  .gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table\n  .gcc_except_table.*) }\n  .gnu_extab   : ONLY_IF_RO { *(.gnu_extab*) }\n  /* These sections are generated by the Sun/Oracle C++ compiler.  */\n  .exception_ranges   : ONLY_IF_RO { *(.exception_ranges\n  .exception_ranges*) }\n  /* Adjust the address for the data segment.  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  {
    "path": "lib/libc/Makefile",
    "content": "#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n# Machine dependent routines are located in a subtree which parallels\n# the top directories.  This subtree is identified by the machine name.\n#\n# Compatibility routines are kept in directories with a prefixing\n# ``compat'' (so they all sort together).\n#\n# The C run-time startup code is always machine dependent and expected\n# to be located in ../startup-${MACHINE_ARCH}.\n#\n# All files contain sccsid strings, but these are not compiled into\n# library objects by default, as a space-saving measure.  To produce\n# a library that contains these strings in every object except\n# system call stubs, add -DLIBC_SCCS to DEFS below; to put these\n# strings into system call stubs, use -DSYSLIBC_SCCS.\n#\n# To compile a non-floating point versions of some standard library\n# routines add -DNONFP.  This will speed up some operations if you don't\n# have hardware floating point.  To compile a non-separate I&D version add\n# -DNONSEPARATE.\n#\nTOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nDEFS\t\t= -Wall -ffreestanding\nALL\t\t= gen stdio stdlib string inet compat ${MACHINE_ARCH}\n\nall:            ../libc.a\n\n../libc.a:      ${ALL}\n\t\trm -rf tmp\n\t\tmkdir tmp\n\t\tcd tmp; for i in ${ALL}; do $(AR) x ../$$i/$$i.a; done; \\\n\t\t\t$(AR) cr ../$@ *.o\n#\t\t\t$(AR) cr ../$@ `sh ../../cmd/lorder.sh *.o | tsort`\n\t\trm -rf tmp\n\n${ALL}:\t\tFRC\n\t\tcd $@; ${MAKE} ${MFLAGS} DEFS=\"${DEFS}\"\n\nFRC:\n\ninstall:\t../libc.a\n#\t\t${INSTALL} -d ${DESTDIR}/usr/lib\n#\t\t${INSTALL} ../libc.a ${DESTDIR}/usr/lib/libc.a\n#\t\t$(RANLIB) ${DESTDIR}/usr/lib/libc.a\n\nclean:\n\t\tfor i in ${ALL}; \\\n\t\t\tdo (cd $$i; ${MAKE} ${MFLAGS} clean); done\n\t\trm -rf tmp *.a *~\n\ndepend:\n\t\tfor i in ${ALL}; \\\n\t\t\tdo (cd $$i; ${MAKE} ${MFLAGS} DEFS=\"${DEFS}\" depend); done\n"
  },
  {
    "path": "lib/libc/arm/Makefile",
    "content": "#\n# Copyright (c) 1987 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n# Machine dependent routines for the Arm are located here\n#\nTOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nALL\t\t= gen string sys\n\narm.a:\t\t${ALL}\n\t\t-mkdir tmp\n\t\tfor i in ${ALL}; do (cd tmp; $(AR) x ../$$i/$$i.a); done\n\t\t$(AR) cr arm.a `ls tmp/*.o | sort`\n\t\trm -rf tmp\n\n${ALL}:\tFRC\n\tcd $@; ${MAKE} ${MFLAGS} DEFS=\"${DEFS}\"\n\nFRC:\n\ntags:\n\t\tfor i in ${ALL}; do \\\n\t\t\t(cd $$i; ${MAKE} ${MFLAGS} TAGSFILE=../${TAGSFILE} tags); \\\n\t\tdone\n\nclean:\n\t\tfor i in ${ALL}; do (cd $$i; ${MAKE} ${MFLAGS} clean); done\n\t\trm -rf *.a tmp *~\n\ndepend:\n\t\tfor i in ${ALL}; do \\\n\t\t\t(cd $$i; ${MAKE} ${MFLAGS} DEFS=\"${DEFS}\" depend); done\n"
  },
  {
    "path": "lib/libc/arm/gen/Makefile",
    "content": "#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\nTOPSRC!=cd ../../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS\t\t+= ${DEFS}\n\nSRCS\t\t= _setjmp.S htonl.S htons.S setjmp.S sigsetjmp.S\nOBJS\t\t= _setjmp.o htonl.o htons.o setjmp.o sigsetjmp.o\n\ngen.a:\t\t${OBJS}\n\t\t@echo \"building gen.a\"\n\t\t@${AR} cr gen.a ${OBJS}\n\ntags:\n\t\tcwd=`pwd`; \\\n\t\tfor i in ${SRCS}; do \\\n\t\t\tctags -a -f ${TAGSFILE} $$cwd/$$i; \\\n\t\tdone\n\nclean:\n\t\trm -f gen.a *.o *~ profiled/*.o tags Makefile.bak\n\ndepend:\n\t\tfor i in ${SRCS}; do \\\n\t\t    cc -M ${CFLAGS} $$i | awk ' { if ($$1 != prev) \\\n\t\t\t{ if (rec != \"\") print rec; rec = $$0; prev = $$1; } \\\n\t\t\telse { if (length(rec $$2) > 78) { print rec; rec = $$0; } \\\n\t\t\telse rec = rec \" \" $$2 } } \\\n\t\t\tEND { print rec } ' >> makedep; done\n\t\techo '/^# DO NOT DELETE THIS LINE/+2,$$d' >eddep\n\t\techo '$$r makedep' >>eddep\n\t\techo 'w' >>eddep\n\t\tcp Makefile Makefile.bak\n\t\ted - Makefile < eddep\n\t\trm eddep makedep\n\t\techo '# DEPENDENCIES MUST END AT END OF FILE' >> Makefile\n\t\techo '# IF YOU PUT STUFF HERE IT WILL GO AWAY' >> Makefile\n\t\techo '# see make depend above' >> Makefile\n\n# DO NOT DELETE THIS LINE -- make depend uses it\n"
  },
  {
    "path": "lib/libc/arm/gen/_setjmp.S",
    "content": "/*\n * Copyright (c) 2022 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n\t.syntax\tunified\n\t.thumb\n\n/*\n * int\n * _setjmp(jmp_buf env);\n */\n\t.text\n\t.align\t2\n\t.thumb_func\n\t.globl\t_setjmp\n\t.type\t_setjmp, %function\n_setjmp:\n\tmovs\tr1, #0\t\t\t/* Not saving sigmask, env[0]=0.. */\n\tstmia\tr0!, {r1}\t\t/*   so _longjmp ignores sigmask. */\n\tstmia\tr0!, {r1}\t\t/* Ignore sigmask, so env[1]=0. */\n\tmov\tip, sp\t\t\t/* Save stack pointer (via ip). */\n#ifdef __thumb2__\n\tstmia\tr0, {r4-r11,ip,lr}\t/* Save regs in env[2-11]. */\n#else /* __thumb__ */\n\tstmia\tr0!, {r4-r7}\t\t/* Save regs in env[2-5]. */\n\tmov\tr2, r8\t\t\t/* Move high regs to low.. */\n\tmov\tr3, r9\n\tmov\tr4, r10\n\tmov\tr5, r11\n\tmov\tr6, ip\n\tmov\tr7, lr\n\tstmia\tr0!, {r2-r7}\t\t/* Save regs in env[6-11]. */\n\tsubs\tr0, r0, #(10 * 4)\t/* Index back to &env[2]. */\n\tldmia\tr0!, {r4-r7}\t\t/* Bring back the low regs. */\n#endif\n\tmovs\tr0, #0\t\t\t/* Always return a 0. */\n\tbx\tlr\n\t.size\t_setjmp, . - _setjmp\n\n\n/*\n * void\n * _longjmp(jmp_buf env, int val);\n */\n\t.text\n\t.align\t2\n\t.thumb_func\n\t.globl\t_longjmp\n\t.type\t_longjmp, %function\n_longjmp:\n\tadds\tr0, r0, #(2 * 4)\t/* Skip savesigs and signal mask. */\n#ifdef __thumb2__\n\tldmia\tr0, {r4-r11,ip,lr}\t/* Restore regs from env[2-11]. */\n#else /* __thumb__ */\n\tadds\tr0, r0, #(4 * 4)\t/* Index to &env[6]. */\n\tldmia\tr0!, {r2-r7}\t\t/* Restore regs from env[6-11]. */\n\tmov\tr8, r2\t\t\t/* Move low regs to high.. */\n\tmov\tr9, r3\n\tmov\tr10, r4\n\tmov\tr11, r5\n\tmov\tip, r6\n\tmov\tlr, r7\n\tsubs\tr0, r0, #(10 * 4)\t/* Index back to &env[2]. */\n\tldmia\tr0!, {r4-r7}\t\t/* Restore regs from env[2-5]. */\n#endif\n\tmov\tsp, ip\t\t\t/* Restore stack pointer (via ip). */\n\tmovs\tr0, r1\t\t\t/* Return val.. */\n\tcmp\tr0, #0\t\t\t/*   but first test if val is 0.. */\n\tbne\t1f\n\tmovs\tr0, #1\t\t\t/*   and return a 1 if val is 0. */\n1:\n\tbx\tlr\n\t.size\t_longjmp, . - _longjmp\n"
  },
  {
    "path": "lib/libc/arm/gen/htonl.S",
    "content": "/*\n * Copyright (c) 2022 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n\t.syntax\tunified\n\t.thumb\n\n/*\n * uint32_t\n * htonl(uint32_t host32);\n *\n * Host order    -> Network order\n * 0x78.56.34.12 -> 0x12.34.56.78\n */\n\t.text\n\t.align\t2\n\t.thumb_func\n\t.globl\thtonl\n\t.type\thtonl, %function\nhtonl:\n\trev\tr0, r0\t\t/* Swap byte order in 32-bit word. */\n\tbx\tlr\n\t.size\thtonl, . - htonl\n\n\n/*\n * uint32_t\n * ntohl(uint32_t net32);\n *\n * Network order -> Host order\n * 0x12.34.56.78 -> 0x78.56.34.12\n */\n\t.text\n\t.align\t2\n\t.thumb_func\n\t.globl\tntohl\n\t.type\tntohl, %function\nntohl:\n\trev\tr0, r0\t\t/* Swap byte order in 32-bit word. */\n\tbx\tlr\n\t.size\tntohl, . - ntohl\n"
  },
  {
    "path": "lib/libc/arm/gen/htons.S",
    "content": "/*\n * Copyright (c) 2022 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n\t.syntax\tunified\n\t.thumb\n\n/*\n * uint16_t\n * htons(uint16_t host16);\n *\n * Host order    -> Half-word rev -> Network order\n * 0x78.56.34.12 -> 0x56.78.12.34 -> 0x00.00.12.34\n *\n * Note: host16 parameter is a half-word, but registers are 32-bit words.\n */\n\t.text\n\t.align\t2\n\t.thumb_func\n\t.globl\thtons\n\t.type\thtons, %function\nhtons:\n\trev16\tr0, r0\t\t/* Swap bytes in each half-word. */\n\tuxth\tr0, r0\t\t/* Unsigned extend half-word to word. */\n\tbx\tlr\n\t.size\thtons, . - htons\n\n\n/*\n * uint16_t\n * ntohs(uint16_t net16);\n *\n * Network order -> Half-word rev -> Host order\n * 0x12.34.56.78 -> 0x34.12.78.56 -> 0x00.00.78.56\n *\n * Note: net16 parameter is a half-word, but registers are 32-bit words.\n */\n\t.text\n\t.align\t2\n\t.thumb_func\n\t.globl\tntohs\n\t.type\tntohl, %function\nntohs:\n\trev16\tr0, r0\t\t/* Swap bytes in each half-word. */\n\tuxth\tr0, r0\t\t/* Unsigned extend half-word to word. */\n\tbx\tlr\n\t.size\tntohs, . - ntohs\n"
  },
  {
    "path": "lib/libc/arm/gen/setjmp.S",
    "content": "/*\n * Copyright (c) 2022 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n\t.syntax\tunified\n\t.thumb\n\n/*\n * int\n * setjmp(jmp_buf env);\n */\n\t.text\n\t.align\t2\n\t.thumb_func\n\t.globl\tsetjmp\n\t.type\tsetjmp, %function\nsetjmp:\n\tpush\t{lr}\t\t\t/* Save return address. */\n\tmovs\tr1, #1\t\t\t/* When saving sigmask, env[0]=1.. */\n\tstr\tr1, [r0]\t\t/*   so longjmp restores sigmask; */\n\tadds\tr0, r0, #(2 * 4)\t/*   skip over sigmask in env[1]. */\n\tmov\tr1, r0\t\t\t/* Save env for sigprocmask. */\n\tmov\tip, sp\t\t\t/* Save stack pointer (via ip). */\n#ifdef __thumb2__\n\tstmia\tr0, {r4-r11,ip,lr}\t/* Save regs in env[2-11]. */\n#else /* __thumb__ */\n\tstmia\tr0!, {r4-r7}\t\t/* Save regs in env[2-5]. */\n\tmov\tr2, r8\t\t\t/* Move high regs to low.. */\n\tmov\tr3, r9\n\tmov\tr4, r10\n\tmov\tr5, r11\n\tmov\tr6, ip\n\tmov\tr7, lr\n\tstmia\tr0!, {r2-r7}\t\t/* Save regs in env[6-11]. */\n\tsubs\tr0, r0, #(10 * 4)\t/* Index back to &env[2]. */\n\tldmia\tr0!, {r4-r7}\t\t/* Bring back the low regs. */\n#endif\n\n\tsubs\tr2, r1, #(1 * 4)\t/* &env[1] signal mask for oset. */\n\tmovs\tr1, #0\t\t\t/* Null for set. Mask is unchanged. */\n\tmovs\tr0, #1\t\t\t/* SIG_BLOCK, but how is irrelevant. */\n\tbl\tsigprocmask\t\t/* Get current sigmask into env[1]. */\n\n\tmovs\tr0, #0\t\t\t/* Always return a 0. */\n\tpop\t{pc}\t\t\t/* Return to whence we came. */\n\t.size\tsetjmp, . - setjmp\n\n\n/*\n * void\n * longjmp(jmp_buf env, int val);\n */\n\t.text\n\t.align\t2\n\t.thumb_func\n\t.globl\tlongjmp\n\t.type\tlongjmp, %function\nlongjmp:\n\tmov\tr3, r0\t\t\t/* Save env before sigprocmask. */\n\n\tmovs\tr2, #0\t\t\t/* Null for oset. */\n\tadds\tr1, r0, #(1 * 4)\t/* &env[1] signal mask for set. */\n\tmovs\tr0, #3\t\t\t/* SIG_SETMASK for how. */\n\tbl\tsigprocmask\t\t/* Restore sigmask from env[1]. */\n\n\tmov\tr0, r3\t\t\t/* Restore env after sigprocmask. */\n\n\tadds\tr0, r0, #(2 * 4)\t/* Skip savesigs and signal mask. */\n#ifdef __thumb2__\n\tldmia\tr0, {r4-r11,ip,lr}\t/* Restore regs from env[2-11]. */\n#else /* __thumb__ */\n\tadds\tr0, r0, #(4 * 4)\t/* Index to &env[6]. */\n\tldmia\tr0!, {r2-r7}\t\t/* Restore regs from env[6-11]. */\n\tmov\tr8, r2\t\t\t/* Move low regs to high.. */\n\tmov\tr9, r3\n\tmov\tr10, r4\n\tmov\tr11, r5\n\tmov\tip, r6\n\tmov\tlr, r7\n\tsubs\tr0, r0, #(10 * 4)\t/* Index back to &env[2]. */\n\tldmia\tr0!, {r4-r7}\t\t/* Restore regs from env[2-5]. */\n#endif\n\tmov\tsp, ip\t\t\t/* Restore stack pointer (via ip). */\n\tmovs\tr0, r1\t\t\t/* Return val.. */\n\tcmp\tr0, #0\t\t\t/*   but first test if val is 0.. */\n\tbne\t1f\n\tmovs\tr0, #1\t\t\t/*   and return a 1 if val is 0. */\n1:\n\tbx\tlr\n\t.size\tlongjmp, . - longjmp\n"
  },
  {
    "path": "lib/libc/arm/gen/sigsetjmp.S",
    "content": "/*\n * Copyright (c) 2022 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n\t.syntax\tunified\n\t.thumb\n\n/*\n * int\n * sigsetjmp(sigjmp_buf env, int savesigs);\n */\n\t.text\n\t.align\t2\n\t.thumb_func\n\t.globl\tsigsetjmp\n\t.type\tsigsetjmp, %function\nsigsetjmp:\n\tcmp\tr1, #0\t\t\t/* If savesigs is zero.. */\n\tbne\t1f\n\tldr\tr3, =_setjmp\t\t/*   skip signal mask handling; */\n\tbx\tr3\n1:\n\tldr\tr3, =setjmp\t\t/*   else handle signal mask. */\n\tbx\tr3\n\t.size\tsigsetjmp, . - sigsetjmp\n\n\n/*\n * void\n * siglongjmp(sigjmp_buf env, int val);\n */\n\t.text\n\t.align\t2\n\t.thumb_func\n\t.globl\tsiglongjmp\n\t.type\tsiglongjmp, %function\nsiglongjmp:\n\tldr\tr2, [r0]\t\t/* Get savesigs. */\n\tcmp\tr2, #0\t\t\t/* If savesigs was zero.. */\n\tbne\t1f\n\tldr\tr3, =_longjmp\t\t/*   skip signal mask handling; */\n\tbx\tr3\n1:\n\tldr\tr3, =longjmp\t\t/*   else handle signal mask. */\n\tbx\tr3\n\t.size\tsiglongjmp, . - siglongjmp\n"
  },
  {
    "path": "lib/libc/arm/string/Makefile",
    "content": "#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\nTOPSRC!=cd ../../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS\t\t+= ${DEFS}\n\nSRCS\t\t= memmove.S strcmp.S\nOBJS\t\t= memmove.o strcmp.o\n\nstring.a:\t${OBJS}\n\t\t@echo \"building string.a\"\n\t\t@${AR} cr string.a ${OBJS}\n\ntags:\n\t\tcwd=`pwd`; \\\n\t\tfor i in ${SRCS}; do \\\n\t\t\tctags -a -f ${TAGSFILE} $$cwd/$$i; \\\n\t\tdone\n\nclean:\n\t\trm -f string.a *.o *~ profiled/*.o tags Makefile.bak\n\ndepend:\n\t\tfor i in ${SRCS}; do \\\n\t\t    cc -M ${CFLAGS} $$i | awk ' { if ($$1 != prev) \\\n\t\t\t{ if (rec != \"\") print rec; rec = $$0; prev = $$1; } \\\n\t\t\telse { if (length(rec $$2) > 78) { print rec; rec = $$0; } \\\n\t\t\telse rec = rec \" \" $$2 } } \\\n\t\t\tEND { print rec } ' >> makedep; done\n\t\techo '/^# DO NOT DELETE THIS LINE/+2,$$d' >eddep\n\t\techo '$$r makedep' >>eddep\n\t\techo 'w' >>eddep\n\t\tcp Makefile Makefile.bak\n\t\ted - Makefile < eddep\n\t\trm eddep makedep\n\t\techo '# DEPENDENCIES MUST END AT END OF FILE' >> Makefile\n\t\techo '# IF YOU PUT STUFF HERE IT WILL GO AWAY' >> Makefile\n\t\techo '# see make depend above' >> Makefile\n\n# DO NOT DELETE THIS LINE -- make depend uses it\n"
  },
  {
    "path": "lib/libc/arm/string/memmove.S",
    "content": "/*\n * Copyright (c) 2015 ARM Ltd\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. The name of the company may not be used to endorse or promote\n *    products derived from this software without specific prior written\n *    permission.\n *\n * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED\n * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\n * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED\n * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n\t.syntax\tunified\n\t.thumb\n\n\t.text\n\t.align\t2\n\t.thumb_func\n\t.globl\tmemmove\n\t.type\tmemmove, %function\nmemmove:\n\tpush\t{r4, lr}\n\tcmp\tr0, r1\n\tbls\t3f\n\tadds\tr4, r1, r2\n\tcmp\tr0, r4\n\tbcs\t3f\n\tsubs\tr3, r2, #1\n\tcmp\tr2, #0\n\tbeq\t2f\n\tsubs\tr2, r4, r2\n1:\n\tldrb\tr1, [r2, r3]\n\tstrb\tr1, [r0, r3]\n\tsubs\tr3, r3, #1\n\tbcs\t1b\n2:\n\tpop\t{r4, pc}\n3:\n\tmovs\tr3, #0\n\tcmp\tr2, #0\n\tbeq\t2b\n4:\n\tldrb\tr4, [r1, r3]\n\tstrb\tr4, [r0, r3]\n\tadds\tr3, r3, #1\n\tcmp\tr2, r3\n\tbne\t4b\n\tb\t2b\n\t.size\tmemmove, . - memmove\n"
  },
  {
    "path": "lib/libc/arm/string/strcmp.S",
    "content": "/*\n * Copyright (c) 2012-2014 ARM Ltd\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. The name of the company may not be used to endorse or promote\n *    products derived from this software without specific prior written\n *    permission.\n *\n * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED\n * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\n * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED\n * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n\t.syntax\tunified\n\t.thumb\n\n\t.text\n\t.align\t2\n\t.thumb_func\n\t.globl\tstrcmp\n\t.type\tstrcmp, %function\nstrcmp:\n1:\n#ifdef __thumb2__\n\t/* Tiny version of strcmp in ARM state.  Used only when optimizing\n\t   for size.  Also supports Thumb-2.  */\n\tldrb\tr2, [r0], #1\n\tldrb\tr3, [r1], #1\n\tcmp\tr2, #1\n\tit\tcs\n\tcmpcs\tr2, r3\n\tbeq\t1b\n#else /* __thumb__ */\n\t/* This version is only used when we want a very basic Thumb1\n\t   implementation or for size, otherwise we use the base ARMv4\n\t   version.  This is also suitable for ARMv6-M.  */\n\tldrb\tr2, [r0]\n\tldrb\tr3, [r1]\n\tcmp\tr2, #0\n\tbeq\t2f\n\tadds\tr0, r0, #1\n\tadds\tr1, r1, #1\n\tcmp\tr2, r3\n\tbeq\t1b\n#endif\n2:\n\tsubs\tr0, r2, r3\n\tbx\tlr\n\t.size\tstrcmp, . - strcmp\n"
  },
  {
    "path": "lib/libc/arm/sys/Makefile",
    "content": "TOPSRC!=cd ../../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nASFLAGS\t\t+= ${DEFS}\nCFLAGS          += -Os\n\n# modules which can not use SYSCALL and must be assembled from sources.  The\n# rest of the system calls are generated with printf(1) and do not have\n# source files associated with them.\n\nCOBJS\t\t= sbrk.o execl.o execle.o execv.o\n\nASMOBJS\t\t= _exit.o _brk.o pipe.o ptrace.o sigaction.o\n\nSYSOBJS\t\t= __sysctl.o accept.o access.o adjtime.o bind.o chdir.o \\\n\t\t  chflags.o chmod.o chown.o chroot.o close.o connect.o dup.o \\\n\t\t  dup2.o execve.o fchdir.o fchflags.o fchmod.o fchown.o \\\n\t\t  fcntl.o flock.o fork.o fstat.o fsync.o ftruncate.o \\\n\t\t  getdtablesize.o getgroups.o getitimer.o getsockname.o \\\n\t\t  getpeername.o getpriority.o getrlimit.o getrusage.o getsockopt.o \\\n\t\t  gettimeofday.o ioctl.o kill.o killpg.o link.o listen.o lstat.o mkdir.o \\\n\t\t  mknod.o mount.o open.o pselect.o quota.o read.o readlink.o readv.o \\\n\t\t  reboot.o \\\n\t\t  recv.o recvfrom.o recvmsg.o rename.o rmdir.o select.o send.o sendmsg.o \\\n\t\t  sendto.o setgroups.o setitimer.o setpgrp.o setpriority.o setquota.o \\\n\t\t  setuid.o seteuid.o setgid.o setegid.o \\\n\t\t  setrlimit.o setsockopt.o settimeofday.o shutdown.o \\\n\t\t  sigaltstack.o socket.o socketpair.o stat.o symlink.o \\\n\t\t  sigprocmask.o sigstack.o sigwait.o \\\n\t\t  statfs.o fstatfs.o getfsstat.o \\\n\t\t  truncate.o umount.o unlink.o utimes.o wait4.o write.o writev.o \\\n\t\t  lseek.o sigsuspend.o \\\n\t\t  getgid.o getegid.o getpgrp.o getpid.o \\\n\t\t  getppid.o getuid.o geteuid.o profil.o sigpending.o sync.o \\\n                  ufetch.o ustore.o ucall.o umask.o vfork.o vhangup.o \\\n\t\t  rdglob.o wrglob.o msec.o kmemdev.o\n\nOBJS\t\t= ${COBJS} ${ASMOBJS} ${SYSOBJS}\n\nTAGSFILE\t= tags\n\nsys.a:\t\t${OBJS}\n\t\t@echo \"building sys.a\"\n\t\t@${AR} cr sys.a ${OBJS}\n\n${SYSOBJS}:\tSYS.h\n#\t\t@echo creating $*.o\n\t\t@printf '#include \"SYS.h\"\\nSYS($*)\\n' | $(AS) ${ASFLAGS} - -c -o $*.o\n\nclean:\n\t\trm -f *~ *.o a.out sys.a\n"
  },
  {
    "path": "lib/libc/arm/sys/SYS.h",
    "content": "/*\n * Copyright (c) 2022 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include <syscall.h>\n\n#define\tENTRY(x) \\\n\t.text; \\\n\t.align\t2; \\\n\t.thumb_func; \\\n\t.globl\tx; \\\n\t.type\tx, %function; \\\nx:\n\n#define\tEND(x) \\\n\t.size\tx, . - x\n\n#define\tSYS(x) \\\n\tENTRY(x); \\\n\tsvc\t#SYS_##x; \\\n\tbcs\t1f; \\\n\tbx\tlr; \\\n1:\tldr\tr1, =errno; \\\n\tstr\tr0, [r1]; \\\n\tmov\tr0, #0; \\\n\tmvn\tr0, r0; \\\n\tbx\tlr; \\\n\tEND(x)\n"
  },
  {
    "path": "lib/libc/arm/sys/_brk.S",
    "content": "/*\n * Copyright (c) 2022 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include \"SYS.h\"\n\nENTRY(_brk)\n\tsvc\t#SYS_sbrk\n\tbcs\t1f\t\t\t/* Error if carry set. */\n\tbx\tlr\t\t\t/* Success return. */\n1:\tldr\tr1, =errno\n\tstr\tr0, [r1]\n\tmov\tr0, #0\n\tmvn\tr0, r0\n\tbx\tlr\t\t\t/* Error return. */\nEND(_brk)\n"
  },
  {
    "path": "lib/libc/arm/sys/_exit.S",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"SYS.h\"\n\nENTRY(_exit)\n\tsvc\t#SYS_exit\nEND(_exit)\n"
  },
  {
    "path": "lib/libc/arm/sys/execl.c",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <unistd.h>\n\nextern char **environ;\n\nint\nexecl (const char *name, const char *arg, ...)\n{\n\treturn execve (name, (char *const*) &arg, environ);\n}\n"
  },
  {
    "path": "lib/libc/arm/sys/execle.c",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <unistd.h>\n#include <stdarg.h>\n\nint\nexecle (const char *name, const char *arg, ...)\n{\n\tva_list ap;\n\tchar **envp;\n\n\tva_start (ap, arg);\n\twhile ((va_arg (ap, char *)) != NULL)\n\t\tcontinue;\n\tenvp = va_arg (ap, char **);\n\tva_end (ap);\n\n\treturn execve (name, (char *const*) &arg, envp);\n}\n"
  },
  {
    "path": "lib/libc/arm/sys/execv.c",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <unistd.h>\n\nextern char **environ;\n\nint\nexecv (name, argv)\n\tconst char *name;\n\tchar *const *argv;\n{\n\treturn execve (name, argv, environ);\n}\n"
  },
  {
    "path": "lib/libc/arm/sys/pipe.S",
    "content": "/*\n * Copyright (c) 2022 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include \"SYS.h\"\n\nENTRY(pipe)\n\tmov\tr3, r0\t\t\t/* Copy &filedes[0] to r3. */\n\tsvc\t#SYS_pipe\n\tbcs\t1f\t\t\t/* Error if carry set. */\n\tstr\tr0, [r3, #0]\t\t/* Save read fd in &filedes[0]. */\n\tstr\tr1, [r3, #4]\t\t/* Save write fd in &filedes[1]. */\n\tmov\tr0, #0\n\tbx\tlr\t\t\t/* Success return. */\n1:\tldr\tr1, =errno\n\tstr\tr0, [r1]\n\tmov\tr0, #0\n\tmvn\tr0, r0\n\tbx\tlr\t\t\t/* Error return. */\nEND(pipe)\n"
  },
  {
    "path": "lib/libc/arm/sys/ptrace.S",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"SYS.h\"\n\nENTRY(ptrace)\n#if 0 /* XXX Arm ASM */\n\t\t# -1 is a legitimate return\n\t\t# value so we must clear errno\n\t\t# so the caller may disambiguate\n\t\tlui\t$t1, %hi(errno)\n\t\tsw      $zero, %lo(errno)($t1)\n\n\t\t.set\tnoreorder\n\t\tsyscall\tSYS_ptrace\n\t\tlui\t$t1, %hi(errno)\t\t# return here on error\n\t\tsw      $t0, %lo(errno)($t1)\n\n\t\t.set\treorder\n\t\tjr\t$ra\t\t\t# return here on success\n#endif /* XXX Arm ASM */\n"
  },
  {
    "path": "lib/libc/arm/sys/sbrk.c",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <unistd.h>\n\nextern char _end[];\nconst char *_curbrk = _end;\n\nvoid *\nsbrk (incr)\n\tint incr;\n{\n\tvoid *oldbrk = (void*) _curbrk;\n\n\tif (incr != 0) {\n\t\t/* calculate and pass break address */\n\t\tconst void *addr = _curbrk + incr;\n\t\tif (_brk (addr) != -1) {\n\t\t\t/* add increment to curbrk */\n\t\t\t_curbrk = addr;\n\t\t}\n\t}\n\t/* return old break address */\n\treturn oldbrk;\n}\n\nvoid *\nbrk (addr)\n\tconst void *addr;\n{\n\tint ret;\n\n\tif (addr < (void*) _end)\t/* break request too low? */\n\t\taddr = _end;\t\t/* yes, knock the request up to _end */\n\tret = _brk (addr);\t\t/* ask for break */\n\tif (ret != -1)\n\t\t_curbrk = addr;\t\t/* and remember it if it succeeded */\n\treturn (void*) ret;\n}\n"
  },
  {
    "path": "lib/libc/arm/sys/sigaction.S",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#include \"SYS.h\"\n\n/*\n * error = sigaction(sig, vec, ovec)\n *\tint\t\terror, sig;\n *\tstruct sigaction *vec, *ovec;\n *\n * We pass one additional parameter to the sigaction sys call: the address of\n * the \"Trampoline Code\", sigtramp - the code that handles saving and restoring\n * register context and so on for signals.  On the VAX-11 under BSD4.3 it isn't\n * necessary to pass this address since the trampoline code is stored in the\n * user structure in u.u_pcb.pcb_sigc at a known address in user space.  It\n * really doesn't introduce much extra overhead, so our method for doing it on\n * a PDP-11 is alright too.\n */\nENTRY(sigaction)\n\tldr\tr3, =sigtramp\t\t/* arg4: address of sigtramp. */\n\tsvc\tSYS_sigaction\n\tbcs\t1f\t\t\t/* Error if carry set. */\n\tbx\tlr\t\t\t/* Success return. */\n1:\tldr\tr1, =errno\n\tstr\tr0, [r1]\n\tmov\tr0, #0\n\tmvn\tr0, r0\n\tbx\tlr\t\t\t/* Error return. */\nEND(sigaction)\n\n/*\n * sigtramp - Signal \"Trampoline Code\"\n *\n * This code is transfered to by the kernel when a signal is delivered to a\n * process.  In general, the idea is that sigtramp saves the process' register\n * context and then vectors on to the real signal action routine.  Upon return\n * from the signal action routine sigtramp restores the process' register\n * context and performs a sigreturn.\n *\n * In the case of the PDP-11, the kernel will have already saved r0 and r1 for\n * sigtramp in a sigcontext structure it passes to us.  Sigtramp vectors onto\n * the signal action routine whose address has been left in r0 by the kernel\n * (sigtramp assumes the signal action routine will save any other registers\n * it uses (as all C routines will)).  Upon return from the signal action\n * routine, sigtramp will execute a sigreturn with the sigcontext structure\n * given to us by the kernel.\n *\n * When the kernel transfers control to sigtramp the stack looks like:\n *\n *\t-------------------------\n *\t| sigcontext structure\t| SIG_SC = sp + 8\n *\t|-----------------------|\n *\t| unused\t\t|\n *\t|-----------------------|\n *\t| $a3: ptr to sigcontext|\n *\t|-----------------------|\n *\t| $a2: code\t\t|\n *\t|-----------------------|\n *sp ->\t| $a1: signal number\t|\n *\t-------------------------\n *\n * The important features of this as far as sigtramp is concerned are:\n * 1.\tThe fact that the signal number, signal code, and signal context\n *\tpointer are already set up as parameters to the signal action\n *\troutine.\n * 2.   There's no need to save r0 & r1 because the kernel's already saved\n *      them for us in the sigcontext structure (C routines save all\n *      registers except r0 & r1 automatically).\n *\n * Note that the stack offset SIG_SC will NOT have to be recomputed if the\n * sigcontext structure changes.\n */\nENTRY(sigtramp)\n\tsvc\tSYS_sigreturn\t\t/* Attempt the sigreturn. */\n\tsvc\tSYS_exit\t\t/* Die if the sigreturn fails ... */\nEND(sigtramp)\n"
  },
  {
    "path": "lib/libc/compat/Makefile",
    "content": "#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\nTOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS\t\t+= ${DEFS} -Os\n\nSRCS\t\t= creat.c ftime.c gethostid.c memccpy.c memchr.c memcmp.c \\\n\t\t  memcpy.c memset.c nice.c pause.c rand.c sethostid.c \\\n\t\t  setregid.c setreuid.c setrgid.c setruid.c sigcompat.c \\\n\t\t  strchr.c strrchr.c times.c tmpnam.c utime.c\nOBJS\t\t= creat.o ftime.o gethostid.o memccpy.o memchr.o memcmp.o \\\n\t\t  memcpy.o memset.o nice.o pause.o rand.o sethostid.o \\\n\t\t  setregid.o setreuid.o setrgid.o setruid.o sigcompat.o \\\n\t\t  strchr.o strrchr.o times.o tmpnam.o utime.o\n\ncompat.a:\t${OBJS}\n\t\t@echo \"building compat.a\"\n\t\t@${AR} cr compat.a ${OBJS}\n\ntags:\n\t\tcwd=`pwd`; \\\n\t\tfor i in ${SRCS}; do \\\n\t\t\tctags -a -f ${TAGSFILE} $$cwd/$$i; \\\n\t\tdone\n\nclean:\n\t\trm -f compat.a *.o *~ profiled/*.o tags Makefile.bak\n\ndepend:\n\t\tfor i in ${SRCS}; do \\\n\t\t    cc -M ${CFLAGS} $$i | awk ' { if ($$1 != prev) \\\n\t\t\t{ if (rec != \"\") print rec; rec = $$0; prev = $$1; } \\\n\t\t\telse { if (length(rec $$2) > 78) { print rec; rec = $$0; } \\\n\t\t\telse rec = rec \" \" $$2 } } \\\n\t\t\tEND { print rec } ' >> makedep; done\n\t\techo '/^# DO NOT DELETE THIS LINE/+2,$$d' >eddep\n\t\techo '$$r makedep' >>eddep\n\t\techo 'w' >>eddep\n\t\tcp Makefile Makefile.bak\n\t\ted - Makefile < eddep\n\t\trm eddep makedep\n\t\techo '# DEPENDENCIES MUST END AT END OF FILE' >> Makefile\n\t\techo '# IF YOU PUT STUFF HERE IT WILL GO AWAY' >> Makefile\n\t\techo '# see make depend above' >> Makefile\n\n# DO NOT DELETE THIS LINE -- make depend uses it\n"
  },
  {
    "path": "lib/libc/compat/creat.c",
    "content": "/*\n * Copyright (c) 1989, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <fcntl.h>\n\nint\ncreat (path, mode)\n\tconst char *path;\n\tmode_t mode;\n{\n\treturn open (path, O_WRONLY | O_CREAT | O_TRUNC, mode);\n}\n"
  },
  {
    "path": "lib/libc/compat/ftime.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/types.h>\n#include <sys/time.h>\n\n/*\n * Backwards compatible ftime.\n */\n\n/* from old timeb.h */\nstruct timeb {\n\ttime_t\ttime;\n\tu_short\tmillitm;\n\tshort\ttimezone;\n\tshort\tdstflag;\n};\n\nint\nftime(tp)\n\tregister struct timeb *tp;\n{\n\tstruct timeval t;\n\tstruct timezone tz;\n\n\tif (gettimeofday(&t, &tz) < 0)\n\t\treturn (-1);\n\ttp->time = t.tv_sec;\n\ttp->millitm = t.tv_usec / 1000;\n\ttp->timezone = tz.tz_minuteswest;\n\ttp->dstflag = tz.tz_dsttime;\n\treturn 0;\n}\n"
  },
  {
    "path": "lib/libc/compat/gethostid.c",
    "content": "/*\n * Copyright (c) 1989, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/param.h>\n#include <sys/sysctl.h>\n\nu_long\ngethostid()\n{\n\tint mib[2];\n\tsize_t size;\n\tu_long value;\n\n\tmib[0] = CTL_KERN;\n\tmib[1] = KERN_HOSTID;\n\tsize = sizeof value;\n\tif (sysctl(mib, 2, &value, &size, NULL, 0) == -1)\n\t\treturn (-1);\n\treturn (value);\n}\n"
  },
  {
    "path": "lib/libc/compat/memccpy.c",
    "content": "/*\n * Copyright (c) 1985 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <string.h>\n\n/*\n * Sys5 compat routine\n */\nvoid *\nmemccpy(vt, vf, c, n)\n\tvoid *vt;\n\tconst void *vf;\n\tregister int c;\n\tregister size_t n;\n{\n\tregister char *t = vt;\n\tregister const char *f = vf;\n\n\twhile (n-- > 0)\n\t\tif ((*t++ = *f++) == c)\n\t\t\treturn (t);\n\treturn (0);\n}\n"
  },
  {
    "path": "lib/libc/compat/memchr.c",
    "content": "/*\n * Copyright (c) 1985 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <string.h>\n\n/*\n * Sys5 compat routine\n */\nvoid *\nmemchr(vs, c, n)\n\tconst void *vs;\n\tregister int c;\n\tregister size_t n;\n{\n\tregister const char *s = vs;\n\n\twhile (n-- > 0)\n\t\tif (*s++ == c)\n\t\t\treturn (void*) --s;\n\treturn (0);\n}\n"
  },
  {
    "path": "lib/libc/compat/memcmp.c",
    "content": "/*\n * Copyright (c) 1985 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <string.h>\n\n/*\n * Sys5 compat routine\n */\nint\nmemcmp (vs1, vs2, n)\n\tconst void *vs1, *vs2;\n\tregister size_t n;\n{\n\tregister const char *s1 = vs1, *s2 = vs2;\n\n\twhile (n-- > 0)\n\t\tif (*s1++ != *s2++)\n\t\t\treturn (*--s1 - *--s2);\n\treturn (0);\n}\n"
  },
  {
    "path": "lib/libc/compat/memcpy.c",
    "content": "/*\n * Copyright (c) 1985 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <string.h>\n\n/*\n * Sys5 compat routine\n */\nvoid *\nmemcpy (vt, vf, n)\n\tvoid *vt;\n\tconst void *vf;\n\tregister size_t n;\n{\n\tregister char *t = vt;\n\tregister const char *f = vf;\n\n\twhile (n-- > 0)\n\t\t*t++ = *f++;\n\n\treturn vt;\n}\n"
  },
  {
    "path": "lib/libc/compat/memset.c",
    "content": "/*\n * Copyright (c) 1985 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <string.h>\n\n/*\n * Sys5 compat routine\n */\nvoid *\nmemset (vs, c, n)\n\tvoid *vs;\n\tregister int c;\n\tregister size_t n;\n{\n\tregister char *s = vs;\n\n\twhile (n-- > 0)\n\t\t*s++ = c;\n\n\treturn vs;\n}\n"
  },
  {
    "path": "lib/libc/compat/nice.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/time.h>\n#include <sys/resource.h>\n\n/*\n * Backwards compatible nice.\n */\nint\nnice(incr)\n\tint incr;\n{\n\tint prio;\n\textern int errno;\n\n\terrno = 0;\n\tprio = getpriority(PRIO_PROCESS, 0);\n\tif (prio == -1 && errno)\n\t\treturn (-1);\n\treturn setpriority(PRIO_PROCESS, 0, prio + incr);\n}\n"
  },
  {
    "path": "lib/libc/compat/pause.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <signal.h>\n\n/*\n * Backwards compatible pause.\n */\nint\npause()\n{\n\tsigset_t set;\n\n\t(void)sigemptyset(&set);\n\tsigsuspend(&set);\n\treturn 0;\n}\n"
  },
  {
    "path": "lib/libc/compat/rand.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\nstatic\tlong\trandx = 1;\n\nvoid\nsrand(x)\n        unsigned x;\n{\n\trandx = x;\n}\n\nint\nrand()\n{\n        randx = randx * 1103515245 + 12345;\n\treturn (randx >> 16) & 0x7fff;\n}\n"
  },
  {
    "path": "lib/libc/compat/sethostid.c",
    "content": "/*\n * Copyright (c) 1989, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/param.h>\n#include <sys/sysctl.h>\n\nu_long\nsethostid(hostid)\n\tu_long hostid;\n{\n\tint mib[2];\n\n\tmib[0] = CTL_KERN;\n\tmib[1] = KERN_HOSTID;\n\tif (sysctl(mib, 2, NULL, NULL, &hostid, sizeof hostid) == -1)\n\t\treturn (-1);\n\treturn (0);\n}\n"
  },
  {
    "path": "lib/libc/compat/setregid.c",
    "content": "/*\n * Copyright (c) 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/types.h>\n#include <unistd.h>\n#include <errno.h>\n\nint\nsetregid(rgid, egid)\n\tregister gid_t rgid, egid;\n{\n\tstatic gid_t savedgid = -1;\n\n\tif (savedgid == -1)\n\t\tsavedgid = getegid();\n\t/*\n\t * we assume that the intent here is to be able to\n\t * get back rgid priviledge. So we make sure that\n\t * we will be able to do so, but do not actually\n\t * set the rgid.\n\t */\n\tif (rgid != -1 && rgid != getgid() && rgid != savedgid) {\n\t\terrno = EPERM;\n\t\treturn (-1);\n\t}\n\tif (egid != -1 && setegid(egid) < 0)\n\t\treturn (-1);\n\treturn (0);\n}\n"
  },
  {
    "path": "lib/libc/compat/setreuid.c",
    "content": "/*\n * Copyright (c) 1992, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/types.h>\n#include <unistd.h>\n#include <errno.h>\n\nint\nsetreuid(ruid, euid)\n\tregister uid_t ruid, euid;\n{\n\tstatic uid_t saveduid = -1;\n\n\tif (saveduid == -1)\n\t\tsaveduid = geteuid();\n\t/*\n\t * we assume that the intent here is to be able to\n\t * get back ruid priviledge. So we make sure that\n\t * we will be able to do so, but do not actually\n\t * set the ruid.\n\t */\n\tif (ruid != -1 && ruid != getuid() && ruid != saveduid) {\n\t\terrno = EPERM;\n\t\treturn (-1);\n\t}\n\tif (euid != -1 && seteuid(euid) < 0)\n\t\treturn (-1);\n\treturn (0);\n}\n"
  },
  {
    "path": "lib/libc/compat/setrgid.c",
    "content": "/*\n * Copyright (c) 1983, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <unistd.h>\n\nint\nsetrgid(rgid)\n\tint rgid;\n{\n\treturn (setregid(rgid, -1));\n}\n"
  },
  {
    "path": "lib/libc/compat/setruid.c",
    "content": "/*\n * Copyright (c) 1983, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <unistd.h>\n\nint\nsetruid(ruid)\n\tint ruid;\n{\n\treturn (setreuid(ruid, -1));\n}\n"
  },
  {
    "path": "lib/libc/compat/sigcompat.c",
    "content": "/*\n * Copyright (c) 1989, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/param.h>\n#include <signal.h>\n\nint\nsigvec(signo, sv, osv)\n\tint signo;\n\tregister struct sigvec *sv, *osv;\n{\n\tint ret;\n\n\tif (sv)\n\t\tsv->sv_flags ^= SV_INTERRUPT;\t/* !SA_INTERRUPT */\n\tret = sigaction(signo, (struct sigaction *)sv, (struct sigaction *)osv);\n\tif (ret == 0 && osv)\n\t\tosv->sv_flags ^= SV_INTERRUPT;\t/* !SA_INTERRUPT */\n\treturn(ret);\n}\n\nint\nsigsetmask(mask)\n\tint mask;\n{\n\tlong omask;\n\tint n;\n\n\tn = sigprocmask(SIG_SETMASK, (sigset_t *) &mask, (sigset_t *) &omask);\n\tif (n)\n\t\treturn((long)n);\n\treturn(omask);\n}\n\nint\nsigblock(mask)\n\tint mask;\n{\n\tlong omask;\n\tint n;\n\n\tn = sigprocmask(SIG_BLOCK, (sigset_t *) &mask, (sigset_t *) &omask);\n\tif (n)\n\t\treturn((long)n);\n\treturn(omask);\n}\n\nint\nsigpause(mask)\n\tint mask;\n{\n\treturn(sigsuspend((sigset_t *)&mask));\n}\n"
  },
  {
    "path": "lib/libc/compat/strchr.c",
    "content": "/*\n * Return the ptr in sp at which the character c appears;\n * NULL if not found\n *\n * this routine is just \"index\" renamed.\n */\nchar *\nstrchr (sp, c)\n\tregister const char *sp;\n\tregister int c;\n{\n\tdo {\n\t\tif (*sp == c)\n\t\t\treturn (char*) sp;\n\t} while (*sp++);\n\treturn 0;\n}\n"
  },
  {
    "path": "lib/libc/compat/strrchr.c",
    "content": "/*\n * Return the ptr in sp at which the character c last\n * appears; NULL if not found\n *\n * This routine is just \"rindex\" renamed.\n */\nchar *\nstrrchr(sp, c)\n\tregister const char *sp;\n\tregister int c;\n{\n\tregister char *r;\n\n\tr = 0;\n\tdo {\n\t\tif (*sp == c)\n\t\t\tr = (char*) sp;\n\t} while (*sp++);\n\treturn(r);\n}\n"
  },
  {
    "path": "lib/libc/compat/times.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/time.h>\n#include <sys/resource.h>\n#include <sys/types.h>\n#include <sys/times.h>\n\nstatic long\nscale60(tvp)\n\tregister struct timeval *tvp;\n{\n\treturn (tvp->tv_sec * 60 + tvp->tv_usec / 16667);\n}\n\nint\ntimes(tmsp)\n\tregister struct tms *tmsp;\n{\n\tstruct rusage ru;\n\tlong scale60();\n\n\tif (getrusage(RUSAGE_SELF, &ru) < 0)\n\t\treturn (-1);\n\ttmsp->tms_utime = scale60(&ru.ru_utime);\n\ttmsp->tms_stime = scale60(&ru.ru_stime);\n\tif (getrusage(RUSAGE_CHILDREN, &ru) < 0)\n\t\treturn (-1);\n\ttmsp->tms_cutime = scale60(&ru.ru_utime);\n\ttmsp->tms_cstime = scale60(&ru.ru_stime);\n\treturn (0);\n}\n"
  },
  {
    "path": "lib/libc/compat/tmpnam.c",
    "content": "/*\n * Copyright (c) 1988 Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that the above copyright notice and this paragraph are\n * duplicated in all such forms and that any documentation,\n * advertising materials, and other materials related to such\n * distribution and use acknowledge that the software was developed\n * by the University of California, Berkeley.  The name of the\n * University may not be used to endorse or promote products derived\n * from this software without specific prior written permission.\n * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n */\n#include <sys/param.h>\n#include <stdio.h>\n#include <string.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <paths.h>\n\nFILE *\ntmpfile()\n{\n\tFILE *fp;\n\tchar *f, *tmpnam();\n\n\tif (!(f = tmpnam((char *)NULL)) || !(fp = fopen(f, \"w+\"))) {\n\t\tfprintf(stderr, \"tmpfile: cannot open %s.\\n\", f);\n\t\treturn(NULL);\n\t}\n\t(void)unlink(f);\n\treturn(fp);\n}\n\nchar *\ntmpnam(s)\n\tchar *s;\n{\n\tif (!s && !(s = malloc((u_int)MAXPATHLEN)))\n\t\treturn(NULL);\n\tstrcpy(s, _PATH_USRTMP \"XXXXXX\");\n\treturn mktemp(s);\n}\n\nchar *\ntempnam(dir, pfx)\n\tchar *dir, *pfx;\n{\n\tchar *f, *name;\n\n\tif (!(name = malloc((u_int)MAXPATHLEN)))\n\t\treturn(NULL);\n\n        f = getenv(\"TMPDIR\");\n\tif (f) {\n\t\t(void)sprintf(name, \"%s/%sXXXXXX\", f, pfx ? \"\" : pfx);\n\t\tf = mktemp(name);\n\t\tif (f)\n\t\t\treturn(f);\n\t}\n\tif (dir) {\n\t\t(void)sprintf(name, \"%s/%sXXXXXX\", dir, pfx ? \"\" : pfx);\n\t\tf = mktemp(name);\n\t\tif (f)\n\t\t\treturn(f);\n\t}\n\t(void)sprintf(name, _PATH_USRTMP \"%sXXXXXX\", pfx ? \"\" : pfx);\n\tf = mktemp(name);\n\tif (f)\n\t\treturn(f);\n\t(void)sprintf(name, \"/tmp/%sXXXXXX\", pfx ? \"\" : pfx);\n\treturn(mktemp(name));\n}\n"
  },
  {
    "path": "lib/libc/compat/utime.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/time.h>\n#include <sys/types.h>\n\n/*\n * Backwards compatible utime.\n */\nint\nutime(name, otv)\n\tchar *name;\n\ttime_t otv[];\n{\n\tstruct timeval tv[2];\n\n\ttv[0].tv_sec = otv[0]; tv[0].tv_usec = 0;\n\ttv[1].tv_sec = otv[1]; tv[1].tv_usec = 0;\n\treturn utimes(name, tv);\n}\n"
  },
  {
    "path": "lib/libc/gen/Makefile",
    "content": "#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\nTOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS\t\t+= ${DEFS} -Os -Wno-attributes -Wno-attribute-alias\n\nSRCS\t\t= ${STDSRC}\nOBJS\t\t= ${STDOBJ}\n\nSTDSRC\t\t= abort.c alarm.c atof.c atoi.c atol.c \\\n\t\t  basename.c bcmp.c bcopy.c \\\n\t\t  bzero.c calloc.c closedir.c crypt.c ctime.c ctype_.c \\\n\t\t  daemon.c devname.c dirname.c \\\n\t\t  ecvt.c err.c execvp.c fakcu.c ffs.c \\\n\t\t  frexp.c fstab.c gcvt.c getenv.c getgrent.c getgrgid.c \\\n\t\t  getgrnam.c getgrouplist.c gethostname.c getloadavg.c \\\n\t\t  getlogin.c getmntinfo.c getpagesize.c getpass.c \\\n\t\t  getpwent.c getttyent.c getttynam.c getusershell.c \\\n\t\t  getwd.c index.c initgroups.c isatty.c isinff.c isnanf.c \\\n\t\t  knlist.c ldexp.c malloc.c mktemp.c modff.c ndbm.c \\\n\t\t  nlist.c opendir.c perror.c popen.c psignal.c qsort.c \\\n\t\t  random.c readdir.c regex.c rindex.c scandir.c seekdir.c \\\n\t\t  setenv.c sethostname.c setmode.c siginterrupt.c \\\n\t\t  siglist.c signal.c sigsetops.c sleep.c strcasecmp.c \\\n\t\t  strcat.c strcmp.c strcpy.c strdup.c strftime.c strlen.c \\\n\t\t  strncat.c strncmp.c strncpy.c swab.c sysctl.c syslog.c \\\n\t\t  system.c telldir.c time.c timezone.c ttyname.c ttyslot.c \\\n\t\t  ualarm.c uname.c usleep.c wait.c wait3.c waitpid.c\n\nSTDOBJ\t\t= abort.o alarm.o atof.o atoi.o atol.o \\\n\t\t  basename.o bcmp.o bcopy.o \\\n\t\t  bzero.o calloc.o closedir.o crypt.o ctime.o ctype_.o \\\n\t\t  daemon.o devname.o dirname.o \\\n\t\t  ecvt.o err.o execvp.o fakcu.o ffs.o \\\n\t\t  frexp.o fstab.o gcvt.o getenv.o getgrent.o getgrgid.o \\\n\t\t  getgrnam.o getgrouplist.o gethostname.o getloadavg.o \\\n\t\t  getlogin.o getmntinfo.o getpagesize.o getpass.o \\\n\t\t  getpwent.o getttyent.o getttynam.o getusershell.o \\\n\t\t  getwd.o index.o initgroups.o isatty.o isinff.o isnanf.o \\\n\t\t  knlist.o ldexp.o malloc.o mktemp.o modff.o ndbm.o \\\n\t\t  nlist.o opendir.o perror.o popen.o psignal.o qsort.o \\\n\t\t  random.o readdir.o regex.o rindex.o scandir.o seekdir.o \\\n\t\t  setenv.o sethostname.o setmode.o siginterrupt.o \\\n\t\t  siglist.o signal.o sigsetops.o sleep.o strcasecmp.o \\\n\t\t  strcat.o strcmp.o strcpy.o strdup.o strftime.o strlen.o \\\n\t\t  strncat.o strncmp.o strncpy.o swab.o sysctl.o syslog.o \\\n\t\t  system.o telldir.o time.o timezone.o ttyname.o ttyslot.o \\\n\t\t  ualarm.o uname.o usleep.o wait.o wait3.o waitpid.o\n\ngen.a:\t\t${OBJS}\n\t\t@echo \"building gen.a\"\n\t\t@${AR} cr gen.a ${OBJS}\n\ntags:\n\t\tcwd=`pwd`; \\\n\t\tfor i in ${SRCS}; do \\\n\t\t\tctags -a -f ${TAGSFILE} $$cwd/$$i; \\\n\t\tdone\n\nclean:\n\t\trm -f gen.a *.o *~ profiled/*.o tags Makefile.bak\n\ndepend:\n\t\tfor i in ${SRCS}; do \\\n\t\t    cc -M ${CFLAGS} $$i | awk ' { if ($$1 != prev) \\\n\t\t\t{ if (rec != \"\") print rec; rec = $$0; prev = $$1; } \\\n\t\t\telse { if (length(rec $$2) > 78) { print rec; rec = $$0; } \\\n\t\t\telse rec = rec \" \" $$2 } } \\\n\t\t\tEND { print rec } ' >> makedep; done\n\t\techo '/^# DO NOT DELETE THIS LINE/+2,$$d' >eddep\n\t\techo '$$r makedep' >>eddep\n\t\techo 'w' >>eddep\n\t\tcp Makefile Makefile.bak\n\t\ted - Makefile < eddep\n\t\trm eddep makedep\n\t\techo '# DEPENDENCIES MUST END AT END OF FILE' >> Makefile\n\t\techo '# IF YOU PUT STUFF HERE IT WILL GO AWAY' >> Makefile\n\t\techo '# see make depend above' >> Makefile\n\n# DO NOT DELETE THIS LINE -- make depend uses it\n"
  },
  {
    "path": "lib/libc/gen/abort.c",
    "content": "/*\n * Copyright (c) 1985, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <signal.h>\n#include <stdlib.h>\n#include <unistd.h>\n\nvoid\nabort()\n{\n\tsigset_t mask;\n\n\t(void)sigfillset(&mask);\n\t/*\n\t * don't block SIGABRT to give any handler a chance; we ignore\n\t * any errors -- X311J doesn't allow abort to return anyway.\n\t */\n\t(void)sigdelset(&mask, SIGABRT);\n\t(void)sigprocmask(SIG_SETMASK, &mask, (sigset_t *)NULL);\n\t(void)kill(getpid(), SIGABRT);\n\n\t/*\n\t * if SIGABRT ignored, or caught and the handler returns, do\n\t * it again, only harder.\n\t */\n\t(void)signal(SIGABRT, SIG_DFL);\n\t(void)sigprocmask(SIG_SETMASK, &mask, (sigset_t *)NULL);\n\t(void)kill(getpid(), SIGABRT);\n\texit(1);\n}\n"
  },
  {
    "path": "lib/libc/gen/abs.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\nabs(arg)\n\tint arg;\n{\n\treturn(arg < 0 ? -arg : arg);\n}\n"
  },
  {
    "path": "lib/libc/gen/alarm.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * Backwards compatible alarm.\n */\n#include <sys/time.h>\n\nint\nalarm(secs)\n\tint secs;\n{\n\tstruct itimerval it, oitv;\n\tregister struct itimerval *itp = &it;\n\n\ttimerclear(&itp->it_interval);\n\titp->it_value.tv_sec = secs;\n\titp->it_value.tv_usec = 0;\n\tif (setitimer(ITIMER_REAL, itp, &oitv) < 0)\n\t\treturn (-1);\n\tif (oitv.it_value.tv_usec)\n\t\toitv.it_value.tv_sec++;\n\treturn (oitv.it_value.tv_sec);\n}\n"
  },
  {
    "path": "lib/libc/gen/atof.c",
    "content": "/*\n * C library - ascii to floating\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <float.h>\n#include <math.h>\n#include <ctype.h>\n\n/*\n * BIG = 2**(DBL_MANT_DIG+3) defines how many decimal digits\n * to take into account from the input. It doesn't make sense\n * to use more digits than log10(2**DBL_MANT_DIG)+1.\n * BIG is equal 2**27 or 2**56, depending on whether double\n * is single or double precision.\n */\n#define BIG (8 * (double)(1L << (DBL_MANT_DIG/2)) * \\\n        (double)(1L << (DBL_MANT_DIG/2 + DBL_MANT_DIG%2)))\n\ndouble\natof(p)\nregister char *p;\n{\n\tregister int c;\n\tdouble fl, flexp, exp5;\n\tdouble big = BIG;\n\tint nd;\n\tregister int eexp, exp, neg, negexp, bexp;\n\n\tneg = 1;\n\twhile((c = *p++) == ' ')\n\t\t;\n\tif (c == '-')\n\t\tneg = -1;\n\telse if (c=='+')\n\t\t;\n\telse\n\t\t--p;\n\n\texp = 0;\n\tfl = 0;\n\tnd = 0;\n\twhile ((c = *p++), isdigit(c)) {\n\t\tif (fl<big)\n\t\t\tfl = 10*fl + (c-'0');\n\t\telse\n\t\t\texp++;\n\t\tnd++;\n\t}\n\n\tif (c == '.') {\n\t\twhile ((c = *p++), isdigit(c)) {\n\t\t\tif (fl<big) {\n\t\t\t\tfl = 10*fl + (c-'0');\n\t\t\t\texp--;\n\t\t\t}\n\t\tnd++;\n\t\t}\n\t}\n\n\tnegexp = 1;\n\teexp = 0;\n\tif ((c == 'E') || (c == 'e')) {\n\t\tif ((c= *p++) == '+')\n\t\t\t;\n\t\telse if (c=='-')\n\t\t\tnegexp = -1;\n\t\telse\n\t\t\t--p;\n\n\t\twhile ((c = *p++), isdigit(c)) {\n\t\t\teexp = 10*eexp+(c-'0');\n\t\t}\n\t\tif (negexp<0)\n\t\t\teexp = -eexp;\n\t\texp = exp + eexp;\n\t}\n\n\tnegexp = 1;\n\tif (exp<0) {\n\t\tnegexp = -1;\n\t\texp = -exp;\n\t}\n\n\n\tif ((nd+exp*negexp) < DBL_MIN_10_EXP - 2) {\n\t\tfl = 0;\n\t\texp = 0;\n\t}\n\tflexp = 1;\n\texp5 = 5;\n\tbexp = exp;\n\tfor (;;) {\n\t\tif (exp&01)\n\t\t\tflexp *= exp5;\n\t\texp >>= 1;\n\t\tif (exp==0)\n\t\t\tbreak;\n\t\texp5 *= exp5;\n\t}\n\tif (negexp<0)\n\t\tfl /= flexp;\n\telse\n\t\tfl *= flexp;\n\tfl = ldexp(fl, negexp*bexp);\n\tif (neg<0)\n\t\tfl = -fl;\n\treturn(fl);\n}\n"
  },
  {
    "path": "lib/libc/gen/atoi.c",
    "content": "int\natoi(p)\n\tregister char *p;\n{\n\tregister int n;\n\tregister int f;\n\n\tn = 0;\n\tf = 0;\n\tfor(;;p++) {\n\t\tswitch(*p) {\n\t\tcase ' ':\n\t\tcase '\\t':\n\t\t\tcontinue;\n\t\tcase '-':\n\t\t\tf++;\n\t\tcase '+':\n\t\t\tp++;\n\t\t}\n\t\tbreak;\n\t}\n\twhile(*p >= '0' && *p <= '9')\n\t\tn = n*10 + *p++ - '0';\n\treturn(f? -n: n);\n}\n"
  },
  {
    "path": "lib/libc/gen/atol.c",
    "content": "long\natol(p)\n\tregister char *p;\n{\n\tlong n;\n\tregister int f;\n\n\tn = 0;\n\tf = 0;\n\tfor(;;p++) {\n\t\tswitch(*p) {\n\t\tcase ' ':\n\t\tcase '\\t':\n\t\t\tcontinue;\n\t\tcase '-':\n\t\t\tf++;\n\t\tcase '+':\n\t\t\tp++;\n\t\t}\n\t\tbreak;\n\t}\n\twhile(*p >= '0' && *p <= '9')\n\t\tn = n*10 + *p++ - '0';\n\treturn(f? -n: n);\n}\n"
  },
  {
    "path": "lib/libc/gen/basename.c",
    "content": "/*\t$OpenBSD: basename.c,v 1.17 2020/10/20 19:30:14 naddy Exp $\t*/\n\n/*\n * Copyright (c) 1997, 2004 Todd C. Miller <millert@openbsd.org>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include <errno.h>\n#include <libgen.h>\n#include <limits.h>\n#include <string.h>\n\nchar *\nbasename(char *path)\n{\n\tstatic char bname[PATH_MAX];\n\tsize_t len;\n\tconst char *endp, *startp;\n\n\t/* Empty or NULL string gets treated as \".\" */\n\tif (path == NULL || *path == '\\0') {\n\t\tbname[0] = '.';\n\t\tbname[1] = '\\0';\n\t\treturn (bname);\n\t}\n\n\t/* Strip any trailing slashes */\n\tendp = path + strlen(path) - 1;\n\twhile (endp > path && *endp == '/')\n\t\tendp--;\n\n\t/* All slashes becomes \"/\" */\n\tif (endp == path && *endp == '/') {\n\t\tbname[0] = '/';\n\t\tbname[1] = '\\0';\n\t\treturn (bname);\n\t}\n\n\t/* Find the start of the base */\n\tstartp = endp;\n\twhile (startp > path && *(startp - 1) != '/')\n\t\tstartp--;\n\n\tlen = endp - startp + 1;\n\tif (len >= sizeof(bname)) {\n\t\terrno = ENAMETOOLONG;\n\t\treturn (NULL);\n\t}\n\tmemcpy(bname, startp, len);\n\tbname[len] = '\\0';\n\treturn (bname);\n}\n"
  },
  {
    "path": "lib/libc/gen/bcmp.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#include <string.h>\n\n/*\n * bcmp -- vax cmpc3 instruction\n */\nint\nbcmp(v1, v2, length)\n\tconst void *v1, *v2;\n\tsize_t length;\n{\n        register const char *b1 = v1;\n        register const char *b2 = v2;\n\tif (length)\n\t\tdo\n\t\t\tif (*b1++ != *b2++)\n\t\t\t\tbreak;\n\t\twhile (--length);\n\treturn(length);\n}\n"
  },
  {
    "path": "lib/libc/gen/bcopy.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * bcopy -- vax movc3 instruction\n */\nvoid\nbcopy(src0, dst0, length)\n\tregister const void *src0;\n\tregister void *dst0;\n\tregister unsigned int length;\n{\n\tconst char *src = src0;\n\tchar *dst = dst0;\n\n\tif (length && src != dst) {\n\t\tif (dst < src) {\n\t\t\tdo\n\t\t\t\t*dst++ = *src++;\n\t\t\twhile (--length);\n\t\t} else {\t\t/* copy backwards */\n\t\t\tsrc += length;\n\t\t\tdst += length;\n\t\t\tdo\n\t\t\t\t*--dst = *--src;\n\t\t\twhile (--length);\n\t\t}\n\t}\n\treturn;\n}\n"
  },
  {
    "path": "lib/libc/gen/bzero.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)bzero.c\t1.1 (Berkeley) 1/19/87\n */\n\n#include <string.h>\n\n/*\n * bzero -- vax movc5 instruction\n */\nvoid\nbzero(void *b, size_t length)\n{\n\tchar *p;\n\n\tif (length) {\n\t\tp = b;\n\t\tdo {\n\t\t\t*p++ = '\\0';\n\t\t} while (--length);\n\t}\n}\n"
  },
  {
    "path": "lib/libc/gen/calloc.c",
    "content": "/*\n * Calloc - allocate and clear memory block\n */\n#include <sys/types.h>\n#include <stdlib.h>\n#include <strings.h>\n\nvoid *\ncalloc(num, size)\n\tsize_t num, size;\n{\n\tregister char *p;\n\n\tsize *= num;\n\tp = malloc(size);\n\tif (p)\n\t\tbzero(p, size);\n\treturn (p);\n}\n\nvoid\ncfree(p, num, size)\n\tchar *p;\n\tunsigned num;\n\tunsigned size;\n{\n\tfree(p);\n}\n"
  },
  {
    "path": "lib/libc/gen/closedir.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/dir.h>\n#include <stdlib.h>\n#include <unistd.h>\n\n/*\n * close a directory.\n */\nvoid\nclosedir(dirp)\n\tregister DIR *dirp;\n{\n\tclose(dirp->dd_fd);\n\tdirp->dd_fd = -1;\n\tdirp->dd_loc = 0;\n\tfree(dirp);\n}\n"
  },
  {
    "path": "lib/libc/gen/crypt.c",
    "content": "/*\n * This program implements the\n * Proposed Federal Information Processing\n *  Data Encryption Standard.\n * See Federal Register, March 17, 1975 (40FR12134)\n */\n\n/*\n * Initial permutation,\n */\nstatic\tchar\tIP[] = {\n\t58,50,42,34,26,18,10, 2,\n\t60,52,44,36,28,20,12, 4,\n\t62,54,46,38,30,22,14, 6,\n\t64,56,48,40,32,24,16, 8,\n\t57,49,41,33,25,17, 9, 1,\n\t59,51,43,35,27,19,11, 3,\n\t61,53,45,37,29,21,13, 5,\n\t63,55,47,39,31,23,15, 7,\n};\n\n/*\n * Final permutation, FP = IP^(-1)\n */\nstatic\tchar\tFP[] = {\n\t40, 8,48,16,56,24,64,32,\n\t39, 7,47,15,55,23,63,31,\n\t38, 6,46,14,54,22,62,30,\n\t37, 5,45,13,53,21,61,29,\n\t36, 4,44,12,52,20,60,28,\n\t35, 3,43,11,51,19,59,27,\n\t34, 2,42,10,50,18,58,26,\n\t33, 1,41, 9,49,17,57,25,\n};\n\n/*\n * Permuted-choice 1 from the key bits\n * to yield C and D.\n * Note that bits 8,16... are left out:\n * They are intended for a parity check.\n */\nstatic\tchar\tPC1_C[] = {\n\t57,49,41,33,25,17, 9,\n\t 1,58,50,42,34,26,18,\n\t10, 2,59,51,43,35,27,\n\t19,11, 3,60,52,44,36,\n};\n\nstatic\tchar\tPC1_D[] = {\n\t63,55,47,39,31,23,15,\n\t 7,62,54,46,38,30,22,\n\t14, 6,61,53,45,37,29,\n\t21,13, 5,28,20,12, 4,\n};\n\n/*\n * Sequence of shifts used for the key schedule.\n*/\nstatic\tchar\tshifts[] = {\n\t1,1,2,2,2,2,2,2,1,2,2,2,2,2,2,1,\n};\n\n/*\n * Permuted-choice 2, to pick out the bits from\n * the CD array that generate the key schedule.\n */\nstatic\tchar\tPC2_C[] = {\n\t14,17,11,24, 1, 5,\n\t 3,28,15, 6,21,10,\n\t23,19,12, 4,26, 8,\n\t16, 7,27,20,13, 2,\n};\n\nstatic\tchar\tPC2_D[] = {\n\t41,52,31,37,47,55,\n\t30,40,51,45,33,48,\n\t44,49,39,56,34,53,\n\t46,42,50,36,29,32,\n};\n\n/*\n * The C and D arrays used to calculate the key schedule.\n */\n\nstatic\tchar\tC[28];\nstatic\tchar\tD[28];\n/*\n * The key schedule.\n * Generated from the key.\n */\nstatic\tchar\tKS[16][48];\n\n/*\n * The E bit-selection table.\n */\nstatic\tchar\tE[48];\nstatic\tchar\te[] = {\n\t32, 1, 2, 3, 4, 5,\n\t 4, 5, 6, 7, 8, 9,\n\t 8, 9,10,11,12,13,\n\t12,13,14,15,16,17,\n\t16,17,18,19,20,21,\n\t20,21,22,23,24,25,\n\t24,25,26,27,28,29,\n\t28,29,30,31,32, 1,\n};\n\n/*\n * Set up the key schedule from the key.\n */\nvoid\nsetkey(key)\nchar *key;\n{\n\tregister int i, j, k;\n\tint t;\n\n\t/*\n\t * First, generate C and D by permuting\n\t * the key.  The low order bit of each\n\t * 8-bit char is not used, so C and D are only 28\n\t * bits apiece.\n\t */\n\tfor (i=0; i<28; i++) {\n\t\tC[i] = key[PC1_C[i]-1];\n\t\tD[i] = key[PC1_D[i]-1];\n\t}\n\t/*\n\t * To generate Ki, rotate C and D according\n\t * to schedule and pick up a permutation\n\t * using PC2.\n\t */\n\tfor (i=0; i<16; i++) {\n\t\t/*\n\t\t * rotate.\n\t\t */\n\t\tfor (k=0; k<shifts[i]; k++) {\n\t\t\tt = C[0];\n\t\t\tfor (j=0; j<28-1; j++)\n\t\t\t\tC[j] = C[j+1];\n\t\t\tC[27] = t;\n\t\t\tt = D[0];\n\t\t\tfor (j=0; j<28-1; j++)\n\t\t\t\tD[j] = D[j+1];\n\t\t\tD[27] = t;\n\t\t}\n\t\t/*\n\t\t * get Ki. Note C and D are concatenated.\n\t\t */\n\t\tfor (j=0; j<24; j++) {\n\t\t\tKS[i][j] = C[PC2_C[j]-1];\n\t\t\tKS[i][j+24] = D[PC2_D[j]-28-1];\n\t\t}\n\t}\n\n\tfor(i=0;i<48;i++)\n\t\tE[i] = e[i];\n}\n\n/*\n * The 8 selection functions.\n * For some reason, they give a 0-origin\n * index, unlike everything else.\n */\nstatic\tchar\tS[8][64] = {\n      { 14, 4,13, 1, 2,15,11, 8, 3,10, 6,12, 5, 9, 0, 7,\n\t 0,15, 7, 4,14, 2,13, 1,10, 6,12,11, 9, 5, 3, 8,\n\t 4, 1,14, 8,13, 6, 2,11,15,12, 9, 7, 3,10, 5, 0,\n\t15,12, 8, 2, 4, 9, 1, 7, 5,11, 3,14,10, 0, 6,13 },\n\n      { 15, 1, 8,14, 6,11, 3, 4, 9, 7, 2,13,12, 0, 5,10,\n\t 3,13, 4, 7,15, 2, 8,14,12, 0, 1,10, 6, 9,11, 5,\n\t 0,14, 7,11,10, 4,13, 1, 5, 8,12, 6, 9, 3, 2,15,\n\t13, 8,10, 1, 3,15, 4, 2,11, 6, 7,12, 0, 5,14, 9 },\n\n      { 10, 0, 9,14, 6, 3,15, 5, 1,13,12, 7,11, 4, 2, 8,\n\t13, 7, 0, 9, 3, 4, 6,10, 2, 8, 5,14,12,11,15, 1,\n\t13, 6, 4, 9, 8,15, 3, 0,11, 1, 2,12, 5,10,14, 7,\n\t 1,10,13, 0, 6, 9, 8, 7, 4,15,14, 3,11, 5, 2,12 },\n\n      {  7,13,14, 3, 0, 6, 9,10, 1, 2, 8, 5,11,12, 4,15,\n\t13, 8,11, 5, 6,15, 0, 3, 4, 7, 2,12, 1,10,14, 9,\n\t10, 6, 9, 0,12,11, 7,13,15, 1, 3,14, 5, 2, 8, 4,\n\t 3,15, 0, 6,10, 1,13, 8, 9, 4, 5,11,12, 7, 2,14 },\n\n      {  2,12, 4, 1, 7,10,11, 6, 8, 5, 3,15,13, 0,14, 9,\n\t14,11, 2,12, 4, 7,13, 1, 5, 0,15,10, 3, 9, 8, 6,\n\t 4, 2, 1,11,10,13, 7, 8,15, 9,12, 5, 6, 3, 0,14,\n\t11, 8,12, 7, 1,14, 2,13, 6,15, 0, 9,10, 4, 5, 3 },\n\n      { 12, 1,10,15, 9, 2, 6, 8, 0,13, 3, 4,14, 7, 5,11,\n\t10,15, 4, 2, 7,12, 9, 5, 6, 1,13,14, 0,11, 3, 8,\n\t 9,14,15, 5, 2, 8,12, 3, 7, 0, 4,10, 1,13,11, 6,\n\t 4, 3, 2,12, 9, 5,15,10,11,14, 1, 7, 6, 0, 8,13 },\n\n      {  4,11, 2,14,15, 0, 8,13, 3,12, 9, 7, 5,10, 6, 1,\n\t13, 0,11, 7, 4, 9, 1,10,14, 3, 5,12, 2,15, 8, 6,\n\t 1, 4,11,13,12, 3, 7,14,10,15, 6, 8, 0, 5, 9, 2,\n\t 6,11,13, 8, 1, 4,10, 7, 9, 5, 0,15,14, 2, 3,12 },\n\n      { 13, 2, 8, 4, 6,15,11, 1,10, 9, 3,14, 5, 0,12, 7,\n\t 1,15,13, 8,10, 3, 7, 4,12, 5, 6,11, 0,14, 9, 2,\n\t 7,11, 4, 1, 9,12,14, 2, 0, 6,10,13,15, 3, 5, 8,\n\t 2, 1,14, 7, 4,10, 8,13,15,12, 9, 0, 3, 5, 6,11 },\n};\n\n/*\n * P is a permutation on the selected combination\n * of the current L and key.\n */\nstatic\tchar\tP[] = {\n\t16, 7,20,21,\n\t29,12,28,17,\n\t 1,15,23,26,\n\t 5,18,31,10,\n\t 2, 8,24,14,\n\t32,27, 3, 9,\n\t19,13,30, 6,\n\t22,11, 4,25,\n};\n\n/*\n * The current block, divided into 2 halves.\n */\nstatic\tchar\tL[64], *R = L+32;\nstatic\tchar\ttempL[32];\nstatic\tchar\tf[32];\n\n/*\n * The combination of the key and the input, before selection.\n */\nstatic\tchar\tpreS[48];\n\n/*\n * The payoff: encrypt a block.\n */\nvoid\nencrypt(block, edflag)\nchar *block;\nint edflag;\n{\n\tint i, ii;\n\tregister int t, j, k;\n\n\t/*\n\t * First, permute the bits in the input\n\t */\n\tfor (j=0; j<64; j++)\n\t\tL[j] = block[IP[j]-1];\n\t/*\n\t * Perform an encryption operation 16 times.\n\t */\n\tfor (ii=0; ii<16; ii++) {\n\t\t/*\n\t\t * Only encrypt for now.\n\t\t */\n\t\ti = ii;\n\t\t/*\n\t\t * Save the R array,\n\t\t * which will be the new L.\n\t\t */\n\t\tfor (j=0; j<32; j++)\n\t\t\ttempL[j] = R[j];\n\t\t/*\n\t\t * Expand R to 48 bits using the E selector;\n\t\t * exclusive-or with the current key bits.\n\t\t */\n\t\tfor (j=0; j<48; j++)\n\t\t\tpreS[j] = R[E[j]-1] ^ KS[i][j];\n\t\t/*\n\t\t * The pre-select bits are now considered\n\t\t * in 8 groups of 6 bits each.\n\t\t * The 8 selection functions map these\n\t\t * 6-bit quantities into 4-bit quantities\n\t\t * and the results permuted\n\t\t * to make an f(R, K).\n\t\t * The indexing into the selection functions\n\t\t * is peculiar; it could be simplified by\n\t\t * rewriting the tables.\n\t\t */\n\t\tfor (j=0; j<8; j++) {\n\t\t\tt = 6*j;\n\t\t\tk = S[j][(preS[t+0]<<5)+\n\t\t\t\t(preS[t+1]<<3)+\n\t\t\t\t(preS[t+2]<<2)+\n\t\t\t\t(preS[t+3]<<1)+\n\t\t\t\t(preS[t+4]<<0)+\n\t\t\t\t(preS[t+5]<<4)];\n\t\t\tt = 4*j;\n\t\t\tf[t+0] = (k>>3)&01;\n\t\t\tf[t+1] = (k>>2)&01;\n\t\t\tf[t+2] = (k>>1)&01;\n\t\t\tf[t+3] = (k>>0)&01;\n\t\t}\n\t\t/*\n\t\t * The new R is L ^ f(R, K).\n\t\t * The f here has to be permuted first, though.\n\t\t */\n\t\tfor (j=0; j<32; j++)\n\t\t\tR[j] = L[j] ^ f[P[j]-1];\n\t\t/*\n\t\t * Finally, the new L (the original R)\n\t\t * is copied back.\n\t\t */\n\t\tfor (j=0; j<32; j++)\n\t\t\tL[j] = tempL[j];\n\t}\n\t/*\n\t * The output L and R are reversed.\n\t */\n\tfor (j=0; j<32; j++) {\n\t\tt = L[j];\n\t\tL[j] = R[j];\n\t\tR[j] = t;\n\t}\n\t/*\n\t * The final output\n\t * gets the inverse permutation of the very original.\n\t */\n\tfor (j=0; j<64; j++)\n\t\tblock[j] = L[FP[j]-1];\n}\n\nchar *\ncrypt(pw,salt)\nchar *pw;\nchar *salt;\n{\n\tregister int i, j, c;\n\tint temp;\n\tstatic char block[66], iobuf[16];\n\n\tfor(i=0; i<66; i++)\n\t\tblock[i] = 0;\n\tfor(i=0; (c= *pw) && i<64; pw++){\n\t\tfor(j=0; j<7; j++, i++)\n\t\t\tblock[i] = (c>>(6-j)) & 01;\n\t\ti++;\n\t}\n\n\tsetkey(block);\n\n\tfor(i=0; i<66; i++)\n\t\tblock[i] = 0;\n\n\tfor(i=0;i<2;i++){\n\t\tc = *salt++;\n\t\tiobuf[i] = c;\n\t\tif(c>'Z') c -= 6;\n\t\tif(c>'9') c -= 7;\n\t\tc -= '.';\n\t\tfor(j=0;j<6;j++){\n\t\t\tif((c>>j) & 01){\n\t\t\t\ttemp = E[6*i+j];\n\t\t\t\tE[6*i+j] = E[6*i+j+24];\n\t\t\t\tE[6*i+j+24] = temp;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\tfor(i=0; i<25; i++)\n\t\tencrypt(block,0);\n\n\tfor(i=0; i<11; i++){\n\t\tc = 0;\n\t\tfor(j=0; j<6; j++){\n\t\t\tc <<= 1;\n\t\t\tc |= block[6*i+j];\n\t\t\t}\n\t\tc += '.';\n\t\tif(c>'9') c += 7;\n\t\tif(c>'Z') c += 6;\n\t\tiobuf[i+2] = c;\n\t}\n\tiobuf[i+2] = 0;\n\tif(iobuf[1]==0)\n\t\tiobuf[1] = iobuf[0];\n\treturn(iobuf);\n}\n"
  },
  {
    "path": "lib/libc/gen/ctime.c",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * This file may be freely redistributed provided that this\n * notice remains attached.\n */\n#include \"sys/param.h\"\n#include \"sys/time.h\"\n#include \"stdio.h\"\n#include \"string.h\"\n#include \"unistd.h\"\n#include \"fcntl.h\"\n#include \"alloca.h\"\n#include \"tzfile.h\"\n#include \"paths.h\"\n\nchar *\nctime(t)\n        const time_t *t;\n{\n\treturn asctime(localtime(t));\n}\n\n/*\n** A la X3J11\n*/\n\nchar *\nasctime(timeptr)\n    register const struct tm *timeptr;\n{\n\tstatic char\twday_name[DAYS_PER_WEEK][3] = {\n\t\t\"Sun\", \"Mon\", \"Tue\", \"Wed\", \"Thu\", \"Fri\", \"Sat\"\n\t};\n\tstatic char\tmon_name[MONS_PER_YEAR][3] = {\n\t\t\"Jan\", \"Feb\", \"Mar\", \"Apr\", \"May\", \"Jun\",\n\t\t\"Jul\", \"Aug\", \"Sep\", \"Oct\", \"Nov\", \"Dec\"\n\t};\n\tstatic char\tresult[26];\n\n\t(void) sprintf(result, \"%.3s %.3s%3d %02d:%02d:%02d %d\\n\",\n\t\twday_name[timeptr->tm_wday],\n\t\tmon_name[timeptr->tm_mon],\n\t\ttimeptr->tm_mday, timeptr->tm_hour,\n\t\ttimeptr->tm_min, timeptr->tm_sec,\n\t\tTM_YEAR_BASE + timeptr->tm_year);\n\treturn result;\n}\n\n#ifndef TRUE\n#define TRUE\t\t1\n#define FALSE\t\t0\n#endif /* !TRUE */\n\nextern char *\t\tgetenv();\nextern char *\t\tstrcpy();\nextern char *\t\tstrcat();\nstruct tm *\t\tofftime();\n\nstruct ttinfo {\t\t\t\t/* time type information */\n\tlong\t\ttt_gmtoff;\t/* GMT offset in seconds */\n\tint\t\ttt_isdst;\t/* used to set tm_isdst */\n\tint\t\ttt_abbrind;\t/* abbreviation list index */\n};\n\nstruct state {\n\tint\t\ttimecnt;\n\tint\t\ttypecnt;\n\tint\t\tcharcnt;\n\ttime_t\t\tats[TZ_MAX_TIMES];\n\tunsigned char\ttypes[TZ_MAX_TIMES];\n\tstruct ttinfo\tttis[TZ_MAX_TYPES];\n\tchar\t\tchars[TZ_MAX_CHARS + 1];\n};\n\nstatic struct state\ts;\n\nstatic int\t\ttz_is_set;\n\nchar *\t\t\ttzname[2] = {\n\t\"GMT\",\n\t\"GMT\"\n};\n\n#ifdef USG_COMPAT\ntime_t\t\t\ttimezone = 0;\nint\t\t\tdaylight = 0;\n#endif /* USG_COMPAT */\n\nstatic long\ndetzcode(codep)\nchar *\tcodep;\n{\n\tregister long\tresult;\n\tregister int\ti;\n\n\tresult = 0;\n\tfor (i = 0; i < 4; ++i)\n\t\tresult = (result << 8) | (codep[i] & 0xff);\n\treturn result;\n}\n\nstatic int\ntzload(name)\nregister char *\tname;\n{\n\tregister int\ti;\n\tregister int\tfid;\n\n\tif (name == 0 && (name = _PATH_LOCALTIME) == 0)\n\t\treturn -1;\n\t{\n\t\tregister char *\tp;\n\t\tregister int\tdoaccess;\n                char          * fullname;\n\n\t\tdoaccess = name[0] == '/';\n\t\tif (!doaccess) {\n\t\t\tif ((p = _PATH_ZONEINFO) == 0)\n\t\t\t\treturn -1;\n\t\t\tif ((strlen(p) + strlen(name) + 1) >= MAXPATHLEN)\n\t\t\t\treturn -1;\n                        fullname = alloca(MAXPATHLEN);\n\t\t\t(void) strcpy(fullname, p);\n\t\t\t(void) strcat(fullname, \"/\");\n\t\t\t(void) strcat(fullname, name);\n\t\t\t/*\n\t\t\t** Set doaccess if '.' (as in \"../\") shows up in name.\n\t\t\t*/\n\t\t\twhile (*name != '\\0')\n\t\t\t\tif (*name++ == '.')\n\t\t\t\t\tdoaccess = TRUE;\n\t\t\tname = fullname;\n\t\t}\n\t\tif (doaccess && access(name, 4) != 0)\n\t\t\treturn -1;\n\t\tif ((fid = open(name, 0)) == -1)\n\t\t\treturn -1;\n\t}\n\t{\n\t\tregister char *\t\t\tp;\n\t\tregister struct tzhead *\ttzhp;\n\t\tchar *\t\t\t\tbuf;\n\n\t\tbuf = alloca(sizeof s);\n\t\ti = read(fid, buf, sizeof s);\n\t\tif (close(fid) != 0 || i < sizeof *tzhp)\n\t\t\treturn -1;\n\t\ttzhp = (struct tzhead *) buf;\n\t\ts.timecnt = (int) detzcode(tzhp->tzh_timecnt);\n\t\ts.typecnt = (int) detzcode(tzhp->tzh_typecnt);\n\t\ts.charcnt = (int) detzcode(tzhp->tzh_charcnt);\n\t\tif (s.timecnt > TZ_MAX_TIMES ||\n\t\t\ts.typecnt == 0 ||\n\t\t\ts.typecnt > TZ_MAX_TYPES ||\n\t\t\ts.charcnt > TZ_MAX_CHARS)\n\t\t\t\treturn -1;\n\t\tif (i < sizeof *tzhp +\n\t\t\ts.timecnt * (4 + sizeof (char)) +\n\t\t\ts.typecnt * (4 + 2 * sizeof (char)) +\n\t\t\ts.charcnt * sizeof (char))\n\t\t\t\treturn -1;\n\t\tp = buf + sizeof *tzhp;\n\t\tfor (i = 0; i < s.timecnt; ++i) {\n\t\t\ts.ats[i] = detzcode(p);\n\t\t\tp += 4;\n\t\t}\n\t\tfor (i = 0; i < s.timecnt; ++i)\n\t\t\ts.types[i] = (unsigned char) *p++;\n\t\tfor (i = 0; i < s.typecnt; ++i) {\n\t\t\tregister struct ttinfo *\tttisp;\n\n\t\t\tttisp = &s.ttis[i];\n\t\t\tttisp->tt_gmtoff = detzcode(p);\n\t\t\tp += 4;\n\t\t\tttisp->tt_isdst = (unsigned char) *p++;\n\t\t\tttisp->tt_abbrind = (unsigned char) *p++;\n\t\t}\n\t\tfor (i = 0; i < s.charcnt; ++i)\n\t\t\ts.chars[i] = *p++;\n\t\ts.chars[i] = '\\0';\t/* ensure '\\0' at end */\n\t}\n\t/*\n\t** Check that all the local time type indices are valid.\n\t*/\n\tfor (i = 0; i < s.timecnt; ++i)\n\t\tif (s.types[i] >= s.typecnt)\n\t\t\treturn -1;\n\t/*\n\t** Check that all abbreviation indices are valid.\n\t*/\n\tfor (i = 0; i < s.typecnt; ++i)\n\t\tif (s.ttis[i].tt_abbrind >= s.charcnt)\n\t\t\treturn -1;\n\t/*\n\t** Set tzname elements to initial values.\n\t*/\n\ttzname[0] = tzname[1] = &s.chars[0];\n#ifdef USG_COMPAT\n\ttimezone = s.ttis[0].tt_gmtoff;\n\tdaylight = 0;\n#endif /* USG_COMPAT */\n\tfor (i = 1; i < s.typecnt; ++i) {\n\t\tregister struct ttinfo *\tttisp;\n\n\t\tttisp = &s.ttis[i];\n\t\tif (ttisp->tt_isdst) {\n\t\t\ttzname[1] = &s.chars[ttisp->tt_abbrind];\n#ifdef USG_COMPAT\n\t\t\tdaylight = 1;\n#endif /* USG_COMPAT */\n\t\t} else {\n\t\t\ttzname[0] = &s.chars[ttisp->tt_abbrind];\n#ifdef USG_COMPAT\n\t\t\ttimezone = ttisp->tt_gmtoff;\n#endif /* USG_COMPAT */\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic int\ntzsetkernel()\n{\n\tstruct timeval\ttv;\n\tstruct timezone\ttz;\n\n\tif (gettimeofday(&tv, &tz))\n\t\treturn -1;\n\ts.timecnt = 0;\t\t/* UNIX counts *west* of Greenwich */\n\ts.ttis[0].tt_gmtoff = tz.tz_minuteswest * -SECS_PER_MIN;\n\ts.ttis[0].tt_abbrind = 0;\n\t(void)strcpy(s.chars, tztab(tz.tz_minuteswest, 0));\n\ttzname[0] = tzname[1] = s.chars;\n#ifdef USG_COMPAT\n\ttimezone = tz.tz_minuteswest * 60;\n\tdaylight = tz.tz_dsttime;\n#endif /* USG_COMPAT */\n\treturn 0;\n}\n\nstatic void\ntzsetgmt()\n{\n\ts.timecnt = 0;\n\ts.ttis[0].tt_gmtoff = 0;\n\ts.ttis[0].tt_abbrind = 0;\n\t(void) strcpy(s.chars, \"GMT\");\n\ttzname[0] = tzname[1] = s.chars;\n#ifdef USG_COMPAT\n\ttimezone = 0;\n\tdaylight = 0;\n#endif /* USG_COMPAT */\n}\n\nvoid\ntzset()\n{\n\tregister char *\tname;\n\n\ttz_is_set = TRUE;\n\tname = getenv(\"TZ\");\n\tif (!name || *name) {\t\t\t/* did not request GMT */\n\t\tif (name && !tzload(name))\t/* requested name worked */\n\t\t\treturn;\n\t\tif (!tzload((char *)0))\t\t/* default name worked */\n\t\t\treturn;\n\t\tif (!tzsetkernel())\t\t/* kernel guess worked */\n\t\t\treturn;\n\t}\n\ttzsetgmt();\t\t\t\t/* GMT is default */\n}\n\nstruct tm *\nlocaltime(timep)\n        const time_t *timep;\n{\n\tregister struct ttinfo *\tttisp;\n\tregister struct tm *\t\ttmp;\n\tregister int\t\t\ti;\n\ttime_t\t\t\t\tt;\n\n\tif (!tz_is_set)\n\t\t(void) tzset();\n\tt = *timep;\n\tif (s.timecnt == 0 || t < s.ats[0]) {\n\t\ti = 0;\n\t\twhile (s.ttis[i].tt_isdst)\n\t\t\tif (++i >= s.timecnt) {\n\t\t\t\ti = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t} else {\n\t\tfor (i = 1; i < s.timecnt; ++i)\n\t\t\tif (t < s.ats[i])\n\t\t\t\tbreak;\n\t\ti = s.types[i - 1];\n\t}\n\tttisp = &s.ttis[i];\n\t/*\n\t** To get (wrong) behavior that's compatible with System V Release 2.0\n\t** you'd replace the statement below with\n\t**\ttmp = offtime((time_t) (t + ttisp->tt_gmtoff), 0L);\n\t*/\n\ttmp = offtime(&t, ttisp->tt_gmtoff);\n\ttmp->tm_isdst = ttisp->tt_isdst;\n\ttzname[tmp->tm_isdst] = &s.chars[ttisp->tt_abbrind];\n\ttmp->tm_zone = &s.chars[ttisp->tt_abbrind];\n\treturn tmp;\n}\n\nstruct tm *\ngmtime(clock)\n        const time_t *clock;\n{\n\tregister struct tm *\ttmp;\n\n\ttmp = offtime(clock, 0L);\n\ttzname[0] = \"GMT\";\n\ttmp->tm_zone = \"GMT\";\t\t/* UCT ? */\n\treturn tmp;\n}\n\nstatic int\tmon_lengths[2][MONS_PER_YEAR] = {\n\t{ 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 },\n\t{ 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 },\n};\n\nstatic int\tyear_lengths[2] = {\n\tDAYS_PER_NYEAR, DAYS_PER_LYEAR\n};\n\nstruct tm *\nofftime(clock, offset)\ntime_t *\tclock;\nlong\t\toffset;\n{\n\tregister struct tm *\ttmp;\n\tregister long\t\tdays;\n\tregister long\t\trem;\n\tregister int\t\ty;\n\tregister int\t\tyleap;\n\tregister int *\t\tip;\n\tstatic struct tm\ttm;\n\n\ttmp = &tm;\n\tdays = *clock / SECS_PER_DAY;\n\trem = *clock % SECS_PER_DAY;\n\trem += offset;\n\twhile (rem < 0) {\n\t\trem += SECS_PER_DAY;\n\t\t--days;\n\t}\n\twhile (rem >= SECS_PER_DAY) {\n\t\trem -= SECS_PER_DAY;\n\t\t++days;\n\t}\n\ttmp->tm_hour = (int) (rem / SECS_PER_HOUR);\n\trem = rem % SECS_PER_HOUR;\n\ttmp->tm_min = (int) (rem / SECS_PER_MIN);\n\ttmp->tm_sec = (int) (rem % SECS_PER_MIN);\n\ttmp->tm_wday = (int) ((EPOCH_WDAY + days) % DAYS_PER_WEEK);\n\tif (tmp->tm_wday < 0)\n\t\ttmp->tm_wday += DAYS_PER_WEEK;\n\ty = EPOCH_YEAR;\n\tif (days >= 0)\n\t\tfor ( ; ; ) {\n\t\t\tyleap = isleap(y);\n\t\t\tif (days < (long) year_lengths[yleap])\n\t\t\t\tbreak;\n\t\t\t++y;\n\t\t\tdays = days - (long) year_lengths[yleap];\n\t\t}\n\telse do {\n\t\t--y;\n\t\tyleap = isleap(y);\n\t\tdays = days + (long) year_lengths[yleap];\n\t} while (days < 0);\n\ttmp->tm_year = y - TM_YEAR_BASE;\n\ttmp->tm_yday = (int) days;\n\tip = mon_lengths[yleap];\n\tfor (tmp->tm_mon = 0; days >= (long) ip[tmp->tm_mon]; ++(tmp->tm_mon))\n\t\tdays = days - (long) ip[tmp->tm_mon];\n\ttmp->tm_mday = (int) (days + 1);\n\ttmp->tm_isdst = 0;\n\ttmp->tm_zone = \"\";\n\ttmp->tm_gmtoff = offset;\n\treturn tmp;\n}\n"
  },
  {
    "path": "lib/libc/gen/ctype_.c",
    "content": "#include <ctype.h>\n\nchar _ctype_[1 + 256] = {\n\t0,\n\t_C,\t_C,\t_C,\t_C,\t_C,\t_C,\t_C,\t_C,\n\t_C,\t_C|_S,\t_C|_S,\t_C|_S,\t_C|_S,\t_C|_S,\t_C,\t_C,\n\t_C,\t_C,\t_C,\t_C,\t_C,\t_C,\t_C,\t_C,\n\t_C,\t_C,\t_C,\t_C,\t_C,\t_C,\t_C,\t_C,\n\t_S|_B,\t_P,\t_P,\t_P,\t_P,\t_P,\t_P,\t_P,\n\t_P,\t_P,\t_P,\t_P,\t_P,\t_P,\t_P,\t_P,\n\t_N,\t_N,\t_N,\t_N,\t_N,\t_N,\t_N,\t_N,\n\t_N,\t_N,\t_P,\t_P,\t_P,\t_P,\t_P,\t_P,\n\t_P,\t_U|_X,\t_U|_X,\t_U|_X,\t_U|_X,\t_U|_X,\t_U|_X,\t_U,\n\t_U,\t_U,\t_U,\t_U,\t_U,\t_U,\t_U,\t_U,\n\t_U,\t_U,\t_U,\t_U,\t_U,\t_U,\t_U,\t_U,\n\t_U,\t_U,\t_U,\t_P,\t_P,\t_P,\t_P,\t_P,\n\t_P,\t_L|_X,\t_L|_X,\t_L|_X,\t_L|_X,\t_L|_X,\t_L|_X,\t_L,\n\t_L,\t_L,\t_L,\t_L,\t_L,\t_L,\t_L,\t_L,\n\t_L,\t_L,\t_L,\t_L,\t_L,\t_L,\t_L,\t_L,\n\t_L,\t_L,\t_L,\t_P,\t_P,\t_P,\t_P,\t_C\n};\n"
  },
  {
    "path": "lib/libc/gen/daemon.c",
    "content": "/*-\n * Copyright (c) 1990, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <fcntl.h>\n#include <sys/ioctl.h>\n#include <unistd.h>\n#include <paths.h>\n\nint\ndaemon(nochdir, noclose)\n\tint nochdir, noclose;\n{\n\tregister int fd;\n\n\tswitch (fork()) {\n\tcase -1:\n\t\treturn (-1);\n\tcase 0:\n\t\tbreak;\n\tdefault:\n\t\t_exit(0);\n\t}\n\n\tif ((fd = open(_PATH_TTY, O_RDWR)) >= 0) {\n\t\tioctl(fd, TIOCNOTTY, 0);\n\t\tclose(fd);\n\t}\n\n\tif (!nochdir)\n\t\t(void)chdir(\"/\");\n\n\tif (!noclose && (fd = open(_PATH_DEVNULL, O_RDWR, 0)) != -1) {\n\t\t(void)dup2(fd, 0);\n\t\t(void)dup2(fd, 1);\n\t\t(void)dup2(fd, 2);\n\t\tif (fd > 2)\n\t\t\t(void)close(fd);\n\t}\n\treturn(0);\n}\n"
  },
  {
    "path": "lib/libc/gen/devname.c",
    "content": "/*\n * Copyright (c) 1989, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/types.h>\n#include <sys/dir.h>\n#include <sys/stat.h>\n#include <fcntl.h>\n#include <paths.h>\n#include <stdio.h>\n#include <string.h>\n#include <unistd.h>\n\nchar *\ndevname(dev, type)\n\tdev_t dev;\n\tmode_t type;\n{\n        DIR *dir;\n        struct direct *entry;\n        char filename[40];\n        struct stat st;\n\n        dir = opendir(\"/dev\");\n        if (dir == NULL) {\n                perror(\"/dev\");\n\t\treturn \"??\";\n        }\n        strcpy(filename, \"/dev/\");\n        while ((entry = readdir(dir)) != NULL) {\n                strcpy(filename+5, entry->d_name);\n                if (stat (filename, &st) < 0)\n                        continue;\n                if (! S_ISCHR(st.st_mode) && ! S_ISBLK(st.st_mode))\n                        continue;\n                if (st.st_rdev == dev) {\n                        closedir(dir);\n                        return entry->d_name;\n                }\n        }\n        closedir(dir);\n\treturn \"??\";\n}\n"
  },
  {
    "path": "lib/libc/gen/dirname.c",
    "content": "/*\t$OpenBSD: dirname.c,v 1.17 2020/10/20 19:30:14 naddy Exp $\t*/\n\n/*\n * Copyright (c) 1997, 2004 Todd C. Miller <millert@openbsd.org>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include <errno.h>\n#include <libgen.h>\n#include <limits.h>\n#include <string.h>\n\nchar *\ndirname(char *path)\n{\n\tstatic char dname[PATH_MAX];\n\tsize_t len;\n\tconst char *endp;\n\n\t/* Empty or NULL string gets treated as \".\" */\n\tif (path == NULL || *path == '\\0') {\n\t\tdname[0] = '.';\n\t\tdname[1] = '\\0';\n\t\treturn (dname);\n\t}\n\n\t/* Strip any trailing slashes */\n\tendp = path + strlen(path) - 1;\n\twhile (endp > path && *endp == '/')\n\t\tendp--;\n\n\t/* Find the start of the dir */\n\twhile (endp > path && *endp != '/')\n\t\tendp--;\n\n\t/* Either the dir is \"/\" or there are no slashes */\n\tif (endp == path) {\n\t\tdname[0] = *endp == '/' ? '/' : '.';\n\t\tdname[1] = '\\0';\n\t\treturn (dname);\n\t} else {\n\t\t/* Move forward past the separating slashes */\n\t\tdo {\n\t\t\tendp--;\n\t\t} while (endp > path && *endp == '/');\n\t}\n\n\tlen = endp - path + 1;\n\tif (len >= sizeof(dname)) {\n\t\terrno = ENAMETOOLONG;\n\t\treturn (NULL);\n\t}\n\tmemcpy(dname, path, len);\n\tdname[len] = '\\0';\n\treturn (dname);\n}\n"
  },
  {
    "path": "lib/libc/gen/ecvt.c",
    "content": "/*\n * ecvt converts to decimal\n * the number of digits is specified by ndigit\n * decpt is set to the position of the decimal point\n * sign is set to 0 for positive, 1 for negative\n */\n#include <stdlib.h>\n\n#define\tNDIG\t80\n\nstatic char *\ncvt(arg, ndigits, decpt, sign, eflag)\n        double arg;\n        int ndigits, *decpt, *sign, eflag;\n{\n\tregister int r2;\n\tdouble fi, fj;\n\tregister char *p, *p1;\n\tstatic char buf[NDIG];\n\tdouble modf();\n\n\tif (ndigits < 0)\n\t\tndigits = 0;\n\tif (ndigits >= NDIG-1)\n\t\tndigits = NDIG-2;\n\tr2 = 0;\n\t*sign = 0;\n\tp = &buf[0];\n\tif (arg < 0) {\n\t\t*sign = 1;\n\t\targ = -arg;\n\t}\n\targ = modf(arg, &fi);\n\tp1 = &buf[NDIG];\n\t/*\n\t * Do integer part\n\t */\n\tif (fi != 0) {\n\t\tp1 = &buf[NDIG];\n\t\twhile (fi != 0) {\n\t\t\tfj = modf(fi/10, &fi);\n\t\t\t*--p1 = (int)((fj+.03)*10) + '0';\n\t\t\tr2++;\n\t\t}\n\t\twhile (p1 < &buf[NDIG])\n\t\t\t*p++ = *p1++;\n\t} else if (arg > 0) {\n\t\twhile ((fj = arg*10) < 1) {\n\t\t\targ = fj;\n\t\t\tr2--;\n\t\t}\n\t}\n\tp1 = &buf[ndigits];\n\tif (eflag == 0)\n\t\tp1 += r2;\n\t*decpt = r2;\n\tif (p1 < &buf[0]) {\n\t\tbuf[0] = '\\0';\n\t\treturn(buf);\n\t}\n\twhile (p <= p1 && p < &buf[NDIG]) {\n\t\targ *= 10;\n\t\targ = modf(arg, &fj);\n\t\t*p++ = (int)fj + '0';\n\t}\n\tif (p1 >= &buf[NDIG]) {\n\t\tbuf[NDIG-1] = '\\0';\n\t\treturn(buf);\n\t}\n\tp = p1;\n\t*p1 += 5;\n\twhile (*p1 > '9') {\n\t\t*p1 = '0';\n\t\tif (p1 > buf)\n\t\t\t++*--p1;\n\t\telse {\n\t\t\t*p1 = '1';\n\t\t\t(*decpt)++;\n\t\t\tif (eflag == 0) {\n\t\t\t\tif (p > buf)\n\t\t\t\t\t*p = '0';\n\t\t\t\tp++;\n\t\t\t}\n\t\t}\n\t}\n\t*p = '\\0';\n\treturn(buf);\n}\n\nchar *\necvt(arg, ndigits, decpt, sign)\n        double arg;\n        int ndigits, *decpt, *sign;\n{\n\treturn cvt(arg, ndigits, decpt, sign, 1);\n}\n\nchar *\nfcvt(arg, ndigits, decpt, sign)\n        double arg;\n        int ndigits, *decpt, *sign;\n{\n\treturn cvt(arg, ndigits, decpt, sign, 0);\n}\n"
  },
  {
    "path": "lib/libc/gen/err.c",
    "content": "/*-\n * Copyright (c) 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n#include <errno.h>\n\n#ifdef __STDC__\n#include <stdarg.h>\n#else\n#include <varargs.h>\n#endif\n\n/*\n * Helper routines.  Repeated constructs of the form \"%s: \" used up too\n * much D space.  On a pdp-11 code can be overlaid but Data space is worth\n * conserving.  An extra function call or two handling an error condition is\n * a reasonable trade for 20 or 30 bytes of D space.\n */\nstatic void\nputcolsp()\n{\n\tfputc (':', stderr);\n\tfputc (' ', stderr);\n}\n\nstatic void\nputprog()\n{\n\tfputs (__progname, stderr);\n\tputcolsp();\n}\n\nvoid\nverr (eval, fmt, ap)\n\tint eval;\n\tconst char *fmt;\n\tva_list ap;\n{\n\tint sverrno;\n\n\tsverrno = errno;\n\tputprog();\n\tif (fmt != NULL) {\n\t\t(void)vfprintf(stderr, fmt, ap);\n\t\tputcolsp();\n\t}\n\t(void)fputs(strerror(sverrno), stderr);\n\t(void)fputc('\\n', stderr);\n\texit(eval);\n}\n\nvoid\n#ifdef __STDC__\nerr (int eval, const char *fmt, ...)\n#else\nerr (eval, fmt, va_alist)\n\tint eval;\n\tconst char *fmt;\n\tva_dcl\n#endif\n{\n\tva_list ap;\n#if __STDC__\n\tva_start(ap, fmt);\n#else\n\tva_start(ap);\n#endif\n\tverr(eval, fmt, ap);\n\tva_end(ap);\n}\n\nvoid\nverrx (eval, fmt, ap)\n\tint eval;\n\tconst char *fmt;\n\tva_list ap;\n{\n\tputprog();\n\tif (fmt != NULL)\n\t\t(void)vfprintf(stderr, fmt, ap);\n\t(void)fputc('\\n', stderr);\n\texit(eval);\n}\n\nvoid\n#if __STDC__\nerrx (int eval, const char *fmt, ...)\n#else\nerrx (eval, fmt, va_alist)\n\tint eval;\n\tconst char *fmt;\n\tva_dcl\n#endif\n{\n\tva_list ap;\n#if __STDC__\n\tva_start(ap, fmt);\n#else\n\tva_start(ap);\n#endif\n\tverrx(eval, fmt, ap);\n\tva_end(ap);\n}\n\nvoid\nvwarn (fmt, ap)\n\tconst char *fmt;\n\tva_list ap;\n{\n\tint sverrno;\n\n\tsverrno = errno;\n\tputprog();\n\tif (fmt != NULL) {\n\t\t(void)vfprintf(stderr, fmt, ap);\n\t\tputcolsp();\n\t}\n\t(void)fputs(strerror(sverrno), stderr);\n\t(void)fputc('\\n', stderr);\n}\n\nvoid\n#if __STDC__\nwarn (const char *fmt, ...)\n#else\nwarn(fmt, va_alist)\n\tconst char *fmt;\n\tva_dcl\n#endif\n{\n\tva_list ap;\n#if __STDC__\n\tva_start(ap, fmt);\n#else\n\tva_start(ap);\n#endif\n\tvwarn(fmt, ap);\n\tva_end(ap);\n}\n\nvoid\nvwarnx (fmt, ap)\n\tconst char *fmt;\n\tva_list ap;\n{\n\tputprog();\n\tif (fmt != NULL)\n\t\t(void)vfprintf(stderr, fmt, ap);\n\t(void)fputc('\\n', stderr);\n}\n\nvoid\n#ifdef __STDC__\nwarnx (const char *fmt, ...)\n#else\nwarnx(fmt, va_alist)\n\tchar *fmt;\n\tva_dcl\n#endif\n{\n\tva_list ap;\n#ifdef __STDC__\n\tva_start(ap, fmt);\n#else\n\tva_start(ap);\n#endif\n\tvwarnx(fmt, ap);\n\tva_end(ap);\n}\n"
  },
  {
    "path": "lib/libc/gen/execvp.c",
    "content": "/*\n *\texeclp(name, arg,...,0)\t(like execl, but does path search)\n *\texecvp(name, argv)\t(like execv, but does path search)\n */\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n#include <errno.h>\n#include <paths.h>\n\nstatic\tchar shell[] =\t\"/bin/sh\";\n\nint\nexeclp(const char *name, const char *argv, ...)\n{\n\treturn execvp (name, (char * const*) &argv);\n}\n\nstatic char *\nexecat(s1, s2, si)\n\tregister char *s1, *s2;\n\tchar *si;\n{\n\tregister char *s;\n\n\ts = si;\n\twhile (*s1 && *s1 != ':')\n\t\t*s++ = *s1++;\n\tif (si != s)\n\t\t*s++ = '/';\n\twhile (*s2)\n\t\t*s++ = *s2++;\n\t*s = '\\0';\n\treturn(*s1? ++s1: 0);\n}\n\nint\nexecvp(name, argv)\n\tconst char *name;\n\tchar *const *argv;\n{\n\tchar *pathstr;\n\tregister char *cp;\n\tchar fname[128];\n\tchar *newargs[256];\n\tint i;\n\tregister unsigned etxtbsy = 1;\n\tregister int eacces = 0;\n\n\tpathstr = getenv(\"PATH\");\n\tif (! pathstr)\n\t\tpathstr = _PATH_STDPATH;\n\tcp = strchr(name, '/') ? \"\" : pathstr;\n\n\tdo {\n\t\tcp = execat(cp, name, fname);\n\tretry:\n\t\texecv(fname, argv);\n\t\tswitch(errno) {\n\t\tcase ENOEXEC:\n\t\t\tnewargs[0] = \"sh\";\n\t\t\tnewargs[1] = fname;\n\t\t\tfor (i=1; (newargs[i+1] = argv[i]); i++) {\n\t\t\t\tif (i>=254) {\n\t\t\t\t\terrno = E2BIG;\n\t\t\t\t\treturn(-1);\n\t\t\t\t}\n\t\t\t}\n\t\t\texecv(shell, newargs);\n\t\t\treturn(-1);\n\t\tcase ETXTBSY:\n\t\t\tif (++etxtbsy > 5)\n\t\t\t\treturn(-1);\n\t\t\tsleep(etxtbsy);\n\t\t\tgoto retry;\n\t\tcase EACCES:\n\t\t\teacces++;\n\t\t\tbreak;\n\t\tcase ENOMEM:\n\t\tcase E2BIG:\n\t\t\treturn(-1);\n\t\t}\n\t} while (cp);\n\tif (eacces)\n\t\terrno = EACCES;\n\treturn(-1);\n}\n"
  },
  {
    "path": "lib/libc/gen/fabs.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\ndouble\nfabs(arg)\n\tdouble arg;\n{\n\treturn(arg < 0 ? -arg : arg);\n}\n"
  },
  {
    "path": "lib/libc/gen/fakcu.c",
    "content": "/*\n * Null cleanup routine to resolve reference in exit()\n * if not using stdio.\n */\nvoid __attribute__((weak)) _cleanup()\n{\n}\n"
  },
  {
    "path": "lib/libc/gen/ffs.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * ffs -- vax ffs instruction\n */\nint\nffs(mask)\n\tregister int mask;\n{\n\tregister int cnt;\n\n\tif (mask == 0)\n\t\treturn(0);\n\tfor (cnt = 1; !(mask&1); cnt++)\n\t\tmask >>= 1;\n\treturn(cnt);\n}\n"
  },
  {
    "path": "lib/libc/gen/frexp.c",
    "content": "/*\n * the call\n *\tx = frexp(arg,&exp);\n * must return a double fp quantity x which is <1.0\n * and the corresponding binary exponent \"exp\".\n * such that\n *\targ = x*2^exp\n * if the argument is 0.0, return 0.0 mantissa and 0 exponent.\n */\n#include <math.h>\n\ndouble\nfrexp(x, i)\n        double x;\n        int *i;\n{\n\tint neg;\n\tint j;\n\n\tj = 0;\n\tneg = 0;\n\tif (x < 0) {\n\t\tx = -x;\n\t\tneg = 1;\n\t}\n\tif (x >= 1.0)\n\t\twhile (x >= 1.0) {\n\t\t\tj = j+1;\n\t\t\tx = x/2;\n\t\t}\n\telse if (x < 0.5 && x != 0.0)\n\t\twhile (x < 0.5) {\n\t\t\tj = j-1;\n\t\t\tx = 2*x;\n\t\t}\n\t*i = j;\n\tif (neg)\n            x = -x;\n\treturn(x);\n}\n"
  },
  {
    "path": "lib/libc/gen/fstab.c",
    "content": "/*\n * Copyright (c) 1980, 1988, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <errno.h>\n#include <fstab.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <strings.h>\n#include <unistd.h>\n#include <paths.h>\n#include <sys/uio.h>\n\nstatic FILE *_fs_fp;\nstatic struct fstab _fs_fstab;\n\nstatic void error();\nstatic int fstabscan();\n\nstatic int\nfstabscan()\n{\n\tchar *cp;\n\tregister char *bp;\n#define\tMAXLINELENGTH\t256\n\tstatic char line[MAXLINELENGTH];\n\tchar subline[MAXLINELENGTH], *colon = \":\";\n\tint typexx;\n\n\tfor (;;) {\n\t\tif (!fgets(line, sizeof(line), _fs_fp))\n\t\t\treturn(0);\n\t\tbp = index(line, '\\n');\n\t\tif (!bp)\n\t\t\treturn(0);\n\t\t*bp = '\\0';\n\t\tcp = line;\n/* OLD_STYLE_FSTAB */\n\t\tif (!strpbrk(cp, \" \\t\")) {\n\t\t\t_fs_fstab.fs_spec = strsep(&cp, colon);\n\t\t\t_fs_fstab.fs_file = strsep(&cp, colon);\n\t\t\t_fs_fstab.fs_type = strsep(&cp, colon);\n\t\t\tif (_fs_fstab.fs_type) {\n\t\t\t\tif (!strcmp(_fs_fstab.fs_type, FSTAB_XX))\n\t\t\t\t\tcontinue;\n\t\t\t\t_fs_fstab.fs_mntops = _fs_fstab.fs_type;\n\t\t\t\t_fs_fstab.fs_vfstype =\n\t\t\t\t    strcmp(_fs_fstab.fs_type, FSTAB_SW) ?\n\t\t\t\t    \"ufs\" : \"swap\";\n                                bp = strsep(&cp, colon);\n\t\t\t\tif (bp) {\n\t\t\t\t\t_fs_fstab.fs_freq = atoi(bp);\n\t\t\t\t\tbp = strsep(&cp, colon);\n\t\t\t\t\tif (bp) {\n\t\t\t\t\t\t_fs_fstab.fs_passno = atoi(bp);\n\t\t\t\t\t\treturn(1);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tgoto bad;\n\t\t}\n/* OLD_STYLE_FSTAB */\n\t\t_fs_fstab.fs_spec = strtok(cp, \" \\t\");\n\t\tif (!_fs_fstab.fs_spec || *_fs_fstab.fs_spec == '#')\n\t\t\tcontinue;\n\t\t_fs_fstab.fs_file = strtok((char *)NULL, \" \\t\");\n\t\t_fs_fstab.fs_vfstype = strtok((char *)NULL, \" \\t\");\n\t\t_fs_fstab.fs_mntops = strtok((char *)NULL, \" \\t\");\n\t\tif (_fs_fstab.fs_mntops == NULL)\n\t\t\tgoto bad;\n\t\t_fs_fstab.fs_freq = 0;\n\t\t_fs_fstab.fs_passno = 0;\n\t\tif ((cp = strtok((char *)NULL, \" \\t\")) != NULL) {\n\t\t\t_fs_fstab.fs_freq = atoi(cp);\n\t\t\tif ((cp = strtok((char *)NULL, \" \\t\")) != NULL)\n\t\t\t\t_fs_fstab.fs_passno = atoi(cp);\n\t\t}\n\t\tstrcpy(subline, _fs_fstab.fs_mntops);\n\t\tfor (typexx = 0, cp = strtok(subline, \",\"); cp;\n\t\t     cp = strtok((char *)NULL, \",\")) {\n\t\t\tif (strlen(cp) != 2)\n\t\t\t\tcontinue;\n\t\t\tif (!strcmp(cp, FSTAB_RW)) {\n\t\t\t\t_fs_fstab.fs_type = FSTAB_RW;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (!strcmp(cp, FSTAB_RQ)) {\n\t\t\t\t_fs_fstab.fs_type = FSTAB_RQ;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (!strcmp(cp, FSTAB_RO)) {\n\t\t\t\t_fs_fstab.fs_type = FSTAB_RO;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (!strcmp(cp, FSTAB_SW)) {\n\t\t\t\t_fs_fstab.fs_type = FSTAB_SW;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (!strcmp(cp, FSTAB_XX)) {\n\t\t\t\t_fs_fstab.fs_type = FSTAB_XX;\n\t\t\t\ttypexx++;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (typexx)\n\t\t\tcontinue;\n\t\tif (cp != NULL)\n\t\t\treturn(1);\n\nbad:\t\t/* no way to distinguish between EOF and syntax error */\n\t\terror(EFTYPE);\n\t}\n\t/* NOTREACHED */\n}\n\nstruct fstab *\ngetfsent()\n{\n\tif (! _fs_fp && ! setfsent())\n\t\treturn 0;\n\tif (! fstabscan())\n\t\treturn 0;\n\treturn &_fs_fstab;\n}\n\nstruct fstab *\ngetfsspec(name)\n\tregister char *name;\n{\n\tif (setfsent())\n\t\twhile (fstabscan())\n\t\t\tif (!strcmp(_fs_fstab.fs_spec, name))\n\t\t\t\treturn(&_fs_fstab);\n\treturn((struct fstab *)NULL);\n}\n\nstruct fstab *\ngetfsfile(name)\n\tregister char *name;\n{\n\tif (setfsent())\n\t\twhile (fstabscan())\n\t\t\tif (!strcmp(_fs_fstab.fs_file, name))\n\t\t\t\treturn(&_fs_fstab);\n\treturn((struct fstab *)NULL);\n}\n\nint\nsetfsent()\n{\n\tif (_fs_fp) {\n\t\trewind(_fs_fp);\n\t\treturn(1);\n\t}\n\t_fs_fp = fopen(_PATH_FSTAB, \"r\");\n\tif (_fs_fp)\n\t\treturn(1);\n\terror(errno);\n\treturn(0);\n}\n\nvoid\nendfsent()\n{\n\tif (_fs_fp) {\n\t\t(void)fclose(_fs_fp);\n\t\t_fs_fp = NULL;\n\t}\n}\n\nstatic void\nerror(err)\n\tint err;\n{\n\tregister int saverrno;\n\n\tsaverrno = errno;\n\terrno = err;\n\twarn(\"%s\", _PATH_FSTAB);\n\terrno = saverrno;\n}\n"
  },
  {
    "path": "lib/libc/gen/gcvt.c",
    "content": "/*\n * gcvt  - Floating output conversion to\n * minimal length string\n */\n#include <stdlib.h>\n\nchar *\ngcvt(number, ndigit, buf)\ndouble number;\nint ndigit;\nchar *buf;\n{\n\tint sign, decpt;\n\tregister char *p1, *p2;\n\tregister int i;\n\n\tp1 = ecvt(number, ndigit, &decpt, &sign);\n\tp2 = buf;\n\tif (sign)\n\t\t*p2++ = '-';\n\tfor (i=ndigit-1; i>0 && p1[i]=='0'; i--)\n\t\tndigit--;\n\tif ((decpt >= 0 && decpt-ndigit > 4) ||\n\t    (decpt < 0 && decpt < -3)) { /* use E-style */\n\t\tdecpt--;\n\t\t*p2++ = *p1++;\n\t\t*p2++ = '.';\n\t\tfor (i=1; i<ndigit; i++)\n\t\t\t*p2++ = *p1++;\n\t\t*p2++ = 'e';\n\t\tif (decpt<0) {\n\t\t\tdecpt = -decpt;\n\t\t\t*p2++ = '-';\n\t\t} else\n\t\t\t*p2++ = '+';\n\t\t*p2++ = decpt/10 + '0';\n\t\t*p2++ = decpt%10 + '0';\n\t} else {\n\t\tif (decpt<=0) {\n\t\t\tif (*p1!='0')\n\t\t\t\t*p2++ = '.';\n\t\t\twhile (decpt<0) {\n\t\t\t\tdecpt++;\n\t\t\t\t*p2++ = '0';\n\t\t\t}\n\t\t}\n\t\tfor (i=1; i<=ndigit; i++) {\n\t\t\t*p2++ = *p1++;\n\t\t\tif (i==decpt)\n\t\t\t\t*p2++ = '.';\n\t\t}\n\t\tif (ndigit<decpt) {\n\t\t\twhile (ndigit++<decpt)\n\t\t\t\t*p2++ = '0';\n\t\t\t*p2++ = '.';\n\t\t}\n\t}\n\tif (p2[-1]=='.')\n\t\tp2--;\n\t*p2 = '\\0';\n\treturn(buf);\n}\n"
  },
  {
    "path": "lib/libc/gen/getenv.c",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * This file may be freely redistributed provided that this\n * notice remains attached.\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n\n/*\n * getenv(name) --\n *\tReturns ptr to value associated with name, if any, else NULL.\n */\nchar *\ngetenv(name)\n\tconst char *name;\n{\n\tint\toffset;\n\tchar\t*_findenv();\n\n\treturn(_findenv(name,&offset));\n}\n\n/*\n * _findenv(name,offset) --\n *\tReturns pointer to value associated with name, if any, else NULL.\n *\tSets offset to be the offset of the name/value combination in the\n *\tenvironmental array, for use by setenv(3) and unsetenv(3).\n *\tExplicitly removes '=' in argument name.\n *\n *\tThis routine *should* be a static; don't use it.\n */\nchar *\n_findenv(name, offset)\n\tregister const char *name;\n\tint\t*offset;\n{\n\tregister int\tlen;\n\tregister char\t**P, *C;\n\tregister const char *E;\n\n        len = 0;\n\tfor (E = name; *E && *E != '='; ++E)\n                ++len;\n\tfor (P = environ; *P; ++P)\n\t\tif (!strncmp(*P, name, len))\n\t\t\tif (*(C = *P + len) == '=') {\n\t\t\t\t*offset = P - environ;\n\t\t\t\treturn(++C);\n\t\t\t}\n\treturn(NULL);\n}\n"
  },
  {
    "path": "lib/libc/gen/getgrent.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <sys/types.h>\n#include <grp.h>\n\n#define\tMAXGRP\t200\n\nstatic char GROUP[] = \"/etc/group\";\nstatic FILE *grf = NULL;\nstatic char line[256+1];\nstatic struct group group;\nstatic char *gr_mem[MAXGRP];\n\nvoid\nsetgrent()\n{\n\tif (!grf)\n\t\tgrf = fopen(GROUP, \"r\");\n\telse\n\t\trewind(grf);\n}\n\nvoid\nendgrent()\n{\n\tif (grf) {\n\t\tfclose(grf);\n\t\tgrf = NULL;\n\t}\n}\n\nstatic char *\ngrskip(p,c)\n        register char *p;\n        register int c;\n{\n\twhile(*p && *p != c) ++p;\n\tif (*p) *p++ = 0;\n\treturn(p);\n}\n\nstruct group *\ngetgrent()\n{\n\tregister char *p, **q;\n\n\tif (!grf && !(grf = fopen(GROUP, \"r\")))\n\t\treturn(NULL);\n\tif (!(p = fgets(line, sizeof(line)-1, grf)))\n\t\treturn(NULL);\n\tgroup.gr_name = p;\n\tgroup.gr_passwd = p = grskip(p,':');\n\tgroup.gr_gid = atoi(p = grskip(p,':'));\n\tgroup.gr_mem = gr_mem;\n\tp = grskip(p,':');\n\tgrskip(p,'\\n');\n\tq = gr_mem;\n\twhile (*p) {\n\t\tif (q < &gr_mem[MAXGRP-1])\n\t\t\t*q++ = p;\n\t\tp = grskip(p,',');\n\t}\n\t*q = NULL;\n\treturn(&group);\n}\n"
  },
  {
    "path": "lib/libc/gen/getgrgid.c",
    "content": "#include <sys/types.h>\n#include <grp.h>\n\nstruct group *\ngetgrgid(gid)\n        register gid_t gid;\n{\n\tregister struct group *p;\n\n\tsetgrent();\n\twhile ((p = getgrent()) && p->gr_gid != gid);\n\tendgrent();\n\treturn(p);\n}\n"
  },
  {
    "path": "lib/libc/gen/getgrnam.c",
    "content": "#include <sys/types.h>\n#include <grp.h>\n#include <string.h>\n\nstruct group *\ngetgrnam(name)\n        register const char *name;\n{\n\tregister struct group *p;\n\n\tsetgrent();\n\twhile ((p = getgrent()) && strcmp(p->gr_name, name));\n\tendgrent();\n\treturn(p);\n}\n"
  },
  {
    "path": "lib/libc/gen/getgrouplist.c",
    "content": "/*\n * Copyright (c) 1991, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n/*\n * get credential\n */\n#include <sys/types.h>\n#include <string.h>\n#include <grp.h>\n\nint\ngetgrouplist(uname, agroup, groups, grpcnt)\n\tchar *uname;\n\tgid_t agroup;\n\tregister gid_t *groups;\n\tint *grpcnt;\n{\n\tregister struct group *grp;\n\tint i, ngroups, ret, maxgroups;\n\n\tret = 0;\n\tngroups = 0;\n\tmaxgroups = *grpcnt;\n\t/*\n\t * When installing primary group, duplicate it;\n\t * the first element of groups is the effective gid\n\t * and will be overwritten when a setgid file is executed.\n\t */\n\tgroups[ngroups++] = agroup;\n\tif (maxgroups > 1)\n\t\tgroups[ngroups++] = agroup;\n\t/*\n\t * Scan the group file to find additional groups.\n\t */\n\tsetgrent();\n\twhile ((grp = getgrent())) {\n\t\tif (grp->gr_gid == agroup)\n\t\t\tcontinue;\n\t\tfor (i = 0; grp->gr_mem[i]; i++) {\n\t\t\tif (!strcmp(grp->gr_mem[i], uname)) {\n\t\t\t\tif (ngroups >= maxgroups) {\n\t\t\t\t\tret = -1;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tgroups[ngroups++] = grp->gr_gid;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\tendgrent();\n\t*grpcnt = ngroups;\n\treturn (ret);\n}\n"
  },
  {
    "path": "lib/libc/gen/gethostname.c",
    "content": "/*\n * Copyright (c) 1989, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/param.h>\n#include <sys/sysctl.h>\n\nint\ngethostname(name, namelen)\n\tchar *name;\n\tint namelen;\n{\n\tint mib[2];\n\tsize_t size;\n\n\tmib[0] = CTL_KERN;\n\tmib[1] = KERN_HOSTNAME;\n\tsize = namelen;\n\tif (sysctl(mib, 2, name, &size, NULL, 0) == -1)\n\t\treturn (-1);\n\treturn (0);\n}\n"
  },
  {
    "path": "lib/libc/gen/getloadavg.c",
    "content": "/*-\n * Copyright (c) 1989, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/param.h>\n#include <sys/sysctl.h>\n#include <sys/vmparam.h>\n\n/*\n * getloadavg() -- Get system load averages.\n *\n * Put `nelem' samples into `loadavg' array.\n * Return number of samples retrieved, or -1 on error.\n */\nint\ngetloadavg(loadavg, nelem)\n\tunsigned loadavg[];\n\tregister int nelem;\n{\n\tstruct loadavg loadinfo;\n\tregister int i;\n\tint mib[2];\n\tsize_t size;\n\n\tmib[0] = CTL_VM;\n\tmib[1] = VM_LOADAVG;\n\tsize = sizeof(loadinfo);\n\tif (sysctl(mib, 2, &loadinfo, &size, NULL, 0) < 0)\n\t\treturn (-1);\n\n\tnelem = MIN(nelem, sizeof(loadinfo.ldavg) / sizeof(short));\n\tfor (i = 0; i < nelem; i++)\n\t\tloadavg[i] = 100 * loadinfo.ldavg[i] / loadinfo.fscale;\n\treturn (nelem);\n}\n"
  },
  {
    "path": "lib/libc/gen/getlogin.c",
    "content": "/*\n * Copyright (c) 1988, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <unistd.h>\n\nchar *\ngetlogin()\n{\n\treturn 0;\n}\n\nint\nsetlogin (name)\n\tconst char *name;\n{\n        return 0;\n}\n"
  },
  {
    "path": "lib/libc/gen/getmntinfo.c",
    "content": "/*\n * Copyright (c) 1989, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/param.h>\n#include <sys/mount.h>\n#include <stdlib.h>\n\n/*\n * Return information about mounted filesystems.\n */\nint\ngetmntinfo(mntbufp, flags)\n\tregister struct statfs **mntbufp;\n\tint flags;\n{\n\tstatic struct statfs *mntbuf;\n\tstatic int mntsize;\n\tstatic int bufsize;\n\n\tif (mntsize <= 0 && (mntsize = getfsstat(0, 0, MNT_NOWAIT)) < 0)\n\t\treturn (0);\n\tif (bufsize > 0 && (mntsize = getfsstat(mntbuf, bufsize, flags)) < 0)\n\t\treturn (0);\n\twhile (bufsize <= mntsize * sizeof(struct statfs)) {\n\t\tif (mntbuf)\n\t\t\tfree(mntbuf);\n\t\tbufsize = (mntsize + 1) * sizeof(struct statfs);\n\t\tif ((mntbuf = (struct statfs *)malloc(bufsize)) == 0)\n\t\t\treturn (0);\n\t\tif ((mntsize = getfsstat(mntbuf, bufsize, flags)) < 0)\n\t\t\treturn (0);\n\t}\n\t*mntbufp = mntbuf;\n\treturn (mntsize);\n}\n"
  },
  {
    "path": "lib/libc/gen/getpagesize.c",
    "content": "/*\n * Copyright (c) 1989, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/param.h>\n#include <sys/sysctl.h>\n\nint\ngetpagesize()\n{\n\tsize_t size;\n\tint mib[2], value;\n\n\tmib[0] = CTL_HW;\n\tmib[1] = HW_PAGESIZE;\n\tsize = sizeof(value);\n\tif (sysctl(mib, 2, &value, &size, NULL, 0) == -1)\n\t\treturn (-1);\n\treturn (value);\n}\n"
  },
  {
    "path": "lib/libc/gen/getpass.c",
    "content": "#include <stdio.h>\n#include <signal.h>\n#include <sgtty.h>\n#include <fcntl.h>\n\nchar *\ngetpass(prompt)\nchar *prompt;\n{\n\tstruct sgttyb ttyb;\n\tint flags;\n\tregister char *p;\n\tregister int c;\n\tFILE *fi;\n\tstatic char pbuf[9];\n\tsig_t sig;\n\n\tfi = fdopen(open(\"/dev/tty\", 2), \"r\");\n\tif (! fi)\n\t\tfi = stdin;\n\telse\n\t\tsetbuf(fi, (char *)NULL);\n\tsig = signal(SIGINT, SIG_IGN);\n\tioctl(fileno(fi), TIOCGETP, &ttyb);\n\tflags = ttyb.sg_flags;\n\tttyb.sg_flags &= ~ECHO;\n\tioctl(fileno(fi), TIOCSETP, &ttyb);\n\tfprintf(stderr, \"%s\", prompt); fflush(stderr);\n\tfor (p=pbuf; (c = getc(fi))!='\\n' && c!=EOF;) {\n\t\tif (p < &pbuf[8])\n\t\t\t*p++ = c;\n\t}\n\t*p = '\\0';\n\tfprintf(stderr, \"\\n\"); fflush(stderr);\n\tttyb.sg_flags = flags;\n\tioctl(fileno(fi), TIOCSETP, &ttyb);\n\tsignal(SIGINT, sig);\n\tif (fi != stdin)\n\t\tfclose(fi);\n\treturn(pbuf);\n}\n"
  },
  {
    "path": "lib/libc/gen/getpwent.c",
    "content": "/*\n * Copyright (c) 1988 The Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that the above copyright notice and this paragraph are\n * duplicated in all such forms and that any documentation,\n * advertising materials, and other materials related to such\n * distribution and use acknowledge that the software was developed\n * by the University of California, Berkeley.  The name of the\n * University may not be used to endorse or promote products derived\n * from this software without specific prior written permission.\n * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n */\n#include <sys/types.h>\n#include <string.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <sys/file.h>\n#include <stdio.h>\n#include <pwd.h>\n#include <strings.h>\n#include <fcntl.h>\n#include <paths.h>\n\nstatic FILE *_pw_fp;\nstatic struct passwd _pw_entry;\nstatic int _pw_stayopen;\nstatic char *_pw_file = _PATH_PASSWD;\n\n#define\tMAXLINELENGTH\t256\nstatic char line[MAXLINELENGTH];\n\nstatic int\nstart_pw()\n{\n\tif (_pw_fp) {\n\t\trewind(_pw_fp);\n\t\treturn(1);\n\t}\n\t_pw_fp = fopen(_pw_file, \"r\");\n\tif (_pw_fp)\n\t\treturn(1);\n\treturn(0);\n}\n\nstatic int\nscanpw()\n{\n\tregister char *cp;\n\tchar\t*bp;\n\tregister int ch;\n\n\tfor (;;) {\n\t\tif (!(fgets(line, sizeof(line), _pw_fp)))\n\t\t\treturn(0);\n\t\t/* skip lines that are too big */\n\t\tcp = strchr(line, '\\n');\n\t\tif (! cp) {\n\t\t\twhile ((ch = fgetc(_pw_fp)) != '\\n' && ch != EOF)\n\t\t\t\t;\n\t\t\tcontinue;\n\t\t}\n\t\t*cp = '\\0';\n\t\tbp = line;\n\t\t_pw_entry.pw_name = strsep(&bp, \":\");\n\t\t_pw_entry.pw_passwd = strsep(&bp, \":\");\n\t\tcp = strsep(&bp, \":\");\n\t\tif (! cp)\n\t\t\tcontinue;\n\t\t_pw_entry.pw_uid = atoi(cp);\n\t\tcp = strsep(&bp, \":\");\n\t\tif (! cp)\n\t\t\tcontinue;\n\t\t_pw_entry.pw_gid = atoi(cp);\n\t\t_pw_entry.pw_gecos = strsep(&bp, \":\");\n\t\t_pw_entry.pw_dir = strsep(&bp, \":\");\n\t\t_pw_entry.pw_shell = strsep(&bp, \":\");\n\t\tif (!_pw_entry.pw_shell)\n\t\t\tcontinue;\n\t\treturn(1);\n\t}\n\t/* NOTREACHED */\n}\n\nstatic void\ngetpw()\n{\n\tstatic char pwbuf[50];\n\toff_t lseek();\n\tlong pos;\n\tint fd, n;\n\tregister char *p;\n\n\tif (geteuid())\n\t\treturn;\n\t/*\n\t * special case; if it's the official password file, look in\n\t * the master password file, otherwise, look in the file itself.\n\t */\n\tp = strcmp(_pw_file, _PATH_PASSWD) == 0 ? _PATH_SHADOW : _pw_file;\n\tif ((fd = open(p, O_RDONLY, 0)) < 0)\n\t\treturn;\n\tpos = atol(_pw_entry.pw_passwd);\n\tif (lseek(fd, pos, L_SET) != pos)\n\t\tgoto bad;\n\tif ((n = read(fd, pwbuf, sizeof(pwbuf) - 1)) < 0)\n\t\tgoto bad;\n\tpwbuf[n] = '\\0';\n\tfor (p = pwbuf; *p; ++p)\n\t\tif (*p == ':') {\n\t\t\t*p = '\\0';\n\t\t\t_pw_entry.pw_passwd = pwbuf;\n\t\t\tbreak;\n\t\t}\nbad:\t(void)close(fd);\n}\n\nstruct passwd *\ngetpwent()\n{\n\tregister int rval;\n\n\tif (!_pw_fp && !start_pw())\n\t\treturn((struct passwd *)NULL);\n\trval = scanpw();\n\tif (! rval)\n\t        return 0;\n\tgetpw();\n\treturn &_pw_entry;\n}\n\nstruct passwd *\ngetpwnam(nam)\n\tchar *nam;\n{\n\tregister int rval;\n\n\tif (!start_pw())\n\t\treturn((struct passwd *)NULL);\n        for (rval = 0; scanpw();) {\n                if (!strcmp(nam, _pw_entry.pw_name)) {\n                        rval = 1;\n                        break;\n                }\n        }\n\tif (!_pw_stayopen)\n\t\tendpwent();\n\tif (! rval)\n\t        return 0;\n\tgetpw();\n\treturn &_pw_entry;\n}\n\nstruct passwd *\ngetpwuid(uid)\n\tint uid;\n{\n\tregister int rval;\n\n\tif (!start_pw())\n\t\treturn((struct passwd *)NULL);\n        for (rval = 0; scanpw();) {\n                if (_pw_entry.pw_uid == uid) {\n                        rval = 1;\n                        break;\n                }\n        }\n\tif (!_pw_stayopen)\n\t\tendpwent();\n\tif (! rval)\n\t        return 0;\n\tgetpw();\n\treturn &_pw_entry;\n}\n\nint\nsetpwent()\n{\n\treturn(setpassent(0));\n}\n\nint\nsetpassent(stayopen)\n\tint stayopen;\n{\n\tif (!start_pw())\n\t\treturn(0);\n\t_pw_stayopen = stayopen;\n\treturn(1);\n}\n\nvoid\nendpwent()\n{\n\tif (_pw_fp) {\n\t\t(void)fclose(_pw_fp);\n\t\t_pw_fp = 0;\n\t}\n}\n\nvoid\nsetpwfile(file)\n\tchar *file;\n{\n\t_pw_file = file;\n}\n"
  },
  {
    "path": "lib/libc/gen/getttyent.c",
    "content": "/*\n * Copyright (c) 1985 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <stdio.h>\n#include <string.h>\n#include <strings.h>\n#include <ttyent.h>\n\nstatic char TTYFILE[] = \"/etc/ttys\";\nstatic int zapchar;\nstatic FILE *tf = NULL;\n#define LINE 256\nstatic char line[LINE];\nstatic struct ttyent tty;\n\nvoid\nsetttyent()\n{\n\tif (tf == NULL)\n\t\ttf = fopen(TTYFILE, \"r\");\n\telse\n\t\trewind(tf);\n}\n\nvoid\nendttyent()\n{\n\tif (tf != NULL) {\n\t\t(void) fclose(tf);\n\t\ttf = NULL;\n\t}\n}\n\n#define QUOTED\t1\n\n/*\n * Skip over the current field, removing quotes,\n * and return a pointer to the next field.\n */\nstatic char *\nskip(p)\n\tregister char *p;\n{\n\tregister char *t = p;\n\tregister int c;\n\tregister int q = 0;\n\n\tfor (; (c = *p) != '\\0'; p++) {\n\t\tif (c == '\"') {\n\t\t\tq ^= QUOTED;\t/* obscure, but nice */\n\t\t\tcontinue;\n\t\t}\n\t\tif (q == QUOTED && *p == '\\\\' && *(p+1) == '\"')\n\t\t\tp++;\n\t\t*t++ = *p;\n\t\tif (q == QUOTED)\n\t\t\tcontinue;\n\t\tif (c == '#') {\n\t\t\tzapchar = c;\n\t\t\t*p = 0;\n\t\t\tbreak;\n\t\t}\n\t\tif (c == '\\t' || c == ' ' || c == '\\n') {\n\t\t\tzapchar = c;\n\t\t\t*p++ = 0;\n\t\t\twhile ((c = *p) == '\\t' || c == ' ' || c == '\\n')\n\t\t\t\tp++;\n\t\t\tbreak;\n\t\t}\n\t}\n\t*--t = '\\0';\n\treturn (p);\n}\n\nstatic char *\nvalue(p)\n\tregister char *p;\n{\n\tif ((p = index(p,'=')) == 0)\n\t\treturn(NULL);\n\tp++;\t\t\t/* get past the = sign */\n\treturn(p);\n}\n\nstruct ttyent *\ngetttyent()\n{\n\tregister char *p;\n\tregister int c;\n\n\tif (tf == NULL) {\n\t\tif ((tf = fopen(TTYFILE, \"r\")) == NULL)\n\t\t\treturn (NULL);\n\t}\n\tdo {\n\t\tp = fgets(line, LINE, tf);\n\t\tif (p == NULL)\n\t\t\treturn (NULL);\n\t\twhile ((c = *p) == '\\t' || c == ' ' || c == '\\n')\n\t\t\tp++;\n\t} while (c == '\\0' || c == '#');\n\tzapchar = 0;\n\ttty.ty_name = p;\n\tp = skip(p);\n\ttty.ty_getty = p;\n\tp = skip(p);\n\ttty.ty_type = p;\n\tp = skip(p);\n\ttty.ty_status = 0;\n\ttty.ty_window = NULL;\n\tfor (; *p; p = skip(p)) {\n#define space(x) ((c = p[x]) == ' ' || c == '\\t' || c == '\\n')\n\t\tif (strncmp(p, \"on\", 2) == 0 && space(2))\n\t\t\ttty.ty_status |= TTY_ON;\n\t\telse if (strncmp(p, \"off\", 3) == 0 && space(3))\n\t\t\ttty.ty_status &= ~TTY_ON;\n\t\telse if (strncmp(p, \"secure\", 6) == 0 && space(6))\n\t\t\ttty.ty_status |= TTY_SECURE;\n\t\telse if (strncmp(p, \"window=\", 7) == 0)\n\t\t\ttty.ty_window = value(p);\n\t\telse\n\t\t\tbreak;\n\t}\n\tif (zapchar == '#' || *p == '#')\n\t\twhile ((c = *++p) == ' ' || c == '\\t')\n\t\t\t;\n\ttty.ty_comment = p;\n\tif (*p == 0)\n\t\ttty.ty_comment = 0;\n        p = index(p, '\\n');\n\tif (p)\n\t\t*p = '\\0';\n\treturn(&tty);\n}\n"
  },
  {
    "path": "lib/libc/gen/getttynam.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <ttyent.h>\n#include <string.h>\n\nstruct ttyent *\ngetttynam(tty)\n\tconst char *tty;\n{\n\tregister struct ttyent *t;\n\n\tsetttyent();\n\twhile ((t = getttyent())) {\n\t\tif (strcmp(tty, t->ty_name) == 0)\n\t\t\tbreak;\n\t}\n\tendttyent();\n\treturn (t);\n}\n"
  },
  {
    "path": "lib/libc/gen/getusershell.c",
    "content": "/*\n * Copyright (c) 1985 Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that the above copyright notice and this paragraph are\n * duplicated in all such forms and that any documentation,\n * advertising materials, and other materials related to such\n * distribution and use acknowledge that the software was developed\n * by the University of California, Berkeley.  The name of the\n * University may not be used to endorse or promote products derived\n * from this software without specific prior written permission.\n * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n */\n#include <sys/param.h>\n#include <sys/file.h>\n#include <sys/stat.h>\n#include <ctype.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n\n#define SHELLS \"/etc/shells\"\n\n/*\n * Do not add local shells here.  They should be added in /etc/shells\n */\nstatic char *okshells[] =\n    { \"/bin/sh\", \"/bin/csh\", 0 };\n\nstatic char **shells, *strings;\nstatic char **curshell = NULL;\n\nstatic char **\ninitshells()\n{\n\tregister char **sp, *cp;\n\tregister FILE *fp;\n\tstruct stat statb;\n\n\tif (shells != NULL)\n\t\tfree((char *)shells);\n\tshells = NULL;\n\tif (strings != NULL)\n\t\tfree(strings);\n\tstrings = NULL;\n\tif ((fp = fopen(SHELLS, \"r\")) == (FILE *)0)\n\t\treturn(okshells);\n\tif (fstat(fileno(fp), &statb) == -1) {\n\t\t(void)fclose(fp);\n\t\treturn(okshells);\n\t}\n\tif ((strings = malloc((unsigned)statb.st_size)) == NULL) {\n\t\t(void)fclose(fp);\n\t\treturn(okshells);\n\t}\n\tshells = (char **)calloc((unsigned)statb.st_size / 3, sizeof (char *));\n\tif (shells == NULL) {\n\t\t(void)fclose(fp);\n\t\tfree(strings);\n\t\tstrings = NULL;\n\t\treturn(okshells);\n\t}\n\tsp = shells;\n\tcp = strings;\n\twhile (fgets(cp, MAXPATHLEN + 1, fp) != NULL) {\n\t\twhile (*cp != '#' && *cp != '/' && *cp != '\\0')\n\t\t\tcp++;\n\t\tif (*cp == '#' || *cp == '\\0')\n\t\t\tcontinue;\n\t\t*sp++ = cp;\n\t\twhile (!isspace(*cp) && *cp != '#' && *cp != '\\0')\n\t\t\tcp++;\n\t\t*cp++ = '\\0';\n\t}\n\t*sp = (char *)0;\n\t(void)fclose(fp);\n\treturn (shells);\n}\n\n/*\n * Get a list of shells from SHELLS, if it exists.\n */\nchar *\ngetusershell()\n{\n\tchar *ret;\n\n\tif (curshell == NULL)\n\t\tcurshell = initshells();\n\tret = *curshell;\n\tif (ret != NULL)\n\t\tcurshell++;\n\treturn (ret);\n}\n\nvoid\nendusershell()\n{\n\tif (shells != NULL)\n\t\tfree((char *)shells);\n\tshells = NULL;\n\tif (strings != NULL)\n\t\tfree(strings);\n\tstrings = NULL;\n\tcurshell = NULL;\n}\n\nvoid\nsetusershell()\n{\n\tcurshell = initshells();\n}\n"
  },
  {
    "path": "lib/libc/gen/getwd.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * getwd() returns the pathname of the current working directory. On error\n * an error message is copied to pathname and null pointer is returned.\n */\n#include <sys/param.h>\n#include <sys/stat.h>\n#include <sys/dir.h>\n#include <string.h>\n#include <unistd.h>\n\n#define GETWDERR(s)\tstrcpy(pathname, (s));\n\nstatic int pathsize;\t\t\t/* pathname length */\n\n/*\n * prepend() tacks a directory name onto the front of a pathname.\n */\nstatic char *\nprepend(dirname, pathname)\n\tregister char *dirname;\n\tregister char *pathname;\n{\n\tregister int i;\t\t\t/* directory name size counter */\n\n\tfor (i = 0; *dirname != '\\0'; i++, dirname++)\n\t\tcontinue;\n\tif ((pathsize += i) < MAXPATHLEN)\n\t\twhile (i-- > 0)\n\t\t\t*--pathname = *--dirname;\n\treturn (pathname);\n}\n\nchar *\ngetwd(pathname)\n\tchar *pathname;\n{\n\tchar pathbuf[MAXPATHLEN];\t\t/* temporary pathname buffer */\n\tchar *pnptr = &pathbuf[(sizeof pathbuf)-1]; /* pathname pointer */\n\tchar curdir[MAXPATHLEN];\t/* current directory buffer */\n\tchar *dptr = curdir;\t\t/* directory pointer */\n\tdev_t cdev, rdev;\t\t/* current & root device number */\n\tino_t cino, rino;\t\t/* current & root inode number */\n\tDIR *dirp;\t\t\t/* directory stream */\n\tstruct direct *dir;\t\t/* directory entry struct */\n\tstruct stat d, dd;\t\t/* file status struct */\n\n\tpathsize = 0;\n\t*pnptr = '\\0';\n\tif (stat(\"/\", &d) < 0) {\n\t\tGETWDERR(\"getwd: can't stat /\");\n\t\treturn (NULL);\n\t}\n\trdev = d.st_dev;\n\trino = d.st_ino;\n\tstrcpy(dptr, \"./\");\n\tdptr += 2;\n\tif (stat(curdir, &d) < 0) {\n\t\tGETWDERR(\"getwd: can't stat .\");\n\t\treturn (NULL);\n\t}\n\tfor (;;) {\n\t\tif (d.st_ino == rino && d.st_dev == rdev)\n\t\t\tbreak;\t\t/* reached root directory */\n\t\tcino = d.st_ino;\n\t\tcdev = d.st_dev;\n\t\tstrcpy(dptr, \"../\");\n\t\tdptr += 3;\n\t\tif ((dirp = opendir(curdir)) == NULL) {\n\t\t\tGETWDERR(\"getwd: can't open ..\");\n\t\t\treturn (NULL);\n\t\t}\n\t\tfstat(dirp->dd_fd, &d);\n\t\tif (cdev == d.st_dev) {\n\t\t\tif (cino == d.st_ino) {\n\t\t\t\t/* reached root directory */\n\t\t\t\tclosedir(dirp);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tdo {\n\t\t\t\tif ((dir = readdir(dirp)) == NULL) {\n\t\t\t\t\tclosedir(dirp);\n\t\t\t\t\tGETWDERR(\"getwd: read error in ..\");\n\t\t\t\t\treturn (NULL);\n\t\t\t\t}\n\t\t\t} while (dir->d_ino != cino);\n\t\t} else\n\t\t\tdo {\n\t\t\t\tif ((dir = readdir(dirp)) == NULL) {\n\t\t\t\t\tclosedir(dirp);\n\t\t\t\t\tGETWDERR(\"getwd: read error in ..\");\n\t\t\t\t\treturn (NULL);\n\t\t\t\t}\n\t\t\t\tstrcpy(dptr, dir->d_name);\n\t\t\t\tlstat(curdir, &dd);\n\t\t\t} while(dd.st_ino != cino || dd.st_dev != cdev);\n\t\tclosedir(dirp);\n\t\tpnptr = prepend(\"/\", prepend(dir->d_name, pnptr));\n\t}\n\tif (*pnptr == '\\0')\t\t/* current dir == root dir */\n\t\tstrcpy(pathname, \"/\");\n\telse\n\t\tstrcpy(pathname, pnptr);\n\treturn (pathname);\n}\n"
  },
  {
    "path": "lib/libc/gen/index.c",
    "content": "/*\n * Return the ptr in sp at which the character c appears;\n * NULL if not found\n */\n\n#define\tNULL\t0\n\nchar *\nindex(sp, c)\n\tregister const char *sp;\n\tregister int c;\n{\n\tdo {\n\t\tif (*sp == c)\n\t\t\treturn((char *)sp);\n\t} while (*sp++);\n\treturn(NULL);\n}\n"
  },
  {
    "path": "lib/libc/gen/initgroups.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * initgroups\n */\n#include <stdio.h>\n#include <sys/param.h>\n#include <grp.h>\n#include <string.h>\n\nint\ninitgroups(uname, agroup)\n\tchar *uname;\n\tint agroup;\n{\n\tgid_t groups[NGROUPS];\n\tregister struct group *grp;\n\tregister int i, ngroups = 0;\n\n\tif (agroup >= 0)\n\t\tgroups[ngroups++] = agroup;\n\tsetgrent();\n\twhile ((grp = getgrent())) {\n\t\tif (grp->gr_gid == agroup)\n\t\t\tcontinue;\n\t\tfor (i = 0; grp->gr_mem[i]; i++)\n\t\t\tif (!strcmp(grp->gr_mem[i], uname)) {\n\t\t\t\tif (ngroups == NGROUPS) {\nfprintf(stderr, \"initgroups: %s is in too many groups\\n\", uname);\n\t\t\t\t\tgoto toomany;\n\t\t\t\t}\n\t\t\t\tgroups[ngroups++] = grp->gr_gid;\n\t\t\t}\n\t}\ntoomany:\n\tendgrent();\n\tif (setgroups(ngroups, groups) < 0) {\n\t\tperror(\"setgroups\");\n\t\treturn (-1);\n\t}\n\treturn (0);\n}\n"
  },
  {
    "path": "lib/libc/gen/insque.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * insque -- vax insque instruction\n *\n * NOTE: this implementation is non-atomic!!\n */\n\nstruct vaxque {\t\t/* queue format expected by VAX queue instructions */\n\tstruct vaxque\t*vq_next;\n\tstruct vaxque\t*vq_prev;\n};\n\ninsque(e, prev)\n\tregister struct vaxque *e, *prev;\n{\n\te->vq_prev = prev;\n\te->vq_next = prev->vq_next;\n\tprev->vq_next->vq_prev = e;\n\tprev->vq_next = e;\n}\n"
  },
  {
    "path": "lib/libc/gen/isatty.c",
    "content": "/*\n * Returns 1 iff file is a tty\n */\n#include <sgtty.h>\n\nint\nisatty(f)\n        int f;\n{\n\tstruct sgttyb ttyb;\n\n\tif (ioctl(f, TIOCGETP, &ttyb) < 0)\n\t\treturn(0);\n\treturn(1);\n}\n"
  },
  {
    "path": "lib/libc/gen/isinf.c",
    "content": "/*\n * Written by J.T. Conklin <jtc@netbsd.org>.\n * Changed to return -1 for -Inf by Ulrich Drepper <drepper@cygnus.com>.\n * Public domain.\n */\n#include <math.h>\n\n/*\n * isinf(x) returns 1 is x is inf, -1 if x is -inf, else 0;\n * no branching!\n */\nint isinf (double x)\n{\n\tlong hx, lx;\n\n        lx = *(unsigned long long*) &x;\n        hx = (*(unsigned long long*) &x) >> 32;\n\n\tlx |= (hx & 0x7fffffff) ^ 0x7ff00000;\n\tlx |= -lx;\n\treturn ~(lx >> 31) & (hx >> 30);\n}\n"
  },
  {
    "path": "lib/libc/gen/isinff.c",
    "content": "/*\n * Written by Serge Vakulenko <serge@vak.ru>.\n *\n * Permission to use, copy, modify, and distribute this\n * software is freely granted, provided that this notice\n * is preserved.\n */\n#include <math.h>\n\n/*\n * isinff(x) returns 1 is x is inf, -1 if x is -inf, else 0;\n * no branching!\n */\nint isinff (float x)\n{\n        union {\n                long s32;\n                float f32;\n        } u;\n        long v;\n\n        u.f32 = x;\n\tv = (u.s32 & 0x7fffffff) ^ 0x7f800000;\n\treturn ~((v | -v) >> 31) & (u.s32 >> 30);\n}\n\n/*\n * For PIC32, double is the same as float.\n */\nint isinf (double x) __attribute__((alias (\"isinff\")));\n"
  },
  {
    "path": "lib/libc/gen/isnan.c",
    "content": "/*\n * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.\n *\n * Developed at SunPro, a Sun Microsystems, Inc. business.\n * Permission to use, copy, modify, and distribute this\n * software is freely granted, provided that this notice\n * is preserved.\n */\n#include <math.h>\n\n/*\n * isnan(x) returns 1 is x is nan, else 0;\n * no branching!\n */\nint isnan (double x)\n{\n\tlong hx, lx;\n\n        lx = *(unsigned long long*) &x;\n        hx = (*(unsigned long long*) &x) >> 32;\n\n\thx &= 0x7fffffff;\n\thx |= (unsigned long) (lx | (-lx)) >> 31;\n\thx = 0x7ff00000 - hx;\n\treturn (int) (((unsigned long) hx) >> 31);\n}\n"
  },
  {
    "path": "lib/libc/gen/isnanf.c",
    "content": "/*\n * Written by Serge Vakulenko <serge@vak.ru>.\n *\n * Permission to use, copy, modify, and distribute this\n * software is freely granted, provided that this notice\n * is preserved.\n */\n#include <math.h>\n\n/*\n * isnan(x) returns 1 is x is nan, else 0;\n * no branching!\n */\nint isnanf (float x)\n{\n        union {\n                long s32;\n                float f32;\n        } u;\n        unsigned long ul;\n\n        u.f32 = x;\n\tul = 0x7f800000 - (u.s32 & 0x7fffffff);\n\treturn ul >> 31;\n}\n\n/*\n * For PIC32, double is the same as float.\n */\nint isnan (double x) __attribute__((alias (\"isnanf\")));\n"
  },
  {
    "path": "lib/libc/gen/knlist.c",
    "content": "#include <stdio.h>\n#include <string.h>\n#include <nlist.h>\n#include <sys/sysctl.h>\n#include <machine/cpu.h>\n\nint\nknlist(list)\n\tstruct nlist *list;\n{\n\tregister struct nlist *p;\n\tint  mib[2], entries = 0;\n\tsize_t size;\n\n\tmib[0] = CTL_MACHDEP;\n\tmib[1] = CPU_NLIST;\n\n\t/*\n\t * Clean out any left-over information for all valid entries.\n\t * Type and value defined to be 0 if not found; historical\n\t * versions cleared other and desc as well.\n\t */\n\tfor (p=list; p->n_name && p->n_name[0]; ++p) {\n                size = sizeof(p->n_value);\n                if (sysctl(mib, 2, &p->n_value, &size,\n                    p->n_name, 1 + strlen(p->n_name)) < 0) {\n                        p->n_value = 0;\n                        continue;\n                }\n                ++entries;\n\t}\n\treturn entries;\n}\n"
  },
  {
    "path": "lib/libc/gen/ldexp.c",
    "content": "#include <float.h>\n#include <math.h>\n\ndouble\nldexp(fr, exp)\n        double fr;\n        int exp;\n{\n\tint neg;\n\tint i;\n\n\tif (fr == 0)\n\t\treturn 0;\n\tneg = 0;\n\tif (fr < 0) {\n\t\tfr = -fr;\n\t\tneg = 1;\n\t}\n\tfr = frexp(fr, &i);\n\twhile (fr < 0.5) {\n\t\tfr = 2*fr;\n\t\ti = i-1;\n\t}\n\texp = exp+i;\n\tif (exp >= DBL_MAX_EXP) {\n\t\tif (neg)\n\t\t\treturn(-HUGE_VAL);\n\t\telse\n\t\t\treturn(HUGE_VAL);\n        }\n\tif (exp < DBL_MIN_EXP - 2)\n\t\treturn(0);\n\twhile (exp > 30) {\n\t\tfr = fr*(1L<<30);\n\t\texp = exp-30;\n\t}\n\twhile (exp < -30) {\n\t\tfr = fr/(1L<<30);\n\t\texp = exp+30;\n\t}\n\tif (exp > 0)\n\t\tfr = fr*(1L<<exp);\n\tif (exp < 0)\n\t\tfr = fr/(1L<<-exp);\n\tif (neg)\n            fr = -fr;\n\treturn(fr);\n}\n"
  },
  {
    "path": "lib/libc/gen/malloc.c",
    "content": "#include <stdlib.h>\n#include <unistd.h>\n\n#ifdef debug\n#include <sys/types.h>\n#include <sys/uio.h>\n\n#define ASSERT(p) if(!(p))botch(\"p\")\n\n/*\n * Can't use 'printf' below because that can call malloc().  If the malloc\n * arena is corrupt malloc() calls botch() which calls printf which calls malloc\n * ... result is a recursive loop which underflows the stack.\n*/\n\nstatic botch(s)\nchar *s;\n{\n\tstruct\tiovec\tiov[3];\n\tregister struct iovec *v = iov;\n\tchar\t*ab = \"assertion botched: \";\n\n\tv->iov_base = ab;\n\tv->iov_len = strlen(ab);\n\tv++;\n\tv->iov_base = s;\n\tv->iov_len = strlen(s);\n\tv++;\n\tv->iov_base = \"\\n\";\n\tv->iov_len = 1;\n\n\twritev(STDOUT_FILENO, iov, 3);\n\tabort();\n}\n#else\n#define ASSERT(p)\n#endif\t/* debug */\n\n/*\n * The origins of the following ifdef are lost.  The only comment attached\n * to it, \"avoid break bug\", probably has something to do with a bug in\n * an older PDP-11 kernel.  Maybe it's still a bug in the current kernel.\n * We'll probably never know ...\n */\n#ifdef pdp11\n#\tdefine GRANULE 64\n#else\n#\tdefine GRANULE 0\n#endif\n\n/*\n * C storage allocator\n *\n * Uses circular first-fit strategy.  Works with a noncontiguous, but\n * monotonically linked, arena.  Each block is preceded by a ptr to the\n * pointer of the next following block.  Blocks are exact number of words\n * long aligned to the data type requirements of ALIGN.\n *\n * Bit 0 (LSB) of pointers is used to indicate whether the block associated\n * with the pointer is in use.  A 1 indicates a busy block and a 0 a free\n * block (obviously pointers can't point at odd addresses).  Gaps in arena\n * are merely noted as busy blocks.  The last block of the arena (pointed\n * to by alloct) is empty and has a pointer to first.  Idle blocks are\n * coalesced during space search\n *\n * Different implementations may need to redefine ALIGN, NALIGN, BLOCK,\n * BUSY, INT where INT is integer type to which a pointer can be cast.\n */\n#define\tINT\t\tint\n#define\tALIGN\t\tint\n#define\tNALIGN\t\t1\n#define\tWORD\t\tsizeof(union store)\n#define\tBLOCK\t\t1024\t/* a multiple of WORD */\n\n#define\tBUSY\t\t1\n\n#define\ttestbusy(p)\t((INT)(p)&BUSY)\n#define\tsetbusy(p)\t(union store *)((INT)(p)|BUSY)\n#define\tclearbusy(p)\t(union store *)((INT)(p)&~BUSY)\n\nunion store {\n\tunion store\t*ptr;\n\tALIGN\t\tdummy[NALIGN];\n\tint\t\tcalloc;\t/* calloc clears an array of integers */\n};\n\nstatic union store\tallocs[2];\t/* initial arena */\nstatic union store\t*allocp;\t/* search ptr */\nstatic union store\t*alloct;\t/* arena top */\nstatic union store\t*allocx;\t/* for benefit of realloc */\n\nvoid *\nmalloc(nbytes)\n\tsize_t nbytes;\n{\n\tregister union store *p, *q;\n\tregister int nw;\n\tstatic int temp;\t/* coroutines assume no auto */\n\n\tif (nbytes == 0)\n\t\treturn(NULL);\n\tif (allocs[0].ptr == 0) {\t/* first time */\n\t\tallocs[0].ptr = setbusy(&allocs[1]);\n\t\tallocs[1].ptr = setbusy(&allocs[0]);\n\t\talloct = &allocs[1];\n\t\tallocp = &allocs[0];\n\t}\n\tnw = (nbytes+WORD+WORD-1)/WORD;\n\tASSERT(allocp >= allocs && allocp <= alloct);\n\tASSERT(allock());\n\tfor (p = allocp; ; ) {\n\t\tfor (temp = 0; ; ) {\n\t\t\tif (!testbusy(p->ptr)) {\n\t\t\t\twhile(!testbusy((q = p->ptr)->ptr)) {\n\t\t\t\t\tASSERT(q > p && q < alloct);\n\t\t\t\t\tp->ptr = q->ptr;\n\t\t\t\t}\n\t\t\t\tif (q >= p+nw && p+nw >= p)\n\t\t\t\t\tgoto found;\n\t\t\t}\n\t\t\tq = p;\n\t\t\tp = clearbusy(p->ptr);\n\t\t\tif (p > q)\n\t\t\t\tASSERT(p <= alloct);\n\t\t\telse if (q != alloct || p != allocs) {\n\t\t\t\tASSERT(q == alloct && p == allocs);\n\t\t\t\treturn(NULL);\n\t\t\t} else if (++temp > 1)\n\t\t\t\tbreak;\n\t\t}\n\t\tq = (union store *)sbrk(0);\n\t\t/*\n\t\t * Line up on page boundry so we can get the last drip at\n\t\t * the end ...\n\t\t */\n\t\ttemp = ((((unsigned)q + WORD*nw + BLOCK-1)/BLOCK)*BLOCK\n\t\t\t- (unsigned)q) / WORD;\n\t\tif (q+temp+GRANULE < q)\n\t\t\treturn(NULL);\n\t\tq = (union store *)sbrk(temp*WORD);\n\t\tif ((INT)q == -1)\n\t\t\treturn(NULL);\n\t\tASSERT(q > alloct);\n\t\talloct->ptr = q;\n\t\tif (q != alloct+1)\n\t\t\talloct->ptr = setbusy(alloct->ptr);\n\t\talloct = q->ptr = q+temp-1;\n\t\talloct->ptr = setbusy(allocs);\n\t}\nfound:\n\tallocp = p + nw;\n\tASSERT(allocp <= alloct);\n\tif (q > allocp) {\n\t\tallocx = allocp->ptr;\n\t\tallocp->ptr = p->ptr;\n\t}\n\tp->ptr = setbusy(allocp);\n\treturn((char *)(p+1));\n}\n\n/*\n * Freeing strategy tuned for LIFO allocation.\n */\nvoid free(ap)\n\tregister void *ap;\n{\n\tregister union store *p = (union store *)ap;\n\n\tif (p == NULL)\n\t        return;\n\tASSERT(p > clearbusy(allocs[1].ptr) && p <= alloct);\n\tASSERT(allock());\n\tallocp = --p;\n\tASSERT(testbusy(p->ptr));\n\tp->ptr = clearbusy(p->ptr);\n\tASSERT(p->ptr > allocp && p->ptr <= alloct);\n}\n\n/*\n * Realloc(p, nbytes) reallocates a block obtained from malloc() and freed\n * since last call of malloc() to have new size nbytes, and old content\n * returns new location, or 0 on failure.\n */\nvoid *\nrealloc(vp, nbytes)\n\tregister void *vp;\n\tsize_t nbytes;\n{\n\tregister union store *p = vp;\n\tregister union store *q;\n\tunion store *s, *t;\n\tregister unsigned nw;\n\tunsigned onw;\n\n\tif (p == NULL)\n\t        return malloc(nbytes);\n\tif (testbusy(p[-1].ptr))\n\t\tfree((char *)p);\n\tonw = p[-1].ptr - p;\n\tq = (union store *)malloc(nbytes);\n\tif (q == NULL || q == p)\n\t\treturn((char *)q);\n\ts = p;\n\tt = q;\n\tnw = (nbytes+WORD-1)/WORD;\n\tif (nw < onw)\n\t\tonw = nw;\n\twhile (onw-- != 0)\n\t\t*t++ = *s++;\n\tif (q < p && q+nw >= p)\n\t\t(q+(q+nw-p))->ptr = allocx;\n\treturn((char *)q);\n}\n\n#ifdef\tdebug\nstatic allock()\n{\n#ifdef longdebug\n\tregister union store *p;\n\tint x;\n\tx = 0;\n\tfor (p= &allocs[0]; clearbusy(p->ptr) > p; p=clearbusy(p->ptr)) {\n\t\tif (p == allocp)\n\t\t\tx++;\n\t}\n\tASSERT(p == alloct);\n\treturn((x == 1) | (p == allocp));\n#else\n\treturn(1);\n#endif\n}\n#endif /* debug */\n"
  },
  {
    "path": "lib/libc/gen/mktemp.c",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/types.h>\n#include <sys/file.h>\n#include <sys/stat.h>\n#include <errno.h>\n#include <stdio.h>\n#include <ctype.h>\n#include <unistd.h>\n#include <fcntl.h>\n\n#define\tYES\t1\n#define\tNO\t0\n\nstatic int\n_gettemp(as, doopen)\n\tchar\t*as;\n\tregister int\t*doopen;\n{\n\textern int\terrno;\n\tregister char\t*start, *trv;\n\tstruct stat\tsbuf;\n\tu_int\tpid;\n\n\tpid = getpid();\n\n\t/* extra X's get set to 0's */\n\tfor (trv = as; *trv; ++trv);\n\twhile (*--trv == 'X') {\n\t\t*trv = (pid % 10) + '0';\n\t\tpid /= 10;\n\t}\n\n\t/*\n\t * check for write permission on target directory; if you have\n\t * six X's and you can't write the directory, this will run for\n\t * a *very* long time.\n\t */\n\tfor (start = ++trv; trv > as && *trv != '/'; --trv);\n\tif (*trv == '/') {\n\t\t*trv = '\\0';\n\t\tif (stat(as, &sbuf) || !(sbuf.st_mode & S_IFDIR))\n\t\t\treturn(NO);\n\t\t*trv = '/';\n\t}\n\telse if (stat(\".\", &sbuf) == -1)\n\t\treturn(NO);\n\n\tfor (;;) {\n\t\tif (doopen) {\n\t\t    if ((*doopen = open(as, O_CREAT|O_EXCL|O_RDWR, 0600)) >= 0)\n\t\t\treturn(YES);\n\t\t    if (errno != EEXIST)\n\t\t\treturn(NO);\n\t\t}\n\t\telse if (stat(as, &sbuf))\n\t\t\treturn(errno == ENOENT ? YES : NO);\n\n\t\t/* tricky little algorithm for backward compatibility */\n\t\tfor (trv = start;;) {\n\t\t\tif (!*trv)\n\t\t\t\treturn(NO);\n\t\t\tif (*trv == 'z')\n\t\t\t\t*trv++ = 'a';\n\t\t\telse {\n\t\t\t\tif (isdigit(*trv))\n\t\t\t\t\t*trv = 'a';\n\t\t\t\telse\n\t\t\t\t\t++*trv;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\t/*NOTREACHED*/\n}\n\nint\nmkstemp(as)\n\tchar\t*as;\n{\n\tint\tfd;\n\n\treturn (_gettemp(as, &fd) ? fd : -1);\n}\n\nchar *\nmktemp(as)\n\tchar\t*as;\n{\n\treturn(_gettemp(as, (int *)NULL) ? as : (char *)NULL);\n}\n"
  },
  {
    "path": "lib/libc/gen/modf.c",
    "content": "/*\n * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.\n *\n * Developed at SunPro, a Sun Microsystems, Inc. business.\n * Permission to use, copy, modify, and distribute this\n * software is freely granted, provided that this notice\n * is preserved.\n */\n#include <math.h>\n\n/* Get two 32 bit ints from a double.  */\n\n#define EXTRACT_WORDS(high,low,d) \\\n        high = *(unsigned long long*) &d; \\\n        low  = (*(unsigned long long*) &d) >> 32\n\n\n/* Set a double from two 32 bit ints.  */\n\n#define INSERT_WORDS(d,high,low) \\\n        *(unsigned long long*) &(x) = (unsigned long long) (high) << 32 | (low)\n\n/*\n * modf(double x, double *iptr)\n * return fraction part of x, and return x's integral part in *iptr.\n * Method:\n *\tBit twiddling.\n *\n * Exception:\n *\tNo exception.\n */\nstatic const double one = 1.0;\n\ndouble modf (double x, double *iptr)\n{\n\tlong i0, i1, j0;\n\tunsigned long i;\n\n\tEXTRACT_WORDS (i0, i1, x);\n\tj0 = ((i0 >> 20) & 0x7ff) - 0x3ff;\t/* exponent of x */\n\tif (j0 < 20) {\t\t\t\t/* integer part in high x */\n\t\tif (j0 < 0) {\t\t\t/* |x|<1 */\n\t\t\tINSERT_WORDS (*iptr, i0 & 0x80000000, 0);\n\t\t\t/* *iptr = +-0 */\n\t\t\treturn x;\n\t\t} else {\n\t\t\ti = (0x000fffff) >> j0;\n\t\t\tif (((i0 & i) | i1) == 0) {\t/* x is integral */\n\t\t\t\t*iptr = x;\n\t\t\t\tINSERT_WORDS (x, i0 & 0x80000000, 0);\n\t\t\t\t/* return +-0 */\n\t\t\t\treturn x;\n\t\t\t} else {\n\t\t\t\tINSERT_WORDS (*iptr, i0 & (~i), 0);\n\t\t\t\treturn x - *iptr;\n\t\t\t}\n\t\t}\n\t} else if (j0 > 51) {\t\t\t/* no fraction part */\n\t\t*iptr = x * one;\n\t\t/* We must handle NaNs separately.  */\n\t\tif (j0 == 0x400 && ((i0 & 0xfffff) | i1))\n\t\t\treturn x * one;\n\n\t\tINSERT_WORDS (x, i0 & 0x80000000, 0);\n\t\t/* return +-0 */\n\t\treturn x;\n\t} else {\t\t\t\t/* fraction part in low x */\n\t\ti = ((unsigned long) (0xffffffff)) >> (j0 - 20);\n\t\tif ((i1 & i) == 0) {\t\t\t/* x is integral */\n\t\t\t*iptr = x;\n\t\t\tINSERT_WORDS (x, i0 & 0x80000000, 0);\n\t\t\t/* return +-0 */\n\t\t\treturn x;\n\t\t} else {\n\t\t\tINSERT_WORDS (*iptr, i0, i1 & (~i));\n\t\t\treturn x - *iptr;\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "lib/libc/gen/modff.c",
    "content": "/*\n * Written by Serge Vakulenko <serge@vak.ru>.\n *\n * Permission to use, copy, modify, and distribute this\n * software is freely granted, provided that this notice\n * is preserved.\n */\n#include <math.h>\n\n/*\n * modff(float x, float *iptr)\n * return fraction part of x, and return x's integral part in *iptr.\n */\nfloat modff (float fx, float *iptr)\n{\n        union {\n                unsigned u32;\n                float f32;\n        } x;\n        unsigned hx, s;\n\n        x.f32 = fx;\n        hx = x.u32 & ~0x80000000;\n        if (hx >= 0x4b000000) { /* x is NaN, infinite, or integral */\n                *iptr = x.f32;\n                if (hx <= 0x7f800000)\n                        x.u32 &= 0x80000000;\n                return x.f32;\n        }\n\n        if (hx < 0x3f800000) {  /* |x| < 1 */\n                float ret = x.f32;\n                x.u32 &= 0x80000000;\n                *iptr = x.f32;\n                return ret;\n        }\n\n        /* split x at the binary point */\n        s = x.u32 & 0x80000000;\n        fx = x.f32;\n        x.u32 &= ~((1 << (0x96 - (hx >> 23))) - 1);\n        *iptr = x.f32;\n        x.f32 = fx - *iptr;\n\n        /* restore sign in case difference is 0 */\n        x.u32 = (x.u32 & ~0x80000000) | s;\n        return x.f32;\n}\n\n/*\n * For PIC32, double is the same as float.\n */\ndouble modf (double x, double *iptr) __attribute__((alias (\"modff\")));\n"
  },
  {
    "path": "lib/libc/gen/ndbm.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <sys/file.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <strings.h>\n#include <unistd.h>\n#include <fcntl.h>\n#include <errno.h>\n#include <ndbm.h>\n\n#define BYTESIZ 8\n#undef setbit\n\nstatic  int hitab[16]\n/* ken's\n{\n\t055,043,036,054,063,014,004,005,\n\t010,064,077,000,035,027,025,071,\n};\n*/\n = {    61, 57, 53, 49, 45, 41, 37, 33,\n\t29, 25, 21, 17, 13,  9,  5,  1,\n};\nstatic  long hltab[64]\n = {\n\t06100151277L,06106161736L,06452611562L,05001724107L,\n\t02614772546L,04120731531L,04665262210L,07347467531L,\n\t06735253126L,06042345173L,03072226605L,01464164730L,\n\t03247435524L,07652510057L,01546775256L,05714532133L,\n\t06173260402L,07517101630L,02431460343L,01743245566L,\n\t00261675137L,02433103631L,03421772437L,04447707466L,\n\t04435620103L,03757017115L,03641531772L,06767633246L,\n\t02673230344L,00260612216L,04133454451L,00615531516L,\n\t06137717526L,02574116560L,02304023373L,07061702261L,\n\t05153031405L,05322056705L,07401116734L,06552375715L,\n\t06165233473L,05311063631L,01212221723L,01052267235L,\n\t06000615237L,01075222665L,06330216006L,04402355630L,\n\t01451177262L,02000133436L,06025467062L,07121076461L,\n\t03123433522L,01010635225L,01716177066L,05161746527L,\n\t01736635071L,06243505026L,03637211610L,01756474365L,\n\t04723077174L,03642763134L,05750130273L,03655541561L,\n};\n\nstatic long\ndcalchash(item)\n\tdatum item;\n{\n\tregister int s, c, j;\n\tregister char *cp;\n\tregister long hashl;\n\tregister int hashi;\n\n\thashl = 0;\n\thashi = 0;\n\tfor (cp = item.dptr, s=item.dsize; --s >= 0; ) {\n\t\tc = *cp++;\n\t\tfor (j=0; j<BYTESIZ; j+=4) {\n\t\t\thashi += hitab[c&017];\n\t\t\thashl += hltab[hashi&63];\n\t\t\tc >>= 4;\n\t\t}\n\t}\n\treturn (hashl);\n}\n\nstatic datum\nmakdatum(buf, n)\n\tchar buf[PBLKSIZ];\n\tint n;\n{\n\tregister short *sp;\n\tregister int t;\n\tdatum item;\n\n\tsp = (short *)buf;\n\tif ((unsigned)n >= sp[0]) {\n\t\titem.dptr = NULL;\n\t\titem.dsize = 0;\n\t\treturn (item);\n\t}\n\tt = PBLKSIZ;\n\tif (n > 0)\n\t\tt = sp[n];\n\titem.dptr = buf+sp[n+1];\n\titem.dsize = t - sp[n+1];\n\treturn (item);\n}\n\nDBM *\ndbm_open(file, flags, mode)\n\tchar *file;\n\tint flags, mode;\n{\n\tstruct stat statb;\n\tregister DBM *db;\n\n\tif ((db = (DBM *)malloc(sizeof *db)) == 0) {\n\t\terrno = ENOMEM;\n\t\treturn ((DBM *)0);\n\t}\n\tdb->dbm_flags = (flags & 03) == O_RDONLY ? _DBM_RDONLY : 0;\n\tif ((flags & 03) == O_WRONLY)\n\t\tflags = (flags & ~03) | O_RDWR;\n\tstrcpy(db->dbm_pagbuf, file);\n\tstrcat(db->dbm_pagbuf, \".pag\");\n\tdb->dbm_pagf = open(db->dbm_pagbuf, flags, mode);\n\tif (db->dbm_pagf < 0)\n\t\tgoto bad;\n\tstrcpy(db->dbm_pagbuf, file);\n\tstrcat(db->dbm_pagbuf, \".dir\");\n\tdb->dbm_dirf = open(db->dbm_pagbuf, flags, mode);\n\tif (db->dbm_dirf < 0)\n\t\tgoto bad1;\n\tfstat(db->dbm_dirf, &statb);\n\tdb->dbm_maxbno = statb.st_size*BYTESIZ-1;\n\tdb->dbm_pagbno = db->dbm_dirbno = -1;\n\treturn (db);\nbad1:\n\t(void) close(db->dbm_pagf);\nbad:\n\tfree((char *)db);\n\treturn ((DBM *)0);\n}\n\nvoid\ndbm_close(db)\n\tDBM *db;\n{\n\n\t(void) close(db->dbm_dirf);\n\t(void) close(db->dbm_pagf);\n\tfree((char *)db);\n}\n\nstatic int\ngetbit(db)\n\tregister DBM *db;\n{\n\tlong bn, b;\n\tregister int i, n;\n\n\tif (db->dbm_bitno > db->dbm_maxbno)\n\t\treturn (0);\n\tn = db->dbm_bitno % BYTESIZ;\n\tbn = db->dbm_bitno / BYTESIZ;\n\ti = bn % DBLKSIZ;\n\tb = bn / DBLKSIZ;\n\tif (b != db->dbm_dirbno) {\n\t\tdb->dbm_dirbno = b;\n\t\t(void) lseek(db->dbm_dirf, b*DBLKSIZ, L_SET);\n\t\tif (read(db->dbm_dirf, db->dbm_dirbuf, DBLKSIZ) != DBLKSIZ)\n\t\t\tbzero(db->dbm_dirbuf, DBLKSIZ);\n\t}\n\treturn (db->dbm_dirbuf[i] & (1<<n));\n}\n\nlong\ndbm_forder(db, key)\n\tregister DBM *db;\n\tdatum key;\n{\n\tlong hash;\n\n\thash = dcalchash(key);\n\tfor (db->dbm_hmask=0;; db->dbm_hmask=(db->dbm_hmask<<1)+1) {\n\t\tdb->dbm_blkno = hash & db->dbm_hmask;\n\t\tdb->dbm_bitno = db->dbm_blkno + db->dbm_hmask;\n\t\tif (getbit(db) == 0)\n\t\t\tbreak;\n\t}\n\treturn (db->dbm_blkno);\n}\n\nstatic void\ndbm_access(db, hash)\n\tregister DBM *db;\n\tlong hash;\n{\n\n\tfor (db->dbm_hmask=0;; db->dbm_hmask=(db->dbm_hmask<<1)+1) {\n\t\tdb->dbm_blkno = hash & db->dbm_hmask;\n\t\tdb->dbm_bitno = db->dbm_blkno + db->dbm_hmask;\n\t\tif (getbit(db) == 0)\n\t\t\tbreak;\n\t}\n\tif (db->dbm_blkno != db->dbm_pagbno) {\n\t\tdb->dbm_pagbno = db->dbm_blkno;\n\t\t(void) lseek(db->dbm_pagf, db->dbm_blkno*PBLKSIZ, L_SET);\n\t\tif (read(db->dbm_pagf, db->dbm_pagbuf, PBLKSIZ) != PBLKSIZ)\n\t\t\tbzero(db->dbm_pagbuf, PBLKSIZ);\n#ifdef DEBUG\n\t\telse if (chkblk(db->dbm_pagbuf) < 0)\n\t\t\tdb->dbm_flags |= _DBM_IOERR;\n#endif\n\t}\n}\n\nstatic int\nfinddatum(buf, item)\n\tchar buf[PBLKSIZ];\n\tdatum item;\n{\n\tregister short *sp;\n\tregister int i, n, j;\n\n\tsp = (short *)buf;\n\tn = PBLKSIZ;\n\tfor (i=0, j=sp[0]; i<j; i+=2, n = sp[i]) {\n\t\tn -= sp[i+1];\n\t\tif (n != item.dsize)\n\t\t\tcontinue;\n\t\tif (n == 0 || bcmp(&buf[sp[i+1]], item.dptr, n) == 0)\n\t\t\treturn (i);\n\t}\n\treturn (-1);\n}\n\ndatum\ndbm_fetch(db, key)\n\tregister DBM *db;\n\tdatum key;\n{\n\tregister int i;\n\tdatum item;\n\n\tif (dbm_error(db))\n\t\tgoto err;\n\tdbm_access(db, dcalchash(key));\n\tif ((i = finddatum(db->dbm_pagbuf, key)) >= 0) {\n\t\titem = makdatum(db->dbm_pagbuf, i+1);\n\t\tif (item.dptr != NULL)\n\t\t\treturn (item);\n\t}\nerr:\n\titem.dptr = NULL;\n\titem.dsize = 0;\n\treturn (item);\n}\n\n/*\n * Delete pairs of items (n & n+1).\n */\nstatic int\ndelitem(buf, n)\n\tchar buf[PBLKSIZ];\n\tint n;\n{\n\tregister short *sp, *sp1;\n\tregister int i1, i2;\n\n\tsp = (short *)buf;\n\ti2 = sp[0];\n\tif ((unsigned)n >= i2 || (n & 1))\n\t\treturn (0);\n\tif (n == i2-2) {\n\t\tsp[0] -= 2;\n\t\treturn (1);\n\t}\n\ti1 = PBLKSIZ;\n\tif (n > 0)\n\t\ti1 = sp[n];\n\ti1 -= sp[n+2];\n\tif (i1 > 0) {\n\t\ti2 = sp[i2];\n\t\tbcopy(&buf[i2], &buf[i2 + i1], sp[n+2] - i2);\n\t}\n\tsp[0] -= 2;\n\tfor (sp1 = sp + sp[0], sp += n+1; sp <= sp1; sp++)\n\t\tsp[0] = sp[2] + i1;\n\treturn (1);\n}\n\nint\ndbm_delete(db, key)\n\tregister DBM *db;\n\tdatum key;\n{\n\tregister int i;\n\n\tif (dbm_error(db))\n\t\treturn (-1);\n\tif (dbm_rdonly(db)) {\n\t\terrno = EPERM;\n\t\treturn (-1);\n\t}\n\tdbm_access(db, dcalchash(key));\n\tif ((i = finddatum(db->dbm_pagbuf, key)) < 0)\n\t\treturn (-1);\n\tif (!delitem(db->dbm_pagbuf, i))\n\t\tgoto err;\n\tdb->dbm_pagbno = db->dbm_blkno;\n\t(void) lseek(db->dbm_pagf, db->dbm_blkno*PBLKSIZ, L_SET);\n\tif (write(db->dbm_pagf, db->dbm_pagbuf, PBLKSIZ) != PBLKSIZ) {\n\terr:\n\t\tdb->dbm_flags |= _DBM_IOERR;\n\t\treturn (-1);\n\t}\n\treturn (0);\n}\n\nstatic void\nsetbit(db)\n\tregister DBM *db;\n{\n\tlong bn, b;\n\tregister int i, n;\n\n\tif (db->dbm_bitno > db->dbm_maxbno)\n\t\tdb->dbm_maxbno = db->dbm_bitno;\n\tn = db->dbm_bitno % BYTESIZ;\n\tbn = db->dbm_bitno / BYTESIZ;\n\ti = bn % DBLKSIZ;\n\tb = bn / DBLKSIZ;\n\tif (b != db->dbm_dirbno) {\n\t\tdb->dbm_dirbno = b;\n\t\t(void) lseek(db->dbm_dirf, b*DBLKSIZ, L_SET);\n\t\tif (read(db->dbm_dirf, db->dbm_dirbuf, DBLKSIZ) != DBLKSIZ)\n\t\t\tbzero(db->dbm_dirbuf, DBLKSIZ);\n\t}\n\tdb->dbm_dirbuf[i] |= 1<<n;\n\tdb->dbm_dirbno = b;\n\t(void) lseek(db->dbm_dirf, (long)b*DBLKSIZ, L_SET);\n\tif (write(db->dbm_dirf, db->dbm_dirbuf, DBLKSIZ) != DBLKSIZ)\n\t\tdb->dbm_flags |= _DBM_IOERR;\n}\n\n/*\n * Add pairs of items (item & item1).\n */\nstatic int\nadditem(buf, item, item1)\n\tchar buf[PBLKSIZ];\n\tdatum item, item1;\n{\n\tregister short *sp;\n\tregister int i1, i2;\n\n\tsp = (short *)buf;\n\ti1 = PBLKSIZ;\n\ti2 = sp[0];\n\tif (i2 > 0)\n\t\ti1 = sp[i2];\n\ti1 -= item.dsize + item1.dsize;\n\tif (i1 <= (int)((i2+3) * sizeof(short)))\n\t\treturn (0);\n\tsp[0] += 2;\n\tsp[++i2] = i1 + item1.dsize;\n\tbcopy(item.dptr, &buf[i1 + item1.dsize], item.dsize);\n\tsp[++i2] = i1;\n\tbcopy(item1.dptr, &buf[i1], item1.dsize);\n\treturn (1);\n}\n\nint\ndbm_store(db, key, dat, replace)\n\tregister DBM *db;\n\tdatum key, dat;\n\tint replace;\n{\n\tregister int i;\n\tdatum item, item1;\n\tchar ovfbuf[PBLKSIZ];\n\n\tif (dbm_error(db))\n\t\treturn (-1);\n\tif (dbm_rdonly(db)) {\n\t\terrno = EPERM;\n\t\treturn (-1);\n\t}\nloop:\n\tdbm_access(db, dcalchash(key));\n\tif ((i = finddatum(db->dbm_pagbuf, key)) >= 0) {\n\t\tif (!replace)\n\t\t\treturn (1);\n\t\tif (!delitem(db->dbm_pagbuf, i)) {\n\t\t\tdb->dbm_flags |= _DBM_IOERR;\n\t\t\treturn (-1);\n\t\t}\n\t}\n\tif (!additem(db->dbm_pagbuf, key, dat))\n\t\tgoto split;\n\tdb->dbm_pagbno = db->dbm_blkno;\n\t(void) lseek(db->dbm_pagf, db->dbm_blkno*PBLKSIZ, L_SET);\n\tif (write(db->dbm_pagf, db->dbm_pagbuf, PBLKSIZ) != PBLKSIZ) {\n\t\tdb->dbm_flags |= _DBM_IOERR;\n\t\treturn (-1);\n\t}\n\treturn (0);\n\nsplit:\n\tif (key.dsize+dat.dsize+3*sizeof(short) >= PBLKSIZ) {\n\t\tdb->dbm_flags |= _DBM_IOERR;\n\t\terrno = ENOSPC;\n\t\treturn (-1);\n\t}\n\tbzero(ovfbuf, PBLKSIZ);\n\tfor (i=0;;) {\n\t\titem = makdatum(db->dbm_pagbuf, i);\n\t\tif (item.dptr == NULL)\n\t\t\tbreak;\n\t\tif (dcalchash(item) & (db->dbm_hmask+1)) {\n\t\t\titem1 = makdatum(db->dbm_pagbuf, i+1);\n\t\t\tif (item1.dptr == NULL) {\n\t\t\t\tfprintf(stderr, \"ndbm: split not paired\\n\");\n\t\t\t\tdb->dbm_flags |= _DBM_IOERR;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (!additem(ovfbuf, item, item1) ||\n\t\t\t    !delitem(db->dbm_pagbuf, i)) {\n\t\t\t\tdb->dbm_flags |= _DBM_IOERR;\n\t\t\t\treturn (-1);\n\t\t\t}\n\t\t\tcontinue;\n\t\t}\n\t\ti += 2;\n\t}\n\tdb->dbm_pagbno = db->dbm_blkno;\n\t(void) lseek(db->dbm_pagf, db->dbm_blkno*PBLKSIZ, L_SET);\n\tif (write(db->dbm_pagf, db->dbm_pagbuf, PBLKSIZ) != PBLKSIZ) {\n\t\tdb->dbm_flags |= _DBM_IOERR;\n\t\treturn (-1);\n\t}\n\t(void) lseek(db->dbm_pagf, (db->dbm_blkno+db->dbm_hmask+1)*PBLKSIZ, L_SET);\n\tif (write(db->dbm_pagf, ovfbuf, PBLKSIZ) != PBLKSIZ) {\n\t\tdb->dbm_flags |= _DBM_IOERR;\n\t\treturn (-1);\n\t}\n\tsetbit(db);\n\tgoto loop;\n}\n\ndatum\ndbm_firstkey(db)\n\tDBM *db;\n{\n\n\tdb->dbm_blkptr = 0L;\n\tdb->dbm_keyptr = 0;\n\treturn (dbm_nextkey(db));\n}\n\ndatum\ndbm_nextkey(db)\n\tregister DBM *db;\n{\n\tstruct stat statb;\n\tdatum item;\n\n\tif (dbm_error(db) || fstat(db->dbm_pagf, &statb) < 0)\n\t\tgoto err;\n\tstatb.st_size /= PBLKSIZ;\n\tfor (;;) {\n\t\tif (db->dbm_blkptr != db->dbm_pagbno) {\n\t\t\tdb->dbm_pagbno = db->dbm_blkptr;\n\t\t\t(void) lseek(db->dbm_pagf, db->dbm_blkptr*PBLKSIZ, L_SET);\n\t\t\tif (read(db->dbm_pagf, db->dbm_pagbuf, PBLKSIZ) != PBLKSIZ)\n\t\t\t\tbzero(db->dbm_pagbuf, PBLKSIZ);\n#ifdef DEBUG\n\t\t\telse if (chkblk(db->dbm_pagbuf) < 0)\n\t\t\t\tdb->dbm_flags |= _DBM_IOERR;\n#endif\n\t\t}\n\t\tif (db->dbm_pagbuf[0] != 0 && db->dbm_pagbuf[1] != 0) {\n\t\t\titem = makdatum(db->dbm_pagbuf, db->dbm_keyptr);\n\t\t\tif (item.dptr != NULL) {\n\t\t\t\tdb->dbm_keyptr += 2;\n\t\t\t\treturn (item);\n\t\t\t}\n\t\t\tdb->dbm_keyptr = 0;\n\t\t}\n\t\tif (++db->dbm_blkptr >= statb.st_size)\n\t\t\tbreak;\n\t}\nerr:\n\titem.dptr = NULL;\n\titem.dsize = 0;\n\treturn (item);\n}\n\n#ifdef DEBUG\nstatic\nchkblk(buf)\n\tchar buf[PBLKSIZ];\n{\n\tregister short *sp;\n\tregister t, i;\n\n\tsp = (short *)buf;\n\tt = PBLKSIZ;\n\tfor (i=0; i<sp[0]; i++) {\n\t\tif (sp[i+1] > t)\n\t\t\treturn (-1);\n\t\tt = sp[i+1];\n\t}\n\tif (t < (sp[0]+1)*sizeof(short))\n\t\treturn (-1);\n\treturn (0);\n}\n#endif\n"
  },
  {
    "path": "lib/libc/gen/nlist.c",
    "content": "/*\n * Copyright (c) 1989 The Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that: (1) source distributions retain this entire copyright\n * notice and comment, and (2) distributions including binaries display\n * the following acknowledgement:  ``This product includes software\n * developed by the University of California, Berkeley and its contributors''\n * in the documentation or other materials provided with the distribution\n * and in all advertising materials mentioning features or use of this\n * software. Neither the name of the University nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n */\n#include <sys/types.h>\n#include <sys/file.h>\n#include <a.out.h>\n#include <stdio.h>\n#include <string.h>\n\n#define\tISVALID(p)\t(p->n_name && p->n_name[0])\n\nint\nnlist(name, list)\n\tchar *name;\n\tstruct nlist *list;\n{\n\tregister struct nlist *p;\n\tstruct exec ebuf;\n\tregister FILE *fsym;\n\toff_t symbol_offset, symbol_size;\n\tint entries, len, maxlen, type;\n\tregister int c;\n\tregister unsigned value;\n\tchar sbuf[128];\n\n\tentries = -1;\n\n\tif (!(fsym = fopen(name, \"r\")))\n\t\treturn(-1);\n\tif (fread((char *)&ebuf, 1, sizeof(ebuf), fsym) != sizeof (ebuf) ||\n\t    N_BADMAG(ebuf))\n\t\tgoto done;\n\n\tsymbol_offset = N_SYMOFF(ebuf);\n\tsymbol_size = ebuf.a_syms;\n\tif (fseek(fsym, symbol_offset, L_SET))\n\t\tgoto done;\n\n\t/*\n\t * clean out any left-over information for all valid entries.\n\t * Type and value defined to be 0 if not found; historical\n\t * versions cleared other and desc as well.  Also figure out\n\t * the largest string length so don't read any more of the\n\t * string table than we have to.\n\t */\n\tfor (p = list, entries = maxlen = 0; ISVALID(p); ++p, ++entries) {\n\t\tp->n_type = 0;\n\t\tp->n_value = 0;\n\t\tif ((len = strlen(p->n_name)) > maxlen)\n\t\t\tmaxlen = len;\n\t}\n\tif (++maxlen > sizeof(sbuf)) {\t\t/* for the NULL */\n\t\t(void)fprintf(stderr, \"nlist: sym 2 big\\n\");\n\t\tentries = -1;\n\t\tgoto done;\n\t}\n\n\tfor (; symbol_size; symbol_size -= len + 6) {\n                len = getc (fsym);\n                if (len <= 0)\n\t\t\tbreak;\n\n                type = getc (fsym);\n                value = getc (fsym);\n                value |= getc (fsym) << 8;\n                value |= getc (fsym) << 16;\n                value |= getc (fsym) << 24;\n                for (c=0; c<len && c<maxlen; c++)\n                        sbuf [c] = getc (fsym);\n                sbuf [c] = '\\0';\n\n\t\tfor (p = list; ISVALID(p); p++)\n\t\t\tif (strcmp(p->n_name, sbuf) == 0) {\n\t\t\t\tp->n_value = value;\n\t\t\t\tp->n_type = type;\n\t\t\t\tif (!--entries)\n\t\t\t\t\tgoto done;\n\t\t\t}\n\t}\ndone:\t(void)fclose(fsym);\n\treturn(entries);\n}\n"
  },
  {
    "path": "lib/libc/gen/opendir.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/dir.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <fcntl.h>\n\n/*\n * open a directory.\n */\nDIR *\nopendir(name)\n\tconst char *name;\n{\n\tregister DIR *dirp;\n\tregister int fd;\n\n\tif ((fd = open(name, 0)) == -1)\n\t\treturn NULL;\n\tif ((dirp = (DIR *)malloc(sizeof(DIR))) == NULL) {\n\t\tclose (fd);\n\t\treturn NULL;\n\t}\n\tdirp->dd_fd = fd;\n\tdirp->dd_loc = 0;\n\treturn dirp;\n}\n"
  },
  {
    "path": "lib/libc/gen/perror.c",
    "content": "/*\n * Copyright (c) 1988, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/types.h>\n#include <sys/uio.h>\n#include <unistd.h>\n#include <errno.h>\n#include <stdio.h>\n#include <string.h>\n\nvoid\nperror(s)\n\tconst char *s;\n{\n\tregister struct iovec *v;\n\tstruct iovec iov[4];\n\n\tv = iov;\n\tif (s && *s) {\n\t\tv->iov_base = (char *)s;\n\t\tv->iov_len = strlen(s);\n\t\tv++;\n\t\tv->iov_base = \": \";\n\t\tv->iov_len = 2;\n\t\tv++;\n\t}\n\tv->iov_base = (void*) strerror(errno);\n\tv->iov_len = strlen(v->iov_base);\n\tv++;\n\tv->iov_base = \"\\n\";\n\tv->iov_len = 1;\n\t(void)writev(STDERR_FILENO, iov, (v - iov) + 1);\n}\n"
  },
  {
    "path": "lib/libc/gen/popen.c",
    "content": "/*\n * Copyright (c) 1988 The Regents of the University of California.\n * All rights reserved.\n *\n * This code is derived from software written by Ken Arnold and\n * published in UNIX Review, Vol. 6, No. 8.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <errno.h>\n#include <sys/signal.h>\n#include <sys/types.h>\n#include <sys/wait.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <strings.h>\n#include <unistd.h>\n\nstatic int *pids;\n\nFILE *\npopen(program, type)\n\tconst char *program;\n\tregister const char *type;\n{\n\tregister FILE *iop;\n\tint pdes[2], fds, pid;\n\n\tif (*type != 'r' && *type != 'w')\n\t\treturn (NULL);\n\tif (type[1])\n\t\treturn (NULL);\n\n\tif (pids == NULL) {\n\t\tif ((fds = getdtablesize()) <= 0)\n\t\t\treturn (NULL);\n\t\tif ((pids = (int *)malloc((u_int)(fds * sizeof(int)))) == NULL)\n\t\t\treturn (NULL);\n\t\tbzero((char *)pids, fds * sizeof(int));\n\t}\n\tif (pipe(pdes) < 0)\n\t\treturn (NULL);\n\tswitch (pid = vfork()) {\n\tcase -1:\t\t\t/* error */\n\t\t(void) close(pdes[0]);\n\t\t(void) close(pdes[1]);\n\t\treturn (NULL);\n\t\t/* NOTREACHED */\n\tcase 0:\t\t\t\t/* child */\n\t\tif (*type == 'r') {\n\t\t\tif (pdes[1] != fileno(stdout)) {\n\t\t\t\t(void) dup2(pdes[1], fileno(stdout));\n\t\t\t\t(void) close(pdes[1]);\n\t\t\t}\n\t\t\t(void) close(pdes[0]);\n\t\t} else {\n\t\t\tif (pdes[0] != fileno(stdin)) {\n\t\t\t\t(void) dup2(pdes[0], fileno(stdin));\n\t\t\t\t(void) close(pdes[0]);\n\t\t\t}\n\t\t\t(void) close(pdes[1]);\n\t\t}\n\t\texecl(\"/bin/sh\", \"sh\", \"-c\", program, (char*)0);\n\t\t_exit(127);\n\t\t/* NOTREACHED */\n\t}\n\t/* parent; assume fdopen can't fail...  */\n\tif (*type == 'r') {\n\t\tiop = fdopen(pdes[0], type);\n\t\t(void) close(pdes[1]);\n\t} else {\n\t\tiop = fdopen(pdes[1], type);\n\t\t(void) close(pdes[0]);\n\t}\n\tpids[fileno(iop)] = pid;\n\treturn (iop);\n}\n\nint\npclose(iop)\n\tFILE *iop;\n{\n\tregister int fdes;\n\tsigset_t omask, nmask;\n\tunion wait pstat;\n\tregister int pid;\n\n\t/*\n\t * pclose returns -1 if stream is not associated with a\n\t * `popened' command, if already `pclosed', or waitpid\n\t * returns an error.\n\t */\n\tif (pids == NULL || pids[fdes = fileno(iop)] == 0)\n\t\treturn (-1);\n\t(void) fclose(iop);\n\t(void) sigemptyset(&nmask);\n\t(void) sigaddset(&nmask, SIGINT);\n\t(void) sigaddset(&nmask, SIGQUIT);\n\t(void) sigaddset(&nmask, SIGHUP);\n\t(void) sigprocmask(SIG_BLOCK, &nmask, &omask);\n\tdo {\n\t\tpid = waitpid(pids[fdes], (int *) &pstat, 0);\n\t} while (pid == -1 && errno == EINTR);\n\t(void) sigprocmask(SIG_SETMASK, &omask, NULL);\n\tpids[fdes] = 0;\n\treturn (pid == -1 ? -1 : pstat.w_status);\n}\n"
  },
  {
    "path": "lib/libc/gen/psignal.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <string.h>\n#include <unistd.h>\n#include <signal.h>\n\n/*\n * Print the name of the signal indicated\n * along with the supplied message.\n */\n\nextern\tchar *sys_siglist[];\n\nvoid\npsignal(sig, s)\n\tunsigned sig;\n\tchar *s;\n{\n\tregister char *c;\n\tregister int n;\n\n\tc = \"Unknown signal\";\n\tif (sig < NSIG)\n\t\tc = sys_siglist[sig];\n\tn = strlen(s);\n\tif (n) {\n\t\twrite(2, s, n);\n\t\twrite(2, \": \", 2);\n\t}\n\twrite(2, c, strlen(c));\n\twrite(2, \"\\n\", 1);\n}\n"
  },
  {
    "path": "lib/libc/gen/qsort.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * qsort.c:\n * Our own version of the system qsort routine which is faster by an average\n * of 25%, with lows and highs of 10% and 50%.\n * The THRESHold below is the insertion sort threshold, and has been adjusted\n * for records of size 48 bytes.\n * The MTHREShold is where we stop finding a better median.\n */\n\n#define\t\tTHRESH\t\t4\t\t/* threshold for insertion */\n#define\t\tMTHRESH\t\t6\t\t/* threshold for median */\n\nstatic  int\t\t(*qcmp)();\t\t/* the comparison routine */\nstatic  int\t\tqsz;\t\t\t/* size of each record */\nstatic  int\t\tthresh;\t\t\t/* THRESHold in chars */\nstatic  int\t\tmthresh;\t\t/* MTHRESHold in chars */\n\n/*\n * qst:\n * Do a quicksort\n * First, find the median element, and put that one in the first place as the\n * discriminator.  (This \"median\" is just the median of the first, last and\n * middle elements).  (Using this median instead of the first element is a big\n * win).  Then, the usual partitioning/swapping, followed by moving the\n * discriminator into the right place.  Then, figure out the sizes of the two\n * partions, do the smaller one recursively and the larger one via a repeat of\n * this code.  Stopping when there are less than THRESH elements in a partition\n * and cleaning up with an insertion sort (in our caller) is a huge win.\n * All data swaps are done in-line, which is space-losing but time-saving.\n * (And there are only three places where this is done).\n */\nstatic void\nqst(base, max)\n\tchar *base, *max;\n{\n\tregister char c, *i, *j, *jj;\n\tregister int ii;\n\tchar *mid, *tmp;\n\tunsigned int lo, hi;\n\n\t/*\n\t * At the top here, lo is the number of characters of elements in the\n\t * current partition.  (Which should be max - base).\n\t * Find the median of the first, last, and middle element and make\n\t * that the middle element.  Set j to largest of first and middle.\n\t * If max is larger than that guy, then it's that guy, else compare\n\t * max with loser of first and take larger.  Things are set up to\n\t * prefer the middle, then the first in case of ties.\n\t */\n\tlo = max - base;\t\t/* number of elements as chars */\n\tdo\t{\n\t\tmid = i = base + qsz * ((lo / qsz) >> 1);\n\t\tif (lo >= mthresh) {\n\t\t\tj = (qcmp((jj = base), i) > 0 ? jj : i);\n\t\t\tif (qcmp(j, (tmp = max - qsz)) > 0) {\n\t\t\t\t/* switch to first loser */\n\t\t\t\tj = (j == jj ? i : jj);\n\t\t\t\tif (qcmp(j, tmp) < 0)\n\t\t\t\t\tj = tmp;\n\t\t\t}\n\t\t\tif (j != i) {\n\t\t\t\tii = qsz;\n\t\t\t\tdo\t{\n\t\t\t\t\tc = *i;\n\t\t\t\t\t*i++ = *j;\n\t\t\t\t\t*j++ = c;\n\t\t\t\t} while (--ii);\n\t\t\t}\n\t\t}\n\t\t/*\n\t\t * Semi-standard quicksort partitioning/swapping\n\t\t */\n\t\tfor (i = base, j = max - qsz; ; ) {\n\t\t\twhile (i < mid && qcmp(i, mid) <= 0)\n\t\t\t\ti += qsz;\n\t\t\twhile (j > mid) {\n\t\t\t\tif (qcmp(mid, j) <= 0) {\n\t\t\t\t\tj -= qsz;\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t\ttmp = i + qsz;\t/* value of i after swap */\n\t\t\t\tif (i == mid) {\n\t\t\t\t\t/* j <-> mid, new mid is j */\n\t\t\t\t\tmid = jj = j;\n\t\t\t\t} else {\n\t\t\t\t\t/* i <-> j */\n\t\t\t\t\tjj = j;\n\t\t\t\t\tj -= qsz;\n\t\t\t\t}\n\t\t\t\tgoto swap;\n\t\t\t}\n\t\t\tif (i == mid) {\n\t\t\t\tbreak;\n\t\t\t} else {\n\t\t\t\t/* i <-> mid, new mid is i */\n\t\t\t\tjj = mid;\n\t\t\t\ttmp = mid = i;\t/* value of i after swap */\n\t\t\t\tj -= qsz;\n\t\t\t}\n\t\tswap:\n\t\t\tii = qsz;\n\t\t\tdo\t{\n\t\t\t\tc = *i;\n\t\t\t\t*i++ = *jj;\n\t\t\t\t*jj++ = c;\n\t\t\t} while (--ii);\n\t\t\ti = tmp;\n\t\t}\n\t\t/*\n\t\t * Look at sizes of the two partitions, do the smaller\n\t\t * one first by recursion, then do the larger one by\n\t\t * making sure lo is its size, base and max are update\n\t\t * correctly, and branching back.  But only repeat\n\t\t * (recursively or by branching) if the partition is\n\t\t * of at least size THRESH.\n\t\t */\n\t\ti = (j = mid) + qsz;\n\t\tif ((lo = j - base) <= (hi = max - i)) {\n\t\t\tif (lo >= thresh)\n\t\t\t\tqst(base, j);\n\t\t\tbase = i;\n\t\t\tlo = hi;\n\t\t} else {\n\t\t\tif (hi >= thresh)\n\t\t\t\tqst(i, max);\n\t\t\tmax = j;\n\t\t}\n\t} while (lo >= thresh);\n}\n\n/*\n * qsort:\n * First, set up some global parameters for qst to share.  Then, quicksort\n * with qst(), and then a cleanup insertion sort ourselves.  Sound simple?\n * It's not...\n */\nvoid\nqsort(base, n, size, compar)\n\tchar\t*base;\n\tint\tn;\n\tint\tsize;\n\tint\t(*compar)();\n{\n\tregister char c, *i, *j, *lo, *hi;\n\tchar *min, *max;\n\n\tif (n <= 1)\n\t\treturn;\n\tqsz = size;\n\tqcmp = compar;\n\tthresh = qsz * THRESH;\n\tmthresh = qsz * MTHRESH;\n\tmax = base + n * qsz;\n\tif (n >= THRESH) {\n\t\tqst(base, max);\n\t\thi = base + thresh;\n\t} else {\n\t\thi = max;\n\t}\n\t/*\n\t * First put smallest element, which must be in the first THRESH, in\n\t * the first position as a sentinel.  This is done just by searching\n\t * the first THRESH elements (or the first n if n < THRESH), finding\n\t * the min, and swapping it into the first position.\n\t */\n\tfor (j = lo = base; (lo += qsz) < hi; )\n\t\tif (qcmp(j, lo) > 0)\n\t\t\tj = lo;\n\tif (j != base) {\n\t\t/* swap j into place */\n\t\tfor (i = base, hi = base + qsz; i < hi; ) {\n\t\t\tc = *j;\n\t\t\t*j++ = *i;\n\t\t\t*i++ = c;\n\t\t}\n\t}\n\t/*\n\t * With our sentinel in place, we now run the following hyper-fast\n\t * insertion sort.  For each remaining element, min, from [1] to [n-1],\n\t * set hi to the index of the element AFTER which this one goes.\n\t * Then, do the standard insertion sort shift on a character at a time\n\t * basis for each element in the frob.\n\t */\n\tfor (min = base; (hi = min += qsz) < max; ) {\n\t\twhile (qcmp(hi -= qsz, min) > 0)\n\t\t\t/* void */;\n\t\tif ((hi += qsz) != min) {\n\t\t\tfor (lo = min + qsz; --lo >= min; ) {\n\t\t\t\tc = *lo;\n\t\t\t\tfor (i = j = lo; (j -= qsz) >= hi; i = j)\n\t\t\t\t\t*i = *j;\n\t\t\t\t*i = c;\n\t\t\t}\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "lib/libc/gen/random.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <stdio.h>\n#include <stdlib.h>\n\n/*\n * random.c:\n * An improved random number generation package.  In addition to the standard\n * rand()/srand() like interface, this package also has a special state info\n * interface.  The initstate() routine is called with a seed, an array of\n * bytes, and a count of how many bytes are being passed in; this array is then\n * initialized to contain information for random number generation with that\n * much state information.  Good sizes for the amount of state information are\n * 32, 64, 128, and 256 bytes.  The state can be switched by calling the\n * setstate() routine with the same array as was initiallized with initstate().\n * By default, the package runs with 128 bytes of state information and\n * generates far better random numbers than a linear congruential generator.\n * If the amount of state information is less than 32 bytes, a simple linear\n * congruential R.N.G. is used.\n * Internally, the state information is treated as an array of longs; the\n * zeroeth element of the array is the type of R.N.G. being used (small\n * integer); the remainder of the array is the state information for the\n * R.N.G.  Thus, 32 bytes of state information will give 7 longs worth of\n * state information, which will allow a degree seven polynomial.  (Note: the\n * zeroeth word of state information also has some other information stored\n * in it -- see setstate() for details).\n * The random number generation technique is a linear feedback shift register\n * approach, employing trinomials (since there are fewer terms to sum up that\n * way).  In this approach, the least significant bit of all the numbers in\n * the state table will act as a linear feedback shift register, and will have\n * period 2^deg - 1 (where deg is the degree of the polynomial being used,\n * assuming that the polynomial is irreducible and primitive).  The higher\n * order bits will have longer periods, since their values are also influenced\n * by pseudo-random carries out of the lower bits.  The total period of the\n * generator is approximately deg*(2**deg - 1); thus doubling the amount of\n * state information has a vast influence on the period of the generator.\n * Note: the deg*(2**deg - 1) is an approximation only good for large deg,\n * when the period of the shift register is the dominant factor.  With deg\n * equal to seven, the period is actually much longer than the 7*(2**7 - 1)\n * predicted by this formula.\n */\n\n/*\n * For each of the currently supported random number generators, we have a\n * break value on the amount of state information (you need at least this\n * many bytes of state info to support this random number generator), a degree\n * for the polynomial (actually a trinomial) that the R.N.G. is based on, and\n * the separation between the two lower order coefficients of the trinomial.\n */\n#define\t\tTYPE_0\t\t0\t\t/* linear congruential */\n#define\t\tBREAK_0\t\t8\n#define\t\tDEG_0\t\t0\n#define\t\tSEP_0\t\t0\n\n#define\t\tTYPE_1\t\t1\t\t/* x**7 + x**3 + 1 */\n#define\t\tBREAK_1\t\t32\n#define\t\tDEG_1\t\t7\n#define\t\tSEP_1\t\t3\n\n#define\t\tTYPE_2\t\t2\t\t/* x**15 + x + 1 */\n#define\t\tBREAK_2\t\t64\n#define\t\tDEG_2\t\t15\n#define\t\tSEP_2\t\t1\n\n#define\t\tTYPE_3\t\t3\t\t/* x**31 + x**3 + 1 */\n#define\t\tBREAK_3\t\t128\n#define\t\tDEG_3\t\t31\n#define\t\tSEP_3\t\t3\n\n#define\t\tTYPE_4\t\t4\t\t/* x**63 + x + 1 */\n#define\t\tBREAK_4\t\t256\n#define\t\tDEG_4\t\t63\n#define\t\tSEP_4\t\t1\n\n\n/*\n * Array versions of the above information to make code run faster -- relies\n * on fact that TYPE_i == i.\n */\n#define\t\tMAX_TYPES\t5\t\t/* max number of types above */\n\nstatic int degrees[MAX_TYPES]\t= { DEG_0, DEG_1, DEG_2, DEG_3, DEG_4 };\n\nstatic int seps[MAX_TYPES]\t= { SEP_0, SEP_1, SEP_2, SEP_3, SEP_4 };\n\n\n/*\n * Initially, everything is set up as if from :\n *\t\tinitstate(1, &randtbl, 128);\n * Note that this initialization takes advantage of the fact that srandom()\n * advances the front and rear pointers 10*rand_deg times, and hence the\n * rear pointer which starts at 0 will also end up at zero; thus the zeroeth\n * element of the state information, which contains info about the current\n * position of the rear pointer is just\n *\tMAX_TYPES*(rptr - state) + TYPE_3 == TYPE_3.\n */\nstatic  long\t\trandtbl[DEG_3 + 1]\t= { TYPE_3,\n\t\t\t    0x9a319039, 0x32d9c024, 0x9b663182, 0x5da1f342,\n\t\t\t    0xde3b81e0, 0xdf0a6fb5, 0xf103bc02, 0x48f340fb,\n\t\t\t    0x7449e56b, 0xbeb1dbb0, 0xab5c5918, 0x946554fd,\n\t\t\t    0x8c2e680f, 0xeb3d799f, 0xb11ee0b7, 0x2d436b86,\n\t\t\t    0xda672e2a, 0x1588ca88, 0xe369735d, 0x904f35f7,\n\t\t\t    0xd7158fd6, 0x6fa6f051, 0x616e6b96, 0xac94efdc,\n\t\t\t    0x36413f93, 0xc622c298, 0xf5a42ab8, 0x8a88d77b,\n\t\t\t\t\t0xf5ad9d0e, 0x8999220b, 0x27fb47b9 };\n\n/*\n * fptr and rptr are two pointers into the state info, a front and a rear\n * pointer.  These two pointers are always rand_sep places aparts, as they cycle\n * cyclically through the state information.  (Yes, this does mean we could get\n * away with just one pointer, but the code for random() is more efficient this\n * way).  The pointers are left positioned as they would be from the call\n *\t\t\tinitstate(1, randtbl, 128)\n * (The position of the rear pointer, rptr, is really 0 (as explained above\n * in the initialization of randtbl) because the state table pointer is set\n * to point to randtbl[1] (as explained below).\n */\nstatic  long\t\t*fptr\t\t\t= &randtbl[SEP_3 + 1];\nstatic  long\t\t*rptr\t\t\t= &randtbl[1];\n\n/*\n * The following things are the pointer to the state information table,\n * the type of the current generator, the degree of the current polynomial\n * being used, and the separation between the two pointers.\n * Note that for efficiency of random(), we remember the first location of\n * the state information, not the zeroeth.  Hence it is valid to access\n * state[-1], which is used to store the type of the R.N.G.\n * Also, we remember the last location, since this is more efficient than\n * indexing every time to find the address of the last element to see if\n * the front and rear pointers have wrapped.\n */\nstatic  long\t\t*state\t\t\t= &randtbl[1];\n\nstatic  int\t\trand_type\t\t= TYPE_3;\nstatic  int\t\trand_deg\t\t= DEG_3;\nstatic  int\t\trand_sep\t\t= SEP_3;\n\nstatic  long\t\t*end_ptr\t\t= &randtbl[DEG_3 + 1];\n\n/*\n * srandom:\n * Initialize the random number generator based on the given seed.  If the\n * type is the trivial no-state-information type, just remember the seed.\n * Otherwise, initializes state[] based on the given \"seed\" via a linear\n * congruential generator.  Then, the pointers are set to known locations\n * that are exactly rand_sep places apart.  Lastly, it cycles the state\n * information a given number of times to get rid of any initial dependencies\n * introduced by the L.C.R.N.G.\n * Note that the initialization of randtbl[] for default usage relies on\n * values produced by this routine.\n */\nvoid\nsrandom (x)\n\tunsigned x;\n{\n    \tregister  int\ti;\n\n\tif (rand_type  ==  TYPE_0) {\n\t    state[0] = x;\n\t} else {\n\t    state[0] = x;\n\t    for(i = 1; i < rand_deg; i++) {\n\t\tstate[i] = 1103515245*state[i - 1] + 12345;\n\t    }\n\t    fptr = &state[rand_sep];\n\t    rptr = &state[0];\n\t    for(i = 0; i < 10*rand_deg; i++)  random();\n\t}\n}\n\n/*\n * initstate:\n * Initialize the state information in the given array of n bytes for\n * future random number generation.  Based on the number of bytes we\n * are given, and the break values for the different R.N.G.'s, we choose\n * the best (largest) one we can and set things up for it.  srandom() is\n * then called to initialize the state information.\n * Note that on return from srandom(), we set state[-1] to be the type\n * multiplexed with the current value of the rear pointer; this is so\n * successive calls to initstate() won't lose this information and will\n * be able to restart with setstate().\n * Note: the first thing we do is save the current state, if any, just like\n * setstate() so that it doesn't matter when initstate is called.\n * Returns a pointer to the old state.\n */\nchar *\ninitstate (seed, arg_state, n)\n\tunsigned\tseed;\t\t\t/* seed for R. N. G. */\n\tchar\t\t*arg_state;\t\t/* pointer to state array */\n\tint\t\tn;\t\t\t/* # bytes of state info */\n{\n\tregister  char\t*ostate\t\t= (char *)(&state[-1]);\n\n\tif (rand_type  ==  TYPE_0)  state[-1] = rand_type;\n\telse  state[-1] = MAX_TYPES*(rptr - state) + rand_type;\n\tif (n  <  BREAK_1) {\n\t    if (n  <  BREAK_0) {\n\t\tfprintf(stderr, \"initstate: not enough state (%d bytes) with which to do jack; ignored.\\n\", n);\n\t\treturn 0;\n\t    }\n\t    rand_type = TYPE_0;\n\t    rand_deg = DEG_0;\n\t    rand_sep = SEP_0;\n\t} else {\n\t    if (n  <  BREAK_2) {\n\t\trand_type = TYPE_1;\n\t\trand_deg = DEG_1;\n\t\trand_sep = SEP_1;\n\t    } else {\n\t\tif (n  <  BREAK_3) {\n\t\t    rand_type = TYPE_2;\n\t\t    rand_deg = DEG_2;\n\t\t    rand_sep = SEP_2;\n\t\t} else {\n\t\t    if (n  <  BREAK_4) {\n\t\t\trand_type = TYPE_3;\n\t\t\trand_deg = DEG_3;\n\t\t\trand_sep = SEP_3;\n\t\t    } else {\n\t\t\trand_type = TYPE_4;\n\t\t\trand_deg = DEG_4;\n\t\t\trand_sep = SEP_4;\n\t\t    }\n\t\t}\n\t    }\n\t}\n\tstate = &(((long *)arg_state)[1]);\t/* first location */\n\tend_ptr = &state[rand_deg];\t/* must set end_ptr before srandom */\n\tsrandom(seed);\n\tif (rand_type == TYPE_0)\n            state[-1] = rand_type;\n\telse\n            state[-1] = MAX_TYPES*(rptr - state) + rand_type;\n\treturn(ostate);\n}\n\n/*\n * setstate:\n * Restore the state from the given state array.\n * Note: it is important that we also remember the locations of the pointers\n * in the current state information, and restore the locations of the pointers\n * from the old state information.  This is done by multiplexing the pointer\n * location into the zeroeth word of the state information.\n * Note that due to the order in which things are done, it is OK to call\n * setstate() with the same state as the current state.\n * Returns a pointer to the old state information.\n */\nchar *\nsetstate (arg_state)\n\tchar\t*arg_state;\n{\n\tregister  long\t*new_state\t= (long *)arg_state;\n\tregister  int\ttype\t\t= new_state[0]%MAX_TYPES;\n\tregister  int\trear\t\t= new_state[0]/MAX_TYPES;\n\tchar\t\t*ostate\t\t= (char *)(&state[-1]);\n\n\tif (rand_type  ==  TYPE_0)  state[-1] = rand_type;\n\telse  state[-1] = MAX_TYPES*(rptr - state) + rand_type;\n\tswitch(type) {\n\t    case  TYPE_0:\n\t    case  TYPE_1:\n\t    case  TYPE_2:\n\t    case  TYPE_3:\n\t    case  TYPE_4:\n\t\trand_type = type;\n\t\trand_deg = degrees[type];\n\t\trand_sep = seps[type];\n\t\tbreak;\n\n\t    default:\n\t\tfprintf(stderr, \"setstate: state info has been munged; not changed.\\n\");\n\t}\n\tstate = &new_state[1];\n\tif (rand_type  !=  TYPE_0) {\n\t    rptr = &state[rear];\n\t    fptr = &state[(rear + rand_sep)%rand_deg];\n\t}\n\tend_ptr = &state[rand_deg];\t\t/* set end_ptr too */\n\treturn(ostate);\n}\n\n/*\n * random:\n * If we are using the trivial TYPE_0 R.N.G., just do the old linear\n * congruential bit.  Otherwise, we do our fancy trinomial stuff, which is the\n * same in all ther other cases due to all the global variables that have been\n * set up.  The basic operation is to add the number at the rear pointer into\n * the one at the front pointer.  Then both pointers are advanced to the next\n * location cyclically in the table.  The value returned is the sum generated,\n * reduced to 31 bits by throwing away the \"least random\" low bit.\n * Note: the code takes advantage of the fact that both the front and\n * rear pointers can't wrap on the same call by not testing the rear\n * pointer if the front one has wrapped.\n * Returns a 31-bit random number.\n */\nlong\nrandom()\n{\n\tlong\ti;\n\n\tif (rand_type  ==  TYPE_0) {\n\t    i = state[0] = (state[0]*1103515245 + 12345)&0x7fffffff;\n\t} else {\n\t    *fptr += *rptr;\n\t    i = (*fptr >> 1)&0x7fffffff;\t/* chucking least random bit */\n\t    if (++fptr  >=  end_ptr) {\n\t\tfptr = state;\n\t\t++rptr;\n\t    } else {\n\t\tif (++rptr >= end_ptr)\n                    rptr = state;\n\t    }\n\t}\n\treturn(i);\n}\n"
  },
  {
    "path": "lib/libc/gen/readdir.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/dir.h>\n#include <unistd.h>\n\n/*\n * get next entry in a directory.\n */\nstruct direct *\nreaddir(dirp)\n\tregister DIR *dirp;\n{\n\tregister struct direct *dp;\n\n\tfor (;;) {\n\t\tif (dirp->dd_loc == 0) {\n\t\t\tdirp->dd_size = read(dirp->dd_fd, dirp->dd_buf,\n\t\t\t    DIRBLKSIZ);\n\t\t\tif (dirp->dd_size <= 0)\n\t\t\t\treturn NULL;\n\t\t}\n\t\tif (dirp->dd_loc >= dirp->dd_size) {\n\t\t\tdirp->dd_loc = 0;\n\t\t\tcontinue;\n\t\t}\n\t\tdp = (struct direct *)(dirp->dd_buf + dirp->dd_loc);\n\t\tif (dp->d_reclen <= 0 ||\n\t\t    dp->d_reclen > DIRBLKSIZ + 1 - dirp->dd_loc)\n\t\t\treturn NULL;\n\t\tdirp->dd_loc += dp->d_reclen;\n\t\tif (dp->d_ino == 0)\n\t\t\tcontinue;\n\t\treturn (dp);\n\t}\n}\n"
  },
  {
    "path": "lib/libc/gen/regex.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * routines to do regular expression matching\n *\n * Entry points:\n *\n *\tre_comp(s)\n *\t\tchar *s;\n *\t ... returns 0 if the string s was compiled successfully,\n *\t\t     a pointer to an error message otherwise.\n *\t     If passed 0 or a null string returns without changing\n *           the currently compiled re (see note 11 below).\n *\n *\tre_exec(s)\n *\t\tchar *s;\n *\t ... returns 1 if the string s matches the last compiled regular\n *\t\t       expression,\n *\t\t     0 if the string s failed to match the last compiled\n *\t\t       regular expression, and\n *\t\t    -1 if the compiled regular expression was invalid\n *\t\t       (indicating an internal error).\n *\n * The strings passed to both re_comp and re_exec may have trailing or\n * embedded newline characters; they are terminated by nulls.\n *\n * The identity of the author of these routines is lost in antiquity;\n * this is essentially the same as the re code in the original V6 ed.\n *\n * The regular expressions recognized are described below. This description\n * is essentially the same as that for ed.\n *\n *\tA regular expression specifies a set of strings of characters.\n *\tA member of this set of strings is said to be matched by\n *\tthe regular expression.  In the following specification for\n *\tregular expressions the word `character' means any character but NUL.\n *\n *\t1.  Any character except a special character matches itself.\n *\t    Special characters are the regular expression delimiter plus\n *\t    \\ [ . and sometimes ^ * $.\n *\t2.  A . matches any character.\n *\t3.  A \\ followed by any character except a digit or ( )\n *\t    matches that character.\n *\t4.  A nonempty string s bracketed [s] (or [^s]) matches any\n *\t    character in (or not in) s. In s, \\ has no special meaning,\n *\t    and ] may only appear as the first letter. A substring\n *\t    a-b, with a and b in ascending ASCII order, stands for\n *\t    the inclusive range of ASCII characters.\n *\t5.  A regular expression of form 1-4 followed by * matches a\n *\t    sequence of 0 or more matches of the regular expression.\n *\t6.  A regular expression, x, of form 1-8, bracketed \\(x\\)\n *\t    matches what x matches.\n *\t7.  A \\ followed by a digit n matches a copy of the string that the\n *\t    bracketed regular expression beginning with the nth \\( matched.\n *\t8.  A regular expression of form 1-8, x, followed by a regular\n *\t    expression of form 1-7, y matches a match for x followed by\n *\t    a match for y, with the x match being as long as possible\n *\t    while still permitting a y match.\n *\t9.  A regular expression of form 1-8 preceded by ^ (or followed\n *\t    by $), is constrained to matches that begin at the left\n *\t    (or end at the right) end of a line.\n *\t10. A regular expression of form 1-9 picks out the longest among\n *\t    the leftmost matches in a line.\n *\t11. An empty regular expression stands for a copy of the last\n *\t    regular expression encountered.\n */\n\n/*\n * constants for re's\n */\n#define\tCBRA\t1\n#define\tCCHR\t2\n#define\tCDOT\t4\n#define\tCCL\t6\n#define\tNCCL\t8\n#define\tCDOL\t10\n#define\tCEOF\t11\n#define\tCKET\t12\n#define\tCBACK\t18\n\n#define\tCSTAR\t01\n\n#define\tESIZE\t512\n#define\tNBRA\t9\n\nstatic\tchar\texpbuf[ESIZE], *braslist[NBRA], *braelist[NBRA];\nstatic\tchar\tcircf;\n\n/*\n * compile the regular expression argument into a dfa\n */\nchar *\nre_comp(sp)\n\tregister char\t*sp;\n{\n\tregister int\tc;\n\tregister char\t*ep = expbuf;\n\tint\tcclcnt, numbra = 0;\n\tchar\t*lastep = 0;\n\tchar\tbracket[NBRA];\n\tchar\t*bracketp = &bracket[0];\n\tstatic\tchar\t*retoolong = \"Regular expression too long\";\n\n#define\tcomerr(msg) {expbuf[0] = 0; numbra = 0; return(msg); }\n\n\tif (sp == 0 || *sp == '\\0') {\n\t\tif (*ep == 0)\n\t\t\treturn(\"No previous regular expression\");\n\t\treturn(0);\n\t}\n\tif (*sp == '^') {\n\t\tcircf = 1;\n\t\tsp++;\n\t}\n\telse\n\t\tcircf = 0;\n\tfor (;;) {\n\t\tif (ep >= &expbuf[ESIZE])\n\t\t\tcomerr(retoolong);\n\t\tif ((c = *sp++) == '\\0') {\n\t\t\tif (bracketp != bracket)\n\t\t\t\tcomerr(\"unmatched \\\\(\");\n\t\t\t*ep++ = CEOF;\n\t\t\t*ep++ = 0;\n\t\t\treturn(0);\n\t\t}\n\t\tif (c != '*')\n\t\t\tlastep = ep;\n\t\tswitch (c) {\n\n\t\tcase '.':\n\t\t\t*ep++ = CDOT;\n\t\t\tcontinue;\n\n\t\tcase '*':\n\t\t\tif (lastep == 0 || *lastep == CBRA || *lastep == CKET)\n\t\t\t\tgoto defchar;\n\t\t\t*lastep |= CSTAR;\n\t\t\tcontinue;\n\n\t\tcase '$':\n\t\t\tif (*sp != '\\0')\n\t\t\t\tgoto defchar;\n\t\t\t*ep++ = CDOL;\n\t\t\tcontinue;\n\n\t\tcase '[':\n\t\t\t*ep++ = CCL;\n\t\t\t*ep++ = 0;\n\t\t\tcclcnt = 1;\n\t\t\tif ((c = *sp++) == '^') {\n\t\t\t\tc = *sp++;\n\t\t\t\tep[-2] = NCCL;\n\t\t\t}\n\t\t\tdo {\n\t\t\t\tif (c == '\\0')\n\t\t\t\t\tcomerr(\"missing ]\");\n\t\t\t\tif (c == '-' && ep [-1] != 0) {\n\t\t\t\t\tif ((c = *sp++) == ']') {\n\t\t\t\t\t\t*ep++ = '-';\n\t\t\t\t\t\tcclcnt++;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t\twhile (ep[-1] < c) {\n\t\t\t\t\t\t*ep = ep[-1] + 1;\n\t\t\t\t\t\tep++;\n\t\t\t\t\t\tcclcnt++;\n\t\t\t\t\t\tif (ep >= &expbuf[ESIZE])\n\t\t\t\t\t\t\tcomerr(retoolong);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t*ep++ = c;\n\t\t\t\tcclcnt++;\n\t\t\t\tif (ep >= &expbuf[ESIZE])\n\t\t\t\t\tcomerr(retoolong);\n\t\t\t} while ((c = *sp++) != ']');\n\t\t\tlastep[1] = cclcnt;\n\t\t\tcontinue;\n\n\t\tcase '\\\\':\n\t\t\tif ((c = *sp++) == '(') {\n\t\t\t\tif (numbra >= NBRA)\n\t\t\t\t\tcomerr(\"too many \\\\(\\\\) pairs\");\n\t\t\t\t*bracketp++ = numbra;\n\t\t\t\t*ep++ = CBRA;\n\t\t\t\t*ep++ = numbra++;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (c == ')') {\n\t\t\t\tif (bracketp <= bracket)\n\t\t\t\t\tcomerr(\"unmatched \\\\)\");\n\t\t\t\t*ep++ = CKET;\n\t\t\t\t*ep++ = *--bracketp;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (c >= '1' && c < ('1' + NBRA)) {\n\t\t\t\t*ep++ = CBACK;\n\t\t\t\t*ep++ = c - '1';\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t*ep++ = CCHR;\n\t\t\t*ep++ = c;\n\t\t\tcontinue;\n\n\t\tdefchar:\n\t\tdefault:\n\t\t\t*ep++ = CCHR;\n\t\t\t*ep++ = c;\n\t\t}\n\t}\n}\n\nstatic int\ncclass(set, c, af)\n\tregister char\t*set, c;\n\tint\taf;\n{\n\tregister int\tn;\n\n\tif (c == 0)\n\t\treturn(0);\n\tn = *set++;\n\twhile (--n)\n\t\tif (*set++ == c)\n\t\t\treturn(af);\n\treturn(! af);\n}\n\nstatic int\nbackref(i, lp)\n\tregister int\ti;\n\tregister char\t*lp;\n{\n\tregister char\t*bp;\n\n\tbp = braslist[i];\n\twhile (*bp++ == *lp++)\n\t\tif (bp >= braelist[i])\n\t\t\treturn(1);\n\treturn(0);\n}\n\n/*\n * try to match the next thing in the dfa\n */\nstatic\tint\nadvance(lp, ep)\n\tregister char\t*lp, *ep;\n{\n\tregister char\t*curlp;\n\tint\tct, i;\n\tint\trv;\n\n\tfor (;;)\n\t\tswitch (*ep++) {\n\n\t\tcase CCHR:\n\t\t\tif (*ep++ == *lp++)\n\t\t\t\tcontinue;\n\t\t\treturn(0);\n\n\t\tcase CDOT:\n\t\t\tif (*lp++)\n\t\t\t\tcontinue;\n\t\t\treturn(0);\n\n\t\tcase CDOL:\n\t\t\tif (*lp == '\\0')\n\t\t\t\tcontinue;\n\t\t\treturn(0);\n\n\t\tcase CEOF:\n\t\t\treturn(1);\n\n\t\tcase CCL:\n\t\t\tif (cclass(ep, *lp++, 1)) {\n\t\t\t\tep += *ep;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\treturn(0);\n\n\t\tcase NCCL:\n\t\t\tif (cclass(ep, *lp++, 0)) {\n\t\t\t\tep += *ep;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\treturn(0);\n\n\t\tcase CBRA:\n\t\t\tbraslist[(unsigned char)*ep++] = lp;\n\t\t\tcontinue;\n\n\t\tcase CKET:\n\t\t\tbraelist[(unsigned char)*ep++] = lp;\n\t\t\tcontinue;\n\n\t\tcase CBACK:\n\t\t\tif (braelist[i = *ep++] == 0)\n\t\t\t\treturn(-1);\n\t\t\tif (backref(i, lp)) {\n\t\t\t\tlp += braelist[i] - braslist[i];\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\treturn(0);\n\n\t\tcase CBACK|CSTAR:\n\t\t\tif (braelist[i = *ep++] == 0)\n\t\t\t\treturn(-1);\n\t\t\tcurlp = lp;\n\t\t\tct = braelist[i] - braslist[i];\n\t\t\twhile (backref(i, lp))\n\t\t\t\tlp += ct;\n\t\t\twhile (lp >= curlp) {\n\t\t\t        rv = advance(lp, ep);\n\t\t\t\tif (rv)\n\t\t\t\t\treturn(rv);\n\t\t\t\tlp -= ct;\n\t\t\t}\n\t\t\tcontinue;\n\n\t\tcase CDOT|CSTAR:\n\t\t\tcurlp = lp;\n\t\t\twhile (*lp++)\n\t\t\t\t;\n\t\t\tgoto star;\n\n\t\tcase CCHR|CSTAR:\n\t\t\tcurlp = lp;\n\t\t\twhile (*lp++ == *ep)\n\t\t\t\t;\n\t\t\tep++;\n\t\t\tgoto star;\n\n\t\tcase CCL|CSTAR:\n\t\tcase NCCL|CSTAR:\n\t\t\tcurlp = lp;\n\t\t\twhile (cclass(ep, *lp++, ep[-1] == (CCL|CSTAR)))\n\t\t\t\t;\n\t\t\tep += *ep;\n\t\t\tgoto star;\n\n\t\tstar:\n\t\t\tdo {\n\t\t\t\tlp--;\n\t\t\t\trv = advance(lp, ep);\n\t\t\t\tif (rv)\n\t\t\t\t\treturn(rv);\n\t\t\t} while (lp > curlp);\n\t\t\treturn(0);\n\n\t\tdefault:\n\t\t\treturn(-1);\n\t\t}\n}\n\n/*\n * match the argument string against the compiled re\n */\nint\nre_exec(p1)\n\tregister char\t*p1;\n{\n\tregister char\t*p2 = expbuf;\n\tregister int\tc;\n\tint\trv;\n\n\tfor (c = 0; c < NBRA; c++) {\n\t\tbraslist[c] = 0;\n\t\tbraelist[c] = 0;\n\t}\n\tif (circf)\n\t\treturn((advance(p1, p2)));\n\t/*\n\t * fast check for first character\n\t */\n\tif (*p2 == CCHR) {\n\t\tc = p2[1];\n\t\tdo {\n\t\t\tif (*p1 != c)\n\t\t\t\tcontinue;\n                        rv = advance(p1, p2);\n\t\t\tif (rv)\n\t\t\t\treturn(rv);\n\t\t} while (*p1++);\n\t\treturn(0);\n\t}\n\t/*\n\t * regular algorithm\n\t */\n\tdo {\n\t        rv = advance(p1, p2);\n\t\tif (rv)\n\t\t\treturn(rv);\n\t} while (*p1++);\n\treturn(0);\n}\n"
  },
  {
    "path": "lib/libc/gen/remque.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * remque -- vax remque instruction\n *\n * NOTE: this implementation is non-atomic!!\n */\n\nstruct vaxque {\t\t/* queue format expected by VAX queue instructions */\n\tstruct vaxque\t*vq_next;\n\tstruct vaxque\t*vq_prev;\n};\n\nremque(e)\n\tregister struct vaxque *e;\n{\n\te->vq_prev->vq_next = e->vq_next;\n\te->vq_next->vq_prev = e->vq_prev;\n}\n"
  },
  {
    "path": "lib/libc/gen/rindex.c",
    "content": "/*\n * Return the ptr in sp at which the character c last\n * appears; NULL if not found\n */\n\n#define NULL 0\n\nchar *\nrindex(sp, c)\n\tregister const char *sp;\n\tregister int c;\n{\n\tregister char *r;\n\n\tr = NULL;\n\tdo {\n\t\tif (*sp == (char)c)\n\t\t\tr = (char *)sp;\n\t} while (*sp++);\n\treturn(r);\n}\n"
  },
  {
    "path": "lib/libc/gen/scandir.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * Scan the directory dirname calling select to make a list of selected\n * directory entries then sort using qsort and compare routine dcomp.\n * Returns the number of entries and a pointer to a list of pointers to\n * struct direct (through namelist). Returns -1 if there were any errors.\n */\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <sys/dir.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n\nint\nscandir(dirname, namelist, select, dcomp)\n\tchar *dirname;\n\tstruct direct *(*namelist[]);\n\tint (*select)(), (*dcomp)();\n{\n\tregister struct direct *d, *p, **names;\n\tregister int nitems;\n\tregister char *cp1, *cp2;\n\tstruct stat stb;\n\tint arraysz;\n\tDIR *dirp;\n\n\tif ((dirp = opendir(dirname)) == NULL)\n\t\treturn(-1);\n\tif (fstat(dirp->dd_fd, &stb) < 0)\n\t\treturn(-1);\n\n\t/*\n\t * estimate the array size by taking the size of the directory file\n\t * and dividing it by a multiple of the minimum size entry.\n\t */\n\tarraysz = (stb.st_size / 24);\n\tnames = (struct direct **)malloc(arraysz * sizeof(struct direct *));\n\tif (names == NULL)\n\t\treturn(-1);\n\n\tnitems = 0;\n\twhile ((d = readdir(dirp)) != NULL) {\n\t\tif (select != NULL && !(*select)(d))\n\t\t\tcontinue;\t/* just selected names */\n\t\t/*\n\t\t * Make a minimum size copy of the data\n\t\t */\n\t\tp = (struct direct *)malloc(DIRSIZ(d));\n\t\tif (p == NULL)\n\t\t\treturn(-1);\n\t\tp->d_ino = d->d_ino;\n\t\tp->d_reclen = d->d_reclen;\n\t\tp->d_namlen = d->d_namlen;\n\t\tfor (cp1 = p->d_name, cp2 = d->d_name; (*cp1++ = *cp2++); );\n\n\t\t/*\n\t\t * Check to make sure the array has space left and\n\t\t * realloc the maximum size.\n\t\t */\n\t\tif (++nitems >= arraysz) {\n\t\t\tif (fstat(dirp->dd_fd, &stb) < 0)\n\t\t\t\treturn(-1);\t/* just might have grown */\n\t\t\tarraysz = stb.st_size / 12;\n\t\t\tnames = (struct direct **)realloc((char *)names,\n\t\t\t\tarraysz * sizeof(struct direct *));\n\t\t\tif (names == NULL)\n\t\t\t\treturn(-1);\n\t\t}\n\t\tnames[nitems-1] = p;\n\t}\n\tclosedir(dirp);\n\tif (nitems && dcomp != NULL)\n\t\tqsort(names, nitems, sizeof(struct direct *), dcomp);\n\t*namelist = names;\n\treturn(nitems);\n}\n\n/*\n * Alphabetic order comparison routine for those who want it.\n */\nint\nalphasort(d1, d2)\n\tstruct direct **d1, **d2;\n{\n\treturn(strcmp((*d1)->d_name, (*d2)->d_name));\n}\n"
  },
  {
    "path": "lib/libc/gen/seekdir.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#include <sys/param.h>\n#include <sys/dir.h>\n\n/*\n * seek to an entry in a directory.\n * Only values returned by \"telldir\" should be passed to seekdir.\n */\nvoid\nseekdir(dirp, loc)\n\tregister DIR *dirp;\n\tlong loc;\n{\n\tlong curloc, base, offset;\n\tstruct direct *dp;\n\textern long lseek();\n\n\tcurloc = telldir(dirp);\n\tif (loc == curloc)\n\t\treturn;\n\tbase = loc & ~(DIRBLKSIZ - 1);\n\toffset = loc & (DIRBLKSIZ - 1);\n\t(void) lseek(dirp->dd_fd, base, 0);\n\tdirp->dd_loc = 0;\n\twhile (dirp->dd_loc < offset) {\n\t\tdp = readdir(dirp);\n\t\tif (dp == NULL)\n\t\t\treturn;\n\t}\n}\n"
  },
  {
    "path": "lib/libc/gen/setenv.c",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/types.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <strings.h>\n#include <unistd.h>\n\n/*\n * setenv(name,value,rewrite)\n *\tSet the value of the environmental variable \"name\" to be\n *\t\"value\".  If rewrite is set, replace any current value.\n */\nint\nsetenv(name, value, rewrite)\n\tregister const char\t*name,\n\t\t\t\t*value;\n\tint\trewrite;\n{\n\tstatic int\talloced;\t\t/* if allocated space before */\n\tregister char\t*C;\n\tregister const char *E;\n\tint l_value, offset;\n\n\tif (*value == '=')\t\t\t/* no `=' in value */\n\t\t++value;\n\tl_value = strlen(value);\n\tif ((C = _findenv(name,&offset))) {\t/* find if already exists */\n\t\tif (!rewrite)\n\t\t\treturn(0);\n\t\tif (strlen(C) >= l_value) {\t/* old larger; copy over */\n\t\t\twhile ((*C++ = *value++));\n\t\t\treturn(0);\n\t\t}\n\t}\n\telse {\t\t\t\t\t/* create new slot */\n\t\tregister int\tcnt;\n\t\tregister char\t**P;\n\n\t\tfor (P = environ,cnt = 0;*P;++P,++cnt);\n\t\tif (alloced) {\t\t\t/* just increase size */\n\t\t\tenviron = (char **)realloc((char *)environ,\n\t\t\t    (u_int)(sizeof(char *) * (cnt + 2)));\n\t\t\tif (!environ)\n\t\t\t\treturn(-1);\n\t\t}\n\t\telse {\t\t\t\t/* get new space */\n\t\t\talloced = 1;\t\t/* copy old entries into it */\n\t\t\tP = (char **)malloc((u_int)(sizeof(char *) *\n\t\t\t    (cnt + 2)));\n\t\t\tif (!P)\n\t\t\t\treturn(-1);\n\t\t\tbcopy(environ,P,cnt * sizeof(char *));\n\t\t\tenviron = P;\n\t\t}\n\t\tenviron[cnt + 1] = NULL;\n\t\toffset = cnt;\n\t}\n\tfor (E = name; *E && *E != '='; ++E);\t/* no `=' in name */\n\tif (!(environ[offset] =\t\t\t/* name + `=' + value */\n\t    malloc((u_int)((int)(E - name) + l_value + 2))))\n\t\treturn(-1);\n\tfor (C = environ[offset]; (*C = *name++) && *C != '='; ++C);\n\tfor (*C++ = '='; (*C++ = *value++); );\n\treturn(0);\n}\n\n/*\n * unsetenv(name) --\n *\tDelete environmental variable \"name\".\n */\nint\nunsetenv(name)\n\tconst char\t*name;\n{\n\tregister char\t**P;\n\tint\toffset;\n\n\twhile (_findenv(name,&offset))\t\t/* if set multiple times */\n\t\tfor (P = &environ[offset];;++P)\n\t\t\tif (!(*P = *(P + 1)))\n\t\t\t\tbreak;\n        return 0;\n}\n"
  },
  {
    "path": "lib/libc/gen/sethostname.c",
    "content": "/*\n * Copyright (c) 1989, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/param.h>\n#include <sys/sysctl.h>\n\nint\nsethostname(name, namelen)\n\tchar *name;\n\tint namelen;\n{\n\tint mib[2];\n\n\tmib[0] = CTL_KERN;\n\tmib[1] = KERN_HOSTNAME;\n\tif (sysctl(mib, 2, NULL, NULL, (void *)name, namelen) == -1)\n\t\treturn (-1);\n\treturn (0);\n}\n"
  },
  {
    "path": "lib/libc/gen/setmode.c",
    "content": "/*\n * Copyright (c) 1989, 1993, 1994\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Dave Borman at Cray Research, Inc.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/types.h>\n#include <sys/stat.h>\n\n#include <ctype.h>\n#include <errno.h>\n#include <signal.h>\n#include <stdlib.h>\n\n#ifdef SETMODE_DEBUG\n#include <stdio.h>\n#endif\n\n#define\tSET_LEN\t6\t\t/* initial # of bitcmd struct to malloc */\n#define\tSET_LEN_INCR 4\t\t/* # of bitcmd structs to add as needed */\n\ntypedef struct bitcmd {\n\tchar\tcmd;\n\tchar\tcmd2;\n\tmode_t\tbits;\n} BITCMD;\n\n#define\tCMD2_CLR\t0x01\n#define\tCMD2_SET\t0x02\n#define\tCMD2_GBITS\t0x04\n#define\tCMD2_OBITS\t0x08\n#define\tCMD2_UBITS\t0x10\n\nstatic BITCMD\t*addcmd();\nstatic int\t compress_mode();\n#ifdef SETMODE_DEBUG\nstatic void\t dumpmode();\n#endif\n\n/*\n * Given the old mode and an array of bitcmd structures, apply the operations\n * described in the bitcmd structures to the old mode, and return the new mode.\n * Note that there is no '=' command; a strict assignment is just a '-' (clear\n * bits) followed by a '+' (set bits).\n */\nmode_t\ngetmode(bbox, omode)\n\tvoid *bbox;\n\tmode_t omode;\n{\n\tregister BITCMD *set;\n\tregister mode_t clrval, newmode, value;\n\n\tset = (BITCMD *)bbox;\n\tnewmode = omode;\n\tfor (value = 0;; set++)\n\t\tswitch(set->cmd) {\n\t\t/*\n\t\t * When copying the user, group or other bits around, we \"know\"\n\t\t * where the bits are in the mode so that we can do shifts to\n\t\t * copy them around.  If we don't use shifts, it gets real\n\t\t * grundgy with lots of single bit checks and bit sets.\n\t\t */\n\t\tcase 'u':\n\t\t\tvalue = (newmode & S_IRWXU) >> 6;\n\t\t\tgoto common;\n\n\t\tcase 'g':\n\t\t\tvalue = (newmode & S_IRWXG) >> 3;\n\t\t\tgoto common;\n\n\t\tcase 'o':\n\t\t\tvalue = newmode & S_IRWXO;\ncommon:\t\t\tif (set->cmd2 & CMD2_CLR) {\n\t\t\t\tclrval =\n\t\t\t\t    (set->cmd2 & CMD2_SET) ?  S_IRWXO : value;\n\t\t\t\tif (set->cmd2 & CMD2_UBITS)\n\t\t\t\t\tnewmode &= ~((clrval<<6) & set->bits);\n\t\t\t\tif (set->cmd2 & CMD2_GBITS)\n\t\t\t\t\tnewmode &= ~((clrval<<3) & set->bits);\n\t\t\t\tif (set->cmd2 & CMD2_OBITS)\n\t\t\t\t\tnewmode &= ~(clrval & set->bits);\n\t\t\t}\n\t\t\tif (set->cmd2 & CMD2_SET) {\n\t\t\t\tif (set->cmd2 & CMD2_UBITS)\n\t\t\t\t\tnewmode |= (value<<6) & set->bits;\n\t\t\t\tif (set->cmd2 & CMD2_GBITS)\n\t\t\t\t\tnewmode |= (value<<3) & set->bits;\n\t\t\t\tif (set->cmd2 & CMD2_OBITS)\n\t\t\t\t\tnewmode |= value & set->bits;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase '+':\n\t\t\tnewmode |= set->bits;\n\t\t\tbreak;\n\n\t\tcase '-':\n\t\t\tnewmode &= ~set->bits;\n\t\t\tbreak;\n\n\t\tcase 'X':\n\t\t\tif (omode & (S_IFDIR|S_IXUSR|S_IXGRP|S_IXOTH))\n\t\t\t\tnewmode |= set->bits;\n\t\t\tbreak;\n\n\t\tcase '\\0':\n\t\tdefault:\n#ifdef SETMODE_DEBUG\n\t\t\t(void)printf(\"getmode:%04o -> %04o\\n\", omode, newmode);\n#endif\n\t\t\treturn (newmode);\n\t\t}\n}\n\n#define\tADDCMD(a, b, c, d)\t\t\t\t\t\t\\\n\tif (set >= endset) {\t\t\t\t\t\t\\\n\t\tregister BITCMD *newset;\t\t\t\t\\\n\t\tsetlen += SET_LEN_INCR;\t\t\t\t\t\\\n\t\tnewset = (BITCMD *)realloc(saveset, sizeof(BITCMD) * setlen); \\\n\t\tif (!saveset)\t\t\t\t\t\t\\\n\t\t\treturn ((void *)NULL);\t\t\t\t\\\n\t\tset = newset + (set - saveset);\t\t\t\t\\\n\t\tsaveset = newset;\t\t\t\t\t\\\n\t\tendset = newset + (setlen - 2);\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\\\n\tset = addcmd(set, (a), (b), (c), (d))\n\n#define\tSTANDARD_BITS\t(S_ISUID|S_ISGID|S_IRWXU|S_IRWXG|S_IRWXO)\n\nvoid *\nsetmode(p)\n\tregister char *p;\n{\n\tregister int perm, who;\n\tchar op;\n\tBITCMD *set, *saveset, *endset;\n#ifdef\tnotnow\n\tsigset_t sigset, sigoset;\n#endif\n\tmode_t mask;\n\tint equalopdone = 0, permXbits, setlen;\n\n\tif (!*p)\n\t\treturn ((void *)NULL);\n\n#ifdef\tnotnow\n\t/*\n\t * Get a copy of the mask for the permissions that are mask relative.\n\t * Flip the bits, we want what's not set.  Since it's possible that\n\t * the caller is opening files inside a signal handler, protect them\n\t * as best we can.\n\t */\n\t(void)sigfillset(&sigset);\n        (void)sigprocmask(SIG_BLOCK, &sigset, &sigoset);\n#endif\n\t(void)umask(mask = umask(0));\n\tmask = ~mask;\n#ifdef\tnotnow\n        (void)sigprocmask(SIG_SETMASK, &sigoset, NULL);\n#endif\n\n\tsetlen = SET_LEN + 2;\n\n\tif ((set = (BITCMD *)malloc((u_int)(sizeof(BITCMD) * setlen))) == NULL)\n\t\treturn ((void *)NULL);\n\tsaveset = set;\n\tendset = set + (setlen - 2);\n\n\t/*\n\t * If an absolute number, get it and return; disallow non-octal digits\n\t * or illegal bits.\n\t */\n\tif (isdigit(*p)) {\n\t\tperm = (mode_t)strtol(p, NULL, 8);\n\t\tif (perm & ~(STANDARD_BITS|S_ISVTX)) {\n\t\t\tfree(saveset);\n\t\t\treturn ((void *)NULL);\n\t\t}\n\t\twhile (*++p)\n\t\t\tif (*p < '0' || *p > '7') {\n\t\t\t\tfree(saveset);\n\t\t\t\treturn ((void *)NULL);\n\t\t\t}\n\t\tADDCMD('=', (STANDARD_BITS|S_ISVTX), perm, mask);\n\t\treturn ((void *)saveset);\n\t}\n\n\t/*\n\t * Build list of structures to set/clear/copy bits as described by\n\t * each clause of the symbolic mode.\n\t */\n\tfor (;;) {\n\t\t/* First, find out which bits might be modified. */\n\t\tfor (who = 0;; ++p) {\n\t\t\tswitch (*p) {\n\t\t\tcase 'a':\n\t\t\t\twho |= STANDARD_BITS;\n\t\t\t\tbreak;\n\t\t\tcase 'u':\n\t\t\t\twho |= S_ISUID|S_IRWXU;\n\t\t\t\tbreak;\n\t\t\tcase 'g':\n\t\t\t\twho |= S_ISGID|S_IRWXG;\n\t\t\t\tbreak;\n\t\t\tcase 'o':\n\t\t\t\twho |= S_IRWXO;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tgoto getop;\n\t\t\t}\n\t\t}\n\ngetop:\t\tif ((op = *p++) != '+' && op != '-' && op != '=') {\n\t\t\tfree(saveset);\n\t\t\treturn ((void *)NULL);\n\t\t}\n\t\tif (op == '=')\n\t\t\tequalopdone = 0;\n\n\t\twho &= ~S_ISVTX;\n\t\tfor (perm = 0, permXbits = 0;; ++p) {\n\t\t\tswitch (*p) {\n\t\t\tcase 'r':\n\t\t\t\tperm |= S_IRUSR|S_IRGRP|S_IROTH;\n\t\t\t\tbreak;\n\t\t\tcase 's':\n\t\t\t\t/* If only \"other\" bits ignore set-id. */\n\t\t\t\tif (who & ~S_IRWXO)\n\t\t\t\t\tperm |= S_ISUID|S_ISGID;\n\t\t\t\tbreak;\n\t\t\tcase 't':\n\t\t\t\t/* If only \"other\" bits ignore sticky. */\n\t\t\t\tif (who & ~S_IRWXO) {\n\t\t\t\t\twho |= S_ISVTX;\n\t\t\t\t\tperm |= S_ISVTX;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 'w':\n\t\t\t\tperm |= S_IWUSR|S_IWGRP|S_IWOTH;\n\t\t\t\tbreak;\n\t\t\tcase 'X':\n\t\t\t\tpermXbits = S_IXUSR|S_IXGRP|S_IXOTH;\n\t\t\t\tbreak;\n\t\t\tcase 'x':\n\t\t\t\tperm |= S_IXUSR|S_IXGRP|S_IXOTH;\n\t\t\t\tbreak;\n\t\t\tcase 'u':\n\t\t\tcase 'g':\n\t\t\tcase 'o':\n\t\t\t\t/*\n\t\t\t\t * When ever we hit 'u', 'g', or 'o', we have\n\t\t\t\t * to flush out any partial mode that we have,\n\t\t\t\t * and then do the copying of the mode bits.\n\t\t\t\t */\n\t\t\t\tif (perm) {\n\t\t\t\t\tADDCMD(op, who, perm, mask);\n\t\t\t\t\tperm = 0;\n\t\t\t\t}\n\t\t\t\tif (op == '=')\n\t\t\t\t\tequalopdone = 1;\n\t\t\t\tif (op == '+' && permXbits) {\n\t\t\t\t\tADDCMD('X', who, permXbits, mask);\n\t\t\t\t\tpermXbits = 0;\n\t\t\t\t}\n\t\t\t\tADDCMD(*p, who, op, mask);\n\t\t\t\tbreak;\n\n\t\t\tdefault:\n\t\t\t\t/*\n\t\t\t\t * Add any permissions that we haven't already\n\t\t\t\t * done.\n\t\t\t\t */\n\t\t\t\tif (perm || (op == '=' && !equalopdone)) {\n\t\t\t\t\tif (op == '=')\n\t\t\t\t\t\tequalopdone = 1;\n\t\t\t\t\tADDCMD(op, who, perm, mask);\n\t\t\t\t\tperm = 0;\n\t\t\t\t}\n\t\t\t\tif (permXbits) {\n\t\t\t\t\tADDCMD('X', who, permXbits, mask);\n\t\t\t\t\tpermXbits = 0;\n\t\t\t\t}\n\t\t\t\tgoto apply;\n\t\t\t}\n\t\t}\n\napply:\t\tif (!*p)\n\t\t\tbreak;\n\t\tif (*p != ',')\n\t\t\tgoto getop;\n\t\t++p;\n\t}\n\tset->cmd = 0;\n#ifdef SETMODE_DEBUG\n\t(void)printf(\"Before compress_mode()\\n\");\n\tdumpmode(saveset);\n#endif\n\tcompress_mode(saveset);\n#ifdef SETMODE_DEBUG\n\t(void)printf(\"After compress_mode()\\n\");\n\tdumpmode(saveset);\n#endif\n\treturn ((void *)saveset);\n}\n\nstatic BITCMD *\naddcmd(set, op, who, oparg, mask)\n\tBITCMD *set;\n\tregister int oparg, who;\n\tregister int op;\n\tu_int mask;\n{\n\tswitch (op) {\n\tcase '=':\n\t\tset->cmd = '-';\n\t\tset->bits = who ? who : STANDARD_BITS;\n\t\tset++;\n\n\t\top = '+';\n\t\t/* FALLTHROUGH */\n\tcase '+':\n\tcase '-':\n\tcase 'X':\n\t\tset->cmd = op;\n\t\tset->bits = (who ? who : mask) & oparg;\n\t\tbreak;\n\n\tcase 'u':\n\tcase 'g':\n\tcase 'o':\n\t\tset->cmd = op;\n\t\tif (who) {\n\t\t\tset->cmd2 = ((who & S_IRUSR) ? CMD2_UBITS : 0) |\n\t\t\t\t    ((who & S_IRGRP) ? CMD2_GBITS : 0) |\n\t\t\t\t    ((who & S_IROTH) ? CMD2_OBITS : 0);\n\t\t\tset->bits = ~0;\n\t\t} else {\n\t\t\tset->cmd2 = CMD2_UBITS | CMD2_GBITS | CMD2_OBITS;\n\t\t\tset->bits = mask;\n\t\t}\n\n\t\tif (oparg == '+')\n\t\t\tset->cmd2 |= CMD2_SET;\n\t\telse if (oparg == '-')\n\t\t\tset->cmd2 |= CMD2_CLR;\n\t\telse if (oparg == '=')\n\t\t\tset->cmd2 |= CMD2_SET|CMD2_CLR;\n\t\tbreak;\n\t}\n\treturn (set + 1);\n}\n\n#ifdef SETMODE_DEBUG\nstatic void\ndumpmode(set)\n\tregister BITCMD *set;\n{\n\tfor (; set->cmd; ++set)\n\t\t(void)printf(\"cmd: '%c' bits %04o%s%s%s%s%s%s\\n\",\n\t\t    set->cmd, set->bits, set->cmd2 ? \" cmd2:\" : \"\",\n\t\t    set->cmd2 & CMD2_CLR ? \" CLR\" : \"\",\n\t\t    set->cmd2 & CMD2_SET ? \" SET\" : \"\",\n\t\t    set->cmd2 & CMD2_UBITS ? \" UBITS\" : \"\",\n\t\t    set->cmd2 & CMD2_GBITS ? \" GBITS\" : \"\",\n\t\t    set->cmd2 & CMD2_OBITS ? \" OBITS\" : \"\");\n}\n#endif\n\n/*\n * Given an array of bitcmd structures, compress by compacting consecutive\n * '+', '-' and 'X' commands into at most 3 commands, one of each.  The 'u',\n * 'g' and 'o' commands continue to be separate.  They could probably be\n * compacted, but it's not worth the effort.\n */\nstatic int\ncompress_mode(set)\n\tregister BITCMD *set;\n{\n\tregister BITCMD *nset;\n\tregister int setbits, clrbits, Xbits, op;\n\n\tfor (nset = set;;) {\n\t\t/* Copy over any 'u', 'g' and 'o' commands. */\n\t\twhile ((op = nset->cmd) != '+' && op != '-' && op != 'X') {\n\t\t\t*set++ = *nset++;\n\t\t\tif (!op)\n\t\t\t\treturn 0;\n\t\t}\n\n\t\tfor (setbits = clrbits = Xbits = 0;; nset++) {\n\t\t\tif ((op = nset->cmd) == '-') {\n\t\t\t\tclrbits |= nset->bits;\n\t\t\t\tsetbits &= ~nset->bits;\n\t\t\t\tXbits &= ~nset->bits;\n\t\t\t} else if (op == '+') {\n\t\t\t\tsetbits |= nset->bits;\n\t\t\t\tclrbits &= ~nset->bits;\n\t\t\t\tXbits &= ~nset->bits;\n\t\t\t} else if (op == 'X')\n\t\t\t\tXbits |= nset->bits & ~setbits;\n\t\t\telse\n\t\t\t\tbreak;\n\t\t}\n\t\tif (clrbits) {\n\t\t\tset->cmd = '-';\n\t\t\tset->cmd2 = 0;\n\t\t\tset->bits = clrbits;\n\t\t\tset++;\n\t\t}\n\t\tif (setbits) {\n\t\t\tset->cmd = '+';\n\t\t\tset->cmd2 = 0;\n\t\t\tset->bits = setbits;\n\t\t\tset++;\n\t\t}\n\t\tif (Xbits) {\n\t\t\tset->cmd = 'X';\n\t\t\tset->cmd2 = 0;\n\t\t\tset->bits = Xbits;\n\t\t\tset++;\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "lib/libc/gen/siginterrupt.c",
    "content": "/*\n * Copyright (c) 1989, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <signal.h>\n\n/*\n * Set signal state to prevent restart of system calls\n * after an instance of the indicated signal.\n */\nint\nsiginterrupt(sig, flag)\n\tint sig, flag;\n{\n\textern sigset_t _sigintr;\n\tstruct sigaction sa;\n\tint ret;\n\n\tif ((ret = sigaction(sig, (struct sigaction *)0, &sa)) < 0)\n\t\treturn (ret);\n\tif (flag) {\n\t\t(void)sigaddset(&_sigintr, sig);\n\t\tsa.sa_flags &= ~SA_RESTART;\n\t} else {\n\t\t(void)sigdelset(&_sigintr, sig);\n\t\tsa.sa_flags |= SA_RESTART;\n\t}\n\treturn (sigaction(sig, &sa, (struct sigaction *)0));\n}\n"
  },
  {
    "path": "lib/libc/gen/siglist.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <signal.h>\n\nchar\t*sys_siglist[NSIG] = {\n\t\"Signal 0\",\n\t\"Hangup\",\t\t\t/* SIGHUP */\n\t\"Interrupt\",\t\t\t/* SIGINT */\n\t\"Quit\",\t\t\t\t/* SIGQUIT */\n\t\"Illegal instruction\",\t\t/* SIGILL */\n\t\"Trace/BPT trap\",\t\t/* SIGTRAP */\n\t\"IOT trap\",\t\t\t/* SIGIOT */\n\t\"EMT trap\",\t\t\t/* SIGEMT */\n\t\"Floating point exception\",\t/* SIGFPE */\n\t\"Killed\",\t\t\t/* SIGKILL */\n\t\"Bus error\",\t\t\t/* SIGBUS */\n\t\"Segmentation fault\",\t\t/* SIGSEGV */\n\t\"Bad system call\",\t\t/* SIGSYS */\n\t\"Broken pipe\",\t\t\t/* SIGPIPE */\n\t\"Alarm clock\",\t\t\t/* SIGALRM */\n\t\"Terminated\",\t\t\t/* SIGTERM */\n\t\"Urgent I/O condition\",\t\t/* SIGURG */\n\t\"Stopped (signal)\",\t\t/* SIGSTOP */\n\t\"Stopped\",\t\t\t/* SIGTSTP */\n\t\"Continued\",\t\t\t/* SIGCONT */\n\t\"Child exited\",\t\t\t/* SIGCHLD */\n\t\"Stopped (tty input)\",\t\t/* SIGTTIN */\n\t\"Stopped (tty output)\",\t\t/* SIGTTOU */\n\t\"I/O possible\",\t\t\t/* SIGIO */\n\t\"Cputime limit exceeded\",\t/* SIGXCPU */\n\t\"Filesize limit exceeded\",\t/* SIGXFSZ */\n\t\"Virtual timer expired\",\t/* SIGVTALRM */\n\t\"Profiling timer expired\",\t/* SIGPROF */\n\t\"Window size changes\",\t\t/* SIGWINCH */\n\t\"Signal 29\",\n\t\"User defined signal 1\",\t/* SIGUSR1 */\n\t\"User defined signal 2\"\t\t/* SIGUSR2 */\n};\n"
  },
  {
    "path": "lib/libc/gen/signal.c",
    "content": "/*\n * Copyright (c) 1985, 1989, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n/*\n * Almost backwards compatible signal.\n */\n#include <signal.h>\n\nsigset_t _sigintr;\t\t/* shared with siginterrupt */\n\nsig_t\nsignal(s, a)\n\tint s;\n\tsig_t a;\n{\n\tstruct sigaction sa, osa;\n\n\tsa.sa_handler = a;\n\t(void)sigemptyset(&sa.sa_mask);\n\tsa.sa_flags = 0;\n\tif (!sigismember(&_sigintr, s))\n\t\tsa.sa_flags |= SA_RESTART;\n\tif (sigaction(s, &sa, &osa) < 0)\n\t\treturn (SIG_ERR);\n\treturn (osa.sa_handler);\n}\n"
  },
  {
    "path": "lib/libc/gen/sigsetops.c",
    "content": "/*-\n * Copyright (c) 1989, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <signal.h>\n\n#undef sigemptyset\n#undef sigfillset\n#undef sigaddset\n#undef sigdelset\n#undef sigismember\n\nint\nsigemptyset(set)\n\tsigset_t *set;\n{\n\t*set = 0;\n\treturn (0);\n}\n\nint\nsigfillset(set)\n\tsigset_t *set;\n{\n\t*set = ~(sigset_t)0;\n\treturn (0);\n}\n\nint\nsigaddset(set, signo)\n\tsigset_t *set;\n\tint signo;\n{\n\t*set |= sigmask(signo);\n\treturn (0);\n}\n\nint\nsigdelset(set, signo)\n\tsigset_t *set;\n\tint signo;\n{\n\t*set &= ~sigmask(signo);\n\treturn (0);\n}\n\nint\nsigismember(set, signo)\n\tsigset_t *set;\n\tint signo;\n{\n\treturn ((*set & ~sigmask(signo)) != 0);\n}\n"
  },
  {
    "path": "lib/libc/gen/sleep.c",
    "content": "/*\n * Program: sleep.c\n * Copyright: 1997, sms\n * Author: Steven M. Schultz\n *\n * Version   Date\tModification\n *     1.0  1997/9/25\t1. Initial release.\n */\n\n#include <stdio.h>\t/* For NULL */\n#include <sys/types.h>\n#include <sys/time.h>\n#include <unistd.h>\n\n/*\n * This implements the sleep(3) function using only 3 system calls instead of\n * the 9 that the old implementation required.  Also this version avoids using\n * signals (with the attendant system overhead) and returns the amount of\n * time left unslept if an interrupt occurs.\n *\n * The error status of gettimeofday is not checked because if that fails the\n * program has scrambled the stack so badly that a sleep() failure is the least\n * problem the program has.  The select() call either completes successfully\n * or is interrupted - no errors to be checked for.\n */\nu_int\nsleep(seconds)\n\tu_int seconds;\n{\n\tstruct timeval f, s;\n\n\tif (seconds) {\n\t\tgettimeofday(&f, NULL);\n\t\ts.tv_sec = seconds;\n\t\ts.tv_usec = 0;\n\t\tselect(0, NULL, NULL, NULL, &s);\n\t\tgettimeofday(&s, NULL);\n\t\tseconds -= (s.tv_sec - f.tv_sec);\n/*\n * ONLY way this can happen is if the system time gets set back while we're\n * in the select() call.  In this case return 0 instead of a bogus number.\n */\n\t\tif (seconds < 0)\n\t\t\tseconds = 0;\n\t}\n\treturn(seconds);\n}\n"
  },
  {
    "path": "lib/libc/gen/strcasecmp.c",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <strings.h>\n\n/*\n * This array is designed for mapping upper and lower case letter\n * together for a case independent comparison.  The mappings are\n * based upon ascii character sequences.\n */\nstatic char charmap[] = {\n\t'\\000', '\\001', '\\002', '\\003', '\\004', '\\005', '\\006', '\\007',\n\t'\\010', '\\011', '\\012', '\\013', '\\014', '\\015', '\\016', '\\017',\n\t'\\020', '\\021', '\\022', '\\023', '\\024', '\\025', '\\026', '\\027',\n\t'\\030', '\\031', '\\032', '\\033', '\\034', '\\035', '\\036', '\\037',\n\t'\\040', '\\041', '\\042', '\\043', '\\044', '\\045', '\\046', '\\047',\n\t'\\050', '\\051', '\\052', '\\053', '\\054', '\\055', '\\056', '\\057',\n\t'\\060', '\\061', '\\062', '\\063', '\\064', '\\065', '\\066', '\\067',\n\t'\\070', '\\071', '\\072', '\\073', '\\074', '\\075', '\\076', '\\077',\n\t'\\100', '\\141', '\\142', '\\143', '\\144', '\\145', '\\146', '\\147',\n\t'\\150', '\\151', '\\152', '\\153', '\\154', '\\155', '\\156', '\\157',\n\t'\\160', '\\161', '\\162', '\\163', '\\164', '\\165', '\\166', '\\167',\n\t'\\170', '\\171', '\\172', '\\133', '\\134', '\\135', '\\136', '\\137',\n\t'\\140', '\\141', '\\142', '\\143', '\\144', '\\145', '\\146', '\\147',\n\t'\\150', '\\151', '\\152', '\\153', '\\154', '\\155', '\\156', '\\157',\n\t'\\160', '\\161', '\\162', '\\163', '\\164', '\\165', '\\166', '\\167',\n\t'\\170', '\\171', '\\172', '\\173', '\\174', '\\175', '\\176', '\\177',\n\t'\\200', '\\201', '\\202', '\\203', '\\204', '\\205', '\\206', '\\207',\n\t'\\210', '\\211', '\\212', '\\213', '\\214', '\\215', '\\216', '\\217',\n\t'\\220', '\\221', '\\222', '\\223', '\\224', '\\225', '\\226', '\\227',\n\t'\\230', '\\231', '\\232', '\\233', '\\234', '\\235', '\\236', '\\237',\n\t'\\240', '\\241', '\\242', '\\243', '\\244', '\\245', '\\246', '\\247',\n\t'\\250', '\\251', '\\252', '\\253', '\\254', '\\255', '\\256', '\\257',\n\t'\\260', '\\261', '\\262', '\\263', '\\264', '\\265', '\\266', '\\267',\n\t'\\270', '\\271', '\\272', '\\273', '\\274', '\\275', '\\276', '\\277',\n\t'\\300', '\\341', '\\342', '\\343', '\\344', '\\345', '\\346', '\\347',\n\t'\\350', '\\351', '\\352', '\\353', '\\354', '\\355', '\\356', '\\357',\n\t'\\360', '\\361', '\\362', '\\363', '\\364', '\\365', '\\366', '\\367',\n\t'\\370', '\\371', '\\372', '\\333', '\\334', '\\335', '\\336', '\\337',\n\t'\\340', '\\341', '\\342', '\\343', '\\344', '\\345', '\\346', '\\347',\n\t'\\350', '\\351', '\\352', '\\353', '\\354', '\\355', '\\356', '\\357',\n\t'\\360', '\\361', '\\362', '\\363', '\\364', '\\365', '\\366', '\\367',\n\t'\\370', '\\371', '\\372', '\\373', '\\374', '\\375', '\\376', '\\377',\n};\n\nint\nstrcasecmp(s1, s2)\n\tregister const char *s1, *s2;\n{\n\tregister char *cm = charmap;\n\n\twhile (cm[(unsigned char)*s1] == cm[(unsigned char)*s2++])\n\t\tif (*s1++ == '\\0')\n\t\t\treturn(0);\n\treturn(cm[(unsigned char)*s1] - cm[(unsigned char)*--s2]);\n}\n\nint\nstrncasecmp(s1, s2, n)\n\tregister const char *s1, *s2;\n\tregister size_t n;\n{\n\tregister char *cm = charmap;\n\n\twhile (n-- > 0 && cm[(unsigned char)*s1] == cm[(unsigned char)*s2++])\n\t\tif (*s1++ == '\\0')\n\t\t\treturn(0);\n\treturn(n == -1 ? 0 : cm[(unsigned char)*s1] - cm[(unsigned char)*--s2]);\n}\n"
  },
  {
    "path": "lib/libc/gen/strcat.c",
    "content": "/*\n * Concatenate s2 on the end of s1.  S1's space must be large enough.\n * Return s1.\n */\n#include <string.h>\n\nchar *\nstrcat(s1, s2)\n\tregister char *s1;\n\tregister const char *s2;\n{\n\tregister char *os1;\n\n\tos1 = s1;\n\twhile (*s1++)\n\t\t;\n\t--s1;\n\twhile ((*s1++ = *s2++))\n\t\t;\n\treturn(os1);\n}\n"
  },
  {
    "path": "lib/libc/gen/strcmp.c",
    "content": "/*\n * Compare strings:  s1>s2: >0  s1==s2: 0  s1<s2: <0\n */\n#include <string.h>\n\nint\nstrcmp(s1, s2)\n\tregister const char *s1, *s2;\n{\n\n\twhile (*s1 == *s2++)\n\t\tif (*s1++=='\\0')\n\t\t\treturn(0);\n\treturn(*s1 - *--s2);\n}\n"
  },
  {
    "path": "lib/libc/gen/strcpy.c",
    "content": "/*\n * Copy string s2 to s1.  s1 must be large enough.\n * return s1\n */\n#include <string.h>\n\nchar *\nstrcpy(s1, s2)\n\tregister char *s1;\n\tregister const char *s2;\n{\n\tregister char *os1;\n\n\tos1 = s1;\n\twhile ((*s1++ = *s2++))\n\t\t;\n\treturn(os1);\n}\n"
  },
  {
    "path": "lib/libc/gen/strdup.c",
    "content": "/*\n * Copyright (c) 1988 The Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that the above copyright notice and this paragraph are\n * duplicated in all such forms and that any documentation,\n * advertising materials, and other materials related to such\n * distribution and use acknowledge that the software was developed\n * by the University of California, Berkeley.  The name of the\n * University may not be used to endorse or promote products derived\n * from this software without specific prior written permission.\n * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n */\n#include <sys/types.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <strings.h>\n\nchar *\nstrdup(str)\n\tconst char *str;\n{\n\tint len;\n\tchar *copy;\n\n\tlen = strlen(str) + 1;\n\tif (!(copy = malloc((u_int)len)))\n\t\treturn((char *)NULL);\n\tbcopy(str, copy, len);\n\treturn(copy);\n}\n"
  },
  {
    "path": "lib/libc/gen/strftime.c",
    "content": "/*\n * Copyright (c) 1989, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/types.h>\n#include <time.h>\n#include <tzfile.h>\n#include <string.h>\n#include <strings.h>\n\nstatic char *Afmt[] = {\n\t\"Sunday\", \"Monday\", \"Tuesday\", \"Wednesday\", \"Thursday\", \"Friday\",\n\t\"Saturday\",\n};\nstatic char *Bfmt[] = {\n\t\"January\", \"February\", \"March\", \"April\", \"May\", \"June\", \"July\",\n\t\"August\", \"September\", \"October\", \"November\", \"December\",\n};\n\nstatic size_t gsize;\nstatic char *pt;\n\nstatic int\n_add(char *str)\n{\n\tfor (;; ++pt, --gsize) {\n\t\tif (!gsize)\n\t\t\treturn(0);\n\t\tif (!(*pt = *str++))\n\t\t\treturn(1);\n\t}\n}\n\nstatic int\n_conv(int n, int digits, char pad)\n{\n\tstatic char buf[10];\n\tregister char *p;\n\n\tfor (p = buf + sizeof(buf) - 2; n > 0 && p > buf; n /= 10, --digits)\n\t\t*p-- = n % 10 + '0';\n\twhile (p > buf && digits-- > 0)\n\t\t*p-- = pad;\n\treturn(_add(++p));\n}\n\nstatic size_t\n_fmt(const char *format, const struct tm *t)\n{\n\tchar\tch, *cp, junk[4];\n\n\tfor (; *format; ++format) {\n\t\tif (*format == '%')\n\t\t\tswitch(ch = *++format) {\n\t\t\tcase '\\0':\n\t\t\t\t--format;\n\t\t\t\tbreak;\n\t\t\tcase 'A':\n\t\t\tcase 'a':\n\t\t\t\tif (t->tm_wday < 0 || t->tm_wday > 6)\n\t\t\t\t\treturn(0);\n\t\t\t\tif\t(ch == 'a')\n\t\t\t\t\t{\n\t\t\t\t\tbcopy(Afmt[t->tm_wday], junk, 3);\n\t\t\t\t\tjunk[3] = '\\0';\n\t\t\t\t\tcp = junk;\n\t\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t\tcp = Afmt[t->tm_wday];\n\t\t\t\tif (!_add(cp))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'B':\n\t\t\tcase 'b':\n\t\t\tcase 'h':\n\t\t\t\tif (t->tm_mon < 0 || t->tm_mon > 11)\n\t\t\t\t\treturn(0);\n\t\t\t\tif\t(ch == 'b')\n\t\t\t\t\t{\n\t\t\t\t\tbcopy(Bfmt[t->tm_mon], junk, 3);\n\t\t\t\t\tjunk[3] = '\\0';\n\t\t\t\t\tcp = junk;\n\t\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t\tcp = Bfmt[t->tm_mon];\n\t\t\t\tif (!_add(cp))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'C':\n\t\t\t\tif (!_fmt(\"%a %b %e %H:%M:%S %Y\", t))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'c':\n\t\t\t\tif (!_fmt(\"%m/%d/%y %H:%M:%S\", t))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'D':\n\t\t\t\tif (!_fmt(\"%m/%d/%y\", t))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'd':\n\t\t\t\tif (!_conv(t->tm_mday, 2, '0'))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'e':\n\t\t\t\tif (!_conv(t->tm_mday, 2, ' '))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'H':\n\t\t\t\tif (!_conv(t->tm_hour, 2, '0'))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'I':\n\t\t\t\tif (!_conv(t->tm_hour % 12 ?\n\t\t\t\t    t->tm_hour % 12 : 12, 2, '0'))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'j':\n\t\t\t\tif (!_conv(t->tm_yday + 1, 3, '0'))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'k':\n\t\t\t\tif (!_conv(t->tm_hour, 2, ' '))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'l':\n\t\t\t\tif (!_conv(t->tm_hour % 12 ?\n\t\t\t\t    t->tm_hour % 12 : 12, 2, ' '))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'M':\n\t\t\t\tif (!_conv(t->tm_min, 2, '0'))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'm':\n\t\t\t\tif (!_conv(t->tm_mon + 1, 2, '0'))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'n':\n\t\t\t\tif (!_add(\"\\n\"))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'p':\n\t\t\t\tif (!_add(t->tm_hour >= 12 ? \"PM\" : \"AM\"))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'R':\n\t\t\t\tif (!_fmt(\"%H:%M\", t))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'r':\n\t\t\t\tif (!_fmt(\"%I:%M:%S %p\", t))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'S':\n\t\t\t\tif (!_conv(t->tm_sec, 2, '0'))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'T':\n\t\t\tcase 'X':\n\t\t\t\tif (!_fmt(\"%H:%M:%S\", t))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 't':\n\t\t\t\tif (!_add(\"\\t\"))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'U':\n\t\t\t\tif (!_conv((t->tm_yday + 7 - t->tm_wday) / 7,\n\t\t\t\t    2, '0'))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'W':\n\t\t\t\tif (!_conv((t->tm_yday + 7 -\n\t\t\t\t    (t->tm_wday ? (t->tm_wday - 1) : 6))\n\t\t\t\t    / 7, 2, '0'))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'w':\n\t\t\t\tif (!_conv(t->tm_wday, 1, '0'))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'x':\n\t\t\t\tif (!_fmt(\"%m/%d/%y\", t))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'y':\n\t\t\t\tif (!_conv((t->tm_year + TM_YEAR_BASE)\n\t\t\t\t    % 100, 2, '0'))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'Y':\n\t\t\t\tif (!_conv(t->tm_year + TM_YEAR_BASE, 4, '0'))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase 'Z':\n\t\t\t\tif (!t->tm_zone || !_add(t->tm_zone))\n\t\t\t\t\treturn(0);\n\t\t\t\tcontinue;\n\t\t\tcase '%':\n\t\t\t/*\n\t\t\t * X311J/88-090 (4.12.3.5): if conversion char is\n\t\t\t * undefined, behavior is undefined.  Print out the\n\t\t\t * character itself as printf(3) does.\n\t\t\t */\n\t\t\tdefault:\n\t\t\t\tbreak;\n\t\t}\n\t\tif (!gsize--)\n\t\t\treturn(0);\n\t\t*pt++ = *format;\n\t}\n\treturn(gsize);\n}\n\nsize_t\nstrftime(char *s, size_t maxsize, const char *format, const struct tm *t)\n{\n\n\tpt = s;\n\tif ((gsize = maxsize) < 1)\n\t\treturn(0);\n\tif (_fmt(format, t)) {\n\t\t*pt = '\\0';\n\t\treturn(maxsize - gsize);\n\t}\n\treturn(0);\n}\n"
  },
  {
    "path": "lib/libc/gen/strlen.c",
    "content": "/*\n * Returns the number of\n * non-NULL bytes in string argument.\n */\n#include <string.h>\n\nsize_t\nstrlen(s)\n\tregister const char *s;\n{\n\tregister int n;\n\n\tn = 0;\n\twhile (*s++)\n\t\tn++;\n\treturn(n);\n}\n"
  },
  {
    "path": "lib/libc/gen/strncat.c",
    "content": "/*\n * Concatenate s2 on the end of s1.  S1's space must be large enough.\n * At most n characters are moved.\n * Return s1.\n */\n#include <string.h>\n\nchar *\nstrncat(s1, s2, n)\n\tregister char *s1;\n\tregister const char *s2;\n\tregister size_t n;\n{\n\tregister char *os1;\n\n\tos1 = s1;\n\twhile (*s1++)\n\t\t;\n\t--s1;\n\twhile ((*s1++ = *s2++))\n\t\tif (n-- == 0) {\n\t\t\t*--s1 = '\\0';\n\t\t\tbreak;\n\t\t}\n\treturn(os1);\n}\n"
  },
  {
    "path": "lib/libc/gen/strncmp.c",
    "content": "/*\n * Compare strings (at most n bytes):  s1>s2: >0  s1==s2: 0  s1<s2: <0\n */\n#include <string.h>\n\nint\nstrncmp (s1, s2, n)\n\tregister const char *s1, *s2;\n\tregister size_t n;\n{\n        for (;;) {\n                if (n-- == 0)\n                        return 0;\n                if (*s1 != *s2++)\n                        return *s1 - *--s2;\n\t\tif (*s1++ == '\\0')\n\t\t\treturn 0;\n        }\n}\n"
  },
  {
    "path": "lib/libc/gen/strncpy.c",
    "content": "/*\n * Copy s2 to s1, truncating or null-padding to always copy n bytes\n * return s1\n */\n#include <string.h>\n\nchar *\nstrncpy(s1, s2, n)\n\tregister char *s1;\n\tregister const char *s2;\n\tsize_t n;\n{\n\tsize_t i;\n\tregister char *os1;\n\n\tos1 = s1;\n\tfor (i = 0; i < n; i++)\n\t\tif ((*s1++ = *s2++) == '\\0') {\n\t\t\twhile (++i < n)\n\t\t\t\t*s1++ = '\\0';\n\t\t\treturn(os1);\n\t\t}\n\treturn(os1);\n}\n"
  },
  {
    "path": "lib/libc/gen/swab.c",
    "content": "/*\n * Swab bytes\n * Jeffrey Mogul, Stanford\n */\nvoid\nswab (from, to, n)\n\tregister char *from, *to;\n\tregister int n;\n{\n#ifdef pdp11\n\tregister int temp;\n#else\n\tregister unsigned long temp;\n#endif\n\n\tn >>= 1; n++;\n#define\tSTEP\ttemp = *from++,*to++ = *from++,*to++ = temp\n\t/* round to multiple of 8 */\n\twhile ((--n) & 07)\n\t\tSTEP;\n\tn >>= 3;\n\twhile (--n >= 0) {\n\t\tSTEP; STEP; STEP; STEP;\n\t\tSTEP; STEP; STEP; STEP;\n\t}\n}\n"
  },
  {
    "path": "lib/libc/gen/sysctl.c",
    "content": "/*-\n * Copyright (c) 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/param.h>\n#include <sys/sysctl.h>\n#include <errno.h>\n#include <string.h>\n#include <paths.h>\n\nint\nsysctl(name, namelen, oldp, oldlenp, newp, newlen)\n\tint *name;\n\tu_int namelen;\n\tvoid *oldp, *newp;\n\tsize_t *oldlenp, newlen;\n{\n\tif (name[0] != CTL_USER)\n\t\treturn (__sysctl(name, namelen, oldp, oldlenp, newp, newlen));\n\n\tif (newp != NULL) {\n\t\terrno = EPERM;\n\t\treturn (-1);\n\t}\n\tif (namelen != 2) {\n\t\terrno = EINVAL;\n\t\treturn (-1);\n\t}\n\n/*\n * This idea behind this section is silly.  Other than 'bc' who cares about\n * half of these?  A 3/4 hearted attempt is made however to return numbers\n * that are not totally bogus.\n *\n * Rather than port over the raft of include files with the attendant plethora\n * of #define statements we just plug in the numbers from 4.4-Lite.\n */\n\n\tswitch (name[1]) {\n\tcase USER_CS_PATH:\n\t\tif (oldp && *oldlenp < sizeof(_PATH_SYSPATH))\n\t\t\treturn (ENOMEM);\n\t\t*oldlenp = sizeof(_PATH_SYSPATH);\n\t\tif (oldp != NULL)\n\t\t\tstrcpy(oldp, _PATH_SYSPATH);\n\t\treturn (0);\n\t}\n\n\tif (oldp && *oldlenp < sizeof(int))\n\t\treturn (ENOMEM);\n\t*oldlenp = sizeof(int);\n\tif (oldp == NULL)\n\t\treturn (0);\n\n\tswitch (name[1]) {\n\tcase USER_BC_BASE_MAX:\n\tcase USER_BC_SCALE_MAX:\n\t\t*(int *)oldp = 99;\n\t\treturn (0);\n\tcase USER_BC_DIM_MAX:\n\t\t*(int *)oldp = 2048;\n\t\treturn (0);\n\tcase USER_BC_STRING_MAX:\n\t\t*(int *)oldp = 1000;\n\t\treturn (0);\n\tcase USER_EXPR_NEST_MAX:\n\t\t*(int *)oldp = 32;\n\t\treturn (0);\n\tcase USER_LINE_MAX:\n\t\t*(int *)oldp = 1024;\n\t\treturn (0);\n\tcase USER_RE_DUP_MAX:\n\t\t*(int *)oldp = 255;\n\t\treturn (0);\n\tcase USER_COLL_WEIGHTS_MAX:\n\tcase USER_POSIX2_VERSION:\n\tcase USER_POSIX2_C_BIND:\n\tcase USER_POSIX2_C_DEV:\n\tcase USER_POSIX2_CHAR_TERM:\n\tcase USER_POSIX2_FORT_DEV:\n\tcase USER_POSIX2_FORT_RUN:\n\tcase USER_POSIX2_LOCALEDEF:\n\tcase USER_POSIX2_SW_DEV:\n\tcase USER_POSIX2_UPE:\n\t\t*(int *)oldp = 0;\n\t\treturn (0);\n\tcase USER_STREAM_MAX:\n\t\t*(int *)oldp = 20;\n\t\treturn (0);\n\tcase USER_TZNAME_MAX:\n\t\t*(int *)oldp = 63;\n\t\treturn (0);\n\tdefault:\n\t\terrno = EINVAL;\n\t\treturn (-1);\n\t}\n\t/* NOTREACHED */\n}\n"
  },
  {
    "path": "lib/libc/gen/syslog.c",
    "content": "/*\n * Copyright (c) 1983, 1988, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/types.h>\n#include <syslog.h>\n#include <sys/uio.h>\n#include <sys/wait.h>\n\n#include <errno.h>\n#include <fcntl.h>\n#include <paths.h>\n#include <stdio.h>\n#include <string.h>\n#include <strings.h>\n#include <unistd.h>\n#include <time.h>\n#include <stdarg.h>\n\n#define\tSTDERR_FILENO\t2\n\nstatic\tint\tLogFile = -1;\t\t/* fd for log */\nstatic\tint\tconnected;\t\t/* have done connect */\nstatic\tint\tLogStat = 0;\t\t/* status bits, set by openlog() */\nstatic\tconst char *LogTag = NULL;\t/* string to tag the entry with */\nstatic\tint\tLogFacility = LOG_USER;\t/* default facility code */\nstatic\tint\tLogMask = 0xff;\t\t/* mask of priorities to be logged */\nstatic\tchar\tlogfile[] = _PATH_MESSAGES;\n\nextern\tint\terrno;\t\t\t/* error number */\n\n/*\n * syslog, vsyslog --\n *\tprint message on log file; output is intended for syslogd(8).\n *\tNo sockets: logfile is used.\n */\nvoid\nvsyslog(pri, fmt, ap)\n\tint pri;\n\tregister const char *fmt;\n\tva_list ap;\n{\n\tint cnt;\n\tchar ch;\n\tregister char *p, *t;\n\ttime_t now;\n\tint fd, saved_errno;\n\tchar *stdp = 0, tbuf[640], fmt_cpy[512];\n\tpid_t\tpid;\n\n#define\tINTERNALLOG\tLOG_ERR|LOG_CONS|LOG_PERROR|LOG_PID\n\t/* Check for invalid bits. */\n\tif (pri & ~(LOG_PRIMASK|LOG_FACMASK)) {\n\t\tsyslog(INTERNALLOG,\n\t\t    \"syslog: bad fac/pri: %x\", pri);\n\t\tpri &= LOG_PRIMASK|LOG_FACMASK;\n\t}\n\n\t/* Check priority against setlogmask values. */\n\tif (!(LOG_MASK(LOG_PRI(pri)) & LogMask))\n\t\treturn;\n\n\tsaved_errno = errno;\n\n\t/* Set default facility if none specified. */\n\tif ((pri & LOG_FACMASK) == 0)\n\t\tpri |= LogFacility;\n\n\t/* Build the message. */\n\t(void)time(&now);\n\tp = tbuf + sprintf(tbuf, \"<%d>\", pri);\n\tp += strftime(p, sizeof (tbuf) - (p - tbuf), \"%h %e %T \",\n\t    localtime(&now));\n\tif (LogStat & LOG_PERROR)\n\t\tstdp = p;\n\tif (LogTag == NULL)\n\t\tLogTag = __progname;\n\tif (LogTag != NULL)\n\t\tp += sprintf(p, \"%s\", LogTag);\n\tif (LogStat & LOG_PID)\n\t\tp += sprintf(p, \"[%d]\", getpid());\n\tif (LogTag != NULL) {\n\t\t*p++ = ':';\n\t\t*p++ = ' ';\n\t}\n\n\t/* Substitute error message for %m. */\n\tfor (t = fmt_cpy; (ch = *fmt); ++fmt)\n\t\tif (ch == '%' && fmt[1] == 'm') {\n\t\t\t++fmt;\n\t\t\tt += sprintf(t, \"%s\", strerror(saved_errno));\n\t\t} else\n\t\t\t*t++ = ch;\n\t*t = '\\0';\n\n\tp += vsprintf(p, fmt_cpy, ap);\n\tcnt = p - tbuf;\n\n\t/* Output to stderr if requested. */\n\tif (LogStat & LOG_PERROR) {\n\t\tstruct iovec iov[2];\n\t\tregister struct iovec *v = iov;\n\n\t\tv->iov_base = stdp;\n\t\tv->iov_len = cnt - (stdp - tbuf);\n\t\t++v;\n\t\tv->iov_base = \"\\n\";\n\t\tv->iov_len = 1;\n\t\t(void)writev(STDERR_FILENO, iov, 2);\n\t}\n\n\t/* Get connected, output the message to the local logger. */\n\tif (!connected)\n\t\topenlog(LogTag, LogStat | LOG_NDELAY, 0);\n        (void)strcat(tbuf, \"\\r\\n\");\n        cnt += 2;\n\tif (write(LogFile, tbuf, cnt) == cnt)\n\t\treturn;\n\n\t/*\n\t * Output the message to the console; don't worry about blocking,\n\t * if console blocks everything will.  Make sure the error reported\n\t * is the one from the syslogd failure.\n\t *\n\t * 2.11BSD has to do a more complicated dance because we do not\n\t * want to acquire a controlling terminal (bad news for 'init'!).\n\t * Until either the tty driver is ported from 4.4 or O_NOCTTY\n\t * is implemented we have to fork and let the child do the open of\n\t * the console.\n\t */\n\tif (LogStat & LOG_CONS) {\n\t\tpid = vfork();\n\t\tif (pid == -1)\n\t\t\treturn;\n\t\tif (pid == 0) {\n\t   \t\tfd = open(_PATH_CONSOLE, O_WRONLY, 0);\n\t\t\tp = index(tbuf, '>') + 1;\n\t\t\t(void)write(fd, p, cnt - (p - tbuf));\n\t\t\t(void)close(fd);\n\t\t\t_exit(0);\n\t\t}\n\t\twhile (waitpid(pid, NULL, NULL) == -1 && (errno == EINTR))\n\t\t\t;\n\t}\n}\n\nvoid\nsyslog (int pri, const char *fmt, ...)\n{\n\tva_list ap;\n\n\tva_start (ap, fmt);\n\tvsyslog (pri, fmt, ap);\n\tva_end (ap);\n}\n\nvoid\nopenlog(ident, logstat, logfac)\n\tconst char *ident;\n\tint logstat;\n\tregister int logfac;\n{\n\tif (ident != NULL)\n\t\tLogTag = ident;\n\tLogStat = logstat;\n\tif (logfac != 0 && (logfac &~ LOG_FACMASK) == 0)\n\t\tLogFacility = logfac;\n\n\tif (LogFile == -1) {\n\t\tif (LogStat & LOG_NDELAY) {\n\t\t\tLogFile = open(logfile, O_WRONLY|O_APPEND);\n\t\t\tconnected = 1;\n\t\t\tif (LogFile == -1)\n\t\t\t\treturn;\n\t\t\t(void)fcntl(LogFile, F_SETFD, 1);\n\t\t}\n\t}\n\tif (LogFile != -1 && !connected) {\n\t\t(void)close(LogFile);\n\t\tLogFile = -1;\n\t}\n}\n\nvoid\ncloselog()\n{\n\t(void)close(LogFile);\n\tLogFile = -1;\n\tconnected = 0;\n}\n\n/* setlogmask -- set the log mask level */\nint\nsetlogmask(pmask)\n\tregister int pmask;\n{\n\tregister int omask;\n\n\tomask = LogMask;\n\tif (pmask != 0)\n\t\tLogMask = pmask;\n\treturn (omask);\n}\n"
  },
  {
    "path": "lib/libc/gen/system.c",
    "content": "/*\n * Copyright (c) 1988 The Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <stdio.h>\n#include <sys/types.h>\n#include <sys/signal.h>\n#include <sys/wait.h>\n#include <unistd.h>\n\nint\nsystem(command)\n\tchar *command;\n{\n\tunion wait pstat;\n\tregister int pid;\n\tsigset_t omask, nmask;\n\tsig_t intsave, quitsave;\n\n\tif (!command)\t\t/* just checking... */\n\t\treturn(1);\n\n\t(void)sigemptyset(&nmask);\n\t(void)sigaddset(&nmask, SIGCHLD);\n\t(void)sigprocmask(SIG_BLOCK, &nmask, &omask);\n\tswitch(pid = vfork()) {\n\tcase -1:\t\t\t/* error */\n\t\t(void)sigprocmask(SIG_SETMASK, &omask, NULL);\n\t\tpstat.w_status = 0;\n\t\tpstat.w_retcode = 127;\n\t\treturn(pstat.w_status);\n\tcase 0:\t\t\t\t/* child */\n\t\t(void)sigprocmask(SIG_SETMASK, &omask, NULL);\n\t\texecl(\"/bin/sh\", \"sh\", \"-c\", command, (char *)NULL);\n\t\t_exit(127);\n\t}\n\tintsave = signal(SIGINT, SIG_IGN);\n\tquitsave = signal(SIGQUIT, SIG_IGN);\n\tpid = waitpid(pid, (int *)&pstat, 0);\n\t(void)sigprocmask(SIG_SETMASK, &omask, NULL);\n\t(void)signal(SIGINT, intsave);\n\t(void)signal(SIGQUIT, quitsave);\n\treturn(pid == -1 ? -1 : pstat.w_status);\n}\n"
  },
  {
    "path": "lib/libc/gen/telldir.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/dir.h>\n\n/*\n * return a pointer into a directory\n */\nlong\ntelldir(dirp)\n\tDIR *dirp;\n{\n\textern long lseek();\n\n\treturn (lseek(dirp->dd_fd, 0L, 1) - dirp->dd_size + dirp->dd_loc);\n}\n"
  },
  {
    "path": "lib/libc/gen/time.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * Backwards compatible time call.\n */\n#include <sys/types.h>\n#include <sys/time.h>\n\nlong\ntime(t)\n\ttime_t *t;\n{\n\tstruct timeval tt;\n\n\tif (gettimeofday(&tt, (struct timezone *)0) < 0)\n\t\treturn (-1);\n\tif (t)\n\t\t*t = tt.tv_sec;\n\treturn (tt.tv_sec);\n}\n"
  },
  {
    "path": "lib/libc/gen/timezone.c",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * This file may be freely redistributed provided that this\n * notice remains attached.\n */\n#include <string.h>\n#include <stdlib.h>\n#include <sys/types.h>\n#include <sys/time.h>\n#include <stdio.h>\n#include <strings.h>\n#include <tzfile.h>\n\n/*\n * timezone --\n *\tThe arguments are the number of minutes of time you are westward\n *\tfrom Greenwich and whether DST is in effect.  It returns a string\n *\tgiving the name of the local timezone.  Should be replaced, in the\n *\tapplication code, by a call to localtime.\n */\n\nstatic char\tczone[TZ_MAX_CHARS];\t\t/* space for zone name */\n\nchar *\ntimezone(zone, dst)\n\tint\tzone,\n\t\tdst;\n{\n\tregister char\t*beg,\n\t\t\t*end;\n\n        beg = getenv(\"TZNAME\");\n\tif (beg) {                              /* set in environment */\n\t        end = index(beg, ',');\n\t\tif (end) {                      /* \"PST,PDT\" */\n\t\t\tif (dst)\n\t\t\t\treturn(++end);\n\t\t\t*end = '\\0';\n\t\t\t(void)strncpy(czone,beg,sizeof(czone) - 1);\n\t\t\tczone[sizeof(czone) - 1] = '\\0';\n\t\t\t*end = ',';\n\t\t\treturn(czone);\n\t\t}\n\t\treturn(beg);\n\t}\n\treturn(tztab(zone,dst));\t/* default: table or created zone */\n}\n\nstatic struct zone {\n\tint\toffset;\n\tchar\t*stdzone;\n\tchar\t*dlzone;\n} zonetab[] = {\n\t{ -1*60,\t\"MET\",\t\"MET DST\"   },\t/* Middle European */\n\t{ -2*60,\t\"EET\",\t\"EET DST\"   },\t/* Eastern European */\n\t{ 4*60,         \"AST\",\t\"ADT\"       },\t/* Atlantic */\n\t{ 5*60,         \"EST\",\t\"EDT\"       },\t/* Eastern */\n\t{ 6*60,         \"CST\",\t\"CDT\"       },\t/* Central */\n\t{ 7*60,         \"MST\",\t\"MDT\"       },\t/* Mountain */\n\t{ 8*60,         \"PST\",\t\"PDT\"       },\t/* Pacific */\n\t{ 0,            \"GMT\",\t0           },\t/* Greenwich */\n\t{ -10*60,\t\"EST\",\t\"EST\"       },\t/* Aust: Eastern */\n        { -10*60+30,\t\"CST\",\t\"CST\"       },\t/* Aust: Central */\n\t{ -8*60,\t\"WST\",\t0           },\t/* Aust: Western */\n\t{ -1 },\n};\n\n/*\n * tztab --\n *\tcheck static tables or create a new zone name; broken out so that\n *\twe can make a guess as to what the zone is if the standard tables\n *\taren't in place in /usr/share/misc.  DO NOT USE THIS ROUTINE OUTSIDE\n *\tOF THE STANDARD LIBRARY.\n */\nchar *\ntztab(zone,dst)\n\tregister int\tzone;\n\tint\tdst;\n{\n\tregister struct zone\t*zp;\n\tregister char\tsign;\n\n\tfor (zp = zonetab; zp->offset != -1;++zp)\t/* static tables */\n\t\tif (zp->offset == zone) {\n\t\t\tif (dst && zp->dlzone)\n\t\t\t\treturn(zp->dlzone);\n\t\t\tif (!dst && zp->stdzone)\n\t\t\t\treturn(zp->stdzone);\n\t\t}\n\n\tif (zone < 0) {\t\t\t\t\t/* create one */\n\t\tzone = -zone;\n\t\tsign = '+';\n\t}\n\telse\n\t\tsign = '-';\n\t(void)sprintf(czone,\"GMT%c%d:%02d\",sign,zone / 60,zone % 60);\n\treturn(czone);\n}\n"
  },
  {
    "path": "lib/libc/gen/ttyname.c",
    "content": "/*\n * ttyname(f): return \"/dev/ttyXX\" which the the name of the\n * tty belonging to file f.\n *  NULL if it is not a tty\n */\n#include <sys/param.h>\n#include <sys/dir.h>\n#include <sys/stat.h>\n#include <string.h>\n#include <unistd.h>\n\nstatic\tchar\tdev[]\t= \"/dev/\";\n\nchar *\nttyname(f)\n\tint f;\n{\n\tstruct stat fsb;\n\tstruct stat tsb;\n\tregister struct direct *db;\n\tregister DIR *df;\n\tstatic char rbuf[32];\n\n\tif (isatty(f)==0)\n\t\treturn 0;\n\tif (fstat(f, &fsb) < 0)\n\t\treturn 0;\n\tif ((fsb.st_mode&S_IFMT) != S_IFCHR)\n\t\treturn 0;\n        df = opendir(dev);\n\tif (! df)\n\t\treturn 0;\n\twhile ((db = readdir(df))) {\n\t\tif (db->d_ino != fsb.st_ino)\n\t\t\tcontinue;\n\t\tstrcpy(rbuf, dev);\n\t\tstrcat(rbuf, db->d_name);\n\t\tif (stat(rbuf, &tsb) < 0)\n\t\t\tcontinue;\n\t\tif (tsb.st_dev == fsb.st_dev && tsb.st_ino == fsb.st_ino) {\n\t\t\tclosedir(df);\n\t\t\treturn(rbuf);\n\t\t}\n\t}\n\tclosedir(df);\n\treturn 0;\n}\n"
  },
  {
    "path": "lib/libc/gen/ttyslot.c",
    "content": "/*\n * Copyright (c) 1984 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * Return the number of the slot in the utmp file\n * corresponding to the current user: try for file 0, 1, 2.\n * Definition is the line number in the /etc/ttys file.\n */\n#include <ttyent.h>\n#include <string.h>\n#include <unistd.h>\n\nint\nttyslot()\n{\n\tregister struct ttyent *ty;\n\tregister char *tp, *p;\n\tregister int s;\n\n\tif (! (tp = ttyname(0)) &&\n\t    ! (tp = ttyname(1)) &&\n\t    ! (tp = ttyname(2)))\n\t\treturn 0;\n        p = strrchr(tp, '/');\n\tif (! p)\n\t\tp = tp;\n\telse\n\t\tp++;\n\tsetttyent();\n\ts = 0;\n\twhile ((ty = getttyent())) {\n\t\ts++;\n\t\tif (strcmp(ty->ty_name, p) == 0) {\n\t\t\tendttyent();\n\t\t\treturn s;\n\t\t}\n\t}\n\tendttyent();\n\treturn 0;\n}\n"
  },
  {
    "path": "lib/libc/gen/ualarm.c",
    "content": "/*\n * Copyright (c) 1985 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/time.h>\n\n#define\tUSPS\t1000000\t\t/* # of microseconds in a second */\n\n/*\n * Generate a SIGALRM signal in ``usecs'' microseconds.\n * If ``reload'' is non-zero, keep generating SIGALRM\n * every ``reload'' microseconds after the first signal.\n */\nunsigned\nualarm(usecs, reload)\n\tregister unsigned usecs;\n\tregister unsigned reload;\n{\n\tstruct itimerval new, old;\n\n\tnew.it_interval.tv_usec = reload % USPS;\n\tnew.it_interval.tv_sec = reload / USPS;\n\n\tnew.it_value.tv_usec = usecs % USPS;\n\tnew.it_value.tv_sec = usecs / USPS;\n\n\tif (setitimer(ITIMER_REAL, &new, &old) == 0)\n\t\treturn (old.it_value.tv_sec * USPS + old.it_value.tv_usec);\n\t/* else */\n\t\treturn (-1);\n}\n"
  },
  {
    "path": "lib/libc/gen/uname.c",
    "content": "/*-\n * Copyright (c) 1994\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n#include <sys/param.h>\n#include <sys/sysctl.h>\n#include <sys/utsname.h>\n\nint\nuname(struct utsname *name)\n{\n\tint mib[2], rval;\n\tsize_t len;\n\tchar *p;\n\n\trval = 0;\n\n\tmib[0] = CTL_KERN;\n\tmib[1] = KERN_OSTYPE;\n\tlen = sizeof(name->sysname);\n\tif (sysctl(mib, 2, &name->sysname, &len, NULL, 0) == -1)\n\t\trval = -1;\n\n\tmib[0] = CTL_KERN;\n\tmib[1] = KERN_HOSTNAME;\n\tlen = sizeof(name->nodename);\n\tif (sysctl(mib, 2, &name->nodename, &len, NULL, 0) == -1)\n\t\trval = -1;\n\n\tmib[0] = CTL_KERN;\n\tmib[1] = KERN_OSRELEASE;\n\tlen = sizeof(name->release);\n\tif (sysctl(mib, 2, &name->release, &len, NULL, 0) == -1)\n\t\trval = -1;\n\n\tmib[0] = CTL_KERN;\n\tmib[1] = KERN_OSVERSION;\n\tlen = sizeof(name->version);\n\tif (sysctl(mib, 2, &name->version, &len, NULL, 0) == -1) {\n\t\t/* Fall back to old behaviour. */\n\t\tmib[0] = CTL_KERN;\n\t\tmib[1] = KERN_VERSION;\n\t\tlen = sizeof(name->version);\n\t\tif (sysctl(mib, 2, &name->version, &len, NULL, 0) == -1)\n\t\t\trval = -1;\n\n\t\t/* If version has newlines in it, turn them into spaces. */\n\t\tfor (p = name->version; len--; ++p) {\n\t\t\tif (*p == '\\n' || *p == '\\t') {\n\t\t\t\tif (len > 1)\n\t\t\t\t\t*p = ' ';\n\t\t\t\telse\n\t\t\t\t\t*p = '\\0';\n\t\t\t}\n\t\t}\n\t}\n\n\tmib[0] = CTL_HW;\n\tmib[1] = HW_MACHINE;\n\tlen = sizeof(name->machine);\n\tif (sysctl(mib, 2, &name->machine, &len, NULL, 0) == -1)\n\t\trval = -1;\n\treturn (rval);\n}\n"
  },
  {
    "path": "lib/libc/gen/usleep.c",
    "content": "/*\n * Program: sleep.c\n * Copyright: 1997, sms\n * Author: Steven M. Schultz\n *\n * Version   Date\tModification\n *     1.0  1997/9/26\t1. Initial release.\n */\n#include <stdio.h>\t/* For NULL */\n#include <sys/types.h>\n#include <sys/time.h>\n\n/*\n * This implements the usleep(3) function using only 1 system call (select)\n * instead of the 9 that the old implementation required.  Also this version\n * avoids using signals (with the attendant system overhead).\n *\n * Nothing is returned and if less than ~20000 microseconds is specified the\n * select will return without any delay at all.\n */\nvoid\nusleep(micros)\n\tlong micros;\n{\n\tstruct timeval s;\n\n\tif (micros > 0) {\n\t\ts.tv_sec = micros / 1000000L;\n\t\ts.tv_usec = micros % 1000000L;\n\t\tselect(0, NULL, NULL, NULL, &s);\n\t}\n}\n"
  },
  {
    "path": "lib/libc/gen/valloc.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <stdlib.h>\n\nchar *\nvalloc(i)\n\tint i;\n{\n#ifdef pdp11\n\t/*\n\t * page boudaries don't mean anything on a PDP-11 and the cost in\n\t * memory is just too prohibitive to blindly use the non-PDP-11\n\t * algorithm.\n\t */\n\treturn(malloc(i));\n#else\n\tint valsiz = getpagesize(), j;\n\tchar *cp = malloc(i + (valsiz-1));\n\n\tj = ((int)cp + (valsiz-1)) &~ (valsiz-1);\n\treturn ((char *)j);\n#endif\n}\n"
  },
  {
    "path": "lib/libc/gen/wait.c",
    "content": "/*\n * Copyright (c) 1988 The Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/types.h>\n#include <sys/time.h>\n#include <sys/wait.h>\n#include <sys/resource.h>\n\nint\nwait(istat)\n\tint *istat;\n{\n\treturn (wait4(WAIT_ANY, istat, 0, (struct rusage *)0));\n}\n"
  },
  {
    "path": "lib/libc/gen/wait3.c",
    "content": "/*\n * Copyright (c) 1988 The Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/types.h>\n#include <sys/time.h>\n#include <sys/wait.h>\n#include <sys/resource.h>\n\nint\nwait3(istat, options, rup)\n\tint *istat;\n\tint options;\n\tstruct rusage *rup;\n{\n\treturn (wait4(WAIT_ANY, istat, options, rup));\n}\n"
  },
  {
    "path": "lib/libc/gen/waitpid.c",
    "content": "/*\n * Copyright (c) 1988 The Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/types.h>\n#include <sys/time.h>\n#include <sys/wait.h>\n#include <sys/resource.h>\n\nint\nwaitpid(pid, istat, options)\n\tint pid;\n\tint *istat;\n\tint options;\n{\n\treturn (wait4(pid, istat, options, (struct rusage *)0));\n}\n"
  },
  {
    "path": "lib/libc/inet/Makefile",
    "content": "#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\nTOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nSRCS\t\t= inet_addr.c inet_network.c inet_netof.c \\\n\t\t  inet_ntoa.c inet_lnaof.c inet_maddr.c\nOBJS\t\t= inet_addr.o inet_network.o inet_netof.o \\\n\t\t  inet_ntoa.o inet_lnaof.o inet_maddr.o\n\nCFLAGS\t\t+= ${DEFS} -Os\n\ninet.a: ${OBJS}\n\t\t@echo \"building inet.a\"\n\t\t@${AR} cr inet.a ${OBJS}\n\ntags:\n\t\tcwd=`pwd`; \\\n\t\tfor i in ${SRCS}; do \\\n\t\t\tctags -a -f ${TAGSFILE} $$cwd/$$i; \\\n\t\tdone\n\nclean:\n\t\trm -f *.a *~ *.o profiled/*.o errs a.out core tags Makefile.bak\n\ndepend:\n\t\tfor i in ${SRCS}; do \\\n\t\t    cc -M ${CFLAGS} $$i | awk ' { if ($$1 != prev) \\\n\t\t\t{ if (rec != \"\") print rec; rec = $$0; prev = $$1; } \\\n\t\t\telse { if (length(rec $$2) > 78) { print rec; rec = $$0; } \\\n\t\t\telse rec = rec \" \" $$2 } } \\\n\t\t\tEND { print rec } ' >> makedep; done\n\t\techo '/^# DO NOT DELETE THIS LINE/+2,$$d' >eddep\n\t\techo '$$r makedep' >>eddep\n\t\techo 'w' >>eddep\n\t\tcp Makefile Makefile.bak\n\t\ted - Makefile < eddep\n\t\trm eddep makedep\n\t\techo '# DEPENDENCIES MUST END AT END OF FILE' >> Makefile\n\t\techo '# IF YOU PUT STUFF HERE IT WILL GO AWAY' >> Makefile\n\t\techo '# see make depend above' >> Makefile\n\n# DO NOT DELETE THIS LINE -- make depend uses it\n"
  },
  {
    "path": "lib/libc/inet/inet_addr.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/types.h>\n#include <ctype.h>\n#include <netinet/in.h>\n#include <arpa/inet.h>\n\n/*\n * Internet address interpretation routine.\n * All the network library routines call this\n * routine to interpret entries in the data bases\n * which are expected to be an address.\n * The value returned is in network order.\n */\nu_long\ninet_addr(cp)\n\tregister char *cp;\n{\n\tregister u_long val, base;\n\tregister u_int n; /* can't switch on longs - should be an int anyway */\n\tregister char c;\n\tu_long parts[4], *pp = parts;\n\nagain:\n\t/*\n\t * Collect number up to ``.''.\n\t * Values are specified as for C:\n\t * 0x=hex, 0=octal, other=decimal.\n\t */\n\tval = 0; base = 10;\n\tif (*cp == '0')\n\t\tbase = 8, cp++;\n\tif (*cp == 'x' || *cp == 'X')\n\t\tbase = 16, cp++;\n\twhile ((c = *cp)) {\n\t\tif (isdigit(c)) {\n\t\t\tval = (val * base) + (c - '0');\n\t\t\tcp++;\n\t\t\tcontinue;\n\t\t}\n\t\tif (base == 16 && isxdigit(c)) {\n\t\t\tval = (val << 4) + (c + 10 - (islower(c) ? 'a' : 'A'));\n\t\t\tcp++;\n\t\t\tcontinue;\n\t\t}\n\t\tbreak;\n\t}\n\tif (*cp == '.') {\n\t\t/*\n\t\t * Internet format:\n\t\t *\ta.b.c.d\n\t\t *\ta.b.c\t(with c treated as 16-bits)\n\t\t *\ta.b\t(with b treated as 24 bits)\n\t\t */\n\t\tif (pp >= parts + 4)\n\t\t\treturn (-1);\n\t\t*pp++ = val, cp++;\n\t\tgoto again;\n\t}\n\t/*\n\t * Check for trailing characters.\n\t */\n\tif (*cp && !isspace(*cp))\n\t\treturn (-1);\n\t*pp++ = val;\n\t/*\n\t * Concoct the address according to\n\t * the number of parts specified.\n\t */\n\tn = pp - parts;\n\tswitch (n) {\n\n\tcase 1:\t\t\t\t/* a -- 32 bits */\n\t\tval = parts[0];\n\t\tbreak;\n\n\tcase 2:\t\t\t\t/* a.b -- 8.24 bits */\n\t\tval = (parts[0] << 24) | (parts[1] & 0xffffff);\n\t\tbreak;\n\n\tcase 3:\t\t\t\t/* a.b.c -- 8.8.16 bits */\n\t\tval = (parts[0] << 24) | ((parts[1] & 0xff) << 16) |\n\t\t\t(parts[2] & 0xffffL);\n\t\tbreak;\n\n\tcase 4:\t\t\t\t/* a.b.c.d -- 8.8.8.8 bits */\n\t\tval = (parts[0] << 24) | ((parts[1] & 0xff) << 16) |\n\t\t      ((parts[2] & 0xff) << 8) | (parts[3] & 0xff);\n\t\tbreak;\n\n\tdefault:\n\t\treturn (-1);\n\t}\n\tval = htonl(val);\n\treturn (val);\n}\n"
  },
  {
    "path": "lib/libc/inet/inet_lnaof.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/types.h>\n#include <netinet/in.h>\n#include <arpa/inet.h>\n\n/*\n * Return the local network address portion of an\n * internet address; handles class a/b/c network\n * number formats.\n */\nu_long\ninet_lnaof(in)\n\tstruct in_addr in;\n{\n\tregister u_long i = ntohl(in.s_addr);\n\n\tif (IN_CLASSA(i))\n\t\treturn ((i)&IN_CLASSA_HOST);\n\telse if (IN_CLASSB(i))\n\t\treturn ((i)&IN_CLASSB_HOST);\n\telse\n\t\treturn ((i)&IN_CLASSC_HOST);\n}\n"
  },
  {
    "path": "lib/libc/inet/inet_maddr.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/types.h>\n#include <netinet/in.h>\n#include <arpa/inet.h>\n\n/*\n * Formulate an Internet address from network + host.  Used in\n * building addresses stored in the ifnet structure.\n */\nstruct in_addr\ninet_makeaddr(net, host)\n\tlong net, host;\n{\n\tu_long addr;\n\n\tif (net < 128)\n\t\taddr = (net << IN_CLASSA_NSHIFT) | (host & IN_CLASSA_HOST);\n\telse if (net < 65536L)\n\t\taddr = (net << IN_CLASSB_NSHIFT) | (host & IN_CLASSB_HOST);\n\telse\n\t\taddr = (net << IN_CLASSC_NSHIFT) | (host & IN_CLASSC_HOST);\n\taddr = htonl(addr);\n\treturn (*(struct in_addr *)&addr);\n}\n"
  },
  {
    "path": "lib/libc/inet/inet_netof.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/param.h>\n#include <netinet/in.h>\n#include <arpa/inet.h>\n\n/*\n * Return the network number from an internet\n * address; handles class a/b/c network #'s.\n */\nu_long\ninet_netof(in)\n\tstruct in_addr in;\n{\n\tu_long i = ntohl(in.s_addr);\n\n\tif (IN_CLASSA(i))\n\t\treturn (((i)&IN_CLASSA_NET) >> IN_CLASSA_NSHIFT);\n\telse if (IN_CLASSB(i))\n\t\treturn (((i)&IN_CLASSB_NET) >> IN_CLASSB_NSHIFT);\n\telse\n\t\treturn (((i)&IN_CLASSC_NET) >> IN_CLASSC_NSHIFT);\n}\n"
  },
  {
    "path": "lib/libc/inet/inet_network.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/types.h>\n#include <netinet/in.h>\n#include <arpa/inet.h>\n#include <ctype.h>\n\n/*\n * Internet network address interpretation routine.\n * The library routines call this routine to interpret\n * network numbers.\n */\nu_long\ninet_network(cp)\n\tregister char *cp;\n{\n\tregister u_long val, base, n;\n\tregister char c;\n\tu_long parts[4], *pp = parts;\n\tregister int i;\n\nagain:\n\tval = 0; base = 10;\n\tif (*cp == '0')\n\t\tbase = 8, cp++;\n\tif (*cp == 'x' || *cp == 'X')\n\t\tbase = 16, cp++;\n\twhile ((c = *cp)) {\n\t\tif (isdigit(c)) {\n\t\t\tval = (val * base) + (c - '0');\n\t\t\tcp++;\n\t\t\tcontinue;\n\t\t}\n\t\tif (base == 16 && isxdigit(c)) {\n\t\t\tval = (val << 4) + (c + 10 - (islower(c) ? 'a' : 'A'));\n\t\t\tcp++;\n\t\t\tcontinue;\n\t\t}\n\t\tbreak;\n\t}\n\tif (*cp == '.') {\n\t\tif (pp >= parts + 4)\n\t\t\treturn (-1);\n\t\t*pp++ = val, cp++;\n\t\tgoto again;\n\t}\n\tif (*cp && !isspace(*cp))\n\t\treturn (-1);\n\t*pp++ = val;\n\tn = pp - parts;\n\tif (n > 4)\n\t\treturn (-1);\n\tfor (val = 0, i = 0; i < n; i++) {\n\t\tval <<= 8;\n\t\tval |= parts[i] & 0xff;\n\t}\n\treturn (val);\n}\n"
  },
  {
    "path": "lib/libc/inet/inet_ntoa.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * Convert network-format internet address\n * to base 256 d.d.d.d representation.\n */\n#include <stdio.h>\n#include <sys/types.h>\n#include <netinet/in.h>\n#include <arpa/inet.h>\n\nchar *\ninet_ntoa(in)\n\tstruct in_addr in;\n{\n\tstatic char b[18];\n\tregister char *p;\n\n\tp = (char *)&in;\n#define\tUC(b)\t(((int)b)&0xff)\n\tsprintf(b, \"%d.%d.%d.%d\", UC(p[0]), UC(p[1]), UC(p[2]), UC(p[3]));\n\treturn (b);\n}\n"
  },
  {
    "path": "lib/libc/mips/Makefile",
    "content": "#\n# Copyright (c) 1987 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n# Machine dependent routines for the MIPS are located here\n#\nTOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nALL\t\t= gen string sys\n\nmips.a:\t\t${ALL}\n\t\t-mkdir tmp\n\t\tfor i in ${ALL}; do (cd tmp; $(AR) x ../$$i/$$i.a); done\n\t\t$(AR) cr mips.a `ls tmp/*.o | sort`\n\t\trm -rf tmp\n\n${ALL}:\tFRC\n\tcd $@; ${MAKE} ${MFLAGS} DEFS=\"${DEFS}\"\n\nFRC:\n\ntags:\n\t\tfor i in ${ALL}; do \\\n\t\t\t(cd $$i; ${MAKE} ${MFLAGS} TAGSFILE=../${TAGSFILE} tags); \\\n\t\tdone\n\nclean:\n\t\tfor i in ${ALL}; do (cd $$i; ${MAKE} ${MFLAGS} clean); done\n\t\trm -rf *.a tmp *~\n\ndepend:\n\t\tfor i in ${ALL}; do \\\n\t\t\t(cd $$i; ${MAKE} ${MFLAGS} DEFS=\"${DEFS}\" depend); done\n"
  },
  {
    "path": "lib/libc/mips/gen/Makefile",
    "content": "#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\nTOPSRC!=cd ../../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS\t\t+= ${DEFS}\n\nSRCS\t\t= _setjmp.S htonl.S htons.S setjmp.S sigsetjmp.S\nOBJS\t\t= _setjmp.o htonl.o htons.o setjmp.o sigsetjmp.o\n\ngen.a:\t\t${OBJS}\n\t\t@echo \"building gen.a\"\n\t\t@${AR} cr gen.a ${OBJS}\n\ntags:\n\t\tcwd=`pwd`; \\\n\t\tfor i in ${SRCS}; do \\\n\t\t\tctags -a -f ${TAGSFILE} $$cwd/$$i; \\\n\t\tdone\n\nclean:\n\t\trm -f gen.a *.o *~ profiled/*.o tags Makefile.bak\n\ndepend:\n\t\tfor i in ${SRCS}; do \\\n\t\t    cc -M ${CFLAGS} $$i | awk ' { if ($$1 != prev) \\\n\t\t\t{ if (rec != \"\") print rec; rec = $$0; prev = $$1; } \\\n\t\t\telse { if (length(rec $$2) > 78) { print rec; rec = $$0; } \\\n\t\t\telse rec = rec \" \" $$2 } } \\\n\t\t\tEND { print rec } ' >> makedep; done\n\t\techo '/^# DO NOT DELETE THIS LINE/+2,$$d' >eddep\n\t\techo '$$r makedep' >>eddep\n\t\techo 'w' >>eddep\n\t\tcp Makefile Makefile.bak\n\t\ted - Makefile < eddep\n\t\trm eddep makedep\n\t\techo '# DEPENDENCIES MUST END AT END OF FILE' >> Makefile\n\t\techo '# IF YOU PUT STUFF HERE IT WILL GO AWAY' >> Makefile\n\t\techo '# see make depend above' >> Makefile\n\n# DO NOT DELETE THIS LINE -- make depend uses it\n"
  },
  {
    "path": "lib/libc/mips/gen/_setjmp.S",
    "content": "/*-\n * Copyright (c) 1991, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Ralph Campbell.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n/*\n * C library -- _setjmp, _longjmp\n *\n *\t_longjmp(a,v)\n * will generate a \"return(v)\" from\n * the last call to\n *\t_setjmp(a)\n * by restoring registers from the stack,\n * The previous signal state is NOT restored.\n */\n\t\t.set\tnoreorder\n\n\t\t.type\t_setjmp, @function\n_setjmp:\t.globl \t_setjmp\n\n\t\tsw\t$s0, (0 * 4) ($a0)\t# save register variables s0-s8\n\t\tsw\t$s1, (1 * 4) ($a0)\n\t\tsw\t$s2, (2 * 4) ($a0)\n\t\tsw\t$s3, (3 * 4) ($a0)\n\t\tsw\t$s4, (4 * 4) ($a0)\n\t\tsw\t$s5, (5 * 4) ($a0)\n\t\tsw\t$s6, (6 * 4) ($a0)\n\t\tsw\t$s7, (7 * 4) ($a0)\n\t\tsw\t$s8, (8 * 4) ($a0)\t# frame pointer\n\t\tsw\t$ra, (9 * 4) ($a0)\t# return address\n\t\tsw\t$gp, (10 * 4) ($a0)\t# global data pointer\n\t\tsw\t$sp, (11 * 4) ($a0)\t# stack pointer\n\n\t\t# For compatibility with longjmp and siglongjmp\n\t\tsw\t$zero, (12 * 4) ($a0)   # signal mask saved\n\t\tsw\t$zero, (13 * 4) ($a0)   # signal mask\n\n\t\tj\t$ra\n\t\tmove\t$v0, $zero\t\t# return a zero for the setjmp call\n\n\t\t.type\t_longjmp, @function\n_longjmp:\t.globl\t_longjmp\n\n\t\tlw\t$s0, (0 * 4) ($a0)\t# restore register variables s0-s8\n\t\tlw\t$s1, (1 * 4) ($a0)\n\t\tlw\t$s2, (2 * 4) ($a0)\n\t\tlw\t$s3, (3 * 4) ($a0)\n\t\tlw\t$s4, (4 * 4) ($a0)\n\t\tlw\t$s5, (5 * 4) ($a0)\n\t\tlw\t$s6, (6 * 4) ($a0)\n\t\tlw\t$s7, (7 * 4) ($a0)\n\t\tlw\t$s8, (8 * 4) ($a0)\t# frame pointer\n\t\tlw\t$ra, (9 * 4) ($a0)\t# return address\n\t\tlw\t$gp, (10 * 4) ($a0)\t# global data pointer\n\t\tlw\t$sp, (11 * 4) ($a0)\t# stack pointer\n\n\t\tj\t$ra\t\t\t# transfer back to setjmp()\n\t\tmove\t$v0, $a1\t\t# get return value in 1st arg\n"
  },
  {
    "path": "lib/libc/mips/gen/htonl.S",
    "content": "/*-\n * Copyright (c) 1997 The NetBSD Foundation, Inc.\n * All rights reserved.\n *\n * This code is derived from software contributed to The NetBSD Foundation\n * by Neil A. Carson\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the NetBSD\n *\tFoundation, Inc. and its contributors.\n * 4. Neither the name of The NetBSD Foundation nor the names of its\n *    contributors may be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS\n * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\n * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n */\n\n#\n# a0 = 0x11223344, return 0x44332211\n#\n\t\t.type\thtonl, @function\nhtonl:\t\t.globl \thtonl\n\t\t.type\tntohl, @function\nntohl:\t\t.globl \tntohl\n\n#ifdef __MIPSEB__\n\t\tmove\t$v0, $a0\n#else\n\t\tsrl     $v1, $a0, 24\t\t# v1 = 0x00000011\n\t\tsll     $v0, $a0, 24\t\t# v0 = 0x44000000\n\t\tor      $v0, $v0, $v1\n\t\tandi    $v1, $a0, 0xff00\n\t\tsll     $v1, $v1, 8\t\t# v1 = 0x00330000\n\t\tor      $v0, $v0, $v1\n\t\tsrl     $v1, $a0, 8\n\t\tandi    $v1, $v1, 0xff00\t# v1 = 0x00002200\n\t\tor      $v0, $v0, $v1\n#endif\n\t\tj       $ra\n"
  },
  {
    "path": "lib/libc/mips/gen/htons.S",
    "content": "/*-\n * Copyright (c) 1999 The NetBSD Foundation, Inc.\n * All rights reserved.\n *\n * This code is derived from software contributed to The NetBSD Foundation\n * by Charles M. Hannum.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the NetBSD\n *\tFoundation, Inc. and its contributors.\n * 4. Neither the name of The NetBSD Foundation nor the names of its\n *    contributors may be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS\n * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\n * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n */\n\n\t\t.type\thtons, @function\nhtons:\t\t.globl \thtons\n\t\t.type\tntohs, @function\nntohs:\t\t.globl \tntohs\n#ifdef __MIPSEB__\n\t\tmove    $v0, $a0\n#else\n\t\tsrl\t$v0, $a0, 8\n\t\tandi\t$v0, $v0, 0xff\n\t\tsll\t$v1, $a0, 8\n\t\tandi\t$v1, $v1, 0xff00\n\t\tor\t$v0, $v0, $v1\n#endif\n\t\tj\t$ra\n"
  },
  {
    "path": "lib/libc/mips/gen/setjmp.S",
    "content": "/*-\n * Copyright (c) 1991, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Ralph Campbell.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n/*\n * C library -- setjmp, longjmp\n *\n *\tlongjmp(a,v)\n * will generate a \"return(v)\" from\n * the last call to\n *\tsetjmp(a)\n * by restoring registers from the stack,\n * and a struct sigcontext, see <signal.h>\n *\n * From: Chris Dearman <cjwdearman@gmail.com>\n */\n\t\t.set\tnoreorder\n\n\t\t.type\tsetjmp, @function\nsetjmp:\t\t.globl \tsetjmp\n\n\t\tsubu\t$sp, $sp, 24\n\t\tsw\t$ra, 20($sp)\n\t\tsw\t$a0, 24($sp)\n\n\t\t/* Get the signal mask. */\n\t\taddu\t$a2, $a0, 13*4\t\t# &omask\n\t\tli\t$a0, 1\t\t\t# SIG_BLOCK\n\t\tjal\tsigprocmask\t\t# get current signal mask\n\t\tmove\t$a1, $0\t\t\t# BDS: NULL\n\n\t\tlw\t$a0, 24($sp)\n\t\tlw\t$ra, 20($sp)\n\t\taddu\t$sp, $sp, 24\n\n\t\tli\t$t0, 1\n\t\tsw\t$t0, (12 * 4)($a0)\n\n\t\tsw\t$s0, (0 * 4) ($a0)\t# save register variables s0-s8\n\t\tsw\t$s1, (1 * 4) ($a0)\n\t\tsw\t$s2, (2 * 4) ($a0)\n\t\tsw\t$s3, (3 * 4) ($a0)\n\t\tsw\t$s4, (4 * 4) ($a0)\n\t\tsw\t$s5, (5 * 4) ($a0)\n\t\tsw\t$s6, (6 * 4) ($a0)\n\t\tsw\t$s7, (7 * 4) ($a0)\n\t\tsw\t$s8, (8 * 4) ($a0)\t# frame pointer\n\t\tsw\t$ra, (9 * 4) ($a0)\t# return address\n\t\tsw\t$gp, (10 * 4) ($a0)\t# global data pointer\n\t\tsw\t$sp, (11 * 4) ($a0)\t# stack pointer\n\n\t\tj\t$ra\n\t\tmove\t$v0, $zero\t\t# BDS: return a zero for the setjmp call\n\n\n\t\t.type\tlongjmp, @function\nlongjmp:\t.globl\tlongjmp\n\n\t\tsubu\t$sp, $sp, 24\n\t\tsw\t$ra, 20($sp)\n\t\tsw\t$a0, 24($sp)\n\t\tsw\t$a1, 28($sp)\n\n\t\t/* Restore signal mask. */\n\t\taddu\t$a1, $a0, 13*4\t\t# &omask\n\t\tmove\t$a2, $0\t\t\t# NULL\n\t\tjal\tsigprocmask\t\t# set current signal mask\n\t\tli\t$a0, 3\t\t\t# BDS: SIG_SETMASK\n\n\t\tlw\t$a1, 28($sp)\n\t\tlw\t$a0, 24($sp)\n\t\tlw\t$ra, 20($sp)\n\t\taddu\t$sp, $sp, 24\n\n\t\tlw\t$s0, (0 * 4) ($a0)\t# restore register variables s0-s8\n\t\tlw\t$s1, (1 * 4) ($a0)\n\t\tlw\t$s2, (2 * 4) ($a0)\n\t\tlw\t$s3, (3 * 4) ($a0)\n\t\tlw\t$s4, (4 * 4) ($a0)\n\t\tlw\t$s5, (5 * 4) ($a0)\n\t\tlw\t$s6, (6 * 4) ($a0)\n\t\tlw\t$s7, (7 * 4) ($a0)\n\t\tlw\t$s8, (8 * 4) ($a0)\t# frame pointer\n\t\tlw\t$ra, (9 * 4) ($a0)\t# return address\n\t\tlw\t$gp, (10 * 4) ($a0)\t# global data pointer\n\t\tlw\t$sp, (11 * 4) ($a0)\t# stack pointer\n\n\t\tj\t$ra\n\t\tmove\t$v0, $a1\t\t# BDS: return value from longjmp\n"
  },
  {
    "path": "lib/libc/mips/gen/sigsetjmp.S",
    "content": "/*-\n * Copyright (c) 1991, 1993, 1995,\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Havard Eidnes.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n/*\n * C library -- sigsetjmp, siglongjmp\n *\n *\tsiglongjmp(a,v)\n * will generate a \"return(v)\" from\n * the last call to\n *\tsigsetjmp(a, savemask)\n * by restoring registers from the stack,\n * and dependent on savemask restores the\n * signal mask.\n *\n * From: Chris Dearman <cjwdearman@gmail.com>\n */\n\t\t.set\tnoreorder\n\n\t\t.type\tsigsetjmp, @function\nsigsetjmp:\t.globl \tsigsetjmp\n\n\t\tbne\t$a1, 0x0, 1f\t\t# do saving of signal mask?\n\t\tnop\n\t\tj\t_setjmp\n\t\tnop\n1:\t\tj\tsetjmp\n\t\tnop\n\n\t\t.type\tsiglongjmp, @function\nsiglongjmp:\t.globl \tsiglongjmp\n\n\t\tlw\t$t0, (12 * 4)($a0)\n\t\tbnez\t$t0, 1f\n\t\tnop\n\t\tj\t_longjmp\n\t\tnop\n1:\t\tj\tlongjmp\n\t\tnop\n"
  },
  {
    "path": "lib/libc/mips/string/Makefile",
    "content": "#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\nTOPSRC!=cd ../../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS\t\t+= ${DEFS}\n\n#\n# Endian-independent assembly-code aliases for unaligned memory accesses.\n# Little endian.\n#\nASFLAGS\t\t+= -DLWHI=lwr -DLWLO=lwl -DSWHI=swr -DSWLO=swl\n\nSRCS\t\t= bcopy.S bzero.S ffs.S memcpy.S memmove.S memset.S \\\n                  strlen.S bcmp.S index.S rindex.S strcmp.S\nOBJS\t\t= bcopy.o bzero.o ffs.o memcpy.o memmove.o memset.o \\\n                  strlen.o bcmp.o index.o rindex.o strcmp.o\n\nstring.a:\t${OBJS}\n\t\t@echo \"building string.a\"\n\t\t@${AR} cr string.a ${OBJS}\n\ntags:\n\t\tcwd=`pwd`; \\\n\t\tfor i in ${SRCS}; do \\\n\t\t\tctags -a -f ${TAGSFILE} $$cwd/$$i; \\\n\t\tdone\n\nclean:\n\t\trm -f string.a *.o *~ profiled/*.o tags Makefile.bak\n\ndepend:\n\t\tfor i in ${SRCS}; do \\\n\t\t    cc -M ${CFLAGS} $$i | awk ' { if ($$1 != prev) \\\n\t\t\t{ if (rec != \"\") print rec; rec = $$0; prev = $$1; } \\\n\t\t\telse { if (length(rec $$2) > 78) { print rec; rec = $$0; } \\\n\t\t\telse rec = rec \" \" $$2 } } \\\n\t\t\tEND { print rec } ' >> makedep; done\n\t\techo '/^# DO NOT DELETE THIS LINE/+2,$$d' >eddep\n\t\techo '$$r makedep' >>eddep\n\t\techo 'w' >>eddep\n\t\tcp Makefile Makefile.bak\n\t\ted - Makefile < eddep\n\t\trm eddep makedep\n\t\techo '# DEPENDENCIES MUST END AT END OF FILE' >> Makefile\n\t\techo '# IF YOU PUT STUFF HERE IT WILL GO AWAY' >> Makefile\n\t\techo '# see make depend above' >> Makefile\n\n# DO NOT DELETE THIS LINE -- make depend uses it\n"
  },
  {
    "path": "lib/libc/mips/string/bcmp.S",
    "content": "/*-\n * Copyright (c) 1991, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Ralph Campbell.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n/* bcmp(s1, s2, n) */\n\n\t.type\tbcmp, @function\nbcmp:\t.globl  bcmp\n\t.set\tnoreorder\n\t.set\tnoat\n\n        slti    $at, $a2, 16\t# small amount to clear?\n        bnez    $at, small\t# is it worth any trouble?\n\txor\t$v0, $a0, $a1\t# compare low two bits of addresses\n\tandi\t$v0, $v0, 3\n\tsubu\t$a3, $zero, $a1\t# compute # bytes to word align address\n\tbne\t$v0, $zero, unaligned # not possible to align addresses\n\tandi\t$a3, $a3, 3\n\n\tbeq\t$a3, $zero, 1f\n\tsubu\t$a2, $a2, $a3\t# subtract from remaining count\n\tmove\t$v0, $v1\t\t# init v0,v1 so unmodified bytes match\n\tLWHI\t$v0, 0($a0)\t# read 1, 2, or 3 bytes\n\tLWHI\t$v1, 0($a1)\n\taddu\t$a1, $a1, $a3\n\tbne\t$v0, $v1, nomatch\n\taddu\t$a0, $a0, $a3\n1:\n        li      $at, ~3\n\tand\t$a3, $a2, $at\t# compute number of whole words left\n\tsubu\t$a2, $a2, $a3\t#   which has to be >= (16-3) & ~3\n\taddu\t$a3, $a3, $a0\t# compute ending address\n2:\n\tlw\t$v0, 0($a0)\t# compare words\n\tlw\t$v1, 0($a1)\n\taddiu\t$a0, $a0, 4\n\tbne\t$v0, $v1, nomatch\n\taddiu\t$a1, $a1, 4\n\tbne\t$a0, $a3, 2b\n\tnop\n\tb\tsmall\t\t# finish remainder\n\tnop\nunaligned:\n\tbeq\t$a3, $zero, 2f\n\tsubu\t$a2, $a2, $a3\t# subtract from remaining count\n\taddu\t$a3, $a3, $a0\t# compute ending address\n1:\n\tlbu\t$v0, 0($a0)\t# compare bytes until a1 word aligned\n\tlbu\t$v1, 0($a1)\n\taddiu\t$a0, $a0, 1\n\tbne\t$v0, $v1, nomatch\n\taddiu\t$a1, $a1, 1\n\tbne\t$a0, $a3, 1b\n\tnop\n2:\n        li      $at, ~3\n\tand\t$a3, $a2, $at\t# compute number of whole words left\n\tsubu\t$a2, $a2, $a3\t#   which has to be >= (16-3) & ~3\n\taddu\t$a3, $a3, $a0\t# compute ending address\n3:\n\tLWHI\t$v0, 0($a0)\t# compare words a0 unaligned, a1 aligned\n\tLWLO\t$v0, 3($a0)\n\tlw\t$v1, 0($a1)\n\taddiu\t$a0, $a0, 4\n\tbne\t$v0, $v1, nomatch\n\taddiu\t$a1, $a1, 4\n\tbne\t$a0, $a3, 3b\n\tnop\nsmall:\n        blez    $a2, match\n\taddu\t$a3, $a2, $a0\t\t# compute ending address\n1:\n\tlbu\t$v0, 0($a0)\n\tlbu\t$v1, 0($a1)\n\taddiu\t$a0, $a0, 1\n\tbne\t$v0, $v1, nomatch\n\taddiu\t$a1, $a1, 1\n\tbne\t$a0, $a3, 1b\n\tnop\nmatch:\n\tj\t$ra\n\tmove\t$v0, $zero\nnomatch:\n\tj\t$ra\n\tli\t$v0, 1\n"
  },
  {
    "path": "lib/libc/mips/string/bcopy.S",
    "content": "/*\n * Fast copy routine.  Derived from aligned_block_copy.\n ^\n *\tbcopy(caddr_t src, caddr_t dst, unsigned int len)\n *\n *\ta0 \tsrc address\n *\ta1\tdst address\n *\ta2\tlength\n *\n * Author:\tChris Maeda\n * Date:\tJune 1993\n *\n * Mach Operating System\n * Copyright (c) 1993 Carnegie Mellon University\n * All Rights Reserved.\n *\n * Permission to use, copy, modify and distribute this software and its\n * documentation is hereby granted, provided that both the copyright\n * notice and this permission notice appear in all copies of the\n * software, derivative works or modified versions, and any portions\n * thereof, and that both notices appear in supporting documentation.\n *\n * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS \"AS IS\"\n * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR\n * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.\n *\n * Carnegie Mellon requests users of this software to return to\n *\n *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU\n *  School of Computer Science\n *  Carnegie Mellon University\n *  Pittsburgh PA 15213-3890\n *\n * any improvements or extensions that they make and grant Carnegie Mellon\n * the rights to redistribute these changes.\n */\n#if defined(MEMCOPY) || defined(MEMMOVE)\n#   ifdef MEMCOPY\n#      define FUNCTION\tmemcpy\n#   else\n#      define FUNCTION\tmemmove\n#   endif\n#   define SRCREG\t$a1\n#   define DSTREG\t$a0\n#else\n#   define FUNCTION\tbcopy\n#   define SRCREG\t$a0\n#   define DSTREG\t$a1\n#endif\n\n#define\tSIZEREG\t\t$a2\n\n\t.globl  FUNCTION\n\t.type\tFUNCTION, @function\nFUNCTION:\n\t.set\tnoat\n\t.set\tnoreorder\n\n#if defined(MEMCOPY) || defined(MEMMOVE)\n\t/* set up return value, while we still can */\n\tmove\t$v0,DSTREG\n#endif\n\t#\n\t# Make sure we can copy forwards.\n\t#\n\tsltu\t$t0,SRCREG,DSTREG\t# t0 == SRCREG < DSTREG\n\tbne\t$t0,$zero,6f\t\t# copy backwards\n\n\t#\n\t# There are four alignment cases (with frequency)\n\t# (Based on measurements taken with a DECstation 5000/200\n\t# inside a Mach kernel.)\n\t#\n\t# aligned   -> aligned\t\t(mostly)\n\t# unaligned -> aligned\t\t(sometimes)\n\t# aligned,unaligned -> unaligned\t(almost never)\n\t#\n\t# Note that we could add another case that checks if\n\t# the destination and source are unaligned but the\n\t# copy is alignable.  eg if src and dest are both\n\t# on a halfword boundary.\n\t#\n\tandi\t$t1,DSTREG,3\t\t# get last 3 bits of dest\n\tbne\t$t1,$zero,3f\n\tandi\t$t0,SRCREG,3\t\t# get last 3 bits of src\n\tbne\t$t0,$zero,5f\n\n\t#\n\t# Forward aligned->aligned copy, 8*4 bytes at a time.\n\t#\n\tli\t$at,-32\n\tand\t$t0,SIZEREG,$at\t\t# count truncated to multiple of 32 */\n\taddu\t$a3,SRCREG,$t0\t\t# run fast loop up to this address\n\tsltu\t$at,SRCREG,$a3\t\t# any work to do?\n\tbeq\t$at,$zero,2f\n\tsubu\tSIZEREG,$t0\n\n\t#\n\t# loop body\n\t#\n1:\t# cp\n\tlw\t$t3,0(SRCREG)\n\tlw\t$v1,4(SRCREG)\n\tlw\t$t0,8(SRCREG)\n\tlw\t$t1,12(SRCREG)\n\taddiu\tSRCREG,32\n\tsw\t$t3,0(DSTREG)\n\tsw\t$v1,4(DSTREG)\n\tsw\t$t0,8(DSTREG)\n\tsw\t$t1,12(DSTREG)\n\tlw\t$t1,-4(SRCREG)\n\tlw\t$t0,-8(SRCREG)\n\tlw\t$v1,-12(SRCREG)\n\tlw\t$t3,-16(SRCREG)\n\taddiu\tDSTREG,32\n\tsw\t$t1,-4(DSTREG)\n\tsw\t$t0,-8(DSTREG)\n\tsw\t$v1,-12(DSTREG)\n\tbne\tSRCREG,$a3,1b\n\tsw\t$t3,-16(DSTREG)\n\n\t#\n\t# Copy a word at a time, no loop unrolling.\n\t#\n2:\t# wordcopy\n\tandi\t$t2,SIZEREG,3\t\t# get byte count / 4\n\tsubu\t$t2,SIZEREG,$t2\t\t# t2 = number of words to copy * 4\n\tbeq\t$t2,$zero,3f\n\taddu\t$t0,SRCREG,$t2\t\t# stop at t0\n\tsubu\tSIZEREG,SIZEREG,$t2\n1:\n\tlw\t$t3,0(SRCREG)\n\taddiu\tSRCREG,4\n\tsw\t$t3,0(DSTREG)\n\tbne\tSRCREG,$t0,1b\n\taddiu\tDSTREG,4\n\n3:\t# bytecopy\n\tbeq\tSIZEREG,$zero,4f\t# nothing left to do?\n\tnop\n1:\n\tlb\t$t3,0(SRCREG)\n\taddiu\tSRCREG,1\n\tsb\t$t3,0(DSTREG)\n\taddiu\tSIZEREG,-1\n\tbgtz\tSIZEREG,1b\n\taddiu\tDSTREG,1\n\n4:\t# copydone\n\tj\t$ra\n\tnop\n\n\t#\n\t# Copy from unaligned source to aligned dest.\n\t#\n5:\t# destaligned\n\tandi\t$t0,SIZEREG,3\t\t# t0 = bytecount mod 4\n\tsubu\t$a3,SIZEREG,$t0\t\t# number of words to transfer\n\tbeq\t$a3,$zero,3b\n\tnop\n\tmove\tSIZEREG,$t0\t\t# this many to do after we are done\n\taddu\t$a3,SRCREG,$a3\t\t# stop point\n\n1:\n\tLWHI\t$t3,0(SRCREG)\n\tLWLO\t$t3,3(SRCREG)\n\taddi\tSRCREG,4\n\tsw\t$t3,0(DSTREG)\n\tbne\tSRCREG,$a3,1b\n\taddi\tDSTREG,4\n\n\tj\t3b\n\tnop\n\n6:\t# backcopy -- based on above\n\taddu\tSRCREG,SIZEREG\n\taddu\tDSTREG,SIZEREG\n\tandi\t$t1,DSTREG,3\t\t# get last 3 bits of dest\n\tbne\t$t1,$zero,3f\n\tandi\t$t0,SRCREG,3\t\t# get last 3 bits of src\n\tbne\t$t0,$zero,5f\n\n\t#\n\t# Forward aligned->aligned copy, 8*4 bytes at a time.\n\t#\n\tli\t$at,-32\n\tand\t$t0,SIZEREG,$at\t\t# count truncated to multiple of 32\n\tbeq\t$t0,$zero,2f\t\t# any work to do?\n\tsubu\tSIZEREG,$t0\n\tsubu\t$a3,SRCREG,$t0\n\n\t#\n\t# loop body\n\t#\n1:\t# cp\n\tlw\t$t3,-16(SRCREG)\n\tlw\t$v1,-12(SRCREG)\n\tlw\t$t0,-8(SRCREG)\n\tlw\t$t1,-4(SRCREG)\n\taddiu\tSRCREG,-32\n\tsw\t$t3,-16(DSTREG)\n\tsw\t$v1,-12(DSTREG)\n\tsw\t$t0,-8(DSTREG)\n\tsw\t$t1,-4(DSTREG)\n\tlw\t$t1,12(SRCREG)\n\tlw\t$t0,8(SRCREG)\n\tlw\t$v1,4(SRCREG)\n\tlw\t$t3,0(SRCREG)\n\taddiu\tDSTREG,-32\n\tsw\t$t1,12(DSTREG)\n\tsw\t$t0,8(DSTREG)\n\tsw\t$v1,4(DSTREG)\n\tbne\tSRCREG,$a3,1b\n\tsw\t$t3,0(DSTREG)\n\n\t#\n\t# Copy a word at a time, no loop unrolling.\n\t#\n2:\t# wordcopy\n\tandi\t$t2,SIZEREG,3\t\t# get byte count / 4\n\tsubu\t$t2,SIZEREG,$t2\t\t# t2 = number of words to copy * 4\n\tbeq\t$t2,$zero,3f\n\tsubu\t$t0,SRCREG,$t2\t\t# stop at t0\n\tsubu\tSIZEREG,SIZEREG,$t2\n1:\n\tlw\t$t3,-4(SRCREG)\n\taddiu\tSRCREG,-4\n\tsw\t$t3,-4(DSTREG)\n\tbne\tSRCREG,$t0,1b\n\taddiu\tDSTREG,-4\n\n3:\t# bytecopy\n\tbeq\tSIZEREG,$zero,4f\t# nothing left to do?\n\tnop\n1:\n\tlb\t$t3,-1(SRCREG)\n\taddiu\tSRCREG,-1\n\tsb\t$t3,-1(DSTREG)\n\taddiu\tSIZEREG,-1\n\tbgtz\tSIZEREG,1b\n\taddiu\tDSTREG,-1\n\n4:\t# copydone\n\tj\t$ra\n\tnop\n\n\t#\n\t# Copy from unaligned source to aligned dest.\n\t#\n5:\t# destaligned\n\tandi\t$t0,SIZEREG,3\t\t# t0 = bytecount mod 4\n\tsubu\t$a3,SIZEREG,$t0\t\t# number of words to transfer\n\tbeq\t$a3,$zero,3b\n\tnop\n\tmove\tSIZEREG,$t0\t\t# this many to do after we are done\n\tsubu\t$a3,SRCREG,$a3\t\t# stop point\n\n1:\n\tLWHI\t$t3,-4(SRCREG)\n\tLWLO\t$t3,-1(SRCREG)\n\taddiu\tSRCREG,-4\n\tsw\t$t3,-4(DSTREG)\n\tbne\tSRCREG,$a3,1b\n\taddiu\tDSTREG,-4\n\n\tj\t3b\n\tnop\n\n\t.set\treorder\n\t.set\tat\n"
  },
  {
    "path": "lib/libc/mips/string/bzero.S",
    "content": "/*-\n * Copyright (c) 1991, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Ralph Campbell.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n/* bzero(s1, n) */\n\n#define SZREG 4\n\n\t.type\tbzero, @function\nbzero:\t.globl  bzero\n\t.set\tnoreorder\n\t.set\tnoat\n\n        slti    $at, $a1, 3*SZREG\t# small amount to clear?\n        bnez    $at, smallclr\n\tsubu\t$a3, $zero, $a0\t\t# compute # bytes to word align address\n\tandi\t$a3, $a3, SZREG-1\n\tbeqz\t$a3, 1f\t\t\t# skip if word aligned\n\tsubu\t$a1, $a1, $a3\t\t# subtract from remaining count\n\tSWHI\t$zero, 0($a0)\t\t# clear 1, 2, or 3 bytes to align\n\taddu\t$a0, $a0, $a3\n1:\n\tandi\t$v0, $a1, SZREG-1\t# compute number of words left\n\tsubu\t$a3, $a1, $v0\n\tmove\t$a1, $v0\n\taddu\t$a3, $a3, $a0\t\t# compute ending address\n2:\n\taddiu\t$a0, $a0, SZREG\t\t# clear words\n\tbne\t$a0, $a3, 2b\t\t# unrolling loop doesnt help\n\tsw\t$zero, -SZREG($a0)\t# since we are limited by memory speed\nsmallclr:\n        blez    $a1, 2f\n\taddu\t$a3, $a1, $a0\t\t# compute ending address\n1:\n\taddiu\t$a0, $a0, 1\t\t# clear bytes\n\tbne\t$a0, $a3, 1b\n\tsb\t$zero, -1($a0)\n2:\n\tj\t$ra\n\tnop\n"
  },
  {
    "path": "lib/libc/mips/string/ffs.S",
    "content": "/*-\n * Copyright (c) 1991, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Ralph Campbell.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n/* bit = ffs(value) */\n        .set    reorder\n\t.type\tffs, @function\nffs:\t.globl  ffs\n\n\tmove\t$v0, $zero\n\tbeq\t$a0, $zero, done\n1:\n\tandi\t$v1, $a0, 1\t\t# bit set?\n\taddiu\t$v0, $v0, 1\n\tsrl\t$a0, $a0, 1\n\tbeq\t$v1, $zero, 1b\t\t# no, continue\ndone:\n\tj\t$ra\n"
  },
  {
    "path": "lib/libc/mips/string/index.S",
    "content": "/*-\n * Copyright (c) 1991, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Ralph Campbell.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n        .set    reorder\n\t.type\tindex, @function\nindex:\t.globl  index\n1:\n\tlbu\t$a2, 0($a0)\t\t# get a byte\n\taddiu\t$a0, $a0, 1\n\tbeq\t$a2, $a1, fnd\n\tbnez\t$a2, 1b\nnotfnd:\n\tmove\t$v0, $zero\n\tj\t$ra\nfnd:\n\taddiu\t$v0, $a0, -1\n\tj\t$ra\n"
  },
  {
    "path": "lib/libc/mips/string/memcpy.S",
    "content": "#define MEMCOPY\n#include \"bcopy.S\"\n"
  },
  {
    "path": "lib/libc/mips/string/memmove.S",
    "content": "#define MEMMOVE\n#include \"bcopy.S\"\n"
  },
  {
    "path": "lib/libc/mips/string/memset.S",
    "content": "#\n# memset(void *s1, int c, int len)\n#\n\t.type\tmemset, @function\nmemset:\t.globl  memset\n\t.set\tnoreorder\n\t.set\tnoat\n\n        slti    $at, $a2, 12\t\t# small amount to clear?\n        bnez    $at, smallclr\n\tmove\t$v0, $a0\t\t# save s1 for result\n\n\tsll\t$t1, $a1, 8\t\t# compute  c << 8 in t1\n\tor\t$t1, $t1, $a1\t\t# compute c << 8 | c in 11\n\tsll\t$t2, $t1, 16\t\t# shift that left 16\n\tor\t$t1, $t2, $t1\t\t# or together\n\n\tsubu\t$t0, $zero, $a0\t\t# compute # bytes to word align address\n\tandi\t$t0, $t0, 3\n\tbeqz\t$t0, 1f\t\t\t# skip if word aligned\n\tsubu\t$a2, $a2, $t0\t\t# subtract from remaining count\n\tSWHI\t$t1, 0($a0)\t\t# store 1, 2, or 3 bytes to align\n\taddu\t$a0, $a0, $t0\n1:\n\tandi\t$v1, $a2, 3\t\t# compute number of whole words left\n\tsubu\t$t0, $a2, $v1\n\tsubu\t$a2, $a2, $t0\n\taddu\t$t0, $t0, $a0\t\t# compute ending address\n2:\n\taddiu\t$a0, $a0, 4\t\t# clear words\n\tbne\t$a0, $t0, 2b\t\t#  unrolling loop does not help\n\tsw\t$t1, -4($a0)\t\t#  since we are limited by memory speed\n\nsmallclr:\n        blez    $a2, 2f\n\taddu\t$t0, $a2, $a0\t\t# compute ending address\n1:\n\taddiu\t$a0, $a0, 1\t\t# clear bytes\n\tbne\t$a0, $t0, 1b\n\tsb\t$a1, -1($a0)\n2:\n\tj\t$ra\n\tnop\n"
  },
  {
    "path": "lib/libc/mips/string/rindex.S",
    "content": "/*-\n * Copyright (c) 1991, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Ralph Campbell.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n        .set    reorder\n\t.type\trindex, @function\nrindex:\t.globl  rindex\n\n\tmove\t$v0, $zero\t\t# default if not found\n1:\n\tlbu\t$a3, 0($a0)\t\t# get a byte\n\taddiu\t$a0, $a0, 1\n\tbne\t$a3, $a1, 2f\n\taddiu\t$v0, $a0, -1\t\t# save address of last match\n2:\n\tbnez\t$a3, 1b\t\t# continue if not end\n\tj\t$ra\n"
  },
  {
    "path": "lib/libc/mips/string/strcmp.S",
    "content": "/*-\n * Copyright (c) 1991, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Ralph Campbell.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n#\n# NOTE: this version assumes unsigned chars in order to be \"8 bit clean\".\n#\n        .set    reorder\n\t.type\tstrcmp, @function\nstrcmp:\t.globl  strcmp\n1:\n\tlbu\t$t0, 0($a0)\t\t# get two bytes and compare them\n\tlbu\t$t1, 0($a1)\n\tbeqz\t$t0, LessOrEq\t\t# end of first string?\n\tbne\t$t0, $t1, NotEq\n\tlbu\t$t0, 1($a0)\t\t# unroll loop\n\tlbu\t$t1, 1($a1)\n\taddi\t$a0, $a0, 2\n\tbeqz\t$t0, LessOrEq\t\t# end of first string?\n\taddi\t$a1, $a1, 2\n\tbeq\t$t0, $t1, 1b\nNotEq:\n\tsubu\t$v0, $t0, $t1\n\tj\t$ra\nLessOrEq:\n\tsubu\t$v0, $zero, $t1\n\tj\t$ra\n"
  },
  {
    "path": "lib/libc/mips/string/strlen.S",
    "content": "/*-\n * Copyright (c) 1991, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Ralph Campbell.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n        .set    reorder\n\t.type\tstrlen, @function\nstrlen:\t.globl  strlen\n\n\taddiu\t$v1, $a0, 1\n1:\n\tlb\t$v0, 0($a0)\t\t# get byte from string\n\taddiu\t$a0, $a0, 1\t\t# increment pointer\n\tbne\t$v0, $zero, 1b\t\t# continue if not end\n\tsubu\t$v0, $a0, $v1\t\t# compute length - 1 for '\\0' char\n\tj\t$ra\n"
  },
  {
    "path": "lib/libc/mips/sys/Makefile",
    "content": "TOPSRC!=cd ../../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nASFLAGS\t\t+= ${DEFS}\nCFLAGS          += -Os\n\n# modules which can not use SYSCALL and must be assembled from sources.  The\n# rest of the system calls are generated with printf(1) and do not have\n# source files associated with them.\n\nCOBJS\t\t= sbrk.o execl.o execle.o execv.o\n\nASMOBJS\t\t= _exit.o _brk.o pipe.o ptrace.o sigaction.o\n\nSYSOBJS\t\t= __sysctl.o accept.o access.o adjtime.o bind.o chdir.o \\\n\t\t  chflags.o chmod.o chown.o chroot.o close.o connect.o dup.o \\\n\t\t  dup2.o execve.o fchdir.o fchflags.o fchmod.o fchown.o \\\n\t\t  fcntl.o flock.o fork.o fstat.o fsync.o ftruncate.o \\\n\t\t  getdtablesize.o getgroups.o getitimer.o getsockname.o \\\n\t\t  getpeername.o getpriority.o getrlimit.o getrusage.o getsockopt.o \\\n\t\t  gettimeofday.o ioctl.o kill.o killpg.o link.o listen.o lstat.o mkdir.o \\\n\t\t  mknod.o mount.o open.o pselect.o quota.o read.o readlink.o readv.o \\\n\t\t  reboot.o \\\n\t\t  recv.o recvfrom.o recvmsg.o rename.o rmdir.o select.o send.o sendmsg.o \\\n\t\t  sendto.o setgroups.o setitimer.o setpgrp.o setpriority.o setquota.o \\\n\t\t  setuid.o seteuid.o setgid.o setegid.o \\\n\t\t  setrlimit.o setsockopt.o settimeofday.o shutdown.o \\\n\t\t  sigaltstack.o socket.o socketpair.o stat.o symlink.o \\\n\t\t  sigprocmask.o sigstack.o sigwait.o \\\n\t\t  statfs.o fstatfs.o getfsstat.o \\\n\t\t  truncate.o umount.o unlink.o utimes.o wait4.o write.o writev.o \\\n\t\t  lseek.o sigsuspend.o \\\n\t\t  getgid.o getegid.o getpgrp.o getpid.o \\\n\t\t  getppid.o getuid.o geteuid.o profil.o sigpending.o sync.o \\\n                  ufetch.o ustore.o ucall.o umask.o vfork.o vhangup.o \\\n\t\t  rdglob.o wrglob.o msec.o kmemdev.o\n\nOBJS\t\t= ${COBJS} ${ASMOBJS} ${SYSOBJS}\n\nTAGSFILE\t= tags\n\nsys.a:\t\t${OBJS}\n\t\t@echo \"building sys.a\"\n\t\t@${AR} cr sys.a ${OBJS}\n\n${SYSOBJS}:\tSYS.h\n#\t\t@echo creating $*.o\n\t\t@printf '#include \"SYS.h\"\\nSYS($*)\\n' | $(AS) ${ASFLAGS} - -c -o $*.o\n\nclean:\n\t\trm -f *~ *.o a.out sys.a\n"
  },
  {
    "path": "lib/libc/mips/sys/SYS.h",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <syscall.h>\n\n#define\tENTRY(s)     s:\t.globl s; \\\n\t\t\t.type   s, @function\n\n#define\tSYS(s)\t\tENTRY(s); \\\n\t\t\t.set\tnoreorder; \\\n\t\t\tsyscall\tSYS_##s; \\\n\t\t\tlui\t$t1, %hi(errno); \\\n\t\t\tsw      $t0, %lo(errno)($t1); \\\n\t\t\t.set\treorder; \\\n\t\t\tjr\t$ra\n"
  },
  {
    "path": "lib/libc/mips/sys/_brk.S",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"SYS.h\"\n\nENTRY(_brk)\n\t\t.set\tnoreorder\n\t\tsyscall\tSYS_sbrk\n\t\tlui\t$t1, %hi(errno)\t\t# return here on error\n\t\tsw      $t0, %lo(errno)($t1)\n\t\t.set\treorder\n\n\t\tjr\t$ra\t\t\t# return here on success\n"
  },
  {
    "path": "lib/libc/mips/sys/_exit.S",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"SYS.h\"\n\nENTRY(_exit)\n\t\tsyscall\tSYS_exit\n"
  },
  {
    "path": "lib/libc/mips/sys/execl.c",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <unistd.h>\n\nextern char **environ;\n\nint\nexecl (const char *name, const char *arg, ...)\n{\n\treturn execve (name, (char *const*) &arg, environ);\n}\n"
  },
  {
    "path": "lib/libc/mips/sys/execle.c",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <unistd.h>\n#include <stdarg.h>\n\nint\nexecle (const char *name, const char *arg, ...)\n{\n\tva_list ap;\n\tchar **envp;\n\n\tva_start (ap, arg);\n\twhile ((va_arg (ap, char *)) != NULL)\n\t\tcontinue;\n\tenvp = va_arg (ap, char **);\n\tva_end (ap);\n\n\treturn execve (name, (char *const*) &arg, envp);\n}\n"
  },
  {
    "path": "lib/libc/mips/sys/execv.c",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <unistd.h>\n\nextern char **environ;\n\nint\nexecv (name, argv)\n\tconst char *name;\n\tchar *const *argv;\n{\n\treturn execve (name, argv, environ);\n}\n"
  },
  {
    "path": "lib/libc/mips/sys/pipe.S",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"SYS.h\"\n\nENTRY(pipe)\n\t\t.set\tnoreorder\n\t\tsyscall\tSYS_pipe\n\t\tj\t1f\t\t# return here on error\n\t\tnop\n\t\t.set\treorder\n\n\t\tsw\t$v0, 0($a0)\t# return here on success\n\t\tsw\t$v1, 4($a0)\n\t\tmove\t$v0, $zero\n\t\tjr\t$ra\n1:\n\t\tlui\t$t1, %hi(errno)\n\t\tsw      $t0, %lo(errno)($t1)\n\t\tjr\t$ra\n"
  },
  {
    "path": "lib/libc/mips/sys/ptrace.S",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"SYS.h\"\n\nENTRY(ptrace)\n\t\t# -1 is a legitimate return\n\t\t# value so we must clear errno\n\t\t# so the caller may disambiguate\n\t\tlui\t$t1, %hi(errno)\n\t\tsw      $zero, %lo(errno)($t1)\n\n\t\t.set\tnoreorder\n\t\tsyscall\tSYS_ptrace\n\t\tlui\t$t1, %hi(errno)\t\t# return here on error\n\t\tsw      $t0, %lo(errno)($t1)\n\n\t\t.set\treorder\n\t\tjr\t$ra\t\t\t# return here on success\n"
  },
  {
    "path": "lib/libc/mips/sys/sbrk.c",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <unistd.h>\n\nextern char _end[];\nconst char *_curbrk = _end;\n\nvoid *\nsbrk (incr)\n\tint incr;\n{\n\tvoid *oldbrk = (void*) _curbrk;\n\n\tif (incr != 0) {\n\t\t/* calculate and pass break address */\n\t\tconst void *addr = _curbrk + incr;\n\t\tif (_brk (addr) != -1) {\n\t\t\t/* add increment to curbrk */\n\t\t\t_curbrk = addr;\n\t\t}\n\t}\n\t/* return old break address */\n\treturn oldbrk;\n}\n\nvoid *\nbrk (addr)\n\tconst void *addr;\n{\n\tint ret;\n\n\tif (addr < (void*) _end)\t/* break request too low? */\n\t\taddr = _end;\t\t/* yes, knock the request up to _end */\n\tret = _brk (addr);\t\t/* ask for break */\n\tif (ret != -1)\n\t\t_curbrk = addr;\t\t/* and remember it if it succeeded */\n\treturn (void*) ret;\n}\n"
  },
  {
    "path": "lib/libc/mips/sys/sigaction.S",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * error = sigaction(sig, vec, ovec)\n *\tint\t\terror, sig;\n *\tstruct sigaction *vec, *ovec;\n *\n * We pass one additional parameter to the sigaction sys call: the address of\n * the \"Trampoline Code\", sigtramp - the code that handles saving and restoring\n * register context and so on for signals.  On the VAX-11 under BSD4.3 it isn't\n * necessary to pass this address since the trampoline code is stored in the\n * user structure in u.u_pcb.pcb_sigc at a known address in user space.  It\n * really doesn't introduce much extra overhead, so our method for doing it on\n * a PDP-11 is alright too.\n */\n#include \"SYS.h\"\n\nENTRY(sigaction)\n                la      $a3, sigtramp           # arg4: address of sigtramp\n\n\t\t.set\tnoreorder\n\t\tsyscall\tSYS_sigaction\n\t\tlui\t$t1, %hi(errno)\t\t# return here on error\n\t\tsw      $t0, %lo(errno)($t1)\n\t\t.set\treorder\n\n\t\tjr\t$ra\t\t\t# return here on success\n\n/*\n * sigtramp - Signal \"Trampoline Code\"\n *\n * This code is transfered to by the kernel when a signal is delivered to a\n * process.  In general, the idea is that sigtramp saves the process' register\n * context and then vectors on to the real signal action routine.  Upon return\n * from the signal action routine sigtramp restores the process' register\n * context and performs a sigreturn.\n *\n * In the case of the PDP-11, the kernel will have already saved r0 and r1 for\n * sigtramp in a sigcontext structure it passes to us.  Sigtramp vectors onto\n * the signal action routine whose address has been left in r0 by the kernel\n * (sigtramp assumes the signal action routine will save any other registers\n * it uses (as all C routines will)).  Upon return from the signal action\n * routine, sigtramp will execute a sigreturn with the sigcontext structure\n * given to us by the kernel.\n *\n * When the kernel transfers control to sigtramp the stack looks like:\n *\n *\t-------------------------\n *\t| sigcontext structure\t| SIG_SC = sp + 8\n *\t|-----------------------|\n *\t| unused\t\t|\n *\t|-----------------------|\n *\t| $a2: ptr to sigcontext|\n *\t|-----------------------|\n *\t| $a1: code\t\t|\n *\t|-----------------------|\n *sp ->\t| $a0: signal number\t|\n *\t-------------------------\n *\n * The important features of this as far as sigtramp is concerned are:\n * 1.\tThe fact that the signal number, signal code, and signal context\n *\tpointer are already set up as parameters to the signal action\n *\troutine.\n * 2.   There's no need to save r0 & r1 because the kernel's already saved\n *      them for us in the sigcontext structure (C routines save all\n *      registers except r0 & r1 automatically).\n *\n * Note that the stack offset SIG_SC will NOT have to be recomputed if the\n * sigcontext structure changes.\n */\nsigtramp:\n                syscall\tSYS_sigreturn\t\t# attempt the sigreturn\n                syscall\tSYS_exit\t\t# die if the sigreturn fails ...\n"
  },
  {
    "path": "lib/libc/net/Makefile",
    "content": "#\n# Copyright (c) 1988 Regents of the University of California.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms are permitted\n# provided that this notice is preserved and that due credit is given\n# to the University of California at Berkeley. The name of the University\n# may not be used to endorse or promote products derived from this\n# software without specific prior written permission. This software\n# is provided ``as is'' without express or implied warranty.\n#\n#\t@(#)Makefile\t5.16 (Berkeley) 3/14/88\n#\nSRCS=\tgetnbyaddr.c getnbyname.c getnent.c getpent.c getpname.c\t\\\n\tgetproto.c getsbyname.c getsbyport.c getsent.c herror.c \t\\\n\trcmd.c res_comp.c res_debug.c res_init.c res_mkquery.c\t\t\\\n\tres_query.c res_send.c\t\\\n\trexec.c ruserpass.c\n\nOBJS=\tgetnbyaddr.o getnbyname.o getnent.o getpent.o getpname.o\t\\\n\tgetproto.o getsbyname.o getsbyport.o getsent.o rcmd.o herror.o\t\\\n\trcmd.o res_comp.o res_debug.o res_init.o res_mkquery.o\t\t\\\n\tres_query.o res_send.o rexec.o ruserpass.o\n\nCFLAGS+= ${DEFS}\nTAGSFILE=tags\n\n.c.o:\n\t${CC} -p -c ${CFLAGS} $*.c\n\t-ld -X -r $*.o\n\tmv a.out profiled/$*.o\n\t${CC} ${CFLAGS} -c $*.c\n\t-ld -x -r $*.o\n\tmv a.out $*.o\n\nnetlib netlib_p: ${OBJS}\n\t@echo \"building profiled netlib\"\n\t@cd profiled; ${AR} cr ../netlib_p ${OBJS}\n\t@echo \"building normal netlib\"\n\t@${AR} cr netlib ${OBJS}\n\ntags:\n\tcwd=`pwd`; \\\n\tfor i in ${SRCS}; do \\\n\t\tctags -a -f ${TAGSFILE} $$cwd/$$i; \\\n\tdone\n\nclean:\n\trm -f *.o profiled/*.o errs a.out core netlib netlib_p tags\n\ndepend:\n\tmkdep ${CFLAGS} ${SRCS}\n\n# DO NOT DELETE THIS LINE -- mkdep uses it.\n# DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY.\n\ngetnbyaddr.o: getnbyaddr.c /usr/include/netdb.h\ngetnbyname.o: getnbyname.c /usr/include/netdb.h\ngetnent.o: getnent.c /usr/include/stdio.h /usr/include/sys/types.h\ngetnent.o: /usr/include/sys/socket.h /usr/include/arpa/inet.h\ngetnent.o: /usr/include/netdb.h /usr/include/ctype.h\ngetpent.o: getpent.c /usr/include/stdio.h /usr/include/sys/types.h\ngetpent.o: /usr/include/sys/socket.h /usr/include/netdb.h /usr/include/ctype.h\ngetpname.o: getpname.c /usr/include/netdb.h\ngetproto.o: getproto.c /usr/include/netdb.h\ngetsbyname.o: getsbyname.c /usr/include/netdb.h\ngetsbyport.o: getsbyport.c /usr/include/netdb.h\ngetsent.o: getsent.c /usr/include/stdio.h /usr/include/sys/types.h\ngetsent.o: /usr/include/sys/socket.h /usr/include/netinet/in.h\ngetsent.o: /usr/include/netdb.h /usr/include/ctype.h\nherror.o: herror.c /usr/include/sys/types.h /usr/include/sys/uio.h\nrcmd.o: rcmd.c /usr/include/stdio.h /usr/include/ctype.h /usr/include/pwd.h\nrcmd.o: /usr/include/sys/param.h /usr/include/sys/localopts.h\nrcmd.o: /usr/include/machine/machparam.h /usr/include/sys/types.h\nrcmd.o: /usr/include/signal.h /usr/include/sys/types.h /usr/include/sys/file.h\nrcmd.o: /usr/include/sys/signal.h /usr/include/sys/socket.h\nrcmd.o: /usr/include/sys/stat.h /usr/include/netinet/in.h /usr/include/netdb.h\nrcmd.o: /usr/include/errno.h\nres_comp.o: res_comp.c /usr/include/sys/types.h /usr/include/stdio.h\nres_comp.o: /usr/include/arpa/nameser.h\nres_debug.o: res_debug.c /usr/include/sys/types.h /usr/include/netinet/in.h\nres_debug.o: /usr/include/stdio.h /usr/include/arpa/nameser.h\nres_init.o: res_init.c /usr/include/sys/types.h /usr/include/sys/socket.h\nres_init.o: /usr/include/netinet/in.h /usr/include/stdio.h\nres_init.o: /usr/include/arpa/nameser.h /usr/include/resolv.h\nres_mkquery.o: res_mkquery.c /usr/include/stdio.h /usr/include/sys/types.h\nres_mkquery.o: /usr/include/netinet/in.h /usr/include/arpa/nameser.h\nres_mkquery.o: /usr/include/resolv.h\nres_query.o: res_query.c /usr/include/sys/param.h /usr/include/sys/localopts.h\nres_query.o: /usr/include/machine/machparam.h /usr/include/sys/types.h\nres_query.o: /usr/include/signal.h /usr/include/sys/types.h\nres_query.o: /usr/include/sys/socket.h /usr/include/netinet/in.h\nres_query.o: /usr/include/ctype.h /usr/include/netdb.h /usr/include/stdio.h\nres_query.o: /usr/include/errno.h /usr/include/strings.h\nres_query.o: /usr/include/arpa/inet.h /usr/include/arpa/nameser.h\nres_query.o: /usr/include/resolv.h\nres_send.o: res_send.c /usr/include/sys/param.h /usr/include/sys/localopts.h\nres_send.o: /usr/include/machine/machparam.h /usr/include/sys/types.h\nres_send.o: /usr/include/signal.h /usr/include/sys/types.h\nres_send.o: /usr/include/sys/time.h /usr/include/time.h\nres_send.o: /usr/include/sys/socket.h /usr/include/sys/uio.h\nres_send.o: /usr/include/netinet/in.h /usr/include/stdio.h /usr/include/errno.h\nres_send.o: /usr/include/arpa/nameser.h /usr/include/resolv.h\nrexec.o: rexec.c /usr/include/sys/types.h /usr/include/sys/socket.h\nrexec.o: /usr/include/netinet/in.h /usr/include/stdio.h /usr/include/netdb.h\nrexec.o: /usr/include/errno.h\nruserpass.o: ruserpass.c /usr/include/stdio.h /usr/include/utmp.h\nruserpass.o: /usr/include/ctype.h /usr/include/sys/types.h\nruserpass.o: /usr/include/sys/stat.h /usr/include/errno.h\n\n# IF YOU PUT ANYTHING HERE IT WILL GO AWAY\n"
  },
  {
    "path": "lib/libc/net/getnbyaddr.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)getnetbyaddr.c\t5.3 (Berkeley) 5/19/86\";\n#endif LIBC_SCCS and not lint\n\n#include <netdb.h>\n\nextern int _net_stayopen;\n\nstruct netent *\ngetnetbyaddr(net, type)\n\tregister long net;\n\tregister int type;\n{\n\tregister struct netent *p;\n\n\tsetnetent(_net_stayopen);\n\twhile (p = getnetent())\n\t\tif (p->n_addrtype == type && p->n_net == net)\n\t\t\tbreak;\n\tif (!_net_stayopen)\n\t\tendnetent();\n\treturn (p);\n}\n"
  },
  {
    "path": "lib/libc/net/getnbyname.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)getnetbyname.c\t5.3 (Berkeley) 5/19/86\";\n#endif LIBC_SCCS and not lint\n\n#include <netdb.h>\n\nextern int _net_stayopen;\n\nstruct netent *\ngetnetbyname(name)\n\tregister char *name;\n{\n\tregister struct netent *p;\n\tregister char **cp;\n\n\tsetnetent(_net_stayopen);\n\twhile (p = getnetent()) {\n\t\tif (strcmp(p->n_name, name) == 0)\n\t\t\tbreak;\n\t\tfor (cp = p->n_aliases; *cp != 0; cp++)\n\t\t\tif (strcmp(*cp, name) == 0)\n\t\t\t\tgoto found;\n\t}\nfound:\n\tif (!_net_stayopen)\n\t\tendnetent();\n\treturn (p);\n}\n"
  },
  {
    "path": "lib/libc/net/getnent.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)getnetent.c\t5.3 (Berkeley) 5/19/86\";\n#endif LIBC_SCCS and not lint\n\n#include <stdio.h>\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <arpa/inet.h>\n#include <netdb.h>\n#include <ctype.h>\n\n#define\tMAXALIASES\t35\n\nstatic char NETDB[] = \"/etc/networks\";\nstatic FILE *netf = NULL;\nstatic char line[256+1];\nstatic struct netent net;\nstatic char *net_aliases[MAXALIASES];\nint _net_stayopen;\nstatic char *any();\n\nsetnetent(f)\n\tint f;\n{\n\tif (netf == NULL)\n\t\tnetf = fopen(NETDB, \"r\" );\n\telse\n\t\trewind(netf);\n\t_net_stayopen |= f;\n}\n\nendnetent()\n{\n\tif (netf) {\n\t\tfclose(netf);\n\t\tnetf = NULL;\n\t}\n\t_net_stayopen = 0;\n}\n\nstruct netent *\ngetnetent()\n{\n\tchar *p;\n\tregister char *cp, **q;\n\n\tif (netf == NULL && (netf = fopen(NETDB, \"r\" )) == NULL)\n\t\treturn (NULL);\nagain:\n\tp = fgets(line, sizeof(line)-1, netf);\n\tif (p == NULL)\n\t\treturn (NULL);\n\tif (*p == '#')\n\t\tgoto again;\n\tcp = any(p, \"#\\n\");\n\tif (cp == NULL)\n\t\tgoto again;\n\t*cp = '\\0';\n\tnet.n_name = p;\n\tcp = any(p, \" \\t\");\n\tif (cp == NULL)\n\t\tgoto again;\n\t*cp++ = '\\0';\n\twhile (*cp == ' ' || *cp == '\\t')\n\t\tcp++;\n\tp = any(cp, \" \\t\");\n\tif (p != NULL)\n\t\t*p++ = '\\0';\n\tnet.n_net = inet_network(cp);\n\tnet.n_addrtype = AF_INET;\n\tq = net.n_aliases = net_aliases;\n\tif (p != NULL) \n\t\tcp = p;\n\twhile (cp && *cp) {\n\t\tif (*cp == ' ' || *cp == '\\t') {\n\t\t\tcp++;\n\t\t\tcontinue;\n\t\t}\n\t\tif (q < &net_aliases[MAXALIASES - 1])\n\t\t\t*q++ = cp;\n\t\tcp = any(cp, \" \\t\");\n\t\tif (cp != NULL)\n\t\t\t*cp++ = '\\0';\n\t}\n\t*q = NULL;\n\treturn (&net);\n}\n\nstatic char *\nany(cp, match)\n\tregister char *cp;\n\tchar *match;\n{\n\tregister char *mp, c;\n\n\twhile (c = *cp) {\n\t\tfor (mp = match; *mp; mp++)\n\t\t\tif (*mp == c)\n\t\t\t\treturn (cp);\n\t\tcp++;\n\t}\n\treturn ((char *)0);\n}\n"
  },
  {
    "path": "lib/libc/net/getpent.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)getprotoent.c\t5.3 (Berkeley) 5/19/86\";\n#endif LIBC_SCCS and not lint\n\n#include <stdio.h>\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <netdb.h>\n#include <ctype.h>\n\n#define\tMAXALIASES\t35\n\nstatic char PROTODB[] = \"/etc/protocols\";\nstatic FILE *protof = NULL;\nstatic char line[256+1];\nstatic struct protoent proto;\nstatic char *proto_aliases[MAXALIASES];\nstatic char *any();\nint _proto_stayopen;\n\nsetprotoent(f)\n\tint f;\n{\n\tif (protof == NULL)\n\t\tprotof = fopen(PROTODB, \"r\" );\n\telse\n\t\trewind(protof);\n\t_proto_stayopen |= f;\n}\n\nendprotoent()\n{\n\tif (protof) {\n\t\tfclose(protof);\n\t\tprotof = NULL;\n\t}\n\t_proto_stayopen = 0;\n}\n\nstruct protoent *\ngetprotoent()\n{\n\tchar *p;\n\tregister char *cp, **q;\n\n\tif (protof == NULL && (protof = fopen(PROTODB, \"r\" )) == NULL)\n\t\treturn (NULL);\nagain:\n\tif ((p = fgets(line, sizeof(line)-1, protof)) == NULL)\n\t\treturn (NULL);\n\tif (*p == '#')\n\t\tgoto again;\n\tcp = any(p, \"#\\n\");\n\tif (cp == NULL)\n\t\tgoto again;\n\t*cp = '\\0';\n\tproto.p_name = p;\n\tcp = any(p, \" \\t\");\n\tif (cp == NULL)\n\t\tgoto again;\n\t*cp++ = '\\0';\n\twhile (*cp == ' ' || *cp == '\\t')\n\t\tcp++;\n\tp = any(cp, \" \\t\");\n\tif (p != NULL)\n\t\t*p++ = '\\0';\n\tproto.p_proto = atoi(cp);\n\tq = proto.p_aliases = proto_aliases;\n\tif (p != NULL) {\n\t\tcp = p;\n\t\twhile (cp && *cp) {\n\t\t\tif (*cp == ' ' || *cp == '\\t') {\n\t\t\t\tcp++;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (q < &proto_aliases[MAXALIASES - 1])\n\t\t\t\t*q++ = cp;\n\t\t\tcp = any(cp, \" \\t\");\n\t\t\tif (cp != NULL)\n\t\t\t\t*cp++ = '\\0';\n\t\t}\n\t}\n\t*q = NULL;\n\treturn (&proto);\n}\n\nstatic char *\nany(cp, match)\n\tregister char *cp;\n\tchar *match;\n{\n\tregister char *mp, c;\n\n\twhile (c = *cp) {\n\t\tfor (mp = match; *mp; mp++)\n\t\t\tif (*mp == c)\n\t\t\t\treturn (cp);\n\t\tcp++;\n\t}\n\treturn ((char *)0);\n}\n"
  },
  {
    "path": "lib/libc/net/getpname.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)getprotoname.c\t5.3 (Berkeley) 5/19/86\";\n#endif LIBC_SCCS and not lint\n\n#include <netdb.h>\n\nextern int _proto_stayopen;\n\nstruct protoent *\ngetprotobyname(name)\n\tregister char *name;\n{\n\tregister struct protoent *p;\n\tregister char **cp;\n\n\tsetprotoent(_proto_stayopen);\n\twhile (p = getprotoent()) {\n\t\tif (strcmp(p->p_name, name) == 0)\n\t\t\tbreak;\n\t\tfor (cp = p->p_aliases; *cp != 0; cp++)\n\t\t\tif (strcmp(*cp, name) == 0)\n\t\t\t\tgoto found;\n\t}\nfound:\n\tif (!_proto_stayopen)\n\t\tendprotoent();\n\treturn (p);\n}\n"
  },
  {
    "path": "lib/libc/net/getproto.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)getproto.c\t5.3 (Berkeley) 5/19/86\";\n#endif LIBC_SCCS and not lint\n\n#include <netdb.h>\n\nextern int _proto_stayopen;\n\nstruct protoent *\ngetprotobynumber(proto)\n\tregister int proto;\n{\n\tregister struct protoent *p;\n\n\tsetprotoent(_proto_stayopen);\n\twhile (p = getprotoent())\n\t\tif (p->p_proto == proto)\n\t\t\tbreak;\n\tif (!_proto_stayopen)\n\t\tendprotoent();\n\treturn (p);\n}\n"
  },
  {
    "path": "lib/libc/net/getsbyname.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)getservbyname.c\t5.3 (Berkeley) 5/19/86\";\n#endif LIBC_SCCS and not lint\n\n#include <netdb.h>\n\nextern int _serv_stayopen;\n\nstruct servent *\ngetservbyname(name, proto)\n\tchar *name, *proto;\n{\n\tregister struct servent *p;\n\tregister char **cp;\n\n\tsetservent(_serv_stayopen);\n\twhile (p = getservent()) {\n\t\tif (strcmp(name, p->s_name) == 0)\n\t\t\tgoto gotname;\n\t\tfor (cp = p->s_aliases; *cp; cp++)\n\t\t\tif (strcmp(name, *cp) == 0)\n\t\t\t\tgoto gotname;\n\t\tcontinue;\ngotname:\n\t\tif (proto == 0 || strcmp(p->s_proto, proto) == 0)\n\t\t\tbreak;\n\t}\n\tif (!_serv_stayopen)\n\t\tendservent();\n\treturn (p);\n}\n"
  },
  {
    "path": "lib/libc/net/getsbyport.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)getservbyport.c\t5.3 (Berkeley) 5/19/86\";\n#endif LIBC_SCCS and not lint\n\n#include <netdb.h>\n\nextern int _serv_stayopen;\n\nstruct servent *\ngetservbyport(port, proto)\n\tint port;\n\tchar *proto;\n{\n\tregister struct servent *p;\n\n\tsetservent(_serv_stayopen);\n\twhile (p = getservent()) {\n\t\tif (p->s_port != port)\n\t\t\tcontinue;\n\t\tif (proto == 0 || strcmp(p->s_proto, proto) == 0)\n\t\t\tbreak;\n\t}\n\tif (!_serv_stayopen)\n\t\tendservent();\n\treturn (p);\n}\n"
  },
  {
    "path": "lib/libc/net/getsent.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)getservent.c\t5.3.1 (2.11BSD GTE) 6/27/94\";\n#endif LIBC_SCCS and not lint\n\n#include <stdio.h>\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <netinet/in.h>\n#include <netdb.h>\n#include <ctype.h>\n\n#define\tMAXALIASES\t16\n\nstatic char SERVDB[] = \"/etc/services\";\nstatic FILE *servf = NULL;\nstatic char line[160+1];\nstatic struct servent serv;\nstatic char *serv_aliases[MAXALIASES];\nstatic char *any();\nint _serv_stayopen;\n\nsetservent(f)\n\tint f;\n{\n\tif (servf == NULL)\n\t\tservf = fopen(SERVDB, \"r\" );\n\telse\n\t\trewind(servf);\n\t_serv_stayopen |= f;\n}\n\nendservent()\n{\n\tif (servf) {\n\t\tfclose(servf);\n\t\tservf = NULL;\n\t}\n\t_serv_stayopen = 0;\n}\n\nstruct servent *\ngetservent()\n{\n\tchar *p;\n\tregister char *cp, **q;\n\n\tif (servf == NULL && (servf = fopen(SERVDB, \"r\" )) == NULL)\n\t\treturn (NULL);\nagain:\n\tif ((p = fgets(line, sizeof(line)-1, servf)) == NULL)\n\t\treturn (NULL);\n\tif (*p == '#')\n\t\tgoto again;\n\tcp = any(p, \"#\\n\");\n\tif (cp == NULL)\n\t\tgoto again;\n\t*cp = '\\0';\n\tserv.s_name = p;\n\tp = any(p, \" \\t\");\n\tif (p == NULL)\n\t\tgoto again;\n\t*p++ = '\\0';\n\twhile (*p == ' ' || *p == '\\t')\n\t\tp++;\n\tcp = any(p, \",/\");\n\tif (cp == NULL)\n\t\tgoto again;\n\t*cp++ = '\\0';\n\tserv.s_port = htons((u_short)atoi(p));\n\tserv.s_proto = cp;\n\tq = serv.s_aliases = serv_aliases;\n\tcp = any(cp, \" \\t\");\n\tif (cp != NULL)\n\t\t*cp++ = '\\0';\n\twhile (cp && *cp) {\n\t\tif (*cp == ' ' || *cp == '\\t') {\n\t\t\tcp++;\n\t\t\tcontinue;\n\t\t}\n\t\tif (q < &serv_aliases[MAXALIASES - 1])\n\t\t\t*q++ = cp;\n\t\tcp = any(cp, \" \\t\");\n\t\tif (cp != NULL)\n\t\t\t*cp++ = '\\0';\n\t}\n\t*q = NULL;\n\treturn (&serv);\n}\n\nstatic char *\nany(cp, match)\n\tregister char *cp;\n\tchar *match;\n{\n\tregister char *mp, c;\n\n\twhile (c = *cp) {\n\t\tfor (mp = match; *mp; mp++)\n\t\t\tif (*mp == c)\n\t\t\t\treturn (cp);\n\t\tcp++;\n\t}\n\treturn ((char *)0);\n}\n"
  },
  {
    "path": "lib/libc/net/herror.c",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)herror.c\t6.1 (Berkeley) 12/4/87\";\n#endif LIBC_SCCS and not lint\n\n#include <sys/types.h>\n#include <sys/uio.h>\n\nchar\t*h_errlist[] = {\n\t\"Error 0\",\n\t\"Unknown host\",\t\t\t\t/* 1 HOST_NOT_FOUND */\n\t\"Host name lookup failure\",\t\t/* 2 TRY_AGAIN */\n\t\"Unknown server error\",\t\t\t/* 3 NO_RECOVERY */\n\t\"No address associated with name\",\t/* 4 NO_ADDRESS */\n};\nint\th_nerr = { sizeof(h_errlist)/sizeof(h_errlist[0]) };\n\nextern int\th_errno;\n\n/*\n * herror --\n *\tprint the error indicated by the h_errno value.\n */\nherror(s)\n\tchar *s;\n{\n\tstruct iovec iov[4];\n\tregister struct iovec *v = iov;\n\n\tif (s && *s) {\n\t\tv->iov_base = s;\n\t\tv->iov_len = strlen(s);\n\t\tv++;\n\t\tv->iov_base = \": \";\n\t\tv->iov_len = 2;\n\t\tv++;\n\t}\n\tv->iov_base = h_errno < h_nerr ? h_errlist[h_errno] : \"Unknown error\";\n\tv->iov_len = strlen(v->iov_base);\n\tv++;\n\tv->iov_base = \"\\n\";\n\tv->iov_len = 1;\n\twritev(2, iov, (v - iov) + 1);\n}\n"
  },
  {
    "path": "lib/libc/net/hosttable/Makefile",
    "content": "\n#\n# Copyright (c) 1983 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n#\t@(#)Makefile\t5.4 (Berkeley) 9/5/85\n#\n\nOBJS=\tgethnamadr.o gethostent.o\nSRCS=\tgethnamadr.c gethostent.c\nCFLAGS+=-O ${DEFS}\n\n.c.o: \n\t${CC} -p -c ${CFLAGS} $*.c\n\t-ld -X -r $*.o\n\tmv a.out profiled/$*.o\n\t${CC} ${CFLAGS} -c $*.c\n\t-ld -x -r $*.o\n\tmv a.out $*.o\n\nhostlib hostlib_p: ${OBJS} \n\t@echo \"building profiled hostlib\"\n\t@cd profiled; ${AR} cr ../hostlib_p ${OBJS}\n\t@echo \"building normal netlib\"\n\t@${AR} cr hostlib ${OBJS}\n\t\ntags:\n\tcwd=`pwd`; \\\n\tfor i in ${SRCS}; do \\\n\t\tctags -a -f ${TAGSFILE} $$cwd/$$i; \\\n\tdone\n\nclean:\n\trm -f *.o errs a.out core hostlib hostlib_p profiled/*.o \\\n\t\ttags Makefile.bak\n\ndepend:\n\tfor i in ${SRCS}; do \\\n\t    cc -M ${CFLAGS} $$i | awk ' { if ($$1 != prev) \\\n\t\t{ if (rec != \"\") print rec; rec = $$0; prev = $$1; } \\\n\t\telse { if (length(rec $$2) > 78) { print rec; rec = $$0; } \\\n\t\telse rec = rec \" \" $$2 } } \\\n\t\tEND { print rec } ' >> makedep; done\n\techo '/^# DO NOT DELETE THIS LINE/+2,$$d' >eddep\n\techo '$$r makedep' >>eddep\n\techo 'w' >>eddep\n\tcp Makefile Makefile.bak\n\ted - Makefile < eddep\n\trm eddep makedep\n\techo '# DEPENDENCIES MUST END AT END OF FILE' >> Makefile\n\techo '# IF YOU PUT STUFF HERE IT WILL GO AWAY' >> Makefile\n\techo '# see make depend above' >> Makefile\n\n# DO NOT DELETE THIS LINE -- make depend uses it\n\n"
  },
  {
    "path": "lib/libc/net/hosttable/gethnamadr.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)gethostnamadr.c\t5.5 (Berkeley) 3/9/86\";\n#endif LIBC_SCCS and not lint\n\n#include <stdio.h>\n#include <sys/types.h>\n#include <netdb.h>\n#include <sys/file.h>\n#include <ndbm.h>\n#include <ctype.h>\n\n#define\tMAXALIASES\t20\n#define\tMAXADDRS\t10\n\nstatic struct hostent host;\nstatic char hostbuf[256];\nstatic char *host_aliases[MAXALIASES];\nstatic char *host_addrs[MAXADDRS];\n\nint h_errno;\n\n/*\n * The following is shared with gethostent.c\n */\nextern\tchar *_host_file;\nDBM\t*_host_db = (DBM *)NULL;\nint\t_host_stayopen;\t/* set by sethostent(), cleared by endhostent() */\n\nstatic struct hostent *\nfetchhost(key)\n\tdatum key;\n{\n        register char *cp, *tp, **ap;\n\tint naliases, naddrs;\n\n        if (key.dptr == 0)\n                return ((struct hostent *)NULL);\n\tkey = dbm_fetch(_host_db, key);\n\tif (key.dptr == 0)\n                return ((struct hostent *)NULL);\n\tcp = key.dptr;\n        tp = hostbuf;\n\thost.h_name = tp;\n\twhile (*tp++ = *cp++)\n\t\t;\n\tbcopy(cp, (char *)&naliases, sizeof(int));\n\tcp += sizeof (int);\n\tfor (ap = host_aliases; naliases > 0; naliases--) {\n\t\t*ap++ = tp;\n\t\twhile (*tp++ = *cp++)\n\t\t\t;\n\t}\n\t*ap = (char *)NULL;\n\thost.h_aliases = host_aliases;\n\tbcopy(cp, (char *)&host.h_addrtype, sizeof (int));\n\tcp += sizeof (int);\n\tbcopy(cp, (char *)&host.h_length, sizeof (int));\n\tcp += sizeof (int);\n\thost.h_addr_list = host_addrs;\n\tnaddrs = (key.dsize - (cp - key.dptr)) / host.h_length;\n\tif (naddrs > MAXADDRS)\n\t\tnaddrs = MAXADDRS;\n\tfor (ap = host_addrs; naddrs; naddrs--) {\n\t\t*ap++ = tp;\n\t\tbcopy(cp, tp, host.h_length);\n\t\tcp += host.h_length;\n\t\ttp += host.h_length;\n\t}\n\t*ap = (char *)NULL;\n        return (&host);\n}\n\nstruct hostent *\ngethostbyname(nam)\n\tregister char *nam;\n{\n\tregister struct hostent *hp;\n\tregister char **cp;\n        datum key;\n\tchar lowname[128];\n\tregister char *lp = lowname;\n\t\n\twhile (*nam)\n\t\tif (isupper(*nam))\n\t\t\t*lp++ = tolower(*nam++);\n\t\telse\n\t\t\t*lp++ = *nam++;\n\t*lp = '\\0';\n\n\tif ((_host_db == (DBM *)NULL)\n\t  && ((_host_db = dbm_open(_host_file, O_RDONLY)) == (DBM *)NULL)) {\n\t\tsethostent(_host_stayopen);\n\t\twhile (hp = gethostent()) {\n\t\t\tif (strcmp(hp->h_name, lowname) == 0)\n\t\t\t\tbreak;\n\t\t\tfor (cp = hp->h_aliases; cp != 0 && *cp != 0; cp++)\n\t\t\t\tif (strcmp(*cp, lowname) == 0)\n\t\t\t\t\tgoto found;\n\t\t}\n\tfound:\n\t\tif (!_host_stayopen)\n\t\t\tendhostent();\n\t\treturn (hp);\n\t}\n        key.dptr = lowname;\n        key.dsize = strlen(lowname);\n\thp = fetchhost(key);\n\tif (!_host_stayopen) {\n\t\tdbm_close(_host_db);\n\t\t_host_db = (DBM *)NULL;\n\t}\n\tif ( hp == NULL)\n\t\th_errno = HOST_NOT_FOUND;\n        return (hp);\n}\n\nstruct hostent *\ngethostbyaddr(addr, length, type)\n\tchar *addr;\n\tregister int length;\n\tregister int type;\n{\n\tregister struct hostent *hp;\n        datum key;\n\n\tif ((_host_db == (DBM *)NULL)\n\t  && ((_host_db = dbm_open(_host_file, O_RDONLY)) == (DBM *)NULL)) {\n\t\tsethostent(_host_stayopen);\n\t\twhile (hp = gethostent()) {\n\t\t\tif (hp->h_addrtype == type && hp->h_length == length\n\t\t\t    && bcmp(hp->h_addr, addr, length) == 0)\n\t\t\t\tbreak;\n\t\t}\n\t\tif (!_host_stayopen)\n\t\t\tendhostent();\n\t\tif ( hp == NULL)\n\t\t\th_errno = HOST_NOT_FOUND;\n\t\treturn (hp);\n\t}\n        key.dptr = addr;\n        key.dsize = length;\n\thp = fetchhost(key);\n\tif (!_host_stayopen) {\n\t\tdbm_close(_host_db);\n\t\t_host_db = (DBM *)NULL;\n\t}\n\tif ( hp == NULL)\n\t\th_errno = HOST_NOT_FOUND;\n        return (hp);\n}\n"
  },
  {
    "path": "lib/libc/net/hosttable/gethostent.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)gethostent.c\t5.3 (Berkeley) 3/9/86\";\n#endif LIBC_SCCS and not lint\n\n#include <stdio.h>\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <arpa/inet.h>\n#include <netdb.h>\n#include <ctype.h>\n#include <ndbm.h>\n\n/*\n * Internet version.\n */\n#define\tMAXALIASES\t20\n#define\tMAXADDRSIZE\t(sizeof (u_long))\n\nstatic FILE *hostf = NULL;\nstatic char line[160+1];\nstatic char hostaddr[MAXADDRSIZE];\nstatic struct hostent host;\nstatic char *host_aliases[MAXALIASES];\nstatic char *host_addrs[] = {\n\thostaddr,\n\tNULL\n};\n\n/*\n * The following is shared with gethostnamadr.c\n */\nchar\t*_host_file = \"/etc/hosts\";\nint\t_host_stayopen;\nDBM\t*_host_db;\t/* set by gethostbyname(), gethostbyaddr() */\n\nstatic char *any();\n\nsethostent(f)\n\tint f;\n{\n\tif (hostf != NULL)\n\t\trewind(hostf);\n\t_host_stayopen |= f;\n}\n\nendhostent()\n{\n\tif (hostf) {\n\t\tfclose(hostf);\n\t\thostf = NULL;\n\t}\n\tif (_host_db) {\n\t\tdbm_close(_host_db);\n\t\t_host_db = (DBM *)NULL;\n\t}\n\t_host_stayopen = 0;\n}\n\nstruct hostent *\ngethostent()\n{\n\tchar *p;\n\tregister char *cp, **q;\n\n\tif (hostf == NULL && (hostf = fopen(_host_file, \"r\" )) == NULL)\n\t\treturn (NULL);\nagain:\n\tif ((p = fgets(line, sizeof(line)-1, hostf)) == NULL)\n\t\treturn (NULL);\n\tif (*p == '#')\n\t\tgoto again;\n\tcp = any(p, \"#\\n\");\n\tif (cp == NULL)\n\t\tgoto again;\n\t*cp = '\\0';\n\tcp = any(p, \" \\t\");\n\tif (cp == NULL)\n\t\tgoto again;\n\t*cp++ = '\\0';\n\t/* THIS STUFF IS INTERNET SPECIFIC */\n\thost.h_addr_list = host_addrs;\n\t*((u_long *)host.h_addr) = inet_addr(p);\n\thost.h_length = sizeof (u_long);\n\thost.h_addrtype = AF_INET;\n\twhile (*cp == ' ' || *cp == '\\t')\n\t\tcp++;\n\thost.h_name = cp;\n\tq = host.h_aliases = host_aliases;\n\tcp = any(cp, \" \\t\");\n\tif (cp != NULL) \n\t\t*cp++ = '\\0';\n\twhile (cp && *cp) {\n\t\tif (*cp == ' ' || *cp == '\\t') {\n\t\t\tcp++;\n\t\t\tcontinue;\n\t\t}\n\t\tif (q < &host_aliases[MAXALIASES - 1])\n\t\t\t*q++ = cp;\n\t\tcp = any(cp, \" \\t\");\n\t\tif (cp != NULL)\n\t\t\t*cp++ = '\\0';\n\t}\n\t*q = NULL;\n\treturn (&host);\n}\n\nsethostfile(file)\n\tchar *file;\n{\n\t_host_file = file;\n}\n\nstatic char *\nany(cp, match)\n\tregister char *cp;\n\tchar *match;\n{\n\tregister char *mp, c;\n\n\twhile (c = *cp) {\n\t\tfor (mp = match; *mp; mp++)\n\t\t\tif (*mp == c)\n\t\t\t\treturn (cp);\n\t\tcp++;\n\t}\n\treturn ((char *)0);\n}\n"
  },
  {
    "path": "lib/libc/net/named/Makefile",
    "content": "#\n# Copyright (c) 1983 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n#\t@(#)Makefile\t6.4 (Berkeley) 6/6/87\n#\n\nOBJS=\tgethnamadr.o sethostent.o\n\nSRCS=\tgethnamadr.c sethostent.c\n\nCFLAGS+=-O ${DEFS}\nTAGSFILE= tags\n\n.c.o:\n\t${CC} -p -c ${CFLAGS} $*.c\n\t-ld -X -r $*.o\n\tmv a.out profiled/$*.o\n\t${CC} ${CFLAGS} -c $*.c\n\t-ld -x -r $*.o\n\tmv a.out $*.o\n\nhostlib hostlib_p: ${OBJS} \n\t@echo \"building profiled hostlib\"\n\t@cd profiled; ${AR} cr ../hostlib_p ${OBJS}\n\t@echo \"building normal hostlib\"\n\t@${AR} cr hostlib ${OBJS}\n\t\ntags:\n\tcwd=`pwd`; \\\n\tfor i in ${SRCS}; do \\\n\t\tctags -a -f ${TAGSFILE} $$cwd/$$i; \\\n\tdone\n\nclean:\n\trm -f *.o errs a.out core hostlib hostlib_p profiled/*.o tags\n\ndepend:\n\tmkdep ${CFLAGS} ${SRCS}\n\n# DO NOT DELETE THIS LINE -- mkdep uses it.\n# DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY.\n\ngethnamadr.o: gethnamadr.c /usr/include/sys/param.h\ngethnamadr.o: /usr/include/sys/localopts.h /usr/include/machine/machparam.h\ngethnamadr.o: /usr/include/sys/types.h /usr/include/signal.h\ngethnamadr.o: /usr/include/sys/types.h /usr/include/sys/socket.h\ngethnamadr.o: /usr/include/netinet/in.h /usr/include/ctype.h\ngethnamadr.o: /usr/include/netdb.h /usr/include/stdio.h /usr/include/errno.h\ngethnamadr.o: /usr/include/arpa/inet.h /usr/include/arpa/nameser.h\ngethnamadr.o: /usr/include/resolv.h\nsethostent.o: sethostent.c /usr/include/sys/types.h /usr/include/arpa/nameser.h\nsethostent.o: /usr/include/netinet/in.h /usr/include/resolv.h\n\n# IF YOU PUT ANYTHING HERE IT WILL GO AWAY\n"
  },
  {
    "path": "lib/libc/net/named/gethnamadr.c",
    "content": "/*\n * Copyright (c) 1985, 1988 Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that this notice is preserved and that due credit is given\n * to the University of California at Berkeley. The name of the University\n * may not be used to endorse or promote products derived from this\n * software without specific prior written permission. This software\n * is provided ``as is'' without express or implied warranty.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)gethostnamadr.c\t6.31.2 (2.11BSD GTE) 6/27/94\";\n#endif /* LIBC_SCCS and not lint */\n\n#include <sys/param.h>\n#include <sys/socket.h>\n#include <netinet/in.h>\n#include <ctype.h>\n#include <netdb.h>\n#include <stdio.h>\n#include <errno.h>\n#include <arpa/inet.h>\n#include <arpa/nameser.h>\n#include <resolv.h>\n\n#define\tMAXALIASES\t16\n#define\tMAXADDRS\t16\n\nstatic char *h_addr_ptrs[MAXADDRS + 1];\n\nstatic struct hostent host;\nstatic char *host_aliases[MAXALIASES];\nstatic char hostbuf[256+1];\nstatic struct in_addr host_addr;\nstatic char HOSTDB[] = \"/etc/hosts\";\nstatic FILE *hostf = NULL;\nstatic char hostaddr[MAXADDRS];\nstatic char *host_addrs[2];\nstatic int stayopen = 0;\nstatic char *any();\n\n#if PACKETSZ > 1024\n#define\tMAXPACKET\tPACKETSZ\n#else\n#define\tMAXPACKET\t1024\n#endif\n\ntypedef union {\n    HEADER hdr;\n    u_char buf[MAXPACKET];\n} querybuf;\n\nstatic union {\n    long al;\n    char ac;\n} align;\n\n\nint h_errno;\nextern errno;\n\nstatic struct hostent *\ngetanswer(answer, anslen, iquery)\n\tquerybuf *answer;\n\tint anslen;\n\tint iquery;\n{\n\tregister HEADER *hp;\n\tregister u_char *cp;\n\tregister int n;\n\tu_char *eom;\n\tchar *bp, **ap;\n\tint type, class, buflen, ancount, qdcount;\n\tint haveanswer, getclass = C_ANY;\n\tchar **hap;\n\n\teom = answer->buf + anslen;\n\t/*\n\t * find first satisfactory answer\n\t */\n\thp = &answer->hdr;\n\tancount = ntohs(hp->ancount);\n\tqdcount = ntohs(hp->qdcount);\n\tbp = hostbuf;\n\tbuflen = sizeof(hostbuf);\n\tcp = answer->buf + sizeof(HEADER);\n\tif (qdcount) {\n\t\tif (iquery) {\n\t\t\tif ((n = dn_expand((char *)answer->buf, eom,\n\t\t\t     cp, bp, buflen)) < 0) {\n\t\t\t\th_errno = NO_RECOVERY;\n\t\t\t\treturn ((struct hostent *) NULL);\n\t\t\t}\n\t\t\tcp += n + QFIXEDSZ;\n\t\t\thost.h_name = bp;\n\t\t\tn = strlen(bp) + 1;\n\t\t\tbp += n;\n\t\t\tbuflen -= n;\n\t\t} else\n\t\t\tcp += dn_skipname(cp, eom) + QFIXEDSZ;\n\t\twhile (--qdcount > 0)\n\t\t\tcp += dn_skipname(cp, eom) + QFIXEDSZ;\n\t} else if (iquery) {\n\t\tif (hp->aa)\n\t\t\th_errno = HOST_NOT_FOUND;\n\t\telse\n\t\t\th_errno = TRY_AGAIN;\n\t\treturn ((struct hostent *) NULL);\n\t}\n\tap = host_aliases;\n\thost.h_aliases = host_aliases;\n\thap = h_addr_ptrs;\n#if BSD >= 43 || defined(h_addr)\t/* new-style hostent structure */\n\thost.h_addr_list = h_addr_ptrs;\n#endif\n\thaveanswer = 0;\n\twhile (--ancount >= 0 && cp < eom) {\n\t\tif ((n = dn_expand((char *)answer->buf, eom, cp, bp, buflen)) < 0)\n\t\t\tbreak;\n\t\tcp += n;\n\t\ttype = _getshort(cp);\n \t\tcp += sizeof(u_short);\n\t\tclass = _getshort(cp);\n \t\tcp += sizeof(u_short) + sizeof(u_long);\n\t\tn = _getshort(cp);\n\t\tcp += sizeof(u_short);\n\t\tif (type == T_CNAME) {\n\t\t\tcp += n;\n\t\t\tif (ap >= &host_aliases[MAXALIASES-1])\n\t\t\t\tcontinue;\n\t\t\t*ap++ = bp;\n\t\t\tn = strlen(bp) + 1;\n\t\t\tbp += n;\n\t\t\tbuflen -= n;\n\t\t\tcontinue;\n\t\t}\n\t\tif (iquery && type == T_PTR) {\n\t\t\tif ((n = dn_expand((char *)answer->buf, eom,\n\t\t\t    cp, bp, buflen)) < 0) {\n\t\t\t\tcp += n;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tcp += n;\n\t\t\thost.h_name = bp;\n\t\t\treturn(&host);\n\t\t}\n\t\tif (iquery || type != T_A)  {\n#ifdef DEBUG\n\t\t\tif (_res.options & RES_DEBUG)\n\t\t\t\tprintf(\"unexpected answer type %d, size %d\\n\",\n\t\t\t\t\ttype, n);\n#endif\n\t\t\tcp += n;\n\t\t\tcontinue;\n\t\t}\n\t\tif (haveanswer) {\n\t\t\tif (n != host.h_length) {\n\t\t\t\tcp += n;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (class != getclass) {\n\t\t\t\tcp += n;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t} else {\n\t\t\thost.h_length = n;\n\t\t\tgetclass = class;\n\t\t\thost.h_addrtype = (class == C_IN) ? AF_INET : AF_UNSPEC;\n\t\t\tif (!iquery) {\n\t\t\t\thost.h_name = bp;\n\t\t\t\tbp += strlen(bp) + 1;\n\t\t\t}\n\t\t}\n\n\t\tbp += sizeof(align) - ((u_long)bp % sizeof(align));\n\n\t\tif (bp + n >= &hostbuf[sizeof(hostbuf)]) {\n#ifdef DEBUG\n\t\t\tif (_res.options & RES_DEBUG)\n\t\t\t\tprintf(\"size (%d) too big\\n\", n);\n#endif\n\t\t\tbreak;\n\t\t}\n\t\tbcopy(cp, *hap++ = bp, n);\n\t\tbp +=n;\n\t\tcp += n;\n\t\thaveanswer++;\n\t}\n\tif (haveanswer) {\n\t\t*ap = NULL;\n#if BSD >= 43 || defined(h_addr)\t/* new-style hostent structure */\n\t\t*hap = NULL;\n#else\n\t\thost.h_addr = h_addr_ptrs[0];\n#endif\n\t\treturn (&host);\n\t} else {\n\t\th_errno = TRY_AGAIN;\n\t\treturn ((struct hostent *) NULL);\n\t}\n}\n\nstruct hostent *\ngethostbyname(name)\n\tchar *name;\n{\n\tquerybuf buf;\n\tregister char *cp;\n\tint n;\n\tstruct hostent *hp, *gethostdomain();\n\textern struct hostent *_gethtbyname();\n\n\t/*\n\t * disallow names consisting only of digits/dots, unless\n\t * they end in a dot.\n\t */\n\tif (isdigit(name[0]))\n\t\tfor (cp = name;; ++cp) {\n\t\t\tif (!*cp) {\n\t\t\t\tif (*--cp == '.')\n\t\t\t\t\tbreak;\n\t\t\t\th_errno = HOST_NOT_FOUND;\n\t\t\t\treturn ((struct hostent *) NULL);\n\t\t\t}\n\t\t\tif (!isdigit(*cp) && *cp != '.') \n\t\t\t\tbreak;\n\t\t}\n\n\tif ((n = res_search(name, C_IN, T_A, buf.buf, sizeof(buf))) < 0) {\n#ifdef DEBUG\n\t\tif (_res.options & RES_DEBUG)\n\t\t\tprintf(\"res_search failed\\n\");\n#endif\n\t\tif (errno == ECONNREFUSED)\n\t\t\treturn (_gethtbyname(name));\n\t\telse\n\t\t\treturn ((struct hostent *) NULL);\n\t}\n\treturn (getanswer(&buf, n, 0));\n}\n\nstruct hostent *\ngethostbyaddr(addr, len, type)\n\tchar *addr;\n\tint len, type;\n{\n\tint n;\n\tquerybuf buf;\n\tregister struct hostent *hp;\n\tchar qbuf[MAXDNAME];\n\textern struct hostent *_gethtbyaddr();\n\t\n\tif (type != AF_INET)\n\t\treturn ((struct hostent *) NULL);\n\t(void)sprintf(qbuf, \"%d.%d.%d.%d.in-addr.arpa\",\n\t\t((unsigned)addr[3] & 0xff),\n\t\t((unsigned)addr[2] & 0xff),\n\t\t((unsigned)addr[1] & 0xff),\n\t\t((unsigned)addr[0] & 0xff));\n\tn = res_query(qbuf, C_IN, T_PTR, (char *)&buf, sizeof(buf));\n\tif (n < 0) {\n#ifdef DEBUG\n\t\tif (_res.options & RES_DEBUG)\n\t\t\tprintf(\"res_query failed\\n\");\n#endif\n\t\tif (errno == ECONNREFUSED)\n\t\t\thp = _gethtbyaddr(addr, len, type);\n\t\treturn ((struct hostent *) NULL);\n\t}\n\thp = getanswer(&buf, n, 1);\n\tif (hp == NULL)\n\t\treturn ((struct hostent *) NULL);\n\thp->h_addrtype = type;\n\thp->h_length = len;\n\th_addr_ptrs[0] = (char *)&host_addr;\n\th_addr_ptrs[1] = (char *)0;\n\thost_addr = *(struct in_addr *)addr;\n\treturn(hp);\n}\n\n_sethtent(f)\n\tint f;\n{\n\tif (hostf == NULL)\n\t\thostf = fopen(HOSTDB, \"r\" );\n\telse\n\t\trewind(hostf);\n\tstayopen |= f;\n}\n\n_endhtent()\n{\n\tif (hostf && !stayopen) {\n\t\t(void) fclose(hostf);\n\t\thostf = NULL;\n\t}\n}\n\nstruct hostent *\n_gethtent()\n{\n\tchar *p;\n\tregister char *cp, **q;\n\n\tif (hostf == NULL && (hostf = fopen(HOSTDB, \"r\" )) == NULL)\n\t\treturn (NULL);\nagain:\n\tif ((p = fgets(hostbuf, sizeof(hostbuf)-1, hostf)) == NULL)\n\t\treturn (NULL);\n\tif (*p == '#')\n\t\tgoto again;\n\tcp = any(p, \"#\\n\");\n\tif (cp == NULL)\n\t\tgoto again;\n\t*cp = '\\0';\n\tcp = any(p, \" \\t\");\n\tif (cp == NULL)\n\t\tgoto again;\n\t*cp++ = '\\0';\n\t/* THIS STUFF IS INTERNET SPECIFIC */\n#if BSD >= 43 || defined(h_addr)\t/* new-style hostent structure */\n\thost.h_addr_list = host_addrs;\n#endif\n\thost.h_addr = hostaddr;\n\t*((u_long *)host.h_addr) = inet_addr(p);\n\thost.h_length = sizeof (u_long);\n\thost.h_addrtype = AF_INET;\n\twhile (*cp == ' ' || *cp == '\\t')\n\t\tcp++;\n\thost.h_name = cp;\n\tq = host.h_aliases = host_aliases;\n\tcp = any(cp, \" \\t\");\n\tif (cp != NULL) \n\t\t*cp++ = '\\0';\n\twhile (cp && *cp) {\n\t\tif (*cp == ' ' || *cp == '\\t') {\n\t\t\tcp++;\n\t\t\tcontinue;\n\t\t}\n\t\tif (q < &host_aliases[MAXALIASES - 1])\n\t\t\t*q++ = cp;\n\t\tcp = any(cp, \" \\t\");\n\t\tif (cp != NULL)\n\t\t\t*cp++ = '\\0';\n\t}\n\t*q = NULL;\n\treturn (&host);\n}\n\nstatic char *\nany(cp, match)\n\tregister char *cp;\n\tchar *match;\n{\n\tregister char *mp, c;\n\n\twhile (c = *cp) {\n\t\tfor (mp = match; *mp; mp++)\n\t\t\tif (*mp == c)\n\t\t\t\treturn (cp);\n\t\tcp++;\n\t}\n\treturn ((char *)0);\n}\n\nstruct hostent *\n_gethtbyname(name)\n\tchar *name;\n{\n\tregister struct hostent *p;\n\tregister char **cp;\n\t\n\t_sethtent(0);\n\twhile (p = _gethtent()) {\n\t\tif (strcasecmp(p->h_name, name) == 0)\n\t\t\tbreak;\n\t\tfor (cp = p->h_aliases; *cp != 0; cp++)\n\t\t\tif (strcasecmp(*cp, name) == 0)\n\t\t\t\tgoto found;\n\t}\nfound:\n\t_endhtent();\n\treturn (p);\n}\n\nstruct hostent *\n_gethtbyaddr(addr, len, type)\n\tchar *addr;\n\tint len, type;\n{\n\tregister struct hostent *p;\n\n\t_sethtent(0);\n\twhile (p = _gethtent())\n\t\tif (p->h_addrtype == type && !bcmp(p->h_addr, addr, len))\n\t\t\tbreak;\n\t_endhtent();\n\treturn (p);\n}\n"
  },
  {
    "path": "lib/libc/net/named/sethostent.c",
    "content": "/*\n * Copyright (c) 1985 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)sethostent.c\t6.3 (Berkeley) 4/10/86\";\n#endif LIBC_SCCS and not lint\n\n#include <sys/types.h>\n#include <arpa/nameser.h>\n#include <netinet/in.h>\n#include <resolv.h>\n\nsethostent(stayopen)\n{\n\tif (stayopen)\n\t\t_res.options |= RES_STAYOPEN | RES_USEVC;\n}\n\nendhostent()\n{\n\t_res.options &= ~(RES_STAYOPEN | RES_USEVC);\n\t_res_close();\n}\n\nsethostfile(name)\nchar *name;\n{\n#ifdef lint\nname = name;\n#endif\n}\n"
  },
  {
    "path": "lib/libc/net/rcmd.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that the above copyright notice and this paragraph are\n * duplicated in all such forms and that any documentation,\n * advertising materials, and other materials related to such\n * distribution and use acknowledge that the software was developed\n * by the University of California, Berkeley.  The name of the\n * University may not be used to endorse or promote products derived\n * from this software without specific prior written permission.\n * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)rcmd.c\t5.20.1 (2.11BSD) 1999/10/24\";\n#endif /* LIBC_SCCS and not lint */\n\n#include <stdio.h>\n#include <ctype.h>\n#include <pwd.h>\n#include <string.h>\n#include <sys/param.h>\n#include <sys/file.h>\n#include <sys/signal.h>\n#include <sys/socket.h>\n#include <sys/stat.h>\n\n#include <netinet/in.h>\n\n#include <netdb.h>\n#include <errno.h>\n\nrcmd(ahost, rport, locuser, remuser, cmd, fd2p)\n\tchar **ahost;\n\tu_short rport;\n\tchar *locuser, *remuser, *cmd;\n\tint *fd2p;\n{\n\tint s, timo = 1, pid;\n\tsigset_t oldmask, nmask;\n\tstruct sockaddr_in sin, sin2, from;\n\tchar c;\n\tint lport = IPPORT_RESERVED - 1;\n\tstruct hostent *hp;\n\tfd_set reads;\n\n\tpid = getpid();\n\thp = gethostbyname(*ahost);\n\tif (hp == 0) {\n\t\therror(*ahost);\n\t\treturn (-1);\n\t}\n\t*ahost = hp->h_name;\n\t(void)sigemptyset(&nmask);\n\t(void)sigaddset(&nmask, SIGURG);\n\t(void)sigprocmask(SIG_BLOCK, &nmask, &oldmask);\n\n\tfor (;;) {\n\t\ts = rresvport(&lport);\n\t\tif (s < 0) {\n\t\t\tif (errno == EAGAIN)\n\t\t\t\tfprintf(stderr, \"socket: All ports in use\\n\");\n\t\t\telse\n\t\t\t\tperror(\"rcmd: socket\");\n\t\t\tsigprocmask(SIG_SETMASK, &oldmask, NULL);\n\t\t\treturn (-1);\n\t\t}\n\t\tfcntl(s, F_SETOWN, pid);\n\t\tsin.sin_family = hp->h_addrtype;\n\t\tbcopy(hp->h_addr_list[0], (caddr_t)&sin.sin_addr, hp->h_length);\n\t\tsin.sin_port = rport;\n\t\tif (connect(s, (caddr_t)&sin, sizeof (sin), 0) >= 0)\n\t\t\tbreak;\n\t\t(void) close(s);\n\t\tif (errno == EADDRINUSE) {\n\t\t\tlport--;\n\t\t\tcontinue;\n\t\t}\n\t\tif (errno == ECONNREFUSED && timo <= 16) {\n\t\t\tsleep(timo);\n\t\t\ttimo *= 2;\n\t\t\tcontinue;\n\t\t}\n\t\tif (hp->h_addr_list[1] != NULL) {\n\t\t\tint oerrno = errno;\n\n\t\t\tfprintf(stderr,\n\t\t\t    \"connect to address %s: \", inet_ntoa(sin.sin_addr));\n\t\t\terrno = oerrno;\n\t\t\tperror(0);\n\t\t\thp->h_addr_list++;\n\t\t\tbcopy(hp->h_addr_list[0], (caddr_t)&sin.sin_addr,\n\t\t\t    hp->h_length);\n\t\t\tfprintf(stderr, \"Trying %s...\\n\",\n\t\t\t\tinet_ntoa(sin.sin_addr));\n\t\t\tcontinue;\n\t\t}\n\t\tperror(hp->h_name);\n\t\tsigprocmask(SIG_SETMASK, &oldmask, NULL);\n\t\treturn (-1);\n\t}\n\tlport--;\n\tif (fd2p == 0) {\n\t\twrite(s, \"\", 1);\n\t\tlport = 0;\n\t} else {\n\t\tchar num[8];\n\t\tint s2 = rresvport(&lport), s3;\n\t\tint len = sizeof (from);\n\n\t\tif (s2 < 0)\n\t\t\tgoto bad;\n\t\tlisten(s2, 1);\n\t\t(void) sprintf(num, \"%d\", lport);\n\t\tif (write(s, num, strlen(num)+1) != strlen(num)+1) {\n\t\t\tperror(\"write: setting up stderr\");\n\t\t\t(void) close(s2);\n\t\t\tgoto bad;\n\t\t}\n\t\tFD_ZERO(&reads);\n\t\tFD_SET(s, &reads);\n\t\tFD_SET(s2, &reads);\n\t\terrno = 0;\n\t\tif (select(32, &reads, 0, 0, 0) < 1 ||\n\t\t    !FD_ISSET(s2, &reads)) {\n\t\t\tif (errno != 0)\n\t\t\t\tperror(\"select: setting up stderr\");\n\t\t\telse\n\t\t\t    fprintf(stderr,\n\t\t\t\t\"select: protocol failure in circuit setup.\\n\");\n\t\t\t(void) close(s2);\n\t\t\tgoto bad;\n\t\t}\n\t\ts3 = accept(s2, &from, &len, 0);\n\t\t(void) close(s2);\n\t\tif (s3 < 0) {\n\t\t\tperror(\"accept\");\n\t\t\tlport = 0;\n\t\t\tgoto bad;\n\t\t}\n\t\t*fd2p = s3;\n\t\tfrom.sin_port = ntohs((u_short)from.sin_port);\n\t\tif (from.sin_family != AF_INET ||\n\t\t    from.sin_port >= IPPORT_RESERVED ||\n\t\t    from.sin_port < IPPORT_RESERVED / 2) {\n\t\t\tfprintf(stderr,\n\t\t\t    \"socket: protocol failure in circuit setup.\\n\");\n\t\t\tgoto bad2;\n\t\t}\n\t}\n\t(void) write(s, locuser, strlen(locuser)+1);\n\t(void) write(s, remuser, strlen(remuser)+1);\n\t(void) write(s, cmd, strlen(cmd)+1);\n\tif (read(s, &c, 1) != 1) {\n\t\tperror(*ahost);\n\t\tgoto bad2;\n\t}\n\tif (c != 0) {\n\t\twhile (read(s, &c, 1) == 1) {\n\t\t\t(void) write(2, &c, 1);\n\t\t\tif (c == '\\n')\n\t\t\t\tbreak;\n\t\t}\n\t\tgoto bad2;\n\t}\n\tsigprocmask(SIG_SETMASK, &oldmask, NULL);\n\treturn (s);\nbad2:\n\tif (lport)\n\t\t(void) close(*fd2p);\nbad:\n\t(void) close(s);\n\tsigprocmask(SIG_SETMASK, &oldmask, NULL);\n\treturn (-1);\n}\n\nrresvport(alport)\n\tint *alport;\n{\n\tstruct sockaddr_in sin;\n\tint s;\n\n\tsin.sin_family = AF_INET;\n\tsin.sin_addr.s_addr = INADDR_ANY;\n\ts = socket(AF_INET, SOCK_STREAM, 0);\n\tif (s < 0)\n\t\treturn (-1);\n\tfor (;;) {\n\t\tsin.sin_port = htons((u_short)*alport);\n\t\tif (bind(s, (caddr_t)&sin, sizeof (sin)) >= 0)\n\t\t\treturn (s);\n\t\tif (errno != EADDRINUSE) {\n\t\t\t(void) close(s);\n\t\t\treturn (-1);\n\t\t}\n\t\t(*alport)--;\n\t\tif (*alport == IPPORT_RESERVED/2) {\n\t\t\t(void) close(s);\n\t\t\terrno = EAGAIN;\t\t/* close */\n\t\t\treturn (-1);\n\t\t}\n\t}\n}\n\nint\t_check_rhosts_file = 1;\n\nruserok(rhost, superuser, ruser, luser)\n\tchar *rhost;\n\tint superuser;\n\tchar *ruser, *luser;\n{\n\tFILE *hostf;\n\tchar fhost[MAXHOSTNAMELEN];\n\tint first = 1;\n\tregister char *sp, *p;\n\tint baselen = -1;\n\n\tsp = rhost;\n\tp = fhost;\n\twhile (*sp) {\n\t\tif (*sp == '.') {\n\t\t\tif (baselen == -1)\n\t\t\t\tbaselen = sp - rhost;\n\t\t\t*p++ = *sp++;\n\t\t} else {\n\t\t\t*p++ = isupper(*sp) ? tolower(*sp++) : *sp++;\n\t\t}\n\t}\n\t*p = '\\0';\n\thostf = superuser ? (FILE *)0 : fopen(\"/etc/hosts.equiv\", \"r\");\nagain:\n\tif (hostf) {\n\t\tif (!_validuser(hostf, fhost, luser, ruser, baselen)) {\n\t\t\t(void) fclose(hostf);\n\t\t\treturn(0);\n\t\t}\n\t\t(void) fclose(hostf);\n\t}\n\tif (first == 1 && (_check_rhosts_file || superuser)) {\n\t\tstruct stat sbuf;\n\t\tstruct passwd *pwd;\n\t\tchar pbuf[MAXPATHLEN];\n\n\t\tfirst = 0;\n\t\tif ((pwd = getpwnam(luser)) == NULL)\n\t\t\treturn(-1);\n\t\t(void)strcpy(pbuf, pwd->pw_dir);\n\t\t(void)strcat(pbuf, \"/.rhosts\");\n\t\tif ((hostf = fopen(pbuf, \"r\")) == NULL)\n\t\t\treturn(-1);\n\t\t/*\n\t\t * if owned by someone other than user or root or if\n\t\t * writeable by anyone but the owner, quit\n\t\t */\n\t\tif (fstat(fileno(hostf), &sbuf) ||\n\t\t    sbuf.st_uid && sbuf.st_uid != pwd->pw_uid ||\n\t\t    sbuf.st_mode&022) {\n\t\t\tfclose(hostf);\n\t\t\treturn(-1);\n\t\t}\n\t\tgoto again;\n\t}\n\treturn (-1);\n}\n\n/* don't make static, used by lpd(8) */\n_validuser(hostf, rhost, luser, ruser, baselen)\n\tchar *rhost, *luser, *ruser;\n\tFILE *hostf;\n\tint baselen;\n{\n\tchar *user;\n\tchar ahost[MAXHOSTNAMELEN];\n\tregister char *p;\n\n\twhile (fgets(ahost, sizeof (ahost), hostf)) {\n\t\tp = ahost;\n\t\twhile (*p != '\\n' && *p != ' ' && *p != '\\t' && *p != '\\0') {\n\t\t\t*p = isupper(*p) ? tolower(*p) : *p;\n\t\t\tp++;\n\t\t}\n\t\tif (*p == ' ' || *p == '\\t') {\n\t\t\t*p++ = '\\0';\n\t\t\twhile (*p == ' ' || *p == '\\t')\n\t\t\t\tp++;\n\t\t\tuser = p;\n\t\t\twhile (*p != '\\n' && *p != ' ' && *p != '\\t' && *p != '\\0')\n\t\t\t\tp++;\n\t\t} else\n\t\t\tuser = p;\n\t\t*p = '\\0';\n\t\tif (_checkhost(rhost, ahost, baselen) &&\n\t\t    !strcmp(ruser, *user ? user : luser)) {\n\t\t\treturn (0);\n\t\t}\n\t}\n\treturn (-1);\n}\n\nstatic\n_checkhost(rhost, lhost, len)\n\tchar *rhost, *lhost;\n\tint len;\n{\n\tstatic char ldomain[MAXHOSTNAMELEN + 1];\n\tstatic char *domainp = NULL;\n\tstatic int nodomain = 0;\n\tregister char *cp;\n\n\tif (len == -1)\n\t\treturn(!strcmp(rhost, lhost));\n\tif (strncmp(rhost, lhost, len))\n\t\treturn(0);\n\tif (!strcmp(rhost, lhost))\n\t\treturn(1);\n\tif (*(lhost + len) != '\\0')\n\t\treturn(0);\n\tif (nodomain)\n\t\treturn(0);\n\tif (!domainp) {\n\t\tif (gethostname(ldomain, sizeof(ldomain)) == -1) {\n\t\t\tnodomain = 1;\n\t\t\treturn(0);\n\t\t}\n\t\tldomain[MAXHOSTNAMELEN] = NULL;\n\t\tif ((domainp = index(ldomain, '.')) == (char *)NULL) {\n\t\t\tnodomain = 1;\n\t\t\treturn(0);\n\t\t}\n\t\tfor (cp = ++domainp; *cp; ++cp)\n\t\t\tif (isupper(*cp))\n\t\t\t\t*cp = tolower(*cp);\n\t}\n\treturn(!strcmp(domainp, rhost + len +1));\n}\n"
  },
  {
    "path": "lib/libc/net/res_comp.c",
    "content": "/*\n * Copyright (c) 1985 Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that this notice is preserved and that due credit is given\n * to the University of California at Berkeley. The name of the University\n * may not be used to endorse or promote products derived from this\n * software without specific prior written permission. This software\n * is provided ``as is'' without express or implied warranty.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)res_comp.c\t6.13 (Berkeley) 3/13/88\";\n#endif /* LIBC_SCCS and not lint */\n\n#include <sys/types.h>\n#include <stdio.h>\n#include <arpa/nameser.h>\n\n\n/*\n * Expand compressed domain name 'comp_dn' to full domain name.\n * 'msg' is a pointer to the begining of the message,\n * 'eomorig' points to the first location after the message,\n * 'exp_dn' is a pointer to a buffer of size 'length' for the result.\n * Return size of compressed name or -1 if there was an error.\n */\ndn_expand(msg, eomorig, comp_dn, exp_dn, length)\n\tu_char *msg, *eomorig, *comp_dn, *exp_dn;\n\tint length;\n{\n\tregister u_char *cp, *dn;\n\tregister int n, c;\n\tu_char *eom;\n\tint len = -1, checked = 0;\n\n\tdn = exp_dn;\n\tcp = comp_dn;\n\teom = exp_dn + length - 1;\n\t/*\n\t * fetch next label in domain name\n\t */\n\twhile (n = *cp++) {\n\t\t/*\n\t\t * Check for indirection\n\t\t */\n\t\tswitch (n & INDIR_MASK) {\n\t\tcase 0:\n\t\t\tif (dn != exp_dn) {\n\t\t\t\tif (dn >= eom)\n\t\t\t\t\treturn (-1);\n\t\t\t\t*dn++ = '.';\n\t\t\t}\n\t\t\tif (dn+n >= eom)\n\t\t\t\treturn (-1);\n\t\t\tchecked += n + 1;\n\t\t\twhile (--n >= 0) {\n\t\t\t\tif ((c = *cp++) == '.') {\n\t\t\t\t\tif (dn+n+1 >= eom)\n\t\t\t\t\t\treturn (-1);\n\t\t\t\t\t*dn++ = '\\\\';\n\t\t\t\t}\n\t\t\t\t*dn++ = c;\n\t\t\t\tif (cp >= eomorig)\t/* out of range */\n\t\t\t\t\treturn(-1);\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase INDIR_MASK:\n\t\t\tif (len < 0)\n\t\t\t\tlen = cp - comp_dn + 1;\n\t\t\tcp = msg + (((n & 0x3f) << 8) | (*cp & 0xff));\n\t\t\tif (cp < msg || cp >= eomorig)\t/* out of range */\n\t\t\t\treturn(-1);\n\t\t\tchecked += 2;\n\t\t\t/*\n\t\t\t * Check for loops in the compressed name;\n\t\t\t * if we've looked at the whole message,\n\t\t\t * there must be a loop.\n\t\t\t */\n\t\t\tif (checked >= eomorig - msg)\n\t\t\t\treturn (-1);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\treturn (-1);\t\t\t/* flag error */\n\t\t}\n\t}\n\t*dn = '\\0';\n\tif (len < 0)\n\t\tlen = cp - comp_dn;\n\treturn (len);\n}\n\n/*\n * Compress domain name 'exp_dn' into 'comp_dn'.\n * Return the size of the compressed name or -1.\n * 'length' is the size of the array pointed to by 'comp_dn'.\n * 'dnptrs' is a list of pointers to previous compressed names. dnptrs[0]\n * is a pointer to the beginning of the message. The list ends with NULL.\n * 'lastdnptr' is a pointer to the end of the arrary pointed to\n * by 'dnptrs'. Side effect is to update the list of pointers for\n * labels inserted into the message as we compress the name.\n * If 'dnptr' is NULL, we don't try to compress names. If 'lastdnptr'\n * is NULL, we don't update the list.\n */\ndn_comp(exp_dn, comp_dn, length, dnptrs, lastdnptr)\n\tu_char *exp_dn, *comp_dn;\n\tint length;\n\tu_char **dnptrs, **lastdnptr;\n{\n\tregister u_char *cp, *dn;\n\tregister int c, l;\n\tu_char **cpp, **lpp, *sp, *eob;\n\tu_char *msg;\n\n\tdn = exp_dn;\n\tcp = comp_dn;\n\teob = cp + length;\n\tif (dnptrs != NULL) {\n\t\tif ((msg = *dnptrs++) != NULL) {\n\t\t\tfor (cpp = dnptrs; *cpp != NULL; cpp++)\n\t\t\t\t;\n\t\t\tlpp = cpp;\t/* end of list to search */\n\t\t}\n\t} else\n\t\tmsg = NULL;\n\tfor (c = *dn++; c != '\\0'; ) {\n\t\t/* look to see if we can use pointers */\n\t\tif (msg != NULL) {\n\t\t\tif ((l = dn_find(dn-1, msg, dnptrs, lpp)) >= 0) {\n\t\t\t\tif (cp+1 >= eob)\n\t\t\t\t\treturn (-1);\n\t\t\t\t*cp++ = (l >> 8) | INDIR_MASK;\n\t\t\t\t*cp++ = l % 256;\n\t\t\t\treturn (cp - comp_dn);\n\t\t\t}\n\t\t\t/* not found, save it */\n\t\t\tif (lastdnptr != NULL && cpp < lastdnptr-1) {\n\t\t\t\t*cpp++ = cp;\n\t\t\t\t*cpp = NULL;\n\t\t\t}\n\t\t}\n\t\tsp = cp++;\t/* save ptr to length byte */\n\t\tdo {\n\t\t\tif (c == '.') {\n\t\t\t\tc = *dn++;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (c == '\\\\') {\n\t\t\t\tif ((c = *dn++) == '\\0')\n\t\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (cp >= eob)\n\t\t\t\treturn (-1);\n\t\t\t*cp++ = c;\n\t\t} while ((c = *dn++) != '\\0');\n\t\t/* catch trailing '.'s but not '..' */\n\t\tif ((l = cp - sp - 1) == 0 && c == '\\0') {\n\t\t\tcp--;\n\t\t\tbreak;\n\t\t}\n\t\tif (l <= 0 || l > MAXLABEL)\n\t\t\treturn (-1);\n\t\t*sp = l;\n\t}\n\tif (cp >= eob)\n\t\treturn (-1);\n\t*cp++ = '\\0';\n\treturn (cp - comp_dn);\n}\n\n/*\n * Skip over a compressed domain name. Return the size or -1.\n */\ndn_skipname(comp_dn, eom)\n\tu_char *comp_dn, *eom;\n{\n\tregister u_char *cp;\n\tregister int n;\n\n\tcp = comp_dn;\n\twhile (cp < eom && (n = *cp++)) {\n\t\t/*\n\t\t * check for indirection\n\t\t */\n\t\tswitch (n & INDIR_MASK) {\n\t\tcase 0:\t\t/* normal case, n == len */\n\t\t\tcp += n;\n\t\t\tcontinue;\n\t\tdefault:\t/* illegal type */\n\t\t\treturn (-1);\n\t\tcase INDIR_MASK:\t/* indirection */\n\t\t\tcp++;\n\t\t}\n\t\tbreak;\n\t}\n\treturn (cp - comp_dn);\n}\n\n/*\n * Search for expanded name from a list of previously compressed names.\n * Return the offset from msg if found or -1.\n * dnptrs is the pointer to the first name on the list,\n * not the pointer to the start of the message.\n */\nstatic\ndn_find(exp_dn, msg, dnptrs, lastdnptr)\n\tu_char *exp_dn, *msg;\n\tu_char **dnptrs, **lastdnptr;\n{\n\tregister u_char *dn, *cp, **cpp;\n\tregister int n;\n\tu_char *sp;\n\n\tfor (cpp = dnptrs; cpp < lastdnptr; cpp++) {\n\t\tdn = exp_dn;\n\t\tsp = cp = *cpp;\n\t\twhile (n = *cp++) {\n\t\t\t/*\n\t\t\t * check for indirection\n\t\t\t */\n\t\t\tswitch (n & INDIR_MASK) {\n\t\t\tcase 0:\t\t/* normal case, n == len */\n\t\t\t\twhile (--n >= 0) {\n\t\t\t\t\tif (*dn == '\\\\')\n\t\t\t\t\t\tdn++;\n\t\t\t\t\tif (*dn++ != *cp++)\n\t\t\t\t\t\tgoto next;\n\t\t\t\t}\n\t\t\t\tif ((n = *dn++) == '\\0' && *cp == '\\0')\n\t\t\t\t\treturn (sp - msg);\n\t\t\t\tif (n == '.')\n\t\t\t\t\tcontinue;\n\t\t\t\tgoto next;\n\n\t\t\tdefault:\t/* illegal type */\n\t\t\t\treturn (-1);\n\n\t\t\tcase INDIR_MASK:\t/* indirection */\n\t\t\t\tcp = msg + (((n & 0x3f) << 8) | *cp);\n\t\t\t}\n\t\t}\n\t\tif (*dn == '\\0')\n\t\t\treturn (sp - msg);\n\tnext:\t;\n\t}\n\treturn (-1);\n}\n\n/*\n * Routines to insert/extract short/long's. Must account for byte\n * order and non-alignment problems. This code at least has the\n * advantage of being portable.\n *\n * used by sendmail.\n */\n\nu_short\n_getshort(msgp)\n\tu_char *msgp;\n{\n\tregister u_char *p = (u_char *) msgp;\n#ifdef vax\n\t/*\n\t * vax compiler doesn't put shorts in registers\n\t */\n\tregister u_long u;\n#else\n\tregister u_short u;\n#endif\n\n\tu = *p++ << 8;\n\treturn ((u_short)(u | *p));\n}\n\nu_long\n_getlong(msgp)\n\tu_char *msgp;\n{\n\tregister u_char *p = (u_char *) msgp;\n\tregister u_long u;\n\n\tu = *p++; u <<= 8;\n\tu |= *p++; u <<= 8;\n\tu |= *p++; u <<= 8;\n\treturn (u | *p);\n}\n\n\nputshort(s, msgp)\n\tregister u_short s;\n\tregister u_char *msgp;\n{\n\n\tmsgp[1] = s;\n\tmsgp[0] = s >> 8;\n}\n\nputlong(l, msgp)\n\tregister u_long l;\n\tregister u_char *msgp;\n{\n\n\tmsgp[3] = l;\n\tmsgp[2] = (l >>= 8);\n\tmsgp[1] = (l >>= 8);\n\tmsgp[0] = l >> 8;\n}\n"
  },
  {
    "path": "lib/libc/net/res_debug.c",
    "content": "/*\n * Copyright (c) 1985 Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that this notice is preserved and that due credit is given\n * to the University of California at Berkeley. The name of the University\n * may not be used to endorse or promote products derived from this\n * software without specific prior written permission. This software\n * is provided ``as is'' without express or implied warranty.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)res_debug.c\t5.22 (Berkeley) 3/7/88\";\n#endif /* LIBC_SCCS and not lint */\n\n#if defined(lint) && !defined(DEBUG)\n#define DEBUG\n#endif\n\n#include <sys/types.h>\n#include <netinet/in.h>\n#include <stdio.h>\n#include <arpa/nameser.h>\n\nextern char *p_cdname(), *p_rr(), *p_type(), *p_class();\nextern char *inet_ntoa();\n\nchar *_res_opcodes[] = {\n\t\"QUERY\",\n\t\"IQUERY\",\n\t\"CQUERYM\",\n\t\"CQUERYU\",\n\t\"4\",\n\t\"5\",\n\t\"6\",\n\t\"7\",\n\t\"8\",\n\t\"UPDATEA\",\n\t\"UPDATED\",\n\t\"UPDATEDA\",\n\t\"UPDATEM\",\n\t\"UPDATEMA\",\n\t\"ZONEINIT\",\n\t\"ZONEREF\",\n};\n\nchar *_res_resultcodes[] = {\n\t\"NOERROR\",\n\t\"FORMERR\",\n\t\"SERVFAIL\",\n\t\"NXDOMAIN\",\n\t\"NOTIMP\",\n\t\"REFUSED\",\n\t\"6\",\n\t\"7\",\n\t\"8\",\n\t\"9\",\n\t\"10\",\n\t\"11\",\n\t\"12\",\n\t\"13\",\n\t\"14\",\n\t\"NOCHANGE\",\n};\n\np_query(msg)\n\tchar *msg;\n{\n#ifdef DEBUG\n\tfp_query(msg,stdout);\n#endif\n}\n\n/*\n * Print the contents of a query.\n * This is intended to be primarily a debugging routine.\n */\nfp_query(msg,file)\n\tchar *msg;\n\tFILE *file;\n{\n#ifdef DEBUG\n\tregister char *cp;\n\tregister HEADER *hp;\n\tregister int n;\n\n\t/*\n\t * Print header fields.\n\t */\n\thp = (HEADER *)msg;\n\tcp = msg + sizeof(HEADER);\n\tfprintf(file,\"HEADER:\\n\");\n\tfprintf(file,\"\\topcode = %s\", _res_opcodes[hp->opcode]);\n\tfprintf(file,\", id = %d\", ntohs(hp->id));\n\tfprintf(file,\", rcode = %s\\n\", _res_resultcodes[hp->rcode]);\n\tfprintf(file,\"\\theader flags: \");\n\tif (hp->qr)\n\t\tfprintf(file,\" qr\");\n\tif (hp->aa)\n\t\tfprintf(file,\" aa\");\n\tif (hp->tc)\n\t\tfprintf(file,\" tc\");\n\tif (hp->rd)\n\t\tfprintf(file,\" rd\");\n\tif (hp->ra)\n\t\tfprintf(file,\" ra\");\n\tif (hp->pr)\n\t\tfprintf(file,\" pr\");\n\tfprintf(file,\"\\n\\tqdcount = %d\", ntohs(hp->qdcount));\n\tfprintf(file,\", ancount = %d\", ntohs(hp->ancount));\n\tfprintf(file,\", nscount = %d\", ntohs(hp->nscount));\n\tfprintf(file,\", arcount = %d\\n\\n\", ntohs(hp->arcount));\n\t/*\n\t * Print question records.\n\t */\n\tif (n = ntohs(hp->qdcount)) {\n\t\tfprintf(file,\"QUESTIONS:\\n\");\n\t\twhile (--n >= 0) {\n\t\t\tfprintf(file,\"\\t\");\n\t\t\tcp = p_cdname(cp, msg, file);\n\t\t\tif (cp == NULL)\n\t\t\t\treturn;\n\t\t\tfprintf(file,\", type = %s\", p_type(_getshort(cp)));\n\t\t\tcp += sizeof(u_short);\n\t\t\tfprintf(file,\", class = %s\\n\\n\", p_class(_getshort(cp)));\n\t\t\tcp += sizeof(u_short);\n\t\t}\n\t}\n\t/*\n\t * Print authoritative answer records\n\t */\n\tif (n = ntohs(hp->ancount)) {\n\t\tfprintf(file,\"ANSWERS:\\n\");\n\t\twhile (--n >= 0) {\n\t\t\tfprintf(file,\"\\t\");\n\t\t\tcp = p_rr(cp, msg, file);\n\t\t\tif (cp == NULL)\n\t\t\t\treturn;\n\t\t}\n\t}\n\t/*\n\t * print name server records\n\t */\n\tif (n = ntohs(hp->nscount)) {\n\t\tfprintf(file,\"NAME SERVERS:\\n\");\n\t\twhile (--n >= 0) {\n\t\t\tfprintf(file,\"\\t\");\n\t\t\tcp = p_rr(cp, msg, file);\n\t\t\tif (cp == NULL)\n\t\t\t\treturn;\n\t\t}\n\t}\n\t/*\n\t * print additional records\n\t */\n\tif (n = ntohs(hp->arcount)) {\n\t\tfprintf(file,\"ADDITIONAL RECORDS:\\n\");\n\t\twhile (--n >= 0) {\n\t\t\tfprintf(file,\"\\t\");\n\t\t\tcp = p_rr(cp, msg, file);\n\t\t\tif (cp == NULL)\n\t\t\t\treturn;\n\t\t}\n\t}\n#endif\n}\n\nchar *\np_cdname(cp, msg, file)\n\tchar *cp, *msg;\n\tFILE *file;\n{\n#ifdef DEBUG\n\tchar name[MAXDNAME];\n\tint n;\n\n\tif ((n = dn_expand(msg, msg + 512, cp, name, sizeof(name))) < 0)\n\t\treturn (NULL);\n\tif (name[0] == '\\0') {\n\t\tname[0] = '.';\n\t\tname[1] = '\\0';\n\t}\n\tfputs(name, file);\n\treturn (cp + n);\n#endif\n}\n\n/*\n * Print resource record fields in human readable form.\n */\nchar *\np_rr(cp, msg, file)\n\tchar *cp, *msg;\n\tFILE *file;\n{\n#ifdef DEBUG\n\tint type, class, dlen, n, c;\n\tstruct in_addr inaddr;\n\tchar *cp1;\n\n\tif ((cp = p_cdname(cp, msg, file)) == NULL)\n\t\treturn (NULL);\t\t\t/* compression error */\n\tfprintf(file,\"\\n\\ttype = %s\", p_type(type = _getshort(cp)));\n\tcp += sizeof(u_short);\n\tfprintf(file,\", class = %s\", p_class(class = _getshort(cp)));\n\tcp += sizeof(u_short);\n\tfprintf(file,\", ttl = %lu\", _getlong(cp));\n\tcp += sizeof(u_long);\n\tfprintf(file,\", dlen = %d\\n\", dlen = _getshort(cp));\n\tcp += sizeof(u_short);\n\tcp1 = cp;\n\t/*\n\t * Print type specific data, if appropriate\n\t */\n\tswitch (type) {\n\tcase T_A:\n\t\tswitch (class) {\n\t\tcase C_IN:\n\t\t\tbcopy(cp, (char *)&inaddr, sizeof(inaddr));\n\t\t\tif (dlen == 4) {\n\t\t\t\tfprintf(file,\"\\tinternet address = %s\\n\",\n\t\t\t\t\tinet_ntoa(inaddr));\n\t\t\t\tcp += dlen;\n\t\t\t} else if (dlen == 7) {\n\t\t\t\tfprintf(file,\"\\tinternet address = %s\",\n\t\t\t\t\tinet_ntoa(inaddr));\n\t\t\t\tfprintf(file,\", protocol = %d\", cp[4]);\n\t\t\t\tfprintf(file,\", port = %d\\n\",\n\t\t\t\t\t(cp[5] << 8) + cp[6]);\n\t\t\t\tcp += dlen;\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tcp += dlen;\n\t\t}\n\t\tbreak;\n\tcase T_CNAME:\n\tcase T_MB:\n#ifdef OLDRR\n\tcase T_MD:\n\tcase T_MF:\n#endif /* OLDRR */\n\tcase T_MG:\n\tcase T_MR:\n\tcase T_NS:\n\tcase T_PTR:\n\t\tfprintf(file,\"\\tdomain name = \");\n\t\tcp = p_cdname(cp, msg, file);\n\t\tfprintf(file,\"\\n\");\n\t\tbreak;\n\n\tcase T_HINFO:\n\t\tif (n = *cp++) {\n\t\t\tfprintf(file,\"\\tCPU=%.*s\\n\", n, cp);\n\t\t\tcp += n;\n\t\t}\n\t\tif (n = *cp++) {\n\t\t\tfprintf(file,\"\\tOS=%.*s\\n\", n, cp);\n\t\t\tcp += n;\n\t\t}\n\t\tbreak;\n\n\tcase T_SOA:\n\t\tfprintf(file,\"\\torigin = \");\n\t\tcp = p_cdname(cp, msg, file);\n\t\tfprintf(file,\"\\n\\tmail addr = \");\n\t\tcp = p_cdname(cp, msg, file);\n\t\tfprintf(file,\"\\n\\tserial=%ld\", _getlong(cp));\n\t\tcp += sizeof(u_long);\n\t\tfprintf(file,\", refresh=%ld\", _getlong(cp));\n\t\tcp += sizeof(u_long);\n\t\tfprintf(file,\", retry=%ld\", _getlong(cp));\n\t\tcp += sizeof(u_long);\n\t\tfprintf(file,\", expire=%ld\", _getlong(cp));\n\t\tcp += sizeof(u_long);\n\t\tfprintf(file,\", min=%ld\\n\", _getlong(cp));\n\t\tcp += sizeof(u_long);\n\t\tbreak;\n\n\tcase T_MX:\n\t\tfprintf(file,\"\\tpreference = %d,\",_getshort(cp));\n\t\tcp += sizeof(u_short);\n\t\tfprintf(file,\" name = \");\n\t\tcp = p_cdname(cp, msg, file);\n\t\tbreak;\n\n\tcase T_MINFO:\n\t\tfprintf(file,\"\\trequests = \");\n\t\tcp = p_cdname(cp, msg, file);\n\t\tfprintf(file,\"\\n\\terrors = \");\n\t\tcp = p_cdname(cp, msg, file);\n\t\tbreak;\n\n\tcase T_UINFO:\n\t\tfprintf(file,\"\\t%s\\n\", cp);\n\t\tcp += dlen;\n\t\tbreak;\n\n\tcase T_UID:\n\tcase T_GID:\n\t\tif (dlen == 4) {\n\t\t\tfprintf(file,\"\\t%ld\\n\", _getlong(cp));\n\t\t\tcp += sizeof(int);\n\t\t}\n\t\tbreak;\n\n\tcase T_WKS:\n\t\tif (dlen < sizeof(u_long) + 1)\n\t\t\tbreak;\n\t\tbcopy(cp, (char *)&inaddr, sizeof(inaddr));\n\t\tcp += sizeof(u_long);\n\t\tfprintf(file,\"\\tinternet address = %s, protocol = %d\\n\\t\",\n\t\t\tinet_ntoa(inaddr), *cp++);\n\t\tn = 0;\n\t\twhile (cp < cp1 + dlen) {\n\t\t\tc = *cp++;\n\t\t\tdo {\n \t\t\t\tif (c & 0200)\n\t\t\t\t\tfprintf(file,\" %d\", n);\n \t\t\t\tc <<= 1;\n\t\t\t} while (++n & 07);\n\t\t}\n\t\tputc('\\n',file);\n\t\tbreak;\n\n#ifdef ALLOW_T_UNSPEC\n\tcase T_UNSPEC:\n\t\t{\n\t\t\tint NumBytes = 8;\n\t\t\tchar *DataPtr;\n\t\t\tint i;\n\n\t\t\tif (dlen < NumBytes) NumBytes = dlen;\n\t\t\tfprintf(file, \"\\tFirst %d bytes of hex data:\",\n\t\t\t\tNumBytes);\n\t\t\tfor (i = 0, DataPtr = cp; i < NumBytes; i++, DataPtr++)\n\t\t\t\tfprintf(file, \" %x\", *DataPtr);\n\t\t\tfputs(\"\\n\", file);\n\t\t\tcp += dlen;\n\t\t}\n\t\tbreak;\n#endif /* ALLOW_T_UNSPEC */\n\n\tdefault:\n\t\tfprintf(file,\"\\t???\\n\");\n\t\tcp += dlen;\n\t}\n\tif (cp != cp1 + dlen)\n\t\tfprintf(file,\"packet size error (%#x != %#x)\\n\", cp, cp1+dlen);\n\tfprintf(file,\"\\n\");\n\treturn (cp);\n#endif\n}\n\nstatic\tchar nbuf[20];\n\n/*\n * Return a string for the type\n */\nchar *\np_type(type)\n\tint type;\n{\n\tswitch (type) {\n\tcase T_A:\n\t\treturn(\"A\");\n\tcase T_NS:\t\t/* authoritative server */\n\t\treturn(\"NS\");\n#ifdef OLDRR\n\tcase T_MD:\t\t/* mail destination */\n\t\treturn(\"MD\");\n\tcase T_MF:\t\t/* mail forwarder */\n\t\treturn(\"MF\");\n#endif /* OLDRR */\n\tcase T_CNAME:\t\t/* connonical name */\n\t\treturn(\"CNAME\");\n\tcase T_SOA:\t\t/* start of authority zone */\n\t\treturn(\"SOA\");\n\tcase T_MB:\t\t/* mailbox domain name */\n\t\treturn(\"MB\");\n\tcase T_MG:\t\t/* mail group member */\n\t\treturn(\"MG\");\n\tcase T_MX:\t\t/* mail routing info */\n\t\treturn(\"MX\");\n\tcase T_MR:\t\t/* mail rename name */\n\t\treturn(\"MR\");\n\tcase T_NULL:\t\t/* null resource record */\n\t\treturn(\"NULL\");\n\tcase T_WKS:\t\t/* well known service */\n\t\treturn(\"WKS\");\n\tcase T_PTR:\t\t/* domain name pointer */\n\t\treturn(\"PTR\");\n\tcase T_HINFO:\t\t/* host information */\n\t\treturn(\"HINFO\");\n\tcase T_MINFO:\t\t/* mailbox information */\n\t\treturn(\"MINFO\");\n\tcase T_AXFR:\t\t/* zone transfer */\n\t\treturn(\"AXFR\");\n\tcase T_MAILB:\t\t/* mail box */\n\t\treturn(\"MAILB\");\n\tcase T_MAILA:\t\t/* mail address */\n\t\treturn(\"MAILA\");\n\tcase T_ANY:\t\t/* matches any type */\n\t\treturn(\"ANY\");\n\tcase T_UINFO:\n\t\treturn(\"UINFO\");\n\tcase T_UID:\n\t\treturn(\"UID\");\n\tcase T_GID:\n\t\treturn(\"GID\");\n#ifdef ALLOW_T_UNSPEC\n\tcase T_UNSPEC:\n\t\treturn(\"UNSPEC\");\n#endif /* ALLOW_T_UNSPEC */\n\tdefault:\n\t\t(void)sprintf(nbuf, \"%d\", type);\n\t\treturn(nbuf);\n\t}\n}\n\n/*\n * Return a mnemonic for class\n */\nchar *\np_class(class)\n\tint class;\n{\n\n\tswitch (class) {\n\tcase C_IN:\t\t/* internet class */\n\t\treturn(\"IN\");\n\tcase C_ANY:\t\t/* matches any class */\n\t\treturn(\"ANY\");\n\tdefault:\n\t\t(void)sprintf(nbuf, \"%d\", class);\n\t\treturn(nbuf);\n\t}\n}\n"
  },
  {
    "path": "lib/libc/net/res_init.c",
    "content": "/*\n * Copyright (c) 1985 Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that this notice is preserved and that due credit is given\n * to the University of California at Berkeley. The name of the University\n * may not be used to endorse or promote products derived from this\n * software without specific prior written permission. This software\n * is provided ``as is'' without express or implied warranty.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)res_init.c\t6.8 (Berkeley) 3/7/88\";\n#endif /* LIBC_SCCS and not lint */\n\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <netinet/in.h>\n#include <stdio.h>\n#include <arpa/nameser.h>\n#include <resolv.h>\n\n/*\n * Resolver configuration file. Contains the address of the\n * inital name server to query and the default domain for\n * non fully qualified domain names.\n */\n\n#ifndef\tCONFFILE\n#define\tCONFFILE\t\"/etc/resolv.conf\"\n#endif\n\n/*\n * Resolver state default settings\n */\n\nstruct state _res = {\n    RES_TIMEOUT,               \t/* retransmition time interval */\n    4,                         \t/* number of times to retransmit */\n    RES_DEFAULT,\t\t/* options flags */\n    1,                         \t/* number of name servers */\n};\n\n/*\n * Set up default settings.  If the configuration file exist, the values\n * there will have precedence.  Otherwise, the server address is set to\n * INADDR_ANY and the default domain name comes from the gethostname().\n *\n * The configuration file should only be used if you want to redefine your\n * domain or run without a server on your machine.\n *\n * Return 0 if completes successfully, -1 on error\n */\nres_init()\n{\n    register FILE *fp;\n    register char *cp, **pp;\n    char buf[BUFSIZ];\n    extern u_long inet_addr();\n    extern char *index();\n    extern char *strcpy(), *strncpy();\n    extern char *getenv();\n    int n = 0;    /* number of nameserver records read from file */\n\n    _res.nsaddr.sin_addr.s_addr = INADDR_ANY;\n    _res.nsaddr.sin_family = AF_INET;\n    _res.nsaddr.sin_port = htons(NAMESERVER_PORT);\n    _res.nscount = 1;\n    _res.defdname[0] = '\\0';\n\n    if ((fp = fopen(CONFFILE, \"r\")) != NULL) {\n        /* read the config file */\n        while (fgets(buf, sizeof(buf), fp) != NULL) {\n            /* read default domain name */\n            if (!strncmp(buf, \"domain\", sizeof(\"domain\") - 1)) {\n                cp = buf + sizeof(\"domain\") - 1;\n                while (*cp == ' ' || *cp == '\\t')\n                    cp++;\n                if (*cp == '\\0')\n                    continue;\n                (void)strncpy(_res.defdname, cp, sizeof(_res.defdname));\n                _res.defdname[sizeof(_res.defdname) - 1] = '\\0';\n                if ((cp = index(_res.defdname, '\\n')) != NULL)\n                    *cp = '\\0';\n                continue;\n            }\n            /* read nameservers to query */\n            if (!strncmp(buf, \"nameserver\", \n               sizeof(\"nameserver\") - 1) && (n < MAXNS)) {\n                cp = buf + sizeof(\"nameserver\") - 1;\n                while (*cp == ' ' || *cp == '\\t')\n                    cp++;\n                if (*cp == '\\0')\n                    continue;\n                _res.nsaddr_list[n].sin_addr.s_addr = inet_addr(cp);\n                if (_res.nsaddr_list[n].sin_addr.s_addr == (unsigned)-1) \n                    _res.nsaddr_list[n].sin_addr.s_addr = INADDR_ANY;\n                _res.nsaddr_list[n].sin_family = AF_INET;\n                _res.nsaddr_list[n].sin_port = htons(NAMESERVER_PORT);\n                if ( ++n >= MAXNS) { \n                    n = MAXNS;\n#ifdef DEBUG\n                    if ( _res.options & RES_DEBUG )\n                        printf(\"MAXNS reached, reading resolv.conf\\n\");\n#endif DEBUG\n                }\n                continue;\n            }\n        }\n        if ( n > 1 ) \n            _res.nscount = n;\n        (void) fclose(fp);\n    }\n    if (_res.defdname[0] == 0) {\n        if (gethostname(buf, sizeof(_res.defdname)) == 0 &&\n           (cp = index(buf, '.')))\n             (void)strcpy(_res.defdname, cp + 1);\n    }\n\n    /* Allow user to override the local domain definition */\n    if ((cp = getenv(\"LOCALDOMAIN\")) != NULL)\n        (void)strncpy(_res.defdname, cp, sizeof(_res.defdname));\n\n    /* find components of local domain that might be searched */\n    pp = _res.dnsrch;\n    *pp++ = _res.defdname;\n    for (cp = _res.defdname, n = 0; *cp; cp++)\n\tif (*cp == '.')\n\t    n++;\n    cp = _res.defdname;\n    for (; n >= LOCALDOMAINPARTS && pp < _res.dnsrch + MAXDNSRCH; n--) {\n\tcp = index(cp, '.');\n\t*pp++ = ++cp;\n    }\n    _res.options |= RES_INIT;\n    return(0);\n}\n"
  },
  {
    "path": "lib/libc/net/res_mkquery.c",
    "content": "/*\n * Copyright (c) 1985 Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that this notice is preserved and that due credit is given\n * to the University of California at Berkeley. The name of the University\n * may not be used to endorse or promote products derived from this\n * software without specific prior written permission. This software\n * is provided ``as is'' without express or implied warranty.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)res_mkquery.c\t6.7 (Berkeley) 3/7/88\";\n#endif /* LIBC_SCCS and not lint */\n\n#include <stdio.h>\n#include <sys/types.h>\n#include <netinet/in.h>\n#include <arpa/nameser.h>\n#include <resolv.h>\n\n/*\n * Form all types of queries.\n * Returns the size of the result or -1.\n */\nres_mkquery(op, dname, class, type, data, datalen, newrr, buf, buflen)\n\tint op;\t\t\t/* opcode of query */\n\tchar *dname;\t\t/* domain name */\n\tint class, type;\t/* class and type of query */\n\tchar *data;\t\t/* resource record data */\n\tint datalen;\t\t/* length of data */\n\tstruct rrec *newrr;\t/* new rr for modify or append */\n\tchar *buf;\t\t/* buffer to put query */\n\tint buflen;\t\t/* size of buffer */\n{\n\tregister HEADER *hp;\n\tregister char *cp;\n\tregister int n;\n\tchar dnbuf[MAXDNAME];\n\tchar *dnptrs[10], **dpp, **lastdnptr;\n\textern char *index();\n\n#ifdef DEBUG\n\tif (_res.options & RES_DEBUG)\n\t\tprintf(\"res_mkquery(%d, %s, %d, %d)\\n\", op, dname, class, type);\n#endif DEBUG\n\t/*\n\t * Initialize header fields.\n\t */\n\thp = (HEADER *) buf;\n\thp->id = htons(++_res.id);\n\thp->opcode = op;\n\thp->qr = hp->aa = hp->tc = hp->ra = 0;\n\thp->pr = (_res.options & RES_PRIMARY) != 0;\n\thp->rd = (_res.options & RES_RECURSE) != 0;\n\thp->rcode = NOERROR;\n\thp->qdcount = 0;\n\thp->ancount = 0;\n\thp->nscount = 0;\n\thp->arcount = 0;\n\tcp = buf + sizeof(HEADER);\n\tbuflen -= sizeof(HEADER);\n\tdpp = dnptrs;\n\t*dpp++ = buf;\n\t*dpp++ = NULL;\n\tlastdnptr = dnptrs + sizeof(dnptrs)/sizeof(dnptrs[0]);\n\t/*\n\t * If the domain name contains no dots (single label), then\n\t * append the default domain name to the one given.\n\t */\n\tif ((_res.options & RES_DEFNAMES) && dname != 0 && dname[0] != '\\0' &&\n\t    index(dname, '.') == NULL) {\n\t\tif (!(_res.options & RES_INIT))\n\t\t\tif (res_init() == -1)\n\t\t\t\treturn(-1);\n\t\tif (_res.defdname[0] != '\\0') {\n\t\t\t(void)sprintf(dnbuf, \"%s.%s\", dname, _res.defdname);\n\t\t\tdname = dnbuf;\n\t\t}\n\t}\n\t/*\n\t * perform opcode specific processing\n\t */\n\tswitch (op) {\n\tcase QUERY:\n\t\tbuflen -= QFIXEDSZ;\n\t\tif ((n = dn_comp(dname, cp, buflen, dnptrs, lastdnptr)) < 0)\n\t\t\treturn (-1);\n\t\tcp += n;\n\t\tbuflen -= n;\n\t\tputshort(type, cp);\n\t\tcp += sizeof(u_short);\n\t\tputshort(class, cp);\n\t\tcp += sizeof(u_short);\n\t\thp->qdcount = htons(1);\n\t\tif (op == QUERY || data == NULL)\n\t\t\tbreak;\n\t\t/*\n\t\t * Make an additional record for completion domain.\n\t\t */\n\t\tbuflen -= RRFIXEDSZ;\n\t\tif ((n = dn_comp(data, cp, buflen, dnptrs, lastdnptr)) < 0)\n\t\t\treturn (-1);\n\t\tcp += n;\n\t\tbuflen -= n;\n\t\tputshort(T_NULL, cp);\n\t\tcp += sizeof(u_short);\n\t\tputshort(class, cp);\n\t\tcp += sizeof(u_short);\n\t\tputlong((long)0, cp);\n\t\tcp += sizeof(u_long);\n\t\tputshort(0, cp);\n\t\tcp += sizeof(u_short);\n\t\thp->arcount = htons(1);\n\t\tbreak;\n\n\tcase IQUERY:\n\t\t/*\n\t\t * Initialize answer section\n\t\t */\n\t\tif (buflen < 1 + RRFIXEDSZ + datalen)\n\t\t\treturn (-1);\n\t\t*cp++ = '\\0';\t/* no domain name */\n\t\tputshort(type, cp);\n\t\tcp += sizeof(u_short);\n\t\tputshort(class, cp);\n\t\tcp += sizeof(u_short);\n\t\tputlong((long)0, cp);\n\t\tcp += sizeof(u_long);\n\t\tputshort(datalen, cp);\n\t\tcp += sizeof(u_short);\n\t\tif (datalen) {\n\t\t\tbcopy(data, cp, datalen);\n\t\t\tcp += datalen;\n\t\t}\n\t\thp->ancount = htons(1);\n\t\tbreak;\n\n#ifdef ALLOW_UPDATES\n\t/*\n\t * For UPDATEM/UPDATEMA, do UPDATED/UPDATEDA followed by UPDATEA\n\t * (Record to be modified is followed by its replacement in msg.)\n\t */\n\tcase UPDATEM:\n\tcase UPDATEMA:\n\n\tcase UPDATED:\n\t\t/*\n\t\t * The res code for UPDATED and UPDATEDA is the same; user\n\t\t * calls them differently: specifies data for UPDATED; server\n\t\t * ignores data if specified for UPDATEDA.\n\t\t */\n\tcase UPDATEDA:\n\t\tbuflen -= RRFIXEDSZ + datalen;\n\t\tif ((n = dn_comp(dname, cp, buflen, dnptrs, lastdnptr)) < 0)\n\t\t\treturn (-1);\n\t\tcp += n;\n\t\tputshort(type, cp);\n                cp += sizeof(u_short);\n                putshort(class, cp);\n                cp += sizeof(u_short);\n\t\tputlong((long)0, cp);\n\t\tcp += sizeof(u_long);\n\t\tputshort(datalen, cp);\n                cp += sizeof(u_short);\n\t\tif (datalen) {\n\t\t\tbcopy(data, cp, datalen);\n\t\t\tcp += datalen;\n\t\t}\n\t\tif ( (op == UPDATED) || (op == UPDATEDA) ) {\n\t\t\thp->ancount = htons(0);\n\t\t\tbreak;\n\t\t}\n\t\t/* Else UPDATEM/UPDATEMA, so drop into code for UPDATEA */\n\n\tcase UPDATEA:\t/* Add new resource record */\n\t\tbuflen -= RRFIXEDSZ + datalen;\n\t\tif ((n = dn_comp(dname, cp, buflen, dnptrs, lastdnptr)) < 0)\n\t\t\treturn (-1);\n\t\tcp += n;\n\t\tputshort(newrr->r_type, cp);\n                cp += sizeof(u_short);\n                putshort(newrr->r_class, cp);\n                cp += sizeof(u_short);\n\t\tputlong((long)0, cp);\n\t\tcp += sizeof(u_long);\n\t\tputshort(newrr->r_size, cp);\n                cp += sizeof(u_short);\n\t\tif (newrr->r_size) {\n\t\t\tbcopy(newrr->r_data, cp, newrr->r_size);\n\t\t\tcp += newrr->r_size;\n\t\t}\n\t\thp->ancount = htons(0);\n\t\tbreak;\n\n#endif ALLOW_UPDATES\n\t}\n\treturn (cp - buf);\n}\n"
  },
  {
    "path": "lib/libc/net/res_query.c",
    "content": "/*\n * Copyright (c) 1988 Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that this notice is preserved and that due credit is given\n * to the University of California at Berkeley. The name of the University\n * may not be used to endorse or promote products derived from this\n * software without specific prior written permission. This software\n * is provided ``as is'' without express or implied warranty.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)res_query.c\t5.3 (Berkeley) 4/5/88\";\n#endif /* LIBC_SCCS and not lint */\n\n#include <sys/param.h>\n#include <sys/socket.h>\n#include <netinet/in.h>\n#include <ctype.h>\n#include <netdb.h>\n#include <stdio.h>\n#include <errno.h>\n#include <strings.h>\n#include <arpa/inet.h>\n#include <arpa/nameser.h>\n#include <resolv.h>\n\n#if PACKETSZ > 1024\n#define MAXPACKET\tPACKETSZ\n#else\n#define MAXPACKET\t1024\n#endif\n\nextern int errno;\nint h_errno;\n\n/*\n * Formulate a normal query, send, and await answer.\n * Returned answer is placed in supplied buffer \"answer\".\n * Perform preliminary check of answer, returning success only\n * if no error is indicated and the answer count is nonzero.\n * Return the size of the response on success, -1 on error.\n * Error number is left in h_errno.\n * Caller must parse answer and determine whether it answers the question.\n */\nres_query(name, class, type, answer, anslen)\n\tchar *name;\t\t/* domain name */\n\tint class, type;\t/* class and type of query */\n\tu_char *answer;\t\t/* buffer to put answer */\n\tint anslen;\t\t/* size of answer buffer */\n{\n\tchar buf[MAXPACKET];\n\tHEADER *hp;\n\tint n;\n\n\tif ((_res.options & RES_INIT) == 0 && res_init() == -1)\n\t\treturn (-1);\n#ifdef DEBUG\n\tif (_res.options & RES_DEBUG)\n\t\tprintf(\"res_query(%s, %d, %d)\\n\", name, class, type);\n#endif\n\tn = res_mkquery(QUERY, name, class, type, (char *)NULL, 0, NULL,\n\t    buf, sizeof(buf));\n\n\tif (n <= 0) {\n#ifdef DEBUG\n\t\tif (_res.options & RES_DEBUG)\n\t\t\tprintf(\"res_query: mkquery failed\\n\");\n#endif\n\t\th_errno = NO_RECOVERY;\n\t\treturn (n);\n\t}\n\tn = res_send(buf, n, answer, anslen);\n\tif (n < 0) {\n#ifdef DEBUG\n\t\tif (_res.options & RES_DEBUG)\n\t\t\tprintf(\"res_query: send error\\n\");\n#endif\n\t\th_errno = TRY_AGAIN;\n\t\treturn(n);\n\t}\n\n\thp = (HEADER *) answer;\n\tif (hp->rcode != NOERROR || ntohs(hp->ancount) == 0) {\n#ifdef DEBUG\n\t\tif (_res.options & RES_DEBUG)\n\t\t\tprintf(\"rcode = %d, ancount=%d\\n\", hp->rcode,\n\t\t\t    ntohs(hp->ancount));\n#endif\n\t\tswitch (hp->rcode) {\n\t\t\tcase NXDOMAIN:\n\t\t\t\th_errno = HOST_NOT_FOUND;\n\t\t\t\tbreak;\n\t\t\tcase SERVFAIL:\n\t\t\t\th_errno = TRY_AGAIN;\n\t\t\t\tbreak;\n\t\t\tcase NOERROR:\n\t\t\t\th_errno = NO_DATA;\n\t\t\t\tbreak;\n\t\t\tcase FORMERR:\n\t\t\tcase NOTIMP:\n\t\t\tcase REFUSED:\n\t\t\tdefault:\n\t\t\t\th_errno = NO_RECOVERY;\n\t\t\t\tbreak;\n\t\t}\n\t\treturn (-1);\n\t}\n\treturn(n);\n}\n\n/*\n * Formulate a normal query, send, and retrieve answer in supplied buffer.\n * Return the size of the response on success, -1 on error.\n * If enabled, implement search rules until answer or unrecoverable failure\n * is detected.  Error number is left in h_errno.\n * Only useful for queries in the same name hierarchy as the local host\n * (not, for example, for host address-to-name lookups in domain in-addr.arpa).\n */\nres_search(name, class, type, answer, anslen)\n\tchar *name;\t\t/* domain name */\n\tint class, type;\t/* class and type of query */\n\tu_char *answer;\t\t/* buffer to put answer */\n\tint anslen;\t\t/* size of answer */\n{\n\tregister char *cp, **domain;\n\tint n, ret;\n\tchar *hostalias();\n\n\tif ((_res.options & RES_INIT) == 0 && res_init() == -1)\n\t\treturn (-1);\n\n\terrno = 0;\n\th_errno = HOST_NOT_FOUND;\t\t/* default, if we never query */\n\tfor (cp = name, n = 0; *cp; cp++)\n\t\tif (*cp == '.')\n\t\t\tn++;\n\tif (n == 0 && (cp = hostalias(name)))\n\t\treturn (res_query(cp, class, type, answer, anslen));\n\n\tif ((n == 0 || *--cp != '.') && (_res.options & RES_DEFNAMES))\n\t    for (domain = _res.dnsrch; *domain; domain++) {\n\t\th_errno = 0;\n\t\tret = res_querydomain(name, *domain, class, type,\n\t\t    answer, anslen);\n\t\tif (ret > 0)\n\t\t\treturn (ret);\n\t\t/*\n\t\t * If no server present, give up.\n\t\t * If name isn't found in this domain,\n\t\t * keep trying higher domains in the search list\n\t\t * (if that's enabled).\n\t\t * On a NO_DATA error, keep trying, otherwise\n\t\t * a wildcard entry of another type could keep us\n\t\t * from finding this entry higher in the domain.\n\t\t * If we get some other error (non-authoritative negative\n\t\t * answer or server failure), then stop searching up,\n\t\t * but try the input name below in case it's fully-qualified.\n\t\t */\n\t\tif (errno == ECONNREFUSED) {\n\t\t\th_errno = TRY_AGAIN;\n\t\t\treturn (-1);\n\t\t}\n\t\tif ((h_errno != HOST_NOT_FOUND && h_errno != NO_DATA) ||\n\t\t    (_res.options & RES_DNSRCH) == 0)\n\t\t\tbreak;\n\t    }\n\t/*\n\t * If the search/default failed, try the name as fully-qualified,\n\t * but only if it contained at least one dot (even trailing).\n\t */\n\tif (n)\n\t\treturn (res_querydomain(name, (char *)NULL, class, type,\n\t\t    answer, anslen));\n\treturn (-1);\n}\n\n/*\n * Perform a call on res_query on the concatenation of name and domain,\n * removing a trailing dot from name if domain is NULL.\n */\nres_querydomain(name, domain, class, type, answer, anslen)\n\tchar *name, *domain;\n\tint class, type;\t/* class and type of query */\n\tu_char *answer;\t\t/* buffer to put answer */\n\tint anslen;\t\t/* size of answer */\n{\n\tchar nbuf[2*MAXDNAME+2];\n\tchar *longname = nbuf;\n\tint n;\n\n#ifdef DEBUG\n\tif (_res.options & RES_DEBUG)\n\t\tprintf(\"res_querydomain(%s, %s, %d, %d)\\n\",\n\t\t    name, domain, class, type);\n#endif\n\tif (domain == NULL) {\n\t\t/*\n\t\t * Check for trailing '.';\n\t\t * copy without '.' if present.\n\t\t */\n\t\tn = strlen(name) - 1;\n\t\tif (name[n] == '.' && n < sizeof(nbuf) - 1) {\n\t\t\tbcopy(name, nbuf, n);\n\t\t\tnbuf[n] = '\\0';\n\t\t} else\n\t\t\tlongname = name;\n\t} else\n\t\t(void)sprintf(nbuf, \"%.*s.%.*s\",\n\t\t    MAXDNAME, name, MAXDNAME, domain);\n\n\treturn (res_query(longname, class, type, answer, anslen));\n}\n\nchar *\nhostalias(name)\n\tregister char *name;\n{\n\tregister char *C1, *C2;\n\tFILE *fp;\n\tchar *file, *getenv(), *strcpy(), *strncpy();\n\tchar buf[BUFSIZ];\n\tstatic char abuf[MAXDNAME];\n\n\tfile = getenv(\"HOSTALIASES\");\n\tif (file == NULL || (fp = fopen(file, \"r\")) == NULL)\n\t\treturn (NULL);\n\tbuf[sizeof(buf) - 1] = '\\0';\n\twhile (fgets(buf, sizeof(buf), fp)) {\n\t\tfor (C1 = buf; *C1 && !isspace(*C1); ++C1);\n\t\tif (!*C1)\n\t\t\tbreak;\n\t\t*C1 = '\\0';\n\t\tif (!strcasecmp(buf, name)) {\n\t\t\twhile (isspace(*++C1));\n\t\t\tif (!*C1)\n\t\t\t\tbreak;\n\t\t\tfor (C2 = C1 + 1; *C2 && !isspace(*C2); ++C2);\n\t\t\tabuf[sizeof(abuf) - 1] = *C2 = '\\0';\n\t\t\t(void)strncpy(abuf, C1, sizeof(abuf) - 1);\n\t\t\tfclose(fp);\n\t\t\treturn (abuf);\n\t\t}\n\t}\n\tfclose(fp);\n\treturn (NULL);\n}\n"
  },
  {
    "path": "lib/libc/net/res_send.c",
    "content": "/*\n * Copyright (c) 1985 Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that this notice is preserved and that due credit is given\n * to the University of California at Berkeley. The name of the University\n * may not be used to endorse or promote products derived from this\n * software without specific prior written permission. This software\n * is provided ``as is'' without express or implied warranty.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)res_send.c\t6.19.1 (Berkeley) 6/27/94\";\n#endif /* LIBC_SCCS and not lint */\n\n/*\n * Send query to name server and wait for reply.\n */\n\n#include <sys/param.h>\n#include <sys/time.h>\n#include <sys/socket.h>\n#include <sys/uio.h>\n#include <netinet/in.h>\n#include <stdio.h>\n#include <errno.h>\n#include <arpa/nameser.h>\n#include <resolv.h>\n\nextern int errno;\n\nstatic int s = -1;\t/* socket used for communications */\nstatic struct sockaddr no_addr;\n  \n\n#ifndef FD_SET\n#define\tNFDBITS\t\t32\n#define\tFD_SETSIZE\t32\n#define\tFD_SET(n, p)\t((p)->fds_bits[(n)/NFDBITS] |= (1 << ((n) % NFDBITS)))\n#define\tFD_CLR(n, p)\t((p)->fds_bits[(n)/NFDBITS] &= ~(1 << ((n) % NFDBITS)))\n#define\tFD_ISSET(n, p)\t((p)->fds_bits[(n)/NFDBITS] & (1 << ((n) % NFDBITS)))\n#define FD_ZERO(p)\tbzero((char *)(p), sizeof(*(p)))\n#endif\n\n#define KEEPOPEN (RES_USEVC|RES_STAYOPEN)\n\nres_send(buf, buflen, answer, anslen)\n\tchar *buf;\n\tint buflen;\n\tchar *answer;\n\tint anslen;\n{\n\tregister int n;\n\tint retry, v_circuit, resplen, ns;\n\tint gotsomewhere = 0, connected = 0;\n\tu_short id, len;\n\tchar *cp;\n\tfd_set dsmask;\n\tstruct timeval timeout;\n\tHEADER *hp = (HEADER *) buf;\n\tHEADER *anhp = (HEADER *) answer;\n\tstruct iovec iov[2];\n\tint terrno = ETIMEDOUT;\n\tchar junk[16];\n\n#ifdef DEBUG\n\tif (_res.options & RES_DEBUG) {\n\t\tprintf(\"res_send()\\n\");\n\t\tp_query(buf);\n\t}\n#endif DEBUG\n\tif (!(_res.options & RES_INIT))\n\t\tif (res_init() == -1) {\n\t\t\treturn(-1);\n\t\t}\n\tv_circuit = (_res.options & RES_USEVC) || buflen > PACKETSZ;\n\tid = hp->id;\n\t/*\n\t * Send request, RETRY times, or until successful\n\t */\n\tfor (retry = _res.retry; retry > 0; retry--) {\n\t   for (ns = 0; ns < _res.nscount; ns++) {\n#ifdef DEBUG\n\t\tif (_res.options & RES_DEBUG)\n\t\t\tprintf(\"Querying server (# %d) address = %s\\n\", ns+1,\n\t\t\t      inet_ntoa(_res.nsaddr_list[ns].sin_addr));\n#endif DEBUG\n\t\tif (v_circuit) {\n\t\t\tint truncated = 0;\n\n\t\t\t/*\n\t\t\t * Use virtual circuit.\n\t\t\t */\n\t\t\tif (s < 0) {\n\t\t\t\ts = socket(AF_INET, SOCK_STREAM, 0);\n\t\t\t\tif (s < 0) {\n\t\t\t\t\tterrno = errno;\n#ifdef DEBUG\n\t\t\t\t\tif (_res.options & RES_DEBUG)\n\t\t\t\t\t    perror(\"socket failed\");\n#endif DEBUG\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t\tif (connect(s, &(_res.nsaddr_list[ns]),\n\t\t\t\t   sizeof(struct sockaddr)) < 0) {\n\t\t\t\t\tterrno = errno;\n#ifdef DEBUG\n\t\t\t\t\tif (_res.options & RES_DEBUG)\n\t\t\t\t\t    perror(\"connect failed\");\n#endif DEBUG\n\t\t\t\t\t(void) close(s);\n\t\t\t\t\ts = -1;\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t}\n\t\t\t/*\n\t\t\t * Send length & message\n\t\t\t */\n\t\t\tlen = htons((u_short)buflen);\n\t\t\tiov[0].iov_base = (caddr_t)&len;\n\t\t\tiov[0].iov_len = sizeof(len);\n\t\t\tiov[1].iov_base = buf;\n\t\t\tiov[1].iov_len = buflen;\n\t\t\tif (writev(s, iov, 2) != sizeof(len) + buflen) {\n\t\t\t\tterrno = errno;\n#ifdef DEBUG\n\t\t\t\tif (_res.options & RES_DEBUG)\n\t\t\t\t\tperror(\"write failed\");\n#endif DEBUG\n\t\t\t\t(void) close(s);\n\t\t\t\ts = -1;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/*\n\t\t\t * Receive length & response\n\t\t\t */\n\t\t\tcp = answer;\n\t\t\tlen = sizeof(short);\n\t\t\twhile (len != 0 &&\n\t\t\t    (n = read(s, (char *)cp, (int)len)) > 0) {\n\t\t\t\tcp += n;\n\t\t\t\tlen -= n;\n\t\t\t}\n\t\t\tif (n <= 0) {\n\t\t\t\tterrno = errno;\n#ifdef DEBUG\n\t\t\t\tif (_res.options & RES_DEBUG)\n\t\t\t\t\tperror(\"read failed\");\n#endif DEBUG\n\t\t\t\t(void) close(s);\n\t\t\t\ts = -1;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tcp = answer;\n\t\t\tif ((resplen = ntohs(*(u_short *)cp)) > anslen) {\n#ifdef DEBUG\n\t\t\t\tif (_res.options & RES_DEBUG)\n\t\t\t\t\tfprintf(stderr, \"response truncated\\n\");\n#endif DEBUG\n\t\t\t\tlen = anslen;\n\t\t\t\ttruncated = 1;\n\t\t\t} else\n\t\t\t\tlen = resplen;\n\t\t\twhile (len != 0 &&\n\t\t\t   (n = read(s, (char *)cp, (int)len)) > 0) {\n\t\t\t\tcp += n;\n\t\t\t\tlen -= n;\n\t\t\t}\n\t\t\tif (n <= 0) {\n\t\t\t\tterrno = errno;\n#ifdef DEBUG\n\t\t\t\tif (_res.options & RES_DEBUG)\n\t\t\t\t\tperror(\"read failed\");\n#endif DEBUG\n\t\t\t\t(void) close(s);\n\t\t\t\ts = -1;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (truncated) {\n\t\t\t\t/*\n\t\t\t\t * Flush rest of answer\n\t\t\t\t * so connection stays in synch.\n\t\t\t\t */\n\t\t\t\tanhp->tc = 1;\n\t\t\t\tlen = resplen - anslen;\n\t\t\t\twhile (len != 0) {\n\t\t\t\t\tn = (len > sizeof(junk) ?\n\t\t\t\t\t    sizeof(junk) : len);\n\t\t\t\t\tif ((n = read(s, junk, n)) > 0)\n\t\t\t\t\t\tlen -= n;\n\t\t\t\t\telse\n\t\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\t/*\n\t\t\t * Use datagrams.\n\t\t\t */\n\t\t\tif (s < 0)\n\t\t\t\ts = socket(AF_INET, SOCK_DGRAM, 0);\n#if\tBSD >= 43\n\t\t\tif (_res.nscount == 1 || retry == _res.retry) {\n\t\t\t\t/*\n\t\t\t\t * Don't use connect if we might\n\t\t\t\t * still receive a response\n\t\t\t\t * from another server.\n\t\t\t\t */\n\t\t\t\tif (connected == 0) {\n\t\t\t\t\tif (connect(s, &_res.nsaddr_list[ns],\n\t\t\t\t\t    sizeof(struct sockaddr)) < 0) {\n#ifdef DEBUG\n\t\t\t\t\t\tif (_res.options & RES_DEBUG)\n\t\t\t\t\t\t\tperror(\"connect\");\n#endif DEBUG\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\t}\n\t\t\t\t\tconnected = 1;\n\t\t\t\t}\n\t\t\t\tif (send(s, buf, buflen, 0) != buflen) {\n#ifdef DEBUG\n\t\t\t\t\tif (_res.options & RES_DEBUG)\n\t\t\t\t\t\tperror(\"send\");\n#endif DEBUG\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t} else\n#endif BSD\n\t\t\tif (sendto(s, buf, buflen, 0, &_res.nsaddr_list[ns],\n\t\t\t    sizeof(struct sockaddr)) != buflen) {\n#ifdef DEBUG\n\t\t\t\tif (_res.options & RES_DEBUG)\n\t\t\t\t\tperror(\"sendto\");\n#endif DEBUG\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * Wait for reply\n\t\t\t */\n\t\t\ttimeout.tv_sec = (_res.retrans << (_res.retry - retry))\n\t\t\t\t/ _res.nscount;\n\t\t\tif (timeout.tv_sec <= 0)\n\t\t\t\ttimeout.tv_sec = 1;\n\t\t\ttimeout.tv_usec = 0;\nwait:\n\t\t\tFD_ZERO(&dsmask);\n\t\t\tFD_SET(s, &dsmask);\n\t\t\tn = select(s+1, &dsmask, (fd_set *)NULL,\n\t\t\t\t(fd_set *)NULL, &timeout);\n\t\t\tif (n < 0) {\n#ifdef DEBUG\n\t\t\t\tif (_res.options & RES_DEBUG)\n\t\t\t\t\tperror(\"select\");\n#endif DEBUG\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (n == 0) {\n\t\t\t\t/*\n\t\t\t\t * timeout\n\t\t\t\t */\n#ifdef DEBUG\n\t\t\t\tif (_res.options & RES_DEBUG)\n\t\t\t\t\tprintf(\"timeout\\n\");\n#endif DEBUG\n\t\t\t\t/*\n\t\t\t\t * Disconnect if we want to listen\n\t\t\t\t * for responses from more than one server.\n\t\t\t\t */\n\t\t\t\tif (_res.nscount > 1 && connected) {\n\t\t\t\t\t(void) connect(s, &no_addr,\n\t\t\t\t\t    sizeof(no_addr));\n\t\t\t\t\tconnected = 0;\n\t\t\t\t}\n\t\t\t\tgotsomewhere = 1;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif ((resplen = recv(s, answer, anslen, 0)) <= 0) {\n#ifdef DEBUG\n\t\t\t\tif (_res.options & RES_DEBUG)\n\t\t\t\t\tperror(\"recvfrom\");\n#endif DEBUG\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tgotsomewhere = 1;\n\t\t\tif (id != anhp->id) {\n\t\t\t\t/*\n\t\t\t\t * response from old query, ignore it\n\t\t\t\t */\n#ifdef DEBUG\n\t\t\t\tif (_res.options & RES_DEBUG) {\n\t\t\t\t\tprintf(\"old answer:\\n\");\n\t\t\t\t\tp_query(answer);\n\t\t\t\t}\n#endif DEBUG\n\t\t\t\tgoto wait;\n\t\t\t}\n\t\t\tif (!(_res.options & RES_IGNTC) && anhp->tc) {\n\t\t\t\t/*\n\t\t\t\t * get rest of answer\n\t\t\t\t */\n#ifdef DEBUG\n\t\t\t\tif (_res.options & RES_DEBUG)\n\t\t\t\t\tprintf(\"truncated answer\\n\");\n#endif DEBUG\n\t\t\t\t(void) close(s);\n\t\t\t\ts = -1;\n\t\t\t\t/*\n\t\t\t\t * retry decremented on continue\n\t\t\t\t * to desired starting value\n\t\t\t\t */\n\t\t\t\tretry = _res.retry + 1;\n\t\t\t\tv_circuit = 1;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t}\n#ifdef DEBUG\n\t\tif (_res.options & RES_DEBUG) {\n\t\t\tprintf(\"got answer:\\n\");\n\t\t\tp_query(answer);\n\t\t}\n#endif DEBUG\n\t\t/*\n\t\t * We are going to assume that the first server is preferred\n\t\t * over the rest (i.e. it is on the local machine) and only\n\t\t * keep that one open.\n\t\t */\n\t\tif ((_res.options & KEEPOPEN) == KEEPOPEN && ns == 0) {\n\t\t\treturn (resplen);\n\t\t} else {\n\t\t\t(void) close(s);\n\t\t\ts = -1;\n\t\t\treturn (resplen);\n\t\t}\n\t   }\n\t}\n\tif (s >= 0) {\n\t\t(void) close(s);\n\t\ts = -1;\n\t}\n\tif (v_circuit == 0)\n\t\tif (gotsomewhere == 0)\n\t\t\terrno = ECONNREFUSED;\n\t\telse\n\t\t\terrno = ETIMEDOUT;\n\telse\n\t\terrno = terrno;\n\treturn (-1);\n}\n\n/*\n * This routine is for closing the socket if a virtual circuit is used and\n * the program wants to close it.  This provides support for endhostent()\n * which expects to close the socket.\n *\n * This routine is not expected to be user visible.\n */\n_res_close()\n{\n\tif (s != -1) {\n\t\t(void) close(s);\n\t\ts = -1;\n\t}\n}\n"
  },
  {
    "path": "lib/libc/net/rexec.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)rexec.c\t5.2.1 (2.11BSD) 1997/10/2\";\n#endif LIBC_SCCS and not lint\n\n#include <sys/types.h>\n#include <sys/socket.h>\n\n#include <netinet/in.h>\n\n#include <stdio.h>\n#include <netdb.h>\n#include <errno.h>\n\nint\trexecoptions;\n\nrexec(ahost, rport, name, pass, cmd, fd2p)\n\tchar **ahost;\n\tint rport;\n\tchar *name, *pass, *cmd;\n\tint *fd2p;\n{\n\tint s, timo = 1, s3;\n\tstruct sockaddr_in sin, sin2, from;\n\tchar c;\n\tu_short port;\n\tstruct hostent *hp;\n\n\thp = gethostbyname(*ahost);\n\tif (hp == 0) {\n\t\tfprintf(stderr, \"%s: unknown host\\n\", *ahost);\n\t\treturn (-1);\n\t}\n\t*ahost = hp->h_name;\n\truserpass(hp->h_name, &name, &pass);\nretry:\n\ts = socket(AF_INET, SOCK_STREAM, 0);\n\tif (s < 0) {\n\t\tperror(\"rexec: socket\");\n\t\treturn (-1);\n\t}\n\tsin.sin_family = hp->h_addrtype;\n\tsin.sin_port = rport;\n\tbcopy(hp->h_addr, (caddr_t)&sin.sin_addr, hp->h_length);\n\tif (connect(s, &sin, sizeof(sin)) < 0) {\n\t\tif (errno == ECONNREFUSED && timo <= 16) {\n\t\t\t(void) close(s);\n\t\t\tsleep(timo);\n\t\t\ttimo *= 2;\n\t\t\tgoto retry;\n\t\t}\n\t\tperror(hp->h_name);\n\t\treturn (-1);\n\t}\n\tif (fd2p == 0) {\n\t\t(void) write(s, \"\", 1);\n\t\tport = 0;\n\t} else {\n\t\tchar num[8];\n\t\tint s2, sin2len;\n\t\t\n\t\ts2 = socket(AF_INET, SOCK_STREAM, 0);\n\t\tif (s2 < 0) {\n\t\t\t(void) close(s);\n\t\t\treturn (-1);\n\t\t}\n\t\tlisten(s2, 1);\n\t\tsin2len = sizeof (sin2);\n\t\tif (getsockname(s2, (char *)&sin2, &sin2len) < 0 ||\n\t\t  sin2len != sizeof (sin2)) {\n\t\t\tperror(\"getsockname\");\n\t\t\t(void) close(s2);\n\t\t\tgoto bad;\n\t\t}\n\t\tport = ntohs((u_short)sin2.sin_port);\n\t\t(void) sprintf(num, \"%u\", port);\n\t\t(void) write(s, num, strlen(num)+1);\n\t\t{ int len = sizeof (from);\n\t\t  s3 = accept(s2, &from, &len, 0);\n\t\t  close(s2);\n\t\t  if (s3 < 0) {\n\t\t\tperror(\"accept\");\n\t\t\tport = 0;\n\t\t\tgoto bad;\n\t\t  }\n\t\t}\n\t\t*fd2p = s3;\n\t}\n\t(void) write(s, name, strlen(name) + 1);\n\t/* should public key encypt the password here */\n\t(void) write(s, pass, strlen(pass) + 1);\n\t(void) write(s, cmd, strlen(cmd) + 1);\n\tif (read(s, &c, 1) != 1) {\n\t\tperror(*ahost);\n\t\tgoto bad;\n\t}\n\tif (c != 0) {\n\t\twhile (read(s, &c, 1) == 1) {\n\t\t\t(void) write(2, &c, 1);\n\t\t\tif (c == '\\n')\n\t\t\t\tbreak;\n\t\t}\n\t\tgoto bad;\n\t}\n\treturn (s);\nbad:\n\tif (port)\n\t\t(void) close(*fd2p);\n\t(void) close(s);\n\treturn (-1);\n}\n"
  },
  {
    "path": "lib/libc/net/ruserpass.c",
    "content": "/*\n * Copyright (c) 1983 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)ruserpass.c\t5.2.1 (2.11BSD) 1996/11/16\";\n#endif LIBC_SCCS and not lint\n\n#include <stdio.h>\n#include <utmp.h>\n#include <ctype.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <errno.h>\n#include <string.h>\n#include <unistd.h>\n#include <stdlib.h>\n\nchar\t*renvlook();\nstruct\tutmp *getutmp();\nstatic\tFILE *cfile;\n\nruserpass(host, aname, apass)\n\tchar *host, **aname, **apass;\n{\n\n\trenv(host, aname, apass);\n\tif (*aname == 0 || *apass == 0)\n\t\trnetrc(host, aname, apass);\n\tif (*aname == 0) {\n\t\tchar *myname = getlogin();\n\t\t*aname = (char *)malloc(16);\n\t\tprintf(\"Name (%s:%s): \", host, myname);\n\t\tfflush(stdout);\n\t\tif (read(2, *aname, 16) <= 0)\n\t\t\texit(1);\n\t\tif ((*aname)[0] == '\\n')\n\t\t\t*aname = myname;\n\t\telse\n\t\t\tif (index(*aname, '\\n'))\n\t\t\t\t*index(*aname, '\\n') = 0;\n\t}\n\tif (*aname && *apass == 0) {\n\t\tprintf(\"Password (%s:%s): \", host, *aname);\n\t\tfflush(stdout);\n\t\t*apass = getpass(\"\");\n\t}\n}\n\nstatic\nrenv(host, aname, apass)\n\tchar *host, **aname, **apass;\n{\n\tregister char *cp;\n\tchar *stemp, fgetlogin, *comma;\n\n\tcp = renvlook(host);\n\tif (cp == NULL)\n\t\treturn;\n\tif (!isalpha(cp[0]))\n\t\treturn;\n\tcomma = index(cp, ',');\n\tif (comma == 0)\n\t\treturn;\n\tif (*aname == 0) {\n\t\t*aname = (char *)malloc(comma - cp + 1);\n\t\tstrncpy(*aname, cp, comma - cp);\n\t} else\n\t\tif (strncmp(*aname, cp, comma - cp))\n\t\t\treturn;\n\tcomma++;\n\tcp = (char *)malloc(strlen(comma)+1);\n\tstrcpy(cp, comma);\n\t*apass = (char *)malloc(16);\n\tmkpwclear(cp, host[0], *apass);\n}\n\nstatic\nchar *\nrenvlook(host)\n\tchar *host;\n{\n\tregister char *cp, **env;\n\n\tenv = environ;\n\tfor (env = environ; *env != NULL; env++)\n\t\tif (!strncmp(*env, \"MACH\", 4)) {\n\t\t\tcp = index(*env, '=');\n\t\t\tif (cp == 0)\n\t\t\t\tcontinue;\n\t\t\tif (strncmp(*env+4, host, cp-(*env+4)))\n\t\t\t\tcontinue;\n\t\t\treturn (cp+1);\n\t\t}\n\treturn (NULL);\n}\n\n#define\tDEFAULT\t1\n#define\tLOGIN\t2\n#define\tPASSWD\t3\n#define\tNOTIFY\t4\n#define\tWRITE\t5\n#define\tYES\t6\n#define\tNO\t7\n#define\tCOMMAND\t8\n#define\tFORCE\t9\n#define\tID\t10\n#define\tMACHINE\t11\n\nstatic char tokval[100];\n\nstatic struct toktab {\n\tchar *tokstr;\n\tint tval;\n} toktab[]= {\n\t\"default\",\tDEFAULT,\n\t\"login\",\tLOGIN,\n\t\"password\",\tPASSWD,\n\t\"notify\",\tNOTIFY,\n\t\"write\",\tWRITE,\n\t\"yes\",\t\tYES,\n\t\"y\",\t\tYES,\n\t\"no\",\t\tNO,\n\t\"n\",\t\tNO,\n\t\"command\",\tCOMMAND,\n\t\"force\",\tFORCE,\n\t\"machine\",\tMACHINE,\n\t0,\t\t0\n};\n\nstatic\nrnetrc(host, aname, apass)\n\tchar *host, **aname, **apass;\n{\n\tchar *hdir, buf[BUFSIZ];\n\tint t;\n\tstruct stat stb;\n\textern int errno;\n\n\thdir = getenv(\"HOME\");\n\tif (hdir == NULL)\n\t\thdir = \".\";\n\tsprintf(buf, \"%s/.netrc\", hdir);\n\tcfile = fopen(buf, \"r\");\n\tif (cfile == NULL) {\n\t\tif (errno != ENOENT)\n\t\t\tperror(buf);\n\t\treturn;\n\t}\nnext:\n\twhile ((t = token())) switch(t) {\n\n\tcase DEFAULT:\n\t\t(void) token();\n\t\tcontinue;\n\n\tcase MACHINE:\n\t\tif (token() != ID || strcmp(host, tokval))\n\t\t\tcontinue;\n\t\twhile ((t = token()) && t != MACHINE) switch(t) {\n\n\t\tcase LOGIN:\n\t\t\tif (token())\n\t\t\t\tif (*aname == 0) {\n\t\t\t\t\t*aname = (char *)malloc(strlen(tokval) + 1);\n\t\t\t\t\tstrcpy(*aname, tokval);\n\t\t\t\t} else {\n\t\t\t\t\tif (strcmp(*aname, tokval))\n\t\t\t\t\t\tgoto next;\n\t\t\t\t}\n\t\t\tbreak;\n\t\tcase PASSWD:\n\t\t\tif (fstat(fileno(cfile), &stb) >= 0\n\t\t\t    && (stb.st_mode & 077) != 0) {\n\tfprintf(stderr, \"Error - .netrc file not correct mode.\\n\");\n\tfprintf(stderr, \"Remove password or correct mode.\\n\");\n\t\t\t\texit(1);\n\t\t\t}\n\t\t\tif (token() && *apass == 0) {\n\t\t\t\t*apass = (char *)malloc(strlen(tokval) + 1);\n\t\t\t\tstrcpy(*apass, tokval);\n\t\t\t}\n\t\t\tbreak;\n\t\tcase COMMAND:\n\t\tcase NOTIFY:\n\t\tcase WRITE:\n\t\tcase FORCE:\n\t\t\t(void) token();\n\t\t\tbreak;\n\t\tdefault:\n\tfprintf(stderr, \"Unknown .netrc option %s\\n\", tokval);\n\t\t\tbreak;\n\t\t}\n\t\tgoto done;\n\t}\ndone:\n\tfclose(cfile);\n}\n\nstatic\ntoken()\n{\n\tchar *cp;\n\tint c;\n\tstruct toktab *t;\n\n\tif (feof(cfile))\n\t\treturn (0);\n\twhile ((c = getc(cfile)) != EOF &&\n\t    (c == '\\n' || c == '\\t' || c == ' ' || c == ','))\n\t\tcontinue;\n\tif (c == EOF)\n\t\treturn (0);\n\tcp = tokval;\n\tif (c == '\"') {\n\t\twhile ((c = getc(cfile)) != EOF && c != '\"') {\n\t\t\tif (c == '\\\\')\n\t\t\t\tc = getc(cfile);\n\t\t\t*cp++ = c;\n\t\t}\n\t} else {\n\t\t*cp++ = c;\n\t\twhile ((c = getc(cfile)) != EOF\n\t\t    && c != '\\n' && c != '\\t' && c != ' ' && c != ',') {\n\t\t\tif (c == '\\\\')\n\t\t\t\tc = getc(cfile);\n\t\t\t*cp++ = c;\n\t\t}\n\t}\n\t*cp = 0;\n\tif (tokval[0] == 0)\n\t\treturn (0);\n\tfor (t = toktab; t->tokstr; t++)\n\t\tif (!strcmp(t->tokstr, tokval))\n\t\t\treturn (t->tval);\n\treturn (ID);\n}\n/* rest is nbs.c stolen from berknet */\n\nchar *deblknot(), *deblkclr();\nchar *nbs8decrypt(), *nbs8encrypt();\nstatic char\tE[48];\n\n/*\n * The E bit-selection table.\n */\nstatic char\te[] = {\n\t32, 1, 2, 3, 4, 5,\n\t 4, 5, 6, 7, 8, 9,\n\t 8, 9,10,11,12,13,\n\t12,13,14,15,16,17,\n\t16,17,18,19,20,21,\n\t20,21,22,23,24,25,\n\t24,25,26,27,28,29,\n\t28,29,30,31,32, 1,\n};\nstatic\nchar *nbsencrypt(str,key,result)\n  char *result;\n  char *str, *key; {\n\tstatic char buf[20],oldbuf[20];\n\tregister int j;\n\tresult[0] = 0;\n\tstrcpy(oldbuf,key);\n\twhile(*str){\n\t\tfor(j=0;j<10;j++)buf[j] = 0;\n\t\tfor(j=0;j<8 && *str;j++)buf[j] = *str++;\n\t\tstrcat(result,nbs8encrypt(buf,oldbuf));\n\t\tstrcat(result,\"$\");\n\t\tstrcpy(oldbuf,buf);\n\t\t}\n\treturn(result);\n\t}\nstatic\nchar *nbsdecrypt(cpt,key,result)\n  char *result;\n  char *cpt,*key; {\n\tchar *s;\n\tchar c,oldbuf[20];\n\tresult[0] = 0;\n\tstrcpy(oldbuf,key);\n\twhile(*cpt){\n\t\tfor(s = cpt;*s && *s != '$';s++);\n\t\tc = *s;\n\t\t*s = 0;\n\t\tstrcpy(oldbuf,nbs8decrypt(cpt,oldbuf));\n\t\tstrcat(result,oldbuf);\n\t\tif(c == 0)break;\n\t\tcpt = s + 1;\n\t\t}\n\treturn(result);\n\t}\n\nstatic\nchar *nbs8encrypt(str,key)\nchar *str, *key; {\n\tstatic char keyblk[100], blk[100];\n\tregister int i;\n\n\tenblkclr(keyblk,key);\n\tnbssetkey(keyblk);\n\n\tfor(i=0;i<48;i++) E[i] = e[i];\n\tenblkclr(blk,str);\n\tblkencrypt(blk,0);\t\t\t/* forward dir */\n\n\treturn(deblknot(blk));\n}\n\nstatic\nchar *nbs8decrypt(crp,key)\nchar *crp, *key; {\n\tstatic char keyblk[100], blk[100];\n\tregister int i;\n\n\tenblkclr(keyblk,key);\n\tnbssetkey(keyblk);\n\n\tfor(i=0;i<48;i++) E[i] = e[i];\n\tenblknot(blk,crp);\n\tblkencrypt(blk,1);\t\t\t/* backward dir */\n\n\treturn(deblkclr(blk));\n}\n\nstatic\nenblkclr(blk,str)\t\t/* ignores top bit of chars in string str */\nchar *blk,*str; {\n\tregister int i,j;\n\tchar c;\n\tfor(i=0;i<70;i++)blk[i] = 0;\n\tfor(i=0; (c= *str) && i<64; str++){\n\t\tfor(j=0; j<7; j++, i++)\n\t\t\tblk[i] = (c>>(6-j)) & 01;\n\t\ti++;\n\t\t}\n\t}\n\nstatic\nchar *deblkclr(blk)\nchar *blk; {\n\tregister int i,j;\n\tchar c;\n\tstatic char iobuf[30];\n\tfor(i=0; i<10; i++){\n\t\tc = 0;\n\t\tfor(j=0; j<7; j++){\n\t\t\tc <<= 1;\n\t\t\tc |= blk[8*i+j];\n\t\t\t}\n\t\tiobuf[i] = c;\n\t}\n\tiobuf[i] = 0;\n\treturn(iobuf);\n\t}\n\nstatic\nenblknot(blk,crp)\nchar *blk;\nchar *crp; {\n\tregister int i,j;\n\tchar c;\n\tfor(i=0;i<70;i++)blk[i] = 0;\n\tfor(i=0; (c= *crp) && i<64; crp++){\n\t\tif(c>'Z') c -= 6;\n\t\tif(c>'9') c -= 7;\n\t\tc -= '.';\n\t\tfor(j=0; j<6; j++, i++)\n\t\t\tblk[i] = (c>>(5-j)) & 01;\n\t\t}\n\t}\n\nstatic\nchar *deblknot(blk)\nchar *blk; {\n\tregister int i,j;\n\tchar c;\n\tstatic char iobuf[30];\n\tfor(i=0; i<11; i++){\n\t\tc = 0;\n\t\tfor(j=0; j<6; j++){\n\t\t\tc <<= 1;\n\t\t\tc |= blk[6*i+j];\n\t\t\t}\n\t\tc += '.';\n\t\tif(c > '9')c += 7;\n\t\tif(c > 'Z')c += 6;\n\t\tiobuf[i] = c;\n\t}\n\tiobuf[i] = 0;\n\treturn(iobuf);\n}\n\n/*\n * This program implements the\n * Proposed Federal Information Processing\n *  Data Encryption Standard.\n * See Federal Register, March 17, 1975 (40FR12134)\n */\n\n/*\n * Initial permutation,\n */\nstatic\tchar\tIP[] = {\n\t58,50,42,34,26,18,10, 2,\n\t60,52,44,36,28,20,12, 4,\n\t62,54,46,38,30,22,14, 6,\n\t64,56,48,40,32,24,16, 8,\n\t57,49,41,33,25,17, 9, 1,\n\t59,51,43,35,27,19,11, 3,\n\t61,53,45,37,29,21,13, 5,\n\t63,55,47,39,31,23,15, 7,\n};\n\n/*\n * Final permutation, FP = IP^(-1)\n */\nstatic\tchar\tFP[] = {\n\t40, 8,48,16,56,24,64,32,\n\t39, 7,47,15,55,23,63,31,\n\t38, 6,46,14,54,22,62,30,\n\t37, 5,45,13,53,21,61,29,\n\t36, 4,44,12,52,20,60,28,\n\t35, 3,43,11,51,19,59,27,\n\t34, 2,42,10,50,18,58,26,\n\t33, 1,41, 9,49,17,57,25,\n};\n\n/*\n * Permuted-choice 1 from the key bits\n * to yield C and D.\n * Note that bits 8,16... are left out:\n * They are intended for a parity check.\n */\nstatic\tchar\tPC1_C[] = {\n\t57,49,41,33,25,17, 9,\n\t 1,58,50,42,34,26,18,\n\t10, 2,59,51,43,35,27,\n\t19,11, 3,60,52,44,36,\n};\n\nstatic\tchar\tPC1_D[] = {\n\t63,55,47,39,31,23,15,\n\t 7,62,54,46,38,30,22,\n\t14, 6,61,53,45,37,29,\n\t21,13, 5,28,20,12, 4,\n};\n\n/*\n * Sequence of shifts used for the key schedule.\n*/\nstatic\tchar\tshifts[] = {\n\t1,1,2,2,2,2,2,2,1,2,2,2,2,2,2,1,\n};\n\n/*\n * Permuted-choice 2, to pick out the bits from\n * the CD array that generate the key schedule.\n */\nstatic\tchar\tPC2_C[] = {\n\t14,17,11,24, 1, 5,\n\t 3,28,15, 6,21,10,\n\t23,19,12, 4,26, 8,\n\t16, 7,27,20,13, 2,\n};\n\nstatic\tchar\tPC2_D[] = {\n\t41,52,31,37,47,55,\n\t30,40,51,45,33,48,\n\t44,49,39,56,34,53,\n\t46,42,50,36,29,32,\n};\n\n/*\n * The C and D arrays used to calculate the key schedule.\n */\n\nstatic\tchar\tC[28];\nstatic\tchar\tD[28];\n/*\n * The key schedule.\n * Generated from the key.\n */\nstatic\tchar\tKS[16][48];\n\n/*\n * Set up the key schedule from the key.\n */\n\nstatic\nnbssetkey(key)\nchar *key;\n{\n\tregister i, j, k;\n\tint t;\n\n\t/*\n\t * First, generate C and D by permuting\n\t * the key.  The low order bit of each\n\t * 8-bit char is not used, so C and D are only 28\n\t * bits apiece.\n\t */\n\tfor (i=0; i<28; i++) {\n\t\tC[i] = key[PC1_C[i]-1];\n\t\tD[i] = key[PC1_D[i]-1];\n\t}\n\t/*\n\t * To generate Ki, rotate C and D according\n\t * to schedule and pick up a permutation\n\t * using PC2.\n\t */\n\tfor (i=0; i<16; i++) {\n\t\t/*\n\t\t * rotate.\n\t\t */\n\t\tfor (k=0; k<shifts[i]; k++) {\n\t\t\tt = C[0];\n\t\t\tfor (j=0; j<28-1; j++)\n\t\t\t\tC[j] = C[j+1];\n\t\t\tC[27] = t;\n\t\t\tt = D[0];\n\t\t\tfor (j=0; j<28-1; j++)\n\t\t\t\tD[j] = D[j+1];\n\t\t\tD[27] = t;\n\t\t}\n\t\t/*\n\t\t * get Ki. Note C and D are concatenated.\n\t\t */\n\t\tfor (j=0; j<24; j++) {\n\t\t\tKS[i][j] = C[PC2_C[j]-1];\n\t\t\tKS[i][j+24] = D[PC2_D[j]-28-1];\n\t\t}\n\t}\n}\n\n\n/*\n * The 8 selection functions.\n * For some reason, they give a 0-origin\n * index, unlike everything else.\n */\nstatic\tchar\tS[8][64] = {\n\t14, 4,13, 1, 2,15,11, 8, 3,10, 6,12, 5, 9, 0, 7,\n\t 0,15, 7, 4,14, 2,13, 1,10, 6,12,11, 9, 5, 3, 8,\n\t 4, 1,14, 8,13, 6, 2,11,15,12, 9, 7, 3,10, 5, 0,\n\t15,12, 8, 2, 4, 9, 1, 7, 5,11, 3,14,10, 0, 6,13,\n\n\t15, 1, 8,14, 6,11, 3, 4, 9, 7, 2,13,12, 0, 5,10,\n\t 3,13, 4, 7,15, 2, 8,14,12, 0, 1,10, 6, 9,11, 5,\n\t 0,14, 7,11,10, 4,13, 1, 5, 8,12, 6, 9, 3, 2,15,\n\t13, 8,10, 1, 3,15, 4, 2,11, 6, 7,12, 0, 5,14, 9,\n\n\t10, 0, 9,14, 6, 3,15, 5, 1,13,12, 7,11, 4, 2, 8,\n\t13, 7, 0, 9, 3, 4, 6,10, 2, 8, 5,14,12,11,15, 1,\n\t13, 6, 4, 9, 8,15, 3, 0,11, 1, 2,12, 5,10,14, 7,\n\t 1,10,13, 0, 6, 9, 8, 7, 4,15,14, 3,11, 5, 2,12,\n\n\t 7,13,14, 3, 0, 6, 9,10, 1, 2, 8, 5,11,12, 4,15,\n\t13, 8,11, 5, 6,15, 0, 3, 4, 7, 2,12, 1,10,14, 9,\n\t10, 6, 9, 0,12,11, 7,13,15, 1, 3,14, 5, 2, 8, 4,\n\t 3,15, 0, 6,10, 1,13, 8, 9, 4, 5,11,12, 7, 2,14,\n\n\t 2,12, 4, 1, 7,10,11, 6, 8, 5, 3,15,13, 0,14, 9,\n\t14,11, 2,12, 4, 7,13, 1, 5, 0,15,10, 3, 9, 8, 6,\n\t 4, 2, 1,11,10,13, 7, 8,15, 9,12, 5, 6, 3, 0,14,\n\t11, 8,12, 7, 1,14, 2,13, 6,15, 0, 9,10, 4, 5, 3,\n\n\t12, 1,10,15, 9, 2, 6, 8, 0,13, 3, 4,14, 7, 5,11,\n\t10,15, 4, 2, 7,12, 9, 5, 6, 1,13,14, 0,11, 3, 8,\n\t 9,14,15, 5, 2, 8,12, 3, 7, 0, 4,10, 1,13,11, 6,\n\t 4, 3, 2,12, 9, 5,15,10,11,14, 1, 7, 6, 0, 8,13,\n\n\t 4,11, 2,14,15, 0, 8,13, 3,12, 9, 7, 5,10, 6, 1,\n\t13, 0,11, 7, 4, 9, 1,10,14, 3, 5,12, 2,15, 8, 6,\n\t 1, 4,11,13,12, 3, 7,14,10,15, 6, 8, 0, 5, 9, 2,\n\t 6,11,13, 8, 1, 4,10, 7, 9, 5, 0,15,14, 2, 3,12,\n\n\t13, 2, 8, 4, 6,15,11, 1,10, 9, 3,14, 5, 0,12, 7,\n\t 1,15,13, 8,10, 3, 7, 4,12, 5, 6,11, 0,14, 9, 2,\n\t 7,11, 4, 1, 9,12,14, 2, 0, 6,10,13,15, 3, 5, 8,\n\t 2, 1,14, 7, 4,10, 8,13,15,12, 9, 0, 3, 5, 6,11,\n};\n\n/*\n * P is a permutation on the selected combination\n * of the current L and key.\n */\nstatic\tchar\tP[] = {\n\t16, 7,20,21,\n\t29,12,28,17,\n\t 1,15,23,26,\n\t 5,18,31,10,\n\t 2, 8,24,14,\n\t32,27, 3, 9,\n\t19,13,30, 6,\n\t22,11, 4,25,\n};\n\n/*\n * The current block, divided into 2 halves.\n */\nstatic\tchar\tL[32], R[32];\nstatic\tchar\ttempL[32];\nstatic\tchar\tf[32];\n\n/*\n * The combination of the key and the input, before selection.\n */\nstatic\tchar\tpreS[48];\n\n/*\n * The payoff: encrypt a block.\n */\n\nstatic\nblkencrypt(block, edflag)\nchar *block;\n{\n\tint i, ii;\n\tregister t, j, k;\n\n\t/*\n\t * First, permute the bits in the input\n\t */\n\tfor (j=0; j<64; j++)\n\t\tL[j] = block[IP[j]-1];\n\t/*\n\t * Perform an encryption operation 16 times.\n\t */\n\tfor (ii=0; ii<16; ii++) {\n\t\t/*\n\t\t * Set direction\n\t\t */\n\t\tif (edflag)\n\t\t\ti = 15-ii;\n\t\telse\n\t\t\ti = ii;\n\t\t/*\n\t\t * Save the R array,\n\t\t * which will be the new L.\n\t\t */\n\t\tfor (j=0; j<32; j++)\n\t\t\ttempL[j] = R[j];\n\t\t/*\n\t\t * Expand R to 48 bits using the E selector;\n\t\t * exclusive-or with the current key bits.\n\t\t */\n\t\tfor (j=0; j<48; j++)\n\t\t\tpreS[j] = R[E[j]-1] ^ KS[i][j];\n\t\t/*\n\t\t * The pre-select bits are now considered\n\t\t * in 8 groups of 6 bits each.\n\t\t * The 8 selection functions map these\n\t\t * 6-bit quantities into 4-bit quantities\n\t\t * and the results permuted\n\t\t * to make an f(R, K).\n\t\t * The indexing into the selection functions\n\t\t * is peculiar; it could be simplified by\n\t\t * rewriting the tables.\n\t\t */\n\t\tfor (j=0; j<8; j++) {\n\t\t\tt = 6*j;\n\t\t\tk = S[j][(preS[t+0]<<5)+\n\t\t\t\t(preS[t+1]<<3)+\n\t\t\t\t(preS[t+2]<<2)+\n\t\t\t\t(preS[t+3]<<1)+\n\t\t\t\t(preS[t+4]<<0)+\n\t\t\t\t(preS[t+5]<<4)];\n\t\t\tt = 4*j;\n\t\t\tf[t+0] = (k>>3)&01;\n\t\t\tf[t+1] = (k>>2)&01;\n\t\t\tf[t+2] = (k>>1)&01;\n\t\t\tf[t+3] = (k>>0)&01;\n\t\t}\n\t\t/*\n\t\t * The new R is L ^ f(R, K).\n\t\t * The f here has to be permuted first, though.\n\t\t */\n\t\tfor (j=0; j<32; j++)\n\t\t\tR[j] = L[j] ^ f[P[j]-1];\n\t\t/*\n\t\t * Finally, the new L (the original R)\n\t\t * is copied back.\n\t\t */\n\t\tfor (j=0; j<32; j++)\n\t\t\tL[j] = tempL[j];\n\t}\n\t/*\n\t * The output L and R are reversed.\n\t */\n\tfor (j=0; j<32; j++) {\n\t\tt = L[j];\n\t\tL[j] = R[j];\n\t\tR[j] = t;\n\t}\n\t/*\n\t * The final output\n\t * gets the inverse permutation of the very original.\n\t */\n\tfor (j=0; j<64; j++)\n\t\tblock[j] = L[FP[j]-1];\n}\n/*\n\tgetutmp()\n\treturn a pointer to the system utmp structure associated with\n\tterminal sttyname, e.g. \"/dev/tty3\"\n\tIs version independent-- will work on v6 systems\n\treturn NULL if error\n*/\nstatic\nstruct utmp *getutmp(sttyname)\nchar *sttyname;\n{\n\tstatic struct utmp utmpstr;\n\tFILE *fdutmp;\n\n\tif(sttyname == NULL || sttyname[0] == 0)return(NULL);\n\n\tfdutmp = fopen(_PATH_UTMP,\"r\");\n\tif(fdutmp == NULL)return(NULL);\n\n\twhile(fread(&utmpstr,1,sizeof utmpstr,fdutmp) == sizeof utmpstr)\n\t\tif(strcmp(utmpstr.ut_line,sttyname+5) == 0){\n\t\t\tfclose(fdutmp);\n\t\t\treturn(&utmpstr);\n\t\t}\n\tfclose(fdutmp);\n\treturn(NULL);\n}\n\nstatic\nsreverse(sto, sfrom)\n\tregister char *sto, *sfrom;\n{\n\tregister int i;\n\n\ti = strlen(sfrom);\n\twhile (i >= 0)\n\t\t*sto++ = sfrom[i--];\n}\n\nstatic\nchar *mkenvkey(mch)\n\tchar mch;\n{\n\tstatic char skey[40];\n\tregister struct utmp *putmp;\n\tchar stemp[40], stemp1[40], sttyname[30];\n\tregister char *sk,*p;\n\n\tif (isatty(2))\n\t\tstrcpy(sttyname,ttyname(2));\n\telse if (isatty(0))\n\t\tstrcpy(sttyname,ttyname(0));\n\telse if (isatty(1))\n\t\tstrcpy(sttyname,ttyname(1));\n\telse\n\t\treturn (NULL);\n\tputmp = getutmp(sttyname);\n\tif (putmp == NULL)\n\t\treturn (NULL);\n\tsk = skey;\n\tp = putmp->ut_line;\n\twhile (*p)\n\t\t*sk++ = *p++;\n\t*sk++ = mch;\n\tsprintf(stemp, \"%ld\", putmp->ut_time);\n\tsreverse(stemp1, stemp);\n\tp = stemp1;\n\twhile (*p)\n\t\t*sk++ = *p++;\n\t*sk = 0;\n\treturn (skey);\n}\n\nmkpwunclear(spasswd,mch,sencpasswd)\n\tchar mch, *spasswd, *sencpasswd;\n{\n\tregister char *skey;\n\n\tif (spasswd[0] == 0) {\n\t\tsencpasswd[0] = 0;\n\t\treturn;\n\t}\n\tskey = mkenvkey(mch);\n\tif (skey == NULL) {\n\t\tfprintf(stderr, \"Can't make key\\n\");\n\t\texit(1);\n\t}\n\tnbsencrypt(spasswd, skey, sencpasswd);\n}\n\nmkpwclear(sencpasswd,mch,spasswd)\n\tchar mch, *spasswd, *sencpasswd;\n{\n\tregister char *skey;\n\n\tif (sencpasswd[0] == 0) {\n\t\tspasswd[0] = 0;\n\t\treturn;\n\t}\n\tskey = mkenvkey(mch);\n\tif (skey == NULL) {\n\t\tfprintf(stderr, \"Can't make key\\n\");\n\t\texit(1);\n\t}\n\tnbsdecrypt(sencpasswd, skey, spasswd);\n}\n"
  },
  {
    "path": "lib/libc/ns/Makefile",
    "content": "#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n#\t@(#)Makefile\t6.1 (Berkeley) 1/29/86\n#\n\nSRCS=\tns_addr.c ns_ntoa.c\nOBJS=\tns_addr.o ns_ntoa.o\nCFLAGS+= ${DEFS}\nTAGSFILE=tags\n\n.c.o:\n\t${CC} -p -c ${CFLAGS} $*.c\n\t-ld -X -r $*.o\n\tmv a.out profiled/$*.o\n\t${CC} ${CFLAGS} -c $*.c\n\t-ld -x -r $*.o\n\tmv a.out $*.o\n\nnslib nslib_p: ${OBJS}\n\t@echo \"building profiled nslib\"\n\t@cd profiled; ${AR} cr ../nslib_p ${OBJS}\n\t@echo \"building normal nslib\"\n\t@${AR} cr nslib ${OBJS}\n\ntags:\n\tcwd=`pwd`; \\\n\tfor i in ${SRCS}; do \\\n\t\tctags -a -f ${TAGSFILE} $$cwd/$$i; \\\n\tdone\n\nclean:\n\trm -f nslib nslib_p *.o profiled/*.o errs a.out core \\\n\t\ttags Makefile.bak\n\ndepend:\n\tfor i in ${SRCS}; do \\\n\t    cc -M ${CFLAGS} $$i | awk ' { if ($$1 != prev) \\\n\t\t{ if (rec != \"\") print rec; rec = $$0; prev = $$1; } \\\n\t\telse { if (length(rec $$2) > 78) { print rec; rec = $$0; } \\\n\t\telse rec = rec \" \" $$2 } } \\\n\t\tEND { print rec } ' >> makedep; done\n\techo '/^# DO NOT DELETE THIS LINE/+2,$$d' >eddep\n\techo '$$r makedep' >>eddep\n\techo 'w' >>eddep\n\tcp Makefile Makefile.bak\n\ted - Makefile < eddep\n\trm eddep makedep\n\techo '# DEPENDENCIES MUST END AT END OF FILE' >> Makefile\n\techo '# IF YOU PUT STUFF HERE IT WILL GO AWAY' >> Makefile\n\techo '# see make depend above' >> Makefile\n\n# DO NOT DELETE THIS LINE -- make depend uses it\n\nns_addr.o: ns_addr.c /usr/include/sys/types.h /usr/include/netns/ns.h\nns_ntoa.o: ns_ntoa.c /usr/include/sys/types.h /usr/include/netns/ns.h\n# DEPENDENCIES MUST END AT END OF FILE\n# IF YOU PUT STUFF HERE IT WILL GO AWAY\n# see make depend above\n"
  },
  {
    "path": "lib/libc/ns/ns_addr.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n * Includes material written at Cornell University, by J. Q. Johnson.\n * Used by permission.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)ns_addr.c\t6.2 (Berkeley) 3/9/86\";\n#endif LIBC_SCCS and not lint\n\n#include <sys/types.h>\n#include <netns/ns.h>\n\nstatic struct ns_addr addr, zero_addr;\n\nstruct ns_addr \nns_addr(name)\n\tchar *name;\n{\n\tu_long net;\n\tu_short socket;\n\tchar separator = '.';\n\tchar *hostname, *socketname, *cp;\n\tchar buf[50];\n\textern char *index();\n\n\taddr = zero_addr;\n\tstrncpy(buf, name, 49);\n\n\t/*\n\t * First, figure out what he intends as a field separtor.\n\t * Despite the way this routine is written, the prefered\n\t * form  2-272.AA001234H.01777, i.e. XDE standard.\n\t * Great efforts are made to insure backward compatability.\n\t */\n\tif (hostname = index(buf, '#'))\n\t\tseparator = '#';\n\telse {\n\t\thostname = index(buf, '.');\n\t\tif ((cp = index(buf, ':')) &&\n\t\t    ( (hostname && cp < hostname) || (hostname == 0))) {\n\t\t\thostname = cp;\n\t\t\tseparator = ':';\n\t\t}\n\t}\n\tif (hostname)\n\t\t*hostname++ = 0;\n\tField(buf, addr.x_net.c_net, 4);\n\tif (hostname == 0)\n\t\treturn (addr);  /* No separator means net only */\n\n\tsocketname = index(hostname, separator);\n\tif (socketname) {\n\t\t*socketname++ = 0;\n\t\tField(socketname, &addr.x_port, 2);\n\t}\n\n\tField(hostname, addr.x_host.c_host, 6);\n\n\treturn (addr);\n}\n\nstatic\nField(buf, out, len)\nchar *buf;\nu_char *out;\nint len;\n{\n\tregister char *bp = buf;\n\tint i, ibase, base16 = 0, base10 = 0, clen = 0;\n\tint hb[6], *hp;\n\tchar *fmt;\n\n\t/*\n\t * first try 2-273#2-852-151-014#socket\n\t */\n\tif ((*buf != '-') &&\n\t    (1 < (i = sscanf(buf, \"%d-%d-%d-%d-%d\",\n\t\t\t&hb[0], &hb[1], &hb[2], &hb[3], &hb[4])))) {\n\t\tcvtbase(1000, 256, hb, i, out, len);\n\t\treturn;\n\t}\n\t/*\n\t * try form 8E1#0.0.AA.0.5E.E6#socket\n\t */\n\tif (1 < (i = sscanf(buf,\"%x.%x.%x.%x.%x.%x\",\n\t\t\t&hb[0], &hb[1], &hb[2], &hb[3], &hb[4], &hb[5]))) {\n\t\tcvtbase(256, 256, hb, i, out, len);\n\t\treturn;\n\t}\n\t/*\n\t * try form 8E1#0:0:AA:0:5E:E6#socket\n\t */\n\tif (1 < (i = sscanf(buf,\"%x:%x:%x:%x:%x:%x\",\n\t\t\t&hb[0], &hb[1], &hb[2], &hb[3], &hb[4], &hb[5]))) {\n\t\tcvtbase(256, 256, hb, i, out, len);\n\t\treturn;\n\t}\n\t/*\n\t * This is REALLY stretching it but there was a\n\t * comma notation separting shorts -- definitely non standard\n\t */\n\tif (1 < (i = sscanf(buf,\"%x,%x,%x\",\n\t\t\t&hb[0], &hb[1], &hb[2]))) {\n\t\thb[0] = htons(hb[0]); hb[1] = htons(hb[1]);\n\t\thb[2] = htons(hb[2]);\n\t\tcvtbase(65536, 256, hb, i, out, len);\n\t\treturn;\n\t}\n\n\t/* Need to decide if base 10, 16 or 8 */\n\twhile (*bp) switch (*bp++) {\n\n\tcase '0': case '1': case '2': case '3': case '4': case '5':\n\tcase '6': case '7': case '-':\n\t\tbreak;\n\n\tcase '8': case '9':\n\t\tbase10 = 1;\n\t\tbreak;\n\n\tcase 'a': case 'b': case 'c': case 'd': case 'e': case 'f':\n\tcase 'A': case 'B': case 'C': case 'D': case 'E': case 'F':\n\t\tbase16 = 1;\n\t\tbreak;\n\t\n\tcase 'x': case 'X':\n\t\t*--bp = '0';\n\t\tbase16 = 1;\n\t\tbreak;\n\n\tcase 'h': case 'H':\n\t\tbase16 = 1;\n\t\t/* fall into */\n\n\tdefault:\n\t\t*--bp = 0; /* Ends Loop */\n\t}\n\tif (base16) {\n\t\tfmt = \"%3x\";\n\t\tibase = 4096;\n\t} else if (base10 == 0 && *buf == '0') {\n\t\tfmt = \"%3o\";\n\t\tibase = 512;\n\t} else {\n\t\tfmt = \"%3d\";\n\t\tibase = 1000;\n\t}\n\n\tfor (bp = buf; *bp++; ) clen++;\n\tif (clen == 0) clen++;\n\tif (clen > 18) clen = 18;\n\ti = ((clen - 1) / 3) + 1;\n\tbp = clen + buf - 3;\n\thp = hb + i - 1;\n\n\twhile (hp > hb) {\n\t\tsscanf(bp, fmt, hp);\n\t\tbp[0] = 0;\n\t\thp--;\n\t\tbp -= 3;\n\t}\n\tsscanf(buf, fmt, hp);\n\tcvtbase(ibase, 256, hb, i, out, len);\n}\n\nstatic\ncvtbase(oldbase,newbase,input,inlen,result,reslen)\n\tlong oldbase;\n\tint newbase;\n\tint input[];\n\tint inlen;\n\tunsigned char result[];\n\tint reslen;\n{\n\tint d, e;\n\tlong sum;\n\n\te = 1;\n\twhile (e > 0 && reslen > 0) {\n\t\td = 0; e = 0; sum = 0;\n\t\t/* long division: input=input/newbase */\n\t\twhile (d < inlen) {\n\t\t\tsum = sum*oldbase + (long) input[d];\n\t\t\te += (sum > 0);\n\t\t\tinput[d++] = sum / newbase;\n\t\t\tsum %= newbase;\n\t\t}\n\t\tresult[--reslen] = sum;\t/* accumulate remainder */\n\t}\n\tfor (d=0; d < reslen; d++)\n\t\tresult[d] = 0;\n}\n"
  },
  {
    "path": "lib/libc/ns/ns_ntoa.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)ns_ntoa.c\t6.3 (Berkeley) 3/9/86\";\n#endif LIBC_SCCS and not lint\n\n#include <sys/types.h>\n#include <netns/ns.h>\n\nchar *\nns_ntoa(addr)\nstruct ns_addr addr;\n{\n\tstatic char obuf[40];\n\tchar *spectHex();\n\tunion { union ns_net net_e; u_long long_e; } net;\n\tu_short port = htons(addr.x_port);\n\tregister char *cp;\n\tchar *cp2;\n\tregister u_char *up = addr.x_host.c_host;\n\tu_char *uplim = up + 6;\n\n\tnet.net_e = addr.x_net;\n\tsprintf(obuf, \"%lx\", ntohl(net.long_e));\n\tcp = spectHex(obuf);\n\tcp2 = cp + 1;\n\twhile (*up==0 && up < uplim) up++;\n\tif (up == uplim) {\n\t\tif (port) {\n\t\t\tsprintf(cp, \".0\");\n\t\t\tcp += 2;\n\t\t}\n\t} else {\n\t\tsprintf(cp, \".%x\", *up++);\n\t\twhile (up < uplim) {\n\t\t\twhile (*cp) cp++;\n\t\t\tsprintf(cp, \"%02x\", *up++);\n\t\t}\n\t\tcp = spectHex(cp2);\n\t}\n\tif (port) {\n\t\tsprintf(cp, \".%x\", port);\n\t\tspectHex(cp + 1);\n\t}\n\treturn (obuf);\n}\n\nstatic char *\nspectHex(p0)\nchar *p0;\n{\n\tint ok = 0;\n\tint nonzero = 0;\n\tregister char *p = p0;\n\tfor (; *p; p++) switch (*p) {\n\n\tcase 'a': case 'b': case 'c': case 'd': case 'e': case 'f':\n\t\t*p += ('A' - 'a');\n\t\t/* fall into . . . */\n\tcase 'A': case 'B': case 'C': case 'D': case 'E': case 'F':\n\t\tok = 1;\n\tcase '1': case '2': case '3': case '4': case '5':\n\tcase '6': case '7': case '8': case '9':\n\t\tnonzero = 1;\n\t}\n\tif (nonzero && !ok) { *p++ = 'H'; *p = 0; }\n\treturn (p);\n}\n"
  },
  {
    "path": "lib/libc/runtime/CREDITS.txt",
    "content": "This file is a partial list of people who have contributed to the LLVM/CompilerRT\nproject.  If you have contributed a patch or made some other contribution to\nLLVM/CompilerRT, please submit a patch to this file to add yourself, and it will be\ndone!\n\nThe list is sorted by surname and formatted to allow easy grepping and\nbeautification by scripts.  The fields are: name (N), email (E), web-address\n(W), PGP key ID and fingerprint (P), description (D), and snail-mail address\n(S).\n\nN: Craig van Vliet\nE: cvanvliet@auroraux.org\nW: http://www.auroraux.org\nD: Code style and Readability fixes.\n\nN: Edward O'Callaghan\nE: eocallaghan@auroraux.org\nW: http://www.auroraux.org\nD: CMake'ify Compiler-RT build system\nD: Maintain Solaris & AuroraUX ports of Compiler-RT\n\nN: Howard Hinnant\nE: hhinnant@apple.com\nD: Architect and primary author of compiler-rt\n\nN: Guan-Hong Liu\nE: koviankevin@hotmail.com\nD: IEEE Quad-precision functions\n\nN: Joerg Sonnenberger\nE: joerg@NetBSD.org\nD: Maintains NetBSD port.\n\nN: Matt Thomas\nE: matt@NetBSD.org\nD: ARM improvements.\n"
  },
  {
    "path": "lib/libc/runtime/LICENSE.txt",
    "content": "==============================================================================\ncompiler_rt License\n==============================================================================\n\nThe compiler_rt library is dual licensed under both the University of Illinois\n\"BSD-Like\" license and the MIT license.  As a user of this code you may choose\nto use it under either license.  As a contributor, you agree to allow your code\nto be used under both.\n\nFull text of the relevant licenses is included below.\n\n==============================================================================\n\nUniversity of Illinois/NCSA\nOpen Source License\n\nCopyright (c) 2009-2018 by the contributors listed in CREDITS.TXT\n\nAll rights reserved.\n\nDeveloped by:\n\n    LLVM Team\n\n    University of Illinois at Urbana-Champaign\n\n    http://llvm.org\n\nPermission is hereby granted, free of charge, to any person obtaining a copy of\nthis software and associated documentation files (the \"Software\"), to deal with\nthe Software without restriction, including without limitation the rights to\nuse, copy, modify, merge, publish, distribute, sublicense, and/or sell copies\nof the Software, and to permit persons to whom the Software is furnished to do\nso, subject to the following conditions:\n\n    * Redistributions of source code must retain the above copyright notice,\n      this list of conditions and the following disclaimers.\n\n    * Redistributions in binary form must reproduce the above copyright notice,\n      this list of conditions and the following disclaimers in the\n      documentation and/or other materials provided with the distribution.\n\n    * Neither the names of the LLVM Team, University of Illinois at\n      Urbana-Champaign, nor the names of its contributors may be used to\n      endorse or promote products derived from this Software without specific\n      prior written permission.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\nFOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE\nCONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE\nSOFTWARE.\n\n==============================================================================\n\nCopyright (c) 2009-2015 by the contributors listed in CREDITS.TXT\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\nall copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE.\n\n==============================================================================\nCopyrights and Licenses for Third Party Software Distributed with LLVM:\n==============================================================================\nThe LLVM software contains code written by third parties.  Such software will\nhave its own individual LICENSE.TXT file in the directory in which it appears.\nThis file will describe the copyrights, license, and restrictions which apply\nto that code.\n\nThe disclaimer of warranty in the University of Illinois Open Source License\napplies to all code in the LLVM Distribution, and nothing in any of the\nother licenses gives permission to use the names of the LLVM Team or the\nUniversity of Illinois to endorse or promote products derived from this\nSoftware.\n\n"
  },
  {
    "path": "lib/libc/runtime/Makefile",
    "content": "#\n# Copyright (c) 1988 Regents of the University of California.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms are permitted\n# provided that the above copyright notice and this paragraph are\n# duplicated in all such forms and that any documentation, advertising\n# materials, and other materials related to such redistribution and\n# use acknowledge that the software was developed by the University\n# of California, Berkeley.  The name of the University may not be\n# used to endorse or promote products derived from this software\n# without specific prior written permission.  THIS SOFTWARE IS PROVIDED\n# ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,\n# WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND\n# FITNESS FOR A PARTICULAR PURPOSE.\n#\nTOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS          += ${DEFS}\n\nOBJS=\t\taddsf3.o comparesf2.o divsf3.o fixsfsi.o fixunssfsi.o \\\n\t\tfloatsisf.o floatunsisf.o mulsf3.o negsf2.o subsf3.o \\\n\t\tadddf3.o comparedf2.o divdf3.o fixdfsi.o fixunsdfsi.o \\\n\t\tfloatsidf.o floatunsidf.o muldf3.o negdf2.o subdf3.o \\\n\t\tashldi3.o lshrdi3.o \\\n\t\tsc_case.o\n\nall:\t\t${OBJS}\n\nclean:\n\t\trm -f *.a *.o *~ profiled/*.o tags\n\ncleandir:       clean\n\t\trm -f .depend\n\ninstall:        all\n#\t\tcp ../libgcc.a ${DESTDIR}/usr/lib/\n#\t\t$(RANLIB) -t ${DESTDIR}/usr/lib/libgcc.a\n#\t\tcp libgcc_p.a ${DESTDIR}/usr/lib/\n#\t\t$(RANLIB) -t ${DESTDIR}/usr/lib/libgcc_p.a\n"
  },
  {
    "path": "lib/libc/runtime/README.txt",
    "content": "Compiler-RT\n================================\n\nThis directory and its subdirectories contain source code for the compiler\nsupport routines.\n\nCompiler-RT is open source software. You may freely distribute it under the\nterms of the license agreement found in LICENSE.txt.\n\n================================\n\nThis is a replacement library for libgcc.  Each function is contained\nin its own file.  Each function has a corresponding unit test under\ntest/Unit.\n\nA rudimentary script to test each file is in the file called\ntest/Unit/test.\n\nHere is the specification for this library:\n\nhttp://gcc.gnu.org/onlinedocs/gccint/Libgcc.html#Libgcc\n\nHere is a synopsis of the contents of this library:\n\ntypedef      int si_int;\ntypedef unsigned su_int;\n\ntypedef          long long di_int;\ntypedef unsigned long long du_int;\n\n// Integral bit manipulation\n\ndi_int __ashldi3(di_int a, si_int b);      // a << b\nti_int __ashlti3(ti_int a, si_int b);      // a << b\n\ndi_int __ashrdi3(di_int a, si_int b);      // a >> b  arithmetic (sign fill)\nti_int __ashrti3(ti_int a, si_int b);      // a >> b  arithmetic (sign fill)\ndi_int __lshrdi3(di_int a, si_int b);      // a >> b  logical    (zero fill)\nti_int __lshrti3(ti_int a, si_int b);      // a >> b  logical    (zero fill)\n\nsi_int __clzsi2(si_int a);  // count leading zeros\nsi_int __clzdi2(di_int a);  // count leading zeros\nsi_int __clzti2(ti_int a);  // count leading zeros\nsi_int __ctzsi2(si_int a);  // count trailing zeros\nsi_int __ctzdi2(di_int a);  // count trailing zeros\nsi_int __ctzti2(ti_int a);  // count trailing zeros\n\nsi_int __ffssi2(si_int a);  // find least significant 1 bit\nsi_int __ffsdi2(di_int a);  // find least significant 1 bit\nsi_int __ffsti2(ti_int a);  // find least significant 1 bit\n\nsi_int __paritysi2(si_int a);  // bit parity\nsi_int __paritydi2(di_int a);  // bit parity\nsi_int __parityti2(ti_int a);  // bit parity\n\nsi_int __popcountsi2(si_int a);  // bit population\nsi_int __popcountdi2(di_int a);  // bit population\nsi_int __popcountti2(ti_int a);  // bit population\n\nuint32_t __bswapsi2(uint32_t a);   // a byteswapped\nuint64_t __bswapdi2(uint64_t a);   // a byteswapped\n\n// Integral arithmetic\n\ndi_int __negdi2    (di_int a);                         // -a\nti_int __negti2    (ti_int a);                         // -a\ndi_int __muldi3    (di_int a, di_int b);               // a * b\nti_int __multi3    (ti_int a, ti_int b);               // a * b\nsi_int __divsi3    (si_int a, si_int b);               // a / b   signed\ndi_int __divdi3    (di_int a, di_int b);               // a / b   signed\nti_int __divti3    (ti_int a, ti_int b);               // a / b   signed\nsu_int __udivsi3   (su_int n, su_int d);               // a / b   unsigned\ndu_int __udivdi3   (du_int a, du_int b);               // a / b   unsigned\ntu_int __udivti3   (tu_int a, tu_int b);               // a / b   unsigned\nsi_int __modsi3    (si_int a, si_int b);               // a % b   signed\ndi_int __moddi3    (di_int a, di_int b);               // a % b   signed\nti_int __modti3    (ti_int a, ti_int b);               // a % b   signed\nsu_int __umodsi3   (su_int a, su_int b);               // a % b   unsigned\ndu_int __umoddi3   (du_int a, du_int b);               // a % b   unsigned\ntu_int __umodti3   (tu_int a, tu_int b);               // a % b   unsigned\ndu_int __udivmoddi4(du_int a, du_int b, du_int* rem);  // a / b, *rem = a % b  unsigned\ntu_int __udivmodti4(tu_int a, tu_int b, tu_int* rem);  // a / b, *rem = a % b  unsigned\nsu_int __udivmodsi4(su_int a, su_int b, su_int* rem);  // a / b, *rem = a % b  unsigned\nsi_int __divmodsi4(si_int a, si_int b, si_int* rem);   // a / b, *rem = a % b  signed\n\n\n\n//  Integral arithmetic with trapping overflow\n\nsi_int __absvsi2(si_int a);           // abs(a)\ndi_int __absvdi2(di_int a);           // abs(a)\nti_int __absvti2(ti_int a);           // abs(a)\n\nsi_int __negvsi2(si_int a);           // -a\ndi_int __negvdi2(di_int a);           // -a\nti_int __negvti2(ti_int a);           // -a\n\nsi_int __addvsi3(si_int a, si_int b);  // a + b\ndi_int __addvdi3(di_int a, di_int b);  // a + b\nti_int __addvti3(ti_int a, ti_int b);  // a + b\n\nsi_int __subvsi3(si_int a, si_int b);  // a - b\ndi_int __subvdi3(di_int a, di_int b);  // a - b\nti_int __subvti3(ti_int a, ti_int b);  // a - b\n\nsi_int __mulvsi3(si_int a, si_int b);  // a * b\ndi_int __mulvdi3(di_int a, di_int b);  // a * b\nti_int __mulvti3(ti_int a, ti_int b);  // a * b\n\n\n// Integral arithmetic which returns if overflow\n\nsi_int __mulosi4(si_int a, si_int b, int* overflow);  // a * b, overflow set to one if result not in signed range\ndi_int __mulodi4(di_int a, di_int b, int* overflow);  // a * b, overflow set to one if result not in signed range\nti_int __muloti4(ti_int a, ti_int b, int* overflow);  // a * b, overflow set to\n one if result not in signed range\n\n\n//  Integral comparison: a  < b -> 0\n//                       a == b -> 1\n//                       a  > b -> 2\n\nsi_int __cmpdi2 (di_int a, di_int b);\nsi_int __cmpti2 (ti_int a, ti_int b);\nsi_int __ucmpdi2(du_int a, du_int b);\nsi_int __ucmpti2(tu_int a, tu_int b);\n\n//  Integral / floating point conversion\n\ndi_int __fixsfdi(      float a);\ndi_int __fixdfdi(     double a);\ndi_int __fixxfdi(long double a);\n\nti_int __fixsfti(      float a);\nti_int __fixdfti(     double a);\nti_int __fixxfti(long double a);\nuint64_t __fixtfdi(long double input);  // ppc only, doesn't match documentation\n\nsu_int __fixunssfsi(      float a);\nsu_int __fixunsdfsi(     double a);\nsu_int __fixunsxfsi(long double a);\n\ndu_int __fixunssfdi(      float a);\ndu_int __fixunsdfdi(     double a);\ndu_int __fixunsxfdi(long double a);\n\ntu_int __fixunssfti(      float a);\ntu_int __fixunsdfti(     double a);\ntu_int __fixunsxfti(long double a);\nuint64_t __fixunstfdi(long double input);  // ppc only\n\nfloat       __floatdisf(di_int a);\ndouble      __floatdidf(di_int a);\nlong double __floatdixf(di_int a);\nlong double __floatditf(int64_t a);        // ppc only\n\nfloat       __floattisf(ti_int a);\ndouble      __floattidf(ti_int a);\nlong double __floattixf(ti_int a);\n\nfloat       __floatundisf(du_int a);\ndouble      __floatundidf(du_int a);\nlong double __floatundixf(du_int a);\nlong double __floatunditf(uint64_t a);     // ppc only\n\nfloat       __floatuntisf(tu_int a);\ndouble      __floatuntidf(tu_int a);\nlong double __floatuntixf(tu_int a);\n\n//  Floating point raised to integer power\n\nfloat       __powisf2(      float a, si_int b);  // a ^ b\ndouble      __powidf2(     double a, si_int b);  // a ^ b\nlong double __powixf2(long double a, si_int b);  // a ^ b\nlong double __powitf2(long double a, si_int b);  // ppc only, a ^ b\n\n//  Complex arithmetic\n\n//  (a + ib) * (c + id)\n\n      float _Complex __mulsc3( float a,  float b,  float c,  float d);\n     double _Complex __muldc3(double a, double b, double c, double d);\nlong double _Complex __mulxc3(long double a, long double b,\n                              long double c, long double d);\nlong double _Complex __multc3(long double a, long double b,\n                              long double c, long double d); // ppc only\n\n//  (a + ib) / (c + id)\n\n      float _Complex __divsc3( float a,  float b,  float c,  float d);\n     double _Complex __divdc3(double a, double b, double c, double d);\nlong double _Complex __divxc3(long double a, long double b,\n                              long double c, long double d);\nlong double _Complex __divtc3(long double a, long double b,\n                              long double c, long double d);  // ppc only\n\n\n//         Runtime support\n\n// __clear_cache() is used to tell process that new instructions have been\n// written to an address range.  Necessary on processors that do not have\n// a unified instruction and data cache.\nvoid __clear_cache(void* start, void* end);\n\n// __enable_execute_stack() is used with nested functions when a trampoline\n// function is written onto the stack and that page range needs to be made\n// executable.\nvoid __enable_execute_stack(void* addr);\n\n// __gcc_personality_v0() is normally only called by the system unwinder.\n// C code (as opposed to C++) normally does not need a personality function\n// because there are no catch clauses or destructors to be run.  But there\n// is a C language extension __attribute__((cleanup(func))) which marks local\n// variables as needing the cleanup function \"func\" to be run when the\n// variable goes out of scope.  That includes when an exception is thrown,\n// so a personality handler is needed.\n_Unwind_Reason_Code __gcc_personality_v0(int version, _Unwind_Action actions,\n         uint64_t exceptionClass, struct _Unwind_Exception* exceptionObject,\n         _Unwind_Context_t context);\n\n// for use with some implementations of assert() in <assert.h>\nvoid __eprintf(const char* format, const char* assertion_expression,\n\t\t\t\tconst char* line, const char* file);\n\n// for systems with emulated thread local storage\nvoid* __emutls_get_address(struct __emutls_control*);\n\n\n//   Power PC specific functions\n\n// There is no C interface to the saveFP/restFP functions.  They are helper\n// functions called by the prolog and epilog of functions that need to save\n// a number of non-volatile float point registers.\nsaveFP\nrestFP\n\n// PowerPC has a standard template for trampoline functions.  This function\n// generates a custom trampoline function with the specific realFunc\n// and localsPtr values.\nvoid __trampoline_setup(uint32_t* trampOnStack, int trampSizeAllocated,\n                                const void* realFunc, void* localsPtr);\n\n// adds two 128-bit double-double precision values ( x + y )\nlong double __gcc_qadd(long double x, long double y);\n\n// subtracts two 128-bit double-double precision values ( x - y )\nlong double __gcc_qsub(long double x, long double y);\n\n// multiples two 128-bit double-double precision values ( x * y )\nlong double __gcc_qmul(long double x, long double y);\n\n// divides two 128-bit double-double precision values ( x / y )\nlong double __gcc_qdiv(long double a, long double b);\n\n\n//    ARM specific functions\n\n// There is no C interface to the switch* functions.  These helper functions\n// are only needed by Thumb1 code for efficient switch table generation.\nswitch16\nswitch32\nswitch8\nswitchu8\n\n// There is no C interface to the *_vfp_d8_d15_regs functions.  There are\n// called in the prolog and epilog of Thumb1 functions.  When the C++ ABI use\n// SJLJ for exceptions, each function with a catch clause or destructors needs\n// to save and restore all registers in it prolog and epilog.  But there is\n// no way to access vector and high float registers from thumb1 code, so the\n// compiler must add call outs to these helper functions in the prolog and\n// epilog.\nrestore_vfp_d8_d15_regs\nsave_vfp_d8_d15_regs\n\n\n// Note: long ago ARM processors did not have floating point hardware support.\n// Floating point was done in software and floating point parameters were\n// passed in integer registers.  When hardware support was added for floating\n// point, new *vfp functions were added to do the same operations but with\n// floating point parameters in floating point registers.\n\n// Undocumented functions\n\nfloat  __addsf3vfp(float a, float b);   // Appears to return a + b\ndouble __adddf3vfp(double a, double b); // Appears to return a + b\nfloat  __divsf3vfp(float a, float b);   // Appears to return a / b\ndouble __divdf3vfp(double a, double b); // Appears to return a / b\nint    __eqsf2vfp(float a, float b);    // Appears to return  one\n                                        //     iff a == b and neither is NaN.\nint    __eqdf2vfp(double a, double b);  // Appears to return  one\n                                        //     iff a == b and neither is NaN.\ndouble __extendsfdf2vfp(float a);       // Appears to convert from\n                                        //     float to double.\nint    __fixdfsivfp(double a);          // Appears to convert from\n                                        //     double to int.\nint    __fixsfsivfp(float a);           // Appears to convert from\n                                        //     float to int.\nunsigned int __fixunssfsivfp(float a);  // Appears to convert from\n                                        //     float to unsigned int.\nunsigned int __fixunsdfsivfp(double a); // Appears to convert from\n                                        //     double to unsigned int.\ndouble __floatsidfvfp(int a);           // Appears to convert from\n                                        //     int to double.\nfloat __floatsisfvfp(int a);            // Appears to convert from\n                                        //     int to float.\ndouble __floatunssidfvfp(unsigned int a); // Appears to convert from\n                                        //     unsigned int to double.\nfloat __floatunssisfvfp(unsigned int a); // Appears to convert from\n                                        //     unsigned int to float.\nint __gedf2vfp(double a, double b);     // Appears to return __gedf2\n                                        //     (a >= b)\nint __gesf2vfp(float a, float b);       // Appears to return __gesf2\n                                        //     (a >= b)\nint __gtdf2vfp(double a, double b);     // Appears to return __gtdf2\n                                        //     (a > b)\nint __gtsf2vfp(float a, float b);       // Appears to return __gtsf2\n                                        //     (a > b)\nint __ledf2vfp(double a, double b);     // Appears to return __ledf2\n                                        //     (a <= b)\nint __lesf2vfp(float a, float b);       // Appears to return __lesf2\n                                        //     (a <= b)\nint __ltdf2vfp(double a, double b);     // Appears to return __ltdf2\n                                        //     (a < b)\nint __ltsf2vfp(float a, float b);       // Appears to return __ltsf2\n                                        //     (a < b)\ndouble __muldf3vfp(double a, double b); // Appears to return a * b\nfloat __mulsf3vfp(float a, float b);    // Appears to return a * b\nint __nedf2vfp(double a, double b);     // Appears to return __nedf2\n                                        //     (a != b)\ndouble __negdf2vfp(double a);           // Appears to return -a\nfloat __negsf2vfp(float a);             // Appears to return -a\nfloat __negsf2vfp(float a);             // Appears to return -a\ndouble __subdf3vfp(double a, double b); // Appears to return a - b\nfloat __subsf3vfp(float a, float b);    // Appears to return a - b\nfloat __truncdfsf2vfp(double a);        // Appears to convert from\n                                        //     double to float.\nint __unorddf2vfp(double a, double b);  // Appears to return __unorddf2\nint __unordsf2vfp(float a, float b);    // Appears to return __unordsf2\n\n\nPreconditions are listed for each function at the definition when there are any.\nAny preconditions reflect the specification at\nhttp://gcc.gnu.org/onlinedocs/gccint/Libgcc.html#Libgcc.\n\nAssumptions are listed in \"int_lib.h\", and in individual files.  Where possible\nassumptions are checked at compile time.\n"
  },
  {
    "path": "lib/libc/runtime/adddf3.c",
    "content": "//===-- lib/adddf3.c - Double-precision addition ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements double-precision soft-float addition with the IEEE-754\n// default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_add_impl.inc\"\n\nCOMPILER_RT_ABI double __adddf3(double a, double b){\n    return __addXf3__(a, b);\n}\n\n#if defined(__ARM_EABI__)\n#if defined(COMPILER_RT_ARMHF_TARGET)\nAEABI_RTABI double __aeabi_dadd(double a, double b) {\n  return __adddf3(a, b);\n}\n#else\nAEABI_RTABI double __aeabi_dadd(double a, double b) COMPILER_RT_ALIAS(__adddf3);\n#endif\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/addsf3.c",
    "content": "//===-- lib/addsf3.c - Single-precision addition ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements single-precision soft-float addition with the IEEE-754\n// default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_add_impl.inc\"\n\nCOMPILER_RT_ABI float __addsf3(float a, float b) {\n    return __addXf3__(a, b);\n}\n\n#if defined(__ARM_EABI__)\n#if defined(COMPILER_RT_ARMHF_TARGET)\nAEABI_RTABI float __aeabi_fadd(float a, float b) {\n  return __addsf3(a, b);\n}\n#else\nAEABI_RTABI float __aeabi_fadd(float a, float b) COMPILER_RT_ALIAS(__addsf3);\n#endif\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/ashldi3.c",
    "content": "/* ====-- ashldi3.c - Implement __ashldi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __ashldi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: a << b */\n\n/* Precondition:  0 <= b < bits_in_dword */\n\nCOMPILER_RT_ABI di_int\n__ashldi3(di_int a, si_int b)\n{\n    const int bits_in_word = (int)(sizeof(si_int) * CHAR_BIT);\n    dwords input;\n    dwords result;\n    input.all = a;\n    if (b & bits_in_word)  /* bits_in_word <= b < bits_in_dword */\n    {\n        result.s.low = 0;\n        result.s.high = input.s.low << (b - bits_in_word);\n    }\n    else  /* 0 <= b < bits_in_word */\n    {\n        if (b == 0)\n            return a;\n        result.s.low  = input.s.low << b;\n        result.s.high = (input.s.high << b) | (input.s.low >> (bits_in_word - b));\n    }\n    return result.all;\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI di_int __aeabi_llsl(di_int a, si_int b) COMPILER_RT_ALIAS(__ashldi3);\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/comparedf2.c",
    "content": "//===-- lib/comparedf2.c - Double-precision comparisons -----------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// // This file implements the following soft-float comparison routines:\n//\n//   __eqdf2   __gedf2   __unorddf2\n//   __ledf2   __gtdf2\n//   __ltdf2\n//   __nedf2\n//\n// The semantics of the routines grouped in each column are identical, so there\n// is a single implementation for each, and wrappers to provide the other names.\n//\n// The main routines behave as follows:\n//\n//   __ledf2(a,b) returns -1 if a < b\n//                         0 if a == b\n//                         1 if a > b\n//                         1 if either a or b is NaN\n//\n//   __gedf2(a,b) returns -1 if a < b\n//                         0 if a == b\n//                         1 if a > b\n//                        -1 if either a or b is NaN\n//\n//   __unorddf2(a,b) returns 0 if both a and b are numbers\n//                           1 if either a or b is NaN\n//\n// Note that __ledf2( ) and __gedf2( ) are identical except in their handling of\n// NaN values.\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\nenum LE_RESULT {\n    LE_LESS      = -1,\n    LE_EQUAL     =  0,\n    LE_GREATER   =  1,\n    LE_UNORDERED =  1\n};\n\nCOMPILER_RT_ABI enum LE_RESULT\n__ledf2(fp_t a, fp_t b) {\n\n    const srep_t aInt = toRep(a);\n    const srep_t bInt = toRep(b);\n    const rep_t aAbs = aInt & absMask;\n    const rep_t bAbs = bInt & absMask;\n\n    // If either a or b is NaN, they are unordered.\n    if (aAbs > infRep || bAbs > infRep) return LE_UNORDERED;\n\n    // If a and b are both zeros, they are equal.\n    if ((aAbs | bAbs) == 0) return LE_EQUAL;\n\n    // If at least one of a and b is positive, we get the same result comparing\n    // a and b as signed integers as we would with a floating-point compare.\n    if ((aInt & bInt) >= 0) {\n        if (aInt < bInt) return LE_LESS;\n        else if (aInt == bInt) return LE_EQUAL;\n        else return LE_GREATER;\n    }\n\n    // Otherwise, both are negative, so we need to flip the sense of the\n    // comparison to get the correct result.  (This assumes a twos- or ones-\n    // complement integer representation; if integers are represented in a\n    // sign-magnitude representation, then this flip is incorrect).\n    else {\n        if (aInt > bInt) return LE_LESS;\n        else if (aInt == bInt) return LE_EQUAL;\n        else return LE_GREATER;\n    }\n}\n\n#if defined(__ELF__)\n// Alias for libgcc compatibility\nFNALIAS(__cmpdf2, __ledf2);\n#endif\n\nenum GE_RESULT {\n    GE_LESS      = -1,\n    GE_EQUAL     =  0,\n    GE_GREATER   =  1,\n    GE_UNORDERED = -1   // Note: different from LE_UNORDERED\n};\n\nCOMPILER_RT_ABI enum GE_RESULT\n__gedf2(fp_t a, fp_t b) {\n\n    const srep_t aInt = toRep(a);\n    const srep_t bInt = toRep(b);\n    const rep_t aAbs = aInt & absMask;\n    const rep_t bAbs = bInt & absMask;\n\n    if (aAbs > infRep || bAbs > infRep) return GE_UNORDERED;\n    if ((aAbs | bAbs) == 0) return GE_EQUAL;\n    if ((aInt & bInt) >= 0) {\n        if (aInt < bInt) return GE_LESS;\n        else if (aInt == bInt) return GE_EQUAL;\n        else return GE_GREATER;\n    } else {\n        if (aInt > bInt) return GE_LESS;\n        else if (aInt == bInt) return GE_EQUAL;\n        else return GE_GREATER;\n    }\n}\n\nCOMPILER_RT_ABI int\n__unorddf2(fp_t a, fp_t b) {\n    const rep_t aAbs = toRep(a) & absMask;\n    const rep_t bAbs = toRep(b) & absMask;\n    return aAbs > infRep || bAbs > infRep;\n}\n\n// The following are alternative names for the preceding routines.\n\nCOMPILER_RT_ABI enum LE_RESULT\n__eqdf2(fp_t a, fp_t b) {\n    return __ledf2(a, b);\n}\n\nCOMPILER_RT_ABI enum LE_RESULT\n__ltdf2(fp_t a, fp_t b) {\n    return __ledf2(a, b);\n}\n\nCOMPILER_RT_ABI enum LE_RESULT\n__nedf2(fp_t a, fp_t b) {\n    return __ledf2(a, b);\n}\n\nCOMPILER_RT_ABI enum GE_RESULT\n__gtdf2(fp_t a, fp_t b) {\n    return __gedf2(a, b);\n}\n\n#if defined(__ARM_EABI__)\n#if defined(COMPILER_RT_ARMHF_TARGET)\nAEABI_RTABI int __aeabi_dcmpun(fp_t a, fp_t b) {\n  return __unorddf2(a, b);\n}\n#else\nAEABI_RTABI int __aeabi_dcmpun(fp_t a, fp_t b) COMPILER_RT_ALIAS(__unorddf2);\n#endif\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/comparesf2.c",
    "content": "//===-- lib/comparesf2.c - Single-precision comparisons -----------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements the following soft-float comparison routines:\n//\n//   __eqsf2   __gesf2   __unordsf2\n//   __lesf2   __gtsf2\n//   __ltsf2\n//   __nesf2\n//\n// The semantics of the routines grouped in each column are identical, so there\n// is a single implementation for each, and wrappers to provide the other names.\n//\n// The main routines behave as follows:\n//\n//   __lesf2(a,b) returns -1 if a < b\n//                         0 if a == b\n//                         1 if a > b\n//                         1 if either a or b is NaN\n//\n//   __gesf2(a,b) returns -1 if a < b\n//                         0 if a == b\n//                         1 if a > b\n//                        -1 if either a or b is NaN\n//\n//   __unordsf2(a,b) returns 0 if both a and b are numbers\n//                           1 if either a or b is NaN\n//\n// Note that __lesf2( ) and __gesf2( ) are identical except in their handling of\n// NaN values.\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\nenum LE_RESULT {\n    LE_LESS      = -1,\n    LE_EQUAL     =  0,\n    LE_GREATER   =  1,\n    LE_UNORDERED =  1\n};\n\nCOMPILER_RT_ABI enum LE_RESULT\n__lesf2(fp_t a, fp_t b) {\n\n    const srep_t aInt = toRep(a);\n    const srep_t bInt = toRep(b);\n    const rep_t aAbs = aInt & absMask;\n    const rep_t bAbs = bInt & absMask;\n\n    // If either a or b is NaN, they are unordered.\n    if (aAbs > infRep || bAbs > infRep) return LE_UNORDERED;\n\n    // If a and b are both zeros, they are equal.\n    if ((aAbs | bAbs) == 0) return LE_EQUAL;\n\n    // If at least one of a and b is positive, we get the same result comparing\n    // a and b as signed integers as we would with a floating-point compare.\n    if ((aInt & bInt) >= 0) {\n        if (aInt < bInt) return LE_LESS;\n        else if (aInt == bInt) return LE_EQUAL;\n        else return LE_GREATER;\n    }\n\n    // Otherwise, both are negative, so we need to flip the sense of the\n    // comparison to get the correct result.  (This assumes a twos- or ones-\n    // complement integer representation; if integers are represented in a\n    // sign-magnitude representation, then this flip is incorrect).\n    else {\n        if (aInt > bInt) return LE_LESS;\n        else if (aInt == bInt) return LE_EQUAL;\n        else return LE_GREATER;\n    }\n}\n\n#if defined(__ELF__)\n// Alias for libgcc compatibility\nFNALIAS(__cmpsf2, __lesf2);\n#endif\n\nenum GE_RESULT {\n    GE_LESS      = -1,\n    GE_EQUAL     =  0,\n    GE_GREATER   =  1,\n    GE_UNORDERED = -1   // Note: different from LE_UNORDERED\n};\n\nCOMPILER_RT_ABI enum GE_RESULT\n__gesf2(fp_t a, fp_t b) {\n\n    const srep_t aInt = toRep(a);\n    const srep_t bInt = toRep(b);\n    const rep_t aAbs = aInt & absMask;\n    const rep_t bAbs = bInt & absMask;\n\n    if (aAbs > infRep || bAbs > infRep) return GE_UNORDERED;\n    if ((aAbs | bAbs) == 0) return GE_EQUAL;\n    if ((aInt & bInt) >= 0) {\n        if (aInt < bInt) return GE_LESS;\n        else if (aInt == bInt) return GE_EQUAL;\n        else return GE_GREATER;\n    } else {\n        if (aInt > bInt) return GE_LESS;\n        else if (aInt == bInt) return GE_EQUAL;\n        else return GE_GREATER;\n    }\n}\n\nCOMPILER_RT_ABI int\n__unordsf2(fp_t a, fp_t b) {\n    const rep_t aAbs = toRep(a) & absMask;\n    const rep_t bAbs = toRep(b) & absMask;\n    return aAbs > infRep || bAbs > infRep;\n}\n\n// The following are alternative names for the preceding routines.\n\nCOMPILER_RT_ABI enum LE_RESULT\n__eqsf2(fp_t a, fp_t b) {\n    return __lesf2(a, b);\n}\n\nCOMPILER_RT_ABI enum LE_RESULT\n__ltsf2(fp_t a, fp_t b) {\n    return __lesf2(a, b);\n}\n\nCOMPILER_RT_ABI enum LE_RESULT\n__nesf2(fp_t a, fp_t b) {\n    return __lesf2(a, b);\n}\n\nCOMPILER_RT_ABI enum GE_RESULT\n__gtsf2(fp_t a, fp_t b) {\n    return __gesf2(a, b);\n}\n\n#if defined(__ARM_EABI__)\n#if defined(COMPILER_RT_ARMHF_TARGET)\nAEABI_RTABI int __aeabi_fcmpun(fp_t a, fp_t b) {\n  return __unordsf2(a, b);\n}\n#else\nAEABI_RTABI int __aeabi_fcmpun(fp_t a, fp_t b) COMPILER_RT_ALIAS(__unordsf2);\n#endif\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/divdf3.c",
    "content": "//===-- lib/divdf3.c - Double-precision division ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements double-precision soft-float division\n// with the IEEE-754 default rounding (to nearest, ties to even).\n//\n// For simplicity, this implementation currently flushes denormals to zero.\n// It should be a fairly straightforward exercise to implement gradual\n// underflow with correct rounding.\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__divdf3(fp_t a, fp_t b) {\n\n    const unsigned int aExponent = toRep(a) >> significandBits & maxExponent;\n    const unsigned int bExponent = toRep(b) >> significandBits & maxExponent;\n    const rep_t quotientSign = (toRep(a) ^ toRep(b)) & signBit;\n\n    rep_t aSignificand = toRep(a) & significandMask;\n    rep_t bSignificand = toRep(b) & significandMask;\n    int scale = 0;\n\n    // Detect if a or b is zero, denormal, infinity, or NaN.\n    if (aExponent-1U >= maxExponent-1U || bExponent-1U >= maxExponent-1U) {\n\n        const rep_t aAbs = toRep(a) & absMask;\n        const rep_t bAbs = toRep(b) & absMask;\n\n        // NaN / anything = qNaN\n        if (aAbs > infRep) return fromRep(toRep(a) | quietBit);\n        // anything / NaN = qNaN\n        if (bAbs > infRep) return fromRep(toRep(b) | quietBit);\n\n        if (aAbs == infRep) {\n            // infinity / infinity = NaN\n            if (bAbs == infRep) return fromRep(qnanRep);\n            // infinity / anything else = +/- infinity\n            else return fromRep(aAbs | quotientSign);\n        }\n\n        // anything else / infinity = +/- 0\n        if (bAbs == infRep) return fromRep(quotientSign);\n\n        if (!aAbs) {\n            // zero / zero = NaN\n            if (!bAbs) return fromRep(qnanRep);\n            // zero / anything else = +/- zero\n            else return fromRep(quotientSign);\n        }\n        // anything else / zero = +/- infinity\n        if (!bAbs) return fromRep(infRep | quotientSign);\n\n        // one or both of a or b is denormal, the other (if applicable) is a\n        // normal number.  Renormalize one or both of a and b, and set scale to\n        // include the necessary exponent adjustment.\n        if (aAbs < implicitBit) scale += normalize(&aSignificand);\n        if (bAbs < implicitBit) scale -= normalize(&bSignificand);\n    }\n\n    // Or in the implicit significand bit.  (If we fell through from the\n    // denormal path it was already set by normalize( ), but setting it twice\n    // won't hurt anything.)\n    aSignificand |= implicitBit;\n    bSignificand |= implicitBit;\n    int quotientExponent = aExponent - bExponent + scale;\n\n    // Align the significand of b as a Q31 fixed-point number in the range\n    // [1, 2.0) and get a Q32 approximate reciprocal using a small minimax\n    // polynomial approximation: reciprocal = 3/4 + 1/sqrt(2) - b/2.  This\n    // is accurate to about 3.5 binary digits.\n    const uint32_t q31b = bSignificand >> 21;\n    uint32_t recip32 = UINT32_C(0x7504f333) - q31b;\n\n    // Now refine the reciprocal estimate using a Newton-Raphson iteration:\n    //\n    //     x1 = x0 * (2 - x0 * b)\n    //\n    // This doubles the number of correct binary digits in the approximation\n    // with each iteration, so after three iterations, we have about 28 binary\n    // digits of accuracy.\n    uint32_t correction32;\n    correction32 = -((uint64_t)recip32 * q31b >> 32);\n    recip32 = (uint64_t)recip32 * correction32 >> 31;\n    correction32 = -((uint64_t)recip32 * q31b >> 32);\n    recip32 = (uint64_t)recip32 * correction32 >> 31;\n    correction32 = -((uint64_t)recip32 * q31b >> 32);\n    recip32 = (uint64_t)recip32 * correction32 >> 31;\n\n    // recip32 might have overflowed to exactly zero in the preceding\n    // computation if the high word of b is exactly 1.0.  This would sabotage\n    // the full-width final stage of the computation that follows, so we adjust\n    // recip32 downward by one bit.\n    recip32--;\n\n    // We need to perform one more iteration to get us to 56 binary digits;\n    // The last iteration needs to happen with extra precision.\n    const uint32_t q63blo = bSignificand << 11;\n    uint64_t correction, reciprocal;\n    correction = -((uint64_t)recip32*q31b + ((uint64_t)recip32*q63blo >> 32));\n    uint32_t cHi = correction >> 32;\n    uint32_t cLo = correction;\n    reciprocal = (uint64_t)recip32*cHi + ((uint64_t)recip32*cLo >> 32);\n\n    // We already adjusted the 32-bit estimate, now we need to adjust the final\n    // 64-bit reciprocal estimate downward to ensure that it is strictly smaller\n    // than the infinitely precise exact reciprocal.  Because the computation\n    // of the Newton-Raphson step is truncating at every step, this adjustment\n    // is small; most of the work is already done.\n    reciprocal -= 2;\n\n    // The numerical reciprocal is accurate to within 2^-56, lies in the\n    // interval [0.5, 1.0), and is strictly smaller than the true reciprocal\n    // of b.  Multiplying a by this reciprocal thus gives a numerical q = a/b\n    // in Q53 with the following properties:\n    //\n    //    1. q < a/b\n    //    2. q is in the interval [0.5, 2.0)\n    //    3. the error in q is bounded away from 2^-53 (actually, we have a\n    //       couple of bits to spare, but this is all we need).\n\n    // We need a 64 x 64 multiply high to compute q, which isn't a basic\n    // operation in C, so we need to be a little bit fussy.\n    rep_t quotient, quotientLo;\n    wideMultiply(aSignificand << 2, reciprocal, &quotient, &quotientLo);\n\n    // Two cases: quotient is in [0.5, 1.0) or quotient is in [1.0, 2.0).\n    // In either case, we are going to compute a residual of the form\n    //\n    //     r = a - q*b\n    //\n    // We know from the construction of q that r satisfies:\n    //\n    //     0 <= r < ulp(q)*b\n    //\n    // if r is greater than 1/2 ulp(q)*b, then q rounds up.  Otherwise, we\n    // already have the correct result.  The exact halfway case cannot occur.\n    // We also take this time to right shift quotient if it falls in the [1,2)\n    // range and adjust the exponent accordingly.\n    rep_t residual;\n    if (quotient < (implicitBit << 1)) {\n        residual = (aSignificand << 53) - quotient * bSignificand;\n        quotientExponent--;\n    } else {\n        quotient >>= 1;\n        residual = (aSignificand << 52) - quotient * bSignificand;\n    }\n\n    const int writtenExponent = quotientExponent + exponentBias;\n\n    if (writtenExponent >= maxExponent) {\n        // If we have overflowed the exponent, return infinity.\n        return fromRep(infRep | quotientSign);\n    }\n\n    else if (writtenExponent < 1) {\n        // Flush denormals to zero.  In the future, it would be nice to add\n        // code to round them correctly.\n        return fromRep(quotientSign);\n    }\n\n    else {\n        const bool round = (residual << 1) > bSignificand;\n        // Clear the implicit bit\n        rep_t absResult = quotient & significandMask;\n        // Insert the exponent\n        absResult |= (rep_t)writtenExponent << significandBits;\n        // Round\n        absResult += round;\n        // Insert the sign and return\n        const double result = fromRep(absResult | quotientSign);\n        return result;\n    }\n}\n\n#if defined(__ARM_EABI__)\n#if defined(COMPILER_RT_ARMHF_TARGET)\nAEABI_RTABI fp_t __aeabi_ddiv(fp_t a, fp_t b) {\n  return __divdf3(a, b);\n}\n#else\nAEABI_RTABI fp_t __aeabi_ddiv(fp_t a, fp_t b) COMPILER_RT_ALIAS(__divdf3);\n#endif\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/divsf3.c",
    "content": "//===-- lib/divsf3.c - Single-precision division ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements single-precision soft-float division\n// with the IEEE-754 default rounding (to nearest, ties to even).\n//\n// For simplicity, this implementation currently flushes denormals to zero.\n// It should be a fairly straightforward exercise to implement gradual\n// underflow with correct rounding.\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__divsf3(fp_t a, fp_t b) {\n\n    const unsigned int aExponent = toRep(a) >> significandBits & maxExponent;\n    const unsigned int bExponent = toRep(b) >> significandBits & maxExponent;\n    const rep_t quotientSign = (toRep(a) ^ toRep(b)) & signBit;\n\n    rep_t aSignificand = toRep(a) & significandMask;\n    rep_t bSignificand = toRep(b) & significandMask;\n    int scale = 0;\n\n    // Detect if a or b is zero, denormal, infinity, or NaN.\n    if (aExponent-1U >= maxExponent-1U || bExponent-1U >= maxExponent-1U) {\n\n        const rep_t aAbs = toRep(a) & absMask;\n        const rep_t bAbs = toRep(b) & absMask;\n\n        // NaN / anything = qNaN\n        if (aAbs > infRep) return fromRep(toRep(a) | quietBit);\n        // anything / NaN = qNaN\n        if (bAbs > infRep) return fromRep(toRep(b) | quietBit);\n\n        if (aAbs == infRep) {\n            // infinity / infinity = NaN\n            if (bAbs == infRep) return fromRep(qnanRep);\n            // infinity / anything else = +/- infinity\n            else return fromRep(aAbs | quotientSign);\n        }\n\n        // anything else / infinity = +/- 0\n        if (bAbs == infRep) return fromRep(quotientSign);\n\n        if (!aAbs) {\n            // zero / zero = NaN\n            if (!bAbs) return fromRep(qnanRep);\n            // zero / anything else = +/- zero\n            else return fromRep(quotientSign);\n        }\n        // anything else / zero = +/- infinity\n        if (!bAbs) return fromRep(infRep | quotientSign);\n\n        // one or both of a or b is denormal, the other (if applicable) is a\n        // normal number.  Renormalize one or both of a and b, and set scale to\n        // include the necessary exponent adjustment.\n        if (aAbs < implicitBit) scale += normalize(&aSignificand);\n        if (bAbs < implicitBit) scale -= normalize(&bSignificand);\n    }\n\n    // Or in the implicit significand bit.  (If we fell through from the\n    // denormal path it was already set by normalize( ), but setting it twice\n    // won't hurt anything.)\n    aSignificand |= implicitBit;\n    bSignificand |= implicitBit;\n    int quotientExponent = aExponent - bExponent + scale;\n\n    // Align the significand of b as a Q31 fixed-point number in the range\n    // [1, 2.0) and get a Q32 approximate reciprocal using a small minimax\n    // polynomial approximation: reciprocal = 3/4 + 1/sqrt(2) - b/2.  This\n    // is accurate to about 3.5 binary digits.\n    uint32_t q31b = bSignificand << 8;\n    uint32_t reciprocal = UINT32_C(0x7504f333) - q31b;\n\n    // Now refine the reciprocal estimate using a Newton-Raphson iteration:\n    //\n    //     x1 = x0 * (2 - x0 * b)\n    //\n    // This doubles the number of correct binary digits in the approximation\n    // with each iteration, so after three iterations, we have about 28 binary\n    // digits of accuracy.\n    uint32_t correction;\n    correction = -((uint64_t)reciprocal * q31b >> 32);\n    reciprocal = (uint64_t)reciprocal * correction >> 31;\n    correction = -((uint64_t)reciprocal * q31b >> 32);\n    reciprocal = (uint64_t)reciprocal * correction >> 31;\n    correction = -((uint64_t)reciprocal * q31b >> 32);\n    reciprocal = (uint64_t)reciprocal * correction >> 31;\n\n    // Exhaustive testing shows that the error in reciprocal after three steps\n    // is in the interval [-0x1.f58108p-31, 0x1.d0e48cp-29], in line with our\n    // expectations.  We bump the reciprocal by a tiny value to force the error\n    // to be strictly positive (in the range [0x1.4fdfp-37,0x1.287246p-29], to\n    // be specific).  This also causes 1/1 to give a sensible approximation\n    // instead of zero (due to overflow).\n    reciprocal -= 2;\n\n    // The numerical reciprocal is accurate to within 2^-28, lies in the\n    // interval [0x1.000000eep-1, 0x1.fffffffcp-1], and is strictly smaller\n    // than the true reciprocal of b.  Multiplying a by this reciprocal thus\n    // gives a numerical q = a/b in Q24 with the following properties:\n    //\n    //    1. q < a/b\n    //    2. q is in the interval [0x1.000000eep-1, 0x1.fffffffcp0)\n    //    3. the error in q is at most 2^-24 + 2^-27 -- the 2^24 term comes\n    //       from the fact that we truncate the product, and the 2^27 term\n    //       is the error in the reciprocal of b scaled by the maximum\n    //       possible value of a.  As a consequence of this error bound,\n    //       either q or nextafter(q) is the correctly rounded\n    rep_t quotient = (uint64_t)reciprocal*(aSignificand << 1) >> 32;\n\n    // Two cases: quotient is in [0.5, 1.0) or quotient is in [1.0, 2.0).\n    // In either case, we are going to compute a residual of the form\n    //\n    //     r = a - q*b\n    //\n    // We know from the construction of q that r satisfies:\n    //\n    //     0 <= r < ulp(q)*b\n    //\n    // if r is greater than 1/2 ulp(q)*b, then q rounds up.  Otherwise, we\n    // already have the correct result.  The exact halfway case cannot occur.\n    // We also take this time to right shift quotient if it falls in the [1,2)\n    // range and adjust the exponent accordingly.\n    rep_t residual;\n    if (quotient < (implicitBit << 1)) {\n        residual = (aSignificand << 24) - quotient * bSignificand;\n        quotientExponent--;\n    } else {\n        quotient >>= 1;\n        residual = (aSignificand << 23) - quotient * bSignificand;\n    }\n\n    const int writtenExponent = quotientExponent + exponentBias;\n\n    if (writtenExponent >= maxExponent) {\n        // If we have overflowed the exponent, return infinity.\n        return fromRep(infRep | quotientSign);\n    }\n\n    else if (writtenExponent < 1) {\n        // Flush denormals to zero.  In the future, it would be nice to add\n        // code to round them correctly.\n        return fromRep(quotientSign);\n    }\n\n    else {\n        const bool round = (residual << 1) > bSignificand;\n        // Clear the implicit bit\n        rep_t absResult = quotient & significandMask;\n        // Insert the exponent\n        absResult |= (rep_t)writtenExponent << significandBits;\n        // Round\n        absResult += round;\n        // Insert the sign and return\n        return fromRep(absResult | quotientSign);\n    }\n}\n\n#if defined(__ARM_EABI__)\n#if defined(COMPILER_RT_ARMHF_TARGET)\nAEABI_RTABI fp_t __aeabi_fdiv(fp_t a, fp_t b) {\n  return __divsf3(a, b);\n}\n#else\nAEABI_RTABI fp_t __aeabi_fdiv(fp_t a, fp_t b) COMPILER_RT_ALIAS(__divsf3);\n#endif\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/fixdfsi.c",
    "content": "/* ===-- fixdfsi.c - Implement __fixdfsi -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\ntypedef si_int fixint_t;\ntypedef su_int fixuint_t;\n#include \"fp_fixint_impl.inc\"\n\nCOMPILER_RT_ABI si_int\n__fixdfsi(fp_t a) {\n    return __fixint(a);\n}\n\n#if defined(__ARM_EABI__)\n#if defined(COMPILER_RT_ARMHF_TARGET)\nAEABI_RTABI si_int __aeabi_d2iz(fp_t a) {\n  return __fixdfsi(a);\n}\n#else\nAEABI_RTABI si_int __aeabi_d2iz(fp_t a) COMPILER_RT_ALIAS(__fixdfsi);\n#endif\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/fixsfsi.c",
    "content": "/* ===-- fixsfsi.c - Implement __fixsfsi -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\ntypedef si_int fixint_t;\ntypedef su_int fixuint_t;\n#include \"fp_fixint_impl.inc\"\n\nCOMPILER_RT_ABI si_int\n__fixsfsi(fp_t a) {\n    return __fixint(a);\n}\n\n#if defined(__ARM_EABI__)\n#if defined(COMPILER_RT_ARMHF_TARGET)\nAEABI_RTABI si_int __aeabi_f2iz(fp_t a) {\n  return __fixsfsi(a);\n}\n#else\nAEABI_RTABI si_int __aeabi_f2iz(fp_t a) COMPILER_RT_ALIAS(__fixsfsi);\n#endif\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/fixunsdfsi.c",
    "content": "/* ===-- fixunsdfsi.c - Implement __fixunsdfsi -----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\ntypedef su_int fixuint_t;\n#include \"fp_fixuint_impl.inc\"\n\nCOMPILER_RT_ABI su_int\n__fixunsdfsi(fp_t a) {\n    return __fixuint(a);\n}\n\n#if defined(__ARM_EABI__)\n#if defined(COMPILER_RT_ARMHF_TARGET)\nAEABI_RTABI su_int __aeabi_d2uiz(fp_t a) {\n  return __fixunsdfsi(a);\n}\n#else\nAEABI_RTABI su_int __aeabi_d2uiz(fp_t a) COMPILER_RT_ALIAS(__fixunsdfsi);\n#endif\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/fixunssfsi.c",
    "content": "/* ===-- fixunssfsi.c - Implement __fixunssfsi -----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __fixunssfsi for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\ntypedef su_int fixuint_t;\n#include \"fp_fixuint_impl.inc\"\n\nCOMPILER_RT_ABI su_int\n__fixunssfsi(fp_t a) {\n    return __fixuint(a);\n}\n\n#if defined(__ARM_EABI__)\n#if defined(COMPILER_RT_ARMHF_TARGET)\nAEABI_RTABI su_int __aeabi_f2uiz(fp_t a) {\n  return __fixunssfsi(a);\n}\n#else\nAEABI_RTABI su_int __aeabi_f2uiz(fp_t a) COMPILER_RT_ALIAS(__fixunssfsi);\n#endif\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/floatsidf.c",
    "content": "//===-- lib/floatsidf.c - integer -> double-precision conversion --*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements integer to double-precision conversion for the\n// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even\n// mode.\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__floatsidf(int a) {\n\n    const int aWidth = sizeof a * CHAR_BIT;\n\n    // Handle zero as a special case to protect clz\n    if (a == 0)\n        return fromRep(0);\n\n    // All other cases begin by extracting the sign and absolute value of a\n    rep_t sign = 0;\n    if (a < 0) {\n        sign = signBit;\n        a = -a;\n    }\n\n    // Exponent of (fp_t)a is the width of abs(a).\n    const int exponent = (aWidth - 1) - __builtin_clz(a);\n    rep_t result;\n\n    // Shift a into the significand field and clear the implicit bit.  Extra\n    // cast to unsigned int is necessary to get the correct behavior for\n    // the input INT_MIN.\n    const int shift = significandBits - exponent;\n    result = (rep_t)(unsigned int)a << shift ^ implicitBit;\n\n    // Insert the exponent\n    result += (rep_t)(exponent + exponentBias) << significandBits;\n    // Insert the sign bit and return\n    return fromRep(result | sign);\n}\n\n#if defined(__ARM_EABI__)\n#if defined(COMPILER_RT_ARMHF_TARGET)\nAEABI_RTABI fp_t __aeabi_i2d(int a) {\n  return __floatsidf(a);\n}\n#else\nAEABI_RTABI fp_t __aeabi_i2d(int a) COMPILER_RT_ALIAS(__floatsidf);\n#endif\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/floatsisf.c",
    "content": "//===-- lib/floatsisf.c - integer -> single-precision conversion --*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements integer to single-precision conversion for the\n// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even\n// mode.\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__floatsisf(int a) {\n\n    const int aWidth = sizeof a * CHAR_BIT;\n\n    // Handle zero as a special case to protect clz\n    if (a == 0)\n        return fromRep(0);\n\n    // All other cases begin by extracting the sign and absolute value of a\n    rep_t sign = 0;\n    if (a < 0) {\n        sign = signBit;\n        a = -a;\n    }\n\n    // Exponent of (fp_t)a is the width of abs(a).\n    const int exponent = (aWidth - 1) - __builtin_clz(a);\n    rep_t result;\n\n    // Shift a into the significand field, rounding if it is a right-shift\n    if (exponent <= significandBits) {\n        const int shift = significandBits - exponent;\n        result = (rep_t)a << shift ^ implicitBit;\n    } else {\n        const int shift = exponent - significandBits;\n        result = (rep_t)a >> shift ^ implicitBit;\n        rep_t round = (rep_t)a << (typeWidth - shift);\n        if (round > signBit) result++;\n        if (round == signBit) result += result & 1;\n    }\n\n    // Insert the exponent\n    result += (rep_t)(exponent + exponentBias) << significandBits;\n    // Insert the sign bit and return\n    return fromRep(result | sign);\n}\n\n#if defined(__ARM_EABI__)\n#if defined(COMPILER_RT_ARMHF_TARGET)\nAEABI_RTABI fp_t __aeabi_i2f(int a) {\n  return __floatsisf(a);\n}\n#else\nAEABI_RTABI fp_t __aeabi_i2f(int a) COMPILER_RT_ALIAS(__floatsisf);\n#endif\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/floatunsidf.c",
    "content": "//===-- lib/floatunsidf.c - uint -> double-precision conversion ---*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements unsigned integer to double-precision conversion for the\n// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even\n// mode.\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__floatunsidf(unsigned int a) {\n\n    const int aWidth = sizeof a * CHAR_BIT;\n\n    // Handle zero as a special case to protect clz\n    if (a == 0) return fromRep(0);\n\n    // Exponent of (fp_t)a is the width of abs(a).\n    const int exponent = (aWidth - 1) - __builtin_clz(a);\n    rep_t result;\n\n    // Shift a into the significand field and clear the implicit bit.\n    const int shift = significandBits - exponent;\n    result = (rep_t)a << shift ^ implicitBit;\n\n    // Insert the exponent\n    result += (rep_t)(exponent + exponentBias) << significandBits;\n    return fromRep(result);\n}\n\n#if defined(__ARM_EABI__)\n#if defined(COMPILER_RT_ARMHF_TARGET)\nAEABI_RTABI fp_t __aeabi_ui2d(unsigned int a) {\n  return __floatunsidf(a);\n}\n#else\nAEABI_RTABI fp_t __aeabi_ui2d(unsigned int a) COMPILER_RT_ALIAS(__floatunsidf);\n#endif\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/floatunsisf.c",
    "content": "//===-- lib/floatunsisf.c - uint -> single-precision conversion ---*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements unsigned integer to single-precision conversion for the\n// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even\n// mode.\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\n#include \"int_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__floatunsisf(unsigned int a) {\n\n    const int aWidth = sizeof a * CHAR_BIT;\n\n    // Handle zero as a special case to protect clz\n    if (a == 0) return fromRep(0);\n\n    // Exponent of (fp_t)a is the width of abs(a).\n    const int exponent = (aWidth - 1) - __builtin_clz(a);\n    rep_t result;\n\n    // Shift a into the significand field, rounding if it is a right-shift\n    if (exponent <= significandBits) {\n        const int shift = significandBits - exponent;\n        result = (rep_t)a << shift ^ implicitBit;\n    } else {\n        const int shift = exponent - significandBits;\n        result = (rep_t)a >> shift ^ implicitBit;\n        rep_t round = (rep_t)a << (typeWidth - shift);\n        if (round > signBit) result++;\n        if (round == signBit) result += result & 1;\n    }\n\n    // Insert the exponent\n    result += (rep_t)(exponent + exponentBias) << significandBits;\n    return fromRep(result);\n}\n\n#if defined(__ARM_EABI__)\n#if defined(COMPILER_RT_ARMHF_TARGET)\nAEABI_RTABI fp_t __aeabi_ui2f(unsigned int a) {\n  return __floatunsisf(a);\n}\n#else\nAEABI_RTABI fp_t __aeabi_ui2f(unsigned int a) COMPILER_RT_ALIAS(__floatunsisf);\n#endif\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/fp_add_impl.inc",
    "content": "//===----- lib/fp_add_impl.inc - floating point addition ----------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements soft-float addition with the IEEE-754 default rounding\n// (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_lib.h\"\n\nstatic __inline fp_t __addXf3__(fp_t a, fp_t b) {\n    rep_t aRep = toRep(a);\n    rep_t bRep = toRep(b);\n    const rep_t aAbs = aRep & absMask;\n    const rep_t bAbs = bRep & absMask;\n\n    // Detect if a or b is zero, infinity, or NaN.\n    if (aAbs - REP_C(1) >= infRep - REP_C(1) ||\n        bAbs - REP_C(1) >= infRep - REP_C(1)) {\n        // NaN + anything = qNaN\n        if (aAbs > infRep) return fromRep(toRep(a) | quietBit);\n        // anything + NaN = qNaN\n        if (bAbs > infRep) return fromRep(toRep(b) | quietBit);\n\n        if (aAbs == infRep) {\n            // +/-infinity + -/+infinity = qNaN\n            if ((toRep(a) ^ toRep(b)) == signBit) return fromRep(qnanRep);\n            // +/-infinity + anything remaining = +/- infinity\n            else return a;\n        }\n\n        // anything remaining + +/-infinity = +/-infinity\n        if (bAbs == infRep) return b;\n\n        // zero + anything = anything\n        if (!aAbs) {\n            // but we need to get the sign right for zero + zero\n            if (!bAbs) return fromRep(toRep(a) & toRep(b));\n            else return b;\n        }\n\n        // anything + zero = anything\n        if (!bAbs) return a;\n    }\n\n    // Swap a and b if necessary so that a has the larger absolute value.\n    if (bAbs > aAbs) {\n        const rep_t temp = aRep;\n        aRep = bRep;\n        bRep = temp;\n    }\n\n    // Extract the exponent and significand from the (possibly swapped) a and b.\n    int aExponent = aRep >> significandBits & maxExponent;\n    int bExponent = bRep >> significandBits & maxExponent;\n    rep_t aSignificand = aRep & significandMask;\n    rep_t bSignificand = bRep & significandMask;\n\n    // Normalize any denormals, and adjust the exponent accordingly.\n    if (aExponent == 0) aExponent = normalize(&aSignificand);\n    if (bExponent == 0) bExponent = normalize(&bSignificand);\n\n    // The sign of the result is the sign of the larger operand, a.  If they\n    // have opposite signs, we are performing a subtraction; otherwise addition.\n    const rep_t resultSign = aRep & signBit;\n    const bool subtraction = (aRep ^ bRep) & signBit;\n\n    // Shift the significands to give us round, guard and sticky, and or in the\n    // implicit significand bit.  (If we fell through from the denormal path it\n    // was already set by normalize( ), but setting it twice won't hurt\n    // anything.)\n    aSignificand = (aSignificand | implicitBit) << 3;\n    bSignificand = (bSignificand | implicitBit) << 3;\n\n    // Shift the significand of b by the difference in exponents, with a sticky\n    // bottom bit to get rounding correct.\n    const unsigned int align = aExponent - bExponent;\n    if (align) {\n        if (align < typeWidth) {\n            const bool sticky = bSignificand << (typeWidth - align);\n            bSignificand = bSignificand >> align | sticky;\n        } else {\n            bSignificand = 1; // sticky; b is known to be non-zero.\n        }\n    }\n    if (subtraction) {\n        aSignificand -= bSignificand;\n        // If a == -b, return +zero.\n        if (aSignificand == 0) return fromRep(0);\n\n        // If partial cancellation occurred, we need to left-shift the result\n        // and adjust the exponent:\n        if (aSignificand < implicitBit << 3) {\n            const int shift = rep_clz(aSignificand) - rep_clz(implicitBit << 3);\n            aSignificand <<= shift;\n            aExponent -= shift;\n        }\n    }\n    else /* addition */ {\n        aSignificand += bSignificand;\n\n        // If the addition carried up, we need to right-shift the result and\n        // adjust the exponent:\n        if (aSignificand & implicitBit << 4) {\n            const bool sticky = aSignificand & 1;\n            aSignificand = aSignificand >> 1 | sticky;\n            aExponent += 1;\n        }\n    }\n\n    // If we have overflowed the type, return +/- infinity:\n    if (aExponent >= maxExponent) return fromRep(infRep | resultSign);\n\n    if (aExponent <= 0) {\n        // Result is denormal before rounding; the exponent is zero and we\n        // need to shift the significand.\n        const int shift = 1 - aExponent;\n        const bool sticky = aSignificand << (typeWidth - shift);\n        aSignificand = aSignificand >> shift | sticky;\n        aExponent = 0;\n    }\n\n    // Low three bits are round, guard, and sticky.\n    const int roundGuardSticky = aSignificand & 0x7;\n\n    // Shift the significand into place, and mask off the implicit bit.\n    rep_t result = aSignificand >> 3 & significandMask;\n\n    // Insert the exponent and sign.\n    result |= (rep_t)aExponent << significandBits;\n    result |= resultSign;\n\n    // Final rounding.  The result may overflow to infinity, but that is the\n    // correct result in that case.\n    if (roundGuardSticky > 0x4) result++;\n    if (roundGuardSticky == 0x4) result += result & 1;\n    return fromRep(result);\n}\n"
  },
  {
    "path": "lib/libc/runtime/fp_fixint_impl.inc",
    "content": "//===-- lib/fixdfsi.c - Double-precision -> integer conversion ----*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements float to integer conversion for the\n// compiler-rt library.\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_lib.h\"\n\nstatic __inline fixint_t __fixint(fp_t a) {\n    const fixint_t fixint_max = (fixint_t)((~(fixuint_t)0) / 2);\n    const fixint_t fixint_min = -fixint_max - 1;\n    // Break a into sign, exponent, significand\n    const rep_t aRep = toRep(a);\n    const rep_t aAbs = aRep & absMask;\n    const fixint_t sign = aRep & signBit ? -1 : 1;\n    const int exponent = (aAbs >> significandBits) - exponentBias;\n    const rep_t significand = (aAbs & significandMask) | implicitBit;\n\n    // If exponent is negative, the result is zero.\n    if (exponent < 0)\n        return 0;\n\n    // If the value is too large for the integer type, saturate.\n    if ((unsigned)exponent >= sizeof(fixint_t) * CHAR_BIT)\n        return sign == 1 ? fixint_max : fixint_min;\n\n    // If 0 <= exponent < significandBits, right shift to get the result.\n    // Otherwise, shift left.\n    if (exponent < significandBits)\n        return sign * (significand >> (significandBits - exponent));\n    else\n        return sign * ((fixint_t)significand << (exponent - significandBits));\n}\n"
  },
  {
    "path": "lib/libc/runtime/fp_fixuint_impl.inc",
    "content": "//===-- lib/fixdfsi.c - Double-precision -> integer conversion ----*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements float to unsigned integer conversion for the\n// compiler-rt library.\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_lib.h\"\n\nstatic __inline fixuint_t __fixuint(fp_t a) {\n    // Break a into sign, exponent, significand\n    const rep_t aRep = toRep(a);\n    const rep_t aAbs = aRep & absMask;\n    const int sign = aRep & signBit ? -1 : 1;\n    const int exponent = (aAbs >> significandBits) - exponentBias;\n    const rep_t significand = (aAbs & significandMask) | implicitBit;\n\n    // If either the value or the exponent is negative, the result is zero.\n    if (sign == -1 || exponent < 0)\n        return 0;\n\n    // If the value is too large for the integer type, saturate.\n    if ((unsigned)exponent >= sizeof(fixuint_t) * CHAR_BIT)\n        return ~(fixuint_t)0;\n\n    // If 0 <= exponent < significandBits, right shift to get the result.\n    // Otherwise, shift left.\n    if (exponent < significandBits)\n        return significand >> (significandBits - exponent);\n    else\n        return (fixuint_t)significand << (exponent - significandBits);\n}\n"
  },
  {
    "path": "lib/libc/runtime/fp_lib.h",
    "content": "//===-- lib/fp_lib.h - Floating-point utilities -------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file is a configuration header for soft-float routines in compiler-rt.\n// This file does not provide any part of the compiler-rt interface, but defines\n// many useful constants and utility routines that are used in the\n// implementation of the soft-float routines in compiler-rt.\n//\n// Assumes that float, double and long double correspond to the IEEE-754\n// binary32, binary64 and binary128 types, respectively, and that integer\n// endianness matches floating point endianness on the target platform.\n//\n//===----------------------------------------------------------------------===//\n\n#ifndef FP_LIB_HEADER\n#define FP_LIB_HEADER\n\n#include <stdint.h>\n#include <stdbool.h>\n#include <limits.h>\n#include \"int_lib.h\"\n\n// x86_64 FreeBSD prior v9.3 define fixed-width types incorrectly in\n// 32-bit mode.\n#if defined(__FreeBSD__) && defined(__i386__)\n# include <sys/param.h>\n# if __FreeBSD_version < 903000  // v9.3\n#  define uint64_t unsigned long long\n#  define int64_t long long\n#  undef UINT64_C\n#  define UINT64_C(c) (c ## ULL)\n# endif\n#endif\n\n#if defined SINGLE_PRECISION\n\ntypedef uint32_t rep_t;\ntypedef int32_t srep_t;\ntypedef float fp_t;\n#define REP_C UINT32_C\n#define significandBits 23\n\nstatic __inline int rep_clz(rep_t a) {\n    return __builtin_clz(a);\n}\n\n// 32x32 --> 64 bit multiply\nstatic __inline void wideMultiply(rep_t a, rep_t b, rep_t *hi, rep_t *lo) {\n    const uint64_t product = (uint64_t)a*b;\n    *hi = product >> 32;\n    *lo = product;\n}\nCOMPILER_RT_ABI fp_t __addsf3(fp_t a, fp_t b);\n\n#elif defined DOUBLE_PRECISION\n\ntypedef uint64_t rep_t;\ntypedef int64_t srep_t;\ntypedef double fp_t;\n#define REP_C UINT64_C\n#define significandBits 52\n\nstatic __inline int rep_clz(rep_t a) {\n#if defined __LP64__\n    return __builtin_clzl(a);\n#else\n    if (a & REP_C(0xffffffff00000000))\n        return __builtin_clz(a >> 32);\n    else\n        return 32 + __builtin_clz(a & REP_C(0xffffffff));\n#endif\n}\n\n#define loWord(a) (a & 0xffffffffU)\n#define hiWord(a) (a >> 32)\n\n// 64x64 -> 128 wide multiply for platforms that don't have such an operation;\n// many 64-bit platforms have this operation, but they tend to have hardware\n// floating-point, so we don't bother with a special case for them here.\nstatic __inline void wideMultiply(rep_t a, rep_t b, rep_t *hi, rep_t *lo) {\n    // Each of the component 32x32 -> 64 products\n    const uint64_t plolo = loWord(a) * loWord(b);\n    const uint64_t plohi = loWord(a) * hiWord(b);\n    const uint64_t philo = hiWord(a) * loWord(b);\n    const uint64_t phihi = hiWord(a) * hiWord(b);\n    // Sum terms that contribute to lo in a way that allows us to get the carry\n    const uint64_t r0 = loWord(plolo);\n    const uint64_t r1 = hiWord(plolo) + loWord(plohi) + loWord(philo);\n    *lo = r0 + (r1 << 32);\n    // Sum terms contributing to hi with the carry from lo\n    *hi = hiWord(plohi) + hiWord(philo) + hiWord(r1) + phihi;\n}\n#undef loWord\n#undef hiWord\n\nCOMPILER_RT_ABI fp_t __adddf3(fp_t a, fp_t b);\n\n#elif defined QUAD_PRECISION\n#if __LDBL_MANT_DIG__ == 113\n#define CRT_LDBL_128BIT\ntypedef __uint128_t rep_t;\ntypedef __int128_t srep_t;\ntypedef long double fp_t;\n#define REP_C (__uint128_t)\n// Note: Since there is no explicit way to tell compiler the constant is a\n// 128-bit integer, we let the constant be casted to 128-bit integer\n#define significandBits 112\n\nstatic __inline int rep_clz(rep_t a) {\n    const union\n        {\n             __uint128_t ll;\n#if _YUGA_BIG_ENDIAN\n             struct { uint64_t high, low; } s;\n#else\n             struct { uint64_t low, high; } s;\n#endif\n        } uu = { .ll = a };\n\n    uint64_t word;\n    uint64_t add;\n\n    if (uu.s.high){\n        word = uu.s.high;\n        add = 0;\n    }\n    else{\n        word = uu.s.low;\n        add = 64;\n    }\n    return __builtin_clzll(word) + add;\n}\n\n#define Word_LoMask   UINT64_C(0x00000000ffffffff)\n#define Word_HiMask   UINT64_C(0xffffffff00000000)\n#define Word_FullMask UINT64_C(0xffffffffffffffff)\n#define Word_1(a) (uint64_t)((a >> 96) & Word_LoMask)\n#define Word_2(a) (uint64_t)((a >> 64) & Word_LoMask)\n#define Word_3(a) (uint64_t)((a >> 32) & Word_LoMask)\n#define Word_4(a) (uint64_t)(a & Word_LoMask)\n\n// 128x128 -> 256 wide multiply for platforms that don't have such an operation;\n// many 64-bit platforms have this operation, but they tend to have hardware\n// floating-point, so we don't bother with a special case for them here.\nstatic __inline void wideMultiply(rep_t a, rep_t b, rep_t *hi, rep_t *lo) {\n\n    const uint64_t product11 = Word_1(a) * Word_1(b);\n    const uint64_t product12 = Word_1(a) * Word_2(b);\n    const uint64_t product13 = Word_1(a) * Word_3(b);\n    const uint64_t product14 = Word_1(a) * Word_4(b);\n    const uint64_t product21 = Word_2(a) * Word_1(b);\n    const uint64_t product22 = Word_2(a) * Word_2(b);\n    const uint64_t product23 = Word_2(a) * Word_3(b);\n    const uint64_t product24 = Word_2(a) * Word_4(b);\n    const uint64_t product31 = Word_3(a) * Word_1(b);\n    const uint64_t product32 = Word_3(a) * Word_2(b);\n    const uint64_t product33 = Word_3(a) * Word_3(b);\n    const uint64_t product34 = Word_3(a) * Word_4(b);\n    const uint64_t product41 = Word_4(a) * Word_1(b);\n    const uint64_t product42 = Word_4(a) * Word_2(b);\n    const uint64_t product43 = Word_4(a) * Word_3(b);\n    const uint64_t product44 = Word_4(a) * Word_4(b);\n\n    const __uint128_t sum0 = (__uint128_t)product44;\n    const __uint128_t sum1 = (__uint128_t)product34 +\n                             (__uint128_t)product43;\n    const __uint128_t sum2 = (__uint128_t)product24 +\n                             (__uint128_t)product33 +\n                             (__uint128_t)product42;\n    const __uint128_t sum3 = (__uint128_t)product14 +\n                             (__uint128_t)product23 +\n                             (__uint128_t)product32 +\n                             (__uint128_t)product41;\n    const __uint128_t sum4 = (__uint128_t)product13 +\n                             (__uint128_t)product22 +\n                             (__uint128_t)product31;\n    const __uint128_t sum5 = (__uint128_t)product12 +\n                             (__uint128_t)product21;\n    const __uint128_t sum6 = (__uint128_t)product11;\n\n    const __uint128_t r0 = (sum0 & Word_FullMask) +\n                           ((sum1 & Word_LoMask) << 32);\n    const __uint128_t r1 = (sum0 >> 64) +\n                           ((sum1 >> 32) & Word_FullMask) +\n                           (sum2 & Word_FullMask) +\n                           ((sum3 << 32) & Word_HiMask);\n\n    *lo = r0 + (r1 << 64);\n    *hi = (r1 >> 64) +\n          (sum1 >> 96) +\n          (sum2 >> 64) +\n          (sum3 >> 32) +\n          sum4 +\n          (sum5 << 32) +\n          (sum6 << 64);\n}\n#undef Word_1\n#undef Word_2\n#undef Word_3\n#undef Word_4\n#undef Word_HiMask\n#undef Word_LoMask\n#undef Word_FullMask\n#endif // __LDBL_MANT_DIG__ == 113\n#else\n#error SINGLE_PRECISION, DOUBLE_PRECISION or QUAD_PRECISION must be defined.\n#endif\n\n#if defined(SINGLE_PRECISION) || defined(DOUBLE_PRECISION) || defined(CRT_LDBL_128BIT)\n#define typeWidth       (sizeof(rep_t)*CHAR_BIT)\n#define exponentBits    (typeWidth - significandBits - 1)\n#define maxExponent     ((1 << exponentBits) - 1)\n#define exponentBias    (maxExponent >> 1)\n\n#define implicitBit     (REP_C(1) << significandBits)\n#define significandMask (implicitBit - 1U)\n#define signBit         (REP_C(1) << (significandBits + exponentBits))\n#define absMask         (signBit - 1U)\n#define exponentMask    (absMask ^ significandMask)\n#define oneRep          ((rep_t)exponentBias << significandBits)\n#define infRep          exponentMask\n#define quietBit        (implicitBit >> 1)\n#define qnanRep         (exponentMask | quietBit)\n\nstatic __inline rep_t toRep(fp_t x) {\n    const union { fp_t f; rep_t i; } rep = {.f = x};\n    return rep.i;\n}\n\nstatic __inline fp_t fromRep(rep_t x) {\n    const union { fp_t f; rep_t i; } rep = {.i = x};\n    return rep.f;\n}\n\nstatic __inline int normalize(rep_t *significand) {\n    const int shift = rep_clz(*significand) - rep_clz(implicitBit);\n    *significand <<= shift;\n    return 1 - shift;\n}\n\nstatic __inline void wideLeftShift(rep_t *hi, rep_t *lo, int count) {\n    *hi = *hi << count | *lo >> (typeWidth - count);\n    *lo = *lo << count;\n}\n\nstatic __inline void wideRightShiftWithSticky(rep_t *hi, rep_t *lo, unsigned int count) {\n    if (count < typeWidth) {\n        const bool sticky = *lo << (typeWidth - count);\n        *lo = *hi << (typeWidth - count) | *lo >> count | sticky;\n        *hi = *hi >> count;\n    }\n    else if (count < 2*typeWidth) {\n        const bool sticky = *hi << (2*typeWidth - count) | *lo;\n        *lo = *hi >> (count - typeWidth) | sticky;\n        *hi = 0;\n    } else {\n        const bool sticky = *hi | *lo;\n        *lo = sticky;\n        *hi = 0;\n    }\n}\n#endif\n\n#endif // FP_LIB_HEADER\n"
  },
  {
    "path": "lib/libc/runtime/fp_mul_impl.inc",
    "content": "//===---- lib/fp_mul_impl.inc - floating point multiplication -----*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements soft-float multiplication with the IEEE-754 default\n// rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#include \"fp_lib.h\"\n\nstatic __inline fp_t __mulXf3__(fp_t a, fp_t b) {\n    const unsigned int aExponent = toRep(a) >> significandBits & maxExponent;\n    const unsigned int bExponent = toRep(b) >> significandBits & maxExponent;\n    const rep_t productSign = (toRep(a) ^ toRep(b)) & signBit;\n\n    rep_t aSignificand = toRep(a) & significandMask;\n    rep_t bSignificand = toRep(b) & significandMask;\n    int scale = 0;\n\n    // Detect if a or b is zero, denormal, infinity, or NaN.\n    if (aExponent-1U >= maxExponent-1U || bExponent-1U >= maxExponent-1U) {\n\n        const rep_t aAbs = toRep(a) & absMask;\n        const rep_t bAbs = toRep(b) & absMask;\n\n        // NaN * anything = qNaN\n        if (aAbs > infRep) return fromRep(toRep(a) | quietBit);\n        // anything * NaN = qNaN\n        if (bAbs > infRep) return fromRep(toRep(b) | quietBit);\n\n        if (aAbs == infRep) {\n            // infinity * non-zero = +/- infinity\n            if (bAbs) return fromRep(aAbs | productSign);\n            // infinity * zero = NaN\n            else return fromRep(qnanRep);\n        }\n\n        if (bAbs == infRep) {\n            // non-zero * infinity = +/- infinity\n            if (aAbs) return fromRep(bAbs | productSign);\n            // zero * infinity = NaN\n            else return fromRep(qnanRep);\n        }\n\n        // zero * anything = +/- zero\n        if (!aAbs) return fromRep(productSign);\n        // anything * zero = +/- zero\n        if (!bAbs) return fromRep(productSign);\n\n        // one or both of a or b is denormal, the other (if applicable) is a\n        // normal number.  Renormalize one or both of a and b, and set scale to\n        // include the necessary exponent adjustment.\n        if (aAbs < implicitBit) scale += normalize(&aSignificand);\n        if (bAbs < implicitBit) scale += normalize(&bSignificand);\n    }\n\n    // Or in the implicit significand bit.  (If we fell through from the\n    // denormal path it was already set by normalize( ), but setting it twice\n    // won't hurt anything.)\n    aSignificand |= implicitBit;\n    bSignificand |= implicitBit;\n\n    // Get the significand of a*b.  Before multiplying the significands, shift\n    // one of them left to left-align it in the field.  Thus, the product will\n    // have (exponentBits + 2) integral digits, all but two of which must be\n    // zero.  Normalizing this result is just a conditional left-shift by one\n    // and bumping the exponent accordingly.\n    rep_t productHi, productLo;\n    wideMultiply(aSignificand, bSignificand << exponentBits,\n                 &productHi, &productLo);\n\n    int productExponent = aExponent + bExponent - exponentBias + scale;\n\n    // Normalize the significand, adjust exponent if needed.\n    if (productHi & implicitBit) productExponent++;\n    else wideLeftShift(&productHi, &productLo, 1);\n\n    // If we have overflowed the type, return +/- infinity.\n    if (productExponent >= maxExponent) return fromRep(infRep | productSign);\n\n    if (productExponent <= 0) {\n        // Result is denormal before rounding\n        //\n        // If the result is so small that it just underflows to zero, return\n        // a zero of the appropriate sign.  Mathematically there is no need to\n        // handle this case separately, but we make it a special case to\n        // simplify the shift logic.\n        const unsigned int shift = REP_C(1) - (unsigned int)productExponent;\n        if (shift >= typeWidth) return fromRep(productSign);\n\n        // Otherwise, shift the significand of the result so that the round\n        // bit is the high bit of productLo.\n        wideRightShiftWithSticky(&productHi, &productLo, shift);\n    }\n    else {\n        // Result is normal before rounding; insert the exponent.\n        productHi &= significandMask;\n        productHi |= (rep_t)productExponent << significandBits;\n    }\n\n    // Insert the sign of the result:\n    productHi |= productSign;\n\n    // Final rounding.  The final result may overflow to infinity, or underflow\n    // to zero, but those are the correct results in those cases.  We use the\n    // default IEEE-754 round-to-nearest, ties-to-even rounding mode.\n    if (productLo > signBit) productHi++;\n    if (productLo == signBit) productHi += productHi & 1;\n    return fromRep(productHi);\n}\n"
  },
  {
    "path": "lib/libc/runtime/int_endianness.h",
    "content": "/* ===-- int_endianness.h - configuration header for compiler-rt ------------===\n *\n *\t\t       The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file is a configuration header for compiler-rt.\n * This file is not part of the interface of this library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#ifndef INT_ENDIANNESS_H\n#define INT_ENDIANNESS_H\n\n#if defined(__BYTE_ORDER__) && defined(__ORDER_BIG_ENDIAN__) && \\\n    defined(__ORDER_LITTLE_ENDIAN__)\n\n/* Clang and GCC provide built-in endianness definitions. */\n#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__\n#define _YUGA_LITTLE_ENDIAN 0\n#define _YUGA_BIG_ENDIAN    1\n#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN    0\n#endif /* __BYTE_ORDER__ */\n\n#else /* Compilers other than Clang or GCC. */\n\n#if defined(__SVR4) && defined(__sun)\n#include <sys/byteorder.h>\n\n#if defined(_BIG_ENDIAN)\n#define _YUGA_LITTLE_ENDIAN 0\n#define _YUGA_BIG_ENDIAN    1\n#elif defined(_LITTLE_ENDIAN)\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN    0\n#else /* !_LITTLE_ENDIAN */\n#error \"unknown endianness\"\n#endif /* !_LITTLE_ENDIAN */\n\n#endif /* Solaris and AuroraUX. */\n\n/* .. */\n\n#if defined(__FreeBSD__) || defined(__NetBSD__) || defined(__DragonFly__) ||   \\\n    defined(__minix)\n#include <sys/endian.h>\n\n#if _BYTE_ORDER == _BIG_ENDIAN\n#define _YUGA_LITTLE_ENDIAN 0\n#define _YUGA_BIG_ENDIAN    1\n#elif _BYTE_ORDER == _LITTLE_ENDIAN\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN    0\n#endif /* _BYTE_ORDER */\n\n#endif /* *BSD */\n\n#if defined(__OpenBSD__)\n#include <machine/endian.h>\n\n#if _BYTE_ORDER == _BIG_ENDIAN\n#define _YUGA_LITTLE_ENDIAN 0\n#define _YUGA_BIG_ENDIAN    1\n#elif _BYTE_ORDER == _LITTLE_ENDIAN\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN    0\n#endif /* _BYTE_ORDER */\n\n#endif /* OpenBSD */\n\n/* .. */\n\n/* Mac OSX has __BIG_ENDIAN__ or __LITTLE_ENDIAN__ automatically set by the\n * compiler (at least with GCC) */\n#if defined(__APPLE__) || defined(__ellcc__ )\n\n#ifdef __BIG_ENDIAN__\n#if __BIG_ENDIAN__\n#define _YUGA_LITTLE_ENDIAN 0\n#define _YUGA_BIG_ENDIAN    1\n#endif\n#endif /* __BIG_ENDIAN__ */\n\n#ifdef __LITTLE_ENDIAN__\n#if __LITTLE_ENDIAN__\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN    0\n#endif\n#endif /* __LITTLE_ENDIAN__ */\n\n#endif /* Mac OSX */\n\n/* .. */\n\n#if defined(_WIN32)\n\n#define _YUGA_LITTLE_ENDIAN 1\n#define _YUGA_BIG_ENDIAN    0\n\n#endif /* Windows */\n\n#endif /* Clang or GCC. */\n\n/* . */\n\n#if !defined(_YUGA_LITTLE_ENDIAN) || !defined(_YUGA_BIG_ENDIAN)\n#error Unable to determine endian\n#endif /* Check we found an endianness correctly. */\n\n#endif /* INT_ENDIANNESS_H */\n"
  },
  {
    "path": "lib/libc/runtime/int_lib.h",
    "content": "/* ===-- int_lib.h - configuration header for compiler-rt  -----------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file is a configuration header for compiler-rt.\n * This file is not part of the interface of this library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#ifndef INT_LIB_H\n#define INT_LIB_H\n\n/* Assumption: Signed integral is 2's complement. */\n/* Assumption: Right shift of signed negative is arithmetic shift. */\n/* Assumption: Endianness is little or big (not mixed). */\n\n#if defined(__ELF__)\n#define FNALIAS(alias_name, original_name) \\\n  void alias_name() __attribute__((__alias__(#original_name)))\n#define COMPILER_RT_ALIAS(aliasee) __attribute__((__alias__(#aliasee)))\n#else\n#define FNALIAS(alias, name) _Pragma(\"GCC error(\\\"alias unsupported on this file format\\\")\")\n#define COMPILER_RT_ALIAS(aliasee) _Pragma(\"GCC error(\\\"alias unsupported on this file format\\\")\")\n#endif\n\n/* ABI macro definitions */\n\n#if __ARM_EABI__\n# ifdef COMPILER_RT_ARMHF_TARGET\n#   define COMPILER_RT_ABI\n# else\n#   define COMPILER_RT_ABI __attribute__((__pcs__(\"aapcs\")))\n# endif\n#else\n# define COMPILER_RT_ABI\n#endif\n\n#define AEABI_RTABI __attribute__((__pcs__(\"aapcs\")))\n\n#ifdef _MSC_VER\n#define ALWAYS_INLINE __forceinline\n#define NOINLINE __declspec(noinline)\n#define NORETURN __declspec(noreturn)\n#define UNUSED\n#else\n#define ALWAYS_INLINE __attribute__((always_inline))\n#define NOINLINE __attribute__((noinline))\n#define NORETURN __attribute__((noreturn))\n#define UNUSED __attribute__((unused))\n#endif\n\n#if defined(__NetBSD__) && (defined(_KERNEL) || defined(_STANDALONE))\n/*\n * Kernel and boot environment can't use normal headers,\n * so use the equivalent system headers.\n */\n#  include <machine/limits.h>\n#  include <sys/stdint.h>\n#  include <sys/types.h>\n#else\n/* Include the standard compiler builtin headers we use functionality from. */\n#  include <limits.h>\n#  include <stdint.h>\n#  include <stdbool.h>\n#  include <float.h>\n#endif\n\n/* Include the commonly used internal type definitions. */\n#include \"int_types.h\"\n\n/* Include internal utility function declarations. */\n#include \"int_util.h\"\n\nCOMPILER_RT_ABI si_int __paritysi2(si_int a);\nCOMPILER_RT_ABI si_int __paritydi2(di_int a);\n\nCOMPILER_RT_ABI di_int __divdi3(di_int a, di_int b);\nCOMPILER_RT_ABI si_int __divsi3(si_int a, si_int b);\nCOMPILER_RT_ABI su_int __udivsi3(su_int n, su_int d);\n\nCOMPILER_RT_ABI su_int __udivmodsi4(su_int a, su_int b, su_int* rem);\nCOMPILER_RT_ABI du_int __udivmoddi4(du_int a, du_int b, du_int* rem);\n#ifdef CRT_HAS_128BIT\nCOMPILER_RT_ABI si_int __clzti2(ti_int a);\nCOMPILER_RT_ABI tu_int __udivmodti4(tu_int a, tu_int b, tu_int* rem);\n#endif\n\n/* Definitions for builtins unavailable on MSVC */\n#if defined(_MSC_VER) && !defined(__clang__)\n#include <intrin.h>\n\nuint32_t __inline __builtin_ctz(uint32_t value) {\n  unsigned long trailing_zero = 0;\n  if (_BitScanForward(&trailing_zero, value))\n    return trailing_zero;\n  return 32;\n}\n\nuint32_t __inline __builtin_clz(uint32_t value) {\n  unsigned long leading_zero = 0;\n  if (_BitScanReverse(&leading_zero, value))\n    return 31 - leading_zero;\n  return 32;\n}\n\n#if defined(_M_ARM) || defined(_M_X64)\nuint32_t __inline __builtin_clzll(uint64_t value) {\n  unsigned long leading_zero = 0;\n  if (_BitScanReverse64(&leading_zero, value))\n    return 63 - leading_zero;\n  return 64;\n}\n#else\nuint32_t __inline __builtin_clzll(uint64_t value) {\n  if (value == 0)\n    return 64;\n  uint32_t msh = (uint32_t)(value >> 32);\n  uint32_t lsh = (uint32_t)(value & 0xFFFFFFFF);\n  if (msh != 0)\n    return __builtin_clz(msh);\n  return 32 + __builtin_clz(lsh);\n}\n#endif\n\n#define __builtin_clzl __builtin_clzll\n#endif /* defined(_MSC_VER) && !defined(__clang__) */\n\n#endif /* INT_LIB_H */\n"
  },
  {
    "path": "lib/libc/runtime/int_types.h",
    "content": "/* ===-- int_lib.h - configuration header for compiler-rt  -----------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file is not part of the interface of this library.\n *\n * This file defines various standard types, most importantly a number of unions\n * used to access parts of larger types.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#ifndef INT_TYPES_H\n#define INT_TYPES_H\n\n#include \"int_endianness.h\"\n\n/* si_int is defined in Linux sysroot's asm-generic/siginfo.h */\n#ifdef si_int\n#undef si_int\n#endif\ntypedef      int si_int;\ntypedef unsigned su_int;\n\ntypedef          long long di_int;\ntypedef unsigned long long du_int;\n\ntypedef union\n{\n    di_int all;\n    struct\n    {\n#if _YUGA_LITTLE_ENDIAN\n        su_int low;\n        si_int high;\n#else\n        si_int high;\n        su_int low;\n#endif /* _YUGA_LITTLE_ENDIAN */\n    }s;\n} dwords;\n\ntypedef union\n{\n    du_int all;\n    struct\n    {\n#if _YUGA_LITTLE_ENDIAN\n        su_int low;\n        su_int high;\n#else\n        su_int high;\n        su_int low;\n#endif /* _YUGA_LITTLE_ENDIAN */\n    }s;\n} udwords;\n\n#if (defined(__LP64__) || defined(__wasm__) || defined(__mips64)) || defined(__riscv)\n#define CRT_HAS_128BIT\n#endif\n\n#ifdef CRT_HAS_128BIT\ntypedef int      ti_int __attribute__ ((mode (TI)));\ntypedef unsigned tu_int __attribute__ ((mode (TI)));\n\ntypedef union\n{\n    ti_int all;\n    struct\n    {\n#if _YUGA_LITTLE_ENDIAN\n        du_int low;\n        di_int high;\n#else\n        di_int high;\n        du_int low;\n#endif /* _YUGA_LITTLE_ENDIAN */\n    }s;\n} twords;\n\ntypedef union\n{\n    tu_int all;\n    struct\n    {\n#if _YUGA_LITTLE_ENDIAN\n        du_int low;\n        du_int high;\n#else\n        du_int high;\n        du_int low;\n#endif /* _YUGA_LITTLE_ENDIAN */\n    }s;\n} utwords;\n\nstatic __inline ti_int make_ti(di_int h, di_int l) {\n    twords r;\n    r.s.high = h;\n    r.s.low = l;\n    return r.all;\n}\n\nstatic __inline tu_int make_tu(du_int h, du_int l) {\n    utwords r;\n    r.s.high = h;\n    r.s.low = l;\n    return r.all;\n}\n\n#endif /* CRT_HAS_128BIT */\n\ntypedef union\n{\n    su_int u;\n    float f;\n} float_bits;\n\ntypedef union\n{\n    udwords u;\n    double  f;\n} double_bits;\n\ntypedef struct\n{\n#if _YUGA_LITTLE_ENDIAN\n    udwords low;\n    udwords high;\n#else\n    udwords high;\n    udwords low;\n#endif /* _YUGA_LITTLE_ENDIAN */\n} uqwords;\n\ntypedef union\n{\n    uqwords     u;\n    long double f;\n} long_double_bits;\n\n#if __STDC_VERSION__ >= 199901L\ntypedef float _Complex Fcomplex;\ntypedef double _Complex Dcomplex;\ntypedef long double _Complex Lcomplex;\n\n#define COMPLEX_REAL(x) __real__(x)\n#define COMPLEX_IMAGINARY(x) __imag__(x)\n#else\ntypedef struct { float real, imaginary; } Fcomplex;\n\ntypedef struct { double real, imaginary; } Dcomplex;\n\ntypedef struct { long double real, imaginary; } Lcomplex;\n\n#define COMPLEX_REAL(x) (x).real\n#define COMPLEX_IMAGINARY(x) (x).imaginary\n#endif\n#endif /* INT_TYPES_H */\n\n"
  },
  {
    "path": "lib/libc/runtime/int_util.h",
    "content": "/* ===-- int_util.h - internal utility functions ----------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE.TXT for details.\n *\n * ===-----------------------------------------------------------------------===\n *\n * This file is not part of the interface of this library.\n *\n * This file defines non-inline utilities which are available for use in the\n * library. The function definitions themselves are all contained in int_util.c\n * which will always be compiled into any compiler-rt library.\n *\n * ===-----------------------------------------------------------------------===\n */\n\n#ifndef INT_UTIL_H\n#define INT_UTIL_H\n\n/** \\brief Trigger a program abort (or panic for kernel code). */\n#define compilerrt_abort() compilerrt_abort_impl(__FILE__, __LINE__, __func__)\n\nNORETURN void compilerrt_abort_impl(const char *file, int line,\n                                    const char *function);\n\n#define COMPILE_TIME_ASSERT(expr) COMPILE_TIME_ASSERT1(expr, __COUNTER__)\n#define COMPILE_TIME_ASSERT1(expr, cnt) COMPILE_TIME_ASSERT2(expr, cnt)\n#define COMPILE_TIME_ASSERT2(expr, cnt)                                        \\\n  typedef char ct_assert_##cnt[(expr) ? 1 : -1] UNUSED\n\n#endif /* INT_UTIL_H */\n"
  },
  {
    "path": "lib/libc/runtime/lshrdi3.c",
    "content": "/* ===-- lshrdi3.c - Implement __lshrdi3 -----------------------------------===\n *\n *                     The LLVM Compiler Infrastructure\n *\n * This file is dual licensed under the MIT and the University of Illinois Open\n * Source Licenses. See LICENSE.TXT for details.\n *\n * ===----------------------------------------------------------------------===\n *\n * This file implements __lshrdi3 for the compiler_rt library.\n *\n * ===----------------------------------------------------------------------===\n */\n\n#include \"int_lib.h\"\n\n/* Returns: logical a >> b */\n\n/* Precondition:  0 <= b < bits_in_dword */\n\nCOMPILER_RT_ABI di_int\n__lshrdi3(di_int a, si_int b)\n{\n    const int bits_in_word = (int)(sizeof(si_int) * CHAR_BIT);\n    udwords input;\n    udwords result;\n    input.all = a;\n    if (b & bits_in_word)  /* bits_in_word <= b < bits_in_dword */\n    {\n        result.s.high = 0;\n        result.s.low = input.s.high >> (b - bits_in_word);\n    }\n    else  /* 0 <= b < bits_in_word */\n    {\n        if (b == 0)\n            return a;\n        result.s.high  = input.s.high >> b;\n        result.s.low = (input.s.high << (bits_in_word - b)) | (input.s.low >> b);\n    }\n    return result.all;\n}\n\n#if defined(__ARM_EABI__)\nAEABI_RTABI di_int __aeabi_llsr(di_int a, si_int b) COMPILER_RT_ALIAS(__lshrdi3);\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/muldf3.c",
    "content": "//===-- lib/muldf3.c - Double-precision multiplication ------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements double-precision soft-float multiplication\n// with the IEEE-754 default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_mul_impl.inc\"\n\nCOMPILER_RT_ABI fp_t __muldf3(fp_t a, fp_t b) {\n    return __mulXf3__(a, b);\n}\n\n#if defined(__ARM_EABI__)\n#if defined(COMPILER_RT_ARMHF_TARGET)\nAEABI_RTABI fp_t __aeabi_dmul(fp_t a, fp_t b) {\n  return __muldf3(a, b);\n}\n#else\nAEABI_RTABI fp_t __aeabi_dmul(fp_t a, fp_t b) COMPILER_RT_ALIAS(__muldf3);\n#endif\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/mulsf3.c",
    "content": "//===-- lib/mulsf3.c - Single-precision multiplication ------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements single-precision soft-float multiplication\n// with the IEEE-754 default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_mul_impl.inc\"\n\nCOMPILER_RT_ABI fp_t __mulsf3(fp_t a, fp_t b) {\n    return __mulXf3__(a, b);\n}\n\n#if defined(__ARM_EABI__)\n#if defined(COMPILER_RT_ARMHF_TARGET)\nAEABI_RTABI fp_t __aeabi_fmul(fp_t a, fp_t b) {\n  return __mulsf3(a, b);\n}\n#else\nAEABI_RTABI fp_t __aeabi_fmul(fp_t a, fp_t b) COMPILER_RT_ALIAS(__mulsf3);\n#endif\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/negdf2.c",
    "content": "//===-- lib/negdf2.c - double-precision negation ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements double-precision soft-float negation.\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__negdf2(fp_t a) {\n    return fromRep(toRep(a) ^ signBit);\n}\n\n#if defined(__ARM_EABI__)\n#if defined(COMPILER_RT_ARMHF_TARGET)\nAEABI_RTABI fp_t __aeabi_dneg(fp_t a) {\n  return __negdf2(a);\n}\n#else\nAEABI_RTABI fp_t __aeabi_dneg(fp_t a) COMPILER_RT_ALIAS(__negdf2);\n#endif\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/negsf2.c",
    "content": "//===-- lib/negsf2.c - single-precision negation ------------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements single-precision soft-float negation.\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\nCOMPILER_RT_ABI fp_t\n__negsf2(fp_t a) {\n    return fromRep(toRep(a) ^ signBit);\n}\n\n#if defined(__ARM_EABI__)\n#if defined(COMPILER_RT_ARMHF_TARGET)\nAEABI_RTABI fp_t __aeabi_fneg(fp_t a) {\n  return __negsf2(a);\n}\n#else\nAEABI_RTABI fp_t __aeabi_fneg(fp_t a) COMPILER_RT_ALIAS(__negsf2);\n#endif\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/sc_case.S",
    "content": "#if __mips__ /* XXX */\n        .set reorder\n#endif /* __mips__ XXX */\n\t.text\n#\n# $v0 = value to switch on\n# 0($sp) = pointer to list of value,ptr cases\n#         ended where ptr=0, value is used as pointer to jump to in default case\n# looks like stack is popped as part of this\n# FIXME - The assembler/linker only stores the bottom 16 bits\n# of the labels in pair, so we construct the address by merging the 16 bits\n# in the cell with the upper 16 bits in the return address of the code that\n# called this. Is there a way to get the assembler linker to store the full\n# address? If so, that should be used instead.\n#\n        .globl  __sc_case\n__sc_case:\n#if __mips__ /* XXX */\n\tlw\t$t1, 16($sp)\t# t1=pointer to list of value/ptr pairs\n\taddiu\t$sp, $sp, 4\t# pop stack that held pointer\n1:\n        lw      $t2, 0($t1)     # get value from pair\n        lw      $t3, 4($t1)     # get ptr from pair\n        beq     $t3, $zero, 2f\n\n\tbeq     $t2, $v0, 3f\n\n        addiu   $t1, $t1, 8     # t1 += size of pair\n        j       1b\n\n2:\n        move\t$t3, $t2\n3:\n\tlui     $t2, 0xffff\n\tand\t$t2, $t2, $ra\n        or      $t3, $t3, $t2\n\tjr\t$t3\n#endif /* __mips__ XXX */\n"
  },
  {
    "path": "lib/libc/runtime/subdf3.c",
    "content": "//===-- lib/adddf3.c - Double-precision subtraction ---------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements double-precision soft-float subtraction with the\n// IEEE-754 default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define DOUBLE_PRECISION\n#include \"fp_lib.h\"\n\n// Subtraction; flip the sign bit of b and add.\nCOMPILER_RT_ABI fp_t\n__subdf3(fp_t a, fp_t b) {\n    return __adddf3(a, fromRep(toRep(b) ^ signBit));\n}\n\n#if defined(__ARM_EABI__)\n#if defined(COMPILER_RT_ARMHF_TARGET)\nAEABI_RTABI fp_t __aeabi_dsub(fp_t a, fp_t b) {\n  return __subdf3(a, b);\n}\n#else\nAEABI_RTABI fp_t __aeabi_dsub(fp_t a, fp_t b) COMPILER_RT_ALIAS(__subdf3);\n#endif\n#endif\n"
  },
  {
    "path": "lib/libc/runtime/subsf3.c",
    "content": "//===-- lib/subsf3.c - Single-precision subtraction ---------------*- C -*-===//\n//\n//                     The LLVM Compiler Infrastructure\n//\n// This file is dual licensed under the MIT and the University of Illinois Open\n// Source Licenses. See LICENSE.TXT for details.\n//\n//===----------------------------------------------------------------------===//\n//\n// This file implements single-precision soft-float subtraction with the\n// IEEE-754 default rounding (to nearest, ties to even).\n//\n//===----------------------------------------------------------------------===//\n\n#define SINGLE_PRECISION\n#include \"fp_lib.h\"\n\n// Subtraction; flip the sign bit of b and add.\nCOMPILER_RT_ABI fp_t\n__subsf3(fp_t a, fp_t b) {\n    return __addsf3(a, fromRep(toRep(b) ^ signBit));\n}\n\n#if defined(__ARM_EABI__)\n#if defined(COMPILER_RT_ARMHF_TARGET)\nAEABI_RTABI fp_t __aeabi_fsub(fp_t a, fp_t b) {\n  return __subsf3(a, b);\n}\n#else\nAEABI_RTABI fp_t __aeabi_fsub(fp_t a, fp_t b) COMPILER_RT_ALIAS(__subsf3);\n#endif\n#endif\n"
  },
  {
    "path": "lib/libc/stdio/Makefile",
    "content": "#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\nTOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS\t\t+= ${DEFS} -Os\n\nSRCS\t\t= ${STDSRC} fgetc.c fgets.c fputc.c fputs.c gets.c puts.c \\\n                  feof.c ferror.c fileno.c\nOBJS\t\t= ${STDOBJ} fgetc.o fgets.o fputc.o fputs.o gets.o puts.o \\\n                  feof.o ferror.o fileno.o\n\nSTDSRC\t\t= clrerr.c doscan.c exit.c clnup.c fdopen.c filbuf.c findiop.c \\\n\t\t  flsbuf.c fopen.c fprintf.c fread.c freopen.c fseek.c \\\n\t\t  ftell.c fwrite.c getchar.c getw.c printf.c putchar.c putw.c \\\n\t\t  rew.c scanf.c setbuf.c setbuffer.c setvbuf.c snprintf.c sprintf.c \\\n\t\t  strout.c ungetc.c vfprintf.c vprintf.c vsprintf.c doprnt.c \\\n\t\t  remove.c\nSTDOBJ\t\t= clrerr.o doscan.o exit.o fdopen.o filbuf.o findiop.o \\\n\t\t  flsbuf.o fopen.o fprintf.o fread.o freopen.o fseek.o \\\n\t\t  ftell.o fwrite.o getchar.o getw.o printf.o putchar.o putw.o \\\n\t\t  rew.o scanf.o setbuf.o setbuffer.o setvbuf.o snprintf.o sprintf.o \\\n\t\t  strout.o ungetc.o vfprintf.o vprintf.o vsprintf.o doprnt.o \\\n\t\t  remove.o\n\nTAGSFILE\t= tags\n\nstdio.a:\t${OBJS}\n\t\t@echo \"building stdio.a\"\n\t\t@${AR} cr stdio.a ${OBJS}\n\ntags:\n\t\tcwd=`pwd`; \\\n\t\tfor i in ${SRCS}; do \\\n\t\t\tctags -a -f ${TAGSFILE} $$cwd/$$i; \\\n\t\tdone\n\nclean:\n\t\trm -f stdio.a *.o *~ profiled/*.o tags Makefile.bak\n\ndepend:\n\t\tfor i in ${SRCS}; do \\\n\t\t    cc -M ${CFLAGS} $$i | awk ' { if ($$1 != prev) \\\n\t\t\t{ if (rec != \"\") print rec; rec = $$0; prev = $$1; } \\\n\t\t\telse { if (length(rec $$2) > 78) { print rec; rec = $$0; } \\\n\t\t\telse rec = rec \" \" $$2 } } \\\n\t\t\tEND { print rec } ' >> makedep; done\n\t\techo '/^# DO NOT DELETE THIS LINE/+2,$$d' >eddep\n\t\techo '$$r makedep' >>eddep\n\t\techo 'w' >>eddep\n\t\tcp Makefile Makefile.bak\n\t\ted - Makefile < eddep\n\t\trm eddep makedep\n\t\techo '# DEPENDENCIES MUST END AT END OF FILE' >> Makefile\n\t\techo '# IF YOU PUT STUFF HERE IT WILL GO AWAY' >> Makefile\n\t\techo '# see make depend above' >> Makefile\n\n# DO NOT DELETE THIS LINE -- make depend uses it\n"
  },
  {
    "path": "lib/libc/stdio/clnup.c",
    "content": "/*\n * This stub is linked in, when application uses no stdio calls.\n */\n__attribute__((weak))\nvoid _cleanup()\n{\n        /* Nothing to do. */\n}\n"
  },
  {
    "path": "lib/libc/stdio/clrerr.c",
    "content": "/*\t$OpenBSD: clrerr.c,v 1.6 2005/08/08 08:05:36 espie Exp $ */\n/*-\n * Copyright (c) 1990, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Chris Torek.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n#include <stdio.h>\n\n/*\n * A subroutine version of the macro clearerr.\n */\n#undef\tclearerr\n\nvoid\nclearerr(FILE *fp)\n{\n\t__sclearerr(fp);\n}\n"
  },
  {
    "path": "lib/libc/stdio/doprnt.c",
    "content": "/*\n * Scaled down version of printf(3).\n * Based on FreeBSD sources, heavily rewritten.\n *\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * Two additional formats:\n *\n * The format %b is supported to decode error registers.\n * Its usage is:\n *\n *\tprintf(\"reg=%b\\n\", regval, \"<base><arg>*\");\n *\n * where <base> is the output base expressed as a control character, e.g.\n * \\10 gives octal; \\20 gives hex.  Each arg is a sequence of characters,\n * the first of which gives the bit number to be inspected (origin 1), and\n * the next characters (up to a control character, i.e. a character <= 32),\n * give the name of the register.  Thus:\n *\n *\tkvprintf(\"reg=%b\\n\", 3, \"\\10\\2BITTWO\\1BITONE\\n\");\n *\n * would produce output:\n *\n *\treg=3<BITTWO,BITONE>\n *\n * The format %D -- Hexdump, takes a pointer. Sharp flag - use `:' as\n * a separator, instead of a space. For example:\n *\n *\t(\"%6D\", ptr)       -> XX XX XX XX XX XX\n *\t(\"%#*D\", len, ptr) -> XX:XX:XX:XX ...\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdarg.h>\n#include <unistd.h>\n#include <float.h>\n#include <math.h>\n\n/* Max number conversion buffer length. */\n#define MAXNBUF\t\\\n\t(1/*sign*/ + DBL_MAX_10_EXP+1/*max integral digits*/ + \\\n\t1/*.*/ + DBL_DIG+1/*max fractional digits*/ + 1/*NUL*/)\n\nstatic unsigned char *ksprintn (unsigned char *buf, unsigned long v, unsigned char base,\n\tint width, unsigned char *lp);\nstatic unsigned char mkhex (unsigned char ch);\n\nstatic int cvt (double number, int prec, int sharpflag, unsigned char *negp,\n\tunsigned char fmtch, unsigned char *startp, unsigned char *endp);\n\nint\n_doprnt (char const *fmt, va_list ap, FILE *stream)\n{\n#define PUTC(c) { putc (c, stream); ++retval; }\n\tunsigned char nbuf [MAXNBUF], padding, *q;\n\tconst unsigned char *s;\n\tunsigned char c, base, lflag, ladjust, sharpflag, neg, dot, size;\n\tint n, width, dwidth, retval, uppercase, extrazeros, sign;\n\tunsigned long ul;\n\n\tif (! stream)\n\t\treturn 0;\n\tif (! fmt)\n\t\tfmt = \"(null)\\n\";\n\n\tretval = 0;\n\tfor (;;) {\n\t\twhile ((c = *fmt++) != '%') {\n\t\t\tif (! c)\n\t\t\t\treturn retval;\n\t\t\tPUTC (c);\n\t\t}\n\t\tpadding = ' ';\n\t\twidth = 0; extrazeros = 0;\n\t\tlflag = 0; ladjust = 0; sharpflag = 0; neg = 0;\n\t\tsign = 0; dot = 0; uppercase = 0; dwidth = -1;\nreswitch:\tswitch (c = *fmt++) {\n\t\tcase '.':\n\t\t\tdot = 1;\n\t\t\tpadding = ' ';\n\t\t\tdwidth = 0;\n\t\t\tgoto reswitch;\n\n\t\tcase '#':\n\t\t\tsharpflag = 1;\n\t\t\tgoto reswitch;\n\n\t\tcase '+':\n\t\t\tsign = -1;\n\t\t\tgoto reswitch;\n\n\t\tcase '-':\n\t\t\tladjust = 1;\n\t\t\tgoto reswitch;\n\n\t\tcase '%':\n\t\t\tPUTC (c);\n\t\t\tbreak;\n\n\t\tcase '*':\n\t\t\tif (! dot) {\n\t\t\t\twidth = va_arg (ap, int);\n\t\t\t\tif (width < 0) {\n\t\t\t\t\tladjust = !ladjust;\n\t\t\t\t\twidth = -width;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tdwidth = va_arg (ap, int);\n\t\t\t}\n\t\t\tgoto reswitch;\n\n\t\tcase '0':\n\t\t\tif (! dot) {\n\t\t\t\tpadding = '0';\n\t\t\t\tgoto reswitch;\n\t\t\t}\n\t\tcase '1': case '2': case '3': case '4':\n\t\tcase '5': case '6': case '7': case '8': case '9':\n\t\t\tfor (n=0; ; ++fmt) {\n\t\t\t\tn = n * 10 + c - '0';\n\t\t\t\tc = *fmt;\n\t\t\t\tif (c < '0' || c > '9')\n\t\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (dot)\n\t\t\t\tdwidth = n;\n\t\t\telse\n\t\t\t\twidth = n;\n\t\t\tgoto reswitch;\n\n\t\tcase 'b':\n\t\t\tul = va_arg (ap, int);\n\t\t\ts = va_arg (ap, const unsigned char*);\n\t\t\tq = ksprintn (nbuf, ul, *s++, -1, 0);\n\t\t\twhile (*q)\n\t\t\t\tPUTC (*q--);\n\n\t\t\tif (! ul)\n\t\t\t\tbreak;\n\t\t\tsize = 0;\n\t\t\twhile (*s) {\n\t\t\t\tn = *s++;\n\t\t\t\tif ((char) (ul >> (n-1)) & 1) {\n\t\t\t\t\tPUTC (size ? ',' : '<');\n\t\t\t\t\tfor (; (n = *s) > ' '; ++s)\n\t\t\t\t\t\tPUTC (n);\n\t\t\t\t\tsize = 1;\n\t\t\t\t} else\n\t\t\t\t\twhile (*s > ' ')\n\t\t\t\t\t\t++s;\n\t\t\t}\n\t\t\tif (size)\n\t\t\t\tPUTC ('>');\n\t\t\tbreak;\n\n\t\tcase 'c':\n\t\t\tif (! ladjust && width > 0)\n\t\t\t\twhile (width--)\n\t\t\t\t\tPUTC (' ');\n\n\t\t\tPUTC (va_arg (ap, int));\n\n\t\t\tif (ladjust && width > 0)\n\t\t\t\twhile (width--)\n\t\t\t\t\tPUTC (' ');\n\t\t\tbreak;\n\n\t\tcase 'D':\n\t\t\tlflag=1;\n\t\t\t/* FALLTHROUGH */\n\n\t\tcase 'd':\n\t\tcase 'i':\n\t\t\tul = lflag ? va_arg (ap, long) : va_arg (ap, int);\n\t\t\tif (! sign) sign = 1;\n\t\t\tbase = 10;\n\t\t\tgoto number;\n\n\t\tcase 'l':\n\t\t\tlflag = 1;\n\t\t\tgoto reswitch;\n\n\t\tcase 'o':\n\t\t\tul = lflag ? va_arg (ap, unsigned long) :\n\t\t\t\tva_arg (ap, unsigned int);\n\t\t\tbase = 8;\n\t\t\tgoto nosign;\n\n\t\tcase 'p':\n\t\t\tul = (size_t) va_arg (ap, void*);\n\t\t\tif (! ul) {\n\t\t\t\ts = (const unsigned char*) \"(nil)\";\n\t\t\t\tgoto string;\n\t\t\t}\n\t\t\tbase = 16;\n\t\t\tsharpflag = (width == 0);\n\t\t\tgoto nosign;\n\n\t\tcase 'n': /* TBD!!! fix this non-standard %n */\n\t\t\tul = lflag ? va_arg (ap, unsigned long) :\n\t\t\t\tsign ? (unsigned long) va_arg (ap, int) :\n\t\t\t\tva_arg (ap, unsigned int);\n\t\t\tbase = 10;\n\t\t\tgoto number;\n\n\t\tcase 's':\n\t\t\ts = va_arg (ap, unsigned char*);\n\t\t\tif (! s)\n\t\t\t\ts = (const unsigned char*) \"(null)\";\nstring:\t\t\tif (! dot)\n\t\t\t\tn = strlen ((char*)s);\n\t\t\telse\n\t\t\t\tfor (n=0; n<dwidth && s[n]; n++)\n\t\t\t\t\tcontinue;\n\n\t\t\twidth -= n;\n\n\t\t\tif (! ladjust && width > 0)\n\t\t\t\twhile (width--)\n\t\t\t\t\tPUTC (' ');\n\t\t\twhile (n--)\n\t\t\t\tPUTC (*s++);\n\t\t\tif (ladjust && width > 0)\n\t\t\t\twhile (width--)\n\t\t\t\t\tPUTC (' ');\n\t\t\tbreak;\n\n\t\tcase 'r':\n\t\t\t/* Saturated counters. */\n\t\t\tbase = 10;\n\t\t\tif (lflag) {\n\t\t\t\tul = va_arg (ap, unsigned long);\n\t\t\t\tif (ul == -1) {\ncnt_unknown:\t\t\t\tif (ladjust)\n\t\t\t\t\t\tPUTC ('-');\n\t\t\t\t\twhile (--width > 0)\n\t\t\t\t\t\tPUTC (' ');\n\t\t\t\t\tif (! ladjust)\n\t\t\t\t\t\tPUTC ('-');\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tif (ul >= -2) {\n\t\t\t\t\tul = -3;\n\t\t\t\t\tneg = '>';\n\t\t\t\t\tgoto nosign;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tul = va_arg (ap, unsigned int);\n\t\t\t\tif (ul == (unsigned short) -1)\n\t\t\t\t\tgoto cnt_unknown;\n\t\t\t\tif (ul >= (unsigned short) -2) {\n\t\t\t\t\tul = (unsigned short) -3;\n\t\t\t\t\tneg = '>';\n\t\t\t\t\tgoto nosign;\n\t\t\t\t}\n\t\t\t}\n\t\t\tgoto nosign;\n\n\t\tcase 'u':\n\t\t\tul = lflag ? va_arg (ap, unsigned long) :\n\t\t\t\tva_arg (ap, unsigned int);\n\t\t\tbase = 10;\n\t\t\tgoto nosign;\n\n\t\tcase 'x':\n\t\tcase 'X':\n\t\t\tul = lflag ? va_arg (ap, unsigned long) :\n\t\t\t\tva_arg (ap, unsigned int);\n\t\t\tbase = 16;\n\t\t\tuppercase = (c == 'X');\n\t\t\tgoto nosign;\n\t\tcase 'z':\n\t\tcase 'Z':\n\t\t\tul = lflag ? va_arg (ap, unsigned long) :\n\t\t\t\tsign ? (unsigned long) va_arg (ap, int) :\n\t\t\t\tva_arg (ap, unsigned int);\n\t\t\tbase = 16;\n\t\t\tuppercase = (c == 'Z');\n\t\t\tgoto number;\n\nnosign:\t\t\tsign = 0;\nnumber:\t\t\tif (sign) {\n\t\t\t\tif ((long) ul < 0L) {\n\t\t\t\t\tneg = '-';\n\t\t\t\t\tul = -(long) ul;\n\t\t\t\t} else if (sign < 0)\n\t\t\t\t\tneg = '+';\n\t\t\t}\n\t\t\tif (dwidth >= (int) sizeof(nbuf)) {\n\t\t\t\textrazeros = dwidth - sizeof(nbuf) + 1;\n\t\t\t\tdwidth = sizeof(nbuf) - 1;\n\t\t\t}\n\t\t\ts = ksprintn (nbuf, ul, base, dwidth, &size);\n\t\t\tif (sharpflag && ul != 0) {\n\t\t\t\tif (base == 8)\n\t\t\t\t\tsize++;\n\t\t\t\telse if (base == 16)\n\t\t\t\t\tsize += 2;\n\t\t\t}\n\t\t\tif (neg)\n\t\t\t\tsize++;\n\n\t\t\tif (! ladjust && width && padding == ' ' &&\n\t\t\t    (width -= size) > 0)\n\t\t\t\tdo {\n\t\t\t\t\tPUTC (' ');\n\t\t\t\t} while (--width > 0);\n\n\t\t\tif (neg)\n\t\t\t\tPUTC (neg);\n\n\t\t\tif (sharpflag && ul != 0) {\n\t\t\t\tif (base == 8) {\n\t\t\t\t\tPUTC ('0');\n\t\t\t\t} else if (base == 16) {\n\t\t\t\t\tPUTC ('0');\n\t\t\t\t\tPUTC (uppercase ? 'X' : 'x');\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (extrazeros)\n\t\t\t\tdo {\n\t\t\t\t\tPUTC ('0');\n\t\t\t\t} while (--extrazeros > 0);\n\n\t\t\tif (! ladjust && width && (width -= size) > 0)\n\t\t\t\tdo {\n\t\t\t\t\tPUTC (padding);\n\t\t\t\t} while (--width > 0);\n\n\t\t\tfor (; *s; --s) {\n\t\t\t\tif (uppercase && *s>='a' && *s<='z') {\n\t\t\t\t\tPUTC (*s + 'A' - 'a');\n\t\t\t\t} else {\n\t\t\t\t\tPUTC (*s);\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (ladjust && width && (width -= size) > 0)\n\t\t\t\tdo {\n\t\t\t\t\tPUTC (' ');\n\t\t\t\t} while (--width > 0);\n\t\t\tbreak;\n\n\t\tcase 'e':\n\t\tcase 'E':\n\t\tcase 'f':\n\t\tcase 'F':\n\t\tcase 'g':\n\t\tcase 'G': {\n\t\t\tdouble d = va_arg (ap, double);\n\t\t\t/*\n\t\t\t * don't do unrealistic precision; just pad it with\n\t\t\t * zeroes later, so buffer size stays rational.\n\t\t\t */\n\t\t\tif (dwidth > DBL_DIG) {\n\t\t\t\tif ((c != 'g' && c != 'G') || sharpflag)\n\t\t\t\t\textrazeros = dwidth - DBL_DIG;\n\t\t\t\tdwidth = DBL_DIG;\n\t\t\t} else if (dwidth == -1) {\n\t\t\t\tdwidth = (lflag ? DBL_DIG : FLT_DIG);\n\t\t\t}\n\t\t\t/*\n\t\t\t * softsign avoids negative 0 if d is < 0 and\n\t\t\t * no significant digits will be shown\n\t\t\t */\n\t\t\tif (d < 0) {\n\t\t\t\tneg = 1;\n\t\t\t\td = -d;\n\t\t\t}\n\t\t\t/*\n\t\t\t * cvt may have to round up past the \"start\" of the\n\t\t\t * buffer, i.e. ``intf(\"%.2f\", (double)9.999);'';\n\t\t\t * if the first char isn't NULL, it did.\n\t\t\t */\n\t\t\tif (isnan (d) || isinf (d)) {\n\t\t\t\tstrcpy ((char*)nbuf, isnan (d) ? \"NaN\" : \"Inf\");\n\t\t\t\tsize = 3;\n\t\t\t\textrazeros = 0;\n\t\t\t\ts = nbuf;\n\t\t\t} else {\n\t\t\t\t*nbuf = 0;\n\t\t\t\tsize = cvt (d, dwidth, sharpflag, &neg, c,\n\t\t\t\t\tnbuf, nbuf + sizeof(nbuf) - 1);\n\t\t\t\tif (*nbuf) {\n\t\t\t\t\ts = nbuf;\n\t\t\t\t\tnbuf [size] = 0;\n\t\t\t\t} else {\n\t\t\t\t\ts = nbuf + 1;\n\t\t\t\t\tnbuf [size + 1] = 0;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (neg || sign)\n\t\t\t\tsize++;\n\t\t\tif (! ladjust && width && padding == ' ' &&\n\t\t\t    (width -= size) > 0)\n\t\t\t\tdo {\n\t\t\t\t\tPUTC (' ');\n\t\t\t\t} while (--width > 0);\n\n\t\t\tif (neg) {\n\t\t\t\tPUTC ('-');\n\t\t\t} else if (sign) {\n\t\t\t\tPUTC ('+');\n\t\t\t}\n\n\t\t\tif (! ladjust && width && (width -= size) > 0)\n\t\t\t\tdo {\n\t\t\t\t\tPUTC (padding);\n\t\t\t\t} while (--width > 0);\n\n\t\t\tfor (; *s; ++s) {\n\t\t\t\tif (extrazeros && (*s == 'e' || *s == 'E'))\n\t\t\t\t\tdo {\n\t\t\t\t\t\tPUTC ('0');\n\t\t\t\t\t} while (--extrazeros > 0);\n\n\t\t\t\tPUTC (*s);\n\t\t\t}\n\t\t\tif (extrazeros)\n\t\t\t\tdo {\n\t\t\t\t\tPUTC ('0');\n\t\t\t\t} while (--extrazeros > 0);\n\n\t\t\tif (ladjust && width && (width -= size) > 0)\n\t\t\t\tdo {\n\t\t\t\t\tPUTC (' ');\n\t\t\t\t} while (--width > 0);\n\t\t\tbreak;\n\t\t}\n\t\tdefault:\n\t\t\tPUTC ('%');\n\t\t\tif (lflag)\n\t\t\t\tPUTC ('l');\n\t\t\tPUTC (c);\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\n/*\n * Put a NUL-terminated ASCII number (base <= 16) in a buffer in reverse\n * order; return an optional length and a pointer to the last character\n * written in the buffer (i.e., the first character of the string).\n * The buffer pointed to by `nbuf' must have length >= MAXNBUF.\n */\nstatic unsigned char *\nksprintn (unsigned char *nbuf, unsigned long ul, unsigned char base, int width,\n\tunsigned char *lenp)\n{\n\tunsigned char *p;\n\n\tp = nbuf;\n\t*p = 0;\n\tfor (;;) {\n\t\t*++p = mkhex (ul % base);\n\t\tul /= base;\n\t\tif (--width > 0)\n\t\t\tcontinue;\n\t\tif (! ul)\n\t\t\tbreak;\n\t}\n\tif (lenp)\n\t\t*lenp = p - nbuf;\n\treturn (p);\n}\n\nstatic unsigned char\nmkhex (unsigned char ch)\n{\n\tch &= 15;\n\tif (ch > 9)\n\t\treturn ch + 'a' - 10;\n\treturn ch + '0';\n}\n\nstatic unsigned char *\ncvtround (double fract, int *exp, unsigned char *start, unsigned char *end, unsigned char ch,\n\tunsigned char *negp)\n{\n\tdouble tmp;\n\n\tif (fract) {\n\t\tmodf (fract * 10, &tmp);\n\t} else {\n\t\ttmp = ch - '0';\n\t}\n\tif (tmp > 4) {\n\t\tfor (;; --end) {\n\t\t\tif (*end == '.') {\n\t\t\t\t--end;\n\t\t\t}\n\t\t\tif (++*end <= '9') {\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\t*end = '0';\n\t\t\tif (end == start) {\n\t\t\t\tif (exp) {\t/* e/E; increment exponent */\n\t\t\t\t\t*end = '1';\n\t\t\t\t\t++*exp;\n\t\t\t\t} else {\t/* f; add extra digit */\n\t\t\t\t\t*--end = '1';\n\t\t\t\t\t--start;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t} else if (*negp) {\n\t\t/*\n\t\t * ``\"%.3f\", (double)-0.0004'' gives you a negative 0.\n\t\t */\n\t\tfor (;; --end) {\n\t\t\tif (*end == '.') {\n\t\t\t\t--end;\n\t\t\t}\n\t\t\tif (*end != '0') {\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (end == start) {\n\t\t\t\t*negp = 0;\n\t\t\t}\n\t\t}\n\t}\n\treturn start;\n}\n\nstatic unsigned char *\nexponent (unsigned char *p, int exp, unsigned char fmtch)\n{\n\tunsigned char expbuf [8], *t;\n\n\t*p++ = fmtch;\n\tif (exp < 0) {\n\t\texp = -exp;\n\t\t*p++ = '-';\n\t} else {\n\t\t*p++ = '+';\n\t}\n\tt = expbuf + sizeof(expbuf);\n\tif (exp > 9) {\n\t\tdo {\n\t\t\t*--t = exp % 10 + '0';\n\t\t} while ((exp /= 10) > 9);\n\t\t*--t = exp + '0';\n\t\tfor (; t < expbuf + sizeof(expbuf); *p++ = *t++)\n\t\t\tcontinue;\n\t} else {\n\t\t*p++ = '0';\n\t\t*p++ = exp + '0';\n\t}\n\treturn p;\n}\n\nstatic int\ncvt (double number, int prec, int sharpflag, unsigned char *negp, unsigned char fmtch,\n\tunsigned char *startp, unsigned char *endp)\n{\n\tunsigned char *p, *t;\n\tdouble fract;\n\tint dotrim, expcnt, gformat;\n\tdouble integer, tmp;\n\n\texpcnt = 0;\n\tdotrim = expcnt = gformat = 0;\n\tfract = modf (number, &integer);\n\n\t/*\n\t * get an extra slot for rounding\n\t */\n\tt = ++startp;\n\n\t/*\n\t * get integer portion of number; put into the end of the buffer; the\n\t * .01 is added for modf (356.0 / 10, &integer) returning .59999999...\n\t */\n\tfor (p = endp - 1; integer; ++expcnt) {\n\t\ttmp = modf (integer / 10, &integer);\n\t\t*p-- = (int) ((tmp + .01) * 10) + '0';\n\t}\n\tswitch (fmtch) {\n\tcase 'f':\n\t\t/* reverse integer into beginning of buffer */\n\t\tif (expcnt) {\n\t\t\tfor (; ++p < endp; *t++ = *p);\n\t\t} else {\n\t\t\t*t++ = '0';\n\t\t}\n\n\t\t/*\n\t\t * if precision required or alternate flag set, add in a\n\t\t * decimal point.\n\t\t */\n\t\tif (prec || sharpflag) {\n\t\t\t*t++ = '.';\n\t\t}\n\n\t\t/*\n\t\t * if requires more precision and some fraction left\n\t\t */\n\t\tif (fract) {\n\t\t\tif (prec) {\n\t\t\t\tdo {\n\t\t\t\t\tfract = modf (fract * 10, &tmp);\n\t\t\t\t\t*t++ = (int)tmp + '0';\n\t\t\t\t} while (--prec && fract);\n\t\t\t}\n\t\t\tif (fract) {\n\t\t\t\tstartp = cvtround (fract, 0, startp,\n\t\t\t\t\tt - 1, '0', negp);\n\t\t\t}\n\t\t}\n\t\tfor (; prec--; *t++ = '0');\n\t\tbreak;\n\tcase 'e':\n\tcase 'E':\neformat:\tif (expcnt) {\n\t\t\t*t++ = *++p;\n\t\t\tif (prec || sharpflag) {\n\t\t\t\t*t++ = '.';\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * if requires more precision and some integer left\n\t\t\t */\n\t\t\tfor (; prec && ++p < endp; --prec) {\n\t\t\t\t*t++ = *p;\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * if done precision and more of the integer component,\n\t\t\t * round using it; adjust fract so we don't re-round\n\t\t\t * later.\n\t\t\t */\n\t\t\tif (! prec && ++p < endp) {\n\t\t\t\tfract = 0;\n\t\t\t\tstartp = cvtround (0, &expcnt, startp,\n\t\t\t\t\tt - 1, *p, negp);\n\t\t\t}\n\t\t\t/*\n\t\t\t * adjust expcnt for digit in front of decimal\n\t\t\t */\n\t\t\t--expcnt;\n\t\t}\n\t\t/*\n\t\t * until first fractional digit, decrement exponent\n\t\t */\n\t\telse if (fract) {\n\t\t\t/*\n\t\t\t * adjust expcnt for digit in front of decimal\n\t\t\t */\n\t\t\tfor (expcnt = -1;; --expcnt) {\n\t\t\t\tfract = modf (fract * 10, &tmp);\n\t\t\t\tif (tmp) {\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\t*t++ = (int)tmp + '0';\n\t\t\tif (prec || sharpflag) {\n\t\t\t\t*t++ = '.';\n\t\t\t}\n\t\t} else {\n\t\t\t*t++ = '0';\n\t\t\tif (prec || sharpflag) {\n\t\t\t\t*t++ = '.';\n\t\t\t}\n\t\t}\n\t\t/*\n\t\t * if requires more precision and some fraction left\n\t\t */\n\t\tif (fract) {\n\t\t\tif (prec) {\n\t\t\t\tdo {\n\t\t\t\t\tfract = modf (fract * 10, &tmp);\n\t\t\t\t\t*t++ = (int)tmp + '0';\n\t\t\t\t} while (--prec && fract);\n\t\t\t}\n\t\t\tif (fract) {\n\t\t\t\tstartp = cvtround (fract, &expcnt, startp,\n\t\t\t\t\tt - 1, '0', negp);\n\t\t\t}\n\t\t}\n\t\t/*\n\t\t * if requires more precision\n\t\t */\n\t\tfor (; prec--; *t++ = '0');\n\n\t\t/*\n\t\t * unless alternate flag, trim any g/G format trailing 0's\n\t\t */\n\t\tif (gformat && ! sharpflag) {\n\t\t\twhile (t > startp && *--t == '0');\n\t\t\tif (*t == '.') {\n\t\t\t\t--t;\n\t\t\t}\n\t\t\t++t;\n\t\t}\n\t\tt = exponent (t, expcnt, fmtch);\n\t\tbreak;\n\tcase 'g':\n\tcase 'G':\n\t\t/*\n\t\t * a precision of 0 is treated as a precision of 1\n\t\t */\n\t\tif (!prec) {\n\t\t\t++prec;\n\t\t}\n\n\t\t/*\n\t\t * ``The style used depends on the value converted; style e\n\t\t * will be used only if the exponent resulting from the\n\t\t * conversion is less than -4 or greater than the precision.''\n\t\t *\t-- ANSI X3J11\n\t\t */\n\t\tif (expcnt > prec || (! expcnt && fract && fract < .0001)) {\n\t\t\t/*\n\t\t\t * g/G format counts \"significant digits, not digits of\n\t\t\t * precision; for the e/E format, this just causes an\n\t\t\t * off-by-one problem, i.e. g/G considers the digit\n\t\t\t * before the decimal point significant and e/E doesn't\n\t\t\t * count it as precision.\n\t\t\t */\n\t\t\t--prec;\n\t\t\tfmtch -= 2;\t\t/* G->E, g->e */\n\t\t\tgformat = 1;\n\t\t\tgoto eformat;\n\t\t}\n\t\t/*\n\t\t * reverse integer into beginning of buffer,\n\t\t * note, decrement precision\n\t\t */\n\t\tif (expcnt) {\n\t\t\tfor (; ++p < endp; *t++ = *p, --prec);\n\t\t} else {\n\t\t\t*t++ = '0';\n\t\t}\n\t\t/*\n\t\t * if precision required or alternate flag set, add in a\n\t\t * decimal point.  If no digits yet, add in leading 0.\n\t\t */\n\t\tif (prec || sharpflag) {\n\t\t\tdotrim = 1;\n\t\t\t*t++ = '.';\n\t\t} else {\n\t\t\tdotrim = 0;\n\t\t}\n\t\t/*\n\t\t * if requires more precision and some fraction left\n\t\t */\n\t\twhile (prec && fract) {\n\t\t\tfract = modf (fract * 10, &tmp);\n\t\t\t*t++ = (int)tmp + '0';\n\t\t\tprec--;\n\t\t}\n\t\tif (fract) {\n\t\t\tstartp = cvtround (fract, 0, startp, t - 1, '0', negp);\n\t\t}\n\t\t/*\n\t\t * alternate format, adds 0's for precision, else trim 0's\n\t\t */\n\t\tif (sharpflag) {\n\t\t\tfor (; prec--; *t++ = '0');\n\t\t} else if (dotrim) {\n\t\t\twhile (t > startp && *--t == '0');\n\t\t\tif (*t != '.') {\n\t\t\t\t++t;\n\t\t\t}\n\t\t}\n\t}\n\treturn t - startp;\n}\n"
  },
  {
    "path": "lib/libc/stdio/doscan.c",
    "content": "#include <stdio.h>\n#include <ctype.h>\n#include <stdarg.h>\n\n#define\tSPC\t01\n#define\tSTP\t02\n\n#define\tSHORT\t0\n#define\tREGULAR\t1\n#define\tLONG\t2\n#define\tINT\t0\n#define\tFLOAT\t1\n\nstatic char *_getccl();\n\nstatic char _sctab[256] = {\n\t0,0,0,0,0,0,0,0,\n\t0,SPC,SPC,0,0,0,0,0,\n\t0,0,0,0,0,0,0,0,\n\t0,0,0,0,0,0,0,0,\n\tSPC,0,0,0,0,0,0,0,\n\t0,0,0,0,0,0,0,0,\n\t0,0,0,0,0,0,0,0,\n\t0,0,0,0,0,0,0,0,\n};\n\nstatic int\n_instr (ptr, type, len, iop, eofptr)\n\tregister char *ptr;\n\tint type, len;\n\tregister FILE *iop;\n\tint *eofptr;\n{\n\tregister int ch;\n\tregister char *optr;\n\tint ignstp;\n\n\t*eofptr = 0;\n\toptr = ptr;\n\tif (type=='c' && len==30000)\n\t\tlen = 1;\n\tignstp = 0;\n\tif (type=='s')\n\t\tignstp = SPC;\n\twhile ((ch = getc(iop)) != EOF && _sctab[ch] & ignstp)\n\t\t;\n\tignstp = SPC;\n\tif (type=='c')\n\t\tignstp = 0;\n\telse if (type=='[')\n\t\tignstp = STP;\n\twhile (ch!=EOF && (_sctab[ch]&ignstp)==0) {\n\t\tif (ptr)\n\t\t\t*ptr++ = ch;\n\t\tif (--len <= 0)\n\t\t\tbreak;\n\t\tch = getc(iop);\n\t}\n\tif (ch != EOF) {\n\t\tif (len > 0)\n\t\t\tungetc(ch, iop);\n\t\t*eofptr = 0;\n\t} else\n\t\t*eofptr = 1;\n\tif (ptr && ptr!=optr) {\n\t\tif (type!='c')\n\t\t\t*ptr++ = '\\0';\n\t\treturn(1);\n\t}\n\treturn(0);\n}\n\nstatic int\n_innum (ptr, type, len, size, iop, eofptr)\n\tint *ptr, *eofptr;\n\tint type, len, size;\n\tFILE *iop;\n{\n\tregister char *np;\n\tchar numbuf[64];\n\tregister int c, base;\n\tint expseen, scale, negflg, c1, ndigit;\n\tlong lcval;\n\n\tif (type=='c' || type=='s' || type=='[')\n\t\treturn(_instr((char*)ptr, type, len, iop, eofptr));\n\tlcval = 0;\n\tndigit = 0;\n\tscale = INT;\n\tif (type=='e'||type=='f')\n\t\tscale = FLOAT;\n\tbase = 10;\n\tif (type=='o')\n\t\tbase = 8;\n\telse if (type=='x')\n\t\tbase = 16;\n\tnp = numbuf;\n\texpseen = 0;\n\tnegflg = 0;\n\twhile ((c = getc(iop))==' ' || c=='\\t' || c=='\\n');\n\tif (c=='-') {\n\t\tnegflg++;\n\t\t*np++ = c;\n\t\tc = getc(iop);\n\t\tlen--;\n\t} else if (c=='+') {\n\t\tlen--;\n\t\tc = getc(iop);\n\t}\n\tfor ( ; --len>=0; *np++ = c, c = getc(iop)) {\n\t\tif (isdigit(c) ||\n\t\t    (base==16 && (('a'<=c && c<='f') || ('A'<=c && c<='F')))) {\n\t\t\tndigit++;\n\t\t\tif (base==8)\n\t\t\t\tlcval <<=3;\n\t\t\telse if (base==10)\n\t\t\t\tlcval = ((lcval<<2) + lcval)<<1;\n\t\t\telse\n\t\t\t\tlcval <<= 4;\n\t\t\tc1 = c;\n\t\t\tif (isdigit(c))\n\t\t\t\tc -= '0';\n\t\t\telse if ('a'<=c && c<='f')\n\t\t\t\tc -= 'a'-10;\n\t\t\telse\n\t\t\t\tc -= 'A'-10;\n\t\t\tlcval += c;\n\t\t\tc = c1;\n\t\t\tcontinue;\n\t\t} else if (c=='.') {\n\t\t\tif (base!=10 || scale==INT)\n\t\t\t\tbreak;\n\t\t\tndigit++;\n\t\t\tcontinue;\n\t\t} else if ((c=='e'||c=='E') && expseen==0) {\n\t\t\tif (base!=10 || scale==INT || ndigit==0)\n\t\t\t\tbreak;\n\t\t\texpseen++;\n\t\t\t*np++ = c;\n\t\t\tc = getc(iop);\n\t\t\tif (c!='+'&&c!='-'&&('0'>c||c>'9'))\n\t\t\t\tbreak;\n\t\t} else\n\t\t\tbreak;\n\t}\n\tif (negflg)\n\t\tlcval = -lcval;\n\tif (c != EOF) {\n\t\tungetc(c, iop);\n\t\t*eofptr = 0;\n\t} else\n\t\t*eofptr = 1;\n \tif (ptr==NULL || np==numbuf || (negflg && np==numbuf+1) )/* gene dykes*/\n\t\treturn(0);\n\t*np++ = 0;\n\tswitch((scale<<4) | size) {\n#if HAVE_FLOAT\n\tcase (FLOAT<<4) | SHORT:\n\tcase (FLOAT<<4) | REGULAR:\n\t\t*(float*)ptr = atof(numbuf);\n\t\tbreak;\n\n\tcase (FLOAT<<4) | LONG:\n\t\t*(double*)ptr = atof(numbuf);\n\t\tbreak;\n#endif\n\tcase (INT<<4) | SHORT:\n\t\t*(short*)ptr = lcval;\n\t\tbreak;\n\n\tcase (INT<<4) | REGULAR:\n\t\t*(int*)ptr = lcval;\n\t\tbreak;\n\n\tcase (INT<<4) | LONG:\n\t\t*(long*)ptr = lcval;\n\t\tbreak;\n\t}\n\treturn(1);\n}\n\nint\n_doscan (iop, fmt, argp)\n\tFILE *iop;\n\tregister const char *fmt;\n\tva_list argp;\n{\n\tregister int ch;\n\tint nmatch, len, ch1;\n\tint *ptr, fileended, size;\n\n\tnmatch = 0;\n\tfileended = 0;\n\tfor (;;) switch (ch = *fmt++) {\n\tcase '\\0':\n\t\treturn (nmatch);\n\tcase '%':\n\t\tif ((ch = *fmt++) == '%')\n\t\t\tgoto def;\n\t\tif (ch == '*') {\n                        ptr = 0;\n\t\t\tch = *fmt++;\n\t\t} else\n\t\t\tptr = va_arg (argp, int*);\n\t\tlen = 0;\n\t\tsize = REGULAR;\n\t\twhile (isdigit(ch)) {\n\t\t\tlen = len*10 + ch - '0';\n\t\t\tch = *fmt++;\n\t\t}\n\t\tif (len == 0)\n\t\t\tlen = 30000;\n\t\tif (ch=='l') {\n\t\t\tsize = LONG;\n\t\t\tch = *fmt++;\n\t\t} else if (ch=='h') {\n\t\t\tsize = SHORT;\n\t\t\tch = *fmt++;\n\t\t} else if (ch=='[')\n\t\t\tfmt = _getccl(fmt);\n\t\tif (isupper(ch)) {\n\t\t\tch = tolower(ch);\n\t\t\tsize = LONG;\n\t\t}\n\t\tif (ch == '\\0')\n\t\t\treturn(-1);\n\t\tif (_innum(ptr, ch, len, size, iop, &fileended) && ptr)\n\t\t\tnmatch++;\n\t\tif (fileended)\n\t\t\treturn(nmatch? nmatch: -1);\n\t\tbreak;\n\n\tcase ' ':\n\tcase '\\n':\n\tcase '\\t':\n\t\twhile ((ch1 = getc(iop))==' ' || ch1=='\\t' || ch1=='\\n')\n\t\t\t;\n\t\tif (ch1 != EOF)\n\t\t\tungetc(ch1, iop);\n\t\tbreak;\n\n\tdefault:\n\tdef:\n\t\tch1 = getc(iop);\n\t\tif (ch1 != ch) {\n\t\t\tif (ch1==EOF)\n\t\t\t\treturn(-1);\n\t\t\tungetc(ch1, iop);\n\t\t\treturn(nmatch);\n\t\t}\n\t}\n}\n\nstatic char *\n_getccl(s)\nregister unsigned char *s;\n{\n\tregister int c, t;\n\n\tt = 0;\n\tif (*s == '^') {\n\t\tt++;\n\t\ts++;\n\t}\n\tfor (c = 0; c < (sizeof _sctab / sizeof _sctab[0]); c++)\n\t\tif (t)\n\t\t\t_sctab[c] &= ~STP;\n\t\telse\n\t\t\t_sctab[c] |= STP;\n\tif ((c = *s) == ']' || c == '-') {\t/* first char is special */\n\t\tif (t)\n\t\t\t_sctab[c] |= STP;\n\t\telse\n\t\t\t_sctab[c] &= ~STP;\n\t\ts++;\n\t}\n\twhile ((c = *s++) != ']') {\n\t\tif (c==0)\n\t\t\treturn((char *)--s);\n\t\telse if (c == '-' && *s != ']' && s[-2] < *s) {\n\t\t\tfor (c = s[-2] + 1; c < *s; c++)\n\t\t\t\tif (t)\n\t\t\t\t\t_sctab[c] |= STP;\n\t\t\t\telse\n\t\t\t\t\t_sctab[c] &= ~STP;\n\t\t} else if (t)\n\t\t\t_sctab[c] |= STP;\n\t\telse\n\t\t\t_sctab[c] &= ~STP;\n\t}\n\treturn((char *)s);\n}\n"
  },
  {
    "path": "lib/libc/stdio/exit.c",
    "content": "#include <stdlib.h>\n#include <unistd.h>\n\nstruct atexit {                 /* entry allocated per atexit() call */\n    struct atexit *next;        /* next enty in a list */\n    void (*func)(void);         /* callback function */\n};\n\nint errno;\nstruct atexit *__atexit;        /* points to head of LIFO stack */\n\nextern void _cleanup();\n\nvoid\nexit (code)\n    int code;\n{\n    register struct atexit *p;\n\n    for (p = __atexit; p; p = p->next)\n        (*p->func)();\n    _cleanup();\n    _exit (code);\n}\n\n/*\n * Register a function to be performed at exit.\n */\nint\natexit(fn)\n    void (*fn)();\n{\n    static struct atexit __atexit0; /* one guaranteed table */\n    register struct atexit *p;\n\n    p = __atexit;\n    if (! p) {\n        p = &__atexit0;\n    } else {\n        p = malloc(sizeof(struct atexit));\n        if (! p)\n            return -1;\n        p->next = __atexit;\n    }\n    p->func = fn;\n    __atexit = p;\n    return 0;\n}\n"
  },
  {
    "path": "lib/libc/stdio/fdopen.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * Unix routine to do an \"fopen\" on file descriptor\n * The mode has to be repeated because you can't query its\n * status\n */\n#include <sys/types.h>\n#include <sys/file.h>\n#include <stdio.h>\n#include <unistd.h>\n\nFILE *\nfdopen(fd, mode)\n\tint fd;\n\tregister const char *mode;\n{\n\tstatic int nofile = -1;\n\tregister FILE *iop;\n\n\tif (nofile < 0)\n\t\tnofile = getdtablesize();\n\n\tif (fd < 0 || fd >= nofile)\n\t\treturn (NULL);\n\n\tiop = _findiop();\n\tif (iop == NULL)\n\t\treturn (NULL);\n\n\tiop->_cnt = 0;\n\tiop->_file = fd;\n\tiop->_bufsiz = 0;\n\tiop->_base = iop->_ptr = NULL;\n\n\tswitch (*mode) {\n\tcase 'r':\n\t\tiop->_flag = _IOREAD;\n\t\tbreak;\n\tcase 'a':\n\t\tlseek(fd, (off_t)0, L_XTND);\n\t\t/* fall into ... */\n\tcase 'w':\n\t\tiop->_flag = _IOWRT;\n\t\tbreak;\n\tdefault:\n\t\treturn (NULL);\n\t}\n\n\tif (mode[1] == '+')\n\t\tiop->_flag = _IORW;\n\n\treturn (iop);\n}\n"
  },
  {
    "path": "lib/libc/stdio/feof.c",
    "content": "/*\t$OpenBSD: feof.c,v 1.5 2005/08/08 08:05:36 espie Exp $ */\n/*-\n * Copyright (c) 1990, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Chris Torek.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n#include <stdio.h>\n\n/*\n * A subroutine version of the macro feof.\n */\n#undef feof\n\nint\nfeof(FILE *fp)\n{\n\treturn (__sfeof(fp));\n}\n"
  },
  {
    "path": "lib/libc/stdio/ferror.c",
    "content": "/*\t$OpenBSD: ferror.c,v 1.5 2005/08/08 08:05:36 espie Exp $ */\n/*-\n * Copyright (c) 1990, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Chris Torek.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n#include <stdio.h>\n\n/*\n * A subroutine version of the macro ferror.\n */\n#undef ferror\n\nint\nferror(FILE *fp)\n{\n\treturn (__sferror(fp));\n}\n"
  },
  {
    "path": "lib/libc/stdio/fgetc.c",
    "content": "#include <stdio.h>\n\nint\nfgetc(fp)\n        register FILE *fp;\n{\n\treturn getc(fp);\n}\n"
  },
  {
    "path": "lib/libc/stdio/fgets.c",
    "content": "#include <stdio.h>\n\nchar *\nfgets(s, n, iop)\n        char *s;\n        int n;\n        register FILE *iop;\n{\n\tregister int c = EOF;\n\tregister char *cs;\n\n\tcs = s;\n\twhile (--n>0 && (c = getc(iop)) != EOF) {\n\t\t*cs++ = c;\n\t\tif (c=='\\n')\n\t\t\tbreak;\n\t}\n\tif (c == EOF && cs==s)\n\t\treturn(NULL);\n\t*cs++ = '\\0';\n\treturn(s);\n}\n"
  },
  {
    "path": "lib/libc/stdio/filbuf.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n\nint\n_filbuf(iop)\nregister FILE *iop;\n{\n\tint size;\n\tstruct stat stbuf;\n\textern char *_smallbuf;\n\tchar c;\n\n\tif (iop->_flag & _IORW)\n\t\tiop->_flag |= _IOREAD;\n\n\tif ((iop->_flag&_IOREAD) == 0)\n\t\treturn(EOF);\n\tif (iop->_flag&(_IOSTRG|_IOEOF))\n\t\treturn(EOF);\ntryagain:\n\tif (iop->_base==NULL) {\n\t\tif (iop->_flag&_IONBF) {\n\t\t\tiop->_base = _smallbuf ? &_smallbuf[fileno(iop)] : &c;\n\t\t\tgoto tryagain;\n\t\t}\n\t\tif (fstat(fileno(iop), &stbuf) < 0 || stbuf.st_blksize <= NULL)\n\t\t\tsize = BUFSIZ;\n\t\telse\n\t\t\tsize = stbuf.st_blksize;\n\t\tif ((iop->_base = malloc(size)) == NULL) {\n\t\t\tiop->_flag |= _IONBF;\n\t\t\tgoto tryagain;\n\t\t}\n\t\tiop->_flag |= _IOMYBUF;\n\t\tiop->_bufsiz = size;\n\t}\n\tif (iop == stdin) {\n\t\tif (stdout->_flag&_IOLBF)\n\t\t\tfflush(stdout);\n\t\tif (stderr->_flag&_IOLBF)\n\t\t\tfflush(stderr);\n\t}\n\tiop->_cnt = read(fileno(iop), iop->_base,\n\t\tiop->_flag & _IONBF ? 1 : iop->_bufsiz);\n\tiop->_ptr = iop->_base;\n\tif (iop->_flag & _IONBF && iop->_base == &c)\n\t\tiop->_base = NULL;\n\tif (--iop->_cnt < 0) {\n\t\tif (iop->_cnt == -1) {\n\t\t\tiop->_flag |= _IOEOF;\n\t\t\tif (iop->_flag & _IORW)\n\t\t\t\tiop->_flag &= ~_IOREAD;\n\t\t} else\n\t\t\tiop->_flag |= _IOERR;\n\t\tiop->_cnt = 0;\n\t\treturn(EOF);\n\t}\n\treturn(*iop->_ptr++&0377);\n}\n"
  },
  {
    "path": "lib/libc/stdio/fileno.c",
    "content": "/*\t$OpenBSD: fileno.c,v 1.5 2005/08/08 08:05:36 espie Exp $ */\n/*-\n * Copyright (c) 1990, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Chris Torek.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n#include <stdio.h>\n\n/*\n * A subroutine version of the macro fileno.\n */\n#undef fileno\n\nint\nfileno(FILE *fp)\n{\n\treturn (__sfileno(fp));\n}\n"
  },
  {
    "path": "lib/libc/stdio/findiop.c",
    "content": "/*\n * Copyright (c) 1983, 1985 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <errno.h>\n\nextern int errno;\n\n#define active(iop)\t((iop)->_flag & (_IOREAD|_IOWRT|_IORW))\n\n#define NSTATIC\t20\t/* stdin + stdout + stderr + the usual */\n\nFILE _iob[NSTATIC] = {\n\t{ 0, NULL, NULL, 0, _IOREAD,\t\t0 },\t/* stdin  */\n\t{ 0, NULL, NULL, 0, _IOWRT,\t\t1 },\t/* stdout */\n\t{ 0, NULL, NULL, 0, _IOWRT|_IONBF,\t2 },\t/* stderr */\n};\n\nstatic\tchar sbuf[NSTATIC];\nchar\t*_smallbuf = sbuf;\nstatic\tFILE\t**iobglue;\nstatic\tFILE\t**endglue;\n\nstatic int\n_f_morefiles()\n{\n\tregister FILE **iov;\n\tregister FILE *fp;\n\tint nfiles;\n\n\tnfiles = getdtablesize();\n\n\tiobglue = (FILE **)calloc(nfiles, sizeof *iobglue);\n\tif (iobglue == NULL)\n\t\treturn (0);\n\n\tendglue = iobglue + nfiles;\n\n\tfor (fp = _iob, iov = iobglue; fp < &_iob[NSTATIC]; /* void */)\n\t\t*iov++ = fp++;\n\n\t_smallbuf = calloc(nfiles, sizeof(*_smallbuf));\n\treturn (1);\n}\n\n/*\n * Find a free FILE for fopen et al.\n * We have a fixed static array of entries, and in addition\n * may allocate additional entries dynamically, up to the kernel\n * limit on the number of open files.\n * At first just check for a free slot in the fixed static array.\n * If none are available, then we allocate a structure to glue together\n * the old and new FILE entries, which are then no longer contiguous.\n */\nFILE *\n_findiop()\n{\n\tregister FILE **iov, *iop;\n\n\tif (iobglue == 0) {\n\t\tfor (iop = _iob; iop < _iob + NSTATIC; iop++)\n\t\t\tif (!active(iop))\n\t\t\t\treturn (iop);\n\n\t\tif (_f_morefiles() == 0) {\n\t\t\terrno = ENOMEM;\n\t\t\treturn (NULL);\n\t\t}\n\t}\n\n\tiov = iobglue;\n\twhile (*iov != NULL && active(*iov))\n\t\tif (++iov >= endglue) {\n\t\t\terrno = EMFILE;\n\t\t\treturn (NULL);\n\t\t}\n\n\tif (*iov == NULL)\n\t\t*iov = (FILE *)calloc(1, sizeof **iov);\n\n\treturn (*iov);\n}\n\nvoid\nf_prealloc()\n{\n\tregister FILE **iov;\n\n\tif (iobglue == NULL && _f_morefiles() == 0)\n\t\treturn;\n\n\tfor (iov = iobglue; iov < endglue; iov++)\n\t\tif (*iov == NULL)\n\t\t\t*iov = (FILE *)calloc(1, sizeof **iov);\n}\n\nvoid\n_fwalk(function)\n\tregister int (*function)();\n{\n\tregister FILE **iov;\n\tregister FILE *fp;\n\n\tif (iobglue == NULL) {\n\t\tfor (fp = _iob; fp < &_iob[NSTATIC]; fp++)\n\t\t\tif (active(fp))\n\t\t\t\t(*function)(fp);\n\t} else {\n\t\tfor (iov = iobglue; iov < endglue; iov++)\n\t\t\tif (*iov && active(*iov))\n\t\t\t\t(*function)(*iov);\n\t}\n}\n\nvoid _cleanup()\n{\n\textern int fclose();\n\n\t_fwalk(fclose);\n}\n"
  },
  {
    "path": "lib/libc/stdio/flsbuf.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n\nint _flsbuf(c, iop)\n    unsigned char c;\n    register FILE *iop;\n{\n\tregister char *base;\n\tregister int n, rn;\n\tchar c1;\n\tint size;\n\tstruct stat stbuf;\n\n\tif (iop->_flag & _IORW) {\n\t\tiop->_flag |= _IOWRT;\n\t\tiop->_flag &= ~(_IOEOF|_IOREAD);\n\t}\n\n\tif ((iop->_flag&_IOWRT)==0)\n\t\treturn(EOF);\ntryagain:\n\tif (iop->_flag&_IOLBF) {\n\t\tbase = iop->_base;\n\t\t*iop->_ptr++ = c;\n\t\tif (iop->_ptr >= base+iop->_bufsiz || c == '\\n') {\n\t\t\tn = write(fileno(iop), base, rn = iop->_ptr - base);\n\t\t\tiop->_ptr = base;\n\t\t\tiop->_cnt = 0;\n\t\t} else\n\t\t\trn = n = 0;\n\t} else if (iop->_flag&_IONBF) {\n\t\tc1 = c;\n\t\trn = 1;\n\t\tn = write(fileno(iop), &c1, rn);\n\t\tiop->_cnt = 0;\n\t} else {\n\t\tif ((base=iop->_base)==NULL) {\n\t\t\tif (fstat(fileno(iop), &stbuf) < 0 ||\n\t\t\t    stbuf.st_blksize <= NULL)\n\t\t\t\tsize = BUFSIZ;\n\t\t\telse\n\t\t\t\tsize = stbuf.st_blksize;\n\t\t\tif ((iop->_base=base=malloc(size)) == NULL) {\n\t\t\t\tiop->_flag |= _IONBF;\n\t\t\t\tgoto tryagain;\n\t\t\t}\n\t\t\tiop->_flag |= _IOMYBUF;\n\t\t\tiop->_bufsiz = size;\n\t\t\tif (iop==stdout && isatty(fileno(stdout))) {\n\t\t\t\tiop->_flag |= _IOLBF;\n\t\t\t\tiop->_ptr = base;\n\t\t\t\tgoto tryagain;\n\t\t\t}\n\t\t\trn = n = 0;\n\t\t} else if ((rn = n = iop->_ptr - base) > 0) {\n\t\t\tiop->_ptr = base;\n\t\t\tn = write(fileno(iop), base, n);\n\t\t}\n\t\tiop->_cnt = iop->_bufsiz-1;\n\t\t*base++ = c;\n\t\tiop->_ptr = base;\n\t}\n\tif (rn != n) {\n\t\tiop->_flag |= _IOERR;\n\t\treturn(EOF);\n\t}\n\treturn(c);\n}\n\nint\nfflush(iop)\nregister FILE *iop;\n{\n\tregister char *base;\n\tregister int n;\n\n\tif ((iop->_flag&(_IONBF|_IOWRT))==_IOWRT\n\t && (base=iop->_base)!=NULL && (n=iop->_ptr-base)>0) {\n\t\tiop->_ptr = base;\n\t\tiop->_cnt = (iop->_flag&(_IOLBF|_IONBF)) ? 0 : iop->_bufsiz;\n\t\tif (write(fileno(iop), base, n)!=n) {\n\t\t\tiop->_flag |= _IOERR;\n\t\t\treturn(EOF);\n\t\t}\n\t}\n\treturn(0);\n}\n\nint\nfclose(iop)\n\tregister FILE *iop;\n{\n\tregister int r;\n\n\tr = EOF;\n\tif (iop->_flag&(_IOREAD|_IOWRT|_IORW) && (iop->_flag&_IOSTRG)==0) {\n\t\tr = fflush(iop);\n\t\tif (close(fileno(iop)) < 0)\n\t\t\tr = EOF;\n\t\tif (iop->_flag&_IOMYBUF)\n\t\t\tfree(iop->_base);\n\t}\n\tiop->_cnt = 0;\n\tiop->_base = (char *)NULL;\n\tiop->_ptr = (char *)NULL;\n\tiop->_bufsiz = 0;\n\tiop->_flag = 0;\n\tiop->_file = 0;\n\treturn(r);\n}\n"
  },
  {
    "path": "lib/libc/stdio/fopen.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/types.h>\n#include <sys/file.h>\n#include <stdio.h>\n#include <unistd.h>\n#include <fcntl.h>\n\nFILE *\nfopen(file, mode)\n\tconst char *file;\n\tregister const char *mode;\n{\n\tregister FILE *iop;\n\tregister int f, rw, oflags;\n\textern FILE *_findiop();\n\n\tiop = _findiop();\n\tif (iop == NULL)\n\t\treturn (NULL);\n\n\trw = (mode[1] == '+');\n\n\tswitch (*mode) {\n\tcase 'a':\n\t\toflags = O_CREAT | (rw ? O_RDWR : O_WRONLY);\n\t\tbreak;\n\tcase 'r':\n\t\toflags = rw ? O_RDWR : O_RDONLY;\n\t\tbreak;\n\tcase 'w':\n\t\toflags = O_TRUNC | O_CREAT | (rw ? O_RDWR : O_WRONLY);\n\t\tbreak;\n\tdefault:\n\t\treturn (NULL);\n\t}\n\n\tf = open(file, oflags, 0666);\n\tif (f < 0)\n\t\treturn (NULL);\n\n\tif (*mode == 'a')\n\t\tlseek(f, (off_t)0, L_XTND);\n\n\tiop->_cnt = 0;\n\tiop->_file = f;\n\tiop->_bufsiz = 0;\n\tif (rw)\n\t\tiop->_flag = _IORW;\n\telse if (*mode == 'r')\n\t\tiop->_flag = _IOREAD;\n\telse\n\t\tiop->_flag = _IOWRT;\n\tiop->_base = iop->_ptr = NULL;\n\treturn (iop);\n}\n"
  },
  {
    "path": "lib/libc/stdio/fprintf.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <stdio.h>\n#include <stdarg.h>\n#include <alloca.h>\n\nint\nfprintf (register FILE *iop, const char *fmt, ...)\n{\n\tva_list ap;\n\n\tva_start (ap, fmt);\n\tif (iop->_flag & _IONBF) {\n\t\tiop->_flag &= ~_IONBF;\n\t\tiop->_ptr = iop->_base = alloca(BUFSIZ);\n\t\tiop->_bufsiz = BUFSIZ;\n\t\t_doprnt(fmt, ap, iop);\n\t\tfflush(iop);\n\t\tiop->_flag |= _IONBF;\n\t\tiop->_base = NULL;\n\t\tiop->_bufsiz = NULL;\n\t\tiop->_cnt = 0;\n\t} else\n\t\t_doprnt(fmt, ap, iop);\n\tva_end (ap);\n\treturn(ferror(iop)? EOF: 0);\n}\n"
  },
  {
    "path": "lib/libc/stdio/fputc.c",
    "content": "#include <stdio.h>\n\nint\nfputc (c, fp)\n\tregister int c;\n\tregister FILE *fp;\n{\n\treturn putc (c, fp);\n}\n"
  },
  {
    "path": "lib/libc/stdio/fputs.c",
    "content": "/*\n * Copyright (c) 1984 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <stdio.h>\n#include <alloca.h>\n\nint\nfputs(s, iop)\n\tregister const char *s;\n\tregister FILE *iop;\n{\n\tregister int r = 0, c;\n\tint unbuffered;\n\n\tunbuffered = iop->_flag & _IONBF;\n\tif (unbuffered) {\n\t\tiop->_flag &= ~_IONBF;\n\t\tiop->_ptr = iop->_base = alloca(BUFSIZ);\n\t\tiop->_bufsiz = BUFSIZ;\n\t}\n\n\twhile ((c = *s++))\n\t\tr = putc(c, iop);\n\n\tif (unbuffered) {\n\t\tfflush(iop);\n\t\tiop->_flag |= _IONBF;\n\t\tiop->_base = NULL;\n\t\tiop->_bufsiz = NULL;\n\t\tiop->_cnt = 0;\n\t}\n\n\treturn(r);\n}\n"
  },
  {
    "path": "lib/libc/stdio/fread.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <stdio.h>\n#include <strings.h>\n\nsize_t\nfread (vptr, size, count, iop)\n\tregister void *vptr;\n\tsize_t size, count;\n\tregister FILE *iop;\n{\n\tregister char *ptr = vptr;\n\tregister unsigned s;\n\tint c;\n\n\ts = size * count;\n\twhile (s > 0) {\n\t\tif (iop->_cnt < s) {\n\t\t\tif (iop->_cnt > 0) {\n\t\t\t\tbcopy(iop->_ptr, ptr, iop->_cnt);\n\t\t\t\tptr += iop->_cnt;\n\t\t\t\ts -= iop->_cnt;\n\t\t\t}\n\t\t\t/*\n\t\t\t * filbuf clobbers _cnt & _ptr,\n\t\t\t * so don't waste time setting them.\n\t\t\t */\n\t\t\tif ((c = _filbuf(iop)) == EOF)\n\t\t\t\tbreak;\n\t\t\t*ptr++ = c;\n\t\t\ts--;\n\t\t}\n\t\tif (iop->_cnt >= s) {\n\t\t\tbcopy(iop->_ptr, ptr, s);\n\t\t\tiop->_ptr += s;\n\t\t\tiop->_cnt -= s;\n\t\t\treturn (count);\n\t\t}\n\t}\n\treturn (size != 0 ? count - ((s + size - 1) / size) : 0);\n}\n"
  },
  {
    "path": "lib/libc/stdio/freopen.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/types.h>\n#include <sys/file.h>\n#include <stdio.h>\n#include <unistd.h>\n#include <fcntl.h>\n\nFILE *\nfreopen(file, mode, iop)\n\tconst char *file;\n\tregister const char *mode;\n\tregister FILE *iop;\n{\n\tregister int f, rw, oflags;\n\n\trw = (mode[1] == '+');\n\n\tfclose(iop);\n\n\tswitch (*mode) {\n\tcase 'a':\n\t\toflags = O_CREAT | (rw ? O_RDWR : O_WRONLY);\n\t\tbreak;\n\tcase 'r':\n\t\toflags = rw ? O_RDWR : O_RDONLY;\n\t\tbreak;\n\tcase 'w':\n\t\toflags = O_TRUNC | O_CREAT | (rw ? O_RDWR : O_WRONLY);\n\t\tbreak;\n\tdefault:\n\t\treturn (NULL);\n\t}\n\n\tf = open(file, oflags, 0666);\n\tif (f < 0)\n\t\treturn (NULL);\n\n\tif (*mode == 'a')\n\t\tlseek(f, (off_t)0, L_XTND);\n\n\tiop->_cnt = 0;\n\tiop->_file = f;\n\tiop->_bufsiz = 0;\n\tif (rw)\n\t\tiop->_flag = _IORW;\n\telse if (*mode == 'r')\n\t\tiop->_flag = _IOREAD;\n\telse\n\t\tiop->_flag = _IOWRT;\n\tiop->_base = iop->_ptr = NULL;\n\treturn (iop);\n}\n"
  },
  {
    "path": "lib/libc/stdio/fseek.c",
    "content": "/*\n * Seek for standard library.  Coordinates with buffering.\n */\n#include <stdio.h>\n#include <unistd.h>\n\nint\nfseek(iop, offset, ptrname)\n\tregister FILE *iop;\n\tlong offset;\n\tint ptrname;\n{\n\tregister int resync, c;\n\tlong p = -1;\t\t\t/* can't happen? */\n\n\tiop->_flag &= ~_IOEOF;\n\tif (iop->_flag&_IOREAD) {\n\t\tif (ptrname<2 && iop->_base &&\n\t\t\t!(iop->_flag&_IONBF)) {\n\t\t\tc = iop->_cnt;\n\t\t\tp = offset;\n\t\t\tif (ptrname==0) {\n\t\t\t\tlong curpos = lseek(fileno(iop), 0L, 1);\n\t\t\t\tif (curpos == -1)\n\t\t\t\t\treturn (-1);\n\t\t\t\tp += c - curpos;\n\t\t\t} else\n\t\t\t\toffset -= c;\n\t\t\tif(!(iop->_flag&_IORW) && c>0&&p<=c\n\t\t\t    && p>=iop->_base-iop->_ptr){\n\t\t\t\tiop->_ptr += (int)p;\n\t\t\t\tiop->_cnt -= (int)p;\n\t\t\t\treturn(0);\n\t\t\t}\n\t\t\tresync = offset&01;\n\t\t} else\n\t\t\tresync = 0;\n\t\tif (iop->_flag & _IORW) {\n\t\t\tiop->_ptr = iop->_base;\n\t\t\tiop->_flag &= ~_IOREAD;\n\t\t\tresync = 0;\n\t\t}\n\t\tp = lseek(fileno(iop), offset-resync, ptrname);\n\t\tiop->_cnt = 0;\n\t\tif (resync && p != -1)\n\t\t\tif (getc(iop) == EOF)\n\t\t\t\tp = -1;\n\t}\n\telse if (iop->_flag & (_IOWRT|_IORW)) {\n\t\tp = fflush(iop);\n\t\tif (iop->_flag & _IORW) {\n\t\t\tiop->_cnt = 0;\n\t\t\tiop->_flag &= ~_IOWRT;\n\t\t\tiop->_ptr = iop->_base;\n\t\t}\n\t\treturn(lseek(fileno(iop), offset, ptrname) == -1 || p == EOF ?\n\t\t    -1 : 0);\n\t}\n\treturn(p==-1?-1:0);\n}\n"
  },
  {
    "path": "lib/libc/stdio/ftell.c",
    "content": "/*\n * Return file offset.\n * Coordinates with buffering.\n */\n#include <stdio.h>\n#include <unistd.h>\n\nlong ftell(iop)\n        register FILE *iop;\n{\n\tregister long tres;\n\tregister int adjust;\n\n\tif (iop->_cnt < 0)\n\t\tiop->_cnt = 0;\n\tif (iop->_flag&_IOREAD)\n\t\tadjust = - iop->_cnt;\n\telse if (iop->_flag&(_IOWRT|_IORW)) {\n\t\tadjust = 0;\n\t\tif (iop->_flag&_IOWRT && iop->_base && (iop->_flag&_IONBF)==0)\n\t\t\tadjust = iop->_ptr - iop->_base;\n\t} else\n\t\treturn(-1);\n\ttres = lseek(fileno(iop), 0L, 1);\n\tif (tres<0)\n\t\treturn(tres);\n\ttres += adjust;\n\treturn(tres);\n}\n"
  },
  {
    "path": "lib/libc/stdio/fwrite.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <stdio.h>\n#include <strings.h>\n\nsize_t\nfwrite(vptr, size, count, iop)\n\tconst void *vptr;\n\tsize_t size, count;\n\tregister FILE *iop;\n{\n\tregister const char *ptr = vptr;\n\tregister unsigned s;\n\n\ts = size * count;\n\tif (iop->_flag & _IOLBF)\n\t\twhile (s > 0) {\n\t\t\tif (--iop->_cnt > -iop->_bufsiz && *ptr != '\\n')\n\t\t\t\t*iop->_ptr++ = *ptr++;\n\t\t\telse if (_flsbuf(*(unsigned char *)ptr++, iop) == EOF)\n\t\t\t\tbreak;\n\t\t\ts--;\n\t\t}\n\telse while (s > 0) {\n\t\tif (iop->_cnt < s) {\n\t\t\tif (iop->_cnt > 0) {\n\t\t\t\tbcopy(ptr, iop->_ptr, iop->_cnt);\n\t\t\t\tptr += iop->_cnt;\n\t\t\t\tiop->_ptr += iop->_cnt;\n\t\t\t\ts -= iop->_cnt;\n\t\t\t}\n\t\t\tif (_flsbuf(*(unsigned char *)ptr++, iop) == EOF)\n\t\t\t\tbreak;\n\t\t\ts--;\n\t\t}\n\t\tif (iop->_cnt >= s) {\n\t\t\tbcopy(ptr, iop->_ptr, s);\n\t\t\tiop->_ptr += s;\n\t\t\tiop->_cnt -= s;\n\t\t\treturn (count);\n\t\t}\n\t}\n\treturn (size != 0 ? count - ((s + size - 1) / size) : 0);\n}\n"
  },
  {
    "path": "lib/libc/stdio/getchar.c",
    "content": "/*\n * A subroutine version of the macro getchar.\n */\n#define\tUSE_STDIO_MACROS\n#include <stdio.h>\n\n#undef getchar\n\nint\ngetchar()\n{\n\treturn getc(stdin);\n}\n"
  },
  {
    "path": "lib/libc/stdio/gets.c",
    "content": "#include <stdio.h>\n\nchar *\ngets(s)\nchar *s;\n{\n\tregister int c;\n\tregister char *cs;\n\n\tcs = s;\n\twhile ((c = getchar()) != '\\n' && c != EOF)\n\t\t*cs++ = c;\n\tif (c == EOF && cs==s)\n\t\treturn(NULL);\n\t*cs++ = '\\0';\n\treturn(s);\n}\n"
  },
  {
    "path": "lib/libc/stdio/getw.c",
    "content": "#include <stdio.h>\n\nint\ngetw(iop)\n        register FILE *iop;\n{\n\tregister int i;\n\tregister char *p;\n\tint w;\n\n\tp = (char *)&w;\n\tfor (i=sizeof(int); --i>=0;)\n\t\t*p++ = getc(iop);\n\tif (feof(iop))\n\t\treturn(EOF);\n\treturn(w);\n}\n\n#ifdef pdp11\nlong\ngetlw(iop)\nregister FILE *iop;\n{\n\tregister int i;\n\tregister char *p;\n\tlong w;\n\n\tp = (char *)&w;\n\tfor (i=sizeof(long); --i>=0;)\n\t\t*p++ = getc(iop);\n\tif (feof(iop))\n\t\treturn(EOF);\n\treturn(w);\n}\n#endif\n"
  },
  {
    "path": "lib/libc/stdio/printf.c",
    "content": "#include <stdio.h>\n#include <stdarg.h>\n\nint\nprintf (const char *fmt, ...)\n{\n\tva_list args;\n\n\tva_start (args, fmt);\n\t_doprnt (fmt, args, stdout);\n\tva_end (args);\n\treturn ferror (stdout) ? EOF : 0;\n}\n"
  },
  {
    "path": "lib/libc/stdio/putchar.c",
    "content": "/*\n * A subroutine version of the macro putchar\n */\n#define\tUSE_STDIO_MACROS\n#include <stdio.h>\n\n#undef putchar\n\nint\nputchar(c)\n        register int c;\n{\n\treturn putc(c, stdout);\n}\n"
  },
  {
    "path": "lib/libc/stdio/puts.c",
    "content": "#include <stdio.h>\n\nint\nputs(s)\n\tregister const char *s;\n{\n\tregister int c;\n\n\twhile ((c = *s++))\n\t\tputchar(c);\n\treturn(putchar('\\n'));\n}\n"
  },
  {
    "path": "lib/libc/stdio/putw.c",
    "content": "#include <stdio.h>\n\nint\nputw(w, iop)\n\tint w;\n        register FILE *iop;\n{\n\tregister char *p;\n\tregister int i;\n\n\tp = (char *)&w;\n\tfor (i=sizeof(int); --i>=0;)\n\t\tputc(*p++, iop);\n\treturn(ferror(iop));\n}\n\n#ifdef pdp11\nint\nputlw(w, iop)\n        long w;\n        register FILE *iop;\n{\n\tregister char *p;\n\tregister int i;\n\n\tp = (char *)&w;\n\tfor (i=sizeof(long); --i>=0;)\n\t\tputc(*p++, iop);\n\treturn(ferror(iop));\n}\n#endif\n"
  },
  {
    "path": "lib/libc/stdio/remove.c",
    "content": "/*-\n * Copyright (c) 1990, 1993\n *  The Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Chris Torek.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <unistd.h>\n#include <stdio.h>\n\nint\nremove(file)\n    const char *file;\n{\n    struct stat sb;\n\n    if (lstat(file, &sb) < 0)\n        return (-1);\n    if (S_ISDIR(sb.st_mode))\n        return (rmdir(file));\n    return (unlink(file));\n}\n"
  },
  {
    "path": "lib/libc/stdio/rew.c",
    "content": "#include <stdio.h>\n#include <unistd.h>\n\nvoid\nrewind(iop)\n        register FILE *iop;\n{\n\tfflush(iop);\n\tlseek(fileno(iop), 0L, 0);\n\tiop->_cnt = 0;\n\tiop->_ptr = iop->_base;\n\tiop->_flag &= ~(_IOERR|_IOEOF);\n\tif (iop->_flag & _IORW)\n\t\tiop->_flag &= ~(_IOREAD|_IOWRT);\n}\n"
  },
  {
    "path": "lib/libc/stdio/scanf.c",
    "content": "#include <stdio.h>\n#include <stdarg.h>\n\nint\nscanf (const char *fmt, ...)\n{\n\tva_list args;\n\tint n;\n\n\tva_start (args, fmt);\n\tn = _doscan (stdin, fmt, args);\n\tva_end (args);\n\treturn n;\n}\n\nint\nfscanf (FILE *iop, const char *fmt, ...)\n{\n\tva_list args;\n\tint n;\n\n\tva_start (args, fmt);\n\tn = _doscan(iop, fmt, args);\n\tva_end (args);\n\treturn n;\n}\n\nint\nsscanf (const char *str, const char *fmt, ...)\n{\n\tFILE _strbuf;\n\tva_list args;\n\tint n;\n\n\t_strbuf._flag = _IOREAD|_IOSTRG;\n\t_strbuf._ptr = _strbuf._base = (void*) str;\n\t_strbuf._cnt = 0;\n\twhile (*str++)\n\t\t_strbuf._cnt++;\n\t_strbuf._bufsiz = _strbuf._cnt;\n\tva_start (args, fmt);\n\tn = _doscan(&_strbuf, fmt, args);\n\tva_end (args);\n\treturn n;\n}\n"
  },
  {
    "path": "lib/libc/stdio/setbuf.c",
    "content": "/*-\n * Copyright (c) 1990, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Chris Torek.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <stdio.h>\n\nvoid\nsetbuf(fp, buf)\n\tFILE *fp;\n\tchar *buf;\n{\n\t(void) setvbuf(fp, buf, buf ? _IOFBF : _IONBF, BUFSIZ);\n}\n"
  },
  {
    "path": "lib/libc/stdio/setbuffer.c",
    "content": "/*-\n * Copyright (c) 1990, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Chris Torek.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <stdio.h>\n#include <sys/types.h>\n\nvoid\nsetbuffer(fp, buf, size)\n\tregister FILE *fp;\n\tchar *buf;\n\tsize_t size;\n{\n\tsetvbuf(fp, buf, buf ? _IOFBF : _IONBF, size);\n}\n\n/*\n * set line buffering\n */\nvoid\nsetlinebuf(fp)\n\tFILE *fp;\n{\n\n\tsetvbuf(fp, (char *)NULL, _IOLBF, (size_t)0);\n}\n"
  },
  {
    "path": "lib/libc/stdio/setvbuf.c",
    "content": "/*-\n * Copyright (c) 1990, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Chris Torek.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <sys/types.h>\n\n/*\n * This has been slightly trimmed from the 4.4BSD version for use with 2.11BSD.\n * In particular 1) the flag names were changed back to the original ones\n * since I didn't feel like porting all of 4.4's stdio package right now and\n * 2) The constant BUFSIZ is used rather than importing the \"optimum buffer\n * size selection\" logic from 4.4 (besides, a PDP11 can't afford more than 1kb\n * most of the time anyhow).\n *\n * Set one of the three kinds of buffering, optionally including\n * a buffer.\n */\nint\nsetvbuf(fp, buf, mode, size)\n\tregister FILE *fp;\n\tchar *buf;\n\tregister int mode;\n\tsize_t size;\n{\n\tint\tret;\n\tregister int flags;\n\n/*\n * Verify arguments. Note, buf and size are ignored when setting _IONBF.\n */\n\tif (mode != _IONBF)\n\t\tif ((mode != _IOFBF && mode != _IOLBF) || (int)size < 0)\n\t\t\treturn (EOF);\n\n\t/*\n\t * Write current buffer, if any.  Discard unread input, cancel\n\t * line buffering, and free old buffer if malloc()ed.\n\t */\n\t(void)fflush(fp);\n\tfp->_cnt = fp->_bufsiz = 0;\n\tflags = fp->_flag;\n\tif (flags & _IOMYBUF)\n\t\tfree((void *)fp->_base);\n\tflags &= ~(_IOLBF | _IONBF | _IOMYBUF);\n\tret = 0;\n\n\t/* If setting unbuffered mode, skip all the hard work. */\n\tif (mode == _IONBF)\n\t\tgoto nbf;\n\n\tif (size == 0) {\n\t\tbuf = NULL;\t/* force local allocation */\n\t\tsize = BUFSIZ;\n\t}\n\n\t/* Allocate buffer if needed. */\n\tif (buf == NULL) {\n\t\tif ((buf = (char *)malloc(size)) == NULL) {\n\t\t\t/*\n\t\t\t * Unable to honor user's request.  We will return\n\t\t\t * failure, but try again with file system size.\n\t\t\t */\n\t\t\tret = EOF;\n\t\t\tif (size != BUFSIZ) {\n\t\t\t\tsize = BUFSIZ;\n\t\t\t\tbuf = (char *)malloc(size);\n\t\t\t}\n\t\t}\n\t\tif (buf == NULL) {\n\t\t\t/* No luck; switch to unbuffered I/O. */\nnbf:\n\t\t\tfp->_flag = flags | _IONBF;\n\t\t\tfp->_base = fp->_ptr = NULL;\n\t\t\treturn (ret);\n\t\t}\n\t\tflags |= _IOMYBUF;\n\t}\n\n\t/*\n\t * Fix up the FILE fields.  If in r/w mode, go to the unknown state\n\t * so that the the first read performs its initial call to _filbuf and\n\t * the first write has an empty buffer to fill.\n\t */\n\tif (mode == _IOLBF)\n\t\tflags |= _IOLBF;\n\tif (flags & _IORW)\n\t\tflags &= ~(_IOREAD | _IOWRT);\n\tfp->_flag = flags;\n\tfp->_base = fp->_ptr = (char *)buf;\n\tfp->_bufsiz = size;\n\treturn (ret);\n}\n"
  },
  {
    "path": "lib/libc/stdio/snprintf.c",
    "content": "/*\n * Copyright (c) 1988 Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that the above copyright notice and this paragraph are\n * duplicated in all such forms and that any documentation,\n * advertising materials, and other materials related to such\n * distribution and use acknowledge that the software was developed\n * by the University of California, Berkeley.  The name of the\n * University may not be used to endorse or promote products derived\n * from this software without specific prior written permission.\n * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n */\n#include <stdio.h>\n#include <stdarg.h>\n\nint\nsnprintf (char *str, size_t nbytes, const char *fmt, ...)\n{\n\tFILE _strbuf;\n\tva_list args;\n\n\t_strbuf._flag = _IOWRT+_IOSTRG;\n\t_strbuf._ptr = str;\n\t_strbuf._cnt = nbytes;\n\tva_start (args, fmt);\n\t_doprnt (fmt, args, &_strbuf);\n\tva_end (args);\n\t*_strbuf._ptr = 0;\n\treturn _strbuf._ptr - str;\n}\n"
  },
  {
    "path": "lib/libc/stdio/sprintf.c",
    "content": "/*\n * Copyright (c) 1988 Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that the above copyright notice and this paragraph are\n * duplicated in all such forms and that any documentation,\n * advertising materials, and other materials related to such\n * distribution and use acknowledge that the software was developed\n * by the University of California, Berkeley.  The name of the\n * University may not be used to endorse or promote products derived\n * from this software without specific prior written permission.\n * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n */\n#include <stdio.h>\n#include <stdarg.h>\n\nint\nsprintf (char *str, const char *fmt, ...)\n{\n\tFILE _strbuf;\n\tva_list args;\n\n\t_strbuf._flag = _IOWRT+_IOSTRG;\n\t_strbuf._ptr = str;\n\t_strbuf._cnt = 32767;\n\tva_start (args, fmt);\n\t_doprnt (fmt, args, &_strbuf);\n\tva_end (args);\n\t*_strbuf._ptr = 0;\n\treturn _strbuf._ptr - str;\n}\n"
  },
  {
    "path": "lib/libc/stdio/strout.c",
    "content": "#include <stdio.h>\n\nvoid\n_strout(count, string, adjust, file, fillch)\n        register char *string;\n        register int count;\n        int adjust;\n        register FILE *file;\n\tint fillch;\n{\n\twhile (adjust < 0) {\n\t\tif (*string=='-' && fillch=='0') {\n\t\t\tputc(*string++, file);\n\t\t\tcount--;\n\t\t}\n\t\tputc(fillch, file);\n\t\tadjust++;\n\t}\n\twhile (--count>=0)\n\t\tputc(*string++, file);\n\twhile (adjust) {\n\t\tputc(fillch, file);\n\t\tadjust--;\n\t}\n}\n"
  },
  {
    "path": "lib/libc/stdio/ungetc.c",
    "content": "#include <stdio.h>\n\nint\nungetc(c, iop)\n\tint c;\n\tregister FILE *iop;\n{\n\tif (c == EOF || (iop->_flag & (_IOREAD|_IORW)) == 0 ||\n\t    iop->_ptr == NULL || iop->_base == NULL)\n\t\treturn (EOF);\n\n\tif (iop->_ptr == iop->_base) {\n\t\tif (iop->_cnt == 0)\n\t\t\tiop->_ptr++;\n\t\telse\n\t\t\treturn (EOF);\n        }\n\n\tiop->_cnt++;\n\t*--iop->_ptr = c;\n\n\treturn (c);\n}\n"
  },
  {
    "path": "lib/libc/stdio/vfprintf.c",
    "content": "/*\n * Copyright (c) 1988 Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that the above copyright notice and this paragraph are\n * duplicated in all such forms and that any documentation,\n * advertising materials, and other materials related to such\n * distribution and use acknowledge that the software was developed\n * by the University of California, Berkeley.  The name of the\n * University may not be used to endorse or promote products derived\n * from this software without specific prior written permission.\n * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n */\n#include <stdio.h>\n#include <stdarg.h>\n#include <alloca.h>\n\nint\nvfprintf(FILE *iop, const char *fmt, va_list ap)\n{\n\tint len;\n\n\tif (iop->_flag & _IONBF) {\n\t\tiop->_flag &= ~_IONBF;\n\t\tiop->_ptr = iop->_base = alloca(BUFSIZ);\n\t\tlen = _doprnt(fmt, ap, iop);\n\t\t(void) fflush(iop);\n\t\tiop->_flag |= _IONBF;\n\t\tiop->_base = NULL;\n\t\tiop->_bufsiz = 0;\n\t\tiop->_cnt = 0;\n\t} else\n\t\tlen = _doprnt(fmt, ap, iop);\n\n\treturn (ferror(iop) ? EOF : len);\n}\n"
  },
  {
    "path": "lib/libc/stdio/vprintf.c",
    "content": "/*\n * Copyright (c) 1988 Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that the above copyright notice and this paragraph are\n * duplicated in all such forms and that any documentation,\n * advertising materials, and other materials related to such\n * distribution and use acknowledge that the software was developed\n * by the University of California, Berkeley.  The name of the\n * University may not be used to endorse or promote products derived\n * from this software without specific prior written permission.\n * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n */\n#include <stdio.h>\n#include <stdarg.h>\n\nint\nvprintf(const char *fmt, va_list ap)\n{\n\tint len;\n\n\tlen = _doprnt(fmt, ap, stdout);\n\treturn (ferror(stdout) ? EOF : len);\n}\n"
  },
  {
    "path": "lib/libc/stdio/vsprintf.c",
    "content": "/*\n * Copyright (c) 1988 Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that the above copyright notice and this paragraph are\n * duplicated in all such forms and that any documentation,\n * advertising materials, and other materials related to such\n * distribution and use acknowledge that the software was developed\n * by the University of California, Berkeley.  The name of the\n * University may not be used to endorse or promote products derived\n * from this software without specific prior written permission.\n * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n */\n#include <stdio.h>\n#include <stdarg.h>\n\nint\nvsprintf(char *str, const char *fmt, va_list ap)\n{\n\tFILE f;\n\n\tf._flag = _IOWRT+_IOSTRG;\n\tf._ptr = str;\n\tf._cnt = 32767;\n\t_doprnt(fmt, ap, &f);\n\t*f._ptr = 0;\n\treturn (f._ptr - str);\n}\n"
  },
  {
    "path": "lib/libc/stdlib/Makefile",
    "content": "#\n# This is the Makefile for 'stdlib'.  New routines ported from 4.4BSD's\n# libc/stdlib directory go here but existing libc/gen files are being left\n# where they are.\n#\nTOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nDEFS\t\t=\nCFLAGS\t\t+= ${DEFS} -Os\n\nSRCS\t\t= getopt.c getsubopt.c strtol.c strtoul.c strtod.c\nOBJS\t\t= getopt.o getsubopt.o strtol.o strtoul.o strtod.o\n\nall:\t\tstdlib.a\n\nstdlib.a:\t${OBJS}\n\t\t@echo \"building stdlib.a\"\n\t\t@${AR} cr stdlib.a ${OBJS}\n\nclean:\n\t\trm -f *.o *~ profiled/*.o tags Makefile.bak stdlib.a stdlib_p.s\n\ndepend:\t\t${SRCS}\n\t\tmkdep ${CFLAGS} ${SRCS}\n\ntags:\n\t\tcwd=`pwd`; \\\n\t\tfor i in ${SRCS}; do \\\n\t\t\tctags -a -f ${TAGSFILE} $$cwd/$$i; \\\n\t\tdone\n\n# DO NOT DELETE THIS LINE -- mkdep uses it.\n# DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY.\n"
  },
  {
    "path": "lib/libc/stdlib/getopt.c",
    "content": "/*\n * Copyright (c) 1987, 1993, 1994\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n\nint\topterr = 1,\t\t/* if error message should be printed */\n\toptind = 1,\t\t/* index into parent argv vector */\n\toptopt,\t\t\t/* character checked for validity */\n\toptreset;\t\t/* reset getopt */\nchar\t*optarg;\t\t/* argument associated with option */\n\n#define\tBADCH\t(int)'?'\n#define\tBADARG\t(int)':'\n#define\tEMSG\t\"\"\n\n/*\n * getopt --\n *\tParse argc/argv argument vector.\n */\nint\ngetopt(nargc, nargv, ostr)\n\tint nargc;\n\tchar * const nargv[];\n\tconst char *ostr;\n{\n\tstatic char *place = EMSG;\t\t/* option letter processing */\n\tchar *oli;\t\t\t\t/* option letter list index */\n\n\tif (optreset || !*place) {\t\t/* update scanning pointer */\n\t\toptreset = 0;\n\t\tif (optind >= nargc || *(place = nargv[optind]) != '-') {\n\t\t\tplace = EMSG;\n\t\t\treturn (EOF);\n\t\t}\n\t\tif (place[1] && *++place == '-') {\t/* found \"--\" */\n\t\t\t++optind;\n\t\t\tplace = EMSG;\n\t\t\treturn (EOF);\n\t\t}\n\t}\t\t\t\t\t/* option letter okay? */\n\tif ((optopt = (int)*place++) == (int)':' ||\n\t    !(oli = strchr(ostr, optopt))) {\n\t\t/*\n\t\t * if the user didn't specify '-' as an option,\n\t\t * assume it means EOF.\n\t\t */\n\t\tif (optopt == (int)'-')\n\t\t\treturn (EOF);\n\t\tif (!*place)\n\t\t\t++optind;\n\t\tif (opterr && *ostr != ':')\n\t\t\t(void)fprintf(stderr,\n\t\t\t    \"%s: illegal option -- %c\\n\", __progname, optopt);\n\t\treturn (BADCH);\n\t}\n\tif (*++oli != ':') {\t\t\t/* don't need argument */\n\t\toptarg = NULL;\n\t\tif (!*place)\n\t\t\t++optind;\n\t}\n\telse {\t\t\t\t\t/* need an argument */\n\t\tif (*place)\t\t\t/* no white space */\n\t\t\toptarg = place;\n\t\telse if (nargc <= ++optind) {\t/* no arg */\n\t\t\tplace = EMSG;\n\t\t\tif (*ostr == ':')\n\t\t\t\treturn (BADARG);\n\t\t\tif (opterr)\n\t\t\t\t(void)fprintf(stderr,\n\t\t\t\t    \"%s: option requires an argument -- %c\\n\",\n\t\t\t\t    __progname, optopt);\n\t\t\treturn (BADCH);\n\t\t}\n\t \telse\t\t\t\t/* white space */\n\t\t\toptarg = nargv[optind];\n\t\tplace = EMSG;\n\t\t++optind;\n\t}\n\treturn (optopt);\t\t\t/* dump back option letter */\n}\n"
  },
  {
    "path": "lib/libc/stdlib/getsubopt.c",
    "content": "/*-\n * Copyright (c) 1990, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <stdlib.h>\n#include <string.h>\n\n/*\n * The SVID interface to getsubopt provides no way of figuring out which\n * part of the suboptions list wasn't matched.  This makes error messages\n * tricky...  The extern variable suboptarg is a pointer to the token\n * which didn't match.\n */\nchar *suboptarg;\n\nint\ngetsubopt(optionp, tokens, valuep)\n\tregister char **optionp;\n\tregister char **valuep;\n\tregister char **tokens;\n{\n\tregister int cnt;\n\tregister char *p;\n\n\tsuboptarg = *valuep = NULL;\n\n\tif (!optionp || !*optionp)\n\t\treturn(-1);\n\n\t/* skip leading white-space, commas */\n\tfor (p = *optionp; *p && (*p == ',' || *p == ' ' || *p == '\\t'); ++p);\n\n\tif (!*p) {\n\t\t*optionp = p;\n\t\treturn(-1);\n\t}\n\n\t/* save the start of the token, and skip the rest of the token. */\n\tfor (suboptarg = p;\n\t    *++p && *p != ',' && *p != '=' && *p != ' ' && *p != '\\t';);\n\n\tif (*p) {\n\t\t/*\n\t\t * If there's an equals sign, set the value pointer, and\n\t\t * skip over the value part of the token.  Terminate the\n\t\t * token.\n\t\t */\n\t\tif (*p == '=') {\n\t\t\t*p = '\\0';\n\t\t\tfor (*valuep = ++p;\n\t\t\t    *p && *p != ',' && *p != ' ' && *p != '\\t'; ++p);\n\t\t\tif (*p)\n\t\t\t\t*p++ = '\\0';\n\t\t} else\n\t\t\t*p++ = '\\0';\n\t\t/* Skip any whitespace or commas after this token. */\n\t\tfor (; *p && (*p == ',' || *p == ' ' || *p == '\\t'); ++p);\n\t}\n\n\t/* set optionp for next round. */\n\t*optionp = p;\n\n\tfor (cnt = 0; *tokens; ++tokens, ++cnt)\n\t\tif (!strcmp(suboptarg, *tokens))\n\t\t\treturn(cnt);\n\treturn(-1);\n}\n"
  },
  {
    "path": "lib/libc/stdlib/strtod.c",
    "content": "/*\n * double strtodx (char *string, char **endPtr, int radix)\n *\tThis procedure converts a floating-point number from an ASCII\n *\tdecimal representation to internal double-precision format.\n *\n * Original sources taken from 386bsd and modified for variable radix\n * by Serge Vakulenko, <vak@kiae.su>.\n *\n * Arguments:\n * string\n *      A decimal ASCII floating-point number, optionally preceded\n *      by white space. Must have form \"-I.FE-X\", where I is the integer\n *      part of the mantissa, F is the fractional part of the mantissa,\n *      and X is the exponent.  Either of the signs may be \"+\", \"-\", or\n *      omitted.  Either I or F may be omitted, or both.  The decimal point\n *      isn't necessary unless F is present. The \"E\" may actually be an \"e\",\n *      or \"E\", \"S\", \"s\", \"F\", \"f\", \"D\", \"d\", \"L\", \"l\".\n *      E and X may both be omitted (but not just one).\n *\n * endPtr\n *      If non-NULL, store terminating character's address here.\n *\n * radix\n *      Radix of floating point, one of 2, 8, 10, 16.\n *\n * The return value is the double-precision floating-point\n * representation of the characters in string.  If endPtr isn't\n * NULL, then *endPtr is filled in with the address of the\n * next character after the last one that was part of the\n * floating-point number.\n */\n#include <stdlib.h>\n#include <ctype.h>\n\ndouble strtod (const char *string, char **endPtr)\n{\n\tint sign = 0, expSign = 0, i;\n\tdouble fraction, dblExp;\n\tregister const char *p;\n\tregister char c;\n\n\t/* Exponent read from \"EX\" field. */\n\tint exp = 0;\n\n\t/* Exponent that derives from the fractional part.  Under normal\n\t * circumstances, it is the negative of the number of digits in F.\n\t * However, if I is very long, the last digits of I get dropped\n\t * (otherwise a long I with a large negative exponent could cause an\n\t * unnecessary overflow on I alone).  In this case, fracExp is\n\t * incremented one for each dropped digit. */\n\tint fracExp = 0;\n\n\t/* Number of digits in mantissa. */\n\tint mantSize;\n\n\t/* Number of mantissa digits BEFORE decimal point. */\n\tint decPt;\n\n\t/* Temporarily holds location of exponent in string. */\n\tconst char *pExp;\n\n\t/* Largest possible base 10 exponent.\n\t * Any exponent larger than this will already\n\t * produce underflow or overflow, so there's\n\t * no need to worry about additional digits. */\n\tstatic int maxExponent = 307;\n\n\t/* Table giving binary powers of 10.\n\t * Entry is 10^2^i.  Used to convert decimal\n\t * exponents into floating-point numbers. */\n\tstatic double powersOf10[] = {\n\t\t1e1, 1e2, 1e4, 1e8, 1e16, 1e32, /*1e64, 1e128, 1e256,*/\n\t};\n#if 0\n\tstatic double powersOf2[] = {\n\t\t2, 4, 16, 256, 65536, 4.294967296e9, 1.8446744073709551616e19,\n                /*3.4028236692093846346e38, 1.1579208923731619542e77, 1.3407807929942597099e154,*/\n\t};\n\tstatic double powersOf8[] = {\n\t\t8, 64, 4096, 2.81474976710656e14, 7.9228162514264337593e28,\n                /*6.2771017353866807638e57, 3.9402006196394479212e115, 1.5525180923007089351e231,*/\n\t};\n\tstatic double powersOf16[] = {\n\t\t16, 256, 65536, 1.8446744073709551616e19,\n                /*3.4028236692093846346e38, 1.1579208923731619542e77, 1.3407807929942597099e154,*/\n\t};\n#endif\n\t/*\n\t * Strip off leading blanks and check for a sign.\n\t */\n\tp = string;\n\twhile (*p==' ' || *p=='\\t')\n\t\t++p;\n\tif (*p == '-') {\n\t\tsign = 1;\n\t\t++p;\n\t} else if (*p == '+')\n\t\t++p;\n\n\t/*\n\t * Count the number of digits in the mantissa (including the decimal\n\t * point), and also locate the decimal point.\n\t */\n\tdecPt = -1;\n\tfor (mantSize=0; ; ++mantSize) {\n\t\tc = *p;\n\t\tif (! isdigit (c)) {\n\t\t\tif (c != '.' || decPt >= 0)\n\t\t\t\tbreak;\n\t\t\tdecPt = mantSize;\n\t\t}\n\t\t++p;\n\t}\n\n\t/*\n\t * Now suck up the digits in the mantissa.  Use two integers to\n\t * collect 9 digits each (this is faster than using floating-point).\n\t * If the mantissa has more than 18 digits, ignore the extras, since\n\t * they can't affect the value anyway.\n\t */\n\tpExp = p;\n\tp -= mantSize;\n\tif (decPt < 0)\n\t\tdecPt = mantSize;\n\telse\n\t\t--mantSize;             /* One of the digits was the point. */\n\n\tif (mantSize > 2 * 9)\n\t\tmantSize = 2 * 9;\n\tfracExp = decPt - mantSize;\n\tif (mantSize == 0) {\n\t\tfraction = 0.0;\n\t\tp = string;\n\t\tgoto done;\n\t} else {\n\t\tint frac1, frac2;\n\n\t\tfor (frac1=0; mantSize>9; --mantSize) {\n\t\t\tc = *p++;\n\t\t\tif (c == '.')\n\t\t\t\tc = *p++;\n\t\t\tfrac1 = frac1 * 10 + (c - '0');\n\t\t}\n\t\tfor (frac2=0; mantSize>0; --mantSize) {\n\t\t\tc = *p++;\n\t\t\tif (c == '.')\n\t\t\t\tc = *p++;\n\t\t\tfrac2 = frac2 * 10 + (c - '0');\n\t\t}\n\t\tfraction = (double) 1000000000 * frac1 + frac2;\n\t}\n\n\t/*\n\t * Skim off the exponent.\n\t */\n\tp = pExp;\n\tif (*p=='E' || *p=='e' || *p=='S' || *p=='s' || *p=='F' || *p=='f' ||\n\t     *p=='D' || *p=='d' || *p=='L' || *p=='l') {\n\t\t++p;\n\t\tif (*p == '-') {\n\t\t\texpSign = 1;\n\t\t\t++p;\n\t\t} else if (*p == '+')\n\t\t\t++p;\n\t\twhile (isdigit (*p))\n\t\t\texp = exp * 10 + (*p++ - '0');\n\t}\n\tif (expSign)\n\t\texp = fracExp - exp;\n\telse\n\t\texp = fracExp + exp;\n\n\t/*\n\t * Generate a floating-point number that represents the exponent.\n\t * Do this by processing the exponent one bit at a time to combine\n\t * many powers of 2 of 10. Then combine the exponent with the\n\t * fraction.\n\t */\n\tif (exp < 0) {\n\t\texpSign = 1;\n\t\texp = -exp;\n\t} else\n\t\texpSign = 0;\n\tif (exp > maxExponent)\n\t\texp = maxExponent;\n\tdblExp = 1.0;\n\tfor (i=0; exp; exp>>=1, ++i)\n\t\tif (exp & 01)\n\t\t\tdblExp *= powersOf10[i];\n\tif (expSign)\n\t\tfraction /= dblExp;\n\telse\n\t\tfraction *= dblExp;\n\ndone:\n\tif (endPtr)\n\t\t*endPtr = (char*) p;\n\n\treturn sign ? -fraction : fraction;\n}\n"
  },
  {
    "path": "lib/libc/stdlib/strtol.c",
    "content": "/*-\n * Copyright (c) 1990, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <limits.h>\n#include <ctype.h>\n#include <errno.h>\n#include <stdlib.h>\n\n/*\n * Convert a string to a long integer.\n *\n * Ignores `locale' stuff.  Assumes that the upper and lower case\n * alphabets and digits are each contiguous.\n */\nlong\nstrtol(nptr, endptr, base)\n\tconst char *nptr;\n\tchar **endptr;\n\tregister int base;\n{\n\tregister const char *s = nptr;\n\tregister unsigned long acc;\n\tregister int c;\n\tregister unsigned long cutoff;\n\tregister int neg = 0, any, cutlim;\n\n\t/*\n\t * Skip white space and pick up leading +/- sign if any.\n\t * If base is 0, allow 0x for hex and 0 for octal, else\n\t * assume decimal; if base is already 16, allow 0x.\n\t */\n\tdo {\n\t\tc = *s++;\n\t} while (isspace(c));\n\tif (c == '-') {\n\t\tneg = 1;\n\t\tc = *s++;\n\t} else if (c == '+')\n\t\tc = *s++;\n\tif ((base == 0 || base == 16) &&\n\t    c == '0' && (*s == 'x' || *s == 'X')) {\n\t\tc = s[1];\n\t\ts += 2;\n\t\tbase = 16;\n\t}\n\tif (base == 0)\n\t\tbase = c == '0' ? 8 : 10;\n\n\t/*\n\t * Compute the cutoff value between legal numbers and illegal\n\t * numbers.  That is the largest legal value, divided by the\n\t * base.  An input number that is greater than this value, if\n\t * followed by a legal input character, is too big.  One that\n\t * is equal to this value may be valid or not; the limit\n\t * between valid and invalid numbers is then based on the last\n\t * digit.  For instance, if the range for longs is\n\t * [-2147483648..2147483647] and the input base is 10,\n\t * cutoff will be set to 214748364 and cutlim to either\n\t * 7 (neg==0) or 8 (neg==1), meaning that if we have accumulated\n\t * a value > 214748364, or equal but the next digit is > 7 (or 8),\n\t * the number is too big, and we will return a range error.\n\t *\n\t * Set any if any `digits' consumed; make it negative to indicate\n\t * overflow.\n\t */\n\tcutoff = neg ? -(unsigned long)LONG_MIN : LONG_MAX;\n\tcutlim = cutoff % (unsigned long)base;\n\tcutoff /= (unsigned long)base;\n\tfor (acc = 0, any = 0;; c = *s++) {\n\t\tif (isdigit(c))\n\t\t\tc -= '0';\n\t\telse if (isalpha(c))\n\t\t\tc -= isupper(c) ? 'A' - 10 : 'a' - 10;\n\t\telse\n\t\t\tbreak;\n\t\tif (c >= base)\n\t\t\tbreak;\n\t\tif (any < 0 || acc > cutoff || (acc == cutoff && c > cutlim))\n\t\t\tany = -1;\n\t\telse {\n\t\t\tany = 1;\n\t\t\tacc *= base;\n\t\t\tacc += c;\n\t\t}\n\t}\n\tif (any < 0) {\n\t\tacc = neg ? LONG_MIN : LONG_MAX;\n\t\terrno = ERANGE;\n\t} else if (neg)\n\t\tacc = -acc;\n\tif (endptr != 0)\n\t\t*endptr = (char *)(any ? s - 1 : nptr);\n\treturn (acc);\n}\n"
  },
  {
    "path": "lib/libc/stdlib/strtoul.c",
    "content": "/*\n * Copyright (c) 1990, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <limits.h>\n#include <ctype.h>\n#include <errno.h>\n#include <stdlib.h>\n\n/*\n * Convert a string to an unsigned long integer.\n *\n * Ignores `locale' stuff.  Assumes that the upper and lower case\n * alphabets and digits are each contiguous.\n */\nunsigned long\nstrtoul(nptr, endptr, base)\n\tconst char *nptr;\n\tchar **endptr;\n\tregister int base;\n{\n\tregister const char *s = nptr;\n\tregister unsigned long acc;\n\tregister int c;\n\tregister unsigned long cutoff;\n\tregister int neg = 0, any, cutlim;\n\n\t/*\n\t * See strtol for comments as to the logic used.\n\t */\n\tdo {\n\t\tc = *s++;\n\t} while (isspace(c));\n\tif (c == '-') {\n\t\tneg = 1;\n\t\tc = *s++;\n\t} else if (c == '+')\n\t\tc = *s++;\n\tif ((base == 0 || base == 16) &&\n\t    c == '0' && (*s == 'x' || *s == 'X')) {\n\t\tc = s[1];\n\t\ts += 2;\n\t\tbase = 16;\n\t}\n\tif (base == 0)\n\t\tbase = c == '0' ? 8 : 10;\n\tcutoff = (unsigned long)ULONG_MAX / (unsigned long)base;\n\tcutlim = (unsigned long)ULONG_MAX % (unsigned long)base;\n\tfor (acc = 0, any = 0;; c = *s++) {\n\t\tif (isdigit(c))\n\t\t\tc -= '0';\n\t\telse if (isalpha(c))\n\t\t\tc -= isupper(c) ? 'A' - 10 : 'a' - 10;\n\t\telse\n\t\t\tbreak;\n\t\tif (c >= base)\n\t\t\tbreak;\n\t\tif (any < 0 || acc > cutoff || (acc == cutoff && c > cutlim))\n\t\t\tany = -1;\n\t\telse {\n\t\t\tany = 1;\n\t\t\tacc *= base;\n\t\t\tacc += c;\n\t\t}\n\t}\n\tif (any < 0) {\n\t\tacc = ULONG_MAX;\n\t\terrno = ERANGE;\n\t} else if (neg)\n\t\tacc = -acc;\n\tif (endptr != 0)\n\t\t*endptr = (char *)(any ? s - 1 : nptr);\n\treturn (acc);\n}\n"
  },
  {
    "path": "lib/libc/string/Makefile",
    "content": "#\n# This is the Makefile for the 'string' functions.  New routines ported from\n# 4.4BSD's libc/string directory go here but existing libc/gen files are\n# being left where they are.\n#\nTOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nDEFS\t\t=\nCFLAGS\t\t+= ${DEFS} -Os\n\nSRCS=\t\tstrcspn.c strerror.c strlcat.c strlcpy.c strpbrk.c \\\n\t\tstrsep.c strspn.c strstr.c strtok.c strtok_r.c\n\nOBJS=\t\tstrcspn.o strerror.o strlcat.o strlcpy.o strpbrk.o \\\n\t\tstrsep.o strspn.o strstr.o strtok.o strtok_r.o\n\nall:\t\tstring.a\n\nstring.a:\t${OBJS}\n\t\t@echo \"building normal string.a\"\n\t\t@${AR} cr string.a ${OBJS}\n\nclean:\n\t\trm -f *.o *~ profiled/*.o tags Makefile.bak string.a string_p.a\n\ndepend:\t\t${SRCS}\n\t\tmkdep ${CFLAGS} ${SRCS}\n\ntags:\n\t\tcwd=`pwd`; \\\n\t\tfor i in ${SRCS}; do \\\n\t\t\tctags -a -f ${TAGSFILE} $$cwd/$$i; \\\n\t\tdone\n\n# DO NOT DELETE THIS LINE -- mkdep uses it.\n# DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY.\n"
  },
  {
    "path": "lib/libc/string/strcspn.c",
    "content": "/*-\n * Copyright (c) 1990, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Chris Torek.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/types.h>\n#include <string.h>\n\n/*\n * Span the complement of string s2.\n */\nsize_t\nstrcspn (s1, s2)\n\tconst char *s1;\n\tconst char *s2;\n{\n\tregister const char *p, *spanp;\n\tregister char c, sc;\n\n\t/*\n\t * Stop as soon as we find any character from s2.  Note that there\n\t * must be a NUL in s2; it suffices to stop when we find that, too.\n\t */\n\tfor (p = s1;;) {\n\t\tc = *p++;\n\t\tspanp = s2;\n\t\tdo {\n\t\t\tif ((sc = *spanp++) == c)\n\t\t\t\treturn (p - 1 - s1);\n\t\t} while (sc != 0);\n\t}\n\t/* NOTREACHED */\n}\n"
  },
  {
    "path": "lib/libc/string/strerror.c",
    "content": "/*\n * Copyright (c) 1988, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <string.h>\n#include <sys/sysctl.h>\n#include <machine/cpu.h>\n\nchar *\nstrerror(errnum)\n\tregister int errnum;\n{\n        static char msgstr[64];\n\tint mib[3];\n\tsize_t size;\n\n        /* Read an error message from kernel to a static buffer. */\n\tmib[0] = CTL_MACHDEP;\n\tmib[1] = CPU_ERRMSG;\n\tmib[2] = errnum;\n\tsize = sizeof (msgstr);\n\tif (sysctl(mib, 3, msgstr, &size, NULL, 0) == -1) {\n                /* Do this by hand, so we don't include stdio(3). */\n                static const char unknown[] = \"Unknown error: \";\n                register char *p, *t;\n                const char *q;\n                char tmp[20];\n\n                t = tmp;\n                do {\n                        *t++ = '0' + ((unsigned)errnum % 10);\n                        errnum = (unsigned)errnum / 10;\n                } while (errnum != 0);\n\n                p = msgstr;\n                for (q=unknown; *q; q++) {\n                        *p++ = *q;\n                }\n                do {\n                        *p++ = *--t;\n                } while (t > tmp);\n                *p = 0;\n        }\n\treturn msgstr;\n}\n"
  },
  {
    "path": "lib/libc/string/strlcat.c",
    "content": "/*\t$OpenBSD: strlcat.c,v 1.19 2019/01/25 00:19:25 millert Exp $\t*/\n\n/*\n * Copyright (c) 1998, 2015 Todd C. Miller <millert@openbsd.org>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include <sys/types.h>\n#include <string.h>\n\n/*\n * Appends src to string dst of size dsize (unlike strncat, dsize is the\n * full size of dst, not space left).  At most dsize-1 characters\n * will be copied.  Always NUL terminates (unless dsize <= strlen(dst)).\n * Returns strlen(src) + MIN(dsize, strlen(initial dst)).\n * If retval >= dsize, truncation occurred.\n */\nsize_t\nstrlcat(char *dst, const char *src, size_t dsize)\n{\n\tconst char *odst = dst;\n\tconst char *osrc = src;\n\tsize_t n = dsize;\n\tsize_t dlen;\n\n\t/* Find the end of dst and adjust bytes left but don't go past end. */\n\twhile (n-- != 0 && *dst != '\\0')\n\t\tdst++;\n\tdlen = dst - odst;\n\tn = dsize - dlen;\n\n\tif (n-- == 0)\n\t\treturn(dlen + strlen(src));\n\twhile (*src != '\\0') {\n\t\tif (n != 0) {\n\t\t\t*dst++ = *src;\n\t\t\tn--;\n\t\t}\n\t\tsrc++;\n\t}\n\t*dst = '\\0';\n\n\treturn(dlen + (src - osrc));\t/* count does not include NUL */\n}\n"
  },
  {
    "path": "lib/libc/string/strlcpy.c",
    "content": "/*\t$OpenBSD: strlcpy.c,v 1.16 2019/01/25 00:19:25 millert Exp $\t*/\n\n/*\n * Copyright (c) 1998, 2015 Todd C. Miller <millert@openbsd.org>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include <sys/types.h>\n#include <string.h>\n\n/*\n * Copy string src to buffer dst of size dsize.  At most dsize-1\n * chars will be copied.  Always NUL terminates (unless dsize == 0).\n * Returns strlen(src); if retval >= dsize, truncation occurred.\n */\nsize_t\nstrlcpy(char *dst, const char *src, size_t dsize)\n{\n\tconst char *osrc = src;\n\tsize_t nleft = dsize;\n\n\t/* Copy as many bytes as will fit. */\n\tif (nleft != 0) {\n\t\twhile (--nleft != 0) {\n\t\t\tif ((*dst++ = *src++) == '\\0')\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* Not enough room in dst, add NUL and traverse rest of src. */\n\tif (nleft == 0) {\n\t\tif (dsize != 0)\n\t\t\t*dst = '\\0';\t\t/* NUL-terminate dst */\n\t\twhile (*src++)\n\t\t\t;\n\t}\n\n\treturn(src - osrc - 1);\t/* count does not include NUL */\n}\n"
  },
  {
    "path": "lib/libc/string/strpbrk.c",
    "content": "/*\n * Copyright (c) 1985, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/types.h>\n#include <string.h>\n#include <stdio.h>\t/* for NULL */\n\n/*\n * Find the first occurrence in s1 of a character in s2 (excluding NUL).\n */\nchar *\nstrpbrk(s1, s2)\n\tregister const char *s1;\n\tconst char *s2;\n{\n\tregister const char *scanp;\n\tregister int c;\n\tint\tsc;\n\n\twhile ((c = *s1++) != 0) {\n\t\tfor (scanp = s2; (sc = *scanp++) != 0;)\n\t\t\tif (sc == c)\n\t\t\t\treturn ((char *)(s1 - 1));\n\t}\n\treturn (NULL);\n}\n"
  },
  {
    "path": "lib/libc/string/strsep.c",
    "content": "/*-\n * Copyright (c) 1990, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/types.h>\n#include <string.h>\n#include <stdio.h>\n\n/*\n * Get next token from string *stringp, where tokens are possibly-empty\n * strings separated by characters from delim.\n *\n * Writes NULs into the string at *stringp to end tokens.\n * delim need not remain constant from call to call.\n * On return, *stringp points past the last NUL written (if there might\n * be further tokens), or is NULL (if there are definitely no more tokens).\n *\n * If *stringp is NULL, strsep returns NULL.\n */\nchar *\nstrsep(stringp, delim)\n\tregister char **stringp;\n\tconst char *delim;\n{\n\tregister char *s;\n\tregister const char *spanp;\n\tint c, sc;\n\tchar *tok;\n\n\tif ((s = *stringp) == NULL)\n\t\treturn (NULL);\n\tfor (tok = s;;) {\n\t\tc = *s++;\n\t\tspanp = delim;\n\t\tdo {\n\t\t\tif ((sc = *spanp++) == c) {\n\t\t\t\tif (c == 0)\n\t\t\t\t\ts = NULL;\n\t\t\t\telse\n\t\t\t\t\ts[-1] = 0;\n\t\t\t\t*stringp = s;\n\t\t\t\treturn (tok);\n\t\t\t}\n\t\t} while (sc != 0);\n\t}\n\t/* NOTREACHED */\n}\n"
  },
  {
    "path": "lib/libc/string/strspn.c",
    "content": "/*\n * Copyright (c) 1989, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/types.h>\n#include <string.h>\n\n/*\n * Span the string s2 (skip characters that are in s2).\n */\nsize_t\nstrspn(s1, s2)\n\tconst char *s1;\n\tconst char *s2;\n{\n\tregister const char *p = s1, *spanp;\n\tregister char c, sc;\n\n\t/*\n\t * Skip any characters in s2, excluding the terminating \\0.\n\t */\ncont:\n\tc = *p++;\n\tfor (spanp = s2; (sc = *spanp++) != 0;)\n\t\tif (sc == c)\n\t\t\tgoto cont;\n\treturn (p - 1 - s1);\n}\n"
  },
  {
    "path": "lib/libc/string/strstr.c",
    "content": "/*-\n * Copyright (c) 1990, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Chris Torek.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <string.h>\n\n/*\n * Find the first occurrence of find in s.\n */\nchar *\nstrstr(s, find)\n\tregister const char *s, *find;\n{\n\tregister char c;\n\tchar\tsc;\n\tsize_t\tlen;\n\n\tif ((c = *find++) != 0) {\n\t\tlen = strlen(find);\n\t\tdo {\n\t\t\tdo {\n\t\t\t\tif ((sc = *s++) == 0)\n\t\t\t\t\treturn (NULL);\n\t\t\t} while (sc != c);\n\t\t} while (strncmp(s, find, len) != 0);\n\t\ts--;\n\t}\n\treturn ((char *)s);\n}\n"
  },
  {
    "path": "lib/libc/string/strtok.c",
    "content": "/*\n * Copyright (c) 1988, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <string.h>\n#include <stdio.h>\n\nchar *\nstrtok(s, delim)\n\tregister char *s;\n\tregister const char *delim;\n{\n\tregister char *spanp;\n\tint c, sc;\n\tchar *tok;\n\tstatic char *last;\n\n\n\tif (s == NULL && (s = last) == NULL)\n\t\treturn (NULL);\n\n\t/*\n\t * Skip (span) leading delimiters (s += strspn(s, delim), sort of).\n\t */\ncont:\n\tc = *s++;\n\tfor (spanp = (char *)delim; (sc = *spanp++) != 0;) {\n\t\tif (c == sc)\n\t\t\tgoto cont;\n\t}\n\n\tif (c == 0) {\t\t/* no non-delimiter characters */\n\t\tlast = NULL;\n\t\treturn (NULL);\n\t}\n\ttok = s - 1;\n\n\t/*\n\t * Scan token (scan for delimiters: s += strcspn(s, delim), sort of).\n\t * Note that delim must have one NUL; we stop if we see that, too.\n\t */\n\tfor (;;) {\n\t\tc = *s++;\n\t\tspanp = (char *)delim;\n\t\tdo {\n\t\t\tif ((sc = *spanp++) == c) {\n\t\t\t\tif (c == 0)\n\t\t\t\t\ts = NULL;\n\t\t\t\telse\n\t\t\t\t\ts[-1] = 0;\n\t\t\t\tlast = s;\n\t\t\t\treturn (tok);\n\t\t\t}\n\t\t} while (sc != 0);\n\t}\n\t/* NOTREACHED */\n}\n"
  },
  {
    "path": "lib/libc/string/strtok_r.c",
    "content": "/*\n * Copyright (c) 1988, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <string.h>\n#include <stdio.h>\n\nchar *strtok_r(char *s, const char *delim, char **last)\n{\n        char *spanp, *tok;\n        int c, sc;\n\n        if (s == NULL && (s = *last) == NULL)\n                return (NULL);\n\n        /*\n         * Skip (span) leading delimiters (s += strspn(s, delim), sort of).\n         */\ncont:\n        c = *s++;\n        for (spanp = (char *)delim; (sc = *spanp++) != 0;) {\n                if (c == sc)\n                        goto cont;\n        }\n\n        if (c == 0) {           /* no non-delimiter characters */\n                *last = NULL;\n                return (NULL);\n        }\n        tok = s - 1;\n\n        /*\n         * Scan token (scan for delimiters: s += strcspn(s, delim), sort of).\n         * Note that delim must have one NUL; we stop if we see that, too.\n         */\n        for (;;) {\n                c = *s++;\n                spanp = (char *)delim;\n                do {\n                        if ((sc = *spanp++) == c) {\n                                if (c == 0)\n                                        s = NULL;\n                                else\n                                        s[-1] = '\\0';\n                                *last = s;\n                                return (tok);\n                        }\n                } while (sc != 0);\n        }\n        /* NOTREACHED */\n}\n\n"
  },
  {
    "path": "lib/libc_aout/Makefile",
    "content": "#\n# libc_aout - a.out libraries, built with a.out utilities\n#\n\nSUBDIR=\tstartup libc libm libcurses libtermlib \\\n\tlibreadline libgpanel libwiznet\n\nall install:\n\t-for dir in ${SUBDIR}; do \\\n\t\t${MAKE} -C $$dir ${MFLAGS} $@; \\\n\tdone\n\nclean:\n\trm -f *~ *.o *.a\n\tfor dir in ${SUBDIR}; do \\\n\t\t${MAKE} -C $$dir ${MFLAGS} clean; \\\n\tdone\n"
  },
  {
    "path": "lib/libc_aout/libc/Makefile",
    "content": "TOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\n# Favor assembler source files over their C source equivalent.\n.SUFFIXES:\n.SUFFIXES: .o .S .c\n\nLIBCDIR          = $(TOPSRC)/lib/libc\n\n.PATH:\t${LIBCDIR}/${MACHINE_ARCH}/sys ${LIBCDIR}/${MACHINE_ARCH}/string \\\n\t${LIBCDIR}/${MACHINE_ARCH}/gen ${LIBCDIR}/gen ${LIBCDIR}/stdio \\\n\t${LIBCDIR}/stdlib ${LIBCDIR}/string ${LIBCDIR}/inet \\\n\t${LIBCDIR}/compat ${LIBCDIR}/runtime\n\nVPATH=\t${LIBCDIR}/${MACHINE_ARCH}/sys ${LIBCDIR}/${MACHINE_ARCH}/string \\\n\t${LIBCDIR}/${MACHINE_ARCH}/gen ${LIBCDIR}/gen ${LIBCDIR}/stdio \\\n\t${LIBCDIR}/stdlib ${LIBCDIR}/string ${LIBCDIR}/inet \\\n\t${LIBCDIR}/compat ${LIBCDIR}/runtime\n\nCOPTS!=if [ x\"${MACHINE_ARCH}\" = x\"mips\" ] ; then \\\n\t\techo \"-Wa,-x -B${TOOLBINDIR}/\" ; \\\n\telse \\\n\t\techo \"\" ; \\\n\tfi\n\nASOPTS!=if [ x\"${MACHINE_ARCH}\" = x\"mips\" ] ; then \\\n\t\techo \"-Wa,-x -B${TOOLBINDIR}/ -DLWHI=lwr -DLWLO=lwl -DSWHI=swr -DSWLO=swl\" ; \\\n\telse \\\n\t\techo \"\" ; \\\n\tfi\n\nDEFS\t\t= -Wall -ffreestanding\nCFLAGS\t\t= ${DEFS} -Os -Wno-attributes -Wno-attribute-alias ${COPTS}\nASFLAGS\t\t= ${DEFS} -I${LIBCDIR}/${MACHINE_ARCH}/sys ${ASOPTS}\n\n# modules which can not use SYSCALL and must be assembled from sources.  The\n# rest of the system calls are generated with printf(1) and do not have\n# source files associated with them.\n\n# libc/$(MACHINE_ARCH)/sys\nSYSOBJS\t\t= __sysctl.o accept.o access.o adjtime.o bind.o chdir.o \\\n\t\t  chflags.o chmod.o chown.o chroot.o close.o connect.o dup.o \\\n\t\t  dup2.o execve.o fchdir.o fchflags.o fchmod.o fchown.o \\\n\t\t  fcntl.o flock.o fork.o fstat.o fsync.o ftruncate.o \\\n\t\t  getdtablesize.o getgroups.o getitimer.o getsockname.o \\\n\t\t  getpeername.o getpriority.o getrlimit.o getrusage.o \\\n                  getsockopt.o gettimeofday.o ioctl.o kill.o killpg.o link.o \\\n                  listen.o lstat.o mkdir.o mknod.o mount.o open.o pselect.o \\\n                  quota.o read.o readlink.o readv.o reboot.o recv.o \\\n                  recvfrom.o recvmsg.o rename.o rmdir.o select.o send.o \\\n                  sendmsg.o sendto.o setgroups.o setitimer.o setpgrp.o \\\n                  setpriority.o setquota.o setuid.o seteuid.o setgid.o \\\n                  setegid.o setrlimit.o setsockopt.o settimeofday.o \\\n                  shutdown.o sigaltstack.o socket.o socketpair.o stat.o \\\n                  symlink.o sigprocmask.o sigstack.o sigwait.o statfs.o \\\n                  fstatfs.o getfsstat.o truncate.o umount.o unlink.o \\\n                  utimes.o wait4.o write.o writev.o lseek.o sigsuspend.o \\\n\t\t  getgid.o getegid.o getpgrp.o getpid.o getppid.o getuid.o \\\n                  geteuid.o profil.o sigpending.o sync.o ufetch.o ustore.o \\\n                  ucall.o umask.o vfork.o vhangup.o rdglob.o wrglob.o\n\nOBJS\t\t= $(SYSOBJS) sbrk.o execl.o execle.o execv.o \\\n\t\t  _exit.o _brk.o pipe.o ptrace.o sigaction.o\n\n# libc/$(MACHINE_ARCH)/string\nOBJS            += bcopy.o bzero.o ffs.o memcpy.o memmove.o memset.o \\\n                   strlen.o bcmp.o index.o rindex.o strcmp.o\n\n# libc/$(MACHINE_ARCH)/gen\nOBJS            += _setjmp.o htonl.o htons.o\n\n# libc/gen\nOBJS            += abort.o alarm.o atof.o atoi.o atol.o basename.o \\\n                   calloc.o closedir.o crypt.o ctime.o ctype_.o \\\n                   daemon.o devname.o dirname.o ecvt.o err.o \\\n                   execvp.o fakcu.o frexp.o fstab.o gcvt.o getenv.o getgrent.o \\\n                   getgrgid.o getgrnam.o getlogin.o \\\n                   getgrouplist.o gethostname.o getpagesize.o \\\n                   getpass.o getpwent.o getloadavg.o getmntinfo.o \\\n                   getttyent.o getttynam.o getusershell.o getwd.o \\\n                   initgroups.o isatty.o isinff.o isnanf.o ldexp.o malloc.o mktemp.o \\\n                   modff.o ndbm.o nlist.o knlist.o opendir.o perror.o popen.o \\\n                   psignal.o qsort.o random.o readdir.o regex.o scandir.o \\\n                   seekdir.o setmode.o sethostname.o setenv.o siglist.o \\\n                   signal.o siginterrupt.o sigsetops.o \\\n                   sleep.o strcasecmp.o strftime.o swab.o sysctl.o syslog.o system.o \\\n                   strcat.o strncat.o strcpy.o strncpy.o strncmp.o \\\n                   telldir.o time.o timezone.o ttyname.o ttyslot.o ualarm.o usleep.o \\\n                   strdup.o uname.o wait.o wait3.o waitpid.o\n\n# libc/stdio\nOBJS            += fgetc.o fgets.o fputc.o fputs.o gets.o puts.o \\\n                   clrerr.o doscan.o exit.o fdopen.o filbuf.o findiop.o \\\n                   flsbuf.o fopen.o fprintf.o fread.o freopen.o fseek.o \\\n                   ftell.o fwrite.o getchar.o getw.o printf.o putchar.o putw.o \\\n                   rew.o scanf.o setbuf.o setbuffer.o setvbuf.o snprintf.o sprintf.o \\\n                   strout.o ungetc.o vfprintf.o vprintf.o vsprintf.o doprnt.o \\\n                   remove.o feof.o ferror.o fileno.o\n\n# libc/stdlib\nOBJS            += getopt.o getsubopt.o strtol.o strtoul.o strtod.o\n\n# libc/string\nOBJS            += strcspn.o strerror.o strlcat.o strlcpy.o strpbrk.o \\\n                   strsep.o strspn.o strstr.o strtok.o strtok_r.o\n\n# libc/inet\nOBJS            += inet_addr.o inet_network.o inet_netof.o \\\n                   inet_ntoa.o inet_lnaof.o inet_maddr.o\n\n# libc/compat\nOBJS            += creat.o ftime.o gethostid.o memccpy.o memchr.o \\\n                   memcmp.o memcpy.o memset.o nice.o pause.o rand.o \\\n                   sethostid.o setregid.o setreuid.o setrgid.o setruid.o \\\n                   sigcompat.o strchr.o strrchr.o times.o tmpnam.o \\\n                   utime.o\n\n# libc/runtime\nOBJS+=\t\taddsf3.o comparesf2.o divsf3.o fixsfsi.o fixunssfsi.o \\\n\t\tfloatsisf.o floatunsisf.o mulsf3.o negsf2.o subsf3.o \\\n\t\tadddf3.o comparedf2.o divdf3.o fixdfsi.o fixunsdfsi.o \\\n\t\tfloatsidf.o floatunsidf.o muldf3.o negdf2.o subdf3.o \\\n\t\tashldi3.o lshrdi3.o \\\n\t\tsc_case.o\n\nall:            ../libc.a\n\n../libc.a:\t${OBJS}\n\t\trm -f $@\n\t\t${AOUT_AR} rc $@ ${OBJS}\n\t\t${AOUT_RANLIB} $@\n\n${OBJS}:\tFRC\n\nFRC:\n\n$(SYSOBJS):\t$(LIBCDIR)/$(MACHINE_ARCH)/sys/SYS.h\n#\t\t@echo creating $*.o\n\t\t@printf '#include \"SYS.h\"\\nSYS($*)\\n' | $(AS) $(ASFLAGS) - -c -o $*.o\n\n# Build objects here instead of ${LIBCDIR} with BSD make.\n.OBJDIR:\t${.CURDIR}\n\ninstall:\t../libc.a\n\t\t${INSTALL} -d ${DESTDIR}/usr/lib\n\t\t${INSTALL} ../libc.a ${DESTDIR}/usr/lib/libc.a\n\t\t${AOUT_RANLIB} -t ${DESTDIR}/usr/lib/libc.a\n\nclean:\n\t\trm -f *~ *.o a.out *.a ../libc.a\n"
  },
  {
    "path": "lib/libc_aout/libcurses/Makefile",
    "content": "TOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nLIBDIR=\t\t${TOPSRC}/lib/libcurses\n\nCOPTS!=if [ x\"${MACHINE_ARCH}\" = x\"mips\" ] ; then \\\n\t\techo \"-Wa,-x -B${TOOLBINDIR}/\" ; \\\n\telse \\\n\t\techo \"\" ; \\\n\tfi\n\nCFLAGS\t\t= -Os ${DEFS} -Wall ${COPTS}\n\nOBJS\t\t= addch.o addstr.o box.o clear.o clrtobot.o clrtoeol.o cr_put.o \\\n                  cr_tty.o curses.o delch.o deleteln.o delwin.o endwin.o erase.o \\\n                  fullname.o getch.o getstr.o idlok.o id_subwins.o initscr.o insch.o \\\n                  insertln.o longname.o move.o mvprintw.o mvscanw.o mvwin.o newwin.o \\\n                  overlay.o overwrite.o printw.o putchar.o refresh.o scanw.o scroll.o \\\n                  toucholap.o standout.o touchwin.o tstp.o unctrl.o\n\nall:            ../libcurses.a\n\n%.o:\t\t${LIBDIR}/%.c\n\t\t${CC} ${DEFS} ${CFLAGS} -c $< -o $@\n\n../libcurses.a:\t${OBJS}\n\t\trm -f $@\n\t\t${AOUT_AR} rc $@ ${OBJS}\n\t\t${AOUT_RANLIB} $@\n\ninstall:\t../libcurses.a\n\t\t${INSTALL} -d ${DESTDIR}/usr/lib\n\t\t${INSTALL} ../libcurses.a ${DESTDIR}/usr/lib/libcurses.a\n\t\t${AOUT_RANLIB} -t ${DESTDIR}/usr/lib/libcurses.a\n\nclean:\n\t\trm -f *~ *.o a.out *.a ../libcurses.a\n\n\naddch.o:\t${LIBDIR}/addch.c\naddstr.o:\t${LIBDIR}/addstr.c\nbox.o:\t\t${LIBDIR}/box.c\nclear.o:\t${LIBDIR}/clear.c\nclrtobot.o:\t${LIBDIR}/clrtobot.c\nclrtoeol.o:\t${LIBDIR}/clrtoeol.c\ncr_put.o:\t${LIBDIR}/cr_put.c\ncr_tty.o:\t${LIBDIR}/cr_tty.c\ncurses.o:\t${LIBDIR}/curses.c\ndelch.o:\t${LIBDIR}/delch.c\ndeleteln.o:\t${LIBDIR}/deleteln.c\ndelwin.o:\t${LIBDIR}/delwin.c\nendwin.o:\t${LIBDIR}/endwin.c\nerase.o:\t${LIBDIR}/erase.c\nfullname.o:\t${LIBDIR}/fullname.c\ngetch.o:\t${LIBDIR}/getch.c\ngetstr.o:\t${LIBDIR}/getstr.c\nidlok.o:\t${LIBDIR}/idlok.c\nid_subwins.o:\t${LIBDIR}/id_subwins.c\ninitscr.o:\t${LIBDIR}/initscr.c\ninsch.o:\t${LIBDIR}/insch.c\ninsertln.o:\t${LIBDIR}/insertln.c\nlongname.o:\t${LIBDIR}/longname.c\nmove.o:\t\t${LIBDIR}/move.c\nmvprintw.o:\t${LIBDIR}/mvprintw.c\nmvscanw.o:\t${LIBDIR}/mvscanw.c\nmvwin.o:\t${LIBDIR}/mvwin.c\nnewwin.o:\t${LIBDIR}/newwin.c\noverlay.o:\t${LIBDIR}/overlay.c\noverwrite.o:\t${LIBDIR}/overwrite.c\nprintw.o:\t${LIBDIR}/printw.c\nputchar.o:\t${LIBDIR}/putchar.c\nrefresh.o:\t${LIBDIR}/refresh.c\nscanw.o:\t${LIBDIR}/scanw.c\nscroll.o:\t${LIBDIR}/scroll.c\ntoucholap.o:\t${LIBDIR}/toucholap.c\nstandout.o:\t${LIBDIR}/standout.c\ntouchwin.o:\t${LIBDIR}/touchwin.c\ntstp.o:\t\t${LIBDIR}/tstp.c\nunctrl.o:\t${LIBDIR}/unctrl.c\n"
  },
  {
    "path": "lib/libc_aout/libgpanel/Makefile",
    "content": "TOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nLIBDIR=\t\t${TOPSRC}/lib/libgpanel\n\nCOPTS!=if [ x\"${MACHINE_ARCH}\" = x\"mips\" ] ; then \\\n\t\techo \"-Wa,-x -B${TOOLBINDIR}/\" ; \\\n\telse \\\n\t\techo \"\" ; \\\n\tfi\n\nCFLAGS\t\t= -Os ${DEFS} -Wall ${COPTS}\n\nOBJS            = open.o clear.o pixel.o line.o rect.o fill.o fill_triangle.o \\\n                  circle.o image.o char.o text.o text_width.o\n\nall:            ../libgpanel.a\n\n%.o:\t\t${LIBDIR}/%.c\n\t\t${CC} ${DEFS} ${CFLAGS} -c $< -o $@\n\n../libgpanel.a:\t${OBJS}\n\t\trm -f $@\n\t\t${AOUT_AR} rc $@ ${OBJS}\n\t\t${AOUT_RANLIB} $@\n\ninstall:\t../libgpanel.a\n\t\t${INSTALL} -d ${DESTDIR}/usr/lib\n\t\t${INSTALL} ../libgpanel.a ${DESTDIR}/usr/lib/libgpanel.a\n\t\t${AOUT_RANLIB} -t ${DESTDIR}/usr/lib/libgpanel.a\n\nclean:\n\t\trm -f *~ *.o a.out *.a ../libgpanel.a\n\n\nopen.o:\t\t${LIBDIR}/open.c\nclear.o:\t${LIBDIR}/clear.c\npixel.o:\t${LIBDIR}/pixel.c\nline.o:\t\t${LIBDIR}/line.c\nrect.o:\t\t${LIBDIR}/rect.c\nfill.o:\t\t${LIBDIR}/fill.c\nfill_triangle.o:${LIBDIR}/fill_triangle.c\ncircle.o:\t${LIBDIR}/circle.c\nimage.o:\t${LIBDIR}/image.c\nchar.o:\t\t${LIBDIR}/char.c\ntext.o:\t\t${LIBDIR}/text.c\ntext_width.o:\t${LIBDIR}/text_width.c\n"
  },
  {
    "path": "lib/libc_aout/libm/Makefile",
    "content": "TOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nLIBDIR=\t\t${TOPSRC}/lib/libm\n\nCOPTS!=if [ x\"${MACHINE_ARCH}\" = x\"mips\" ] ; then \\\n\t\techo \"-Wa,-x -B${TOOLBINDIR}/\" ; \\\n\telse \\\n\t\techo \"\" ; \\\n\tfi\n\nCFLAGS          = -Os ${DEFS} -Wall ${COPTS}\n\nOBJS            = asin.o atan.o exp.o erf.o floor.o fmod.o hypot.o j0.o j1.o \\\n                  jn.o log.o pow.o sin.o sinh.o sqrt.o tan.o tanh.o\n\nall:            ../libm.a\n\n%.o:\t\t${LIBDIR}/%.c\n\t\t${CC} ${DEFS} ${CFLAGS} -c $< -o $@\n\n../libm.a:\t${OBJS}\n\t\trm -f $@\n\t\t${AOUT_AR} rc $@ ${OBJS}\n\t\t${AOUT_RANLIB} $@\n\ninstall:\t../libm.a\n\t\t${INSTALL} -d ${DESTDIR}/usr/lib\n\t\t${INSTALL} ../libm.a ${DESTDIR}/usr/lib/libm.a\n\t\t${AOUT_RANLIB} -t ${DESTDIR}/usr/lib/libm.a\n\nclean:\n\t\trm -f *~ *.o a.out *.a ../libm.a\n\n\nasin.o:\t\t${LIBDIR}/asin.c\natan.o:\t\t${LIBDIR}/atan.c\nexp.o:\t\t${LIBDIR}/exp.c\nerf.o:\t\t${LIBDIR}/erf.c\nfloor.o:\t${LIBDIR}/floor.c\nfmod.o:\t\t${LIBDIR}/fmod.c\nhypot.o:\t${LIBDIR}/hypot.c\nj0.o:\t\t${LIBDIR}/j0.c\nj1.o:\t\t${LIBDIR}/j1.c\njn.o:\t\t${LIBDIR}/jn.c\nlog.o:\t\t${LIBDIR}/log.c\npow.o:\t\t${LIBDIR}/pow.c\nsin.o:\t\t${LIBDIR}/sin.c\nsinh.o:\t\t${LIBDIR}/sinh.c\nsqrt.o:\t\t${LIBDIR}/sqrt.c\ntan.o:\t\t${LIBDIR}/tan.c\ntanh.o:\t\t${LIBDIR}/tanh.c\n"
  },
  {
    "path": "lib/libc_aout/libreadline/Makefile",
    "content": "TOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nLIBDIR=\t\t${TOPSRC}/lib/libreadline\n\nCOPTS!=if [ x\"${MACHINE_ARCH}\" = x\"mips\" ] ; then \\\n\t\techo \"-Wa,-x -B${TOOLBINDIR}/\" ; \\\n\telse \\\n\t\techo \"\" ; \\\n\tfi\n\nCFLAGS\t\t= -Os ${DEFS} -Wall ${COPTS}\n\nOBJS\t\t= readline.o\n\nall:            ../libreadline.a\n\n%.o:\t\t${LIBDIR}/%.c\n\t\t${CC} ${DEFS} ${CFLAGS} -c $< -o $@\n\n../libreadline.a: ${OBJS}\n\t\trm -f $@\n\t\t${AOUT_AR} rc $@ ${OBJS}\n\t\t${AOUT_RANLIB} $@\n\ninstall:\t../libreadline.a\n\t\t${INSTALL} -d ${DESTDIR}/usr/lib\n\t\t${INSTALL} ../libreadline.a ${DESTDIR}/usr/lib/libreadline.a\n\t\t${AOUT_RANLIB} -t ${DESTDIR}/usr/lib/libreadline.a\n\nclean:\n\t\trm -f *~ *.o a.out *.a ../libreadline.a\n\n\nreadline.o:\t${LIBDIR}/readline.c\n"
  },
  {
    "path": "lib/libc_aout/libtermlib/Makefile",
    "content": "TOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nLIBDIR=\t\t${TOPSRC}/lib/libtermlib\n\nCOPTS!=if [ x\"${MACHINE_ARCH}\" = x\"mips\" ] ; then \\\n\t\techo \"-Wa,-x -B${TOOLBINDIR}/\" ; \\\n\telse \\\n\t\techo \"\" ; \\\n\tfi\n\nCFLAGS\t\t= -Os ${DEFS} -Wall ${COPTS}\n\nOBJS\t\t= termcap.o tgoto.o tputs.o tcattr.o\n\nall:            ../libtermlib.a\n\n%.o:\t\t${LIBDIR}/%.c\n\t\t${CC} ${DEFS} ${CFLAGS} -c $< -o $@\n\n../libtermlib.a: ${OBJS}\n\t\trm -f $@\n\t\t${AOUT_AR} rc $@ ${OBJS}\n\t\t${AOUT_RANLIB} $@\n\ninstall:\t../libtermlib.a\n\t\t${INSTALL} -d ${DESTDIR}/usr/lib\n\t\t${INSTALL} ../libtermlib.a ${DESTDIR}/usr/lib/libtermlib.a\n\t\t${AOUT_RANLIB} -t ${DESTDIR}/usr/lib/libtermlib.a\n\nclean:\n\t\trm -f *~ *.o a.out *.a ../libtermlib.a\n\n\ntermcap.o:\t${LIBDIR}/termcap.c\ntgoto.o:\t${LIBDIR}/tgoto.c\ntputs.o:\t${LIBDIR}/tputs.c\ntcattr.o:\t${LIBDIR}/tcattr.c\n"
  },
  {
    "path": "lib/libc_aout/libwiznet/Makefile",
    "content": "TOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nLIBDIR=\t\t${TOPSRC}/lib/libwiznet\n\nCOPTS!=if [ x\"${MACHINE_ARCH}\" = x\"mips\" ] ; then \\\n\t\techo \"-Wa,-x -B${TOOLBINDIR}/\" ; \\\n\telse \\\n\t\techo \"\" ; \\\n\tfi\n\nCFLAGS\t\t= -Os ${DEFS} -Wall ${COPTS}\n\nOBJS\t\t= w5100.o socket.o ethernet.o client.o server.o udp.o\n\nall:            ../libwiznet.a\n\n%.o:\t\t${LIBDIR}/%.c\n\t\t${CC} ${DEFS} ${CFLAGS} -c $< -o $@\n\n../libwiznet.a:\t${OBJS}\n\t\trm -f $@\n\t\t${AOUT_AR} rc $@ ${OBJS}\n\t\t${AOUT_RANLIB} $@\n\ninstall:\t../libwiznet.a\n\t\t${INSTALL} -d ${DESTDIR}/usr/lib\n\t\t${INSTALL} ../libwiznet.a ${DESTDIR}/usr/lib/libwiznet.a\n\t\t${AOUT_RANLIB} -t ${DESTDIR}/usr/lib/libwiznet.a\n\nclean:\n\t\trm -f *~ *.o a.out *.a ../libwiznet.a\n\n\nw5100.o:\t${LIBDIR}/w5100.c\nsocket.o:\t${LIBDIR}/socket.c\nethernet.o:\t${LIBDIR}/ethernet.c\nclient.o:\t${LIBDIR}/client.c\nserver.o:\t${LIBDIR}/server.c\nudp.o:\t\t${LIBDIR}/udp.c\n"
  },
  {
    "path": "lib/libc_aout/startup/Makefile",
    "content": "#\n# Copyright (c) 1987 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n#\tcrt0\tNormal C run time startoff\n#\nTOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCOPTS!=if [ x\"${MACHINE_ARCH}\" = x\"mips\" ] ; then \\\n\t\techo \"-Wa,-x -B${TOOLBINDIR}/\" ; \\\n\telse \\\n\t\techo \"\" ; \\\n\tfi\n\nCFLAGS=\t\t-Os ${DEFS} -Wall ${COPTS}\n\nSRCS=\t\t${TOPSRC}/lib/startup-${MACHINE_ARCH}/crt0.c\nOBJS=\t\t../crt0.o\n\nall:\t\t${OBJS}\n\n${OBJS}:\t${SRCS}\n\t\t${CC} ${DEFS} ${CFLAGS} -c ${SRCS} -o $@\n\ninstall:\t${OBJS}\n\t\t${INSTALL} -d ${DESTDIR}/usr/lib\n\t\t${INSTALL} ${OBJS} ${DESTDIR}/usr/lib/crt0.o\n\nclean:\n\t\trm -f ${OBJS} *~\n"
  },
  {
    "path": "lib/libcurses/Makefile",
    "content": "# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n# curses package\n#\nTOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFILES=\taddch.c addstr.c box.c clear.c clrtobot.c clrtoeol.c cr_put.c \\\n\tcr_tty.c curses.c delch.c deleteln.c delwin.c endwin.c erase.c \\\n\tfullname.c getch.c getstr.c idlok.c id_subwins.c initscr.c insch.c \\\n\tinsertln.c longname.c move.c mvprintw.c mvscanw.c mvwin.c newwin.c \\\n\toverlay.c overwrite.c printw.c putchar.c refresh.c scanw.c scroll.c \\\n\ttoucholap.c standout.c touchwin.c tstp.c unctrl.c\nOBJS=\taddch.o addstr.o box.o clear.o clrtobot.o clrtoeol.o cr_put.o \\\n\tcr_tty.o curses.o delch.o deleteln.o delwin.o endwin.o erase.o \\\n\tfullname.o getch.o getstr.o idlok.o id_subwins.o initscr.o insch.o \\\n\tinsertln.o longname.o move.o mvprintw.o mvscanw.o mvwin.o newwin.o \\\n\toverlay.o overwrite.o printw.o putchar.o refresh.o scanw.o scroll.o \\\n\ttoucholap.o standout.o touchwin.o tstp.o unctrl.o\nPOBJS=\t../addch.o ../addstr.o ../box.o ../clear.o ../clrtobot.o ../clrtoeol.o ../cr_put.o \\\n\t../cr_tty.o ../curses.o ../delch.o ../deleteln.o ../delwin.o ../endwin.o ../erase.o \\\n\t../fullname.o ../getch.o ../getstr.o ../idlok.o ../id_subwins.o ../initscr.o ../insch.o \\\n\t../insertln.o ../longname.o ../move.o ../mvprintw.o ../mvscanw.o ../mvwin.o ../newwin.o \\\n\t../overlay.o ../overwrite.o ../printw.o ../putchar.o ../refresh.o ../scanw.o ../scroll.o \\\n\t../toucholap.o ../standout.o ../touchwin.o ../tstp.o ../unctrl.o\n\nCTAGS=\tctags\nDEFS=\t-DNOSCCS\nCFLAGS+=-O -Wall ${DEFS}\nTAGSFILE=tags\n\nall:    ../libcurses.a\n\n../libcurses.a: ${OBJS}\n\t@echo building normal ../libcurses.a\n\t@${AR} cr ../libcurses.a ${OBJS}\n\t$(RANLIB) ../libcurses.a\n\n../libcurses_p.a: ${OBJS}\n\t@echo building profiled ../libcurses.a\n\t@cd profiled; ${AR} cr ../../libcurses_p.a ${POBJS}\n\t$(RANLIB) ../libcurses_p.a\n\ninstall: all\n#\tcp ../libcurses.a ${DESTDIR}/usr/lib/libcurses.a\n#\t$(RANLIB) ${DESTDIR}/usr/lib/libcurses.a\n#\tcp ../libcurses_p.a ${DESTDIR}/usr/lib/libcurses_p.a\n#\t$(RANLIB) ${DESTDIR}/usr/lib/libcurses_p.a\n\ntags:\n\tcwd=`pwd`; \\\n\tfor i in ${CFILES}; do \\\n\t\tctags -a -f ${TAGSFILE} $$cwd/$$i; \\\n\tdone\n\nclean:\n\trm -f ${OBJS} profiled/*.o a.out core test errs \\\n\t    ../libcurses.a ../libcurses_p.a tags\n\nctags:\n\t${CTAGS} ${CFILES} curses.h\n\nlint:\n\tlint -hxb ${CFILES} -lcurses > lint.out\n\ntest:\tlibcurses test.o\n\t${CC} ${LDFLAGS} ${CFLAGS} -o test test.o libcurses -ltermlib\n\ntest.o:\ttest.c\n\t${CC} ${CFLAGS} -c test.c\n\nar:\n\tar crv curses.ar ${CFILES} curses.h curses.ext Makefile\n"
  },
  {
    "path": "lib/libcurses/addch.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n * set_ch:\n *\tSet the first and last change flags for this window.\n */\nstatic void\nset_ch(win, y, x, ch)\n        WINDOW\t*win;\n        int\ty, x, ch;\n{\n# ifdef\tFULLDEBUG\n\tfprintf(outf, \"SET_CH(%0.2o, %d, %d)\\n\", win, y, x);\n# endif\n\tif (win->_y[y][x] != ch) {\n\t\tx += win->_ch_off;\n\t\tif (win->_firstch[y] == _NOCHANGE)\n\t\t\twin->_firstch[y] = win->_lastch[y] = x;\n\t\telse if (x < win->_firstch[y])\n\t\t\twin->_firstch[y] = x;\n\t\telse if (x > win->_lastch[y])\n\t\t\twin->_lastch[y] = x;\n# ifdef FULLDEBUG\n\t\tfprintf(outf, \"SET_CH: change gives f/l: %d/%d [%d/%d]\\n\",\n\t\t\twin->_firstch[y], win->_lastch[y],\n\t\t\twin->_firstch[y] - win->_ch_off,\n\t\t\twin->_lastch[y] - win->_ch_off);\n# endif\n\t}\n}\n\n/*\n * This routine adds the character to the current position\n */\nint waddch(win, c)\n        WINDOW\t*win;\n        char\tc;\n{\n\tint\tx, y;\n\tint\tnewx;\n\n\tx = win->_curx;\n\ty = win->_cury;\n# ifdef FULLDEBUG\n\tfprintf(outf, \"ADDCH('%c') at (%d, %d)\\n\", c, y, x);\n# endif\n\tswitch (c) {\n\t  case '\\t':\n\t\tfor (newx = x + (8 - (x & 07)); x < newx; x++)\n\t\t\tif (waddch(win, ' ') == ERR)\n\t\t\t\treturn ERR;\n\t\treturn OK;\n\n\t  default:\n# ifdef FULLDEBUG\n\t\tfprintf(outf, \"ADDCH: 1: y = %d, x = %d, firstch = %d, lastch = %d\\n\", y, x, win->_firstch[y], win->_lastch[y]);\n# endif\n\t\tif (win->_flags & _STANDOUT)\n\t\t\tc |= _STANDOUT;\n\t\tset_ch(win, y, x, c);\n\t\twin->_y[y][x++] = c;\n\t\tif (x >= win->_maxx) {\n\t\t\tx = 0;\nnewline:\n\t\t\tif (++y >= win->_maxy) {\n\t\t\t\tif (! win->_scroll)\n\t\t\t\t\treturn ERR;\n\t\t\t\tscroll(win);\n\t\t\t\t--y;\n                        }\n\t\t}\n# ifdef FULLDEBUG\n\t\tfprintf(outf, \"ADDCH: 2: y = %d, x = %d, firstch = %d, lastch = %d\\n\", y, x, win->_firstch[y], win->_lastch[y]);\n# endif\n\t\tbreak;\n\t  case '\\n':\n\t\twclrtoeol(win);\n\t\tif (!NONL)\n\t\t\tx = 0;\n\t\tgoto newline;\n\t  case '\\r':\n\t\tx = 0;\n\t\tbreak;\n\t  case '\\b':\n\t\tif (--x < 0)\n\t\t\tx = 0;\n\t\tbreak;\n\t}\n\twin->_curx = x;\n\twin->_cury = y;\n\treturn OK;\n}\n"
  },
  {
    "path": "lib/libcurses/addstr.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n * This routine adds a string starting at (_cury,_curx)\n */\nint\nwaddstr(win, str)\n        WINDOW\t*win;\n        char\t*str;\n{\n# ifdef DEBUG\n\tfprintf(outf, \"WADDSTR(\\\"%s\\\")\\n\", str);\n# endif\n\twhile (*str)\n\t\tif (waddch(win, *str++) == ERR)\n\t\t\treturn ERR;\n\treturn OK;\n}\n"
  },
  {
    "path": "lib/libcurses/box.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n *\tThis routine draws a box around the given window with \"vert\"\n * as the vertical delimiting char, and \"hor\", as the horizontal one.\n *\n */\nvoid\nbox(win, vert, hor)\n        WINDOW\t*win;\n        char\tvert, hor;\n{\n\tint\ti;\n\tint\tendy, endx;\n\tchar\t*fp, *lp;\n\n\tendx = win->_maxx;\n\tendy = win->_maxy - 1;\n\tfp = win->_y[0];\n\tlp = win->_y[endy];\n\tfor (i = 0; i < endx; i++)\n\t\tfp[i] = lp[i] = hor;\n\tendx--;\n\tfor (i = 0; i <= endy; i++)\n\t\twin->_y[i][0] = (win->_y[i][endx] = vert);\n\tif (!win->_scroll && (win->_flags&_SCROLLWIN))\n\t\tfp[0] = fp[endx] = lp[0] = lp[endx] = ' ';\n\ttouchwin(win);\n}\n"
  },
  {
    "path": "lib/libcurses/clear.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n * This routine clears the window.\n */\nint wclear(win)\n        WINDOW *win;\n{\n\twerase(win);\n\twin->_clear = TRUE;\n\treturn OK;\n}\n"
  },
  {
    "path": "lib/libcurses/clrtobot.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n * This routine erases everything on the window.\n */\nvoid\nwclrtobot(win)\n        WINDOW\t*win;\n{\n\tint\ty;\n\tchar\t*sp, *end, *maxx;\n\tint\tstartx, minx;\n\n\tstartx = win->_curx;\n\tfor (y = win->_cury; y < win->_maxy; y++) {\n\t\tminx = _NOCHANGE;\n\t\tmaxx = 0;\n\t\tend = &win->_y[y][win->_maxx];\n\t\tfor (sp = &win->_y[y][startx]; sp < end; sp++)\n\t\t\tif (*sp != ' ') {\n\t\t\t\tmaxx = sp;\n\t\t\t\tif (minx == _NOCHANGE)\n\t\t\t\t\tminx = sp - win->_y[y];\n\t\t\t\t*sp = ' ';\n\t\t\t}\n\t\tif (minx != _NOCHANGE)\n\t\t\ttouchline(win, y, minx, maxx - &win->_y[y][0]);\n\t\tstartx = 0;\n\t}\n}\n"
  },
  {
    "path": "lib/libcurses/clrtoeol.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n * This routine clears up to the end of line\n */\nvoid\nwclrtoeol(win)\n        WINDOW\t*win;\n{\n\tchar\t*sp, *end;\n\tint\ty, x;\n\tchar\t*maxx;\n\tint\tminx;\n\n\ty = win->_cury;\n\tx = win->_curx;\n\tend = &win->_y[y][win->_maxx];\n\tminx = _NOCHANGE;\n\tmaxx = &win->_y[y][x];\n\tfor (sp = maxx; sp < end; sp++)\n\t\tif (*sp != ' ') {\n\t\t\tmaxx = sp;\n\t\t\tif (minx == _NOCHANGE)\n\t\t\t\tminx = sp - win->_y[y];\n\t\t\t*sp = ' ';\n\t\t}\n\t/*\n\t * update firstch and lastch for the line\n\t */\n\ttouchline(win, y, win->_curx, win->_maxx - 1);\n# ifdef DEBUG\n\tfprintf(outf, \"CLRTOEOL: minx = %d, maxx = %d, firstch = %d, lastch = %d\\n\", minx, maxx - win->_y[y], win->_firstch[y], win->_lastch[y]);\n# endif\n}\n"
  },
  {
    "path": "lib/libcurses/cr_put.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n#include <string.h>\n\n#define HARDTABS\t8\n\n/*\n * Terminal driving and line formatting routines.\n * Basic motion optimizations are done here as well\n * as formatting of lines (printing of control characters,\n * line numbering and the like).\n */\n\n/*\n * Sync the position of the output cursor.\n * Most work here is rounding for terminal boundaries getting the\n * column position implied by wraparound or the lack thereof and\n * rolling up the screen to get destline on the screen.\n */\n\nstatic int\toutcol, outline, destcol, destline;\n\nWINDOW\t\t*_win;\n\n/*\n * Move (slowly) to destination.\n * Hard thing here is using home cursor on really deficient terminals.\n * Otherwise just use cursor motions, hacking use of tabs and overtabbing\n * and backspace.\n */\n\nstatic int plodcnt, plodflg;\n\nstatic int\nplodput(c)\n\tint\tc;\n{\n\tif (plodflg) {\n\t\tplodcnt--;\n\t\treturn 0;\n        }\n\treturn _putchar(c);\n}\n\n/*\n * Return the column number that results from being in column col and\n * hitting a tab, where tabs are set every ts columns.  Work right for\n * the case where col > COLS, even if ts does not divide COLS.\n */\nstatic int\ntabcol(col, ts)\n        int col, ts;\n{\n\tint offset;\n\n\tif (col >= COLS) {\n\t\toffset = COLS * (col / COLS);\n\t\tcol -= offset;\n\t}\n\telse\n\t\toffset = 0;\n\treturn col + ts - (col % ts) + offset;\n}\n\nstatic int\nplod(cnt)\n\tint\tcnt;\n{\n\tregister int i, j, k;\n\tregister int soutcol, soutline;\n\n\tplodcnt = plodflg = cnt;\n\tsoutcol = outcol;\n\tsoutline = outline;\n\t/*\n\t * Consider homing and moving down/right from there, vs moving\n\t * directly with local motions to the right spot.\n\t */\n\tif (HO) {\n\t\t/*\n\t\t * i is the cost to home and tab/space to the right to\n\t\t * get to the proper column.  This assumes ND space costs\n\t\t * 1 char.  So i+destcol is cost of motion with home.\n\t\t */\n\t\tif (GT)\n\t\t\ti = (destcol / HARDTABS) + (destcol % HARDTABS);\n\t\telse\n\t\t\ti = destcol;\n\t\t/*\n\t\t * j is cost to move locally without homing\n\t\t */\n\t\tif (destcol >= outcol) {\t/* if motion is to the right */\n\t\t\tj = destcol / HARDTABS - outcol / HARDTABS;\n\t\t\tif (GT && j)\n\t\t\t\tj += destcol % HARDTABS;\n\t\t\telse\n\t\t\t\tj = destcol - outcol;\n\t\t}\n\t\telse\n\t\t\t/* leftward motion only works if we can backspace. */\n\t\t\tif (outcol - destcol <= i && (BS || BC))\n\t\t\t\ti = j = outcol - destcol; /* cheaper to backspace */\n\t\t\telse\n\t\t\t\tj = i + 1; /* impossibly expensive */\n\n\t\t/* k is the absolute value of vertical distance */\n\t\tk = outline - destline;\n\t\tif (k < 0)\n\t\t\tk = -k;\n\t\tj += k;\n\n\t\t/*\n\t\t * Decision.  We may not have a choice if no UP.\n\t\t */\n\t\tif (i + destline < j || (!UP && destline < outline)) {\n\t\t\t/*\n\t\t\t * Cheaper to home.  Do it now and pretend it's a\n\t\t\t * regular local motion.\n\t\t\t */\n\t\t\ttputs(HO, 0, plodput);\n\t\t\toutcol = outline = 0;\n\t\t}\n\t\telse if (LL) {\n\t\t\t/*\n\t\t\t * Quickly consider homing down and moving from there.\n\t\t\t * Assume cost of LL is 2.\n\t\t\t */\n\t\t\tk = (LINES - 1) - destline;\n\t\t\tif (i + k + 2 < j && (k<=0 || UP)) {\n\t\t\t\ttputs(LL, 0, plodput);\n\t\t\t\toutcol = 0;\n\t\t\t\toutline = LINES - 1;\n\t\t\t}\n\t\t}\n\t}\n\telse\n\t/*\n\t * No home and no up means it's impossible.\n\t */\n\t\tif (!UP && destline < outline)\n\t\t\treturn -1;\n\tif (GT)\n\t\ti = destcol % HARDTABS + destcol / HARDTABS;\n\telse\n\t\ti = destcol;\n/*\n\tif (BT && outcol > destcol && (j = (((outcol+7) & ~7) - destcol - 1) >> 3)) {\n\t\tj *= (k = strlen(BT));\n\t\tif ((k += (destcol&7)) > 4)\n\t\t\tj += 8 - (destcol&7);\n\t\telse\n\t\t\tj += k;\n\t}\n\telse\n*/\n\t\tj = outcol - destcol;\n\t/*\n\t * If we will later need a \\n which will turn into a \\r\\n by\n\t * the system or the terminal, then don't bother to try to \\r.\n\t */\n\tif (!_pfast && outline < destline)\n\t\tgoto dontcr;\n\t/*\n\t * If the terminal will do a \\r\\n and there isn't room for it,\n\t * then we can't afford a \\r.\n\t */\n\tif (NC && outline >= destline)\n\t\tgoto dontcr;\n\t/*\n\t * If it will be cheaper, or if we can't back up, then send\n\t * a return preliminarily.\n\t */\n\tif (j > i + 1 || (outcol > destcol && !BS && !BC)) {\n\t\t/*\n\t\t * BUG: this doesn't take the (possibly long) length\n\t\t * of CR into account.\n\t\t */\n\t\tif (CR)\n\t\t\ttputs(CR, 0, plodput);\n\t\telse\n\t\t\tplodput('\\r');\n\t\tif (NC) {\n\t\t\tif (NL)\n\t\t\t\ttputs(NL, 0, plodput);\n\t\t\telse\n\t\t\t\tplodput('\\n');\n\t\t\toutline++;\n\t\t}\n\t\toutcol = 0;\n\t}\ndontcr:\n\twhile (outline < destline) {\n\t\toutline++;\n\t\tif (NL)\n\t\t\ttputs(NL, 0, plodput);\n\t\telse {\n                        plodput('\\n');\n                        if (!_pfast)\n                                outcol = 0;\n                }\n\t\tif (plodcnt < 0)\n\t\t\tgoto out;\n\t}\n\tif (BT)\n\t\tk = strlen(BT);\n\twhile (outcol > destcol) {\n\t\tif (plodcnt < 0)\n\t\t\tgoto out;\n/*\n\t\tif (BT && outcol - destcol > k + 4) {\n\t\t\ttputs(BT, 0, plodput);\n\t\t\toutcol--;\n\t\t\toutcol &= ~7;\n\t\t\tcontinue;\n\t\t}\n*/\n\t\toutcol--;\n\t\tif (BC)\n\t\t\ttputs(BC, 0, plodput);\n\t\telse\n\t\t\tplodput('\\b');\n\t}\n\twhile (outline > destline) {\n\t\toutline--;\n\t\ttputs(UP, 0, plodput);\n\t\tif (plodcnt < 0)\n\t\t\tgoto out;\n\t}\n\tif (GT && destcol - outcol > 1) {\n\t\tfor (;;) {\n\t\t\ti = tabcol(outcol, HARDTABS);\n\t\t\tif (i > destcol)\n\t\t\t\tbreak;\n\t\t\tif (TA)\n\t\t\t\ttputs(TA, 0, plodput);\n\t\t\telse\n\t\t\t\tplodput('\\t');\n\t\t\toutcol = i;\n\t\t}\n\t\tif (destcol - outcol > 4 && i < COLS && (BC || BS)) {\n\t\t\tif (TA)\n\t\t\t\ttputs(TA, 0, plodput);\n\t\t\telse\n\t\t\t\tplodput('\\t');\n\t\t\toutcol = i;\n\t\t\twhile (outcol > destcol) {\n\t\t\t\toutcol--;\n\t\t\t\tif (BC)\n\t\t\t\t\ttputs(BC, 0, plodput);\n\t\t\t\telse\n\t\t\t\t\tplodput('\\b');\n\t\t\t}\n\t\t}\n\t}\n\twhile (outcol < destcol) {\n\t\t/*\n\t\t * move one char to the right.  We don't use ND space\n\t\t * because it's better to just print the char we are\n\t\t * moving over.\n\t\t */\n\t\tif (_win != NULL)\n\t\t\tif (plodflg)\t/* avoid a complex calculation */\n\t\t\t\tplodcnt--;\n\t\t\telse {\n\t\t\t\ti = curscr->_y[outline][outcol];\n\t\t\t\tif ((i&_STANDOUT) == (curscr->_flags&_STANDOUT))\n\t\t\t\t\t_putchar(i);\n\t\t\t\telse\n\t\t\t\t\tgoto nondes;\n\t\t\t}\n\t\telse\nnondes:\n                if (ND)\n\t\t\ttputs(ND, 0, plodput);\n\t\telse\n\t\t\tplodput(' ');\n\t\toutcol++;\n\t\tif (plodcnt < 0)\n\t\t\tgoto out;\n\t}\nout:\n\tif (plodflg) {\n\t\toutcol = soutcol;\n\t\toutline = soutline;\n\t}\n\treturn(plodcnt);\n}\n\nvoid\nfgoto()\n{\n\tchar\t*cgp;\n\tint\tl, c;\n\n\tif (destcol >= COLS) {\n\t\tdestline += destcol / COLS;\n\t\tdestcol %= COLS;\n\t}\n\tif (outcol >= COLS) {\n\t\tl = (outcol + 1) / COLS;\n\t\toutline += l;\n\t\toutcol %= COLS;\n\t\tif (AM == 0) {\n\t\t\twhile (l > 0) {\n\t\t\t\tif (_pfast) {\n\t\t\t\t\tif (CR)\n\t\t\t\t\t\t_puts(CR);\n\t\t\t\t\telse\n\t\t\t\t\t\t_putchar('\\r');\n                                }\n\t\t\t\tif (NL)\n\t\t\t\t\t_puts(NL);\n\t\t\t\telse\n\t\t\t\t\t_putchar('\\n');\n\t\t\t\tl--;\n\t\t\t}\n\t\t\toutcol = 0;\n\t\t}\n\t\tif (outline > LINES - 1) {\n\t\t\tdestline -= outline - (LINES - 1);\n\t\t\toutline = LINES - 1;\n\t\t}\n\t}\n\tif (destline >= LINES) {\n\t\tl = destline;\n\t\tdestline = LINES - 1;\n\t\tif (outline < LINES - 1) {\n\t\t\tc = destcol;\n\t\t\tif (_pfast == 0 && !CA)\n\t\t\t\tdestcol = 0;\n\t\t\tfgoto();\n\t\t\tdestcol = c;\n\t\t}\n\t\twhile (l >= LINES) {\n\t\t\t/*\n\t\t\t * The following linefeed (or simulation thereof)\n\t\t\t * is supposed to scroll up the screen, since we\n\t\t\t * are on the bottom line.  We make the assumption\n\t\t\t * that linefeed will scroll.  If ns is in the\n\t\t\t * capability list this won't work.  We should\n\t\t\t * probably have an sc capability but sf will\n\t\t\t * generally take the place if it works.\n\t\t\t *\n\t\t\t * Superbee glitch:  in the middle of the screen we\n\t\t\t * have to use esc B (down) because linefeed screws up\n\t\t\t * in \"Efficient Paging\" (what a joke) mode (which is\n\t\t\t * essential in some SB's because CRLF mode puts garbage\n\t\t\t * in at end of memory), but you must use linefeed to\n\t\t\t * scroll since down arrow won't go past memory end.\n\t\t\t * I turned this off after recieving Paul Eggert's\n\t\t\t * Superbee description which wins better.\n\t\t\t */\n\t\t\tif (NL /* && !XB */ && _pfast)\n\t\t\t\t_puts(NL);\n\t\t\telse\n\t\t\t\t_putchar('\\n');\n\t\t\tl--;\n\t\t\tif (_pfast == 0)\n\t\t\t\toutcol = 0;\n\t\t}\n\t}\n\tif (destline < outline && !(CA || UP))\n\t\tdestline = outline;\n\tif (CA) {\n\t\tcgp = tgoto(CM, destcol, destline);\n\t\tif (plod(strlen(cgp)) > 0)\n\t\t\tplod(0);\n\t\telse\n\t\t\ttputs(cgp, 0, _putchar);\n\t}\n\telse\n\t\tplod(0);\n\toutline = destline;\n\toutcol = destcol;\n}\n\nvoid\nmvcur(ly, lx, y, x)\n        int\tly, lx, y, x;\n{\n#ifdef DEBUG\n\tfprintf(outf, \"MVCUR: moving cursor from (%d,%d) to (%d,%d)\\n\", ly, lx, y, x);\n#endif\n\tdestcol = x;\n\tdestline = y;\n\toutcol = lx;\n\toutline = ly;\n\tfgoto();\n}\n"
  },
  {
    "path": "lib/libcurses/cr_tty.c",
    "content": "/*\n * Terminal initialization routines.\n *\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n#include <term.h>\n#include <string.h>\n\nstatic bool\t*sflags[] = {\n\t\t\t&AM, &BS, &DA, &DB, &EO, &HC, &HZ, &IN, &MI,\n\t\t\t&MS, &NC, &NS, &OS, &UL, &XB, &XN, &XT, &XS,\n\t\t\t&XX\n\t\t};\n\nstatic char\t*_PC,\n\t\t**sstrs[] = {\n\t\t\t&AL, &BC, &BT, &CD, &CE, &CL, &CM, &CR, &CS,\n\t\t\t&DC, &DL, &DM, &DO, &ED, &EI, &K0, &K1, &K2,\n\t\t\t&K3, &K4, &K5, &K6, &K7, &K8, &K9, &HO, &IC,\n\t\t\t&IM, &IP, &KD, &KE, &KH, &KL, &KR, &KS, &KU,\n\t\t\t&LL, &MA, &ND, &NL, &_PC, &RC, &SC, &SE, &SF,\n\t\t\t&SO, &SR, &TA, &TE, &TI, &UC, &UE, &UP, &US,\n\t\t\t&VB, &VS, &VE, &AL_PARM, &DL_PARM, &UP_PARM,\n\t\t\t&DOWN_PARM, &LEFT_PARM, &RIGHT_PARM,\n\t\t};\n\nchar\t\t_tspace[2048];\t\t/* Space for capability strings */\n\nstatic char\t*aoftspace;\t\t/* Address of _tspace for relocation */\n\nstatic int\tdestcol, destline;\n\n/*\n *\tThis routine does terminal type initialization routines, and\n * calculation of flags at entry.  It is almost entirely stolen from\n * Bill Joy's ex version 2.6.\n */\nshort\tospeed = -1;\n\nvoid\ngettmode()\n{\n\tif (ioctl(_tty_ch, TIOCGETP, &_tty) < 0)\n\t\treturn;\n\tsavetty();\n\tif (ioctl(_tty_ch, TIOCSETP, &_tty) < 0)\n\t\t_tty.sg_flags = _res_flg;\n\tospeed = _tty.sg_ospeed;\n\t_res_flg = _tty.sg_flags;\n\tGT = ((_tty.sg_flags & XTABS) == 0);\n\tNONL = ((_tty.sg_flags & CRMOD) == 0);\n\t_pfast = NONL;\n\t_tty.sg_flags &= ~XTABS;\n\tioctl(_tty_ch, TIOCSETP, &_tty);\n# ifdef DEBUG\n\tfprintf(outf, \"GETTMODE: GT = %s\\n\", GT ? \"TRUE\" : \"FALSE\");\n\tfprintf(outf, \"GETTMODE: NONL = %s\\n\", NONL ? \"TRUE\" : \"FALSE\");\n\tfprintf(outf, \"GETTMODE: ospeed = %d\\n\", ospeed);\n# endif\n}\n\n/*\n * This routine gets all the terminal flags from the termcap database\n */\nstatic void\nzap()\n{\n\tregister char\t*namp;\n\tregister bool\t**fp;\n\tregister char\t***sp;\n#ifdef\tDEBUG\n\tregister char\t*cp;\n#endif\n\n\tnamp = \"ambsdadbeohchzinmimsncnsosulxbxnxtxsxx\";\n\tfp = sflags;\n\tdo {\n\t\t*(*fp++) = tgetflag(namp);\n#ifdef DEBUG\n\t\tfprintf(outf, \"%2.2s = %s\\n\", namp, *fp[-1] ? \"TRUE\" : \"FALSE\");\n#endif\n\t\tnamp += 2;\n\t} while (*namp);\n\tnamp = \"albcbtcdceclcmcrcsdcdldmdoedeik0k1k2k3k4k5k6k7k8k9hoicimipkdkekhklkrkskullmandnlpcrcscsesfsosrtatetiucueupusvbvsveALDLUPDOLERI\";\n\tsp = sstrs;\n\tdo {\n\t\t*(*sp++) = tgetstr(namp, &aoftspace);\n#ifdef DEBUG\n\t\tfprintf(outf, \"%2.2s = %s\", namp, *sp[-1] == NULL ? \"NULL\\n\" : \"\\\"\");\n\t\tif (*sp[-1] != NULL) {\n\t\t\tfor (cp = *sp[-1]; *cp; cp++)\n\t\t\t\tfprintf(outf, \"%s\", unctrl(*cp));\n\t\t\tfprintf(outf, \"\\\"\\n\");\n\t\t}\n#endif\n\t\tnamp += 2;\n\t} while (*namp);\n\tif (XS)\n\t\tSO = SE = NULL;\n\telse {\n\t\tif (tgetnum(\"sg\") > 0)\n\t\t\tSO = NULL;\n\t\tif (tgetnum(\"ug\") > 0)\n\t\t\tUS = NULL;\n\t\tif (!SO && US) {\n\t\t\tSO = US;\n\t\t\tSE = UE;\n\t\t}\n\t}\n\tif (DO && !NL)\n\t        NL = DO;\n}\n\nint\nsetterm(type)\n        char\t*type;\n{\n\tint\tunknown;\n\tstatic char genbuf[1024];\n# ifdef TIOCGWINSZ\n\tstruct winsize win;\n# endif\n\n# ifdef DEBUG\n\tfprintf(outf, \"SETTERM(\\\"%s\\\")\\n\", type);\n\tfprintf(outf, \"SETTERM: LINES = %d, COLS = %d\\n\", LINES, COLS);\n# endif\n\tif (type[0] == '\\0')\n\t\ttype = \"xx\";\n\tunknown = FALSE;\n\tif (tgetent(genbuf, type) != 1) {\n\t\tunknown++;\n\t\tstrcpy(genbuf, \"xx|dumb:\");\n\t}\n# ifdef DEBUG\n\tfprintf(outf, \"SETTERM: tty = %s\\n\", type);\n# endif\n# ifdef TIOCGWINSZ\n\tif (ioctl(_tty_ch, TIOCGWINSZ, &win) >= 0) {\n\t\tif (LINES == 0)\n\t\t\tLINES = win.ws_row;\n\t\tif (COLS == 0)\n\t\t\tCOLS = win.ws_col;\n\t}\n# endif\n\n\tif (LINES == 0)\n\t\tLINES = tgetnum(\"li\");\n\tif (LINES <= 5)\n\t\tLINES = 24;\n\n\tif (COLS == 0)\n\t\tCOLS = tgetnum(\"co\");\n\tif (COLS <= 4)\n\t\tCOLS = 80;\n\n# ifdef DEBUG\n\tfprintf(outf, \"SETTERM: LINES = %d, COLS = %d\\n\", LINES, COLS);\n# endif\n\taoftspace = _tspace;\n\tzap();\t\t\t/* get terminal description\t\t*/\n\n\t/*\n\t * Handle funny termcap capabilities\n\t */\n\tif (CS && SC && RC) AL=DL=\"\";\n\tif (AL_PARM && AL==NULL) AL=\"\";\n\tif (DL_PARM && DL==NULL) DL=\"\";\n\tif (IC && IM==NULL) IM=\"\";\n\tif (IC && EI==NULL) EI=\"\";\n\tif (!GT) BT=NULL;\t/* If we can't tab, we can't backtab either */\n\n\tif (tgoto(CM, destcol, destline)[0] == 'O')\n\t\tCA = FALSE, CM = 0;\n\telse\n\t\tCA = TRUE;\n\n\tPC = _PC ? _PC[0] : FALSE;\n\taoftspace = _tspace;\n\tstrncpy(ttytype, longname(genbuf, type), sizeof(ttytype) - 1);\n\tttytype[sizeof(ttytype) - 1] = '\\0';\n\tif (unknown)\n\t\treturn ERR;\n\treturn OK;\n}\n\n/*\n * return a capability from termcap\n */\nchar *\ngetcap(name)\nchar *name;\n{\n\tchar *tgetstr();\n\n\treturn tgetstr(name, &aoftspace);\n}\n"
  },
  {
    "path": "lib/libcurses/curses.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * Define global variables\n *\n */\n#include \"curses.h\"\n\nbool\t_echoit\t\t= TRUE,\t/* set if stty indicates ECHO\t\t*/\n\t_rawmode\t= FALSE,/* set if stty indicates RAW mode\t*/\n\tMy_term\t\t= FALSE,/* set if user specifies terminal type\t*/\n\t_endwin\t\t= FALSE;/* set if endwin has been called\t*/\n\nchar\tttytype[50],\t\t/* long name of tty\t\t\t*/\n\t*Def_term\t= \"unknown\";\t/* default terminal type\t*/\n\nint\t_tty_ch\t\t= 1,\t/* file channel which is a tty\t\t*/\n\tLINES,\t\t\t/* number of lines allowed on screen\t*/\n\tCOLS,\t\t\t/* number of columns allowed on screen\t*/\n\t_res_flg;\t\t/* sgtty flags for reseting later\t*/\n\nWINDOW\t*stdscr\t\t= NULL,\n\t*curscr\t\t= NULL;\n\n# ifdef DEBUG\nFILE\t*outf;\t\t\t/* debug output file\t\t\t*/\n# endif\n\nSGTTY\t_tty;\t\t\t/* tty modes\t\t\t\t*/\n\nbool\tAM, BS, CA, DA, DB, EO, HC, HZ, IN, MI, MS, NC, NS, OS, UL, XB, XN,\n\tXT, XS, XX;\nchar\t*AL, *BC, *BT, *CD, *CE, *CL, *CM, *CR, *CS, *DC, *DL, *DM,\n\t*DO, *ED, *EI, *K0, *K1, *K2, *K3, *K4, *K5, *K6, *K7, *K8,\n\t*K9, *HO, *IC, *IM, *IP, *KD, *KE, *KH, *KL, *KR, *KS, *KU,\n\t*LL, *MA, *ND, *NL, *RC, *SC, *SE, *SF, *SO, *SR, *TA, *TE,\n\t*TI, *UC, *UE, *UP, *US, *VB, *VS, *VE, *AL_PARM, *DL_PARM,\n\t*UP_PARM, *DOWN_PARM, *LEFT_PARM, *RIGHT_PARM;\nchar\tPC;\n\n/*\n * From the tty modes...\n */\n\nbool\tGT, NONL, normtty, _pfast;\n"
  },
  {
    "path": "lib/libcurses/curses.ext",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)curses.ext\t5.2 (Berkeley) 6/19/85\n */\n\n/*\n * External variables for the curses library\n */\n\n/* LINTLIBRARY */\n\n#include \"curses.h\"\n#include <stdarg.h>\n\nextern bool\t_echoit, _rawmode, My_term, _endwin;\n\nextern char\tttytype[50], *_unctrl[];\n\nextern int\t_tty_ch, LINES, COLS;\n\nextern SGTTY\t_tty;\n\nint\t_putchar (int);\nvoid    _id_subwins (WINDOW *);\nvoid    gettmode (void);\nvoid    tstp (int);\nint     _sprintw (WINDOW *, char *, va_list);\nint     _sscans (WINDOW *, char *, va_list); /* XXX */\nvoid    _swflags_ (WINDOW *);\nvoid    _set_subwin_ (WINDOW *, WINDOW *);\nvoid    mvcur (int, int, int, int);\n\n#ifdef DEBUG\n#   define\toutf\t_outf\n\nFILE\t\t*outf;\n#endif\n"
  },
  {
    "path": "lib/libcurses/delch.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n *\tThis routine performs an insert-char on the line, leaving\n * (_cury,_curx) unchanged.\n */\nint\nwdelch(win)\n        WINDOW\t*win;\n{\n\tchar\t*temp1, *temp2;\n\tchar\t*end;\n\n\tend = &win->_y[win->_cury][win->_maxx - 1];\n\ttemp1 = &win->_y[win->_cury][win->_curx];\n\ttemp2 = temp1 + 1;\n\twhile (temp1 < end)\n\t\t*temp1++ = *temp2++;\n\t*temp1 = ' ';\n\ttouchline(win, win->_cury, win->_curx, win->_maxx - 1);\n\treturn OK;\n}\n"
  },
  {
    "path": "lib/libcurses/deleteln.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n#include <strings.h>\n\n/*\n *\tThis routine deletes a line from the screen.  It leaves\n * (_cury,_curx) unchanged.\n */\nint\nwdeleteln(win)\n        WINDOW\t*win;\n{\n\tchar\t*temp;\n\tint\ty;\n\tchar\t*end;\n\n# ifdef DEBUG\n\tfprintf(outf, \"DELETELN(%0.2o)\\n\", win);\n# endif\n\ttemp = win->_y[win->_cury];\n\tfor (y = win->_cury; y < win->_maxy - 1; y++) {\n\t\tif (win->_orig == NULL)\n\t\t\twin->_y[y] = win->_y[y + 1];\n\t\telse\n\t\t\tbcopy(win->_y[y + 1], win->_y[y], win->_maxx);\n\t\ttouchline(win, y, 0, win->_maxx - 1);\n\t}\n\tif (win->_orig == NULL)\n\t\twin->_y[y] = temp;\n\telse\n\t\ttemp = win->_y[y];\n\tfor (end = &temp[win->_maxx]; temp < end; )\n\t\t*temp++ = ' ';\n\ttouchline(win, win->_cury, 0, win->_maxx - 1);\n\tif (win->_orig == NULL)\n\t\t_id_subwins(win);\n\treturn OK;\n}\n"
  },
  {
    "path": "lib/libcurses/delwin.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n#include <stdlib.h>\n\n/*\n * This routine deletes a window and releases it back to the system.\n */\nint\ndelwin(win)\n        WINDOW\t*win;\n{\n\tint\ti;\n\tWINDOW\t*wp, *np;\n\n\tif (win->_orig == NULL) {\n\t\t/*\n\t\t * If we are the original window, delete the space for\n\t\t * all the subwindows, and the array of space as well.\n\t\t */\n\t\tfor (i = 0; i < win->_maxy && win->_y[i]; i++)\n\t\t\tfree(win->_y[i]);\n\t\tfree(win->_firstch);\n\t\tfree(win->_lastch);\n\t\twp = win->_nextp;\n\t\twhile (wp != win) {\n\t\t\tnp = wp->_nextp;\n\t\t\tdelwin(wp);\n\t\t\twp = np;\n\t\t}\n\t} else {\n\t\t/*\n\t\t * If we are a subwindow, take ourselves out of the\n\t\t * list.  NOTE: if we are a subwindow, the minimum list\n\t\t * is orig followed by this subwindow, so there are\n\t\t * always at least two windows in the list.\n\t\t */\n\t\tfor (wp = win->_nextp; wp->_nextp != win; wp = wp->_nextp)\n\t\t\tcontinue;\n\t\twp->_nextp = win->_nextp;\n\t}\n\tfree(win->_y);\n\tfree(win);\n\treturn 0;\n}\n"
  },
  {
    "path": "lib/libcurses/endwin.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n * Clean things up before exiting\n */\nvoid endwin()\n{\n\tresetty();\n\t_puts(VE);\n\t_puts(TE);\n\tif (curscr) {\n\t\tif (curscr->_flags & _STANDOUT) {\n\t\t\t_puts(SE);\n\t\t\tcurscr->_flags &= ~_STANDOUT;\n\t\t}\n\t\t_endwin = TRUE;\n\t}\n}\n"
  },
  {
    "path": "lib/libcurses/erase.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n * This routine erases everything on the window.\n */\nvoid\nwerase(win)\n        WINDOW\t*win;\n{\n\tint\ty;\n\tchar\t*sp, *end, *start, *maxx;\n\tint\tminx;\n\n# ifdef DEBUG\n\tfprintf(outf, \"WERASE(%0.2o)\\n\", win);\n# endif\n\tfor (y = 0; y < win->_maxy; y++) {\n\t\tminx = _NOCHANGE;\n\t\tmaxx = 0;\n\t\tstart = win->_y[y];\n\t\tend = &start[win->_maxx];\n\t\tfor (sp = start; sp < end; sp++)\n\t\t\tif (*sp != ' ') {\n\t\t\t\tmaxx = sp;\n\t\t\t\tif (minx == _NOCHANGE)\n\t\t\t\t\tminx = sp - start;\n\t\t\t\t*sp = ' ';\n\t\t\t}\n\t\tif (minx != _NOCHANGE)\n\t\t\ttouchline(win, y, minx, maxx - win->_y[y]);\n\t}\n\twin->_curx = win->_cury = 0;\n}\n"
  },
  {
    "path": "lib/libcurses/fullname.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n *\tThis routine fills in \"def\" with the full name of the terminal.\n * This is assumed to be the last name in the list of aliases.\n *\n */\nchar *\nfullname(bp, def)\n        char\t*bp, *def;\n{\n\tchar\t*cp;\n\n\t*def = 0;\t\t\t/* in case no name */\n\n\twhile (*bp && *bp != ':') {\n\t\tcp = def;\t\t/* start of answer */\n\t\twhile (*bp && *bp != ':' && *bp != '|') {\n\t\t\t*cp++ = *bp++;\t/* copy name over */\n\t\t}\n\t\t*cp = 0;\t\t/* zero end of name */\n\t\tif (*bp == '|') {\n\t\t\tbp++;\t\t/* skip over '|' if that is case */\n\t\t}\n\t}\n\treturn(def);\n}\n"
  },
  {
    "path": "lib/libcurses/getch.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n * This routine reads in a character from the window.\n */\nint wgetch(win)\n        WINDOW\t*win;\n{\n\tbool\tweset = FALSE;\n\tchar\tinp;\n\n\tif (!win->_scroll && (win->_flags&_FULLWIN)\n\t    && win->_curx == win->_maxx - 1 && win->_cury == win->_maxy - 1)\n\t\treturn ERR;\n# ifdef DEBUG\n\tfprintf(outf, \"WGETCH: _echoit = %c, _rawmode = %c\\n\", _echoit ? 'T' : 'F', _rawmode ? 'T' : 'F');\n# endif\n\tif (_echoit && !_rawmode) {\n\t\tcbreak();\n\t\tweset++;\n\t}\n\tinp = getchar();\n# ifdef DEBUG\n\tfprintf(outf,\"WGETCH got '%s'\\n\",unctrl(inp));\n# endif\n\tif (_echoit) {\n\t\tmvwaddch(curscr, win->_cury + win->_begy,\n\t\t\twin->_curx + win->_begx, inp);\n\t\twaddch(win, inp);\n\t}\n\tif (weset)\n\t\tnocbreak();\n\treturn inp;\n}\n"
  },
  {
    "path": "lib/libcurses/getstr.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n * This routine gets a string starting at (_cury,_curx)\n */\nint\nwgetstr(win, str)\n        WINDOW\t*win;\n        char\t*str;\n{\n\twhile ((*str = wgetch(win)) != ERR && *str != '\\n')\n\t\tstr++;\n\tif (*str == ERR) {\n\t\t*str = '\\0';\n\t\treturn ERR;\n\t}\n\t*str = '\\0';\n\treturn OK;\n}\n"
  },
  {
    "path": "lib/libcurses/id_subwins.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n * _id_subwins:\n *\tRe-sync the pointers to _y for all the subwindows.\n */\nvoid\n_id_subwins(orig)\n        WINDOW\t*orig;\n{\n\tWINDOW\t*win;\n\tint\trealy;\n\tint\ty, oy;\n\n\trealy = orig->_begy + orig->_cury;\n\tfor (win = orig->_nextp; win != orig; win = win->_nextp) {\n\t\t/*\n\t\t * If the window ends before our current position,\n\t\t * don't need to do anything.\n\t\t */\n\t\tif (win->_begy + win->_maxy <= realy)\n\t\t\tcontinue;\n\n\t\toy = orig->_cury;\n\t\tfor (y = realy - win->_begy; y < win->_maxy; y++, oy++)\n\t\t\twin->_y[y] = &orig->_y[oy][win->_ch_off];\n\t}\n}\n"
  },
  {
    "path": "lib/libcurses/idlok.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n * idlok:\n *\tTurn on and off using insert/deleteln sequences for the given\n *\twindow.\n */\nvoid\nidlok(win, bf)\n        WINDOW\t*win;\n        bool\tbf;\n{\n\tif (bf)\n\t\twin->_flags |= _IDLINE;\n\telse\n\t\twin->_flags &= ~_IDLINE;\n}\n"
  },
  {
    "path": "lib/libcurses/initscr.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n#include <stdlib.h>\n#include <unistd.h>\n#include <signal.h>\n\n/*\n * This routine initializes the current and standard screen.\n */\nWINDOW *\ninitscr()\n{\n\tchar\t*sp;\n\tint \tnfd;\n\n# ifdef DEBUG\n\tfprintf(outf, \"INITSCR()\\n\");\n# endif\n\tif (My_term)\n\t\tsetterm(Def_term);\n\telse {\n\t        nfd = getdtablesize();\n\t\tfor (_tty_ch = 0; _tty_ch < nfd; _tty_ch++)\n\t\t\tif (isatty(_tty_ch))\n\t\t\t\tbreak;\n\t\tgettmode();\n\t\tsp = getenv(\"TERM\");\n\t\tif (! sp)\n\t\t\tsp = Def_term;\n\t\tsetterm(sp);\n# ifdef DEBUG\n\t\tfprintf(outf, \"INITSCR: term = %s\\n\", sp);\n# endif\n\t}\n\t_puts(TI);\n\t_puts(VS);\n# ifdef SIGTSTP\n\tsignal(SIGTSTP, (sig_t)tstp);\n# endif\n\tif (curscr != NULL) {\n# ifdef DEBUG\n\t\tfprintf(outf, \"INITSCR: curscr = 0%o\\n\", curscr);\n# endif\n\t\tdelwin(curscr);\n\t}\n# ifdef DEBUG\n\tfprintf(outf, \"LINES = %d, COLS = %d\\n\", LINES, COLS);\n# endif\n\tif ((curscr = newwin(LINES, COLS, 0, 0)) == ERR)\n\t\treturn ERR;\n\tclearok(curscr, TRUE);\n\tcurscr->_flags &= ~_FULLLINE;\n\tif (stdscr != NULL) {\n# ifdef DEBUG\n\t\tfprintf(outf, \"INITSCR: stdscr = 0%o\\n\", stdscr);\n# endif\n\t\tdelwin(stdscr);\n\t}\n\tstdscr = newwin(LINES, COLS, 0, 0);\n\treturn stdscr;\n}\n"
  },
  {
    "path": "lib/libcurses/insch.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n *\tThis routine performs an insert-char on the line, leaving\n * (_cury,_curx) unchanged.\n */\nint\nwinsch(win, c)\n        WINDOW\t*win;\n        char\tc;\n{\n\tchar\t*temp1, *temp2;\n\tchar\t*end;\n\n\tend = &win->_y[win->_cury][win->_curx];\n\ttemp1 = &win->_y[win->_cury][win->_maxx - 1];\n\ttemp2 = temp1 - 1;\n\twhile (temp1 > end)\n\t\t*temp1-- = *temp2--;\n\t*temp1 = c;\n\ttouchline(win, win->_cury, win->_curx, win->_maxx - 1);\n\tif (win->_cury == LINES - 1 && win->_y[LINES-1][COLS-1] != ' ') {\n\t\tif (! win->_scroll)\n\t\t\treturn ERR;\n\t\twrefresh(win);\n\t\tscroll(win);\n\t\twin->_cury--;\n        }\n\treturn OK;\n}\n"
  },
  {
    "path": "lib/libcurses/insertln.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n#include <strings.h>\n\n/*\n *\tThis routine performs an insert-line on the window, leaving\n * (_cury,_curx) unchanged.\n */\nvoid\nwinsertln(win)\n        WINDOW\t*win;\n{\n\tchar\t*temp = 0;\n\tint\ty;\n\tchar\t*end;\n\n#ifdef\tDEBUG\n\tfprintf(outf, \"INSERTLN(%0.2o)\\n\", win);\n#endif\n\tif (win->_orig == NULL)\n\t\ttemp = win->_y[win->_maxy - 1];\n\tfor (y = win->_maxy - 1; y > win->_cury; --y) {\n\t\tif (win->_orig == NULL)\n\t\t\twin->_y[y] = win->_y[y - 1];\n\t\telse\n\t\t\tbcopy(win->_y[y - 1], win->_y[y], win->_maxx);\n\t\ttouchline(win, y, 0, win->_maxx - 1);\n\t}\n\tif (win->_orig == NULL)\n\t\twin->_y[y] = temp;\n\telse\n\t\ttemp = win->_y[y];\n\tfor (end = &temp[win->_maxx]; temp < end; )\n\t\t*temp++ = ' ';\n\ttouchline(win, y, 0, win->_maxx - 1);\n\tif (win->_orig == NULL)\n\t\t_id_subwins(win);\n}\n"
  },
  {
    "path": "lib/libcurses/longname.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * This routine fills in \"def\" with the long name of the terminal.\n */\nchar *\nlongname(bp, def)\n        char\t*bp, *def;\n{\n\tchar\t*cp;\n\n\twhile (*bp && *bp != ':' && *bp != '|')\n\t\tbp++;\n\tif (*bp == '|') {\n\t\tbp++;\n\t\tcp = def;\n\t\twhile (*bp && *bp != ':' && *bp != '|')\n\t\t\t*cp++ = *bp++;\n\t\t*cp = 0;\n\t}\n\treturn def;\n}\n"
  },
  {
    "path": "lib/libcurses/move.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n * This routine moves the cursor to the given point\n */\nint wmove(win, y, x)\n        WINDOW\t*win;\n        int\ty, x;\n{\n#ifdef DEBUG\n\tfprintf(outf, \"MOVE to (%d, %d)\\n\", y, x);\n#endif\n\tif (x < 0 || y < 0)\n\t\treturn ERR;\n\tif (x >= win->_maxx || y >= win->_maxy)\n\t\treturn ERR;\n\twin->_curx = x;\n\twin->_cury = y;\n\treturn OK;\n}\n"
  },
  {
    "path": "lib/libcurses/mvprintw.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n * implement the mvprintw commands.  Due to the variable number of\n * arguments, they cannot be macros.  Sigh....\n *\n */\nint\nmvprintw(int y, int x, char *fmt, ...)\n{\n\tva_list args;\n        int ret;\n\n\tif (move(y, x) != OK)\n\t        return ERR;\n\tva_start (args, fmt);\n\tret = _sprintw (stdscr, fmt, args);\n\tva_end (args);\n\treturn ret;\n}\n\nint\nmvwprintw(WINDOW *win, int y, int x, char *fmt, ...)\n{\n\tva_list args;\n        int ret;\n\n\tif (wmove(win, y, x) != OK)\n\t        return ERR;\n\tva_start (args, fmt);\n\tret = _sprintw (win, fmt, args);\n\tva_end (args);\n\treturn ret;\n}\n"
  },
  {
    "path": "lib/libcurses/mvscanw.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n * implement the mvscanw commands.  Due to the variable number of\n * arguments, they cannot be macros.  Another sigh....\n */\nint\nmvscanw(y, x, fmt, args)\n        int\ty, x;\n        char\t*fmt;\n        va_list\targs; /* XXX */\n{\n\treturn move(y, x) == OK ? _sscans(stdscr, fmt, args) : ERR; /* XXX */\n}\n\nint\nmvwscanw(win, y, x, fmt, args)\n        WINDOW\t*win;\n        int\ty, x;\n        char\t*fmt;\n        va_list\targs; /* XXX */\n{\n\treturn wmove(win, y, x) == OK ? _sscans(win, fmt, args) : ERR; /* XXX */\n}\n"
  },
  {
    "path": "lib/libcurses/mvwin.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n * relocate the starting position of a window\n */\nint\nmvwin(win, by, bx)\n        WINDOW\t*win;\n        int\tby, bx;\n{\n\tWINDOW\t*orig;\n\tint\tdy, dx;\n\n\tif (by + win->_maxy > LINES || bx + win->_maxx > COLS)\n\t\treturn ERR;\n\tdy = by - win->_begy;\n\tdx = bx - win->_begx;\n\torig = win->_orig;\n\tif (orig == NULL) {\n\t\torig = win;\n\t\tdo {\n\t\t\twin->_begy += dy;\n\t\t\twin->_begx += dx;\n\t\t\t_swflags_(win);\n\t\t\twin = win->_nextp;\n\t\t} while (win != orig);\n\t}\n\telse {\n\t\tif (by < orig->_begy || win->_maxy + dy > orig->_maxy)\n\t\t\treturn ERR;\n\t\tif (bx < orig->_begx || win->_maxx + dx > orig->_maxx)\n\t\t\treturn ERR;\n\t\twin->_begy = by;\n\t\twin->_begx = bx;\n\t\t_swflags_(win);\n\t\t_set_subwin_(orig, win);\n\t}\n\ttouchwin(win);\n\treturn OK;\n}\n"
  },
  {
    "path": "lib/libcurses/newwin.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * allocate space for and set up defaults for a new window\n *\n */\n#include \"curses.ext\"\n#include <stdlib.h>\n\n#define SMALLOC\t(short*)malloc\n\n#undef nl\t/* don't need it here, and it interferes\t*/\n\n/*\n * This routine sets up a window buffer and returns a pointer to it.\n */\nstatic WINDOW *\nmakenew(num_lines, num_cols, begy, begx)\n        int\tnum_lines, num_cols, begy, begx;\n{\n\tWINDOW\t*win;\n\tint\tby, bx, nl, nc;\n\n\tby = begy;\n\tbx = begx;\n\tnl = num_lines;\n\tnc = num_cols;\n\n# ifdef\tDEBUG\n\tfprintf(outf, \"MAKENEW(%d, %d, %d, %d)\\n\", nl, nc, by, bx);\n# endif\n\tif ((win = (WINDOW *) malloc(sizeof *win)) == NULL)\n\t\treturn NULL;\n# ifdef DEBUG\n\tfprintf(outf, \"MAKENEW: nl = %d\\n\", nl);\n# endif\n\tif ((win->_y = (char **) malloc(nl * sizeof win->_y[0])) == NULL) {\n\t\tfree(win);\n\t\treturn NULL;\n\t}\n# ifdef DEBUG\n\tfprintf(outf, \"MAKENEW: nc = %d\\n\", nc);\n# endif\n\twin->_cury = win->_curx = 0;\n\twin->_clear = FALSE;\n\twin->_maxy = nl;\n\twin->_maxx = nc;\n\twin->_begy = by;\n\twin->_begx = bx;\n\twin->_flags = 0;\n\twin->_scroll = win->_leave = FALSE;\n\t_swflags_(win);\n# ifdef DEBUG\n\tfprintf(outf, \"MAKENEW: win->_clear = %d\\n\", win->_clear);\n\tfprintf(outf, \"MAKENEW: win->_leave = %d\\n\", win->_leave);\n\tfprintf(outf, \"MAKENEW: win->_scroll = %d\\n\", win->_scroll);\n\tfprintf(outf, \"MAKENEW: win->_flags = %0.2o\\n\", win->_flags);\n\tfprintf(outf, \"MAKENEW: win->_maxy = %d\\n\", win->_maxy);\n\tfprintf(outf, \"MAKENEW: win->_maxx = %d\\n\", win->_maxx);\n\tfprintf(outf, \"MAKENEW: win->_begy = %d\\n\", win->_begy);\n\tfprintf(outf, \"MAKENEW: win->_begx = %d\\n\", win->_begx);\n# endif\n\treturn win;\n}\n\nWINDOW *\nnewwin(num_lines, num_cols, begy, begx)\n        int\tnum_lines, num_cols, begy, begx;\n{\n\tWINDOW\t*win;\n\tchar\t*sp;\n\tint\ti, by, bx, nl, nc;\n\tint\tj;\n\n\tby = begy;\n\tbx = begx;\n\tnl = num_lines;\n\tnc = num_cols;\n\n\tif (nl == 0)\n\t\tnl = LINES - by;\n\tif (nc == 0)\n\t\tnc = COLS - bx;\n\tif ((win = makenew(nl, nc, by, bx)) == NULL)\n\t\treturn ERR;\n\tif ((win->_firstch = SMALLOC(nl * sizeof win->_firstch[0])) == NULL) {\n\t\tfree(win->_y);\n\t\tfree(win);\n\t\treturn NULL;\n\t}\n\tif ((win->_lastch = SMALLOC(nl * sizeof win->_lastch[0])) == NULL) {\n\t\tfree(win->_y);\n\t\tfree(win->_firstch);\n\t\tfree(win);\n\t\treturn NULL;\n\t}\n\twin->_nextp = win;\n\tfor (i = 0; i < nl; i++) {\n\t\twin->_firstch[i] = _NOCHANGE;\n\t\twin->_lastch[i] = _NOCHANGE;\n\t}\n\tfor (i = 0; i < nl; i++)\n\t\tif ((win->_y[i] = malloc(nc * sizeof win->_y[0])) == NULL) {\n\t\t\tfor (j = 0; j < i; j++)\n\t\t\t\tfree(win->_y[j]);\n\t\t\tfree(win->_firstch);\n\t\t\tfree(win->_lastch);\n\t\t\tfree(win->_y);\n\t\t\tfree(win);\n\t\t\treturn ERR;\n\t\t}\n\t\telse\n\t\t\tfor (sp = win->_y[i]; sp < win->_y[i] + nc; )\n\t\t\t\t*sp++ = ' ';\n\twin->_ch_off = 0;\n# ifdef DEBUG\n\tfprintf(outf, \"NEWWIN: win->_ch_off = %d\\n\", win->_ch_off);\n# endif\n\treturn win;\n}\n\nWINDOW *\nsubwin(orig, num_lines, num_cols, begy, begx)\n        WINDOW\t*orig;\n        int\tnum_lines, num_cols, begy, begx;\n{\n\tWINDOW\t*win;\n\tint\tby, bx, nl, nc;\n\n\tby = begy;\n\tbx = begx;\n\tnl = num_lines;\n\tnc = num_cols;\n\n\t/*\n\t * make sure window fits inside the original one\n\t */\n# ifdef\tDEBUG\n\tfprintf(outf, \"SUBWIN(%0.2o, %d, %d, %d, %d)\\n\", orig, nl, nc, by, bx);\n# endif\n\tif (by < orig->_begy || bx < orig->_begx\n\t    || by + nl > orig->_maxy + orig->_begy\n\t    || bx + nc > orig->_maxx + orig->_begx)\n\t\treturn ERR;\n\tif (nl == 0)\n\t\tnl = orig->_maxy + orig->_begy - by;\n\tif (nc == 0)\n\t\tnc = orig->_maxx + orig->_begx - bx;\n\tif ((win = makenew(nl, nc, by, bx)) == NULL)\n\t\treturn ERR;\n\twin->_nextp = orig->_nextp;\n\torig->_nextp = win;\n\twin->_orig = orig;\n\t_set_subwin_(orig, win);\n\treturn win;\n}\n\n/*\n * this code is shared with mvwin()\n */\nvoid\n_set_subwin_(orig, win)\n        register WINDOW\t*orig, *win;\n{\n\tregister int\ti, j, k;\n\n\tj = win->_begy - orig->_begy;\n\tk = win->_begx - orig->_begx;\n\twin->_ch_off = k;\n# ifdef DEBUG\n\tfprintf(outf, \"_SET_SUBWIN_: win->_ch_off = %d\\n\", win->_ch_off);\n# endif\n\twin->_firstch = &orig->_firstch[j];\n\twin->_lastch = &orig->_lastch[j];\n\tfor (i = 0; i < win->_maxy; i++, j++)\n\t\twin->_y[i] = &orig->_y[j][k];\n}\n\nvoid\n_swflags_(win)\n        register WINDOW\t*win;\n{\n\twin->_flags &= ~(_ENDLINE|_FULLLINE|_FULLWIN|_SCROLLWIN);\n\tif (win->_begx + win->_maxx == COLS) {\n\t\twin->_flags |= _ENDLINE;\n\t\tif (win->_begx == 0) {\n\t\t\tif (AL && DL)\n\t\t\t\twin->_flags |= _FULLLINE;\n\t\t\tif (win->_maxy == LINES && win->_begy == 0)\n\t\t\t\twin->_flags |= _FULLWIN;\n\t\t}\n\t\tif (win->_begy + win->_maxy == LINES)\n\t\t\twin->_flags |= _SCROLLWIN;\n\t}\n}\n"
  },
  {
    "path": "lib/libcurses/overlay.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n#include <ctype.h>\n#include <strings.h>\n\n#define min(a,b)\t(a < b ? a : b)\n#define max(a,b)\t(a > b ? a : b)\n\n/*\n * This routine writes win1 on win2 non-destructively.\n */\nvoid\noverlay(win1, win2)\n        WINDOW\t*win1, *win2;\n{\n\tchar\t*sp, *end;\n\tint\tx, y, endy, endx, starty, startx;\n\tint \ty1,y2;\n\n# ifdef DEBUG\n\tfprintf(outf, \"OVERLAY(%0.2o, %0.2o);\\n\", win1, win2);\n# endif\n\tstarty = max(win1->_begy, win2->_begy);\n\tstartx = max(win1->_begx, win2->_begx);\n\tendy = min(win1->_maxy + win1->_begy, win2->_maxy + win2->_begx);\n\tendx = min(win1->_maxx + win1->_begx, win2->_maxx + win2->_begx);\n# ifdef DEBUG\n\tfprintf(outf, \"OVERLAY:from (%d,%d) to (%d,%d)\\n\", starty, startx, endy, endx);\n# endif\n\tif (starty >= endy || startx >= endx)\n\t\treturn;\n\tx = endx - startx;\n\tfor (y = starty; y < endy; y++) {\n\t\tbcopy(&win1->_y[y - win1->_begy][startx - win1->_begx],\n\t\t      &win2->_y[y - win2->_begy][startx - win2->_begx], x);\n\t\ttouchline(win2, y, startx - win2->_begx, endx - win2->_begx);\n\t}\n\ty1 = starty - win1->_begy;\n\ty2 = starty - win2->_begy;\n\tfor (y = starty; y < endy; y++, y1++, y2++) {\n\t\tend = &win1->_y[y1][endx - win1->_begx];\n\t\tx = startx - win2->_begx;\n\t\tfor (sp = &win1->_y[y1][startx - win1->_begx]; sp < end; sp++) {\n\t\t\tif (!isspace(*sp))\n\t\t\t\tmvwaddch(win2, y2, x, *sp);\n\t\t\tx++;\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "lib/libcurses/overwrite.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n#include <ctype.h>\n#include <strings.h>\n\n#define min(a,b)\t(a < b ? a : b)\n#define max(a,b)\t(a > b ? a : b)\n\n/*\n * This routine writes win1 on win2 destructively.\n */\nvoid\noverwrite(win1, win2)\n        WINDOW\t*win1, *win2;\n{\n\tint\tx, y, endy, endx, starty, startx;\n\n# ifdef DEBUG\n\tfprintf(outf, \"OVERWRITE(%0.2o, %0.2o);\\n\", win1, win2);\n# endif\n\tstarty = max(win1->_begy, win2->_begy);\n\tstartx = max(win1->_begx, win2->_begx);\n\tendy = min(win1->_maxy + win1->_begy, win2->_maxy + win2->_begx);\n\tendx = min(win1->_maxx + win1->_begx, win2->_maxx + win2->_begx);\n\tif (starty >= endy || startx >= endx)\n\t\treturn;\n# ifdef DEBUG\n\tfprintf(outf, \"OVERWRITE:from (%d,%d) to (%d,%d)\\n\", starty, startx, endy, endx);\n# endif\n\tx = endx - startx;\n\tfor (y = starty; y < endy; y++) {\n\t\tbcopy(&win1->_y[y - win1->_begy][startx - win1->_begx],\n\t\t      &win2->_y[y - win2->_begy][startx - win2->_begx], x);\n\t\ttouchline(win2, y, startx - win2->_begx, endx - win2->_begx);\n\t}\n}\n"
  },
  {
    "path": "lib/libcurses/printw.c",
    "content": "/*\n * printw and friends\n *\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n * This routine actually executes the printf and adds it to the window\n *\n * This is really a modified version of \"sprintf\".  As such,\n * it assumes that sprintf interfaces with the other printf functions\n * in a certain way.  If this is not how your system works, you\n * will have to modify this routine to use the interface that your\n * \"sprintf\" uses.\n */\nint _sprintw (WINDOW *win, char *fmt, va_list args)\n{\n\tFILE\tjunk;\n\tchar\tbuf[512];\n\n\tjunk._flag = _IOWRT + _IOSTRG;\n\tjunk._ptr = buf;\n\tjunk._cnt = 32767;\n\t_doprnt(fmt, args, &junk);\n\tputc('\\0', &junk);\n\treturn waddstr(win, buf);\n}\n\n/*\n * This routine implements a printf on the standard screen.\n */\nint printw (char *fmt, ...)\n{\n\tva_list args;\n        int ret;\n\n\tva_start (args, fmt);\n\tret = _sprintw (stdscr, fmt, args);\n\tva_end (args);\n\treturn ret;\n}\n\n/*\n * This routine implements a printf on the given window.\n */\nint wprintw (WINDOW *win, char *fmt, ...)\n{\n\tva_list args;\n        int ret;\n\n\tva_start (args, fmt);\n\tret = _sprintw (win, fmt, args); /* XXX */\n\tva_end (args);\n\treturn ret;\n}\n"
  },
  {
    "path": "lib/libcurses/putchar.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\nint\n_putchar(c)\n        int\tc;\n{\n\tputchar(c);\n#ifdef DEBUG\n\tfprintf(outf, \"_PUTCHAR(%s)\\n\", unctrl(c));\n#endif\n        return 0;\n}\n"
  },
  {
    "path": "lib/libcurses/refresh.c",
    "content": "/*\n * make the current screen look like \"win\" over the area coverd by\n * win.\n *\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <string.h>\n#include \"curses.ext\"\n\n#ifdef DEBUG\n#   define STATIC\n#else\n#   define STATIC static\n#endif\n\nSTATIC short\tly, lx;\n\nSTATIC bool\tcurwin;\n\nWINDOW\t*_win = NULL;\n\n/*\n * perform a mvcur, leaving standout mode if necessary\n */\nSTATIC void\ndomvcur(oy, ox, ny, nx)\n        int\toy, ox, ny, nx;\n{\n\tif (curscr->_flags & _STANDOUT && !MS) {\n\t\t_puts(SE);\n\t\tcurscr->_flags &= ~_STANDOUT;\n\t}\n\tmvcur(oy, ox, ny, nx);\n}\n\n/*\n * make a change on the screen\n */\nSTATIC int\nmakech(win, wy)\n        WINDOW\t*win;\n        short\twy;\n{\n\tchar\t*nsp, *csp, *ce;\n\tshort\twx, lch, y;\n\tint\tnlsp = 0, clsp;         /* last space in lines */\n\n\twx = win->_firstch[wy] - win->_ch_off;\n\tif (wx >= win->_maxx)\n\t\treturn OK;\n\telse if (wx < 0)\n\t\twx = 0;\n\tlch = win->_lastch[wy] - win->_ch_off;\n\tif (lch < 0)\n\t\treturn OK;\n\telse if (lch >= win->_maxx)\n\t\tlch = win->_maxx - 1;;\n\ty = wy + win->_begy;\n\n\tif (curwin)\n\t\tcsp = \" \";\n\telse\n\t\tcsp = &curscr->_y[wy + win->_begy][wx + win->_begx];\n\n\tnsp = &win->_y[wy][wx];\n\tif (CE && !curwin) {\n\t\tfor (ce = &win->_y[wy][win->_maxx - 1]; *ce == ' '; ce--)\n\t\t\tif (ce <= win->_y[wy])\n\t\t\t\tbreak;\n\t\tnlsp = ce - win->_y[wy];\n\t}\n\n\tif (!curwin)\n\t\tce = CE;\n\telse\n\t\tce = NULL;\n\n\twhile (wx <= lch) {\n\t\tif (*nsp != *csp) {\n\t\t\tdomvcur(ly, lx, y, wx + win->_begx);\n# ifdef DEBUG\n\t\t\tfprintf(outf, \"MAKECH: 1: wx = %d, lx = %d\\n\", wx, lx);\n# endif\n\t\t\tly = y;\n\t\t\tlx = wx + win->_begx;\n\t\t\twhile (*nsp != *csp && wx <= lch) {\n\t\t\t\tif (ce != NULL && wx >= nlsp && *nsp == ' ') {\n\t\t\t\t\t/*\n\t\t\t\t\t * check for clear to end-of-line\n\t\t\t\t\t */\n\t\t\t\t\tce = &curscr->_y[ly][COLS - 1];\n\t\t\t\t\twhile (*ce == ' ')\n\t\t\t\t\t\tif (ce-- <= csp)\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\tclsp = ce - curscr->_y[ly] - win->_begx;\n# ifdef DEBUG\n\t\t\t\t\tfprintf(outf, \"MAKECH: clsp = %d, nlsp = %d\\n\", clsp, nlsp);\n# endif\n\t\t\t\t\tif (clsp - nlsp >= strlen(CE)\n\t\t\t\t\t    && clsp < win->_maxx) {\n# ifdef DEBUG\n\t\t\t\t\t\tfprintf(outf, \"MAKECH: using CE\\n\");\n# endif\n\t\t\t\t\t\t_puts(CE);\n\t\t\t\t\t\tlx = wx + win->_begx;\n\t\t\t\t\t\twhile (wx++ <= clsp)\n\t\t\t\t\t\t\t*csp++ = ' ';\n\t\t\t\t\t\treturn OK;\n\t\t\t\t\t}\n\t\t\t\t\tce = NULL;\n\t\t\t\t}\n\t\t\t\t/*\n\t\t\t\t * enter/exit standout mode as appropriate\n\t\t\t\t */\n\t\t\t\tif (SO && (*nsp&_STANDOUT) != (curscr->_flags&_STANDOUT)) {\n\t\t\t\t\tif (*nsp & _STANDOUT) {\n\t\t\t\t\t\t_puts(SO);\n\t\t\t\t\t\tcurscr->_flags |= _STANDOUT;\n\t\t\t\t\t}\n\t\t\t\t\telse {\n\t\t\t\t\t\t_puts(SE);\n\t\t\t\t\t\tcurscr->_flags &= ~_STANDOUT;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\twx++;\n\t\t\t\tif (wx >= win->_maxx && wy == win->_maxy - 1) {\n\t\t\t\t\tif (win->_scroll) {\n\t\t\t\t\t    if ((curscr->_flags&_STANDOUT) &&\n\t\t\t\t\t        (win->_flags & _ENDLINE))\n\t\t\t\t\t\t    if (!MS) {\n\t\t\t\t\t\t\t_puts(SE);\n\t\t\t\t\t\t\tcurscr->_flags &= ~_STANDOUT;\n\t\t\t\t\t\t    }\n\t\t\t\t\t    if (!curwin)\n\t\t\t\t\t\t_putchar((*csp = *nsp) & 0177);\n\t\t\t\t\t    else\n\t\t\t\t\t\t_putchar(*nsp & 0177);\n\t\t\t\t\t    if (win->_flags&_FULLWIN && !curwin)\n\t\t\t\t\t\tscroll(curscr);\n\t\t\t\t\t    ly = win->_begy+win->_cury;\n\t\t\t\t\t    lx = win->_begx+win->_curx;\n\t\t\t\t\t    return OK;\n\t\t\t\t\t}\n\t\t\t\t\telse if (win->_flags&_SCROLLWIN) {\n\t\t\t\t\t    lx = --wx;\n\t\t\t\t\t    return ERR;\n\t\t\t\t\t}\n                                }\n\t\t\t\tif (!curwin)\n\t\t\t\t\t_putchar((*csp++ = *nsp) & 0177);\n\t\t\t\telse\n\t\t\t\t\t_putchar(*nsp & 0177);\n# ifdef FULLDEBUG\n\t\t\t\tfprintf(outf,\n\t\t\t\t\t\"MAKECH:putchar(%c)\\n\", *nsp & 0177);\n# endif\n\t\t\t\tif (UC && (*nsp & _STANDOUT)) {\n\t\t\t\t\t_putchar('\\b');\n\t\t\t\t\t_puts(UC);\n\t\t\t\t}\n\t\t\t\tnsp++;\n\t\t\t}\n# ifdef DEBUG\n\t\t\tfprintf(outf, \"MAKECH: 2: wx = %d, lx = %d\\n\", wx, lx);\n# endif\n\t\t\tif (lx == wx + win->_begx)\t/* if no change */\n\t\t\t\tbreak;\n\t\t\tlx = wx + win->_begx;\n\t\t\tif (lx >= COLS && AM) {\n\t\t\t\tlx = 0;\n\t\t\t\tly++;\n\t\t\t\t/*\n\t\t\t\t * xn glitch: chomps a newline after auto-wrap.\n\t\t\t\t * we just feed it now and forget about it.\n\t\t\t\t */\n\t\t\t\tif (XN) {\n\t\t\t\t\t_putchar('\\n');\n\t\t\t\t\t_putchar('\\r');\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse if (wx <= lch)\n\t\t\twhile (*nsp == *csp && wx <= lch) {\n\t\t\t\tnsp++;\n\t\t\t\tif (!curwin)\n\t\t\t\t\tcsp++;\n\t\t\t\t++wx;\n\t\t\t}\n\t\telse\n\t\t\tbreak;\n# ifdef DEBUG\n\t\tfprintf(outf, \"MAKECH: 3: wx = %d, lx = %d\\n\", wx, lx);\n# endif\n\t}\n\treturn OK;\n}\n\nint wrefresh(win)\n        WINDOW\t*win;\n{\n\tshort\twy;\n\tint\tretval;\n\n\t/*\n\t * make sure were in visual state\n\t */\n\tif (_endwin) {\n\t\t_puts(VS);\n\t\t_puts(TI);\n\t\t_endwin = FALSE;\n\t}\n\n\t/*\n\t * initialize loop parameters\n\t */\n\n\tly = curscr->_cury;\n\tlx = curscr->_curx;\n\twy = 0;\n\t_win = win;\n\tcurwin = (win == curscr);\n\n\tif (win->_clear || curscr->_clear || curwin) {\n\t\tif ((win->_flags & _FULLWIN) || curscr->_clear) {\n\t\t\t_puts(CL);\n\t\t\tly = 0;\n\t\t\tlx = 0;\n\t\t\tif (!curwin) {\n\t\t\t\tcurscr->_clear = FALSE;\n\t\t\t\tcurscr->_cury = 0;\n\t\t\t\tcurscr->_curx = 0;\n\t\t\t\twerase(curscr);\n\t\t\t}\n\t\t\ttouchwin(win);\n\t\t}\n\t\twin->_clear = FALSE;\n\t}\n\tif (!CA) {\n\t\tif (win->_curx != 0)\n\t\t\t_putchar('\\n');\n\t\tif (!curwin)\n\t\t\twerase(curscr);\n\t}\n# ifdef DEBUG\n\tfprintf(outf, \"REFRESH(%0.2o): curwin = %d\\n\", win, curwin);\n\tfprintf(outf, \"REFRESH:\\n\\tfirstch\\tlastch\\n\");\n# endif\n\tfor (wy = 0; wy < win->_maxy; wy++) {\n# ifdef DEBUG\n\t\tfprintf(outf, \"%d\\t%d\\t%d\\n\", wy, win->_firstch[wy],\n\t\t\twin->_lastch[wy]);\n# endif\n\t\tif (win->_firstch[wy] != _NOCHANGE) {\n\t\t\tif (makech(win, wy) == ERR)\n\t\t\t\treturn ERR;\n\t\t\telse {\n\t\t\t\tif (win->_firstch[wy] >= win->_ch_off)\n\t\t\t\t\twin->_firstch[wy] = win->_maxx +\n\t\t\t\t\t\t\t    win->_ch_off;\n\t\t\t\tif (win->_lastch[wy] < win->_maxx +\n\t\t\t\t\t\t       win->_ch_off)\n\t\t\t\t\twin->_lastch[wy] = win->_ch_off;\n\t\t\t\tif (win->_lastch[wy] < win->_firstch[wy])\n\t\t\t\t\twin->_firstch[wy] = _NOCHANGE;\n\t\t\t}\n                }\n# ifdef DEBUG\n\t\tfprintf(outf, \"\\t%d\\t%d\\n\", win->_firstch[wy],\n\t\t\twin->_lastch[wy]);\n# endif\n\t}\n\n\tif (win == curscr)\n\t\tdomvcur(ly, lx, win->_cury, win->_curx);\n\telse {\n\t\tif (win->_leave) {\n\t\t\tcurscr->_cury = ly;\n\t\t\tcurscr->_curx = lx;\n\t\t\tly -= win->_begy;\n\t\t\tlx -= win->_begx;\n\t\t\tif (ly >= 0 && ly < win->_maxy && lx >= 0 &&\n\t\t\t    lx < win->_maxx) {\n\t\t\t\twin->_cury = ly;\n\t\t\t\twin->_curx = lx;\n\t\t\t}\n\t\t\telse\n\t\t\t\twin->_cury = win->_curx = 0;\n\t\t}\n\t\telse {\n\t\t\tdomvcur(ly, lx, win->_cury + win->_begy,\n\t\t\t\twin->_curx + win->_begx);\n\t\t\tcurscr->_cury = win->_cury + win->_begy;\n\t\t\tcurscr->_curx = win->_curx + win->_begx;\n\t\t}\n\t}\n\tretval = OK;\n\t_win = NULL;\n\tfflush(stdout);\n\treturn retval;\n}\n"
  },
  {
    "path": "lib/libcurses/scanw.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * scanw and friends\n *\n */\n#include <string.h>\n#include \"curses.ext\"\n\n/*\n *\tThis routine implements a scanf on the standard screen.\n */\nint\nscanw(fmt, args)\n        char\t*fmt;\n        va_list\targs; /* XXX */\n{\n\treturn _sscans(stdscr, fmt, args); /* XXX */\n}\n/*\n *\tThis routine implements a scanf on the given window.\n */\nint\nwscanw(win, fmt, args)\n        WINDOW\t*win;\n        char\t*fmt;\n        va_list\targs; /* XXX */\n{\n\treturn _sscans(win, fmt, args); /* XXX */\n}\n\n/*\n *\tThis routine actually executes the scanf from the window.\n *\n *\tThis is really a modified version of \"sscanf\".  As such,\n * it assumes that sscanf interfaces with the other scanf functions\n * in a certain way.  If this is not how your system works, you\n * will have to modify this routine to use the interface that your\n * \"sscanf\" uses.\n */\nint\n_sscans(win, fmt, args)\n        WINDOW\t*win;\n        char\t*fmt;\n        va_list\targs; /* XXX */\n{\n\tchar\tbuf[100];\n\tFILE\tjunk;\n\n\tjunk._flag = _IOREAD|_IOSTRG;\n\tjunk._base = junk._ptr = buf;\n\tif (wgetstr(win, buf) == ERR)\n\t\treturn ERR;\n\tjunk._cnt = strlen(buf);\n\treturn _doscan(&junk, fmt, args); /* XXX */\n}\n"
  },
  {
    "path": "lib/libcurses/scroll.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n * This routine scrolls the window up a line.\n */\nint\nscroll(win)\n        WINDOW *win;\n{\n\tint\toy, ox;\n\n# ifdef DEBUG\n\tfprintf(outf, \"SCROLL(%0.2o)\\n\", win);\n# endif\n\n\tif (! win->_scroll)\n\t\treturn ERR;\n\n\tgetyx(win, oy, ox);\n\twmove(win, 0, 0);\n\twdeleteln(win);\n\twmove(win, oy, ox);\n\n\tif (win == curscr) {\n\t\t_putchar('\\n');\n\t\tif (!NONL)\n\t\t\twin->_curx = 0;\n# ifdef DEBUG\n\t\tfprintf(outf, \"SCROLL: win == curscr\\n\");\n# endif\n\t}\n\treturn OK;\n}\n"
  },
  {
    "path": "lib/libcurses/standout.c",
    "content": "/*\n * routines dealing with entering and exiting standout mode\n *\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n * enter standout mode\n */\nchar *\nwstandout(win)\n        WINDOW\t*win;\n{\n\tif (!SO && !UC)\n\t\treturn FALSE;\n\n\twin->_flags |= _STANDOUT;\n\treturn (SO ? SO : UC);\n}\n\n/*\n * exit standout mode\n */\nchar *\nwstandend(win)\n        WINDOW\t*win;\n{\n\tif (!SO && !UC)\n\t\treturn FALSE;\n\n\twin->_flags &= ~_STANDOUT;\n\treturn (SE ? SE : UC);\n}\n"
  },
  {
    "path": "lib/libcurses/test.c",
    "content": "#include <curses.h>\n\n#define YPOSBOX\t\t 0\n#define XPOSBOX\t\t 0\n#define YBOX\t\t20\n#define XBOX\t        80\n\n#define YPOSSBOX\t 2\n#define XPOSSBOX\t10\n#define YSBOX\t        17\n#define XSBOX\t        66\n\nWINDOW *boxing,*sub_box;\nmain()\n{\n\tboxing = newwin(YBOX,XBOX,YPOSBOX,XPOSBOX);\n\tsub_box = subwin(boxing,YSBOX,XSBOX,YPOSSBOX,XPOSSBOX);\n\tinitscr();\n\tbox(boxing,'|','-');\n\twrefresh(boxing);\n\tbox(sub_box,'.','.');\n\toverlay(sub_box,boxing);/* overlays sub_box on top of boxing */\n\twrefresh(sub_box);\n\tmvcur(0,COLS-1,LINES-1,0);\t/* move to bottom of screen */\n\tendwin();\n}\n"
  },
  {
    "path": "lib/libcurses/toucholap.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n#define min(a,b)\t(a < b ? a : b)\n#define max(a,b)\t(a > b ? a : b)\n\n/*\n * Touch, on win2, the part that overlaps with win1.\n */\nvoid\ntouchoverlap(win1, win2)\n        WINDOW\t*win1, *win2;\n{\n\tint\ty, endy, endx, starty, startx;\n\n# ifdef DEBUG\n\tfprintf(outf, \"TOUCHOVERLAP(%0.2o, %0.2o);\\n\", win1, win2);\n# endif\n\tstarty = max(win1->_begy, win2->_begy);\n\tstartx = max(win1->_begx, win2->_begx);\n\tendy = min(win1->_maxy + win1->_begy, win2->_maxy + win2->_begx);\n\tendx = min(win1->_maxx + win1->_begx, win2->_maxx + win2->_begx);\n# ifdef DEBUG\n\tfprintf(outf, \"TOUCHOVERLAP:from (%d,%d) to (%d,%d)\\n\", starty, startx, endy, endx);\n\tfprintf(outf, \"TOUCHOVERLAP:win1 (%d,%d) to (%d,%d)\\n\", win1->_begy, win1->_begx, win1->_begy + win1->_maxy, win1->_begx + win1->_maxx);\n\tfprintf(outf, \"TOUCHOVERLAP:win2 (%d,%d) to (%d,%d)\\n\", win2->_begy, win2->_begx, win2->_begy + win2->_maxy, win2->_begx + win2->_maxx);\n# endif\n\tif (starty >= endy || startx >= endx)\n\t\treturn;\n\tstarty -= win2->_begy;\n\tstartx -= win2->_begx;\n\tendy -= win2->_begy;\n\tendx -= win2->_begx;\n\tendx--;\n\tfor (y = starty; y < endy; y++)\n\t\ttouchline(win2, y, startx, endx);\n}\n"
  },
  {
    "path": "lib/libcurses/touchwin.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include \"curses.ext\"\n\n/*\n * make it look like the whole window has been changed.\n *\n */\nint touchwin(win)\n        WINDOW\t*win;\n{\n\tint\ty, maxy;\n\n# ifdef\tDEBUG\n\tfprintf(outf, \"TOUCHWIN(%0.2o)\\n\", win);\n# endif\n\tmaxy = win->_maxy;\n\tfor (y = 0; y < maxy; y++)\n\t\ttouchline(win, y, 0, win->_maxx - 1);\n        return OK;\n}\n\n/*\n * touch a given line\n */\nint touchline(win, y, sx, ex)\n        WINDOW\t*win;\n        int\ty, sx, ex;\n{\n# ifdef DEBUG\n\tfprintf(outf, \"TOUCHLINE(%0.2o, %d, %d, %d)\\n\", win, y, sx, ex);\n\tfprintf(outf, \"TOUCHLINE:first = %d, last = %d\\n\", win->_firstch[y], win->_lastch[y]);\n# endif\n\tsx += win->_ch_off;\n\tex += win->_ch_off;\n\tif (win->_firstch[y] == _NOCHANGE) {\n\t\twin->_firstch[y] = sx;\n\t\twin->_lastch[y] = ex;\n\t}\n\telse {\n\t\tif (win->_firstch[y] > sx)\n\t\t\twin->_firstch[y] = sx;\n\t\tif (win->_lastch[y] < ex)\n\t\t\twin->_lastch[y] = ex;\n\t}\n# ifdef\tDEBUG\n\tfprintf(outf, \"TOUCHLINE:first = %d, last = %d\\n\", win->_firstch[y], win->_lastch[y]);\n# endif\n        return OK;\n}\n"
  },
  {
    "path": "lib/libcurses/tstp.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <signal.h>\n#include \"curses.ext\"\n\n/*\n * handle stop and start signals\n */\nvoid tstp(sig)\n\tint\tsig;\n{\n\tSGTTY\ttty;\n\tsigset_t oset, set;\n#ifdef DEBUG\n\tif (outf)\n\t\tfflush(outf);\n#endif\n\t/*\n\t * Block window change and timer signals.  The latter is because\n\t * applications use timers to decide when to repaint the screen.\n\t */\n\t(void)sigemptyset(&set);\n\t(void)sigaddset(&set, SIGALRM);\n\t(void)sigaddset(&set, SIGWINCH);\n\t(void)sigprocmask(SIG_BLOCK, &set, &oset);\n\n\ttty = _tty;\n\tmvcur(0, COLS - 1, LINES - 1, 0);\n\tendwin();\n\tfflush(stdout);\n\n\t/* Unblock SIGTSTP. */\n\t(void)sigemptyset(&set);\n\t(void)sigaddset(&set, SIGTSTP);\n\t(void)sigprocmask(SIG_UNBLOCK, &set, NULL);\n\n\t/* Stop ourselves. */\n\tsignal(SIGTSTP, SIG_DFL);\n\tkill(0, SIGTSTP);\n\n\t/* Time passes ... */\n\n\t/* Reset the SIGTSTP handler. */\n\tsignal(SIGTSTP, (sig_t)tstp);\n\n\t_tty = tty;\n\tioctl(_tty_ch, TIOCSETP, &_tty);\n\n\t/* Repaint the screen. */\n\twrefresh(curscr);\n\n\t/* Reset the signals. */\n\t(void)sigprocmask(SIG_SETMASK, &oset, NULL);\n}\n"
  },
  {
    "path": "lib/libcurses/unctrl.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n/*\n * define unctrl codes for each character\n *\n */\n\n/* LINTLIBRARY */\nchar *_unctrl[] = {\t/* unctrl codes for ttys\t\t*/\n\t\"^@\", \"^A\", \"^B\", \"^C\", \"^D\", \"^E\", \"^F\", \"^G\", \"^H\", \"^I\", \"^J\", \"^K\",\n\t\"^L\", \"^M\", \"^N\", \"^O\", \"^P\", \"^Q\", \"^R\", \"^S\", \"^T\", \"^U\", \"^V\", \"^W\",\n\t\"^X\", \"^Y\", \"^Z\", \"^[\", \"^\\\\\", \"^]\", \"^~\", \"^_\",\n\t\" \", \"!\", \"\\\"\", \"#\", \"$\",  \"%\", \"&\", \"'\", \"(\", \")\", \"*\", \"+\", \",\", \"-\",\n\t\".\", \"/\", \"0\",  \"1\", \"2\",  \"3\", \"4\", \"5\", \"6\", \"7\", \"8\", \"9\", \":\", \";\",\n\t\"<\", \"=\", \">\",  \"?\", \"@\",  \"A\", \"B\", \"C\", \"D\", \"E\", \"F\", \"G\", \"H\", \"I\",\n\t\"J\", \"K\", \"L\",  \"M\", \"N\",  \"O\", \"P\", \"Q\", \"R\", \"S\", \"T\", \"U\", \"V\", \"W\",\n\t\"X\", \"Y\", \"Z\",  \"[\", \"\\\\\", \"]\", \"^\", \"_\", \"`\", \"a\", \"b\", \"c\", \"d\", \"e\",\n\t\"f\", \"g\", \"h\",  \"i\", \"j\",  \"k\", \"l\", \"m\", \"n\", \"o\", \"p\", \"q\", \"r\", \"s\",\n\t\"t\", \"u\", \"v\",  \"w\", \"x\",  \"y\", \"z\", \"{\", \"|\", \"}\", \"~\", \"^?\"\n};\n"
  },
  {
    "path": "lib/libgpanel/Makefile",
    "content": "TOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS          += -O -Wall\nMAN             = gpanel.0\nMANSRC          = gpanel.3\n\nOBJS    \t= open.o clear.o pixel.o line.o rect.o fill.o fill_triangle.o \\\n                  circle.o image.o char.o text.o text_width.o\n\nall:    \t../libgpanel.a $(MAN)\n\n../libgpanel.a: ${OBJS}\n\t\t@${AR} cr $@ ${OBJS}\n\t\t$(RANLIB) $@\n\n$(MAN):         $(MANSRC)\n\t\t${MANROFF} ${MANSRC} > $@\n\ninstall: \tall\n\t\tcp ${MAN} ${DESTDIR}/usr/share/man/cat3/\n\nclean:\n\t\trm -f *.o a.out core test errs ../libgpanel*.a $(MAN)\n"
  },
  {
    "path": "lib/libgpanel/char.c",
    "content": "/*\n * Draw a single character glyph.\n *\n * Copyright (C) 2015 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/ioctl.h>\n#include <sys/gpanel.h>\n\nvoid gpanel_char(const struct gpanel_font_t *font, int color, int background,\n    int x, int y, int sym)\n{\n    struct gpanel_char_t param;\n\n    param.font = font;\n    param.color = color;\n    param.background = background;\n    param.x = x;\n    param.y = y;\n    param.sym = sym;\n    ioctl(_gpanel_fd, GPANEL_CHAR, &param);\n}\n"
  },
  {
    "path": "lib/libgpanel/circle.c",
    "content": "/*\n * Draw a circle (no fill).\n *\n * Copyright (C) 2015 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/ioctl.h>\n#include <sys/gpanel.h>\n\nvoid gpanel_circle(int color, int x, int y, int radius)\n{\n    struct gpanel_circle_t param;\n\n    param.color = color;\n    param.x = x;\n    param.y = y;\n    param.radius = radius;\n    ioctl(_gpanel_fd, GPANEL_CIRCLE, &param);\n}\n"
  },
  {
    "path": "lib/libgpanel/clear.c",
    "content": "/*\n * Clear the screen.\n *\n * Copyright (C) 2015 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/ioctl.h>\n#include <sys/gpanel.h>\n\nvoid gpanel_clear(int color, int *xsize, int *ysize)\n{\n    struct gpanel_clear_t param;\n\n    param.color = color;\n    param.xsize = xsize ? *xsize : 0;\n    param.ysize = ysize ? *ysize : 0;\n    ioctl(_gpanel_fd, GPANEL_CLEAR, &param);\n    if (xsize)\n        *xsize = param.xsize;\n    if (ysize)\n        *ysize = param.ysize;\n}\n"
  },
  {
    "path": "lib/libgpanel/fill.c",
    "content": "/*\n * Fill a rectangle.\n *\n * Copyright (C) 2015 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/ioctl.h>\n#include <sys/gpanel.h>\n\nvoid gpanel_fill(int color, int x0, int y0, int x1, int y1)\n{\n    struct gpanel_rect_t param;\n\n    param.color = color;\n    param.x0 = x0;\n    param.y0 = y0;\n    param.x1 = x1;\n    param.y1 = y1;\n    ioctl(_gpanel_fd, GPANEL_FILL, &param);\n}\n"
  },
  {
    "path": "lib/libgpanel/fill_triangle.c",
    "content": "/*\n * Fill a triangle.\n * Code ported from AdaFruit TFT LCD library.\n *\n * Copyright (C) 2015 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/ioctl.h>\n#include <sys/gpanel.h>\n\n/*\n * Swap values of two integer variables.\n */\n#define swapi(x,y) { int _t = x; x = y; y = _t; }\n\nvoid gpanel_fill_triangle(int color, int x0, int y0,\n    int x1, int y1, int x2, int y2)\n{\n    int a, b, y, last;\n\n    // Sort coordinates by Y order (y2 >= y1 >= y0)\n    if (y0 > y1) {\n        swapi(y0, y1);\n        swapi(x0, x1);\n    }\n    if (y1 > y2) {\n        swapi(y2, y1);\n        swapi(x2, x1);\n    }\n    if (y0 > y1) {\n        swapi(y0, y1);\n        swapi(x0, x1);\n    }\n\n    if (y0 == y2) {\n        // Handle awkward all-on-same-line case as its own thing\n        a = b = x0;\n\n        if (x1 < a)\n            a = x1;\n        else if (x1 > b)\n            b = x1;\n\n        if (x2 < a)\n            a = x2;\n        else if (x2 > b)\n            b = x2;\n\n        gpanel_fill(color, a, y0, b, y0);\n        return;\n    }\n\n    int dx01 = x1 - x0;\n    int dy01 = y1 - y0;\n    int dx02 = x2 - x0;\n    int dy02 = y2 - y0;\n    int dx12 = x2 - x1;\n    int dy12 = y2 - y1;\n    int sa = 0;\n    int sb = 0;\n\n    // For upper part of triangle, find scanline crossings for segments\n    // 0-1 and 0-2.  If y1=y2 (flat-bottomed triangle), the scanline y1\n    // is included here (and second loop will be skipped, avoiding a /0\n    // error there), otherwise scanline y1 is skipped here and handled\n    // in the second loop...which also avoids a /0 error here if y0=y1\n    // (flat-topped triangle).\n    if (y1 == y2)\n        last = y1;      // Include y1 scanline\n    else\n        last = y1-1;    // Skip it\n\n    for (y=y0; y<=last; y++) {\n        a   = x0 + sa / dy01;\n        b   = x0 + sb / dy02;\n        sa += dx01;\n        sb += dx02;\n\n        /* longhand:\n         * a = x0 + (x1 - x0) * (y - y0) / (y1 - y0);\n         * b = x0 + (x2 - x0) * (y - y0) / (y2 - y0);\n         */\n        if (a > b)\n            swapi(a, b);\n\n        gpanel_fill(color, a, y, b, y);\n    }\n\n    // For lower part of triangle, find scanline crossings for segments\n    // 0-2 and 1-2.  This loop is skipped if y1=y2.\n    sa = dx12 * (y - y1);\n    sb = dx02 * (y - y0);\n    for (; y<=y2; y++) {\n        a   = x1 + sa / dy12;\n        b   = x0 + sb / dy02;\n        sa += dx12;\n        sb += dx02;\n\n        /* longhand:\n         * a = x1 + (x2 - x1) * (y - y1) / (y2 - y1);\n         * b = x0 + (x2 - x0) * (y - y0) / (y2 - y0);\n         */\n        if (a > b)\n            swapi(a, b);\n\n        gpanel_fill(color, a, y, b, y);\n    }\n}\n"
  },
  {
    "path": "lib/libgpanel/gpanel.3",
    "content": ".\\\" No copyright (2015) - Serge Vakulenko (serge@vak.ru)\n.\\\"\n.TH GPANEL 3 \"June 10, 2023\"\n.UC 6\n.SH NAME\ngpanel_open, gpanel_close, gpanel_clear, gpanel_pixel, gpanel_line, gpanel_rect, gpanel_fill, gpanel_circle, gpanel_image, gpanel_char, gpanel_text, panel_text_width \\- graphics panel routines\n.SH SYNOPSIS\n.nf\n.PP\n.ft B\n#include <sys/gpanel.h>\n.PP\n.ft B\nint gpanel_open(const char *devname);\n.PP\n.ft B\nvoid gpanel_close(void);\n.PP\n.ft B\nvoid gpanel_clear(int color, int *xsize, int *ysize);\n.PP\n.ft B\nvoid gpanel_pixel(int color, int x, int y);\n.PP\n.ft B\nvoid gpanel_line(int color, int x0, int y0, int x1, int y1);\n.PP\n.ft B\nvoid gpanel_rect(int color, int x0, int y0, int x1, int y1);\n.PP\n.ft B\nvoid gpanel_fill(int color, int x0, int y0, int x1, int y1);\n.PP\n.ft B\nvoid gpanel_circle(int color, int x, int y, int radius);\n.PP\n.ft B\nvoid gpanel_image(int x, int y, int width, int height,\n                  const unsigned short *data);\n.PP\n.ft B\nvoid gpanel_char(const struct gpanel_font_t *font, int color,\n                 int background, int x, int y, int sym);\n.PP\n.ft B\nvoid gpanel_text(const struct gpanel_font_t *font, int color,\n                 int background, int x, int y, const char *text);\n.PP\n.ft B\nint gpanel_text_width(const struct gpanel_font_t *font,\n                      const char *text, int nchars);\n.fi\n.bp\n.SH DESCRIPTION\nThis library provides a set of routines for access to a graphics panel\nlike TFT LCD or OLED displays.  HX8357 display on a Picadillo-35T board\nis an example of such display. Use cc option\n.I -lgpanel\nto link the gpanel library.\n.PP\n.IR gpanel_open\n\\- This routine opens a connection to the display driver.\nThe argument to this function is the name of the device, like \"/dev/tft0\".\nNegative value is returned in case of error.\n.PP\n.IR gpanel_close\n\\- Close a connection to the device.\n.PP\n.IR gpanel_clear\n\\- This routine is used to clear the whole screen to a given color,\noptionally switch the display resolution and orientation,\nand get the display size in pixels.\nOn input, parameters\n.I xsize\nand\n.I ysize\nshould contain the desired dimensions of the display, or zeros to use\nthe default screen size and orientation. On output,\n.I xsize\nand\n.I ysize\nare set to the current display size.\n.PP\n.IR gpanel_pixel\n\\- Draw a single pixel of a specified color.\n.PP\n.IR gpanel_line\n\\- Draw a line.\n.PP\n.IR gpanel_rect\n\\- Draw a rectangular frame (not filled).\n.PP\n.IR gpanel_fill\n\\- Draw a rectangle filled with specified color.\n.PP\n.IR gpanel_circle\n\\- Draw a circle with a given center and radius.\n.PP\n.IR gpanel_image\n\\- Draw an arbitrary image: fill a rectangular area with pixel values\nfrom a user-supplied data.\n.PP\n.IR gpanel_char\n\\- Draw a single character with a specified Unicode encoding.\n.PP\n.IR gpanel_text\n\\- Draw a text string in UTF-8 encoding.\n.PP\n.IR gpanel_text_width\n\\- Compute a width in pixels for a text string in UTF-8 encoding.\n.PP\n.SH EXAMPLE\n.ft R\n#include <stdio.h>\n.br\n#include <sys/gpanel.h>\n\nint main()\n.br\n{\n    int xsize, ysize;\n\n    if (gpanel_open(\"/dev/tft0\") < 0) {\n        printf(\"Cannot open display\\n\");\n        exit(-1);\n    }\n    /* Get screen size */\n    gpanel_clear(0, &xsize, &ysize);\n\n    /* Draw a white rectangle of max size */\n    gpanel_rect(0xffff, 0, 0, xsize-1, ysize-1);\n    return 0;\n.br\n}\n.fi\n.SH FONTS\n.ft R\nstruct gpanel_font_t {\n    const char *    name;         /* font name */\n    int             maxwidth;     /* max width in pixels */\n    unsigned int    height;       /* height in pixels */\n    int             ascent;       /* ascent (baseline) height */\n    int             firstchar;    /* first character in bitmap */\n    int             size;         /* font size in characters */\n    const unsigned short *bits;   /* 16-bit right-padded bitmap data */\n    const unsigned short *offset; /* offsets into bitmap data */\n    const unsigned char *width;   /* character widths or 0 if fixed */\n    int             defaultchar;  /* default char (not glyph index) */\n    long            bits_size;    /* number of words of bits */\n.br\n};\n.PP\nFonts are specified via a data structure\n.I struct\\ gpanel_font_t\n, which defines character sizes and glyph images.\nFont data for some commonly used fonts are available in\n.I /usr/share/examples/gpanel/fonts\ndirectory.\nA utility\n.I convbdf\ncan be used to convert XWindows BDF fonts to a struct gpanel_font_t data.\nWhen combined with\n.I otf2bdf\nutility, this allows to generate font data for any TrueType font,\nlike Verdana or Lucida Sans Unicode.\n.SH BUGS\nData and font pointers in gpanel_image and gpanel_text routines\nare not checked for validity, and can cause unexpected errors when not correct.\n.SH FILES\n.ta \\w'/usr/share/examples/gpanel  'u\n/usr/share/examples/gpanel  Examples of using the \\fIlibgpanel\\fP library.\n.PP\n/dev/tft0                   Device name for hx8357 TFT display driver.\n"
  },
  {
    "path": "lib/libgpanel/image.c",
    "content": "/*\n * Draw a rectangular image.\n *\n * Copyright (C) 2015 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/ioctl.h>\n#include <sys/gpanel.h>\n\nvoid gpanel_image(int x, int y, int width, int height, const unsigned short *data)\n{\n    struct gpanel_image_t param;\n\n    param.x = x;\n    param.y = y;\n    param.width = width;\n    param.height = height;\n    param.image = data;\n    ioctl(_gpanel_fd, GPANEL_IMAGE, &param);\n}\n"
  },
  {
    "path": "lib/libgpanel/line.c",
    "content": "/*\n * Draw a line.\n *\n * Copyright (C) 2015 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/ioctl.h>\n#include <sys/gpanel.h>\n\nvoid gpanel_line(int color, int x0, int y0, int x1, int y1)\n{\n    struct gpanel_line_t param;\n\n    param.color = color;\n    param.x0 = x0;\n    param.y0 = y0;\n    param.x1 = x1;\n    param.y1 = y1;\n    ioctl(_gpanel_fd, GPANEL_LINE, &param);\n}\n"
  },
  {
    "path": "lib/libgpanel/open.c",
    "content": "/*\n * Device open and close routines.\n *\n * Copyright (C) 2015 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <unistd.h>\n#include <fcntl.h>\n#include <sys/gpanel.h>\n\nint _gpanel_fd = -1;\n\n/*\n * Open a graphics panel device.\n */\nint gpanel_open(const char *devname)\n{\n    _gpanel_fd = open(devname, O_RDWR);\n    if (_gpanel_fd < 0)\n        return -1;\n    return 0;\n}\n\n/*\n * Close gpanel device.\n */\nvoid gpanel_close(void)\n{\n    if (_gpanel_fd >= 0) {\n        close(_gpanel_fd);\n        _gpanel_fd = -1;\n    }\n}\n"
  },
  {
    "path": "lib/libgpanel/pixel.c",
    "content": "/*\n * Draw a single pixel.\n *\n * Copyright (C) 2015 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/ioctl.h>\n#include <sys/gpanel.h>\n\nvoid gpanel_pixel(int color, int x, int y)\n{\n    struct gpanel_pixel_t param;\n\n    param.color = color;\n    param.x = x;\n    param.y = y;\n    ioctl(_gpanel_fd, GPANEL_PIXEL, &param);\n}\n"
  },
  {
    "path": "lib/libgpanel/rect.c",
    "content": "/*\n * Draw a rectangle frame (no fill).\n *\n * Copyright (C) 2015 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/ioctl.h>\n#include <sys/gpanel.h>\n\nvoid gpanel_rect(int color, int x0, int y0, int x1, int y1)\n{\n    struct gpanel_rect_t param;\n\n    param.color = color;\n    param.x0 = x0;\n    param.y0 = y0;\n    param.x1 = x1;\n    param.y1 = y1;\n    ioctl(_gpanel_fd, GPANEL_RECT, &param);\n}\n"
  },
  {
    "path": "lib/libgpanel/text.c",
    "content": "/*\n * Draw a string.\n *\n * Copyright (C) 2015 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/ioctl.h>\n#include <sys/gpanel.h>\n\nvoid gpanel_text(const struct gpanel_font_t *font, int color, int background,\n    int x, int y, const char *text)\n{\n    struct gpanel_text_t param;\n\n    param.font = font;\n    param.color = color;\n    param.background = background;\n    param.x = x;\n    param.y = y;\n    param.text = text;\n    ioctl(_gpanel_fd, GPANEL_TEXT, &param);\n}\n"
  },
  {
    "path": "lib/libgpanel/text_width.c",
    "content": "/*\n * Compute a string width in pixels.\n *\n * Copyright (C) 2015 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <string.h>\n#include <sys/ioctl.h>\n#include <sys/gpanel.h>\n\n/*\n * Calculate a width of text output.\n * Handle both fixed and proportional fonts.\n * TODO: UTF8 decoding.\n */\nint gpanel_text_width(const struct gpanel_font_t *font, const char *text, int nchars)\n{\n    int width, c;\n\n    if (! nchars)\n        nchars = strlen (text);\n    if (! font->width) {\n        /* Fixed-width font. */\n        return nchars * font->maxwidth;\n    }\n\n    width = 0;\n    while (--nchars >= 0) {\n        c = (unsigned char) *text++;\n        if (c < font->firstchar || c >= font->firstchar + font->size)\n            c = font->defaultchar;\n        width += font->width[c - font->firstchar];\n    }\n    return width;\n}\n"
  },
  {
    "path": "lib/libicache/icache.ld",
    "content": "OUTPUT_FORMAT(\"elf32-tradlittlemips\")\nOUTPUT_FORMAT(\"elf32-tradlittlemips\")\nOUTPUT_ARCH(pic32mx)\n\nENTRY(_icstart_)\n\nMEMORY\n{\n  /* 96K internal CPU RAM */\n  cpu_ram   (rwx)  : ORIGIN = 0x7F008000, LENGTH = 0x18000\n\n  /* 512K, loaded on demand into instruction cache from executable file */\n  file_rom  (rx!w) : ORIGIN = 0x40000000, LENGTH = 0x80000\n}\n\nSECTIONS\n{\n  /* Code Sections */\n\n  /* !!! fix this ugliness with '.', 'ORIGIN(cpu_ram)' and 'ORIGIN(file_rom)' !!! */\n\n  . = ORIGIN(cpu_ram);\n\n\n  .ictext ALIGN(4):\n  {\n    *icache?.o(.text .stub .text.* .gnu.linkonce.t.*)\n    . = ALIGN(4);\n  } > cpu_ram\n\n  .startup : /* contains code */\n  {\n    KEEP (*(.startup))\n  } > cpu_ram\n\n\n  __icache_tmp__ = .;\n  . = ORIGIN(file_rom);\n\n\n  .text ALIGN(64): /* instruction cache uses 32-byte cache lines 32-bytes-aligned */\n  {\n    _text_begin = .;\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    KEEP (*(.text.*personality*))\n    *(.gnu.warning)\n    *(.mips16.fn.*)\n    *(.mips16.call.*)\n    . = ALIGN(64); /* instruction cache uses 32-byte cache lines 32-bytes-aligned */\n    _text_end = .;\n  } > file_rom = 0\n\n\n  . = __icache_tmp__;\n\n\n  /* Various initialization/finalization constructor/destructor sections */\n\n  .init : /* contains code, right? */\n  {\n    KEEP (*crti.o(.init))\n    KEEP (*crtbegin.o(.init))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o *crtn.o ).init))\n    KEEP (*crtend.o(.init))\n    KEEP (*crtn.o(.init))\n  } > cpu_ram\n\n  .fini : /* contains code, right? */\n  {\n    KEEP (*(.fini))\n  } > cpu_ram\n\n  .preinit_array : /* contains data, right? */\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } > cpu_ram\n\n  .init_array : /* contains data, right? */\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } > cpu_ram\n\n  .fini_array : /* contains data, right? */\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } > cpu_ram\n\n  .ctors : /* contains data */\n  {\n    /* gcc uses crtbegin.o to find the start of\n       the constructors, so we make sure it is\n       first.  Because this is a wildcard, it\n       doesn't matter if the user does not\n       actually link against crtbegin.o; the\n       linker won't look for a file to match a\n       wildcard.  The wildcard also means that it\n       doesn't matter which directory crtbegin.o\n       is in. */\n    KEEP (*crtbegin.o(.ctors))\n    KEEP (*crtbegin?.o(.ctors))\n    /* We don't want to include the .ctor section from\n       the crtend.o file until after the sorted ctors.\n       The .ctor section from the crtend file contains the\n       end of ctors marker and it must be last */\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))\n    KEEP (*(SORT(.ctors.*)))\n    KEEP (*(.ctors))\n  } > cpu_ram\n\n  .dtors : /* contains data */\n  {\n    KEEP (*crtbegin.o(.dtors))\n    KEEP (*crtbegin?.o(.dtors))\n    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))\n    KEEP (*(SORT(.dtors.*)))\n    KEEP (*(.dtors))\n  } > cpu_ram\n\n  .preinit_array : /* contains data, right? */\n  {\n    KEEP (*(.preinit_array))\n  } > cpu_ram\n\n  /* Data Sections */\n\n  /* Read-only sections */\n\n  /*\n   * Small initialized constant global and static data can be placed in the\n   * .sdata2 section.  This is different from .sdata, which contains small\n   * initialized non-constant global and static data.\n   */\n  .sdata2 ALIGN(4):\n  {\n    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)\n    . = ALIGN(4);\n  } > cpu_ram\n\n  /*\n   * Uninitialized constant global and static data (i.e., variables which will\n   * always be zero).  Again, this is different from .sbss, which contains\n   * small non-initialized, non-constant global and static data.\n   */\n  .sbss2 ALIGN(4):\n  {\n    *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)\n    . = ALIGN(4);\n  } > cpu_ram\n\n  .dbg_data (NOLOAD):\n  {\n    . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);\n  } > cpu_ram\n\n  /* Persistent data */\n  .persist ALIGN(4):\n  {\n    _persist_begin = .;\n    *(.persist .persist.*)\n    . = ALIGN(4);\n    _persist_end = .;\n  } > cpu_ram\n\n/* !!! .rodata moved from code sections !!! */\n  .rodata ALIGN(4):\n  {\n    *(.rodata .rodata.* .gnu.linkonce.r.*)\n    *(.rodata1)\n    . = ALIGN(4);\n  } > cpu_ram\n\n  _data_begin = .;\n  .data ALIGN(4):\n  {\n    *(.data .data.* .gnu.linkonce.d.*)\n    KEEP (*(.gnu.linkonce.d.*personality*))\n    *(.data1)\n    . = ALIGN(4);\n  } > cpu_ram\n\n  . = .;\n  _gp = ALIGN(16) + 0x7ff0;\n  .got ALIGN(4):\n  {\n     *(.got.plt) *(.got)\n  } > cpu_ram\n\n  /*\n   * We want the small data sections together, so single-instruction offsets\n   * can access them all, and initialized data all before uninitialized, so\n   * we can shorten the on-disk segment size.\n   */\n  .sdata ALIGN(4):\n  {\n    _sdata_begin = .;\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n    _sdata_end = .;\n  } > cpu_ram\n  .lit8 :\n  {\n    *(.lit8)\n  } > cpu_ram\n  .lit4 :\n  {\n    *(.lit4)\n  } > cpu_ram\n  . = ALIGN(4);\n  _data_end = .;\n\n  _bss_begin = .;\n  .sbss ALIGN(4):\n  {\n    _sbss_begin = .;\n    *(.dynsbss)\n    *(.sbss .sbss.* .gnu.linkonce.sb.*)\n    *(.scommon)\n    . = ALIGN(4);\n    _sbss_end = .;\n  } > cpu_ram\n\n  .bss ALIGN(4):\n  {\n    *(.dynbss)\n    *(.bss .bss.* .gnu.linkonce.b.*)\n    *(COMMON)\n    /*\n     * Align here to ensure that the .bss section occupies space up to\n     * _end.  Align after .bss to ensure correct alignment even if the\n     * .bss section disappears because there are no input sections.\n     */\n    . = ALIGN(4);\n  } > cpu_ram\n  . = ALIGN(4);\n  _bss_end = .;\n\n  _end = .;\n\n  /* The .pdr section belongs in the absolute section */\n  /DISCARD/ : { *(.pdr) }\n  /* We don't load .reginfo onto the target, so don't locate it\n   * in real memory\n   */\n  /DISCARD/ : { *(.reginfo) }\n\n  /* Stabs debugging sections. */\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  /* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0. */\n  /* DWARF 1 */\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  /* GNU DWARF 1 extensions */\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  /* DWARF 1.1 and DWARF 2 */\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  /* DWARF 2 */\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  /DISCARD/         : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  /DISCARD/         : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  /* SGI/MIPS DWARF 2 extensions */\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  /* DWARF 3 */\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }\n  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }\n  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }\n  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }\n  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }\n  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }\n  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }\n  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }\n  /DISCARD/ : { *(.MIPS.abiflags) }\n  /DISCARD/ : { *(.rel.dyn) }\n  /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }\n}\n"
  },
  {
    "path": "lib/libicache/icachec.c",
    "content": "/*\nCopyright (c) 2013, Alexey Frunze\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n1. Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer.\n2. Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\nANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\nANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nThe views and conclusions contained in the software and documentation are those\nof the authors and should not be interpreted as representing official policies,\neither expressed or implied, of the FreeBSD Project.\n*/\n\n/*****************************************************************************/\n/*                                                                           */\n/*                               MIPS icache                                 */\n/*                                                                           */\n/*****************************************************************************/\n\n// the For best performance, this file should be compiled using gcc's -O3 option.\n\n// Define this macro to enable statistics\n//#define STATS\n\n// Define this macro to do a more rigorous check\n// for invalid/unsupported instructions\n// (at the expense of performance, of course).\n//#define CHECK_INVALID_INSTR\n\n#define STATIC static\n\n// Rename non-static functions and variables\n// to prevent name collisions with other code\n// when compiling together with it.\n#define DoSysCall       _icDoSysCall_\n#define main            _icmain_\n#define Regs            _icRegs_\n#define HostRegs        _icHostRegs_\n\ntypedef unsigned char uchar, uint8;\ntypedef signed char schar, int8;\ntypedef unsigned short ushort, uint16;\ntypedef short int16;\ntypedef unsigned uint, uint32, size_t;\ntypedef int int32, ssize_t, off_t;\ntypedef unsigned long ulong;\ntypedef long long longlong, int64;\ntypedef unsigned long long ulonglong, uint64;\n\n#define C_ASSERT(expr) extern char CAssertExtern[(expr)?1:-1]\n\n//C_ASSERT(CHAR_BIT == 8);\nC_ASSERT(sizeof(int) == 4);\nC_ASSERT(sizeof(long) == 4);\nC_ASSERT(sizeof(longlong) == 8);\nC_ASSERT(sizeof(void*) == 4);\nC_ASSERT(sizeof(void(*)()) == 4);\nC_ASSERT(sizeof(size_t) == 4);\nC_ASSERT(sizeof(ssize_t) == 4);\nC_ASSERT(sizeof(off_t) == 4);\nC_ASSERT(sizeof(uint16) == 2);\nC_ASSERT(sizeof(uint32) == 4);\nC_ASSERT(sizeof(uint64) == 8);\n\n\n#pragma pack(push,1)\n\ntypedef struct\n{\n  uint32 a_magic;   /* magic number */\n#define OMAGIC 0407 /* old impure format */\n\n  uint32 a_text;    /* size of text segment */\n  uint32 a_data;    /* size of initialized data */\n  uint32 a_bss;     /* size of uninitialized data */\n  uint32 a_reltext; /* size of text relocation info */\n  uint32 a_reldata; /* size of data relocation info */\n  uint32 a_syms;    /* size of symbol table */\n  uint32 a_entry;   /* entry point */\n} AoutHdr;\n\n#pragma pack(pop)\n\nC_ASSERT(sizeof(AoutHdr) == 32);\n\n\nstatic inline\nvoid* memset(void* dst, int ch, size_t size)\n{\n  unsigned char *p = dst;\n  while (size--)\n    *p++ = ch;\n  return dst;\n}\n\n// flags for RetroBSD's open():\n#define O_RDONLY 0x0000\n#define O_WRONLY 0x0001\n#define O_RDWR   0x0002\n#define O_APPEND 0x0008\n#define O_CREAT  0x0200\n#define O_TRUNC  0x0400\n#define O_TEXT   0x0000\n#define O_BINARY 0x0000\n\n// flags for RetroBSD's lseek():\n#define SEEK_SET 0\n#define SEEK_CUR 1\n#define SEEK_END 2\n\nstatic\nvoid exit(int code)\n{\n  asm volatile (\"move $4, %0\\n\"\n                \"syscall 1\" // SYS_exit\n                :\n                : \"r\" (code)\n                : \"$2\", \"$4\");\n}\n\nstatic\nint open(const char* name, int oflags)\n{\n  int handle;\n  asm volatile (\"move $4, %1\\n\"\n                \"move $5, %2\\n\"\n                \"syscall 5\\n\" // SYS_open\n                \"nop\\n\"\n                \"nop\\n\"\n                \"move %0, $2\\n\"\n                : \"=r\" (handle)\n                : \"r\" (name), \"r\" (oflags)\n                : \"$2\", \"$4\", \"$5\");\n  return handle;\n}\n\nstatic\nssize_t read(int handle, void* buf, size_t size)\n{\n  ssize_t sz;\n  asm volatile (\"move $4, %1\\n\"\n                \"move $5, %2\\n\"\n                \"move $6, %3\\n\"\n                \"syscall 3\\n\" // SYS_read\n                \"nop\\n\"\n                \"nop\\n\"\n                \"move %0, $2\\n\"\n                : \"=r\" (sz)\n                : \"r\" (handle), \"r\" (buf), \"r\" (size)\n                : \"$2\", \"$4\", \"$5\", \"$6\", \"memory\");\n  return sz;\n}\n\nstatic\nssize_t write(int handle, const void* buf, size_t size)\n{\n  ssize_t sz;\n  asm volatile (\"move $4, %1\\n\"\n                \"move $5, %2\\n\"\n                \"move $6, %3\\n\"\n                \"syscall 4\\n\" // SYS_write\n                \"nop\\n\"\n                \"nop\\n\"\n                \"move %0, $2\\n\"\n                : \"=r\" (sz)\n                : \"r\" (handle), \"r\" (buf), \"r\" (size)\n                : \"$2\", \"$4\", \"$5\", \"$6\", \"memory\"); // WTF? I shouldn't need \"memory\" here !!!\n  return sz;\n}\n\nstatic\noff_t lseek(int handle, off_t pos, int whence)\n{\n  off_t p;\n  asm volatile (\"move $4, %1\\n\"\n                \"move $5, %2\\n\"\n                \"move $6, %3\\n\"\n                \"syscall 19\\n\" // SYS_lseek\n                \"nop\\n\"\n                \"nop\\n\"\n                \"move %0, $2\\n\"\n                : \"=r\" (p)\n                : \"r\" (handle), \"r\" (pos), \"r\" (whence)\n                : \"$2\", \"$4\", \"$5\", \"$6\");\n  return p;\n}\n\n#if 0\n// close() is unused. We rely on the system to close\n// all files/handles on process termination.\nstatic\nint close(int handle)\n{\n  int err;\n  asm volatile (\"move $4, %1\\n\"\n                \"syscall 6\\n\" // SYS_close\n                \"nop\\n\"\n                \"nop\\n\"\n                \"move %0, $2\\n\"\n                : \"=r\" (err)\n                : \"r\" (handle)\n                : \"$2\", \"$4\");\n  return err;\n}\n#endif\n\nstatic\nvoid printchr(int ch)\n{\n  char c = ch;\n  write(1, &c, 1);\n}\n\nstatic\nvoid printstr(const char* s)\n{\n  while (*s != '\\0')\n    write(1, s++, 1);\n}\n\n#ifdef STATS\nstatic\nvoid printdec(int n)\n{\n  unsigned un = n;\n  if (n < 0)\n  {\n    un = -un;\n    printchr('-');\n  }\n  if (un >= 10)\n    printdec(un / 10);\n  printchr('0' + un % 10);\n}\n\nstatic\nchar* Bin64ToDec(uint64 n)\n{\n  // log10(x) = log2(x) / log2(10) ~= log2(x) / 3.322\n  static char s[64 / 3 + 1 + 1];\n  char* p = s;\n  int i;\n\n  memset(s, '0', sizeof s - 1);\n  s[sizeof s - 1] = '\\0';\n\n  for (i = 0; i < 64; i++)\n  {\n    int j, carry;\n\n    // Extract the most significant bit of n into carry\n    carry = (n >> 63) & 1;\n    // Shift n left\n    n <<= 1;\n\n    // Add s[] to itself in decimal, doubling it,\n    // and add carry to it\n    for (j = sizeof s - 2; j >= 0; j--)\n    {\n      s[j] += s[j] - '0' + carry;\n\n      carry = s[j] > '9';\n\n      if (carry)\n        s[j] -= 10;\n    }\n  }\n\n  while ((*p == '0') && (p < &s[sizeof s - 2]))\n    p++;\n\n  return p;\n}\n\nstatic\nvoid printdec64(int64 n)\n{\n  uint64 un = n;\n  if (n < 0)\n  {\n    un = -un;\n    printchr('-');\n  }\n  printstr(Bin64ToDec(un));\n}\n#endif\n\nstatic\nvoid printhex(unsigned n)\n{\n  int i;\n  for (i = 0; i < 8; i++)\n    printchr(\"0123456789ABCDEF\"[(n >> 28) & 15]), n <<= 4;\n}\n\n#ifdef STATS\nuint64 EmulateCnt = 0;\nuint64 CacheHits = 0;\nuint64 CacheHits2 = 0;\nuint64 CacheMisses = 0;\n#endif\n\n\n#define REG_GP 28\n#define REG_SP 29\n#define REG_RA 31\n#define REG_LO 32\n#define REG_HI 33\n#define REG_PC 34\nuint32 Regs[32 + 3];\nuint32 HostRegs[32 + 3];\n\n\n#define CACHE_BYTES_PER_INSTR  4\n#ifndef CACHE_INSTRS_PER_ENTRY\n#define CACHE_INSTRS_PER_ENTRY 8\n#endif\n#define CACHE_BYTES_PER_ENTRY  (CACHE_BYTES_PER_INSTR * CACHE_INSTRS_PER_ENTRY)\n\n#ifndef CACHE_ENTRIES_PER_WAY\n#define CACHE_ENTRIES_PER_WAY  64\n#endif\n#ifndef CACHE_WAYS\n#define CACHE_WAYS             4\n#endif\n#define CACHE_ENTRIES_TOTAL    (CACHE_ENTRIES_PER_WAY * CACHE_WAYS)\n\n#define CACHE_SIZE             (CACHE_BYTES_PER_ENTRY * CACHE_ENTRIES_TOTAL)\n\nSTATIC uint32 Cache[CACHE_ENTRIES_PER_WAY][CACHE_WAYS][CACHE_INSTRS_PER_ENTRY];\nSTATIC uint32 CacheTagAndValid[CACHE_ENTRIES_PER_WAY][CACHE_WAYS];\n\nSTATIC int CachedCnt = 0;\nSTATIC uint32* CachedInstr = &Cache[0][0][0];\n\n\nextern void _icstart_(int argc, char** argv, char** env);\nSTATIC void Emulate(void);\n\nSTATIC int ExeHandle = -1;\nSTATIC uint32 ExeOffs = 0;\n\nint main(int argc, char** argv, char** env)\n{\n  AoutHdr aoutHdr;\n\n  if ((ExeHandle = open(argv[0], O_BINARY | O_RDONLY)) < 0)\n  {\n    printstr(\"Can't open \"); printstr(argv[0]); printchr('\\n');\n    exit(-1);\n  }\n\n  if (read(ExeHandle, &aoutHdr, sizeof aoutHdr) != sizeof aoutHdr)\n  {\n    printstr(\"Can't read \"); printstr(argv[0]); printchr('\\n');\n    exit(-1);\n  }\n\n  if (aoutHdr.a_magic != OMAGIC)\n  {\n    printstr(argv[0]); printstr(\" is not an a.out file\\n\");\n    exit(-1);\n  }\n\n  ExeOffs = sizeof aoutHdr + aoutHdr.a_text + aoutHdr.a_data;\n\n  memset(CacheTagAndValid, 0xFF, sizeof CacheTagAndValid); // invalidate cache\n  Regs[4] = argc;\n  Regs[5] = (uint32)argv;\n  Regs[6] = (uint32)env;\n  // Regs[REG_SP] = ...; // _icstart() has done this\n  // Regs[REG_GP] = (uint32)&_gp; // _start() will do this if needed\n  Regs[REG_PC] = (uint32)&_icstart_;\n  Emulate(); // isn't supposed to return...\n  exit(-1); // ... but let's exit explicitly just in case\n  return -1;\n}\n\nextern const char _text_begin;\nextern const char _text_end;\n\nSTATIC inline\nuint32 FetchProgramWord(uint32 Addr)\n{\n  uint32 ofs, idx, tag, way;\n\n  if (CachedCnt > 0)\n  {\n    CachedCnt--;\n    // Cache hit\n#ifdef STATS\n    CacheHits++;\n    CacheHits2++;\n#endif\n    return *++CachedInstr;\n  }\n\n  if (Addr < (uint32)&_text_begin ||\n      Addr >= (uint32)&_text_end)\n  {\n    CachedCnt = 0;\n    CachedInstr = (uint32*)Addr;\n    return *CachedInstr;\n  }\n\n  ofs = Addr % CACHE_BYTES_PER_ENTRY / CACHE_BYTES_PER_INSTR;\n  idx = Addr / CACHE_BYTES_PER_ENTRY % CACHE_ENTRIES_PER_WAY;\n  tag = Addr / CACHE_BYTES_PER_ENTRY / CACHE_ENTRIES_PER_WAY;\n  for (way = 0; way < CACHE_WAYS; way++)\n  {\n    if (CacheTagAndValid[idx][way] == tag)\n    {\n      // Cache hit\n#ifdef STATS\n      CacheHits++;\n#endif\n      CachedCnt = CACHE_INSTRS_PER_ENTRY - 1 - ofs;\n      CachedInstr = &Cache[idx][way][ofs];\n      return *CachedInstr;\n    }\n  }\n\n  // Cache miss\n#ifdef STATS\n  CacheMisses++;\n#endif\n\n  for (way = 0; way < CACHE_WAYS; way++)\n  {\n    if (CacheTagAndValid[idx][way] & 0x80000000)\n    {\n      // Use an invalid entry\n      goto lreuse;\n    }\n  }\n\n  // Reuse a valid entry (need to choose one for eviction and refill,\n  // preferably not penalizing the same entry over and over again)\n  {\n    static uint32 w = CACHE_WAYS - 1;\n    w = (w + 1) % CACHE_WAYS; // pseudo-LRU\n    way = w;\n  }\n\nlreuse:\n\n  if (lseek(ExeHandle,\n            ExeOffs + (Addr / CACHE_BYTES_PER_ENTRY * CACHE_BYTES_PER_ENTRY - (uint32)&_text_begin),\n            SEEK_SET) < 0 ||\n      read(ExeHandle, Cache[idx][way], CACHE_BYTES_PER_ENTRY) != CACHE_BYTES_PER_ENTRY)\n  {\n    printstr(\"\\nCan't read into the cache from the executable file\\n\");\n    exit(-1);\n  }\n\n  CacheTagAndValid[idx][way] = tag;\n\n  CachedCnt = CACHE_INSTRS_PER_ENTRY - 1 - ofs;\n  CachedInstr = &Cache[idx][way][ofs];\n  return *CachedInstr;\n}\n\nextern int DoSysCall(uint32 instr);\n\n#ifdef STATS\nSTATIC\nint DoSysCall2(uint32 instr)\n{\n  uint32 code = (instr >> 6) & 0xFFFFF;\n\n  // intercept exit() syscall\n  if ((code == 0 && Regs[2] == 10) || // SPIM's exit()\n      (code == /*SYS_exit*/1)) // RetroBSD's exit()\n  {\n    uint32 idx, way, used = 0;\n    for (idx = 0; idx < CACHE_ENTRIES_PER_WAY; idx++)\n      for (way = 0; way < CACHE_WAYS; way++)\n        used += CacheTagAndValid[idx][way] < 0x80000000;\n    printstr(\"\\n\"); printdec64(EmulateCnt); printstr(\" instruction(s) emulated\\n\");\n    printdec((int)used); printchr('/'); printdec(CACHE_ENTRIES_TOTAL); printstr(\" cache entries used\\n\");\n    printdec64(CacheHits); printchr('(');\n    printdec64(CacheHits2); printstr(\")/\");\n    printdec64(CacheMisses); printstr(\" cache hits(hits2)/misses\\n\");\n  }\n  return DoSysCall(instr);\n}\n#undef DoSysCall\n#define DoSysCall DoSysCall2\n#endif\n\nstatic inline uint8 ReadByte(uint32 Addr)\n{\n  return *(uint8*)Addr;\n}\nstatic inline void WriteByte(uint32 Addr, uint8 Val)\n{\n  *(uint8*)Addr = Val;\n}\n\nstatic inline uint16 ReadHalfWord(uint32 Addr)\n{\n  return *(uint16*)Addr;\n}\nstatic inline void WriteHalfWord(uint32 Addr, uint16 Val)\n{\n  *(uint16*)Addr = Val;\n}\n\nstatic inline uint32 ReadWord(uint32 Addr)\n{\n  return *(uint32*)Addr;\n}\nstatic inline void WriteWord(uint32 Addr, uint32 Val)\n{\n  *(uint32*)Addr = Val;\n}\n\n/*\n  Supported instructions:\n\n    add, addi, addiu, addu, and, andi,\n    bal, beq, beql, bgez, bgezal, bgezall,\n    bgezl, bgtz, bgtzl, blez, blezl, bltz,\n    bltzal, bltzall, bltzl, bne, bnel, break,\n    clo, clz,\n    div, divu,\n    ext,\n    ins,\n    j, jal, jalr, jr,\n    lb, lbu, lh, lhu, lui, lw, lwl, lwr,\n    madd, maddu, mfhi, mflo, movn, movz, msub,\n    msubu, mthi, mtlo, mul, mult, multu,\n    nop, nor,\n    or, ori,\n    rotr, rotrv,\n    sb, seb, seh, sh, sll, sllv, slt, slti, sltiu,\n    sltu, sra, srav, srl, srlv, sub, subu, sw,\n    swl, swlr, syscall,\n    teq, teqi, tge, tgei, tgeiu, tgeu, tlt, tlti,\n    tltiu, tltu, tne, tnei,\n    wsbh,\n    xor, xori\n\n  Unsupported instructions:\n\n    bc2f, bc2fl, bc2t, bc2tl,\n    cache, cfc2, cop0, cop2, ctc2,\n    deret, di,\n    ehb, ei, eret,\n    jalr.hb, jr.hb,\n    ll, lwc2,\n    mfc0, mfc2, mtc0, mtc2, mthc2,\n    pref,\n    rdhwr, rdpgpr,\n    sc, sdbbp, ssnop, swc2, sync, synci,\n    wait, wrpgpr\n*/\n\nSTATIC void DoBreak(uint32 instr);\nSTATIC void DoTrap(uint32 instr);\nSTATIC void DoOverflow(void);\nSTATIC void DoInvalidInstruction(uint32 instr);\n\nSTATIC\nuint32 CountLeadingZeroes(uint32 n)\n{\n#if 0\n  uint32 c = 0;\n  if (n == 0)\n    return 32;\n  while (n < 0x80000000)\n    n <<= 1, c++;\n#else\n  uint32 c;\n  asm volatile(\"clz %0, %1\" : \"=r\" (c) : \"r\" (n));\n#endif\n  return c;\n}\n\nSTATIC\nuint32 CountLeadingOnes(uint32 n)\n{\n#if 0\n  uint32 c = 0;\n  while (n >= 0x80000000)\n    n <<= 1, c++;\n#else\n  uint32 c;\n  asm volatile(\"clo %0, %1\" : \"=r\" (c) : \"r\" (n));\n#endif\n  return c;\n}\n\nSTATIC\nuint32 ShiftRightArithm(uint32 n, uint32 c)\n{\n#if 0\n  uint32 s = -(n >> 31);\n  n >>= c;\n  n |= s << (31 - c) << 1;\n  return n;\n#else\n  uint32 nn;\n  asm volatile(\"srav %0, %1, %2\" : \"=r\" (nn) : \"r\" (n), \"r\" (c));\n  return nn;\n#endif\n}\n\nSTATIC\nuint32 RotateRight(uint32 n, uint32 c)\n{\n#if 0\n  return (n >> c) | (n << (31 - c) << 1);\n#else\n  uint32 nn;\n  asm volatile(\"rotrv %0, %1, %2\" : \"=r\" (nn) : \"r\" (n), \"r\" (c));\n  return nn;\n#endif\n}\n\nSTATIC\nvoid Emulate(void)\n{\n  int delaySlot = 0;\n  uint32 postDelaySlotPc = 0;\n  uint32 instr = 0;\n\n  for (;;)\n  {\n    const uint32 pc = Regs[REG_PC];\n    uint32 nextPc = pc + 4;\n    /*const uint32*/ instr = FetchProgramWord(pc);\n#if 0\n    const uint32 op = instr >> 26;\n    const uint32 r1 = (instr >> 21) & 0x1F;\n    const uint32 r2 = (instr >> 16) & 0x1F;\n    const uint32 r3 = (instr >> 11) & 0x1F;\n    const uint32 shft = (instr >> 6) & 0x1F;\n    const uint32 fxn = instr & 0x3F;\n    const uint32 imm16 = instr & 0xFFFF;\n    const uint32 simm16 = (int16)imm16;\n    const uint32 jtgt = instr & 0x3FFFFFF;\n#else\n#define op     (instr >> 26)\n#define r1     ((instr >> 21) & 0x1F)\n#define r2     ((instr >> 16) & 0x1F)\n#define r3     ((instr >> 11) & 0x1F)\n#define shft   ((instr >> 6) & 0x1F)\n#define fxn    (instr & 0x3F)\n#define imm16  (instr & 0xFFFF)\n#define simm16 ((int16)imm16)\n#define jtgt   (instr & 0x3FFFFFF)\n#endif\n\n    switch (op)\n    {\n    case 0:\n      switch (fxn)\n      {\n      case 0:\n#ifdef CHECK_INVALID_INSTR\n        if (r1)\n          goto lInvalidInstruction;\n#endif\n        Regs[r3] = Regs[r2] << shft;\n        break; // sll d,w,shft\n      case 2:\n        switch (r1)\n        {\n        case 0: Regs[r3] = Regs[r2] >> shft; break; // srl d,w,shft\n        case 1: Regs[r3] = RotateRight(Regs[r2], shft); break; // rotr d,w,shft\n        default: goto lInvalidInstruction;\n        }\n        break;\n      case 3:\n#ifdef CHECK_INVALID_INSTR\n        if (r1)\n          goto lInvalidInstruction;\n#endif\n        Regs[r3] = ShiftRightArithm(Regs[r2], shft);\n        break; // sra d,w,shft\n      case 4:\n#ifdef CHECK_INVALID_INSTR\n        if (shft)\n          goto lInvalidInstruction;\n#endif\n        Regs[r3] = Regs[r2] << (Regs[r1] & 31);\n        break; // sllv d,w,s\n      case 6:\n        switch (shft)\n        {\n        case 0: Regs[r3] = Regs[r2] >> (Regs[r1] & 31); break; // srlv d,w,s\n        case 1: Regs[r3] = RotateRight(Regs[r2], Regs[r1] & 31); break; // rotrv d,w,s\n        default: goto lInvalidInstruction;\n        }\n        break;\n      case 7:\n#ifdef CHECK_INVALID_INSTR\n        if (shft)\n          goto lInvalidInstruction;\n#endif\n        Regs[r3] = ShiftRightArithm(Regs[r2], Regs[r1] & 31);\n        break; // srav d,w,s\n      case 8:\n#ifdef CHECK_INVALID_INSTR\n        if (r2 | r3 | shft)\n          goto lInvalidInstruction;\n#endif\n        nextPc = Regs[r1]; delaySlot = 1;\n        break; // jr s\n      case 9:\n#ifdef CHECK_INVALID_INSTR\n        if (r2 | shft)\n          goto lInvalidInstruction;\n#endif\n        Regs[r3] = nextPc + 4; nextPc = Regs[r1]; delaySlot = 1;\n        break; // jalr [d,] s\n      case 10:\n#ifdef CHECK_INVALID_INSTR\n        if (shft)\n          goto lInvalidInstruction;\n#endif\n        if (Regs[r2] == 0) Regs[r3] = Regs[r1];\n        break; // movz d,s,t\n      case 11:\n#ifdef CHECK_INVALID_INSTR\n        if (shft)\n          goto lInvalidInstruction;\n#endif\n        if (Regs[r2]) Regs[r3] = Regs[r1];\n        break; // movn d,s,t\n      case 12:\n        {\n          // RetroBSD may advance PC on returning from a syscall handler,\n          // skipping 2 instructions that follow the syscall instruction.\n          // Those 2 instructions typically set C's errno variable and\n          // are either executed on error or skipped on success.\n          // Account for this peculiarity.\n          uint32 skip = DoSysCall(instr);\n          nextPc += skip * 4; CachedCnt -= skip; CachedInstr += skip;\n        }\n        break; // syscall code\n      case 13: goto lBreak; break; // break code\n      case 16:\n#ifdef CHECK_INVALID_INSTR\n        if (r1 | r2 | shft)\n          goto lInvalidInstruction;\n#endif\n        Regs[r3] = Regs[REG_HI];\n        break; // mfhi d\n      case 17:\n#ifdef CHECK_INVALID_INSTR\n        if (r2 | r3 | shft)\n          goto lInvalidInstruction;\n#endif\n        Regs[REG_HI] = Regs[r1];\n        break; // mthi s\n      case 18:\n#ifdef CHECK_INVALID_INSTR\n        if (r1 | r2 | shft)\n          goto lInvalidInstruction;\n#endif\n        Regs[r3] = Regs[REG_LO];\n        break; // mflo d\n      case 19:\n#ifdef CHECK_INVALID_INSTR\n        if (r2 | r3 | shft)\n          goto lInvalidInstruction;\n#endif\n        Regs[REG_LO] = Regs[r1];\n        break; // mtlo s\n      case 24:\n#ifdef CHECK_INVALID_INSTR\n        if (r3 | shft)\n          goto lInvalidInstruction;\n#endif\n        {\n          int64 p = (int64)(int32)Regs[r1] * (int32)Regs[r2];\n          Regs[REG_LO] = (uint32)p;\n          Regs[REG_HI] = (uint32)(p >> 32);\n        }\n        break; // mult s,t\n      case 25:\n#ifdef CHECK_INVALID_INSTR\n        if (r3 | shft)\n          goto lInvalidInstruction;\n#endif\n        {\n          uint64 p = (uint64)Regs[r1] * Regs[r2];\n          Regs[REG_LO] = (uint32)p;\n          Regs[REG_HI] = (uint32)(p >> 32);\n        }\n        break; // multu s,t\n      case 26:\n#ifdef CHECK_INVALID_INSTR\n        if (r3 | shft)\n          goto lInvalidInstruction;\n#endif\n        if (!(Regs[r2] == 0 || (Regs[r1] == 0x80000000 && Regs[r2] == 0xFFFFFFFF)))\n          Regs[REG_LO] = (int32)Regs[r1] / (int32)Regs[r2], Regs[REG_HI] = (int32)Regs[r1] % (int32)Regs[r2];\n        break; // div s,t\n      case 27:\n#ifdef CHECK_INVALID_INSTR\n        if (r3 | shft)\n          goto lInvalidInstruction;\n#endif\n        if (Regs[r2])\n          Regs[REG_LO] = Regs[r1] / Regs[r2], Regs[REG_HI] = Regs[r1] % Regs[r2];\n        break; // divu s,t\n      case 32:\n#ifdef CHECK_INVALID_INSTR\n        if (shft)\n          goto lInvalidInstruction;\n#endif\n        {\n          uint32 sum = Regs[r1] + Regs[r2];\n          if (((Regs[r1] ^ Regs[r2] ^ 0x80000000) & 0x80000000) &&\n              ((sum ^ Regs[r1]) & 0x80000000))\n            goto lOverflow;\n          Regs[r3] = sum;\n        }\n        break; // add d,s,t\n      case 33:\n#ifdef CHECK_INVALID_INSTR\n        if (shft)\n          goto lInvalidInstruction;\n#endif\n        Regs[r3] = Regs[r1] + Regs[r2];\n        break; // addu d,s,t\n      case 34:\n#ifdef CHECK_INVALID_INSTR\n        if (shft)\n          goto lInvalidInstruction;\n#endif\n        {\n          uint32 diff = Regs[r1] - Regs[r2];\n          if (((Regs[r1] ^ Regs[r2]) & 0x80000000) &&\n              ((diff ^ Regs[r1]) & 0x80000000))\n            goto lOverflow;\n          Regs[r3] = diff;\n        }\n        break; // sub d,s,t\n      case 35:\n#ifdef CHECK_INVALID_INSTR\n        if (shft)\n          goto lInvalidInstruction;\n#endif\n        Regs[r3] = Regs[r1] - Regs[r2];\n        break; // subu d,s,t\n      case 36:\n#ifdef CHECK_INVALID_INSTR\n        if (shft)\n          goto lInvalidInstruction;\n#endif\n        Regs[r3] = Regs[r1] & Regs[r2];\n        break; // and d,s,t\n      case 37:\n#ifdef CHECK_INVALID_INSTR\n        if (shft)\n          goto lInvalidInstruction;\n#endif\n        Regs[r3] = Regs[r1] | Regs[r2];\n        break; // or d,s,t\n      case 38:\n#ifdef CHECK_INVALID_INSTR\n        if (shft)\n          goto lInvalidInstruction;\n#endif\n        Regs[r3] = Regs[r1] ^ Regs[r2];\n        break; // xor d,s,t\n      case 39:\n#ifdef CHECK_INVALID_INSTR\n        if (shft)\n          goto lInvalidInstruction;\n#endif\n        Regs[r3] = ~(Regs[r1] | Regs[r2]);\n        break; // nor d,s,t\n      case 42:\n#ifdef CHECK_INVALID_INSTR\n        if (shft)\n          goto lInvalidInstruction;\n#endif\n        Regs[r3] = (int32)Regs[r1] < (int32)Regs[r2];\n        break; // slt d,s,t\n      case 43:\n#ifdef CHECK_INVALID_INSTR\n        if (shft)\n          goto lInvalidInstruction;\n#endif\n        Regs[r3] = Regs[r1] < Regs[r2];\n        break; // sltu d,s,t\n\n      case 48: if ((int32)Regs[r1] >= (int32)Regs[r2]) goto lTrap; break; // tge s,t\n      case 49: if (Regs[r1] >= Regs[r2]) goto lTrap; break; // tgeu s,t\n      case 50: if ((int32)Regs[r1] < (int32)Regs[r2]) goto lTrap; break; // tlt s,t\n      case 51: if (Regs[r1] < Regs[r2]) goto lTrap; break; // tltu s,t\n      case 52: if (Regs[r1] == Regs[r2]) goto lTrap; break; // teq s,t\n      case 53: if (Regs[r1] != Regs[r2]) goto lTrap; break; // tne s,t\n\n      default: goto lInvalidInstruction;\n      }\n      break;\n\n    case 1:\n      switch (r2)\n      {\n      case 0: if ((int32)Regs[r1] < 0) nextPc += simm16 << 2, delaySlot = 1; break; // bltz s,p\n      case 1: if ((int32)Regs[r1] >= 0) nextPc += simm16 << 2, delaySlot = 1; break; // bgez s,p\n      case 2: if ((int32)Regs[r1] < 0) nextPc += simm16 << 2, delaySlot = 1; else nextPc += 4, CachedCnt--, ++CachedInstr; break; // bltzl s,p\n      case 3: if ((int32)Regs[r1] >= 0) nextPc += simm16 << 2, delaySlot = 1; else nextPc += 4, CachedCnt--, ++CachedInstr; break; // bgezl s,p\n\n      case 8: if ((int32)Regs[r1] >= (int32)simm16) goto lTrap; break; // tgei s,j\n      case 9: if (Regs[r1] >= (uint32)simm16) goto lTrap; break; // tgeiu s,j\n      case 10: if ((int32)Regs[r1] < (int32)simm16) goto lTrap; break; // tlti s,j\n      case 11: if (Regs[r1] < (uint32)simm16) goto lTrap; break; // tltiu s,j\n      case 12: if (Regs[r1] == (uint32)simm16) goto lTrap; break; // teqi s,j\n      case 14: if (Regs[r1] != (uint32)simm16) goto lTrap; break; // tnei s,j\n\n      case 16: Regs[REG_RA] = nextPc + 4; if ((int32)Regs[r1] < 0) nextPc += simm16 << 2, delaySlot = 1; break; // bltzal s,p\n      case 17: Regs[REG_RA] = nextPc + 4; if ((int32)Regs[r1] >= 0) nextPc += simm16 << 2, delaySlot = 1; break; // bgezal s,p\n      case 18: Regs[REG_RA] = nextPc + 4; if ((int32)Regs[r1] < 0) nextPc += simm16 << 2, delaySlot = 1; else nextPc += 4, CachedCnt--, ++CachedInstr; break; // bltzall s,p\n      case 19: Regs[REG_RA] = nextPc + 4; if ((int32)Regs[r1] >= 0) nextPc += simm16 << 2, delaySlot = 1; else nextPc += 4, CachedCnt--, ++CachedInstr; break; // bgezall s,p\n\n      default: goto lInvalidInstruction;\n      }\n      break;\n\n    case 2: nextPc = (pc & 0xF0000000) | (jtgt << 2); delaySlot = 1; break; // j target\n    case 3: Regs[REG_RA] = nextPc + 4; nextPc = (pc & 0xF0000000) | (jtgt << 2); delaySlot = 1; break; // jal target\n\n    case 4: if (Regs[r1] == Regs[r2]) nextPc += simm16 << 2, delaySlot = 1; break; // beq s,t,p\n    case 5: if (Regs[r1] != Regs[r2]) nextPc += simm16 << 2, delaySlot = 1; break; // bne s,t,p\n    case 6:\n#ifdef CHECK_INVALID_INSTR\n      if (r2)\n        goto lInvalidInstruction;\n#endif\n      if ((int32)Regs[r1] <= 0) nextPc += simm16 << 2, delaySlot = 1; break; // blez s,p\n    case 7:\n#ifdef CHECK_INVALID_INSTR\n      if (r2)\n        goto lInvalidInstruction;\n#endif\n      if ((int32)Regs[r1] > 0) nextPc += simm16 << 2, delaySlot = 1; break; // bgtz s,p\n\n    case 8:\n      {\n        uint32 sum = Regs[r1] + simm16;\n        if (((Regs[r1] ^ simm16 ^ 0x80000000) & 0x80000000) &&\n            ((sum ^ Regs[r1]) & 0x80000000))\n          goto lOverflow;\n        Regs[r2] = sum;\n      }\n      break; // addi d,s,const\n    case 9: Regs[r2] = Regs[r1] + simm16; break; // addiu d,s,const\n    case 10: Regs[r2] = (int32)Regs[r1] < (int32)simm16; break; // slti d,s,const\n    case 11: Regs[r2] = Regs[r1] < (uint32)simm16; break; // sltiu d,s,const\n    case 12: Regs[r2] = Regs[r1] & imm16; break; // andi d,s,const\n    case 13: Regs[r2] = Regs[r1] | imm16; break; // ori d,s,const\n    case 14: Regs[r2] = Regs[r1] ^ imm16; break; // xori d,s,const\n    case 15:\n#ifdef CHECK_INVALID_INSTR\n      if (r1)\n        goto lInvalidInstruction;\n#endif\n      Regs[r2] = imm16 << 16; break; // lui d,const\n\n    case 20: if (Regs[r1] == Regs[r2]) nextPc += simm16 << 2, delaySlot = 1; else nextPc += 4, CachedCnt--, ++CachedInstr; break; // beql s,t,p\n    case 21: if (Regs[r1] != Regs[r2]) nextPc += simm16 << 2, delaySlot = 1; else nextPc += 4, CachedCnt--, ++CachedInstr; break; // bnel s,t,p\n    case 22:\n#ifdef CHECK_INVALID_INSTR\n      if (r2)\n        goto lInvalidInstruction;\n#endif\n      if ((int32)Regs[r1] <= 0) nextPc += simm16 << 2, delaySlot = 1; else nextPc += 4, CachedCnt--, ++CachedInstr; break; // blezl s,p\n    case 23:\n#ifdef CHECK_INVALID_INSTR\n      if (r2)\n        goto lInvalidInstruction;\n#endif\n      if ((int32)Regs[r1] > 0) nextPc += simm16 << 2, delaySlot = 1; else nextPc += 4, CachedCnt--, ++CachedInstr; break; // bgtzl s,p\n\n    case 28:\n#ifdef CHECK_INVALID_INSTR\n      if (shft)\n        goto lInvalidInstruction;\n#endif\n      switch (fxn)\n      {\n      case 0:\n#ifdef CHECK_INVALID_INSTR\n        if (r3)\n          goto lInvalidInstruction;\n#endif\n        {\n          int64 p = (int64)(int32)Regs[r1] * (int32)Regs[r2];\n          if (Regs[REG_LO] > 0xFFFFFFFF - (uint32)p)\n            Regs[REG_HI]++;\n          Regs[REG_LO] += (uint32)p;\n          Regs[REG_HI] += (uint32)(p >> 32);\n        }\n        break; // madd s,t\n      case 1:\n#ifdef CHECK_INVALID_INSTR\n        if (r3)\n          goto lInvalidInstruction;\n#endif\n        {\n          uint64 p = (uint64)Regs[r1] * Regs[r2];\n          if (Regs[REG_LO] > 0xFFFFFFFF - (uint32)p)\n            Regs[REG_HI]++;\n          Regs[REG_LO] += (uint32)p;\n          Regs[REG_HI] += (uint32)(p >> 32);\n        }\n        break; // maddu s,t\n      case 2: Regs[r3] = Regs[r1] * Regs[r2]; break; // mul d,s,t\n      case 4:\n#ifdef CHECK_INVALID_INSTR\n        if (r3)\n          goto lInvalidInstruction;\n#endif\n        {\n          int64 p = (int64)(int32)Regs[r1] * (int32)Regs[r2];\n          if (Regs[REG_LO] < (uint32)p)\n            Regs[REG_HI]--;\n          Regs[REG_LO] -= (uint32)p;\n          Regs[REG_HI] -= (uint32)(p >> 32);\n        }\n        break; // msub s,t\n      case 5:\n#ifdef CHECK_INVALID_INSTR\n        if (r3)\n          goto lInvalidInstruction;\n#endif\n        {\n          uint64 p = (uint64)Regs[r1] * Regs[r2];\n          if (Regs[REG_LO] < (uint32)p)\n            Regs[REG_HI]--;\n          Regs[REG_LO] -= (uint32)p;\n          Regs[REG_HI] -= (uint32)(p >> 32);\n        }\n        break; // msubu s,t\n\n      case 32:\n#ifdef CHECK_INVALID_INSTR\n        if (r1 != r2)\n          goto lInvalidInstruction;\n#endif\n        Regs[r3] = CountLeadingZeroes(Regs[r2]); break; // clz d,s\n      case 33:\n#ifdef CHECK_INVALID_INSTR\n        if (r1 != r2)\n          goto lInvalidInstruction;\n#endif\n        Regs[r3] = CountLeadingOnes(Regs[r2]); break; // clo d,s\n\n      default: goto lInvalidInstruction;\n      }\n      break;\n\n    case 31:\n      switch (fxn)\n      {\n      case 0:\n        if (shft + r3 <= 31)\n        {\n          uint size = r3 + 1;\n          uint32 mask = (0xFFFFFFFF >> (32 - size)) << shft;\n          Regs[r2] = (Regs[r1] & mask) >> shft;\n        }\n        break; // ext t,s,pos,sz\n      case 4:\n        if (r3 >= shft)\n        {\n          uint size = r3 - shft + 1;\n          uint32 mask = (0xFFFFFFFF >> (32 - size)) << shft;\n          Regs[r2] = (Regs[r2] & ~mask) | ((Regs[r1] << shft) & mask);\n        }\n        break; // ins t,s,pos,sz\n      case 32:\n#ifdef CHECK_INVALID_INSTR\n        if (r1)\n          goto lInvalidInstruction;\n#endif\n        switch (shft)\n        {\n        case 2: Regs[r3] = ((Regs[r2] & 0x00FF) << 8) |\n                           ((Regs[r2] & 0xFF00) >> 8) |\n                           ((Regs[r2] & 0x00FF0000) << 8) |\n                           ((Regs[r2] & 0xFF000000) >> 8); break; // wsbh d,t\n        case 16: Regs[r3] = (int8)Regs[r2]; break; // seb d,t\n        case 24: Regs[r3] = (int16)Regs[r2]; break; // seh d,t\n        default: goto lInvalidInstruction;\n        }\n        break;\n\n      default: goto lInvalidInstruction;\n      }\n      break;\n\n    case 32: Regs[r2] = (int8)ReadByte(Regs[r1] + simm16); break; // lb t,o(b)\n    case 33: Regs[r2] = (int16)ReadHalfWord(Regs[r1] + simm16); break; // lh t,o(b)\n    case 34:\n      {\n        uint32 v = ReadByte(Regs[r1] + simm16);\n        v = (v << 8) | ReadByte(Regs[r1] + simm16 - 1);\n        Regs[r2] = (Regs[r2] & 0xFFFF) | (v << 16);\n      }\n      break; // lwl t,o(b)\n    case 35: Regs[r2] = ReadWord(Regs[r1] + simm16); break; // lw t,o(b)\n    case 36: Regs[r2] = ReadByte(Regs[r1] + simm16); break; // lbu t,o(b)\n    case 37: Regs[r2] = ReadHalfWord(Regs[r1] + simm16); break; // lhu t,o(b)\n    case 38:\n      {\n        uint32 v = ReadByte(Regs[r1] + simm16);\n        v |= (uint32)ReadByte(Regs[r1] + simm16 + 1) << 8;\n        Regs[r2] = (Regs[r2] & 0xFFFF0000) | v;\n      }\n      break; // lwr t,o(b)\n\n    case 40: WriteByte(Regs[r1] + simm16, (uint8)Regs[r2]); break; // sb t,o(b)\n    case 41: WriteHalfWord(Regs[r1] + simm16, (uint16)Regs[r2]); break; // sh t,o(b)\n    case 42:\n      WriteByte(Regs[r1] + simm16, (uint8)(Regs[r2] >> 24));\n      WriteByte(Regs[r1] + simm16 - 1, (uint8)(Regs[r2] >> 16));\n      break; // swl t,o(b)\n    case 43: WriteWord(Regs[r1] + simm16, Regs[r2]); break; // sw t,o(b)\n    case 46:\n      WriteByte(Regs[r1] + simm16, (uint8)Regs[r2]);\n      WriteByte(Regs[r1] + simm16 + 1, (uint8)(Regs[r2] >> 8));\n      break; // swr t,o(b)\n\n    default:\n      goto lInvalidInstruction;\n    }\n\n    Regs[0] = 0;\n\n    Regs[REG_PC] = nextPc;\n\n    if (delaySlot)\n    {\n      if (delaySlot == 1)\n      {\n         postDelaySlotPc = nextPc;\n         Regs[REG_PC] = pc + 4;\n         delaySlot = 2;\n      }\n      else\n      {\n         Regs[REG_PC] = postDelaySlotPc;\n         delaySlot = 0;\n         CachedCnt = 0;\n      }\n    }\n\n#ifdef STATS\n    EmulateCnt++;\n#endif\n  } // for (;;)\n\nlBreak:\n  DoBreak(instr);\n  return;\n\nlTrap:\n  DoTrap(instr);\n  return;\n\nlOverflow:\n  DoOverflow();\n  return;\n\nlInvalidInstruction:\n  DoInvalidInstruction(instr);\n  return;\n#if 01\n#undef op\n#undef r1\n#undef r2\n#undef r3\n#undef shft\n#undef fxn\n#undef imm16\n#undef simm16\n#undef jtgt\n#endif\n}\n\nSTATIC\nvoid DoBreak(uint32 instr)\n{\n  uint32 code = (instr >> 16) & 0x3FF; // are there really another/extra 10 bits of the code?\n\n  switch (code)\n  {\n  case 6:\n    printstr(\"\\nBreak: Signed division overflow\");\n    break;\n  case 7:\n    printstr(\"\\nBreak: Division by 0\");\n    break;\n  default:\n    printstr(\"\\nBreak: Code: 0x\"); printhex(code);\n    break;\n  }\n  printstr(\" at PC = 0x\"); printhex(Regs[REG_PC]); printchr('\\n');\n  exit(-1);\n}\n\nSTATIC\nvoid DoTrap(uint32 instr)\n{\n  uint32 code = (instr >> 6) & 0x3FF;\n\n  switch (code)\n  {\n  case 6:\n    printstr(\"\\nTrap: Signed division overflow\");\n    break;\n  case 7:\n    printstr(\"\\nTrap: Division by 0\");\n    break;\n  default:\n    printstr(\"\\nTrap: Code: 0x\"); printhex(code);\n    break;\n  }\n  printstr(\" at PC = 0x\"); printhex(Regs[REG_PC]); printchr('\\n');\n  exit(-1);\n}\n\nSTATIC\nvoid DoOverflow(void)\n{\n  printstr(\"Signed integer addition/subtraction overflow\");\n  printstr(\" at PC = 0x\"); printhex(Regs[REG_PC]); printchr('\\n');\n  exit(-1);\n}\n\nSTATIC\nvoid DoInvalidInstruction(uint32 instr)\n{\n  printstr(\"Invalid/unsupported instruction: Opcode: 0x\"); printhex(instr);\n  printstr(\" at PC = 0x\"); printhex(Regs[REG_PC]); printchr('\\n');\n  exit(-1);\n}\n"
  },
  {
    "path": "lib/libicache/icaches.s",
    "content": " # /*\n # Copyright (c) 2013, Alexey Frunze\n # All rights reserved.\n #\n # Redistribution and use in source and binary forms, with or without\n # modification, are permitted provided that the following conditions are met: \n #\n # 1. Redistributions of source code must retain the above copyright notice, this\n #    list of conditions and the following disclaimer. \n # 2. Redistributions in binary form must reproduce the above copyright notice,\n #    this list of conditions and the following disclaimer in the documentation\n #    and/or other materials provided with the distribution. \n #\n # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\n # ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n #\n # The views and conclusions contained in the software and documentation are those\n # of the authors and should not be interpreted as representing official policies, \n # either expressed or implied, of the FreeBSD Project.\n # */\n #\n # /*****************************************************************************/\n # /*                                                                           */\n # /*                               MIPS icache                                 */\n # /*                                                                           */\n # /*****************************************************************************/\n\n        .text\n\n        .extern _gp\n        .extern _icRegs_\n        .extern _icHostRegs_\n        .extern _icmain_\n\n        .globl  _icstart_\n        .type   _icstart_, @function\n_icstart_:\n        la      $28, _gp\n        subu    $29, $29, 1024 # allocate 1K of stack for us\n        sw      $29, _icRegs_ + 4*29 # leave the rest to the program\n        addu    $29, $29, 1024 - 16\n        j       _icmain_\n\n        .globl  _icDoSysCall_\n        .type   _icDoSysCall_, @function\n_icDoSysCall_:\n        sw      $4, $_icsyscall_ # patch the syscall instruction\n        # We need to write back the data cache and invalidate the instruction\n        # cache for the location of the modified instruction before we can\n        # actually execute it\n        la      $4, $_icsyscall_\n        synci   0($4) # does nothing on MIPS32 M4K since it has no caches\n\n #      sw      $1, _icHostRegs_ + 4*1 # ar\n #      lw      $1, _icRegs_     + 4*1 #\n #      sw      $2, _icHostRegs_ + 4*2 # v0\n        lw      $2, _icRegs_     + 4*2 #\n #      sw      $3, _icHostRegs_ + 4*3 # v1\n        lw      $3, _icRegs_     + 4*3 #\n #      sw      $4, _icHostRegs_ + 4*4 # a0\n        lw      $4, _icRegs_     + 4*4 #\n #      sw      $5, _icHostRegs_ + 4*5 # a1\n        lw      $5, _icRegs_     + 4*5 #\n #      sw      $6, _icHostRegs_ + 4*6 # a2\n        lw      $6, _icRegs_     + 4*6 #\n #      sw      $7, _icHostRegs_ + 4*7 # a3\n        lw      $7, _icRegs_     + 4*7 #\n #      sw      $8, _icHostRegs_ + 4*8 # t0\n        lw      $8, _icRegs_     + 4*8 #\n #      sw      $9, _icHostRegs_ + 4*9 # t1\n        lw      $9, _icRegs_     + 4*9 #\n #      sw      $10, _icHostRegs_ + 4*10 # t2\n        lw      $10, _icRegs_     + 4*10 #\n #      sw      $11, _icHostRegs_ + 4*11 # t3\n        lw      $11, _icRegs_     + 4*11 #\n #      sw      $12, _icHostRegs_ + 4*12 # t4\n        lw      $12, _icRegs_     + 4*12 #\n #      sw      $13, _icHostRegs_ + 4*13 # t5\n        lw      $13, _icRegs_     + 4*13 #\n #      sw      $14, _icHostRegs_ + 4*14 # t6\n        lw      $14, _icRegs_     + 4*14 #\n #      sw      $15, _icHostRegs_ + 4*15 # t7\n        lw      $15, _icRegs_     + 4*15 #\n        sw      $16, _icHostRegs_ + 4*16\n        lw      $16, _icRegs_     + 4*16\n        sw      $17, _icHostRegs_ + 4*17\n        lw      $17, _icRegs_     + 4*17\n        sw      $18, _icHostRegs_ + 4*18\n        lw      $18, _icRegs_     + 4*18\n        sw      $19, _icHostRegs_ + 4*19\n        lw      $19, _icRegs_     + 4*19\n        sw      $20, _icHostRegs_ + 4*20\n        lw      $20, _icRegs_     + 4*20\n        sw      $21, _icHostRegs_ + 4*21\n        lw      $21, _icRegs_     + 4*21\n        sw      $22, _icHostRegs_ + 4*22\n        lw      $22, _icRegs_     + 4*22\n        sw      $23, _icHostRegs_ + 4*23\n        lw      $23, _icRegs_     + 4*23\n #      sw      $24, _icHostRegs_ + 4*24 # t8\n        lw      $24, _icRegs_     + 4*24 #\n #      sw      $25, _icHostRegs_ + 4*25 # t9\n        lw      $25, _icRegs_     + 4*25 #\n #      sw      $26, _icHostRegs_ + 4*26 # k0\n #      lw      $26, _icRegs_     + 4*26 #\n #      sw      $27, _icHostRegs_ + 4*27 # k1\n #      lw      $27, _icRegs_     + 4*27 #\n        sw      $28, _icHostRegs_ + 4*28 # gp\n        lw      $28, _icRegs_     + 4*28 #\n        sw      $29, _icHostRegs_ + 4*29 # sp\n #       lw      $29, _icRegs_     + 4*29 #\n        # Make sure sp is updated \"atomically\" and not part by part\n        .set    noat\n        lw      $1, _icRegs_     + 4*29 #\n        move    $29, $1 #\n        .set    at\n        sw      $30, _icHostRegs_ + 4*30\n        lw      $30, _icRegs_     + 4*30\n #      sw      $31, _icHostRegs_ + 4*31 # ra\n #      lw      $31, _icRegs_     + 4*31 # ra\n\n$_icsyscall_:\n        # This instruction gets patched, so it can have\n        # the requested system call number embedded in it\n        syscall\n\n        # RetroBSD may advance PC on returning from a syscall handler,\n        # skipping 2 instructions that follow the syscall instruction.\n        # Those 2 instructions typically set C's errno variable and\n        # are either executed on error or skipped on success.\n        # Account for this peculiarity.\n        j       $_icsyscall_error_\n        nop\n$_icsyscall_success_:\n\n #      sw      $1, _icRegs_     + 4*1 # ar\n #      lw      $1, _icHostRegs_ + 4*1 #\n        sw      $2, _icRegs_     + 4*2 # v0\n #      lw      $2, _icHostRegs_ + 4*2 #\n        sw      $3, _icRegs_     + 4*3 # v1\n #      lw      $3, _icHostRegs_ + 4*3 #\n        sw      $4, _icRegs_     + 4*4 # a0\n #      lw      $4, _icHostRegs_ + 4*4 #\n        sw      $5, _icRegs_     + 4*5 # a1\n #      lw      $5, _icHostRegs_ + 4*5 #\n        sw      $6, _icRegs_     + 4*6 # a2\n #      lw      $6, _icHostRegs_ + 4*6 #\n        sw      $7, _icRegs_     + 4*7 # a3\n #      lw      $7, _icHostRegs_ + 4*7 #\n        sw      $8, _icRegs_     + 4*8 # t0\n #      lw      $8, _icHostRegs_ + 4*8 #\n        sw      $9, _icRegs_     + 4*9 # t1\n #      lw      $9, _icHostRegs_ + 4*9 #\n        sw      $10, _icRegs_     + 4*10 # t2\n #      lw      $10, _icHostRegs_ + 4*10 #\n        sw      $11, _icRegs_     + 4*11 # t3\n #      lw      $11, _icHostRegs_ + 4*11 #\n        sw      $12, _icRegs_     + 4*12 # t4\n #      lw      $12, _icHostRegs_ + 4*12 #\n        sw      $13, _icRegs_     + 4*13 # t5\n #      lw      $13, _icHostRegs_ + 4*13 #\n        sw      $14, _icRegs_     + 4*14 # t6\n #      lw      $14, _icHostRegs_ + 4*14 #\n        sw      $15, _icRegs_     + 4*15 # t7\n #      lw      $15, _icHostRegs_ + 4*15 #\n        sw      $16, _icRegs_     + 4*16\n        lw      $16, _icHostRegs_ + 4*16\n        sw      $17, _icRegs_     + 4*17\n        lw      $17, _icHostRegs_ + 4*17\n        sw      $18, _icRegs_     + 4*18\n        lw      $18, _icHostRegs_ + 4*18\n        sw      $19, _icRegs_     + 4*19\n        lw      $19, _icHostRegs_ + 4*19\n        sw      $20, _icRegs_     + 4*20\n        lw      $20, _icHostRegs_ + 4*20\n        sw      $21, _icRegs_     + 4*21\n        lw      $21, _icHostRegs_ + 4*21\n        sw      $22, _icRegs_     + 4*22\n        lw      $22, _icHostRegs_ + 4*22\n        sw      $23, _icRegs_     + 4*23\n        lw      $23, _icHostRegs_ + 4*23\n        sw      $24, _icRegs_     + 4*24 # t8\n #      lw      $24, _icHostRegs_ + 4*24 #\n        sw      $25, _icRegs_     + 4*25 # t9\n #      lw      $25, _icHostRegs_ + 4*25 #\n #      sw      $26, _icRegs_     + 4*26 # k0\n #      lw      $26, _icHostRegs_ + 4*26 #\n #      sw      $27, _icRegs_     + 4*27 # k1\n #      lw      $27, _icHostRegs_ + 4*27 #\n        sw      $28, _icRegs_     + 4*28 # gp\n        lw      $28, _icHostRegs_ + 4*28 #\n        sw      $29, _icRegs_     + 4*29 # sp\n #       lw      $29, _icHostRegs_ + 4*29 #\n        # Make sure sp is updated \"atomically\" and not part by part\n        .set    noat\n        lw      $1, _icHostRegs_ + 4*29 #\n        move    $29, $1\n        .set    at\n        sw      $30, _icRegs_     + 4*30\n        lw      $30, _icHostRegs_ + 4*30\n #      sw      $31, _icRegs_     + 4*31 # ra\n #      lw      $31, _icHostRegs_ + 4*31 #\n\n        li      $2, 2 # success, 2 instructions skipped\n        j       $31\n\n$_icsyscall_error_:\n #      sw      $1, _icRegs_     + 4*1 # ar\n #      lw      $1, _icHostRegs_ + 4*1 #\n        sw      $2, _icRegs_     + 4*2 # v0\n #      lw      $2, _icHostRegs_ + 4*2 #\n        sw      $3, _icRegs_     + 4*3 # v1\n #      lw      $3, _icHostRegs_ + 4*3 #\n        sw      $4, _icRegs_     + 4*4 # a0\n #      lw      $4, _icHostRegs_ + 4*4 #\n        sw      $5, _icRegs_     + 4*5 # a1\n #      lw      $5, _icHostRegs_ + 4*5 #\n        sw      $6, _icRegs_     + 4*6 # a2\n #      lw      $6, _icHostRegs_ + 4*6 #\n        sw      $7, _icRegs_     + 4*7 # a3\n #      lw      $7, _icHostRegs_ + 4*7 #\n        sw      $8, _icRegs_     + 4*8 # t0\n #      lw      $8, _icHostRegs_ + 4*8 #\n        sw      $9, _icRegs_     + 4*9 # t1\n #      lw      $9, _icHostRegs_ + 4*9 #\n        sw      $10, _icRegs_     + 4*10 # t2\n #      lw      $10, _icHostRegs_ + 4*10 #\n        sw      $11, _icRegs_     + 4*11 # t3\n #      lw      $11, _icHostRegs_ + 4*11 #\n        sw      $12, _icRegs_     + 4*12 # t4\n #      lw      $12, _icHostRegs_ + 4*12 #\n        sw      $13, _icRegs_     + 4*13 # t5\n #      lw      $13, _icHostRegs_ + 4*13 #\n        sw      $14, _icRegs_     + 4*14 # t6\n #      lw      $14, _icHostRegs_ + 4*14 #\n        sw      $15, _icRegs_     + 4*15 # t7\n #      lw      $15, _icHostRegs_ + 4*15 #\n        sw      $16, _icRegs_     + 4*16\n        lw      $16, _icHostRegs_ + 4*16\n        sw      $17, _icRegs_     + 4*17\n        lw      $17, _icHostRegs_ + 4*17\n        sw      $18, _icRegs_     + 4*18\n        lw      $18, _icHostRegs_ + 4*18\n        sw      $19, _icRegs_     + 4*19\n        lw      $19, _icHostRegs_ + 4*19\n        sw      $20, _icRegs_     + 4*20\n        lw      $20, _icHostRegs_ + 4*20\n        sw      $21, _icRegs_     + 4*21\n        lw      $21, _icHostRegs_ + 4*21\n        sw      $22, _icRegs_     + 4*22\n        lw      $22, _icHostRegs_ + 4*22\n        sw      $23, _icRegs_     + 4*23\n        lw      $23, _icHostRegs_ + 4*23\n        sw      $24, _icRegs_     + 4*24 # t8\n #      lw      $24, _icHostRegs_ + 4*24 #\n        sw      $25, _icRegs_     + 4*25 # t9\n #      lw      $25, _icHostRegs_ + 4*25 #\n #      sw      $26, _icRegs_     + 4*26 # k0\n #      lw      $26, _icHostRegs_ + 4*26 #\n #      sw      $27, _icRegs_     + 4*27 # k1\n #      lw      $27, _icHostRegs_ + 4*27 #\n        sw      $28, _icRegs_     + 4*28 # gp\n        lw      $28, _icHostRegs_ + 4*28 #\n        sw      $29, _icRegs_     + 4*29 # sp\n #       lw      $29, _icHostRegs_ + 4*29 #\n        # Make sure sp is updated \"atomically\" and not part by part\n        .set    noat\n        lw      $1, _icHostRegs_ + 4*29 #\n        move    $29, $1 #\n        .set    at\n        sw      $30, _icRegs_     + 4*30\n        lw      $30, _icHostRegs_ + 4*30\n #      sw      $31, _icRegs_     + 4*31 # ra\n #      lw      $31, _icHostRegs_ + 4*31 #\n\n        li      $2, 0 # failure, 0 instructions skipped\n        j       $31\n"
  },
  {
    "path": "lib/libicache/license.txt",
    "content": "Copyright (c) 2013, Alexey Frunze\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met: \n\n1. Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer. \n2. Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution. \n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\nANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\nANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nThe views and conclusions contained in the software and documentation are those\nof the authors and should not be interpreted as representing official policies, \neither expressed or implied, of the FreeBSD Project.\n"
  },
  {
    "path": "lib/libicache/readme.txt",
    "content": "icache is a MIPS emulator + software instruction cache.\n\nWith it one may be able to run large programs on MIPS32 processors\nthat would otherwise not fit into small on-chip RAMs of ~128KB.\n\nSupported platform: RetroBSD.\nhttp://www.retrobsd.org/\n\nSee the Wiki for more up-to-date details:\nhttp://github.com/alexfru/icacheMips/wiki\n"
  },
  {
    "path": "lib/libm/Makefile",
    "content": "TOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS          += ${DEFS} -Wall\n\nSRCS            = login.c logout.c logwtmp.c\nOBJS            = asin.o atan.o exp.o erf.o floor.o fmod.o hypot.o j0.o j1.o \\\n                  jn.o log.o pow.o sin.o sinh.o sqrt.o tan.o tanh.o\n\nall:            ../libm.a\n\n../libm.a:\t${OBJS}\n\t\t${AR} cr $@ ${OBJS}\n\t\t$(RANLIB) $@\n\ninstall:\tall\n#\t\t${INSTALL} -d ${DESTDIR}/usr/lib\n#\t\t${INSTALL} ../libm.a ${DESTDIR}/usr/lib/libm.a\n#\t\t$(RANLIB) ${DESTDIR}/usr/lib/libm.a\n\nclean:\n\t\trm -f ../libm.a *.o *~ tags\n\ncleandir:       clean\n\t\trm -f .depend\n\ndepend:\n\t\tmkdep ${CFLAGS} ${SRCS}\n\ntags:\n\t\tctags ${SRCS}\n"
  },
  {
    "path": "lib/libm/asin.c",
    "content": "/*\n * asin(arg) and acos(arg) return the arcsin, arccos,\n * respectively of their arguments.\n *\n * Arctan is called after appropriate range reduction.\n */\n#include <errno.h>\n#include <math.h>\n\nint errno;\n\nstatic double pio2\t= 1.570796326794896619;\n\ndouble\nasin(arg)\n        double arg;\n{\n\tdouble sign, temp;\n\n\tsign = 1.;\n\tif(arg <0){\n\t\targ = -arg;\n\t\tsign = -1.;\n\t}\n\n\tif(arg > 1.){\n\t\terrno = EDOM;\n\t\treturn(0.);\n\t}\n\n\ttemp = sqrt(1. - arg*arg);\n\tif(arg > 0.7)\n\t\ttemp = pio2 - atan(temp/arg);\n\telse\n\t\ttemp = atan(arg/temp);\n\n\treturn(sign*temp);\n}\n\ndouble\nacos(arg)\n        double arg;\n{\n\tif(arg < 0)\n\t\targ = -arg;\n\n\tif(arg > 1.){\n\t\terrno = EDOM;\n\t\treturn(0.);\n\t}\n\n\treturn(pio2 - asin(arg));\n}\n"
  },
  {
    "path": "lib/libm/atan.c",
    "content": "/*\n * floating-point arctangent\n *\n * atan returns the value of the arctangent of its\n * argument in the range [-pi/2,pi/2].\n *\n * atan2 returns the arctangent of arg1/arg2\n * in the range [-pi,pi].\n *\n * there are no error returns.\n *\n * coefficients are #5077 from Hart & Cheney. (19.56D)\n */\n#include <math.h>\n\ndouble static sq2p1\t =2.414213562373095048802e0;\nstatic double sq2m1\t = .414213562373095048802e0;\nstatic double pio2\t =1.570796326794896619231e0;\nstatic double pio4\t = .785398163397448309615e0;\nstatic double p4\t = .161536412982230228262e2;\nstatic double p3\t = .26842548195503973794141e3;\nstatic double p2\t = .11530293515404850115428136e4;\nstatic double p1\t = .178040631643319697105464587e4;\nstatic double p0\t = .89678597403663861959987488e3;\nstatic double q4\t = .5895697050844462222791e2;\nstatic double q3\t = .536265374031215315104235e3;\nstatic double q2\t = .16667838148816337184521798e4;\nstatic double q1\t = .207933497444540981287275926e4;\nstatic double q0\t = .89678597403663861962481162e3;\n\n/*\n * xatan evaluates a series valid in the\n * range [-0.414...,+0.414...].\n */\nstatic double\nxatan(arg)\ndouble arg;\n{\n\tdouble argsq;\n\tdouble value;\n\n\targsq = arg*arg;\n\tvalue = ((((p4*argsq + p3)*argsq + p2)*argsq + p1)*argsq + p0);\n\tvalue = value/(((((argsq + q4)*argsq + q3)*argsq + q2)*argsq + q1)*argsq + q0);\n\treturn(value*arg);\n}\n\n/*\n * satan reduces its argument (known to be positive)\n * to the range [0,0.414...] and calls xatan.\n */\nstatic double\nsatan(arg)\ndouble arg;\n{\n\tif(arg < sq2m1)\n\t\treturn(xatan(arg));\n\telse if(arg > sq2p1)\n\t\treturn(pio2 - xatan(1.0/arg));\n\telse\n\t\treturn(pio4 + xatan((arg-1.0)/(arg+1.0)));\n}\n\n/*\n * atan makes its argument positive and\n * calls the inner routine satan.\n */\ndouble\natan(arg)\ndouble arg;\n{\n\tif(arg>0)\n\t\treturn(satan(arg));\n\telse\n\t\treturn(-satan(-arg));\n}\n\n\n/*\n * atan2 discovers what quadrant the angle\n * is in and calls atan.\n */\ndouble\natan2(arg1,arg2)\ndouble arg1,arg2;\n{\n\tif((arg1+arg2)==arg1)\n\t\tif(arg1 >= 0.) return(pio2);\n\t\telse return(-pio2);\n\telse if(arg2 <0.)\n\t\tif(arg1 >= 0.)\n\t\t\treturn(pio2+pio2 - satan(-arg1/arg2));\n\t\telse\n\t\t\treturn(-pio2-pio2 + satan(arg1/arg2));\n\telse if(arg1>0)\n\t\treturn(satan(arg1/arg2));\n\telse\n\t\treturn(-satan(-arg1/arg2));\n}\n"
  },
  {
    "path": "lib/libm/erf.c",
    "content": "/*\n * C program for floating point error function\n *\n * erf(x) returns the error function of its argument\n * erfc(x) returns 1.0-erf(x)\n *\n * erf(x) is defined by\n * ${2 over sqrt(pi)} int from 0 to x e sup {-t sup 2} dt$\n *\n * the entry for erfc is provided because of the\n * extreme loss of relative accuracy if erf(x) is\n * called for large x and the result subtracted\n * from 1. (e.g. for x= 10, 12 places are lost).\n *\n * There are no error returns.\n *\n * Calls exp.\n *\n * Coefficients for large x are #5667 from Hart & Cheney (18.72D).\n */\n#include <math.h>\n\n#define M 7\n#define N 9\n\nint errno;\nstatic double torp = 1.1283791670955125738961589031;\nstatic double p1[] = {\n\t0.804373630960840172832162e5,\n\t0.740407142710151470082064e4,\n\t0.301782788536507577809226e4,\n\t0.380140318123903008244444e2,\n\t0.143383842191748205576712e2,\n\t-.288805137207594084924010e0,\n\t0.007547728033418631287834e0,\n};\nstatic double q1[]  = {\n\t0.804373630960840172826266e5,\n\t0.342165257924628539769006e5,\n\t0.637960017324428279487120e4,\n\t0.658070155459240506326937e3,\n\t0.380190713951939403753468e2,\n\t0.100000000000000000000000e1,\n\t0.0,\n};\nstatic double p2[]  = {\n\t0.18263348842295112592168999e4,\n\t0.28980293292167655611275846e4,\n\t0.2320439590251635247384768711e4,\n\t0.1143262070703886173606073338e4,\n\t0.3685196154710010637133875746e3,\n\t0.7708161730368428609781633646e2,\n\t0.9675807882987265400604202961e1,\n\t0.5641877825507397413087057563e0,\n\t0.0,\n};\nstatic double q2[]  = {\n\t0.18263348842295112595576438e4,\n\t0.495882756472114071495438422e4,\n\t0.60895424232724435504633068e4,\n\t0.4429612803883682726711528526e4,\n\t0.2094384367789539593790281779e4,\n\t0.6617361207107653469211984771e3,\n\t0.1371255960500622202878443578e3,\n\t0.1714980943627607849376131193e2,\n\t1.0,\n};\n\ndouble\nerf(arg) double arg;{\n\tdouble erfc();\n\tint sign;\n\tdouble argsq;\n\tdouble d, n;\n\tint i;\n\n\terrno = 0;\n\tsign = 1;\n\tif(arg < 0.){\n\t\targ = -arg;\n\t\tsign = -1;\n\t}\n\tif(arg < 0.5){\n\t\targsq = arg*arg;\n\t\tfor(n=0,d=0,i=M-1; i>=0; i--){\n\t\t\tn = n*argsq + p1[i];\n\t\t\td = d*argsq + q1[i];\n\t\t}\n\t\treturn(sign*torp*arg*n/d);\n\t}\n\tif(arg >= 10.)\n\t\treturn(sign*1.);\n\treturn(sign*(1. - erfc(arg)));\n}\n\ndouble\nerfc(arg) double arg;{\n\tdouble erf();\n\tdouble exp();\n\tdouble n, d;\n\tint i;\n\n\terrno = 0;\n\tif(arg < 0.)\n\t\treturn(2. - erfc(-arg));\n/*\n\tif(arg < 0.5)\n\t\treturn(1. - erf(arg));\n*/\n\tif(arg >= 10.)\n\t\treturn(0.);\n\n\tfor(n=0,d=0,i=N-1; i>=0; i--){\n\t\tn = n*arg + p2[i];\n\t\td = d*arg + q2[i];\n\t}\n\treturn(exp(-arg*arg)*n/d);\n}\n"
  },
  {
    "path": "lib/libm/exp.c",
    "content": "/*\n * exp returns the exponential function of its\n * floating-point argument.\n *\n * The coefficients are #1069 from Hart and Cheney. (22.35D)\n */\n#include <float.h>\n#include <errno.h>\n#include <math.h>\n\nint\terrno;\nstatic double\tp0\t= .2080384346694663001443843411e7;\nstatic double\tp1\t= .3028697169744036299076048876e5;\nstatic double\tp2\t= .6061485330061080841615584556e2;\nstatic double\tq0\t= .6002720360238832528230907598e7;\nstatic double\tq1\t= .3277251518082914423057964422e6;\nstatic double\tq2\t= .1749287689093076403844945335e4;\nstatic double\tlog2e\t= 1.4426950408889634073599247;\nstatic double\tsqrt2\t= 1.4142135623730950488016887;\nstatic double\tmaxf\t= DBL_MAX_10_EXP * 2.5/*>ln(10)*/;\n\ndouble\nexp(arg)\ndouble arg;\n{\n\tdouble fract;\n\tdouble temp1, temp2, xsq;\n\tint ent;\n\n\tif(arg == 0.)\n\t\treturn(1.);\n\tif(arg < -maxf)\n\t\treturn(0.);\n\tif(arg > maxf) {\n\t\terrno = ERANGE;\n\t\treturn(HUGE_VAL);\n\t}\n\targ *= log2e;\n\tent = floor(arg);\n\tfract = (arg-ent) - 0.5;\n\txsq = fract*fract;\n\ttemp1 = ((p2*xsq+p1)*xsq+p0)*fract;\n\ttemp2 = ((1.0*xsq+q2)*xsq+q1)*xsq + q0;\n\treturn(ldexp(sqrt2*(temp2+temp1)/(temp2-temp1), ent));\n}\n"
  },
  {
    "path": "lib/libm/fabs.c",
    "content": "#include <math.h>\n\ndouble\nfabs(arg)\n        double arg;\n{\n\n\tif(arg < 0.)\n\t\targ = -arg;\n\treturn(arg);\n}\n"
  },
  {
    "path": "lib/libm/floor.c",
    "content": "/*\n * floor and ceil-- greatest integer <= arg\n * (resp least >=)\n */\n#include <math.h>\n\ndouble\nfloor(d)\n        double d;\n{\n\tdouble fract;\n\n\tif (d<0.0) {\n\t\td = -d;\n\t\tfract = modf(d, &d);\n\t\tif (fract != 0.0)\n\t\t\td += 1;\n\t\td = -d;\n\t} else\n\t\tmodf(d, &d);\n\treturn(d);\n}\n\ndouble\nceil(d)\n        double d;\n{\n\treturn(-floor(-d));\n}\n"
  },
  {
    "path": "lib/libm/fmod.c",
    "content": "#include <stdio.h>\n#include <stdint.h>\n\ntypedef union {\n    double value;\n    struct {\n        uint32_t lo;\n        uint32_t hi;\n    } uns;\n} union64_t;\n\n/*\n * Get two 32 bit ints from a double.\n */\n#define UNPACK_DOUBLE(high,low,d) {\\\n        union64_t u = {0}; \\\n        u.value = d; \\\n        high = u.uns.hi; \\\n        low  = u.uns.lo; \\\n    }\n\n/*\n * Set a double from two 32 bit ints.\n */\n#define PACK_DOUBLE(d,high,low) { \\\n        union64_t u = {0}; \\\n        u.uns.hi = high; \\\n        u.uns.lo = low; \\\n        d = u.value; \\\n    }\n\ntypedef union {\n    float value;\n    uint32_t word;\n} union32_t;\n\n/*\n * Get two 32 bit ints from a double.\n */\n#define UNPACK_FLOAT(w,f) {\\\n        union32_t u = {0}; \\\n        u.value = f; \\\n        w = u.word; \\\n    }\n\n/*\n * Set a double from two 32 bit ints.\n */\n#define PACK_FLOAT(f,w) { \\\n        union32_t u = {0}; \\\n        u.word = w; \\\n        f = u.value; \\\n    }\n\nstatic const double one = 1.0, Zero[] = {0.0, -0.0,};\n\ndouble fmod(double x, double y)\n{\n    int32_t n=0, hx=0, hy=0, hz=0, ix=0, iy=0, sx=0, i=0;\n\n    if (sizeof(float) == sizeof(double)) {\n        /*\n         * Double is 32-bit.\n         */\n        UNPACK_FLOAT(hx,x);\n        UNPACK_FLOAT(hy,y);\n        sx = hx & 0x80000000;                           /* sign of x */\n        hx ^= sx;                                       /* |x| */\n        hy &= 0x7fffffff;                               /* |y| */\n\n        /* purge off exception values */\n        if (hy == 0 || hx >= 0x7f800000 ||              /* y=0, or x not finite */\n            hy > 0x7f800000)                            /* or y is NaN */\n            return (x*y) / (x*y);\n        if (hx < hy)\n            return x;                                   /* |x| < |y| return x */\n        if (hx == hy)\n            return Zero[(uint32_t)sx >> 31];            /* |x| = |y| return x*0*/\n\n        /* determine ix = ilogb(x) */\n        if (hx < 0x00800000) {                          /* subnormal x */\n            for (ix= -126, i=hx<<8; i>0; i<<=1)\n                ix -= 1;\n        } else\n            ix = (hx >> 23) - 127;\n\n        /* determine iy = ilogb(y) */\n        if (hy < 0x00800000) {                          /* subnormal y */\n            for (iy= -126, i=hy<<8; i>=0; i<<=1)\n                iy -= 1;\n        } else iy = (hy >> 23) - 127;\n\n        /* set up {hx,lx}, {hy,ly} and align y to x */\n        if (ix >= -126)\n            hx = 0x00800000 | (0x007fffff & hx);\n        else {                                          /* subnormal x, shift x to normal */\n            n = -126 - ix;\n            hx = hx << n;\n        }\n        if (iy >= -126)\n            hy = 0x00800000 | (0x007fffff & hy);\n        else {                                          /* subnormal y, shift y to normal */\n            n = -126 - iy;\n            hy = hy << n;\n        }\n\n        /* fix point fmod */\n        n = ix - iy;\n        while (n--) {\n            hz = hx - hy;\n            if (hz < 0) {\n                hx = hx + hx;\n            } else {\n                if (hz == 0)                            /* return sign(x)*0 */\n                    return Zero[(uint32_t)sx >> 31];\n                hx = hz + hz;\n            }\n        }\n        hz = hx - hy;\n        if (hz >= 0) {\n            hx = hz;\n        }\n\n        /* convert back to floating value and restore the sign */\n        if (hx == 0)                                    /* return sign(x)*0 */\n            return Zero[(uint32_t)sx >> 31];\n        while (hx < 0x00800000) {                       /* normalize x */\n            hx = hx + hx;\n            iy -= 1;\n        }\n        if (iy >= -126) {                               /* normalize output */\n            hx = (hx - 0x00800000) | ((iy + 127) << 23);\n            PACK_FLOAT(x, hx | sx);\n        } else {                                        /* subnormal output */\n            n = -126 - iy;\n            hx >>= n;\n            PACK_FLOAT(x, hx | sx);\n            x *= one;                                   /* create necessary signal */\n        }\n    } else {\n        /*\n         * Double is 64-bit.\n         */\n        uint32_t lx=0, ly=0, lz=0;\n\n        UNPACK_DOUBLE(hx, lx, x);\n        UNPACK_DOUBLE(hy, ly, y);\n        sx = hx & 0x80000000;                           /* sign of x */\n        hx ^= sx;                                       /* |x| */\n        hy &= 0x7fffffff;                               /* |y| */\n\n        /* purge off exception values */\n        if ((hy | ly) == 0 || hx >= 0x7ff00000 ||       /* y=0,or x not finite */\n            (hy | ((ly | -ly) >> 31)) > 0x7ff00000)     /* or y is NaN */\n            return (x*y) / (x*y);\n        if (hx <= hy) {\n            if (hx < hy || lx < ly)\n                return x;                               /* |x| < |y| return x */\n            if (lx == ly)\n                return Zero[(uint32_t)sx >> 31];        /* |x| = |y| return x*0 */\n        }\n\n        /* determine ix = ilogb(x) */\n        if (hx < 0x00100000) {                          /* subnormal x */\n            if (hx == 0) {\n                for (ix = -1043, i=lx; i>0; i<<=1)\n                    ix -= 1;\n            } else {\n                for (ix = -1022, i=hx<<11; i>0; i<<=1)\n                    ix -= 1;\n            }\n        } else\n            ix = (hx >> 20) - 1023;\n\n        /* determine iy = ilogb(y) */\n        if (hy < 0x00100000) {                          /* subnormal y */\n            if(hy==0) {\n                for (iy = -1043, i=ly; i>0; i<<=1)\n                    iy -= 1;\n            } else {\n                for (iy = -1022,i=(hy<<11); i>0; i<<=1)\n                    iy -= 1;\n            }\n        } else\n            iy = (hy >> 20) - 1023;\n\n        /* set up {hx,lx}, {hy,ly} and align y to x */\n        if (ix >= -1022)\n            hx = 0x00100000 | (0x000fffff & hx);\n        else {                                          /* subnormal x, shift x to normal */\n            n = -1022 - ix;\n            if (n <= 31) {\n                hx = (hx << n) | (lx >> (32 - n));\n                lx <<= n;\n            } else {\n                hx = lx << (n - 32);\n                lx = 0;\n            }\n        }\n        if (iy >= -1022)\n            hy = 0x00100000 | (0x000fffff & hy);\n        else {                                          /* subnormal y, shift y to normal */\n            n = -1022 - iy;\n            if (n <= 31) {\n                hy = (hy << n) | (ly >> (32 - n));\n                ly <<= n;\n            } else {\n                hy = ly << (n - 32);\n                ly = 0;\n            }\n        }\n\n        /* fix point fmod */\n        n = ix - iy;\n        while (n--) {\n            hz = hx - hy;\n            lz = lx - ly;\n            if (lx < ly)\n                hz -= 1;\n\n            if (hz < 0) {\n                hx = hx + hx + (lx >> 31);\n                lx = lx + lx;\n            } else {\n                if ((hz | lz) == 0)                     /* return sign(x)*0 */\n                    return Zero[(uint32_t)sx >> 31];\n                hx = hz + hz + (lz >> 31);\n                lx = lz + lz;\n            }\n        }\n        hz = hx - hy;\n        lz = lx - ly;\n        if (lx < ly)\n            hz -= 1;\n        if (hz >= 0) {\n            hx = hz;\n            lx = lz;\n        }\n\n        /* convert back to floating value and restore the sign */\n        if ((hx | lx) == 0)                             /* return sign(x)*0 */\n            return Zero[(uint32_t)sx >> 31];\n        while (hx < 0x00100000) {                       /* normalize x */\n            hx = hx + hx + (lx >> 31);\n            lx = lx + lx;\n            iy -= 1;\n        }\n        if (iy >= -1022) {                              /* normalize output */\n            hx = (hx - 0x00100000) | ((iy + 1023) << 20);\n            PACK_DOUBLE(x, hx | sx, lx);\n        } else {                                        /* subnormal output */\n            n = -1022 - iy;\n            if (n <= 20) {\n                lx = (lx >> n) | ((uint32_t)hx << (32 - n));\n                hx >>= n;\n            } else if (n <= 31) {\n                lx = (hx << (32 - n)) | (lx >> n);\n                hx = sx;\n            } else {\n                lx = hx >> (n - 32);\n                hx = sx;\n            }\n            PACK_DOUBLE(x, hx | sx, lx);\n            x *= one;                                   /* create necessary signal */\n        }\n    }\n    return x;                                           /* exact output */\n}\n"
  },
  {
    "path": "lib/libm/hypot.c",
    "content": "/*\n * sqrt(a^2 + b^2)\n *\t(but carefully)\n */\n#include <math.h>\n\ndouble\nhypot(a, b)\n        double a, b;\n{\n\tdouble t;\n\n\tif (a < 0)\n                a = -a;\n\tif (b < 0)\n                b = -b;\n\tif (a > b) {\n\t\tt = a;\n\t\ta = b;\n\t\tb = t;\n\t}\n\tif (b==0)\n                return(0.);\n\ta /= b;\n\t/*\n\t * pathological overflow possible\n\t * in the next line.\n\t */\n\treturn(b*sqrt(1. + a*a));\n}\n\n#if 0\nstruct\tcomplex\n{\n\tdouble\tr;\n\tdouble\ti;\n};\n\ndouble\ncabs(arg)\n        struct complex arg;\n{\n\treturn(hypot(arg.r, arg.i));\n}\n#endif\n"
  },
  {
    "path": "lib/libm/j0.c",
    "content": "/*\n * floating point Bessel's function\n * of the first and second kinds\n * of order zero\n *\n * j0(x) returns the value of J0(x)\n * for all real values of x.\n *\n * There are no error returns.\n * Calls sin, cos, sqrt.\n *\n * There is a niggling bug in J0 which\n * causes errors up to 2e-16 for x in the\n * interval [-8,8].\n * The bug is caused by an inappropriate order\n * of summation of the series.  rhm will fix it\n * someday.\n *\n * Coefficients are from Hart & Cheney.\n * #5849 (19.22D)\n * #6549 (19.25D)\n * #6949 (19.41D)\n *\n * y0(x) returns the value of Y0(x)\n * for positive real values of x.\n * For x<=0, error number EDOM is set and a\n * large negative value is returned.\n *\n * Calls sin, cos, sqrt, log, j0.\n *\n * The values of Y0 have not been checked\n * to more than ten places.\n *\n * Coefficients are from Hart & Cheney.\n * #6245 (18.78D)\n * #6549 (19.25D)\n * #6949 (19.41D)\n */\n#include <math.h>\n#include <errno.h>\n\nint\terrno;\nstatic double pzero, qzero;\nstatic double tpi\t= .6366197723675813430755350535e0;\nstatic double pio4\t= .7853981633974483096156608458e0;\nstatic double p1[] = {\n\t0.4933787251794133561816813446e21,\n\t-.1179157629107610536038440800e21,\n\t0.6382059341072356562289432465e19,\n\t-.1367620353088171386865416609e18,\n\t0.1434354939140344111664316553e16,\n\t-.8085222034853793871199468171e13,\n\t0.2507158285536881945555156435e11,\n\t-.4050412371833132706360663322e8,\n\t0.2685786856980014981415848441e5,\n};\nstatic double q1[] = {\n\t0.4933787251794133562113278438e21,\n\t0.5428918384092285160200195092e19,\n\t0.3024635616709462698627330784e17,\n\t0.1127756739679798507056031594e15,\n\t0.3123043114941213172572469442e12,\n\t0.6699987672982239671814028660e9,\n\t0.1114636098462985378182402543e7,\n\t0.1363063652328970604442810507e4,\n\t1.0\n};\nstatic double p2[] = {\n\t0.5393485083869438325262122897e7,\n\t0.1233238476817638145232406055e8,\n\t0.8413041456550439208464315611e7,\n\t0.2016135283049983642487182349e7,\n\t0.1539826532623911470917825993e6,\n\t0.2485271928957404011288128951e4,\n\t0.0,\n};\nstatic double q2[] = {\n\t0.5393485083869438325560444960e7,\n\t0.1233831022786324960844856182e8,\n\t0.8426449050629797331554404810e7,\n\t0.2025066801570134013891035236e7,\n\t0.1560017276940030940592769933e6,\n\t0.2615700736920839685159081813e4,\n\t1.0,\n};\nstatic double p3[] = {\n\t-.3984617357595222463506790588e4,\n\t-.1038141698748464093880530341e5,\n\t-.8239066313485606568803548860e4,\n\t-.2365956170779108192723612816e4,\n\t-.2262630641933704113967255053e3,\n\t-.4887199395841261531199129300e1,\n\t0.0,\n};\nstatic double q3[] = {\n\t0.2550155108860942382983170882e6,\n\t0.6667454239319826986004038103e6,\n\t0.5332913634216897168722255057e6,\n\t0.1560213206679291652539287109e6,\n\t0.1570489191515395519392882766e5,\n\t0.4087714673983499223402830260e3,\n\t1.0,\n};\nstatic double p4[] = {\n\t-.2750286678629109583701933175e20,\n\t0.6587473275719554925999402049e20,\n\t-.5247065581112764941297350814e19,\n\t0.1375624316399344078571335453e18,\n\t-.1648605817185729473122082537e16,\n\t0.1025520859686394284509167421e14,\n\t-.3436371222979040378171030138e11,\n\t0.5915213465686889654273830069e8,\n\t-.4137035497933148554125235152e5,\n};\nstatic double q4[] = {\n\t0.3726458838986165881989980e21,\n\t0.4192417043410839973904769661e19,\n\t0.2392883043499781857439356652e17,\n\t0.9162038034075185262489147968e14,\n\t0.2613065755041081249568482092e12,\n\t0.5795122640700729537480087915e9,\n\t0.1001702641288906265666651753e7,\n\t0.1282452772478993804176329391e4,\n\t1.0,\n};\n\nstatic void\nasympt(arg)\n        double arg;\n{\n\tdouble zsq, n, d;\n\tint i;\n\tzsq = 64./(arg*arg);\n\tfor(n=0,d=0,i=6;i>=0;i--){\n\t\tn = n*zsq + p2[i];\n\t\td = d*zsq + q2[i];\n\t}\n\tpzero = n/d;\n\tfor(n=0,d=0,i=6;i>=0;i--){\n\t\tn = n*zsq + p3[i];\n\t\td = d*zsq + q3[i];\n\t}\n\tqzero = (8./arg)*(n/d);\n}\n\ndouble\nj0(arg)\n        double arg;\n{\n\tdouble argsq, n, d;\n\tdouble sin(), cos(), sqrt();\n\tint i;\n\n\tif(arg < 0.) arg = -arg;\n\tif(arg > 8.){\n\t\tasympt(arg);\n\t\tn = arg - pio4;\n\t\treturn(sqrt(tpi/arg)*(pzero*cos(n) - qzero*sin(n)));\n\t}\n\targsq = arg*arg;\n\tfor(n=0,d=0,i=8;i>=0;i--){\n\t\tn = n*argsq + p1[i];\n\t\td = d*argsq + q1[i];\n\t}\n\treturn(n/d);\n}\n\ndouble\ny0(arg)\n        double arg;\n{\n\tdouble argsq, n, d;\n\tdouble sin(), cos(), sqrt(), log(), j0();\n\tint i;\n\n\terrno = 0;\n\tif(arg <= 0.){\n\t\terrno = EDOM;\n\t\treturn(-HUGE_VAL);\n\t}\n\tif(arg > 8.){\n\t\tasympt(arg);\n\t\tn = arg - pio4;\n\t\treturn(sqrt(tpi/arg)*(pzero*sin(n) + qzero*cos(n)));\n\t}\n\targsq = arg*arg;\n\tfor(n=0,d=0,i=8;i>=0;i--){\n\t\tn = n*argsq + p4[i];\n\t\td = d*argsq + q4[i];\n\t}\n\treturn(n/d + tpi*j0(arg)*log(arg));\n}\n"
  },
  {
    "path": "lib/libm/j1.c",
    "content": "/*\n * floating point Bessel's function\n * of the first and second kinds\n * of order one\n *\n * j1(x) returns the value of J1(x)\n * for all real values of x.\n *\n * There are no error returns.\n * Calls sin, cos, sqrt.\n *\n * There is a niggling bug in J1 which\n * causes errors up to 2e-16 for x in the\n * interval [-8,8].\n * The bug is caused by an inappropriate order\n * of summation of the series.  rhm will fix it\n * someday.\n *\n * Coefficients are from Hart & Cheney.\n * #6050 (20.98D)\n * #6750 (19.19D)\n * #7150 (19.35D)\n *\n * y1(x) returns the value of Y1(x)\n * for positive real values of x.\n * For x<=0, error number EDOM is set and a\n * large negative value is returned.\n *\n * Calls sin, cos, sqrt, log, j1.\n *\n * The values of Y1 have not been checked\n * to more than ten places.\n *\n * Coefficients are from Hart & Cheney.\n * #6447 (22.18D)\n * #6750 (19.19D)\n * #7150 (19.35D)\n */\n#include <math.h>\n#include <errno.h>\n\nint\terrno;\nstatic double pzero, qzero;\nstatic double tpi\t= .6366197723675813430755350535e0;\nstatic double pio4\t= .7853981633974483096156608458e0;\nstatic double p1[] = {\n\t0.581199354001606143928050809e21,\n\t-.6672106568924916298020941484e20,\n\t0.2316433580634002297931815435e19,\n\t-.3588817569910106050743641413e17,\n\t0.2908795263834775409737601689e15,\n\t-.1322983480332126453125473247e13,\n\t0.3413234182301700539091292655e10,\n\t-.4695753530642995859767162166e7,\n\t0.2701122710892323414856790990e4,\n};\nstatic double q1[] = {\n\t0.1162398708003212287858529400e22,\n\t0.1185770712190320999837113348e20,\n\t0.6092061398917521746105196863e17,\n\t0.2081661221307607351240184229e15,\n\t0.5243710262167649715406728642e12,\n\t0.1013863514358673989967045588e10,\n\t0.1501793594998585505921097578e7,\n\t0.1606931573481487801970916749e4,\n\t1.0,\n};\nstatic double p2[] = {\n\t-.4435757816794127857114720794e7,\n\t-.9942246505077641195658377899e7,\n\t-.6603373248364939109255245434e7,\n\t-.1523529351181137383255105722e7,\n\t-.1098240554345934672737413139e6,\n\t-.1611616644324610116477412898e4,\n\t0.0,\n};\nstatic double q2[] = {\n\t-.4435757816794127856828016962e7,\n\t-.9934124389934585658967556309e7,\n\t-.6585339479723087072826915069e7,\n\t-.1511809506634160881644546358e7,\n\t-.1072638599110382011903063867e6,\n\t-.1455009440190496182453565068e4,\n\t1.0,\n};\nstatic double p3[] = {\n\t0.3322091340985722351859704442e5,\n\t0.8514516067533570196555001171e5,\n\t0.6617883658127083517939992166e5,\n\t0.1849426287322386679652009819e5,\n\t0.1706375429020768002061283546e4,\n\t0.3526513384663603218592175580e2,\n\t0.0,\n};\nstatic double q3[] = {\n\t0.7087128194102874357377502472e6,\n\t0.1819458042243997298924553839e7,\n\t0.1419460669603720892855755253e7,\n\t0.4002944358226697511708610813e6,\n\t0.3789022974577220264142952256e5,\n\t0.8638367769604990967475517183e3,\n\t1.0,\n};\nstatic double p4[] = {\n\t-.9963753424306922225996744354e23,\n\t0.2655473831434854326894248968e23,\n\t-.1212297555414509577913561535e22,\n\t0.2193107339917797592111427556e20,\n\t-.1965887462722140658820322248e18,\n\t0.9569930239921683481121552788e15,\n\t-.2580681702194450950541426399e13,\n\t0.3639488548124002058278999428e10,\n\t-.2108847540133123652824139923e7,\n\t0.0,\n};\nstatic double q4[] = {\n\t0.5082067366941243245314424152e24,\n\t0.5435310377188854170800653097e22,\n\t0.2954987935897148674290758119e20,\n\t0.1082258259408819552553850180e18,\n\t0.2976632125647276729292742282e15,\n\t0.6465340881265275571961681500e12,\n\t0.1128686837169442121732366891e10,\n\t0.1563282754899580604737366452e7,\n\t0.1612361029677000859332072312e4,\n\t1.0,\n};\n\nstatic void\nasympt(arg)\n        double arg;\n{\n\tdouble zsq, n, d;\n\tint i;\n\tzsq = 64./(arg*arg);\n\tfor(n=0,d=0,i=6;i>=0;i--){\n\t\tn = n*zsq + p2[i];\n\t\td = d*zsq + q2[i];\n\t}\n\tpzero = n/d;\n\tfor(n=0,d=0,i=6;i>=0;i--){\n\t\tn = n*zsq + p3[i];\n\t\td = d*zsq + q3[i];\n\t}\n\tqzero = (8./arg)*(n/d);\n}\n\ndouble\nj1(arg)\n        double arg;\n{\n\tdouble xsq, n, d, x;\n\tdouble sin(), cos(), sqrt();\n\tint i;\n\n\tx = arg;\n\tif(x < 0.) x = -x;\n\tif(x > 8.){\n\t\tasympt(x);\n\t\tn = x - 3.*pio4;\n\t\tn = sqrt(tpi/x)*(pzero*cos(n) - qzero*sin(n));\n\t\tif(arg <0.) n = -n;\n\t\treturn(n);\n\t}\n\txsq = x*x;\n\tfor(n=0,d=0,i=8;i>=0;i--){\n\t\tn = n*xsq + p1[i];\n\t\td = d*xsq + q1[i];\n\t}\n\treturn(arg*n/d);\n}\n\ndouble\ny1(arg)\n        double arg;\n{\n\tdouble xsq, n, d, x;\n\tdouble sin(), cos(), sqrt(), log(), j1();\n\tint i;\n\n\terrno = 0;\n\tx = arg;\n\tif(x <= 0.){\n\t\terrno = EDOM;\n\t\treturn(-HUGE_VAL);\n\t}\n\tif(x > 8.){\n\t\tasympt(x);\n\t\tn = x - 3*pio4;\n\t\treturn(sqrt(tpi/x)*(pzero*sin(n) + qzero*cos(n)));\n\t}\n\txsq = x*x;\n\tfor(n=0,d=0,i=9;i>=0;i--){\n\t\tn = n*xsq + p4[i];\n\t\td = d*xsq + q4[i];\n\t}\n\treturn(x*n/d + tpi*(j1(x)*log(x)-1./x));\n}\n"
  },
  {
    "path": "lib/libm/jn.c",
    "content": "/*\n * floating point Bessel's function of\n * the first and second kinds and of integer order.\n *\n * int n;\n * double x;\n * jn(n,x);\n *\n * returns the value of Jn(x) for all\n * integer values of n and all real values of x.\n *\n * There are no error returns.\n * Calls j0, j1.\n *\n * For n=0, j0(x) is called,\n * for n=1, j1(x) is called,\n * for n<x, forward recursion us used starting\n * from values of j0(x) and j1(x).\n * for n>x, a continued fraction approximation to\n * j(n,x)/j(n-1,x) is evaluated and then backward\n * recursion is used starting from a supposed value\n * for j(n,x). The resulting value of j(0,x) is\n * compared with the actual value to correct the\n * supposed value of j(n,x).\n *\n * yn(n,x) is similar in all respects, except\n * that forward recursion is used for all values of n>1.\n */\n#include <math.h>\n#include <errno.h>\n\nint\terrno;\n\ndouble\njn(n,x) int n; double x;{\n\tint i;\n\tdouble a, b, temp;\n\tdouble xsq, t;\n\tdouble j0(), j1();\n\n\tif(n<0){\n\t\tn = -n;\n\t\tx = -x;\n\t}\n\tif(n==0) return(j0(x));\n\tif(n==1) return(j1(x));\n\tif(x == 0.) return(0.);\n\tif(n>x) goto recurs;\n\n\ta = j0(x);\n\tb = j1(x);\n\tfor(i=1;i<n;i++){\n\t\ttemp = b;\n\t\tb = (2.*i/x)*b - a;\n\t\ta = temp;\n\t}\n\treturn(b);\n\nrecurs:\n\txsq = x*x;\n\tfor(t=0,i=n+16;i>n;i--){\n\t\tt = xsq/(2.*i - t);\n\t}\n\tt = x/(2.*n-t);\n\n\ta = t;\n\tb = 1;\n\tfor(i=n-1;i>0;i--){\n\t\ttemp = b;\n\t\tb = (2.*i/x)*b - a;\n\t\ta = temp;\n\t}\n\treturn(t*j0(x)/b);\n}\n\ndouble\nyn(n,x) int n; double x;{\n\tint i;\n\tint sign;\n\tdouble a, b, temp;\n\tdouble y0(), y1();\n\n\tif (x <= 0) {\n\t\terrno = EDOM;\n\t\treturn(-HUGE_VAL);\n\t}\n\tsign = 1;\n\tif(n<0){\n\t\tn = -n;\n\t\tif(n%2 == 1) sign = -1;\n\t}\n\tif(n==0) return(y0(x));\n\tif(n==1) return(sign*y1(x));\n\n\ta = y0(x);\n\tb = y1(x);\n\tfor(i=1;i<n;i++){\n\t\ttemp = b;\n\t\tb = (2.*i/x)*b - a;\n\t\ta = temp;\n\t}\n\treturn(sign*b);\n}\n"
  },
  {
    "path": "lib/libm/log.c",
    "content": "/*\n * log returns the natural logarithm of its floating\n * point argument.\n *\n * The coefficients are #2705 from Hart & Cheney. (19.38D)\n *\n * It calls frexp.\n */\n#include <errno.h>\n#include <math.h>\n\nint\terrno;\n\nstatic double\t_log2\t= 0.693147180559945309e0;\nstatic double\tln10\t= 2.302585092994045684;\nstatic double\tsqrto2\t= 0.707106781186547524e0;\nstatic double\tp0\t= -.240139179559210510e2;\nstatic double\tp1\t= 0.309572928215376501e2;\nstatic double\tp2\t= -.963769093368686593e1;\nstatic double\tp3\t= 0.421087371217979714e0;\nstatic double\tq0\t= -.120069589779605255e2;\nstatic double\tq1\t= 0.194809660700889731e2;\nstatic double\tq2\t= -.891110902798312337e1;\n\ndouble\nlog(arg)\ndouble arg;\n{\n\tdouble x,z, zsq, temp;\n\tint exp;\n\n\tif(arg <= 0.) {\n\t\terrno = EDOM;\n\t\treturn(-HUGE_VAL);\n\t}\n\tx = frexp(arg,&exp);\n\twhile(x<0.5) {\n\t\tx = x*2;\n\t\texp = exp-1;\n\t}\n\tif(x<sqrto2) {\n\t\tx = 2*x;\n\t\texp = exp-1;\n\t}\n\n\tz = (x-1)/(x+1);\n\tzsq = z*z;\n\n\ttemp = ((p3*zsq + p2)*zsq + p1)*zsq + p0;\n\ttemp = temp/(((1.0*zsq + q2)*zsq + q1)*zsq + q0);\n\ttemp = temp*z + exp*_log2;\n\treturn(temp);\n}\n\ndouble\nlog10(arg)\ndouble arg;\n{\n\n\treturn(log(arg)/ln10);\n}\n"
  },
  {
    "path": "lib/libm/pow.c",
    "content": "/*\n * computes a^b.\n * uses log and exp\n */\n#include <errno.h>\n#include <math.h>\n\nint errno;\n\ndouble\npow(arg1,arg2)\n        double arg1, arg2;\n{\n\tdouble temp;\n\tlong l;\n\n\tif(arg1 <= 0.) {\n\t\tif(arg1 == 0.) {\n\t\t\tif(arg2 <= 0.)\n\t\t\t\tgoto domain;\n\t\t\treturn(0.);\n\t\t}\n\t\tl = arg2;\n\t\tif(l != arg2)\n\t\t\tgoto domain;\n\t\ttemp = exp(arg2 * log(-arg1));\n\t\tif(l & 1)\n\t\t\ttemp = -temp;\n\t\treturn(temp);\n\t}\n\treturn(exp(arg2 * log(arg1)));\n\ndomain:\n\terrno = EDOM;\n\treturn(0.);\n}\n"
  },
  {
    "path": "lib/libm/sin.c",
    "content": "/*\n * C program for floating point sin/cos.\n * Calls modf.\n * There are no error exits.\n * Coefficients are #3370 from Hart & Cheney (18.80D).\n */\n#include <math.h>\n\nstatic double twoopi\t= 0.63661977236758134308;\nstatic double p0\t=  .1357884097877375669092680e8;\nstatic double p1\t= -.4942908100902844161158627e7;\nstatic double p2\t=  .4401030535375266501944918e6;\nstatic double p3\t= -.1384727249982452873054457e5;\nstatic double p4\t=  .1459688406665768722226959e3;\nstatic double q0\t=  .8644558652922534429915149e7;\nstatic double q1\t=  .4081792252343299749395779e6;\nstatic double q2\t=  .9463096101538208180571257e4;\nstatic double q3\t=  .1326534908786136358911494e3;\n\nstatic double\nsinus(arg, quad)\n        double arg;\n        int quad;\n{\n\tdouble modf();\n\tdouble e, f;\n\tdouble ysq;\n\tdouble x,y;\n\tint k;\n\tdouble temp1, temp2;\n\n\tx = arg;\n\tif(x<0) {\n\t\tx = -x;\n\t\tquad = quad + 2;\n\t}\n\tx = x*twoopi;\t/*underflow?*/\n\tif(x>32764){\n\t\ty = modf(x,&e);\n\t\te = e + quad;\n\t\tmodf(0.25*e,&f);\n\t\tquad = e - 4*f;\n\t}else{\n\t\tk = x;\n\t\ty = x - k;\n\t\tquad = (quad + k) & 03;\n\t}\n\tif (quad & 01)\n\t\ty = 1-y;\n\tif(quad > 1)\n\t\ty = -y;\n\n\tysq = y*y;\n\ttemp1 = ((((p4*ysq+p3)*ysq+p2)*ysq+p1)*ysq+p0)*y;\n\ttemp2 = ((((ysq+q3)*ysq+q2)*ysq+q1)*ysq+q0);\n\treturn(temp1/temp2);\n}\n\ndouble\ncos(arg)\n        double arg;\n{\n\tdouble sinus();\n\tif(arg<0)\n\t\targ = -arg;\n\treturn(sinus(arg, 1));\n}\n\ndouble\nsin(arg)\n        double arg;\n{\n\tdouble sinus();\n\treturn(sinus(arg, 0));\n}\n"
  },
  {
    "path": "lib/libm/sinh.c",
    "content": "/*\n * sinh(arg) returns the hyperbolic sine of its floating-\n * point argument.\n *\n * The exponential function is called for arguments\n * greater in magnitude than 0.5.\n *\n * A series is used for arguments smaller in magnitude than 0.5.\n * The coefficients are #2029 from Hart & Cheney. (20.36D)\n *\n * cosh(arg) is computed from the exponential function for\n * all arguments.\n */\n#include <math.h>\n\nstatic double p0  = -0.6307673640497716991184787251e+6;\nstatic double p1  = -0.8991272022039509355398013511e+5;\nstatic double p2  = -0.2894211355989563807284660366e+4;\nstatic double p3  = -0.2630563213397497062819489e+2;\nstatic double q0  = -0.6307673640497716991212077277e+6;\nstatic double q1   = 0.1521517378790019070696485176e+5;\nstatic double q2  = -0.173678953558233699533450911e+3;\n\ndouble\nsinh(arg)\n        double arg;\n{\n\tdouble temp, argsq;\n\tregister int sign;\n\n\tsign = 1;\n\tif(arg < 0) {\n\t\targ = - arg;\n\t\tsign = -1;\n\t}\n\n\tif(arg > 21.) {\n\t\ttemp = exp(arg)/2;\n\t\tif (sign>0)\n\t\t\treturn(temp);\n\t\telse\n\t\t\treturn(-temp);\n\t}\n\n\tif(arg > 0.5) {\n\t\treturn(sign*(exp(arg) - exp(-arg))/2);\n\t}\n\n\targsq = arg*arg;\n\ttemp = (((p3*argsq+p2)*argsq+p1)*argsq+p0)*arg;\n\ttemp /= (((argsq+q2)*argsq+q1)*argsq+q0);\n\treturn(sign*temp);\n}\n\ndouble\ncosh(arg)\n        double arg;\n{\n\tif(arg < 0)\n\t\targ = - arg;\n\tif(arg > 21.) {\n\t\treturn(exp(arg)/2);\n\t}\n\n\treturn((exp(arg) + exp(-arg))/2);\n}\n"
  },
  {
    "path": "lib/libm/sqrt.c",
    "content": "/*\n * sqrt returns the square root of its floating\n * point argument. Newton's method.\n *\n * calls frexp\n */\n#include <errno.h>\n#include <math.h>\n\nint errno;\n\ndouble\nsqrt(arg)\n        double arg;\n{\n\tdouble x, temp;\n\tint exp;\n\tint i;\n\n\tif(arg <= 0.) {\n\t\tif(arg < 0.)\n\t\t\terrno = EDOM;\n\t\treturn(0.);\n\t}\n\tx = frexp(arg,&exp);\n\twhile(x < 0.5) {\n\t\tx *= 2;\n\t\texp--;\n\t}\n\t/*\n\t * NOTE\n\t * this wont work on 1's comp\n\t */\n\tif(exp & 1) {\n\t\tx *= 2;\n\t\texp--;\n\t}\n\ttemp = 0.5*(1.0+x);\n\n\twhile(exp > 60) {\n\t\ttemp *= (1L<<30);\n\t\texp -= 60;\n\t}\n\twhile(exp < -60) {\n\t\ttemp /= (1L<<30);\n\t\texp += 60;\n\t}\n\tif(exp >= 0)\n\t\ttemp *= 1L << (exp/2);\n\telse\n\t\ttemp /= 1L << (-exp/2);\n\tfor(i=0; i<=4; i++)\n\t\ttemp = 0.5*(temp + arg/temp);\n\treturn(temp);\n}\n"
  },
  {
    "path": "lib/libm/tan.c",
    "content": "/*\n * floating point tangent\n *\n * A series is used after range reduction.\n * Coefficients are #4285 from Hart & Cheney. (19.74D)\n */\n#include <errno.h>\n#include <math.h>\n\nint\terrno;\n\nstatic double invpi\t  = 1.27323954473516268;\nstatic double p0\t = -0.1306820264754825668269611177e+5;\nstatic double p1\t  = 0.1055970901714953193602353981e+4;\nstatic double p2\t = -0.1550685653483266376941705728e+2;\nstatic double p3\t  = 0.3422554387241003435328470489e-1;\nstatic double p4\t  = 0.3386638642677172096076369e-4;\nstatic double q0\t = -0.1663895238947119001851464661e+5;\nstatic double q1\t  = 0.4765751362916483698926655581e+4;\nstatic double q2\t = -0.1555033164031709966900124574e+3;\n\ndouble\ntan(arg)\n        double arg;\n{\n\tdouble modf();\n\tdouble sign, temp, e, x, xsq;\n\tint flag, i;\n\n\tflag = 0;\n\tsign = 1.;\n\tif(arg < 0.){\n\t\targ = -arg;\n\t\tsign = -1.;\n\t}\n\targ = arg*invpi;   /*overflow?*/\n\tx = modf(arg,&e);\n\ti = e;\n\tswitch(i%4) {\n\tcase 1:\n\t\tx = 1. - x;\n\t\tflag = 1;\n\t\tbreak;\n\n\tcase 2:\n\t\tsign = - sign;\n\t\tflag = 1;\n\t\tbreak;\n\n\tcase 3:\n\t\tx = 1. - x;\n\t\tsign = - sign;\n\t\tbreak;\n\n\tcase 0:\n\t\tbreak;\n\t}\n\n\txsq = x*x;\n\ttemp = ((((p4*xsq+p3)*xsq+p2)*xsq+p1)*xsq+p0)*x;\n\ttemp = temp/(((1.0*xsq+q2)*xsq+q1)*xsq+q0);\n\n\tif(flag == 1) {\n\t\tif(temp == 0.) {\n\t\t\terrno = ERANGE;\n\t\t\tif (sign>0)\n\t\t\t\treturn(HUGE_VAL);\n\t\t\treturn(-HUGE_VAL);\n\t\t}\n\t\ttemp = 1./temp;\n\t}\n\treturn(sign*temp);\n}\n"
  },
  {
    "path": "lib/libm/tanh.c",
    "content": "/*\n * tanh(arg) computes the hyperbolic tangent of its floating\n * point argument.\n *\n * sinh and cosh are called except for large arguments, which\n * would cause overflow improperly.\n */\n#include <math.h>\n\ndouble\ntanh(arg)\n        double arg;\n{\n\tdouble sign;\n\n\tsign = 1.;\n\tif(arg < 0.){\n\t\targ = -arg;\n\t\tsign = -1.;\n\t}\n\n\tif(arg > 21.)\n\t\treturn(sign);\n\n\treturn(sign*sinh(arg)/cosh(arg));\n}\n"
  },
  {
    "path": "lib/libreadline/LICENSE",
    "content": "Copyright (c) 2010-2014, Salvatore Sanfilippo <antirez at gmail dot com>\nCopyright (c) 2010-2013, Pieter Noordhuis <pcnoordhuis at gmail dot com>\n\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n* Redistributions of source code must retain the above copyright notice,\n  this list of conditions and the following disclaimer.\n\n* Redistributions in binary form must reproduce the above copyright notice,\n  this list of conditions and the following disclaimer in the documentation\n  and/or other materials provided with the distribution.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\nANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\nANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\nANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n"
  },
  {
    "path": "lib/libreadline/Makefile",
    "content": "TOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS          += -O -Wall\n\nOBJS\t\t= readline.o\nHDRS\t\t= readline/readline.h readline/history.h\n\nall:            ../libreadline.a\n\n../libreadline.a: ${OBJS}\n\t\t@${AR} cr $@ ${OBJS}\n\t\t$(RANLIB) $@\n\ninstall: \tall ${HDRS}\n\t\t${INSTALL} -d ${DESTDIR}/usr/include/readline/\n\t\tcp -p ${HDRS} ${DESTDIR}/usr/include/readline/\n\nclean:\n\t\trm -f *~ *.o a.out ../libreadline*.a\n"
  },
  {
    "path": "lib/libreadline/Makefile-unix",
    "content": "CFLAGS += -Wall -Os -g\n\nexample: readline.o example.o\n\t$(CC) $(LDFLAGS) -o $@ readline.o example.o\n\nclean:\n\trm -rf *.o example example.dSYM history.txt\n\n###\nexample.o: example.c readline/readline.h readline/history.h\nreadline.o: readline.c readline/readline.h readline/history.h\n"
  },
  {
    "path": "lib/libreadline/README",
    "content": "Linenoise\n~~~~~~~~~\nA minimal, zero-config, BSD licensed, readline replacement used\nin Redis, MongoDB, and Android.\n\n  * Single and multi line editing mode with the usual key bindings implemented.\n  * History handling.\n  * Completion.\n  * About 1,100 lines of BSD license source code.\n  * Only uses a subset of VT100 escapes (ANSI.SYS compatible).\n\n\nCan a line editing library be 20k lines of code?\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nLine editing with some support for history is a really\nimportant feature for command line utilities. Instead of\nretyping almost the same stuff again and again it's just much\nbetter to hit the up arrow and edit on syntax errors, or in\norder to try a slightly different command. But apparently code\ndealing with terminals is some sort of Black Magic: readline is\n30k lines of code, libedit 20k. Is it reasonable to link small\nutilities to huge libraries just to get a minimal support for\nline editing?\n\nSo what usually happens is either:\n\n  * Large programs with configure scripts disabling line editing\n    if readline is not present in the system, or not supporting it\n    at all since readline is GPL licensed and libedit (the BSD\n    clone) is not as known and available as readline is (Real world\n    example of this problem: Tclsh).\n\n  * Smaller programs not using a configure script not\n    supporting line editing at all (A problem we had with Redis-cli\n    for instance).\n\nThe result is a pollution of binaries without line editing support.\n\nSo I spent more or less two hours doing a reality check\nresulting in this little library: is it *really* needed for a\nline editing library to be 20k lines of code? Apparently not,\nit is possibe to get a very small, zero configuration, trivial\nto embed library, that solves the problem. Smaller programs\nwill just include this, supporing line editing out of the box.\nLarger programs may use this little library or just checking\nwith configure if readline/libedit is available and resorting\nto linenoise if not.\n\n\nTerminals, in 2010\n~~~~~~~~~~~~~~~~~~\nApparently almost every terminal you can happen to use today\nhas some kind of support for basic VT100 escape sequences. So I\ntried to write a lib using just very basic VT100 features. The\nresulting library appears to work everywhere I tried to use it,\nand now can work even on ANSI.SYS compatible terminals, since\nno VT220 specific sequences are used anymore.\n\nThe library is currently about 1100 lines of code. In order to\nuse it in your project just look at the *example.c* file in the\nsource distribution, it is trivial. Linenoise is BSD code, so\nyou can use both in free software and commercial software.\n\n\nTested with...\n~~~~~~~~~~~~~~\n  * Linux text only console ($TERM = linux)\n  * Linux KDE terminal application ($TERM = xterm)\n  * Linux xterm ($TERM = xterm)\n  * Linux Buildroot ($TERM = vt100)\n  * Mac OS X iTerm ($TERM = xterm)\n  * Mac OS X default Terminal.app ($TERM = xterm)\n  * OpenBSD 4.5 through an OSX Terminal.app ($TERM = screen)\n  * IBM AIX 6.1\n  * FreeBSD xterm ($TERM = xterm)\n  * ANSI.SYS\n  * Emacs comint mode ($TERM = dumb)\n\nPlease test it everywhere you can and report back!\n\n\nLet's push this forward!\n~~~~~~~~~~~~~~~~~~~~~~~~\nPatches should be provided in the respect of linenoise\nsensibility for small easy to understand code.\n\nSend feedbacks to antirez at gmail\n"
  },
  {
    "path": "lib/libreadline/example.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n\n#include \"readline/readline.h\"\n#include \"readline/history.h\"\n\nint main(int argc, char **argv) {\n    char *line;\n    char *prgname = argv[0];\n\n    /* Parse options, with --multiline we enable multi line editing. */\n    while(argc > 1) {\n        argc--;\n        argv++;\n        if (!strcmp(*argv,\"--multiline\")) {\n            readline_set_multiline(1);\n            printf(\"Multi-line mode enabled.\\n\");\n        } else if (!strcmp(*argv,\"--keycodes\")) {\n            readline_print_keycodes();\n            exit(0);\n        } else {\n            fprintf(stderr, \"Usage: %s [--multiline] [--keycodes]\\n\", prgname);\n            exit(1);\n        }\n    }\n\n    /* Load history from file. The history file is just a plain text file\n     * where entries are separated by newlines. */\n    add_history(\"history.txt\"); /* Load the history at startup */\n\n    /* Now this is the main loop of the typical readline-based application.\n     * The call to readline() will block as long as the user types something\n     * and presses enter.\n     *\n     * The typed string is returned as a malloc() allocated string by\n     * readline, so the user needs to free() it. */\n    while((line = readline(\"hello> \")) != NULL) {\n        /* Do something with the string. */\n        if (line[0] != '\\0' && line[0] != '/') {\n            printf(\"echo: '%s'\\n\", line);\n            add_history(line); /* Add to the history. */\n            write_history(\"history.txt\"); /* Save the history on disk. */\n        } else if (!strncmp(line,\"/historylen\",11)) {\n            /* The \"/historylen\" command will change the history len. */\n            int len = atoi(line+11);\n            history_set_length(len);\n        } else if (line[0] == '/') {\n            printf(\"Unrecognized command: %s\\n\", line);\n        }\n        free(line);\n    }\n    return 0;\n}\n"
  },
  {
    "path": "lib/libreadline/readline/history.h",
    "content": "/*\n * Guerrilla line editing library against the idea that a line editing lib\n * needs to be 20,000 lines of C code.\n *\n * Based on linenoise.c with API modified for compatibility with\n * traditional readline library.\n *\n * ------------------------------------------------------------------------\n *\n * Copyright (c) 2010-2014, Salvatore Sanfilippo <antirez at gmail dot com>\n * Copyright (c) 2010-2013, Pieter Noordhuis <pcnoordhuis at gmail dot com>\n * Copyright (c) 2015, Serge Vakulenko <serge at vak dot ru>\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are\n * met:\n *\n *  *  Redistributions of source code must retain the above copyright\n *     notice, this list of conditions and the following disclaimer.\n *\n *  *  Redistributions in binary form must reproduce the above copyright\n *     notice, this list of conditions and the following disclaimer in the\n *     documentation and/or other materials provided with the distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#ifndef __HISTORY_H\n#define __HISTORY_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/*\n * Place STRING at the end of the history list.\n * The associated data field (if any) is set to NULL.\n */\nvoid add_history(const char *line);\n\n/*\n * Set the maximum length of the current history array.\n */\nint history_set_length(int len);\n\n/*\n * Add the contents of FILENAME to the history list, a line at a time.\n * If FILENAME is NULL, then read from ~/.history.  Returns 0 if\n * successful, or errno if not.\n */\nint read_history(const char *filename);\n\n/*\n * Write the current history to FILENAME.  If FILENAME is NULL,\n * then write the history list to ~/.history.  Values returned\n * are as in read_history ().\n */\nint write_history(const char *filename);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __HISTORY_H */\n"
  },
  {
    "path": "lib/libreadline/readline/readline.h",
    "content": "/*\n * Guerrilla line editing library against the idea that a line editing lib\n * needs to be 20,000 lines of C code.\n *\n * Based on linenoise.c with API modified for compatibility with\n * traditional readline library.\n *\n * ------------------------------------------------------------------------\n *\n * Copyright (c) 2010-2014, Salvatore Sanfilippo <antirez at gmail dot com>\n * Copyright (c) 2010-2013, Pieter Noordhuis <pcnoordhuis at gmail dot com>\n * Copyright (c) 2015, Serge Vakulenko <serge at vak dot ru>\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are\n * met:\n *\n *  *  Redistributions of source code must retain the above copyright\n *     notice, this list of conditions and the following disclaimer.\n *\n *  *  Redistributions in binary form must reproduce the above copyright\n *     notice, this list of conditions and the following disclaimer in the\n *     documentation and/or other materials provided with the distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#ifndef __READLINE_H\n#define __READLINE_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/*\n * Read a line of input.\n * Prompt with PROMPT.\n * A NULL PROMPT means none.\n */\nchar *readline(const char *prompt);\n\n/*\n * Clear the screen.\n * Used to handle Ctrl+L.\n */\nvoid readline_clear_screen(void);\n\n/*\n * Set if to use or not the multi line mode.\n */\nvoid readline_set_multiline(int ml);\n\n/*\n * This routine is used in order to print scan codes on screen\n * for debugging / development purposes.\n */\nvoid readline_print_keycodes(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __READLINE_H */\n"
  },
  {
    "path": "lib/libreadline/readline.c",
    "content": "/*\n * Guerrilla line editing library against the idea that a line editing lib\n * needs to be 20,000 lines of C code.\n * Based on linenoise.c with API modified for compatibility with\n * traditional readline library.\n *\n * Does a number of crazy assumptions that happen to be true in 99.9999% of\n * the 2010 UNIX computers around.\n *\n * You can find the original linenoise source code at:\n *\n *   http://github.com/antirez/linenoise\n *\n * ------------------------------------------------------------------------\n *\n * Copyright (c) 2010-2014, Salvatore Sanfilippo <antirez at gmail dot com>\n * Copyright (c) 2010-2013, Pieter Noordhuis <pcnoordhuis at gmail dot com>\n * Copyright (c) 2015, Serge Vakulenko <serge at vak dot ru>\n *\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are\n * met:\n *\n *  *  Redistributions of source code must retain the above copyright\n *     notice, this list of conditions and the following disclaimer.\n *\n *  *  Redistributions in binary form must reproduce the above copyright\n *     notice, this list of conditions and the following disclaimer in the\n *     documentation and/or other materials provided with the distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n * ------------------------------------------------------------------------\n *\n * References:\n * - http://invisible-island.net/xterm/ctlseqs/ctlseqs.html\n * - http://www.3waylabs.com/nw/WWW/products/wizcon/vt220.html\n *\n * Todo list:\n * - Filter bogus Ctrl+<char> combinations.\n * - Win32 support\n *\n * Bloat:\n * - History search like Ctrl+r in readline?\n *\n * List of escape sequences used by this program, we do everything just\n * with three sequences. In order to be so cheap we may have some\n * flickering effect with some slow terminal, but the lesser sequences\n * the more compatible.\n *\n * EL (Erase Line)\n *    Sequence: ESC [ n K\n *    Effect: if n is 0 or missing, clear from cursor to end of line\n *    Effect: if n is 1, clear from beginning of line to cursor\n *    Effect: if n is 2, clear entire line\n *\n * CUF (CUrsor Forward)\n *    Sequence: ESC [ n C\n *    Effect: moves cursor forward n chars\n *\n * CUB (CUrsor Backward)\n *    Sequence: ESC [ n D\n *    Effect: moves cursor backward n chars\n *\n * The following is used to get the terminal width if getting\n * the width with the TIOCGWINSZ ioctl fails\n *\n * DSR (Device Status Report)\n *    Sequence: ESC [ 6 n\n *    Effect: reports the current cusor position as ESC [ n ; m R\n *            where n is the row and m is the column\n *\n * When multi line mode is enabled, we also use an additional escape\n * sequence. However multi line editing is disabled by default.\n *\n * CUU (Cursor Up)\n *    Sequence: ESC [ n A\n *    Effect: moves cursor up of n chars.\n *\n * CUD (Cursor Down)\n *    Sequence: ESC [ n B\n *    Effect: moves cursor down of n chars.\n *\n * When readline_clear_screen() is called, two additional escape sequences\n * are used in order to clear the screen and position the cursor at home\n * position.\n *\n * CUP (Cursor position)\n *    Sequence: ESC [ H\n *    Effect: moves the cursor to upper left corner\n *\n * ED (Erase display)\n *    Sequence: ESC [ 2 J\n *    Effect: clear the whole screen\n *\n */\n#include <unistd.h>\n#include <stdlib.h>\n#include <stdio.h>\n#include <errno.h>\n#include <string.h>\n#include <strings.h>\n#include <stdlib.h>\n#include <ctype.h>\n#include <sys/types.h>\n#include <sys/ioctl.h>\n#include <unistd.h>\n\n#include \"readline/readline.h\"\n#include \"readline/history.h\"\n\n#ifdef USE_TERMIOS\n#   include <termios.h>\n#else\n#   define termios sgttyb\n#endif\n\n#define LINENOISE_DEFAULT_HISTORY_MAX_LEN 100\n#define LINENOISE_MAX_LINE 4096\nstatic char *unsupported_term[] = {\"dumb\", \"cons25\", \"emacs\", NULL};\n\nstatic struct termios term_orig;    /* In order to restore at exit. */\nstatic int rawmode = 0;             /* For atexit() function to check if restore is needed */\nstatic int mlmode = 0;              /* Multi line mode. Default is single line. */\nstatic int atexit_registered = 0;   /* Register atexit just 1 time. */\nstatic int history_max_len = LINENOISE_DEFAULT_HISTORY_MAX_LEN;\nstatic int history_len = 0;\nstatic char **history = NULL;\n\n/* The linenoiseState structure represents the state during line editing.\n * We pass this state to functions implementing specific editing\n * functionalities. */\nstruct linenoiseState {\n    int ifd;            /* Terminal stdin file descriptor. */\n    int ofd;            /* Terminal stdout file descriptor. */\n    char *buf;          /* Edited line buffer. */\n    size_t buflen;      /* Edited line buffer size. */\n    const char *prompt; /* Prompt to display. */\n    size_t plen;        /* Prompt length. */\n    size_t pos;         /* Current cursor position. */\n    size_t oldpos;      /* Previous refresh cursor position. */\n    size_t len;         /* Current edited line length. */\n    size_t cols;        /* Number of columns in terminal. */\n    size_t maxrows;     /* Maximum num of rows used so far (multiline mode) */\n    int history_index;  /* The history index we are currently editing. */\n};\n\nenum KEY_ACTION{\n    KEY_NULL = 0,       /* NULL */\n    CTRL_A = 1,         /* Ctrl+a */\n    CTRL_B = 2,         /* Ctrl-b */\n    CTRL_C = 3,         /* Ctrl-c */\n    CTRL_D = 4,         /* Ctrl-d */\n    CTRL_E = 5,         /* Ctrl-e */\n    CTRL_F = 6,         /* Ctrl-f */\n    CTRL_H = 8,         /* Ctrl-h */\n    TAB = 9,            /* Tab */\n    CTRL_K = 11,        /* Ctrl+k */\n    CTRL_L = 12,        /* Ctrl+l */\n    ENTER = 13,         /* Enter */\n    CTRL_N = 14,        /* Ctrl-n */\n    CTRL_P = 16,        /* Ctrl-p */\n    CTRL_T = 20,        /* Ctrl-t */\n    CTRL_U = 21,        /* Ctrl+u */\n    CTRL_W = 23,        /* Ctrl+w */\n    ESC = 27,           /* Escape */\n    BACKSPACE = 127,    /* Backspace */\n};\n\nstatic void linenoiseAtExit(void);\nstatic void refreshLine(struct linenoiseState *l);\n\n/* Debugging macro. */\n#if 0\nFILE *lndebug_fp = NULL;\n#define lndebug(...) \\\n    do { \\\n        if (lndebug_fp == NULL) { \\\n            lndebug_fp = fopen(\"/tmp/lndebug.txt\",\"a\"); \\\n            fprintf(lndebug_fp, \\\n            \"[%d %d %d] p: %d, rows: %d, rpos: %d, max: %d, oldmax: %d\\n\", \\\n            (int)l->len,(int)l->pos,(int)l->oldpos,plen,rows,rpos, \\\n            (int)l->maxrows,old_rows); \\\n        } \\\n        fprintf(lndebug_fp, \", \" __VA_ARGS__); \\\n        fflush(lndebug_fp); \\\n    } while (0)\n#else\n#define lndebug(fmt, ...)\n#endif\n\n/* ======================= Low level terminal handling ====================== */\n\n/* Set if to use or not the multi line mode. */\nvoid readline_set_multiline(int ml)\n{\n    mlmode = ml;\n}\n\n/* Return true if the terminal name is in the list of terminals we know are\n * not able to understand basic escape sequences. */\nstatic int isUnsupportedTerm(void)\n{\n    char *term = getenv(\"TERM\");\n    int j;\n\n    if (term == NULL)\n        return 0;\n    for (j = 0; unsupported_term[j]; j++)\n        if (!strcasecmp(term, unsupported_term[j]))\n            return 1;\n    return 0;\n}\n\n/* Raw mode: 1960 magic shit. */\nstatic int enableRawMode(int fd)\n{\n    struct termios raw;\n\n    if (!isatty(STDIN_FILENO))\n        goto fatal;\n    if (!atexit_registered) {\n        atexit(linenoiseAtExit);\n        atexit_registered = 1;\n    }\n\n#ifdef TCSAFLUSH\n    /* Modern POSIX style of tty control. */\n    if (tcgetattr(fd, &term_orig) < 0)\n        goto fatal;\n\n    raw = term_orig;    /* modify the original mode */\n    /* input modes: no break, no CR to NL, no parity check, no strip char,\n     * no start/stop output control. */\n    raw.c_iflag &= ~(BRKINT | ICRNL | INPCK | ISTRIP | IXON);\n    /* output modes - disable post processing */\n    raw.c_oflag &= ~(OPOST);\n    /* control modes - set 8 bit chars */\n    raw.c_cflag |= (CS8);\n    /* local modes - choing off, canonical off, no extended functions,\n     * no signal chars (^Z,^C) */\n    raw.c_lflag &= ~(ECHO | ICANON | IEXTEN); // leave ISIG ON- allow intr's\n    /* control chars - set return condition: min number of bytes and timer.\n     * We want read to return every single byte, without timeout. */\n    raw.c_cc[VMIN] = 1;\n    raw.c_cc[VTIME] = 0; /* 1 byte, no timer */\n\n    /* put terminal in raw mode after flushing */\n    if (tcsetattr(fd, TCSAFLUSH, &raw) < 0)\n        goto fatal;\n#else\n    /* Outdated SysV Unix style of tty control. */\n    if (ioctl(fd, TIOCGETP, &term_orig) < 0)\n        goto fatal;\n\n    raw = term_orig;    /* modify the original mode */\n    raw.sg_flags &= ~(ECHO | CRMOD | XTABS | RAW);\n    raw.sg_flags |= CBREAK;\n\n    /* put terminal in raw mode  */\n    if (ioctl(fd, TIOCSETP, &raw) < 0)\n        goto fatal;\n#endif\n\n    rawmode = 1;\n    return 0;\n\nfatal:\n    errno = ENOTTY;\n    return -1;\n}\n\nstatic void disableRawMode(int fd)\n{\n    /* Don't even check the return value as it's too late. */\n    if (rawmode) {\n#ifdef TCSAFLUSH\n        if (tcsetattr(fd, TCSAFLUSH, &term_orig) < 0)\n            return;\n#else\n        if (ioctl(fd, TIOCSETP, &term_orig) < 0)\n            return;\n#endif\n\n        rawmode = 0;\n    }\n}\n\n/* Use the ESC [6n escape sequence to query the horizontal cursor position\n * and return it. On error -1 is returned, on success the position of the\n * cursor. */\nstatic int getCursorPosition(int ifd, int ofd)\n{\n    char buf[32];\n    int cols, rows;\n    unsigned int i = 0;\n\n    /* Report cursor location */\n    if (write(ofd, \"\\x1b[6n\", 4) != 4)\n        return -1;\n\n    /* Read the response: ESC [ rows ; cols R */\n    while (i < sizeof(buf)-1) {\n        if (read(ifd,buf+i,1) != 1)\n            break;\n        if (buf[i] == 'R')\n            break;\n        i++;\n    }\n    buf[i] = '\\0';\n\n    /* Parse it. */\n    if (buf[0] != ESC || buf[1] != '[')\n        return -1;\n    if (sscanf(buf+2,\"%d;%d\",&rows,&cols) != 2)\n        return -1;\n    return cols;\n}\n\n/* Try to get the number of columns in the current terminal, or assume 80\n * if it fails. */\nstatic int getColumns(int ifd, int ofd)\n{\n    struct winsize ws;\n\n    if (ioctl(1, TIOCGWINSZ, &ws) == -1 || ws.ws_col == 0) {\n        /* ioctl() failed. Try to query the terminal itself. */\n        int start, cols;\n\n        /* Get the initial position so we can restore it later. */\n        start = getCursorPosition(ifd,ofd);\n        if (start == -1)\n            goto failed;\n\n        /* Go to right margin and get position. */\n        if (write(ofd,\"\\x1b[999C\",6) != 6)\n            goto failed;\n        cols = getCursorPosition(ifd,ofd);\n        if (cols == -1)\n            goto failed;\n\n        /* Restore position. */\n        if (cols > start) {\n            char seq[32];\n            snprintf(seq,32,\"\\x1b[%dD\",cols-start);\n            if (write(ofd,seq,strlen(seq)) == -1) {\n                /* Can't recover... */\n            }\n        }\n        return cols;\n    } else {\n        return ws.ws_col;\n    }\n\nfailed:\n    return 80;\n}\n\n/* Clear the screen. Used to handle ctrl+l */\nvoid readline_clear_screen(void)\n{\n    if (write(STDOUT_FILENO,\"\\x1b[H\\x1b[2J\",7) <= 0) {\n        /* nothing to do, just to avoid warning. */\n    }\n}\n\n/* =========================== Line editing ================================= */\n\n/* We define a very simple \"append buffer\" structure, that is an heap\n * allocated string where we can append to. This is useful in order to\n * write all the escape sequences in a buffer and flush them to the standard\n * output in a single call, to avoid flickering effects. */\nstruct abuf {\n    char *b;\n    int len;\n};\n\nstatic void abInit(struct abuf *ab)\n{\n    ab->b = NULL;\n    ab->len = 0;\n}\n\nstatic void abAppend(struct abuf *ab, const char *s, int len)\n{\n    char *new = realloc(ab->b,ab->len+len);\n\n    if (new == NULL)\n        return;\n    memcpy(new+ab->len,s,len);\n    ab->b = new;\n    ab->len += len;\n}\n\nstatic void abFree(struct abuf *ab)\n{\n    free(ab->b);\n}\n\n/* Single line low level line refresh.\n *\n * Rewrite the currently edited line accordingly to the buffer content,\n * cursor position, and number of columns of the terminal. */\nstatic void refreshSingleLine(struct linenoiseState *l)\n{\n    char seq[64];\n    size_t plen = strlen(l->prompt);\n    int fd = l->ofd;\n    char *buf = l->buf;\n    size_t len = l->len;\n    size_t pos = l->pos;\n    struct abuf ab;\n\n    while((plen+pos) >= l->cols) {\n        buf++;\n        len--;\n        pos--;\n    }\n    while (plen+len > l->cols) {\n        len--;\n    }\n\n    abInit(&ab);\n    /* Cursor to left edge */\n    snprintf(seq,64,\"\\r\");\n    abAppend(&ab,seq,strlen(seq));\n    /* Write the prompt and the current buffer content */\n    abAppend(&ab,l->prompt,strlen(l->prompt));\n    abAppend(&ab,buf,len);\n    /* Erase to right */\n    snprintf(seq,64,\"\\x1b[0K\");\n    abAppend(&ab,seq,strlen(seq));\n    /* Move cursor to original position. */\n    snprintf(seq,64,\"\\r\\x1b[%dC\", (int)(pos+plen));\n    abAppend(&ab,seq,strlen(seq));\n    if (write(fd,ab.b,ab.len) == -1) {\n        /* Can't recover from write error. */\n    }\n    abFree(&ab);\n}\n\n/* Multi line low level line refresh.\n *\n * Rewrite the currently edited line accordingly to the buffer content,\n * cursor position, and number of columns of the terminal. */\nstatic void refreshMultiLine(struct linenoiseState *l)\n{\n    char seq[64];\n    int plen = strlen(l->prompt);\n    int rows = (plen+l->len+l->cols-1)/l->cols; /* rows used by current buf. */\n    int rpos = (plen+l->oldpos+l->cols)/l->cols; /* cursor relative row. */\n    int rpos2; /* rpos after refresh. */\n    int col; /* colum position, zero-based. */\n    int old_rows = l->maxrows;\n    int fd = l->ofd, j;\n    struct abuf ab;\n\n    /* Update maxrows if needed. */\n    if (rows > (int)l->maxrows)\n        l->maxrows = rows;\n\n    /* First step: clear all the lines used before. To do so start by\n     * going to the last row. */\n    abInit(&ab);\n    if (old_rows-rpos > 0) {\n        lndebug(\"go down %d\", old_rows-rpos);\n        snprintf(seq,64,\"\\x1b[%dB\", old_rows-rpos);\n        abAppend(&ab,seq,strlen(seq));\n    }\n\n    /* Now for every row clear it, go up. */\n    for (j = 0; j < old_rows-1; j++) {\n        lndebug(\"clear+up\");\n        snprintf(seq,64,\"\\r\\x1b[0K\\x1b[1A\");\n        abAppend(&ab,seq,strlen(seq));\n    }\n\n    /* Clean the top line. */\n    lndebug(\"clear\");\n    snprintf(seq,64,\"\\r\\x1b[0K\");\n    abAppend(&ab,seq,strlen(seq));\n\n    /* Write the prompt and the current buffer content */\n    abAppend(&ab,l->prompt,strlen(l->prompt));\n    abAppend(&ab,l->buf,l->len);\n\n    /* If we are at the very end of the screen with our prompt, we need to\n     * emit a newline and move the prompt to the first column. */\n    if (l->pos &&\n        l->pos == l->len &&\n        (l->pos+plen) % l->cols == 0)\n    {\n        lndebug(\"<newline>\");\n        abAppend(&ab,\"\\n\",1);\n        snprintf(seq,64,\"\\r\");\n        abAppend(&ab,seq,strlen(seq));\n        rows++;\n        if (rows > (int)l->maxrows)\n            l->maxrows = rows;\n    }\n\n    /* Move cursor to right position. */\n    rpos2 = (plen+l->pos+l->cols)/l->cols; /* current cursor relative row. */\n    lndebug(\"rpos2 %d\", rpos2);\n\n    /* Go up till we reach the expected positon. */\n    if (rows-rpos2 > 0) {\n        lndebug(\"go-up %d\", rows-rpos2);\n        snprintf(seq,64,\"\\x1b[%dA\", rows-rpos2);\n        abAppend(&ab,seq,strlen(seq));\n    }\n\n    /* Set column. */\n    col = (plen+(int)l->pos) % (int)l->cols;\n    lndebug(\"set col %d\", 1+col);\n    if (col)\n        snprintf(seq,64,\"\\r\\x1b[%dC\", col);\n    else\n        snprintf(seq,64,\"\\r\");\n    abAppend(&ab,seq,strlen(seq));\n\n    lndebug(\"\\n\");\n    l->oldpos = l->pos;\n\n    if (write(fd,ab.b,ab.len) == -1) {\n        /* Can't recover from write error. */\n    }\n    abFree(&ab);\n}\n\n/* Calls the two low level functions refreshSingleLine() or\n * refreshMultiLine() according to the selected mode. */\nstatic void refreshLine(struct linenoiseState *l)\n{\n    if (mlmode)\n        refreshMultiLine(l);\n    else\n        refreshSingleLine(l);\n}\n\n/* Insert the character 'c' at cursor current position.\n *\n * On error writing to the terminal -1 is returned, otherwise 0. */\nstatic int edit_insert(struct linenoiseState *l, char c)\n{\n    if (l->len < l->buflen) {\n        if (l->len == l->pos) {\n            l->buf[l->pos] = c;\n            l->pos++;\n            l->len++;\n            l->buf[l->len] = '\\0';\n            if ((!mlmode && l->plen+l->len < l->cols) /* || mlmode */) {\n                /* Avoid a full update of the line in the\n                 * trivial case. */\n                if (write(l->ofd,&c,1) == -1)\n                    return -1;\n            } else {\n                refreshLine(l);\n            }\n        } else {\n            memmove(l->buf+l->pos+1,l->buf+l->pos,l->len-l->pos);\n            l->buf[l->pos] = c;\n            l->len++;\n            l->pos++;\n            l->buf[l->len] = '\\0';\n            refreshLine(l);\n        }\n    }\n    return 0;\n}\n\n/* Move cursor on the left. */\nstatic void edit_move_left(struct linenoiseState *l)\n{\n    if (l->pos > 0) {\n        l->pos--;\n        refreshLine(l);\n    }\n}\n\n/* Move cursor on the right. */\nstatic void edit_move_right(struct linenoiseState *l)\n{\n    if (l->pos != l->len) {\n        l->pos++;\n        refreshLine(l);\n    }\n}\n\n/* Move cursor to the start of the line. */\nstatic void edit_move_home(struct linenoiseState *l)\n{\n    if (l->pos != 0) {\n        l->pos = 0;\n        refreshLine(l);\n    }\n}\n\n/* Move cursor to the end of the line. */\nstatic void edit_move_end(struct linenoiseState *l)\n{\n    if (l->pos != l->len) {\n        l->pos = l->len;\n        refreshLine(l);\n    }\n}\n\n/* Substitute the currently edited line with the next or previous history\n * entry as specified by 'dir'. */\n#define LINENOISE_HISTORY_NEXT 0\n#define LINENOISE_HISTORY_PREV 1\n\nstatic void edit_history_next(struct linenoiseState *l, int dir)\n{\n    if (history_len > 1) {\n        /* Update the current history entry before to\n         * overwrite it with the next one. */\n        free(history[history_len - 1 - l->history_index]);\n        history[history_len - 1 - l->history_index] = strdup(l->buf);\n        /* Show the new entry */\n        l->history_index += (dir == LINENOISE_HISTORY_PREV) ? 1 : -1;\n        if (l->history_index < 0) {\n            l->history_index = 0;\n            return;\n        } else if (l->history_index >= history_len) {\n            l->history_index = history_len-1;\n            return;\n        }\n        strncpy(l->buf,history[history_len - 1 - l->history_index],l->buflen);\n        l->buf[l->buflen-1] = '\\0';\n        l->len = l->pos = strlen(l->buf);\n        refreshLine(l);\n    }\n}\n\n/* Delete the character at the right of the cursor without altering the cursor\n * position. Basically this is what happens with the \"Delete\" keyboard key. */\nstatic void edit_delete(struct linenoiseState *l)\n{\n    if (l->len > 0 && l->pos < l->len) {\n        memmove(l->buf+l->pos,l->buf+l->pos+1,l->len-l->pos-1);\n        l->len--;\n        l->buf[l->len] = '\\0';\n        refreshLine(l);\n    }\n}\n\n/* Backspace implementation. */\nstatic void edit_backspace(struct linenoiseState *l)\n{\n    if (l->pos > 0 && l->len > 0) {\n        memmove(l->buf+l->pos-1,l->buf+l->pos,l->len-l->pos);\n        l->pos--;\n        l->len--;\n        l->buf[l->len] = '\\0';\n        refreshLine(l);\n    }\n}\n\n/* Delete the previosu word, maintaining the cursor at the start of the\n * current word. */\nstatic void edit_delete_prev_word(struct linenoiseState *l)\n{\n    size_t old_pos = l->pos;\n    size_t diff;\n\n    while (l->pos > 0 && l->buf[l->pos-1] == ' ')\n        l->pos--;\n    while (l->pos > 0 && l->buf[l->pos-1] != ' ')\n        l->pos--;\n    diff = old_pos - l->pos;\n    memmove(l->buf+l->pos,l->buf+old_pos,l->len-old_pos+1);\n    l->len -= diff;\n    refreshLine(l);\n}\n\n/* This function is the core of the line editing capability of linenoise.\n * It expects 'fd' to be already in \"raw mode\" so that every key pressed\n * will be returned ASAP to read().\n *\n * The resulting string is put into 'buf' when the user type enter, or\n * when ctrl+d is typed.\n *\n * The function returns the length of the current buffer. */\nstatic int edit(int stdin_fd, int stdout_fd, char *buf, size_t buflen, const char *prompt)\n{\n    struct linenoiseState l;\n\n    /* Populate the linenoise state that we pass to functions implementing\n     * specific editing functionalities. */\n    l.ifd = stdin_fd;\n    l.ofd = stdout_fd;\n    l.buf = buf;\n    l.buflen = buflen;\n    l.prompt = prompt;\n    l.plen = strlen(prompt);\n    l.oldpos = l.pos = 0;\n    l.len = 0;\n    l.cols = getColumns(stdin_fd, stdout_fd);\n    l.maxrows = 0;\n    l.history_index = 0;\n\n    /* Buffer starts empty. */\n    l.buf[0] = '\\0';\n    l.buflen--; /* Make sure there is always space for the nulterm */\n\n    /* The latest history entry is always our current buffer, that\n     * initially is just an empty string. */\n    add_history(\"\");\n\n    if (write(l.ofd,prompt,l.plen) == -1)\n        return -1;\n    while(1) {\n        char c;\n        int nread;\n        char seq[3];\n\n        nread = read(l.ifd,&c,1);\n        if (nread <= 0)\n            return l.len;\n\n        switch(c) {\n        case ENTER:    /* enter */\n            history_len--;\n            free(history[history_len]);\n            if (mlmode)\n                edit_move_end(&l);\n            return (int)l.len;\n        case CTRL_C:     /* ctrl-c */\n            errno = EAGAIN;\n            return -1;\n        case BACKSPACE:   /* backspace */\n        case 8:     /* ctrl-h */\n            edit_backspace(&l);\n            break;\n        case CTRL_D:     /* ctrl-d, remove char at right of cursor, or if the\n                            line is empty, act as end-of-file. */\n            if (l.len > 0) {\n                edit_delete(&l);\n            } else {\n                history_len--;\n                free(history[history_len]);\n                return -1;\n            }\n            break;\n        case CTRL_T:    /* ctrl-t, swaps current character with previous. */\n            if (l.pos > 0 && l.pos < l.len) {\n                int aux = buf[l.pos-1];\n                buf[l.pos-1] = buf[l.pos];\n                buf[l.pos] = aux;\n                if (l.pos != l.len-1)\n                    l.pos++;\n                refreshLine(&l);\n            }\n            break;\n        case CTRL_B:     /* ctrl-b */\n            edit_move_left(&l);\n            break;\n        case CTRL_F:     /* ctrl-f */\n            edit_move_right(&l);\n            break;\n        case CTRL_P:    /* ctrl-p */\n            edit_history_next(&l, LINENOISE_HISTORY_PREV);\n            break;\n        case CTRL_N:    /* ctrl-n */\n            edit_history_next(&l, LINENOISE_HISTORY_NEXT);\n            break;\n        case ESC:    /* escape sequence */\n            /* Read the next two bytes representing the escape sequence.\n             * Use two calls to handle slow terminals returning the two\n             * chars at different times. */\n            if (read(l.ifd,seq,1) == -1)\n                break;\n            if (read(l.ifd,seq+1,1) == -1)\n                break;\n\n            /* ESC [ sequences. */\n            if (seq[0] == '[') {\n                if (seq[1] >= '0' && seq[1] <= '9') {\n                    /* Extended escape, read additional byte. */\n                    if (read(l.ifd,seq+2,1) == -1)\n                        break;\n                    if (seq[2] == '~') {\n                        switch(seq[1]) {\n                        case '3': /* Delete key. */\n                            edit_delete(&l);\n                            break;\n                        }\n                    }\n                } else {\n                    switch(seq[1]) {\n                    case 'A': /* Up */\n                        edit_history_next(&l, LINENOISE_HISTORY_PREV);\n                        break;\n                    case 'B': /* Down */\n                        edit_history_next(&l, LINENOISE_HISTORY_NEXT);\n                        break;\n                    case 'C': /* Right */\n                        edit_move_right(&l);\n                        break;\n                    case 'D': /* Left */\n                        edit_move_left(&l);\n                        break;\n                    case 'H': /* Home */\n                        edit_move_home(&l);\n                        break;\n                    case 'F': /* End*/\n                        edit_move_end(&l);\n                        break;\n                    }\n                }\n            }\n\n            /* ESC O sequences. */\n            else if (seq[0] == 'O') {\n                switch(seq[1]) {\n                case 'H': /* Home */\n                    edit_move_home(&l);\n                    break;\n                case 'F': /* End*/\n                    edit_move_end(&l);\n                    break;\n                }\n            }\n            break;\n        default:\n            if (edit_insert(&l,c))\n                return -1;\n            break;\n        case CTRL_U: /* Ctrl+u, delete the whole line. */\n            buf[0] = '\\0';\n            l.pos = l.len = 0;\n            refreshLine(&l);\n            break;\n        case CTRL_K: /* Ctrl+k, delete from current to end of line. */\n            buf[l.pos] = '\\0';\n            l.len = l.pos;\n            refreshLine(&l);\n            break;\n        case CTRL_A: /* Ctrl+a, go to the start of the line */\n            edit_move_home(&l);\n            break;\n        case CTRL_E: /* ctrl+e, go to the end of the line */\n            edit_move_end(&l);\n            break;\n        case CTRL_L: /* ctrl+l, clear screen */\n            readline_clear_screen();\n            refreshLine(&l);\n            break;\n        case CTRL_W: /* ctrl+w, delete previous word */\n            edit_delete_prev_word(&l);\n            break;\n        }\n    }\n    return l.len;\n}\n\n/* This special mode is used by linenoise in order to print scan codes\n * on screen for debugging / development purposes. It is implemented\n * by the linenoise_example program using the --keycodes option. */\nvoid readline_print_keycodes(void)\n{\n    char quit[4];\n\n    printf(\"Linenoise key codes debugging mode.\\n\"\n            \"Press keys to see scan codes. Type 'quit' at any time to exit.\\n\");\n    if (enableRawMode(STDIN_FILENO) == -1)\n        return;\n    memset(quit,' ',4);\n    while(1) {\n        char c;\n        int nread;\n\n        nread = read(STDIN_FILENO,&c,1);\n        if (nread <= 0)\n            continue;\n        memmove(quit,quit+1,sizeof(quit)-1); /* shift string to left. */\n        quit[sizeof(quit)-1] = c; /* Insert current char on the right. */\n        if (memcmp(quit,\"quit\",sizeof(quit)) == 0)\n            break;\n\n        printf(\"'%c' %02x (%d) (type quit to exit)\\n\",\n            isprint(c) ? c : '?', (int)c, (int)c);\n        printf(\"\\r\"); /* Go left edge manually, we are in raw mode. */\n        fflush(stdout);\n    }\n    disableRawMode(STDIN_FILENO);\n}\n\n/* This function calls the line editing function edit() using\n * the STDIN file descriptor set in raw mode. */\nstatic int linenoiseRaw(char *buf, size_t buflen, const char *prompt)\n{\n    int count;\n\n    if (buflen == 0) {\n        errno = EINVAL;\n        return -1;\n    }\n    if (!isatty(STDIN_FILENO)) {\n        /* Not a tty: read from file / pipe. */\n        if (fgets(buf, buflen, stdin) == NULL)\n            return -1;\n        count = strlen(buf);\n        if (count && buf[count-1] == '\\n') {\n            count--;\n            buf[count] = '\\0';\n        }\n    } else {\n        /* Interactive editing. */\n        if (enableRawMode(STDIN_FILENO) == -1)\n            return -1;\n        count = edit(STDIN_FILENO, STDOUT_FILENO, buf, buflen, prompt);\n        disableRawMode(STDIN_FILENO);\n        printf(\"\\n\");\n    }\n    return count;\n}\n\n/* The high level function that is the main API of the linenoise library.\n * This function checks if the terminal has basic capabilities, just checking\n * for a blacklist of stupid terminals, and later either calls the line\n * editing function or uses dummy fgets() so that you will be able to type\n * something even in the most desperate of the conditions. */\nchar *readline(const char *prompt)\n{\n    char buf[LINENOISE_MAX_LINE];\n    int count;\n\n    if (isUnsupportedTerm()) {\n        size_t len;\n\n        printf(\"%s\",prompt);\n        fflush(stdout);\n        if (fgets(buf,LINENOISE_MAX_LINE,stdin) == NULL)\n            return NULL;\n        len = strlen(buf);\n        while(len && (buf[len-1] == '\\n' || buf[len-1] == '\\r')) {\n            len--;\n            buf[len] = '\\0';\n        }\n        return strdup(buf);\n    } else {\n        count = linenoiseRaw(buf,LINENOISE_MAX_LINE,prompt);\n        if (count == -1)\n            return NULL;\n        return strdup(buf);\n    }\n}\n\n/* ================================ History ================================= */\n\n/* Free the history, but does not reset it. Only used when we have to\n * exit() to avoid memory leaks are reported by valgrind & co. */\nstatic void freeHistory(void)\n{\n    if (history) {\n        int j;\n\n        for (j = 0; j < history_len; j++)\n            free(history[j]);\n        free(history);\n    }\n}\n\n/* At exit we'll try to fix the terminal to the initial conditions. */\nstatic void linenoiseAtExit(void)\n{\n    disableRawMode(STDIN_FILENO);\n    freeHistory();\n}\n\n/* This is the API call to add a new entry in the linenoise history.\n * It uses a fixed array of char pointers that are shifted (memmoved)\n * when the history max length is reached in order to remove the older\n * entry and make room for the new one, so it is not exactly suitable for huge\n * histories, but will work well for a few hundred of entries.\n *\n * Using a circular buffer is smarter, but a bit more complex to handle. */\nvoid add_history(const char *line)\n{\n    char *linecopy;\n\n    if (history_max_len == 0)\n        return;\n\n    /* Initialization on first call. */\n    if (history == NULL) {\n        history = malloc(sizeof(char*)*history_max_len);\n        if (history == NULL)\n            return;\n        memset(history,0,(sizeof(char*)*history_max_len));\n    }\n\n    /* Don't add duplicated lines. */\n    if (history_len && !strcmp(history[history_len-1], line))\n        return;\n\n    /* Add an heap allocated copy of the line in the history.\n     * If we reached the max length, remove the older line. */\n    linecopy = strdup(line);\n    if (!linecopy)\n        return;\n    if (history_len == history_max_len) {\n        free(history[0]);\n        memmove(history,history+1,sizeof(char*)*(history_max_len-1));\n        history_len--;\n    }\n    history[history_len] = linecopy;\n    history_len++;\n}\n\n/* Set the maximum length for the history. This function can be called even\n * if there is already some history, the function will make sure to retain\n * just the latest 'len' elements if the new history length value is smaller\n * than the amount of items already inside the history. */\nint history_set_length(int len)\n{\n    char **new;\n\n    if (len < 1)\n        return 0;\n    if (history) {\n        int tocopy = history_len;\n\n        new = malloc(sizeof(char*)*len);\n        if (new == NULL)\n            return 0;\n\n        /* If we can't copy everything, free the elements we'll not use. */\n        if (len < tocopy) {\n            int j;\n\n            for (j = 0; j < tocopy-len; j++) free(history[j]);\n            tocopy = len;\n        }\n        memset(new,0,sizeof(char*)*len);\n        memcpy(new,history+(history_len-tocopy), sizeof(char*)*tocopy);\n        free(history);\n        history = new;\n    }\n    history_max_len = len;\n    if (history_len > history_max_len)\n        history_len = history_max_len;\n    return 1;\n}\n\n/* Save the history in the specified file. On success 0 is returned\n * otherwise -1 is returned. */\nint write_history(const char *filename)\n{\n    FILE *fp = fopen(filename,\"w\");\n    int j;\n\n    if (fp == NULL)\n        return -1;\n    for (j = 0; j < history_len; j++)\n        fprintf(fp,\"%s\\n\",history[j]);\n    fclose(fp);\n    return 0;\n}\n\n/* Load the history from the specified file. If the file does not exist\n * zero is returned and no operation is performed.\n *\n * If the file exists and the operation succeeded 0 is returned, otherwise\n * on error -1 is returned. */\nint read_history(const char *filename)\n{\n    FILE *fp = fopen(filename,\"r\");\n    char buf[LINENOISE_MAX_LINE];\n\n    if (fp == NULL)\n        return -1;\n\n    while (fgets(buf,LINENOISE_MAX_LINE,fp) != NULL) {\n        char *p;\n\n        p = strchr(buf,'\\r');\n        if (!p)\n            p = strchr(buf,'\\n');\n        if (p)\n            *p = '\\0';\n        add_history(buf);\n    }\n    fclose(fp);\n    return 0;\n}\n"
  },
  {
    "path": "lib/libtcl/Makefile",
    "content": "TOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS\t\t+= ${DEFS} -Os -Wall -Wno-pointer-sign\nCFLAGS\t\t+= -DTCL_FILE_CMDS -DTCL_ENV_CMDS\n\nOBJS\t\t= tclget.o tclproc.o tclvar.o tclassem.o \\\n\t\t  tclcmdah.o tclcmdmz.o tclhash.o tclparse.o \\\n\t\t  tclcmdil.o tclbasic.o tclexpr.o tclutil.o \\\n\t\t  regexp.o regsub.o tclenv.o tclglob.o \\\n                  tclunxaz.o tcluxstr.o tcluxutl.o\n\nall:\t\t../libtcl.a\n\n../libtcl.a:    ${OBJS}\n\t\t${AR} cr $@ ${OBJS}\n\t\t$(RANLIB) $@\n\ninstall:\tall\n\nclean:\n\t\trm -f ../libtcl.a *.o *~\n\n###\nregexp.o: regexp.c regexp.h regpriv.h\nregsub.o: regsub.c regexp.h regpriv.h\ntclassem.o: tclassem.c internal.h hash.h\ntclbasic.o: tclbasic.c internal.h hash.h\ntclcmdah.o: tclcmdah.c internal.h hash.h\ntclcmdil.o: tclcmdil.c internal.h hash.h\ntclcmdmz.o: tclcmdmz.c internal.h hash.h regexp.h regpriv.h\ntclenv.o: tclenv.c internal.h hash.h\ntclexpr.o: tclexpr.c internal.h hash.h\ntclget.o: tclget.c internal.h hash.h\ntclglob.o: tclglob.c internal.h hash.h\ntclhash.o: tclhash.c internal.h hash.h\ntclparse.o: tclparse.c internal.h hash.h\ntclproc.o: tclproc.c internal.h hash.h\ntclunxaz.o: tclunxaz.c internal.h hash.h\ntclutil.o: tclutil.c internal.h hash.h regexp.h\ntcluxstr.o: tcluxstr.c internal.h hash.h\ntcluxutl.o: tcluxutl.c internal.h hash.h\ntclvar.o: tclvar.c internal.h hash.h\n"
  },
  {
    "path": "lib/libtcl/doc/AddErrInfo.3",
    "content": "'\\\"\n'\\\" Copyright 1989 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/AddErrInfo.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_AddErrorInfo tcl\n.BS\n.SH NAME\nTcl_AddErrorInfo, Tcl_SetErrorCode, Tcl_UnixError, Tcl_CheckStatus \\- record information about errors\n.SH SYNOPSIS\n.nf\n\\fB#include <tcl.h>\\fR\n.sp\nchar *\n\\fBTcl_AddErrorInfo\\fR(\\fIinterp, message\\fR)\n.sp\n.VS\nvoid\n\\fBTcl_SetErrorCode\\fR(\\fIinterp, element, element, ...\\fR)\n.sp\nchar *\n\\fBTcl_UnixError\\fR(\\fIinterp\\fR)\n.VE\n.SH ARGUMENTS\n.AS Tcl_Interp *message\n.AP Tcl_Interp *interp in\nInterpreter in which to record information.\n.AP char *message in\nIdentifying string to record in \\fBerrorInfo\\fR variable.\n.AP char *element in\n.VS\nString to record as one element of \\fBerrorCode\\fR variable.\nLast \\fIelement\\fR argument must be NULL.\n.VE\n.BE\n\n.SH DESCRIPTION\n.PP\n.VS\nThese procedures are used to manipulate two global variables\nthat hold information about errors.\nThe variable \\fBerrorInfo\\fR holds a stack trace of the\noperations that were in progress when an error occurred, and\nis intended to be human-readable.\nThe variable \\fBerrorCode\\fR holds a list of items that\nare intended to be machine-readable.\nThe first item in \\fBerrorCode\\fR identifies the class of\nerror that occurred (e.g. UNIX means an error occurred in\na Unix system call) and additional elements in \\fBerrorCode\\fR\nhold additional pieces of information that depend on the class.\nSee the Tcl overview manual entry for details on the various\nformats for \\fBerrorCode\\fR.\n.PP\nThe \\fBerrorInfo\\fR variable is gradually built up as an\nerror unwinds through the nested operations.\nEach time an error code is returned to \\fBTcl_Eval\\fR\nit calls the procedure \\fBTcl_AddErrorInfo\\fR to add\nadditional text to \\fBerrorInfo\\fR describing the\ncommand that was being executed when the error occurred.\nBy the time the error has been passed all the way back\nto the application, it will contain a complete trace\nof the activity in progress when the error occurred.\n.PP\nIt is sometimes useful to add additional information to\n\\fBerrorInfo\\fR beyond what can be supplied automatically\nby \\fBTcl_Eval\\fR.\n\\fBTcl_AddErrorInfo\\fR may be used for this purpose:\nits \\fImessage\\fR argument contains an additional\nstring to be appended to \\fBerrorInfo\\fR.\nFor example, the \\fBsource\\fR command calls \\fBTcl_AddErrorInfo\\fR\nto record the name of the file being processed and the\nline number on which the error occurred;  for Tcl procedures, the\nprocedure name and line number within the procedure are recorded,\nand so on.\nThe best time to call \\fBTcl_AddErrorInfo\\fR is just after\n\\fBTcl_Eval\\fR has returned \\fBTCL_ERROR\\fR.\nIn calling \\fBTcl_AddErrorInfo\\fR, you may find it useful to\nuse the \\fBerrorLine\\fR field of the interpreter (see the\n\\fBTcl_Interp\\fR manual entry for details).\n.PP\nThe procedure \\fBTcl_SetErrorCode\\fR is used to set the\n\\fBerrorCode\\fR variable.\nIts \\fIelement\\fR arguments give one or more strings to record\nin \\fBerrorCode\\fR:  each \\fIelement\\fR will become one item\nof a properly-formed Tcl list stored in \\fBerrorCode\\fR.\n\\fBTcl_SetErrorCode\\fR is typically invoked just before returning\nan error.\nIf an error is returned without calling \\fBTcl_SetErrorCode\\fR\nthen the Tcl interpreter automatically sets \\fBerrorCode\\fR\nto \\fBNONE\\fR.\n.PP\n\\fBTcl_UnixError\\fR sets the \\fBerrorCode\\fR variable after an error\nin a UNIX kernel call.\nIt reads the value of the \\fBerrno\\fR C variable and calls\n\\fBTcl_SetErrorCode\\fR to set \\fBerrorCode\\fR in the\n\\fBUNIX\\fR format.\nIn addition, \\fBTcl_UnixError\\fR returns a human-readable\ndiagnostic message for the error (this is the same value that\nwill appear as the third element in \\fBerrorCode\\fR).\nIt may be convenient to include this string as part of the\nerror message returned to the application in \\fIinterp->result\\fR.\n.PP\nIt is important to call the procedures described here rather than\nsetting \\fBerrorInfo\\fR or \\fBerrorCode\\fR directly with\n\\fBTcl_SetVar\\fR.\nThe reason for this is that the Tcl interpreter keeps information\nabout whether these procedures have been called.\nFor example, the first time \\fBTcl_AppendResult\\fR is called\nfor an error, it clears the existing value of \\fBerrorInfo\\fR\nand adds the error message in \\fIinterp->result\\fR to the variable\nbefore appending \\fImessage\\fR;  in subsequent calls, it just\nappends the new \\fImessage\\fR.\nWhen \\fBTcl_SetErrorCode\\fR is called, it sets a flag indicating\nthat \\fBerrorCode\\fR has been set;  this allows the Tcl interpreter\nto set \\fBerrorCode\\fR to \\fBNONE\\fB if it receives an error return\nwhen \\fBTcl_SetErrorCode\\fR hasn't been called.\n.PP\nIf the procedure \\fBTcl_ResetResult\\fR is called, it clears all\nof the state associated with \\fBerrorInfo\\fR and \\fBerrorCode\\fR\n(but it doesn't actually modify the variables).\nIf an error had occurred, this will clear the error state to\nmake it appear as if no error had occurred after all.\n.VE\n\n.SH \"SEE ALSO\"\nTcl_ResetResult, Tcl_Interp\n\n.SH KEYWORDS\nerror, stack, trace, variable\n"
  },
  {
    "path": "lib/libtcl/doc/AssembCmd.3",
    "content": "'\\\"\n'\\\" Copyright 1989-1992 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/AssembCmd.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_AssembleCmd tcl\n.BS\n.SH NAME\nTcl_CreateCmdBuf, Tcl_AssembleCmd, Tcl_DeleteCmdBuf \\- buffer pieces of Tcl commands\n.SH SYNOPSIS\n.nf\n\\fB#include <tcl.h>\\fR\n.sp\nTcl_CmdBuf\n\\fBTcl_CreateCmdBuf\\fR()\n.sp\n\\fBTcl_DeleteCmdBuf\\fR(\\fIbuffer\\fR)\n.sp\nchar *\n.VS\n\\fBTcl_AssembleCmd\\fR(\\fIbuffer\\fR, \\fIstring\\fR)\n.VE\n.sp\nint\n\\fBTcl_CommandComplete\\fR(\\fIcmd\\fR)\n.SH ARGUMENTS\n.AS Tcl_CmdBuf *string;\n.AP Tcl_CmdBuf buffer in\nToken for a command buffer (the result of some previous call to\n\\fBTcl_CreateCmdBuf\\fR).\n.AP char *string in\nAdditional piece of command input to be added to anything currently\nbuffered.\n.AP char *cmd in\n.VS\nCommand string to test for completeness.\n.VE\n.BE\n\n.SH DESCRIPTION\n.PP\nThese procedures provide a convenient mechanism for assembling\nTcl commands from an input source where command boundaries are not\nobvious.  For example, if input is being read from a terminal, a user\nmay type commands that span multiple lines.  In situations like\nthis, \\fBTcl_AssembleCmd\\fR can be called with the individual lines\nas they are received.  It buffers the lines internally and returns\nfull commands when they are complete.\n.PP\nA command buffer is created by calling \\fBTcl_CreateCmdBuf\\fR, and\nit is deleted by calling \\fBTcl_DeleteCmdBuf\\fR.  There may be any\nnumber of command buffers for a particular program or even for a\nparticular interpreter;  in most cases there should be one\nbuffer for each independent source of command input.\n.PP\nWhen input arrives from a source you should call \\fBTcl_AssembleCmd\\fR,\npassing it the new input as the \\fIstring\\fR argument.\n\\fBTcl_AssembleCmd\\fR will add the new input to anything currently\nbuffered in \\fIbuffer\\fR.  If the information now buffered represents\na complete Tcl command (i.e. there are no unclosed quotes, braces,\nbrackets, or variable references),\nthen \\fBTcl_AssembleCmd\\fR returns a pointer to the complete command\nand arranges for the buffer to be cleared on the next call to\n\\fBTcl_AssembleCmd\\fR.  If the command is still incomplete (because,\nfor example, there are unmatched braces) then \\fBTcl_AssembleCmd\\fR\nreturns NULL.  \\fBTcl_AssembleCmd\\fR keeps a private copy of the\ncommand being assembled, so that the caller need not preserve the\ncontents of \\fIstring\\fR between calls to \\fBTcl_AssembleCmd\\fR.\n\\fBTcl_AssembleCmd\\fR supports commands of arbitrary length (up to\nthe total memory limit imposed by the operating system, if any).\n.PP\n.VS\nThe procedure \\fBTcl_CommandComplete\\fR takes a Tcl command string\nas argument and determines whether the command string is complete\nin the sense defined above.\nIf so then it returns 1; otherwise it returns 0.\n.VE\n\n.SH KEYWORDS\nassemble, buffer, partial command\n"
  },
  {
    "path": "lib/libtcl/doc/Backslash.3",
    "content": "'\\\"\n'\\\" Copyright 1989 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/Backslash.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_Backslash tcl\n.BS\n.SH NAME\nTcl_Backslash \\- parse a backslash sequence\n.SH SYNOPSIS\n.nf\n\\fB#include <tcl.h>\\fR\n.sp\nchar\n\\fBTcl_Backslash\\fR(\\fIsrc, countPtr\\fR)\n.SH ARGUMENTS\n.AS char *countPtr\n.AP char *src in\nPointer to a string starting with a backslash.\n.AP int *countPtr out\nIf \\fIcountPtr\\fR isn't NULL, \\fI*countPtr\\fR gets filled\nin with number of characters in the backslash sequence, including\nthe backslash character.\n.BE\n\n.SH DESCRIPTION\n.PP\nThis is a utility procedure used by several of the Tcl\ncommands.  It parses a backslash sequence and returns\nthe single character corresponding to the sequence.\n.VS\nIf the backslash sequence should be replaced by no character\nat all (e.g. backslash-newline) then \\fBTcl_Backslash\\fR returns 0.\n.VE\n\\fBTcl_Backslash\\fR modifies \\fI*countPtr\\fR to contain the number\nof characters in the backslash sequence.\nIf \\fIsrc\\fR doesn't point to a backslash\nsequence understood by Tcl, then Tcl_Backslash returns a backslash\nas its result and \\fI*countPtr\\fR gets set to 1 (in this case the\nbackslash character should not get any special treatment).\n.PP\nSee the Tcl manual entry for information on the valid\nbackslash sequences.\n.VS\nAll of the sequences described in the Tcl\nmanual entry are supported by \\fBTcl_Backslash\\fR.\n.VE\n\n.SH KEYWORDS\nbackslash, parse\n"
  },
  {
    "path": "lib/libtcl/doc/Concat.3",
    "content": "'\\\"\n'\\\" Copyright 1989 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/Concat.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_Concat tcl\n.BS\n.SH NAME\nTcl_Concat \\- concatenate a collection of strings\n.SH SYNOPSIS\n.nf\n\\fB#include <tcl.h>\\fR\n.sp\nchar *\n\\fBTcl_Concat\\fR(\\fIargc, argv\\fR)\n.SH ARGUMENTS\n.AP int argc in\nNumber of strings.\n.AP char *argv[] in\nArray of strings to concatenate.  Must have \\fIargc\\fR entries.\n.BE\n\n.SH DESCRIPTION\n.PP\n\\fBTcl_Concat\\fR is a utility procedure used by several of the\nTcl commands.  Given a collection of strings, it concatenates\nthem together into a single string, with the original strings\nseparated by spaces.  This procedure behaves differently than\n\\fBTcl_Merge\\fR, in that the arguments are simply concatenated:\nno effort is made to ensure proper list structure.\n.VS\nHowever, in most common usage the arguments will all be proper\nlists themselves;  if this is true, then the result will also have\nproper list structure.\n.PP\n\\fBTcl_Concat\\fR eliminates leading and trailing white space as it\ncopies strings from \\fBargv\\fR to the result.  If an element of\n\\fBargv\\fR consists of nothing but white space, then that string\nis ignored entirely.  This white-space removal was added to make\nthe output of the \\fBconcat\\fR command cleaner-looking.\n.VE\n.PP\nThe result string is dynamically allocated\nusing \\fBmalloc()\\fR;  the caller must eventually release the space\nby calling \\fBfree()\\fR.\n\n.SH KEYWORDS\nconcatenate, strings\n"
  },
  {
    "path": "lib/libtcl/doc/CrtCommand.3",
    "content": "'\\\"\n'\\\" Copyright 1989 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/CrtCommand.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_CreateCommand tcl\n.BS\n.SH NAME\nTcl_CreateCommand, Tcl_DeleteCommand \\- define application-specific command bindings\n.SH SYNOPSIS\n.nf\n\\fB#include <tcl.h>\\fR\n.sp\n\\fBTcl_CreateCommand\\fR(\\fIinterp, cmdName, proc, clientData, deleteProc\\fR)\n.sp\nint\n\\fBTcl_DeleteCommand\\fR(\\fIinterp, cmdName\\fR)\n.SH ARGUMENTS\n.AS Tcl_CmdDeleteProc (*deleteProc)()\n.AP Tcl_Interp *interp in\nInterpreter in which to create new command.\n.AP char *cmdName in\nName of command to create or delete.\n.AP Tcl_CmdProc *proc in\nImplementation of new command:  \\fIproc\\fR will be called whenever\n\\fIcmdName\\fR is invoked as a command.\n.AP ClientData clientData in\nArbitrary one-word value to pass to \\fIproc\\fR and \\fIdeleteProc\\fR.\n.AP Tcl_CmdDeleteProc *deleteProc in\nProcedure to call before \\fIcmdName\\fR is deleted from the interpreter;\nallows for command-specific cleanup.  If NULL, then no procedure is\ncalled before the command is deleted.\n.BE\n\n.SH DESCRIPTION\n.PP\n\\fBTcl_CreateCommand\\fR defines a new command in \\fIinterp\\fR and associates\nit with procedure \\fIproc\\fR such that whenever \\fIcmdName\\fR is\ninvoked as a Tcl command (via a call to \\fBTcl_Eval\\fR) the Tcl interpreter\nwill call \\fIproc\\fR\nto process the command.  If there is already a command \\fIcmdName\\fR\nassociated with the interpreter, it is deleted.  \\fIProc\\fP should\nhave arguments and result that match the type \\fBTcl_CmdProc\\fR:\n.nf\n.RS\ntypedef int Tcl_CmdProc(\n.RS\nClientData \\fIclientData\\fR,\nTcl_Interp *\\fIinterp\\fR,\nint \\fIargc\\fR,\nchar *\\fIargv\\fR[]);\n.RE\n.RE\n.fi\nWhen \\fIproc\\fR is invoked the \\fIclientData\\fP and \\fIinterp\\fR\nparameters will be copies of the \\fIclientData\\fP and \\fIinterp\\fR\narguments given to \\fBTcl_CreateCommand\\fR.\nTypically, \\fIclientData\\fR points to an application-specific\ndata structure that describes what to do when the command procedure\nis invoked.  \\fIArgc\\fR and \\fIargv\\fR describe the arguments to\nthe command, \\fIargc\\fR giving the number of arguments (including\nthe command name) and \\fIargv\\fR giving the values of the arguments\nas strings.  The \\fIargv\\fR array will contain \\fIargc\\fR+1 values;\nthe first \\fIargc\\fR values point to the argument strings, and the\nlast value is NULL.\n.PP\n\\fIProc\\fR must return an integer code that is either \\fBTCL_OK\\fR, \\fBTCL_ERROR\\fR,\n\\fBTCL_RETURN\\fR, \\fBTCL_BREAK\\fR, or \\fBTCL_CONTINUE\\fR.  See the Tcl overview man page\nfor details on what these codes mean.  Most normal commands will only\nreturn \\fBTCL_OK\\fR or \\fBTCL_ERROR\\fR.  In addition, \\fIproc\\fR must set\n\\fIinterp->result\\fR to point to a string value;\nin the case of a \\fBTCL_OK\\fR return code this gives the result\nof the command, and in the case of \\fBTCL_ERROR\\fR it gives an error message.\nThe \\fBTcl_SetResult\\fR procedure provides an easy interface for setting\nthe return value;  for complete details on how the \\fIinterp->result\\fR\nfield is managed, see the \\fBTcl_Interp\\fR man page.\nBefore invoking a command procedure,\n\\fBTcl_Eval\\fR sets \\fIinterp->result\\fR to point to an empty string, so simple\ncommands can return an empty result by doing nothing at all.\n.PP\nThe contents of the \\fIargv\\fR array are copies made by the Tcl interpreter\nfor the use of \\fIproc\\fR.  \\fIProc\\fR may alter any of the strings\nin \\fIargv\\fR.  However, the \\fIargv\\fR array\nis recycled as soon as \\fIproc\\fR returns, so \\fIproc\\fR must not set\n\\fIinterp->result\\fR to point anywhere within the \\fIargv\\fR values\n(call Tcl_SetResult\nwith status \\fBTCL_VOLATILE\\fR if you want to return something from the\n\\fIargv\\fR array).\n.PP\n\\fIDeleteProc\\fR will be invoked when (if) \\fIcmdName\\fR is deleted.\nThis can occur through a call to \\fBTcl_DeleteCommand\\fR or \\fBTcl_DeleteInterp\\fR,\nor by replacing \\fIcmdName\\fR in another call to Tcl_CreateCommand.\n\\fIDeleteProc\\fR is invoked before the command is deleted, and gives the\napplication an opportunity to release any structures associated\nwith the command.  \\fIDeleteProc\\fR should have arguments and\nresult that match the type \\fBTcl_CmdDeleteProc\\fR:\n.nf\n.RS\n.sp\ntypedef void Tcl_CmdDeleteProc(ClientData \\fIclientData\\fR);\n.sp\n.RE\n.fi\nThe \\fIclientData\\fR argument will be the same as the \\fIclientData\\fR\nargument passed to \\fBTcl_CreateCommand\\fR.\n.PP\n\\fBTcl_DeleteCommand\\fR deletes a command from a command interpreter.\nOnce the call completes, attempts to invoke \\fIcmdName\\fR in\n\\fIinterp\\fR will result in errors.\nIf \\fIcmdName\\fR isn't bound as a command in \\fIinterp\\fR then\n\\fBTcl_DeleteCommand\\fR does nothing and returns -1;  otherwise\nit returns 0.\nThere are no restrictions on \\fIcmdName\\fR:  it may refer to\na built-in command, an application-specific command, or a Tcl procedure.\n\n.SH KEYWORDS\nbind, command, create, delete, interpreter\n"
  },
  {
    "path": "lib/libtcl/doc/CrtInterp.3",
    "content": "'\\\"\n'\\\" Copyright 1989 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/CrtInterp.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_CreateInterp tcl\n.BS\n.SH NAME\nTcl_CreateInterp, Tcl_DeleteInterp \\- create and delete Tcl command interpreters\n.SH SYNOPSIS\n.nf\n\\fB#include <tcl.h>\\fR\n.sp\nTcl_Interp *\n\\fBTcl_CreateInterp\\fR()\n.sp\n\\fBTcl_DeleteInterp\\fR(\\fIinterp\\fR)\n.SH ARGUMENTS\n.AS Tcl_Interp *interp\n.AP Tcl_Interp *interp in\nToken for interpreter to be destroyed.\n.BE\n\n.SH DESCRIPTION\n.PP\n\\fBTcl_CreateInterp\\fR creates a new interpreter structure and returns\na token for it.  The token is required in calls to most other Tcl\nprocedures, such as \\fBTcl_CreateCommand\\fR, \\fBTcl_Eval\\fR, and\n\\fBTcl_DeleteInterp\\fR.\nClients are only allowed to access a few of the fields of\nTcl_Interp structures;  see the Tcl_Interp\nand \\fBTcl_CreateCommand\\fR man pages for details.\nThe new interpreter is initialized with no defined variables and only\nthe built-in Tcl commands.  To bind in additional commands, call\n\\fBTcl_CreateCommand\\fR.\n.PP\n\\fBTcl_DeleteInterp\\fR destroys a command interpreter and releases all of\nthe resources associated with it, including variables, procedures,\nand application-specific command bindings.  After \\fBTcl_DeleteInterp\\fR\nreturns the caller should never again use the \\fIinterp\\fR token.\n\n.SH KEYWORDS\ncommand, create, delete, interpreter\n"
  },
  {
    "path": "lib/libtcl/doc/CrtPipelin.3",
    "content": "'\\\"\n'\\\" Copyright 1989 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/CrtPipelin.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_CreatePipeline tcl\n.VS\n.BS\n.SH NAME\nTcl_CreatePipeline \\- create one or more child processes, with I/O redirection\n.SH SYNOPSIS\n.nf\n\\fB#include <tcl.h>\\fR\n.sp\nint\n\\fBTcl_CreatePipeline\\fR(\\fIinterp, argc, argv, pidArrayPtr, inPipePtr, outPipePtr, errFilePtr\\fR)\n.SH ARGUMENTS\n.AS Tcl_Interp **pidArrayPtr\n.AP Tcl_Interp *interp in\nInterpreter to use for error reporting.\n.AP int argc in\nNumber of strings in \\fIargv\\fR array.\n.AP char **argv in\nArray of strings describing command(s) and I/O redirection.\n.AP int **pidArrayPtr out\nThe value at \\fI*pidArrayPtr\\fR is modified to hold a pointer to\nan array of process identifiers.  The array is dynamically\nallocated and must be freed by the caller.\n.AP char *inPipePtr out\nIf this argument is NULL then standard input for the first command\nin the pipeline comes from the current standard input.\nIf \\fIinPipePtr\\fR is not NULL then \\fBTcl_CreatePipeline\\fR will\ncreate a pipe, arrange for it to be used for standard input\nto the first command,\nand store a file id for writing to that pipe at \\fI*inPipePtr\\fR.\nIf the command specified its own input using redirection, then\nno pipe is created and -1 is stored at \\fI*inPipePtr\\fR.\n.AP char *outPipePtr out\nIf this argument is NULL then standard output for the last command\nin the pipeline goes to the current standard output.\nIf \\fIoutPipePtr\\fR is not NULL then \\fBTcl_CreatePipeline\\fR will\ncreate a pipe, arrange for it to be used for standard output from\nthe last command, and store a file id for reading from that\npipe at \\fI*outPipePtr\\fR.\nIf the command specified its own output using redirection then\nno pipe is created and -1 is stored at \\fI*outPipePtr\\fR.\n.AP char *errFilePtr out\nIf this argument is NULL then error output for all the commands\nin the pipeline will go to the current standard error file.\nIf \\fIerrFilePtr\\fR is not NULL, error output from all the commands\nin the pipeline will go to a temporary file created by\n\\fBTcl_CreatePipeline\\fR.\nA file id to read from that file will be stored at \\fI*errFilePtr\\fR.\nThe file will already have been removed, so closing the file\ndescriptor at \\fI*errFilePtr\\fR will cause the file to be flushed\ncompletely.\n.BE\n\n.SH DESCRIPTION\n.PP\n\\fBTcl_CreatePipeline\\fR processes the \\fIargv\\fR array and sets\nup one or more child processes in a pipeline configuration.\n\\fBTcl_CreatePipeline\\fR handles pipes specified with ``|'',\ninput redirection specified with ``<'' or ``<<'', and output\nredirection specified with ``>'';  see the documentation for\nthe \\fBexec\\fR command for details on these specifications.\nThe return value from \\fBTcl_CreatePipeline\\fR is a count of\nthe number of child processes created;  the process identifiers\nfor those processes are stored in a \\fImalloc\\fR-ed array and\na pointer to that array is stored at \\fI*pidArrayPtr\\fR.\nIt is the caller's responsibility to free the array when finished\nwith it.\n.PP\nIf the \\fIinPipePtr\\fR, \\fIoutPipePtr\\fR, and \\fIerrFilePtr\\fR\narguments are NULL then the pipeline's standard input, standard\noutput, and standard error are taken from the corresponding\nstreams of the process.  Non-NULL values may be specified for\nthese arguments to use pipes for standard input and standard\noutput and a file for standard error.  \\fBTcl_CreatePipeline\\fR\nwill create the requested pipes or file and return file identifiers\nthat may be used to read or write them.  It is the caller's\nresponsibility to close all of these files when they are no\nlonger needed.  If \\fIargv\\fR specifies redirection for standard\ninput or standard output, then pipes will not be created even\nif requested by the \\fIinPipePtr\\fR and \\fIoutPipePtr\\fR\narguments.\n.PP\nIf an error occurs in \\fBTcl_CreatePipeline\\fR (e.g. ``|'' or\n``<'' was the last argument in \\fIargv\\fR, or it wasn't possible\nto fork off a child), then -1 is returned\nand \\fIinterp->result\\fR is set to an error message.\n\n.SH \"SEE ALSO\"\n\\fBTcl_WaitPids\\fR, \\fBTcl_DetachPids\\fR\n\n.SH KEYWORDS\nbackground, child, detach, fork, process, status, wait\n.VE\n"
  },
  {
    "path": "lib/libtcl/doc/CrtTrace.3",
    "content": "'\\\"\n'\\\" Copyright 1989 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/CrtTrace.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_CreateTrace tcl\n.BS\n.SH NAME\nTcl_CreateTrace, Tcl_DeleteTrace \\- arrange for command execution to be traced\n.SH SYNOPSIS\n.nf\n\\fB#include <tcl.h>\\fR\n.sp\nTcl_Trace\n\\fBTcl_CreateTrace\\fR(\\fIinterp, level, proc, clientData\\fR)\n.sp\n\\fBTcl_DeleteTrace\\fR(\\fIinterp, trace\\fR)\n.SH ARGUMENTS\n.AS Tcl_CmdTraceProc (clientData)()\n.AP Tcl_Interp *interp in\nInterpreter containing command to be traced or untraced.\n.AP int level in\nOnly commands at or below this nesting level will be traced.  1 means\ntop-level commands only, 2 means top-level commands or those that are\ninvoked as immediate consequences of executing top-level commands\n(procedure bodies, bracketed commands, etc.) and so on.\n.AP Tcl_CmdTraceProc *proc in\nProcedure to call for each command that's executed.  See below for\ndetails on the calling sequence.\n.AP ClientData clientData in\nArbitrary one-word value to pass to \\fIproc\\fR.\n.AP Tcl_Trace trace in\nToken for trace to be removed (return value from previous call\nto \\fBTcl_CreateTrace\\fR).\n.BE\n\n.SH DESCRIPTION\n.PP\n\\fBTcl_CreateTrace\\fR arranges for command tracing.  From now on, \\fIproc\\fR\nwill be invoked before Tcl calls command procedures to process\ncommands in \\fIinterp\\fR.  The return value from\n\\fBTcl_CreateTrace\\fR is a token for the trace,\nwhich may be passed to \\fBTcl_DeleteTrace\\fR to remove the trace.  There may\nbe many traces in effect simultaneously for the same command interpreter.\n.PP\n\\fIProc\\fR should have arguments and result that match the\ntype \\fBTcl_CmdTraceProc\\fR:\n.nf\n.sp\n.RS\ntypedef void Tcl_CmdTraceProc(\n.RS\nClientData \\fIclientData\\fR,\nTcl_Interp *\\fIinterp\\fR,\nint \\fIlevel\\fR,\nchar *\\fIcommand\\fR,\nTcl_CmdProc *\\fIcmdProc\\fR,\nClientData \\fIcmdClientData\\fR,\nint \\fIargc\\fR,\nchar *\\fIargv\\fR[]));\n.sp\n.RE\n.RE\n.fi\nThe \\fIclientData\\fP and \\fIinterp\\fP parameters are\ncopies of the corresponding arguments given to \\fBTcl_CreateTrace\\fR.\n\\fIClientData\\fR typically points to an application-specific\ndata structure that describes what to do when \\fIproc\\fR\nis invoked.  \\fILevel\\fR gives the nesting level of the command\n(1 for top-level commands passed to \\fBTcl_Eval\\fR by the application,\n2 for the next-level commands passed to \\fBTcl_Eval\\fR as part of parsing\nor interpreting level-1 commands, and so on).  \\fICommand\\fR\npoints to a string containing the text of the\ncommand, before any argument substitution.\n\\fICmdProc\\fR contains the address of the command procedure that\nwill be called to process the command (i.e. the \\fIproc\\fR argument\nof some previous call to \\fBTcl_CreateCommand\\fR) and \\fIcmdClientData\\fR\ncontains the associated client data for \\fIcmdProc\\fR (the \\fIclientData\\fR\nvalue passed to \\fBTcl_CreateCommand\\fR).  \\fIArgc\\fR and \\fIargv\\fR give\nthe final argument information that will be passed to \\fIcmdProc\\fR, after\ncommand, variable, and backslash substitution.\n\\fIProc\\fR must not modify the \\fIcommand\\fR or \\fIargv\\fR strings.\n.PP\nTracing will only occur for commands at nesting level less than\nor equal to the \\fIlevel\\fR parameter (i.e. the \\fIlevel\\fR\nparameter to \\fIproc\\fR will always be less than or equal to the\n\\fIlevel\\fR parameter to \\fBTcl_CreateTrace\\fR).\n.PP\nCalls to \\fIproc\\fR will be made by the Tcl parser immediately before\nit calls the command procedure for the command (\\fIcmdProc\\fR).  This\noccurs after argument parsing and substitution, so tracing for\nsubstituted commands occurs before tracing of the commands\ncontaining the substitutions.  If there is a syntax error in a\ncommand, or if there is no command procedure associated with a\ncommand name, then no tracing will occur for that command.  If a\nstring passed to Tcl_Eval contains multiple commands (bracketed, or\non different lines) then multiple calls to \\fIproc\\fR will occur,\none for each command.  The \\fIcommand\\fR string for each of these\ntrace calls will reflect only a single command, not the entire string\npassed to Tcl_Eval.\n.PP\n\\fBTcl_DeleteTrace\\fR removes a trace, so that no future calls will be\nmade to the procedure associated with the trace.  After \\fBTcl_DeleteTrace\\fR\nreturns, the caller should never again use the \\fItrace\\fR token.\n\n.SH KEYWORDS\ncommand, create, delete, interpreter, trace\n"
  },
  {
    "path": "lib/libtcl/doc/Eval.3",
    "content": "'\\\"\n'\\\" Copyright 1989 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/Eval.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_Eval tcl\n.BS\n.SH NAME\nTcl_Eval, Tcl_VarEval, Tcl_EvalFile, Tcl_GlobalEval \\- execute Tcl commands\n.SH SYNOPSIS\n.nf\n\\fB#include <tcl.h>\\fR\n.sp\nint\n\\fBTcl_Eval\\fR(\\fIinterp, cmd, flags, termPtr\\fR)\n.sp\nint\n\\fBTcl_VarEval\\fR(\\fIinterp, string, string, ... \\fB(char *) NULL\\fR)\n.sp\nint\n\\fBTcl_EvalFile\\fR(\\fIinterp, fileName\\fR)\n.sp\n.VS\nint\n\\fBTcl_GlobalEval\\fR(\\fIinterp, cmd\\fR)\n.VE\n.SH ARGUMENTS\n.AS Tcl_Interp **termPtr;\n.AP Tcl_Interp *interp in\nInterpreter in which to execute the command.  String result will be\nstored in \\fIinterp->result\\fR.\n.AP char *cmd in\nCommand (or sequence of commands) to execute.  Must be in writable\nmemory (Tcl_Eval makes temporary modifications to the command).\n.AP int flags in\nEither \\fBTCL_BRACKET_TERM\\fR or 0.\nIf 0, then \\fBTcl_Eval\\fR will process commands from \\fIcmd\\fR until\nit reaches the null character at the end of the string.\nIf \\fBTCL_BRACKET_TERM\\fR,\nthen \\fBTcl_Eval\\fR will process comands from \\fIcmd\\fR until either it\nreaches a null character or it encounters a close bracket that isn't\nbackslashed or enclosed in braces, at which point it will return.\nUnder normal conditions, \\fIflags\\fR should be 0.\n.AP char **termPtr out\nIf \\fItermPtr\\fR is non-NULL, \\fBTcl_Eval\\fR fills in *\\fItermPtr\\fR with\nthe address of the character just after the last one in the last command\nsuccessfully executed (normally the null character at the end of \\fIcmd\\fR).\nIf an error occurs in the first command in \\fIcmd\\fR, then \\fI*termPtr\\fR\nwill be set to \\fIcmd\\fR.\n.AP char *string in\nString forming part of Tcl command.\n.AP char *fileName in\nName of file containing Tcl command string.\n.BE\n\n.SH DESCRIPTION\n.PP\nAll four of these procedures execute Tcl commands.\n\\fBTcl_Eval\\fR is the core procedure:  it parses commands\nfrom \\fIcmd\\fR and executes them in\norder until either an error occurs or \\fBTcl_Eval\\fR reaches a terminating\ncharacter (']' or '\\e0', depending on the value of \\fIflags\\fR).\nThe return value from \\fBTcl_Eval\\fR is one\nof the Tcl return codes \\fBTCL_OK\\fR, \\fBTCL_ERROR\\fR, \\fBTCL_RETURN\\fR, \\fBTCL_BREAK\\fR, or\n\\fBTCL_CONTINUE\\fR, and \\fIinterp->result\\fR will point to\na string with additional information (result value or error message).\nThis return information corresponds to the last command executed from\n\\fIcmd\\fR.\n.PP\n\\fBTcl_VarEval\\fR takes any number of string arguments\nof any length, concatenates\nthem into a single string, then calls \\fBTcl_Eval\\fR to\nexecute that string as a Tcl command.\nIt returns the result of the command and also modifies\n\\fIinterp->result\\fR in the usual fashion for Tcl commands.  The\nlast argument to \\fBTcl_VarEval\\fR must be NULL to indicate the end\nof arguments.\n.PP\n\\fBTcl_EvalFile\\fR reads the file given by \\fIfileName\\fR and evaluates\nits contents as a Tcl command by calling \\fBTcl_Eval\\fR.  It returns\na standard Tcl result that reflects the result of evaluating the\nfile.\nIf the file couldn't be read then a Tcl error is returned to describe\nwhy the file couldn't be read.\n.PP\n.VS\n\\fBTcl_GlobalEval\\fR is similar to \\fBTcl_Eval\\fR except that it\nprocesses the command at global level.\nThis means that the variable context for the command consists of\nglobal variables only (it ignores any Tcl procedure that is active).\nThis produces an effect similar to the Tcl command ``\\fBuplevel 0\\fR''.\n.VE\n.PP\nDuring the processing of a Tcl command it is legal to make nested\ncalls to evaluate other commands (this is how conditionals, loops,\nand procedures are implemented).\nIf a code other than\n\\fBTCL_OK\\fR is returned from a nested \\fBTcl_Eval\\fR invocation, then the\ncaller should normally return immediately, passing that same\nreturn code back to its caller, and so on until the top-level application is\nreached.  A few commands, like \\fBfor\\fR, will check for certain\nreturn codes, like \\fBTCL_BREAK\\fR and \\fBTCL_CONTINUE\\fR, and process them\nspecially without returning.\n.PP\n\\fBTcl_Eval\\fR keeps track of how many nested Tcl_Eval invocations are\nin progress for \\fIinterp\\fR.\nIf a code of \\fBTCL_RETURN\\fR, \\fBTCL_BREAK\\fR, or \\fBTCL_CONTINUE\\fR is\nabout to be returned from the topmost \\fBTcl_Eval\\fR invocation for\n\\fIinterp\\fR, then \\fBTcl_Eval\\fR converts the return code to \\fBTCL_ERROR\\fR\nand sets \\fIinterp->result\\fR to point to an error message indicating that\nthe \\fBreturn\\fR, \\fBbreak\\fR, or \\fBcontinue\\fR command was\ninvoked in an inappropriate place.  This means that top-level\napplications should never see a return code from \\fBTcl_Eval\\fR other then\n\\fBTCL_OK\\fR or \\fBTCL_ERROR\\fR.\n\n.SH KEYWORDS\ncommand, execute, file, global, interpreter, variable\n"
  },
  {
    "path": "lib/libtcl/doc/ExprLong.3",
    "content": "'\\\"\n'\\\" Copyright 1989 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/ExprLong.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_ExprLong tcl\n.BS\n.SH NAME\nTcl_ExprLong, Tcl_ExprDouble, Tcl_ExprBool, Tcl_ExprString \\- evaluate an expression\n.SH SYNOPSIS\n.nf\n\\fB#include <tcl.h>\\fR\n.VS\n.sp\nint\n\\fBTcl_ExprLong\\fR(\\fIinterp, string, longPtr\\fR)\n.sp\nint\n\\fBTcl_ExprDouble\\fR(\\fIinterp, string, doublePtr\\fR)\n.sp\nint\n\\fBTcl_ExprBoolean\\fR(\\fIinterp, string, booleanPtr\\fR)\n.sp\nint\n\\fBTcl_ExprString\\fR(\\fIinterp, string\\fR)\n.SH ARGUMENTS\n.AS Tcl_Interp *booleanPtr\n.AP Tcl_Interp *interp in\nInterpreter in whose context to evaluate \\fIstring\\fR.\n.AP char *string in\nExpression to be evaluated.  Must be in writable memory (the expression\nparser makes temporary modifications to the string during parsing, which\nit undoes before returning).\n.AP long *longPtr out\nPointer to location in which to store the integer value of the\nexpression.\n.AP int *doublePtr out\nPointer to location in which to store the floating-point value of the\nexpression.\n.AP int *booleanPtr out\nPointer to location in which to store the 0/1 boolean value of the\nexpression.\n.BE\n\n.SH DESCRIPTION\n.PP\nThese four procedures all evaluate a string expression, returning\nthe result in one of four different forms.\nThe expression is given by the \\fIstring\\fR argument, and it\ncan have any of the forms accepted by the \\fBexpr\\fR command.\nThe \\fIinterp\\fR argument refers to an interpreter used to\nevaluate the expression (e.g. for variables and nested Tcl\ncommands) and to return error information.  \\fIInterp->result\\fR\nis assumed to be initialized in the standard fashion when any\nof the procedures are invoked.\n.PP\nFor all of these procedures the return value is a standard\nTcl result:  \\fBTCL_OK\\fR means the expression was succesfully\nevaluated, and \\fBTCL_ERROR\\fR means that an error occurred while\nevaluating the expression.  If \\fBTCL_ERROR\\fR is returned then\n\\fIinterp->result\\fR will hold a message describing the error.\nIf an error occurs while executing a Tcl command embedded in\n\\fIstring\\fR, then that error will be returned.\n.PP\nIf the expression is successfully evaluated, then its value will\nbe returned in one of four forms, depending on which procedure\nis invoked.\n\\fBTcl_ExprLong\\fR stores an integer value at \\fI*longPtr\\fR.\nIf the expression's actual value was a floating-point number,\nthen it is truncated to an integer.\nIf the expression's actual value was a non-numeric string then\nan error is returned.\n.PP\n\\fBTcl_ExprDouble\\fR stores a floating-point value at \\fI*doublePtr\\fR.\nIf the expression's actual value was an integer, it is converted to\nfloating-point.\nIf the expression's actual value was a non-numeric string then\nan error is returned.\n.PP\n\\fBTcl_ExprBoolean\\fR stores a 0/1 integer value at \\fI*booleanPtr\\fR.\nIf the expression's actual value was an integer or floating-point\nnumber, then \\fBTcl_ExprBoolean\\fR stores 0 at \\fI*booleanPtr\\fR if\nthe value was zero and 1 otherwise.\nIf the expression's actual value was a non-numeric string then\nan error is returned.\n.PP\n\\fBTcl_ExprString\\fR returns the value of the expression as a\nstring stored in \\fIinterp->result\\fR.\nIf the expression's actual value was an integer or floating-point\nnumber, then \\fBTcl_ExprString\\fR converts it to string (using \\fBsprintf\\fR\nwith a ``%d'' or ``%g'' converter).\n\n.SH KEYWORDS\nboolean, double, evaluate, expression, integer, string\n.VE\n"
  },
  {
    "path": "lib/libtcl/doc/Fork.3",
    "content": "'\\\"\n'\\\" Copyright 1989 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/Fork.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_Fork tcl\n.BS\n.VS\n.SH NAME\nTcl_Fork, Tcl_WaitPids, Tcl_DetachPids \\- manage child processes\n.SH SYNOPSIS\n.nf\n\\fB#include <tcl.h>\\fR\n.sp\nint\n\\fBTcl_Fork\\fR( )\n.sp\nint\n\\fBTcl_WaitPids\\fR(\\fInumPids, pidPtr, statusPtr\\fR)\n.sp\nint\n\\fBTcl_DetachPids\\fR(\\fInumPids, pidPtr\\fR)\n.SH ARGUMENTS\n.AS int *statusPtr\n.AP int numPids in\nNumber of process ids contained in the array pointed to by \\fIpidPtr\\fR.\n.AP int *pidPtr in\nAddress of array containing \\fInumPids\\fR process ids.\n.AP int *statusPtr out\nAddress of place to store status returned by exited/suspended process.\n.BE\n\n.SH DESCRIPTION\n.PP\nThese procedures keep track of child processes in order to make it\neasier for one application to manage several children.\nIf an application uses\nthe UNIX \\fIfork\\fR and \\fIwait\\fR kernel calls directly,\nproblems occur in situations like the following:\n.IP [1]\nOne part of an application creates child C1.  It plans to\nlet the child run in background, then later wait for it to\ncomplete.\n.IP [2]\nSome other part of the application creates another child C2,\nnot knowing anything about C1.\n.IP [3]\nThe second part of the application uses \\fIwait\\fR to wait for C2\nto complete.\n.IP [4]\nC1 completes before C2, so C1 is returned by the\n\\fIwait\\fR kernel call.\n.IP [5]\nThe second part of the application doesn't recognize C1, so it\nignores it and calls \\fIwait\\fR again.  This time C2\ncompletes.\n.IP [6]\nThe first part of the application eventually decides to wait\nfor its child to complete.  When it calls \\fIwait\\fR there are\nno children left, so \\fIwait\\fR returns an error and the\napplication never gets to examine the exit status for C1.\n.PP\nThe procedures \\fBTcl_Fork\\fR, \\fBTcl_WaitPids\\fR, and \\fBTcl_DetachPids\\fR\nget around this problem by keeping a table of child processes and\ntheir exit statuses.\nThey also provide a more flexible waiting\nmechanism than the \\fIwait\\fR kernel call.\nTcl-based applications should never call \\fIfork\\fR and\n\\fIwait\\fR directly;  they should use \\fBTcl_Fork\\fR,\n\\fBTcl_WaitPids\\fR, and \\fBTcl_DetachPids\\fR.\n.PP\n\\fBTcl_Fork\\fR calls \\fIfork\\fR and returns the result of\nthe \\fIfork\\fR kernel call.\nIf the \\fIfork\\fR call was successful then \\fBTcl_Fork\\fR also\nenters the new process into its internal table of child\nproceses.\nIf \\fIfork\\fR returns an error then \\fBTcl_Fork\\fR returns that\nsame error.\n.PP\n\\fBTcl_WaitPids\\fR calls \\fIwait\\fR repeatedly until one of the processes\nin the \\fIpidPtr\\fR array has exited or been killed or suspended by a\nsignal.\nWhen this occurs, \\fBTcl_WaitPids\\fR returns the process\nidentifier for the process and stores its wait status at\n\\fI*statusPtr\\fR.\nIf the process no longer exists (it exited or was killed by a signal),\nthen \\fBTcl_WaitPids\\fR removes its entry from the internal\nprocess table.\nIf \\fIwait\\fR returns a process that isn't\nin the \\fIpidPtr\\fR array, \\fBTcl_WaitPids\\fR saves its wait\nstatus in the internal process table and calls \\fIwait\\fR again.\nIf one of the processes in the \\fIpidPtr\\fR array has already\nexited (or suspended or been killed) when \\fBTcl_WaitPids\\fR\nis called, that process and its wait status are returned\nimmediately without calling \\fIwait\\fR.\n.PP\n\\fBTcl_WaitPids\\fR provides two advantages.  First, it allows\nprocesses to exit in any order, and saves their wait statuses.\nSecond, it allows waiting on a number of processes simultaneously,\nreturning when any of the processes is returned by \\fIwait\\fR.\n.PP\n\\fBTcl_DetachPids\\fR is used to indicate that the application\nno longer cares about the processes given by the \\fIpidPtr\\fR\narray and will never use \\fBTcl_WaitPids\\fR to wait for them.\nThis occurs, for example, if one or more children are to be\nexecuted in background and the parent doesn't care whether\nthey complete successfully.\nWhen \\fBTcl_DetachPids\\fR is called, the internal process\ntable entries for the processes are marked so that the\nentries will be removed as soon as the processes exit or\nare killed.\n.PP\nIf none of the pids passed to \\fBTcl_WaitPids\\fR exists in\nthe internal process table, then -1 is returned and \\fIerrno\\fR\nis set to ECHILD.\nIf a \\fIwait\\fR kernel call returns an error,\nthen \\fBTcl_WaitPids\\fR returns that same error.\nIf a \\fIwait\\fR kernel call returns a process that isn't in\nthe internal process table,  \\fBTcl_WaitPids\\fR panics and\naborts the application.\nIf this situation occurs, it means that a process has been\ncreated without calling \\fBTcl_Fork\\fR and that its exit\nstatus is about to be lost.\n.PP\n\\fBTcl_WaitPids\\fR defines wait statuses to have type \\fIint\\fR,\nwhich is correct for POSIX and many variants of UNIX. \nSome BSD-based UNIX systems still use type \\fIunion wait\\fR for\nwait statuses;  it should be safe to cast a pointer to a\n\\fIunion wait\\fR structure to \\fI(int *)\\fR before passing\nit to \\fBTcl_WaitPids\\fR as in the following code:\n.nf\n.RS\n\n\\fBunion wait status;\nint pid1, pid2;\n\\&...\npid2 = Tcl_WaitPids(1, &pid1, (int *) &status);\\fR\n.RE\n.fi\n\n.SH KEYWORDS\nbackground, child, detach, fork, process, status, wait\n.VE\n"
  },
  {
    "path": "lib/libtcl/doc/GetInt.3",
    "content": "'\\\"\n'\\\" Copyright 1989 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/GetInt.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_GetInt tcl\n.BS\n.SH NAME\nTcl_GetInt, Tcl_GetDouble, Tcl_GetBoolean \\- convert from string to integer, double, or boolean\n.SH SYNOPSIS\n.nf\n\\fB#include <tcl.h>\\fR\n.sp\nint\n\\fBTcl_GetInt\\fR(\\fIinterp, string, intPtr\\fR)\n.sp\nint\n\\fBTcl_GetDouble\\fR(\\fIinterp, string, doublePtr\\fR)\n.sp\nint\n\\fBTcl_GetBoolean\\fR(\\fIinterp, string, boolPtr\\fR)\n.SH ARGUMENTS\n.AS Tcl_Interp *doublePtr\n.AP Tcl_Interp *interp in\nInterpreter to use for error reporting.\n.AP char *string in\nTextual value to be converted.\n.AP int *intPtr out\nPoints to place to store integer value converted from \\fIstring\\fR.\n.AP double *doublePtr out\nPoints to place to store double-precision floating-point\nvalue converted from \\fIstring\\fR.\n.AP int *boolPtr out\nPoints to place to store boolean value (0 or 1) converted from \\fIstring\\fR.\n.BE\n\n.SH DESCRIPTION\n.PP\nThese procedures convert from strings to integers or double-precision\nfloating-point values or booleans (represented as 0- or 1-valued\nintegers).  Each of the procedures takes a \\fIstring\\fR argument,\nconverts it to an internal form of a particular type, and stores\nthe converted value at the location indicated by the procedure's\nthird argument.  If all goes well, each of the procedures returns\nTCL_OK.  If \\fIstring\\fR doesn't have the proper syntax for the\ndesired type then TCL_ERROR is returned, an error message is left\nin \\fIinterp->result\\fR, and nothing is stored at *\\fIintPtr\\fR\nor *\\fIdoublePtr\\fR or *\\fIboolPtr\\fR.\n.PP\n\\fBTcl_GetInt\\fR expects \\fIstring\\fR to consist of a collection\nof integer digits, optionally signed and optionally preceded by\nwhite space.  If the first two characters of \\fIstring\\fR are ``0x''\nthen \\fIstring\\fR is expected to be in hexadecimal form;  otherwise,\nif the first character of \\fIstring\\fR is ``0'' then \\fIstring\\fR\nis expected to be in octal form;  otherwise, \\fIstring\\fR is\nexpected to be in decimal form.\n.PP\n\\fBTcl_GetDouble\\fR expects \\fIstring\\fR to consist of a floating-point\nnumber, which is:  white space;  a sign; a sequence of digits;  a\ndecimal point;  a sequence of digits;  the letter ``e'';  and a\nsigned decimal exponent.  Any of the fields may be omitted, except that\nthe digits either before or after the decimal point must be present\nand if the ``e'' is present then it must be followed by the\nexponent number.\n.PP\n\\fBTcl_GetBoolean\\fR expects \\fIstring\\fR to specify a boolean\nvalue.  If \\fIstring\\fR is any of \\fB0\\fR, \\fBfalse\\fR,\n.VS\n\\fBno\\fR, or \\fBoff\\fR, then \\fBTcl_GetBoolean\\fR stores a zero\nvalue at \\fI*boolPtr\\fR.\nIf \\fIstring\\fR is any of \\fB1\\fR, \\fBtrue\\fR, \\fByes\\fR, or \\fBon\\fR,\n.VE\nthen 1 is stored at \\fI*boolPtr\\fR.\nAny of these values may be abbreviated, and upper-case spellings\nare also acceptable.\n\n.SH KEYWORDS\nboolean, conversion, double, floating-point, integer\n"
  },
  {
    "path": "lib/libtcl/doc/Hash.3",
    "content": "'\\\"\n'\\\" Copyright 1989 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/Hash.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_Hash tcl\n.BS\n.SH NAME\n.na\nTcl_InitHashTable, Tcl_DeleteHashTable, Tcl_CreateHashEntry, Tcl_DeleteHashEntry, Tcl_FindHashEntry, Tcl_GetHashValue, Tcl_SetHashValue, Tcl_GetHashKey, Tcl_FirstHashEntry, Tcl_NextHashEntry, Tcl_HashStats \\- procedures to manage hash tables\n.SH SYNOPSIS\n.nf\n\\fB#include <tclHash.h>\\fR\n.sp\n\\fBTcl_InitHashTable\\fR(\\fItablePtr, keyType\\fR)\n.sp\n\\fBTcl_DeleteHashTable\\fR(\\fItablePtr\\fR)\n.sp\nTcl_HashEntry *\n\\fBTcl_CreateHashEntry\\fR(\\fItablePtr, key, newPtr\\fR)\n.sp\n\\fBTcl_DeleteHashEntry\\fR(\\fIentryPtr\\fR)\n.sp\nTcl_HashEntry *\n\\fBTcl_FindHashEntry\\fR(\\fItablePtr, key\\fR)\n.sp\nClientData\n\\fBTcl_GetHashValue\\fR(\\fIentryPtr\\fR)\n.sp\n\\fBTcl_SetHashValue\\fR(\\fIentryPtr, value\\fR)\n.sp\nchar *\n\\fBTcl_GetHashKey\\fR(\\fItablePtr, entryPtr\\fR)\n.sp\nTcl_HashEntry *\n\\fBTcl_FirstHashEntry\\fR(\\fItablePtr, searchPtr\\fR)\n.sp\nTcl_HashEntry *\n\\fBTcl_NextHashEntry\\fR(\\fIsearchPtr\\fR)\n.sp\nchar *\n\\fBTcl_HashStats\\fR(\\fItablePtr\\fR)\n.SH ARGUMENTS\n.AS Tcl_HashSearch *searchPtr\n.AP Tcl_HashTable *tablePtr in\nAddress of hash table structure (for all procedures but\n\\fBTcl_InitHashTable\\fR, this must have been initialized by\nprevious call to \\fBTcl_InitHashTable\\fR).\n.AP int keyType in\nKind of keys to use for new hash table.  Must be either\nTCL_STRING_KEYS, TCL_ONE_WORD_KEYS, or an integer value\ngreater than 1.\n.AP char *key in\nKey to use for probe into table.  Exact form depends on\n\\fIkeyType\\fR used to create table.\n.AP int *newPtr out\nThe word at \\fI*newPtr\\fR is set to 1 if a new entry was created\nand 0 if there was already an entry for \\fIkey\\fR.\n.AP Tcl_HashEntry *entryPtr in\nPointer to hash table entry.\n.AP ClientData value in\nNew value to assign to hash table entry.  Need not have type\nClientData, but must fit in same space as ClientData.\n.AP Tcl_HashSearch *searchPtr in\nPointer to record to use to keep track of progress in enumerating\nall the entries in a hash table.\n.BE\n\n.SH DESCRIPTION\n.PP\nA hash table consists of zero or more entries, each consisting of\na key and a value.\nGiven the key for an entry, the hashing routines can very quickly\nlocate the entry, and hence its value.\nThere may be at most one entry in a hash table with a\nparticular key, but many entries may have the same value.\nKeys can take one of three forms:  strings,\none-word values, or integer arrays.\nAll of the keys in a given table have the same form, which is\nspecified when the table is initialized.\n.PP\nThe value of a hash table entry can be anything that fits in\nthe same space as a ``char *'' pointer.\nValues for hash table entries are managed entirely by clients,\nnot by the hash module itself.\nTypically each entry's value is a pointer to a data structure\nmanaged by client code.\n.PP\nHash tables grow gracefully as the number of entries increases,\nso that there are always less than three entries per hash bucket,\non average.\nThis allows for fast lookups regardless of the number of entries\nin a table.\n.PP\n\\fBTcl_InitHashTable\\fR initializes a structure that describes\na new hash table.\nThe space for the structure is provided by the caller, not by\nthe hash module.\nThe value of \\fIkeyType\\fR indicates what kinds of keys will\nbe used for all entries in the table.  \\fIKeyType\\fR must have\none of the following values:\n.IP \\fBTCL_STRING_KEYS\\fR 25\nKeys are null-terminated ASCII strings.\nThey are passed to hashing routines using the address of the\nfirst character of the string.\n.IP \\fBTCL_ONE_WORD_KEYS\\fR 25\nKeys are single-word values;  they are passed to hashing routines\nand stored in hash table entries as ``char *'' values.\nThe pointer value is the key;  it need not (and usually doesn't)\nactually point to a string.\n.IP \\fIother\\fR 25\nIf \\fIkeyType\\fR is not TCL_STRING_KEYS or TCL_ONE_WORD_KEYS,\nthen it must be an integer value greater than 1.\nIn this case the keys will be arrays of ``int'' values, where\n\\fIkeyType\\fR gives the number of ints in each key.\nThis allows structures to be used as keys.\nAll keys must have the same size.\nArray keys are passed into hashing functions using the address\nof the first int in the array.\n.PP\n\\fBTcl_DeleteHashTable\\fR deletes all of the entries in a hash\ntable and frees up the memory associated with the table's\nbucket array and entries.\nIt does not free the actual table structure (pointed to\nby \\fItablePtr\\fR), since that memory is assumed to be managed\nby the client.\n\\fBTcl_DeleteHashTable\\fR also does not free or otherwise\nmanipulate the values of the hash table entries.\nIf the entry values point to dynamically-allocated memory, then\nit is the client's responsibility to free these structures\nbefore deleting the table.\n.PP\n\\fBTcl_CreateHashEntry\\fR locates the entry corresponding to a\nparticular key, creating a new entry in the table if there\nwasn't already one with the given key.\nIf an entry already existed with the given key then \\fI*newPtr\\fR\nis set to zero.\nIf a new entry was created, then \\fI*newPtr\\fR is set to a non-zero\nvalue and the value of the new entry will be set to zero.\nThe return value from \\fBTcl_CreateHashEntry\\fR is a pointer to\nthe entry, which may be used to retrieve and modify the entry's\nvalue or to delete the entry from the table.\n.PP\n\\fBTcl_DeleteHashEntry\\fR will remove an existing entry from a\ntable.\nThe memory associated with the entry itself will be freed, but\nthe client is responsible for any cleanup associated with the\nentry's value, such as freeing a structure that it points to.\n.PP\n\\fBTcl_FindHashEntry\\fR is similar to \\fBTcl_CreateHashEntry\\fR\nexcept that it doesn't create a new entry if the key doesn't exist;\ninstead, it returns NULL as result.\n.PP\n\\fBTcl_GetHashValue\\fR and \\fBTcl_SetHashValue\\fR are used to\nread and write an entry's value, respectively.\nValues are stored and retrieved as type ``ClientData'', which is\nlarge enough to hold a pointer value.  On almost all machines this is\nlarge enough to hold an integer value too.\n.PP\n\\fBTcl_GetHashKey\\fR returns the key for a given hash table entry,\neither as a pointer to a string, a one-word (``char *'') key, or\nas a pointer to the first word of an array of integers, depending\non the \\fIkeyType\\fR used to create a hash table.\nIn all cases \\fBTcl_GetHashKey\\fR returns a result with type\n``char *''.\nWhen the key is a string or array, the result of \\fBTcl_GetHashKey\\fR\npoints to information in the table entry;  this information will\nremain valid until the entry is deleted or its table is deleted.\n.PP\n\\fBTcl_FirstHashEntry\\fR and \\fBTcl_NextHashEntry\\fR may be used\nto scan all of the entries in a hash table.\nA structure of type ``Tcl_HashSearch'', provided by the client,\nis used to keep track of progress through the table.\n\\fBTcl_FirstHashEntry\\fR initializes the search record and\nreturns the first entry in the table (or NULL if the table is\nempty).\nEach susequent call to \\fBTcl_NextHashEntry\\fR returns the\nnext entry in the table or\nNULL if the end of the table has been reached.\nA call to \\fBTcl_FirstHashEntry\\fR followed by calls to\n\\fBTcl_NextHashEntry\\fR will return each of the entries in\nthe table exactly once, in an arbitrary order.\nIt is unadvisable to modify the structure of the table, e.g.\nby creating or deleting entries, while the search is in\nprogress.\n.PP\n\\fBTcl_HashStats\\fR returns a dynamically-allocated string with\noverall information about a hash table, such as the number of\nentries it contains, the number of buckets in its hash array,\nand the utilization of the buckets.\nIt is the caller's responsibility to free the result string\nby passing it to \\fBfree\\fR.\n.PP\nThe header file \\fBtclHash.h\\fR defines the actual data structures\nused to implement hash tables.\nThis is necessary so that clients can allocate Tcl_HashTable\nstructures and so that macros can be used to read and write\nthe values of entries.\nHowever, users of the hashing routines should never refer directly\nto any of the fields of any of the hash-related data structures;\nuse the procedures and macros defined here.\n\n.SH KEYWORDS\nhash table, key, lookup, search, value\n"
  },
  {
    "path": "lib/libtcl/doc/History.3",
    "content": "'\\\"\n'\\\" Copyright 1989 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/History.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_InitHistory tcl\n.BS\n.SH NAME\nTcl_InitHistory, Tcl_RecordAndEval \\- procedures for managing history list\n.SH SYNOPSIS\n.nf\n\\fB#include <tcl.h>\\fR\n.sp\n.VS\n\\fBTcl_InitHistory\\fR(\\fIinterp\\fR)\n.VE\n.sp\nint\n\\fBTcl_RecordAndEval\\fR(\\fIinterp, cmd, flags\\fR)\n.SH ARGUMENTS\n.AS Tcl_Interp *interp;\n.AP Tcl_Interp *interp in\nTcl interpreter in which history facilities are being used.\n.AP char *cmd in\nCommand (or sequence of commands) to execute.\n.AP char flags in\nFlags to pass to \\fBTcl_Eval\\fR (normally 0).  If -1, then the\ncommand is not executed;  it's just recorded.\n.BE\n\n.SH DESCRIPTION\n.PP\nThe procedure \\fBTcl_InitHistory\\fR is invoked to enable the\n.VS\nhistory facilities in an interpreter (by default there is no\n\\fBhistory\\fR command in an interpreter).\nAfter this command has been executed the \\fBhistory\\fR\ncommand will be available in \\fIinterp\\fR and the history facilities\nwill be initialized.\n\\fBTcl_InitHistory\\fR is invoked automatically by\n\\fBTcl_RecordAndEval\\fR, so it need not be invoked explicitly\nunless the \\fBhistory\\fR command is to\nbe used before \\fBTcl_RecordAndEval\\fR has been called.\n.VE\n.PP\n\\fBTcl_RecordAndEval\\fR is invoked to record a command on the history\nlist and then execute it.  Programs that do not wish to use the history\nmechanism should not call \\fBTcl_RecordAndEval\\fR;  they should call\n\\fBTcl_Eval\\fR instead.  Furthermore, \\fBTcl_RecordAndEval\\fR should\nonly be called with top-level commands typed by the user, since the\npurpose of history is to allow the user to re-issue recently-invoked\ncommands.\n.PP\n\\fBTcl_RecordAndEval\\fR does three things.\nFirst, it calls \\fBTcl_InitHistory\\fR to initialize history for the\ninterpreter \\fIinterp\\fR, if this hasn't already been done.\nSecond, \\fBTcl_RecordAndEval\\fR saves \\fIcommand\\fR in\nthe history list for \\fIinterp\\fR, making a new event to hold the\ncommand.\nThird, \\fBTcl_RecordAndEval\\fR executes the command by passing it\nand \\fIflags\\fR to \\fBTcl_Eval\\fR.  If \\fIflags\\fR is -1 then only\nthe first two steps are taken;  the command will not be executed.\n\n.SH KEYWORDS\ncommand, event, execute, history, interpreter, record\n"
  },
  {
    "path": "lib/libtcl/doc/Interp.3",
    "content": "'\\\"\n'\\\" Copyright 1989 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/Interp.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_Interp tcl\n.BS\n.SH NAME\nTcl_Interp \\- client-visible fields of interpreter structures\n.SH SYNOPSIS\n.nf\n\\fB#include <tcl.h>\\fR\n.sp\ntypedef struct {\n\tchar *\\fIresult\\fR;\n.VS\n\tTcl_FreeProc *\\fIfreeProc\\fR;\n.VE\n\tint \\fIerrorLine\\fR;\n} Tcl_Interp;\n\n.VS\ntypedef void Tcl_FreeProc(char *\\fIblockPtr\\fR);\n.VE\n.BE\n\n.SH DESCRIPTION\n.PP\nThe \\fBTcl_CreateInterp\\fR procedure returns a pointer to a Tcl_Interp\nstructure.  This pointer is then passed into other Tcl procedures\nto process commands in the interpreter and perform other operations\non the interpreter.  Interpreter structures contain many many fields\nthat are used by Tcl, but only three that may be accessed by\n.VS\nclients:  \\fIresult\\fR, \\fIfreeProc\\fR, and \\fIerrorLine\\fR.\n.PP\nThe \\fIresult\\fR and \\fIfreeProc\\fR fields are used to return\nresults or error messages from commands.\nThis information is returned by command procedures back to \\fBTcl_Eval\\fR,\nand by \\fBTcl_Eval\\fR back to its callers.\nThe \\fIresult\\fR field points to the string that represents the\nresult or error message, and the \\fIfreeProc\\fR field tells how\nto dispose of the storage for the string when it isn't needed anymore.\nThe easiest way for command procedures to manipulate these\nfields is to call procedures like \\fBTcl_SetResult\\fR\nor \\fBTcl_AppendResult\\fR;  they\nwill hide all the details of managing the fields.\nThe description below is for those procedures that manipulate the\nfields directly.\n.PP\nWhenever a command procedure returns, it must ensure\nthat the \\fIresult\\fR field of its interpreter points to the string\nbeing returned by the command.\nThe \\fIresult\\fR field must always point to a valid string.\nIf a command wishes to return no result then \\fIinterp->result\\fR\nshould point to an empty string.\nNormally, results are assumed to be statically allocated,\nwhich means that the contents will not change before the next time\n\\fBTcl_Eval\\fR is called or some other command procedure is invoked.\nIn this case, the \\fIfreeProc\\fR field must be zero.\nAlternatively, a command procedure may dynamically\nallocate its return value (e.g. using \\fBmalloc\\fR)\nand store a pointer to it in \\fIinterp->result\\fR.\nIn this case, the command procedure must also set \\fIinterp->freeProc\\fR\nto the address of a procedure that can free the value (usually \\fBfree\\fR).\nIf \\fIinterp->freeProc\\fR is non-zero, then Tcl will call \\fIfreeProc\\fR\nto free the space pointed to by \\fIinterp->result\\fR before it\ninvokes the next command.\nIf a client procedure overwrites \\fIinterp->result\\fR when\n\\fIinterp->freeProc\\fR is non-zero, then it is responsible for calling\n\\fIfreeProc\\fR to free the old \\fIinterp->result\\fR (the \\fBTcl_FreeResult\\fR\nmacro should be used for this purpose).\n.PP\n\\fIFreeProc\\fR should have arguments and result that match the\n\\fBTcl_FreeProc\\fR declaration above:  it receives a single\nargument which is a pointer to the result value to free.\nIn most applications \\fBfree\\fR is the only non-zero value ever\nused for \\fIfreeProc\\fR.\nHowever, an application may store a different procedure address\nin \\fIfreeProc\\fR in order to use an alternate memory allocator\nor in order to do other cleanup when the result memory is freed.\n.PP\nAs part of processing each command, \\fBTcl_Eval\\fR initializes\n\\fIinterp->result\\fR\nand \\fIinterp->freeProc\\fR just before calling the command procedure for\nthe command.  The \\fIfreeProc\\fR field will be initialized to zero,\nand \\fIinterp->result\\fR will point to an empty string.  Commands that\ndo not return any value can simply leave the fields alone.\n.VE\nFurthermore, the empty string pointed to by \\fIresult\\fR is actually\npart of an array of \\fBTCL_RESULT_SIZE\\fR characters (approximately 200).\nIf a command wishes to return a short string, it can simply copy\nit to the area pointed to by \\fIinterp->result\\fR.  Or, it can use\nthe sprintf procedure to generate a short result string at the location\npointed to by \\fIinterp->result\\fR.\n.PP\nIt is a general convention in Tcl-based applications that the result\nof an interpreter is normally in the initialized state described\nin the previous paragraph.\nProcedures that manipulate an interpreter's result (e.g. by\nreturning an error) will generally assume that the result\nhas been initialized when the procedure is called.\nIf such a procedure is to be called after the result has been\nchanged, then \\fBTcl_ResetResult\\fR should be called first to\nreset the result to its initialized state.\n.PP\nThe \\fIerrorLine\\fR\nfield is valid only after \\fBTcl_Eval\\fR returns\na \\fBTCL_ERROR\\fR return code.  In this situation the \\fIerrorLine\\fR\nfield identifies the line number of the command being executed when\nthe error occurred.  The line numbers are relative to the command\nbeing executed:  1 means the first line of the command passed to\n\\fBTcl_Eval\\fR, 2 means the second line, and so on.\nThe \\fIerrorLine\\fR field is typically used in conjunction with\n\\fBTcl_AddErrorInfo\\fR to report information about where an error\noccurred.\n\\fIErrorLine\\fR should not normally be modified except by \\fBTcl_Eval\\fR.\n\n.SH KEYWORDS\nfree, initialized, interpreter, malloc, result\n"
  },
  {
    "path": "lib/libtcl/doc/SetResult.3",
    "content": "'\\\"\n'\\\" Copyright 1989 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/SetResult.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_SetResult tcl\n.BS\n.SH NAME\nTcl_SetResult, Tcl_AppendResult, Tcl_AppendElement, Tcl_ResetResult \\- manipulate Tcl result string\n.SH SYNOPSIS\n.nf\n\\fB#include <tcl.h>\\fR\n.sp\n.VS\n\\fBTcl_SetResult\\fR(\\fIinterp, string, freeProc\\fR)\n.VE\n.sp\n\\fBTcl_AppendResult(\\fIinterp, string, string, ... , \\fB(char *) NULL\\fR)\n.sp\n.VS\n\\fBTcl_AppendElement\\fR(\\fIinterp, string, noSep\\fR)\n.sp\n\\fBTcl_ResetResult\\fR(\\fIinterp\\fR)\n.sp\n\\fBTcl_FreeResult\\fR(\\fIinterp\\fR)\n.VE\n.SH ARGUMENTS\n.AS Tcl_FreeProc freeProc\n.AP Tcl_Interp *interp out\nInterpreter whose result is to be modified.\n.AP char *string in\nString value to become result for \\fIinterp\\fR or to be\nappended to existing result.\n.AP Tcl_FreeProc freeProc in\n.VS\nAddress of procedure to call to release storage at\n\\fIstring\\fR, or \\fBTCL_STATIC\\fR, \\fBTCL_DYNAMIC\\fR, or\n\\fBTCL_VOLATILE\\fR.\n.AP int noSep in\nIf non-zero then don't output a space character before this element,\neven if the element isn't the first thing in the result string.\n.VE\n.BE\n\n.SH DESCRIPTION\n.PP\nThe procedures described here are utilities for setting the\nresult/error string in a Tcl interpreter.\n.PP\n\\fBTcl_SetResult\\fR\narranges for \\fIstring\\fR to be the return string for the current Tcl\ncommand in \\fIinterp\\fR, replacing any existing result.\n.VS\nIf \\fIfreeProc\\fR is \\fBTCL_STATIC\\fR it means that \\fIstring\\fR\nrefers to an area of static storage that is guaranteed not to be\nmodified until at least the next call to \\fBTcl_Eval\\fR.\nIf \\fIfreeProc\\fR\nis \\fBTCL_DYNAMIC\\fR it means that \\fIstring\\fR was allocated with a call\nto \\fBmalloc()\\fR and is now the property of the Tcl system.\n\\fBTcl_SetResult\\fR will arrange for the string's storage to be\nreleased by calling \\fBfree()\\fR when it is no longer needed.\nIf \\fIfreeProc\\fR is \\fBTCL_VOLATILE\\fR it means that \\fIstring\\fR\npoints to an area of memory that is likely to be overwritten when\n\\fBTcl_SetResult\\fR returns (e.g. it points to something in a stack frame).\nIn this case \\fBTcl_SetResult\\fR will make a copy of the string in\ndynamically allocated storage and arrange for the copy to be the\nreturn string for the current Tcl command.\n.PP\nIf \\fIfreeProc\\fR isn't one of the values \\fBTCL_STATIC\\fR,\n\\fBTCL_DYNAMIC\\fR, and \\fBTCL_VOLATILE\\fR, then it is the address\nof a procedure that Tcl should call to free the string.\nThis allows applications to use non-standard storage allocators.\nWhen Tcl no longer needs the storage for the string, it will\ncall \\fIfreeProc\\fR.  \\fIFreeProc\\fR should have arguments and\nresult that match the type \\fBTcl_FreeProc\\fR:\n.nf\n.RS\n\ntypedef void Tcl_FreeProc(char *\\fIblockPtr\\fR);\n\n.RE\n.fi\nWhen \\fIfreeProc\\fR is called, its \\fIblockPtr\\fR will be set to\nthe value of \\fIstring\\fR passed to \\fBTcl_SetResult\\fR.\n.VE\n.PP\nIf \\fIstring\\fR is \\fBNULL\\fR, then \\fIfreeProc\\fR is ignored\nand \\fBTcl_SetResult\\fR\nre-initializes \\fIinterp\\fR's result to point to the pre-allocated result\narea, with an empty string in the result area.\n.PP\n.VS\nIf \\fBTcl_SetResult\\fR is called at a time when \\fIinterp\\fR holds a\nresult, \\fBTcl_SetResult\\fR does whatever is necessary to dispose\nof the old result (see the \\fBTcl_Interp\\fR manual entry for details\non this).\n.VE\n.PP\n\\fBTcl_AppendResult\\fR makes it easy to build up Tcl results in pieces.\nIt takes each of its \\fIstring\\fR arguments and appends them in order\nto the current result associated with \\fIinterp\\fR.\n.VS\nIf the result is in its initialized empty state (e.g. a command procedure\nwas just invoked or \\fBTcl_ResetResult\\fR was just called),\nthen \\fBTcl_AppendResult\\fR sets the result to the concatenation of\nits \\fIstring\\fR arguments.\n.VE\n\\fBTcl_AppendResult\\fR may be called repeatedly as additional pieces\nof the result are produced.\n\\fBTcl_AppendResult\\fR takes care of all the\nstorage management issues associated with managing \\fIinterp\\fR's\nresult, such as allocating a larger result area if necessary.\nAny number of \\fIstring\\fR arguments may be passed in a single\ncall;  the last argument in the list must be a NULL pointer.\n.PP\n\\fBTcl_AppendElement\\fR is similar to \\fBTcl_AppendResult\\fR in\n.VS\nthat it allows results to be built up in pieces.\nHowever, \\fBTcl_AppendElement\\fR takes only a single \\fIstring\\fR\nargument and it appends that argument to the current result\nas a proper Tcl list element.\n\\fBTcl_AppendElement\\fR adds backslashes or braces if necessary\nto ensure that \\fIinterp\\fR's result can be parsed as a list and that\n\\fIstring\\fR will be extracted as a single element.\nUnder normal conditions, \\fBTcl_AppendElement\\fR will add a space\ncharacter to \\fIinterp\\fR's result just before adding the new\nlist element, so that the list elements in the result are properly\nseparated.\nHowever, if \\fIinterp\\fR's result is empty when \\fBTcl_AppendElement\\fR\nis called, or if the \\fInoSep\\fR argument is 1, then no space\nis added.\n.PP\n\\fBTcl_ResetResult\\fR clears the result for \\fIinterp\\fR,\nfreeing the memory associated with it if the current result was\ndynamically allocated.\nIt leaves the result in its normal initialized state with\n\\fIinterp->result\\fR pointing to a static buffer containing\n\\fBTCL_RESULT_SIZE\\fR characters, of which the first character\nis zero.\n\\fBTcl_ResetResult\\fR also clears the error state managed by\n\\fBTcl_AddErrorInfo\\fR and \\fBTcl_SetErrorCode\\fR.\n.PP\n\\fBTcl_FreeResult\\fR is a macro that performs part of the work\nof \\fBTcl_ResetResult\\fR.\nIt frees up the memory associated with \\fIinterp\\fR's result\nand sets \\fIinterp->freeProc\\fR to zero, but it doesn't\nchange \\fIinterp->result\\fR or clear error state.\n\\fBTcl_FreeResult\\fR is most commonly used when a procedure\nis about to replace one result value with another.\n.VE\n\n.SH \"SEE ALSO\"\nTcl_AddErrorInfo, Tcl_SetErrorCode, Tcl_Interp\n\n.SH KEYWORDS\nappend, command, element, list, result, return value, interpreter\n"
  },
  {
    "path": "lib/libtcl/doc/SetVar.3",
    "content": "'\\\"\n'\\\" Copyright 1989 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/SetVar.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_SetVar tcl\n.BS\n.VS\n.SH NAME\nTcl_SetVar, Tcl_SetVar2, Tcl_GetVar, Tcl_GetVar2, Tcl_UnsetVar, Tcl_UnsetVar2 \\- manipulate Tcl variables\n.SH SYNOPSIS\n.nf\n\\fB#include <tcl.h>\\fR\n.sp\nchar *\n\\fBTcl_SetVar\\fR(\\fIinterp, varName, newValue, flags\\fR)\n.sp\nchar *\n\\fBTcl_SetVar2\\fR(\\fIinterp, name1, name2, newValue, flags\\fR)\n.sp\nchar *\n\\fBTcl_GetVar\\fR(\\fIinterp, varName, flags\\fR)\n.sp\nchar *\n\\fBTcl_GetVar2\\fR(\\fIinterp, name1, name2, flags\\fR)\n.sp\nint\n\\fBTcl_UnsetVar\\fR(\\fIinterp, varName, flags\\fR)\n.sp\nint\n\\fBTcl_UnsetVar2\\fR(\\fIinterp, name1, name2, flags\\fR)\n.SH ARGUMENTS\n.AS Tcl_Interp *newValue\n.AP Tcl_Interp *interp in\nInterpreter containing variable.\n.AP char *varName in\nName of variable.  May refer to a scalar variable or an element of\nan array variable.\n.AP char *newValue in\nNew value for variable.\n.AP int flags in\nOR-ed combination of bits providing additional information for\noperation. See below for valid values.\n.AP char *name1 in\nName of scalar variable, or name of array variable if \\fIname2\\fR\nis non-NULL.\n.AP char *name2 in\nIf non-NULL, gives name of element within array and \\fIname1\\fR\nmust refer to an array variable.\n.BE\n\n.SH DESCRIPTION\n.PP\nThese procedures may be used to create, modify, read, and delete\nTcl variables from C code.\n\\fBTcl_SetVar\\fR and \\fBTcl_SetVar2\\fR will create a new variable\nor modify an existing one.\nBoth of these procedures set the given variable to the value\ngiven by \\fInewValue\\fR, and they return a pointer to a\ncopy of the variable's new value, which is stored in Tcl's\nvariable structure.\nTcl keeps a private copy of the variable's value, so the caller\nmay change \\fInewValue\\fR after these procedures return without\naffecting the value of the variable.\nIf an error occurs in setting the variable (e.g. an array\nvariable is referenced without giving an index into the array),\nthen NULL is returned.\n.PP\nThe name of the variable may be specified in either of two ways.\nIf \\fBTcl_SetVar\\fR is called, the variable name is given as\na single string, \\fIvarName\\fR.\nIf \\fIvarName\\fR contains an open parenthesis and ends with a\nclose parenthesis, then the value between the parentheses is\ntreated as an index (which can have any string value) and\nthe characters before the first open\nparenthesis are treated as the name of an array variable.\nIf \\fIvarName\\fR doesn't have parentheses as described above, then\nthe entire string is treated as the name of a scalar variable.\nIf \\fBTcl_SetVar2\\fR is called, then the array name and index\nhave been separated by the caller into two separate strings,\n\\fIname1\\fR and \\fIname2\\fR respectively;  if \\fIname2\\fR is\nzero it means that a scalar variable is being referenced.\n.PP\nThe \\fIflags\\fR argument may be used to specify any of several\noptions to the procedures.\nIt consists of an OR-ed combination of any of the following\nbits:\n.IP TCL_GLOBAL_ONLY\nUnder normal circumstances the procedures look up variables\nat the current level of procedure call for \\fIinterp\\fR, or\nat global level if there is no call active.\nHowever, if this bit is set in \\fIflags\\fR then the variable\nis looked up at global level even if there is a procedure\ncall active.\n.IP TCL_LEAVE_ERR_MSG\nIf an error is returned and this bit is set in \\fIflags\\fR, then\nan error message will be left in \\fI\\%interp->result\\fR.  If this\nflag bit isn't set then no error message is left (\\fI\\%interp->result\\fR\nwill not be modified).\n.IP TCL_APPEND_VALUE\nIf this bit is set then \\fInewValue\\fR is appended to the current\nvalue, instead of replacing it.\nIf the variable is currently undefined, then this bit is ignored.\n.IP TCL_LIST_ELEMENT\nIf this bit is set, then \\fInewValue\\fR is converted to a valid\nTcl list element before setting (or appending to) the variable.\nIf the list element is being appended to an non-empty value, then\na space character is appended before the new list element to\nseparate it from previous elements.\n.IP TCL_NO_SPACE\nIf this bit is set, it prevents the output of a separating space\ncharacter in TCL_LIST_ELEMENT appends.\nThis bit has no effect if the TCL_LIST_ELEMENT bit isn't set.\n.PP\n\\fBTcl_GetVar\\fR and \\fBTcl_GetVar2\\fR return the current value\nof a variable.\nThe arguments to these procedures are treated in the same way\nas the arguments to \\fBTcl_SetVar\\fR and \\fBTcl_SetVar2\\fR.\nUnder normal circumstances, the return value is a pointer\nto the variable's value (which is stored in Tcl's variable\nstructure and will not change before the next call to \\fBTcl_SetVar\\fR\nor \\fBTcl_SetVar2\\fR).\nThe only bits of \\fIflags\\fR that are used are TCL_GLOBAL_ONLY\nand TCL_LEAVE_ERR_MSG, both of\nwhich have\nthe same meaning as for \\fBTcl_SetVar\\fR.\nIf an error occurs in reading the variable (e.g. the variable\ndoesn't exist or an array element is specified for a scalar\nvariable), then NULL is returned.\n.PP\n\\fBTcl_UnsetVar\\fR and \\fBTcl_UnsetVar2\\fR may be used to remove\na variable, so that future calls to \\fBTcl_GetVar\\fR or \\fBTcl_GetVar2\\fR\nfor the variable will return an error.\nThe arguments to these procedures are treated in the same way\nas the arguments to \\fBTcl_GetVar\\fR and \\fBTcl_GetVar2\\fR.\nIf the variable is successfully removed then 0 is returned.\nIf the variable cannot be removed because it doesn't exist\nor because a trace is active for it, then -1 is returned.\nIf an array element is specified, the given element is removed\nbut the array remains.\nIf an array name is specified without an index, then the entire\narray is removed.\n\n.SH \"SEE ALSO\"\nTcl_TraceVar\n\n.SH KEYWORDS\narray, interpreter, scalar, set, unset, variable\n.VE\n"
  },
  {
    "path": "lib/libtcl/doc/SplitList.3",
    "content": "'\\\"\n'\\\" Copyright 1989-1991 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/SplitList.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_SplitList tcl\n.BS\n.SH NAME\nTcl_SplitList, Tcl_Merge, Tcl_ScanElement, Tcl_ConvertElement \\- manipulate Tcl lists\n.SH SYNOPSIS\n.nf\n\\fB#include <tcl.h>\\fR\n.sp\nint\n\\fBTcl_SplitList\\fR(\\fIinterp, list, argcPtr, argvPtr\\fR)\n.sp\nchar *\n\\fBTcl_Merge\\fR(\\fIargc, argv\\fR)\n.sp\n.VS\nint\n\\fBTcl_ScanElement\\fR(\\fIsrc, flagsPtr\\fR)\n.sp\nint\n\\fBTcl_ConvertElement\\fR(\\fIsrc, dst, flags\\fR)\n.VE\n.SH ARGUMENTS\n.AS Tcl_Interp ***argvPtr\n.AP Tcl_Interp *interp out\nInterpreter to use for error reporting.\n.AP char *list in\nPointer to a string with proper list structure.\n.AP int *argcPtr out\nFilled in with number of elements in \\fIlist\\fR.\n.AP char ***argvPtr out\n\\fI*argvPtr\\fR will be filled in with the address of an array of\npointers to the strings that are the extracted elements of \\fIlist\\fR.\nThere will be \\fI*argcPtr\\fR valid entries in the array, followed by\na NULL entry.\n.AP int argc in\nNumber of elements in \\fIargv\\fR.\n.AP char **argv in\nArray of strings to merge together into a single list.\nEach string will become a separate element of the list.\n.AP char *src in\n.VS\nString that is to become an element of a list.\n.AP int *flagsPtr in\nPointer to word to fill in with information about \\fIsrc\\fR.\nThe value of *\\fIflagsPtr\\fR must be passed to \\fBTcl_ConvertElement\\fR.\n.AP char *dst in\nPlace to copy converted list element.  Must contain enough characters\nto hold converted string.\n.AP int flags in\nInformation about \\fIsrc\\fR. Must be value returned by previous\ncall to \\fBTcl_ScanElement\\fR, possibly OR-ed\nwith \\fBTCL_DONT_USE_BRACES\\fR.\n.VE\n.BE\n\n.SH DESCRIPTION\n.PP\nThese procedures may be used to disassemble and reassemble Tcl lists.\n\\fBTcl_SplitList\\fR breaks a list up into its constituent elements,\nreturning an array of pointers to the elements using\n\\fIargcPtr\\fR and \\fIargvPtr\\fR.\nWhile extracting the arguments, \\fBTcl_SplitList\\fR obeys the usual\nrules for backslash substitutions and braces.  The area of\nmemory pointed to by \\fI*argvPtr\\fR is dynamically allocated;  in\naddition to the array of pointers, it\nalso holds copies of all the list elements.  It is the caller's\nresponsibility to free up all of this storage by calling\n.DS\n\\fBfree\\fR((char *) \\fI*argvPtr\\fR)\n.DE\nwhen the list elements are no longer needed.\n.PP\n\\fBTcl_SplitList\\fR normally returns \\fBTCL_OK\\fR, which means the list was\nsuccessfully parsed.\nIf there was a syntax error in \\fIlist\\fR, then \\fBTCL_ERROR\\fR is returned\nand \\fIinterp->result\\fR will point to an error message describing the\nproblem.\nIf \\fBTCL_ERROR\\fR is returned then no memory is allocated and \\fI*argvPtr\\fR\nis not modified.\n.PP\n\\fBTcl_Merge\\fR is the inverse of \\fBTcl_SplitList\\fR:  it\ntakes a collection of strings given by \\fIargc\\fR\nand \\fIargv\\fR and generates a result string\nthat has proper list structure.\nThis means that commands like \\fBindex\\fR may be used to\nextract the original elements again.\nIn addition, if the result of \\fBTcl_Merge\\fR is passed to \\fBTcl_Eval\\fR,\nit will be parsed into \\fIargc\\fR words whose values will\nbe the same as the \\fIargv\\fR strings passed to \\fBTcl_Merge\\fR.\n\\fBTcl_Merge\\fR will modify the list elements with braces and/or\nbackslashes in order to produce proper Tcl list structure.\nThe result string is dynamically allocated\nusing \\fBmalloc()\\fR;  the caller must eventually release the space\nusing \\fBfree()\\fR.\n.PP\nIf the result of \\fBTcl_Merge\\fR is passed to \\fBTcl_SplitList\\fR,\nthe elements returned by \\fBTcl_SplitList\\fR will be identical to\nthose passed into \\fBTcl_Merge\\fR.\nHowever, the converse is not true:  if \\fBTcl_SplitList\\fR\nis passed a given string, and the resulting \\fIargc\\fR and\n\\fIargv\\fR are passed to \\fBTcl_Merge\\fR, the resulting string\nmay not be the same as the original string passed to \\fBTcl_SplitList\\fR.\nThis is because \\fBTcl_Merge\\fR may use backslashes and braces\ndifferently than the original string.\n.PP\n.VS\n\\fBTcl_ScanElement\\fR and \\fBTcl_ConvertElement\\fR are the\nprocedures that do all of the real work of \\fBTcl_Merge\\fR.\n\\fBTcl_ScanElement\\fR scans its \\fIsrc\\fR argument\nand determines how to use backslashes and braces\nwhen converting it to a list element.\nIt returns an overestimate of the number of characters\nrequired to represent \\fIsrc\\fR as a list element, and\nit stores information in \\fI*flagsPtr\\fR that is needed\nby \\fBTcl_ConvertElement\\fR.\n.PP\n\\fBTcl_ConvertElement\\fR is a companion procedure to \\fBTcl_ScanElement\\fR.\nIt does the actual work of converting a string to a list element.\nIts \\fIflags\\fR argument must be the same as the value returned\nby \\fBTcl_ScanElement\\fR.\n\\fBTcl_ConvertElement\\fR writes a proper list element to memory\nstarting at *\\fIdst\\fR and returns a count of the total number\nof characters written, which will be no more than the result\nreturned by \\fBTcl_ScanElement\\fR.\n\\fBTcl_ConvertElement\\fR writes out only the actual list element\nwithout any leading or trailing spaces: it is up to the caller to\ninclude spaces between adjacent list elements.\n.PP\n\\fBTcl_ConvertElement\\fR uses one of two different approaches to\nhandle the special characters in \\fIsrc\\fR.  Wherever possible, it\nhandles special characters by surrounding the string with braces.\nThis produces clean-looking output, but can't be used in some situations,\nsuch as when \\fIsrc\\fR contains unmatched braces.\nIn these situations, \\fBTcl_ConvertElement\\fR handles special\ncharacters by generating backslash sequences for them.\nThe caller may insist on the second approach by OR-ing the\nflag value returned by \\fBTcl_ScanElement\\fR with\n\\fBTCL_DONT_USE_BRACES\\fR.\nAlthough this will produce an uglier result, it is useful in some\nspecial situations, such as when \\fBTcl_ConvertElement\\fR is being\nused to generate a portion of an argument for a Tcl command.\nIn this case, surrounding \\fIsrc\\fR with curly braces would cause\nthe command not to be parsed correctly.\n.VE\n\n.SH KEYWORDS\nbackslash, convert, element, list, merge, split, strings\n"
  },
  {
    "path": "lib/libtcl/doc/StrMatch.3",
    "content": "'\\\"\n'\\\" Copyright 1989 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/StrMatch.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_StringMatch tcl\n.BS\n.SH NAME\nTcl_StringMatch \\- test whether a string matches a pattern\n.SH SYNOPSIS\n.nf\n\\fB#include <tcl.h>\\fR\n.sp\nint\n\\fBTcl_StringMatch\\fR(\\fIstring\\fR, \\fIpattern\\fR)\n.SH ARGUMENTS\n.AP char *string in\nString to test.\n.AP char *pattern in\nPattern to match against string.  May contain special\ncharacters from the set *?\\e[].\n.BE\n\n.SH DESCRIPTION\n.PP\nThis utility procedure determines whether a string matches\na given pattern.  If it does, then \\fBTcl_StringMatch\\fR returns\n1.  Otherwise \\fBTcl_StringMatch\\fR returns 0.  The algorithm\nused for matching is the same algorithm used in the ``string match''\nTcl command and is similar to the algorithm used by the C-shell\nfor file name matching;  see the Tcl manual entry for details.\n\n.SH KEYWORDS\nmatch, pattern, string\n"
  },
  {
    "path": "lib/libtcl/doc/Tcl.n",
    "content": "'\\\"\n'\\\" Copyright 1989-1992 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/Tcl.n,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\n.so man.macros\n.de UL\n\\\\$1\\l'|0\\(ul'\\\\$2\n..\n.HS Tcl tcl\n.BS\n.SH NAME\nTcl \\- overview of tool command language facilities\n.BE\n\n.SH INTRODUCTION\n.PP\nTcl stands for ``tool command language'' and is pronounced ``tickle.''\nIt is actually two things:\na language and a library.\nFirst, Tcl is a simple textual language,\nintended primarily for issuing commands to interactive programs such\nas text editors, debuggers, illustrators, and shells.  It has\na simple syntax and is also programmable, so\nTcl users can write command procedures to provide more powerful\ncommands than those in the built-in set.\n.PP\nSecond, Tcl is a library package that can be embedded in application\nprograms.  The Tcl library consists of a parser for the Tcl\nlanguage, routines to implement the Tcl built-in commands, and\nprocedures that allow each application to extend Tcl with additional\ncommands specific to that application.  The application program\ngenerates Tcl commands and passes them to the Tcl parser for\nexecution.  Commands may be generated\nby reading characters from an input\nsource, or by associating command strings with elements of the\napplication's user interface, such as menu entries, buttons, or\nkeystrokes.\nWhen the Tcl library receives commands it parses them\ninto component fields and executes built-in commands directly.\nFor commands implemented by the\napplication, Tcl calls back to the application to execute the\ncommands.  In many cases commands will invoke recursive invocations\nof the Tcl interpreter by passing in additional strings to execute\n(procedures, looping commands, and conditional commands all work\nin this way).\n.PP\nAn application program gains three advantages by using Tcl for\nits command language.  First, Tcl provides a standard syntax:  once\nusers know Tcl, they will be able to issue commands easily\nto any Tcl-based application.  Second, Tcl provides programmability.\nAll a Tcl application needs to do is to implement a few\napplication-specific low-level commands.  Tcl provides many utility\ncommands plus a general programming interface for building up\ncomplex command procedures.  By using Tcl, applications need not\nre-implement these features.  Third, Tcl can be used as\n.VS\na common language for communicating between applications.\nInter-application communication is not built into the Tcl core\ndescribed here, but various add-on libraries, such as the Tk toolkit,\nallow applications to issue commands to each other.\nThis makes it possible for applications to work together in much\nmore powerful ways than was previously possible.\n.VE\n.PP\nThis manual page focuses primarily on the Tcl language.  It describes\nthe language syntax and the built-in commands that will be available in\nany application based on Tcl.  The individual library\nprocedures are described in more detail in separate manual pages, one\nper procedure.\n\n.SH \"INTERPRETERS\"\n.PP\nThe central data structure in Tcl is an interpreter (C type\n``Tcl_Interp'').  An interpreter consists of a set of command\nbindings, a set of variable values, and a few other miscellaneous\npieces of state.  Each Tcl command is interpreted in the context\nof a particular interpreter.\nSome Tcl-based applications will maintain\nmultiple interpreters simultaneously, each associated with a\ndifferent widget or portion of the application.\nInterpreters are relatively lightweight structures.  They can\nbe created and deleted quickly, so application programmers should feel free to\nuse multiple interpreters if that simplifies the application.\nEventually Tcl will provide a mechanism for sending Tcl commands\nand results back and forth between interpreters, even if the\ninterpreters are managed by different processes.\n\n.SH \"DATA TYPES\"\n.PP\nTcl supports only one type of data:  strings.  All commands,\nall arguments to commands, all command results, and all variable values\nare strings.\nWhere commands require numeric arguments or return numeric results,\nthe arguments and results are passed as strings.\nMany commands expect their string arguments to have certain formats,\nbut this interpretation is\nup to the individual commands.  For example, arguments often contain\nTcl command strings, which may get executed as part of the commands.\nThe easiest way to understand the Tcl interpreter is to remember that\neverything is just an operation on a string.  In many cases Tcl constructs\nwill look similar to more structured constructs from other languages.\nHowever, the Tcl constructs\nare not structured at all; they are just strings of characters, and this\ngives them a different behavior than the structures they may look like.\n.PP\nAlthough the exact interpretation of a Tcl string depends on who is\ndoing the interpretation, there are three common forms that strings\ntake:  commands, expressions, and lists.  The major sections below\ndiscuss these three forms in more detail.\n\n.SH \"BASIC COMMAND SYNTAX\"\n.PP\nThe Tcl language has syntactic similarities to both the Unix shells\nand Lisp.  However, the interpretation of commands is different\nin Tcl than in either of those other two systems.\nA Tcl command string consists of one or more commands separated\nby newline characters or semi-colons.\nEach command consists of a collection of fields separated by\nwhite space (spaces or tabs).\nThe first field must be the name of a command, and the\nadditional fields, if any, are arguments that will be passed to\nthat command.  For example, the command\n.DS\n\\fBset a 22\\fR\n.DE\nhas three fields:  the first, \\fBset\\fR, is the name of a Tcl command, and\nthe last two, \\fBa\\fR and \\fB22\\fR, will be passed as arguments to\nthe \\fBset\\fR command.  The command name may refer either to a built-in\nTcl command, an application-specific command bound in with the library\nprocedure \\fBTcl_CreateCommand\\fR, or a command procedure defined with the\n\\fBproc\\fR built-in command.\nArguments are passed literally as\ntext strings.  Individual commands may interpret those strings in any\nfashion they wish.  The \\fBset\\fR command, for example, will treat its\nfirst argument as the name of a variable and its second argument as a\nstring value to assign to that variable.  For other commands arguments\nmay be interpreted as integers, lists, file names, or Tcl commands.\n.PP\n.VS\nCommand names should normally be typed completely (e.g. no abbreviations).\nHowever, if the Tcl interpreter cannot locate a command it invokes a\nspecial command named \\fBunknown\\fR which attempts to find or create\nthe command.\nFor example, at many sites \\fBunknown\\fR will search\nthrough library directories for the desired command and create it\nas a Tcl procedure if it is found.\nThe \\fBunknown\\fR command often provides automatic completion of\nabbreviated commands, but usually only for commands that were typed\ninteractively.\nIt's probably a bad idea to use abbreviations in command scripts\nand other forms that will be re-used over time:  changes\nto the command set may cause abbreviations to become ambiguous,\nresulting in scripts that no longer work.\n.VE\n\n.SH \"COMMENTS\"\n.PP\nIf the first non-blank character in a command is \\fB#\\fR, then everything\nfrom the \\fB#\\fR up through the next newline character is treated as\na comment and ignored.  When comments are embedded inside nested\ncommands (e.g. fields enclosed in braces) they must have properly-matched\nbraces (this is necessary because when Tcl parses the top-level command\nit doesn't yet know that the nested field will be used as a command so\nit cannot process the nested comment character as a comment).\n\n.SH \"GROUPING ARGUMENTS WITH DOUBLE-QUOTES\"\n.PP\nNormally each argument field ends at the next white space, but\ndouble-quotes may be used to create arguments with embedded\nspace.  If an argument\nfield begins with a double-quote, then the argument isn't\nterminated by white space (including newlines) or a semi-colon\n(see below for information on semi-colons); instead it ends at the next\ndouble-quote character.  The double-quotes are not included\nin the resulting argument.  For example, the\ncommand\n.DS\n\\fBset a \"This is a single argument\"\\fR\n.DE\nwill pass two arguments to \\fBset\\fR:  \\fBa\\fR and\n\\fBThis is a single argument\\fR.  Within double-quotes, command\nsubstitutions, variable substitutions, and backslash substitutions\nstill occur, as described below.  If the first character of a\ncommand field is not a quote, then quotes receive no special\ninterpretation in the parsing of that field.\n\n.SH \"GROUPING ARGUMENTS WITH BRACES\"\n.PP\nCurly braces may also be used for grouping arguments.  They are\nsimilar to quotes except for two differences.  First, they nest;\nthis makes them easier to use for complicated arguments like nested Tcl\ncommand strings.  Second, the substitutions described below for\ncommands, variables, and backslashes do \\fInot\\fR occur in arguments\nenclosed in braces, so braces can be used to prevent substitutions\nwhere they are undesirable.\nIf an argument field\nbegins with a left brace, then the argument ends at the matching\nright brace.  Tcl will strip off the outermost layer of braces\nand pass the information between the braces to the command without\nany further modification.  For example, in the command\n.DS\n\\fBset a {xyz a {b c d}}\\fR\n.DE\nthe \\fBset\\fR command will receive two arguments: \\fBa\\fR\nand \\fBxyz a {b c d}\\fR.\n.PP\nWhen braces or quotes are in effect, the matching brace\nor quote need not be on\nthe same line as the starting quote or brace; in this case\nthe newline will be\nincluded in the argument field along with any other characters up to the\nmatching brace or quote.  For example, the \\fBeval\\fR command\ntakes one\nargument, which is a command string; \\fBeval\\fR invokes the Tcl\ninterpreter to execute the command string.  The command\n.DS\n\\fBeval {\n\tset a 22\n\tset b 33\n}\\fR\n.DE\nwill assign the value \\fB22\\fR to \\fBa\\fR and \\fB33\\fR to \\fBb\\fR.\n.PP\nIf the first character of a command field is not a left\nbrace, then neither left nor right\nbraces in the field will be treated specially (except as part of\nvariable substitution; see below).\n\n.SH \"COMMAND SUBSTITUTION WITH BRACKETS\"\n.PP\nIf an open bracket occurs in a field of a command, then\ncommand substitution occurs (except for fields enclosed in\nbraces).  All of the text up to the matching\nclose bracket is treated as a Tcl command and executed immediately.\nThen the result of that command is substituted for the bracketed\ntext.  For example, consider the command\n.DS\n\\fBset a [set b]\\fR\n.DE\nWhen the \\fBset\\fR command has only a single argument, it is the\nname of a variable and \\fBset\\fR returns the contents of that\nvariable.  In this case, if variable \\fBb\\fR has the value \\fBfoo\\fR,\nthen the command above is equivalent to the command\n.DS\n\\fBset a foo\\fR\n.DE\nBrackets can be used in more complex ways.  For example, if the\nvariable \\fBb\\fR has the value \\fBfoo\\fR and the variable \\fBc\\fR\nhas the value \\fBgorp\\fR, then the command\n.DS\n\\fBset a xyz[set b].[set c]\\fR\n.DE\nis equivalent to the command\n.DS\n\\fBset a xyzfoo.gorp\\fR\n.DE\n.VS\nA bracketed command may contain multiple commands separated by\nnewlines or semi-colons in the usual fashion.\nIn this case the value of the last command is used for substitution.\nFor example, the command\n.DS\n\\fBset a x[set b 22\nexpr $b+2]x\\fR\n.DE\nis equivalent to the command\n.DS\n\\fBset a x24x\\fR\n.DE\n.VE\nIf a field is enclosed in braces then the brackets and the characters\nbetween them are not interpreted specially; they are passed through\nto the argument verbatim.\n\n.SH \"VARIABLE SUBSTITUTION WITH $\"\n.PP\nThe dollar sign (\\fB$\\fR) may be used as a special shorthand form\nfor substituting variable values.\nIf \\fB$\\fR appears in an argument that isn't enclosed in braces\nthen variable substitution will occur.  The characters after\nthe \\fB$\\fR, up to the first character that isn't a number, letter, or\nunderscore, are taken as a variable name and the string value of that\nvariable is substituted for the name.\n.VS\nFor example, if variable \\fBfoo\\fR\nhas the value \\fBtest\\fR, then the command\n.DS C\n\\fBset a $foo.c\\fR\n.DE\nis equivalent to the command\n.DS C\n\\fBset a test.c\\fR\n.DE\n.PP\nThere are two special forms for variable substitution.\nIf the next character after the name of the variable is an\nopen parenthesis, then the variable is assumed to be an array\nname, and all of the characters between the open parenthesis\nand the next close parenthesis are taken as an index into the array.\nCommand substitutions and variable substitutions are\nperformed on the information between the parentheses before it is\nused as an index.\nFor example, if the variable \\fBx\\fR is an array with one element\nnamed \\fBfirst\\fR and value \\fB87\\fR and another element named\n\\fB14\\fR and value \\fBmore\\fR, then the command\n.DS C\n\\fBset a xyz$x(first)zyx\n.DE\nis equivalent to the command\n.DS C\n\\fBset a xyz87zyx\\fR\n.DE\nIf the variable \\fBindex\\fR has the value \\fB14\\fR, then the command\n.DS C\n\\fBset a xyz$x($index)zyx\n.DE\nis equivalent to the command\n.DS C\n\\fBset a xyzmorezyx\n.DE\nFor more information on arrays, see VARIABLES AND ARRAYS below.\n.PP\nThe second special form for variables occurs when\nthe dollar sign is followed by an open curly brace.\nIn this case the variable name consists of all the characters\nup to the next curly brace.\nArray references are not possible in this form:  the name\nbetween braces is assumed to refer to a scalar variable.\nFor example, if variable \\fBfoo\\fR has the value \\fBtest\\fR,\nthen the command\n.DS C\n\\fBset a abc${foo}bar\\fR\n.DE\nis equivalent to the command\n.DS C\n\\fBset a abctestbar\\fR\n.DE\n.VE\nVariable substitution does not occur in arguments that are enclosed\nin braces:  the\ndollar sign and variable name are passed through to the argument verbatim.\n.PP\nThe dollar sign abbreviation is simply a shorthand form.  \\fB$a\\fR is\ncompletely equivalent to \\fB[set a]\\fR; it is provided as a convenience\nto reduce typing.\n\n.SH \"SEPARATING COMMANDS WITH SEMI-COLONS\"\n.PP\nNormally, each command occupies one line (the command is terminated by\na newline character).  However, semi-colon (``;'') is treated\nas a command separator character; multiple commands may be placed\non one line by separating them with a semi-colon.  Semi-colons are\nnot treated as command separators if they appear within curly braces\nor double-quotes.\n\n.SH \"BACKSLASH SUBSTITUTION\"\n.PP\nBackslashes may be used to insert non-printing characters into\ncommand fields and also to insert special characters like\nbraces and brackets into fields\nwithout them being interpreted specially as described above.\nThe backslash sequences understood by the Tcl interpreter are\nlisted below.  In each case, the backslash\nsequence is replaced by the given character:\n.TP 20\n\\fB\\eb\\fR\nBackspace (0x8).\n.TP 20\n\\fB\\ef\\fR\nForm feed (0xc).\n.TP 20\n\\fB\\en\\fR\nNewline (0xa).\n.TP 20\n\\fB\\er\\fR\nCarriage-return (0xd).\n.TP 20\n\\fB\\et\\fR\nTab (0x9).\n.TP 20\n\\fB\\ev\\fR\nVertical tab (0xb).\n.TP 20\n\\fB\\e{\\fR\nLeft brace (``{'').\n.TP 20\n\\fB\\e}\\fR\nRight brace (``}'').\n.TP 20\n\\fB\\e[\\fR\nOpen bracket (``['').\n.TP 20\n\\fB\\e]\\fR\nClose bracket (``]'').\n.TP 20\n\\fB\\e$\\fR\nDollar sign (``$'').\n.TP 20\n\\fB\\e<space>\\fR\nSpace (`` ''): doesn't terminate argument.\n.br\n.TP 20\n\\fB\\e;\\fR\nSemi-colon: doesn't terminate command.\n.TP 20\n\\fB\\e\"\\fR\nDouble-quote.\n.TP 20\n\\fB\\e<newline>\\fR\nNothing:  this joins two lines together\ninto a single line.  This backslash feature is unique in that\nit will be applied even when the sequence occurs within braces.\n.TP 20\n\\fB\\e\\e\\fR\nBackslash (``\\e'').\n.TP 20\n\\fB\\e\\fIddd\\fR\nThe digits \\fIddd\\fR (one, two, or three of them) give the octal value of\nthe character.  Null characters may not be embedded in command fields;\nif \\fIddd\\fR is zero then the backslash sequence is ignored (i.e. it\nmaps to an empty string).\n.PP\nFor example, in the command\n.DS\n\\fBset a \\e{x\\e[\\e\\0yz\\e141\\fR\n.DE\nthe second argument to \\fBset\\fR will be ``\\fB{x[\\0yza\\fR''.\n.PP\nIf a backslash is followed by something other than one of the options\ndescribed above, then the backslash is transmitted to the argument\nfield without any special processing, and the Tcl scanner continues\nnormal processing with the next character.  For example, in the\ncommand\n.DS\n\\fBset \\e*a \\e\\e\\e{foo\\fR\n.DE\nThe first argument to \\fBset\\fR will be \\fB\\e*a\\fR and the second\nargument will be \\fB\\e{foo\\fR.\n.PP\nIf an argument is enclosed in braces, then backslash sequences inside\nthe argument are parsed but no substitution occurs (except for\nbackslash-newline):  the backslash\nsequence is passed through to the argument as is, without making\nany special interpretation of the characters in the backslash sequence.\nIn particular, backslashed braces are not counted in locating the\nmatching right brace that terminates the argument.\nFor example, in the\ncommand\n.DS\n\\fBset a {\\e{abc}\\fR\n.DE\nthe second argument to \\fBset\\fR will be \\fB\\e{abc\\fR.\n.PP\nThis backslash mechanism is not sufficient to generate absolutely\nany argument structure; it only covers the\nmost common cases.  To produce particularly complicated arguments\nit is probably easiest to use the \\fBformat\\fR command along with\ncommand substitution.\n\n.SH \"COMMAND SUMMARY\"\n.IP [1]\nA command is just a string.\n.IP [2]\nWithin a string commands are separated by newlines or semi-colons\n(unless the newline or semi-colon is within braces or brackets\nor is backslashed).\n.IP [3]\nA command consists of fields.  The first field is the name of the command.\nThe other fields are strings that are passed to that command as arguments.\n.IP [4]\nFields are normally separated by white space.\n.IP [5]\nDouble-quotes allow white space and semi-colons to appear within\na single argument.\nCommand substitution, variable substitution, and backslash substitution\nstill occur inside quotes.\n.IP [6]\nBraces defer interpretation of special characters.\nIf a field begins with a left brace, then it consists of everything\nbetween the left brace and the matching right brace. The\nbraces themselves are not included in the argument.\nNo further processing is done on the information between the braces\nexcept that backslash-newline sequences are eliminated.\n.IP [7]\nIf a field doesn't begin with a brace then backslash,\nvariable, and command substitution are done on the field.  Only a\nsingle level of processing is done:  the results of one substitution\nare not scanned again for further substitutions or any other\nspecial treatment.  Substitution can\noccur on any field of a command, including the command name\nas well as the arguments.\n.IP [8]\nIf the first non-blank character of a command is a \\fB#\\fR, everything\nfrom the \\fB#\\fR up through the next newline is treated as a comment\nand ignored.\n\n.SH \"EXPRESSIONS\"\n.VS\n.PP\nThe second major interpretation applied to strings in Tcl is\nas expressions.  Several commands, such as \\fBexpr\\fR, \\fBfor\\fR,\nand \\fBif\\fR, treat one or more of their arguments as expressions\nand call the Tcl expression processors (\\fBTcl_ExprLong\\fR,\n\\fBTcl_ExprBoolean\\fR, etc.) to evaluate them.\nThe operators permitted in Tcl expressions are a subset of\nthe operators permitted in C expressions, and they have the\nsame meaning and precedence as the corresponding C operators.\nExpressions almost always yield numeric results\n(integer or floating-point values).\nFor example, the expression\n.DS\n\\fB8.2 + 6\\fR\n.DE\nevaluates to 14.2.\nTcl expressions differ from C expressions in the way that\noperands are specified, and in that Tcl expressions support\nnon-numeric operands and string comparisons.\n.PP\nA Tcl expression consists of a combination of operands, operators,\nand parentheses.\nWhite space may be used between the operands and operators and\nparentheses; it is ignored by the expression processor.\nWhere possible, operands are interpreted as integer values.\nInteger values may be specified in decimal (the normal case), in octal (if the\nfirst character of the operand is \\fB0\\fR), or in hexadecimal (if the first\ntwo characters of the operand are \\fB0x\\fR).\nIf an operand does not have one of the integer formats given\nabove, then it is treated as a floating-point number if that is\npossible.  Floating-point numbers may be specified in any of the\nways accepted by an ANSI-compliant C compiler (except that the\n``f'', ``F'', ``l'', and ``L'' suffixes will not be permitted in\nmost installations).  For example, all of the\nfollowing are valid floating-point numbers:  2.1, 3., 6e4, 7.91e+16.\nIf no numeric interpretation is possible, then an operand is left\nas a string (and only a limited set of operators may be applied to\nit).\n.PP\nOperands may be specified in any of the following ways:\n.IP [1]\nAs an numeric value, either integer or floating-point.\n.IP [2]\nAs a Tcl variable, using standard \\fB$\\fR notation.\nThe variable's value will be used as the operand.\n.IP [3]\nAs a string enclosed in double-quotes.\nThe expression parser will perform backslash, variable, and\ncommand substitutions on the information between the quotes,\nand use the resulting value as the operand\n.IP [4]\nAs a string enclosed in braces.\nThe characters between the open brace and matching close brace\nwill be used as the operand without any substitutions.\n.IP [5]\nAs a Tcl command enclosed in brackets.\nThe command will be executed and its result will be used as\nthe operand.\n.LP\nWhere substitutions occur above (e.g. inside quoted strings), they\nare performed by the expression processor.\nHowever, an additional layer of substitution may already have\nbeen performed by the command parser before the expression\nprocessor was called.\nAs discussed below, it is usually best to enclose expressions\nin braces to prevent the command parser from performing substitutions\non the contents.\n.PP\nFor some examples of simple expressions, suppose the variable\n\\fBa\\fR has the value 3 and\nthe variable \\fBb\\fR has the value 6.\nThen the expression on the left side of each of the lines below\nwill evaluate to the value on the right side of the line:\n.DS\n.ta 6c\n\\fB3.1 + $a\t6.1\n2 + \"$a.$b\"\t5.6\n4*[llength \"6 2\"]\t8\n{word one} < \"word $a\"\t0\\fR\n.DE\n.PP\nThe valid operators are listed below, grouped in decreasing order\nof precedence:\n.TP 20\n\\fB\\-\\0\\0~\\0\\0!\\fR\nUnary minus, bit-wise NOT, logical NOT.  None of these operands\nmay be applied to string operands, and bit-wise NOT may be\napplied only to integers.\n.TP 20\n\\fB*\\0\\0/\\0\\0%\\fR\nMultiply, divide, remainder.  None of these operands may be\napplied to string operands, and remainder may be applied only\nto integers.\n.TP 20\n\\fB+\\0\\0\\-\\fR\nAdd and subtract.  Valid for any numeric operands.\n.TP 20\n\\fB<<\\0\\0>>\\fR\nLeft and right shift.  Valid for integer operands only.\n.TP 20\n\\fB<\\0\\0>\\0\\0<=\\0\\0>=\\fR\nBoolean less, greater, less than or equal, and greater than or equal.\nEach operator produces 1 if the condition is true, 0 otherwise.\nThese operators may be applied to strings as well as numeric operands,\nin which case string comparison is used.\n.TP 20\n\\fB==\\0\\0!=\\fR\nBoolean equal and not equal.  Each operator produces a zero/one result.\nValid for all operand types.\n.TP 20\n\\fB&\\fR\nBit-wise AND.  Valid for integer operands only.\n.TP 20\n\\fB^\\fR\nBit-wise exclusive OR.  Valid for integer operands only.\n.TP 20\n\\fB|\\fR\nBit-wise OR.  Valid for integer operands only.\n.TP 20\n\\fB&&\\fR\nLogical AND.  Produces a 1 result if both operands are non-zero, 0 otherwise.\nValid for numeric operands only (integers or floating-point).\n.TP 20\n\\fB||\\fR\nLogical OR.  Produces a 0 result if both operands are zero, 1 otherwise.\nValid for numeric operands only (integers or floating-point).\n.TP 20\n\\fIx\\fB?\\fIy\\fB:\\fIz\\fR\nIf-then-else, as in C.  If \\fIx\\fR\nevaluates to non-zero, then the result is the value of \\fIy\\fR.\nOtherwise the result is the value of \\fIz\\fR.\nThe \\fIx\\fR operand must have a numeric value.\n.LP\nSee the C manual for more details on the results\nproduced by each operator.\nAll of the binary operators group left-to-right within the same\nprecedence level.  For example, the expression\n.DS\n\\fB4*2 < 7\\fR\n.DE\nevaluates to 0.\n.PP\nThe \\fB&&\\fP, \\fB||\\fP, and \\fB?:\\fP operators have ``lazy\nevaluation'', just as in C, \nwhich means that operands are not evaluated if they are\nnot needed to determine the outcome.  For example, in\n.DS\n\\fB$v ? [a] : [b]\\fR\n.DE\nonly one of \\fB[a]\\fR or \\fB[b]\\fR will actually be evaluated,\ndepending on the value of \\fB$v\\fP.\n.PP\nAll internal computations involving integers are done with the C type\n\\fIlong\\fP, and all internal computations involving floating-point are\ndone with the C type \\fIdouble\\fP.\nWhen converting a string to floating-point, exponent overflow is\ndetected and results in a Tcl error.\nFor conversion to integer from string, detection of overflow depends\non the behavior of some routines in the local C library, so it should\nbe regarded as unreliable.\nIn any case, overflow and underflow are generally not detected\nreliably for intermediate results.\n.PP\nConversion among internal representations for integer, floating-point,\nand string operands is done automatically as needed.\nFor arithmetic computations, integers are used until some\nfloating-point number is introduced, after which floating-point is used.\nFor example,\n.DS\n\\fB5 / 4\\fR\n.DE\nyields the result 1, while\n.DS\n\\fB5 / 4.0\\fR\n\\fB5 / ( [string length \"abcd\"] + 0.0 )\n.DE\nboth yield the result 1.25.\n.PP\nString values may be used as operands of the comparison operators,\nalthough the expression evaluator tries to do comparisons as integer\nor floating-point when it can.\nIf one of the operands of a comparison is a string and the other\nhas a numeric value, the numeric operand is converted back to\na string using the C \\fIsprintf\\fP format specifier\n\\fB%d\\fR for integers and \\fB%g\\fR for floating-point values.\nFor example, the expressions\n.DS\n\\fB\"0x03\" > \"2\"\\fR\n\\fB\"0y\" < \"0x12\"\\fR\n.DE\nboth evaluate to 1.  The first comparison is done using integer\ncomparison, and the second is done using string comparison after\nthe second operand is converted to the string ``18''.\n.VE\n.PP\nIn general it is safest to enclose an expression in braces when\nentering it in a command:  otherwise, if the expression contains\nany white space then the Tcl interpreter will split it\namong several arguments.  For example, the command\n.DS C\n\\fBexpr $a + $b\\fR\n.DE\nresults in three arguments being passed to \\fBexpr\\fR:  \\fB$a\\fR,\n\\fB+\\fR, and \\fB$b\\fR.  In addition, if the expression isn't in braces\nthen the Tcl interpreter will perform variable and command substitution\nimmediately (it will happen in the command parser rather than in\nthe expression parser).  In many cases the expression is being\npassed to a command that will evaluate the expression later (or\neven many times if, for example, the expression is to be used to\ndecide when to exit a loop).  Usually the desired goal is to re-do\nthe variable or command substitutions each time the expression is\nevaluated, rather than once and for all at the beginning.  For example,\nthe command\n.DS C\n.ta 7c\n\\fBfor {set i 1} $i<=10 {incr i} {...}\\fR\t*** WRONG ***\n.DE\nis probably intended to iterate over all values of \\fBi\\fR from 1 to 10.\nAfter each iteration of the body of the loop, \\fBfor\\fR will pass\nits second argument to the expression evaluator to see whether or not\nto continue processing.  Unfortunately, in this case the value of \\fBi\\fR\nin the second argument will be substituted once and for all when the\n\\fBfor\\fR command is parsed.  If \\fBi\\fR was 0 before the \\fBfor\\fR\ncommand was invoked then \\fBfor\\fR's second argument will be \\fB0<=10\\fR\nwhich will always evaluate to 1, even though \\fBi\\fR's value eventually\nbecomes greater than 10.  In the above case the loop will never\nterminate.  Instead, the expression should be placed in braces:\n.DS C\n.ta 7c\n\\fBfor {set i 1} {$i<=10} {incr i} {...}\\fR\t*** RIGHT ***\n.DE\nThis causes the substitution of \\fBi\\fR's\nvalue to be delayed; it will be re-done each time the expression is\nevaluated, which is the desired result.\n\n.SH LISTS\n.PP\nThe third major way that strings are interpreted in Tcl is as lists.\nA list is just a string with a list-like structure\nconsisting of fields separated by white space.  For example, the\nstring\n.DS\n\\fBAl Sue Anne John\\fR\n.DE\nis a list with four elements or fields.\nLists have the same basic structure as command strings, except\nthat a newline character in a list is treated as a field separator\njust like space or tab.  Conventions for braces and quotes\nand backslashes are the same for lists as for commands.  For example,\nthe string\n.DS\n\\fBa b\\e c {d e {f g h}}\\fR\n.DE\nis a list with three elements:  \\fBa\\fR, \\fBb c\\fR, and \\fBd e {f g h}\\fR.\nWhenever an element\nis extracted from a list, the same rules about braces and quotes and\nbackslashes are applied as for commands.  Thus in the example above\nwhen the third element is extracted from the list, the result is\n.DS\n\\fBd e {f g h}\\fR\n.DE\n(when the field was extracted, all that happened was to strip off\nthe outermost layer of braces).  Command substitution and\nvariable substitution are never\nmade on a list (at least, not by the list-processing commands; the\nlist can always be passed to the Tcl interpreter for evaluation).\n.PP\nThe Tcl commands \\fBconcat\\fR, \\fBforeach\\fR, \n.VS\n\\fBlappend\\fR, \\fBlindex\\fR, \\fBlinsert\\fR, \\fBlist\\fR, \\fBllength\\fR,\n\\fBlrange\\fR, \\fBlreplace\\fR, \\fBlsearch\\fR, and \\fBlsort\\fR allow\nyou to build lists,\n.VE\nextract elements from them, search them, and perform other list-related\nfunctions.\n\n.SH \"REGULAR EXPRESSIONS\"\n.VS\n.PP\nTcl provides two commands that support string matching using\n\\fBegrep\\fR-style regular expressions: \\fBregexp\\fR and \\fBregsub\\fR.\nRegular expressions are implemented using Henry Spencer's package,\nand the description of regular expressions below is copied verbatim\nfrom his manual entry.\n.PP\nA regular expression is zero or more \\fIbranches\\fR, separated by ``|''.\nIt matches anything that matches one of the branches.\n.PP\nA branch is zero or more \\fIpieces\\fR, concatenated.\nIt matches a match for the first, followed by a match for the second, etc.\n.PP\nA piece is an \\fIatom\\fR possibly followed by ``*'', ``+'', or ``?''.\nAn atom followed by ``*'' matches a sequence of 0 or more matches of the atom.\nAn atom followed by ``+'' matches a sequence of 1 or more matches of the atom.\nAn atom followed by ``?'' matches a match of the atom, or the null string.\n.PP\nAn atom is a regular expression in parentheses (matching a match for the\nregular expression), a \\fIrange\\fR (see below), ``.''\n(matching any single character), ``^'' (matching the null string at the\nbeginning of the input string), ``$'' (matching the null string at the\nend of the input string), a ``\\e'' followed by a single character (matching\nthat character), or a single character with no other significance\n(matching that character).\n.PP\nA \\fIrange\\fR is a sequence of characters enclosed in ``[]''.\nIt normally matches any single character from the sequence.\nIf the sequence begins with ``^'',\nit matches any single character \\fInot\\fR from the rest of the sequence.\nIf two characters in the sequence are separated by ``\\-'', this is shorthand\nfor the full list of ASCII characters between them\n(e.g. ``[0-9]'' matches any decimal digit).\nTo include a literal ``]'' in the sequence, make it the first character\n(following a possible ``^'').\nTo include a literal ``\\-'', make it the first or last character.\n.PP\nIf a regular expression could match two different parts of a string,\nit will match the one which begins earliest.\nIf both begin in the same place but match different lengths, or match\nthe same length in different ways, life gets messier, as follows.\n.PP\nIn general, the possibilities in a list of branches are considered in\nleft-to-right order, the possibilities for ``*'', ``+'', and ``?'' are\nconsidered longest-first, nested constructs are considered from the\noutermost in, and concatenated constructs are considered leftmost-first.\nThe match that will be chosen is the one that uses the earliest\npossibility in the first choice that has to be made.\nIf there is more than one choice, the next will be made in the same manner\n(earliest possibility) subject to the decision on the first choice.\nAnd so forth.\n.PP\nFor example, ``(ab|a)b*c'' could match ``abc'' in one of two ways.\nThe first choice is between ``ab'' and ``a''; since ``ab'' is earlier, and does\nlead to a successful overall match, it is chosen.\nSince the ``b'' is already spoken for,\nthe ``b*'' must match its last possibility\\(emthe empty string\\(emsince\nit must respect the earlier choice.\n.PP\nIn the particular case where no ``|''s are present and there is only one\n``*'', ``+'', or ``?'', the net effect is that the longest possible\nmatch will be chosen.\nSo ``ab*'', presented with ``xabbbby'', will match ``abbbb''.\nNote that if ``ab*'' is tried against ``xabyabbbz'', it\nwill match ``ab'' just after ``x'', due to the begins-earliest rule.\n(In effect, the decision on where to start the match is the first choice\nto be made, hence subsequent choices must respect it even if this leads them\nto less-preferred alternatives.)\n.VE\n\n.SH \"COMMAND RESULTS\"\n.PP\nEach command produces two results:  a code and a string.  The\ncode indicates whether the command completed successfully or not,\nand the string gives additional information.  The valid codes are\ndefined in tcl.h, and are:\n.RS\n.TP 20\n\\fBTCL_OK\\fR\nThis is the normal return code, and indicates that the command completed\nsuccessfully.  The string gives the command's return value.\n.TP 20\n\\fBTCL_ERROR\\fR\nIndicates that an error occurred; the string gives a message describing\nthe error.\n.VS\nIn addition, the global variable \\fBerrorInfo\\fR will contain\nhuman-readable information\ndescribing which commands and procedures were being executed when the\nerror occurred, and the global variable \\fBerrorCode\\fR will contain\nmachine-readable details about the error, if they are available.\nSee the section BUILT-IN VARIABLES below for more information.\n.VE\n.VE\n.TP 20\n\\fBTCL_RETURN\\fR\nIndicates that the \\fBreturn\\fR command has been invoked, and that the\ncurrent procedure (or top-level command or \\fBsource\\fR command)\nshould return immediately.  The\nstring gives the return value for the procedure or command.\n.TP 20\n\\fBTCL_BREAK\\fR\nIndicates that the \\fBbreak\\fR command has been invoked, so the\ninnermost loop should abort immediately.  The string should always\nbe empty.\n.TP 20\n\\fBTCL_CONTINUE\\fR\nIndicates that the \\fBcontinue\\fR command has been invoked, so the\ninnermost loop should go on to the next iteration.  The string\nshould always be empty.\n.RE\nTcl programmers do not normally need to think about return codes,\nsince TCL_OK is almost always returned.  If anything else is returned\nby a command, then the Tcl interpreter immediately stops processing\ncommands and returns to its caller.  If there are several nested\ninvocations of the Tcl interpreter in progress, then each nested\ncommand will usually return the error to its caller, until eventually\nthe error is reported to the top-level application code.  The\napplication will then display the error message for the user.\n.PP\nIn a few cases, some commands will handle certain ``error'' conditions\nthemselves and not return them upwards.  For example, the \\fBfor\\fR\ncommand checks for the TCL_BREAK code; if it occurs, then \\fBfor\\fR\nstops executing the body of the loop and returns TCL_OK to its\ncaller.  The \\fBfor\\fR command also handles TCL_CONTINUE codes and the\nprocedure interpreter handles TCL_RETURN codes.  The \\fBcatch\\fR\ncommand allows Tcl programs to catch errors and handle them without\naborting command interpretation any further.\n\n.SH PROCEDURES\n.PP\nTcl allows you to extend the command interface by defining\nprocedures.  A Tcl procedure can be invoked just like any other Tcl\ncommand (it has a name and it receives one or more arguments).\nThe only difference is that its body isn't a piece of C code linked\ninto the program; it is a string containing one or more other\nTcl commands.  See the \\fBproc\\fR command for information on\nhow to define procedures and what happens when they are invoked.\n\n.SH VARIABLES \\- SCALARS AND ARRAYS\n.VS\n.PP\nTcl allows the definition of variables and the use of their values\neither through \\fB$\\fR-style variable substitution, the \\fBset\\fR\ncommand, or a few other mechanisms.\nVariables need not be declared:  a new variable will automatically\nbe created each time a new variable name is used.\n.PP\nTcl supports two types of variables:  scalars and arrays.\nA scalar variable has a single value, whereas an array variable\ncan have any number of elements, each with a name (called\nits ``index'') and a value.\nArray indexes may be arbitrary strings; they need not be numeric.\nParentheses are used refer to array elements in Tcl commands.\nFor example, the command\n.DS C\n\\fBset x(first) 44\\fR\n.DE\nwill modify the element of \\fBx\\fR whose index is \\fBfirst\\fR\nso that its new value is \\fB44\\fR.\nTwo-dimensional arrays can be simulated in Tcl by using indexes\nthat contain multiple concatenated values.\nFor example, the commands\n.DS C\n\\fBset a(2,3) 1\\fR\n\\fBset a(3,6) 2\\fR\n.DE\nset the elements of \\fBa\\fR whose indexes are \\fB2,3\\fR and \\fB3,6\\fR.\n.PP\nIn general, array elements may be used anywhere in Tcl that scalar\nvariables may be used.\nIf an array is defined with a particular name, then there may\nnot be a scalar variable with the same name.\nSimilarly, if there is a scalar variable with a particular\nname then it is not possible to make array references to the\nvariable.\nTo convert a scalar variable to an array or vice versa, remove\nthe existing variable with the \\fBunset\\fR command.\n.PP\nThe \\fBarray\\fR command provides several features for dealing\nwith arrays, such as querying the names of all the elements of\nthe array and searching through the array one element at a time.\n.VE\n.PP\nVariables may be either global or local.  If a variable\nname is used when a procedure isn't being executed, then it\nautomatically refers to a global variable.  Variable names used\nwithin a procedure normally refer to local variables associated with that\ninvocation of the procedure.  Local variables are deleted whenever\na procedure exits.  The \\fBglobal\\fR command may be used to request\nthat a name refer to a global variable for the duration of the current\nprocedure (this is somewhat analogous to \\fBextern\\fR in C).\n\n.SH \"BUILT-IN COMMANDS\"\n.PP\nThe Tcl library provides the following built-in commands, which will\nbe available in any application using Tcl.  In addition to these\nbuilt-in commands, there may be additional commands defined by each\napplication, plus commands defined as Tcl procedures.\nIn the command syntax descriptions below, words in boldface are\nliterals that you type verbatim to Tcl.\nWords in italics are meta-symbols; they serve as names for any of\na range of values that you can type.\nOptional arguments or groups of arguments are indicated by enclosing them\nin question-marks.\nEllipses (``...'') indicate that any number of additional\narguments or groups of arguments may appear, in the same format\nas the preceding argument(s).\n.TP\n\\fBappend \\fIvarName value \\fR?\\fIvalue value ...\\fR?\n.VS\nAppend all of the \\fIvalue\\fR arguments to the current value\nof variable \\fIvarName\\fR.  If \\fIvarName\\fR doesn't exist,\nit is given a value equal to the concatenation of all the\n\\fIvalue\\fR arguments.\nThis command provides an efficient way to build up long\nvariables incrementally.\nFor example, ``\\fBappend a $b\\fR'' is much more efficient than\n``\\fBset a $a$b\\fR'' if \\fB$a\\fR is long.\n.VE\n.TP\n\\fBarray \\fIoption arrayName\\fR ?\\fIarg arg ...\\fR?\n.VS\nThis command performs one of several operations on the\nvariable given by \\fIarrayName\\fR.\n\\fIArrayName\\fR must be the name of an existing array variable.\nThe \\fIoption\\fR argument determines what action is carried\nout by the command.\nThe legal \\fIoptions\\fR (which may be abbreviated) are:\n.RS\n.TP\n\\fBarray anymore \\fIarrayName searchId\\fR\nReturns 1 if there are any more elements left to be processed\nin an array search, 0 if all elements have already been\nreturned.\n\\fISearchId\\fR indicates which search on \\fIarrayName\\fR to\ncheck, and must have been the return value from a previous\ninvocation of \\fBarray startsearch\\fR.\nThis option is particularly useful if an array has an element\nwith an empty name, since the return value from\n\\fBarray nextelement\\fR won't indicate whether the search\nhas been completed.\n.TP\n\\fBarray donesearch \\fIarrayName searchId\\fR\nThis command terminates an array search and destroys all the\nstate associated with that search.  \\fISearchId\\fR indicates\nwhich search on \\fIarrayName\\fR to destroy, and must have\nbeen the return value from a previous invocation of\n\\fBarray startsearch\\fR.  Returns an empty string.\n.TP\n\\fBarray names \\fIarrayName\\fR\nReturns a list containing the names of all of the elements in\nthe array.\nIf there are no elements in the array then an empty string is\nreturned.\n.TP\n\\fBarray nextelement \\fIarrayName searchId\\fR\nReturns the name of the next element in \\fIarrayName\\fR, or\nan empty string if all elements of \\fIarrayName\\fR have\nalready been returned in this search.  The \\fIsearchId\\fR\nargument identifies the search, and must have\nbeen the return value of an \\fBarray startsearch\\fR command.\nWarning:  if elements are added to or deleted from the array,\nthen all searches are automatically terminated just as if\n\\fBarray donesearch\\fR had been invoked; this will cause\n\\fBarray nextelement\\fR operations to fail for those searches.\n.TP\n\\fBarray size \\fIarrayName\\fR\nReturns a decimal string giving the number of elements in the\narray.\n.TP\n\\fBarray startsearch \\fIarrayName\\fR\nThis command initializes an element-by-element search through the\narray given by \\fIarrayName\\fR, such that invocations of the\n\\fBarray nextelement\\fR command will return the names of the\nindividual elements in the array.\nWhen the search has been completed, the \\fBarray donesearch\\fR\ncommand should be invoked.\nThe return value is a\nsearch identifier that must be used in \\fBarray nextelement\\fR\nand \\fBarray donesearch\\fR commands; it allows multiple\nsearches to be underway simultaneously for the same array.\n.VE\n.RE\n.TP\n\\fBbreak\\fR\nThis command may be invoked only inside the body of a loop command\nsuch as \\fBfor\\fR or \\fBforeach\\fR or \\fBwhile\\fR.  It returns a TCL_BREAK code\nto signal the innermost containing loop command to return immediately.\n.TP\n\\fBcase\\fI string \\fR?\\fBin\\fR? \\fIpatList body \\fR?\\fIpatList body \\fR...?\n.TP\n\\fBcase\\fI string \\fR?\\fBin\\fR? {\\fIpatList body \\fR?\\fIpatList body \\fR...?}\nMatch \\fIstring\\fR against each of the \\fIpatList\\fR arguments\nin order.  If one matches, then evaluate the following \\fIbody\\fR argument\nby passing it recursively to the Tcl interpreter, and return the result\nof that evaluation.  Each \\fIpatList\\fR argument consists of a single\npattern or list of patterns.  Each pattern may contain any of the wild-cards\ndescribed under \\fBstring match\\fR.  If a \\fIpatList\\fR\nargument is \\fBdefault\\fR, the corresponding body will be evaluated\nif no \\fIpatList\\fR matches \\fIstring\\fR.  If no \\fIpatList\\fR argument\nmatches \\fIstring\\fR and no default is given, then the \\fBcase\\fR\ncommand returns an empty string.\n.RS\n.PP\nTwo syntaxes are provided.\nThe first uses a separate argument for each of the patterns and commands;\nthis form is convenient if substitutions are desired on some of the\npatterns or commands.\n.VS\nThe second form places all of the patterns and commands together into\na single argument; the argument must have proper list structure, with\nthe elements of the list being the patterns and commands.\nThe second form makes it easy to construct multi-line case commands,\nsince the braces around the whole list make it unnecessary to include a\nbackslash at the end of each line.\nSince the \\fIpatList\\fR arguments are in braces in the second form,\nno command or variable substitutions are performed on them;  this makes\nthe behavior of the second form different than the first form in some\ncases.\n.PP\nBelow are some examples of \\fBcase\\fR commands:\n.DS\n\\fBcase abc in {a b} {format 1} default {format 2} a* {format 3}\n.DE\nwill return \\fB3\\fR, \n.DS\n.ta .5c 1c\n\\fBcase a in {\n\t{a b} {format 1}\n\tdefault {format 2}\n\ta* {format 3}\n}\n.DE\nwill return \\fB1\\fR, and\n.DS\n.ta .5c 1c\n\\fBcase xyz {\n\t{a b}\n\t\t{format 1}\n\tdefault\n\t\t{format 2}\n\ta*\n\t\t{format 3}\n}\n.DE\nwill return \\fB2\\fR.\n.VE\n.RE\n.TP\n\\fBcatch\\fI command \\fR?\\fIvarName\\fR?\nThe \\fBcatch\\fR command may be used to prevent errors from aborting\ncommand interpretation.  \\fBCatch\\fR calls the Tcl interpreter recursively\nto execute \\fIcommand\\fR, and always returns a TCL_OK code, regardless of\nany errors that might occur while executing \\fIcommand\\fR.  The return\nvalue from \\fBcatch\\fR is a decimal string giving the\ncode returned by the Tcl interpreter after executing \\fIcommand\\fR.\nThis will be \\fB0\\fR (TCL_OK) if there were no errors in \\fIcommand\\fR; otherwise\nit will have a non-zero value corresponding to one of the exceptional\nreturn codes (see tcl.h for the definitions of code values).  If the\n\\fIvarName\\fR argument is given, then it gives the name of a variable;\n\\fBcatch\\fR will set the value of the variable to the string returned\nfrom \\fIcommand\\fR (either a result or an error message).\n.TP\n\\fBcd \\fR?\\fIdirName\\fR?\n.VS\nChange the current working directory to \\fIdirName\\fR, or to the\nhome directory (as specified in the HOME environment variable) if\n\\fIdirName\\fR is not given.\nIf \\fIdirName\\fR starts with a tilde, then tilde-expansion is\ndone as described for \\fBTcl_TildeSubst\\fR.\nReturns an empty string.\nThis command can potentially be disruptive to an application,\nso it may be removed in some applications.\n.TP\n\\fBclose \\fIfileId\\fR\nCloses the file given by \\fIfileId\\fR.\n\\fIFileId\\fR must be the return value from a previous invocation\nof the \\fBopen\\fR command; after this command, it should not be\nused anymore.\nIf \\fIfileId\\fR refers to a command pipeline instead of a file,\nthen \\fBclose\\fR waits for the children to complete.\nThe normal result of this command is an empty string, but errors\nare returned if there are problems in closing the file or waiting\nfor children to complete.\n.VE\n.TP\n\\fBconcat\\fI arg \\fR?\\fIarg ...\\fR?\nThis command treats each argument as a list and concatenates them\ninto a single list.  It permits any number of arguments.  For example,\nthe command\n.RS\n.DS\n\\fBconcat a b {c d e} {f {g h}}\\fR\n.DE\nwill return\n.DS\n\\fBa b c d e f {g h}\\fR\n.DE\nas its result.\n.RE\n.TP\n\\fBcontinue\\fR\nThis command may be invoked only inside the body of a loop command\nsuch as \\fBfor\\fR or \\fBforeach\\fR or \\fBwhile\\fR.  It\nreturns a  TCL_CONTINUE code\nto signal the innermost containing loop command to skip the\nremainder of the loop's body\nbut continue with the next iteration of the loop.\n.TP\n\\fBeof \\fIfileId\\fR\n.VS\nReturns 1 if an end-of-file condition has occurred on \\fIfileId\\fR,\n0 otherwise.\n\\fIFileId\\fR must have been the return\nvalue from a previous call to \\fBopen\\fR, or it may be \\fBstdin\\fR,\n\\fBstdout\\fR, or \\fBstderr\\fR to refer to one of the standard I/O\nchannels.\n.VE\n.TP\n\\fBerror \\fImessage\\fR ?\\fIinfo\\fR? ?\\fIcode\\fR?\nReturns a TCL_ERROR code, which causes command interpretation to be\nunwound.  \\fIMessage\\fR is a string that is returned to the application\nto indicate what went wrong.\n.RS\n.PP\nIf the \\fIinfo\\fR argument is provided and is non-empty,\nit is used to initialize the global variable \\fBerrorInfo\\fR.\n\\fBerrorInfo\\fR is used to accumulate a stack trace of what\nwas in progress when an error occurred; as nested commands unwind,\nthe Tcl interpreter adds information to \\fBerrorInfo\\fR.  If the\n\\fIinfo\\fR argument is present, it is used to initialize\n\\fBerrorInfo\\fR and the first increment of unwind information\nwill not be added by the Tcl interpreter.  In other\nwords, the command containing the \\fBerror\\fR command will not appear\nin \\fBerrorInfo\\fR; in its place will be \\fIinfo\\fR.\nThis feature is most useful in conjunction with the \\fBcatch\\fR command:\nif a caught error cannot be handled successfully, \\fIinfo\\fR can be used\nto return a stack trace reflecting the original point of occurrence\nof the error:\n.DS\n\\fBcatch {...} errMsg\nset savedInfo $errorInfo\n\\&...\nerror $errMsg $savedInfo\\fR\n.DE\n.PP\n.VS\nIf the \\fIcode\\fR argument is present, then its value is stored\nin the \\fBerrorCode\\fR global variable.  This variable is intended\nto hold a machine-readable description of the error in cases where\nsuch information is available; see the section BUILT-IN VARIABLES\nbelow for information on the proper format for the variable.\nIf the \\fIcode\\fR argument is not\npresent, then \\fBerrorCode\\fR is automatically reset to\n``NONE'' by the Tcl interpreter as part of processing the\nerror generated by the command.\n.VE\n.RE\n.TP\n\\fBeval \\fIarg \\fR?\\fIarg ...\\fR?\n\\fBEval\\fR takes one or more arguments, which together comprise a Tcl\ncommand (or collection of Tcl commands separated by newlines in the\nusual way).  \\fBEval\\fR concatenates all its arguments in the same\nfashion as the \\fBconcat\\fR command, passes the concatenated string to the\nTcl interpreter recursively, and returns the result of that\nevaluation (or any error generated by it).\n.TP\n\\fBexec \\fIarg \\fR?\\fIarg ...\\fR?\n.VS\nThis command treats its arguments as the specification\nof one or more UNIX commands to execute as subprocesses.\nThe commands take the form of a standard shell pipeline;\n``|'' arguments separate commands in the\npipeline and cause standard output of the preceding command\nto be piped into standard input of the next command.\n.RS\n.PP\nUnder normal conditions the result of the \\fBexec\\fR command\nconsists of the standard output produced by the last command\nin the pipeline.\nIf any of the commands in the pipeline exit abnormally or\nare killed or suspended, then \\fBexec\\fR will return an error\nand the error message will include the pipeline's output followed by\nerror messages describing the abnormal terminations; the\n\\fBerrorCode\\fR variable will contain additional information\nabout the last abnormal termination encountered.\nIf any of the commands writes to its standard error file,\nthen \\fBexec\\fR will return an error, and the error message\nwill include the pipeline's output, followed by messages\nabout abnormal terminations (if any), followed by the standard error\noutput.\n.PP\nIf the last character of the result or error message\nis a newline then that character is deleted from the result\nor error message for consistency with normal\nTcl return values.\n.PP\nIf an \\fIarg\\fR has the value ``>'' then the\nfollowing argument is taken as the name of a file and\nthe standard output of the last command in the pipeline\nis redirected to the file.  In this situation \\fBexec\\fR\nwill normally return an empty string.\n.PP\nIf an \\fIarg\\fR has the value ``<'' then the following\nargument is taken as the name of a file to use\nfor standard input to the first command in the\npipeline.\nIf an argument has the value ``<<'' then the following\nargument is taken as an immediate value to be passed to\nthe first command as standard input.\nIf there is no ``<'' or ``<<'' argument then the standard\ninput for the first command in the pipeline is taken from\nthe application's current standard input.\n.PP\nIf the last \\fIarg\\fR is ``&'' then the command will be\nexecuted in background.\nIn this case the standard output from the last command\nin the pipeline will\ngo to the application's standard output unless\nredirected in the command, and error output from all\nthe commands in the pipeline will go to the application's\nstandard error file.\n.PP\nEach \\fIarg\\fR becomes one word for a command, except for\n``|'', ``<'', ``<<'', ``>'', and ``&'' arguments, and the\narguments that follow ``<'', ``<<'', and ``>''.\nThe first word in each command is taken as the command name;\ntilde-substitution is performed on it, and the directories\nin the PATH environment variable are searched for\nan executable by the given name.\nNo ``glob'' expansion or other shell-like substitutions\nare performed on the arguments to commands.\n.RE\n.TP\n\\fBexit \\fR?returnCode\\fR?\nTerminate the process, returning \\fIreturnCode\\fR to the\nparent as the exit status.\nIf \\fIreturnCode\\fR isn't specified then it defaults\nto 0.\n.VE\n.TP\n\\fBexpr \\fIarg\\fR\nCalls the expression processor to evaluate \\fIarg\\fR, and returns\nthe result as a string.  See the section EXPRESSIONS above.\n.TP\n\\fBfile \\fIoption\\fR \\fIname\\fR ?\\fIarg arg ...\\fR?\n.VS\nOperate on a file or a file name.  \\fIName\\fR is the name of a file;\nif it starts with a tilde, then tilde substitution is done before\nexecuting the command (see the manual entry for \\fBTcl_TildeSubst\\fR\nfor details).\n\\fIOption\\fR indicates what to do with the file name.  Any unique\nabbreviation for \\fIoption\\fR is acceptable.  The valid options are:\n.RS\n.TP\n\\fBfile \\fBatime \\fIname\\fR\nReturn a decimal string giving the time at which file \\fIname\\fR\nwas last accessed.  The time is measured in the standard UNIX\nfashion as seconds from a fixed starting time (often January 1, 1970).\nIf the file doesn't exist or its access time cannot be queried then an\nerror is generated.\n.TP\n\\fBfile \\fBdirname \\fIname\\fR\nReturn all of the characters in \\fIname\\fR up to but not including\nthe last slash character.  If there are no slashes in \\fIname\\fR\nthen return ``.''.  If the last slash in \\fIname\\fR is its first\ncharacter, then return ``/''.\n.TP\n\\fBfile \\fBexecutable \\fIname\\fR\nReturn \\fB1\\fR if file \\fIname\\fR is executable by\nthe current user, \\fB0\\fR otherwise.\n.TP\n\\fBfile \\fBexists \\fIname\\fR\nReturn \\fB1\\fR if file \\fIname\\fR exists and the current user has\nsearch privileges for the directories leading to it, \\fB0\\fR otherwise.\n.TP\n\\fBfile \\fBextension \\fIname\\fR\nReturn all of the characters in \\fIname\\fR after and including the\nlast dot in \\fIname\\fR.  If there is no dot in \\fIname\\fR then return\nthe empty string.\n.TP\n\\fBfile \\fBisdirectory \\fIname\\fR\nReturn \\fB1\\fR if file \\fIname\\fR is a directory,\n\\fB0\\fR otherwise.\n.TP\n\\fBfile \\fBisfile \\fIname\\fR\nReturn \\fB1\\fR if file \\fIname\\fR is a regular file,\n\\fB0\\fR otherwise.\n.TP\n\\fBfile lstat \\fIname varName\\fR\nSame as \\fBstat\\fR option (see below) except uses the \\fIlstat\\fR\nkernel call instead of \\fIstat\\fR.  This means that if \\fIname\\fR\nrefers to a symbolic link the information returned in \\fIvarName\\fR\nis for the link rather than the file it refers to.  On systems that\ndon't support symbolic links this option behaves exactly the same\nas the \\fBstat\\fR option.\n.TP\n\\fBfile \\fBmtime \\fIname\\fR\nReturn a decimal string giving the time at which file \\fIname\\fR\nwas last modified.  The time is measured in the standard UNIX\nfashion as seconds from a fixed starting time (often January 1, 1970).\nIf the file doesn't exist or its modified time cannot be queried then an\nerror is generated.\n.TP\n\\fBfile \\fBowned \\fIname\\fR\nReturn \\fB1\\fR if file \\fIname\\fR is owned by the current user,\n\\fB0\\fR otherwise.\n.TP\n\\fBfile \\fBreadable \\fIname\\fR\nReturn \\fB1\\fR if file \\fIname\\fR is readable by\nthe current user, \\fB0\\fR otherwise.\n.TP\n\\fBfile readlink \\fIname\\fR\nReturns the value of the symbolic link given by \\fIname\\fR (i.e. the\nname of the file it points to).  If\n\\fIname\\fR isn't a symbolic link or its value cannot be read, then\nan error is returned.  On systems that don't support symbolic links\nthis option is undefined.\n.TP\n\\fBfile \\fBrootname \\fIname\\fR\nReturn all of the characters in \\fIname\\fR up to but not including\nthe last ``.'' character in the name.  If \\fIname\\fR doesn't contain\na dot, then return \\fIname\\fR.\n.TP\n\\fBfile \\fBsize \\fIname\\fR\nReturn a decimal string giving the size of file \\fIname\\fR in bytes.\nIf the file doesn't exist or its size cannot be queried then an\nerror is generated.\n.TP\n\\fBfile \\fBstat  \\fIname varName\\fR\nInvoke the \\fBstat\\fR kernel call on \\fIname\\fR, and use the\nvariable given by \\fIvarName\\fR to hold information returned from\nthe kernel call.\n\\fIVarName\\fR is treated as an array variable,\nand the following elements of that variable are set: \\fBatime\\fR,\n\\fBctime\\fR, \\fBdev\\fR, \\fBgid\\fR, \\fBino\\fR, \\fBmode\\fR, \\fBmtime\\fR,\n\\fBnlink\\fR, \\fBsize\\fR, \\fBtype\\fR, \\fBuid\\fR.\nEach element except \\fBtype\\fR is a decimal string with the value of\nthe corresponding field from the \\fBstat\\fR return structure; see the\nmanual entry for \\fBstat\\fR for details on the meanings of the values.\nThe \\fBtype\\fR element gives the type of the file in the same form\nreturned by the command \\fBfile type\\fR.\nThis command returns an empty string.\n.TP\n\\fBfile \\fBtail \\fIname\\fR\nReturn all of the characters in \\fIname\\fR after the last slash.\nIf \\fIname\\fR contains no slashes then return \\fIname\\fR.\n.TP\n\\fBfile \\fBtype \\fIname\\fR\nReturns a string giving the type of file \\fIname\\fR, which will be\none of \\fBfile\\fR, \\fBdirectory\\fR, \\fBcharacterSpecial\\fR,\n\\fBblockSpecial\\fR, \\fBfifo\\fR, \\fBlink\\fR, or \\fBsocket\\fR.\n.TP\n\\fBfile \\fBwritable \\fIname\\fR\nReturn \\fB1\\fR if file \\fIname\\fR is writable by\nthe current user, \\fB0\\fR otherwise.\n.RE\n.IP\nThe \\fBfile\\fR commands that return 0/1 results are often used in\nconditional or looping commands, for example:\n.RS\n.DS\n\\fBif {![file exists foo]} then {error {bad file name}} else {...}\\fR\n.DE\n.VE\n.RE\n.TP\n\\fBflush \\fIfileId\\fR\n.VS\nFlushes any output that has been buffered for \\fIfileId\\fR.\n\\fIFileId\\fR must have been the return\nvalue from a previous call to \\fBopen\\fR, or it may be\n\\fBstdout\\fR or \\fBstderr\\fR to access one of the standard I/O streams;\nit must refer to a file that was opened for writing.\nThis command returns an empty string.\n.VE\n.TP\n\\fBfor \\fIstart test next body\\fR\n\\fBFor\\fR is a looping command, similar in structure to the C\n\\fBfor\\fR statement.  The \\fIstart\\fR, \\fInext\\fR, and\n\\fIbody\\fR arguments must be Tcl command strings, and \\fItest\\fR\nis an expression string.\nThe \\fBfor\\fR command first invokes the Tcl interpreter to\nexecute \\fIstart\\fR.  Then it repeatedly evaluates \\fItest\\fR as\nan expression; if the result is non-zero it invokes the Tcl\ninterpreter on \\fIbody\\fR, then invokes the Tcl interpreter on \\fInext\\fR,\nthen repeats the loop.  The command terminates when \\fItest\\fR evaluates\nto 0.  If a \\fBcontinue\\fR command is invoked within \\fIbody\\fR then\nany remaining commands in the current execution of \\fIbody\\fR are skipped;\nprocessing continues by invoking the Tcl interpreter on \\fInext\\fR, then\nevaluating \\fItest\\fR, and so on.  If a \\fBbreak\\fR command is invoked\nwithin \\fIbody\\fR\nor \\fInext\\fR,\nthen the \\fBfor\\fR command will\nreturn immediately.\nThe operation of \\fBbreak\\fR and \\fBcontinue\\fR are similar to the\ncorresponding statements in C.\n\\fBFor\\fR returns an empty string.\n.TP\n\\fBforeach \\fIvarname list body\\fR\nIn this command, \\fIvarname\\fR is the name of a variable, \\fIlist\\fR\nis a list of values to assign to \\fIvarname\\fR, and \\fIbody\\fR is a\ncollection of Tcl commands.  For each field in \\fIlist\\fR (in order\nfrom left to right), \\fBforeach\\fR assigns the contents of the\nfield to \\fIvarname\\fR (as if the \\fBlindex\\fR command had been used\nto extract the field), then calls the Tcl interpreter to execute\n\\fIbody\\fR.  The \\fBbreak\\fR and \\fBcontinue\\fR statements may be\ninvoked inside \\fIbody\\fR, with the same effect as in the \\fBfor\\fR\ncommand.  \\fBForeach\\fR returns an empty string.\n.TP\n\\fBformat \\fIformatString \\fR?\\fIarg arg ...\\fR?\nThis command generates a formatted string in the same way as the\nC \\fBsprintf\\fR procedure (it uses \\fBsprintf\\fR in its\nimplementation).  \\fIFormatString\\fR indicates how to format\nthe result, using \\fB%\\fR fields as in \\fBsprintf\\fR, and the additional\narguments, if any, provide values to be substituted into the result.\nAll of the \\fBsprintf\\fR options are valid; see the \\fBsprintf\\fR\nman page for details.  Each \\fIarg\\fR must match the expected type\nfrom the \\fB%\\fR field in \\fIformatString\\fR; the \\fBformat\\fR command\nconverts each argument to the correct type (floating, integer, etc.)\nbefore passing it to \\fBsprintf\\fR for formatting.\nThe only unusual conversion is for \\fB%c\\fR; in this case the argument\nmust be a decimal string, which will then be converted to the corresponding\nASCII character value.\n\\fBFormat\\fR does backslash substitution on its \\fIformatString\\fR\nargument, so backslash sequences in \\fIformatString\\fR will be handled\ncorrectly even if the argument is in braces.\nThe return value from \\fBformat\\fR\nis the formatted string.\n.TP\n\\fBgets \\fIfileId\\fR ?\\fIvarName\\fR?\n.VS\nReads the next line from the file given by \\fIfileId\\fR and discards\nthe terminating newline character.\nIf \\fIvarName\\fR is specified, then the line is placed in the variable\nby that name and the return value is a count of the number of characters\nread (not including the newline).\nIf the end of the file is reached before reading\nany characters then \\-1 is returned and \\fIvarName\\fR is set to an\nempty string.\nIf \\fIvarName\\fR is not specified then the return value will be\nthe line (minus the newline character) or an empty string if\nthe end of the file is reached before reading any characters.\nAn empty string will also be returned if a line contains no characters\nexcept the newline, so \\fBeof\\fR may have to be used to determine\nwhat really happened.\nIf the last character in the file is not a newline character, then\n\\fBgets\\fR behaves as if there were an additional newline character\nat the end of the file.\n\\fIFileId\\fR must be \\fBstdin\\fR or the return value from a previous\ncall to \\fBopen\\fR; it must refer to a file that was opened\nfor reading.\n.VE\n.TP\n\\fBglob \\fR?\\fB\\-nocomplain\\fR? \\fIfilename\\fR ?\\fIfilename ...\\fR?\nThis command performs filename globbing, using csh rules.  The returned\nvalue from \\fBglob\\fR is the list of expanded filenames.\n.VS\nIf \\fB\\-nocomplain\\fR is specified as the first argument then an empty\nlist may be returned;  otherwise an error is returned if the expanded\nlist is empty.  The \\fB\\-nocomplain\\fR argument must be provided\nexactly: an abbreviation will not be accepted.\n.VE\n.TP\n\\fBglobal \\fIvarname \\fR?\\fIvarname ...\\fR?\nThis command is ignored unless a Tcl procedure is being interpreted.\nIf so, then it declares the given \\fIvarname\\fR's to be global variables\nrather than local ones.  For the duration of the current procedure\n(and only while executing in the current procedure), any reference to\nany of the \\fIvarname\\fRs will be bound to a global variable instead\nof a local one.\n.TP\n\\fBhistory \\fR?\\fIoption\\fR? ?\\fIarg arg ...\\fR?\nNote:  this command may not be available in all Tcl-based applications.\nTypically, only those that receive command input in a typescript\nform will support history.\nThe \\fBhistory\\fR command performs one of several operations related to\nrecently-executed commands recorded in a history list.  Each of\nthese recorded commands is referred to as an ``event''.  When\nspecifying an event to the \\fBhistory\\fR command, the following\nforms may be used:\n.RS\n.IP [1]\nA number:  if positive, it refers to the event with\nthat number (all events are numbered starting at 1).  If the number\nis negative, it selects an event relative to the current event\n(\\fB\\-1\\fR refers to the previous event, \\fB\\-2\\fR to the one before that, and\nso on).\n.IP [2]\nA string:  selects the most recent event that matches the string.\nAn event is considered to match the string either if the string is\nthe same as the first characters of the event, or if the string\nmatches the event in the sense of the \\fBstring match\\fR command.\n.LP\nThe \\fBhistory\\fR command can take any of the following forms:\n.TP\n\\fBhistory\\fR\nSame\n.VS\nas \\fBhistory info\\fR, described below.\n.VE\n.TP\n\\fBhistory add\\fI command \\fR?\\fBexec\\fR?\nAdd the \\fIcommand\\fR argument to the history list as a new event.  If\n\\fBexec\\fR is specified (or abbreviated) then the command is also\nexecuted and its result is returned.  If \\fBexec\\fR isn't specified\nthen an empty string is returned as result.\n.TP\n\\fBhistory change\\fI newValue\\fR ?\\fIevent\\fR?\nReplace the value recorded for an event with \\fInewValue\\fR.  \\fIEvent\\fR\nspecifies the event to replace, and\ndefaults to the \\fIcurrent\\fR event (not event \\fB\\-1\\fR).  This command\nis intended for use in commands that implement new forms of history\nsubstitution and wish to replace the current event (which invokes the\nsubstitution) with the command created through substitution.  The return\nvalue is an empty string.\n.TP\n\\fBhistory event\\fR ?\\fIevent\\fR?\nReturns the value of the event given by \\fIevent\\fR.  \\fIEvent\\fR\ndefaults to \\fB\\-1\\fR.  This command causes history revision to occur:\nsee below for details.\n.TP\n\\fBhistory info \\fR?\\fIcount\\fR?\nReturns a formatted string (intended for humans to read) giving\nthe event number and contents for each of the events in the history\nlist except the current event.  If \\fIcount\\fR is specified\nthen only the most recent \\fIcount\\fR events are returned.\n.TP\n\\fBhistory keep \\fIcount\\fR\nThis command may be used to change the size of the history list to\n\\fIcount\\fR events.  Initially, 20 events are retained in the history\nlist.  This command returns an empty string.\n.TP\n\\fBhistory nextid\\fR\nReturns the number of the next event to be recorded\nin the history list.  It is useful for things like printing the\nevent number in command-line prompts.\n.TP\n\\fBhistory redo \\fR?\\fIevent\\fR?\nRe-execute the command indicated by \\fIevent\\fR and return its result.\n\\fIEvent\\fR defaults to \\fB\\-1\\fR.  This command results in history\nrevision:  see below for details.\n.TP\n\\fBhistory substitute \\fIold new \\fR?\\fIevent\\fR?\nRetrieve the command given by \\fIevent\\fR\n(\\fB\\-1\\fR by default), replace any occurrences of \\fIold\\fR by\n\\fInew\\fR in the command (only simple character equality is supported;\nno wild cards), execute the resulting command, and return the result\nof that execution.  This command results in history\nrevision:  see below for details.\n.TP\n\\fBhistory words \\fIselector\\fR ?\\fIevent\\fR?\nRetrieve from the command given by \\fIevent\\fR (\\fB\\-1\\fR by default)\nthe words given by \\fIselector\\fR, and return those words in a string\nseparated by spaces.  The \\fBselector\\fR argument has three forms.\nIf it is a single number then it selects the word given by that\nnumber (\\fB0\\fR for the command name, \\fB1\\fR for its first argument,\nand so on).  If it consists of two numbers separated by a dash,\nthen it selects all the arguments between those two.  Otherwise\n\\fBselector\\fR is treated as a pattern; all words matching that\npattern (in the sense of \\fBstring match\\fR) are returned.  In\nthe numeric forms \\fB$\\fR may be used\nto select the last word of a command.\nFor example, suppose the most recent command in the history list is\n.RS\n.DS\n\\fBformat  {%s is %d years old} Alice [expr $ageInMonths/12]\\fR\n.DE\nBelow are some history commands and the results they would produce:\n.DS\n.ta 4c\n.fi\n.UL Command \"\t\"\n.UL Result\n.nf\n\n\\fBhistory words $\t[expr $ageInMonths/12]\\fR\n\\fBhistory words 1-2\t{%s is %d years  old} Alice\\fR\n\\fBhistory words *a*o*\t{%s is %d years old} [expr $ageInMonths/12]\\fR\n.DE\n\\fBHistory words\\fR results in history revision:  see below for details.\n.RE\nThe history options \\fBevent\\fR, \\fBredo\\fR, \\fBsubstitute\\fR,\nand \\fBwords\\fR result in ``history revision''.\nWhen one of these options is invoked then the current event\nis modified to eliminate the history command and replace it with\nthe result of the history command.\nFor example, suppose that the most recent command in the history\nlist is\n.DS\n\\fBset a [expr $b+2]\\fR\n.DE\nand suppose that the next command invoked is one of the ones on\nthe left side of the table below.  The command actually recorded in\nthe history event will be the corresponding one on the right side\nof the table.\n.ne 1.5c\n.DS\n.ta 4c\n.fi\n.UL \"Command Typed\" \"\t\"\n.UL \"Command Recorded\"\n.nf\n\n\\fBhistory redo\tset a [expr $b+2]\\fR\n\\fBhistory s a b\tset b [expr $b+2]\\fR\n\\fBset c [history w 2]\tset c [expr $b+2]\\fR\n.DE\n.VS\nHistory revision is needed because event specifiers like \\fB\\-1\\fR\nare only valid at a particular time:  once more events have been\nadded to the history list a different event specifier would be\nneeded.\nHistory revision occurs even when \\fBhistory\\fR is invoked\nindirectly from the current event (e.g. a user types a command\nthat invokes a Tcl procedure that invokes \\fBhistory\\fR):  the\ntop-level command whose execution eventually resulted in a\n\\fBhistory\\fR command is replaced.\nIf you wish to invoke commands like \\fBhistory words\\fR without\nhistory revision, you can use \\fBhistory event\\fR to save the\ncurrent history event and then use \\fBhistory change\\fR to\nrestore it later.\n.VE\n.RE\n.TP\n\\fBif \\fIexpr1 \\fR?\\fBthen\\fR? \\fIbody1 \\fBelseif \\fIexpr2 \\fR?\\fBthen\\fR? \\fIbody2\\fR \\fBelseif\\fR ... \\fR?\\fBelse\\fR? ?\\fIbodyN\\fR?\n.VS\nThe \\fIif\\fR command evaluates \\fIexpr1\\fR as an expression (in the\nsame way that \\fBexpr\\fR evaluates its argument).  The value of the\nexpression must be numeric; if it\nis non-zero then \\fIbody1\\fR is executed by passing it to the\nTcl interpreter.\nOtherwise \\fIexpr2\\fR is evaluated as an expression and if it is non-zero\nthen \\fBbody2\\fR is executed, and so on.\nIf none of the expressions evaluates to non-zero then \\fIbodyN\\fR is\nexecuted.\nThe \\fBthen\\fR and \\fBelse\\fR arguments are optional\n``noise words'' to make the command easier to read.\nThere may be any number of \\fBelseif\\fR clauses, including zero.\n\\fIBodyN\\fR may also be omitted as long as \\fBelse\\fR is omitted too.\nThe return value from the command is the result of the body script\nthat was executed, or an empty string\nif none of the expressions was non-zero and there was no \\fIbodyN\\fR.\n.VE\n.TP\n\\fBincr \\fIvarName \\fR?\\fIincrement\\fR?\n.VS\nIncrement the value stored in the variable whose name is \\fIvarName\\fR.\nThe value of the variable must be integral.\nIf \\fIincrement\\fR is supplied then its value (which must be an\ninteger) is added to the value of variable \\fIvarName\\fR;  otherwise\n1 is added to \\fIvarName\\fR.\nThe new value is stored as a decimal string in variable \\fIvarName\\fR\nand also returned as result.\n.VE\n.TP\n\\fBinfo \\fIoption \\fR?\\fIarg arg ...\\fR?\nProvide information about various internals to the Tcl interpreter.\nThe legal \\fIoption\\fR's (which may be abbreviated) are:\n.RS\n.TP\n\\fBinfo args \\fIprocname\\fR\nReturns a list containing the names of the arguments to procedure\n\\fIprocname\\fR, in order.  \\fIProcname\\fR must be the name of a\nTcl command procedure.\n.TP\n\\fBinfo body \\fIprocname\\fR\nReturns the body of procedure \\fIprocname\\fR.  \\fIProcname\\fR must be\nthe name of a Tcl command procedure.\n.TP\n\\fBinfo cmdcount\\fR\nReturns a count of the total number of commands that have been invoked\nin this interpreter.\n.TP\n\\fBinfo commands \\fR?\\fIpattern\\fR?\nIf \\fIpattern\\fR isn't specified, returns a list of names of all the\nTcl commands, including both the built-in commands written in C and\nthe command procedures defined using the \\fBproc\\fR command.\nIf \\fIpattern\\fR is specified, only those names matching \\fIpattern\\fR\nare returned.  Matching is determined using the same rules as for\n\\fBstring match\\fR.\n.TP\n\\fBinfo complete \\fIcommand\\fR\n.VS\nReturns 1 if \\fIcommand\\fR is a complete Tcl command in the sense of\nhaving no unclosed quotes, braces, brackets or array element names,\nIf the command doesn't appear to be complete then 0 is returned.\nThis command is typically used in line-oriented input environments\nto allow users to type in commands that span multiple lines;  if the\ncommand isn't complete, the script can delay evaluating it until additional\nlines have been typed to complete the command.\n.VE\n.TP\n\\fBinfo default \\fIprocname arg varname\\fR\n\\fIProcname\\fR must be the name of a Tcl command procedure and \\fIarg\\fR\nmust be the name of an argument to that procedure.  If \\fIarg\\fR\ndoesn't have a default value then the command returns \\fB0\\fR.\nOtherwise it returns \\fB1\\fR and places the default value of \\fIarg\\fR\ninto variable \\fIvarname\\fR.\n.TP\n\\fBinfo exists \\fIvarName\\fR\nReturns \\fB1\\fR if the variable named \\fIvarName\\fR exists in the\ncurrent context (either as a global or local variable), returns \\fB0\\fR\notherwise.\n.TP\n\\fBinfo globals \\fR?\\fIpattern\\fR?\nIf \\fIpattern\\fR isn't specified, returns a list of all the names\nof currently-defined global variables.\nIf \\fIpattern\\fR is specified, only those names matching \\fIpattern\\fR\nare returned.  Matching is determined using the same rules as for\n\\fBstring match\\fR.\n.TP\n\\fBinfo level\\fR ?\\fInumber\\fR?\nIf \\fInumber\\fR is not specified, this command returns a number\ngiving the stack level of the invoking procedure, or 0 if the\ncommand is invoked at top-level.  If \\fInumber\\fR is specified,\nthen the result is a list consisting of the name and arguments for the\nprocedure call at level \\fInumber\\fR on the stack.  If \\fInumber\\fR\nis positive then it selects a particular stack level (1 refers\nto the top-most active procedure, 2 to the procedure it called, and\nso on); otherwise it gives a level relative to the current level\n(0 refers to the current procedure, -1 to its caller, and so on).\nSee the \\fBuplevel\\fR command for more information on what stack\nlevels mean.\n.TP\n\\fBinfo library\\fR\n.VS\nReturns the name of the library directory in which standard Tcl\nscripts are stored.\nThe default value for the library is compiled into Tcl, but it\n.VS\nmay be overridden by setting the TCL_LIBRARY environment variable.\nIf there is no TCL_LIBRARY variable and no compiled-in value then\nand error is generated.\n.VE\nSee the \\fBlibrary\\fR manual entry for details of the facilities\nprovided by the Tcl script library.\nNormally each application will have its own application-specific\nscript library in addition to the Tcl script library;  I suggest that\neach application set a global variable with a name like\n.VS\n\\fB$\\fIapp\\fB_library\\fR (where \\fIapp\\fR is the application's name)\n.VE\nto hold the location of that application's library directory.\n.VE\n.TP\n\\fBinfo locals \\fR?\\fIpattern\\fR?\nIf \\fIpattern\\fR isn't specified, returns a list of all the names\nof currently-defined local variables, including arguments to the\ncurrent procedure, if any.\n.VS\nVariables defined with the \\fBglobal\\fR and \\fBupvar\\fR commands\nwill not be returned.\n.VE\nIf \\fIpattern\\fR is specified, only those names matching \\fIpattern\\fR\nare returned.  Matching is determined using the same rules as for\n\\fBstring match\\fR.\n.TP\n\\fBinfo procs \\fR?\\fIpattern\\fR?\nIf \\fIpattern\\fR isn't specified, returns a list of all the\nnames of Tcl command procedures.\nIf \\fIpattern\\fR is specified, only those names matching \\fIpattern\\fR\nare returned.  Matching is determined using the same rules as for\n\\fBstring match\\fR.\n.TP\n\\fBinfo script\\fR\n.VS\nIf a Tcl script file is currently being evaluated (i.e. there is a\ncall to \\fBTcl_EvalFile\\fR active or there is an active invocation\nof the \\fBsource\\fR command), then this command returns the name\nof the innermost file being processed.  Otherwise the command returns an\nempty string.\n.VE\n.TP\n\\fBinfo tclversion\\fR\nReturns the version number for this version of Tcl in the form \\fIx.y\\fR,\nwhere changes to \\fIx\\fR represent major changes with probable\nincompatibilities and changes to \\fIy\\fR represent small enhancements and\nbug fixes that retain backward compatibility.\n.TP\n\\fBinfo vars\\fR ?\\fIpattern\\fR?\nIf \\fIpattern\\fR isn't specified,\nreturns a list of all the names of currently-visible variables, including\nboth locals and currently-visible globals.\nIf \\fIpattern\\fR is specified, only those names matching \\fIpattern\\fR\nare returned.  Matching is determined using the same rules as for\n\\fBstring match\\fR.\n.RE\n.TP\n\\fBjoin \\fIlist \\fR?\\fIjoinString\\fR?\n.VS\nThe \\fIlist\\fR argument must be a valid Tcl list.\nThis command returns the string\nformed by joining all of the elements of \\fIlist\\fR together with\n\\fIjoinString\\fR separating each adjacent pair of elements.\nThe \\fIjoinString\\fR argument defaults to a space character.\n.VE\n.TP\n\\fBlappend \\fIvarName value \\fR?\\fIvalue value ...\\fR?\n.VS\nTreat the variable given by \\fIvarName\\fR as a list and append\neach of the \\fIvalue\\fR arguments to that list as a separate\nelement, with spaces between elements.\nIf \\fIvarName\\fR doesn't exist, it is created as a list with elements\ngiven by the \\fIvalue\\fR arguments.\n\\fBLappend\\fR is similar to \\fBappend\\fR except that the \\fIvalue\\fRs\nare appended as list elements rather than raw text.\nThis command provides a relatively efficient way to build up\nlarge lists.  For example, ``\\fBlappend a $b\\fR'' is much\nmore efficient than ``\\fBset a [concat $a [list $b]]\\fR'' when\n\\fB$a\\fR is long.\n.TP\n\\fBlindex \\fIlist index\\fR\nTreats \\fIlist\\fR as a Tcl list and returns the \\fIindex\\fR'th element\nfrom it (0 refers to the first element of the list).\nIn extracting the element, \\fIlindex\\fR observes the same rules\nconcerning braces and quotes and backslashes as the Tcl command\ninterpreter; however, variable\nsubstitution and command substitution do not occur.\nIf \\fIindex\\fR is negative or greater than or equal to the number\nof elements in \\fIvalue\\fR, then an empty\nstring is returned.\n.TP\n\\fBlinsert \\fIlist index element \\fR?\\fIelement element ...\\fR?\nThis command produces a new list from \\fIlist\\fR by inserting all\nof the \\fIelement\\fR arguments just before the \\fIindex\\fRth\nelement of \\fIlist\\fR.  Each \\fIelement\\fR argument will become\na separate element of the new list.  If \\fIindex\\fR is less than\nor equal to zero, then the new elements are inserted at the\nbeginning of the list.  If \\fIindex\\fR is greater than or equal\nto the number of elements in the list, then the new elements are\nappended to the list.\n.VE\n.TP\n\\fBlist \\fIarg \\fR?\\fIarg ...\\fR?\nThis command returns a list comprised of all the \\fIarg\\fRs.  Braces\nand backslashes get added as necessary, so that the \\fBindex\\fR command\nmay be used on the result to re-extract the original arguments, and also\nso that \\fBeval\\fR may be used to execute the resulting list, with\n\\fIarg1\\fR comprising the command's name and the other \\fIarg\\fRs comprising\nits arguments.  \\fBList\\fR produces slightly different results than\n\\fBconcat\\fR:  \\fBconcat\\fR removes one level of grouping before forming\nthe list, while \\fBlist\\fR works directly from the original arguments.\nFor example, the command\n.RS\n.DS\n\\fBlist a b {c d e} {f {g h}}\n.DE\nwill return\n.DS\n\\fBa b {c d e} {f {g h}}\n.DE\nwhile \\fBconcat\\fR with the same arguments will return\n.DS\n\\fBa b c d e f {g h}\\fR\n.DE\n.RE\n.br\n.VS\n.TP\n\\fBllength \\fIlist\\fR\nTreats \\fIlist\\fR as a list and returns a decimal string giving\nthe number of elements in it.\n.TP\n\\fBlrange \\fIlist first last\n\\fIList\\fR must be a valid Tcl list.  This command will\nreturn a new list consisting of elements\n\\fIfirst\\fR through \\fIlast\\fR, inclusive.\n\\fILast\\fR may be \\fBend\\fR (or any\nabbreviation of it) to refer to the last element of the list.\nIf \\fIfirst\\fR is less than zero, it is treated as if it were zero.\nIf \\fIlast\\fR is greater than or equal to the number of elements\nin the list, then it is treated as if it were \\fBend\\fR.\nIf \\fIfirst\\fR is greater than \\fIlast\\fR then an empty string\nis returned.\nNote: ``\\fBlrange \\fIlist first first\\fR'' does not always produce the\nsame result as ``\\fBlindex \\fIlist first\\fR'' (although it often does\nfor simple fields that aren't enclosed in braces); it does, however,\nproduce exactly the same results as ``\\fBlist [lindex \\fIlist first\\fB]\\fR''\n.TP\n\\fBlreplace \\fIlist first last \\fR?\\fIelement element ...\\fR?\nReturns a new list formed by replacing one or more elements of\n\\fIlist\\fR with the \\fIelement\\fR arguments.\n\\fIFirst\\fR gives the index in \\fIlist\\fR of the first element\nto be replaced.\nIf \\fIfirst\\fR is less than zero then it refers to the first\nelement of \\fIlist\\fR;  the element indicated by \\fIfirst\\fR\nmust exist in the list.\n\\fILast\\fR gives the index in \\fIlist\\fR of the last element\nto be replaced;  it must be greater than or equal to \\fIfirst\\fR.\n\\fILast\\fR may be \\fBend\\fR (or any abbreviation of it) to indicate\nthat all elements between \\fIfirst\\fR and the end of the list should\nbe replaced.\nThe \\fIelement\\fR arguments specify zero or more new arguments to\nbe added to the list in place of those that were deleted.\nEach \\fIelement\\fR argument will become a separate element of\nthe list.\nIf no \\fIelement\\fR arguments are specified, then the elements\nbetween \\fIfirst\\fR and \\fIlast\\fR are simply deleted.\n.TP\n\\fBlsearch \\fIlist pattern\\fR\nSearch the elements of \\fIlist\\fR to see if one of them matches\n\\fIpattern\\fR.\nIf so, the command returns the index of the first matching\nelement.\nIf not, the command returns \\fB\\-1\\fR.\nPattern matching is done in the same way as for the \\fBstring match\\fR\ncommand.\n.TP\n\\fBlsort \\fIlist\\fR\nSort the elements of \\fIlist\\fR, returning a new list in sorted\norder.\nASCII sorting is used, with the result in increasing order.\n.VE\n.TP\n\\fBopen \\fIfileName\\fR ?\\fIaccess\\fR?\n.VS\nOpens a file and returns an identifier\nthat may be used in future invocations\nof commands like \\fBread\\fR, \\fBputs\\fR, and \\fBclose\\fR.\n\\fIFileName\\fR gives the name of the file to open; if it starts with\na tilde then tilde substitution is performed as described for\n\\fBTcl_TildeSubst\\fR.\nIf the first character of \\fIfileName\\fR is ``|'' then the\nremaining characters of \\fIfileName\\fR are treated as a command\npipeline to invoke, in the same style as for \\fBexec\\fR.\nIn this case, the identifier returned by \\fBopen\\fR may be used\nto write to the command's input pipe or read from its output pipe.\nThe \\fIaccess\\fR argument indicates the way in which the file\n(or command pipeline) is to be accessed.\nIt may have any of the following values:\n.RS\n.TP\n\\fBr\\fR\nOpen the file for reading only; the file must already exist.\n.TP\n\\fBr+\\fR\nOpen the file for both reading and writing; the file must\nalready exist.\n.TP\n\\fBw\\fR\nOpen the file for writing only.  Truncate it if it exists.  If it doesn't\nexist, create a new file.\n.TP\n\\fBw+\\fR\nOpen the file for reading and writing.  Truncate it if it exists.\nIf it doesn't exist, create a new file.\n.TP\n\\fBa\\fR\nOpen the file for writing only.  The file must already exist, and the file\nis positioned so that new data is appended to the file.\n.TP\n\\fBa+\\fR\nOpen the file for reading and writing.  If the file doesn't exist,\ncreate a new empty file.\nSet the initial access position  to the end of the file.\n.PP\n\\fIAccess\\fR defaults to \\fBr\\fR.\nIf a file is opened for both reading and writing, then \\fBseek\\fR\nmust be invoked between a read and a write, or vice versa (this\nrestriction does not apply to command pipelines opened with \\fBopen\\fR).\nWhen \\fIfileName\\fR specifies a command pipeline and a write-only access\nis used, then standard output from the pipeline is directed to the\ncurrent standard output unless overridden by the command.\nWhen \\fIfileName\\fR specifies a command pipeline and a read-only access\nis used, then standard input from the pipeline is taken from the\ncurrent standard input unless overridden by the command.\n.RE\n.VE\n.TP\n\\fBproc \\fIname args body\\fR\nThe \\fBproc\\fR command creates a new Tcl command procedure,\n\\fIname\\fR, replacing\nany existing command there may have been by that name.  Whenever the\nnew command is invoked, the contents of \\fIbody\\fR will be executed\nby the Tcl interpreter.  \\fIArgs\\fR specifies the formal arguments to the\nprocedure.  It consists of a list, possibly empty, each of whose\nelements specifies\none argument.  Each argument specifier is also a list with either\none or two fields.  If there is only a single field in the specifier,\nthen it is the name of the argument; if there are two fields, then\nthe first is the argument name and the second is its default value.\nbraces and backslashes may be used in the usual way to specify\ncomplex default values.\n.IP\nWhen \\fIname\\fR is invoked, a local variable\nwill be created for each of the formal arguments to the procedure; its\nvalue will be the value of corresponding argument in the invoking command\nor the argument's default value.\nArguments with default values need not be\nspecified in a procedure invocation.  However, there must be enough\nactual arguments for all the\nformal arguments that don't have defaults, and there must not be any extra\nactual arguments.  There is one special case to permit procedures with\nvariable numbers of arguments.  If the last formal argument has the name\n\\fBargs\\fR, then a call to the procedure may contain more actual arguments\nthan the procedure has formals.  In this case, all of the actual arguments\nstarting at the one that would be assigned to \\fBargs\\fR are combined into\na list (as if the \\fBlist\\fR command had been used); this combined value\nis assigned to the local variable \\fBargs\\fR.\n.IP\nWhen \\fIbody\\fR is being executed, variable names normally refer to\nlocal variables, which are created automatically when referenced and\ndeleted when the procedure returns.  One local variable is automatically\ncreated for each of the procedure's arguments.\nGlobal variables can only be accessed by invoking\nthe \\fBglobal\\fR command.\n.IP\nThe \\fBproc\\fR command returns the null string.  When a procedure is\ninvoked, the procedure's return value is the value specified in a\n\\fBreturn\\fR command.  If the procedure doesn't execute an explicit\n\\fBreturn\\fR, then its return value is the value of the last command\nexecuted in the procedure's body.\nIf an error occurs while executing the procedure\nbody, then the procedure-as-a-whole will return that same error.\n.TP\n\\fBputs \\fR?\\fB\\-nonewline\\fR? ?\\fIfileId\\fR? \\fIstring\\fR\n.VS\nWrites the characters given by \\fIstring\\fR to the file given\nby \\fIfileId\\fR.\n\\fIFileId\\fR must have been the return\nvalue from a previous call to \\fBopen\\fR, or it may be\n\\fBstdout\\fR or \\fBstderr\\fR to refer to one of the standard I/O\nchannels; it must refer to a file that was opened for\nwriting.\nIf no \\fIfileId\\fR is specified then it defaults to \\fBstdout\\fR.\n\\fBPuts\\fR normally outputs a newline character after \\fIstring\\fR,\n.VS\nbut this feature may be suppressed by specifying the \\fB\\-nonewline\\fR\nswitch.\n.VE\nOutput to files is buffered internally by Tcl; the \\fBflush\\fR\ncommand may be used to force buffered characters to be output.\n.TP\n\\fBpwd\\fR\n.br\nReturns the path name of the current working directory.\n.TP\n\\fBread \\fR?\\fB\\-nonewline\\fR? \\fIfileId\\fR\n.VS\n.TP\n\\fBread \\fIfileId numBytes\\fR\nIn the first form, all of the remaining bytes are read from the file\ngiven by \\fIfileId\\fR; they are returned as the result of the command.\nIf the \\fB\\-nonewline\\fR switch is specified then the last\ncharacter of the file is discarded if it is a newline.\n.VE\nIn the second form, the extra argument specifies how many bytes to read;\nexactly this many bytes will be read and returned, unless there are fewer than\n\\fInumBytes\\fR bytes left in the file; in this case, all the remaining\nbytes are returned.\n\\fIFileId\\fR must be \\fBstdin\\fR or the return\nvalue from a previous call to \\fBopen\\fR; it must\nrefer to a file that was opened for reading.\n.TP\n\\fBregexp \\fR?\\fB\\-indices\\fR? \\fR?\\fB\\-nocase\\fR? \\fIexp string \\fR?\\fImatchVar\\fR? ?\\fIsubMatchVar subMatchVar ...\\fR?\nDetermines whether the regular expression \\fIexp\\fR matches part or\nall of \\fIstring\\fR and returns 1 if it does, 0 if it doesn't.\nSee REGULAR EXPRESSIONS above for complete information on the\nsyntax of \\fIexp\\fR and how it is matched against \\fIstring\\fR.\n.RS\n.LP\nIf the \\fB\\-nocase\\fR switch is specified then upper-case\ncharacters in \\fIstring\\fR\nare treated as lower case during the matching process.\nThe \\fB\\-nocase\\fR switch must be specified before \\fIexp\\fR and\nmay not be abbreviated.\n.LP\nIf additional arguments are specified after \\fIstring\\fR then they\nare treated as the names of variables to use to return\ninformation about which part(s) of \\fIstring\\fR matched \\fIexp\\fR.\n\\fIMatchVar\\fR will be set to the range of \\fIstring\\fR that\nmatched all of \\fIexp\\fR.  The first \\fIsubMatchVar\\fR will contain\nthe characters in \\fIstring\\fR that matched the leftmost parenthesized\nsubexpression within \\fIexp\\fR, the next \\fIsubMatchVar\\fR will\ncontain the characters that matched the next parenthesized\nsubexpression to the right in \\fIexp\\fR, and so on.\n.LP\nNormally, \\fImatchVar\\fR and the \\fIsubMatchVar\\fRs are set to hold\nthe matching characters from \\fBstring\\fR.\nHowever, if the \\fB\\-indices\\fR switch is specified then each variable\nwill contain a list of two decimal strings giving the indices\nin \\fIstring\\fR of the first and last characters in the matching\nrange of characters.\nThe \\fB\\-indices\\fR switch must be specified before the \\fIexp\\fR\nargument and may not be abbreviated.\n.LP\nIf there are more \\fIsubMatchVar\\fR's than parenthesized\nsubexpressions within \\fIexp\\fR, or if a particular subexpression\nin \\fIexp\\fR doesn't match the string (e.g. because it was in a\nportion of the expression that wasn't matched), then the corresponding\n\\fIsubMatchVar\\fR will be set to ``\\fB\\-1 \\-1\\fR'' if \\fB\\-indices\\fR\nhas been specified or to an empty string otherwise.\n.RE\n.TP\n\\fBregsub \\fR?\\fB\\-all\\fR? ?\\fB\\-nocase\\fR? \\fIexp string subSpec varName\\fR\nThis command matches the regular expression \\fIexp\\fR against\n\\fIstring\\fR using the rules described in REGULAR EXPRESSIONS\nabove.\nIf there is no match, then the command returns 0 and does nothing\nelse.\nIf there is a match, then the command returns 1 and also copies\n\\fIstring\\fR to the variable whose name is given by \\fIvarName\\fR.\nWhen copying \\fIstring\\fR, the portion of \\fIstring\\fR that\nmatched \\fIexp\\fR is replaced with \\fIsubSpec\\fR.\nIf \\fIsubSpec\\fR contains a ``&'' or ``\\e0'', then it is replaced\nin the substitution with the portion of \\fIstring\\fR that\nmatched \\fIexp\\fR.\nIf \\fIsubSpec\\fR contains a ``\\e\\fIn\\fR'', where \\fIn\\fR is a digit\nbetween 1 and 9, then it is replaced in the substitution with\nthe portion of \\fIstring\\fR that matched the \\fIn\\fR-th\nparenthesized subexpression of \\fIexp\\fR.\nAdditional backslashes may be used in \\fIsubSpec\\fR to prevent special\ninterpretation of ``&'' or ``\\e0'' or ``\\e\\fIn\\fR'' or\nbackslash.\nThe use of backslashes in \\fIsubSpec\\fR tends to interact badly\nwith the Tcl parser's use of backslashes, so it's generally\nsafest to enclose \\fIsubSpec\\fR in braces if it includes\nbackslashes.\nIf the \\fB\\-all\\fR argument is specified, then all ranges in\n\\fIstring\\fR that match \\fIexp\\fR are found and substitution is\nperformed for each of these ranges;  otherwise only the first\nmatching range is found and substituted.\nIf \\fB\\-all\\fR is specified, then ``&'' and ``\\e\\fIn\\fR''\nsequences are handled for each substitution using the information\nfrom the corresponding match.\nIf the \\fB\\-nocase\\fR argument is specified, then upper-case\ncharacters in \\fIstring\\fR are converted to lower-case before\nmatching against \\fIexp\\fR;  however, substitutions specified\nby \\fIsubSpec\\fR use the original unconverted form of \\fIstring\\fR.\nThe \\fB\\-all\\fR and \\fB\\-nocase\\fR arguments must be specified\nexactly:  no abbreviations are permitted.\n.VE\n.TP\n\\fBrename \\fIoldName newName\\fR\nRename the command that used to be called \\fIoldName\\fR so that it\nis now called \\fInewName\\fR.  If \\fInewName\\fR is an empty string\n(e.g. {}) then \\fIoldName\\fR is deleted.  The \\fBrename\\fR command\nreturns an empty string as result.\n.TP\n\\fBreturn \\fR?\\fIvalue\\fR?\nReturn immediately from the current procedure\n(or top-level command or \\fBsource\\fR command),\nwith \\fIvalue\\fR as the return value.  If \\fIvalue\\fR is not specified,\nan empty string will be returned as result.\n.TP\n\\fBscan \\fIstring format varname1 \\fR?\\fIvarname2 ...\\fR?\nThis command parses fields from an input string in the same fashion\nas the C \\fBsscanf\\fR procedure.  \\fIString\\fR gives the input to\nbe parsed and \\fIformat\\fR indicates how to parse it, using \\fB%\\fR\nfields as in \\fBsscanf\\fR.  All of the \\fBsscanf\\fR options are valid;\nsee the \\fBsscanf\\fR man page for details.  Each \\fIvarname\\fR gives\nthe name of a variable; when a field is scanned from \\fIstring\\fR,\nthe result is converted back into a string and assigned to the\ncorresponding \\fIvarname\\fR.  The only unusual conversion is for\n\\fB%c\\fR.  For \\fB%c\\fR conversions a single character value is\nconverted to a decimal string, which is then assigned to the\ncorresponding \\fIvarname\\fR;\n.VS\nno field width may be specified for this conversion.\n.TP\n\\fBseek \\fIfileId offset \\fR?\\fIorigin\\fR?\nChange the current access position for \\fIfileId\\fR.\nThe \\fIoffset\\fR and \\fIorigin\\fR arguments specify the position at\nwhich the next read or write will occur for \\fIfileId\\fR.\n\\fIOffset\\fR must be a number (which may be negative) and \\fIorigin\\fR\nmust be one of the following:\n.RS\n.TP\n\\fBstart\\fR\nThe new access position will be \\fIoffset\\fR bytes from the start\nof the file.\n.TP\n\\fBcurrent\\fR\nThe new access position will be \\fIoffset\\fR bytes from the current\naccess position; a negative \\fIoffset\\fR moves the access position\nbackwards in the file.\n.TP\n\\fBend\\fR\nThe new access position will be \\fIoffset\\fR bytes from the end of\nthe file.  A negative \\fIoffset\\fR places the access position before\nthe end-of-file, and a positive \\fIoffset\\fR places the access position\nafter the end-of-file.\n.LP\nThe \\fIorigin\\fR argument defaults to \\fBstart\\fR.\n\\fIFileId\\fR must have been the return\nvalue from a previous call to \\fBopen\\fR, or it may be \\fBstdin\\fR,\n\\fBstdout\\fR, or \\fBstderr\\fR to refer to one of the standard I/O\nchannels.\nThis command returns an empty string.\n.RE\n.VE\n.TP\n\\fBset \\fIvarname \\fR?\\fIvalue\\fR?\nReturns the value of variable \\fIvarname\\fR.\nIf \\fIvalue\\fR is specified, then set\nthe value of \\fIvarname\\fR to \\fIvalue\\fR, creating a new variable\nif one doesn't already exist, and return its value.\n.VS\nIf \\fIvarName\\fR contains an open parenthesis and ends with a\nclose parenthesis, then it refers to an array element:  the characters\nbefore the open parenthesis are the name of the array, and the characters\nbetween the parentheses are the index within the array.\nOtherwise \\fIvarName\\fR refers to a scalar variable.\n.VE\nIf no procedure is active, then \\fIvarname\\fR refers to a global\nvariable.\nIf a procedure is active, then \\fIvarname\\fR refers to a parameter\nor local variable of the procedure, unless the \\fIglobal\\fR command\nhas been invoked to declare \\fIvarname\\fR to be global.\n.TP\n\\fBsource \\fIfileName\\fR\nRead file \\fIfileName\\fR and pass the contents to the Tcl interpreter\nas a sequence of commands to execute in the normal fashion.  The return\nvalue of \\fBsource\\fR is the return value of the last command executed\nfrom the file.  If an error occurs in executing the contents of the\nfile, then the \\fBsource\\fR command will return that error.\nIf a \\fBreturn\\fR command is invoked from within the file, the remainder of\nthe file will be skipped and the \\fBsource\\fR command will return\nnormally with the result from the \\fBreturn\\fR command.\nIf \\fIfileName\\fR starts with a tilde, then it is tilde-substituted\nas described in the \\fBTcl_TildeSubst\\fR manual entry.\n.TP\n\\fBsplit \\fIstring \\fR?\\fIsplitChars\\fR?\nReturns a list created by splitting \\fIstring\\fR at each character\nthat is in the \\fIsplitChars\\fR argument.\nEach element of the result list will consist of the\ncharacters from \\fIstring\\fR between instances of the\ncharacters in \\fIsplitChars\\fR.\nEmpty list elements will be generated if \\fIstring\\fR contains\nadjacent characters in \\fIsplitChars\\fR, or if the first or last\ncharacter of \\fIstring\\fR is in \\fIsplitChars\\fR.\nIf \\fIsplitChars\\fR is an empty string then each character of\n\\fIstring\\fR becomes a separate element of the result list.\n\\fISplitChars\\fR defaults to the standard white-space characters.\nFor example,\n.RS\n.DS\n\\fBsplit \"comp.unix.misc\" .\\fR\n.DE\nreturns \\fB\"comp unix misc\"\\fR and\n.DS\n\\fBsplit \"Hello world\" {}\\fR\n.DE\nreturns \\fB\"H e l l o { } w o r l d\"\\fR.\n.VE\n.RE\n.TP\n\\fBstring \\fIoption arg \\fR?\\fIarg ...?\\fR\nPerform one of several string operations, depending on \\fIoption\\fR.\nThe legal \\fIoption\\fRs (which may be abbreviated) are:\n.RS\n.TP\n\\fBstring compare \\fIstring1 string2\\fR\nPerform a character-by-character comparison of strings \\fIstring1\\fR and\n\\fIstring2\\fR in the same way as the C \\fBstrcmp\\fR procedure.  Return\n-1, 0, or 1, depending on whether \\fIstring1\\fR is lexicographically\nless than, equal to, or greater than \\fIstring2\\fR.\n.TP\n\\fBstring first \\fIstring1 string2\\fR\nSearch \\fIstring2\\fR for a sequence of characters that exactly match\nthe characters in \\fIstring1\\fR.  If found, return the index of the\nfirst character in the first such match within \\fIstring2\\fR.  If not\nfound, return -1.\n.br\n.VS\n.TP\n\\fBstring index \\fIstring charIndex\\fR\nReturns the \\fIcharIndex\\fR'th character of the \\fIstring\\fR\nargument.  A \\fIcharIndex\\fR of 0 corresponds to the first\ncharacter of the string.\nIf \\fIcharIndex\\fR is less than 0 or greater than\nor equal to the length of the string then an empty string is\nreturned.\n.VE\n.TP\n\\fBstring last \\fIstring1 string2\\fR\nSearch \\fIstring2\\fR for a sequence of characters that exactly match\nthe characters in \\fIstring1\\fR.  If found, return the index of the\nfirst character in the last such match within \\fIstring2\\fR.  If there\nis no match, then return \\-1.\n.br\n.VS\n.TP\n\\fBstring length \\fIstring\\fR\nReturns a decimal string giving the number of characters in \\fIstring\\fR.\n.VE\n.TP\n\\fBstring match \\fIpattern\\fR \\fIstring\\fR\nSee if \\fIpattern\\fR matches \\fIstring\\fR; return 1 if it does, 0\nif it doesn't.  Matching is done in a fashion similar to that\nused by the C-shell.  For the two strings to match, their contents\nmust be identical except that the following special sequences\nmay appear in \\fIpattern\\fR:\n.RS\n.IP \\fB*\\fR 10\nMatches any sequence of characters in \\fIstring\\fR,\nincluding a null string.\n.IP \\fB?\\fR 10\nMatches any single character in \\fIstring\\fR.\n.IP \\fB[\\fIchars\\fB]\\fR 10\nMatches any character in the set given by \\fIchars\\fR.  If a sequence\nof the form\n\\fIx\\fB\\-\\fIy\\fR appears in \\fIchars\\fR, then any character\nbetween \\fIx\\fR and \\fIy\\fR, inclusive, will match.\n.IP \\fB\\e\\fIx\\fR 10\nMatches the single character \\fIx\\fR.  This provides a way of\navoiding the special interpretation of the characters\n\\fB*?[]\\e\\fR in \\fIpattern\\fR.\n.RE\n.br\n.VS\n.TP\n\\fBstring range \\fIstring first last\\fR\nReturns a range of consecutive characters from \\fIstring\\fR, starting\nwith the character whose index is \\fIfirst\\fR and ending with the\ncharacter whose index is \\fIlast\\fR.  An index of 0 refers to the\nfirst character of the string.  \\fILast\\fR may be \\fBend\\fR (or any\nabbreviation of it) to refer to the last character of the string.\nIf \\fIfirst\\fR is less than zero then it is treated as if it were zero, and\nif \\fIlast\\fR is greater than or equal to the length of the string then\nit is treated as if it were \\fBend\\fR.  If \\fIfirst\\fR is greater than\n\\fIlast\\fR then an empty string is returned.\n.TP\n\\fBstring tolower \\fIstring\\fR\nReturns a value equal to \\fIstring\\fR except that all upper case\nletters have been converted to lower case.\n.TP\n\\fBstring toupper \\fIstring\\fR\nReturns a value equal to \\fIstring\\fR except that all lower case\nletters have been converted to upper case.\n.TP\n\\fBstring trim \\fIstring\\fR ?\\fIchars\\fR?\nReturns a value equal to \\fIstring\\fR except that any leading\nor trailing characters from the set given by \\fIchars\\fR are\nremoved.\nIf \\fIchars\\fR is not specified then white space is removed\n(spaces, tabs, newlines, and carriage returns).\n.TP\n\\fBstring trimleft \\fIstring\\fR ?\\fIchars\\fR?\nReturns a value equal to \\fIstring\\fR except that any\nleading characters from the set given by \\fIchars\\fR are\nremoved.\nIf \\fIchars\\fR is not specified then white space is removed\n(spaces, tabs, newlines, and carriage returns).\n.TP\n\\fBstring trimright \\fIstring\\fR ?\\fIchars\\fR?\nReturns a value equal to \\fIstring\\fR except that any\ntrailing characters from the set given by \\fIchars\\fR are\nremoved.\nIf \\fIchars\\fR is not specified then white space is removed\n(spaces, tabs, newlines, and carriage returns).\n.RE\n.TP\n\\fBtell \\fIfileId\\fR\nReturns a decimal string giving the current access position in\n\\fIfileId\\fR.\n\\fIFileId\\fR must have been the return\nvalue from a previous call to \\fBopen\\fR, or it may be \\fBstdin\\fR,\n\\fBstdout\\fR, or \\fBstderr\\fR to refer to one of the standard I/O\nchannels.\n.VE\n.TP\n\\fBtime \\fIcommand\\fR ?\\fIcount\\fR?\nThis command will call the Tcl interpreter \\fIcount\\fR\ntimes to execute \\fIcommand\\fR (or once if \\fIcount\\fR isn't\nspecified).  It will then return a string of the form\n.RS\n.DS\n\\fB503 microseconds per iteration\\fR\n.DE\nwhich indicates the average amount of time required per iteration,\nin microseconds.\nTime is measured in elapsed time, not CPU time.\n.RE\n.TP\n\\fBtrace \\fIoption\\fR ?\\fIarg arg ...\\fR?\n.VS\nCause Tcl commands to be executed whenever certain operations are\ninvoked.  At present, only variable tracing is implemented. The\nlegal \\fIoption\\fR's (which may be abbreviated) are:\n.RS\n.TP\n\\fBtrace variable \\fIname ops command\\fR\nArrange for \\fIcommand\\fR to be executed whenever variable \\fIname\\fR\nis accessed in one of the ways given by \\fIops\\fR.  \\fIName\\fR may\nrefer to a normal variable, an element of an array, or to an array\nas a whole (i.e. \\fIname\\fR may be just the name of an array, with no\nparenthesized index).  If \\fIname\\fR refers to a whole array, then\n\\fIcommand\\fR is invoked whenever any element of the array is\nmanipulated.\n.RS\n.LP\n\\fIOps\\fR indicates which operations are of interest, and consists of\none or more of the following letters:\n.RS\n.TP\n\\fBr\\fR\nInvoke \\fIcommand\\fR whenever the variable is read.\n.TP\n\\fBw\\fR\nInvoke \\fIcommand\\fR whenever the variable is written.\n.TP\n\\fBu\\fR\nInvoke \\fIcommand\\fR whenever the variable is unset.  Variables\ncan be unset explicitly with the \\fBunset\\fR command, or\nimplicitly when procedures return (all of their local variables\nare unset).  Variables are also unset when interpreters are\ndeleted, but traces will not be invoked because there is no\ninterpreter in which to execute them.\n.RE\n.LP\nWhen the trace triggers, three arguments are appended to\n\\fIcommand\\fR so that the actual command is as follows:\n.DS C\n\\fIcommand name1 name2 op\\fR\n.DE\n\\fIName1\\fR and \\fIname2\\fR give the name(s) for the variable\nbeing accessed:  if the variable is a scalar then \\fIname1\\fR\ngives the variable's name and \\fIname2\\fR is an empty string;\nif the variable is an array element then \\fIname1\\fR gives the\nname of the array and name2 gives the index into the array;\nif an entire array is being deleted and the trace was registered\non the overall array, rather than a single element, then \\fIname1\\fR\ngives the array name and \\fIname2\\fR is an empty string.\n\\fIOp\\fR indicates what operation is being performed on the\nvariable, and is one of \\fBr\\fR, \\fBw\\fR, or \\fBu\\fR as\ndefined above.\n.LP\n\\fICommand\\fR executes in the same context as the code that invoked\nthe traced operation:  if the variable was accessed as part of a\nTcl procedure, then \\fIcommand\\fR will have access to the same\nlocal variables as code in the procedure.  This context may be\ndifferent than the context in which the trace was created.\nIf \\fIcommand\\fR invokes a procedure (which it normally does) then\nthe procedure will have to use \\fBupvar\\fR or \\fBuplevel\\fR if it\nwishes to access the traced variable.\nNote also that \\fIname1\\fR may not necessarily be the same as the name\nused to set the trace on the variable;  differences can occur if\nthe access is made through a variable defined with the \\fBupvar\\fR\ncommand.\n.LP\nFor read and write traces, \\fIcommand\\fR can modify\nthe variable to affect the result of the traced operation.\nIf \\fIcommand\\fR modifies the value of a variable during a\nread or write trace, then the new value will be returned as the\nresult of the traced operation.\nThe return value from  \\fIcommand\\fR is ignored except that\nif it returns an error of any sort then the traced operation\nis aborted with an error message saying that the access was denied\n(this mechanism can be used to implement read-only variables, for\nexample).\nFor write traces, \\fIcommand\\fR is invoked after the variable's\nvalue has been changed; it can write a new value into the variable\nto override the original value specified in the write operation.\nTo implement read-only variables, \\fIcommand\\fR will have to restore\nthe old value of the variable.\n.LP\nWhile \\fIcommand\\fR is executing during a read or write trace, traces\non the variable are temporarily disabled.\nThis means that reads and writes invoked by\n\\fIcommand\\fR will occur directly, without invoking \\fIcommand\\fR\n(or any other traces) again.\n.LP\nWhen an unset trace is invoked, the variable has already been\ndeleted:  it will appear to be undefined with no traces.\nIf an unset occurs because of a procedure return, then the\ntrace will be invoked in the variable context of the procedure\nbeing returned to:  the stack frame of the returning procedure\nwill no longer exist.\nTraces are not disabled during unset traces, so if an unset trace\ncommand creates a new trace and accesses the variable, the\ntrace will be invoked.\n.LP\nIf there are multiple traces on a variable they are invoked\nin order of creation, most-recent first.\nIf one trace returns an error, then no further traces are\ninvoked for the variable.\nIf an array element has a trace set, and there is also a trace\nset on the array as a whole, the trace on the overall array\nis invoked before the one on the element.\n.LP\nOnce created, the trace remains in effect either until the\ntrace is removed with the \\fBtrace vdelete\\fR command described\nbelow, until the variable is unset, or until the interpreter\nis deleted.\nUnsetting an element of array will remove any traces on that\nelement, but will not remove traces on the overall array.\n.LP\nThis command returns an empty string.\n.RE\n.TP\n\\fBtrace vdelete \\fIname ops command\\fR\nIf there is a trace set on variable \\fIname\\fR with the\noperations and command given by \\fIops\\fR and \\fIcommand\\fR,\nthen the trace is removed, so that \\fIcommand\\fR will never\nagain be invoked.\nReturns an empty string.\n.TP\n\\fBtrace vinfo \\fIname\\fR\nReturns a list containing one element for each trace\ncurrently set on variable \\fIname\\fR.\nEach element of the list is itself a list containing two\nelements, which are the \\fIops\\fR and \\fIcommand\\fR associated\nwith the trace.\nIf \\fIname\\fR doesn't exist or doesn't have any traces set, then\nthe result of the command will be an empty string.\n.RE\n.TP\n\\fBunknown \\fIcmdName \\fR?\\fIarg arg ...\\fR?\nThis command doesn't actually exist as part of Tcl, but Tcl will\ninvoke it if it does exist.\nIf the Tcl interpreter encounters a command name for which there\nis not a defined command, then Tcl checks for the existence of\na command named \\fBunknown\\fR.\nIf there is no such command, then the interpeter returns an\nerror.\nIf the \\fBunknown\\fR command exists, then it is invoked with\narguments consisting of the fully-substituted name and arguments\nfor the original non-existent command.\nThe \\fBunknown\\fR command typically does things like searching\nthrough library directories for a command procedure with the name\n\\fIcmdName\\fR, or expanding abbreviated command names to full-length,\nor automatically executing unknown commands as UNIX sub-processes.\nIn some cases (such as expanding abbreviations) \\fBunknown\\fR will\nchange the original command slightly and then (re-)execute it.\nThe result of the \\fBunknown\\fR command is used as the result for\nthe original non-existent command.\n.TP\n\\fBunset \\fIname \\fR?\\fIname name ...\\fR?\nRemove one or more variables.\nEach \\fIname\\fR is a variable name, specified in any of the\nways acceptable to the \\fBset\\fR command.\nIf a \\fIname\\fR refers to an element of an array, then that\nelement is removed without affecting the rest of the array.\nIf a \\fIname\\fR consists of an array name with no parenthesized\nindex, then the entire array is deleted.\nThe \\fBunset\\fR command returns an empty string as result.\nAn error occurs if any of the variables doesn't exist.\n.VE\n.TP\n\\fBuplevel \\fR?\\fIlevel\\fR?\\fI command \\fR?\\fIcommand ...\\fR?\nAll of the \\fIcommand\\fR arguments are concatenated as if they had\nbeen passed to \\fBconcat\\fR; the result is then evaluated in the\nvariable context indicated by \\fIlevel\\fR.  \\fBUplevel\\fR returns\nthe result of that evaluation.  If \\fIlevel\\fR is an integer, then\nit gives a distance (up the procedure calling stack) to move before\nexecuting the command.  If \\fIlevel\\fR consists of \\fB#\\fR followed by\na number then the number gives an absolute level number.  If \\fIlevel\\fR\nis omitted then it defaults to \\fB1\\fR.  \\fILevel\\fR cannot be\ndefaulted if the first \\fIcommand\\fR argument starts with a digit or \\fB#\\fR.\nFor example, suppose that procedure \\fBa\\fR was invoked\nfrom top-level, and that it called \\fBb\\fR, and that \\fBb\\fR called \\fBc\\fR.\nSuppose that \\fBc\\fR invokes the \\fBuplevel\\fR command.  If \\fIlevel\\fR\nis \\fB1\\fR or \\fB#2\\fR  or omitted, then the command will be executed\nin the variable context of \\fBb\\fR.  If \\fIlevel\\fR is \\fB2\\fR or \\fB#1\\fR\nthen the command will be executed in the variable context of \\fBa\\fR.\nIf \\fIlevel\\fR is \\fB3\\fR or \\fB#0\\fR then the command will be executed\nat top-level (only global variables will be visible).\nThe \\fBuplevel\\fR command causes the invoking procedure to disappear\nfrom the procedure calling stack while the command is being executed.\nIn the above example, suppose \\fBc\\fR invokes the command\n.RS\n.DS\n\\fBuplevel 1 {set x 43; d}\n.DE\nwhere \\fBd\\fR is another Tcl procedure.  The \\fBset\\fR command will\nmodify the variable \\fBx\\fR in \\fBb\\fR's context, and \\fBd\\fR will execute\nat level 3, as if called from \\fBb\\fR.  If it in turn executes\nthe command\n.DS\n\\fBuplevel {set x 42}\n.DE\nthen the \\fBset\\fR command will modify the same variable \\fBx\\fR in \\fBb\\fR's\ncontext:  the procedure \\fBc\\fR does not appear to be on the call stack\nwhen \\fBd\\fR is executing.  The command ``\\fBinfo level\\fR'' may\nbe used to obtain the level of the current procedure.\n\\fBUplevel\\fR makes it possible to implement new control\nconstructs as Tcl procedures (for example, \\fBuplevel\\fR could\nbe used to implement the \\fBwhile\\fR construct as a Tcl procedure).\n.RE\n.TP\n\\fBupvar \\fR?\\fIlevel\\fR? \\fIotherVar myVar \\fR?\\fIotherVar myVar \\fR...?\n.VS\nThis command arranges for one or more local variables in the current\nprocedure to refer to variables in an enclosing procedure call or\nto global variables.\n\\fILevel\\fR may have any of the forms permitted for the \\fBuplevel\\fR\ncommand, and may be omitted if the first letter of the first \\fIotherVar\\fR\nisn't \\fB#\\fR or a digit (it defaults to \\fB1\\fR).\nFor each \\fIotherVar\\fR argument, \\fBupvar\\fR makes the variable\nby that name in the procedure frame given by \\fIlevel\\fR (or at\nglobal level, if \\fIlevel\\fR is \\fB#0\\fR) accessible\nin the current procedure by the name given in the corresponding\n\\fImyVar\\fR argument.\nThe variable named by \\fIotherVar\\fR need not exist at the time of the\ncall;  it will be created the first time \\fImyVar\\fR is referenced, just like\nan ordinary variable.\n\\fBUpvar\\fR may only be invoked from within procedures.\nNeither \\fIotherVar\\fR or \\fImyVar\\fR may refer to an element of an\narray.\n\\fBUpvar\\fR returns an empty string.\n.RS\n.LP\nThe \\fBupvar\\fR command simplifies the implementation of call-by-name\nprocedure calling and also makes it easier to build new control constructs\nas Tcl procedures.\nFor example, consider the following procedure:\n.DS\n.ta 1c 2c 3c\n\\fBproc add2 name {\n    upvar $name x\n    set x [expr $x+2]\n}\n.DE\n\\fBAdd2\\fR is invoked with an argument giving the name of a variable,\nand it adds two to the value of that variable.\nAlthough \\fBadd2\\fR could have been implemented using \\fBuplevel\\fR\ninstead of \\fBupvar\\fR, \\fBupvar\\fR makes it simpler for \\fBadd2\\fR\nto access the variable in the caller's procedure frame.\n.VE\n.RE\n.TP\n\\fBwhile \\fItest body\n.VS\nThe \\fIwhile\\fR command evaluates \\fItest\\fR as an expression\n(in the same way that \\fBexpr\\fR evaluates its argument).\nThe value of the expression must be numeric; if it is non-zero\nthen \\fIbody\\fR is executed by passing it to the Tcl interpreter.\nOnce \\fIbody\\fR has been executed then \\fItest\\fR is evaluated\nagain, and the process repeats until eventually \\fItest\\fR\nevaluates to a zero numeric value.  \\fBContinue\\fR\ncommands may be executed inside \\fIbody\\fR to terminate the current\niteration of the loop, and \\fBbreak\\fR\ncommands may be executed inside \\fIbody\\fR to cause immediate\ntermination of the \\fBwhile\\fR command.  The \\fBwhile\\fR command\nalways returns an empty string.\n.VE\n\n.SH \"BUILT-IN VARIABLES\"\n.PP\nThe following global variables are created and managed automatically\nby the Tcl library.  Except where noted below, these variables should\nnormally be treated as read-only by application-specific code and by users.\n.TP\n\\fBenv\\fR\n.br\n.VS\nThis variable is maintained by Tcl as an array\nwhose elements are the environment variables for the process.\nReading an element will return the value of the corresponding\nenvironment variable.\nSetting an element of the array will modify the corresponding\nenvironment variable or create a new one if it doesn't already\nexist.\nUnsetting an element of \\fBenv\\fR will remove the corresponding\nenvironment variable.\nChanges to the \\fBenv\\fR array will affect the environment\npassed to children by commands like \\fBexec\\fR.\nIf the entire \\fBenv\\fR array is unset then Tcl will stop\nmonitoring \\fBenv\\fR accesses and will not update environment\nvariables.\n.TP\n\\fBerrorCode\\fR\nAfter an error has occurred, this variable will be set to hold\nadditional information about the error in a form that is easy\nto process with programs.\n\\fBerrorCode\\fR consists of a Tcl list with one or more elements.\nThe first element of the list identifies a general class of\nerrors, and determines the format of the rest of the list.\nThe following formats for \\fBerrorCode\\fR are used by the\nTcl core; individual applications may define additional formats.\n.RS\n.TP\n\\fBCHILDKILLED\\fI pid sigName msg\\fR\nThis format is used when a child process has been killed because of\na signal.  The second element of \\fBerrorCode\\fR will be the\nprocess's identifier (in decimal).\nThe third element will be the symbolic name of the signal that caused\nthe process to terminate; it will be one of the names from the\ninclude file signal.h, such as \\fBSIGPIPE\\fR.\nThe fourth element will be a short human-readable message\ndescribing the signal, such as ``write on pipe with no readers''\nfor \\fBSIGPIPE\\fR.\n.TP\n\\fBCHILDSTATUS\\fI pid code\\fR\nThis format is used when a child process has exited with a non-zero\nexit status.  The second element of \\fBerrorCode\\fR will be the\nprocess's identifier (in decimal) and the third element will be the exit\ncode returned by the process (also in decimal).\n.TP\n\\fBCHILDSUSP\\fI pid sigName msg\\fR\nThis format is used when a child process has been suspended because\nof a signal.\nThe second element of \\fBerrorCode\\fR will be the process's identifier,\nin decimal.\nThe third element will be the symbolic name of the signal that caused\nthe process to suspend; this will be one of the names from the\ninclude file signal.h, such as \\fBSIGTTIN\\fR.\nThe fourth element will be a short human-readable message\ndescribing the signal, such as ``background tty read''\nfor \\fBSIGTTIN\\fR.\n.TP\n\\fBNONE\\fR\n.br\nThis format is used for errors where no additional information is\navailable for an error besides the message returned with the\nerror.  In these cases \\fBerrorCode\\fR will consist of a list\ncontaining a single element whose contents are \\fBNONE\\fR.\n.TP\n\\fBUNIX \\fIerrName msg\\fR\nIf the first element of \\fBerrorCode\\fR is \\fBUNIX\\fR, then\nthe error occurred during a UNIX kernel call.\nThe second element of the list will contain the symbolic name\nof the error that occurred, such as \\fBENOENT\\fR; this will\nbe one of the values defined in the include file errno.h.\nThe third element of the list will be a human-readable\nmessage corresponding to \\fIerrName\\fR, such as\n``no such file or directory'' for the \\fBENOENT\\fR case.\n.PP\nTo set \\fBerrorCode\\fR, applications should use library\nprocedures such as \\fBTcl_SetErrorCode\\fR and\n\\fBTcl_UnixError\\fR, or they may invoke the \\fBerror\\fR command.\nIf one of these methods hasn't been used, then the Tcl\ninterpreter will reset the variable to \\fBNONE\\fR after\nthe next error.\n.RE\n.VE\n.TP\n\\fBerrorInfo\\fR\nAfter an error has occurred, this string will contain one or more lines\nidentifying the Tcl commands and procedures that were being executed\nwhen the most recent error occurred.\nIts contents take the form of a stack trace showing the various\nnested Tcl commands that had been invoked at the time of the error.\n\n.SH AUTHOR\nJohn Ousterhout, University of California at Berkeley (ouster@sprite.berkeley.edu)\n.sp\nMany people have contributed to Tcl in various ways, but the following\npeople have made unusually large contributions:\n.sp\n.nf\nBill Carpenter\nPeter Da Silva\nMark Diekhans\nKarl Lehenbauer\nMary Ann May-Pumphrey\n"
  },
  {
    "path": "lib/libtcl/doc/TildeSubst.3",
    "content": "'\\\"\n'\\\" Copyright 1989 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/TildeSubst.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_TildeSubst tcl\n.BS\n.SH NAME\nTcl_TildeSubst \\- replace tilde with home directory in a file name\n.SH SYNOPSIS\n.nf\n\\fB#include <tcl.h>\\fR\n.sp\nchar *\n\\fBTcl_TildeSubst\\fR(\\fIinterp\\fR, \\fIname\\fR)\n.SH ARGUMENTS\n.AS Tcl_Interp *interp\n.AP Tcl_Interp *interp in\nInterpreter in which to report an error, if any.\n.AP char *name in\nFile name, which may start with a ``~''.\n.BE\n\n.SH DESCRIPTION\n.PP\nThis utility procedure does tilde substition.  If \\fIname\\fR doesn't\nstart with a ``~'' character, then the procedure returns \\fIname\\fR.\nIf \\fIname\\fR does start with a tilde, then \\fBTcl_TildeSubst\\fR\nreturns a new string identical to \\fIname\\fR except that the first\nelement of \\fIname\\fR is replaced with the location of the home\ndirectory for the given user.  The substitution is carried out in\nthe same way that it would be done by \\fIcsh\\fR.  If the tilde is\nfollowed immediately by a slash, then the \\fB$HOME\\fR environment\nvariable is substituted.  Otherwise the characters between the\ntilde and the next slash are taken as a user name, which is\nlooked up in the password file;  the user's home directory is\nretrieved from the password file and substituted.\n.PP\nThe string returned by \\fBTcl_TildeSubst\\fR is a static string\nbelonging to \\fBTcl_TildeSubst\\fR.  Its value will only persist\nuntil the next call to \\fBTcl_TildeSubst\\fR;  the caller should\nmake a copy of the result if it needs to live a long time.\n.PP\nIf an error occurs (e.g. because there was no user by the given\nname) then NULL is returned and an error message will be left\nat \\fIinterp->result\\fR.  It is assumed that \\fIinterp->result\\fR\nhas been initialized in the standard way when \\fBTcl_TildeSubst\\fR\nis invoked.\n\n.SH KEYWORDS\nfile name, home directory, tilde, user\n"
  },
  {
    "path": "lib/libtcl/doc/TraceVar.3",
    "content": "'\\\"\n'\\\" Copyright 1989 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/TraceVar.3,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\\\" \n.so man.macros\n.HS Tcl_TraceVar tcl\n.VS\n.BS\n.SH NAME\nTcl_TraceVar, Tcl_TraceVar2, Tcl_UntraceVar, Tcl_UntraceVar2, Tcl_VarTraceInfo, Tcl_VarTraceInfo2 \\- monitor accesses to a variable\n.SH SYNOPSIS\n.nf\n\\fB#include <tcl.h>\\fR\n.sp\nint\n\\fBTcl_TraceVar(\\fIinterp, varName, flags, proc, clientData\\fB)\\fR\n.sp\nint\n\\fBTcl_TraceVar2(\\fIinterp, name1, name2, flags, proc, clientData\\fB)\\fR\n.sp\n\\fBTcl_UnTraceVar(\\fIinterp, varName, flags, proc, clientData\\fB)\\fR\n.sp\n\\fBTcl_UnTraceVar2(\\fIinterp, name1, name2, flags, proc, clientData\\fB)\\fR\n.sp\nClientData\n\\fBTcl_VarTraceInfo(\\fIinterp, varName, flags, proc, prevClientData\\fB)\\fR\n.sp\nClientData\n\\fBTcl_VarTraceInfo2(\\fIinterp, name1, name2, flags, proc, prevClientData\\fB)\\fR\n.SH ARGUMENTS\n.AS Tcl_VarTraceProc prevClientData\n.AP Tcl_Interp *interp in\nInterpreter containing variable.\n.AP char *varName in\nName of variable.  May refer to a scalar variable, to\nan array variable with no index, or to an array variable\nwith a parenthesized index.\n.AP int flags in\nOR-ed combination of the values TCL_TRACE_READS, TCL_TRACE_WRITES, and\nTCL_TRACE_UNSETS, and TCL_GLOBAL_ONLY.  Not all flags are used by all\nprocedures.  See below for more information.\n.AP Tcl_VarTraceProc *proc in\nProcedure to invoke whenever one of the traced operations occurs.\n.AP ClientData clientData in\nArbitrary one-word value to pass to \\fIproc\\fR.\n.AP char *name1 in\nName of scalar or array variable (without array index).\n.AP char *name2 in\nFor a trace on an element of an array, gives the index of the\nelement.  For traces on scalar variables or on whole arrays,\nis NULL.\n.AP ClientData prevClientData in\nIf non-NULL, gives last value returned by \\fBTcl_VarTraceInfo\\fR or\n\\fBTcl_VarTraceInfo2\\fR, so this call will return information about\nnext trace.  If NULL, this call will return information about first\ntrace.\n.BE\n\n.SH DESCRIPTION\n.PP\n\\fBTcl_TraceVar\\fR allows a C procedure to monitor and control\naccess to a Tcl variable, so that the C procedure is invoked\nwhenever the variable is read or written or unset.\nIf the trace is created successfully then \\fBTcl_TraceVar\\fR returns\nTCL_OK.  If an error occurred (e.g. \\fIvarName\\fR specifies an element\nof an array, but the actual variable isn't an array) then TCL_ERROR\nis returned and an error message is left in \\fIinterp->result\\fR.\n.PP\nThe \\fIflags\\fR argument to \\fBTcl_TraceVar\\fR indicates when the\ntrace procedure is to be invoked and provides information\nfor setting up the trace.  It consists of an OR-ed combination\nof any of the following values:\n.TP\n\\fBTCL_GLOBAL_ONLY\\fR\nNormally, the variable will be looked up at the current level of\nprocedure call;  if this bit is set then the variable will be looked\nup at global level, ignoring any active procedures.\n.TP\n\\fBTCL_TRACE_READS\\fR\nInvoke \\fIproc\\fR whenever an attempt is made to read the variable.\n.TP\n\\fBTCL_TRACE_WRITES\\fR\nInvoke \\fIproc\\fR whenever an attempt is made to modify the variable.\n.TP\n\\fBTCL_TRACE_UNSETS\\fR\nInvoke \\fIproc\\fR whenever the variable is unset.\nA variable may be unset either explicitly by an \\fBunset\\fR command,\nor implicitly when a procedure returns (its local variables are\nautomatically unset) or when the interpreter is deleted (all\nvariables are automatically unset).\n.PP\nWhenever one of the specified operations occurs on the variable,\n\\fIproc\\fR will be invoked.\nIt should have arguments and result that match the type\n\\fBTcl_VarTraceProc\\fR:\n.nf\n.RS\ntypedef char *Tcl_VarTraceProc(\n.RS\nClientData \\fIclientData\\fR,\nTcl_Interp *\\fIinterp\\fR,\nchar *\\fIname1\\fR,\nchar *\\fIname2\\fR,\nint \\fIflags\\fR);\n.RE\n.RE\n.fi\nThe \\fIclientData\\fP and \\fIinterp\\fP parameters will\nhave the same values as those passed to \\fBTcl_TraceVar\\fR when the\ntrace was created.\n\\fIClientData\\fR typically points to an application-specific\ndata structure that describes what to do when \\fIproc\\fR\nis invoked.\n\\fIName1\\fR and \\fIname2\\fR give the name of the traced variable\nin the normal two-part form (see the description of \\fBTcl_TraceVar2\\fR\nbelow for details).\n\\fIFlags\\fR is an OR-ed combination of bits providing several\npieces of information.\nOne of the bits TCL_TRACE_READS, TCL_TRACE_WRITES, or TCL_TRACE_UNSETS\nwill be set in \\fIflags\\fR to indicate which operation is being performed\non the variable.\nThe bit TCL_GLOBAL_ONLY will be set whenever the variable being\naccessed is a global one not accessible from the current level of\nprocedure call:  the trace procedure will need to pass this flag\nback to variable-related procedures like \\fBTcl_GetVar\\fR if it\nattempts to access the variable.\nThe bit TCL_TRACE_DESTROYED will be set in \\fIflags\\fR if the trace is\nabout to be destroyed;  this information may be useful to \\fIproc\\fR\nso that it can clean up its own internal data structures (see\nthe section TCL_TRACE_DESTROYED below for more details).\nLastly, the bit TCL_INTERP_DESTROYED will be set if the entire\ninterpreter is being destroyed.\nWhen this bit is set, \\fIproc\\fR must be especially careful in\nthe things it does (see the section TCL_INTERP_DESTROYED below).\nThe trace procedure's return value should normally be NULL;  see\nERROR RETURNS below for information on other possibilities.\n.PP\n\\fBTcl_UntraceVar\\fR may be used to remove a trace.\nIf the variable specified by \\fIinterp\\fR, \\fIvarName\\fR, and \\fIflags\\fR\nhas a trace set with \\fIflags\\fR, \\fIproc\\fR, and\n\\fIclientData\\fR, then the corresponding trace is removed.\nIf no such trace exists, then the call to \\fBTcl_UntraceVar\\fR\nhas no effect.\nThe same bits are valid for \\fIflags\\fR as for calls to \\fBTcl_TraceVars\\fR.\n.PP\n\\fBTcl_VarTraceInfo\\fR may be used to retrieve information about\ntraces set on a given variable.\nThe return value from \\fBTcl_VarTraceInfo\\fR is the \\fIclientData\\fR\nassociated with a particular trace.\nThe trace must be on the variable specified by the \\fIinterp\\fR,\n\\fIvarName\\fR, and \\fIflags\\fR arguments (only the TCL_GLOBAL_ONLY\nbit from \\fIflags\\fR is used;  other bits are ignored) and its trace procedure\nmust the same as the \\fIproc\\fR argument.\nIf the \\fIprevClientData\\fR argument is NULL then the return\nvalue corresponds to the first (most recently created) matching\ntrace, or NULL if there are no matching traces.\nIf the \\fIprevClientData\\fR argument isn't NULL, then it should\nbe the return value from a previous call to \\fBTcl_VarTraceInfo\\fR.\nIn this case, the new return value will correspond to the next\nmatching trace after the one whose \\fIclientData\\fR matches\n\\fIprevClientData\\fR, or NULL if no trace matches \\fIprevClientData\\fR\nor if there are no more matching traces after it.\nThis mechanism makes it possible to step through all of the\ntraces for a given variable that have the same \\fIproc\\fR.\n\n.SH \"TWO-PART NAMES\"\n.PP\nThe procedures \\fBTcl_TraceVar2\\fR, \\fBTcl_UntraceVar2\\fR, and\n\\fBTcl_VarTraceInfo2\\fR are identical to \\fBTcl_TraceVar\\fR,\n\\fBTcl_UntraceVar\\fR, and \\fBTcl_VarTraceInfo\\fR, respectively,\nexcept that the name of the variable has already been\nseparated by the caller into two parts.\n\\fIName1\\fR gives the name of a scalar variable or array,\nand \\fIname2\\fR gives the name of an element within an\narray.\nIf \\fIname2\\fR is NULL it means that either the variable is\na scalar or the trace is to be set on the entire array rather\nthan an individual element (see WHOLE-ARRAY TRACES below for\nmore information).\n\n.SH \"ACCESSING VARIABLES DURING TRACES\"\n.PP\nDuring read and write traces, the\ntrace procedure can read or write the value of the traced\nvariable using \\fBTcl_GetVar2\\fR, \\fBTcl_SetVar2\\fR, and\nother procedures.\nWhile \\fIproc\\fR is executing, traces are temporarily disabled\nfor the variable, so that calls to \\fBTcl_GetVar2\\fR and\n\\fBTcl_SetVar2\\fR will not cause \\fIproc\\fR or other trace procedures\nto be invoked again.\nDisabling only occurs for the variable whose trace procedure\nis active;  accesses to other variables will still be traced.\n.PP\nDuring unset traces the variable has already been completely\nexpunged.\nIt is possible for the trace procedure to read or write the\nvariable, but this will be a new version of the variable.\nTraces are not disabled during unset traces as they are for\nread and write traces, but existing traces have been removed\nfrom the variable before any trace procedures are invoked.\nIf new traces are set by unset trace procedures, these traces\nwill be invoked on accesses to the variable by the trace\nprocedures.\n\n.SH \"CALLBACK TIMING\"\n.PP\nWhen read tracing has been specified for a variable, the trace\nprocedure will be invoked whenever the variable's value is\nread.  This includes \\fBset\\fR Tcl commands, \\fB$\\fR-notation\nin Tcl commands, and invocations of the \\fBTcl_GetVar\\fR\nand \\fBTcl_GetVar2\\fR procedures.\n\\fIProc\\fR is invoked just before the variable's value is\nreturned.\nIt may modify the value of the variable to affect what\nis returned by the traced access.\n.PP\nWhen write tracing has been specified for a variable, the\ntrace procedure will be invoked whenever the variable's value\nis modified.  This includes \\fBset\\fR commands\\fR,\ncommands that modify variables as side effects (such as\n\\fBcatch\\fR and \\fBscan\\fR), and calls to the \\fBTcl_SetVar\\fR\nand \\fBTcl_SetVar2\\fR procedures).\n\\fIProc\\fR will be invoked after the variable's value has been\nmodified, but before the new value of the variable has been\nreturned.\nIt may modify the value of the variable to override the change\nand to determine the value actually returned by the traced\naccess.\n.PP\nWhen unset tracing has been specified, the trace procedure\nwill be invoked whenever the variable is destroyed.\nThe traces will be called after the variable has been\ncompletely unset.\n\n.SH \"WHOLE-ARRAY TRACES\"\n.PP\nIf a call to \\fBTcl_TraceVar\\fR or \\fBTcl_TraceVar2\\fR specifies\nthe name of an array variable without an index into the array,\nthen the trace will be set on the array as a whole.\nThis means that \\fIproc\\fR will be invoked whenever any\nelement of the array is accessed in the ways specified by\n\\fIflags\\fR.\nWhen an array is unset, a whole-array trace will be invoked\njust once, with \\fIname1\\fR equal to the name of the array\nand \\fIname2\\fR NULL;  it will not be invoked once for each\nelement.\n\n.SH \"MULTIPLE TRACES\"\n.PP\nIt is possible for multiple traces to exist on the same variable.\nWhen this happens, all of the trace procedures will be invoked on each\naccess, in order from most-recently-created to least-recently-created.\nWhen there exist whole-array traces for an array as well as\ntraces on individual elements, the whole-array traces are invoked\nbefore the individual-element traces.\n\n.SH \"ERROR RETURNS\"\n.PP\nUnder normal conditions trace procedures should return NULL, indicating\nsuccessful completion.\nIf \\fIproc\\fR returns a non-NULL value it signifies that an\nerror occurred.\nThe return value must be a pointer to a static character string\ncontaining an error message.\nIf a trace procedure returns an error, no further traces are\ninvoked for the access and the traced access aborts with the\ngiven message.\nTrace procedures can use this facility to make variables\nread-only, for example (but note that the value of the variable\nwill already have been modified before the trace procedure is\ncalled, so the trace procedure will have to restore the correct\nvalue).\n.PP\nThe return value from \\fIproc\\fR is only used during read and\nwrite tracing.\nDuring unset traces, the return value is ignored and all relevant\ntrace procedures will always be invoked.\n\n.SH \"RESTRICTIONS\"\n.PP\nIt is not legal to delete a variable while a trace procedure\nis active for the variable.\n.PP\n.VS\nAlso, a trace procedure can be called at any time, even when there\nis a partically-formed result in the interpreter's result area.  If\nthe trace procedure does anything that could damage this result (such\nas calling \\fBTcl_Eval\\fR) then it must save the original values of\nthe interpreter's \\fBresult\\fR and \\fBfreeProc\\fR fields and restore\nthem before it returns.\n.VE\n\n.SH \"UNDEFINED VARIABLES\"\n.PP\nIt is legal to set a trace on an undefined variable.\nThe variable will still appear to be undefined until the\nfirst time its value is set.\nIf an undefined variable is traced and then unset, the unset will fail\nwith an error (``no such variable''), but the trace\nprocedure will still be invoked.\n\n.SH \"TCL_TRACE_DELETED FLAG\"\n.PP\nIn an unset callback to \\fIproc\\fR, the TCL_TRACE_DELETED bit\nis set in \\fIflags\\fR if the trace is being removed as part\nof the deletion.\nTraces on a variable are always removed whenever the variable\nis deleted;  the only time TCL_TRACE_DELETED isn't set is for\na whole-array trace invoked when only a single element of an\narray is unset.\n\n.SH \"TCL_INTERP_DESTROYED\"\n.PP\nWhen an interpreter is destroyed, unset traces are called for\nall of its variables.\nThe TCL_INTERP_DESTROYED bit will be set in the \\fIflags\\fR\nargument passed to the trace procedures.\nTrace procedures must be extremely careful in what they do if\nthe TCL_INTERP_DESTROYED bit is set.\nIt is not safe for the procedures to invoke any Tcl procedures\non the interpreter, since its state is partially deleted.\nAll that trace procedures should do under these circumstances is\nto clean up and free their own internal data structures.\n\n.SH BUGS\n.PP\nTcl doesn't do any error checking to prevent trace procedures\nfrom misusing the interpreter during traces with TCL_INTERP_DESTROYED\nset.\n\n.SH KEYWORDS\nclientData, trace, variable\n.VE\n"
  },
  {
    "path": "lib/libtcl/doc/library.n",
    "content": "'\\\"\n'\\\" Copyright 1991-1992 Regents of the University of California\n'\\\" Permission to use, copy, modify, and distribute this\n'\\\" documentation for any purpose and without fee is hereby\n'\\\" granted, provided that this notice appears in all copies.\n'\\\" The University of California makes no representations about\n'\\\" the suitability of this material for any purpose.  It is\n'\\\" provided \"as is\" without express or implied warranty.\n'\\\" \n'\\\" $Header: /cvsroot/PROCPLACE/pptinytcl/doc/library.n,v 1.1.1.1 2001/04/20 15:03:06 karl Exp $ SPRITE (Berkeley)\n'\n.so man.macros\n.de UL\n\\\\$1\\l'|0\\(ul'\\\\$2\n..\n.HS library tcl\n.BS\n.SH NAME\nlibrary \\- standard library of Tcl procedures\n.SH SYNOPSIS\n.nf\n\\fBauto_execok \\fIcmd\\fR\n\\fBauto_load \\fIcmd\\fR\n\\fBauto_mkindex \\fIdir pattern\\fR\n\\fBauto_reset\\fR\n\\fBparray \\fIarrayName\\fR\n\\fBunknown \\fIcmd \\fR?\\fIarg arg ...\\fR?\n.fi\n.BE\n\n.SH INTRODUCTION\n.PP\nTcl includes a library of Tcl procedures for commonly-needed functions.\nThe procedures defined in the Tcl library are generic ones suitable\nfor use by many different applications.\nThe location of the Tcl library is returned by the \\fBinfo library\\fR\ncommand.\nIn addition to the Tcl library, each application will normally have\nits own library of support procedures as well;  the location of this\n.VS\nlibrary is normally given by the value of the \\fB$\\fIapp\\fB_library\\fR\nglobal variable, where \\fIapp\\fR is the name of the application.\nFor example, the location of the Tk library is kept in the variable\n\\fB$tk_library\\fR.\n.VE\n.PP\nTo access the procedures in the Tcl library, an application should\nsource the file \\fBinit.tcl\\fR in the library, for example with\nthe Tcl command\n.DS\n\\fBsource [info library]/init.tcl\n.DE\nThis will define the \\fBunknown\\fR procedure and arrange for the\nother procedures to be loaded on-demand using the auto-load\nmechanism defined below.\n\n.SH \"COMMAND PROCEDURES\"\n.PP\nThe following procedures are provided in the Tcl library:\n.TP\n\\fBauto_execok \\fIcmd\\fR\nDetermines whether there is an executable file by the name \\fIcmd\\fR.\nThis command examines the directories in the current search path\n(given by the PATH enviornment variable) to see if there is an\nexecutable file named \\fIcmd\\fR in any of those directories.\nIf so, it returns 1;  if not it returns 0.  \\fBAuto_exec\\fR\nremembers information about previous searches in an array\nnamed \\fBauto_execs\\fR;  this avoids the path search in\nfuture calls for the same \\fIcmd\\fR.  The command \\fBauto_reset\\fR\nmay be used to force \\fBauto_execok\\fR to forget its cached\ninformation.\n.TP\n\\fBauto_load \\fIcmd\\fR\nThis command attempts to load the definition for a Tcl procedure named\n\\fIcmd\\fR.\nTo do this, it searches an \\fIauto-load path\\fR, which is a list of\none or more directories.\nThe auto-load path is given by the global variable \\fB$auto_path\\fR\nif it exists.\nIf there is no \\fB$auto_path\\fR variable, then the TCLLIBPATH environment\nvariable is used, if it exists.\nOtherwise the auto-load path consists of just the Tcl library directory.\nWithin each directory in the auto-load path there must be a file\n\\fBtclIndex\\fR that describes the procedures defined in that directory\nand the file in which each procedure is defined.  The \\fBtclIndex\\fR\nfile should be generated with the \\fBauto_mkindex\\fR command.\nIf \\fIcmd\\fR is found in an index file, then the appropriate\nscript is \\fBsource\\fRd to create the procedure.\nThe \\fBauto_load\\fR command returns 1 if the script was successfully\nsourced and \\fIcmd\\fR now exists.\nThe command returns 0 if there was no index entry for \\fIcmd\\fR\nor if the script didn't actually define \\fIcmd\\fR (e.g. because\nindex information is out of date).\nIf an error occurs while processing the script, then that error\nis returned.\n\\fBAuto_load\\fR only reads the index information once and saves it\nin the array \\fBauto_index\\fR;  future calls to \\fBauto_load\\fR\ncheck for \\fIcmd\\fR in the array rather than re-reading the index\nfiles.\nThe cached index information may be deleted with the command\n\\fBauto_reset\\fR.\nThis will force the next \\fBauto_load\\fR command to reload the\nindex database from disk.\n.TP\n\\fBauto_mkindex \\fIdir pattern\\fR\nGenerates an index suitable for use by \\fBauto_load\\fR.\nThe command searches \\fIdir\\fR for all files whose names match\n\\fIpattern\\fR (matching is done with the \\fBglob\\fR command),\ngenerates an index of all the Tcl command\nprocedures defined in all the matching files, and stores the\nindex information in a file named \\fBtclIndex\\fR in \\fIdir\\fR.\nFor example, the command\n.RS\n.DS\n\\fBauto_mkindex foo *.tcl\\fR\n.DE\n.LP\nwill read all the \\fB.tcl\\fR files in subdirectory \\fBfoo\\fR\nand generate a new index file \\fBfoo/tclIndex\\fR.\n.PP\n\\fBAuto_mkindex\\fR parses the Tcl scripts in a relatively\nunsophisticated way:  if any line contains the word \\fBproc\\fR\nas its first characters then it is assumed to be a procedure\ndefinition and the next word of the line is taken as the\nprocedure's name.\nProcedure definitions that don't appear in this way (e.g. they\nhave spaces before the \\fBproc\\fR) will not be indexed.\n.RE\n.TP\n\\fBauto_reset\\fR\nDestroys all the information cached by \\fBauto_execok\\fR and\n\\fBauto_load\\fR.\nThis information will be re-read from disk the next time it is\nneeded.\n.VS\n\\fBAuto_reset\\fR also deletes any procedures listed in the auto-load\nindex, so that fresh copies of them will be loaded the next time\nthat they're used.\n.VE\n.TP\n\\fBparray \\fIarrayName\\fR\nPrints on standard output the names and values of all the elements\nin the array \\fIarrayName\\fR.\n.VS\n\\fBArrayName\\fR must be an array accessible to the caller of \\fBparray\\fR.\nIt may be either local or global.\n.VE\n.TP\n\\fBunknown \\fIcmd \\fR?\\fIarg arg ...\\fR?\nThis procedure is invoked automatically by the Tcl interpreter\nwhenever the name of a command doesn't exist.\nThe \\fBunknown\\fR procedure receives as its arguments the\nname and arguments of the missing command.\n\\fBUnknown\\fR first calls \\fBauto_load\\fR to load a procedure for\nthe command.\nIf this succeeds, then it executes the original command with its\noriginal arguments.\nIf the auto-load fails then \\fBunknown\\fR calls \\fBauto_execok\\fR\nto see if there is an executable file by the name \\fIcmd\\fR.\nIf so, it invokes the Tcl \\fBexec\\fR command\nwith \\fIcmd\\fR and all the \\fIargs\\fR as arguments.\nIf \\fIcmd\\fR can't be auto-executed, \\fBunknown\\fR checks to\nsee if the command was invoked at top-level and outside of any\nscript.  If so, then \\fBunknown\\fR takes takes two additional steps.\nFirst, it sees if \\fIcmd\\fR has one of the following three forms:\n\\fB!!\\fR, \\fB!\\fIevent\\fR, or \\fB^\\fIold\\fB^\\fInew\\fR?\\fB^\\fR?.\nIf so, then \\fBunknown\\fR carries out history substitution\nin the same way that \\fBcsh\\fR would for these constructs.\nSecond, and last, \\fBunknown\\fR checks to see if \\fIcmd\\fR is\na unique abbreviation for an existing Tcl command.\nIf so, it expands the command name and executes the command with\nthe original arguments.\nIf none of the above efforts has been able to execute\nthe command, \\fBunknown\\fR generates an error return.\nIf the global variable \\fBauto_noload\\fR is defined, then the auto-load\nstep is skipped.\nIf the global variable \\fBauto_noexec\\fR is defined then the\nauto-exec step is skipped.\nUnder normal circumstances the return value from \\fBunknown\\fR\nis the return value from the command that was eventually\nexecuted.\n\n.SH \"VARIABLES\"\n.PP\nThe following global variables are defined or used by the procedures in\nthe Tcl library:\n.TP\n\\fBauto_execs\\fR\nUsed by \\fBauto_execok\\fR to record information about whether\nparticular commands exist as executable files.\n.TP\n\\fBauto_index\\fR\nUsed by \\fBauto_load\\fR to save the index information read from\ndisk.\n.TP\n\\fBauto_noexec\\fR\nIf set to any value, then \\fBunknown\\fR will not attempt to auto-exec\nany commands.\n.TP\n\\fBauto_noload\\fR\nIf set to any value, then \\fBunknown\\fR will not attempt to auto-load\nany commands.\n.TP\n\\fBauto_path\\fR\nIf set, then it must contain a valid Tcl list giving directories to\nsearch during auto-load operations.\n.TP\n\\fBenv(TCL_LIBRARY)\\fR\n.VS\nIf set, then it specifies the location of the directory containing\nlibrary scripts (the value of this variable will be returned by\nthe command \\fBinfo library\\fR).  If this variable isn't set then\na default value is used.\n.VE\n.TP\n\\fBenv(TCLLIBPATH)\\fR\nIf set, then it must contain a valid Tcl list giving directories to\nsearch during auto-load operations.\nThis variable is only used if \\fBauto_path\\fR is not defined.\n.TP\n\\fBunknown_active\\fR\nThis variable is set by \\fBunknown\\fR to indicate that it is active.\nIt is used to detect errors where \\fBunknown\\fR recurses on itself\ninfinitely.\nThe variable is unset before \\fBunknown\\fR returns.\n\n.SH KEYWORDS\nauto-exec, auto-load, library, unknown\n"
  },
  {
    "path": "lib/libtcl/doc/man.macros",
    "content": ".\\\" The definitions below are for supplemental macros used in Tcl/Tk\n.\\\" manual entries.\n.\\\"\n.\\\" .HS name section [date [version]]\n.\\\"\tReplacement for .TH in other man pages.  See below for valid\n.\\\"\tsection names.\n.\\\"\n.\\\" .AP type name in/out [indent]\n.\\\"\tStart paragraph describing an argument to a library procedure.\n.\\\"\ttype is type of argument (int, etc.), in/out is either \"in\", \"out\",\n.\\\"\tor \"in/out\" to describe whether procedure reads or modifies arg,\n.\\\"\tand indent is equivalent to second arg of .IP (shouldn't ever be\n.\\\"\tneeded;  use .AS below instead)\n.\\\"\n.\\\" .AS [type [name]]\n.\\\"\tGive maximum sizes of arguments for setting tab stops.  Type and\n.\\\"\tname are examples of largest possible arguments that will be passed\n.\\\"\tto .AP later.  If args are omitted, default tab stops are used.\n.\\\"\n.\\\" .BS\n.\\\"\tStart box enclosure.  From here until next .BE, everything will be\n.\\\"\tenclosed in one large box.\n.\\\"\n.\\\" .BE\n.\\\"\tEnd of box enclosure.\n.\\\"\n.\\\" .VS\n.\\\"\tBegin vertical sidebar, for use in marking newly-changed parts\n.\\\"\tof man pages.\n.\\\"\n.\\\" .VE\n.\\\"\tEnd of vertical sidebar.\n.\\\"\n.\\\" .DS\n.\\\"\tBegin an indented unfilled display.\n.\\\"\n.\\\" .DE\n.\\\"\tEnd of indented unfilled display.\n.\\\"\n'\\\"\t# Heading for Tcl/Tk man pages\n.de HS\n.if '\\\\$2'cmds'       .TH \\\\$1 1 \\\\$3 \\\\$4\n.if '\\\\$2'lib'        .TH \\\\$1 3 \\\\$3 \\\\$4\n.if '\\\\$2'tcl'        .TH \\\\$1 3 \\\\$3 \\\\$4\n.if '\\\\$2'tk'         .TH \\\\$1 3 \\\\$3 \\\\$4\n.if t .wh -1.3i ^B\n.nr ^l \\\\n(.l\n.ad b\n..\n'\\\"\t# Start an argument description\n.de AP\n.ie !\"\\\\$4\"\" .TP \\\\$4\n.el \\{\\\n.   ie !\"\\\\$2\"\" .TP \\\\n()Cu\n.   el          .TP 15\n.\\}\n.ie !\"\\\\$3\"\" \\{\\\n.ta \\\\n()Au \\\\n()Bu\n\\&\\\\$1\t\\\\fI\\\\$2\\\\fP\t(\\\\$3)\n.\\\".b\n.\\}\n.el \\{\\\n.br\n.ie !\"\\\\$2\"\" \\{\\\n\\&\\\\$1\t\\\\fI\\\\$2\\\\fP\n.\\}\n.el \\{\\\n\\&\\\\fI\\\\$1\\\\fP\n.\\}\n.\\}\n..\n'\\\"\t# define tabbing values for .AP\n.de AS\n.nr )A 10n\n.if !\"\\\\$1\"\" .nr )A \\\\w'\\\\$1'u+3n\n.nr )B \\\\n()Au+15n\n.\\\"\n.if !\"\\\\$2\"\" .nr )B \\\\w'\\\\$2'u+\\\\n()Au+3n\n.nr )C \\\\n()Bu+\\\\w'(in/out)'u+2n\n..\n'\\\"\t# BS - start boxed text\n'\\\"\t# ^y = starting y location\n'\\\"\t# ^b = 1\n.de BS\n.br\n.mk ^y\n.nr ^b 1u\n.if n .nf\n.if n .ti 0\n.if n \\l'\\\\n(.lu\\(ul'\n.if n .fi\n..\n'\\\"\t# BE - end boxed text (draw box now)\n.de BE\n.nf\n.ti 0\n.mk ^t\n.ie n \\l'\\\\n(^lu\\(ul'\n.el \\{\\\n.\\\"\tDraw four-sided box normally, but don't draw top of\n.\\\"\tbox if the box started on an earlier page.\n.ie !\\\\n(^b-1 \\{\\\n\\h'-1.5n'\\L'|\\\\n(^yu-1v'\\l'\\\\n(^lu+3n\\(ul'\\L'\\\\n(^tu+1v-\\\\n(^yu'\\l'|0u-1.5n\\(ul'\n.\\}\n.el \\}\\\n\\h'-1.5n'\\L'|\\\\n(^yu-1v'\\h'\\\\n(^lu+3n'\\L'\\\\n(^tu+1v-\\\\n(^yu'\\l'|0u-1.5n\\(ul'\n.\\}\n.\\}\n.fi\n.br\n.nr ^b 0\n..\n'\\\"\t# VS - start vertical sidebar\n'\\\"\t# ^Y = starting y location\n'\\\"\t# ^v = 1 (for troff;  for nroff this doesn't matter)\n.de VS\n.mk ^Y\n.ie n 'mc \\s12\\(br\\s0\n.el .nr ^v 1u\n..\n'\\\"\t# VE - end of vertical sidebar\n.de VE\n.ie n 'mc\n.el \\{\\\n.ev 2\n.nf\n.ti 0\n.mk ^t\n\\h'|\\\\n(^lu+3n'\\L'|\\\\n(^Yu-1v\\(bv'\\v'\\\\n(^tu+1v-\\\\n(^Yu'\\h'-|\\\\n(^lu+3n'\n.sp -1\n.fi\n.ev\n.\\}\n.nr ^v 0\n..\n'\\\"\t# Special macro to handle page bottom:  finish off current\n'\\\"\t# box/sidebar if in box/sidebar mode, then invoked standard\n'\\\"\t# page bottom macro.\n.de ^B\n.ev 2\n'ti 0\n'nf\n.mk ^t\n.if \\\\n(^b \\{\\\n.\\\"\tDraw three-sided box if this is the box's first page,\n.\\\"\tdraw two sides but no top otherwise.\n.ie !\\\\n(^b-1 \\h'-1.5n'\\L'|\\\\n(^yu-1v'\\l'\\\\n(^lu+3n\\(ul'\\L'\\\\n(^tu+1v-\\\\n(^yu'\\h'|0u'\\c\n.el \\h'-1.5n'\\L'|\\\\n(^yu-1v'\\h'\\\\n(^lu+3n'\\L'\\\\n(^tu+1v-\\\\n(^yu'\\h'|0u'\\c\n.\\}\n.if \\\\n(^v \\{\\\n.nr ^x \\\\n(^tu+1v-\\\\n(^Yu\n\\kx\\h'-\\\\nxu'\\h'|\\\\n(^lu+3n'\\ky\\L'-\\\\n(^xu'\\v'\\\\n(^xu'\\h'|0u'\\c\n.\\}\n.bp\n'fi\n.ev\n.if \\\\n(^b \\{\\\n.mk ^y\n.nr ^b 2\n.\\}\n.if \\\\n(^v \\{\\\n.mk ^Y\n.\\}\n..\n'\\\"\t# DS - begin display\n.de DS\n.RS\n.nf\n.sp\n..\n'\\\"\t# DE - end display\n.de DE\n.fi\n.RE\n.sp .5\n..\n"
  },
  {
    "path": "lib/libtcl/hash.h",
    "content": "/*\n * tclHash.h --\n *\n *\tThis header file declares the facilities provided by the\n *\tTcl hash table procedures.\n *\n * Copyright 1991 Regents of the University of California\n * Permission to use, copy, modify, and distribute this\n * software and its documentation for any purpose and without\n * fee is hereby granted, provided that the above copyright\n * notice appear in all copies.  The University of California\n * makes no representations about the suitability of this\n * software for any purpose.  It is provided \"as is\" without\n * express or implied warranty.\n */\n\n/*\n * Structure definition for an entry in a hash table.  No-one outside\n * Tcl should access any of these fields directly;  use the macros\n * defined below.\n */\ntypedef struct Tcl_HashEntry {\n    struct Tcl_HashEntry *nextPtr;\t/* Pointer to next entry in this\n\t\t\t\t\t * hash bucket, or NULL for end of\n\t\t\t\t\t * chain. */\n    struct Tcl_HashTable *tablePtr;\t/* Pointer to table containing entry. */\n    struct Tcl_HashEntry **bucketPtr;\t/* Pointer to bucket that points to\n\t\t\t\t\t * first entry in this entry's chain:\n\t\t\t\t\t * used for deleting the entry. */\n    void *clientData;\t\t\t/* Application stores something here\n\t\t\t\t\t * with Tcl_SetHashValue. */\n    union {\t\t\t\t/* Key has one of these forms: */\n\tunsigned char *oneWordValue;\t/* One-word value for key. */\n\tint words[1];\t\t\t/* Multiple integer words for key.\n\t\t\t\t\t * The actual size will be as large\n\t\t\t\t\t * as necessary for this table's\n\t\t\t\t\t * keys. */\n\tunsigned char string[4];\t/* String for key.  The actual size\n\t\t\t\t\t * will be as large as needed to hold\n\t\t\t\t\t * the key. */\n    } key;\t\t\t\t/* MUST BE LAST FIELD IN RECORD!! */\n} Tcl_HashEntry;\n\n/*\n * Structure definition for a hash table.  Must be in tcl.h so clients\n * can allocate space for these structures, but clients should never\n * access any fields in this structure.\n */\n#define TCL_SMALL_HASH_TABLE 4\n\ntypedef struct Tcl_HashTable {\n    Tcl_HashEntry **buckets;\t\t/* Pointer to bucket array.  Each\n\t\t\t\t\t * element points to first entry in\n\t\t\t\t\t * bucket's hash chain, or NULL. */\n    Tcl_HashEntry *staticBuckets[TCL_SMALL_HASH_TABLE];\n\t\t\t\t\t/* Bucket array used for small tables\n\t\t\t\t\t * (to avoid mallocs and frees). */\n    int numBuckets;\t\t\t/* Total number of buckets allocated\n\t\t\t\t\t * at **bucketPtr. */\n    int numEntries;\t\t\t/* Total number of entries present\n\t\t\t\t\t * in table. */\n    int rebuildSize;\t\t\t/* Enlarge table when numEntries gets\n\t\t\t\t\t * to be this large. */\n    int downShift;\t\t\t/* Shift count used in hashing\n\t\t\t\t\t * function.  Designed to use high-\n\t\t\t\t\t * order bits of randomized keys. */\n    int mask;\t\t\t\t/* Mask value used in hashing\n\t\t\t\t\t * function. */\n    int keyType;\t\t\t/* Type of keys used in this table.\n\t\t\t\t\t * It's either TCL_STRING_KEYS,\n\t\t\t\t\t * TCL_ONE_WORD_KEYS, or an integer\n\t\t\t\t\t * giving the number of ints in a\n\t\t\t\t\t */\n    Tcl_HashEntry *(*findProc) (struct Tcl_HashTable *tablePtr, unsigned char *key);\n    Tcl_HashEntry *(*createProc) (struct Tcl_HashTable *tablePtr,\n\t    unsigned char *key, int *newPtr);\n} Tcl_HashTable;\n\n/*\n * Structure definition for information used to keep track of searches\n * through hash tables:\n */\ntypedef struct Tcl_HashSearch {\n    Tcl_HashTable *tablePtr;\t\t/* Table being searched. */\n    int nextIndex;\t\t\t/* Index of next bucket to be\n\t\t\t\t\t * enumerated after present one. */\n    Tcl_HashEntry *nextEntryPtr;\t/* Next entry to be enumerated in the\n\t\t\t\t\t * the current bucket. */\n} Tcl_HashSearch;\n\n/*\n * Acceptable key types for hash tables:\n */\n#define TCL_STRING_KEYS\t\t0\n#define TCL_ONE_WORD_KEYS\t1\n\n/*\n * Macros for clients to use to access fields of hash entries:\n */\n#define Tcl_GetHashValue(h) ((h)->clientData)\n#define Tcl_SetHashValue(h, value) ((h)->clientData = (void*) (value))\n#define Tcl_GetHashKey(tablePtr, h) \\\n    (((tablePtr)->keyType == TCL_ONE_WORD_KEYS) ? (h)->key.oneWordValue \\\n\t\t\t\t\t\t: (h)->key.string)\n\n/*\n * Macros to use for clients to use to invoke find and create procedures\n * for hash tables:\n */\n#define Tcl_FindHashEntry(tablePtr, key) \\\n\t(*((tablePtr)->findProc))(tablePtr, key)\n#define Tcl_CreateHashEntry(tablePtr, key, newPtr) \\\n\t(*((tablePtr)->createProc))(tablePtr, key, newPtr)\n\n/*\n * Exported procedures:\n */\nextern void\t\tTcl_DeleteHashEntry (Tcl_HashEntry *entryPtr);\nextern void\t\tTcl_DeleteHashTable (Tcl_HashTable *tablePtr);\nextern Tcl_HashEntry *\tTcl_FirstHashEntry (Tcl_HashTable *tablePtr,\n\t\t\t\tTcl_HashSearch *searchPtr);\nextern unsigned char *\tTcl_HashStats (Tcl_HashTable *tablePtr);\nextern void\t\tTcl_InitHashTable (Tcl_HashTable *tablePtr,\n                                int keyType);\nextern Tcl_HashEntry *\tTcl_NextHashEntry (Tcl_HashSearch *searchPtr);\n"
  },
  {
    "path": "lib/libtcl/internal.h",
    "content": "/*\n * tclInt.h --\n *\n *\tDeclarations of things used internally by the Tcl interpreter.\n *\n * Copyright 1987-1991 Regents of the University of California\n * Permission to use, copy, modify, and distribute this\n * software and its documentation for any purpose and without\n * fee is hereby granted, provided that the above copyright\n * notice appear in all copies.  The University of California\n * makes no representations about the suitability of this\n * software for any purpose.  It is provided \"as is\" without\n * express or implied warranty.\n */\n\n/*\n * Common include files needed by most of the Tcl source files are\n * included here, so that system-dependent personalizations for the\n * include files only have to be made in once place.\n */\n#ifdef CROSS\n#   include </usr/include/stdio.h>\n#   include </usr/include/ctype.h>\n#else\n#   include <stdio.h>\n#   include <ctype.h>\n#endif\n#include <stdlib.h>\n#include <string.h>\n#include <tcl/tcl.h>\n#include \"hash.h\"\n\n/*\n *----------------------------------------------------------------\n * Data structures related to variables.   These are used primarily\n * in tclVar.c\n *----------------------------------------------------------------\n */\n\n/*\n * The following structure defines a variable trace, which is used to\n * invoke a specific C procedure whenever certain operations are performed\n * on a variable.\n */\ntypedef struct VarTrace {\n    Tcl_VarTraceProc *traceProc;/* Procedure to call when operations given\n\t\t\t\t * by flags are performed on variable. */\n    void *clientData;\t\t/* Argument to pass to proc. */\n    unsigned char flags;\t/* What events the trace procedure is\n\t\t\t\t * interested in:  OR-ed combination of\n\t\t\t\t * TCL_TRACE_READS, TCL_TRACE_WRITES, and\n\t\t\t\t * TCL_TRACE_UNSETS. */\n    struct VarTrace *nextPtr;\t/* Next in list of traces associated with\n\t\t\t\t * a particular variable. */\n} VarTrace;\n\n/*\n * When a variable trace is active (i.e. its associated procedure is\n * executing), one of the following structures is linked into a list\n * associated with the variable's interpreter.  The information in\n * the structure is needed in order for Tcl to behave reasonably\n * if traces are deleted while traces are active.\n */\ntypedef struct ActiveVarTrace {\n    struct ActiveVarTrace *nextPtr;\n\t\t\t\t/* Next in list of all active variable\n\t\t\t\t * traces for the interpreter, or NULL\n\t\t\t\t * if no more. */\n    VarTrace *nextTracePtr;\t/* Next trace to check after current\n\t\t\t\t * trace procedure returns;  if this\n\t\t\t\t * trace gets deleted, must update pointer\n\t\t\t\t * to avoid using free'd memory. */\n} ActiveVarTrace;\n\n/*\n * The following structure describes an enumerative search in progress on\n * an array variable;  this are invoked with options to the \"array\"\n * command.\n */\ntypedef struct ArraySearch {\n    unsigned short id;\t\t/* Integer id used to distinguish among\n\t\t\t\t * multiple concurrent searches for the\n\t\t\t\t * same array. */\n    struct Var *varPtr;\t\t/* Pointer to array variable that's being\n\t\t\t\t * searched. */\n    Tcl_HashSearch search;\t/* Info kept by the hash module about\n\t\t\t\t * progress through the array. */\n    Tcl_HashEntry *nextEntry;\t/* Non-null means this is the next element\n\t\t\t\t * to be enumerated (it's leftover from\n\t\t\t\t * the Tcl_FirstHashEntry call or from\n\t\t\t\t * an \"array anymore\" command).  NULL\n\t\t\t\t * means must call Tcl_NextHashEntry\n\t\t\t\t * to get value to return. */\n    struct ArraySearch *nextPtr;/* Next in list of all active searches\n\t\t\t\t * for this variable, or NULL if this is\n\t\t\t\t * the last one. */\n} ArraySearch;\n\n/*\n * The structure below defines a variable, which associates a string name\n * with a string value.  Pointers to these structures are kept as the\n * values of hash table entries, and the name of each variable is stored\n * in the hash entry.\n */\ntypedef struct Var {\n    unsigned short valueLength;\t/* Holds the number of non-null bytes\n\t\t\t\t * actually occupied by the variable's\n\t\t\t\t * current value in value.string (extra\n\t\t\t\t * space is sometimes left for expansion).\n\t\t\t\t * For array and global variables this is\n\t\t\t\t * meaningless. */\n    unsigned short valueSpace;\t/* Total number of bytes of space allocated\n\t\t\t\t * at value. */\n    unsigned short upvarUses;\t/* Counts number of times variable is\n\t\t\t\t * is referenced via global or upvar variables\n\t\t\t\t * (i.e. how many variables have \"upvarPtr\"\n\t\t\t\t * pointing to this variable).  Variable\n\t\t\t\t * can't be deleted until this count reaches\n\t\t\t\t * 0. */\n    VarTrace *tracePtr;\t\t/* First in list of all traces set for this\n\t\t\t\t * variable. */\n    ArraySearch *searchPtr;\t/* First in list of all searches active\n\t\t\t\t * for this variable, or NULL if none. */\n    unsigned char flags;\t/* Miscellaneous bits of information about\n\t\t\t\t * variable.  See below for definitions. */\n    union {\n\tunsigned char string[4]; /* String value of variable.  The actual\n\t\t\t\t * length of this field is given by the\n\t\t\t\t * valueSpace field above. */\n\tTcl_HashTable *tablePtr;/* For array variables, this points to\n\t\t\t\t * information about the hash table used\n\t\t\t\t * to implement the associative array.\n\t\t\t\t * Points to malloc-ed data. */\n\tTcl_HashEntry *upvarPtr;\n\t\t\t\t/* If this is a global variable being\n\t\t\t\t * referred to in a procedure, or a variable\n\t\t\t\t * created by \"upvar\", this field points to\n\t\t\t\t * the hash table entry for the higher-level\n\t\t\t\t * variable. */\n    } value;\t\t\t/* MUST BE LAST FIELD IN STRUCTURE!!! */\n} Var;\n\n/*\n * Flag bits for variables:\n *\n * VAR_ARRAY\t-\t\t1 means this is an array variable rather\n *\t\t\t\tthan a scalar variable.\n * VAR_UPVAR - \t\t\t1 means this variable just contains a\n *\t\t\t\tpointer to another variable that has the\n *\t\t\t\treal value.  Variables like this come\n *\t\t\t\tabout through the \"upvar\" and \"global\"\n *\t\t\t\tcommands.\n * VAR_UNDEFINED -\t\t1 means that the variable is currently\n *\t\t\t\tundefined.  Undefined variables usually\n *\t\t\t\tgo away completely, but if an undefined\n *\t\t\t\tvariable has a trace on it, or if it is\n *\t\t\t\ta global variable being used by a procedure,\n *\t\t\t\tthen it stays around even when undefined.\n * VAR_ELEMENT_ACTIVE -\t\tUsed only in array variables;  1 means that\n *\t\t\t\tan element of the array is currently being\n *\t\t\t\tmanipulated in some way, so that it isn't\n *\t\t\t\tsafe to delete the whole array.\n * VAR_TRACE_ACTIVE -\t\t1 means that trace processing is currently\n *\t\t\t\tunderway for a read or write access, so\n *\t\t\t\tnew read or write accesses should not cause\n *\t\t\t\ttrace procedures to be called and the\n *\t\t\t\tvariable can't be deleted.\n */\n#define VAR_ARRAY\t\t1\n#define VAR_UPVAR\t\t2\n#define VAR_UNDEFINED\t\t4\n#define VAR_ELEMENT_ACTIVE\t0x10\n#define VAR_TRACE_ACTIVE\t0x20\n#define VAR_SEARCHES_POSSIBLE\t0x40\n\n/*\n *----------------------------------------------------------------\n * Data structures related to procedures.   These are used primarily\n * in tclProc.c\n *----------------------------------------------------------------\n */\n\n/*\n * The structure below defines an argument to a procedure, which\n * consists of a name and an (optional) default value.\n */\ntypedef struct Arg {\n    struct Arg *nextPtr;\t/* Next argument for this procedure,\n\t\t\t\t * or NULL if this is the last argument. */\n    unsigned char *defValue;\t/* Pointer to arg's default value, or NULL\n\t\t\t\t * if no default value. */\n    unsigned char name[4];\t/* Name of argument starts here.  The name\n\t\t\t\t * is followed by space for the default,\n\t\t\t\t * if there is one.  The actual size of this\n\t\t\t\t * field will be as large as necessary to\n\t\t\t\t * hold both name and default value.  THIS\n\t\t\t\t * MUST BE THE LAST FIELD IN THE STRUCTURE!! */\n} Arg;\n\n/*\n * The structure below defines a command procedure, which consists of\n * a collection of Tcl commands plus information about arguments and\n * variables.\n */\ntypedef struct Proc {\n    struct Interp *iPtr;\t/* Interpreter for which this command\n\t\t\t\t * is defined. */\n    unsigned char *command;\t/* Command that constitutes the body of\n\t\t\t\t * the procedure (dynamically allocated). */\n    Arg *argPtr;\t\t/* Pointer to first of procedure's formal\n\t\t\t\t * arguments, or NULL if none. */\n} Proc;\n\n/*\n * The structure below defines a command trace.  This is used to allow Tcl\n * clients to find out whenever a command is about to be executed.\n */\ntypedef struct Trace {\n    unsigned short level;\t/* Only trace commands at nesting level\n\t\t\t\t * less than or equal to this. */\n    Tcl_CmdTraceProc *proc;\t/* Procedure to call to trace command. */\n    void *clientData;\t\t/* Arbitrary value to pass to proc. */\n    struct Trace *nextPtr;\t/* Next in list of traces for this interp. */\n} Trace;\n\n/*\n * The structure below defines a frame, which is a procedure invocation.\n * These structures exist only while procedures are being executed, and\n * provide a sort of call stack.\n */\ntypedef struct CallFrame {\n    Tcl_HashTable varTable;\t/* Hash table containing all of procedure's\n\t\t\t\t * local variables. */\n    unsigned short level;\t/* Level of this procedure, for \"uplevel\"\n\t\t\t\t * purposes (i.e. corresponds to nesting of\n\t\t\t\t * callerVarPtr's, not callerPtr's).  1 means\n\t\t\t\t * outer-most procedure, 0 means top-level. */\n    int argc;\t\t\t/* This and argv below describe name and\n\t\t\t\t * arguments for this procedure invocation. */\n    unsigned char **argv;\t/* Array of arguments. */\n    struct CallFrame *callerPtr;\n\t\t\t\t/* Value of interp->framePtr when this\n\t\t\t\t * procedure was invoked (i.e. next in\n\t\t\t\t * stack of all active procedures). */\n    struct CallFrame *callerVarPtr;\n\t\t\t\t/* Value of interp->varFramePtr when this\n\t\t\t\t * procedure was invoked (i.e. determines\n\t\t\t\t * variable scoping within caller;  same\n\t\t\t\t * as callerPtr unless an \"uplevel\" command\n\t\t\t\t * or something equivalent was active in\n\t\t\t\t * the caller). */\n} CallFrame;\n\n/*\n * The structure below defines one history event (a previously-executed\n * command that can be re-executed in whole or in part).\n */\ntypedef struct {\n    unsigned char *command;\t/* String containing previously-executed\n\t\t\t\t * command. */\n    unsigned short bytesAvl;\t/* Total # of bytes available at *event (not\n\t\t\t\t * all are necessarily in use now). */\n} HistoryEvent;\n\n/*\n *----------------------------------------------------------------\n * Data structures related to history.   These are used primarily\n * in tclHistory.c\n *----------------------------------------------------------------\n */\n\n/*\n * The structure below defines a pending revision to the most recent\n * history event.  Changes are linked together into a list and applied\n * during the next call to Tcl_RecordHistory.  See the comments at the\n * beginning of tclHistory.c for information on revisions.\n */\ntypedef struct HistoryRev {\n    unsigned short firstIndex;\t/* Index of the first byte to replace in\n\t\t\t\t * current history event. */\n    unsigned short lastIndex;\t/* Index of last byte to replace in\n\t\t\t\t * current history event. */\n    unsigned short newSize;\t/* Number of bytes in newBytes. */\n    unsigned char *newBytes;\t/* Replacement for the range given by\n\t\t\t\t * firstIndex and lastIndex. */\n    struct HistoryRev *nextPtr;\t/* Next in chain of revisions to apply, or\n\t\t\t\t * NULL for end of list. */\n} HistoryRev;\n\n/*\n *----------------------------------------------------------------\n * Data structures related to files.  These are used primarily in\n * tclUnixUtil.c and tclUnixAZ.c.\n *----------------------------------------------------------------\n */\n\n/*\n * The data structure below defines an open file (or connection to\n * a process pipeline) as returned by the \"open\" command.\n */\ntypedef struct OpenFile {\n    FILE *f;\t\t\t/* Stdio file to use for reading and/or\n\t\t\t\t * writing. */\n    FILE *f2;\t\t\t/* Normally NULL.  In the special case of\n\t\t\t\t * a command pipeline with pipes for both\n\t\t\t\t * input and output, this is a stdio file\n\t\t\t\t * to use for writing to the pipeline. */\n    int readable;\t\t/* Non-zero means file may be read. */\n    int writable;\t\t/* Non-zero means file may be written. */\n    int numPids;\t\t/* If this is a connection to a process\n\t\t\t\t * pipeline, gives number of processes\n\t\t\t\t * in pidPtr array below;  otherwise it\n\t\t\t\t * is 0. */\n    int *pidPtr;\t\t/* Pointer to malloc-ed array of child\n\t\t\t\t * process ids (numPids of them), or NULL\n\t\t\t\t * if this isn't a connection to a process\n\t\t\t\t * pipeline. */\n    int errorId;\t\t/* File id of file that receives error\n\t\t\t\t * output from pipeline.  -1 means not\n\t\t\t\t * used (i.e. this is a normal file). */\n} OpenFile;\n\n/*\n *----------------------------------------------------------------\n * This structure defines an interpreter, which is a collection of\n * commands plus other state information related to interpreting\n * commands, such as variable storage.  Primary responsibility for\n * this data structure is in tclBasic.c, but almost every Tcl\n * source file uses something in here.\n *----------------------------------------------------------------\n */\ntypedef struct Command {\n    Tcl_CmdProc *proc;\t\t/* Procedure to process command. */\n    void *clientData;\t\t/* Arbitrary value to pass to proc. */\n    Tcl_CmdDeleteProc *deleteProc;\n\t\t\t\t/* Procedure to invoke when deleting\n\t\t\t\t * command. */\n} Command;\n\n#define CMD_SIZE(nameLength) ((unsigned) sizeof(Command) + nameLength - 3)\n\ntypedef struct Interp {\n\n    /*\n     * Note:  the first four fields must match exactly the fields in\n     * a Tcl_Interp struct (see tcl.h).  If you change one, be sure to\n     * change the other.\n     */\n\n    unsigned char *result;\t/* Points to result returned by last\n\t\t\t\t * command. */\n    Tcl_FreeProc *freeProc;\t/* Zero means result is statically allocated.\n\t\t\t\t * If non-zero, gives address of procedure\n\t\t\t\t * to invoke to free the result.  Must be\n\t\t\t\t * freed by Tcl_Eval before executing next\n\t\t\t\t * command. */\n    int errorLine;\t\t/* When TCL_ERROR is returned, this gives\n\t\t\t\t * the line number within the command where\n\t\t\t\t * the error occurred (1 means first line). */\n    Tcl_HashTable commandTable;\t/* Contains all of the commands currently\n\t\t\t\t * registered in this interpreter.  Indexed\n\t\t\t\t * by strings; values have type (Command *). */\n\n    /*\n     * Information related to procedures and variables.  See tclProc.c\n     * and tclvar.c for usage.\n     */\n\n    Tcl_HashTable globalTable;\t/* Contains all global variables for\n\t\t\t\t * interpreter. */\n    unsigned short numLevels;\t/* Keeps track of how many nested calls to\n\t\t\t\t * Tcl_Eval are in progress for this\n\t\t\t\t * interpreter.  It's used to delay deletion\n\t\t\t\t * of the table until all Tcl_Eval invocations\n\t\t\t\t * are completed. */\n    CallFrame *framePtr;\t/* Points to top-most in stack of all nested\n\t\t\t\t * procedure invocations.  NULL means there\n\t\t\t\t * are no active procedures. */\n    CallFrame *varFramePtr;\t/* Points to the call frame whose variables\n\t\t\t\t * are currently in use (same as framePtr\n\t\t\t\t * unless an \"uplevel\" command is being\n\t\t\t\t * executed).  NULL means no procedure is\n\t\t\t\t * active or \"uplevel 0\" is being exec'ed. */\n    ActiveVarTrace *activeTracePtr;\n\t\t\t\t/* First in list of active traces for interp,\n\t\t\t\t * or NULL if no active traces. */\n\n    /*\n     * Information related to history:\n     */\n    unsigned short numEvents;\t/* Number of previously-executed commands\n\t\t\t\t * to retain. */\n    HistoryEvent *events;\t/* Array containing numEvents entries\n\t\t\t\t * (dynamically allocated). */\n    unsigned short curEvent;\t/* Index into events of place where current\n\t\t\t\t * (or most recent) command is recorded. */\n    unsigned short curEventNum;\t/* Event number associated with the slot\n\t\t\t\t * given by curEvent. */\n    HistoryRev *revPtr;\t\t/* First in list of pending revisions. */\n    unsigned char *historyFirst; /* First char. of current command executed\n\t\t\t\t * from history module or NULL if none. */\n    unsigned short revDisables;\t/* 0 means history revision OK;  > 0 gives\n\t\t\t\t * a count of number of times revision has\n\t\t\t\t * been disabled. */\n    unsigned char *evalFirst;\t/* If TCL_RECORD_BOUNDS flag set, Tcl_Eval\n\t\t\t\t * sets this field to point to the first\n\t\t\t\t * char. of text from which the current\n\t\t\t\t * command came.  Otherwise Tcl_Eval sets\n\t\t\t\t * this to NULL. */\n    unsigned char *evalLast;\t/* Similar to evalFirst, except points to\n\t\t\t\t * last character of current command. */\n\n    /*\n     * Information used by Tcl_AppendResult to keep track of partial\n     * results.  See Tcl_AppendResult code for details.\n     */\n    unsigned char *appendResult; /* Storage space for results generated\n\t\t\t\t * by Tcl_AppendResult.  Malloc-ed.  NULL\n\t\t\t\t * means not yet allocated. */\n    unsigned short appendAvl;\t/* Total amount of space available at\n\t\t\t\t * partialResult. */\n    unsigned short appendUsed;\t/* Number of non-null bytes currently\n\t\t\t\t * stored at partialResult. */\n\n    /*\n     * Information related to files.  See tclUnixAZ.c and tclUnixUtil.c\n     * for details.\n     */\n    unsigned short numFiles;\t/* Number of entries in filePtrArray\n\t\t\t\t * below.  0 means array hasn't been\n\t\t\t\t * created yet. */\n    OpenFile **filePtrArray;\t/* Pointer to malloc-ed array of pointers\n\t\t\t\t * to information about open files.  Entry\n\t\t\t\t * N corresponds to the file with fileno N.\n\t\t\t\t * If an entry is NULL then the corresponding\n\t\t\t\t * file isn't open.  If filePtrArray is NULL\n\t\t\t\t * it means no files have been used, so even\n\t\t\t\t * stdin/stdout/stderr entries haven't been\n\t\t\t\t * setup yet. */\n    /*\n     * A cache of compiled regular expressions.  See TclCompileRegexp\n     * in tclUtil.c for details.\n     */\n#define NUM_REGEXPS 5\n    unsigned char *patterns [NUM_REGEXPS];\n\t\t\t\t/* Strings corresponding to compiled\n\t\t\t\t * regular expression patterns.  NULL\n\t\t\t\t * means that this slot isn't used.\n\t\t\t\t * Malloc-ed. */\n    unsigned short patLengths [NUM_REGEXPS];\n\t\t\t\t/* Number of non-null characters in\n\t\t\t\t * corresponding entry in patterns.\n\t\t\t\t * -1 means entry isn't used. */\n    struct _regexp_t *regexps [NUM_REGEXPS];\n\t\t\t\t/* Compiled forms of above strings.  Also\n\t\t\t\t * malloc-ed, or NULL if not in use yet. */\n\n\n    /*\n     * Miscellaneous information:\n     */\n    unsigned long cmdCount;\t/* Total number of times a command procedure\n\t\t\t\t * has been called for this interpreter. */\n    unsigned char *scriptFile;\t/* NULL means there is no nested source\n\t\t\t\t * command active;  otherwise this points to\n\t\t\t\t * the name of the file being sourced (it's\n\t\t\t\t * not malloc-ed:  it points to an argument\n\t\t\t\t * to Tcl_EvalFile. */\n    unsigned char noEval;\t/* Non-zero means no commands should actually\n\t\t\t\t * be executed:  just parse only.  Used in\n\t\t\t\t * expressions when the result is already\n\t\t\t\t * determined. */\n    unsigned char flags;\t/* Various flag bits.  See below. */\n    Trace *tracePtr;\t\t/* List of traces for this interpreter. */\n    unsigned char resultSpace [TCL_RESULT_SIZE+1];\n\t\t\t\t/* Static space for storing small results. */\n} Interp;\n\n/*\n * Flag bits for Interp structures:\n *\n * DELETED:\t\tNon-zero means the interpreter has been deleted:\n *\t\t\tdon't process any more commands for it, and destroy\n *\t\t\tthe structure as soon as all nested invocations of\n *\t\t\tTcl_Eval are done.\n * ERR_IN_PROGRESS:\tNon-zero means an error unwind is already in progress.\n *\t\t\tZero means a command proc has been invoked since last\n *\t\t\terror occured.\n * ERR_ALREADY_LOGGED:\tNon-zero means information has already been logged\n *\t\t\tin $errorInfo for the current Tcl_Eval instance,\n *\t\t\tso Tcl_Eval needn't log it (used to implement the\n *\t\t\t\"error message log\" command).\n * ERROR_CODE_SET:\tNon-zero means that Tcl_SetErrorCode has been\n *\t\t\tcalled to record information for the current\n *\t\t\terror.  Zero means Tcl_Eval must clear the\n *\t\t\terrorCode variable if an error is returned.\n */\n#define DELETED\t\t\t1\n#define ERR_IN_PROGRESS\t\t2\n#define ERR_ALREADY_LOGGED\t4\n#define ERROR_CODE_SET\t\t8\n\n/*\n *----------------------------------------------------------------\n * Data structures related to command parsing.   These are used in\n * tclParse.c and its clients.\n *----------------------------------------------------------------\n */\n\n/*\n * The following data structure is used by various parsing procedures\n * to hold information about where to store the results of parsing\n * (e.g. the substituted contents of a quoted argument, or the result\n * of a nested command).  At any given time, the space available\n * for output is fixed, but a procedure may be called to expand the\n * space available if the current space runs out.\n */\ntypedef struct ParseValue {\n    unsigned char *buffer;\t/* Address of first character in\n\t\t\t\t * output buffer. */\n    unsigned char *next;\t/* Place to store next character in\n\t\t\t\t * output buffer. */\n    unsigned char *end;\t\t/* Address of the last usable character\n\t\t\t\t * in the buffer. */\n    void (*expandProc) (struct ParseValue *pvPtr, unsigned short needed);\n\t\t\t\t/* Procedure to call when space runs out;\n\t\t\t\t * it will make more space. */\n    void *clientData;\t\t/* Arbitrary information for use of\n\t\t\t\t * expandProc. */\n} ParseValue;\n\n/*\n * Possible values returned by CHAR_TYPE:\n *\n * TCL_NORMAL -\t\tAll characters that don't have special significance\n *\t\t\tto the Tcl language.\n * TCL_SPACE -\t\tCharacter is space, tab, or return.\n * TCL_COMMAND_END -\tCharacter is newline or null or semicolon or\n *\t\t\tclose-bracket.\n * TCL_QUOTE -\t\tCharacter is a double-quote.\n * TCL_OPEN_BRACKET -\tCharacter is a \"[\".\n * TCL_OPEN_BRACE -\tCharacter is a \"{\".\n * TCL_CLOSE_BRACE -\tCharacter is a \"}\".\n * TCL_BACKSLASH -\tCharacter is a \"\\\".\n * TCL_DOLLAR -\t\tCharacter is a \"$\".\n */\n#define TCL_NORMAL\t\t0\n#define TCL_SPACE\t\t1\n#define TCL_COMMAND_END\t\t2\n#define TCL_QUOTE\t\t3\n#define TCL_OPEN_BRACKET\t4\n#define TCL_OPEN_BRACE\t\t5\n#define TCL_CLOSE_BRACE\t\t6\n#define TCL_BACKSLASH\t\t7\n#define TCL_DOLLAR\t\t8\n\n/*\n * Additional flags passed to Tcl_Eval.  See tcl.h for other flags to\n * Tcl_Eval;  these ones are only used internally by Tcl.\n *\n * TCL_RECORD_BOUNDS\tTells Tcl_Eval to record information in the\n *\t\t\tevalFirst and evalLast fields for each command\n *\t\t\texecuted directly from the string (top-level\n *\t\t\tcommands and those from command substitution).\n */\n#define TCL_RECORD_BOUNDS\t0x100\n\n/*\n * Maximum number of levels of nesting permitted in Tcl commands.\n */\n#define MAX_NESTING_DEPTH\t100\n\n/*\n *----------------------------------------------------------------\n * Procedures shared among Tcl modules but not used by the outside\n * world:\n *----------------------------------------------------------------\n */\nextern struct _regexp_t *TclCompileRegexp (Tcl_Interp *interp,\n\t\t\t    unsigned char *string);\nextern void\t\tTclCopyAndCollapse (int count, unsigned char *src,\n\t\t\t    unsigned char *dst);\nextern void\t\tTclDeleteVars (Interp *iPtr,\n\t\t\t    Tcl_HashTable *tablePtr);\nextern void\t\tTclExpandParseValue (ParseValue *pvPtr,\n\t\t\t    unsigned short needed);\nextern int\t\tTclFindElement (Tcl_Interp *interp,\n\t\t\t    unsigned char *list, unsigned char **elementPtr,\n\t\t\t    unsigned char **nextPtr, int *sizePtr, int *bracePtr);\nextern Proc *\t\tTclFindProc (Interp *iPtr,\n\t\t\t    unsigned char *procName);\nextern int\t\tTclGetFrame (Tcl_Interp *interp,\n\t\t\t    unsigned char *string, CallFrame **framePtrPtr);\nextern int\t\tTclGetListIndex (Tcl_Interp *interp,\n\t\t\t    unsigned char *string, int *indexPtr);\nextern int\t\tTclGetOpenFile (Tcl_Interp *interp,\n\t\t\t    char *string, OpenFile **filePtrPtr);\nextern Proc *\t\tTclIsProc (Command *cmdPtr);\nextern void\t\tTclMakeFileTable (Interp *iPtr,\n\t\t\t    int index);\nextern int\t\tTclParseBraces (Tcl_Interp *interp,\n\t\t\t    unsigned char *string, unsigned char **termPtr,\n\t\t\t    ParseValue *pvPtr);\nextern int\t\tTclParseNestedCmd (Tcl_Interp *interp,\n\t\t\t    unsigned char *string, int flags, unsigned char **termPtr,\n\t\t\t    ParseValue *pvPtr);\nextern int\t\tTclParseQuotes (Tcl_Interp *interp,\n\t\t\t    unsigned char *string, int termChar, int flags,\n\t\t\t    unsigned char **termPtr, ParseValue *pvPtr);\nextern int\t\tTclParseWords (Tcl_Interp *interp,\n\t\t\t    unsigned char *string, int flags, int maxWords,\n\t\t\t    unsigned char **termPtr, int *argcPtr, unsigned char **argv,\n\t\t\t    ParseValue *pvPtr);\nextern void\t\tTclSetupEnv (Tcl_Interp *interp);\nextern unsigned char *\tTclWordEnd (unsigned char *start, int nested);\nextern unsigned char *  Tcl_UnixError (Tcl_Interp *interp);\n\n/*\n *----------------------------------------------------------------\n * Command procedures in the generic core:\n *----------------------------------------------------------------\n */\nextern int\tTcl_AppendCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_ArrayCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_BreakCmd (void *clientData,\tTcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_CaseCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_CatchCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_ConcatCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_ContinueCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_ErrorCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_EvalCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_ExprCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_ForCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_ForeachCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_FormatCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_GlobalCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_HistoryCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_IfCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_IncrCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_InfoCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_JoinCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_LappendCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_LindexCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_LinsertCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_LlengthCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_ListCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_LrangeCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_LreplaceCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_LsearchCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_LsortCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_ProcCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_RegexpCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_RegsubCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_RenameCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_ReturnCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_ScanCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_SetCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_SplitCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_StringCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_TraceCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_UnsetCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_UplevelCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_UpvarCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_WhileCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_Cmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_Cmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\n\n/*\n *----------------------------------------------------------------\n * Command procedures in the UNIX core:\n *----------------------------------------------------------------\n */\nextern int\tTcl_CdCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_CloseCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_EofCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_ExecCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_ExitCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_FileCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_FlushCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_GetsCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_GlobCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_OpenCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_PutsCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_PwdCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_ReadCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_SeekCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_SourceCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_TellCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\nextern int\tTcl_TimeCmd (void *clientData, Tcl_Interp *interp, int argc, unsigned char **argv);\n"
  },
  {
    "path": "lib/libtcl/regexp.c",
    "content": "/*\n * regcomp and regexec -- regsub is elsewhere\n *\n *\tCopyright (c) 1986 by University of Toronto.\n *\tWritten by Henry Spencer.  Not derived from licensed software.\n *\n *\tPermission is granted to anyone to use this software for any\n *\tpurpose on any computer system, and to redistribute it freely,\n *\tsubject to the following restrictions:\n *\n *\t1. The author is not responsible for the consequences of use of\n *\t\tthis software, no matter how awful, even if they arise\n *\t\tfrom defects in it.\n *\n *\t2. The origin of this software must not be misrepresented, either\n *\t\tby explicit claim or by omission.\n *\n *\t3. Altered versions must be plainly marked as such, and must not\n *\t\tbe misrepresented as being the original software.\n *** THIS IS AN ALTERED VERSION.  It was altered by Serge Vakulenko,\n *** vak@cronyx.ru, on 10 Novc 2002, to make it thread-safe.\n *** THIS IS AN ALTERED VERSION.  It was altered by John Gilmore,\n *** hoptoad!gnu, on 27 Dec 1986, to add \\n as an alternative to |\n *** to assist in implementing egrep.\n *** THIS IS AN ALTERED VERSION.  It was altered by John Gilmore,\n *** hoptoad!gnu, on 27 Dec 1986, to add \\< and \\> for word-matching\n *** as in BSD grep and ex.\n *** THIS IS AN ALTERED VERSION.  It was altered by John Gilmore,\n *** hoptoad!gnu, on 28 Dec 1986, to optimize characters quoted with \\.\n *** THIS IS AN ALTERED VERSION.  It was altered by James A. Woods,\n *** ames!jaw, on 19 June 1987, to quash a regcomp() redundancy.\n *\n * Beware that some of this code is subtly aware of the way operator\n * precedence is structured in regular expressions.  Serious changes in\n * regular-expression syntax might require a total rethink.\n */\n#include <stdlib.h>\n#include <string.h>\n#include \"regexp.h\"\n#include \"regpriv.h\"\n\n/*\n * Structure for regexp \"program\".  This is essentially a linear encoding\n * of a nondeterministic finite-state machine (aka syntax charts or\n * \"railroad normal form\" in parsing technology).  Each node is an opcode\n * plus a \"next\" pointer, possibly plus an operand.  \"Next\" pointers of\n * all nodes except BRANCH implement concatenation; a \"next\" pointer with\n * a BRANCH on both ends of it is connecting two alternatives.  (Here we\n * have one of the subtle syntax dependencies:  an individual BRANCH (as\n * opposed to a collection of them) is never concatenated with anything\n * because of operator precedence.)  The operand of some types of node is\n * a literal string; for others, it is a node leading into a sub-FSM.  In\n * particular, the operand of a BRANCH node is the first node of the branch.\n * (NB this is *not* a tree structure:  the tail of the branch connects\n * to the thing following the set of BRANCHes.)  The opcodes are:\n */\n\n/* definition\tnumber\topnd?\tmeaning */\n#define\tEND\t0\t/* no\tEnd of program. */\n#define\tBOL\t1\t/* no\tMatch \"\" at beginning of line. */\n#define\tEOL\t2\t/* no\tMatch \"\" at end of line. */\n#define\tANY\t3\t/* no\tMatch any one character. */\n#define\tANYOF\t4\t/* str\tMatch any character in this string. */\n#define\tANYBUT\t5\t/* str\tMatch any character not in this string. */\n#define\tBRANCH\t6\t/* node\tMatch this alternative, or the next... */\n#define\tBACK\t7\t/* no\tMatch \"\", \"next\" ptr points backward. */\n#define\tEXACTLY\t8\t/* str\tMatch this string. */\n#define\tNOTHING\t9\t/* no\tMatch empty string. */\n#define\tSTAR\t10\t/* node\tMatch this (simple) thing 0 or more times. */\n#define\tPLUS\t11\t/* node\tMatch this (simple) thing 1 or more times. */\n#define\tWORDA\t12\t/* no\tMatch \"\" at wordchar, where prev is nonword */\n#define\tWORDZ\t13\t/* no\tMatch \"\" at nonwordchar, where prev is word */\n#define\tOPEN\t20\t/* no\tMark this point in input as start of #n. */\n\t\t\t/*\tOPEN+1 is number 1, etc. */\n#define\tCLOSE\t30\t/* no\tAnalogous to OPEN. */\n\n/*\n * Opcode notes:\n *\n * BRANCH\tThe set of branches constituting a single choice are hooked\n *\t\ttogether with their \"next\" pointers, since precedence prevents\n *\t\tanything being concatenated to any individual branch.  The\n *\t\t\"next\" pointer of the last BRANCH in a choice points to the\n *\t\tthing following the whole choice.  This is also where the\n *\t\tfinal \"next\" pointer of each individual branch points; each\n *\t\tbranch starts with the operand node of a BRANCH node.\n *\n * BACK\t\tNormal \"next\" pointers all implicitly point forward; BACK\n *\t\texists to make loop structures possible.\n *\n * STAR,PLUS\t'?', and complex '*' and '+', are implemented as circular\n *\t\tBRANCH structures using BACK.  Simple cases (one character\n *\t\tper match) are implemented with STAR and PLUS for speed\n *\t\tand to minimize recursive plunges.\n *\n * OPEN,CLOSE\t...are numbered at compile time.\n */\n\n/*\n * A node is one char of opcode followed by two chars of \"next\" pointer.\n * \"Next\" pointers are stored as two 8-bit pieces, high order first.  The\n * value is a positive offset from the opcode of the node containing it.\n * An operand, if any, simply follows the node.  (Note that much of the\n * code generation knows about this implicit relationship.)\n *\n * Using two bytes for the \"next\" pointer is vast overkill for most things,\n * but allows patterns to get big without disasters.\n */\n#define\tOP(p)\t\t(*(p))\n#define\tNEXT(p)\t\t(((*((p)+1)&0377)<<8) + (*((p)+2)&0377))\n#define\tOPERAND(p)\t((p) + 3)\n\n/*\n * Utility definitions.\n */\n#define\tISMULT(c)\t((c) == '*' || (c) == '+' || (c) == '?')\n#define ISALNUM(c)\t(((c)>='a' && (c)<='z') || \\\n\t\t\t((c)>='A' && (c)<='Z') || \\\n\t\t\t((c)>='0' && (c)<='9') || \\\n\t\t\t((c)>=0300))\n\n/*\n * Flags to be passed up and down.\n */\n#define\tHASWIDTH\t01\t/* Known never to match null string. */\n#define\tSIMPLE\t\t02\t/* Simple enough to be STAR/PLUS operand. */\n#define\tSPSTART\t\t04\t/* Starts with * or +. */\n#define\tWORST\t\t0\t/* Worst case. */\n\n/*\n * Global work variables for regcomp().\n */\ntypedef struct {\n\tunsigned const char\t*parse;\t/* Input-scan pointer. */\n\tunsigned char\tnpar;\t/* () count. */\n\tunsigned char\t*code;\t/* Code-emit pointer; &regdummy = don't. */\n\tunsigned short\tsize;\t/* Code size. */\n} compile_t;\n\nstatic unsigned char regdummy;\n\n/*\n * Forward declarations for regcomp()'s friends.\n */\nstatic unsigned char *reg (compile_t *x, unsigned char paren, unsigned char *flagp);\nstatic unsigned char *regbranch (compile_t *x, unsigned char *flagp);\nstatic unsigned char *regpiece (compile_t *x, unsigned char *flagp);\nstatic unsigned char *regatom (compile_t *x, unsigned char *flagp);\nstatic unsigned char *regnode (compile_t *x, unsigned char op);\nstatic void regc (compile_t *x, unsigned char b);\nstatic void reginsert (compile_t *x, unsigned char op, unsigned char *opnd);\nstatic unsigned char *regnext (unsigned char *p);\nstatic void regtail (unsigned char *p, unsigned char *val);\nstatic void regoptail (unsigned char *p, unsigned char *val);\n\n/*\n * Global work variables for regexec().\n */\ntypedef struct {\n\tconst unsigned char\t*input;\t/* String-input pointer. */\n\tconst unsigned char\t*bol;\t/* Beginning of input, for ^ check. */\n\tconst unsigned char\t**startp; /* Pointer to startp array. */\n\tconst unsigned char\t**endp;\t/* Ditto for endp. */\n} execute_t;\n\n/*\n * Forwards.\n */\nstatic unsigned char regtry (regexp_t *prog, execute_t *z, const unsigned char *string);\nstatic unsigned char regmatch (execute_t *z, unsigned char *prog);\nstatic unsigned short regrepeat (execute_t *z, unsigned char *p);\n\n#ifdef DEBUG_REGEXP\n#include <stdio.h>\nstatic unsigned char *regprop (unsigned char *op);\n#endif\n\n/*\n * Determine the required size.\n * On failure, returns 0.\n */\nunsigned\nregexp_size (const unsigned char *exp)\n{\n\tcompile_t x;\n\tunsigned char flags;\n\n\tif (! exp) {\n\t\t/* FAIL(\"NULL argument\"); */\n\t\treturn 0;\n\t}\n\n\tx.parse = exp;\n\tx.npar = 1;\n\tx.size = 0L;\n\tx.code = &regdummy;\n\tregc (&x, MAGIC);\n\tif (! reg (&x, 0, &flags))\n\t\treturn 0;\n\n\treturn sizeof (regexp_t) + x.size;\n}\n\n/*\n * Compile a regular expression into internal code.\n * Returns 1 on success, or 0 on failure.\n *\n * We can't allocate space until we know how big the compiled form will be,\n * but we can't compile it (and thus know how big it is) until we've got a\n * place to put the code.  So we cheat:  we compile it twice, once with code\n * generation turned off and size counting turned on, and once \"for real\".\n * This also means that we don't allocate space until we are sure that the\n * thing really will compile successfully, and we never have to move the\n * code and thus invalidate pointers into it.  (Note that it has to be in\n * one piece because free() must be able to free it all.)\n *\n * Beware that the optimization-preparation code in here knows about some\n * of the structure of the compiled regexp.\n */\nbool_t\nregexp_compile (regexp_t *r, const unsigned char *exp)\n{\n\tunsigned char *scan;\n\tunsigned char *longest;\n\tcompile_t x;\n\tunsigned short len;\n\tunsigned char flags;\n\n\tif (! r || ! exp) {\n\t\t/* FAIL(\"NULL argument\"); */\n\t\treturn 0;\n\t}\n\n\t/* Second pass: emit code. */\n\tx.parse = exp;\n\tx.npar = 1;\n\tx.code = r->program;\n\tregc (&x, MAGIC);\n\tif (! reg (&x, 0, &flags))\n\t\treturn 0;\n\n\t/* Dig out information for optimizations. */\n\tr->start = '\\0';\t/* Worst-case defaults. */\n\tr->anchor = 0;\n\tr->must = 0;\n\tr->mustlen = 0;\n\tscan = r->program+1;\t\t\t/* First BRANCH. */\n\tif (OP (regnext (scan)) == END) {\t/* Only one top-level choice. */\n\t\tscan = OPERAND(scan);\n\n\t\t/* Starting-point info. */\n\t\tif (OP(scan) == EXACTLY)\n\t\t\tr->start = *OPERAND(scan);\n\t\telse if (OP(scan) == BOL)\n\t\t\tr->anchor++;\n\n\t\t/*\n\t\t * If there's something expensive in the r.e., find the\n\t\t * longest literal string that must appear and make it the\n\t\t * `must'.  Resolve ties in favor of later strings, since\n\t\t * the start check works with the beginning of the r.e.\n\t\t * and avoiding duplication strengthens checking.  Not a\n\t\t * strong reason, but sufficient in the absence of others.\n\t\t */\n\t\tif (flags & SPSTART) {\n\t\t\tlongest = 0;\n\t\t\tlen = 0;\n\t\t\tfor (; scan; scan=regnext(scan))\n\t\t\t\tif (OP(scan) == EXACTLY &&\n\t\t\t\t    strlen (OPERAND (scan)) >= len) {\n\t\t\t\t\tlongest = OPERAND (scan);\n\t\t\t\t\tlen = strlen(OPERAND (scan));\n\t\t\t\t}\n\t\t\tr->must = longest;\n\t\t\tr->mustlen = len;\n\t\t}\n\t}\n\treturn 1;\n}\n\n/*\n - reg - regular expression, i.e. main body or parenthesized thing\n *\n * Caller must absorb opening parenthesis.\n *\n * Combining parenthesis handling with the base level of regular expression\n * is a trifle forced, but the need to tie the tails of the branches to what\n * follows makes it hard to avoid.\n */\nstatic unsigned char *\nreg (compile_t *x, unsigned char paren, unsigned char *flagp)\n{\n\tunsigned char *ret;\n\tunsigned char *br;\n\tunsigned char *ender;\n\tunsigned char parno = 0;\n\tunsigned char flags;\n\n\t*flagp = HASWIDTH;\t/* Tentatively. */\n\n\t/* Make an OPEN node, if parenthesized. */\n\tif (paren) {\n\t\tif (x->npar >= NSUBEXP) {\n\t\t\t/* FAIL(\"too many ()\"); */\n\t\t\treturn 0;\n\t\t}\n\t\tparno = x->npar;\n\t\tx->npar++;\n\t\tret = regnode (x, OPEN+parno);\n\t} else\n\t\tret = 0;\n\n\t/* Pick up the branches, linking them together. */\n\tbr = regbranch (x, &flags);\n\tif (! br)\n\t\treturn 0;\n\n\tif (ret)\n\t\tregtail (ret, br);\t/* OPEN -> first. */\n\telse\n\t\tret = br;\n\n\tif (!(flags&HASWIDTH))\n\t\t*flagp &= ~HASWIDTH;\n\t*flagp |= flags & SPSTART;\n\twhile (*x->parse == '|' || *x->parse == '\\n') {\n\t\tx->parse++;\n\t\tbr = regbranch (x, &flags);\n\t\tif (! br)\n\t\t\treturn 0;\n\n\t\tregtail (ret, br);\t/* BRANCH -> BRANCH. */\n\t\tif (!(flags & HASWIDTH))\n\t\t\t*flagp &= ~HASWIDTH;\n\t\t*flagp |= flags & SPSTART;\n\t}\n\n\t/* Make a closing node, and hook it on the end. */\n\tender = regnode (x, paren ? CLOSE+parno : END);\n\tregtail (ret, ender);\n\n\t/* Hook the tails of the branches to the closing node. */\n\tfor (br=ret; br; br=regnext(br))\n\t\tregoptail (br, ender);\n\n\t/* Check for proper termination. */\n\tif (paren && *x->parse++ != ')') {\n\t\t/* FAIL(\"unmatched ()\"); */\n\t\treturn 0;\n\t}\n\tif (! paren && *x->parse != '\\0') {\n\t\tif (*x->parse == ')') {\n\t\t\t/* FAIL(\"unmatched ()\"); */\n\t\t\treturn 0;\n\t\t}\n\t\t/* \"Can't happen\". */\n\t\t/* FAIL(\"junk on end\"); */\n\t\treturn 0;\n\t\t/* NOTREACHED */\n\t}\n\treturn ret;\n}\n\n/*\n - regbranch - one alternative of an | operator\n *\n * Implements the concatenation operator.\n */\nstatic unsigned char *\nregbranch (compile_t *x, unsigned char *flagp)\n{\n\tunsigned char *ret;\n\tunsigned char *chain;\n\tunsigned char *latest;\n\tunsigned char flags;\n\n\t*flagp = WORST;\t\t/* Tentatively. */\n\n\tret = regnode (x, BRANCH);\n\tchain = 0;\n\twhile (*x->parse != '\\0' && *x->parse != ')' &&\n\t       *x->parse != '\\n' && *x->parse != '|') {\n\t\tlatest = regpiece (x, &flags);\n\t\tif (! latest)\n\t\t\treturn 0;\n\n\t\t*flagp |= flags & HASWIDTH;\n\t\tif (! chain)\t\t/* First piece. */\n\t\t\t*flagp |= flags & SPSTART;\n\t\telse\n\t\t\tregtail (chain, latest);\n\t\tchain = latest;\n\t}\n\tif (! chain)\t\t\t/* Loop ran zero times. */\n\t\tregnode (x, NOTHING);\n\n\treturn ret;\n}\n\n/*\n - regpiece - something followed by possible [*+?]\n *\n * Note that the branching code sequences used for ? and the general cases\n * of * and + are somewhat optimized:  they use the same NOTHING node as\n * both the endmarker for their branch list and the body of the last branch.\n * It might seem that this node could be dispensed with entirely, but the\n * endmarker role is not redundant.\n */\nstatic unsigned char *\nregpiece (compile_t *x, unsigned char *flagp)\n{\n\tunsigned char *ret;\n\tunsigned char op;\n\tunsigned char *next;\n\tunsigned char flags;\n\n\tret = regatom (x, &flags);\n\tif (! ret)\n\t\treturn 0;\n\n\top = *x->parse;\n\tif (! ISMULT (op)) {\n\t\t*flagp = flags;\n\t\treturn ret;\n\t}\n\n\tif (!(flags&HASWIDTH) && op != '?') {\n\t\t/* FAIL(\"*+ operand could be empty\"); */\n\t\treturn 0;\n\t}\n\t*flagp = (op != '+') ? (WORST | SPSTART) : (WORST | HASWIDTH);\n\n\tif (op == '*' && (flags&SIMPLE))\n\t\treginsert (x, STAR, ret);\n\telse if (op == '*') {\n\t\t/* Emit x* as (x&|), where & means \"self\". */\n\t\treginsert (x, BRANCH, ret);\t\t/* Either x */\n\t\tregoptail (ret, regnode (x, BACK));\t/* and loop */\n\t\tregoptail (ret, ret);\t\t\t/* back */\n\t\tregtail (ret, regnode (x, BRANCH));\t/* or */\n\t\tregtail (ret, regnode (x, NOTHING));\t/* null. */\n\t} else if (op == '+' && (flags&SIMPLE))\n\t\treginsert (x, PLUS, ret);\n\telse if (op == '+') {\n\t\t/* Emit x+ as x(&|), where & means \"self\". */\n\t\tnext = regnode (x, BRANCH);\t\t/* Either */\n\t\tregtail (ret, next);\n\t\tregtail (regnode (x, BACK), ret);\t/* loop back */\n\t\tregtail (next, regnode (x, BRANCH));\t/* or */\n\t\tregtail (ret, regnode (x, NOTHING));\t/* null. */\n\t} else if (op == '?') {\n\t\t/* Emit x? as (x|) */\n\t\treginsert (x, BRANCH, ret);\t\t/* Either x */\n\t\tregtail (ret, regnode (x, BRANCH));\t/* or */\n\t\tnext = regnode (x, NOTHING);\t\t/* null. */\n\t\tregtail (ret, next);\n\t\tregoptail (ret, next);\n\t}\n\tx->parse++;\n\tif (ISMULT (*x->parse)) {\n\t\t/* FAIL(\"nested *?+\"); */\n\t\treturn 0;\n\t}\n\treturn ret;\n}\n\n/*\n - regatom - the lowest level\n *\n * Optimization:  gobbles an entire sequence of ordinary characters so that\n * it can turn them into a single node, which is smaller to store and\n * faster to run.  Backslashed characters are exceptions, each becoming a\n * separate node; the code is simpler that way and it's not worth fixing.\n */\nstatic unsigned char *\nregatom (compile_t *x, unsigned char *flagp)\n{\n\tunsigned char *ret;\n\tunsigned char flags;\n\n\t*flagp = WORST;\t\t/* Tentatively. */\n\n\tswitch (*x->parse++) {\n\t/* FIXME: these chars only have meaning at beg/end of pat? */\n\tcase '^':\n\t\tret = regnode (x, BOL);\n\t\tbreak;\n\tcase '$':\n\t\tret = regnode (x, EOL);\n\t\tbreak;\n\tcase '.':\n\t\tret = regnode (x, ANY);\n\t\t*flagp |= HASWIDTH | SIMPLE;\n\t\tbreak;\n\tcase '[': {\n\t\t\tunsigned char class, classend;\n\n\t\t\tif (*x->parse == '^') {\t/* Complement of range. */\n\t\t\t\tret = regnode (x, ANYBUT);\n\t\t\t\tx->parse++;\n\t\t\t} else\n\t\t\t\tret = regnode (x, ANYOF);\n\t\t\tif (*x->parse == ']' || *x->parse == '-')\n\t\t\t\tregc (x, *x->parse++);\n\t\t\twhile (*x->parse != '\\0' && *x->parse != ']') {\n\t\t\t\tif (*x->parse == '-') {\n\t\t\t\t\tx->parse++;\n\t\t\t\t\tif (*x->parse == ']' || *x->parse == '\\0')\n\t\t\t\t\t\tregc (x, '-');\n\t\t\t\t\telse {\n\t\t\t\t\t\tclass = UCHARAT(x->parse-2);\n\t\t\t\t\t\tclassend = UCHARAT(x->parse);\n\t\t\t\t\t\tif (class > classend) {\n\t\t\t\t\t\t\t/* FAIL(\"invalid [] range\"); */\n\t\t\t\t\t\t\treturn 0;\n\t\t\t\t\t\t}\n\t\t\t\t\t\tfor (class++; class <= classend; class++)\n\t\t\t\t\t\t\tregc (x, class);\n\t\t\t\t\t\tx->parse++;\n\t\t\t\t\t}\n\t\t\t\t} else\n\t\t\t\t\tregc (x, *x->parse++);\n\t\t\t}\n\t\t\tregc (x, '\\0');\n\t\t\tif (*x->parse != ']') {\n\t\t\t\t/* FAIL(\"unmatched []\"); */\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t\tx->parse++;\n\t\t\t*flagp |= HASWIDTH | SIMPLE;\n\t\t}\n\t\tbreak;\n\tcase '(':\n\t\tret = reg (x, 1, &flags);\n\t\tif (! ret)\n\t\t\treturn 0;\n\t\t*flagp |= flags & (HASWIDTH | SPSTART);\n\t\tbreak;\n\tcase '\\0':\n\tcase '|':\n\tcase '\\n':\n\tcase ')':\n\t\t/* Supposed to be caught earlier. */\n\t\t/* FAIL(\"internal urp\"); */\n\t\treturn 0;\n\tcase '?':\n\tcase '+':\n\tcase '*':\n\t\t/* FAIL(\"?+* follows nothing\"); */\n\t\treturn 0;\n\tcase '\\\\':\n\t\tswitch (*x->parse++) {\n\t\tcase '\\0':\n\t\t\t/* FAIL(\"trailing \\\\\"); */\n\t\t\treturn 0;\n\t\tcase '<':\n\t\t\tret = regnode (x, WORDA);\n\t\t\tbreak;\n\t\tcase '>':\n\t\t\tret = regnode (x, WORDZ);\n\t\t\tbreak;\n\t\t/* FIXME: Someday handle \\1, \\2, ... */\n\t\tdefault:\n\t\t\t/* Handle general quoted chars in exact-match routine */\n\t\t\tgoto de_fault;\n\t\t}\n\t\tbreak;\n\tde_fault:\n\tdefault:\n\t\t/*\n\t\t * Encode a string of characters to be matched exactly.\n\t\t *\n\t\t * This is a bit tricky due to quoted chars and due to\n\t\t * '*', '+', and '?' taking the SINGLE char previous\n\t\t * as their operand.\n\t\t *\n\t\t * On entry, the char at regparse[-1] is going to go\n\t\t * into the string, no matter what it is.  (It could be\n\t\t * following a \\ if we are entered from the '\\' case.)\n\t\t *\n\t\t * Basic idea is to pick up a good char in  ch  and\n\t\t * examine the next char.  If it's *+? then we twiddle.\n\t\t * If it's \\ then we frozzle.  If it's other magic char\n\t\t * we push  ch  and terminate the string.  If none of the\n\t\t * above, we push  ch  on the string and go around again.\n\t\t *\n\t\t * `Regprev' is used to remember where \"the current char\"\n\t\t * starts in the string, if due to a *+? we need to back\n\t\t * up and put the current char in a separate, 1-char, string.\n\t\t * When `regprev' is NULL,  ch  is the only char in the\n\t\t * string; this is used in *+? handling, and in setting\n\t\t * flags |= SIMPLE at the end.\n\t\t */\n\t\t{\n\t\t\tconst unsigned char *regprev;\n\t\t\tunsigned char ch;\n\n\t\t\tx->parse--;\t\t\t/* Look at cur char */\n\t\t\tret = regnode (x, EXACTLY);\n\t\t\tregprev = 0;\n\t\t\tfor (;;) {\n\t\t\t\tch = *x->parse++;\t/* Get current char */\n\t\t\t\tswitch (*x->parse) {\t/* look at next one */\n\n\t\t\t\tdefault:\n\t\t\t\t\tregc (x, ch);\t/* Add cur to string */\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase '.': case '[': case '(':\n\t\t\t\tcase ')': case '|': case '\\n':\n\t\t\t\tcase '$': case '^':\n\t\t\t\tcase '\\0':\n\t\t\t\t/* FIXME, $ and ^ should not always be magic */\n\t\t\t\tmagic:\n\t\t\t\t\tregc (x, ch);\t/* dump cur char */\n\t\t\t\t\tgoto done;\t/* and we are done */\n\n\t\t\t\tcase '?': case '+': case '*':\n\t\t\t\t\tif (! regprev) \t/* If just ch in str, */\n\t\t\t\t\t\tgoto magic;\t/* use it */\n\t\t\t\t\t/* End mult-char string one early */\n\t\t\t\t\tx->parse = regprev; /* Back up parse */\n\t\t\t\t\tgoto done;\n\n\t\t\t\tcase '\\\\':\n\t\t\t\t\tregc (x, ch);\t/* Cur char OK */\n\t\t\t\t\tswitch (x->parse[1]){ /* Look after \\ */\n\t\t\t\t\tcase '\\0':\n\t\t\t\t\tcase '<':\n\t\t\t\t\tcase '>':\n\t\t\t\t\t/* FIXME: Someday handle \\1, \\2, ... */\n\t\t\t\t\t\tgoto done; /* Not quoted */\n\t\t\t\t\tdefault:\n\t\t\t\t\t\t/* Backup point is \\, scan\t\t\t\t\t\t\t * point is after it. */\n\t\t\t\t\t\tregprev = x->parse;\n\t\t\t\t\t\tx->parse++;\n\t\t\t\t\t\tcontinue;\t/* NOT break; */\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tregprev = x->parse;\t/* Set backup point */\n\t\t\t}\n\t\tdone:\n\t\t\tregc (x, '\\0');\n\t\t\t*flagp |= HASWIDTH;\n\t\t\tif (! regprev)\t\t/* One char? */\n\t\t\t\t*flagp |= SIMPLE;\n\t\t}\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\n/*\n - regnode - emit a node\n */\nstatic unsigned char *\t\t\t/* Location. */\nregnode (compile_t *x, unsigned char op)\n{\n\tunsigned char *ret;\n\tunsigned char *ptr;\n\n\tret = x->code;\n\tif (ret == &regdummy) {\n\t\tx->size += 3;\n\t\treturn ret;\n\t}\n\n\tptr = ret;\n\t*ptr++ = op;\n\t*ptr++ = '\\0';\t\t/* Null \"next\" pointer. */\n\t*ptr++ = '\\0';\n\tx->code = ptr;\n\n\treturn ret;\n}\n\n/*\n - regc - emit (if appropriate) a byte of code\n */\nstatic void\nregc (compile_t *x, unsigned char b)\n{\n\tif (x->code != &regdummy)\n\t\t*x->code++ = b;\n\telse\n\t\tx->size++;\n}\n\n/*\n - reginsert - insert an operator in front of already-emitted operand\n *\n * Means relocating the operand.\n */\nstatic void\nreginsert (compile_t *x, unsigned char op, unsigned char *opnd)\n{\n\tunsigned char *src;\n\tunsigned char *dst;\n\tunsigned char *place;\n\n\tif (x->code == &regdummy) {\n\t\tx->size += 3;\n\t\treturn;\n\t}\n\n\tsrc = x->code;\n\tx->code += 3;\n\tdst = x->code;\n\twhile (src > opnd)\n\t\t*--dst = *--src;\n\n\tplace = opnd;\t\t/* Op node, where operand used to be. */\n\t*place++ = op;\n\t*place++ = '\\0';\n\t*place++ = '\\0';\n}\n\n/*\n - regtail - set the next-pointer at the end of a node chain\n */\nstatic void\nregtail (unsigned char *p, unsigned char *val)\n{\n\tunsigned char *scan;\n\tunsigned char *temp;\n\tunsigned short offset;\n\n\tif (p == &regdummy)\n\t\treturn;\n\n\t/* Find last node. */\n\tscan = p;\n\tfor (;;) {\n\t\ttemp = regnext (scan);\n\t\tif (! temp)\n\t\t\tbreak;\n\t\tscan = temp;\n\t}\n\n\tif (OP(scan) == BACK)\n\t\toffset = scan - val;\n\telse\n\t\toffset = val - scan;\n\t*(scan+1) = (offset >> 8) & 0377;\n\t*(scan+2) = offset & 0377;\n}\n\n/*\n - regoptail - regtail on operand of first argument; nop if operandless\n */\nstatic void\nregoptail (unsigned char *p, unsigned char *val)\n{\n\t/* \"Operandless\" and \"op != BRANCH\" are synonymous in practice. */\n\tif (! p || p == &regdummy || OP(p) != BRANCH)\n\t\treturn;\n\tregtail (OPERAND(p), val);\n}\n\n/*\n * regexec and friends\n */\n\n/*\n * Match a regular expression against a string.\n * Returns 1 on success, or 0 on failure.\n */\nbool_t\nregexp_execute (regexp_t *prog, const unsigned char *string)\n{\n\texecute_t z;\n\tconst unsigned char *s;\n\n\t/* Be paranoid... */\n\tif (! prog || ! string) {\n\t\t/* regerror(\"NULL parameter\"); */\n\t\treturn 0;\n\t}\n\n\t/* Check validity of program. */\n\tif (UCHARAT (prog->program) != MAGIC) {\n\t\t/* regerror(\"corrupted program\"); */\n\t\treturn 0;\n\t}\n\n\t/* If there is a \"must appear\" string, look for it. */\n\tif (prog->must) {\n\t\ts = string;\n\t\twhile ((s = strchr (s, prog->must[0])) != 0) {\n\t\t\tif (strncmp (s, prog->must, prog->mustlen) == 0)\n\t\t\t\tbreak;\t/* Found it. */\n\t\t\ts++;\n\t\t}\n\t\tif (! s)\t/* Not present. */\n\t\t\treturn 0;\n\t}\n\n\t/* Mark beginning of line for ^ . */\n\tz.bol = string;\n\n\t/* Simplest case:  anchored match need be tried only once. */\n\tif (prog->anchor)\n\t\treturn regtry (prog, &z, string);\n\n\t/* Messy cases:  unanchored match. */\n\ts = string;\n\tif (prog->start != '\\0')\n\t\t/* We know what char it must start with. */\n\t\twhile ((s = strchr (s, prog->start)) != 0) {\n\t\t\tif (regtry (prog, &z, s))\n\t\t\t\treturn 1;\n\t\t\ts++;\n\t\t}\n\telse\n\t\t/* We don't -- general case. */\n\t\tdo {\n\t\t\tif (regtry (prog, &z, s))\n\t\t\t\treturn 1;\n\t\t} while (*s++ != '\\0');\n\n\t/* Failure. */\n\treturn 0;\n}\n\n/*\n - regtry - try match at specific point\n */\nstatic unsigned char\t\t\t/* 0 failure, 1 success */\nregtry (regexp_t *prog, execute_t *z, const unsigned char *string)\n{\n\tunsigned char i;\n\tconst unsigned char **sp;\n\tconst unsigned char **ep;\n\n\tz->input = string;\n\tz->startp = prog->startp;\n\tz->endp = prog->endp;\n\n\tsp = prog->startp;\n\tep = prog->endp;\n\tfor (i=NSUBEXP; i>0; i--) {\n\t\t*sp++ = 0;\n\t\t*ep++ = 0;\n\t}\n\tif (regmatch (z, prog->program + 1)) {\n\t\tprog->startp[0] = string;\n\t\tprog->endp[0] = z->input;\n\t\treturn 1;\n\t}\n\treturn 0;\n}\n\n/*\n - regmatch - main matching routine\n *\n * Conceptually the strategy is simple:  check to see whether the current\n * node matches, call self recursively to see whether the rest matches,\n * and then act accordingly.  In practice we make some effort to avoid\n * recursion, in particular by going through \"ordinary\" nodes (that don't\n * need to know whether the rest of the match failed) by a loop instead of\n * by recursion.\n */\nstatic unsigned char\t\t\t/* 0 failure, 1 success */\nregmatch (execute_t *z, unsigned char *prog)\n{\n\tunsigned char *scan;\t\t/* Current node. */\n\tunsigned char *next;\t\t/* Next node. */\n\n\tscan = prog;\n#ifdef DEBUG_REGEXP\n\tif (scan && regsub_narrate)\n\t\tfprintf (stderr, \"%s(\\n\", regprop (scan));\n#endif\n\twhile (scan) {\n#ifdef DEBUG_REGEXP\n\t\tif (regsub_narrate)\n\t\t\tfprintf (stderr, \"%s...\\n\", regprop (scan));\n#endif\n\t\tnext = regnext (scan);\n\n\t\tswitch (OP(scan)) {\n\t\tcase BOL:\n\t\t\tif (z->input != z->bol)\n\t\t\t\treturn 0;\n\t\t\tbreak;\n\t\tcase EOL:\n\t\t\tif (*z->input != '\\0')\n\t\t\t\treturn 0;\n\t\t\tbreak;\n\t\tcase WORDA:\n\t\t\t/* Must be looking at a letter, digit, or _ */\n\t\t\tif ((!ISALNUM((unsigned char)*z->input)) && *z->input != '_')\n\t\t\t\treturn 0;\n\t\t\t/* Prev must be BOL or nonword */\n\t\t\tif (z->input > z->bol &&\n\t\t\t    (ISALNUM((unsigned char)z->input[-1]) || z->input[-1] == '_'))\n\t\t\t\treturn 0;\n\t\t\tbreak;\n\t\tcase WORDZ:\n\t\t\t/* Must be looking at non letter, digit, or _ */\n\t\t\tif (ISALNUM((unsigned char)*z->input) || *z->input == '_')\n\t\t\t\treturn 0;\n\t\t\t/* We don't care what the previous char was */\n\t\t\tbreak;\n\t\tcase ANY:\n\t\t\tif (*z->input == '\\0')\n\t\t\t\treturn 0;\n\t\t\tz->input++;\n\t\t\tbreak;\n\t\tcase EXACTLY: {\n\t\t\t\tunsigned short len;\n\t\t\t\tunsigned char *opnd;\n\n\t\t\t\topnd = OPERAND(scan);\n\t\t\t\t/* Inline the first character, for speed. */\n\t\t\t\tif (*opnd != *z->input)\n\t\t\t\t\treturn 0;\n\t\t\t\tlen = strlen(opnd);\n\t\t\t\tif (len > 1 && strncmp(opnd, z->input, len) != 0)\n\t\t\t\t\treturn 0;\n\t\t\t\tz->input += len;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase ANYOF:\n \t\t\tif (*z->input == '\\0' || strchr(OPERAND(scan), *z->input) == 0)\n\t\t\t\treturn 0;\n\t\t\tz->input++;\n\t\t\tbreak;\n\t\tcase ANYBUT:\n \t\t\tif (*z->input == '\\0' || strchr(OPERAND(scan), *z->input) != 0)\n\t\t\t\treturn 0;\n\t\t\tz->input++;\n\t\t\tbreak;\n\t\tcase NOTHING:\n\t\t\tbreak;\n\t\tcase BACK:\n\t\t\tbreak;\n\t\tcase OPEN+1:\n\t\tcase OPEN+2:\n\t\tcase OPEN+3:\n\t\tcase OPEN+4:\n\t\tcase OPEN+5:\n\t\tcase OPEN+6:\n\t\tcase OPEN+7:\n\t\tcase OPEN+8:\n\t\tcase OPEN+9: {\n\t\t\t\tunsigned char no;\n\t\t\t\tconst unsigned char *save;\n\n\t\t\t\tno = OP(scan) - OPEN;\n\t\t\t\tsave = z->input;\n\n\t\t\t\tif (regmatch (z, next)) {\n\t\t\t\t\t/*\n\t\t\t\t\t * Don't set startp if some later\n\t\t\t\t\t * invocation of the same parentheses\n\t\t\t\t\t * already has.\n\t\t\t\t\t */\n\t\t\t\t\tif (! z->startp[no])\n\t\t\t\t\t\tz->startp[no] = save;\n\t\t\t\t\treturn 1;\n\t\t\t\t}\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase CLOSE+1:\n\t\tcase CLOSE+2:\n\t\tcase CLOSE+3:\n\t\tcase CLOSE+4:\n\t\tcase CLOSE+5:\n\t\tcase CLOSE+6:\n\t\tcase CLOSE+7:\n\t\tcase CLOSE+8:\n\t\tcase CLOSE+9: {\n\t\t\t\tunsigned char no;\n\t\t\t\tconst unsigned char *save;\n\n\t\t\t\tno = OP(scan) - CLOSE;\n\t\t\t\tsave = z->input;\n\n\t\t\t\tif (regmatch (z, next)) {\n\t\t\t\t\t/*\n\t\t\t\t\t * Don't set endp if some later\n\t\t\t\t\t * invocation of the same parentheses\n\t\t\t\t\t * already has.\n\t\t\t\t\t */\n\t\t\t\t\tif (! z->endp[no])\n\t\t\t\t\t\tz->endp[no] = save;\n\t\t\t\t\treturn 1;\n\t\t\t\t}\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase BRANCH: {\n\t\t\t\tconst unsigned char *save;\n\n\t\t\t\tif (OP(next) != BRANCH)\t\t/* No choice. */\n\t\t\t\t\tnext = OPERAND(scan);\t/* Avoid recursion. */\n\t\t\t\telse {\n\t\t\t\t\tdo {\n\t\t\t\t\t\tsave = z->input;\n\t\t\t\t\t\tif (regmatch (z, OPERAND(scan)))\n\t\t\t\t\t\t\treturn 1;\n\t\t\t\t\t\tz->input = save;\n\t\t\t\t\t\tscan = regnext (scan);\n\t\t\t\t\t} while (scan && OP(scan) == BRANCH);\n\t\t\t\t\treturn 0;\n\t\t\t\t\t/* NOTREACHED */\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\t\tcase STAR:\n\t\tcase PLUS: {\n\t\t\t\tunsigned char nextch;\n\t\t\t\tunsigned short no, min;\n\t\t\t\tconst unsigned char *save;\n\n\t\t\t\t/*\n\t\t\t\t * Lookahead to avoid useless match attempts\n\t\t\t\t * when we know what character comes next.\n\t\t\t\t */\n\t\t\t\tnextch = '\\0';\n\t\t\t\tif (OP(next) == EXACTLY)\n\t\t\t\t\tnextch = *OPERAND(next);\n\t\t\t\tmin = (OP(scan) == STAR) ? 0 : 1;\n\t\t\t\tsave = z->input;\n\t\t\t\tno = regrepeat (z, OPERAND(scan));\n\t\t\t\twhile (no >= min) {\n\t\t\t\t\t/* If it could work, try it. */\n\t\t\t\t\tif (nextch == '\\0' || *z->input == nextch)\n\t\t\t\t\t\tif (regmatch (z, next))\n\t\t\t\t\t\t\treturn 1;\n\t\t\t\t\t/* Couldn't or didn't -- back up. */\n\t\t\t\t\tno--;\n\t\t\t\t\tz->input = save + no;\n\t\t\t\t}\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase END:\n\t\t\treturn 1;\t/* Success! */\n\t\tdefault:\n\t\t\t/* regerror(\"memory corruption\"); */\n\t\t\treturn 0;\n\t\t}\n\n\t\tscan = next;\n\t}\n\n\t/*\n\t * We get here only if there's trouble -- normally \"case END\" is\n\t * the terminating point.\n\t */\n\t/* regerror(\"corrupted pointers\"); */\n\treturn 0;\n}\n\n/*\n - regrepeat - repeatedly match something simple, report how many\n */\nstatic unsigned short\nregrepeat (execute_t *z, unsigned char *p)\n{\n\tunsigned short count = 0;\n\tconst unsigned char *scan;\n\tunsigned char *opnd;\n\n\tscan = z->input;\n\topnd = OPERAND(p);\n\tswitch (OP(p)) {\n\tcase ANY:\n\t\tcount = strlen(scan);\n\t\tscan += count;\n\t\tbreak;\n\tcase EXACTLY:\n\t\twhile (*opnd == *scan) {\n\t\t\tcount++;\n\t\t\tscan++;\n\t\t}\n\t\tbreak;\n\tcase ANYOF:\n\t\twhile (*scan != '\\0' && strchr(opnd, *scan) != 0) {\n\t\t\tcount++;\n\t\t\tscan++;\n\t\t}\n\t\tbreak;\n\tcase ANYBUT:\n\t\twhile (*scan != '\\0' && strchr(opnd, *scan) == 0) {\n\t\t\tcount++;\n\t\t\tscan++;\n\t\t}\n\t\tbreak;\n\tdefault:\t\t/* Oh dear.  Called inappropriately. */\n\t\t/* regerror(\"internal foulup\"); */\n\t\tcount = 0;\t/* Best compromise. */\n\t\tbreak;\n\t}\n\tz->input = scan;\n\n\treturn count;\n}\n\n/*\n - regnext - dig the \"next\" pointer out of a node\n */\nstatic unsigned char *\nregnext (unsigned char *p)\n{\n\tunsigned short offset;\n\n\tif (p == &regdummy)\n\t\treturn 0;\n\n\toffset = NEXT(p);\n\tif (offset == 0)\n\t\treturn 0;\n\n\tif (OP(p) == BACK)\n\t\treturn p - offset;\n\telse\n\t\treturn p + offset;\n}\n\n#ifdef DEBUG_REGEXP\n\n/*\n * Dump a regexp onto stdout in vaguely comprehensible form\n */\nvoid\nregsub_dump (regexp_t *r)\n{\n\tunsigned char *s;\n\tunsigned char op = EXACTLY;\t/* Arbitrary non-END op. */\n\tunsigned char *next;\n\n\ts = r->program + 1;\n\twhile (op != END) {\t/* While that wasn't END last time... */\n\t\top = OP(s);\n\t\tprintf(\"%2d%s\", s-r->program, regprop (s));\t/* Where, what. */\n\t\tnext = regnext (s);\n\t\tif (! next)\t\t/* Next ptr. */\n\t\t\tprintf(\"(0)\");\n\t\telse\n\t\t\tprintf(\"(%d)\", (s-r->program)+(next-s));\n\t\ts += 3;\n\t\tif (op == ANYOF || op == ANYBUT || op == EXACTLY) {\n\t\t\t/* Literal string, where present. */\n\t\t\twhile (*s != '\\0') {\n\t\t\t\tputchar(*s);\n\t\t\t\ts++;\n\t\t\t}\n\t\t\ts++;\n\t\t}\n\t\tputchar('\\n');\n\t}\n\n\t/* Header fields of interest. */\n\tif (r->start != '\\0')\n\t\tprintf(\"start `%c' \", r->start);\n\tif (r->anchor)\n\t\tprintf(\"anchored \");\n\tif (r->must)\n\t\tprintf(\"must have \\\"%s\\\"\", r->must);\n\tprintf(\"\\n\");\n}\n\n/*\n - regprop - printable representation of opcode\n */\nstatic unsigned char *\nregprop (unsigned char *op)\n{\n\tunsigned char *p;\n\tstatic unsigned char buf[50];\n\n\tstrcpy (buf, \":\");\n\n\tswitch (OP(op)) {\n\tcase BOL:\tp = \"BOL\";\tbreak;\n\tcase EOL:\tp = \"EOL\";\tbreak;\n\tcase ANY:\tp = \"ANY\";\tbreak;\n\tcase ANYOF:\tp = \"ANYOF\";\tbreak;\n\tcase ANYBUT:\tp = \"ANYBUT\";\tbreak;\n\tcase BRANCH:\tp = \"BRANCH\";\tbreak;\n\tcase EXACTLY:\tp = \"EXACTLY\";\tbreak;\n\tcase NOTHING:\tp = \"NOTHING\";\tbreak;\n\tcase BACK:\tp = \"BACK\";\tbreak;\n\tcase END:\tp = \"END\";\tbreak;\n\tcase STAR:\tp = \"STAR\";\tbreak;\n\tcase PLUS:\tp = \"PLUS\";\tbreak;\n\tcase WORDA:\tp = \"WORDA\";\tbreak;\n\tcase WORDZ:\tp = \"WORDZ\";\tbreak;\n\tcase OPEN+1:\n\tcase OPEN+2:\n\tcase OPEN+3:\n\tcase OPEN+4:\n\tcase OPEN+5:\n\tcase OPEN+6:\n\tcase OPEN+7:\n\tcase OPEN+8:\n\tcase OPEN+9:\n\t\tsprintf (buf + strlen (buf), \"OPEN%d\", OP(op) - OPEN);\n\t\tp = 0;\n\t\tbreak;\n\tcase CLOSE+1:\n\tcase CLOSE+2:\n\tcase CLOSE+3:\n\tcase CLOSE+4:\n\tcase CLOSE+5:\n\tcase CLOSE+6:\n\tcase CLOSE+7:\n\tcase CLOSE+8:\n\tcase CLOSE+9:\n\t\tsprintf (buf + strlen (buf), \"CLOSE%d\", OP(op) - CLOSE);\n\t\tp = 0;\n\t\tbreak;\n\tdefault:\n\t\t/* corrupted opcode */\n\t\tp = \"???\";\n\t\tbreak;\n\t}\n\tif (p)\n\t\tstrcat (buf, p);\n\treturn buf;\n}\n#endif\n"
  },
  {
    "path": "lib/libtcl/regexp.h",
    "content": "/*\n * Definitions etc. for regexp(3) routines.\n */\ntypedef struct _regexp_t regexp_t;\ntypedef int bool_t;\n\n/*\n * Determine the required size.\n * On failure, returns 0.\n */\nunsigned regexp_size (const unsigned char *pattern);\n\n/*\n * Compile a regular expression into internal code.\n * Returns 1 on success, or 0 on failure.\n */\nbool_t regexp_compile (regexp_t *re, const unsigned char *pattern);\n\n/*\n * Match a regular expression against a string.\n * Returns 1 on success, or 0 on failure.\n */\nbool_t regexp_execute (regexp_t *re, const unsigned char *str);\n\n/*\n * Perform substitutions after a regexp match.\n * Returns 1 on success, or 0 on failure.\n */\nbool_t regexp_substitute (const regexp_t *re,\n\tconst unsigned char *src, unsigned char *dst);\n"
  },
  {
    "path": "lib/libtcl/regpriv.h",
    "content": "/*\n * Internal definitions for regexp(3) routines.\n */\n#define NSUBEXP\t\t10\n\n/*\n * The \"internal use only\" fields in regexp.h are present to pass info from\n * compile to execute that permits the execute phase to run lots faster on\n * simple cases.  They are:\n *\n * start\tchar that must begin a match; '\\0' if none obvious\n * anchor\tis the match anchored (at beginning-of-line only)?\n * must\t\tstring (pointer into program) that match must include, or NULL\n * mustlen\tlength of `must' string\n *\n * `Start' and `anchor' permit very fast decisions on suitable starting points\n * for a match, cutting down the work a lot.  `Must' permits fast rejection\n * of lines that cannot possibly match.  The `must' tests are costly enough\n * that regcomp() supplies a `must' only if the r.e. contains something\n * potentially expensive (at present, the only such thing detected is * or +\n * at the start of the r.e., which can involve a lot of backup).  `Mustlen' is\n * supplied because the test in regexec() needs it and regcomp() is computing\n * it anyway.\n */\nstruct _regexp_t {\n\tconst unsigned char\t*startp [NSUBEXP];\n\tconst unsigned char\t*endp [NSUBEXP];\n\tunsigned char\t\tstart;\n\tunsigned char\t\tanchor;\n\tunsigned char\t\t*must;\n\tunsigned short\t\tmustlen;\n\tunsigned char\t\tprogram [1];\n};\n\n/*\n * Utility definitions.\n */\n#define\tUCHARAT(p)\t(*(unsigned char*)(p))\n\n/*\n * The first byte of the regexp internal \"program\" is actually this magic\n * number; the start node begins in the second byte.\n */\n#define\tMAGIC\t\t0234\n\n#ifdef DEBUG_REGEXP\nunsigned char regsub_narrate;\nvoid regsub_dump (regexp_t *r);\n#endif\n"
  },
  {
    "path": "lib/libtcl/regsub.c",
    "content": "/*\n *\tCopyright (c) 1986 by University of Toronto.\n *\tWritten by Henry Spencer.  Not derived from licensed software.\n *\n *\tPermission is granted to anyone to use this software for any\n *\tpurpose on any computer system, and to redistribute it freely,\n *\tsubject to the following restrictions:\n *\n *\t1. The author is not responsible for the consequences of use of\n *\t\tthis software, no matter how awful, even if they arise\n *\t\tfrom defects in it.\n *\n *\t2. The origin of this software must not be misrepresented, either\n *\t\tby explicit claim or by omission.\n *\n *\t3. Altered versions must be plainly marked as such, and must not\n *\t\tbe misrepresented as being the original software.\n */\n#include <stdlib.h>\n#include <string.h>\n#include \"regexp.h\"\n#include \"regpriv.h\"\n\n/*\n * Perform substitutions after a regexp match.\n * Returns 1 on success, or 0 on failure.\n */\nbool_t\nregexp_substitute (const regexp_t *prog, const unsigned char *src, unsigned char *dst)\n{\n\tunsigned char c;\n\tunsigned char no;\n\tunsigned short len;\n\n\tif (! prog || ! src || ! dst) {\n\t\t/* regerror(\"NULL parm to regsub\"); */\n\t\treturn 0;\n\t}\n\tif (UCHARAT(prog->program) != MAGIC) {\n\t\t/* regerror(\"damaged regexp fed to regsub\"); */\n\t\treturn 0;\n\t}\n\n\twhile ((c = *src++) != '\\0') {\n\t\tif (c == '&')\n\t\t\tno = 0;\n\t\telse if (c == '\\\\' && '0' <= *src && *src <= '9')\n\t\t\tno = *src++ - '0';\n\t\telse\n\t\t\tno = 10;\n \t\tif (no > 9) {\n\t\t\t/* Ordinary character. */\n \t\t\tif (c == '\\\\' && (*src == '\\\\' || *src == '&'))\n \t\t\t\tc = *src++;\n \t\t\t*dst++ = c;\n \t\t} else if (prog->startp[no] && prog->endp[no]) {\n\t\t\tlen = prog->endp[no] - prog->startp[no];\n\t\t\tstrncpy (dst, prog->startp[no], len);\n\t\t\tdst += len;\n\t\t\tif (len != 0 && dst[-1] == '\\0') {\n\t\t\t\t/* strncpy hit NUL. */\n\t\t\t\t/* regerror(\"damaged match string\"); */\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\t}\n\t*dst = '\\0';\n\treturn 1;\n}\n"
  },
  {
    "path": "lib/libtcl/tclassem.c",
    "content": "/*\n * tclAssem.c --\n *\n *\tThis file contains procedures to help assemble Tcl commands\n *\tfrom an input source  where commands may arrive in pieces, e.g.\n *\tseveral lines of type-in corresponding to one command.\n *\n * Copyright 1990-1991 Regents of the University of California\n * Permission to use, copy, modify, and distribute this\n * software and its documentation for any purpose and without\n * fee is hereby granted, provided that the above copyright\n * notice appear in all copies.  The University of California\n * makes no representations about the suitability of this\n * software for any purpose.  It is provided \"as is\" without\n * express or implied warranty.\n */\n#include \"internal.h\"\n\n/*\n * The structure below is the internal representation for a command\n * buffer, which is used to hold a piece of a command until a full\n * command is available.  When a full command is available, it will\n * be returned to the user, but it will also be retained in the buffer\n * until the NEXT call to Tcl_AssembleCmd, at which point it will be\n * removed.\n */\n\ntypedef struct {\n    unsigned char *buffer;\t/* Storage for command being assembled.\n\t\t\t\t * Malloc-ed, and grows as needed. */\n    int bufSize;\t\t/* Total number of bytes in buffer. */\n    int bytesUsed;\t\t/* Number of bytes in buffer currently\n\t\t\t\t * occupied (0 means there is not a\n\t\t\t\t * buffered incomplete command). */\n} CmdBuf;\n\n/*\n * Default amount of space to allocate in command buffer:\n */\n\n#define CMD_BUF_SIZE 100\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_CreateCmdBuf --\n *\n *\tAllocate and initialize a command buffer.\n *\n * Results:\n *\tThe return value is a token that may be passed to\n *\tTcl_AssembleCmd and Tcl_DeleteCmdBuf.\n *\n * Side effects:\n *\tMemory is allocated.\n *\n *----------------------------------------------------------------------\n */\n\nTcl_CmdBuf\nTcl_CreateCmdBuf ()\n{\n    register CmdBuf *cbPtr;\n\n    cbPtr = (CmdBuf*) malloc (sizeof(CmdBuf));\n    cbPtr->buffer = malloc (CMD_BUF_SIZE);\n    cbPtr->buffer[0] = '\\0';\n    cbPtr->bufSize = CMD_BUF_SIZE;\n    cbPtr->bytesUsed = 0;\n    return (Tcl_CmdBuf) cbPtr;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_DeleteCmdBuf --\n *\n *\tRelease all of the resources associated with a command buffer.\n *\tThe caller should never again use buffer again.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tMemory is released.\n *\n *----------------------------------------------------------------------\n */\n\nvoid\nTcl_DeleteCmdBuf(buffer)\n    Tcl_CmdBuf buffer;\t\t/* Token for command buffer (return value\n\t\t\t\t * from previous call to Tcl_CreateCmdBuf). */\n{\n    register CmdBuf *cbPtr = (CmdBuf *) buffer;\n\n    free (cbPtr->buffer);\n    free (cbPtr);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_AssembleCmd --\n *\n *\tThis is a utility procedure to assist in situations where\n *\tcommands may be read piece-meal from some input source.  Given\n *\tsome input text, it adds the text to an input buffer and returns\n *\twhole commands when they are ready.\n *\n * Results:\n *\tIf the addition of string to any currently-buffered information\n *\tresults in one or more complete Tcl commands, then the return value\n *\tis a pointer to the complete command(s).  The command value will\n *\tonly be valid until the next call to this procedure with the\n *\tsame buffer.  If the addition of string leaves an incomplete\n *\tcommand at the end of the buffer, then NULL is returned.\n *\n * Side effects:\n *\tIf string leaves a command incomplete, the partial command\n *\tinformation is buffered for use in later calls to this procedure.\n *\tOnce a command has been returned, that command is deleted from\n *\tthe buffer on the next call to this procedure.\n *\n *----------------------------------------------------------------------\n */\n\nunsigned char *\nTcl_AssembleCmd (buffer, string)\n    Tcl_CmdBuf buffer;\t\t/* Token for a command buffer previously\n\t\t\t\t * created by Tcl_CreateCmdBuf.  */\n    unsigned char *string;\t/* Bytes to be appended to command stream.\n\t\t\t\t * Note:  if the string is zero length,\n\t\t\t\t * then whatever is buffered will be\n\t\t\t\t * considered to be a complete command\n\t\t\t\t * regardless of whether parentheses are\n\t\t\t\t * matched or not. */\n{\n    register CmdBuf *cbPtr = (CmdBuf *) buffer;\n    int length, totalLength, c;\n\n    /*\n     * If an empty string is passed in, just pretend the current\n     * command is complete, whether it really is or not.\n     */\n\n    length = strlen(string);\n    if (length == 0) {\n\tcbPtr->buffer[cbPtr->bytesUsed] = 0;\n\tcbPtr->bytesUsed = 0;\n\treturn cbPtr->buffer;\n    }\n\n    /*\n     * Add the new information to the buffer.  If the current buffer\n     * isn't large enough, grow it by at least a factor of two, or\n     * enough to hold the new text.\n     */\n\n    length = strlen(string);\n    totalLength = cbPtr->bytesUsed + length + 1;\n    if (totalLength > cbPtr->bufSize) {\n\tunsigned int newSize;\n\tunsigned char *newBuf;\n\n\tnewSize = cbPtr->bufSize*2;\n\tif (newSize < totalLength) {\n\t    newSize = totalLength;\n\t}\n\tnewBuf = malloc (newSize);\n\tstrcpy(newBuf, cbPtr->buffer);\n\tfree(cbPtr->buffer);\n\tcbPtr->buffer = newBuf;\n\tcbPtr->bufSize = newSize;\n    }\n    strcpy(cbPtr->buffer+cbPtr->bytesUsed, string);\n    cbPtr->bytesUsed += length;\n\n    /*\n     * See if there is now a complete command in the buffer.\n     */\n\n    c = cbPtr->buffer[cbPtr->bytesUsed-1];\n    if ((c != '\\n') && (c != ';')) {\n\treturn 0;\n    }\n    if (Tcl_CommandComplete(cbPtr->buffer)) {\n\tcbPtr->bytesUsed = 0;\n\treturn cbPtr->buffer;\n    }\n    return 0;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_CommandComplete --\n *\n *\tGiven a partial or complete Tcl command, this procedure\n *\tdetermines whether the command is complete in the sense\n *\tof having matched braces and quotes and brackets.\n *\n * Results:\n *\t1 is returned if the command is complete, 0 otherwise.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTcl_CommandComplete(cmd)\n    unsigned char *cmd;\t\t/* Command to check. */\n{\n    register unsigned char *p = cmd;\n\n    p = cmd;\n    while (1) {\n\twhile (isspace(*p)) {\n\t    p++;\n\t}\n\tif (*p == 0) {\n\t    return 1;\n\t}\n\tp = TclWordEnd(p, 0);\n\tif (*p == 0) {\n\t    return 0;\n\t}\n\tp++;\n    }\n}\n"
  },
  {
    "path": "lib/libtcl/tclbasic.c",
    "content": "/*\n * tclBasic.c --\n *\n *\tContains the basic facilities for TCL command interpretation,\n *\tincluding interpreter creation and deletion, command creation\n *\tand deletion, and command parsing and execution.\n *\n * Copyright 1987-1992 Regents of the University of California\n * Permission to use, copy, modify, and distribute this\n * software and its documentation for any purpose and without\n * fee is hereby granted, provided that the above copyright\n * notice appear in all copies.  The University of California\n * makes no representations about the suitability of this\n * software for any purpose.  It is provided \"as is\" without\n * express or implied warranty.\n */\n#include \"internal.h\"\n#include <stdarg.h>\n\n/*\n * The following structure defines all of the commands in the Tcl core,\n * and the C procedures that execute them.\n */\ntypedef struct {\n\tunsigned char *name;\t/* Name of command. */\n\tTcl_CmdProc *proc;\t/* Procedure that executes command. */\n} CmdInfo;\n\n/*\n * Built-in commands, and the procedures associated with them:\n */\n\nstatic CmdInfo builtin_cmds[] = {\n    /*\n     * Commands in the generic core:\n     */\n\n    {(unsigned char*) \"append\",\t\tTcl_AppendCmd},\n    {(unsigned char*) \"array\",\t\tTcl_ArrayCmd},\n    {(unsigned char*) \"break\",\t\tTcl_BreakCmd},\n    {(unsigned char*) \"case\",\t\tTcl_CaseCmd},\n    {(unsigned char*) \"catch\",\t\tTcl_CatchCmd},\n    {(unsigned char*) \"concat\",\t\tTcl_ConcatCmd},\n    {(unsigned char*) \"continue\",\tTcl_ContinueCmd},\n    {(unsigned char*) \"error\",\t\tTcl_ErrorCmd},\n    {(unsigned char*) \"eval\",\t\tTcl_EvalCmd},\n    {(unsigned char*) \"expr\",\t\tTcl_ExprCmd},\n    {(unsigned char*) \"for\",\t\tTcl_ForCmd},\n    {(unsigned char*) \"foreach\",\tTcl_ForeachCmd},\n    {(unsigned char*) \"format\",\t\tTcl_FormatCmd},\n    {(unsigned char*) \"global\",\t\tTcl_GlobalCmd},\n    {(unsigned char*) \"if\",\t\tTcl_IfCmd},\n    {(unsigned char*) \"incr\",\t\tTcl_IncrCmd},\n    {(unsigned char*) \"info\",\t\tTcl_InfoCmd},\n    {(unsigned char*) \"join\",\t\tTcl_JoinCmd},\n    {(unsigned char*) \"lappend\",\tTcl_LappendCmd},\n    {(unsigned char*) \"lindex\",\t\tTcl_LindexCmd},\n    {(unsigned char*) \"linsert\",\tTcl_LinsertCmd},\n    {(unsigned char*) \"list\",\t\tTcl_ListCmd},\n    {(unsigned char*) \"llength\",\tTcl_LlengthCmd},\n    {(unsigned char*) \"lrange\",\t\tTcl_LrangeCmd},\n    {(unsigned char*) \"lreplace\",\tTcl_LreplaceCmd},\n    {(unsigned char*) \"lsearch\",\tTcl_LsearchCmd},\n    {(unsigned char*) \"lsort\",\t\tTcl_LsortCmd},\n    {(unsigned char*) \"proc\",\t\tTcl_ProcCmd},\n    {(unsigned char*) \"regexp\",\t\tTcl_RegexpCmd},\n    {(unsigned char*) \"regsub\",\t\tTcl_RegsubCmd},\n    {(unsigned char*) \"rename\",\t\tTcl_RenameCmd},\n    {(unsigned char*) \"return\",\t\tTcl_ReturnCmd},\n    {(unsigned char*) \"scan\",\t\tTcl_ScanCmd},\n    {(unsigned char*) \"set\",\t\tTcl_SetCmd},\n    {(unsigned char*) \"split\",\t\tTcl_SplitCmd},\n    {(unsigned char*) \"string\",\t\tTcl_StringCmd},\n    {(unsigned char*) \"trace\",\t\tTcl_TraceCmd},\n    {(unsigned char*) \"unset\",\t\tTcl_UnsetCmd},\n    {(unsigned char*) \"uplevel\",\tTcl_UplevelCmd},\n    {(unsigned char*) \"upvar\",\t\tTcl_UpvarCmd},\n    {(unsigned char*) \"while\",\t\tTcl_WhileCmd},\n\n    /*\n     * Commands in the UNIX core:\n     */\n#ifdef TCL_FILE_CMDS\n    {(unsigned char*) \"glob\",\t\tTcl_GlobCmd},\n    {(unsigned char*) \"cd\",\t\tTcl_CdCmd},\n    {(unsigned char*) \"close\",\t\tTcl_CloseCmd},\n    {(unsigned char*) \"eof\",\t\tTcl_EofCmd},\n    {(unsigned char*) \"exit\",\t\tTcl_ExitCmd},\n    {(unsigned char*) \"file\",\t\tTcl_FileCmd},\n    {(unsigned char*) \"flush\",\t\tTcl_FlushCmd},\n    {(unsigned char*) \"gets\",\t\tTcl_GetsCmd},\n    {(unsigned char*) \"open\",\t\tTcl_OpenCmd},\n    {(unsigned char*) \"puts\",\t\tTcl_PutsCmd},\n    {(unsigned char*) \"pwd\",\t\tTcl_PwdCmd},\n    {(unsigned char*) \"read\",\t\tTcl_ReadCmd},\n    {(unsigned char*) \"seek\",\t\tTcl_SeekCmd},\n    {(unsigned char*) \"source\",\t\tTcl_SourceCmd},\n    {(unsigned char*) \"tell\",\t\tTcl_TellCmd},\n#endif\n    {0,\t\t\t\t\t0}\n};\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_CreateInterp --\n *\n *\tCreate a new TCL command interpreter.\n *\n * Results:\n *\tThe return value is a token for the interpreter, which may be\n *\tused in calls to procedures like Tcl_CreateCmd, Tcl_Eval, or\n *\tTcl_DeleteInterp.\n *\n * Side effects:\n *\tThe command interpreter is initialized with an empty variable\n *\ttable and the built-in commands.\n *\n *----------------------------------------------------------------------\n */\n\nTcl_Interp *\nTcl_CreateInterp ()\n{\n    Interp *iPtr;\n    Command *c;\n    CmdInfo *ci;\n    int i;\n\n    iPtr = (Interp*) malloc (sizeof(Interp));\n    iPtr->result = iPtr->resultSpace;\n    iPtr->freeProc = 0;\n    iPtr->errorLine = 0;\n    Tcl_InitHashTable (&iPtr->commandTable, TCL_STRING_KEYS);\n    Tcl_InitHashTable (&iPtr->globalTable, TCL_STRING_KEYS);\n    iPtr->numLevels = 0;\n    iPtr->framePtr = 0;\n    iPtr->varFramePtr = 0;\n    iPtr->activeTracePtr = 0;\n    iPtr->numEvents = 0;\n    iPtr->events = 0;\n    iPtr->curEvent = 0;\n    iPtr->curEventNum = 0;\n    iPtr->revPtr = 0;\n    iPtr->historyFirst = 0;\n    iPtr->revDisables = 1;\n    iPtr->evalFirst = iPtr->evalLast = 0;\n    iPtr->appendResult = 0;\n    iPtr->appendAvl = 0;\n    iPtr->appendUsed = 0;\n    iPtr->numFiles = 0;\n    iPtr->filePtrArray = 0;\n    for (i = 0; i < NUM_REGEXPS; i++) {\n\tiPtr->patterns[i] = 0;\n\tiPtr->patLengths[i] = -1;\n\tiPtr->regexps[i] = 0;\n    }\n    iPtr->cmdCount = 0;\n    iPtr->noEval = 0;\n    iPtr->scriptFile = 0;\n    iPtr->flags = 0;\n    iPtr->tracePtr = 0;\n    iPtr->resultSpace[0] = 0;\n\n    /*\n     * Create the built-in commands.  Do it here, rather than calling\n     * Tcl_CreateCommand, because it's faster (there's no need to\n     * check for a pre-existing command by the same name).\n     */\n     for (ci = builtin_cmds; ci->name != 0; ci++) {\n\tint new;\n\tTcl_HashEntry *he;\n\n\the = Tcl_CreateHashEntry (&iPtr->commandTable, ci->name, &new);\n\tif (new) {\n\t    c = (Command*) malloc (sizeof(Command));\n\t    c->proc = ci->proc;\n\t    c->clientData = (void*) 0;\n\t    c->deleteProc = 0;\n\t    Tcl_SetHashValue (he, c);\n\t}\n    }\n#ifdef TCL_ENV_CMDS\n    TclSetupEnv ((Tcl_Interp *) iPtr);\n#endif\n    return (Tcl_Interp *) iPtr;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_DeleteInterp --\n *\n *\tDelete an interpreter and free up all of the resources associated\n *\twith it.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tThe interpreter is destroyed.  The caller should never again\n *\tuse the interp token.\n *\n *----------------------------------------------------------------------\n */\n\nvoid\nTcl_DeleteInterp(interp)\n    Tcl_Interp *interp;\t\t/* Token for command interpreter (returned\n\t\t\t\t * by a previous call to Tcl_CreateInterp). */\n{\n    Interp *iPtr = (Interp *) interp;\n    Tcl_HashEntry *he;\n    Tcl_HashSearch search;\n    register Command *c;\n    int i;\n\n    /*\n     * If the interpreter is in use, delay the deletion until later.\n     */\n\n    iPtr->flags |= DELETED;\n    if (iPtr->numLevels != 0) {\n\treturn;\n    }\n\n    /*\n     * Free up any remaining resources associated with the\n     * interpreter.\n     */\n\n    for (he = Tcl_FirstHashEntry(&iPtr->commandTable, &search);\n\t    he != 0; he = Tcl_NextHashEntry(&search)) {\n\tc = (Command *) Tcl_GetHashValue(he);\n\tif (c->deleteProc != 0) {\n\t    (*c->deleteProc)(c->clientData);\n\t}\n\tfree (c);\n    }\n    Tcl_DeleteHashTable(&iPtr->commandTable);\n    TclDeleteVars(iPtr, &iPtr->globalTable);\n    if (iPtr->events != 0) {\n\tint i;\n\n\tfor (i = 0; i < iPtr->numEvents; i++) {\n\t    free(iPtr->events[i].command);\n\t}\n\tfree (iPtr->events);\n    }\n    while (iPtr->revPtr != 0) {\n\tHistoryRev *nextPtr = iPtr->revPtr->nextPtr;\n\n\tfree (iPtr->revPtr);\n\tiPtr->revPtr = nextPtr;\n    }\n    if (iPtr->appendResult != 0) {\n\tfree(iPtr->appendResult);\n    }\n#ifdef TCL_FILE_CMDS\n    if (iPtr->numFiles > 0) {\n\tfor (i = 0; i < iPtr->numFiles; i++) {\n\t    OpenFile *filePtr;\n\n\t    filePtr = iPtr->filePtrArray[i];\n\t    if (filePtr == 0) {\n\t\tcontinue;\n\t    }\n\t    if (i >= 3) {\n\t\tfclose(filePtr->f);\n\t\tif (filePtr->f2 != 0) {\n\t\t    fclose(filePtr->f2);\n\t\t}\n\t\tif (filePtr->numPids > 0) {\n\t\t    /* Tcl_DetachPids(filePtr->numPids, filePtr->pidPtr); */\n\t\t    free (filePtr->pidPtr);\n\t\t}\n\t    }\n\t    free (filePtr);\n\t}\n\tfree (iPtr->filePtrArray);\n    }\n#endif\n    for (i = 0; i < NUM_REGEXPS; i++) {\n\tif (iPtr->patterns[i] == 0) {\n\t    break;\n\t}\n\tfree (iPtr->patterns[i]);\n\tfree (iPtr->regexps[i]);\n    }\n    while (iPtr->tracePtr != 0) {\n\tTrace *nextPtr = iPtr->tracePtr->nextPtr;\n\n\tfree (iPtr->tracePtr);\n\tiPtr->tracePtr = nextPtr;\n    }\n    free (iPtr);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_CreateCommand --\n *\n *\tDefine a new command in a command table.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tIf a command named cmdName already exists for interp, it is\n *\tdeleted.  In the future, when cmdName is seen as the name of\n *\ta command by Tcl_Eval, proc will be called.  When the command\n *\tis deleted from the table, deleteProc will be called.  See the\n *\tmanual entry for details on the calling sequence.\n *\n *----------------------------------------------------------------------\n */\n\nvoid\nTcl_CreateCommand(interp, cmdName, proc, clientData, deleteProc)\n    Tcl_Interp *interp;\t\t/* Token for command interpreter (returned\n\t\t\t\t * by a previous call to Tcl_CreateInterp). */\n    unsigned char *cmdName;\t/* Name of command. */\n    Tcl_CmdProc *proc;\t\t/* Command procedure to associate with\n\t\t\t\t * cmdName. */\n    void *clientData;\t\t/* Arbitrary one-word value to pass to proc. */\n    Tcl_CmdDeleteProc *deleteProc;\n\t\t\t\t/* If not NULL, gives a procedure to call when\n\t\t\t\t * this command is deleted. */\n{\n    Interp *iPtr = (Interp *) interp;\n    register Command *c;\n    Tcl_HashEntry *he;\n    int new;\n\n    he = Tcl_CreateHashEntry(&iPtr->commandTable, cmdName, &new);\n    if (!new) {\n\t/*\n\t * Command already exists:  delete the old one.\n\t */\n\n\tc = (Command *) Tcl_GetHashValue(he);\n\tif (c->deleteProc != 0) {\n\t    (*c->deleteProc)(c->clientData);\n\t}\n    } else {\n\tc = (Command*) malloc (sizeof(Command));\n\tTcl_SetHashValue(he, c);\n    }\n    c->proc = proc;\n    c->clientData = clientData;\n    c->deleteProc = deleteProc;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_DeleteCommand --\n *\n *\tRemove the given command from the given interpreter.\n *\n * Results:\n *\t0 is returned if the command was deleted successfully.\n *\t-1 is returned if there didn't exist a command by that\n *\tname.\n *\n * Side effects:\n *\tCmdName will no longer be recognized as a valid command for\n *\tinterp.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTcl_DeleteCommand(interp, cmdName)\n    Tcl_Interp *interp;\t\t/* Token for command interpreter (returned\n\t\t\t\t * by a previous call to Tcl_CreateInterp). */\n    unsigned char *cmdName;\t/* Name of command to remove. */\n{\n    Interp *iPtr = (Interp *) interp;\n    Tcl_HashEntry *he;\n    Command *c;\n\n    he = Tcl_FindHashEntry(&iPtr->commandTable, cmdName);\n    if (he == 0) {\n\treturn -1;\n    }\n    c = (Command *) Tcl_GetHashValue(he);\n    if (c->deleteProc != 0) {\n\t(*c->deleteProc)(c->clientData);\n    }\n    free (c);\n    Tcl_DeleteHashEntry(he);\n    return 0;\n}\n\f\n/*\n *-----------------------------------------------------------------\n *\n * Tcl_Eval --\n *\n *\tParse and execute a command in the Tcl language.\n *\n * Results:\n *\tThe return value is one of the return codes defined in tcl.hd\n *\t(such as TCL_OK), and interp->result contains a string value\n *\tto supplement the return code.  The value of interp->result\n *\twill persist only until the next call to Tcl_Eval:  copy it or\n *\tlose it! *TermPtr is filled in with the character just after\n *\tthe last one that was part of the command (usually a NULL\n *\tcharacter or a closing bracket).\n *\n * Side effects:\n *\tAlmost certainly;  depends on the command.\n *\n *-----------------------------------------------------------------\n */\n\nint\nTcl_Eval(interp, cmd, flags, termPtr)\n    Tcl_Interp *interp;\t\t/* Token for command interpreter (returned\n\t\t\t\t * by a previous call to Tcl_CreateInterp). */\n    unsigned char *cmd;\t\t/* Pointer to TCL command to interpret. */\n    int flags;\t\t\t/* OR-ed combination of flags like\n\t\t\t\t * TCL_BRACKET_TERM and TCL_RECORD_BOUNDS. */\n    unsigned char **termPtr;\t/* If non-NULL, fill in the address it points\n\t\t\t\t * to with the address of the char. just after\n\t\t\t\t * the last one that was part of cmd.  See\n\t\t\t\t * the man page for details on this. */\n{\n    /*\n     * The storage immediately below is used to generate a copy\n     * of the command, after all argument substitutions.  Pv will\n     * contain the argv values passed to the command procedure.\n     */\n\n#   define NUM_CHARS 200\n    unsigned char copyStorage[NUM_CHARS];\n    ParseValue pv;\n    unsigned char *oldBuffer;\n\n    /*\n     * This procedure generates an (argv, argc) array for the command,\n     * It starts out with stack-allocated space but uses dynamically-\n     * allocated storage to increase it if needed.\n     */\n\n#   define NUM_ARGS 10\n    unsigned char *(argStorage[NUM_ARGS]);\n    unsigned char **argv = argStorage;\n    int argc;\n    int argSize = NUM_ARGS;\n\n    register unsigned char *src;\t/* Points to current character\n\t\t\t\t\t * in cmd. */\n    char termChar;\t\t\t/* Return when this character is found\n\t\t\t\t\t * (either ']' or '\\0').  Zero means\n\t\t\t\t\t * that newlines terminate commands. */\n    int result;\t\t\t\t/* Return value. */\n    register Interp *iPtr = (Interp *) interp;\n    Tcl_HashEntry *he;\n    Command *c;\n    unsigned char *dummy;\t\t/* Make termPtr point here if it was\n\t\t\t\t\t * originally NULL. */\n    unsigned char *cmdStart;\t\t/* Points to first non-blank char. in\n\t\t\t\t\t * command (used in calling trace\n\t\t\t\t\t * procedures). */\n    unsigned char *ellipsis = (unsigned char*) \"\";\n\t\t\t\t\t/* Used in setting errorInfo variable;\n\t\t\t\t\t * set to \"...\" to indicate that not\n\t\t\t\t\t * all of offending command is included\n\t\t\t\t\t * in errorInfo.  \"\" means that the\n\t\t\t\t\t * command is all there. */\n    register Trace *tracePtr;\n\n    /*\n     * Initialize the result to an empty string and clear out any\n     * error information.  This makes sure that we return an empty\n     * result if there are no commands in the command string.\n     */\n\n    Tcl_FreeResult((Tcl_Interp *) iPtr);\n    iPtr->result = iPtr->resultSpace;\n    iPtr->resultSpace[0] = 0;\n    result = TCL_OK;\n\n    /*\n     * Check depth of nested calls to Tcl_Eval:  if this gets too large,\n     * it's probably because of an infinite loop somewhere.\n     */\n\n    iPtr->numLevels++;\n    if (iPtr->numLevels > MAX_NESTING_DEPTH) {\n\tiPtr->numLevels--;\n\tiPtr->result = (unsigned char*) \"too many nested calls to Tcl_Eval (infinite loop?)\";\n\treturn TCL_ERROR;\n    }\n\n    /*\n     * Initialize the area in which command copies will be assembled.\n     */\n\n    pv.buffer = copyStorage;\n    pv.end = copyStorage + NUM_CHARS - 1;\n    pv.expandProc = TclExpandParseValue;\n    pv.clientData = (void*) 0;\n\n    src = cmd;\n    if (flags & TCL_BRACKET_TERM) {\n\ttermChar = ']';\n    } else {\n\ttermChar = 0;\n    }\n    if (termPtr == 0) {\n\ttermPtr = &dummy;\n    }\n    *termPtr = src;\n    cmdStart = src;\n\n    /*\n     * There can be many sub-commands (separated by semi-colons or\n     * newlines) in one command string.  This outer loop iterates over\n     * individual commands.\n     */\n\n    while (*src != termChar) {\n\tiPtr->flags &= ~(ERR_IN_PROGRESS | ERROR_CODE_SET);\n\n\t/*\n\t * Skim off leading white space and semi-colons, and skip\n\t * comments.\n\t */\n\twhile (1) {\n\t    switch (*src) {\n\t    case '\\t':\n\t    case '\\v':\n\t    case '\\f':\n\t    case '\\r':\n\t    case '\\n':\n\t    case ' ':\n\t    case ':':\n\t\t++src;\n\t\tcontinue;\n\t    }\n\t    break;\n\t}\n\tif (*src == '#') {\n\t    for (src++; *src != 0; src++) {\n\t\tif ((*src == '\\n') && (src[-1] != '\\\\')) {\n\t\t    src++;\n\t\t    break;\n\t\t}\n\t    }\n\t    continue;\n\t}\n\tcmdStart = src;\n\n\t/*\n\t * Parse the words of the command, generating the argc and\n\t * argv for the command procedure.  May have to call\n\t * TclParseWords several times, expanding the argv array\n\t * between calls.\n\t */\n\n\tpv.next = oldBuffer = pv.buffer;\n\targc = 0;\n\twhile (1) {\n\t    int newArgs, maxArgs;\n\t    unsigned char **newArgv;\n\t    int i;\n\n\t    /*\n\t     * Note:  the \"- 2\" below guarantees that we won't use the\n\t     * last two argv slots here.  One is for a NULL pointer to\n\t     * mark the end of the list, and the other is to leave room\n\t     * for inserting the command name \"unknown\" as the first\n\t     * argument (see below).\n\t     */\n\n\t    maxArgs = argSize - argc - 2;\n\t    result = TclParseWords((Tcl_Interp *) iPtr, src, flags,\n\t\t    maxArgs, termPtr, &newArgs, &argv[argc], &pv);\n\t    src = *termPtr;\n\t    if (result != TCL_OK) {\n\t\tellipsis = (unsigned char*) \"...\";\n\t\tgoto done;\n\t    }\n\n\t    /*\n\t     * Careful!  Buffer space may have gotten reallocated while\n\t     * parsing words.  If this happened, be sure to update all\n\t     * of the older argv pointers to refer to the new space.\n\t     */\n\n\t    if (oldBuffer != pv.buffer) {\n\t\tint i;\n\n\t\tfor (i = 0; i < argc; i++) {\n\t\t    argv[i] = pv.buffer + (argv[i] - oldBuffer);\n\t\t}\n\t\toldBuffer = pv.buffer;\n\t    }\n\t    argc += newArgs;\n\t    if (newArgs < maxArgs) {\n\t\targv[argc] = 0;\n\t\tbreak;\n\t    }\n\n\t    /*\n\t     * Args didn't all fit in the current array.  Make it bigger.\n\t     */\n\n\t    argSize *= 2;\n\t    newArgv = (unsigned char**) malloc ((unsigned)\n                        argSize * sizeof(char *));\n\t    for (i = 0; i < argc; i++) {\n\t\tnewArgv[i] = argv[i];\n\t    }\n\t    if (argv != argStorage) {\n\t\tfree (argv);\n\t    }\n\t    argv = newArgv;\n\t}\n\n\t/*\n\t * If this is an empty command (or if we're just parsing\n\t * commands without evaluating them), then just skip to the\n\t * next command.\n\t */\n\n\tif ((argc == 0) || iPtr->noEval) {\n\t    continue;\n\t}\n\targv[argc] = 0;\n\n\t/*\n\t * Save information for the history module, if needed.\n\t */\n\n\tif (flags & TCL_RECORD_BOUNDS) {\n\t    iPtr->evalFirst = cmdStart;\n\t    iPtr->evalLast = src-1;\n\t}\n\n\t/*\n\t * Find the procedure to execute this command.  If there isn't\n\t * one, then see if there is a command \"unknown\".  If so,\n\t * invoke it instead, passing it the words of the original\n\t * command as arguments.\n\t */\n\n\the = Tcl_FindHashEntry(&iPtr->commandTable, argv[0]);\n\tif (he == 0) {\n\t    int i;\n\n\t    he = Tcl_FindHashEntry(&iPtr->commandTable, (unsigned char*) \"unknown\");\n\t    if (he == 0) {\n\t\tTcl_ResetResult(interp);\n\t\tTcl_AppendResult(interp, \"invalid command name: \\\"\",\n\t\t\targv[0], \"\\\"\", 0);\n\t\tresult = TCL_ERROR;\n\t\tgoto done;\n\t    }\n\t    for (i = argc; i >= 0; i--) {\n\t\targv[i+1] = argv[i];\n\t    }\n\t    argv[0] = (unsigned char*) \"unknown\";\n\t    argc++;\n\t}\n\tc = (Command *) Tcl_GetHashValue(he);\n\n\t/*\n\t * Call trace procedures, if any.\n\t */\n\n\tfor (tracePtr = iPtr->tracePtr; tracePtr != 0;\n\t\ttracePtr = tracePtr->nextPtr) {\n\t    char saved;\n\n\t    if (tracePtr->level < iPtr->numLevels) {\n\t\tcontinue;\n\t    }\n\t    saved = *src;\n\t    *src = 0;\n\t    (*tracePtr->proc)(tracePtr->clientData, interp, iPtr->numLevels,\n\t\t    cmdStart, c->proc, c->clientData, argc, argv);\n\t    *src = saved;\n\t}\n\n\t/*\n\t * At long last, invoke the command procedure.  Reset the\n\t * result to its default empty value first (it could have\n\t * gotten changed by earlier commands in the same command\n\t * string).\n\t */\n\n\tiPtr->cmdCount++;\n\tTcl_FreeResult ((Tcl_Interp*) iPtr);\n\tiPtr->result = iPtr->resultSpace;\n\tiPtr->resultSpace[0] = 0;\n\tresult = (*c->proc)(c->clientData, interp, argc, argv);\n\tif (result != TCL_OK) {\n\t    break;\n\t}\n    }\n\n    /*\n     * Free up any extra resources that were allocated.\n     */\n\n    done:\n    if (pv.buffer != copyStorage) {\n\tfree (pv.buffer);\n    }\n    if (argv != argStorage) {\n\tfree (argv);\n    }\n    iPtr->numLevels--;\n    if (iPtr->numLevels == 0) {\n\tif (result == TCL_RETURN) {\n\t    result = TCL_OK;\n\t}\n\tif ((result != TCL_OK) && (result != TCL_ERROR)) {\n\t    Tcl_ResetResult(interp);\n\t    if (result == TCL_BREAK) {\n\t\tiPtr->result = (unsigned char*) \"invoked \\\"break\\\" outside of a loop\";\n\t    } else if (result == TCL_CONTINUE) {\n\t\tiPtr->result = (unsigned char*) \"invoked \\\"continue\\\" outside of a loop\";\n\t    } else {\n\t\tiPtr->result = iPtr->resultSpace;\n\t\tsprintf(iPtr->resultSpace, \"command returned bad code: %d\",\n\t\t\tresult);\n\t    }\n\t    result = TCL_ERROR;\n\t}\n\tif (iPtr->flags & DELETED) {\n\t    Tcl_DeleteInterp(interp);\n\t}\n    }\n\n    /*\n     * If an error occurred, record information about what was being\n     * executed when the error occurred.\n     */\n\n    if ((result == TCL_ERROR) && !(iPtr->flags & ERR_ALREADY_LOGGED)) {\n\tint numChars;\n\tregister unsigned char *p;\n\n\t/*\n\t * Compute the line number where the error occurred.\n\t */\n\n\tiPtr->errorLine = 1;\n\tfor (p = cmd; p != cmdStart; p++) {\n\t    if (*p == '\\n') {\n\t\tiPtr->errorLine++;\n\t    }\n\t}\n\tfor ( ; isspace(*p) || (*p == ';'); p++) {\n\t    if (*p == '\\n') {\n\t\tiPtr->errorLine++;\n\t    }\n\t}\n\n\t/*\n\t * Figure out how much of the command to print in the error\n\t * message (up to a certain number of characters, or up to\n\t * the first new-line).\n\t */\n\n\tnumChars = src - cmdStart;\n\tif (numChars > (NUM_CHARS-50)) {\n\t    numChars = NUM_CHARS-50;\n\t    ellipsis = (unsigned char*) \" ...\";\n\t}\n\n\tif (!(iPtr->flags & ERR_IN_PROGRESS)) {\n\t    sprintf(copyStorage, \"\\n    while executing\\n\\\"%.*s%s\\\"\",\n\t\t    numChars, cmdStart, ellipsis);\n\t} else {\n\t    sprintf(copyStorage, \"\\n    invoked from within\\n\\\"%.*s%s\\\"\",\n\t\t    numChars, cmdStart, ellipsis);\n\t}\n\tTcl_AddErrorInfo(interp, copyStorage);\n\tiPtr->flags &= ~ERR_ALREADY_LOGGED;\n    } else {\n\tiPtr->flags &= ~ERR_ALREADY_LOGGED;\n    }\n    return result;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_CreateTrace --\n *\n *\tArrange for a procedure to be called to trace command execution.\n *\n * Results:\n *\tThe return value is a token for the trace, which may be passed\n *\tto Tcl_DeleteTrace to eliminate the trace.\n *\n * Side effects:\n *\tFrom now on, proc will be called just before a command procedure\n *\tis called to execute a Tcl command.  Calls to proc will have the\n *\tfollowing form:\n *\n *\tvoid\n *\tproc(clientData, interp, level, command, cmdProc, cmdClientData,\n *\t\targc, argv)\n *\t    void *clientData;\n *\t    Tcl_Interp *interp;\n *\t    int level;\n *\t    unsigned char *command;\n *\t    int (*cmdProc)();\n *\t    void *cmdClientData;\n *\t    int argc;\n *\t    unsigned char **argv;\n *\t{\n *\t}\n *\n *\tThe clientData and interp arguments to proc will be the same\n *\tas the corresponding arguments to this procedure.  Level gives\n *\tthe nesting level of command interpretation for this interpreter\n *\t(0 corresponds to top level).  Command gives the ASCII text of\n *\tthe raw command, cmdProc and cmdClientData give the procedure that\n *\twill be called to process the command and the ClientData value it\n *\twill receive, and argc and argv give the arguments to the\n *\tcommand, after any argument parsing and substitution.  Proc\n *\tdoes not return a value.\n *\n *----------------------------------------------------------------------\n */\n\nTcl_Trace\nTcl_CreateTrace(interp, level, proc, clientData)\n    Tcl_Interp *interp;\t\t/* Interpreter in which to create the trace. */\n    int level;\t\t\t/* Only call proc for commands at nesting level\n\t\t\t\t * <= level (1 => top level). */\n    Tcl_CmdTraceProc *proc;\t/* Procedure to call before executing each\n\t\t\t\t * command. */\n    void *clientData;\t\t/* Arbitrary one-word value to pass to proc. */\n{\n    register Trace *tracePtr;\n    register Interp *iPtr = (Interp *) interp;\n\n    tracePtr = (Trace*) malloc (sizeof(Trace));\n    tracePtr->level = level;\n    tracePtr->proc = proc;\n    tracePtr->clientData = clientData;\n    tracePtr->nextPtr = iPtr->tracePtr;\n    iPtr->tracePtr = tracePtr;\n\n    return (Tcl_Trace) tracePtr;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_DeleteTrace --\n *\n *\tRemove a trace.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tFrom now on there will be no more calls to the procedure given\n *\tin trace.\n *\n *----------------------------------------------------------------------\n */\n\nvoid\nTcl_DeleteTrace(interp, trace)\n    Tcl_Interp *interp;\t\t/* Interpreter that contains trace. */\n    Tcl_Trace trace;\t\t/* Token for trace (returned previously by\n\t\t\t\t * Tcl_CreateTrace). */\n{\n    register Interp *iPtr = (Interp *) interp;\n    register Trace *tracePtr = (Trace *) trace;\n    register Trace *tracePtr2;\n\n    if (iPtr->tracePtr == tracePtr) {\n\tiPtr->tracePtr = tracePtr->nextPtr;\n\tfree (tracePtr);\n    } else {\n\tfor (tracePtr2 = iPtr->tracePtr; tracePtr2 != 0;\n\t\ttracePtr2 = tracePtr2->nextPtr) {\n\t    if (tracePtr2->nextPtr == tracePtr) {\n\t\ttracePtr2->nextPtr = tracePtr->nextPtr;\n\t\tfree (tracePtr);\n\t\treturn;\n\t    }\n\t}\n    }\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_AddErrorInfo --\n *\n *\tAdd information to a message being accumulated that describes\n *\tthe current error.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tThe contents of message are added to the \"errorInfo\" variable.\n *\tIf Tcl_Eval has been called since the current value of errorInfo\n *\twas set, errorInfo is cleared before adding the new message.\n *\n *----------------------------------------------------------------------\n */\n\nvoid\nTcl_AddErrorInfo(interp, message)\n    Tcl_Interp *interp;\t\t/* Interpreter to which error information\n\t\t\t\t * pertains. */\n    unsigned char *message;\t/* Message to record. */\n{\n    register Interp *iPtr = (Interp *) interp;\n\n    /*\n     * If an error is already being logged, then the new errorInfo\n     * is the concatenation of the old info and the new message.\n     * If this is the first piece of info for the error, then the\n     * new errorInfo is the concatenation of the message in\n     * interp->result and the new message.\n     */\n\n    if (!(iPtr->flags & ERR_IN_PROGRESS)) {\n\tTcl_SetVar2(interp, (unsigned char*) \"errorInfo\", 0, interp->result,\n\t\tTCL_GLOBAL_ONLY);\n\tiPtr->flags |= ERR_IN_PROGRESS;\n\n\t/*\n\t * If the errorCode variable wasn't set by the code that generated\n\t * the error, set it to \"NONE\".\n\t */\n\n\tif (!(iPtr->flags & ERROR_CODE_SET)) {\n\t\tTcl_SetVar2(interp, (unsigned char*) \"errorCode\", 0,\n\t\t\t(unsigned char*) \"NONE\", TCL_GLOBAL_ONLY);\n\t}\n    }\n    Tcl_SetVar2(interp, (unsigned char*) \"errorInfo\", 0, message,\n\t    TCL_GLOBAL_ONLY|TCL_APPEND_VALUE);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_VarEval --\n *\n *\tGiven a variable number of string arguments, concatenate them\n *\tall together and execute the result as a Tcl command.\n *\n * Results:\n *\tA standard Tcl return result.  An error message or other\n *\tresult may be left in interp->result.\n *\n * Side effects:\n *\tDepends on what was done by the command.\n *\n *----------------------------------------------------------------------\n */\n\t/* VARARGS2 */ /* ARGSUSED */\nint\nTcl_VarEval (Tcl_Interp *interp,/* Interpreter in which to execute command. */\n\t...)\t\t\t/* One or more strings to concatenate,\n\t\t\t\t * terminated with a NULL string. */\n{\n    va_list argList;\n#define FIXED_SIZE 200\n    unsigned char fixedSpace[FIXED_SIZE+1];\n    int spaceAvl, spaceUsed, length;\n    unsigned char *string, *cmd;\n    int result;\n\n    /*\n     * Copy the strings one after the other into a single larger\n     * string.  Use stack-allocated space for small commands, but if\n     * the commands gets too large than call mem_alloc to create the\n     * space.\n     */\n    va_start(argList, interp);\n    spaceAvl = FIXED_SIZE;\n    spaceUsed = 0;\n    cmd = fixedSpace;\n    while (1) {\n\tstring = va_arg(argList, unsigned char *);\n\tif (string == 0) {\n\t    break;\n\t}\n\tlength = strlen(string);\n\tif ((spaceUsed + length) > spaceAvl) {\n\t    unsigned char *new;\n\n\t    spaceAvl = spaceUsed + length;\n\t    spaceAvl += spaceAvl/2;\n\t    new = malloc ((unsigned) spaceAvl);\n\t    memcpy ((void*) new, (void*) cmd, spaceUsed);\n\t    if (cmd != fixedSpace) {\n\t\tfree(cmd);\n\t    }\n\t    cmd = new;\n\t}\n\tstrcpy(cmd + spaceUsed, string);\n\tspaceUsed += length;\n    }\n    va_end(argList);\n    cmd[spaceUsed] = '\\0';\n\n    result = Tcl_Eval(interp, cmd, 0, 0);\n    if (cmd != fixedSpace) {\n\tfree(cmd);\n    }\n    return result;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_GlobalEval --\n *\n *\tEvaluate a command at global level in an interpreter.\n *\n * Results:\n *\tA standard Tcl result is returned, and interp->result is\n *\tmodified accordingly.\n *\n * Side effects:\n *\tThe command string is executed in interp, and the execution\n *\tis carried out in the variable context of global level (no\n *\tprocedures active), just as if an \"uplevel #0\" command were\n *\tbeing executed.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTcl_GlobalEval(interp, command)\n    Tcl_Interp *interp;\t\t/* Interpreter in which to evaluate command. */\n    unsigned char *command;\t/* Command to evaluate. */\n{\n    register Interp *iPtr = (Interp *) interp;\n    int result;\n    CallFrame *savedVarFramePtr;\n\n    savedVarFramePtr = iPtr->varFramePtr;\n    iPtr->varFramePtr = 0;\n    result = Tcl_Eval(interp, command, 0, 0);\n    iPtr->varFramePtr = savedVarFramePtr;\n    return result;\n}\n"
  },
  {
    "path": "lib/libtcl/tclcmdah.c",
    "content": "/*\n * tclCmdAH.c --\n *\n *\tThis file contains the top-level command routines for most of\n *\tthe Tcl built-in commands whose names begin with the letters\n *\tA to H.\n *\n * Copyright 1987-1991 Regents of the University of California\n * Permission to use, copy, modify, and distribute this\n * software and its documentation for any purpose and without\n * fee is hereby granted, provided that the above copyright\n * notice appear in all copies.  The University of California\n * makes no representations about the suitability of this\n * software for any purpose.  It is provided \"as is\" without\n * express or implied warranty.\n */\n#include \"internal.h\"\n\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_BreakCmd --\n *\n *\tThis procedure is invoked to process the \"break\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_BreakCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    if (argc != 1) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\targv[0], \"\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    return TCL_BREAK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_CaseCmd --\n *\n *\tThis procedure is invoked to process the \"case\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_CaseCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int i, result;\n    int body;\n    unsigned char *string;\n    int caseArgc, splitArgs;\n    unsigned char **caseArgv;\n\n    if (argc < 3) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\targv[0], \" string ?in? patList body ... ?default body?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    string = argv[1];\n    body = -1;\n    if (strcmp(argv[2], (unsigned char*) \"in\") == 0) {\n\ti = 3;\n    } else {\n\ti = 2;\n    }\n    caseArgc = argc - i;\n    caseArgv = argv + i;\n\n    /*\n     * If all of the pattern/command pairs are lumped into a single\n     * argument, split them out again.\n     */\n\n    splitArgs = 0;\n    if (caseArgc == 1) {\n\tresult = Tcl_SplitList(interp, caseArgv[0], &caseArgc, &caseArgv);\n\tif (result != TCL_OK) {\n\t    return result;\n\t}\n\tsplitArgs = 1;\n    }\n\n    for (i = 0; i < caseArgc; i += 2) {\n\tint patArgc, j;\n\tunsigned char **patArgv;\n\tregister unsigned char *p;\n\n\tif (i == (caseArgc-1)) {\n\t    interp->result = (unsigned char*) \"extra case pattern with no body\";\n\t    result = TCL_ERROR;\n\t    goto cleanup;\n\t}\n\n\t/*\n\t * Check for special case of single pattern (no list) with\n\t * no backslash sequences.\n\t */\n\n\tfor (p = caseArgv[i]; *p != 0; p++) {\n\t    if (isspace(*p) || (*p == '\\\\')) {\n\t\tbreak;\n\t    }\n\t}\n\tif (*p == 0) {\n\t    if ((*caseArgv[i] == 'd')\n\t\t    && (strcmp(caseArgv[i], (unsigned char*) \"default\") == 0)) {\n\t\tbody = i+1;\n\t    }\n\t    if (Tcl_StringMatch(string, caseArgv[i])) {\n\t\tbody = i+1;\n\t\tgoto match;\n\t    }\n\t    continue;\n\t}\n\n\t/*\n\t * Break up pattern lists, then check each of the patterns\n\t * in the list.\n\t */\n\n\tresult = Tcl_SplitList(interp, caseArgv[i], &patArgc, &patArgv);\n\tif (result != TCL_OK) {\n\t    goto cleanup;\n\t}\n\tfor (j = 0; j < patArgc; j++) {\n\t    if (Tcl_StringMatch(string, patArgv[j])) {\n\t\tbody = i+1;\n\t\tbreak;\n\t    }\n\t}\n\tfree (patArgv);\n\tif (j < patArgc) {\n\t    break;\n\t}\n    }\n\n    match:\n    if (body != -1) {\n\tresult = Tcl_Eval(interp, caseArgv[body], 0, 0);\n\tif (result == TCL_ERROR) {\n\t    unsigned char msg[100];\n\t    sprintf(msg, \"\\n    (\\\"%.50s\\\" arm line %d)\", caseArgv[body-1],\n\t\t    interp->errorLine);\n\t    Tcl_AddErrorInfo(interp, msg);\n\t}\n\tgoto cleanup;\n    }\n\n    /*\n     * Nothing matched:  return nothing.\n     */\n\n    result = TCL_OK;\n\n    cleanup:\n    if (splitArgs) {\n\tfree (caseArgv);\n    }\n    return result;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_CatchCmd --\n *\n *\tThis procedure is invoked to process the \"catch\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_CatchCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int result;\n\n    if ((argc != 2) && (argc != 3)) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\targv[0], \" command ?varName?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    result = Tcl_Eval(interp, argv[1], 0, 0);\n    if (argc == 3) {\n\tif (Tcl_SetVar(interp, argv[2], interp->result, 0) == 0) {\n\t    Tcl_SetResult(interp, (unsigned char*) \"couldn't save command result in variable\",\n\t\t    TCL_STATIC);\n\t    return TCL_ERROR;\n\t}\n    }\n    Tcl_ResetResult(interp);\n    sprintf(interp->result, \"%d\", result);\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_ConcatCmd --\n *\n *\tThis procedure is invoked to process the \"concat\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_ConcatCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    if (argc == 1) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" arg ?arg ...?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n\n    interp->result = Tcl_Concat (argc-1, argv+1);\n    interp->freeProc = (Tcl_FreeProc *) free;\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_ContinueCmd --\n *\n *\tThis procedure is invoked to process the \"continue\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_ContinueCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    if (argc != 1) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\"\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    return TCL_CONTINUE;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_ErrorCmd --\n *\n *\tThis procedure is invoked to process the \"error\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_ErrorCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    Interp *iPtr = (Interp *) interp;\n\n    if ((argc < 2) || (argc > 4)) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" message ?errorInfo? ?errorCode?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    if ((argc >= 3) && (argv[2][0] != 0)) {\n\tTcl_AddErrorInfo(interp, argv[2]);\n\tiPtr->flags |= ERR_ALREADY_LOGGED;\n    }\n    if (argc == 4) {\n\tTcl_SetVar2(interp, (unsigned char*) \"errorCode\", 0, argv[3],\n\t\tTCL_GLOBAL_ONLY);\n\tiPtr->flags |= ERROR_CODE_SET;\n    }\n    Tcl_SetResult(interp, argv[1], TCL_VOLATILE);\n    return TCL_ERROR;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_EvalCmd --\n *\n *\tThis procedure is invoked to process the \"eval\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_EvalCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int result;\n    unsigned char *cmd;\n\n    if (argc < 2) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" arg ?arg ...?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    if (argc == 2) {\n\tresult = Tcl_Eval(interp, argv[1], 0, 0);\n    } else {\n\n\t/*\n\t * More than one argument:  concatenate them together with spaces\n\t * between, then evaluate the result.\n\t */\n\n\tcmd = Tcl_Concat (argc-1, argv+1);\n\tresult = Tcl_Eval(interp, cmd, 0, 0);\n\tfree(cmd);\n    }\n    if (result == TCL_ERROR) {\n\tunsigned char msg[60];\n\tsprintf(msg, \"\\n    (\\\"eval\\\" body line %d)\", interp->errorLine);\n\tTcl_AddErrorInfo(interp, msg);\n    }\n    return result;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_ExprCmd --\n *\n *\tThis procedure is invoked to process the \"expr\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_ExprCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    if (argc != 2) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" expression\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n\n    return Tcl_ExprString(interp, argv[1]);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_ForCmd --\n *\n *\tThis procedure is invoked to process the \"for\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_ForCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int result, value;\n\n    if (argc != 5) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" start test next command\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n\n    result = Tcl_Eval(interp, argv[1], 0, 0);\n    if (result != TCL_OK) {\n\tif (result == TCL_ERROR) {\n\t    Tcl_AddErrorInfo(interp, (unsigned char*) \"\\n    (\\\"for\\\" initial command)\");\n\t}\n\treturn result;\n    }\n    while (1) {\n\tresult = Tcl_ExprBoolean(interp, argv[2], &value);\n\tif (result != TCL_OK) {\n\t    return result;\n\t}\n\tif (!value) {\n\t    break;\n\t}\n\tresult = Tcl_Eval(interp, argv[4], 0, 0);\n\tif (result == TCL_CONTINUE) {\n\t    result = TCL_OK;\n\t} else if (result != TCL_OK) {\n\t    if (result == TCL_ERROR) {\n\t\tunsigned char msg[60];\n\t\tsprintf(msg, \"\\n    (\\\"for\\\" body line %d)\", interp->errorLine);\n\t\tTcl_AddErrorInfo(interp, msg);\n\t    }\n\t    break;\n\t}\n\tresult = Tcl_Eval(interp, argv[3], 0, 0);\n\tif (result == TCL_BREAK) {\n\t    break;\n\t} else if (result != TCL_OK) {\n\t    if (result == TCL_ERROR) {\n\t\tTcl_AddErrorInfo(interp, (unsigned char*) \"\\n    (\\\"for\\\" loop-end command)\");\n\t    }\n\t    return result;\n\t}\n    }\n    if (result == TCL_BREAK) {\n\tresult = TCL_OK;\n    }\n    if (result == TCL_OK) {\n\tTcl_ResetResult(interp);\n    }\n    return result;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_ForeachCmd --\n *\n *\tThis procedure is invoked to process the \"foreach\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_ForeachCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int listArgc, i, result;\n    unsigned char **listArgv;\n\n    if (argc != 4) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" varName list command\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n\n    /*\n     * Break the list up into elements, and execute the command once\n     * for each value of the element.\n     */\n\n    result = Tcl_SplitList(interp, argv[2], &listArgc, &listArgv);\n    if (result != TCL_OK) {\n\treturn result;\n    }\n    for (i = 0; i < listArgc; i++) {\n\tif (Tcl_SetVar(interp, argv[1], listArgv[i], 0) == 0) {\n\t    Tcl_SetResult(interp, (unsigned char*) \"couldn't set loop variable\", TCL_STATIC);\n\t    result = TCL_ERROR;\n\t    break;\n\t}\n\n\tresult = Tcl_Eval(interp, argv[3], 0, 0);\n\tif (result != TCL_OK) {\n\t    if (result == TCL_CONTINUE) {\n\t\tresult = TCL_OK;\n\t    } else if (result == TCL_BREAK) {\n\t\tresult = TCL_OK;\n\t\tbreak;\n\t    } else if (result == TCL_ERROR) {\n\t\tunsigned char msg[100];\n\t\tsprintf(msg, \"\\n    (\\\"foreach\\\" body line %d)\",\n\t\t\tinterp->errorLine);\n\t\tTcl_AddErrorInfo(interp, msg);\n\t\tbreak;\n\t    } else {\n\t\tbreak;\n\t    }\n\t}\n    }\n    free (listArgv);\n    if (result == TCL_OK) {\n\tTcl_ResetResult(interp);\n    }\n    return result;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_FormatCmd --\n *\n *\tThis procedure is invoked to process the \"format\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_FormatCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    register unsigned char *format; /* Used to read characters from the format\n\t\t\t\t * string. */\n    unsigned char newFormat[40]; /* A new format specifier is generated here. */\n    int width;\t\t\t/* Field width from field specifier, or 0 if\n\t\t\t\t * no width given. */\n    int precision;\t\t/* Field precision from field specifier, or 0\n\t\t\t\t * if no precision given. */\n    int size;\t\t\t/* Number of bytes needed for result of\n\t\t\t\t * conversion, based on type of conversion\n\t\t\t\t * (\"e\", \"s\", etc.) and width from above. */\n    unsigned char *oneWordValue = 0; /* Used to hold value to pass to sprintf, if\n\t\t\t\t * it's a one-word value. */\n    unsigned char *dst = interp->result; /* Where result is stored.  Starts off at\n\t\t\t\t * interp->resultSpace, but may get dynamically\n\t\t\t\t * re-allocated if this isn't enough. */\n    int dstSize = 0;\t\t/* Number of non-null characters currently\n\t\t\t\t * stored at dst. */\n    int dstSpace = TCL_RESULT_SIZE;\n\t\t\t\t/* Total amount of storage space available\n\t\t\t\t * in dst (not including null terminator. */\n    int noPercent;\t\t/* Special case for speed:  indicates there's\n\t\t\t\t * no field specifier, just a string to copy. */\n    unsigned char **curArg;\t/* Remainder of argv array. */\n    int useShort;\t\t/* Value to be printed is short (half word). */\n\n    /*\n     * This procedure is a bit nasty.  The goal is to use sprintf to\n     * do most of the dirty work.  There are several problems:\n     * 1. this procedure can't trust its arguments.\n     * 2. we must be able to provide a large enough result area to hold\n     *    whatever's generated.  This is hard to estimate.\n     * 2. there's no way to move the arguments from argv to the call\n     *    to sprintf in a reasonable way.  This is particularly nasty\n     *    because some of the arguments may be two-word values (doubles).\n     * So, what happens here is to scan the format string one % group\n     * at a time, making many individual calls to sprintf.\n     */\n\n    if (argc < 2) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" formatString ?arg arg ...?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    curArg = argv+2;\n    argc -= 2;\n    for (format = argv[1]; *format != 0; ) {\n\tregister unsigned char *newPtr = newFormat;\n\n\twidth = precision = noPercent = useShort = 0;\n\n\t/*\n\t * Get rid of any characters before the next field specifier.\n\t * Collapse backslash sequences found along the way.\n\t */\n\n\tif (*format != '%') {\n\t    register unsigned char *p;\n\t    int bsSize;\n\n\t    oneWordValue = p = format;\n\t    while ((*format != '%') && (*format != 0)) {\n\t\tif (*format == '\\\\') {\n\t\t    *p = Tcl_Backslash(format, &bsSize);\n\t\t    if (*p != 0) {\n\t\t\tp++;\n\t\t    }\n\t\t    format += bsSize;\n\t\t} else {\n\t\t    *p = *format;\n\t\t    p++;\n\t\t    format++;\n\t\t}\n\t    }\n\t    size = p - oneWordValue;\n\t    noPercent = 1;\n\t    goto doField;\n\t}\n\n\tif (format[1] == '%') {\n\t    oneWordValue = format;\n\t    size = 1;\n\t    noPercent = 1;\n\t    format += 2;\n\t    goto doField;\n\t}\n\n\t/*\n\t * Parse off a field specifier, compute how many characters\n\t * will be needed to store the result, and substitute for\n\t * \"*\" size specifiers.\n\t */\n\n\t*newPtr = '%';\n\tnewPtr++;\n\tformat++;\n\twhile ((*format == '-') || (*format == '#') || (*format == '0')\n\t\t|| (*format == ' ') || (*format == '+')) {\n\t    *newPtr = *format;\n\t    newPtr++;\n\t    format++;\n\t}\n\tif (isdigit(*format)) {\n\t    width = atoi(format);\n\t    do {\n\t\tformat++;\n\t    } while (isdigit(*format));\n\t} else if (*format == '*') {\n\t    if (argc <= 0) {\n\t\tgoto notEnoughArgs;\n\t    }\n\t    if (Tcl_GetInt(interp, *curArg, &width) != TCL_OK) {\n\t\tgoto fmtError;\n\t    }\n\t    argc--;\n\t    curArg++;\n\t    format++;\n\t}\n\tif (width != 0) {\n\t    sprintf(newPtr, \"%d\", width);\n\t    while (*newPtr != 0) {\n\t\tnewPtr++;\n\t    }\n\t}\n\tif (*format == '.') {\n\t    *newPtr = '.';\n\t    newPtr++;\n\t    format++;\n\t}\n\tif (isdigit(*format)) {\n\t    precision = atoi(format);\n\t    do {\n\t\tformat++;\n\t    } while (isdigit(*format));\n\t} else if (*format == '*') {\n\t    if (argc <= 0) {\n\t\tgoto notEnoughArgs;\n\t    }\n\t    if (Tcl_GetInt(interp, *curArg, &precision) != TCL_OK) {\n\t\tgoto fmtError;\n\t    }\n\t    argc--;\n\t    curArg++;\n\t    format++;\n\t}\n\tif (precision != 0) {\n\t    sprintf(newPtr, \"%d\", precision);\n\t    while (*newPtr != 0) {\n\t\tnewPtr++;\n\t    }\n\t}\n\tif (*format == 'l') {\n\t    format++;\n\t} else if (*format == 'h') {\n\t    useShort = 1;\n\t    *newPtr = 'h';\n\t    newPtr++;\n\t    format++;\n\t}\n\t*newPtr = *format;\n\tnewPtr++;\n\t*newPtr = 0;\n\tif (argc <= 0) {\n\t    goto notEnoughArgs;\n\t}\n\tswitch (*format) {\n\t    case 'D':\n\t    case 'O':\n\t    case 'U':\n\t\tif (!useShort) {\n\t\t    newPtr++;\n\t\t} else {\n\t\t    useShort = 0;\n\t\t}\n\t\tnewPtr[-1] = tolower(*format);\n\t\tnewPtr[-2] = 'l';\n\t\t*newPtr = 0;\n\t    case 'd':\n\t    case 'o':\n\t    case 'u':\n\t    case 'x':\n\t    case 'X':\n\t\tif (Tcl_GetInt(interp, *curArg, (void*) &oneWordValue)\n\t\t\t!= TCL_OK) {\n\t\t    goto fmtError;\n\t\t}\n\t\tsize = 40;\n\t\tbreak;\n\t    case 's':\n\t\toneWordValue = *curArg;\n\t\tsize = strlen(*curArg);\n\t\tbreak;\n\t    case 'c':\n\t\tif (Tcl_GetInt(interp, *curArg, (void*) &oneWordValue)\n\t\t\t!= TCL_OK) {\n\t\t    goto fmtError;\n\t\t}\n\t\tsize = 1;\n\t\tbreak;\n\t    case 0:\n\t\tinterp->result = (unsigned char*)\n\t\t\t\"format string ended in middle of field specifier\";\n\t\tgoto fmtError;\n\t    default:\n\t\tsprintf(interp->result,\n\t\t\t\"bad field specifier \\\"%c\\\"\", *format);\n\t\tgoto fmtError;\n\t}\n\targc--;\n\tcurArg++;\n\tformat++;\n\n\t/*\n\t * Make sure that there's enough space to hold the formatted\n\t * result, then format it.\n\t */\n\n\tdoField:\n\tif (width > size) {\n\t    size = width;\n\t}\n\tif ((dstSize + size) > dstSpace) {\n\t    unsigned char *newDst;\n\t    int newSpace;\n\n\t    newSpace = 2*(dstSize + size);\n\t    newDst = malloc ((unsigned) newSpace+1);\n\t    if (dstSize != 0) {\n\t\tmemcpy ((void*) newDst, (void*) dst, dstSize);\n\t    }\n\t    if (dstSpace != TCL_RESULT_SIZE) {\n\t\tfree (dst);\n\t    }\n\t    dst = newDst;\n\t    dstSpace = newSpace;\n\t}\n\tif (noPercent) {\n\t    memcpy ((void*) (dst+dstSize), (void*) oneWordValue, size);\n\t    dstSize += size;\n\t    dst[dstSize] = 0;\n\t} else {\n\t    if (useShort) {\n\t\t/*\n\t\t * The double cast below is needed for a few machines\n\t\t * (e.g. Pyramids as of 1/93) that don't like casts\n\t\t * directly from pointers to shorts.\n\t\t */\n\t\tsprintf(dst+dstSize, (char*) newFormat, (short) (int) oneWordValue);\n\t    } else {\n\t\tsprintf(dst+dstSize, (char*) newFormat, oneWordValue);\n\t    }\n\t    dstSize += strlen(dst+dstSize);\n\t}\n    }\n\n    interp->result = dst;\n    if (dstSpace != TCL_RESULT_SIZE) {\n\tinterp->freeProc = (Tcl_FreeProc *) free;\n    } else {\n\tinterp->freeProc = 0;\n    }\n    return TCL_OK;\n\n    notEnoughArgs:\n    interp->result = (unsigned char*) \"not enough arguments for all format specifiers\";\n    fmtError:\n    if (dstSpace != TCL_RESULT_SIZE) {\n\tfree(dst);\n    }\n    return TCL_ERROR;\n}\n"
  },
  {
    "path": "lib/libtcl/tclcmdil.c",
    "content": "/*\n * tclCmdIL.c --\n *\n *\tThis file contains the top-level command routines for most of\n *\tthe Tcl built-in commands whose names begin with the letters\n *\tI through L.  It contains only commands in the generic core\n *\t(i.e. those that don't depend much upon UNIX facilities).\n *\n * Copyright 1987-1991 Regents of the University of California\n * Permission to use, copy, modify, and distribute this\n * software and its documentation for any purpose and without\n * fee is hereby granted, provided that the above copyright\n * notice appear in all copies.  The University of California\n * makes no representations about the suitability of this\n * software for any purpose.  It is provided \"as is\" without\n * express or implied warranty.\n */\n#include \"internal.h\"\n\n/*\n * Forward declarations for procedures defined in this file:\n */\n\nstatic int\t\tSortCompareProc (const void *first, const void *second);\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_IfCmd --\n *\n *\tThis procedure is invoked to process the \"if\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_IfCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int i, result, value;\n\n    i = 1;\n    while (1) {\n\t/*\n\t * At this point in the loop, argv and argc refer to an expression\n\t * to test, either for the main expression or an expression\n\t * following an \"elseif\".  The arguments after the expression must\n\t * be \"then\" (optional) and a script to execute if the expression is\n\t * true.\n\t */\n\n\tif (i >= argc) {\n\t    Tcl_AppendResult(interp, \"wrong # args: no expression after \\\"\",\n\t\t    argv[i-1], \"\\\" argument\", 0);\n\t    return TCL_ERROR;\n\t}\n\tresult = Tcl_ExprBoolean(interp, argv[i], &value);\n\tif (result != TCL_OK) {\n\t    return result;\n\t}\n\ti++;\n\tif ((i < argc) && (strcmp(argv[i], (unsigned char*) \"then\") == 0)) {\n\t    i++;\n\t}\n\tif (i >= argc) {\n\t    Tcl_AppendResult(interp, \"wrong # args: no script following \\\"\",\n\t\t    argv[i-1], \"\\\" argument\", 0);\n\t    return TCL_ERROR;\n\t}\n\tif (value) {\n\t    return Tcl_Eval(interp, argv[i], 0, 0);\n\t}\n\n\t/*\n\t * The expression evaluated to false.  Skip the command, then\n\t * see if there is an \"else\" or \"elseif\" clause.\n\t */\n\n\ti++;\n\tif (i >= argc) {\n\t    return TCL_OK;\n\t}\n\tif ((argv[i][0] == 'e') && (strcmp(argv[i], (unsigned char*) \"elseif\") == 0)) {\n\t    i++;\n\t    continue;\n\t}\n\tbreak;\n    }\n\n    /*\n     * Couldn't find a \"then\" or \"elseif\" clause to execute.  Check now\n     * for an \"else\" clause.  We know that there's at least one more\n     * argument when we get here.\n     */\n\n    if (strcmp(argv[i], (unsigned char*) \"else\") == 0) {\n\ti++;\n\tif (i >= argc) {\n\t    Tcl_AppendResult(interp,\n\t\t    \"wrong # args: no script following \\\"else\\\" argument\", 0);\n\t    return TCL_ERROR;\n\t}\n    }\n    return Tcl_Eval(interp, argv[i], 0, 0);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_IncrCmd --\n *\n *\tThis procedure is invoked to process the \"incr\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n    /* ARGSUSED */\nint\nTcl_IncrCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int value;\n    unsigned char *oldString, *result;\n    unsigned char newString[30];\n\n    if ((argc != 2) && (argc != 3)) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" varName ?increment?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n\n    oldString = Tcl_GetVar(interp, argv[1], TCL_LEAVE_ERR_MSG);\n    if (oldString == 0) {\n\treturn TCL_ERROR;\n    }\n    if (Tcl_GetInt(interp, oldString, &value) != TCL_OK) {\n\tTcl_AddErrorInfo(interp, (unsigned char*)\n\t\t\"\\n    (reading value of variable to increment)\");\n\treturn TCL_ERROR;\n    }\n    if (argc == 2) {\n\tvalue += 1;\n    } else {\n\tint increment;\n\n\tif (Tcl_GetInt(interp, argv[2], &increment) != TCL_OK) {\n\t    Tcl_AddErrorInfo(interp, (unsigned char*)\n\t\t    \"\\n    (reading increment)\");\n\t    return TCL_ERROR;\n\t}\n\tvalue += increment;\n    }\n    sprintf(newString, \"%d\", value);\n    result = Tcl_SetVar(interp, argv[1], newString, TCL_LEAVE_ERR_MSG);\n    if (result == 0) {\n\treturn TCL_ERROR;\n    }\n    interp->result = result;\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_InfoCmd --\n *\n *\tThis procedure is invoked to process the \"info\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_InfoCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    register Interp *iPtr = (Interp *) interp;\n    int length;\n    char c;\n    Arg *argPtr;\n    Proc *procPtr;\n    Var *varPtr;\n    Command *cmdPtr;\n    Tcl_HashEntry *hPtr;\n    Tcl_HashSearch search;\n\n    if (argc < 2) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" option ?arg arg ...?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    c = argv[1][0];\n    length = strlen(argv[1]);\n    if ((c == 'a') && (strncmp(argv[1], (unsigned char*) \"args\", length)) == 0) {\n\tif (argc != 3) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\t    argv[0], \" args procname\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tprocPtr = TclFindProc(iPtr, argv[2]);\n\tif (procPtr == 0) {\n\t    infoNoSuchProc:\n\t    Tcl_AppendResult(interp, \"\\\"\", argv[2],\n\t\t    \"\\\" isn't a procedure\", 0);\n\t    return TCL_ERROR;\n\t}\n\tfor (argPtr = procPtr->argPtr; argPtr != 0;\n\t\targPtr = argPtr->nextPtr) {\n\t    Tcl_AppendElement(interp, argPtr->name, 0);\n\t}\n\treturn TCL_OK;\n    } else if ((c == 'b') && (strncmp(argv[1], (unsigned char*) \"body\", length)) == 0) {\n\tif (argc != 3) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" body procname\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tprocPtr = TclFindProc(iPtr, argv[2]);\n\tif (procPtr == 0) {\n\t    goto infoNoSuchProc;\n\t}\n\tiPtr->result = procPtr->command;\n\treturn TCL_OK;\n    } else if ((c == 'c') && (strncmp(argv[1], (unsigned char*) \"cmdcount\", length) == 0)\n\t    && (length >= 2)) {\n\tif (argc != 2) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" cmdcount\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tsprintf(iPtr->result, \"%ld\", iPtr->cmdCount);\n\treturn TCL_OK;\n    } else if ((c == 'c') && (strncmp(argv[1], (unsigned char*) \"commands\", length) == 0)\n\t    && (length >= 4)) {\n\tif (argc > 3) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" commands [pattern]\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tfor (hPtr = Tcl_FirstHashEntry(&iPtr->commandTable, &search);\n\t\thPtr != 0; hPtr = Tcl_NextHashEntry(&search)) {\n\t    unsigned char *name = Tcl_GetHashKey(&iPtr->commandTable, hPtr);\n\t    if ((argc == 3) && !Tcl_StringMatch(name, argv[2])) {\n\t\tcontinue;\n\t    }\n\t    Tcl_AppendElement(interp, name, 0);\n\t}\n\treturn TCL_OK;\n    } else if ((c == 'c') && (strncmp(argv[1], (unsigned char*) \"complete\", length) == 0)\n\t    && (length >= 4)) {\n\tif (argc != 3) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" complete command\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tif (Tcl_CommandComplete(argv[2])) {\n\t    interp->result = (unsigned char*) \"1\";\n\t} else {\n\t    interp->result = (unsigned char*) \"0\";\n\t}\n\treturn TCL_OK;\n    } else if ((c == 'd') && (strncmp(argv[1], (unsigned char*) \"default\", length)) == 0) {\n\tif (argc != 5) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\t    argv[0], \" default procname arg varname\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tprocPtr = TclFindProc(iPtr, argv[2]);\n\tif (procPtr == 0) {\n\t    goto infoNoSuchProc;\n\t}\n\tfor (argPtr = procPtr->argPtr; ; argPtr = argPtr->nextPtr) {\n\t    if (argPtr == 0) {\n\t\tTcl_AppendResult(interp, \"procedure \\\"\", argv[2],\n\t\t\t\"\\\" doesn't have an argument \\\"\", argv[3],\n\t\t\t\"\\\"\", 0);\n\t\treturn TCL_ERROR;\n\t    }\n\t    if (strcmp(argv[3], argPtr->name) == 0) {\n\t\tif (argPtr->defValue != 0) {\n\t\t    if (Tcl_SetVar((Tcl_Interp *) iPtr, argv[4],\n\t\t\t    argPtr->defValue, 0) == 0) {\n\t\t\tdefStoreError:\n\t\t\tTcl_AppendResult(interp,\n\t\t\t\t\"couldn't store default value in variable \\\"\",\n\t\t\t\targv[4], \"\\\"\", 0);\n\t\t\treturn TCL_ERROR;\n\t\t    }\n\t\t    iPtr->result = (unsigned char*) \"1\";\n\t\t} else {\n\t\t    if (Tcl_SetVar((Tcl_Interp *) iPtr, argv[4], (unsigned char*) \"\", 0)\n\t\t\t    == 0) {\n\t\t\tgoto defStoreError;\n\t\t    }\n\t\t    iPtr->result = (unsigned char*) \"0\";\n\t\t}\n\t\treturn TCL_OK;\n\t    }\n\t}\n    } else if ((c == 'e') && (strncmp(argv[1], (unsigned char*) \"exists\", length) == 0)) {\n\tunsigned char *p;\n\tif (argc != 3) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" exists varName\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tp = Tcl_GetVar((Tcl_Interp *) iPtr, argv[2], 0);\n\n\t/*\n\t * The code below handles the special case where the name is for\n\t * an array:  Tcl_GetVar will reject this since you can't read\n\t * an array variable without an index.\n\t */\n\n\tif (p == 0) {\n\t    Tcl_HashEntry *hPtr;\n\t    Var *varPtr;\n\n\t    if (strchr(argv[2], '(') != 0) {\n\t\tnoVar:\n\t\tiPtr->result = (unsigned char*) \"0\";\n\t\treturn TCL_OK;\n\t    }\n\t    if (iPtr->varFramePtr == 0) {\n\t\thPtr = Tcl_FindHashEntry(&iPtr->globalTable, argv[2]);\n\t    } else {\n\t\thPtr = Tcl_FindHashEntry(&iPtr->varFramePtr->varTable, argv[2]);\n\t    }\n\t    if (hPtr == 0) {\n\t\tgoto noVar;\n\t    }\n\t    varPtr = (Var *) Tcl_GetHashValue(hPtr);\n\t    if (varPtr->flags & VAR_UPVAR) {\n\t\tvarPtr = (Var *) Tcl_GetHashValue(varPtr->value.upvarPtr);\n\t    }\n\t    if (!(varPtr->flags & VAR_ARRAY)) {\n\t\tgoto noVar;\n\t    }\n\t}\n\tiPtr->result = (unsigned char*) \"1\";\n\treturn TCL_OK;\n    } else if ((c == 'g') && (strncmp(argv[1], (unsigned char*) \"globals\", length) == 0)) {\n\tunsigned char *name;\n\n\tif (argc > 3) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" globals [pattern]\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tfor (hPtr = Tcl_FirstHashEntry(&iPtr->globalTable, &search);\n\t\thPtr != 0; hPtr = Tcl_NextHashEntry(&search)) {\n\t    varPtr = (Var *) Tcl_GetHashValue(hPtr);\n\t    if (varPtr->flags & VAR_UNDEFINED) {\n\t\tcontinue;\n\t    }\n\t    name = Tcl_GetHashKey(&iPtr->globalTable, hPtr);\n\t    if ((argc == 3) && !Tcl_StringMatch(name, argv[2])) {\n\t\tcontinue;\n\t    }\n\t    Tcl_AppendElement(interp, name, 0);\n\t}\n\treturn TCL_OK;\n    } else if ((c == 'l') && (strncmp(argv[1], (unsigned char*) \"level\", length) == 0)\n\t    && (length >= 2)) {\n\tif (argc == 2) {\n\t    if (iPtr->varFramePtr == 0) {\n\t\tiPtr->result = (unsigned char*) \"0\";\n\t    } else {\n\t\tsprintf(iPtr->result, \"%d\", iPtr->varFramePtr->level);\n\t    }\n\t    return TCL_OK;\n\t} else if (argc == 3) {\n\t    int level;\n\t    CallFrame *framePtr;\n\n\t    if (Tcl_GetInt(interp, argv[2], &level) != TCL_OK) {\n\t\treturn TCL_ERROR;\n\t    }\n\t    if (level <= 0) {\n\t\tif (iPtr->varFramePtr == 0) {\n\t\t    levelError:\n\t\t    Tcl_AppendResult(interp, \"bad level \\\"\", argv[2],\n\t\t\t    \"\\\"\", 0);\n\t\t    return TCL_ERROR;\n\t\t}\n\t\tlevel += iPtr->varFramePtr->level;\n\t    }\n\t    for (framePtr = iPtr->varFramePtr; framePtr != 0;\n\t\t    framePtr = framePtr->callerVarPtr) {\n\t\tif (framePtr->level == level) {\n\t\t    break;\n\t\t}\n\t    }\n\t    if (framePtr == 0) {\n\t\tgoto levelError;\n\t    }\n\t    iPtr->result = Tcl_Merge (framePtr->argc, framePtr->argv);\n\t    iPtr->freeProc = (Tcl_FreeProc *) free;\n\t    return TCL_OK;\n\t}\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" level [number]\\\"\", 0);\n\treturn TCL_ERROR;\n#ifdef TCL_FILE_CMDS\n    } else if ((c == 'l') && (strncmp(argv[1], \"library\", length) == 0)\n\t    && (length >= 2)) {\n\tif (argc != 2) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" library\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tinterp->result = getenv(\"TCL_LIBRARY\");\n\tif (interp->result == 0) {\n#ifdef TCL_LIBRARY\n\t    interp->result = TCL_LIBRARY;\n#else\n\t    interp->result = \"there is no Tcl library at this installation\";\n\t    return TCL_ERROR;\n#endif\n\t}\n\treturn TCL_OK;\n#endif\n    } else if ((c == 'l') && (strncmp(argv[1], (unsigned char*) \"locals\", length) == 0)\n\t    && (length >= 2)) {\n\tunsigned char *name;\n\n\tif (argc > 3) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" locals [pattern]\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tif (iPtr->varFramePtr == 0) {\n\t    return TCL_OK;\n\t}\n\tfor (hPtr = Tcl_FirstHashEntry(&iPtr->varFramePtr->varTable, &search);\n\t\thPtr != 0; hPtr = Tcl_NextHashEntry(&search)) {\n\t    varPtr = (Var *) Tcl_GetHashValue(hPtr);\n\t    if (varPtr->flags & (VAR_UNDEFINED|VAR_UPVAR)) {\n\t\tcontinue;\n\t    }\n\t    name = Tcl_GetHashKey(&iPtr->varFramePtr->varTable, hPtr);\n\t    if ((argc == 3) && !Tcl_StringMatch(name, argv[2])) {\n\t\tcontinue;\n\t    }\n\t    Tcl_AppendElement(interp, name, 0);\n\t}\n\treturn TCL_OK;\n    } else if ((c == 'p') && (strncmp(argv[1], (unsigned char*) \"procs\", length)) == 0) {\n\tif (argc > 3) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" procs [pattern]\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tfor (hPtr = Tcl_FirstHashEntry(&iPtr->commandTable, &search);\n\t\thPtr != 0; hPtr = Tcl_NextHashEntry(&search)) {\n\t    unsigned char *name = Tcl_GetHashKey(&iPtr->commandTable, hPtr);\n\n\t    cmdPtr = (Command *) Tcl_GetHashValue(hPtr);\n\t    if (!TclIsProc(cmdPtr)) {\n\t\tcontinue;\n\t    }\n\t    if ((argc == 3) && !Tcl_StringMatch(name, argv[2])) {\n\t\tcontinue;\n\t    }\n\t    Tcl_AppendElement(interp, name, 0);\n\t}\n\treturn TCL_OK;\n    } else if ((c == 's') && (strncmp(argv[1], (unsigned char*) \"script\", length) == 0)) {\n\tif (argc != 2) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\t    argv[0], \" script\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tif (iPtr->scriptFile != 0) {\n\t    interp->result = iPtr->scriptFile;\n\t}\n\treturn TCL_OK;\n    } else if ((c == 't') && (strncmp(argv[1], (unsigned char*) \"tclversion\", length) == 0)) {\n\tif (argc != 2) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\t    argv[0], \" tclversion\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\n\t/*\n\t * Note:  TCL_VERSION below is expected to be set with a \"-D\"\n\t * switch in the Makefile.\n\t */\n\n\tstrcpy(iPtr->result, (unsigned char*) TCL_VERSION);\n\treturn TCL_OK;\n    } else if ((c == 'v') && (strncmp(argv[1], (unsigned char*) \"vars\", length)) == 0) {\n\tTcl_HashTable *tablePtr;\n\tunsigned char *name;\n\n\tif (argc > 3) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\t    argv[0], \" vars [pattern]\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tif (iPtr->varFramePtr == 0) {\n\t    tablePtr = &iPtr->globalTable;\n\t} else {\n\t    tablePtr = &iPtr->varFramePtr->varTable;\n\t}\n\tfor (hPtr = Tcl_FirstHashEntry(tablePtr, &search);\n\t\thPtr != 0; hPtr = Tcl_NextHashEntry(&search)) {\n\t    varPtr = (Var *) Tcl_GetHashValue(hPtr);\n\t    if (varPtr->flags & VAR_UNDEFINED) {\n\t\tcontinue;\n\t    }\n\t    name = Tcl_GetHashKey(tablePtr, hPtr);\n\t    if ((argc == 3) && !Tcl_StringMatch(name, argv[2])) {\n\t\tcontinue;\n\t    }\n\t    Tcl_AppendElement(interp, name, 0);\n\t}\n\treturn TCL_OK;\n    } else {\n\tTcl_AppendResult(interp, \"bad option \\\"\", argv[1],\n\t\t\"\\\": should be args, body, cmdcount, commands, \",\n\t\t\"complete, default, \",\n\t\t\"exists, globals, level, library, locals, procs, \",\n\t\t\"script, tclversion, or vars\", 0);\n\treturn TCL_ERROR;\n    }\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_JoinCmd --\n *\n *\tThis procedure is invoked to process the \"join\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_JoinCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    unsigned char *joinString;\n    unsigned char **listArgv;\n    int listArgc, i;\n\n    if (argc == 2) {\n\tjoinString = (unsigned char*) \" \";\n    } else if (argc == 3) {\n\tjoinString = argv[2];\n    } else {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" list ?joinString?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n\n    if (Tcl_SplitList(interp, argv[1], &listArgc, &listArgv) != TCL_OK) {\n\treturn TCL_ERROR;\n    }\n    for (i = 0; i < listArgc; i++) {\n\tif (i == 0) {\n\t    Tcl_AppendResult(interp, listArgv[0], 0);\n\t} else  {\n\t    Tcl_AppendResult(interp, joinString, listArgv[i], 0);\n\t}\n    }\n    free (listArgv);\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_LindexCmd --\n *\n *\tThis procedure is invoked to process the \"lindex\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n    /* ARGSUSED */\nint\nTcl_LindexCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    unsigned char *p, *element;\n    int index, size, parenthesized, result;\n\n    if (argc != 3) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" list index\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    if (Tcl_GetInt(interp, argv[2], &index) != TCL_OK) {\n\treturn TCL_ERROR;\n    }\n    if (index < 0) {\n\treturn TCL_OK;\n    }\n    for (p = argv[1] ; index >= 0; index--) {\n\tresult = TclFindElement(interp, p, &element, &p, &size,\n\t\t&parenthesized);\n\tif (result != TCL_OK) {\n\t    return result;\n\t}\n    }\n    if (size == 0) {\n\treturn TCL_OK;\n    }\n    if (size >= TCL_RESULT_SIZE) {\n\tinterp->result = malloc ((unsigned) size + 1);\n\tinterp->freeProc = (Tcl_FreeProc *) free;\n    }\n    if (parenthesized) {\n\tmemcpy((void *) interp->result, (void *) element, size);\n\tinterp->result[size] = 0;\n    } else {\n\tTclCopyAndCollapse(size, element, interp->result);\n    }\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_LinsertCmd --\n *\n *\tThis procedure is invoked to process the \"linsert\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_LinsertCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    unsigned char *p, *element, savedChar;\n    int i, index, count, result, size;\n\n    if (argc < 4) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" list index element ?element ...?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    if (Tcl_GetInt(interp, argv[2], &index) != TCL_OK) {\n\treturn TCL_ERROR;\n    }\n\n    /*\n     * Skip over the first \"index\" elements of the list, then add\n     * all of those elements to the result.\n     */\n\n    size = 0;\n    element = argv[1];\n    for (count = 0, p = argv[1]; (count < index) && (*p != 0); count++) {\n\tresult = TclFindElement(interp, p, &element, &p, &size, (int *) 0);\n\tif (result != TCL_OK) {\n\t    return result;\n\t}\n    }\n    if (*p == 0) {\n\tTcl_AppendResult(interp, argv[1], 0);\n    } else {\n\tunsigned char *end;\n\n\tend = element+size;\n\tif (element != argv[1]) {\n\t    while ((*end != 0) && !isspace(*end)) {\n\t\tend++;\n\t    }\n\t}\n\tsavedChar = *end;\n\t*end = 0;\n\tTcl_AppendResult(interp, argv[1], 0);\n\t*end = savedChar;\n    }\n\n    /*\n     * Add the new list elements.\n     */\n\n    for (i = 3; i < argc; i++) {\n\tTcl_AppendElement(interp, argv[i], 0);\n    }\n\n    /*\n     * Append the remainder of the original list.\n     */\n\n    if (*p != 0) {\n\tTcl_AppendResult(interp, \" \", p, 0);\n    }\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_ListCmd --\n *\n *\tThis procedure is invoked to process the \"list\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_ListCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    if (argc < 2) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" arg ?arg ...?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    interp->result = Tcl_Merge (argc-1, argv+1);\n    interp->freeProc = (Tcl_FreeProc *) free;\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_LlengthCmd --\n *\n *\tThis procedure is invoked to process the \"llength\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_LlengthCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int count, result;\n    unsigned char *element, *p;\n\n    if (argc != 2) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" list\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    for (count = 0, p = argv[1]; *p != 0 ; count++) {\n\tresult = TclFindElement(interp, p, &element, &p, (int *) 0,\n\t\t(int *) 0);\n\tif (result != TCL_OK) {\n\t    return result;\n\t}\n\tif (*element == 0) {\n\t    break;\n\t}\n    }\n    sprintf(interp->result, \"%d\", count);\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_LrangeCmd --\n *\n *\tThis procedure is invoked to process the \"lrange\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_LrangeCmd(notUsed, interp, argc, argv)\n    void *notUsed;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int first, last, result;\n    unsigned char *begin, *end, c, *dummy;\n    int count;\n\n    if (argc != 4) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" list first last\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    if (Tcl_GetInt(interp, argv[2], &first) != TCL_OK) {\n\treturn TCL_ERROR;\n    }\n    if (first < 0) {\n\tfirst = 0;\n    }\n    if ((*argv[3] == 'e') && (strncmp(argv[3], (unsigned char*) \"end\", strlen(argv[3])) == 0)) {\n\tlast = 30000;\n    } else {\n\tif (Tcl_GetInt(interp, argv[3], &last) != TCL_OK) {\n\t    Tcl_ResetResult(interp);\n\t    Tcl_AppendResult(interp,\n\t\t    \"expected integer or \\\"end\\\" but got \\\"\",\n\t\t    argv[3], \"\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n    }\n    if (first > last) {\n\treturn TCL_OK;\n    }\n\n    /*\n     * Extract a range of fields.\n     */\n\n    for (count = 0, begin = argv[1]; count < first; count++) {\n\tresult = TclFindElement(interp, begin, &dummy, &begin, (int *) 0,\n\t\t(int *) 0);\n\tif (result != TCL_OK) {\n\t    return result;\n\t}\n\tif (*begin == 0) {\n\t    break;\n\t}\n    }\n    for (count = first, end = begin; (count <= last) && (*end != 0);\n\t    count++) {\n\tresult = TclFindElement(interp, end, &dummy, &end, (int *) 0,\n\t\t(int *) 0);\n\tif (result != TCL_OK) {\n\t    return result;\n\t}\n    }\n\n    /*\n     * Chop off trailing spaces.\n     */\n\n    while (isspace(end[-1])) {\n\tend--;\n    }\n    c = *end;\n    *end = 0;\n    Tcl_SetResult(interp, begin, TCL_VOLATILE);\n    *end = c;\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_LreplaceCmd --\n *\n *\tThis procedure is invoked to process the \"lreplace\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_LreplaceCmd(notUsed, interp, argc, argv)\n    void *notUsed;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    unsigned char *p1, *p2, *element, savedChar, *dummy;\n    int i, first, last, count, result, size;\n\n    if (argc < 4) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" list first last ?element element ...?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    if (Tcl_GetInt(interp, argv[2], &first) != TCL_OK) {\n\treturn TCL_ERROR;\n    }\n    if (TclGetListIndex(interp, argv[3], &last) != TCL_OK) {\n\treturn TCL_ERROR;\n    }\n    if (first < 0) {\n\tfirst = 0;\n    }\n    if (last < 0) {\n\tlast = 0;\n    }\n    if (first > last) {\n\tTcl_AppendResult(interp, \"first index must not be greater than second\", 0);\n\treturn TCL_ERROR;\n    }\n\n    /*\n     * Skip over the elements of the list before \"first\".\n     */\n\n    size = 0;\n    element = argv[1];\n    for (count = 0, p1 = argv[1]; (count < first) && (*p1 != 0); count++) {\n\tresult = TclFindElement(interp, p1, &element, &p1, &size,\n\t\t(int *) 0);\n\tif (result != TCL_OK) {\n\t    return result;\n\t}\n    }\n    if (*p1 == 0) {\n\tTcl_AppendResult(interp, \"list doesn't contain element \",\n\t\targv[2], 0);\n\treturn TCL_ERROR;\n    }\n\n    /*\n     * Skip over the elements of the list up through \"last\".\n     */\n\n    for (p2 = p1 ; (count <= last) && (*p2 != 0); count++) {\n\tresult = TclFindElement(interp, p2, &dummy, &p2, (int *) 0,\n\t\t(int *) 0);\n\tif (result != TCL_OK) {\n\t    return result;\n\t}\n    }\n\n    /*\n     * Add the elements before \"first\" to the result.  Be sure to\n     * include quote or brace characters that might terminate the\n     * last of these elements.\n     */\n\n    p1 = element+size;\n    if (element != argv[1]) {\n\twhile ((*p1 != 0) && !isspace(*p1)) {\n\t    p1++;\n\t}\n    }\n    savedChar = *p1;\n    *p1 = 0;\n    Tcl_AppendResult(interp, argv[1], 0);\n    *p1 = savedChar;\n\n    /*\n     * Add the new list elements.\n     */\n\n    for (i = 4; i < argc; i++) {\n\tTcl_AppendElement(interp, argv[i], 0);\n    }\n\n    /*\n     * Append the remainder of the original list.\n     */\n\n    if (*p2 != 0) {\n\tif (*interp->result == 0) {\n\t    Tcl_SetResult(interp, p2, TCL_VOLATILE);\n\t} else {\n\t    Tcl_AppendResult(interp, \" \", p2, 0);\n\t}\n    }\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_LsearchCmd --\n *\n *\tThis procedure is invoked to process the \"lsearch\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_LsearchCmd(notUsed, interp, argc, argv)\n    void *notUsed;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int listArgc;\n    unsigned char **listArgv;\n    int i, match;\n\n    if (argc != 3) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" list pattern\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    if (Tcl_SplitList(interp, argv[1], &listArgc, &listArgv) != TCL_OK) {\n\treturn TCL_ERROR;\n    }\n    match = -1;\n    for (i = 0; i < listArgc; i++) {\n\tif (Tcl_StringMatch(listArgv[i], argv[2])) {\n\t    match = i;\n\t    break;\n\t}\n    }\n    sprintf (interp->result, \"%d\", match);\n    free (listArgv);\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_LsortCmd --\n *\n *\tThis procedure is invoked to process the \"lsort\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_LsortCmd(notUsed, interp, argc, argv)\n    void *notUsed;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int listArgc;\n    unsigned char **listArgv;\n\n    if (argc != 2) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" list\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    if (Tcl_SplitList(interp, argv[1], &listArgc, &listArgv) != TCL_OK) {\n\treturn TCL_ERROR;\n    }\n    qsort((void *) listArgv, listArgc, sizeof (char*), SortCompareProc);\n    interp->result = Tcl_Merge (listArgc, listArgv);\n    interp->freeProc = (Tcl_FreeProc *) free;\n    free (listArgv);\n    return TCL_OK;\n}\n\n/*\n * The procedure below is called back by qsort to determine\n * the proper ordering between two elements.\n */\n\nstatic int\nSortCompareProc(first, second)\n    const void *first, *second;\t\t/* Elements to be compared. */\n{\n    return strcmp(*((unsigned char **) first), *((unsigned char **) second));\n}\n"
  },
  {
    "path": "lib/libtcl/tclcmdmz.c",
    "content": "/*\n * tclCmdMZ.c --\n *\n *\tThis file contains the top-level command routines for most of\n *\tthe Tcl built-in commands whose names begin with the letters\n *\tM to Z.  It contains only commands in the generic core (i.e.\n *\tthose that don't depend much upon UNIX facilities).\n *\n * Copyright 1987-1991 Regents of the University of California\n * Permission to use, copy, modify, and distribute this\n * software and its documentation for any purpose and without\n * fee is hereby granted, provided that the above copyright\n * notice appear in all copies.  The University of California\n * makes no representations about the suitability of this\n * software for any purpose.  It is provided \"as is\" without\n * express or implied warranty.\n */\n#include \"internal.h\"\n#include \"regexp.h\"\n#include \"regpriv.h\"\n\n/*\n * Structure used to hold information about variable traces:\n */\n\ntypedef struct {\n    int flags;\t\t\t/* Operations for which Tcl command is\n\t\t\t\t * to be invoked. */\n    int length;\t\t\t/* Number of non-NULL chars. in command. */\n    unsigned char command[4];\t/* Space for Tcl command to invoke.  Actual\n\t\t\t\t * size will be as large as necessary to\n\t\t\t\t * hold command.  This field must be the\n\t\t\t\t * last in the structure, so that it can\n\t\t\t\t * be larger than 4 bytes. */\n} TraceVarInfo;\n\n/*\n * Forward declarations for procedures defined in this file:\n */\n\nstatic unsigned char *\tTraceVarProc (void *clientData,\n\t\t\t    Tcl_Interp *interp, unsigned char *name1,\n\t\t\t    unsigned char *name2, int flags);\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_RegexpCmd --\n *\n *\tThis procedure is invoked to process the \"regexp\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_RegexpCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int noCase = 0;\n    int indices = 0;\n    regexp_t *regexpPtr;\n    unsigned char **argPtr, *string;\n    int match, i;\n\n    if (argc < 3) {\n\twrongNumArgs:\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" ?-nocase? exp string ?matchVar? ?subMatchVar \",\n\t\t\"subMatchVar ...?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    argPtr = argv+1;\n    argc--;\n    while ((argc > 0) && (argPtr[0][0] == '-')) {\n\tif (strcmp(argPtr[0], (unsigned char*) \"-indices\") == 0) {\n\t    argPtr++;\n\t    argc--;\n\t    indices = 1;\n\t} else if (strcmp(argPtr[0], (unsigned char*) \"-nocase\") == 0) {\n\t    argPtr++;\n\t    argc--;\n\t    noCase = 1;\n\t} else {\n\t    break;\n\t}\n    }\n    if (argc < 2) {\n\tgoto wrongNumArgs;\n    }\n    regexpPtr = TclCompileRegexp(interp, argPtr[0]);\n    if (regexpPtr == 0) {\n\treturn TCL_ERROR;\n    }\n\n    /*\n     * Convert the string to lower case, if desired, and perform\n     * the match.\n     */\n    if (noCase) {\n\tregister unsigned char *dst, *src;\n\n\tstring = malloc (strlen(argPtr[1]) + 1);\n\tfor (src = argPtr[1], dst = string; *src != 0; src++, dst++) {\n\t    if (isupper(*src)) {\n\t\t*dst = tolower(*src);\n\t    } else {\n\t\t*dst = *src;\n\t    }\n\t}\n\t*dst = 0;\n    } else {\n\tstring = argPtr[1];\n    }\n    match = regexp_execute (regexpPtr, string);\n    if (string != argPtr[1]) {\n\tfree(string);\n    }\n    if (match) {\n\tinterp->result = (unsigned char*) \"0\";\n\treturn TCL_OK;\n    }\n\n    /*\n     * If additional variable names have been specified, return\n     * index information in those variables.\n     */\n\n    argc -= 2;\n    if (argc > 10) {\n\tinterp->result = (unsigned char*) \"too many substring variables\";\n\treturn TCL_ERROR;\n    }\n    for (i = 0; i < argc; i++) {\n\tunsigned char *result, info[50];\n\n\tif (regexpPtr->startp[i] == 0) {\n\t    if (indices) {\n\t\tresult = Tcl_SetVar(interp, argPtr[i+2], (unsigned char*) \"-1 -1\", 0);\n\t    } else {\n\t\tresult = Tcl_SetVar(interp, argPtr[i+2], (unsigned char*) \"\", 0);\n\t    }\n\t} else {\n\t    if (indices) {\n\t\tsprintf(info, \"%d %d\", (int) (regexpPtr->startp[i] - string),\n\t\t\t(int) (regexpPtr->endp[i] - string - 1));\n\t\tresult = Tcl_SetVar(interp, argPtr[i+2], info, 0);\n\t    } else {\n\t\tunsigned char savedChar, *first, *last;\n\n\t\tfirst = argPtr[1] + (regexpPtr->startp[i] - string);\n\t\tlast = argPtr[1] + (regexpPtr->endp[i] - string);\n\t\tsavedChar = *last;\n\t\t*last = 0;\n\t\tresult = Tcl_SetVar(interp, argPtr[i+2], first, 0);\n\t\t*last = savedChar;\n\t    }\n\t}\n\tif (result == 0) {\n\t    Tcl_AppendResult(interp, \"couldn't set variable \\\"\",\n\t\t    argPtr[i+2], \"\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n    }\n    interp->result = (unsigned char*) \"1\";\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_RegsubCmd --\n *\n *\tThis procedure is invoked to process the \"regsub\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_RegsubCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int noCase = 0, all = 0;\n    regexp_t *regexpPtr;\n    unsigned char *string, *p, *firstChar, *newValue, **argPtr;\n    int match, result, flags;\n    register unsigned char *src, c;\n\n    if (argc < 5) {\n\twrongNumArgs:\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" ?-nocase? ?-all? exp string subSpec varName\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    argPtr = argv+1;\n    argc--;\n    while (argPtr[0][0] == '-') {\n\tif (strcmp(argPtr[0], (unsigned char*) \"-nocase\") == 0) {\n\t    argPtr++;\n\t    argc--;\n\t    noCase = 1;\n\t} else if (strcmp(argPtr[0], (unsigned char*) \"-all\") == 0) {\n\t    argPtr++;\n\t    argc--;\n\t    all = 1;\n\t} else {\n\t    break;\n\t}\n    }\n    if (argc != 4) {\n\tgoto wrongNumArgs;\n    }\n    regexpPtr = TclCompileRegexp(interp, argPtr[0]);\n    if (regexpPtr == 0) {\n\treturn TCL_ERROR;\n    }\n\n    /*\n     * Convert the string to lower case, if desired.\n     */\n\n    if (noCase) {\n\tregister unsigned char *dst;\n\n\tstring = malloc (strlen(argPtr[1]) + 1);\n\tfor (src = argPtr[1], dst = string; *src != 0; src++, dst++) {\n\t    if (isupper(*src)) {\n\t\t*dst = tolower(*src);\n\t    } else {\n\t\t*dst = *src;\n\t    }\n\t}\n\t*dst = 0;\n    } else {\n\tstring = argPtr[1];\n    }\n\n    /*\n     * The following loop is to handle multiple matches within the\n     * same source string;  each iteration handles one match and its\n     * corresponding substitution.  If \"-all\" hasn't been specified\n     * then the loop body only gets executed once.\n     */\n\n    flags = 0;\n    for (p = string; *p != 0; ) {\n\tmatch = regexp_execute (regexpPtr, p);\n\tif (match) {\n\t    break;\n\t}\n\n\t/*\n\t * Copy the portion of the source string before the match to the\n\t * result variable.\n\t */\n\n\tsrc = argPtr[1] + (regexpPtr->startp[0] - string);\n\tc = *src;\n\t*src = 0;\n\tnewValue = Tcl_SetVar(interp, argPtr[3], argPtr[1] + (p - string),\n\t\tflags);\n\t*src = c;\n\tflags = TCL_APPEND_VALUE;\n\tif (newValue == 0) {\n\t    cantSet:\n\t    Tcl_AppendResult(interp, \"couldn't set variable \\\"\",\n\t\t    argPtr[3], \"\\\"\", 0);\n\t    result = TCL_ERROR;\n\t    goto done;\n\t}\n\n\t/*\n\t * Append the subSpec argument to the variable, making appropriate\n\t * substitutions.  This code is a bit hairy because of the backslash\n\t * conventions and because the code saves up ranges of characters in\n\t * subSpec to reduce the number of calls to Tcl_SetVar.\n\t */\n\tfor (src = firstChar = argPtr[2], c = *src; c != 0; src++, c = *src) {\n\t    int index;\n\n\t    if (c == '&') {\n\t\tindex = 0;\n\t    } else if (c == '\\\\') {\n\t\tc = src[1];\n\t\tif ((c >= '0') && (c <= '9')) {\n\t\t    index = c - '0';\n\t\t} else if ((c == '\\\\') || (c == '&')) {\n\t\t    *src = c;\n\t\t    src[1] = 0;\n\t\t    newValue = Tcl_SetVar(interp, argPtr[3], firstChar,\n\t\t\t    TCL_APPEND_VALUE);\n\t\t    *src = '\\\\';\n\t\t    src[1] = c;\n\t\t    if (newValue == 0) {\n\t\t\tgoto cantSet;\n\t\t    }\n\t\t    firstChar = src+2;\n\t\t    src++;\n\t\t    continue;\n\t\t} else {\n\t\t    continue;\n\t\t}\n\t    } else {\n\t\tcontinue;\n\t    }\n\t    if (firstChar != src) {\n\t\tc = *src;\n\t\t*src = 0;\n\t\tnewValue = Tcl_SetVar(interp, argPtr[3], firstChar,\n\t\t\tTCL_APPEND_VALUE);\n\t\t*src = c;\n\t\tif (newValue == 0) {\n\t\t    goto cantSet;\n\t\t}\n\t    }\n\t    if ((index < 10) && (regexpPtr->startp[index] != 0)\n\t\t    && (regexpPtr->endp[index] != 0)) {\n\t\tunsigned char *first, *last, saved;\n\n\t\tfirst = argPtr[1] + (regexpPtr->startp[index] - string);\n\t\tlast = argPtr[1] + (regexpPtr->endp[index] - string);\n\t\tsaved = *last;\n\t\t*last = 0;\n\t\tnewValue = Tcl_SetVar(interp, argPtr[3], first,\n\t\t\tTCL_APPEND_VALUE);\n\t\t*last = saved;\n\t\tif (newValue == 0) {\n\t\t    goto cantSet;\n\t\t}\n\t    }\n\t    if (*src == '\\\\') {\n\t\tsrc++;\n\t    }\n\t    firstChar = src+1;\n\t}\n\tif (firstChar != src) {\n\t    if (Tcl_SetVar(interp, argPtr[3], firstChar,\n\t\t    TCL_APPEND_VALUE) == 0) {\n\t\tgoto cantSet;\n\t    }\n\t}\n\tp = (unsigned char*) regexpPtr->endp[0];\n\tif (!all) {\n\t    break;\n\t}\n    }\n\n    /*\n     * If there were no matches at all, then return a \"0\" result.\n     */\n\n    if (p == string) {\n\tinterp->result = (unsigned char*) \"0\";\n\tresult = TCL_OK;\n\tgoto done;\n    }\n\n    /*\n     * Copy the portion of the source string after the last match to the\n     * result variable.\n     */\n\n    if (*p != 0) {\n\tif (Tcl_SetVar(interp, argPtr[3], p, TCL_APPEND_VALUE) == 0) {\n\t    goto cantSet;\n\t}\n    }\n    interp->result = (unsigned char*) \"1\";\n    result = TCL_OK;\n\n    done:\n    if (string != argPtr[1]) {\n\tfree(string);\n    }\n    return result;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_RenameCmd --\n *\n *\tThis procedure is invoked to process the \"rename\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_RenameCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    register Command *cmdPtr;\n    Interp *iPtr = (Interp *) interp;\n    Tcl_HashEntry *hPtr;\n    int new;\n\n    if (argc != 3) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" oldName newName\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    if (argv[2][0] == '\\0') {\n\tif (Tcl_DeleteCommand(interp, argv[1]) != 0) {\n\t    Tcl_AppendResult(interp, \"can't delete \\\"\", argv[1],\n\t\t    \"\\\": command doesn't exist\", 0);\n\t    return TCL_ERROR;\n\t}\n\treturn TCL_OK;\n    }\n    hPtr = Tcl_FindHashEntry(&iPtr->commandTable, argv[2]);\n    if (hPtr != 0) {\n\tTcl_AppendResult(interp, \"can't rename to \\\"\", argv[2],\n\t\t\"\\\": command already exists\", 0);\n\treturn TCL_ERROR;\n    }\n    hPtr = Tcl_FindHashEntry(&iPtr->commandTable, argv[1]);\n    if (hPtr == 0) {\n\tTcl_AppendResult(interp, \"can't rename \\\"\", argv[1],\n\t\t\"\\\":  command doesn't exist\", 0);\n\treturn TCL_ERROR;\n    }\n    cmdPtr = (Command *) Tcl_GetHashValue(hPtr);\n    Tcl_DeleteHashEntry(hPtr);\n    hPtr = Tcl_CreateHashEntry(&iPtr->commandTable, argv[2], &new);\n    Tcl_SetHashValue(hPtr, cmdPtr);\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_ReturnCmd --\n *\n *\tThis procedure is invoked to process the \"return\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_ReturnCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    if (argc > 2) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" ?value?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    if (argc == 2) {\n\tTcl_SetResult(interp, argv[1], TCL_VOLATILE);\n    }\n    return TCL_RETURN;\n}\n\f\n/*\n * This procedure is invoked to process the \"scan\" Tcl command.\n * See the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n */\n\t/* ARGSUSED */\nint\nTcl_ScanCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int arg1Length;\t\t\t/* Number of bytes in argument to be\n\t\t\t\t\t * scanned.  This gives an upper limit\n\t\t\t\t\t * on string field sizes. */\n#   define MAX_FIELDS 20\n    typedef struct {\n\tunsigned char fmt;\t\t/* Format for field. */\n\tint size;\t\t\t/* How many bytes to allow for\n\t\t\t\t\t * field. */\n\tunsigned char *location;\t/* Where field will be stored. */\n    } Field;\n    Field fields[MAX_FIELDS];\t\t/* Info about all the fields in the\n\t\t\t\t\t * format string. */\n    register Field *curField;\n    int numFields = 0;\t\t\t/* Number of fields actually\n\t\t\t\t\t * specified. */\n    int suppress;\t\t\t/* Current field is assignment-\n\t\t\t\t\t * suppressed. */\n    int totalSize = 0;\t\t\t/* Number of bytes needed to store\n\t\t\t\t\t * all results combined. */\n    unsigned char *results;\t\t/* Where scanned output goes.  */\n    int numScanned;\t\t\t/* sscanf's result. */\n    register unsigned char *fmt;\n    int i, widthSpecified;\n\n    if (argc < 3) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" string format ?varName varName ...?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n\n    /*\n     * This procedure operates in four stages:\n     * 1. Scan the format string, collecting information about each field.\n     * 2. Allocate an array to hold all of the scanned fields.\n     * 3. Call sscanf to do all the dirty work, and have it store the\n     *    parsed fields in the array.\n     * 4. Pick off the fields from the array and assign them to variables.\n     */\n    arg1Length = (strlen(argv[1]) + 4) & ~03;\n    for (fmt = argv[2]; *fmt != 0; fmt++) {\n\tif (*fmt != '%') {\n\t    continue;\n\t}\n\tfmt++;\n\tif (*fmt == '*') {\n\t    suppress = 1;\n\t    fmt++;\n\t} else {\n\t    suppress = 0;\n\t}\n\twidthSpecified = 0;\n\twhile (isdigit(*fmt)) {\n\t    widthSpecified = 1;\n\t    fmt++;\n\t}\n\tif (suppress) {\n\t    continue;\n\t}\n\tif (numFields == MAX_FIELDS) {\n\t    interp->result = (unsigned char*) \"too many fields to scan\";\n\t    return TCL_ERROR;\n\t}\n\tcurField = &fields[numFields];\n\tnumFields++;\n\tswitch (*fmt) {\n\t    case 'D':\n\t    case 'O':\n\t    case 'X':\n\t    case 'd':\n\t    case 'o':\n\t    case 'x':\n\t\tcurField->fmt = 'd';\n\t\tcurField->size = sizeof(int);\n\t\tbreak;\n\n\t    case 's':\n\t\tcurField->fmt = 's';\n\t\tcurField->size = arg1Length;\n\t\tbreak;\n\n\t    case 'c':\n                if (widthSpecified) {\n                    interp->result = (unsigned char*)\n                         \"field width may not be specified in %c conversion\";\n                    return TCL_ERROR;\n                }\n\t\tcurField->fmt = 'c';\n\t\tcurField->size = sizeof(int);\n\t\tbreak;\n\t    case '[':\n\t\tcurField->fmt = 's';\n\t\tcurField->size = arg1Length;\n\t\tdo {\n\t\t    fmt++;\n\t\t} while (*fmt != ']');\n\t\tbreak;\n\n\t    default:\n\t\tsprintf(interp->result,\n\t\t\t\"bad scan conversion character \\\"%c\\\"\", *fmt);\n\t\treturn TCL_ERROR;\n\t}\n\ttotalSize += curField->size;\n    }\n\n    if (numFields != (argc-3)) {\n\tinterp->result = (unsigned char*)\n\t\t\"different numbers of variable names and field specifiers\";\n\treturn TCL_ERROR;\n    }\n\n    /*\n     * Step 2:\n     */\n    results = malloc (totalSize);\n    for (i = 0, totalSize = 0, curField = fields;\n\t    i < numFields; i++, curField++) {\n\tcurField->location = results + totalSize;\n\ttotalSize += curField->size;\n    }\n\n    /*\n     * Fill in the remaining fields with NULL;  the only purpose of\n     * this is to keep some memory analyzers, like Purify, from\n     * complaining.\n     */\n    for ( ; i < MAX_FIELDS; i++, curField++) {\n\tcurField->location = 0;\n    }\n\n    /*\n     * Step 3:\n     */\n    numScanned = sscanf(argv[1], (char*) argv[2],\n\t    fields[0].location, fields[1].location, fields[2].location,\n\t    fields[3].location, fields[4].location, fields[5].location,\n\t    fields[6].location, fields[7].location, fields[8].location,\n\t    fields[9].location, fields[10].location, fields[11].location,\n\t    fields[12].location, fields[13].location, fields[14].location,\n\t    fields[15].location, fields[16].location, fields[17].location,\n\t    fields[18].location, fields[19].location);\n\n    /*\n     * Step 4:\n     */\n    if (numScanned < numFields) {\n\tnumFields = numScanned;\n    }\n    for (i = 0, curField = fields; i < numFields; i++, curField++) {\n\tswitch (curField->fmt) {\n\t    unsigned char string[120];\n\n\t    case 'd':\n\t\tsprintf(string, \"%d\", *((int *) curField->location));\n\t\tif (Tcl_SetVar(interp, argv[i+3], string, 0) == 0) {\n\t\t    storeError:\n\t\t    Tcl_AppendResult(interp,\n\t\t\t    \"couldn't set variable \\\"\", argv[i+3], \"\\\"\", 0);\n\t\t    free (results);\n\t\t    return TCL_ERROR;\n\t\t}\n\t\tbreak;\n\n\t    case 'c':\n\t\tsprintf(string, \"%d\", *curField->location & 0xff);\n\t\tif (Tcl_SetVar(interp, argv[i+3], string, 0) == 0) {\n\t\t    goto storeError;\n\t\t}\n\t\tbreak;\n\n\t    case 's':\n\t\tif (Tcl_SetVar(interp, argv[i+3], curField->location, 0)\n\t\t\t== 0) {\n\t\t    goto storeError;\n\t\t}\n\t\tbreak;\n\t}\n    }\n    free(results);\n    sprintf(interp->result, \"%d\", numScanned);\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_SplitCmd --\n *\n *\tThis procedure is invoked to process the \"split\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_SplitCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    unsigned char *splitChars;\n    register unsigned char *p, *p2;\n    unsigned char *elementStart;\n\n    if (argc == 2) {\n\tsplitChars = (unsigned char*) \" \\n\\t\\r\";\n    } else if (argc == 3) {\n\tsplitChars = argv[2];\n    } else {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" string ?splitChars?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n\n    /*\n     * Handle the special case of splitting on every character.\n     */\n\n    if (*splitChars == 0) {\n\tunsigned char string[2];\n\tstring[1] = 0;\n\tfor (p = argv[1]; *p != 0; p++) {\n\t    string[0] = *p;\n\t    Tcl_AppendElement(interp, string, 0);\n\t}\n\treturn TCL_OK;\n    }\n\n    /*\n     * Normal case: split on any of a given set of characters.\n     * Discard instances of the split characters.\n     */\n\n    for (p = elementStart = argv[1]; *p != 0; p++) {\n\tunsigned char c = *p;\n\tfor (p2 = splitChars; *p2 != 0; p2++) {\n\t    if (*p2 == c) {\n\t\t*p = 0;\n\t\tTcl_AppendElement(interp, elementStart, 0);\n\t\t*p = c;\n\t\telementStart = p+1;\n\t\tbreak;\n\t    }\n\t}\n    }\n    if (p != argv[1]) {\n\tTcl_AppendElement(interp, elementStart, 0);\n    }\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_StringCmd --\n *\n *\tThis procedure is invoked to process the \"string\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_StringCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int length;\n    register unsigned char *p, c;\n    int match;\n    int first;\n    int left = 0, right = 0;\n\n    if (argc < 2) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" option arg ?arg ...?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    c = argv[1][0];\n    length = strlen(argv[1]);\n    if ((c == 'c') && (strncmp(argv[1], (unsigned char*) \"compare\", length) == 0)) {\n\tif (argc != 4) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" compare string1 string2\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tmatch = strcmp(argv[2], argv[3]);\n\tif (match > 0) {\n\t    interp->result = (unsigned char*) \"1\";\n\t} else if (match < 0) {\n\t    interp->result = (unsigned char*) \"-1\";\n\t} else {\n\t    interp->result = (unsigned char*) \"0\";\n\t}\n\treturn TCL_OK;\n    } else if ((c == 'f') && (strncmp(argv[1], (unsigned char*) \"first\", length) == 0)) {\n\tif (argc != 4) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" first string1 string2\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tfirst = 1;\n\n\tfirstLast:\n\tmatch = -1;\n\tc = *argv[2];\n\tlength = strlen(argv[2]);\n\tfor (p = argv[3]; *p != 0; p++) {\n\t    if (*p != c) {\n\t\tcontinue;\n\t    }\n\t    if (strncmp(argv[2], p, length) == 0) {\n\t\tmatch = p-argv[3];\n\t\tif (first) {\n\t\t    break;\n\t\t}\n\t    }\n\t}\n\tsprintf(interp->result, \"%d\", match);\n\treturn TCL_OK;\n    } else if ((c == 'i') && (strncmp(argv[1], (unsigned char*) \"index\", length) == 0)) {\n\tint index;\n\n\tif (argc != 4) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" index string charIndex\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tif (Tcl_GetInt(interp, argv[3], &index) != TCL_OK) {\n\t    return TCL_ERROR;\n\t}\n\tif ((index >= 0) && (index < strlen(argv[2]))) {\n\t    interp->result[0] = argv[2][index];\n\t    interp->result[1] = 0;\n\t}\n\treturn TCL_OK;\n    } else if ((c == 'l') && (strncmp(argv[1], (unsigned char*) \"last\", length) == 0)\n\t    && (length >= 2)) {\n\tif (argc != 4) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" last string1 string2\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tfirst = 0;\n\tgoto firstLast;\n    } else if ((c == 'l') && (strncmp(argv[1], (unsigned char*) \"length\", length) == 0)\n\t    && (length >= 2)) {\n\tif (argc != 3) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" length string\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tsprintf(interp->result, \"%u\", (unsigned int) strlen(argv[2]));\n\treturn TCL_OK;\n    } else if ((c == 'm') && (strncmp(argv[1], (unsigned char*) \"match\", length) == 0)) {\n\tif (argc != 4) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" match pattern string\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tif (Tcl_StringMatch(argv[3], argv[2]) != 0) {\n\t    interp->result = (unsigned char*) \"1\";\n\t} else {\n\t    interp->result = (unsigned char*) \"0\";\n\t}\n\treturn TCL_OK;\n    } else if ((c == 'r') && (strncmp(argv[1], (unsigned char*) \"range\", length) == 0)) {\n\tint first, last, stringLength;\n\n\tif (argc != 5) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" range string first last\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tstringLength = strlen(argv[2]);\n\tif (Tcl_GetInt(interp, argv[3], &first) != TCL_OK) {\n\t    return TCL_ERROR;\n\t}\n\tif ((*argv[4] == 'e')\n\t\t&& (strncmp(argv[4], (unsigned char*) \"end\", strlen(argv[4])) == 0)) {\n\t    last = stringLength-1;\n\t} else {\n\t    if (Tcl_GetInt(interp, argv[4], &last) != TCL_OK) {\n\t\tTcl_ResetResult(interp);\n\t\tTcl_AppendResult(interp,\n\t\t\t\"expected integer or \\\"end\\\" but got \\\"\",\n\t\t\targv[4], \"\\\"\", 0);\n\t\treturn TCL_ERROR;\n\t    }\n\t}\n\tif (first < 0) {\n\t    first = 0;\n\t}\n\tif (last >= stringLength) {\n\t    last = stringLength-1;\n\t}\n\tif (last >= first) {\n\t    unsigned char saved, *p;\n\n\t    p = argv[2] + last + 1;\n\t    saved = *p;\n\t    *p = 0;\n\t    Tcl_SetResult(interp, argv[2] + first, TCL_VOLATILE);\n\t    *p = saved;\n\t}\n\treturn TCL_OK;\n    } else if ((c == 't') && (strncmp(argv[1], (unsigned char*) \"tolower\", length) == 0)\n\t    && (length >= 3)) {\n\tregister unsigned char *p;\n\n\tif (argc != 3) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" tolower string\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tTcl_SetResult(interp, argv[2], TCL_VOLATILE);\n\tfor (p = interp->result; *p != 0; p++) {\n\t    if (isupper(*p)) {\n\t\t*p = tolower(*p);\n\t    }\n\t}\n\treturn TCL_OK;\n    } else if ((c == 't') && (strncmp(argv[1], (unsigned char*) \"toupper\", length) == 0)\n\t    && (length >= 3)) {\n\tregister unsigned char *p;\n\n\tif (argc != 3) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" toupper string\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tTcl_SetResult(interp, argv[2], TCL_VOLATILE);\n\tfor (p = interp->result; *p != 0; p++) {\n\t    if (islower(*p)) {\n\t\t*p = toupper(*p);\n\t    }\n\t}\n\treturn TCL_OK;\n    } else if ((c == 't') && (strncmp(argv[1], (unsigned char*) \"trim\", length) == 0)\n\t    && (length == 4)) {\n\tunsigned char *trimChars;\n\tregister unsigned char *p, *checkPtr;\n\n\tleft = right = 1;\n\n\ttrim:\n\tif (argc == 4) {\n\t    trimChars = argv[3];\n\t} else if (argc == 3) {\n\t    trimChars = (unsigned char*) \" \\t\\n\\r\";\n\t} else {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" \", argv[1], \" string ?chars?\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tp = argv[2];\n\tif (left) {\n\t    for (c = *p; c != 0; p++, c = *p) {\n\t\tfor (checkPtr = trimChars; *checkPtr != c; checkPtr++) {\n\t\t    if (*checkPtr == 0) {\n\t\t\tgoto doneLeft;\n\t\t    }\n\t\t}\n\t    }\n\t}\n\tdoneLeft:\n\tTcl_SetResult(interp, p, TCL_VOLATILE);\n\tif (right) {\n\t    unsigned char *donePtr;\n\n\t    p = interp->result + strlen(interp->result) - 1;\n\t    donePtr = &interp->result[-1];\n\t    for (c = *p; p != donePtr; p--, c = *p) {\n\t\tfor (checkPtr = trimChars; *checkPtr != c; checkPtr++) {\n\t\t    if (*checkPtr == 0) {\n\t\t\tgoto doneRight;\n\t\t    }\n\t\t}\n\t    }\n\t    doneRight:\n\t    p[1] = 0;\n\t}\n\treturn TCL_OK;\n    } else if ((c == 't') && (strncmp(argv[1], (unsigned char*) \"trimleft\", length) == 0)\n\t    && (length > 4)) {\n\tleft = 1;\n\targv[1] = (unsigned char*) \"trimleft\";\n\tgoto trim;\n    } else if ((c == 't') && (strncmp(argv[1], (unsigned char*) \"trimright\", length) == 0)\n\t    && (length > 4)) {\n\tright = 1;\n\targv[1] = (unsigned char*) \"trimright\";\n\tgoto trim;\n    } else {\n\tTcl_AppendResult(interp, \"bad option \\\"\", argv[1],\n\t\t\"\\\": should be compare, first, index, last, length, match, \",\n\t\t\"range, tolower, toupper, trim, trimleft, or trimright\", 0);\n\treturn TCL_ERROR;\n    }\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_TraceCmd --\n *\n *\tThis procedure is invoked to process the \"trace\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_TraceCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    char c;\n    int length;\n\n    if (argc < 2) {\n\tTcl_AppendResult(interp, \"too few args: should be \\\"\",\n\t\targv[0], \" option [arg arg ...]\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    c = argv[1][1];\n    length = strlen(argv[1]);\n    if ((c == 'a') && (strncmp(argv[1], (unsigned char*) \"variable\", length) == 0)\n\t    && (length >= 2)) {\n\tunsigned char *p;\n\tint flags, length;\n\tTraceVarInfo *tvarPtr;\n\n\tif (argc != 5) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\t    argv[0], \" variable name ops command\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\n\tflags = 0;\n\tfor (p = argv[3] ; *p != 0; p++) {\n\t    if (*p == 'r') {\n\t\tflags |= TCL_TRACE_READS;\n\t    } else if (*p == 'w') {\n\t\tflags |= TCL_TRACE_WRITES;\n\t    } else if (*p == 'u') {\n\t\tflags |= TCL_TRACE_UNSETS;\n\t    } else {\n\t\tgoto badOps;\n\t    }\n\t}\n\tif (flags == 0) {\n\t    goto badOps;\n\t}\n\n\tlength = strlen(argv[4]);\n\ttvarPtr = (TraceVarInfo*) malloc ((unsigned)\n\t\t(sizeof(TraceVarInfo) - sizeof(tvarPtr->command) + length + 1));\n\ttvarPtr->flags = flags;\n\ttvarPtr->length = length;\n\tflags |= TCL_TRACE_UNSETS;\n\tstrcpy(tvarPtr->command, argv[4]);\n\tif (Tcl_TraceVar(interp, argv[2], flags, TraceVarProc,\n\t\t(void*) tvarPtr) != TCL_OK) {\n\t    free (tvarPtr);\n\t    return TCL_ERROR;\n\t}\n    } else if ((c == 'd') && (strncmp(argv[1], (unsigned char*) \"vdelete\", length)\n\t    && (length >= 2)) == 0) {\n\tunsigned char *p;\n\tint flags, length;\n\tTraceVarInfo *tvarPtr;\n\tvoid *clientData;\n\n\tif (argc != 5) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\t    argv[0], \" vdelete name ops command\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\n\tflags = 0;\n\tfor (p = argv[3] ; *p != 0; p++) {\n\t    if (*p == 'r') {\n\t\tflags |= TCL_TRACE_READS;\n\t    } else if (*p == 'w') {\n\t\tflags |= TCL_TRACE_WRITES;\n\t    } else if (*p == 'u') {\n\t\tflags |= TCL_TRACE_UNSETS;\n\t    } else {\n\t\tgoto badOps;\n\t    }\n\t}\n\tif (flags == 0) {\n\t    goto badOps;\n\t}\n\n\t/*\n\t * Search through all of our traces on this variable to\n\t * see if there's one with the given command.  If so, then\n\t * delete the first one that matches.\n\t */\n\n\tlength = strlen(argv[4]);\n\tclientData = 0;\n\twhile ((clientData = Tcl_VarTraceInfo(interp, argv[2], 0,\n\t\tTraceVarProc, clientData)) != 0) {\n\t    tvarPtr = (TraceVarInfo *) clientData;\n\t    if ((tvarPtr->length == length) && (tvarPtr->flags == flags)\n\t\t    && (strncmp(argv[4], tvarPtr->command, length) == 0)) {\n\t\tTcl_UntraceVar(interp, argv[2], flags | TCL_TRACE_UNSETS,\n\t\t\tTraceVarProc, clientData);\n\t\tfree (tvarPtr);\n\t\tbreak;\n\t    }\n\t}\n    } else if ((c == 'i') && (strncmp(argv[1], (unsigned char*) \"vinfo\", length) == 0)\n\t    && (length >= 2)) {\n\tvoid *clientData;\n\tunsigned char ops[4], *p;\n\tunsigned char *prefix = (unsigned char*) \"{\";\n\n\tif (argc != 3) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\t    argv[0], \" vinfo name\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tclientData = 0;\n\twhile ((clientData = Tcl_VarTraceInfo(interp, argv[2], 0,\n\t\tTraceVarProc, clientData)) != 0) {\n\t    TraceVarInfo *tvarPtr = (TraceVarInfo *) clientData;\n\t    p = ops;\n\t    if (tvarPtr->flags & TCL_TRACE_READS) {\n\t\t*p = 'r';\n\t\tp++;\n\t    }\n\t    if (tvarPtr->flags & TCL_TRACE_WRITES) {\n\t\t*p = 'w';\n\t\tp++;\n\t    }\n\t    if (tvarPtr->flags & TCL_TRACE_UNSETS) {\n\t\t*p = 'u';\n\t\tp++;\n\t    }\n\t    *p = '\\0';\n\t    Tcl_AppendResult(interp, prefix, 0);\n\t    Tcl_AppendElement(interp, ops, 1);\n\t    Tcl_AppendElement(interp, tvarPtr->command, 0);\n\t    Tcl_AppendResult(interp, \"}\", 0);\n\t    prefix = (unsigned char*) \" {\";\n\t}\n    } else {\n\tTcl_AppendResult(interp, \"bad option \\\"\", argv[1],\n\t\t\"\\\": should be variable, vdelete, or vinfo\", 0);\n\treturn TCL_ERROR;\n    }\n    return TCL_OK;\n\n    badOps:\n    Tcl_AppendResult(interp, \"bad operations \\\"\", argv[3],\n\t    \"\\\": should be one or more of rwu\", 0);\n    return TCL_ERROR;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * TraceVarProc --\n *\n *\tThis procedure is called to handle variable accesses that have\n *\tbeen traced using the \"trace\" command.\n *\n * Results:\n *\tNormally returns NULL.  If the trace command returns an error,\n *\tthen this procedure returns an error string.\n *\n * Side effects:\n *\tDepends on the command associated with the trace.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nstatic unsigned char *\nTraceVarProc(clientData, interp, name1, name2, flags)\n    void *clientData;\t\t/* Information about the variable trace. */\n    Tcl_Interp *interp;\t\t/* Interpreter containing variable. */\n    unsigned char *name1;\t/* Name of variable or array. */\n    unsigned char *name2;\t/* Name of element within array;  NULL means\n\t\t\t\t * scalar variable is being referenced. */\n    int flags;\t\t\t/* OR-ed bits giving operation and other\n\t\t\t\t * information. */\n{\n    TraceVarInfo *tvarPtr = (TraceVarInfo *) clientData;\n    unsigned char *result;\n    int code, cmdLength, flags1, flags2;\n    Interp dummy;\n#define STATIC_SIZE 199\n    unsigned char staticSpace[STATIC_SIZE+1];\n    unsigned char *cmdPtr, *p;\n\n    result = 0;\n    if ((tvarPtr->flags & flags) && !(flags & TCL_INTERP_DESTROYED)) {\n\n\t/*\n\t * Generate a command to execute by appending list elements\n\t * for the two variable names and the operation.  The five\n\t * extra characters are for three space, the opcode character,\n\t * and the terminating null.\n\t */\n\n\tif (name2 == 0) {\n\t    name2 = (unsigned char*) \"\";\n\t}\n\tcmdLength = tvarPtr->length + Tcl_ScanElement(name1, &flags1) +\n\t\tTcl_ScanElement(name2, &flags2) + 5;\n\tif (cmdLength < STATIC_SIZE) {\n\t    cmdPtr = staticSpace;\n\t} else {\n\t    cmdPtr = malloc (cmdLength);\n\t}\n\tp = cmdPtr;\n\tstrcpy(p, tvarPtr->command);\n\tp += tvarPtr->length;\n\t*p = ' ';\n\tp++;\n\tp += Tcl_ConvertElement(name1, p, flags1);\n\t*p = ' ';\n\tp++;\n\tp += Tcl_ConvertElement(name2, p, flags2);\n\t*p = ' ';\n\tif (flags & TCL_TRACE_READS) {\n\t    p[1] = 'r';\n\t} else if (flags & TCL_TRACE_WRITES) {\n\t    p[1] = 'w';\n\t} else if (flags & TCL_TRACE_UNSETS) {\n\t    p[1] = 'u';\n\t}\n\tp[2] = '\\0';\n\n\t/*\n\t * Execute the command.  Be careful to save and restore the\n\t * result from the interpreter used for the command.\n\t */\n\n\tif (interp->freeProc == 0) {\n\t    dummy.freeProc = (Tcl_FreeProc *) 0;\n\t    dummy.result = (unsigned char*) \"\";\n\t    Tcl_SetResult((Tcl_Interp *) &dummy, interp->result, TCL_VOLATILE);\n\t} else {\n\t    dummy.freeProc = interp->freeProc;\n\t    dummy.result = interp->result;\n\t}\n\tcode = Tcl_Eval(interp, cmdPtr, 0, 0);\n\tif (cmdPtr != staticSpace) {\n\t    free(cmdPtr);\n\t}\n\tif (code != TCL_OK) {\n\t    result = (unsigned char*) \"access disallowed by trace command\";\n\t    Tcl_ResetResult(interp);\t\t/* Must clear error state. */\n\t}\n\tTcl_FreeResult(interp);\n\tinterp->result = dummy.result;\n\tinterp->freeProc = dummy.freeProc;\n    }\n    if (flags & TCL_TRACE_DESTROYED) {\n\tfree (tvarPtr);\n    }\n    return result;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_WhileCmd --\n *\n *\tThis procedure is invoked to process the \"while\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_WhileCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int result, value;\n\n    if (argc != 3) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\targv[0], \" test command\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n\n    while (1) {\n\tresult = Tcl_ExprBoolean(interp, argv[1], &value);\n\tif (result != TCL_OK) {\n\t    return result;\n\t}\n\tif (!value) {\n\t    break;\n\t}\n\tresult = Tcl_Eval(interp, argv[2], 0, 0);\n\tif (result == TCL_CONTINUE) {\n\t    result = TCL_OK;\n\t} else if (result != TCL_OK) {\n\t    if (result == TCL_ERROR) {\n\t\tunsigned char msg[60];\n\t\tsprintf(msg, \"\\n    (\\\"while\\\" body line %d)\",\n\t\t\tinterp->errorLine);\n\t\tTcl_AddErrorInfo(interp, msg);\n\t    }\n\t    break;\n\t}\n    }\n    if (result == TCL_BREAK) {\n\tresult = TCL_OK;\n    }\n    if (result == TCL_OK) {\n\tTcl_ResetResult(interp);\n    }\n    return result;\n}\n"
  },
  {
    "path": "lib/libtcl/tclenv.c",
    "content": "/*\n * tclEnv.c --\n *\n *\tTcl support for environment variables, including a setenv\n *\tprocedure.\n *\n * Copyright 1991 Regents of the University of California\n * Permission to use, copy, modify, and distribute this\n * software and its documentation for any purpose and without\n * fee is hereby granted, provided that this copyright\n * notice appears in all copies.  The University of California\n * makes no representations about the suitability of this\n * software for any purpose.  It is provided \"as is\" without\n * express or implied warranty.\n */\n#include \"internal.h\"\n\nextern char **environ;\n\n/*\n * The structure below is used to keep track of all of the interpereters\n * for which we're managing the \"env\" array.  It's needed so that they\n * can all be updated whenever an environment variable is changed\n * anywhere.\n */\n\ntypedef struct EnvInterp {\n    Tcl_Interp *interp;\t\t/* Interpreter for which we're managing\n\t\t\t\t * the env array. */\n    struct EnvInterp *nextPtr;\t/* Next in list of all such interpreters,\n\t\t\t\t * or zero. */\n} EnvInterp;\n\nstatic EnvInterp *firstInterpPtr;\n\t\t\t\t/* First in list of all managed interpreters,\n\t\t\t\t * or NULL if none. */\n\nstatic int environSize = 0;\t/* Non-zero means that the all of the\n\t\t\t\t * environ-related information is malloc-ed\n\t\t\t\t * and the environ array itself has this\n\t\t\t\t * many total entries allocated to it (not\n\t\t\t\t * all may be in use at once).  Zero means\n\t\t\t\t * that the environment array is in its\n\t\t\t\t * original static state. */\n\n/*\n * Declarations for local procedures defined in this file:\n */\n\nstatic void\t\tEnvInit (void);\nstatic unsigned char *\tEnvTraceProc (void *clientData,\n\t\t\t    Tcl_Interp *interp, unsigned char *name1,\n                            unsigned char *name2, int flags);\nstatic int\t\tFindVariable (const char *name,\n\t\t\t    int *lengthPtr);\nint\t\t\tunsetenv (const char *name);\n\f\n/*\n *----------------------------------------------------------------------\n *\n * TclSetupEnv --\n *\n *\tThis procedure is invoked for an interpreter to make environment\n *\tvariables accessible from that interpreter via the \"env\"\n *\tassociative array.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tThe interpreter is added to a list of interpreters managed\n *\tby us, so that its view of envariables can be kept consistent\n *\twith the view in other interpreters.  If this is the first\n *\tcall to Tcl_SetupEnv, then additional initialization happens,\n *\tsuch as copying the environment to dynamically-allocated space\n *\tfor ease of management.\n *\n *----------------------------------------------------------------------\n */\n\nvoid\nTclSetupEnv(interp)\n    Tcl_Interp *interp;\t\t/* Interpreter whose \"env\" array is to be\n\t\t\t\t * managed. */\n{\n    EnvInterp *eiPtr;\n    int i;\n\n    /*\n     * First, initialize our environment-related information, if\n     * necessary.\n     */\n\n    if (environSize == 0) {\n\tEnvInit();\n    }\n\n    /*\n     * Next, add the interpreter to the list of those that we manage.\n     */\n\n    eiPtr = (EnvInterp *) malloc(sizeof(EnvInterp));\n    eiPtr->interp = interp;\n    eiPtr->nextPtr = firstInterpPtr;\n    firstInterpPtr = eiPtr;\n\n    /*\n     * Store the environment variable values into the interpreter's\n     * \"env\" array, and arrange for us to be notified on future\n     * writes and unsets to that array.\n     */\n\n    (void) Tcl_UnsetVar2(interp, \"env\", (char *) NULL, TCL_GLOBAL_ONLY);\n    for (i = 0; ; i++) {\n\tchar *p, *p2;\n\n\tp = environ[i];\n\tif (p == NULL) {\n\t    break;\n\t}\n\tfor (p2 = p; *p2 != '='; p2++) {\n\t    /* Empty loop body. */\n\t}\n\t*p2 = 0;\n\t(void) Tcl_SetVar2(interp, \"env\", p, p2+1, TCL_GLOBAL_ONLY);\n\t*p2 = '=';\n    }\n    Tcl_TraceVar2(interp, \"env\", (char *) NULL,\n\t    TCL_GLOBAL_ONLY | TCL_TRACE_WRITES | TCL_TRACE_UNSETS,\n\t    EnvTraceProc, (void*) NULL);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * FindVariable --\n *\n *\tLocate the entry in environ for a given name.\n *\n * Results:\n *\tThe return value is the index in environ of an entry with the\n *\tname \"name\", or -1 if there is no such entry.   The integer at\n *\t*lengthPtr is filled in with the length of name (if a matching\n *\tentry is found) or the length of the environ array (if no matching\n *\tentry is found).\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nstatic int\nFindVariable(name, lengthPtr)\n    const char *name;\t\t/* Name of desired environment variable. */\n    int *lengthPtr;\t\t/* Used to return length of name (for\n\t\t\t\t * successful searches) or number of non-NULL\n\t\t\t\t * entries in environ (for unsuccessful\n\t\t\t\t * searches). */\n{\n    int i;\n    const register char *p1, *p2;\n\n    for (i = 0, p1 = environ[i]; p1 != NULL; i++, p1 = environ[i]) {\n\tfor (p2 = name; *p2 == *p1; p1++, p2++) {\n\t    /* NULL loop body. */\n\t}\n\tif ((*p1 == '=') && (*p2 == '\\0')) {\n\t    *lengthPtr = p2-name;\n\t    return i;\n\t}\n    }\n    *lengthPtr = i;\n    return -1;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * setenv --\n *\n *\tSet an environment variable, replacing an existing value\n *\tor creating a new variable if there doesn't exist a variable\n *\tby the given name.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tThe environ array gets updated, as do all of the interpreters\n *\tthat we manage.\n *\n *----------------------------------------------------------------------\n */\n\nint\nsetenv(name, value, overwrite)\n    const char *name;\t\t/* Name of variable whose value is to be\n\t\t\t\t * set. */\n    const char *value;\t\t/* New value for variable. */\n    int overwrite;\n{\n    int index, length, nameLength;\n    char *p;\n    EnvInterp *eiPtr;\n\n    if (environSize == 0) {\n\tEnvInit();\n    }\n\n    /*\n     * Figure out where the entry is going to go.  If the name doesn't\n     * already exist, enlarge the array if necessary to make room.  If\n     * the name exists, free its old entry.\n     */\n\n    index = FindVariable(name, &length);\n    if (index == -1) {\n\tif ((length+2) > environSize) {\n\t    char **newEnviron;\n\n\t    newEnviron = (char **) malloc((unsigned)\n\t\t    ((length+5) * sizeof(char *)));\n\t    memcpy((void *) newEnviron, (void *) environ,\n\t\t    length*sizeof(char *));\n\t    free((char *) environ);\n\t    environ = newEnviron;\n\t    environSize = length+5;\n\t}\n\tindex = length;\n\tenviron[index+1] = NULL;\n\tnameLength = strlen(name);\n    } else {\n\t/*\n\t * Compare the new value to the existing value.  If they're\n\t * the same then quit immediately (e.g. don't rewrite the\n\t * value or propagate it to other interpeters).  Otherwise,\n\t * when there are N interpreters there will be N! propagations\n\t * of the same value among the interpreters.\n\t */\n\n\tif (strcmp(value, environ[index]+length+1) == 0) {\n\t    return 0;\n\t}\n\tfree(environ[index]);\n\tnameLength = length;\n    }\n\n    /*\n     * Create a new entry and enter it into the table.\n     */\n\n    p = (char *) malloc((unsigned) (nameLength + strlen(value) + 2));\n    environ[index] = p;\n    strcpy(p, name);\n    p += nameLength;\n    *p = '=';\n    strcpy(p+1, value);\n\n    /*\n     * Update all of the interpreters.\n     */\n\n    for (eiPtr= firstInterpPtr; eiPtr != NULL; eiPtr = eiPtr->nextPtr) {\n\t(void) Tcl_SetVar2(eiPtr->interp, \"env\", (char *) name,\n\t\tp+1, TCL_GLOBAL_ONLY);\n    }\n    return 0;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * putenv --\n *\n *\tSet an environment variable.  Similar to setenv except that\n *\tthe information is passed in a single string of the form\n *\tNAME=value, rather than as separate name strings.  This procedure\n *\tis a stand-in for the standard UNIX procedure by the same name,\n *\tso that applications using that procedure will interface\n *\tproperly to Tcl.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tThe environ array gets updated, as do all of the interpreters\n *\tthat we manage.\n *\n *----------------------------------------------------------------------\n */\n\nint\nputenv(string)\n    char *string;\t\t/* Info about environment variable in the\n\t\t\t\t * form NAME=value. */\n{\n    int nameLength;\n    char *name, *value;\n\n    if (string == NULL) {\n\treturn 0;\n    }\n\n    /*\n     * Separate the string into name and value parts, then call\n     * setenv to do all of the real work.\n     */\n\n    value = strchr(string, '=');\n    if (value == NULL) {\n\treturn 0;\n    }\n    nameLength = value - string;\n    if (nameLength == 0) {\n\treturn 0;\n    }\n    name = malloc(nameLength+1);\n    memcpy(name, string, nameLength);\n    name[nameLength] = 0;\n    setenv(name, value+1, 1);\n    free(name);\n    return 0;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * unsetenv --\n *\n *\tRemove an environment variable, updating the \"env\" arrays\n *\tin all interpreters managed by us.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tInterpreters are updated, as is environ.\n *\n *----------------------------------------------------------------------\n */\n\nint\nunsetenv(name)\n    const char *name;\t\t\t/* Name of variable to remove. */\n{\n    int index, dummy;\n    char **envPtr;\n    EnvInterp *eiPtr;\n\n    if (environSize == 0) {\n\tEnvInit();\n    }\n\n    /*\n     * Update the environ array.\n     */\n\n    index = FindVariable(name, &dummy);\n    if (index == -1) {\n\treturn 0;\n    }\n    free(environ[index]);\n    for (envPtr = environ+index+1; ; envPtr++) {\n\tenvPtr[-1] = *envPtr;\n\tif (*envPtr == NULL) {\n\t    break;\n       }\n    }\n\n    /*\n     * Update all of the interpreters.\n     */\n\n    for (eiPtr = firstInterpPtr; eiPtr != NULL; eiPtr = eiPtr->nextPtr) {\n\t(void) Tcl_UnsetVar2(eiPtr->interp, \"env\", (char *) name,\n\t\tTCL_GLOBAL_ONLY);\n    }\n    return 0;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * EnvTraceProc --\n *\n *\tThis procedure is invoked whenever an environment variable\n *\tis modified or deleted.  It propagates the change to the\n *\t\"environ\" array and to any other interpreters for whom\n *\twe're managing an \"env\" array.\n *\n * Results:\n *\tAlways returns NULL to indicate success.\n *\n * Side effects:\n *\tEnvironment variable changes get propagated.  If the whole\n *\t\"env\" array is deleted, then we stop managing things for\n *\tthis interpreter (usually this happens because the whole\n *\tinterpreter is being deleted).\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nstatic unsigned char *\nEnvTraceProc(clientData, interp, name1, name2, flags)\n    void *clientData;           /* Not used. */\n    Tcl_Interp *interp;\t\t/* Interpreter whose \"env\" variable is\n\t\t\t\t * being modified. */\n    unsigned char *name1;\t/* Better be \"env\". */\n    unsigned char *name2;\t/* Name of variable being modified, or\n\t\t\t\t * NULL if whole array is being deleted. */\n    int flags;\t\t\t/* Indicates what's happening. */\n{\n    /*\n     * First see if the whole \"env\" variable is being deleted.  If\n     * so, just forget about this interpreter.\n     */\n\n    if (name2 == NULL) {\n\tregister EnvInterp *eiPtr, *prevPtr;\n\n\tif ((flags & (TCL_TRACE_UNSETS|TCL_TRACE_DESTROYED))\n\t\t!= (TCL_TRACE_UNSETS|TCL_TRACE_DESTROYED)) {\n\t    fprintf(stderr, \"EnvTraceProc called with confusing arguments\\n\");\n            abort();\n\t}\n\teiPtr = firstInterpPtr;\n\tif (eiPtr->interp == interp) {\n\t    firstInterpPtr = eiPtr->nextPtr;\n\t} else {\n\t    for (prevPtr = eiPtr, eiPtr = eiPtr->nextPtr; ;\n\t\t    prevPtr = eiPtr, eiPtr = eiPtr->nextPtr) {\n\t\tif (eiPtr == NULL) {\n\t\t    fprintf(stderr, \"EnvTraceProc couldn't find interpreter\\n\");\n                    abort();\n\t\t}\n\t\tif (eiPtr->interp == interp) {\n\t\t    prevPtr->nextPtr = eiPtr->nextPtr;\n\t\t    break;\n\t\t}\n\t    }\n\t}\n\tfree((char *) eiPtr);\n\treturn NULL;\n    }\n\n    /*\n     * If a value is being set, call setenv to do all of the work.\n     */\n\n    if (flags & TCL_TRACE_WRITES) {\n\tsetenv(name2, Tcl_GetVar2(interp, \"env\", name2, TCL_GLOBAL_ONLY), 1);\n    }\n\n    if (flags & TCL_TRACE_UNSETS) {\n\tunsetenv(name2);\n    }\n    return NULL;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * EnvInit --\n *\n *\tThis procedure is called to initialize our management\n *\tof the environ array.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tEnviron gets copied to malloc-ed storage, so that in\n *\tthe future we don't have to worry about which entries\n *\tare malloc-ed and which are static.\n *\n *----------------------------------------------------------------------\n */\n\nstatic void\nEnvInit()\n{\n    char **newEnviron;\n    int i, length;\n\n    if (environSize != 0) {\n\treturn;\n    }\n    for (length = 0; environ[length] != NULL; length++) {\n\t/* Empty loop body. */\n    }\n    environSize = length+5;\n    newEnviron = (char **) malloc((unsigned)\n\t\t(environSize * sizeof(char *)));\n    for (i = 0; i < length; i++) {\n\tnewEnviron[i] = (char *) malloc((unsigned) (strlen(environ[i]) + 1));\n\tstrcpy(newEnviron[i], environ[i]);\n    }\n    newEnviron[length] = NULL;\n    environ = newEnviron;\n}\n"
  },
  {
    "path": "lib/libtcl/tclexpr.c",
    "content": "/*\n * tclExpr.c --\n *\n *\tThis file contains the code to evaluate expressions for\n *\tTcl.\n *\n *\tThis implementation of floating-point support was modelled\n *\tafter an initial implementation by Bill Carpenter.\n *\n * Copyright 1987-1991 Regents of the University of California\n * Permission to use, copy, modify, and distribute this\n * software and its documentation for any purpose and without\n * fee is hereby granted, provided that the above copyright\n * notice appear in all copies.  The University of California\n * makes no representations about the suitability of this\n * software for any purpose.  It is provided \"as is\" without\n * express or implied warranty.\n */\n#include \"internal.h\"\n\n/*\n * The data structure below is used to describe an expression value,\n * which can be either an integer (the usual case), or a string.\n * A given number has only one value at a time.\n */\n#define STATIC_STRING_SPACE\t40\n\ntypedef struct {\n\tunsigned char\ttype;\t\t/* Type: TYPE_INT or TYPE_STRING. */\n\tlong\t\tint_value;\t/* Integer value, if any. */\n\tParseValue\tpv;\t\t/* A string value, if any. */\n\tunsigned char\tstatic_space [STATIC_STRING_SPACE];\n\t\t\t\t\t/* Storage for small strings;\n\t\t\t\t\t * large ones are malloc-ed. */\n} Value_t;\n\n/*\n * Valid values for type:\n */\n#define TYPE_INT\t0\n#define TYPE_STRING\t1\n\n/*\n * The data structure below describes the state of parsing an expression.\n * It's passed among the routines in this module.\n */\ntypedef struct {\n\tunsigned char\t*original_expr;\n\t\t\t\t/* The entire expression, as originally\n\t\t\t\t * passed to Tcl_Expr. */\n\tunsigned char\t*expr;\t/* Position to the next character to be\n\t\t\t\t * scanned from the expression string. */\n\tunsigned char token;\t/* Type of the last token to be parsed from\n\t\t\t\t * expr.  See below for definitions.\n\t\t\t\t * Corresponds to the characters just\n\t\t\t\t * before expr. */\n} Expr_info_t;\n\n/*\n * The token types are defined below.  In addition, there is a table\n * associating a precedence with each operator.  The order of types\n * is important.  Consult the code before changing it.\n */\n#define VALUE\t\t0\n#define OPEN_PAREN\t1\n#define CLOSE_PAREN\t2\n#define END\t\t3\n#define UNKNOWN\t\t4\n\n/*\n * Binary operators:\n */\n#define MULT\t\t8\n#define DIVIDE\t\t9\n#define MOD\t\t10\n#define PLUS\t\t11\n#define MINUS\t\t12\n#define LEFT_SHIFT\t13\n#define RIGHT_SHIFT\t14\n#define LESS\t\t15\n#define GREATER\t\t16\n#define LEQ\t\t17\n#define GEQ\t\t18\n#define EQUAL\t\t19\n#define NEQ\t\t20\n#define BIT_AND\t\t21\n#define BIT_XOR\t\t22\n#define BIT_OR\t\t23\n#define AND\t\t24\n#define OR\t\t25\n#define QUESTY\t\t26\n#define COLON\t\t27\n\n/*\n * Unary operators:\n */\n#define\tUNARY_MINUS\t28\n#define NOT\t\t29\n#define BIT_NOT\t\t30\n\n/*\n * Precedence table.  The values for non-operator token types are ignored.\n */\nstatic unsigned char prec_table [] = {\n\t0, 0, 0, 0, 0, 0, 0, 0,\n\t11, 11, 11,\t\t\t/* MULT, DIVIDE, MOD */\n\t10, 10,\t\t\t\t/* PLUS, MINUS */\n\t9, 9,\t\t\t\t/* LEFT_SHIFT, RIGHT_SHIFT */\n\t8, 8, 8, 8,\t\t\t/* LESS, GREATER, LEQ, GEQ */\n\t7, 7,\t\t\t\t/* EQUAL, NEQ */\n\t6,\t\t\t\t/* BIT_AND */\n\t5,\t\t\t\t/* BIT_XOR */\n\t4,\t\t\t\t/* BIT_OR */\n\t3,\t\t\t\t/* AND */\n\t2,\t\t\t\t/* OR */\n\t1, 1,\t\t\t\t/* QUESTY, COLON */\n\t12, 12, 12\t\t\t/* UNARY_MINUS, NOT, BIT_NOT */\n};\n\n/*\n * Mapping from operator numbers to strings;  used for error messages.\n */\nstatic char *operator_strings[] = {\n\t\"VALUE\", \"(\", \")\", \"END\", \"UNKNOWN\", \"5\", \"6\", \"7\",\n\t\"*\", \"/\", \"%\", \"+\", \"-\", \"<<\", \">>\", \"<\", \">\", \"<=\",\n\t\">=\", \"==\", \"!=\", \"&\", \"^\", \"|\", \"&&\", \"||\", \"?\", \":\",\n\t\"-\", \"!\", \"~\"\n};\n\n/*\n * Declarations for local procedures to this file:\n */\nstatic void make_string (Value_t *valuePtr);\n\f\n/*\n * Given a string (such as one coming from command or variable\n * substitution), make a Value_t based on the string.  The value\n * will be a floating-point or integer, if possible, or else it\n * will just be a copy of the string.\n *\n * Results:\n *\tTCL_OK is returned under normal circumstances, and TCL_ERROR\n *\tis returned if a floating-point overflow or underflow occurred\n *\twhile reading in a number.  The value at *valuePtr is modified\n *\tto hold a number, if possible.\n *\n * Side effects:\n *\tNone.\n */\nstatic unsigned char\nparse_string (Tcl_Interp *interp,\t/* Where to store error message. */\n\tunsigned char *string,\t\t/* String to turn into value. */\n\tValue_t *valuePtr)\t\t/* Where to store value information.\n\t\t\t\t\t * Caller must have initialized pv field. */\n{\n    char c;\n\n    /*\n     * Try to convert the string to a number.\n     */\n    c = *string;\n    if (((c >= '0') && (c <= '9')) || (c == '-')) {\n\tchar *term;\n\n\tvaluePtr->type = TYPE_INT;\n\tvaluePtr->int_value = strtol (string, &term, 0);\n\tc = *term;\n\tif (c == '\\0') {\n\t    return TCL_OK;\n\t}\n    }\n\n    /*\n     * Not a valid number.  Save a string value (but don't do anything\n     * if it's already the value).\n     */\n    valuePtr->type = TYPE_STRING;\n    if (string != valuePtr->pv.buffer) {\n\tunsigned short length, space;\n\n\tlength = strlen (string);\n\tvaluePtr->pv.next = valuePtr->pv.buffer;\n\tspace = valuePtr->pv.end - valuePtr->pv.buffer;\n\tif (length > space) {\n\t    (*valuePtr->pv.expandProc) (&valuePtr->pv, length - space);\n\t}\n\tstrcpy (valuePtr->pv.buffer, string);\n    }\n    return TCL_OK;\n}\n\f\n/*\n * Lexical analyzer for expression parser:  parses a single value,\n * operator, or other syntactic element from an expression string.\n *\n * Results:\n *\tTCL_OK is returned unless an error occurred while doing lexical\n *\tanalysis or executing an embedded command.  In that case a\n *\tstandard Tcl error is returned, using interp->result to hold\n *\tan error message.  In the event of a successful return, the token\n *\tand field in infoPtr is updated to refer to the next symbol in\n *\tthe expression string, and the expr field is advanced past that\n *\ttoken;  if the token is a value, then the value is stored at\n *\tvaluePtr.\n *\n * Side effects:\n *\tNone.\n */\nstatic unsigned char\nget_lex (Tcl_Interp *interp,\t/* Interpreter to use for error reporting. */\n\tExpr_info_t *infoPtr,\t/* Describes the state of the parse. */\n\tValue_t *valuePtr)\t/* Where to store value, if that is\n\t\t\t\t * what's parsed from string.  Caller\n\t\t\t\t * must have initialized pv field correctly. */\n{\n    char *p, c, *var, *term;\n    unsigned char result;\n\n    p = infoPtr->expr;\n    c = *p;\n    while (isspace(c)) {\n\tp++;\n\tc = *p;\n    }\n    infoPtr->expr = p+1;\n    switch (c) {\n\tcase '0':\n\tcase '1':\n\tcase '2':\n\tcase '3':\n\tcase '4':\n\tcase '5':\n\tcase '6':\n\tcase '7':\n\tcase '8':\n\tcase '9':\n\n\t    /*\n\t     * Number.  First read an integer.  Then if it looks like\n\t     * there's a floating-point number (or if it's too big a\n\t     * number to fit in an integer), parse it as a floating-point\n\t     * number.\n\t     */\n\n\t    infoPtr->token = VALUE;\n\t    valuePtr->type = TYPE_INT;\n\t    valuePtr->int_value = strtoul (p, &term, 0);\n\t    c = *term;\n\t    infoPtr->expr = term;\n\t    return TCL_OK;\n\n\tcase '$':\n\n\t    /*\n\t     * Variable.  Fetch its value, then see if it makes sense\n\t     * as an integer or floating-point number.\n\t     */\n\n\t    infoPtr->token = VALUE;\n\t    var = Tcl_ParseVar(interp, p, &infoPtr->expr);\n\t    if (var == 0) {\n\t\treturn TCL_ERROR;\n\t    }\n\t    if (((Interp *) interp)->noEval) {\n\t\tvaluePtr->type = TYPE_INT;\n\t\tvaluePtr->int_value = 0;\n\t\treturn TCL_OK;\n\t    }\n\t    return parse_string(interp, var, valuePtr);\n\n\tcase '[':\n\t    infoPtr->token = VALUE;\n\t    result = Tcl_Eval(interp, p+1, TCL_BRACKET_TERM,\n\t\t    &infoPtr->expr);\n\t    if (result != TCL_OK) {\n\t\treturn result;\n\t    }\n\t    infoPtr->expr++;\n\t    if (((Interp *) interp)->noEval) {\n\t\tvaluePtr->type = TYPE_INT;\n\t\tvaluePtr->int_value = 0;\n\t\tTcl_ResetResult(interp);\n\t\treturn TCL_OK;\n\t    }\n\t    result = parse_string(interp, interp->result, valuePtr);\n\t    if (result != TCL_OK) {\n\t\treturn result;\n\t    }\n\t    Tcl_ResetResult(interp);\n\t    return TCL_OK;\n\n\tcase '\"':\n\t    infoPtr->token = VALUE;\n\t    result = TclParseQuotes(interp, infoPtr->expr, '\"', 0,\n\t\t    &infoPtr->expr, &valuePtr->pv);\n\t    if (result != TCL_OK) {\n\t\treturn result;\n\t    }\n\t    return parse_string(interp, valuePtr->pv.buffer, valuePtr);\n\n\tcase '{':\n\t    infoPtr->token = VALUE;\n\t    result = TclParseBraces(interp, infoPtr->expr, &infoPtr->expr,\n\t\t    &valuePtr->pv);\n\t    if (result != TCL_OK) {\n\t\treturn result;\n\t    }\n\t    return parse_string(interp, valuePtr->pv.buffer, valuePtr);\n\n\tcase '(':\n\t    infoPtr->token = OPEN_PAREN;\n\t    return TCL_OK;\n\n\tcase ')':\n\t    infoPtr->token = CLOSE_PAREN;\n\t    return TCL_OK;\n\n\tcase '*':\n\t    infoPtr->token = MULT;\n\t    return TCL_OK;\n\n\tcase '/':\n\t    infoPtr->token = DIVIDE;\n\t    return TCL_OK;\n\n\tcase '%':\n\t    infoPtr->token = MOD;\n\t    return TCL_OK;\n\n\tcase '+':\n\t    infoPtr->token = PLUS;\n\t    return TCL_OK;\n\n\tcase '-':\n\t    infoPtr->token = MINUS;\n\t    return TCL_OK;\n\n\tcase '?':\n\t    infoPtr->token = QUESTY;\n\t    return TCL_OK;\n\n\tcase ':':\n\t    infoPtr->token = COLON;\n\t    return TCL_OK;\n\n\tcase '<':\n\t    switch (p[1]) {\n\t\tcase '<':\n\t\t    infoPtr->expr = p+2;\n\t\t    infoPtr->token = LEFT_SHIFT;\n\t\t    break;\n\t\tcase '=':\n\t\t    infoPtr->expr = p+2;\n\t\t    infoPtr->token = LEQ;\n\t\t    break;\n\t\tdefault:\n\t\t    infoPtr->token = LESS;\n\t\t    break;\n\t    }\n\t    return TCL_OK;\n\n\tcase '>':\n\t    switch (p[1]) {\n\t\tcase '>':\n\t\t    infoPtr->expr = p+2;\n\t\t    infoPtr->token = RIGHT_SHIFT;\n\t\t    break;\n\t\tcase '=':\n\t\t    infoPtr->expr = p+2;\n\t\t    infoPtr->token = GEQ;\n\t\t    break;\n\t\tdefault:\n\t\t    infoPtr->token = GREATER;\n\t\t    break;\n\t    }\n\t    return TCL_OK;\n\n\tcase '=':\n\t    if (p[1] == '=') {\n\t\tinfoPtr->expr = p+2;\n\t\tinfoPtr->token = EQUAL;\n\t    } else {\n\t\tinfoPtr->token = UNKNOWN;\n\t    }\n\t    return TCL_OK;\n\n\tcase '!':\n\t    if (p[1] == '=') {\n\t\tinfoPtr->expr = p+2;\n\t\tinfoPtr->token = NEQ;\n\t    } else {\n\t\tinfoPtr->token = NOT;\n\t    }\n\t    return TCL_OK;\n\n\tcase '&':\n\t    if (p[1] == '&') {\n\t\tinfoPtr->expr = p+2;\n\t\tinfoPtr->token = AND;\n\t    } else {\n\t\tinfoPtr->token = BIT_AND;\n\t    }\n\t    return TCL_OK;\n\n\tcase '^':\n\t    infoPtr->token = BIT_XOR;\n\t    return TCL_OK;\n\n\tcase '|':\n\t    if (p[1] == '|') {\n\t\tinfoPtr->expr = p+2;\n\t\tinfoPtr->token = OR;\n\t    } else {\n\t\tinfoPtr->token = BIT_OR;\n\t    }\n\t    return TCL_OK;\n\n\tcase '~':\n\t    infoPtr->token = BIT_NOT;\n\t    return TCL_OK;\n\n\tcase 0:\n\t    infoPtr->token = END;\n\t    infoPtr->expr = p;\n\t    return TCL_OK;\n\n\tdefault:\n\t    infoPtr->expr = p+1;\n\t    infoPtr->token = UNKNOWN;\n\t    return TCL_OK;\n    }\n}\n\f\n/*\n * Parse a \"value\" from the remainder of the expression in infoPtr.\n *\n * Results:\n *\tNormally TCL_OK is returned.  The value of the expression is\n *\treturned in *valuePtr.  If an error occurred, then interp->result\n *\tcontains an error message and TCL_ERROR is returned.\n *\tInfoPtr->token will be left pointing to the token AFTER the\n *\texpression, and infoPtr->expr will point to the character just\n *\tafter the terminating token.\n *\n * Side effects:\n *\tNone.\n */\nstatic unsigned char\nget_value (Tcl_Interp *interp,\t/* Interpreter to use for error reporting. */\n\tExpr_info_t *infoPtr,\t/* Describes the state of the parse just\n\t\t\t\t * before the value (i.e. get_lex will be\n\t\t\t\t * called to get first token of value). */\n\tint prec,\t\t/* Treat any un-parenthesized operator\n\t\t\t\t * with precedence <= this as the end\n\t\t\t\t * of the expression. */\n\tValue_t *valuePtr)\t/* Where to store the value of the\n\t\t\t\t * expression.  Caller must have\n\t\t\t\t * initialized pv field. */\n{\n    Interp *iPtr = (Interp *) interp;\n    Value_t value2;\t\t\t/* Second operand for current\n\t\t\t\t\t * operator.  */\n    int operator;\t\t\t/* Current operator (either unary\n\t\t\t\t\t * or binary). */\n    int gotOp;\t\t\t\t/* Non-zero means already lexed the\n\t\t\t\t\t * operator (while picking up value\n\t\t\t\t\t * for unary operator).  Don't lex\n\t\t\t\t\t * again. */\n    unsigned char result;\n\n    /*\n     * There are two phases to this procedure.  First, pick off an initial\n     * value.  Then, parse (binary operator, value) pairs until done.\n     */\n\n    gotOp = 0;\n    value2.pv.buffer = value2.pv.next = value2.static_space;\n    value2.pv.end = value2.pv.buffer + STATIC_STRING_SPACE - 1;\n    value2.pv.expandProc = TclExpandParseValue;\n    value2.pv.clientData = (void*) 0;\n    result = get_lex(interp, infoPtr, valuePtr);\n    if (result != TCL_OK) {\n\tgoto done;\n    }\n    if (infoPtr->token == OPEN_PAREN) {\n\n\t/*\n\t * Parenthesized sub-expression.\n\t */\n\n\tresult = get_value(interp, infoPtr, -1, valuePtr);\n\tif (result != TCL_OK) {\n\t    goto done;\n\t}\n\tif (infoPtr->token != CLOSE_PAREN) {\n\t    Tcl_ResetResult(interp);\n\t    Tcl_AppendResult(interp,\n\t\t    \"unmatched parentheses in expression \\\"\",\n\t\t    infoPtr->original_expr, \"\\\"\", 0);\n\t    result = TCL_ERROR;\n\t    goto done;\n\t}\n    } else {\n\tif (infoPtr->token == MINUS) {\n\t    infoPtr->token = UNARY_MINUS;\n\t}\n\tif (infoPtr->token >= UNARY_MINUS) {\n\n\t    /*\n\t     * Process unary operators.\n\t     */\n\n\t    operator = infoPtr->token;\n\t    result = get_value(interp, infoPtr, prec_table[infoPtr->token],\n\t\t    valuePtr);\n\t    if (result != TCL_OK) {\n\t\tgoto done;\n\t    }\n\t    switch (operator) {\n\t\tcase UNARY_MINUS:\n\t\t    if (valuePtr->type == TYPE_INT) {\n\t\t\tvaluePtr->int_value = -valuePtr->int_value;\n\t\t    } else {\n\t\t\tgoto illegalType;\n\t\t    }\n\t\t    break;\n\t\tcase NOT:\n\t\t    if (valuePtr->type == TYPE_INT) {\n\t\t\tvaluePtr->int_value = !valuePtr->int_value;\n\t\t    } else {\n\t\t\tgoto illegalType;\n\t\t    }\n\t\t    break;\n\t\tcase BIT_NOT:\n\t\t    if (valuePtr->type == TYPE_INT) {\n\t\t\tvaluePtr->int_value = ~valuePtr->int_value;\n\t\t    } else {\n\t\t\tgoto illegalType;\n\t\t    }\n\t\t    break;\n\t    }\n\t    gotOp = 1;\n\t} else if (infoPtr->token != VALUE) {\n\t    goto syntaxError;\n\t}\n    }\n\n    /*\n     * Got the first operand.  Now fetch (operator, operand) pairs.\n     */\n\n    if (!gotOp) {\n\tresult = get_lex(interp, infoPtr, &value2);\n\tif (result != TCL_OK) {\n\t    goto done;\n\t}\n    }\n    while (1) {\n\toperator = infoPtr->token;\n\tvalue2.pv.next = value2.pv.buffer;\n\tif ((operator < MULT) || (operator >= UNARY_MINUS)) {\n\t    if ((operator == END) || (operator == CLOSE_PAREN)) {\n\t\tresult = TCL_OK;\n\t\tgoto done;\n\t    } else {\n\t\tgoto syntaxError;\n\t    }\n\t}\n\tif (prec_table[operator] <= prec) {\n\t    result = TCL_OK;\n\t    goto done;\n\t}\n\n\t/*\n\t * If we're doing an AND or OR and the first operand already\n\t * determines the result, don't execute anything in the\n\t * second operand:  just parse.  Same style for ?: pairs.\n\t */\n\n\tif ((operator == AND) || (operator == OR) || (operator == QUESTY)) {\n\t    if (valuePtr->type == TYPE_STRING) {\n\t\tgoto illegalType;\n\t    }\n\t    if (((operator == AND) && !valuePtr->int_value)\n\t\t    || ((operator == OR) && valuePtr->int_value)) {\n\t\tiPtr->noEval++;\n\t\tresult = get_value(interp, infoPtr, prec_table[operator],\n\t\t\t&value2);\n\t\tiPtr->noEval--;\n\t    } else if (operator == QUESTY) {\n\t\tif (valuePtr->int_value != 0) {\n\t\t    valuePtr->pv.next = valuePtr->pv.buffer;\n\t\t    result = get_value(interp, infoPtr, prec_table[operator],\n\t\t\t    valuePtr);\n\t\t    if (result != TCL_OK) {\n\t\t\tgoto done;\n\t\t    }\n\t\t    if (infoPtr->token != COLON) {\n\t\t\tgoto syntaxError;\n\t\t    }\n\t\t    value2.pv.next = value2.pv.buffer;\n\t\t    iPtr->noEval++;\n\t\t    result = get_value(interp, infoPtr, prec_table[operator],\n\t\t\t    &value2);\n\t\t    iPtr->noEval--;\n\t\t} else {\n\t\t    iPtr->noEval++;\n\t\t    result = get_value(interp, infoPtr, prec_table[operator],\n\t\t\t    &value2);\n\t\t    iPtr->noEval--;\n\t\t    if (result != TCL_OK) {\n\t\t\tgoto done;\n\t\t    }\n\t\t    if (infoPtr->token != COLON) {\n\t\t\tgoto syntaxError;\n\t\t    }\n\t\t    valuePtr->pv.next = valuePtr->pv.buffer;\n\t\t    result = get_value(interp, infoPtr, prec_table[operator],\n\t\t\t    valuePtr);\n\t\t}\n\t    } else {\n\t\tresult = get_value(interp, infoPtr, prec_table[operator],\n\t\t\t&value2);\n\t    }\n\t} else {\n\t    result = get_value(interp, infoPtr, prec_table[operator],\n\t\t    &value2);\n\t}\n\tif (result != TCL_OK) {\n\t    goto done;\n\t}\n\tif ((infoPtr->token < MULT) && (infoPtr->token != VALUE)\n\t\t&& (infoPtr->token != END)\n\t\t&& (infoPtr->token != CLOSE_PAREN)) {\n\t    goto syntaxError;\n\t}\n\n\t/*\n\t * At this point we've got two values and an operator.  Check\n\t * to make sure that the particular data types are appropriate\n\t * for the particular operator, and perform type conversion\n\t * if necessary.\n\t */\n\n\tswitch (operator) {\n\n\t    /*\n\t     * For the operators below, no strings are allowed and\n\t     * ints get converted to floats if necessary.\n\t     */\n\n\t    case MULT: case DIVIDE: case PLUS: case MINUS:\n\t\tif ((valuePtr->type == TYPE_STRING)\n\t\t\t|| (value2.type == TYPE_STRING)) {\n\t\t    goto illegalType;\n\t\t}\n\t\tbreak;\n\n\t    /*\n\t     * For the operators below, only integers are allowed.\n\t     */\n\n\t    case MOD: case LEFT_SHIFT: case RIGHT_SHIFT:\n\t    case BIT_AND: case BIT_XOR: case BIT_OR:\n\t\t if (valuePtr->type != TYPE_INT) {\n\t\t     goto illegalType;\n\t\t } else if (value2.type != TYPE_INT) {\n\t\t     goto illegalType;\n\t\t }\n\t\t break;\n\n\t    /*\n\t     * For the operators below, any type is allowed but the\n\t     * two operands must have the same type.  Convert integers\n\t     * to floats and either to strings, if necessary.\n\t     */\n\n\t    case LESS: case GREATER: case LEQ: case GEQ:\n\t    case EQUAL: case NEQ:\n\t\tif (valuePtr->type == TYPE_STRING) {\n\t\t    if (value2.type != TYPE_STRING) {\n\t\t\tmake_string (&value2);\n\t\t    }\n\t\t} else if (value2.type == TYPE_STRING) {\n\t\t    if (valuePtr->type != TYPE_STRING) {\n\t\t\tmake_string (valuePtr);\n\t\t    }\n\t\t}\n\t\tbreak;\n\n\t    /*\n\t     * For the operators below, no strings are allowed.\n\t     */\n\t    case AND: case OR:\n\t\tif (valuePtr->type == TYPE_STRING) {\n\t\t    goto illegalType;\n\t\t}\n\t\tif (value2.type == TYPE_STRING) {\n\t\t    goto illegalType;\n\t\t}\n\t\tbreak;\n\n\t    /*\n\t     * For the operators below, type and conversions are\n\t     * irrelevant:  they're handled elsewhere.\n\t     */\n\n\t    case QUESTY: case COLON:\n\t\tbreak;\n\n\t    /*\n\t     * Any other operator is an error.\n\t     */\n\n\t    default:\n\t\tinterp->result = (unsigned char*) \"unknown operator in expression\";\n\t\tresult = TCL_ERROR;\n\t\tgoto done;\n\t}\n\n\t/*\n\t * If necessary, convert one of the operands to the type\n\t * of the other.  If the operands are incompatible with\n\t * the operator (e.g. \"+\" on strings) then return an\n\t * error.\n\t */\n\n\tswitch (operator) {\n\t    case MULT:\n\t\tif (valuePtr->type == TYPE_INT) {\n\t\t    valuePtr->int_value *= value2.int_value;\n\t\t}\n\t\tbreak;\n\t    case DIVIDE:\n\t\tif (valuePtr->type == TYPE_INT) {\n\t\t    if (value2.int_value == 0) {\n\t\t\tdivideByZero:\n\t\t\tinterp->result = (unsigned char*) \"divide by zero\";\n\t\t\tresult = TCL_ERROR;\n\t\t\tgoto done;\n\t\t    }\n\t\t    valuePtr->int_value /= value2.int_value;\n\t\t}\n\t\tbreak;\n\t    case MOD:\n\t\tif (value2.int_value == 0) {\n\t\t    goto divideByZero;\n\t\t}\n\t\tvaluePtr->int_value %= value2.int_value;\n\t\tbreak;\n\t    case PLUS:\n\t\tif (valuePtr->type == TYPE_INT) {\n\t\t    valuePtr->int_value += value2.int_value;\n\t\t}\n\t\tbreak;\n\t    case MINUS:\n\t\tif (valuePtr->type == TYPE_INT) {\n\t\t    valuePtr->int_value -= value2.int_value;\n\t\t}\n\t\tbreak;\n\t    case LEFT_SHIFT:\n\t\tvaluePtr->int_value <<= value2.int_value;\n\t\tbreak;\n\t    case RIGHT_SHIFT:\n\t\t/*\n\t\t * The following code is a bit tricky:  it ensures that\n\t\t * right shifts propagate the sign bit even on machines\n\t\t * where \">>\" won't do it by default.\n\t\t */\n\n\t\tif (valuePtr->int_value < 0) {\n\t\t    valuePtr->int_value =\n\t\t\t    ~((~valuePtr->int_value) >> value2.int_value);\n\t\t} else {\n\t\t    valuePtr->int_value >>= value2.int_value;\n\t\t}\n\t\tbreak;\n\t    case LESS:\n\t\tif (valuePtr->type == TYPE_INT) {\n\t\t    valuePtr->int_value =\n\t\t\tvaluePtr->int_value < value2.int_value;\n\t\t} else {\n\t\t    valuePtr->int_value =\n\t\t\t    strcmp(valuePtr->pv.buffer, value2.pv.buffer) < 0;\n\t\t}\n\t\tvaluePtr->type = TYPE_INT;\n\t\tbreak;\n\t    case GREATER:\n\t\tif (valuePtr->type == TYPE_INT) {\n\t\t    valuePtr->int_value =\n\t\t\tvaluePtr->int_value > value2.int_value;\n\t\t} else {\n\t\t    valuePtr->int_value =\n\t\t\t    strcmp(valuePtr->pv.buffer, value2.pv.buffer) > 0;\n\t\t}\n\t\tvaluePtr->type = TYPE_INT;\n\t\tbreak;\n\t    case LEQ:\n\t\tif (valuePtr->type == TYPE_INT) {\n\t\t    valuePtr->int_value =\n\t\t\tvaluePtr->int_value <= value2.int_value;\n\t\t} else {\n\t\t    valuePtr->int_value =\n\t\t\t    strcmp(valuePtr->pv.buffer, value2.pv.buffer) <= 0;\n\t\t}\n\t\tvaluePtr->type = TYPE_INT;\n\t\tbreak;\n\t    case GEQ:\n\t\tif (valuePtr->type == TYPE_INT) {\n\t\t    valuePtr->int_value =\n\t\t\tvaluePtr->int_value >= value2.int_value;\n\t\t} else {\n\t\t    valuePtr->int_value =\n\t\t\t    strcmp(valuePtr->pv.buffer, value2.pv.buffer) >= 0;\n\t\t}\n\t\tvaluePtr->type = TYPE_INT;\n\t\tbreak;\n\t    case EQUAL:\n\t\tif (valuePtr->type == TYPE_INT) {\n\t\t    valuePtr->int_value =\n\t\t\tvaluePtr->int_value == value2.int_value;\n\t\t} else {\n\t\t    valuePtr->int_value =\n\t\t\t    strcmp(valuePtr->pv.buffer, value2.pv.buffer) == 0;\n\t\t}\n\t\tvaluePtr->type = TYPE_INT;\n\t\tbreak;\n\t    case NEQ:\n\t\tif (valuePtr->type == TYPE_INT) {\n\t\t    valuePtr->int_value =\n\t\t\tvaluePtr->int_value != value2.int_value;\n\t\t} else {\n\t\t    valuePtr->int_value =\n\t\t\t    strcmp(valuePtr->pv.buffer, value2.pv.buffer) != 0;\n\t\t}\n\t\tvaluePtr->type = TYPE_INT;\n\t\tbreak;\n\t    case BIT_AND:\n\t\tvaluePtr->int_value &= value2.int_value;\n\t\tbreak;\n\t    case BIT_XOR:\n\t\tvaluePtr->int_value ^= value2.int_value;\n\t\tbreak;\n\t    case BIT_OR:\n\t\tvaluePtr->int_value |= value2.int_value;\n\t\tbreak;\n\n\t    case AND:\n\t\tvaluePtr->int_value = valuePtr->int_value && value2.int_value;\n\t\tbreak;\n\t    case OR:\n\t\tvaluePtr->int_value = valuePtr->int_value || value2.int_value;\n\t\tbreak;\n\n\t    case COLON:\n\t\tinterp->result = (unsigned char*) \"can't have : operator without ? first\";\n\t\tresult = TCL_ERROR;\n\t\tgoto done;\n\t}\n    }\n\n    done:\n    if (value2.pv.buffer != value2.static_space) {\n\tfree (value2.pv.buffer);\n    }\n    return result;\n\n    syntaxError:\n    Tcl_ResetResult(interp);\n    Tcl_AppendResult(interp, \"syntax error in expression \\\"\",\n\t    infoPtr->original_expr, \"\\\"\", 0);\n    result = TCL_ERROR;\n    goto done;\n\n    illegalType:\n    Tcl_AppendResult(interp, \"can't use non-numeric string as operand of \\\"\",\n            operator_strings[operator], \"\\\"\", 0);\n    result = TCL_ERROR;\n    goto done;\n}\n\f\n/*\n * Convert a value from int representation to a string.\n *\n * Results:\n *\tThe information at *valuePtr gets converted to string\n *\tformat, if it wasn't that way already.\n *\n * Side effects:\n *\tNone.\n */\nstatic void\nmake_string (Value_t *valuePtr)\t\t/* Value to be converted. */\n{\n    unsigned short space;\n\n    space = valuePtr->pv.end - valuePtr->pv.buffer;\n    if (20 > space) {\n\t(*valuePtr->pv.expandProc) (&valuePtr->pv, 20 - space);\n    }\n    if (valuePtr->type == TYPE_INT) {\n\tsprintf (valuePtr->pv.buffer, \"%ld\", valuePtr->int_value);\n    }\n    valuePtr->type = TYPE_STRING;\n}\n\f\n/*\n * This procedure provides top-level functionality shared by\n * procedures like Tcl_ExprInt, etc.\n *\n * Results:\n *\tThe result is a standard Tcl return value.  If an error\n *\toccurs then an error message is left in interp->result.\n *\tThe value of the expression is returned in *valuePtr, in\n *\twhatever form it ends up in (could be string or integer).\n *\tCaller may need to convert result.  Caller\n *\tis also responsible for freeing string memory in *valuePtr,\n *\tif any was allocated.\n *\n * Side effects:\n *\tNone.\n */\nstatic unsigned char\nevaluate (Tcl_Interp *interp,\t/* Context in which to evaluate the\n\t\t\t\t * expression. */\n\tunsigned char *string,\t/* Expression to evaluate. */\n\tValue_t *valuePtr)\t/* Where to store result.  Should\n\t\t\t\t * not be initialized by caller. */\n{\n    Expr_info_t info;\n    unsigned char result;\n\n    info.original_expr = string;\n    info.expr = string;\n    valuePtr->pv.buffer = valuePtr->pv.next = valuePtr->static_space;\n    valuePtr->pv.end = valuePtr->pv.buffer + STATIC_STRING_SPACE - 1;\n    valuePtr->pv.expandProc = TclExpandParseValue;\n    valuePtr->pv.clientData = (void*) 0;\n\n    result = get_value(interp, &info, -1, valuePtr);\n    if (result != TCL_OK) {\n\treturn result;\n    }\n    if (info.token != END) {\n\tTcl_AppendResult(interp, \"syntax error in expression \\\"\",\n\t\tstring, \"\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    return TCL_OK;\n}\n\f\n/*\n * Procedures to evaluate an expression and return its value\n * in a particular form.\n *\n * Results:\n *\tEach of the procedures below returns a standard Tcl result.\n *\tIf an error occurs then an error message is left in\n *\tinterp->result.  Otherwise the value of the expression,\n *\tin the appropriate form, is stored at *resultPtr.  If\n *\tthe expression had a result that was incompatible with the\n *\tdesired form then an error is returned.\n *\n * Side effects:\n *\tNone.\n */\nint\nTcl_ExprLong (Tcl_Interp *interp,\t/* Context in which to evaluate the\n\t\t\t\t\t * expression. */\n\tunsigned char *string,\t\t/* Expression to evaluate. */\n\tlong *ptr)\t\t\t/* Where to store result. */\n{\n    Value_t value;\n    unsigned char result;\n\n    result = evaluate (interp, string, &value);\n    if (result == TCL_OK) {\n\tif (value.type == TYPE_INT) {\n\t    *ptr = value.int_value;\n\t} else {\n\t    interp->result = (unsigned char*) \"expression didn't have numeric value\";\n\t    result = TCL_ERROR;\n\t}\n    }\n    if (value.pv.buffer != value.static_space) {\n\tfree (value.pv.buffer);\n    }\n    return result;\n}\n\nint\nTcl_ExprBoolean (Tcl_Interp *interp,\t/* Context in which to evaluate the\n\t\t\t\t\t * expression. */\n\tunsigned char *string,\t\t/* Expression to evaluate. */\n\tint *ptr)\t\t\t/* Where to store 0/1 result. */\n{\n    Value_t value;\n    unsigned char result;\n\n    result = evaluate (interp, string, &value);\n    if (result == TCL_OK) {\n\tif (value.type == TYPE_INT) {\n\t    *ptr = value.int_value != 0;\n\t} else {\n\t    interp->result = (unsigned char*) \"expression didn't have numeric value\";\n\t    result = TCL_ERROR;\n\t}\n    }\n    if (value.pv.buffer != value.static_space) {\n\tfree (value.pv.buffer);\n    }\n    return result;\n}\n\f\n/*\n * Evaluate an expression and return its value in string form.\n *\n * Results:\n *\tA standard Tcl result.  If the result is TCL_OK, then the\n *\tinterpreter's result is set to the string value of the\n *\texpression.  If the result is TCL_OK, then interp->result\n *\tcontains an error message.\n *\n * Side effects:\n *\tNone.\n */\nint\nTcl_ExprString (Tcl_Interp *interp,\t/* Context in which to evaluate the\n\t\t\t\t\t * expression. */\n\tunsigned char *string)\t\t/* Expression to evaluate. */\n{\n    Value_t value;\n    unsigned char result;\n\n    result = evaluate (interp, string, &value);\n    if (result == TCL_OK) {\n\tif (value.type == TYPE_INT) {\n\t    sprintf (interp->result, \"%ld\", value.int_value);\n\t} else {\n\t    if (value.pv.buffer != value.static_space) {\n\t\tinterp->result = value.pv.buffer;\n\t\tinterp->freeProc = (Tcl_FreeProc *) free;\n\t\tvalue.pv.buffer = value.static_space;\n\t    } else {\n\t\tTcl_SetResult (interp, value.pv.buffer, TCL_VOLATILE);\n\t    }\n\t}\n    }\n    if (value.pv.buffer != value.static_space) {\n\tfree (value.pv.buffer);\n    }\n    return result;\n}\n"
  },
  {
    "path": "lib/libtcl/tclget.c",
    "content": "/*\n * tclGet.c --\n *\n *\tThis file contains procedures to convert strings into\n *\tother forms, like integers or floating-point numbers or\n *\tbooleans, doing syntax checking along the way.\n *\n * Copyright 1990-1991 Regents of the University of California\n * Permission to use, copy, modify, and distribute this\n * software and its documentation for any purpose and without\n * fee is hereby granted, provided that the above copyright\n * notice appear in all copies.  The University of California\n * makes no representations about the suitability of this\n * software for any purpose.  It is provided \"as is\" without\n * express or implied warranty.\n */\n#include \"internal.h\"\n\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_GetInt --\n *\n *\tGiven a string, produce the corresponding integer value.\n *\n * Results:\n *\tThe return value is normally TCL_OK;  in this case *intPtr\n *\twill be set to the integer value equivalent to string.  If\n *\tstring is improperly formed then TCL_ERROR is returned and\n *\tan error message will be left in interp->result.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTcl_GetInt(interp, string, intPtr)\n    Tcl_Interp *interp;\t\t/* Interpreter to use for error reporting. */\n    char *string;\t\t/* String containing a (possibly signed)\n\t\t\t\t * integer in a form acceptable to strtol. */\n    int *intPtr;\t\t/* Place to store converted result. */\n{\n    char *end;\n    int i;\n\n    i = strtol(string, &end, 0);\n    while ((*end != '\\0') && isspace(*end)) {\n\tend++;\n    }\n    if ((end == string) || (*end != 0)) {\n\tTcl_AppendResult(interp, \"expected integer but got \\\"\", string,\n\t\t\"\\\"\", (char *) 0);\n\treturn TCL_ERROR;\n    }\n    *intPtr = i;\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_GetBoolean --\n *\n *\tGiven a string, return a 0/1 boolean value corresponding\n *\tto the string.\n *\n * Results:\n *\tThe return value is normally TCL_OK;  in this case *boolPtr\n *\twill be set to the 0/1 value equivalent to string.  If\n *\tstring is improperly formed then TCL_ERROR is returned and\n *\tan error message will be left in interp->result.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTcl_GetBoolean(interp, string, boolPtr)\n    Tcl_Interp *interp;\t\t/* Interpreter to use for error reporting. */\n    unsigned char *string;\t/* String containing a boolean number\n\t\t\t\t * specified either as 1/0 or true/false or\n\t\t\t\t * yes/no. */\n    int *boolPtr;\t\t/* Place to store converted result, which\n\t\t\t\t * will be 0 or 1. */\n{\n    char c;\n    unsigned char lowerCase[10];\n    int i, length;\n\n    /*\n     * Convert the input string to all lower-case.\n     */\n\n    for (i = 0; i < 9; i++) {\n\tc = string[i];\n\tif (c == 0) {\n\t    break;\n\t}\n\tif ((c >= 'A') && (c <= 'Z')) {\n\t    c += 'a' - 'A';\n\t}\n\tlowerCase[i] = c;\n    }\n    lowerCase[i] = 0;\n\n    length = strlen(lowerCase);\n    c = lowerCase[0];\n    if ((c == '0') && (lowerCase[1] == '\\0')) {\n\t*boolPtr = 0;\n    } else if ((c == '1') && (lowerCase[1] == '\\0')) {\n\t*boolPtr = 1;\n    } else if ((c == 'y') && (strncmp(lowerCase, (unsigned char*) \"yes\", length) == 0)) {\n\t*boolPtr = 1;\n    } else if ((c == 'n') && (strncmp(lowerCase, (unsigned char*) \"no\", length) == 0)) {\n\t*boolPtr = 0;\n    } else if ((c == 't') && (strncmp(lowerCase, (unsigned char*) \"true\", length) == 0)) {\n\t*boolPtr = 1;\n    } else if ((c == 'f') && (strncmp(lowerCase, (unsigned char*) \"false\", length) == 0)) {\n\t*boolPtr = 0;\n    } else if ((c == 'o') && (length >= 2)) {\n\tif (strncmp(lowerCase, (unsigned char*) \"on\", length) == 0) {\n\t    *boolPtr = 1;\n\t} else if (strncmp(lowerCase, (unsigned char*) \"off\", length) == 0) {\n\t    *boolPtr = 0;\n\t}\n    } else {\n\tTcl_AppendResult(interp, \"expected boolean value but got \\\"\",\n\t\tstring, \"\\\"\", (char *) 0);\n\treturn TCL_ERROR;\n    }\n    return TCL_OK;\n}\n"
  },
  {
    "path": "lib/libtcl/tclglob.c",
    "content": "/*\n * tclGlob.c --\n *\n *\tThis file provides procedures and commands for file name\n *\tmanipulation, such as tilde expansion and globbing.\n *\n * Copyright 1990-1991 Regents of the University of California\n * Permission to use, copy, modify, and distribute this\n * software and its documentation for any purpose and without\n * fee is hereby granted, provided that the above copyright\n * notice appear in all copies.  The University of California\n * makes no representations about the suitability of this\n * software for any purpose.  It is provided \"as is\" without\n * express or implied warranty.\n */\n#include \"internal.h\"\n#include <sys/stat.h>\n#include <unistd.h>\n#include <pwd.h>\n#ifdef CROSS\n#   include <dirent.h>\n#else\n#   include <sys/dir.h>\n#   define dirent direct\n#endif\n\n/*\n * The structure below is used to keep track of a globbing result\n * being built up (i.e. a partial list of file names).  The list\n * grows dynamically to be as big as needed.\n */\n\ntypedef struct {\n    char *result;\t\t/* Pointer to result area. */\n    int totalSpace;\t\t/* Total number of characters allocated\n\t\t\t\t * for result. */\n    int spaceUsed;\t\t/* Number of characters currently in use\n\t\t\t\t * to hold the partial result (not including\n\t\t\t\t * the terminating NULL). */\n    int dynamic;\t\t/* 0 means result is static space, 1 means\n\t\t\t\t * it's dynamic. */\n} GlobResult;\n\n/*\n * Declarations for procedures local to this file:\n */\n\nstatic void\t\tAppendResult (Tcl_Interp *interp,\n\t\t\t    char *dir, char *separator, char *name,\n\t\t\t    int nameLength);\nstatic int\t\tDoGlob (Tcl_Interp *interp, char *dir,\n\t\t\t    char *rem);\n\f\n/*\n *----------------------------------------------------------------------\n *\n * AppendResult --\n *\n *\tGiven two parts of a file name (directory and element within\n *\tdirectory), concatenate the two together and append them to\n *\tthe result building up in interp.\n *\n * Results:\n *\tThere is no return value.\n *\n * Side effects:\n *\tInterp->result gets extended.\n *\n *----------------------------------------------------------------------\n */\n\nstatic void\nAppendResult(interp, dir, separator, name, nameLength)\n    Tcl_Interp *interp;\t\t/* Interpreter whose result should be\n\t\t\t\t * appended to. */\n    char *dir;\t\t\t/* Name of directory, without trailing\n\t\t\t\t * slash except for root directory. */\n    char *separator;\t\t/* Separator string so use between dir and\n\t\t\t\t * name:  either \"/\" or \"\" depending on dir. */\n    char *name;\t\t\t/* Name of file withing directory (NOT\n\t\t\t\t * necessarily null-terminated!). */\n    int nameLength;\t\t/* Number of characters in name. */\n{\n    int dirFlags, nameFlags;\n    char *p, saved;\n\n    /*\n     * Next, see if we can put together a valid list element from dir\n     * and name by calling Tcl_AppendResult.\n     */\n\n    if (*dir == 0) {\n\tdirFlags = 0;\n    } else {\n\tTcl_ScanElement(dir, &dirFlags);\n    }\n    saved = name[nameLength];\n    name[nameLength] = 0;\n    Tcl_ScanElement(name, &nameFlags);\n    if ((dirFlags == 0) && (nameFlags == 0)) {\n\tif (*interp->result != 0) {\n\t    Tcl_AppendResult(interp, \" \", dir, separator, name, (char *) NULL);\n\t} else {\n\t    Tcl_AppendResult(interp, dir, separator, name, (char *) NULL);\n\t}\n\tname[nameLength] = saved;\n\treturn;\n    }\n\n    /*\n     * This name has weird characters in it, so we have to convert it to\n     * a list element.  To do that, we have to merge the characters\n     * into a single name.  To do that, malloc a buffer to hold everything.\n     */\n\n    p = (char *) malloc((unsigned) (strlen(dir) + strlen(separator)\n\t    + nameLength + 1));\n    sprintf(p, \"%s%s%s\", dir, separator, name);\n    name[nameLength] = saved;\n    Tcl_AppendElement(interp, p, 0);\n    free(p);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * DoGlob --\n *\n *\tThis recursive procedure forms the heart of the globbing\n *\tcode.  It performs a depth-first traversal of the tree\n *\tgiven by the path name to be globbed.\n *\n * Results:\n *\tThe return value is a standard Tcl result indicating whether\n *\tan error occurred in globbing.  After a normal return the\n *\tresult in interp will be set to hold all of the file names\n *\tgiven by the dir and rem arguments.  After an error the\n *\tresult in interp will hold an error message.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nstatic int\nDoGlob(interp, dir, rem)\n    Tcl_Interp *interp;\t\t\t/* Interpreter to use for error\n\t\t\t\t\t * reporting (e.g. unmatched brace). */\n    char *dir;\t\t\t\t/* Name of a directory at which to\n\t\t\t\t\t * start glob expansion.  This name\n\t\t\t\t\t * is fixed: it doesn't contain any\n\t\t\t\t\t * globbing chars. */\n    char *rem;\t\t\t\t/* Path to glob-expand. */\n{\n    /*\n     * When this procedure is entered, the name to be globbed may\n     * already have been partly expanded by ancestor invocations of\n     * DoGlob.  The part that's already been expanded is in \"dir\"\n     * (this may initially be empty), and the part still to expand\n     * is in \"rem\".  This procedure expands \"rem\" one level, making\n     * recursive calls to itself if there's still more stuff left\n     * in the remainder.\n     */\n\n    register char *p;\n    register char c;\n    char *openBrace, *closeBrace;\n    int gotSpecial, result;\n    char *separator;\n\n    /*\n     * Figure out whether we'll need to add a slash between the directory\n     * name and file names within the directory when concatenating them\n     * together.\n     */\n\n    if ((dir[0] == 0) || ((dir[0] == '/') && (dir[1] == 0))) {\n\tseparator = \"\";\n    } else {\n\tseparator = \"/\";\n    }\n\n    /*\n     * When generating information for the next lower call,\n     * use static areas if the name is short, and malloc if the name\n     * is longer.\n     */\n\n#define STATIC_SIZE 200\n\n    /*\n     * First, find the end of the next element in rem, checking\n     * along the way for special globbing characters.\n     */\n\n    gotSpecial = 0;\n    openBrace = closeBrace = NULL;\n    for (p = rem; ; p++) {\n\tc = *p;\n\tif ((c == '\\0') || (c == '/')) {\n\t    break;\n\t}\n\tif ((c == '{') && (openBrace == NULL)) {\n\t    openBrace = p;\n\t}\n\tif ((c == '}') && (closeBrace == NULL)) {\n\t    closeBrace = p;\n\t}\n\tif ((c == '*') || (c == '[') || (c == '\\\\') || (c == '?')) {\n\t    gotSpecial = 1;\n\t}\n    }\n\n    /*\n     * If there is an open brace in the argument, then make a recursive\n     * call for each element between the braces.  In this case, the\n     * recursive call to DoGlob uses the same \"dir\" that we got.\n     * If there are several brace-pairs in a single name, we just handle\n     * one here, and the others will be handled in recursive calls.\n     */\n\n    if (openBrace != NULL) {\n\tint remLength, l1, l2;\n\tchar static1[STATIC_SIZE];\n\tchar *element, *newRem;\n\n\tif (closeBrace == NULL) {\n\t    Tcl_ResetResult(interp);\n\t    interp->result = \"unmatched open-brace in file name\";\n\t    return TCL_ERROR;\n\t}\n\tremLength = strlen(rem) + 1;\n\tif (remLength <= STATIC_SIZE) {\n\t    newRem = static1;\n\t} else {\n\t    newRem = (char *) malloc((unsigned) remLength);\n\t}\n\tl1 = openBrace-rem;\n\tstrncpy(newRem, rem, l1);\n\tp = openBrace;\n\tfor (p = openBrace; *p != '}'; ) {\n\t    element = p+1;\n\t    for (p = element; ((*p != '}') && (*p != ',')); p++) {\n\t\t/* Empty loop body:  just find end of this element. */\n\t    }\n\t    l2 = p - element;\n\t    strncpy(newRem+l1, element, l2);\n\t    strcpy(newRem+l1+l2, closeBrace+1);\n\t    if (DoGlob(interp, dir, newRem) != TCL_OK) {\n\t\treturn TCL_ERROR;\n\t    }\n\t}\n\tif (remLength > STATIC_SIZE) {\n\t    free(newRem);\n\t}\n\treturn TCL_OK;\n    }\n\n    /*\n     * If there were any pattern-matching characters, then scan through\n     * the directory to find all the matching names.\n     */\n\n    if (gotSpecial) {\n\tDIR *d;\n\tstruct dirent *entryPtr;\n\tint l1, l2;\n\tchar *pattern, *newDir, *dirName;\n\tchar static1[STATIC_SIZE], static2[STATIC_SIZE];\n\tstruct stat statBuf;\n\n\t/*\n\t * Be careful not to do any actual file system operations on a\n\t * directory named \"\";  instead, use \".\".  This is needed because\n\t * some versions of UNIX don't treat \"\" like \".\" automatically.\n\t */\n\n\tif (*dir == '\\0') {\n\t    dirName = \".\";\n\t} else {\n\t    dirName = dir;\n\t}\n\tif ((stat(dirName, &statBuf) != 0) || !S_ISDIR(statBuf.st_mode)) {\n\t    return TCL_OK;\n\t}\n\td = opendir(dirName);\n\tif (d == NULL) {\n\t    Tcl_ResetResult(interp);\n\t    Tcl_AppendResult(interp, \"couldn't read directory \\\"\",\n\t\t    dirName, \"\\\": \", Tcl_UnixError(interp), (char *) NULL);\n\t    return TCL_ERROR;\n\t}\n\tl1 = strlen(dir);\n\tl2 = (p - rem);\n\tif (l2 < STATIC_SIZE) {\n\t    pattern = static2;\n\t} else {\n\t    pattern = (char *) malloc((unsigned) (l2+1));\n\t}\n\tstrncpy(pattern, rem, l2);\n\tpattern[l2] = '\\0';\n\tresult = TCL_OK;\n\twhile (1) {\n\t    entryPtr = readdir(d);\n\t    if (entryPtr == NULL) {\n\t\tbreak;\n\t    }\n\n\t    /*\n\t     * Don't match names starting with \".\" unless the \".\" is\n\t     * present in the pattern.\n\t     */\n\n\t    if ((*entryPtr->d_name == '.') && (*pattern != '.')) {\n\t\tcontinue;\n\t    }\n\t    if (Tcl_StringMatch(entryPtr->d_name, pattern)) {\n\t\tint nameLength = strlen(entryPtr->d_name);\n\t\tif (*p == 0) {\n\t\t    AppendResult(interp, dir, separator, entryPtr->d_name,\n\t\t\t    nameLength);\n\t\t} else {\n\t\t    if ((l1+nameLength+2) <= STATIC_SIZE) {\n\t\t\tnewDir = static1;\n\t\t    } else {\n\t\t\tnewDir = (char *) malloc((unsigned) (l1+nameLength+2));\n\t\t    }\n\t\t    sprintf(newDir, \"%s%s%s\", dir, separator, entryPtr->d_name);\n\t\t    result = DoGlob(interp, newDir, p+1);\n\t\t    if (newDir != static1) {\n\t\t\tfree(newDir);\n\t\t    }\n\t\t    if (result != TCL_OK) {\n\t\t\tbreak;\n\t\t    }\n\t\t}\n\t    }\n\t}\n\tclosedir(d);\n\tif (pattern != static2) {\n\t    free(pattern);\n\t}\n\treturn result;\n    }\n\n    /*\n     * This is the simplest case:  just another path element.  Move\n     * it to the dir side and recurse (or just add the name to the\n     * list, if we're at the end of the path).\n     */\n\n    if (*p == 0) {\n\tAppendResult(interp, dir, separator, rem, p-rem);\n    } else {\n\tint l1, l2;\n\tchar *newDir;\n\tchar static1[STATIC_SIZE];\n\n\tl1 = strlen(dir);\n\tl2 = l1 + (p - rem) + 2;\n\tif (l2 <= STATIC_SIZE) {\n\t    newDir = static1;\n\t} else {\n\t    newDir = (char *) malloc((unsigned) l2);\n\t}\n\tsprintf(newDir, \"%s%s%.*s\", dir, separator, (int) (p - rem), rem);\n\tresult = DoGlob(interp, newDir, p+1);\n\tif (newDir != static1) {\n\t    free(newDir);\n\t}\n\tif (result != TCL_OK) {\n\t    return TCL_ERROR;\n\t}\n    }\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_TildeSubst --\n *\n *\tGiven a name starting with a tilde, produce a name where\n *\tthe tilde and following characters have been replaced by\n *\tthe home directory location for the named user.\n *\n * Results:\n *\tThe result is a pointer to a static string containing\n *\tthe new name.  This name will only persist until the next\n *\tcall to Tcl_TildeSubst;  save it if you care about it for\n *\tthe long term.  If there was an error in processing the\n *\ttilde, then an error message is left in interp->result\n *\tand the return value is NULL.\n *\n * Side effects:\n *\tNone that the caller needs to worry about.\n *\n *----------------------------------------------------------------------\n */\n\nunsigned char *\nTcl_TildeSubst(interp, name)\n    Tcl_Interp *interp;\t\t/* Interpreter in which to store error\n\t\t\t\t * message (if necessary). */\n    unsigned char *name;\t/* File name, which may begin with \"~/\"\n\t\t\t\t * (to indicate current user's home directory)\n\t\t\t\t * or \"~<user>/\" (to indicate any user's\n\t\t\t\t * home directory). */\n{\n#define STATIC_BUF_SIZE 50\n    static char staticBuf[STATIC_BUF_SIZE];\n    static int curSize = STATIC_BUF_SIZE;\n    static char *curBuf = staticBuf;\n    char *dir;\n    int length;\n    int fromPw = 0;\n    register unsigned char *p;\n\n    if (name[0] != '~') {\n\treturn name;\n    }\n\n    /*\n     * First, find the directory name corresponding to the tilde entry.\n     */\n\n    if ((name[1] == '/') || (name[1] == '\\0')) {\n\tdir = getenv(\"HOME\");\n\tif (dir == NULL) {\n\t    Tcl_ResetResult(interp);\n\t    Tcl_AppendResult(interp, \"couldn't find HOME environment \",\n\t\t    \"variable to expand \\\"\", name, \"\\\"\", (char *) NULL);\n\t    return NULL;\n\t}\n\tp = name+1;\n    } else {\n\tstruct passwd *pwPtr;\n\n\tfor (p = &name[1]; (*p != 0) && (*p != '/'); p++) {\n\t    /* Null body;  just find end of name. */\n\t}\n\tlength = p - &name[1];\n\tif (length >= curSize) {\n\t    length = curSize-1;\n\t}\n\tmemcpy((void *) curBuf, (void *) (name+1), length);\n\tcurBuf[length] = '\\0';\n\tpwPtr = getpwnam(curBuf);\n\tif (pwPtr == NULL) {\n\t    endpwent();\n\t    Tcl_ResetResult(interp);\n\t    Tcl_AppendResult(interp, \"user \\\"\", curBuf,\n\t\t    \"\\\" doesn't exist\", (char *) NULL);\n\t    return NULL;\n\t}\n\tdir = pwPtr->pw_dir;\n\tfromPw = 1;\n    }\n\n    /*\n     * Grow the buffer if necessary to make enough space for the\n     * full file name.\n     */\n\n    length = strlen(dir) + strlen(p);\n    if (length >= curSize) {\n\tif (curBuf != staticBuf) {\n\t    free(curBuf);\n\t}\n\tcurSize = length + 1;\n\tcurBuf = (char *) malloc((unsigned) curSize);\n    }\n\n    /*\n     * Finally, concatenate the directory name with the remainder\n     * of the path in the buffer.\n     */\n\n    strcpy(curBuf, dir);\n    strcat(curBuf, p);\n    if (fromPw) {\n\tendpwent();\n    }\n    return curBuf;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_GlobCmd --\n *\n *\tThis procedure is invoked to process the \"glob\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_GlobCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int i, result, noComplain;\n\n    if (argc < 2) {\n\tnotEnoughArgs:\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" ?-nocomplain? name ?name ...?\\\"\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n    noComplain = 0;\n    if ((argv[1][0] == '-') && (strcmp(argv[1], \"-nocomplain\") == 0)) {\n\tif (argc < 3) {\n\t    goto notEnoughArgs;\n\t}\n\tnoComplain = 1;\n    }\n\n    for (i = 1 + noComplain; i < argc; i++) {\n\tchar *thisName;\n\n\t/*\n\t * Do special checks for names starting at the root and for\n\t * names beginning with ~.  Then let DoGlob do the rest.\n\t */\n\n\tthisName = argv[i];\n\tif (*thisName == '~') {\n\t    thisName = Tcl_TildeSubst(interp, thisName);\n\t    if (thisName == NULL) {\n\t\treturn TCL_ERROR;\n\t    }\n\t}\n\tif (*thisName == '/') {\n\t    result = DoGlob(interp, \"/\", thisName+1);\n\t} else {\n\t    result = DoGlob(interp, \"\", thisName);\n\t}\n\tif (result != TCL_OK) {\n\t    return result;\n\t}\n    }\n    if ((*interp->result == 0) && !noComplain) {\n\tchar *sep = \"\";\n\n\tTcl_AppendResult(interp, \"no files matched glob pattern\",\n\t\t(argc == 2) ? \" \\\"\" : \"s \\\"\", (char *) NULL);\n\tfor (i = 1; i < argc; i++) {\n\t    Tcl_AppendResult(interp, sep, argv[i], (char *) NULL);\n\t    sep = \" \";\n\t}\n\tTcl_AppendResult(interp, \"\\\"\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n    return TCL_OK;\n}\n"
  },
  {
    "path": "lib/libtcl/tclhash.c",
    "content": "/*\n * tclHash.c --\n *\n *\tImplementation of in-memory hash tables for Tcl and Tcl-based\n *\tapplications.\n *\n * Copyright 1991 Regents of the University of California\n * Permission to use, copy, modify, and distribute this\n * software and its documentation for any purpose and without\n * fee is hereby granted, provided that this copyright\n * notice appears in all copies.  The University of California\n * makes no representations about the suitability of this\n * software for any purpose.  It is provided \"as is\" without\n * express or implied warranty.\n */\n#include \"internal.h\"\n#include <assert.h>\n\n/*\n * When there are this many entries per bucket, on average, rebuild\n * the hash table to make it larger.\n */\n\n#define REBUILD_MULTIPLIER\t3\n\n\n/*\n * The following macro takes a preliminary integer hash value and\n * produces an index into a hash tables bucket list.  The idea is\n * to make it so that preliminary values that are arbitrarily similar\n * will end up in different buckets.  The hash function was taken\n * from a random-number generator.\n */\n\n#define RANDOM_INDEX(tablePtr, i) \\\n    (((((size_t) (i))*1103515245) >> (tablePtr)->downShift) & (tablePtr)->mask)\n\n/*\n * Procedure prototypes for static procedures in this file:\n */\n\nstatic Tcl_HashEntry *\tArrayFind (Tcl_HashTable *tablePtr, unsigned char *key);\nstatic Tcl_HashEntry *\tArrayCreate (Tcl_HashTable *tablePtr, unsigned char *key,\n\t\t\t\tint *newPtr);\nstatic Tcl_HashEntry *\tBogusFind (Tcl_HashTable *tablePtr, unsigned char *key);\nstatic Tcl_HashEntry *\tBogusCreate (Tcl_HashTable *tablePtr, unsigned char *key,\n\t\t\t\tint *newPtr);\nstatic unsigned int\tHashString (unsigned char *string);\nstatic void\t\tRebuildTable (Tcl_HashTable *tablePtr);\nstatic Tcl_HashEntry *\tStringFind (Tcl_HashTable *tablePtr, unsigned char *key);\nstatic Tcl_HashEntry *\tStringCreate (Tcl_HashTable *tablePtr, unsigned char *key,\n\t\t\t\tint *newPtr);\nstatic Tcl_HashEntry *\tOneWordFind (Tcl_HashTable *tablePtr, unsigned char *key);\nstatic Tcl_HashEntry *\tOneWordCreate (Tcl_HashTable *tablePtr, unsigned char *key,\n\t\t\t\tint *newPtr);\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_InitHashTable --\n *\n *\tGiven storage for a hash table, set up the fields to prepare\n *\tthe hash table for use.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tTablePtr is now ready to be passed to Tcl_FindHashEntry and\n *\tTcl_CreateHashEntry.\n *\n *----------------------------------------------------------------------\n */\n\nvoid\nTcl_InitHashTable(Tcl_HashTable *tablePtr, /* Pointer to table record, which\n\t\t\t\t\t * is supplied by the caller. */\n\tint keyType)\t\t\t/* Type of keys to use in table:\n\t\t\t\t\t * TCL_STRING_KEYS, TCL_ONE_WORD_KEYS,\n\t\t\t\t\t * or an integer >= 2. */\n{\n    tablePtr->buckets = tablePtr->staticBuckets;\n    tablePtr->staticBuckets[0] = tablePtr->staticBuckets[1] = 0;\n    tablePtr->staticBuckets[2] = tablePtr->staticBuckets[3] = 0;\n    tablePtr->numBuckets = TCL_SMALL_HASH_TABLE;\n    tablePtr->numEntries = 0;\n    tablePtr->rebuildSize = TCL_SMALL_HASH_TABLE*REBUILD_MULTIPLIER;\n    tablePtr->downShift = 28;\n    tablePtr->mask = 3;\n    tablePtr->keyType = keyType;\n    if (keyType == TCL_STRING_KEYS) {\n\ttablePtr->findProc = StringFind;\n\ttablePtr->createProc = StringCreate;\n    } else if (keyType == TCL_ONE_WORD_KEYS) {\n\ttablePtr->findProc = OneWordFind;\n\ttablePtr->createProc = OneWordCreate;\n    } else {\n\ttablePtr->findProc = ArrayFind;\n\ttablePtr->createProc = ArrayCreate;\n    };\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_DeleteHashEntry --\n *\n *\tRemove a single entry from a hash table.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tThe entry given by entryPtr is deleted from its table and\n *\tshould never again be used by the caller.  It is up to the\n *\tcaller to free the clientData field of the entry, if that\n *\tis relevant.\n *\n *----------------------------------------------------------------------\n */\n\nvoid\nTcl_DeleteHashEntry(entryPtr)\n    Tcl_HashEntry *entryPtr;\n{\n    register Tcl_HashEntry *prevPtr;\n\n    if (*entryPtr->bucketPtr == entryPtr) {\n\t*entryPtr->bucketPtr = entryPtr->nextPtr;\n    } else {\n\tfor (prevPtr = *entryPtr->bucketPtr; ; prevPtr = prevPtr->nextPtr) {\n\t    assert (prevPtr != 0);\n\t    if (prevPtr->nextPtr == entryPtr) {\n\t\tprevPtr->nextPtr = entryPtr->nextPtr;\n\t\tbreak;\n\t    }\n\t}\n    }\n    entryPtr->tablePtr->numEntries--;\n    free (entryPtr);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_DeleteHashTable --\n *\n *\tFree up everything associated with a hash table except for\n *\tthe record for the table itself.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tThe hash table is no longer useable.\n *\n *----------------------------------------------------------------------\n */\n\nvoid\nTcl_DeleteHashTable(tablePtr)\n    register Tcl_HashTable *tablePtr;\t\t/* Table to delete. */\n{\n    register Tcl_HashEntry *hPtr, *nextPtr;\n    int i;\n\n    /*\n     * Free up all the entries in the table.\n     */\n    for (i = 0; i < tablePtr->numBuckets; i++) {\n\thPtr = tablePtr->buckets[i];\n\twhile (hPtr != 0) {\n\t    nextPtr = hPtr->nextPtr;\n\t    free (hPtr);\n\t    hPtr = nextPtr;\n\t}\n    }\n\n    /*\n     * Free up the bucket array, if it was dynamically allocated.\n     */\n    if (tablePtr->buckets != tablePtr->staticBuckets) {\n\tfree (tablePtr->buckets);\n    }\n\n    /*\n     * Arrange for panics if the table is used again without\n     * re-initialization.\n     */\n    tablePtr->findProc = BogusFind;\n    tablePtr->createProc = BogusCreate;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_FirstHashEntry --\n *\n *\tLocate the first entry in a hash table and set up a record\n *\tthat can be used to step through all the remaining entries\n *\tof the table.\n *\n * Results:\n *\tThe return value is a pointer to the first entry in tablePtr,\n *\tor NULL if tablePtr has no entries in it.  The memory at\n *\t*searchPtr is initialized so that subsequent calls to\n *\tTcl_NextHashEntry will return all of the entries in the table,\n *\tone at a time.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nTcl_HashEntry *\nTcl_FirstHashEntry(tablePtr, searchPtr)\n    Tcl_HashTable *tablePtr;\t\t/* Table to search. */\n    Tcl_HashSearch *searchPtr;\t\t/* Place to store information about\n\t\t\t\t\t * progress through the table. */\n{\n    searchPtr->tablePtr = tablePtr;\n    searchPtr->nextIndex = 0;\n    searchPtr->nextEntryPtr = 0;\n    return Tcl_NextHashEntry(searchPtr);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_NextHashEntry --\n *\n *\tOnce a hash table enumeration has been initiated by calling\n *\tTcl_FirstHashEntry, this procedure may be called to return\n *\tsuccessive elements of the table.\n *\n * Results:\n *\tThe return value is the next entry in the hash table being\n *\tenumerated, or NULL if the end of the table is reached.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nTcl_HashEntry *\nTcl_NextHashEntry(searchPtr)\n    register Tcl_HashSearch *searchPtr;\t/* Place to store information about\n\t\t\t\t\t * progress through the table.  Must\n\t\t\t\t\t * have been initialized by calling\n\t\t\t\t\t * Tcl_FirstHashEntry. */\n{\n    Tcl_HashEntry *hPtr;\n\n    while (searchPtr->nextEntryPtr == 0) {\n\tif (searchPtr->nextIndex >= searchPtr->tablePtr->numBuckets) {\n\t    return 0;\n\t}\n\tsearchPtr->nextEntryPtr =\n\t\tsearchPtr->tablePtr->buckets[searchPtr->nextIndex];\n\tsearchPtr->nextIndex++;\n    }\n    hPtr = searchPtr->nextEntryPtr;\n    searchPtr->nextEntryPtr = hPtr->nextPtr;\n    return hPtr;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_HashStats --\n *\n *\tReturn statistics describing the layout of the hash table\n *\tin its hash buckets.\n *\n * Results:\n *\tThe return value is a malloc-ed string containing information\n *\tabout tablePtr.  It is the caller's responsibility to free\n *\tthis string.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nunsigned char *\nTcl_HashStats (Tcl_HashTable *tablePtr)\t/* Table for which to produce stats. */\n{\n#define NUM_COUNTERS 10\n    int count[NUM_COUNTERS], overflow, i, j, size;\n/*    double average, tmp;*/\n    register Tcl_HashEntry *hPtr;\n    unsigned char *result, *p;\n\n    /*\n     * Compute a histogram of bucket usage.\n     */\n\n    memset (count, 0, sizeof (count));\n    overflow = 0;\n/*    average = 0.0;*/\n    for (i = 0; i < tablePtr->numBuckets; i++) {\n\tj = 0;\n\tfor (hPtr = tablePtr->buckets[i]; hPtr != 0; hPtr = hPtr->nextPtr) {\n\t    j++;\n\t}\n\tif (j < NUM_COUNTERS) {\n\t    count[j]++;\n\t} else {\n\t    overflow++;\n\t}\n/*\ttmp = j;*/\n/*\taverage += (tmp+1.0)*(tmp/tablePtr->numEntries)/2.0;*/\n    }\n\n    /*\n     * Print out the histogram and a few other pieces of information.\n     */\n    size = NUM_COUNTERS*60 + 300;\n    result = malloc (size);\n    sprintf(result, \"%d entries in table, %d buckets\\n\",\n\t    tablePtr->numEntries, tablePtr->numBuckets);\n    p = result + strlen(result);\n    for (i = 0; i < NUM_COUNTERS; i++) {\n\tsprintf(p, \"number of buckets with %d entries: %d\\n\", i, count[i]);\n\tp += strlen(p);\n    }\n    sprintf(p, \"number of buckets with more %d or more entries: %d\",\n\tNUM_COUNTERS, overflow);\n/*    p += strlen(p);*/\n/*    sprintf(p, \"\\naverage search distance for entry: %.1f\", average);*/\n    return result;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * HashString --\n *\n *\tCompute a one-word summary of a text string, which can be\n *\tused to generate a hash index.\n *\n * Results:\n *\tThe return value is a one-word summary of the information in\n *\tstring.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nstatic unsigned int\nHashString(string)\n    register unsigned char *string;\t/* String from which to compute hash value. */\n{\n    register unsigned int result;\n    register int c;\n\n    /*\n     * I tried a zillion different hash functions and asked many other\n     * people for advice.  Many people had their own favorite functions,\n     * all different, but no-one had much idea why they were good ones.\n     * I chose the one below (multiply by 9 and add new character)\n     * because of the following reasons:\n     *\n     * 1. Multiplying by 10 is perfect for keys that are decimal strings,\n     *    and multiplying by 9 is just about as good.\n     * 2. Times-9 is (shift-left-3) plus (old).  This means that each\n     *    character's bits hang around in the low-order bits of the\n     *    hash value for ever, plus they spread fairly rapidly up to\n     *    the high-order bits to fill out the hash value.  This seems\n     *    works well both for decimal and non-decimal strings.\n     */\n\n    result = 0;\n    while (1) {\n\tc = *string;\n\tstring++;\n\tif (c == 0) {\n\t    break;\n\t}\n\tresult += (result<<3) + c;\n    }\n    return result;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * StringFind --\n *\n *\tGiven a hash table with string keys, and a string key, find\n *\tthe entry with a matching key.\n *\n * Results:\n *\tThe return value is a token for the matching entry in the\n *\thash table, or NULL if there was no matching entry.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nstatic Tcl_HashEntry *\nStringFind(tablePtr, key)\n    Tcl_HashTable *tablePtr;\t/* Table in which to lookup entry. */\n    unsigned char *key;\t\t/* Key to use to find matching entry. */\n{\n    register Tcl_HashEntry *hPtr;\n    register unsigned char *p1, *p2;\n    int index;\n\n    index = HashString(key) & tablePtr->mask;\n\n    /*\n     * Search all of the entries in the appropriate bucket.\n     */\n\n    for (hPtr = tablePtr->buckets[index]; hPtr != 0;\n\t    hPtr = hPtr->nextPtr) {\n\tfor (p1 = key, p2 = hPtr->key.string; ; p1++, p2++) {\n\t    if (*p1 != *p2) {\n\t\tbreak;\n\t    }\n\t    if (*p1 == '\\0') {\n\t\treturn hPtr;\n\t    }\n\t}\n    }\n    return 0;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * StringCreate --\n *\n *\tGiven a hash table with string keys, and a string key, find\n *\tthe entry with a matching key.  If there is no matching entry,\n *\tthen create a new entry that does match.\n *\n * Results:\n *\tThe return value is a pointer to the matching entry.  If this\n *\tis a newly-created entry, then *newPtr will be set to a non-zero\n *\tvalue;  otherwise *newPtr will be set to 0.  If this is a new\n *\tentry the value stored in the entry will initially be 0.\n *\n * Side effects:\n *\tA new entry may be added to the hash table.\n *\n *----------------------------------------------------------------------\n */\n\nstatic Tcl_HashEntry *\nStringCreate(tablePtr, key, newPtr)\n    Tcl_HashTable *tablePtr;\t/* Table in which to lookup entry. */\n    unsigned char *key;\t\t/* Key to use to find or create matching\n\t\t\t\t * entry. */\n    int *newPtr;\t\t/* Store info here telling whether a new\n\t\t\t\t * entry was created. */\n{\n    register Tcl_HashEntry *hPtr;\n    register unsigned char *p1, *p2;\n    int index;\n\n    index = HashString(key) & tablePtr->mask;\n\n    /*\n     * Search all of the entries in this bucket.\n     */\n\n    for (hPtr = tablePtr->buckets[index]; hPtr != 0;\n\t    hPtr = hPtr->nextPtr) {\n\tfor (p1 = key, p2 = hPtr->key.string; ; p1++, p2++) {\n\t    if (*p1 != *p2) {\n\t\tbreak;\n\t    }\n\t    if (*p1 == '\\0') {\n\t\t*newPtr = 0;\n\t\treturn hPtr;\n\t    }\n\t}\n    }\n\n    /*\n     * Entry not found.  Add a new one to the bucket.\n     */\n\n    *newPtr = 1;\n    hPtr = (Tcl_HashEntry*) malloc ((unsigned)\n\t    (sizeof(Tcl_HashEntry) + strlen(key) - (sizeof(hPtr->key) -1)));\n    hPtr->tablePtr = tablePtr;\n    hPtr->bucketPtr = &(tablePtr->buckets[index]);\n    hPtr->nextPtr = *hPtr->bucketPtr;\n    hPtr->clientData = 0;\n    strcpy(hPtr->key.string, key);\n    *hPtr->bucketPtr = hPtr;\n    tablePtr->numEntries++;\n\n    /*\n     * If the table has exceeded a decent size, rebuild it with many\n     * more buckets.\n     */\n\n    if (tablePtr->numEntries >= tablePtr->rebuildSize) {\n\tRebuildTable(tablePtr);\n    }\n    return hPtr;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * OneWordFind --\n *\n *\tGiven a hash table with one-word keys, and a one-word key, find\n *\tthe entry with a matching key.\n *\n * Results:\n *\tThe return value is a token for the matching entry in the\n *\thash table, or NULL if there was no matching entry.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nstatic Tcl_HashEntry *\nOneWordFind(tablePtr, key)\n    Tcl_HashTable *tablePtr;\t\t/* Table in which to lookup entry. */\n    register unsigned char *key;\t/* Key to use to find matching entry. */\n{\n    register Tcl_HashEntry *hPtr;\n    int index;\n\n    index = RANDOM_INDEX(tablePtr, key);\n\n    /*\n     * Search all of the entries in the appropriate bucket.\n     */\n\n    for (hPtr = tablePtr->buckets[index]; hPtr != 0;\n\t    hPtr = hPtr->nextPtr) {\n\tif (hPtr->key.oneWordValue == key) {\n\t    return hPtr;\n\t}\n    }\n    return 0;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * OneWordCreate --\n *\n *\tGiven a hash table with one-word keys, and a one-word key, find\n *\tthe entry with a matching key.  If there is no matching entry,\n *\tthen create a new entry that does match.\n *\n * Results:\n *\tThe return value is a pointer to the matching entry.  If this\n *\tis a newly-created entry, then *newPtr will be set to a non-zero\n *\tvalue;  otherwise *newPtr will be set to 0.  If this is a new\n *\tentry the value stored in the entry will initially be 0.\n *\n * Side effects:\n *\tA new entry may be added to the hash table.\n *\n *----------------------------------------------------------------------\n */\n\nstatic Tcl_HashEntry *\nOneWordCreate(tablePtr, key, newPtr)\n    Tcl_HashTable *tablePtr;\t/* Table in which to lookup entry. */\n    register unsigned char *key; /* Key to use to find or create matching\n\t\t\t\t * entry. */\n    int *newPtr;\t\t/* Store info here telling whether a new\n\t\t\t\t * entry was created. */\n{\n    register Tcl_HashEntry *hPtr;\n    int index;\n\n    index = RANDOM_INDEX(tablePtr, key);\n\n    /*\n     * Search all of the entries in this bucket.\n     */\n\n    for (hPtr = tablePtr->buckets[index]; hPtr != 0;\n\t    hPtr = hPtr->nextPtr) {\n\tif (hPtr->key.oneWordValue == key) {\n\t    *newPtr = 0;\n\t    return hPtr;\n\t}\n    }\n\n    /*\n     * Entry not found.  Add a new one to the bucket.\n     */\n\n    *newPtr = 1;\n    hPtr = (Tcl_HashEntry*) malloc (sizeof(Tcl_HashEntry));\n    hPtr->tablePtr = tablePtr;\n    hPtr->bucketPtr = &(tablePtr->buckets[index]);\n    hPtr->nextPtr = *hPtr->bucketPtr;\n    hPtr->clientData = 0;\n    hPtr->key.oneWordValue = key;\n    *hPtr->bucketPtr = hPtr;\n    tablePtr->numEntries++;\n\n    /*\n     * If the table has exceeded a decent size, rebuild it with many\n     * more buckets.\n     */\n\n    if (tablePtr->numEntries >= tablePtr->rebuildSize) {\n\tRebuildTable(tablePtr);\n    }\n    return hPtr;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * ArrayFind --\n *\n *\tGiven a hash table with array-of-int keys, and a key, find\n *\tthe entry with a matching key.\n *\n * Results:\n *\tThe return value is a token for the matching entry in the\n *\thash table, or NULL if there was no matching entry.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nstatic Tcl_HashEntry *\nArrayFind(tablePtr, key)\n    Tcl_HashTable *tablePtr;\t/* Table in which to lookup entry. */\n    unsigned char *key;\t\t/* Key to use to find matching entry. */\n{\n    register Tcl_HashEntry *hPtr;\n    int *arrayPtr = (int *) key;\n    register int *iPtr1, *iPtr2;\n    int index, count;\n\n    for (index = 0, count = tablePtr->keyType, iPtr1 = arrayPtr;\n\t    count > 0; count--, iPtr1++) {\n\tindex += *iPtr1;\n    }\n    index = RANDOM_INDEX(tablePtr, index);\n\n    /*\n     * Search all of the entries in the appropriate bucket.\n     */\n\n    for (hPtr = tablePtr->buckets[index]; hPtr != 0;\n\t    hPtr = hPtr->nextPtr) {\n\tfor (iPtr1 = arrayPtr, iPtr2 = hPtr->key.words,\n\t\tcount = tablePtr->keyType; ; count--, iPtr1++, iPtr2++) {\n\t    if (count == 0) {\n\t\treturn hPtr;\n\t    }\n\t    if (*iPtr1 != *iPtr2) {\n\t\tbreak;\n\t    }\n\t}\n    }\n    return 0;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * ArrayCreate --\n *\n *\tGiven a hash table with one-word keys, and a one-word key, find\n *\tthe entry with a matching key.  If there is no matching entry,\n *\tthen create a new entry that does match.\n *\n * Results:\n *\tThe return value is a pointer to the matching entry.  If this\n *\tis a newly-created entry, then *newPtr will be set to a non-zero\n *\tvalue;  otherwise *newPtr will be set to 0.  If this is a new\n *\tentry the value stored in the entry will initially be 0.\n *\n * Side effects:\n *\tA new entry may be added to the hash table.\n *\n *----------------------------------------------------------------------\n */\n\nstatic Tcl_HashEntry *\nArrayCreate(tablePtr, key, newPtr)\n    Tcl_HashTable *tablePtr;\t/* Table in which to lookup entry. */\n    register unsigned char *key; /* Key to use to find or create matching\n\t\t\t\t * entry. */\n    int *newPtr;\t\t/* Store info here telling whether a new\n\t\t\t\t * entry was created. */\n{\n    register Tcl_HashEntry *hPtr;\n    int *arrayPtr = (int *) key;\n    register int *iPtr1, *iPtr2;\n    int index, count;\n\n    for (index = 0, count = tablePtr->keyType, iPtr1 = arrayPtr;\n\t    count > 0; count--, iPtr1++) {\n\tindex += *iPtr1;\n    }\n    index = RANDOM_INDEX(tablePtr, index);\n\n    /*\n     * Search all of the entries in the appropriate bucket.\n     */\n\n    for (hPtr = tablePtr->buckets[index]; hPtr != 0;\n\t    hPtr = hPtr->nextPtr) {\n\tfor (iPtr1 = arrayPtr, iPtr2 = hPtr->key.words,\n\t\tcount = tablePtr->keyType; ; count--, iPtr1++, iPtr2++) {\n\t    if (count == 0) {\n\t\t*newPtr = 0;\n\t\treturn hPtr;\n\t    }\n\t    if (*iPtr1 != *iPtr2) {\n\t\tbreak;\n\t    }\n\t}\n    }\n\n    /*\n     * Entry not found.  Add a new one to the bucket.\n     */\n\n    *newPtr = 1;\n    hPtr = (Tcl_HashEntry*) malloc ((unsigned)\n\t(sizeof(Tcl_HashEntry) + (tablePtr->keyType*sizeof(int)) - 4));\n    hPtr->tablePtr = tablePtr;\n    hPtr->bucketPtr = &(tablePtr->buckets[index]);\n    hPtr->nextPtr = *hPtr->bucketPtr;\n    hPtr->clientData = 0;\n    for (iPtr1 = arrayPtr, iPtr2 = hPtr->key.words, count = tablePtr->keyType;\n\t    count > 0; count--, iPtr1++, iPtr2++) {\n\t*iPtr2 = *iPtr1;\n    }\n    *hPtr->bucketPtr = hPtr;\n    tablePtr->numEntries++;\n\n    /*\n     * If the table has exceeded a decent size, rebuild it with many\n     * more buckets.\n     */\n\n    if (tablePtr->numEntries >= tablePtr->rebuildSize) {\n\tRebuildTable(tablePtr);\n    }\n    return hPtr;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * BogusFind --\n *\n *\tThis procedure is invoked when an Tcl_FindHashEntry is called\n *\ton a table that has been deleted.\n *\n * Results:\n *\tIf panic returns (which it shouldn't) this procedure returns\n *\tNULL.\n *\n * Side effects:\n *\tGenerates a panic.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nstatic Tcl_HashEntry *\nBogusFind(tablePtr, key)\n    Tcl_HashTable *tablePtr;\t/* Table in which to lookup entry. */\n    unsigned char *key;\t\t/* Key to use to find matching entry. */\n{\n    assert (0);\n    return 0;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * BogusCreate --\n *\n *\tThis procedure is invoked when an Tcl_CreateHashEntry is called\n *\ton a table that has been deleted.\n *\n * Results:\n *\tIf panic returns (which it shouldn't) this procedure returns\n *\tNULL.\n *\n * Side effects:\n *\tGenerates a panic.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nstatic Tcl_HashEntry *\nBogusCreate(tablePtr, key, newPtr)\n    Tcl_HashTable *tablePtr;\t/* Table in which to lookup entry. */\n    unsigned char *key;\t\t/* Key to use to find or create matching\n\t\t\t\t * entry. */\n    int *newPtr;\t\t/* Store info here telling whether a new\n\t\t\t\t * entry was created. */\n{\n    assert (0);\n    return 0;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * RebuildTable --\n *\n *\tThis procedure is invoked when the ratio of entries to hash\n *\tbuckets becomes too large.  It creates a new table with a\n *\tlarger bucket array and moves all of the entries into the\n *\tnew table.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tMemory gets reallocated and entries get re-hashed to new\n *\tbuckets.\n *\n *----------------------------------------------------------------------\n */\n\nstatic void\nRebuildTable(tablePtr)\n    register Tcl_HashTable *tablePtr;\t/* Table to enlarge. */\n{\n    int oldSize, count, index;\n    Tcl_HashEntry **oldBuckets;\n    register Tcl_HashEntry **oldChainPtr, **newChainPtr;\n    register Tcl_HashEntry *hPtr;\n\n    oldSize = tablePtr->numBuckets;\n    oldBuckets = tablePtr->buckets;\n\n    /*\n     * Allocate and initialize the new bucket array, and set up\n     * hashing constants for new array size.\n     */\n\n    tablePtr->numBuckets *= 4;\n    tablePtr->buckets = (Tcl_HashEntry**) malloc ((unsigned)\n            (tablePtr->numBuckets * sizeof(Tcl_HashEntry *)));\n    for (count = tablePtr->numBuckets, newChainPtr = tablePtr->buckets;\n\t    count > 0; count--, newChainPtr++) {\n\t*newChainPtr = 0;\n    }\n    tablePtr->rebuildSize *= 4;\n    tablePtr->downShift -= 2;\n    tablePtr->mask = (tablePtr->mask << 2) + 3;\n\n    /*\n     * Rehash all of the existing entries into the new bucket array.\n     */\n\n    for (oldChainPtr = oldBuckets; oldSize > 0; oldSize--, oldChainPtr++) {\n\tfor (hPtr = *oldChainPtr; hPtr != 0; hPtr = *oldChainPtr) {\n\t    *oldChainPtr = hPtr->nextPtr;\n\t    if (tablePtr->keyType == TCL_STRING_KEYS) {\n\t\tindex = HashString(hPtr->key.string) & tablePtr->mask;\n\t    } else if (tablePtr->keyType == TCL_ONE_WORD_KEYS) {\n\t\tindex = RANDOM_INDEX(tablePtr, hPtr->key.oneWordValue);\n\t    } else {\n\t\tregister int *iPtr;\n\t\tint count;\n\n\t\tfor (index = 0, count = tablePtr->keyType,\n\t\t\tiPtr = hPtr->key.words; count > 0; count--, iPtr++) {\n\t\t    index += *iPtr;\n\t\t}\n\t\tindex = RANDOM_INDEX(tablePtr, index);\n\t    }\n\t    hPtr->bucketPtr = &(tablePtr->buckets[index]);\n\t    hPtr->nextPtr = *hPtr->bucketPtr;\n\t    *hPtr->bucketPtr = hPtr;\n\t}\n    }\n\n    /*\n     * Free up the old bucket array, if it was dynamically allocated.\n     */\n\n    if (oldBuckets != tablePtr->staticBuckets) {\n\tfree (oldBuckets);\n    }\n}\n"
  },
  {
    "path": "lib/libtcl/tclparse.c",
    "content": "/*\n * tclParse.c --\n *\n *\tThis file contains a collection of procedures that are used\n *\tto parse Tcl commands or parts of commands (like quoted\n *\tstrings or nested sub-commands).\n *\n * Copyright 1991 Regents of the University of California.\n * Permission to use, copy, modify, and distribute this\n * software and its documentation for any purpose and without\n * fee is hereby granted, provided that the above copyright\n * notice appear in all copies.  The University of California\n * makes no representations about the suitability of this\n * software for any purpose.  It is provided \"as is\" without\n * express or implied warranty.\n */\n#include \"internal.h\"\n\n/*\n * A table used to classify input characters to assist in parsing\n * Tcl commands.  The table should be indexed with a signed character\n * using the CHAR_TYPE macro.  The character may have a negative\n * value.\n */\n#define CHAR_TYPE(c) tclTypeTable [(unsigned char)(c)]\n\n/*\n * The following table assigns a type to each character.  Only types\n * meaningful to Tcl parsing are represented here.  The table indexes\n * all 256 characters, with the negative ones first, then the positive\n * ones.\n */\nstatic const char tclTypeTable[] = {\n/*0*/\n    TCL_COMMAND_END,   TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_SPACE,         TCL_COMMAND_END,   TCL_SPACE,\n    TCL_SPACE,         TCL_SPACE,         TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n/*32*/\n    TCL_SPACE,         TCL_NORMAL,        TCL_QUOTE,         TCL_NORMAL,\n    TCL_DOLLAR,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_COMMAND_END,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n/*64*/\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_OPEN_BRACKET,\n    TCL_BACKSLASH,     TCL_COMMAND_END,   TCL_NORMAL,        TCL_NORMAL,\n/*96*/\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_OPEN_BRACE,\n    TCL_NORMAL,        TCL_CLOSE_BRACE,   TCL_NORMAL,        TCL_NORMAL,\n/*-128*/\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n/*-96*/\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n/*-64*/\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n/*-32*/\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n    TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,        TCL_NORMAL,\n};\n\n/*\n * Function prototypes for procedures local to this file:\n */\n\nstatic unsigned char *\tQuoteEnd (unsigned char *string, int term);\nstatic unsigned char *\tVarNameEnd (unsigned char *string);\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_Backslash --\n *\n *\tFigure out how to handle a backslash sequence.\n *\n * Results:\n *\tThe return value is the character that should be substituted\n *\tin place of the backslash sequence that starts at src, or 0\n *\tif the backslash sequence should be replace by nothing (e.g.\n *\tbackslash followed by newline).  If readPtr isn't NULL then\n *\tit is filled in with a count of the number of characters in\n *\tthe backslash sequence.  Note:  if the backslash isn't followed\n *\tby characters that are understood here, then the backslash\n *\tsequence is only considered to be one character long, and it\n *\tis replaced by a backslash char.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nchar\nTcl_Backslash(src, readPtr)\n    unsigned char *src;\t\t/* Points to the backslash character of\n\t\t\t\t * a backslash sequence. */\n    int *readPtr;\t\t/* Fill in with number of characters read\n\t\t\t\t * from src, unless NULL. */\n{\n    register unsigned char *p = src+1;\n    char result;\n    int count;\n\n    count = 2;\n\n    switch (*p) {\n\tcase 'b':\n\t    result = '\\b';\n\t    break;\n\tcase 'e':\n\t    result = 033;\n\t    break;\n\tcase 'f':\n\t    result = '\\f';\n\t    break;\n\tcase 'n':\n\t    result = '\\n';\n\t    break;\n\tcase 'r':\n\t    result = '\\r';\n\t    break;\n\tcase 't':\n\t    result = '\\t';\n\t    break;\n\tcase 'v':\n\t    result = '\\v';\n\t    break;\n\tcase 'C':\n\t    p++;\n\t    if (isspace(*p) || (*p == 0)) {\n\t\tresult = 'C';\n\t\tcount = 1;\n\t\tbreak;\n\t    }\n\t    count = 3;\n\t    if (*p == 'M') {\n\t\tp++;\n\t\tif (isspace(*p) || (*p == 0)) {\n\t\t    result = 'M' & 037;\n\t\t    break;\n\t\t}\n\t\tcount = 4;\n\t\tresult = (*p & 037) | '\\200';\n\t\tbreak;\n\t    }\n\t    count = 3;\n\t    result = *p & 037;\n\t    break;\n\tcase 'M':\n\t    p++;\n\t    if (isspace(*p) || (*p == 0)) {\n\t\tresult = 'M';\n\t\tcount = 1;\n\t\tbreak;\n\t    }\n\t    count = 3;\n\t    result = *p + '\\200';\n\t    break;\n\tcase '}':\n\tcase '{':\n\tcase ']':\n\tcase '[':\n\tcase '$':\n\tcase ' ':\n\tcase ';':\n\tcase '\"':\n\tcase '\\\\':\n\t    result = *p;\n\t    break;\n\tcase '\\n':\n\t    result = 0;\n\t    break;\n\tdefault:\n\t    if (isdigit(*p)) {\n\t\tresult = *p - '0';\n\t\tp++;\n\t\tif (!isdigit(*p)) {\n\t\t    break;\n\t\t}\n\t\tcount = 3;\n\t\tresult = (result << 3) + (*p - '0');\n\t\tp++;\n\t\tif (!isdigit(*p)) {\n\t\t    break;\n\t\t}\n\t\tcount = 4;\n\t\tresult = (result << 3) + (*p - '0');\n\t\tbreak;\n\t    }\n\t    result = '\\\\';\n\t    count = 1;\n\t    break;\n    }\n\n    if (readPtr != 0) {\n\t*readPtr = count;\n    }\n    return result;\n}\n\f\n/*\n *--------------------------------------------------------------\n *\n * TclParseQuotes --\n *\n *\tThis procedure parses a double-quoted string such as a\n *\tquoted Tcl command argument or a quoted value in a Tcl\n *\texpression.  This procedure is also used to parse array\n *\telement names within parentheses, or anything else that\n *\tneeds all the substitutions that happen in quotes.\n *\n * Results:\n *\tThe return value is a standard Tcl result, which is\n *\tTCL_OK unless there was an error while parsing the\n *\tquoted string.  If an error occurs then interp->result\n *\tcontains a standard error message.  *TermPtr is filled\n *\tin with the address of the character just after the\n *\tlast one successfully processed;  this is usually the\n *\tcharacter just after the matching close-quote.  The\n *\tfully-substituted contents of the quotes are stored in\n *\tstandard fashion in *pvPtr, null-terminated with\n *\tpvPtr->next pointing to the terminating null character.\n *\n * Side effects:\n *\tThe buffer space in pvPtr may be enlarged by calling its\n *\texpandProc.\n *\n *--------------------------------------------------------------\n */\n\nint\nTclParseQuotes(interp, string, termChar, flags, termPtr, pvPtr)\n    Tcl_Interp *interp;\t\t/* Interpreter to use for nested command\n\t\t\t\t * evaluations and error messages. */\n    unsigned char *string;\t/* Character just after opening double-\n\t\t\t\t * quote. */\n    int termChar;\t\t/* Character that terminates \"quoted\" string\n\t\t\t\t * (usually double-quote, but sometimes\n\t\t\t\t * right-paren or something else). */\n    int flags;\t\t\t/* Flags to pass to nested Tcl_Eval calls. */\n    unsigned char **termPtr;\t/* Store address of terminating character\n\t\t\t\t * here. */\n    ParseValue *pvPtr;\t\t/* Information about where to place\n\t\t\t\t * fully-substituted result of parse. */\n{\n    register unsigned char *src, *dst, c;\n\n    src = string;\n    dst = pvPtr->next;\n\n    while (1) {\n\tif (dst == pvPtr->end) {\n\t    /*\n\t     * Target buffer space is about to run out.  Make more space.\n\t     */\n\n\t    pvPtr->next = dst;\n\t    (*pvPtr->expandProc) (pvPtr, 1);\n\t    dst = pvPtr->next;\n\t}\n\n\tc = *src;\n\tsrc++;\n\tif (c == termChar) {\n\t    *dst = '\\0';\n\t    pvPtr->next = dst;\n\t    *termPtr = src;\n\t    return TCL_OK;\n\t} else if (CHAR_TYPE(c) == TCL_NORMAL) {\n\t    copy:\n\t    *dst = c;\n\t    dst++;\n\t    continue;\n\t} else if (c == '$') {\n\t    int length;\n\t    unsigned char *value;\n\n\t    value = Tcl_ParseVar(interp, src-1, termPtr);\n\t    if (value == 0) {\n\t\treturn TCL_ERROR;\n\t    }\n\t    src = *termPtr;\n\t    length = strlen(value);\n\t    if ((pvPtr->end - dst) <= length) {\n\t\tpvPtr->next = dst;\n\t\t(*pvPtr->expandProc) (pvPtr, length);\n\t\tdst = pvPtr->next;\n\t    }\n\t    strcpy(dst, value);\n\t    dst += length;\n\t    continue;\n\t} else if (c == '[') {\n\t    int result;\n\n\t    pvPtr->next = dst;\n\t    result = TclParseNestedCmd(interp, src, flags, termPtr, pvPtr);\n\t    if (result != TCL_OK) {\n\t\treturn result;\n\t    }\n\t    src = *termPtr;\n\t    dst = pvPtr->next;\n\t    continue;\n\t} else if (c == '\\\\') {\n\t    int numRead;\n\n\t    src--;\n\t    *dst = Tcl_Backslash(src, &numRead);\n\t    if (*dst != 0) {\n\t\tdst++;\n\t    }\n\t    src += numRead;\n\t    continue;\n\t} else if (c == '\\0') {\n\t    Tcl_ResetResult(interp);\n\t    sprintf(interp->result, \"missing %c\", termChar);\n\t    *termPtr = string-1;\n\t    return TCL_ERROR;\n\t} else {\n\t    goto copy;\n\t}\n    }\n}\n\f\n/*\n *--------------------------------------------------------------\n *\n * TclParseNestedCmd --\n *\n *\tThis procedure parses a nested Tcl command between\n *\tbrackets, returning the result of the command.\n *\n * Results:\n *\tThe return value is a standard Tcl result, which is\n *\tTCL_OK unless there was an error while executing the\n *\tnested command.  If an error occurs then interp->result\n *\tcontains a standard error message.  *TermPtr is filled\n *\tin with the address of the character just after the\n *\tlast one processed;  this is usually the character just\n *\tafter the matching close-bracket, or the null character\n *\tat the end of the string if the close-bracket was missing\n *\t(a missing close bracket is an error).  The result returned\n *\tby the command is stored in standard fashion in *pvPtr,\n *\tnull-terminated, with pvPtr->next pointing to the null\n *\tcharacter.\n *\n * Side effects:\n *\tThe storage space at *pvPtr may be expanded.\n *\n *--------------------------------------------------------------\n */\n\nint\nTclParseNestedCmd(interp, string, flags, termPtr, pvPtr)\n    Tcl_Interp *interp;\t\t/* Interpreter to use for nested command\n\t\t\t\t * evaluations and error messages. */\n    unsigned char *string;\t/* Character just after opening bracket. */\n    int flags;\t\t\t/* Flags to pass to nested Tcl_Eval. */\n    unsigned char **termPtr;\t/* Store address of terminating character\n\t\t\t\t * here. */\n    register ParseValue *pvPtr;\t/* Information about where to place\n\t\t\t\t * result of command. */\n{\n    int result, length, shortfall;\n    Interp *iPtr = (Interp *) interp;\n\n    result = Tcl_Eval(interp, string, flags | TCL_BRACKET_TERM, termPtr);\n    if (result != TCL_OK) {\n\t/*\n\t * The increment below results in slightly cleaner message in\n\t * the errorInfo variable (the close-bracket will appear).\n\t */\n\n\tif (**termPtr == ']') {\n\t    *termPtr += 1;\n\t}\n\treturn result;\n    }\n    (*termPtr) += 1;\n    length = strlen(iPtr->result);\n    shortfall = length + 1 - (pvPtr->end - pvPtr->next);\n    if (shortfall > 0) {\n\t(*pvPtr->expandProc) (pvPtr, shortfall);\n    }\n    strcpy(pvPtr->next, iPtr->result);\n    pvPtr->next += length;\n    Tcl_FreeResult ((Tcl_Interp*) iPtr);\n    iPtr->result = iPtr->resultSpace;\n    iPtr->resultSpace[0] = '\\0';\n    return TCL_OK;\n}\n\f\n/*\n *--------------------------------------------------------------\n *\n * TclParseBraces --\n *\n *\tThis procedure scans the information between matching\n *\tcurly braces.\n *\n * Results:\n *\tThe return value is a standard Tcl result, which is\n *\tTCL_OK unless there was an error while parsing string.\n *\tIf an error occurs then interp->result contains a\n *\tstandard error message.  *TermPtr is filled\n *\tin with the address of the character just after the\n *\tlast one successfully processed;  this is usually the\n *\tcharacter just after the matching close-brace.  The\n *\tinformation between curly braces is stored in standard\n *\tfashion in *pvPtr, null-terminated with pvPtr->next\n *\tpointing to the terminating null character.\n *\n * Side effects:\n *\tThe storage space at *pvPtr may be expanded.\n *\n *--------------------------------------------------------------\n */\n\nint\nTclParseBraces(interp, string, termPtr, pvPtr)\n    Tcl_Interp *interp;\t\t/* Interpreter to use for nested command\n\t\t\t\t * evaluations and error messages. */\n    unsigned char *string;\t/* Character just after opening bracket. */\n    unsigned char **termPtr;\t/* Store address of terminating character\n\t\t\t\t * here. */\n    register ParseValue *pvPtr;\t/* Information about where to place\n\t\t\t\t * result of command. */\n{\n    int level;\n    register unsigned char *src, *dst, *end;\n    register char c;\n\n    src = string;\n    dst = pvPtr->next;\n    end = pvPtr->end;\n    level = 1;\n\n    /*\n     * Copy the characters one at a time to the result area, stopping\n     * when the matching close-brace is found.\n     */\n\n    while (1) {\n\tc = *src;\n\tsrc++;\n\tif (dst == end) {\n\t    pvPtr->next = dst;\n\t    (*pvPtr->expandProc) (pvPtr, 20);\n\t    dst = pvPtr->next;\n\t    end = pvPtr->end;\n\t}\n\t*dst = c;\n\tdst++;\n\tif (CHAR_TYPE(c) == TCL_NORMAL) {\n\t    continue;\n\t} else if (c == '{') {\n\t    level++;\n\t} else if (c == '}') {\n\t    level--;\n\t    if (level == 0) {\n\t\tdst--;\t\t\t/* Don't copy the last close brace. */\n\t\tbreak;\n\t    }\n\t} else if (c == '\\\\') {\n\t    int count;\n\n\t    /*\n\t     * Must always squish out backslash-newlines, even when in\n\t     * braces.  This is needed so that this sequence can appear\n\t     * anywhere in a command, such as the middle of an expression.\n\t     */\n\n\t    if (*src == '\\n') {\n\t\tdst--;\n\t\tsrc++;\n\t    } else {\n\t\t(void) Tcl_Backslash(src-1, &count);\n\t\twhile (count > 1) {\n                    if (dst == end) {\n                        pvPtr->next = dst;\n                        (*pvPtr->expandProc) (pvPtr, 20);\n                        dst = pvPtr->next;\n                        end = pvPtr->end;\n                    }\n\t\t    *dst = *src;\n\t\t    dst++;\n\t\t    src++;\n\t\t    count--;\n\t\t}\n\t    }\n\t} else if (c == '\\0') {\n\t    Tcl_SetResult(interp, (unsigned char*) \"missing close-brace\", TCL_STATIC);\n\t    *termPtr = string-1;\n\t    return TCL_ERROR;\n\t}\n    }\n\n    *dst = '\\0';\n    pvPtr->next = dst;\n    *termPtr = src;\n    return TCL_OK;\n}\n\f\n/*\n *--------------------------------------------------------------\n *\n * TclParseWords --\n *\n *\tThis procedure parses one or more words from a command\n *\tstring and creates argv-style pointers to fully-substituted\n *\tcopies of those words.\n *\n * Results:\n *\tThe return value is a standard Tcl result.\n *\n *\t*argcPtr is modified to hold a count of the number of words\n *\tsuccessfully parsed, which may be 0.  At most maxWords words\n *\twill be parsed.  If 0 <= *argcPtr < maxWords then it\n *\tmeans that a command separator was seen.  If *argcPtr\n *\tis maxWords then it means that a command separator was\n *\tnot seen yet.\n *\n *\t*TermPtr is filled in with the address of the character\n *\tjust after the last one successfully processed in the\n *\tlast word.  This is either the command terminator (if\n *\t*argcPtr < maxWords), the character just after the last\n *\tone in a word (if *argcPtr is maxWords), or the vicinity\n *\tof an error (if the result is not TCL_OK).\n *\n *\tThe pointers at *argv are filled in with pointers to the\n *\tfully-substituted words, and the actual contents of the\n *\twords are copied to the buffer at pvPtr.\n *\n *\tIf an error occurrs then an error message is left in\n *\tinterp->result and the information at *argv, *argcPtr,\n *\tand *pvPtr may be incomplete.\n *\n * Side effects:\n *\tThe buffer space in pvPtr may be enlarged by calling its\n *\texpandProc.\n *\n *--------------------------------------------------------------\n */\n\nint\nTclParseWords(interp, string, flags, maxWords, termPtr, argcPtr, argv, pvPtr)\n    Tcl_Interp *interp;\t\t/* Interpreter to use for nested command\n\t\t\t\t * evaluations and error messages. */\n    unsigned char *string;\t/* First character of word. */\n    int flags;\t\t\t/* Flags to control parsing (same values as\n\t\t\t\t * passed to Tcl_Eval). */\n    int maxWords;\t\t/* Maximum number of words to parse. */\n    unsigned char **termPtr;\t/* Store address of terminating character\n\t\t\t\t * here. */\n    int *argcPtr;\t\t/* Filled in with actual number of words\n\t\t\t\t * parsed. */\n    unsigned char **argv;\t/* Store addresses of individual words here. */\n    register ParseValue *pvPtr;\t/* Information about where to place\n\t\t\t\t * fully-substituted word. */\n{\n    register unsigned char *src, *dst;\n    register char c;\n    int type, result, argc;\n    unsigned char *oldBuffer;\t/* Used to detect when pvPtr's buffer gets\n\t\t\t\t * reallocated, so we can adjust all of the\n\t\t\t\t * argv pointers. */\n\n    src = string;\n    oldBuffer = pvPtr->buffer;\n    dst = pvPtr->next;\n    for (argc = 0; argc < maxWords; argc++) {\n\targv[argc] = dst;\n\n\t/*\n\t * Skip leading space.\n\t */\n\n\tskipSpace:\n\tc = *src;\n\ttype = CHAR_TYPE(c);\n\twhile (type == TCL_SPACE) {\n\t    src++;\n\t    c = *src;\n\t    type = CHAR_TYPE(c);\n\t}\n\n\t/*\n\t * Handle the normal case (i.e. no leading double-quote or brace).\n\t */\n\n\tif (type == TCL_NORMAL) {\n\t    normalArg:\n\t    while (1) {\n\t\tif (dst == pvPtr->end) {\n\t\t    /*\n\t\t     * Target buffer space is about to run out.  Make\n\t\t     * more space.\n\t\t     */\n\n\t\t    pvPtr->next = dst;\n\t\t    (*pvPtr->expandProc) (pvPtr, 1);\n\t\t    dst = pvPtr->next;\n\t\t}\n\n\t\tif (type == TCL_NORMAL) {\n\t\t    copy:\n\t\t    *dst = c;\n\t\t    dst++;\n\t\t    src++;\n\t\t} else if (type == TCL_SPACE) {\n\t\t    goto wordEnd;\n\t\t} else if (type == TCL_DOLLAR) {\n\t\t    int length;\n\t\t    unsigned char *value;\n\n\t\t    value = Tcl_ParseVar(interp, src, termPtr);\n\t\t    if (value == 0) {\n\t\t\treturn TCL_ERROR;\n\t\t    }\n\t\t    src = *termPtr;\n\t\t    length = strlen(value);\n\t\t    if ((pvPtr->end - dst) <= length) {\n\t\t\tpvPtr->next = dst;\n\t\t\t(*pvPtr->expandProc) (pvPtr, length);\n\t\t\tdst = pvPtr->next;\n\t\t    }\n\t\t    strcpy(dst, value);\n\t\t    dst += length;\n\t\t} else if (type == TCL_COMMAND_END) {\n\t\t    if ((c == ']') && !(flags & TCL_BRACKET_TERM)) {\n\t\t\tgoto copy;\n\t\t    }\n\n\t\t    /*\n\t\t     * End of command;  simulate a word-end first, so\n\t\t     * that the end-of-command can be processed as the\n\t\t     * first thing in a new word.\n\t\t     */\n\n\t\t    goto wordEnd;\n\t\t} else if (type == TCL_OPEN_BRACKET) {\n\t\t    pvPtr->next = dst;\n\t\t    result = TclParseNestedCmd(interp, src+1, flags, termPtr,\n\t\t\t    pvPtr);\n\t\t    if (result != TCL_OK) {\n\t\t\treturn result;\n\t\t    }\n\t\t    src = *termPtr;\n\t\t    dst = pvPtr->next;\n\t\t} else if (type == TCL_BACKSLASH) {\n\t\t    int numRead;\n\n\t\t    *dst = Tcl_Backslash(src, &numRead);\n\t\t    if (*dst != 0) {\n\t\t\tdst++;\n\t\t    }\n\t\t    src += numRead;\n\t\t} else {\n\t\t    goto copy;\n\t\t}\n\t\tc = *src;\n\t\ttype = CHAR_TYPE(c);\n\t    }\n\t} else {\n\n\t    /*\n\t     * Check for the end of the command.\n\t     */\n\n\t    if (type == TCL_COMMAND_END) {\n\t\tif (flags & TCL_BRACKET_TERM) {\n\t\t    if (c == '\\0') {\n\t\t\tTcl_SetResult(interp, (unsigned char*) \"missing close-bracket\",\n\t\t\t\tTCL_STATIC);\n\t\t\treturn TCL_ERROR;\n\t\t    }\n\t\t} else {\n\t\t    if (c == ']') {\n\t\t\tgoto normalArg;\n\t\t    }\n\t\t}\n\t\tgoto done;\n\t    }\n\n\t    /*\n\t     * Now handle the special cases: open braces, double-quotes,\n\t     * and backslash-newline.\n\t     */\n\n\t    pvPtr->next = dst;\n\t    if (type == TCL_QUOTE) {\n\t\tresult = TclParseQuotes(interp, src+1, '\"', flags,\n\t\t\ttermPtr, pvPtr);\n\t    } else if (type == TCL_OPEN_BRACE) {\n\t\tresult = TclParseBraces(interp, src+1, termPtr, pvPtr);\n\t    } else if ((type == TCL_BACKSLASH) && (src[1] == '\\n')) {\n\t\tsrc += 2;\n\t\tgoto skipSpace;\n\t    } else {\n\t\tgoto normalArg;\n\t    }\n\t    if (result != TCL_OK) {\n\t\treturn result;\n\t    }\n\n\t    /*\n\t     * Back from quotes or braces;  make sure that the terminating\n\t     * character was the end of the word.  Have to be careful here\n\t     * to handle continuation lines (i.e. lines ending in backslash).\n\t     */\n\n\t    c = **termPtr;\n\t    if ((c == '\\\\') && ((*termPtr)[1] == '\\n')) {\n\t\tc = (*termPtr)[2];\n\t    }\n\t    type = CHAR_TYPE(c);\n\t    if ((type != TCL_SPACE) && (type != TCL_COMMAND_END)) {\n\t\tif (*src == '\"') {\n\t\t    Tcl_SetResult(interp, (unsigned char*) \"extra characters after close-quote\",\n\t\t\t    TCL_STATIC);\n\t\t} else {\n\t\t    Tcl_SetResult(interp, (unsigned char*) \"extra characters after close-brace\",\n\t\t\t    TCL_STATIC);\n\t\t}\n\t\treturn TCL_ERROR;\n\t    }\n\t    src = *termPtr;\n\t    dst = pvPtr->next;\n\n\t}\n\n\t/*\n\t * We're at the end of a word, so add a null terminator.  Then\n\t * see if the buffer was re-allocated during this word.  If so,\n\t * update all of the argv pointers.\n\t */\n\n\twordEnd:\n\t*dst = '\\0';\n\tdst++;\n\tif (oldBuffer != pvPtr->buffer) {\n\t    int i;\n\n\t    for (i = 0; i <= argc; i++) {\n\t\targv[i] = pvPtr->buffer + (argv[i] - oldBuffer);\n\t    }\n\t    oldBuffer = pvPtr->buffer;\n\t}\n    }\n\n    done:\n    pvPtr->next = dst;\n    *termPtr = src;\n    *argcPtr = argc;\n    return TCL_OK;\n}\n\f\n/*\n *--------------------------------------------------------------\n *\n * TclExpandParseValue --\n *\n *\tThis procedure is commonly used as the value of the\n *\texpandProc in a ParseValue.  It uses malloc to allocate\n *\tmore space for the result of a parse.\n *\n * Results:\n *\tThe buffer space in *pvPtr is reallocated to something\n *\tlarger, and if pvPtr->clientData is non-zero the old\n *\tbuffer is freed.  Information is copied from the old\n *\tbuffer to the new one.\n *\n * Side effects:\n *\tNone.\n *\n *--------------------------------------------------------------\n */\n\nvoid\nTclExpandParseValue (ParseValue *pvPtr,\t/* Information about buffer that\n\t\t\t\t\t * must be expanded.  If the clientData\n\t\t\t\t\t * in the structure is non-zero, it\n\t\t\t\t\t * means that the current buffer is\n\t\t\t\t\t * dynamically allocated. */\n\tunsigned short needed)\t\t/* Minimum amount of additional space\n\t\t\t\t\t * to allocate. */\n{\n    int newSpace;\n    unsigned char *new;\n\n    /*\n     * Either double the size of the buffer or add enough new space\n     * to meet the demand, whichever produces a larger new buffer.\n     */\n\n    newSpace = (pvPtr->end - pvPtr->buffer) + 1;\n    if (newSpace < needed) {\n\tnewSpace += needed;\n    } else {\n\tnewSpace += newSpace;\n    }\n    new = malloc (newSpace);\n\n    /*\n     * Copy from old buffer to new, free old buffer if needed, and\n     * mark new buffer as malloc-ed.\n     */\n    memcpy ((void*) new, (void*) pvPtr->buffer, pvPtr->next - pvPtr->buffer);\n    pvPtr->next = new + (pvPtr->next - pvPtr->buffer);\n    if (pvPtr->clientData != 0) {\n\tfree(pvPtr->buffer);\n    }\n    pvPtr->buffer = new;\n    pvPtr->end = new + newSpace - 1;\n    pvPtr->clientData = (void*) 1;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * TclWordEnd --\n *\n *\tGiven a pointer into a Tcl command, find the end of the next\n *\tword of the command.\n *\n * Results:\n *\tThe return value is a pointer to the last character that's part\n *\tof the word pointed to by \"start\".  If the word doesn't end\n *\tproperly within the string then the return value is the address\n *\tof the null character at the end of the string.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nunsigned char *\nTclWordEnd(start, nested)\n    unsigned char *start;\t/* Beginning of a word of a Tcl command. */\n    int nested;\t\t\t/* Zero means this is a top-level command.\n\t\t\t\t * One means this is a nested command (close\n\t\t\t\t * brace is a word terminator). */\n{\n    register unsigned char *p;\n    int count;\n\n    p = start;\n    while (isspace(*p)) {\n\tp++;\n    }\n\n    /*\n     * Handle words beginning with a double-quote or a brace.\n     */\n\n    if (*p == '\"') {\n\tp = QuoteEnd(p+1, '\"');\n\tif (*p == 0) {\n\t    return p;\n\t}\n\tp++;\n    } else if (*p == '{') {\n\tint braces = 1;\n\twhile (braces != 0) {\n\t    p++;\n\t    while (*p == '\\\\') {\n\t\t(void) Tcl_Backslash(p, &count);\n\t\tp += count;\n\t    }\n\t    if (*p == '}') {\n\t\tbraces--;\n\t    } else if (*p == '{') {\n\t\tbraces++;\n\t    } else if (*p == 0) {\n\t\treturn p;\n\t    }\n\t}\n\tp++;\n    }\n\n    /*\n     * Handle words that don't start with a brace or double-quote.\n     * This code is also invoked if the word starts with a brace or\n     * double-quote and there is garbage after the closing brace or\n     * quote.  This is an error as far as Tcl_Eval is concerned, but\n     * for here the garbage is treated as part of the word.\n     */\n\n    while (1) {\n\tif (*p == '[') {\n\t    for (p++; *p != ']'; p++) {\n\t\tp = TclWordEnd(p, 1);\n\t\tif (*p == 0) {\n\t\t    return p;\n\t\t}\n\t    }\n\t    p++;\n\t} else if (*p == '\\\\') {\n\t    (void) Tcl_Backslash(p, &count);\n\t    p += count;\n\t    if ((*p == 0) && (count == 2) && (p[-1] == '\\n')) {\n\t\treturn p;\n\t    }\n\t} else if (*p == '$') {\n\t    p = VarNameEnd(p);\n\t    if (*p == 0) {\n\t\treturn p;\n\t    }\n\t    p++;\n\t} else if (*p == ';') {\n\t    /*\n\t     * Include the semi-colon in the word that is returned.\n\t     */\n\n\t    return p;\n\t} else if (isspace(*p)) {\n\t    return p-1;\n\t} else if ((*p == ']') && nested) {\n\t    return p-1;\n\t} else if (*p == 0) {\n\t    if (nested) {\n\t\t/*\n\t\t * Nested commands can't end because of the end of the\n\t\t * string.\n\t\t */\n\t\treturn p;\n\t    }\n\t    return p-1;\n\t} else {\n\t    p++;\n\t}\n    }\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * QuoteEnd --\n *\n *\tGiven a pointer to a string that obeys the parsing conventions\n *\tfor quoted things in Tcl, find the end of that quoted thing.\n *\tThe actual thing may be a quoted argument or a parenthesized\n *\tindex name.\n *\n * Results:\n *\tThe return value is a pointer to the last character that is\n *\tpart of the quoted string (i.e the character that's equal to\n *\tterm).  If the quoted string doesn't terminate properly then\n *\tthe return value is a pointer to the null character at the\n *\tend of the string.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nstatic unsigned char *\nQuoteEnd(string, term)\n    unsigned char *string;\t/* Pointer to character just after opening\n\t\t\t\t * \"quote\". */\n    int term;\t\t\t/* This character will terminate the\n\t\t\t\t * quoted string (e.g. '\"' or ')'). */\n{\n    register unsigned char *p = string;\n    int count;\n\n    while (*p != term) {\n\tif (*p == '\\\\') {\n\t    (void) Tcl_Backslash(p, &count);\n\t    p += count;\n\t} else if (*p == '[') {\n\t    for (p++; *p != ']'; p++) {\n\t\tp = TclWordEnd(p, 1);\n\t\tif (*p == 0) {\n\t\t    return p;\n\t\t}\n\t    }\n\t    p++;\n\t} else if (*p == '$') {\n\t    p = VarNameEnd(p);\n\t    if (*p == 0) {\n\t\treturn p;\n\t    }\n\t    p++;\n\t} else if (*p == 0) {\n\t    return p;\n\t} else {\n\t    p++;\n\t}\n    }\n    return p-1;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * VarNameEnd --\n *\n *\tGiven a pointer to a variable reference using $-notation, find\n *\tthe end of the variable name spec.\n *\n * Results:\n *\tThe return value is a pointer to the last character that\n *\tis part of the variable name.  If the variable name doesn't\n *\tterminate properly then the return value is a pointer to the\n *\tnull character at the end of the string.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nstatic unsigned char *\nVarNameEnd(string)\n    unsigned char *string;\t/* Pointer to dollar-sign character. */\n{\n    register unsigned char *p = string+1;\n\n    if (*p == '{') {\n\tfor (p++; (*p != '}') && (*p != 0); p++) {\n\t    /* Empty loop body. */\n\t}\n\treturn p;\n    }\n    while (isalnum(*p) || (*p == '_')) {\n\tp++;\n    }\n    if ((*p == '(') && (p != string+1)) {\n\treturn QuoteEnd(p+1, ')');\n    }\n    return p-1;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_ParseVar --\n *\n *\tGiven a string starting with a $ sign, parse off a variable\n *\tname and return its value.\n *\n * Results:\n *\tThe return value is the contents of the variable given by\n *\tthe leading characters of string.  If termPtr isn't NULL,\n *\t*termPtr gets filled in with the address of the character\n *\tjust after the last one in the variable specifier.  If the\n *\tvariable doesn't exist, then the return value is NULL and\n *\tan error message will be left in interp->result.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nunsigned char *\nTcl_ParseVar(interp, string, termPtr)\n    Tcl_Interp *interp;\t\t\t/* Context for looking up variable. */\n    register unsigned char *string;\t/* String containing variable name.\n\t\t\t\t\t * First character must be \"$\". */\n    unsigned char **termPtr;\t\t/* If non-NULL, points to word to fill\n\t\t\t\t\t * in with character just after last\n\t\t\t\t\t * one in the variable specifier. */\n\n{\n    unsigned char *name1, *name1End, c, *result;\n    register unsigned char *name2;\n#define NUM_CHARS 200\n    unsigned char copyStorage[NUM_CHARS];\n    ParseValue pv;\n\n    /*\n     * There are three cases:\n     * 1. The $ sign is followed by an open curly brace.  Then the variable\n     *    name is everything up to the next close curly brace, and the\n     *    variable is a scalar variable.\n     * 2. The $ sign is not followed by an open curly brace.  Then the\n     *    variable name is everything up to the next character that isn't\n     *    a letter, digit, or underscore.  If the following character is an\n     *    open parenthesis, then the information between parentheses is\n     *    the array element name, which can include any of the substitutions\n     *    permissible between quotes.\n     * 3. The $ sign is followed by something that isn't a letter, digit,\n     *    or underscore:  in this case, there is no variable name, and \"$\"\n     *    is returned.\n     */\n\n    name2 = 0;\n    string++;\n    if (*string == '{') {\n\tstring++;\n\tname1 = string;\n\twhile (*string != '}') {\n\t    if (*string == 0) {\n\t\tTcl_SetResult(interp, (unsigned char*) \"missing close-brace for variable name\",\n\t\t\tTCL_STATIC);\n\t\tif (termPtr != 0) {\n\t\t    *termPtr = string;\n\t\t}\n\t\treturn 0;\n\t    }\n\t    string++;\n\t}\n\tname1End = string;\n\tstring++;\n    } else {\n\tname1 = string;\n\twhile (isalnum(*string) || (*string == '_')) {\n\t    string++;\n\t}\n\tif (string == name1) {\n\t    if (termPtr != 0) {\n\t\t*termPtr = string;\n\t    }\n\t    return (unsigned char*) \"$\";\n\t}\n\tname1End = string;\n\tif (*string == '(') {\n\t    unsigned char *end;\n\n\t    /*\n\t     * Perform substitutions on the array element name, just as\n\t     * is done for quotes.\n\t     */\n\n\t    pv.buffer = pv.next = copyStorage;\n\t    pv.end = copyStorage + NUM_CHARS - 1;\n\t    pv.expandProc = TclExpandParseValue;\n\t    pv.clientData = (void*) 0;\n\t    if (TclParseQuotes(interp, string+1, ')', 0, &end, &pv)\n\t\t    != TCL_OK) {\n\t\tunsigned char msg[100];\n\t\tsprintf(msg, \"\\n    (parsing index for array \\\"%.*s\\\")\",\n\t\t\t(int) (string - name1), name1);\n\t\tTcl_AddErrorInfo(interp, msg);\n\t\tresult = 0;\n\t\tname2 = pv.buffer;\n\t\tif (termPtr != 0) {\n\t\t    *termPtr = end;\n\t\t}\n\t\tgoto done;\n\t    }\n\t    string = end;\n\t    name2 = pv.buffer;\n\t}\n    }\n    if (termPtr != 0) {\n\t*termPtr = string;\n    }\n\n    if (((Interp *) interp)->noEval) {\n\treturn (unsigned char*) \"\";\n    }\n    c = *name1End;\n    *name1End = 0;\n    result = Tcl_GetVar2(interp, name1, name2, TCL_LEAVE_ERR_MSG);\n    *name1End = c;\n\n    done:\n    if ((name2 != 0) && (pv.buffer != copyStorage)) {\n\tfree(pv.buffer);\n    }\n    return result;\n}\n"
  },
  {
    "path": "lib/libtcl/tclproc.c",
    "content": "/*\n * tclProc.c --\n *\n *\tThis file contains routines that implement Tcl procedures,\n *\tincluding the \"proc\" and \"uplevel\" commands.\n *\n * Copyright 1987-1991 Regents of the University of California\n * Permission to use, copy, modify, and distribute this\n * software and its documentation for any purpose and without\n * fee is hereby granted, provided that the above copyright\n * notice appear in all copies.  The University of California\n * makes no representations about the suitability of this\n * software for any purpose.  It is provided \"as is\" without\n * express or implied warranty.\n */\n#include \"internal.h\"\n\n/*\n * Forward references to procedures defined later in this file:\n */\nstatic  int\tInterpProc (void *clientData, Tcl_Interp *interp,\n\t\t\tint argc, unsigned char **argv);\nstatic  void\tProcDeleteProc (void *clientData);\n\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_ProcCmd --\n *\n *\tThis procedure is invoked to process the \"proc\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result value.\n *\n * Side effects:\n *\tA new procedure gets created.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_ProcCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    register Interp *iPtr = (Interp *) interp;\n    register Proc *procPtr;\n    int result, argCount, i;\n    unsigned char **argArray = 0;\n    Arg *lastArgPtr;\n    register Arg *argPtr = 0;\t\t/* Initialization not needed, but\n\t\t\t\t\t * prevents compiler warning. */\n\n    if (argc != 4) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" name args body\\\"\", (char *) 0);\n\treturn TCL_ERROR;\n    }\n\n    procPtr = (Proc*) malloc (sizeof(Proc));\n    procPtr->iPtr = iPtr;\n    procPtr->command = malloc (strlen(argv[3]) + 1);\n    strcpy(procPtr->command, argv[3]);\n    procPtr->argPtr = 0;\n\n    /*\n     * Break up the argument list into argument specifiers, then process\n     * each argument specifier.\n     */\n\n    result = Tcl_SplitList(interp, argv[2], &argCount, &argArray);\n    if (result != TCL_OK) {\n\tgoto procError;\n    }\n    lastArgPtr = 0;\n    for (i = 0; i < argCount; i++) {\n\tint fieldCount, nameLength, valueLength;\n\tunsigned char **fieldValues;\n\n\t/*\n\t * Now divide the specifier up into name and default.\n\t */\n\n\tresult = Tcl_SplitList(interp, argArray[i], &fieldCount,\n\t\t&fieldValues);\n\tif (result != TCL_OK) {\n\t    goto procError;\n\t}\n\tif (fieldCount > 2) {\n\t    free((char *) fieldValues);\n\t    Tcl_AppendResult(interp,\n\t\t    \"too many fields in argument specifier \\\"\",\n\t\t    argArray[i], \"\\\"\", (char *) 0);\n\t    result = TCL_ERROR;\n\t    goto procError;\n\t}\n\tif ((fieldCount == 0) || (*fieldValues[0] == 0)) {\n\t    free((char *) fieldValues);\n\t    Tcl_AppendResult(interp, \"procedure \\\"\", argv[1],\n\t\t    \"\\\" has argument with no name\", (char *) 0);\n\t    result = TCL_ERROR;\n\t    goto procError;\n\t}\n\tnameLength = strlen(fieldValues[0]) + 1;\n\tif (fieldCount == 2) {\n\t    valueLength = strlen(fieldValues[1]) + 1;\n\t} else {\n\t    valueLength = 0;\n\t}\n\targPtr = (Arg*) malloc ((unsigned) (sizeof(Arg) - sizeof(argPtr->name)\n                + nameLength + valueLength));\n\tif (lastArgPtr == 0) {\n\t    procPtr->argPtr = argPtr;\n\t} else {\n\t    lastArgPtr->nextPtr = argPtr;\n\t}\n\tlastArgPtr = argPtr;\n\targPtr->nextPtr = 0;\n\tstrcpy(argPtr->name, fieldValues[0]);\n\tif (fieldCount == 2) {\n\t    argPtr->defValue = argPtr->name + nameLength;\n\t    strcpy(argPtr->defValue, fieldValues[1]);\n\t} else {\n\t    argPtr->defValue = 0;\n\t}\n\tfree((char *) fieldValues);\n    }\n\n    Tcl_CreateCommand(interp, argv[1], InterpProc, (void*) procPtr,\n\t    ProcDeleteProc);\n    free((char *) argArray);\n    return TCL_OK;\n\n    procError:\n    free(procPtr->command);\n    while (procPtr->argPtr != 0) {\n\targPtr = procPtr->argPtr;\n\tprocPtr->argPtr = argPtr->nextPtr;\n\tfree((char *) argPtr);\n    }\n    free((char *) procPtr);\n    if (argArray != 0) {\n\tfree((char *) argArray);\n    }\n    return result;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * TclGetFrame --\n *\n *\tGiven a description of a procedure frame, such as the first\n *\targument to an \"uplevel\" or \"upvar\" command, locate the\n *\tcall frame for the appropriate level of procedure.\n *\n * Results:\n *\tThe return value is -1 if an error occurred in finding the\n *\tframe (in this case an error message is left in interp->result).\n *\t1 is returned if string was either a number or a number preceded\n *\tby \"#\" and it specified a valid frame.  0 is returned if string\n *\tisn't one of the two things above (in this case, the lookup\n *\tacts as if string were \"1\").  The variable pointed to by\n *\tframePtrPtr is filled in with the address of the desired frame\n *\t(unless an error occurs, in which case it isn't modified).\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTclGetFrame(interp, string, framePtrPtr)\n    Tcl_Interp *interp;\t\t/* Interpreter in which to find frame. */\n    unsigned char *string;\t/* String describing frame. */\n    CallFrame **framePtrPtr;\t/* Store pointer to frame here (or NULL\n\t\t\t\t * if global frame indicated). */\n{\n    register Interp *iPtr = (Interp *) interp;\n    int level, result;\n    CallFrame *framePtr;\n\n    if (iPtr->varFramePtr == 0) {\n\tiPtr->result = (unsigned char*) \"already at top level\";\n\treturn -1;\n    }\n\n    /*\n     * Parse string to figure out which level number to go to.\n     */\n\n    result = 1;\n    if (*string == '#') {\n\tif (Tcl_GetInt(interp, string+1, &level) != TCL_OK) {\n\t    return -1;\n\t}\n\tif (level < 0) {\n\t    levelError:\n\t    Tcl_AppendResult(interp, \"bad level \\\"\", string, \"\\\"\",\n\t\t    (char *) 0);\n\t    return -1;\n\t}\n    } else if (isdigit(*string)) {\n\tif (Tcl_GetInt(interp, string, &level) != TCL_OK) {\n\t    return -1;\n\t}\n\tlevel = iPtr->varFramePtr->level - level;\n    } else {\n\tlevel = iPtr->varFramePtr->level - 1;\n\tresult = 0;\n    }\n\n    /*\n     * Figure out which frame to use, and modify the interpreter so\n     * its variables come from that frame.\n     */\n\n    if (level == 0) {\n\tframePtr = 0;\n    } else {\n\tfor (framePtr = iPtr->varFramePtr; framePtr != 0;\n\t\tframePtr = framePtr->callerVarPtr) {\n\t    if (framePtr->level == level) {\n\t\tbreak;\n\t    }\n\t}\n\tif (framePtr == 0) {\n\t    goto levelError;\n\t}\n    }\n    *framePtrPtr = framePtr;\n    return result;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_UplevelCmd --\n *\n *\tThis procedure is invoked to process the \"uplevel\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result value.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_UplevelCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    register Interp *iPtr = (Interp *) interp;\n    int result;\n    CallFrame *savedVarFramePtr, *framePtr;\n\n    if (argc < 2) {\n\tuplevelSyntax:\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" ?level? command ?arg ...?\\\"\", (char *) 0);\n\treturn TCL_ERROR;\n    }\n\n    /*\n     * Find the level to use for executing the command.\n     */\n\n    result = TclGetFrame(interp, argv[1], &framePtr);\n    if (result == -1) {\n\treturn TCL_ERROR;\n    }\n    argc -= (result+1);\n    if (argc == 0) {\n\tgoto uplevelSyntax;\n    }\n    argv += (result+1);\n\n    /*\n     * Modify the interpreter state to execute in the given frame.\n     */\n\n    savedVarFramePtr = iPtr->varFramePtr;\n    iPtr->varFramePtr = framePtr;\n\n    /*\n     * Execute the residual arguments as a command.\n     */\n\n    if (argc == 1) {\n\tresult = Tcl_Eval(interp, argv[0], 0, 0);\n    } else {\n\tunsigned char *cmd;\n\n\tcmd = Tcl_Concat (argc, argv);\n\tresult = Tcl_Eval (interp, cmd, 0, 0);\n\tfree(cmd);\n    }\n    if (result == TCL_ERROR) {\n\tunsigned char msg[60];\n\tsprintf(msg, \"\\n    (\\\"uplevel\\\" body line %d)\",\n\t\tinterp->errorLine);\n\tTcl_AddErrorInfo(interp, msg);\n    }\n\n    /*\n     * Restore the variable frame, and return.\n     */\n\n    iPtr->varFramePtr = savedVarFramePtr;\n    return result;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * TclFindProc --\n *\n *\tGiven the name of a procedure, return a pointer to the\n *\trecord describing the procedure.\n *\n * Results:\n *\tNULL is returned if the name doesn't correspond to any\n *\tprocedure.  Otherwise the return value is a pointer to\n *\tthe procedure's record.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nProc *\nTclFindProc(iPtr, procName)\n    Interp *iPtr;\t\t/* Interpreter in which to look. */\n    unsigned char *procName;\t/* Name of desired procedure. */\n{\n    Tcl_HashEntry *hPtr;\n    Command *cmdPtr;\n\n    hPtr = Tcl_FindHashEntry(&iPtr->commandTable, procName);\n    if (hPtr == 0) {\n\treturn 0;\n    }\n    cmdPtr = (Command *) Tcl_GetHashValue(hPtr);\n    if (cmdPtr->proc != InterpProc) {\n\treturn 0;\n    }\n    return (Proc *) cmdPtr->clientData;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * TclIsProc --\n *\n *\tTells whether a command is a Tcl procedure or not.\n *\n * Results:\n *\tIf the given command is actuall a Tcl procedure, the\n *\treturn value is the address of the record describing\n *\tthe procedure.  Otherwise the return value is 0.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nProc *\nTclIsProc(cmdPtr)\n    Command *cmdPtr;\t\t/* Command to test. */\n{\n    if (cmdPtr->proc == InterpProc) {\n\treturn (Proc *) cmdPtr->clientData;\n    }\n    return (Proc *) 0;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * InterpProc --\n *\n *\tWhen a Tcl procedure gets invoked, this routine gets invoked\n *\tto interpret the procedure.\n *\n * Results:\n *\tA standard Tcl result value, usually TCL_OK.\n *\n * Side effects:\n *\tDepends on the commands in the procedure.\n *\n *----------------------------------------------------------------------\n */\n\nstatic int\nInterpProc(clientData, interp, argc, argv)\n    void *clientData;\t\t/* Record describing procedure to be\n\t\t\t\t * interpreted. */\n    Tcl_Interp *interp;\t\t/* Interpreter in which procedure was\n\t\t\t\t * invoked. */\n    int argc;\t\t\t/* Count of number of arguments to this\n\t\t\t\t * procedure. */\n    unsigned char **argv;\t/* Argument values. */\n{\n    register Proc *procPtr = (Proc *) clientData;\n    register Arg *argPtr;\n    register Interp *iPtr = (Interp *) interp;\n    unsigned char **args;\n    CallFrame frame;\n    unsigned char *value, *end;\n    int result;\n\n    /*\n     * Set up a call frame for the new procedure invocation.\n     */\n\n    iPtr = procPtr->iPtr;\n    Tcl_InitHashTable (&frame.varTable, TCL_STRING_KEYS);\n    if (iPtr->varFramePtr != 0) {\n\tframe.level = iPtr->varFramePtr->level + 1;\n    } else {\n\tframe.level = 1;\n    }\n    frame.argc = argc;\n    frame.argv = argv;\n    frame.callerPtr = iPtr->framePtr;\n    frame.callerVarPtr = iPtr->varFramePtr;\n    iPtr->framePtr = &frame;\n    iPtr->varFramePtr = &frame;\n\n    /*\n     * Match the actual arguments against the procedure's formal\n     * parameters to compute local variables.\n     */\n\n    for (argPtr = procPtr->argPtr, args = argv+1, argc -= 1;\n\t    argPtr != 0;\n\t    argPtr = argPtr->nextPtr, args++, argc--) {\n\n\t/*\n\t * Handle the special case of the last formal being \"args\".  When\n\t * it occurs, assign it a list consisting of all the remaining\n\t * actual arguments.\n\t */\n\n\tif ((argPtr->nextPtr == 0) &&\n\t  (strcmp (argPtr->name, (unsigned char*) \"args\") == 0)) {\n\t    if (argc < 0) {\n\t\targc = 0;\n\t    }\n\t    value = Tcl_Merge (argc, args);\n\t    Tcl_SetVar (interp, argPtr->name, value, 0);\n\t    free (value);\n\t    argc = 0;\n\t    break;\n\t} else if (argc > 0) {\n\t    value = *args;\n\t} else if (argPtr->defValue != 0) {\n\t    value = argPtr->defValue;\n\t} else {\n\t    Tcl_AppendResult(interp, \"no value given for parameter \\\"\",\n\t\t    argPtr->name, \"\\\" to \\\"\", argv[0], \"\\\"\", 0);\n\t    result = TCL_ERROR;\n\t    goto procDone;\n\t}\n\tTcl_SetVar(interp, argPtr->name, value, 0);\n    }\n    if (argc > 0) {\n\tTcl_AppendResult(interp, \"called \\\"\", argv[0],\n\t\t\"\\\" with too many arguments\", 0);\n\tresult = TCL_ERROR;\n\tgoto procDone;\n    }\n\n    /*\n     * Invoke the commands in the procedure's body.\n     */\n\n    result = Tcl_Eval(interp, procPtr->command, 0, &end);\n    if (result == TCL_RETURN) {\n\tresult = TCL_OK;\n    } else if (result == TCL_ERROR) {\n\tunsigned char msg[100];\n\n\t/*\n\t * Record information telling where the error occurred.\n\t */\n\n\tsprintf(msg, \"\\n    (procedure \\\"%.50s\\\" line %d)\", argv[0],\n\t\tiPtr->errorLine);\n\tTcl_AddErrorInfo(interp, msg);\n    } else if (result == TCL_BREAK) {\n\tiPtr->result = (unsigned char*) \"invoked \\\"break\\\" outside of a loop\";\n\tresult = TCL_ERROR;\n    } else if (result == TCL_CONTINUE) {\n\tiPtr->result = (unsigned char*) \"invoked \\\"continue\\\" outside of a loop\";\n\tresult = TCL_ERROR;\n    }\n\n    /*\n     * Delete the call frame for this procedure invocation (it's\n     * important to remove the call frame from the interpreter\n     * before deleting it, so that traces invoked during the\n     * deletion don't see the partially-deleted frame).\n     */\n\n    procDone:\n    iPtr->framePtr = frame.callerPtr;\n    iPtr->varFramePtr = frame.callerVarPtr;\n    TclDeleteVars(iPtr, &frame.varTable);\n    return result;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * ProcDeleteProc --\n *\n *\tThis procedure is invoked just before a command procedure is\n *\tremoved from an interpreter.  Its job is to release all the\n *\tresources allocated to the procedure.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tMemory gets freed.\n *\n *----------------------------------------------------------------------\n */\n\nstatic void\nProcDeleteProc(clientData)\n    void *clientData;\t\t/* Procedure to be deleted. */\n{\n    register Proc *procPtr = (Proc *) clientData;\n    register Arg *argPtr;\n\n    free (procPtr->command);\n    for (argPtr = procPtr->argPtr; argPtr != 0; ) {\n\tArg *nextPtr = argPtr->nextPtr;\n\n\tfree (argPtr);\n\targPtr = nextPtr;\n    }\n    free (procPtr);\n}\n\n/*\n * Free up result of interpreter.\n */\nvoid\nTcl_FreeResult (Tcl_Interp *interp)\n{\n    if (interp->freeProc != 0) {\n\tif (interp->freeProc == TCL_DYNAMIC)\n\t    free (interp->result);\n\telse\n\t    (*interp->freeProc) (interp->result);\n\tinterp->freeProc = 0;\n    }\n}\n"
  },
  {
    "path": "lib/libtcl/tclunxaz.c",
    "content": "/*\n * tclUnixAZ.c --\n *\n *\tThis file contains the top-level command procedures for\n *\tcommands in the Tcl core that require UNIX facilities\n *\tsuch as files and process execution.  Much of the code\n *\tin this file is based on earlier versions contributed\n *\tby Karl Lehenbauer, Mark Diekhans and Peter da Silva.\n *\n * Copyright 1991 Regents of the University of California\n * Permission to use, copy, modify, and distribute this\n * software and its documentation for any purpose and without\n * fee is hereby granted, provided that this copyright\n * notice appears in all copies.  The University of California\n * makes no representations about the suitability of this\n * software for any purpose.  It is provided \"as is\" without\n * express or implied warranty.\n */\n#include \"internal.h\"\n#include <sys/stat.h>\n#include <sys/param.h>\n#include <sys/time.h>\n#include <sys/wait.h>\n#include <unistd.h>\n#ifdef CROSS\n#   include </usr/include/errno.h>\n#else\n#   include <errno.h>\n#endif\n\n/*\n * The variable below caches the name of the current working directory\n * in order to avoid repeated calls to getwd.  The string is malloc-ed.\n * NULL means the cache needs to be refreshed.\n */\n\nstatic char *currentDir =  NULL;\n\n/*\n * Prototypes for local procedures defined in this file:\n */\n\nstatic int\t\tCleanupChildren (Tcl_Interp *interp,\n\t\t\t    int numPids, int *pidPtr, int errorId);\nstatic char *\t\tGetFileType (int mode);\nstatic int\t\tStoreStatData (Tcl_Interp *interp,\n\t\t\t    char *varName, struct stat *statPtr);\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_CdCmd --\n *\n *\tThis procedure is invoked to process the \"cd\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_CdCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    char *dirName;\n\n    if (argc > 2) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" dirName\\\"\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n\n    if (argc == 2) {\n\tdirName = argv[1];\n    } else {\n\tdirName = \"~\";\n    }\n    dirName = Tcl_TildeSubst(interp, dirName);\n    if (dirName == NULL) {\n\treturn TCL_ERROR;\n    }\n    if (currentDir != NULL) {\n\tfree(currentDir);\n\tcurrentDir = NULL;\n    }\n    if (chdir(dirName) != 0) {\n\tTcl_AppendResult(interp, \"couldn't change working directory to \\\"\",\n\t\tdirName, \"\\\": \", Tcl_UnixError(interp), (char *) NULL);\n\treturn TCL_ERROR;\n    }\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_CloseCmd --\n *\n *\tThis procedure is invoked to process the \"close\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_CloseCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    OpenFile *filePtr;\n    int result = TCL_OK;\n\n    if (argc != 2) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" fileId\\\"\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n    if (TclGetOpenFile(interp, argv[1], &filePtr) != TCL_OK) {\n\treturn TCL_ERROR;\n    }\n    ((Interp *) interp)->filePtrArray[(int)fileno(filePtr->f)] = NULL;\n\n    /*\n     * First close the file (in the case of a process pipeline, there may\n     * be two files, one for the pipe at each end of the pipeline).\n     */\n\n    if (filePtr->f2 != NULL) {\n\tif (fclose(filePtr->f2) == EOF) {\n\t    Tcl_AppendResult(interp, \"error closing \\\"\", argv[1],\n\t\t    \"\\\": \", Tcl_UnixError(interp), \"\\n\", (char *) NULL);\n\t    result = TCL_ERROR;\n\t}\n    }\n    if (fclose(filePtr->f) == EOF) {\n\tTcl_AppendResult(interp, \"error closing \\\"\", argv[1],\n\t\t\"\\\": \", Tcl_UnixError(interp), \"\\n\", (char *) NULL);\n\tresult = TCL_ERROR;\n    }\n\n    /*\n     * If the file was a connection to a pipeline, clean up everything\n     * associated with the child processes.\n     */\n\n    if (filePtr->numPids > 0) {\n\tif (CleanupChildren(interp, filePtr->numPids, filePtr->pidPtr,\n\t\tfilePtr->errorId) != TCL_OK) {\n\t    result = TCL_ERROR;\n\t}\n    }\n\n    free((char *) filePtr);\n    return result;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_EofCmd --\n *\n *\tThis procedure is invoked to process the \"eof\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_EofCmd(notUsed, interp, argc, argv)\n    void *notUsed;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    OpenFile *filePtr;\n\n    if (argc != 2) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" fileId\\\"\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n    if (TclGetOpenFile(interp, argv[1], &filePtr) != TCL_OK) {\n\treturn TCL_ERROR;\n    }\n    if (feof(filePtr->f)) {\n\tinterp->result = \"1\";\n    } else {\n\tinterp->result = \"0\";\n    }\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_ExecCmd --\n *\n *\tThis procedure is invoked to process the \"exec\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_ExecCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int outputId;\t\t\t/* File id for output pipe.  -1\n\t\t\t\t\t * means command overrode. */\n    int errorId;\t\t\t/* File id for temporary file\n\t\t\t\t\t * containing error output. */\n    int *pidPtr;\n    int numPids, result;\n\n    /*\n     * See if the command is to be run in background;  if so, create\n     * the command, detach it, and return.\n     */\n\n    if ((argv[argc-1][0] == '&') && (argv[argc-1][1] == 0)) {\n\targc--;\n\targv[argc] = NULL;\n\tnumPids = Tcl_CreatePipeline(interp, argc-1, argv+1, &pidPtr,\n\t\t(int *) NULL, (int *) NULL, (int *) NULL);\n\tif (numPids < 0) {\n\t    return TCL_ERROR;\n\t}\n\tTcl_DetachPids(numPids, pidPtr);\n\tfree((char *) pidPtr);\n\treturn TCL_OK;\n    }\n\n    /*\n     * Create the command's pipeline.\n     */\n\n    numPids = Tcl_CreatePipeline(interp, argc-1, argv+1, &pidPtr,\n\t    (int *) NULL, &outputId, &errorId);\n    if (numPids < 0) {\n\treturn TCL_ERROR;\n    }\n\n    /*\n     * Read the child's output (if any) and put it into the result.\n     */\n\n    result = TCL_OK;\n    if (outputId != -1) {\n\twhile (1) {\n#\t    define BUFFER_SIZE 1000\n\t    char buffer[BUFFER_SIZE+1];\n\t    int count;\n\n\t    count = read(outputId, buffer, BUFFER_SIZE);\n\n\t    if (count == 0) {\n\t\tbreak;\n\t    }\n\t    if (count < 0) {\n\t\tTcl_ResetResult(interp);\n\t\tTcl_AppendResult(interp,\n\t\t\t\"error reading from output pipe: \",\n\t\t\tTcl_UnixError(interp), (char *) NULL);\n\t\tresult = TCL_ERROR;\n\t\tbreak;\n\t    }\n\t    buffer[count] = 0;\n\t    Tcl_AppendResult(interp, buffer, (char *) NULL);\n\t}\n\tclose(outputId);\n    }\n\n    if (CleanupChildren(interp, numPids, pidPtr, errorId) != TCL_OK) {\n\tresult = TCL_ERROR;\n    }\n    return result;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_ExitCmd --\n *\n *\tThis procedure is invoked to process the \"exit\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_ExitCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int value;\n\n    if ((argc != 1) && (argc != 2)) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" ?returnCode?\\\"\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n    if (argc == 1) {\n\texit(0);\n    }\n    if (Tcl_GetInt(interp, argv[1], &value) != TCL_OK) {\n\treturn TCL_ERROR;\n    }\n    exit(value);\n    return TCL_OK;\t\t\t/* Better not ever reach this! */\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_FileCmd --\n *\n *\tThis procedure is invoked to process the \"file\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_FileCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    char *p;\n    int length, statOp;\n    int mode = 0;\t\t\t/* Initialized only to prevent\n\t\t\t\t\t * compiler warning message. */\n    struct stat statBuf;\n    char *fileName, c;\n\n    if (argc < 3) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" option name ?arg ...?\\\"\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n    c = argv[1][0];\n    length = strlen(argv[1]);\n\n    /*\n     * First handle operations on the file name.\n     */\n\n    fileName = Tcl_TildeSubst(interp, argv[2]);\n    if (fileName == NULL) {\n\treturn TCL_ERROR;\n    }\n    if ((c == 'd') && (strncmp(argv[1], \"dirname\", length) == 0)) {\n\tif (argc != 3) {\n\t    argv[1] = \"dirname\";\n\t    not3Args:\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" \", argv[1], \" name\\\"\", (char *) NULL);\n\t    return TCL_ERROR;\n\t}\n\tp = strrchr(fileName, '/');\n\tif (p == NULL) {\n\t    interp->result = \".\";\n\t} else if (p == fileName) {\n\t    interp->result = \"/\";\n\t} else {\n\t    *p = 0;\n\t    Tcl_SetResult(interp, fileName, TCL_VOLATILE);\n\t    *p = '/';\n\t}\n\treturn TCL_OK;\n    } else if ((c == 'r') && (strncmp(argv[1], \"rootname\", length) == 0)\n\t    && (length >= 2)) {\n\tchar *lastSlash;\n\n\tif (argc != 3) {\n\t    argv[1] = \"rootname\";\n\t    goto not3Args;\n\t}\n\tp = strrchr(fileName, '.');\n\tlastSlash = strrchr(fileName, '/');\n\tif ((p == NULL) || ((lastSlash != NULL) && (lastSlash > p))) {\n\t    Tcl_SetResult(interp, fileName, TCL_VOLATILE);\n\t} else {\n\t    *p = 0;\n\t    Tcl_SetResult(interp, fileName, TCL_VOLATILE);\n\t    *p = '.';\n\t}\n\treturn TCL_OK;\n    } else if ((c == 'e') && (strncmp(argv[1], \"extension\", length) == 0)\n\t    && (length >= 3)) {\n\tchar *lastSlash;\n\n\tif (argc != 3) {\n\t    argv[1] = \"extension\";\n\t    goto not3Args;\n\t}\n\tp = strrchr(fileName, '.');\n\tlastSlash = strrchr(fileName, '/');\n\tif ((p != NULL) && ((lastSlash == NULL) || (lastSlash < p))) {\n\t    Tcl_SetResult(interp, p, TCL_VOLATILE);\n\t}\n\treturn TCL_OK;\n    } else if ((c == 't') && (strncmp(argv[1], \"tail\", length) == 0)\n\t    && (length >= 2)) {\n\tif (argc != 3) {\n\t    argv[1] = \"tail\";\n\t    goto not3Args;\n\t}\n\tp = strrchr(fileName, '/');\n\tif (p != NULL) {\n\t    Tcl_SetResult(interp, p+1, TCL_VOLATILE);\n\t} else {\n\t    Tcl_SetResult(interp, fileName, TCL_VOLATILE);\n\t}\n\treturn TCL_OK;\n    }\n\n    /*\n     * Next, handle operations that can be satisfied with the \"access\"\n     * kernel call.\n     */\n\n    if (fileName == NULL) {\n\treturn TCL_ERROR;\n    }\n    if ((c == 'r') && (strncmp(argv[1], \"readable\", length) == 0)\n\t    && (length >= 5)) {\n\tif (argc != 3) {\n\t    argv[1] = \"readable\";\n\t    goto not3Args;\n\t}\n\tmode = R_OK;\n\tcheckAccess:\n\tif (access(fileName, mode) == -1) {\n\t    interp->result = \"0\";\n\t} else {\n\t    interp->result = \"1\";\n\t}\n\treturn TCL_OK;\n    } else if ((c == 'w') && (strncmp(argv[1], \"writable\", length) == 0)) {\n\tif (argc != 3) {\n\t    argv[1] = \"writable\";\n\t    goto not3Args;\n\t}\n\tmode = W_OK;\n\tgoto checkAccess;\n    } else if ((c == 'e') && (strncmp(argv[1], \"executable\", length) == 0)\n\t    && (length >= 3)) {\n\tif (argc != 3) {\n\t    argv[1] = \"executable\";\n\t    goto not3Args;\n\t}\n\tmode = X_OK;\n\tgoto checkAccess;\n    } else if ((c == 'e') && (strncmp(argv[1], \"exists\", length) == 0)\n\t    && (length >= 3)) {\n\tif (argc != 3) {\n\t    argv[1] = \"exists\";\n\t    goto not3Args;\n\t}\n\tmode = F_OK;\n\tgoto checkAccess;\n    }\n\n    /*\n     * Lastly, check stuff that requires the file to be stat-ed.\n     */\n\n    if ((c == 'a') && (strncmp(argv[1], \"atime\", length) == 0)) {\n\tif (argc != 3) {\n\t    argv[1] = \"atime\";\n\t    goto not3Args;\n\t}\n\tif (stat(fileName, &statBuf) == -1) {\n\t    goto badStat;\n\t}\n\tsprintf(interp->result, \"%ld\", statBuf.st_atime);\n\treturn TCL_OK;\n    } else if ((c == 'i') && (strncmp(argv[1], \"isdirectory\", length) == 0)\n\t    && (length >= 3)) {\n\tif (argc != 3) {\n\t    argv[1] = \"isdirectory\";\n\t    goto not3Args;\n\t}\n\tstatOp = 2;\n    } else if ((c == 'i') && (strncmp(argv[1], \"isfile\", length) == 0)\n\t    && (length >= 3)) {\n\tif (argc != 3) {\n\t    argv[1] = \"isfile\";\n\t    goto not3Args;\n\t}\n\tstatOp = 1;\n    } else if ((c == 'l') && (strncmp(argv[1], \"lstat\", length) == 0)) {\n\tif (argc != 4) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" lstat name varName\\\"\", (char *) NULL);\n\t    return TCL_ERROR;\n\t}\n\n\tif (lstat(fileName, &statBuf) == -1) {\n\t    Tcl_AppendResult(interp, \"couldn't lstat \\\"\", argv[2],\n\t\t    \"\\\": \", Tcl_UnixError(interp), (char *) NULL);\n\t    return TCL_ERROR;\n\t}\n\treturn StoreStatData(interp, argv[3], &statBuf);\n    } else if ((c == 'm') && (strncmp(argv[1], \"mtime\", length) == 0)) {\n\tif (argc != 3) {\n\t    argv[1] = \"mtime\";\n\t    goto not3Args;\n\t}\n\tif (stat(fileName, &statBuf) == -1) {\n\t    goto badStat;\n\t}\n\tsprintf(interp->result, \"%ld\", statBuf.st_mtime);\n\treturn TCL_OK;\n    } else if ((c == 'o') && (strncmp(argv[1], \"owned\", length) == 0)) {\n\tif (argc != 3) {\n\t    argv[1] = \"owned\";\n\t    goto not3Args;\n\t}\n\tstatOp = 0;\n#ifdef S_IFLNK\n    /*\n     * This option is only included if symbolic links exist on this system\n     * (in which case S_IFLNK should be defined).\n     */\n    } else if ((c == 'r') && (strncmp(argv[1], \"readlink\", length) == 0)\n\t    && (length >= 5)) {\n\tchar linkValue[MAXPATHLEN+1];\n\tint linkLength;\n\n\tif (argc != 3) {\n\t    argv[1] = \"readlink\";\n\t    goto not3Args;\n\t}\n\tlinkLength = readlink(fileName, linkValue, sizeof(linkValue) - 1);\n\tif (linkLength == -1) {\n\t    Tcl_AppendResult(interp, \"couldn't readlink \\\"\", argv[2],\n\t\t    \"\\\": \", Tcl_UnixError(interp), (char *) NULL);\n\t    return TCL_ERROR;\n\t}\n\tlinkValue[linkLength] = 0;\n\tTcl_SetResult(interp, linkValue, TCL_VOLATILE);\n\treturn TCL_OK;\n#endif\n    } else if ((c == 's') && (strncmp(argv[1], \"size\", length) == 0)\n\t    && (length >= 2)) {\n\tif (argc != 3) {\n\t    argv[1] = \"size\";\n\t    goto not3Args;\n\t}\n\tif (stat(fileName, &statBuf) == -1) {\n\t    goto badStat;\n\t}\n\tsprintf(interp->result, \"%ld\", statBuf.st_size);\n\treturn TCL_OK;\n    } else if ((c == 's') && (strncmp(argv[1], \"stat\", length) == 0)\n\t    && (length >= 2)) {\n\tif (argc != 4) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t    \" stat name varName\\\"\", (char *) NULL);\n\t    return TCL_ERROR;\n\t}\n\n\tif (stat(fileName, &statBuf) == -1) {\n\t    badStat:\n\t    Tcl_AppendResult(interp, \"couldn't stat \\\"\", argv[2],\n\t\t    \"\\\": \", Tcl_UnixError(interp), (char *) NULL);\n\t    return TCL_ERROR;\n\t}\n\treturn StoreStatData(interp, argv[3], &statBuf);\n    } else if ((c == 't') && (strncmp(argv[1], \"type\", length) == 0)\n\t    && (length >= 2)) {\n\tif (argc != 3) {\n\t    argv[1] = \"type\";\n\t    goto not3Args;\n\t}\n\tif (lstat(fileName, &statBuf) == -1) {\n\t    goto badStat;\n\t}\n\tinterp->result = GetFileType((int) statBuf.st_mode);\n\treturn TCL_OK;\n    } else {\n\tTcl_AppendResult(interp, \"bad option \\\"\", argv[1],\n\t\t\"\\\": should be atime, dirname, executable, exists, \",\n\t\t\"extension, isdirectory, isfile, lstat, mtime, owned, \",\n\t\t\"readable, \",\n#ifdef S_IFLNK\n\t\t\"readlink, \",\n#endif\n\t\t\"root, size, stat, tail, type, \",\n\t\t\"or writable\",\n\t\t(char *) NULL);\n\treturn TCL_ERROR;\n    }\n    if (stat(fileName, &statBuf) == -1) {\n\tinterp->result = \"0\";\n\treturn TCL_OK;\n    }\n    switch (statOp) {\n\tcase 0:\n\t    mode = (geteuid() == statBuf.st_uid);\n\t    break;\n\tcase 1:\n\t    mode = S_ISREG(statBuf.st_mode);\n\t    break;\n\tcase 2:\n\t    mode = S_ISDIR(statBuf.st_mode);\n\t    break;\n    }\n    if (mode) {\n\tinterp->result = \"1\";\n    } else {\n\tinterp->result = \"0\";\n    }\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * StoreStatData --\n *\n *\tThis is a utility procedure that breaks out the fields of a\n *\t\"stat\" structure and stores them in textual form into the\n *\telements of an associative array.\n *\n * Results:\n *\tReturns a standard Tcl return value.  If an error occurs then\n *\ta message is left in interp->result.\n *\n * Side effects:\n *\tElements of the associative array given by \"varName\" are modified.\n *\n *----------------------------------------------------------------------\n */\n\nstatic int\nStoreStatData(interp, varName, statPtr)\n    Tcl_Interp *interp;\t\t\t/* Interpreter for error reports. */\n    char *varName;\t\t\t/* Name of associative array variable\n\t\t\t\t\t * in which to store stat results. */\n    struct stat *statPtr;\t\t/* Pointer to buffer containing\n\t\t\t\t\t * stat data to store in varName. */\n{\n    char string[30];\n\n    sprintf(string, \"%d\", statPtr->st_dev);\n    if (Tcl_SetVar2(interp, varName, \"dev\", string, TCL_LEAVE_ERR_MSG)\n\t    == NULL) {\n\treturn TCL_ERROR;\n    }\n    sprintf(string, \"%d\", statPtr->st_ino);\n    if (Tcl_SetVar2(interp, varName, \"ino\", string, TCL_LEAVE_ERR_MSG)\n\t    == NULL) {\n\treturn TCL_ERROR;\n    }\n    sprintf(string, \"%d\", statPtr->st_mode);\n    if (Tcl_SetVar2(interp, varName, \"mode\", string, TCL_LEAVE_ERR_MSG)\n\t    == NULL) {\n\treturn TCL_ERROR;\n    }\n    sprintf(string, \"%d\", statPtr->st_nlink);\n    if (Tcl_SetVar2(interp, varName, \"nlink\", string, TCL_LEAVE_ERR_MSG)\n\t    == NULL) {\n\treturn TCL_ERROR;\n    }\n    sprintf(string, \"%d\", statPtr->st_uid);\n    if (Tcl_SetVar2(interp, varName, \"uid\", string, TCL_LEAVE_ERR_MSG)\n\t    == NULL) {\n\treturn TCL_ERROR;\n    }\n    sprintf(string, \"%d\", statPtr->st_gid);\n    if (Tcl_SetVar2(interp, varName, \"gid\", string, TCL_LEAVE_ERR_MSG)\n\t    == NULL) {\n\treturn TCL_ERROR;\n    }\n    sprintf(string, \"%ld\", statPtr->st_size);\n    if (Tcl_SetVar2(interp, varName, \"size\", string, TCL_LEAVE_ERR_MSG)\n\t    == NULL) {\n\treturn TCL_ERROR;\n    }\n    sprintf(string, \"%ld\", statPtr->st_atime);\n    if (Tcl_SetVar2(interp, varName, \"atime\", string, TCL_LEAVE_ERR_MSG)\n\t    == NULL) {\n\treturn TCL_ERROR;\n    }\n    sprintf(string, \"%ld\", statPtr->st_mtime);\n    if (Tcl_SetVar2(interp, varName, \"mtime\", string, TCL_LEAVE_ERR_MSG)\n\t    == NULL) {\n\treturn TCL_ERROR;\n    }\n    sprintf(string, \"%ld\", statPtr->st_ctime);\n    if (Tcl_SetVar2(interp, varName, \"ctime\", string, TCL_LEAVE_ERR_MSG)\n\t    == NULL) {\n\treturn TCL_ERROR;\n    }\n    if (Tcl_SetVar2(interp, varName, \"type\",\n\t    GetFileType((int) statPtr->st_mode), TCL_LEAVE_ERR_MSG) == NULL) {\n\treturn TCL_ERROR;\n    }\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * GetFileType --\n *\n *\tGiven a mode word, returns a string identifying the type of a\n *\tfile.\n *\n * Results:\n *\tA static text string giving the file type from mode.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nstatic char *\nGetFileType(mode)\n    int mode;\n{\n    if (S_ISREG(mode)) {\n\treturn \"file\";\n    } else if (S_ISDIR(mode)) {\n\treturn \"directory\";\n    } else if (S_ISCHR(mode)) {\n\treturn \"characterSpecial\";\n    } else if (S_ISBLK(mode)) {\n\treturn \"blockSpecial\";\n#ifdef S_ISFIFO\n    } else if (S_ISFIFO(mode)) {\n\treturn \"fifo\";\n#endif\n    } else if (S_ISLNK(mode)) {\n\treturn \"link\";\n    } else if (S_ISSOCK(mode)) {\n\treturn \"socket\";\n    }\n    return \"unknown\";\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_FlushCmd --\n *\n *\tThis procedure is invoked to process the \"flush\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_FlushCmd(notUsed, interp, argc, argv)\n    void *notUsed;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    OpenFile *filePtr;\n    FILE *f;\n\n    if (argc != 2) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" fileId\\\"\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n    if (TclGetOpenFile(interp, argv[1], &filePtr) != TCL_OK) {\n\treturn TCL_ERROR;\n    }\n    if (!filePtr->writable) {\n\tTcl_AppendResult(interp, \"\\\"\", argv[1],\n\t\t\"\\\" wasn't opened for writing\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n    f = filePtr->f2;\n    if (f == NULL) {\n\tf = filePtr->f;\n    }\n    if (fflush(f) == EOF) {\n\tTcl_AppendResult(interp, \"error flushing \\\"\", argv[1],\n\t\t\"\\\": \", Tcl_UnixError(interp), (char *) NULL);\n\tclearerr(f);\n\treturn TCL_ERROR;\n    }\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_GetsCmd --\n *\n *\tThis procedure is invoked to process the \"gets\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_GetsCmd(notUsed, interp, argc, argv)\n    void *notUsed;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n#   define BUF_SIZE 200\n    char buffer[BUF_SIZE+1];\n    int totalCount, done, flags;\n    OpenFile *filePtr;\n    register FILE *f;\n\n    if ((argc != 2) && (argc != 3)) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" fileId ?varName?\\\"\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n    if (TclGetOpenFile(interp, argv[1], &filePtr) != TCL_OK) {\n\treturn TCL_ERROR;\n    }\n    if (!filePtr->readable) {\n\tTcl_AppendResult(interp, \"\\\"\", argv[1],\n\t\t\"\\\" wasn't opened for reading\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n\n    /*\n     * We can't predict how large a line will be, so read it in\n     * pieces, appending to the current result or to a variable.\n     */\n\n    totalCount = 0;\n    done = 0;\n    flags = 0;\n    f = filePtr->f;\n    while (!done) {\n\tregister int c, count;\n\tregister char *p;\n\n\tfor (p = buffer, count = 0; count < BUF_SIZE-1; count++, p++) {\n\t    c = getc(f);\n\t    if (c == EOF) {\n\t\tif (ferror(filePtr->f)) {\n\t\t    Tcl_ResetResult(interp);\n\t\t    Tcl_AppendResult(interp, \"error reading \\\"\", argv[1],\n\t\t\t    \"\\\": \", Tcl_UnixError(interp), (char *) NULL);\n\t\t    clearerr(filePtr->f);\n\t\t    return TCL_ERROR;\n\t\t} else if (feof(filePtr->f)) {\n\t\t    if ((totalCount == 0) && (count == 0)) {\n\t\t\ttotalCount = -1;\n\t\t    }\n\t\t    done = 1;\n\t\t    break;\n\t\t}\n\t    }\n\t    if (c == '\\n') {\n\t\tdone = 1;\n\t\tbreak;\n\t    }\n\t    *p = c;\n\t}\n\t*p = 0;\n\tif (argc == 2) {\n\t    Tcl_AppendResult(interp, buffer, (char *) NULL);\n\t} else {\n\t    if (Tcl_SetVar(interp, argv[2], buffer, flags|TCL_LEAVE_ERR_MSG)\n\t\t    == NULL) {\n\t\treturn TCL_ERROR;\n\t    }\n\t    flags = TCL_APPEND_VALUE;\n\t}\n\ttotalCount += count;\n    }\n\n    if (argc == 3) {\n\tsprintf(interp->result, \"%d\", totalCount);\n    }\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_OpenCmd --\n *\n *\tThis procedure is invoked to process the \"open\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_OpenCmd(notUsed, interp, argc, argv)\n    void *notUsed;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    Interp *iPtr = (Interp *) interp;\n    int pipeline, fd;\n    char *access;\n    register OpenFile *filePtr;\n\n    if (argc == 2) {\n\taccess = \"r\";\n    } else if (argc == 3) {\n\taccess = argv[2];\n    } else {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" filename ?access?\\\"\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n\n    filePtr = (OpenFile *) malloc(sizeof(OpenFile));\n    filePtr->f = NULL;\n    filePtr->f2 = NULL;\n    filePtr->readable = 0;\n    filePtr->writable = 0;\n    filePtr->numPids = 0;\n    filePtr->pidPtr = NULL;\n    filePtr->errorId = -1;\n\n    /*\n     * Verify the requested form of access.\n     */\n\n    pipeline = 0;\n    if (argv[1][0] == '|') {\n\tpipeline = 1;\n    }\n    switch (access[0]) {\n\tcase 'r':\n\t    filePtr->readable = 1;\n\t    break;\n\tcase 'w':\n\t    filePtr->writable = 1;\n\t    break;\n\tcase 'a':\n\t    filePtr->writable = 1;\n\t    break;\n\tdefault:\n\t    badAccess:\n\t    Tcl_AppendResult(interp, \"illegal access mode \\\"\", access,\n\t\t    \"\\\"\", (char *) NULL);\n\t    goto error;\n    }\n    if (access[1] == '+') {\n\tfilePtr->readable = filePtr->writable = 1;\n\tif (access[2] != 0) {\n\t    goto badAccess;\n\t}\n    } else if (access[1] != 0) {\n\tgoto badAccess;\n    }\n\n    /*\n     * Open the file or create a process pipeline.\n     */\n\n    if (!pipeline) {\n\tchar *fileName = argv[1];\n\n\tif (fileName[0] == '~') {\n\t    fileName = Tcl_TildeSubst(interp, fileName);\n\t    if (fileName == NULL) {\n\t\tgoto error;\n\t    }\n\t}\n\tfilePtr->f = fopen(fileName, access);\n\tif (filePtr->f == NULL) {\n\t    Tcl_AppendResult(interp, \"couldn't open \\\"\", argv[1],\n\t\t    \"\\\": \", Tcl_UnixError(interp), (char *) NULL);\n\t    goto error;\n\t}\n    } else {\n\tint *inPipePtr, *outPipePtr;\n\tint cmdArgc, inPipe, outPipe;\n\tunsigned char **cmdArgv;\n\n\tif (Tcl_SplitList(interp, argv[1]+1, &cmdArgc, &cmdArgv) != TCL_OK) {\n\t    goto error;\n\t}\n\tinPipePtr = (filePtr->writable) ? &inPipe : NULL;\n\toutPipePtr = (filePtr->readable) ? &outPipe : NULL;\n\tinPipe = outPipe = -1;\n\tfilePtr->numPids = Tcl_CreatePipeline(interp, cmdArgc, cmdArgv,\n\t\t&filePtr->pidPtr, inPipePtr, outPipePtr, &filePtr->errorId);\n\tfree((char *) cmdArgv);\n\tif (filePtr->numPids < 0) {\n\t    goto error;\n\t}\n\tif (filePtr->readable) {\n\t    if (outPipe == -1) {\n\t\tif (inPipe != -1) {\n\t\t    close(inPipe);\n\t\t}\n\t\tTcl_AppendResult(interp, \"can't read output from command:\",\n\t\t\t\" standard output was redirected\", (char *) NULL);\n\t\tgoto error;\n\t    }\n\t    filePtr->f = fdopen(outPipe, \"r\");\n\t}\n\tif (filePtr->writable) {\n\t    if (inPipe == -1) {\n\t\tTcl_AppendResult(interp, \"can't write input to command:\",\n\t\t\t\" standard input was redirected\", (char *) NULL);\n\t\tgoto error;\n\t    }\n\t    if (filePtr->f != NULL) {\n\t\tfilePtr->f2 = fdopen(inPipe, \"w\");\n\t    } else {\n\t\tfilePtr->f = fdopen(inPipe, \"w\");\n\t    }\n\t}\n    }\n\n    /*\n     * Enter this new OpenFile structure in the table for the\n     * interpreter.  May have to expand the table to do this.\n     */\n\n    fd = fileno(filePtr->f);\n    TclMakeFileTable(iPtr, fd);\n    if (iPtr->filePtrArray[fd] != NULL) {\n\tfprintf (stderr, \"Tcl_OpenCmd found file already open\\n\");\n\tabort();\n    }\n    iPtr->filePtrArray[fd] = filePtr;\n    sprintf(interp->result, \"file%d\", fd);\n    return TCL_OK;\n\n    error:\n    if (filePtr->f != NULL) {\n\tfclose(filePtr->f);\n    }\n    if (filePtr->f2 != NULL) {\n\tfclose(filePtr->f2);\n    }\n    if (filePtr->numPids > 0) {\n\tTcl_DetachPids(filePtr->numPids, filePtr->pidPtr);\n\tfree((char *) filePtr->pidPtr);\n    }\n    if (filePtr->errorId != -1) {\n\tclose(filePtr->errorId);\n    }\n    free((char *) filePtr);\n    return TCL_ERROR;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_PwdCmd --\n *\n *\tThis procedure is invoked to process the \"pwd\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_PwdCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    char buffer[MAXPATHLEN+1];\n\n    if (argc != 1) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\targv[0], \"\\\"\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n    if (currentDir == NULL) {\n#if TCL_GETWD\n\tif (getwd(buffer) == NULL) {\n\t    Tcl_AppendResult(interp, \"error getting working directory name: \",\n\t\t    buffer, (char *) NULL);\n\t    return TCL_ERROR;\n\t}\n#else\n\tif (getwd(buffer) == NULL) {\n\t    if (errno == ERANGE) {\n\t\tinterp->result = \"working directory name is too long\";\n\t    } else {\n\t\tTcl_AppendResult(interp,\n\t\t\t\"error getting working directory name: \",\n\t\t\tTcl_UnixError(interp), (char *) NULL);\n\t    }\n\t    return TCL_ERROR;\n\t}\n#endif\n\tcurrentDir = (char *) malloc((unsigned) (strlen(buffer) + 1));\n\tstrcpy(currentDir, buffer);\n    }\n    interp->result = currentDir;\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_PutsCmd --\n *\n *\tThis procedure is invoked to process the \"puts\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_PutsCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    OpenFile *filePtr;\n    FILE *f;\n    int i, newline;\n    char *fileId;\n\n    i = 1;\n    newline = 1;\n    if ((argc >= 2) && (strcmp(argv[1], \"-nonewline\") == 0)) {\n\tnewline = 0;\n\ti++;\n    }\n    if ((i < (argc-3)) || (i >= argc)) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\"\\\" ?-nonewline? ?fileId? string\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n\n    /*\n     * The code below provides backwards compatibility with an old\n     * form of the command that is no longer recommended or documented.\n     */\n\n    if (i == (argc-3)) {\n\tif (strncmp(argv[i+2], \"nonewline\", strlen(argv[i+2])) != 0) {\n\t    Tcl_AppendResult(interp, \"bad argument \\\"\", argv[i+2],\n\t\t    \"\\\": should be \\\"nonewline\\\"\", (char *) NULL);\n\t    return TCL_ERROR;\n\t}\n\tnewline = 0;\n    }\n    if (i == (argc-1)) {\n\tfileId = \"stdout\";\n    } else {\n\tfileId = argv[i];\n\ti++;\n    }\n\n    if (TclGetOpenFile(interp, fileId, &filePtr) != TCL_OK) {\n\treturn TCL_ERROR;\n    }\n    if (!filePtr->writable) {\n\tTcl_AppendResult(interp, \"\\\"\", fileId,\n\t\t\"\\\" wasn't opened for writing\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n    f = filePtr->f2;\n    if (f == NULL) {\n\tf = filePtr->f;\n    }\n\n    fputs(argv[i], f);\n    if (newline) {\n\tfputc('\\n', f);\n    }\n    if (ferror(f)) {\n\tTcl_AppendResult(interp, \"error writing \\\"\", fileId,\n\t\t\"\\\": \", Tcl_UnixError(interp), (char *) NULL);\n\tclearerr(f);\n\treturn TCL_ERROR;\n    }\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_ReadCmd --\n *\n *\tThis procedure is invoked to process the \"read\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_ReadCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    OpenFile *filePtr;\n    int bytesLeft, bytesRead, count;\n#define READ_BUF_SIZE 4096\n    char buffer[READ_BUF_SIZE+1];\n    int newline, i;\n\n    if ((argc != 2) && (argc != 3)) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" fileId ?numBytes?\\\" or \\\"\", argv[0],\n\t\t\" ?-nonewline? fileId\\\"\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n    i = 1;\n    newline = 1;\n    if ((argc == 3) && (strcmp(argv[1], \"-nonewline\") == 0)) {\n\tnewline = 0;\n\ti++;\n    }\n\n    if (TclGetOpenFile(interp, argv[i], &filePtr) != TCL_OK) {\n\treturn TCL_ERROR;\n    }\n    if (!filePtr->readable) {\n\tTcl_AppendResult(interp, \"\\\"\", argv[i],\n\t\t\"\\\" wasn't opened for reading\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n\n    /*\n     * Compute how many bytes to read, and see whether the final\n     * newline should be dropped.\n     */\n\n    if ((argc >= (i + 2)) && isdigit(argv[i+1][0])) {\n\tif (Tcl_GetInt(interp, argv[i+1], &bytesLeft) != TCL_OK) {\n\t    return TCL_ERROR;\n\t}\n    } else {\n\tbytesLeft = 1<<30;\n\n\t/*\n\t * The code below provides backward compatibility for an\n\t * archaic earlier version of this command.\n\t */\n\n\tif (argc >= (i + 2)) {\n\t    if (strncmp(argv[i+1], \"nonewline\", strlen(argv[i+1])) == 0) {\n\t\tnewline = 0;\n\t    } else {\n\t\tTcl_AppendResult(interp, \"bad argument \\\"\", argv[i+1],\n\t\t\t\"\\\": should be \\\"nonewline\\\"\", (char *) NULL);\n\t\treturn TCL_ERROR;\n\t    }\n\t}\n    }\n\n    /*\n     * Read the file in one or more chunks.\n     */\n\n    bytesRead = 0;\n    while (bytesLeft > 0) {\n\tcount = READ_BUF_SIZE;\n\tif (bytesLeft < READ_BUF_SIZE) {\n\t    count = bytesLeft;\n\t}\n\tcount = fread(buffer, 1, count, filePtr->f);\n\tif (ferror(filePtr->f)) {\n\t    Tcl_ResetResult(interp);\n\t    Tcl_AppendResult(interp, \"error reading \\\"\", argv[i],\n\t\t    \"\\\": \", Tcl_UnixError(interp), (char *) NULL);\n\t    clearerr(filePtr->f);\n\t    return TCL_ERROR;\n\t}\n\tif (count == 0) {\n\t    break;\n\t}\n\tbuffer[count] = 0;\n\tTcl_AppendResult(interp, buffer, (char *) NULL);\n\tbytesLeft -= count;\n\tbytesRead += count;\n    }\n    if ((newline == 0) && (bytesRead > 0)\n\t    && (interp->result[bytesRead-1] == '\\n')) {\n\tinterp->result[bytesRead-1] = 0;\n    }\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_SeekCmd --\n *\n *\tThis procedure is invoked to process the \"seek\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_SeekCmd(notUsed, interp, argc, argv)\n    void *notUsed;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    OpenFile *filePtr;\n    int offset, mode;\n\n    if ((argc != 3) && (argc != 4)) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" fileId offset ?origin?\\\"\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n    if (TclGetOpenFile(interp, argv[1], &filePtr) != TCL_OK) {\n\treturn TCL_ERROR;\n    }\n    if (Tcl_GetInt(interp, argv[2], &offset) != TCL_OK) {\n\treturn TCL_ERROR;\n    }\n    mode = SEEK_SET;\n    if (argc == 4) {\n\tint length;\n\tchar c;\n\n\tlength = strlen(argv[3]);\n\tc = argv[3][0];\n\tif ((c == 's') && (strncmp(argv[3], \"start\", length) == 0)) {\n\t    mode = SEEK_SET;\n\t} else if ((c == 'c') && (strncmp(argv[3], \"current\", length) == 0)) {\n\t    mode = SEEK_CUR;\n\t} else if ((c == 'e') && (strncmp(argv[3], \"end\", length) == 0)) {\n\t    mode = SEEK_END;\n\t} else {\n\t    Tcl_AppendResult(interp, \"bad origin \\\"\", argv[3],\n\t\t    \"\\\": should be start, current, or end\", (char *) NULL);\n\t    return TCL_ERROR;\n\t}\n    }\n    if (fseek(filePtr->f, (long) offset, mode) == -1) {\n\tTcl_AppendResult(interp, \"error during seek: \",\n\t\tTcl_UnixError(interp), (char *) NULL);\n\tclearerr(filePtr->f);\n\treturn TCL_ERROR;\n    }\n\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_SourceCmd --\n *\n *\tThis procedure is invoked to process the \"source\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_SourceCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    if (argc != 2) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" fileName\\\"\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n    return Tcl_EvalFile(interp, argv[1]);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_TellCmd --\n *\n *\tThis procedure is invoked to process the \"tell\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_TellCmd(notUsed, interp, argc, argv)\n    void *notUsed;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    OpenFile *filePtr;\n\n    if (argc != 2) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" fileId\\\"\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n    if (TclGetOpenFile(interp, argv[1], &filePtr) != TCL_OK) {\n\treturn TCL_ERROR;\n    }\n    sprintf(interp->result, \"%ld\", ftell(filePtr->f));\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_TimeCmd --\n *\n *\tThis procedure is invoked to process the \"time\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_TimeCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int count, i, result;\n    double timePer;\n    struct timeval start, stop;\n    struct timezone tz;\n    int micros;\n\n    if (argc == 2) {\n\tcount = 1;\n    } else if (argc == 3) {\n\tif (Tcl_GetInt(interp, argv[2], &count) != TCL_OK) {\n\t    return TCL_ERROR;\n\t}\n    } else {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" command ?count?\\\"\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n    gettimeofday(&start, &tz);\n    for (i = count ; i > 0; i--) {\n\tresult = Tcl_Eval(interp, argv[1], 0, NULL);\n\tif (result != TCL_OK) {\n\t    if (result == TCL_ERROR) {\n\t\tchar msg[60];\n\t\tsprintf(msg, \"\\n    (\\\"time\\\" body line %d)\",\n\t\t\tinterp->errorLine);\n\t\tTcl_AddErrorInfo(interp, msg);\n\t    }\n\t    return result;\n\t}\n    }\n    gettimeofday(&stop, &tz);\n    micros = (stop.tv_sec - start.tv_sec)*1000000\n\t    + (stop.tv_usec - start.tv_usec);\n    timePer = micros;\n\n    Tcl_ResetResult(interp);\n    sprintf(interp->result, \"%.0f microseconds per iteration\", timePer/count);\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * CleanupChildren --\n *\n *\tThis is a utility procedure used to wait for child processes\n *\tto exit, record information about abnormal exits, and then\n *\tcollect any stderr output generated by them.\n *\n * Results:\n *\tThe return value is a standard Tcl result.  If anything at\n *\tweird happened with the child processes, TCL_ERROR is returned\n *\tand a message is left in interp->result.\n *\n * Side effects:\n *\tIf the last character of interp->result is a newline, then it\n *\tis removed.  File errorId gets closed, and pidPtr is freed\n *\tback to the storage allocator.\n *\n *----------------------------------------------------------------------\n */\n\nstatic int\nCleanupChildren(interp, numPids, pidPtr, errorId)\n    Tcl_Interp *interp;\t\t/* Used for error messages. */\n    int numPids;\t\t/* Number of entries in pidPtr array. */\n    int *pidPtr;\t\t/* Array of process ids of children. */\n    int errorId;\t\t/* File descriptor index for file containing\n\t\t\t\t * stderr output from pipeline.  -1 means\n\t\t\t\t * there isn't any stderr output. */\n{\n    int result = TCL_OK;\n    int i, pid, length;\n#define WAIT_STATUS_TYPE int\n    WAIT_STATUS_TYPE waitStatus;\n\n    for (i = 0; i < numPids; i++) {\n\tpid = Tcl_WaitPids(1, &pidPtr[i], (int *) &waitStatus);\n\tif (pid == -1) {\n\t    Tcl_AppendResult(interp, \"error waiting for process to exit: \",\n\t\t    Tcl_UnixError(interp), (char *) NULL);\n\t    continue;\n\t}\n\n\t/*\n\t * Create error messages for unusual process exits.  An\n\t * extra newline gets appended to each error message, but\n\t * it gets removed below (in the same fashion that an\n\t * extra newline in the command's output is removed).\n\t */\n\n\tif (!WIFEXITED(waitStatus) || (WEXITSTATUS(waitStatus) != 0)) {\n\t    char msg1[20], msg2[20];\n\n\t    result = TCL_ERROR;\n\t    sprintf(msg1, \"%d\", pid);\n\t    if (WIFEXITED(waitStatus)) {\n\t\tsprintf(msg2, \"%d\", WEXITSTATUS(waitStatus));\n\t\tTcl_SetErrorCode(interp, \"CHILDSTATUS\", msg1, msg2,\n\t\t\t(char *) NULL);\n\t    } else if (WIFSIGNALED(waitStatus)) {\n\t\tchar *p;\n\n\t\tp = Tcl_SignalMsg((int) (WTERMSIG(waitStatus)));\n\t\tTcl_SetErrorCode(interp, \"CHILDKILLED\", msg1,\n\t\t\tTcl_SignalId((int) (WTERMSIG(waitStatus))), p,\n\t\t\t(char *) NULL);\n\t\tTcl_AppendResult(interp, \"child killed: \", p, \"\\n\",\n\t\t\t(char *) NULL);\n\t    } else if (WIFSTOPPED(waitStatus)) {\n\t\tchar *p;\n\n\t\tp = Tcl_SignalMsg((int) (WSTOPSIG(waitStatus)));\n\t\tTcl_SetErrorCode(interp, \"CHILDSUSP\", msg1,\n\t\t\tTcl_SignalId((int) (WSTOPSIG(waitStatus))), p, (char *) NULL);\n\t\tTcl_AppendResult(interp, \"child suspended: \", p, \"\\n\",\n\t\t\t(char *) NULL);\n\t    } else {\n\t\tTcl_AppendResult(interp,\n\t\t\t\"child wait status didn't make sense\\n\",\n\t\t\t(char *) NULL);\n\t    }\n\t}\n    }\n    free((char *) pidPtr);\n\n    /*\n     * Read the standard error file.  If there's anything there,\n     * then return an error and add the file's contents to the result\n     * string.\n     */\n\n    if (errorId >= 0) {\n\twhile (1) {\n#\t    define BUFFER_SIZE 1000\n\t    char buffer[BUFFER_SIZE+1];\n\t    int count;\n\n\t    count = read(errorId, buffer, BUFFER_SIZE);\n\n\t    if (count == 0) {\n\t\tbreak;\n\t    }\n\t    if (count < 0) {\n\t\tTcl_AppendResult(interp,\n\t\t\t\"error reading stderr output file: \",\n\t\t\tTcl_UnixError(interp), (char *) NULL);\n\t\tbreak;\n\t    }\n\t    buffer[count] = 0;\n\t    Tcl_AppendResult(interp, buffer, (char *) NULL);\n\t}\n\tclose(errorId);\n    }\n\n    /*\n     * If the last character of interp->result is a newline, then remove\n     * the newline character (the newline would just confuse things).\n     */\n\n    length = strlen(interp->result);\n    if ((length > 0) && (interp->result[length-1] == '\\n')) {\n\tinterp->result[length-1] = '\\0';\n    }\n\n    return result;\n}\n"
  },
  {
    "path": "lib/libtcl/tclutil.c",
    "content": "/*\n * tclUtil.c --\n *\n *\tThis file contains utility procedures that are used by many Tcl\n *\tcommands.\n *\n * Copyright 1987-1991 Regents of the University of California\n * Permission to use, copy, modify, and distribute this\n * software and its documentation for any purpose and without\n * fee is hereby granted, provided that the above copyright\n * notice appear in all copies.  The University of California\n * makes no representations about the suitability of this\n * software for any purpose.  It is provided \"as is\" without\n * express or implied warranty.\n */\n#include \"internal.h\"\n#include \"regexp.h\"\n#include <stdarg.h>\n\n/*\n * The following values are used in the flags returned by Tcl_ScanElement\n * and used by Tcl_ConvertElement.  The value TCL_DONT_USE_BRACES is also\n * defined in tcl.h;  make sure its value doesn't overlap with any of the\n * values below.\n *\n * TCL_DONT_USE_BRACES -\t1 means the string mustn't be enclosed in\n *\t\t\t\tbraces (e.g. it contains unmatched braces,\n *\t\t\t\tor ends in a backslash character, or user\n *\t\t\t\tjust doesn't want braces);  handle all\n *\t\t\t\tspecial characters by adding backslashes.\n * USE_BRACES -\t\t\t1 means the string contains a special\n *\t\t\t\tcharacter that can be handled simply by\n *\t\t\t\tenclosing the entire argument in braces.\n * BRACES_UNMATCHED -\t\t1 means that braces aren't properly matched\n *\t\t\t\tin the argument.\n */\n\n#define USE_BRACES\t\t2\n#define BRACES_UNMATCHED\t4\n\n/*\n * Function prototypes for local procedures in this file:\n */\n\nstatic void\t\tSetupAppendBuffer (Interp *iPtr, int newSpace);\n\f\n/*\n *----------------------------------------------------------------------\n *\n * TclFindElement --\n *\n *\tGiven a pointer into a Tcl list, locate the first (or next)\n *\telement in the list.\n *\n * Results:\n *\tThe return value is normally TCL_OK, which means that the\n *\telement was successfully located.  If TCL_ERROR is returned\n *\tit means that list didn't have proper list structure;\n *\tinterp->result contains a more detailed error message.\n *\n *\tIf TCL_OK is returned, then *elementPtr will be set to point\n *\tto the first element of list, and *nextPtr will be set to point\n *\tto the character just after any white space following the last\n *\tcharacter that's part of the element.  If this is the last argument\n *\tin the list, then *nextPtr will point to the NULL character at the\n *\tend of list.  If sizePtr is non-NULL, *sizePtr is filled in with\n *\tthe number of characters in the element.  If the element is in\n *\tbraces, then *elementPtr will point to the character after the\n *\topening brace and *sizePtr will not include either of the braces.\n *\tIf there isn't an element in the list, *sizePtr will be zero, and\n *\tboth *elementPtr and *termPtr will refer to the null character at\n *\tthe end of list.  Note:  this procedure does NOT collapse backslash\n *\tsequences.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTclFindElement(interp, list, elementPtr, nextPtr, sizePtr, bracePtr)\n    Tcl_Interp *interp;\t\t/* Interpreter to use for error reporting. */\n    register unsigned char *list; /* String containing Tcl list with zero\n\t\t\t\t * or more elements (possibly in braces). */\n    unsigned char **elementPtr;\t/* Fill in with location of first significant\n\t\t\t\t * character in first element of list. */\n    unsigned char **nextPtr;\t/* Fill in with location of character just\n\t\t\t\t * after all white space following end of\n\t\t\t\t * argument (i.e. next argument or end of\n\t\t\t\t * list). */\n    int *sizePtr;\t\t/* If non-zero, fill in with size of\n\t\t\t\t * element. */\n    int *bracePtr;\t\t/* If non-zero fill in with non-zero/zero\n\t\t\t\t * to indicate that arg was/wasn't\n\t\t\t\t * in braces. */\n{\n    register unsigned char *p;\n    int openBraces = 0;\n    int inQuotes = 0;\n    int size;\n\n    /*\n     * Skim off leading white space and check for an opening brace or quote.\n     */\n    while (isspace (*list)) {\n\tlist++;\n    }\n    if (*list == '{') {\n\topenBraces = 1;\n\tlist++;\n    } else if (*list == '\"') {\n\tinQuotes = 1;\n\tlist++;\n    }\n    if (bracePtr != 0) {\n\t*bracePtr = openBraces;\n    }\n    p = list;\n\n    /*\n     * Find the end of the element (either a space or a close brace or\n     * the end of the string).\n     */\n\n    while (1) {\n\tswitch (*p) {\n\n\t    /*\n\t     * Open brace: don't treat specially unless the element is\n\t     * in braces.  In this case, keep a nesting count.\n\t     */\n\n\t    case '{':\n\t\tif (openBraces != 0) {\n\t\t    openBraces++;\n\t\t}\n\t\tbreak;\n\n\t    /*\n\t     * Close brace: if element is in braces, keep nesting\n\t     * count and quit when the last close brace is seen.\n\t     */\n\n\t    case '}':\n\t\tif (openBraces == 1) {\n\t\t    unsigned char *p2;\n\n\t\t    size = p - list;\n\t\t    p++;\n\t\t    if ((isspace (*p)) || (*p == 0)) {\n\t\t\tgoto done;\n\t\t    }\n\t\t    for (p2 = p; (*p2 != 0) && (!isspace(*p2)) && (p2 < p+20);\n\t\t\t    p2++) {\n\t\t\t/* null body */\n\t\t    }\n\t\t    Tcl_ResetResult(interp);\n\t\t    sprintf(interp->result,\n\t\t\t    \"list element in braces followed by \\\"%.*s\\\" instead of space\",\n\t\t\t    (int) (p2 - p), p);\n\t\t    return TCL_ERROR;\n\t\t} else if (openBraces != 0) {\n\t\t    openBraces--;\n\t\t}\n\t\tbreak;\n\n\t    /*\n\t     * Backslash:  skip over everything up to the end of the\n\t     * backslash sequence.\n\t     */\n\n\t    case '\\\\': {\n\t\tint size;\n\n\t\t(void) Tcl_Backslash(p, &size);\n\t\tp += size - 1;\n\t\tbreak;\n\t    }\n\n\t    /*\n\t     * Space: ignore if element is in braces or quotes;  otherwise\n\t     * terminate element.\n\t     */\n\n\t    case ' ':\n\t    case '\\f':\n\t    case '\\n':\n\t    case '\\r':\n\t    case '\\t':\n\t    case '\\v':\n\t\tif ((openBraces == 0) && !inQuotes) {\n\t\t    size = p - list;\n\t\t    goto done;\n\t\t}\n\t\tbreak;\n\n\t    /*\n\t     * Double-quote:  if element is in quotes then terminate it.\n\t     */\n\n\t    case '\"':\n\t\tif (inQuotes) {\n\t\t    unsigned char *p2;\n\n\t\t    size = p-list;\n\t\t    p++;\n\t\t    if (isspace (*p) || (*p == 0)) {\n\t\t\tgoto done;\n\t\t    }\n\t\t    for (p2 = p; (*p2 != 0) && (!isspace(*p2)) && (p2 < p+20);\n\t\t\t    p2++) {\n\t\t\t/* null body */\n\t\t    }\n\t\t    Tcl_ResetResult(interp);\n\t\t    sprintf(interp->result,\n\t\t\t    \"list element in quotes followed by \\\"%.*s\\\" %s\",\n\t\t\t    (int) (p2 - p), p, \"instead of space\");\n\t\t    return TCL_ERROR;\n\t\t}\n\t\tbreak;\n\n\t    /*\n\t     * End of list:  terminate element.\n\t     */\n\n\t    case 0:\n\t\tif (openBraces != 0) {\n\t\t    Tcl_SetResult(interp, (unsigned char*) \"unmatched open brace in list\",\n\t\t\t    TCL_STATIC);\n\t\t    return TCL_ERROR;\n\t\t} else if (inQuotes) {\n\t\t    Tcl_SetResult(interp, (unsigned char*) \"unmatched open quote in list\",\n\t\t\t    TCL_STATIC);\n\t\t    return TCL_ERROR;\n\t\t}\n\t\tsize = p - list;\n\t\tgoto done;\n\n\t}\n\tp++;\n    }\n\n    done:\n    while (isspace (*p)) {\n\tp++;\n    }\n    *elementPtr = list;\n    *nextPtr = p;\n    if (sizePtr != 0) {\n\t*sizePtr = size;\n    }\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * TclCopyAndCollapse --\n *\n *\tCopy a string and eliminate any backslashes that aren't in braces.\n *\n * Results:\n *\tThere is no return value.  Count chars. get copied from src\n *\tto dst.  Along the way, if backslash sequences are found outside\n *\tbraces, the backslashes are eliminated in the copy.\n *\tAfter scanning count chars. from source, a null character is\n *\tplaced at the end of dst.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nvoid\nTclCopyAndCollapse(count, src, dst)\n    int count;\t\t\t/* Total number of characters to copy\n\t\t\t\t * from src. */\n    register unsigned char *src; /* Copy from here... */\n    register unsigned char *dst; /* ... to here. */\n{\n    register char c;\n    int numRead;\n\n    for (c = *src; count > 0; src++, c = *src, count--) {\n\tif (c == '\\\\') {\n\t    *dst = Tcl_Backslash(src, &numRead);\n\t    if (*dst != 0) {\n\t\tdst++;\n\t    }\n\t    src += numRead-1;\n\t    count -= numRead-1;\n\t} else {\n\t    *dst = c;\n\t    dst++;\n\t}\n    }\n    *dst = 0;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_SplitList --\n *\n *\tSplits a list up into its constituent fields.\n *\n * Results\n *\tThe return value is normally TCL_OK, which means that\n *\tthe list was successfully split up.  If TCL_ERROR is\n *\treturned, it means that \"list\" didn't have proper list\n *\tstructure;  interp->result will contain a more detailed\n *\terror message.\n *\n *\t*argvPtr will be filled in with the address of an array\n *\twhose elements point to the elements of list, in order.\n *\t*argcPtr will get filled in with the number of valid elements\n *\tin the array.  A single block of memory is dynamically allocated\n *\tto hold both the argv array and a copy of the list (with\n *\tbackslashes and braces removed in the standard way).\n *\tThe caller must eventually free this memory by calling free()\n *\ton *argvPtr.  Note:  *argvPtr and *argcPtr are only modified\n *\tif the procedure returns normally.\n *\n * Side effects:\n *\tMemory is allocated.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTcl_SplitList(interp, list, argcPtr, argvPtr)\n    Tcl_Interp *interp;\t\t/* Interpreter to use for error reporting. */\n    unsigned char *list;\t/* Pointer to string with list structure. */\n    int *argcPtr;\t\t/* Pointer to location to fill in with\n\t\t\t\t * the number of elements in the list. */\n    unsigned char ***argvPtr;\t/* Pointer to place to store pointer to array\n\t\t\t\t * of pointers to list elements. */\n{\n    unsigned char **argv;\n    register unsigned char *p;\n    int size, i, result, elSize, brace;\n    unsigned char *element;\n\n    /*\n     * Figure out how much space to allocate.  There must be enough\n     * space for both the array of pointers and also for a copy of\n     * the list.  To estimate the number of pointers needed, count\n     * the number of space characters in the list.\n     */\n\n    for (size = 1, p = list; *p != 0; p++) {\n\tif (isspace(*p)) {\n\t    size++;\n\t}\n    }\n    size++;\t\t\t/* Leave space for final NULL pointer. */\n    argv = (unsigned char**) malloc ((unsigned)\n\t    ((size * sizeof(char *)) + (p - list) + 1));\n    for (i = 0, p = ((unsigned char *) argv) + size*sizeof(char *);\n\t    *list != 0; i++) {\n\tresult = TclFindElement(interp, list, &element, &list, &elSize, &brace);\n\tif (result != TCL_OK) {\n\t    free (argv);\n\t    return result;\n\t}\n\tif (*element == 0) {\n\t    break;\n\t}\n\tif (i >= size) {\n\t    free (argv);\n\t    Tcl_SetResult(interp, (unsigned char*) \"internal error in Tcl_SplitList\",\n\t\t    TCL_STATIC);\n\t    return TCL_ERROR;\n\t}\n\targv[i] = p;\n\tif (brace) {\n\t    strncpy(p, element, elSize);\n\t    p += elSize;\n\t    *p = 0;\n\t    p++;\n\t} else {\n\t    TclCopyAndCollapse(elSize, element, p);\n\t    p += elSize+1;\n\t}\n    }\n\n    argv[i] = 0;\n    *argvPtr = argv;\n    *argcPtr = i;\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_ScanElement --\n *\n *\tThis procedure is a companion procedure to Tcl_ConvertElement.\n *\tIt scans a string to see what needs to be done to it (e.g.\n *\tadd backslashes or enclosing braces) to make the string into\n *\ta valid Tcl list element.\n *\n * Results:\n *\tThe return value is an overestimate of the number of characters\n *\tthat will be needed by Tcl_ConvertElement to produce a valid\n *\tlist element from string.  The word at *flagPtr is filled in\n *\twith a value needed by Tcl_ConvertElement when doing the actual\n *\tconversion.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTcl_ScanElement(string, flagPtr)\n    unsigned char *string;\t/* String to convert to Tcl list element. */\n    int *flagPtr;\t\t/* Where to store information to guide\n\t\t\t\t * Tcl_ConvertElement. */\n{\n    int flags, nestingLevel;\n    register unsigned char *p;\n\n    /*\n     * This procedure and Tcl_ConvertElement together do two things:\n     *\n     * 1. They produce a proper list, one that will yield back the\n     * argument strings when evaluated or when disassembled with\n     * Tcl_SplitList.  This is the most important thing.\n     *\n     * 2. They try to produce legible output, which means minimizing the\n     * use of backslashes (using braces instead).  However, there are\n     * some situations where backslashes must be used (e.g. an element\n     * like \"{abc\": the leading brace will have to be backslashed.  For\n     * each element, one of three things must be done:\n     *\n     * (a) Use the element as-is (it doesn't contain anything special\n     * characters).  This is the most desirable option.\n     *\n     * (b) Enclose the element in braces, but leave the contents alone.\n     * This happens if the element contains embedded space, or if it\n     * contains characters with special interpretation ($, [, ;, or \\),\n     * or if it starts with a brace or double-quote, or if there are\n     * no characters in the element.\n     *\n     * (c) Don't enclose the element in braces, but add backslashes to\n     * prevent special interpretation of special characters.  This is a\n     * last resort used when the argument would normally fall under case\n     * (b) but contains unmatched braces.  It also occurs if the last\n     * character of the argument is a backslash or if the element contains\n     * a backslash followed by newline.\n     *\n     * The procedure figures out how many bytes will be needed to store\n     * the result (actually, it overestimates).  It also collects information\n     * about the element in the form of a flags word.\n     */\n\n    nestingLevel = 0;\n    flags = 0;\n    if (string == 0) {\n\tstring = (unsigned char*) \"\";\n    }\n    p = string;\n    if ((*p == '{') || (*p == '\"') || (*p == 0)) {\n\tflags |= USE_BRACES;\n    }\n    for ( ; *p != 0; p++) {\n\tswitch (*p) {\n\t    case '{':\n\t\tnestingLevel++;\n\t\tbreak;\n\t    case '}':\n\t\tnestingLevel--;\n\t\tif (nestingLevel < 0) {\n\t\t    flags |= TCL_DONT_USE_BRACES|BRACES_UNMATCHED;\n\t\t}\n\t\tbreak;\n\t    case '[':\n\t    case '$':\n\t    case ';':\n\t    case ' ':\n\t    case '\\f':\n\t    case '\\n':\n\t    case '\\r':\n\t    case '\\t':\n\t    case '\\v':\n\t\tflags |= USE_BRACES;\n\t\tbreak;\n\t    case '\\\\':\n\t\tif ((p[1] == 0) || (p[1] == '\\n')) {\n\t\t    flags = TCL_DONT_USE_BRACES;\n\t\t} else {\n\t\t    int size;\n\n\t\t    (void) Tcl_Backslash(p, &size);\n\t\t    p += size-1;\n\t\t    flags |= USE_BRACES;\n\t\t}\n\t\tbreak;\n\t}\n    }\n    if (nestingLevel != 0) {\n\tflags = TCL_DONT_USE_BRACES | BRACES_UNMATCHED;\n    }\n    *flagPtr = flags;\n\n    /*\n     * Allow enough space to backslash every character plus leave\n     * two spaces for braces.\n     */\n\n    return 2*(p-string) + 2;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_ConvertElement --\n *\n *\tThis is a companion procedure to Tcl_ScanElement.  Given the\n *\tinformation produced by Tcl_ScanElement, this procedure converts\n *\ta string to a list element equal to that string.\n *\n * Results:\n *\tInformation is copied to *dst in the form of a list element\n *\tidentical to src (i.e. if Tcl_SplitList is applied to dst it\n *\twill produce a string identical to src).  The return value is\n *\ta count of the number of characters copied (not including the\n *\tterminating NULL character).\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTcl_ConvertElement(src, dst, flags)\n    register unsigned char *src; /* Source information for list element. */\n    unsigned char *dst;\t\t/* Place to put list-ified element. */\n    int flags;\t\t\t/* Flags produced by Tcl_ScanElement. */\n{\n    register unsigned char *p = dst;\n\n    /*\n     * See the comment block at the beginning of the Tcl_ScanElement\n     * code for details of how this works.\n     */\n\n    if (src == 0) {\n\tsrc = (unsigned char*) \"\";\n    }\n    if ((flags & USE_BRACES) && !(flags & TCL_DONT_USE_BRACES)) {\n\t*p = '{';\n\tp++;\n\tfor ( ; *src != 0; src++, p++) {\n\t    *p = *src;\n\t}\n\t*p = '}';\n\tp++;\n    } else if (*src == 0) {\n\t/*\n\t * If string is empty but can't use braces, then use special\n\t * backslash sequence that maps to empty string.\n\t */\n\n\tp[0] = '\\\\';\n\tp[1] = '0';\n\tp += 2;\n    } else {\n\tfor (; *src != 0 ; src++) {\n\t    switch (*src) {\n\t\tcase ']':\n\t\tcase '[':\n\t\tcase '$':\n\t\tcase ';':\n\t\tcase ' ':\n\t\tcase '\\\\':\n\t\tcase '\"':\n\t\t    *p = '\\\\';\n\t\t    p++;\n\t\t    break;\n\t\tcase '{':\n\t\tcase '}':\n\t\t    if (flags & BRACES_UNMATCHED) {\n\t\t\t*p = '\\\\';\n\t\t\tp++;\n\t\t    }\n\t\t    break;\n\t\tcase '\\f':\n\t\t    *p = '\\\\';\n\t\t    p++;\n\t\t    *p = 'f';\n\t\t    p++;\n\t\t    continue;\n\t\tcase '\\n':\n\t\t    *p = '\\\\';\n\t\t    p++;\n\t\t    *p = 'n';\n\t\t    p++;\n\t\t    continue;\n\t\tcase '\\r':\n\t\t    *p = '\\\\';\n\t\t    p++;\n\t\t    *p = 'r';\n\t\t    p++;\n\t\t    continue;\n\t\tcase '\\t':\n\t\t    *p = '\\\\';\n\t\t    p++;\n\t\t    *p = 't';\n\t\t    p++;\n\t\t    continue;\n\t\tcase '\\v':\n\t\t    *p = '\\\\';\n\t\t    p++;\n\t\t    *p = 'v';\n\t\t    p++;\n\t\t    continue;\n\t    }\n\t    *p = *src;\n\t    p++;\n\t}\n    }\n    *p = '\\0';\n    return p-dst;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_Merge --\n *\n *\tGiven a collection of strings, merge them together into a\n *\tsingle string that has proper Tcl list structured (i.e.\n *\tTcl_SplitList may be used to retrieve strings equal to the\n *\toriginal elements, and Tcl_Eval will parse the string back\n *\tinto its original elements).\n *\n * Results:\n *\tThe return value is the address of a dynamically-allocated\n *\tstring containing the merged list.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\nunsigned char *\nTcl_Merge (int argc,\t\t/* How many strings to merge. */\n\tunsigned char **argv)\t/* Array of string values. */\n{\n#   define LOCAL_SIZE 20\n    int localFlags[LOCAL_SIZE], *flagPtr;\n    int numChars;\n    unsigned char *result;\n    register unsigned char *dst;\n    int i;\n\n    /*\n     * Pass 1: estimate space, gather flags.\n     */\n\n    if (argc <= LOCAL_SIZE) {\n\tflagPtr = localFlags;\n    } else {\n\tflagPtr = (int*) malloc ((unsigned) argc*sizeof(int));\n    }\n    numChars = 1;\n    for (i = 0; i < argc; i++) {\n\tnumChars += Tcl_ScanElement(argv[i], &flagPtr[i]) + 1;\n    }\n\n    /*\n     * Pass two: copy into the result area.\n     */\n\n    result = malloc (numChars);\n    dst = result;\n    for (i = 0; i < argc; i++) {\n\tnumChars = Tcl_ConvertElement(argv[i], dst, flagPtr[i]);\n\tdst += numChars;\n\t*dst = ' ';\n\tdst++;\n    }\n    if (dst == result) {\n\t*dst = 0;\n    } else {\n\tdst[-1] = 0;\n    }\n\n    if (flagPtr != localFlags) {\n\tfree (flagPtr);\n    }\n    return result;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_Concat --\n *\n *\tConcatenate a set of strings into a single large string.\n *\n * Results:\n *\tThe return value is dynamically-allocated string containing\n *\ta concatenation of all the strings in argv, with spaces between\n *\tthe original argv elements.\n *\n * Side effects:\n *\tMemory is allocated for the result;  the caller is responsible\n *\tfor freeing the memory.\n *\n *----------------------------------------------------------------------\n */\n\nunsigned char *\nTcl_Concat (int argc,\t\t/* Number of strings to concatenate. */\n\tunsigned char **argv)\t/* Array of strings to concatenate. */\n{\n    int totalSize, i;\n    register unsigned char *p;\n    unsigned char *result;\n\n    for (totalSize = 1, i = 0; i < argc; i++) {\n\ttotalSize += strlen(argv[i]) + 1;\n    }\n    result = malloc (totalSize);\n    if (argc == 0) {\n\t*result = '\\0';\n\treturn result;\n    }\n    for (p = result, i = 0; i < argc; i++) {\n\tunsigned char *element;\n\tint length;\n\n\t/*\n\t * Clip white space off the front and back of the string\n\t * to generate a neater result, and ignore any empty\n\t * elements.\n\t */\n\n\telement = argv[i];\n\twhile (isspace(*element)) {\n\t    element++;\n\t}\n\tfor (length = strlen(element);\n\t\t(length > 0) && (isspace(element[length-1]));\n\t\tlength--) {\n\t    /* Null loop body. */\n\t}\n\tif (length == 0) {\n\t    continue;\n\t}\n\t(void) strncpy(p, element, length);\n\tp += length;\n\t*p = ' ';\n\tp++;\n    }\n    if (p != result) {\n\tp[-1] = 0;\n    } else {\n\t*p = 0;\n    }\n    return result;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_StringMatch --\n *\n *\tSee if a particular string matches a particular pattern.\n *\n * Results:\n *\tThe return value is 1 if string matches pattern, and\n *\t0 otherwise.  The matching operation permits the following\n *\tspecial characters in the pattern: *?\\[] (see the manual\n *\tentry for details on what these mean).\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTcl_StringMatch(string, pattern)\n    register unsigned char *string;\t/* String. */\n    register unsigned char *pattern;\t/* Pattern, which may contain\n\t\t\t\t\t * special characters. */\n{\n    char c2;\n\n    while (1) {\n\t/* See if we're at the end of both the pattern and the string.\n\t * If so, we succeeded.  If we're at the end of the pattern\n\t * but not at the end of the string, we failed.\n\t */\n\n\tif (*pattern == 0) {\n\t    if (*string == 0) {\n\t\treturn 1;\n\t    } else {\n\t\treturn 0;\n\t    }\n\t}\n\tif ((*string == 0) && (*pattern != '*')) {\n\t    return 0;\n\t}\n\n\t/* Check for a \"*\" as the next pattern character.  It matches\n\t * any substring.  We handle this by calling ourselves\n\t * recursively for each postfix of string, until either we\n\t * match or we reach the end of the string.\n\t */\n\n\tif (*pattern == '*') {\n\t    pattern += 1;\n\t    if (*pattern == 0) {\n\t\treturn 1;\n\t    }\n\t    while (1) {\n\t\tif (Tcl_StringMatch(string, pattern)) {\n\t\t    return 1;\n\t\t}\n\t\tif (*string == 0) {\n\t\t    return 0;\n\t\t}\n\t\tstring += 1;\n\t    }\n\t}\n\n\t/* Check for a \"?\" as the next pattern character.  It matches\n\t * any single character.\n\t */\n\n\tif (*pattern == '?') {\n\t    goto thisCharOK;\n\t}\n\n\t/* Check for a \"[\" as the next pattern character.  It is followed\n\t * by a list of characters that are acceptable, or by a range\n\t * (two characters separated by \"-\").\n\t */\n\n\tif (*pattern == '[') {\n\t    pattern += 1;\n\t    while (1) {\n\t\tif ((*pattern == ']') || (*pattern == 0)) {\n\t\t    return 0;\n\t\t}\n\t\tif (*pattern == *string) {\n\t\t    break;\n\t\t}\n\t\tif (pattern[1] == '-') {\n\t\t    c2 = pattern[2];\n\t\t    if (c2 == 0) {\n\t\t\treturn 0;\n\t\t    }\n\t\t    if ((*pattern <= *string) && (c2 >= *string)) {\n\t\t\tbreak;\n\t\t    }\n\t\t    if ((*pattern >= *string) && (c2 <= *string)) {\n\t\t\tbreak;\n\t\t    }\n\t\t    pattern += 2;\n\t\t}\n\t\tpattern += 1;\n\t    }\n\t    while ((*pattern != ']') && (*pattern != 0)) {\n\t\tpattern += 1;\n\t    }\n\t    goto thisCharOK;\n\t}\n\n\t/* If the next pattern character is '/', just strip off the '/'\n\t * so we do exact matching on the character that follows.\n\t */\n\n\tif (*pattern == '\\\\') {\n\t    pattern += 1;\n\t    if (*pattern == 0) {\n\t\treturn 0;\n\t    }\n\t}\n\n\t/* There's no special character.  Just make sure that the next\n\t * characters of each string match.\n\t */\n\n\tif (*pattern != *string) {\n\t    return 0;\n\t}\n\n\tthisCharOK: pattern += 1;\n\tstring += 1;\n    }\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_SetResult --\n *\n *\tArrange for \"string\" to be the Tcl return value.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tinterp->result is left pointing either to \"string\" (if \"copy\" is 0)\n *\tor to a copy of string.\n *\n *----------------------------------------------------------------------\n */\n\nvoid\nTcl_SetResult(interp, string, freeProc)\n    Tcl_Interp *interp;\t\t/* Interpreter with which to associate the\n\t\t\t\t * return value. */\n    unsigned char *string;\t/* Value to be returned.  If NULL,\n\t\t\t\t * the result is set to an empty string. */\n    Tcl_FreeProc *freeProc;\t/* Gives information about the string:\n\t\t\t\t * TCL_STATIC, TCL_VOLATILE, or the address\n\t\t\t\t * of a Tcl_FreeProc such as free. */\n{\n    register Interp *iPtr = (Interp *) interp;\n    int length;\n    Tcl_FreeProc *oldFreeProc = iPtr->freeProc;\n    unsigned char *oldResult = iPtr->result;\n\n    iPtr->freeProc = freeProc;\n    if (string == 0) {\n\tiPtr->resultSpace[0] = 0;\n\tiPtr->result = iPtr->resultSpace;\n\tiPtr->freeProc = 0;\n    } else if (freeProc == TCL_VOLATILE) {\n\tlength = strlen(string);\n\tif (length > TCL_RESULT_SIZE) {\n\t    iPtr->result = malloc (length+1);\n\t    iPtr->freeProc = (Tcl_FreeProc *) free;\n\t} else {\n\t    iPtr->result = iPtr->resultSpace;\n\t    iPtr->freeProc = 0;\n\t}\n\tstrcpy(iPtr->result, string);\n    } else {\n\tiPtr->result = string;\n    }\n\n    /*\n     * If the old result was dynamically-allocated, free it up.  Do it\n     * here, rather than at the beginning, in case the new result value\n     * was part of the old result value.\n     */\n\n    if (oldFreeProc != 0) {\n\tif (oldFreeProc == TCL_DYNAMIC) {\n\t    free(oldResult);\n\t} else {\n\t    (*oldFreeProc)(oldResult);\n\t}\n    }\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_AppendResult --\n *\n *\tAppend a variable number of strings onto the result already\n *\tpresent for an interpreter.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tThe result in the interpreter given by the first argument\n *\tis extended by the strings given by the second and following\n *\targuments (up to a terminating NULL argument).\n *\n *----------------------------------------------------------------------\n */\n\n\t/* VARARGS2 */\nvoid\nTcl_AppendResult (Tcl_Interp *interp,\t/* Interpreter whose result is to be\n\t\t\t\t\t * extended. */\n\t...)\t\t\t\t/* One or more strings to add to the\n\t\t\t\t\t * result, terminated with NULL. */\n{\n    va_list argList;\n    register Interp *iPtr = (Interp *) interp;\n    unsigned char *string;\n    int newSpace;\n\n    /*\n     * First, scan through all the arguments to see how much space is\n     * needed.\n     */\n    va_start(argList, interp);\n    newSpace = 0;\n    while (1) {\n\tstring = va_arg(argList, unsigned char *);\n\tif (string == 0) {\n\t    break;\n\t}\n\tnewSpace += strlen(string);\n    }\n    va_end(argList);\n\n    /*\n     * If the append buffer isn't already setup and large enough\n     * to hold the new data, set it up.\n     */\n    if ((iPtr->result != iPtr->appendResult)\n\t   || ((newSpace + iPtr->appendUsed) >= iPtr->appendAvl)) {\n       SetupAppendBuffer(iPtr, newSpace);\n    }\n\n    /*\n     * Final step:  go through all the argument strings again, copying\n     * them into the buffer.\n     */\n    va_start(argList, interp);\n    while (1) {\n\tstring = va_arg(argList, unsigned char *);\n\tif (string == 0) {\n\t    break;\n\t}\n\tstrcpy(iPtr->appendResult + iPtr->appendUsed, string);\n\tiPtr->appendUsed += strlen(string);\n    }\n    va_end(argList);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_AppendElement --\n *\n *\tConvert a string to a valid Tcl list element and append it\n *\tto the current result (which is ostensibly a list).\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tThe result in the interpreter given by the first argument\n *\tis extended with a list element converted from string.  If\n *\tthe original result wasn't empty, then a blank is added before\n *\tthe converted list element.\n *\n *----------------------------------------------------------------------\n */\n\nvoid\nTcl_AppendElement(interp, string, noSep)\n    Tcl_Interp *interp;\t\t/* Interpreter whose result is to be\n\t\t\t\t * extended. */\n    unsigned char *string;\t/* String to convert to list element and\n\t\t\t\t * add to result. */\n    int noSep;\t\t\t/* If non-zero, then don't output a\n\t\t\t\t * space character before this element,\n\t\t\t\t * even if the element isn't the first\n\t\t\t\t * thing in the output buffer. */\n{\n    register Interp *iPtr = (Interp *) interp;\n    int size, flags;\n    unsigned char *dst;\n\n    /*\n     * See how much space is needed, and grow the append buffer if\n     * needed to accommodate the list element.\n     */\n\n    size = Tcl_ScanElement(string, &flags) + 1;\n    if ((iPtr->result != iPtr->appendResult)\n\t   || ((size + iPtr->appendUsed) >= iPtr->appendAvl)) {\n       SetupAppendBuffer(iPtr, size+iPtr->appendUsed);\n    }\n\n    /*\n     * Convert the string into a list element and copy it to the\n     * buffer that's forming.\n     */\n\n    dst = iPtr->appendResult + iPtr->appendUsed;\n    if (!noSep && (iPtr->appendUsed != 0)) {\n\tiPtr->appendUsed++;\n\t*dst = ' ';\n\tdst++;\n    }\n    iPtr->appendUsed += Tcl_ConvertElement(string, dst, flags);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * SetupAppendBuffer --\n *\n *\tThis procedure makes sure that there is an append buffer\n *\tproperly initialized for interp, and that it has at least\n *\tenough room to accommodate newSpace new bytes of information.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nstatic void\nSetupAppendBuffer(iPtr, newSpace)\n    register Interp *iPtr;\t/* Interpreter whose result is being set up. */\n    int newSpace;\t\t/* Make sure that at least this many bytes\n\t\t\t\t * of new information may be added. */\n{\n    int totalSpace;\n\n    /*\n     * Make the append buffer larger, if that's necessary, then\n     * copy the current result into the append buffer and make the\n     * append buffer the official Tcl result.\n     */\n\n    if (iPtr->result != iPtr->appendResult) {\n\t/*\n\t * If an oversized buffer was used recently, then free it up\n\t * so we go back to a smaller buffer.  This avoids tying up\n\t * memory forever after a large operation.\n\t */\n\n\tif (iPtr->appendAvl > 500) {\n\t    free (iPtr->appendResult);\n\t    iPtr->appendResult = 0;\n\t    iPtr->appendAvl = 0;\n\t}\n\tiPtr->appendUsed = strlen(iPtr->result);\n    }\n    totalSpace = newSpace + iPtr->appendUsed;\n    if (totalSpace >= iPtr->appendAvl) {\n\tunsigned char *new;\n\n\tif (totalSpace < 100) {\n\t    totalSpace = 200;\n\t} else {\n\t    totalSpace *= 2;\n\t}\n\tnew = malloc (totalSpace);\n\tstrcpy(new, iPtr->result);\n\tif (iPtr->appendResult != 0) {\n\t    free (iPtr->appendResult);\n\t}\n\tiPtr->appendResult = new;\n\tiPtr->appendAvl = totalSpace;\n    } else if (iPtr->result != iPtr->appendResult) {\n\tstrcpy(iPtr->appendResult, iPtr->result);\n    }\n    Tcl_FreeResult ((Tcl_Interp*) iPtr);\n    iPtr->result = iPtr->appendResult;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_ResetResult --\n *\n *\tThis procedure restores the result area for an interpreter\n *\tto its default initialized state, freeing up any memory that\n *\tmay have been allocated for the result and clearing any\n *\terror information for the interpreter.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nvoid\nTcl_ResetResult(interp)\n    Tcl_Interp *interp;\t\t/* Interpreter for which to clear result. */\n{\n    register Interp *iPtr = (Interp *) interp;\n\n    Tcl_FreeResult ((Tcl_Interp*) iPtr);\n    iPtr->result = iPtr->resultSpace;\n    iPtr->resultSpace[0] = 0;\n    iPtr->flags &=\n\t    ~(ERR_ALREADY_LOGGED | ERR_IN_PROGRESS | ERROR_CODE_SET);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_SetErrorCode --\n *\n *\tThis procedure is called to record machine-readable information\n *\tabout an error that is about to be returned.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tThe errorCode global variable is modified to hold all of the\n *\targuments to this procedure, in a list form with each argument\n *\tbecoming one element of the list.  A flag is set internally\n *\tto remember that errorCode has been set, so the variable doesn't\n *\tget set automatically when the error is returned.\n *\n *----------------------------------------------------------------------\n */\n\t/* VARARGS2 */\nvoid\nTcl_SetErrorCode (Tcl_Interp *interp,\t/* Interpreter whose errorCode variable is\n\t\t\t\t\t * to be set. */\n\t...)\t\t\t\t/* One or more elements to add to errorCode,\n\t\t\t\t\t * terminated with NULL. */\n{\n    va_list argList;\n    unsigned char *string;\n    int flags;\n    Interp *iPtr = (Interp *) interp;\n\n    /*\n     * Scan through the arguments one at a time, appending them to\n     * $errorCode as list elements.\n     */\n    va_start(argList, interp);\n    flags = TCL_GLOBAL_ONLY | TCL_LIST_ELEMENT;\n    while (1) {\n\tstring = va_arg(argList, unsigned char *);\n\tif (string == 0) {\n\t    break;\n\t}\n\tTcl_SetVar2((Tcl_Interp *) iPtr, (unsigned char*) \"errorCode\",\n\t\t0, string, flags);\n\tflags |= TCL_APPEND_VALUE;\n    }\n    va_end(argList);\n    iPtr->flags |= ERROR_CODE_SET;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * TclGetListIndex --\n *\n *\tParse a list index, which may be either an integer or the\n *\tvalue \"end\".\n *\n * Results:\n *\tThe return value is either TCL_OK or TCL_ERROR.  If it is\n *\tTCL_OK, then the index corresponding to string is left in\n *\t*indexPtr.  If the return value is TCL_ERROR, then string\n *\twas bogus;  an error message is returned in interp->result.\n *\tIf a negative index is specified, it is rounded up to 0.\n *\tThe index value may be larger than the size of the list\n *\t(this happens when \"end\" is specified).\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTclGetListIndex(interp, string, indexPtr)\n    Tcl_Interp *interp;\t\t\t/* Interpreter for error reporting. */\n    unsigned char *string;\t\t/* String containing list index. */\n    int *indexPtr;\t\t\t/* Where to store index. */\n{\n    if (isdigit(*string) || (*string == '-')) {\n\tif (Tcl_GetInt(interp, string, indexPtr) != TCL_OK) {\n\t    return TCL_ERROR;\n\t}\n\tif (*indexPtr < 0) {\n\t    *indexPtr = 0;\n\t}\n    } else if (strncmp(string, (unsigned char*) \"end\", strlen(string)) == 0) {\n\t*indexPtr = 32767;\n    } else {\n\tTcl_AppendResult(interp, \"bad index \\\"\", string,\n\t\t\"\\\": must be integer or \\\"end\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * TclCompileRegexp --\n *\n *\tCompile a regular expression into a form suitable for fast\n *\tmatching.  This procedure retains a small cache of pre-compiled\n *\tregular expressions in the interpreter, in order to avoid\n *\tcompilation costs as much as possible.\n *\n * Results:\n *\tThe return value is a pointer to the compiled form of string,\n *\tsuitable for passing to regexec.  If an error occurred while\n *\tcompiling the pattern, then NULL is returned and an error\n *\tmessage is left in interp->result.\n *\n * Side effects:\n *\tThe cache of compiled regexp's in interp will be modified to\n *\thold information for string, if such information isn't already\n *\tpresent in the cache.\n *\n *----------------------------------------------------------------------\n */\n\nregexp_t *\nTclCompileRegexp(interp, string)\n    Tcl_Interp *interp;\t\t\t/* For use in error reporting. */\n    unsigned char *string;\t\t/* String for which to produce\n\t\t\t\t\t * compiled regular expression. */\n{\n    register Interp *iPtr = (Interp *) interp;\n    int i, length, size;\n    regexp_t *result;\n\n    length = strlen(string);\n    for (i = 0; i < NUM_REGEXPS; i++) {\n\tif ((length == iPtr->patLengths[i])\n\t\t&& (strcmp(string, iPtr->patterns[i]) == 0)) {\n\t    /*\n\t     * Move the matched pattern to the first slot in the\n\t     * cache and shift the other patterns down one position.\n\t     */\n\n\t    if (i != 0) {\n\t\tint j;\n\t\tunsigned char *cachedString;\n\n\t\tcachedString = iPtr->patterns[i];\n\t\tresult = iPtr->regexps[i];\n\t\tfor (j = i-1; j >= 0; j--) {\n\t\t    iPtr->patterns[j+1] = iPtr->patterns[j];\n\t\t    iPtr->patLengths[j+1] = iPtr->patLengths[j];\n\t\t    iPtr->regexps[j+1] = iPtr->regexps[j];\n\t\t}\n\t\tiPtr->patterns[0] = cachedString;\n\t\tiPtr->patLengths[0] = length;\n\t\tiPtr->regexps[0] = result;\n\t    }\n\t    return iPtr->regexps[0];\n\t}\n    }\n\n    /*\n     * No match in the cache.  Compile the string and add it to the\n     * cache.\n     */\n    size = regexp_size (string);\n    if (size <= 0) {\n\tTcl_AppendResult(interp, \"invalid regular expression pattern\", 0);\n\treturn 0;\n    }\n    result = (regexp_t*) malloc (size);\n    if (! regexp_compile (result, string)) {\n\tTcl_AppendResult(interp, \"couldn't compile regular expression pattern\", 0);\n\treturn 0;\n    }\n    if (iPtr->patterns[NUM_REGEXPS-1] != 0) {\n\tfree (iPtr->patterns[NUM_REGEXPS-1]);\n\tfree (iPtr->regexps[NUM_REGEXPS-1]);\n    }\n    for (i = NUM_REGEXPS - 2; i >= 0; i--) {\n\tiPtr->patterns[i+1] = iPtr->patterns[i];\n\tiPtr->patLengths[i+1] = iPtr->patLengths[i];\n\tiPtr->regexps[i+1] = iPtr->regexps[i];\n    }\n    iPtr->patterns[0] = malloc (length+1);\n    strcpy(iPtr->patterns[0], string);\n    iPtr->patLengths[0] = length;\n    iPtr->regexps[0] = result;\n    return result;\n}\n"
  },
  {
    "path": "lib/libtcl/tcluxstr.c",
    "content": "/*\n * tclUnixStr.c --\n *\n *\tThis file contains procedures that generate strings\n *\tcorresponding to various UNIX-related codes, such\n *\tas errno and signals.\n *\n * Copyright 1991 Regents of the University of California\n * Permission to use, copy, modify, and distribute this\n * software and its documentation for any purpose and without\n * fee is hereby granted, provided that this copyright\n * notice appears in all copies.  The University of California\n * makes no representations about the suitability of this\n * software for any purpose.  It is provided \"as is\" without\n * express or implied warranty.\n */\n#include \"internal.h\"\n#ifdef CROSS\n#   include </usr/include/errno.h>\n#else\n#   include <errno.h>\n#endif\n\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_ErrnoId --\n *\n *\tReturn a textual identifier for the current errno value.\n *\n * Results:\n *\tThis procedure returns a machine-readable textual identifier\n *\tthat corresponds to the current errno value (e.g. \"EPERM\").\n *\tThe identifier is the same as the #define name in errno.h.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nunsigned char *\nTcl_ErrnoId()\n{\n    switch (errno) {\n#ifdef E2BIG\n\tcase E2BIG: return \"E2BIG\";\n#endif\n#ifdef EACCES\n\tcase EACCES: return \"EACCES\";\n#endif\n#ifdef EADDRINUSE\n\tcase EADDRINUSE: return \"EADDRINUSE\";\n#endif\n#ifdef EADDRNOTAVAIL\n\tcase EADDRNOTAVAIL: return \"EADDRNOTAVAIL\";\n#endif\n#ifdef EADV\n\tcase EADV: return \"EADV\";\n#endif\n#ifdef EAFNOSUPPORT\n\tcase EAFNOSUPPORT: return \"EAFNOSUPPORT\";\n#endif\n#ifdef EAGAIN\n\tcase EAGAIN: return \"EAGAIN\";\n#endif\n#ifdef EALIGN\n\tcase EALIGN: return \"EALIGN\";\n#endif\n#ifdef EALREADY\n\tcase EALREADY: return \"EALREADY\";\n#endif\n#ifdef EBADE\n\tcase EBADE: return \"EBADE\";\n#endif\n#ifdef EBADF\n\tcase EBADF: return \"EBADF\";\n#endif\n#ifdef EBADFD\n\tcase EBADFD: return \"EBADFD\";\n#endif\n#ifdef EBADMSG\n\tcase EBADMSG: return \"EBADMSG\";\n#endif\n#ifdef EBADR\n\tcase EBADR: return \"EBADR\";\n#endif\n#ifdef EBADRPC\n\tcase EBADRPC: return \"EBADRPC\";\n#endif\n#ifdef EBADRQC\n\tcase EBADRQC: return \"EBADRQC\";\n#endif\n#ifdef EBADSLT\n\tcase EBADSLT: return \"EBADSLT\";\n#endif\n#ifdef EBFONT\n\tcase EBFONT: return \"EBFONT\";\n#endif\n#ifdef EBUSY\n\tcase EBUSY: return \"EBUSY\";\n#endif\n#ifdef ECHILD\n\tcase ECHILD: return \"ECHILD\";\n#endif\n#ifdef ECHRNG\n\tcase ECHRNG: return \"ECHRNG\";\n#endif\n#ifdef ECOMM\n\tcase ECOMM: return \"ECOMM\";\n#endif\n#ifdef ECONNABORTED\n\tcase ECONNABORTED: return \"ECONNABORTED\";\n#endif\n#ifdef ECONNREFUSED\n\tcase ECONNREFUSED: return \"ECONNREFUSED\";\n#endif\n#ifdef ECONNRESET\n\tcase ECONNRESET: return \"ECONNRESET\";\n#endif\n#if defined(EDEADLK) && (!defined(EWOULDBLOCK) || (EDEADLK != EWOULDBLOCK))\n\tcase EDEADLK: return \"EDEADLK\";\n#endif\n/*\n#ifdef EDEADLOCK\n\tcase EDEADLOCK: return \"EDEADLOCK\";\n#endif\n*/\n#ifdef EDESTADDRREQ\n\tcase EDESTADDRREQ: return \"EDESTADDRREQ\";\n#endif\n#ifdef EDIRTY\n\tcase EDIRTY: return \"EDIRTY\";\n#endif\n#ifdef EDOM\n\tcase EDOM: return \"EDOM\";\n#endif\n#ifdef EDOTDOT\n\tcase EDOTDOT: return \"EDOTDOT\";\n#endif\n#ifdef EDQUOT\n\tcase EDQUOT: return \"EDQUOT\";\n#endif\n#ifdef EDUPPKG\n\tcase EDUPPKG: return \"EDUPPKG\";\n#endif\n#ifdef EEXIST\n\tcase EEXIST: return \"EEXIST\";\n#endif\n#ifdef EFAULT\n\tcase EFAULT: return \"EFAULT\";\n#endif\n#ifdef EFBIG\n\tcase EFBIG: return \"EFBIG\";\n#endif\n#ifdef EHOSTDOWN\n\tcase EHOSTDOWN: return \"EHOSTDOWN\";\n#endif\n#ifdef EHOSTUNREACH\n\tcase EHOSTUNREACH: return \"EHOSTUNREACH\";\n#endif\n#ifdef EIDRM\n\tcase EIDRM: return \"EIDRM\";\n#endif\n#ifdef EINIT\n\tcase EINIT: return \"EINIT\";\n#endif\n#ifdef EINPROGRESS\n\tcase EINPROGRESS: return \"EINPROGRESS\";\n#endif\n#ifdef EINTR\n\tcase EINTR: return \"EINTR\";\n#endif\n#ifdef EINVAL\n\tcase EINVAL: return \"EINVAL\";\n#endif\n#ifdef EIO\n\tcase EIO: return \"EIO\";\n#endif\n#ifdef EISCONN\n\tcase EISCONN: return \"EISCONN\";\n#endif\n#ifdef EISDIR\n\tcase EISDIR: return \"EISDIR\";\n#endif\n#ifdef EISNAME\n\tcase EISNAM: return \"EISNAM\";\n#endif\n#ifdef ELBIN\n\tcase ELBIN: return \"ELBIN\";\n#endif\n#ifdef EL2HLT\n\tcase EL2HLT: return \"EL2HLT\";\n#endif\n#ifdef EL2NSYNC\n\tcase EL2NSYNC: return \"EL2NSYNC\";\n#endif\n#ifdef EL3HLT\n\tcase EL3HLT: return \"EL3HLT\";\n#endif\n#ifdef EL3RST\n\tcase EL3RST: return \"EL3RST\";\n#endif\n#ifdef ELIBACC\n\tcase ELIBACC: return \"ELIBACC\";\n#endif\n#ifdef ELIBBAD\n\tcase ELIBBAD: return \"ELIBBAD\";\n#endif\n#ifdef ELIBEXEC\n\tcase ELIBEXEC: return \"ELIBEXEC\";\n#endif\n#ifdef ELIBMAX\n\tcase ELIBMAX: return \"ELIBMAX\";\n#endif\n#ifdef ELIBSCN\n\tcase ELIBSCN: return \"ELIBSCN\";\n#endif\n#ifdef ELNRNG\n\tcase ELNRNG: return \"ELNRNG\";\n#endif\n#ifdef ELOOP\n\tcase ELOOP: return \"ELOOP\";\n#endif\n#ifdef EMFILE\n\tcase EMFILE: return \"EMFILE\";\n#endif\n#ifdef EMLINK\n\tcase EMLINK: return \"EMLINK\";\n#endif\n#ifdef EMSGSIZE\n\tcase EMSGSIZE: return \"EMSGSIZE\";\n#endif\n#ifdef EMULTIHOP\n\tcase EMULTIHOP: return \"EMULTIHOP\";\n#endif\n#ifdef ENAMETOOLONG\n\tcase ENAMETOOLONG: return \"ENAMETOOLONG\";\n#endif\n#ifdef ENAVAIL\n\tcase ENAVAIL: return \"ENAVAIL\";\n#endif\n#ifdef ENET\n\tcase ENET: return \"ENET\";\n#endif\n#ifdef ENETDOWN\n\tcase ENETDOWN: return \"ENETDOWN\";\n#endif\n#ifdef ENETRESET\n\tcase ENETRESET: return \"ENETRESET\";\n#endif\n#ifdef ENETUNREACH\n\tcase ENETUNREACH: return \"ENETUNREACH\";\n#endif\n#ifdef ENFILE\n\tcase ENFILE: return \"ENFILE\";\n#endif\n#ifdef ENOANO\n\tcase ENOANO: return \"ENOANO\";\n#endif\n#if defined(ENOBUFS) && (!defined(ENOSR) || (ENOBUFS != ENOSR))\n\tcase ENOBUFS: return \"ENOBUFS\";\n#endif\n#ifdef ENOCSI\n\tcase ENOCSI: return \"ENOCSI\";\n#endif\n#ifdef ENODATA\n\tcase ENODATA: return \"ENODATA\";\n#endif\n#ifdef ENODEV\n\tcase ENODEV: return \"ENODEV\";\n#endif\n#ifdef ENOENT\n\tcase ENOENT: return \"ENOENT\";\n#endif\n#ifdef ENOEXEC\n\tcase ENOEXEC: return \"ENOEXEC\";\n#endif\n#ifdef ENOLCK\n\tcase ENOLCK: return \"ENOLCK\";\n#endif\n#ifdef ENOLINK\n\tcase ENOLINK: return \"ENOLINK\";\n#endif\n#ifdef ENOMEM\n\tcase ENOMEM: return \"ENOMEM\";\n#endif\n#ifdef ENOMSG\n\tcase ENOMSG: return \"ENOMSG\";\n#endif\n#ifdef ENONET\n\tcase ENONET: return \"ENONET\";\n#endif\n#ifdef ENOPKG\n\tcase ENOPKG: return \"ENOPKG\";\n#endif\n#ifdef ENOPROTOOPT\n\tcase ENOPROTOOPT: return \"ENOPROTOOPT\";\n#endif\n#ifdef ENOSPC\n\tcase ENOSPC: return \"ENOSPC\";\n#endif\n#ifdef ENOSR\n\tcase ENOSR: return \"ENOSR\";\n#endif\n#ifdef ENOSTR\n\tcase ENOSTR: return \"ENOSTR\";\n#endif\n#ifdef ENOSYM\n\tcase ENOSYM: return \"ENOSYM\";\n#endif\n#ifdef ENOSYS\n\tcase ENOSYS: return \"ENOSYS\";\n#endif\n#ifdef ENOTBLK\n\tcase ENOTBLK: return \"ENOTBLK\";\n#endif\n#ifdef ENOTCONN\n\tcase ENOTCONN: return \"ENOTCONN\";\n#endif\n#ifdef ENOTDIR\n\tcase ENOTDIR: return \"ENOTDIR\";\n#endif\n#if defined(ENOTEMPTY) && (!defined(EEXIST) || (ENOTEMPTY != EEXIST))\n\tcase ENOTEMPTY: return \"ENOTEMPTY\";\n#endif\n#ifdef ENOTNAM\n\tcase ENOTNAM: return \"ENOTNAM\";\n#endif\n#ifdef ENOTSOCK\n\tcase ENOTSOCK: return \"ENOTSOCK\";\n#endif\n#ifdef ENOTTY\n\tcase ENOTTY: return \"ENOTTY\";\n#endif\n#ifdef ENOTUNIQ\n\tcase ENOTUNIQ: return \"ENOTUNIQ\";\n#endif\n#ifdef ENXIO\n\tcase ENXIO: return \"ENXIO\";\n#endif\n#ifdef EOPNOTSUPP\n\tcase EOPNOTSUPP: return \"EOPNOTSUPP\";\n#endif\n#ifdef EPERM\n\tcase EPERM: return \"EPERM\";\n#endif\n#ifdef EPFNOSUPPORT\n\tcase EPFNOSUPPORT: return \"EPFNOSUPPORT\";\n#endif\n#ifdef EPIPE\n\tcase EPIPE: return \"EPIPE\";\n#endif\n#ifdef EPROCLIM\n\tcase EPROCLIM: return \"EPROCLIM\";\n#endif\n#ifdef EPROCUNAVAIL\n\tcase EPROCUNAVAIL: return \"EPROCUNAVAIL\";\n#endif\n#ifdef EPROGMISMATCH\n\tcase EPROGMISMATCH: return \"EPROGMISMATCH\";\n#endif\n#ifdef EPROGUNAVAIL\n\tcase EPROGUNAVAIL: return \"EPROGUNAVAIL\";\n#endif\n#ifdef EPROTO\n\tcase EPROTO: return \"EPROTO\";\n#endif\n#ifdef EPROTONOSUPPORT\n\tcase EPROTONOSUPPORT: return \"EPROTONOSUPPORT\";\n#endif\n#ifdef EPROTOTYPE\n\tcase EPROTOTYPE: return \"EPROTOTYPE\";\n#endif\n#ifdef ERANGE\n\tcase ERANGE: return \"ERANGE\";\n#endif\n#if defined(EREFUSED) && (!defined(ECONNREFUSED) || (EREFUSED != ECONNREFUSED))\n\tcase EREFUSED: return \"EREFUSED\";\n#endif\n#ifdef EREMCHG\n\tcase EREMCHG: return \"EREMCHG\";\n#endif\n#ifdef EREMDEV\n\tcase EREMDEV: return \"EREMDEV\";\n#endif\n#ifdef EREMOTE\n\tcase EREMOTE: return \"EREMOTE\";\n#endif\n#ifdef EREMOTEIO\n\tcase EREMOTEIO: return \"EREMOTEIO\";\n#endif\n#ifdef EREMOTERELEASE\n\tcase EREMOTERELEASE: return \"EREMOTERELEASE\";\n#endif\n#ifdef EROFS\n\tcase EROFS: return \"EROFS\";\n#endif\n#ifdef ERPCMISMATCH\n\tcase ERPCMISMATCH: return \"ERPCMISMATCH\";\n#endif\n#ifdef ERREMOTE\n\tcase ERREMOTE: return \"ERREMOTE\";\n#endif\n#ifdef ESHUTDOWN\n\tcase ESHUTDOWN: return \"ESHUTDOWN\";\n#endif\n#ifdef ESOCKTNOSUPPORT\n\tcase ESOCKTNOSUPPORT: return \"ESOCKTNOSUPPORT\";\n#endif\n#ifdef ESPIPE\n\tcase ESPIPE: return \"ESPIPE\";\n#endif\n#ifdef ESRCH\n\tcase ESRCH: return \"ESRCH\";\n#endif\n#ifdef ESRMNT\n\tcase ESRMNT: return \"ESRMNT\";\n#endif\n#ifdef ESTALE\n\tcase ESTALE: return \"ESTALE\";\n#endif\n#ifdef ESUCCESS\n\tcase ESUCCESS: return \"ESUCCESS\";\n#endif\n#ifdef ETIME\n\tcase ETIME: return \"ETIME\";\n#endif\n#ifdef ETIMEDOUT\n\tcase ETIMEDOUT: return \"ETIMEDOUT\";\n#endif\n#ifdef ETOOMANYREFS\n\tcase ETOOMANYREFS: return \"ETOOMANYREFS\";\n#endif\n#ifdef ETXTBSY\n\tcase ETXTBSY: return \"ETXTBSY\";\n#endif\n#ifdef EUCLEAN\n\tcase EUCLEAN: return \"EUCLEAN\";\n#endif\n#ifdef EUNATCH\n\tcase EUNATCH: return \"EUNATCH\";\n#endif\n#ifdef EUSERS\n\tcase EUSERS: return \"EUSERS\";\n#endif\n#ifdef EVERSION\n\tcase EVERSION: return \"EVERSION\";\n#endif\n#if defined(EWOULDBLOCK) && (!defined(EAGAIN) || (EWOULDBLOCK != EAGAIN))\n\tcase EWOULDBLOCK: return \"EWOULDBLOCK\";\n#endif\n#ifdef EXDEV\n\tcase EXDEV: return \"EXDEV\";\n#endif\n#ifdef EXFULL\n\tcase EXFULL: return \"EXFULL\";\n#endif\n    }\n    return \"unknown error\";\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_SignalId --\n *\n *\tReturn a textual identifier for a signal number.\n *\n * Results:\n *\tThis procedure returns a machine-readable textual identifier\n *\tthat corresponds to sig.  The identifier is the same as the\n *\t#define name in signal.h.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nunsigned char *\nTcl_SignalId(sig)\n    int sig;\t\t\t/* Number of signal. */\n{\n    switch (sig) {\n#ifdef SIGABRT\n\tcase SIGABRT: return \"SIGABRT\";\n#endif\n#ifdef SIGALRM\n\tcase SIGALRM: return \"SIGALRM\";\n#endif\n#ifdef SIGBUS\n\tcase SIGBUS: return \"SIGBUS\";\n#endif\n#ifdef SIGCHLD\n\tcase SIGCHLD: return \"SIGCHLD\";\n#endif\n#if defined(SIGCLD) && (!defined(SIGCHLD) || (SIGCLD != SIGCHLD))\n\tcase SIGCLD: return \"SIGCLD\";\n#endif\n#ifdef SIGCONT\n\tcase SIGCONT: return \"SIGCONT\";\n#endif\n#if defined(SIGEMT) && (!defined(SIGXCPU) || (SIGEMT != SIGXCPU))\n\tcase SIGEMT: return \"SIGEMT\";\n#endif\n#ifdef SIGFPE\n\tcase SIGFPE: return \"SIGFPE\";\n#endif\n#ifdef SIGHUP\n\tcase SIGHUP: return \"SIGHUP\";\n#endif\n#ifdef SIGILL\n\tcase SIGILL: return \"SIGILL\";\n#endif\n#ifdef SIGINT\n\tcase SIGINT: return \"SIGINT\";\n#endif\n#ifdef SIGIO\n\tcase SIGIO: return \"SIGIO\";\n#endif\n#if defined(SIGIOT) && (!defined(SIGABRT) || (SIGIOT != SIGABRT))\n\tcase SIGIOT: return \"SIGIOT\";\n#endif\n#ifdef SIGKILL\n\tcase SIGKILL: return \"SIGKILL\";\n#endif\n#if defined(SIGLOST) && (!defined(SIGIOT) || (SIGLOST != SIGIOT)) && (!defined(SIGURG) || (SIGLOST != SIGURG))\n\tcase SIGLOST: return \"SIGLOST\";\n#endif\n#ifdef SIGPIPE\n\tcase SIGPIPE: return \"SIGPIPE\";\n#endif\n#if defined(SIGPOLL) && (!defined(SIGIO) || (SIGPOLL != SIGIO))\n\tcase SIGPOLL: return \"SIGPOLL\";\n#endif\n#ifdef SIGPROF\n\tcase SIGPROF: return \"SIGPROF\";\n#endif\n#if defined(SIGPWR) && (!defined(SIGXFSZ) || (SIGPWR != SIGXFSZ))\n\tcase SIGPWR: return \"SIGPWR\";\n#endif\n#ifdef SIGQUIT\n\tcase SIGQUIT: return \"SIGQUIT\";\n#endif\n#ifdef SIGSEGV\n\tcase SIGSEGV: return \"SIGSEGV\";\n#endif\n#ifdef SIGSTOP\n\tcase SIGSTOP: return \"SIGSTOP\";\n#endif\n#ifdef SIGSYS\n\tcase SIGSYS: return \"SIGSYS\";\n#endif\n#ifdef SIGTERM\n\tcase SIGTERM: return \"SIGTERM\";\n#endif\n#ifdef SIGTRAP\n\tcase SIGTRAP: return \"SIGTRAP\";\n#endif\n#ifdef SIGTSTP\n\tcase SIGTSTP: return \"SIGTSTP\";\n#endif\n#ifdef SIGTTIN\n\tcase SIGTTIN: return \"SIGTTIN\";\n#endif\n#ifdef SIGTTOU\n\tcase SIGTTOU: return \"SIGTTOU\";\n#endif\n#if defined(SIGURG) && (!defined(SIGIO) || (SIGURG != SIGIO))\n\tcase SIGURG: return \"SIGURG\";\n#endif\n#ifdef SIGUSR1\n\tcase SIGUSR1: return \"SIGUSR1\";\n#endif\n#ifdef SIGUSR2\n\tcase SIGUSR2: return \"SIGUSR2\";\n#endif\n#ifdef SIGVTALRM\n\tcase SIGVTALRM: return \"SIGVTALRM\";\n#endif\n#ifdef SIGWINCH\n\tcase SIGWINCH: return \"SIGWINCH\";\n#endif\n#ifdef SIGXCPU\n\tcase SIGXCPU: return \"SIGXCPU\";\n#endif\n#ifdef SIGXFSZ\n\tcase SIGXFSZ: return \"SIGXFSZ\";\n#endif\n    }\n    return \"unknown signal\";\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_SignalMsg --\n *\n *\tReturn a human-readable message describing a signal.\n *\n * Results:\n *\tThis procedure returns a string describing sig that should\n *\tmake sense to a human.  It may not be easy for a machine\n *\tto parse.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nunsigned char *\nTcl_SignalMsg(sig)\n    int sig;\t\t\t/* Number of signal. */\n{\n    switch (sig) {\n#ifdef SIGABRT\n\tcase SIGABRT: return \"SIGABRT\";\n#endif\n#ifdef SIGALRM\n\tcase SIGALRM: return \"alarm clock\";\n#endif\n#ifdef SIGBUS\n\tcase SIGBUS: return \"bus error\";\n#endif\n#ifdef SIGCHLD\n\tcase SIGCHLD: return \"child status changed\";\n#endif\n#if defined(SIGCLD) && (!defined(SIGCHLD) || (SIGCLD != SIGCHLD))\n\tcase SIGCLD: return \"child status changed\";\n#endif\n#ifdef SIGCONT\n\tcase SIGCONT: return \"continue after stop\";\n#endif\n#if defined(SIGEMT) && (!defined(SIGXCPU) || (SIGEMT != SIGXCPU))\n\tcase SIGEMT: return \"EMT instruction\";\n#endif\n#ifdef SIGFPE\n\tcase SIGFPE: return \"floating-point exception\";\n#endif\n#ifdef SIGHUP\n\tcase SIGHUP: return \"hangup\";\n#endif\n#ifdef SIGILL\n\tcase SIGILL: return \"illegal instruction\";\n#endif\n#ifdef SIGINT\n\tcase SIGINT: return \"interrupt\";\n#endif\n#ifdef SIGIO\n\tcase SIGIO: return \"input/output possible on file\";\n#endif\n#if defined(SIGIOT) && (!defined(SIGABRT) || (SIGABRT != SIGIOT))\n\tcase SIGIOT: return \"IOT instruction\";\n#endif\n#ifdef SIGKILL\n\tcase SIGKILL: return \"kill signal\";\n#endif\n#if defined(SIGLOST) && (!defined(SIGIOT) || (SIGLOST != SIGIOT)) && (!defined(SIGURG) || (SIGLOST != SIGURG))\n\tcase SIGLOST: return \"resource lost\";\n#endif\n#ifdef SIGPIPE\n\tcase SIGPIPE: return \"write on pipe with no readers\";\n#endif\n#if defined(SIGPOLL) && (!defined(SIGIO) || (SIGPOLL != SIGIO))\n\tcase SIGPOLL: return \"input/output possible on file\";\n#endif\n#ifdef SIGPROF\n\tcase SIGPROF: return \"profiling alarm\";\n#endif\n#if defined(SIGPWR) && (!defined(SIGXFSZ) || (SIGPWR != SIGXFSZ))\n\tcase SIGPWR: return \"power-fail restart\";\n#endif\n#ifdef SIGQUIT\n\tcase SIGQUIT: return \"quit signal\";\n#endif\n#ifdef SIGSEGV\n\tcase SIGSEGV: return \"segmentation violation\";\n#endif\n#ifdef SIGSTOP\n\tcase SIGSTOP: return \"stop\";\n#endif\n#ifdef SIGSYS\n\tcase SIGSYS: return \"bad argument to system call\";\n#endif\n#ifdef SIGTERM\n\tcase SIGTERM: return \"software termination signal\";\n#endif\n#ifdef SIGTRAP\n\tcase SIGTRAP: return \"trace trap\";\n#endif\n#ifdef SIGTSTP\n\tcase SIGTSTP: return \"stop signal from tty\";\n#endif\n#ifdef SIGTTIN\n\tcase SIGTTIN: return \"background tty read\";\n#endif\n#ifdef SIGTTOU\n\tcase SIGTTOU: return \"background tty write\";\n#endif\n#if defined(SIGURG) && (!defined(SIGIO) || (SIGURG != SIGIO))\n\tcase SIGURG: return \"urgent I/O condition\";\n#endif\n#ifdef SIGUSR1\n\tcase SIGUSR1: return \"user-defined signal 1\";\n#endif\n#ifdef SIGUSR2\n\tcase SIGUSR2: return \"user-defined signal 2\";\n#endif\n#ifdef SIGVTALRM\n\tcase SIGVTALRM: return \"virtual time alarm\";\n#endif\n#ifdef SIGWINCH\n\tcase SIGWINCH: return \"window changed\";\n#endif\n#ifdef SIGXCPU\n\tcase SIGXCPU: return \"exceeded CPU time limit\";\n#endif\n#ifdef SIGXFSZ\n\tcase SIGXFSZ: return \"exceeded file size limit\";\n#endif\n    }\n    return \"unknown signal\";\n}\n"
  },
  {
    "path": "lib/libtcl/tcluxutl.c",
    "content": "/*\n * tclUnixUtil.c --\n *\n *\tThis file contains a collection of utility procedures that\n *\tare present in the Tcl's UNIX core but not in the generic\n *\tcore.  For example, they do file manipulation and process\n *\tmanipulation.\n *\n *\tThe Tcl_Fork and Tcl_WaitPids procedures are based on code\n *\tcontributed by Karl Lehenbauer, Mark Diekhans and Peter\n *\tda Silva.\n *\n * Copyright 1991 Regents of the University of California\n * Permission to use, copy, modify, and distribute this\n * software and its documentation for any purpose and without\n * fee is hereby granted, provided that this copyright\n * notice appears in all copies.  The University of California\n * makes no representations about the suitability of this\n * software for any purpose.  It is provided \"as is\" without\n * express or implied warranty.\n */\n#include \"internal.h\"\n#include <sys/stat.h>\n#include <sys/wait.h>\n#include <unistd.h>\n#include <fcntl.h>\n#include <signal.h>\n#ifdef CROSS\n#   include </usr/include/errno.h>\n#else\n#   include <errno.h>\n#endif\n\n/*\n * Data structures of the following type are used by Tcl_Fork and\n * Tcl_WaitPids to keep track of child processes.\n */\n#define WAIT_STATUS_TYPE int\n\ntypedef struct {\n    int pid;\t\t\t/* Process id of child. */\n    WAIT_STATUS_TYPE status;\t/* Status returned when child exited or\n\t\t\t\t * suspended. */\n    int flags;\t\t\t/* Various flag bits;  see below for\n\t\t\t\t * definitions. */\n} WaitInfo;\n\n/*\n * Flag bits in WaitInfo structures:\n *\n * WI_READY -\t\t\tNon-zero means process has exited or\n *\t\t\t\tsuspended since it was forked or last\n *\t\t\t\treturned by Tcl_WaitPids.\n * WI_DETACHED -\t\tNon-zero means no-one cares about the\n *\t\t\t\tprocess anymore.  Ignore it until it\n *\t\t\t\texits, then forget about it.\n */\n\n#define WI_READY\t1\n#define WI_DETACHED\t2\n\nstatic WaitInfo *waitTable = NULL;\nstatic int waitTableSize = 0;\t/* Total number of entries available in\n\t\t\t\t * waitTable. */\nstatic int waitTableUsed = 0;\t/* Number of entries in waitTable that\n\t\t\t\t * are actually in use right now.  Active\n\t\t\t\t * entries are always at the beginning\n\t\t\t\t * of the table. */\n#define WAIT_TABLE_GROW_BY 4\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_EvalFile --\n *\n *\tRead in a file and process the entire file as one gigantic\n *\tTcl command.\n *\n * Results:\n *\tA standard Tcl result, which is either the result of executing\n *\tthe file or an error indicating why the file couldn't be read.\n *\n * Side effects:\n *\tDepends on the commands in the file.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTcl_EvalFile(interp, fileName)\n    Tcl_Interp *interp;\t\t/* Interpreter in which to process file. */\n    unsigned char *fileName;\t/* Name of file to process.  Tilde-substitution\n\t\t\t\t * will be performed on this name. */\n{\n    int fileId, result;\n    struct stat statBuf;\n    unsigned char *cmdBuffer, *end, *oldScriptFile;\n    Interp *iPtr = (Interp *) interp;\n\n    oldScriptFile = iPtr->scriptFile;\n    iPtr->scriptFile = fileName;\n    fileName = Tcl_TildeSubst(interp, fileName);\n    if (fileName == NULL) {\n\tgoto error;\n    }\n    fileId = open(fileName, O_RDONLY, 0);\n    if (fileId < 0) {\n\tTcl_AppendResult(interp, \"couldn't read file \\\"\", fileName,\n\t\t\"\\\": \", Tcl_UnixError(interp), (char *) NULL);\n\tgoto error;\n    }\n    if (fstat(fileId, &statBuf) == -1) {\n\tTcl_AppendResult(interp, \"couldn't stat file \\\"\", fileName,\n\t\t\"\\\": \", Tcl_UnixError(interp), (char *) NULL);\n\tclose(fileId);\n\tgoto error;\n    }\n    cmdBuffer = (unsigned char *) malloc((unsigned) statBuf.st_size+1);\n    if (read(fileId, cmdBuffer, (int) statBuf.st_size) != statBuf.st_size) {\n\tTcl_AppendResult(interp, \"error in reading file \\\"\", fileName,\n\t\t\"\\\": \", Tcl_UnixError(interp), (char *) NULL);\n\tclose(fileId);\n\tfree(cmdBuffer);\n\tgoto error;\n    }\n    if (close(fileId) != 0) {\n\tTcl_AppendResult(interp, \"error closing file \\\"\", fileName,\n\t\t\"\\\": \", Tcl_UnixError(interp), (char *) NULL);\n\tfree(cmdBuffer);\n\tgoto error;\n    }\n    cmdBuffer[statBuf.st_size] = 0;\n    result = Tcl_Eval(interp, cmdBuffer, 0, &end);\n    if (result == TCL_RETURN) {\n\tresult = TCL_OK;\n    }\n    if (result == TCL_ERROR) {\n\tchar msg[200];\n\n\t/*\n\t * Record information telling where the error occurred.\n\t */\n\n\tsprintf(msg, \"\\n    (file \\\"%.150s\\\" line %d)\", fileName,\n\t\tinterp->errorLine);\n\tTcl_AddErrorInfo(interp, msg);\n    }\n    free(cmdBuffer);\n    iPtr->scriptFile = oldScriptFile;\n    return result;\n\n    error:\n    iPtr->scriptFile = oldScriptFile;\n    return TCL_ERROR;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_Fork --\n *\n *\tCreate a new process using the vfork system call, and keep\n *\ttrack of it for \"safe\" waiting with Tcl_WaitPids.\n *\n * Results:\n *\tThe return value is the value returned by the vfork system\n *\tcall (0 means child, > 0 means parent (value is child id),\n *\t< 0 means error).\n *\n * Side effects:\n *\tA new process is created, and an entry is added to an internal\n *\ttable of child processes if the process is created successfully.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTcl_Fork()\n{\n    WaitInfo *waitPtr;\n    pid_t pid;\n\n    /*\n     * Disable SIGPIPE signals:  if they were allowed, this process\n     * might go away unexpectedly if children misbehave.  This code\n     * can potentially interfere with other application code that\n     * expects to handle SIGPIPEs;  what's really needed is an\n     * arbiter for signals to allow them to be \"shared\".\n     */\n\n    if (waitTable == NULL) {\n\t(void) signal(SIGPIPE, SIG_IGN);\n    }\n\n    /*\n     * Enlarge the wait table if there isn't enough space for a new\n     * entry.\n     */\n\n    if (waitTableUsed == waitTableSize) {\n\tint newSize;\n\tWaitInfo *newWaitTable;\n\n\tnewSize = waitTableSize + WAIT_TABLE_GROW_BY;\n\tnewWaitTable = (WaitInfo *) malloc((unsigned)\n\t\t(newSize * sizeof(WaitInfo)));\n\tmemcpy((void *) newWaitTable, (void *) waitTable,\n\t\t(waitTableSize * sizeof(WaitInfo)));\n\tif (waitTable != NULL) {\n\t    free((char *) waitTable);\n\t}\n\twaitTable = newWaitTable;\n\twaitTableSize = newSize;\n    }\n\n    /*\n     * Make a new process and enter it into the table if the fork\n     * is successful.\n     */\n\n    waitPtr = &waitTable[waitTableUsed];\n    pid = fork();\n    if (pid > 0) {\n\twaitPtr->pid = pid;\n\twaitPtr->flags = 0;\n\twaitTableUsed++;\n    }\n    return pid;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_WaitPids --\n *\n *\tThis procedure is used to wait for one or more processes created\n *\tby Tcl_Fork to exit or suspend.  It records information about\n *\tall processes that exit or suspend, even those not waited for,\n *\tso that later waits for them will be able to get the status\n *\tinformation.\n *\n * Results:\n *\t-1 is returned if there is an error in the wait kernel call.\n *\tOtherwise the pid of an exited/suspended process from *pidPtr\n *\tis returned and *statusPtr is set to the status value returned\n *\tby the wait kernel call.\n *\n * Side effects:\n *\tDoesn't return until one of the pids at *pidPtr exits or suspends.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTcl_WaitPids(numPids, pidPtr, statusPtr)\n    int numPids;\t\t/* Number of pids to wait on:  gives size\n\t\t\t\t * of array pointed to by pidPtr. */\n    int *pidPtr;\t\t/* Pids to wait on:  return when one of\n\t\t\t\t * these processes exits or suspends. */\n    int *statusPtr;\t\t/* Wait status is returned here. */\n{\n    int i, count, pid;\n    register WaitInfo *waitPtr;\n    int anyProcesses;\n    WAIT_STATUS_TYPE status;\n\n    while (1) {\n\t/*\n\t * Scan the table of child processes to see if one of the\n\t * specified children has already exited or suspended.  If so,\n\t * remove it from the table and return its status.\n\t */\n\n\tanyProcesses = 0;\n\tfor (waitPtr = waitTable, count = waitTableUsed;\n\t\tcount > 0; waitPtr++, count--) {\n\t    for (i = 0; i < numPids; i++) {\n\t\tif (pidPtr[i] != waitPtr->pid) {\n\t\t    continue;\n\t\t}\n\t\tanyProcesses = 1;\n\t\tif (waitPtr->flags & WI_READY) {\n\t\t    *statusPtr = *((int *) &waitPtr->status);\n\t\t    pid = waitPtr->pid;\n\t\t    if (WIFEXITED(waitPtr->status)\n\t\t\t    || WIFSIGNALED(waitPtr->status)) {\n\t\t\t*waitPtr = waitTable[waitTableUsed-1];\n\t\t\twaitTableUsed--;\n\t\t    } else {\n\t\t\twaitPtr->flags &= ~WI_READY;\n\t\t    }\n\t\t    return pid;\n\t\t}\n\t    }\n\t}\n\n\t/*\n\t * Make sure that the caller at least specified one valid\n\t * process to wait for.\n\t */\n\n\tif (!anyProcesses) {\n\t    errno = ECHILD;\n\t    return -1;\n\t}\n\n\t/*\n\t * Wait for a process to exit or suspend, then update its\n\t * entry in the table and go back to the beginning of the\n\t * loop to see if it's one of the desired processes.\n\t */\n\n\tpid = wait(&status);\n\tif (pid < 0) {\n\t    return pid;\n\t}\n\tfor (waitPtr = waitTable, count = waitTableUsed; ;\n\t\twaitPtr++, count--) {\n\t    if (count == 0) {\n\t\tbreak;\t\t\t/* Ignore unknown processes. */\n\t    }\n\t    if (pid != waitPtr->pid) {\n\t\tcontinue;\n\t    }\n\n\t    /*\n\t     * If the process has been detached, then ignore anything\n\t     * other than an exit, and drop the entry on exit.\n\t     */\n\n\t    if (waitPtr->flags & WI_DETACHED) {\n\t\tif (WIFEXITED(status) || WIFSIGNALED(status)) {\n\t\t    *waitPtr = waitTable[waitTableUsed-1];\n\t\t    waitTableUsed--;\n\t\t}\n\t    } else {\n\t\twaitPtr->status = status;\n\t\twaitPtr->flags |= WI_READY;\n\t    }\n\t    break;\n\t}\n    }\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_DetachPids --\n *\n *\tThis procedure is called to indicate that one or more child\n *\tprocesses have been placed in background and are no longer\n *\tcared about.  They should be ignored in future calls to\n *\tTcl_WaitPids.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nvoid\nTcl_DetachPids(numPids, pidPtr)\n    int numPids;\t\t/* Number of pids to detach:  gives size\n\t\t\t\t * of array pointed to by pidPtr. */\n    int *pidPtr;\t\t/* Array of pids to detach:  must have\n\t\t\t\t * been created by Tcl_Fork. */\n{\n    register WaitInfo *waitPtr;\n    int i, count, pid;\n\n    for (i = 0; i < numPids; i++) {\n\tpid = pidPtr[i];\n\tfor (waitPtr = waitTable, count = waitTableUsed;\n\t\tcount > 0; waitPtr++, count--) {\n\t    if (pid != waitPtr->pid) {\n\t\tcontinue;\n\t    }\n\n\t    /*\n\t     * If the process has already exited then destroy its\n\t     * table entry now.\n\t     */\n\n\t    if ((waitPtr->flags & WI_READY) && (WIFEXITED(waitPtr->status)\n\t\t    || WIFSIGNALED(waitPtr->status))) {\n\t\t*waitPtr = waitTable[waitTableUsed-1];\n\t\twaitTableUsed--;\n\t    } else {\n\t\twaitPtr->flags |= WI_DETACHED;\n\t    }\n\t    goto nextPid;\n\t}\n\tfprintf (stderr, \"Tcl_Detach couldn't find process\\n\");\n        abort();\nnextPid:\n\tcontinue;\n    }\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_CreatePipeline --\n *\n *\tGiven an argc/argv array, instantiate a pipeline of processes\n *\tas described by the argv.\n *\n * Results:\n *\tThe return value is a count of the number of new processes\n *\tcreated, or -1 if an error occurred while creating the pipeline.\n *\t*pidArrayPtr is filled in with the address of a dynamically\n *\tallocated array giving the ids of all of the processes.  It\n *\tis up to the caller to free this array when it isn't needed\n *\tanymore.  If inPipePtr is non-NULL, *inPipePtr is filled in\n *\twith the file id for the input pipe for the pipeline (if any):\n *\tthe caller must eventually close this file.  If outPipePtr\n *\tisn't NULL, then *outPipePtr is filled in with the file id\n *\tfor the output pipe from the pipeline:  the caller must close\n *\tthis file.  If errFilePtr isn't NULL, then *errFilePtr is filled\n *\twith a file id that may be used to read error output after the\n *\tpipeline completes.\n *\n * Side effects:\n *\tProcesses and pipes are created.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTcl_CreatePipeline(interp, argc, argv, pidArrayPtr, inPipePtr,\n\toutPipePtr, errFilePtr)\n    Tcl_Interp *interp;\t\t/* Interpreter to use for error reporting. */\n    int argc;\t\t\t/* Number of entries in argv. */\n    unsigned char **argv;\t/* Array of strings describing commands in\n\t\t\t\t * pipeline plus I/O redirection with <,\n\t\t\t\t * <<, and >.  Argv[argc] must be NULL. */\n    int **pidArrayPtr;\t\t/* Word at *pidArrayPtr gets filled in with\n\t\t\t\t * address of array of pids for processes\n\t\t\t\t * in pipeline (first pid is first process\n\t\t\t\t * in pipeline). */\n    int *inPipePtr;\t\t/* If non-NULL, input to the pipeline comes\n\t\t\t\t * from a pipe (unless overridden by\n\t\t\t\t * redirection in the command).  The file\n\t\t\t\t * id with which to write to this pipe is\n\t\t\t\t * stored at *inPipePtr.  -1 means command\n\t\t\t\t * specified its own input source. */\n    int *outPipePtr;\t\t/* If non-NULL, output to the pipeline goes\n\t\t\t\t * to a pipe, unless overriden by redirection\n\t\t\t\t * in the command.  The file id with which to\n\t\t\t\t * read frome this pipe is stored at\n\t\t\t\t * *outPipePtr.  -1 means command specified\n\t\t\t\t * its own output sink. */\n    int *errFilePtr;\t\t/* If non-NULL, all stderr output from the\n\t\t\t\t * pipeline will go to a temporary file\n\t\t\t\t * created here, and a descriptor to read\n\t\t\t\t * the file will be left at *errFilePtr.\n\t\t\t\t * The file will be removed already, so\n\t\t\t\t * closing this descriptor will be the end\n\t\t\t\t * of the file.  If this is NULL, then\n\t\t\t\t * all stderr output goes to our stderr. */\n{\n    int *pidPtr = NULL;\t\t/* Points to malloc-ed array holding all\n\t\t\t\t * the pids of child processes. */\n    int numPids = 0;\t\t/* Actual number of processes that exist\n\t\t\t\t * at *pidPtr right now. */\n    int cmdCount;\t\t/* Count of number of distinct commands\n\t\t\t\t * found in argc/argv. */\n    char *input = NULL;\t\t/* Describes input for pipeline, depending\n\t\t\t\t * on \"inputFile\".  NULL means take input\n\t\t\t\t * from stdin/pipe. */\n    int inputFile = 0;\t\t/* Non-zero means input is name of input\n\t\t\t\t * file.  Zero means input holds actual\n\t\t\t\t * text to be input to command. */\n    char *output = NULL;\t/* Holds name of output file to pipe to,\n\t\t\t\t * or NULL if output goes to stdout/pipe. */\n    int inputId = -1;\t\t/* Readable file id input to current command in\n\t\t\t\t * pipeline (could be file or pipe).  -1\n\t\t\t\t * means use stdin. */\n    int outputId = -1;\t\t/* Writable file id for output from current\n\t\t\t\t * command in pipeline (could be file or pipe).\n\t\t\t\t * -1 means use stdout. */\n    int errorId = -1;\t\t/* Writable file id for all standard error\n\t\t\t\t * output from all commands in pipeline.  -1\n\t\t\t\t * means use stderr. */\n    int lastOutputId = -1;\t/* Write file id for output from last command\n\t\t\t\t * in pipeline (could be file or pipe).\n\t\t\t\t * -1 means use stdout. */\n    int pipeIds[2];\t\t/* File ids for pipe that's being created. */\n    int firstArg, lastArg;\t/* Indexes of first and last arguments in\n\t\t\t\t * current command. */\n    int lastBar;\n    char *execName;\n    int i, j, pid;\n\n    if (inPipePtr != NULL) {\n\t*inPipePtr = -1;\n    }\n    if (outPipePtr != NULL) {\n\t*outPipePtr = -1;\n    }\n    if (errFilePtr != NULL) {\n\t*errFilePtr = -1;\n    }\n    pipeIds[0] = pipeIds[1] = -1;\n\n    /*\n     * First, scan through all the arguments to figure out the structure\n     * of the pipeline.  Count the number of distinct processes (it's the\n     * number of \"|\" arguments).  If there are \"<\", \"<<\", or \">\" arguments\n     * then make note of input and output redirection and remove these\n     * arguments and the arguments that follow them.\n     */\n\n    cmdCount = 1;\n    lastBar = -1;\n    for (i = 0; i < argc; i++) {\n\tif ((argv[i][0] == '|') && ((argv[i][1] == 0))) {\n\t    if ((i == (lastBar+1)) || (i == (argc-1))) {\n\t\tinterp->result = \"illegal use of | in command\";\n\t\treturn -1;\n\t    }\n\t    lastBar = i;\n\t    cmdCount++;\n\t    continue;\n\t} else if (argv[i][0] == '<') {\n\t    if (argv[i][1] == 0) {\n\t\tinput = argv[i+1];\n\t\tinputFile = 1;\n\t    } else if ((argv[i][1] == '<') && (argv[i][2] == 0)) {\n\t\tinput = argv[i+1];\n\t\tinputFile = 0;\n\t    } else {\n\t\tcontinue;\n\t    }\n\t} else if ((argv[i][0] == '>') && (argv[i][1] == 0)) {\n\t    output = argv[i+1];\n\t} else {\n\t    continue;\n\t}\n\tif (i >= (argc-1)) {\n\t    Tcl_AppendResult(interp, \"can't specify \\\"\", argv[i],\n\t\t    \"\\\" as last word in command\", (char *) NULL);\n\t    return -1;\n\t}\n\tfor (j = i+2; j < argc; j++) {\n\t    argv[j-2] = argv[j];\n\t}\n\targc -= 2;\n\ti--;\t\t\t/* Process new arg from same position. */\n    }\n    if (argc == 0) {\n\tinterp->result =  \"didn't specify command to execute\";\n\treturn -1;\n    }\n\n    /*\n     * Set up the redirected input source for the pipeline, if\n     * so requested.\n     */\n\n    if (input != NULL) {\n\tif (!inputFile) {\n\t    /*\n\t     * Immediate data in command.  Create temporary file and\n\t     * put data into file.\n\t     */\n\n#\t    define TMP_STDIN_NAME \"/tmp/tcl.in.XXXXXX\"\n\t    char inName[sizeof(TMP_STDIN_NAME) + 1];\n\t    int length;\n\n\t    strcpy(inName, TMP_STDIN_NAME);\n\t    mktemp(inName);\n\t    inputId = open(inName, O_RDWR|O_CREAT|O_TRUNC, 0600);\n\t    if (inputId < 0) {\n\t\tTcl_AppendResult(interp,\n\t\t\t\"couldn't create input file for command: \",\n\t\t\tTcl_UnixError(interp), (char *) NULL);\n\t\tgoto error;\n\t    }\n\t    length = strlen(input);\n\t    if (write(inputId, input, length) != length) {\n\t\tTcl_AppendResult(interp,\n\t\t\t\"couldn't write file input for command: \",\n\t\t\tTcl_UnixError(interp), (char *) NULL);\n\t\tgoto error;\n\t    }\n\t    if ((lseek(inputId, 0L, 0) == -1) || (unlink(inName) == -1)) {\n\t\tTcl_AppendResult(interp,\n\t\t\t\"couldn't reset or remove input file for command: \",\n\t\t\tTcl_UnixError(interp), (char *) NULL);\n\t\tgoto error;\n\t    }\n\t} else {\n\t    /*\n\t     * File redirection.  Just open the file.\n\t     */\n\n\t    inputId = open(input, O_RDONLY, 0);\n\t    if (inputId < 0) {\n\t\tTcl_AppendResult(interp,\n\t\t\t\"couldn't read file \\\"\", input, \"\\\": \",\n\t\t\tTcl_UnixError(interp), (char *) NULL);\n\t\tgoto error;\n\t    }\n\t}\n    } else if (inPipePtr != NULL) {\n\tif (pipe(pipeIds) != 0) {\n\t    Tcl_AppendResult(interp,\n\t\t    \"couldn't create input pipe for command: \",\n\t\t    Tcl_UnixError(interp), (char *) NULL);\n\t    goto error;\n\t}\n\tinputId = pipeIds[0];\n\t*inPipePtr = pipeIds[1];\n\tpipeIds[0] = pipeIds[1] = -1;\n    }\n\n    /*\n     * Set up the redirected output sink for the pipeline from one\n     * of two places, if requested.\n     */\n\n    if (output != NULL) {\n\t/*\n\t * Output is to go to a file.\n\t */\n\n\tlastOutputId = open(output, O_WRONLY|O_CREAT|O_TRUNC, 0666);\n\tif (lastOutputId < 0) {\n\t    Tcl_AppendResult(interp,\n\t\t    \"couldn't write file \\\"\", output, \"\\\": \",\n\t\t    Tcl_UnixError(interp), (char *) NULL);\n\t    goto error;\n\t}\n    } else if (outPipePtr != NULL) {\n\t/*\n\t * Output is to go to a pipe.\n\t */\n\n\tif (pipe(pipeIds) != 0) {\n\t    Tcl_AppendResult(interp,\n\t\t    \"couldn't create output pipe: \",\n\t\t    Tcl_UnixError(interp), (char *) NULL);\n\t    goto error;\n\t}\n\tlastOutputId = pipeIds[1];\n\t*outPipePtr = pipeIds[0];\n\tpipeIds[0] = pipeIds[1] = -1;\n    }\n\n    /*\n     * Set up the standard error output sink for the pipeline, if\n     * requested.  Use a temporary file which is opened, then deleted.\n     * Could potentially just use pipe, but if it filled up it could\n     * cause the pipeline to deadlock:  we'd be waiting for processes\n     * to complete before reading stderr, and processes couldn't complete\n     * because stderr was backed up.\n     */\n\n    if (errFilePtr != NULL) {\n#\tdefine TMP_STDERR_NAME \"/tmp/tcl.err.XXXXXX\"\n\tchar errName[sizeof(TMP_STDERR_NAME) + 1];\n\n\tstrcpy(errName, TMP_STDERR_NAME);\n\tmktemp(errName);\n\terrorId = open(errName, O_WRONLY|O_CREAT|O_TRUNC, 0600);\n\tif (errorId < 0) {\n\t    errFileError:\n\t    Tcl_AppendResult(interp,\n\t\t    \"couldn't create error file for command: \",\n\t\t    Tcl_UnixError(interp), (char *) NULL);\n\t    goto error;\n\t}\n\t*errFilePtr = open(errName, O_RDONLY, 0);\n\tif (*errFilePtr < 0) {\n\t    goto errFileError;\n\t}\n\tif (unlink(errName) == -1) {\n\t    Tcl_AppendResult(interp,\n\t\t    \"couldn't remove error file for command: \",\n\t\t    Tcl_UnixError(interp), (char *) NULL);\n\t    goto error;\n\t}\n    }\n\n    /*\n     * Scan through the argc array, forking off a process for each\n     * group of arguments between \"|\" arguments.\n     */\n\n    pidPtr = (int *) malloc((unsigned) (cmdCount * sizeof(int)));\n    for (i = 0; i < numPids; i++) {\n\tpidPtr[i] = -1;\n    }\n    for (firstArg = 0; firstArg < argc; numPids++, firstArg = lastArg+1) {\n\tfor (lastArg = firstArg; lastArg < argc; lastArg++) {\n\t    if ((argv[lastArg][0] == '|') && (argv[lastArg][1] == 0)) {\n\t\tbreak;\n\t    }\n\t}\n\targv[lastArg] = NULL;\n\tif (lastArg == argc) {\n\t    outputId = lastOutputId;\n\t} else {\n\t    if (pipe(pipeIds) != 0) {\n\t\tTcl_AppendResult(interp, \"couldn't create pipe: \",\n\t\t\tTcl_UnixError(interp), (char *) NULL);\n\t\tgoto error;\n\t    }\n\t    outputId = pipeIds[1];\n\t}\n\texecName = Tcl_TildeSubst(interp, argv[firstArg]);\n\tpid = Tcl_Fork();\n\tif (pid == -1) {\n\t    Tcl_AppendResult(interp, \"couldn't fork child process: \",\n\t\t    Tcl_UnixError(interp), (char *) NULL);\n\t    goto error;\n\t}\n\tif (pid == 0) {\n\t    char errSpace[200];\n\n\t    if (((inputId != -1) && (dup2(inputId, 0) == -1))\n\t\t    || ((outputId != -1) && (dup2(outputId, 1) == -1))\n\t\t    || ((errorId != -1) && (dup2(errorId, 2) == -1))) {\n\t\tchar *err;\n\t\terr = \"forked process couldn't set up input/output\\n\";\n\t\twrite(errorId < 0 ? 2 : errorId, err, strlen(err));\n\t\t_exit(1);\n\t    }\n\t    for (i = 3; (i <= outputId) || (i <= inputId) || (i <= errorId);\n\t\t    i++) {\n\t\tclose(i);\n\t    }\n\t    execvp(execName, (char**) &argv[firstArg]);\n\t    sprintf(errSpace, \"couldn't find \\\"%.150s\\\" to execute\\n\",\n\t\t    argv[firstArg]);\n\t    write(2, errSpace, strlen(errSpace));\n\t    _exit(1);\n\t} else {\n\t    pidPtr[numPids] = pid;\n\t}\n\n\t/*\n\t * Close off our copies of file descriptors that were set up for\n\t * this child, then set up the input for the next child.\n\t */\n\n\tif (inputId != -1) {\n\t    close(inputId);\n\t}\n\tif (outputId != -1) {\n\t    close(outputId);\n\t}\n\tinputId = pipeIds[0];\n\tpipeIds[0] = pipeIds[1] = -1;\n    }\n    *pidArrayPtr = pidPtr;\n\n    /*\n     * All done.  Cleanup open files lying around and then return.\n     */\n\ncleanup:\n    if (inputId != -1) {\n\tclose(inputId);\n    }\n    if (lastOutputId != -1) {\n\tclose(lastOutputId);\n    }\n    if (errorId != -1) {\n\tclose(errorId);\n    }\n    return numPids;\n\n    /*\n     * An error occurred.  There could have been extra files open, such\n     * as pipes between children.  Clean them all up.  Detach any child\n     * processes that have been created.\n     */\n\n    error:\n    if ((inPipePtr != NULL) && (*inPipePtr != -1)) {\n\tclose(*inPipePtr);\n\t*inPipePtr = -1;\n    }\n    if ((outPipePtr != NULL) && (*outPipePtr != -1)) {\n\tclose(*outPipePtr);\n\t*outPipePtr = -1;\n    }\n    if ((errFilePtr != NULL) && (*errFilePtr != -1)) {\n\tclose(*errFilePtr);\n\t*errFilePtr = -1;\n    }\n    if (pipeIds[0] != -1) {\n\tclose(pipeIds[0]);\n    }\n    if (pipeIds[1] != -1) {\n\tclose(pipeIds[1]);\n    }\n    if (pidPtr != NULL) {\n\tfor (i = 0; i < numPids; i++) {\n\t    if (pidPtr[i] != -1) {\n\t\tTcl_DetachPids(1, &pidPtr[i]);\n\t    }\n\t}\n\tfree((char *) pidPtr);\n    }\n    numPids = -1;\n    goto cleanup;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_UnixError --\n *\n *\tThis procedure is typically called after UNIX kernel calls\n *\treturn errors.  It stores machine-readable information about\n *\tthe error in $errorCode returns an information string for\n *\tthe caller's use.\n *\n * Results:\n *\tThe return value is a human-readable string describing the\n *\terror, as returned by strerror.\n *\n * Side effects:\n *\tThe global variable $errorCode is reset.\n *\n *----------------------------------------------------------------------\n */\n\nunsigned char *\nTcl_UnixError(interp)\n    Tcl_Interp *interp;\t\t/* Interpreter whose $errorCode variable\n\t\t\t\t * is to be changed. */\n{\n    char *id;\n    const char *msg;\n\n    id = Tcl_ErrnoId();\n    msg = strerror(errno);\n    Tcl_SetErrorCode(interp, \"UNIX\", id, msg, (char *) NULL);\n    return (unsigned char *) msg;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * TclMakeFileTable --\n *\n *\tCreate or enlarge the file table for the interpreter, so that\n *\tthere is room for a given index.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tThe file table for iPtr will be created if it doesn't exist\n *\t(and entries will be added for stdin, stdout, and stderr).\n *\tIf it already exists, then it will be grown if necessary.\n *\n *----------------------------------------------------------------------\n */\n\nvoid\nTclMakeFileTable(iPtr, index)\n    Interp *iPtr;\t\t/* Interpreter whose table of files is\n\t\t\t\t * to be manipulated. */\n    int index;\t\t\t/* Make sure table is large enough to\n\t\t\t\t * hold at least this index. */\n{\n    /*\n     * If the table doesn't even exist, then create it and initialize\n     * entries for standard files.\n     */\n\n    if (iPtr->numFiles == 0) {\n\tOpenFile *filePtr;\n\tint i;\n\n\tif (index < 2) {\n\t    iPtr->numFiles = 3;\n\t} else {\n\t    iPtr->numFiles = index+1;\n\t}\n\tiPtr->filePtrArray = (OpenFile **) malloc((unsigned)\n\t\t((iPtr->numFiles)*sizeof(OpenFile *)));\n\tfor (i = iPtr->numFiles-1; i >= 0; i--) {\n\t    iPtr->filePtrArray[i] = NULL;\n\t}\n\n\tfilePtr = (OpenFile *) malloc(sizeof(OpenFile));\n\tfilePtr->f = stdin;\n\tfilePtr->f2 = NULL;\n\tfilePtr->readable = 1;\n\tfilePtr->writable = 0;\n\tfilePtr->numPids = 0;\n\tfilePtr->pidPtr = NULL;\n\tfilePtr->errorId = -1;\n\tiPtr->filePtrArray[0] = filePtr;\n\n\tfilePtr = (OpenFile *) malloc(sizeof(OpenFile));\n\tfilePtr->f = stdout;\n\tfilePtr->f2 = NULL;\n\tfilePtr->readable = 0;\n\tfilePtr->writable = 1;\n\tfilePtr->numPids = 0;\n\tfilePtr->pidPtr = NULL;\n\tfilePtr->errorId = -1;\n\tiPtr->filePtrArray[1] = filePtr;\n\n\tfilePtr = (OpenFile *) malloc(sizeof(OpenFile));\n\tfilePtr->f = stderr;\n\tfilePtr->f2 = NULL;\n\tfilePtr->readable = 0;\n\tfilePtr->writable = 1;\n\tfilePtr->numPids = 0;\n\tfilePtr->pidPtr = NULL;\n\tfilePtr->errorId = -1;\n\tiPtr->filePtrArray[2] = filePtr;\n    } else if (index >= iPtr->numFiles) {\n\tint newSize;\n\tOpenFile **newPtrArray;\n\tint i;\n\n\tnewSize = index+1;\n\tnewPtrArray = (OpenFile **) malloc((unsigned)\n\t\t((newSize)*sizeof(OpenFile *)));\n\tmemcpy((void *) newPtrArray, (void *) iPtr->filePtrArray,\n\t\tiPtr->numFiles*sizeof(OpenFile *));\n\tfor (i = iPtr->numFiles; i < newSize; i++) {\n\t    newPtrArray[i] = NULL;\n\t}\n\tfree((char *) iPtr->filePtrArray);\n\tiPtr->numFiles = newSize;\n\tiPtr->filePtrArray = newPtrArray;\n    }\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * TclGetOpenFile --\n *\n *\tGiven a string identifier for an open file, find the corresponding\n *\topen file structure, if there is one.\n *\n * Results:\n *\tA standard Tcl return value.  If the open file is successfully\n *\tlocated, *filePtrPtr is modified to point to its structure.\n *\tIf TCL_ERROR is returned then interp->result contains an error\n *\tmessage.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTclGetOpenFile(interp, string, filePtrPtr)\n    Tcl_Interp *interp;\t\t/* Interpreter in which to find file. */\n    char *string;\t\t/* String that identifies file. */\n    OpenFile **filePtrPtr;\t/* Address of word in which to store pointer\n\t\t\t\t * to structure about open file. */\n{\n    int fd = 0;\t\t\t/* Initial value needed only to stop compiler\n\t\t\t\t * warnings. */\n    Interp *iPtr = (Interp *) interp;\n\n    if ((string[0] == 'f') && (string[1] == 'i') && (string[2] == 'l')\n\t    & (string[3] == 'e')) {\n\tchar *end;\n\n\tfd = strtoul(string+4, &end, 10);\n\tif ((end == string+4) || (*end != 0)) {\n\t    goto badId;\n\t}\n    } else if ((string[0] == 's') && (string[1] == 't')\n\t    && (string[2] == 'd')) {\n\tif (strcmp(string+3, \"in\") == 0) {\n\t    fd = 0;\n\t} else if (strcmp(string+3, \"out\") == 0) {\n\t    fd = 1;\n\t} else if (strcmp(string+3, \"err\") == 0) {\n\t    fd = 2;\n\t} else {\n\t    goto badId;\n\t}\n    } else {\n\tbadId:\n\tTcl_AppendResult(interp, \"bad file identifier \\\"\", string,\n\t\t\"\\\"\", (char *) NULL);\n\treturn TCL_ERROR;\n    }\n\n    if (fd >= iPtr->numFiles) {\n\tif ((iPtr->numFiles == 0) && (fd <= 2)) {\n\t    TclMakeFileTable(iPtr, fd);\n\t} else {\n\t    notOpen:\n\t    Tcl_AppendResult(interp, \"file \\\"\", string, \"\\\" isn't open\",\n\t\t    (char *) NULL);\n\t    return TCL_ERROR;\n\t}\n    }\n    if (iPtr->filePtrArray[fd] == NULL) {\n\tgoto notOpen;\n    }\n    *filePtrPtr = iPtr->filePtrArray[fd];\n    return TCL_OK;\n}\n"
  },
  {
    "path": "lib/libtcl/tclvar.c",
    "content": "/*\n * tclVar.c --\n *\n *\tThis file contains routines that implement Tcl variables\n *\t(both scalars and arrays).\n *\n *\tThe implementation of arrays is modelled after an initial\n *\timplementation by Karl Lehenbauer, Mark Diekhans and\n *\tPeter da Silva.\n *\n * Copyright 1987-1991 Regents of the University of California\n * Permission to use, copy, modify, and distribute this\n * software and its documentation for any purpose and without\n * fee is hereby granted, provided that the above copyright\n * notice appear in all copies.  The University of California\n * makes no representations about the suitability of this\n * software for any purpose.  It is provided \"as is\" without\n * express or implied warranty.\n */\n#include \"internal.h\"\n#include <assert.h>\n\n/*\n * The strings below are used to indicate what went wrong when a\n * variable access is denied.\n */\n\nstatic unsigned char *noSuchVar\n\t= (unsigned char*) \"no such variable\";\nstatic unsigned char *isArray\n\t= (unsigned char*) \"variable is array\";\nstatic unsigned char *needArray\n\t= (unsigned char*) \"variable isn't array\";\nstatic unsigned char *noSuchElement\n\t= (unsigned char*) \"no such element in array\";\nstatic unsigned char *traceActive\n\t= (unsigned char*) \"trace is active on variable\";\n\n/*\n * Forward references to procedures defined later in this file:\n */\n\nstatic unsigned char *\tCallTraces (Interp *iPtr, Var *arrayPtr,\n\t\t\t    Tcl_HashEntry *hPtr, unsigned char *part1,\n\t\t\t    unsigned char *part2, int flags);\nstatic void\t\tDeleteSearches (Var *arrayVarPtr);\nstatic void\t\tDeleteArray (Interp *iPtr, unsigned char *arrayName,\n\t\t\t    Var *varPtr, int flags);\nstatic Var *\t\tNewVar (int space);\nstatic ArraySearch *\tParseSearchId (Tcl_Interp *interp,\n\t\t\t    Var *varPtr, unsigned char *varName, char *string);\nstatic void\t\tVarErrMsg (Tcl_Interp *interp,\n\t\t\t    unsigned char *part1, unsigned char *part2,\n\t\t\t    unsigned char *operation, unsigned char *reason);\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_GetVar --\n *\n *\tReturn the value of a Tcl variable.\n *\n * Results:\n *\tThe return value points to the current value of varName.  If\n *\tthe variable is not defined or can't be read because of a clash\n *\tin array usage then a NULL pointer is returned and an error\n *\tmessage is left in interp->result if the TCL_LEAVE_ERR_MSG\n *\tflag is set.  Note:  the return value is only valid up until\n *\tthe next call to Tcl_SetVar or Tcl_SetVar2;  if you depend on\n *\tthe value lasting longer than that, then make yourself a private\n *\tcopy.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nunsigned char *\nTcl_GetVar(interp, varName, flags)\n    Tcl_Interp *interp;\t\t/* Command interpreter in which varName is\n\t\t\t\t * to be looked up. */\n    unsigned char *varName;\t/* Name of a variable in interp. */\n    int flags;\t\t\t/* OR-ed combination of TCL_GLOBAL_ONLY\n\t\t\t\t * or TCL_LEAVE_ERR_MSG bits. */\n{\n    register unsigned char *p;\n\n    /*\n     * If varName refers to an array (it ends with a parenthesized\n     * element name), then handle it specially.\n     */\n\n    for (p = varName; *p != '\\0'; p++) {\n\tif (*p == '(') {\n\t    unsigned char *result;\n\t    unsigned char *open = p;\n\n\t    do {\n\t\tp++;\n\t    } while (*p != '\\0');\n\t    p--;\n\t    if (*p != ')') {\n\t\tgoto scalar;\n\t    }\n\t    *open = '\\0';\n\t    *p = '\\0';\n\t    result = Tcl_GetVar2(interp, varName, open+1, flags);\n\t    *open = '(';\n\t    *p = ')';\n\t    return result;\n\t}\n    }\n\n    scalar:\n    return Tcl_GetVar2(interp, varName, 0, flags);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_GetVar2 --\n *\n *\tReturn the value of a Tcl variable, given a two-part name\n *\tconsisting of array name and element within array.\n *\n * Results:\n *\tThe return value points to the current value of the variable\n *\tgiven by part1 and part2.  If the specified variable doesn't\n *\texist, or if there is a clash in array usage, then NULL is\n *\treturned and a message will be left in interp->result if the\n *\tTCL_LEAVE_ERR_MSG flag is set.  Note:  the return value is\n *\tonly valid up until the next call to Tcl_SetVar or Tcl_SetVar2;\n *\tif you depend on the value lasting longer than that, then make\n *\tyourself a private copy.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nunsigned char *\nTcl_GetVar2(interp, part1, part2, flags)\n    Tcl_Interp *interp;\t\t/* Command interpreter in which variable is\n\t\t\t\t * to be looked up. */\n    unsigned char *part1;\t/* Name of array (if part2 is NULL) or\n\t\t\t\t * name of variable. */\n    unsigned char *part2;\t/* If non-null, gives name of element in\n\t\t\t\t * array. */\n    int flags;\t\t\t/* OR-ed combination of TCL_GLOBAL_ONLY\n\t\t\t\t * or TCL_LEAVE_ERR_MSG bits. */\n{\n    Tcl_HashEntry *hPtr;\n    Var *varPtr;\n    Interp *iPtr = (Interp *) interp;\n    Var *arrayPtr = 0;\n\n    /*\n     * Lookup the first name.\n     */\n\n    if ((flags & TCL_GLOBAL_ONLY) || (iPtr->varFramePtr == 0)) {\n\thPtr = Tcl_FindHashEntry(&iPtr->globalTable, part1);\n    } else {\n\thPtr = Tcl_FindHashEntry(&iPtr->varFramePtr->varTable, part1);\n    }\n    if (hPtr == 0) {\n\tif (flags & TCL_LEAVE_ERR_MSG) {\n\t    VarErrMsg(interp, part1, part2, (unsigned char*) \"read\", noSuchVar);\n\t}\n\treturn 0;\n    }\n    varPtr = (Var *) Tcl_GetHashValue(hPtr);\n    if (varPtr->flags & VAR_UPVAR) {\n\thPtr = varPtr->value.upvarPtr;\n\tvarPtr = (Var *) Tcl_GetHashValue(hPtr);\n    }\n\n    /*\n     * If this is an array reference, then remember the traces on the array\n     * and lookup the element within the array.\n     */\n    if (part2 != 0) {\n\tif (varPtr->flags & VAR_UNDEFINED) {\n\t    if (flags & TCL_LEAVE_ERR_MSG) {\n\t\tVarErrMsg(interp, part1, part2, (unsigned char*) \"read\", noSuchVar);\n\t    }\n\t    return 0;\n\t} else if (!(varPtr->flags & VAR_ARRAY)) {\n\t    if (flags & TCL_LEAVE_ERR_MSG) {\n\t\tVarErrMsg(interp, part1, part2, (unsigned char*) \"read\", needArray);\n\t    }\n\t    return 0;\n\t}\n\tarrayPtr = varPtr;\n\thPtr = Tcl_FindHashEntry(varPtr->value.tablePtr, part2);\n\tif (hPtr == 0) {\n\t    if (flags & TCL_LEAVE_ERR_MSG) {\n\t\tVarErrMsg(interp, part1, part2, (unsigned char*) \"read\", noSuchElement);\n\t    }\n\t    return 0;\n\t}\n\tvarPtr = (Var *) Tcl_GetHashValue(hPtr);\n    }\n\n    /*\n     * Invoke any traces that have been set for the variable.\n     */\n\n    if ((varPtr->tracePtr != 0)\n\t    || ((arrayPtr != 0) && (arrayPtr->tracePtr != 0))) {\n\tunsigned char *msg;\n\n\tmsg = CallTraces(iPtr, arrayPtr, hPtr, part1, part2,\n\t\t(flags & TCL_GLOBAL_ONLY) | TCL_TRACE_READS);\n\tif (msg != 0) {\n\t    VarErrMsg(interp, part1, part2, (unsigned char*) \"read\", msg);\n\t    return 0;\n\t}\n\n\t/*\n\t * Watch out!  The variable could have gotten re-allocated to\n\t * a larger size.  Fortunately the hash table entry will still\n\t * be around.\n\t */\n\n\tvarPtr = (Var *) Tcl_GetHashValue(hPtr);\n    }\n    if (varPtr->flags & (VAR_UNDEFINED|VAR_UPVAR|VAR_ARRAY)) {\n\tif (flags & TCL_LEAVE_ERR_MSG) {\n\t    VarErrMsg(interp, part1, part2, (unsigned char*) \"read\", noSuchVar);\n\t}\n\treturn 0;\n    }\n    return varPtr->value.string;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_SetVar --\n *\n *\tChange the value of a variable.\n *\n * Results:\n *\tReturns a pointer to the malloc'ed string holding the new\n *\tvalue of the variable.  The caller should not modify this\n *\tstring.  If the write operation was disallowed then NULL\n *\tis returned;  if the TCL_LEAVE_ERR_MSG flag is set, then\n *\tan explanatory message will be left in interp->result.\n *\n * Side effects:\n *\tIf varName is defined as a local or global variable in interp,\n *\tits value is changed to newValue.  If varName isn't currently\n *\tdefined, then a new global variable by that name is created.\n *\n *----------------------------------------------------------------------\n */\n\nunsigned char *\nTcl_SetVar(interp, varName, newValue, flags)\n    Tcl_Interp *interp;\t\t/* Command interpreter in which varName is\n\t\t\t\t * to be looked up. */\n    unsigned char *varName;\t/* Name of a variable in interp. */\n    unsigned char *newValue;\t/* New value for varName. */\n    int flags;\t\t\t/* Various flags that tell how to set value:\n\t\t\t\t * any of TCL_GLOBAL_ONLY, TCL_APPEND_VALUE,\n\t\t\t\t * TCL_LIST_ELEMENT, TCL_NO_SPACE, or\n\t\t\t\t * TCL_LEAVE_ERR_MSG. */\n{\n    register unsigned char *p;\n\n    /*\n     * If varName refers to an array (it ends with a parenthesized\n     * element name), then handle it specially.\n     */\n\n    for (p = varName; *p != '\\0'; p++) {\n\tif (*p == '(') {\n\t    unsigned char *result;\n\t    unsigned char *open = p;\n\n\t    do {\n\t\tp++;\n\t    } while (*p != '\\0');\n\t    p--;\n\t    if (*p != ')') {\n\t\tgoto scalar;\n\t    }\n\t    *open = '\\0';\n\t    *p = '\\0';\n\t    result = Tcl_SetVar2(interp, varName, open+1, newValue, flags);\n\t    *open = '(';\n\t    *p = ')';\n\t    return result;\n\t}\n    }\n\n    scalar:\n    return Tcl_SetVar2(interp, varName, 0, newValue, flags);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_SetVar2 --\n *\n *\tGiven a two-part variable name, which may refer either to a\n *\tscalar variable or an element of an array, change the value\n *\tof the variable.  If the named scalar or array or element\n *\tdoesn't exist then create one.\n *\n * Results:\n *\tReturns a pointer to the malloc'ed string holding the new\n *\tvalue of the variable.  The caller should not modify this\n *\tstring.  If the write operation was disallowed because an\n *\tarray was expected but not found (or vice versa), then NULL\n *\tis returned;  if the TCL_LEAVE_ERR_MSG flag is set, then\n *\tan explanatory message will be left in interp->result.\n *\n * Side effects:\n *\tThe value of the given variable is set.  If either the array\n *\tor the entry didn't exist then a new one is created.\n *\n *----------------------------------------------------------------------\n */\n\nunsigned char *\nTcl_SetVar2(interp, part1, part2, newValue, flags)\n    Tcl_Interp *interp;\t\t/* Command interpreter in which variable is\n\t\t\t\t * to be looked up. */\n    unsigned char *part1;\t/* If part2 is NULL, this is name of scalar\n\t\t\t\t * variable.  Otherwise it is name of array. */\n    unsigned char *part2;\t/* Name of an element within array, or NULL. */\n    unsigned char *newValue;\t/* New value for variable. */\n    int flags;\t\t\t/* Various flags that tell how to set value:\n\t\t\t\t * any of TCL_GLOBAL_ONLY, TCL_APPEND_VALUE,\n\t\t\t\t * TCL_LIST_ELEMENT, and TCL_NO_SPACE, or\n\t\t\t\t * TCL_LEAVE_ERR_MSG . */\n{\n    Tcl_HashEntry *hPtr;\n    register Var *varPtr = 0;\n\t\t\t\t/* Initial value only used to stop compiler\n\t\t\t\t * from complaining; not really needed. */\n    register Interp *iPtr = (Interp *) interp;\n    int length, new, listFlags;\n    Var *arrayPtr = 0;\n\n    /*\n     * Lookup the first name.\n     */\n\n    if ((flags & TCL_GLOBAL_ONLY) || (iPtr->varFramePtr == 0)) {\n\thPtr = Tcl_CreateHashEntry(&iPtr->globalTable, part1, &new);\n    } else {\n\thPtr = Tcl_CreateHashEntry(&iPtr->varFramePtr->varTable,\n\t\tpart1, &new);\n    }\n    if (!new) {\n\tvarPtr = (Var *) Tcl_GetHashValue(hPtr);\n\tif (varPtr->flags & VAR_UPVAR) {\n\t    hPtr = varPtr->value.upvarPtr;\n\t    varPtr = (Var *) Tcl_GetHashValue(hPtr);\n\t}\n    }\n\n    /*\n     * If this is an array reference, then create a new array (if\n     * needed), remember any traces on the array, and lookup the\n     * element within the array.\n     */\n\n    if (part2 != 0) {\n\tif (new) {\n\t    varPtr = NewVar (0);\n\t    Tcl_SetHashValue(hPtr, varPtr);\n\t    varPtr->flags = VAR_ARRAY;\n\t    varPtr->value.tablePtr = (Tcl_HashTable*)\n\t\t    malloc (sizeof(Tcl_HashTable));\n\t    Tcl_InitHashTable (varPtr->value.tablePtr, TCL_STRING_KEYS);\n\t} else {\n\t    if (varPtr->flags & VAR_UNDEFINED) {\n\t\tvarPtr->flags = VAR_ARRAY;\n\t\tvarPtr->value.tablePtr = (Tcl_HashTable*)\n\t\t\tmalloc (sizeof(Tcl_HashTable));\n\t\tTcl_InitHashTable (varPtr->value.tablePtr, TCL_STRING_KEYS);\n\t    } else if (!(varPtr->flags & VAR_ARRAY)) {\n\t\tif (flags & TCL_LEAVE_ERR_MSG) {\n\t\t    VarErrMsg(interp, part1, part2, (unsigned char*) \"set\", needArray);\n\t\t}\n\t\treturn 0;\n\t    }\n\t    arrayPtr = varPtr;\n\t}\n\thPtr = Tcl_CreateHashEntry(varPtr->value.tablePtr, part2, &new);\n    }\n\n    /*\n     * Compute how many bytes will be needed for newValue (leave space\n     * for a separating space between list elements).\n     */\n\n    if (flags & TCL_LIST_ELEMENT) {\n\tlength = Tcl_ScanElement(newValue, &listFlags) + 1;\n    } else {\n\tlength = strlen(newValue);\n    }\n\n    /*\n     * If the variable doesn't exist then create a new one.  If it\n     * does exist then clear its current value unless this is an\n     * append operation.\n     */\n\n    if (new) {\n\tvarPtr = NewVar (length);\n\tTcl_SetHashValue(hPtr, varPtr);\n\tif ((arrayPtr != 0) && (arrayPtr->searchPtr != 0)) {\n\t    DeleteSearches(arrayPtr);\n\t}\n    } else {\n\tvarPtr = (Var *) Tcl_GetHashValue(hPtr);\n\tif (varPtr->flags & VAR_ARRAY) {\n\t    if (flags & TCL_LEAVE_ERR_MSG) {\n\t\tVarErrMsg(interp, part1, part2, (unsigned char*) \"set\", isArray);\n\t    }\n\t    return 0;\n\t}\n\tif (!(flags & TCL_APPEND_VALUE) || (varPtr->flags & VAR_UNDEFINED)) {\n\t    varPtr->valueLength = 0;\n\t}\n    }\n\n    /*\n     * Make sure there's enough space to hold the variable's\n     * new value.  If not, enlarge the variable's space.\n     */\n\n    if ((length + varPtr->valueLength) >= varPtr->valueSpace) {\n\tVar *newVarPtr;\n\tint newSize;\n\n\tnewSize = 2*varPtr->valueSpace;\n\tif (newSize <= (length + varPtr->valueLength)) {\n\t    newSize += length;\n\t}\n\tnewVarPtr = NewVar (newSize);\n\tnewVarPtr->valueLength = varPtr->valueLength;\n\tnewVarPtr->upvarUses = varPtr->upvarUses;\n\tnewVarPtr->tracePtr = varPtr->tracePtr;\n\tnewVarPtr->searchPtr = varPtr->searchPtr;\n\tnewVarPtr->flags = varPtr->flags;\n\tstrcpy(newVarPtr->value.string, varPtr->value.string);\n\tTcl_SetHashValue(hPtr, newVarPtr);\n\tfree (varPtr);\n\tvarPtr = newVarPtr;\n    }\n\n    /*\n     * Append the new value to the variable, either as a list\n     * element or as a string.\n     */\n\n    if (flags & TCL_LIST_ELEMENT) {\n\tif ((varPtr->valueLength > 0) && !(flags & TCL_NO_SPACE)) {\n\t    varPtr->value.string[varPtr->valueLength] = ' ';\n\t    varPtr->valueLength++;\n\t}\n\tvarPtr->valueLength += Tcl_ConvertElement(newValue,\n\t\tvarPtr->value.string + varPtr->valueLength, listFlags);\n\tvarPtr->value.string[varPtr->valueLength] = 0;\n    } else {\n\tstrcpy(varPtr->value.string + varPtr->valueLength, newValue);\n\tvarPtr->valueLength += length;\n    }\n    varPtr->flags &= ~VAR_UNDEFINED;\n\n    /*\n     * Invoke any write traces for the variable.\n     */\n\n    if ((varPtr->tracePtr != 0)\n\t    || ((arrayPtr != 0) && (arrayPtr->tracePtr != 0))) {\n\tunsigned char *msg;\n\n\tmsg = CallTraces(iPtr, arrayPtr, hPtr, part1, part2,\n\t\t(flags & TCL_GLOBAL_ONLY) | TCL_TRACE_WRITES);\n\tif (msg != 0) {\n\t    VarErrMsg(interp, part1, part2, (unsigned char*) \"set\", msg);\n\t    return 0;\n\t}\n\n\t/*\n\t * Watch out!  The variable could have gotten re-allocated to\n\t * a larger size.  Fortunately the hash table entry will still\n\t * be around.\n\t */\n\n\tvarPtr = (Var *) Tcl_GetHashValue(hPtr);\n    }\n    return varPtr->value.string;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_UnsetVar --\n *\n *\tDelete a variable, so that it may not be accessed anymore.\n *\n * Results:\n *\tReturns 0 if the variable was successfully deleted, -1\n *\tif the variable can't be unset.  In the event of an error,\n *\tif the TCL_LEAVE_ERR_MSG flag is set then an error message\n *\tis left in interp->result.\n *\n * Side effects:\n *\tIf varName is defined as a local or global variable in interp,\n *\tit is deleted.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTcl_UnsetVar(interp, varName, flags)\n    Tcl_Interp *interp;\t\t/* Command interpreter in which varName is\n\t\t\t\t * to be looked up. */\n    unsigned char *varName;\t/* Name of a variable in interp.  May be\n\t\t\t\t * either a scalar name or an array name\n\t\t\t\t * or an element in an array. */\n    int flags;\t\t\t/* OR-ed combination of any of\n\t\t\t\t * TCL_GLOBAL_ONLY or TCL_LEAVE_ERR_MSG. */\n{\n    register unsigned char *p;\n    int result;\n\n    /*\n     * Figure out whether this is an array reference, then call\n     * Tcl_UnsetVar2 to do all the real work.\n     */\n\n    for (p = varName; *p != '\\0'; p++) {\n\tif (*p == '(') {\n\t    unsigned char *open = p;\n\n\t    do {\n\t\tp++;\n\t    } while (*p != '\\0');\n\t    p--;\n\t    if (*p != ')') {\n\t\tgoto scalar;\n\t    }\n\t    *open = '\\0';\n\t    *p = '\\0';\n\t    result = Tcl_UnsetVar2(interp, varName, open+1, flags);\n\t    *open = '(';\n\t    *p = ')';\n\t    return result;\n\t}\n    }\n\n    scalar:\n    return Tcl_UnsetVar2(interp, varName, 0, flags);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_UnsetVar2 --\n *\n *\tDelete a variable, given a 2-part name.\n *\n * Results:\n *\tReturns 0 if the variable was successfully deleted, -1\n *\tif the variable can't be unset.  In the event of an error,\n *\tif the TCL_LEAVE_ERR_MSG flag is set then an error message\n *\tis left in interp->result.\n *\n * Side effects:\n *\tIf part1 and part2 indicate a local or global variable in interp,\n *\tit is deleted.  If part1 is an array name and part2 is NULL, then\n *\tthe whole array is deleted.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTcl_UnsetVar2(interp, part1, part2, flags)\n    Tcl_Interp *interp;\t\t/* Command interpreter in which varName is\n\t\t\t\t * to be looked up. */\n    unsigned char *part1;\t/* Name of variable or array. */\n    unsigned char *part2;\t/* Name of element within array or NULL. */\n    int flags;\t\t\t/* OR-ed combination of any of\n\t\t\t\t * TCL_GLOBAL_ONLY or TCL_LEAVE_ERR_MSG. */\n{\n    Tcl_HashEntry *hPtr, dummyEntry;\n    Var *varPtr, dummyVar;\n    Interp *iPtr = (Interp *) interp;\n    Var *arrayPtr = 0;\n\n    if ((flags & TCL_GLOBAL_ONLY) || (iPtr->varFramePtr == 0)) {\n\thPtr = Tcl_FindHashEntry(&iPtr->globalTable, part1);\n    } else {\n\thPtr = Tcl_FindHashEntry(&iPtr->varFramePtr->varTable, part1);\n    }\n    if (hPtr == 0) {\n\tif (flags & TCL_LEAVE_ERR_MSG) {\n\t    VarErrMsg(interp, part1, part2, (unsigned char*) \"unset\", noSuchVar);\n\t}\n\treturn -1;\n    }\n    varPtr = (Var *) Tcl_GetHashValue(hPtr);\n\n    /*\n     * For global variables referenced in procedures, leave the procedure's\n     * reference variable in place, but unset the global variable.  Can't\n     * decrement the actual variable's use count, since we didn't delete\n     * the reference variable.\n     */\n\n    if (varPtr->flags & VAR_UPVAR) {\n\thPtr = varPtr->value.upvarPtr;\n\tvarPtr = (Var *) Tcl_GetHashValue(hPtr);\n    }\n\n    /*\n     * If the variable being deleted is an element of an array, then\n     * remember trace procedures on the overall array and find the\n     * element to delete.\n     */\n\n    if (part2 != 0) {\n\tif (!(varPtr->flags & VAR_ARRAY)) {\n\t    if (flags & TCL_LEAVE_ERR_MSG) {\n\t\tVarErrMsg(interp, part1, part2, (unsigned char*) \"unset\", needArray);\n\t    }\n\t    return -1;\n\t}\n\tif (varPtr->searchPtr != 0) {\n\t    DeleteSearches(varPtr);\n\t}\n\tarrayPtr = varPtr;\n\thPtr = Tcl_FindHashEntry(varPtr->value.tablePtr, part2);\n\tif (hPtr == 0) {\n\t    if (flags & TCL_LEAVE_ERR_MSG) {\n\t\tVarErrMsg(interp, part1, part2, (unsigned char*) \"unset\", noSuchElement);\n\t    }\n\t    return -1;\n\t}\n\tvarPtr = (Var *) Tcl_GetHashValue(hPtr);\n    }\n\n    /*\n     * If there is a trace active on this variable or if the variable\n     * is already being deleted then don't delete the variable:  it\n     * isn't safe, since there are procedures higher up on the stack\n     * that will use pointers to the variable.  Also don't delete an\n     * array if there are traces active on any of its elements.\n     */\n\n    if (varPtr->flags &\n\t    (VAR_TRACE_ACTIVE|VAR_ELEMENT_ACTIVE)) {\n\tif (flags & TCL_LEAVE_ERR_MSG) {\n\t    VarErrMsg(interp, part1, part2, (unsigned char*) \"unset\", traceActive);\n\t}\n\treturn -1;\n    }\n\n    /*\n     * The code below is tricky, because of the possibility that\n     * a trace procedure might try to access a variable being\n     * deleted.  To handle this situation gracefully, copy the\n     * contents of the variable and its hash table entry to\n     * dummy variables, then clean up the actual variable so that\n     * it's been completely deleted before the traces are called.\n     * Then call the traces, and finally clean up the variable's\n     * storage using the dummy copies.\n     */\n\n    dummyVar = *varPtr;\n    Tcl_SetHashValue(&dummyEntry, &dummyVar);\n    if (varPtr->upvarUses == 0) {\n\tTcl_DeleteHashEntry(hPtr);\n\tfree (varPtr);\n    } else {\n\tvarPtr->flags = VAR_UNDEFINED;\n\tvarPtr->tracePtr = 0;\n    }\n\n    /*\n     * Call trace procedures for the variable being deleted and delete\n     * its traces.\n     */\n\n    if ((dummyVar.tracePtr != 0)\n\t    || ((arrayPtr != 0) && (arrayPtr->tracePtr != 0))) {\n\t(void) CallTraces(iPtr, arrayPtr, &dummyEntry, part1, part2,\n\t\t(flags & TCL_GLOBAL_ONLY) | TCL_TRACE_UNSETS);\n\twhile (dummyVar.tracePtr != 0) {\n\t    VarTrace *tracePtr = dummyVar.tracePtr;\n\t    dummyVar.tracePtr = tracePtr->nextPtr;\n\t    free (tracePtr);\n\t}\n    }\n\n    /*\n     * If the variable is an array, delete all of its elements.  This\n     * must be done after calling the traces on the array, above (that's\n     * the way traces are defined).\n     */\n\n    if (dummyVar.flags & VAR_ARRAY) {\n\tDeleteArray(iPtr, part1, &dummyVar,\n\t    (flags & TCL_GLOBAL_ONLY) | TCL_TRACE_UNSETS);\n    }\n    if (dummyVar.flags & VAR_UNDEFINED) {\n\tif (flags & TCL_LEAVE_ERR_MSG) {\n\t    VarErrMsg(interp, part1, part2, (unsigned char*) \"unset\",\n\t\t    (part2 == 0) ? noSuchVar : noSuchElement);\n\t}\n\treturn -1;\n    }\n    return 0;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_TraceVar --\n *\n *\tArrange for reads and/or writes to a variable to cause a\n *\tprocedure to be invoked, which can monitor the operations\n *\tand/or change their actions.\n *\n * Results:\n *\tA standard Tcl return value.\n *\n * Side effects:\n *\tA trace is set up on the variable given by varName, such that\n *\tfuture references to the variable will be intermediated by\n *\tproc.  See the manual entry for complete details on the calling\n *\tsequence for proc.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTcl_TraceVar(interp, varName, flags, proc, clientData)\n    Tcl_Interp *interp;\t\t/* Interpreter in which variable is\n\t\t\t\t * to be traced. */\n    unsigned char *varName;\t/* Name of variable;  may end with \"(index)\"\n\t\t\t\t * to signify an array reference. */\n    int flags;\t\t\t/* OR-ed collection of bits, including any\n\t\t\t\t * of TCL_TRACE_READS, TCL_TRACE_WRITES,\n\t\t\t\t * TCL_TRACE_UNSETS, and TCL_GLOBAL_ONLY. */\n    Tcl_VarTraceProc *proc;\t/* Procedure to call when specified ops are\n\t\t\t\t * invoked upon varName. */\n    void *clientData;\t\t/* Arbitrary argument to pass to proc. */\n{\n    register unsigned char *p;\n\n    /*\n     * If varName refers to an array (it ends with a parenthesized\n     * element name), then handle it specially.\n     */\n\n    for (p = varName; *p != '\\0'; p++) {\n\tif (*p == '(') {\n\t    int result;\n\t    unsigned char *open = p;\n\n\t    do {\n\t\tp++;\n\t    } while (*p != '\\0');\n\t    p--;\n\t    if (*p != ')') {\n\t\tgoto scalar;\n\t    }\n\t    *open = '\\0';\n\t    *p = '\\0';\n\t    result = Tcl_TraceVar2(interp, varName, open+1, flags,\n\t\t    proc, clientData);\n\t    *open = '(';\n\t    *p = ')';\n\t    return result;\n\t}\n    }\n\n    scalar:\n    return Tcl_TraceVar2(interp, varName, 0, flags, proc, clientData);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_TraceVar2 --\n *\n *\tArrange for reads and/or writes to a variable to cause a\n *\tprocedure to be invoked, which can monitor the operations\n *\tand/or change their actions.\n *\n * Results:\n *\tA standard Tcl return value.\n *\n * Side effects:\n *\tA trace is set up on the variable given by part1 and part2, such\n *\tthat future references to the variable will be intermediated by\n *\tproc.  See the manual entry for complete details on the calling\n *\tsequence for proc.\n *\n *----------------------------------------------------------------------\n */\n\nint\nTcl_TraceVar2(interp, part1, part2, flags, proc, clientData)\n    Tcl_Interp *interp;\t\t/* Interpreter in which variable is\n\t\t\t\t * to be traced. */\n    unsigned char *part1;\t/* Name of scalar variable or array. */\n    unsigned char *part2;\t/* Name of element within array;  NULL means\n\t\t\t\t * trace applies to scalar variable or array\n\t\t\t\t * as-a-whole. */\n    int flags;\t\t\t/* OR-ed collection of bits, including any\n\t\t\t\t * of TCL_TRACE_READS, TCL_TRACE_WRITES,\n\t\t\t\t * TCL_TRACE_UNSETS, and TCL_GLOBAL_ONLY. */\n    Tcl_VarTraceProc *proc;\t/* Procedure to call when specified ops are\n\t\t\t\t * invoked upon varName. */\n    void *clientData;\t\t/* Arbitrary argument to pass to proc. */\n{\n    Tcl_HashEntry *hPtr;\n    Var *varPtr = 0;\t\t/* Initial value only used to stop compiler\n\t\t\t\t * from complaining; not really needed. */\n    Interp *iPtr = (Interp *) interp;\n    register VarTrace *tracePtr;\n    int new;\n\n    /*\n     * Locate the variable, making a new (undefined) one if necessary.\n     */\n\n    if ((flags & TCL_GLOBAL_ONLY) || (iPtr->varFramePtr == 0)) {\n\thPtr = Tcl_CreateHashEntry(&iPtr->globalTable, part1, &new);\n    } else {\n\thPtr = Tcl_CreateHashEntry(&iPtr->varFramePtr->varTable, part1, &new);\n    }\n    if (!new) {\n\tvarPtr = (Var *) Tcl_GetHashValue(hPtr);\n\tif (varPtr->flags & VAR_UPVAR) {\n\t    hPtr = varPtr->value.upvarPtr;\n\t    varPtr = (Var *) Tcl_GetHashValue(hPtr);\n\t}\n    }\n\n    /*\n     * If the trace is to be on an array element, make sure that the\n     * variable is an array variable.  If the variable doesn't exist\n     * then define it as an empty array.  Then find the specific\n     * array element.\n     */\n\n    if (part2 != 0) {\n\tif (new) {\n\t    varPtr = NewVar (0);\n\t    Tcl_SetHashValue(hPtr, varPtr);\n\t    varPtr->flags = VAR_ARRAY;\n\t    varPtr->value.tablePtr = (Tcl_HashTable*)\n\t\tmalloc (sizeof(Tcl_HashTable));\n\t    Tcl_InitHashTable (varPtr->value.tablePtr, TCL_STRING_KEYS);\n\t} else {\n\t    if (varPtr->flags & VAR_UNDEFINED) {\n\t\tvarPtr->flags = VAR_ARRAY;\n\t\tvarPtr->value.tablePtr = (Tcl_HashTable*)\n\t\t    malloc (sizeof(Tcl_HashTable));\n\t\tTcl_InitHashTable (varPtr->value.tablePtr, TCL_STRING_KEYS);\n\t    } else if (!(varPtr->flags & VAR_ARRAY)) {\n\t\tiPtr->result = needArray;\n\t\treturn TCL_ERROR;\n\t    }\n\t}\n\thPtr = Tcl_CreateHashEntry(varPtr->value.tablePtr, part2, &new);\n    }\n\n    if (new) {\n\tif ((part2 != 0) && (varPtr->searchPtr != 0)) {\n\t    DeleteSearches(varPtr);\n\t}\n\tvarPtr = NewVar (0);\n\tvarPtr->flags = VAR_UNDEFINED;\n\tTcl_SetHashValue(hPtr, varPtr);\n    } else {\n\tvarPtr = (Var *) Tcl_GetHashValue(hPtr);\n    }\n\n    /*\n     * Set up trace information.\n     */\n\n    tracePtr = (VarTrace*) malloc (sizeof(VarTrace));\n    tracePtr->traceProc = proc;\n    tracePtr->clientData = clientData;\n    tracePtr->flags = flags &\n\t    (TCL_TRACE_READS|TCL_TRACE_WRITES|TCL_TRACE_UNSETS);\n    tracePtr->nextPtr = varPtr->tracePtr;\n    varPtr->tracePtr = tracePtr;\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_UntraceVar --\n *\n *\tRemove a previously-created trace for a variable.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tIf there exists a trace for the variable given by varName\n *\twith the given flags, proc, and clientData, then that trace\n *\tis removed.\n *\n *----------------------------------------------------------------------\n */\n\nvoid\nTcl_UntraceVar(interp, varName, flags, proc, clientData)\n    Tcl_Interp *interp;\t\t/* Interpreter containing traced variable. */\n    unsigned char *varName;\t/* Name of variable;  may end with \"(index)\"\n\t\t\t\t * to signify an array reference. */\n    int flags;\t\t\t/* OR-ed collection of bits describing\n\t\t\t\t * current trace, including any of\n\t\t\t\t * TCL_TRACE_READS, TCL_TRACE_WRITES,\n\t\t\t\t * TCL_TRACE_UNSETS, and TCL_GLOBAL_ONLY. */\n    Tcl_VarTraceProc *proc;\t/* Procedure assocated with trace. */\n    void *clientData;\t\t/* Arbitrary argument to pass to proc. */\n{\n    register unsigned char *p;\n\n    /*\n     * If varName refers to an array (it ends with a parenthesized\n     * element name), then handle it specially.\n     */\n\n    for (p = varName; *p != '\\0'; p++) {\n\tif (*p == '(') {\n\t    unsigned char *open = p;\n\n\t    do {\n\t\tp++;\n\t    } while (*p != '\\0');\n\t    p--;\n\t    if (*p != ')') {\n\t\tgoto scalar;\n\t    }\n\t    *open = '\\0';\n\t    *p = '\\0';\n\t    Tcl_UntraceVar2(interp, varName, open+1, flags, proc, clientData);\n\t    *open = '(';\n\t    *p = ')';\n\t    return;\n\t}\n    }\n\n    scalar:\n    Tcl_UntraceVar2(interp, varName, 0, flags, proc, clientData);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_UntraceVar2 --\n *\n *\tRemove a previously-created trace for a variable.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tIf there exists a trace for the variable given by part1\n *\tand part2 with the given flags, proc, and clientData, then\n *\tthat trace is removed.\n *\n *----------------------------------------------------------------------\n */\n\nvoid\nTcl_UntraceVar2(interp, part1, part2, flags, proc, clientData)\n    Tcl_Interp *interp;\t\t/* Interpreter containing traced variable. */\n    unsigned char *part1;\t/* Name of variable or array. */\n    unsigned char *part2;\t/* Name of element within array;  NULL means\n\t\t\t\t * trace applies to scalar variable or array\n\t\t\t\t * as-a-whole. */\n    int flags;\t\t\t/* OR-ed collection of bits describing\n\t\t\t\t * current trace, including any of\n\t\t\t\t * TCL_TRACE_READS, TCL_TRACE_WRITES,\n\t\t\t\t * TCL_TRACE_UNSETS, and TCL_GLOBAL_ONLY. */\n    Tcl_VarTraceProc *proc;\t/* Procedure assocated with trace. */\n    void *clientData;\t\t/* Arbitrary argument to pass to proc. */\n{\n    register VarTrace *tracePtr;\n    VarTrace *prevPtr;\n    Var *varPtr;\n    Interp *iPtr = (Interp *) interp;\n    Tcl_HashEntry *hPtr;\n    ActiveVarTrace *activePtr;\n\n    /*\n     * First, lookup the variable.\n     */\n\n    if ((flags & TCL_GLOBAL_ONLY) || (iPtr->varFramePtr == 0)) {\n\thPtr = Tcl_FindHashEntry(&iPtr->globalTable, part1);\n    } else {\n\thPtr = Tcl_FindHashEntry(&iPtr->varFramePtr->varTable, part1);\n    }\n    if (hPtr == 0) {\n\treturn;\n    }\n    varPtr = (Var *) Tcl_GetHashValue(hPtr);\n    if (varPtr->flags & VAR_UPVAR) {\n\thPtr = varPtr->value.upvarPtr;\n\tvarPtr = (Var *) Tcl_GetHashValue(hPtr);\n    }\n    if (part2 != 0) {\n\tif (!(varPtr->flags & VAR_ARRAY)) {\n\t    return;\n\t}\n\thPtr = Tcl_FindHashEntry(varPtr->value.tablePtr, part2);\n\tif (hPtr == 0) {\n\t    return;\n\t}\n\tvarPtr = (Var *) Tcl_GetHashValue(hPtr);\n    }\n\n    flags &= (TCL_TRACE_READS | TCL_TRACE_WRITES | TCL_TRACE_UNSETS);\n    for (tracePtr = varPtr->tracePtr, prevPtr = 0; ;\n\t    prevPtr = tracePtr, tracePtr = tracePtr->nextPtr) {\n\tif (tracePtr == 0) {\n\t    return;\n\t}\n\tif ((tracePtr->traceProc == proc) && (tracePtr->flags == flags)\n\t\t&& (tracePtr->clientData == clientData)) {\n\t    break;\n\t}\n    }\n\n    /*\n     * The code below makes it possible to delete traces while traces\n     * are active:  it makes sure that the deleted trace won't be\n     * processed by CallTraces.\n     */\n\n    for (activePtr = iPtr->activeTracePtr; activePtr != 0;\n\t    activePtr = activePtr->nextPtr) {\n\tif (activePtr->nextTracePtr == tracePtr) {\n\t    activePtr->nextTracePtr = tracePtr->nextPtr;\n\t}\n    }\n    if (prevPtr == 0) {\n\tvarPtr->tracePtr = tracePtr->nextPtr;\n    } else {\n\tprevPtr->nextPtr = tracePtr->nextPtr;\n    }\n    free (tracePtr);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_VarTraceInfo --\n *\n *\tReturn the clientData value associated with a trace on a\n *\tvariable.  This procedure can also be used to step through\n *\tall of the traces on a particular variable that have the\n *\tsame trace procedure.\n *\n * Results:\n *\tThe return value is the clientData value associated with\n *\ta trace on the given variable.  Information will only be\n *\treturned for a trace with proc as trace procedure.  If\n *\tthe clientData argument is NULL then the first such trace is\n *\treturned;  otherwise, the next relevant one after the one\n *\tgiven by clientData will be returned.  If the variable\n *\tdoesn't exist, or if there are no (more) traces for it,\n *\tthen NULL is returned.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nvoid *\nTcl_VarTraceInfo(interp, varName, flags, proc, prevClientData)\n    Tcl_Interp *interp;\t\t/* Interpreter containing variable. */\n    unsigned char *varName;\t/* Name of variable;  may end with \"(index)\"\n\t\t\t\t * to signify an array reference. */\n    int flags;\t\t\t/* 0 or TCL_GLOBAL_ONLY. */\n    Tcl_VarTraceProc *proc;\t/* Procedure assocated with trace. */\n    void *prevClientData;\t/* If non-NULL, gives last value returned\n\t\t\t\t * by this procedure, so this call will\n\t\t\t\t * return the next trace after that one.\n\t\t\t\t * If NULL, this call will return the\n\t\t\t\t * first trace. */\n{\n    register unsigned char *p;\n\n    /*\n     * If varName refers to an array (it ends with a parenthesized\n     * element name), then handle it specially.\n     */\n\n    for (p = varName; *p != '\\0'; p++) {\n\tif (*p == '(') {\n\t    void *result;\n\t    unsigned char *open = p;\n\n\t    do {\n\t\tp++;\n\t    } while (*p != '\\0');\n\t    p--;\n\t    if (*p != ')') {\n\t\tgoto scalar;\n\t    }\n\t    *open = '\\0';\n\t    *p = '\\0';\n\t    result = Tcl_VarTraceInfo2(interp, varName, open+1, flags, proc,\n\t\tprevClientData);\n\t    *open = '(';\n\t    *p = ')';\n\t    return result;\n\t}\n    }\n\n    scalar:\n    return Tcl_VarTraceInfo2(interp, varName, 0, flags, proc, prevClientData);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_VarTraceInfo2 --\n *\n *\tSame as Tcl_VarTraceInfo, except takes name in two pieces\n *\tinstead of one.\n *\n * Results:\n *\tSame as Tcl_VarTraceInfo.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nvoid *\nTcl_VarTraceInfo2(interp, part1, part2, flags, proc, prevClientData)\n    Tcl_Interp *interp;\t\t/* Interpreter containing variable. */\n    unsigned char *part1;\t/* Name of variable or array. */\n    unsigned char *part2;\t/* Name of element within array;  NULL means\n\t\t\t\t * trace applies to scalar variable or array\n\t\t\t\t * as-a-whole. */\n    int flags;\t\t\t/* 0 or TCL_GLOBAL_ONLY. */\n    Tcl_VarTraceProc *proc;\t/* Procedure assocated with trace. */\n    void *prevClientData;\t/* If non-NULL, gives last value returned\n\t\t\t\t * by this procedure, so this call will\n\t\t\t\t * return the next trace after that one.\n\t\t\t\t * If NULL, this call will return the\n\t\t\t\t * first trace. */\n{\n    register VarTrace *tracePtr;\n    Var *varPtr;\n    Interp *iPtr = (Interp *) interp;\n    Tcl_HashEntry *hPtr;\n\n    /*\n     * First, lookup the variable.\n     */\n    if ((flags & TCL_GLOBAL_ONLY) || (iPtr->varFramePtr == 0)) {\n\thPtr = Tcl_FindHashEntry(&iPtr->globalTable, part1);\n    } else {\n\thPtr = Tcl_FindHashEntry(&iPtr->varFramePtr->varTable, part1);\n    }\n    if (hPtr == 0) {\n\treturn 0;\n    }\n    varPtr = (Var *) Tcl_GetHashValue(hPtr);\n    if (varPtr->flags & VAR_UPVAR) {\n\thPtr = varPtr->value.upvarPtr;\n\tvarPtr = (Var *) Tcl_GetHashValue(hPtr);\n    }\n    if (part2 != 0) {\n\tif (!(varPtr->flags & VAR_ARRAY)) {\n\t    return 0;\n\t}\n\thPtr = Tcl_FindHashEntry(varPtr->value.tablePtr, part2);\n\tif (hPtr == 0) {\n\t    return 0;\n\t}\n\tvarPtr = (Var *) Tcl_GetHashValue(hPtr);\n    }\n\n    /*\n     * Find the relevant trace, if any, and return its clientData.\n     */\n\n    tracePtr = varPtr->tracePtr;\n    if (prevClientData != 0) {\n\tfor ( ; tracePtr != 0; tracePtr = tracePtr->nextPtr) {\n\t    if ((tracePtr->clientData == prevClientData)\n\t\t    && (tracePtr->traceProc == proc)) {\n\t\ttracePtr = tracePtr->nextPtr;\n\t\tbreak;\n\t    }\n\t}\n    }\n    for ( ; tracePtr != 0; tracePtr = tracePtr->nextPtr) {\n\tif (tracePtr->traceProc == proc) {\n\t    return tracePtr->clientData;\n\t}\n    }\n    return 0;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_SetCmd --\n *\n *\tThis procedure is invoked to process the \"set\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result value.\n *\n * Side effects:\n *\tA variable's value may be changed.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_SetCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    register Tcl_Interp *interp;\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    if (argc == 2) {\n\tunsigned char *value;\n\n\tvalue = Tcl_GetVar(interp, argv[1], TCL_LEAVE_ERR_MSG);\n\tif (value == 0) {\n\t    return TCL_ERROR;\n\t}\n\tinterp->result = value;\n\treturn TCL_OK;\n    } else if (argc == 3) {\n\tunsigned char *result;\n\n\tresult = Tcl_SetVar(interp, argv[1], argv[2], TCL_LEAVE_ERR_MSG);\n\tif (result == 0) {\n\t    return TCL_ERROR;\n\t}\n\tinterp->result = result;\n\treturn TCL_OK;\n    } else {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\targv[0], \" varName ?newValue?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_UnsetCmd --\n *\n *\tThis procedure is invoked to process the \"unset\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result value.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_UnsetCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    register Tcl_Interp *interp;\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int i;\n\n    if (argc < 2) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\targv[0], \" varName ?varName ...?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    for (i = 1; i < argc; i++) {\n\tif (Tcl_UnsetVar(interp, argv[i], TCL_LEAVE_ERR_MSG) != 0) {\n\t    return TCL_ERROR;\n\t}\n    }\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_AppendCmd --\n *\n *\tThis procedure is invoked to process the \"append\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result value.\n *\n * Side effects:\n *\tA variable's value may be changed.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_AppendCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    register Tcl_Interp *interp;\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int i;\n    unsigned char *result = 0;\t\t/* (Initialization only needed to keep\n\t\t\t\t\t * the compiler from complaining) */\n\n    if (argc < 3) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\targv[0], \" varName value ?value ...?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n\n    for (i = 2; i < argc; i++) {\n\tresult = Tcl_SetVar(interp, argv[1], argv[i],\n\t\tTCL_APPEND_VALUE|TCL_LEAVE_ERR_MSG);\n\tif (result == 0) {\n\t    return TCL_ERROR;\n\t}\n    }\n    interp->result = result;\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_LappendCmd --\n *\n *\tThis procedure is invoked to process the \"lappend\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result value.\n *\n * Side effects:\n *\tA variable's value may be changed.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_LappendCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    register Tcl_Interp *interp;\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int i;\n    unsigned char *result = 0;\t\t/* (Initialization only needed to keep\n\t\t\t\t\t * the compiler from complaining) */\n\n    if (argc < 3) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\targv[0], \" varName value ?value ...?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n\n    for (i = 2; i < argc; i++) {\n\tresult = Tcl_SetVar(interp, argv[1], argv[i],\n\t\tTCL_APPEND_VALUE|TCL_LIST_ELEMENT|TCL_LEAVE_ERR_MSG);\n\tif (result == 0) {\n\t    return TCL_ERROR;\n\t}\n    }\n    interp->result = result;\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_ArrayCmd --\n *\n *\tThis procedure is invoked to process the \"array\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result value.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_ArrayCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    register Tcl_Interp *interp;\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    int length;\n    char c;\n    Var *varPtr;\n    Tcl_HashEntry *hPtr;\n    Interp *iPtr = (Interp *) interp;\n\n    if (argc < 3) {\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\targv[0], \" option arrayName ?arg ...?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n\n    /*\n     * Locate the array variable (and it better be an array).\n     */\n\n    if (iPtr->varFramePtr == 0) {\n\thPtr = Tcl_FindHashEntry(&iPtr->globalTable, argv[2]);\n    } else {\n\thPtr = Tcl_FindHashEntry(&iPtr->varFramePtr->varTable, argv[2]);\n    }\n    if (hPtr == 0) {\n\tnotArray:\n\tTcl_AppendResult(interp, \"\\\"\", argv[2], \"\\\" isn't an array\", 0);\n\treturn TCL_ERROR;\n    }\n    varPtr = (Var *) Tcl_GetHashValue(hPtr);\n    if (varPtr->flags & VAR_UPVAR) {\n\tvarPtr = (Var *) Tcl_GetHashValue(varPtr->value.upvarPtr);\n    }\n    if (!(varPtr->flags & VAR_ARRAY)) {\n\tgoto notArray;\n    }\n\n    /*\n     * Dispatch based on the option.\n     */\n\n    c = argv[1][0];\n    length = strlen(argv[1]);\n    if ((c == 'a') && (strncmp(argv[1], (unsigned char*) \"anymore\", length) == 0)) {\n\tArraySearch *searchPtr;\n\n\tif (argc != 4) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\t    argv[0], \" anymore arrayName searchId\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tsearchPtr = ParseSearchId(interp, varPtr, argv[2], argv[3]);\n\tif (searchPtr == 0) {\n\t    return TCL_ERROR;\n\t}\n\twhile (1) {\n\t    Var *varPtr2;\n\n\t    if (searchPtr->nextEntry != 0) {\n\t\tvarPtr2 = (Var *) Tcl_GetHashValue(searchPtr->nextEntry);\n\t\tif (!(varPtr2->flags & VAR_UNDEFINED)) {\n\t\t    break;\n\t\t}\n\t    }\n\t    searchPtr->nextEntry = Tcl_NextHashEntry(&searchPtr->search);\n\t    if (searchPtr->nextEntry == 0) {\n\t\tinterp->result = (unsigned char*) \"0\";\n\t\treturn TCL_OK;\n\t    }\n\t}\n\tinterp->result = (unsigned char*) \"1\";\n\treturn TCL_OK;\n    } else if ((c == 'd') && (strncmp(argv[1], (unsigned char*) \"donesearch\", length) == 0)) {\n\tArraySearch *searchPtr, *prevPtr;\n\n\tif (argc != 4) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\t    argv[0], \" donesearch arrayName searchId\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tsearchPtr = ParseSearchId(interp, varPtr, argv[2], argv[3]);\n\tif (searchPtr == 0) {\n\t    return TCL_ERROR;\n\t}\n\tif (varPtr->searchPtr == searchPtr) {\n\t    varPtr->searchPtr = searchPtr->nextPtr;\n\t} else {\n\t    for (prevPtr = varPtr->searchPtr; ; prevPtr = prevPtr->nextPtr) {\n\t\tif (prevPtr->nextPtr == searchPtr) {\n\t\t    prevPtr->nextPtr = searchPtr->nextPtr;\n\t\t    break;\n\t\t}\n\t    }\n\t}\n\tfree (searchPtr);\n    } else if ((c == 'n') && (strncmp(argv[1], (unsigned char*) \"names\", length) == 0)\n\t    && (length >= 2)) {\n\tTcl_HashSearch search;\n\tVar *varPtr2;\n\n\tif (argc != 3) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\t    argv[0], \" names arrayName\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tfor (hPtr = Tcl_FirstHashEntry(varPtr->value.tablePtr, &search);\n\t\thPtr != 0; hPtr = Tcl_NextHashEntry(&search)) {\n\t    varPtr2 = (Var *) Tcl_GetHashValue(hPtr);\n\t    if (varPtr2->flags & VAR_UNDEFINED) {\n\t\tcontinue;\n\t    }\n\t    Tcl_AppendElement(interp,\n\t\t    Tcl_GetHashKey(varPtr->value.tablePtr, hPtr), 0);\n\t}\n    } else if ((c == 'n') && (strncmp(argv[1], (unsigned char*) \"nextelement\", length) == 0)\n\t    && (length >= 2)) {\n\tArraySearch *searchPtr;\n\tTcl_HashEntry *hPtr;\n\n\tif (argc != 4) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\t    argv[0], \" nextelement arrayName searchId\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tsearchPtr = ParseSearchId(interp, varPtr, argv[2], argv[3]);\n\tif (searchPtr == 0) {\n\t    return TCL_ERROR;\n\t}\n\twhile (1) {\n\t    Var *varPtr2;\n\n\t    hPtr = searchPtr->nextEntry;\n\t    if (hPtr == 0) {\n\t\thPtr = Tcl_NextHashEntry(&searchPtr->search);\n\t\tif (hPtr == 0) {\n\t\t    return TCL_OK;\n\t\t}\n\t    } else {\n\t\tsearchPtr->nextEntry = 0;\n\t    }\n\t    varPtr2 = (Var *) Tcl_GetHashValue(hPtr);\n\t    if (!(varPtr2->flags & VAR_UNDEFINED)) {\n\t\tbreak;\n\t    }\n\t}\n\tinterp->result = Tcl_GetHashKey(varPtr->value.tablePtr, hPtr);\n    } else if ((c == 's') && (strncmp(argv[1], (unsigned char*) \"size\", length) == 0)\n\t    && (length >= 2)) {\n\tTcl_HashSearch search;\n\tVar *varPtr2;\n\tint size;\n\n\tif (argc != 3) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\t    argv[0], \" size arrayName\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tsize = 0;\n\tfor (hPtr = Tcl_FirstHashEntry(varPtr->value.tablePtr, &search);\n\t\thPtr != 0; hPtr = Tcl_NextHashEntry(&search)) {\n\t    varPtr2 = (Var *) Tcl_GetHashValue(hPtr);\n\t    if (varPtr2->flags & VAR_UNDEFINED) {\n\t\tcontinue;\n\t    }\n\t    size++;\n\t}\n\tsprintf(interp->result, \"%d\", size);\n    } else if ((c == 's') && (strncmp(argv[1], (unsigned char*) \"startsearch\", length) == 0)\n\t    && (length >= 2)) {\n\tArraySearch *searchPtr;\n\n\tif (argc != 3) {\n\t    Tcl_AppendResult(interp, \"wrong # args: should be \\\"\",\n\t\t    argv[0], \" startsearch arrayName\\\"\", 0);\n\t    return TCL_ERROR;\n\t}\n\tsearchPtr = (ArraySearch*) malloc (sizeof(ArraySearch));\n\tif (varPtr->searchPtr == 0) {\n\t    searchPtr->id = 1;\n\t    Tcl_AppendResult(interp, \"s-1-\", argv[2], 0);\n\t} else {\n\t    unsigned char string[20];\n\n\t    searchPtr->id = varPtr->searchPtr->id + 1;\n\t    sprintf(string, \"%u\", searchPtr->id);\n\t    Tcl_AppendResult(interp, \"s-\", string, \"-\", argv[2], 0);\n\t}\n\tsearchPtr->varPtr = varPtr;\n\tsearchPtr->nextEntry = Tcl_FirstHashEntry(varPtr->value.tablePtr,\n\t\t&searchPtr->search);\n\tsearchPtr->nextPtr = varPtr->searchPtr;\n\tvarPtr->searchPtr = searchPtr;\n    } else {\n\tTcl_AppendResult(interp, \"bad option \\\"\", argv[1],\n\t\t\"\\\": should be anymore, donesearch, names, nextelement, \",\n\t\t\"size, or startsearch\", 0);\n\treturn TCL_ERROR;\n    }\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_GlobalCmd --\n *\n *\tThis procedure is invoked to process the \"global\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result value.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_GlobalCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    Var *varPtr, *gVarPtr;\n    register Interp *iPtr = (Interp *) interp;\n    Tcl_HashEntry *hPtr, *hPtr2;\n    int new;\n\n    if (argc < 2) {\n\tTcl_AppendResult((Tcl_Interp *) iPtr, \"wrong # args: should be \\\"\",\n\t\targv[0], \" varName ?varName ...?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n    if (iPtr->varFramePtr == 0) {\n\treturn TCL_OK;\n    }\n\n    for (argc--, argv++; argc > 0; argc--, argv++) {\n\thPtr = Tcl_CreateHashEntry(&iPtr->globalTable, *argv, &new);\n\tif (new) {\n\t    gVarPtr = NewVar (0);\n\t    gVarPtr->flags |= VAR_UNDEFINED;\n\t    Tcl_SetHashValue(hPtr, gVarPtr);\n\t} else {\n\t    gVarPtr = (Var *) Tcl_GetHashValue(hPtr);\n\t}\n\thPtr2 = Tcl_CreateHashEntry(&iPtr->varFramePtr->varTable, *argv, &new);\n\tif (!new) {\n\t    Var *varPtr;\n\t    varPtr = (Var *) Tcl_GetHashValue(hPtr2);\n\t    if (varPtr->flags & VAR_UPVAR) {\n\t\tcontinue;\n\t    } else {\n\t\tTcl_AppendResult((Tcl_Interp *) iPtr, \"variable \\\"\", *argv,\n\t\t    \"\\\" already exists\", 0);\n\t\treturn TCL_ERROR;\n\t    }\n\t}\n\tvarPtr = NewVar (0);\n\tvarPtr->flags |= VAR_UPVAR;\n\tvarPtr->value.upvarPtr = hPtr;\n\tgVarPtr->upvarUses++;\n\tTcl_SetHashValue(hPtr2, varPtr);\n    }\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * Tcl_UpvarCmd --\n *\n *\tThis procedure is invoked to process the \"upvar\" Tcl command.\n *\tSee the user documentation for details on what it does.\n *\n * Results:\n *\tA standard Tcl result value.\n *\n * Side effects:\n *\tSee the user documentation.\n *\n *----------------------------------------------------------------------\n */\n\n\t/* ARGSUSED */\nint\nTcl_UpvarCmd(dummy, interp, argc, argv)\n    void *dummy;\t\t\t/* Not used. */\n    Tcl_Interp *interp;\t\t\t/* Current interpreter. */\n    int argc;\t\t\t\t/* Number of arguments. */\n    unsigned char **argv;\t\t/* Argument strings. */\n{\n    register Interp *iPtr = (Interp *) interp;\n    int result;\n    CallFrame *framePtr;\n    Var *varPtr = 0;\n    Tcl_HashTable *upVarTablePtr;\n    Tcl_HashEntry *hPtr, *hPtr2;\n    int new;\n    Var *upVarPtr;\n\n    if (argc < 3) {\n\tupvarSyntax:\n\tTcl_AppendResult(interp, \"wrong # args: should be \\\"\", argv[0],\n\t\t\" ?level? otherVar localVar ?otherVar localVar ...?\\\"\", 0);\n\treturn TCL_ERROR;\n    }\n\n    /*\n     * Find the hash table containing the variable being referenced.\n     */\n\n    result = TclGetFrame(interp, argv[1], &framePtr);\n    if (result == -1) {\n\treturn TCL_ERROR;\n    }\n    argc -= result+1;\n    argv += result+1;\n    if (framePtr == 0) {\n\tupVarTablePtr = &iPtr->globalTable;\n    } else {\n\tupVarTablePtr = &framePtr->varTable;\n    }\n\n    if ((argc & 1) != 0) {\n\tgoto upvarSyntax;\n    }\n\n    /*\n     * Iterate over all the pairs of (local variable, other variable)\n     * names.  For each pair, create a hash table entry in the upper\n     * context (if the name wasn't there already), then associate it\n     * with a new local variable.\n     */\n\n    while (argc > 0) {\n        hPtr = Tcl_CreateHashEntry(upVarTablePtr, argv[0], &new);\n        if (new) {\n            upVarPtr = NewVar (0);\n            upVarPtr->flags |= VAR_UNDEFINED;\n            Tcl_SetHashValue(hPtr, upVarPtr);\n        } else {\n            upVarPtr = (Var *) Tcl_GetHashValue(hPtr);\n\t    if (upVarPtr->flags & VAR_UPVAR) {\n\t\thPtr = upVarPtr->value.upvarPtr;\n\t\tupVarPtr = (Var *) Tcl_GetHashValue(hPtr);\n\t    }\n        }\n\n        hPtr2 = Tcl_CreateHashEntry(&iPtr->varFramePtr->varTable,\n                    argv[1], &new);\n        if (!new) {\n            Tcl_AppendResult((Tcl_Interp *) iPtr, \"variable \\\"\", argv[1],\n                \"\\\" already exists\", 0);\n            return TCL_ERROR;\n        }\n        varPtr = NewVar (0);\n        varPtr->flags |= VAR_UPVAR;\n        varPtr->value.upvarPtr = hPtr;\n        upVarPtr->upvarUses++;\n        Tcl_SetHashValue(hPtr2, varPtr);\n\n        argc -= 2;\n        argv += 2;\n    }\n    return TCL_OK;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * TclDeleteVars --\n *\n *\tThis procedure is called to recycle all the storage space\n *\tassociated with a table of variables.  For this procedure\n *\tto work correctly, it must not be possible for any of the\n *\tvariable in the table to be accessed from Tcl commands\n *\t(e.g. from trace procedures).\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tVariables are deleted and trace procedures are invoked, if\n *\tany are declared.\n *\n *----------------------------------------------------------------------\n */\n\nvoid\nTclDeleteVars(iPtr, tablePtr)\n    Interp *iPtr;\t\t/* Interpreter to which variables belong. */\n    Tcl_HashTable *tablePtr;\t/* Hash table containing variables to\n\t\t\t\t * delete. */\n{\n    Tcl_HashSearch search;\n    Tcl_HashEntry *hPtr;\n    register Var *varPtr;\n    int flags, globalFlag;\n\n    flags = TCL_TRACE_UNSETS;\n    if (tablePtr == &iPtr->globalTable) {\n\tflags |= TCL_INTERP_DESTROYED | TCL_GLOBAL_ONLY;\n    }\n    for (hPtr = Tcl_FirstHashEntry(tablePtr, &search); hPtr != 0;\n\t    hPtr = Tcl_NextHashEntry(&search)) {\n\tvarPtr = (Var *) Tcl_GetHashValue(hPtr);\n\n\t/*\n\t * For global/upvar variables referenced in procedures, free up the\n\t * local space and then decrement the reference count on the\n\t * variable referred to.  If there are no more references to the\n\t * global/upvar and it is undefined and has no traces set, then\n\t * follow on and delete the referenced variable too.\n\t */\n\n\tglobalFlag = 0;\n\tif (varPtr->flags & VAR_UPVAR) {\n\t    hPtr = varPtr->value.upvarPtr;\n\t    free (varPtr);\n\t    varPtr = (Var *) Tcl_GetHashValue(hPtr);\n\t    varPtr->upvarUses--;\n\t    if ((varPtr->upvarUses != 0) || !(varPtr->flags & VAR_UNDEFINED)\n\t\t    || (varPtr->tracePtr != 0)) {\n\t\tcontinue;\n\t    }\n\t    globalFlag = TCL_GLOBAL_ONLY;\n\t}\n\n\t/*\n\t * Invoke traces on the variable that is being deleted, then\n\t * free up the variable's space (no need to free the hash entry\n\t * here, unless we're dealing with a global variable:  the\n\t * hash entries will be deleted automatically when the whole\n\t * table is deleted).\n\t */\n\n\tif (varPtr->tracePtr != 0) {\n\t    (void) CallTraces(iPtr, (Var *) 0, hPtr,\n\t\t    Tcl_GetHashKey(tablePtr, hPtr), 0,\n\t\t    flags | globalFlag);\n\t    while (varPtr->tracePtr != 0) {\n\t\tVarTrace *tracePtr = varPtr->tracePtr;\n\t\tvarPtr->tracePtr = tracePtr->nextPtr;\n\t\tfree (tracePtr);\n\t    }\n\t}\n\tif (varPtr->flags & VAR_ARRAY) {\n\t    DeleteArray(iPtr, Tcl_GetHashKey(tablePtr, hPtr), varPtr,\n\t\t    flags | globalFlag);\n\t}\n\tif (globalFlag) {\n\t    Tcl_DeleteHashEntry(hPtr);\n\t}\n\tfree (varPtr);\n    }\n    Tcl_DeleteHashTable(tablePtr);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * CallTraces --\n *\n *\tThis procedure is invoked to find and invoke relevant\n *\ttrace procedures associated with a particular operation on\n *\ta variable.  This procedure invokes traces both on the\n *\tvariable and on its containing array (where relevant).\n *\n * Results:\n *\tThe return value is 0 if no trace procedures were invoked, or\n *\tif all the invoked trace procedures returned successfully.\n *\tThe return value is non-zero if a trace procedure returned an\n *\terror (in this case no more trace procedures were invoked after\n *\tthe error was returned).  In this case the return value is a\n *\tpointer to a static string describing the error.\n *\n * Side effects:\n *\tAlmost anything can happen, depending on trace;  this procedure\n *\titself doesn't have any side effects.\n *\n *----------------------------------------------------------------------\n */\n\nstatic unsigned char *\nCallTraces (iPtr, arrayPtr, hPtr, part1, part2, flags)\n    Interp *iPtr;\t\t\t/* Interpreter containing variable. */\n    register Var *arrayPtr;\t\t/* Pointer to array variable that\n\t\t\t\t\t * contains the variable, or 0 if\n\t\t\t\t\t * the variable isn't an element of an\n\t\t\t\t\t * array. */\n    Tcl_HashEntry *hPtr;\t\t/* Hash table entry corresponding to\n\t\t\t\t\t * variable whose traces are to be\n\t\t\t\t\t * invoked. */\n    unsigned char *part1, *part2;\t/* Variable's two-part name. */\n    int flags;\t\t\t\t/* Flags to pass to trace procedures:\n\t\t\t\t\t * indicates what's happening to\n\t\t\t\t\t * variable, plus other stuff like\n\t\t\t\t\t * TCL_GLOBAL_ONLY and\n\t\t\t\t\t * TCL_INTERP_DESTROYED. */\n{\n    Var *varPtr;\n    register VarTrace *tracePtr;\n    ActiveVarTrace active;\n    unsigned char *result;\n    int savedArrayFlags = 0;\t\t/* (Initialization not needed except\n\t\t\t\t\t * to prevent compiler warning) */\n\n    /*\n     * If there are already similar trace procedures active for the\n     * variable, don't call them again.\n     */\n\n    varPtr = (Var *) Tcl_GetHashValue(hPtr);\n    if (varPtr->flags & VAR_TRACE_ACTIVE) {\n\treturn 0;\n    }\n    varPtr->flags |= VAR_TRACE_ACTIVE;\n\n    /*\n     * Invoke traces on the array containing the variable, if relevant.\n     */\n\n    result = 0;\n    active.nextPtr = iPtr->activeTracePtr;\n    iPtr->activeTracePtr = &active;\n    if (arrayPtr != 0) {\n\tsavedArrayFlags = arrayPtr->flags;\n\tarrayPtr->flags |= VAR_ELEMENT_ACTIVE;\n\tfor (tracePtr = arrayPtr->tracePtr;  tracePtr != 0;\n\t\ttracePtr = active.nextTracePtr) {\n\t    active.nextTracePtr = tracePtr->nextPtr;\n\t    if (!(tracePtr->flags & flags)) {\n\t\tcontinue;\n\t    }\n\t    result = (*tracePtr->traceProc)(tracePtr->clientData,\n\t\t    (Tcl_Interp *) iPtr, part1, part2, flags);\n\t    if (result != 0) {\n\t\tif (flags & TCL_TRACE_UNSETS) {\n\t\t    result = 0;\n\t\t} else {\n\t\t    goto done;\n\t\t}\n\t    }\n\t}\n    }\n\n    /*\n     * Invoke traces on the variable itself.\n     */\n\n    if (flags & TCL_TRACE_UNSETS) {\n\tflags |= TCL_TRACE_DESTROYED;\n    }\n    for (tracePtr = varPtr->tracePtr; tracePtr != 0;\n\t    tracePtr = active.nextTracePtr) {\n\tactive.nextTracePtr = tracePtr->nextPtr;\n\tif (!(tracePtr->flags & flags)) {\n\t    continue;\n\t}\n\tresult = (*tracePtr->traceProc)(tracePtr->clientData,\n\t\t(Tcl_Interp *) iPtr, part1, part2, flags);\n\tif (result != 0) {\n\t    if (flags & TCL_TRACE_UNSETS) {\n\t\tresult = 0;\n\t    } else {\n\t\tgoto done;\n\t    }\n\t}\n    }\n\n    /*\n     * Restore the variable's flags, remove the record of our active\n     * traces, and then return.  Remember that the variable could have\n     * been re-allocated during the traces, but its hash entry won't\n     * change.\n     */\n\n    done:\n    if (arrayPtr != 0) {\n\tarrayPtr->flags = savedArrayFlags;\n    }\n    varPtr = (Var *) Tcl_GetHashValue(hPtr);\n    varPtr->flags &= ~VAR_TRACE_ACTIVE;\n    iPtr->activeTracePtr = active.nextPtr;\n    return result;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * NewVar --\n *\n *\tCreate a new variable with a given initial value.\n *\n * Results:\n *\tThe return value is a pointer to the new variable structure.\n *\tThe variable will not be part of any hash table yet, and its\n *\tupvarUses count is initialized to 0.  Its initial value will\n *\tbe empty, but \"space\" bytes will be available in the value\n *\tarea.\n *\n * Side effects:\n *\tStorage gets allocated.\n *\n *----------------------------------------------------------------------\n */\n\nstatic Var *\nNewVar (int space)\t\t/* Minimum amount of space to allocate\n\t\t\t\t * for variable's value. */\n{\n    int extra;\n    register Var *varPtr;\n\n    extra = space - sizeof(varPtr->value);\n    if (extra < 0) {\n\textra = 0;\n\tspace = sizeof(varPtr->value);\n    }\n    varPtr = (Var*) malloc ((unsigned) (sizeof(Var) + extra));\n    varPtr->valueLength = 0;\n    varPtr->valueSpace = space;\n    varPtr->upvarUses = 0;\n    varPtr->tracePtr = 0;\n    varPtr->searchPtr = 0;\n    varPtr->flags = 0;\n    varPtr->value.string[0] = 0;\n    return varPtr;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * ParseSearchId --\n *\n *\tThis procedure translates from a string to a pointer to an\n *\tactive array search (if there is one that matches the string).\n *\n * Results:\n *\tThe return value is a pointer to the array search indicated\n *\tby string, or 0 if there isn't one.  If 0 is returned,\n *\tinterp->result contains an error message.\n *\n * Side effects:\n *\tNone.\n *\n *----------------------------------------------------------------------\n */\n\nstatic ArraySearch *\nParseSearchId(interp, varPtr, varName, string)\n    Tcl_Interp *interp;\t\t/* Interpreter containing variable. */\n    Var *varPtr;\t\t/* Array variable search is for. */\n    unsigned char *varName;\t/* Name of array variable that search is\n\t\t\t\t * supposed to be for. */\n    char *string;\t\t/* String containing id of search.  Must have\n\t\t\t\t * form \"search-num-var\" where \"num\" is a\n\t\t\t\t * decimal number and \"var\" is a variable\n\t\t\t\t * name. */\n{\n    char *end;\n    int id;\n    ArraySearch *searchPtr;\n\n    /*\n     * Parse the id into the three parts separated by dashes.\n     */\n\n    if ((string[0] != 's') || (string[1] != '-')) {\n\tsyntax:\n\tTcl_AppendResult(interp, \"illegal search identifier \\\"\", string,\n\t\t\"\\\"\", 0);\n\treturn 0;\n    }\n    id = strtoul(string+2, &end, 10);\n    if ((end == (string+2)) || (*end != '-')) {\n\tgoto syntax;\n    }\n    if (strcmp(end+1, varName) != 0) {\n\tTcl_AppendResult(interp, \"search identifier \\\"\", string,\n\t\t\"\\\" isn't for variable \\\"\", varName, \"\\\"\", 0);\n\treturn 0;\n    }\n\n    /*\n     * Search through the list of active searches on the interpreter\n     * to see if the desired one exists.\n     */\n\n    for (searchPtr = varPtr->searchPtr; searchPtr != 0;\n\t    searchPtr = searchPtr->nextPtr) {\n\tif (searchPtr->id == id) {\n\t    return searchPtr;\n\t}\n    }\n    Tcl_AppendResult(interp, \"couldn't find search \\\"\", string, \"\\\"\", 0);\n    return 0;\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * DeleteSearches --\n *\n *\tThis procedure is called to free up all of the searches\n *\tassociated with an array variable.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tMemory is released to the storage allocator.\n *\n *----------------------------------------------------------------------\n */\n\nstatic void\nDeleteSearches(arrayVarPtr)\n    register Var *arrayVarPtr;\t\t/* Variable whose searches are\n\t\t\t\t\t * to be deleted. */\n{\n    ArraySearch *searchPtr;\n\n    while (arrayVarPtr->searchPtr != 0) {\n\tsearchPtr = arrayVarPtr->searchPtr;\n\tarrayVarPtr->searchPtr = searchPtr->nextPtr;\n\tfree (searchPtr);\n    }\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * DeleteArray --\n *\n *\tThis procedure is called to free up everything in an array\n *\tvariable.  It's the caller's responsibility to make sure\n *\tthat the array is no longer accessible before this procedure\n *\tis called.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tAll storage associated with varPtr's array elements is deleted\n *\t(including the hash table).  Any delete trace procedures for\n *\tarray elements are invoked.\n *\n *----------------------------------------------------------------------\n */\nstatic void\nDeleteArray(iPtr, arrayName, varPtr, flags)\n    Interp *iPtr;\t\t\t/* Interpreter containing array. */\n    unsigned char *arrayName;\t\t/* Name of array (used for trace\n\t\t\t\t\t * callbacks). */\n    Var *varPtr;\t\t\t/* Pointer to variable structure. */\n    int flags;\t\t\t\t/* Flags to pass to CallTraces:\n\t\t\t\t\t * TCL_TRACE_UNSETS and sometimes\n\t\t\t\t\t * TCL_INTERP_DESTROYED and/or\n\t\t\t\t\t * TCL_GLOBAL_ONLY. */\n{\n    Tcl_HashSearch search;\n    register Tcl_HashEntry *hPtr;\n    register Var *elPtr;\n\n    DeleteSearches(varPtr);\n    for (hPtr = Tcl_FirstHashEntry(varPtr->value.tablePtr, &search);\n\t    hPtr != 0; hPtr = Tcl_NextHashEntry(&search)) {\n\telPtr = (Var *) Tcl_GetHashValue(hPtr);\n\tif (elPtr->tracePtr != 0) {\n\t    (void) CallTraces(iPtr, (Var *) 0, hPtr, arrayName,\n\t\t    Tcl_GetHashKey(varPtr->value.tablePtr, hPtr), flags);\n\t    while (elPtr->tracePtr != 0) {\n\t\tVarTrace *tracePtr = elPtr->tracePtr;\n\t\telPtr->tracePtr = tracePtr->nextPtr;\n\t\tfree (tracePtr);\n\t    }\n\t}\n\tassert ((elPtr->flags & VAR_SEARCHES_POSSIBLE) == 0);\n\n\tfree (elPtr);\n    }\n    Tcl_DeleteHashTable(varPtr->value.tablePtr);\n    free (varPtr->value.tablePtr);\n}\n\f\n/*\n *----------------------------------------------------------------------\n *\n * VarErrMsg --\n *\n *\tGenerate a reasonable error message describing why a variable\n *\toperation failed.\n *\n * Results:\n *\tNone.\n *\n * Side effects:\n *\tInterp->result is reset to hold a message identifying the\n *\tvariable given by part1 and part2 and describing why the\n *\tvariable operation failed.\n *\n *----------------------------------------------------------------------\n */\n\nstatic void\nVarErrMsg(interp, part1, part2, operation, reason)\n    Tcl_Interp *interp;\t\t/* Interpreter in which to record message. */\n    unsigned char *part1, *part2; /* Variable's two-part name. */\n    unsigned char *operation;\t/* String describing operation that failed,\n\t\t\t\t * e.g. \"read\", \"set\", or \"unset\". */\n    unsigned char *reason;\t/* String describing why operation failed. */\n{\n    Tcl_ResetResult(interp);\n    Tcl_AppendResult(interp, \"can't \", operation, \" \\\"\", part1, 0);\n    if (part2 != 0) {\n\tTcl_AppendResult(interp, \"(\", part2, \")\", 0);\n    }\n    Tcl_AppendResult(interp, \"\\\": \", reason, 0);\n}\n"
  },
  {
    "path": "lib/libtermlib/Makefile",
    "content": "#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\nTOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nDEFS    = -DNOSCCS\nCFLAGS += -O -DCM_N -DCM_GT -DCM_B -DCM_D ${DEFS} -Wall\nLD      = $(CC)\nSRCS    = termcap.c tgoto.c tputs.c tcattr.c\nOBJS    = termcap.o tgoto.o tputs.o tcattr.o\nPOBJS   = ../termcap.o ../tgoto.o ../tputs.o ../tcattr.o\nTAGSFILE= tags\n\n#.c.o:\n#\t$(CC) $(CFLAGS) -c -p $*.c\n#\t$(LD) $(LDFLAGS) -x -r -o profiled/$*.o $*.o\n#\t$(CC) $(CFLAGS) -c $*.c\n#\t$(LD) $(LDFLAGS) -X -r $*.o\n#\tmv a.out $*.o\n\nall:    ../libtermcap.a termcap\n\n.PHONY: termcap\n\ntermcap:\n\tcd termcap && ${MAKE}\n\n../libtermcap.a: ${OBJS}\n\t$(AR) cr ../libtermcap.a ${OBJS}\n\n../libtermcap_p.a: ${OBJS}\n\tcd profiled; $(AR) cr ../../libtermcap_p.a ${POBJS}\n\ninstall: all\n#\tcp ../libtermcap.a ${DESTDIR}/usr/lib/libtermcap.a\n#\t@-rm -f ${DESTDIR}/usr/lib/libtermlib.a\n#\tln ${DESTDIR}/usr/lib/libtermcap.a ${DESTDIR}/usr/lib/libtermlib.a\n#\t$(RANLIB) ${DESTDIR}/usr/lib/libtermcap.a\n\t$(MAKE) -C termcap install\n#\tcp ../libtermcap_p.a ${DESTDIR}/usr/lib/libtermcap_p.a\n#\t@-rm -f ${DESTDIR}/usr/lib/libtermlib_p.a\n#\tln ${DESTDIR}/usr/lib/libtermcap_p.a ${DESTDIR}/usr/lib/libtermlib_p.a\n#\t$(RANLIB) ${DESTDIR}/usr/lib/libtermcap_p.a\n\ntags:\n\tcwd=`pwd`; \\\n\tfor i in ${SRCS}; do \\\n\t\tctags -a -f ${TAGSFILE} $$cwd/$$i; \\\n\tdone\n\nclean:\n\t-rm -f *.o profiled/*.o\n\t-rm -f ../libtermcap.a ../libtermcap_p.a\n\t-rm -f termcap/termcap termcap/termcap.full\n\nVGRIND=\tcsh /usr/ucb/vgrind\nvgrind:\n\tcp /dev/null index\n\t${VGRIND} -h \"Termcap library\" termcap.c tputs.c tgoto.c\n\t${VGRIND} -h \"Termcap library\" -x index\n"
  },
  {
    "path": "lib/libtermlib/tc1.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * tc1 [term]\n * dummy program to test termlib.\n * gets entry, counts it, and prints it.\n */\n#include <stdio.h>\nchar buf[1024];\nchar *getenv();\n\nmain(argc, argv) char **argv; {\n\tchar *p;\n\tint rc;\n\n\tif (argc < 2)\n\t\tp = getenv(\"TERM\");\n\telse\n\t\tp = argv[1];\n\trc = tgetent(buf,p);\n\tprintf(\"tgetent returns %d, len=%d, text=\\n'%s'\\n\",rc,strlen(buf),buf);\n}\n"
  },
  {
    "path": "lib/libtermlib/tc2.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * tc2 [term]\n * Dummy program to test out termlib.\n * Commands are \"tcc\\n\" where t is type (s for string, f for flag,\n * or n for number) and cc is the name of the capability.\n */\n#include <stdio.h>\nchar buf[1024];\nchar *getenv(), *tgetstr();\n\nmain(argc, argv) char **argv; {\n\tchar *p, *q;\n\tint rc;\n\tchar b[3], c;\n\tchar area[200];\n\n\tif (argc < 2)\n\t\tp = getenv(\"TERM\");\n\telse\n\t\tp = argv[1];\n\trc = tgetent(buf,p);\n\tfor (;;) {\n\t\tc = getchar();\n\t\tif (c < 0)\n\t\t\texit(0);\n\t\tb[0] = getchar();\n\t\tif (b[0] < ' ')\n\t\t\texit(0);\n\t\tb[1] = getchar();\n\t\tb[2] = 0;\n\t\tgetchar();\n\t\tswitch(c) {\n\t\t\tcase 'f':\n\t\t\t\tprintf(\"%s: %d\\n\",b,tgetflag(b));\n\t\t\t\tbreak;\n\t\t\tcase 'n':\n\t\t\t\tprintf(\"%s: %d\\n\",b,tgetnum(b));\n\t\t\t\tbreak;\n\t\t\tcase 's':\n\t\t\t\tq = area;\n\t\t\t\tprintf(\"%s: %s\\n\",b,tgetstr(b,&q));\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\texit(0);\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "lib/libtermlib/tc3.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * tc3 [term]\n * Dummy program to test out termlib.\n * Input two numbers and it prints out the tgoto string generated.\n */\n#include <stdio.h>\nchar buf[1024];\nchar *getenv(), *tgetstr();\nchar *rdchar();\nchar *tgoto();\nchar *CM;\nchar cmbuff[30];\nchar *x;\nchar *UP;\nchar *tgout;\n\nmain(argc, argv) char **argv; {\n\tchar *p;\n\tint rc;\n\tint row, col;\n\n\tif (argc < 2)\n\t\tp = getenv(\"TERM\");\n\telse\n\t\tp = argv[1];\n\trc = tgetent(buf,p);\n\tx = cmbuff;\n\tUP = tgetstr(\"up\", &x);\n\tprintf(\"UP = %x = \", UP); pr(UP); printf(\"\\n\");\n\tif (UP && *UP==0)\n\t\tUP = 0;\n\tCM = tgetstr(\"cm\", &x);\n\tprintf(\"CM = \"); pr(CM); printf(\"\\n\");\n\tfor (;;) {\n\t\tif (scanf(\"%d %d\", &row, &col) < 2)\n\t\t\texit(0);\n\t\ttgout = tgoto(CM, row, col);\n\t\tpr(tgout);\n\t\tprintf(\"\\n\");\n\t}\n}\n\npr(p)\nregister char *p;\n{\n\tfor (; *p; p++)\n\t\tprintf(\"%s\", rdchar(*p));\n}\n\n/*\n * rdchar: returns a readable representation of an ASCII char, using ^ notation.\n */\n#include <ctype.h>\nchar *rdchar(c)\nchar c;\n{\n\tstatic char ret[4];\n\tregister char *p;\n\n\t/*\n\t * Due to a bug in isprint, this prints spaces as ^`, but this is OK\n\t * because we want something to show up on the screen.\n\t */\n\tret[0] = ((c&0377) > 0177) ? '\\'' : ' ';\n\tc &= 0177;\n\tret[1] = isprint(c) ? ' ' : '^';\n\tret[2] = isprint(c) ?  c  : c^0100;\n\tret[3] = 0;\n\tfor (p=ret; *p==' '; p++)\n\t\t;\n\treturn (p);\n}\n"
  },
  {
    "path": "lib/libtermlib/tcattr.c",
    "content": "//\n// TODO: termios support\n//\n#if 0\n#include <errno.h>\n#include <termios.h>\n\nint tcgetattr(int fd, struct termios *t)\n{\n\n        return (ioctl(fd, TIOCGETA, t));\n}\n\nint tcsetattr(int fd, int opt, struct termios *t)\n{\n        struct termios localterm;\n\n        if (opt & TCSASOFT) {\n                localterm = *t;\n                localterm.c_cflag |= CIGNORE;\n                t = &localterm;\n        }\n        switch (opt & ~TCSASOFT) {\n        case TCSANOW:\n                return (ioctl(fd, TIOCSETA, t));\n        case TCSADRAIN:\n                return (ioctl(fd, TIOCSETAW, t));\n        case TCSAFLUSH:\n                return (ioctl(fd, TIOCSETAF, t));\n        default:\n                errno = EINVAL;\n                return (-1);\n        }\n}\n#endif\n"
  },
  {
    "path": "lib/libtermlib/termcap/.gitignore",
    "content": "termcap.full\n"
  },
  {
    "path": "lib/libtermlib/termcap/Makefile",
    "content": "#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n#\t@(#)Makefile\t5.2.4 (2.11BSD GTE) 1997/9/22\n#\n# reorder gives an editor command for most common terminals\n# (in reverse order from n'th to 1'st most commonly used)\n# to move them to the front of termcap\n#\nTOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\ntermcap.full: reorder termcap.src\n\tex - termcap.src < reorder\n\ninstall: termcap.small termcap.full\n\trm -f ${DESTDIR}/usr/share/misc/termcap\n\t${INSTALL} -c -m 444 termcap.small ${DESTDIR}/usr/share/misc/termcap\n#\t${INSTALL} -c -m 444 termcap.full ${DESTDIR}/etc/termcap.full\n\ntabset: FRC\n\trm -fr ${DESTDIR}/usr/share/tabset\n\tmkdir ${DESTDIR}/usr/share/tabset\n\tchmod 755 ${DESTDIR}/usr/share/tabset\n\t${INSTALL} -c -m 444 tabset/* ${DESTDIR}/usr/share/tabset\n\nclean:\n\trm -f termcap.full\n\nFRC:\n"
  },
  {
    "path": "lib/libtermlib/termcap/README",
    "content": "To install this directory on your system:\n\nFirst determine a list of \"common terminals\" for your system.\nThis list will probably be small, and can be empty if you like,\nbut you should probably put your own terminal in it.\n\nSecond, edit the editor script \"reorder\" to use this list instead\nof the list built in to it.  The changes will be evident from looking\nat the script.  Notice that the script contains the terminals in order\nfrom least common to most common, since the move commands will move them\nto the front in that order, the effect will be to put the most common\nat the front of termcap since that's moved last.  The s.* terminals\nare specials, and although they don't have to go to the front, they are\nprobably quite common and really should go near the front.\n\nThird, if you are not a super user and cannot create the directory\n/usr/share/tabset, make a corresponding directory somewhere you can and\nadd a line to reorder to globally change all /usr/share/tabset's to your\nown path name.  This change is better than just changing the termcap.src\nfile because it makes it easier to diff it from newer distributed versions.\nTry to keep the source as is whenever possible, and put mungings into reorder.\n\nNow you can run \"make install\" which will create an /etc/termcap. Again,\nif you aren't a super user change the cp command to put it where you can.\nIn this case you will have to redefine E_TERMCAP in \"local/uparm.h\", which\nwill probably be in subdirectories with the other UCB software.\n\n\nFinally, if you make additions or fixes to termcap, please mail a note\nexplaining what you did with the fixed termcap entry (not the whole file,\nplease!) to me at one of the addresses below, so it can be incorporated\nback into the original source.  I will normally include anything unless\nthere is a good reason not to, but I reserve the right to redo it differently.\n\n\tucbvax!termcap\t\t\t\t(uucp)\n\ttermcap@berkeley\t\t\t(Arpanet)\nor\n\tKevin Layer\n\tComputer Science Division\n\tEvans Hall\n\tUniversity of California\n\tBerkeley, California  94720\n"
  },
  {
    "path": "lib/libtermlib/termcap/map3270",
    "content": "# /usr/share/misc/map3270\n# mail corrections and additions to \"termcap\"\n#\n# this file contains mappings between characters entered from the keyboard,\n# and 3270 keys, for use by programs (like tn3270) doing 3270 emulation\n# from unix.\n#\n# inside the single quotes, a caret (\"^\") introduces a control character\n# sequence (rub out = ^?, by the way).  also inside the single quotes,\n# a backslash ('\\') introduces an escaped character.  Also, \\n, \\r, \\t,\n# are all as in c, and \\E is another way of representing escape.\n#\n#\tNOTE that while we are defining lots of function, much of that\n# function (ie: local editing keys) may not yet be available from\n# tn3270.\n\n\n3a | adm3a {\n    enter = '^m';\n    clear = '^z';\n\n    nl = '^n' | '^^';\n    tab = '^i';\n    btab = '^b';\n    left = '^h';\n    right = '^l';\n    up = '^k';\n    down = '^j';\n    home = '^@';\n\n    delete = '^d' | '^?';\n    eeof = '^e';\n    einp = '^w';\n    insrt = '\\E ';\n    dp = '^u';\n    fm = '^y';\n\n    # pf keys\n    pfk1 = '\\E1'; pfk2 = '\\E2'; pfk3 = '\\E3'; pfk4 = '\\E4';\n    pfk5 = '\\E5'; pfk6 = '\\E6'; pfk7 = '\\E7'; pfk8 = '\\E8';\n    pfk9 = '\\E9'; pfk10 = '\\E0'; pfk11 = '\\E:'; pfk12 = '\\E-';\n    pfk13 = '^f13'; pfk14 = '^f14'; pfk15 = '^f15'; pfk16 = '^f16';\n    pfk17 = '^f17'; pfk18 = '^f18'; pfk19 = '^f19'; pfk20 = '^f20';\n    pfk21 = '^f21'; pfk22 = '^f22'; pfk23 = '^f23'; pfk24 = '^f24';\n\n    # program attention keys\n    pa1 = '^p1';\n    pa2 = '^p2';\n    pa3 = '^p3';\n\n    # other keys\n    cursel = '\\E.';\n\n    # local control keys\n\n    reset = '^t';\t# well, there is a little confusion here...\n    master_reset = '^g';\n    flinp = '^x';\n    reshow = '^v';\t# redisplay screen \n    escape = '^c';\t# escape to telnet command mode\n\n    # local editing keys\n    settab = '\\E;';\n    clrtab = '\\E+';\n    setmrg = '\\E(';\n    sethom = '\\E!';\n    coltab = '\\Ei';\n    colbak = '\\Eb';\n    indent = '\\El';\n    undent = '\\Eh';\n\n} # end of adm3a\n\n920c | tvi920c {\t# tvi920c definitions...\n\n    # command keys\n    enter = '^m';\n    clear = '^z';\n\n    # cursor movement keys\n    nl = '^^';\n    tab = '^i';\n    btab = '^b';\n    left = '^h';\n    right = '^l';\n    up = '^k';\n    down = '^j';\n    home = '^@';\n\n    # edit control keys\n    delete = '^?' | '^d';\n    eeof = '^e';\n    einp = '^w';\n    insrt = '\\E ';\n    dp = '^u';\n    fm = '^y';\n\n    # program function keys\n    pfk1 = '^a@^m'; pfk2 = '^aA^m'; pfk3 = '^aB^m'; pfk4 = '^aC^m';\n    pfk5 = '^aD^m'; pfk6 = '^aE^m'; pfk7 = '^aF^m'; pfk8 = '^aG^m';\n    pfk9 = '^aH^m'; pfk10 = '^aI^m'; pfk11 = '^aJ^m' | '\\E^a@^m';\n\t\t\t\t\t\tpfk12 = '^aj^m' | '\\E^aA^m';\n    pfk13 = '\\E^aB^m'; pfk14 = '\\E^aC^m'; pfk15 = '\\E^aD^m'; pfk16 = '\\E^aE^m';\n    pfk17 = '\\E^aF^m'; pfk18 = '\\E^aG^m'; pfk19 = '\\E^aH^m'; pfk20 = '\\E^aI^m';\n    pfk21 = '\\E^a`^m'; pfk22 = '\\E^aa^m'; pfk23 = '\\E^ab^m'; pfk24 = '\\E^ac^m';\n\n    # program attention keys\n\n    pa1 = '^a`^m';\n    pa2 = '^aa^m';\n    pa3 = '^ab^m';\n\n    # miscellaneous 3270 keys\n\n    cursel = '\\E.';\n\n    # local control keys\n\n    reset = '^t';\t\t# there is some confusion here...\n    master_reset = '^g';\n    flinp = '^x';\n    reshow = '^v';\n    escape = '^c';\t# escape to telnet command mode\n\n    # local editing keys\n\n    settab = '\\E;';\n    clrtab = '\\E:';\n    setmrg = '\\E*';\n    sethom = '\\E!';\n    coltab = '\\Ei' | '\\EI';\n    colbak = '\\Eb' | '\\EB';\n    indent = '\\El' | '\\EL';\n    undent = '\\Eh' | '\\EH';\n} # end of tvi920c table...\n\n925 | tvi925 | 925vb | tvi925vb | televideo 925 {\n\n    # command keys\n\n    enter = '^m';\n    clear = '^z';\n\n    # cursor movement keys\n\n    nl = '^j';\n    tab = '^i';\n    btab = '\\EI';\n    left = '^h';\n    right = '^l';\n    up = '^k';\n    down = '^v';\n    home = '^^';\n\n    # edit control keys\n\n    delete = '^?';\t# that's rubout...\n    eeof = '^e';\n    einp = '^w';\n    insrt = '\\E ' | '\\EW';\n\n    # program function keys\n\n    pfk1 = '^a@^m';\n    pfk2 = '^aA^m';\n    pfk3 = '^aB^m';\n    pfk4 = '^aC^m';\n    pfk5 = '^aD^m';\n    pfk6 = '^aE^m';\n    pfk7 = '^aF^m';\n    pfk8 = '^aG^m';\n    pfk9 = '^aH^m';\n    pfk10 = '^aI^m';\n    pfk11 = '^aJ^m';\n    pfk12 = '\\EQ';\n    pfk13 = '\\E^a@^m';\n    pfk14 = '\\E^aA^m';\n    pfk15 = '\\E^aB^m';\n    pfk16 = '\\E^aC^m';\n    pfk17 = '\\E^aD^m';\n    pfk18 = '\\E^aE^m';\n    pfk19 = '\\E^aF^m';\n    pfk20 = '\\E^aG^m';\n    pfk21 = '\\E^aH^m';\n    pfk22 = '\\E^aI^m';\n    pfk23 = '\\E^aJ^m';\n    pfk24 = '\\E\\EQ';\n\n    # program attention keys\n\n    pa1 = '^a`^m';\n    pa2 = '^aa^m';\n    pa3 = '^ab^m';\n\n    # other keys\n\n    # local control keys\n\n    reset = '^t';\t\t# again, there is some confusion here...\n    master_reset = '^g';\n    flinp = '^x';\n    reshow = '^b';\n    escape = '^c';\t# escape to telnet command mode\n\n# local editing keys\n\n    settab = '\\EY';\n    deltab = '\\Ey';\n    clrtab = '\\E:';\n    setmrg = '\\ET';\n    sethom = '\\Et';\n    coltab = '^p';\n    colbak = '^o';\n    indent = '\\ER';\n    undent = '\\EE';\n}\n\n\n924 | tvi924 {\n\n    # command keys\n\n    enter = '^m';\n    clear = '^z';\n\n    # cursor movement keys\n\n    nl = '^j';\n    tab = '^i';\n    btab = '\\EI';\n    left = '^h';\n    right = '^l';\n    up = '^k';\n    down = '^v';\n    home = '^^';\n\n    # edit control keys\n\n    delete = '^?';\t# that's rubout...\n    eeof = '^e';\n    einp = '^w';\n    insrt = '\\E ' | '\\EW';\n    dp = '^u';\n    fm = '^y';\n\n    # program function keys\n\n    pfk1 = '^a@^m';\n    pfk2 = '^aA^m';\n    pfk3 = '^aB^m';\n    pfk4 = '^aC^m';\n    pfk5 = '^aD^m';\n    pfk6 = '^aE^m';\n    pfk7 = '^aF^m';\n    pfk8 = '^aG^m';\n    pfk9 = '^aH^m';\n    pfk10 = '^aI^m';\n    pfk11 = '^aJ^m';\n    pfk12 = '^aK^m';\n    pfk13 = '\\E^a@^m';\n    pfk14 = '\\E^aA^m';\n    pfk15 = '\\E^aB^m';\n    pfk16 = '\\E^aC^m';\n    pfk17 = '\\E^aD^m';\n    pfk18 = '\\E^aE^m';\n    pfk19 = '\\E^aF^m';\n    pfk20 = '\\E^aG^m';\n    pfk21 = '\\E^aH^m';\n    pfk22 = '\\E^aI^m';\n    pfk23 = '\\E^aJ^m';\n    pfk24 = '\\E^aK^m';\n\n    # program attention keys\n\n    pa1 = '^a`^m';\n    pa2 = '^aa^m';\n    pa3 = '^ab^m';\n\n    # other keys\n\n    # local control keys\n\n    reset = '^t';\t\t# again, there is some confusion here...\n    master_reset = '^g';\n    flinp = '^x';\n    reshow = '^b';\n    escape = '^c';\t# escape to telnet command mode\n\n    # local editing keys\n\n    settab = '\\EY';\n    deltab = '\\Ey';\n    clrtab = '\\E:';\n    setmrg = '\\ET';\n    sethom = '\\Et';\n    coltab = '^p';\n    colbak = '^o';\n    indent = '\\ER';\n    undent = '\\EE';\n}\n\n#kb | h19 | heath | h19b | heathkit | heath-19 | z19 | zenith {\n kb | h19 | heath | h19b | heathkit | z19 | zenith {  #coughs on heath-19\nenter = '^m';\nclear = '^z';\n\nnl = '^n' | '^?';\ntab = '^i';\nbtab = '^b';\nleft = '^h';\nright = '^l';\nup = '^k';\ndown = '^j';\nhome = '^@';\n\ndelete = '^d';\neeof = '^e';\neinp = '^w';\ninsrt = '\\E ';\n\n# pf keys\npfk1 = '\\E?p\\E?q'; pfk2 = '\\E?p\\E?r'; pfk3 = '\\E?p\\E?s'; pfk4 = '\\E?p\\E?t';\npfk5 = '\\E?p\\E?u'; pfk6 = '\\E?p\\E?v'; pfk7 = '\\E?p\\E?w'; pfk8 = '\\E?p\\E?x';\npfk9 = '\\E?p\\E?y'; pfk10 = '\\E?q\\E?p'; pfk11 = '\\E?q\\E?q'; pfk12 = '\\E?q\\E?r';\npfk13 = '\\E?q\\E?s'; pfk14 = '\\E?q\\E?t'; pfk15 = '\\E?q\\E?u'; pfk16 = '\\E?q\\E?v';\npfk17 = '\\E?q\\E?w'; pfk18 = '\\E?q\\E?x'; pfk19 = '\\E?q\\E?y'; pfk20 = '\\E?r\\E?p';\npfk21 = '\\E?r\\E?q'; pfk22 = '\\E?r\\E?r'; pfk23 = '\\E?r\\E?s'; pfk24 = '\\E?r\\E?t';\n\n# program attention keys\npa1 = '\\EP';\npa2 = '\\EQ';\npa3 = '\\ER';\n\n# other keys\n# cursel = '\\E.'; # find out what this does\nmaster_reset = '^g';\n\n# local control keys\n\nreset = '^t';\t# well, there is a little confusion here...\nflinp = '^x';\nreshow = '^v';\t# redisplay screen \nescape = '^c';\t# escape to telnet command mode\n\n# local editing keys\nsettab = '\\E;';\nclrtab = '\\E:';\nsetmrg = '\\E\\'';\nsethom = '\\E!';\ncoltab = '\\Ei';\ncolbak = '\\Eb';\nindent = '\\El';\nundent = '\\Eh';\n\n} # end of h19\n\n\n#co | c100 | concept | c100-4p | concept100 {\nco | c100 | concept | concept100 {  # coughs on c100-4p\nenter = '^m';\nclear = '^z' | '^\\2';\n\nnl = '^n';\ntab = '^i';\nbtab = '^b';\nleft = '^h' | '\\E>';\nright = '^l' | '\\E=';\nup = '^k' | '\\E;';\ndown = '^j' | '\\E<';\nhome = '\\E?';\n\ndelete = '^d' | '^?' | '^\\1';\neeof = '^e' | '^\\3';\neinp = '^w';\ninsrt = '^\\0';\n\n# pf keys\npfk1 = '\\E\\E1' | '^\\5'; pfk2 = '\\E\\E2' | '^\\6'; pfk3 = '\\E\\E3' | '^\\7';\npfk4 = '\\E\\E4' | '^\\8'; pfk5 = '\\E\\E5' | '^\\9'; pfk6 = '\\E\\E6' | '^\\:';\npfk7 = '\\E\\E7' | '^\\;'; pfk8 = '\\E\\E8' | '^\\<'; pfk9 = '\\E\\E9' | '^\\=';\npfk10 = '\\E\\E0' | '^\\>'; pfk11 = '\\E\\E-' | '^\\?'; pfk12 = '^\\@';\npfk13 = '^\\A'; pfk14 = '^\\B'; pfk15 = '^\\)'; pfk16 = '^\\*';\npfk17 = '^\\+'; pfk18 = '^\\,'; pfk19 = '^\\-'; pfk20 = '^\\.';\npfk21 = '^\\/'; pfk22 = '^\\C'; pfk23 = '^\\D'; pfk24 = '^\\E';\n\n# program attention keys\npa1 = '^\\%';\npa2 = '^\\&' | '\\E+';\npa3 = '^\\\\'';\n\n# other keys\ncursel = '\\E.'; \naplon = '\\E{';\naplend = '\\E}';\naploff = '\\E_';\nmaster_reset = '^g';\n\n# local control keys\n\nreset = '^t';\t# well, there is a little confusion here...\nflinp = '^x';\nreshow = '^v';\t# redisplay screen \nescape = '^c';\t# escape to telnet command mode\n\n# local editing keys\nsettab = '\\E\\E;';\nclrtab = '\\E\\E:';\nsetmrg = '\\E\\E*';\nsethom = '\\E\\E!';\ncoltab = '\\E\\Ei';\ncolbak = '\\E\\Eb';\nindent = '\\E\\El';\nundent = '\\E\\Eh';\n\n} # end of concept\navt | vt100 | vt100nam | pt100 | vt125 | vt102 | direct831 {\nenter = '^m';\nclear = '^z' | '\\EOM';\t\t\t# Keypad enter key\n\nnl = '^?';\ntab = '^i';\nbtab = '^b';\nleft = '^h' | '\\E[D' | '\\EOD';\t\t# Arrow key (application/numeric modes)\nright = '^l' | '\\E[C' | '\\EOC';\t\t# Arrow key (application/numeric modes)\nup = '^k' | '\\E[A' | '\\EOA';\t\t# Arrow key (application/numeric modes)\ndown = '^j' | '\\E[B' | '\\EOB';\t\t# Arrow key (application/numeric modes)\nhome = '\\EOn';\t\t\t\t# Keypad period key\n\ndelete = '^d';\neeof = '^e';\neinp = '^w';\ninsrt = '^ ';\n\n# pfk keys\n# Keypad digits 1-9 correspond to pf keys 1-9\npfk1 = '\\EOq' | '\\E1'; pfk2 = '\\EOr' | '\\E2'; pfk3 = '\\EOs' | '\\E3';\npfk4 = '\\EOt' | '\\E4'; pfk5 = '\\EOu' | '\\E5'; pfk6 = '\\EOv' | '\\E6';\npfk7 = '\\EOw' | '\\E7'; pfk8 = '\\EOx' | '\\E8'; pfk9 = '\\EOy' | '\\E9';\n\n# Keypad digits 0-9 prefixed by pf1 (gold key) correspond to pfk10-19\npfk10 = '\\EOP\\EOp' | '\\E0'; pfk11 = '\\EOP\\EOq' | '\\E-';\npfk12 = '\\EOP\\EOr' | '\\E='; pfk13 = '\\EOP\\EOs' | '^f13';\npfk14 = '\\EOP\\EOt' | '^f14'; pfk15 = '\\EOP\\EOu' | '^f15';\npfk16 = '\\EOP\\EOv' | '^f16'; pfk17 = '\\EOP\\EOw' | '^f17';\npfk18 = '\\EOP\\EOx' | '^f18'; pfk19 = '\\EOP\\EOy' | '^f19';\n\n# Keypad digits 0-9 prefixed by pf2 correspond to pfk20,21\npfk20 = '\\EOQ\\EOp' | '^f20'; pfk21 = '\\EOQ\\EOq' | '^f21';\n\n# program attention keys\npa1 = '\\E\\EOP' | '^p1';\t\t# pa1 is Escape pf1\npa2 = '\\E\\EOQ' | '^p2';\t\t# pa2 is Escape pf2\n\n# local control keys\n\nreset = '^t';\t# well, there is a little confusion here...\nflinp = '^x';\nreshow = '^v';\t# redisplay screen \nescape = '^c';\t# escape to telnet command mode\nmaster_reset = '^g';\n\n# local editing keys\nsettab = '\\E;';\t\t\t# Escape key\ndeltab = '\\E\\'';\t\t# Escape \\\nclrtab = '\\E:';\t\t\t# Escape :\nsetmrg = '\\E,';\t\t\t# Escape ,\nsethom = '\\E.';\t\t\t# Escape .\ncoltab = '\\E\\E[B' | '\\E\\EOB';\t# Escape down-arrow\ncolbak = '\\E\\E[A' | '\\E\\EOA';\t# Escape up-arrow\nindent = '\\E\\E[C' | '\\E\\EOC';\t# Escape right-arrow\nundent = '\\E\\E[D' | '\\E\\EOD';\t# Escape left-arrow\n}    # end of vt100, etc.\n\ntvipt | vp | televideopt {\n    enter = '^m';\n    clear = '^z';\n\n nl = '^n';\n    tab = '^i';\n    btab = '^b';\n    left = '^h';\n    right = '^l';\n    up = '^k';\n    down = '^j';\n    home = '^^';\n\n    delete = '^?';\n    eeof = '^e';\n    einp = '^w';\n    insrt = '\\E ';\n\n    # pf keys\n    pfk1 = '\\E1' | '^A@^m';\t\t\n    pfk2 = '\\E2' | '^AA^m';\n    pfk3 = '\\E3' | '^AB^m'; \n    pfk4 = '\\E4' | '^AC^m';\n    pfk5 = '\\E5' | '^AD^m';\n    pfk6 = '\\E6' | '^AE^m'; \n    pfk7 = '\\E7' | '^AF^m';\n    pfk8 = '\\E8';\n    pfk9 = '\\E9';\n    pfk10 = '\\E0';\n    pfk11 = '\\E!' | '\\E^A@^m';\n    pfk12 = '\\E@' | '\\E^AA^m';\n    pfk13 = '\\E#' | '\\E^AB^m';\n    pfk14 = '\\E$' | '\\E^AC^m';\n    pfk15 = '\\E%' | '\\E^AD^m';\n    pfk16 = '\\E^AE^m' | '\\E\\^';\n    pfk17 = '\\E&' | '\\E^AF^m';\n    pfk18 = '\\E*'; \n    pfk19 = '\\E(';\n    pfk20 = '\\E)';\n\n    # program attention keys\n    pa1 = '^AG^m';\n    pa2 = '^AH^m';\n    pa3 = '^AI^m';\n\n    # other keys\n#    # cursel = '\\E.';\n\n    # local control keys\n\n    reset = '^t';\t# well, there is a little confusion here...\n    master_reset = '^g';\n    flinp = '^x';\n    reshow = '^v';\t# redisplay screen \n    escape = '^c';\t# escape to telnet command mode\n\n    # local editing keys\n    settab = '\\E;';\n    clrtab = '\\E:';\n    setmrg = '\\E[';\n    sethom = '\\E+';\n    coltab = '\\Ei' | '\\EI';\n    colbak = '\\Eb' | '\\EB';\n    indent = '\\El' | '\\EL';\n    undent = '\\Eh' | '\\EH';\n} # end of tvipt\n"
  },
  {
    "path": "lib/libtermlib/termcap/reorder",
    "content": "$r termcap.local\n/|c100|/;.,/^[^\t]/-m9\n/|c100-rv|/;.,/^[^\t]/-m9\n/|c100-rv-pp|/;.,/^[^\t]/-m9\n/|c108-4p|/;.,/^[^\t]/-m9\n/|c108-rv-4p|/;.,/^[^\t]/-m9\n/|c108-8p|/;.,/^[^\t]/-m9\n/|c108-rv-8p|/;.,/^[^\t]/-m9\n/|avt|/;.,/^[^\t]/-m9\n/|avt-rv|/;.,/^[^\t]/-m9\n/|avt-4p-s|/;.,/^[^\t]/-m9\n/|avt-8p-s|/;.,/^[^\t]/-m9\n/|sun-17|/;.,/^[^\t]/-m9\n/|sun-24|/;.,/^[^\t]/-m9\n/|sun-34|/;.,/^[^\t]/-m9\n/|sun-48|/;.,/^[^\t]/-m9\n/|sun-s-e|/;.,/^[^\t]/-m9\n/|sun-s|/;.,/^[^\t]/-m9\n/|sun-e|/;.,/^[^\t]/-m9\n/|sun|/;.,/^[^\t]/-m9\n/|xterms|/;.,/^[^\t]/-m9\n/|xterm|/;.,/^[^\t]/-m9\n/|adm3|/;.,/^[^\t]/-m9\n/|adm31|/;.,/^[^\t]/-m9\n/|adm3a|/;.,/^[^\t]/-m9\n/|vt100|/;.,/^[^\t]/-m9\n/|vt220|/;.,/^[^\t]/-m9\n/|2645|/;.,/^[^\t]/-m9\n/|2621-nl|/;.,/^[^\t]/-m9\n/|2621|/;.,/^[^\t]/-m9\n/|h29|/;.,/^[^\t]/-m9\n/|h19|/;.,/^[^\t]/-m9\n/|h19-u|/;.,/^[^\t]/-m9\n/|h19-us|/;.,/^[^\t]/-m9\n/|h19-e|/;.,/^[^\t]/-m9\n/|h19-g|/;.,/^[^\t]/-m9\n/|5620|/;.,/^[^\t]/-m9\n/^s/;.,/^#/-m9\nw! termcap.full\nq\n"
  },
  {
    "path": "lib/libtermlib/termcap/tabset/3101",
    "content": "\u001bH        \u001b0        \u001b0        \u001b0        \u001b0        \u001b0        \u001b0        \u001b0        \u001b0        \u001b0\n"
  },
  {
    "path": "lib/libtermlib/termcap/tabset/aa",
    "content": "\u001c\u0010\u0010        \u001d\u00101       \u001d\u00101       \u001d\u00101       \u001d\u00101       \u001d\u00101       \u001d\u00101       \u001d\u00101       \u001d\u00101       \u001d\u00101       \u001d\u0010\u0010\n"
  },
  {
    "path": "lib/libtermlib/termcap/tabset/aed512",
    "content": "\\EG1MMM.`40K0001202080K8001????00^L\\EC80L80{80^L\\EK010100????K0601??0000c818100\\EG1HHH.\\07210000019A27FD006A280D002A200A52429FE8524861086118612861360N031B4C3F3F1800N041B0C1B4C38301800N001B3B313030301800N011B3B313030341800N021B3B313030381800N050800N061B3B313335301800\\07211000015A58E8D5011A58F8D5111A5908D5211A5918D531160\\07212000015AD5011858EAD5111858FAD52118590AD5311859160\\0721300004B2071C5858E0A18658E0A0A858EA900858F268FA5278590A50A29018591A9F51865908590A90165918591A59038E58E8590A591E58F290185912071C5180A0A0A0901858EA900858F268F60\\0721350000BA9472031DEA9502031DE60\\E\\E\\E\\EG1MMM.^A\n"
  },
  {
    "path": "lib/libtermlib/termcap/tabset/beehive",
    "content": "\r\u000b\n\u0006 \u0016 \u0016 \u0016 \u0016 \u0016 \u0016 \u0016 \u0006 \u0016 \u0016 \u0016 \u0016 \u0016 \u0016 \u0016 \u0006 \u0016 \u0016 \u0016 \u0016 \u0016 \u0016 \u0016 \u0006 \u0016 \u0016 \u0016 \u0016 \u0016 \u0016 \u0016 \u0006 \u0016 \u0016 \u0016 \u0016 \u0016 \u0016 \u0016 \u0006 \u0016 \u0016 \u0016 \u0016 \u0016 \u0016 \u0016 \u0006 \u0016 \u0016 \u0016 \u0016 \u0016 \u0016 \u0016 \u0006 \u0016 \u0016 \u0016 \u0016 \u0016 \u0016 \u0016 \u0006 \u0016 \u0016 \u0016 \u0016 \u0016 \u0016 \u0016 \u0006 \u0016 \u0016 \u0016 \u0016 \u0016 \u0016 \u0016\u000b\n"
  },
  {
    "path": "lib/libtermlib/termcap/tabset/diablo",
    "content": "\u001b\t\u0001\u001b9\n\u001b2\u001b\t\t\u001b1\u001b\t\u0011\u001b1\u001b\t\u0019\u001b1\u001b\t!\u001b1\u001b\t)\u001b1\u001b\t1\u001b1\u001b\t9\u001b1\u001b\tA\u001b1\u001b\tI\u001b1\u001b\tQ\u001b1\u001b\tY\u001b1\u001b\ta\u001b1\u001b\ti\u001b1\u001b\tq\u001b1\u001b\ty\u001b1\n\t\u001b9\n"
  },
  {
    "path": "lib/libtermlib/termcap/tabset/dtc382",
    "content": "\r\u001b\t        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1\r"
  },
  {
    "path": "lib/libtermlib/termcap/tabset/ibm3101",
    "content": "\u001bH        \u001b0        \u001b0        \u001b0        \u001b0        \u001b0        \u001b0        \u001b0        \u001b0        \u001b0\r"
  },
  {
    "path": "lib/libtermlib/termcap/tabset/std",
    "content": "\r\u001b3\r        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1\n"
  },
  {
    "path": "lib/libtermlib/termcap/tabset/stdcrt",
    "content": "\r\u001b3\r        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1\r"
  },
  {
    "path": "lib/libtermlib/termcap/tabset/tandem653",
    "content": "\u001b3\r\u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1\n"
  },
  {
    "path": "lib/libtermlib/termcap/tabset/teleray",
    "content": "\u001bG\u001bY9(\u001bF\u001bY90\u001bF\u001bY98\u001bF\u001bY9@\u001bF\u001bY9H\u001bF\u001bY9P\u001bF\u001bY9X\u001bF\u001bY9`\u001bF\u001bY9h\u001bF\r"
  },
  {
    "path": "lib/libtermlib/termcap/tabset/vt100",
    "content": "\n\u001b[3g\n\u001bH        \u001bH        \u001bH        \u001bH        \u001bH        \u001bH        \u001bH        \u001bH        \u001bH        \u001bH        \u001bH        \u001bH        \u001bH        \u001bH        \u001bH        \u001bH\n"
  },
  {
    "path": "lib/libtermlib/termcap/tabset/wyse-adds",
    "content": "Setting tabs...\r\u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b1 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b1 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b1 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b1 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b1 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b1 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b1 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b1 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b1 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2 \u001b2\n\n\r\n"
  },
  {
    "path": "lib/libtermlib/termcap/tabset/xerox1720",
    "content": "\u001b2        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1        \u001b1\r"
  },
  {
    "path": "lib/libtermlib/termcap/tabset/zenith29",
    "content": "\u001b[3g\r\u001bH        \u001bH        \u001bH        \u001bH        \u001bH        \u001bH        \u001bH        \u001bH        \u001bH        \u001bH\n"
  },
  {
    "path": "lib/libtermlib/termcap/termcap.local",
    "content": "#\n# END OF LOCAL TERMCAP\n# --------------------------\n"
  },
  {
    "path": "lib/libtermlib/termcap/termcap.small",
    "content": "# Copyright (c) 1980, 1985, 1989 The Regents of the University of California.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n# 1. Redistributions of source code must retain the above copyright\n#    notice, this list of conditions and the following disclaimer.\n# 2. Redistributions in binary form must reproduce the above copyright\n#    notice, this list of conditions and the following disclaimer in the\n#    documentation and/or other materials provided with the distribution.\n# 3. All advertising materials mentioning features or use of this software\n#    must display the following acknowledgement:\n#\tThis product includes software developed by the University of\n#\tCalifornia, Berkeley and its contributors.\n# 4. Neither the name of the University nor the names of its contributors\n#    may be used to endorse or promote products derived from this software\n#    without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n# ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n# SUCH DAMAGE.\n#\n#\t@(#)termcap.src\t5.88 (Berkeley) 4/30/91\n# $FreeBSD$\n#\ncons25|ansi|ansi80x25:\\\n\t:am:bs:NP:ms:pt:AX:eo:bw:ut:km:\\\n\t:co#80:li#25:pa#64:Co#8:it#8:\\\n\t:al=\\E[L:cd=\\E[J:ce=\\E[K:cl=\\E[H\\E[J:cm=\\E[%i%d;%dH:\\\n\t:dc=\\E[P:dl=\\E[M:do=\\E[B:bt=\\E[Z:ho=\\E[H:ic=\\E[@:cb=\\E[1K:\\\n\t:nd=\\E[C:rs=\\Ec:so=\\E[7m:se=\\E[27m:up=\\E[A:cr=^M:ta=^I:\\\n\t:AF=\\E[3%dm:AB=\\E[4%dm:op=\\E[39;49m:sc=\\E7:rc=\\E8:\\\n\t:k1=\\E[M:k2=\\E[N:k3=\\E[O:k4=\\E[P:k5=\\E[Q:k6=\\E[R:k7=\\E[S:k8=\\E[T:\\\n\t:k9=\\E[U:k;=\\E[V:F1=\\E[W:F2=\\E[X:K2=\\E[E:nw=\\E[E:ec=\\E[%dX:\\\n\t:kb=^H:kh=\\E[H:ku=\\E[A:kd=\\E[B:kl=\\E[D:kr=\\E[C:le=^H:sf=\\E[S:sr=\\E[T:\\\n\t:kN=\\E[G:kP=\\E[I:@7=\\E[F:kI=\\E[L:kD=\\177:kB=\\E[Z:\\\n\t:IC=\\E[%d@:DC=\\E[%dP:SF=\\E[%dS:SR=\\E[%dT:AL=\\E[%dL:DL=\\E[%dM:\\\n\t:DO=\\E[%dB:LE=\\E[%dD:RI=\\E[%dC:UP=\\E[%dA:cv=\\E[%i%dd:ch=\\E[%i%d`:\\\n\t:mb=\\E[5m:md=\\E[1m:mr=\\E[7m:me=\\E[m:bl=^G:\\\n\t:ve=\\E[=S:vi=\\E[=1S:vs=\\E[=2S:\n\nvt100|dec-vt100|vt100-am|vt100am|dec vt100:\\\n\t:do=2\\E[B:co#80:li#24:cl=50\\E[H\\E[J:sf=2*\\ED:\\\n\t:le=^H:bs:am:cm=5\\E[%i%d;%dH:nd=2\\E[C:up=2\\E[A:\\\n\t:ce=3\\E[K:cd=50\\E[J:so=2\\E[7m:se=2\\E[m:us=2\\E[4m:ue=2\\E[m:\\\n\t:md=2\\E[1m:mr=2\\E[7m:mb=2\\E[5m:me=2\\E[m:\\\n\t:is=\\E>\\E[?1;3;4;5l\\E[?7;8h\\E[1;24r\\E[24;1H:\\\n\t:if=/usr/share/tabset/vt100:nw=2\\EE:ho=\\E[H:\\\n\t:as=2\\E(0:ae=2\\E(B:\\\n\t:ac=``aaffggjjkkllmmnnooppqqrrssttuuvvwwxxyyzz{{||:\\\n\t:rs=\\E>\\E[?1;3;4;5l\\E[?7;8h:ks=\\E[?1h\\E=:ke=\\E[?1l\\E>:\\\n\t:ku=\\EOA:kd=\\EOB:kr=\\EOC:kl=\\EOD:kb=\\177:\\\n\t:k0=\\EOy:k1=\\EOP:k2=\\EOQ:k3=\\EOR:k4=\\EOS:k5=\\EOt:\\\n\t:k6=\\EOu:k7=\\EOv:k8=\\EOl:k9=\\EOw:k;=\\EOx:@8=\\EOM:\\\n\t:K1=\\EOq:K2=\\EOr:K3=\\EOs:K4=\\EOp:K5=\\EOn:pt:sr=2*\\EM:xn:\\\n\t:sc=2\\E7:rc=2\\E8:cs=5\\E[%i%d;%dr:UP=2\\E[%dA:DO=2\\E[%dB:RI=2\\E[%dC:\\\n\t:LE=2\\E[%dD:ct=2\\E[3g:st=2\\EH:ta=^I:ms:bl=^G:cr=^M:eo:it#8:\\\n\t:RA=\\E[?7l:SA=\\E[?7h:po=\\E[5i:pf=\\E[4i:\n\n# $XTermId: termcap,v 1.78 2009/11/09 00:24:26 tom Exp $\n#\nxterm|linux|modern xterm:\\\n\t:@7=\\EOF:@8=\\EOM:F1=\\E[23~:F2=\\E[24~:K2=\\EOE:Km=\\E[M:\\\n\t:k1=\\EOP:k2=\\EOQ:k3=\\EOR:k4=\\EOS:k5=\\E[15~:k6=\\E[17~:\\\n\t:k7=\\E[18~:k8=\\E[19~:k9=\\E[20~:k;=\\E[21~:kI=\\E[2~:\\\n\t:kN=\\E[6~:kP=\\E[5~:kd=\\EOB:kh=\\EOH:kl=\\EOD:kr=\\EOC:ku=\\EOA:\\\n\t:tc=xterm-basic:\n#\n# This chunk is used for building the VT220/Sun/PC keyboard variants.\nxterm-basic|modern xterm common:\\\n\t:am:bs:km:mi:ms:ut:xn:AX:\\\n\t:Co#8:co#80:kn#12:li#24:pa#64:\\\n\t:AB=\\E[4%dm:AF=\\E[3%dm:AL=\\E[%dL:DC=\\E[%dP:DL=\\E[%dM:\\\n\t:DO=\\E[%dB:LE=\\E[%dD:RI=\\E[%dC:UP=\\E[%dA:ae=\\E(B:al=\\E[L:\\\n\t:as=\\E(0:bl=^G:cd=\\E[J:ce=\\E[K:cl=\\E[H\\E[2J:\\\n\t:cm=\\E[%i%d;%dH:cs=\\E[%i%d;%dr:ct=\\E[3g:dc=\\E[P:dl=\\E[M:do=\\E[B:\\\n\t:ei=\\E[4l:ho=\\E[H:im=\\E[4h:is=\\E[!p\\E[?3;4l\\E[4l\\E>:\\\n\t:kD=\\E[3~:kb=^H:ke=\\E[?1l\\E>:ks=\\E[?1h\\E=:le=^H:md=\\E[1m:\\\n\t:me=\\E[m:ml=\\El:mr=\\E[7m:mu=\\Em:nd=\\E[C:op=\\E[39;49m:\\\n\t:rc=\\E8:rs=\\E[!p\\E[?3;4l\\E[4l\\E>:sc=\\E7:se=\\E[27m:sf=^J:\\\n\t:so=\\E[7m:sr=\\EM:st=\\EH:\\\n\t:ue=\\E[24m:up=\\E[A:us=\\E[4m:ve=\\E[?12l\\E[?25h:vi=\\E[?25l:vs=\\E[?12;25h:\n#\n# This should work for the commonly used \"color xterm\" variations (XFree86\n# xterm, color_xterm, nxterm, rxvt).  Note that it does not set 'bce', so for\n# XFree86 and rxvt, some applications that use colors will be less efficient,\n# and in a few special cases (with \"smart\" optimization) the wrong color will\n# be painted in spots.\nxterm-color|generic \"ANSI\" color xterm:\\\n\t:Co#8:NC@:pa#64:\\\n\t:AB=\\E[4%dm:AF=\\E[3%dm:ac=:op=\\E[m:tc=xterm-r6:\n"
  },
  {
    "path": "lib/libtermlib/termcap/termcap.src",
    "content": "# ------------------------\n#\n#\tTermcap source file\t@(#)termcap.src\t5.40.1 (2.11BSD) 1996/10/21\n#\tJohn Kunze, Berkeley\n#\tCraig Leres, Berkeley\n#\n# Please mail changes to (arpanet):  termcap@berkeley\n# See DESCRIPTION section for information about contents.\n#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n# DESCRIPTION:\n# This file describes capabilities of various terminals, as needed by\n# software such as screen editors.  It does not attempt to describe\n# printing terminals very well, nor graphics terminals.  Someday.\n# See termcap(5) in the Unix Programmers Manual for documentation.\n#\n# Conventions: First entry is two chars, first char is manufacturer,\n# second char is canonical name for model or mode.\n# Third entry is the one the editor will print with \"set\" command.\n# Last entry is verbose description.\n# Others are mnemonic synonyms for the terminal.\n#\n# Terminal naming conventions:\n# Terminal names look like <manufacturer> <model> - <modes/options>\n# Certain abbreviations (e.g. c100 for concept100) are also allowed\n# for upward compatibility.  The part to the left of the dash, if a\n# dash is present, describes the particular hardware of the terminal.\n# The part to the right can be used for flags indicating special ROM's,\n# extra memory, particular terminal modes, or user preferences.\n# All names are always in lower case, for consistency in typing.\n#\n# The following are conventionally used flags:\n#\trv\tTerminal in reverse video mode (black on white)\n#\t2p\tHas two pages of memory.  Likewise 4p, 8p, etc.\n#\tw\tWide - in 132 column mode.\n#\tpp\tHas a printer port which is used.\n#\tna\tNo arrow keys - termcap ignores arrow keys which are\n#\t\tactually there on the terminal, so the user can use\n#\t\tthe arrow keys locally.\n#\n# There are some cases where the same name is used for two different\n# terminals, e.g. \"teleray\" or \"2621\" or \"vt100\".  In these cases,\n# if a site has one of these, they should choose a local default and\n# bring that terminal to the front in the reorder script.  This works\n# because tgetent picks the first match in /etc/termcap.\n# The list of names intentionally duplicated is:\n# 2621, c108, dtc, hp2621, teleray, tvi, vt100.\n#\n# To easily test a new terminal description, put it in $HOME/.termcap\n# and programs will look there before looking in /etc/termcap.\n# You can also setenv TERMPATH to a list of full pathnames (separated\n# by spaces or colons) to be searched by tgetent() in the order listed.\n# The TERMCAP environment variable is usually set to the termcap\n# entry itself to avoid reading files when starting up a program.\n#\n# If you absolutely MUST check for a specific terminal (this is discouraged)\n# check for the 2nd entry (the canonical form) since all other codes are\n# subject to change.  The two letter codes are there for version 6 and are\n# EXTREMELY subject to change, or even to go away if version 6 becomes for\n# all practical purposes obsolete.  We would much rather put in special\n# capabilities to describe your terminal rather than having you key on the\n# name.\n#\n#  Special manufacturer codes:\n#\tA: hardcopy daisy wheel terminals\n#\tM: Misc. (with only a few terminals)\n#\tq: Homemade\n#\ts: special (dialup, etc.)\n#\n# Comments in this file begin with # - they cannot appear in the middle\n# of a termcap entry.  Individual entries are commented out by\n# placing a period between the colon and the capability name.\n#\n#  This file is to be installed with an editor script (reorder)\n#  that moves the most common terminals to the front of the file.\n#  If the source is not available, it can be constructed by sorting\n#  the above entries by the 2 char initial code.\n# \f# --------------------------------\n#\n# A: DAISY WHEEL PRINTERS\n#\n# The A manufacturer represents Diablo, DTC, Xerox, Qume, and other Daisy\n# wheel terminals until such time as termcap distinguishes between them\n# enough to justify separate codes.\n# This is an \"experimental\" entry for the SRI Agiles.\n# It has been tried in a minimal way -- the Agile did not blow up!\n# However, it has not been exhaustively tested.\n# Anyone who tries it and finds it wanting should get in touch with:\n#\tRalph Keirstead (ralph@sri-unix);\n#\tEK352; SRI International; 333 Ravenswood Avenue; Menlo Park, CA 94025\nAa|agile|agiles|sri agiles:\\\n\t:bs:hc:os:pl:co#132:do=^J:kb=^H:up=\\E\\n:\\\n\t:hu=\\E0:hd=\\E9:if=/usr/share/tabset/std:is=\\EE\\EF\\EJ:\nA6|1620|1720|450|ipsi|diablo 1620:\\\n\t:do=^J:ct=\\E2:st=\\E1:ch=\\E\\t%i%.:\\\n\t:if=/usr/share/tabset/xerox1720:\\\n\t:kb=^H:le=^H:bs:co#132:hc:hu=\\EU:hd=\\ED:os:pt:up=\\E\\n:\nA7|1620-m8|1640-m8|diablo 1620 w/8 column left margin:\\\n\t:do=^J:co#124:is=\\r        \\E9:tc=1620:\nA8|1640|1740|630|1730|x1700|diablo|xerox|diablo 1640:\\\n\t:if=/usr/share/tabset/xerox1730:\\\n\t:us=\\EE:ue=\\ER:so=\\EW:se=\\E&:tc=1620:\nAm|1640-lm|1740-lm|630-lm|1730-lm|x1700-lm|diablo-lm|xerox-lm|\\\n\tdiablo 1640 with idented left margin:\\\n\t:if=/usr/share/tabset/xerox1730-lm:\\\n\t:co#124:us=\\EE:ue=\\ER:so=\\EW:se=\\E&:tc=1620:\n# DTC 382 with VDU.  Has no cd so we fake it with ce.  Standout works but\n# won't go away without dynamite.  The terminal has tabs, but I'm getting\n# tired of fighting the braindamage.  If no tab is set or the terminal's\n# in a bad mood, it glitches the screen around all of memory.  Note that\n# return puts a blank (\"a return character\") in the space the cursor was\n# at, so we use ^P return (and thus ^P newline for newline).  Note also\n# that if you turn off pt and let Unix expand tabs, curses won't work\n# (current version) because it doesn't turn off this bit, and cursor\n# addressing sends a tab for row/column 9.  What a losing terminal!  I\n# have been unable to get tabs set in all 96 lines - it always leaves at\n# least one line with no tabs in it, and once you tab through that line,\n# it completely weirds out.\nAc|dtc|ps|dtc382|382:\\\n\t:do=^J:al=^P^Z:am:le=^H:\\\n\t:bs:co#80:ce=^P^U:cl=20^P^]:cm=%r^P^Q%.%.:dc=^X:\\\n\t:dl=^P^S:ei=^Pi:ho=^P^R:im=^PI:ve=^Pb:vs=^PB:pc=\\177:te=20^P^]:\\\n\t:li#24:nd=^PR:.se=^P \\200:.so=^P \\002^PF:us=^P \\020:ue=^P \\200:\\\n\t:up=^P^L:nc:xr:xs:da:db:.pt:cr=^P^M:cd=^P^U^P^S^P^S:\\\n\t:if=/usr/share/tabset/dtc382:\nAd|dtc300s|300|300s|dtc 300s:\\\n\t:ct=\\E3:st=\\E1:do=^J:\\\n\t:kb=^h:le=^H:bs:co#132:hc:hu=\\EH:hd=\\Eh:os:pt:up=^Z:\nAg|gsi:\\\n\t:le=^H:bs:co#132:hc:hd=\\Eh:hu=\\EH:os:pt:up=^Z:do=^J:\n# This used to have :pl: - maybe they meant :pt:?\nAj|aj830|aj832|aj|anderson jacobson:\\\n\t:do=^J:le=^H:bs:hc:hd=\\E9:hu=\\E8:os:up=\\E7:\n# From Chris Torek <chris@gyre.umd.edu> Thu, 7 Nov 85 18:21:58 EST\nAJ|aj510|AJ510|Anderson-Jacobson model 510:\\\n\t:ic=:ip=.1*:so=\\E\"I:us=\\E\"U:cd=\\E'P:ce=\\E'L:cl=^L:cm=\\E#%+ %+ :\\\n\t:dl=2*\\E&D:ue=\\E\"U:co#80:li#24:se=\\E\"I:al=2*\\E&I:im=\\E'I:ei=\\E'J:\\\n\t:dc=.1*\\E'D:up=\\EY:nd=\\EX:bs:am:mi:ti=\\E\"N:te=\\E\"N:\\\n\t:ku=\\EY:kd=\\EZ:kl=\\EW:kr=\\EX:pc=\\177:\n# From cbosg!ucbvax!pur-ee!cincy!chris Thu Aug 20 09:09:18 1981\n# This is incomplete, but it's a start.\nAn|5520|nec|spinwriter|nec 5520:\\\n\t:ct=\\E3:st=\\E1:do=^J:kb=^h:le=^H:bs:co#132:hc:hu=\\E]s\\E9\\E]W:\\\n\t:hd=\\E]s\\n\\E]W:os:pt:up=\\E9:\nAq|qume5|qume|Qume Sprint 5:\\\n\t:ct=\\E3:st=\\E1:do=^J:\\\n\t:kb=^h:le=^H:bs:co#80:hc:hu=\\EH:hd=\\Eh:os:pt:up=^Z:\nAr|q102|qume102|Qume 102:\\\n\t:al=\\EE:am:bs:bt=\\EI:\\\n\t:cd=\\EY:ce=\\ET:cl=^Z:cm=\\E=%+ %+ :co#80:ct=\\E3:\\\n\t:dc=\\EW:dl=\\ER:do=^J:ei=:ho=^^:ic=\\EQ:im=:\\\n\t:k0=^A@\\r:k1=^AA\\r:k2=^AB\\r:k3=^AC\\r:kd=^J:kl=^H:kr=^L:ku=^K:\\\n\t:le=^H:li#24:ma=^K^P^L :nd=^L:\\\n\t:se=\\EG0:sg#1:so=\\EG4:st=\\E1:\\\n\t:ue=\\EG0:ug#1:up=^K:us=\\EG8:\n# From ucbvax!mtxinu!sybase!tim (Tim Wood) Fri Sep 27 10:25:24 PDT 1985\n# This entry supports line and character insert and delete, scroll up and\n# down and the arrow keys.  To use it, perform the following on your qvt-101\n#\t1) enter SET-UP mode, select the SET 3 line;\n#\t2) move the cursor to the EMULATION item and hit SPACE\n#\t   until QVT-101B appears\n#\t3) enter SHIFT-S\n#\t4) exit SET-UP - the terminal is now configured\nAq|q101|qvt101|qvt-101|Qume 101 $310 special:\\\n\t:al=\\EE:am:bt=\\EI:ce=\\Et:cl=\\E*:dc=\\EW:\\\n\t:dl=\\ER:do=^J:ic=\\EQ:ei=:im=:md=\\E(:me=\\EG0:mh=\\E):\\\n\t:le=^H:bs:cm=\\E=%+ %+ :cl=1^Z:co#80:ho=^^:li#24:ma=^K^P:nd=^L:ku=^K:\\\n\t:vs=\\EM4\\040\\200\\200\\200:mr=\\EG4:ms:so=\\EG4:se=\\EG1:\n# I suspect the xerox1720 is the same as the diablo 1620.\nAx|x1720|x1700|1700|x1750|xerox 1720:\\\n\t:co#132:le=^H:bs:hc:os:pt:do=^J:ct=\\E2:st=\\E1:\n# \f# --------------------------------\n#\n# B: AT&T ATT\n#\n# AT&T Teletype 5410 Terminal (a.k.a. 4410)\n# From: carvalho%kepler@Berkeley.EDU (Marcio de Carvalho)\n# Date: Thu, 26 Feb 87 09:16:50 PST\n#\n# Although the 5410 supports labels, it blanks the screen after\n# each label is programmed creating to much visual activity.\n# To use the labels, use FL=\\E[%d;00q%-16s\n#\nBa|5410|4410|tty5410|att4410|AT&T Teletype 5410 terminal with 80 columns:\\\n\t:al=\\E[L:am:bs:cd=\\E[J:ce=\\E[K:cl=\\E[H\\E[J:\\\n\t:cm=5\\E[%i%2;%2H:co#80:dc=\\E[P:dl=\\E[M:im=:ei=:ic=\\E[@:\\\n\t:kd=\\E[B:kh=\\E[H:kl=\\E[D:kr=\\E[C:ku=\\E[A:\\\n\t:li#24:nd=\\E[C:se=\\E[m:so=\\E[2;7m:sr=\\EM:\\\n\t:ue=\\E[m:up=\\E[A:us=\\E[4m:EE=\\E[m:BO=\\E[0;7m:DS=\\E[2m:\\\n\t:KM=/usr/share/ua/kmap.5410:is=\\E[0m^O\\E[?6l:kn#8:\\\n\t:k1=\\EOc:k2=\\EOd:k3=\\EOe:k4=\\EOf:k4=\\EOg:k6=\\EOh:\\\n\t:k7=\\EOi:k8=\\EOj:ko=nd,up,ho:\n# AT&T Teletype 5420 Terminal (a.k.a. 4415) June 5, 1985\nBb|5420|4415|tty5420|att4415|AT&T Teletype 5420 terminal:\\\n\t:al=\\E[L:am:bs:cd=\\E[J:ce=\\E[K:cl=\\E[H\\E[J:\\\n\t:cm=\\E[%i%2;%2H:co#80:dc=\\E[P:dl=\\E[M:im=\\E[4h:ei=\\E[4l:\\\n\t:kd=\\E[B:kh=\\E[H:kl=\\E[D:kr=\\E[C:ku=\\E[A:\\\n\t:li#24:nd=\\E[C:se=\\E[m:so=\\E[2;7m:sr=\\EM:\\\n\t:ue=\\E[m:up=\\E[A:us=\\E[4m:EE=\\E[m:BO=\\E[0;7m:DS=\\E[2m:\\\n\t:KM=/usr/share/ua/kmap.5420:\\\n\t:is=\\E[0m^O\\E[1;2;3;4;6l\\E[12;13;14;20l\\E[?6;97;99l\\E[?7h\\E[4i\\Ex\\E[25;1j\\212\\E[8;0j\\E[9;0j\\E[10;0j\\E[19;1j:\\\n\t:db:mi:pt:kn#8:k1=\\EOc:k2=\\EOd:k3=\\EOe:k4=\\EOf:k5=\\EOg:k6=\\EOh:\\\n\t:k7=\\EOi:k8=\\EOj:ve=\\E[11;0j:\\\n\t:vs=\\E[11;1j:ko=bt,nd,up,dc,dl,ho,im,al:\n# AT&T Teletype 5425 Terminal (a.k.a 4425) June 5, 1985\nBc|5425|4425|tty5425|att4425|AT&T Teletype 5425:\\\n\t:FL=\\E[%d;00q%-16s\\E~:FE=\\E|:KM=/usr/share/ua/kmap.5425:\\\n\t:is=\\E[0m^O\\E[1;2;3;4;6l\\E[12;13;14;20l\\E[?6l\\E[?7h\\E[4i\\E[9;0j\\E[10;0j\\E[11;0j\\E[21;1j\\E[25;1j\\212:\\\n\t:ve=\\E[12;0j:vs=\\E[12;1j:tc=5420:\nBd|t4|4420|tty4420|Teletype 4420:\\\n\t:vs=\\ER:ve=\\ER:am:da:db:mi:cr=\\EG:\\\n\t:im=:ei=:dm=:ed=:nl=\\EG\\EB:li#23:\\\n\t:co#80:cl=\\EH\\EJ:cd=\\EJ:cm=\\EY%+ %+ :\\\n\t:bs:up=\\E7:do=\\EB:nd=\\EC:al=\\EL:\\\n\t:dl=\\EM:dc=\\EP:ic=\\E\\136:sf=\\EH\\EM\\EY5 :sr=\\ET:kb=^H:\nBe|pc6300plus|6300|6300plus:\\\n\t:al=\\E[1L:am:bs:cd=\\E[0J:ce=\\E[0K:cl=\\E[2J\\E[H:cm=\\E[%i%2;%2H:co#80:\\\n\t:dc=\\E[1P:dl=\\E[1M:do=\\E[B:ei=:ho=\\E[H:\\\n\t:ic=\\E[1@:im=:kb=\\10:kd=\\E[B:kl=\\E[D:kr=\\E[C:ku=\\E[A:li#24:\\\n\t:k1=\\EOc:k2=\\EOd:k3=\\EOe:k4=\\EOf:k5=\\EOg:k6=\\EOh:k7=\\EOi:k8=\\EOj:\\\n\t:k9=\\EOk:k10=\\EOu:nd=\\E[C:se=\\E[m:so=\\E[7m:ue=\\E[m:up=\\E[A:us=\\E[4m:\\\n\t:EE=\\E[m:BO=\\E[0;7m:CV=\\E[=C:CI=\\E[=1C:KM=/usr/share/ua/kmap.s5:\nBf|s4|PC7300|unixpc|pc7300|7300|3b1|Safari 4:\\\n\t:so=\\E[2;7m:DS=\\E[2m:XS=\\E[9m:KM=/usr/share/ua/kmap.s4:tc=pc6300plus:\n# AT&T Teletype 610 Terminal\nBg|b610|610|610bct|tty610:\\\n\t:CV=\\E[25h:CI=\\E[25l:KM=/usr/share/ua/kmap.s4:\\\n\t:FL=\\E[%d;00q%-16s\\E[0p:FE=\\E[2p:cl=\\E[1;1H\\E[J:\\\n\t:is=\\E[0m^O\\E[25;1|^J\\E[8;0|\\E[4;13;20l\\E[?5l\\E[12h\\E[?7h\\E[?4i:\\\n\t:ve=\\E[?12l:vs=\\E[?12h:tc=5420:\n# \f# --------------------------------\n#\n# C: CONTROL DATA\n#\nCa|cdc456|cdc:\\\n\t:do=^J:li#24:co#80:cl=^Y^X:nd=^L:up=^Z:le=^H:bs:\\\n\t:cm=\\E1%+ %+ :ho=^Y:al=\\E\\114:dl=\\E\\112:ce=^V:cd=^X:am:\nCc|cdc456tst:\\\n\t:do=^J:li#24:co#80:cl=^y^x:le=^H:bs:cm=\\E1%+ %+ :am:\n# \f# --------------------------------\n#\n# D: DATAMEDIA\n#\nD0|dm1520|dm1521|1521|1520|datamedia 1520:\\\n\t:do=^J:am:le=^H:bs:cd=^K:ce=^]:cl=^L:cm=^^%r%+ %+ :co#80:ho=^Y:\\\n\t:ku=^_:kd=^J:kl=^H:kr=^\\:kh=^Y:\\\n\t:li#24:nd=^\\:up=^_:xn:ma=^\\ ^_^P^YH:pt:\nD2|dm2500|datamedia2500|2500|datamedia 2500:\\\n\t:do=^J:al=15^P\\n^X^]^X^]:le=^H:bs:ce=^W:cl=^^^^\\177:\\\n\t:cm=^L%r%n%.%.:co#80:dc=10*^P\\b^X^]:dl=10*^P^Z^X^]:\\\n\t:dm=^P:ed=^X^]:ei=10\\377\\377^X^]:ho=^B:ic=10*^P^\\^X^]:\\\n\t:im=^P:li#24:nc:nd=^\\:pc=\\377:so@=^N:se=^X^]:up=^Z:\nD3|dm3025|datamedia 3025a:\\\n\t:MT:is=\\EQ\\EU\\EV:do=^J:\\\n\t:al=130\\EP\\n\\EQ:le=^H:bs:cd=2\\EJ:ce=\\EK:cl=2\\EM:cm=\\EY%r%+ %+ :\\\n\t:co#80:dc=6\\b:dl=130\\EP\\EA\\EQ:dm=\\EP:ed=\\EQ:ei=\\EQ:ho=\\EH:\\\n\t:im=\\EP:ip=6:li#24:nd=\\EC:pt:so=\\EO1:se=\\EO0:up=\\EA:\nD4|3045|dm3045|datamedia 3045a:\\\n\t:is=\\EU\\EV:do=^J:\\\n\t:am:le=^H:bs:cd=2\\EJ:ce=\\EK:cl=2\\EM:cm=\\EY%r%+ %+ :co#80:\\\n\t:dc=6\\EB:dm=:ed=:ei=\\EP:ho=\\EH:ic=:im=\\EP:ip=6:\\\n\t:k0=\\Ey\\r:k1=\\Ep\\r:k2=\\Eq\\r:k3=\\Er\\r:k4=\\Es\\r:\\\n\t:k5=\\Et\\r:k6=\\Eu\\r:k7=\\Ev\\r:k8=\\Ew\\r:k9=\\Ex\\r:\\\n\t:kh=\\EH:ku=\\EA:kr=\\EC:li#24:nd=\\EC:pc=\\177:pt:eo:ul:up=\\EA:xn:\n# dt80/1 is a vt100 lookalike, but it doesn't seem to need any padding.\nD5|dt80|dmdt80|dm80|datamedia dt80/1:\\\n\t:do=^J:cd=\\E[J:ce=\\E[K:cl=\\E[2J\\E[H:cm=%i\\E[%d;%dH:ho=\\E[H:\\\n\t:nd=\\E[C:sr=\\EM:so=\\E[7m:se=\\E[m:up=\\E[A:us=\\E[4m:ue=\\E[m:tc=vt100:\n# except in 132 column mode, where it needs a little padding.\n# This is still less padding than the vt100, and you can always turn on\n# the ^S/^Q handshaking, so you can use vt100 flavors for things like\n# reverse video.\nD6|dt80w|dmdt80w|dm80w|datamedia dt80/1 in 132 char mode:\\\n\t:do=^J:cd=20\\E[0J:co#132:ce=20\\E[0K:\\\n\t:cm=5\\E[%i%d;%dH:cl=50\\E[H\\E[2J:up=5\\E[A:tc=dmdt80:\n# \f# --------------------------------\n#\n# H: HAZELTINE\n#\n# Since nd is blank, when you want to erase something you\n# are out of luck.  You will have to do ^L's a lot to\n# redraw the screen.  h1000 is untested.  It doesn't work in\n# vi - this terminal is too dumb for even vi.  (The code is\n# there but it isn't debugged for this case.)\nH1|h1000|hazeltine 1000:\\\n\t:le=^H:bs:ho=^K:cl=^L:nd= :co#80:li#12:do=^J:\n# Note: the h1552 appears to be the first Hazeltine terminal which\n# is not braindamaged.  It has tildes and backprimes and everything!\n# Be sure the auto lf/cr switch is set to cr.\nH2|h1552|hazeltine 1552:\\\n\t:do=^J:al=\\EE:dl=\\EO:k1=\\EP:l1=blue:k2=\\EQ:\\\n\t:l2=red:k3=\\ER:l3=green:tc=vt52:\nH3|h1552rv|hazeltine 1552 reverse video:\\\n\t:do=^J:so=\\ES:se=\\ET:tc=h1552:\n# From cbosg!ucbvax!pur-ee!cincy!chris Thu Aug 20 09:09:18 1981\nH4|h1420|hazeltine 1420:\\\n\t:do=^J:le=^H:bs:am:li#24:co#80:al=\\E^Z:dl=\\E^S:cd=\\E^X:cl=\\E\\034:\\\n\t:up=\\E^L:nd=^P:ce=\\E^O:ta=^N:cm=\\E^Q%r%.%+ :so=\\E\\037:se=\\E^Y:\nH5|h1500|hazeltine 1500:\\\n\t:do=^J:al=40~^Z:am:le=^H:bs:cd=10~^X:ce=~^O:cl=~^\\:cm=~^Q%r%.%.:\\\n\t:co#80:dl=40~^S:do=~^K:hz:li#24:nd=^P:.se=~^_:.so=~^Y:up=~^L:\n# h1510 assumed to be in sane escape mode.  Else use h1500.\nH6|h1510|hazeltine 1510:\\\n\t:do=^J:al=\\E^Z:am:le=^H:bs:cd=\\E^X:ce=\\E^O:cl=\\E^\\:cm=\\E^Q%r%.%.:\\\n\t:co#80:dl=\\E^S:do=\\E^K:hz:li#24:nd=^P:.se=\\E^_:.so=\\E^Y:up=\\E^L:\nH8|h1520|hazeltine 1520:\\\n\t:do=^J:al=~^Z:am:le=^H:bs:cd=~^X:ce=~^O:cl=~\\034:cm=~^Q%r%.%.\\200:\\\n\t:co#80:dl=~^S:do=~^K:hz:li#24:nd=^P:se=~^Y:so=~\\037:up=~^L:ho=~^R:\n# Note: h2000 won't work well because of a clash between upper case and ~'s.\nH7|h2000|hazeltine 2000:\\\n\t:do=^J:al=6~^z:am:le=^H:bs:cl=6~^\\:cm=~^q%r%.%.:co#74:\\\n\t:dl=6~^s:ho=~^r:li#27:nc:pc=\\177:\n# Hazeltine esprit entries from Univ of Utah  Tue Feb  1 06:39:37 1983\n# J.Lepreau, lepreau@utah-cs, harpo!utah-cs!lepreau\nHE|esprit|hazeltine esprit:\\\n\t:al=40\\E^Z:bs:cd=5\\E^X:ce=\\E^O:cl=\\E^\\:cm=\\E^Q%r%>^^ %+`%+`:co#80:\\\n\t:dl=40\\E^S:do=\\E^K:ho=\\E^R:li#24:nd=^P:se=\\E^Y:so=\\E^_:up=\\E^L:\nHF|esprit-am|hazeltine esprit auto-margin:\\\n\t:am:tc=esprit:\n# \f# --------------------------------\n#\n# I: IBM\n#\n# ibm61 and ibm63 from Warren Gish (cswarren@violet.berkeley.edu).\n# installed 12-17-86.\n# 3161 only opens a new line if a null line exists on the screen.\n# To ensure a null line exists, an SBA is performed, positioning the\n# Buffer Address in column 0 of the last line.  The last line is then\n# cleared to nulls, BA mode is cancelled, and the new line is opened\n# at the cursor position.\nI1|ibm61|ibm3161|3161|IBM 3161-11:\\\n\t:am:bs:bw:cl=\\EL:li#24:co#80:cd=\\EJ:al=\\EX7 \\EI\\E Z\\EN:\\\n\t:ce=\\EI:cm=\\EY%+\\040%+\\040:nd=\\EC:up=\\EA:do=\\EB:\\\n\t:dl=\\EO:dc=\\EQ:kd=\\EB:ku=\\EA:kl=\\ED:kr=\\EC:kh=\\EH:\\\n\t:us=\\E4\\102:ue=\\E4\\100:so=\\E4\\110:se=\\E4\\100:\nI3|ibm63|ibm3163|3163|i3163|IBM 3163:\\\n\t:tc=ibm61:\nI4|ibm|ibm3101|3101|i3101|IBM 3101-10:\\\n\t:do=^J:ct=\\EH:st=\\E0:\\\n\t:if=/usr/share/tabset/ibm3101:\\\n\t:am:le=^H:bs:cl=\\EK:li#24:co#80:nd=\\EC:up=\\EA:cd=\\EJ:ce=\\EI:\\\n\t:kd=\\EB:kl=\\ED:kr=\\EC:ku=\\EA:ho=\\EH:cm=\\EY%+\\40%+\\40:pt:\nIa|ibm-apl|apl|IBM apl terminal simulator:\\\n\t:li#25:tc=dm1520:\n# ibmapa* and ibmmono entries come from ACIS 4.3 distribution\nIb|rtpc|ibmapa16|ibm6155|IBM 6155 Extended Monochrome Graphics Display:\\\n\t:ts=\\Ej\\EY@%+ \\Eo:ds=\\Ej\\EY@\\40\\EI\\Ek:li#32:tc=ibmconsole:\n# Advanced Monochrome (6153) and Color (6154) Graphics Display:\nIc|ibmapa8c|ibmapa8|ibm6154|ibm6153|IBM 6153/4 Advanced Graphics Display:\\\n\t:ts=\\Ej\\EY?%+ \\Eo:ds=\\Ej\\EY?\\40\\EI\\Ek:li#31:tc=ibmconsole:\nId|ibmapa8c-c|ibm6154-c|IBM 6154 Advanced Color Graphics Display color termcap:\\\n\t:ts=\\Ej\\EY?%+ \\Eo:ds=\\Ej\\EY?\\40\\EI\\Ek:li#31:mh=\\EF\\Ef7;:tc=ibmega-c:\nIe|ibmmono|ibmconsole|ibm5151|IBM workstation monochrome:\\\n\t:se=\\Ez:so=\\EZ:sr=\\EA:al=\\EL:dl=\\EM:\\\n\t:kb=^H:us=\\EW:ue=\\Ew:\\\n\t:k1=\\ES:k2=\\ET:k3=\\EU:k4=\\EV:k5=\\EW:k6=\\EP:k7=\\EQ:k8=\\ER:k9=\\EY:\\\n\t:k0=\\E<:I0=f10:kI=\\000:kh=\\EH:kR=\\EG:kP=\\Eg:kF=\\EE:kN=\\EE:\\\n\t:md=\\EZ:me=\\Ew\\Eq\\Ez\\EB:mk=\\EF\\Ef0;\\Eb0;:mr=\\Ep:\\\n\t:ts=\\Ej\\EY8%+ \\Eo:fs=\\Ek:ds=\\Ej\\EY8\\40\\EI\\Ek:es:hs:sb:tc=ibm3101:\nIf|ibmega-c|ibm5154-c|IBM Enhanced Color Display color termcap:\\\n\t:se=\\EB:so=\\EF\\Ef3;:ue=\\EB:us=\\EF\\Ef2;:tc=ibmconsole:\n# \f# --------------------------------\n#\n# M: MISCELLANEOUS TERMINALS\n#\n# The tab 132 uses xon/xoff, so no padding needed.\n# ks/ke have nothing to do with arrow keys.\n# is sets 80 col mode, normal video, autowrap on (for am).\n# Seems to be no way to get rid of status line.\nM0|abm80|amtek business machines 80:\\\n\t:do=^J:al=\\E^Z:am:le=^H:bs:cd=\\E^X:ce=\\E^O:cl=\\E^\\:cm=\\E^Q%r%+ %+ :\\\n\t:co#80:dl=\\E^S:do=\\E^K:li#24:nd=^P:.so=\\E^_:.se=\\E^Y:up=\\E^L:\\\n\t:bw:bt=^T:ho=\\E^R:\nM1|tab132|tab|tab132/15|tab 132/15:\\\n\t:is=\\E[?7h\\E[?3l\\E[?5l:dN@:ks@:ke@:do=^J:\\\n\t:da:db:al=\\E[L:dl=\\E[M:dc=\\E[P:ei=\\E[4l:im=\\E[4h:cm=\\E[%i%d;%dH:\\\n\t:ku=\\E[A:kd=\\E[B:kl=\\E[D:tc=vt100:\nM2|tab132w:\\\n\t:co#132:is=\\E[?7h\\E[?3h\\E[?5l:tc=tab132:\nM3|tab132rv:\\\n\t:is=\\E[?7h\\E[?3l\\E[?5h:tc=tab132:\nM4|tab132wrv:\\\n\t:is=\\E[?7h\\E[?3h\\E[?5h:tc=tab132w:\n# This used to say \"de#001202\" which presumably refers to the stty bits\n# that need to be set for some version of Unix.  We need the real delay\n# requirements in MS.\nM5|mw2|Multiwriter 2:\\\n\t:do=^J:co#132:hc:os:\nM6|trs80|trs-80|radio shack trs-80 Model I:\\\n\t:do=^J:am:le=^H:bs:co#64:li#16:\nM7|d800|Direct 800/A:\\\n\t:do=^J:co#80:li#24:am:cl=\\E[1;1H\\E[2J:le=^H:bs:cm=\\E[%i%d;%dH:\\\n\t:nd=\\E[C:up=\\E[A:ce=\\E[K:cd=\\E[J:\\\n\t:so=\\E[7m:se=\\E[0m:us=\\E[4m:ue=\\E[0m:xs:vs=\\E[>12l:ve=\\E[>12h:\\\n\t:sf=\\ED:sr=\\EM:da:db:as=\\E[1m:ae=\\E[0m:ms:pt:\\\n\t:kl=\\E[D:kr=\\E[C:ku=\\E[A:kd=\\E[B:\\\n\t:k1=\\EOP:k2=\\EOQ:k3=\\EOR:k4=\\EOS:\\\n\t:k5=\\EOT:k6=\\EOU:k7=\\EOV:k8=\\EOW:\nM8|vc404|volker-craig 404:\\\n\t:do=^J:am:le=^H:bs:cd=40^W:ce=20^V:cl=40^X:cm=^P%+ %+ :co#80:\\\n\t:ho=40^Y:kd=^J:kl=^H:kr=^U:ku=^Z:li#24:ma=^Z^P^U :nd=^U:up=^Z:\nM9|vc404-s|volker-craig 404 w/standout mode:\\\n\t:do=^J:se=^O:so=^N:tc=vc404:\nMA|vc404-na|volker-craig 404 w/no arrow keys:\\\n\t:ma@:kr@:ku@:tc=vc404:\nMB|vc404-s-na|volker-craig 404 w/standout mode and no arrow keys:\\\n\t:se=^O:so=^N:tc=vc404-na:\n# missing in vc303a and vc303 descriptions:  they scroll 2 lines at a time\nMC|vc303a|vc403a|volker-craig 303a:\\\n\t:do=^J:am:le=^H:bs:ce=20^V:cl=40^X:co#80:ho=40^Y:kd=^J:kl=^H::kr=^U:\\\n\t:ku=^Z:li#24:ll=^P^@W:nd=^U:ns:up=^Z:\nMD|vc303|vc103|vc203|volker-craig 303:\\\n\t:do=^J:am:le=^H:bs:cl=40^L:co#80:ho=40^K:kd=^J:kl=^H:\\\n\t:kr=^I:ku=^N:li#24:ll=^O\\200W:nd=^I:ns:up=^N:\n# Test version for Falco ts-1. See \"arpavax.hickman@ucb\" for info\nME|falco|ts1|ts-1|falco ts-1:is=\\Eu\\E3:\\\n\t:do=^J:al=\\EE:am:bs:ce=\\ET\\EG0^h:cm=\\E=%+ %+ :cl=\\E*:cd=\\EY:co#80:\\\n\t:dc=\\EW:dl=\\ER:ei=\\Er:ho=^^:im=\\Eq:k0=^A0\\r:kd=^J:kl=^H:pt:\\\n\t:kr=^L:ku=^K:li#24:nd=^L:se=\\Eg0:so=\\Eg1:up=^K:us=\\Eg1:ue=\\Eg0:\nMF|falco-p|falco ts-1sp|falco with paging option:\\\n\t:is=\\EZ\\E3\\E_c:\\\n\t:al=\\EE:am:bs:ce=\\ET\\EG0^H\\Eg0:cl=\\E*:cd=\\EY:co#80:dc=\\EW:\\\n\t:dl=\\ER:kd=\\E[B:kl=\\E[D:ei=\\Er:im=\\Eq:pt:db:\\\n\t:kr=\\E[C:ku=\\E[A:li#24:nd=\\E[C:se=\\Eg0:so=\\Eg4:\\\n\t:up=\\E[A:us=\\Eg1:ti=\\E_d:te=\\E_b:\\\n\t:ue=\\Eg0:do=\\E[B:cm=\\E=%+ %+ :ms:kh=\\E[H:da:mi:bt=\\EI:\n#NOTE: bg can scroll, it just would rather not (ns) - rwells 3/13/81.\n# (Shouldn't you take out ns and put in an nl instead? - mrh)\nMG|bg|bitgraph|BBN BitGraph terminal:\\\n\t:do=^J:al=2*\\E[L:bs:cd=150\\E[J:ce=2\\E[K:\\\n\t:cl=150\\E[H\\E[J:cm=%i\\E[%d;%dH:co#85:\\\n\t:dl=2*\\E[M:k0=\\EP:k1=\\EQ:k2=\\ER:k3=\\ES:kd=\\EB:ke=\\E>:kl=\\ED:kr=\\EC:\\\n\t:ks=\\E=:ku=\\EA:li#64:nd=\\E[C:ns:pt:se=\\E[0m:so=\\E[7m:up=\\E[A:sf=280\\n:\nMH|d132|datagraphix|datagraphix 132a:\\\n\t:do=^J:co#80:li#30:cl=^l:ho=\\Et:da:db:sf=\\Ev:sr=\\Ew:\\\n\t:up=\\Ek:nd=\\El:vs=\\ex:ve=\\Em\\En:\\\n\t:al=\\E3:ic=\\E5:dc=\\E6:in:ic=\\E5:\nMI|soroc|Soroc 120:\\\n\t:do=^J:cd=\\EY:ce=\\ET:cl=2\\E*:ma=^K^P^R^L^L :\\\n\t:kl=^H:ku=^K:kr=^L:kd=^J:tc=adm3a:\n#  From: ma179abu%sdcc3@sdcsvax.ucsd.edu (Bill Houle)\nMI|iq140|soroc140|Soroc IQ140 with inverse & dim:\\\n\t:ic=\\EQ:dc=\\EW:al=\\EE:dl=\\ER:ce=\\ET:cd=\\EY:cl=\\E+:cm=\\E=%+ %+ :\\\n\t:up=^K:do=^J:le=^H:nd=^L:ho=^^:ta=\\Ei:ma=^Kk^Jj^Hh^Ll^^h:am:bs:\\\n\t:co#80:li#24:ei=:im=:kb=^H:kh=^^:ku=^K:kd=^J:kl=^H:kr=^L:\\\n\t:k0=^AI:k1=^A@:k2=^AA:k3=^AB:k4=^AC:k5=^AD:k6=^AE:k7=^AF:\\\n\t:k8=^AG:k9=^AH:se=\\E:so=\\E:us=\\E):ue=\\E(:\n# tec is untested, and taken from CB/Unix virtual terminal driver.\n# Upper case terminal, uses lower case for control sequences!!!\n# The driver shows the C ~ operator used on CM coordinates.\n# Without the terminal in front of me, I can't figure out what's\n# going on, so I've dotted out the cm.  Note there is no ~ in tgoto.\nMJ|tec400|tec scope:\\\n\t:do=^J:.cm=l%r%.%.:up=x:do=h:nd=g:le=w:ho=i:so={:se=|:sg#1:\\\n\t:cl=f:al=e:dl=u:ic=d:dc=t:ce=c:cd=s:\n# From ucbvax!geoff Mon Sep 21 21:15:45 1981\n# This entry has been tested.\nMK|tec500|tec 500:\\\n\t:do=^J:am:le=^H:bs:cm=\\E=%+ %+ :cl=20^Z:\\\n\t:co#80:ho=^^:li#24:nd=^L:up=^K:so=^]:se=^\\:\n# I would appreciate more information on this terminal, such as the\n# manufacturer and the model number.  There are too many tecs in here.\nML|tec:\\\n\t:li#24:co#80:cl=^l:up=^k:nd=\\037:\\\n\t:am:le=^H:bs:ho=\\036:ma=^K^P^_ :do=^J:\nMM|teletec|Teletec Datascreen:\\\n\t:do=^J:am:le=^H:bs:co#80:cl=^l:ho=^^:li#24:nd=^_:up=^k:\n# From cbosg!ucbvax!SRC:george Fri Sep 11 22:38:32 1981\nMN|ampex|d80|dialogue|dialogue80|ampex dialogue 80:\\\n\t:ct=\\E3:st=\\E1:do=^J:is=\\EA:us=\\El:ue=\\Em:\\\n\t:am:le=^H:bs:pt:cl=75\\E*:cm=\\E=%+ %+ :\\\n\t:al=5*\\EE:bt=\\EI:ic=\\EQ:im=:ei=:dl=5*\\ER:dc=\\EW:\\\n\t:ce=\\Et:cd=\\Ey:so=\\Ej:se=\\Ek:li#24:co#80:nd=^L:up=^K:\n#  From: atd!dsd!rcb@ucbvax.berkeley.edu (Richard Bascove)\nA2|a210|210|ampex210|ampex a210:\\\n\t:am:bs:cl=\\E*:cm=\\E=%+ %+ :al=\\EE:bt=\\EI:ic=\\EQ:im=:ei=:\\\n\t:dl=\\ER:dc=\\EW:ho=^^:xn:ce=\\Et:cd=\\Ey:li#24:co#80:nd=^L:up=^K:\\\n\t:pt:if=/usr/share/tabset/std:is=\\EC\\Eu\\E'\\E(\\El\\EA\\E%\\E{\\E.2\\EG0\\Ed\\En:\\\n\t:kl=^H:kr=^L:kd=^V:ku=^K:kh=^^:hs:ts=\\E.0\\Eg\\E}\\Ef:fs=\\E.2:\\\n\t:kn#10:k0=^A0^M:k1=^A1^M:k2=^A2^M:k3=^A3^M:k4=^A4^M:k5=^A5^M:\\\n\t:vb=\\EU\\EX\\EU\\EX\\EU\\EX\\EU\\EX:k6=^A6^M:k7=^A7^M:k8=^A8^M:k9=^A9^M:\\\n\t:so=\\EG4:se=\\EG0:us=\\EG8:ue=\\EG0:ug#1:sg#1:\nMO|digilog|333|digilog 333:\\\n\t:le=^H:bs:co#80:ce=\\030:ho=^n:li#16:nd=^i:up=^o:do=^J:\nMP|ep48|ep4080|execuport 4080:\\\n\t:am:le=^H:bs:os:co#80:hu=\\036:hd=\\034:do=^J:\nMQ|ep40|ep4000|execuport 4000:\\\n\t:am:le=^H:bs:os:co#136:hu=\\036:hd=\\034:do=^J:\nMR|terminet1200|terminet300|tn1200|tn300|terminet|GE terminet 1200:\\\n\t:co#120:hc:os:do=^J:\n# AED 512\n# by giles Billingsley (gilesb%ucbcad@berkeley)\n# rewritten 8/82 for newer AEDs and better operation of vi,etc.\nMS|aed|AED|aed512|AED512|aed 512:\\\n\t:db:co#64:li#40:cl=^L:bs:nd=\\Ei0800\\001:\\\n\t:up=^K:ve=\\E\\E\\E\\E\\E\\E\\E\\072004=000200??\\001:\\\n\t:vb=\\EK0001??0000K0001202080\\001:\\\n\t:us=\\E\\07200>8000140\\001:ue=\\E\\07200>8000100\\001:\\\n\t:uc=\\Ei???>l0800i0102\\001:\\\n\t:ti=\\E\\07200>8000140{<04<0??00001010L<0\\072004=0002??00\\001:\\\n\t:te=\\E\\07200>8000100{804<0??00001000L80\\072004=000200??\\001:\\\n\t:so=\\E\\07200>8000140[80C00\\001:se=\\E[00C80\\001:\\\n\t:is=\\EG1MMM.`40K0001202080K8001????00^L\\EC80L80{80^L\\EK010100????K060\\\n1??0000c818100\\EG1HHH.\\07210000019A27FD006A280D002A200A52429FE852486108611861\\\n2861360N031B4C3F3F1800N041B0C1B4C38301800N001B3B313030301800N011B3B3130303418\\\n00N021B3B313030381800N050800N061B3B313335301800\\07211000015A58E8D5011A58F8D51\\\n11A5908D5211A5918D531160\\07212000015AD5011858EAD5111858FAD52118590AD531185916\\\n0\\0721300004B2071C5858E0A18658E0A0A858EA900858F268FA5278590A50A29018591A9F518\\\n65908590A90165918591A59038E58E8590A591E58F290185912071C5180A0A0A0901858EA9008\\\n58F268F60\\0721350000BA9472031DEA9502031DE60\\E\\E\\E\\EG1MMM.^A:\nzL|aed-ucb|AED-UCB|aed512-ucb|AED512-UCB|aed 512 w/o UCB ROM:\\\n\t:db:co#64:li#40:cl=^L:bs:nd=\\Ei0800\\001:up=^K:\\\n\t:ve=\\E\\E\\E\\E\\E\\E\\E\\072004=000200??\\001:\\\n\t:vb=\\EK0001??0000K0001202080\\001:\\\n\t:us=\\E\\07200>8000140\\001:ue=\\E\\07200>8000100\\001:\\\n\t:uc=\\Ei???>l0800i0102\\001:\\\n\t:ti=\\E\\07200>8000140{<04<0??00001010L<0\\072004=0002??00\\001:\\\n\t:te=\\E\\07200>8000100{804<0??00001000L80\\072004=000200??\\001:\\\n\t:so=\\E\\07200>8000140[80C00\\001:se=\\E[00C80\\001:\\\n\t:if=/usr/share/tabset/aed512:\n# CIT 80  - vt 100 emulator, the termcap has been modified to remove\n#           the delay times and do an auto tab set rather than the indirect\n#           file used in vt100.\nMT|cit80|cit 80|Citoh 80:\\\n\t:co#80:li#24:am:cl=\\E[;H\\EJ:bs:cm=\\E[%i%2;%2H:nd=\\E[C:up=\\E[A:\\\n\t:ce=\\EK:cd=\\EJ:is=\\E>:ks=\\E[?1h\\E=:ke=\\E[?1l\\E>:\\\n\t:ku=\\EOA:kd=\\EOB:kr=\\EOC:kl=\\EOD:\n# From mtxinu!sybase!tim (Tim Wood) Fri Sep 27 09:39:12 PDT 1985\n# Alternate cit101 (vt100 em) file used in vt100.\n#\t    Uses 23 lines so can run citsys (like h19sys).\n#\t24 May 85 (mtxinu!sybase!tim) - removed 2-byte limit on 'cm' cursor\n#\t  coordinates otherwise there is garbling on long lines in \n#\t  co#132 mode; also added support for multipage\tmemory on the Itoh.\nMU|citc|Citoh fast vt100:\\\n\t:co#80:li#23:am:cl=\\E[;H\\E[2J:bs:cm=\\E[%i%d;%dH:nd=\\E[C:up=\\E[A:\\\n\t:ce=\\E[K:cd=\\E[J:so=\\E[7m:se=\\E[m:us=\\E[4m:ue=\\E[m:\\\n\t:is=\\E>\\E[?3l\\E[?4l\\E[?5l\\E[?7h\\E[?8h\\E[3g\\E[>5g:\\\n\t:ks=\\E[?1h\\E=:ke=\\E[?1l\\E>:ku=\\EOA:kd=\\EOB:kr=\\EOC:kl=\\EOD:\\\n\t:vb=\\E[?5h\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\E[?5l:\\\n\t:dc=\\E[P:al=\\E[L:im=:ei=:dl=\\E[M:ic=\\E[@:vs=\\E7\\E[U:ve=\\E[V\\E8:xn:\nMV|cita|:\\\n\t:co#80:li#23:am:cl=\\E[;H\\E[2J:bs:cm=\\E[%i%d;%dH:nd=\\E[C:up=\\E[A:\\\n\t:ce=\\E[K:cd=\\E[J:so=\\E[7m:se=\\E[m:us=\\E[4m:ue=\\E[m:\\\n\t:is=\\E>\\E[?3l\\E[?4l\\E[?5l\\E[?7h\\E[?8h\\E[3g\\E[>5g:\\\n\t:ks=\\E[?1h\\E=:ke=\\E[?1l\\E>:\\\n\t:ku=\\EOA:kd=\\EOB:kr=\\EOC:kl=\\EOD:vs=\\E7\\E[U:ve=\\E[V\\E8:\\\n\t:vb=\\E[?5h\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\E[?5l:xn:\nMW|cit101:li#24:vb@:tc=citc\nMX|cit101b:li#24:tc=citc\nMh|cit500|cit-500|cit 500:\\\n\t:co#80:li#40:cl=50\\E[;H\\E[2J:bs:am:cm=5\\E[%i%2;%2H:nd=2\\E[C:up=2\\E[A:\\\n\t:ce=3\\E[K:cd=50\\E[J:so=2\\E[7m:se=2\\E[m:us=2\\E[4m:ue=2\\E[m:\\\n\t:is=\\E(B\\E)0\\E>\\E[?3l\\E[?7h\\E[?8h:ks=\\E[?1h\\E=:ke=\\E[?1l\\E>:\\\n\t:if=/usr/share/tabset/vt100:ku=\\EOA:kd=\\EOB:kr=\\EOC:kl=\\EOD:\\\n\t:kh=\\E[H:k1=\\EOP:k2=\\EOQ:k3=\\EOR:k4=\\EOS:pt:sr=5\\EM:xn:\\\n\t:do=\\ED:al=\\E[L:dc=\\E[P:dl=\\E[M:\n# Note several versions of blit.  I don't know exactly what is what\n# so please send me any corrections to this -- mrh\n# From research!ikeya!rob Tue Aug 31 23:41 EDT 1982\nMY|blit|jerq|blit-pb|blit running teletype rom:\\\n\t:do=^J:IC=\\Ef%+ :DC=\\Ee%+ :AL=\\EF%+ :DL=\\EE%+ :\\\n\t:mi:dl=\\EE!:ic=\\Ef!:dc=\\Ee!:al=\\EF!:\\\n\t:ce=\\EK:cl=^L:cm=\\EY%r%+ %+ :co#87:li#72:nd=\\EC:\\\n\t:up=\\EA:ku=\\EA:kd=\\EB:kr=\\EC:kl=\\ED:kb=^H:am:ul:pt:eo:\nMZ|cbblit|columbus enhanced tty blit:\\\n\t:vb=\\E^G:so=\\EU!:se=\\EV!:us=\\EU\":ue=\\EV\":cd=\\EJ:\\\n\t:im=\\EQ:ei=\\ER:ic@:co#88:sf=\\EG:tc=blit:\nMa|oblit|ojerq|first version of blit rom:\\\n\t:do=^J:AL=\\Ef%+ :DL=\\Ee%+ :mi:dl=\\EE:ei=\\ER:im=\\EQ:dc=\\EO:da:db:\\\n\t:al=\\EF:cd=\\EJ:ce=\\EK:cl=^L:cm=\\EY%r%+ %+ :co#88:li#72:nd=\\EC:\\\n\t:up=\\EA:vb=\\E^G:am:ul:pt:eo:\nMb|daleblit|daleterm|blit running Dale DeJager's ROM:\\\n\t:ku=\\EA:kd=\\EB:kr=\\EC:kl=\\ED:so=\\EU!:se=\\EV!:us=\\EU\":ue=\\EV\":\\\n\t:da@:db@:tc=oblit:\nMc|datapoint|dp3|dp3360|datapoint 3360:\\\n\t:do=^J:am:le=^H:bs:cd=^_:ce=^^:cl=^]^_:co#82:ho=^]:li#25:nd=^x:up=^z:\n#From: cbosgd!utcs!romwa@ucbvax.berkeley.edu (mark dornfeld)\n#\t\tThis termcap is for the LANPAR Technologies VISION 3220\n#\tterminal.  The function key definitions k0-k5 represent the\n#\tedit keypad: FIND, INSERT HERE, REMOVE, SELECT, PREV SCREEN,\n#\tNEXT SCREEN. The key definitions k6-k9 represent the PF1 to\n#\tPF4 keys.\nv0|v3220|LANPAR Vision II model 3220/3221/3222:\\\n\t:co#80:li#24:cl=\\E[H\\E[J:bs:am:cm=\\E[%i%d;%dH:nd=\\E[C:up=\\E[A:\\\n\t:ce=\\E[K:cd=\\E[J:so=\\E[7m:se=\\E[m:us=\\E[4m:ue=\\E[m:\\\n\t:is=\\E>\\E[?3l\\E[?7h\\E[?8h\\E[p:ks=\\E=:ke=\\E>:\\\n\t:kn#10:k0=\\E[1~:k1=\\E[2~:k2=\\E[3~:k3=\\E[4~:k4=\\E[5~:k5=\\E[6~:\\\n\t:k6=\\E[OP:k7=\\E[OQ:k8=\\E[OR:k9=\\E[OS:\\\n\t:ku=\\E[A:kd=\\E[B:kr=\\E[C:kl=\\E[D:\\\n\t:kh=\\E[H:pt:sr=\\EM:xn:\\\n\t:dl=\\E[M:dc=\\E[P:ei=\\E[4l:al=\\E[L:im=\\E[4h:mi:\n# From ucbvax!faletti (Faletti@Berkeley)\n# FREEDOM 100 by Liberty Electronics USA, SF.\n# :kh=^^:  left out because it precludes using change-to-alternate-file in vi.\n# Basic Freedom 100 entry, works with VI at 1200 baud.\nMd|f100|freedom100|freedom|freedom 100 no padding:\\\n\t:am:bs:bw:mi:ms:pt:co#80:kn#20:li#24:\\\n\t:ct=\\E3:st=\\E1:is=\\Eg\\Ef\\r\\Ed:kr=^L:\\\n\t:cl=^Z:do=^J:ho=^^:kb=^H:kl=^H:\\:kd=^V:\\\n\t:ko=dc,al,dl,cl,bt,ce,cd:ku=^K:le=^H:nd=^L:\\\n\t:ch=\\E]%+ :cm=\\E=%+ %+ :cv=\\E[%+ :sr=\\Ej:up=^K:\\\n\t:al=\\EE:bt=\\EI:cd=\\EY:ce=\\ET:dc=\\EW:dl=\\ER:ei=\\Er:im=\\Eq:\\\n\t:se=\\EG0:so=\\EG4:ue=\\EG0:us=\\EG8:as=\\E$:ae=\\E%:\\\n\t:vb=\\Eb\\200\\200\\Ed:\\\n\t:k1=^A@\\r:k2=^AA\\r:k3=^AB\\r:k4=^AC\\r:k5=^AD\\r:\\\n\t:k6=^AE\\r:k7=^AF\\r:k8=^AG\\r:k9=^AH\\r:k0=^AI\\r:\\\n\t:hs:ts=\\Eg\\Ef:fs=\\r:ds=\\Eg\\Ef\\r:\nMe|f100-rv|freedom100-rv|freedom-rv|freedom100 with reverse video at 1200:\\\n\t:is=\\Eg\\Ef\\r\\Eb:vb=\\Ed\\200\\200\\Eb:tc=freedom100:\n# VI at 9600 baud (or EMACS at 1200 -- but may be more than is needed for emacs)\nMf|f100-v|freedom100-v|freedom-v|freedom100 for 9600 vi or 1200 emacs:\\\n\t:al=6.5*\\EE:dl=11.5*\\ER:\\\n\t:vb=\\Eb\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\Ed:\\\n\t:tc=freedom100:\nMx|f100-v-rv|freedom100-v-rv|freedom-v-rv|freedom100 rev. vid. for 9600 vi:\\\n\t:al=6.5*\\EE:dl=11.5*\\ER:is=\\Eg\\Ef\\r\\Eb:\\\n\t:vb=\\Ed\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\Eb:\\\n\t:tc=freedom100:\n# EMACS at 9600 baud -- this still needs some more work on the padding\nMy|f100-e|freedom100-e|freedom-e|freedom100 for 9600 emacs:\\\n\t:al=8.5*\\EE:dl=11.5*\\ER:ip=6:\\\n\t:vb=\\Eb\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\Ed:\\\n\t:tc=freedom100:\nMz|f100-e-rv|freedom100-e-rv|freedom-e-rv|freedom100 rev. vid. for emacs 9600:\\\n\t:al=8.5*\\EE:dl=11.5*\\ER:ip=6:is=\\Eg\\Ef\\r\\Eb:\\\n\t:vb=\\Ed\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\Eb:\\\n\t:tc=freedom100:\nzM|f110-v|freedom110-v|freedom110 for 9600 vi or 1200 emacs:\\\n\t:is=\\Eg\\Ef\\r\\Ed\\EO:dc=\\EO\\EW:im=\\EO\\Eq:\\\n\t:al=6.5*\\EE:dl=11.5*\\ER:\\\n\t:vb=\\Eb\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\Ed:\\\n\t:tc=freedom100:\n# (from kerch@lll-crg)\nQ1|f200|freedom200| Freedom 200 VDT by Liberty Electronics :\\\n\t:if=/usr/share/tabset/stdcrt:al=\\EE:am:bs:bt=\\EI:cd=\\EY:\\\n\t:ce=\\ET:cl=^Z:cm=\\E=%+ %+ :co#80:dc=\\EW:dl=\\ER:do=^V:\\\n\t:ds=\\Eh:ei=\\Er:im=\\Eq:is=\\Eg\\El\\E\\041\\062:\\\n\t:k1=^A@\\r:k2=^AA\\r:k3=^AB\\r:k4=^AC\\r:k5=^AD\\r:\\\n\t:k6=^AE\\r:k7=^AE\\r:k8=^AF\\r:k9=^AG\\r:kd=^V:kr=L:\\\n\t:ku=^K:li#24:ms:nd=^L:se=\\EG0:so=\\EG4:sr=\\Ej:\\\n\t:te=\\EJ\\E\\\\2\\E|\\041\\061^L^Y:ti=\\E\\\\1\\EK\\E|\\041\\061L^Y:\\\n\t:ts=\\Ef:ue=\\EG0:up=^K:us=\\EG8:vb=\\Eb\\Ed:hs:i2=\\E^O\\Eg:\\\n\t:ts=\\Ef:fs=^M:ds=\\E^N:\nMg|dg|dg6053|data general 6053:\\\n\t:do=^J:am:le=^H:bs:cm=^P%r%.%.:cl=^L:ho=^H:nd=^S:\\\n\t:up=^W:ce=^K:co#80:li#24:\n# dg450 and dg200 from cornell\nMj|dg450|dg6134|data general 6134:\\\n\t:nd=\\030:bs@:tc=dg200:\nMk|dg200|data general Dasher 200:\\\n\t:am:bc=^Y:bs=0:ce=^K:cl=^L:cm=^P%r%+\\200%+\\200:co#80:do=^Z:\\\n\t:ho=^H:li#24:\\\n\t:ll=\\036FP0017:se=\\036E:so=\\036D:up=^W:\\\n\t:is=\\036O\\036FQ2\\036FB000\\036FE\\036FA\\036FQ2:\n# Note: lesser Dasher terminals will not work with vi because vi insists upon\n# having a command to move straight down from any position on the bottom line\n# and scroll the screen up, or a direct vertical scroll command.  The 460 and\n# above have both, the D210/211, for instance, has neither.  We must use ANSI\n# mode rather than DG mode because standard UNIX tty drivers assume that ^H is\n# backspace on all terminals.  This is not so in DG mode.\nzF|dg460-ansi|Data General Dasher 460, ANSI-mode:\\\n\t:al=\\E[L:am:bs:cd=\\E[J:ce=\\E[K:cl=\\E[2J:\\\n\t:cm=\\E[%i%2;%2H:co#80:dc=\\E[P:dl=\\E[M:do=\\E[B:\\\n\t:ei=:ho=\\E[H:ic=\\E[@:im=:ue=\\E[05:ul:up=\\E[A:us=\\E[4m:is=\\036F@:\\\n\t:k0=\\E[001z:k1=\\E[002z:k2=\\E[003z:k3=\\E[004z:k4=\\E[005z:k5=\\E[006z:\\\n\t:k6=\\E[007z:k7=\\E[008z:k8=\\E[009z:k9=\\E[00\\:z:\\\n\t:kb=\\E[D:kd=\\E[B:kh=\\E[H:kl=\\E[D:kr=\\E[C:ku=\\E[A:kn#6:\\\n\t:l0=f1:l1=f2:l2=f3:l3=f4:l4=f5:l5=f6:l6=f7:l7=f8:l9=f10:\\\n\t:le=^H:li#24:mb=\\E[5m:me=\\E[0m:mh=\\E[2m:mr=\\E[7m:ms:mu=\\EW:\\\n\t:nd=\\E[C:nl=\\ED:pt:se=\\E[0m:sf=\\E[S:so=\\E[7m:sr=\\E[T:\nMi|cdi|cdi1203:\\\n\t:am:le=^H:bs:hc:os:co#80:dC#200:do=^J:\n# ^S is an arrow key!  Boy is this guy in for a surprise on v7!\nMl|sol:\\\n\t:do=^J:am:le=^Y:ho=^H:bs:cm=\\E^1%.\\E^2%.:cl=^K:ho=^N:co#64:li#16:\\\n\t:nd=^S:up=^W:kl=^A:kr=^S:ku=^W:kd=^Z:ma=^A^H^S ^W^P^Z^N:\nMn|xl83|Cybernex XL-83:\\\n\t:do=^J:am:le=^H:bs:cd=62^P:ce=3^O:cl=62^L:cm=^W%+ %+ :co#80:ho=^K:\\\n\t:kd=^J:kl=^H:ku=^N:li#24:up=^N:nd=^I:\nMo|omron|Omron 8025AG:\\\n\t:do=^J:al=\\EL:am:le=^H:bs:cd=\\ER:co#80:ce=\\EK:cl=\\EJ:\\\n\t:da:db:dc=\\EP:dl=\\EM:ho=\\EH:li#24:nd=\\EC:se=\\E4:sf=\\ES:\\\n\t:so=\\Ef:sr=\\ET:up=\\EA:ve=:vs=\\EN:\nMp|plasma|plasma panel:\\\n\t:am:le=^H:bs:cl=^L:co#85:ho=^^:li#45:nd=\\030:up=\\026:do=^J:\nMq|pty|psuedo teletype:\\\n\t:do=^J:co#80:li#24:am:cl=\\EJ:le=^H:bs:cm=\\EG%+ %+ :nd=\\EC:\\\n\t:up=\\EA:ce=\\EK:cd=\\EL:al=\\EP:dl=\\EN:ic=\\EO:\\\n\t:so=\\Ea$:se=\\Eb$:us=\\Ea!:ue=\\Eb!:\nMr|remote|virtual remote terminal:\\\n\t:co#79:am@:nl@:tc=virtual:\nMs|swtp|ct82|southwest technical products ct82:\\\n\t:do=^J:am:le=^d:bc=^d:\\\n\t:al=^\\^y:cd=^v:ce=^F:cl=^L:cm=%r^k%.%.:co#82:li#20:\\\n\t:dl=^z:nd=^s:up=^a:so=^^^v:se=^^^F:dc=^\\^h:ic=^\\^x:ho=^p:\\\n\t:ei=:sf=^n:sr=^o:ll=^c:im=:\\\n\t:is=^\\^r^^^s^^^d^]^w^i^s^^^]^^^o^]^w^r^i:\nMt|terak|Terak emulating Datamedia 1520:\\\n\t:tc=dm1520:\nMu|sun|Sun Microsystems Workstation console:\\\n\t:li#34:co#80:cl=^L:cm=\\E[%i%d;%dH:nd=\\E[C:up=\\E[A:\\\n\t:am:bs:mi:ms:pt:\\\n\t:ce=\\E[K:cd=\\E[J:so=\\E[7m:se=\\E[m:\\\n\t:kd=\\E[B:kl=\\E[D:ku=\\E[A:kr=\\E[C:kh=\\E[H:\\\n\t:k1=\\EOP:k2=\\EOQ:k3=\\EOR:k4=\\EOS:\\\n\t:al=\\E[L:dl=\\E[M:im=:ei=:ic=\\E[@:dc=\\E[P:\\\n\t:AL=\\E[%dL:DL=\\E[%dM:\n# From john@ucbrenoir  Tue Sep 24 13:14:44 1985\nMu|sun-s|Sun Microsystems Workstation window with status line:\\\n\t:hs:ts=\\E]l:fs=\\E\\\\:ds=\\E]l\\E\\\\:tc=sun:\nMu|sun-e-s|sun-s-e|Sun Microsystems Workstation with status hacked for emacs:\\\n\t:hs:ts=\\E]l:fs=\\E\\\\:ds=\\E]l\\E\\\\:tc=sun-e:\nM0|sun-48|Sun 48-line window:\\\n\t:li#48:co#80:tc=sun:\nM1|sun-34|Sun 34-line window:\\\n\t:li#34:co#80:tc=sun:\nM2|sun-24|Sun 24-line window:\\\n\t:li#24:co#80:tc=sun:\nM3|sun-17|Sun 17-line window:\\\n\t:li#17:co#80:tc=sun:\nM4|sun-12|Sun 12-line window:\\\n\t:li#12:co#80:tc=sun:\nM5|sun-1|Sun 1-line window for sysline:\\\n\t:li#1:co#80:es:hs:ts=\\r:fs=\\E[K:ds=^L:tc=sun:\nM6|sun-e|sun-nic|sune|Sun Microsystems Workstation without insert character:\\\n\t:ic@:im@:ei@:tc=sun:\nLS|apollo:\\\n\t:al=\\EI:am:bs:cd=\\EJ:ce=\\EK:ch=\\EN%d:cl=^L:cm=\\EM%+ %d):\\\n\t:cv=\\EO+ :dc=\\EP:dl=\\EL:do=\\EB:ei=\\ER:im=\\EQ:mi:nd=\\EC:se=\\ET:sf=\\EE:\\\n\t:so=\\ES:sr=\\ED:te=\\EX:ti=\\EW:ue=\\EV:up=\\EA:us=\\EU:co#88:li#53:\n# Apollo termcaps from Gary Darland, goodmanc@garnet\nLP|apollo_15P|apollo 15 inch display:\\\n\t:dN@:tc=vt132:\nLQ|apollo_19L|apollo 19 inch display:\\\n\t:dN@:tc=vt132:\nLR|apollo_color|apollo color display:\\\n\t:dN@:tc=vt132:\nMv|virtual|VIRTUAL|cb unix virtual terminal:\\\n\t:do=^J:co#80:li#24:am:cl=\\E\\112:le=^H:bs:cm=\\E\\107%r%.%.:nd=\\E\\103:\\\n\t:up=\\E\\101:ce=\\E\\113:cd=\\E\\114:al=\\E\\120:dl=\\E\\116:im=:ei=:ic=\\E\\117:\\\n\t:da:db:kl=\\E\\104:kr=\\E\\103:ku=\\E\\101:kd=\\E\\102:kh=\\E\\105:\\\n\t:so=\\E\\141\\004:se=\\E\\142\\004:us=\\E\\141\\001:ue=\\E\\142\\001:\nMw|it2|intertube2|intertec data systems intertube 2:\\\n\t:do=^J:am:bs:cl=^L:co#80:ho=^A:li#25:up=^Z:ce=\\EK:\\\n\t:cm=^N%+ %+ :ch=^P%\\102%.:cv=^K%.:nd=^F:do=\\n:ll=^K^X\\r:\\\n\t:so=\\E0P:se=\\E0@:\nMx|delta|dd5000|delta data 5000:\\\n\t:do=^J:am:le=^H:bs:cl=^NR:cm=^O%\\068%+9%\\068%+9:co#80:li#27:\\\n\t:ho=^NQ:nc:nd=^Y:up=^Z:ce=^NU:dc=^NV:ma=^K^J^Z^P^Y :xr:\nMy|mdl110|cybernex mdl-110:\\\n\t:cm=^P%+ %+ :co#80:li#24:am:cl=70^X:le=^H:bs:do=^J:\\\n\t:nd=^U:up=^Z:ho=^Y:ce=145^N@^V:cd=145^NA^W:al=65^NA^N^]:\\\n\t:dl=40^NA^N^^:im=:ei=:ic=3.5^NA^]:dm=:ed=:dc=3.5^NA^^:\\\n\t:so=^NF:se=^NG:ta=43\\t:ma=^Z^P:cd=6^N@^V\nMz|zen30|z30|zentec 30:\\\n\t:do=^J:mi:co#80:li#24:ma=^L ^R^L^K^P:ul:\\\n\t:al=1.5*\\EE:le=^H:bs:ce=1.0*\\ET:cm=\\E=%+ %+ :cl=\\E*:\\\n\t:ho=^^:nd=^L:se=\\EG0:so=\\EG6:up=^K:im=\\Eq:ei=\\Er:\\\n\t:am:dc=\\EW:dl=1.5*\\ER:cd=\\EY:\nm0|modgraph|mod|Modgraph terminal emulating vt100, 24x80:\\\n\t:xn@:rf@:sr=5\\EM\\E[K:vs=\\E\\^9;0s\\E\\^7;1s:\\\n\t:is=\\E\\^9;0s\\E\\^7;1s\\E[3g\\E\\^11;9s\\E\\^11;17s\\E\\^11;25s\\E\\^11;33s\\E\\^11;41s\\E\\^11;49s\\E\\^11;57s\\E\\^11;65s\\E\\^11;73s\\E\\^11;81s\\E\\^11;89s:\\\n\t:tc=vt100:\n# dmchat is like DM2500, but DOES need \"all that padding\" (jcm 1/31/82)\n# also, has a meta-key (MT)\n# from goldberger@su-csli.arpa\nMX|dmchat|dmchat version of datamedia 2500:\\\n\t:al=1*^P\\n^X^]^X^]:\\\n\t:MT:km:\\\n\t:dl=2^P^Z^X^]:\\\n\t:tc=dm2500:\n#from Carol Block at ear (cblock@ear)\n#\nm7|mt70|m70|morrow mt70:\\\n\t:is=EGO\\E\"5:\\\n\t:cl=^Z:\\\n\t:cm=\\E=%+ %+ :\\\n\t:do=^J:\\\n\t:im=:ic=\\EQ:ei:\\\n\t:dm=:dc=\\EW:ed=:\\\n\t:kl=\\034L:kr=\\034M:ku=\\034J:kd=\\034K:\\\n\t:so=\\EG4:se=\\EGO:\\\n\t:us=\\EG1:ue=\\EGO:\\\n\t:vs=\\E\"2:ve=\\E\"5\\E(:\\\n\t:tc=adm31:\n# from keith bostic (bostic@monet)\n#\nm2|mod2|Modgraph GX-1000, set to 80x24, keypad not enabled:\\\n\t:is=\\E<\\E\\^5;2s\\E\\^7;1s\\E[3g\\E\\^11;9s\\E\\^11;17s\\E\\^11;25s\\E\\^11;33s\\E\\^11;41s\\E\\^11;49s\\E\\^11;57s\\E\\^11;65s\\E\\^11;73s\\E\\^11;81s\\E\\^11;89s\\E\\^12;0s\\E\\^14;2s\\E\\^15;9s\\E\\^25;1s\\E\\^9;1s\\E\\^27;1:\\\n\t:bs:cd=50\\EJ:ce=3\\EK:cl=50\\EH\\EJ:cm=5\\EY%+ %+ :co#80:li#24:nd=2\\EC:\\\n\t:pt:sr=5\\EI:up=2\\EA:da:db:am:\nS1|wsiris|iris40|iris emulating a 40 line visual 50 (approximately):\\\n\t:am:al=\\EL:is=\\E7B0\\E7F7\\E7C2\\E7R3:\\\n\t:bs:cd=\\EJ:ce=\\EK:cl=\\EH\\EJ:ho=\\EH:cm=\\EY%+ %+ :co#80:li#40:nd=\\EC:\\\n\t:pt:sr=\\EI:up=\\EA:ku=\\EA:kd=\\EB:kr=\\EC:kl=\\ED:\\\n\t:k0=\\E0:k1=\\E1:k2=\\E2:k3=\\E3:k4=\\E4:k5=\\E5:k6=\\E6:k7=\\E7:k8=\\E8:k9=\\E9:\\\n\t:vs=\\E;:ve=\\E>:cl=\\Ev:ho=\\EH:dl=\\EM:so=\\E9P:se=\\E0@:\\\n\t:HS=\\E7F2:HE=\\E7F7:\\\n\t:us=\\E7R2\\E9P:ue=\\E7R3\\E0@:\\\n\t:CT#2:CZ=*Bblack,red,green,yellow,blue,magenta,cyan,*Fwhite:\n\t\n# \f# --------------------------------\n#\n# N: ANN ARBOR\n#\n# Needs function keys added.\n# Originally from Mike O'Brien@Rand and Howard Katseff at Bell Labs.\n# Highly modified 6/22 by Mike O'Brien.\n# split out into several for the various screen sizes by dave-yost@rand\n# Modifications made 3/82 by Mark Horton\n# Modified by Tom Quarles at UCB for greater efficiency and more diversity\n# status line moved to top of screen, vb removed 5/82\n#\n# assumes the following setup:\n#   A menu: 0000 1010  0001 0000\n#   B menu: 9600  0100 1000  0000 0000  1000 0000  17  19\n#   C menu: 56   66   0    0    9600  0110 1100\n#   D menu: 0110 1001   1   0\n#\n#\tBriefly, the settings are for the following modes:\n#\t   (values are for bit set/clear with * indicating our preference\n#\t    and the value used to test these termcaps)\n#\tNote that many of these settings are irelevent to the termcap\n#\tand are just set to the default mode of the terminal as shipped\n#\tby the factory.\n#\n# A menu: 0000 1010  0001 0000\n#\tBlock/underline cursor*\n#\tblinking/nonblinking cursor*\n#\tkey click/no key click*\n#\tbell/no bell at column 72*\n#\n#\tkey pad is cursor control*/key pad is numeric\n#\treturn and line feed/return for <cr> key *\n#\trepeat after .5 sec*/no repeat\n#\trepeat at 25/15 chars per sec. *\n#\n#\thold data until pause pressed/process data unless pause pressed*\n#\tslow scroll/no slow scroll*\n#\tHold in area/don't hold in area*\n#\tfunctions keys have default*/function keys disabled on powerup\n#\n#\tshow/don't show position of cursor during page transmit*\n#\tunused\n#\tunused\n#\tunused\n#\n# B menu: 9600  0100 1000  0000 0000  1000 0000  17  19\n#\tBaud rate (9600*)\n#\n#\t2 bits of parity - 00=odd,01=even*,10=space,11=mark\n#\t1 stop bit*/2 stop bits\n#\tparity error detection off*/on\n#\n#\tkeyboard local/on line*\n#\thalf/full duplex*\n#\tdisable/do not disable keyboard after data transmission*\n#\n#\ttransmit entire page/stop transmission at cursor*\n#\ttransfer/do not transfer protected characters*\n#\ttransmit all characters/transmit only selected characters*\n#\ttransmit all selected areas/transmit only 1 selected area*\n#\n#\ttransmit/do not transmit line seperators to host*\n#\ttransmit/do not transmit page tab stops tabs to host*\n#\ttransmit/do not transmit column tab stop tabs to host*\n#\ttransmit/do not transmit graphics control (underline,inverse..)*\n#\n#\tenable*/disable auto XON/XOFF control\n#\trequire/do not require receipt of a DC1 from host after each LF*\n#\tpause key acts as a meta key/pause key is pause*\n#\tunused\n#\n#\tunused\n#\tunused\n#\tunused\n#\tunused\n#\n#\tXON character (17*)\n#\tXOFF character (19*)\n#\n# C menu: 56   66   0    0    9600  0110 1100\n#\tnumber of lines to print data on (printer) (56*)\n#\n#\tnumber of lines on a sheet of paper (printer) (66*)\n#\n#\tleft margin (printer) (0*)\n#\n#\tnumber of pad chars on new line to printer (0*)\n#\n#\tprinter baud rate (9600*)\n#\n#\tprinter parity: 00=odd,01=even*,10=space,11=mark\n#\tprinter stop bits: 2*/1\n#\tprint/do not print guarded areas*\n#\n#\tnew line is: 01=LF,10=CR,11=CRLF*\n#\tunused\n#\tunused\n#\n# D menu: 0110 1001   1   0\n#\tLF is newline/LF is down one line, same column*\n#\twrap to preceeding line if move left from col 1*/don't wrap\n#\twrap to next line if move right from col 80*/don't wrap\n#\tbackspace is/is not destructive*\n#\n#\tdisplay*/ignore DEL character\n#\tdisplay will not/will scroll*\n#\tpage/column tab stops*\n#\terase everything*/erase unprotected only\n#\n#\tediting extent: 0=display,1=line*,2=field,3=area\n#\n#\tunused\n#\nNA|aaa-unk|ann arbor ambassador (internal - don't use this directly):\\\n\t:do=^J:al=3\\E[L:am:le=^H:bs:\\\n\t:cd=\\E[J:ce=5\\E[K:cl=156\\E[H\\E[J:cm=\\E[%i%d;%dH:co#80:\\\n\t:dc=4\\E[P:dl=3\\E[M:ho=\\E[H:ic=4\\E[@:\\\n\t:md=\\E[1m:mr=\\E[7m:mb=\\E[5m:mk=\\E[8m:me=\\E[m:\\\n\t:ku=\\EM:kd=\\ED:kl=\\E[D:kr=\\E[C:kh=\\E[H:ko=cl,dc,dl,ce,cd:\\\n\t:ks=\\EP`?z~[H~[[J`>z~[[J`8xz~[M`4xz~[[D`6xz~[[C`2xz~[D\\E\\\\:\\\n\t:ke=\\EP`?y~[H~[[J`>y~[[2J`8xy~[M`4xy~[[D`6xy~[[C`2xy~[D\\E\\\\:\\\n\t:ch=\\E[%i%d`:ei=:im=:pt:bw:bt=\\E[Z:\\\n\t:mi:nd=\\E[C:se=\\E[m:so=\\E[7m:ue=\\E[m:us=\\E[4m:up=\\EM:\nNB|aaa-18|ann arbor ambassador/18 lines:\\\n\t:ti=\\E[2J\\E[18;0;0;18p:te=\\E[60;0;0;18p\\E[18;1H\\E[J:\\\n\t:is=\\EP`+x~M\\E\\\\\\E[m\\E7\\E[60;0;0;18p\\E[3g\\E[f\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E8\\E[>6h\\E[1Q:\\\n\t:li#18:tc=aaa-unk:\nNC|aaa-20|ann arbor ambassador/20 lines:\\\n\t:ti=\\E[2J\\E[20;0;0;20p:te=\\E[60;0;0;20p\\E[20;1H\\E[J:\\\n\t:is=\\EP`+x~M\\E\\\\\\E[m\\E7\\E[60;0;0;20p\\E[3g\\E[f\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E8\\E[>6h\\E[1Q:\\\n\t:li#20:tc=aaa-unk:\nND|aaa-22|ann arbor ambassador/22 lines:\\\n\t:ti=\\E[2J\\E[22;0;0;22p:te=\\E[60;0;0;22p\\E[22;1H\\E[J:\\\n\t:is=\\EP`+x~M\\E\\\\\\E[m\\E7\\E[60;0;0;22p\\E[3g\\E[f\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E8\\E[>6h\\E[1Q:\\\n\t:li#22:tc=aaa-unk:\nNE|aaa-24|ann arbor ambassador/24 lines:\\\n\t:ti=\\E[2J\\E[24;0;0;24p:te=\\E[60;0;0;24p\\E[24;1H\\E[J:\\\n\t:is=\\EP`+x~M\\E\\\\\\E[m\\E7\\E[60;0;0;24p\\E[3g\\E[f\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E8\\E[>6h\\E[1Q:\\\n\t:li#24:tc=aaa-unk:\nNF|aaa-26|ann arbor ambassador/26 lines:\\\n\t:ti=\\E[2J\\E[26;0;0;26p:te=\\E[60;0;0;26p\\E[26;1H\\E[J:\\\n\t:is=\\EP`+x~M\\E\\\\\\E[m\\E7\\E[60;0;0;26p\\E[3g\\E[f\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E8\\E[>6h\\E[1Q:\\\n\t:li#26:tc=aaa-unk:\nNG|aaa-28|ann arbor ambassador/28 lines:\\\n\t:ti=\\E[2J\\E[28;0;0;28p:te=\\E[60;0;0;28p\\E[28;1H\\E[J:\\\n\t:is=\\EP`+x~M\\E\\\\\\E[m\\E7\\E[60;0;0;28p\\E[3g\\E[f\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E8\\E[>6h\\E[1Q:\\\n\t:li#28:tc=aaa-unk:\nNH|aaa|aaa-30|ambas|ambassador|ann arbor ambassador/30 lines:\\\n\t:ti=\\E[2J\\E[30;0;0;30p:te=\\E[60;0;0;30p\\E[30;1H\\E[J:\\\n\t:is=\\EP`+x~M\\E\\\\\\E[m\\E7\\E[60;0;0;30p\\E[3g\\E[f\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E8\\E[>6h\\E[1Q:\\\n\t:li#30:tc=aaa-unk:\nNI|aaa-36|ann arbor ambassador/36 lines:\\\n\t:ti=\\E[2J\\E[36;0;0;36p:te=\\E[60;0;0;36p\\E[36;1H\\E[J:\\\n\t:is=\\EP`+x~M\\E\\\\\\E[m\\E7\\E[60;0;0;36p\\E[3g\\E[f\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E8\\E[>6h\\E[1Q:\\\n\t:li#36:tc=aaa-unk:\nNJ|aaa-40|ann arbor ambassador/40 lines:\\\n\t:ti=\\E[2J\\E[40;0;0;40p:te=\\E[60;0;0;40p\\E[40;1H\\E[J:\\\n\t:is=\\EP`+x~M\\E\\\\\\E[m\\E7\\E[60;0;0;40p\\E[3g\\E[f\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E8\\E[>6h\\E[1Q:\\\n\t:li#40:tc=aaa-unk:\nNK|aaa-48|ann arbor ambassador/48 lines:\\\n\t:ti=\\E[2J\\E[48;0;0;48p:te=\\E[60;0;0;48p\\E[48;1H\\E[J:\\\n\t:is=\\EP`+x~M\\E\\\\\\E[m\\E7\\E[60;0;0;48p\\E[3g\\E[f\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E8\\E[>6h\\E[1Q:\\\n\t:li#48:tc=aaa-unk:\nNL|aaa-60|ann arbor ambassador/60 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lines+sl+rv:\\\n\t:md=\\E[1;7m:mr=\\E[m:mb=\\E[5;7m:mk=\\E[7;8m:me=\\E[7m:\\\n\t:us=\\E[4;7m:ue=\\E[7m:se=\\E[7m:so=\\E[m:\\\n\t:ti=\\E[2J\\E[36;1;0;36p:te=\\E[60;1;0;36p\\E[35;1H\\E[J:li#35:\\\n\t:is=\\EP`+x~M\\E\\\\\\E[7m\\E7\\E[60;1;0;36p\\E[3g\\E[f\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E8\\E[>6h\\E[1Q:\\\n\t:tc=aaa-unk-s:\nNr|aaa-40-rv-s|aaa-40-s-rv|ambassador/40 lines+sl+rv:\\\n\t:md=\\E[1;7m:mr=\\E[m:mb=\\E[5;7m:mk=\\E[7;8m:me=\\E[7m:\\\n\t:us=\\E[4;7m:ue=\\E[7m:se=\\E[7m:so=\\E[m:\\\n\t:ti=\\E[2J\\E[40;1;0;40p:te=\\E[60;1;0;40p\\E[39;1H\\E[J:li#39:\\\n\t:is=\\EP`+x~M\\E\\\\\\E[7m\\E7\\E[60;1;0;40p\\E[3g\\E[f\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E8\\E[>6h\\E[1Q:\\\n\t:tc=aaa-unk-s:\nNs|aaa-48-rv-s|aaa-48-s-rv|ambassador/48 lines+sl+rv:\\\n\t:md=\\E[1;7m:mr=\\E[m:mb=\\E[5;7m:mk=\\E[7;8m:me=\\E[7m:\\\n\t:us=\\E[4;7m:ue=\\E[7m:se=\\E[7m:so=\\E[m:\\\n\t:ti=\\E[2J\\E[48;1;0;48p:te=\\E[60;1;0;48p\\E[47;1H\\E[J:li#47:\\\n\t:is=\\EP`+x~M\\E\\\\\\E[7m\\E7\\E[60;1;0;48p\\E[3g\\E[f\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E8\\E[>6h\\E[1Q:\\\n\t:tc=aaa-unk-s:\nNt|aaa-60-rv-s|aaa-60-s-rv|ambassador/60 lines+sl+rv:\\\n\t:md=\\E[1;7m:mr=\\E[m:mb=\\E[5;7m:mk=\\E[7;8m:me=\\E[7m:\\\n\t:us=\\E[4;7m:ue=\\E[7m:se=\\E[7m:so=\\E[m:\\\n\t:ti=\\E[2J\\E[60;1;0;60p:te=\\E[60;1;0;60p\\E[59;1H\\E[J:li#59:\\\n\t:is=\\EP`+x~M\\E\\\\\\E[7m\\E7\\E[60;1;0;60p\\E[3g\\E[f\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E8\\E[>6h\\E[1Q:\\\n\t:tc=aaa-unk-s:\nNL|aaa-24-ctxt|ann arbor ambassador/24 lines:\\\n\t:ti=\\E[30;1H\\E[K\\E[24;0;0;24p:te=\\E[60;1;0;24p\\E[60;1H\\E[K:tc=aaa-24:\nNL|aaa-24-rv-ctxt|ambassador/24+rv:\\\n\t:ti=\\E[30;1H\\E[K\\E[24;0;0;24p:te=\\E[60;1;0;24p\\E[60;1H\\E[K:tc=aaa-24-rv:\nNL|aaa-s-ctxt|aaa-30-s-ctxt|hairy aaa:\\\n\t:ti=\\E[30;1H\\E[K\\E[30;1;0;30p:te=\\E[60;1;0;30p\\E[59;1H\\E[K:tc=aaa-30-s:\nNL|aaa-s-rv-ctxt|aaa-30-s-rv-ctxt|hairy aaa:\\\n\t:md=\\E[1;7m:mr=\\E[m:mb=\\E[5;7m:mk=\\E[7;8m:me=\\E[7m:\\\n\t:us=\\E[4;7m:ue=\\E[7m:se=\\E[7m:so=\\E[m:\\\n\t:is=\\EP`+x~M\\E\\\\\\E[7m\\E7\\E[60;1;0;30p\\E[3g\\E[f\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E8\\E[>6h\\E[1Q:\\\n\t:ti=\\E[30;1H\\E[K\\E[30;1;0;30p:te=\\E[60;1;0;30p\\E[59;1H\\E[K:\\\n\t:li#29:tc=aaa-unk-s:\nNH|aaa-ctxt|aaa-30-ctxt|ann arbor ambassador/30 lines:\\\n\t:ti=\\E[30;0;0;30p:te=\\E[60;0;0;30p\\E[60;1H\\E[K:tc=aaa-30:\nNH|aaa-rv-ctxt|aaa-30-rv-ctxt|ann arbor ambassador/30 lines:\\\n\t:ti=\\E[30;0;0;30p:te=\\E[60;0;0;30p\\E[60;1H\\E[K:\\\n\t:md=\\E[1;7m:mr=\\E[m:mb=\\E[5;7m:mk=\\E[7;8m:me=\\E[7m:\\\n\t:us=\\E[4;7m:ue=\\E[7m:se=\\E[7m:so=\\E[m:\\\n\t:is=\\EP`+x~M\\E\\\\\\E[7m\\E7\\E[60;0;0;30p\\E[3g\\E[f\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E[8a\\EH\\E8\\E[>6h\\E[1Q:\\\n\t:li#30:tc=aaa-unk:\nNd|aaa-db|ann arbor ambassador 30/destructive backspace:\\\n\t:ti=\\E[H\\E[J\\E[30;0;0;30p:te=\\E7\\E[60;0;0;30p\\E8:li#30:\\\n\t:is=\\E[60;0;0;30p\\E[H\\E[J\\E[1Q\\E[m\\E[20l\\E[>30h:le=\\E[D:bc=\\E[D:bs@:\\\n\t:tc=aaa-unk:\nN1|aa|annarbor|4080|ann arbor 4080:\\\n\t:do=^J:pt:ct=^\\^P^P:st=^]^P1:cm=^O%r%\\066%.%>^S^L%+@:\\\n\t:co#80:li#40:le=^H:bs:cl=2^L:up=^N:nd=^_:ho=^K:am:\\\n\t:kb=^^:kd=^J:ku=^N:kl=^H:kr=^_:kh=^K:ma=^_ ^N^P:\n# \f# --------------------------------\n#\n# P: PC entries for use with kermit\n#\n# greg small (gts@populi)\n#\n# Cannot use :pt:, it does not work (why?).  :ho: seems required (why?). [gts]\n# Caution: 4.3 BSD tset does not pass li#25 to stty rows except during login?\n# :cl: clears attributes and sets wrap at margin before clearing the screen.\nP1|ansi.sys|ansisys|PC-DOS 3.1 ANSI.SYS:\\\n\t:am:bs:ce=\\E[K:cl=\\E[m\\E[7h\\E[2J:cm=\\E[%i%d;%dH:co#80:\\\n\t:ku=^K:kd=^J:kl=^H:kr=^L:kh=^^:ma=^Hh\\012j^Kk^Ll^^H:\\\n\t:ho=\\E[H:li#25:nd=\\E[C:up=\\E[A:\\\n\t:ms:md=\\E[1m:me=\\E[m:mr=\\E[7m:se=\\E[m:so=\\E[1m:ue=\\E[m:us=\\E[4m:\\\n\t:is=U1 PC-DOS 3.1 ANSI.SYS 9-23-86\\n\\E[m\\E[7h:\n#\n# Define IBM PC keypad keys for vi as per MS-Kermit while using ANSI.SYS.\n# This should only be used when the terminal emulator cannot redefine the keys.\n# Since redefining keys with ansi.sys also affects PC-DOS programs, the key\n# definitions must be restored.  If the terminal emulator is quit while in vi\n# or others using :ks:ke:, the keypad keys will not be defined as per PC-DOS.\n# The PgUp and PgDn are prefixed with ESC so that tn3270 can be used on Unix\n# (^U and ^D are already defined for tn3270).  The ESC is safe for vi but it\n# does \"beep\".  ESC ESC i is used for Ins to avoid tn3270 ESC i for coltab.\n# Left arrow is always BS, because PC-dos can tolerate this change.\n# Caution: vi is limited to 256 string bytes, longer crashes or wierds vi.\n# Consequently the End keypad key could not be set (it is relatively safe and\n# actually useful because it sends ^@ O, which beeps and opens a line above).\nP2|ansi.sysk|ansisysk|PC-DOS 3.1 ANSI.SYS with keypad redefined for vi:\\\n\t:ks=\\E[;71;30p\\E[;72;11p\\E[;73;27;21p\\E[;77;12p\\E[;80;10p\\E[;81;27;4p\\E[;82;27;27;105p\\E[;83;127p:\\\n\t:ke=\\E[;71;0;71p\\E[;72;0;72p\\E[;73;0;73p\\E[;77;0;77p\\E[;80;0;80p\\E[;81;0;81p\\E[;82;0;82p\\E[;83;0;83p:\\\n\t:is=U2 PC-DOS 3.1 ANSI.SYS with keypad redefined for vi 9-29-86\\n\\E[;75;8p:\\\n\t:tc=ansi.sys\n#\n# Adds ins/del line/character, hence vi reverse scrolls/inserts/deletes nicer.\nP3|nansi.sys|nansisys||PC-DOS Public Domain NANSI.SYS:\\\n\t:al=\\E[1L:dl=\\E[1M:ic=\\E[1@:dc=\\E[1P:\\\n\t:is=U3 PC-DOS Public Domain NANSI.SYS 9-23-86\\n:\\\n\t:tc=ansi.sys:\n#\n# See U2 ansi.sysk and U3 nansi.sys above.\nP4|nansi.sysk|nansisysk|PC-DOS Public Domain NANSI.SYS with keypad redefined for vi:\\\n\t:al=\\E[1L:dl=\\E[1M:ic=\\E[1@:dc=\\E[1P:\\\n\t:is=U4 PC-DOS Public Domain NANSI.SYS with keypad redefined for vi 9-29-86\\n\\E[;75;8p:\\\n\t:tc=ansi.sysk:\n# \f# --------------------------------\n#\n# T: TELETYPE\n#\n# We need descriptions for the model 40.  There are known to be at least three\n# flavors of the 40, both seem more like IBM half duplex forms fillers than\n# ASCII terminals.  They have lots of awful braindamage, such as printing\n# a visible newline indicator after each newline.  The 40-1 is a half duplex\n# terminal and is hopeless.  The 40-2 is braindamaged but has hope and is\n# described here.  The 40-4 is a 3270 lookalike and beyond hope.\n# The terminal has visible bell but I don't know it - it's\n# null here to prevent it from showing the BL character.\n# There is an \\EG in nl because of a bug in vi (if stty says you have\n# a \"newline\" style terminal (-crmode) vi figures all it needs is nl\n# to get crlf, even if cr is not ^M.)\nT0|40|tty40|ds40|ds40/2|ds40-2|dataspeed40|teletype dataspeed 40/2:\\\n\t:cl=160\\ER:cd=160\\EJ:al=160\\EL:dl=160\\EM:dc=50\\EP:im=:ei=:ic=50\\E\\^:\\\n\t:nd=\\EC:up=\\E7:bs:cr=\\EG:nl=\\EG\\EB:do=\\EB:co#80:li#24:vb=:\\\n\t:so=\\E3:se=\\E4:\nT3|33|tty33|tty|model 33 teletype:\\\n\t:do=^J:co#72:hc:os:\nT4|43|tty43|model 43 teletype:\\\n\t:do=^J:kb=^h:am:le=^H:bs:hc:os:co#132:\nT7|37|tty37|model 37 teletype:\\\n\t:do=^J:le=^H:bs:hc:hu=\\E8:hd=\\E9:up=\\E7:os:\n# From jwb Wed Mar 31 13:25:09 1982 remote from ihuxp\n# This entry appears to avoid the top line - I have no idea why.\nTT|4424|tty4424|teletype 4424M:\\\n\t:al=\\EL:da:db:ip=2:im=:ei=:ic=\\E\\^:dc=\\EP:dl=\\EM:\\\n\t:co#80:li#23:am:cl=\\E[2;H\\E[J:bs:cm=\\E[%i%2;%2H\\E[B:\\\n\t:nd=\\E[C:up=\\E[A:pt:mi:sr=\\ET:\\\n\t:ce=\\E[K:so=\\E[7m:se=\\E[m:us=\\E[4m:ue=\\E[m:\\\n\t:is=\\E[m\\E[2;24r:\\\n\t:kd=\\E[B:kl=\\E[D:ku=\\E[A:kr=\\E[C:\\\n\t:kh=\\E[H:k1=\\EOP:k2=\\EOQ:k3=\\EOR:k4=\\EOS:\n# Teletype blit.\nTD|dmd|5620|ttydmd|tty5620|5620\tterminal 88 columns:\\\n\t:co#88:li#70:am:bs:pt:cm=\\E[%i%d;%dH:nd=\\E[C:up=\\E[A:\\\n\t:cl=\\E[H\\E[J:cd=\\E[J:ce=\\E[K:al=\\E[L:dl=\\E[M:do=^J:\\\n\t:im=:ei=:ic=\\E[@:dc=\\E[P:sr=\\E[T:sf=\\E[S:le=^H:kb=^H:\\\n\t:kl=\\E[D:kr=\\E[C:ku=\\E[A:kd=\\E[B:kh=\\E[H:ho=\\E[H:ll=\\E[70;1H:\\\n\t:AL=\\E[%dL:DL=\\E[%dM:IC=\\E[%d@:DC=\\E[%dP:rc=\\E8:rs=\\Ec:sc=\\E7:\\\n\t:so=\\E[7m:se=\\E[0m:us=\\E[4m:ue=\\E[0m:ms:me=\\E[0m:mr=\\E[7m:\n# \f# --------------------------------\n#\n# V: VISUAL\n#\n# The Visual 200 beeps when you type a character in insert mode.\n# This is a horribly obnoxious misfeature, and some of the entries\n# below try to get around the problem by ignoring the feature or\n# turning it off when inputting a character.  They are said not to\n# work well at 300 baud.  (You could always cut the wire to the bell!)\n#From mike@brl-vgr Mon Nov 14 08:34:29 1983\nV2|vi200|vis200|visual 200 with function keys:\\\n\t:so=\\E4:se=\\E3:ms:do=^J:\\\n\t:al=\\EL:am:le=^H:bs:cd=\\Ey:ce=\\Ex:cl=\\Ev:\\\n\t:cm=\\EY%+ %+ :co#80:dc=\\EO:dl=\\EM:ho=\\EH:\\\n\t:im=:ei=:ic=\\Ei \\b\\Ej:\\\n\t:is=\\E3\\Eb\\Ej\\E\\\\\\El\\EG\\Ec\\Ek:\\\n\t:k0=\\EP:k1=\\EQ:k2=\\ER:k3=\\E :k4=\\E!:k5=\\E\":k6=\\E#:\\\n\t:k7=\\E$:k8=\\E%:k9=\\E&:kl=\\ED:kr=\\EC:ku=\\EA:kd=\\EB:kh=\\EH:\\\n\t:li#24:nd=\\EC:pt:sr=\\EI:up=\\EA:vs=\\Ed:ve=\\Ec:\nVR|vi200-rv-ic|visual 200 reverse video using insert char:\\\n\t:ei=\\Ej:im=\\Ei:ic@:tc=vi200-rv:\n# The older Visuals didn't come with function keys. This entry uses\n# ks and ke so that the keypad keys can be used as function keys.\n# If your version of vi doesn't support function keys you may want\n# to use V2.\nVf|vi200-f|visual|visual 200 no function keys:\\\n\t:do=^J:al=\\EL:am:le=^H:bs:cd=\\Ey:ce=4*\\Ex:cl=\\Ev:\\\n\t:cm=\\EY%+ %+ :co#80:dc=4*\\EO:dl=4*\\EM:ho=\\EH:\\\n\t:im=:ei=:ic=\\Ei \\b\\Ej:\\\n\t:is=\\E3\\Eb\\Ej\\E\\\\\\El\\EG\\Ed\\Ek:ks=\\E=:ke=\\E>:\\\n\t:k0=\\E?p:k1=\\E?q:k2=\\E?r:k3=\\E?s:k4=\\E?t:k5=\\E?u:k6=\\E?v:\\\n\t:k7=\\E?w:k8=\\E?x:k9=\\E?y:kl=\\ED:kr=\\EC:ku=\\EA:kd=\\EB:kh=\\EH:\\\n\t:li#24:nd=\\EC:pt:sr=\\EI:up=\\EA:vs=\\Ed:ve=\\Ec:\nVr|vi200-rv|visual 200 reverse video:\\\n\t:so=\\E4:se=\\E3:sr@:vs@:ve@:tc=vi200:\nVt|vi200-ic|visual 200 using insert char:\\\n\t:ei=\\Ej:im=\\Ei:ic@:tc=vi200:\n# From: jbs@athena.mit.edu\tJeff Siegal\nV5|vi55|Visual 55:\\\n\t:im=\\Ea:ei=\\Eb:mi:dc=\\Ew:dm=:ed=:al=\\EL:dl=\\EM:cs=\\E_%+A%+A:\\\n\t:ho=\\EH:cl=\\Ev:is=\\Ev\\E_AX\\Eb\\EW\\E9P\\ET:so=\\EU:se=\\ET:ms:\\\n\t:do=^J:le=^H:bs:cd=\\EJ:ce=\\EK:cm=\\EY%+ %+ :co#80:li#24:\\\n\t:nd=\\EC:pt:sr=\\EI:up=\\EA:ku=\\EA:kd=\\EB:kr=\\EC:kl=\\ED:kb=^H:\n# \f# --------------------------------\n#\n# X: TEKTRONIX\n#\nXa|tek|tek4012|4012|tektronix 4012:\\\n\t:do=^J:is=\\E^O:le=^H:bs:cl=1000\\E^L:co#75:ns:li#35:os:\nXb|tek4013|4013|tektronix 4013:\\\n\t:as=\\E^N:ae=\\E^O:dF#1000:tc=4012:\nXc|tek4014|4014|tektronix 4014:\\\n\t:is=\\E^O\\E9:co#81:li#38:dF#1000:tc=tek4012:\nXd|tek4015|4015|tektronix 4015:\\\n\t:as=\\E^N:ae=\\E^O:tc=4014:\nXe|tek4014-sm|4014-sm|tektronix 4014 in small font:\\\n\t:is=\\E^O\\E\\072:co#121:li#58:tc=tek4014:\nXf|tek4015-sm|4015-sm|tektronix 4015 in small font:\\\n\t:as=\\E^N:ae=\\E^O:tc=4014-sm:\n# I think the 1000UP is supposed to be so expensive it never happens.\nX4|tek4023|4023|tex|tektronix 4023:\\\n\t:do=^J:so=^_P:se=^_@:cm=\\034%r%+ %+ :nd=\\t:le=^H:\\\n\t:bs:cl=4\\E^L:co#80:li#24:am:up=1000UP:vt#4:\n# Can't use cursor motion because it's memory relative, and because\n# it only works in the workspace, not the monitor.  Same for home.\n# Likewise, standout only works in the workspace.\n# 145 ms padding on al and AL taken out since it doesn't seem to be needed much.\nX5|4025|4027|4024|tek4025|tek4027|tek4024|4025cu|4027cu|tektronix 4024/4025/4027:\\\n\t:sf=^F^J:do=^F^J:is=\\41com 31\\r\\n^_sto 9 17 25 33 41 49 57 65 73\\r:\\\n\t:ks=^_lea p4 /h/\\r^_lea p8 /k/\\r^_lea p6 / /\\r^_lea p2 /j/\\r^_lea f5 /H/\\r^_lea p5 /H/\\r:\\\n\t:ke=^_lea p2\\r^_lea p4\\r^_lea p6\\r^_lea p8\\r^_lea p5\\r^_lea f5\\r:\\\n\t:am:le=^H:bs:da:db:pt:li#34:co#80:cl=^_era\\r\\n\\n:up=^K:nd=^_rig\\r:\\\n\t:al=^_up\\r^_ili\\r:dl=^_dli\\r^F:\\\n\t:dc=^_dch\\r:im=^_ich\\r:ei=^F^_dow\\r^K:nl=^F\\n:\\\n\t:cd=^_dli 50\\r:CC=^_:AL=^_up\\r^_ili %d\\r:DL=^_dli %d\\r^F:\\\n\t:UP=^_up %d\\r:DO=^_dow %d\\r:LE=^_lef %d\\r:RI=^_rig %d\\r:\nX7|4025-17|4027-17|tek 4025 17 line window:\\\n\t:li#17:tc=4025:\nX8|4025-17ws|4027-17ws|tek 4025 17 line window in workspace:\\\n\t:is=\\41com 31\\r\\n^_sto 9,17,25,33,41,49,57,65,73\\r^_wor 17\\r^_mon 17\\r:\\\n\t:ti=^_wor h\\r:te=^_mon h\\r:so=^_att e\\r:se=^_att s\\r:tc=4025-17:\nX9|4025ex|4027ex|tek 4025 w/!:\\\n\t:ti=\\41com 31\\r:te=^_com 33\\r:\\\n\t:is=^_com 33\\r\\n\\41sto 9,17,25,33,41,49,57,65,73\\r:tc=4025:\n# From jcoker@ucbic\nXp|4107|tek4107|Tektronix 4107 graphics terminal with memory:\\\n\t:ti=\\E[?6l\\E[H\\E[J:te=\\E[?6h\\E%!0\\ELBP0\\E%!1\\E[32;1f:\\\n\t:is=\\E%!0\\ELBP0\\E%!1\\E[H\\E[2g\\EH\\E[8C\\EH\\E[8C\\EH\\E[8C\\EH\\E[8C\\EH\\E[8C\\EH\\E[8C\\EH\\E[8C\\EH\\E[8C\\EH\\E[8C\\EH\\E[J:\\\n\t:li#32:do=^J:al=3\\E[L:xn:am:le=^H:bs:cd=\\E[J:\\\n\t:ce=5\\E[K:cl=156\\E[H\\E[J:cm=\\E[%i%d;%dH:co#80:dc=4\\E[P:dl=3\\E[M:\\\n\t:ho=\\E[H:ic=4\\E[@:md=\\E[1m:mr=\\E[7m:mb=\\E[5m:me=\\E[m:ku=\\EM:\\\n\t:kd=\\ED:kl=\\E[D:kr=\\E[C:kh=\\E[H:\\\n\t:ei=:im=:pt:bw:bt=\\E[Z:mi:nd=\\E[C:se=\\E[m:so=\\E[7m:\\\n\t:ue=\\E[m:us=\\E[4m:up=\\EM:\n#  Tektronix 4107 with sysline\nXq|4107-s|tek4107-s|Tektronix 4107 with sysline but no memory:\\\n\t:is=\\E%!1\\E[2;32r\\E[132D\\E[2g\\EH\\E[8C\\EH\\E[8C\\EH\\E[8C\\EH\\E[8C\\EH\\E[8C\\EH\\E[8C\\EH\\E[8C\\EH\\E[8C\\EH\\E[8C\\EH\\E[J:\\\n\t:es:hs:i2=\\E7\\E[?6l\\E[2K\\E[?6h\\E8:ts=\\E7\\E[?6l\\E[2K\\E[;%i%df:\\\n\t:fs=\\E[?6h\\E8:ds=\\E7\\E[?6l\\E[2K\\E[?6h\\E8:tc=4107:\n# From cbosg!teklabs!davem Wed Sep 16 21:11:41 1981\n# Here's the comamnd file that I use to get rogue to work on the 4025.\n# It should work with any program using the old curses (e.g. it better\n# not try to scroll, or cursor addressing won't work.  Also, you can't\n# see the cursor.)\n# (This \"learns\" the arrow keys for rogue. I have adapted it for termcap - mrh)\nXr|4025-cr|tek 4025 for curses and rogue:\\\n\t:is=\\41com 31\\r\\n^_sto 9 17 25 33 41 49 57 65 73\\r:\\\n\t:am:le=^H:bs:pt:li#33:co#80:cm=^_jum%i%d,%d;:up=^K:\\\n\t:do=^F^J:cl=^_era;:nd=^_rig;:nl=^F\\n:ti=^_wor 33h:te=^_wor 0:\n# next two lines commented out since curses only allows 128 chars, sigh.\n#\t:ti=^_lea p1/b/^_lea p2/j/^_lea p3/n/^_lea p4/h/^_lea p5/ /^_lea p6/l/^_lea p7/y/^_lea p8/k/^_lea p9/u/^_lea p./f/^_lea pt/`era w/13^_lea p0/s/^_wor 33h:\\\n#\t:te=^_lea p1^_lea p2^_lea p3^_lea p4^_lea pt^_lea p5^_lea p6^_lea p7^_lea p8^_lea p9/la/13^_lea p.^_lea p0^_wor 0:\n# The 4110 series may be a wonderful graphics series, but they make the 4025\n# look good for screen editing.  In the dialog area, you can't move the cursor\n# off the bottom line.  Out of the dialog area, ^K moves it up, but there\n# is no way to scroll.\nXs|4112|4114|tek4112|tektronix 4110 series:\\\n\t:is=\\E3!1:li#34:co#80:am:al=\\E[L:bs:bt=\\E[Z:\\\n\t:cd=\\E[0J:ce=\\E[0K:cl=\\E[2J\\E[0;0H:cm=\\E[%i%d;%dH:\\\n\t:db:dc=\\E[P:dl=\\E[M:ic=\\E[@:im=:nd=\\E[C:se=\\E[m:\\\n\t:so=\\E[7m:ue=\\E[m:up=\\EM:us=\\E[4m:vs=:ve=:\\\n\t:sr=\\E7\\E[0;0H\\E[L\\E8:sf=\\E7\\E[0;0H\\E[M\\E8:\nXt|4112-nd|4112 not in dialog area:up=^K:ns:tc=4112:\nXu|4112-5|4112 in 5 line dialog area:li#5:tc=4112:\nXv|4113|tek4113|tektronix 4113 color graphics, 5 line dialog area:\\\n\t:le=^H:do=^J:eo:da:bs:am:li#5:co#80:is=\\EKA1\\ELL5\\ELV0\\ELV1:\\\n\t:vb=\\ERBA4\\ERBA4\\ERBA4\\ERBA4\\ERBA4\\ERBA4\\ERBA4\\ERBA4\\ERBA4\\ERBA4\\ERB0:\\\n\t:cl=\\ELZ:uc=^H\\ELM1_\\ELM0:nd=\\LM1 \\LM0:\\\n\t:.as=\\E^N:.ae=\\E^O:\nXw|4113-34|tek4113-34|tektronix 4113 color graphics, 34 line dialog area:\\\n\t:is=\\EKA1\\ELLB2\\ELV0\\ELV1:li#34:tc=tek4113:\n# ns hidden from vi to allow visual mode. APL font (as, ae) not supported here.\n# uc is slow, but looks nice. Suggest setenv MORE -up . vb needs enough delay\n# to let you see the background color being toggled.\nXy|4113-nd|tek4113-nd|tektronix 4113 color graphics, no dialog area:\\\n\t:le=^H:do=^J:nd=\\t:up=^K:ll=\\ELF hl @:ho=\\ELF7l\\177 @:\\\n\t:eo:bs:am:li#34:co#80:is=\\ELZ\\EKA0\\ELF7l\\177 @:vs=\\ELZ\\EKA0:\\\n\t:vb=\\ERBA4\\ERBA4\\ERBA4\\ERBA4\\ERBA4\\ERBA4\\ERBA4\\ERBA4\\ERBA4\\ERBA4\\ERB0:\\\n\t:cl=\\E\\f:uc=^H\\EMG1_\\EMG0:so=\\EMT2:se=\\EMT1:\\\n\t:.ns:.as=\\E^N:.ae=\\E^O:\nXz|4105|tek4105:\\\n\t:al=\\E[1L:am:bs:cd=\\E[J:ce=\\E[K:cl=\\E[2J\\E[H:cm=\\E[%i%2;%2H:co#80:\\\n\t:dc=\\E[1P:dl=\\E[1M:dn=\\E[1B:ho=\\E[H:im=\\E[4h:li#30:mi:nd=\\E[1C:\\\n\t:as=\\E[1m:ae=\\E[0m:ms:pt:se=\\E[0m:so=\\E[7m:up=\\E[1A:kb=^h:ku=\\E[1A:\\\n\t:kd=\\E[1B:kl=\\E[1D:kr=\\E[1C:us=\\E[4m:ue=\\E[0m:is=\\E%!1\\E[?6l\\E[0m:\\\n\t:mr=\\E[<3m:md=\\E[<4m:mh=\\E[<6m:mb=\\E[<7m:me=\\E[<1m:ti=\\E%!1\\E[?6l:xt:\n# This entry is from Tek. Inc.  (Brian Biehl)\nXz|4115|tek4115|Tektronix 4115:\\\n\t:co#80:li#34:\\\n\t:al=\\E[L:am:bc=\\E[D:bs:bt=\\E[Z:cd=\\E[J:ce=\\E[K:\\\n\t:cl=\\E[;H\\E[2J:cm=\\E[%i%d;%dH:da:db:dc=\\E[P:dl=\\E[M:do=\\E[B:\\\n\t:ei=\\E[4l:eo:ho=\\E[;H:im=\\E[4h:if=/usr/share/tabset/vt100:\\\n\t:is=\\E%\\0410\\E%\\014\\ELV0\\EKA1\\ELBB2\\ENU@\\075\\ELLB2\\ELM0\\ELV1\\EKYA?\\E%\\0411\\E[<1l\\E[?7h\\E[?8h\\E[34;1H\\E[34B\\E[0m:\\\n\t:kb=^H:ke=\\E>:ks=\\E=:nd=\\E[C:pt:se=\\E[m:so=\\E[7m:sr=\\EM:\\\n\t:te=\\E%\\0410\\ELBG8\\E%\\0411\\E[34;1H\\E[J:\n\t:ti=\\E%\\0410\\ELBB2\\E%\\0411:\\\n\t:ue=\\E[m:up=\\E[A:us=\\E[4m:\\\n\t:ve=\\E%\\0410\\ELBG8\\E%\\0411\\E[34;1H:\\\n\t:vs=\\E%\\0410\\ELBB2\\E%\\0411:\n# The tek4125 emulates a vt100 incorrectly - the scrolling region\n# command is ignored. The following entry replaces the cs with the\n# needed al, dl, and im; removes some cursor pad commands that the tek4125\n# chokes on; and adds a lot of initialization for the tek dialog area.\n# Note that this entry uses all 34 lines and sets the cursor color to green.\n# Steve Jacobson 8/85\nXB|tek4125:\\\n\t:ks=\\E=:li#34:\\\n\t:is=\\E%\\!0\\EQD1\\EUX03\\EKA\\ELBB2\\ELCE0\\ELI100\\ELJ2\\ELLB2\\ELM0\\ELS1\\ELX00\\ELV1\\E%\\!1\\E>\\E[?3l\\E[?4l\\E[?5l\\E[?7h\\E[?8h:dl=\\E[1M:\\\n\t:al=\\E[1L:cs@:sc@:rc@:im=\\E1:tc=vt100:\n# From carolyn@dali.berkeley.edu  Thu Oct 31 12:54:27 1985\nXA|4404|tek4404:\\\n\t:al=\\E[1L:bs:cd=\\E[J:ce=\\E[K:cl=\\E[;H\\E[2J:cm=\\E[%i%d;%dH:co#80:\\\n\t:cs=\\E[%i%d;%dr:dc=\\E[P:dl=\\E[1M:do=^J:ei=\\E[4l:ho=\\E[H:im=\\E[4h:\\\n\t:kd=\\E[B:ke=\\E[?1h:kl=\\E[D:kr=\\E[C:ks=\\E[?1l:ku=\\E[A:li#32::mb=\\E[5m:\\\n\t:md=\\E[1m:me=\\E[m:nd=\\E[C:pt:rc=\\E8:sc=\\E7:se=\\E[27m:so=\\E[7m:\\\n\t:ta=\\E[2I:ti=\\E%\\!1\\E[1;32r\\E[?6l\\E>:te=\\E[1;1H\\E[0J\\E[?6h\\E[?1l:\\\n\t:ue=\\E[m:up=\\E[A:us=\\E[4m:\n# \f# --------------------------------\n#\n# Z: Miscellaneous\n#\n# These compucolors appear similar, but they at least have different\n# sized screens.  I don't know what's going on here.\nZ1|8001|ISC8001|compucolor|intecolor:\\\n\t:do=^J:al=\\EU:am:le=^Z:bc=^Z:cl=3*^L:cm=^C%r%.%.:\\\n\t:co#80:cd=\\EQ:dm=\\EQ:ed=\\EF:dc=\\177:dl=\\EV:ei=\\EF:\\\n\t:im=\\EQ:li#40:nd=1^Y:ta=8\\t:up=^\\:ho=1^H:pc=^@:\nZ2|compucolor2|compucolorII:\\\n\t:do=^J:pt:am:cm=%r^C%.%.:le=^Z:bc=^Z:li#32:co#64:\\\n\t:cl=^L:ho=^H:nd=^Y:up=^\\:\n# From cithep!eric  Wed Sep 16 08:06:44 1981\nZ3|intext|Interactive Systems Corporation modified owl 1200:\\\n\t:do=^J:al=5.5*\\020:am:le=^_:bc=^_:le=^H:bs:bt=^Y:cd=5.5*\\026J:\\\n\t:ce=^K\\160^R:cl=132\\014:cm=\\017%+ %+ :co#80:dc=5.5*\\022:dl=5.5*\\021:\\\n\t:ei=\\026\\074:im=\\026\\073:ip=5.5*:li#24:nd=\\036:pt:up=\\034:\\\n\t:se=^V# :sg#1:so=^V$,:ma=^K^P^R^L^L :\\\n\t:kl=^_:kd=^J:kr=^^:ku=\\034:kb=^H:kh=^Z:\\\n\t:k1=^VA\\r:k2=^VB\\r:k3=^VC\\r:k4=^VD\\r:k5=^VE\\r:\\\n\t:k6=^VF\\r:k7=^VG\\r:k8=^VH\\r:k9=^VI\\r:k0=^VJ\\r:\n# \f# --------------------------------\n#\n# a: ADDS\n#\n# Regent: lowest common denominator, works on all regents.\na0|regent|Adds Regent Series:li#24:co#80:am:cl=^L:ll=^A:up=^Z:\\\n\t:bs:bc=^U:nd=^F:do=^J:ho=\\EY  :\n# Regent 100 has a bug where if computer sends escape when user is holding\n# down shift key it gets confused, so we avoid escape.\na1|regent100|Adds Regent 100:k0=^B1^M:k1=^B2^M:k2=^B3^M:k3=^B4^M:\\\n\t:k4=^B5^M:k5=^B6^M:k6=^B7^M:k7=^B8^M:\\\n\t:l0=F1:l1=F2:l2=F3:l3=F4:l4=F5:l5=F6:l6=F7:l7=F8:\\\n\t:so=\\E0P:ue=\\E0@:us=\\E0`:se=\\E0@:\\\n\t:cm=^K%+ %B^P%.:ug#1:sg#1:tc=regent:\na2|regent20|Adds Regent 20:cd=\\Ek:ce=\\EK:cm=\\EY%+ %+ :tc=regent:\na3|regent25|Adds Regent 25:kh=^A:kl=^U:kr=^F:ku=^Z:kd=^J:tc=regent20:\na4|regent40|Adds Regent 40:k0=^B1^M:k1=^B2^M:k2=^B3^M:k3=^B4^M:\\\n\t:k4=^B5^M:k5=^B6^M:k6=^B7^M:k7=^B8^M:\\\n\t:l0=F1:l1=F2:l2=F3:l3=F4:l4=F5:l5=F6:l6=F7:l7=F8:\\\n\t:al=2*\\EM:dl=2*\\El:\\\n\t:so=\\E0P:ue=\\E0@:us=\\E0`:se=\\E0@:ug#1:sg#1:tc=regent25:\na5|regent40+|Adds Regent 40+:is=\\EB:tc=regent40:\na6|regent60|regent200|Adds Regent 60:se=\\ER\\E0@\\EV:so=\\ER\\E0P\\EV:dc=\\EE:ei=\\EF:\\\n\t:im=\\EF:is=\\EV\\EB:ko=dc,im,ei:tc=regent40+:\na7|regent60na|regent 60 w/no arrow keys:\\\n\tkl@:kr@:ku@:kd@:tc=regent60:\n#\n# adds viewpoint 90 - from cornell\n# Note:  emacs sends ei occasionally to insure the terminal is out of\n#        insert mode. This unfortunately puts the viewpoint90 IN insert\n#        mode.  A hack to get around this is:  ic=\\EF \\EF^U.  (Also,\n#   -    ei=:im=: must be present.)\n#   -    xs indicates glich that attributes stick to location\n#   -    bs save to move in standout mode\n#   -    cl=\\EG\\Ek clears screen and visual attributes without affecting\n#               the status line\na9|vp90|viewpoint90|adds viewpoint 90:\\\n\t:bs:bw:cd=\\Ek:ce=\\EK:cl=\\EG\\Ek:cm=\\EY%+ %+ :co#80:\\\n\t:dc=\\EE:dl=\\El:dm=:do=^J:ed=:ei=:im=:ic=\\EF \\EF^U:ho=\\EY  :\\\n\t:nd=^F:up=^Z:\\\n\t:kb=^H:kd=^J:kh=^A:kl=^U:kr=^F:ku=^Z:li#24:ll=^A:\\\n\t:so=\\ER\\E0Q\\EV:se=\\ER\\E0@\\EV:\\\n\t:us=\\ER\\E0`\\EV:ue=\\ER\\E0@\\EV:\\\n\t:xs:ms:\n# Note: if return acts weird on a980, check internal switch #2\n# on the top chip on the CONTROL pc board.\nac|a980|adds consul 980:\\\n\t:do=^J:al=13\\E^N:am:le=^H:bs:cl=^L\\200^K@:cm=^K%+@\\E^E%2:co#80:\\\n\t:dl=13\\E^O:k0=\\E0:k1=\\E1:k2=\\E2:k3=\\E3:k4=\\E4:k5=\\E5:k6=\\E6:k7=\\E7:\\\n\t:k8=\\E8:k9=\\E9:li#24:nd=\\E^E01:so=^Y^^^N:se=^O:up=9:\nas|viewpt60|viewpoint60|addsviewpoint60|adds viewpoint60:\\\n\t:tc=regent40:\n# From Onyx:edward  Thu Jul  9 09:27:33 1981\nav|viewpoint|addsviewpoint|adds viewpoint:\\\n\t:do=^J:am:le=^H:bs:li#24:co#80:cm=\\EY%+ %+ :cd=\\Ek:ce=\\EK:\\\n\t:up=^Z:cl=^L:ll=^A:kl=^U:kd=^J:ku=^Z:kh=^A:\\\n\t:so=^N:se=^O:us=^N:ue=^O:is=^O\\E0`:vs=^O\\E0P:ve=^O\\E0`:\n# \f# --------------------------------\n#\n# b: BEEHIVE\n#\n# Reports are that most of these Beehive entries (except superbee) have not been\n# tested and do not work right.  se is a trouble spot.  Be warned.\nb2|sb2|sb3|fixed superbee:\\\n\t:xb@:tc=superbee:\n# set tab is ^F, clear (one) tab is ^V, no way to clear all tabs.\n# good grief - does this entry make sg/ug when it doesn't have to?\n# look at those spaces in se/so.  Seems strange to me...\nbh|bh3m|beehiveIIIm:\\\n\t:if=/usr/share/tabset/beehive:do=^J:\\\n\t:al=160^S:am:le=^H:bs:cd=^R:ce=^P:cl=^E^R:\\\n\t:co#80:dl=350^Q:ho=^E:li#20:ll=^E^K:\\\n\t:nd=^L:pt:se= ^_:so=^] :up=^K:\n# This loses on lines > 80 chars long, use at your own risk\nbi|superbeeic|super bee with insert char:\\\n\t:ic=:im=\\EQ:ei=\\ER:tc=superbee:\nbm|microb|microbee|micro bee series:\\\n\t:do=^J:am:le=^H:bs:cd=\\EJ:ce=\\EK:cl=\\EE:co#80:cm=\\EF%+ %+ :\\\n\t:k1=\\Ep:k2=\\Eq:k3=\\Er:k4=\\Es:k5=\\Et:k6=\\Eu:k7=\\Ev:k8=\\Ew:k9=\\Ex:\\\n\t:kd=\\EB:kh=\\EH:kl=\\ED:kr=\\EC:ku=\\EA:\\\n\t:li#24:nd=\\EC:pt:se=\\Ed@ :so= \\EdP:ue=\\Ed@:up=\\EA:us=\\Ed`:\n# Superbee - f1=escape, f2=^C.\n# Note: there are at least 3 kinds of superbees in the world.  The sb1\n# holds onto escapes and botches ^C's.  The sb2 is the best of the 3.\n# The sb3 puts garbage on the bottom of the screen when you scroll with\n# the switch in the back set to CRLF instead of AEP.  This description\n# is tested on the sb2 but should work on all with either switch setting.\n# The f1/f2 business is for the sb1 and the :xb: can be taken out for\n# the other two if you want to try to hit that tiny escape key.\n# This description is tricky: being able to use cm depends on there being\n# 2048 bytes of memory and the hairy nl string.\nbs|sb1|superbee|superb|beehive super bee:\\\n\t:ct=\\E3:st=\\E1:is=\\EH\\EJ:do=^J:\\\n\t:sf=\\n\\200\\200\\200\\n\\200\\200\\200\\EA\\EK\\200\\200\\200\\ET\\ET:\\\n\t:am:le=^H:bs:cd=3\\EJ:ce=3\\EK:cl=3\\EH\\EJ:co#80:cm=\\EF%r%3%3:cr=1000\\r:\\\n\t:dC#10:da:db:xb:dc=3\\EP:dl=100\\EM:so=\\E_1:se=\\E_3:\\\n\t:li#25:nl=\\n\\200\\200\\200\\n\\200\\200\\200\\EA\\EK\\200\\200\\200\\ET\\ET:\\\n\t:nd=\\EC:pt:up=\\EA:ho=\\EH:ve=\\n:\\\n\t:k1=\\Ep:k2=\\Eq:k3=\\Er:k4=\\Es:k5=\\Et:k6=\\Eu:k7=\\Ev:k8=\\Ew:\\\n\t:kd=\\EB:kh=\\EH:kl=\\ED:kr=\\EC:ku=\\EA:\n# 8675, 8686, and bee from Cyrus Rahman\nb7|8675|harris 8675:\\\n\t:k1=^F:k2=^P:k3=^N:k4=^V:k5=^J:k6=^T:k7=^H:k8=\\177:k9=\\Ee:k10=\\Ed:\\\n\t:k11=^W:k12=\\ER:k13=\\EE:k14=\\EI:k15=\\Ei:k16=\\Eg:\\\n\t:is=\\ES\\E#\\E*\\Eh\\Em\\E?\\E1\\E9\\E@\\EX\\EU:\\\n\t:tc=bee:\nb8|8686|harris 8686:\\\n\t:k1=^B^[p^C:k2=^B^[q^C:k3=^B^[r^C:k4=^B^[s^C:k5=\\E3:\\\n\t:k6=\\EI:k7=\\ER:k8=\\EJ:k9=\\E(:k10=\\Ej:k11=\\EW:\\\n\t:k12=^B^[{^C:k13=^B^[|^C:k14=^B^[}^C:k15=^B^[~^C:k16=^B^[\\177^C:\\\n\t:is=\\ES\\E#\\E*\\Eh\\Em\\E?\\E1\\E9\\E@\\EX\\EU\\E\"*Z01\\\n\t\\E\"8F35021B7C83#\\E\"8F45021B7D83#\\E\"8F55021B7E83#\\E\"8F65021B7F83#\\\n\t\\E\"8F75021B7383#\\E\"8F851BD7#\\E\"8F95021B7083#\\E\"8FA5021B7183#\\\n\t\\E\"8FB5021B7283#:\\\n\t:tc=bee:\nbe|bee|harris beehive:\\\n\t:co#80:li#24:am:bs:cd=\\EJ:ce=\\EK:cl=\\EE:nd=\\EC:\\\n\t:cm=\\EF%+ %+ :up=\\EA:do=\\EB:ho=\\EH:bt=\\E>:\\\n\t:al=\\EL:dc=\\EP:dl=\\EM:ei=\\E@:im=\\EQ:ic=:mi:\\\n\t:kl=\\ED:kr=\\EC:ku=\\EA:kd=\\EB:kh=\\EH:kb=^H:\\\n\t:us=\\Ed`:ue=\\Ed@:so=\\EdP:se=\\Ed@:\\\n\t:ko=al,bt,ce,cl,dc,dl,ei,ho,ic,im:\n# \f# --------------------------------\n#\n# c: CONCEPT (HUMAN DESIGNED SYSTEMS)\n#\n# From vax135!hpk  Sat Jun 27 07:41:20 1981\n# Extensive changes to c108 by arpavax:eric Feb 1982\n#\n# There seem to be a number of different versions of the C108 PROMS\n# (with bug fixes in its Z-80 program).\n# The first one that we had would lock out the keyboard of you\n# sent lots of short lines (like /usr/dict/words) at 9600 baud.\n# Try that on your C108 and see if it sends a ^S when you type it.\n# If so, you have an old version of the PROMs.\n# The old one also messed up running vi with a 132-character line-length.\n# You should configure the C108 to send ^S/^Q before running this.\n# It is much faster (at 9600 baud) than the c100 because the delays\n# are not fixed.\n# new status line display entries for c108:\n# hs - has status capability\n# es - escape sequences are OK on status line\n# i2 - second init str - setup term for status display - set programmer mode,\n#\tselect window 2, define window at last line of memory,\n#\tset bkgnd stat mesg there, select window 0.\n# ts - to status line - select window 2, home cursor, erase to end-of-window,\n#\t1/2 bright on, goto(line#0, col#?)\n# fs - from status line - 1/2 bright off, select window 0\n# ds - disable status display - set bkgnd status mesg with illegal window #\n#\n# the following two entries are for emacs -- they are just like the regular\n# entries except that they have buffer overflow control OFF\nc0|e108-8p:\\\n\t:i2=\\EU\\E z\"\\Ev^A\\177 !p\\E ;\"\\E z \\Ev  ^A\\177p\\Ep\\n:\\\n\t:te=\\Ev  ^A\\177p\\Ep\\r\\n:tc=e108-4p:\nc1|e108-4p:\\\n\t:is=\\EU\\E f\\Ef\\E7\\E5\\E8\\El\\ENH\\EK\\E\\200\\Eo&\\200\\Eo\\47\\E\\E!\\E^G!\\E^HA@ :\\\n\t:tc=c108-4p:\nc2|c108|c108-8p|concept108-8p|concept 108 w/8 pages:\\\n\t:i2=\\EU\\E z\"\\Ev^A\\177 !p\\E ;\"\\E z \\Ev  ^A\\177p\\Ep\\n:\\\n\t:te=\\Ev  ^A\\177p\\Ep\\r\\n:tc=c108-4p:\nc3|c108-4p|concept108-4p|concept 108 w/4 pages:\\\n\t:es:hs:ts=\\E z\"\\E?\\E^C\\Ea %+ :fs=\\E z :ds=\\E ;\\177:\\\n\t:i2=\\EU\\E z\"\\Ev\\177 !p\\E ;\"\\E z \\Ev  \\177p\\Ep\\n:do=^J:pt:\\\n\t:is=\\EU\\E F\\Ef\\E7\\E5\\E8\\El\\ENH\\EK\\E\\200\\Eo&\\200\\Eo\\47\\E\\E!\\E^G!\\E^HA@ :\\\n\t:ti=\\EU\\Ev  8p\\Ep\\r:te=\\Ev  \\177p\\Ep\\r\\n:\\\n\t:al=\\E^R:le=^H:bs:cd=\\E^C:ce=\\E^S:cl=\\E?\\E^E:cm=\\Ea%+ %+ :co#80:\\\n\t:dc=\\E^Q:dl=\\E^B:ei=\\E\\200:eo:im=\\E^P:li#24:mi:nd=\\E=:\\\n\t:kb=^h:up=\\E;:db:us=\\EG:ue=\\Eg:vs=\\EW:ve=\\Ew:am:xn:\\\n\t:vb=\\Ek\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\EK:\\\n\t:ks=\\EX:ke=\\Ex:ku=\\E;:kd=\\E<:kl=\\E>:kr=\\E=:kh=\\E?:\\\n\t:k1=\\E5:k2=\\E6:k3=\\E7:k4=\\E8:k5=\\E9:k6=\\E\\72:\\\n\t:so=\\ED:se=\\Ed:mh=\\EE:md=\\ED:mr=\\ED:me=\\Ee\\Ed\\Eg\\Ec:\nc4|c108-rv-8p|concept108-rv-8p|concept 108 w/8 pages, in reverse video:\\\n\t:vb=\\EK\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\Ek:\\\n\t:is=\\EU\\E F\\Ef\\E7\\E5\\E8\\El\\ENH\\Ek\\E\\200\\Eo&\\200\\Eo\\47\\E\\E!\\E^G!\\E^HA@ :\\\n\t:ts=\\E z\"\\E?\\E^C\\EE\\Ea %+ :fs=\\Ee\\E z :tc=c108-8p:\nc5|c108-rv-4p|concept108-rv-4p|concept 108 w/4 pages, in reverse video:\\\n\t:vb=\\EK\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\Ek:\\\n\t:is=\\EU\\E F\\Ef\\E7\\E5\\E8\\El\\ENH\\Ek\\E\\200\\Eo&\\200\\Eo\\47\\E\\E!\\E^G!\\E^HA@ :\\\n\t:ts=\\E z\"\\E?\\E^C\\EE\\Ea %+ :fs=\\Ee\\E z :tc=c108-4p:\nc6|c108-na|c108-na-8p|concept108-na-8p|concept 108 w/8 pages, no arrows:\\\n\t:ks@:ke@:k7=\\E;:k8=\\E<:k9=\\E=:tc=c108-8p\nc7|c108-rv-na|c108-rv-na-8p|concept 108 w/8 pages, no arrows in rev video:\\\n\t:ts=\\E z\"\\E?\\E^C\\EE\\Ea %+ :fs=\\Ee\\E z :\\\n\t:ks@:ke@:k7=\\E;:k8=\\E<:k9=\\E=:tc=c108-rv-8p\n# this needs new frotz in the cm capability for 2-char addrs when > 95....\nc8|c108-w|c108-w-8p|concept108-w-8p|concept 108 w/8 pages in wide mode:\\\n\t:is=\\EU\\E F\\Ef\\E7\\E5\\E8\\El\\ENH\\EK\\E\\200\\Eo&\\200\\Eo\\47\\E\\E\"\\E^G!\\E^HA@ :\\\n\t:ti=\\EU\\Ev  8^AD\\Ep\\r:te=\\Ev  ^A0^AD\\Ep\\r\\n:pt@:cm@:\\\n\t:co#132:tc=c108-8p\ncA|avt-w|avtw|HDS concept avt w/4 or 8 pages; 132 columns:\\\n\t:is=\\E[1*q\\E[2!t\\E[7!t\\E[=4;101;119l\\E[=103;107;118;207h\\E)1\\E[1Q\\EW\\E[7!y\\E[0\\0720\\07232!r\\E[w\\E2\\r\\n:\\\n\t:ch=\\E[%i%3G:cm=\\E[%i%2;%3H:co#132:tc=avt:\ncB|avt-8p-s|concept avt w/8 pages & 80 cols running sysline:\\\n\t:is=\\E[1*q\\E[2!t\\E[7!t\\E[=4;101;103;119l\\E[=107;118;207h\\E)1\\E[1Q\\EW\\E[0!y\\E[0\\0720\\07232!r\\E[2!w\\E[192w\\E[2*w\\E[!w\\E[1;191w\\E2\\r\\n:\\\n\t:hs:es:ts=\\E[2!w\\E[H\\E[J\\E[%i%dG:fs=\\E[!w:\\\n\t:ds=\\E[2!w\\E[2J\\E[!w\\E[*w:te=\\E[1;191w\\E2\\n:tc=avt:\ncC|avt-4p-s|concept avt w/4 pages & 80 cols running sysline:\\\n\t:is=\\E[1*q\\E[2!t\\E[7!t\\E[=4;101;103;119l\\E[=107;118;207h\\E)1\\E[1Q\\EW\\E[0!y\\E[0\\0720\\07232!r\\E[2!w\\E[96w\\E[2*w\\E[!w\\E[1;95w\\E2\\r\\n:\\\n\t:hs:es:ts=\\E[2!w\\E[H\\E[J\\E[%i%dG:fs=\\E[!w:\\\n\t:ds=\\E[2!w\\E[2J\\E[!w\\E[*w:te=\\E[1;95w\\E2\\n:tc=avt:\ncD|avt-rv|HDS concept avt w/4 or 8 pages, 80 columns, reverse video:\\\n\t:is=\\E[1*q\\E[2!t\\E[7!t\\E[=4;101;103;119l\\E[=107;118;205;207h\\E)1\\E[1Q\\EW\\E[0!y\\E[0\\0720\\07232!r\\E[w\\E2\\r\\n:\\\n\t:ve=\\E[4l:vs=\\E[4l:tc=avt\ncE|avt|HDS concept avt w/4 or 8 pages, 80 columns:\\\n\t:is=\\E[1*q\\E[2!t\\E[7!t\\E[=4;101;103;119;205l\\E[=107;118;207h\\E)1\\E[1Q\\EW\\E[0!y\\E[0\\0720\\07232!r\\E[w\\E2\\r\\n\\E[*w:\\\n\t:ae=^O:al=\\E[L:am:as=^N:bs:bt=\\E[Z:cd=\\E[J:ce=\\E[K:\\\n\t:ch=\\E[%i%2G:cl=\\E[H\\E[J:cm=\\E[%i%2;%2H:co#80:cv=\\E[%i%2d:\\\n\t:dc=\\E[P:dl=\\E[M:do=\\E[B:ei=\\E1:eo:ho=\\E[H:im=\\E1:kb=^H:kd=\\E[B:\\\n\t:kh=\\E[H:kl=\\E[D:ko=do,ho,nd,up:kr=\\E[C:\\\n\t:ks=\\E[1;4!z\\E[1;8!z\\E[1;10!z\\E[1;11!z\\E[1;12!z\\E[1;14!z\\E[3;7!z\\E[3;9!z:\\\n\t:ke=\\E[;4!z\\E[;8!z\\E[;10!z\\E[;11!z\\E[;12!z\\E[3;14!z\\E[;7!z\\E[;9!z:\\\n\t:ku=\\E[A:li#24:mi:nd=\\E[C:pt:se=\\E[7!{:so=\\E[7m:\\\n\t:te=\\E[w\\E2\\n:ti=\\E[1;24w\\E2\\n:ue=\\E[4!{:\\\n\t:up=\\E[A:us=\\E[4m:ve=\\E[=4;119l:vs=\\E[4l\\E[=119h:xn:\n#\n# Concepts have only window relative cursor addressing, not screen relative.\n# To get it to work right here, ti/te (which were invented for the concept)\n# lock you into a one page window for screen style programs.  To get out of\n# the one page window, we use a clever trick: we set the window size to zero\n# (\"\\Ev    \" in te) which the terminal recognizes as an error and resets the\n# window to all of memory.\n#\n# Some tty drivers use cr3 for concept, others use nl3, hence dN/dC below.\n# This padding is only needed at 9600 baud.\n# 2 nulls padding on te isn't always enough.  6 works fine.  Maybe less\n# than 6 but more than 2 will work.\nca|c100|concept|c1004p|c100-4p|concept100|concept 100:\\\n\t:is=\\EU\\Ef\\E7\\200\\200\\E5\\E8\\200\\200\\El\\ENH\\EK\\E\\200\\Eo&\\200\\Eo\\47\\E\\E^G\\041\\E^HA@ :\\\n\t:ti=\\EU\\Ev  8p\\Ep\\r:te=\\Ev    \\200\\200\\200\\200\\200\\200\\Ep\\r\\n:\\\n\t:al=3*\\E^R:am:le=^H:bs:cd=16*\\E^C:ce=16\\E^U:cl=2*^L:cm=\\Ea%+ %+ :co#80:\\\n\t:dc=16\\E^Q:dl=3*\\E^B:ei=\\E\\200:eo:im=\\E^P:ip=16*:li#24:mi:nd=\\E=:\\\n\t:pt:kb=^h:ta=8\\t:up=\\E;:db:us=\\EG:ue=\\Eg:xn:\\\n\t:vb=\\Ek\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\EK:\\\n\t:.dN#9:dC#9:pb#9600:vt#8:us=\\EG:ue=\\Eg:so=\\EE\\ED:se=\\Ed\\Ee:\\\n\t:mh=\\EE:mr=\\ED:mb=\\EC:mp=\\EI:mk=\\EH:me=\\EN\\200:do=^J:\\\n\t:ks=\\EX:ke=\\Ex:ku=\\E;:kd=\\E<:kl=\\E>:kr=\\E=:kh=\\E?:k1=\\E5:k2=\\E6:k3=\\E7:\ncb|c100-rv-pp|c100-rv-4p-pp|concept100-rv-pp|c100rv4ppp|w/ printer port:\\\n\t:is=\\EU\\Ef\\E7\\200\\200\\E5\\E8\\200\\200\\El\\ENH\\Ek\\E\\200\\Eo&\\200\\Eo\\041\\200\\EQ\"\\EY(^W\\Eo\\47\\E\\E^G\\041\\E^HA@ :\\\n\t:tc=c100-rv:\ncc|c100-rv-na|c100-rv-4p-na|concept100-rv-na|c100rv4pna|c100 with no arrows:\\\n\t:ks@:ke@:tc=c100-rv:\ncd|c100-rv|c100-rv-4p|concept100-rv|c100rv4p|c100rv|c100 rev video:\\\n\t:is=\\EU\\Ef\\E7\\200\\200\\E5\\E8\\200\\200\\El\\ENH\\Ek\\E\\200\\Eo&\\200\\Eo\\47\\E\\E^G\\041\\E^HA@ :\\\n\t:vb=\\EK\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\Ek:\\\n\t:so=\\EE:se=\\Ee:tc=c100:\n# This is useful at 1200 baud.\nce|c100-s|concept-s|concept100-s|slow concept 100:\\\n\t:vb=\\Ek\\200\\EK:pt:dC@:dN@:tc=c100:\ncf|c100-rv-s|concept-rv-s|concept100-rv-s|c100rvs|slow reverse concept 100:\\\n\t:vb=\\EK\\200\\Ek:pt:dC@:dN@:tc=c100-rv:\n# \f# --------------------------------\n#\n# d: DEC (DIGITAL EQUIPMENT CORPORATION)\n#\n# Note that xn glitch in vt100 is not quite the same as concept, since\n# the cursor is left in a different position while in the weird state\n# (concept at beginning of next line, vt100 at end of this line) so\n# all versions of vi before 3.7 don't handle xn right on vt100.\n# I assume you have smooth scroll off or are at a slow enough baud\n# rate that it doesn't matter (1200? or less).  Also this assumes\n# that you set auto-nl to \"on\", if you set it off use vt100-nam below.\n#\n# Since there are two things here called vt100, the installer can make\n# a local decision to make either one standard \"vt100\" by including\n# it in the list of terminals in reorder, since the first vt100 in\n# /etc/termcap is the one that it will find.  The choice is between\n# nam (no automatic margins) and am (automatic margins), as determined\n# by the wrapline switch (group 3 #2).  I presonally recommend turning\n# on the bit and using vt100-am, since having stuff hammer on the right\n# margin is sort of hard to read.  However, the xn glitch does not occur\n# if you turn the bit off.\n#\n# I am unsure about the padding requirements listed here.  I have heard\n# a claim that the vt100 needs no padding.  It's possible that it needs\n# padding only if the xon/xoff switch is off.  For UNIX, this switch\n# should probably be on.\n#\n# The vt100 uses rs and rf rather than is/ct/st because the tab settings\n# are in non-volatile memory and don't need to be reset upon login.\n# You can type \"reset\" to get them set.\ndp|vt100-np|vt100 with no padding (for psl games):\\\n\t:cl=\\E[H\\E[2J:sr=\\EM:cm=\\E[%i%d;%dH:nd=\\E[C:up=\\E[A:\\\n\t:ce=\\E[K:cd=\\E[J:so=\\E[7m:se=\\E[m:us=\\E[4m:ue=\\E[m:\\\n\t:md=\\E[1m:mr=\\E[7m:mb=\\E[5m:me=\\E[m:tc=vt100:\nd0|vt100|vt100-am|vt100am|dec vt100:\\\n\t:do=^J:co#80:li#24:cl=50\\E[;H\\E[2J:sf=2*\\ED:\\\n\t:le=^H:bs:am:cm=5\\E[%i%d;%dH:nd=2\\E[C:up=2\\E[A:\\\n\t:ce=3\\E[K:cd=50\\E[J:so=2\\E[7m:se=2\\E[m:us=2\\E[4m:ue=2\\E[m:\\\n\t:md=2\\E[1m:mr=2\\E[7m:mb=2\\E[5m:me=2\\E[m:is=\\E[1;24r\\E[24;1H:\\\n\t:rf=/usr/share/tabset/vt100:\\\n\t:rs=\\E>\\E[?3l\\E[?4l\\E[?5l\\E[?7h\\E[?8h:ks=\\E[?1h\\E=:ke=\\E[?1l\\E>:\\\n\t:ku=\\EOA:kd=\\EOB:kr=\\EOC:kl=\\EOD:kb=^H:\\\n\t:ho=\\E[H:k1=\\EOP:k2=\\EOQ:k3=\\EOR:k4=\\EOS:pt:sr=2*\\EM:vt#3:xn:\\\n\t:sc=\\E7:rc=\\E8:cs=\\E[%i%d;%dr:\nd1|vt100-nam|vt100nam|vt100 w/no am:\\\n\t:am@:xn@:\\\n\t:is=\\E>\\E[?3l\\E[?4l\\E[?5l\\E[?7l\\E[?8h:ks=\\E[?1h\\E=:ke=\\E[?1l\\E>:\\\n\t:tc=vt100-am:\nd2|gt42|dec gt42:\\\n\t:do=^J:le=^H:bs:co#72:ns:li#40:os:\nd3|vt132|vt132:\\\n\t:al=99\\E[L:dl=99\\E[M:ip=7:dc=7\\E[P:ei=\\E[4l:im=\\E[4h:xn:dN#30:tc=vt100:\nd4|gt40|dec gt40:\\\n\t:do=^J:le=^H:bs:co#72:ns:li#30:os:\nd5|vt50|dec vt50:\\\n\t:do=^J:le=^H:bs:cd=\\EJ:ce=\\EK:cl=\\EH\\EJ:co#80:li#12:nd=\\EC:pt:up=\\EA:\nd6|vt125|vt125-am|DEC vt125:\\\n\t:xn:do=^J:co#80:li#24:cl=50\\E[H\\E[2J:dC=10:dN=10:\\\n\t:le=^H:am:bs:cm=5\\E[%i%d;%dH:nd=2\\E[C:up=2\\E[A:ce=3\\E[K:cd=50\\E[J:\\\n\t:so=2\\E[7m:se=2\\E[m:us=2\\E[4m:ue=2\\E[m:md=2\\E[1m:mr=2\\E[7m:mb=2\\E[5m:\\\n\t:me=2\\E[m:is=\\E[1;24r\\E[24;1H\\E>\\E[?3l\\E[?4l\\E[?5l\\E[?7h\\E[?8h:\\\n\t:ks=\\E[?1h\\E=:ke=\\E[?1l\\E>:if=/usr/share/tabset/vt100:ku=\\EOA:kd=\\EOB:\\\n\t:kr=\\EOC:kl=\\EOD:kb=^H:ho=\\E[H:k1=\\EOP:k2=\\EOQ:k3=\\EOR:k4=\\EOS:\\\n\t:pt:sr=5\\EM:vt#3:sc=\\E7:rc=\\E8:cs=\\E[%i%d;%dr:\nd9|vt125-nam|DEC vt125 no automatic margin:\\\n\t:am@:tc=vt125-am:\n# DEC gigi color graphic terminal, same as vt52\nd7|gigi|dec gigi terminal:\\\n\t:co#80:is=200\\E>\\E[?4l\\E[?5l\\E[?7h\\E[?8h:\\\n\t:li#24:cl=100\\E[;H\\E[2J:bs:cm=50\\E[%i%2;%2H:nd=200\\E[C:up=100\\E[A:\\\n\t:ce=120\\E[K:cd=100\\E[J:so=20\\E[7m:se=20\\E[m:us=20\\E[4m:ue=20\\E[m:\\\n\t:ks=200\\E[?1h\\E=:ke=200\\E[?1l\\E>:\\\n\t:ku=\\EOA:kd=\\EOB:kr=\\EOC:kl=\\EOD:\\\n\t:kh=\\E[H:k1=\\EOP:k2=\\EOQ:k3=\\EOR:k4=\\EOS:pt:sr=200\\EM:\\\n\t:dC=50:dF=200:dN=50:dT=50:\ndI|dw1|decwriter I:\\\n\t:do=^J:le=^H:bs:co#72:hc:os:\n# From tut@Topaz.CC Thu May 12 14:49:02 1983\ndJ|dw3|la120|decwriter III:\\\n\t:bs:kb=^H:co#132:hc:os:pt:\\\n\t:is=\\E(B\\E[20l\\E[w\\E[1;132s\\E[2g\\E[9;17;25;33;41;49;57;65;73;81;89;97;105;113;121;129u\\E[z\\E[66t\\E[1;66r\\E[4g\\E>\\r:\n# From tut@topaz.CC Thu Sep 24 22:10:46 1981\ndf|dw4|decwriter IV:\\\n\t:do=^J:le=^H:bs:co#132:hc:os:am:\\\n\t:pt:is=\\Ec:k0=\\EOP:k1=\\EOQ:k2=\\EOR:k3=\\EOS:kb=^H:\ndh|vt50h|dec vt50h:\\\n\t:do=^J:le=^H:bs:cd=\\EJ:ce=\\EK:cl=\\EH\\EJ:cm=\\EY%+ %+ :\\\n\t:co#80:li#12:nd=\\EC:pt:sr=\\EI:up=\\EA:\ndi|vt100-s|vt100 with status line at top:\\\n\t:li#23:i2=\\E[2;24r\\E[24;1H:cm@:ho=\\E[H^J:cl=50\\E[;H^J\\E[0J:\\\n\t:hs:es:ts=\\E7\\E[1;%dH\\E[1K:fs=\\E8:tc=vt100-am:\ndj|vt100-s-bot|vt100 with status line at bottom:\\\n\t:li#23:i2=\\E[1;23r\\E[23;1H:\\\n\t:hs:es:ts=\\E7\\E[24;%dH\\E[1K:fs=\\E8:tc=vt100-am:\nds|vt100-nav|dec vt100 132 cols 14 lines (w/o advanced video option):\\\n\t:li#14:tc=vt100-w:\ndt|vt100-w|dec vt100 132 cols (w/advanced video):\\\n\t:co#132:li#24:rs=\\E>\\E[?3h\\E[?4l\\E[?5l\\E[?8h:tc=vt100-am:\ndv|vt100-w-nam|dec vt100 132 cols (w/advanced video), no am:\\\n\t:co#132:li#24:rs=\\E>\\E[?3h\\E[?4l\\E[?5l\\E[?8h:vt@:tc=vt100-nam:\nd8|vt102|vt100 w/adv. video:\\\n\t:al=\\E[1L:dl=\\E[1M:im=\\E[4h:ei=\\E[4l:mi:dc=\\E[1P:ku=\\EOA:kd=\\EOB:\\\n\t:kr=\\EOC:kl=\\EOD:k0=\\EOp:k1=\\EOq:k2=\\EOr:k3=\\EOs:k4=\\EOt:k5=\\EOu:\\\n\t:k6=\\EOv:k7=\\EOw:k8=\\EOx:k9=\\EOy:as=\\E(0:ae=\\E(B:am@:xn@:tc=vt100am:\n# (from lai@decwrl) should be a vt102, but have heard enough\n# unsubstantiated complaints to make it an alternate (obsolete) version\ndy|vt102-obs|dec vt102:\\\n\t:do=^J:co#80:li#24:cl=50\\E[;H\\E[2J:\\\n\t:le=^H:bs:cm=5\\E[%i%d;%dH:nd=2\\E[C:up=2\\E[A:\\\n\t:ce=3\\E[K:cd=50\\E[J:so=2\\E[7m:se=2\\E[m:us=2\\E[4m:ue=2\\E[m:\\\n\t:md=2\\E[1m:mr=2\\E[7m:mb=2\\E[5m:me=2\\E[m:is=\\E[1;24r\\E[24;1H:\\\n\t:rs=\\E>\\E[?3l\\E[?4l\\E[?5l\\E[?7h\\E[?8h:ks=\\E[?1h\\E=:ke=\\E[?1l\\E>:\\\n\t:ku=\\EOA:kd=\\EOB:kr=\\EOC:kl=\\EOD:kb=^H:\\\n\t:ho=\\E[H:k1=\\EOP:k2=\\EOQ:k3=\\EOR:k4=\\EOS:pt:sr=5\\EM:vt#3:\\\n\t:sc=\\E7:rc=\\E8:cs=\\E[%i%d;%dr:vs=\\E[?7l:ve=\\E[?7h:\ndw|vt52|dec vt52:\\\n\t:do=^J:le=^H:bs:cd=\\EJ:ce=\\EK:cl=\\EH\\EJ:cm=\\EY%+ %+ :co#80:li#24:\\\n\t:nd=\\EC:pt:sr=\\EI:up=\\EA:ku=\\EA:kd=\\EB:kr=\\EC:kl=\\ED:kb=^H:\n# vt61 created by Roger Sacilotto  Massachusetts Computer Associates, Inc\n# Similar to vt52 but add al and dl\n#\ndq|vt61|dec vt61:\\\n\t:al=\\EPf:dl=\\EPd:tc=vt52:\ndx|dw2|decwriter II:\\\n\t:do=^J:kb=^h:le=^H:bs:co#132:hc:os:\n# DEC PRO-350 console (VT220-style)\ndP|pro350|decpro|dec pro console:\\\n\t:bs:cd=\\EJ:ce=\\EK:cl=\\EH\\EJ:\\\n\t:cm=\\EY%+ %+ :co#80:ho=\\EH:\\\n\t:kl=\\ED:kr=\\EC:ku=\\EA:kd=\\EB:kh=\\EH:\\\n\t:k0=\\EE:k1=\\EF:k2=\\EG:k3=\\EH:k4=\\EI:k5=\\EJ:k6=\\Ei:k7=\\Ej:\\\n\t:li#24:nd=\\EC:pt:sr=\\EI:up=\\EA:do=\\EB:\\\n\t:se=\\E^N:so=\\E^H:us=\\E^D:ue=\\E^C:\\\n\t:ae=\\EG:as=\\EF:\n#\n# From: Bracy H. Elton  <elton@lll-crg>\ndl|vt200|vt220|vt200-js|vt220-js|dec vt200 series with jump scroll:\\\n\t:im=\\E[4h:ei=\\E[4l:mi:dc=\\E[P:dm=:ed=:al=\\E[L:dl=\\E[M:\\\n\t:cs=\\E[%i%d;%dr:sf=\\ED:sr=\\EM:sb=\\EM:\\\n\t:ce=\\E[K:cl=\\E[H\\E[J:cd=\\E[J:cm=\\E[%i%d;%dH:nd=\\E[C:up=\\E[A:\\\n\t:so=\\E[7m:se=\\E[27m:us=\\E[4m:ue=\\E[24m:\\\n\t:md=\\E[1m:mr=\\E[7m:mb=\\E[5m:me=\\E[m:\\\n\t:is=\\E>\\E[?3l\\E[?4l\\E[?5l\\E[?7h\\E[?8h\\E[1;24r\\E[24;1H:\\\n\t:rs=\\E>\\E[?3l\\E[?4l\\E[?5l\\E[?7h\\E[?8h:\\\n\t:tc=vt100:\ndm|vt200-ss|vt220-ss|dec vt200 series with smooth scroll:\\\n\t:is=\\E>\\E[?3l\\E[?4h\\E[?5l\\E[?7h\\E[?8h\\E[1;24r\\E[24;1H:\\\n\t:rs=\\E>\\E[?3l\\E[?4h\\E[?5l\\E[?7h\\E[?8h:\\\n\t:tc=vt200:\ndn|vt200-w|vt220-w|vt200-wj|vt220-wj|dec vt200 series; 132 col.; jump scroll:\\\n\t:is=\\E>\\E[?3h\\E[?4l\\E[?5l\\E[?7h\\E[?8h\\E[1;24r\\E[24;1H:\\\n\t:rs=\\E>\\E[?3h\\E[?4l\\E[?5l\\E[?7h\\E[?8h:\\\n\t:co#132:tc=vt200:\ndo|vt200-ws|vt220-ws|dec vt200 series; 132 col.; smooth scroll:\\\n\t:is=\\E>\\E[?3h\\E[?4h\\E[?5l\\E[?7h\\E[?8h\\E[1;24r\\E[24;1H:\\\n\t:rs=\\E>\\E[?3h\\E[?4h\\E[?5l\\E[?7h\\E[?8h:\\\n\t:co#132:tc=vt200:\ndl|vt300|vt320|vt340|dec vt300 series with jump scroll:\\\n\t:im=\\E[4h:ei=\\E[4l:mi:dc=\\E[P:dm=:ed=:al=\\E[L:\\\n\t:cs=\\E[%i%d;%dr:sf=\\ED:sr=\\EM:sb=\\EM:\\\n\t:ce=\\E[K:cl=\\E[H\\E[J:cd=\\E[J:cm=\\E[%i%d;%dH:nd=\\E[C:up=\\E[A:\\\n\t:so=\\E[7m:se=\\E[27m:us=\\E[4m:ue=\\E[24m:\\\n\t:md=\\E[1m:mr=\\E[7m:mb=\\E[5m:me=\\E[m:\\\n\t:is=\\E>\\E[?3l\\E[?4l\\E[?5l\\E[?7h\\E[?8h\\E[1;24r\\E[24;1H:\\\n\t:rs=\\E>\\E[?3l\\E[?4l\\E[?5l\\E[?7h\\E[?8h:\\\n\t:tc=vt100:\n# @(#)termcap\tX10/6.6\t11/7/86, minus alternate screen, plus :cs\nvs|xterm|vs100|xterm terminal emulator (X window system):\\\n\t:do=^J:le=^H:ho=\\E[H:\\\n\t:co#80:li#65:cl=\\E[H\\E[2J:bs:am:cm=\\E[%i%d;%dH:nd=\\E[C:up=\\E[A:\\\n\t:ce=\\E[K:cd=\\E[J:so=\\E[7m:se=\\E[m:us=\\E[4m:ue=\\E[m:\\\n\t:md=\\E[1m:mr=\\E[7m:me=\\E[m:\\\n\t:ku=\\EOA:kd=\\EOB:kr=\\EOC:kl=\\EOD:kb=^H:\\\n\t:k1=\\EOP:k2=\\EOQ:k3=\\EOR:k4=\\EOS:pt:sf=\\n:sr=\\EM:\\\n\t:al=\\E[L:dl=\\E[M:im=\\E[4h:ei=\\E[4l:mi:dc=\\E[P:\\\n\t:MT:ks=\\E[?1h\\E=:ke=\\E[?1l\\E>:xn:\\\n\t:AL=\\E[%dL:DL=\\E[%dM:IC=\\E[%d@:DC=\\E[%dP:\\\n\t:hs:ts=\\E[?E\\E[?%i%dT:fs=\\E[?F:es:ds=\\E[?E:\\\n\t:is=\\E\\E[m\\E[?7h\\E[?1;4l:cs=\\E[%i%d;%dr:\\\n\t:rs=\\E[r\\E<\\E[m\\E[H\\E[2J\\E[?7h\\E[?1;3;4;6l:\nv2|xterms|vs100s|xterm terminal emulator (small)(X window system):\\\n\t:co#80:li#24:tc=xterm:\n# vs100 emulator using tsim\t(from lai@decwrl)\nvt|vs100t|tsim|vs100-tsim:\\\n\t:bs:cm=\\EM%+ %+ :ho=\\EH:do=^J:up=^K:cl=\\EE:ce=\\EL:cs=\\ES%+ %+ :\\\n\t:so=\\Eh:se=\\Er:us=\\Eu:ue=\\Ev:al=\\EI:Al=\\E+%+ :dl=\\ED:Dl=\\E-%+ :\\\n\t:ic=\\Ei:dc=\\Ed:is=\\ER:rs=\\ER:am:cd=\\EQ:pt:nd=\\En:li#24:co#80:\n# \f# --------------------------------\n#\n# h: HEWLETT PACKARD\n#\n# Note: no \"ho\" on HP's since that homes to top of memory, not screen.\n# Due to severe 2621 braindamage, the only way to get the arrow keys to\n# transmit anything at all is to turn on the function key labels\n# (f1-f8) with ks, and even then the poor user has to hold down shift!\n# The default 2621 turns off the labels except when it has to to enable\n# the function keys.  If your installation prefers labels on all the time,\n# or off all the time (at the \"expense\" of the function keys) move the\n# 2621-nl or 2621-wl labels to the front using reorder.\n# Note: there are newer ROM's for 2621's that allow you to set strap A\n# so the regular arrow keys xmit \\EA, etc, as with the 2645.  However,\n# even with this strap set, the terminal stops xmitting if you reset it,\n# until you unset and reset the strap!  Since there is no way to set/unset\n# the strap with an escape sequence, we don't use it in the default.\n# If you like, you can use 2621-ba (braindamaged arrow keys).\nh1|2621-ba|2621 w/new rom, strap A set:\\\n\t:ks@:ke@:ku=\\EA:kd=\\EB:kl=\\ED:kr=\\EC:kh=\\Eh:tc=hp2621:\n# 2621 with function labels.  Most of the time they are off,\n# but inside vi, the function key labels appear.  You have to\n# hold down shift to get them to xmit.\nh2|2621|hp2621|hp2621a|hp2621p|2621a|2621p|2621-pb|hp2621-fl|hp 2621:\\\n\t:is=\\E&j@\\r:bt=\\Ei:cm=\\E&a%r%dc%dY:dc=2\\EP:ip=2:pb#19200:\\\n\t:so=\\E&dD:se=\\E&d@:us=\\E&dD:ue=\\E&d@:me=\\E&d@:\\\n\t:kh=\\Ep\\r:ku=\\Et\\r:kl=\\Eu\\r:kr=\\Ev\\r:kd=\\Ew\\r:\\\n\t:kn#8:k1=\\Ep\\r:k2=\\Eq\\r:k3=\\Er\\r:k4=\\Es\\r:k5=\\Et\\r:k6=\\Eu\\r:k7=\\Ev\\r:\\\n\t:k8=\\Ew\\r:ks=\\E&jB:ke=\\E&j@:ta=2^I:tc=hp:\n# 2621k45: untested\n# 2622: unsure if this is quite it, have only heard about the terminal.\nh3|2621k45|hp2621k45|k45|2622|hp2622|hp 2621 with 45 keyboard:\\\n\t:kb=^H:ku=\\EA:kd=\\EB:kl=\\ED:kr=\\EC:kh=\\Eh:ks=\\E&s1A:ke=\\E&s0A:tc=2621:\nh4|hp2645|2645|hp45:\\\n\t:mh=\\E&dH:mr=\\E&dB:us=\\E&dD:mb=\\E&dA:me=\\E&d@:\\\n\t:ku=\\EA:kd=\\EB:kl=\\ED:kr=\\EC:kh=\\Eh:ks=\\E&s1A:ke=\\E&s0A:tc=hp:\nh5|hp|hewlett-packard:\\\n\t:ct=\\E3:st=\\E1:do=^J:al=\\EL:am:le=^H:bs:\\\n\t:cd=\\EJ:ce=\\EK:ch=\\E&a%dC:cl=\\EH\\EJ:cm=6\\E&a%r%dc%dY:\\\n\t:co#80:cv=\\E&a%dY:da:db:dc=\\EP:dl=\\EM:ei=\\ER:im=\\EQ:\\\n\t:kb=^H:li#24:mi:nd=\\EC:pt:se=\\E&d@:so=\\E&dJ:\\\n\t:us=\\E&dD:ue=\\E&d@:up=\\EA:xs:vt#6:pb#9600:\n# This entry does not use any of the fancy windowing stuff of the 2621.\n# Indeed, termcap does not yet handle such stuff.  We are looking at it.\nh6|hp2626|hp2626a|hp2626p|2626|2626a|2626p|hp 2626:\\\n\t:dc=2\\EP:ip=2:se=\\E&d@:so=\\E&dB:cd=500\\EJ:\\\n\t:mr=\\E&dB:us=\\E&dD:mb=\\E&dA:mk=\\E&dS:me=\\E&d@:ue=\\E&d@:\\\n\t:kh=\\Eh:ku=\\EA:kl=\\ED:kr=\\EC:kd=\\EB:ks=\\E&s1A:ke=\\E&s0A:\\\n\t:sf=\\ES:ta=2^I:xs:tc=2621:\n# cD is a pain - but it only screws up at 9600 baud.\n# You should use this terminal at 4800 baud or less.\nh8|hp2648|hp2648a|2648a|2648|HP 2648a graphics terminal:\\\n\t:cl=50\\EH\\EJ:cm=20\\E&a%r%dc%dY:dc=7\\EP:ip=5:tc=2645:\n# This terminal should be used at 4800 baud or less.\nh9|hp2645-np|2645 w/no padding:cm=\\E&a%r%dc%dY:tc=hp2645:\n# 2640a doesn't have the Y cursor addressing feature, and C is memory relative\n# instead of screen relative, as we need.\nha|2640|hp2640a|2640a|hp 2640a:\\\n\t:cm@:ks@:ke@:tc=2645:\nhb|2640b|hp2640b|2644a|hp2644a|hp 264x series:\\\n\t:ks@:ke@:tc=2645:\n# 2621 using all 48 lines of memory, only 24 visible at any time.  Untested.\nhl|2621-48|48 line 2621:\\\n\t:li#48:ho=\\EH:cm=\\E&a%r%dc%dR:tc=2621:\n# Hp 110 computer is the same as 2621 except has 16 lines\nhm|hp110|110|hp 110 computer:\\\n\t:li#16:tc=2621:\n# 2621 with no labels ever.  Also prevents vi delays on escape.\nhn|2621-nl|hp2621nl|2621nl|hp2621-nl|hp 2621 with no labels:\\\n\t:ks@:ke@:kh@:ku@:kl@:kr@:kd@:tc=hp2621-fl:\n# Needed for UCB ARPAVAX console, since lsi-11 expands tabs (wrong).\nht|hp2621-nt|2621nt|2621-nt|hp2621nt|hp 2621 w/no tabs:\\\n\t:pt@:tc=hp2621:\n# 2621 with labels on all the time - normal outside vi, function inside vi.\nhw|hp2621wl|2621wl|2621-wl|hp2621-wl|hp 2621 w/labels:\\\n\t:is=\\E&jA\\r:ke=\\E&jA:tc=hp2621-fl:\n# 2392 (from haddix@arpa?)\nhz|2392|hp2392|hp2392a:\\\n\t:bt=\\Ei:ip=2:is=\\E&j@\\E3\\r:if=/usr/share/tabset/stdcrt:\\\n\t:ml=\\El:MT:mu=\\Em:km:\\\n\t:mh=\\E&dH:mr=\\E&dB:us=\\E&dD:mb=\\E&dA:me=\\E&d@:\\\n\t:ku=\\EA:kd=\\EB:kl=\\ED:kr=\\EC:kh=\\Eh:ks=\\E&s1A:ke=\\E&s0A:tc=hp:\n#HP 236 console\n#from ddavis@ic.berkeley.edu\nh7|236|hp236|HP236 internal terminal emulator:\\\n\t:am:bs:li#24:co#80:cl=\\EF:cm=\\EE%+ %+ :\\\n\t:dc=\\EJ:dl=\\EH:ic=\\EI:al=\\EG:up=^K:im=:ei=:\\\n\t:so=\\EBI:se=\\ECI:vs=\\EDB:ve=\\EDE:\n# hp150 from ddavis@ic.berkeley.edu\nh0|150|hp150|hp150a|150a:\\\n\t:is=\\E&s1A\\E&f0a1k2L\\Ep\\r\\E&k0K\\E&f0a2k2L\\Eq\\r\\E&f0a3k2L\\Er\\r\\E&f0a4k2L\\Es\\r\\E&f0a5k2L\\Et\\r\\E&f0a6k2L\\Eu\\r\\E&f0a7k2L\\Ev\\r\\E&f0a8k2L\\Ew\\r\\E&k0D\\E&s0A:\\\n\t:bt=\\Ei:li#24:cm=\\E&a%r%dc%dY:dc=2\\EP:ip=2:pb#19200:so=\\E&dJ:\\\n\t:se=\\E&d@:us=\\E&dD:ue=\\E&d@:me=\\E&d@:kh=\\Eh:ku=\\EA:kl=\\ED:kr=\\EC:\\\n\t:kd=\\EB:kn#8:k1=\\Ep:k2=\\Eq:k3=\\Er:k4=\\Es:k5=\\Et:k6=\\Eu:k7=\\Ev:\\\n\t:k8=\\Ew:ta=2^I:ct=\\E3:st=\\E1:do=^J:al=\\EL:am:le=^H:\\\n\t:bs:cd=\\EJ:ce=\\EK:ch=\\E&a%dC:cl=\\Eh\\EJ:co#80:cv=\\E&a%dY:da:db:dl=\\EM:\\\n\t:ei=\\ER:im=\\EQ:kb=^H:mi:nd=\\EC:pt:up=\\EA:xs:vt#6:sf=\\ES:sr=\\ET:\\\n\t:vs=\\E&s1A:ve=\\E&s0A:ks=\\E&jB\\E&j@:ke=\\E&j@:\n# \f# --------------------------------\n#\n# i: INFOTON (GENERAL TERMINAL)\n#\n# Infoton is now called General Terminal Corp. or some such thing.\n# gt100 sounds like something DEC would come out with.  Lets hope they don't.\ni1|i100|gt100|gt100a|General Terminal 100A (formerly Infoton 100):\\\n\t:do=^J:cl=^L:cd=\\EJ:ce=\\EK:li#24:co#80:\\\n\t:al=\\EL:dl=\\EM:up=\\EA:nd=\\EC:ho=\\EH:cm=\\Ef%r%+ %+ :vb=\\Eb\\Ea:\\\n\t:am:le=^H:bs:so=\\Eb:se=\\Ea:\ni4|i400|400|infoton 400:\\\n\t:do=^J:al=\\E[L:am:le=^H:bs:ce=\\E[N:cl=\\E[2J:cm=%i\\E[%3;%3H:co#80:\\\n\t:dl=\\E[M:li#25:nd=\\E[C:up=\\E[A:im=\\E[4h\\E[2Q:ei=\\E[4l\\E[0Q:\\\n\t:dc=\\E[4h\\E[2Q\\E[P\\E[4l\\E[0Q:\nia|addrinfo:\\\n\t:do=^J:li#24:co#80:cl=^L:ho=^H:nd=^Y:cd=^K:\\\n\t:up=^\\:am:le=^Z:bc=^Z:cm=\\037%+\\377%+\\377:ll=^H^\\:\nik|infotonKAS:\\\n\t:do=^J:am:le=^Z:bc=^Z:cd=^K:cl=^L:co#80:li#24:nd=^Y:up=^\\:ll=^H^\\:\n# \f# --------------------------------\n#\n# k: HEATHKIT (ZENITH)\n#\nkA|h19-a|h19a|heath-ansi|heathkit-a|heathkit h19 ansi mode:\\\n\t:\\\n\t:al=1*\\E[1L:am:le=^H:bs:cd=\\E[J:ce=\\E[K:cl=\\E[2J:cm=\\E[%i%2;%2H:co#80:\\\n\t:dc=\\E[1P:dl=1*\\E[1M:do=\\E[1B:ei=\\E[4l:ho=\\E[H:im=\\E[4h:li#24:mi:\\\n\t:nd=\\E[1C:as=\\E[10m:ae=\\E[11m:ms:pt:se=\\E[0m:so=\\E[7m:up=\\E[1A:\\\n\t:vs=\\E[>4h:ve=\\E[>4l:kb=^h:ku=\\E[1A:kd=\\E[1B:kl=\\E[1D:kr=\\E[1C:\\\n\t:kh=\\E[H:kn#8:k1=\\EOS:k2=\\EOT:k3=\\EOU:k4=\\EOV:k5=\\EOW:l6=blue:\\\n\t:l7=red:l8=white:k6=\\EOP:k7=\\EOQ:k8=\\EOR:\\\n\t:sr=\\EM:is=\\E<\\E[>1;2;3;4;5;6;7;8;9l\\E[0m\\E[11m\\E[?7h:\nkB|h19-bs|h19bs|heathkit w/keypad shifted:\\\n\t:ks=\\Et:ke=\\Eu:tc=h19-b:\n#written by David Shewmake, UCSF Medical Information Science\n#ucbvax!ucsfmis!shewmake\nkC|h29|heath-29|z29|zenith-29:\\\n\t:am:bc=\\ED:bt=\\E-:do=^J:\\\n\t:al=\\EL:le=^H:bs:cd=\\EJ:ce=\\EK:cl=\\EE:cm=\\EY%+ %+ :co#80:dc=\\EN:\\\n\t:dl=1*\\EM:do=\\EB:ei=\\EO:ho=\\EH:im=\\E@:li#24:mi:nd=\\EC:as=\\EF:ae=\\EG:\\\n\t:ms:pt:sr=\\EI:se=\\Eq:so=\\Ep:up=\\EA:vs=\\Ex4:ve=\\Ey4:\\\n\t:kb=^H:ku=\\EA:kd=\\EB:kl=\\ED:kr=\\EC:kh=\\EH:kn#1:k0=\\E~:l0=HOME:\\\n\t:k1=\\ES:k2=\\ET:k3=\\EU:k4=\\EV:k5=\\EW:k6=\\EP:k7=\\EQ:k8=\\ER:k9=\\E0I:\\\n\t:es:hs:ts=\\Ej\\Ex5\\Ex1\\EY8%+ \\Eo:fs=\\Ek\\Ey5:ds=\\Ey1:us=\\Es8:ue=\\Es0:\n#the z29-e entry sucks...but it works with emacs\nkD|z29-e|zenith 29 hacked for emacs:\\\n\t:ip=1.5:ks=\\Et:ke=\\Eu:vs@:ve@:al=1*\\EL:am:le=^H:\\\n\t:bs:cd=\\EJ:ce=\\EK:cl=\\EE:cm=\\EY%+ %+ :co#80:dc=\\EN:dl=1*\\EM:\\\n\t:do=\\EB:ho=\\EH:li#24:nd=\\EC:as=\\EF:ae=\\EG:ms:\\\n\t:pt:sr=\\EI:se=\\Eq:so=\\Ep:up=\\EA:vs=\\Ex4:ve=\\Ey4:kb=^h:\\\n\t:ku=\\EA:kd=\\EB:kl=\\ED:kr=\\EC:kh=\\EH:kn#8:k1=\\ES:k2=\\ET:k3=\\EU:\\\n\t:k4=\\EV:k5=\\EW:l6=blue:l7=red:l8=white:k6=\\EP:k7=\\EQ:k8=\\ER:es:hs:\\\n\t:ts=\\Ej\\Ex5\\Ex1\\EY8%+ \\Eo:fs=\\Ek\\Ey5:ds=\\Ey1:\n# z29 in ansi mode. Assumes that the cursor is in the correct state, and that\n# the world is stable. `rs' causes the terminal to be reset to the state\n# indicated by the name. kc -> key click, nkc -> no key click, uc -> underscore\n# cursor, bc -> block cursor.\n# from Mike Meyers\nkF|z29a|z29a-kc-bc|h29a-kc-bc|heath/zenith 29 in ansi mode:\\\n\t:do=^J:co#80:li#24:cl=\\E[2J:pt:ho=\\E[H:\\\n\t:le=^H:bs:cm=\\E[%i%d;%dH:nd=\\E[C:up=\\E[A:mb=\\E[5m:mr=\\E7m:\\\n\t:ce=\\E[K:cd=\\E[J:so=\\E[7;2m:se=\\E[m:us=\\E[4m:ue=\\E[m:mh=\\E[2m:\\\n\t:md=\\E[2m:mr=\\E[7m:mb=\\E[5m:me=\\E[m:\\\n\t:rs=\\E<\\E[1;24r\\E[24;1H\\E[?7h\\E[>4h\\E[>1;2;3;5;6;7;8;9l\\E[m\\E[11m:\\\n\t:ku=\\EOA:kd=\\EOB:kr=\\EOC:kl=\\EOD:kb=^H:\\\n\t:k1=\\EOS:k2=\\EOT:k3=\\EOU:k4=\\EOV:k5=\\EOW:k6=\\EOP:k7=\\EOQ:k8=\\EOR:\\\n\t:k9=\\EOX:k0=\\E[~:l0=help:kn#2:ko=ho,cd:if=/usr/share/tabset/zenith29:\\\n\t:es:hs:ts=\\E[s\\E[>5;1h\\E[25;%i%dH\\E[1K:fs=\\E[u\\E[>5l:ds=\\E[>1l:\\\n\t:cs=\\E[%i%d;%dr:sr=\\EM:sf=\\ED:DO=\\E[%dB:UP=\\E[%dA:LE=\\E[%dD:\\\n\t:RI=\\E[%dC:AL=\\E[%dL:DL=\\E[%dM:sc=\\E[s:rc=\\E[r:dc=\\E[1P:DC=\\E[%dP:\\\n\t:kC=\\E[J:ct=\\E[3g:st=\\EH:ti=\\E[?7l:te=\\E[?7h:ps=\\E#7:\nkG|z29a-kc-uc|h29a-kc-uc|heath/zenith 29 in ansi mode:\\\n\t:rs=\\E<\\E[1;24r\\E[24;1H\\E[?7h\\E[>1;2;3;4;5;6;7;8;9l\\E[m\\E[11m:\\\n\t:tc=z29a:\nkH|z29a-nkc-bc|h29a-nkc-bc|heath/zenith 29 in ansi mode:\\\n\t:rs=\\E<\\E[1;24r\\E[24;1H\\E[?7h\\E[>2;4h\\E[>1;3;5;6;7;8;9l\\E[m\\E[11m:\\\n\t:tc=z29a:\nkI|z29a-nkc-uc|h29a-nkc-uc|heath/zenith 29 in ansi mode:\\\n\t:rs=\\E<\\E[1;24r\\E[24;1H\\E[?7h\\E[>2h\\E[>1;3;4;5;6;7;8;9l\\E[m\\E[11m:\\\n\t:tc=z29a:\n#z100 entry from Brad Brahms at TRW (Brahms@USC-ECLC)\n#\t\t\t   usenet: {decvax,ucbvax}!trwrb!trwspp!brahms\nkc|z100|h100|z110|z-100|h-100|heath/zenith z-100 pc with color monitor:\\\n\t:vs=\\Ex4\\Em71:ve=\\Ey4\\Em70:tc=z100bw:\nkY|z100bw|h100bw|z110bw|z-100bw|h-100bw|heath/zenith z-100 pc:\\\n\t:al=5*\\EL:bs:cd=\\EJ:ce=\\EK:cl=5*\\EE:cm=1*\\EY%+ %+ :co#80:dc=1*\\EN:\\\n\t:dl=5*\\EM:do=\\EB:ei=\\EO:ho=\\EH:im=\\E@:li#24:mi:nd=\\EC:as=\\EF:ae=\\EG:\\\n\t:ms:pt:sr=\\EI:se=\\Eq:so=\\Ep:up=\\EA:vs=\\Ex4:ve=\\Ey4:\\\n\t:kb=^h:ku=\\EA:kd=\\EB:kl=\\ED:kr=\\EC:kh=\\EH:kn#10:\\\n\t:k0=\\EJ:k1=\\ES:k2=\\ET:k3=\\EU:k4=\\EV:k5=\\EW:\\k6=\\EP:k7=\\EQ:\\\n\t:k8=\\ER:k9=\\EOI:\nkp|p19:\\\n\t:al=2*\\EL:dl=2*\\EM:tc=h19-b:\nkU|h19-us|h19us|heathkit w/keypad shifted/underscore cursor:\\\n\t:ks=\\Et:ke=\\Eu:tc=h19-u:\nkb|h19|heath|h19-b|h19b|heathkit|heath-19|z19|zenith|heathkit h19:\\\n\t:al=1*\\EL:am:le=^H:bs:cd=\\EJ:ce=\\EK:cl=\\EE:cm=\\EY%+ %+ :co#80:dc=\\EN:\\\n\t:dl=1*\\EM:do=\\EB:ei=\\EO:ho=\\EH:im=\\E@:li#24:mi:nd=\\EC:as=\\EF:ae=\\EG:\\\n\t:ms:pt:sr=\\EI:se=\\Eq:so=\\Ep:up=\\EA:vs=\\Ex4:ve=\\Ey4:\\\n\t:kb=^h:ku=\\EA:kd=\\EB:kl=\\ED:kr=\\EC:kh=\\EH:kn#8:ke=\\E>:ks=\\E=:\\\n\t:k1=\\ES:k2=\\ET:k3=\\EU:k4=\\EV:k5=\\EW:\\\n\t:l6=blue:l7=red:l8=white:k6=\\EP:k7=\\EQ:k8=\\ER:\\\n\t:es:hs:ts=\\Ej\\Ex5\\Ex1\\EY8%+ \\Eo:fs=\\Ek\\Ey5:ds=\\Ey1:\nke|h19-e|h19e|h19 for emacs:ip=1.5:tc=h19-us:\nku|h19-u|h19u|heathkit with underscore cursor:\\\n\t:vs@:ve@:tc=h19-b:\nkg|h19-g|h19g|heathkit w/block cursor:\\\n\t:ve=\\Ex4:tc=h19-b:\n# from ucscc!B.fiatlux@ucbvax.berkeley.edu\nzx|ztx|ztx11|zt-1|htx11|ztx-1-a|ztx-10/11:\\\n\t:al=\\EL:am:bs:cd=\\EJ:ce=\\EK:cl=\\EE:cm=\\EY%+ %+ :co#80:\\\n\t:dl=\\EM:do=^J:ho=\\EH:is=\\Ej\\EH\\Eq\\Ek\\Ev\\Ey1\\Ey5\\EG\\Ey8\\Ey9\\Ey>:\\\n\t:k0=\\ES:k1=\\EB:k2=\\EU:k3=\\EV:k4=\\EW:k5=\\EP:k6=\\EQ:k7=\\ER:kb=^H:kd=\\EB:\\\n\t:kl=\\ED:kr=\\EC:ku=\\EA:le=^H:li#24:nd=\\EC:pt:se=\\Eq:so=\\Es5:\\\n\t:sr=\\EI:sr=\\EI:ue=\\Eq:up=\\EA:us=\\Es2:\\\n\t:es:hs:ts=\\Ej\\Ex5\\Ex1\\EY8%+ \\Eo:fs=\\Ek\\Ey5:ds=\\Ey1:\n# \f# --------------------------------\n#\n# l: LEAR SIEGLER (ADM)\n#\n# If the adm31 gives you trouble with standout mode, check the DIP switch\n# in position 6, bank @c11, 25% from back end of pc.  Should be OFF.\n# If there is no such switch, you have an old adm31 and must use oadm31\nl1|adm31|31|lsi adm31:\\\n\t:is=\\Eu\\E0:do=^J:al=\\EE:am:le=^H:bs:ce=\\ET:cm=\\E=%+ %+ :\\\n\t:cl=\\E*:cd=\\EY:co#80:dc=\\EW:dl=\\ER:ei=\\Er:ho=^^:im=\\Eq:\\\n\t:k0=^A0\\r:k1=^A1\\r:k2=^A2\\r:k3=^A3\\r:k4=^A4\\r:\\\n\t:k5=^A5\\r:k6=^A6\\r:k7=^A7\\r:k8=^A8\\r:k9=^A9\\r:kd=^J:kl=^H:kr=^L:ku=^K:\\\n\t:li#24:ma=j^Jk^P^K^Pl ^R^L^L :mi:nd=^L:\\\n\t:se=\\EG0:so=\\EG1:up=^K:us=\\EG1:ue=\\EG0:\nl2|adm2|lsi adm2:\\\n\t:do=^J:al=\\EE:am:le=^H:bs:cd=\\EY:ce=\\ET:cl=\\E;:\\\n\t:cm=\\E=%+ %+ :co#80:dc=\\EW:dl=\\ER:\\\n\t:ei=:ho=^^:ic=\\EQ:im=:kd=^J:kh=^^:kl=^H:kr=^L:ku=^K:li#24:nd=^L:up=^K:\nl3|adm3|3|lsi adm3:\\\n\t:do=^J:am:le=^H:bs:cl=^Z:li#24:ma=^K^P:co#80:\nl4|adm42|42|lsi adm42:\\\n\t:vs=\\EC\\E3 \\E3(:do=^J:al=270\\EE:am:le=^H:bs:cd=\\EY:ce=\\ET:cl=\\E;:\\\n\t:cm=\\E=%+ %+ :co#80:dc=\\EW:dl=\\ER:ei=\\Er:im=\\Eq:ip=6*:li#24:\\\n\t:bt=\\EI:nd=^L:se=\\EG0:so=\\EG4:up=^k:ma=^K^P:pc=\\177:\nl5|adm5|5|lsi adm5:\\\n\t:do=^J:cd=\\EY:ce=\\ET:do=^J:kb=^H:kh=^^:\\\n\t:ma=^Hh^Jj^Kk^Ll^^H:se=\\EG:sg#1:so=\\EG:tc=adm3aplus:\nl7|adm20|lear siegler adm20:\\\n\t:am:li#24:co#80:bs:cl=^Z:cm=\\E=%i%r%+^_%+^_:nd=^L:up=^K:ho=^^:ce=\\ET:\\\n\t:cd=\\EY:al=\\EE:dl=\\ER:im=:ei=:ic=\\EQ:dm=:ed=:dc=\\EW:so=\\E):se=\\E(:\\\n\t:bt=\\EI:pt:kn#7:k1=^A:k2=^B:k3=^W:k4=^D:k5=^E:k6:^X:k7=^Z:\n# From Andrew Scott Beals <bandy@lll-crg.ARPA>\nl8|adm12|12|lsi adm12:\\\n\t:is=\\Eq:do=^J:al=\\EE:am:le=^H:bs:ce=\\ET:cm=\\E=%+ %+ :cl=^Z:cd=\\EY:\\\n\t:co#80:dc=\\EW:dl=\\ER:ei=\\Er:ho=^^:im=\\Eq:\\\n\t:k0=^A0\\r:k1=^A1\\r:k2=^A2\\r:k3=^A3\\r:k4=^A4\\r:\\\n\t:k5=^A5\\r:k6=^A6\\r:k7=^A7\\r:k8=^A8\\r:k9=^A9\\r:kd=^J:kl=^H:kr=^L:ku=^K:\\\n\t:li#24:ma=j^Jk^P^K^Pl ^R^L^L :mi:nd=^L:\\\n\t:se=\\EG0:so=\\EG4:up=^K:us=\\EG1:ue=\\EG0:\nla|adm3a|3a|lsi adm3a:\\\n\t:am:do=^J:le=^H:bs:cm=\\E=%+ %+ :cl=1^Z:co#80:ho=^^:\\\n\t:li#24:ma=^K^P:nd=^L:up=^K:\nlb|adm3a+|3a+|adm3aplus:\\\n\t:kl=^H:kd=^J:ku=^K:kr=^L:tc=adm3a:\nlc|adm22|22|lsi adm22:\\\n\t:is=\\E%\\014\\014\\014\\016\\003\\000\\003\\002\\003\\002\\000\\000\\000\\000\\000\\000\\000\\000\\000\\000\\000:\\\n\t:al=\\EE:am:bs:bt=\\EI:cd=\\Ey:ce=\\Et:cl=\\E+:cm=\\000\\E=%+ %+ :co#80:\\\n\t:dc=\\EW:dl=\\ER:do=^J:em=:ho=^^:ic=\\EQ:im=:\\\n\t:k1=\\001@\\015:k2=\\001A\\015:k3=\\001B\\015:k4=\\001C\\015:\\\n\t:k5=\\001D\\015:k6=\\001E\\015:k7=\\001F\\015:kn#7:\\\n\t:ko=ho:l1=F1:l2=F2:l3=F3:l4=F4:l5=F5:l6=F6:l7=F7:\\\n\t:kb=^H:kd=^J:kh=^^:kl=^H:kr=^L:ku=^K:li#24:\\\n\t:ma=j^Jk^P^K^Pl ^R^L^L :nd=^L:se=\\E(:so=\\E):ta=\\Ei:up=^K:\n#From: stephen%comp.lancs.ac.uk@ucl-cs.arpa\nle|adm11|lsi adm11:\\\n\t:do=^J:bs:\\\n\t:cd=\\EY:ce=\\ET:kb=^H:kh=^^:\\\n\t:ma=^Hh^Jj^Kk^Ll^^H:so=\\E):se=\\E(:\\\n\t:kl=^H:kd=^J:ku=^K:kr=^L:\\\n\t:am:cm=\\E=%+ %+ :cl=^Z:co#80:li#24:nd=^L:up=^K:\\\n\t:hs:ts=\\EF\\E):fs=\\E(^M:ds=\\Eh:\n# \f# --------------------------------\n#\n# m: MICROTERM\n#\n# These mime1 entries refer to the Microterm Mime I or Mime II.\n# The default mime is assumed to be in enhanced act iv mode.\nm3|mime3a|mime1 emulating 3a:\\\n\t:am@:ma=^X ^K^J^Z^P:ku=^Z:kd=^K:kl=^H:kr=^X:tc=adm3a:\nm4|microterm|act4|microterm act iv:\\\n\t:am:do=^J:le=^H:bs:cd=^_:ce=^^:cl=^L:cm=^T%.%.:\\\n\t:co#80:li#24:nd=^X:up=^Z:ho=^]:\n# The padding on sr and ta for act5 and mime is a guess and not final.\n# The act 5 has hardware tabs, but they are in columns 8, 16, 24, 32, 41 (!)...\nm5|microterm5|act5|microterm act v:\\\n\t:uc=^H\\EA:sr=3\\EH:ku=^Z:kd=^K:kl=^H:kr=^X:ma=^Z^P^Xl^Kj:tc=act4:\n# Act V in split screen mode.  act5s is not tested and said not to work.\nmS|act5s|skinny act5:\\\n\t:ti=\\EP:te=\\EQ:li#48:co#39:tc=act5:\n# Mimes using brightness for standout.  Half bright is really dim unless\n# you turn up the brightness so far that lines show up on the screen.\n# uc is disabled to get around a curses bug, should be put back in someday.\nmf|mime-fb|full bright mime1:\\\n\t:so=^Y:se=^S:is=^S\\E:tc=mime:\nmh|mime-hb|half bright mime1:\\\n\t:so=^S:se=^Y:is=^Y\\E:tc=mime:\nmm|mime|mime1|mime2|mimei|mimeii|microterm mime1:\\\n\t:do=^J:al=80^A:am:le=^H:bs:cd=^_:ce=^^:cl=\\035^C:cm=^T%+^X%> 0%+P:\\\n\t:co#80:dl=80^W:ta=2^I:li#24:nd=^X:pt:uc=^U:up=^z:ho=\\035:do=^K:\\\n\t:is=^S\\E^Q:ma=^X ^K^J^Z^P:ku=^Z:kd=^K:kl=^H:kr=^X:sr=3^R:vt#9:\n# These termcaps (for mime 2a) put the terminal in low intensity mode\n# since high intensity mode is so obnoxious.\nms|mime2a-s|microterm mime2a (emulating an enhanced soroc iq120):\\\n\t:do=^J:\\\n\t:al=20*^A:am:le=^H:bs:cd=20*\\EJ:ce=\\EK:cl=\\EL:cm=\\E=%+ %+ :co#80:dc=\\ED:\\\n\t:dl=20*^W:kl=^H:kr=^L:ku=^K:kd=^J:ho=^^:is=\\E):sr=\\EI\\\n\t:im=\\EE:ei=^Z:ip=2:li#24:nd=^L:so=\\E\\072:se=\\E;:up=\\EI:\\\n\t:us=\\E6:ue=\\E7:\n# This is the preferred mode (but ^X can't be used as a kill character)\nmv|mime2a|mime2a-v|microterm mime2a (emulating an enhanced vt52):\\\n\t:do=^J:al=20*^A:le=^H:bs:cd=20*\\EQ:co#80:ce=\\EP:cl=\\EL:cm=\\EY%+ %+ :\\\n\t:is=^Ydc=^N:dl=20*^W:ip=2:ei=^Z:ho=\\EH:im=^O:kd=\\EB:kl=\\ED:kr=\\EC:\\\n\t:ku=\\EA:li#24:nd=\\EC:pt:se=\\E9:so=\\E8:up=\\EA:sr=\\EA:us=\\E4:ue=\\E5:\nmx|mime3ax|mime-3ax|mime1 emulating enhanced 3a:\\\n\t:al=80^A:dl=80^W:pt:ce=^X:cd=^_:tc=mime3a:\n# \f# --------------------------------\n#\n# p: PERKIN ELMER\n#\npe|pe550|bantam|perkin elmer 550:\\\n\t:do=^J:le=^H:bs:co#80:ce=20\\EI:cl=20\\EK:cm=\\EX%+ \\EY%+ :\\\n\t:ho=\\EH:li#24:ll=\\EH\\EA:nd=\\EC:up=\\EA:ma=^Z^P:cd=6^N@^V:\npf|fox|perkin elmer 1100:\\\n\t:ct=\\E3:st=\\E1:do=^J:\\\n\t:am:le=^H:bs:cd=5.5*\\EJ:ce=\\EI:cl=132\\EH\\EJ:co#80:ho=\\EH:li#24:\\\n\t:ll=\\EH\\EA:nd=\\EC:cm=\\EX%+ \\EY%+ :up=\\EA:vb=^P^B^P^C:\npo|owl|perkin elmer 1200:\\\n\t:ct=\\E3:st=\\E1:do=^J:al=5.5*\\EL:am:le=^H:\\\n\t:bs:cd=5.5*\\EJ:ce=5.5\\EI:cl=132\\EH\\EJ:ho=\\EH:ll=\\EH\\EA:\\\n\t:cm=\\EX%+ \\EY%+ :co#80:dc=5.5*\\EO:dl=5.5*\\EM:ei=:ic=\\EN:im=:ip=5.5*:\\\n\t:kb=^h:in:li#24:nd=\\EC:up=\\EA:se?=\\E!\\200:so?=\\E!^H:vb=^P^B^P^C:\\\n\t:k1=\\ERA:k2=\\ERB:k3=\\ERC:k4=\\ERD:k5=\\ERE:k6=\\ERF:\\\n\t:k7=\\ERG:k8=\\ERH:k9=\\ERI:k0=\\ERJ:\n# \f# --------------------------------\n#\n# q: HOME MADE TERMINALS\n#\nqB|bc|bill croft homebrew:\\\n\t:do=^J:am:le=^H:bs:cm=\\E=%+ %+ :cl=^Z:co#96:ho=^^:li#72:\\\n\t:nd=^L:up=^K:vb=:\nqN|nucterm|rayterm|NUC homebrew:\\\n\t:do=^J:am:le=^H:bs:cl=1^L:li#24:co#80:nd=^C:\\\n\t:up=^N:ho=^B:ll=^K:ce=^A:cd=^E:\nqb|ex3000:\\\n\t:do=^J:li#24:co#80:ho=^Q:\nqc|carlock|klc:\\\n\t:do=^J:al=^E:am:bs:ce=^U:cl=100^Z:cm=\\E=%+ %+ :co#80:dc=\\177:dl=^D:\\\n\t:dm=:ed=:ei=^T:ho=^^:im=^T:li#24:nd=^L:se=^V:so=^V:up=^K:vb=\\EV\\EV:\n# uVAX\nqd|qdss|qdcons|qdss glass tty:\\\n\t:am:do=^J:le=^H:bs:cm=\\E=%.%.:cl=1^Z:co#128:li#57::nd=^L:up=^K:\nqe|exidy|exidy2500|exidy sorcerer as dm2500:\\\n\t:do=^J:al=^P^J^X:am:le=^H:bs:ce=^W:cl=^^:cm=^L%r%n%.%.:co#64:\\\n\t:dc=\\b:dl=^P^Z^X:dm=^P:ed=^X:ei=^X:ho=^B:ic=^\\:\\\n\t:im=^P:li#30:nd=^\\:pt:so=^N:se=^X:up=^Z:\nqn|netx|netronics:\\\n\t:do=^J:le=^H:bs:cd=2000^F^E:ce=1600^E:cl=466^L:cm=\\E=%+@%+@:\\\n\t:co#64:ho=^D:li#16:ma=j^Jk^Pl :nd=\\E+@A:pc=\\200:sr=\\E=@@^K:up=^K:\n# This came from the comp ctr who got it from some user.  Smart indeed!\nqs|sexidy|exidy smart:\\\n\t:do=^J:li#24:co#64:cl=^l:ho=^q:nd=^s:\\\n\t:up=^w:le=^H:bs:le=^a:bc=^a:ma=^x^J:kd=^S:\nqu|ubell|ubellchar:\\\n\t:if=/usr/share/tabset/ubell:do=^J:am:le=^H:bs:pt:ce=\\Ed:cl=^Z:\\\n\t:cm=\\E=%+ %+ :co#80:li#24:nd=^L:up=^K:ma=j^Jk^P^K^Pl :ho=^^:\nqw|ttyWilliams:\\\n\t:do=^J:co#80:li#12:le=^Y:bc=^Y:do=^K:up=^Z:cl=^^:ce=^_:am:ho=^]:nd=^X:\nqx|xitex|xitex sct-100:\\\n\t:do=^J:le=^H:bs:cd=2000^F^E:ce=1600^E:cl=400^L:cm=\\E=%+@%+@:co#64:\\\n\t:ho=^D:li#16:ma=j^Jk^Pl :nd=\\E+@A:pc=\\200:sr=\\E=@@^K:up=^K:\n# \f# --------------------------------\n#\n# s: SPECIALS\n#\n# Special \"terminals\".  These are used to label tty lines when you don't\n# know what kind of terminal is on it.  The characteristics of an unknown\n# terminal are the lowest common denominator - they look about like a ti 700.\nsa|network:\\\n\t:tc=unknown:\nsb|arpanet:\\\n\t:tc=unknown:\nsc|bussiplexer:\\\n\t:tc=unknown:\nsd|du|dialup:\\\n\t:tc=unknown:\nse|ethernet:\\\n\t:tc=unknown:\nsl|lpr|printer|print|printing|line printer:\\\n\t:do=^J:le=^H:bs:co#132:hc:os:\nsp|plugboard|patch|patchboard:\\\n\t:tc=unknown:\nsu|dumb|un|unknown:\\\n\t:am:co#80:do=^J:\nsw|switch|intelligent switch:\\\n\t:tc=unknown:\nsx|ansi|any ansi terminal with pessimistic assumptions:\\\n\t:co#80:li#24:cl=50\\E[;H\\E[2J:bs:am:cm=\\E[%i%d;%dH:\\\n\t:nd=\\E[C:up=\\E[A:ce=\\E[K:ho=\\E[H:pt:\n# \f# --------------------------------\n#\n# t: TEXAS INSTRUMENTS\n#\nt3|ti|ti700|ti733|735|ti735|ti silent 700:\\\n\t:do=^J:le=^H:bs:co#80:hc:os:dC#162:\nt4|ti745|745|743|ti silent 745:\\\n\t:do=^J:le=^H:bs:co#80:hc:os:\nt8|ti800|ti omni 800:\\\n\t:do=^J:le=^H:bs:co#132:hc:os:\n# From lesleymw@topaz.berkeley.edu\nt9|ti931|ti 931:\\\n\tal=\\EN:am:bs:cd=\\EJ:ce=\\EI:cl=\\EL:cm=\\EY%+ %+ :co=#80:dl=\\EO:do=\\EB:\\\n\teo:ho=\\EH:li=#24:ku=\\EA:kd=\\EB:kr=\\EC:kl=\\ED:mi:nd:sf=\\Eb:sr=\\Ea:up=\\EA:\n# \f# --------------------------------\n#\n# v: TELEVIDEO\n#\n# There are some tvi's that require incredible amounts of padding and\n# some that don't.  I'm assuming 912 and 920 are the old slow ones,\n# and 912b, 912c, 920b, 920c are the new ones that don't need padding.\nv1|tvi912|912|920|tvi920|old televideo:\\\n\t:ct=\\E3:st=\\E1:do=^J:\\\n\t:al=33*\\EE:le=^H:ce=\\ET:cm=\\E=%+ %+ :cl=^Z:co#80:dc=\\EW:dl=33*\\ER:ei=:\\\n\t:kb=^H:ku=^K:kd=^J:kl=^H:kr=^L:k0=^AI\\r:k1=^A@\\r:k2=^AA\\r:k3=^AB\\r:\\\n\t:bs:am:k4=^AC\\r:k5=^AD\\r:k6=^AE\\r:k7=^AF\\r:k8=^AG\\r:k9=^AH\\r:\\\n\t:ho=^^:im=:ic=\\EQ:li#24:nd=^L:pt:se=\\Ek:so=\\Ej:up=^K:us=\\El:ue=\\Em:\\\n\t:ma=^K^P^L :sg#1:ug#1:if=/usr/share/tabset/stdcrt\n# the 912 has a <funct> key that's like shift: <funct>8 xmits \"^A8\\r\".\n# The 920 has this plus real function keys that xmit different things.\n# Termcap makes you use the funct key on the 912 but the real keys on the 920.\nv2|912b|912c|tvi912b|tvi912c|tvi|new televideo 912:\\\n\t:al=5*\\EE:dl=5*\\ER:tc=tvi912:\nv3|920b|920c|tvi920b|tvi920c|new televideo 920:\\\n\t:k0=^AI\\r:k1=^A@\\r:k2=^AA\\r:k3=^AB\\r:k4=^AC\\r:k5=^AD\\r:\\\n\t:k6=^AE\\r:k7=^AF\\r:k8=^AG\\r:k9=^AH\\r:al=5*\\EE:dl=5*\\ER:tc=tvi912:\n# set to page 1 when entering ex (\\E-17 )\n# reset to page 0 when exiting ex (\\E-07 )\nv4|tvi912-2p|tvi920-2p|912-2p|920-2p|tvi-2p|televideo w/2 pages:\\\n\t:ti=\\E-17 :te=\\E-07 :tc=tvi912:\nv5|tvi950-ap|tvi 950 w/alt pages:\\\n\t:is=\\E\\\\1:ti=\\E-06 :te=\\E-16 :tc=tvi950:\nv6|tvi950-b|bare tvi950 no is:\\\n\t:is@:tc=tvi950:\nv7|tvi950-ns|tvi950 w/no standout:\\\n\t:so@:se@:us@:ue@:tc=tvi950:\nvi|tvi925|925|televideo model 925:\\\n\t:hs:xn:am:bs:co#80:li#24:cm=\\E=%+ %+ :cl=\\E*:cd=\\Ey:ce=\\Et:is=\\El\\E\":\\\n\t:al=\\EE:dl=\\ER:im=:ei=:ic=\\EQ:dc=\\EW:if=/usr/share/tabset/stdcrt:\\\n\t:ho=^^:nd=^L:bt=\\EI:pt:so=\\EG4:se=\\EG0:sg#1:us=\\EG8:ue=\\EG0:ug#1:\\\n\t:up=^K:do=^V:kb=^H:ku=^K:kd=^V:kl=^H:kr=^L:kh=^^:ma=^V^J^L :\\\n\t:k1=^A@\\r:k2=^AA\\r:k3=^AB\\r:k4=^AC\\r:k5=^AD\\r:k6=^AE\\r:k7=^AF\\r:\\\n\t:k8=^AG\\r:k9=^AH\\r:k0=^AI\\r:ko=ic,dc,al,dl,cl,ce,cd,bt:\\\n\t:ts=\\Ef:fs=^M\\Eg:ds=\\Eh:sr=\\Ej:\nvj|tvi925vb|925vb|televideo model 925 visual bells:\\\n\t:vb=\\Eb\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\Ed:\\\n\t:tc=tvi925:\n# Since the 925's uses a character position to store the escape sequences to go\n# in and out of both stand out and underline modes, screen positioning is\n# difficult.  The following 925 entries don't use these modes.\nvn|tvi925n|925n|televideo model 925 no standout or underline:\\\n\t:so@:se@:us@:ue@:tc=tvi925:\nvk|tvi925vbn|925vbn|televideo model 925 visual bells no so or ul:\\\n\t:vb=\\Eb\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\Ed:\\\n\t:tc=tvi925n:\n# entry by Tim Curry 5/21/82 Univ. of Central Fla. duke!ucf-cs!tim\nv9|925a|tvi925a|TeleVideo Model 925:\\\n\t:al=\\EE:am:bs:bt=\\EI:bw:cd=\\EY:ce=\\ET:cl=^Z:cm=\\E=%+ %+ :co#80:dc=\\EW:\\\n\t:dl=\\ER:do=^V:ei=:ic=\\EQ:if=/usr/share/tabset/std:im=:kb=^H:kd=^V:\\\n\t:kh=^^:kl=^H:kn#12:kr=^L:ku=^K:li#24:nd=^L:pt:se=\\EG0:sg=#1:so=\\EG4:\\\n\t:ue=\\EG0:ug#1:up=^K:us=\\EG8:is=\\El\\\n\t:vb=\\Eb\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\Ed:\\\n\t:ve=\\E.4:vs=\\E.2:\n# The following tvi descriptions from B:pjphar and virus!mike\n# is for all 950's.  It sets the following attributes:\n# full duplex (\\EDF)\t\twrite protect off (\\E()\n# conversation mode (\\EC)\tgraphics mode off (\\E%)\n# white on black (\\Ed)\t\tauto page flip off (\\Ew)\n# turn off status line (\\Eg)\tclear status line (\\Ef\\r)\n# normal video (\\E0)\t\tmonitor mode off (\\EX or \\Eu)\n# edit mode (\\Er)\t\tload blank char to space (\\Ee\\040)\n# line edit mode (\\EO)\t\tenable buffer control (^O)\n# protect mode off (\\E\\047)\tduplex edit keys (\\El)\n# program unshifted send key to send line all (\\E016)\n# program shifted send key to send line unprotected (\\E004)\n# set the following to nulls:\n#\tfield delimiter (\\Ex0\\200\\200)\n#\tline delimiter (\\Ex1\\200\\200)\n#\tstart-protected field delimiter (\\Ex2\\200\\200)\n#\tend-protected field delimiter (\\Ex3\\200\\200)\n# set end of text delimiter to carriage return/null (\\Ex4\\r\\200)\n# CHANGED 4-29-87 to set tabs and keep status line --John Kunze (jak@opal)\nva|tvi950|950|televideo950:\\\n\t:ct=\\E3:st=\\E1:do=^J:\\\n\t:is=\\EDF\\EC\\Ed\\EG0\\Er\\EO\\E\\047\\E(\\E%\\Ew\\EX\\Ee ^O\\\n\t\\El\\E016\\E004\\Ex0\\200\\200\\Ex1\\200\\200\\Ex2\\200\\200\\\n\t\\Ex3\\200\\200\\Ex4\\r\\200\\Ef\\r:if=/usr/share/tabset/stdcrt:\\\n\t:al=\\EE:am:le=^H:bs:bt=\\EI:cd=\\Ey:ce=\\Et:cl=\\E*:cm=\\E=%+ %+ :\\\n\t:co#80:dc=\\EW:dl=\\ER:do=^V:ei=\\Er:ho=^^:im=\\Eq:k0=^A0\\r:\\\n\t:k1=^A@\\r:k2=^AA\\r:k3=^AB\\r:k4=^AC\\r:k5=^AD\\r:k6=^AE\\r:\\\n\t:k7=^AF\\r:k8=^AG\\r:k9=^AH\\r:kb=^H:kd=^V:kh=^^:kl=^H:\\\n\t:ko=ic\\054dc\\054al\\054dl\\054cl\\054bt\\054ce\\054cd:kr=^L:\\\n\t:ku=^K:li#24:ma=^Vj^Kk^Hh^Ll^^H:mi:ms:nd=^L:pt:se=\\EG0:\\\n\t:sg#1:so=\\EG4:sr=\\Ej:ue=\\EG0:ug#1:up=^K:us=\\EG8:\\\n\t:vb=\\Eb\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\Ed:\\\n\t:xn:hs:ts=\\Eg\\Ef:fs=\\r:ds=\\Eg\\Ef\\r:\n#\n# is for 950 with two pages adds the following:\n#\tset 48 line page (\\E\\\\2)\n#\tplace cursor at page 0, line 24, column 1 (\\E-07 )\n#\tset local (no send) edit keys (\\Ek)\n#\n# two page 950 adds the following:\n#\twhen entering ex, set 24 line page (\\E\\\\1)\n#\twhen exiting ex, reset 48 line page (\\E\\\\2)\n#\t\t\t place cursor at 0,24,1 (\\E-07 )\n#\tset duplex (send) edit keys (\\El) when entering vi\n#\tset local (no send) edit keys (\\Ek) when exiting vi\n#\nvb|tvi950-2p|950-2p|televideo950 w/2 pages:\\\n\t:is=\\EDF\\EC\\Ed\\EG0\\Eg\\Er\\EO\\E\\047\\E(\\E%\\Ew\\EX\\Ee ^O\\\n\t\\Ek\\E016\\E004\\Ex0\\200\\200\\Ex1\\200\\200\\Ex2\\200\\200\\\n\t\\Ex3\\200\\200\\Ex4\\r\\200\\E\\\\2\\E-07 \\\n\t:te=\\E\\\\2\\E-07 :ti=\\E\\\\1\\E-07 :ks=\\El:ke=\\Ek:tc=tvi950:\n#\n# is for 950 with four pages adds the following:\n#\tset 96 line page (\\E\\\\3)\n#\tplace cursor at page 0, line 24, column 1 (\\E-07 )\n#\n# four page 950 adds the following:\n#\twhen entering ex, set 24 line page (\\E\\\\1)\n#\twhen exiting ex, reset 96 line page (\\E\\\\3)\n#\t\t\t place cursor at 0,24,1 (\\E-07 )\n#\nvc|tvi950-4p|950-4p|televideo950 w/4 pages:\\\n\t:is=\\EDF\\EC\\Ed\\EG0\\Eg\\Er\\EO\\E\\047\\E(\\E%\\Ew\\EX\\Ee ^O\\\n\t\\Ek\\E016\\E004\\Ex0\\200\\200\\Ex1\\200\\200\\Ex2\\200\\200\\\n\t\\Ex3\\200\\200\\Ex4\\r\\200\\E\\\\3\\E-07 \\\n\t:te=\\E\\\\3\\E-07 :ti=\\E\\\\1\\E-07 :ks=\\El:ke=\\Ek:tc=tvi950:\n#\n# is for reverse video 950 changes the following:\n#\tset reverse video (\\Ed)\n#\n# set vb accordingly (\\Ed ...nulls... \\Eb)\n#\nvd|tvi950-rv|950-rv|televideo950 rev video:\\\n\t:is=\\EDF\\EC\\Eb\\EG0\\Eg\\Er\\EO\\E\\047\\E(\\E%\\Ew\\EX\\Ee ^O\\\n\t\\El\\E016\\E004\\Ex0\\200\\200\\Ex1\\200\\200\\Ex2\\200\\200\\\n\t\\Ex3\\200\\200\\Ex4\\r\\200:\\\n\t:vb=\\Ed\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\Eb:\\\n\t:tc=tvi950:\n#\n# uses the appropriate entries from 950-2p and 950-rv\n#\nve|tvi950-rv-2p|950-rv-2p|televideo950 rev video w/2 pages:\\\n\t:is=\\EDF\\EC\\Eb\\EG0\\Eg\\Er\\EO\\E\\047\\E(\\E%\\Ew\\EX\\Ee ^O\\\n\t\\Ek\\E016\\E004\\Ex0\\200\\200\\Ex1\\200\\200\\Ex2\\200\\200\\\n\t\\Ex3\\200\\200\\Ex4\\r\\200\\E\\\\2\\E-07 :\\\n\t:vb=\\Ed\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\Eb:\\\n\t:te=\\E\\\\2\\E-07 :ti=\\E\\\\1\\E-07 :ks=\\El:ke=\\Ek:tc=tvi950:\n#\n# uses the appropriate entries from 950-4p and 950-rv\n#\nvf|tvi950-rv-4p|950-rv-4p|televideo950 rev video w/4 pages:\\\n\t:is=\\EDF\\EC\\Eb\\EG0\\Er\\EO\\E\\047\\E(\\E%\\Ew\\EX\\Ee ^O\\\n\t\\Ek\\E016\\E004\\Ex0\\200\\200\\Ex1\\200\\200\\Ex2\\200\\200\\\n\t\\Ex3\\200\\200\\Ex4\\r\\200\\E\\\\3\\E-07 :\\\n\t:vb=\\Ed\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\Eb:\\\n\t:te=\\E\\\\3\\E-07 :ti=\\E\\\\1\\E-07 :ks=\\El:ke=\\Ek:tc=tvi950:\nvg|tvi924|924|televideo model 924:\\\n\t:am:bs:xn:co#80:li#24:cm=\\E=%+ %+ :cl=\\E*0:cd=\\Ey:ce=\\Et:is=\\Ek0\\E\"^O:\\\n\t:al=\\EE:dl=\\ER:im=:ei=:ic=\\EQ:dc=\\EW:if=/usr/share/tabset/stdcrt:ho=^^:\\\n\t:nd=^L:bt=\\EI:pt:so=\\EG4:se=\\EG0:us=\\EG8:ue=\\EG0:up=^K:do=^V:kb=^H:\\\n\t:ku=^K:kd=^V:kl=^H:kr=^L:kh=^^:ma=^Vj^Kk^Ll^^H^R^L:k1=^A@\\r:k2=^AA\\r:\\\n\t:k3=^AB\\r:k4=^AC\\r:k5=^AD\\r:k6=^AE\\r:k7=^AF\\r:k8=^AG\\r:k9=^AH\\r:\\\n\t:k0=^AI\\r:ko=ic,dc,al,dl,cl,ce,cd,bt:sr=\\Ej:\\\n\t:hs:fs=^Y\\Es1:ts=\\Ef:ds=\\Es0\\Ef^Y:\nvo|tvi924vb|924vb|televideo model 924 visual bells:\\\n\t:vb=\\Eb\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\Ed:\\\n\t:tc=tvi924:\n# tvipt termcap from armsis@amber (Gene Rochlin), 9/19/84.  Works with vi and\n# rogue.  NOTE: Esc v sets autowrap on, Esc u sets 80 char/line (rather than\n# 40), Esc K chooses the normal character set.  Not sure padding is needed, but\n# adapted from the tvi920c termcap.  so and us are klutzy, but at least use no\n# screen space.\nvp|tvipt|televideopt:if=/usr/share/tabset/stdcrt:\\\n\t:is=\\Ev\\Eu\\EK:al=5*\\EE:am:bs:bt=\\EI:ce=\\ET:cm=\\E=%+ %+ :cl=^Z:co#80:\\\n\t:dl=5*\\ER:kb=^H:ku=^K:kd=^J:kl=^H:kr=^L:ho=^^:li#24:nd=^L:se=\\EF:\\\n\t:so=\\EG1@A\\EH:ue=\\EF:us=\\EG1B@\\EH:up=^K:ma=^Kk^Ll^R^L:\n# Vanilla tvi910 -- W. Gish (cswarren@violet) 10/29/86\nvm|tvi910|910|televideo model 910:if=/usr/share/tabset/stdcrt:\\\n\t:bs:bt=\\EI:cd=\\EY:ce=\\ET:cm=\\E=%+ %+ :cl=^Z:co#80:\\\n\t:kb=^H:ku=^K:kd=^J:kl=^H:kr=^L:k1=^A@\\r:k2=^AA\\r:k3=^AB\\r:k4=^AC\\r:\\\n\t:k5=^AD\\r:k6=^AE\\r:k7=^AF\\r:k8=^AG\\r:k9=^AH\\r:k0=^AI\\r:\\\n\t:li#24:nd=^L:pt:se=\\EG0:so=\\EG4:up=^K:us=\\EG8:ue=\\EG0:\\\n\t:ho=\\E=\\001\\001:ma=^Kk^Ll^R^L:sg#1:\n# from Alan R. Rogers (rogers%albany@csnet-relay)\nvh|tvi910+|910+|televideo 910+:\\\n\t:al=5*\\EE:am:bs:bt=\\EI:cd=\\EY:ce=\\ET:cl=^Z:cm=\\E=%+\\040%+\\040:\\\n\t:co#80:dc=\\EW:dl=\\ER:do=^J:ei=:ho=^^:ic=\\EQ:\\\n\t:if=/usr/share/tabset/stdcrt:im=:k0=^A@\\r:k1=^AA\\r:k2=^AB\\r:k3=^AC\\r:\\\n\t:k4=^AD\\r:k5=^AE\\r:k6=^AF\\r:k7=^AG\\r:k8=^AH\\r:k9=^AI\\r:kb=^H:\\\n\t:kd=^J:kh=^^:kl=^H:kr=^L:ku=^K:li#24:ll=\\E=7\\040:ma=^K^P^L\\040:\\\n\t:nd=^L:pt:se=\\EG0:sg#1:so=\\EG4:ue=\\EG0:up=^K:us=\\EG8:xn:\n# From fair@ucbarpa  Sun Oct 27 07:21:05 1985\nv6|ims950-b|bare ims950 no is:\\\n\t:is@:tc=ims950:\nv7|ims950-ns|ims950 w/no standout:\\\n\t:so@:se@:us@:ue@:tc=ims950:\nva|ims950|ims televideo 950 emulation:\\\n\t:k0@:k1@:k2@:k3@:k4@:k5@:k6@:k7@:k8@:k9@:kb@:kd@:kh@:kl@:ko@:kr@:ku@:\\\n\t:vb@:xn@:tc=tvi950:\nvd|ims950-rv|ims tvi950 rev video:\\\n\t:k0@:k1@:k2@:k3@:k4@:k5@:k6@:k7@:k8@:k9@:kb@:kd@:kh@:kl@:ko@:kr@:ku@:\\\n\t:vb@:xn@:tc=tvi950-rv:\nvx|ims-ansi|ultima2|ultimaII|IMS Ultima II:\\\n\t:pt:am:bs:co#80:li#24:\\\n\t:is=\\E[0m\\E[>14l\\E[?1;?5;20l\\E>\\E[1m^M:if=/usr/share/tabset/vt100:\\\n\t:cl=\\E[;H\\E[2J:cd=\\E[0J:ce=\\E[0K:cm=\\E[%i%2;%2H:up=\\EM:do=\\ED:\\\n\t:ku=\\E[A:kd=\\E[B:kr=\\E[C:kl=\\E[D:kh=\\E[H:\\\n\t:so=\\E[7m:se=\\E[0m\\E[1m:us=\\E[4m:ue=\\E[0m\\E[1m:sr=\\EM:\n# \f# --------------------------------\n#\n# y: TELERAY\n#\n# Note two things called \"teleray\".  Reorder should move the common one\n# to the front if you have either.  A dumb teleray with the cursor stuck\n# on the bottom and no obvious model number is probably a 3700.\ny1|t3700|teleray|dumb teleray 3700:\\\n\t:do=^J:le=^H:bs:cl=^L:co#80:li#24:\ny3|t3800|teleray 3800 series:\\\n\t:do=^J:le=^H:bs:cd=\\EJ:ce=\\EK:cl=^L:cm=\\EY%+ %+ :co#80: \\\n\t:do=\\n:ho=\\EH:li#24:ll=\\EY7 :nd=\\EC:pt:up=^K:\ny6|t1061|teleray 1061:\\\n\t:if=/usr/share/tabset/teleray:\\\n\t:ct=\\EG:st=\\EF:do=^J:\\\n\t:al=2*\\EL:am:le=^H:bs:cd=1\\EJ:ce=\\EK:cl=1^L:cm=\\EY%+ %+ :co#80:\\\n\t:dc=\\EQ:dl=2*\\EM:ei=:ho=\\EH:ic=\\EP:im=:ip=0.4*:\\\n\t:k1=^Z1:k2=^Z2:k3=^Z3:k4=^Z4:k5=^Z5:k6=^Z6:k7=^Z7:k8=^Z8:\\\n\t:li#24:nd=\\EC:pt:se=\\ER@:so= \\ERD:\\\n\t:is=\\Ee\\EU01^Z1\\EV\\EU02^Z2\\EV\\EU03^Z3\\EV\\EU04^Z4\\EV\\EU05^Z5\\EV\\EU06^Z6\\EV\\EU07^Z7\\EV\\EU08^Z8\\EV\\Ef:\\\n\t:up=\\EA:us=\\ERH:ue=\\ER@:xs:xt:sg#2:ug#1:\n# \"Teleray Arpa Special\", offically designated as\n# \"Teleray Arpa network model 10\" with \"Special feature 720\".\n# This is the new (1981) fast microcode updating the older \"arpa\" proms\n# (which gave meta-key and pgmmable-fxn keys).  720 is much much faster,\n# converts the keypad to programmable function keys, and has other goodies.\n# Standout mode is still broken (magic cookie, etc) so is suppressed as no\n# programs handle such lossage properly.\n# Note: this is NOT the old termcap's \"t1061f with fast proms.\"\n# From Univ of Utah, J.Lepreau  Tue Feb  1 06:39:37 1983\n# lepreau@utah-cs, harpo!utah-cs!lepreau\n#\ny7|t10|teleray 10 special:\\\n\t:so@:se@:us@:ue@:\\\n\t:al=\\EL:bs:cd=\\EJ:ce=\\EK:cl=30\\Ej:cm=\\EY%+ %+ :co#80:\\\n\t:dc=\\EQ:dl=\\EM:ei=:ho=\\EH:ic=\\EP:im=:km:li#24:nd=\\EC:pc=\\200:pt:\\\n\t:se=\\ER@:so=\\ERD:sf=\\Eq:sg#2:sr=\\Ep:up=\\EA:ug#1:ue=\\ER@:us=\\ERH:\\\n\t:xs:xt:\nyf|t1061f|teleray 1061 with fast PROMs:\\\n\t:al=\\EL:ip@:dl=\\EM:tc=t1061:\n# Wyse 50 entry by Toni Guttman extended by Jeff Anton\nye|w50|wyse50|Wyse 50:\\\n\t:al=\\EE:am:bs:bt=\\EI:cd=\\EY:ce=\\ET:cl=^Z:cm=\\E=%+ %+ :co#80:\\\n\t:dc=\\EW:dl=\\ER:do=^J:ei=\\Er:im=\\Eq:is=\\E`\\072\\200\\EC\\EDF\\E0\\E'\\E(\\EA21:\\\n\t:kd=^J:kl=^H:kr=^L:ku=^K:li#24:nd=^L:up=^K:us=\\EG8:ue=\\EG0:\\\n\t:so=\\EG4:se=\\EG0:sg#1:sr=\\Ej:ho=^^:ug#1:\n# it is not known if the status line works with sysline\nyh|w50-s|wyse50-s|Wyse 50 for sysline:\\\n\t:hs:ts=\\Ef:fs=\\r:ds=\\Ef\\r:es:tc=w50:\nyg|w50-w|w50-132|wyse50-132|Wyse 50-132:\\\n\t:cm=\\Ea%i%dR%dC:co#132:is=\\E`;\\200\\EC\\EDF\\E0\\E'\\E(\\EA21:tc=w50:\nw6|w60|wyse60|Wyse 60 in native mode:\\\n\t:ae=\\EcD:al=\\EE:am:as=\\EcE:bs:bt=\\EI:bw:cd=\\Ey:ce=\\Et:\\\n\t:cl=^Z:cm=\\E=%+\\040%+\\040:co#80:ct=\\E0:dc=\\EW:dl=\\ER:do=^J:\\\n\t:ei=\\Er:im=\\Eq:is=:kb=^?:kd=^N:ke=\\E~2:kl=^B:kr=^F:ks=\\E~3:ku=^P:\\\n\t:le=^H:li#43:ll=^^^K:mb=\\EG2:me=\\EG0:mh=\\EGp:mi:mr=\\EG4:ms:\\\n\t:nd=^L:pt:se=\\EG0:sf=\\n:so=\\EG4:sr=\\Ej:ue=\\EG0:up=^K:us=\\EG8:\n# from John Gillmore hoptoad!gnu@lll-crg.arpa\nwv|wyse-vp|wyse|Wyse 50 in ADDS Viewpoint emulation mode with \"enhance\" on:\\\n\t:am:do=^J:if=/usr/share/tabset/wyse-adds:\\\n\t:le=^H:bs:li#24:co#80:cm=\\EY%+ %+ :cd=\\Ek:ce=\\EK:nd=^F:\\\n\t:up=^Z:cl=^L:ho=^A:ll=^A^Z:kl=^U:kr=^F:kd=^J:ku=^Z:kh=^A:\\\n\t:pt:so=^N:se=^O:us=^N:ue=^O:dl=\\El:al=\\EM:im=\\Eq:ei=\\Er:dc=\\EW:\\\n\t:is=\\E`\\072\\E`9^O\\Er:rs=\\E`\\072\\E`9^O\\Er:\nwk|wyse-vp-nk|Wyse 50 in ADDS Viewpoint enhanced mode with cursor keys gone:\\\n\t:kl@:kr@:kd@:ku@:kh@:tc=wyse-vp:\nvw|wyse925|Wyse-50 emulating tvi925:\\\n\t:xn@:tc=tvi925:\n# wyse 75 series from JLarson.pa@xerox.arpa\nwx|wyse75|wy75|wyse 75 terminal :\\\n\t:co#80:li#24:cl=50\\E[H\\E[2J:bs:cm=5\\E[%i%d;%dH:nd=\\E[C:up=\\E[A:\\\n\t:al=3\\E[L:dl=3\\E[M:ku=\\E[A:kd=\\E[B:kr=\\E[C:kl=\\E[D:do=\\E[B:\\\n\t:ic=\\E[@:ei=:im=:pt:bw:dc=\\E[P:ce=3\\E[K:ho=10\\E[H:pt:\\\n\t:mi:nd=\\E[C:bt=\\E[Z:us=\\E[8p:ue=\\E[p:so=\\E[5m:se=\\E[m:\\\n\t:md=\\E[1p:mr=\\E[16p:mb=\\E[2p:mk=\\E[4p:me=\\E[0p:hs:ll=\\E[24;1H:\\\n\t:cd=50\\E[J:cs=9\\E[%i%d;%dr:ae=\\E(B:as=\\E(0:kh=\\E[H:kb=^H:\\\n\t:k0=\\EOP:k1=\\EOQ:k2=\\EOR:k3=\\EOS:k4=\\E[M:\\\n\t:k5=\\E[17~:k6=\\E[31~:k7=\\E[18~:k8=\\E[19~:k9=\\E[20~:kn#10:\\\n\t:l0=PF1:l1=PF2:l2=PF3:l3=PF4:l4=F5:\\\n\t:l5=F6:l6=F7:l7=F8:l8=F9:l9=F10:\\\n\t:is=\\E[1;24r\\E[24;1H\\E[35;?25h\\E[4;?10;3;1l\\E[m\\E(B\\E>:\\\n\t:ds=\\E7\\E[>,//\\E8:ts=\\E7\\E[>,^A:fs=^A\\E8:\nwx|wyse75-80|wy75-80|wyse 75 terminal with 80-column initialization:\\\n\t:is=\\E[?3l:tc=wy75:\nwl|wyse75-132|wy75-132|wyse 75 terminal with 132 columns :\\\n\t:is=\\E[?3h:co#132:tc=wy75:\n#\n#   Wyse WY75 utilizing keypad\n#\nw5|wy75ap|wyse75ap|wy-75ap|wyse-75ap|Wyse WY-75 Applications and Cursor keypad:\\\n\t:is=\\E[1;24r\\E[?10;3l\\E[?1;25h\\E[4l\\E[m\\E(B\\E=:\\\n\t:kd=\\EOB:ke=10\\E[?1l\\E>:kh=\\EOH:kl=\\EOD:kr=\\EOC:\\\n\t:ks=10\\E[?1h\\E=:ku=\\EOA:\\\n\t:tc=wyse75:\n# from ucbvax!ucsfmis!shewmake\nWc|wy85|wyse85|wyse-85:\\\n\t:do=^J:co#80:li#24:cl=\\E[;H\\E[2J:\\\n\t:le=^H:bs:cm=\\E[%i%d;%dH:nd=\\E[C:up=\\E[A:\\\n\t:ce=\\E[0K:cd=\\E[0J:so=\\E[7m:se=\\E[27m:\\\n\t:us=\\E[4m:ue=\\E[24m:\\\n\t:is=\\E[1;24r\\E[24;1H\\E[0m:\\\n\t:ks=\\E[?1h\\E=:ke=\\E[?1l\\E>:\\\n\t:ku=\\EOA:kd=\\EOB:kr=\\EOC:kl=\\EOD:kb=^H:\\\n\t:ho=\\E[H:k1=\\EOP:k2=\\EOQ:k3=\\EOR:k4=\\EOS:kh=\\E[H\"ta=^I:pt:sr=\\EM:\\\n\t:sc=\\E7:rc=\\E8:cs=\\E[%i%d;%dr:as=^N:ae=^O:bt=\\E[Z:\\\n\t:dc=\\E[P:dl=\\E[M:al=\\E[L:ei=\\E[4l:im=\\E[4h:\\\n\t:vb=\\E[?5h\\E[?5l:\\\n\t:hs:es:ts=\\E7\\E[?25l\\E[40h\\E[25;%dH\\E[2K:fs=\\E[1;24r\\E8\\E[?25h:\n# \f# --------------------------------\n#\n# z: Miscellaneous\n#\nz0|wind:\\\n\t:bs:cm=\\Ep%r%.%.:cl=\\En\\120\\030\\Eo:co#80:\\\n\t:ho=\\Ep\\200\\200:li#24:nd=^L:up=^K:nl=\\035:\\\n\t:kl=\\E3:kr=\\E4:ku=\\E1:kd=\\E2:k1=\\E5:k2=\\E6:k3=\\E7:k4=\\E8:\\\n\t:so=\\Em\\014:se=\\Em\\003:\nz1|wind16:\\\n\t:bs:cm=\\Ep%r%.%.:cl=\\En\\120\\020\\Eo:co#80:\\\n\t:ho=\\Ep\\200\\200:li#16:nd=^L:up=^K:nl=\\035:\\\n\t:so=\\Em\\014:se=\\Em\\003:\nz2|wind40:\\\n\t:bs:cm=\\Ep%r%.%.:cl=\\En\\120\\050\\Eo:co#80:\\\n\t:ho=\\Ep\\200\\200:li#40:nd=^L:up=^K:nl=\\035:\\\n\t:so=\\Em\\014:se=\\Em\\003:\nz3|wind50:\\\n\t:bs:cm=\\Ep%r%.%.:cl=\\En\\128\\062\\Eo:co#88:\\\n\t:ho=\\Ep\\200\\200:li#50:nd=^L:up=^K:nl=\\035:\\\n\t:kl=\\E3:kr=\\E4:ku=\\E1:kd=\\E2:k1=\\E5:k2=\\E6:k3=\\E7:k4=\\E8:\\\n\t:so=\\Em\\014:se=\\Em\\003:\nz4|cad68-3|cgc3|cad68 basic monitor transparent mode size 3 chars:\\\n\t:am:bs:cl=^Z:co#73:ho=\\036:li#36:nd=^L:up=^K:\nz5|cad68-2|cgc2|cad68 basic monitor transparent mode size 2 chars:\\\n\t:am:bs:cl=^Z:co#85:ho=\\036:li#39:nd=^L:up=^K:\\\n\t:kl=\\E3:kr=\\E4:ku=\\E1:kd=\\E2:k1=\\E5:k2=\\E6:k3=\\E7:k4=\\E8:\\\n\t:so=\\Em\\014:se=\\Em\\003:\nz6|v50|visual 50:\\\n\t:am:bs:al=\\EL:dl=\\EM:\\\n\t:cd=\\Ek:ce=\\EK:cl=^Z:cm=\\E=%+\\040%+\\040:co#80:do=^J:ho=\\EH:\\\n\t:kb=^H:kd=\\EB:kh=\\EH:kl=\\ED:kr=\\EC:ku=\\EA:li#24:ms:nd=^L:pt:\\\n\t:so=\\EU:se=\\ET:up=^K:\nz7|trs2|trsII|trs80II|Radio Shack Model II using P&T CP/M:\\\n\t:nl=^_:al=^D:am:bs:cd=^B:ce=^A:cl=^L:cm=\\EY%+ %+ :co#80:\\\n\t:dl=^K:do=^_:ho=^F:li#24:nd=^]:ms:pt:se=^O:so=^N:up:=^^:\\\n\t:kb=^H:kd=^_:kl=^\\:kr=^]:ku=^^:\nz9|ps300|Picture System 300:us@:ue@:so@:se@:xt:pt@:tc=vt100:\nza|masscomp2:co#64:li#21:tc=masscomp:\nzb|masscomp1:co#104:li#36:tc=masscomp:\nzc|masscomp:\\\n\t:al=\\E[L:bs:cd=\\E[J:ce=\\E[K:co#80:dc=\\E[P:dl=\\E[M:do=\\E[B:\\\n\t:ei=\\E[4l:im=\\E[4h:is=\\EGc\\EGb\\EGw:li#24:mi:MT:nd=\\E[C:pt:se=\\E[0m:\\\n\t:sg#0:so=\\E[7m:cm=\\E[%i%d;%dH:ue=\\EGau:us=\\EGu:up=\\E[A:\\\n\t:ku=\\EOA:kd=\\EOB:kr=\\EOC:kl=\\EOD:kb=^h:cl=\\E[2J:\n# Kimtron TC entries include (undocumented) codes for: enter dim mode (mh),\n# enter bold mode (md), enter reverse mode (mr), turn off all attributes (me)\n# Kimtron ABM 85 added by Dual Systems\nzd|abm85|Kimtron ABM 85:\\\n\t:is=\\EC\\EX\\Eg\\En\\E%\\Er\\E(\\Ek\\Em\\Eq:if=/usr/share/tabset/stdcrt:\\\n\t:li#24:co#80:am:bs:bw:ms:pt:\\\n\t:cl=\\E*:cd=\\Ey:dl=\\ER:al=\\EE:ce=\\Et:dc=\\EW:im=\\EQ:ei=\\Er:\\\n\t:cm=\\E=%+ %+ :do=^J:nd=^L:up=^K:bt=\\EI:\\\n\t:kh=^^:kb=^H:kd=^J:ku=^K:kd=^J:kl=^H:kr=^L:\\\n\t:so=\\Ej:se=\\Ek:sg#1:us=\\El:ue=\\Em:ug#1:\n# Kimtron ABM 85H added by Dual Systems.\n# Some notes about the 85h entries:\n# 1) there are several firmware revs of 85H in the world. Use o85h for\n#    firmware revs prior to SP51\n# 2) Make sure to use 85h entry if the terminal is in 85H mode and the\n#    85e entry if it is in 920 emulation mode. They are incompatible in\n#    some places and NOT software settable i.e., `is' can't fix change it)\n# 3) In 85h mode, the arrow keys and special functions transmit when\n#    the terminal is in dup-edit, and work only locally in local-edit.\n#    Vi won't swallow `del char' for instance, but `vs' turns on\n#    dup-edit anyway so that the arrow keys will work right. If the\n#    arrow keys don't work the way you like, change `vs', `ve', and `is'.\n#    920E mode does not have software commands to toggle between dup\n#    and local edit, so you get whatever was set last on the terminal.\n# 4) vb attribute is nice, but seems too slow to work correctly (\\Eb<pad>\\Ed)\n# 5) Make sure `hidden' attributes are selected. If `embedded' attributes\n#    are selected, the entries :sg@: and :ug@: should be removed.\n# 6) auto new-line should be on (selectable from setup mode only)\n#\n# From fair@ucbarpa  Sun Oct 27 07:21:05 1985\nze|85h|85H|abm85h|Kimtron ABM 85H, 85H mode:\\\n\t:is=\\EC\\EN\\EX^T^N\\EA\\Ea\\E%\\E9\\Ee\\Er\\En\\E\"\\E}\\E'\\E(\\Ef^M\\EG0\\Ed\\E.4\\El:\\\n\t:im=\\EZ:kd=^V:so=\\EG4:se=\\EG0:us=\\EG8:ue=\\EG0:vb@:vs=\\E.2:ve=\\E.4:\\\n\t:mh=\\E):mr=\\EG4:me=\\E(\\EG0:sg@:ug@:ds=\\Ee:fs=^M:hs:ts=\\Eg\\Ef:tc=abm85:\nzf|85e|85E|abm85e|Kimtron ABM 85H, 920E mode:\\\n\t:is=\\EC\\EX\\EA\\E%\\E9\\Ee\\Er\\En\\E\"\\E}\\E'\\E(\\Ef^M\\Ek\\Eq\\Em:\\\n\t:mh=\\E):mr=\\Ej:me=\\E(\\Ek:im=\\EZ:sg@:ug@:vb@:tc=abm85:\nzg|o85h|oabm85h|Kimtron ABM 85H, old firmware rev.:\\\n\t:is=\\E}\\EC\\EX\\Ee\\En\\E%\\Er\\E(\\Ek\\Em\\Eq\\Ed\\ET\\EC\\E9\\EF:\\\n\t:im=\\EZ:sg@:ug@:vb=\\200\\200\\200^G\\200\\200\\200:\\\n\t:mh=\\E):mr=\\Ej:me=\\E(\\Ek:tc=abm85:\n#from  malman@bbn-vax.arpa\nzE|kt7|kimtron model kt-7:\\\n\t:am:bs:co#80:li#24:cm=\\E=%+ %+ :cl=^Z:cd=\\EY:ce=\\ET:is=\\El\\E\":\\\n\t:al=\\EE:dl=\\ER:im=:ei=:ic=\\EQ:dc=\\EW:if=/usr/share/tabset/stdcrt:\\\n\t:ho=^^:nd=^L:bt=\\EI:pt:so=\\EG4:se=\\EG0:sg#0:us=\\EG8:ue=\\EG0:ug#0:\\\n\t:up=^K:do=^V:kb=^H:ku=^K:kd=^V:kl=^H:kr=^L:kh=^^:ma=^V^J^L :\\\n\t:k1=^A@\\r:k2=^AA\\r:k3=^AB\\r:k4=^AC\\r:k5=^AD\\r:k6=^AE\\r:k7=^AF\\r:\\\n\t:k8=^AG\\r:k9=^AH\\r:k0=^AI\\r:ko=ic,dc,al,dl,cl,ce,cd,bt:\\\n\t:ts=\\Ef:fs=\\Eg:\nzh|appleII|apple ii plus:vs=\\024\\103\\066:ve=\\024\\103\\062:\\\n\t:am:co#80:ce=\\035:li#24:cl=\\014:bs:nd=\\034:up=\\037:ho=\\E\\031:pt:\\\n\t:cd=\\013:so=\\017:se=\\016:cm=\\036%r%+ %+ :is=\\024T1\\016:do=^J:kd=^J:\\\n\t:vb=\\024G1\\024T1:kr=\u0015:\n#  Gary Ford 21NOV83\n#  New version from ee178aci%sdcc7@SDCSVAX.ARPA  Fri Oct 11 21:27:00 1985\nzi|apple-80|apple II with smarterm 80 col:\\\n\t:am:bs:bt=^R:bw:cd=10*^K:ce=10^]:cl=10*^L:cm=^^%r%+ %+ :\\\n\t:co#80:cr=10*^M:do=^J:ho=^Y:le=^H:li#24:nd=^\\\\:up=^_:\n#\nzj|lisa|apple lisa xenix console display (white on black):\\\n\t:al=\\E[L:am:bs:cd=\\E[J:ce=\\E[K:cl=^L:cm=\\E[%i%d;%dH:co#88:\\\n\t:dc=\\E[P:dl=\\E[M:dn=\\E[B:ei=:ho=\\E[H:ic=\\E[@:im=:li#32:\\\n\t:nd=\\E[C:ms:pt:so=\\E[m:se=\\E[7m:us=\\E[4m:ue=\\E[7m:up=\\E[A:\\\n\t:kb=^h:ku=\\E[A:kd=\\E[B:kl=\\E[D:kr=\\E[C:eo:\\\n\t:is=\\E[7m^L:GS=\\E[11m:GE=\\E[10m:GV=\\140:GH=a:G1=c:\\\n\t:G2=f:G3=e:G4=d:GU=u:GD=s:GC=b:GL=v:GR=t:\n# The following is a version of the ibm-pc entry distributed with PC/IX,\n# (Interactive Systems' System 3 for the Big Blue), modified by Richard\n# McIntosh at UCB/CSM.  The :pt: and :uc: have been removed from the original,\n# (the former is untrue, and the latter failed under UCB/man); standout and\n# underline modes have been added.  Note: this entry describes the \"native\"\n# capabilities of the PC monochrome display, without ANY emulation; most\n# communications packages (but NOT PC/IX connect) do some kind of emulation.\npc|ibmpc|ibm pc PC/IX:\\\n\t:li#24:co#80:am:bs:bw:eo:\\\n\t:cd=\\E[J:ce=\\E[K:cl=\\Ec:cm=\\E[%i%2;%2H:do=\\E[B:ho=\\E[;H:\\\n\t:nd=\\E[C:up=\\E[A:so=\\E[7m:se=\\E[0m:us=\\E[4m:ue=\\E[0m:\npc3-bold|ibmpc3|IBM PC BSD/386 Console with bold instead of underline:\\\n\t:us=\\E[=15F:ue=\\E[=R:tc=pc3:\\\npc3|ibmpc3|IBM PC BSD/386 Console:\\\n        :li#25:al=\\E[L:dl=\\E[M:md=\\E[=15F:me=\\E[=R:mh=\\E[=8F:\\\n        :kh=\\E[H:kH=\\E[F:kP=\\E[I:kN=\\E[G:kI=\\E[L:\\\n        :ku=\\E[A:kd=\\E[B:kl=\\E[D:kr=\\E[C:tc=pc:\nzk|ibmx|ibmpcx|IBM PC xenix console display:\\\n\t:al=\\E[L:am:bs:cd=\\E[J:ce=\\E[K:cl=^L:cm=\\E[%d;%dH:co#80:\\\n\t:dc=\\E[P:dl=\\E[M:dn=\\E[B:ei=:ho=\\E[H:ic=\\E[@:im=:li#25:\\\n\t:nd=\\E[C:ms:se=\\E[0m:so=\\E[7m:us=\\E[4m:\\\n\t:ue=\\E[m:up=\\E[A:MR=\\E[0m:\\\n\t:kb=^h:kh=\\E[Y:ku=\\E[A:kd=\\E[B:kl=\\E[D:kr=\\E[C:eo:\\\n\t:GS=\\E[11m:GE=\\E[10m:\\\n\t:GC=b:GL=v:GR=t:RT=^J:\\\n\t:GH=\\E[196g:GV=\\E[179g:\\\n\t:GU=\\E[193g:GD=\\E[194g:\\\n\t:G1=\\E[191g:G2=\\E[218g:G3=\\E[192g:G4=\\E[217g:\\\n\t:CW=\\E[E:NU=\\E[F:RF=\\E[G:RC=\\E[H:\\\n\t:WL=\\E[K:WR=\\E[L:CL=\\E[M:CR=\\E[N:\\\n\t:HM=\\E[Y:EN=\\E[d:PU=\\E[Z:PD=\\E[e:\nzl|ibmc|ibmcpc|IBM PC xenix color console display:\\\n\t:tc=ibm:\nzl|ibmcx|ibmcpcx|IBM PC xenix color console display:\\\n\t:tc=ibmx:\nzm|kaypro|kaypro2|kaypro II:\\\n\t:am:bs:cm=\\E=%+ %+ :cl=1^Z:co#80:ho=^^:li#24:ma=^K^P:nd=^L:up=^K:\\\n\t:kr=\f:kl=^H:ku=\u000b:kd=^J:\n# From Suk Lee ..!{decvax,linus,allegra,ihnp4}!utcsrgv!spoo\nzn|trs100|Radio Shack Model 100:\\\n\t:am:bs:le=^H:li#8:co#40:ku=^^:kd=^_:kl=^]:kr=^\\:up=\\EA:\\\n\t:nd=\\EC:ho=\\EH:ce=\\EK:cd=\\EJ:cl=\\EE:xt:cm=\\EY%+ %+ :\\\n\t:so=\\Ep:se=\\Eq:al=\\EL:dl=\\EM:\nzt|mac|macintosh|Macintosh with MacTerminal:\\\n\t:al=20\\E[L:dl=20\\E[M:ip=7:dc=7\\E[P:ic=9\\E[@:xn:dN#30:tc=vt100:\nzs|zen50|z50:zephyr:\\\n\t:cm=\\E=%+ %+ :cd=\\EY:co#80:li#24:\\\n\t:am:al=\\EE:ce=\\ET:dc=\\EW:dl=\\ER:ic=\\EQ:im=:ei=:\\\n\t:cl=\\E+:bs:ma=^Hh^Ll^Jj^Kk:sg#1:se=\\EGO:so=\\EG4:\\\n\t:kl=^H:kr=^L:ku=^K:kd=^J:kh=\\036:up=^K:\\\n\t:BS=^U:CL=^V:CR=^B:RK=^L:UK=^K:LK=^H:DK=^J:HM=\\036:\nzu|go140|graphon go-140:\\\n\t:co#80:li#24:cl=10\\E[;H\\E[2J:bs:cm=\\E[%i%2;%2H:nd=\\E[C:up=\\E[A:\\\n\t:ce=\\E[K:cd=10\\E[J:so=\\E[7m:se=\\E[m:us=\\E[4m:ue=\\E[m:\\\n\t:is=\\E<\\E=\\E[?3l\\E[?7l\\E(B\\E[J\\E7\\E[;r\\E8\\E[m\\E[q:\\\n\t:dl=\\E[M:al=\\E[L:dc=\\E[P:im=\\E[4h:ei=\\E[4l:\\\n\t:ks=\\E[?1h\\E=:ke=\\E[?1l\\E>:\\\n\t:if=/usr/share/tabset/vt100:ku=\\EOA:kd=\\EOB:kr=\\EOC:kl=\\EOD:\\\n\t:kh=\\E[H:k1=\\EOP:k2=\\EOQ:k3=\\EOR:k4=\\EOS:pt:sr=\\EM:\nzv|go140w|graphon go-140 in 132 column mode:\\\n\t:co#132:is=\\E<\\E=\\E[?3h\\E[?7h\\E(B\\E[J\\E7\\E[;r\\E8\\E[m\\E[q:\\\n\t:tc=go140:\nzw|sanyo55|sanyo|sanyo mbc-55x pc compatible:\\\n\t:co#80:li#25:am:cl=\\E[H\\E[J:bs:cm=\\E[%i%d;%dH:nd=\\E[C:up=\\E[A:\\\n\t:ce=\\E[K:cd=\\E[J:so=\\E[7m:se=\\E[m:us=\\E[4m:ue=\\E[m:\n#From: Simson L. Garfinkel <simsong@media-lab.mit.edu>\nzC|ST|atari st:\\\n\t:bs:cd=\\EJ:ce=\\EK:cl=\\EH\\EJ:cm=\\EY%+ %+ :co#80:li#25:nd=\\EC:\\\n\t:pt:sr=\\EI:up=\\EA:ku=\\EA:kd=\\EB:kr=\\EC:kl=\\ED:\\\n\t:do=\\EB:\\\n\t:so=\\Ep:se=\\Eq:dl=\\EM:al=\\EL:am:\n# UniTerm terminal program for the Atari ST:  49-line VT220 emulation mode\n# From Paul M. Aoki, aoki@ucbvax.Berkeley.EDU\nzD|uniterm|uniterm49|UniTerm VT200 emulator, 49 lines:\\\n\t:li#49:is=\\E>\\E[?3l\\E[?4l\\E[?5l\\E[?7h\\E[?8h\\E[1;49r\\E[49;1H:\\\n\t:tc=vt200:\n# YTERM standard version 1.0.  (gts 9-25-84)\n# Straight old ascii keyboard except function keys are Yale (e.g.,ASCII.KBD).\n# Only 80 tab columns (else yterm 1.1 bug).  No :xn: in 1.0.\n# Cannot use termcap :sr=\\EM: because vi will not work, too bad.\n# vi string is given so that yterm is reset each vi startup.\nY0|yterm10|yterm 1.0 UCB ascii.kbd:\\\n\t:am:bs:cd=^K:ce=^]:cl=^L:cm=^^%r%+ %+ :co#80:EP:ho=^Y:li#24:nd=^\\:pt:\\\n\t:rc=\\E8:sc=\\E7:so=\\E[7m:se=\\E[m:up=^_:us=\\E[4m:ue=\\E[m:\\\n\t:is=^O\\E[7i\\E[m\\E[?7h\\E[?3g\\r\\EHY0  for \\EHYTERM 1.\\EH0 with A\\EHSCII.KBD\\EH 9-13-84\\EH        \\EH        \\EH        \\EH        \\EH\\n:\\\n\t:ku=^K:kd=^J:kl=^H:kr=^L:kh=^^:ma=\bh\\012j\u000bk\fl\u001eH:\\\n\t:k0=\\E0:k1=\\E1:k2=\\E2:k3=\\E3:k4=\\E4:k5=\\E5:k6=\\E6:k7=\\E7:k8=\\E8:k9=\\E9:\\\n\t:vs=^O\\E[7i\\E[m\\E[?7h\\E[?3g\\r\\EHY0      \\EH        \\EH        \\EH        \\EH        \\EH        \\EH        \\EH        \\EH        \\EH\\r:\n# YTERM varient version 1.1.  (gts 9-13-84)  Version 1.1 has :xn:.\nY1|yterm11|yterm 1.1 UCB ascii.kbd:\\\n\t:xn:is=^O\\E[7i\\E[m\\E[?7h\\E[?3g\\r\\EHY1  for \\EHYTERM 1.\\EH1 with A\\EHSCII.KBD\\EH 9-13-84\\EH        \\EH        \\EH        \\EH        \\EH\\n:\\\n\t:tc=yterm10\n# YTERM 1.0 varient no autowrap or tabs\n# X does not remember autowrap or tabs when T is deleted and restarted.\nY2|yterm10nat|yterm 1.0 UCB ascii.kbd no autowrap or tabs:\\\n\t:am@:pt@:vs=^O\\E[7i\\E[m\\E[?7l\\E[?3g\\rY2\\r:\\\n\t:is=^O\\E[7i\\E[m\\E[?7l\\E[?3g\\rY2  for YTERM 1.0 with ASCII.KBD 9-20-84 no autowrap or tabs\\n:\\\n\t:tc=yterm10\n# KERMIT standard all versions.  (gts 9-25-84)\n# Straight ascii keyboard. :sr=\\EI: not avail. many versions + bug prone in vi.\nK0|kermit|standard kermit:\\\n\t:bs:cd=\\EJ:ce=\\EK:cl=\\EE:cm=\\EY%+ %+ :co#80:ho=\\EH:li#24:nd=\\EC:up=\\EA:\\\n\t:ku=^K:kd=^J:kl=^H:kr=^L:kh=^^:ma=^Hh\\012j^Kk^Ll^^H:\\\n\t:is=K0 Standard Kermit  9-25-84\\n:\nK1|kermitam|standard kermit plus am:\\\n\t:am:is=K1 Standard Kermit plus Automatic Margins\\n:tc=kermit:\n# IBMPC Kermit 1.2.  (gts 8-30-84)\n# Bugs :cd:ce: do not work except at beginning of line!  :cl: does not work,\n# but fake with :cl=\\EH\\EJ (since :cd=\\EJ: works at beginning of line).\nK2|pckermit|pckermit12|UCB IBMPC Kermit 1.2:\\\n\t:am:li#25:cd@:ce@:cl=\\EH\\EJ:\\\n\t:is=K2 UCB IBMPC Kermit 1.2  8-30-84\\n:tc=kermit:\n# IBMPC Kermit 1.20\t(gts 12-19-84)\n# Cannot use line 25, now acts funny like ansi special scrolling region.\n# Initialization must escape from that region by cursor position to line 24.\n# Cannot use character insert because 1.20 goes crazy if insert at col 80.\n# Does not use am: because autowrap mode lost when kermit dropped and restarted.\nK3|pckermit120|UCB IBMPC Kermit 1.20:\\\n\t:al=\\EL:am@:dc=\\EN:dl=\\EM:do=\\EB:ei@:im@:li#24:pt:se=\\Eq:so=\\Ep:\\\n\t:is=\\EO\\Eq\\EJ\\EY7 K3 UCB IBMPC Kermit 1.20  12-19-84\\n:\\\n\t:vs=\\EO\\Eq\\EEK3:tc=kermit:\n# MS-DOS Kermit 2.27 for the IBMPC\t(UCB gts 3-17-85)\n# Straight ascii keyboard. :sr=\\EI: not avail. many versions + bug prone in vi.\n# Cannot use line 25, now acts funny like ansi special scrolling region.\n# Initialization must escape from that region by cursor position to line 24.\n# Does not use am: because autowrap mode lost when kermit dropped and restarted.\n# Reverse video for standout like H19.\nK4|msk227|mskermit227|MS-DOS Kermit 2.27 for the IBMPC:\\\n\t:al=\\EL:am@:bs:cd=\\EJ:ce=\\EK:cl=\\EE:cm=\\EY%+ %+ :co#80:\\\n\t:dc=\\EN:dl=\\EM:do=\\EB:ei=\\EO:im=\\E@:\\\n\t:ho=\\EH:li#24:nd=\\EC:up=\\EA:pt:rc=\\Ek:sc=\\Ej:se=\\Eq:so=\\Ep:\\\n\t:ku=^K:kd=^J:kl=^H:kr=^L:kh=^^:ma=^Hh\\012j^Kk^Ll^^H:\\\n\t:is=\\EO\\Eq\\EG\\Ew\\EJ\\EY7 K4 MS Kermit 2.27 for the IBMPC 3-17-85\\n:\\\n\t:vs=\\EO\\Eq\\EG\\EwK4:\n# MS-DOS Kermit 2.27 with automatic margins\t(UCB gts 3-17-85)\nK5|msk227am|mskermit227am|UCB MS-DOS Kermit 2.27 with automatic margins:\\\n\t:am:\\\n\t:is=\\EO\\Eq\\EG\\Ev\\EJ\\EY7 K5 MS Kermit 2.27 +automatic margins 3-17-85\\n:\\\n\t:vs=\\EO\\Eq\\EG\\EvK5:tc=mskermit227:\n# MS-DOS Kermit 2.27 UCB 227.14 for the IBM PC\t(UCB gts 3-17-85)\n# Automatic margins now default.  Use ansi set graphic rendition for standout,\n# underline and ul codes (md,me,mr).  Define function keys.\nK6|msk22714|mskermit22714|UCB MS-DOS Kermit 2.27 UCB 227.14 IBM PC:\\\n\t:am:kn#10:\\\n\t:k0=\\E0:k1=\\E1:k2=\\E2:k3=\\E3:k4=\\E4:k5=\\E5:k6=\\E6:k7=\\E7:k8=\\E8:k9=\\E9:\\\n\t:md=\\E[1m:me=\\E[m:mr=\\E[7m:se=\\E[m:so=\\E[1m:ue=\\E[m:us=\\E[4m:\\\n\t:is=\\EO\\Eq\\EG\\Ev\\EJ\\EY7 K6 MS Kermit 2.27 UCB 227.14 IBM PC 3-17-85\\n:\\\n\t:vs=\\EO\\Eq\\EG\\EvK6:tc=mskermit227:\n# From earle@smeagol.UUCP 29 Oct 85 05:40:18 GMT\n# MS-Kermit with Heath-19 emulation mode enabled\nKh|h19k|h19kermit|heathkit emulation provided by Kermit (no auto margin):\\\n\t:am@:ta@:pt@:xt:da:db:tc=h19-u:\n# rough draft of Amiga termcap by Mike Meyer\nAA|amiga|Amiga ANSI:\\\n\t:co#80:li#25:am:do=\\E[B:ce=\\E[K:cd=\\E[J:\\\n\t:cl=\\E[H\\E[J:ku=\\E[A:kd=\\E[B:kl=\\E[C:kr=\\E[D:kb=^H:\\\n\t:al=\\E[L:dl=\\E[M:le=^H:cm=\\E[%i%d;%dH:nd=\\E[C:up=\\E[A:\\\n\t:ce=\\E[K:ho=\\E[H:dc=\\E[P:ic=\\E[@:\\\n\t:so=\\E[2m:se=\\E[m:us=\\E[4m:ue=\\E[m:mr=\\E[7m:mb=\\E[7;2m:me=\\E[m:\n# The pcplot IBM-PC terminal emulation program is really messed up. It is\n# supposed to emulate a vt-100, but emulates the wraparound bug incorrectly,\n# doesn't support scrolling regions, ignores add line commands, and ignores\n# delete line commands. Consequently, the resulting behavior looks like a\n# crude adm3a-type terminal.\n# Steve Jacobson 8/85\npp|pcplot:\\\n\t:cs@:sc@:rc@:xn@:tc=vt100:\n# From Joel Rubin, jmrubin@coral, a preliminary TERMCAP for VIDTEX,\n# a terminal program sold by Compuserve.  Line and column numbers are\n# computer-dependent (I have a Commodore '64); you should use the meta-B\n# option to shut off clean-breaking of lines.  No key codes included \n# since some of them are programmable and most are machine-specific.\n# Works on vi if you don't use clean-breaking.  Very similar to the IBM 3101\n# termcap.  Escape-D used for backspace because control-H is destructive\n# backspace.  There seem to be a few weirdnesses (especially at the beginning\n# of a wrapped line), and the cursor does not, unfortunately, flash.\nzQ|vid|vidtex|Compuserve vidtex program:\\\n\t:am:bc=\\ED:cl=^L:li#25:co#40:nd=\\EC:up=\\EA:cd=\\EJ:ce=\\EK:\\\n\t:ho=\\EH:cm=\\EY%+\\40%+\\40:pt:\n# Fortune from c160-3bp@Coral (Robert Nathanson) via tut   Wed Oct 5, 1983\nzK|fos|fortune|Fortune system:\\\n\t:is=^_..:li#25:co#80:am:bs:bw:cl=20^L:cd=3*^\\Y:\\\n\t:ic=5^\\Q:dc=5^\\W:dl=15^\\R:al=15^\\E:cm=^\\C%+ %+ :ta=^Z:ho=10^^:do=3^J:\\\n\t:up=3^K:bs=^H:kb=^H:kd=^Ay\\r:kh=^A?\\r:kl=^Aw\\r:kr=^Az\\r:ku=^Ax\\r:\\\n\t:nl=5^J:so=^\\H`:se=^\\I`:sg=0:us=^\\HP:ue=^\\IP:ug=0:ce=^\\Z:rv=\\EH:re=\\EI:\\\n\t:rg=0:GS=\\Eo:GE=^O:GG=0:GV=-:GH=&:GU=%:GD=#:G1=(:G2= :G3=\":G4=*:CF=\\E]:\\\n\t:CO=\\E\\\\:WL=^Aa\\r:WR=^Ab\\r:CL=^Ac\\r:CR=^Ad\\r:DL=^Ae\\r:RF=^Af\\r:\\\n\t:RC=^Ag\\r:CW=^Ah\\r:NU=^Aj\\r:EN=^Ak\\r:HM=^Al:PL=^Am\\r:PU=^An\\r:PD=^Ao\\r:\\\n\t:PR=^Ap\\r:HP=^A@\\r:RT=^Aq\\r:TB=\\r:CN=\\177:MP=\\E+F:\n# basis from Peter Harrison, Computer Graphics Lab, San Francisco\n#   ucbvax!ucsfmis!harrison ...uucp / ucbvax!ucsfmis!harrison@BERKELEY ...ARPA\nba|basis|BASIS108 computer with terminal translation table active:\\\n\t:do=5000^J:nl=5000*^J:\\\n\t:cd=\\EY:ce=\\ET:cl=300\\E*:ma=^K^P^R^L^L :\\\n\t:kb=^H:kl=^H:ku=^K:kr=^L:kd=^J:so=\\E(:se=\\E):tc=adm3a:\n# From Peter Harrison, Computer Graphics Lab, San Francisco\n#   ucbvax!ucsfmis!harrison  .....uucp\n#   ucbvax!ucsfmis!harrison@BERKELEY   .......ARPA\n# \"These two work.  If you don't have the inverse video chip for the\n# Apple with videx then remove the so and se fields.\"\nzO|DaleApple|Apple with videx videoterm 80 column board with inverse video:\\\n\t:do=^J:am:le=^H:bs:cd=^K:ce=^]:cl=300^L:cm=^^%r%+ %+ :co#80:ho=^Y:\\\n\t:kd=^J:kl=^H:kr=^U:kh=^Y:\\\n\t:li#24:nd=^\\:pt:so=^Z3:se=^Z2:up=^_:xn:\nzJ|ibmaed|IBM Experimental display:\\\n\t:al=\\EN:am:bs:cd=\\EJ:ce=\\EI:cl=\\EH\\EK:cm=\\EY%+\\40%+\\40:co#80:\\\n\t:dc=\\EQ:dl=\\EO:do=\\EB:ei=:ho=\\EH:ic=\\EP:im=:li#52:\\\n\t:nd=\\EC:ms:so=\\E0:se=\\E0:us=:ue=:up=\\EA:\\\n\t:kb=^h:ku=\\EA:kd=\\EB:kl=\\ED:kr=\\EC:eo:vb=\\EG:pt:\n# funny terminal that the TANDEM uses.\nzA|653|t653x|Tandem 653x multipage terminal:\\\n\t:li#24:co#80:ho=\\EH:cm=\\023%+ %+ :cl=\\EI:cd=\\EJ:ce=\\EK:am:bs:\\\n\t:if=/usr/share/tabset/tandem653:sb=\\ES:sr=\\ET:da:db:so=\\E6$:se=\\E6 :\\\n\t:us=\\E60:ue=\\E6 :sg#1:ug#1:up=\\EA:do=\\012:le=\\010:nd=\\EC:\\\n\t:hs:ts=\\Eo:fs=\\r:ds=\\Eo\\r:ws#64:\n# From Paul Leondis, unllab@amber.berkeley.edu\nzB|ifmr|Informer D304:\\\n\t:am:bs:cd=\\E/:ce=\\EQ:cl=\\EZ:cm=\\EY%r%+ %+ :co#80:dc=\\E\\\\:\\\n\t:do=^J:im=:ei=:ic=\\E[:li#24:nd=\\EC:so=\\EJ:se=\\EK:up=\\EA:\\\n\t:sr=\\En:ho=\\EH:\n#\n# END OF TERMCAP\n#  ------------------------\n"
  },
  {
    "path": "lib/libtermlib/termcap.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <string.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <fcntl.h>\n#include <ctype.h>\n#include <term.h>\n\n#define\tBUFSIZ\t\t1024\n#define MAXHOP\t\t32\t/* max number of tc= indirections */\n#define\tE_TERMCAP\t\"/etc/termcap\"\n\n/*\n * termcap - routines for dealing with the terminal capability data base\n *\n * BUG:\t\tShould use a \"last\" pointer in tbuf, so that searching\n *\t\tfor capabilities alphabetically would not be a n**2/2\n *\t\tprocess when large numbers of capabilities are given.\n * Note:\tIf we add a last pointer now we will screw up the\n *\t\ttc capability. We really should compile termcap.\n *\n * Essentially all the work here is scanning and decoding escapes\n * in string capabilities.  We don't use stdio because the editor\n * doesn't, and because living w/o it is not hard.\n */\n\nstatic\tchar *tbuf;\nstatic\tint hopcount;\t/* detect infinite loops in termcap, init 0 */\n\n/*\n * Tnamatch deals with name matching.  The first field of the termcap\n * entry is a sequence of names separated by |'s, so we compare\n * against each such name.  The normal : terminator after the last\n * name (before the first field) stops us.\n */\nstatic int\ntnamatch(np)\n\tchar *np;\n{\n\tregister char *Np, *Bp;\n\n\tBp = tbuf;\n\tif (*Bp == '#')\n\t\treturn(0);\n\tfor (;;) {\n\t\tfor (Np = np; *Np && *Bp == *Np; Bp++, Np++)\n\t\t\tcontinue;\n\t\tif (*Np == 0 && (*Bp == '|' || *Bp == ':' || *Bp == 0))\n\t\t\treturn (1);\n\t\twhile (*Bp && *Bp != ':' && *Bp != '|')\n\t\t\tBp++;\n\t\tif (*Bp == 0 || *Bp == ':')\n\t\t\treturn (0);\n\t\tBp++;\n\t}\n}\n\n/*\n * tnchktc: check the last entry, see if it's tc=xxx. If so,\n * recursively find xxx and append that entry (minus the names)\n * to take the place of the tc=xxx entry. This allows termcap\n * entries to say \"like an HP2621 but doesn't turn on the labels\".\n * Note that this works because of the left to right scan.\n */\nstatic int\ntnchktc()\n{\n\tregister char *p, *q;\n\tchar tcname[16];\t/* name of similar terminal */\n\tchar tcbuf[BUFSIZ];\n\tchar *holdtbuf = tbuf;\n\tint l;\n\n\tp = tbuf + strlen(tbuf) - 2;\t/* before the last colon */\n\twhile (*--p != ':')\n\t\tif (p<tbuf) {\n\t\t\twrite(2, \"Bad termcap entry\\n\", 18);\n\t\t\treturn (0);\n\t\t}\n\tp++;\n\t/* p now points to beginning of last field */\n\tif (p[0] != 't' || p[1] != 'c')\n\t\treturn(1);\n\tstrcpy(tcname,p+3);\n\tq = tcname;\n\twhile (*q && *q != ':')\n\t\tq++;\n\t*q = 0;\n\tif (++hopcount > MAXHOP) {\n\t\twrite(2, \"Infinite tc= loop\\n\", 18);\n\t\treturn (0);\n\t}\n\tif (tgetent(tcbuf, tcname) != 1) {\n\t\thopcount = 0;\t\t/* unwind recursion */\n\t\treturn(0);\n\t}\n\tfor (q=tcbuf; *q != ':'; q++)\n\t\t;\n\tl = p - holdtbuf + strlen(q);\n\tif (l > BUFSIZ) {\n\t\twrite(2, \"Termcap entry too long\\n\", 23);\n\t\tq[BUFSIZ - (p-tbuf)] = 0;\n\t}\n\tstrcpy(p, q+1);\n\ttbuf = holdtbuf;\n\thopcount = 0;\t\t\t/* unwind recursion */\n\treturn(1);\n}\n\n/*\n * Get an entry for terminal name in buffer bp,\n * from the termcap file.  Parse is very rudimentary;\n * we just notice escaped newlines.\n */\nint\ntgetent(bp, name)\n\tchar *bp, *name;\n{\n\tregister char *cp;\n\tregister int c;\n\tregister int i = 0, cnt = 0;\n\tchar ibuf[BUFSIZ];\n\tint tf;\n\n\ttbuf = bp;\n\ttf = -1;\n#ifndef V6\n\tcp = getenv(\"TERMCAP\");\n\t/*\n\t * TERMCAP can have one of two things in it. It can be the\n\t * name of a file to use instead of /etc/termcap. In this\n\t * case it better start with a \"/\". Or it can be an entry to\n\t * use so we don't have to read the file. In this case it\n\t * has to already have the newlines crunched out.\n\t */\n\tif (cp && *cp) {\n\t\tif (*cp == '/') {\n\t\t\ttf = open(cp, 0);\n\t\t} else {\n\t\t\ttbuf = cp;\n\t\t\tc = tnamatch(name);\n\t\t\ttbuf = bp;\n\t\t\tif (c) {\n\t\t\t\tstrcpy(bp,cp);\n\t\t\t\treturn(tnchktc());\n\t\t\t}\n\t\t}\n\t}\n\tif (tf < 0)\n\t\ttf = open(E_TERMCAP, 0);\n#else\n\ttf = open(E_TERMCAP, 0);\n#endif\n\tif (tf < 0)\n\t\treturn (-1);\n\tfor (;;) {\n\t\tcp = bp;\n\t\tfor (;;) {\n\t\t\tif (i == cnt) {\n\t\t\t\tcnt = read(tf, ibuf, BUFSIZ);\n\t\t\t\tif (cnt <= 0) {\n\t\t\t\t\tclose(tf);\n\t\t\t\t\treturn (0);\n\t\t\t\t}\n\t\t\t\ti = 0;\n\t\t\t}\n\t\t\tc = ibuf[i++];\n\t\t\tif (c == '\\n') {\n\t\t\t\tif (cp > bp && cp[-1] == '\\\\'){\n\t\t\t\t\tcp--;\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (cp >= bp+BUFSIZ) {\n\t\t\t\twrite(2,\"Termcap entry too long\\n\", 23);\n\t\t\t\tbreak;\n\t\t\t} else\n\t\t\t\t*cp++ = c;\n\t\t}\n\t\t*cp = 0;\n\n\t\t/*\n\t\t * The real work for the match.\n\t\t */\n\t\tif (tnamatch(name)) {\n\t\t\tclose(tf);\n\t\t\treturn(tnchktc());\n\t\t}\n\t}\n}\n\n/*\n * Skip to the next field.  Notice that this is very dumb, not\n * knowing about \\: escapes or any such.  If necessary, :'s can be put\n * into the termcap file in octal.\n */\nstatic char *\ntskip(bp)\n\tregister char *bp;\n{\n\n\twhile (*bp && *bp != ':')\n\t\tbp++;\n\tif (*bp == ':')\n\t\tbp++;\n\treturn (bp);\n}\n\n/*\n * Return the (numeric) option id.\n * Numeric options look like\n *\tli#80\n * i.e. the option string is separated from the numeric value by\n * a # character.  If the option is not found we return -1.\n * Note that we handle octal numbers beginning with 0.\n */\nint\ntgetnum(id)\n\tchar *id;\n{\n\tregister int i, base;\n\tregister char *bp = tbuf;\n\n\tfor (;;) {\n\t\tbp = tskip(bp);\n\t\tif (*bp == 0)\n\t\t\treturn (-1);\n\t\tif (*bp++ != id[0] || *bp == 0 || *bp++ != id[1])\n\t\t\tcontinue;\n\t\tif (*bp == '@')\n\t\t\treturn(-1);\n\t\tif (*bp != '#')\n\t\t\tcontinue;\n\t\tbp++;\n\t\tbase = 10;\n\t\tif (*bp == '0')\n\t\t\tbase = 8;\n\t\ti = 0;\n\t\twhile (isdigit(*bp))\n\t\t\ti *= base, i += *bp++ - '0';\n\t\treturn (i);\n\t}\n}\n\n/*\n * Handle a flag option.\n * Flag options are given \"naked\", i.e. followed by a : or the end\n * of the buffer.  Return 1 if we find the option, or 0 if it is\n * not given.\n */\nint\ntgetflag(id)\n\tchar *id;\n{\n\tregister char *bp = tbuf;\n\n\tfor (;;) {\n\t\tbp = tskip(bp);\n\t\tif (!*bp)\n\t\t\treturn (0);\n\t\tif (*bp++ == id[0] && *bp != 0 && *bp++ == id[1]) {\n\t\t\tif (!*bp || *bp == ':')\n\t\t\t\treturn (1);\n\t\t\telse if (*bp == '@')\n\t\t\t\treturn(0);\n\t\t}\n\t}\n}\n\n/*\n * Tdecode does the grung work to decode the\n * string capability escapes.\n */\nstatic char *\ntdecode(str, area)\n\tregister char *str;\n\tchar **area;\n{\n\tregister char *cp;\n\tregister int c;\n\tregister char *dp;\n\tint i;\n\n\tcp = *area;\n\twhile ((c = *str++) && c != ':') {\n\t\tswitch (c) {\n\n\t\tcase '^':\n\t\t\tc = *str++ & 037;\n\t\t\tbreak;\n\n\t\tcase '\\\\':\n\t\t\tdp = \"E\\033^^\\\\\\\\::n\\nr\\rt\\tb\\bf\\f\";\n\t\t\tc = *str++;\nnextc:\n\t\t\tif (*dp++ == c) {\n\t\t\t\tc = *dp++;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tdp++;\n\t\t\tif (*dp)\n\t\t\t\tgoto nextc;\n\t\t\tif (isdigit(c)) {\n\t\t\t\tc -= '0', i = 2;\n\t\t\t\tdo\n\t\t\t\t\tc <<= 3, c |= *str++ - '0';\n\t\t\t\twhile (--i && isdigit(*str));\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t\t*cp++ = c;\n\t}\n\t*cp++ = 0;\n\tstr = *area;\n\t*area = cp;\n\treturn (str);\n}\n\n/*\n * Get a string valued option.\n * These are given as\n *\tcl=^Z\n * Much decoding is done on the strings, and the strings are\n * placed in area, which is a ref parameter which is updated.\n * No checking on area overflow.\n */\nchar *\ntgetstr(id, area)\n\tchar *id, **area;\n{\n\tregister char *bp = tbuf;\n\n\tfor (;;) {\n\t\tbp = tskip(bp);\n\t\tif (!*bp)\n\t\t\treturn (0);\n\t\tif (*bp++ != id[0] || *bp == 0 || *bp++ != id[1])\n\t\t\tcontinue;\n\t\tif (*bp == '@')\n\t\t\treturn(0);\n\t\tif (*bp != '=')\n\t\t\tcontinue;\n\t\tbp++;\n\t\treturn (tdecode(bp, area));\n\t}\n}\n"
  },
  {
    "path": "lib/libtermlib/tgoto.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#include <string.h>\n#define\tCTRL(c)\t('c' & 037)\n\n#define MAXRETURNSIZE 64\n\nchar\t*UP;\nchar\t*BC;\n\n/*\n * Routine to perform cursor addressing.\n * CM is a string containing printf type escapes to allow\n * cursor addressing.  We start out ready to print the destination\n * line, and switch each time we print row or column.\n * The following escapes are defined for substituting row/column:\n *\n *\t%d\tas in printf\n *\t%2\tlike %2d\n *\t%3\tlike %3d\n *\t%.\tgives %c hacking special case characters\n *\t%+x\tlike %c but adding x first\n *\n *\tThe codes below affect the state but don't use up a value.\n *\n *\t%>xy\tif value > x add y\n *\t%r\treverses row/column\n *\t%i\tincrements row/column (for one origin indexing)\n *\t%%\tgives %\n *\t%B\tBCD (2 decimal digits encoded in one byte)\n *\t%D\tDelta Data (backwards bcd)\n *\n * all other characters are ``self-inserting''.\n */\nchar *\ntgoto(CM, destcol, destline)\n\tchar *CM;\n\tint destcol, destline;\n{\n\tstatic char result[MAXRETURNSIZE];\n\tstatic char added[10];\n\tchar *cp = CM;\n\tregister char *dp = result;\n\tregister int c;\n\tint oncol = 0;\n\tregister int which = destline;\n\n\tif (cp == 0) {\ntoohard:\n\t\t/*\n\t\t * ``We don't do that under BOZO's big top''\n\t\t */\n\t\treturn (\"OOPS\");\n\t}\n\tadded[0] = 0;\n\twhile ((c = *cp++)) {\n\t\tif (c != '%') {\n\t\t\t*dp++ = c;\n\t\t\tcontinue;\n\t\t}\n\t\tswitch (c = *cp++) {\n\n#ifdef CM_N\n\t\tcase 'n':\n\t\t\tdestcol ^= 0140;\n\t\t\tdestline ^= 0140;\n\t\t\tgoto setwhich;\n#endif\n\n\t\tcase 'd':\n\t\t\tif (which < 10)\n\t\t\t\tgoto one;\n\t\t\tif (which < 100)\n\t\t\t\tgoto two;\n\t\t\t/* fall into... */\n\n\t\tcase '3':\n\t\t\t*dp++ = (which / 100) | '0';\n\t\t\twhich %= 100;\n\t\t\t/* fall into... */\n\n\t\tcase '2':\ntwo:\n\t\t\t*dp++ = which / 10 | '0';\none:\n\t\t\t*dp++ = which % 10 | '0';\nswap:\n\t\t\toncol = 1 - oncol;\nsetwhich:\n\t\t\twhich = oncol ? destcol : destline;\n\t\t\tcontinue;\n\n#ifdef CM_GT\n\t\tcase '>':\n\t\t\tif (which > *cp++)\n\t\t\t\twhich += *cp++;\n\t\t\telse\n\t\t\t\tcp++;\n\t\t\tcontinue;\n#endif\n\n\t\tcase '+':\n\t\t\twhich += *cp++;\n\t\t\t/* fall into... */\n\n\t\tcase '.':\n\t\t\t/*\n\t\t\t * This code is worth scratching your head at for a\n\t\t\t * while.  The idea is that various weird things can\n\t\t\t * happen to nulls, EOT's, tabs, and newlines by the\n\t\t\t * tty driver, arpanet, and so on, so we don't send\n\t\t\t * them if we can help it.\n\t\t\t *\n\t\t\t * Tab is taken out to get Ann Arbors to work, otherwise\n\t\t\t * when they go to column 9 we increment which is wrong\n\t\t\t * because bcd isn't continuous.  We should take out\n\t\t\t * the rest too, or run the thing through more than\n\t\t\t * once until it doesn't make any of these, but that\n\t\t\t * would make termlib (and hence pdp-11 ex) bigger,\n\t\t\t * and also somewhat slower.  This requires all\n\t\t\t * programs which use termlib to stty tabs so they\n\t\t\t * don't get expanded.  They should do this anyway\n\t\t\t * because some terminals use ^I for other things,\n\t\t\t * like nondestructive space.\n\t\t\t */\n\t\t\tif (which == 0 || which == CTRL(d) || /* which == '\\t' || */ which == '\\n') {\n\t\t\t\tif (oncol || UP) /* Assumption: backspace works */\n\t\t\t\t\t/*\n\t\t\t\t\t * Loop needed because newline happens\n\t\t\t\t\t * to be the successor of tab.\n\t\t\t\t\t */\n\t\t\t\t\tdo {\n\t\t\t\t\t\tstrcat(added, oncol ? (BC ? BC : \"\\b\") : UP);\n\t\t\t\t\t\twhich++;\n\t\t\t\t\t} while (which == '\\n');\n\t\t\t}\n\t\t\t*dp++ = which;\n\t\t\tgoto swap;\n\n\t\tcase 'r':\n\t\t\toncol = 1;\n\t\t\tgoto setwhich;\n\n\t\tcase 'i':\n\t\t\tdestcol++;\n\t\t\tdestline++;\n\t\t\twhich++;\n\t\t\tcontinue;\n\n\t\tcase '%':\n\t\t\t*dp++ = c;\n\t\t\tcontinue;\n\n#ifdef CM_B\n\t\tcase 'B':\n\t\t\twhich = (which/10 << 4) + which%10;\n\t\t\tcontinue;\n#endif\n\n#ifdef CM_D\n\t\tcase 'D':\n\t\t\twhich = which - 2 * (which%16);\n\t\t\tcontinue;\n#endif\n\n\t\tdefault:\n\t\t\tgoto toohard;\n\t\t}\n\t}\n\tstrcpy(dp, added);\n\treturn (result);\n}\n"
  },
  {
    "path": "lib/libtermlib/tputs.c",
    "content": "/*\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#include <sgtty.h>\n#include <ctype.h>\n\n/*\n * The following array gives the number of tens of milliseconds per\n * character for each speed as returned by gtty.  Thus since 300\n * baud returns a 7, there are 33.3 milliseconds per char at 300 baud.\n */\nstatic short tmspc10[] = {\n\t0, 2000, 1333, 909, 743, 666, 500, 333, 166, 83, 55, 41, 20, 10, 5\n};\n\nshort\tospeed;\nchar\tPC;\n\n/*\n * Put the character string cp out, with padding.\n * The number of affected lines is affcnt, and the routine\n * used to output one character is outc.\n */\nvoid\ntputs(cp, affcnt, outc)\n\tregister char *cp;\n\tint affcnt;\n\tint (*outc)();\n{\n\tregister int i = 0;\n\tregister int mspc10;\n\n\tif (cp == 0)\n\t\treturn;\n\n\t/*\n\t * Convert the number representing the delay.\n\t */\n\tif (isdigit(*cp)) {\n\t\tdo\n\t\t\ti = i * 10 + *cp++ - '0';\n\t\twhile (isdigit(*cp));\n\t}\n\ti *= 10;\n\tif (*cp == '.') {\n\t\tcp++;\n\t\tif (isdigit(*cp))\n\t\t\ti += *cp - '0';\n\t\t/*\n\t\t * Only one digit to the right of the decimal point.\n\t\t */\n\t\twhile (isdigit(*cp))\n\t\t\tcp++;\n\t}\n\n\t/*\n\t * If the delay is followed by a `*', then\n\t * multiply by the affected lines count.\n\t */\n\tif (*cp == '*')\n\t\tcp++, i *= affcnt;\n\n\t/*\n\t * The guts of the string.\n\t */\n\twhile (*cp)\n\t\t(*outc)(*cp++);\n\n\t/*\n\t * If no delay needed, or output speed is\n\t * not comprehensible, then don't try to delay.\n\t */\n\tif (i == 0)\n\t\treturn;\n\tif (ospeed <= 0 || ospeed >= (sizeof tmspc10 / sizeof tmspc10[0]))\n\t\treturn;\n\n\t/*\n\t * Round up by a half a character frame,\n\t * and then do the delay.\n\t * Too bad there are no user program accessible programmed delays.\n\t * Transmitting pad characters slows many\n\t * terminals down and also loads the system.\n\t */\n\tmspc10 = tmspc10[ospeed];\n\ti += mspc10 / 2;\n\tfor (i /= mspc10; i > 0; i--)\n\t\t(*outc)(PC);\n}\n"
  },
  {
    "path": "lib/libutil/Makefile",
    "content": "#\n# Copyright (c) 1988 Regents of the University of California.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms are permitted\n# provided that the above copyright notice and this paragraph are\n# duplicated in all such forms and that any documentation, advertising\n# materials, and other materials related to such redistribution and\n# use acknowledge that the software was developed by the University\n# of California, Berkeley.  The name of the University may not be\n# used to endorse or promote products derived from this software\n# without specific prior written permission.  THIS SOFTWARE IS PROVIDED\n# ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,\n# WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND\n# FITNESS FOR A PARTICULAR PURPOSE.\n#\nTOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS          += ${DEFS}\n\nSRCS            = login.c logout.c logwtmp.c\nOBJS            = login.o logout.o logwtmp.o\n\nall:            ../libutil.a\n\n../libutil.a:\t${OBJS}\n\t\t${AR} cr $@ ${OBJS}\n\t\t$(RANLIB) $@\n\nclean:\n\t\trm -f *.a *.o *~ profiled/*.o tags\n\ncleandir:       clean\n\t\trm -f .depend\n\ndepend:\n\t\tmkdep ${CFLAGS} ${SRCS}\n\ninstall:        all\n#\t\tcp ../libutil.a ${DESTDIR}/usr/lib/\n#\t\t$(RANLIB) -t ${DESTDIR}/usr/lib/libutil.a\n#\t\tcp libutil_p.a ${DESTDIR}/usr/lib/\n#\t\t$(RANLIB) -t ${DESTDIR}/usr/lib/libutil_p.a\n\ntags:\n\t\tctags ${SRCS}\n"
  },
  {
    "path": "lib/libutil/login.c",
    "content": "/*\n * Copyright (c) 1988 The Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that the above copyright notice and this paragraph are\n * duplicated in all such forms and that any documentation,\n * advertising materials, and other materials related to such\n * distribution and use acknowledge that the software was developed\n * by the University of California, Berkeley.  The name of the\n * University may not be used to endorse or promote products derived\n * from this software without specific prior written permission.\n * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n */\n#include <sys/types.h>\n#include <sys/file.h>\n#include <fcntl.h>\n#include <unistd.h>\n#include <stdlib.h>\n#include <utmp.h>\n#include <stdio.h>\n#include <paths.h>\n\nvoid\nlogin(ut)\n\tstruct utmp *ut;\n{\n\tregister int fd;\n\tint tty;\n\toff_t lseek();\n\n\ttty = ttyslot();\n\tif (tty > 0 && (fd = open(_PATH_UTMP, O_WRONLY, 0)) >= 0) {\n\t\t(void)lseek(fd, (long)(tty * sizeof(struct utmp)), L_SET);\n\t\t(void)write(fd, (char *)ut, sizeof(struct utmp));\n\t\t(void)close(fd);\n\t}\n\tif ((fd = open(_PATH_WTMP, O_WRONLY|O_APPEND, 0)) >= 0) {\n\t\t(void)write(fd, (char *)ut, sizeof(struct utmp));\n\t\t(void)close(fd);\n\t}\n}\n"
  },
  {
    "path": "lib/libutil/logout.c",
    "content": "/*\n * Copyright (c) 1988 The Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that the above copyright notice and this paragraph are\n * duplicated in all such forms and that any documentation,\n * advertising materials, and other materials related to such\n * distribution and use acknowledge that the software was developed\n * by the University of California, Berkeley.  The name of the\n * University may not be used to endorse or promote products derived\n * from this software without specific prior written permission.\n * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n */\n\n#include <sys/types.h>\n#include <sys/file.h>\n#include <sys/time.h>\n\n#include <fcntl.h>\n#include <utmp.h>\n#include <unistd.h>\n#include <paths.h>\n#include <string.h>\n\ntypedef struct utmp UTMP;\n\nint\nlogout(char *line)\n{\n\tint fd;\n\tUTMP ut;\n\tint rval;\n\toff_t lseek();\n\ttime_t time();\n\n\tif ((fd = open(_PATH_UTMP, O_RDWR)) < 0)\n\t\treturn (0);\n\trval = 0;\n\twhile (read(fd, (char *)&ut, sizeof(UTMP)) == sizeof(UTMP)) {\n\t\tif (!ut.ut_name[0] || strncmp(ut.ut_line, line, UT_LINESIZE))\n\t\t\tcontinue;\n\t\tmemset(ut.ut_name, 0, UT_NAMESIZE);\n\t\tmemset(ut.ut_host, 0, UT_HOSTSIZE);\n\t\t(void)time(&ut.ut_time);\n\t\t(void)lseek(fd, -(long)sizeof(UTMP), L_INCR);\n\t\t(void)write(fd, (char *)&ut, sizeof(UTMP));\n\t\trval = 1;\n\t}\n\t(void)close(fd);\n\treturn (rval);\n}\n"
  },
  {
    "path": "lib/libutil/logwtmp.c",
    "content": "/*\n * Copyright (c) 1988 The Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms are permitted\n * provided that the above copyright notice and this paragraph are\n * duplicated in all such forms and that any documentation,\n * advertising materials, and other materials related to such\n * distribution and use acknowledge that the software was developed\n * by the University of California, Berkeley.  The name of the\n * University may not be used to endorse or promote products derived\n * from this software without specific prior written permission.\n * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n */\n#include <sys/types.h>\n#include <sys/file.h>\n#include <sys/time.h>\n#include <sys/stat.h>\n#include <fcntl.h>\n#include <string.h>\n#include <unistd.h>\n#include <utmp.h>\n#include <paths.h>\n\nvoid\nlogwtmp(line, name, host)\n\tchar *line, *name, *host;\n{\n\tstruct utmp ut;\n\tstruct stat buf;\n\tint fd;\n\ttime_t time();\n\tchar *strncpy();\n\n\tif ((fd = open(_PATH_WTMP, O_WRONLY|O_APPEND, 0)) < 0)\n\t\treturn;\n\tif (!fstat(fd, &buf)) {\n\t\t(void)strncpy(ut.ut_line, line, sizeof(ut.ut_line));\n\t\t(void)strncpy(ut.ut_name, name, sizeof(ut.ut_name));\n\t\t(void)strncpy(ut.ut_host, host, sizeof(ut.ut_host));\n\t\t(void)time(&ut.ut_time);\n\t\tif (write(fd, (char *)&ut, sizeof(struct utmp)) !=\n\t\t    sizeof(struct utmp))\n\t\t\t(void)ftruncate(fd, buf.st_size);\n\t}\n\t(void)close(fd);\n}\n"
  },
  {
    "path": "lib/libvmf/.gitignore",
    "content": "*.0\n"
  },
  {
    "path": "lib/libvmf/Makefile",
    "content": "# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n# vmf package\n#\nTOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFILES  \t= vmf.c\nOBJS    \t= vmf.o\nPOBJS   \t= ../vmf.o\nMAN\t\t= vmf.0\nMANSRC\t\t= vmf.3\n\nCTAGS   \t= ctags\n#DEFS   \t= -DNOSCCS\n#CFLAGS\t\t+= -O ${DEFS}\nTAGSFILE\t= tags\n\nall:    \t../libvmf.a $(MAN)\n\n../libvmf.a: \t${OBJS}\n\t\t@echo building normal ../libvmf.a\n\t\t@${AR} cr ../libvmf.a ${OBJS}\n\t\t$(RANLIB) ../libvmf.a\n\n../libvmf_p.a: \t${OBJS}\n\t\t@echo building profiled ../libvmf.a\n\t\t@cd profiled; ${AR} cr ../../libvmf_p.a ${POBJS}\n\t\t$(RANLIB) ../libvmf_p.a\n\n$(MAN):         $(MANSRC)\n\t\t${MANROFF} ${MANSRC} > $@\n\ninstall: \tall\n\t\tcp ${MAN} ${DESTDIR}/usr/share/man/cat3/\n#\t\tcp ../libvmf.a ${DESTDIR}/usr/lib/libvmf.a\n#\t\t$(RANLIB) ${DESTDIR}/usr/lib/libvmf.a\n#\t\tcp ../libvmf_p.a ${DESTDIR}/usr/lib/libvmf_p.a\n#\t\t$(RANLIB) ${DESTDIR}/usr/lib/libvmf_p.a\n\nclean:\n\trm -f *.o profiled/*.o a.out core test errs ../libvmf*.a vmf.0\n"
  },
  {
    "path": "lib/libvmf/vmf.3",
    "content": ".\\\" No copyright (1993) - Steven M. Schultz (sms@wlv.iipo.gtegsc.com)\n.\\\" @(#)vmf.3\t3.0 (2.11BSD) 9/24/93\n.\\\"\n.TH VMF 3 \"September 24, 1993\"\n.UC 6\n.SH NAME\nvminit, vmopen, vmclose, vmmapseg, vmmodify, vmlock, vmunlock, vmclrseg, vmflush, \\- disk based virtual memory routines\n.SH SYNOPSIS\n.nf\n.PP\n.ft B\n#include <vmf.h>\n.PP\n.ft B\nstruct vspace {\n\tint     v_fd;           /* file for swapping */\n\toff_t   v_foffset;      /* offset for computing file addresses */\n\tint     v_maxsegno;     /* number of segments in this space */\n\t};\n.PP\n.ft B\nstruct\tvseg {                    /* structure of a segment in memory */\n\tstruct\tdlink\ts_link;\t\t/* for linking into lru list */\n\tint\ts_segno;        \t/* segment number */\n\tstruct\tvspace\t*s_vspace;      /* which virtual space */\n\tint\ts_lock_count;\n\tint     s_flags;\n\tunion\n\t\t{\n\t\tint\t_winfo[WORDSPERSEG];\t/* the actual segment */\n\t\tchar\t_cinfo[BYTESPERSEG];\n\t\t} v_un;\n\t};\n#define\ts_winfo\tv_un._winfo\n#define\ts_cinfo\tv_un._cinfo\n.PP\n.ft B\nint\tvminit(nseg);\n\tint nseg;\n.PP\n.ft B\nint\tvmopen(space, filename);\n\tstruct vspace *space;\n\tchar\t*filename;\n.PP\n.ft B\nstruct\tvseg\t*vmmapseg(space, segno);\n\tstruct\tvspace\t*space;\n\tint\tsegno;\n.PP\n.ft B\nvoid\tvmlock(seg);\n\tstruct\tvseg *seg;\n.PP\n.ft B\nvoid\tvmunlock(seg);\n\tstruct\tvseg *seg;\n.PP\n.ft B\nvoid\tvmclrseg(seg);\n\tstruct\tvseg *seg;\n.PP\n.ft B\nvoid\tvmmodify(seg);\n.PP\n.ft B\nvoid\tvmflush();\n.PP\n.ft B\nvoid\tvmclose(space);\n\tstruct\tvspace *space;\n.fi\n.bp\n.SH DESCRIPTION\nThis library provides a standard set\nof routines for managing large virtual memory spaces.  It supports\ncreation of multiple concurrent virtual spaces, mapping of virtual\npages into real memory, a lock/unlock mechanism, and a capability to\nclear specified virtual pages.\n.PP\n.IR vminit\\ -\nThis routine initializes the virtual memory system by setting up the\npool of in-memory segment buffers.  The argument to this function is\nthe number of memory segments to allocate (typically 4 to 8 but can be \nhigher as long as memory can be malloc'd).\nIt must be called before any\nother \"libvmf\" routine is called.\n.PP\n.IR vmopen\\ -\nFor each virtual space that a program uses, the program must \nallocate an instance of the space structure ('struct vspace').  \nThis routine is used to initialize\na virtual space structure using the specified address of a\nspace structure and the name of the file that will serve as \nswap file for the space.  If the second argument is \\fBNULL\\fP\nan invisible temporary file is used rather than a named (permanent)\nfile.\n.PP\n.IR vmclose\\ -\nThis routine is used to close the UNIX file descriptor associated\nwith the swap file for a virtual space.  Any modified in-memory segments\nbelonging to the specified address space are flushed to the paging file.\n.PP\n.IR vmmapseg\\ -\nThis routine is the primary interface to the virtual memory mechanism.\nIt is executed with a specified virtual space address and a segment\nnumber (between 0 and 511), and returns a pointer to an in-memory\npage containing the specified segment.\n.PP\n.IR vmmodify\\ -\nWhenever a program modifies the data of a segment, it is the program's\nresponsibility to inform the virtual memory system of the modification.\nThis function is also available as a macro\n(\\fBVMMODIFY\\fP) for use in-line.\n.PP\n.IR vmlock\\ -\nThis routine increments the lock count of the specified segment buffer.\nA buffer with a nonzero lock count is\n.I locked\nand cannot be swapped out.\n.PP\n.IR vmunlock\\ -\nThis routine decrements the lock count of the specified buffer.  It is\na serious error to decrement the count below zero (lock underflow).\n.PP\n.IR vmclrseg\\ -\nThis routine clears the user data area (page) of the specified segment buffer.\n.IR vmflush\\ -\nThis routine simply swaps out all segments that are marked as\nmodified.\n.SH BUGS\nNot as transparent (or as fast) as a larger hardware address space.\n.PP\nThere is no automatic segment crossing capability, the application must\ncheck if a\n.I virtual address\ncrosses page/segment boundaries and perform a\n.I vmmapseg\ncall.\n.SH SEE ALSO\nThere is a nroff document (using the \\-ms macros) in the \\fIlibvmf\\fP source \ndirectory which goes into more details about the \\fBvm\\fP functions.\n"
  },
  {
    "path": "lib/libvmf/vmf.c",
    "content": "/*      Program Name:   vmf.c\n *      Author:  S.M. Schultz\n *\n *      -----------   Modification History   ------------\n *      Version Date            Reason For Modification\n *      1.0     1JAN80          1. Initial release.\n *      2.0     31Mar83         2. Cleanup.\n *\t2.1\t19Oct87\t\t3. Experiment increasing number of segments.\n *\t2.2\t03Dec90\t\t4. Merged error.c into this because it had\n *\t\t\t\t   been reduced to two write() statements.\n *\t3.0\t08Sep93\t\t5. Polish it up for use in 'ld.c' (2.11BSD).\n *\t\t\t\t   Release into the Public Domain.\n *      --------------------------------------------------              \n*/\n\n#include <vmf.h>\n#include <errno.h>\n#include <fcntl.h>\n#include <stdio.h>\n#include <sys/file.h>\n#include <stdlib.h>\n#include <strings.h>\n#include <string.h>\n#include <unistd.h>\n\n/*\n * Choose ONE and only one of the following swap policies\n */\n/* #define LRU                  /* Least Recently Used */\n/* #define PERC 3               /* Percolation */\n#define LRS                     /* Least Recently Swapped */\n\n#ifndef DEBUG\n#define debugseg(s,m)           /* do nothing */\n#else\nstatic void debugseg();\n#endif\n\n/*\n * This is vfm.c, the file of virtual memory management primitives.\n * Call vminit first to get the in memory segments set up.\n * Then call vmopen for each virtual space to be used.\n * Normal transactions against segments are handled via vmmapseg.\n * At wrapup time, call vmflush if any modified segments are\n * assigned to permanent files.\n */\n\n#define NOSEGNO (-1)            /* can never match a segment number */\n\n\tstatic\tstruct dlink seghead[1];\n\tlong\tnswaps, nmapsegs;      /* statistics */\n\textern\tint\tread(), write(), errno;\n\tstatic\tint\tswap();\n\tstatic\tvoid\tpromote(), vmerror();\n\n/*\n * vminit --- initialize virtual memory system with 'n' in-memory segments\n */\n\nint\nvminit(n)\n\tint\tn;\n\t{\n\tregister struct vseg *s;\n        static struct vseg *segs;\n\n\tsegs = (struct vseg *)calloc(n, sizeof (struct vseg));\n\tif\t(!segs)\n\t\t{\n\t\terrno = ENOMEM;\n\t\treturn(-1);\n\t\t}\n        seghead[0].fwd = seghead[0].back = seghead; /* selfpoint */\n\n\tfor     (s = segs; s < &segs[n] ; s++)\n\t\t{\n\t\ts->s_link.fwd = seghead;\n\t\ts->s_link.back = seghead[0].back;\n\t\ts->s_link.back->fwd = s->s_link.fwd->back = (struct dlink *)s;\n\t\ts->s_segno = NOSEGNO;\n\t\ts->s_vspace = NULL;\n\t\ts->s_lock_count = 0;            /* vmunlocked */\n\t\ts->s_flags = 0;                 /* not DIRTY */\n\t\t}\n\treturn(0);\n\t}\n\n/*\n * vmmapseg --- convert segment number to real memory address\n */\n\nstruct vseg *\nvmmapseg(vspace, segno)\n\tstruct \tvspace *vspace;\n\tu_short segno;\n\t{\n\tregister struct vseg *s;\n\n\tnmapsegs++;\n\n\tif\t(segno >= vspace->v_maxsegno || segno < 0)\n\t\t{\n#ifdef DEBUG\n\t\tfprintf(stderr,\"vmmapseg vspace0%o segno%d\\n\", vspace, segno);\n#endif\n\t\tvmerror(\"vmmapseg: bad segno\");\n\t\t}\n\n\t/* look for segment in memory */\n\tfor\t(s = (struct vseg *)seghead[0].fwd;\n\t\t s->s_segno != segno || s->s_vspace != vspace;\n\t    \t s = (struct vseg *)s->s_link.fwd)\n\t\t{\n\t\tif\t(s == (struct vseg *)seghead)\n\t\t\t{     /* not in memory */\n\t\t\tint status;\n\n\t\t\tfor (s = (struct vseg *)s->s_link.back; s->s_lock_count != 0; \n\t\t\t\t\ts = (struct vseg *)s->s_link.back)\n\t\t\t\t{\n\t\t\t\tif (s == (struct vseg *)seghead)\n\t\t\t\t\tvmerror(\"Too many locked segs!\");\n\t\t\t\tdebugseg(s, \"back skip\");\n\t\t\t\t}\n\t\t\tdebugseg(s, \"dump on\");\n\t\t\tif\t(s->s_flags & S_DIRTY)\n\t\t\t\tif\t(swap(s, write) != 0)\n\t\t\t\t\t{\n\t\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\t\"write swap, v=%d fd=%d\\n\",\n\t\t\t\t\t\ts->s_vspace,s->s_vspace->v_fd);\n\t\t\t\t\texit(-2);\n\t\t\t\t\t}\n\t\t\ts->s_vspace = vspace;\n\t\t\ts->s_segno = segno;\n\t\t\ts->s_flags &= ~S_DIRTY;\n\t\t\tstatus = swap(s, read);\n\t\t\tif\t(status == -2)\n\t\t\t\t{\n\t\t\t\tfprintf(stderr, \"can't read swap file\");\n\t\t\t\texit(-2);\n\t\t\t\t}\n\t\t\telse if (status == -1)\n\t\t\t\t(void)vmclrseg(s);\n#ifdef LRS                              /* Least Recently Swapped */\n\t\t\tpromote(s);\n#endif\n\t\t\tbreak;\n\t\t\t}\n\t\tdebugseg(s, \"forward skip\");\n\t\t}\n#ifdef PERC\n\t{       /* percolate just-referenced segment up list */\n\tregister struct dlink *neighbor, *target;\n\tint count;\n\n\ts->fwd->back = s->back;         /* delete */\n\ts->back->fwd = s->fwd;\n\n\tcount = PERC;                   /* upward mobility */\n\tfor\t(target = s; target != seghead && count-- > 0; )\n\t\ttarget = target->back;\n\tneighbor = target->fwd;\n\ts->back = target;               /* reinsert */\n\ts->fwd = neighbor;\n\ttarget->fwd = neighbor->back = s;\n\t}\n#endif\n#ifdef LRU                              /* Least Recently Used */\n\tpromote(s);\n#endif\n\tdebugseg(s, \"vmmapseg returns\");\n\treturn(s);\n\t}\n\n/*\n * swap --- swap a segment in or out\n *      (called only from this file)\n */\n\nstatic int\nswap(seg, iofunc)           /* used only from this file */\n\tregister struct vseg *seg;\n\tint (*iofunc)();\n\t{\n\toff_t file_address;\n\tregister struct vspace *v;\n\n\tv = seg->s_vspace;\n\tnswaps++;\n\tfile_address = seg->s_segno;\n\tfile_address *= (BYTESPERSEG);\n\tfile_address += v->v_foffset;\n#ifdef SWAPTRACE\n\tprintf(\"fd%d blk%d\\tswap %s\\n\", v->v_fd, file_address,\n\t\tiofunc == read ? \"in\" : \"out\");\n#endif\n\tif\t(lseek(v->v_fd, file_address, L_SET) == -1L)\n\t\treturn(-2);\n\n\tswitch\t((*iofunc)(v->v_fd, seg->s_cinfo, BYTESPERSEG)) \n\t\t{\n\t\tcase BYTESPERSEG:\n\t\t\treturn(0);\n\t\tcase 0:\n\t\t\treturn(-1);\n\t\tdefault:\n\t\t\treturn(-2);\n\t\t}\n\t}\n\nvoid\nvmclrseg(seg)\n\tregister struct vseg *seg;\n\t{\n\n\t(void)bzero(seg->s_cinfo, BYTESPERSEG);\n\tvmmodify(seg);\n\t}\n\n/*\n * vmlock --- vmlock a segment into real memory\n */\n\nvoid\nvmlock(seg)\n\tregister struct vseg *seg;\n\t{\n\n\tseg->s_lock_count++;\n\tif\t(seg->s_lock_count < 0)\n\t\tvmerror(\"vmlock: overflow\");\n\t}\n\n/*\n * vmunlock --- unlock a segment\n */\n\nvoid\nvmunlock(seg)\n\tregister struct vseg *seg;\n\t{\n\n        --seg->s_lock_count;\n\tif\t(seg->s_lock_count < 0)\n\t\tvmerror(\"vmlock: underflow\");\n\t}\n\n/*\n * vmmodify --- declare a segment to have been modified\n */\n\nvoid\nvmmodify(seg)\nregister struct vseg *seg;\n\t{\n\n\tVMMODIFY(seg);\n\tdebugseg(seg, \"vmmodify\");\n\t}\n\n/*\n * vmflush --- flush out virtual space buffers\n */\n\nvoid\nvmflush()\n\t{\n\tregister struct vseg *s;\n\n\tfor\t(s = (struct vseg *)seghead[0].fwd; s != (struct vseg *)seghead;\n\t\t s = (struct vseg *)s->s_link.fwd)\n\t\tif\t(s->s_flags & S_DIRTY)\n\t\t\tswap(s, write);\n\t}\n\n/*\n * debugseg --- output debugging information about a seg in mem\n */\n#ifdef DEBUG\nstatic void\ndebugseg(s, msg)\n\tchar \t*msg;\n\tregister struct\tvseg *s;\n\t{\n\tfprintf(stderr, \"seg%o vspace%o segno%d flags%o vmlock%d %s\\r\\n\",\n\t\ts, s->s_vspace, s->s_segno, s->s_flags, s->s_lock_count, msg);\n\t}\n#endif\n\n/*\n * vmopen --- open a virtual space associated with a file\n */\n\nint\nvmopen(vs, filename)\n\tregister struct vspace *vs;\n\tchar *filename;\n\t{\n\tregister int\tfd;\n\tchar\tjunk[32];\n\n\tif\t(!filename)\n\t\t{\n\t\tstrcpy(junk, \"/tmp/vmXXXXXX\");\n\t\tfd = mkstemp(junk);\n\t\tunlink(junk);\n\t\t}\n\telse\n\t\tfd = open(filename, O_RDWR|O_CREAT, 0664);\n\n\tif\t(fd != -1)\n\t\t{\n\t\tvs->v_fd = fd;\n\t\tvs->v_foffset = 0;\n\t\tvs->v_maxsegno = MAXSEGNO;\n\t\t}\n\treturn(fd);\n\t}\n\n/*\n * vmclose --- closes a virtual space associated with a file\n * invalidates all segments associated with that file\n */\n\nvoid\nvmclose(vs)\n\tregister struct vspace *vs;\n\t{\n\tregister struct vseg *s;\n\n\tvmflush();\n\t/* invalidate all segments associated with that file */\n\tfor\t(s = (struct vseg *)seghead[0].fwd; s != (struct vseg *)seghead;\n\t\t s = (struct vseg *)s->s_link.fwd) \n\t\t{\n\t\tif\t(s->s_vspace == vs) \n\t\t\t{\n\t\t\ts->s_segno = NOSEGNO;\n\t\t\ts->s_vspace = NULL;\n\t\t\ts->s_lock_count = 0;            /* vmunlocked */\n\t\t\ts->s_flags &= ~S_DIRTY;\n\t\t\t}\n\t\t}\n\tclose(vs->v_fd);\n\t}\n\n/*\n * promote --- put a segment at the top of the list\n */\n\nstatic void\npromote(s)\n\tregister struct vseg *s;\n\t{\n\n        s->s_link.fwd->back = s->s_link.back;         /* delete */\n\ts->s_link.back->fwd = s->s_link.fwd;\n\n\ts->s_link.fwd = seghead[0].fwd;   /* insert at top of totem pole */\n\ts->s_link.back = seghead;\n\tseghead[0].fwd = s->s_link.fwd->back = (struct dlink *)s;\n\t}\n\n/*\n * vmerror --- print error message and commit suicide\n *      Message should always make clear where called from.\n *\tExample:\tvmerror(\"In floogle: can't happen!\");\n */\n\nstatic void\nvmerror(msg)\n\tchar *msg;\n\t{\n\tfprintf(stderr, \"%s\\n\", msg);\n\tabort();\t/* terminate process with core dump */\n\t}\n"
  },
  {
    "path": "lib/libvmf/vmlib.ms",
    "content": ".NH 1\nVMF -- Virtual Memory Facility\n.NH 2\nIntroduction\n.PP\nSince 2.11BSD is not a virtual memory operating system, a user level\n\"virtual memory\" system can be of great utility to programs with\nlarge address space requirements. This library provides a standard set\nof routines for managing large virtual memory spaces.  It supports\ncreation of multiple concurrent virtual spaces, mapping of virtual\npages into real memory, a lock/unlock mechanism, and a capability to\nclear specified virtual pages.\n.NH 3\nConcepts\n.PP\nThe virtual memory scheme supports any number (subject to open file\nlimitations) of virtual\n.I spaces,\neach of which is made up of up to 512\n.I segments\n(pages), each of which is 512 words (16 bit shorts) long.\nThe 512 ints (1024 chars) of a segment can be used for any purpose.\n.PP\nEach space may be temporary or permanent, in the sense that it is or\nis not forgotten when the program ends.  Between program invocations,\neach permanent space resides in a named file.  The most common (by\nfar) type is temporary using a file which is unlinked immediately\nafter opening the virtual address space.\n.PP\nAt any time during the lifetime of a process that uses the virtual \nmemory facility, some number of segments will be in real memory, but\ntypically most will be \"swapped out\" to a file.\nWhen the calling program knows\nthe real memory address of a segment, the segment may be viewed\nand accessed as an array of 512 integers or as an array of 1024\ncharacters.\n.NH 3\nData Structures\n.PP\nTwo structures are associated with the virtual memory scheme: the\nspace structure and the segment buffer structure.\n.IP Space\\ Structure 4\n.sp\nOne instance of the space structure must be allocated by the user for\neach space to be used.  Spaces are identified by the address of their\nspace structures.  Included in the structure is the UNIX file descriptor\nof the \"swap\" file to be used for the space, the offset (in bytes)\ninto the file at which the room allocated for the virtual space begins\n(currently this is always zero and is reserved for future use),\nand the number of segments in the space (currently always 512).  The\nuser must never be concerned with any element of the space structure.\n.IP Segment\\ Buffer\\ Structure 4\n.sp\nThe virtual memory system includes a pool of buffers for holding\nsegments while they reside in real memory.\n.sp\nThe segment buffer structure (see 'struct seg' definition below)\nincludes: a double link, the segment number (in range [0, 511]),\nthe address of the virtual space structure instance for the virtual\nspace of which the segment is a member, a lock count, a \"modified\"\nflag, and an array of 512 shorts (1024 bytes) for the segment itself.  This\narray represents the virtual page which is accessed directly by\nthe user.\n.NH 2\nDefined Constants and Global Variables\n.PP\nThe following defined symbolic constants are specified as either\ncalling parameters or returned values of the routines in the \"dtlib\"\nfacility.\n.IP MAXSEGNO 18\nSpecifies the maximum number of segments (pages) in a virtual space.\n.IP WORDSPERSEG 18\nSpecifies the number of words in a segment.\n.IP BYTESPERSEG 18\nSpecifies the number of bytes in a segment.  This is always a power of 2.\n.IP LOG2BPS 18\nThe base 2 logarithm of BYTESPERSEG.\n.PP\nThere are several global variables defined by the \"vmlib\" facility that an\napplications programmer may examine. \n.IP nswaps 18\nThis is a 32 bit value which gives the number of pages swapped to or from\nthe paging file.\n.IP nmapsegs 18\nThis 32 bit value holds the number of calls made to map a segment into\nmemory via \\fIvmmapseg\\fP.\n.PP\nThe following\ndefined \"C\" Language structures are specified as calling parameters\nand/or returned values of the routines in the \"vmlib\" facility.\n.PP\n.nf\nstruct vspace {\n\tint     v_fd;           /* file for swapping */\n\toff_t   v_foffset;      /* offset for computing file addresses */\n\tint     v_maxsegno;     /* number of segments in this space */\n\t};\n\nstruct dlink {                  /* general double link structure */\n\tstruct dlink *fwd;      /* forward link */\n\tstruct dlink *back;     /* back link */\n\t};\n\nstruct\tvseg {                    /* structure of a segment in memory */\n\tstruct\tdlink\ts_link;\t\t/* for linking into lru list */\n\tint\ts_segno;        \t/* segment number */\n\tstruct\tvspace\t*s_vspace;      /* which virtual space */\n\tint\ts_lock_count;\n\tint     s_flags;\n\tunion\n\t\t{\n\t\tint\t_winfo[WORDSPERSEG];\t/* the actual segment */\n\t\tchar\t_cinfo[BYTESPERSEG];\n\t\t} v_un;\n\t};\n\n#define\ts_winfo\tv_un._winfo\n#define\ts_cinfo\tv_un._cinfo\n.fi\n.NH 2\nRoutine Synopsis\n.PP\nBelow are listed the names of each function\nin the \"vmlib\" facility along with a brief synopsis\nof what each routine does.\n.IP vminit 14\nThis routine initializes the virtual memory system by setting up the\npool of in-memory segment buffers.  The argument to this function is\nthe number (typically 4 to 8 but can be higher as long as memory\ncan be malloc'd).\nIt must be called before any\nother \"vmlib\" facility routine is called.\n.IP vmopen 14\nFor each virtual space that a program uses, the program must \nallocate an instance of the space structure (see definition \nof 'struct vspace' above).  This routine is used to initialize\na virtual space structure using the specified address of a\nspace structure and the name of the file that will serve as \nswap file for the space.  If the second argument is \\fBNULL\\fP\nan invisible temporary file is used rather than a named (permanent)\nfile.\n.IP vmclose 14\nThis routine is used to close the UNIX file descriptor associated\nwith the swap file for a virtual space.  Any modified in-memory segments\nbelonging to the specified address space are flushed to the paging file.\n.IP vmmapseg 14\nThis routine is the primary interface to the virtual memory mechanism.\nIt is executed with a specified virtual space address and a segment\nnumber ( in range [0, 511]), and returns a pointer to an in-memory\npage containing the specified segment.\n.IP vmmodify 14\nWhenever a program modifies the data of a segment, it is the program's\nresponsibility to inform the virtual memory system of the modification.\nThis routine flags the specified segment as modified and should be\nexecuted before any future execution of 'vmmapseg' that could overlay\nthe modified buffer.  This function is also available as a macro\n(\\fBVMMODIFY\\fP) for use in-line.  The macro form is actually preferred\nsince only a single bit is being set in a word.\n.IP vmlock 14\nThis routine increments the lock count of the specified segment buffer.\nA buffer with a nonzero lock count is\n.I locked\nand cannot be overlayed.  The utility of this feature to the user is\nthat a locked segment buffer will stay at the same real memory address\nuntil unlocked, hence real memory pointers into or to it can remain\nvalid.  Overuse of this feature will result in not being able to page\nany new segments into memory from the paging file.\n.IP vmunlock 14\nThis routine decrements the lock count of the specified buffer.  It is\na serious error to decrement the count below zero (lock underflow).\n.IP vmclrseg 14\nThis routine clears the user data area (page) of the specified segment buffer.\n.IP vmflush 14\nThis routine simply swaps out all segments that are marked as\n\"modified\".  It may be called at any time and is always called when\n\\fIvmclose\\fP is called.\n.bp\n.NH 2\nDetailed Description of Virtual Memory Functions\n.NH 3\nvminit -- Initialize Virtual Memory Interface\n.NH 4\n.PP\nThe \"vminit\" routine initializes the virtual memory system by setting up the\npool of in-memory segment buffers.  It must be called before any\nother \"vmlib\" facility routine is called.\n.NH 4\nCALLING SEQUENCE\n.PP\n.in +8\n.nf\nstatus = vminit(nseg)\n\nint nseg;\nint status;\n.fi\n.in -8\n.IP status\nThe return value will be \\-1 and \\fIerrno\\fP will be set to ENOMEM\nif memory for\nthe specified number of segments can not be allocated.\n.IP nseg\nThis is the number of in-memory segments to allocate.  These are shared\nbetween all virtual spaces opened.  Each segment is 1kb plus overhead,\nso the number of segments should be chosen with care (if all data could\nbe held in memory we wouldn't need a virtual memory system after all).\nTypical number of segments is between 4 and 8 although some applications\nsuch as \\fBld\\fP(1) use 12 or more.\n.NH 3\nvmopen -- Open a Virtual Space\n.NH 4\n.PP\nFor each virtual space that a program uses, the program must \nallocate an instance of the space structure (see definition \nof 'struct vspace' above).  The \"vmopen\" routine is used to initialize\na virtual space structure using the specified address of a\nspace structure and the name of the file that will serve as \nswap file for the space.  If the filename is NULL then an invisible\ntemporary file created in /tmp will be used and the address space\nwill be vanish when the program exits or calls \\fIvmclose\\fP.\n.NH 4\nCALLING SEQUENCE\n.PP\n.in +8\n.nf\nstatus = vmopen(vsptr,filename)\n\nstruct vspace   *vsptr;\nchar *filename;\nint status;\n.fi\n.in -8\n.IP status\nIndicates success if 0, an error if \\-1.  An error is caused by failure\nto create (or open for update) the specified file.  The global \\fBerrno\\fP\nwill be set if \\-1 is returned by \\fIvmopen\\fP.\n.NH 3\nvmclose -- Close a Virtual Space\n.NH 4\n.PP\nClose the UNIX file descriptor associated with the swap \nfile for a virtual space.  Modified segments belonging to the specified\nvirtual space are flushed.\n.NH 4\nCALLING SEQUENCE\n.PP\n.in +8\n.nf\nvoid vmclose(vsptr)\n\nstruct vspace   *vsptr;\n.fi\n.in -8\n.IP vsptr\nThe address of the virtual space structure to be closed.  No status is\nreturned.\n.NH 3\nvmmapseg -- Map a Virtual Segment into Real Memory\n.NH 4\n.PP\nThe \"vmmapseg\" routine is the primary interface to the virtual memory mechanism.\nIt is executed with a specified virtual space address and a segment\nnumber ( in range [0, 511]), and returns the real memory address\nof a buffer guaranteed to contain the segment requested.  The address \nreturned is that of the 'struct vseg' not that of the data portion.  It\nis up to the program to refer to the 's_cinfo' or 's_winfo' member \nto refer to the byte or word oriented data respectively.\n.NH 4\nCALLING SEQUENCE\n.PP\n.in +8\n.nf\nsegptr = vmmapseg(vsptr,segno)\n\nstruct vspace *vsptr;\nint segno;\nstruct vseg *segptr;\n.fi\n.in -8\n.NH 4\n.IP vsptr\nSpecifies the address of a virtual space structure allocated by\nthe calling program.  A previous vmopen call using this structure\nmust have been performed before calling \\fIvmmapseg\\fP.\n.IP segno\nSpecifies the segment i.e., virtual page, number to be mapped into\nreal physical memory.  The value must be in the range [0 to MAXSEGNO-1].\nThere are two macros (defined in \\fIvmf.h\\fP) which are useful in\ncalculating segment numbers: \\fBVSEG\\fP and \\fBVOFF\\fP.\n.IP segptr\nThe address of a virtual seg structure which contains the virtual\nspace segment associated with segno.  The data is referred to with\nthe 's_cinfo' or 's_winfo' structure members:  segptr->s_cinfo\nor segptr->s_winfo respectively.\n.PP\nCurrently this routine aborts the program on an error condition.\n.NH 3\nvmmodify -- Mark a Segment as Modified\n.NH 4\n.PP\nWhenever the user program modifies any segment, it is the program's\nresponsibility to inform the virtual memory system of the modification.\nThe \"vmmodify\" routine flags the specified segment as modified and should be\nexecuted before any future execution of 'vmmapseg' that could reuse\nthe modified buffer.  Note that a locked segment buffer cannot be reused,\nuntil it is unlocked.  A macro form of this routine exists, \\fBVMMODIFY\\fP\nmay be used to mark a segment as modified.\n.NH 4\nCALLING SEQUENCE\n.PP\n.in +8\n.nf\nvoid vmmodify(segptr)\n\nstruct vseg *segptr;\n.fi\n.in -8\n.IP segptr\nSpecifies the address of a seg structure associated with a current\nincore virtual memory segment which has been modified.\n.NH 3\nvmlock -- Lock a Virtual Segment into Real Memory\n.NH 4\n.PP\nIncrement the lock count of the specified segment buffer.\nA buffer with a nonzero lock count is\n.I locked\nand cannot be reused/swapped-out.  The utility of this feature to the user is\nthat a locked segment buffer will stay at the same real memory address\nuntil unlocked, hence real memory pointers into or to it can remain\nvalid.  Overuse of \\fIvmlock\\fP will cause errors in \\fIvmmapseg\\fP\nwhen no segments are available to satisfy swap in/out requests.\n.NH 4\nCALLING SEQUENCE\n.PP\n.in +8\n.nf\nvoid vmlock(segptr1)\n\nstruct vseg      *segptr;\n.fi\n.in -8\n.NH 4\n.IP segptr\nSpecifies the address of a seg structure associated with a current\nincore virtual memory segment.  No information is returned.\n.NH 3\nvmunlock -- Unlock a Previously Locked Virtual Memory Segment\n.NH 4\n.PP\nDecrement the lock count of the specified buffer.  It is a serious error\nto decrement the count below zero, this typically means that the segment\nwas never locked in the first place.\n.NH 4\nCALLING SEQUENCE\n.PP\n.in +8\n.nf\nvoid vmunlock(segptr)\n\nstruct vseg      *segptr;\n.fi\n.in -8\n.NH 4\n.IP segptr1\nSpecifies the address of a seg structure associated with a current\nincore virtual memory segment.  No information is returned from this\nroutine.\n.NH 3\nvmclrseg -- Clear a Virtual Memory Segment to Zeros\n.NH 4\n.PP\nClear the data area of the specified segement buffer.  No information is\nreturned by this function.\n.NH 4\nCALLING SEQUENCE\n.PP\n.in +8\n.nf\nvoid vmclrseg(segptr)\n\nstruct vseg      *segptr\n.fi\n.in -8\n.NH 4\n.IP segptr\nSpecifies the address of a seg structure associated with a current\nincore virtual memory segment.  The data portion (segptr->s_cinfo)\nis cleared by a call to \\fIbzero\\fP(3).\n.NH 3\nvmflush -- Flush Virtual Memory Cache to Swap File\n.NH 4\n.PP\nSwap out all segments that are marked as\n\"modified\". It may be called just prior to program termination\nif there are any permanent spaces that have been modified but \nnormally a program will simply call \\fIvmclose\\fP which takes care\nof flushing modified pages as part of its normal duties.\n.NH 4\nCALLING SEQUENCE\n.PP\n.in +8\n.nf\nvoid vmflush()\n.fi\n.in -8\n"
  },
  {
    "path": "lib/libwiznet/Makefile",
    "content": "TOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS          += -O -Wall\n\nOBJS    \t= w5100.o socket.o ethernet.o client.o server.o udp.o\n\nall:    \t../libwiznet.a\n\n../libwiznet.a: ${OBJS}\n\t\t@${AR} cr $@ ${OBJS}\n\t\t$(RANLIB) $@\n\ninstall: \tall\n\nclean:\n\t\trm -f *.o a.out core test errs ../libwiznet*.a\n"
  },
  {
    "path": "lib/libwiznet/client.c",
    "content": "#include <string.h>\n#include <unistd.h>\n#include <wiznet/ethernet.h>\n#include <wiznet/socket.h>\n\nunsigned _client_srcport = 1024;\n\nvoid client_init (client_t *c, uint8_t *ip, unsigned port)\n{\n    c->ip = ip;\n    c->port = port;\n    c->sock = MAX_SOCK_NUM;\n}\n\nvoid client_init_sock (client_t *c, unsigned sock)\n{\n    c->sock = sock;\n}\n\nint client_connect (client_t *c)\n{\n    int i;\n\n    if (c->sock != MAX_SOCK_NUM)\n        return 0;\n\n    for (i = 0; i < MAX_SOCK_NUM; i++) {\n        unsigned s = w5100_readSnSR (i);\n        if (s == SnSR_CLOSED || s == SnSR_FIN_WAIT) {\n            c->sock = i;\n            break;\n        }\n    }\n\n    if (c->sock == MAX_SOCK_NUM)\n        return 0;\n\n    _client_srcport++;\n    if (_client_srcport == 0)\n        _client_srcport = 1024;\n    socket_init (c->sock, SnMR_TCP, _client_srcport, 0);\n\n    if (! socket_connect (c->sock, c->ip, c->port)) {\n        c->sock = MAX_SOCK_NUM;\n        return 0;\n    }\n\n    while (client_status(c) != SnSR_ESTABLISHED) {\n        usleep (10000);\n        if (client_status(c) == SnSR_CLOSED) {\n            c->sock = MAX_SOCK_NUM;\n            return 0;\n        }\n    }\n    return 1;\n}\n\nvoid client_putc (client_t *c, uint8_t b)\n{\n    if (c->sock != MAX_SOCK_NUM)\n        socket_send (c->sock, &b, 1);\n}\n\nvoid client_puts (client_t *c, const char *str)\n{\n    if (c->sock != MAX_SOCK_NUM)\n        socket_send (c->sock, (const uint8_t *)str, strlen(str));\n}\n\nvoid client_write (client_t *c, const uint8_t *buf, size_t size)\n{\n    if (c->sock != MAX_SOCK_NUM)\n        socket_send (c->sock, buf, size);\n}\n\nint client_available (client_t *c)\n{\n    if (c->sock != MAX_SOCK_NUM)\n        return w5100_getRXReceivedSize (c->sock);\n    return 0;\n}\n\nint client_getc (client_t *c)\n{\n    uint8_t b;\n\n    if (socket_recv (c->sock, &b, 1) <= 0) {\n        // No data available\n        return -1;\n    }\n    return b;\n}\n\nint client_read (client_t *c, uint8_t *buf, size_t size)\n{\n    return socket_recv (c->sock, buf, size);\n}\n\nint client_peek (client_t *c)\n{\n    uint8_t b;\n\n    // Unlike recv, peek doesn't check to see if there's any data available, so we must\n    if (! client_available (c))\n      return -1;\n\n    b = socket_peek (c->sock);\n    return b;\n}\n\nvoid client_flush (client_t *c)\n{\n    while (client_available (c))\n        client_getc (c);\n}\n\nvoid client_stop (client_t *c)\n{\n    int i;\n\n    if (c->sock == MAX_SOCK_NUM)\n        return;\n\n    // attempt to close the connection gracefully (send a FIN to other side)\n    socket_disconnect (c->sock);\n\n    // wait a second for the connection to close\n    for (i=0; i<100; i++) {\n        if (client_status (c) == SnSR_CLOSED)\n            break;\n        usleep (10000);\n    }\n\n    // if it hasn't closed, close it forcefully\n    if (client_status(c) != SnSR_CLOSED)\n        socket_close (c->sock);\n\n    _socket_port[c->sock] = 0;\n    c->sock = MAX_SOCK_NUM;\n}\n\nint client_connected (client_t *c)\n{\n    if (c->sock == MAX_SOCK_NUM)\n        return 0;\n\n    unsigned s = client_status (c);\n    return ! (s == SnSR_LISTEN || s == SnSR_CLOSED || s == SnSR_FIN_WAIT ||\n        (s == SnSR_CLOSE_WAIT && ! client_available (c)));\n}\n\nunsigned client_status (client_t *c)\n{\n    if (c->sock == MAX_SOCK_NUM)\n        return SnSR_CLOSED;\n    return w5100_readSnSR (c->sock);\n}\n"
  },
  {
    "path": "lib/libwiznet/ethernet.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <arpa/inet.h>\n#include <wiznet/ethernet.h>\n#include <wiznet/w5100.h>\n\nunsigned char ethernet_mac [6];\nunsigned char ethernet_ip [4];\nunsigned char ethernet_gateway [4];\nunsigned char ethernet_netmask [4];\n\n/*\n * Get MAC address from string to byte array.\n */\nstatic void parse_mac (unsigned char *macp, char *str)\n{\n    unsigned char *limit = macp + 6;\n    register unsigned c, val;\n\n    do {\n        /* Collect number up to \":\". */\n        val = 0;\n        while ((c = (unsigned char) *str)) {\n            if (c >= '0' && c <= '9')\n                val = (val << 4) + (c - '0');\n            else if (c >= 'a' && c <= 'f')\n                val = (val << 4) + (c - 'a' + 10);\n            else if (c >= 'A' && c <= 'F')\n                val = (val << 4) + (c - 'A' + 10);\n            else\n                break;\n            str++;\n        }\n        *macp++ = val;\n    } while (*str++ == ':' && macp < limit);\n}\n\n/*\n * Get IP address from string to byte array.\n */\nstatic void parse_ip (unsigned char *val, char *str)\n{\n    unsigned long addr;\n\n    if (! str)\n        return;\n    addr = inet_addr (str);\n    val[0] = addr >> 0;\n    val[1] = addr >> 8;\n    val[2] = addr >> 16;\n    val[3] = addr >> 24;\n}\n\n/*\n * Initialize Ethernet controller.\n * Get parameters from environment:\n *  MAC=aa:bb:cc:dd:ee:ff   - unique MAC address\n *  IP=12.34.56.78          - IP address\n *  GATEWAY=12.34.56.1      - gateway to Internet (optional)\n *  NETMASK=255.255.255.0   - netmask of local Ethernet network (optional)\n */\nvoid ethernet_init ()\n{\n    char *mac, *ip, *gateway, *netmask;\n\n    mac = getenv(\"MAC\");\n    if (! mac) {\n        fprintf (stderr, \"Please set MAC environment variable\\n\");\n        exit (-1);\n    }\n    parse_mac (ethernet_mac, mac);\n\n    ip = getenv(\"IP\");\n    if (! ip) {\n        fprintf (stderr, \"Please set IP environment variable\\n\");\n        exit (-1);\n    }\n    parse_ip (ethernet_ip, ip);\n\n    gateway = getenv(\"GATEWAY\");\n    if (gateway != 0) {\n        parse_ip (ethernet_gateway, gateway);\n    } else {\n        ethernet_gateway[0] = ethernet_ip[0];\n        ethernet_gateway[1] = ethernet_ip[1];\n        ethernet_gateway[2] = ethernet_ip[2];\n        ethernet_gateway[3] = 1;\n    }\n\n    netmask = getenv(\"NETMASK\");\n    if (netmask != 0) {\n        parse_ip (ethernet_netmask, netmask);\n    } else {\n        ethernet_netmask[0] = 255;\n        ethernet_netmask[1] = 255;\n        ethernet_netmask[2] = 255;\n        ethernet_netmask[3] = 0;\n    }\n    printf(\"local MAC address %02x:%02x:%02x:%02x:%02x:%02x\\n\",\n        ethernet_mac[0], ethernet_mac[1], ethernet_mac[2],\n        ethernet_mac[3], ethernet_mac[4], ethernet_mac[5]);\n    printf(\"local IP address %u.%u.%u.%u\\n\",\n        ethernet_ip[0], ethernet_ip[1],\n        ethernet_ip[2], ethernet_ip[3]);\n    printf(\"gateway %u.%u.%u.%u\\n\",\n        ethernet_gateway[0], ethernet_gateway[1],\n        ethernet_gateway[2], ethernet_gateway[3]);\n    printf(\"netmask %u.%u.%u.%u\\n\",\n        ethernet_netmask[0], ethernet_netmask[1],\n        ethernet_netmask[2], ethernet_netmask[3]);\n\n    w5100_init();\n\n    /* Set Ethernet MAC address. */\n    w5100_writeSHAR (ethernet_mac);\n\n    /* Set local IP address. */\n    w5100_writeSIPR (ethernet_ip);\n\n    /* Set gateway IP address. */\n    w5100_writeGAR (ethernet_gateway);\n\n    /* Set subnet mask. */\n    w5100_writeSUBR (ethernet_netmask);\n\n    /* Set retransmission timeout to 200 msec. */\n    w5100_writeRTR (200*10);\n\n    /* Set retransmission count. */\n    //w5100_writeRCR (3);\n}\n"
  },
  {
    "path": "lib/libwiznet/server.c",
    "content": "#include <string.h>\n#include <wiznet/socket.h>\n#include <wiznet/server.h>\n\nunsigned _server_port;\n\nvoid server_init (unsigned port)\n{\n    unsigned sock;\n    client_t client;\n\n    _server_port = port;\n    for (sock = 0; sock < MAX_SOCK_NUM; sock++) {\n        client_init_sock (&client, sock);\n\n        if (client_status (&client) == SnSR_CLOSED) {\n            socket_init (sock, SnMR_TCP, port, 0);\n            socket_listen (sock);\n            _socket_port[sock] = port;\n            break;\n        }\n    }\n}\n\nvoid server_accept()\n{\n    unsigned sock;\n    client_t client;\n    int listening = 0;\n\n    for (sock = 0; sock < MAX_SOCK_NUM; sock++) {\n        client_init_sock (&client, sock);\n\n        if (_socket_port[sock] == _server_port) {\n            if (client_status (&client) == SnSR_LISTEN) {\n                listening = 1;\n            }\n            else if (client_status (&client) == SnSR_CLOSE_WAIT &&\n                     ! client_available (&client)) {\n                client_stop (&client);\n            }\n        }\n    }\n\n    if (! listening) {\n        server_init (_server_port);\n    }\n}\n\nint server_available (client_t *client)\n{\n    unsigned sock;\n\n    server_accept();\n\n    for (sock = 0; sock < MAX_SOCK_NUM; sock++) {\n        client_init_sock (client, sock);\n\n        if (_socket_port[sock] == _server_port &&\n              (client_status (client) == SnSR_ESTABLISHED ||\n               client_status (client) == SnSR_CLOSE_WAIT)) {\n            if (client_available (client)) {\n                // XXX: don't always pick the lowest numbered socket.\n                return 1;\n            }\n        }\n    }\n    return 0;\n}\n\nvoid server_putc (uint8_t b)\n{\n    server_write (&b, 1);\n}\n\nvoid server_puts (const char *str)\n{\n    server_write ((const uint8_t *)str, strlen(str));\n}\n\nvoid server_write (const uint8_t *buffer, size_t size)\n{\n    unsigned sock;\n    client_t client;\n\n    server_accept();\n\n    for (sock = 0; sock < MAX_SOCK_NUM; sock++) {\n        client_init_sock (&client, sock);\n\n        if (_socket_port[sock] == _server_port &&\n          client_status (&client) == SnSR_ESTABLISHED) {\n            client_write (&client, buffer, size);\n        }\n    }\n}\n"
  },
  {
    "path": "lib/libwiznet/socket.c",
    "content": "#include <stdio.h>\n#include <unistd.h>\n#include <wiznet/socket.h>\n\nunsigned _socket_port [MAX_SOCK_NUM] = { 0 };\n\nstatic unsigned local_port;\n\n/*\n * This Socket function initialize the channel in perticular mode,\n * and set the port and wait for W5100 done it.\n * Return 1 for success else 0.\n */\nunsigned socket_init (unsigned sock, unsigned protocol, unsigned port, unsigned flag)\n{\n    if ((protocol == SnMR_TCP) || (protocol == SnMR_UDP) ||\n        (protocol == SnMR_IPRAW) || (protocol == SnMR_MACRAW) ||\n        (protocol == SnMR_PPPOE))\n    {\n        socket_close (sock);\n        w5100_writeSnMR (sock, protocol | flag);\n        if (port != 0) {\n            w5100_writeSnPORT (sock, port);\n        } else {\n            /* if don't set the source port, set local_port number. */\n            local_port++;\n            w5100_writeSnPORT (sock, local_port);\n        }\n\n        w5100_socket_cmd (sock, Sock_OPEN);\n        return 1;\n    }\n    return 0;\n}\n\n/*\n * This function close the socket and parameter is \"sock\" which represent\n * the socket number.\n */\nvoid socket_close (unsigned sock)\n{\n    w5100_socket_cmd (sock, Sock_CLOSE);\n    w5100_writeSnIR (sock, 0xFF);\n}\n\n/*\n * This function established the connection for the channel in passive\n * (server) mode. This function waits for the request from the peer.\n * Return 1 for success else 0.\n */\nunsigned socket_listen (unsigned sock)\n{\n    if (w5100_readSnSR (sock) != SnSR_INIT)\n        return 0;\n    w5100_socket_cmd (sock, Sock_LISTEN);\n    return 1;\n}\n\n/*\n * This function established  the connection for the channel in Active\n * (client) mode.  This function waits for the untill the connection\n * is established.\n * Return 1 for success else 0.\n */\nunsigned socket_connect (unsigned sock, uint8_t * addr, unsigned port)\n{\n    if (((addr[0] == 0xFF) && (addr[1] == 0xFF) &&\n         (addr[2] == 0xFF) && (addr[3] == 0xFF)) ||\n        ((addr[0] == 0x00) && (addr[1] == 0x00) &&\n         (addr[2] == 0x00) && (addr[3] == 0x00)) ||\n        (port == 0))\n      return 0;\n\n    /* set destination IP */\n    w5100_writeSnDIPR (sock, addr);\n    w5100_writeSnDPORT (sock, port);\n    w5100_socket_cmd (sock, Sock_CONNECT);\n    return 1;\n}\n\n/*\n * This function used for disconnect the socket and parameter is \"sock\"\n * which represent the socket number\n * Return 1 for success else 0.\n */\nvoid socket_disconnect (unsigned sock)\n{\n    w5100_socket_cmd (sock, Sock_DISCON);\n}\n\n/*\n * This function used to send the data in TCP mode\n * Return 1 for success else 0.\n */\nunsigned socket_send (unsigned sock, const uint8_t * buf, unsigned nbytes)\n{\n    unsigned status = 0;\n    unsigned freesize = 0;\n\n    /* check size not to exceed MAX size. */\n    if (nbytes > TXBUF_SIZE)\n        nbytes = TXBUF_SIZE;\n\n    /* if freebuf is available, start. */\n    do {\n        freesize = w5100_getTXFreeSize (sock);\n        status = w5100_readSnSR (sock);\n        if ((status != SnSR_ESTABLISHED) &&\n            (status != SnSR_CLOSE_WAIT)) {\n            return 0;\n        }\n    } while (freesize < nbytes);\n\n    /* copy data */\n    w5100_send_chunk (sock, buf, nbytes);\n    w5100_socket_cmd (sock, Sock_SEND);\n\n    /* +2008.01 bj */\n    while ((w5100_readSnIR (sock) & SnIR_SEND_OK) != SnIR_SEND_OK) {\n        /* m2008.01 [bj] : reduce code */\n        if (w5100_readSnSR (sock) == SnSR_CLOSED) {\n          socket_close (sock);\n          return 0;\n        }\n    }\n    /* +2008.01 bj */\n    w5100_writeSnIR (sock, SnIR_SEND_OK);\n    return nbytes;\n}\n\n/*\n * This function is an application I/F function which is used to receive\n * the data in TCP mode.  It continues to wait for data as much as\n * the application wants to receive.\n * Return received data size for success else -1.\n */\nunsigned socket_recv (unsigned sock, uint8_t *buf, unsigned len)\n{\n    /* Check how much data is available */\n    unsigned navail = w5100_getRXReceivedSize (sock);\n    if (navail == 0) {\n        /* No data available. */\n        w5100_readSnSR (sock);\n\n        if (sock == SnSR_LISTEN ||\n            sock == SnSR_CLOSED ||\n            sock == SnSR_CLOSE_WAIT)\n        {\n            /* The remote end has closed its side of the connection,\n             * so this is the eof state */\n            return 0;\n        }\n        /* The connection is still up, but there's no data waiting\n         * to be read */\n        return -1;\n    }\n\n    if (navail > len) {\n        navail = len;\n    }\n\n    w5100_recv_chunk (sock, buf, navail);\n    w5100_socket_cmd (sock, Sock_RECV);\n    return navail;\n}\n\n/*\n * Returns the first byte in the receive queue (no checking)\n */\nunsigned socket_peek (unsigned sock)\n{\n    return w5100_recv_peek (sock);\n}\n\n/*\n * This function is an application I/F function which is used to send\n * the data for other then TCP mode.  Unlike TCP transmission, the peer's\n * destination address and the port is needed.\n *\n * This function return send data size for success else -1.\n */\nunsigned socket_sendto (unsigned sock, const uint8_t *buf, unsigned len, uint8_t *addr, unsigned port)\n{\n    unsigned ret = 0;\n\n    /* check size not to exceed MAX size. */\n    if (len > TXBUF_SIZE)\n        ret = TXBUF_SIZE;\n    else\n        ret = len;\n\n    if (((addr[0] == 0x00) && (addr[1] == 0x00) &&\n         (addr[2] == 0x00) && (addr[3] == 0x00)) ||\n        (port == 0) || (ret == 0)) {\n        /* +2008.01 [bj] : added return value */\n        ret = 0;\n    } else {\n        w5100_writeSnDIPR (sock, addr);\n        w5100_writeSnDPORT (sock, port);\n\n        /* copy data */\n        w5100_send_chunk (sock, buf, ret);\n        w5100_socket_cmd (sock, Sock_SEND);\n\n        /* +2008.01 bj */\n        while ((w5100_readSnIR (sock) & SnIR_SEND_OK) != SnIR_SEND_OK) {\n            if (w5100_readSnIR (sock) & SnIR_TIMEOUT) {\n                /* +2008.01 [bj]: clear interrupt */\n                /* clear SEND_OK & TIMEOUT */\n                w5100_writeSnIR (sock, SnIR_SEND_OK | SnIR_TIMEOUT);\n                return 0;\n            }\n        }\n\n        /* +2008.01 bj */\n        w5100_writeSnIR (sock, SnIR_SEND_OK);\n    }\n    return ret;\n}\n\n/*\n * This function is an application I/F function which is used to receive\n * the data in other then TCP mode.  This function is used to receive UDP,\n * IP_RAW and MAC_RAW mode, and handle the header as well.\n *\n * This function return received data size for success else -1.\n */\nunsigned socket_recvfrom (unsigned sock, uint8_t *buf, unsigned len,\n    uint8_t *addr, unsigned *port)\n{\n    uint8_t head[8];\n    unsigned nreceived = 0;\n    unsigned ptr, mode;\n\n    if (len <= 0)\n        return 0;\n\n    ptr = w5100_readSnRX_RD (sock);\n    mode = w5100_readSnMR (sock);\n    W5100_DEBUG (\"socket_recvfrom: mode %02x, RX pointer = %04x\\n\", mode, ptr);\n\n    switch (mode & 0x07) {\n    case SnMR_UDP:\n        w5100_read_data (sock, ptr, head, 8);\n        ptr += 8;\n\n        /* read peer's IP address, port number. */\n        W5100_DEBUG (\"UDP peer %u.%u.%u.%u, port %u\\n\",\n            head[0], head[1], head[2], head[3], (head[4] << 8) | head[5]);\n        if (addr) {\n            addr[0] = head[0];\n            addr[1] = head[1];\n            addr[2] = head[2];\n            addr[3] = head[3];\n        }\n        if (port)\n            *port = (head[4] << 8) | head[5];\n\n        nreceived = (head[6] << 8) + head[7];\n        break;\n\n    case SnMR_IPRAW:\n        w5100_read_data (sock, ptr, head, 6);\n        ptr += 6;\n\n        /* read peer's IP address. */\n        W5100_DEBUG (\"IPRAW peer %u.%u.%u.%u\\n\",\n            head[0], head[1], head[2], head[3]);\n        if (addr) {\n            addr[0] = head[0];\n            addr[1] = head[1];\n            addr[2] = head[2];\n            addr[3] = head[3];\n        }\n        nreceived = (head[4] << 8) + head[5];\n        break;\n\n    case SnMR_MACRAW:\n        w5100_read_data (sock, ptr, head, 2);\n        ptr += 2;\n\n        nreceived = (head[0] << 8) + head[1] - 2;\n        break;\n\n    default:\n        W5100_DEBUG (\"unknown mode %02x\\n\", mode);\n        return 0;\n    }\n    W5100_DEBUG (\"received %u bytes\\n\", nreceived);\n\n    /* data copy. */\n    w5100_read_data (sock, ptr, buf, nreceived);\n    ptr += nreceived;\n\n    w5100_writeSnRX_RD (sock, ptr);\n    W5100_DEBUG (\"set RX pointer = %04x\\n\", ptr);\n\n    w5100_socket_cmd (sock, Sock_RECV);\n    return nreceived;\n}\n\nunsigned socket_igmpsend (unsigned sock, const uint8_t * buf, unsigned len)\n{\n    unsigned ret = 0;\n\n    if (len > TXBUF_SIZE)\n        ret = TXBUF_SIZE; /* check size not to exceed MAX size. */\n    else\n        ret = len;\n\n    if (ret == 0)\n        return 0;\n\n    w5100_send_chunk (sock, buf, ret);\n    w5100_socket_cmd (sock, Sock_SEND);\n\n    while ((w5100_readSnIR (sock) & SnIR_SEND_OK) != SnIR_SEND_OK) {\n        w5100_readSnSR (sock);\n        if (w5100_readSnIR (sock) & SnIR_TIMEOUT) {\n            /* in case of igmp, if send fails, then socket closed */\n            /* if you want change, remove this code. */\n            socket_close (sock);\n            return 0;\n        }\n    }\n\n    w5100_writeSnIR (sock, SnIR_SEND_OK);\n    return ret;\n}\n"
  },
  {
    "path": "lib/libwiznet/udp.c",
    "content": "/*\n * Udp.cpp: Library to send/receive UDP packets with the Arduino ethernet shield.\n * This version only offers minimal wrapping of socket.c/socket.h\n *\n * MIT License:\n * Copyright (c) 2008 Bjoern Hartmann\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n * in the Software without restriction, including without limitation the rights\n * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n * copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in\n * all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n * THE SOFTWARE.\n *\n * bjoern@cs.stanford.edu 12/30/2008\n */\n#include <string.h>\n#include <wiznet/socket.h>\n#include <wiznet/ethernet.h>\n#include <wiznet/udp.h>\n\n/*\n * Start UDP socket, listening at local port PORT\n */\nint udp_init (udp_t *u, unsigned port)\n{\n    int i;\n\n    for (i = 0; i < MAX_SOCK_NUM; i++) {\n        uint8_t s = w5100_readSnSR(i);\n        if (s == SnSR_CLOSED || s == SnSR_FIN_WAIT) {\n            u->sock = i;\n            break;\n        }\n    }\n\n    if (u->sock == MAX_SOCK_NUM)\n        return 0;\n\n    u->port = port;\n    socket_init (u->sock, SnMR_UDP, u->port, 0);\n    return 1;\n}\n\n/*\n * Is data available in rx buffer?\n * Returns 0 if no, number of available bytes if yes.\n * returned value includes 8 byte UDP header!\n */\nunsigned udp_available (udp_t *u)\n{\n    return w5100_getRXReceivedSize (u->sock);\n}\n\n/*\n * Release any resources being used by this UDP instance.\n */\nvoid udp_stop (udp_t *u)\n{\n    if (u->sock == MAX_SOCK_NUM)\n        return;\n\n    socket_close (u->sock);\n\n    _socket_port[u->sock] = 0;\n    u->sock = MAX_SOCK_NUM;\n}\n\n/*\n * Send packet contained in buf of length len to peer at specified ip, and port.\n * Use this function to transmit binary data that might contain 0x00 bytes.\n * This function returns sent data size for success else -1.\n */\nunsigned udp_send_packet (udp_t *u, const uint8_t *buf, unsigned len,\n                          uint8_t *ip, unsigned port)\n{\n    return socket_sendto (u->sock, buf, len, ip, port);\n}\n\n/*\n * Send zero-terminated string str as packet to peer at specified ip, and port.\n * This function returns sent data size for success else -1.\n */\nunsigned udp_send_string (udp_t *u, const char *str,\n                          uint8_t *ip, unsigned port)\n{\n    unsigned len = strlen (str);\n\n    return socket_sendto (u->sock, (const uint8_t *) str, len, ip, port);\n}\n\n/*\n * Read a received packet into buffer buf (which is of maximum length len);\n * store calling ip and port as well. Call available() to make sure data is\n * ready first.\n * NOTE: I don't believe len is ever checked in implementation of recvfrom(),\n *       so it's easy to overflow buffer. so we check and truncate.\n * Returns number of bytes read, or negative number of bytes we would have\n * needed if we truncated.\n */\nint udp_read_packet (udp_t *u, uint8_t *buf, unsigned len,\n                     uint8_t *ip, unsigned *port)\n{\n    int nbytes = udp_available (u) - 8;     /* skip UDP header */\n    if (nbytes < 0) {\n        /* No real data here. */\n        return 0;\n    }\n\n    if (nbytes > (int)len) {\n        /* Packet is too large - truncate.\n         * HACK: hand-parse the UDP packet using TCP recv method. */\n        uint8_t tmpBuf[8];\n        int i;\n\n        /* Read 8 header bytes and get IP and port from it. */\n        socket_recv (u->sock, tmpBuf, 8);\n        if (ip != 0) {\n            ip[0] = tmpBuf[0];\n            ip[1] = tmpBuf[1];\n            ip[2] = tmpBuf[2];\n            ip[3] = tmpBuf[3];\n        }\n        if (port != 0)\n            *port = (tmpBuf[4] << 8) + tmpBuf[5];\n\n        /* Now copy first (len) bytes into buf. */\n        for (i=0; i<(int)len; i++) {\n            socket_recv (u->sock, tmpBuf, 1);\n            buf[i] = tmpBuf[0];\n        }\n\n        /* And just read the rest byte by byte and throw it away. */\n        while (udp_available (u)) {\n            socket_recv (u->sock, tmpBuf, 1);\n        }\n        return -nbytes;\n    }\n    return socket_recvfrom (u->sock, buf, len, ip, port);\n}\n"
  },
  {
    "path": "lib/libwiznet/w5100.c",
    "content": "/*\n * Copyright (c) 2010 by Cristian Maglie <c.maglie@bug.st>\n *\n * This file is free software; you can redistribute it and/or modify\n * it under the terms of either the GNU General Public License version 2\n * or the GNU Lesser General Public License version 2.1, both as\n * published by the Free Software Foundation.\n *\n * Edit History\n *  Aug  3,  2011 <Lowell Scott Hanson> ported toh chipKIT boards\n *  Sept 13, 2011 <Gene Apperson> change SPI clock divider from DIV8 to DIV32\n *  Apr  16, 2012 <Serge Vakulenko> ported to RetroBSD\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <fcntl.h>\n#include <sys/spi.h>\n#include <wiznet/w5100.h>\n\n#define SPI_DEVNAME         \"/dev/spi2\" // W5100 chip is connected to SPI2\n#define SPI_KHZ             5000        // Clock speed 5 MHz\n#define SPI_SELPIN          0x0404      // chipKIT board: select pin D4\n\n#define TXBUF_BASE          0x4000\n#define RXBUF_BASE          0x6000\n\n#define RST                 7           // Reset BIT\n\n#define TXBUF_MASK          (TXBUF_SIZE-1)      // Tx buffer MASK\n#define RXBUF_MASK          (RXBUF_SIZE-1)      // Rx buffer MASK\n\nstatic uint16_t SBASE [MAX_SOCK_NUM];   // Tx buffer base address\nstatic uint16_t RBASE [MAX_SOCK_NUM];   // Rx buffer base address\n\nstatic int spi;                         // SPI driver descriptor\n\nvoid w5100_init()\n{\n    int i, failed;\n\n    spi = open (SPI_DEVNAME, O_RDWR);\n    if (spi < 0) {\n        perror (SPI_DEVNAME);\n        exit (-1);\n    }\n\n    ioctl (spi, SPICTL_SETRATE, SPI_KHZ);\n    ioctl (spi, SPICTL_SETSELPIN, SPI_SELPIN);\n\n    /* Reset the chip. */\n    w5100_writeMR (MR_RST);\n\n    /* Assign 2 kbytes of memory to RX and TX of each socket. */\n    w5100_writeTMSR (0x55);\n    w5100_writeRMSR (0x55);\n\n    for (i=0; i<MAX_SOCK_NUM; i++) {\n        SBASE[i] = TXBUF_BASE + TXBUF_SIZE * i;\n        RBASE[i] = RXBUF_BASE + RXBUF_SIZE * i;\n    }\n\n    /* Self test. */\n    failed = 0;\n    for (i=0; i<16; i++) {\n        unsigned val, got;\n\n        val = 1 << i;\n        w5100_writeRTR (val);\n        got = w5100_readRTR();\n        if (got != val) {\n            failed++;\n            fprintf (stderr, \"w5100 self test failed: written %08x, got %08x\\n\",\n                val, got);\n        }\n    }\n    if (failed)\n        exit (-1);\n}\n\nunsigned w5100_getTXFreeSize (unsigned sock)\n{\n    unsigned val, val2;\n\n    for (;;) {\n        /* Nonzero value expected. */\n        val = w5100_readSnTX_FSR (sock);\n        if (val == 0)\n            return 0;\n\n        /* Do it twice until value matches. */\n        val2 = w5100_readSnTX_FSR (sock);\n        if (val == val2) {\n            W5100_DEBUG (\"TX free = %u\\n\", val);\n            return val;\n        }\n    }\n}\n\nunsigned w5100_getRXReceivedSize (unsigned sock)\n{\n    unsigned val, val2;\n\n    for (;;) {\n        /* Nonzero value expected. */\n        val = w5100_readSnRX_RSR (sock);\n        if (val == 0)\n            return 0;\n\n        /* Do it twice until value matches. */\n        val2 = w5100_readSnRX_RSR (sock);\n        if (val == val2) {\n            W5100_DEBUG (\"RX received = %u\\n\", val);\n            return val;\n        }\n    }\n}\n\nvoid w5100_send_chunk (unsigned sock, const uint8_t *data, unsigned len)\n{\n    unsigned ptr = w5100_readSnTX_WR (sock);\n    unsigned offset = ptr & TXBUF_MASK;\n    unsigned dstAddr = offset + SBASE[sock];\n\n    W5100_DEBUG (\"send chunk: TX write pointer = %04x\\n\", ptr);\n    if (offset + len > TXBUF_SIZE) {\n        // Wrap around circular buffer\n        unsigned size = TXBUF_SIZE - offset;\n        w5100_write (dstAddr, data, size);\n        w5100_write (SBASE[sock], data + size, len - size);\n        W5100_DEBUG (\"TX %04x-%04x, %04x-%04x\\n\", dstAddr, dstAddr+size-1, SBASE[sock], SBASE[sock]+len-size-1);\n    } else {\n        w5100_write (dstAddr, data, len);\n        W5100_DEBUG (\"TX %04x-%04x\\n\", dstAddr, dstAddr+len-1);\n    }\n\n    ptr += len;\n    w5100_writeSnTX_WR (sock, ptr);\n    W5100_DEBUG (\"set TX write pointer = %04x\\n\", ptr);\n}\n\nvoid w5100_recv_chunk (unsigned sock, uint8_t *data, unsigned len)\n{\n    unsigned ptr = w5100_readSnRX_RD (sock);\n\n    W5100_DEBUG (\"recv chunk: RX pointer = %04x\\n\", ptr);\n    w5100_read_data (sock, ptr, data, len);\n\n    ptr += len;\n    w5100_writeSnRX_RD (sock, ptr);\n    W5100_DEBUG (\"set RX pointer = %04x\\n\", ptr);\n}\n\nunsigned w5100_recv_peek (unsigned sock)\n{\n    unsigned ptr = w5100_readSnRX_RD (sock);\n    unsigned char byte;\n\n    w5100_read_data (sock, ptr, &byte, 1);\n    return byte;\n}\n\nvoid w5100_socket_cmd (unsigned sock, int cmd)\n{\n    // Send command to socket\n    w5100_writeSnCR (sock, cmd);\n\n    // Wait for command to complete\n    while (w5100_readSnCR (sock))\n        ;\n}\n\nvoid w5100_read_data (unsigned sock, unsigned ptr, uint8_t *dst, unsigned len)\n{\n    unsigned offset = ptr & RXBUF_MASK;\n    unsigned srcAddr = offset + RBASE[sock];\n\n    if (offset + len > RXBUF_SIZE)\n    {\n        unsigned size = RXBUF_SIZE - offset;\n        w5100_read (srcAddr, dst, size);\n        w5100_read (RBASE[sock], dst + size, len - size);\n        W5100_DEBUG (\"RX %04x-%04x, %04x-%04x\\n\", srcAddr, srcAddr+size-1, SBASE[sock], SBASE[sock]+len-size-1);\n    } else {\n        w5100_read (srcAddr, dst, len);\n        W5100_DEBUG (\"RX %04x-%04x\\n\", srcAddr, srcAddr+len-1);\n    }\n}\n\nunsigned w5100_write_byte (unsigned addr, int byte)\n{\n    uint8_t data[4];\n\n    data[0] = 0xF0;\n    data[1] = addr >> 8;\n    data[2] = addr;\n    data[3] = byte;\n    ioctl (spi, SPICTL_IO8(4), data);\n    return 1;\n}\n\nunsigned w5100_write (unsigned addr, const uint8_t *buf, unsigned len)\n{\n    uint8_t data[4];\n    unsigned i;\n\n    for (i=0; i<len; i++) {\n        data[0] = 0xF0;\n        data[1] = addr >> 8;\n        data[2] = addr;\n        data[3] = buf[i];\n        ioctl (spi, SPICTL_IO8(4), data);\n        addr++;\n    }\n    return len;\n}\n\nunsigned w5100_read_byte (unsigned addr)\n{\n    uint8_t data[4];\n\n    data[0] = 0x0F;\n    data[1] = addr >> 8;\n    data[2] = addr;\n    data[3] = 0xFF;\n    ioctl (spi, SPICTL_IO8(4), data);\n\n    return data[3];\n}\n\nunsigned w5100_read (unsigned addr, uint8_t *buf, unsigned len)\n{\n    uint8_t data[4];\n    unsigned i;\n\n    for (i=0; i<len; i++) {\n        data[0] = 0x0F;\n        data[1] = addr >> 8;\n        data[2] = addr;\n        data[3] = 0xFF;\n        ioctl (spi, SPICTL_IO8(4), data);\n        addr++;\n        buf[i] = data[3];\n    }\n    return len;\n}\n"
  },
  {
    "path": "lib/startup-arm/Makefile",
    "content": "#\n# Copyright (c) 1987 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n#\tcrt0\tNormal C run time startoff\n#\nTOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS\t\t+= -O ${DEFS}\n\nSRCS\t\t= crt0.c\nOBJS\t\t= crt0.o\n\nTAGSFILE\t= tags\n\nall:\t\t${OBJS}\n\t\tcp crt0.o ../\n\ninstall:\t${OBJS}\n#\t\t${INSTALL} -d ${DESTDIR}/usr/lib\n#\t\t$(INSTALL) crt0.o ${DESTDIR}/usr/lib/crt0.o\n#\t\t$(INSTALL) mcrt0.o ${DESTDIR}/usr/lib/mcrt0.o\n#\t\t$(INSTALL) gcrt0.o ${DESTDIR}/usr/lib/gcrt0.o\n\ncrt0.o:\t\tcrt0.c\n\t\t${CC} ${DEFS} ${CFLAGS} -c crt0.c -o $@\n\ntags:\n\t\tcwd=`pwd`; \\\n\t\tfor i in *.c; do \\\n\t\t\tctags -a -f ${TAGSFILE} $$cwd/$$i; \\\n\t\tdone\n\nclean:\n\t\trm -f *.o *~ core errs tags Makefile.bak\n\ndepend:\n\t\tfor i in ${SRCS}; do \\\n\t\t    cc -M ${DEFS} ${DFLAGS} $$i | awk ' { if ($$1 != prev) \\\n\t\t\t{ if (rec != \"\") print rec; rec = $$0; prev = $$1; } \\\n\t\t\telse { if (length(rec $$2) > 78) { print rec; rec = $$0; } \\\n\t\t\telse rec = rec \" \" $$2 } } \\\n\t\t\tEND { print rec } ' >> makedep; done\n\t\techo '/^# DO NOT DELETE THIS LINE/+2,$$d' >eddep\n\t\techo '$$r makedep' >>eddep\n\t\techo 'w' >>eddep\n\t\tcp Makefile Makefile.bak\n\t\ted - Makefile < eddep\n\t\trm eddep makedep\n\t\techo '# DEPENDENCIES MUST END AT END OF FILE' >> Makefile\n\t\techo '# IF YOU PUT STUFF HERE IT WILL GO AWAY' >> Makefile\n\t\techo '# see make depend above' >> Makefile\n\n# DO NOT DELETE THIS LINE -- make depend uses it\n"
  },
  {
    "path": "lib/startup-arm/crt0.c",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <stdlib.h>\n#include <unistd.h>\n\n/*\n * C runtime startoff.  When an a.out is loaded by the kernel, the kernel\n * sets up the stack as follows:\n *\n *\t--------------------------------- top of memory\n *\t| (NULL)\t\t\t| end of command-line args and env\n *\t|-------------------------------|\n *\t| \t\t\t\t|\n *\t| environment strings\t\t|\n *\t| \t\t\t\t|\n *\t|-------------------------------|\n *\t| \t\t\t\t|\n *\t| argument strings\t\t|\n *\t| \t\t\t\t|\n *\t|-------------------------------|\n *\t| envv[envc] (NULL)\t\t| end of environment vector tag, a 0\n *\t|-------------------------------|\n *\t| envv[envc-1]\t\t\t| pointer to last environment string\n *\t|-------------------------------|\n *\t| ...\t\t\t\t|\n *\t|-------------------------------|\n *\t| envv[0]\t\t\t| pointer to first environment string\n *\t|-------------------------------|\n *\t| argv[argc] (NULL)\t\t| end of argument vector tag, a 0\n *\t|-------------------------------|\n *\t| argv[argc-1]\t\t\t| pointer to last argument string\n *\t|-------------------------------|\n *\t| ...\t\t\t\t|\n *\t|-------------------------------|\n *\t| argv[0]\t\t\t| pointer to first argument string\n *\t|-------------------------------|\n *\t| &envv[0]\t\t\t| pointer to array of env pointers\n *\t|-------------------------------|\n *\t| &argv[0]\t\t\t| pointer to array of arg pointers\n *\t|-------------------------------|\n * sp->\t| argc\t\t\t\t| number of command-line arguments\n *\t---------------------------------\n *\n * Arguments are passed in registers $a1, $a2 and $a3.\n *\n * Crt0 simply moves the env to environ variable, calculates\n * the __progname and then calls main.\n */\nextern int main (int, char **, char **);\n\nchar **environ;\nconst char *__progname = \"\";\n\nvoid _start (int, char **, char **);\n\n/* The entry function. */\nvoid\n_start (argc, argv, env)\n\tint argc;\n\tchar **argv;\n\tchar **env;\n{\n\tenviron = env;\n\tif (argc > 0 && argv[0] != 0) {\n\t\tconst char *s;\n\n\t\t__progname = argv[0];\n\t\tfor (s = __progname; *s != '\\0'; s++)\n\t\t\tif (*s == '/')\n\t\t\t\t__progname = s + 1;\n\t}\n\texit (main (argc, argv, environ));\n}\n"
  },
  {
    "path": "lib/startup-arm/mon.c",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)mon.c\t5.5 (GTE) 3/23/92\";\n#endif LIBC_SCCS and not lint\n\n#define ARCDENSITY\t1\t/* density of routines per 100 bytes */\n#define MINARCS\t\t50\t/* minimum number of counters */\n#define\tHISTFRACTION\t8\t/* fraction of text space for histograms */\n\n\nstruct phdr {\t\t/* mon.out header */\n\tint\t*lpc;\t\t/* low pc of histogramed text space */\n\tint\t*hpc;\t\t/* high pc */\n\tint\tncnt;\t\t/* number of functions counted */\n};\n\nstruct cnt {\t\t/* function entry count structure */\n\tint\t(*pc)();\t/* address of profiled function */\n\tlong\tncall;\t\t/* number of time function called */\n};\n\nstatic struct cnt *countbase;\t/* next free cnt struct */\nstatic struct cnt *countend;\t/* first address past cnt structs */\n\nstatic short\t*s_sbuf;\t/* start of histogram buffer */\nstatic unsigned\ts_bufsize;\t/* size of histogram buffer (in chars) */\nstatic char\t*s_lowpc;\t/* low pc for histgram recording */\nstatic unsigned\ts_scale;\t/* histogram scale */\n\n#define\tPERROR(s)\twrite(2, s, sizeof(s)-1)\n\nmonstartup(lowpc, highpc)\n\tchar *lowpc;\n\tchar *highpc;\n{\n\tunsigned int cntsize, monsize;\n\tchar *buffer;\n\textern char *sbrk();\n\textern char *minbrk;\n\n\tcntsize = (unsigned)(highpc - lowpc) * ARCDENSITY / 100;\n\tif (cntsize < MINARCS)\n\t\tcntsize = MINARCS;\n\tmonsize = (unsigned)(highpc - lowpc + HISTFRACTION - 1) / HISTFRACTION\n\t\t+ sizeof(struct phdr) + cntsize * sizeof(struct cnt);\n\tmonsize = (monsize + 1) & ~1;\n\tbuffer = sbrk(monsize);\n\tif (buffer == (char *)-1) {\n\t\tPERROR(\"monstartup: no space for monitor buffer(s)\\n\");\n\t\treturn;\n\t}\n\tminbrk = sbrk(0);\n\tmonitor(lowpc, highpc, buffer, monsize>>1, cntsize);\n}\n\nmonitor(lowpc, highpc, buf, bufsize, cntsize)\n\tchar *lowpc, *highpc;\n\tchar *buf;\t\t/* really (short *) but easier this way */\n\tunsigned bufsize, cntsize;\n{\n\tregister unsigned o;\n\tregister struct phdr *php;\n\tstatic char *sbuf;\t/* saved base of profiling buffer */\n\tstatic unsigned ssize;\t/* saved buffer size */\n\n\tif (lowpc == 0) {\n\t\tmoncontrol(0);\n\t\to = creat(\"mon.out\", 0666);\n\t\twrite(o, sbuf, ssize);\n\t\tclose(o);\n\t\treturn;\n\t}\n\tbufsize *= sizeof(short);\n\tif (bufsize < sizeof(struct phdr)+sizeof(struct cnt)+sizeof(short)) {\n\t\tPERROR(\"monitor: buffer too small\");\n\t\treturn;\n\t}\n\tsbuf = buf;\n\tssize = bufsize;\n\n\tcountbase = (struct cnt *)(buf + sizeof(struct phdr));\n\to = sizeof(struct phdr) + cntsize * sizeof(struct cnt);\n\tif (o > bufsize) {\n\t\tcntsize = (bufsize - sizeof(struct phdr))/sizeof(struct cnt);\n\t\to = sizeof(struct phdr) + cntsize * sizeof(struct cnt);\n\t}\n\tcountend = (struct cnt *)(buf + o);\n\n\tphp = (struct phdr *)buf;\n\tphp->lpc = (int *)lowpc;\n\tphp->hpc = (int *)highpc;\n\tphp->ncnt = cntsize;\n\n\ts_sbuf = (short *)countend;\n\ts_bufsize = bufsize - o;\n\ts_lowpc = lowpc;\n\to = highpc - lowpc;\n\tif(s_bufsize < o)\n\t\to = ((long)s_bufsize << 16) / o;\n\telse\n\t\to = 0xffff;\n\ts_scale = o;\n\tmoncontrol(1);\n}\n\n/*\n * Control profiling\n */\nmoncontrol(mode)\n\tint mode;\n{\n\tif (mode) {\n\t\t/* start */\n\t\tprofil(s_sbuf, s_bufsize, s_lowpc, s_scale);\n\t} else {\n\t\t/* stop */\n\t\tprofil((char *)0, 0, 0, 0);\n\t}\n}\n"
  },
  {
    "path": "lib/startup-arm/mon.ex",
    "content": "\"\t@(#)mon.ex\t4.4 (Berkeley) 7/26/83\"\n\"\tfix funny name for minbrk used by monstartup() to limit brk()\"\ng/_minbrk/s//minbrk/g\nw\nq\n"
  },
  {
    "path": "lib/startup-mips/Makefile",
    "content": "#\n# Copyright (c) 1987 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n#\tcrt0\tNormal C run time startoff\n#\nTOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\n# Do not include -mips16 as it chokes on `la $gp,_gp'.\nCFLAGS          = -O ${DEFS}\n\nSRCS\t\t= crt0.c\nOBJS\t\t= crt0.o\n\nTAGSFILE\t= tags\n\nall:\t\t${OBJS}\n\t\tcp crt0.o ../\n\ninstall:\t${OBJS}\n#\t\t${INSTALL} -d ${DESTDIR}/usr/lib\n#\t\t$(INSTALL) crt0.o ${DESTDIR}/usr/lib/crt0.o\n#\t\t$(INSTALL) mcrt0.o ${DESTDIR}/usr/lib/mcrt0.o\n#\t\t$(INSTALL) gcrt0.o ${DESTDIR}/usr/lib/gcrt0.o\n\ncrt0.o:\t\tcrt0.c\n\t\t${CC} ${DEFS} ${CFLAGS} -c crt0.c -o $@\n\ntags:\n\t\tcwd=`pwd`; \\\n\t\tfor i in *.c; do \\\n\t\t\tctags -a -f ${TAGSFILE} $$cwd/$$i; \\\n\t\tdone\n\nclean:\n\t\trm -f *.o *~ core errs tags Makefile.bak\n\ndepend:\n\t\tfor i in ${SRCS}; do \\\n\t\t    cc -M ${DEFS} ${DFLAGS} $$i | awk ' { if ($$1 != prev) \\\n\t\t\t{ if (rec != \"\") print rec; rec = $$0; prev = $$1; } \\\n\t\t\telse { if (length(rec $$2) > 78) { print rec; rec = $$0; } \\\n\t\t\telse rec = rec \" \" $$2 } } \\\n\t\t\tEND { print rec } ' >> makedep; done\n\t\techo '/^# DO NOT DELETE THIS LINE/+2,$$d' >eddep\n\t\techo '$$r makedep' >>eddep\n\t\techo 'w' >>eddep\n\t\tcp Makefile Makefile.bak\n\t\ted - Makefile < eddep\n\t\trm eddep makedep\n\t\techo '# DEPENDENCIES MUST END AT END OF FILE' >> Makefile\n\t\techo '# IF YOU PUT STUFF HERE IT WILL GO AWAY' >> Makefile\n\t\techo '# see make depend above' >> Makefile\n\n# DO NOT DELETE THIS LINE -- make depend uses it\n"
  },
  {
    "path": "lib/startup-mips/crt0.c",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <stdlib.h>\n#include <unistd.h>\n\n/*\n * C runtime startoff.  When an a.out is loaded by the kernel, the kernel\n * sets up the stack as follows:\n *\n *\t_________________________________\n *\t| (NULL)\t\t\t| top of memory\n *\t|-------------------------------|\n *\t| \t\t\t\t|\n *\t| environment strings\t\t|\n *\t| \t\t\t\t|\n *\t|-------------------------------|\n *\t| \t\t\t\t|\n *\t| argument strings\t\t|\n *\t| \t\t\t\t|\n *\t|-------------------------------|\n *\t| envv[envc] (NULL)\t\t| end of environment vector tag, a 0\n *\t|-------------------------------|\n *\t| envv[envc-1]\t\t\t| pointer to last environment string\n *\t|-------------------------------|\n *\t| ...\t\t\t\t|\n *\t|-------------------------------|\n *\t| envv[0]\t\t\t| pointer to first environment string\n *\t|-------------------------------|\n *\t| argv[argc] (NULL)\t\t| end of argument vector tag, a 0\n *\t|-------------------------------|\n *\t| argv[argc-1]\t\t\t| pointer to last argument string\n *\t|-------------------------------|\n *\t| ...\t\t\t\t|\n *\t|-------------------------------|\n *\t| argv[0]\t\t\t| pointer to first argument string\n *\t|-------------------------------|\n *\t|\t\t\t\t| space for fourth argument\n *\t|-------------------------------|\n *\t|\t\t\t\t| space for third argument\n *\t|-------------------------------|\n *\t|\t\t\t\t| space for second argument\n *\t|-------------------------------|\n * sp->\t| \t\t\t\t| space for first\n *\t---------------------------------\n *\n * Arguments are passed in registers $a0, $a1 and $a2.\n * Register $gp is set to the start of data section.\n *\n * Crt0 simply moves the env to environ variable, calculates\n * the __progname and then calls main.\n */\nextern int main (int, char **, char **);\n\nchar **environ;\nconst char *__progname = \"\";\n\nvoid _start (int, char **, char **);\n\n/* The entry function. */\nvoid\n_start (argc, argv, env)\n\tint argc;\n\tchar **argv;\n\tchar **env;\n{\n        asm volatile (\"la $gp, _gp\");\n\n\tenviron = env;\n\tif (argc > 0 && argv[0] != 0) {\n\t\tconst char *s;\n\n\t\t__progname = argv[0];\n\t\tfor (s = __progname; *s != '\\0'; s++)\n\t\t\tif (*s == '/')\n\t\t\t\t__progname = s + 1;\n\t}\n\texit (main (argc, argv, env));\n}\n"
  },
  {
    "path": "lib/startup-mips/mcount.S",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#ifdef LIBC_SCCS\n\t<@(#)mcount.s\t1.1 (Berkeley) 5/2/87\\0>\n\t.even\n#endif LIBC_SCCS\n\n/*\n * Count subroutine calls during simple (non-gprof) profiling.  This file is\n * appended to the compiled assembly output of mon.c.\n *\n * struct cnt {\n *\tint\t(*pc)();\t\t/ address of function\n *\tlong\tncall;\t\t\t/ number of times _foo entered\n * }\n *\n * mcount(cntp::r0)\n *\tlong\t**cntp;\n *\n * Mcount is called with a pointer to a function's local call count pointer in\n * r0.  On first entry, mcount allocates a (struct cnt) and initializes it with\n * the function's base segment address and points the functions local call\n * counter pointer just past the structure's ncall field.  (we do this so we\n * can do long increments slightly faster)\n *\n * The C compiler generates the following preamble for every function\n * compiled with profiling:\n *\n *\t.data\n *\t1:\t_foo+1\n *\t.text\n *\n *\t_foo:\t\t\t\t/ unique name of foo (always in base)\n *\t~foo:\t\t\t\t/ real address of foo\n *\t+0\tjsr\tr5,csv\t\t/ perform standard C entry\n *\t+4\tmov\t$1b,r0\t\t/ point to local call counter pointer\n *\t+8\tjsr\tpc,mcount\t/ and have mcount do its thing\n *\t+12\t...\t\t\t/ first `real' word of ~foo\n *\n * Function and ncall field addresses are always even so the \"_foo+1\" doesn't\n * destroy information and can be used to determine a first call to mcount.\n *\n * Note that because we now use functions' base segment address rather than\n * our own return address (as was done in the past) and because the call to\n * mcount is after that to csv, profiling now works for overlaid objects.\n * Only static routines in overlays which are assigned the same address by\n * the loader may be counted incorrectly.\n */\n#include \"../sys/SYS.h\"\n#undef\tPROF\n\n\t.text\nASENTRY(mcount)\n\ttst\t_countbase\t\t/ buffer set up yet?\n\tbeq\t2f\t\t\t/ nope, just exit\n\tmov\t(r0),r1\t\t\t/ cnt struct allocated yet?\n\tbit\t$1,r1\n\tbne\t3f\t\t\t/ nope, grab one\n1:\t\n\tadd\t$1,-(r1)\t\t/ increment *(*cnt-1)\n\tadc\t-(r1)\n2:\n\trts\tpc\t\t\t/ and return\n3:\n\tmov\t_countbase,r1\n\tcmp\tr1,_countend\t\t/ no, out of cnt structs?\n\tbhis\t3f\t\t\t/   yes, output error message\n\tmov\t(r0),(r1)\t\t/ save _foo\n\tbic\t$1,(r1)+\n\tcmp\t(r1)+,(r1)+\t\t/ move on to next cnt struct and\n\tmov\tr1,_countbase\t\t/   save in _countbase\n\tmov\tr1,(r0)\t\t\t/ save pointer to &ncall+1 in *cntp\n\tbr\t1b\t\t\t/ increment ncall (to 1)\n3:\n\tmov\t$9f-8f,-(sp)\t\t/ ran out cnt structs, output an\n\tmov\t$8f,-(sp)\t\t/   error message\n\tmov\t$2,-(sp)\n\ttst\t-(sp)\t\t\t/ simulate return address stack\n\tSYS(write)\t\t\t/   spacing and perform write (we\n\tadd\t$8.,sp\t\t\t/   have to do the syscall because\n\trts\tpc\t\t\t/   _write calls mcount)\n\n.data\n8:\t<mcount: counter overflow\\n>\n9:\n.text\n"
  },
  {
    "path": "lib/startup-mips/mon.c",
    "content": "/*\n * Copyright (c) 1987 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#if defined(LIBC_SCCS) && !defined(lint)\nstatic char sccsid[] = \"@(#)mon.c\t5.5 (GTE) 3/23/92\";\n#endif LIBC_SCCS and not lint\n\n#define ARCDENSITY\t1\t/* density of routines per 100 bytes */\n#define MINARCS\t\t50\t/* minimum number of counters */\n#define\tHISTFRACTION\t8\t/* fraction of text space for histograms */\n\n\nstruct phdr {\t\t/* mon.out header */\n\tint\t*lpc;\t\t/* low pc of histogramed text space */\n\tint\t*hpc;\t\t/* high pc */\n\tint\tncnt;\t\t/* number of functions counted */\n};\n\nstruct cnt {\t\t/* function entry count structure */\n\tint\t(*pc)();\t/* address of profiled function */\n\tlong\tncall;\t\t/* number of time function called */\n};\n\nstatic struct cnt *countbase;\t/* next free cnt struct */\nstatic struct cnt *countend;\t/* first address past cnt structs */\n\nstatic short\t*s_sbuf;\t/* start of histogram buffer */\nstatic unsigned\ts_bufsize;\t/* size of histogram buffer (in chars) */\nstatic char\t*s_lowpc;\t/* low pc for histgram recording */\nstatic unsigned\ts_scale;\t/* histogram scale */\n\n#define\tPERROR(s)\twrite(2, s, sizeof(s)-1)\n\nmonstartup(lowpc, highpc)\n\tchar *lowpc;\n\tchar *highpc;\n{\n\tunsigned int cntsize, monsize;\n\tchar *buffer;\n\textern char *sbrk();\n\textern char *minbrk;\n\n\tcntsize = (unsigned)(highpc - lowpc) * ARCDENSITY / 100;\n\tif (cntsize < MINARCS)\n\t\tcntsize = MINARCS;\n\tmonsize = (unsigned)(highpc - lowpc + HISTFRACTION - 1) / HISTFRACTION\n\t\t+ sizeof(struct phdr) + cntsize * sizeof(struct cnt);\n\tmonsize = (monsize + 1) & ~1;\n\tbuffer = sbrk(monsize);\n\tif (buffer == (char *)-1) {\n\t\tPERROR(\"monstartup: no space for monitor buffer(s)\\n\");\n\t\treturn;\n\t}\n\tminbrk = sbrk(0);\n\tmonitor(lowpc, highpc, buffer, monsize>>1, cntsize);\n}\n\nmonitor(lowpc, highpc, buf, bufsize, cntsize)\n\tchar *lowpc, *highpc;\n\tchar *buf;\t\t/* really (short *) but easier this way */\n\tunsigned bufsize, cntsize;\n{\n\tregister unsigned o;\n\tregister struct phdr *php;\n\tstatic char *sbuf;\t/* saved base of profiling buffer */\n\tstatic unsigned ssize;\t/* saved buffer size */\n\n\tif (lowpc == 0) {\n\t\tmoncontrol(0);\n\t\to = creat(\"mon.out\", 0666);\n\t\twrite(o, sbuf, ssize);\n\t\tclose(o);\n\t\treturn;\n\t}\n\tbufsize *= sizeof(short);\n\tif (bufsize < sizeof(struct phdr)+sizeof(struct cnt)+sizeof(short)) {\n\t\tPERROR(\"monitor: buffer too small\");\n\t\treturn;\n\t}\n\tsbuf = buf;\n\tssize = bufsize;\n\n\tcountbase = (struct cnt *)(buf + sizeof(struct phdr));\n\to = sizeof(struct phdr) + cntsize * sizeof(struct cnt);\n\tif (o > bufsize) {\n\t\tcntsize = (bufsize - sizeof(struct phdr))/sizeof(struct cnt);\n\t\to = sizeof(struct phdr) + cntsize * sizeof(struct cnt);\n\t}\n\tcountend = (struct cnt *)(buf + o);\n\n\tphp = (struct phdr *)buf;\n\tphp->lpc = (int *)lowpc;\n\tphp->hpc = (int *)highpc;\n\tphp->ncnt = cntsize;\n\n\ts_sbuf = (short *)countend;\n\ts_bufsize = bufsize - o;\n\ts_lowpc = lowpc;\n\to = highpc - lowpc;\n\tif(s_bufsize < o)\n\t\to = ((long)s_bufsize << 16) / o;\n\telse\n\t\to = 0xffff;\n\ts_scale = o;\n\tmoncontrol(1);\n}\n\n/*\n * Control profiling\n */\nmoncontrol(mode)\n\tint mode;\n{\n\tif (mode) {\n\t\t/* start */\n\t\tprofil(s_sbuf, s_bufsize, s_lowpc, s_scale);\n\t} else {\n\t\t/* stop */\n\t\tprofil((char *)0, 0, 0, 0);\n\t}\n}\n"
  },
  {
    "path": "lib/startup-mips/mon.ex",
    "content": "\"\t@(#)mon.ex\t4.4 (Berkeley) 7/26/83\"\n\"\tfix funny name for minbrk used by monstartup() to limit brk()\"\ng/_minbrk/s//minbrk/g\nw\nq\n"
  },
  {
    "path": "libexec/Makefile",
    "content": "#\n# Public domain - 1996/10/26 - sms\n#\n#\t@(#)Makefile\t1.3 (2.11BSD) 1999/7/21\n#\nTOPSRC!=cd ..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nSUBDIR=\tgetty\n\nall:\t${SUBDIR}\n\n${SUBDIR}: FRC\n\tcd $@; ${MAKE} ${MFLAGS} all\n\nFRC:\n\ninstall: FRC\n\t-for i in ${SUBDIR}; do \\\n\t\t(cd $$i; ${MAKE} ${MFLAGS} DESTDIR=${DESTDIR} install); done\n\nclean:\n\t-for i in ${SUBDIR}; do (cd $$i; ${MAKE} ${MFLAGS} clean); done\n\trm -f *~\n"
  },
  {
    "path": "sbin/Makefile",
    "content": "#\n# Public domain - 1996/10/26 - sms\n#\n#\t@(#)Makefile\t1.3 (2.11BSD) 1999/7/21\n#\nTOPSRC!=cd ..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nSUBDIR=\tchown fdisk fsck init mkfs mknod mount \\\n\treboot shutdown sysctl umount\n\nall:\t${SUBDIR}\n\n${SUBDIR}: FRC\n\tcd $@; ${MAKE} ${MFLAGS} all\n\nFRC:\n\ninstall: FRC\n\t-for i in ${SUBDIR}; do \\\n\t\t(cd $$i; ${MAKE} ${MFLAGS} DESTDIR=${DESTDIR} install); done\n\nclean:\n\tfor i in ${SUBDIR}; do (cd $$i; ${MAKE} ${MFLAGS} clean); done\n\trm -f *~\n"
  },
  {
    "path": "share/Makefile",
    "content": "#\n# Public domain - 1996/10/21 - sms\n#\n#\t@(#)Makefile\t1.1 (2.11BSD) 1996/11/29\n#\nTOPSRC!=cd ..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nSUBDIR\t\t= dict examples man misc zoneinfo\n\nall:\t\t${SUBDIR}\n\n${SUBDIR}: \tFRC\n\t\tcd $@; ${MAKE} ${MFLAGS}\n\nFRC:\n\ninstall: \tFRC\n\t\t-for i in ${SUBDIR}; do \\\n\t\t\t(cd $$i; ${MAKE} ${MFLAGS} DESTDIR=${DESTDIR} install); done\n\nclean:\n\t\trm -f *~\n\t\tfor i in ${SUBDIR}; do (cd $$i; ${MAKE} ${MFLAGS} clean); done\n"
  },
  {
    "path": "share/dict/Makefile",
    "content": "#\t@(#)Makefile\t8.1 (Berkeley) 6/5/93\nTOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nFILES=\twords\n\nall clean cleandir depend lint tags:\n\ninstall:\n\t${INSTALL} -d ${DESTDIR}/usr/share/dict\n\t${INSTALL} -c -m 444 ${FILES} ${DESTDIR}/usr/share/dict\n"
  },
  {
    "path": "share/dict/words",
    "content": "a\nAAA\nAAAS\naardvark\nAarhus\nAaron\nABA\nAbaba\naback\nabacus\nabalone\nabandon\nabase\nabash\nabate\nabbas\nabbe\nabbey\nabbot\nAbbott\nabbreviate\nabc\nabdicate\nabdomen\nabdominal\nabduct\nAbe\nabed\nAbel\nAbelian\nAbelson\nAberdeen\nAbernathy\naberrant\naberrate\nabet\nabetted\nabetting\nabeyance\nabeyant\nabhor\nabhorred\nabhorrent\nabide\nAbidjan\nAbigail\nabject\nabjure\nablate\nablaze\nable\nablution\nabnegation\nAbner\nabnormal\nAbo\naboard\nabode\nabolish\nabolition\nabominable\nabominate\naboriginal\naborigine\naborning\nabort\nabound\nabout\nabove\naboveboard\naboveground\nabovementioned\nabrade\nAbraham\nAbram\nAbramson\nabrasion\nabrasive\nabreact\nabreast\nabridge\nabridgment\nabroad\nabrogate\nabrupt\nabscess\nabscissa\nabscissae\nabscond\nabsent\nabsentee\nabsenteeism\nabsentia\nabsentminded\nabsinthe\nabsolute\nabsolution\nabsolve\nabsorb\nabsorbent\nabsorption\nabsorptive\nabstain\nabstention\nabstinent\nabstract\nabstractor\nabstruse\nabsurd\nabsurdum\nabuilding\nabundant\nabusable\nabuse\nabusive\nabut\nabutted\nabutting\nabysmal\nabyss\nAbyssinia\nAC\nacacia\nacademia\nacademic\nacademician\nacademy\nAcadia\nacanthus\nAcapulco\naccede\naccelerate\naccelerometer\naccent\naccentual\naccentuate\naccept\nacceptant\nacceptor\naccess\naccessible\naccession\naccessory\naccident\naccidental\naccipiter\nacclaim\nacclamation\nacclimate\naccolade\naccommodate\naccompaniment\naccompanist\naccompany\naccomplice\naccomplish\naccord\naccordant\naccordion\naccost\naccount\naccountant\naccouter\nAccra\naccredit\naccreditation\naccretion\naccrual\naccrue\nacculturate\naccumulate\naccuracy\naccurate\naccusation\naccusative\naccusatory\naccuse\naccustom\nace\nacerbic\nacerbity\nacetaminophen\nacetate\nacetic\nacetone\nacetylene\nAchaean\nache\nachieve\nAchilles\naching\nachromatic\nacid\nacidic\nacidify\nacidulate\nacidulous\nAckerman\nAckley\nacknowledge\nacknowledgeable\nACM\nacme\nacolyte\nacorn\nacoustic\nacquaint\nacquaintance\nacquiesce\nacquiescent\nacquire\nacquisition\nacquisitive\nacquit\nacquittal\nacquitting\nacre\nacreage\nacrid\nacrimonious\nacrimony\nacrobacy\nacrobat\nacrobatic\nacronym\nacrophobia\nacrophobic\nacropolis\nacross\nacrylate\nacrylic\nact\nActaeon\nactinic\nactinide\nactinium\nactinolite\nactinometer\nactivate\nActon\nactor\nactress\nactual\nactuarial\nactuate\nacuity\nacumen\nacupuncture\nacute\nacyclic\nad\nAda\nadage\nadagio\nAdair\nAdam\nadamant\nAdamson\nadapt\nadaptation\nadaptive\nadd\naddend\naddenda\naddendum\naddict\nAddis\nAddison\naddition\nadditive\naddle\naddress\naddressee\nAddressograph\nadduce\nAdelaide\nAdele\nAdelia\nAden\nadenine\nadenoma\nadenosine\nadept\nadequacy\nadequate\nadhere\nadherent\nadhesion\nadhesive\nadiabatic\nadieu\nadipic\nAdirondack\nadjacent\nadject\nadjectival\nadjoin\nadjoint\nadjourn\nadjudge\nadjudicate\nadjunct\nadjust\nadjutant\nAdkins\nAdler\nAdlerian\nadminister\nadministrable\nadministrate\nadministratrix\nadmiral\nadmiralty\nadmiration\nadmire\nadmissible\nadmission\nadmit\nadmittance\nadmitted\nadmitting\nadmix\nadmixture\nadmonish\nadmonition\nado\nadobe\nadolescent\nAdolph\nAdolphus\nAdonis\nadopt\nadoption\nadoptive\nadoration\nadore\nadorn\nadposition\nadrenal\nadrenalin\nadrenaline\nAdrian\nAdriatic\nAdrienne\nadrift\nadroit\nadsorb\nadsorbate\nadsorption\nadsorptive\nadulate\nadult\nadulterate\nadulterous\nadultery\nadvance\nadvantage\nadvantageous\nadvent\nadventitious\nadventure\nadventurous\nadverb\nadverbial\nadversary\nadverse\nadvert\nadvertise\nadvice\nadvisable\nadvise\nadvisee\nadvisor\nadvisory\nadvocacy\nadvocate\nAegean\naegis\nAeneas\nAeneid\naeolian\nAeolus\naerate\naerial\naerie\nAerobacter\naerobic\naerodynamic\naerofoil\naerogene\naeronautic\naerosol\naerospace\nAeschylus\nAesop\naesthete\naesthetic\nafar\naffable\naffair\naffect\naffectate\naffectionate\nafferent\naffiance\naffidavit\naffiliate\naffine\naffirm\naffirmation\naffirmative\naffix\nafflict\naffluent\nafford\nafforest\nafforestation\naffricate\naffront\nAfghan\nAfghanistan\naficionado\nafield\nafire\naflame\nafloat\nafoot\naforementioned\naforesaid\naforethought\nafraid\nafreet\nafresh\nAfrica\nAfrikaans\nAfrikaner\nafro\naft\nafterbirth\naftereffect\nafterglow\nafterimage\nafterlife\naftermath\nafternoon\nafterthought\nafterward\nafterword\nagain\nagainst\nAgamemnon\nagar\nagate\nAgatha\nagave\nage\nAgee\nagenda\nagent\nagglomerate\nagglutinate\nagglutinin\naggravate\naggregate\naggression\naggressive\naggressor\naggrieve\naghast\nagile\nagitate\nagleam\nAgnes\nAgnew\nagnomen\nagnostic\nago\nagog\nagone\nagony\nagouti\nagrarian\nagree\nagreeable\nagreeing\nagribusiness\nAgricola\nagricultural\nagriculture\nagrimony\nagronomist\nagronomy\nague\nAgway\nah\nahead\nahem\nAhmedabad\nahoy\naid\nAida\naide\nAides\nAiken\nail\nailanthus\naile\naileron\naim\nain't\nAinu\nair\nairborne\nairbrush\naircraft\nairdrop\nairedale\nAires\nairfare\nairfield\nairflow\nairframe\nairlift\nairline\nairlock\nairmail\nairman\nairmass\nairmen\nairpark\nairplane\nairport\nairspeed\nairstrip\nairtight\nairway\nairy\naisle\nAitken\najar\nAjax\nAK\nAkers\nakin\nAkron\nAL\nala\nAlabama\nAlabamian\nalabaster\nalacrity\nAladdin\nalai\nAlameda\nAlamo\nalan\nalarm\nAlasdair\nAlaska\nAlastair\nalb\nalba\nalbacore\nAlbania\nAlbany\nalbatross\nalbeit\nAlberich\nAlbert\nAlberta\nAlberto\nalbino\nAlbrecht\nAlbright\nalbum\nalbumin\nAlbuquerque\nAlcestis\nalchemist\nalchemy\nAlcmena\nAlcoa\nalcohol\nalcoholic\nAlcott\nalcove\nAldebaran\naldehyde\nAlden\nalder\nalderman\naldermen\nAldrich\naldrin\nale\nAlec\nAleck\naleph\nalert\nAleutian\nalewife\nAlex\nAlexander\nAlexandra\nAlexandre\nAlexandria\nAlexei\nAlexis\nalfalfa\nalfonso\nAlfred\nAlfredo\nalfresco\nalga\nalgae\nalgaecide\nalgal\nalgebra\nalgebraic\nAlgenib\nAlger\nAlgeria\nAlgiers\nalginate\nAlgol\nAlgonquian\nAlgonquin\nalgorithm\nalgorithmic\nAlhambra\nAli\nalia\nalias\nalibi\nAlice\nAlicia\nalien\nalienate\nalight\nalign\nalike\nalimentary\nalimony\naliphatic\naliquot\nAlison\nAlistair\nalive\nalizarin\nalkali\nalkaline\nalkaloid\nall\nAllah\nAllan\nallay\nallegate\nallege\nAllegheny\nallegiant\nallegoric\nallegory\nAllegra\nallegro\nallele\nallemand\nAllen\nAllentown\nallergic\nallergy\nalleviate\nalley\nalleyway\nalliance\nalligator\nAllis\nAllison\nalliterate\nallmsgs\nallocable\nallocate\nallot\nallotropic\nallotted\nallotting\nallow\nallowance\nalloy\nallspice\nAllstate\nallude\nallure\nallusion\nallusive\nalluvial\nalluvium\nally\nallyl\nAllyn\nalma\nAlmaden\nalmagest\nalmanac\nalmighty\nalmond\nalmost\naloe\naloft\naloha\nalone\nalong\nalongside\naloof\naloud\nalp\nalpaca\nalpenstock\nAlpert\nalpha\nalphabet\nalphabetic\nalphanumeric\nAlpheratz\nAlphonse\nalpine\nalready\nAlsatian\nalso\nAlsop\nAltair\naltar\nalter\nalterate\naltercate\naltern\nalternate\nalthea\nalthough\naltimeter\naltitude\nalto\naltogether\nAlton\naltruism\naltruist\nalum\nalumina\naluminate\nalumna\nalumnae\nalumni\nalumnus\nalundum\nAlva\nAlvarez\nalveolar\nalveoli\nalveolus\nAlvin\nalways\nalyssum\nA&M\nam\nAMA\nAmadeus\namalgam\namalgamate\namanita\namanuensis\namaranth\nAmarillo\namass\namateur\namateurish\namatory\namaze\nAmazon\nambassador\namber\nambiance\nambidextrous\nambient\nambiguity\nambiguous\nambition\nambitious\nambivalent\namble\nambrose\nambrosia\nambrosial\nambulant\nambulatory\nambuscade\nambush\nAmelia\nameliorate\namen\namend\namende\nAmerada\nAmerica\nAmericana\namericium\nAmes\namethyst\namethystine\nAmharic\nAmherst\nami\namicable\namid\namide\namidst\namigo\namino\naminobenzoic\namiss\namity\nAmman\nAmmerman\nammeter\nammo\nammonia\nammoniac\nammonite\nammonium\nammunition\namnesia\namnesiac\namnesty\namniocentesis\namniotic\nAmoco\namoeba\namoebae\namoeboid\namok\namong\namongst\namoral\namorphous\namort\nAmos\namount\namp\namperage\nampere\nampersand\nAmpex\namphetamine\namphibian\namphibious\namphibole\namphibology\namphioxis\nample\namplify\namplitude\namply\namputate\namra\nAmsterdam\nAmtrak\namulet\namuse\namy\namygdaloid\nan\nana\nAnabaptist\nAnabel\nanachronism\nanachronistic\nanaconda\nAnacreon\nanaerobic\nanaglyph\nanagram\nAnaheim\nAnalects\nanaleptic\nanalgesic\nanalogous\nanalogue\nanalogy\nanalyses\nanalysis\nanalyst\nanalytic\nanamorphic\nanaphora\nanaphoric\nanaplasmosis\nanarch\nanarchic\nanarchy\nAnastasia\nanastigmat\nanastigmatic\nanastomosis\nanastomotic\nanathema\nAnatole\nanatomic\nanatomist\nanatomy\nancestor\nancestral\nancestry\nanchor\nanchorage\nanchorite\nanchovy\nancient\nancillary\nand\nAndalusia\nAndean\nAndersen\nAnderson\nAndes\nandesine\nandesite\nAndorra\nAndover\nAndre\nAndrea\nAndrei\nAndrew\nandrogen\nAndromache\nAndromeda\nAndy\nanecdotal\nanecdote\nanemone\nanent\nanew\nangel\nAngela\nAngeles\nangelfish\nangelic\nAngelica\nAngelina\nAngeline\nAngelo\nanger\nAngie\nangiosperm\nangle\nAngles\nAnglican\nAnglo\nAnglophobia\nAngola\nAngora\nangry\nangst\nangstrom\nanguish\nangular\nAngus\nanharmonic\nAnheuser\nanhydride\nanhydrite\nanhydrous\nani\naniline\nanimadversion\nanimadvert\nanimal\nanimate\nanimism\nanimist\nanimosity\nanion\nanionic\nanise\naniseikonic\nanisotropic\nanisotropy\nAnita\nAnkara\nankle\nAnn\nAnna\nannal\nAnnale\nAnnalen\nAnnapolis\nAnne\nanneal\nannelid\nAnnette\nannex\nAnnie\nannihilate\nanniversary\nannotate\nannounce\nannoy\nannoyance\nannual\nannuity\nannul\nannular\nannuli\nannulled\nannulling\nannulus\nannum\nannunciate\nanode\nanodic\nanoint\nanomalous\nanomaly\nanomie\nanonymity\nanonymous\nanorexia\nanorthic\nanorthite\nanorthosite\nanother\nAnselm\nAnselmo\nANSI\nanswer\nant\nantacid\nAntaeus\nantagonism\nantagonist\nantarctic\nAntarctica\nAntares\nante\nanteater\nantebellum\nantecedent\nantedate\nantelope\nantenna\nantennae\nanterior\nanthem\nanther\nanthology\nAnthony\nanthracite\nanthracnose\nanthropocentric\nanthropogenic\nanthropoid\nanthropology\nanthropomorphic\nanthropomorphism\nanti\nantic\nanticipate\nanticipatory\nanticonvulsant\nAntietam\nantigen\nAntigone\nantigorite\nAntilles\nantimony\nAntioch\nantipasto\nantipathy\nantiperspirant\nantiphonal\nantipodal\nantipode\nantiquarian\nantiquary\nantiquated\nantique\nantiquity\nantisemite\nantisemitic\nantithetic\nantivenin\nantler\nAntoine\nAntoinette\nAnton\nAntonio\nAntony\nantonym\nAntwerp\nanus\nanvil\nanxiety\nanxious\nany\nanybody\nanybody'd\nanyhow\nanyone\nanyplace\nanything\nanyway\nanywhere\naorta\nA&P\napache\napart\napartheid\napathetic\napathy\napatite\nape\naperiodic\naperture\napex\naphasia\naphasic\naphelion\naphid\naphorism\naphrodisiac\nAphrodite\napiary\napical\napices\napiece\naplomb\napocalypse\napocalyptic\nApocrypha\napocryphal\napogee\nApollo\nApollonian\napologetic\napologia\napology\napoplectic\napoplexy\napostasy\napostate\napostle\napostolic\napostrophe\napothecary\napothegm\napotheosis\nAppalachia\nappall\nappanage\napparatus\napparel\napparent\napparition\nappeal\nappear\nappearance\nappeasable\nappease\nappellant\nappellate\nappend\nappendage\nappendices\nappendix\nappertain\nappetite\nAppian\napplaud\napplause\napple\nAppleby\napplejack\nAppleton\nappliance\napplicable\napplicant\napplicate\napplique\napply\nappoint\nappointe\nappointee\napport\napposite\napposition\nappraisal\nappraise\nappreciable\nappreciate\napprehend\napprehension\napprehensive\napprentice\napprise\napproach\napprobation\nappropriable\nappropriate\napproval\napprove\napproximable\napproximant\napproximate\napricot\nApril\napron\napropos\napse\napt\naptitude\naqua\naquarium\nAquarius\naquatic\naqueduct\naqueous\naquifer\nAquila\nAquinas\nAR\nArab\narabesque\nArabia\nArabic\nAraby\nArachne\narachnid\nArapaho\narbiter\narbitrage\narbitrary\narbitrate\narboreal\narborescent\narboretum\narbutus\narc\narcade\nArcadia\narcana\narcane\narccos\narccosine\narch\narchae\narchaic\narchaism\narchangel\narchbishop\narchdiocese\narchenemy\narchery\narchetype\narchetypical\narchfool\nArchibald\nArchimedes\narchipelago\narchitect\narchitectonic\narchitectural\narchitecture\narchival\narchive\narcing\narclength\narcsin\narcsine\narctan\narctangent\narctic\nArcturus\nArden\nardent\narduous\nare\narea\nareaway\nareawide\narena\narenaceous\naren't\nArequipa\nAres\nArgentina\nArgentine\nArgentinian\nargillaceous\narginine\nArgive\nargo\nargon\nArgonaut\nArgonne\nargot\nargue\nargument\nargumentation\nargumentative\nArgus\narhat\naria\nAriadne\nArianism\narid\nAries\narise\narisen\naristocracy\naristocrat\naristocratic\nAristotelean\nAristotelian\nAristotle\narithmetic\nArizona\nark\nArkansan\nArkansas\nArlen\nArlene\nArlington\narm\narmada\narmadillo\nArmageddon\narmament\nArmata\narmature\narmchair\nArmco\nArmenia\narmful\narmhole\narmillaria\narmistice\narmload\narmoire\nArmonk\nArmour\narmpit\nArmstrong\narmy\nArnold\naroma\naromatic\narose\naround\narousal\narouse\nARPA\narpeggio\narrack\nArragon\narraign\narrange\narrangeable\narray\narrear\narrest\nArrhenius\narrival\narrive\narrogant\narrogate\narrow\narrowhead\narrowroot\narroyo\narsenal\narsenate\narsenic\narsenide\narsine\narson\nart\nArtemis\nartemisia\narterial\narteriole\narteriolosclerosis\narteriosclerosis\nartery\nartful\narthritis\narthropod\nArthur\nartichoke\narticle\narticulate\narticulatory\nArtie\nartifact\nartifice\nartificial\nartillery\nartisan\nartistry\nArturo\nartwork\narty\nAruba\narum\naryl\na's\nas\nasbestos\nascend\nascendant\nascension\nascent\nascertain\nascetic\nascii\nascomycetes\nascribe\nascription\naseptic\nash\nashame\nashen\nAsher\nAsheville\nAshland\nAshley\nashman\nashmen\nAshmolean\nashore\nashram\nashtray\nashy\nAsia\nAsiatic\naside\nAsilomar\nasinine\nask\naskance\naskew\nasleep\nasocial\nasparagine\nasparagus\naspartic\naspect\naspen\nasperity\naspersion\nasphalt\naspheric\nasphyxiate\naspidistra\naspirant\naspirate\naspire\naspirin\nasplenium\nass\nassai\nassail\nassailant\nAssam\nassassin\nassassinate\nassault\nassay\nassemblage\nassemble\nassent\nassert\nassess\nassessor\nasset\nassiduity\nassiduous\nassign\nassignation\nassignee\nassimilable\nassimilate\nassist\nassistant\nassociable\nassociate\nassonant\nassort\nassuage\nassume\nassumption\nassurance\nassure\nAssyria\nAssyriology\nAstarte\nastatine\naster\nasteria\nasterisk\nasteroid\nasteroidal\nasthma\nastigmat\nastigmatic\nASTM\nastonish\nAstor\nAstoria\nastound\nastraddle\nastral\nastray\nastride\nastringent\nastrologer\nastrology\nastronaut\nastronautic\nastronomer\nastronomic\nastronomy\nastrophysical\nastrophysicist\nastrophysics\nastute\nAsuncion\nasunder\nasylum\nasymmetry\nasymptomatic\nasymptote\nasymptotic\nasynchronous\nasynchrony\nat\nAtalanta\natavism\natavistic\nAtchison\nate\nAthabascan\natheism\natheist\nAthena\nAthenian\nAthens\nathlete\nathletic\nathwart\nAtkins\nAtkinson\nAtlanta\natlantes\natlantic\nAtlantis\natlas\natmosphere\natmospheric\natoll\natom\natomic\natonal\natone\natonic\natop\nAtreus\natrocious\natrocity\natrophic\natrophy\nAtropos\nAT&T\nattach\nattache\nattack\nattain\nattainder\nattempt\nattend\nattendant\nattendee\nattention\nattentive\nattenuate\nattest\nattestation\nattic\nAttica\nattire\nattitude\nAttlee\nattorney\nattract\nattribute\nattribution\nattributive\nattrition\nattune\nAtwater\nAtwood\natypic\nAuberge\nAubrey\nauburn\nAuckland\nauction\nauctioneer\naudacious\naudacity\naudible\naudience\naudio\naudiotape\naudiovisual\naudit\naudition\nauditor\nauditorium\nauditory\nAudrey\nAudubon\nAuerbach\nAug\nAugean\nauger\naugite\naugment\naugmentation\naugur\naugust\nAugusta\nAugustine\nAugustus\nauk\naunt\nauntie\naura\naural\nAurelius\naureomycin\nauric\nAuriga\naurochs\naurora\nAuschwitz\nauspice\nauspices\nauspicious\naustenite\naustere\nAustin\naustral\nAustralia\nAustralis\naustralite\nAustria\nauthentic\nauthenticate\nauthor\nauthoritarian\nauthoritative\nautism\nautistic\nauto\nautobiography\nautochthonous\nautoclave\nautocollimate\nautocorrelate\nautocracy\nautocrat\nautocratic\nautograph\nautomat\nautomata\nautomate\nautomatic\nautomaton\nautomobile\nautomorphism\nautomotive\nautonomic\nautonomous\nautonomy\nautopilot\nautopsy\nautosuggestible\nautotransformer\nautumn\nautumnal\nauxiliary\nauxin\navail\navalanche\navarice\navaricious\nAve\navenge\nAventine\navenue\naver\naverage\nAvernus\naverred\naverring\naverse\naversion\navert\nAvery\nAvesta\navian\naviary\naviate\naviatrix\navid\nAvignon\navionic\nAvis\nAviv\navocado\navocate\navocet\nAvogadro\navoid\navoidance\nAvon\navow\navowal\nawait\nawake\nawaken\naward\naware\nawash\naway\nawe\nawesome\nawful\nawhile\nawkward\nawl\nawn\nawoke\nawry\nax\naxe\naxial\naxiology\naxiom\naxiomatic\naxis\naxisymmetric\naxle\naxolotl\naxon\naye\nAyers\nAylesbury\nAZ\nazalea\nAzerbaijan\nazimuth\nazimuthal\nAzores\nAztec\nAztecan\nazure\nb\nbabbitt\nbabble\nBabcock\nbabe\nBabel\nbaboon\nbaby\nBabylon\nbabysat\nbabysit\nbabysitting\nbaccalaureate\nbaccarat\nbacchanalian\nBacchus\nBach\nbachelor\nbacilli\nbacillus\nback\nbackboard\nbackbone\nbackdrop\nbackfill\nbackgammon\nbackground\nbackhand\nbacklash\nbacklog\nbackorder\nbackpack\nbackpedal\nbackplane\nbackplate\nbackscatter\nbackside\nbackslash\nbackslide\nbackspace\nbackstage\nbackstitch\nbackstop\nbacktrack\nbackup\nbackward\nbackwash\nbackwater\nbackwood\nbackyard\nbacon\nbacteria\nbacterial\nbacterium\nbad\nbade\nBaden\nbadge\nbadinage\nbadland\nbadminton\nBaffin\nbaffle\nbag\nbagatelle\nbaggage\nbagging\nbaggy\nBaghdad\nBagley\nbagpipe\nbah\nBahama\nBahrein\nbail\nBailey\nbailiff\nbainite\nBaird\nbait\nBaja\nbake\nBakelite\nBakersfield\nbakery\nBakhtiari\nbaklava\nBaku\nbalance\nBalboa\nbalcony\nbald\nbaldpate\nBaldwin\nbaldy\nbale\nbaleen\nbaleful\nBalfour\nBali\nBalinese\nbalk\nBalkan\nbalky\nball\nballad\nBallard\nballast\nballerina\nballet\nballetomane\nballfield\nballoon\nballot\nballroom\nballyhoo\nbalm\nbalmy\nbalsa\nbalsam\nBaltic\nBaltimore\nBaltimorean\nbalustrade\nBalzac\nbam\nBamako\nBamberger\nBambi\nbamboo\nban\nBanach\nbanal\nbanana\nBanbury\nband\nbandage\nbandgap\nbandit\nbandpass\nbandstand\nbandstop\nbandwagon\nbandwidth\nbandy\nbane\nbaneberry\nbaneful\nbang\nbangkok\nBangladesh\nbangle\nBangor\nBangui\nbanish\nbanister\nbanjo\nbank\nbankrupt\nbankruptcy\nbannock\nbanquet\nbanshee\nbantam\nbanter\nBantu\nBantus\nbaobab\nbaptism\nbaptismal\nBaptist\nBaptiste\nbaptistery\nbar\nbarb\nBarbados\nBarbara\nbarbarian\nbarbaric\nbarbarism\nbarbarous\nbarbecue\nbarbell\nbarber\nbarberry\nbarbital\nbarbiturate\nBarbour\nbarbudo\nBarcelona\nBarclay\nbard\nbare\nbareback\nbarefaced\nbarefoot\nbarfly\nbargain\nbarge\nbaritone\nbarium\nbark\nbarkeep\nbarley\nBarlow\nbarn\nBarnabas\nbarnacle\nBarnard\nBarnes\nBarnet\nBarnett\nBarney\nBarnhard\nbarnstorm\nBarnum\nbarnyard\nbarometer\nbaron\nbaroness\nbaronet\nbaronial\nbarony\nbaroque\nBarr\nbarrack\nbarracuda\nbarrage\nbarre\nbarrel\nbarren\nBarrett\nbarrette\nbarricade\nbarrier\nBarrington\nbarrow\nBarry\nBarrymore\nBarstow\nbartend\nbartender\nbarter\nBarth\nBartholomew\nBartlett\nBartok\nBarton\nbarycentric\nbaryon\nbasal\nbasalt\nbasaltic\nbase\nbaseball\nbaseband\nbaseboard\nBasel\nbaseline\nbaseman\nbasemen\nbaseplate\nbasepoint\nbash\nbashaw\nbashful\nbasic\nbasidiomycetes\nbasil\nbasilar\nbasilica\nbasilisk\nbasin\nbasis\nbask\nbasket\nbasketball\nbasketry\nbasophilic\nBasque\nbass\nBassett\nbassi\nbassinet\nbasso\nbassoon\nbasswood\nbastard\nbaste\nbastion\nbat\nBatavia\nbatch\nBatchelder\nbate\nbateau\nBateman\nbater\nbath\nbathe\nbathos\nbathrobe\nbathroom\nbathtub\nBathurst\nbatik\nbaton\nBator\nbatt\nbattalion\nBattelle\nbatten\nbattery\nbattle\nbattlefield\nbattlefront\nbattleground\nbatwing\nbauble\nbaud\nBaudelaire\nBauer\nBauhaus\nBausch\nbauxite\nBavaria\nbawd\nbawdy\nbawl\nBaxter\nbay\nbayberry\nBayda\nBayesian\nBaylor\nbayonet\nBayonne\nbayou\nBayport\nBayreuth\nbazaar\nbe\nbeach\nbeachhead\nbeacon\nbead\nbeadle\nbeady\nbeagle\nbeak\nbeam\nbean\nbear\nbearberry\nbeard\nBeardsley\nbearish\nbeast\nbeastie\nbeat\nbeaten\nbeater\nbeatific\nbeatify\nbeatitude\nbeatnik\nBeatrice\nbeau\nBeaujolais\nBeaumont\nBeauregard\nbeauteous\nbeautiful\nbeautify\nbeauty\nbeaux\nbeaver\nbebop\nbecalm\nbecame\nbecause\nBechtel\nbeck\nbecket\nBeckman\nbeckon\nBecky\nbecome\nbed\nbedazzle\nbedbug\nbedevil\nbedfast\nbedfellow\nBedford\nbedim\nbedimmed\nbedimming\nbedlam\nbedpost\nbedraggle\nbedridden\nbedrock\nbedroom\nbedside\nbedspread\nbedspring\nbedstraw\nbedtime\nbee\nBeebe\nbeebread\nbeech\nBeecham\nbeechwood\nbeef\nbeefsteak\nbeefy\nbeehive\nbeen\nbeep\nbeer\nbeeswax\nbeet\nBeethoven\nbeetle\nbefall\nbefallen\nbefell\nbefit\nbefitting\nbefog\nbefogging\nbefore\nbeforehand\nbefoul\nbefriend\nbefuddle\nbeg\nbegan\nbegat\nbeget\nbegetting\nbeggar\nbeggary\nbegging\nbegin\nbeginner\nbeginning\nbegonia\nbegot\nbegotten\nbegrudge\nbeguile\nbegun\nbehalf\nbehave\nbehead\nbeheld\nbehind\nbehold\nbeige\nBeijing\nbeing\nBeirut\nbel\nBela\nbelate\nbelch\nBelfast\nbelfry\nBelgian\nBelgium\nBelgrade\nbelie\nbelief\nbelieve\nbelittle\nBelize\nbell\nBella\nbelladonna\nBellamy\nBellatrix\nbellboy\nbelle\nbellflower\nbellhop\nbellicose\nbelligerent\nBellingham\nBellini\nbellman\nbellmen\nbellow\nbellum\nbellwether\nbelly\nbellyache\nbellyaching\nbellyful\nBelmont\nBeloit\nbelong\nbelove\nbelow\nBelshazzar\nbelt\nBeltsville\nbeluga\nbelvedere\nBEMA\nbemadden\nbeman\nbemoan\nbemuse\nBen\nBenares\nbench\nbenchmark\nbend\nBendix\nbeneath\nBenedict\nBenedictine\nbenediction\nBenedikt\nbenefactor\nbenefice\nbeneficent\nbeneficial\nbeneficiary\nbenefit\nBenelux\nbenevolent\nBengal\nBengali\nbenight\nbenign\nBenjamin\nBennett\nBennington\nBenny\nBenson\nbent\nBentham\nbenthic\nBentley\nBenton\nBenz\nBenzedrine\nbenzene\nBeograd\nBeowulf\nbeplaster\nbequeath\nbequest\nberate\nBerea\nbereave\nbereft\nBerenices\nBeresford\nberet\nberg\nbergamot\nBergen\nBergland\nBerglund\nBergman\nBergson\nBergstrom\nberibbon\nberiberi\nBerkeley\nberkelium\nBerkowitz\nBerkshire\nBerlin\nBerlioz\nBerlitz\nBerman\nBermuda\nBern\nBernadine\nBernard\nBernardino\nBernardo\nberne\nBernet\nBernhard\nBernice\nBernie\nBerniece\nBernini\nBernoulli\nBernstein\nBerra\nberry\nberserk\nBert\nberth\nBertha\nBertie\nBertram\nBertrand\nBerwick\nberyl\nberyllium\nbeseech\nbeset\nbesetting\nbeside\nbesiege\nbesmirch\nbesotted\nbespeak\nbespectacled\nbespoke\nBess\nBessel\nBessemer\nBessie\nbest\nbestial\nbestiary\nbestir\nbestirring\nbestow\nbestowal\nbestseller\nbestselling\nbestubble\nbet\nbeta\nbetatron\nbetel\nBetelgeuse\nbeth\nbethel\nBethesda\nBethlehem\nbethought\nbetide\nbetoken\nbetony\nbetray\nbetrayal\nbetroth\nbetrothal\nBetsey\nBetsy\nBette\nbettor\nBetty\nbetween\nbetwixt\nbevel\nbeverage\nBeverly\nbevy\nbewail\nbeware\nbewhisker\nbewilder\nbewitch\nbey\nbeyond\nbezel\nBhagavadgita\nbhoy\nBhutan\nBialystok\nbianco\nbias\nbiaxial\nbib\nbibb\nBible\nbiblical\nbibliography\nbibliophile\nbicameral\nbicarbonate\nbicep\nbichromate\nbicker\nbiconcave\nbiconnected\nbicycle\nbid\nbidden\nbiddy\nbide\nbidiagonal\nbidirectional\nbien\nbiennial\nbiennium\nbifocal\nbifurcate\nbig\nbigamy\nBigelow\nBiggs\nbighorn\nbigot\nbigotry\nbiharmonic\nbijection\nbijective\nbijouterie\nbike\nbikini\nbilabial\nbilateral\nbilayer\nBilbao\nbile\nbilge\nbilharziasis\nbilinear\nbilingual\nbilk\nbill\nbillboard\nbillet\nbillfold\nbilliard\nBillie\nBilliken\nbillion\nbillionth\nbillow\nbilly\nBiltmore\nbimetallic\nbimetallism\nBimini\nbimodal\nbimolecular\nbimonthly\nbin\nbinary\nbinaural\nbind\nbindery\nbindle\nbindweed\nbing\nbinge\nBingham\nBinghamton\nbingle\nBini\nbinocular\nbinomial\nbinuclear\nbiochemic\nbiography\nbiology\nbiometry\nbiopsy\nbiota\nbiotic\nbiotite\nbipartisan\nbipartite\nbipedal\nbiplane\nbipolar\nbiracial\nbirch\nbird\nbirdbath\nbirdcage\nbirdie\nbirdseed\nbirdwatch\nbirefringent\nBirgit\nBirmingham\nbirth\nbirthday\nbirthplace\nbirthrate\nbirthright\nbiscuit\nbisect\nbisexual\nbishop\nbishopric\nBismarck\nBismark\nbismuth\nbison\nbisque\nBissau\nbistable\nbistate\nbit\nbitch\nbite\nbitnet\nbitt\nbitten\nbittern\nbitternut\nbitterroot\nbittersweet\nbitumen\nbituminous\nbitwise\nbivalve\nbivariate\nbivouac\nbiz\nbizarre\nBizet\nblab\nblack\nblackball\nblackberry\nblackbird\nblackboard\nblackbody\nBlackburn\nblacken\nBlackfeet\nBlackfoot\nblackguard\nblackjack\nblackmail\nBlackman\nblackout\nblacksmith\nBlackstone\nblacktop\nBlackwell\nbladder\nbladdernut\nbladderwort\nblade\nBlaine\nBlair\nBlake\nblame\nblameworthy\nblanc\nblanch\nBlanchard\nBlanche\nbland\nblandish\nblank\nblanket\nblare\nblaspheme\nblasphemous\nblasphemy\nblast\nblastula\nblat\nblatant\nblather\nBlatz\nblaze\nblazon\nbleach\nbleak\nbleary\nbleat\nbled\nbleed\nBleeker\nblemish\nblend\nBlenheim\nbless\nblest\nblew\nblight\nblimp\nblind\nblindfold\nblink\nBlinn\nblip\nbliss\nblissful\nblister\nblithe\nblitz\nblitzkrieg\nblizzard\nbloat\nblob\nbloc\nBloch\nblock\nblockade\nblockage\nblockhouse\nblocky\nbloke\nBlomberg\nBlomquist\nblond\nblonde\nblood\nbloodbath\nbloodhound\nbloodletting\nbloodline\nbloodroot\nbloodshed\nbloodshot\nbloodstain\nbloodstone\nbloodstream\nbloody\nbloom\nBloomfield\nBloomington\nbloop\nblossom\nblot\nblotch\nblouse\nblow\nblowfish\nblown\nblowup\nblubber\nbludgeon\nblue\nblueback\nblueberry\nbluebill\nbluebird\nbluebonnet\nbluebook\nbluebush\nbluefish\nbluegill\nbluegrass\nbluejacket\nblueprint\nbluestocking\nbluet\nbluff\nbluish\nBlum\nBlumenthal\nblunder\nblunderbuss\nblunt\nblur\nblurb\nblurry\nblurt\nblush\nbluster\nblustery\nblutwurst\nBlvd\nBlythe\nBMW\nboa\nboar\nboard\nboardinghouse\nboast\nboastful\nboat\nboathouse\nboatload\nboatman\nboatmen\nboatswain\nboatyard\nbob\nBobbie\nbobbin\nbobble\nbobby\nbobcat\nbobolink\nBoca\nbock\nbode\nbodhisattva\nbodice\nBodleian\nbody\nbodybuilder\nbodybuilding\nbodyguard\nBoeing\nBoeotia\nbog\nbogey\nbogeyman\nbogeymen\nbogging\nboggle\nboggy\nBogota\nbogus\nbogy\nBohemia\nBohr\nboil\nBois\nBoise\nboisterous\nbold\nboldface\nbole\nboletus\nbolivar\nBolivia\nbolo\nBologna\nbolometer\nBolshevik\nBolshevism\nBolshevist\nBolshoi\nbolster\nbolt\nBolton\nBoltzmann\nbomb\nbombard\nbombast\nbombastic\nBombay\nbombproof\nbon\nbona\nbonanza\nBonaparte\nBonaventure\nbond\nbondage\nbondsman\nbondsmen\nbone\nbonfire\nbong\nbongo\nBoniface\nbonito\nBonn\nbonnet\nBonneville\nBonnie\nbonus\nbony\nbonze\nboo\nbooby\nboogie\nbook\nbookbind\nbookcase\nbookend\nbookie\nbookish\nbookkeep\nbooklet\nbookmark\nbookplate\nbookseller\nbookshelf\nbookshelves\nbookstore\nbookworm\nbooky\nboolean\nboom\nboomerang\nboon\nBoone\nboor\nboorish\nboost\nboot\nBootes\nbooth\nbootleg\nbootlegger\nbootlegging\nbootstrap\nbootstrapping\nbooty\nbooze\nbop\nborate\nborax\nBordeaux\nbordello\nBorden\nborder\nborderland\nborderline\nbore\nboreal\nBorealis\nBoreas\nboredom\nBorg\nboric\nBoris\nborn\nborne\nBorneo\nboron\nborosilicate\nborough\nBorroughs\nborrow\nBosch\nBose\nbosom\nboson\nbosonic\nBosporus\nboss\nbossy\nBoston\nBoswell\nbotanic\nbotanist\nbotany\nbotch\nbotfly\nboth\nbothersome\nBotswana\nbottle\nbottlecap\nbottleneck\nbottom\nbottommost\nbotulin\nbotulism\nBoucher\nbouffant\nbough\nbought\nbouillabaisse\nbouillon\nboulder\nboulevard\nbounce\nbouncy\nbound\nboundary\nbountiful\nbounty\nbouquet\nBourbaki\nbourbon\nbourgeois\nbourgeoisie\nbourn\nboustrophedon\nbout\nboutique\nbovine\nbow\nBowditch\nBowdoin\nbowel\nBowen\nbowerbird\nbowfin\nbowie\nbowl\nbowline\nbowman\nbowmen\nbowstring\nbox\nboxcar\nboxwood\nboxy\nboy\nboyar\nBoyce\nboycott\nBoyd\nboyish\nBoyle\nBoylston\nBP\nbrace\nbracelet\nbracken\nbracket\nbrackish\nbract\nbrad\nBradbury\nBradford\nBradley\nBradshaw\nBrady\nbrae\nbrag\nBragg\nbragging\nBrahmaputra\nBrahms\nBrahmsian\nbraid\nBraille\nbrain\nBrainard\nbrainchild\nbrainstorm\nbrainwash\nbrainy\nbrake\nbrakeman\nbrakemen\nbramble\nbran\nbranch\nbrand\nBrandeis\nBrandenburg\nbrandish\nBrandon\nBrandt\nbrandy\nbrandywine\nBraniff\nbrant\nbrash\nBrasilia\nbrass\nbrassiere\nbrassy\nbratwurst\nBraun\nbravado\nbrave\nbravery\nbravo\nbravura\nbrawl\nbray\nbrazen\nbrazier\nBrazil\nBrazilian\nBrazzaville\nbreach\nbread\nbreadboard\nbreadfruit\nbreadroot\nbreadth\nbreak\nbreakage\nbreakaway\nbreakdown\nbreakfast\nbreakneck\nbreakoff\nbreakpoint\nbreakthrough\nbreakup\nbreakwater\nbream\nbreast\nbreastplate\nbreastwork\nbreath\nbreathe\nbreathtaking\nbreathy\nbreccia\nbred\nbreech\nbreed\nbreeze\nbreezy\nBremen\nbremsstrahlung\nBrenda\nBrendan\nBrennan\nBrenner\nBrent\nBrest\nbrethren\nBreton\nBrett\nbreve\nbrevet\nbrevity\nbrew\nbrewery\nBrewster\nBrian\nbriar\nbribe\nbribery\nBrice\nbrick\nbrickbat\nbricklayer\nbricklaying\nbridal\nbride\nbridegroom\nbridesmaid\nbridge\nbridgeable\nbridgehead\nBridgeport\nBridget\nBridgetown\nBridgewater\nbridgework\nbridle\nBrie\nbrief\nbriefcase\nbrig\nbrigade\nbrigadier\nbrigand\nbrigantine\nBriggs\nBrigham\nbright\nbrighten\nBrighton\nbrilliant\nBrillouin\nbrim\nbrimful\nbrimstone\nBrindisi\nbrindle\nbrine\nbring\nbrink\nbrinkmanship\nbriny\nBrisbane\nbrisk\nbristle\nbristlecone\nbristly\nBristol\nBritain\nBritannic\nBritannica\nbritches\nBritish\nBriton\nBrittany\nBritten\nbrittle\nbroach\nbroad\nbroadcast\nbroaden\nbroadloom\nbroadminded\nbroadside\nBroadway\nbrocade\nbroccoli\nbrochure\nBrock\nbrockle\nBroglie\nbroil\nbroke\nbroken\nbrokerage\nBromfield\nbromide\nbromine\nBromley\nbronchi\nbronchial\nbronchiolar\nbronchiole\nbronchitis\nbronchus\nbronco\nBrontosaurus\nBronx\nbronze\nbronzy\nbrood\nbroody\nbrook\nBrooke\nBrookhaven\nBrookline\nBrooklyn\nbrookside\nbroom\nbroomcorn\nbroth\nbrothel\nbrother\nbrought\nbrouhaha\nbrow\nbrowbeaten\nbrown\nBrowne\nBrownell\nBrownian\nbrownie\nbrownish\nbrowse\nBruce\nbrucellosis\nBruckner\nBruegel\nbruise\nbruit\nBrumidi\nbrunch\nbrunette\nBrunhilde\nBruno\nBrunswick\nbrunt\nbrush\nbrushfire\nbrushstroke\nbrushwork\nbrushy\nbrusque\nBrussels\nbrutal\nbrute\nBryan\nBryant\nBryce\nBryn\nbryophyta\nbryophyte\nbryozoa\nb's\nBSTJ\nBTL\nbub\nbubble\nbubonic\nbuccaneer\nBuchanan\nBucharest\nBuchenwald\nBuchwald\nbuck\nbuckaroo\nbuckboard\nbucket\nbucketful\nbuckeye\nbuckhorn\nbuckle\nBuckley\nBucknell\nbuckshot\nbuckskin\nbuckthorn\nbuckwheat\nbucolic\nbud\nBudapest\nBudd\nBuddha\nBuddhism\nBuddhist\nbuddy\nbudge\nbudget\nbudgetary\nBudweiser\nBuena\nBuenos\nbuff\nbuffalo\nbuffet\nbufflehead\nbuffoon\nbug\nbugaboo\nbugeyed\nbugging\nbuggy\nbugle\nBuick\nbuild\nbuildup\nbuilt\nbuiltin\nBujumbura\nbulb\nbulblet\nbulbous\nBulgaria\nbulge\nbulk\nbulkhead\nbulky\nbull\nbulldog\nbulldoze\nbullet\nbulletin\nbullfinch\nbullfrog\nbullhead\nbullhide\nbullish\nbullock\nbullrush\nbullseye\nbullwhack\nbully\nbullyboy\nbulrush\nbulwark\nbum\nbumble\nbumblebee\nbump\nbumpkin\nbumptious\nbumpy\nbun\nbunch\nBundestag\nbundle\nBundoora\nbundy\nbungalow\nbungle\nbunk\nbunkmate\nbunny\nBunsen\nbunt\nBunyan\nbuoy\nbuoyant\nburbank\nBurch\nburden\nburdensome\nburdock\nbureau\nbureaucracy\nbureaucrat\nbureaucratic\nburet\nburette\nburg\nburgeon\nburgess\nburgher\nburglar\nburglarproof\nburglary\nBurgundian\nBurgundy\nburial\nBurke\nburl\nburlap\nburlesque\nburley\nBurlington\nburly\nBurma\nBurmese\nburn\nBurnett\nBurnham\nburnish\nburnout\nBurnside\nburnt\nburp\nBurr\nburro\nBurroughs\nburrow\nbursitis\nburst\nbursty\nBurt\nBurton\nBurtt\nBurundi\nbury\nbus\nbusboy\nBusch\nbush\nbushel\nbushland\nbushmaster\nBushnell\nbushwhack\nbushy\nbusiness\nbusinessman\nbusinessmen\nbusinesswoman\nbusinesswomen\nbusload\nbuss\nbust\nbustard\nbustle\nbusy\nbusywork\nbut\nbutadiene\nbutane\nbutch\nbutchery\nbutene\nbuteo\nbutler\nbutt\nbutte\nbutterball\nbuttercup\nbutterfat\nButterfield\nbutterfly\nbuttermilk\nbutternut\nbutterscotch\nbuttery\nbuttock\nbutton\nbuttonhole\nbuttonweed\nbuttress\nButtrick\nbutyl\nbutyrate\nbutyric\nbuxom\nBuxtehude\nBuxton\nbuy\nbuzz\nbuzzard\nbuzzing\nbuzzword\nbuzzy\nby\nbye\nbygone\nbylaw\nbyline\nbypass\nbypath\nbyproduct\nByrd\nByrne\nbyroad\nByron\nByronic\nbystander\nbyte\nbyway\nbyword\nByzantine\nByzantium\nc\nCA\ncab\ncabal\ncabana\ncabaret\ncabbage\ncabdriver\ncabin\ncabinet\ncabinetmake\ncabinetry\ncable\nCabot\ncacao\ncachalot\ncache\ncaching\ncackle\nCACM\ncacophonist\ncacophonous\ncacophony\ncacti\ncactus\ncadaver\ncadaverous\ncaddis\ncaddy\ncadent\ncadenza\ncadet\nCadillac\ncadmium\ncadre\nCady\nCaesar\nCaesarian\ncafe\ncafeteria\ncage\ncagey\nCahill\ncahoot\ncaiman\nCain\nCaine\ncairn\nCairo\ncajole\nCajun\ncake\nCal\ncalabash\nCalais\ncalamitous\ncalamity\ncalamus\ncalcareous\ncalcify\ncalcite\ncalcium\ncalculable\ncalculate\ncalculi\ncalculus\nCalcutta\nCalder\ncaldera\nCaldwell\nCaleb\ncalendar\ncalendrical\ncalf\ncalfskin\nCalgary\nCalhoun\ncaliber\ncalibrate\ncalibre\ncalico\nCalifornia\ncalifornium\ncaliper\ncaliph\ncaliphate\ncalisthenic\nCalkins\ncall\ncalla\nCallaghan\nCallahan\ncalligraph\ncalligraphy\ncalliope\nCallisto\ncallosity\ncallous\ncallus\ncalm\ncaloric\ncalorie\ncalorimeter\nCalumet\ncalumniate\ncalumny\nCalvary\ncalve\nCalvert\nCalvin\ncalypso\ncalyx\ncam\ncamaraderie\ncamber\nCambodia\nCambrian\ncambric\nCambridge\nCamden\ncame\ncamel\ncamelback\ncamellia\ncamelopard\nCamelot\nCamembert\ncameo\ncamera\ncameraman\ncameramen\nCameron\nCameroon\nCameroun\ncamilla\nCamille\nCamino\ncamouflage\ncamp\ncampaign\ncampanile\nCampbell\ncampfire\ncampground\ncampion\ncampsite\ncampus\ncan\nCanaan\nCanada\nCanadian\ncanal\ncanary\nCanaveral\nCanberra\ncancel\ncancellate\ncancelled\ncancelling\ncancer\ncancerous\ncandela\ncandelabra\ncandid\ncandidacy\ncandidate\nCandide\ncandle\ncandlelight\ncandlestick\ncandlewick\ncandy\ncane\nCanfield\ncanine\nCanis\ncanister\ncanker\ncankerworm\ncanna\ncannabis\ncannel\ncannery\ncannibal\ncannister\ncannon\ncannonball\ncannot\ncanny\ncanoe\ncanoeist\nCanoga\ncanon\ncanonic\nCanopus\ncanopy\ncan't\ncant\nCantabrigian\ncantaloupe\ncanteen\nCanterbury\ncanterelle\ncanticle\ncantilever\ncantle\ncanto\ncanton\nCantonese\ncantor\ncanvas\ncanvasback\ncanvass\ncanyon\ncap\ncapacious\ncapacitance\ncapacitate\ncapacitive\ncapacitor\ncapacity\ncape\ncapella\ncaper\nCapetown\ncapillary\nCapistrano\ncapita\ncapital\ncapitol\nCapitoline\ncapitulate\ncapo\ncaprice\ncapricious\nCapricorn\ncapsize\ncapstan\ncapstone\ncapsule\ncaptain\ncaptaincy\ncaption\ncaptious\ncaptivate\ncaptive\ncaptor\ncapture\ncapuchin\nCaputo\ncapybara\ncar\ncarabao\nCaracas\ncaramel\ncarapace\ncaravan\ncaraway\ncarbide\ncarbine\ncarbohydrate\nCarboloy\ncarbon\ncarbonaceous\ncarbonate\nCarbondale\nCarbone\ncarbonic\nCarboniferous\ncarbonium\ncarbonyl\ncarborundum\ncarboxy\ncarboxylic\ncarboy\ncarbuncle\ncarcass\ncarcinogen\ncarcinogenic\ncarcinoma\ncard\ncardamom\ncardboard\ncardiac\nCardiff\ncardigan\ncardinal\ncardioid\ncardiology\ncardiovascular\ncare\ncareen\ncareer\ncarefree\ncareful\ncaress\ncaret\ncaretaker\ncareworn\nCarey\nCargill\ncargo\ncargoes\nCarib\nCaribbean\ncaribou\ncaricature\nCarl\nCarla\nCarleton\nCarlin\nCarlisle\nCarlo\ncarload\nCarlsbad\nCarlson\nCarlton\nCarlyle\nCarmela\nCarmen\nCarmichael\ncarmine\ncarnage\ncarnal\ncarnation\ncarne\nCarnegie\ncarney\ncarnival\ncarob\ncarol\nCarolina\nCaroline\nCarolingian\nCarolinian\nCarolyn\ncarouse\ncarousel\ncarp\ncarpal\nCarpathia\ncarpenter\ncarpentry\ncarpet\ncarpetbag\ncarpetbagger\ncarpetbagging\ncarport\nCarr\ncarrageen\nCarrara\ncarrel\ncarriage\nCarrie\ncarrion\nCarroll\ncarrot\nCarruthers\ncarry\ncarryover\nCarson\ncart\ncarte\ncartel\nCartesian\nCarthage\ncartilage\ncartilaginous\ncartographer\ncartography\ncarton\ncartoon\ncartridge\ncartwheel\nCaruso\ncarve\ncarven\nCasanova\ncasbah\ncascade\ncascara\ncase\ncasebook\ncasein\ncasework\nCasey\ncash\ncashew\ncashier\ncashmere\ncasino\ncask\ncasket\nCassandra\ncassava\ncasserole\ncassette\nCassiopeia\nCassius\ncassock\ncast\ncastanet\ncaste\ncasteth\ncastigate\nCastillo\ncastle\ncastor\ncastrate\nCastro\ncasual\ncasualty\ncat\ncataclysmic\ncataleptic\nCatalina\ncatalogue\nCatalonia\ncatalpa\ncatalysis\ncatalyst\ncatalytic\ncatapult\ncataract\ncatastrophe\ncatastrophic\ncatatonia\ncatatonic\ncatawba\ncatbird\ncatch\ncatchup\ncatchword\ncatchy\ncatechism\ncategoric\ncategory\ncatenate\ncater\ncaterpillar\ncatfish\ncatharsis\ncathedral\nCatherine\nCatherwood\ncatheter\ncathode\ncathodic\ncatholic\nCathy\ncation\ncationic\ncatkin\ncatnip\nCatskill\ncatsup\ncattail\ncattle\ncattleman\ncattlemen\ncatwalk\nCaucasian\nCaucasus\nCauchy\ncaucus\ncaudal\ncaught\ncauliflower\ncaulk\ncausal\ncausate\ncause\ncaustic\ncaution\ncautionary\ncautious\ncavalcade\ncavalier\ncavalry\ncave\ncaveat\ncaveman\ncavemen\nCavendish\ncavern\ncavernous\ncaviar\ncavil\ncavilling\nCaviness\ncavort\ncaw\ncayenne\nCayley\nCayuga\nCBS\nCDC\ncease\nceasefire\nCecil\nCecilia\nCecropia\ncedar\ncede\ncedilla\nCedric\nceil\ncelandine\nCelanese\nCelebes\ncelebrant\ncelebrate\ncelebratory\ncelebrity\ncelerity\ncelery\ncelesta\ncelestial\nCelia\ncell\ncellar\ncellophane\ncellular\ncelluloid\ncellulose\nCelsius\nCelt\nCeltic\ncement\ncemetery\nCenozoic\ncensor\ncensorial\ncensure\ncensus\ncent\ncentaur\ncentenary\ncentennial\ncenterline\ncenterpiece\ncentigrade\ncentipede\ncentral\ncentrex\ncentric\ncentrifugal\ncentrifugate\ncentrifuge\ncentripetal\ncentrist\ncentroid\ncentum\ncentury\nCepheus\nceramic\nceramium\nCerberus\ncereal\ncerebellum\ncerebral\ncerebrate\nceremonial\nceremonious\nceremony\nCeres\ncereus\ncerise\ncerium\nCERN\ncertain\ncertainty\ncertificate\ncertify\ncertiorari\ncertitude\ncerulean\nCervantes\ncervix\nCesare\ncesium\ncessation\ncession\nCessna\ncetacean\ncetera\nCetus\nCeylon\nCezanne\ncf\nChablis\nChad\nChadwick\nchafe\nchaff\nchagrin\nchain\nchair\nchairlady\nchairman\nchairmen\nchairperson\nchairwoman\nchairwomen\nchaise\nchalcedony\nchalcocite\nchalice\nchalk\nchalkline\nchalky\nchallenge\nChalmers\nchamber\nchamberlain\nchambermaid\nchameleon\nchamfer\nchamois\nchamomile\nchamp\nchampagne\nChampaign\nchampion\nChamplain\nchance\nchancel\nchancellor\nchancery\nchancy\nchandelier\nChandigarh\nchandler\nChang\nchange\nchangeable\nchangeover\nchannel\nchanson\nchant\nchantey\nChantilly\nchantry\nChao\nchaos\nchaotic\nchap\nchaparral\nchapati\nchapel\nchaperon\nchaperone\nchaplain\nChaplin\nChapman\nchapter\nchar\ncharacter\ncharacteristic\ncharcoal\ncharcuterie\nchard\ncharge\nchargeable\nchariot\ncharisma\ncharismatic\ncharitable\ncharity\nCharlemagne\nCharles\nCharleston\nCharley\nCharlie\nCharlotte\nCharlottesville\ncharm\nCharon\nchart\nCharta\nChartres\nchartreuse\nchartroom\nCharybdis\nchase\nchasm\nchassis\nchaste\nchastise\nchastity\nchat\nchateau\nchateaux\nChatham\nChattanooga\nchattel\nchatty\nChaucer\nchauffeur\nChauncey\nChautauqua\nchauvinism\nchauvinist\nchaw\ncheap\ncheat\ncheater\ncheck\ncheckbook\ncheckerberry\ncheckerboard\nchecklist\ncheckout\ncheckpoint\nchecksum\nchecksummed\nchecksumming\ncheckup\nCheddar\ncheek\ncheekbone\ncheeky\ncheer\ncheerful\ncheerleader\ncheery\ncheese\ncheesecake\ncheesecloth\ncheesemaking\ncheesy\ncheetah\nchef\nchelate\nChelsea\nchemic\nchemise\nchemisorb\nchemisorption\nchemist\nchemistry\nchemotherapy\nChen\nCheney\nchenille\ncherish\nCherokee\ncherry\nchert\ncherub\ncherubim\nCheryl\nChesapeake\nCheshire\nchess\nchest\nChester\nChesterton\nchestnut\nchevalier\nChevrolet\nchevron\nchevy\nchew\nchewy\nCheyenne\nchi\nChiang\nchianti\nchic\nChicago\nChicagoan\nchicanery\nChicano\nchick\nchickadee\nchicken\nchickpea\nchickweed\nchicory\nchide\nchief\nchiefdom\nchieftain\nchiffon\nchigger\nchignon\nchilblain\nchild\nchildbearing\nchildbirth\nchildish\nchildrearing\nchildren\nChile\nchili\nchill\nchilly\nchime\nchimera\nchimeric\nChimique\nchimney\nchimpanzee\nchin\nchina\nChinaman\nChinamen\nChinatown\nchinch\nchinchilla\nchine\nChinese\nchink\nChinook\nchinquapin\nchintz\nchintzy\nchip\nchipboard\nchipmunk\nChippendale\nchiropractor\nchirp\nchisel\nChisholm\nchit\nchitin\nchitinous\nchiton\nchivalrous\nchivalry\nchive\nChloe\nchlorate\nchlordane\nchloride\nchlorine\nchloroform\nchlorophyll\nchloroplast\nchloroplatinate\nchock\nchocolate\nChoctaw\nchoice\nchoir\nchoirmaster\nchoke\nchokeberry\ncholera\ncholesterol\ncholine\ncholinesterase\nchomp\nChomsky\nchondrite\nchoose\nchoosy\nchop\nChopin\nchoppy\nchopstick\nchoral\nchorale\nchord\nchordal\nchordata\nchordate\nchore\nchoreograph\nchoreography\nchorine\nchortle\nchorus\nchoryza\nchose\nchosen\nChou\nchow\nchowder\nChris\nChrist\nchristen\nChristendom\nChristensen\nChristenson\nChristian\nChristiana\nChristianson\nChristie\nChristina\nChristine\nChristmas\nChristoffel\nChristoph\nChristopher\nChristy\nchromate\nchromatic\nchromatin\nchromatogram\nchromatograph\nchromatography\nchrome\nchromic\nchromium\nchromosomal\nchromosome\nchromosphere\nchronic\nchronicle\nchronograph\nchronography\nchronology\nchrysalis\nchrysanthemum\nChrysler\nchrysolite\nchub\nchubby\nchuck\nchuckle\nchuckwalla\nchuff\nchug\nchugging\nchum\nchummy\nchump\nChungking\nchunk\nchunky\nchurch\nchurchgoer\nchurchgoing\nChurchill\nChurchillian\nchurchman\nchurchmen\nchurchwoman\nchurchwomen\nchurchyard\nchurn\nchute\nchutney\nCIA\ncicada\nCicero\nCiceronian\ncider\ncigar\ncigarette\ncilia\nciliate\ncinch\nCincinnati\ncinder\nCinderella\nCindy\ncinema\ncinematic\nCinerama\ncinnabar\ncinnamon\ncinquefoil\ncipher\ncirca\ncircadian\nCirce\ncircle\ncirclet\ncircuit\ncircuitous\ncircuitry\ncirculant\ncircular\ncirculate\ncirculatory\ncircumcircle\ncircumcise\ncircumcision\ncircumference\ncircumferential\ncircumflex\ncircumlocution\ncircumpolar\ncircumscribe\ncircumscription\ncircumspect\ncircumsphere\ncircumstance\ncircumstantial\ncircumvent\ncircumvention\ncircus\ncistern\ncit\ncitadel\ncitation\ncite\ncitizen\ncitizenry\ncitrate\ncitric\nCitroen\ncitron\ncitrus\ncity\ncityscape\ncitywide\ncivet\ncivic\ncivil\ncivilian\nclad\ncladophora\nclaim\nclaimant\nClaire\nclairvoyant\nclam\nclamber\nclammy\nclamp\nclamshell\nclan\nclandestine\nclang\nclank\nclannish\nclap\nclapboard\nClapeyron\nClara\nClare\nClaremont\nClarence\nClarendon\nclaret\nclarify\nclarinet\nclarity\nClark\nClarke\nclash\nclasp\nclass\nclassic\nclassificatory\nclassify\nclassmate\nclassroom\nclassy\nclatter\nclattery\nClaude\nClaudia\nClaudio\nClaus\nclause\nClausen\nClausius\nclaustrophobia\nclaustrophobic\nclavicle\nclaw\nclay\nClayton\nclean\ncleanse\ncleanup\nclear\nclearance\nclearheaded\nClearwater\ncleat\ncleavage\ncleave\nclef\ncleft\nClemens\nclement\nClemson\nclench\nclergy\nclergyman\nclergymen\ncleric\nclerk\nCleveland\nclever\ncliche\nclick\nclient\nclientele\ncliff\ncliffhang\nClifford\nClifton\nclimactic\nclimate\nclimatic\nclimatology\nclimax\nclimb\nclime\nclinch\ncling\nclinic\nclinician\nclink\nClint\nClinton\nClio\nclip\nclipboard\nclique\nclitoris\nClive\ncloaca\ncloacal\ncloak\ncloakroom\nclobber\nclock\nclockwatcher\nclockwise\nclockwork\nclod\ncloddish\nclog\nclogging\ncloister\nclomp\nclone\nclonic\nclose\ncloset\ncloseup\nclosure\nclot\ncloth\nclothbound\nclothe\nclothesbrush\nclotheshorse\nclothesline\nclothesman\nclothesmen\nclothier\nClotho\ncloture\ncloud\ncloudburst\ncloudy\nclout\nclove\nclown\nclownish\ncloy\nclub\nclubhouse\nclubroom\ncluck\nclue\nCluj\nclump\nclumsy\nclung\ncluster\nclutch\nclutter\nClyde\nClytemnestra\nCO\nco\ncoach\ncoachman\ncoachmen\ncoachwork\ncoadjutor\ncoagulable\ncoagulate\ncoal\ncoalesce\ncoalescent\ncoalition\ncoarse\ncoarsen\ncoast\ncoastal\ncoastline\ncoat\nCoates\ncoattail\ncoauthor\ncoax\ncoaxial\ncob\ncobalt\nCobb\ncobble\ncobblestone\nCobol\ncobra\ncobweb\ncoca\ncocaine\ncoccidiosis\ncochineal\ncochlea\nCochran\nCochrane\ncock\ncockatoo\ncockcrow\ncockeye\ncockfight\ncockle\ncocklebur\ncockleshell\ncockpit\ncockroach\ncocksure\ncocktail\ncocky\ncoco\ncocoa\ncoconut\ncocoon\ncod\ncoda\nCoddington\ncoddle\ncode\ncodebreak\ncodeposit\ncodetermine\ncodeword\ncodex\ncodfish\ncodicil\ncodify\ncodomain\ncodon\ncodpiece\nCody\ncoed\ncoeditor\ncoeducation\ncoefficient\ncoequal\ncoerce\ncoercible\ncoercion\ncoercive\ncoevolution\ncoexist\ncoexistent\ncoextensive\ncofactor\ncoffee\ncoffeecup\ncoffeepot\ncoffer\nCoffey\ncoffin\nCoffman\ncog\ncogent\ncogitate\ncognac\ncognate\ncognition\ncognitive\ncognoscenti\nCohen\ncohere\ncoherent\ncohesion\ncohesive\nCohn\ncohomology\ncohort\ncohosh\ncoiffure\ncoil\ncoin\ncoinage\ncoincide\ncoincident\ncoincidental\ncoke\ncol\ncola\ncolander\ncolatitude\nColby\ncold\ncoldhearted\nCole\nColeman\nColeridge\nColette\ncoleus\nColgate\ncolic\ncolicky\ncoliform\ncoliseum\ncollaborate\ncollage\ncollagen\ncollapse\ncollapsible\ncollar\ncollarbone\ncollard\ncollate\ncollateral\ncolleague\ncollect\ncollectible\ncollector\ncollege\ncollegian\ncollegiate\ncollet\ncollide\ncollie\nCollier\ncollimate\ncollinear\nCollins\ncollision\ncollocate\ncolloidal\nColloq\ncolloquia\ncolloquial\ncolloquium\ncolloquy\ncollude\ncollusion\ncologne\nColombia\nColombo\ncolon\ncolonel\ncolonial\ncolonist\ncolonnade\ncolony\nColorado\ncolorate\ncoloratura\ncolorimeter\ncolossal\nColosseum\ncolossi\ncolossus\ncolt\ncoltish\ncoltsfoot\nColumbia\ncolumbine\nColumbus\ncolumn\ncolumnar\ncolza\ncoma\nComanche\ncomatose\ncomb\ncombat\ncombatant\ncombatted\ncombinate\ncombinatorial\ncombinatoric\ncombine\ncombustible\ncombustion\ncome\ncomeback\ncomedian\ncomedy\ncomestible\ncomet\ncometary\ncometh\ncomfort\ncomic\nCominform\ncomma\ncommand\ncommandant\ncommandeer\ncommando\ncommemorate\ncommend\ncommendation\ncommendatory\ncommensal\ncommensurable\ncommensurate\ncomment\ncommentary\ncommentator\ncommerce\ncommercial\ncommingle\ncommiserate\ncommissariat\ncommissary\ncommission\ncommit\ncommittable\ncommittal\ncommitted\ncommittee\ncommitteeman\ncommitteemen\ncommitteewoman\ncommitteewomen\ncommitting\ncommodious\ncommodity\ncommodore\ncommon\ncommonality\ncommonplace\ncommonweal\ncommonwealth\ncommotion\ncommunal\ncommune\ncommunicable\ncommunicant\ncommunicate\ncommunion\ncommunique\ncommutate\ncommute\ncompact\ncompactify\nCompagnie\ncompanion\ncompanionway\ncompany\ncomparative\ncomparator\ncompare\ncomparison\ncompartment\ncompass\ncompassion\ncompassionate\ncompatible\ncompatriot\ncompel\ncompellable\ncompelled\ncompelling\ncompendia\ncompendium\ncompensable\ncompensate\ncompensatory\ncompete\ncompetent\ncompetition\ncompetitive\ncompetitor\ncompilation\ncompile\ncomplacent\ncomplain\ncomplainant\ncomplaint\ncomplaisant\ncomplement\ncomplementarity\ncomplementary\ncomplementation\ncomplete\ncompletion\ncomplex\ncomplexion\ncompliant\ncomplicate\ncomplicity\ncompliment\ncomplimentary\ncompline\ncomply\ncomponent\ncomponentry\ncomport\ncompose\ncomposite\ncomposition\ncompositor\ncompost\ncomposure\ncompote\ncompound\ncomprehend\ncomprehensible\ncomprehension\ncomprehensive\ncompress\ncompressible\ncompression\ncompressive\ncompressor\ncomprise\ncompromise\nCompton\ncomptroller\ncompulsion\ncompulsive\ncompulsory\ncompunction\ncomputation\ncompute\ncomrade\ncon\nConakry\nConant\nconcatenate\nconcave\nconceal\nconcede\nconceit\nconceive\nconcentrate\nconcentric\nconcept\nconception\nconceptual\nconcern\nconcert\nconcerti\nconcertina\nconcertmaster\nconcerto\nconcession\nconcessionaire\nconch\nconcierge\nconciliate\nconciliatory\nconcise\nconcision\nconclave\nconclude\nconclusion\nconclusive\nconcoct\nconcomitant\nconcord\nconcordant\nconcourse\nconcrete\nconcretion\nconcubine\nconcur\nconcurred\nconcurrent\nconcurring\nconcussion\ncondemn\ncondemnate\ncondemnatory\ncondensate\ncondense\ncondensible\ncondescend\ncondescension\ncondiment\ncondition\ncondolence\ncondominium\ncondone\nconduce\nconducive\nconduct\nconductance\nconductor\nconduit\ncone\nconeflower\nConestoga\nconey\nconfabulate\nconfect\nconfectionery\nconfederacy\nconfederate\nconfer\nconferee\nconference\nconferrable\nconferred\nconferring\nconfess\nconfession\nconfessor\nconfidant\nconfidante\nconfide\nconfident\nconfidential\nconfiguration\nconfigure\nconfine\nconfirm\nconfirmation\nconfirmatory\nconfiscable\nconfiscate\nconfiscatory\nconflagrate\nconflict\nconfluent\nconfocal\nconform\nconformal\nconformance\nconformation\nconfound\nconfrere\nconfront\nconfrontation\nConfucian\nConfucius\nconfuse\nconfusion\nconfute\ncongeal\ncongener\ncongenial\ncongenital\ncongest\ncongestion\ncongestive\nconglomerate\nCongo\nCongolese\ncongratulate\ncongratulatory\ncongregate\ncongress\ncongressional\ncongressman\ncongressmen\ncongresswoman\ncongresswomen\ncongruent\nconic\nconifer\nconiferous\nconjectural\nconjecture\nconjoin\nconjoint\nconjugacy\nconjugal\nconjugate\nconjunct\nconjuncture\nconjure\nConklin\nConley\nconn\nConnally\nconnect\nConnecticut\nconnector\nConner\nConnie\nconnivance\nconnive\nconnoisseur\nConnors\nconnotation\nconnotative\nconnote\nconnubial\nconquer\nconqueror\nconquest\nconquistador\nConrad\nConrail\nconsanguine\nconsanguineous\nconscience\nconscientious\nconscionable\nconscious\nconscript\nconscription\nconsecrate\nconsecutive\nconsensus\nconsent\nconsequent\nconsequential\nconservation\nconservatism\nconservative\nconservator\nconservatory\nconserve\nconsider\nconsiderate\nconsign\nconsignee\nconsignor\nconsist\nconsistent\nconsolation\nconsole\nconsolidate\nconsonant\nconsonantal\nconsort\nconsortium\nconspecific\nconspicuous\nconspiracy\nconspirator\nconspiratorial\nconspire\nconstant\nConstantine\nConstantinople\nconstellate\nconsternate\nconstipate\nconstituent\nconstitute\nconstitution\nconstitutive\nconstrain\nconstraint\nconstrict\nconstrictor\nconstrual\nconstruct\nconstructible\nconstructor\nconstrue\nconsul\nconsular\nconsulate\nconsult\nconsultant\nconsultation\nconsultative\nconsume\nconsummate\nconsumption\nconsumptive\ncontact\ncontagion\ncontagious\ncontain\ncontaminant\ncontaminate\ncontemplate\ncontemporaneous\ncontemporary\ncontempt\ncontemptible\ncontemptuous\ncontend\ncontent\ncontention\ncontentious\ncontest\ncontestant\ncontext\ncontextual\ncontiguity\ncontiguous\ncontinent\ncontinental\ncontingent\ncontinua\ncontinual\ncontinuant\ncontinuation\ncontinue\ncontinuity\ncontinuo\ncontinuous\ncontinuum\ncontort\ncontour\ncontraband\ncontrabass\ncontraception\ncontraceptive\ncontract\ncontractor\ncontractual\ncontradict\ncontradictory\ncontradistinct\ncontradistinguish\ncontraindicate\ncontralateral\ncontralto\ncontrapositive\ncontraption\ncontrariety\ncontrary\ncontrast\ncontravariant\ncontravene\ncontravention\ncontretemps\ncontribute\ncontribution\ncontributor\ncontributory\ncontrite\ncontrition\ncontrivance\ncontrive\ncontrol\ncontrollable\ncontrolled\ncontroller\ncontrolling\ncontroversial\ncontroversy\ncontrovertible\ncontumacy\ncontusion\nconundrum\nConvair\nconvalesce\nconvalescent\nconvect\nconvene\nconvenient\nconvent\nconvention\nconverge\nconvergent\nconversant\nconversation\nconverse\nconversion\nconvert\nconvertible\nconvex\nconvey\nconveyance\nconveyor\nconvict\nconvince\nconvivial\nconvocate\nconvoke\nconvolute\nconvolution\nconvolve\nconvoy\nconvulse\nconvulsion\nconvulsive\nConway\ncony\ncoo\ncook\ncookbook\nCooke\ncookery\ncookie\ncooky\ncool\ncoolant\nCooley\ncoolheaded\nCoolidge\ncoon\ncoop\ncooperate\ncoordinate\nCoors\ncoot\ncop\ncope\nCopeland\nCopenhagen\nCopernican\nCopernicus\ncopious\ncoplanar\ncopolymer\ncopperas\nCopperfield\ncopperhead\ncoppery\ncopra\ncoprinus\ncoprocessor\ncoproduct\ncopter\ncopulate\ncopy\ncopybook\ncopyright\ncopywriter\ncoquette\ncoquina\ncoral\ncoralberry\ncoralline\ncorbel\nCorbett\nCorcoran\ncord\ncordage\ncordial\ncordite\ncordon\ncorduroy\ncore\nCorey\ncoriander\nCorinth\nCorinthian\nCoriolanus\ncork\ncorkscrew\ncormorant\ncorn\ncornbread\ncornea\nCornelia\nCornelius\nCornell\ncornerstone\ncornet\ncornfield\ncornflower\ncornish\ncornmeal\ncornstarch\ncornucopia\nCornwall\ncorny\ncorolla\ncorollary\ncorona\nCoronado\ncoronary\ncoronate\ncoroner\ncoronet\ncoroutine\nCorp\ncorpora\ncorporal\ncorporate\ncorporeal\ncorps\ncorpse\ncorpsman\ncorpsmen\ncorpulent\ncorpus\ncorpuscle\ncorpuscular\ncorral\ncorralled\ncorrect\ncorrector\ncorrelate\ncorrespond\ncorrespondent\ncorridor\ncorrigenda\ncorrigendum\ncorrigible\ncorroborate\ncorroboree\ncorrode\ncorrodible\ncorrosion\ncorrosive\ncorrugate\ncorrupt\ncorruptible\ncorruption\ncorsage\ncorset\nCorsica\ncortege\ncortex\nCortez\ncortical\nCortland\ncorundum\ncoruscate\nCorvallis\ncorvette\nCorvus\ncos\ncosec\ncoset\nCosgrove\ncosh\ncosine\ncosmetic\ncosmic\ncosmology\ncosmopolitan\ncosmos\ncosponsor\nCossack\ncost\nCosta\nCostello\ncostume\ncosy\ncot\ncotangent\ncoterie\ncotillion\ncotman\ncotoneaster\ncotta\ncottage\ncotton\ncottonmouth\ncottonseed\ncottontail\ncottonwood\ncottony\nCottrell\ncotty\ncotyledon\ncouch\ncougar\ncough\ncould\ncouldn't\ncoulomb\nCoulter\ncouncil\ncouncilman\ncouncilmen\ncouncilwoman\ncouncilwomen\ncounsel\ncounselor\ncount\ncountdown\ncountenance\ncounteract\ncounterargument\ncounterattack\ncounterbalance\ncounterclockwise\ncounterexample\ncounterfeit\ncounterflow\ncounterintuitive\ncounterman\ncountermand\ncountermeasure\ncountermen\ncounterpart\ncounterpoint\ncounterpoise\ncounterproductive\ncounterproposal\ncounterrevolution\ncounterrevolutionary\ncountersink\ncountersunk\ncounterthreat\ncountervail\ncounterweight\ncountrify\ncountry\ncountryman\ncountrymen\ncountryside\ncountrywide\ncounty\ncountywide\ncoup\ncoupe\ncouple\ncouplet\ncoupon\ncourage\ncourageous\ncourier\ncourse\ncourt\ncourteous\ncourtesan\ncourtesy\ncourthouse\ncourtier\nCourtney\ncourtroom\ncourtyard\ncouscous\ncousin\ncouturier\ncovalent\ncovariant\ncovariate\ncovary\ncove\ncoven\ncovenant\nCoventry\ncover\ncoverage\ncoverall\ncoverlet\ncovert\ncovet\ncovetous\ncow\nCowan\ncoward\ncowardice\ncowbell\ncowbird\ncowboy\ncowhand\ncowherd\ncowhide\ncowl\ncowlick\ncowman\ncowmen\ncoworker\ncowpea\ncowpoke\ncowpony\ncowpox\ncowpunch\ncowry\ncowslip\ncox\ncoxcomb\ncoy\ncoyly\ncoyote\ncoypu\ncozen\ncozy\nCPA\ncpu\ncrab\ncrabapple\ncrack\ncrackle\ncrackpot\ncradle\ncraft\ncraftsman\ncraftsmen\ncraftspeople\ncraftsperson\ncrafty\ncrag\ncraggy\nCraig\ncram\nCramer\ncramp\ncrampon\ncranberry\nCrandall\ncrane\nCranford\ncrania\ncranium\ncrank\ncrankcase\ncrankshaft\ncranky\ncranny\nCranston\ncrap\ncrappie\ncrash\ncrass\ncrate\ncrater\ncravat\ncrave\ncraven\ncraw\nCrawford\ncrawl\ncrawlspace\ncrayfish\ncrayon\ncraze\ncrazy\ncreak\ncreaky\ncream\ncreamery\ncreamy\ncrease\ncreate\ncreature\ncreche\ncredent\ncredential\ncredenza\ncredible\ncredit\ncreditor\ncredo\ncredulity\ncredulous\ncreed\ncreedal\ncreek\ncreekside\ncreep\ncreepy\ncremate\ncrematory\nCreole\nCreon\ncreosote\ncrepe\ncrept\ncrescendo\ncrescent\ncress\ncrest\ncrestfallen\nCrestview\nCretaceous\nCretan\nCrete\ncretin\ncretinous\ncrevice\ncrew\ncrewcut\ncrewel\ncrewman\ncrewmen\ncrib\ncribbage\ncricket\ncrime\nCrimea\ncriminal\ncrimp\ncrimson\ncringe\ncrinkle\ncrinoid\ncripple\ncrises\ncrisis\ncrisp\nCrispin\ncriss\ncrisscross\ncriteria\ncriterion\ncritic\ncritique\ncritter\ncroak\nCroatia\ncrochet\ncrock\ncrockery\nCrockett\ncrocodile\ncrocodilian\ncrocus\ncroft\nCroix\nCromwell\nCromwellian\ncrone\ncrony\ncrook\ncroon\ncrop\ncropland\ncrore\nCrosby\ncross\ncrossarm\ncrossbar\ncrossbill\ncrosscut\ncrosshatch\ncrosslink\ncrossover\ncrosspoint\ncrossroad\ncrosstalk\ncrosswalk\ncrossway\ncrosswise\ncrossword\ncrosswort\ncrotch\ncrotchety\ncrouch\ncroupier\ncrow\ncrowbait\ncrowbar\ncrowberry\ncrowd\ncrowfoot\nCrowley\ncrown\ncroydon\nCRT\ncrucial\ncrucible\ncrucifix\ncrucifixion\ncrucify\ncrud\ncruddy\ncrude\ncruel\ncruelty\nCruickshank\ncruise\ncrumb\ncrumble\ncrummy\ncrump\ncrumple\ncrunch\ncrunchy\ncrupper\ncrusade\ncrush\nCrusoe\ncrust\ncrustacean\ncrusty\ncrutch\ncrux\nCruz\ncry\ncryogenic\ncryostat\ncrypt\ncryptanalysis\ncryptanalyst\ncryptanalytic\ncryptic\ncrypto\ncryptogram\ncryptographer\ncryptography\ncrystal\ncrystalline\ncrystallite\ncrystallographer\ncrystallography\nc's\ncsnet\nCT\ncub\nCuba\ncubby\ncubbyhole\ncube\ncubic\ncubicle\ncubit\ncuckoo\ncucumber\ncud\ncuddle\ncuddly\ncudgel\ncue\ncuff\ncufflink\ncuisine\nCulbertson\nculinary\ncull\nculminate\nculpa\nculpable\nculprit\ncult\ncultivable\ncultivar\ncultivate\ncultural\nculture\nCulver\nculvert\nCumberland\ncumbersome\ncumin\nCummings\nCummins\ncumulate\ncumulus\nCunard\ncuneiform\ncunning\nCunningham\nCUNY\ncup\ncupboard\ncupful\nCupid\ncupidity\ncupric\ncuprous\ncur\ncurate\ncurb\ncurbside\ncurd\ncurdle\ncure\ncurfew\ncuria\ncurie\ncurio\ncuriosity\ncurious\ncurium\ncurl\ncurlew\ncurlicue\ncurmudgeon\nCurran\ncurrant\ncurrent\ncurricula\ncurricular\ncurriculum\ncurry\ncurse\ncursive\ncursor\ncursory\ncurt\ncurtail\ncurtain\nCurtis\ncurtsey\ncurvaceous\ncurvature\ncurve\ncurvilinear\nCushing\ncushion\nCushman\ncusp\nCuster\ncustodial\ncustodian\ncustody\ncustom\ncustomary\ncustomhouse\ncut\ncutaneous\ncutback\ncute\ncutlass\ncutler\ncutlet\ncutoff\ncutout\ncutover\ncutset\ncutthroat\ncuttlebone\ncuttlefish\ncutworm\nCuvier\nCuzco\nCyanamid\ncyanate\ncyanic\ncyanide\ncybernetic\ncycad\nCyclades\ncycle\ncyclic\ncyclist\ncyclone\ncyclopean\nCyclops\ncyclorama\ncyclotomic\ncyclotron\ncygnet\nCygnus\ncylinder\ncylindric\ncymbal\ncynic\nCynthia\ncypress\nCyprian\nCypriot\nCyprus\nCyril\nCyrillic\nCyrus\ncyst\ncysteine\ncytochemistry\ncytolysis\ncytoplasm\ncytosine\nCZ\nczar\nczarina\nCzech\nCzechoslovakia\nCzerniak\nd\ndab\ndabble\nDacca\ndachshund\ndactyl\ndactylic\ndad\nDada\ndaddy\nDade\nDaedalus\ndaemon\ndaffodil\ndaffy\ndagger\ndaguerreotype\nDahl\ndahlia\nDahomey\nDailey\nDaimler\ndainty\ndairy\nDairylea\ndairyman\ndairymen\ndais\ndaisy\nDakar\nDakota\ndal\ndale\nDaley\nDalhousie\nDallas\ndally\nDalton\nDaly\nDalzell\ndam\ndamage\nDamascus\ndamask\ndame\ndamn\ndamnation\nDamocles\nDamon\ndamp\ndampen\ndamsel\ndamselfly\nDan\nDana\nDanbury\ndance\ndandelion\ndandy\nDane\ndang\ndanger\ndangerous\ndangle\nDaniel\nDanielson\nDanish\ndank\nDanny\nDante\nDanube\nDanubian\nDanzig\nDaphne\ndapper\ndapple\nDar\ndare\nDarius\ndark\ndarken\ndarkle\nDarlene\ndarling\ndarn\nDARPA\nDarrell\nDarry\nd'art\ndart\nDartmouth\nDarwin\nDarwinian\ndash\ndashboard\ndastard\ndata\ndatabase\ndate\ndateline\ndater\nDatsun\ndatum\ndatura\ndaub\nDaugherty\ndaughter\ndaunt\ndauphin\ndauphine\nDave\ndavenport\nDavid\nDavidson\nDavies\nDavis\nDavison\ndavit\nDavy\ndawdle\ndawn\nDawson\nday\ndaybed\ndaybreak\ndaydream\ndaylight\ndaytime\nDayton\nDaytona\ndaze\ndazzle\nDC\nde\ndeacon\ndeaconess\ndeactivate\ndead\ndeaden\ndeadhead\ndeadline\ndeadlock\ndeadwood\ndeaf\ndeafen\ndeal\ndeallocate\ndealt\ndean\nDeane\nDeanna\ndear\nDearborn\ndearie\ndearth\ndeath\ndeathbed\ndeathward\ndebacle\ndebar\ndebarring\ndebase\ndebate\ndebater\ndebauch\ndebauchery\nDebbie\nDebby\ndebenture\ndebilitate\ndebility\ndebit\ndebonair\nDeborah\nDebra\ndebrief\ndebris\ndebt\ndebtor\ndebug\ndebugged\ndebugger\ndebugging\ndebunk\nDebussy\ndebut\ndebutante\nDec\ndecade\ndecadent\ndecal\ndecant\ndecapitate\ndecapod\ndecathlon\nDecatur\ndecay\nDecca\ndecease\ndecedent\ndeceit\ndeceitful\ndeceive\ndecelerate\nDecember\ndecennial\ndecent\ndeception\ndeceptive\ndecertify\ndecibel\ndecide\ndeciduous\ndecile\ndecimal\ndecimate\ndecipher\ndecision\ndecisive\ndeck\ndeclaim\ndeclamation\ndeclamatory\ndeclaration\ndeclarative\ndeclarator\ndeclaratory\ndeclare\ndeclassify\ndeclination\ndecline\ndeclivity\ndecode\ndecolletage\ndecollimate\ndecompile\ndecomposable\ndecompose\ndecomposition\ndecompress\ndecompression\ndecontrol\ndecontrolled\ndecontrolling\ndeconvolution\ndeconvolve\ndecor\ndecorate\ndecorous\ndecorticate\ndecorum\ndecouple\ndecoy\ndecrease\ndecree\ndecreeing\ndecrement\ndecry\ndecrypt\ndecryption\ndedicate\ndeduce\ndeducible\ndeduct\ndeductible\nDee\ndeed\ndeem\ndeep\ndeepen\ndeer\nDeere\ndeerskin\ndeerstalker\ndeface\ndefault\ndefeat\ndefecate\ndefect\ndefector\ndefend\ndefendant\ndefensible\ndefensive\ndefer\ndeferent\ndeferrable\ndeferred\ndeferring\ndefiant\ndeficient\ndeficit\ndefine\ndefinite\ndefinition\ndefinitive\ndeflate\ndeflater\ndeflect\ndeflector\ndefocus\ndefoliate\ndeforest\ndeforestation\ndeform\ndeformation\ndefraud\ndefray\ndefrost\ndeft\ndefunct\ndefy\ndegas\ndegassing\ndegeneracy\ndegenerate\ndegradation\ndegrade\ndegrease\ndegree\ndegum\ndegumming\ndehumidify\ndehydrate\ndeify\ndeign\nDeimos\nDeirdre\ndeity\ndeja\ndeject\nDel\nDelaney\nDelano\nDelaware\ndelay\ndelectable\ndelectate\ndelegable\ndelegate\ndelete\ndeleterious\ndeletion\nDelft\nDelhi\nDelia\ndeliberate\ndelicacy\ndelicate\ndelicatessen\ndelicious\ndelicti\ndelight\ndelightful\nDelilah\ndelimit\ndelimitation\ndelineament\ndelineate\ndelinquent\ndeliquesce\ndeliquescent\ndelirious\ndelirium\ndeliver\ndeliverance\ndelivery\ndeliveryman\ndeliverymen\ndell\nDella\nDelmarva\ndelouse\nDelphi\nDelphic\ndelphine\ndelphinium\nDelphinus\ndelta\ndeltoid\ndelude\ndeluge\ndelusion\ndelusive\ndeluxe\ndelve\ndemagnify\ndemagogue\ndemand\ndemarcate\ndemark\ndemean\ndemented\ndementia\ndemerit\nDemeter\ndemi\ndemigod\ndemijohn\ndemiscible\ndemise\ndemit\ndemitted\ndemitting\ndemocracy\ndemocrat\ndemocratic\ndemodulate\ndemographer\ndemography\ndemolish\ndemolition\ndemon\ndemoniac\ndemonic\ndemonstrable\ndemonstrate\ndemote\ndemountable\nDempsey\ndemultiplex\ndemur\ndemure\ndemurred\ndemurrer\ndemurring\ndemystify\nden\ndenature\ndendrite\ndendritic\nDeneb\nDenebola\ndeniable\ndenial\ndenigrate\ndenizen\nDenmark\nDennis\nDenny\ndenominate\ndenotation\ndenotative\ndenote\ndenouement\ndenounce\ndense\ndensitometer\ndent\ndental\ndentistry\ndentition\nDenton\ndenture\ndenudation\ndenude\ndenumerable\ndenunciate\nDenver\ndeny\ndeodorant\ndeoxyribonucleic\ndeoxyribose\ndepart\ndeparture\ndepend\ndependent\ndepict\ndeplane\ndeplete\ndepletion\ndeplore\ndeploy\ndeport\ndeportation\ndeportee\ndepose\ndeposit\ndepositary\ndeposition\ndepositor\ndepository\ndepot\ndeprave\ndeprecate\ndeprecatory\ndepreciable\ndepreciate\ndepredation\ndepress\ndepressant\ndepressible\ndepression\ndepressive\ndepressor\ndeprivation\ndeprive\ndepth\ndeputation\ndepute\ndeputy\nderail\nderange\nderate\nderby\nDerbyshire\ndereference\nderegulate\nDerek\nderelict\nderide\nderision\nderisive\nderivate\nderive\ndermatology\nderogate\nderogatory\nderrick\nderriere\ndervish\nDes\ndescant\nDescartes\ndescend\ndescendant\ndescendent\ndescent\ndescribe\ndescription\ndescriptive\ndescriptor\ndesecrate\ndesecrater\ndesegregate\ndesert\ndeserve\ndesiccant\ndesiccate\ndesiderata\ndesideratum\ndesign\ndesignate\ndesire\ndesirous\ndesist\ndesk\nDesmond\ndesolate\ndesolater\ndesorption\ndespair\ndesperado\ndesperate\ndespicable\ndespise\ndespite\ndespoil\ndespond\ndespondent\ndespot\ndespotic\ndessert\ndestinate\ndestine\ndestiny\ndestitute\ndestroy\ndestruct\ndestructor\ndesuetude\ndesultory\ndetach\ndetail\ndetain\nd'etat\ndetect\ndetector\ndetent\ndetente\ndetention\ndeter\ndetergent\ndeteriorate\ndeterminacy\ndeterminant\ndeterminate\ndetermine\ndeterred\ndeterrent\ndeterring\ndetest\ndetestation\ndetonable\ndetonate\ndetour\ndetoxify\ndetract\ndetractor\ndetriment\ndetritus\nDetroit\ndeuce\ndeus\ndeuterate\ndeuterium\ndeuteron\ndevastate\ndevelop\ndeviant\ndeviate\ndevice\ndevil\ndevilish\ndevious\ndevise\ndevisee\ndevoid\ndevolve\nDevon\nDevonshire\ndevote\ndevotee\ndevotion\ndevour\ndevout\ndew\ndewar\ndewdrop\nDewey\nDewitt\ndewy\ndexter\ndexterity\ndextrose\ndextrous\ndey\nDhabi\ndharma\ndiabase\ndiabetes\ndiabetic\ndiabolic\ndiachronic\ndiacritic\ndiadem\ndiagnosable\ndiagnose\ndiagnosis\ndiagnostic\ndiagnostician\ndiagonal\ndiagram\ndiagrammatic\ndiagrammed\ndiagramming\ndial\ndialect\ndialectic\ndialogue\ndialup\ndialysis\ndiamagnetic\ndiamagnetism\ndiameter\ndiamond\nDiana\nDiane\nDianne\ndiaper\ndiaphanous\ndiaphragm\ndiary\ndiathermy\ndiathesis\ndiatom\ndiatomaceous\ndiatomic\ndiatonic\ndiatribe\ndibble\ndice\ndichloride\ndichondra\ndichotomy\ndick\ndickcissel\ndickens\nDickerson\ndickey\nDickinson\nDickson\ndicotyledon\ndicta\ndictate\ndictatorial\ndiction\ndictionary\ndictum\ndid\ndidactic\ndiddle\ndidn't\nDido\ndie\nDiebold\nDiego\ndiehard\ndieldrin\ndielectric\ndiem\ndieresis\ndiesel\ndiet\ndietary\ndietetic\ndiethylstilbestrol\ndietician\nDietrich\ndiety\nDietz\ndiffeomorphic\ndiffeomorphism\ndiffer\ndifferent\ndifferentiable\ndifferential\ndifferentiate\ndifficult\ndifficulty\ndiffident\ndiffract\ndiffractometer\ndiffuse\ndiffusible\ndiffusion\ndiffusive\ndifluoride\ndig\ndigamma\ndigest\ndigestible\ndigestion\ndigestive\ndigging\ndigit\ndigital\ndigitalis\ndignify\ndignitary\ndignity\ndigram\ndigress\ndigression\ndihedral\ndilapidate\ndilatation\ndilate\ndilatory\ndilemma\ndilettante\ndiligent\ndill\nDillon\ndilogarithm\ndiluent\ndilute\ndilution\ndim\ndime\ndimension\ndimethyl\ndiminish\ndiminuendo\ndiminution\ndiminutive\ndimorphic\ndimorphism\ndimple\ndin\nDinah\ndine\nding\ndinghy\ndingo\ndingy\ndinnertime\ndinnerware\ndinosaur\ndint\ndiocesan\ndiocese\nDiocletian\ndiode\nDiogenes\nDionysian\nDionysus\nDiophantine\ndiopter\ndiorama\ndiorite\ndioxide\ndip\ndiphtheria\ndiphthong\ndiploid\ndiploidy\ndiploma\ndiplomacy\ndiplomat\ndiplomatic\ndipole\nDirac\ndire\ndirect\ndirector\ndirectorate\ndirectory\ndirectrices\ndirectrix\ndirge\nDirichlet\ndirt\ndirty\nDis\ndisaccharide\ndisambiguate\ndisastrous\ndisburse\ndisc\ndiscern\ndiscernible\ndisciple\ndisciplinary\ndiscipline\ndiscoid\ndiscomfit\ndiscordant\ndiscovery\ndiscreet\ndiscrepant\ndiscrete\ndiscretion\ndiscretionary\ndiscriminable\ndiscriminant\ndiscriminate\ndiscriminatory\ndiscus\ndiscuss\ndiscussant\ndiscussion\ndisdain\ndisdainful\ndisembowel\ndisgruntle\ndisgustful\ndish\ndishevel\ndishwasher\ndishwater\ndisjunct\ndisk\ndismal\ndismissal\nDisney\nDisneyland\ndisparage\ndisparate\ndispel\ndispelled\ndispelling\ndispensable\ndispensary\ndispensate\ndispense\ndispersal\ndisperse\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tic\nectoderm\nectopic\nEcuador\necumenic\necumenist\nEd\nEddie\neddy\nedelweiss\nedematous\nEden\nEdgar\nedge\nEdgerton\nedgewise\nedgy\nedible\nedict\nedifice\nedify\nEdinburgh\nEdison\nedit\nEdith\nedition\neditor\neditorial\nEdmonds\nEdmondson\nEdmonton\nEdmund\nEdna\nEDT\nEduardo\neducable\neducate\nEdward\nEdwardian\nEdwardine\nEdwin\nEdwina\neel\neelgrass\nEEOC\ne'er\neerie\neerily\nefface\neffaceable\neffect\neffectual\neffectuate\neffeminate\nefferent\neffete\nefficacious\nefficacy\nefficient\nEffie\neffloresce\nefflorescent\neffluent\neffluvia\neffluvium\neffort\neffusion\neffusive\neft\ne.g\negalitarian\nEgan\negg\negghead\neggplant\neggshell\nego\negocentric\negotism\negotist\negregious\negress\negret\nEgypt\nEgyptian\nEgyptology\neh\nEhrlich\neider\neidetic\neigenfunction\neigenspace\neigenstate\neigenvalue\neigenvector\neight\neighteen\neighteenth\neightfold\neighth\neightieth\neighty\neightyfold\nEileen\nEinstein\nEinsteinian\neinsteinium\nEire\nEisenhower\nEisner\neither\nejaculate\neject\nejector\neke\nEkstrom\nEktachrome\nel\nelaborate\nElaine\nelan\nelapse\nelastic\nelastomer\nelate\nElba\nelbow\nelder\neldest\nEldon\nEleanor\nEleazar\nelect\nelector\nelectoral\nelectorate\nElectra\nelectress\nelectret\nelectric\nelectrician\nelectrify\nelectro\nelectrocardiogram\nelectrocardiograph\nelectrode\nelectroencephalogram\nelectroencephalograph\nelectroencephalography\nelectrolysis\nelectrolyte\nelectrolytic\nelectron\nelectronic\nelectrophoresis\nelectrophorus\nelegant\nelegiac\nelegy\nelement\nelementary\nElena\nelephant\nelephantine\nelevate\neleven\nelevenfold\neleventh\nelfin\nElgin\nEli\nelicit\nelide\neligible\nElijah\neliminable\neliminate\nElinor\nEliot\nElisabeth\nElisha\nelision\nelite\nElizabeth\nElizabethan\nelk\nElkhart\nell\nElla\nEllen\nElliot\nElliott\nellipse\nellipsis\nellipsoid\nellipsoidal\nellipsometer\nelliptic\nEllis\nEllison\nEllsworth\nEllwood\nelm\nElmer\nElmhurst\nElmira\nElmsford\nEloise\nelongate\nelope\neloquent\nelse\nElsevier\nelsewhere\nElsie\nElsinore\nElton\neluate\nelucidate\nelude\nelusive\nelute\nelution\nelver\nelves\nEly\nElysee\nelysian\nem\nemaciate\nemacs\nemanate\nemancipate\nEmanuel\nemasculate\nembalm\nembank\nembarcadero\nembargo\nembargoes\nembark\nembarrass\nembassy\nembattle\nembed\nembeddable\nembedded\nembedder\nembedding\nembellish\nember\nembezzle\nembitter\nemblazon\nemblem\nemblematic\nembodiment\nembody\nembolden\nemboss\nembouchure\nembower\nembrace\nembraceable\nembrittle\nembroider\nembroidery\nembroil\nembryo\nembryology\nembryonic\nemcee\nemendable\nemerald\nemerge\nemergent\nemeriti\nemeritus\nEmerson\nEmery\nemetic\nemigrant\nemigrate\nemigre\nemigree\nEmil\nEmile\nEmilio\nEmily\neminent\nemirate\nemissary\nemission\nemissive\nemit\nemittance\nemitted\nemitter\nemitting\nemma\nEmmanuel\nEmmett\nemolument\nEmory\nemotion\nempathic\nempathy\nemperor\nemphases\nemphasis\nemphatic\nemphysema\nemphysematous\nempire\nempiric\nemplace\nemploy\nemployee\nemporium\nempower\nempress\nempty\nemptyhanded\nemulate\nemulsify\nemulsion\nen\nenamel\nencapsulate\nencephalitis\nenchantress\nenclave\nencomia\nencomium\nencore\nencroach\nencryption\nencumber\nencumbrance\nencyclopedic\nend\nendemic\nendgame\nEndicott\nendoderm\nendogamous\nendogamy\nendogenous\nendometrial\nendometriosis\nendomorphism\nendorse\nendosperm\nendothelial\nendothermic\nendow\nendpoint\nendure\nenemy\nenergetic\nenergy\nenervate\nenfant\nenforceable\nenforcible\nEng\nengage\nEngel\nengine\nengineer\nEngland\nEnglander\nEngle\nEnglewood\nEnglish\nEnglishman\nEnglishmen\nenhance\nEnid\nenigma\nenigmatic\nenjoinder\nenlargeable\nenmity\nEnoch\nenol\nenormity\nenormous\nEnos\nenough\nenquire\nenquiry\nEnrico\nenrollee\nensconce\nensemble\nenstatite\nentendre\nenter\nenterprise\nentertain\nenthalpy\nenthusiasm\nenthusiast\nenthusiastic\nentice\nentire\nentirety\nentity\nentomology\nentourage\nentranceway\nentrant\nentrepreneur\nentrepreneurial\nentropy\nentry\nenumerable\nenumerate\nenunciable\nenunciate\nenvelop\nenvelope\nenviable\nenvious\nenviron\nenvoy\nenvy\nenzymatic\nenzyme\nenzymology\nEocene\neohippus\neosine\nEPA\nepaulet\nephemeral\nephemerides\nephemeris\nEphesian\nEphesus\nEphraim\nepic\nepicure\nEpicurean\nepicycle\nepicyclic\nepidemic\nepidemiology\nepidermic\nepidermis\nepigenetic\nepigram\nepigrammatic\nepigraph\nepilepsy\nepileptic\nepilogue\nepimorphism\nEpiphany\nepiphany\nepiphyseal\nepiphysis\nepiphyte\nepiphytic\nepiscopal\nEpiscopalian\nepiscopate\nepisode\nepisodic\nepistemology\nepistle\nepistolatory\nepitaph\nepitaxial\nepitaxy\nepithelial\nepithelium\nepithet\nepitome\nepoch\nepochal\neponymous\nepoxy\nepsilon\nEpsom\nEpstein\nequable\nequal\nequanimity\nequate\nequatorial\nequestrian\nequidistant\nequilateral\nequilibrate\nequilibria\nequilibrium\nequine\nequinoctial\nequinox\nequip\nequipoise\nequipotent\nequipped\nequipping\nequitable\nequitation\nequity\nequivalent\nequivocal\nequivocate\nera\neradicable\neradicate\nerasable\nerase\nErasmus\nErastus\nerasure\nErato\nEratosthenes\nerbium\nERDA\nere\nerect\nerg\nergative\nergodic\nEric\nErich\nErickson\nEricsson\nErie\nErik\nErlenmeyer\nermine\nErnest\nErnestine\nErnie\nErnst\nerode\nerodible\nEros\nerosible\nerosion\nerosive\nerotic\nerotica\nerr\nerrand\nerrant\nerrantry\nerrata\nerratic\nerratum\nErrol\nerroneous\nerror\nersatz\nErskine\nerudite\nerudition\nerupt\neruption\nErvin\nErwin\ne's\nescadrille\nescalate\nescapade\nescape\nescapee\nescarpment\nescheat\nEscherichia\neschew\nescort\nescritoire\nescrow\nescutcheon\nEskimo\nEsmark\nesophagi\nesoteric\nespecial\nespionage\nesplanade\nEsposito\nespousal\nespouse\nesprit\nesquire\nessay\nEssen\nessence\nessential\nEssex\nEST\nestablish\nestate\nesteem\nEstella\nester\nEstes\nEsther\nestimable\nestimate\nEstonia\nestop\nestoppal\nestrange\nestrogen\nestrous\nestrus\nestuarine\nestuary\net\neta\netc\netch\neternal\neternity\nEthan\nethane\nethanol\nEthel\nether\nethereal\nethernet\nethic\nEthiopia\nethnic\nethnography\nethnology\nethnomusicology\nethology\nethos\nethyl\nethylene\netiology\netiquette\nEtruria\nEtruscan\netude\netymology\neucalyptus\nEucharist\nEuclid\nEuclidean\neucre\nEugene\nEugenia\neugenic\neuglena\neukaryote\neukaryotic\nEuler\nEulerian\neulogy\nEumenides\nEunice\neuphemism\neuphemist\neuphonious\neuphony\neuphorbia\neuphoria\neuphoric\nEuphrates\nEurasia\neureka\nEuridyce\nEuripides\nEuropa\nEurope\nEuropean\neuropium\nEurydice\neutectic\nEuterpe\neuthanasia\neutrophication\nEva\nevacuate\nevade\nevaluable\nevaluate\nevanescent\nevangel\nevangelic\nEvans\nEvanston\nEvansville\nevaporate\nevasion\nevasive\neve\nEvelyn\neven\nevenhanded\nevensong\nevent\neventful\neventide\neventual\neventuate\nEveready\nEverett\nEverglade\nevergreen\nEverhart\neverlasting\nevery\neverybody\neveryday\neveryman\neveryone\neverything\neverywhere\nevict\nevident\nevidential\nevil\nevildoer\nevince\neviscerate\nevocable\nevocate\nevoke\nevolution\nevolutionary\nevolve\nevzone\newe\nex\nexacerbate\nexact\nexactitude\nexaggerate\nexalt\nexaltation\nexam\nexamination\nexamine\nexample\nexasperate\nexasperater\nexcavate\nexceed\nexcel\nexcelled\nexcellent\nexcelling\nexcelsior\nexcept\nexception\nexcerpt\nexcess\nexcessive\nexchange\nexchangeable\nexchequer\nexcisable\nexcise\nexcision\nexcitation\nexcitatory\nexcite\nexciton\nexclaim\nexclamation\nexclamatory\nexclude\nexclusion\nexclusionary\nexclusive\nexcommunicate\nexcoriate\nexcrement\nexcrescent\nexcrete\nexcretion\nexcretory\nexcruciate\nexculpate\nexculpatory\nexcursion\nexcursus\nexcusable\nexcuse\nexec\nexecrable\nexecrate\nexecute\nexecution\nexecutive\nexecutor\nexecutrix\nexegesis\nexegete\nexemplar\nexemplary\nexemplify\nexempt\nexemption\nexercisable\nexercise\nexert\nExeter\nexfoliate\nexhale\nexhaust\nexhaustible\nexhaustion\nexhaustive\nexhibit\nexhibition\nexhibitor\nexhilarate\nexhort\nexhortation\nexhumation\nexhume\nexigent\nexile\nexist\nexistent\nexistential\nexit\nexodus\nexogamous\nexogamy\nexogenous\nexonerate\nexorbitant\nexorcise\nexorcism\nexorcist\nexoskeleta\nexoskeleton\nexothermic\nexotic\nexotica\nexpand\nexpanse\nexpansible\nexpansion\nexpansive\nexpatiate\nexpatriate\nexpect\nexpectant\nexpectation\nexpectorant\nexpectorate\nexpedient\nexpedite\nexpedition\nexpeditious\nexpel\nexpellable\nexpelled\nexpelling\nexpend\nexpenditure\nexpense\nexpensive\nexperience\nexperiential\nexperiment\nexperimentation\nexpert\nexpertise\nexpiable\nexpiate\nexpiration\nexpire\nexpiry\nexplain\nexplanation\nexplanatory\nexpletive\nexplicable\nexplicate\nexplicit\nexplode\nexploit\nexploitation\nexploration\nexploratory\nexplore\nexplosion\nexplosive\nexponent\nexponential\nexponentiate\nexport\nexportation\nexpose\nexposit\nexposition\nexpositor\nexpository\nexposure\nexpound\nexpress\nexpressible\nexpression\nexpressive\nexpressway\nexpropriate\nexpulsion\nexpunge\nexpurgate\nexquisite\nextant\nextemporaneous\nextempore\nextend\nextendible\nextensible\nextension\nextensive\nextensor\nextent\nextenuate\nexterior\nexterminate\nexternal\nextinct\nextinguish\nextirpate\nextol\nextolled\nextoller\nextolling\nextort\nextra\nextracellular\nextract\nextractor\nextracurricular\nextradite\nextradition\nextralegal\nextramarital\nextramural\nextraneous\nextraordinary\nextrapolate\nextraterrestrial\nextraterritorial\nextravagant\nextravaganza\nextrema\nextremal\nextreme\nextremum\nextricable\nextricate\nextrinsic\nextroversion\nextrovert\nextrude\nextrusion\nextrusive\nexuberant\nexudate\nexude\nexult\nexultant\nexultation\nExxon\neye\neyeball\neyebright\neyebrow\neyeful\neyeglass\neyelash\neyelet\neyelid\neyepiece\neyesight\neyesore\neyewitness\nEzekiel\nEzra\nf\nFAA\nFaber\nFabian\nfable\nfabric\nfabricate\nfabulous\nfacade\nface\nfaceplate\nfacet\nfacetious\nfacial\nfacile\nfacilitate\nfacsimile\nfact\nfactious\nfacto\nfactor\nfactorial\nfactory\nfactual\nfaculty\nfad\nfade\nfadeout\nfaery\nFafnir\nfag\nFahey\nFahrenheit\nfaience\nfail\nfailsafe\nfailsoft\nfailure\nfain\nfaint\nfair\nFairchild\nFairfax\nFairfield\nfairgoer\nFairport\nfairway\nfairy\nfaith\nfaithful\nfake\nfalcon\nfalconry\nFalkland\nfall\nfallacious\nfallacy\nfallen\nfallible\nfalloff\nFallopian\nfallout\nfallow\nFalmouth\nfalse\nfalsetto\nfalsify\nFalstaff\nfalter\nfame\nfamilial\nfamiliar\nfamilism\nfamily\nfamine\nfamish\nfamous\nfan\nfanatic\nfanciful\nfancy\nfanfare\nfanfold\nfang\nfangled\nFanny\nfanout\nfantasia\nfantasist\nfantastic\nfantasy\nfantod\nfar\nfarad\nFaraday\nFarber\nfarce\nfarcical\nfare\nfarewell\nfarfetched\nFargo\nfarina\nFarkas\nFarley\nfarm\nfarmhouse\nFarmington\nfarmland\nFarnsworth\nfaro\nFarrell\nfarsighted\nfarther\nfarthest\nfascicle\nfasciculate\nfascinate\nfascism\nfascist\nfashion\nfast\nfasten\nfastidious\nfat\nfatal\nfate\nfateful\nfather\nfathom\nfatigue\nFatima\nfatten\nfatty\nfatuous\nfaucet\nFaulkner\nfault\nfaulty\nfaun\nfauna\nfaunal\nFaust\nFaustian\nFaustus\nfawn\nfay\nFayette\nFayetteville\nfaze\nFBI\nFCC\nFDA\nFe\nfealty\nfear\nfearful\nfearsome\nfeasible\nfeast\nfeat\nfeather\nfeatherbed\nfeatherbedding\nfeatherbrain\nfeathertop\nfeatherweight\nfeathery\nfeature\nFeb\nfebrile\nFebruary\nfecal\nfeces\nfeckless\nfecund\nfed\nfederal\nfederate\nFedora\nfee\nfeeble\nfeed\nfeedback\nfeel\nFeeney\nfeet\nfeign\nfeint\nfeisty\nFeldman\nfeldspar\nFelice\nFelicia\nfelicitous\nfelicity\nfeline\nFelix\nfell\nfellow\nfelon\nfelonious\nfelony\nfelsite\nfelt\nfemale\nfeminine\nfeminism\nfeminist\nfemoral\nfemur\nfence\nfencepost\nfend\nfennec\nfennel\nFenton\nfenugreek\nFerber\nFerdinand\nFerguson\nFermat\nferment\nfermentation\nFermi\nfermion\nfermium\nfern\nFernando\nfernery\nferocious\nferocity\nFerreira\nFerrer\nferret\nferric\nferris\nferrite\nferroelectric\nferromagnet\nferromagnetic\nferrous\nferruginous\nferrule\nferry\nfertile\nfervent\nfervid\nfescue\nfest\nfestival\nfestive\nfestoon\nfetal\nfetch\nfete\nfetid\nfetish\nfetter\nfettle\nfetus\nfeud\nfeudal\nfeudatory\nfever\nfeverish\nfew\nfiance\nfiancee\nfiasco\nfiat\nfib\nfiberboard\nFiberglas\nFibonacci\nfibration\nfibrin\nfibrosis\nfibrous\nfiche\nfickle\nfiction\nfictitious\nfictive\nfiddle\nfiddlehead\nfiddlestick\nfide\nfidelity\nfidget\nfiducial\nfief\nfiefdom\nfield\nfieldstone\nfieldwork\nfiend\nfiendish\nfierce\nfiery\nfiesta\nfife\nFIFO\nfifteen\nfifteenth\nfifth\nfiftieth\nfifty\nfiftyfold\nfig\nfigaro\nfight\nfigural\nfigurate\nfigure\nfigurine\nFiji\nFijian\nfilament\nfilamentary\nfilamentous\nfilbert\nfilch\nfile\nfilet\nfilial\nfilibuster\nfiligree\nFilipino\nfill\nfillet\nfillip\nfilly\nfilm\nfilmdom\nfilmmake\nfilmstrip\nfilmy\nfilter\nfilth\nfilthy\nfiltrate\nfin\nfinal\nfinale\nfinance\nfinancial\nfinancier\nfinch\nfind\nfine\nfinery\nfinesse\nfinessing\nfinger\nfingerling\nfingernail\nfingerprint\nfingertip\nfinial\nfinicky\nfinish\nfinite\nfinitude\nfink\nFinland\nFinley\nFinn\nFinnegan\nFinnish\nfinny\nfir\nfire\nfirearm\nfireboat\nfirebreak\nfirebug\nfirecracker\nfirefly\nfirehouse\nfirelight\nfireman\nfiremen\nfireplace\nfirepower\nfireproof\nfireside\nFirestone\nfirewall\nfirewood\nfirework\nfirm\nfirmware\nfirst\nfirsthand\nfiscal\nFischbein\nFischer\nfish\nfisherman\nfishermen\nfishery\nfishmonger\nfishpond\nfishy\nFisk\nFiske\nfissile\nfission\nfissure\nfist\nfisticuff\nfit\nFitch\nFitchburg\nfitful\nFitzgerald\nFitzpatrick\nFitzroy\nfive\nfivefold\nfix\nfixate\nfixture\nFizeau\nfizzle\nfjord\nFL\nflabbergast\nflack\nflag\nflagellate\nflageolet\nflagging\nFlagler\nflagpole\nflagrant\nFlagstaff\nflagstone\nflail\nflair\nflak\nflake\nflaky\nflam\nflamboyant\nflame\nflamingo\nflammable\nflan\nFlanagan\nFlanders\nflange\nflank\nflannel\nflap\nflare\nflash\nflashback\nflashlight\nflashy\nflask\nflat\nflatbed\nflathead\nflatiron\nflatland\nflatten\nflattery\nflatulent\nflatus\nflatworm\nflaunt\nflautist\nflaw\nflax\nflaxen\nflaxseed\nflea\nfleabane\nfleawort\nfleck\nfled\nfledge\nfledgling\nflee\nfleece\nfleeing\nfleet\nFleming\nflemish\nflesh\nfleshy\nfletch\nFletcher\nflew\nflex\nflexible\nflexural\nflexure\nflick\nflight\nflimsy\nflinch\nfling\nflint\nflintlock\nflinty\nflip\nflipflop\nflippant\nflirt\nflirtation\nflirtatious\nflit\nFlo\nfloat\nfloc\nflocculate\nflock\nfloe\nflog\nflogging\nflood\nfloodgate\nfloodlight\nfloodlit\nfloodwater\nfloor\nfloorboard\nflop\nfloppy\nflora\nfloral\nFlorence\nFlorentine\nflorican\nflorid\nFlorida\nFloridian\nflorin\nflorist\nfloruit\nflotation\nflotilla\nflounce\nflounder\nflour\nflourish\nfloury\nflout\nflow\nflowchart\nflowerpot\nflowery\nflown\nFloyd\nflu\nflub\nfluctuate\nflue\nfluent\nfluff\nfluffy\nfluid\nfluke\nflung\nflunk\nflunky\nfluoresce\nfluorescein\nfluorescent\nfluoridate\nfluoride\nfluorine\nfluorite\nfluorocarbon\nfluorspar\nflurry\nflush\nfluster\nflute\nflutter\nflux\nfly\nflycatcher\nflyer\nFlynn\nflyway\nFM\nFMC\nfoal\nfoam\nfoamflower\nfoamy\nfob\nfocal\nfoci\nfocus\nfocussed\nfodder\nfoe\nfog\nFogarty\nfogging\nfoggy\nfogy\nfoible\nfoil\nfoist\nfold\nfoldout\nFoley\nfoliage\nfoliate\nfolic\nfolio\nfolk\nfolklore\nfolksinger\nfolksinging\nfolksong\nfolksy\nfolktale\nfollicle\nfollicular\nfollow\nfolloweth\nfolly\nFomalhaut\nfoment\nfond\nfondle\nfont\nFontaine\nFontainebleau\nfood\nfoodstuff\nfool\nfoolhardy\nfoolish\nfoolproof\nfoolscap\nfoot\nfootage\nfootball\nfootbridge\nFoote\nfootfall\nfoothill\nfoothold\nfootman\nfootmen\nfootnote\nfootpad\nfootpath\nfootprint\nfootstep\nfootstool\nfootwear\nfootwork\nfop\nfoppish\nfor\nforage\nforaminifera\nforay\nforbade\nforbear\nforbearance\nForbes\nforbid\nforbidden\nforbidding\nforbore\nforborne\nforce\nforceful\nforcible\nford\nFordham\nfore\nforeign\nforensic\nforest\nforestry\nforever\nforfeit\nforfeiture\nforfend\nforgather\nforgave\nforge\nforgery\nforget\nforgetful\nforgettable\nforgetting\nforgive\nforgiven\nforgo\nforgone\nforgot\nforgotten\nfork\nforklift\nforlorn\nform\nformal\nformaldehyde\nformant\nformat\nformate\nformatted\nformatting\nformic\nFormica\nformidable\nFormosa\nformula\nformulae\nformulaic\nformulate\nforsake\nforsaken\nforsook\nforswear\nforswore\nforsworn\nForsythe\nfort\nforte\nFortescue\nforth\nforthcome\nforthcoming\nforthright\nforthwith\nfortieth\nfortify\nfortin\nfortiori\nfortitude\nfortnight\nfortran\nfortress\nfortuitous\nfortunate\nfortune\nforty\nfortyfold\nforum\nforward\nforwent\nFoss\nfossil\nfossiliferous\nfoster\nfosterite\nfought\nfoul\nfoulmouth\nfound\nfoundation\nfoundling\nfoundry\nfount\nfountain\nfountainhead\nfour\nfourfold\nFourier\nfoursome\nfoursquare\nfourteen\nfourteenth\nfourth\nfovea\nfowl\nfox\nfoxglove\nFoxhall\nfoxhole\nfoxhound\nfoxtail\nfoxtrot\nfoxy\nfoyer\nFPC\nfractal\nfraction\nfractionate\nfractious\nfracture\nfragile\nfragment\nfragmentary\nfragmentation\nfragrant\nfrail\nfrailty\nframbesia\nframe\nframework\nFran\nfranc\nfranca\nFrance\nFrances\nfranchise\nFrancine\nFrancis\nFranciscan\nFrancisco\nfrancium\nfranco\nFrancoise\nfrangipani\nfrank\nFrankel\nFrankfort\nFrankfurt\nfrankfurter\nfranklin\nfrantic\nFranz\nFraser\nfraternal\nfraternity\nFrau\nfraud\nfraudulent\nfraught\nfray\nFrazier\nfrazzle\nfreak\nfreakish\nfreckle\nFred\nFreddie\nFreddy\nFrederic\nFrederick\nFredericksburg\nFredericton\nFredholm\nFredrickson\nfree\nfreeboot\nfreedman\nfreedmen\nfreedom\nfreehand\nfreehold\nfreeing\nfreeload\nfreeman\nfreemen\nFreeport\nfreestone\nfreethink\nFreetown\nfreeway\nfreewheel\nfreeze\nfreight\nFrench\nFrenchman\nFrenchmen\nfrenetic\nfrenzy\nfreon\nfrequent\nfresco\nfrescoes\nfresh\nfreshen\nfreshman\nfreshmen\nfreshwater\nFresnel\nFresno\nfret\nFreud\nFreudian\nFrey\nFreya\nfriable\nfriar\nfricative\nFrick\nfriction\nFriday\nfridge\nFriedman\nFriedrich\nfriend\nFriesland\nfrieze\nfrigate\nFrigga\nfright\nfrighten\nfrightful\nfrigid\nFrigidaire\nfrill\nfrilly\nfringe\nFrisian\nfrisky\nfritillary\nfritter\nFritz\nfrivolity\nfrivolous\nfrizzle\nfrizzy\nfro\nfrock\nfrog\nfrolic\nfrolicked\nfrolicking\nfrom\nfrond\nfront\nfrontage\nfrontal\nfrontier\nfrontiersman\nfrontiersmen\nfrost\nfrostbite\nfrostbitten\nfrosty\nfroth\nfrothy\nfrown\nfrowzy\nfroze\nfrozen\nfructose\nFruehauf\nfrugal\nfruit\nfruitful\nfruition\nfrustrate\nfrustrater\nfrustum\nfry\nFrye\nf's\nFt\nFTC\nFuchs\nFuchsia\nfudge\nfuel\nfugal\nfugitive\nfugue\nFuji\nFujitsu\nFulbright\nfulcrum\nfulfill\nfull\nfullback\nFullerton\nfully\nfulminate\nfulsome\nFulton\nfum\nfumarole\nfumble\nfume\nfumigant\nfumigate\nfun\nfunction\nfunctionary\nfunctor\nfunctorial\nfund\nfundamental\nfundraiser\nfundraising\nfuneral\nfunerary\nfunereal\nfungal\nfungi\nfungible\nfungicide\nfungoid\nfungus\nfunk\nfunky\nfunnel\nfunny\nfur\nfurbish\nfurious\nfurl\nfurlong\nfurlough\nFurman\nfurnace\nfurnish\nfurniture\nfurrier\nfurrow\nfurry\nfurther\nfurthermore\nfurthermost\nfurthest\nfurtive\nfury\nfurze\nfuse\nfuselage\nfusible\nfusiform\nfusillade\nfusion\nfuss\nfussy\nfusty\nfutile\nfuture\nfuzz\nfuzzy\ng\nGA\ngab\ngabardine\ngabble\ngabbro\nGaberones\ngable\nGabon\nGabriel\nGabrielle\ngad\ngadfly\ngadget\ngadgetry\ngadolinium\ngadwall\nGaelic\ngaff\ngaffe\ngag\ngage\ngagging\ngaggle\ngagwriter\ngaiety\nGail\ngaillardia\ngain\nGaines\nGainesville\ngainful\ngait\nGaithersburg\ngal\ngala\ngalactic\ngalactose\nGalapagos\nGalatea\nGalatia\ngalaxy\nGalbreath\ngale\nGalen\ngalena\ngalenite\nGalilean\nGalilee\nGalileo\ngall\nGallagher\ngallant\ngallantry\ngallberry\ngallery\ngalley\ngallinule\ngallium\ngallivant\ngallon\ngallonage\ngallop\nGalloway\ngallows\ngallstone\nGallup\ngallus\nGalois\nGalt\ngalvanic\ngalvanism\ngalvanometer\nGalveston\nGalway\ngam\nGambia\ngambit\ngamble\ngambol\ngame\ngamecock\ngamesmanship\ngamete\ngamin\ngamma\ngamut\ngander\nGandhi\nGandhian\ngang\nGanges\ngangland\ngangling\nganglion\ngangplank\ngangster\ngangway\ngannet\nGannett\ngantlet\ngantry\nGanymede\nGAO\ngap\ngape\ngar\ngarage\ngarb\ngarbage\ngarble\nGarcia\ngarden\ngardenia\nGardner\nGarfield\ngargantuan\ngargle\nGaribaldi\ngarish\ngarland\ngarlic\ngarner\ngarnet\ngarnish\nGarrett\ngarrison\nGarrisonian\ngarrulous\nGarry\ngarter\nGarth\nGarvey\nGary\ngas\nGascony\ngaseous\ngases\ngash\ngasify\ngasket\ngaslight\ngasoline\ngasp\nGaspee\ngassy\nGaston\ngastrointestinal\ngastronome\ngastronomic\ngastronomy\ngate\ngatekeeper\nGates\ngateway\ngather\nGatlinburg\ngator\ngauche\ngaucherie\ngaudy\ngauge\ngaugeable\nGauguin\nGaul\ngauleiter\nGaulle\ngaunt\ngauntlet\ngaur\ngauss\nGaussian\nGautama\ngauze\ngauzy\ngave\ngavel\nGavin\ngavotte\ngawk\ngawky\ngay\nGaylord\ngaze\ngazebo\ngazelle\ngazette\ngazpacho\nGE\ngear\ngecko\ngee\ngeese\nGegenschein\nGeiger\nGeigy\ngeisha\ngel\ngelable\ngelatin\ngelatine\ngelatinous\ngeld\ngem\ngeminate\nGemini\nGeminid\nGemma\ngemsbok\ngemstone\ngender\ngene\ngenealogy\ngenera\ngeneral\ngenerate\ngeneric\ngenerosity\ngenerous\nGenesco\ngenesis\ngenetic\nGeneva\nGenevieve\ngenial\ngenie\ngenii\ngenital\ngenitive\ngenius\nGenoa\ngenotype\ngenre\ngent\ngenteel\ngentian\ngentile\ngentle\ngentleman\ngentlemen\ngentlewoman\ngentlewomen\ngentry\ngenuflect\ngenuine\ngenus\ngeocentric\ngeochemical\ngeochemistry\ngeochronology\ngeode\ngeodesic\ngeodesy\ngeodetic\ngeoduck\nGeoffrey\ngeographer\ngeography\ngeology\ngeometer\ngeometrician\ngeophysical\ngeophysics\ngeopolitic\nGeorge\nGeorgetown\nGeorgia\ngeothermal\nGerald\nGeraldine\ngeranium\nGerard\nGerber\ngerbil\nGerhard\nGerhardt\ngeriatric\ngerm\nGerman\ngermane\nGermanic\ngermanium\nGermantown\nGermany\ngermicidal\ngermicide\ngerminal\ngerminate\nGerry\nGershwin\nGertrude\ngerund\ngerundial\ngerundive\ngestalt\nGestapo\ngestation\ngesticulate\ngestural\ngesture\nget\ngetaway\nGetty\nGettysburg\ngeyser\nGhana\nGhanian\nghastly\nGhent\ngherkin\nghetto\nghost\nghoul\nghoulish\nGiacomo\ngiant\ngiantess\ngibberellin\ngibberish\ngibbet\ngibbon\ngibbous\nGibbs\ngibby\ngibe\ngiblet\nGibraltar\nGibson\ngiddap\ngiddy\nGideon\nGifford\ngift\ngig\ngigacycle\ngigahertz\ngigantic\ngigavolt\ngigawatt\ngigging\ngiggle\nGil\ngila\ngilbert\nGilbertson\nGilchrist\ngild\nGilead\nGiles\ngill\nGillespie\nGillette\nGilligan\nGilmore\ngilt\ngimbal\nGimbel\ngimlet\ngimpy\ngin\nGina\nginger\ngingham\nginkgo\nginmill\nGinn\nGino\nGinsberg\nGinsburg\nginseng\nGiovanni\ngiraffe\ngird\ngirdle\ngirl\ngirlie\ngirlish\ngirt\ngirth\ngist\nGiuliano\nGiuseppe\ngive\ngiveaway\ngiven\ngiveth\ngizmo\ngizzard\ngjetost\nglacial\nglaciate\nglacier\nglacis\nglad\ngladden\ngladdy\nglade\ngladiator\ngladiolus\nGladstone\nGladys\nglamor\nglamorous\nglamour\nglance\ngland\nglandular\nglans\nglare\nGlasgow\nglass\nglassine\nglassware\nglasswort\nglassy\nGlaswegian\nglaucoma\nglaucous\nglaze\ngleam\nglean\nGleason\nglee\ngleeful\nglen\nGlenda\nGlendale\nGlenn\nglib\nglibly\nGlidden\nglide\nglimmer\nglimpse\nglint\nglissade\nglisten\nglitch\nglitter\ngloat\nglob\nglobal\nglobe\nglobular\nglobule\nglobulin\nglom\nglomerular\ngloom\ngloomy\nGloria\nGloriana\nglorify\nglorious\nglory\ngloss\nglossary\nglossolalia\nglossy\nglottal\nglottis\nGloucester\nglove\nglow\nglucose\nglue\ngluey\nglum\nglut\nglutamate\nglutamic\nglutamine\ngluten\nglutinous\nglutton\ngluttonous\ngluttony\nglyceride\nglycerin\nglycerinate\nglycerine\nglycerol\nglycine\nglycogen\nglycol\nglyph\nGM\nGMT\ngnarl\ngnash\ngnat\ngnaw\ngneiss\ngnome\ngnomon\ngnomonic\ngnostic\nGNP\ngnu\ngo\nGoa\ngoad\ngoal\ngoat\ngob\ngobble\ngobbledygook\nGobi\ngoblet\ngod\nGoddard\ngoddess\ngodfather\nGodfrey\ngodhead\ngodkin\ngodmother\ngodparent\ngodsend\ngodson\nGodwin\ngodwit\ngoes\nGoethe\nGoff\ngog\ngoggle\nGogh\ngogo\ngold\nGoldberg\ngolden\ngoldeneye\ngoldenrod\ngoldenseal\ngoldfinch\ngoldfish\nGoldman\ngoldsmith\nGoldstein\nGoldstine\nGoldwater\nGoleta\ngolf\nGoliath\ngolly\ngonad\ngonadotropic\ngondola\ngone\ngong\nGonzales\nGonzalez\ngoober\ngood\ngoodbye\nGoode\nGoodman\nGoodrich\ngoodwill\nGoodwin\ngoody\nGoodyear\ngoof\ngoofy\ngoose\ngooseberry\nGOP\ngopher\nGordian\nGordon\ngore\nGoren\ngorge\ngorgeous\ngorgon\nGorham\ngorilla\nGorky\ngorse\nGorton\ngory\ngosh\ngoshawk\ngosling\ngospel\ngossamer\ngossip\ngot\nGotham\nGothic\ngotten\nGottfried\nGoucher\nGouda\ngouge\nGould\ngourd\ngourmet\ngout\ngovern\ngovernance\ngoverness\ngovernor\ngown\nGPO\ngrab\ngrace\ngraceful\ngracious\ngrackle\ngrad\ngradate\ngrade\ngradient\ngradual\ngraduate\nGrady\nGraff\ngraft\ngraham\ngrail\ngrain\ngrainy\ngrammar\ngrammarian\ngrammatic\ngramophone\ngranary\ngrand\ngrandchild\ngrandchildren\ngranddaughter\ngrandeur\ngrandfather\ngrandiloquent\ngrandiose\ngrandma\ngrandmother\ngrandnephew\ngrandniece\ngrandpa\ngrandparent\ngrandson\ngrandstand\ngranite\ngranitic\ngranny\ngranola\ngrant\ngrantee\ngrantor\ngranular\ngranulate\ngranule\nGranville\ngrape\ngrapefruit\ngrapevine\ngraph\ngrapheme\ngraphic\ngraphite\ngrapple\ngrasp\ngrass\ngrasshopper\ngrassland\ngrassy\ngrata\ngrate\ngrateful\ngrater\ngratify\ngratis\ngratitude\ngratuitous\ngratuity\ngrave\ngravel\ngraven\ngravestone\ngraveyard\ngravid\ngravitate\ngravitometer\ngraviton\ngravy\nGrayson\ngraze\ngrease\ngreasy\ngreat\ngreatcoat\ngreater\ngrebe\nGrecian\nGreece\ngreed\ngreedy\nGreek\ngreen\nGreenbelt\nGreenberg\nGreenblatt\nGreenbriar\nGreene\ngreenery\nGreenfield\ngreengrocer\ngreenhouse\ngreenish\nGreenland\nGreensboro\ngreensward\ngreenware\nGreenwich\ngreenwood\nGreer\ngreet\nGreg\ngregarious\nGregg\nGregory\ngremlin\ngrenade\nGrendel\nGrenoble\ngrep\nGresham\nGreta\nGretchen\ngrew\ngrey\ngreyhound\ngreylag\ngrid\ngriddle\ngridiron\ngridlock\ngrief\ngrievance\ngrieve\ngrievous\ngriffin\nGriffith\ngrill\ngrille\ngrillwork\ngrim\ngrimace\nGrimaldi\ngrime\nGrimm\ngrimy\ngrin\ngrind\ngrindstone\ngrip\ngripe\ngrippe\ngrisly\ngrist\ngristmill\nGriswold\ngrit\ngritty\ngrizzle\ngrizzly\ngroan\ngroat\ngrocer\ngrocery\ngroggy\ngroin\ngrommet\ngroom\ngroove\ngrope\ngrosbeak\ngross\nGrosset\nGrossman\nGrosvenor\ngrotesque\nGroton\ngrotto\ngrottoes\ngrouch\ngrouchy\nground\ngroundhog\ngroundsel\ngroundskeep\ngroundwork\ngroup\ngroupoid\ngrouse\ngrout\ngrove\ngrovel\nGrover\ngrow\ngrowl\ngrown\ngrownup\ngrowth\ngrub\ngrubby\ngrudge\ngruesome\ngruff\ngrumble\nGrumman\ngrump\ngrumpy\ngrunt\nGruyere\ngryphon\ng's\nGSA\nGU\nGuam\nguanidine\nguanine\nguano\nguarantee\nguaranteeing\nguaranty\nguard\nguardhouse\nGuardia\nguardian\nGuatemala\ngubernatorial\nGuelph\nGuenther\nguerdon\nguernsey\nguerrilla\nguess\nguesswork\nguest\nguffaw\nGuggenheim\nGuiana\nguidance\nguide\nguidebook\nguideline\nguidepost\nguignol\nguild\nguildhall\nguile\nGuilford\nguillemot\nguillotine\nguilt\nguilty\nguinea\nGuinevere\nguise\nguitar\nGujarat\nGujarati\ngulch\ngules\ngulf\ngull\nGullah\ngullet\ngullible\ngully\ngulp\ngum\ngumbo\ngumdrop\ngummy\ngumption\ngumshoe\ngun\nGunderson\ngunfight\ngunfire\ngunflint\ngunk\ngunky\ngunman\ngunmen\ngunnery\ngunny\ngunplay\ngunpoint\ngunpowder\ngunshot\ngunsling\nGunther\ngurgle\nGurkha\nguru\nGus\ngush\ngusset\ngust\nGustafson\nGustav\nGustave\nGustavus\ngusto\ngusty\ngut\nGutenberg\nGuthrie\ngutsy\nguttural\nguy\nGuyana\nguzzle\nGwen\nGwyn\ngym\ngymnasium\ngymnast\ngymnastic\ngymnosperm\ngyp\ngypsite\ngypsum\ngypsy\ngyrate\ngyrfalcon\ngyro\ngyrocompass\ngyroscope\nh\nha\nHaag\nHaas\nhabeas\nhaberdashery\nHaberman\nHabib\nhabit\nhabitant\nhabitat\nhabitation\nhabitual\nhabituate\nhacienda\nhack\nhackberry\nHackett\nhackle\nhackmatack\nhackney\nhacksaw\nhad\nHadamard\nHaddad\nhaddock\nHades\nHadley\nhadn't\nHadrian\nhadron\nhafnium\nHagen\nHager\nhaggard\nhaggis\nhaggle\nhagiography\nHagstrom\nHague\nHahn\nHaifa\nhaiku\nhail\nhailstone\nhailstorm\nHaines\nhair\nhaircut\nhairdo\nhairpin\nhairspring\nhairy\nHaiti\nHaitian\nHal\nhalcyon\nhale\nHaley\nhalf\nhalfback\nhalfhearted\nhalftone\nhalfway\nhalibut\nhalide\nHalifax\nhalite\nhall\nhallelujah\nHalley\nhallmark\nhallow\nHalloween\nhallucinate\nhallucinatory\nhallucinogen\nhallucinogenic\nhallway\nhalma\nhalo\nhalocarbon\nhalogen\nHalpern\nHalsey\nHalstead\nhalt\nhalvah\nhalve\nHalverson\nham\nHamal\nHamburg\nhamburger\nHamilton\nhamlet\nHamlin\nhammerhead\nhammock\nHammond\nhamper\nHampshire\nHampton\nhamster\nhamstrung\nHan\nHancock\nhand\nhandbag\nhandbook\nhandclasp\nhandcuff\nHandel\nhandful\nhandgun\nhandhold\nhandicap\nhandicapped\nhandicapper\nhandicapping\nhandicraft\nhandicraftsman\nhandicraftsmen\nhandiwork\nhandkerchief\nhandle\nhandleable\nhandlebar\nhandline\nhandmade\nhandmaiden\nhandout\nhandpicked\nhandprint\nhandset\nhandshake\nhandsome\nhandspike\nhandstand\nhandwaving\nhandwrite\nhandwritten\nhandy\nhandyman\nhandymen\nHaney\nHanford\nhang\nhangable\nhangar\nhangdog\nhangman\nhangmen\nhangnail\nhangout\nhangover\nhank\nHankel\nHanley\nHanlon\nHanna\nHannah\nHannibal\nHanoi\nHanover\nHanoverian\nHans\nHansel\nHansen\nhansom\nHanson\nHanukkah\nhap\nhaphazard\nhaploid\nhaploidy\nhaplology\nhappen\nhappenstance\nhappy\nHapsburg\nharangue\nharass\nHarbin\nharbinger\nHarcourt\nhard\nhardbake\nhardboard\nhardboiled\nhardbound\nhardcopy\nhardcover\nharden\nhardhat\nhardhearted\nHardin\nhardscrabble\nhardtack\nhardtop\nhardware\nhardwire\nhardwood\nhardworking\nhardy\nhare\nharebrained\nharelip\nharem\nhark\nharken\nHarlan\nHarlem\nHarley\nharm\nharmful\nHarmon\nharmonic\nharmonica\nharmonious\nharmony\nharness\nHarold\nharp\nharpoon\nharpsichord\nharpy\nHarriet\nHarriman\nHarrington\nHarris\nHarrisburg\nHarrison\nharrow\nharry\nharsh\nharshen\nhart\nHartford\nHartley\nHartman\nHarvard\nharvest\nharvestman\nHarvey\nhas\nhash\nhashish\nhasn't\nhasp\nhassle\nhast\nhaste\nhasten\nHastings\nhasty\nhat\nhatch\nhatchery\nhatchet\nhatchway\nhate\nhateful\nhater\nHatfield\nhath\nHathaway\nhatred\nHatteras\nHattie\nHattiesburg\nHaugen\nhaughty\nhaul\nhaulage\nhaunch\nhaunt\nHausa\nHausdorff\nHavana\nhave\nhaven\nhaven't\nhaversack\nHavilland\nhavoc\nhaw\nHawaii\nHawaiian\nhawk\nHawkins\nHawley\nhawthorn\nHawthorne\nhay\nHayden\nHaydn\nHayes\nhayfield\nHaynes\nhaystack\nhayward\nhazard\nhazardous\nhaze\nhazel\nhazelnut\nhazy\nhe\nhead\nheadache\nheadboard\nheadcount\nheaddress\nheadland\nheadlight\nheadline\nheadlong\nheadman\nheadmaster\nheadmen\nheadphone\nheadquarter\nheadroom\nheadset\nheadsman\nheadsmen\nheadstand\nheadstone\nheadstrong\nheadwall\nheadwater\nheadway\nheadwind\nheady\nheal\nHealey\nhealth\nhealthful\nhealthy\nHealy\nheap\nhear\nheard\nhearken\nhearsay\nhearse\nHearst\nheart\nheartbeat\nheartbreak\nhearten\nheartfelt\nhearth\nheartland\nheartrending\nheartthrob\nhearty\nheat\nheater\nheath\nheathen\nheathenish\nHeathkit\nheave\nheaven\nheavenward\nheavy\nheavyset\nheavyweight\nHebe\nhebephrenic\nHebraic\nHebrew\nHebrides\nHecate\nhecatomb\nheck\nheckle\nHeckman\nhectic\nhector\nHecuba\nhe'd\nhedge\nhedgehog\nhedonism\nhedonist\nheed\nheel\nheft\nhefty\nHegelian\nhegemony\nHeidegger\nHeidelberg\nheifer\nheigh\nheight\nheighten\nHeine\nHeinrich\nHeinz\nheir\nheiress\nHeisenberg\nheld\nHelen\nHelena\nHelene\nHelga\nhelical\nhelicopter\nheliocentric\nheliotrope\nhelium\nhelix\nhe'll\nhell\nhellbender\nhellebore\nHellenic\nHellespont\nhellfire\nhellgrammite\nhellish\nhello\nhelm\nhelmet\nHelmholtz\nhelmsman\nhelmsmen\nHelmut\nhelp\nhelpful\nhelpmate\nHelsinki\nHelvetica\nhem\nhematite\nHemingway\nhemisphere\nhemispheric\nhemlock\nhemp\nHempstead\nhen\nhenbane\nhence\nhenceforth\nhenchman\nhenchmen\nHenderson\nHendrick\nHendrickson\nhenequen\nHenley\nhenpeck\nHenri\nHenrietta\nhenry\nhepatica\nhepatitis\nHepburn\nheptane\nher\nHera\nHeraclitus\nherald\nherb\nherbarium\nHerbert\nherbicide\nherbivore\nherbivorous\nHerculean\nHercules\nherd\nherdsman\nherdsmen\nhere\nhereabout\nhereafter\nhereby\nhereditary\nheredity\nHereford\nherein\nhereinabove\nhereinafter\nhereinbelow\nhereof\nheresy\nheretic\nhereto\nheretofore\nhereunder\nhereunto\nherewith\nheritable\nheritage\nHerkimer\nHerman\nHermann\nhermaphrodite\nhermaphroditic\nhermeneutic\nHermes\nhermetic\nhermit\nhermitage\nHermite\nhermitian\nHermosa\nHernandez\nhernia\nhero\nHerodotus\nheroes\nheroic\nheroin\nheroine\nheroism\nheron\nherpes\nherpetology\nHerr\nherringbone\nHerschel\nherself\nHershel\nHershey\nhertz\nHertzog\nhesitant\nhesitate\nhesitater\nHesperus\nHess\nHesse\nHessian\nHester\nheterocyclic\nheterodyne\nheterogamous\nheterogeneity\nheterogeneous\nheterosexual\nheterostructure\nheterozygous\nHetman\nHettie\nHetty\nHeublein\nheuristic\nHeusen\nHeuser\nhew\nHewett\nHewitt\nHewlett\nhewn\nhex\nhexachloride\nhexadecimal\nhexafluoride\nhexagon\nhexagonal\nhexameter\nhexane\nhey\nheyday\nhi\nHiatt\nhiatus\nHiawatha\nhibachi\nHibbard\nhibernate\nHibernia\nhick\nHickey\nHickman\nhickory\nhid\nhidalgo\nhidden\nhide\nhideaway\nhidebound\nhideous\nhideout\nhierarchal\nhierarchic\nhierarchy\nhieratic\nhieroglyphic\nHieronymus\nhifalutin\nHiggins\nhigh\nhighball\nhighboy\nhighfalutin\nhighhanded\nhighland\nhighlight\nhighroad\nhightail\nhighway\nhighwayman\nhighwaymen\nhijack\nhike\nhilarious\nhilarity\nHilbert\nHildebrand\nhill\nhillbilly\nHillcrest\nHillel\nhillman\nhillmen\nhillock\nhillside\nhilltop\nhilly\nhilt\nHilton\nhilum\nhim\nHimalaya\nhimself\nhind\nHindi\nhindmost\nhindquarters\nhindrance\nhindsight\nHindu\nHindustan\nHines\nhinge\nHinman\nhint\nhinterland\nhip\nhippie\nhippo\nHippocrates\nHippocratic\nhippodrome\nhippopotamus\nhippy\nhipster\nHiram\nhire\nhireling\nHiroshi\nHiroshima\nHirsch\nhirsute\nhis\nHispanic\nhiss\nhistamine\nhistidine\nhistochemic\nhistochemistry\nhistogram\nhistology\nhistorian\nhistoric\nhistoriography\nhistory\nhistrionic\nhit\nHitachi\nhitch\nHitchcock\nhither\nhitherto\nHitler\nhive\nho\nhoagie\nHoagland\nhoagy\nhoar\nhoard\nhoarfrost\nhoarse\nhoax\nhob\nHobart\nHobbes\nhobble\nHobbs\nhobby\nhobbyhorse\nhobo\nHoboken\nhoc\nhock\nhockey\nhodge\nhodgepodge\nHodges\nHodgkin\nhoe\nHoff\nHoffman\nhog\nhogan\nhogging\nhoi\nHokan\nHolbrook\nHolcomb\nhold\nholden\nholdover\nholdup\nhole\nholeable\nholiday\nHolland\nhollandaise\nholler\nHollerith\nHollingsworth\nHollister\nhollow\nHolloway\nhollowware\nholly\nhollyhock\nHollywood\nHolm\nHolman\nHolmdel\nHolmes\nholmium\nholocaust\nHolocene\nhologram\nholography\nHolst\nHolstein\nholster\nholt\nHolyoke\nholystone\nHom\nhomage\nhome\nhomebound\nhomebuilder\nhomebuilding\nhomecoming\nhomeland\nhomemade\nhomemake\nhomeobox\nhomeomorph\nhomeomorphic\nhomeopath\nhomeopathic\nhomeowner\nHomeric\nhomesick\nhomespun\nhomestead\nhomeward\nhomework\nhomicidal\nhomicide\nhomily\nhominid\nhomo\nhomogenate\nhomogeneity\nhomogeneous\nhomologous\nhomologue\nhomology\nhomomorphic\nhomomorphism\nhomonym\nhomophobia\nhomosexual\nhomotopy\nhomozygous\nhomunculus\nHonda\nhondo\nHonduras\nhone\nhonest\nhonesty\nhoney\nhoneybee\nhoneycomb\nhoneydew\nhoneymoon\nhoneysuckle\nHoneywell\nhong\nhonk\nhonky\nHonolulu\nhonoraria\nhonorarium\nhonorary\nhonoree\nhonorific\nHonshu\nhooch\nhood\nhoodlum\nhoof\nhoofmark\nhoofprint\nhook\nhookup\nhookworm\nhooligan\nhoop\nhoopla\nhoosegow\nHoosier\nhoot\nHoover\nhooves\nhop\nhope\nhopeful\nHopi\nHopkins\nHopkinsian\nhopple\nhopscotch\nHorace\nHoratio\nhorde\nhorehound\nhorizon\nhorizontal\nhormonal\nhormone\nhorn\nhornbeam\nhornblende\nHornblower\nhornet\nhornmouth\nhornpipe\nhorntail\nhornwort\nhorny\nhorology\nhoroscope\nHorowitz\nhorrendous\nhorrible\nhorrid\nhorrify\nhorror\nhorse\nhorseback\nhorsedom\nhorseflesh\nhorsefly\nhorsehair\nhorseman\nhorsemen\nhorseplay\nhorsepower\nhorseshoe\nhorsetail\nhorsewoman\nhorsewomen\nhorticulture\nHorton\nHorus\nhose\nhosiery\nhospice\nhospitable\nhospital\nhost\nhostage\nhostelry\nhostess\nhostile\nhostler\nhot\nhotbed\nhotbox\nhotel\nhotelman\nhotfoot\nhothead\nhothouse\nhotrod\nHottentot\nHoudaille\nHoudini\nhough\nHoughton\nhound\nhour\nhourglass\nhouse\nhouseboat\nhousebreak\nhousebroken\nhousefly\nhousehold\nhousekeep\nhousemate\nhousewife\nhousewives\nhousework\nHouston\nhove\nhovel\nhover\nhow\nHoward\nhowdy\nHowe\nHowell\nhowever\nhowl\nhowsoever\nhowsomever\nhoy\nhoyden\nhoydenish\nHoyt\nHrothgar\nh's\nhub\nHubbard\nHubbell\nhubbub\nhubby\nhubcap\nHuber\nHubert\nhubris\nhuck\nhuckleberry\nhuckster\nhuddle\nHudson\nhue\nhuff\nHuffman\nhug\nhuge\nhugging\nHuggins\nHugh\nHughes\nHugo\nhuh\nhulk\nhull\nhullaballoo\nhullabaloo\nhum\nhuman\nhumane\nhumanitarian\nhumble\nHumboldt\nhumdrum\nhumerus\nhumid\nhumidify\nhumidistat\nhumiliate\nhumility\nHummel\nhummingbird\nhummock\nhumorous\nhump\nhumpback\nHumphrey\nhumpty\nhumus\nHun\nhunch\nhunchback\nhundred\nhundredfold\nhundredth\nhung\nHungarian\nHungary\nhungry\nhunk\nhunt\nHuntington\nHuntley\nHuntsville\nHurd\nhurdle\nhurl\nhurley\nHuron\nhurrah\nhurray\nhurricane\nhurry\nHurst\nhurt\nhurtle\nhurty\nHurwitz\nhusband\nhusbandman\nhusbandmen\nhusbandry\nhush\nhusky\nhustle\nHuston\nhut\nhutch\nHutchins\nHutchinson\nHutchison\nHuxley\nHuxtable\nhuzzah\nhyacinth\nHyades\nhyaline\nHyannis\nhybrid\nHyde\nhydra\nhydrangea\nhydrant\nhydrate\nhydraulic\nhydride\nhydro\nhydrocarbon\nhydrochemistry\nhydrochloric\nhydrochloride\nhydrocyanic\nhydrodynamic\nhydroelectric\nhydrofluoric\nhydrogen\nhydrogenate\nhydrology\nhydrolysis\nhydrometer\nhydronium\nhydrophilic\nhydrophobia\nhydrophobic\nhydrophone\nhydrosphere\nhydrostatic\nhydrothermal\nhydrous\nhydroxide\nhydroxy\nhydroxyl\nhydroxylate\nhyena\nhygiene\nhygrometer\nhygroscopic\nhying\nHyman\nhymen\nhymn\nhymnal\nhyper\nhyperbola\nhyperbolic\nhyperboloid\nhyperboloidal\nhypertensive\nhyperthermia\nhyphen\nhyphenate\nhypnosis\nhypnotic\nhypoactive\nhypochlorite\nhypochlorous\nhypocrisy\nhypocrite\nhypocritic\nhypocycloid\nhypodermic\nhypophyseal\nhypotenuse\nhypothalamic\nhypothalamus\nhypothalmus\nhypothermia\nhypotheses\nhypothesis\nhypothetic\nhypothyroid\nhypotonic\nhysterectomy\nhysteresis\nhysteria\nhysteric\nhysteron\ni\nIA\niambic\nIan\nIberia\nibex\nibid\nibis\nIBM\nIbn\nIcarus\nICC\nice\niceberg\nicebox\nicecap\niceland\nIcelandic\niceman\nichneumon\nicicle\nicky\nicon\niconoclasm\niconoclast\niconography\nicosahedra\nicosahedral\nicosahedron\nicy\nI'd\nid\nIda\nIdaho\nidea\nideal\nideate\nidempotent\nidentical\nidentify\nidentity\nideogram\nideolect\nideology\nidetic\nidiocy\nidiom\nidiomatic\nidiosyncrasy\nidiosyncratic\nidiot\nidiotic\nidle\nidly\nidol\nidolatry\nidyll\nidyllic\ni.e\nIEEE\nif\niffy\nIfni\nigloo\nigneous\nignite\nignition\nignoble\nignominious\nignominy\nignoramus\nignorant\nignore\nIgor\nii\niii\nIke\nIL\nileum\niliac\nIliad\nI'll\nill\nillegal\nillegible\nillegitimacy\nillegitimate\nillicit\nillimitable\nIllinois\nilliteracy\nilliterate\nillogic\nillume\nilluminate\nillumine\nillusion\nillusionary\nillusive\nillusory\nillustrate\nillustrious\nIlona\nIlyushin\nI'm\nimage\nimagen\nimagery\nimaginary\nimaginate\nimagine\nimbalance\nimbecile\nimbibe\nImbrium\nimbroglio\nimbrue\nimbue\nimitable\nimitate\nimmaculate\nimmanent\nimmaterial\nimmature\nimmeasurable\nimmediacy\nimmediate\nimmemorial\nimmense\nimmerse\nimmersion\nimmigrant\nimmigrate\nimminent\nimmiscible\nimmobile\nimmobility\nimmoderate\nimmodest\nimmodesty\nimmoral\nimmortal\nimmovable\nimmune\nimmunoelectrophoresis\nimmunology\nimmutable\nimp\nimpact\nimpair\nimpale\nimpalpable\nimpart\nimpartation\nimpartial\nimpassable\nimpasse\nimpassion\nimpassive\nimpatient\nimpeach\nimpeccable\nimpedance\nimpede\nimpediment\nimpel\nimpelled\nimpeller\nimpelling\nimpend\nimpenetrable\nimperate\nimperceivable\nimperceptible\nimperfect\nimperial\nimperil\nimperious\nimperishable\nimpermeable\nimpermissible\nimpersonal\nimpersonate\nimpertinent\nimperturbable\nimpervious\nimpetuous\nimpetus\nimpiety\nimpinge\nimpious\nimpish\nimplacable\nimplant\nimplantation\nimplausible\nimplement\nimplementation\nimplementer\nimplementor\nimplicant\nimplicate\nimplicit\nimplore\nimpolite\nimpolitic\nimponderable\nimport\nimportant\nimportation\nimportunate\nimportune\nimpose\nimposition\nimpossible\nimpost\nimposture\nimpotent\nimpound\nimpoverish\nimpracticable\nimpractical\nimprecate\nimprecise\nimpregnable\nimpregnate\nimpresario\nimpress\nimpressible\nimpression\nimpressive\nimprimatur\nimprint\nimprison\nimprobable\nimpromptu\nimproper\nimpropriety\nimprove\nimprovident\nimprovisate\nimprovise\nimprudent\nimpudent\nimpugn\nimpulse\nimpulsive\nimpunity\nimpure\nimputation\nimpute\nin\ninability\ninaccessible\ninaccuracy\ninaccurate\ninaction\ninactivate\ninactive\ninadequacy\ninadequate\ninadmissible\ninadvertent\ninadvisable\ninalienable\ninalterable\ninane\ninanimate\ninappeasable\ninapplicable\ninappreciable\ninapproachable\ninappropriate\ninapt\ninaptitude\ninarticulate\ninasmuch\ninattention\ninattentive\ninaudible\ninaugural\ninaugurate\ninauspicious\ninauthentic\ninboard\ninborn\ninbred\ninbreed\nInc\nInca\nincalculable\nincandescent\nincant\nincantation\nincapable\nincapacitate\nincapacity\nincarcerate\nincarnate\nincautious\nincendiary\nincense\nincentive\ninception\ninceptor\nincessant\nincest\nincestuous\ninch\ninchoate\ninchworm\nincident\nincidental\nincinerate\nincipient\nincise\nincisive\nincisor\nincite\ninclement\ninclination\nincline\ninclose\ninclude\ninclusion\ninclusive\nincognito\nincoherent\nincombustible\nincome\nincommensurable\nincommensurate\nincommunicable\nincommutable\nincomparable\nincompatible\nincompetent\nincomplete\nincompletion\nincomprehensible\nincomprehension\nincompressible\nincomputable\ninconceivable\ninconclusive\nincondensable\nincongruity\nincongruous\ninconsequential\ninconsiderable\ninconsiderate\ninconsistent\ninconsolable\ninconspicuous\ninconstant\nincontestable\nincontrollable\nincontrovertible\ninconvenient\ninconvertible\nincorporable\nincorporate\nincorrect\nincorrigible\nincorruptible\nincreasable\nincrease\nincredible\nincredulity\nincredulous\nincrement\nincriminate\nincubate\nincubi\nincubus\ninculcate\ninculpable\nincumbent\nincur\nincurred\nincurrer\nincurring\nincursion\nindebted\nindecent\nindecipherable\nindecision\nindecisive\nindecomposable\nindeed\nindefatigable\nindefensible\nindefinable\nindefinite\nindelible\nindelicate\nindemnity\nindent\nindentation\nindenture\nindependent\nindescribable\nindestructible\nindeterminable\nindeterminacy\nindeterminate\nindex\nIndia\nIndiana\nIndianapolis\nindicant\nindicate\nindices\nindict\nIndies\nindifferent\nindigene\nindigenous\nindigent\nindigestible\nindigestion\nindignant\nindignation\nindignity\nindigo\nIndira\nindirect\nindiscernible\nindiscoverable\nindiscreet\nindiscretion\nindiscriminate\nindispensable\nindispose\nindisposition\nindisputable\nindissoluble\nindistinct\nindistinguishable\nindium\nindividual\nindividuate\nindivisible\nIndo\nIndochina\nIndochinese\nindoctrinate\nIndoeuropean\nindolent\nindomitable\nIndonesia\nindoor\nindorse\nindubitable\ninduce\ninducible\ninduct\ninductance\ninductee\ninductor\nindulge\nindulgent\nIndus\nindustrial\nindustrious\nindustry\nindwell\nindy\ninebriate\ninedible\nineducable\nineffable\nineffective\nineffectual\ninefficacy\ninefficient\ninelastic\ninelegant\nineligible\nineluctable\ninept\ninequality\ninequitable\ninequity\ninequivalent\nineradicable\ninert\ninertance\ninertia\ninertial\ninescapable\ninessential\ninestimable\ninevitable\ninexact\ninexcusable\ninexhaustible\ninexorable\ninexpedient\ninexpensive\ninexperience\ninexpert\ninexpiable\ninexplainable\ninexplicable\ninexplicit\ninexpressible\ninextinguishable\ninextricable\ninfallible\ninfamous\ninfamy\ninfant\ninfanticide\ninfantile\ninfantry\ninfantryman\ninfantrymen\ninfarct\ninfatuate\ninfeasible\ninfect\ninfectious\ninfelicitous\ninfelicity\ninfer\ninference\ninferential\ninferior\ninfernal\ninferno\ninferred\ninferring\ninfertile\ninfest\ninfestation\ninfidel\ninfield\ninfighting\ninfiltrate\ninfima\ninfimum\ninfinite\ninfinitesimal\ninfinitive\ninfinitude\ninfinitum\ninfinity\ninfirm\ninfirmary\ninfix\ninflame\ninflammable\ninflammation\ninflammatory\ninflate\ninflater\ninflationary\ninflect\ninflexible\ninflict\ninflorescent\ninflow\ninfluence\ninfluent\ninfluential\ninfluenza\ninflux\ninfo\ninform\ninformal\ninformant\ninformation\ninformative\ninfra\ninfract\ninfrared\ninfrastructure\ninfrequent\ninfringe\ninfuriate\ninfuse\ninfusible\ninfusion\ninfusoria\ningather\ningenious\ningenuity\ningenuous\nIngersoll\ningest\ningestible\ningestion\ninglorious\ningot\ningrained\nIngram\ningrate\ningratiate\ningratitude\ningredient\ningrown\ninhabit\ninhabitant\ninhabitation\ninhalation\ninhale\ninharmonious\ninhere\ninherent\ninherit\ninheritance\ninheritor\ninhibit\ninhibition\ninhibitor\ninhibitory\ninholding\ninhomogeneity\ninhomogeneous\ninhospitable\ninhuman\ninhumane\ninimical\ninimitable\niniquitous\niniquity\ninitial\ninitiate\ninject\ninjudicious\nInjun\ninjunct\ninjure\ninjurious\ninjury\ninjustice\nink\ninkling\ninlaid\ninland\ninlay\ninlet\nInman\ninmate\ninn\ninnard\ninnate\ninnermost\ninnkeeper\ninnocent\ninnocuous\ninnovate\ninnuendo\ninnumerable\ninoculate\ninoperable\ninoperative\ninopportune\ninordinate\ninorganic\ninput\ninputting\ninquest\ninquire\ninquiry\ninquisition\ninquisitive\ninquisitor\ninroad\ninsane\ninsatiable\ninscribe\ninscription\ninscrutable\ninsect\ninsecticide\ninsectivore\ninsectivorous\ninsecure\ninseminate\ninsensible\ninsensitive\ninseparable\ninsert\ninset\ninshore\ninside\ninsidious\ninsight\ninsightful\ninsignia\ninsignificant\ninsincere\ninsinuate\ninsipid\ninsist\ninsistent\ninsofar\ninsolate\ninsolent\ninsoluble\ninsolvable\ninsolvent\ninsomnia\ninsomniac\ninsouciant\ninspect\ninspector\ninspiration\ninspire\ninstable\ninstall\ninstallation\ninstant\ninstantaneous\ninstantiate\ninstar\ninstead\ninstep\ninstigate\ninstill\ninstillation\ninstinct\ninstinctual\ninstitute\ninstitution\ninstruct\ninstructor\ninstrument\ninstrumentation\ninsubordinate\ninsubstantial\ninsufferable\ninsufficient\ninsular\ninsulate\ninsulin\ninsult\ninsuperable\ninsupportable\ninsuppressible\ninsurance\ninsure\ninsurgent\ninsurmountable\ninsurrect\nintact\nintake\nintangible\ninteger\nintegrable\nintegral\nintegrand\nintegrate\nintegrity\nintegument\nintellect\nintellectual\nintelligent\nintelligentsia\nintelligible\nintemperance\nintemperate\nintend\nintendant\nintense\nintensify\nintensive\nintent\nintention\ninter\nintercalate\nintercept\ninterception\ninterceptor\nintercom\ninterdict\ninterdigitate\ninterest\ninterfere\ninterference\ninterferometer\ninterferon\ninterim\ninterior\ninterject\ninterlude\nintermediary\nintermit\nintermittent\nintern\ninternal\ninternescine\nInterpol\ninterpolate\ninterpolatory\ninterpret\ninterpretation\ninterpretive\ninterregnum\ninterrogate\ninterrogatory\ninterrupt\ninterruptible\ninterruption\nintersect\nintersperse\ninterstice\ninterstitial\ninterval\nintervene\nintervenor\nintervention\ninterviewee\nintestate\nintestinal\nintestine\nintimacy\nintimal\nintimate\nintimater\nintimidate\ninto\nintolerable\nintolerant\nintonate\nintone\nintoxicant\nintoxicate\nintra\nintractable\nintransigent\nintransitive\nintrepid\nintricacy\nintricate\nintrigue\nintrinsic\nintroduce\nintroduction\nintroductory\nintroit\nintroject\nintrospect\nintroversion\nintrovert\nintrude\nintrusion\nintrusive\nintuit\nintuition\nintuitive\ninundate\ninure\ninvade\ninvalid\ninvalidate\ninvaluable\ninvariable\ninvariant\ninvasion\ninvasive\ninvective\ninveigh\ninveigle\ninvent\ninvention\ninventive\ninventor\ninventory\nInverness\ninverse\ninversion\ninvert\ninvertebrate\ninvertible\ninvest\ninvestigate\ninvestigatory\ninvestor\ninveterate\ninviable\ninvidious\ninvigorate\ninvincible\ninviolable\ninviolate\ninvisible\ninvitation\ninvite\ninvitee\ninvocable\ninvocate\ninvoice\ninvoke\ninvoluntary\ninvolute\ninvolution\ninvolutorial\ninvolve\ninvulnerable\ninward\nIo\niodate\niodide\niodinate\niodine\nion\nionic\nionosphere\nionospheric\niota\nIowa\nipecac\nipsilateral\nipso\nIQ\nIR\nIra\nIran\nIranian\nIraq\nIraqi\nirate\nire\nIreland\nIrene\niridium\niris\nIrish\nIrishman\nIrishmen\nirk\nirksome\nIrma\niron\nironbound\nironic\nironside\nironstone\nironwood\nirony\nIroquois\nirradiate\nirrational\nIrrawaddy\nirreclaimable\nirreconcilable\nirreconciliable\nirrecoverable\nirredeemable\nirredentism\nirredentist\nirreducible\nirrefutable\nirregular\nirrelevant\nirremediable\nirremovable\nirreparable\nirreplaceable\nirrepressible\nirreproachable\nirreproducible\nirresistible\nirresolute\nirresolution\nirresolvable\nirrespective\nirresponsible\nirretrievable\nirreverent\nirreversible\nirrevocable\nirrigate\nirritable\nirritant\nirritate\nirruption\nIRS\nIrvin\nIrvine\nIrving\nIrwin\ni's\nis\nIsaac\nIsaacson\nIsabel\nIsabella\nIsadore\nIsaiah\nisentropic\nIsfahan\nIsing\nisinglass\nIsis\nIslam\nIslamabad\nIslamic\nisland\nisle\nislet\nisn't\nisochronal\nisochronous\nisocline\nisolate\nIsolde\nisomer\nisomorph\nisomorphic\nisopleth\nisotherm\nisotope\nisotropy\nIsrael\nIsraeli\nIsraelite\nissuant\nissue\nIstanbul\nisthmus\nIstvan\nit\nItalian\nitalic\nItaly\nitch\nitchy\nit'd\nitem\niterate\nIthaca\nitinerant\nitinerary\nit'll\nIto\nitself\nIT&T\nITT\niv\nIvan\nIvanhoe\nI've\nIverson\nivory\nivy\nix\nIzvestia\nj\njab\nJablonsky\njack\njackal\njackanapes\njackass\njackboot\njackdaw\njacket\nJackie\njackknife\nJackman\njackpot\nJackson\nJacksonville\nJacky\nJACM\nJacob\nJacobean\nJacobi\nJacobian\nJacobite\nJacobsen\nJacobson\nJacobus\nJacqueline\nJacques\njade\nJaeger\njag\njagging\njaguar\nJaime\nJakarta\njake\njalopy\njam\nJamaica\njamboree\nJames\nJamestown\nJan\nJane\nJaneiro\nJanet\njangle\nJanice\njanissary\njanitor\njanitorial\nJanos\nJansenist\nJanuary\nJanus\nJapan\nJapanese\njar\njargon\nJarvin\nJason\njasper\njaundice\njaunty\nJava\njava\njavelin\njaw\njawbone\njay\njazz\njazzy\njealous\njealousy\njean\nJeannie\nJed\njeep\nJeff\nJefferson\nJeffrey\nJehovah\njejune\njejunum\njelly\njellyfish\nJenkins\nJennie\nJennifer\nJennings\njenny\nJensen\njeopard\njeopardy\nJeremiah\nJeremy\nJeres\nJericho\njerk\njerky\nJeroboam\nJerome\njerry\njersey\nJerusalem\njess\nJesse\nJessica\nJessie\njest\nJesuit\nJesus\njet\njetliner\njettison\nJew\njewel\nJewell\njewelry\nJewett\nJewish\njibe\njiffy\njig\njigging\njiggle\njigsaw\nJill\njilt\nJim\nJimenez\nJimmie\njimmy\njingle\njinx\njitter\njitterbug\njittery\njive\nJo\nJoan\nJoanna\nJoanne\nJoaquin\njob\njobholder\njock\njockey\njockstrap\njocose\njocular\njocund\nJoe\nJoel\njoey\njog\njogging\njoggle\nJohann\nJohanna\nJohannes\nJohannesburg\nJohansen\nJohanson\nJohn\nJohnny\nJohnsen\nJohnson\nJohnston\nJohnstown\njoin\njoint\njoke\nJoliet\nJolla\njolly\njolt\nJon\nJonas\nJonathan\nJones\njonquil\nJordan\nJorge\nJorgensen\nJorgenson\nJose\nJosef\nJoseph\nJosephine\nJosephson\nJosephus\nJoshua\nJosiah\njoss\njostle\njot\njoule\njounce\njournal\njournalese\njourney\njourneyman\njourneymen\njoust\nJovanovich\nJove\njovial\nJovian\njowl\njowly\njoy\nJoyce\njoyful\njoyous\njoyride\njoystick\nJr\nj's\nJuan\nJuanita\njubilant\njubilate\nJudaica\nJudaism\nJudas\nJudd\nJude\njudge\njudicable\njudicatory\njudicature\njudicial\njudiciary\njudicious\nJudith\njudo\nJudson\nJudy\njug\njugate\njuggernaut\njugging\njuggle\nJugoslavia\njuice\njuicy\njuju\njujube\njuke\njukebox\nJukes\njulep\nJules\nJulia\nJulie\nJuliet\nJulio\nJulius\nJuly\njumble\njumbo\njump\njumpy\njunco\njunction\njunctor\njuncture\nJune\nJuneau\nJung\nJungian\njungle\njunior\njuniper\njunk\njunkerdom\njunketeer\njunky\nJuno\njunta\nJupiter\nJura\nJurassic\njure\njuridic\njurisdiction\njurisprudent\njurisprudential\njuror\njury\njust\njustice\njusticiable\njustify\nJustine\nJustinian\njut\njute\nJutish\nJutland\njuvenile\njuxtapose\njuxtaposition\nk\nKabuki\nKabul\nKaddish\nKafka\nKafkaesque\nKahn\nkaiser\nKajar\nKalamazoo\nkale\nkaleidescope\nkaleidoscope\nkalmia\nKalmuk\nKamchatka\nkamikaze\nKampala\nKampuchea\nKane\nkangaroo\nKankakee\nKannada\nKansas\nKant\nkaolin\nkaolinite\nKaplan\nkapok\nkappa\nKarachi\nKaramazov\nkarate\nKaren\nKarl\nkarma\nKarol\nKarp\nkaryatid\nKashmir\nKaskaskia\nKate\nKatharine\nKatherine\nKathleen\nKathy\nKatie\nKatmandu\nKatowice\nkatydid\nKatz\nKauffman\nKaufman\nkava\nKay\nkayo\nkazoo\nKeaton\nKeats\nkeddah\nkeel\nkeelson\nkeen\nKeenan\nkeep\nkeeshond\nkeg\nKeith\nKeller\nKelley\nKellogg\nkelly\nkelp\nKelsey\nKelvin\nKemp\nken\nKendall\nKennan\nKennecott\nKennedy\nkennel\nKenneth\nKenney\nkeno\nKensington\nKent\nKenton\nKentucky\nKenya\nKenyon\nKepler\nkept\nkerchief\nKermit\nkern\nkernel\nKernighan\nkerosene\nKerouac\nKerr\nkerry\nkerygma\nKessler\nkestrel\nketch\nketchup\nketo\nketone\nketosis\nKettering\nkettle\nKevin\nkey\nkeyboard\nKeyes\nkeyhole\nKeynes\nKeynesian\nkeynote\nkeypunch\nkeystone\nkeyword\nkhaki\nkhan\nKhartoum\nKhmer\nKhrushchev\nkibbutzim\nkibitz\nkick\nkickback\nkickoff\nkid\nKidde\nkiddie\nkidnap\nkidnapped\nkidnapping\nkidney\nKieffer\nKiev\nKiewit\nKigali\nKikuyu\nKilgore\nKilimanjaro\nkill\nkilldeer\nkilljoy\nkilohm\nKim\nKimball\nKimberly\nkimono\nkin\nkind\nkindergarten\nkindle\nkindred\nkinematic\nkinesic\nkinetic\nking\nkingbird\nkingdom\nkingfisher\nkinglet\nkingpin\nKingsbury\nKingsley\nKingston\nkink\nkinkajou\nkinky\nKinney\nKinshasha\nkinsman\nkinsmen\nkiosk\nKiowa\nKipling\nKirby\nKirchner\nKirchoff\nkirk\nKirkland\nKirkpatrick\nKirov\nkiss\nkit\nKitakyushu\nkitchen\nkitchenette\nkite\nkitten\nkittenish\nkittle\nkitty\nkiva\nkivu\nKiwanis\nkiwi\nKlan\nKlaus\nklaxon\nkleenex\nKlein\nKline\nKlux\nklystron\nknack\nKnapp\nknapsack\nKnauer\nknead\nknee\nkneecap\nkneel\nknelt\nknew\nknick\nKnickerbocker\nknife\nknight\nKnightsbridge\nknit\nknives\nknob\nknobby\nknock\nknockdown\nknockout\nknoll\nKnossos\nknot\nKnott\nknotty\nknow\nknoweth\nknowhow\nknowledge\nknowledgeable\nKnowles\nKnowlton\nknown\nKnox\nKnoxville\nknuckle\nknuckleball\nKnudsen\nKnudson\nknurl\nKnutsen\nKnutson\nkoala\nKobayashi\nKoch\nKochab\nKodachrome\nkodak\nKodiak\nKoenig\nKoenigsberg\nkohlrabi\nkoinonia\nkola\nkolkhoz\nkombu\nKong\nKonrad\nKoppers\nKoran\nKorea\nkosher\nKovacs\nKowalewski\nKowalski\nKowloon\nkraft\nKrakatoa\nKrakow\nKramer\nKrause\nkraut\nKrebs\nKremlin\nKresge\nKrieger\nkrill\nKrishna\nKristin\nKronecker\nKrueger\nKruger\nkrummholz\nKruse\nkrypton\nKS\nk's\nKu\nkudo\nkudzu\nKuhn\nkulak\nKumar\nkumquat\nKurd\nKurt\nKuwait\nkwashiorkor\nKY\nKyle\nKyoto\nl\nla\nlab\nLaban\nlabel\nlabia\nlabial\nlabile\nlability\nlabium\nlaboratory\nlaborious\nlabour\nLabrador\nlabradorite\nlabyrinth\nlac\nlace\nlacerate\nLacerta\nlacewing\nLachesis\nlachrymose\nlack\nlackadaisic\nlackey\nlaconic\nlacquer\nlacrosse\nlactate\nlactose\nlacuna\nlacunae\nlacustrine\nlacy\nlad\nladen\nladle\nlady\nladybird\nladybug\nladyfern\nLafayette\nlag\nlager\nlagging\nlagoon\nLagos\nLagrange\nLagrangian\nLaguerre\nLahore\nlaid\nLaidlaw\nlain\nlair\nlaissez\nlaity\nlake\nLakehurst\nlakeside\nlakh\nlam\nlama\nLamar\nLamarck\nlamb\nlambda\nlambert\nlame\nlamellar\nlament\nlamentation\nlaminar\nlaminate\nlamp\nlampblack\nlamplight\nlampoon\nlamprey\nLana\nLancashire\nLancaster\nlance\nLancelot\nlancet\nland\nlandau\nlandfill\nlandhold\nLandis\nlandlady\nlandlocked\nlandlord\nlandlubber\nlandmark\nlandmass\nlandowner\nlandowning\nlandscape\nlandslide\nlane\nLang\nLange\nLangley\nLangmuir\nlanguage\nlanguid\nlanguish\nlangur\nLanka\nlanky\nLansing\nlantern\nlanthanide\nlanthanum\nLao\nLaocoon\nLaos\nLaotian\nlap\nlapel\nlapelled\nlapidary\nLaplace\nlappet\nlapse\nLaramie\nlarceny\nlarch\nlard\nLaredo\nLares\nlarge\nlargemouth\nlargesse\nlariat\nlark\nLarkin\nlarkspur\nLarry\nLars\nLarsen\nLarson\nlarva\nlarvae\nlarval\nlaryngeal\nlarynges\nlarynx\nlascar\nlascivious\nlase\nlash\nlass\nlasso\nlast\nLaszlo\nlatch\nlate\nlatent\nlater\nlatera\nlateral\nLateran\nlaterite\nlatex\nlath\nlathe\nLathrop\nLatin\nLatinate\nlatitude\nlatitudinal\nlatitudinary\nLatrobe\nlatter\nlattice\nlatus\nLatvia\nlaud\nlaudanum\nlaudatory\nLauderdale\nLaue\nlaugh\nlaughingstock\nLaughlin\nlaughter\nlaunch\nlaunder\nlaundry\nlaura\nlaureate\nlaurel\nLauren\nLaurent\nLaurentian\nLaurie\nLausanne\nlava\nlavabo\nlavatory\nlavender\nlavish\nLavoisier\nlaw\nlawbreaker\nlawbreaking\nlawful\nlawgiver\nlawgiving\nlawmake\nlawman\nlawmen\nlawn\nLawrence\nlawrencium\nLawson\nlawsuit\nlawyer\nlax\nlaxative\nlay\nlayette\nlayman\nlaymen\nlayoff\nlayout\nlayperson\nLayton\nlayup\nLazarus\nlaze\nlazy\nlazybones\nlea\nleach\nleachate\nlead\nleaden\nleadeth\nleadsman\nleadsmen\nleaf\nleaflet\nleafy\nleague\nleak\nleakage\nleaky\nlean\nLeander\nleap\nleapfrog\nleapt\nLear\nlearn\nlease\nleasehold\nleash\nleast\nleather\nleatherback\nleatherneck\nleatherwork\nleathery\nleave\nleaven\nLeavenworth\nLebanese\nLebanon\nlebensraum\nLebesgue\nlecher\nlechery\nlectern\nlectionary\nlecture\nled\nledge\nlee\nleech\nLeeds\nleek\nleer\nleery\nLeeuwenhoek\nleeward\nleeway\nleft\nleftmost\nleftover\nleftward\nlefty\nleg\nlegacy\nlegal\nlegate\nlegatee\nlegato\nlegend\nlegendary\nLegendre\nlegerdemain\nlegging\nleggy\nleghorn\nlegible\nlegion\nlegislate\nlegislature\nlegitimacy\nlegitimate\nlegume\nleguminous\nLehigh\nLehman\nLeibniz\nLeigh\nLeighton\nLeila\nleisure\nleitmotif\nleitmotiv\nLeland\nlemma\nlemming\nlemon\nlemonade\nLemuel\nlemur\nLen\nLena\nlend\nlength\nlengthen\nlengthwise\nlengthy\nlenient\nLenin\nLeningrad\nLennox\nLenny\nLenore\nlens\nlent\nLenten\nlenticular\nlentil\nLeo\nLeon\nLeona\nLeonard\nLeonardo\nLeone\nLeonid\nleonine\nleopard\nLeopold\nleper\nlepidolite\nlepidopterist\nleprosy\nLeroy\nLesbian\nlesion\nLeslie\nLesotho\nless\nlessee\nlessen\nlesson\nlessor\nlest\nLester\nlet\nlethal\nlethargy\nLethe\nLetitia\nletterhead\nletterman\nlettermen\nlettuce\nleucine\nLev\nlevee\nlevel\nlever\nleverage\nLevi\nleviathan\nLevin\nLevine\nLevis\nlevitate\nLeviticus\nLevitt\nlevity\nlevulose\nlevy\nlew\nlewd\nlewis\nlexical\nlexicographer\nlexicography\nlexicon\nLexington\nLeyden\nliable\nliaison\nliana\nliar\nlibation\nlibel\nlibelous\nliberal\nliberate\nLiberia\nlibertarian\nlibertine\nliberty\nlibidinous\nlibido\nLibra\nlibrarian\nlibrary\nlibrate\nlibrettist\nlibretto\nLibreville\nLibya\nlice\nlicensable\nlicensee\nlicensor\nlicentious\nlichen\nlick\nlicorice\nlid\nlie\nLieberman\nLiechtenstein\nlien\nlieu\nlieutenant\nlife\nlifeblood\nlifeboat\nlifeguard\nlifelong\nlifespan\nlifestyle\nlifetime\nLIFO\nlift\nligament\nligand\nligature\nLigget\nLiggett\nlight\nlighten\nlightface\nlightfooted\nlighthearted\nlighthouse\nlightning\nlightproof\nlightweight\nlignite\nlignum\nlike\nlikeable\nliken\nlikewise\nLila\nlilac\nLilian\nLillian\nLilliputian\nLilly\nlilt\nlily\nlim\nLima\nlimb\nlimbic\nlimbo\nlime\nlimelight\nlimerick\nlimestone\nlimit\nlimitate\nlimnology\nlimousine\nlimp\nlimpet\nlimpid\nlimpkin\nLin\nlinchpin\nLincoln\nLind\nLinda\nLindberg\nLindbergh\nlinden\nLindholm\nLindquist\nLindsay\nLindsey\nLindstrom\nline\nlineage\nlineal\nlinear\nlinebacker\nlineman\nlinemen\nlinen\nlineprinter\nlineup\nlinger\nlingerie\nlingo\nlingua\nlingual\nlinguist\nliniment\nlink\nlinkage\nLinnaeus\nlinoleic\nlinoleum\nLinotype\nlinseed\nlint\nLinton\nLinus\nlion\nLionel\nlioness\nlip\nlipid\nLippincott\nLipschitz\nLipscomb\nlipstick\nLipton\nliquefaction\nliquefy\nliqueur\nliquid\nliquidate\nliquor\nLisa\nLisbon\nLise\nlisle\nlisp\nLissajous\nlist\nlisten\nlit\nlitany\nliteracy\nliteral\nliterary\nliterate\nliterature\nlithe\nlithic\nlithium\nlithograph\nlithography\nlithology\nlithosphere\nlithospheric\nLithuania\nlitigant\nlitigate\nlitigious\nlitmus\nlitterbug\nlittermate\nlittle\nlittleneck\nLittleton\nLitton\nlittoral\nliturgic\nliturgy\nlive\nliven\nLivermore\nLiverpool\nLiverpudlian\nliverwort\nlivery\nlivestock\nliveth\nlivid\nLivingston\nlivre\nLiz\nlizard\nLizzie\nllama\nLloyd\nlo\nload\nloaf\nloam\nloamy\nloan\nloanword\nloath\nloathe\nloathsome\nloaves\nlob\nlobar\nlobby\nlobe\nLobelia\nloblolly\nlobo\nlobscouse\nlobster\nlobular\nlobule\nlocal\nlocale\nlocate\nloch\nloci\nlock\nLocke\nLockhart\nLockheed\nLockian\nlocknut\nlockout\nlocksmith\nlockup\nLockwood\nlocomote\nlocomotion\nlocomotive\nlocomotor\nlocomotory\nlocoweed\nlocus\nlocust\nlocutor\nlodestone\nlodge\nlodgepole\nLodowick\nLoeb\nl'oeil\nloess\nloft\nlofty\nlog\nLogan\nlogarithm\nlogarithmic\nloge\nloggerhead\nlogging\nlogic\nlogician\nlogin\nlogistic\nlogjam\nloin\nloincloth\nLoire\nLois\nloiter\nLoki\nLola\nloll\nlollipop\nlolly\nLomb\nLombard\nLombardy\nLome\nLondon\nlone\nlonesome\nlong\nlongevity\nLongfellow\nlonghand\nlonghorn\nlongish\nlongitude\nlongitudinal\nlongleg\nlongstanding\nlongtime\nlongue\nlongwinded\nlook\nlookout\nlookup\nloom\nLoomis\nloon\nloop\nloophole\nloose\nlooseleaf\nloosen\nloosestrife\nloot\nlop\nlope\nLopez\nlopseed\nlopsided\nloquacious\nloquacity\nloquat\nlord\nlordosis\nlore\nLorelei\nLoren\nLorenz\nLorinda\nloris\nLorraine\nlorry\nlosable\nlose\nloss\nlossy\nlost\nlot\nlotion\nLotte\nlottery\nLottie\nlotus\nLou\nloud\nloudspeaker\nloudspeaking\nLouis\nLouisa\nLouise\nLouisiana\nLouisville\nlounge\nLounsbury\nLourdes\nlouse\nlousewort\nlousy\nLouvre\nlove\nlovebird\nLovelace\nLoveland\nlovelorn\nlow\nlowboy\nlowdown\nLowe\nLowell\nlowland\nLowry\nlox\nloy\nloyal\nloyalty\nlozenge\nl's\nLSI\nLTV\nLubbock\nLubell\nlubricant\nlubricate\nlubricious\nlubricity\nLucas\nLucerne\nLucia\nLucian\nlucid\nLucifer\nLucille\nLucius\nluck\nlucky\nlucrative\nlucre\nLucretia\nLucretius\nlucy\nludicrous\nLudlow\nLudwig\nLufthansa\nLuftwaffe\nlug\nluge\nluger\nluggage\nlugging\nlugubrious\nLuis\nluke\nlukewarm\nlull\nlullaby\nlulu\nlumbago\nlumbar\nlumber\nlumberjack\nlumberman\nlumbermen\nlumen\nluminance\nluminary\nluminescent\nluminosity\nluminous\nlummox\nlump\nlumpish\nLumpur\nlumpy\nlunacy\nlunar\nlunary\nlunate\nlunatic\nlunch\nluncheon\nlunchroom\nlunchtime\nLund\nLundberg\nLundquist\nlung\nlunge\nlupine\nLura\nlurch\nlure\nlurid\nlurk\nLusaka\nluscious\nlush\nlust\nlustful\nlustrous\nlusty\nlutanist\nlute\nlutetium\nLuther\nLutheran\nLutz\nlux\nluxe\nLuxembourg\nluxuriant\nluxuriate\nluxurious\nluxury\nLuzon\nL'vov\nlycee\nlycopodium\nLydia\nlye\nlying\nLykes\nLyle\nLyman\nlymph\nlymphocyte\nlymphoma\nlynch\nLynchburg\nLynn\nlynx\nLyon\nLyra\nlyre\nlyrebird\nlyric\nLysenko\nlysergic\nlysine\nm\nma\nMabel\nMac\nmacabre\nMacadamia\nmacaque\nMacArthur\nMacassar\nmacaw\nMacbeth\nMacDonald\nMacDougall\nmace\nMacedon\nMacedonia\nmacerate\nMacGregor\nMach\nmachete\nMachiavelli\nmachination\nmachine\nmachinery\nmachismo\nmacho\nmacintosh\nmack\nMacKenzie\nmackerel\nMackey\nMackinac\nMackinaw\nmackintosh\nMacMahon\nMacMillan\nMacon\nmacro\nmacromolecular\nmacromolecule\nmacrophage\nmacroscopic\nmacrostructure\nmad\nMadagascar\nmadam\nMadame\nmadcap\nmadden\nMaddox\nmade\nMadeira\nMadeleine\nMadeline\nmadhouse\nMadhya\nMadison\nmadman\nmadmen\nMadonna\nMadras\nMadrid\nmadrigal\nMadsen\nmadstone\nMae\nmaelstrom\nmaestro\nMafia\nMafioso\nmagazine\nMagdalene\nMagellanic\nmagenta\nMaggie\nmaggot\nmaggoty\nmagi\nmagic\nmagician\nmagisterial\nmagistrate\nmagma\nmagna\nmagnanimity\nmagnanimous\nmagnate\nmagnesia\nmagnesite\nmagnesium\nmagnet\nmagnetic\nmagnetite\nmagneto\nmagnetron\nmagnificent\nmagnify\nmagnitude\nmagnolia\nmagnum\nMagnuson\nMagog\nmagpie\nMagruder\nmaharaja\nMaharashtra\nMahayana\nMahayanist\nmahogany\nMahoney\nmaid\nmaiden\nmaidenhair\nmaidservant\nMaier\nmail\nmailbox\nmailman\nmailmen\nmaim\nmain\nMaine\nmainframe\nmainland\nmainline\nmainstay\nmainstream\nmaintain\nmaintenance\nmaitre\nmajestic\nmajesty\nmajor\nMajorca\nmake\nmakeshift\nmakeup\nMalabar\nmaladapt\nmaladaptive\nmaladjust\nmaladroit\nmalady\nMalagasy\nmalaise\nmalaprop\nmalaria\nmalarial\nMalawi\nMalay\nMalaysia\nMalcolm\nmalconduct\nmalcontent\nMalden\nmaldistribute\nMaldive\nmale\nmaledict\nmalevolent\nmalfeasant\nmalformation\nmalformed\nmalfunction\nMali\nmalice\nmalicious\nmalign\nmalignant\nmall\nmallard\nmalleable\nmallet\nMallory\nmallow\nmalnourished\nmalnutrition\nmalocclusion\nMalone\nMaloney\nmalposed\nmalpractice\nMalraux\nmalt\nMalta\nMaltese\nMalthus\nMalthusian\nMalton\nmaltose\nmaltreat\nmaltster\nmambo\nmamma\nmammal\nmammalian\nmammary\nmammoth\nman\nmana\nmanage\nmanageable\nmanagerial\nManagua\nManama\nmanatee\nManchester\nManchuria\nmandamus\nmandarin\nmandate\nmandatory\nmandible\nmandrake\nmandrel\nmandrill\nmane\nmaneuver\nManfred\nmanganese\nmange\nmangel\nmangle\nmango\nmangrove\nmangy\nManhattan\nmanhole\nmania\nmaniac\nmaniacal\nmanic\nmanicure\nmanifest\nmanifestation\nmanifesto\nmanifold\nmanikin\nManila\nmanioc\nmanipulable\nmanipulate\nManitoba\nmankind\nManley\nMann\nmanna\nmannequin\nmannitol\nmanometer\nmanor\nmanpower\nmanse\nmanservant\nMansfield\nmansion\nmanslaughter\nmantel\nmantelpiece\nmantic\nmantis\nmantissa\nmantle\nmantrap\nmanual\nManuel\nmanufacture\nmanumission\nmanumit\nmanumitted\nmanure\nmanuscript\nManville\nmany\nmanzanita\nMao\nMaori\nmap\nmaple\nmar\nmarathon\nmaraud\nmarble\nMarc\nMarceau\nMarcel\nMarcello\nmarch\nMarcia\nMarco\nMarcus\nMarcy\nMardi\nmare\nMargaret\nmargarine\nMargery\nmargin\nmarginal\nmarginalia\nMargo\nMarguerite\nmaria\nMarianne\nMarie\nMarietta\nmarigold\nmarijuana\nMarilyn\nmarimba\nMarin\nmarina\nmarinade\nmarinate\nmarine\nMarino\nMario\nMarion\nmarionette\nmarital\nmaritime\nmarjoram\nMarjorie\nMarjory\nmark\nmarket\nmarketeer\nmarketplace\nmarketwise\nMarkham\nMarkov\nMarkovian\nmarksman\nmarksmen\nMarlboro\nMarlborough\nMarlene\nmarlin\nMarlowe\nmarmalade\nmarmoset\nmarmot\nmaroon\nmarque\nmarquee\nmarquess\nMarquette\nmarquis\nmarriage\nmarriageable\nMarrietta\nMarriott\nmarrow\nmarrowbone\nmarry\nMarseilles\nmarsh\nMarsha\nmarshal\nMarshall\nmarshland\nmarshmallow\nmarshy\nmarsupial\nmart\nmarten\nmartensite\nMartha\nmartial\nMartian\nmartin\nMartinez\nmartingale\nmartini\nMartinique\nMartinson\nMarty\nmartyr\nmartyrdom\nmarvel\nmarvelous\nMarvin\nMarx\nMary\nMaryland\nmarzipan\nmascara\nmasculine\nmaser\nMaseru\nmash\nmask\nmasochism\nmasochist\nmason\nMasonic\nMasonite\nmasonry\nmasque\nmasquerade\nmass\nMassachusetts\nmassacre\nmassage\nmasseur\nMassey\nmassif\nmassive\nmast\nmasterful\nmastermind\nmasterpiece\nmastery\nmastic\nmastiff\nmastodon\nmat\nmatch\nmatchbook\nmatchmake\nmate\nMateo\nmater\nmaterial\nmateriel\nmaternal\nmaternity\nmath\nmathematic\nmathematician\nMathews\nMathewson\nMathias\nMathieu\nMatilda\nmatinal\nmatinee\nmatins\nMatisse\nmatriarch\nmatriarchal\nmatriarchy\nmatrices\nmatriculate\nmatrilineal\nmatrimonial\nmatrimony\nmatrix\nmatroid\nmatron\nMatson\nMatsumoto\nmatte\nMatthew\nmattock\nmattress\nMattson\nmaturate\nmature\nmaudlin\nmaul\nMaureen\nMaurice\nMauricio\nMaurine\nMauritania\nMauritius\nmausoleum\nmauve\nmaverick\nMavis\nmaw\nmawkish\nMawr\nmax\nmaxim\nmaxima\nmaximal\nMaximilian\nmaximum\nMaxine\nmaxwell\nMaxwellian\nmay\nMaya\nmayapple\nmaybe\nMayer\nMayfair\nMayflower\nmayfly\nmayhem\nMaynard\nMayo\nmayonnaise\nmayor\nmayoral\nmayst\nMazda\nmaze\nmazurka\nMBA\nMbabane\nMcAdams\nMcAllister\nMcBride\nMcCabe\nMcCall\nMcCallum\nMcCann\nMcCarthy\nMcCarty\nMcCauley\nMcClain\nMcClellan\nMcClure\nMcCluskey\nMcConnel\nMcConnell\nMcCormick\nMcCoy\nMcCracken\nMcCullough\nMcDaniel\nMcDermott\nMcDonald\nMcDonnell\nMcDougall\nMcDowell\nMcElroy\nMcFadden\nMcFarland\nMcGee\nMcGill\nMcGinnis\nMcGovern\nMcGowan\nMcGrath\nMcGraw\nMcGregor\nMcGuire\nMcHugh\nMcIntosh\nMcIntyre\nMcKay\nMcKee\nMcKenna\nMcKenzie\nMcKeon\nMcKesson\nMcKinley\nMcKinney\nMcKnight\nMcLaughlin\nMcLean\nMcLeod\nMcMahon\nMcMillan\nMcMullen\nMcNally\nMcNaughton\nMcNeil\nMcNulty\nMcPherson\nMD\nme\nmead\nmeadow\nmeadowland\nmeadowlark\nmeadowsweet\nmeager\nmeal\nmealtime\nmealy\nmean\nmeander\nmeaningful\nmeant\nmeantime\nmeanwhile\nmeasle\nmeasure\nmeat\nmeaty\nMecca\nmechanic\nmechanism\nmechanist\nmecum\nmedal\nmedallion\nmeddle\nMedea\nMedford\nmedia\nmedial\nmedian\nmediate\nmedic\nmedicate\nMedici\nmedicinal\nmedicine\nmedico\nmediocre\nmediocrity\nmeditate\nMediterranean\nmedium\nmedlar\nmedley\nMedusa\nmeek\nmeet\nmeetinghouse\nMeg\nmegabit\nmegabyte\nmegahertz\nmegalomania\nmegalomaniac\nmegalopolis\nmegaton\nmegavolt\nmegawatt\nmegaword\nmegohm\nMeier\nMeiji\nmeiosis\nMeistersinger\nMekong\nMel\nmelamine\nmelancholy\nMelanesia\nmelange\nMelanie\nmelanin\nmelanism\nmelanoma\nMelbourne\nMelcher\nmeld\nmelee\nMelinda\nmeliorate\nMelissa\nMellon\nmellow\nmelodic\nmelodious\nmelodrama\nmelodramatic\nmelody\nmelon\nMelpomene\nmelt\nmeltdown\nMelville\nMelvin\nmember\nmembrane\nmemento\nmemo\nmemoir\nmemorabilia\nmemorable\nmemoranda\nmemorandum\nmemorial\nmemory\nMemphis\nmen\nmenace\nmenagerie\nmenarche\nmend\nmendacious\nmendacity\nMendel\nmendelevium\nMendelian\nMendelssohn\nMenelaus\nmenfolk\nmenhaden\nmenial\nmeningitis\nmeniscus\nMenlo\nMennonite\nmenopausal\nmenopause\nMenorca\nmenstrual\nmenstruate\nmensurable\nmensuration\nmental\nmention\nmentor\nmenu\nMenzies\nmeow\nMephistopheles\nmercantile\nMercator\nMercedes\nmercenary\nmercer\nmerchandise\nmerchant\nmerciful\nMerck\nmercurial\nmercuric\nmercury\nmercy\nmere\nMeredith\nmeretricious\nmerganser\nmerge\nmeridian\nmeridional\nmeringue\nmerit\nmeritorious\nMerle\nmerlin\nmermaid\nMerriam\nMerrill\nMerrimack\nmerriment\nMerritt\nmerry\nmerrymake\nMervin\nmesa\nmescal\nmescaline\nmesenteric\nmesh\nmesmeric\nmesoderm\nmeson\nMesopotamia\nMesozoic\nmesquite\nmess\nmessage\nmessenger\nMessiah\nmessiah\nmessianic\nmessieurs\nMessrs\nmessy\nmestizo\nmet\nmetabole\nmetabolic\nmetabolism\nmetabolite\nmetal\nmetallic\nmetalliferous\nmetallography\nmetalloid\nmetallurgic\nmetallurgist\nmetallurgy\nmetalwork\nmetamorphic\nmetamorphism\nmetamorphose\nmetamorphosis\nmetaphor\nmetaphoric\nmetazoa\nmetazoan\nMetcalf\nmete\nmeteor\nmeteoric\nmeteorite\nmeteoritic\nmeteorology\nmeter\nmethacrylate\nmethane\nmethanol\nmethionine\nmethod\nmethodic\nmethodology\nMethuen\nMethuselah\nmethyl\nmethylene\nmeticulous\nmetier\nmetonymy\nmetric\nmetro\nmetronome\nmetropolis\nmetropolitan\nmettle\nmettlesome\nMetzler\nmew\nMexican\nMexico\nMeyer\nmezzanine\nmezzo\nmi\nMiami\nmiaow\nmiasma\nmiasmal\nmica\nmice\nMichael\nMichaelangelo\nMichel\nMichelangelo\nMichele\nMichelin\nMichelson\nmichigan\nMickelson\nMickey\nMicky\nmicro\nmicrobe\nmicrobial\nmicrocosm\nmicrography\nmicron\nMicronesia\nmicroscopy\nmid\nMidas\nmidband\nmidday\nmiddle\nMiddlebury\nmiddleman\nmiddlemen\nMiddlesex\nMiddleton\nMiddletown\nmiddleweight\nmidge\nmidget\nmidland\nmidmorn\nmidnight\nmidpoint\nmidrange\nmidscale\nmidsection\nmidshipman\nmidshipmen\nmidspan\nmidst\nmidstream\nmidterm\nmidway\nmidweek\nMidwest\nMidwestern\nmidwife\nmidwinter\nmidwives\nmidyear\nmien\nmiff\nmig\nmight\nmightn't\nmighty\nmignon\nmigrant\nmigrate\nmigratory\nMiguel\nmike\nmila\nMilan\nmilch\nmild\nmildew\nMildred\nmile\nmileage\nMiles\nmilestone\nmilieu\nmilitant\nmilitarism\nmilitarist\nmilitary\nmilitate\nmilitia\nmilitiaman\nmilitiamen\nmilk\nmilkweed\nmilky\nmill\nMillard\nmillenarian\nmillenia\nmillennia\nmillennium\nmillet\nMillie\nMillikan\nmillinery\nmillion\nmillionaire\nmillionfold\nmillionth\nmillipede\nmillstone\nmilord\nmilt\nMilton\nMiltonic\nMilwaukee\nmimeograph\nmimesis\nmimetic\nMimi\nmimic\nmimicked\nmimicking\nmimicry\nmimosa\nmin\nminaret\nmince\nmincemeat\nmind\nMindanao\nmindful\nmine\nminefield\nmineral\nmineralogy\nMinerva\nminestrone\nminesweeper\nmingle\nmini\nminiature\nminicomputer\nminim\nminima\nminimal\nminimax\nminimum\nminion\nministerial\nministry\nmink\nMinneapolis\nMinnesota\nMinnie\nminnow\nMinoan\nminor\nMinos\nminot\nMinotaur\nMinsk\nMinsky\nminstrel\nminstrelsy\nmint\nminuend\nminuet\nminus\nminuscule\nminute\nminuteman\nminutemen\nminutiae\nMiocene\nMira\nmiracle\nmiraculous\nmirage\nMiranda\nmire\nMirfak\nMiriam\nmirror\nmirth\nmisanthrope\nmisanthropic\nmiscegenation\nmiscellaneous\nmiscellany\nmischievous\nmiscible\nmiscreant\nmiser\nmisery\nmisnomer\nmisogynist\nmisogyny\nmiss\nmisshapen\nmissile\nmission\nmissionary\nMississippi\nMississippian\nmissive\nMissoula\nMissouri\nMissy\nmist\nmistletoe\nmistress\nmisty\nMIT\nMitchell\nmite\nmiterwort\nmitigate\nmitochondria\nmitosis\nmitral\nmitre\nmitt\nmitten\nmix\nmixture\nmixup\nMizar\nMN\nmnemonic\nMO\nmoan\nmoat\nmob\nmobcap\nMobil\nmobile\nmobility\nmobster\nmoccasin\nmocha\nmock\nmockernut\nmockery\nmockingbird\nmockup\nmodal\nmode\nmodel\nmodem\nmoderate\nmodern\nmodest\nModesto\nmodesty\nmodicum\nmodify\nmodish\nmodular\nmodulate\nmodule\nmoduli\nmodulo\nmodulus\nMoe\nMoen\nMogadiscio\nMoghul\nMohammed\nMohammedan\nMohawk\nMohr\nmoiety\nMoines\nmoire\nMoiseyev\nmoist\nmoisten\nmoisture\nmolal\nmolar\nmolasses\nmold\nMoldavia\nmoldboard\nmoldy\nmole\nmolecular\nmolecule\nmolehill\nmolest\nMoliere\nMoline\nMoll\nMollie\nmollify\nmollusk\nMolly\nmollycoddle\nMoloch\nmolt\nmolten\nMoluccas\nmolybdate\nmolybdenite\nmolybdenum\nmoment\nmomenta\nmomentary\nmomentous\nmomentum\nmommy\nMona\nMonaco\nmonad\nmonadic\nmonarch\nmonarchic\nmonarchy\nMonash\nmonastery\nmonastic\nmonaural\nMonday\nmonel\nmonetarism\nmonetary\nmoney\nmoneymake\nmoneywort\nMongolia\nmongoose\nmonic\nMonica\nmonies\nmonitor\nmonitory\nmonk\nmonkey\nmonkeyflower\nmonkish\nMonmouth\nMonoceros\nmonochromator\nmonocular\nmonogamous\nmonogamy\nmonolith\nmonologist\nmonologue\nmonomer\nmonomeric\nmonomial\nMonongahela\nmonopoly\nmonotonous\nmonotreme\nmonoxide\nMonroe\nMonrovia\nMonsanto\nmonsieur\nmonsoon\nmonster\nmonstrosity\nmonstrous\nMont\nmontage\nMontague\nMontana\nMontclair\nmonte\nMontenegrin\nMonterey\nMonteverdi\nMontevideo\nMontgomery\nmonth\nMonticello\nMontmartre\nMontpelier\nMontrachet\nMontreal\nMonty\nmonument\nmoo\nmooch\nmood\nmoody\nmoon\nmoonbeam\nMooney\nmoonlight\nmoonlit\nmoor\nMoore\nMoorish\nmoose\nmoot\nmop\nmoraine\nmoral\nmorale\nMoran\nmorass\nmoratorium\nMoravia\nmorbid\nmore\nmorel\nMoreland\nmoreover\nMoresby\nMorgan\nmorgen\nmorgue\nMoriarty\nmoribund\nMorley\nMormon\nmorn\nMoroccan\nMorocco\nmoron\nmorose\nmorpheme\nmorphemic\nmorphine\nmorphism\nmorphology\nmorphophonemic\nMorrill\nmorris\nMorrison\nMorrissey\nMorristown\nmorrow\nMorse\nmorsel\nmort\nmortal\nmortar\nmortem\nmortgage\nmortgagee\nmortgagor\nmortician\nmortify\nmortise\nMorton\nmortuary\nmosaic\nMoscow\nMoser\nMoses\nMoslem\nmosque\nmosquito\nmosquitoes\nmoss\nmossy\nmost\nmot\nmotel\nmotet\nmoth\nmother\nmotherland\nmotif\nmotion\nmotivate\nmotive\nmotley\nmotor\nmotorcade\nmotorcar\nmotorcycle\nMotorola\nmottle\nmotto\nmould\nMoulton\nmound\nmount\nmountain\nmountaineer\nmountainous\nmountainside\nmountaintop\nmountebank\nmourn\nmournful\nmouse\nmousse\nmoustache\nmousy\nmouth\nmouthful\nmouthpart\nmouthpiece\nMouton\nmove\nmovie\nmow\nMoyer\nMozart\nmozzarella\nMPH\nMr\nMrs\nMs\nm's\nMt\nmu\nmuch\nmucilage\nmuck\nmucosa\nmucus\nmud\nMudd\nmuddle\nmuddlehead\nmuddy\nmudguard\nmudhole\nmudsling\nMueller\nMuenster\nmuezzin\nmuff\nmuffin\nmuffle\nmug\nmugging\nmuggy\nmugho\nMuir\nMukden\nmukluk\nmulatto\nmulberry\nmulch\nmulct\nmule\nmulish\nmull\nmullah\nmullein\nMullen\nmulligan\nmulligatawny\nmullion\nmulti\nMultics\nmultifarious\nmultinomial\nmultiple\nmultiplet\nmultiplex\nmultiplexor\nmultiplicand\nmultiplication\nmultiplicative\nmultiplicity\nmultitude\nmultitudinous\nmum\nmumble\nMumford\nmummify\nmummy\nmunch\nMuncie\nmundane\nmung\nMunich\nmunicipal\nmunificent\nmunition\nMunson\nmuon\nMuong\nmural\nmurder\nmurderous\nmuriatic\nMuriel\nmurk\nmurky\nmurmur\nMurphy\nMurray\nmurre\nMuscat\nmuscle\nMuscovite\nMuscovy\nmuscular\nmusculature\nmuse\nmuseum\nmush\nmushroom\nmushy\nmusic\nmusicale\nmusician\nmusicology\nmusk\nMuskegon\nmuskellunge\nmusket\nmuskmelon\nmuskox\nmuskoxen\nmuskrat\nmusky\nmuslim\nmuslin\nmussel\nmust\nmustache\nmustachio\nmustang\nmustard\nmustn't\nmusty\nmutagen\nmutandis\nmutant\nmutate\nmutatis\nmute\nmutilate\nmutineer\nmutiny\nmutt\nmutter\nmutton\nmutual\nmutuel\nMuzak\nMuzo\nmuzzle\nmy\nMycenae\nMycenaean\nmycobacteria\nmycology\nmycoplasma\nmycorrhiza\nmyel\nmyeline\nmyeloid\nMyers\nmylar\nmynah\nMynheer\nmyocardial\nmyocardium\nmyofibril\nmyoglobin\nmyopia\nmyopic\nmyosin\nMyra\nmyriad\nMyron\nmyrrh\nmyrtle\nmyself\nMysore\nmysterious\nmystery\nmystic\nmystify\nmystique\nmyth\nmythic\nmythology\nn\nNAACP\nnab\nNabisco\nNadine\nnadir\nnag\nNagasaki\nnagging\nNagoya\nNagy\nnaiad\nnail\nNair\nNairobi\nnaive\nnaivete\nNakayama\nnaked\nname\nnameable\nnameplate\nnamesake\nNan\nNancy\nNanette\nNanking\nnanosecond\nNantucket\nNaomi\nnap\nnapkin\nNaples\nNapoleon\nNapoleonic\nNarbonne\nnarcissist\nnarcissus\nnarcosis\nnarcotic\nNarragansett\nnarrate\nnarrow\nnarrowminded\nnarwhal\nnary\nNASA\nnasal\nnascent\nNash\nNashua\nNashville\nNassau\nnasturtium\nnasty\nNat\nnatal\nNatalie\nNatchez\nNate\nNathan\nNathaniel\nnation\nnationwide\nnative\nNATO\nnatty\nnatural\nnature\nnaturopath\nnaughty\nnausea\nnauseate\nnauseum\nnautical\nnautilus\nNavajo\nnaval\nnave\nnavel\nnavigable\nnavigate\nnavy\nnawab\nnay\nNazarene\nNazareth\nNazi\nNazism\nNBC\nNBS\nNC\nNCAA\nNCO\nNCR\nND\nNdjamena\nne\nNeal\nNeanderthal\nNeapolitan\nnear\nnearby\nnearsighted\nneat\nneater\nneath\nNebraska\nNebuchadnezzar\nnebula\nnebulae\nnebular\nnebulous\nnecessary\nnecessitate\nnecessity\nneck\nnecklace\nneckline\nnecktie\nnecromancer\nnecromancy\nnecromantic\nnecropsy\nnecrosis\nnecrotic\nnectar\nnectareous\nnectarine\nnectary\nNed\nnee\nneed\nneedful\nneedham\nneedle\nneedlepoint\nneedn't\nneedy\nnefarious\nNeff\nnegate\nneglect\nnegligee\nnegligent\nnegligible\nnegotiable\nnegotiate\nNegro\nNegroes\nNegroid\nNehru\nneigh\nNeil\nneither\nNell\nNellie\nNelsen\nNelson\nnematocyst\nnematode\nnemesis\nneo\nneoclassic\nneodymium\nneolithic\nneologism\nneon\nneonatal\nneonate\nneophyte\nneoprene\nneoteny\nNepal\nnepenthe\nnephew\nnepotism\nnepotistic\nNeptune\nneptunium\nnereid\nNero\nnerve\nnervous\nNess\nnest\nnestle\nNestor\nnet\nnether\nNetherlands\nnetherworld\nnettle\nnettlesome\nnetwork\nNeumann\nneural\nneuralgia\nneurasthenic\nneuritis\nneuroanatomic\nneuroanatomy\nneuroanotomy\nneurology\nneuromuscular\nneuron\nneuronal\nneuropathology\nneurophysiology\nneuropsychiatric\nneuroses\nneurosis\nneurotic\nneuter\nneutral\nneutrino\nneutron\nneutronium\nNeva\nNevada\nnever\nnevertheless\nNevins\nnew\nNewark\nNewbold\nnewborn\nNewcastle\nnewcomer\nnewel\nNewell\nnewfound\nNewfoundland\nnewline\nnewlywed\nNewman\nNewport\nnewsboy\nnewscast\nnewsletter\nnewsman\nnewsmen\nnewspaper\nnewspaperman\nnewspapermen\nnewsreel\nnewsstand\nNewsweek\nnewt\nnewton\nNewtonian\nnext\nNguyen\nNH\nniacin\nNiagara\nNiamey\nnib\nnibble\nNibelung\nNicaragua\nnice\nnicety\nniche\nNicholas\nNicholls\nNichols\nNicholson\nnichrome\nnick\nnickel\nnickname\nNicodemus\nNicosia\nnicotinamide\nnicotine\nniece\nNielsen\nNielson\nNietzsche\nnifty\nNiger\nNigeria\nniggardly\nnigger\nniggle\nnigh\nnight\nnightcap\nnightclub\nnightdress\nnightfall\nnightgown\nnighthawk\nnightingale\nnightmare\nnightmarish\nnightshade\nnightshirt\nnighttime\nNIH\nnihilism\nnihilist\nNikko\nNikolai\nnil\nNile\nnilpotent\nnimble\nnimbus\nNIMH\nNina\nnine\nninebark\nninefold\nnineteen\nnineteenth\nninetieth\nninety\nninetyfold\nNineveh\nninth\nNiobe\nniobium\nnip\nnipple\nNippon\nnirvana\nnit\nnitpick\nnitrate\nnitric\nnitride\nnitrite\nnitrogen\nnitrogenous\nnitroglycerine\nnitrous\nnitty\nNixon\nNJ\nNM\nNNE\nNNW\nno\nNOAA\nNoah\nnob\nNobel\nnobelium\nnoble\nnobleman\nnoblemen\nnoblesse\nnobody\nnobody'd\nnocturnal\nnocturne\nnod\nnodal\nnode\nnodular\nnodule\nNoel\nNoetherian\nnoise\nnoisemake\nnoisome\nnoisy\nNolan\nNoll\nnolo\nnomad\nnomadic\nnomenclature\nnominal\nnominate\nnominee\nnomogram\nnomograph\nnon\nnonce\nnonchalant\nnondescript\nnone\nnonetheless\nnonogenarian\nnonsensic\nnoodle\nnook\nnoon\nnoontime\nnoose\nnor\nNora\nNordhoff\nNordic\nNordstrom\nNoreen\nNorfolk\nnorm\nNorma\nnormal\nnormalcy\nNorman\nNormandy\nnormative\nNorris\nNorse\nnorth\nNorthampton\nnorthbound\nnortheast\nnortheastern\nnortherly\nnorthern\nnorthernmost\nnorthland\nNorthrop\nNorthrup\nNorthumberland\nnorthward\nnorthwest\nnorthwestern\nNorton\nNorwalk\nNorway\nNorwegian\nNorwich\nnose\nnosebag\nnosebleed\nnostalgia\nnostalgic\nNostradamus\nNostrand\nnostril\nnosy\nnot\nnotary\nnotate\nnotch\nnote\nnotebook\nnoteworthy\nnothing\nnotice\nnoticeable\nnotify\nnotion\nnotocord\nnotoriety\nnotorious\nNotre\nNottingham\nnotwithstanding\nNouakchott\nnought\nnoun\nnourish\nnouveau\nNov\nnova\nnovae\nNovak\nnovel\nnovelty\nNovember\nnovice\nnovitiate\nnovo\nNovosibirsk\nnow\nnowadays\nnowhere\nnowise\nnoxious\nnozzle\nNRC\nnroff\nn's\nNSF\nNTIS\nnu\nnuance\nNubia\nnubile\nnucleant\nnuclear\nnucleate\nnuclei\nnucleic\nnucleoli\nnucleolus\nnucleon\nnucleotide\nnucleus\nnuclide\nnude\nnudge\nnudibranch\nnugatory\nnugget\nnuisance\nnull\nnullify\nNullstellensatz\nnumb\nnumbly\nnumerable\nnumeral\nnumerate\nnumeric\nnumerology\nnumerous\nnuminous\nnumismatic\nnumismatist\nnun\nnuptial\nnurse\nnursery\nnurturant\nnurture\nnut\nnutate\nnutcrack\nnuthatch\nnutmeg\nnutria\nnutrient\nnutrition\nnutritious\nnutritive\nnutshell\nnuzzle\nNV\nNW\nNY\nNYC\nnylon\nnymph\nnymphomania\nnymphomaniac\nNyquist\nNYU\no\noaf\noak\noaken\nOakland\nOakley\noakwood\noar\noases\noasis\noat\noatcake\noath\noatmeal\nobduracy\nobdurate\nobedient\nobeisant\nobelisk\nOberlin\nobese\nobey\nobfuscate\nobfuscatory\nobituary\nobject\nobjectify\nobjector\nobjet\noblate\nobligate\nobligatory\noblige\noblique\nobliterate\noblivion\noblivious\noblong\nobnoxious\noboe\noboist\nO'Brien\nobscene\nobscure\nobsequious\nobsequy\nobservant\nobservation\nobservatory\nobserve\nobsess\nobsession\nobsessive\nobsidian\nobsolescent\nobsolete\nobstacle\nobstetric\nobstetrician\nobstinacy\nobstinate\nobstruct\nobstruent\nobtain\nobtrude\nobtrusive\nobtuse\nobverse\nobviate\nobvious\nocarina\noccasion\noccident\noccidental\noccipital\nocclude\nocclusion\nocclusive\noccult\noccultate\noccupant\noccupation\noccupy\noccur\noccurred\noccurrent\noccurring\nocean\nOceania\noceanic\noceanographer\noceanography\noceanside\nocelot\no'clock\nO'Connell\nO'Connor\nOct\noctagon\noctagonal\noctahedra\noctahedral\noctahedron\noctal\noctane\noctant\noctave\nOctavia\noctennial\noctet\noctile\noctillion\nOctober\noctogenarian\noctopus\noctoroon\nocular\nodd\noddball\node\nO'Dell\nOdessa\nOdin\nodious\nodium\nodometer\nO'Donnell\nodorous\nO'Dwyer\nOdysseus\nodyssey\noedipal\nOedipus\noenology\no'er\noersted\nof\noff\noffal\noffbeat\nOffenbach\noffend\noffensive\noffer\noffertory\noffhand\noffice\nofficeholder\nofficemate\nofficial\nofficialdom\nofficiate\nofficio\nofficious\noffload\noffprint\noffsaddle\noffset\noffsetting\noffshoot\noffshore\noffspring\noffstage\noft\noften\noftentimes\nOgden\nogle\nogre\nogress\noh\nO'Hare\nOhio\nohm\nohmic\nohmmeter\noil\noilcloth\noilman\noilmen\noilseed\noily\noint\nOjibwa\nOK\nokapi\nokay\nOkinawa\nOklahoma\nokra\nOlaf\nOlav\nold\nolden\nOldenburg\nOldsmobile\noldster\nOlduvai\noldy\noleander\nO'Leary\nolefin\noleomargarine\nolfactory\nOlga\noligarchic\noligarchy\nOligocene\noligoclase\noligopoly\nOlin\nolive\nOlivetti\nOlivia\nOlivier\nolivine\nOlsen\nOlson\nOlympia\nOlympic\nOmaha\nOman\nombudsman\nombudsperson\nomega\nomelet\nomen\nomicron\nominous\nomission\nomit\nomitted\nomitting\nomnibus\nomnipotent\nomnipresent\nomniscient\nomnivore\nomnivorous\non\nonce\noncology\noncoming\none\nOneida\nO'Neill\nonerous\noneself\nonetime\noneupmanship\nongoing\nonion\nonlooker\nonlooking\nonly\nonomatopoeia\nonomatopoeic\nOnondaga\nonrush\nonrushing\nonset\nonslaught\nOntario\nonto\nontogeny\nontology\nonus\nonward\nonyx\noocyte\noodles\nooze\nopacity\nopal\nopalescent\nopaque\nOPEC\nOpel\nopen\nopera\noperable\noperand\noperant\noperate\noperatic\noperetta\noperon\nOphiucus\nopiate\nopinion\nopinionate\nopium\nopossum\nOppenheimer\nopponent\nopportune\nopposable\noppose\nopposite\nopposition\noppress\noppression\noppressive\noppressor\nopprobrium\nopt\nopthalmic\nopthalmology\noptic\noptima\noptimal\noptimism\noptimist\noptimum\noption\noptoacoustic\noptoisolate\noptometrist\noptometry\nopulent\nopus\nor\noracle\noracular\noral\norange\norangeroot\norangutan\norate\noratoric\noratorio\noratory\norb\norbit\norbital\nOrca\norchard\norchestra\norchestral\norchestrate\norchid\norchis\nordain\nordeal\norder\nordinal\nordinance\nordinary\nordinate\nordnance\nore\noregano\nOregon\nOresteia\nOrestes\norgan\norgandy\norganic\norganismic\norganometallic\norgasm\norgiastic\norgy\norient\noriental\norifice\norigami\norigin\noriginal\noriginate\nOrin\nOrinoco\noriole\nOrion\nOrkney\nOrlando\nOrleans\nornament\nornamentation\nornate\nornery\nornithology\norography\nOrono\norphan\norphanage\nOrpheus\nOrphic\nOrr\nOrtega\northant\northicon\northoclase\northodontic\northodontist\northodox\northodoxy\northogonal\northography\northonormal\northopedic\northophosphate\northorhombic\nOrville\nOrwell\nOrwellian\no's\nOsaka\nOsborn\nOsborne\nOscar\noscillate\noscillatory\noscilloscope\nOsgood\nO'Shea\nOshkosh\nosier\nOsiris\nOslo\nosmium\nosmosis\nosmotic\nosprey\nosseous\nossify\nostensible\nostentation\nostentatious\nosteology\nosteopath\nosteopathic\nosteopathy\nosteoporosis\nostracism\nostracod\nOstrander\nostrich\nO'Sullivan\nOswald\nOthello\nother\notherwise\notherworld\notiose\nOtis\nOtt\nOttawa\notter\nOtto\nOttoman\nOuagadougou\nouch\nought\noughtn't\nounce\nour\nourselves\noust\nout\noutermost\noutlandish\noutlawry\noutrageous\nouvre\nouzel\nouzo\nova\noval\novary\novate\noven\novenbird\nover\novert\noverture\nOvid\noviduct\noviform\noviparous\novipositor\novoviviparous\novulate\novum\now\nowe\nOwens\nowl\nowlet\nowly\nown\nox\noxalate\noxalic\noxbow\noxcart\noxen\noxeye\nOxford\noxidant\noxidate\noxide\nOxnard\nOxonian\noxygen\noxygenate\noyster\nOzark\nozone\np\npa\nPablo\nPabst\npace\npacemake\npacesetting\npacific\npacifism\npacifist\npacify\npack\npackage\nPackard\npacket\npact\npad\npaddle\npaddock\npaddy\npadlock\npadre\npaean\npagan\npage\npageant\npageantry\npaginate\npagoda\npaid\npail\npain\nPaine\npainful\npainstaking\npaint\npaintbrush\npair\npairwise\nPakistan\nPakistani\npal\npalace\npalaeontology\npalate\nPalatine\npalazzi\npalazzo\npale\npaleoanthropology\nPaleolithic\nPaleozoic\nPalermo\nPalestine\npalette\npalfrey\npalindrome\npalindromic\npalisade\npall\npalladia\nPalladian\npalladium\npallet\npalliate\npallid\npalm\npalmate\npalmetto\nPalmolive\nPalmyra\nPalo\nPalomar\npalp\npalpate\npalsy\nPam\nPamela\npampa\npamper\npamphlet\npan\npanacea\npanama\nPanamanian\npancake\nPancho\npancreas\npancreatic\npanda\nPandanus\npandemic\npandemonium\npander\nPandora\npane\npanel\npang\nPangaea\npanhandle\npanic\npanicked\npanicking\npanicky\npanicle\npanjandrum\npanoply\npanorama\npanoramic\npansy\npant\npantaloon\npantheism\npantheist\npantheon\npanther\npantomime\npantomimic\npantothenic\npantry\npanty\nPaoli\npap\npapa\npapacy\npapal\npapaw\npaper\npaperback\npaperweight\npaperwork\npapery\npapillary\npapoose\nPappas\npappy\npaprika\nPapua\npapyri\npapyrus\npar\nparabola\nparabolic\nparaboloid\nparaboloidal\nparachute\nparade\nparadigm\nparadigmatic\nparadise\nparadox\nparadoxic\nparaffin\nparagon\nparagonite\nparagraph\nParaguay\nParaguayan\nparakeet\nparalinguistic\nparallax\nparallel\nparallelepiped\nparallelogram\nparalysis\nparalytic\nparamagnet\nparamagnetic\nparameter\nparamilitary\nparamount\nParamus\nparanoia\nparanoiac\nparanoid\nparanormal\nparapet\nparaphernalia\nparaphrase\nparapsychology\nparasite\nparasitic\nparasol\nparasympathetic\nparatroop\nparaxial\nparboil\nparcel\nparch\npardon\npare\nparegoric\nparent\nparentage\nparental\nparentheses\nparenthesis\nparenthetic\nPareto\npariah\nparimutuel\nParis\nparish\nparishioner\nParisian\npark\nparka\nParke\nParkinson\nparkish\nparkland\nparkway\nparlance\nparlay\nparley\nparliament\nparliamentarian\nparliamentary\nParmesan\nparochial\nparody\nparole\nparolee\nparoxysm\nparquet\nParr\nParrish\nparrot\nparry\nparse\nParsi\nParsifal\nparsimonious\nparsimony\nparsley\nparsnip\nparson\nparsonage\npart\npartake\nParthenon\nParthia\npartial\nparticipant\nparticipate\nparticiple\nparticle\nparticular\nparticulate\npartisan\npartition\npartner\npartook\npartridge\nparty\nparvenu\nPasadena\nPascal\npaschal\npasha\nPaso\npass\npassage\npassageway\nPassaic\npassarine\npassband\npassbook\npasse\npassenger\npasserby\npassim\npassion\npassionate\npassivate\npassive\nPassover\npassport\npassword\npast\npaste\npasteboard\npastel\npasteup\nPasteur\npastiche\npastime\npastor\npastoral\npastry\npasture\npasty\npat\nPatagonia\npatch\npatchwork\npatchy\npate\npatent\npatentee\npater\npaternal\npaternoster\nPaterson\npath\npathbreaking\npathetic\npathogen\npathogenesis\npathogenic\npathology\npathos\npathway\npatient\npatina\npatio\npatois\npatriarch\npatriarchal\npatriarchy\nPatrice\nPatricia\npatrician\nPatrick\npatrilineage\npatrilineal\npatrimonial\npatrimony\npatriot\npatriotic\npatristic\npatrol\npatrolled\npatrolling\npatrolman\npatrolmen\npatron\npatronage\npatroness\nPatsy\npattern\nPatterson\nPatti\nPatton\npatty\npaucity\nPaul\nPaula\nPaulette\nPauli\nPauline\nPaulo\nPaulsen\nPaulson\nPaulus\npaunch\npaunchy\npauper\npause\npavanne\npave\npavilion\nPavlov\nPavlovian\npaw\npawn\npawnbroker\npawnshop\npawpaw\nPawtucket\npax\npay\npaycheck\npayday\npayload\npaymaster\nPayne\npayoff\npayroll\nPaz\nPBS\nPDP\npea\nPeabody\npeace\npeaceable\npeaceful\npeacemake\npeacetime\npeach\nPeachtree\npeacock\npeafowl\npeahen\npeak\npeaky\npeal\nPeale\npeanut\npear\nPearce\npearl\npearlite\npearlstone\nPearson\npeasant\nPease\npeat\npebble\npecan\npeccary\npeck\nPecos\npectoral\npectoralis\npeculate\npeculiar\npecuniary\npedagogic\npedagogue\npedagogy\npedal\npedant\npedantic\npedantry\npeddle\npedestal\npedestrian\npediatric\npediatrician\npedigree\npediment\nPedro\npee\npeek\npeel\npeep\npeephole\npeepy\npeer\npeg\nPegasus\npegboard\npegging\nPeggy\npejorative\nPeking\npelagic\nPelham\npelican\npellagra\npellet\npellucid\nPeloponnese\npelt\npeltry\npelvic\npelvis\nPembroke\npemmican\npen\npenal\npenalty\npenance\npenates\npence\npenchant\npencil\npencilled\npend\npendant\npendulous\npendulum\nPenelope\npenetrable\npenetrate\npenguin\nPenh\npenicillin\npeninsula\npeninsular\npenis\npenitent\npenitential\npenitentiary\npenman\npenmen\nPenn\npenna\npennant\nPennsylvania\npenny\npennyroyal\nPenrose\nPensacola\npension\npensive\npent\npentagon\npentagonal\npentagram\npentane\nPentateuch\npentatonic\nPentecost\npentecostal\npenthouse\npenultimate\npenumbra\npenumbral\npenurious\npenury\npeon\npeony\npeople\nPeoria\npep\npeppercorn\npeppergrass\npeppermint\npepperoni\npeppery\npeppy\nPepsi\nPepsiCo\npeptide\nper\nperceive\npercent\npercentage\npercentile\npercept\nperceptible\nperception\nperceptive\nperceptual\nperch\nperchance\nperchlorate\nPercival\npercolate\npercussion\npercussive\nPercy\nperdition\nperegrine\nperemptory\nperennial\nPerez\nperfect\nperfectible\nperfidious\nperfidy\nperforate\nperforce\nperform\nperformance\nperfume\nperfumery\nperfunctory\nperfusion\nPergamon\nperhaps\nPericlean\nPericles\nperidotite\nperigee\nperihelion\nperil\nPerilla\nperilous\nperimeter\nperiod\nperiodic\nperipatetic\nperipheral\nperiphery\nperiphrastic\nperiscope\nperish\nperitectic\nperiwinkle\nperjure\nperjury\nperk\nPerkins\nperky\nPerle\npermafrost\npermalloy\npermanent\npermeable\npermeate\nPermian\npermissible\npermission\npermissive\npermit\npermitted\npermitting\npermutation\npermute\npernicious\nperoxide\nperpendicular\nperpetrate\nperpetual\nperpetuate\nperpetuity\nperplex\nperquisite\nPerry\npersecute\npersecution\npersecutory\nPerseid\nPersephone\nPerseus\nperseverant\npersevere\nPershing\nPersia\npersiflage\npersimmon\npersist\npersistent\nperson\npersona\npersonage\npersonal\npersonify\npersonnel\nperspective\nperspicacious\nperspicacity\nperspicuity\nperspicuous\nperspiration\nperspire\npersuade\npersuasion\npersuasive\npert\npertain\nPerth\npertinacious\npertinent\nperturb\nperturbate\nPeru\nperusal\nperuse\nPeruvian\npervade\npervasion\npervasive\nperverse\nperversion\npervert\npessimal\npessimism\npessimist\npessimum\npest\npeste\npesticide\npestilent\npestilential\npestle\npet\npetal\nPete\npeter\nPetersburg\nPetersen\nPeterson\npetiole\npetit\npetite\npetition\npetrel\npetri\npetrify\npetrochemical\npetroglyph\npetrol\npetroleum\npetrology\npetticoat\npetty\npetulant\npetunia\nPeugeot\npew\npewee\npewter\npfennig\nPfizer\npH\nphage\nphagocyte\nphalanger\nphalanges\nphalanx\nphalarope\nphantasm\nphantasy\nphantom\npharmaceutic\npharmacist\npharmacology\npharmacopoeia\npharmacy\nphase\nPh.D\nPhD\npheasant\nPhelps\nphenol\nphenolic\nphenomena\nphenomenal\nphenomenology\nphenomenon\nphenotype\nphenyl\nphenylalanine\npheromone\nphi\nPhil\nPhiladelphia\nphilanthrope\nphilanthropic\nphilanthropy\nphilharmonic\nPhilip\nPhilippine\nPhilistine\nPhillip\nphilodendron\nphilology\nphilosoph\nphilosophic\nphilosophy\nPhipps\nphloem\nphlox\nphobic\nPhobos\nphoebe\nPhoenicia\nphoenix\nphon\nphone\nphoneme\nphonemic\nphonetic\nphonic\nphonograph\nphonology\nphonon\nphony\nphosgene\nphosphate\nphosphide\nphosphine\nphosphite\nphosphor\nphosphoresce\nphosphorescent\nphosphoric\nphosphorous\nphosphorus\nphosphorylate\nphoto\nphotogenic\nphotography\nphotolysis\nphotolytic\nphotometry\nphoton\nphrase\nphrasemake\nphraseology\nphthalate\nphycomycetes\nphyla\nPhyllis\nphylogenetic\nphylogeny\nphylum\nphysic\nphysician\nphysiochemical\nphysiognomy\nphysiology\nphysiotherapist\nphysiotherapy\nphysique\nphytoplankton\npi\npianissimo\npianist\npiano\npianoforte\npiazza\npica\nPicasso\npicayune\nPiccadilly\npiccolo\npick\npickaxe\npickerel\nPickering\npicket\nPickett\nPickford\npickle\nPickman\npickoff\npickup\npicky\npicnic\npicnicked\npicnicker\npicnicking\npicofarad\npicojoule\npicosecond\nPict\npictorial\npicture\npicturesque\npiddle\npidgin\npie\npiece\npiecemeal\npiecewise\nPiedmont\npier\npierce\nPierre\nPierson\npietism\npiety\npiezoelectric\npig\npigeon\npigeonberry\npigeonfoot\npigeonhole\npigging\npiggish\npiggy\npigment\npigmentation\npigpen\npigroot\npigskin\npigtail\npike\nPilate\npile\npilewort\npilfer\npilferage\npilgrim\npilgrimage\npill\npillage\npillar\npillory\npillow\nPillsbury\npiloerection\npilot\npimp\npimple\npin\npinafore\npinball\npincer\npinch\npincushion\npine\npineapple\nPinehurst\nping\npinhead\npinhole\npinion\npink\npinkie\npinkish\npinnacle\npinnate\npinniped\npinochle\npinpoint\npinscher\nPinsky\npint\npintail\npinto\npinwheel\npinxter\npion\npioneer\nPiotr\npious\npip\npipe\npipeline\npipette\npipetting\npipsissewa\npiquant\npique\npiracy\nPiraeus\npirate\npirogue\npirouette\npirouetting\nPiscataway\nPisces\npiss\npistachio\npistol\npistole\npiston\npit\npitch\npitchblende\npitchfork\npitchstone\npiteous\npitfall\npith\npithy\npitiable\npitiful\npitman\nPitney\nPitt\nPittsburgh\nPittsfield\nPittston\npituitary\npity\nPius\npivot\npivotal\npixel\npixy\nPizarro\npizza\npizzicato\nPl\nplacate\nplacater\nplace\nplaceable\nplacebo\nplaceholder\nplacemat\nplacenta\nplacental\nplacid\nplagiarism\nplagiarist\nplagioclase\nplague\nplaguey\nplaid\nplain\nPlainfield\nplaintiff\nplaintive\nplait\nplan\nplanar\nPlanck\nplane\nplaneload\nplanet\nplanetaria\nplanetarium\nplanetary\nplanetesimal\nplanetoid\nplank\nplankton\nplanoconcave\nplanoconvex\nplant\nplantain\nplantation\nplaque\nplasm\nplasma\nplasmid\nplasmon\nplaster\nplastic\nplastisol\nplastron\nplat\nplate\nplateau\nplatelet\nplaten\nplatform\nplatinum\nplatitude\nplatitudinous\nPlato\nplatonic\nPlatonism\nPlatonist\nplatoon\nPlatte\nplatypus\nplaudit\nplausible\nplay\nplaya\nplayback\nplayboy\nplayful\nplayground\nplayhouse\nplaymate\nplayoff\nplaypen\nplayroom\nplaything\nplaytime\nplaywright\nplaywriting\nplaza\nplea\nplead\npleasant\nplease\npleasure\npleat\nplebeian\nplebian\nplebiscite\nplectrum\npledge\nPleiades\nPleistocene\nplenary\nplenipotentiary\nplenitude\nplentiful\nplenty\nplenum\nplethora\npleura\npleural\npleurisy\nPlexiglas\npliable\npliant\nplight\nPliny\nPliocene\nplod\nplop\nplot\nplover\nplow\nplowman\nplowmen\nplowshare\nploy\npluck\nplucky\nplug\nplugboard\npluggable\nplugging\nplum\nplumage\nplumb\nplumbago\nplumbate\nplume\nplummet\nplump\nplunder\nplunge\nplunk\npluperfect\nplural\nplus\nplush\nplushy\nPlutarch\nPluto\npluton\nplutonium\nply\nPlymouth\nplyscore\nplywood\nPM\npneumatic\npneumococcus\npneumonia\nPo\npoach\nPOBox\npocket\npocketbook\npocketful\nPocono\npod\npodge\npodia\npodium\nPoe\npoem\npoesy\npoet\npoetic\npoetry\npogo\npogrom\npoi\npoignant\nPoincare\npoinsettia\npoint\npointwise\npoise\npoison\npoisonous\nPoisson\npoke\npokerface\npol\nPoland\npolar\npolarimeter\nPolaris\npolariscope\npolariton\npolarogram\npolarograph\npolarography\nPolaroid\npolaron\npole\npolecat\npolemic\npolice\npoliceman\npolicemen\npolicewoman\npolicy\npolio\npoliomyelitis\npolis\npolish\nPolitburo\npolite\npolitic\npolitician\npoliticking\npolitico\nPolk\npolka\npolkadot\npoll\nPollard\npollen\npollinate\npollock\npolloi\npollutant\npollute\npollution\nPollux\npollywog\npolo\npolonaise\npolonium\npolopony\npolyandrous\npolyandry\npolygamous\npolygamy\npolygon\npolygonal\npolygynous\npolygyny\npolyhedra\npolyhedral\npolyhedron\nPolyhymnia\npolymer\npolymerase\npolymeric\npolymorph\npolymorphic\nPolynesia\npolynomial\nPolyphemus\npolyphony\npolyploidy\npolysaccharide\npolysemous\npolysemy\npolytechnic\npolytope\npolytypy\npomade\npomegranate\npomelo\npomology\nPomona\npomp\npompadour\npompano\nPompeii\npompey\npompon\npomposity\npompous\nPonce\nPonchartrain\nponcho\npond\nponder\nponderosa\nponderous\npong\npont\nPontiac\npontiff\npontific\npontificate\npontification\npony\npooch\npoodle\npooh\npool\nPoole\npoop\npoor\npop\npope\npopish\npoplar\npoplin\npoppy\npopulace\npopular\npopulate\npopulism\npopulist\npopulous\nporcelain\nporch\nporcine\nporcupine\npore\npork\npornographer\npornography\nporosity\nporous\nporphyry\nporpoise\nporridge\nport\nportage\nportal\nPorte\nportend\nportent\nportentous\nporterhouse\nportfolio\nPortia\nportico\nportland\nportmanteau\nPorto\nportrait\nportraiture\nportray\nportrayal\nPortsmouth\nPortugal\nPortuguese\nportulaca\nposable\npose\nPoseidon\nposeur\nposey\nposh\nposit\nposition\npositive\npositron\nPosner\nposse\nposseman\npossemen\npossess\npossession\npossessive\npossessor\npossible\npossum\npost\npostage\npostal\npostcard\npostcondition\npostdoctoral\nposterior\nposteriori\nposterity\npostfix\npostgraduate\nposthumous\npostlude\npostman\npostmark\npostmaster\npostmen\npostmodern\npostmortem\npostmultiply\npostoperative\npostorder\npostpone\npostposition\npostprocess\npostprocessor\npostscript\npostulate\nposture\npostwar\nposy\npot\npotable\npotash\npotassium\npotato\npotatoes\npotbelly\npotboil\npotent\npotentate\npotential\npotentiometer\npothole\npotion\npotlatch\nPotomac\npotpourri\npotsherd\npottery\nPotts\npouch\nPoughkeepsie\npoultice\npoultry\npounce\npound\npour\npout\npoverty\npow\npowder\npowderpuff\npowdery\nPowell\npower\npowerful\npowerhouse\nPoynting\nppm\nPR\npracticable\npractical\npractice\npractise\npractitioner\nPradesh\nPrado\npraecox\npragmatic\npragmatism\npragmatist\nPrague\nprairie\npraise\npraiseworthy\npraline\npram\nprance\nprank\npraseodymium\nPratt\nPravda\npray\nprayerful\npre\npreach\npreachy\nPrecambrian\nprecarious\nprecedent\nprecept\nprecess\nprecinct\nprecious\nprecipice\nprecipitable\nprecipitate\nprecipitous\nprecise\nprecision\npreclude\nprecocious\nprecocity\npredacious\npredatory\npredecessor\npredicament\npredicate\npredict\npredictor\npredilect\npreempt\npreemption\npreemptive\npreemptor\npreen\nprefab\nprefatory\nprefect\nprefecture\nprefer\npreference\npreferential\npreferred\npreferring\npregnant\nprehensile\nprejudice\npreliminary\nprelude\npremier\npremiere\npremise\npremium\npremonition\nPrentice\nprep\npreparation\npreparative\npreparator\npreparatory\nprepare\npreponderant\npreponderate\npreposterous\nprerogative\nPresbyterian\nPrescott\nprescription\nprescriptive\npresentation\npreservation\npreside\npresident\npresidential\npress\npressure\nprestidigitate\nprestige\nprestigious\npresto\nPreston\npresume\npresumption\npresumptive\npretentious\nPretoria\npretty\nprevail\nprevalent\nprevention\npreventive\nprevious\nprexy\nprey\nPriam\nprice\nprick\nprickle\npride\npriest\npriestess\nPriestley\nprig\npriggish\nprim\nprima\nprimacy\nprimal\nprimary\nprimate\nprime\nprimeval\nprimitive\nprimordial\nprimp\nprimrose\nprince\nprincess\nPrinceton\nprincipal\nPrincipia\nprinciple\nprint\nprintmake\nprintout\nprior\npriori\npriory\nPriscilla\nprism\nprismatic\nprison\nprissy\npristine\nPritchard\nprivacy\nprivate\nprivet\nprivilege\nprivy\nprize\nprizewinning\npro\nprobabilist\nprobate\nprobationary\nprobe\nproblem\nproblematic\nprobosces\nproboscis\nprocaine\nprocedural\nprocedure\nproceed\nprocess\nprocession\nprocessor\nproclaim\nproclamation\nproclivity\nprocrastinate\nprocreate\nprocrustean\nProcrustes\nProcter\nproctor\nprocure\nProcyon\nprod\nprodigal\nprodigious\nprodigy\nproduce\nproducible\nproduct\nProf\nprofane\nprofess\nprofession\nprofessor\nprofessorial\nproffer\nproficient\nprofile\nprofit\nprofiteer\nprofligate\nprofound\nprofundity\nprofuse\nprofusion\nprogenitor\nprogeny\nprognosis\nprognosticate\nprogrammable\nprogrammatic\nprogrammed\nprogrammer\nprogramming\nprogress\nprogression\nprogressive\nprohibit\nprohibition\nprohibitive\nprohibitory\nproject\nprojectile\nprojector\nprokaryote\nprokaryotic\nProkofieff\nprolate\nproletariat\nproliferate\nprolific\nproline\nprolix\nprologue\nprolong\nprolongate\nprolusion\nprom\npromenade\nPromethean\nPrometheus\npromethium\nprominent\npromiscuity\npromiscuous\npromise\npromote\npromotion\nprompt\npromptitude\npromulgate\nprone\nprong\npronghorn\npronominal\npronoun\npronounce\npronounceable\npronto\npronunciation\nproof\nproofread\nprop\npropaganda\npropagandist\npropagate\npropane\npropel\npropellant\npropelled\npropeller\npropelling\npropensity\nproper\nproperty\nprophecy\nprophesy\nprophet\nprophetic\npropionate\npropitiate\npropitious\nproponent\nproportion\nproportionate\npropos\nproposal\npropose\nproposition\nproprietary\nproprietor\npropriety\nproprioception\nproprioceptive\npropulsion\npropyl\npropylene\nprorate\nprorogue\nprosaic\nproscenium\nprosciutto\nproscribe\nproscription\nprose\nprosecute\nprosecution\nprosecutor\nproselyte\nProserpine\nprosodic\nprosody\nprosopopoeia\nprospect\nprospector\nprospectus\nprosper\nprosperous\nprostaglandin\nprostate\nprosthetic\nprostitute\nprostitution\nprostrate\nprotactinium\nprotagonist\nprotean\nprotease\nprotect\nprotector\nprotectorate\nprotege\nprotein\nproteolysis\nproteolytic\nprotest\nprotestant\nprotestation\nprothonotary\nProtista\nproto\nprotocol\nproton\nProtophyta\nprotoplasm\nprotoplasmic\nprototype\nprototypic\nProtozoa\nprotozoan\nprotract\nprotractor\nprotrude\nprotrusion\nprotrusive\nprotuberant\nproud\nProust\nprove\nproven\nprovenance\nProvence\nproverb\nproverbial\nprovide\nprovident\nprovidential\nprovince\nprovincial\nprovision\nproviso\nprovocateur\nprovocation\nprovocative\nprovoke\nprovost\nprow\nprowess\nprowl\nproximal\nproximate\nproximity\nproxy\nprude\nprudent\nprudential\nprudish\nprune\nprurient\nPrussia\nprussic\npry\np's\npsalm\npsalter\npseudo\npseudonym\npseudonymous\npsi\npsych\npsyche\npsychiatric\npsychiatrist\npsychiatry\npsychic\npsycho\npsychoacoustic\npsychoanalysis\npsychoanalyst\npsychoanalytic\npsychobiology\npsychology\npsychometry\npsychopath\npsychopathic\npsychophysic\npsychophysiology\npsychopomp\npsychoses\npsychosis\npsychosomatic\npsychotherapeutic\npsychotherapist\npsychotherapy\npsychotic\npsyllium\nPTA\nptarmigan\npterodactyl\nPtolemaic\nPtolemy\npub\npuberty\npubescent\npublic\npublication\npublish\nPuccini\npuck\npuckish\npudding\npuddingstone\npuddle\npuddly\npueblo\npuerile\nPuerto\npuff\npuffball\npuffery\npuffin\npuffy\npug\nPugh\npuissant\npuke\nPulaski\nPulitzer\npull\npullback\npulley\nPullman\npullover\npulmonary\npulp\npulpit\npulsar\npulsate\npulse\npulverable\npuma\npumice\npummel\npump\npumpkin\npumpkinseed\npun\npunch\npunctilio\npunctilious\npunctual\npunctuate\npuncture\npundit\npunditry\npungent\nPunic\npunish\npunitive\nPunjab\nPunjabi\npunk\npunky\npunster\npunt\npuny\npup\npupa\npupae\npupal\npupate\npupil\npuppet\npuppeteer\npuppy\npuppyish\nPurcell\npurchasable\npurchase\nPurdue\npure\npuree\npurgation\npurgative\npurgatory\npurge\npurify\nPurina\npurine\nPuritan\npuritanic\npurl\npurloin\npurple\npurport\npurpose\npurposeful\npurposive\npurr\npurse\npurslane\npursuant\npursue\npursuit\npurvey\npurveyor\npurview\npus\nPusan\nPusey\npush\npushbutton\npushout\npushover\npushpin\npushy\npussy\npussycat\nput\nputative\nputdown\nPutnam\nputrefaction\nputrefy\nputrid\nputt\nputty\npuzzle\nPVC\nPygmalion\npygmy\npyknotic\nPyle\nPyongyang\npyracanth\npyramid\npyramidal\npyre\nPyrex\npyridine\npyridoxine\npyrimidine\npyrite\npyroelectric\npyrolyse\npyrolysis\npyrometer\npyrophosphate\npyrotechnic\npyroxene\npyroxenite\nPyrrhic\nPythagoras\nPythagorean\npython\nq\nQatar\nQED\nq's\nqua\nquack\nquackery\nquad\nquadrangle\nquadrangular\nquadrant\nquadratic\nquadrature\nquadrennial\nquadric\nquadriceps\nquadrilateral\nquadrille\nquadrillion\nquadripartite\nquadrivium\nquadrupedal\nquadruple\nquadruplet\nquadrupole\nquaff\nquagmire\nquahog\nquail\nquaint\nquake\nQuakeress\nqualify\nqualitative\nquality\nqualm\nquandary\nquanta\nQuantico\nquantify\nquantile\nquantitative\nquantity\nquantum\nquarantine\nquark\nquarrel\nquarrelsome\nquarry\nquarryman\nquarrymen\nquart\nquarterback\nquartermaster\nquartet\nquartic\nquartile\nquarto\nquartz\nquartzite\nquasar\nquash\nquasi\nquasiparticle\nquaternary\nquatrain\nquaver\nquay\nqueasy\nQuebec\nqueen\nQueensland\nqueer\nquell\nquench\nquern\nquerulous\nquery\nquest\nquestion\nquestionnaire\nquetzal\nqueue\nqueueing\nQuezon\nquibble\nQuichua\nquick\nquicken\nquickie\nquicklime\nquicksand\nquicksilver\nquickstep\nquid\nquiescent\nquiet\nquietus\nquill\nquillwort\nquilt\nquince\nquinine\nQuinn\nquint\nquintessence\nquintessential\nquintet\nquintic\nquintillion\nquintuplet\nquintus\nquip\nquipped\nquipping\nQuirinal\nquirk\nquirky\nquirt\nquit\nquite\nQuito\nquitter\nquitting\nquiver\nQuixote\nquixotic\nquiz\nquizzed\nquizzes\nquizzical\nquizzing\nquo\nquod\nquonset\nquorum\nquota\nquotation\nquote\nquotient\nr\nrabat\nrabbet\nrabbi\nrabbinate\nrabbinical\nrabbit\nrabble\nrabid\nrabies\nRabin\nraccoon\nrace\nracemose\nracetrack\nraceway\nRachel\nRachmaninoff\nracial\nrack\nracket\nracketeer\nrackety\nracy\nradar\nRadcliffe\nradial\nradian\nradiant\nradiate\nradical\nradices\nradii\nradio\nradioactive\nradioastronomy\nradiocarbon\nradiochemical\nradiochemistry\nradiography\nradiology\nradiometer\nradiophysics\nradiosonde\nradiotherapy\nradish\nradium\nradius\nradix\nradon\nRae\nRafael\nRafferty\nraffia\nraffish\nraft\nrag\nrage\nragging\nragout\nRagusan\nragweed\nraid\nrail\nrailbird\nrailhead\nraillery\nrailroad\nrailway\nrain\nrainbow\nraincoat\nraindrop\nrainfall\nrainstorm\nrainwater\nrainy\nraise\nraisin\nraj\nrajah\nrake\nrakish\nRaleigh\nrally\nRalph\nRalston\nram\nRamada\nRaman\nramble\nrambunctious\nramify\nRamo\nramp\nrampage\nrampant\nrampart\nramrod\nRamsey\nramshackle\nran\nranch\nrancho\nrancid\nrancorous\nRand\nRandall\nRandolph\nrandom\nrandy\nrang\nrange\nrangeland\nRangoon\nrangy\nRanier\nrank\nRankin\nRankine\nrankle\nransack\nransom\nrant\nRaoul\nrap\nrapacious\nrapacity\nrape\nRaphael\nrapid\nrapier\nrapport\nrapprochement\nrapt\nraptor\nraptorial\nrapture\nrare\nrarefy\nRaritan\nrasa\nrascal\nrash\nRasmussen\nrasp\nraspberry\nraster\nRastus\nrat\nrata\nrate\nrater\nrather\nratify\nratio\nratiocinate\nrationale\nrattail\nrattle\nrattlesnake\nraucous\nRaul\nraunchy\nravage\nrave\nravel\nraven\nravenous\nravine\nravish\nraw\nrawboned\nrawhide\nRawlinson\nray\nRayleigh\nRaymond\nRaytheon\nraze\nrazor\nrazorback\nRCA\nR&D\nRd\nre\nreach\nreactant\nreactionary\nread\nreadout\nready\nReagan\nreal\nrealm\nrealtor\nrealty\nream\nreap\nrear\nreason\nreave\nreb\nRebecca\nrebel\nrebellion\nrebellious\nrebuke\nrebuttal\nrecalcitrant\nreceipt\nreceive\nreceptacle\nreception\nreceptive\nreceptor\nrecess\nrecessive\nrecherche\nRecife\nrecipe\nrecipient\nreciprocal\nreciprocate\nreciprocity\nrecital\nrecitative\nreck\nreckon\nreclamation\nrecline\nrecluse\nreclusive\nrecompense\nreconcile\nrecondite\nreconnaissance\nrecovery\nrecriminate\nrecrudescent\nrecruit\nrectangle\nrectangular\nrectifier\nrectify\nrectilinear\nrectitude\nrector\nrectory\nrecumbent\nrecuperate\nrecursion\nrecusant\nrecuse\nred\nredact\nredactor\nredbird\nredbud\nredcoat\nredden\nreddish\nredemption\nredemptive\nredhead\nRedmond\nredneck\nredolent\nredound\nredpoll\nredshank\nredstart\nRedstone\nredtop\nreduce\nreducible\nreductio\nredundant\nredwood\nreed\nreedbuck\nreedy\nreef\nreek\nreel\nReese\nrefectory\nrefer\nreferee\nrefereeing\nreferenda\nreferendum\nreferent\nreferential\nreferral\nreferred\nreferring\nreflect\nreflectance\nreflector\nreflexive\nreformatory\nrefract\nrefractometer\nrefractory\nrefrain\nrefrigerate\nrefuge\nrefugee\nrefusal\nrefutation\nrefute\nregal\nregalia\nregard\nregatta\nregent\nregime\nregimen\nregiment\nregimentation\nRegina\nReginald\nregion\nRegis\nregistrable\nregistrant\nregistrar\nregistration\nregistry\nregress\nregression\nregressive\nregret\nregretful\nregrettable\nregretted\nregretting\nregular\nregulate\nregulatory\nRegulus\nregurgitate\nrehabilitate\nrehearsal\nReich\nReid\nreign\nReilly\nreimbursable\nreimburse\nrein\nreindeer\nreinforce\nReinhold\nreinstate\nreject\nrejoice\nrejoinder\nrelaxation\nreleasable\nrelevant\nreliant\nrelic\nrelict\nrelief\nrelieve\nreligion\nreligiosity\nreligious\nrelinquish\nreliquary\nrelish\nreluctant\nremainder\nremand\nRembrandt\nremediable\nremedy\nremembrance\nRemington\nreminisce\nreminiscent\nremit\nremittance\nremnant\nremonstrate\nremorse\nremorseful\nremote\nremoval\nremunerate\nRena\nrenaissance\nrenal\nRenault\nrend\nrender\nrendezvous\nrendition\nRene\nrenewal\nrennet\nRenoir\nrenounce\nrenovate\nrenown\nRensselaer\nrent\nrental\nrenunciate\nrep\nrepairman\nrepairmen\nreparation\nrepartee\nrepeater\nrepel\nrepelled\nrepellent\nrepelling\nrepentant\nrepertoire\nrepertory\nrepetitious\nrepetitive\nreplenish\nreplete\nreplica\nreplicate\nreportorial\nrepository\nreprehensible\nrepresentative\nrepression\nrepressive\nreprieve\nreprimand\nreprisal\nreprise\nreproach\nreptile\nreptilian\nrepublican\nrepudiate\nrepugnant\nrepulsion\nrepulsive\nreputation\nrepute\nrequire\nrequisite\nrequisition\nrescind\nrescue\nresemblant\nresemble\nresentful\nreserpine\nreservation\nreservoir\nresident\nresidential\nresidual\nresiduary\nresidue\nresiduum\nresignation\nresilient\nresiny\nresist\nresistant\nresistible\nresistive\nresistor\nresonate\nresorcinol\nresourceful\nrespect\nrespectful\nrespiration\nrespirator\nrespiratory\nresplendent\nrespond\nrespondent\nresponse\nresponsible\nresponsive\nrest\nrestaurant\nrestaurateur\nrestful\nrestitution\nrestive\nrestoration\nrestorative\nrestraint\nrestroom\nresult\nresultant\nresume\nresumption\nresurgent\nresurrect\nresuscitate\nret\nretain\nretaliate\nretaliatory\nretard\nretardant\nretardation\nretch\nretention\nretentive\nreticent\nreticulate\nreticulum\nretina\nretinal\nretinue\nretiree\nretribution\nretrieval\nretrieve\nretroactive\nretrofit\nretrofitted\nretrofitting\nretrograde\nretrogress\nretrogressive\nretrorocket\nretrospect\nretrovision\nreturnee\nReub\nReuben\nReuters\nrev\nrevel\nrevelation\nrevelatory\nrevelry\nrevenge\nrevenue\nrever\nreverberate\nrevere\nreverend\nreverent\nreverie\nreversal\nreversible\nrevert\nrevisable\nrevisal\nrevival\nrevive\nrevocable\nrevoke\nrevolution\nrevolutionary\nrevolve\nrevulsion\nrevved\nrevving\nRex\nReykjavik\nReynolds\nrhapsodic\nrhapsody\nRhea\nRhenish\nrhenium\nrheology\nrheostat\nrhesus\nrhetoric\nrhetorician\nrheum\nrheumatic\nrheumatism\nRhine\nrhinestone\nrhino\nrhinoceros\nrhizome\nrho\nRhoda\nRhode\nRhodes\nRhodesia\nrhodium\nrhododendron\nrhodolite\nrhodonite\nrhombi\nrhombic\nrhombus\nrhubarb\nrhyme\nrhythm\nrhythmic\nRI\nrib\nribald\nribbon\nriboflavin\nribonucleic\nribose\nribosome\nRica\nrice\nrich\nRichard\nRichardson\nRichfield\nRichmond\nRichter\nrick\nrickets\nRickettsia\nrickety\nrickshaw\nRico\nricochet\nricotta\nrid\nriddance\nridden\nriddle\nride\nridge\nridgepole\nRidgway\nridicule\nridiculous\nRiemann\nRiemannian\nrife\nriffle\nrifle\nrifleman\nriflemen\nrift\nrig\nRiga\nRigel\nrigging\nRiggs\nright\nrighteous\nrightful\nrightmost\nrightward\nrigid\nrigorous\nRiley\nrill\nrilly\nrim\nrime\nrimy\nRinehart\nring\nringlet\nringside\nrink\nrinse\nRio\nRiordan\nriot\nriotous\nrip\nriparian\nripe\nripen\nRipley\nripoff\nripple\nrise\nrisen\nrisible\nrisk\nrisky\nRitchie\nrite\nRitter\nritual\nRitz\nrival\nrivalry\nriven\nriver\nriverbank\nriverfront\nriverine\nriverside\nrivet\nRiviera\nrivulet\nRiyadh\nRNA\nroach\nroad\nroadbed\nroadblock\nroadhouse\nroadrunner\nroadside\nroadster\nroadway\nroam\nroar\nroast\nrob\nrobbery\nrobbin\nrobe\nRobert\nRoberta\nRoberto\nRobertson\nrobin\nRobinson\nrobot\nrobotics\nrobust\nRochester\nrock\nrockabye\nrockaway\nrockbound\nRockefeller\nrocket\nRockford\nRockies\nRockland\nRockwell\nrocky\nrococo\nrod\nrode\nrodent\nrodeo\nRodgers\nRodney\nRodriguez\nroe\nroebuck\nRoentgen\nRoger\nrogue\nroguish\nroil\nroister\nRoland\nrole\nroll\nrollback\nrollick\nRollins\nRoman\nromance\nRomanesque\nRomania\nRomano\nromantic\nRome\nRomeo\nromp\nRomulus\nRon\nRonald\nrondo\nRonnie\nrood\nroof\nrooftop\nrooftree\nrook\nrookie\nrooky\nroom\nroomful\nroommate\nroomy\nRoosevelt\nRooseveltian\nroost\nroot\nrootstock\nrope\nropy\nRosa\nRosalie\nrosary\nrose\nrosebud\nrosebush\nRoseland\nrosemary\nRosen\nRosenberg\nRosenblum\nRosenthal\nRosenzweig\nRosetta\nrosette\nRoss\nroster\nrostrum\nrosy\nrot\nRotarian\nrotary\nrotate\nROTC\nrote\nrotenone\nRoth\nRothschild\nrotogravure\nrotor\nrototill\nrotten\nrotund\nrotunda\nrouge\nrough\nroughcast\nroughen\nroughish\nroughneck\nroughshod\nroulette\nround\nroundabout\nroundhead\nroundhouse\nroundoff\nroundtable\nroundup\nroundworm\nrouse\nRousseau\nroustabout\nrout\nroute\nroutine\nrove\nrow\nrowboat\nrowdy\nRowe\nRowena\nRowland\nRowley\nRoxbury\nRoy\nroyal\nroyalty\nRoyce\nRPM\nr's\nRSVP\nRuanda\nrub\nRubaiyat\nrubbery\nrubbish\nrubble\nrubdown\nRube\nRuben\nrubicund\nrubidium\nRubin\nrubric\nruby\nruckus\nrudder\nruddy\nrude\nrudiment\nrudimentary\nRudolf\nRudolph\nRudy\nRudyard\nrue\nrueful\nruffian\nruffle\nrufous\nRufus\nrug\nruin\nruination\nruinous\nrule\nrum\nRumania\nrumble\nrumen\nRumford\nruminant\nruminate\nrummage\nrummy\nrump\nrumple\nrumpus\nrun\nrunabout\nrunaway\nrundown\nrune\nrung\nRunge\nrunic\nrunneth\nrunny\nRunnymede\nrunoff\nrunt\nrunty\nrunway\nRunyon\nrupee\nrupture\nrural\nruse\nrush\nRushmore\nrusk\nRuss\nRussell\nrusset\nRussia\nRusso\nrussula\nrust\nrustic\nrustle\nrustproof\nrusty\nrut\nrutabaga\nRutgers\nRuth\nruthenium\nRutherford\nruthless\nrutile\nRutland\nRutledge\nrutty\nRwanda\nRyan\nRydberg\nRyder\nrye\ns\nsa\nsabbath\nsabbatical\nSabina\nSabine\nsable\nsabotage\nsabra\nsac\nsaccharine\nsachem\nSachs\nsack\nsacral\nsacrament\nSacramento\nsacred\nsacrifice\nsacrificial\nsacrilege\nsacrilegious\nsacristan\nsacrosanct\nsad\nsadden\nsaddle\nsaddlebag\nSadie\nsadism\nsadist\nSadler\nsafari\nsafe\nsafeguard\nsafekeeping\nsafety\nsaffron\nsag\nsaga\nsagacious\nsagacity\nsage\nsagebrush\nsagging\nSaginaw\nsagittal\nSagittarius\nsago\nsaguaro\nSahara\nsaid\nSaigon\nsail\nsailboat\nsailfish\nsailor\nsaint\nsake\nSal\nsalaam\nsalacious\nsalad\nsalamander\nsalami\nsalary\nsale\nSalem\nSalerno\nsalesgirl\nSalesian\nsaleslady\nsalesman\nsalesmen\nsalesperson\nsalient\nSalina\nsaline\nSalisbury\nSalish\nsaliva\nsalivary\nsalivate\nSalk\nSalle\nsallow\nsally\nsalmon\nsalmonberry\nsalmonella\nsalon\nsaloon\nsaloonkeep\nsalsify\nsalt\nsaltbush\nSalton\nsaltwater\nsalty\nsalubrious\nsalutary\nsalutation\nsalute\nsalutory\nSalvador\nsalvage\nsalvageable\nsalvation\nSalvatore\nsalve\nsalvo\nSam\nsamarium\nsamba\nsame\nSammy\nSamoa\nsamovar\nsample\nSampson\nSamson\nSamuel\nSamuelson\nsamurai\nSan\nSana\nsanatoria\nsanatorium\nSanborn\nSanchez\nSancho\nsanctify\nsanctimonious\nsanction\nsanctity\nsanctuary\nsand\nsandal\nsandalwood\nsandbag\nsandblast\nSandburg\nsanderling\nSanderson\nsandhill\nSandia\nsandman\nsandpaper\nsandpile\nsandpiper\nSandra\nsandstone\nSandusky\nsandwich\nsandy\nsane\nSanford\nsang\nsangaree\nsanguinary\nsanguine\nsanguineous\nSanhedrin\nsanicle\nsanitarium\nsanitary\nsanitate\nsank\nsans\nSanskrit\nSanta\nSantayana\nSantiago\nSanto\nSao\nsap\nsapiens\nsapient\nsapling\nsaponify\nsapphire\nSappho\nsappy\nsaprophyte\nsaprophytic\nsapsucker\nSara\nSaracen\nSarah\nSaran\nSarasota\nSaratoga\nsarcasm\nsarcastic\nsarcoma\nsarcophagus\nsardine\nSardinia\nsardonic\nSargent\nsari\nsarong\nsarsaparilla\nsarsparilla\nsash\nsashay\nsashimi\nSaskatchewan\nSaskatoon\nsassafras\nsat\nsatan\nsatanic\nsatellite\nsatiable\nsatiate\nsatiety\nsatin\nsatire\nsatiric\nsatisfaction\nsatisfactory\nsatisfy\nsaturable\nsaturate\nsaturater\nSaturday\nSaturn\nSaturnalia\nsaturnine\nsatyr\nsauce\nsaucepan\nsaucy\nSaud\nSaudi\nsauerkraut\nSaul\nSault\nsauna\nSaunders\nsaunter\nsausage\nsaute\nsauterne\nsavage\nsavagery\nsavanna\nSavannah\nsavant\nsave\nSaviour\nSavonarola\nsavoy\nSavoyard\nsavvy\nsaw\nsawbelly\nsawdust\nsawfish\nsawfly\nsawmill\nsawtimber\nsawtooth\nsawyer\nsax\nsaxifrage\nSaxon\nSaxony\nsaxophone\nsay\nSC\nscab\nscabbard\nscabious\nscabrous\nscad\nscaffold\nScala\nscalar\nscald\nscale\nscallop\nscalp\nscaly\nscam\nscamp\nscan\nscandal\nscandalous\nScandinavia\nscandium\nscant\nscanty\nscapegoat\nscapula\nscapular\nscar\nScarborough\nscarce\nscare\nscarecrow\nscarf\nscarface\nscarify\nScarlatti\nscarlet\nscarp\nScarsdale\nscarves\nscary\nscat\nscathe\nscathing\nscatterbrain\nscattergun\nscaup\nscavenge\nscenario\nscene\nscenery\nscenic\nscent\nsceptic\nSchaefer\nSchafer\nSchantz\nschedule\nScheherazade\nschelling\nschema\nschemata\nschematic\nscheme\nSchenectady\nscherzo\nSchiller\nschism\nschist\nschizoid\nschizomycetes\nschizophrenia\nschizophrenic\nSchlesinger\nschlieren\nSchlitz\nSchloss\nSchmidt\nSchmitt\nSchnabel\nschnapps\nSchneider\nSchoenberg\nSchofield\nscholar\nscholastic\nschool\nschoolbook\nschoolboy\nschoolgirl\nschoolgirlish\nschoolhouse\nschoolmarm\nschoolmaster\nschoolmate\nschoolroom\nschoolteacher\nschoolwork\nschoolyard\nschooner\nSchottky\nSchroeder\nSchroedinger\nSchubert\nSchultz\nSchulz\nSchumacher\nSchumann\nSchuster\nSchuyler\nSchuylkill\nSchwab\nSchwartz\nSchweitzer\nSci\nsciatica\nscience\nscientific\nscientist\nscimitar\nscintillate\nscion\nscissor\nsclerosis\nsclerotic\nSCM\nscoff\nscold\nscoop\nscoot\nscope\nscopic\nscops\nscorch\nscore\nscoreboard\nscorecard\nscoria\nscorn\nscornful\nScorpio\nscorpion\nScot\nscotch\nScotia\nScotland\nScotsman\nScotsmen\nScott\nScottish\nScottsdale\nScotty\nscoundrel\nscour\nscourge\nscout\nscowl\nscrabble\nscraggly\nscram\nscramble\nScranton\nscrap\nscrapbook\nscrape\nscrappy\nscratch\nscratchy\nscrawl\nscrawny\nscream\nscreech\nscreechy\nscreed\nscreen\nscreenful\nscreenplay\nscrew\nscrewball\nscrewbean\nscrewdriver\nscrewworm\nscrewy\nscribble\nscribe\nScribners\nscrim\nscrimmage\nScripps\nscript\nscription\nscriptural\nscripture\nscriptwriter\nscriven\nscroll\nscrooge\nscrotum\nscrounge\nscrub\nscrubby\nscruffy\nscrumptious\nscruple\nscrupulosity\nscrupulous\nscrutable\nscrutiny\nscuba\nscud\nscuff\nscuffle\nscull\nsculpin\nsculpt\nsculptor\nsculptural\nsculpture\nscum\nscurrilous\nscurry\nscurvy\nscuttle\nscutum\nScylla\nscythe\nScythia\nSD\nSE\nsea\nseabed\nseaboard\nSeaborg\nseacoast\nseafare\nseafood\nSeagram\nseagull\nseahorse\nseal\nsealant\nseam\nseaman\nseamen\nseamstress\nseamy\nSean\nseance\nseaport\nseaquake\nsear\nsearch\nsearchlight\nseashell\nseashore\nseaside\nseason\nseasonal\nseat\nseater\nSeattle\nseaward\nseawater\nseaweed\nseaworthy\nsebaceous\nSebastian\nsec\nsecant\nsecede\nsecession\nseclude\nseclusion\nsecond\nsecondary\nsecondhand\nsecrecy\nsecret\nsecretarial\nsecretariat\nsecretary\nsecrete\nsecretion\nsecretive\nsect\nsectarian\nsection\nsector\nsecular\nsecure\nsedan\nsedate\nsedentary\nseder\nsedge\nsediment\nsedimentary\nsedimentation\nsedition\nseditious\nseduce\nseduction\nseductive\nsedulous\nsee\nseeable\nseed\nseedbed\nseedling\nseedy\nseeing\nseek\nseem\nseen\nseep\nseepage\nseersucker\nseethe\nseething\nsegment\nsegmentation\nSegovia\nsegregant\nsegregate\nSegundo\nSeidel\nseismic\nseismograph\nseismography\nseismology\nseize\nseizure\nseldom\nselect\nselectman\nselectmen\nselector\nSelectric\nSelena\nselenate\nselenite\nselenium\nself\nselfadjoint\nselfish\nSelfridge\nSelkirk\nsell\nsellout\nSelma\nseltzer\nselves\nSelwyn\nsemantic\nsemaphore\nsemblance\nsemester\nsemi\nseminal\nseminar\nseminarian\nseminary\nSeminole\nSemiramis\nSemite\nSemitic\nsemper\nsen\nsenate\nsenatorial\nsend\nSeneca\nSenegal\nsenescent\nsenile\nsenior\nsenor\nSenora\nsenorita\nsensate\nsense\nsensible\nsensitive\nsensor\nsensory\nsensual\nsensuous\nsent\nsentence\nsentential\nsentient\nsentiment\nsentinel\nsentry\nSeoul\nsepal\nseparable\nseparate\nsepia\nSepoy\nsept\nsepta\nseptate\nSeptember\nseptennial\nseptic\nseptillion\nseptuagenarian\nseptum\nsepulchral\nseq\nsequel\nsequent\nsequential\nsequester\nsequestration\nsequin\nsequitur\nSequoia\nsera\nseraglio\nserape\nseraphim\nSerbia\nserenade\nserendipitous\nserendipity\nserene\nserf\nserge\nsergeant\nSergei\nserial\nseriatim\nsericulture\nseries\nserif\nserine\nserious\nsermon\nserology\nSerpens\nserpent\nserpentine\nserum\nservant\nserve\nservice\nserviceable\nserviceberry\nserviceman\nservicemen\nserviette\nservile\nservitor\nservitude\nservo\nservomechanism\nsesame\nsession\nset\nsetback\nSeth\nSeton\nsetscrew\nsettle\nsetup\nseven\nsevenfold\nseventeen\nseventeenth\nseventh\nseventieth\nseventy\nseventyfold\nsever\nseveral\nseveralfold\nseveralty\nsevere\nSevern\nSeville\nsew\nsewage\nSeward\nsewerage\nsewn\nsex\nSextans\nsextet\nsextic\nsextillion\nsexton\nsextuple\nsextuplet\nsexual\nsexy\nSeychelle\nSeymour\nsforzando\nshabby\nshack\nshackle\nshad\nshadbush\nshade\nshadflower\nshadow\nshadowy\nshady\nShafer\nShaffer\nshaft\nshag\nshagbark\nshagging\nshaggy\nshah\nshake\nshakeable\nshakedown\nshaken\nShakespeare\nShakespearean\nShakespearian\nshako\nshaky\nshale\nshall\nshallot\nshallow\nshalom\nsham\nshaman\nshamble\nshame\nshameface\nshameful\nshampoo\nshamrock\nShanghai\nshank\nShannon\nshan't\nShantung\nshanty\nshape\nShapiro\nshard\nshare\nsharecrop\nsharecropper\nshareholder\nShari\nshark\nSharon\nsharp\nSharpe\nsharpen\nsharpshoot\nShasta\nshatter\nshatterproof\nShattuck\nshave\nshaven\nshaw\nshawl\nShawnee\nshay\nshe\nShea\nsheaf\nshear\nShearer\nsheath\nsheathe\nsheave\nshebang\nshe'd\nshed\nShedir\nSheehan\nsheen\nsheep\nsheepherder\nsheepskin\nsheer\nsheet\nSheffield\nsheik\nSheila\nShelby\nSheldon\nshelf\nshe'll\nshell\nShelley\nshellfish\nshelter\nShelton\nshelve\nShenandoah\nshenanigan\nShepard\nshepherd\nshepherdess\nSheppard\nSheraton\nsherbet\nSheridan\nsheriff\nSherlock\nSherman\nSherrill\nsherry\nSherwin\nSherwood\nshibboleth\nshield\nshift\nshifty\nshill\nShiloh\nshim\nshimmy\nshin\nshinbone\nshine\nshingle\nShinto\nshiny\nship\nshipboard\nshipbuild\nshipbuilding\nshiplap\nShipley\nshipload\nshipman\nshipmate\nshipmen\nshipshape\nshipwreck\nshipyard\nshire\nshirk\nShirley\nshirt\nshirtmake\nshish\nshitepoke\nshiv\nShiva\nshiver\nshivery\nShmuel\nshoal\nshock\nShockley\nshod\nshoddy\nshoe\nshoehorn\nshoelace\nshoemake\nshoestring\nshoji\nshone\nshoo\nshoofly\nshook\nshoot\nshop\nshopkeep\nshopworn\nshore\nshorebird\nshorefront\nshoreline\nshort\nshortage\nshortcake\nshortcoming\nshortcut\nshorten\nshortfall\nshorthand\nshortish\nshortsighted\nshortstop\nShoshone\nshot\nshotbush\nshotgun\nshould\nshoulder\nshouldn't\nshout\nshove\nshovel\nshow\nshowboat\nshowcase\nshowdown\nshowman\nshowmen\nshown\nshowpiece\nshowplace\nshowroom\nshowy\nshrank\nshrapnel\nshred\nShreveport\nshrew\nshrewd\nshrewish\nshriek\nshrift\nshrike\nshrill\nshrilly\nshrimp\nshrine\nshrink\nshrinkage\nshrive\nshrivel\nshroud\nshrove\nshrub\nshrubbery\nshrug\nshrugging\nshrunk\nshrunken\nShu\nshuck\nshudder\nshuddery\nshuffle\nshuffleboard\nShulman\nshun\nshunt\nshut\nshutdown\nshutoff\nshutout\nshuttle\nshuttlecock\nshy\nShylock\nshyly\nsial\nSIAM\nSiamese\nSian\nsib\nSiberia\nsibilant\nSibley\nsibling\nsibyl\nsic\nSicilian\nSicily\nsick\nsickbed\nsicken\nsickish\nsickle\nsicklewort\nsickroom\nside\nsidearm\nsideband\nsideboard\nsidecar\nsidelight\nsideline\nsidelong\nsideman\nsidemen\nsidereal\nsiderite\nsidesaddle\nsideshow\nsidestep\nsidestepped\nsidestepping\nsidetrack\nsidewalk\nsidewall\nsideway\nsidewinder\nsidewise\nsidle\nSidney\nsiege\nSiegel\nSiegfried\nSieglinda\nSiegmund\nSiemens\nSiena\nsienna\nsierra\nsiesta\nsieve\nsift\nsigh\nsight\nsightsee\nsightseeing\nsightseer\nsigma\nSigmund\nsign\nsignal\nsignature\nsignboard\nsignet\nsignificant\nsignify\nSignor\nSignora\nsignpost\nSikh\nSikkim\nSikorsky\nsilage\nsilane\nSilas\nsilent\nsilhouette\nsilica\nsilicate\nsiliceous\nsilicic\nsilicide\nsilicon\nsilicone\nsilicosis\nsilk\nsilken\nsilkworm\nsilky\nsill\nsilly\nsilo\nsilt\nsiltation\nsiltstone\nsilty\nsilver\nSilverman\nsilversmith\nsilverware\nsilvery\nsima\nsimian\nsimilar\nsimile\nsimilitude\nSimla\nsimmer\nSimmons\nSimon\nSimonson\nsimper\nsimple\nsimplectic\nsimpleminded\nsimpleton\nsimplex\nsimplicial\nsimplicity\nsimplify\nsimplistic\nsimply\nSimpson\nSims\nsimulate\nsimulcast\nsimultaneity\nsimultaneous\nsin\nSinai\nSinbad\nsince\nsincere\nSinclair\nsine\nsinew\nsinewy\nsinful\nsing\nsingable\nSingapore\nsinge\nsingle\nsinglehanded\nsingleminded\nsinglet\nsingleton\nsingsong\nsingular\nsinh\nsinister\nsinistral\nsink\nsinkhole\nSino\nSinology\nsinter\nsinuous\nsinus\nsinusoid\nsinusoidal\nSioux\nsip\nsir\nsire\nsiren\nSirius\nsis\nsisal\nsiskin\nsister\nSistine\nSisyphean\nSisyphus\nsit\nsite\nsitu\nsituate\nsitus\nsiva\nsix\nsixfold\nsixgun\nsixteen\nsixteenth\nsixth\nsixtieth\nsixty\nsixtyfold\nsize\nsizzle\nskat\nskate\nskateboard\nskater\nskeet\nskein\nskeleta\nskeletal\nskeleton\nskeptic\nsketch\nsketchbook\nsketchpad\nsketchy\nskew\nski\nskid\nskiddy\nskiff\nskill\nskillet\nskillful\nskim\nskimp\nskimpy\nskin\nskindive\nskinflint\nskinny\nskintight\nskip\nskipjack\nSkippy\nskirmish\nskirt\nskit\nskittle\nSkopje\nskulk\nskull\nskullcap\nskullduggery\nskunk\nsky\nSkye\nskyhook\nskyjack\nskylark\nskylight\nskyline\nskyrocket\nskyscrape\nskyward\nskywave\nskyway\nslab\nslack\nslacken\nsladang\nslag\nslain\nslake\nslam\nslander\nslanderous\nslang\nslant\nslap\nslapdash\nslapstick\nslash\nslat\nslate\nslater\nslaughter\nslaughterhouse\nSlav\nslave\nslavery\nSlavic\nslavish\nSlavonic\nslay\nsleazy\nsled\nsledge\nsledgehammer\nsleek\nsleep\nsleepwalk\nsleepy\nsleet\nsleety\nsleeve\nsleigh\nsleight\nslender\nslept\nsleuth\nslew\nslice\nslick\nslid\nslide\nslight\nslim\nslime\nslimy\nsling\nslingshot\nslink\nslip\nslippage\nslippery\nslipshod\nslit\nslither\nsliver\nslivery\nSloan\nSloane\nslob\nSlocum\nsloe\nslog\nslogan\nsloganeer\nslogging\nsloop\nslop\nslope\nsloppy\nslosh\nslot\nsloth\nslothful\nslouch\nslough\nSlovakia\nsloven\nSlovenia\nslow\nslowdown\nsludge\nslug\nslugging\nsluggish\nsluice\nslum\nslumber\nslump\nslung\nslunk\nslur\nslurp\nslurry\nslush\nslushy\nsly\nsmack\nsmall\nSmalley\nsmallish\nsmallpox\nsmalltime\nsmart\nsmash\nsmattering\nsmear\nsmell\nsmelly\nsmelt\nsmile\nsmirk\nsmite\nsmith\nsmithereens\nSmithfield\nSmithson\nsmithy\nsmitten\nsmog\nsmoke\nsmokehouse\nsmokescreen\nsmokestack\nsmoky\nsmolder\nsmooch\nsmooth\nsmoothbore\nsmote\nsmother\nSmucker\nsmudge\nsmudgy\nsmug\nsmuggle\nsmut\nsmutty\nSmyrna\nSmythe\nsnack\nsnafu\nsnag\nsnagging\nsnail\nsnake\nsnakebird\nsnakebite\nsnakeroot\nsnap\nsnapback\nsnapdragon\nsnappish\nsnappy\nsnapshot\nsnare\nsnark\nsnarl\nsnatch\nsnazzy\nsneak\nsneaky\nsneer\nsneeze\nsnell\nsnick\nSnider\nsniff\nsniffle\nsnifter\nsnigger\nsnip\nsnipe\nsnippet\nsnippy\nsnivel\nsnob\nsnobbery\nsnobbish\nsnook\nsnoop\nsnoopy\nsnore\nsnorkel\nsnort\nsnotty\nsnout\nsnow\nsnowball\nsnowbank\nsnowfall\nsnowflake\nsnowshoe\nsnowstorm\nsnowy\nsnub\nsnuff\nsnuffle\nsnug\nsnuggle\nsnuggly\nSnyder\nso\nsoak\nsoap\nsoapstone\nsoapsud\nsoapy\nsoar\nsob\nsober\nsobriety\nsobriquet\nSoc\nsoccer\nsociable\nsocial\nsocietal\nSociete\nsociety\nsocioeconomic\nsociolinguistic\nsociology\nsociometry\nsock\nsocket\nsockeye\nSocrates\nSocratic\nsod\nsoda\nsodden\nsodium\nsofa\nsoffit\nSofia\nsoft\nsoftball\nsoftcover\nsoften\nsoftware\nsoftwood\nsoggy\nsoignee\nsoil\nsoiree\nsojourn\nSol\nsolace\nsolar\nsold\nsolder\nsoldier\nsoldiery\nsole\nsolecism\nsolemn\nsolenoid\nsolicit\nsolicitation\nsolicitor\nsolicitous\nsolicitude\nsolid\nsolidarity\nsolidify\nsoliloquy\nsolipsism\nsolitary\nsoliton\nsolitude\nsolo\nSolomon\nSolon\nsolstice\nsoluble\nsolute\nsolution\nsolvate\nsolve\nsolvent\nsoma\nsomal\nSomali\nSomalia\nsomatic\nsomber\nsombre\nsome\nsomebody\nsomebody'll\nsomeday\nsomehow\nsomeone\nsomeone'll\nsomeplace\nSomers\nsomersault\nSomerset\nSomerville\nsomething\nsometime\nsomewhat\nsomewhere\nsommelier\nSommerfeld\nsomnolent\nson\nsonant\nsonar\nsonata\nsong\nsongbag\nsongbird\nsongbook\nsongful\nsonic\nsonnet\nsonny\nSonoma\nSonora\nsonorant\nsonority\nsonorous\nSony\nsoon\nsoot\nsooth\nsoothe\nsoothsay\nsoothsayer\nsop\nsophia\nSophie\nsophism\nsophisticate\nsophistry\nSophoclean\nSophocles\nsophomore\nsophomoric\nsoprano\nsora\nsorb\nsorcery\nsordid\nsore\nSorensen\nSorenson\nsorghum\nsorority\nsorption\nsorrel\nsorrow\nsorrowful\nsorry\nsort\nsortie\nsou\nsouffle\nsough\nsought\nsoul\nsoulful\nsound\nsoundproof\nsoup\nsoupy\nsour\nsourberry\nsource\nsourdough\nsourwood\nSousa\nsoutane\nsouth\nSouthampton\nsouthbound\nsoutheast\nsoutheastern\nsouthern\nsouthernmost\nSouthey\nsouthland\nsouthpaw\nsouthward\nsouthwest\nsouthwestern\nsouvenir\nsovereign\nsovereignty\nsoviet\nsovkhoz\nsow\nsowbelly\nsowbug\nsown\nsoy\nsoya\nsoybean\nspa\nspace\nspacecraft\nspacesuit\nspacetime\nspacious\nspade\nspaghetti\nSpain\nspalding\nspan\nspandrel\nspangle\nSpaniard\nspaniel\nSpanish\nspar\nspare\nsparge\nspark\nsparkle\nSparkman\nsparky\nsparling\nsparrow\nsparse\nSparta\nspartan\nspasm\nspasmodic\nspastic\nspat\nspate\nspatial\nspatlum\nspatterdock\nspatula\nSpaulding\nspavin\nspawn\nspay\nspeak\nspeakeasy\nspear\nspearhead\nspearmint\nspec\nspecial\nspeciate\nspecie\nspecies\nspecific\nspecify\nspecimen\nspecious\nspeck\nspeckle\nspectacle\nspectacular\nspectator\nSpector\nspectra\nspectral\nspectrogram\nspectrograph\nspectrography\nspectrometer\nspectrophotometer\nspectroscope\nspectroscopic\nspectroscopy\nspectrum\nspecular\nspeculate\nsped\nspeech\nspeed\nspeedboat\nspeedometer\nspeedup\nspeedwell\nspeedy\nspell\nspellbound\nSpencer\nSpencerian\nspend\nspent\nsperm\nspermatophyte\nspermatozoa\nspermatozoon\nSperry\nspew\nsphagnum\nsphalerite\nsphere\nspheric\nspheroid\nspheroidal\nspherule\nsphinx\nsphygmomanometer\nSpica\nspice\nspicebush\nspicy\nspider\nspiderwort\nspidery\nSpiegel\nspigot\nspike\nspikenard\nspiky\nspill\nspillover\nspilt\nspin\nspinach\nspinal\nspindle\nspindly\nspine\nspinel\nspinnaker\nspinneret\nspinodal\nspinoff\nspinster\nspiny\nspiral\nspire\nspirit\nspiritual\nSpiro\nspirochaete\nSpirogyra\nspit\nspite\nspiteful\nspitfire\nspittle\nspitz\nsplash\nsplashy\nsplat\nsplay\nspleen\nspleenwort\nsplendid\nsplenetic\nsplice\nspline\nsplint\nsplintery\nsplit\nsplotch\nsplotchy\nsplurge\nsplutter\nspoil\nspoilage\nSpokane\nspoke\nspoken\nspokesman\nspokesmen\nspokesperson\nsponge\nspongy\nsponsor\nspontaneity\nspontaneous\nspoof\nspook\nspooky\nspool\nspoon\nspoonful\nsporadic\nspore\nsport\nsportsman\nsportsmen\nsportswear\nsportswriter\nsportswriting\nsporty\nspot\nspotlight\nspotty\nspouse\nspout\nSprague\nsprain\nsprang\nsprawl\nspray\nspread\nspree\nsprig\nsprightly\nspring\nspringboard\nspringe\nSpringfield\nspringtail\nspringtime\nspringy\nsprinkle\nsprint\nsprite\nsprocket\nSproul\nsprout\nspruce\nsprue\nsprung\nspud\nspume\nspumoni\nspun\nspunk\nspunky\nspur\nspurge\nspurious\nspurn\nspurt\nsputnik\nsputter\nspy\nspyglass\nsquabble\nsquad\nsquadron\nsqualid\nsquall\nsquamous\nsquander\nsquare\nsquash\nsquashberry\nsquashy\nsquat\nsquatted\nsquatter\nsquatting\nsquaw\nsquawbush\nsquawk\nsquawroot\nsqueak\nsqueaky\nsqueal\nsqueamish\nsqueegee\nsqueeze\nsquelch\nSquibb\nsquid\nsquill\nsquint\nsquire\nsquirm\nsquirmy\nsquirrel\nsquirt\nsquishy\nSri\ns's\nSSE\nSST\nSSW\nSt\nstab\nstabile\nstable\nstableman\nstablemen\nstaccato\nstack\nStacy\nstadia\nstadium\nstaff\nStafford\nstag\nstage\nstagecoach\nstagnant\nstagnate\nstagy\nStahl\nstaid\nstain\nstair\nstaircase\nstairway\nstairwell\nstake\nstalactite\nstalagmite\nstale\nstalemate\nStaley\nStalin\nstalk\nstall\nstallion\nstalwart\nstamen\nStamford\nstamina\nstaminate\nstammer\nstamp\nstampede\nStan\nstance\nstanch\nstanchion\nstand\nstandard\nstandby\nstandeth\nStandish\nstandoff\nstandpoint\nstandstill\nStanford\nStanhope\nstank\nStanley\nstannic\nstannous\nStanton\nstanza\nstaph\nstaphylococcus\nstaple\nStapleton\nstar\nstarboard\nstarch\nstarchy\nstardom\nstare\nstarfish\nstargaze\nstark\nStarkey\nstarlet\nstarlight\nstarling\nStarr\nstarry\nstart\nstartle\nstartup\nstarvation\nstarve\nstash\nstasis\nstate\nStaten\nstater\nstateroom\nstatesman\nstatesmen\nstatewide\nstatic\nstationarity\nstationary\nstationery\nstationmaster\nstatistician\nStatler\nstator\nstatuary\nstatue\nstatuesque\nstatuette\nstature\nstatus\nstatute\nstatutory\nStauffer\nstaunch\nStaunton\nstave\nstay\nstead\nsteadfast\nsteady\nsteak\nsteal\nstealth\nstealthy\nsteam\nsteamboat\nsteamy\nstearate\nstearic\nStearns\nsteed\nsteel\nSteele\nsteelmake\nsteely\nSteen\nsteep\nsteepen\nsteeple\nsteeplebush\nsteeplechase\nsteer\nsteeve\nStefan\nStegosaurus\nstein\nSteinberg\nSteiner\nstella\nstellar\nstem\nstench\nstencil\nstenographer\nstenography\nstenotype\nstep\nstepchild\nStephanie\nstephanotis\nStephen\nStephenson\nstepmother\nsteppe\nsteprelation\nstepson\nstepwise\nsteradian\nstereo\nstereography\nstereoscopy\nsterile\nsterling\nstern\nsternal\nSternberg\nSterno\nsternum\nsteroid\nstethoscope\nStetson\nSteuben\nSteve\nstevedore\nSteven\nStevenson\nstew\nsteward\nstewardess\nStewart\nstick\nstickle\nstickleback\nstickpin\nsticktight\nsticky\nstiff\nstiffen\nstifle\nstigma\nstigmata\nstile\nstiletto\nstill\nstillbirth\nstillwater\nstilt\nstimulant\nstimulate\nstimulatory\nstimuli\nstimulus\nsting\nstingray\nstingy\nstink\nstinkbug\nstinkpot\nstinky\nstint\nstipend\nstipple\nstipulate\nstir\nStirling\nstirrup\nstitch\nstoat\nstochastic\nstock\nstockade\nstockbroker\nstockholder\nStockholm\nstockpile\nstockroom\nStockton\nstocky\nstodgy\nstoic\nstoichiometry\nstoke\nStokes\nstole\nstolen\nstolid\nstomach\nstomp\nstone\nstonecrop\nStonehenge\nstonewall\nstoneware\nstonewort\nstony\nstood\nstooge\nstool\nstoop\nstop\nstopband\nstopcock\nstopgap\nstopover\nstoppage\nstopwatch\nstorage\nstore\nstorefront\nstorehouse\nstorekeep\nstoreroom\nStorey\nstork\nstorm\nstormbound\nstormy\nstory\nstoryboard\nstoryteller\nstorytelling\nstout\nstove\nstow\nstowage\nstowaway\nstrabismic\nstrabismus\nstraddle\nstrafe\nstraggle\nstraight\nstraightaway\nstraighten\nstraightforward\nstraightway\nstrain\nstrait\nstrand\nstrange\nstrangle\nstrangulate\nstrap\nstrata\nstratagem\nstrategic\nstrategist\nstrategy\nStratford\nstratify\nstratosphere\nstratospheric\nStratton\nstratum\nstratus\nStrauss\nstraw\nstrawberry\nstrawflower\nstray\nstreak\nstream\nstreamline\nstreamside\nstreet\nstreetcar\nstrength\nstrengthen\nstrenuous\nstreptococcus\nstreptomycin\nstress\nstressful\nstretch\nstrewn\nstriate\nstricken\nStrickland\nstrict\nstricture\nstride\nstrident\nstrife\nstrike\nstrikebreak\nstring\nstringent\nstringy\nstrip\nstripe\nstriptease\nstrive\nstriven\nstrobe\nstroboscopic\nstrode\nstroke\nstroll\nStrom\nStromberg\nstrong\nstronghold\nstrongroom\nstrontium\nstrop\nstrophe\nstrove\nstruck\nstructural\nstructure\nstruggle\nstrum\nstrung\nstrut\nstrychnine\nStuart\nstub\nstubble\nstubborn\nstubby\nstucco\nstuck\nstud\nStudebaker\nstudent\nstudio\nstudious\nstudy\nstuff\nstuffy\nstultify\nstumble\nstump\nstumpage\nstumpy\nstun\nstung\nstunk\nstunt\nstupa\nstupefy\nstupendous\nstupid\nstupor\nSturbridge\nsturdy\nsturgeon\nSturm\nstutter\nStuttgart\nStuyvesant\nStygian\nstyle\nstyli\nstylish\nstylites\nstylus\nstymie\nstyrene\nStyrofoam\nStyx\nsuave\nsub\nsubject\nsubjunctive\nsublimate\nsubliminal\nsubmersible\nsubmit\nsubmittal\nsubmitted\nsubmitting\nsubpoena\nsubrogation\nsubservient\nsubsidiary\nsubsidy\nsubsist\nsubsistent\nsubstantial\nsubstantiate\nsubstantive\nsubstituent\nsubstitute\nsubstitution\nsubstitutionary\nsubstrate\nsubsume\nsubterfuge\nsubterranean\nsubtle\nsubtlety\nsubtly\nsubtrahend\nsuburb\nsuburbia\nsubversive\nsubvert\nsucceed\nsuccess\nsuccessful\nsuccession\nsuccessive\nsuccessor\nsuccinct\nsuccubus\nsuccumb\nsuch\nsuck\nsuckle\nsucrose\nsuction\nsud\nSudan\nSudanese\nsudden\nsudorific\nsuds\nsue\nsuet\nsuey\nSuez\nsuffer\nsuffice\nsufficient\nsuffix\nsuffocate\nSuffolk\nsuffrage\nsuffragette\nsuffuse\nsugar\nsugary\nsuggest\nsuggestible\nsuggestion\nsuggestive\nsuicidal\nsuicide\nsuit\nsuitcase\nsuite\nsuitor\nsukiyaki\nsulfa\nsulfanilamide\nsulfate\nsulfide\nsulfite\nsulfonamide\nsulfur\nsulfuric\nsulfurous\nsulk\nsulky\nsullen\nSullivan\nsully\nsulphur\nsultan\nsultry\nsum\nsumac\nSumatra\nSumeria\nsummand\nsummary\nsummate\nsummer\nsummertime\nsummit\nsummitry\nsummon\nSumner\nsumptuous\nSumter\nsun\nsunbeam\nsunbonnet\nsunburn\nsunburnt\nSunday\nsunder\nsundew\nsundial\nsundown\nsundry\nsunfish\nsunflower\nsung\nsunglasses\nsunk\nsunken\nsunlight\nsunlit\nsunny\nSunnyvale\nsunrise\nsunscreen\nsunset\nsunshade\nsunshine\nsunshiny\nsunspot\nsuntan\nsuntanned\nsuntanning\nSUNY\nsup\nsuper\nsuperannuate\nsuperb\nsuperbly\nsupercilious\nsuperficial\nsuperfluity\nsuperfluous\nsuperintendent\nsuperior\nsuperlative\nsuperlunary\nsupernatant\nsupersede\nsuperstition\nsuperstitious\nsupervene\nsupervisory\nsupine\nsupplant\nsupple\nsupplementary\nsupplicant\nsupplicate\nsupply\nsupport\nsupposable\nsuppose\nsupposition\nsuppress\nsuppressible\nsuppression\nsuppressor\nsupra\nsupranational\nsupremacy\nsupreme\nsupremum\nsurah\nsurcease\nsurcharge\nsure\nsurefire\nsurety\nsurf\nsurface\nsurfactant\nsurfeit\nsurge\nsurgeon\nsurgery\nsurgical\nsurjection\nsurjective\nsurly\nsurmise\nsurmount\nsurname\nsurpass\nsurplus\nsurprise\nsurreal\nsurrender\nsurreptitious\nsurrey\nsurrogate\nsurround\nsurtax\nsurtout\nsurveillant\nsurvey\nsurveyor\nsurvival\nsurvive\nsurvivor\nSus\nSusan\nSusanne\nsusceptance\nsusceptible\nsushi\nSusie\nsuspect\nsuspend\nsuspense\nsuspension\nsuspensor\nsuspicion\nsuspicious\nSussex\nsustain\nsustenance\nSutherland\nSutton\nsuture\nSuzanne\nsuzerain\nsuzerainty\nSuzuki\nsvelte\nSvetlana\nSW\nswab\nswabby\nswag\nSwahili\nswain\nswallow\nswallowtail\nswam\nswami\nswamp\nswampland\nswampy\nswan\nswank\nswanky\nSwanson\nswap\nswarm\nswart\nSwarthmore\nSwarthout\nswarthy\nswastika\nswat\nswatch\nswath\nswathe\nsway\nSwaziland\nswear\nsweat\nsweatband\nsweater\nsweatpants\nsweatshirt\nsweatshop\nsweatsocks\nsweaty\nSwede\nSweden\nSwedish\nSweeney\nsweep\nsweepstake\nsweet\nsweetbread\nsweeten\nsweetheart\nsweetie\nsweetish\nswell\nswelt\nswelter\nSwenson\nswept\nswerve\nswidden\nswift\nswig\nswigging\nswill\nswim\nswimsuit\nswindle\nswine\nswing\nswingable\nswingy\nswipe\nswirl\nswirly\nswish\nswishy\nswiss\nswitch\nswitchback\nswitchblade\nswitchboard\nswitchgear\nswitchman\nswitchmen\nSwitzer\nSwitzerland\nswivel\nswizzle\nswollen\nswoop\nsword\nswordfish\nswordplay\nswordtail\nswore\nsworn\nswum\nswung\nsybarite\nSybil\nsycamore\nsycophant\nsycophantic\nSydney\nsyenite\nSykes\nsyllabi\nsyllabic\nsyllabify\nsyllable\nsyllabus\nsyllogism\nsyllogistic\nSylow\nsylvan\nSylvania\nSylvester\nSylvia\nsymbiont\nsymbiosis\nsymbiote\nsymbiotic\nsymbol\nsymbolic\nsymmetry\nsympathetic\nsympathy\nsymphonic\nsymphony\nsymplectic\nsymposia\nsymposium\nsymptom\nsymptomatic\nsynagogue\nsynapse\nsynaptic\nsynchronism\nsynchronous\nsynchrony\nsynchrotron\nsyncopate\nsyndic\nsyndicate\nsyndrome\nsynecdoche\nsynergism\nsynergistic\nsynergy\nSynge\nsynod\nsynonym\nsynonymous\nsynonymy\nsynopses\nsynopsis\nsynoptic\nsyntactic\nsyntax\nsynthesis\nsynthetic\nsyphilis\nsyphilitic\nSyracuse\nSyria\nsyringa\nsyringe\nsyrinx\nsyrup\nsyrupy\nsystem\nsystematic\nsystemic\nsystemwide\nsyzygy\nSzilard\nt\nTA\ntab\ntabernacle\ntable\ntableau\ntableaux\ntablecloth\ntableland\ntablespoon\ntablespoonful\ntablet\ntabletop\ntabloid\ntaboo\ntabu\ntabula\ntabular\ntabulate\ntachinid\ntachometer\ntachyon\ntacit\ntaciturn\nTacitus\ntack\ntackle\ntacky\nTacoma\ntact\ntactful\ntactic\ntactile\ntactual\ntad\ntadpole\ntaffeta\ntaffy\ntaft\ntag\ntagging\nTahiti\nTahoe\ntaiga\ntail\ntailgate\ntaillight\ntailor\ntailspin\ntailwind\ntaint\nTaipei\nTaiwan\ntake\ntaken\ntakeoff\ntakeover\ntalc\ntalcum\ntale\ntalent\ntalisman\ntalismanic\ntalk\ntalkative\ntalkie\ntalky\ntall\nTallahassee\ntallow\ntally\ntallyho\nTalmud\nTalmudic\ntalon\ntalus\ntam\ntamale\ntamarack\ntamarind\ntamarisk\ntambourine\ntame\nTamil\nTammany\ntamp\nTampa\ntampon\ntan\ntanager\nTanaka\nTananarive\ntandem\ntang\nTanganyika\ntangent\ntangential\ntangerine\ntangible\ntangle\ntango\ntangy\ntanh\ntank\ntankard\ntannin\ntansy\ntantalum\nTantalus\ntantamount\nTantric\ntantrum\nTanya\nTanzania\ntao\ntap\ntapa\ntape\ntaper\ntapestry\ntapeworm\ntapioca\ntapir\ntapis\ntappa\ntappet\ntaproot\ntar\ntara\ntarantara\ntarantula\nTarbell\ntardy\ntarget\ntariff\ntarnish\ntaro\ntarpaper\ntarpaulin\ntarpon\ntarry\nTarrytown\ntarsier\ntart\ntartar\nTartary\nTarzan\ntask\ntaskmaster\nTasmania\nTass\ntassel\ntaste\ntasteful\ntasting\ntasty\ntat\ntate\ntater\ntattle\ntattler\ntattletale\ntattoo\ntatty\ntau\ntaught\ntaunt\nTaurus\ntaut\ntautology\ntavern\ntaverna\ntawdry\ntawny\ntax\ntaxa\ntaxation\ntaxi\ntaxicab\ntaxidermist\ntaxidermy\ntaxied\ntaxiway\ntaxon\ntaxonomic\ntaxonomist\ntaxonomy\ntaxpayer\ntaxpaying\nTaylor\ntea\nteacart\nteach\nteacup\nteahouse\nteak\nteakettle\nteakwood\nteal\nteam\nteammate\nteamster\nteamwork\nteapot\ntear\nteardrop\ntearful\ntease\nteasel\nteaspoon\nteaspoonful\nteat\ntech\ntechnetium\ntechnic\ntechnician\nTechnion\ntechnique\ntechnology\ntectonic\ntecum\nTed\nTeddy\ntedious\ntedium\ntee\nteeing\nteem\nteen\nteenage\nteensy\nteet\nteeth\nteethe\nteetotal\nTeflon\nTegucigalpa\nTeheran\nTehran\ntektite\nTektronix\nTel\ntelecommunicate\nteleconference\nTeledyne\nTelefunken\ntelegram\ntelegraph\ntelegraphy\ntelekinesis\ntelemeter\nteleology\nteleost\ntelepathic\ntelepathy\ntelephone\ntelephonic\ntelephony\ntelephoto\ntelephotography\nteleprinter\nteleprocessing\nteleprompter\ntelescope\ntelescopic\nteletype\nteletypesetting\nteletypewrite\ntelevise\ntelevision\nTelex\ntell\ntelltale\ntellurium\ntemerity\ntemper\ntempera\ntemperance\ntemperate\ntemperature\ntempest\ntempestuous\ntemplate\ntemple\nTempleton\ntempo\ntemporal\ntemporary\ntempt\ntemptation\ntemptress\nten\ntenable\ntenacious\ntenacity\ntenant\ntend\ntendency\ntenderfoot\ntenderhearted\ntenderloin\ntendon\ntenebrous\ntenement\ntenet\ntenfold\nTenneco\nTennessee\nTenney\ntennis\nTennyson\ntenon\ntenor\ntense\ntensile\ntension\ntensor\ntenspot\ntent\ntentacle\ntentative\ntenth\ntenuous\ntenure\ntepee\ntepid\nteratogenic\nteratology\nterbium\ntercel\nTeresa\nterm\ntermcap\nterminable\nterminal\nterminate\ntermini\nterminology\nterminus\ntermite\ntern\nternary\nTerpsichore\nterpsichorean\nTerra\nterrace\nterrain\nterramycin\nterrapin\nTerre\nterrestrial\nterrible\nterrier\nterrific\nterrify\nterritorial\nterritory\nterror\nterry\nterse\ntertiary\nTess\ntessellate\ntest\ntestament\ntestamentary\ntestate\ntestes\ntesticle\ntesticular\ntestify\ntestimonial\ntestimony\ntestosterone\ntesty\ntetanus\ntete\ntether\ntetrachloride\ntetrafluoride\ntetragonal\ntetrahedra\ntetrahedral\ntetrahedron\ntetravalent\nTeutonic\nTEX\nTexaco\nTexan\nTexas\ntext\ntextbook\ntextile\nTextron\ntextual\ntextural\ntexture\nThai\nThailand\nThalia\nthallium\nthallophyte\nthan\nthank\nthankful\nthanksgiving\nthat\nthatch\nthat'd\nthat'll\nthaw\nThayer\nthe\nThea\ntheatric\nThebes\nthee\ntheft\ntheir\ntheism\ntheist\nThelma\nthem\nthematic\ntheme\nthemselves\nthen\nthence\nthenceforth\ntheocracy\ntheocratic\nTheodore\nTheodosian\ntheologian\ntheology\ntheorem\ntheoretic\ntheoretician\ntheorist\ntheory\ntherapeutic\ntherapist\ntherapy\nthere\nthereabouts\nthereafter\nthereat\nthereby\nthere'd\ntherefor\ntherefore\ntherefrom\ntherein\nthere'll\nthereof\nthereon\nTheresa\nthereto\ntheretofore\nthereunder\nthereupon\ntherewith\nthermal\nthermionic\nthermistor\nthermo\nThermofax\nthermophilic\nthermostat\nthesaurus\nthese\ntheses\nTheseus\nthesis\nthespian\nThessalonian\nThessaly\ntheta\nThetis\nthey\nthey'd\nthey'll\nthey're\nthey've\nthiamin\nthick\nthicken\nthicket\nthickish\nthief\nthieves\nthieving\nthigh\nthimble\nthimbleful\nThimbu\nthin\nthine\nthing\nthink\nthinnish\nthiocyanate\nthiouracil\nthird\nthirdhand\nthirst\nthirsty\nthirteen\nthirteenth\nthirtieth\nthirty\nthirtyfold\nthis\nthis'll\nthistle\nthistledown\nthither\nThomas\nThomistic\nThompson\nThomson\nthong\nThor\nthoracic\nthorax\nThoreau\nthoriate\nthorium\nthorn\nThornton\nthorny\nthorough\nthoroughbred\nthoroughfare\nthoroughgoing\nThorpe\nThorstein\nthose\nthou\nthough\nthought\nthoughtful\nthousand\nthousandfold\nthousandth\nThrace\nThracian\nthrall\nthrash\nthread\nthreadbare\nthreat\nthreaten\nthree\nthreefold\nthreesome\nthreonine\nthresh\nthreshold\nthrew\nthrice\nthrift\nthrifty\nthrill\nthrips\nthrive\nthroat\nthroaty\nthrob\nthroes\nthrombosis\nthrone\nthrong\nthrottle\nthrough\nthroughout\nthroughput\nthrow\nthrowback\nthrown\nthrum\nthrush\nthrust\nThruway\nThuban\nthud\nthug\nthuggee\nThule\nthulium\nthumb\nthumbnail\nthumbprint\nthump\nthunder\nthunderclap\nthundercloud\nthunderflower\nthunderous\nthundershower\nthunderstorm\nThurman\nThursday\nthus\nthwack\nthwart\nthy\nthyme\nthymine\nthymus\nthyratron\nthyroglobulin\nthyroid\nthyroidal\nthyronine\nthyrotoxic\nthyroxine\nthyself\nti\nTiber\ntibet\nTibetan\ntibia\ntic\ntick\nticket\ntickle\nticklish\ntid\ntidal\ntidbit\ntide\ntideland\ntidewater\ntidy\ntie\nTientsin\ntier\nTiffany\ntift\ntiger\ntight\ntighten\ntightwad\ntigress\nTigris\ntil\ntilde\ntile\ntill\ntilt\ntilth\nTim\ntimber\ntimberland\ntimbre\ntime\ntimeout\ntimepiece\ntimeshare\ntimetable\ntimeworn\nTimex\ntimid\nTimon\ntimothy\ntin\nTina\ntincture\ntinder\ntine\ntinfoil\ntinge\ntingle\ntinker\ntinkle\ntinny\ntinsel\ntint\ntintype\ntiny\nTioga\ntip\ntipoff\nTipperary\ntipple\ntippy\ntipsy\ntiptoe\ntirade\nTirana\ntire\ntiresome\ntissue\ntit\nTitan\ntitanate\ntitanic\ntitanium\ntithe\ntithing\ntitian\ntitillate\ntitle\ntitmice\ntitmouse\nTito\ntitrate\ntitular\nTitus\ntizzy\nTN\nTNT\nto\ntoad\ntoady\ntoast\ntobacco\nTobago\nToby\ntoccata\ntoday\ntoday'll\nTodd\ntoddle\ntoddy\ntoe\nTOEFL\ntoehold\ntoenail\ntoffee\ntofu\ntog\ntogether\ntogging\ntoggle\nTogo\ntogs\ntoil\ntoilet\ntoilsome\ntokamak\ntoken\nTokyo\ntold\nToledo\ntolerable\ntolerant\ntolerate\ntoll\ntollbooth\ntollgate\ntollhouse\nTolstoy\ntoluene\nTom\ntomahawk\ntomato\ntomatoes\ntomb\ntombstone\ntome\nTomlinson\nTommie\ntommy\ntomography\ntomorrow\nTompkins\nton\ntonal\ntone\ntong\ntongue\nToni\ntonic\ntonight\ntonk\ntonnage\ntonsil\ntonsillitis\ntony\ntoo\ntoodle\ntook\ntool\ntoolkit\ntoolmake\ntoolsmith\ntoot\ntooth\ntoothache\ntoothbrush\ntoothpaste\ntoothpick\ntoothy\ntootle\ntop\ntopaz\ntopcoat\nTopeka\ntopgallant\ntopheavy\ntopic\ntopmost\ntopnotch\ntopocentric\ntopography\ntopology\ntoponym\ntoponymy\ntopple\ntopsoil\nTopsy\ntor\ntorah\ntorch\ntore\ntori\ntorn\ntornado\ntoroid\ntoroidal\nToronto\ntorpedo\ntorpedoes\ntorpid\ntorpor\ntorque\ntorr\nTorrance\ntorrent\ntorrential\ntorrid\ntorsion\ntorso\ntort\ntortoise\ntortoiseshell\ntortuous\ntorture\ntorus\ntory\nToshiba\ntoss\ntot\ntotal\ntotalitarian\ntote\ntotem\ntotemic\ntoto\ntouch\ntouchdown\ntouchstone\ntouchy\ntough\ntour\ntournament\ntousle\ntout\ntow\ntoward\ntowboat\ntowel\ntower\ntowhead\ntowhee\ntown\ntownhouse\nTownsend\ntownsman\ntownsmen\ntoxic\ntoxicology\ntoxin\ntoy\nToyota\ntrace\ntraceable\ntracery\ntrachea\ntracheae\ntrack\ntrackage\ntract\ntractor\nTracy\ntrade\ntrademark\ntradeoff\ntradesman\ntradesmen\ntradition\ntraffic\ntrafficked\ntrafficker\ntrafficking\ntrag\ntragedian\ntragedy\ntragic\ntragicomic\ntrail\ntrailblazer\ntrailblazing\ntrailhead\ntrailside\ntrain\ntrainee\ntrainload\ntrainman\ntrainmen\ntraipse\ntrait\ntraitor\ntraitorous\ntrajectory\ntram\ntrammel\ntramp\ntrample\ntramway\ntrance\ntranquil\ntranquillity\ntrans\ntransact\ntransalpine\ntransatlantic\ntransceiver\ntranscend\ntranscendent\ntranscendental\ntransconductance\ntranscontinental\ntranscribe\ntranscript\ntranscription\ntransducer\ntransduction\ntransect\ntransept\ntransfer\ntransferee\ntransference\ntransferor\ntransferral\ntransferred\ntransferring\ntransfinite\ntransfix\ntransform\ntransformation\ntransfusable\ntransfuse\ntransfusion\ntransgress\ntransgression\ntransgressor\ntransient\ntransistor\ntransit\nTransite\ntransition\ntransitive\ntransitory\ntranslate\ntransliterate\ntranslucent\ntransmissible\ntransmission\ntransmit\ntransmittable\ntransmittal\ntransmittance\ntransmitted\ntransmitter\ntransmitting\ntransmutation\ntransmute\ntransoceanic\ntransom\ntransonic\ntranspacific\ntransparent\ntranspiration\ntranspire\ntransplant\ntransplantation\ntransport\ntransportation\ntransposable\ntranspose\ntransposition\ntransship\ntransshipping\ntransudate\nTransvaal\ntransversal\ntransverse\ntransvestite\nTransylvania\ntrap\ntrapezium\ntrapezoid\ntrapezoidal\ntrash\ntrashy\nTrastevere\ntrauma\ntraumatic\ntravail\ntravel\ntravelogue\ntraversable\ntraversal\ntraverse\ntravertine\ntravesty\nTravis\ntrawl\ntray\ntreacherous\ntreachery\ntread\ntreadle\ntreadmill\ntreason\ntreasonous\ntreasure\ntreasury\ntreat\ntreatise\ntreaty\ntreble\ntree\ntreetop\ntrefoil\ntrek\ntrellis\ntremble\ntremendous\ntremolo\ntremor\ntremulous\ntrench\ntrenchant\ntrencherman\ntrenchermen\ntrend\ntrendy\nTrenton\ntrepidation\ntrespass\ntress\ntrestle\nTrevelyan\ntriable\ntriad\ntrial\ntriangle\ntriangular\ntriangulate\nTriangulum\nTrianon\nTriassic\ntriatomic\ntribal\ntribe\ntribesman\ntribesmen\ntribulate\ntribunal\ntribune\ntributary\ntribute\nTriceratops\nTrichinella\ntrichloroacetic\ntrichloroethane\ntrichrome\ntrick\ntrickery\ntrickle\ntrickster\ntricky\ntrident\ntridiagonal\ntriennial\ntrifle\ntrifluoride\ntrig\ntrigonal\ntrigonometry\ntrigram\ntrilingual\ntrill\ntrillion\ntrillium\ntrilobite\ntrilogy\ntrim\ntrimer\ntrimester\nTrinidad\ntrinitarian\ntrinity\ntrinket\ntrio\ntriode\ntrioxide\ntrip\ntripartite\ntripe\ntriphammer\ntriphenylphosphine\ntriple\ntriplet\nTriplett\ntriplex\ntriplicate\ntriploid\ntriploidy\ntripod\ntripoli\ntriptych\ntrisodium\nTristan\ntristate\ntrisyllable\ntrite\ntritium\ntriton\ntriumph\ntriumphal\ntriumphant\ntriune\ntrivalent\ntrivia\ntrivial\ntrivium\nTrobriand\ntrod\ntrodden\ntroff\ntroglodyte\ntroika\nTrojan\ntroll\ntrolley\ntrollop\ntrombone\ntrompe\ntroop\ntrophic\ntrophy\ntropic\ntropopause\ntroposphere\ntropospheric\ntrot\ntrouble\ntroubleshoot\ntroublesome\ntrough\ntrounce\ntroupe\ntrouser\ntrout\nTroutman\ntroy\ntruant\ntruce\ntruck\ntruckload\ntruculent\ntrudge\nTrudy\ntrue\ntruffle\ntruism\nTruk\ntruly\nTruman\nTrumbull\ntrump\ntrumpery\ntrumpet\ntruncate\ntrundle\ntrunk\ntrunkful\ntruss\ntrust\ntrustee\ntrustful\ntrustworthy\ntrusty\ntruth\ntruthful\nTRW\ntry\ntrypsin\ntrytophan\nt's\ntsar\ntsarina\ntset\ntsunami\nTTL\nTTY\ntty\ntub\ntuba\ntube\ntuberculin\ntuberculosis\ntuberous\ntubular\ntubule\ntuck\nTucson\nTudor\nTuesday\ntuff\ntuft\ntug\ntugboat\ntugging\ntuition\nTulane\ntularemia\ntulip\ntulle\nTulsa\ntum\ntumble\ntumbrel\ntumult\ntumultuous\ntun\ntuna\ntundra\ntune\ntuneful\ntung\ntungstate\ntungsten\ntunic\nTunis\nTunisia\ntunnel\ntupelo\ntuple\nturban\nturbid\nturbidity\nturbinate\nturbine\nturbofan\nturbojet\nturbulent\nturf\nTurin\nTuring\nturk\nturkey\nTurkish\nturmeric\nturmoil\nturn\nturnabout\nturnaround\nturnery\nturnip\nturnkey\nturnoff\nturnout\nturnover\nturnpike\nturnstone\nturntable\nturpentine\nturpitude\nturquoise\nturret\nturtle\nturtleback\nturtleneck\nturvy\nTuscaloosa\nTuscan\nTuscany\nTuscarora\ntusk\nTuskegee\ntussle\ntussock\nTutankhamen\ntutelage\nTutenkhamon\ntutor\ntutorial\nTuttle\ntutu\ntuxedo\nTV\nTVA\nTWA\ntwaddle\ntwain\ntweak\ntweed\ntweedy\ntweeze\ntwelfth\ntwelve\ntwelvefold\ntwentieth\ntwenty\ntwentyfold\ntwice\ntwiddle\ntwig\ntwigging\ntwilight\ntwill\ntwin\ntwine\ntwinge\ntwinkle\ntwirl\ntwirly\ntwist\ntwisty\ntwit\ntwitch\ntwitchy\ntwo\ntwofold\nTwombly\ntwosome\nTWX\nTX\nTyburn\ntycoon\ntying\ntyke\nTyler\ntympanum\ntype\ntypeface\ntypescript\ntypeset\ntypesetter\ntypesetting\ntypewrite\ntypewritten\ntyphoid\nTyphon\ntyphoon\ntyphus\ntypic\ntypify\ntypo\ntypographer\ntypography\ntypology\ntyrannic\ntyrannicide\nTyrannosaurus\ntyranny\ntyrant\ntyrosine\nTyson\nTzeltal\nu\nubiquitous\nubiquity\nUCLA\nUganda\nugh\nugly\nUK\nUkraine\nUkrainian\nUlan\nulcer\nulcerate\nUllman\nulna\nUlster\nulterior\nultimate\nultimatum\nultra\nUlysses\number\numbilical\numbilici\numbilicus\numbra\numbrage\numbrella\numpire\nUN\nun\nunanimity\nunanimous\nunary\nunbeknownst\nunchristian\nuncle\nuncouth\nunction\nunctuous\nunder\nunderclassman\nunderclassmen\nunderivable\nunderived\nunderling\nundulate\nUNESCO\nungulate\nuniaxial\nunicorn\nunidimensional\nunidirectional\nuniform\nunify\nunilateral\nunimodal\nuninominal\nunion\nuniplex\nunipolar\nuniprocessor\nunique\nUniroyal\nunisex\nunison\nunit\nunital\nunitarian\nunitary\nunite\nunity\nUnivac\nunivalent\nunivariate\nuniversal\nuniverse\nUnix\nunkempt\nunruly\nuntil\nunwieldy\nup\nupbeat\nupbraid\nupbring\nupcome\nupdate\nupdraft\nupend\nupgrade\nupheaval\nupheld\nuphill\nuphold\nupholster\nupholstery\nupkeep\nupland\nuplift\nupon\nupperclassman\nupperclassmen\nuppercut\nuppermost\nupraise\nupright\nuprise\nupriver\nuproar\nuproarious\nuproot\nupset\nupsetting\nupshot\nupside\nupsilon\nupslope\nupstage\nupstair\nupstand\nupstart\nupstate\nupstater\nupstream\nupsurge\nupswing\nuptake\nUpton\nuptown\nuptrend\nupturn\nupward\nupwell\nupwind\nuracil\nurania\nuranium\nUranus\nuranyl\nurban\nUrbana\nurbane\nurbanite\nurchin\nUrdu\nurea\nuremia\nurethane\nurethra\nurge\nurgent\nUri\nurinal\nurinary\nurinate\nurine\nUris\nurn\nurology\nUrquhart\nUrsa\nUrsula\nUrsuline\nUruguay\nurushiol\nU.S\nu's\nus\nU.S.A\nUSA\nusable\nUSAF\nusage\nUSC\nUSC&GS\nUSDA\nuse\nuseful\nUSGS\nusher\nUSIA\nUSN\nUSPS\nUSSR\nusual\nusurer\nusurious\nusurp\nusurpation\nusury\nUT\nUtah\nutensil\nuterine\nuterus\nUtica\nutile\nutilitarian\nutility\nutmost\nutopia\nutopian\nUtrecht\nutter\nutterance\nuttermost\nv\nVA\nvacant\nvacate\nvacationland\nvaccinate\nvaccine\nvacillate\nvacua\nvacuo\nvacuolate\nvacuole\nvacuous\nvacuum\nvade\nVaduz\nvagabond\nvagary\nvagina\nvaginal\nvagrant\nvague\nVail\nvain\nvainglorious\nvale\nvaledictorian\nvaledictory\nvalent\nvalentine\nValerie\nValery\nvalet\nvaleur\nValhalla\nvaliant\nvalid\nvalidate\nvaline\nValkyrie\nValletta\nvalley\nValois\nValparaiso\nvaluate\nvalue\nvalve\nvamp\nvampire\nvan\nvanadium\nVance\nVancouver\nvandal\nVandenberg\nVanderbilt\nVanderpoel\nvane\nvanguard\nvanilla\nvanish\nvanity\nvanquish\nvantage\nvariable\nvariac\nVarian\nvariant\nvariate\nvariegate\nvariety\nvarious\nvaristor\nVaritype\nvarnish\nvarsity\nvary\nvascular\nvase\nvasectomy\nvasoconstriction\nVasquez\nvassal\nVassar\nvast\nvat\nVatican\nvaudeville\nVaudois\nVaughan\nVaughn\nvault\nveal\nvector\nvectorial\nVeda\nvee\nveer\nveery\nVega\nvegetable\nvegetarian\nvegetate\nvehement\nvehicle\nvehicular\nveil\nvein\nvelar\nVelasquez\nveldt\nVella\nvellum\nvelocity\nvelours\nvelvet\nvelvety\nvenal\nvend\nvendetta\nvendible\nvendor\nveneer\nvenerable\nvenerate\nvenereal\nVenetian\nvenetian\nVeneto\nVenezuela\nvengeance\nvengeful\nvenial\nVenice\nvenison\nvenom\nvenomous\nvenous\nvent\nventilate\nventral\nventricle\nventriloquism\nventriloquist\nventure\nventuresome\nventuri\nVenus\nVenusian\nVera\nveracious\nveracity\nveranda\nverandah\nverb\nverbal\nverbatim\nverbena\nverbiage\nverbose\nverdant\nVerde\nVerdi\nverdict\nverge\nveridic\nverify\nverisimilitude\nveritable\nverity\nVerlag\nvermeil\nvermiculite\nvermilion\nvermin\nVermont\nvermouth\nVerna\nvernacular\nvernal\nVerne\nvernier\nVernon\nVerona\nVeronica\nversa\nVersailles\nversatec\nversatile\nverse\nversion\nversus\nvertebra\nvertebrae\nvertebral\nvertebrate\nvertex\nvertical\nvertices\nvertigo\nverve\nvery\nvesicular\nvesper\nvessel\nvest\nvestal\nvestibule\nvestige\nvestigial\nvestry\nVesuvius\nvet\nvetch\nveteran\nveterinarian\nveterinary\nveto\nvex\nvexation\nvexatious\nvi\nvia\nviaduct\nvial\nvibrant\nvibrate\nvibrato\nviburnum\nvicar\nvicarious\nvice\nviceroy\nVichy\nvicinal\nvicinity\nvicious\nvicissitude\nVicksburg\nVicky\nvictim\nvictor\nVictoria\nvictorious\nvictory\nvictrola\nvictual\nVida\nvideo\nvideotape\nvie\nVienna\nViennese\nVientiane\nViet\nVietnam\nVietnamese\nview\nviewpoint\nvigil\nvigilant\nvigilante\nvignette\nvigorous\nvii\nviii\nViking\nVikram\nvile\nvilify\nvilla\nvillage\nvillain\nvillainous\nvillein\nvinaigrette\nVincent\nVinci\nvindicate\nvindictive\nvine\nvinegar\nvineyard\nVinson\nvintage\nvintner\nvinyl\nviola\nviolate\nviolent\nviolet\nviolin\nviper\nviral\nVirgil\nvirgin\nvirginal\nVirginia\nVirgo\nvirgule\nvirile\nvirtual\nvirtue\nvirtuosi\nvirtuosity\nvirtuoso\nvirtuous\nvirulent\nvirus\nvisa\nvisage\nviscera\nvisceral\nviscid\nviscoelastic\nviscometer\nviscosity\nviscount\nviscous\nvise\nVishnu\nvisible\nVisigoth\nvision\nvisionary\nvisit\nvisitation\nvisitor\nvisor\nvista\nvisual\nvita\nvitae\nvital\nvitamin\nvitiate\nVito\nvitreous\nvitrify\nvitriol\nvitriolic\nvitro\nviva\nvivace\nvivacious\nvivacity\nVivaldi\nVivian\nvivid\nvivify\nviviparous\nvivisection\nvivo\nvixen\nviz\nVladimir\nVladivostok\nvocable\nvocabularian\nvocabulary\nvocal\nvocalic\nvocate\nvociferous\nvodka\nVogel\nvogue\nvoice\nvoiceband\nvoid\nvolatile\nvolcanic\nvolcanism\nvolcano\nvolcanoes\nvole\nvolition\nVolkswagen\nvolley\nvolleyball\nVolstead\nvolt\nVolta\nvoltage\nvoltaic\nVoltaire\nVolterra\nvoltmeter\nvoluble\nvolume\nvolumetric\nvoluminous\nvoluntary\nvolunteer\nvoluptuous\nVolvo\nvomit\nvon\nvoodoo\nvoracious\nvoracity\nvortex\nvortices\nvorticity\nVoss\nvotary\nvote\nvotive\nvouch\nvouchsafe\nVought\nvow\nvowel\nvoyage\nVreeland\nv's\nvs\nVT\nVulcan\nvulgar\nvulnerable\nvulpine\nvulture\nvying\nw\nWA\nWaals\nWabash\nWAC\nwack\nwacke\nwacky\nWaco\nwad\nwaddle\nwade\nwadi\nWadsworth\nwafer\nwaffle\nwag\nwage\nwagging\nwaggle\nWagner\nwagoneer\nwagonload\nwah\nWahl\nwail\nwainscot\nWainwright\nwaist\nwaistcoat\nwaistline\nwait\nWaite\nwaitress\nwaive\nwake\nWakefield\nwakeful\nwaken\nwakerobin\nwakeup\nWalcott\nWalden\nWaldo\nWaldorf\nWaldron\nwale\nWalgreen\nwalk\nwalkie\nwalkout\nwalkover\nwalkway\nwall\nwalla\nwallaby\nWallace\nwallboard\nWaller\nwallet\nWallis\nwallop\nwallow\nwallpaper\nwally\nwalnut\nWalpole\nwalrus\nWalsh\nWalt\nWalter\nWaltham\nWalton\nwaltz\nwan\nwand\nwander\nwane\nWang\nwangle\nwant\nwanton\nwapato\nwapiti\nWappinger\nwar\nwarble\nWarburton\nward\nwarden\nwardrobe\nwardroom\nware\nwarehouse\nwarehouseman\nwarehousemen\nwarfare\nwarhead\nWaring\nwarm\nwarmhearted\nwarmish\nwarmonger\nwarmth\nwarmup\nwarn\nwarp\nwarplane\nwarrant\nwarranty\nwarren\nwarrior\nWarsaw\nwart\nwartime\nwarty\nWarwick\nwary\nwas\nwash\nwashbasin\nwashboard\nwashbowl\nWashburn\nWashington\nwashout\nwashy\nwasn't\nwasp\nwaspish\nWasserman\nwast\nwastage\nwaste\nwastebasket\nwasteful\nwasteland\nwastewater\nwasting\nwastrel\nWatanabe\nwatch\nwatchband\nwatchdog\nwatchful\nwatchmake\nwatchman\nwatchmen\nwatchword\nwatchworks\nwater\nWaterbury\nwatercourse\nwatercress\nwaterfall\nwaterfowl\nwaterfront\nWatergate\nwaterhole\nWaterhouse\nwaterline\nWaterloo\nWaterman\nwatermelon\nwaterproof\nwatershed\nwaterside\nwatertight\nWatertown\nwaterway\nwatery\nWatkins\nWatson\nwatt\nwattage\nwattle\nwave\nwaveform\nwavefront\nwaveguide\nwavelength\nwavenumber\nwavy\nwax\nwaxen\nwaxwing\nwaxwork\nwaxy\nway\nwaybill\nwaylaid\nwaylay\nWayne\nwayside\nwayward\nwe\nweak\nweaken\nweal\nwealth\nwealthy\nwean\nweapon\nweaponry\nwear\nwearisome\nweary\nweasel\nweather\nweatherbeaten\nweatherproof\nweatherstrip\nweatherstripping\nweave\nweb\nWebb\nweber\nWebster\nWECo\nwe'd\nwed\nwedge\nwedlock\nWednesday\nwee\nweed\nweedy\nweek\nweekday\nweekend\nweep\nWehr\nWei\nWeierstrass\nweigh\nweight\nweighty\nWeinberg\nWeinstein\nweir\nweird\nWeiss\nWelch\nwelcome\nweld\nWeldon\nwelfare\nwe'll\nwell\nwellbeing\nWeller\nWelles\nWellesley\nwellington\nwellwisher\nwelsh\nwelt\nWendell\nWendy\nwent\nwept\nwe're\nwere\nweren't\nWerner\nwert\nWerther\nWesley\nWesleyan\nwest\nwestbound\nWestchester\nwesterly\nwestern\nwesternmost\nWestfield\nWestinghouse\nWestminster\nWeston\nwestward\nwet\nwetland\nwe've\nWeyerhauser\nwhack\nwhale\nwhalebone\nWhalen\nwham\nwharf\nWharton\nwharves\nwhat\nwhat'd\nwhatever\nWhatley\nwhatnot\nwhat're\nwhatsoever\nwheat\nWheatstone\nwhee\nwheedle\nwheel\nwheelbarrow\nwheelbase\nwheelchair\nwheelhouse\nwheeze\nwheezy\nWhelan\nwhelk\nWheller\nwhelm\nwhelp\nwhen\nwhence\nwhenever\nwhere\nwhereabout\nwhereas\nwhereby\nwhere'd\nwherefore\nwherein\nwhereof\nwhereon\nwhere're\nwheresoever\nwhereupon\nwherever\nwherewith\nwhet\nwhether\nwhey\nwhich\nwhichever\nwhiff\nwhig\nwhile\nwhim\nwhimper\nwhimsey\nwhimsic\nwhimsy\nwhine\nwhinny\nwhip\nwhiplash\nWhippany\nwhippet\nWhipple\nwhipsaw\nwhir\nwhirl\nwhirligig\nwhirlpool\nwhirlwind\nwhisk\nwhisper\nwhistle\nwhistleable\nwhit\nWhitaker\nWhitcomb\nwhite\nwhiteface\nWhitehall\nwhitehead\nWhitehorse\nwhiten\nwhitetail\nwhitewash\nwhither\nwhitish\nWhitlock\nWhitman\nWhitney\nWhittaker\nWhittier\nwhittle\nwhiz\nwhizzing\nwho\nwhoa\nwho'd\nwhodunit\nwhoever\nwhole\nwholehearted\nwholesale\nwholesome\nwho'll\nwholly\nwhom\nwhomever\nwhomsoever\nwhoop\nwhoopee\nwhoosh\nwhop\nwhore\nwhorl\nwhose\nwhosoever\nwhup\nwhy\nWI\nWichita\nwick\nwicket\nwide\nwiden\nwidespread\nwidgeon\nwidget\nwidow\nwidth\nwidthwise\nwield\nwiener\nWier\nwife\nwig\nwigging\nWiggins\nwiggle\nwiggly\nWightman\nwigmake\nwigwam\nWilbur\nWilcox\nwild\nwildcat\nwildcatter\nwildebeest\nwilderness\nwildfire\nwildflower\nwildlife\nwile\nWiley\nWilfred\nwilful\nWilhelm\nWilhelmina\nWilkes\nWilkie\nWilkins\nWilkinson\nwill\nWilla\nWillard\nwillful\nWilliam\nWilliamsburg\nWilliamson\nWillie\nWillis\nWilloughby\nwillow\nwillowy\nWilma\nWilmington\nWilshire\nWilson\nwilt\nwily\nwin\nwince\nwinch\nWinchester\nwind\nwindbag\nwindblown\nwindbreak\nwindfall\nwindmill\nwindow\nwindowpane\nwindowsill\nwindshield\nWindsor\nwindstorm\nwindsurf\nwindswept\nwindup\nwindward\nwindy\nwine\nwinemake\nwinemaster\nwinery\nwineskin\nWinfield\nwing\nwingback\nwingbeat\nwingman\nwingmen\nwingspan\nwingspread\nwingtip\nWinifred\nwink\nwinkle\nWinnetka\nWinnie\nWinnipeg\nWinnipesaukee\nwinnow\nwino\nWinslow\nwinsome\nWinston\nwinter\nwintergreen\nwintertime\nWinthrop\nwintry\nwiny\nwipe\nwire\nwireman\nwiremen\nwiry\nWisconsin\nwisdom\nwise\nwiseacre\nwisecrack\nwisenheimer\nwish\nwishbone\nwishful\nwishy\nwisp\nwispy\nwistful\nwit\nwitch\nwitchcraft\nwith\nwithal\nwithdraw\nwithdrawal\nwithdrawn\nwithdrew\nwithe\nwither\nwithheld\nwithhold\nwithin\nwithout\nwithstand\nwithstood\nwithy\nwitness\nWitt\nWittgenstein\nwitty\nwive\nwizard\nwobble\nwoe\nwoebegone\nwoeful\nwok\nwoke\nWolcott\nwold\nwolf\nWolfe\nWolff\nWolfgang\nwolfish\nwolve\nwolverine\nwoman\nwomb\nwombat\nwomen\nwon\nwonder\nwonderful\nwonderland\nwondrous\nWong\nwon't\nwont\nwoo\nwood\nWoodard\nWoodbury\nwoodcarver\nwoodchuck\nwoodcock\nwoodcut\nwooden\nwoodgrain\nwoodhen\nwoodland\nWoodlawn\nwoodlot\nwoodpeck\nwoodrow\nwoodruff\nwoodshed\nwoodside\nWoodstock\nwoodward\nwoodwind\nwoodwork\nwoody\nwoodyard\nwool\nwoolgather\nWoolworth\nWooster\nwop\nWorcester\nWorcestershire\nword\nWordsworth\nwordy\nwore\nwork\nworkbench\nworkbook\nworkday\nworkforce\nworkhorse\nworkload\nworkman\nworkmen\nworkout\nworkpiece\nworkplace\nworksheet\nworkshop\nworkspace\nworkstation\nworktable\nworld\nworldwide\nworm\nwormy\nworn\nworrisome\nworry\nworse\nworsen\nworship\nworshipful\nworst\nworth\nWorthington\nworthwhile\nworthy\nWotan\nwould\nwouldn't\nwound\nwove\nwoven\nwow\nwrack\nwraith\nwrangle\nwrap\nwraparound\nwrapup\nwrasse\nwrath\nwrathful\nwreak\nwreath\nwreathe\nwreck\nwreckage\nwren\nwrench\nwrest\nwrestle\nwretch\nwriggle\nwright\nWrigley\nwring\nwrinkle\nwrist\nwristband\nwristwatch\nwrit\nwrite\nwriteup\nwrithe\nwrithing\nwritten\nwrong\nwrongdoer\nwrongdoing\nwrongful\nWronskian\nwrote\nwrought\nwry\nw's\nWu\nWuhan\nWV\nWY\nWyandotte\nWyatt\nWyeth\nWylie\nWyman\nWyner\nwynn\nWyoming\nwysiwyg\nx\nXavier\nxenon\nxenophobia\nxerography\nxerox\nXerxes\nXhosa\nxi\nx's\nxylem\nxylene\nxylophone\ny\nyacht\nyachtsman\nyachtsmen\nyah\nyak\nYakima\nYale\nYalta\nyam\nYamaha\nyang\nyank\nYankee\nYankton\nYaounde\nyap\nyapping\nYaqui\nyard\nyardage\nyardstick\nYarmouth\nyarmulke\nyarn\nyarrow\nYates\nyaw\nyawl\nyawn\nye\nyea\nYeager\nyeah\nyear\nyearbook\nyearn\nyeast\nyeasty\nYeats\nyell\nyellow\nyellowish\nYellowknife\nYellowstone\nyelp\nYemen\nyen\nyeoman\nyeomanry\nyeomen\nyeshiva\nyesterday\nyesteryear\nyet\nyew\nYiddish\nyield\nyin\nyip\nyipping\nYMCA\nyodel\nYoder\nyoga\nyoghurt\nyogi\nyogurt\nyoke\nyokel\nYokohama\nYokuts\nyolk\nyon\nyond\nYonkers\nyore\nYork\nYorkshire\nYorktown\nYosemite\nYost\nyou\nyou'd\nyou'll\nyoung\nyoungish\nyoungster\nYoungstown\nyour\nyou're\nyourself\nyourselves\nyouth\nyouthful\nyou've\nyow\nYpsilanti\ny's\nytterbium\nyttrium\nYucatan\nyucca\nyuck\nYugoslav\nYugoslavia\nyuh\nYuki\nYukon\nyule\nYves\nYvette\nYWCA\nz\nZachary\nzag\nzagging\nZagreb\nZaire\nZambia\nZan\nZanzibar\nzap\nzazen\nzeal\nZealand\nzealot\nzealous\nzebra\nZeiss\nZellerbach\nZen\nzenith\nzero\nzeroes\nzeroth\nzest\nzesty\nzeta\nZeus\nZiegler\nzig\nzigging\nzigzag\nzigzagging\nzilch\nzillion\nZimmerman\nzinc\nzing\nzinnia\nZion\nzip\nzircon\nzirconium\nzither\nzloty\nzodiac\nzodiacal\nZoe\nZomba\nzombie\nzone\nzoo\nzoology\nzoom\nzooplankton\nZorn\nZoroaster\nZoroastrian\nzounds\nz's\nzucchini\nZulu\nZurich\nzygote\n"
  },
  {
    "path": "share/examples/Makefile",
    "content": "# Public Domain.  2023/02/21 - Christopher Hettrick\nTOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nall clean cleandir depend lint tags:\n\ninstall:\n\t${INSTALL} -d ${DESTDIR}/usr/share/examples\n\ttar cf - . | (cd ${DESTDIR}/usr/share/examples && tar xpf -)\n"
  },
  {
    "path": "share/examples/asm/Makefile",
    "content": "\nall:\tashello echo\n\nashello: ashello.o\n\t$(LD) ashello.o -o $@\n\necho:   echo.o\n\t$(LD) $@.o -o $@\n\nclean:\n\trm -f *.o ashello echo *.dis *~\n"
  },
  {
    "path": "share/examples/asm/Makefile-host",
    "content": "TOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS\t\t+= -Werror\nASFLAGS\t\t+= -DCROSS\nASLDFLAGS       = --oformat=elf32-tradlittlemips -N -nostartfiles -T $(TOPSRC)/src/elf32-mips.ld\n\nall:            echo\n\necho:           echo.o\n\t\t${LD} ${ASLDFLAGS} -o $@.elf $@.o\n\t\t${OBJDUMP} -S $@.elf > $@.dis\n\t\t${SIZE} $@.elf\n\t\t${ELF2AOUT} $@.elf $@\n\nclean:\n\t\trm -f *.o *.elf ${MAN} echo *.elf *.dis tags *~\n"
  },
  {
    "path": "share/examples/asm/ashello.S",
    "content": "/*\n * This is an example of MIPS assembly program for RetroBSD.\n *\n * To compile this program, type:\n *  cc -c ashello.S\n *  ld ashello.o -o ashello\n */\n#include <syscall.h>\n\n        .data                               // begin data segment\nhello:  .ascii  \"Hello, assembly world!\\n\"  // a string\n\n        .text                               // begin code segment\n        .globl  start                       // entry point for ld\nstart:\n        li      $a0, 0                      // arg 1: stdout fd\n        la      $a1, hello                  // arg 2: string address\n        li      $a2, 23                     // arg 3: string length\n        syscall SYS_write                   // call the kernel: write()\n        nop                                 // returns here on error\n        nop                                 // skips two words on success\n\n        li      $a0, 0                      // arg 1: exit status\n        syscall SYS_exit                    // call the kernel: exit()\n        // no return\n"
  },
  {
    "path": "share/examples/asm/echo.S",
    "content": "/*\n * This is a standard /bin/echo utility, rewritten in MIPS assembler.\n *\n * To compile this program, type:\n *  cc -c echo.S\n *  ld echo.o -o echo\n *\n * Run as:\n *  ./echo Make love not war\n */\n#include <syscall.h>\n\n        .data                           // begin data segment\neoln:   .ascii  \"\\n\"\nspace:  .ascii  \" \"\n\n        .text                           // begin code segment\nstart:  .globl  start                   // entry point for ld\n\n        //\n        // Program gets three arguments:\n        // argc in $a0 - number of words in command line\n        // argv in $a1 - address of list of pointers to words\n        // env  in $a2 - address of list of pointers to environment variables\n        //\n        addi    $s0, $a0, -1            // argc - 1\n        beq     $s0, $zero, done        // if (argc == 0) goto gone\n        addi    $s1, $a1, 4             // argv + 4\nloop:\n        jal     print                   // print string\n        lw      $a0, 0($s1)             // arg 1: *argv\n\n        addi    $s0, $s0, -1            // --argc\n        la      $a1, eoln               // arg2: newline\n        beq     $s0, $zero, last        // if (argc == 0) goto last\n        li      $a0, 1                  // arg1: stdout\n        la      $a1, space              // arg2: space\nlast:\n        li      $a2, 1                  // arg3: length\n        syscall SYS_write               // call the kernel: write()\n        nop                             // ignore errors\n        nop\n\n        bne     $s0, $zero, loop        // if (argc == 0) goto gone\n        addi    $s1, $s1, 4             // ++argv\ndone:\n        li      $a0, 0                  // arg1: exit status\n        syscall SYS_exit                // call the kernel: exit()\n        // no return\n\nprint:  move    $a1, $a0                // arg2: string\n\n\taddi\t$a2, $a0, 1             // compute length\nstrlen:\n\tlb\t$v0, 0($a0)\t\t// get byte from string\n\tbne\t$v0, $zero, strlen\t// continue if not end\n\taddi\t$a0, $a0, 1\t\t// increment pointer\n\n\tsubu\t$a2, $a0, $a2\t\t// arg3: length\n\n        li      $a0, 1                  // arg1: stdout\n        syscall SYS_write               // call the kernel: write()\n        nop                             // ignore errors\n        nop\n\n        jr      $ra\n        nop\n"
  },
  {
    "path": "share/examples/basic/blkjack.bas",
    "content": "10 rem **************************************\n20 rem *** Play the \"blackjack\" (21) game ***\n30 rem **************************************\n40 dim C(52): m = 1000\n50 rem\n60 rem Create deck of cards and shuffle it\n70 rem\n80 for i=0 to 51: c(i) = i: next i\n90 for i=0 to 51: i1=rnd(52): i2=c(i): c(i)=c(i2): c(i2)=i1: next i\n100 rem\n110 rem Prompt for amount of bet (on this game)\n120 rem\n130 print \"You have\", m, \" dollars\"\n140 input \"How much do you wish to bet?\", b: if b=0 then stop\n150 lif b>m then print \"You don't have enough money\":goto 140\n160 t = 0: d = 0\n170 rem\n180 rem Prompt PLAYER for another card\n190 rem\n200 print \"Total:\", t,:Input \" Another card (Y/N)?\", a$\n210 if a$=\"n\" then 380\n220 lif a$<>\"y\" then print \"Please answer y-Yes or n-No\":goto 200\n230 c = c(d): d = d + 1: gosub 530\n240 c = c % 13: if c > 9 then c = 9\n250 if c > 0 then 300\n260 input \"(1)one or (t)ten ?\", a$\n270 if a$=\"1\" then 300\n280 if a$<>\"t\" then 260\n290 c = 9\n300 t = t + c + 1\n310 if t <= 21 then 200\n320 print \"You went over 21! - you LOSE!\"\n330 m = m - b: if m > 0 then 80\n340 print \"You went BUST!\":end\n350 rem\n360 rem Play DEALER\n370 rem\n380 t1 = 0\n390 c = c(d): d = d + 1: print \"Dealer draws \",: gosub 530\n400 c = c % 13: if c > 9 then c = 9\n410 if c > 0 then 470\n420 if t1 < 10 then 450\n430 if (t1+10) > 23 then 460\n440 if (t1+10) >= t then 450\n450 c = 9\n460 print \"Dealer chooses\", c+1\n470 t1 = t1 + c + 1: print \"Dealer totals\", t1: if t1 < t then 390\n480 lif t1 <= 21 then print \"Dealer wins - You LOSE!\": goto 330\n490 print \"Dealer loses - You WIN!!!\": m = m + b: goto 80\n500 rem\n510 rem Subroutine to display text description of a card\n520 rem\n530 order 590\n540 for a = 0 to c / 13: read a$: next a\n550 order 600\n560 for a = 0 to c % 13: read a1$:next a\n570 print a1$, \" of \", a$\n580 return\n590 data \"Hearts\", \"Diamonds\", \"Clubs\", \"Spades\"\n600 data \"Ace\", \"Two\", \"Three\", \"Four\", \"Five\", \"Six\", \"Seven\"\n610 data \"Eight\", \"Nine\", \"Ten\", \"Jack\", \"Queen\", \"King\"\n"
  },
  {
    "path": "share/examples/basic/hilow.bas",
    "content": "10 rem ****************************\n20 rem *** Play the HI/LOW game ***\n30 rem ****************************\n40 n = rnd(100)\n50 c = 0\n60 input \"Guess a number? \", g\n70 c = c+1\n80 if g=n then 120\n90 if g>n then print \"lower\"\n100 if g<n then print \"higher\"\n110 goto 60\n120 print \"You guessed it in\", c, \" tries!\"\n130 exit\n"
  },
  {
    "path": "share/examples/basic/stars.bas",
    "content": "10 INPUT \"Your name: \", U$\n20 PRINT \"Hello \", U$\n30 INPUT \"How many stars do you want: \", N\n40 S$ = \"\"\n50 FOR I = 1 TO N\n60 S$ = S$ + \"*\"\n70 NEXT I\n80 PRINT S$\n90 INPUT \"Do you want more stars? \", A$\n100 IF A$ = \"\" THEN GOTO 90\n110 IF A$ = \"Y\" THEN GOTO 30\n120 IF A$ = \"y\" THEN GOTO 30\n130 PRINT \"Goodbye \", U$\n140 END\n"
  },
  {
    "path": "share/examples/c/Makefile",
    "content": "CC      = cc\nPROG    = hello stdarg skeleton primelist primesum test1 test2 test3 \\\n          gpio adc rain q8 tetris lcd6\n\nall:    $(PROG)\n\nhello:\thello.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $?\n\nstdarg: stdarg.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $?\n\nskeleton: skeleton.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $?\n\nprimelist: primelist.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $?\n\nprimesum: primesum.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $?\n\ngpio:   gpio.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $?\n\nadc:    adc.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $?\n\nrain:   rain.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $?\n\nq8:     q8.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $?\n\ntetris: tetris.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $?\n\nlcd6:   lcd6.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $?\n\ntest1:\ttest1.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $?\n\ntest2:\ttest2.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $?\n\ntest3:\ttest3.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $?\n\nclean:\n\trm -f *.o *~ $(PROG)\n"
  },
  {
    "path": "share/examples/c/Makefile-host",
    "content": "TOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS\t\t+= -Werror -Wall\n\nall:            chello stdarg lcd6\n\nchello:         chello.o\n\t\t${CC} ${LDFLAGS} -o chello.elf chello.o ${LIBS}\n\t\t${OBJDUMP} -S chello.elf > chello.dis\n\t\t${SIZE} chello.elf\n\t\t${ELF2AOUT} chello.elf $@\n\ntetris:         tetris.o\n\t\t${CC} ${LDFLAGS} -o tetris.elf tetris.o ${LIBS}\n\t\t${OBJDUMP} -S tetris.elf > tetris.dis\n\t\t${SIZE} tetris.elf\n\t\t${ELF2AOUT} tetris.elf $@\n\nlcd6:           lcd6.o\n\t\t${CC} ${LDFLAGS} -o lcd6.elf lcd6.o ${LIBS}\n\t\t${OBJDUMP} -S lcd6.elf > lcd6.dis\n\t\t${SIZE} lcd6.elf\n\t\t${ELF2AOUT} lcd6.elf $@\n\nclean:\n\t\trm -f *.o *.elf ${MAN} chello stdarg lcd6 *.elf *.dis tags *~\n"
  },
  {
    "path": "share/examples/c/adc.c",
    "content": "/*\n * Example of reading ADC data.\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <fcntl.h>\n#include <unistd.h>\n\nchar buf[100];\n\nint main(void)\n{\n    int i, fd, value;\n\n    for (i=0; i<16; i++) {\n        sprintf(buf, \"/dev/adc%d\", i);\n        fd = open(buf, O_RDWR);\n        if (fd < 0) {\n            printf(\"Error: unable to open %s\\n\", buf);\n        } else {\n            if (read(fd, buf, 20) > 0) {\n                value = strtol (buf, 0, 0);\n                printf(\"adc%-2d = %d\\n\", i, value);\n            }\n            close(fd);\n        }\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/c/gpio.c",
    "content": "/*\n * Example of polling general purpose i/o pins.\n */\n#include <stdio.h>\n#include <fcntl.h>\n#include <sys/ioctl.h>\n#include <sys/gpio.h>\n\nint main(void)\n{\n    int fd, pnum, value;\n\n    fd = open (\"/dev/porta\", O_RDWR);\n    if (fd < 0) {\n        perror (\"/dev/porta\");\n        return -1;\n    }\n\n    for (pnum=0; pnum<7; pnum++) {\n        value = ioctl (fd, GPIO_POLL | GPIO_PORT (pnum), 0);\n        if (value < 0)\n            perror (\"GPIO_POLL\");\n        printf (\"port%c = 0x%04x\\n\", pnum + 'A', value);\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/c/hello.c",
    "content": "#include <stdio.h>\n\nint main()\n{\n    printf (\"Hello, C World!\\n\");\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/c/lcd6.c",
    "content": "/*\n * Demo for 6 digit LCD module based on HT1261 controller.\n * Based on example sources from http://www.canton-electronics.com\n *\n * Copyright (C) 2015 Serge Vakulenko\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <stdlib.h>\n#include <stdio.h>\n#include <unistd.h>\n#include <fcntl.h>\n#include <sys/time.h>\n#include <sys/gpio.h>\n\n/*\n * Digits, decimal dots and battery levels:\n *   A     B     C     D     E     F\n *   --    --    --    --    --    --  z\n *  |  |  |  |  |  |  |  |  |  |  |  | y\n *   --    --    --    --    --    --  x\n *  |  |  |  |  |  |  |  |  |  |  |  |\n *   --    --    -- c  -- d  -- e  --\n *\n * Memory map:\n *  Byte 0, bits 0-6    - segments of digit 'F'\n *  Byte 0, bit 7       - decimal dot 'e'\n *  Byte 1, bits 0-6    - segments of digit 'E'\n *  Byte 1, bit 7       - decimal dot 'd'\n *  Byte 2, bits 0-6    - segments of digit 'D'\n *  Byte 2, bit 7       - decimal dot 'c'\n *  Byte 3, bits 0-6    - segments of digit 'C'\n *  Byte 3, bit 7       - battery level 'x'\n *  Byte 4, bits 0-6    - segments of digit 'B'\n *  Byte 4, bit 7       - battery level 'y'\n *  Byte 5, bits 0-6    - segments of digit 'A'\n *  Byte 5, bit 7       - battery level 'z'\n *\n * Segments are mapped to bits 0-6:\n *  --4--\n *  0---5\n *  --1--\n *  2---6\n *  --3--\n */\n\n/*\n * Signal assignment.\n * LED modulee is connected to pins 16,17,18 of Fubarino SD board.\n *\n * Fubarino PIC32  LED module\n * --------------------------\n *  16      RE0    CS\n *  17      RE1    WR\n *  18      RE2    DATA\n */\n#define gpio_cs_clear()     ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, 1 << 0)\n#define gpio_cs_set()       ioctl(gpio, GPIO_PORTE | GPIO_SET,   1 << 0)\n#define gpio_wr_clear()     ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, 1 << 1)\n#define gpio_wr_set()       ioctl(gpio, GPIO_PORTE | GPIO_SET,   1 << 1)\n#define gpio_data_clear()   ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, 1 << 2)\n#define gpio_data_set()     ioctl(gpio, GPIO_PORTE | GPIO_SET,   1 << 2)\n\n/*\n * HT1621 commands\n */\n#define HT_SYS_DIS      0x00    /* Turn off system osc and bias generator */\n#define HT_SYS_EN       0x01    /* Turn on system oscillator */\n#define HT_LCD_OFF      0x02    /* Turn off LCD bias generator */\n#define HT_LCD_ON       0x03    /* Turn on LCD bias generator */\n#define HT_CLOCK_XTAL   0x14    /* Crystal 32kHz */\n#define HT_CLOCK_RC     0x18    /* On-chip RC oscillator 256kHz */\n#define HT_CLOCK_EXT    0x1c    /* External clock */\n#define HT_BIAS_1_3     0x21    /* LCD 1/3 bias option, 2 commons default */\n#define HT_COMMONS_3    0x04    /* 3 commons option */\n#define HT_COMMONS_4    0x08    /* 4 commons option */\n\n/*\n * Mapping of symbols to segments.\n *  0, 1, 2, 3, 4, 5, 6, 7,\n *  8, 9, A, b, C, c, d, E,\n *  F, H, h, L, n, N, o, P,\n *  r, t, U, -,  ,\n */\nconst char char_to_segm[] = {\n    0x7D,   0x60,   0x3E,   0x7A,   0x63,   0x5B,   0x5F,   0x70,\n    0x7F,   0x7B,   0x77,   0x4F,   0x1D,   0x0E,   0x6E,   0x1F,\n    0x17,   0x67,   0x47,   0x0D,   0x46,   0x75,   0x37,   0x06,\n    0x0F,   0x6D,   0x02,   0x00,\n};\n\n/*\n * File descriptor for GPIO driver.\n */\nint gpio;\n\n/*\n * Suspend the process for some amount of milliseconds.\n */\nvoid mdelay(unsigned msec)\n{\n    usleep(msec * 1000);\n}\n\n/*\n * Send a series of bits to HT1621.\n * Up to 8 bits, high bit first.\n * Max clock rate is 150kHz.\n */\nvoid ht_send(int nbits, int data)\n{\n    data <<= (8 - nbits);\n    gpio_wr_clear();\n    while (nbits-- > 0) {\n        if (data & 0x80)\n            gpio_data_set();\n        else\n            gpio_data_clear();\n        gpio_wr_set();\n        gpio_wr_clear();\n        data <<= 1;\n    }\n}\n\n/*\n * Send command to HT1621.\n */\nvoid ht_cmd(int command)\n{\n    gpio_cs_clear();\n    ht_send(3, 0x4);        /* Mode \"100\" */\n    ht_send(8, command);\n    gpio_cs_set();\n}\n\n/*\n * Send data and command.\n */\nvoid ht_write(int addr, int data)\n{\n    gpio_cs_clear();\n    ht_send(3, 0x5);        /* Mode \"101\" */\n    ht_send(6, addr << 1);  /* Half-byte address 6 bits */\n    ht_send(8, data);       /* Data 8 bits */\n    gpio_cs_set();\n}\n\n/*\n * Initialize LCD controller.\n */\nvoid lcd_init()\n{\n    /* Open GPIO driver. */\n    gpio = open(\"/dev/porta\", 1);\n    if (gpio < 0) {\n        perror(\"/dev/porta\");\n        exit(-1);\n    }\n\n    /* Configure pins RE0-RE2 as outputs. */\n    ioctl(gpio, GPIO_PORTE | GPIO_CONFOUT, 0x07);\n    gpio_cs_set();\n    gpio_wr_clear();\n\n    /* Setup appropriate HT1621 mode. */\n    ht_cmd(HT_SYS_EN);\n    ht_cmd(HT_CLOCK_RC);\n    ht_cmd(HT_BIAS_1_3 | HT_COMMONS_4);\n    ht_cmd(HT_LCD_ON);\n}\n\n/*\n * Set display memory to given value.\n */\nvoid lcd_clear(int value)\n{\n    int i;\n\n    for (i=0; i<6; i++) {\n        ht_write(i, value);\n    }\n}\n\n/*\n * LCD on/off.\n */\nvoid lcd_enable(int on)\n{\n    if (on)\n        ht_cmd(HT_LCD_ON);\n    else\n        ht_cmd(HT_LCD_OFF);\n}\n\n/*\n * Display data.\n *  val - Data to be displayed, 0-999999\n *  dot - Display decimal dot, 0-3\n *  bat - Battery level, 0-3\n */\nvoid lcd_display(unsigned val, int dot, int bat)\n{\n    int i, byte[6];\n\n    /* Set numeric value. */\n    byte[5] = char_to_segm[val / 100000];\n    byte[4] = char_to_segm[(val / 10000) % 10];\n    byte[3] = char_to_segm[(val / 1000) % 10];\n    byte[2] = char_to_segm[(val / 100) % 10];\n    byte[1] = char_to_segm[(val / 10) % 10];\n    byte[0] = char_to_segm[val % 10];\n\n    /* Enable decimal dot/ */\n    switch (dot) {\n    case 1:\n        byte[0] |= 1 << 7;\n        break;\n    case 2:\n        byte[1] |= 1 << 7;\n        break;\n    case 3:\n        byte[2] |= 1 << 7;\n        break;\n    default:\n        break;\n    }\n    if (bat > 0)\n        byte[3] |= 1 << 7;\n    if (bat > 1)\n        byte[4] |= 1 << 7;\n    if (bat > 2)\n        byte[5] |= 1 << 7;\n\n    for (i=0; i<6; i++) {\n        ht_write(i, byte[i]);\n    }\n}\n\nint main()\n{\n    int i;\n\n    /* Initialize hardware. */\n    lcd_init();\n\n    /* Blink all segments twice. */\n    lcd_clear(0xff);\n    mdelay(1000);\n    lcd_clear(0);\n    mdelay(1000);\n    lcd_clear(0xff);\n    mdelay(1000);\n    lcd_clear(0);\n    mdelay(1000);\n\n    /* Show all characters on all segments. */\n    for (i=0; i<sizeof(char_to_segm); i++) {\n        lcd_clear(char_to_segm[i]);\n        mdelay(200);\n    }\n    lcd_clear(0);\n\n    /* Display counter 0 to 999999. */\n    for (;;) {\n       for (i=0; i<999999; i++) {\n            lcd_display(i, i/10%4, i/10%4);\n            mdelay(100);\n       }\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/c/primelist.c",
    "content": "/*\n * Print the list of prime numbers up to 100.\n */\n#include <stdio.h>\n\nint isprime(int);\n\nint main(void)\n{\n    int n;\n\n    for (n=2; n<100; ++n) {\n        if (isprime(n)) {\n            printf(\"%d \", n);\n        }\n    }\n    printf(\"\\n\");\n}\n\nint isprime(int n)\n{\n    int j;\n\n    if (n == 2)\n        return 1;\n\n    if (n % 2 == 0)\n        return 0;\n\n    for (j=3; j*j<=n; j+=2)\n        if (n % j == 0)\n            return 0;\n    return 1;\n}\n\n"
  },
  {
    "path": "share/examples/c/primesum.c",
    "content": "/*\n * Compute the sum of prime numbers up to 10000.\n */\n#include <stdio.h>\n\nint isprime(int);\n\nint main(void)\n{\n    int sum, n;\n\n    sum = 0;\n    for (n=2; n<10000; ++n) {\n        if (isprime(n)) {\n            sum += n;\n        }\n    }\n    printf(\"Sum of primes less than 10000: %d\\n\", sum);\n}\n\nint isprime(int n)\n{\n    int j;\n\n    if (n == 2)\n        return 1;\n\n    if (n % 2 == 0)\n        return 0;\n\n    for (j=3; j*j<=n; j+=2)\n        if (n % j == 0)\n            return 0;\n    return 1;\n}\n"
  },
  {
    "path": "share/examples/c/q8.c",
    "content": "/*\n * Eight Queens puzzle\n *\n * (C) 2010 by Mark Sproul\n * Open source as per standard Arduino code\n * Modified by Pito 12/2012 for SmallC and then by Alexey Frunze for Smaller C\n */\n#include <stdio.h>\n#define TRUE    1\n#define FALSE   0\n\nunsigned int gChessBoard[8];\nunsigned int gLoopCounter;\nint gValidCount;\n\nint CheckCurrentBoard(void)\n{\n    int ii;\n    int jj;\n    int theRow;\n    int theLongRow;\n    int theLongColumns;\n    int bitCount;\n\n    //* we know we have 1 in each row,\n    //* Check for 1 in each column\n    theRow = 0;\n    for (ii=0; ii<8; ii++) {\n        theRow |= gChessBoard[ii];\n    }\n    if (theRow != 0x0ff) {\n        return FALSE;\n    }\n\n    //* we have 1 in each column, now check the diagonals\n    theLongColumns = 0;\n    for (ii=0; ii<8; ii++) {\n        theLongRow = gChessBoard[ii] & 0x0ff;\n        theLongRow = theLongRow << ii;\n\n        theLongColumns |= theLongRow;\n    }\n\n    //* now count the bits\n    bitCount = 0;\n    for (ii=0; ii<16; ii++) {\n        if ((theLongColumns & 0x01) == 0x01) {\n            bitCount++;\n        }\n        theLongColumns = theLongColumns >> 1;\n    }\n\n    if (bitCount != 8) {\n        return FALSE;\n    }\n\n    //* we now have to check the other diagonal\n    theLongColumns = 0;\n    for (ii=0; ii<8; ii++) {\n        theLongRow = gChessBoard[ii] & 0x0ff;\n        theLongRow = theLongRow << 8;\n        theLongRow = theLongRow >> ii;\n\n        theLongColumns |= theLongRow;\n    }\n\n    //* now count the bits\n    bitCount = 0;\n    for (ii=0; ii<16; ii++) {\n        if ((theLongColumns & 0x01) == 0x01) {\n            bitCount++;\n        }\n        theLongColumns = theLongColumns >> 1;\n    }\n\n    if (bitCount != 8) {\n        return FALSE;\n    }\n    return TRUE;\n}\n\nint CheckForDone(void)\n{\n    int ii;\n    int weAreDone;\n    int theRow;\n\n    weAreDone = FALSE;\n\n    //* we know we have 1 in each row,\n    //* Check for 1 in each column\n    theRow = 0;\n    for (ii=0; ii<8; ii++) {\n        theRow |= gChessBoard[ii];\n    }\n\n    if (theRow == 0x01) {\n        weAreDone = TRUE;\n    }\n    return weAreDone;\n}\n\nvoid RotateQueens(void)\n{\n    int ii;\n    int keepGoing;\n    int theRow;\n\n    ii = 0;\n    keepGoing = TRUE;\n    while (keepGoing && (ii < 8)) {\n        theRow = gChessBoard[ii] & 0x0ff;\n        theRow = (theRow >> 1) & 0x0ff;\n        if (theRow != 0) {\n            gChessBoard[ii] = theRow;\n            keepGoing = FALSE;\n        } else {\n            gChessBoard[ii] = 0x080;\n        }\n        ii++;\n    }\n}\n\nvoid PrintChessBoard(void)\n{\n    int ii;\n    int jj;\n    int theRow;\n    char textString[32];\n\n    printf(\"\\nLoop= %d\\n\", gLoopCounter);\n    printf(\"Solution count= %d\\n\", gValidCount);\n\n    printf(\"+----------------+\\n\");\n    for (ii=0; ii<8; ii++) {\n        theRow = gChessBoard[ii];\n\n        printf(\"|\");\n        for (jj=0; jj<8; jj++) {\n            if (theRow & 0x080) {\n                printf(\"Q \");\n            } else {\n                printf(\". \");\n            }\n            theRow = theRow << 1;\n        }\n        printf(\"|\\n\");\n    }\n    printf(\"+----------------+\\n\");\n}\n\nint main(void)\n{\n    int ii;\n\n    printf(\"\\nEight Queens brute force\");\n    printf(\"\\n************************\\n\");\n    //* put the 8 queens on the board, 1 in each row\n    for (ii=0; ii<8; ii++) {\n        gChessBoard[ii] = 0x080;\n    }\n    PrintChessBoard();\n\n    gLoopCounter = 0;\n    gValidCount = 0;\n\n\n    while (1) {\n        gLoopCounter++;\n\n        if (CheckCurrentBoard()) {\n            gValidCount++;\n            PrintChessBoard();\n        } else if ((gLoopCounter % 1000) == 0) {\n            //PrintChessBoard();\n        }\n\n        RotateQueens();\n        if (CheckForDone()) {\n            //int elapsedSeconds;\n            //int elapsedMinutes;\n            //int elapsedHours;\n\n            //elapsedSeconds = millis() / 1000;\n            //elapsedMinutes = elapsedSeconds / 60;\n            //elapsedHours = elapsedMinutes / 60;\n\n            printf(\"----------------------------------\\n\");\n            printf(\"All done\\n\");\n\n            PrintChessBoard();\n            printf(\"----------------------------------\\n\");\n\n            //Serial.print(\"total seconds=\");\n            //Serial.println(elapsedSeconds);\n\n            //Serial.print(\"hours=\");\n            //Serial.println(elapsedHours);\n\n            //Serial.print(\"minutes=\");\n            //Serial.println(elapsedMinutes % 60);\n\n            //Serial.print(\"seconds=\");\n            //Serial.println(elapsedSeconds % 60);\n\n            return (1);\n        }\n    }\n}\n"
  },
  {
    "path": "share/examples/c/rain.c",
    "content": "/*\n * Example of using termcap library for SmallC.\n * 11/3/1980 EPS/CITHEP\n *\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <signal.h>\n#include <unistd.h>\n\n#define CO 80               /* number of columns */\n#define LI 24               /* number of lines */\n\n#define CL \"\\33[H\\33[J\"     /* clear the screen */\n#define CM \"\\33[%u;%uH\"     /* move the cursor to row, column */\n#define BC \"\\b\"             /* move cursor left */\n#define DN \"\\33[B\"          /* move cursor down */\n#define ND \" \"              /* move cursor right */\n\nint xpos[5], ypos[5];\nchar outbuf[BUFSIZ];\n\nvoid moveto(int col, int row)\n{\n    printf(CM, row, col);\n}\n\nvoid onsig(int n)\n{\n    moveto(0, LI - 1);\n    fflush(stdout);\n    _exit(0);\n}\n\nint main(void)\n{\n    int x, y, j;\n\n    setbuf(stdout, outbuf);\n    for (j = SIGHUP; j <= SIGTERM; j++)\n        if (signal(j, SIG_IGN) != SIG_IGN)\n            signal(j, onsig);\n\n    fputs(CL, stdout);\n    fflush(stdout);\n    for (j = 5; --j >= 0; ) {\n        xpos[j] = 2 + rand() % (CO - 4);\n        ypos[j] = 2 + rand() % (LI - 4);\n    }\n    for (j = 0; ; ) {\n        x = 2 + rand() % (CO - 4);\n        y = 2 + rand() % (LI - 4);\n        moveto(x, y);\n        putchar('.');\n        moveto(xpos[j], ypos[j]);\n        putchar('o');\n        if (j == 0)\n            j = 4;\n        else\n            --j;\n        moveto(xpos[j], ypos[j]);\n        putchar('O');\n        if (j == 0)\n            j = 4;\n        else\n            --j;\n        moveto(xpos[j], ypos[j]-1);\n        putchar('-');\n        fputs(DN, stdout);\n        fputs(BC, stdout);\n        fputs(BC, stdout);\n        fputs(\"|.|\", stdout);\n        fputs(DN, stdout);\n        fputs(BC, stdout);\n        fputs(BC, stdout);\n        putchar('-');\n        if (j == 0)\n            j = 4;\n        else\n            --j;\n        moveto(xpos[j], ypos[j]-2);\n        putchar('-');\n        fputs(DN, stdout);\n        fputs(BC, stdout);\n        fputs(BC, stdout);\n        fputs(\"/ \\\\\", stdout);\n        moveto(xpos[j]-2, ypos[j]);\n        fputs(\"| O |\", stdout);\n        moveto(xpos[j]-1, ypos[j]+1);\n        fputs(\"\\\\ /\", stdout);\n        fputs(DN, stdout);\n        fputs(BC, stdout);\n        fputs(BC, stdout);\n        putchar('-');\n        if (j == 0)\n            j = 4;\n        else\n            --j;\n        moveto(xpos[j], ypos[j]-2);\n        putchar(' ');\n        fputs(DN, stdout);\n        fputs(BC, stdout);\n        fputs(BC, stdout);\n        putchar(' ');\n        fputs(ND, stdout);\n        putchar(' ');\n        moveto(xpos[j]-2, ypos[j]);\n        putchar(' ');\n        fputs(ND, stdout);\n        putchar(' ');\n        fputs(ND, stdout);\n        putchar(' ');\n        moveto(xpos[j]-1, ypos[j]+1);\n        putchar(' ');\n        fputs(ND, stdout);\n        putchar(' ');\n        fputs(DN, stdout);\n        fputs(BC, stdout);\n        fputs(BC, stdout);\n        putchar(' ');\n        xpos[j] = x;\n        ypos[j] = y;\n        fflush(stdout);\n        usleep(100000);\n    }\n}\n"
  },
  {
    "path": "share/examples/c/skeleton.c",
    "content": "/*\n * Generic skeleton for a C program.\n * When you create your own program based on this skeleton,\n * you can replace the author's name and copyright with\n * whatever your want.  When you redistribute this skeleton or\n * enhance it, please leave my name and copyright on it.\n *\n * Copyright (C) 1993-2014 Serge Vakulenko, <vak@cronyx.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n\nconst char version[] = \"1.0\";\nconst char copyright[] = \"Copyright (C) 1993-2014 Serge Vakulenko\";\n\nchar *progname;         /* Name of the current program (argv[0]) */\nint verbose;            /* Option -v */\nint trace;              /* Option -t */\nint debug;              /* Option -d */\n\nvoid usage ()\n{\n    fprintf (stderr, \"Generic C skeleton, Version %s, %s\\n\", version, copyright);\n    fprintf (stderr, \"Usage:\\n\\t%s [-vtd] [-r count] file...\\n\", progname);\n    fprintf (stderr, \"Options:\\n\");\n    fprintf (stderr, \"\\t-v\\tverbose mode\\n\");\n    fprintf (stderr, \"\\t-t\\ttrace mode\\n\");\n    fprintf (stderr, \"\\t-d\\tdebug\\n\");\n    fprintf (stderr, \"\\t-r #\\trepeat count\\n\");\n    exit (-1);\n}\n\nint main (int argc, char **argv)\n{\n    int count = 1;      /* Option -r # */\n\n    progname = *argv;\n    for (;;) {\n        switch (getopt (argc, argv, \"vtdr:\")) {\n        case EOF:\n            break;\n        case 'v':\n            ++verbose;\n            continue;\n        case 't':\n            ++trace;\n            continue;\n        case 'd':\n            ++debug;\n            continue;\n        case 'r':\n            count = strtol (optarg, 0, 0);\n            continue;\n        default:\n            usage ();\n        }\n        break;\n    }\n    argc -= optind;\n    argv += optind;\n\n    if (argc < 1)\n        usage ();\n\n    while (count-- > 0) {\n        int i;\n\n        for (i=0; i<argc; ++i)\n            printf (\"%s \", argv[i]);\n        printf (\"\\n\");\n    }\n    return (0);\n}\n"
  },
  {
    "path": "share/examples/c/stdarg.c",
    "content": "#include <stdio.h>\n#include <stdarg.h>\n\nvoid print(char *fmt, ...)\n{\n    va_list ap;\n    int d;\n    char c, *s;\n\n    va_start(ap, fmt);\n    while (*fmt) {\n        switch (*fmt++) {\n        case 's':              /* string */\n            s = va_arg(ap, char*);\n            printf(\"string %s\\n\", s);\n            break;\n        case 'd':              /* int */\n            d = va_arg(ap, int);\n            printf(\"int %d\\n\", d);\n            break;\n        case 'c':              /* char */\n            c = va_arg(ap, int);\n            printf(\"char %c\\n\", c);\n            break;\n        }\n    }\n    va_end(ap);\n}\n\nint main()\n{\n    print(\"sdcsdc\", \"abracadabra\", 12345, 'Z', \"foo\", 365, '%');\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/c/test1.c",
    "content": "#include <stdio.h>\n\nint ga[5];\n\nint main(void)\n{\n    int a, b, c, d;\n    int arr[5];\n    int *pi;\n    char arrc[5];\n    char *pic;\n    int s1, s2;\n    int z;\n    int t;\n    int *pip;\n    int *picp;\n    int e1, e2;\n\n    ga[0] = 10;\n    ga[1] = 20;\n    ga[2] = 30;\n    ga[3] = 40;\n    ga[4] = 50;\n    \n    a = 21;\n    b = 31;\n    c = 71;\n    d = 82;\n\n    arr[0] = 10;\n    arr[1] = 20;\n    arr[2] = 30;\n    arr[3] = 40;\n    arr[4] = 50;\n    pi = &arr[0];\n\n    arrc[0] = 13;\n    arrc[1] = 23;\n    arrc[2] = 33;\n    arrc[3] = 43;\n    arrc[4] = 53;\n    pic = &arrc[0];\n\n    printf(\"          21 + 31 = %d (52)\\n\",   a + b);\n    printf(\"          21 - 31 = %d (-10)\\n\",  a - b);\n    printf(\"          21 & 71 = %d (5)\\n\",    a & c);\n    printf(\"          21 | 82 = %d (87)\\n\",   a | d);\n    printf(\"          21 ^ 82 = %d (71)\\n\",   a ^ d);\n    printf(\"          21 * 82 = %d (1722)\\n\", a * d);\n    printf(\"          82 %% 21 = %d (19)\\n\",  d % a);\n    printf(\"          82 / 21 = %d (3)\\n\",    d / a);\n    printf(\"              *pi = %d (10)\\n\",   *pi);\n    printf(\"          *pi + 1 = %d (11)\\n\",   *pi + 1);\n    printf(\"        *(pi + 1) = %d (20)\\n\",   *(pi + 1));\n    printf(\"&arr[3] - &arr[0] = %d (3)\\n\",    &arr[3] - &arr[0]);\n    printf(\"    arr[3]-arr[0] = %d (30)\\n\",   arr[3] - arr[0]);\n    printf(\"    arr[3]+arr[0] = %d (50)\\n\",   arr[3] + arr[0]);\n    printf(\"  &ga[3] - &ga[0] = %d (3)\\n\",    &ga[3] - &ga[0]);\n    printf(\"      ga[3]-ga[0] = %d (30)\\n\",   ga[3] - ga[0]);\n    printf(\"      ga[3]+ga[0] = %d (50)\\n\",   ga[3] + ga[0]);\n    printf(\"\\n\");\n\n    printf(\"               *pic = %d (13)\\n\", *pic);\n    printf(\"           *pic + 1 = %d (14)\\n\", *pic+1);\n    printf(\"         *(pic + 1) = %d (23)\\n\", *(pic+1));\n    printf(\"&arrc[3] - &arrc[0] = %d (3)\\n\",  &arrc[3]-&arrc[0]);\n    printf(\"\\n\");\n\n    s1 = 3;\n    s2 = -200;\n    printf(\"  82 << 3 = %d (656)\\n\",   d << s1);\n    printf(\"  82 >> 3 = %d (10)\\n\",    d >> s1);\n    printf(\"-200 >> 3 = %d (-25)\\n\",   s2 >> s1);\n    printf(\"-200 << 3 = %d (-1600)\\n\", s2 << s1);\n    printf(\"\\n\");\n\n    printf(\"-s1 = %d (-3)\\n\",  -s1);\n    printf(\"-s2 = %d (200)\\n\", -s2);\n    printf(\"\\n\");\n\n    printf(\"~82 = %d (-83)\\n\", ~d);\n    printf(\"\\n\");\n\n    z = 0;\n    printf(\"!82 = %d (0)\\n\", !d);\n    printf(\" !0 = %d (1)\\n\", !z);\n    printf(\"\\n\");\n\n    printf(\" 0 && 0  = %d (0)\\n\", z && z);\n    printf(\" 0 && 21 = %d (0)\\n\", z && a);\n    printf(\" 3 && 21 = %d (1)\\n\", s1 && a);\n    printf(\"21 && 3  = %d (1)\\n\", a && s1);\n    printf(\"\\n\");\n\n    printf(\" 0 || 0  = %d (0)\\n\", z || z);\n    printf(\" 0 || 21 = %d (1)\\n\", z || a);\n    printf(\" 3 || 21 = %d (1)\\n\", s1 || a);\n    printf(\"21 || 3  = %d (1)\\n\", a || s1);\n    printf(\"\\n\");\n\n    pi = 4;\n    printf(\"pi++ = %d (4)\\n\",  pi++);\n    printf(\"  pi = %d (8)\\n\",  pi);\n    printf(\"++pi = %d (12)\\n\", ++pi);\n    printf(\"pi-- = %d (12)\\n\", pi--);\n    printf(\"  pi = %d (8)\\n\",  pi);\n    printf(\"--pi = %d (4)\\n\",  --pi);\n    printf(\"\\n\");\n\n    pic = 4;\n    printf(\"pic++ = %d (4)\\n\", pic++);\n    printf(\"  pic = %d (5)\\n\", pic);\n    printf(\"++pic = %d (6)\\n\", ++pic);\n    printf(\"pic-- = %d (6)\\n\", pic--);\n    printf(\"  pic = %d (5)\\n\", pic);\n    printf(\"--pic = %d (4)\\n\", --pic);\n    printf(\"\\n\");\n\n    t = 4;\n    printf(\"t++ = %d (4)\\n\", t++);\n    printf(\"  t = %d (5)\\n\", t);\n    printf(\"++t = %d (6)\\n\", ++t);\n    printf(\"t-- = %d (6)\\n\", t--);\n    printf(\"  t = %d (5)\\n\", t);\n    printf(\"--t = %d (4)\\n\", --t);\n    printf(\"\\n\");\n\n    t = 4;\n    printf(\" t==4 = %d (1)\\n\", t == 4);\n    printf(\" t==3 = %d (0)\\n\", t == 3);\n    printf(\" t==5 = %d (0)\\n\", t == 5);\n    t = -4;\n    printf(\"t==-4 = %d (1)\\n\", t == -4);\n    printf(\"t==-3 = %d (0)\\n\", t == -3);\n    printf(\"t==-5 = %d (0)\\n\", t == -5);\n    printf(\" t==4 = %d (0)\\n\", t == 4);\n    printf(\" t==3 = %d (0)\\n\", t == 3);\n    printf(\" t==5 = %d (0)\\n\", t == 5);\n    printf(\"\\n\");\n\n    t = 4;\n    printf(\" t!=4 = %d (0)\\n\", t != 4);\n    printf(\" t!=3 = %d (1)\\n\", t != 3);\n    printf(\" t!=5 = %d (1)\\n\", t != 5);\n    t = -4;\n    printf(\"t!=-4 = %d (0)\\n\", t != -4);\n    printf(\"t!=-3 = %d (1)\\n\", t != -3);\n    printf(\"t!=-5 = %d (1)\\n\", t != -5);\n    printf(\" t!=4 = %d (1)\\n\", t != 4);\n    printf(\" t!=3 = %d (1)\\n\", t != 3);\n    printf(\" t!=5 = %d (1)\\n\", t != 5);\n    printf(\"\\n\");\n\n    t = 4;\n    printf(\" t<4 = %d (0)\\n\", t < 4);\n    printf(\" t<3 = %d (0)\\n\", t < 3);\n    printf(\" t<5 = %d (1)\\n\", t < 5);\n    printf(\"t<-1 = %d (0)\\n\", t < -1);\n    printf(\"\\n\");\n\n    printf(\" t<=4 = %d (1)\\n\", t <= 4);\n    printf(\" t<=3 = %d (0)\\n\", t <= 3);\n    printf(\" t<=5 = %d (1)\\n\", t <= 5);\n    printf(\"t<=-1 = %d (0)\\n\", t <= -1);\n    printf(\"\\n\");\n\n    t = 4;\n    printf(\" t>4 = %d (0)\\n\", t > 4);\n    printf(\" t>3 = %d (1)\\n\", t > 3);\n    printf(\" t>5 = %d (0)\\n\", t > 5);\n    printf(\"t>-1 = %d (1)\\n\", t > -1);\n    printf(\"\\n\");\n\n    printf(\" t>=4 = %d (1)\\n\", t >= 4);\n    printf(\" t>=3 = %d (1)\\n\", t >= 3);\n    printf(\" t>=5 = %d (0)\\n\", t >= 5);\n    printf(\"t>=-1 = %d (1)\\n\", t >= -1);\n    printf(\"\\n\");\n\n    pi = -100;\n    printf(\"   pi<4 = %d (0)\\n\", pi < (int*)4);\n    printf(\"   pi<3 = %d (0)\\n\", pi < (int*)3);\n    printf(\"pi<-100 = %d (0)\\n\", pi < (int*)-100);\n    printf(\"  pi<-1 = %d (1)\\n\", pi < (int*)-1);\n    printf(\"\\n\");\n\n    printf(\"   pi<=4 = %d (0)\\n\", pi <= (int*)4);\n    printf(\"   pi<=3 = %d (0)\\n\", pi <= (int*)3);\n    printf(\"pi<=-100 = %d (1)\\n\", pi <= (int*)-100);\n    printf(\"  pi<=-1 = %d (1)\\n\", pi <= (int*)-1);\n    printf(\"\\n\");\n\n    pi = -100;\n    printf(\"   pi>4 = %d (1)\\n\", pi > (int*)4);\n    printf(\"   pi>3 = %d (1)\\n\", pi > (int*)3);\n    printf(\"pi>-100 = %d (0)\\n\", pi > (int*)-100);\n    printf(\"  pi>-1 = %d (0)\\n\", pi > (int*)-1);\n    printf(\"\\n\");\n\n    printf(\"   pi>=4 = %d (1)\\n\", pi >= (int*)4);\n    printf(\"   pi>=3 = %d (1)\\n\", pi >= (int*)3);\n    printf(\"pi>=-100 = %d (1)\\n\", pi >= (int*)-100);\n    printf(\"  pi>=-1 = %d (0)\\n\", pi >= (int*)-1);\n    printf(\"\\n\");\n\n    pi = &arr[0];\n    pip = &arr[3];\n    printf(\"    *pip - *pi: %d (30)\\n\", *pip - *pi);\n    printf(\"      pip - pi: %d (3)\\n\",  pip - pi);\n    printf(\"          *pip: %d (40)\\n\", *pip);\n    printf(\"    *(pip - 3): %d (10)\\n\", *(pip - 3));\n    printf(\"      *&arr[3]: %d (40)\\n\", *&arr[3]);\n    printf(\"*(&arr[3] - 3): %d (10)\\n\", *(&arr[3]-3));\n}\n"
  },
  {
    "path": "share/examples/c/test2.c",
    "content": "#include <stdio.h>\n#include <errno.h>\n#include <fcntl.h>\n#include <unistd.h>\n\nint aaa;\nint bbb;\nint ccc;\nchar gc;\nchar gbuffer[3];\nint gibuffer[4];\n\nint main(void)\n{\n    char b;\n    int la;\n    unsigned int u1, u2;\n    int s1, s2;\n    unsigned char uc1, uc2;\n    char sc1, sc2;\n    int fd;\n    char buffer[6];\n    int ibuffer[7];\n\n    printf(\"                sizeof(uc1): %d 1\\n\",  sizeof(uc1));\n    printf(\"                sizeof(sc1): %d 1\\n\",  sizeof(sc1));\n    printf(\"                 sizeof(u1): %d 4\\n\",  sizeof(u1));\n    printf(\"                 sizeof(s1): %d 4\\n\",  sizeof(s1));\n    printf(\"                sizeof(aaa): %d 4\\n\",  sizeof(aaa));\n    printf(\"                sizeof(bbb): %d 4\\n\",  sizeof(bbb));\n    printf(\"                 sizeof(gc): %d 1\\n\",  sizeof(gc));\n    printf(\"             sizeof(buffer): %d 6\\n\",  sizeof(buffer));\n    printf(\"            sizeof(ibuffer): %d 28\\n\", sizeof(ibuffer));\n    printf(\"               sizeof(char): %d 1\\n\",  sizeof(char));\n    printf(\"                sizeof(int): %d 4\\n\",  sizeof(int));\n    printf(\"            sizeof(gbuffer): %d 3\\n\",  sizeof(gbuffer));\n    printf(\"           sizeof(gibuffer): %d 16\\n\", sizeof(gibuffer));\n    // sizeof(ibuffer[0]) is not supported, so the following can be used...\n    printf(\"sizeof(ibuffer)/sizeof(int): %d 7\\n\",  sizeof(ibuffer)/sizeof(int));\n\n    aaa = 1;\n    bbb = 2;\n    la = 4;\n    printf(\"%d 1\\n\", aaa);\n    printf(\"%d 2\\n\", bbb);\n    printf(\"%d 4\\n\", la);\n\n    uc1 = 0x80;\n    sc1 = 0x80;\n    s1 = uc1;\n    s2 = sc1;\n    printf(\"unsigned char (0x80) -> int: %d 128\\n\",  s1);\n    printf(\"  signed char (0x80) -> int: %d -128\\n\", s2);\n\n    u1 = uc1;\n    u2 = sc1;\n    printf(\"unsigned char (0x80) -> unsigned: %d 128\\n\", u1);\n    printf(\"  signed char (0x80) -> unsigned: %d -128\\n\", u2);\n\n    la = errno;\n    printf(\"errno: %d 0\\n\", la);\n\n    write(1, \"abcd \", 5);\n    la = errno;\n    printf(\"errno after good write call: %d 0\\n\", la);\n\n    write(10, \"abcde\", 5);\n    la = errno;\n    printf(\"errno after bad write call: %d 9\\n\", la);\n\n    write(1, \"abcd \", 5);\n    la = errno;\n    printf(\"good write after failed should not overwrite errno: %d 9\\n\", la);\n\n    errno = 0;\n    write(1, \"abcd \", 5);\n    la = errno;\n    printf(\"good write after errno set to zero: %d 0\\n\", la);\n\n    la = write(1, \"abcd \", 5);\n    printf(\"write() return: %d 5\\n\", la);\n\n    la = write(10, \"abcd \", 5);\n    printf(\"write(bad fd) return: %d -1\\n\", la);\n\n    fd = open(\"/a.txt\", O_WRONLY | O_CREAT, 0666);\n    if (fd != -1) {\n        printf(\"open success\\n\");\n        la = write(fd, \"abcd\\n\", 5);\n        if (la == 5) printf(\"write success\\n\"); else  printf(\"write failed\\n\");\n        la = close(fd);\n        if (la != -1) printf(\"close success\\n\"); else printf(\"close failed\\n\");\n    } else {\n        printf(\"open failed\\n\");\n    }\n\n    buffer[0] = 0;\n    buffer[1] = 0;\n    buffer[2] = 0;\n    buffer[3] = 0;\n    buffer[4] = 0;\n    buffer[5] = 0;\n\n    fd = open(\"/a.txt\", O_RDONLY, 0666);\n    if (fd != -1) {\n        printf(\"open success\\n\");\n        la = read(fd, buffer, 5);\n        printf(buffer);\n        if (la == 5) printf(\"read success\\n\"); else  printf(\"read failed\\n\");\n        la = close(fd);\n        if (la != -1) printf(\"close success\\n\"); else printf(\"close failed\\n\");\n    } else {\n        printf(\"open failed\\n\");\n    }\n\n    if (buffer[0] != 'a')  printf(\"data0 readback from file MISMATCH\\n\");\n    if (buffer[1] != 'b')  printf(\"data1 readback from file MISMATCH\\n\");\n    if (buffer[2] != 'c')  printf(\"data2 readback from file MISMATCH\\n\");\n    if (buffer[3] != 'd')  printf(\"data3 readback from file MISMATCH\\n\");\n    if (buffer[4] != '\\n') printf(\"data4 readback from file MISMATCH\\n\");\n\n    if (buffer[0] != 'a' || buffer[1] != 'b' || buffer[2] != 'c' ||\n        buffer[3] != 'd' || buffer[4] != '\\n') {\n        printf(\"data readback from file MISMATCH\\n\");\n    } else {\n        printf(\"data readback from file OK\\n\");\n    }\n}\n"
  },
  {
    "path": "share/examples/c/test3.c",
    "content": "#include <stdio.h>\n\nvoid printt(int t, char* str);\n\nint main(void)\n{\n    int t;\n\n    t = 0;\n    if (t) printt(t, \"failure\"); else printt(t, \"success\");\n    t = 1;\n    if (t) printt(t, \"success\"); else printt(t, \"failure\");\n    t = 8;\n    if (t) printt(t, \"success\"); else printt(t, \"failure\");\n    t = -2;\n    if (t) printt(t, \"success\"); else printt(t, \"failure\");\n    printf(\"\\n\");\n\n    t = 4;\n    printf(\"switch test: \");\n    switch (t) {\n    case 3:\n        printf(\"failure\");\n        break;\n    case 4:\n        printf(\"success\");\n        break;\n    case 5:\n        printf(\"failure\");\n        break;\n    }\n    printf(\"\\n\");\n\n    printf(\"switch fallthrough test: \");\n    switch (t) {\n    case 3:\n        printf(\"failure\");\n        break;\n    case 4:\n        printf(\"OKSOFAR: \");\n    case 5:\n        printf(\"success if oksofar printed before this in caps\");\n        break;\n    }\n    printf(\"\\n\");\n}\n\nvoid printt(int t, char* str)\n{\n    printf(\"bool test on value %d %s\\n\", t, str);\n}\n"
  },
  {
    "path": "share/examples/c/tetris.c",
    "content": "/*\n * Tetris (C) Copyright 1995, Vadim Antonov\n * Port to RetroBSD (C) 2015, Serge Vakulenko\n *\n * This program is designed to run on Olimex Duinomite board\n * with SainSmart Graphic LCD4884 shield, modified for 3.3V.\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <stdlib.h>\n#include <stdio.h>\n#include <string.h>\n#include <unistd.h>\n#include <fcntl.h>\n#include <sys/gpio.h>\n\n#define PITWIDTH    12\n#define PITDEPTH    21\n\n#define NSHAPES     7\n#define NBLOCKS     5\n\n#define FIN         999\n\ntypedef struct {\n    int x, y;\n} coord_t;\n\ntypedef struct {\n    int dx, dy;\n    coord_t p[NBLOCKS];\n} shape_t;\n\nconst shape_t shape [NSHAPES] = {\n/* OOOO */  { 0, 3, { {0,0}, {0,1}, {0,2}, {0,3}, {FIN,FIN} } },\n\n/* O   */   { 1, 2, { {0,0}, {1,0}, {1,1}, {1,2}, {FIN,FIN} } },\n/* OOO */\n\n/*  O  */   { 1, 2, { {0,1}, {1,0}, {1,1}, {1,2}, {FIN,FIN} } },\n/* OOO */\n\n/*   O */   { 1, 2, { {0,2}, {1,0}, {1,1}, {1,2}, {FIN,FIN} } },\n/* OOO */\n\n/*  OO */   { 1, 2, { {0,0}, {0,1}, {1,1}, {1,2}, {FIN,FIN} } },\n/* OO  */\n\n/* OO  */   { 1, 2, { {0,1}, {0,2}, {1,0}, {1,1}, {FIN,FIN} } },\n/*  OO */\n\n/* OO */    { 1, 1, { {0,0}, {0,1}, {1,0}, {1,1}, {FIN,FIN} } },\n/* OO */\n};\n\nint pit [PITDEPTH+1] [PITWIDTH];\nint pitcnt [PITDEPTH];\ncoord_t old [NBLOCKS], new [NBLOCKS], chk [NBLOCKS];\nint gpio;                               /* File descriptor of GPIO driver. */\nint adc3;                               /* File descriptor of ADC3 driver. */\n\n/*-------------------------------------------------------------\n * Definitions for a \"digital\" joystick at A0 analog input.\n * Button values are determined by resistors on a board.\n */\nenum {\n    JOYSTICK_LEFT,\n    JOYSTICK_SELECT,\n    JOYSTICK_DOWN,\n    JOYSTICK_RIGHT,\n    JOYSTICK_UP,\n    JOYSTICK_IDLE = -1,\n};\n\n/*\n * Initialize ADC for a joystick.\n */\nvoid joystick_init()\n{\n    /* Open ADC driver. */\n    adc3 = open(\"/dev/adc3\", 0);\n    if (adc3 < 0) {\n        perror(\"/dev/adc3\");\n        exit(-1);\n    }\n}\n\n/*\n * Get a state of joystick.\n * Convert ADC value to key number.\n * Input buttons are connected to a series network of resistors:\n * GND - 3.3k - 1k - 620 - 330 - 2k - +3.3V\n * Expected values are:\n * 0 - 144 - 329 - 506 - 741 - 1023\n */\nint joystick_get()\n{\n    static const unsigned level[5] = { 72, 236, 417, 623, 882 };\n    unsigned input, k;\n    char buf[16];\n\n    if (read(adc3, buf, sizeof(buf)) <= 0) {\n        perror(\"adc\");\n        exit(-1);\n    }\n    input = strtol(buf, 0, 10);\n    for (k=0; k<5; k++) {\n        if (input < level[k]) {\n            return k;\n        }\n    }\n    return JOYSTICK_IDLE;\n}\n\n/*-------------------------------------------------------------\n * Routines for Nokia 5110 display.\n * See Philips PCD8544 datasheet.\n */\n#define NROW 48\n#define NCOL 84\n\n/*\n * Pinout for SainSmart Graphic LCD4884 Shield.\n */\n#define MASKE_LCD_SCK   (1 << 2)    /* signal D2, pin RE2 */\n#define MASKE_LCD_MOSI  (1 << 3)    /* signal D3, pin RE3 */\n#define MASKE_LCD_DC    (1 << 4)    /* signal D4, pin RE4 */\n#define MASKE_LCD_CS    (1 << 5)    /* signal D5, pin RE5 */\n#define MASKE_LCD_RST   (1 << 6)    /* signal D6, pin RE6 */\n#define MASKE_LCD_BL    (1 << 7)    /* signal D7, pin RE7 */\n\nstatic unsigned char gpanel_screen [NROW*NCOL/8];\nint gpanel_row, gpanel_col;\n\nstatic void lcd_cs(unsigned on)\n{\n    if (on) {\n        ioctl(gpio, GPIO_PORTE | GPIO_SET, MASKE_LCD_CS);\n    } else {\n        ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, MASKE_LCD_CS);\n    }\n}\n\nstatic void lcd_rst(unsigned on)\n{\n    if (on) {\n        ioctl(gpio, GPIO_PORTE | GPIO_SET, MASKE_LCD_RST);\n    } else {\n        ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, MASKE_LCD_RST);\n    }\n}\n\nstatic void lcd_dc(unsigned on)\n{\n    if (on) {\n        ioctl(gpio, GPIO_PORTE | GPIO_SET, MASKE_LCD_DC);\n    } else {\n        ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, MASKE_LCD_DC);\n    }\n}\n\nstatic void lcd_bl(unsigned on)\n{\n    if (on) {\n        ioctl(gpio, GPIO_PORTE | GPIO_SET, MASKE_LCD_BL);\n    } else {\n        ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, MASKE_LCD_BL);\n    }\n}\n\nstatic void lcd_mosi(unsigned on)\n{\n    if (on) {\n        ioctl(gpio, GPIO_PORTE | GPIO_SET, MASKE_LCD_MOSI);\n    } else {\n        ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, MASKE_LCD_MOSI);\n    }\n}\n\nstatic void lcd_sck(unsigned on)\n{\n    if (on) {\n        ioctl(gpio, GPIO_PORTE | GPIO_SET, MASKE_LCD_SCK);\n    } else {\n        ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, MASKE_LCD_SCK);\n    }\n}\n\nstatic void lcd_write(unsigned byte, unsigned data_flag)\n{\n    unsigned i;\n\n    lcd_cs(0);\n    lcd_dc(data_flag);\n    for (i=0; i<8; i++, byte<<=1) {\n        lcd_mosi(byte & 0x80);          /* SDIN = bit[i] */\n        lcd_sck(0);                     /* SCLK = 0 */\n        lcd_sck(1);                     /* SCLK = 1 */\n    }\n    lcd_cs(1);\n}\n\n/*\n * Set up hardware for communication to Nokia 5110 LCD Display.\n * Do not clear the display.\n * Leave backlight turned off.\n */\nvoid gpanel_init()\n{\n    gpanel_row = 0;\n    gpanel_col = 0;\n\n    /* Open GPIO driver. */\n    gpio = open(\"/dev/porta\", 0);\n    if (gpio < 0) {\n        perror(\"/dev/porta\");\n        exit(-1);\n    }\n\n    /*\n     * Set pins as outputs.\n     */\n    ioctl(gpio, GPIO_PORTE | GPIO_CONFOUT, MASKE_LCD_SCK |\n        MASKE_LCD_MOSI | MASKE_LCD_DC | MASKE_LCD_CS |\n        MASKE_LCD_RST | MASKE_LCD_BL);\n    ioctl(gpio, GPIO_PORTE | GPIO_SET, MASKE_LCD_RST | MASKE_LCD_CS);\n    ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, MASKE_LCD_SCK |\n        MASKE_LCD_MOSI | MASKE_LCD_DC | MASKE_LCD_BL);\n\n    /* Turn off backlight. */\n    lcd_bl(0);\n\n    /* Reset the display. */\n    lcd_rst(0);\n    usleep(10000);          // need 1 usec\n    lcd_rst(1);\n    usleep(10000);          // need 1 usec\n\n    lcd_write(0x21, 0);     // Enable extended instruction set\n    lcd_write(0xbf, 0);     // Set Vop - contrast level\n    lcd_write(0x04, 0);     // Set temperature coefficient to 0\n    lcd_write(0x14, 0);     // Set bias to 4\n    lcd_write(0x20, 0);     // Back to normal instruction set\n    lcd_write(0x0c, 0);     // Set normal mode\n\n    /* Enable backlight. */\n    lcd_bl(1);\n}\n\n/*\n * Clear the the LCD screen.\n */\nvoid gpanel_clear()\n{\n    unsigned i;\n\n    /* Clear data */\n    lcd_write(0x40, 0);\n    lcd_write(0x80, 0);\n    for (i=0; i<NROW*NCOL/8; i++) {\n        gpanel_screen[i] = 0;\n        lcd_write(0, 1);\n    }\n    gpanel_row = 0;\n    gpanel_col = 0;\n}\n\n/*\n * Lights a single pixel in the specified color\n * at the specified x and y addresses\n */\nvoid gpanel_pixel(int x, int y, int color)\n{\n    unsigned char *data;\n\n    if (x >= NCOL || y >= NROW)\n        return;\n    data = &gpanel_screen [(y >> 3) * NCOL + x];\n\n    if (color)\n        *data |= 1 << (y & 7);\n    else\n        *data &= ~(1 << (y & 7));\n\n    lcd_write(0x40 | (y >> 3), 0);\n    lcd_write(0x80 | x, 0);\n    lcd_write(*data, 1);\n}\n\n/*\n * Draw a filled rectangle in the specified color from (x1,y1) to (x2,y2).\n *\n * The best way to fill a rectangle is to take advantage of the \"wrap-around\" featute\n * built into the Philips PCF8833 controller. By defining a drawing box, the memory can\n * be simply filled by successive memory writes until all pixels have been illuminated.\n */\nvoid gpanel_rect_filled(int x0, int y0, int x1, int y1, int color)\n{\n    /* Temporary solution */\n    int xmin, xmax, ymin, ymax, x, y;\n\n    /* calculate the min and max for x and y directions */\n    if (x0 <= x1) {\n        xmin = x0;\n        xmax = x1;\n    } else {\n        xmin = x1;\n        xmax = x0;\n    }\n    if (y0 <= y1) {\n        ymin = y0;\n        ymax = y1;\n    } else {\n        ymin = y1;\n        ymax = y0;\n    }\n    for (y=ymin; y<=ymax; y++)\n        for (x=xmin; x<=xmax; x++)\n            gpanel_pixel(x, y, color);\n}\n\n/*-------------------------------------------------------------\n * Output piece coordinates given its center and angle\n */\nvoid translate(const shape_t *t, const coord_t *c, int a, coord_t *res)\n{\n    coord_t org, tmp;\n    int yw, xw, i;\n\n    if (a & 1) {            /* 90 deg */\n        xw = t->dy;\n        yw = t->dx;\n    } else {\n        xw = t->dx;\n        yw = t->dy;\n    }\n    org = *c;\n    org.x -= (xw + 1) / 2;\n    org.y -= yw / 2;\n    if (org.y < 0)\n        org.y = 0;\n    if (org.y + yw >= PITWIDTH && c->y <= PITWIDTH)\n        org.y = PITWIDTH-1 - yw;\n    for (i=0; t->p[i].x!=FIN; i++) {\n        switch (a) {\n        case 0:\n            res[i].x = t->p[i].x;\n            res[i].y = t->p[i].y;\n            break;\n        case 3:\n            res[i].x = xw - t->p[i].y;\n            res[i].y = t->p[i].x;\n            break;\n        case 2:\n            res[i].x = xw - t->p[i].x;\n            res[i].y = yw - t->p[i].y;\n            break;\n        case 1:\n            res[i].x = t->p[i].y;\n            res[i].y = yw - t->p[i].x;\n        }\n        res[i].x += org.x;\n        res[i].y += org.y;\n    }\n    res[i].x = res[i].y = FIN;\n\n    do {\n        xw = 0;\n        for (i=0; res[i+1].x!=FIN; i++) {\n            if (res[i].x < res[i+1].x)\n                continue;\n            if (res[i].x == res[i+1].x && res[i].y <= res[i+1].y)\n                continue;\n            xw++;\n            tmp = res[i];\n            res[i] = res[i+1];\n            res[i+1] = tmp;\n        }\n    } while (xw);\n}\n\n/*\n * Draw the block\n */\nvoid draw_block(int h, int w, int visible)\n{\n    h *= 4;\n    w *= 4;\n    if (visible) {\n        gpanel_rect_filled(NCOL-1 - h, w, NCOL-1 - (h + 3), w + 3, 1);\n    } else {\n        gpanel_rect_filled(NCOL-1 - h, w, NCOL-1 - (h + 3), w + 3, 0);\n\n        if (h == (PITDEPTH-1)*5)\n            gpanel_pixel(NCOL-1 - (h + 3), w + 2, 1);\n\n        if (w == 0)\n            gpanel_pixel(NCOL-1 - (h + 2), w, 1);\n        else if (w % 16 == 12)\n            gpanel_pixel(NCOL-1 - (h + 2), w + 3, 1);\n    }\n}\n\n/*\n * Move the piece\n */\nvoid move(coord_t *old, coord_t *new)\n{\n    for (;;) {\n        if (old->x == FIN) {\ndraw:       if (new->x == FIN)\n                break;\n            if (new->x >= 0)\n                draw_block(new->x, new->y, 1);\n            new++;\n            continue;\n        }\n        if (new->x == FIN) {\nclear:      if (old->x >= 0)\n                draw_block(old->x, old->y, 0);\n            old++;\n            continue;\n        }\n        if (old->x > new->x)\n            goto draw;\n        if (old->x < new->x)\n            goto clear;\n        if (old->y > new->y)\n            goto draw;\n        if (old->y != new->y)\n            goto clear;\n        /* old & new at the same place */\n        old++;\n        new++;\n    }\n}\n\n/*\n * Draw the pit\n */\nvoid clear()\n{\n    int h, w;\n\n    for (h=0; h<PITDEPTH; h++) {\n        for (w=0; w<PITWIDTH; w++) {\n            draw_block(h, w, 0);\n            pit[h][w] = 0;\n        }\n        pitcnt[h] = 0;\n    }\n    for (w=0; w<PITWIDTH; w++)\n        pit[PITDEPTH][w] = 1;\n}\n\n/*\n * The piece reached the bottom\n */\nvoid stopped(coord_t *c)\n{\n    int h, nfull, w, k;\n\n    /* Count the full lines */\n    nfull = 0;\n    for (; c->x!=FIN; c++) {\n        if (c->x <= 0) {\n            /* Game over. */\n            clear();\n            return;\n        }\n        pit[c->x][c->y] = 1;\n        ++pitcnt[c->x];\n        if (pitcnt[c->x] == PITWIDTH)\n            nfull++;\n    }\n    if (! nfull)\n        return;\n\n    /* Clear upper nfull lines */\n    for (h=0; h<nfull; h++) {\n        for (w=0; w<PITWIDTH; w++) {\n            if (pit[h][w]) {\n                draw_block(h, w, 0);\n            }\n        }\n    }\n\n    /* Move lines down */\n    k = nfull;\n    for (h=nfull; h<PITDEPTH && k>0; h++) {\n        if (pitcnt[h-k] == PITWIDTH) {\n            k--;\n            h--;\n            continue;\n        }\n        for (w=0; w<PITWIDTH; w++) {\n            if (pit[h][w] != pit[h-k][w]) {\n                draw_block(h, w, pit[h-k][w]);\n            }\n        }\n    }\n\n    /* Now fix the pit contents */\n    for (h=PITDEPTH-1; h>0; h--) {\n        if (pitcnt[h] != PITWIDTH)\n            continue;\n        memmove(pit[0]+PITWIDTH, pit[0], h * sizeof(pit[0]));\n        memset(pit[0], 0, sizeof(pit[0]));\n        memmove(pitcnt+1, pitcnt, h * sizeof(pitcnt[0]));\n        pitcnt[0] = 0;\n        h++;\n    }\n}\n\nint main()\n{\n    int ptype;              /* Piece type */\n    int angle, anew;        /* Angle */\n    int msec;               /* Timeout */\n    coord_t c, cnew, *cp;\n    unsigned up_pressed = 0, left_pressed = 0;\n    unsigned right_pressed = 0, down_pressed = 0;\n\n    joystick_init();\n    gpanel_init();\n    gpanel_clear();\n\n    /* Draw the pit */\n    clear();\n\nnewpiece:\n    ptype = rand() % NSHAPES;\n    angle = rand() % 3;\n\n    c.y = PITWIDTH/2 - 1;\n    for (c.x= -2; ; c.x++) {\n        translate(&shape[ptype], &c, angle, new);\n        for (cp=new; cp->x!=FIN; cp++) {\n            if (cp->x >= 0)\n                goto ok;\n        }\n    }\nok:\n    /* Draw new piece */\n    for (cp=new; cp->x!=FIN; cp++) {\n        if (cp->x >= 0) {\n            draw_block(cp->x, cp->y, 1);\n        }\n    }\n    memcpy(old, new, sizeof old);\n\n    msec = 500;\n    for (;;) {\n        cnew = c;\n        anew = angle;\n\n        if (msec <= 0) {\n            /* Timeout: move down */\n            msec = 500;\n            cnew.x++;\n            translate(&shape[ptype], &cnew, anew, chk);\n            for (cp=chk; cp->x!=FIN; cp++) {\n                if (cp->x >= 0 && pit[cp->x][cp->y]) {\n                    stopped(new);\n                    goto newpiece;\n                }\n            }\n            goto check;\n        }\n\n        int key = joystick_get();\n        if (key != JOYSTICK_RIGHT)\n            right_pressed = 0;\n        else if (! right_pressed) {\n            right_pressed = 1;\n\n            /* Right: rotate */\n            if (--anew < 0)\n                anew = 3;\n            translate(&shape[ptype], &cnew, anew, chk);\n            goto check;\n        }\n\n        if (key != JOYSTICK_UP)\n            up_pressed = 0;\n        else if (! up_pressed) {\n            up_pressed = 1;\n\n            /* Up: move left. */\n            if (cnew.y <= 0)\n                continue;\n            cnew.y--;\n            translate(&shape[ptype], &cnew, anew, chk);\n            goto check;\n        }\n\n        if (key != JOYSTICK_DOWN)\n            down_pressed = 0;\n        else if (! down_pressed) {\n            down_pressed = 1;\n\n            /* Down: move right */\n            if (cnew.y >= PITWIDTH-1)\n                continue;\n            cnew.y++;\n            translate(&shape[ptype], &cnew, anew, chk);\n            goto check;\n        }\n\n        if (key != JOYSTICK_LEFT)\n            left_pressed = 0;\n        else if (! left_pressed) {\n            left_pressed = 1;\n\n            /* Right: drop */\n            for (;;) {\n                cnew.x++;\n                translate(&shape[ptype], &cnew, anew, chk);\n                for (cp=chk; cp->x!=FIN; cp++) {\n                    if (cp->x >= 0 && pit[cp->x][cp->y]) {\n                        cnew.x--;\n                        translate(&shape[ptype], &cnew, anew, chk);\n                        move(new, chk);\n                        stopped(chk);\n                        goto newpiece;\n                    }\n                }\n            }\n        }\n\n        usleep(10000);\n        msec -= 10;\n        continue;\ncheck:\n        for (cp=chk; cp->x!=FIN; cp++) {\n            if (cp->y < 0 || cp->y >= PITWIDTH)\n                goto done;\n        }\n        for (cp=chk; cp->x!=FIN; cp++) {\n            if (cp->x >= 0 && pit[cp->x][cp->y])\n                goto done;\n        }\n        c = cnew;\n        angle = anew;\n        memcpy(old, new, sizeof old);\n        memcpy(new, chk, sizeof new);\n        move(old, new);\ndone:   ;\n    }\n}\n"
  },
  {
    "path": "share/examples/cube/Makefile",
    "content": "PROG    = all backlight cube demo\n\n# Duinomite board\n#OBJS    = duinomite.o\n\n# Fubarino board\nOBJS    = fubarino.o\n\nall:    $(PROG)\n\nall:    all.c $(OBJS)\n\tcc $@.c $(OBJS) -o $@\n\nbacklight: backlight.c $(OBJS)\n\tcc $@.c $(OBJS) -o $@\n\ncube:   cube.c $(OBJS)\n\tcc $@.c $(OBJS) -o $@\n\ndemo:   demo.c $(OBJS)\n\tcc $@.c $(OBJS) -o $@\n\nclean:\n\trm -f *.o *~ $(PROG)\n"
  },
  {
    "path": "share/examples/cube/Makefile-host",
    "content": "TOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nCFLAGS\t\t+= -Werror\nLIBS            += -lm\n\n#all:           demo\n\ndemo:           demo.o fubarino.o\n\t\t${CC} ${LDFLAGS} -o demo.elf demo.o fubarino.o ${LIBS}\n\t\t${OBJDUMP} -S demo.elf > demo.dis\n\t\t${SIZE} demo.elf\n\t\t${ELF2AOUT} demo.elf $@\n\nclean:\n\t\trm -f *.o *.elf ${MAN} demo *.elf *.dis tags *~\n"
  },
  {
    "path": "share/examples/cube/README.txt",
    "content": "Examples for LED cube 8x8x8.\n"
  },
  {
    "path": "share/examples/cube/all.c",
    "content": "/*\n * Demo for LED cube 8x8x8.\n * Turn on all LEDs.\n */\n#include <stdio.h>\n#include \"cube.h\"\n\nint main()\n{\n    static unsigned char data[8] = {\n        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n    };\n    int i;\n\n    gpio_init();\n    gpio_le(0);\n    gpio_plane(data);\n    gpio_ext(1);\n    for (;;) {\n        for (i=0; i<8; i++) {\n            gpio_layer(i);\n        }\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/cube/backlight.c",
    "content": "/*\n * Demo for LED cube 8x8x8.\n * Test backlight LEDs.\n */\n#include <stdio.h>\n#include \"cube.h\"\n\nint main()\n{\n    gpio_init();\n    for (;;) {\n        gpio_backlight_upper(1);\n        usleep(500000);\n        gpio_backlight_upper(0);\n        gpio_backlight_lower(1);\n        usleep(500000);\n        gpio_backlight_lower(0);\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/cube/cube.c",
    "content": "/*\n * Demo for LED cube 8x8x8.\n * Switch between two static images.\n */\n#include <stdio.h>\n#include <sys/time.h>\n#include \"cube.h\"\n\nvoid display(int duration, unsigned char *data)\n{\n    struct timeval t0, now;\n    int z, msec;\n\n    gettimeofday(&t0, 0);\n    z = 0;\n    for (;;) {\n        /* Send layer data. Latch is active,\n         * so previous layer is still displayed. */\n        gpio_plane(data + z*CUBE_SIZE);\n\n        /* Disable output, activate latch,\n         * switch to next layer. */\n        gpio_oe(0);\n        gpio_le(0);\n        gpio_le(1);\n        gpio_layer(z);\n        gpio_oe(1);\n\n        /* Next layer. */\n        z++;\n        if (z >= CUBE_SIZE) {\n            z = 0;\n\n            /* Check time. */\n            gettimeofday(&now, 0);\n            msec = (now.tv_sec - t0.tv_sec) * 1000;\n            msec += (now.tv_usec - t0.tv_usec) / 1000;\n            if (msec >= duration)\n                break;\n        }\n    }\n}\n\nint main()\n{\n    static unsigned char foo[64] = {\n        0xff, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0xff,\n        0x81, 0,    0,    0,    0,    0,    0,    0x81,\n        0x81, 0,    0,    0,    0,    0,    0,    0x81,\n        0x81, 0,    0,    0,    0,    0,    0,    0x81,\n        0x81, 0,    0,    0,    0,    0,    0,    0x81,\n        0x81, 0,    0,    0,    0,    0,    0,    0x81,\n        0x81, 0,    0,    0,    0,    0,    0,    0x81,\n        0xff, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0xff,\n    };\n    static unsigned char bar[64] = {\n        0,    0,    0,    0,    0,    0,    0,    0,\n        0,    0x7e, 0x42, 0x42, 0x42, 0x42, 0x7e, 0,\n        0,    0x42, 0,    0,    0,    0,    0x42, 0,\n        0,    0x42, 0,    0,    0,    0,    0x42, 0,\n        0,    0x42, 0,    0,    0,    0,    0x42, 0,\n        0,    0x42, 0,    0,    0,    0,    0x42, 0,\n        0,    0x7e, 0x42, 0x42, 0x42, 0x42, 0x7e, 0,\n        0,    0,    0,    0,    0,    0,    0,    0,\n    };\n    gpio_init();\n    gpio_ext(1);\n    for (;;) {\n        display(500, foo);\n        display(500, bar);\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/cube/cube.h",
    "content": "/*\n * Interface to LED cube 8x8x8.\n */\n#define CUBE_SIZE 8\n\nvoid gpio_init(void);\nvoid gpio_ext(int on);\nvoid gpio_oe(int active);\nvoid gpio_le(int active);\nvoid gpio_backlight_upper(int on);\nvoid gpio_backlight_lower(int on);\nvoid gpio_layer(int z);\nvoid gpio_plane(unsigned char *data);\n"
  },
  {
    "path": "share/examples/cube/demo.c",
    "content": "#include <stdio.h>\n#include <string.h>\n#include <sys/time.h>\n#include \"cube.h\"\n\n#define AXIS_X 1\n#define AXIS_Y 2\n#define AXIS_Z 3\n\nunsigned char cube[8][8];\n\n// Delay loop.\n// This is not calibrated to milliseconds,\n// but we had allready made to many effects using this\n// calibration when we figured it might be a good idea\n// to calibrate it.\nvoid delay_ms(unsigned duration)\n{\n    struct timeval t0, now;\n    int z, msec;\n\n    gettimeofday(&t0, 0);\n    z = 0;\n    for (;;) {\n        /* Send layer data. Latch is active,\n         * so previous layer is still displayed. */\n        gpio_plane(cube[z]);\n\n        /* Disable output, activate latch,\n         * switch to next layer. */\n        gpio_oe(0);\n        gpio_le(0);\n        gpio_le(1);\n        gpio_layer(z);\n        gpio_oe(1);\n\n        /* Next layer. */\n        z++;\n        if (z >= CUBE_SIZE) {\n            z = 0;\n\n            /* Check time. */\n            gettimeofday(&now, 0);\n            msec = (now.tv_sec - t0.tv_sec) * 1000;\n            msec += (now.tv_usec - t0.tv_usec) / 1000;\n            if (msec >= duration)\n                break;\n        }\n    }\n}\n\n// ==========================================================================================\n//   Draw functions\n// ==========================================================================================\n\n// Set a single voxel to ON\nvoid setvoxel(int x, int y, int z)\n{\n    if (inrange(x, y, z))\n        cube[z][y] |= (1 << x);\n}\n\n// Set a single voxel to ON\nvoid clrvoxel(int x, int y, int z)\n{\n    if (inrange(x, y, z))\n        cube[z][y] &= ~(1 << x);\n}\n\n// This function validates that we are drawing inside the cube.\nint inrange(int x, int y, int z)\n{\n    return x >= 0 && x < 8 && y >= 0 && y < 8 && z >= 0 && z < 8;\n}\n\n// Get the current status of a voxel\nint getvoxel(int x, int y, int z)\n{\n    if (! inrange(x, y, z))\n        return 0;\n\n    return (cube[z][y] >> x) & 1;\n}\n\n// In some effect we want to just take bool and write it to a voxel\n// this function calls the apropriate voxel manipulation function.\nvoid altervoxel(int x, int y, int z, int state)\n{\n    if (state == 1) {\n        setvoxel(x, y, z);\n    } else {\n        clrvoxel(x, y, z);\n    }\n}\n\n// Flip the state of a voxel.\n// If the voxel is 1, its turned into a 0, and vice versa.\nvoid flpvoxel(int x, int y, int z)\n{\n    if (inrange(x, y, z))\n        cube[z][y] ^= (1 << x);\n}\n\n// Makes sure x1 is alwas smaller than x2\n// This is usefull for functions that uses for loops,\n// to avoid infinite loops\nvoid argorder(int ix1, int ix2, int *ox1, int *ox2)\n{\n\tif (ix1>ix2)\n\t{\n\t\tint tmp;\n\t\ttmp = ix1;\n\t\tix1= ix2;\n\t\tix2 = tmp;\n\t}\n\t*ox1 = ix1;\n\t*ox2 = ix2;\n}\n\n// Sets all voxels along a X/Y plane at a given point\n// on axis Z\nvoid setplane_z(int z)\n{\n\tint i;\n\n\tif (z>=0 && z<8)\n\t{\n\t\tfor (i=0;i<8;i++)\n\t\t\tcube[z][i] = 0xff;\n\t}\n}\n\n// Clears voxels in the same manner as above\nvoid clrplane_z (int z)\n{\n\tint i;\n\n\tif (z>=0 && z<8)\n\t{\n\t\tfor (i=0;i<8;i++)\n\t\t\tcube[z][i] = 0x00;\n\t}\n}\n\nvoid setplane_x(int x)\n{\n\tint z, y;\n\n\tif (x>=0 && x<8)\n\t{\n\t\tfor (z=0;z<8;z++)\n\t\t{\n\t\t\tfor (y=0;y<8;y++)\n\t\t\t{\n\t\t\t\tcube[z][y] |= (1 << x);\n\t\t\t}\n\t\t}\n\t}\n}\n\nvoid clrplane_x(int x)\n{\n\tint z;\n\tint y;\n\tif (x>=0 && x<8)\n\t{\n\t\tfor (z=0;z<8;z++)\n\t\t{\n\t\t\tfor (y=0;y<8;y++)\n\t\t\t{\n\t\t\t\tcube[z][y] &= ~(1 << x);\n\t\t\t}\n\t\t}\n\t}\n}\n\nvoid setplane_y(int y)\n{\n\tint z;\n\tif (y>=0 && y<8)\n\t{\n\t\tfor (z=0;z<8;z++)\n\t\t\tcube[z][y] = 0xff;\n\t}\n}\n\nvoid clrplane_y(int y)\n{\n\tint z;\n\tif (y>=0 && y<8)\n\t{\n\t\tfor (z=0;z<8;z++)\n\t\t\tcube[z][y] = 0x00;\n\t}\n}\n\nvoid setplane(char axis, unsigned char i)\n{\n    switch (axis)\n    {\n        case AXIS_X:\n            setplane_x(i);\n            break;\n\n       case AXIS_Y:\n            setplane_y(i);\n            break;\n\n       case AXIS_Z:\n            setplane_z(i);\n            break;\n    }\n}\n\nvoid clrplane(char axis, unsigned char i)\n{\n    switch (axis)\n    {\n        case AXIS_X:\n            clrplane_x(i);\n            break;\n\n       case AXIS_Y:\n            clrplane_y(i);\n            break;\n\n       case AXIS_Z:\n            clrplane_z(i);\n            break;\n    }\n}\n\n// Fill a value into all 64 byts of the cube buffer\n// Mostly used for clearing. fill(0x00)\n// or setting all on. fill(0xff)\nvoid fill(unsigned char pattern)\n{\n\tint z;\n\tint y;\n\tfor (z=0;z<8;z++)\n\t{\n\t\tfor (y=0;y<8;y++)\n\t\t{\n\t\t\tcube[z][y] = pattern;\n\t\t}\n\t}\n}\n\n// Returns a byte with a row of 1's drawn in it.\n// byteline(2,5) gives 0b00111100\nchar byteline(int start, int end)\n{\n\treturn (0xff << start) & ~(0xff << (end+1));\n}\n\n// Draw a box with all walls drawn and all voxels inside set\nvoid box_filled(int x1, int y1, int z1, int x2, int y2, int z2)\n{\n\tint iy;\n\tint iz;\n\n\targorder(x1, x2, &x1, &x2);\n\targorder(y1, y2, &y1, &y2);\n\targorder(z1, z2, &z1, &z2);\n\n\tfor (iz=z1;iz<=z2;iz++)\n\t{\n\t\tfor (iy=y1;iy<=y2;iy++)\n\t\t{\n\t\t\tcube[iz][iy] |= byteline(x1, x2);\n\t\t}\n\t}\n\n}\n\n// Darw a hollow box with side walls.\nvoid box_walls(int x1, int y1, int z1, int x2, int y2, int z2)\n{\n\tint iy;\n\tint iz;\n\n\targorder(x1, x2, &x1, &x2);\n\targorder(y1, y2, &y1, &y2);\n\targorder(z1, z2, &z1, &z2);\n\n\tfor (iz=z1;iz<=z2;iz++)\n\t{\n\t\tfor (iy=y1;iy<=y2;iy++)\n\t\t{\n\t\t\tif (iy == y1 || iy == y2 || iz == z1 || iz == z2)\n\t\t\t{\n\t\t\t\tcube[iz][iy] = byteline(x1, x2);\n\t\t\t} else\n\t\t\t{\n\t\t\t\tcube[iz][iy] |= ((0x01 << x1) | (0x01 << x2));\n\t\t\t}\n\t\t}\n\t}\n\n}\n\n// Draw a wireframe box. This only draws the corners and edges,\n// no walls.\nvoid box_wireframe(int x1, int y1, int z1, int x2, int y2, int z2)\n{\n\tint iy;\n\tint iz;\n\n\targorder(x1, x2, &x1, &x2);\n\targorder(y1, y2, &y1, &y2);\n\targorder(z1, z2, &z1, &z2);\n\n\t// Lines along X axis\n\tcube[z1][y1] = byteline(x1, x2);\n\tcube[z1][y2] = byteline(x1, x2);\n\tcube[z2][y1] = byteline(x1, x2);\n\tcube[z2][y2] = byteline(x1, x2);\n\n\t// Lines along Y axis\n\tfor (iy=y1;iy<=y2;iy++)\n\t{\n\t\tsetvoxel(x1, iy, z1);\n\t\tsetvoxel(x1, iy, z2);\n\t\tsetvoxel(x2, iy, z1);\n\t\tsetvoxel(x2, iy, z2);\n\t}\n\n\t// Lines along Z axis\n\tfor (iz=z1;iz<=z2;iz++)\n\t{\n\t\tsetvoxel(x1, y1, iz);\n\t\tsetvoxel(x1, y2, iz);\n\t\tsetvoxel(x2, y1, iz);\n\t\tsetvoxel(x2, y2, iz);\n\t}\n\n}\n\n// Draw a line between any coordinates in 3d space.\n// Uses integer values for input, so dont expect smooth animations.\nvoid line(int x1, int y1, int z1, int x2, int y2, int z2)\n{\n    int x, y, z, dx, dy, dz;\n    int lasty, lastz;\n\n    // We always want to draw the line from x=0 to x=7.\n    // If x1 is bigget than x2, we need to flip all the values.\n    if (x1 > x2) {\n        int tmp;\n        tmp = x2; x2 = x1; x1 = tmp;\n        tmp = y2; y2 = y1; y1 = tmp;\n        tmp = z2; z2 = z1; z1 = tmp;\n    }\n    dx = x2 - x1;\n\n    if (y1 > y2) {\n        dy = y1 - y2;\n        lasty = y2;\n    } else {\n        dy = y2 - y1;\n        lasty = y1;\n    }\n\n    if (z1 > z2) {\n        dz = z1 - z2;\n        lastz = z2;\n    } else {\n        dz = z2 - z1;\n        lastz = z1;\n    }\n\n    // For each step of x, y increments by:\n    for (x = x1; x <= x2; x++) {\n        y = (dy * (x-x1) / dx) + y1;\n        z = (dz * (x-x1) / dx) + z1;\n        setvoxel(x, y, z);\n    }\n}\n\n// Shift the entire contents of the cube along an axis\n// This is great for effects where you want to draw something\n// on one side of the cube and have it flow towards the other\n// side. Like rain flowing down the Z axiz.\nvoid shift(char axis, int direction)\n{\n\tint i, x, y;\n\tint ii, iii;\n\tint state;\n\n\tfor (i = 0; i < 8; i++)\n\t{\n\t\tif (direction == -1)\n\t\t{\n\t\t\tii = i;\n\t\t} else\n\t\t{\n\t\t\tii = (7-i);\n\t\t}\n\n\n\t\tfor (x = 0; x < 8; x++)\n\t\t{\n\t\t\tfor (y = 0; y < 8; y++)\n\t\t\t{\n\t\t\t\tif (direction == -1)\n\t\t\t\t{\n\t\t\t\t\tiii = ii+1;\n\t\t\t\t} else\n\t\t\t\t{\n\t\t\t\t\tiii = ii-1;\n\t\t\t\t}\n\n\t\t\t\tif (axis == AXIS_Z)\n\t\t\t\t{\n\t\t\t\t\tstate = getvoxel(x, y, iii);\n\t\t\t\t\taltervoxel(x, y, ii, state);\n\t\t\t\t}\n\n\t\t\t\tif (axis == AXIS_Y)\n\t\t\t\t{\n\t\t\t\t\tstate = getvoxel(x, iii, y);\n\t\t\t\t\taltervoxel(x, ii, y, state);\n\t\t\t\t}\n\n\t\t\t\tif (axis == AXIS_X)\n\t\t\t\t{\n\t\t\t\t\tstate = getvoxel(iii, y, x);\n\t\t\t\t\taltervoxel(ii, y, x, state);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tif (direction == -1)\n\t{\n\t\ti = 7;\n\t} else\n\t{\n\t\ti = 0;\n\t}\n\n\tfor (x = 0; x < 8; x++)\n\t{\n\t\tfor (y = 0; y < 8; y++)\n\t\t{\n\t\t\tif (axis == AXIS_Z)\n\t\t\t\tclrvoxel(x, y, i);\n\n\t\t\tif (axis == AXIS_Y)\n\t\t\t\tclrvoxel(x, i, y);\n\n\t\t\tif (axis == AXIS_X)\n\t\t\t\tclrvoxel(i, y, x);\n\t\t}\n\t}\n}\n\n// ==========================================================================================\n//   Effect functions\n// ==========================================================================================\n\nvoid fireworks(int iterations, int delay)\n{\n#define NFIREWORKS 30\n    int i, f, e;\n    int origin_x = 3;\n    int origin_y = 3;\n    int origin_z = 3;\n    int rand_y, rand_x, rand_z;\n    int slowrate, gravity;\n\n    // Particles and their position, x,y,z and their movement, dx,dy,dz.\n    // Scaled by 100 for integer arith.\n    int particles[NFIREWORKS][6];\n\n    fill(0x00);\n    for (i=0; i<iterations; i++) {\n\n        origin_x = rand() % 4;\n        origin_y = rand() % 4;\n        origin_z = rand() % 2;\n        origin_z += 5;\n        origin_x += 2;\n        origin_y += 2;\n\n        // shoot a particle up in the air\n        for (e=0; e<origin_z; e++) {\n            setvoxel(origin_x, origin_y, e);\n            delay_ms(300+250*e);\n            fill(0x00);\n        }\n\n        // Fill particle array\n        for (f=0; f<NFIREWORKS; f++) {\n            // Position\n            particles[f][0] = origin_x * 100;\n            particles[f][1] = origin_y * 100;\n            particles[f][2] = origin_z * 100;\n\n            rand_x = rand() % 200;\n            rand_y = rand() % 200;\n            rand_z = rand() % 200;\n\n            // Movement\n            particles[f][3] = 100 - rand_x; // dx\n            particles[f][4] = 100 - rand_y; // dy\n            particles[f][5] = 100 - rand_z; // dz\n        }\n\n        // explode\n        for (e=0; e<25; e++) {\n            // Coefficient = tan((e+0.1)/20) * 1000.\n            static const int coeff[25] = {\n                5, 55, 105, 156, 207, 260, 314, 370, 428, 489,\n                552, 620, 691, 768, 850, 940, 1039, 1149, 1273, 1413,\n                1574, 1763, 1989, 2264, 2610,\n            };\n\n            slowrate = 100 + coeff[e];\n            gravity = coeff[e] / 20;\n\n            for (f=0; f<NFIREWORKS; f++) {\n                particles[f][0] += particles[f][3] * 100 / slowrate;\n                particles[f][1] += particles[f][4] * 100 / slowrate;\n                particles[f][2] += particles[f][5] * 100 / slowrate;\n                particles[f][2] -= gravity;\n\n                setvoxel(particles[f][0] / 100,\n                         particles[f][1] / 100,\n                         particles[f][2] / 100);\n            }\n            delay_ms(delay);\n            fill(0x00);\n        }\n    }\n}\n\nconst unsigned char LUT[65] = {\n    0, 8, 17, 26, 35, 43, 52, 60, 69, 77,\n    85, 93, 100, 107, 114, 121, 127, 134, 139, 145,\n    150, 155, 159, 163, 167, 170, 173, 175, 177, 179,\n    180, 180, 181, 180, 180, 179, 177, 175, 173, 170,\n    167, 163, 159, 155, 150, 145, 139, 134, 127, 121,\n    114, 107, 100, 93, 85, 77, 69, 60, 52, 43,\n    35, 26, 17, 8, 0,\n};\n\nint totty_sin(int sin_of)\n{\n    unsigned char inv = 0;\n    if (sin_of < 0) {\n        sin_of = -sin_of;\n        inv = 1;\n    }\n    sin_of &= 0x7f; //127\n    if (sin_of > 64) {\n        sin_of -= 64;\n        inv = 1-inv;\n    }\n    if (inv)\n        return -LUT[sin_of];\n    else\n        return LUT[sin_of];\n}\n\nint totty_cos(int cos_of)\n{\n    unsigned char inv = 0;\n\n    cos_of += 32;   // Simply rotate by 90 degrees for COS\n    cos_of &= 0x7f; // 127\n    if (cos_of > 64) {\n        cos_of -= 64;\n        inv = 1;\n    }\n    if (inv)\n        return -LUT[cos_of];\n    else\n        return LUT[cos_of];\n}\n\nvoid quad_ripples(int iterations, int delay)\n{\n    // 16 values for square root of a^2+b^2.  index a*4+b = 10*sqrt\n    // This gives the distance to 3.5,3.5 from the point\n    unsigned char sqrt_LUT[] = {\n        49, 43, 38, 35, 43, 35, 29, 26, 38, 29, 21, 16, 35, 25, 16, 7\n    };\n    unsigned char x, y, height, distance;\n    int i;\n\n    for (i=0; i<iterations*4; i+=4) {\n        fill(0x00);\n        for (x=0; x<4; x++) {\n            for (y=0; y<4; y++) {\n                // x+y*4 gives no. from 0-15 for sqrt_LUT\n                distance = sqrt_LUT[x + y*4]; // distance is 0-50 roughly\n\n                // height is sin of distance + iteration*4\n                //height = 4 + totty_sin(distance+i) / 52;\n                height = (196 + totty_sin(distance+i)) / 49;\n\n                // Use 4-way mirroring to save on calculations\n                setvoxel(x,   y,        height);\n                setvoxel(7-x, y,        height);\n                setvoxel(x,   7-y,      height);\n                setvoxel(7-x, 7-y,      height);\n                setvoxel(x,   y,        7-height);\n                setvoxel(7-x, y,        7-height);\n                setvoxel(x,   7-y,      7-height);\n                setvoxel(7-x, 7-y,      7-height);\n                setvoxel(x,   height,   y);\n                setvoxel(7-x, height,   y);\n                setvoxel(x,   height,   7-y);\n                setvoxel(7-x, height,   7-y);\n                setvoxel(x,   7-height, y);\n                setvoxel(7-x, 7-height, y);\n                setvoxel(x,   7-height, 7-y);\n                setvoxel(7-x, 7-height, 7-y);\n            }\n        }\n        delay_ms(delay);\n    }\n}\n\n// **********************************************************\n\nvoid effect_random_sparkle_flash(int iterations, int voxels, int delay)\n{\n\tint i;\n\tint v;\n\tfor (i = 0; i < iterations; i++)\n\t{\n\t\tfor (v=0;v<=voxels;v++)\n\t\t\tsetvoxel(rand()%8, rand()%8, rand()%8);\n\n        delay_ms(delay);\n\t\tfill(0x00);\n\t}\n}\n\n// blink 1 random voxel, blink 2 random voxels..... blink 20 random voxels\n// and back to 1 again.\nvoid effect_random_sparkle(void)\n{\n\tint i;\n\n\tfor (i=1;i<20;i++)\n\t{\n        effect_random_sparkle_flash(5, i, 100);\n\t}\n\n\tfor (i=20;i>=1;i--)\n\t{\n        effect_random_sparkle_flash(5, i, 100);\n\t}\n\n}\n\nint effect_telcstairs_do(int x, int val, int delay)\n{\n\tint y, z;\n\n\tfor(y = 0, z = x; y <= z; y++, x--)\n\t{\n\t\tif(x < CUBE_SIZE && y < CUBE_SIZE)\n\t\t{\n\t\t\tcube[x][y] = val;\n\t\t}\n\t}\n\tdelay_ms(delay);\n\treturn z;\n}\n\nvoid effect_telcstairs(int invert, int delay, int val)\n{\n\tint x;\n\n\tif(invert)\n\t{\n\t\tfor(x = CUBE_SIZE*2; x >= 0; x--)\n\t\t{\n\t\t\tx = effect_telcstairs_do(x, val, delay);\n\t\t}\n\t}\n\telse\n\t{\n\t\tfor(x = 0; x < CUBE_SIZE*2; x++)\n\t\t{\n\t\t\tx = effect_telcstairs_do(x, val, delay);\n\t\t}\n\t}\n}\n\nvoid draw_positions_axis(char axis, unsigned char positions[64], int invert)\n{\n\tint x, y, p;\n\n\tfill(0x00);\n\n\tfor (x=0; x<8; x++)\n\t{\n\t\tfor (y=0; y<8; y++)\n\t\t{\n\t\t\tif (invert)\n\t\t\t{\n\t\t\t\tp = (7-positions[(x*8)+y]);\n\t\t\t} else\n\t\t\t{\n\t\t\t\tp = positions[(x*8)+y];\n\t\t\t}\n\n\t\t\tif (axis == AXIS_Z)\n\t\t\t\tsetvoxel(x, y, p);\n\n\t\t\tif (axis == AXIS_Y)\n\t\t\t\tsetvoxel(x, p, y);\n\n\t\t\tif (axis == AXIS_X)\n\t\t\t\tsetvoxel(p, y, x);\n\t\t}\n\t}\n\n}\n\nvoid effect_wormsqueeze(int size, int axis, int direction, int iterations,\n    int delay)\n{\n\tint x, y, i, j, k, dx, dy;\n\tint cube_size;\n\tint origin = 0;\n\n\tif (direction == -1)\n\t\torigin = 7;\n\n\tcube_size = 8-(size-1);\n\n\tx = rand()%cube_size;\n\ty = rand()%cube_size;\n\n\tfor (i=0; i<iterations; i++)\n\t{\n\t\tdx = ((rand()%3)-1);\n\t\tdy = ((rand()%3)-1);\n\n\t\tif ((x+dx) > 0 && (x+dx) < cube_size)\n\t\t\tx += dx;\n\n\t\tif ((y+dy) > 0 && (y+dy) < cube_size)\n\t\t\ty += dy;\n\n\t\tshift(axis, direction);\n\n\n\t\tfor (j=0; j<size;j++)\n\t\t{\n\t\t\tfor (k=0; k<size;k++)\n\t\t\t{\n\t\t\t\tif (axis == AXIS_Z)\n\t\t\t\t\tsetvoxel(x+j, y+k, origin);\n\n\t\t\t\tif (axis == AXIS_Y)\n\t\t\t\t\tsetvoxel(x+j, origin, y+k);\n\n\t\t\t\tif (axis == AXIS_X)\n\t\t\t\t\tsetvoxel(origin, y+j, x+k);\n\t\t\t}\n\t\t}\n\n\t\tdelay_ms(delay);\n\t}\n}\n\nvoid line_3d(int x1, int y1, int z1, int x2, int y2, int z2)\n{\n    int i, dx, dy, dz, l, m, n, x_inc, y_inc, z_inc,\n        err_1, err_2, dx2, dy2, dz2;\n    int pixel[3];\n\n    pixel[0] = x1;\n    pixel[1] = y1;\n    pixel[2] = z1;\n    dx = x2 - x1;\n    dy = y2 - y1;\n    dz = z2 - z1;\n    if (dx >= 0) {\n        x_inc = 1;\n        l = dx;\n    } else {\n        x_inc = -1;\n        l = -dx;\n    }\n    if (dy >= 0) {\n        y_inc = 1;\n        m = dy;\n    } else {\n        y_inc = -1;\n        m = -dy;\n    }\n    if (dz >= 0) {\n        z_inc = 1;\n        n = dz;\n    } else {\n        z_inc = -1;\n        n = -dz;\n    }\n    dx2 = l << 1;\n    dy2 = m << 1;\n    dz2 = n << 1;\n    if ((l >= m) && (l >= n)) {\n        err_1 = dy2 - l;\n        err_2 = dz2 - l;\n        for (i = 0; i < l; i++) {\n            //PUT_PIXEL(pixel);\n            setvoxel(pixel[0], pixel[1], pixel[2]);\n            //printf(\"Setting %i %i %i \\n\", pixel[0], pixel[1], pixel[2]);\n            if (err_1 > 0) {\n                pixel[1] += y_inc;\n                err_1 -= dx2;\n            }\n            if (err_2 > 0) {\n                pixel[2] += z_inc;\n                err_2 -= dx2;\n            }\n            err_1 += dy2;\n            err_2 += dz2;\n            pixel[0] += x_inc;\n        }\n    } else if ((m >= l) && (m >= n)) {\n        err_1 = dx2 - m;\n        err_2 = dz2 - m;\n        for (i = 0; i < m; i++) {\n            //PUT_PIXEL(pixel);\n            setvoxel(pixel[0], pixel[1], pixel[2]);\n            //printf(\"Setting %i %i %i \\n\", pixel[0], pixel[1], pixel[2]);\n            if (err_1 > 0) {\n                pixel[0] += x_inc;\n                err_1 -= dy2;\n            }\n            if (err_2 > 0) {\n                pixel[2] += z_inc;\n                err_2 -= dy2;\n            }\n            err_1 += dx2;\n            err_2 += dz2;\n            pixel[1] += y_inc;\n        }\n    } else {\n        err_1 = dy2 - n;\n        err_2 = dx2 - n;\n        for (i = 0; i < n; i++) {\n            setvoxel(pixel[0], pixel[1], pixel[2]);\n            //printf(\"Setting %i %i %i \\n\", pixel[0], pixel[1], pixel[2]);\n            //PUT_PIXEL(pixel);\n            if (err_1 > 0) {\n                pixel[1] += y_inc;\n                err_1 -= dz2;\n            }\n            if (err_2 > 0) {\n                pixel[0] += x_inc;\n                err_2 -= dz2;\n            }\n            err_1 += dy2;\n            err_2 += dx2;\n            pixel[2] += z_inc;\n        }\n    }\n    setvoxel(pixel[0], pixel[1], pixel[2]);\n    //printf(\"Setting %i %i %i \\n\", pixel[0], pixel[1], pixel[2]);\n    //PUT_PIXEL(pixel);\n}\n\n#if 0\nvoid sinelines(int iterations, int delay)\n{\n    int i, x;\n\n    float left, right, sine_base, x_dividor, ripple_height;\n\n    for (i=0; i<iterations; i++) {\n        for (x=0; x<8; x++) {\n            x_dividor = 2 + sin((float)i / 100) + 1;\n            ripple_height = 3 + (sin((float)i / 200) + 1) * 6;\n\n            sine_base = (float) i/40 + (float) x/x_dividor;\n\n            left = 4 + sin(sine_base) * ripple_height;\n            right = 4 + cos(sine_base) * ripple_height;\n            right = 7-left;\n\n            //printf(\"%i %i \\n\", (int) left, (int) right);\n\n            line_3d(0-3, x, (int) left, 7+3, x, (int) right);\n            //line_3d((int) right, 7, x);\n        }\n\n        // delay_ms(delay);\n        fill(0x00);\n    }\n}\n#endif\n\nvoid effect_boxside_randsend_parallel(char axis, int origin, int delay,\n    int mode)\n{\n\tint i;\n\tint done;\n\tunsigned char cubepos[64];\n\tunsigned char pos[64];\n\tint notdone = 1;\n\tint notdone2 = 1;\n\tint sent = 0;\n\n\tfor (i=0;i<64;i++)\n\t{\n\t\tpos[i] = 0;\n\t}\n\n\twhile (notdone)\n\t{\n\t\tif (mode == 1)\n\t\t{\n\t\t\tnotdone2 = 1;\n\t\t\twhile (notdone2 && sent<64)\n\t\t\t{\n\t\t\t\ti = rand()%64;\n\t\t\t\tif (pos[i] == 0)\n\t\t\t\t{\n\t\t\t\t\tsent++;\n\t\t\t\t\tpos[i] += 1;\n\t\t\t\t\tnotdone2 = 0;\n\t\t\t\t}\n\t\t\t}\n\t\t} else if (mode == 2)\n\t\t{\n\t\t\tif (sent<64)\n\t\t\t{\n\t\t\t\tpos[sent] += 1;\n\t\t\t\tsent++;\n\t\t\t}\n\t\t}\n\n\t\tdone = 0;\n\t\tfor (i=0;i<64;i++)\n\t\t{\n\t\t\tif (pos[i] > 0 && pos[i] <7)\n\t\t\t{\n\t\t\t\tpos[i] += 1;\n\t\t\t}\n\n\t\t\tif (pos[i] == 7)\n\t\t\t\tdone++;\n\t\t}\n\n\t\tif (done == 64)\n\t\t\tnotdone = 0;\n\n\t\tfor (i=0;i<64;i++)\n\t\t{\n\t\t\tif (origin == 0)\n\t\t\t{\n\t\t\t\tcubepos[i] = pos[i];\n\t\t\t} else\n\t\t\t{\n\t\t\t\tcubepos[i] = (7-pos[i]);\n\t\t\t}\n\t\t}\n\n\t\tdelay_ms(delay);\n\t\tdraw_positions_axis(axis, cubepos, 0);\n\t}\n\n}\n\nvoid effect_rain(int iterations)\n{\n\tint i, ii;\n\tint rnd_x;\n\tint rnd_y;\n\tint rnd_num;\n\n\tfor (ii=0;ii<iterations;ii++)\n\t{\n\t\trnd_num = rand()%4;\n\n\t\tfor (i=0; i < rnd_num;i++)\n\t\t{\n\t\t\trnd_x = rand()%8;\n\t\t\trnd_y = rand()%8;\n\t\t\tsetvoxel(rnd_x, rnd_y, 7);\n\t\t}\n\n        delay_ms(500);\n\t\tshift(AXIS_Z, -1);\n\t}\n}\n\n// Set or clear exactly 512 voxels in a random order.\nvoid effect_random_filler(int delay, int state)\n{\n\tint x, y, z;\n\tint loop = 0;\n\n    if (state == 1) {\n\t\tfill(0x00);\n    } else {\n\t\tfill(0xff);\n\t}\n\n    while (loop < 511)\n\t{\n\t\tx = rand()%8;\n\t\ty = rand()%8;\n\t\tz = rand()%8;\n\n        if ((state == 0 && getvoxel(x, y, z) == 1) ||\n            (state == 1 && getvoxel(x, y, z) == 0))\n\t\t{\n\t\t\taltervoxel(x, y, z, state);\n\t\t\tdelay_ms(delay);\n\t\t\tloop++;\n\t\t}\n\t}\n}\n\nvoid effect_axis_updown_randsuspend(char axis, int delay, int sleep, int invert)\n{\n\tunsigned char positions[64];\n\tunsigned char destinations[64];\n\n\tint i, px;\n\n    // Set 64 random positions\n\tfor (i=0; i<64; i++)\n\t{\n\t\tpositions[i] = 0; // Set all starting positions to 0\n\t\tdestinations[i] = rand()%8;\n\t}\n\n    // Loop 8 times to allow destination 7 to reach all the way\n\tfor (i=0; i<8; i++)\n\t{\n        // For every iteration, move all position one step closer to their destination\n\t\tfor (px=0; px<64; px++)\n\t\t{\n\t\t\tif (positions[px]<destinations[px])\n\t\t\t{\n\t\t\t\tpositions[px]++;\n\t\t\t}\n\t\t}\n        // Draw the positions and take a nap\n\t\tdraw_positions_axis(axis, positions, invert);\n\t\tdelay_ms(delay);\n\t}\n\n    // Set all destinations to 7 (opposite from the side they started out)\n\tfor (i=0; i<64; i++)\n\t{\n\t\tdestinations[i] = 7;\n\t}\n\n    // Suspend the positions in mid-air for a while\n\tdelay_ms(sleep);\n\n    // Then do the same thing one more time\n\tfor (i=0; i<8; i++)\n\t{\n\t\tfor (px=0; px<64; px++)\n\t\t{\n\t\t\tif (positions[px]<destinations[px])\n\t\t\t{\n\t\t\t\tpositions[px]++;\n\t\t\t}\n\t\t\tif (positions[px]>destinations[px])\n\t\t\t{\n\t\t\t\tpositions[px]--;\n\t\t\t}\n\t\t}\n\t\tdraw_positions_axis(axis, positions, invert);\n\t\tdelay_ms(delay);\n\t}\n}\n\nvoid effect_blinky2()\n{\n\tint i, r;\n\tfill(0x00);\n\n\tfor (r=0;r<2;r++)\n\t{\n        i = 350;\n\t\twhile (i>0)\n\t\t{\n\t\t\tfill(0x00);\n\t\t\tdelay_ms(i);\n\n\t\t\tfill(0xff);\n\t\t\tdelay_ms(100);\n\n            i = i - (7 + (500 / (i/10)));\n\t\t}\n\n        delay_ms(500);\n\n        i = 350;\n\t\twhile (i>0)\n\t\t{\n\t\t\tfill(0x00);\n            delay_ms(351-i);\n\n\t\t\tfill(0xff);\n\t\t\tdelay_ms(100);\n\n            i = i - (7 + (500 / (i/10)));\n\t\t}\n\t}\n}\n\n// Draw a plane on one axis and send it back and forth once.\nvoid effect_planboing(int plane, int speed)\n{\n\tint i;\n\tfor (i=0;i<8;i++)\n\t{\n\t\tfill(0x00);\n                setplane(plane, i);\n\t\tdelay_ms(speed);\n\t}\n\n\tfor (i=7;i>=0;i--)\n\t{\n\t\tfill(0x00);\n                setplane(plane, i);\n\t\tdelay_ms(speed);\n\t}\n}\n\n\n//********************************************************\n\n// ********************************************************\nconst char font_data[128][8] =\n{\n  { 0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00 },    // 0 :\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n\n  { 0x00,  0x3E,  0x41,  0x55,  0x41,  0x55,  0x49,  0x3E },    // 1 : \u0001\n                //              |          |\n                //              |   *****  |\n                //              |  *     * |\n                //              |  * * * * |\n                //              |  *     * |\n                //              |  * * * * |\n                //              |  *  *  * |\n                //              |   *****  |\n\n  { 0x00,  0x3E,  0x7F,  0x6B,  0x7F,  0x6B,  0x77,  0x3E },    // 2 : \u0002\n                //              |          |\n                //              |   *****  |\n                //              |  ******* |\n                //              |  ** * ** |\n                //              |  ******* |\n                //              |  ** * ** |\n                //              |  *** *** |\n                //              |   *****  |\n\n  { 0x00,  0x22,  0x77,  0x7F,  0x7F,  0x3E,  0x1C,  0x08 },    // 3 : \u0003\n                //              |          |\n                //              |   *   *  |\n                //              |  *** *** |\n                //              |  ******* |\n                //              |  ******* |\n                //              |   *****  |\n                //              |    ***   |\n                //              |     *    |\n\n  { 0x00,  0x08,  0x1C,  0x3E,  0x7F,  0x3E,  0x1C,  0x08 },    // 4 : \u0004\n                //              |          |\n                //              |     *    |\n                //              |    ***   |\n                //              |   *****  |\n                //              |  ******* |\n                //              |   *****  |\n                //              |    ***   |\n                //              |     *    |\n\n  { 0x00,  0x08,  0x1C,  0x2A,  0x7F,  0x2A,  0x08,  0x1C },    // 5 : \u0005\n                //              |          |\n                //              |     *    |\n                //              |    ***   |\n                //              |   * * *  |\n                //              |  ******* |\n                //              |   * * *  |\n                //              |     *    |\n                //              |    ***   |\n\n  { 0x00,  0x08,  0x1C,  0x3E,  0x7F,  0x3E,  0x08,  0x1C },    // 6 : \u0006\n                //              |          |\n                //              |     *    |\n                //              |    ***   |\n                //              |   *****  |\n                //              |  ******* |\n                //              |   *****  |\n                //              |     *    |\n                //              |    ***   |\n\n  { 0x00,  0x00,  0x1C,  0x3E,  0x3E,  0x3E,  0x1C,  0x00 },    // 7 :\n                //              |          |\n                //              |          |\n                //              |    ***   |\n                //              |   *****  |\n                //              |   *****  |\n                //              |   *****  |\n                //              |    ***   |\n                //              |          |\n\n  { 0xFF,  0xFF,  0xE3,  0xC1,  0xC1,  0xC1,  0xE3,  0xFF },    // 8 : \b\n                //              | ******** |\n                //              | ******** |\n                //              | ***   ** |\n                //              | **     * |\n                //              | **     * |\n                //              | **     * |\n                //              | ***   ** |\n                //              | ******** |\n\n  { 0x00,  0x00,  0x1C,  0x22,  0x22,  0x22,  0x1C,  0x00 },    // 9 :\n                //              |          |\n                //              |          |\n                //              |    ***   |\n                //              |   *   *  |\n                //              |   *   *  |\n                //              |   *   *  |\n                //              |    ***   |\n                //              |          |\n\n  { 0xFF,  0xFF,  0xE3,  0xDD,  0xDD,  0xDD,  0xE3,  0xFF },    // 10 :\n\n                //              | ******** |\n                //              | ******** |\n                //              | ***   ** |\n                //              | ** *** * |\n                //              | ** *** * |\n                //              | ** *** * |\n                //              | ***   ** |\n                //              | ******** |\n\n  { 0x00,  0x0F,  0x03,  0x05,  0x39,  0x48,  0x48,  0x30 },    // 11 :\n\n                //              |          |\n                //              |     **** |\n                //              |       ** |\n                //              |      * * |\n                //              |   ***  * |\n                //              |  *  *    |\n                //              |  *  *    |\n                //              |   **     |\n\n  { 0x00,  0x08,  0x3E,  0x08,  0x1C,  0x22,  0x22,  0x1C },    // 12 : \f\n                //              |          |\n                //              |     *    |\n                //              |   *****  |\n                //              |     *    |\n                //              |    ***   |\n                //              |   *   *  |\n                //              |   *   *  |\n                //              |    ***   |\n\n  { 0x00,  0x18,  0x14,  0x10,  0x10,  0x30,  0x70,  0x60 },    // 13 :\n\n                //              |          |\n                //              |    **    |\n                //              |    * *   |\n                //              |    *     |\n                //              |    *     |\n                //              |   **     |\n                //              |  ***     |\n                //              |  **      |\n\n  { 0x00,  0x0F,  0x19,  0x11,  0x13,  0x37,  0x76,  0x60 },    // 14 : \u000e\n                //              |          |\n                //              |     **** |\n                //              |    **  * |\n                //              |    *   * |\n                //              |    *  ** |\n                //              |   ** *** |\n                //              |  *** **  |\n                //              |  **      |\n\n  { 0x00,  0x08,  0x2A,  0x1C,  0x77,  0x1C,  0x2A,  0x08 },    // 15 : \u000f\n                //              |          |\n                //              |     *    |\n                //              |   * * *  |\n                //              |    ***   |\n                //              |  *** *** |\n                //              |    ***   |\n                //              |   * * *  |\n                //              |     *    |\n\n  { 0x00,  0x60,  0x78,  0x7E,  0x7F,  0x7E,  0x78,  0x60 },    // 16 : \u0010\n                //              |          |\n                //              |  **      |\n                //              |  ****    |\n                //              |  ******  |\n                //              |  ******* |\n                //              |  ******  |\n                //              |  ****    |\n                //              |  **      |\n\n  { 0x00,  0x03,  0x0F,  0x3F,  0x7F,  0x3F,  0x0F,  0x03 },    // 17 : \u0011\n                //              |          |\n                //              |       ** |\n                //              |     **** |\n                //              |   ****** |\n                //              |  ******* |\n                //              |   ****** |\n                //              |     **** |\n                //              |       ** |\n\n  { 0x00,  0x08,  0x1C,  0x2A,  0x08,  0x2A,  0x1C,  0x08 },    // 18 : \u0012\n                //              |          |\n                //              |     *    |\n                //              |    ***   |\n                //              |   * * *  |\n                //              |     *    |\n                //              |   * * *  |\n                //              |    ***   |\n                //              |     *    |\n\n  { 0x00,  0x66,  0x66,  0x66,  0x66,  0x00,  0x66,  0x66 },    // 19 : \u0013\n                //              |          |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |          |\n                //              |  **  **  |\n                //              |  **  **  |\n\n  { 0x00,  0x3F,  0x65,  0x65,  0x3D,  0x05,  0x05,  0x05 },    // 20 : \u0014\n                //              |          |\n                //              |   ****** |\n                //              |  **  * * |\n                //              |  **  * * |\n                //              |   **** * |\n                //              |      * * |\n                //              |      * * |\n                //              |      * * |\n\n  { 0x00,  0x0C,  0x32,  0x48,  0x24,  0x12,  0x4C,  0x30 },    // 21 : \u0015\n                //              |          |\n                //              |     **   |\n                //              |   **  *  |\n                //              |  *  *    |\n                //              |   *  *   |\n                //              |    *  *  |\n                //              |  *  **   |\n                //              |   **     |\n\n  { 0x00,  0x00,  0x00,  0x00,  0x00,  0x7F,  0x7F,  0x7F },    // 22 : \u0016\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |  ******* |\n                //              |  ******* |\n                //              |  ******* |\n\n  { 0x00,  0x08,  0x1C,  0x2A,  0x08,  0x2A,  0x1C,  0x3E },    // 23 : \u0017\n                //              |          |\n                //              |     *    |\n                //              |    ***   |\n                //              |   * * *  |\n                //              |     *    |\n                //              |   * * *  |\n                //              |    ***   |\n                //              |   *****  |\n\n  { 0x00,  0x08,  0x1C,  0x3E,  0x7F,  0x1C,  0x1C,  0x1C },    // 24 : \u0018\n                //              |          |\n                //              |     *    |\n                //              |    ***   |\n                //              |   *****  |\n                //              |  ******* |\n                //              |    ***   |\n                //              |    ***   |\n                //              |    ***   |\n\n  { 0x00,  0x1C,  0x1C,  0x1C,  0x7F,  0x3E,  0x1C,  0x08 },    // 25 : \u0019\n                //              |          |\n                //              |    ***   |\n                //              |    ***   |\n                //              |    ***   |\n                //              |  ******* |\n                //              |   *****  |\n                //              |    ***   |\n                //              |     *    |\n\n  { 0x00,  0x08,  0x0C,  0x7E,  0x7F,  0x7E,  0x0C,  0x08 },    // 26 : \u001a\n                //              |          |\n                //              |     *    |\n                //              |     **   |\n                //              |  ******  |\n                //              |  ******* |\n                //              |  ******  |\n                //              |     **   |\n                //              |     *    |\n\n  { 0x00,  0x08,  0x18,  0x3F,  0x7F,  0x3F,  0x18,  0x08 },    // 27 : \u001b\n                //              |          |\n                //              |     *    |\n                //              |    **    |\n                //              |   ****** |\n                //              |  ******* |\n                //              |   ****** |\n                //              |    **    |\n                //              |     *    |\n\n  { 0x00,  0x00,  0x00,  0x70,  0x70,  0x70,  0x7F,  0x7F },    // 28 : \u001c\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |  ***     |\n                //              |  ***     |\n                //              |  ***     |\n                //              |  ******* |\n                //              |  ******* |\n\n  { 0x00,  0x00,  0x14,  0x22,  0x7F,  0x22,  0x14,  0x00 },    // 29 : \u001d\n                //              |          |\n                //              |          |\n                //              |    * *   |\n                //              |   *   *  |\n                //              |  ******* |\n                //              |   *   *  |\n                //              |    * *   |\n                //              |          |\n\n  { 0x00,  0x08,  0x1C,  0x1C,  0x3E,  0x3E,  0x7F,  0x7F },    // 30 : \u001e\n                //              |          |\n                //              |     *    |\n                //              |    ***   |\n                //              |    ***   |\n                //              |   *****  |\n                //              |   *****  |\n                //              |  ******* |\n                //              |  ******* |\n\n  { 0x00,  0x7F,  0x7F,  0x3E,  0x3E,  0x1C,  0x1C,  0x08 },    // 31 : \u001f\n                //              |          |\n                //              |  ******* |\n                //              |  ******* |\n                //              |   *****  |\n                //              |   *****  |\n                //              |    ***   |\n                //              |    ***   |\n                //              |     *    |\n\n  { 0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00 },    // 32 :\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n\n  { 0x00,  0x18,  0x18,  0x18,  0x18,  0x18,  0x00,  0x18 },    // 33 : !\n                //              |          |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |          |\n                //              |    **    |\n\n  { 0x00,  0x36,  0x36,  0x14,  0x00,  0x00,  0x00,  0x00 },    // 34 : \"\n                //              |          |\n                //              |   ** **  |\n                //              |   ** **  |\n                //              |    * *   |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n\n  { 0x00,  0x36,  0x36,  0x7F,  0x36,  0x7F,  0x36,  0x36 },    // 35 : #\n                //              |          |\n                //              |   ** **  |\n                //              |   ** **  |\n                //              |  ******* |\n                //              |   ** **  |\n                //              |  ******* |\n                //              |   ** **  |\n                //              |   ** **  |\n\n  { 0x00,  0x08,  0x1E,  0x20,  0x1C,  0x02,  0x3C,  0x08 },    // 36 : $\n                //              |          |\n                //              |     *    |\n                //              |    ****  |\n                //              |   *      |\n                //              |    ***   |\n                //              |       *  |\n                //              |   ****   |\n                //              |     *    |\n\n  { 0x00,  0x60,  0x66,  0x0C,  0x18,  0x30,  0x66,  0x06 },    // 37 : %\n                //              |          |\n                //              |  **      |\n                //              |  **  **  |\n                //              |     **   |\n                //              |    **    |\n                //              |   **     |\n                //              |  **  **  |\n                //              |      **  |\n\n  { 0x00,  0x3C,  0x66,  0x3C,  0x28,  0x65,  0x66,  0x3F },    // 38 : &\n                //              |          |\n                //              |   ****   |\n                //              |  **  **  |\n                //              |   ****   |\n                //              |   * *    |\n                //              |  **  * * |\n                //              |  **  **  |\n                //              |   ****** |\n\n  { 0x00,  0x18,  0x18,  0x18,  0x30,  0x00,  0x00,  0x00 },    // 39 : '\n                //              |          |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |   **     |\n                //              |          |\n                //              |          |\n                //              |          |\n\n  { 0x00,  0x60,  0x30,  0x18,  0x18,  0x18,  0x30,  0x60 },    // 40 : (\n                //              |          |\n                //              |  **      |\n                //              |   **     |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |   **     |\n                //              |  **      |\n\n  { 0x00,  0x06,  0x0C,  0x18,  0x18,  0x18,  0x0C,  0x06 },    // 41 : )\n                //              |          |\n                //              |      **  |\n                //              |     **   |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |     **   |\n                //              |      **  |\n\n  { 0x00,  0x00,  0x36,  0x1C,  0x7F,  0x1C,  0x36,  0x00 },    // 42 : *\n                //              |          |\n                //              |          |\n                //              |   ** **  |\n                //              |    ***   |\n                //              |  ******* |\n                //              |    ***   |\n                //              |   ** **  |\n                //              |          |\n\n  { 0x00,  0x00,  0x08,  0x08,  0x3E,  0x08,  0x08,  0x00 },    // 43 : +\n                //              |          |\n                //              |          |\n                //              |     *    |\n                //              |     *    |\n                //              |   *****  |\n                //              |     *    |\n                //              |     *    |\n                //              |          |\n\n  { 0x00,  0x00,  0x00,  0x00,  0x30,  0x30,  0x30,  0x60 },    // 44 : ,\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |   **     |\n                //              |   **     |\n                //              |   **     |\n                //              |  **      |\n\n  { 0x00,  0x00,  0x00,  0x00,  0x3C,  0x00,  0x00,  0x00 },    // 45 : -\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |   ****   |\n                //              |          |\n                //              |          |\n                //              |          |\n\n  { 0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x60,  0x60 },    // 46 : .\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |  **      |\n                //              |  **      |\n\n  { 0x00,  0x00,  0x06,  0x0C,  0x18,  0x30,  0x60,  0x00 },    // 47 : /\n                //              |          |\n                //              |          |\n                //              |      **  |\n                //              |     **   |\n                //              |    **    |\n                //              |   **     |\n                //              |  **      |\n                //              |          |\n\n  { 0x00,  0x3C,  0x66,  0x6E,  0x76,  0x66,  0x66,  0x3C },    // 48 : 0\n                //              |          |\n                //              |   ****   |\n                //              |  **  **  |\n                //              |  ** ***  |\n                //              |  *** **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |   ****   |\n\n  { 0x00,  0x18,  0x18,  0x38,  0x18,  0x18,  0x18,  0x7E },    // 49 : 1\n                //              |          |\n                //              |    **    |\n                //              |    **    |\n                //              |   ***    |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |  ******  |\n\n  { 0x00,  0x3C,  0x66,  0x06,  0x0C,  0x30,  0x60,  0x7E },    // 50 : 2\n                //              |          |\n                //              |   ****   |\n                //              |  **  **  |\n                //              |      **  |\n                //              |     **   |\n                //              |   **     |\n                //              |  **      |\n                //              |  ******  |\n\n  { 0x00,  0x3C,  0x66,  0x06,  0x1C,  0x06,  0x66,  0x3C },    // 51 : 3\n                //              |          |\n                //              |   ****   |\n                //              |  **  **  |\n                //              |      **  |\n                //              |    ***   |\n                //              |      **  |\n                //              |  **  **  |\n                //              |   ****   |\n\n  { 0x00,  0x0C,  0x1C,  0x2C,  0x4C,  0x7E,  0x0C,  0x0C },    // 52 : 4\n                //              |          |\n                //              |     **   |\n                //              |    ***   |\n                //              |   * **   |\n                //              |  *  **   |\n                //              |  ******  |\n                //              |     **   |\n                //              |     **   |\n\n  { 0x00,  0x7E,  0x60,  0x7C,  0x06,  0x06,  0x66,  0x3C },    // 53 : 5\n                //              |          |\n                //              |  ******  |\n                //              |  **      |\n                //              |  *****   |\n                //              |      **  |\n                //              |      **  |\n                //              |  **  **  |\n                //              |   ****   |\n\n  { 0x00,  0x3C,  0x66,  0x60,  0x7C,  0x66,  0x66,  0x3C },    // 54 : 6\n                //              |          |\n                //              |   ****   |\n                //              |  **  **  |\n                //              |  **      |\n                //              |  *****   |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |   ****   |\n\n  { 0x00,  0x7E,  0x66,  0x0C,  0x0C,  0x18,  0x18,  0x18 },    // 55 : 7\n                //              |          |\n                //              |  ******  |\n                //              |  **  **  |\n                //              |     **   |\n                //              |     **   |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n\n  { 0x00,  0x3C,  0x66,  0x66,  0x3C,  0x66,  0x66,  0x3C },    // 56 : 8\n                //              |          |\n                //              |   ****   |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |   ****   |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |   ****   |\n\n  { 0x00,  0x3C,  0x66,  0x66,  0x3E,  0x06,  0x66,  0x3C },    // 57 : 9\n                //              |          |\n                //              |   ****   |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |   *****  |\n                //              |      **  |\n                //              |  **  **  |\n                //              |   ****   |\n\n  { 0x00,  0x00,  0x18,  0x18,  0x00,  0x18,  0x18,  0x00 },    // 58 : :\n                //              |          |\n                //              |          |\n                //              |    **    |\n                //              |    **    |\n                //              |          |\n                //              |    **    |\n                //              |    **    |\n                //              |          |\n\n  { 0x00,  0x00,  0x18,  0x18,  0x00,  0x18,  0x18,  0x30 },    // 59 : ;\n                //              |          |\n                //              |          |\n                //              |    **    |\n                //              |    **    |\n                //              |          |\n                //              |    **    |\n                //              |    **    |\n                //              |   **     |\n\n  { 0x00,  0x06,  0x0C,  0x18,  0x30,  0x18,  0x0C,  0x06 },    // 60 : <\n                //              |          |\n                //              |      **  |\n                //              |     **   |\n                //              |    **    |\n                //              |   **     |\n                //              |    **    |\n                //              |     **   |\n                //              |      **  |\n\n  { 0x00,  0x00,  0x00,  0x3C,  0x00,  0x3C,  0x00,  0x00 },    // 61 : =\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |   ****   |\n                //              |          |\n                //              |   ****   |\n                //              |          |\n                //              |          |\n\n  { 0x00,  0x60,  0x30,  0x18,  0x0C,  0x18,  0x30,  0x60 },    // 62 : >\n                //              |          |\n                //              |  **      |\n                //              |   **     |\n                //              |    **    |\n                //              |     **   |\n                //              |    **    |\n                //              |   **     |\n                //              |  **      |\n\n  { 0x00,  0x3C,  0x66,  0x06,  0x1C,  0x18,  0x00,  0x18 },    // 63 : ?\n                //              |          |\n                //              |   ****   |\n                //              |  **  **  |\n                //              |      **  |\n                //              |    ***   |\n                //              |    **    |\n                //              |          |\n                //              |    **    |\n\n  { 0x00,  0x38,  0x44,  0x5C,  0x58,  0x42,  0x3C,  0x00 },    // 64 : @\n                //              |          |\n                //              |   ***    |\n                //              |  *   *   |\n                //              |  * ***   |\n                //              |  * **    |\n                //              |  *    *  |\n                //              |   ****   |\n                //              |          |\n\n  { 0x00,  0x3C,  0x66,  0x66,  0x7E,  0x66,  0x66,  0x66 },    // 65 : A\n                //              |          |\n                //              |   ****   |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  ******  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n\n  { 0x00,  0x7C,  0x66,  0x66,  0x7C,  0x66,  0x66,  0x7C },    // 66 : B\n                //              |          |\n                //              |  *****   |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  *****   |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  *****   |\n\n  { 0x00,  0x3C,  0x66,  0x60,  0x60,  0x60,  0x66,  0x3C },    // 67 : C\n                //              |          |\n                //              |   ****   |\n                //              |  **  **  |\n                //              |  **      |\n                //              |  **      |\n                //              |  **      |\n                //              |  **  **  |\n                //              |   ****   |\n\n  { 0x00,  0x7C,  0x66,  0x66,  0x66,  0x66,  0x66,  0x7C },    // 68 : D\n                //              |          |\n                //              |  *****   |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  *****   |\n\n  { 0x00,  0x7E,  0x60,  0x60,  0x7C,  0x60,  0x60,  0x7E },    // 69 : E\n                //              |          |\n                //              |  ******  |\n                //              |  **      |\n                //              |  **      |\n                //              |  *****   |\n                //              |  **      |\n                //              |  **      |\n                //              |  ******  |\n\n  { 0x00,  0x7E,  0x60,  0x60,  0x7C,  0x60,  0x60,  0x60 },    // 70 : F\n                //              |          |\n                //              |  ******  |\n                //              |  **      |\n                //              |  **      |\n                //              |  *****   |\n                //              |  **      |\n                //              |  **      |\n                //              |  **      |\n\n  { 0x00,  0x3C,  0x66,  0x60,  0x60,  0x6E,  0x66,  0x3C },    // 71 : G\n                //              |          |\n                //              |   ****   |\n                //              |  **  **  |\n                //              |  **      |\n                //              |  **      |\n                //              |  ** ***  |\n                //              |  **  **  |\n                //              |   ****   |\n\n  { 0x00,  0x66,  0x66,  0x66,  0x7E,  0x66,  0x66,  0x66 },    // 72 : H\n                //              |          |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  ******  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n\n  { 0x00,  0x3C,  0x18,  0x18,  0x18,  0x18,  0x18,  0x3C },    // 73 : I\n                //              |          |\n                //              |   ****   |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |   ****   |\n\n  { 0x00,  0x1E,  0x0C,  0x0C,  0x0C,  0x6C,  0x6C,  0x38 },    // 74 : J\n                //              |          |\n                //              |    ****  |\n                //              |     **   |\n                //              |     **   |\n                //              |     **   |\n                //              |  ** **   |\n                //              |  ** **   |\n                //              |   ***    |\n\n  { 0x00,  0x66,  0x6C,  0x78,  0x70,  0x78,  0x6C,  0x66 },    // 75 : K\n                //              |          |\n                //              |  **  **  |\n                //              |  ** **   |\n                //              |  ****    |\n                //              |  ***     |\n                //              |  ****    |\n                //              |  ** **   |\n                //              |  **  **  |\n\n  { 0x00,  0x60,  0x60,  0x60,  0x60,  0x60,  0x60,  0x7E },    // 76 : L\n                //              |          |\n                //              |  **      |\n                //              |  **      |\n                //              |  **      |\n                //              |  **      |\n                //              |  **      |\n                //              |  **      |\n                //              |  ******  |\n\n  { 0x00,  0x63,  0x77,  0x7F,  0x6B,  0x63,  0x63,  0x63 },    // 77 : M\n                //              |          |\n                //              |  **   ** |\n                //              |  *** *** |\n                //              |  ******* |\n                //              |  ** * ** |\n                //              |  **   ** |\n                //              |  **   ** |\n                //              |  **   ** |\n\n  { 0x00,  0x63,  0x73,  0x7B,  0x6F,  0x67,  0x63,  0x63 },    // 78 : N\n                //              |          |\n                //              |  **   ** |\n                //              |  ***  ** |\n                //              |  **** ** |\n                //              |  ** **** |\n                //              |  **  *** |\n                //              |  **   ** |\n                //              |  **   ** |\n\n  { 0x00,  0x3C,  0x66,  0x66,  0x66,  0x66,  0x66,  0x3C },    // 79 : O\n                //              |          |\n                //              |   ****   |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |   ****   |\n\n  { 0x00,  0x7C,  0x66,  0x66,  0x66,  0x7C,  0x60,  0x60 },    // 80 : P\n                //              |          |\n                //              |  *****   |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  *****   |\n                //              |  **      |\n                //              |  **      |\n\n  { 0x00,  0x3C,  0x66,  0x66,  0x66,  0x6E,  0x3C,  0x06 },    // 81 : Q\n                //              |          |\n                //              |   ****   |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  ** ***  |\n                //              |   ****   |\n                //              |      **  |\n\n  { 0x00,  0x7C,  0x66,  0x66,  0x7C,  0x78,  0x6C,  0x66 },    // 82 : R\n                //              |          |\n                //              |  *****   |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  *****   |\n                //              |  ****    |\n                //              |  ** **   |\n                //              |  **  **  |\n\n  { 0x00,  0x3C,  0x66,  0x60,  0x3C,  0x06,  0x66,  0x3C },    // 83 : S\n                //              |          |\n                //              |   ****   |\n                //              |  **  **  |\n                //              |  **      |\n                //              |   ****   |\n                //              |      **  |\n                //              |  **  **  |\n                //              |   ****   |\n\n  { 0x00,  0x7E,  0x5A,  0x18,  0x18,  0x18,  0x18,  0x18 },    // 84 : T\n                //              |          |\n                //              |  ******  |\n                //              |  * ** *  |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n\n  { 0x00,  0x66,  0x66,  0x66,  0x66,  0x66,  0x66,  0x3E },    // 85 : U\n                //              |          |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |   *****  |\n\n  { 0x00,  0x66,  0x66,  0x66,  0x66,  0x66,  0x3C,  0x18 },    // 86 : V\n                //              |          |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |   ****   |\n                //              |    **    |\n\n  { 0x00,  0x63,  0x63,  0x63,  0x6B,  0x7F,  0x77,  0x63 },    // 87 : W\n                //              |          |\n                //              |  **   ** |\n                //              |  **   ** |\n                //              |  **   ** |\n                //              |  ** * ** |\n                //              |  ******* |\n                //              |  *** *** |\n                //              |  **   ** |\n\n  { 0x00,  0x63,  0x63,  0x36,  0x1C,  0x36,  0x63,  0x63 },    // 88 : X\n                //              |          |\n                //              |  **   ** |\n                //              |  **   ** |\n                //              |   ** **  |\n                //              |    ***   |\n                //              |   ** **  |\n                //              |  **   ** |\n                //              |  **   ** |\n\n  { 0x00,  0x66,  0x66,  0x66,  0x3C,  0x18,  0x18,  0x18 },    // 89 : Y\n                //              |          |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |   ****   |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n\n  { 0x00,  0x7E,  0x06,  0x0C,  0x18,  0x30,  0x60,  0x7E },    // 90 : Z\n                //              |          |\n                //              |  ******  |\n                //              |      **  |\n                //              |     **   |\n                //              |    **    |\n                //              |   **     |\n                //              |  **      |\n                //              |  ******  |\n\n  { 0x00,  0x1E,  0x18,  0x18,  0x18,  0x18,  0x18,  0x1E },    // 91 : [\n                //              |          |\n                //              |    ****  |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |    ****  |\n\n  { 0x00,  0x00,  0x60,  0x30,  0x18,  0x0C,  0x06,  0x00 },    // 92 : \\\n                //              |          |\n                //              |          |\n                //              |  **      |\n                //              |   **     |\n                //              |    **    |\n                //              |     **   |\n                //              |      **  |\n                //              |          |\n\n  { 0x00,  0x78,  0x18,  0x18,  0x18,  0x18,  0x18,  0x78 },    // 93 : ]\n                //              |          |\n                //              |  ****    |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |  ****    |\n\n  { 0x00,  0x08,  0x14,  0x22,  0x41,  0x00,  0x00,  0x00 },    // 94 : ^\n                //              |          |\n                //              |     *    |\n                //              |    * *   |\n                //              |   *   *  |\n                //              |  *     * |\n                //              |          |\n                //              |          |\n                //              |          |\n\n  { 0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x7F },    // 95 : _\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |  ******* |\n\n  { 0x00,  0x0C,  0x0C,  0x06,  0x00,  0x00,  0x00,  0x00 },    // 96 : `\n                //              |          |\n                //              |     **   |\n                //              |     **   |\n                //              |      **  |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n\n  { 0x00,  0x00,  0x00,  0x3C,  0x06,  0x3E,  0x66,  0x3E },    // 97 : a\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |   ****   |\n                //              |      **  |\n                //              |   *****  |\n                //              |  **  **  |\n                //              |   *****  |\n\n  { 0x00,  0x60,  0x60,  0x60,  0x7C,  0x66,  0x66,  0x7C },    // 98 : b\n                //              |          |\n                //              |  **      |\n                //              |  **      |\n                //              |  **      |\n                //              |  *****   |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  *****   |\n\n  { 0x00,  0x00,  0x00,  0x3C,  0x66,  0x60,  0x66,  0x3C },    // 99 : c\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |   ****   |\n                //              |  **  **  |\n                //              |  **      |\n                //              |  **  **  |\n                //              |   ****   |\n\n  { 0x00,  0x06,  0x06,  0x06,  0x3E,  0x66,  0x66,  0x3E },    // 100 : d\n                //              |          |\n                //              |      **  |\n                //              |      **  |\n                //              |      **  |\n                //              |   *****  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |   *****  |\n\n  { 0x00,  0x00,  0x00,  0x3C,  0x66,  0x7E,  0x60,  0x3C },    // 101 : e\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |   ****   |\n                //              |  **  **  |\n                //              |  ******  |\n                //              |  **      |\n                //              |   ****   |\n\n  { 0x00,  0x1C,  0x36,  0x30,  0x30,  0x7C,  0x30,  0x30 },    // 102 : f\n                //              |          |\n                //              |    ***   |\n                //              |   ** **  |\n                //              |   **     |\n                //              |   **     |\n                //              |  *****   |\n                //              |   **     |\n                //              |   **     |\n\n  { 0x00,  0x00,  0x3E,  0x66,  0x66,  0x3E,  0x06,  0x3C },    // 103 : g\n                //              |          |\n                //              |          |\n                //              |   *****  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |   *****  |\n                //              |      **  |\n                //              |   ****   |\n\n  { 0x00,  0x60,  0x60,  0x60,  0x7C,  0x66,  0x66,  0x66 },    // 104 : h\n                //              |          |\n                //              |  **      |\n                //              |  **      |\n                //              |  **      |\n                //              |  *****   |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n\n  { 0x00,  0x00,  0x18,  0x00,  0x18,  0x18,  0x18,  0x3C },    // 105 : i\n                //              |          |\n                //              |          |\n                //              |    **    |\n                //              |          |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |   ****   |\n\n  { 0x00,  0x0C,  0x00,  0x0C,  0x0C,  0x6C,  0x6C,  0x38 },    // 106 : j\n                //              |          |\n                //              |     **   |\n                //              |          |\n                //              |     **   |\n                //              |     **   |\n                //              |  ** **   |\n                //              |  ** **   |\n                //              |   ***    |\n\n  { 0x00,  0x60,  0x60,  0x66,  0x6C,  0x78,  0x6C,  0x66 },    // 107 : k\n                //              |          |\n                //              |  **      |\n                //              |  **      |\n                //              |  **  **  |\n                //              |  ** **   |\n                //              |  ****    |\n                //              |  ** **   |\n                //              |  **  **  |\n\n  { 0x00,  0x18,  0x18,  0x18,  0x18,  0x18,  0x18,  0x18 },    // 108 : l\n                //              |          |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n\n  { 0x00,  0x00,  0x00,  0x63,  0x77,  0x7F,  0x6B,  0x6B },    // 109 : m\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |  **   ** |\n                //              |  *** *** |\n                //              |  ******* |\n                //              |  ** * ** |\n                //              |  ** * ** |\n\n  { 0x00,  0x00,  0x00,  0x7C,  0x7E,  0x66,  0x66,  0x66 },    // 110 : n\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |  *****   |\n                //              |  ******  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n\n  { 0x00,  0x00,  0x00,  0x3C,  0x66,  0x66,  0x66,  0x3C },    // 111 : o\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |   ****   |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |   ****   |\n\n  { 0x00,  0x00,  0x7C,  0x66,  0x66,  0x7C,  0x60,  0x60 },    // 112 : p\n                //              |          |\n                //              |          |\n                //              |  *****   |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  *****   |\n                //              |  **      |\n                //              |  **      |\n\n  { 0x00,  0x00,  0x3C,  0x6C,  0x6C,  0x3C,  0x0D,  0x0F },    // 113 : q\n                //              |          |\n                //              |          |\n                //              |   ****   |\n                //              |  ** **   |\n                //              |  ** **   |\n                //              |   ****   |\n                //              |     ** * |\n                //              |     **** |\n\n  { 0x00,  0x00,  0x00,  0x7C,  0x66,  0x66,  0x60,  0x60 },    // 114 : r\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |  *****   |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **      |\n                //              |  **      |\n\n  { 0x00,  0x00,  0x00,  0x3E,  0x40,  0x3C,  0x02,  0x7C },    // 115 : s\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |   *****  |\n                //              |  *       |\n                //              |   ****   |\n                //              |       *  |\n                //              |  *****   |\n\n  { 0x00,  0x00,  0x18,  0x18,  0x7E,  0x18,  0x18,  0x18 },    // 116 : t\n                //              |          |\n                //              |          |\n                //              |    **    |\n                //              |    **    |\n                //              |  ******  |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n\n  { 0x00,  0x00,  0x00,  0x66,  0x66,  0x66,  0x66,  0x3E },    // 117 : u\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |   *****  |\n\n  { 0x00,  0x00,  0x00,  0x00,  0x66,  0x66,  0x3C,  0x18 },    // 118 : v\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |   ****   |\n                //              |    **    |\n\n  { 0x00,  0x00,  0x00,  0x63,  0x6B,  0x6B,  0x6B,  0x3E },    // 119 : w\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |  **   ** |\n                //              |  ** * ** |\n                //              |  ** * ** |\n                //              |  ** * ** |\n                //              |   *****  |\n\n  { 0x00,  0x00,  0x00,  0x66,  0x3C,  0x18,  0x3C,  0x66 },    // 120 : x\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |  **  **  |\n                //              |   ****   |\n                //              |    **    |\n                //              |   ****   |\n                //              |  **  **  |\n\n  { 0x00,  0x00,  0x00,  0x66,  0x66,  0x3E,  0x06,  0x3C },    // 121 : y\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |  **  **  |\n                //              |  **  **  |\n                //              |   *****  |\n                //              |      **  |\n                //              |   ****   |\n\n  { 0x00,  0x00,  0x00,  0x3C,  0x0C,  0x18,  0x30,  0x3C },    // 122 : z\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |   ****   |\n                //              |     **   |\n                //              |    **    |\n                //              |   **     |\n                //              |   ****   |\n\n  { 0x00,  0x0E,  0x18,  0x18,  0x30,  0x18,  0x18,  0x0E },    // 123 : {\n                //              |          |\n                //              |     ***  |\n                //              |    **    |\n                //              |    **    |\n                //              |   **     |\n                //              |    **    |\n                //              |    **    |\n                //              |     ***  |\n\n  { 0x00,  0x18,  0x18,  0x18,  0x00,  0x18,  0x18,  0x18 },    // 124 : |\n                //              |          |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n                //              |          |\n                //              |    **    |\n                //              |    **    |\n                //              |    **    |\n\n  { 0x00,  0x70,  0x18,  0x18,  0x0C,  0x18,  0x18,  0x70 },    // 125 : }\n                //              |          |\n                //              |  ***     |\n                //              |    **    |\n                //              |    **    |\n                //              |     **   |\n                //              |    **    |\n                //              |    **    |\n                //              |  ***     |\n\n  { 0x00,  0x00,  0x00,  0x3A,  0x6C,  0x00,  0x00,  0x00 },    // 126 : ~\n                //              |          |\n                //              |          |\n                //              |          |\n                //              |   *** *  |\n                //              |  ** **   |\n                //              |          |\n                //              |          |\n                //              |          |\n\n  { 0x00,  0x08,  0x1C,  0x36,  0x63,  0x41,  0x41,  0x7F }    // 127 : \n                //              |          |\n                //              |     *    |\n                //              |    ***   |\n                //              |   ** **  |\n                //              |  **   ** |\n                //              |  *     * |\n                //              |  *     * |\n                //              |  ******* |\n\n\n};\n\nvoid effect_text(char *string, int delayt)\n{\n    int ltr, dist, rw;\n\n    fill(0x00);\n    for (ltr=0; string[ltr]; ltr++) {       // For each letter in string array\n        for (dist = 0; dist < 8; dist++) {  // bring letter forward\n            int rev = 0;\n\n            fill(0x00);                     // blank cube\n            for (rw = 7; rw >= 0; rw--) {   // copy rows\n#if 0\n                // put this in for normal cube\n                cube[rev][dist] = bitswap(font_data[string[ltr]][rw]);\n#else\n                cube[rev][dist] = font_data[string[ltr]][rw];\n                // use above line for backward ass cubes\n#endif\n                rev++;\n            }\n            delay_ms(delayt);\n        }\n    }\n}\n\nvoid effect_text_up(char *string, int delayt)\n{\n    int ltr, dist, rw;\n\n    fill(0x00);\n    for (ltr=0; string[ltr]; ltr++) {       // For each letter in string array\n        for (dist = 0; dist < 8; dist++) {  // bring letter forward\n            int rev = 0;\n\n            fill(0x00);                     // blank cube\n            for (rw = 7; rw >= 0; rw--) {   // copy rows\n#if 0\n                // put this in for miswired backwards cube\n                cube[rev][dist] = bitswap(font_data[string[ltr]][rw]);\n#else\n                cube[dist][rev] = font_data[string[ltr]][rw];\n                // use above line for proper cubes\n#endif\n                rev++;\n            }\n            delay_ms(delayt);\n        }\n    }\n}\n\nvoid int_ripples(int iterations, int delay)\n{\n\t// 16 values for square root of a^2+b^2.  index a*4+b = 10*sqrt\n\t// This gives the distance to 3.5,3.5 from the point\n\tunsigned char sqrt_LUT[]={\n            49, 43, 38, 35, 43, 35, 29, 26, 38, 29, 21, 16, 35, 25, 16, 7\n        };\n\tunsigned char x, y, height, distance;\n\tint i;\n\n\tfor (i=0;i<iterations*4;i+=4)\n\t{\n\t\tfill(0x00);\n\t\tfor (x=0;x<4;x++)\n\t\t\tfor (y=0;y<4;y++)\n\t\t\t{\n\t\t\t\t// x+y*4 gives no. from 0-15 for sqrt_LUT\n\t\t\t\tdistance=sqrt_LUT[x+y*4];// distance is 0-50 roughly\n\t\t\t\t// height is sin of distance + iteration*4\n\t\t\t\t//height = 4 + totty_sin(distance+i) / 52;\n\t\t\t\theight = (196 + totty_sin(distance+i)) / 49;\n\t\t\t\t// Use 4-way mirroring to save on calculations\n\t\t\t\tsetvoxel(x,   y,   height);\n\t\t\t\tsetvoxel(7-x, y,   height);\n\t\t\t\tsetvoxel(x,   7-y, height);\n\t\t\t\tsetvoxel(7-x, 7-y, height);\n\t\t\t}\n\t\tdelay_ms(delay);\n\t}\n}\n\nvoid side_ripples(int iterations, int delay)\n{\n\t// 16 values for square root of a^2+b^2.  index a*4+b = 10*sqrt\n\t// This gives the distance to 3.5,3.5 from the point\n\tunsigned char sqrt_LUT[]={\n            49, 43, 38, 35, 43, 35, 29, 26, 38, 29, 21, 16, 35, 25, 16, 7\n        };\n\tunsigned char x, y, height, distance;\n\tint i;\n\n\tfor (i=0;i<iterations*4;i+=4)\n\t{\n\t\tfill(0x00);\n\t\tfor (x=0;x<4;x++)\n\t\t\tfor (y=0;y<4;y++)\n\t\t\t{\n\t\t\t\t// x+y*4 gives no. from 0-15 for sqrt_LUT\n\t\t\t\tdistance=sqrt_LUT[x+y*4];// distance is 0-50 roughly\n\t\t\t\t// height is sin of distance + iteration*4\n\t\t\t\t//height = 4 + totty_sin(distance+i) / 52;\n\t\t\t\theight = (196 + totty_sin(distance+i)) / 49;\n\t\t\t\t// Use 4-way mirroring to save on calculations\n\t\t\t\tsetvoxel(x,   height,   y);\n\t\t\t\tsetvoxel(7-x, height,   y);\n\t\t\t\tsetvoxel(x,   height,   7-y);\n\t\t\t\tsetvoxel(7-x, height,   7-y);\n\t\t\t\tsetvoxel(x,   7-height, y);\n\t\t\t\tsetvoxel(7-x, 7-height, y);\n\t\t\t\tsetvoxel(x,   7-height, 7-y);\n\t\t\t\tsetvoxel(7-x, 7-height, 7-y);\n\t\t\t}\n\t\tdelay_ms(delay);\n\t}\n}\n\nvoid mirror_ripples(int iterations, int delay)\n{\n\t// 16 values for square root of a^2+b^2.  index a*4+b = 10*sqrt\n\t// This gives the distance to 3.5,3.5 from the point\n\tunsigned char sqrt_LUT[]={\n            49, 43, 38, 35, 43, 35, 29, 26, 38, 29, 21, 16, 35, 25, 16, 7\n        };\n\tunsigned char x, y, height, distance;\n\tint i;\n\n\tfor (i=0;i<iterations*4;i+=4)\n\t{\n\t\tfill(0x00);\n\t\tfor (x=0;x<4;x++)\n\t\t\tfor (y=0;y<4;y++)\n\t\t\t{\n\t\t\t\t// x+y*4 gives no. from 0-15 for sqrt_LUT\n\t\t\t\tdistance=sqrt_LUT[x+y*4];// distance is 0-50 roughly\n\t\t\t\t// height is sin of distance + iteration*4\n\t\t\t\t//height = 4 + totty_sin(distance+i) / 52;\n\t\t\t\theight = (196 + totty_sin(distance+i)) / 49;\n\t\t\t\t// Use 4-way mirroring to save on calculations\n\t\t\t\tsetvoxel(x,   y,   height);\n\t\t\t\tsetvoxel(7-x, y,   height);\n\t\t\t\tsetvoxel(x,   7-y, height);\n\t\t\t\tsetvoxel(7-x, 7-y, height);\n\t\t\t\tsetvoxel(x,   y,   7-height);\n\t\t\t\tsetvoxel(7-x, y,   7-height);\n\t\t\t\tsetvoxel(x,   7-y, 7-height);\n\t\t\t\tsetvoxel(7-x, 7-y, 7-height);\n\t\t\t}\n\t\tdelay_ms(delay);\n\t}\n}\n\nvoid zoom_pyramid_clear()\n{\n  //1\n\n  box_walls(0, 0, 0, 7, 0, 7);\n  delay_ms(250);\n\n  //2\n\n  //Pyramid\n    box_wireframe(0, 0, 0, 7, 0, 1);\n\n   clrplane_y(0);\n  delay_ms(250);\n\n  //3\n\n  //Pyramid\n     clrplane_y(1);\n  box_walls(0, 2, 0, 7, 2, 7);\n  delay_ms(250);\n\n  //4\n\n  //Pyramid\n     clrplane_y(2);\n  box_walls(0, 3, 0, 7, 3, 7);\n  delay_ms(250);\n\n  //5\n\n  //Pyramid\n     clrplane_y(3);\n  box_walls(0, 4, 0, 7, 4, 7);\n  delay_ms(250);\n\n  //5\n\n  //Pyramid\n\n     clrplane_y(4);\n  box_walls(0, 5, 0, 7, 5, 7);\n  delay_ms(250);\n  //6\n\n\n  //Pyramid\n\n     clrplane_y(5);\n      box_walls(0, 6, 0, 7, 6, 7);\n  delay_ms(250);\n  //7\n\n  //Pyramid\n\n  clrplane_y(6);\n  box_walls(0, 7, 0, 7, 7, 7);\n  delay_ms(250);\n\n  clrplane_y(7);\n  delay_ms(5000);\n}\n\nvoid zoom_pyramid()\n{\n    int i, j, k, time;\n\n  //1\n  fill(0x00);\n\n  box_walls(0, 0, 0, 7, 0, 7);\n  delay_ms(250);\n\n  //2\n  fill(0x00);\n  //Pyramid\n    box_wireframe(0, 0, 0, 7, 0, 1);\n\n   box_walls(0, 1, 0, 7, 1, 7);\n  delay_ms(250);\n\n  //3\n  fill(0x00);\n  //Pyramid\n    box_wireframe(0, 0, 0, 7, 1, 1);\n    box_wireframe(1, 1, 2, 6, 1, 3);\n\n  box_walls(0, 2, 0, 7, 2, 7);\n  delay_ms(250);\n\n  //4\n  fill(0x00);\n  //Pyramid\n    box_wireframe(0, 0, 0, 7, 2, 1);\n    box_wireframe(1, 1, 2, 6, 2, 3);\n    box_wireframe(2, 2, 4, 5, 2, 5);\n\n  box_walls(0, 3, 0, 7, 3, 7);\n  delay_ms(250);\n\n  //5\n  fill(0x00);\n  //Pyramid\n    box_wireframe(0, 0, 0, 7, 3, 1);\n    box_wireframe(1, 1, 2, 6, 3, 3);\n    box_wireframe(2, 2, 4, 5, 3, 5);\n    box_wireframe(3, 3, 6, 4, 3, 7);\n\n  box_walls(0, 4, 0, 7, 4, 7);\n  delay_ms(250);\n\n  //5\n  fill(0x00);\n  //Pyramid\n    box_wireframe(0, 0, 0, 7, 4, 1);\n    box_wireframe(1, 1, 2, 6, 4, 3);\n    box_wireframe(2, 2, 4, 5, 4, 5);\n    box_wireframe(3, 3, 6, 4, 4, 7);\n\n  box_walls(0, 5, 0, 7, 5, 7);\n  delay_ms(250);\n  //6\n\n  fill(0x00);\n  //Pyramid\n    box_wireframe(0, 0, 0, 7, 5, 1);\n    box_wireframe(1, 1, 2, 6, 5, 3);\n    box_wireframe(2, 2, 4, 5, 5, 5);\n    box_wireframe(3, 3, 6, 4, 4, 7);\n\n      box_walls(0, 6, 0, 7, 6, 7);\n  delay_ms(250);\n  //7\n  fill(0x00);\n  //Pyramid\n    box_wireframe(0, 0, 0, 7, 6, 1);\n    box_wireframe(1, 1, 2, 6, 6, 3);\n    box_wireframe(2, 2, 4, 5, 5, 5);\n    box_wireframe(3, 3, 6, 4, 4, 7);\n\n  box_walls(0, 7, 0, 7, 7, 7);\n  delay_ms(250);\n\n  fill(0x00);\n  box_wireframe(0, 0, 0, 7, 7, 1);\n  box_wireframe(1, 1, 2, 6, 6, 3);\n  box_wireframe(2, 2, 4, 5, 5, 5);\n  box_wireframe(3, 3, 6, 4, 4, 7);\n\n  delay_ms(5000);\n}\n\nvoid effect_intro()\n{\n    int cnt, cnt_2, time;\n\n    // Bottom To Top\n\n    for (cnt=0; cnt<=7; cnt++) {\n        box_wireframe(0, 0, 0, 7, 7, cnt);\n        delay_ms(300);\n    }\n    for (cnt=0; cnt<7; cnt++) {\n        clrplane_z(cnt);\n        delay_ms(300);\n    }\n\n    // Shift Things Right\n    // 1\n    shift(AXIS_Y, -1);\n    for (cnt=0; cnt<=7; cnt++) {\n        setvoxel(cnt, 0, 6);\n    }\n    delay_ms(300);\n    // 2\n    shift(AXIS_Y, -1);\n    for (cnt=0; cnt<=7; cnt++) {\n        setvoxel(cnt, 0, 5);\n    }\n    setvoxel(0, 0, 6);\n    setvoxel(7, 0, 6);\n    delay_ms(300);\n    // 3\n    shift(AXIS_Y, -1);\n    for (cnt=0; cnt<=7; cnt++) {\n        setvoxel(cnt, 0, 4);\n    }\n    setvoxel(0, 0, 5);\n    setvoxel(7, 0, 5);\n    setvoxel(0, 0, 6);\n    setvoxel(7, 0, 6);\n    delay_ms(300);\n\n    // 4\n    shift(AXIS_Y, -1);\n    for (cnt=0; cnt<=7; cnt++) {\n        setvoxel(cnt, 0, 3);\n    }\n    setvoxel(0, 0 ,4);\n    setvoxel(7, 0, 4);\n    setvoxel(0, 0, 5);\n    setvoxel(7, 0, 5);\n    setvoxel(0, 0, 6);\n    setvoxel(7, 0, 6);\n    delay_ms(300);\n\n    // 5\n    shift(AXIS_Y, -1);\n    for(cnt=0; cnt<=7; cnt++) {\n        setvoxel(cnt, 0, 2);\n    }\n    setvoxel(0, 0, 3);\n    setvoxel(7, 0, 3);\n    setvoxel(0, 0, 4);\n    setvoxel(7, 0, 4);\n    setvoxel(0, 0, 5);\n    setvoxel(7, 0, 5);\n    setvoxel(0, 0, 6);\n    setvoxel(7, 0, 6);\n    delay_ms(300);\n\n    // 6\n    shift(AXIS_Y, -1);\n    for(cnt=0; cnt<=7; cnt++) {\n        setvoxel(cnt, 0, 1);\n    }\n    setvoxel(0, 0, 2);\n    setvoxel(7, 0, 2);\n    setvoxel(0, 0, 3);\n    setvoxel(7, 0, 3);\n    setvoxel(0, 0, 4);\n    setvoxel(7, 0, 4);\n    setvoxel(0, 0, 5);\n    setvoxel(7, 0, 5);\n    delay_ms(300);\n\n    // 7\n    shift(AXIS_Y, -1);\n    for(cnt=0;cnt<=7;cnt++){\n        setvoxel(cnt, 0, 0);\n    }\n    setvoxel(0, 0, 1);\n    setvoxel(7, 0, 1);\n    setvoxel(0, 0, 2);\n    setvoxel(7, 0, 2);\n    setvoxel(0, 0, 3);\n    setvoxel(7, 0, 3);\n    setvoxel(0, 0, 4);\n    setvoxel(7, 0, 4);\n    setvoxel(0, 0, 5);\n    setvoxel(7, 0, 5);\n    delay_ms(300);\n\n    // Right To Left\n    for (cnt=0; cnt<=7; cnt++) {\n        box_wireframe(0, 0, 0, 7, cnt, 7);\n        delay_ms(300);\n    }\n    for (cnt=0; cnt<7; cnt++) {\n        clrplane_y(cnt);\n        delay_ms(300);\n    }\n\n    // Shift to the bottom\n    for (cnt_2=6; cnt_2>=0; cnt_2--) {\n        shift(AXIS_Z, -1);\n        for (cnt=0; cnt<=7; cnt++) {\n            setvoxel(cnt, cnt_2, 0);\n        }\n        for (cnt=6; cnt>cnt_2; cnt--) {\n            setvoxel(0, cnt, 0);\n            setvoxel(7, cnt, 0);\n        }\n        delay_ms(300);\n    }\n\n    // Make All Wall Box\n\n    for (cnt=0; cnt<=6; cnt++) {\n        fill(0x00);\n        box_walls(0, 0, 0, 7, 7, cnt);\n        delay_ms(300);\n    }\n\n    time = 500;\n    for (cnt_2=0; cnt_2<5; cnt_2++) {\n        time -= 75;\n        // Make Box Smaller\n        for (cnt=0; cnt<=3; cnt++) {\n            fill(0x00);\n            box_walls(cnt, cnt, cnt, 7-cnt, 7-cnt, 7-cnt);\n            delay_ms(time);\n        }\n\n        // Make Box Bigger\n        for (cnt=0; cnt<=3; cnt++) {\n            fill(0x00);\n            box_walls(3-cnt, 3-cnt, 3-cnt, 4+cnt, 4+cnt, 4+cnt);\n            delay_ms(time);\n        }\n    }\n    for (cnt_2=0; cnt_2<5; cnt_2++) {\n        time += 75;\n        // Make Box Smaller\n        for (cnt=0; cnt<=3; cnt++) {\n            fill(0x00);\n            box_walls(cnt, cnt, cnt, 7-cnt, 7-cnt, 7-cnt);\n            delay_ms(time);\n        }\n\n        // Make Box Bigger\n        for (cnt=0; cnt<=3; cnt++) {\n            fill(0x00);\n            box_walls(3-cnt, 3-cnt, 3-cnt, 4+cnt, 4+cnt, 4+cnt);\n            delay_ms(time);\n        }\n    }\n    delay_ms(500);\n}\n\n// ******************************************\n// 3D addins ********************************\n// ******************************************\n#if 0\nvoid linespin(int iterations, int delay)\n{\n\tfloat top_x, top_y, top_z, bot_x, bot_y, bot_z, sin_base;\n\tfloat center_x, center_y;\n\n\tcenter_x = 4;\n\tcenter_y = 4;\n\n\tint i, z;\n\tfor (i=0;i<iterations;i++)\n\t{\n\n\t\t//printf(\"Sin base %f \\n\", sin_base);\n\n\t\tfor (z = 0; z < 8; z++)\n\t\t{\n\n\t\tsin_base = (float)i/50 + (float)z/(10 + (7*sin((float)i / 200)));\n\n\t\ttop_x = center_x + sin(sin_base) * 5;\n\t\ttop_y = center_x + cos(sin_base) * 5;\n\t\t//top_z = center_x + cos(sin_base/100) * 2.5;\n\n\t\tbot_x = center_x + sin(sin_base+3.14) * 10;\n\t\tbot_y = center_x + cos(sin_base+3.14) * 10;\n\t\t//bot_z = 7-top_z;\n\n\t\tbot_z = z;\n\t\ttop_z = z;\n\n\t\t// setvoxel((int) top_x, (int) top_y, 7);\n\t\t// setvoxel((int) bot_x, (int) bot_y, 0);\n\n\t\t//printf(\"P1: %i %i %i P2: %i %i %i \\n\", (int) top_x, (int) top_y, 7, (int) bot_x, (int) bot_y, 0);\n\n\t\t//line_3d((int) top_x, (int) top_y, (int) top_z, (int) bot_x, (int) bot_y, (int) bot_z);\n\t\tline_3d((int) top_z, (int) top_x, (int) top_y, (int) bot_z, (int) bot_x, (int) bot_y);\n\t\t}\n\n\t\t// delay_ms(delay);\n\t\tfill(0x00);\n\t}\n\n}\n#endif\n\n// circle, len 16, offset 28\nconst unsigned char paths[44] = {\n    0x07,0x06,0x05,0x04,0x03,0x02,0x01,0x00,\n    0x10,0x20,0x30,0x40,0x50,0x60,0x70,0x71,\n    0x72,0x73,0x74,0x75,0x76,0x77,0x67,0x57,\n    0x47,0x37,0x27,0x17,0x04,0x03,0x12,0x21,\n    0x30,0x40,0x51,0x62,0x73,0x74,0x65,0x56,\n    0x47,0x37,0x26,0x15\n};\n\nvoid font_getpath(unsigned char path, unsigned char *destination, int length)\n{\n\tint i;\n\tint offset = 0;\n\n\tif (path == 1)\n\t\toffset = 28;\n\n\tfor (i = 0; i < length; i++)\n\t\tdestination[i] = paths[i+offset];\n}\n\n// ************************************************************\n\nvoid effect_pathmove(unsigned char *path, int length)\n{\n\tint i, z;\n\tunsigned char state;\n\n\tfor (i=(length-1);i>=1;i--)\n\t{\n\t\tfor (z=0;z<8;z++)\n\t\t{\n\n\t\t\tstate = getvoxel(((path[(i-1)]>>4) & 0x0f), (path[(i-1)] & 0x0f), z);\n\t\t\taltervoxel(((path[i]>>4) & 0x0f), (path[i] & 0x0f), z, state);\n\t\t}\n\t}\n\tfor (i=0;i<8;i++)\n\t\tclrvoxel(((path[0]>>4) & 0x0f), (path[0] & 0x0f), i);\n}\n\nvoid effect_rand_patharound(int iterations, int delay)\n{\n\tint z, dz, i;\n\tz = 4;\n\tunsigned char path[28];\n\n\tfont_getpath(0, path, 28);\n\n\tfor (i = 0; i < iterations; i++)\n\t{\n\t\tdz = ((rand()%3)-1);\n\t\tz += dz;\n\n\t\tif (z>7)\n\t\t\tz = 7;\n\n\t\tif (z<0)\n\t\t\tz = 0;\n\n\t\teffect_pathmove(path, 28);\n\t\tsetvoxel(0, 7, z);\n\t\tdelay_ms(delay);\n\t}\n}\n\nvoid main()\n{\n    int i, x, y, z, m, n;\n\n    gpio_init();\n    gpio_ext(1);\n\n    for (y=0; y<8; y++) {\n        for (x=0; x<8; x++) {\n            for (z=0; z<8; z++) {\n                setvoxel(x, y, z);\n            }\n\n            delay_ms(20);\n\n            for (z=0; z<8; z++) {\n                clrvoxel(x, y, z);\n            }\n        }\n    }\n    for (z=0; z<8; z++) {\n        for (y=0; y<8; y++) {\n            for (x=0; x<8; x++) {\n                setvoxel(x, y, z);\n                delay_ms(5);\n            }\n        }\n    }\n    fill(0);\n\n    for (;;) {\n        printf(\"intro\\n\");\n        effect_intro();\n\n        printf(\"wormsqueeze\\n\");\n        effect_wormsqueeze(2, AXIS_Z, -1, 100, 500);\n\n        printf(\"pyramid\\n\");\n        zoom_pyramid();\n        zoom_pyramid_clear();\n\n        printf(\"text\\n\");\n        effect_text(\"MIPS RETROBSD\", 600);\n        //sinelines(4000, 10);\n        //linespin(1500, 10);\n\n        printf(\"planboing\\n\");\n        effect_planboing(AXIS_Z, 450);\n        effect_planboing(AXIS_Y, 450);\n        effect_planboing(AXIS_X, 450);\n\n        printf(\"blinky2\\n\");\n        effect_blinky2();\n\n        printf(\"mirror ripples\\n\");\n        mirror_ripples(600, 200);\n\n        printf(\"axis_updown_randsuspend\\n\");\n        effect_axis_updown_randsuspend(AXIS_Z, 250, 2500, 0);\n        effect_axis_updown_randsuspend(AXIS_Z, 250, 2500, 1);\n        effect_axis_updown_randsuspend(AXIS_Z, 250, 2500, 0);\n        effect_axis_updown_randsuspend(AXIS_Z, 250, 2500, 1);\n        effect_axis_updown_randsuspend(AXIS_X, 250, 2500, 0);\n        effect_axis_updown_randsuspend(AXIS_X, 250, 2500, 1);\n        effect_axis_updown_randsuspend(AXIS_Y, 250, 2500, 0);\n        effect_axis_updown_randsuspend(AXIS_Y, 250, 2500, 1);\n\n        printf(\"rand_patharound\\n\");\n        effect_rand_patharound(200, 250);\n\n        printf(\"fireworks\\n\");\n        fireworks(10, 250);\n\n        //printf(\"random_filler\\n\");\n        //effect_random_filler(35, 1);\n        //effect_random_filler(35, 0);\n\n        printf(\"rain\\n\");\n        effect_rain(100);\n\n        printf(\"side ripples\\n\");\n        side_ripples(300, 250);\n\n        printf(\"text up\\n\");\n        effect_text_up(\"MIPS RETROBSD\", 600);\n\n        printf(\"random sparkle\\n\");\n        effect_random_sparkle();\n\n        printf(\"quad ripples\\n\");\n        quad_ripples(600, 150);\n\n        printf(\"boxside_randsend_parallel\\n\");\n        effect_boxside_randsend_parallel(AXIS_X, 0, 70, 1);\n        effect_boxside_randsend_parallel(AXIS_X, 1, 70, 1);\n        effect_boxside_randsend_parallel(AXIS_Y, 0, 70, 1);\n        effect_boxside_randsend_parallel(AXIS_Y, 1, 70, 1);\n        effect_boxside_randsend_parallel(AXIS_Z, 0, 70, 1);\n        effect_boxside_randsend_parallel(AXIS_Z, 1, 70, 1);\n    }\n}\n"
  },
  {
    "path": "share/examples/cube/duinomite.c",
    "content": "/*\n * Interface to LED cube 8x8x8.\n * The cube is connected to pins D0-D9 of Duinomite board.\n *\n * Pin  PIC32  Function\n * ---------------\n *  D0  RE0    Y0  \\\n *  D1  RE1    Y1  | Layer select\n *  D2  RE2    Y2  /\n *  D3  RE3    Y3  - Upper backlignt\n *  D4  RE4    Y4  - Lower backlight\n *  D5  RE5    SDI - Serial data   \\\n *  D6  RE6    CLK - Clock         | to shift registers\n *  D7  RE7    /LE - Latch enable  |\n *  D8  RB11   /OE - Output enable /\n *  D10 RD11   EXT - Unknown\n */\n#include <stdlib.h>\n#include <stdio.h>\n#include <sys/ioctl.h>\n#include <sys/gpio.h>\n#include \"cube.h\"\n\nstatic int gpio;\n\nvoid gpio_init()\n{\n    char *devname = \"/dev/porta\";\n\n    /* Open GPIO driver. */\n    gpio = open(devname, 1);\n    if (gpio < 0) {\n        perror(devname);\n        exit(-1);\n    }\n\n    /* Configure pins RE0-RE7, RB11 and RD11 as output. */\n    ioctl(gpio, GPIO_PORTE | GPIO_CONFOUT, 0xff);\n    ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, 0xff);\n    ioctl(gpio, GPIO_PORTB | GPIO_CONFOUT, 1 << 11);\n    ioctl(gpio, GPIO_PORTB | GPIO_CLEAR, 1 << 11);\n    ioctl(gpio, GPIO_PORTD | GPIO_CONFOUT, 1 << 11);\n    ioctl(gpio, GPIO_PORTD | GPIO_CLEAR, 1 << 11);\n}\n\nvoid gpio_ext(int on)\n{\n    /* EXT signal at RD11. */\n    if (on)\n        ioctl(gpio, GPIO_PORTD | GPIO_SET, 1 << 11);\n    else\n        ioctl(gpio, GPIO_PORTD | GPIO_CLEAR, 1 << 11);\n}\n\nvoid gpio_oe(int active)\n{\n    /* /OE signal at RB11, active low. */\n    if (active)\n        ioctl(gpio, GPIO_PORTB | GPIO_CLEAR, 1 << 11);\n    else\n        ioctl(gpio, GPIO_PORTB | GPIO_SET, 1 << 11);\n}\n\nvoid gpio_le(int active)\n{\n    /* /LE signal at RE7, active low. */\n    if (active)\n        ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, 1 << 7);\n    else\n        ioctl(gpio, GPIO_PORTE | GPIO_SET, 1 << 7);\n}\n\nvoid gpio_backlight_upper(int on)\n{\n    /* Y4 signal at RE4. */\n    if (on)\n        ioctl(gpio, GPIO_PORTE | GPIO_SET, 1 << 4);\n    else\n        ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, 1 << 4);\n}\n\nvoid gpio_backlight_lower(int on)\n{\n    /* Y3 signal at RE3. */\n    if (on)\n        ioctl(gpio, GPIO_PORTE | GPIO_SET, 1 << 3);\n    else\n        ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, 1 << 3);\n}\n\nvoid gpio_layer(int z)\n{\n    /* Y0-Y2 signals at RE0-RE23. */\n    if (z & 1)\n        ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, 1 << 0);\n    else\n        ioctl(gpio, GPIO_PORTE | GPIO_SET, 1 << 0);\n\n    if (z & 2)\n        ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, 1 << 1);\n    else\n        ioctl(gpio, GPIO_PORTE | GPIO_SET, 1 << 1);\n\n    if (z & 4)\n        ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, 1 << 2);\n    else\n        ioctl(gpio, GPIO_PORTE | GPIO_SET, 1 << 2);\n}\n\nvoid gpio_plane(unsigned char *data)\n{\n    int i, n, val;\n\n    /* Send 8 bytes of tada to shift registers. */\n    for (i=0; i<8; i+=2) {\n        val = *data++;\n        for (n=0; n<8; n++) {\n            /* SDI signal at RE5. */\n            if (val & 0x80)\n                ioctl(gpio, GPIO_PORTE | GPIO_SET, 1 << 5);\n            else\n                ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, 1 << 5);\n\n            /* CLK signal at RE6. */\n            ioctl(gpio, GPIO_PORTE | GPIO_SET, 1 << 6);\n            ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, 1 << 6);\n\n            val <<= 1;\n        }\n        val = *data++;\n        for (n=0; n<8; n++) {\n            /* SDI signal at RE5. */\n            if (val & 1)\n                ioctl(gpio, GPIO_PORTE | GPIO_SET, 1 << 5);\n            else\n                ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, 1 << 5);\n\n            /* CLK signal at RE6. */\n            ioctl(gpio, GPIO_PORTE | GPIO_SET, 1 << 6);\n            ioctl(gpio, GPIO_PORTE | GPIO_CLEAR, 1 << 6);\n\n            val >>= 1;\n        }\n    }\n}\n"
  },
  {
    "path": "share/examples/cube/fubarino.c",
    "content": "/*\n * Interface to LED cube 8x8x8.\n * The cube is connected to pins 4-13 of Fubarino board.\n *\n * Pin  PIC32  Function\n * ---------------\n *  4   RD0    Y0  \\\n *  5   RC13   Y1  | Layer select\n *  6   RC14   Y2  /\n *  7   RD1    Y3  - Upper backlignt\n *  8   RD2    Y4  - Lower backlight\n *  9   RD3    SDI - Serial data   \\\n *  10  RD4    CLK - Clock         | to shift registers\n *  11  RD5    /LE - Latch enable  |\n *  12  RD6    /OE - Output enable /\n *  13  RD7    EXT - Unknown\n */\n#include <stdlib.h>\n#include <stdio.h>\n#include <sys/ioctl.h>\n#include <sys/gpio.h>\n#include \"cube.h\"\n\nstatic int gpio;\n\nvoid gpio_init()\n{\n    char *devname = \"/dev/porta\";\n\n    /* Open GPIO driver. */\n    gpio = open(devname, 1);\n    if (gpio < 0) {\n        perror(devname);\n        exit(-1);\n    }\n\n    /* Configure pins RD0-RD7, RC13 and RC14 as output. */\n    ioctl(gpio, GPIO_PORTD | GPIO_CONFOUT, 0xff);\n    ioctl(gpio, GPIO_PORTD | GPIO_CLEAR, 0xff);\n    ioctl(gpio, GPIO_PORTC | GPIO_CONFOUT, 3 << 13);\n    ioctl(gpio, GPIO_PORTC | GPIO_CLEAR, 3 << 13);\n}\n\nvoid gpio_ext(int on)\n{\n    /* EXT signal at RD7. */\n    if (on)\n        ioctl(gpio, GPIO_PORTD | GPIO_SET, 1 << 7);\n    else\n        ioctl(gpio, GPIO_PORTD | GPIO_CLEAR, 1 << 7);\n}\n\nvoid gpio_oe(int active)\n{\n    /* /OE signal at RD6, active low. */\n    if (active)\n        ioctl(gpio, GPIO_PORTD | GPIO_CLEAR, 1 << 6);\n    else\n        ioctl(gpio, GPIO_PORTD | GPIO_SET, 1 << 6);\n}\n\nvoid gpio_le(int active)\n{\n    /* /LE signal at RD5, active low. */\n    if (active)\n        ioctl(gpio, GPIO_PORTD | GPIO_CLEAR, 1 << 5);\n    else\n        ioctl(gpio, GPIO_PORTD | GPIO_SET, 1 << 5);\n}\n\nvoid gpio_backlight_upper(int on)\n{\n    /* Y4 signal at RD2. */\n    if (on)\n        ioctl(gpio, GPIO_PORTD | GPIO_SET, 1 << 2);\n    else\n        ioctl(gpio, GPIO_PORTD | GPIO_CLEAR, 1 << 2);\n}\n\nvoid gpio_backlight_lower(int on)\n{\n    /* Y3 signal at RD1. */\n    if (on)\n        ioctl(gpio, GPIO_PORTD | GPIO_SET, 1 << 1);\n    else\n        ioctl(gpio, GPIO_PORTD | GPIO_CLEAR, 1 << 1);\n}\n\nvoid gpio_layer(int z)\n{\n    /* Y0-Y2 signals at RD0, RC13, RC14. */\n    if (z & 1)\n        ioctl(gpio, GPIO_PORTD | GPIO_CLEAR, 1 << 0);\n    else\n        ioctl(gpio, GPIO_PORTD | GPIO_SET, 1 << 0);\n\n    if (z & 2)\n        ioctl(gpio, GPIO_PORTC | GPIO_CLEAR, 1 << 13);\n    else\n        ioctl(gpio, GPIO_PORTC | GPIO_SET, 1 << 13);\n\n    if (z & 4)\n        ioctl(gpio, GPIO_PORTC | GPIO_CLEAR, 1 << 14);\n    else\n        ioctl(gpio, GPIO_PORTC | GPIO_SET, 1 << 14);\n}\n\nvoid gpio_plane(unsigned char *data)\n{\n    int i, n, val;\n\n    /* Send 8 bytes of tada to shift registers. */\n    for (i=0; i<8; i+=2) {\n        val = *data++;\n        for (n=0; n<8; n++) {\n            /* SDI signal at RD3. */\n            if (val & 0x80)\n                ioctl(gpio, GPIO_PORTD | GPIO_SET, 1 << 3);\n            else\n                ioctl(gpio, GPIO_PORTD | GPIO_CLEAR, 1 << 3);\n\n            /* CLK signal at RD4. */\n            ioctl(gpio, GPIO_PORTD | GPIO_SET, 1 << 4);\n            ioctl(gpio, GPIO_PORTD | GPIO_CLEAR, 1 << 4);\n\n            val <<= 1;\n        }\n        val = *data++;\n        for (n=0; n<8; n++) {\n            /* SDI signal at RD3. */\n            if (val & 1)\n                ioctl(gpio, GPIO_PORTD | GPIO_SET, 1 << 3);\n            else\n                ioctl(gpio, GPIO_PORTD | GPIO_CLEAR, 1 << 3);\n\n            /* CLK signal at RD4. */\n            ioctl(gpio, GPIO_PORTD | GPIO_SET, 1 << 4);\n            ioctl(gpio, GPIO_PORTD | GPIO_CLEAR, 1 << 4);\n\n            val >>= 1;\n        }\n    }\n}\n"
  },
  {
    "path": "share/examples/curses/Makefile",
    "content": "PROG    = flip jump timer typetext\n#CFLAGS  = -DNCURSES_OPAQUE=0\nLIBS    = -lcurses -ltermlib\n\nall:    $(PROG)\n\nclean:\n\trm -f *.o *~ $(PROG)\n\nflip:   flip.c\n\tcc $(CFLAGS) -o $@ $@.c $(LIBS)\n\njump:   jump.c\n\tcc $(CFLAGS) -o $@ $@.c $(LIBS)\n\ntimer:  timer.c\n\tcc $(CFLAGS) -o $@ $@.c $(LIBS)\n\ntypetext: typetext.c\n\tcc $(CFLAGS) -o $@ $@.c $(LIBS)\n"
  },
  {
    "path": "share/examples/curses/flip.c",
    "content": "#include <curses.h>\n#include <signal.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <string.h>\n\n#define W_LINES 10\n#define W_COLS  30\n\n#define center(WIND,LN,TEXT)    \\\n\tmvwaddstr((WIND), (LN), (W_COLS - strlen(TEXT))/2, (TEXT))\n\nvoid die(int sig)\n{\n    signal(sig, SIG_IGN);\n    clear();\n    refresh();\n    endwin();\n    exit(0);\n}\n\nint main()\n{\n    WINDOW *win1, *win2;\n\n    if (! initscr()) {\n        fprintf(stderr, \"Sorry, unknown terminal.\\n\");\n        exit(1);\n    }\n\n    signal(SIGINT, die);\n    signal(SIGQUIT, die);\n    signal(SIGHUP, die);\n\n    noecho();\n\n    win1 = newwin(W_LINES, W_COLS, ((LINES - W_LINES)/2), ((COLS - W_COLS)/2));\n    win2 = newwin(W_LINES, W_COLS, ((LINES - W_LINES)/2 + 4), ((COLS - W_COLS)/2 + 10));\n\n    scrollok(win1, FALSE);\n    scrollok(win2, FALSE);\n\n    box(win1, '*', '*');\n    box(win2, '*', '*');\n\n    center(win1, 3, \"This is window 1\");\n    center(win2, 3, \"This is window 2\");\n\n    for (;;) {\n        wrefresh(win1);\n        touchwin(win1);\n        usleep(200000);\n        wrefresh(win2);\n        touchwin(win2);\n        usleep(200000);\n    }\n}\n"
  },
  {
    "path": "share/examples/curses/jump.c",
    "content": "#include <curses.h>\n#include <signal.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <string.h>\n#include <time.h>\n\n#define W_LINES 7\n#define W_COLS  11\n\nvoid die(int sig)\n{\n    signal(sig, SIG_IGN);\n    werase(curscr);\n    wmove(curscr, 0, 0);\n    wrefresh(curscr);\n    endwin();\n    exit(0);\n}\n\nint main()\n{\n    WINDOW *win, *blank;\n    int x, y;\n\n    if (! initscr()) {\n        fprintf(stderr, \"Sorry, unknown terminal.\\n\");\n        exit(1);\n    }\n\n    signal(SIGINT, die);\n    signal(SIGQUIT, die);\n    signal(SIGHUP, die);\n\n    noecho();\n\n    //delwin(stdscr);\n\n    win = newwin(W_LINES, W_COLS, 0, 0);\n    blank = newwin(W_LINES, W_COLS, 0, 0);\n\n    box(win, '*', '*');\n    mvwaddstr(win, W_LINES/2, (W_COLS - strlen(\"RetroBSD\"))/2, \"RetroBSD\");\n\n    srand(time(0));\n\n    for (;;) {\n        x = rand() % (COLS - W_COLS);\n        y = rand() % (LINES - W_LINES);\n        wrefresh(blank);\n        if (mvwin(win, y, x) == OK) {\n            wrefresh(win);\n            usleep(500000);\n            mvwin(blank, y, x);\n        }\n    }\n}\n"
  },
  {
    "path": "share/examples/curses/timer.c",
    "content": "#include <curses.h>\n#include <signal.h>\n#include <string.h>\n#include <strings.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <time.h>\n\n#define centered(y,str) mvaddstr(y, (COLS - strlen(str))/2, str)\n\nvoid die()\n{\n    alarm(0);\n    signal(SIGINT, SIG_IGN);\n    signal(SIGQUIT, SIG_IGN);\n    signal(SIGHUP, SIG_IGN);\n    signal(SIGTERM, SIG_IGN);\n    clear();\n    refresh();\n    endwin();\n    exit(0);\n}\n\nint main(int ac, char **av)\n{\n    int     move_col,\n            msec;\n    int     time_line,\n            move_line;\n    long    num_start_time,\n            num_now_time;\n    char    str_start_time[60],\n            str_now_time[60];\n\n    msec = 0;\n    if (ac > 1) {\n        msec = atoi(av[1]);\n\tif (msec < 10)\n\t    msec = 10;\n\telse if (msec > 1000)\n\t    msec = 1000;\n    }\n    if (! initscr())\n\texit(1);\n\n    signal(SIGINT, die);\n    signal(SIGQUIT, die);\n    signal(SIGHUP, die);\n    signal(SIGTERM, die);\n\n    box(stdscr, '*', '*');\n\n    time(&num_start_time);\n    strcpy(str_start_time, ctime(&num_start_time));\n    *(index(str_start_time, '\\n')) = '\\0';\n\n    centered(3, \"*** Test started at: ***\");\n    centered(4, str_start_time);\n\n    move_col = 1;\n    move_line = (LINES - 2) / 2;\n    time_line = move_line + (LINES - move_line - 1) / 2;\n\n    while (TRUE) {\n\ttime(&num_now_time);\n\tstrcpy(str_now_time, ctime(&num_now_time));\n\t*(index(str_now_time, '\\n')) = '\\0';\n\n\tcentered(time_line, str_now_time);\n\n\tmvaddstr(move_line, move_col, \"<-*->\");\n\n\trefresh();\n\n\tmvaddstr(move_line, move_col, \"     \");\n\tif (++move_col >= (COLS - 6))\n\t    move_col = 1;\n\n\tif (msec)\n\t    usleep(msec * 1000);\n    }\n}\n"
  },
  {
    "path": "share/examples/curses/typetext.c",
    "content": "#include <curses.h>\n#include <signal.h>\n#include <ctype.h>\n#include <stdlib.h>\n\n#define CNTRL(c)        ((c) &037)\n\nvoid die(int sig)\n{\n    signal(sig, SIG_IGN);\n    move((LINES - 1), 0);\n    refresh();\n    endwin();\n    exit(0);\n}\n\nint main()\n{\n    WINDOW *win, *boxing;\n    int c;\n    int x, y;\n\n    initscr();\n\n    signal(SIGINT, die);\n    noecho();\n    crmode();\n\n    win = subwin(stdscr,\n\t    LINES / 2,\n\t    COLS / 2,\n\t    LINES / 4,\n\t    COLS / 4);\n    scrollok(win, TRUE);\n\n    boxing = subwin(stdscr,\n\t    LINES / 2 + 2,\n\t    COLS / 2 + 2,\n\t    LINES / 4 - 1,\n\t    COLS / 4 - 1);\n\n    box(boxing, '!', '-');\n    refresh();\n\n    wmove(win, 0, 0);\n    wrefresh(win);\n\n    while ((c = wgetch(win)) != '#') {\n\tif (iscntrl(c)) {\n\t    switch (c) {\n            case CNTRL('E'):\n                werase(win);\n                wrefresh(win);\n                continue;\n\n            case CNTRL('R'):\n                wrefresh(curscr);\n                continue;\n\n            case CNTRL('['):\n                getyx(win, y, x);\n                c = wgetch(win);\n                if (c == '[' || c == 'O')\n                    c = wgetch(win);\n                switch (c) {\n                case 'H':\n                    x = 0;\n                    y = 0;\n                    goto change;\n                case 'A':\n                    y--;\n                    goto change;\n                case 'B':\n                    y++;\n                    goto change;\n                case 'C':\n                    x++;\n                    goto change;\n                case 'D':\n                    x--;\nchange:\n                    if (x >= win->_maxx) {\n                        x = 0;\n                        y++;\n                    }\n                    if (y >= win->_maxy)\n                        y = 0;\n                    wmove(win, y, x);\n                    wrefresh(win);\n                    continue;\n                default:\n                    break;\n                }\n                break;\n            default:\n                continue;\n\t    }\n        }\n\twaddch(win, c);\n\twrefresh(win);\n    }\n    die(SIGINT);\n}\n"
  },
  {
    "path": "share/examples/dhrystone/Makefile",
    "content": "OBJS    = dhry_1.o dhry_2.o\n\nall:    dhrystone\n\ndhrystone: $(OBJS)\n\t$(CC) $(LDFLAGS) -o $@ $(OBJS)\n\nclean:\n\trm -f *.o dhrystone\n"
  },
  {
    "path": "share/examples/dhrystone/RATIONALE",
    "content": "\n\n    Dhrystone Benchmark: Rationale for Version 2 and Measurement Rules\n\n        [published in SIGPLAN Notices 23,8 (Aug. 1988), 49-62]\n\n\n                 Reinhold P. Weicker\n                 Siemens AG, E STE 35\n                 [now: Siemens AG, AUT E 51]\n                 Postfach 3220\n                 D-8520 Erlangen\n                 Germany (West)\n\n\n\n\n1.  Why a Version 2 of Dhrystone?\n\nThe Dhrystone benchmark  program  [1]  has  become  a  popular  benchmark  for\nCPU/compiler   performance   measurement,   in   particular  in  the  area  of\nminicomputers, workstations, PC's and microprocesors.  It apparently satisfies\na  need  for  an  easy-to-use  integer benchmark; it gives a first performance\nindication which is more meaningful than MIPS numbers which, in their  literal\nmeaning  (million  instructions  per  second), cannot be used across different\ninstruction sets (e.g. RISC  vs.  CISC).   With  the  increasing  use  of  the\nbenchmark, it seems necessary to reconsider the benchmark and to check whether\nit can still fulfill this function.  Version 2 of Dhrystone is the  result  of\nsuch a re-evaluation, it has been made for two reasons:\n\no Dhrystone has been published in Ada [1], and Versions in Ada, Pascal  and  C\n  have  been  distributed  by  Reinhold Weicker via floppy disk.  However, the\n  version that was used most often for benchmarking has been the version  made\n  by  Rick  Richardson  by another translation from the Ada version into the C\n  programming language, this has been the version  distributed  via  the  UNIX\n  network Usenet [2].\n\n  There is an obvious need for a common C version of Dhrystone, since C is  at\n  present  the  most  popular  system  programming  language  for the class of\n  systems (microcomputers, minicomputers,  workstations)  where  Dhrystone  is\n  used  most.   There  should  be,  as  far as possible, only one C version of\n  Dhrystone such that results can be compared  without  restrictions.  In  the\n  past,  the  C  versions  distributed by Rick Richardson (Version 1.1) and by\n  Reinhold Weicker had small (though not significant) differences.\n\n  Together with the new C version, the  Ada  and  Pascal  versions  have  been\n  updated as well.\n\no As far as it is  possible  without  changes  to  the  Dhrystone  statistics,\n  optimizing   compilers   should   be  prevented  from  removing  significant\n  statements.  It has  turned  out  in  the  past  that  optimizing  compilers\n  suppressed  code  generation for too many statements (by \"dead code removal\"\n  or  \"dead  variable  elimination\").   This  has  lead  to  the  danger  that\n  benchmarking  results obtained by a naive application of Dhrystone - without\n  inspection of the code that was generated - could become meaningless.\n\nThe  overall  policiy  for  version  2  has  been  that  the  distribution  of\nstatements,  operand types and operand locality described in [1] should remain\nunchanged as much as possible.  (Very few changes were necessary; their impact\nshould be negligible.)  Also, the order of statements should remain unchanged.\nAlthough I am aware of some critical remarks on the benchmark - I  agree  with\nseveral  of them - and know some suggestions for improvement, I didn't want to\nchange the benchmark into something different from what has  become  known  as\n\"Dhrystone\"; the confusion generated by such a change would probably outweight\nthe benefits. If I were to write a new benchmark program, I wouldn't  give  it\nthe  name  \"Dhrystone\"  since  this  denotes  the  program  published  in [1].\nHowever, I do recognize  the  need  for  a  larger  number  of  representative\nprograms  that can be used as benchmarks; users should always be encouraged to\nuse more than just one benchmark.\n\nThe new versions (version 2.1 for C, Pascal and Ada) will  be  distributed  as\nwidely as possible.  (Version 2.1 differs from version 2.0 distributed via the\nUNIX Network Usenet in  March  1988  only  in  a  few  corrections  for  minor\ndeficiencies  found  by  users  of  version 2.0.)  Readers who want to use the\nbenchmark for their own measurements can obtain  a  copy  in  machine-readable\nform on floppy disk (MS-DOS or XENIX format) from the author.\n\n\n2.  Overall Characteristics of Version 2\n\nIn general, version 2  follows  -  in  the  parts  that  are  significant  for\nperformance  measurement,  i.e.   within  the measurement loop - the published\n(Ada) version and the C versions previously distributed.  Where  the  versions\ndistributed  by  Rick Richardson [2] and Reinhold Weicker have been different,\nit  follows  the  version  distributed  by  Reinhold  Weicker.  (However,  the\ndifferences  have  been  so  small  that their impact on execution time in all\nlikelihood has been negligible.)  The initialization and UNIX  instrumentation\npart  -  which  had  been  omitted  in  [1] - follows mostly the ideas of Rick\nRichardson [2].  However, any changes in the initialization part  and  in  the\nprinting  of  the  result have no impact on performance measurement since they\nare outside the measaurement loop.  As a concession to older compilers,  names\nhave been made unique within the first 8 characters for the C version.\n\nThe original publication of Dhrystone did not contain any statements for  time\nmeasurement  since  they  are necessarily system-dependent. However, it turned\nout that it is not enough just to inclose the main procedure of Dhrystone in a\nloop  and  to  measure the execution time.  If the variables that are computed\nare not used somehow, there is the danger that the compiler considers them  as\n\"dead  variables\" and suppresses code generation for a part of the statements.\nTherefore in version 2 all variables of \"main\" are printed at the end  of  the\nprogram.  This also permits some plausibility control for correct execution of\nthe benchmark.\n\nAt several places in the benchmark, code has been added, but only in  branches\nthat  are  not  executed. The intention is that optimizing compilers should be\nprevented from moving code out of the measurement loop, or from removing  code\naltogether.  Statements that are executed have been changed in very few places\nonly.  In these cases, only the role of some operands has been changed, and it\nwas   made  sure  that  the  numbers  defining  the  \"Dhrystone  distribution\"\n(distribution of statements, operand types and locality) still hold as much as\npossible.   Except for sophisticated optimizing compilers, execution times for\nversion 2.1 should be the same as for previous versions.\n\nBecause of the self-imposed limitation that the order and distribution of  the\nexecuted  statements  should  not  be  changed,  there  are  still cases where\noptimizing compilers may not generate code for some statements. To  a  certain\ndegree,  this  is  unavoidable  for  small synthetic benchmarks.  Users of the\nbenchmark are advised to check code listings whether code is generated for all\nstatements of Dhrystone.\n\nContrary to the suggestion in the published paper and its realization  in  the\nversions previously distributed, no attempt has been made to subtract the time\nfor the measurement loop overhead. (This calculation has proven  difficult  to\nimplement  in  a  correct  way,  and  its omission makes the program simpler.)\nHowever, since the loop check is now part of the benchmark, this does have  an\nimpact  -  though a very minor one - on the distribution statistics which have\nbeen updated for this version.\n\n\n3.  Discussion of Individual Changes\n\nIn this section, all changes are described that affect  the  measurement  loop\nand  that  are  not  just  renamings  of variables. All remarks refer to the C\nversion; the other language versions have been updated similarly.\n\nIn addition to adding  the  measurement  loop  and  the  printout  statements,\nchanges have been made at the following places:\n\no In procedure \"main\", three statements have been added  in  the  non-executed\n  \"then\" part of the statement\n\n        if (Enum_Loc == Func_1 (Ch_Index, 'C'))\n\n  they are\n\n        strcpy (Str_2_Loc, \"DHRYSTONE PROGRAM, 3'RD STRING\");\n        Int_2_Loc = Run_Index;\n        Int_Glob = Run_Index;\n\n  The string assignment prevents  movement  of  the  preceding  assignment  to\n  Str_2_Loc  (5'th  statement  of  \"main\")  out  of the measurement loop (This\n  probably will not happen for the C version, but it did happen  with  another\n  language   and  compiler.)   The  assignment  to  Int_2_Loc  prevents  value\n  propagation for Int_2_Loc, and the assignment to Int_Glob makes the value of\n  Int_Glob possibly dependent from the value of Run_Index.\n\no In the three arithmetic computations at the end of the measurement  loop  in\n  \"main  \",  the  role  of  some  variables has been exchanged, to prevent the\n  division from just cancelling out the multiplication as it was  in  [1].   A\n  very   smart  compiler  might  have  recognized  this  and  suppressed  code\n  generation for the division.\n\no For Proc_2, no code has been changed, but the values of the actual parameter\n  have changed due to changes in \"main\".\n\no In Proc_4, the second assignment has been changed from\n\n        Bool_Loc = Bool_Loc | Bool_Glob;\n\n  to\n\n        Bool_Glob = Bool_Loc | Bool_Glob;\n\n  It now assigns a value to a global variable  instead  of  a  local  variable\n  (Bool_Loc);   Bool_Loc  would  be  a  \"dead  variable\"  which  is  not  used\n  afterwards.\n\no In Func_1, the statement\n\n        Ch_1_Glob = Ch_1_Loc;\n\n  was added in the non-executed \"else\" part of the \"if\" statement, to  prevent\n  the suppression of code generation for the assignment to Ch_1_Loc.\n\no In Func_2, the second character comparison statement has been changed to\n\n        if (Ch_Loc == 'R')\n\n  ('R' instead of 'X') because  a  comparison  with  'X'  is  implied  in  the\n  preceding \"if\" statement.\n\n  Also in Func_2, the statement\n\n        Int_Glob = Int_Loc;\n\n  has been added in the non-executed part of the last \"if\" statement, in order\n  to prevent Int_Loc from becoming a dead variable.\n\no In Func_3, a non-executed \"else\" part has been added to the \"if\"  statement.\n  While  the  program  would  not be incorrect without this \"else\" part, it is\n  considered bad programming practice if a function  can  be  left  without  a\n  return value.\n\n  To compensate for this change, the (non-executed) \"else\" part  in  the  \"if\"\n  statement of Proc_3 was removed.\n\nThe distribution statistics have been changed only  by  the  addition  of  the\nmeasurement loop iteration (1 additional statement, 4 additional local integer\noperands) and by the change in Proc_4  (one  operand  changed  from  local  to\nglobal).  The distribution statistics in the comment headers have been updated\naccordingly.\n\n\n4.  String Operations\n\nThe string operations (string assignment and string comparison) have not  been\nchanged, to keep the program consistent with the original version.\n\nThere has been some concern that the string operations are over-represented in\nthe  program,  and that execution time is dominated by these operations.  This\nwas true in particular when optimizing compilers removed too much code in  the\nmain part of the program, this should have been mitigated in version 2.\n\nIt should be noted that this is a  language-dependent  issue:   Dhrystone  was\nfirst  published  in  Ada, and with Ada or Pascal semantics, the time spent in\nthe string operations is,  at  least  in  all  implementations  known  to  me,\nconsiderably smaller.  In Ada and Pascal, assignment and comparison of strings\nare operators defined in the language, and the upper  bounds  of  the  strings\noccuring  in  Dhrystone  are part of the type information known at compilation\ntime.  The compilers can therefore generate  efficient  inline  code.   In  C,\nstring  assignemt  and comparisons are not part of the language, so the string\noperations must be expressed in terms of the C library functions \"strcpy\"  and\n\"strcmp\".   (ANSI  C  allows  an  implementation  to use inline code for these\nfunctions.)  In addition to the overhead caused by additional function  calls,\nthese  functions  are  defined for null-terminated strings where the length of\nthe strings is not known at compilation time; the function has to check  every\nbyte for the termination condition (the null byte).\n\nObviously, a C library which includes efficiently coded \"strcpy\" and  \"strcmp\"\nfunctions  helps to obtain good Dhrystone results. However, I don't think that\nthis is unfair since string  functions  do  occur  quite  frequently  in  real\nprograms  (editors, command interpreters, etc.).  If the strings functions are\nimplemented efficiently,  this  helps  real  programs  as  well  as  benchmark\nprograms.\n\nI admit that the  string  comparison  in  Dhrystone  terminates  later  (after\nscanning  20  characters)  than most string comparisons in real programs.  For\nconsistency with the original benchmark, I didn't change the  program  despite\nthis weakness.\n\n\n5.  Intended Use of Dhrystone\n\nWhen Dhrystone is used, the following \"ground rules\" apply:\n\no Separate compilation (Ada and C versions)\n\n  As mentioned in [1], Dhrystone was written  to  reflect  actual  programming\n  practice  in  systems  programming.   The  division into several compilation\n  units (5 in the Ada version, 2 in the C version)  is  intended,  as  is  the\n  distribution of inter-module and intra-module subprogram calls.  Although on\n  many systems there will be no difference in execution time  to  a  Dhrystone\n  version  where  all  compilation units are merged into one file, the rule is\n  that separate compilation should  be  used.   The  intention  is  that  real\n  programming  practice,  where  programs  consist  of  several  independently\n  compiled units, should  be  reflected.   This  also  has  implies  that  the\n  compiler,  while  compiling  one  unit,  has no information about the use of\n  variables, register allocation etc.  occuring in  other  compilation  units.\n  Although  in  real  life  compilation  units  will  probably  be larger, the\n  intention is that these effects  of  separate  compilation  are  modeled  in\n  Dhrystone.\n\n  A few language systems have post-linkage optimization available (e.g., final\n  register allocation is performed after linkage).  This is a borderline case:\n  Post-linkage  optimization  involves  additional  program  preparation  time\n  (although  not  as  much  as  compilation in one unit) which may prevent its\n  general use in practical programming.  I think that  since  it  defeats  the\n  intentions given above, it should not be used for Dhrystone.\n\n  Unfortunately, ISO/ANSI  Pascal  does  not  contain  language  features  for\n  separate  compilation.   Although  most  commercial Pascal compilers provide\n  separate compilation in some way, we cannot use it for Dhrystone since  such\n  a  version  would  not  be portable.  Therefore, no attempt has been made to\n  provide a Pascal version with several compilation units.\n\no No procedure merging\n\n  Although Dhrystone contains some very short procedures where execution would\n  benefit  from  procedure  merging (inlining, macro expansion of procedures),\n  procedure merging is not to be used.  The reason is that the  percentage  of\n  procedure  and  function  calls  is  part of the \"Dhrystone distribution\" of\n  statements contained in [1].  This restriction does not hold for the  string\n  functions  of  the  C  version  since ANSI C allows an implementation to use\n  inline code for these functions.\n\no Other optimizations are allowed, but they should be indicated\n\n  It is often hard to draw an exact line between \"normal code generation\"  and\n  \"optimization\"  in  compilers:  Some compilers perform operations by default\n  that are invoked in other compilers only  when  optimization  is  explicitly\n  requested.  Also, we cannot avoid that in benchmarking people try to achieve\n  results that look as good as possible.  Therefore,  optimizations  performed\n  by  compilers  -  other  than  those  listed  above - are not forbidden when\n  Dhrystone execution times are measured.  Dhrystone is  not  intended  to  be\n  non-optimizable  but  is  intended  to  be  similarly  optimizable as normal\n  programs.   For  example,  there  are  several  places  in  Dhrystone  where\n  performance   benefits   from   optimizations   like   common  subexpression\n  elimination, value  propagation  etc.,  but  normal  programs  usually  also\n  benefit  from  these  optimizations.   Therefore,  no  effort  was  made  to\n  artificially  prevent  such  optimizations.   However,  measurement  reports\n  should  indicate  which  compiler  optimization  levels  have been used, and\n  reporting results with different levels of  compiler  optimization  for  the\n  same hardware is encouraged.\n\no Default results are those without \"register\" declarations (C version)\n\n  When Dhrystone results are quoted  without  additional  qualification,  they\n  should  be  understood  as  results  obtained  without use of the \"register\"\n  attribute. Good compilers should be able to make good use of registers  even\n  without explicit register declarations ([3], p. 193).\n\nOf course, for experimental  purposes,  post-linkage  optimization,  procedure\nmerging and/or compilation in one unit can be done to determine their effects.\nHowever,  Dhrystone  numbers  obtained  under  these  conditions   should   be\nexplicitly  marked as such; \"normal\" Dhrystone results should be understood as\nresults obtained following the ground rules listed above.\n\nIn any case, for serious performance evaluation, users are advised to ask  for\ncode  listings  and  to  check  them carefully.  In this way, when results for\ndifferent systems are  compared,  the  reader  can  get  a  feeling  how  much\nperformance  difference is due to compiler optimization and how much is due to\nhardware speed.\n\n\n6.  Acknowledgements\n\nThe C version 2.1 of Dhrystone has been developed  in  cooperation  with  Rick\nRichardson  (Tinton  Falls,  NJ), it incorporates many ideas from the \"Version\n1.1\" distributed previously by him over the UNIX network Usenet.  Through  his\nactivity with Usenet, Rick Richardson has made a very valuable contribution to\nthe dissemination of the benchmark.  I also thank  Chaim  Benedelac  (National\nSemiconductor),  David Ditzel (SUN), Earl Killian and John Mashey (MIPS), Alan\nSmith and Rafael  Saavedra-Barrera  (UC  at  Berkeley)  for  their  help  with\ncomments on earlier versions of the benchmark.\n\n\n7.  Bibliography\n\n[1]\n   Reinhold P. Weicker: Dhrystone: A Synthetic Systems Programming Benchmark.\n   Communications of the ACM 27, 10 (Oct. 1984), 1013-1030\n\n[2]\n   Rick Richardson: Dhrystone 1.1 Benchmark Summary (and Program Text)\n   Informal Distribution via \"Usenet\", Last Version Known  to  me:  Sept.  21,\n   1987\n\n[3]\n   Brian W. Kernighan and Dennis M. Ritchie:  The C Programming Language.\n   Prentice-Hall, Englewood Cliffs (NJ) 1978\n\n"
  },
  {
    "path": "share/examples/dhrystone/README",
    "content": "Downloaded from:\n    http://www.netlib.org/benchmark/dhry-c\n\nCalls time() and times() replaced by gettimeofday().\n"
  },
  {
    "path": "share/examples/dhrystone/README_C",
    "content": "This \"shar\" file contains the documentation for the\nelectronic mail distribution of the Dhrystone benchmark (C version 2.1);\na companion \"shar\" file contains the source code.\n(Because of mail length restrictions for some mailers, I have\nsplit the distribution in two parts.)\n\nFor versions in other languages, see the other \"shar\" files.\n\nFiles containing the C version (*.h: Header File, *.c: C Modules)\n\n  dhry.h\n  dhry_1.c\n  dhry_2.c\n  \nThe file RATIONALE contains the article \n\n  \"Dhrystone Benchmark: Rationale for Version 2 and Measurement Rules\"\n\nwhich has been published, together with the C source code (Version 2.0),\nin SIGPLAN Notices vol. 23, no. 8 (Aug. 1988), pp. 49-62.\nThis article explains all changes that have been made for Version 2,\ncompared with the version of the original publication\nin Communications of the ACM vol. 27, no. 10 (Oct. 1984), pp. 1013-1030.\nIt also contains \"ground rules\" for benchmarking with Dhrystone\nwhich should be followed by everyone who uses the program and publishes\nDhrystone results.\n\nCompared with the Version 2.0 published in SIGPLAN Notices, Version 2.1\ncontains a few corrections that have been made after Version 2.0 was\ndistriobuted over the UNIX network Usenet. These small differences between\nVersion 2.0 and 2.1 should not affect execution time measurements.\nFor those who want to compare the exact contents of both versions,\nthe file \"dhry_c.dif\" contains the differences between the two versions,\nas generated by a file comparison of the corresponding files with the\nUNIX utility \"diff\".\n\nThe file VARIATIONS contains the article\n\n  \"Understanding Variations in Dhrystone Performance\"\n\nwhich has been published in Microprocessor Report, May 1989\n(Editor: M. Slater), pp. 16-17. It describes the points that users\nshould know if C Dhrystone results are compared.\n\nRecipients of this shar file who perform measurements are asked\nto send measurement results to the author and/or to Rick Richardson.\nRick Richardson publishes regularly Dhrystone results on the UNIX network\nUsenet. For submissions of results to him (preferably by electronic mail,\nsee address in the program header), he has provided a form which is contained\nin the file \"submit.frm\".\n\n\nThe following files are contained in other \"shar\" files:\n\nFiles containing the Ada version (*.s: Specifications, *.b: Bodies):\n\n  d_global.s\n  d_main.b\n  d_pack_1.b\n  d_pack_1.s\n  d_pack_2.b\n  d_pack_2.s\n\nFile containing the Pascal version:\n\n  dhry.p\n\n\nFebruary 22, 1990\n\n                 Reinhold P. Weicker\n                 Siemens AG, AUT E 51\n                 Postfach 3220\n                 D-8520 Erlangen\n                 Germany (West)\n\n                 Phone:  [xxx-49]-9131-7-20330  (8-17 Central European Time)\n                 UUCP:   ..!mcsun!unido!estevax!weicker\n"
  },
  {
    "path": "share/examples/dhrystone/VARIATIONS",
    "content": "\n            Understanding Variations in Dhrystone Performance\n\n\n\n          By Reinhold P. Weicker, Siemens AG, AUT E 51, Erlangen\n\n\n\n                                April 1989\n\n\n                      This article has appeared in:\n\n\n        Microprocessor Report, May 1989 (Editor: M. Slater), pp. 16-17\n\n\n\n\nMicroprocessor manufacturers tend to credit all the  performance  measured  by\nbenchmarks to the speed of their processors, they often don't even mention the\nprogramming language and compiler used. In their detailed  documents,  usually\ncalled  \"performance brief\" or \"performance report,\" they usually do give more\ndetails. However, these details are often lost in the press releases and other\nmarketing  statements.  For serious performance evaluation, it is necessary to\nstudy the code generated by the various compilers.\n\nDhrystone was originally published in Ada (Communications  of  the  ACM,  Oct.\n1984).  However, since good Ada compilers were rare at this time and, together\nwith UNIX, C became more and more popular, the C version of Dhrystone  is  the\none  now  mainly  used in industry. There are \"official\" versions 2.1 for Ada,\nPascal, and C,  which  are  as  close  together  as  the  languages'  semantic\ndifferences permit.\n\nDhrystone contains two statements  where  the  programming  language  and  its\ntranslation play a major part in the execution time measured by the benchmark:\n\n  o   String assignment (in procedure Proc_0 / main)\n  o   String comparison (in function Func_2)\n\nIn Ada and Pascal, strings are arrays of characters where the  length  of  the\nstring  is  part  of the type information known at compile time. In C, strings\nare also arrays of characters, but there  are  no  operators  defined  in  the\nlanguage  for  assignment  and  comparison  of  strings.   Instead,  functions\n\"strcpy\" and \"strcmp\" are used. These functions are  defined  for  strings  of\narbitrary  length, and make use of the fact that strings in C have to end with\na terminating null byte. For general-purpose calls  to  these  functions,  the\nimplementor  can  assume  nothing  about  the  length and the alignment of the\nstrings involved.\n\nThe C version of Dhrystone spends a relatively large amount of time  in  these\ntwo  functions.  Some  time  ago, I made measurements on a VAX 11/785 with the\nBerkeley UNIX (4.2) compilers (often-used compilers,  but  certainly  not  the\nmost  advanced).  In  the  C  version, 23% of the time was spent in the string\nfunctions; in the Pascal version, only 10%. On good RISC machines (where  less\ntime is spent in the procedure calling sequence than on a VAX) and with better\noptimizing compilers, the percentage is higher; MIPS has reported 34%  for  an\nR3000.   Because  of this effect, Pascal and Ada Dhrystone results are usually\nbetter than C results (except when the optimization quality of the C  compiler\nis considerably better than that of the other compilers).\n\nSeveral people have noted that the string operations are  over-represented  in\nDhrystone,  mainly  because the strings occurring in Dhrystone are longer than\naverage strings. I admit that this is true, and have said  so  in  my  SIGPLAN\nNotices  paper  (Aug.  1988);  however, I didn't want to generate confusion by\nchanging the string lengths from version 1 to version 2.\n\nEven if they are somewhat over-represented in Dhrystone, string operations are\nfrequent  enough  that  it makes sense to implement them in the most efficient\nway possible, not only for benchmarking purposes.  This means  that  they  can\nand should be written in assembly language code. ANSI C also explicitly allows\nthe strings functions to be implemented as macros, i.e. by inline code.\n\nThere is also a third way to speed up the \"strcpy\" statement in Dhrystone: For\nthis  particular  \"strcpy\" statement, the source of the assignment is a string\nconstant. Therefore, in contrast to calls to \"strcpy\" in the general case, the\ncompiler  knows  the  length  and alignment of the strings involved at compile\ntime and can generate code in the same efficient  way  as  a  Pascal  compiler\n(word instructions instead of byte instructions).\n\nThis is not allowed in the case of the \"strcmp\" call: Here, the addresses  are\nformal  procedure  parameters, and no assumptions can be made about the length\nor alignment of the strings.  Any such assumptions would indicate an incorrect\nimplementation.  They  might work for Dhrystone, where the strings are in fact\nword-aligned  with  typical  compilers,  but  other  programs  would   deliver\nincorrect results.\n\nSo, for an apple-to-apple  comparison  between  processors,  and  not  between\nseveral  possible  (legal  or  illegal)  degrees of compiler optimization, one\nshould check that the systems are comparable with  respect  to  the  following\nthree points:\n\n  (1) String functions in assembly language vs. in C\n\n      Frequently used functions such as the string functions can and should be\n      written  in  assembly language, and all serious C language systems known\n      to me do this. (I list this point  for  completeness  only.)  Note  that\n      processors  with an instruction that checks a word for a null byte (such\n      as AMD's  29000  and  Intel's  80960)  have  an  advantage  here.  (This\n      advantage  decreases  relatively if optimization (3) is applied.) Due to\n      the length of the strings involved in Dhrystone, this advantage  may  be\n      considered  too  high  in  perspective, but it is certainly legal to use\n      such instructions - after all,  these  situations  are  what  they  were\n      invented for.\n\n  (2) String function code inline vs. as library functions.\n\n      ANSI  C  has  created  a  new  situation,  compared   with   the   older\n      Kernighan/Ritchie  C.  In  the  original C, the definition of the string\n      function was not part of the  language.  Now  it  is,  and  inlining  is\n      explicitly  allowed.  I  probably  should have stated more clearly in my\n      SIGPLAN  Notices  paper  that  the  rule  \"No  procedure  inlining   for\n      Dhrystone\"  referred  to  the  user level procedures only and not to the\n      library routines.\n\n  (3) Fixed-length and alignment assumptions for the strings\n\n      Compilers should be allowed to optimize in these cases if (and only  if)\n      it  is safe to do so. For Dhrystone, this is the \"strcpy\" statement, but\n      not the  \"strcmp\"  statement  (unless,  of  course,  the  \"strcmp\"  code\n      explicitly   checks   the  alignment  at  execution  time  and  branches\n      accordingly).  A \"Dhrystone switch\" for the  compiler  that  causes  the\n      generation  of  code  that  may  not work under certain circumstances is\n      certainly inappropriate for comparisons. It has been reported in  Usenet\n      that some C compilers provide such a compiler option; since I don't have\n      access to all C compilers involved, I cannot verify this.\n\n      If the fixed-length and word-alignment assumption can be  used,  a  wide\n      bus  that permits fast multi-word load instructions certainly does help;\n      however, this fact by itself should not make a really big difference.\n\nA check of  these  points  -  something  that  is  necessary  for  a  thorough\nevaluation  and  comparison  of  the  Dhrystone  performance claims - requires\nobject code listings as well as listings for  the  string  functions  (strcpy,\nstrcmp) that are possibly called by the program.\n\nI don't pretend that Dhrystone is  a  perfect  tool  to  measure  the  integer\nperformance  of microprocessors. The more it is used and discussed, the more I\nmyself learn about aspects that I hadn't noticed yet when I wrote the program.\nAnd  of  course,  the  very success of a benchmark program is a danger in that\npeople may tune their compilers and/or hardware to it, and  with  this  action\nmake it less useful.\n\nWhetstone and Linpack have their critical points also:  The  Whetstone  rating\ndepends  heavily on the speed of the mathematical functions (sine, sqrt, ...),\nand Linpack is sensitive to data alignment for some cache configurations.\n\nIntroduction of a standard set of public domain benchmark software  (something\nthe  SPEC  effort attempts) is certainly a worthwhile thing.  In the meantime,\npeople will continue to use whatever is available and widely distributed,  and\nDhrystone  ratings  are probably still better than MIPS ratings if these are -\nas often in industry - based on  no  reproducible  derivation.   However,  any\nserious  performance  evaluation  requires  more than just a comparison of raw\nnumbers; one has to make sure  that  the  numbers  have  been  obtained  in  a\ncomparable way.\n\n"
  },
  {
    "path": "share/examples/dhrystone/dhry.h",
    "content": "/*\n ****************************************************************************\n *\n *                   \"DHRYSTONE\" Benchmark Program\n *                   -----------------------------\n *\n *  Version:    C, Version 2.1\n *\n *  File:       dhry.h (part 1 of 3)\n *\n *  Date:       May 25, 1988\n *\n *  Author:     Reinhold P. Weicker\n *                      Siemens AG, AUT E 51\n *                      Postfach 3220\n *                      8520 Erlangen\n *                      Germany (West)\n *                              Phone:  [+49]-9131-7-20330\n *                                      (8-17 Central European Time)\n *                              Usenet: ..!mcsun!unido!estevax!weicker\n *\n *              Original Version (in Ada) published in\n *              \"Communications of the ACM\" vol. 27., no. 10 (Oct. 1984),\n *              pp. 1013 - 1030, together with the statistics\n *              on which the distribution of statements etc. is based.\n *\n *              In this C version, the following C library functions are used:\n *              - strcpy, strcmp (inside the measurement loop)\n *              - printf, scanf (outside the measurement loop)\n *              In addition, Berkeley UNIX system calls \"times ()\" or \"time ()\"\n *              are used for execution time measurement. For measurements\n *              on other systems, these calls have to be changed.\n *\n *  Collection of Results:\n *              Reinhold Weicker (address see above) and\n *\n *              Rick Richardson\n *              PC Research. Inc.\n *              94 Apple Orchard Drive\n *              Tinton Falls, NJ 07724\n *                      Phone:  (201) 389-8963 (9-17 EST)\n *                      Usenet: ...!uunet!pcrat!rick\n *\n *      Please send results to Rick Richardson and/or Reinhold Weicker.\n *      Complete information should be given on hardware and software used.\n *      Hardware information includes: Machine type, CPU, type and size\n *      of caches; for microprocessors: clock frequency, memory speed\n *      (number of wait states).\n *      Software information includes: Compiler (and runtime library)\n *      manufacturer and version, compilation switches, OS version.\n *      The Operating System version may give an indication about the\n *      compiler; Dhrystone itself performs no OS calls in the measurement loop.\n *\n *      The complete output generated by the program should be mailed\n *      such that at least some checks for correctness can be made.\n *\n ***************************************************************************\n *\n *  History:    This version C/2.1 has been made for two reasons:\n *\n *              1) There is an obvious need for a common C version of\n *              Dhrystone, since C is at present the most popular system\n *              programming language for the class of processors\n *              (microcomputers, minicomputers) where Dhrystone is used most.\n *              There should be, as far as possible, only one C version of\n *              Dhrystone such that results can be compared without\n *              restrictions. In the past, the C versions distributed\n *              by Rick Richardson (Version 1.1) and by Reinhold Weicker\n *              had small (though not significant) differences.\n *\n *              2) As far as it is possible without changes to the Dhrystone\n *              statistics, optimizing compilers should be prevented from\n *              removing significant statements.\n *\n *              This C version has been developed in cooperation with\n *              Rick Richardson (Tinton Falls, NJ), it incorporates many\n *              ideas from the \"Version 1.1\" distributed previously by\n *              him over the UNIX network Usenet.\n *              I also thank Chaim Benedelac (National Semiconductor),\n *              David Ditzel (SUN), Earl Killian and John Mashey (MIPS),\n *              Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley)\n *              for their help with comments on earlier versions of the\n *              benchmark.\n *\n *  Changes:    In the initialization part, this version follows mostly\n *              Rick Richardson's version distributed via Usenet, not the\n *              version distributed earlier via floppy disk by Reinhold Weicker.\n *              As a concession to older compilers, names have been made\n *              unique within the first 8 characters.\n *              Inside the measurement loop, this version follows the\n *              version previously distributed by Reinhold Weicker.\n *\n *              At several places in the benchmark, code has been added,\n *              but within the measurement loop only in branches that\n *              are not executed. The intention is that optimizing compilers\n *              should be prevented from moving code out of the measurement\n *              loop, or from removing code altogether. Since the statements\n *              that are executed within the measurement loop have NOT been\n *              changed, the numbers defining the \"Dhrystone distribution\"\n *              (distribution of statements, operand types and locality)\n *              still hold. Except for sophisticated optimizing compilers,\n *              execution times for this version should be the same as\n *              for previous versions.\n *\n *              Since it has proven difficult to subtract the time for the\n *              measurement loop overhead in a correct way, the loop check\n *              has been made a part of the benchmark. This does have\n *              an impact - though a very minor one - on the distribution\n *              statistics which have been updated for this version.\n *\n *              All changes within the measurement loop are described\n *              and discussed in the companion paper \"Rationale for\n *              Dhrystone version 2\".\n *\n *              Because of the self-imposed limitation that the order and\n *              distribution of the executed statements should not be\n *              changed, there are still cases where optimizing compilers\n *              may not generate code for some statements. To a certain\n *              degree, this is unavoidable for small synthetic benchmarks.\n *              Users of the benchmark are advised to check code listings\n *              whether code is generated for all statements of Dhrystone.\n *\n *              Version 2.1 is identical to version 2.0 distributed via\n *              the UNIX network Usenet in March 1988 except that it corrects\n *              some minor deficiencies that were found by users of version 2.0.\n *              The only change within the measurement loop is that a\n *              non-executed \"else\" part was added to the \"if\" statement in\n *              Func_3, and a non-executed \"else\" part removed from Proc_3.\n *\n ***************************************************************************\n *\n *  Compilation model and measurement (IMPORTANT):\n *\n *  This C version of Dhrystone consists of three files:\n *  - dhry.h (this file, containing global definitions and comments)\n *  - dhry_1.c (containing the code corresponding to Ada package Pack_1)\n *  - dhry_2.c (containing the code corresponding to Ada package Pack_2)\n *\n *  The following \"ground rules\" apply for measurements:\n *  - Separate compilation\n *  - No procedure merging\n *  - Otherwise, compiler optimizations are allowed but should be indicated\n *  - Default results are those without register declarations\n *  See the companion paper \"Rationale for Dhrystone Version 2\" for a more\n *  detailed discussion of these ground rules.\n *\n *  For 16-Bit processors (e.g. 80186, 80286), times for all compilation\n *  models (\"small\", \"medium\", \"large\" etc.) should be given if possible,\n *  together with a definition of these models for the compiler system used.\n *\n **************************************************************************\n *\n *  Dhrystone (C version) statistics:\n *\n *  [Comment from the first distribution, updated for version 2.\n *   Note that because of language differences, the numbers are slightly\n *   different from the Ada version.]\n *\n *  The following program contains statements of a high level programming\n *  language (here: C) in a distribution considered representative:\n *\n *    assignments                  52 (51.0 %)\n *    control statements           33 (32.4 %)\n *    procedure, function calls    17 (16.7 %)\n *\n *  103 statements are dynamically executed. The program is balanced with\n *  respect to the three aspects:\n *\n *    - statement type\n *    - operand type\n *    - operand locality\n *         operand global, local, parameter, or constant.\n *\n *  The combination of these three aspects is balanced only approximately.\n *\n *  1. Statement Type:\n *  -----------------             number\n *\n *     V1 = V2                     9\n *       (incl. V1 = F(..)\n *     V = Constant               12\n *     Assignment,                 7\n *       with array element\n *     Assignment,                 6\n *       with record component\n *                                --\n *                                34       34\n *\n *     X = Y +|-|\"&&\"|\"|\" Z        5\n *     X = Y +|-|\"==\" Constant     6\n *     X = X +|- 1                 3\n *     X = Y *|/ Z                 2\n *     X = Expression,             1\n *           two operators\n *     X = Expression,             1\n *           three operators\n *                                --\n *                                18       18\n *\n *     if ....                    14\n *       with \"else\"      7\n *       without \"else\"   7\n *           executed        3\n *           not executed    4\n *     for ...                     7  |  counted every time\n *     while ...                   4  |  the loop condition\n *     do ... while                1  |  is evaluated\n *     switch ...                  1\n *     break                       1\n *     declaration with            1\n *       initialization\n *                                --\n *                                34       34\n *\n *     P (...)  procedure call    11\n *       user procedure      10\n *       library procedure    1\n *     X = F (...)\n *             function  call      6\n *       user function        5\n *       library function     1\n *                                --\n *                                17       17\n *                                        ---\n *                                        103\n *\n *    The average number of parameters in procedure or function calls\n *    is 1.82 (not counting the function values as implicit parameters).\n *\n *\n *  2. Operators\n *  ------------\n *                          number    approximate\n *                                    percentage\n *\n *    Arithmetic             32          50.8\n *\n *       +                     21          33.3\n *       -                      7          11.1\n *       *                      3           4.8\n *       / (int div)            1           1.6\n *\n *    Comparison             27           42.8\n *\n *       ==                     9           14.3\n *       /=                     4            6.3\n *       >                      1            1.6\n *       <                      3            4.8\n *       >=                     1            1.6\n *       <=                     9           14.3\n *\n *    Logic                   4            6.3\n *\n *       && (AND-THEN)          1            1.6\n *       |  (OR)                1            1.6\n *       !  (NOT)               2            3.2\n *\n *                           --          -----\n *                           63          100.1\n *\n *\n *  3. Operand Type (counted once per operand reference):\n *  ---------------\n *                          number    approximate\n *                                    percentage\n *\n *     Integer               175        72.3 %\n *     Character              45        18.6 %\n *     Pointer                12         5.0 %\n *     String30                6         2.5 %\n *     Array                   2         0.8 %\n *     Record                  2         0.8 %\n *                           ---       -------\n *                           242       100.0 %\n *\n *  When there is an access path leading to the final operand (e.g. a record\n *  component), only the final data type on the access path is counted.\n *\n *\n *  4. Operand Locality:\n *  -------------------\n *                                number    approximate\n *                                          percentage\n *\n *     local variable              114        47.1 %\n *     global variable              22         9.1 %\n *     parameter                    45        18.6 %\n *        value                        23         9.5 %\n *        reference                    22         9.1 %\n *     function result               6         2.5 %\n *     constant                     55        22.7 %\n *                                 ---       -------\n *                                 242       100.0 %\n *\n *\n *  The program does not compute anything meaningful, but it is syntactically\n *  and semantically correct. All variables have a value assigned to them\n *  before they are used as a source operand.\n *\n *  There has been no explicit effort to account for the effects of a\n *  cache, or to balance the use of long or short displacements for code or\n *  data.\n *\n ***************************************************************************\n */\n\n/* Compiler and system dependent definitions: */\n\ntypedef enum {\n    Ident_1,\n    Ident_2,\n    Ident_3,\n    Ident_4,\n    Ident_5\n} Enumeration;\n\n\n/* General definitions: */\n\n#define true  1\n#define false 0\n\ntypedef int     One_Thirty;\ntypedef int     One_Fifty;\ntypedef char    Capital_Letter;\ntypedef int     Boolean;\ntypedef char    Str_30 [31];\ntypedef int     Arr_1_Dim [50];\ntypedef int     Arr_2_Dim [50] [50];\n\ntypedef struct record\n    {\n    struct record *Ptr_Comp;\n    Enumeration    Discr;\n    union {\n          struct {\n                  Enumeration Enum_Comp;\n                  int         Int_Comp;\n                  char        Str_Comp [31];\n                  } var_1;\n          struct {\n                  Enumeration E_Comp_2;\n                  char        Str_2_Comp [31];\n                  } var_2;\n          struct {\n                  char        Ch_1_Comp;\n                  char        Ch_2_Comp;\n                  } var_3;\n          } variant;\n      } Rec_Type, *Rec_Pointer;\n\n\n/* Forward declaration necessary since Enumeration may not simply be int */\nvoid            Proc_1 (Rec_Pointer);\nvoid            Proc_2 (One_Fifty *);\nvoid            Proc_3 (Rec_Pointer *);\nvoid            Proc_4 (void);\nvoid            Proc_5 (void);\nvoid            Proc_6 (Enumeration, Enumeration *);\nvoid            Proc_7 (One_Fifty, One_Fifty, One_Fifty *);\nvoid            Proc_8 (Arr_1_Dim, Arr_2_Dim, int, int);\nEnumeration     Func_1 (Capital_Letter, Capital_Letter);\nBoolean         Func_2 (Str_30, Str_30);\nBoolean         Func_3 (Enumeration);\n"
  },
  {
    "path": "share/examples/dhrystone/dhry_1.c",
    "content": "/*\n ****************************************************************************\n *\n *                   \"DHRYSTONE\" Benchmark Program\n *                   -----------------------------\n *\n *  Version:    C, Version 2.1\n *\n *  File:       dhry_1.c (part 2 of 3)\n *\n *  Date:       May 25, 1988\n *\n *  Author:     Reinhold P. Weicker\n *\n ****************************************************************************\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <sys/time.h>\n#include \"dhry.h\"\n\n/* Speed of Vak-11/780, 1 DMIPS by definition */\n\n#define DHRYSTONES_PER_DMIPS 1757\n\n/* Global Variables: */\n\nRec_Pointer     Ptr_Glob,\n                Next_Ptr_Glob;\nint             Int_Glob;\nBoolean         Bool_Glob;\nchar            Ch_1_Glob,\n                Ch_2_Glob;\nint             Arr_1_Glob [50];\nint             Arr_2_Glob [50] [50];\n\n/* variables for time measurement: */\n\nstruct timeval  time_info;\n\nlong            Begin_Time,\n                End_Time,\n                Microseconds,\n                Dhrystones_per_Millisecond,\n                Dmips;\n\n/* end of variables for time measurement */\n\n\nint main ()\n/*****/\n\n  /* main program, corresponds to procedures        */\n  /* Main and Proc_0 in the Ada version             */\n{\n  One_Fifty       Int_1_Loc;\n  One_Fifty       Int_2_Loc;\n  One_Fifty       Int_3_Loc;\n  char            Ch_Index;\n  Enumeration     Enum_Loc;\n  Str_30          Str_1_Loc;\n  Str_30          Str_2_Loc;\n  int             Run_Index;\n  int             Number_Of_Runs = 1000000;\n\n  /* Initializations */\n\n  Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));\n  Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));\n\n  Ptr_Glob->Ptr_Comp                    = Next_Ptr_Glob;\n  Ptr_Glob->Discr                       = Ident_1;\n  Ptr_Glob->variant.var_1.Enum_Comp     = Ident_3;\n  Ptr_Glob->variant.var_1.Int_Comp      = 40;\n  strcpy (Ptr_Glob->variant.var_1.Str_Comp,\n          \"DHRYSTONE PROGRAM, SOME STRING\");\n  strcpy (Str_1_Loc, \"DHRYSTONE PROGRAM, 1'ST STRING\");\n\n  Arr_2_Glob [8][7] = 10;\n        /* Was missing in published program. Without this statement,    */\n        /* Arr_2_Glob [8][7] would have an undefined value.             */\n        /* Warning: With 16-Bit processors and Number_Of_Runs > 32000,  */\n        /* overflow may occur for this array element.                   */\n\n  printf (\"\\n\");\n  printf (\"Dhrystone Benchmark, Version 2.1 (Language: C)\\n\");\n  printf (\"\\n\");\n\nagain:\n  printf (\"Execution starts, %d runs through Dhrystone\\n\", Number_Of_Runs);\n\n  /***************/\n  /* Start timer */\n  /***************/\n\n  gettimeofday(&time_info, 0);\n  Begin_Time = time_info.tv_sec * 1000000L + time_info.tv_usec;\n\n  for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index)\n  {\n\n    Proc_5();\n    Proc_4();\n      /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */\n    Int_1_Loc = 2;\n    Int_2_Loc = 3;\n    strcpy (Str_2_Loc, \"DHRYSTONE PROGRAM, 2'ND STRING\");\n    Enum_Loc = Ident_2;\n    Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc);\n      /* Bool_Glob == 1 */\n    while (Int_1_Loc < Int_2_Loc)  /* loop body executed once */\n    {\n      Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc;\n        /* Int_3_Loc == 7 */\n      Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc);\n        /* Int_3_Loc == 7 */\n      Int_1_Loc += 1;\n    } /* while */\n      /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */\n    Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc);\n      /* Int_Glob == 5 */\n    Proc_1 (Ptr_Glob);\n    for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index)\n                             /* loop body executed twice */\n    {\n      if (Enum_Loc == Func_1 (Ch_Index, 'C'))\n          /* then, not executed */\n        {\n        Proc_6 (Ident_1, &Enum_Loc);\n        strcpy (Str_2_Loc, \"DHRYSTONE PROGRAM, 3'RD STRING\");\n        Int_2_Loc = Run_Index;\n        Int_Glob = Run_Index;\n        }\n    }\n      /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */\n    Int_2_Loc = Int_2_Loc * Int_1_Loc;\n    Int_1_Loc = Int_2_Loc / Int_3_Loc;\n    Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc;\n      /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */\n    Proc_2 (&Int_1_Loc);\n      /* Int_1_Loc == 5 */\n\n  } /* loop \"for Run_Index\" */\n\n  /**************/\n  /* Stop timer */\n  /**************/\n\n  gettimeofday(&time_info, 0);\n  End_Time = time_info.tv_sec * 1000000L + time_info.tv_usec;\n\n  /* Measurements should last at least 2 seconds */\n  Microseconds = End_Time - Begin_Time;\n  if (Microseconds < 2000000)\n  {\n    printf (\"Measured time too small to obtain meaningful results\\n\");\n    printf (\"Increasing the number of runs\\n\");\n    printf (\"\\n\");\n    Number_Of_Runs *= 10;\n    goto again;\n  }\n\n  printf (\"Execution ends\\n\");\n  printf (\"\\n\");\n  printf (\"Final values of the variables used in the benchmark:\\n\");\n  printf (\"\\n\");\n  printf (\"Int_Glob:            %d\\n\", Int_Glob);\n  printf (\"        should be:   %d\\n\", 5);\n  printf (\"Bool_Glob:           %d\\n\", Bool_Glob);\n  printf (\"        should be:   %d\\n\", 1);\n  printf (\"Ch_1_Glob:           %c\\n\", Ch_1_Glob);\n  printf (\"        should be:   %c\\n\", 'A');\n  printf (\"Ch_2_Glob:           %c\\n\", Ch_2_Glob);\n  printf (\"        should be:   %c\\n\", 'B');\n  printf (\"Arr_1_Glob[8]:       %d\\n\", Arr_1_Glob[8]);\n  printf (\"        should be:   %d\\n\", 7);\n  printf (\"Arr_2_Glob[8][7]:    %d\\n\", Arr_2_Glob[8][7]);\n  printf (\"        should be:   Number_Of_Runs + 10\\n\");\n  printf (\"Ptr_Glob->\\n\");\n  printf (\"  Ptr_Comp:          %p\\n\", Ptr_Glob->Ptr_Comp);\n  printf (\"        should be:   (implementation-dependent)\\n\");\n  printf (\"  Discr:             %d\\n\", Ptr_Glob->Discr);\n  printf (\"        should be:   %d\\n\", 0);\n  printf (\"  Enum_Comp:         %d\\n\", Ptr_Glob->variant.var_1.Enum_Comp);\n  printf (\"        should be:   %d\\n\", 2);\n  printf (\"  Int_Comp:          %d\\n\", Ptr_Glob->variant.var_1.Int_Comp);\n  printf (\"        should be:   %d\\n\", 17);\n  printf (\"  Str_Comp:          %s\\n\", Ptr_Glob->variant.var_1.Str_Comp);\n  printf (\"        should be:   DHRYSTONE PROGRAM, SOME STRING\\n\");\n  printf (\"Next_Ptr_Glob->\\n\");\n  printf (\"  Ptr_Comp:          %p\\n\", Next_Ptr_Glob->Ptr_Comp);\n  printf (\"        should be:   (implementation-dependent), same as above\\n\");\n  printf (\"  Discr:             %d\\n\", Next_Ptr_Glob->Discr);\n  printf (\"        should be:   %d\\n\", 0);\n  printf (\"  Enum_Comp:         %d\\n\", Next_Ptr_Glob->variant.var_1.Enum_Comp);\n  printf (\"        should be:   %d\\n\", 1);\n  printf (\"  Int_Comp:          %d\\n\", Next_Ptr_Glob->variant.var_1.Int_Comp);\n  printf (\"        should be:   %d\\n\", 18);\n  printf (\"  Str_Comp:          %s\\n\",\n                                Next_Ptr_Glob->variant.var_1.Str_Comp);\n  printf (\"        should be:   DHRYSTONE PROGRAM, SOME STRING\\n\");\n  printf (\"Int_1_Loc:           %d\\n\", Int_1_Loc);\n  printf (\"        should be:   %d\\n\", 5);\n  printf (\"Int_2_Loc:           %d\\n\", Int_2_Loc);\n  printf (\"        should be:   %d\\n\", 13);\n  printf (\"Int_3_Loc:           %d\\n\", Int_3_Loc);\n  printf (\"        should be:   %d\\n\", 7);\n  printf (\"Enum_Loc:            %d\\n\", Enum_Loc);\n  printf (\"        should be:   %d\\n\", 1);\n  printf (\"Str_1_Loc:           %s\\n\", Str_1_Loc);\n  printf (\"        should be:   DHRYSTONE PROGRAM, 1'ST STRING\\n\");\n  printf (\"Str_2_Loc:           %s\\n\", Str_2_Loc);\n  printf (\"        should be:   DHRYSTONE PROGRAM, 2'ND STRING\\n\");\n  printf (\"\\n\");\n\n  /* Dhrystones per 10^-5 sec. */\n  Dhrystones_per_Millisecond = Number_Of_Runs / (Microseconds / 1000);\n\n  Dmips = Dhrystones_per_Millisecond * 10000 / DHRYSTONES_PER_DMIPS;\n\n  printf (\"Nanoseconds for one run through Dhrystone: %lu \\n\",\n          Microseconds / (Number_Of_Runs / 1000));\n  printf (\"            Million Dhrystones per Second: %lu.%03lu \\n\",\n          Dhrystones_per_Millisecond / 1000, Dhrystones_per_Millisecond % 1000);\n  printf (\"                                    DMIPS: %lu.%lu \\n\",\n          Dmips / 10, Dmips % 10);\n  printf (\"\\n\");\n\n  return 0;\n}\n\n\nvoid Proc_1 (Rec_Pointer Ptr_Val_Par)\n/******************/\n    /* executed once */\n{\n  Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp;\n                                        /* == Ptr_Glob_Next */\n  /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp,    */\n  /* corresponds to \"rename\" in Ada, \"with\" in Pascal           */\n\n  *Ptr_Val_Par->Ptr_Comp = *Ptr_Glob;\n  Ptr_Val_Par->variant.var_1.Int_Comp = 5;\n  Next_Record->variant.var_1.Int_Comp\n        = Ptr_Val_Par->variant.var_1.Int_Comp;\n  Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp;\n  Proc_3 (&Next_Record->Ptr_Comp);\n    /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp\n                        == Ptr_Glob->Ptr_Comp */\n  if (Next_Record->Discr == Ident_1)\n    /* then, executed */\n  {\n    Next_Record->variant.var_1.Int_Comp = 6;\n    Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp,\n           &Next_Record->variant.var_1.Enum_Comp);\n    Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp;\n    Proc_7 (Next_Record->variant.var_1.Int_Comp, 10,\n           &Next_Record->variant.var_1.Int_Comp);\n  }\n  else /* not executed */\n    *Ptr_Val_Par = *Ptr_Val_Par->Ptr_Comp;\n} /* Proc_1 */\n\n\nvoid Proc_2 (One_Fifty *Int_Par_Ref)\n/******************/\n    /* executed once */\n    /* *Int_Par_Ref == 1, becomes 4 */\n{\n  One_Fifty   Int_Loc;\n  Enumeration Enum_Loc;\n\n  Int_Loc = *Int_Par_Ref + 10;\n  do /* executed once */\n    if (Ch_1_Glob == 'A')\n      /* then, executed */\n    {\n      Int_Loc -= 1;\n      *Int_Par_Ref = Int_Loc - Int_Glob;\n      Enum_Loc = Ident_1;\n    } /* if */\n  while (Enum_Loc != Ident_1); /* true */\n} /* Proc_2 */\n\n\nvoid Proc_3 (Rec_Pointer *Ptr_Ref_Par)\n/******************/\n    /* executed once */\n    /* Ptr_Ref_Par becomes Ptr_Glob */\n{\n  if (Ptr_Glob != 0)\n    /* then, executed */\n    *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp;\n  Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp);\n} /* Proc_3 */\n\n\nvoid Proc_4 () /* without parameters */\n/*******/\n    /* executed once */\n{\n  Boolean Bool_Loc;\n\n  Bool_Loc = Ch_1_Glob == 'A';\n  Bool_Glob = Bool_Loc | Bool_Glob;\n  Ch_2_Glob = 'B';\n} /* Proc_4 */\n\n\nvoid Proc_5 () /* without parameters */\n/*******/\n    /* executed once */\n{\n  Ch_1_Glob = 'A';\n  Bool_Glob = false;\n} /* Proc_5 */\n"
  },
  {
    "path": "share/examples/dhrystone/dhry_2.c",
    "content": "/*\n ****************************************************************************\n *\n *                   \"DHRYSTONE\" Benchmark Program\n *                   -----------------------------\n *\n *  Version:    C, Version 2.1\n *\n *  File:       dhry_2.c (part 3 of 3)\n *\n *  Date:       May 25, 1988\n *\n *  Author:     Reinhold P. Weicker\n *\n ****************************************************************************\n */\n\n#include <string.h>\n#include \"dhry.h\"\n\nextern  int     Int_Glob;\nextern  char    Ch_1_Glob;\n\n\nvoid Proc_6 (Enumeration Enum_Val_Par,\n             Enumeration *Enum_Ref_Par)\n/*********************************/\n    /* executed once */\n    /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */\n{\n  *Enum_Ref_Par = Enum_Val_Par;\n  if (! Func_3 (Enum_Val_Par))\n    /* then, not executed */\n    *Enum_Ref_Par = Ident_4;\n  switch (Enum_Val_Par)\n  {\n    case Ident_1:\n      *Enum_Ref_Par = Ident_1;\n      break;\n    case Ident_2:\n      if (Int_Glob > 100)\n        /* then */\n      *Enum_Ref_Par = Ident_1;\n      else *Enum_Ref_Par = Ident_4;\n      break;\n    case Ident_3: /* executed */\n      *Enum_Ref_Par = Ident_2;\n      break;\n    case Ident_4: break;\n    case Ident_5:\n      *Enum_Ref_Par = Ident_3;\n      break;\n  } /* switch */\n} /* Proc_6 */\n\n\nvoid Proc_7 (One_Fifty Int_1_Par_Val,\n             One_Fifty Int_2_Par_Val,\n             One_Fifty *Int_Par_Ref)\n/**********************************************/\n    /* executed three times                                      */\n    /* first call:      Int_1_Par_Val == 2, Int_2_Par_Val == 3,  */\n    /*                  Int_Par_Ref becomes 7                    */\n    /* second call:     Int_1_Par_Val == 10, Int_2_Par_Val == 5, */\n    /*                  Int_Par_Ref becomes 17                   */\n    /* third call:      Int_1_Par_Val == 6, Int_2_Par_Val == 10, */\n    /*                  Int_Par_Ref becomes 18                   */\n{\n  One_Fifty Int_Loc;\n\n  Int_Loc = Int_1_Par_Val + 2;\n  *Int_Par_Ref = Int_2_Par_Val + Int_Loc;\n} /* Proc_7 */\n\n\nvoid Proc_8 (Arr_1_Dim Arr_1_Par_Ref,\n             Arr_2_Dim Arr_2_Par_Ref,\n             int Int_1_Par_Val,\n             int Int_2_Par_Val)\n/*********************************************************************/\n    /* executed once      */\n    /* Int_Par_Val_1 == 3 */\n    /* Int_Par_Val_2 == 7 */\n{\n  One_Fifty Int_Index;\n  One_Fifty Int_Loc;\n\n  Int_Loc = Int_1_Par_Val + 5;\n  Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val;\n  Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc];\n  Arr_1_Par_Ref [Int_Loc+30] = Int_Loc;\n  for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index)\n    Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc;\n  Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1;\n  Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc];\n  Int_Glob = 5;\n} /* Proc_8 */\n\n\nEnumeration Func_1 (Capital_Letter Ch_1_Par_Val,\n                    Capital_Letter Ch_2_Par_Val)\n/*************************************************/\n    /* executed three times                                         */\n    /* first call:      Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R'    */\n    /* second call:     Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C'    */\n    /* third call:      Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C'    */\n{\n  Capital_Letter        Ch_1_Loc;\n  Capital_Letter        Ch_2_Loc;\n\n  Ch_1_Loc = Ch_1_Par_Val;\n  Ch_2_Loc = Ch_1_Loc;\n  if (Ch_2_Loc != Ch_2_Par_Val)\n    /* then, executed */\n    return (Ident_1);\n  else  /* not executed */\n  {\n    Ch_1_Glob = Ch_1_Loc;\n    return (Ident_2);\n   }\n} /* Func_1 */\n\n\nBoolean Func_2 (Str_30 Str_1_Par_Ref,\n                Str_30 Str_2_Par_Ref)\n/*************************************************/\n    /* executed once */\n    /* Str_1_Par_Ref == \"DHRYSTONE PROGRAM, 1'ST STRING\" */\n    /* Str_2_Par_Ref == \"DHRYSTONE PROGRAM, 2'ND STRING\" */\n{\n  One_Thirty        Int_Loc;\n  Capital_Letter    Ch_Loc;\n\n  Int_Loc = 2;\n  while (Int_Loc <= 2) /* loop body executed once */\n    if (Func_1 (Str_1_Par_Ref[Int_Loc],\n                Str_2_Par_Ref[Int_Loc+1]) == Ident_1)\n      /* then, executed */\n    {\n      Ch_Loc = 'A';\n      Int_Loc += 1;\n    } /* if, while */\n  if (Ch_Loc >= 'W' && Ch_Loc < 'Z')\n    /* then, not executed */\n    Int_Loc = 7;\n  if (Ch_Loc == 'R')\n    /* then, not executed */\n    return (true);\n  else /* executed */\n  {\n    if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0)\n      /* then, not executed */\n    {\n      Int_Loc += 7;\n      Int_Glob = Int_Loc;\n      return (true);\n    }\n    else /* executed */\n      return (false);\n  } /* if Ch_Loc */\n} /* Func_2 */\n\n\nBoolean Func_3 (Enumeration Enum_Par_Val)\n/***************************/\n    /* executed once        */\n    /* Enum_Par_Val == Ident_3 */\n{\n  Enumeration Enum_Loc;\n\n  Enum_Loc = Enum_Par_Val;\n  if (Enum_Loc == Ident_3)\n    /* then, executed */\n    return (true);\n  else /* not executed */\n    return (false);\n} /* Func_3 */\n"
  },
  {
    "path": "share/examples/forth/fact.fth",
    "content": "\\ Iterative factorial function.\n\n.\" Defining fact function ... \"\n: fact  ( n -- n! )\n\tdup 2 < if drop 1 else\n\tdup begin 1- swap over * swap dup 1 = until\n\tdrop then\n; .\" done.\" cr\n\n.\" 1! = \"  1  fact . cr\n.\" 2! = \"  2  fact . cr\n.\" 3! = \"  3  fact . cr\n.\" 4! = \"  4  fact . cr\n.\" 5! = \"  5  fact . cr\n.\" 6! = \"  6  fact . cr\n.\" 7! = \"  7  fact . cr\n.\" 8! = \"  8  fact . cr\n.\" 9! = \"  9  fact . cr\n.\" 10! = \" 10 fact . cr\n.\" 11! = \" 11 fact . cr\n.\" 12! = \" 12 fact . cr\n\nhalt\n"
  },
  {
    "path": "share/examples/gpanel/Makefile",
    "content": "CC      = cc\nLIBS    = -lgpanel\nPROG    = tft tftetris pixel line rect fill circle font color speed flappy\n\nFONTS   = 5x7.o 6x9.o digits20.o digits32.o lucidasans11.o lucidasans15.o \\\n          lucidasans28.o lucidasans7.o lucidasans9.o verdana7.o\n\nall:    $(PROG)\n\nclean:\n\trm -f *.o *~ $(PROG)\n\ntft:\ttft.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $?\n\ntftetris: tftetris.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $?\n\npixel:  pixel.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $? $(LIBS)\n\nline:   line.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $? $(LIBS)\n\nrect:   rect.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $? $(LIBS)\n\nfill:   fill.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $? $(LIBS)\n\ncircle: circle.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $? $(LIBS)\n\ncolor:  color.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) $? $(LIBS)\n\nspeed:  speed.c lucidasans15.o\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) speed.c lucidasans15.o $(LIBS)\n\nflappy: flappy.c lucidasans15.o lucidasans28.o\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) flappy.c lucidasans15.o lucidasans28.o $(LIBS)\n\nfont:   font.c $(FONTS)\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) font.c $(FONTS) $(LIBS)\n\n5x7.o:  fonts/5x7.c\n\t$(CC) $(CFLAGS) -o $@ -c $?\n\n6x9.o:  fonts/6x9.c\n\t$(CC) $(CFLAGS) -o $@ -c $?\n\ndigits20.o: fonts/digits20.c\n\t$(CC) $(CFLAGS) -o $@ -c $?\n\ndigits32.o: fonts/digits32.c\n\t$(CC) $(CFLAGS) -o $@ -c $?\n\nlucidasans11.o: fonts/lucidasans11.c\n\t$(CC) $(CFLAGS) -o $@ -c $?\n\nlucidasans15.o: fonts/lucidasans15.c\n\t$(CC) $(CFLAGS) -o $@ -c $?\n\nlucidasans28.o: fonts/lucidasans28.c\n\t$(CC) $(CFLAGS) -o $@ -c $?\n\nlucidasans7.o: fonts/lucidasans7.c\n\t$(CC) $(CFLAGS) -o $@ -c $?\n\nlucidasans9.o: fonts/lucidasans9.c\n\t$(CC) $(CFLAGS) -o $@ -c $?\n\nverdana7.o: fonts/verdana7.c\n\t$(CC) $(CFLAGS) -o $@ -c $?\n"
  },
  {
    "path": "share/examples/gpanel/circle.c",
    "content": "/*\n * Draw random circles.\n */\n#include <stdio.h>\n#include <sys/gpanel.h>\n\nint xsize, ysize;\n\nint main()\n{\n    char *devname = \"/dev/tft0\";\n    int x, y, r, color;\n\n    if (gpanel_open(devname) < 0) {\n        printf(\"Cannot open %s\\n\", devname);\n        exit(-1);\n    }\n    gpanel_clear(0, &xsize, &ysize);\n    printf(\"Screen size %u x %u.\\n\", xsize, ysize);\n\n    srand(time(0));\n    printf(\"Draw random circles.\\n\");\n    printf(\"Press ^C to stop.\\n\");\n\n    for (;;) {\n        x = rand() % xsize;\n        y = rand() % ysize;\n        r = rand() % ysize;\n        color = rand() << 1;\n        gpanel_circle(color, x, y, r);\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/gpanel/color.c",
    "content": "/*\n * Display a color palette.\n * Assume RGB 5-6-5 color format.\n * Color is a 16-bit value: rrrrrggggggbbbbb, where rrrrr,\n * gggggg and bbbbb are red, green and blue components.\n */\n#include <stdio.h>\n#include <sys/gpanel.h>\n\nint xsize, ysize;\n\nint scale_red(int x, int y)\n{\n    int r;\n\n    r = 32 * y * (xsize-x-1) / xsize / ysize;\n    if (r > 31)\n        r = 31;\n    return r;\n}\n\nint scale_green(int x, int y)\n{\n    int g;\n\n    g = 64 * x / xsize;\n    if (g > 63)\n        g = 63;\n    return g;\n}\n\nint scale_blue(int x, int y)\n{\n    int b;\n\n    b = 32 * (ysize-y-1) * (xsize-x-1) / xsize / ysize;\n    if (b > 31)\n        b = 31;\n    return b;\n}\n\nint main()\n{\n    char *devname = \"/dev/tft0\";\n    int x, y, r, g, b, color;\n\n    if (gpanel_open(devname) < 0) {\n        printf(\"Cannot open %s\\n\", devname);\n        exit(-1);\n    }\n    gpanel_clear(0, &xsize, &ysize);\n    printf(\"Screen size %u x %u.\\n\", xsize, ysize);\n\n    printf(\"Display color palette.\\n\");\n    for (y=0; y<ysize; y++) {\n        for (x=0; x<xsize; x++) {\n            r = scale_red(x, y);\n            g = scale_green(x, y);\n            b = scale_blue(x, y);\n            color = r << 11 | g << 5 | b;\n            gpanel_pixel(color, x, y);\n        }\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/gpanel/fill.c",
    "content": "/*\n * Draw random filled rectangles.\n */\n#include <stdio.h>\n#include <sys/gpanel.h>\n\nint xsize, ysize;\n\nint main()\n{\n    char *devname = \"/dev/tft0\";\n    int x0, y0, x1, y1, color;\n\n    if (gpanel_open(devname) < 0) {\n        printf(\"Cannot open %s\\n\", devname);\n        exit(-1);\n    }\n    gpanel_clear(0, &xsize, &ysize);\n    printf(\"Screen size %u x %u.\\n\", xsize, ysize);\n\n    srand(time(0));\n    printf(\"Draw random filled rectangles.\\n\");\n    printf(\"Press ^C to stop.\\n\");\n\n    for (;;) {\n        x0 = rand() % xsize;\n        y0 = rand() % ysize;\n        x1 = rand() % xsize;\n        y1 = rand() % ysize;\n        color = rand() << 1;\n        gpanel_fill(color, x0, y0, x1, y1);\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/gpanel/flappy.c",
    "content": "#include <stdlib.h>\n#include <stdio.h>\n#include <signal.h>\n#include <string.h>\n#include <unistd.h>\n#include <fcntl.h>\n#include <sgtty.h>\n#include <sys/time.h>\n#include <sys/gpanel.h>\n\n/*\n * Assign human-readable names to some common 16-bit color values:\n */\n#define\tBLACK   0x0000\n#define\tBLUE    0x002F\n#define\tRED     0xF800\n#define\tGREEN   0x07E0\n#define CYAN    0x07FF\n#define MAGENTA 0xF81F\n#define YELLOW  0xFFE0\n#define WHITE   0xFFFF\n\n/*\n * Redraw every 50 msec\n */\n#define DRAW_LOOP_INTERVAL  50\n\n/*\n * File name for saving the high score.\n */\n#define SCORE_FILENAME      \"flappy.score\"\n\n/*\n * Data from external font files.\n */\nextern const struct gpanel_font_t font_lucidasans15;\nextern const struct gpanel_font_t font_lucidasans28;\n\nint wing;\nint fx, fy, fall_rate;\nint pillar_pos, gap_pos;\nint score;\nint high_score = 0;\nint running = 0;\nint crashed = 0;\nint scr_press = 0;\ntime_t next_draw_time;\n\nvoid rect(int color, int x, int y, int w, int h)\n{\n    gpanel_rect(color, x, y, x+w-1, y+h-1);\n}\n\nvoid fill(int color, int x, int y, int w, int h)\n{\n    gpanel_fill(color, x, y, x+w-1, y+h-1);\n}\n\nvoid draw_pillar(int x, int gap)\n{\n    if (x >= 320)\n        return;\n\n    fill(GREEN, x+2, 2,      46, gap-4);\n    fill(GREEN, x+2, gap+92, 46, 136-gap);\n\n    rect(BLACK, x,   0,      50, gap);\n    rect(BLACK, x+1, 1,      48, gap-2);\n    rect(BLACK, x,   gap+90, 50, 140-gap);\n    rect(BLACK, x+1, gap+91, 48, 138-gap);\n}\n\nvoid clear_pillar(int x, int gap)\n{\n    if (x >= 320)\n        return;\n\n    /* \"Cheat\" slightly and just clear the right hand pixels\n     * to help minimise flicker, the rest will be overdrawn. */\n    fill(BLUE, x+45, 0,      5, gap);\n    fill(BLUE, x+45, gap+90, 5, 140-gap);\n}\n\nvoid clear_flappy(int x, int y)\n{\n    fill(BLUE, x, y, 34, 24);\n}\n\nvoid draw_flappy(int x, int y)\n{\n    /* Upper & lower body */\n    fill(BLACK, x+2,  y+8,  2,  10);\n    fill(BLACK, x+4,  y+6,  2,  2);\n    fill(BLACK, x+6,  y+4,  2,  2);\n    fill(BLACK, x+8,  y+2,  4,  2);\n    fill(BLACK, x+12, y,    12, 2);\n    fill(BLACK, x+24, y+2,  2,  2);\n    fill(BLACK, x+26, y+4,  2,  2);\n    fill(BLACK, x+28, y+6,  2,  6);\n    fill(BLACK, x+10, y+22, 10, 2);\n    fill(BLACK, x+4,  y+18, 2,  2);\n    fill(BLACK, x+6,  y+20, 4,  2);\n\n    /* Body fill */\n    fill(YELLOW, x+12, y+2,  6,  2);\n    fill(YELLOW, x+8,  y+4,  8,  2);\n    fill(YELLOW, x+6,  y+6,  10, 2);\n    fill(YELLOW, x+4,  y+8,  12, 2);\n    fill(YELLOW, x+4,  y+10, 14, 2);\n    fill(YELLOW, x+4,  y+12, 16, 2);\n    fill(YELLOW, x+4,  y+14, 14, 2);\n    fill(YELLOW, x+4,  y+16, 12, 2);\n    fill(YELLOW, x+6,  y+18, 12, 2);\n    fill(YELLOW, x+10, y+20, 10, 2);\n\n    /* Eye */\n    fill(BLACK, x+18, y+2,  2, 2);\n    fill(BLACK, x+16, y+4,  2, 6);\n    fill(BLACK, x+18, y+10, 2, 2);\n    fill(WHITE, x+18, y+4,  2, 6);\n    fill(WHITE, x+20, y+2,  4, 10);\n    fill(WHITE, x+24, y+4,  2, 8);\n    fill(WHITE, x+26, y+6,  2, 6);\n    fill(BLACK, x+24, y+6,  2, 4);\n\n    /* Beak */\n    fill(BLACK, x+20, y+12, 12, 2);\n    fill(BLACK, x+18, y+14, 2,  2);\n    fill(RED,   x+20, y+14, 12, 2);\n    fill(BLACK, x+32, y+14, 2,  2);\n    fill(BLACK, x+16, y+16, 2,  2);\n    fill(RED,   x+18, y+16, 2,  2);\n    fill(BLACK, x+20, y+16, 12, 2);\n    fill(BLACK, x+18, y+18, 2,  2);\n    fill(RED,   x+20, y+18, 10, 2);\n    fill(BLACK, x+30, y+18, 2,  2);\n    fill(BLACK, x+20, y+20, 10, 2);\n}\n\n/*\n * Wing down.\n */\nvoid draw_wing1(int x, int y)\n{\n    fill(BLACK, x,    y+14, 2,  6);\n    fill(BLACK, x+2,  y+20, 8,  2);\n    fill(BLACK, x+2,  y+12, 10, 2);\n    fill(BLACK, x+12, y+14, 2,  2);\n    fill(BLACK, x+10, y+16, 2,  2);\n    fill(WHITE, x+2,  y+14, 8,  6);\n    fill(BLACK, x+8,  y+18, 2,  2);\n    fill(WHITE, x+10, y+14, 2,  2);\n}\n\n/*\n * Wing middle.\n */\nvoid draw_wing2(int x, int y)\n{\n    fill(BLACK, x+2,  y+10, 10, 2);\n    fill(BLACK, x+2,  y+16, 10, 2);\n    fill(BLACK, x,    y+12, 2,  4);\n    fill(BLACK, x+12, y+12, 2,  4);\n    fill(WHITE, x+2,  y+12, 10, 4);\n}\n\n/*\n * Wing up.\n */\nvoid draw_wing3(int x, int y)\n{\n    fill(BLACK, x+2,  y+6,  8, 2);\n    fill(BLACK, x,    y+8,  2, 6);\n    fill(BLACK, x+10, y+8,  2, 2);\n    fill(BLACK, x+12, y+10, 2, 4);\n    fill(BLACK, x+10, y+14, 2, 2);\n    fill(BLACK, x+2,  y+14, 2, 2);\n    fill(BLACK, x+4,  y+16, 6, 2);\n    fill(WHITE, x+2,  y+8,  8, 6);\n    fill(WHITE, x+4,  y+14, 6, 2);\n    fill(WHITE, x+10, y+10, 2, 4);\n}\n\ntime_t millis()\n{\n    struct timeval tv;\n\n    gettimeofday(&tv, 0);\n    return (tv.tv_sec * 1000) + (tv.tv_usec / 1000);\n}\n\nvoid start_game()\n{\n    fx = 50;\n    fy = 125;\n    fall_rate = -1;\n    pillar_pos = 320;\n    gap_pos = 60;\n    crashed = 0;\n    score = 0;\n\n    gpanel_clear(BLUE, 0, 0);\n    gpanel_text(&font_lucidasans28, WHITE, BLUE, 10, 10,\n        \"Flappy Bird\");\n    gpanel_text(&font_lucidasans15, WHITE, BLUE, 50, 180,\n        \"(Press Space to start)\");\n\n    char score_line[80];\n    sprintf(score_line, \"High Score: %u\", high_score);\n    gpanel_text(&font_lucidasans28, GREEN, BLUE, 10, 60, score_line);\n\n    /* Draw ground. */\n    int tx, ty = 230;\n    for (tx = 0; tx <= 300; tx += 20) {\n        gpanel_fill_triangle(GREEN,  tx,    ty,   tx+9,  ty, tx,    ty+9);\n        gpanel_fill_triangle(YELLOW, tx+9,  ty+9, tx+9,  ty, tx,    ty+9);\n        gpanel_fill_triangle(YELLOW, tx+10, ty,   tx+19, ty, tx+10, ty+9);\n        gpanel_fill_triangle(GREEN,  tx+19, ty+9, tx+19, ty, tx+10, ty+9);\n    }\n\n    next_draw_time = millis() + DRAW_LOOP_INTERVAL;\n}\n\nvoid draw_loop()\n{\n    /* Clear moving items. */\n    clear_pillar(pillar_pos, gap_pos);\n\n    /* Move items. */\n    if (running) {\n        clear_flappy(fx, fy);\n\n        fy += fall_rate;\n        fall_rate++;\n\n        pillar_pos -= 5;\n        if (pillar_pos == 0) {\n            score++;\n        }\n        else if (pillar_pos < -50) {\n            pillar_pos = 320;\n            gap_pos = 20 + random() % 100;\n        }\n    }\n\n    /* Draw moving items & animate. */\n    draw_flappy(fx, fy);\n    draw_pillar(pillar_pos, gap_pos);\n    switch (wing) {\n    case 0:\n    case 1:\n        draw_wing1(fx, fy);\n        break;\n    case 2:\n    case 3:\n        draw_wing2(fx, fy);\n        break;\n    case 4:\n    case 5:\n        draw_wing3(fx, fy);\n        break;\n    }\n    wing++;\n    if (wing == 6)\n        wing = 0;\n}\n\n/*\n * Write high score value to file.\n */\nvoid save_score()\n{\n    int fd, nbytes;\n    char line[80];\n\n    fd = open(SCORE_FILENAME, O_WRONLY | O_CREAT, 0644);\n    if (fd < 0) {\n        perror(SCORE_FILENAME);\n        return;\n    }\n    sprintf(line, \"%u\\n\", high_score);\n    nbytes = strlen(line);\n    if (write(fd, line, nbytes) != nbytes)\n        perror(SCORE_FILENAME);\n    close(fd);\n}\n\n/*\n * Read high score value from file.\n */\nvoid load_score()\n{\n    int fd, nbytes;\n    char line[80];\n\n    fd = open(SCORE_FILENAME, O_RDONLY);\n    if (fd < 0) {\n        /* No high score file yet. */\n        return;\n    }\n    nbytes = read(fd, line, sizeof(line));\n    if (nbytes <= 0) {\n        if (nbytes < 0)\n            perror(SCORE_FILENAME);\n        return;\n    }\n    close(fd);\n    high_score = strtol(line, 0, 0);\n}\n\nvoid check_collision()\n{\n    /* Collision with ground. */\n    if (fy > 206)\n        crashed = 1;\n\n    /* Collision with pillar. */\n    if (fx + 34 > pillar_pos && fx < pillar_pos + 50)\n        if (fy < gap_pos || fy + 24 > gap_pos + 90)\n             crashed = 1;\n\n    if (crashed) {\n        gpanel_text(&font_lucidasans28, RED, BLUE, 50, 50, \"Game Over!\");\n\n        char score_line[80];\n        sprintf(score_line, \"Score: %u\", score);\n        gpanel_text(&font_lucidasans28, RED, BLUE, 50, 100, score_line);\n\n        if (score > high_score) {\n            high_score = score;\n            gpanel_text(&font_lucidasans28, RED, BLUE, 50, 150, \"NEW HIGH!\");\n            save_score();\n        }\n\n        /* Stop animation. */\n        running = 0;\n\n        /* Delay to stop any last minute clicks from restarting immediately. */\n        sleep(1);\n    }\n}\n\n#if 1\n#ifndef SDL\nstruct sgttyb origtty, newtty;\n#endif\n\n/*\n * Terminate the game when ^C pressed.\n */\nvoid quit(int sig)\n{\n    signal(SIGINT, SIG_IGN);\n#ifndef SDL\n    if (newtty.sg_flags != 0)\n        ioctl(0, TIOCSETP, &origtty);\n#endif\n    gpanel_close();\n    exit(0);\n}\n\n/*\n * Return 1 when any key is pressed on console.\n */\nint get_input()\n{\n#ifdef SDL\n    extern int gpanel_input(void);\n\n    return gpanel_input();\n#else\n    if (newtty.sg_flags == 0) {\n        ioctl(0, TIOCGETP, &origtty);\n\n        newtty = origtty;\n        newtty.sg_flags &= ~(ECHO|XTABS);\n        newtty.sg_flags |= CBREAK;\n        ioctl(0, TIOCSETP, &newtty);\n    }\n    int nchars = 0;\n    ioctl(0, FIONREAD, &nchars);\n    if (nchars <= 0)\n        return 0;\n\n    char c;\n    read(0, &c, 1);\n    return 1;\n#endif\n}\n#endif\n\nint main()\n{\n    char *devname = \"/dev/tft0\";\n    int xsize = 320, ysize = 240;\n\n    signal(SIGINT, quit);\n    if (gpanel_open(devname) < 0) {\n        printf(\"Cannot open %s\\n\", devname);\n        exit(-1);\n    }\n    gpanel_clear(BLUE, &xsize, &ysize);\n\n    load_score();\n    start_game();\n\n    for (;;) {\n        if (millis() > next_draw_time && !crashed) {\n            draw_loop();\n            check_collision();\n            next_draw_time += DRAW_LOOP_INTERVAL;\n        }\n        usleep(10000);\n\n        /* Get user input. */\n        int user_input = get_input();\n\n        /* Process \"user input\". */\n        if (user_input > 0 && !scr_press) {\n            if (crashed) {\n                /* Restart game. */\n                start_game();\n            }\n            else if (!running) {\n                /* Clear text & start scrolling. */\n                gpanel_fill(BLUE, 0, 0, 320-1, 100);\n                gpanel_fill(BLUE, 0, 180, 320-1, 205);\n                running = 1;\n            } else {\n                /* Fly up. */\n                fall_rate = -8;\n                scr_press = 1;\n            }\n        } else if (user_input == 0 && scr_press) {\n            /* Attempt to throttle presses. */\n            scr_press = 0;\n        }\n    }\n}\n"
  },
  {
    "path": "share/examples/gpanel/font.c",
    "content": "/*\n * Draw samples of various fonts.\n */\n#include <stdio.h>\n#include <sys/gpanel.h>\n\n/*\n * Data from external font files.\n */\nextern const struct gpanel_font_t font_lucidasans15;\nextern const struct gpanel_font_t font_lucidasans11;\nextern const struct gpanel_font_t font_lucidasans9;\nextern const struct gpanel_font_t font_lucidasans7;\nextern const struct gpanel_font_t font_verdana7;\nextern const struct gpanel_font_t font_6x9;\nextern const struct gpanel_font_t font_5x7;\nextern const struct gpanel_font_t font_digits32;\nextern const struct gpanel_font_t font_digits20;\n\n/*\n * Color constants.\n */\n#define COLOR_RGB(r,g,b)    ((r)<<11 | (g)<<5 | (b))\n#define COLOR_BLACK         0\n#define COLOR_WHITE         COLOR_RGB(31, 63, 31)\n#define COLOR_YELLOW        COLOR_RGB(31, 63, 0)\n#define COLOR_MAGENTA       COLOR_RGB(31, 0,  31)\n#define COLOR_CYAN          COLOR_RGB(0,  63, 31)\n#define COLOR_RED           COLOR_RGB(31, 0,  0)\n#define COLOR_GREEN         COLOR_RGB(0,  63, 0)\n#define COLOR_BLUE          COLOR_RGB(0,  0,  31)\n\n/*\n * Screen size.\n */\nint xsize, ysize;\n\nvoid show(const struct gpanel_font_t *font, const char *title, int digits_only)\n{\n    char line[100];\n    int x = 0, y = 0, i, color;\n    const char *phrase = digits_only ? \"0123456789\" :\n                         \"The quick brown fox jumps over the lazy dog.\";\n    static const int colortab[] = {\n        COLOR_YELLOW, COLOR_CYAN,  COLOR_MAGENTA,\n        COLOR_RED,    COLOR_GREEN, COLOR_BLUE,\n        0,\n    };\n\n    gpanel_clear(COLOR_BLACK, 0, 0);\n    gpanel_text(&font_lucidasans15, COLOR_WHITE, COLOR_BLACK, x, y, title);\n    y += font_lucidasans15.height * 2;\n\n    for (i=0; y<ysize; i++) {\n        color = colortab[i];\n        if (color == 0)\n            color = colortab[i = 0];\n\n        gpanel_text(font, color, COLOR_BLACK, x, y, phrase);\n        y += font->height;\n    }\n\n    printf(\"Font %s: press Enter...\", title);\n    fflush(stdout);\n    fgets(line, sizeof(line), stdin);\n}\n\nint main()\n{\n    char *devname = \"/dev/tft0\";\n    int x, y, color;\n\n    if (gpanel_open(devname) < 0) {\n        printf(\"Cannot open %s\\n\", devname);\n        exit(-1);\n    }\n    gpanel_clear(0, &xsize, &ysize);\n    printf(\"Screen size %u x %u.\\n\", xsize, ysize);\n    printf(\"Draw fonts.\\n\");\n    printf(\"Press ^C to stop.\\n\");\n\n    for (;;) {\n        show(&font_lucidasans15, \"Lucida Sans 15\", 0);\n        show(&font_lucidasans11, \"Lucida Sans 11\", 0);\n        show(&font_lucidasans9, \"Lucida Sans 9\", 0);\n        show(&font_lucidasans7, \"Lucida Sans 7\", 0);\n        show(&font_verdana7, \"Verdana 7\", 0);\n        show(&font_6x9, \"Fixed 6x9\", 0);\n        show(&font_5x7, \"Fixed 5x7\", 0);\n        show(&font_digits32, \"Digits 32\", 1);\n        show(&font_digits20, \"Digits 20\", 1);\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/gpanel/fonts/5x7.c",
    "content": "/* Generated by convbdf on Thu Oct  8 21:26:35 2015. */\n#include <sys/gpanel.h>\n\n/* Font information:\n   name: 5x7\n   facename: -Misc-Fixed-Medium-R-Normal--7-70-75-75-C-50-ISO10646-1\n   w x h: 5x7\n   size: 1104\n   ascent: 6\n   descent: 1\n   first char: 0 (0x00)\n   last char: 1103 (0x44f)\n   default char: 0 (0x00)\n   proportional: no\n   Public domain font.  Share and enjoy.\n*/\n\n/* Font character bitmap data. */\nstatic const unsigned short _5x7_bits[] = {\n\n/* Character 0 (0x00):\n   width 5\n   +-----+\n   |     |\n   |* * *|\n   |     |\n   |*   *|\n   |     |\n   |* * *|\n   |     |\n   +-----+ */\n0x0000,\n0xa800,\n0x0000,\n0x8800,\n0x0000,\n0xa800,\n0x0000,\n\n/* Character 32 (0x20):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 33 (0x21):\n   width 5\n   +-----+\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |     |\n   |  *  |\n   |     |\n   +-----+ */\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x0000,\n0x2000,\n0x0000,\n\n/* Character 34 (0x22):\n   width 5\n   +-----+\n   | * * |\n   | * * |\n   | * * |\n   |     |\n   |     |\n   |     |\n   |     |\n   +-----+ */\n0x5000,\n0x5000,\n0x5000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 35 (0x23):\n   width 5\n   +-----+\n   |     |\n   | * * |\n   |*****|\n   | * * |\n   |*****|\n   | * * |\n   |     |\n   +-----+ */\n0x0000,\n0x5000,\n0xf800,\n0x5000,\n0xf800,\n0x5000,\n0x0000,\n\n/* Character 36 (0x24):\n   width 5\n   +-----+\n   |     |\n   | *** |\n   |* *  |\n   | *** |\n   |  * *|\n   | *** |\n   |     |\n   +-----+ */\n0x0000,\n0x7000,\n0xa000,\n0x7000,\n0x2800,\n0x7000,\n0x0000,\n\n/* Character 37 (0x25):\n   width 5\n   +-----+\n   |*    |\n   |*  * |\n   |  *  |\n   | *   |\n   |*  * |\n   |   * |\n   |     |\n   +-----+ */\n0x8000,\n0x9000,\n0x2000,\n0x4000,\n0x9000,\n0x1000,\n0x0000,\n\n/* Character 38 (0x26):\n   width 5\n   +-----+\n   |     |\n   | *   |\n   |* *  |\n   | *   |\n   |* *  |\n   | * * |\n   |     |\n   +-----+ */\n0x0000,\n0x4000,\n0xa000,\n0x4000,\n0xa000,\n0x5000,\n0x0000,\n\n/* Character 39 (0x27):\n   width 5\n   +-----+\n   |  *  |\n   |  *  |\n   |  *  |\n   |     |\n   |     |\n   |     |\n   |     |\n   +-----+ */\n0x2000,\n0x2000,\n0x2000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 40 (0x28):\n   width 5\n   +-----+\n   |  *  |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   |  *  |\n   |     |\n   +-----+ */\n0x2000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x2000,\n0x0000,\n\n/* Character 41 (0x29):\n   width 5\n   +-----+\n   | *   |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   | *   |\n   |     |\n   +-----+ */\n0x4000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x4000,\n0x0000,\n\n/* Character 42 (0x2a):\n   width 5\n   +-----+\n   |     |\n   | * * |\n   |  *  |\n   | *** |\n   |  *  |\n   | * * |\n   |     |\n   +-----+ */\n0x0000,\n0x5000,\n0x2000,\n0x7000,\n0x2000,\n0x5000,\n0x0000,\n\n/* Character 43 (0x2b):\n   width 5\n   +-----+\n   |     |\n   |  *  |\n   |  *  |\n   |*****|\n   |  *  |\n   |  *  |\n   |     |\n   +-----+ */\n0x0000,\n0x2000,\n0x2000,\n0xf800,\n0x2000,\n0x2000,\n0x0000,\n\n/* Character 44 (0x2c):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |     |\n   |  ** |\n   |  *  |\n   | *   |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x2000,\n0x4000,\n\n/* Character 45 (0x2d):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |**** |\n   |     |\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0xf000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 46 (0x2e):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |     |\n   | **  |\n   | **  |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x6000,\n0x6000,\n0x0000,\n\n/* Character 47 (0x2f):\n   width 5\n   +-----+\n   |     |\n   |   * |\n   |  *  |\n   | *   |\n   |*    |\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x1000,\n0x2000,\n0x4000,\n0x8000,\n0x0000,\n0x0000,\n\n/* Character 48 (0x30):\n   width 5\n   +-----+\n   |  *  |\n   | * * |\n   | * * |\n   | * * |\n   | * * |\n   |  *  |\n   |     |\n   +-----+ */\n0x2000,\n0x5000,\n0x5000,\n0x5000,\n0x5000,\n0x2000,\n0x0000,\n\n/* Character 49 (0x31):\n   width 5\n   +-----+\n   |  *  |\n   | **  |\n   |  *  |\n   |  *  |\n   |  *  |\n   | *** |\n   |     |\n   +-----+ */\n0x2000,\n0x6000,\n0x2000,\n0x2000,\n0x2000,\n0x7000,\n0x0000,\n\n/* Character 50 (0x32):\n   width 5\n   +-----+\n   | **  |\n   |*  * |\n   |   * |\n   |  *  |\n   | *   |\n   |**** |\n   |     |\n   +-----+ */\n0x6000,\n0x9000,\n0x1000,\n0x2000,\n0x4000,\n0xf000,\n0x0000,\n\n/* Character 51 (0x33):\n   width 5\n   +-----+\n   |**** |\n   |   * |\n   | **  |\n   |   * |\n   |*  * |\n   | **  |\n   |     |\n   +-----+ */\n0xf000,\n0x1000,\n0x6000,\n0x1000,\n0x9000,\n0x6000,\n0x0000,\n\n/* Character 52 (0x34):\n   width 5\n   +-----+\n   |  *  |\n   | **  |\n   |* *  |\n   |**** |\n   |  *  |\n   |  *  |\n   |     |\n   +-----+ */\n0x2000,\n0x6000,\n0xa000,\n0xf000,\n0x2000,\n0x2000,\n0x0000,\n\n/* Character 53 (0x35):\n   width 5\n   +-----+\n   |**** |\n   |*    |\n   |***  |\n   |   * |\n   |*  * |\n   | **  |\n   |     |\n   +-----+ */\n0xf000,\n0x8000,\n0xe000,\n0x1000,\n0x9000,\n0x6000,\n0x0000,\n\n/* Character 54 (0x36):\n   width 5\n   +-----+\n   | **  |\n   |*    |\n   |***  |\n   |*  * |\n   |*  * |\n   | **  |\n   |     |\n   +-----+ */\n0x6000,\n0x8000,\n0xe000,\n0x9000,\n0x9000,\n0x6000,\n0x0000,\n\n/* Character 55 (0x37):\n   width 5\n   +-----+\n   |**** |\n   |   * |\n   |  *  |\n   |  *  |\n   | *   |\n   | *   |\n   |     |\n   +-----+ */\n0xf000,\n0x1000,\n0x2000,\n0x2000,\n0x4000,\n0x4000,\n0x0000,\n\n/* Character 56 (0x38):\n   width 5\n   +-----+\n   | **  |\n   |*  * |\n   | **  |\n   |*  * |\n   |*  * |\n   | **  |\n   |     |\n   +-----+ */\n0x6000,\n0x9000,\n0x6000,\n0x9000,\n0x9000,\n0x6000,\n0x0000,\n\n/* Character 57 (0x39):\n   width 5\n   +-----+\n   | **  |\n   |*  * |\n   |*  * |\n   | *** |\n   |   * |\n   | **  |\n   |     |\n   +-----+ */\n0x6000,\n0x9000,\n0x9000,\n0x7000,\n0x1000,\n0x6000,\n0x0000,\n\n/* Character 58 (0x3a):\n   width 5\n   +-----+\n   |     |\n   | **  |\n   | **  |\n   |     |\n   | **  |\n   | **  |\n   |     |\n   +-----+ */\n0x0000,\n0x6000,\n0x6000,\n0x0000,\n0x6000,\n0x6000,\n0x0000,\n\n/* Character 59 (0x3b):\n   width 5\n   +-----+\n   |     |\n   | **  |\n   | **  |\n   |     |\n   | **  |\n   | *   |\n   |*    |\n   +-----+ */\n0x0000,\n0x6000,\n0x6000,\n0x0000,\n0x6000,\n0x4000,\n0x8000,\n\n/* Character 60 (0x3c):\n   width 5\n   +-----+\n   |     |\n   |   * |\n   |  *  |\n   | *   |\n   |  *  |\n   |   * |\n   |     |\n   +-----+ */\n0x0000,\n0x1000,\n0x2000,\n0x4000,\n0x2000,\n0x1000,\n0x0000,\n\n/* Character 61 (0x3d):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |**** |\n   |     |\n   |**** |\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0xf000,\n0x0000,\n0xf000,\n0x0000,\n0x0000,\n\n/* Character 62 (0x3e):\n   width 5\n   +-----+\n   |     |\n   | *   |\n   |  *  |\n   |   * |\n   |  *  |\n   | *   |\n   |     |\n   +-----+ */\n0x0000,\n0x4000,\n0x2000,\n0x1000,\n0x2000,\n0x4000,\n0x0000,\n\n/* Character 63 (0x3f):\n   width 5\n   +-----+\n   |  *  |\n   | * * |\n   |   * |\n   |  *  |\n   |     |\n   |  *  |\n   |     |\n   +-----+ */\n0x2000,\n0x5000,\n0x1000,\n0x2000,\n0x0000,\n0x2000,\n0x0000,\n\n/* Character 64 (0x40):\n   width 5\n   +-----+\n   | **  |\n   |*  * |\n   |* ** |\n   |* ** |\n   |*    |\n   | **  |\n   |     |\n   +-----+ */\n0x6000,\n0x9000,\n0xb000,\n0xb000,\n0x8000,\n0x6000,\n0x0000,\n\n/* Character 65 (0x41):\n   width 5\n   +-----+\n   | **  |\n   |*  * |\n   |*  * |\n   |**** |\n   |*  * |\n   |*  * |\n   |     |\n   +-----+ */\n0x6000,\n0x9000,\n0x9000,\n0xf000,\n0x9000,\n0x9000,\n0x0000,\n\n/* Character 66 (0x42):\n   width 5\n   +-----+\n   |***  |\n   |*  * |\n   |***  |\n   |*  * |\n   |*  * |\n   |***  |\n   |     |\n   +-----+ */\n0xe000,\n0x9000,\n0xe000,\n0x9000,\n0x9000,\n0xe000,\n0x0000,\n\n/* Character 67 (0x43):\n   width 5\n   +-----+\n   | **  |\n   |*  * |\n   |*    |\n   |*    |\n   |*  * |\n   | **  |\n   |     |\n   +-----+ */\n0x6000,\n0x9000,\n0x8000,\n0x8000,\n0x9000,\n0x6000,\n0x0000,\n\n/* Character 68 (0x44):\n   width 5\n   +-----+\n   |***  |\n   |*  * |\n   |*  * |\n   |*  * |\n   |*  * |\n   |***  |\n   |     |\n   +-----+ */\n0xe000,\n0x9000,\n0x9000,\n0x9000,\n0x9000,\n0xe000,\n0x0000,\n\n/* Character 69 (0x45):\n   width 5\n   +-----+\n   |**** |\n   |*    |\n   |***  |\n   |*    |\n   |*    |\n   |**** |\n   |     |\n   +-----+ */\n0xf000,\n0x8000,\n0xe000,\n0x8000,\n0x8000,\n0xf000,\n0x0000,\n\n/* Character 70 (0x46):\n   width 5\n   +-----+\n   |**** |\n   |*    |\n   |***  |\n   |*    |\n   |*    |\n   |*    |\n   |     |\n   +-----+ */\n0xf000,\n0x8000,\n0xe000,\n0x8000,\n0x8000,\n0x8000,\n0x0000,\n\n/* Character 71 (0x47):\n   width 5\n   +-----+\n   | **  |\n   |*  * |\n   |*    |\n   |* ** |\n   |*  * |\n   | *** |\n   |     |\n   +-----+ */\n0x6000,\n0x9000,\n0x8000,\n0xb000,\n0x9000,\n0x7000,\n0x0000,\n\n/* Character 72 (0x48):\n   width 5\n   +-----+\n   |*  * |\n   |*  * |\n   |**** |\n   |*  * |\n   |*  * |\n   |*  * |\n   |     |\n   +-----+ */\n0x9000,\n0x9000,\n0xf000,\n0x9000,\n0x9000,\n0x9000,\n0x0000,\n\n/* Character 73 (0x49):\n   width 5\n   +-----+\n   | *** |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   | *** |\n   |     |\n   +-----+ */\n0x7000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x7000,\n0x0000,\n\n/* Character 74 (0x4a):\n   width 5\n   +-----+\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |*  * |\n   | **  |\n   |     |\n   +-----+ */\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x9000,\n0x6000,\n0x0000,\n\n/* Character 75 (0x4b):\n   width 5\n   +-----+\n   |*  * |\n   |* *  |\n   |**   |\n   |**   |\n   |* *  |\n   |*  * |\n   |     |\n   +-----+ */\n0x9000,\n0xa000,\n0xc000,\n0xc000,\n0xa000,\n0x9000,\n0x0000,\n\n/* Character 76 (0x4c):\n   width 5\n   +-----+\n   |*    |\n   |*    |\n   |*    |\n   |*    |\n   |*    |\n   |**** |\n   |     |\n   +-----+ */\n0x8000,\n0x8000,\n0x8000,\n0x8000,\n0x8000,\n0xf000,\n0x0000,\n\n/* Character 77 (0x4d):\n   width 5\n   +-----+\n   |*  * |\n   |**** |\n   |**** |\n   |*  * |\n   |*  * |\n   |*  * |\n   |     |\n   +-----+ */\n0x9000,\n0xf000,\n0xf000,\n0x9000,\n0x9000,\n0x9000,\n0x0000,\n\n/* Character 78 (0x4e):\n   width 5\n   +-----+\n   |*  * |\n   |** * |\n   |** * |\n   |* ** |\n   |* ** |\n   |*  * |\n   |     |\n   +-----+ */\n0x9000,\n0xd000,\n0xd000,\n0xb000,\n0xb000,\n0x9000,\n0x0000,\n\n/* Character 79 (0x4f):\n   width 5\n   +-----+\n   | **  |\n   |*  * |\n   |*  * |\n   |*  * |\n   |*  * |\n   | **  |\n   |     |\n   +-----+ */\n0x6000,\n0x9000,\n0x9000,\n0x9000,\n0x9000,\n0x6000,\n0x0000,\n\n/* Character 80 (0x50):\n   width 5\n   +-----+\n   |***  |\n   |*  * |\n   |*  * |\n   |***  |\n   |*    |\n   |*    |\n   |     |\n   +-----+ */\n0xe000,\n0x9000,\n0x9000,\n0xe000,\n0x8000,\n0x8000,\n0x0000,\n\n/* Character 81 (0x51):\n   width 5\n   +-----+\n   | **  |\n   |*  * |\n   |*  * |\n   |*  * |\n   |** * |\n   | **  |\n   |   * |\n   +-----+ */\n0x6000,\n0x9000,\n0x9000,\n0x9000,\n0xd000,\n0x6000,\n0x1000,\n\n/* Character 82 (0x52):\n   width 5\n   +-----+\n   |***  |\n   |*  * |\n   |*  * |\n   |***  |\n   |* *  |\n   |*  * |\n   |     |\n   +-----+ */\n0xe000,\n0x9000,\n0x9000,\n0xe000,\n0xa000,\n0x9000,\n0x0000,\n\n/* Character 83 (0x53):\n   width 5\n   +-----+\n   | **  |\n   |*  * |\n   | *   |\n   |  *  |\n   |*  * |\n   | **  |\n   |     |\n   +-----+ */\n0x6000,\n0x9000,\n0x4000,\n0x2000,\n0x9000,\n0x6000,\n0x0000,\n\n/* Character 84 (0x54):\n   width 5\n   +-----+\n   | *** |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |     |\n   +-----+ */\n0x7000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x0000,\n\n/* Character 85 (0x55):\n   width 5\n   +-----+\n   |*  * |\n   |*  * |\n   |*  * |\n   |*  * |\n   |*  * |\n   | **  |\n   |     |\n   +-----+ */\n0x9000,\n0x9000,\n0x9000,\n0x9000,\n0x9000,\n0x6000,\n0x0000,\n\n/* Character 86 (0x56):\n   width 5\n   +-----+\n   |*  * |\n   |*  * |\n   |*  * |\n   |*  * |\n   | **  |\n   | **  |\n   |     |\n   +-----+ */\n0x9000,\n0x9000,\n0x9000,\n0x9000,\n0x6000,\n0x6000,\n0x0000,\n\n/* Character 87 (0x57):\n   width 5\n   +-----+\n   |*  * |\n   |*  * |\n   |*  * |\n   |**** |\n   |**** |\n   |*  * |\n   |     |\n   +-----+ */\n0x9000,\n0x9000,\n0x9000,\n0xf000,\n0xf000,\n0x9000,\n0x0000,\n\n/* Character 88 (0x58):\n   width 5\n   +-----+\n   |*  * |\n   |*  * |\n   | **  |\n   | **  |\n   |*  * |\n   |*  * |\n   |     |\n   +-----+ */\n0x9000,\n0x9000,\n0x6000,\n0x6000,\n0x9000,\n0x9000,\n0x0000,\n\n/* Character 89 (0x59):\n   width 5\n   +-----+\n   | * * |\n   | * * |\n   | * * |\n   |  *  |\n   |  *  |\n   |  *  |\n   |     |\n   +-----+ */\n0x5000,\n0x5000,\n0x5000,\n0x2000,\n0x2000,\n0x2000,\n0x0000,\n\n/* Character 90 (0x5a):\n   width 5\n   +-----+\n   |**** |\n   |   * |\n   |  *  |\n   | *   |\n   |*    |\n   |**** |\n   |     |\n   +-----+ */\n0xf000,\n0x1000,\n0x2000,\n0x4000,\n0x8000,\n0xf000,\n0x0000,\n\n/* Character 91 (0x5b):\n   width 5\n   +-----+\n   | *** |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   | *** |\n   |     |\n   +-----+ */\n0x7000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x7000,\n0x0000,\n\n/* Character 92 (0x5c):\n   width 5\n   +-----+\n   |     |\n   |*    |\n   | *   |\n   |  *  |\n   |   * |\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x8000,\n0x4000,\n0x2000,\n0x1000,\n0x0000,\n0x0000,\n\n/* Character 93 (0x5d):\n   width 5\n   +-----+\n   | *** |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   | *** |\n   |     |\n   +-----+ */\n0x7000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x7000,\n0x0000,\n\n/* Character 94 (0x5e):\n   width 5\n   +-----+\n   |  *  |\n   | * * |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   +-----+ */\n0x2000,\n0x5000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 95 (0x5f):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |**** |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0xf000,\n0x0000,\n\n/* Character 96 (0x60):\n   width 5\n   +-----+\n   | *   |\n   |  *  |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   +-----+ */\n0x4000,\n0x2000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 97 (0x61):\n   width 5\n   +-----+\n   |     |\n   |     |\n   | *** |\n   |*  * |\n   |* ** |\n   | * * |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x7000,\n0x9000,\n0xb000,\n0x5000,\n0x0000,\n\n/* Character 98 (0x62):\n   width 5\n   +-----+\n   |*    |\n   |*    |\n   |***  |\n   |*  * |\n   |*  * |\n   |***  |\n   |     |\n   +-----+ */\n0x8000,\n0x8000,\n0xe000,\n0x9000,\n0x9000,\n0xe000,\n0x0000,\n\n/* Character 99 (0x63):\n   width 5\n   +-----+\n   |     |\n   |     |\n   | **  |\n   |*    |\n   |*    |\n   | **  |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x6000,\n0x8000,\n0x8000,\n0x6000,\n0x0000,\n\n/* Character 100 (0x64):\n   width 5\n   +-----+\n   |   * |\n   |   * |\n   | *** |\n   |*  * |\n   |*  * |\n   | *** |\n   |     |\n   +-----+ */\n0x1000,\n0x1000,\n0x7000,\n0x9000,\n0x9000,\n0x7000,\n0x0000,\n\n/* Character 101 (0x65):\n   width 5\n   +-----+\n   |     |\n   |     |\n   | **  |\n   |* ** |\n   |**   |\n   | **  |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x6000,\n0xb000,\n0xc000,\n0x6000,\n0x0000,\n\n/* Character 102 (0x66):\n   width 5\n   +-----+\n   |  *  |\n   | * * |\n   | *   |\n   |***  |\n   | *   |\n   | *   |\n   |     |\n   +-----+ */\n0x2000,\n0x5000,\n0x4000,\n0xe000,\n0x4000,\n0x4000,\n0x0000,\n\n/* Character 103 (0x67):\n   width 5\n   +-----+\n   |     |\n   |     |\n   | *** |\n   |*  * |\n   | **  |\n   |*    |\n   | *** |\n   +-----+ */\n0x0000,\n0x0000,\n0x7000,\n0x9000,\n0x6000,\n0x8000,\n0x7000,\n\n/* Character 104 (0x68):\n   width 5\n   +-----+\n   |*    |\n   |*    |\n   |***  |\n   |*  * |\n   |*  * |\n   |*  * |\n   |     |\n   +-----+ */\n0x8000,\n0x8000,\n0xe000,\n0x9000,\n0x9000,\n0x9000,\n0x0000,\n\n/* Character 105 (0x69):\n   width 5\n   +-----+\n   |  *  |\n   |     |\n   | **  |\n   |  *  |\n   |  *  |\n   | *** |\n   |     |\n   +-----+ */\n0x2000,\n0x0000,\n0x6000,\n0x2000,\n0x2000,\n0x7000,\n0x0000,\n\n/* Character 106 (0x6a):\n   width 5\n   +-----+\n   |   * |\n   |     |\n   |   * |\n   |   * |\n   |   * |\n   | * * |\n   |  *  |\n   +-----+ */\n0x1000,\n0x0000,\n0x1000,\n0x1000,\n0x1000,\n0x5000,\n0x2000,\n\n/* Character 107 (0x6b):\n   width 5\n   +-----+\n   |*    |\n   |*    |\n   |* *  |\n   |**   |\n   |* *  |\n   |*  * |\n   |     |\n   +-----+ */\n0x8000,\n0x8000,\n0xa000,\n0xc000,\n0xa000,\n0x9000,\n0x0000,\n\n/* Character 108 (0x6c):\n   width 5\n   +-----+\n   | **  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   | *** |\n   |     |\n   +-----+ */\n0x6000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x7000,\n0x0000,\n\n/* Character 109 (0x6d):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |* *  |\n   |**** |\n   |*  * |\n   |*  * |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0xa000,\n0xf000,\n0x9000,\n0x9000,\n0x0000,\n\n/* Character 110 (0x6e):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |***  |\n   |*  * |\n   |*  * |\n   |*  * |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0xe000,\n0x9000,\n0x9000,\n0x9000,\n0x0000,\n\n/* Character 111 (0x6f):\n   width 5\n   +-----+\n   |     |\n   |     |\n   | **  |\n   |*  * |\n   |*  * |\n   | **  |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x6000,\n0x9000,\n0x9000,\n0x6000,\n0x0000,\n\n/* Character 112 (0x70):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |***  |\n   |*  * |\n   |*  * |\n   |***  |\n   |*    |\n   +-----+ */\n0x0000,\n0x0000,\n0xe000,\n0x9000,\n0x9000,\n0xe000,\n0x8000,\n\n/* Character 113 (0x71):\n   width 5\n   +-----+\n   |     |\n   |     |\n   | *** |\n   |*  * |\n   |*  * |\n   | *** |\n   |   * |\n   +-----+ */\n0x0000,\n0x0000,\n0x7000,\n0x9000,\n0x9000,\n0x7000,\n0x1000,\n\n/* Character 114 (0x72):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |***  |\n   |*  * |\n   |*    |\n   |*    |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0xe000,\n0x9000,\n0x8000,\n0x8000,\n0x0000,\n\n/* Character 115 (0x73):\n   width 5\n   +-----+\n   |     |\n   |     |\n   | *** |\n   |**   |\n   |  ** |\n   |***  |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x7000,\n0xc000,\n0x3000,\n0xe000,\n0x0000,\n\n/* Character 116 (0x74):\n   width 5\n   +-----+\n   | *   |\n   | *   |\n   |***  |\n   | *   |\n   | *   |\n   |  ** |\n   |     |\n   +-----+ */\n0x4000,\n0x4000,\n0xe000,\n0x4000,\n0x4000,\n0x3000,\n0x0000,\n\n/* Character 117 (0x75):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |*  * |\n   |*  * |\n   |*  * |\n   | *** |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x9000,\n0x9000,\n0x9000,\n0x7000,\n0x0000,\n\n/* Character 118 (0x76):\n   width 5\n   +-----+\n   |     |\n   |     |\n   | * * |\n   | * * |\n   | * * |\n   |  *  |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x5000,\n0x5000,\n0x5000,\n0x2000,\n0x0000,\n\n/* Character 119 (0x77):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |*  * |\n   |*  * |\n   |**** |\n   |**** |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x9000,\n0x9000,\n0xf000,\n0xf000,\n0x0000,\n\n/* Character 120 (0x78):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |*  * |\n   | **  |\n   | **  |\n   |*  * |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x9000,\n0x6000,\n0x6000,\n0x9000,\n0x0000,\n\n/* Character 121 (0x79):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |*  * |\n   |*  * |\n   | * * |\n   |  *  |\n   | *   |\n   +-----+ */\n0x0000,\n0x0000,\n0x9000,\n0x9000,\n0x5000,\n0x2000,\n0x4000,\n\n/* Character 122 (0x7a):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |**** |\n   |  *  |\n   | *   |\n   |**** |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0xf000,\n0x2000,\n0x4000,\n0xf000,\n0x0000,\n\n/* Character 123 (0x7b):\n   width 5\n   +-----+\n   |   * |\n   |  *  |\n   | **  |\n   |  *  |\n   |  *  |\n   |   * |\n   |     |\n   +-----+ */\n0x1000,\n0x2000,\n0x6000,\n0x2000,\n0x2000,\n0x1000,\n0x0000,\n\n/* Character 124 (0x7c):\n   width 5\n   +-----+\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |     |\n   +-----+ */\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x0000,\n\n/* Character 125 (0x7d):\n   width 5\n   +-----+\n   | *   |\n   |  *  |\n   |  ** |\n   |  *  |\n   |  *  |\n   | *   |\n   |     |\n   +-----+ */\n0x4000,\n0x2000,\n0x3000,\n0x2000,\n0x2000,\n0x4000,\n0x0000,\n\n/* Character 126 (0x7e):\n   width 5\n   +-----+\n   | * * |\n   |* *  |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   +-----+ */\n0x5000,\n0xa000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 1040 (0x410):\n   width 5\n   +-----+\n   | **  |\n   |*  * |\n   |*  * |\n   |**** |\n   |*  * |\n   |*  * |\n   |     |\n   +-----+ */\n0x6000,\n0x9000,\n0x9000,\n0xf000,\n0x9000,\n0x9000,\n0x0000,\n\n/* Character 1041 (0x411):\n   width 5\n   +-----+\n   |***  |\n   |*    |\n   |***  |\n   |*  * |\n   |*  * |\n   |***  |\n   |     |\n   +-----+ */\n0xe000,\n0x8000,\n0xe000,\n0x9000,\n0x9000,\n0xe000,\n0x0000,\n\n/* Character 1042 (0x412):\n   width 5\n   +-----+\n   |***  |\n   |*  * |\n   |***  |\n   |*  * |\n   |*  * |\n   |***  |\n   |     |\n   +-----+ */\n0xe000,\n0x9000,\n0xe000,\n0x9000,\n0x9000,\n0xe000,\n0x0000,\n\n/* Character 1043 (0x413):\n   width 5\n   +-----+\n   |**** |\n   |*    |\n   |*    |\n   |*    |\n   |*    |\n   |*    |\n   |     |\n   +-----+ */\n0xf000,\n0x8000,\n0x8000,\n0x8000,\n0x8000,\n0x8000,\n0x0000,\n\n/* Character 1044 (0x414):\n   width 5\n   +-----+\n   |  ** |\n   | * * |\n   | * * |\n   | * * |\n   | * * |\n   |**** |\n   |*  * |\n   +-----+ */\n0x3000,\n0x5000,\n0x5000,\n0x5000,\n0x5000,\n0xf000,\n0x9000,\n\n/* Character 1045 (0x415):\n   width 5\n   +-----+\n   |**** |\n   |*    |\n   |***  |\n   |*    |\n   |*    |\n   |**** |\n   |     |\n   +-----+ */\n0xf000,\n0x8000,\n0xe000,\n0x8000,\n0x8000,\n0xf000,\n0x0000,\n\n/* Character 1046 (0x416):\n   width 5\n   +-----+\n   |* * *|\n   |* * *|\n   | *** |\n   | *** |\n   |* * *|\n   |* * *|\n   |     |\n   +-----+ */\n0xa800,\n0xa800,\n0x7000,\n0x7000,\n0xa800,\n0xa800,\n0x0000,\n\n/* Character 1047 (0x417):\n   width 5\n   +-----+\n   |***  |\n   |   * |\n   | **  |\n   |   * |\n   |*  * |\n   | **  |\n   |     |\n   +-----+ */\n0xe000,\n0x1000,\n0x6000,\n0x1000,\n0x9000,\n0x6000,\n0x0000,\n\n/* Character 1048 (0x418):\n   width 5\n   +-----+\n   |*  * |\n   |* ** |\n   |* ** |\n   |** * |\n   |** * |\n   |*  * |\n   |     |\n   +-----+ */\n0x9000,\n0xb000,\n0xb000,\n0xd000,\n0xd000,\n0x9000,\n0x0000,\n\n/* Character 1049 (0x419):\n   width 5\n   +-----+\n   |** * |\n   |* ** |\n   |* ** |\n   |** * |\n   |** * |\n   |*  * |\n   |     |\n   +-----+ */\n0xd000,\n0xb000,\n0xb000,\n0xd000,\n0xd000,\n0x9000,\n0x0000,\n\n/* Character 1050 (0x41a):\n   width 5\n   +-----+\n   |*  * |\n   |* *  |\n   |**   |\n   |**   |\n   |* *  |\n   |*  * |\n   |     |\n   +-----+ */\n0x9000,\n0xa000,\n0xc000,\n0xc000,\n0xa000,\n0x9000,\n0x0000,\n\n/* Character 1051 (0x41b):\n   width 5\n   +-----+\n   |  ** |\n   | * * |\n   | * * |\n   | * * |\n   | * * |\n   |*  * |\n   |     |\n   +-----+ */\n0x3000,\n0x5000,\n0x5000,\n0x5000,\n0x5000,\n0x9000,\n0x0000,\n\n/* Character 1052 (0x41c):\n   width 5\n   +-----+\n   |*  * |\n   |**** |\n   |**** |\n   |*  * |\n   |*  * |\n   |*  * |\n   |     |\n   +-----+ */\n0x9000,\n0xf000,\n0xf000,\n0x9000,\n0x9000,\n0x9000,\n0x0000,\n\n/* Character 1053 (0x41d):\n   width 5\n   +-----+\n   |*  * |\n   |*  * |\n   |**** |\n   |*  * |\n   |*  * |\n   |*  * |\n   |     |\n   +-----+ */\n0x9000,\n0x9000,\n0xf000,\n0x9000,\n0x9000,\n0x9000,\n0x0000,\n\n/* Character 1054 (0x41e):\n   width 5\n   +-----+\n   | **  |\n   |*  * |\n   |*  * |\n   |*  * |\n   |*  * |\n   | **  |\n   |     |\n   +-----+ */\n0x6000,\n0x9000,\n0x9000,\n0x9000,\n0x9000,\n0x6000,\n0x0000,\n\n/* Character 1055 (0x41f):\n   width 5\n   +-----+\n   |**** |\n   |*  * |\n   |*  * |\n   |*  * |\n   |*  * |\n   |*  * |\n   |     |\n   +-----+ */\n0xf000,\n0x9000,\n0x9000,\n0x9000,\n0x9000,\n0x9000,\n0x0000,\n\n/* Character 1056 (0x420):\n   width 5\n   +-----+\n   |***  |\n   |*  * |\n   |*  * |\n   |***  |\n   |*    |\n   |*    |\n   |     |\n   +-----+ */\n0xe000,\n0x9000,\n0x9000,\n0xe000,\n0x8000,\n0x8000,\n0x0000,\n\n/* Character 1057 (0x421):\n   width 5\n   +-----+\n   | **  |\n   |*  * |\n   |*    |\n   |*    |\n   |*  * |\n   | **  |\n   |     |\n   +-----+ */\n0x6000,\n0x9000,\n0x8000,\n0x8000,\n0x9000,\n0x6000,\n0x0000,\n\n/* Character 1058 (0x422):\n   width 5\n   +-----+\n   | *** |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |     |\n   +-----+ */\n0x7000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x0000,\n\n/* Character 1059 (0x423):\n   width 5\n   +-----+\n   | * * |\n   | * * |\n   | * * |\n   |  *  |\n   |  *  |\n   | *   |\n   |     |\n   +-----+ */\n0x5000,\n0x5000,\n0x5000,\n0x2000,\n0x2000,\n0x4000,\n0x0000,\n\n/* Character 1060 (0x424):\n   width 5\n   +-----+\n   |  *  |\n   | *** |\n   | * * |\n   | * * |\n   | *** |\n   |  *  |\n   |     |\n   +-----+ */\n0x2000,\n0x7000,\n0x5000,\n0x5000,\n0x7000,\n0x2000,\n0x0000,\n\n/* Character 1061 (0x425):\n   width 5\n   +-----+\n   |*  * |\n   |*  * |\n   | **  |\n   | **  |\n   |*  * |\n   |*  * |\n   |     |\n   +-----+ */\n0x9000,\n0x9000,\n0x6000,\n0x6000,\n0x9000,\n0x9000,\n0x0000,\n\n/* Character 1062 (0x426):\n   width 5\n   +-----+\n   |*  * |\n   |*  * |\n   |*  * |\n   |*  * |\n   |*  * |\n   |**** |\n   |   * |\n   +-----+ */\n0x9000,\n0x9000,\n0x9000,\n0x9000,\n0x9000,\n0xf000,\n0x1000,\n\n/* Character 1063 (0x427):\n   width 5\n   +-----+\n   |*  * |\n   |*  * |\n   |*  * |\n   | *** |\n   |   * |\n   |   * |\n   |     |\n   +-----+ */\n0x9000,\n0x9000,\n0x9000,\n0x7000,\n0x1000,\n0x1000,\n0x0000,\n\n/* Character 1064 (0x428):\n   width 5\n   +-----+\n   |* * *|\n   |* * *|\n   |* * *|\n   |* * *|\n   |* * *|\n   |*****|\n   |     |\n   +-----+ */\n0xa800,\n0xa800,\n0xa800,\n0xa800,\n0xa800,\n0xf800,\n0x0000,\n\n/* Character 1065 (0x429):\n   width 5\n   +-----+\n   |* * *|\n   |* * *|\n   |* * *|\n   |* * *|\n   |* * *|\n   |*****|\n   |    *|\n   +-----+ */\n0xa800,\n0xa800,\n0xa800,\n0xa800,\n0xa800,\n0xf800,\n0x0800,\n\n/* Character 1066 (0x42a):\n   width 5\n   +-----+\n   |**   |\n   | *   |\n   | **  |\n   | * * |\n   | * * |\n   | **  |\n   |     |\n   +-----+ */\n0xc000,\n0x4000,\n0x6000,\n0x5000,\n0x5000,\n0x6000,\n0x0000,\n\n/* Character 1067 (0x42b):\n   width 5\n   +-----+\n   |*  * |\n   |*  * |\n   |** * |\n   |* ** |\n   |* ** |\n   |** * |\n   |     |\n   +-----+ */\n0x9000,\n0x9000,\n0xd000,\n0xb000,\n0xb000,\n0xd000,\n0x0000,\n\n/* Character 1068 (0x42c):\n   width 5\n   +-----+\n   |*    |\n   |*    |\n   |***  |\n   |*  * |\n   |*  * |\n   |***  |\n   |     |\n   +-----+ */\n0x8000,\n0x8000,\n0xe000,\n0x9000,\n0x9000,\n0xe000,\n0x0000,\n\n/* Character 1069 (0x42d):\n   width 5\n   +-----+\n   | **  |\n   |*  * |\n   |  ** |\n   |   * |\n   |*  * |\n   | **  |\n   |     |\n   +-----+ */\n0x6000,\n0x9000,\n0x3000,\n0x1000,\n0x9000,\n0x6000,\n0x0000,\n\n/* Character 1070 (0x42e):\n   width 5\n   +-----+\n   |* *  |\n   |** * |\n   |** * |\n   |** * |\n   |** * |\n   |* *  |\n   |     |\n   +-----+ */\n0xa000,\n0xd000,\n0xd000,\n0xd000,\n0xd000,\n0xa000,\n0x0000,\n\n/* Character 1071 (0x42f):\n   width 5\n   +-----+\n   | *** |\n   |*  * |\n   |*  * |\n   | *** |\n   | * * |\n   |*  * |\n   |     |\n   +-----+ */\n0x7000,\n0x9000,\n0x9000,\n0x7000,\n0x5000,\n0x9000,\n0x0000,\n\n/* Character 1072 (0x430):\n   width 5\n   +-----+\n   |     |\n   |     |\n   | *** |\n   |*  * |\n   |* ** |\n   | * * |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x7000,\n0x9000,\n0xb000,\n0x5000,\n0x0000,\n\n/* Character 1073 (0x431):\n   width 5\n   +-----+\n   |     |\n   | **  |\n   |*    |\n   |***  |\n   |*  * |\n   | **  |\n   |     |\n   +-----+ */\n0x0000,\n0x6000,\n0x8000,\n0xe000,\n0x9000,\n0x6000,\n0x0000,\n\n/* Character 1074 (0x432):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |***  |\n   |***  |\n   |*  * |\n   |***  |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0xe000,\n0xe000,\n0x9000,\n0xe000,\n0x0000,\n\n/* Character 1075 (0x433):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |**** |\n   |*    |\n   |*    |\n   |*    |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0xf000,\n0x8000,\n0x8000,\n0x8000,\n0x0000,\n\n/* Character 1076 (0x434):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |  ** |\n   | * * |\n   | * * |\n   |**** |\n   |*  * |\n   +-----+ */\n0x0000,\n0x0000,\n0x3000,\n0x5000,\n0x5000,\n0xf000,\n0x9000,\n\n/* Character 1077 (0x435):\n   width 5\n   +-----+\n   |     |\n   |     |\n   | **  |\n   |* ** |\n   |**   |\n   | **  |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x6000,\n0xb000,\n0xc000,\n0x6000,\n0x0000,\n\n/* Character 1078 (0x436):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |* * *|\n   | *** |\n   | *** |\n   |* * *|\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0xa800,\n0x7000,\n0x7000,\n0xa800,\n0x0000,\n\n/* Character 1079 (0x437):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |***  |\n   | **  |\n   |  *  |\n   |**   |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0xe000,\n0x6000,\n0x2000,\n0xc000,\n0x0000,\n\n/* Character 1080 (0x438):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |*  * |\n   |* ** |\n   |** * |\n   |*  * |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x9000,\n0xb000,\n0xd000,\n0x9000,\n0x0000,\n\n/* Character 1081 (0x439):\n   width 5\n   +-----+\n   |*  * |\n   | **  |\n   |*  * |\n   |* ** |\n   |** * |\n   |*  * |\n   |     |\n   +-----+ */\n0x9000,\n0x6000,\n0x9000,\n0xb000,\n0xd000,\n0x9000,\n0x0000,\n\n/* Character 1082 (0x43a):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |*  * |\n   |***  |\n   |* *  |\n   |*  * |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x9000,\n0xe000,\n0xa000,\n0x9000,\n0x0000,\n\n/* Character 1083 (0x43b):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |  ** |\n   | * * |\n   | * * |\n   |*  * |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x3000,\n0x5000,\n0x5000,\n0x9000,\n0x0000,\n\n/* Character 1084 (0x43c):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |*   *|\n   |** **|\n   |* * *|\n   |* * *|\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x8800,\n0xd800,\n0xa800,\n0xa800,\n0x0000,\n\n/* Character 1085 (0x43d):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |*  * |\n   |**** |\n   |*  * |\n   |*  * |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x9000,\n0xf000,\n0x9000,\n0x9000,\n0x0000,\n\n/* Character 1086 (0x43e):\n   width 5\n   +-----+\n   |     |\n   |     |\n   | **  |\n   |*  * |\n   |*  * |\n   | **  |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x6000,\n0x9000,\n0x9000,\n0x6000,\n0x0000,\n\n/* Character 1087 (0x43f):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |**** |\n   |*  * |\n   |*  * |\n   |*  * |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0xf000,\n0x9000,\n0x9000,\n0x9000,\n0x0000,\n\n/* Character 1088 (0x440):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |***  |\n   |*  * |\n   |*  * |\n   |***  |\n   |*    |\n   +-----+ */\n0x0000,\n0x0000,\n0xe000,\n0x9000,\n0x9000,\n0xe000,\n0x8000,\n\n/* Character 1089 (0x441):\n   width 5\n   +-----+\n   |     |\n   |     |\n   | **  |\n   |*    |\n   |*    |\n   | **  |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x6000,\n0x8000,\n0x8000,\n0x6000,\n0x0000,\n\n/* Character 1090 (0x442):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |***  |\n   | *   |\n   | *   |\n   | *   |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0xe000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n\n/* Character 1091 (0x443):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |*  * |\n   |*  * |\n   | * * |\n   |  *  |\n   | *   |\n   +-----+ */\n0x0000,\n0x0000,\n0x9000,\n0x9000,\n0x5000,\n0x2000,\n0x4000,\n\n/* Character 1092 (0x444):\n   width 5\n   +-----+\n   | **  |\n   |  *  |\n   |  *  |\n   | *** |\n   | * * |\n   | *** |\n   |  *  |\n   +-----+ */\n0x6000,\n0x2000,\n0x2000,\n0x7000,\n0x5000,\n0x7000,\n0x2000,\n\n/* Character 1093 (0x445):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |*  * |\n   | **  |\n   | **  |\n   |*  * |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x9000,\n0x6000,\n0x6000,\n0x9000,\n0x0000,\n\n/* Character 1094 (0x446):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |*  * |\n   |*  * |\n   |*  * |\n   |**** |\n   |   * |\n   +-----+ */\n0x0000,\n0x0000,\n0x9000,\n0x9000,\n0x9000,\n0xf000,\n0x1000,\n\n/* Character 1095 (0x447):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |*  * |\n   |*  * |\n   | *** |\n   |   * |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x9000,\n0x9000,\n0x7000,\n0x1000,\n0x0000,\n\n/* Character 1096 (0x448):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |* * *|\n   |* * *|\n   |* * *|\n   |*****|\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0xa800,\n0xa800,\n0xa800,\n0xf800,\n0x0000,\n\n/* Character 1097 (0x449):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |* * *|\n   |* * *|\n   |* * *|\n   |*****|\n   |    *|\n   +-----+ */\n0x0000,\n0x0000,\n0xa800,\n0xa800,\n0xa800,\n0xf800,\n0x0800,\n\n/* Character 1098 (0x44a):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |**   |\n   | **  |\n   | * * |\n   | **  |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0xc000,\n0x6000,\n0x5000,\n0x6000,\n0x0000,\n\n/* Character 1099 (0x44b):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |*  * |\n   |** * |\n   |* ** |\n   |** * |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x9000,\n0xd000,\n0xb000,\n0xd000,\n0x0000,\n\n/* Character 1100 (0x44c):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |*    |\n   |***  |\n   |*  * |\n   |***  |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x8000,\n0xe000,\n0x9000,\n0xe000,\n0x0000,\n\n/* Character 1101 (0x44d):\n   width 5\n   +-----+\n   |     |\n   |     |\n   | **  |\n   |  ** |\n   |   * |\n   | **  |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x6000,\n0x3000,\n0x1000,\n0x6000,\n0x0000,\n\n/* Character 1102 (0x44e):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |* *  |\n   |** * |\n   |** * |\n   |* *  |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0xa000,\n0xd000,\n0xd000,\n0xa000,\n0x0000,\n\n/* Character 1103 (0x44f):\n   width 5\n   +-----+\n   |     |\n   |     |\n   | **  |\n   |* *  |\n   | **  |\n   |* *  |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x6000,\n0xa000,\n0x6000,\n0xa000,\n0x0000,\n};\n\n/* Character->glyph mapping. */\nstatic const unsigned short _5x7_offset[] = {\n  0,\t/* (0x00) */\n  0,\t/* (0x01) */\n  0,\t/* (0x02) */\n  0,\t/* (0x03) */\n  0,\t/* (0x04) */\n  0,\t/* (0x05) */\n  0,\t/* (0x06) */\n  0,\t/* (0x07) */\n  0,\t/* (0x08) */\n  0,\t/* (0x09) */\n  0,\t/* (0x0a) */\n  0,\t/* (0x0b) */\n  0,\t/* (0x0c) */\n  0,\t/* (0x0d) */\n  0,\t/* (0x0e) */\n  0,\t/* (0x0f) */\n  0,\t/* (0x10) */\n  0,\t/* (0x11) */\n  0,\t/* (0x12) */\n  0,\t/* (0x13) */\n  0,\t/* (0x14) */\n  0,\t/* (0x15) */\n  0,\t/* (0x16) */\n  0,\t/* (0x17) */\n  0,\t/* (0x18) */\n  0,\t/* (0x19) */\n  0,\t/* (0x1a) */\n  0,\t/* (0x1b) */\n  0,\t/* (0x1c) */\n  0,\t/* (0x1d) */\n  0,\t/* (0x1e) */\n  0,\t/* (0x1f) */\n  7,\t/* (0x20) */\n  14,\t/* (0x21) */\n  21,\t/* (0x22) */\n  28,\t/* (0x23) */\n  35,\t/* (0x24) */\n  42,\t/* (0x25) */\n  49,\t/* (0x26) */\n  56,\t/* (0x27) */\n  63,\t/* (0x28) */\n  70,\t/* (0x29) */\n  77,\t/* (0x2a) */\n  84,\t/* (0x2b) */\n  91,\t/* (0x2c) */\n  98,\t/* (0x2d) */\n  105,\t/* (0x2e) */\n  112,\t/* (0x2f) */\n  119,\t/* (0x30) */\n  126,\t/* (0x31) */\n  133,\t/* (0x32) */\n  140,\t/* (0x33) */\n  147,\t/* (0x34) */\n  154,\t/* (0x35) */\n  161,\t/* (0x36) */\n  168,\t/* (0x37) */\n  175,\t/* (0x38) */\n  182,\t/* (0x39) */\n  189,\t/* (0x3a) */\n  196,\t/* (0x3b) */\n  203,\t/* (0x3c) */\n  210,\t/* (0x3d) */\n  217,\t/* (0x3e) */\n  224,\t/* (0x3f) */\n  231,\t/* (0x40) */\n  238,\t/* (0x41) */\n  245,\t/* (0x42) */\n  252,\t/* (0x43) */\n  259,\t/* (0x44) */\n  266,\t/* (0x45) */\n  273,\t/* (0x46) */\n  280,\t/* (0x47) */\n  287,\t/* (0x48) */\n  294,\t/* (0x49) */\n  301,\t/* (0x4a) */\n  308,\t/* (0x4b) */\n  315,\t/* (0x4c) */\n  322,\t/* (0x4d) */\n  329,\t/* (0x4e) */\n  336,\t/* (0x4f) */\n  343,\t/* (0x50) */\n  350,\t/* (0x51) */\n  357,\t/* (0x52) */\n  364,\t/* (0x53) */\n  371,\t/* (0x54) */\n  378,\t/* (0x55) */\n  385,\t/* (0x56) */\n  392,\t/* (0x57) */\n  399,\t/* (0x58) */\n  406,\t/* (0x59) */\n  413,\t/* (0x5a) */\n  420,\t/* (0x5b) */\n  427,\t/* (0x5c) */\n  434,\t/* (0x5d) */\n  441,\t/* (0x5e) */\n  448,\t/* (0x5f) */\n  455,\t/* (0x60) */\n  462,\t/* (0x61) */\n  469,\t/* (0x62) */\n  476,\t/* (0x63) */\n  483,\t/* (0x64) */\n  490,\t/* (0x65) */\n  497,\t/* (0x66) */\n  504,\t/* (0x67) */\n  511,\t/* (0x68) */\n  518,\t/* (0x69) */\n  525,\t/* (0x6a) */\n  532,\t/* (0x6b) */\n  539,\t/* (0x6c) */\n  546,\t/* (0x6d) */\n  553,\t/* (0x6e) */\n  560,\t/* (0x6f) */\n  567,\t/* (0x70) */\n  574,\t/* (0x71) */\n  581,\t/* (0x72) */\n  588,\t/* (0x73) */\n  595,\t/* (0x74) */\n  602,\t/* (0x75) */\n  609,\t/* (0x76) */\n  616,\t/* (0x77) */\n  623,\t/* (0x78) */\n  630,\t/* (0x79) */\n  637,\t/* (0x7a) */\n  644,\t/* (0x7b) */\n  651,\t/* (0x7c) */\n  658,\t/* (0x7d) */\n  665,\t/* (0x7e) */\n  0,\t/* (0x7f) */\n  0,\t/* (0x80) */\n  0,\t/* (0x81) */\n  0,\t/* (0x82) */\n  0,\t/* (0x83) */\n  0,\t/* (0x84) */\n  0,\t/* (0x85) */\n  0,\t/* (0x86) */\n  0,\t/* (0x87) */\n  0,\t/* (0x88) */\n  0,\t/* (0x89) */\n  0,\t/* (0x8a) */\n  0,\t/* (0x8b) */\n  0,\t/* (0x8c) */\n  0,\t/* (0x8d) */\n  0,\t/* (0x8e) */\n  0,\t/* (0x8f) */\n  0,\t/* (0x90) */\n  0,\t/* (0x91) */\n  0,\t/* (0x92) */\n  0,\t/* (0x93) */\n  0,\t/* (0x94) */\n  0,\t/* (0x95) */\n  0,\t/* (0x96) */\n  0,\t/* (0x97) */\n  0,\t/* (0x98) */\n  0,\t/* (0x99) */\n  0,\t/* (0x9a) */\n  0,\t/* (0x9b) */\n  0,\t/* (0x9c) */\n  0,\t/* (0x9d) */\n  0,\t/* (0x9e) */\n  0,\t/* (0x9f) */\n  0,\t/* (0xa0) */\n  0,\t/* (0xa1) */\n  0,\t/* (0xa2) */\n  0,\t/* (0xa3) */\n  0,\t/* (0xa4) */\n  0,\t/* (0xa5) */\n  0,\t/* (0xa6) */\n  0,\t/* (0xa7) */\n  0,\t/* (0xa8) */\n  0,\t/* (0xa9) */\n  0,\t/* (0xaa) */\n  0,\t/* (0xab) */\n  0,\t/* (0xac) */\n  0,\t/* (0xad) */\n  0,\t/* (0xae) */\n  0,\t/* (0xaf) */\n  0,\t/* (0xb0) */\n  0,\t/* (0xb1) */\n  0,\t/* (0xb2) */\n  0,\t/* (0xb3) */\n  0,\t/* (0xb4) */\n  0,\t/* (0xb5) */\n  0,\t/* (0xb6) */\n  0,\t/* (0xb7) */\n  0,\t/* (0xb8) */\n  0,\t/* (0xb9) */\n  0,\t/* (0xba) */\n  0,\t/* (0xbb) */\n  0,\t/* (0xbc) */\n  0,\t/* (0xbd) */\n  0,\t/* (0xbe) */\n  0,\t/* (0xbf) */\n  0,\t/* (0xc0) */\n  0,\t/* (0xc1) */\n  0,\t/* (0xc2) */\n  0,\t/* (0xc3) */\n  0,\t/* (0xc4) */\n  0,\t/* (0xc5) */\n  0,\t/* (0xc6) */\n  0,\t/* (0xc7) */\n  0,\t/* (0xc8) */\n  0,\t/* (0xc9) */\n  0,\t/* (0xca) */\n  0,\t/* (0xcb) */\n  0,\t/* (0xcc) */\n  0,\t/* (0xcd) */\n  0,\t/* (0xce) */\n  0,\t/* (0xcf) */\n  0,\t/* (0xd0) */\n  0,\t/* (0xd1) */\n  0,\t/* (0xd2) */\n  0,\t/* (0xd3) */\n  0,\t/* (0xd4) */\n  0,\t/* (0xd5) */\n  0,\t/* (0xd6) */\n  0,\t/* (0xd7) */\n  0,\t/* (0xd8) */\n  0,\t/* (0xd9) */\n  0,\t/* (0xda) */\n  0,\t/* (0xdb) */\n  0,\t/* (0xdc) */\n  0,\t/* (0xdd) */\n  0,\t/* (0xde) */\n  0,\t/* (0xdf) */\n  0,\t/* (0xe0) */\n  0,\t/* (0xe1) */\n  0,\t/* (0xe2) */\n  0,\t/* (0xe3) */\n  0,\t/* (0xe4) */\n  0,\t/* (0xe5) */\n  0,\t/* (0xe6) */\n  0,\t/* (0xe7) */\n  0,\t/* (0xe8) */\n  0,\t/* (0xe9) */\n  0,\t/* (0xea) */\n  0,\t/* (0xeb) */\n  0,\t/* (0xec) */\n  0,\t/* (0xed) */\n  0,\t/* (0xee) */\n  0,\t/* (0xef) */\n  0,\t/* (0xf0) */\n  0,\t/* (0xf1) */\n  0,\t/* (0xf2) */\n  0,\t/* (0xf3) */\n  0,\t/* (0xf4) */\n  0,\t/* (0xf5) */\n  0,\t/* (0xf6) */\n  0,\t/* (0xf7) */\n  0,\t/* (0xf8) */\n  0,\t/* (0xf9) */\n  0,\t/* (0xfa) */\n  0,\t/* (0xfb) */\n  0,\t/* (0xfc) */\n  0,\t/* (0xfd) */\n  0,\t/* (0xfe) */\n  0,\t/* (0xff) */\n  0,\t/* (0x100) */\n  0,\t/* (0x101) */\n  0,\t/* (0x102) */\n  0,\t/* (0x103) */\n  0,\t/* (0x104) */\n  0,\t/* (0x105) */\n  0,\t/* (0x106) */\n  0,\t/* (0x107) */\n  0,\t/* (0x108) */\n  0,\t/* (0x109) */\n  0,\t/* (0x10a) */\n  0,\t/* (0x10b) */\n  0,\t/* (0x10c) */\n  0,\t/* (0x10d) */\n  0,\t/* (0x10e) */\n  0,\t/* (0x10f) */\n  0,\t/* (0x110) */\n  0,\t/* (0x111) */\n  0,\t/* (0x112) */\n  0,\t/* (0x113) */\n  0,\t/* (0x114) */\n  0,\t/* (0x115) */\n  0,\t/* (0x116) */\n  0,\t/* (0x117) */\n  0,\t/* (0x118) */\n  0,\t/* (0x119) */\n  0,\t/* (0x11a) */\n  0,\t/* (0x11b) */\n  0,\t/* (0x11c) */\n  0,\t/* (0x11d) */\n  0,\t/* (0x11e) */\n  0,\t/* (0x11f) */\n  0,\t/* (0x120) */\n  0,\t/* (0x121) */\n  0,\t/* (0x122) */\n  0,\t/* (0x123) */\n  0,\t/* (0x124) */\n  0,\t/* (0x125) */\n  0,\t/* (0x126) */\n  0,\t/* (0x127) */\n  0,\t/* (0x128) */\n  0,\t/* (0x129) */\n  0,\t/* (0x12a) */\n  0,\t/* (0x12b) */\n  0,\t/* (0x12c) */\n  0,\t/* (0x12d) */\n  0,\t/* (0x12e) */\n  0,\t/* (0x12f) */\n  0,\t/* (0x130) */\n  0,\t/* (0x131) */\n  0,\t/* (0x132) */\n  0,\t/* (0x133) */\n  0,\t/* (0x134) */\n  0,\t/* (0x135) */\n  0,\t/* (0x136) */\n  0,\t/* (0x137) */\n  0,\t/* (0x138) */\n  0,\t/* (0x139) */\n  0,\t/* (0x13a) */\n  0,\t/* (0x13b) */\n  0,\t/* (0x13c) */\n  0,\t/* (0x13d) */\n  0,\t/* (0x13e) */\n  0,\t/* (0x13f) */\n  0,\t/* (0x140) */\n  0,\t/* (0x141) */\n  0,\t/* (0x142) */\n  0,\t/* (0x143) */\n  0,\t/* (0x144) */\n  0,\t/* (0x145) */\n  0,\t/* (0x146) */\n  0,\t/* (0x147) */\n  0,\t/* (0x148) */\n  0,\t/* (0x149) */\n  0,\t/* (0x14a) */\n  0,\t/* (0x14b) */\n  0,\t/* (0x14c) */\n  0,\t/* (0x14d) */\n  0,\t/* (0x14e) */\n  0,\t/* (0x14f) */\n  0,\t/* (0x150) */\n  0,\t/* (0x151) */\n  0,\t/* (0x152) */\n  0,\t/* (0x153) */\n  0,\t/* (0x154) */\n  0,\t/* (0x155) */\n  0,\t/* (0x156) */\n  0,\t/* (0x157) */\n  0,\t/* (0x158) */\n  0,\t/* (0x159) */\n  0,\t/* (0x15a) */\n  0,\t/* (0x15b) */\n  0,\t/* (0x15c) */\n  0,\t/* (0x15d) */\n  0,\t/* (0x15e) */\n  0,\t/* (0x15f) */\n  0,\t/* (0x160) */\n  0,\t/* (0x161) */\n  0,\t/* (0x162) */\n  0,\t/* (0x163) */\n  0,\t/* (0x164) */\n  0,\t/* (0x165) */\n  0,\t/* (0x166) */\n  0,\t/* (0x167) */\n  0,\t/* (0x168) */\n  0,\t/* (0x169) */\n  0,\t/* (0x16a) */\n  0,\t/* (0x16b) */\n  0,\t/* (0x16c) */\n  0,\t/* (0x16d) */\n  0,\t/* (0x16e) */\n  0,\t/* (0x16f) */\n  0,\t/* (0x170) */\n  0,\t/* (0x171) */\n  0,\t/* (0x172) */\n  0,\t/* (0x173) */\n  0,\t/* (0x174) */\n  0,\t/* (0x175) */\n  0,\t/* (0x176) */\n  0,\t/* (0x177) */\n  0,\t/* (0x178) */\n  0,\t/* (0x179) */\n  0,\t/* (0x17a) */\n  0,\t/* (0x17b) */\n  0,\t/* (0x17c) */\n  0,\t/* (0x17d) */\n  0,\t/* (0x17e) */\n  0,\t/* (0x17f) */\n  0,\t/* (0x180) */\n  0,\t/* (0x181) */\n  0,\t/* (0x182) */\n  0,\t/* (0x183) */\n  0,\t/* (0x184) */\n  0,\t/* (0x185) */\n  0,\t/* (0x186) */\n  0,\t/* (0x187) */\n  0,\t/* (0x188) */\n  0,\t/* (0x189) */\n  0,\t/* (0x18a) */\n  0,\t/* (0x18b) */\n  0,\t/* (0x18c) */\n  0,\t/* (0x18d) */\n  0,\t/* (0x18e) */\n  0,\t/* (0x18f) */\n  0,\t/* (0x190) */\n  0,\t/* (0x191) */\n  0,\t/* (0x192) */\n  0,\t/* (0x193) */\n  0,\t/* (0x194) */\n  0,\t/* (0x195) */\n  0,\t/* (0x196) */\n  0,\t/* (0x197) */\n  0,\t/* (0x198) */\n  0,\t/* (0x199) */\n  0,\t/* (0x19a) */\n  0,\t/* (0x19b) */\n  0,\t/* (0x19c) */\n  0,\t/* (0x19d) */\n  0,\t/* (0x19e) */\n  0,\t/* (0x19f) */\n  0,\t/* (0x1a0) */\n  0,\t/* (0x1a1) */\n  0,\t/* (0x1a2) */\n  0,\t/* (0x1a3) */\n  0,\t/* (0x1a4) */\n  0,\t/* (0x1a5) */\n  0,\t/* (0x1a6) */\n  0,\t/* (0x1a7) */\n  0,\t/* (0x1a8) */\n  0,\t/* (0x1a9) */\n  0,\t/* (0x1aa) */\n  0,\t/* (0x1ab) */\n  0,\t/* (0x1ac) */\n  0,\t/* (0x1ad) */\n  0,\t/* (0x1ae) */\n  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0,\t/* (0x38a) */\n  0,\t/* (0x38b) */\n  0,\t/* (0x38c) */\n  0,\t/* (0x38d) */\n  0,\t/* (0x38e) */\n  0,\t/* (0x38f) */\n  0,\t/* (0x390) */\n  0,\t/* (0x391) */\n  0,\t/* (0x392) */\n  0,\t/* (0x393) */\n  0,\t/* (0x394) */\n  0,\t/* (0x395) */\n  0,\t/* (0x396) */\n  0,\t/* (0x397) */\n  0,\t/* (0x398) */\n  0,\t/* (0x399) */\n  0,\t/* (0x39a) */\n  0,\t/* (0x39b) */\n  0,\t/* (0x39c) */\n  0,\t/* (0x39d) */\n  0,\t/* (0x39e) */\n  0,\t/* (0x39f) */\n  0,\t/* (0x3a0) */\n  0,\t/* (0x3a1) */\n  0,\t/* (0x3a2) */\n  0,\t/* (0x3a3) */\n  0,\t/* (0x3a4) */\n  0,\t/* (0x3a5) */\n  0,\t/* (0x3a6) */\n  0,\t/* (0x3a7) */\n  0,\t/* (0x3a8) */\n  0,\t/* (0x3a9) */\n  0,\t/* (0x3aa) */\n  0,\t/* (0x3ab) */\n  0,\t/* (0x3ac) */\n  0,\t/* (0x3ad) */\n  0,\t/* (0x3ae) */\n  0,\t/* (0x3af) */\n  0,\t/* (0x3b0) */\n  0,\t/* (0x3b1) */\n  0,\t/* (0x3b2) */\n  0,\t/* (0x3b3) */\n  0,\t/* (0x3b4) */\n  0,\t/* (0x3b5) */\n  0,\t/* (0x3b6) */\n  0,\t/* (0x3b7) */\n  0,\t/* (0x3b8) */\n  0,\t/* (0x3b9) */\n  0,\t/* (0x3ba) */\n  0,\t/* (0x3bb) */\n  0,\t/* (0x3bc) */\n  0,\t/* (0x3bd) */\n  0,\t/* (0x3be) */\n  0,\t/* (0x3bf) */\n  0,\t/* (0x3c0) */\n  0,\t/* (0x3c1) */\n  0,\t/* (0x3c2) */\n  0,\t/* (0x3c3) */\n  0,\t/* (0x3c4) */\n  0,\t/* (0x3c5) */\n  0,\t/* (0x3c6) */\n  0,\t/* (0x3c7) */\n  0,\t/* (0x3c8) */\n  0,\t/* (0x3c9) */\n  0,\t/* (0x3ca) */\n  0,\t/* (0x3cb) */\n  0,\t/* (0x3cc) */\n  0,\t/* (0x3cd) */\n  0,\t/* (0x3ce) */\n  0,\t/* (0x3cf) */\n  0,\t/* (0x3d0) */\n  0,\t/* (0x3d1) */\n  0,\t/* (0x3d2) */\n  0,\t/* (0x3d3) */\n  0,\t/* (0x3d4) */\n  0,\t/* (0x3d5) */\n  0,\t/* (0x3d6) */\n  0,\t/* (0x3d7) */\n  0,\t/* (0x3d8) */\n  0,\t/* (0x3d9) */\n  0,\t/* (0x3da) */\n  0,\t/* (0x3db) */\n  0,\t/* (0x3dc) */\n  0,\t/* (0x3dd) */\n  0,\t/* (0x3de) */\n  0,\t/* (0x3df) */\n  0,\t/* (0x3e0) */\n  0,\t/* (0x3e1) */\n  0,\t/* (0x3e2) */\n  0,\t/* (0x3e3) */\n  0,\t/* (0x3e4) */\n  0,\t/* (0x3e5) */\n  0,\t/* (0x3e6) */\n  0,\t/* (0x3e7) */\n  0,\t/* (0x3e8) */\n  0,\t/* (0x3e9) */\n  0,\t/* (0x3ea) */\n  0,\t/* (0x3eb) */\n  0,\t/* (0x3ec) */\n  0,\t/* (0x3ed) */\n  0,\t/* (0x3ee) */\n  0,\t/* (0x3ef) */\n  0,\t/* (0x3f0) */\n  0,\t/* (0x3f1) */\n  0,\t/* (0x3f2) */\n  0,\t/* (0x3f3) */\n  0,\t/* (0x3f4) */\n  0,\t/* (0x3f5) */\n  0,\t/* (0x3f6) */\n  0,\t/* (0x3f7) */\n  0,\t/* (0x3f8) */\n  0,\t/* (0x3f9) */\n  0,\t/* (0x3fa) */\n  0,\t/* (0x3fb) */\n  0,\t/* (0x3fc) */\n  0,\t/* (0x3fd) */\n  0,\t/* (0x3fe) */\n  0,\t/* (0x3ff) */\n  0,\t/* (0x400) */\n  0,\t/* (0x401) */\n  0,\t/* (0x402) */\n  0,\t/* (0x403) */\n  0,\t/* (0x404) */\n  0,\t/* (0x405) */\n  0,\t/* (0x406) */\n  0,\t/* (0x407) */\n  0,\t/* (0x408) */\n  0,\t/* (0x409) */\n  0,\t/* (0x40a) */\n  0,\t/* (0x40b) */\n  0,\t/* (0x40c) */\n  0,\t/* (0x40d) */\n  0,\t/* (0x40e) */\n  0,\t/* (0x40f) */\n  672,\t/* (0x410) */\n  679,\t/* (0x411) */\n  686,\t/* (0x412) */\n  693,\t/* (0x413) */\n  700,\t/* (0x414) */\n  707,\t/* (0x415) */\n  714,\t/* (0x416) */\n  721,\t/* (0x417) */\n  728,\t/* (0x418) */\n  735,\t/* (0x419) */\n  742,\t/* (0x41a) */\n  749,\t/* (0x41b) */\n  756,\t/* (0x41c) */\n  763,\t/* (0x41d) */\n  770,\t/* (0x41e) */\n  777,\t/* (0x41f) */\n  784,\t/* (0x420) */\n  791,\t/* (0x421) */\n  798,\t/* (0x422) */\n  805,\t/* (0x423) */\n  812,\t/* (0x424) */\n  819,\t/* (0x425) */\n  826,\t/* (0x426) */\n  833,\t/* (0x427) */\n  840,\t/* (0x428) */\n  847,\t/* (0x429) */\n  854,\t/* (0x42a) */\n  861,\t/* (0x42b) */\n  868,\t/* (0x42c) */\n  875,\t/* (0x42d) */\n  882,\t/* (0x42e) */\n  889,\t/* (0x42f) */\n  896,\t/* (0x430) */\n  903,\t/* (0x431) */\n  910,\t/* (0x432) */\n  917,\t/* (0x433) */\n  924,\t/* (0x434) */\n  931,\t/* (0x435) */\n  938,\t/* (0x436) */\n  945,\t/* (0x437) */\n  952,\t/* (0x438) */\n  959,\t/* (0x439) */\n  966,\t/* (0x43a) */\n  973,\t/* (0x43b) */\n  980,\t/* (0x43c) */\n  987,\t/* (0x43d) */\n  994,\t/* (0x43e) */\n  1001,\t/* (0x43f) */\n  1008,\t/* (0x440) */\n  1015,\t/* (0x441) */\n  1022,\t/* (0x442) */\n  1029,\t/* (0x443) */\n  1036,\t/* (0x444) */\n  1043,\t/* (0x445) */\n  1050,\t/* (0x446) */\n  1057,\t/* (0x447) */\n  1064,\t/* (0x448) */\n  1071,\t/* (0x449) */\n  1078,\t/* (0x44a) */\n  1085,\t/* (0x44b) */\n  1092,\t/* (0x44c) */\n  1099,\t/* (0x44d) */\n  1106,\t/* (0x44e) */\n  1113,\t/* (0x44f) */\n};\n\n/* Exported structure definition. */\nconst struct gpanel_font_t font_5x7 = {\n  \"5x7\",\n  5,\n  7,\n  6,\n  0,\n  1104,\n  _5x7_bits,\n  _5x7_offset,\n  0,  /* fixed width*/\n  0,\n  sizeof(_5x7_bits) / sizeof(_5x7_bits[0]),\n};\n"
  },
  {
    "path": "share/examples/gpanel/fonts/6x9.c",
    "content": "/* Generated by convbdf on Thu Oct  8 21:26:35 2015. */\n#include <sys/gpanel.h>\n\n/* Font information:\n   name: 6x9\n   facename: -Misc-Fixed-Medium-R-Normal--9-90-75-75-C-60-ISO10646-1\n   w x h: 6x9\n   size: 1104\n   ascent: 7\n   descent: 2\n   first char: 0 (0x00)\n   last char: 1103 (0x44f)\n   default char: 0 (0x00)\n   proportional: no\n   Public domain font.  Share and enjoy.\n*/\n\n/* Font character bitmap data. */\nstatic const unsigned short _6x9_bits[] = {\n\n/* Character 0 (0x00):\n   width 6\n   +------+\n   |      |\n   |  * * |\n   | *    |\n   |    * |\n   | *    |\n   |    * |\n   | * *  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x2800,\n0x4000,\n0x0800,\n0x4000,\n0x0800,\n0x5000,\n0x0000,\n0x0000,\n\n/* Character 32 (0x20):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 33 (0x21):\n   width 6\n   +------+\n   |      |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |      |\n   |  *   |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x0000,\n0x2000,\n0x0000,\n0x0000,\n\n/* Character 34 (0x22):\n   width 6\n   +------+\n   |      |\n   | * *  |\n   | * *  |\n   | * *  |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x5000,\n0x5000,\n0x5000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 35 (0x23):\n   width 6\n   +------+\n   |      |\n   | * *  |\n   | * *  |\n   |***** |\n   | * *  |\n   |***** |\n   | * *  |\n   | * *  |\n   |      |\n   +------+ */\n0x0000,\n0x5000,\n0x5000,\n0xf800,\n0x5000,\n0xf800,\n0x5000,\n0x5000,\n0x0000,\n\n/* Character 36 (0x24):\n   width 6\n   +------+\n   |  *   |\n   | ***  |\n   |* * * |\n   |* *   |\n   | ***  |\n   |  * * |\n   |* * * |\n   | ***  |\n   |  *   |\n   +------+ */\n0x2000,\n0x7000,\n0xa800,\n0xa000,\n0x7000,\n0x2800,\n0xa800,\n0x7000,\n0x2000,\n\n/* Character 37 (0x25):\n   width 6\n   +------+\n   | *    |\n   |* * * |\n   | *  * |\n   |   *  |\n   |  *   |\n   | *  * |\n   | * * *|\n   |    * |\n   |      |\n   +------+ */\n0x4000,\n0xa800,\n0x4800,\n0x1000,\n0x2000,\n0x4800,\n0x5400,\n0x0800,\n0x0000,\n\n/* Character 38 (0x26):\n   width 6\n   +------+\n   |      |\n   | **   |\n   |*  *  |\n   |*  *  |\n   | **   |\n   |*  ** |\n   |*  *  |\n   | ** * |\n   |      |\n   +------+ */\n0x0000,\n0x6000,\n0x9000,\n0x9000,\n0x6000,\n0x9800,\n0x9000,\n0x6800,\n0x0000,\n\n/* Character 39 (0x27):\n   width 6\n   +------+\n   |      |\n   |  *   |\n   |  *   |\n   |  *   |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x2000,\n0x2000,\n0x2000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 40 (0x28):\n   width 6\n   +------+\n   |      |\n   |   *  |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |   *  |\n   |      |\n   +------+ */\n0x0000,\n0x1000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x1000,\n0x0000,\n\n/* Character 41 (0x29):\n   width 6\n   +------+\n   |      |\n   |  *   |\n   |   *  |\n   |   *  |\n   |   *  |\n   |   *  |\n   |   *  |\n   |  *   |\n   |      |\n   +------+ */\n0x0000,\n0x2000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x2000,\n0x0000,\n\n/* Character 42 (0x2a):\n   width 6\n   +------+\n   |      |\n   |      |\n   |*   * |\n   | * *  |\n   |***** |\n   | * *  |\n   |*   * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x8800,\n0x5000,\n0xf800,\n0x5000,\n0x8800,\n0x0000,\n0x0000,\n\n/* Character 43 (0x2b):\n   width 6\n   +------+\n   |      |\n   |      |\n   |  *   |\n   |  *   |\n   |***** |\n   |  *   |\n   |  *   |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x2000,\n0x2000,\n0xf800,\n0x2000,\n0x2000,\n0x0000,\n0x0000,\n\n/* Character 44 (0x2c):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |  **  |\n   |   *  |\n   |   *  |\n   |  *   |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x1000,\n0x1000,\n0x2000,\n\n/* Character 45 (0x2d):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |      |\n   |***** |\n   |      |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0xf800,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 46 (0x2e):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |  **  |\n   |  **  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x3000,\n0x0000,\n0x0000,\n\n/* Character 47 (0x2f):\n   width 6\n   +------+\n   |      |\n   |    * |\n   |    * |\n   |   *  |\n   |  *   |\n   | *    |\n   | *    |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0800,\n0x0800,\n0x1000,\n0x2000,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 48 (0x30):\n   width 6\n   +------+\n   |      |\n   |  **  |\n   | *  * |\n   | *  * |\n   | *  * |\n   | *  * |\n   |  **  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x3000,\n0x4800,\n0x4800,\n0x4800,\n0x4800,\n0x3000,\n0x0000,\n0x0000,\n\n/* Character 49 (0x31):\n   width 6\n   +------+\n   |      |\n   |  *   |\n   | **   |\n   |  *   |\n   |  *   |\n   |  *   |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x2000,\n0x6000,\n0x2000,\n0x2000,\n0x2000,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 50 (0x32):\n   width 6\n   +------+\n   |      |\n   |  **  |\n   | *  * |\n   |    * |\n   |   *  |\n   |  *   |\n   | **** |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x3000,\n0x4800,\n0x0800,\n0x1000,\n0x2000,\n0x7800,\n0x0000,\n0x0000,\n\n/* Character 51 (0x33):\n   width 6\n   +------+\n   |      |\n   | **** |\n   |   *  |\n   |  **  |\n   |    * |\n   |    * |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7800,\n0x1000,\n0x3000,\n0x0800,\n0x0800,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 52 (0x34):\n   width 6\n   +------+\n   |      |\n   |   *  |\n   |  **  |\n   | * *  |\n   |*  *  |\n   |***** |\n   |   *  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x1000,\n0x3000,\n0x5000,\n0x9000,\n0xf800,\n0x1000,\n0x0000,\n0x0000,\n\n/* Character 53 (0x35):\n   width 6\n   +------+\n   |      |\n   | **** |\n   | *    |\n   | ***  |\n   |    * |\n   |    * |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7800,\n0x4000,\n0x7000,\n0x0800,\n0x0800,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 54 (0x36):\n   width 6\n   +------+\n   |      |\n   |  **  |\n   | *    |\n   | ***  |\n   | *  * |\n   | *  * |\n   |  **  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x3000,\n0x4000,\n0x7000,\n0x4800,\n0x4800,\n0x3000,\n0x0000,\n0x0000,\n\n/* Character 55 (0x37):\n   width 6\n   +------+\n   |      |\n   | **** |\n   |    * |\n   |    * |\n   |   *  |\n   |  *   |\n   |  *   |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7800,\n0x0800,\n0x0800,\n0x1000,\n0x2000,\n0x2000,\n0x0000,\n0x0000,\n\n/* Character 56 (0x38):\n   width 6\n   +------+\n   |      |\n   |  **  |\n   | *  * |\n   |  **  |\n   | *  * |\n   | *  * |\n   |  **  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x3000,\n0x4800,\n0x3000,\n0x4800,\n0x4800,\n0x3000,\n0x0000,\n0x0000,\n\n/* Character 57 (0x39):\n   width 6\n   +------+\n   |      |\n   |  **  |\n   | *  * |\n   | *  * |\n   |  *** |\n   |    * |\n   |  **  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x3000,\n0x4800,\n0x4800,\n0x3800,\n0x0800,\n0x3000,\n0x0000,\n0x0000,\n\n/* Character 58 (0x3a):\n   width 6\n   +------+\n   |      |\n   |      |\n   |  **  |\n   |  **  |\n   |      |\n   |  **  |\n   |  **  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x3000,\n0x3000,\n0x0000,\n0x3000,\n0x3000,\n0x0000,\n0x0000,\n\n/* Character 59 (0x3b):\n   width 6\n   +------+\n   |      |\n   |      |\n   |  **  |\n   |  **  |\n   |      |\n   |  **  |\n   |   *  |\n   |   *  |\n   |  *   |\n   +------+ */\n0x0000,\n0x0000,\n0x3000,\n0x3000,\n0x0000,\n0x3000,\n0x1000,\n0x1000,\n0x2000,\n\n/* Character 60 (0x3c):\n   width 6\n   +------+\n   |      |\n   |      |\n   |   ** |\n   | **   |\n   |*     |\n   | **   |\n   |   ** |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x1800,\n0x6000,\n0x8000,\n0x6000,\n0x1800,\n0x0000,\n0x0000,\n\n/* Character 61 (0x3d):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |***** |\n   |      |\n   |***** |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0xf800,\n0x0000,\n0xf800,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 62 (0x3e):\n   width 6\n   +------+\n   |      |\n   |      |\n   |**    |\n   |  **  |\n   |    * |\n   |  **  |\n   |**    |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0xc000,\n0x3000,\n0x0800,\n0x3000,\n0xc000,\n0x0000,\n0x0000,\n\n/* Character 63 (0x3f):\n   width 6\n   +------+\n   |  **  |\n   | *  * |\n   |    * |\n   |  **  |\n   |  *   |\n   |      |\n   |  *   |\n   |      |\n   |      |\n   +------+ */\n0x3000,\n0x4800,\n0x0800,\n0x3000,\n0x2000,\n0x0000,\n0x2000,\n0x0000,\n0x0000,\n\n/* Character 64 (0x40):\n   width 6\n   +------+\n   |      |\n   | ***  |\n   |*  *  |\n   |* * * |\n   |* **  |\n   |*     |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7000,\n0x9000,\n0xa800,\n0xb000,\n0x8000,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 65 (0x41):\n   width 6\n   +------+\n   |      |\n   |  *   |\n   | * *  |\n   |*   * |\n   |***** |\n   |*   * |\n   |*   * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x2000,\n0x5000,\n0x8800,\n0xf800,\n0x8800,\n0x8800,\n0x0000,\n0x0000,\n\n/* Character 66 (0x42):\n   width 6\n   +------+\n   |      |\n   |****  |\n   |*   * |\n   |****  |\n   |*   * |\n   |*   * |\n   |****  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0xf000,\n0x8800,\n0xf000,\n0x8800,\n0x8800,\n0xf000,\n0x0000,\n0x0000,\n\n/* Character 67 (0x43):\n   width 6\n   +------+\n   |      |\n   |  **  |\n   | *  * |\n   | *    |\n   | *    |\n   | *  * |\n   |  **  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x3000,\n0x4800,\n0x4000,\n0x4000,\n0x4800,\n0x3000,\n0x0000,\n0x0000,\n\n/* Character 68 (0x44):\n   width 6\n   +------+\n   |      |\n   | ***  |\n   | *  * |\n   | *  * |\n   | *  * |\n   | *  * |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7000,\n0x4800,\n0x4800,\n0x4800,\n0x4800,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 69 (0x45):\n   width 6\n   +------+\n   |      |\n   | **** |\n   | *    |\n   | ***  |\n   | *    |\n   | *    |\n   | **** |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7800,\n0x4000,\n0x7000,\n0x4000,\n0x4000,\n0x7800,\n0x0000,\n0x0000,\n\n/* Character 70 (0x46):\n   width 6\n   +------+\n   |      |\n   | **** |\n   | *    |\n   | ***  |\n   | *    |\n   | *    |\n   | *    |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7800,\n0x4000,\n0x7000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 71 (0x47):\n   width 6\n   +------+\n   |      |\n   |  **  |\n   | *  * |\n   | *    |\n   | * ** |\n   | *  * |\n   |  **  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x3000,\n0x4800,\n0x4000,\n0x5800,\n0x4800,\n0x3000,\n0x0000,\n0x0000,\n\n/* Character 72 (0x48):\n   width 6\n   +------+\n   |      |\n   | *  * |\n   | *  * |\n   | **** |\n   | *  * |\n   | *  * |\n   | *  * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x4800,\n0x4800,\n0x7800,\n0x4800,\n0x4800,\n0x4800,\n0x0000,\n0x0000,\n\n/* Character 73 (0x49):\n   width 6\n   +------+\n   |      |\n   | ***  |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 74 (0x4a):\n   width 6\n   +------+\n   |      |\n   |  *** |\n   |   *  |\n   |   *  |\n   |   *  |\n   |*  *  |\n   | **   |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x3800,\n0x1000,\n0x1000,\n0x1000,\n0x9000,\n0x6000,\n0x0000,\n0x0000,\n\n/* Character 75 (0x4b):\n   width 6\n   +------+\n   |      |\n   | *  * |\n   | * *  |\n   | **   |\n   | * *  |\n   | *  * |\n   | *  * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x4800,\n0x5000,\n0x6000,\n0x5000,\n0x4800,\n0x4800,\n0x0000,\n0x0000,\n\n/* Character 76 (0x4c):\n   width 6\n   +------+\n   |      |\n   | *    |\n   | *    |\n   | *    |\n   | *    |\n   | *    |\n   | **** |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x7800,\n0x0000,\n0x0000,\n\n/* Character 77 (0x4d):\n   width 6\n   +------+\n   |      |\n   |*   * |\n   |** ** |\n   |* * * |\n   |* * * |\n   |*   * |\n   |*   * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x8800,\n0xd800,\n0xa800,\n0xa800,\n0x8800,\n0x8800,\n0x0000,\n0x0000,\n\n/* Character 78 (0x4e):\n   width 6\n   +------+\n   |      |\n   | *  * |\n   | ** * |\n   | * ** |\n   | *  * |\n   | *  * |\n   | *  * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x4800,\n0x6800,\n0x5800,\n0x4800,\n0x4800,\n0x4800,\n0x0000,\n0x0000,\n\n/* Character 79 (0x4f):\n   width 6\n   +------+\n   |      |\n   | ***  |\n   |*   * |\n   |*   * |\n   |*   * |\n   |*   * |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7000,\n0x8800,\n0x8800,\n0x8800,\n0x8800,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 80 (0x50):\n   width 6\n   +------+\n   |      |\n   | ***  |\n   | *  * |\n   | *  * |\n   | ***  |\n   | *    |\n   | *    |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7000,\n0x4800,\n0x4800,\n0x7000,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 81 (0x51):\n   width 6\n   +------+\n   |      |\n   |  **  |\n   | *  * |\n   | *  * |\n   | ** * |\n   | * ** |\n   |  **  |\n   |    * |\n   |      |\n   +------+ */\n0x0000,\n0x3000,\n0x4800,\n0x4800,\n0x6800,\n0x5800,\n0x3000,\n0x0800,\n0x0000,\n\n/* Character 82 (0x52):\n   width 6\n   +------+\n   |      |\n   | ***  |\n   | *  * |\n   | *  * |\n   | ***  |\n   | *  * |\n   | *  * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7000,\n0x4800,\n0x4800,\n0x7000,\n0x4800,\n0x4800,\n0x0000,\n0x0000,\n\n/* Character 83 (0x53):\n   width 6\n   +------+\n   |      |\n   |  **  |\n   | *  * |\n   |  *   |\n   |   *  |\n   | *  * |\n   |  **  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x3000,\n0x4800,\n0x2000,\n0x1000,\n0x4800,\n0x3000,\n0x0000,\n0x0000,\n\n/* Character 84 (0x54):\n   width 6\n   +------+\n   |      |\n   |***** |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0xf800,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x0000,\n0x0000,\n\n/* Character 85 (0x55):\n   width 6\n   +------+\n   |      |\n   | *  * |\n   | *  * |\n   | *  * |\n   | *  * |\n   | *  * |\n   |  **  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x4800,\n0x4800,\n0x4800,\n0x4800,\n0x4800,\n0x3000,\n0x0000,\n0x0000,\n\n/* Character 86 (0x56):\n   width 6\n   +------+\n   |      |\n   | *  * |\n   | *  * |\n   | *  * |\n   | **** |\n   |  **  |\n   |  **  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x4800,\n0x4800,\n0x4800,\n0x7800,\n0x3000,\n0x3000,\n0x0000,\n0x0000,\n\n/* Character 87 (0x57):\n   width 6\n   +------+\n   |      |\n   |*   * |\n   |*   * |\n   |* * * |\n   |* * * |\n   |** ** |\n   |*   * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x8800,\n0x8800,\n0xa800,\n0xa800,\n0xd800,\n0x8800,\n0x0000,\n0x0000,\n\n/* Character 88 (0x58):\n   width 6\n   +------+\n   |      |\n   |*   * |\n   | * *  |\n   |  *   |\n   |  *   |\n   | * *  |\n   |*   * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x8800,\n0x5000,\n0x2000,\n0x2000,\n0x5000,\n0x8800,\n0x0000,\n0x0000,\n\n/* Character 89 (0x59):\n   width 6\n   +------+\n   |      |\n   |*   * |\n   |*   * |\n   | * *  |\n   |  *   |\n   |  *   |\n   |  *   |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x8800,\n0x8800,\n0x5000,\n0x2000,\n0x2000,\n0x2000,\n0x0000,\n0x0000,\n\n/* Character 90 (0x5a):\n   width 6\n   +------+\n   |      |\n   | **** |\n   |    * |\n   |   *  |\n   |  *   |\n   | *    |\n   | **** |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7800,\n0x0800,\n0x1000,\n0x2000,\n0x4000,\n0x7800,\n0x0000,\n0x0000,\n\n/* Character 91 (0x5b):\n   width 6\n   +------+\n   |      |\n   | ***  |\n   | *    |\n   | *    |\n   | *    |\n   | *    |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 92 (0x5c):\n   width 6\n   +------+\n   |      |\n   | *    |\n   | *    |\n   |  *   |\n   |   *  |\n   |    * |\n   |    * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x4000,\n0x4000,\n0x2000,\n0x1000,\n0x0800,\n0x0800,\n0x0000,\n0x0000,\n\n/* Character 93 (0x5d):\n   width 6\n   +------+\n   |      |\n   | ***  |\n   |   *  |\n   |   *  |\n   |   *  |\n   |   *  |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 94 (0x5e):\n   width 6\n   +------+\n   |      |\n   |  *   |\n   | * *  |\n   |*   * |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x2000,\n0x5000,\n0x8800,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 95 (0x5f):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |***** |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0xf800,\n\n/* Character 96 (0x60):\n   width 6\n   +------+\n   |      |\n   |  *   |\n   |   *  |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x2000,\n0x1000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 97 (0x61):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |  *** |\n   | *  * |\n   | *  * |\n   |  *** |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3800,\n0x4800,\n0x4800,\n0x3800,\n0x0000,\n0x0000,\n\n/* Character 98 (0x62):\n   width 6\n   +------+\n   |      |\n   | *    |\n   | *    |\n   | ***  |\n   | *  * |\n   | *  * |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x4000,\n0x4000,\n0x7000,\n0x4800,\n0x4800,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 99 (0x63):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |  *** |\n   | *    |\n   | *    |\n   |  *** |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3800,\n0x4000,\n0x4000,\n0x3800,\n0x0000,\n0x0000,\n\n/* Character 100 (0x64):\n   width 6\n   +------+\n   |      |\n   |    * |\n   |    * |\n   |  *** |\n   | *  * |\n   | *  * |\n   |  *** |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0800,\n0x0800,\n0x3800,\n0x4800,\n0x4800,\n0x3800,\n0x0000,\n0x0000,\n\n/* Character 101 (0x65):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |  **  |\n   | * ** |\n   | **   |\n   |  *** |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x5800,\n0x6000,\n0x3800,\n0x0000,\n0x0000,\n\n/* Character 102 (0x66):\n   width 6\n   +------+\n   |      |\n   |   *  |\n   |  * * |\n   |  *   |\n   | ***  |\n   |  *   |\n   |  *   |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x1000,\n0x2800,\n0x2000,\n0x7000,\n0x2000,\n0x2000,\n0x0000,\n0x0000,\n\n/* Character 103 (0x67):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |  **  |\n   | *  * |\n   | *  * |\n   |  *** |\n   |    * |\n   |  **  |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x4800,\n0x4800,\n0x3800,\n0x0800,\n0x3000,\n\n/* Character 104 (0x68):\n   width 6\n   +------+\n   |      |\n   | *    |\n   | *    |\n   | ***  |\n   | *  * |\n   | *  * |\n   | *  * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x4000,\n0x4000,\n0x7000,\n0x4800,\n0x4800,\n0x4800,\n0x0000,\n0x0000,\n\n/* Character 105 (0x69):\n   width 6\n   +------+\n   |      |\n   |  *   |\n   |      |\n   | **   |\n   |  *   |\n   |  *   |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x2000,\n0x0000,\n0x6000,\n0x2000,\n0x2000,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 106 (0x6a):\n   width 6\n   +------+\n   |      |\n   |   *  |\n   |      |\n   |  **  |\n   |   *  |\n   |   *  |\n   |   *  |\n   | * *  |\n   |  *   |\n   +------+ */\n0x0000,\n0x1000,\n0x0000,\n0x3000,\n0x1000,\n0x1000,\n0x1000,\n0x5000,\n0x2000,\n\n/* Character 107 (0x6b):\n   width 6\n   +------+\n   |      |\n   | *    |\n   | *    |\n   | * *  |\n   | **   |\n   | * *  |\n   | *  * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x4000,\n0x4000,\n0x5000,\n0x6000,\n0x5000,\n0x4800,\n0x0000,\n0x0000,\n\n/* Character 108 (0x6c):\n   width 6\n   +------+\n   |      |\n   | **   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x6000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 109 (0x6d):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |** *  |\n   |* * * |\n   |* * * |\n   |*   * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0xd000,\n0xa800,\n0xa800,\n0x8800,\n0x0000,\n0x0000,\n\n/* Character 110 (0x6e):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | ***  |\n   | *  * |\n   | *  * |\n   | *  * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7000,\n0x4800,\n0x4800,\n0x4800,\n0x0000,\n0x0000,\n\n/* Character 111 (0x6f):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |  **  |\n   | *  * |\n   | *  * |\n   |  **  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x4800,\n0x4800,\n0x3000,\n0x0000,\n0x0000,\n\n/* Character 112 (0x70):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | ***  |\n   | *  * |\n   | *  * |\n   | ***  |\n   | *    |\n   | *    |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7000,\n0x4800,\n0x4800,\n0x7000,\n0x4000,\n0x4000,\n\n/* Character 113 (0x71):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |  *** |\n   | *  * |\n   | *  * |\n   |  *** |\n   |    * |\n   |    * |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3800,\n0x4800,\n0x4800,\n0x3800,\n0x0800,\n0x0800,\n\n/* Character 114 (0x72):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | * *  |\n   | ** * |\n   | *    |\n   | *    |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x5000,\n0x6800,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 115 (0x73):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |  *** |\n   | **   |\n   |   ** |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3800,\n0x6000,\n0x1800,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 116 (0x74):\n   width 6\n   +------+\n   |      |\n   |  *   |\n   |  *   |\n   | ***  |\n   |  *   |\n   |  * * |\n   |   *  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x2000,\n0x2000,\n0x7000,\n0x2000,\n0x2800,\n0x1000,\n0x0000,\n0x0000,\n\n/* Character 117 (0x75):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | *  * |\n   | *  * |\n   | *  * |\n   |  *** |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x4800,\n0x4800,\n0x4800,\n0x3800,\n0x0000,\n0x0000,\n\n/* Character 118 (0x76):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | *  * |\n   | *  * |\n   |  **  |\n   |  **  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x4800,\n0x4800,\n0x3000,\n0x3000,\n0x0000,\n0x0000,\n\n/* Character 119 (0x77):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |*   * |\n   |* * * |\n   |* * * |\n   | * *  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x8800,\n0xa800,\n0xa800,\n0x5000,\n0x0000,\n0x0000,\n\n/* Character 120 (0x78):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | *  * |\n   |  **  |\n   |  **  |\n   | *  * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x4800,\n0x3000,\n0x3000,\n0x4800,\n0x0000,\n0x0000,\n\n/* Character 121 (0x79):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | *  * |\n   | *  * |\n   | *  * |\n   |  *** |\n   | *  * |\n   |  **  |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x4800,\n0x4800,\n0x4800,\n0x3800,\n0x4800,\n0x3000,\n\n/* Character 122 (0x7a):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | **** |\n   |   *  |\n   |  *   |\n   | **** |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7800,\n0x1000,\n0x2000,\n0x7800,\n0x0000,\n0x0000,\n\n/* Character 123 (0x7b):\n   width 6\n   +------+\n   |   *  |\n   |  *   |\n   |  *   |\n   | *    |\n   |  *   |\n   |  *   |\n   |   *  |\n   |      |\n   |      |\n   +------+ */\n0x1000,\n0x2000,\n0x2000,\n0x4000,\n0x2000,\n0x2000,\n0x1000,\n0x0000,\n0x0000,\n\n/* Character 124 (0x7c):\n   width 6\n   +------+\n   |      |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |      |\n   +------+ */\n0x0000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x0000,\n\n/* Character 125 (0x7d):\n   width 6\n   +------+\n   | *    |\n   |  *   |\n   |  *   |\n   |   *  |\n   |  *   |\n   |  *   |\n   | *    |\n   |      |\n   |      |\n   +------+ */\n0x4000,\n0x2000,\n0x2000,\n0x1000,\n0x2000,\n0x2000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 126 (0x7e):\n   width 6\n   +------+\n   |      |\n   |      |\n   |  * * |\n   | * *  |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x2800,\n0x5000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 1040 (0x410):\n   width 6\n   +------+\n   |      |\n   |  *   |\n   | * *  |\n   |*   * |\n   |***** |\n   |*   * |\n   |*   * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x2000,\n0x5000,\n0x8800,\n0xf800,\n0x8800,\n0x8800,\n0x0000,\n0x0000,\n\n/* Character 1041 (0x411):\n   width 6\n   +------+\n   |      |\n   |****  |\n   |*     |\n   |****  |\n   |*   * |\n   |*   * |\n   |****  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0xf000,\n0x8000,\n0xf000,\n0x8800,\n0x8800,\n0xf000,\n0x0000,\n0x0000,\n\n/* Character 1042 (0x412):\n   width 6\n   +------+\n   |      |\n   |****  |\n   |*   * |\n   |****  |\n   |*   * |\n   |*   * |\n   |****  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0xf000,\n0x8800,\n0xf000,\n0x8800,\n0x8800,\n0xf000,\n0x0000,\n0x0000,\n\n/* Character 1043 (0x413):\n   width 6\n   +------+\n   |      |\n   | **** |\n   | *    |\n   | *    |\n   | *    |\n   | *    |\n   | *    |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7800,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 1044 (0x414):\n   width 6\n   +------+\n   |      |\n   |  **  |\n   | * *  |\n   | * *  |\n   | * *  |\n   | * *  |\n   |***** |\n   |*   * |\n   |      |\n   +------+ */\n0x0000,\n0x3000,\n0x5000,\n0x5000,\n0x5000,\n0x5000,\n0xf800,\n0x8800,\n0x0000,\n\n/* Character 1045 (0x415):\n   width 6\n   +------+\n   |      |\n   | **** |\n   | *    |\n   | ***  |\n   | *    |\n   | *    |\n   | **** |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7800,\n0x4000,\n0x7000,\n0x4000,\n0x4000,\n0x7800,\n0x0000,\n0x0000,\n\n/* Character 1046 (0x416):\n   width 6\n   +------+\n   |      |\n   |* * * |\n   |* * * |\n   | ***  |\n   |* * * |\n   |* * * |\n   |* * * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0xa800,\n0xa800,\n0x7000,\n0xa800,\n0xa800,\n0xa800,\n0x0000,\n0x0000,\n\n/* Character 1047 (0x417):\n   width 6\n   +------+\n   |      |\n   | ***  |\n   |*   * |\n   |  **  |\n   |    * |\n   |*   * |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7000,\n0x8800,\n0x3000,\n0x0800,\n0x8800,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 1048 (0x418):\n   width 6\n   +------+\n   |      |\n   | *  * |\n   | * ** |\n   | ** * |\n   | *  * |\n   | *  * |\n   | *  * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x4800,\n0x5800,\n0x6800,\n0x4800,\n0x4800,\n0x4800,\n0x0000,\n0x0000,\n\n/* Character 1049 (0x419):\n   width 6\n   +------+\n   | *  * |\n   |  **  |\n   | *  * |\n   | * ** |\n   | ** * |\n   | *  * |\n   | *  * |\n   |      |\n   |      |\n   +------+ */\n0x4800,\n0x3000,\n0x4800,\n0x5800,\n0x6800,\n0x4800,\n0x4800,\n0x0000,\n0x0000,\n\n/* Character 1050 (0x41a):\n   width 6\n   +------+\n   |      |\n   | *  * |\n   | * *  |\n   | **   |\n   | * *  |\n   | *  * |\n   | *  * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x4800,\n0x5000,\n0x6000,\n0x5000,\n0x4800,\n0x4800,\n0x0000,\n0x0000,\n\n/* Character 1051 (0x41b):\n   width 6\n   +------+\n   |      |\n   |  *** |\n   | *  * |\n   | *  * |\n   | *  * |\n   | *  * |\n   |*   * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x3800,\n0x4800,\n0x4800,\n0x4800,\n0x4800,\n0x8800,\n0x0000,\n0x0000,\n\n/* Character 1052 (0x41c):\n   width 6\n   +------+\n   |      |\n   |*   * |\n   |** ** |\n   |* * * |\n   |* * * |\n   |*   * |\n   |*   * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x8800,\n0xd800,\n0xa800,\n0xa800,\n0x8800,\n0x8800,\n0x0000,\n0x0000,\n\n/* Character 1053 (0x41d):\n   width 6\n   +------+\n   |      |\n   | *  * |\n   | *  * |\n   | **** |\n   | *  * |\n   | *  * |\n   | *  * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x4800,\n0x4800,\n0x7800,\n0x4800,\n0x4800,\n0x4800,\n0x0000,\n0x0000,\n\n/* Character 1054 (0x41e):\n   width 6\n   +------+\n   |      |\n   | ***  |\n   |*   * |\n   |*   * |\n   |*   * |\n   |*   * |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7000,\n0x8800,\n0x8800,\n0x8800,\n0x8800,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 1055 (0x41f):\n   width 6\n   +------+\n   |      |\n   |***** |\n   |*   * |\n   |*   * |\n   |*   * |\n   |*   * |\n   |*   * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0xf800,\n0x8800,\n0x8800,\n0x8800,\n0x8800,\n0x8800,\n0x0000,\n0x0000,\n\n/* Character 1056 (0x420):\n   width 6\n   +------+\n   |      |\n   | ***  |\n   | *  * |\n   | *  * |\n   | ***  |\n   | *    |\n   | *    |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7000,\n0x4800,\n0x4800,\n0x7000,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 1057 (0x421):\n   width 6\n   +------+\n   |      |\n   |  **  |\n   | *  * |\n   | *    |\n   | *    |\n   | *  * |\n   |  **  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x3000,\n0x4800,\n0x4000,\n0x4000,\n0x4800,\n0x3000,\n0x0000,\n0x0000,\n\n/* Character 1058 (0x422):\n   width 6\n   +------+\n   |      |\n   |***** |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0xf800,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x0000,\n0x0000,\n\n/* Character 1059 (0x423):\n   width 6\n   +------+\n   |      |\n   |*   * |\n   |*   * |\n   |*   * |\n   | **** |\n   |    * |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x8800,\n0x8800,\n0x8800,\n0x7800,\n0x0800,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 1060 (0x424):\n   width 6\n   +------+\n   |      |\n   |  *   |\n   | ***  |\n   |* * * |\n   |* * * |\n   | ***  |\n   |  *   |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x2000,\n0x7000,\n0xa800,\n0xa800,\n0x7000,\n0x2000,\n0x0000,\n0x0000,\n\n/* Character 1061 (0x425):\n   width 6\n   +------+\n   |      |\n   |*   * |\n   | * *  |\n   |  *   |\n   |  *   |\n   | * *  |\n   |*   * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x8800,\n0x5000,\n0x2000,\n0x2000,\n0x5000,\n0x8800,\n0x0000,\n0x0000,\n\n/* Character 1062 (0x426):\n   width 6\n   +------+\n   |      |\n   |*  *  |\n   |*  *  |\n   |*  *  |\n   |*  *  |\n   |*  *  |\n   |***** |\n   |    * |\n   |   *  |\n   +------+ */\n0x0000,\n0x9000,\n0x9000,\n0x9000,\n0x9000,\n0x9000,\n0xf800,\n0x0800,\n0x1000,\n\n/* Character 1063 (0x427):\n   width 6\n   +------+\n   |      |\n   |*   * |\n   |*   * |\n   |*   * |\n   | **** |\n   |    * |\n   |    * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x8800,\n0x8800,\n0x8800,\n0x7800,\n0x0800,\n0x0800,\n0x0000,\n0x0000,\n\n/* Character 1064 (0x428):\n   width 6\n   +------+\n   |      |\n   |* * * |\n   |* * * |\n   |* * * |\n   |* * * |\n   |* * * |\n   |***** |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0xa800,\n0xa800,\n0xa800,\n0xa800,\n0xa800,\n0xf800,\n0x0000,\n0x0000,\n\n/* Character 1065 (0x429):\n   width 6\n   +------+\n   |      |\n   |* * * |\n   |* * * |\n   |* * * |\n   |* * * |\n   |* * * |\n   |***** |\n   |    * |\n   |   *  |\n   +------+ */\n0x0000,\n0xa800,\n0xa800,\n0xa800,\n0xa800,\n0xa800,\n0xf800,\n0x0800,\n0x1000,\n\n/* Character 1066 (0x42a):\n   width 6\n   +------+\n   |      |\n   |**    |\n   | *    |\n   | ***  |\n   | *  * |\n   | *  * |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0xc000,\n0x4000,\n0x7000,\n0x4800,\n0x4800,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 1067 (0x42b):\n   width 6\n   +------+\n   |      |\n   |*   * |\n   |*   * |\n   |*** * |\n   |*  ** |\n   |*  ** |\n   |*** * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x8800,\n0x8800,\n0xe800,\n0x9800,\n0x9800,\n0xe800,\n0x0000,\n0x0000,\n\n/* Character 1068 (0x42c):\n   width 6\n   +------+\n   |      |\n   | *    |\n   | *    |\n   | ***  |\n   | *  * |\n   | *  * |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x4000,\n0x4000,\n0x7000,\n0x4800,\n0x4800,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 1069 (0x42d):\n   width 6\n   +------+\n   |      |\n   | ***  |\n   |*   * |\n   |  *** |\n   |    * |\n   |*   * |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7000,\n0x8800,\n0x3800,\n0x0800,\n0x8800,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 1070 (0x42e):\n   width 6\n   +------+\n   |      |\n   |*  *  |\n   |* * * |\n   |*** * |\n   |*** * |\n   |* * * |\n   |*  *  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x9000,\n0xa800,\n0xe800,\n0xe800,\n0xa800,\n0x9000,\n0x0000,\n0x0000,\n\n/* Character 1071 (0x42f):\n   width 6\n   +------+\n   |      |\n   |  *** |\n   | *  * |\n   | *  * |\n   |  *** |\n   | *  * |\n   | *  * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x3800,\n0x4800,\n0x4800,\n0x3800,\n0x4800,\n0x4800,\n0x0000,\n0x0000,\n\n/* Character 1072 (0x430):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | ***  |\n   |*  *  |\n   |*  *  |\n   | **** |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7000,\n0x9000,\n0x9000,\n0x7800,\n0x0000,\n0x0000,\n\n/* Character 1073 (0x431):\n   width 6\n   +------+\n   |    * |\n   |  **  |\n   | *    |\n   | ***  |\n   | *  * |\n   | *  * |\n   |  **  |\n   |      |\n   |      |\n   +------+ */\n0x0800,\n0x3000,\n0x4000,\n0x7000,\n0x4800,\n0x4800,\n0x3000,\n0x0000,\n0x0000,\n\n/* Character 1074 (0x432):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | **   |\n   | * *  |\n   | ** * |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x6000,\n0x5000,\n0x6800,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 1075 (0x433):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | **** |\n   | *    |\n   | *    |\n   | *    |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7800,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 1076 (0x434):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |  **  |\n   | * *  |\n   | * *  |\n   |***** |\n   |*   * |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x5000,\n0x5000,\n0xf800,\n0x8800,\n0x0000,\n\n/* Character 1077 (0x435):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | **   |\n   |*  *  |\n   |***   |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x6000,\n0x9000,\n0xe000,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 1078 (0x436):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |* * * |\n   | ***  |\n   | ***  |\n   |* * * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0xa800,\n0x7000,\n0x7000,\n0xa800,\n0x0000,\n0x0000,\n\n/* Character 1079 (0x437):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |  **  |\n   |  * * |\n   |   ** |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x2800,\n0x1800,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 1080 (0x438):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |*   * |\n   |*  ** |\n   |* * * |\n   |**  * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x8800,\n0x9800,\n0xa800,\n0xc800,\n0x0000,\n0x0000,\n\n/* Character 1081 (0x439):\n   width 6\n   +------+\n   |*   * |\n   | ***  |\n   |      |\n   |*   * |\n   |*  ** |\n   |* * * |\n   |**  * |\n   |      |\n   |      |\n   +------+ */\n0x8800,\n0x7000,\n0x0000,\n0x8800,\n0x9800,\n0xa800,\n0xc800,\n0x0000,\n0x0000,\n\n/* Character 1082 (0x43a):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | *  * |\n   | * *  |\n   | ***  |\n   | *  * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x4800,\n0x5000,\n0x7000,\n0x4800,\n0x0000,\n0x0000,\n\n/* Character 1083 (0x43b):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |  *** |\n   | *  * |\n   | *  * |\n   |*   * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3800,\n0x4800,\n0x4800,\n0x8800,\n0x0000,\n0x0000,\n\n/* Character 1084 (0x43c):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |*   * |\n   |** ** |\n   |* * * |\n   |*   * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x8800,\n0xd800,\n0xa800,\n0x8800,\n0x0000,\n0x0000,\n\n/* Character 1085 (0x43d):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |*   * |\n   |***** |\n   |*   * |\n   |*   * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x8800,\n0xf800,\n0x8800,\n0x8800,\n0x0000,\n0x0000,\n\n/* Character 1086 (0x43e):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | ***  |\n   |*   * |\n   |*   * |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7000,\n0x8800,\n0x8800,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 1087 (0x43f):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |***** |\n   |*   * |\n   |*   * |\n   |*   * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0xf800,\n0x8800,\n0x8800,\n0x8800,\n0x0000,\n0x0000,\n\n/* Character 1088 (0x440):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |****  |\n   |*   * |\n   |*   * |\n   |****  |\n   |*     |\n   |*     |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0xf000,\n0x8800,\n0x8800,\n0xf000,\n0x8000,\n0x8000,\n\n/* Character 1089 (0x441):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | ***  |\n   |*   * |\n   |*     |\n   | **** |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7000,\n0x8800,\n0x8000,\n0x7800,\n0x0000,\n0x0000,\n\n/* Character 1090 (0x442):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |***** |\n   |  *   |\n   |  *   |\n   |  *   |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0xf800,\n0x2000,\n0x2000,\n0x2000,\n0x0000,\n0x0000,\n\n/* Character 1091 (0x443):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |*   * |\n   |*   * |\n   |*   * |\n   | **** |\n   |    * |\n   | ***  |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x8800,\n0x8800,\n0x8800,\n0x7800,\n0x0800,\n0x7000,\n\n/* Character 1092 (0x444):\n   width 6\n   +------+\n   |      |\n   |  *   |\n   |  *   |\n   | ***  |\n   |* * * |\n   |* * * |\n   | ***  |\n   |  *   |\n   |  *   |\n   +------+ */\n0x0000,\n0x2000,\n0x2000,\n0x7000,\n0xa800,\n0xa800,\n0x7000,\n0x2000,\n0x2000,\n\n/* Character 1093 (0x445):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | *  * |\n   |  **  |\n   |  **  |\n   | *  * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x4800,\n0x3000,\n0x3000,\n0x4800,\n0x0000,\n0x0000,\n\n/* Character 1094 (0x446):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |*  *  |\n   |*  *  |\n   |*  *  |\n   |***** |\n   |    * |\n   |   *  |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x9000,\n0x9000,\n0x9000,\n0xf800,\n0x0800,\n0x1000,\n\n/* Character 1095 (0x447):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |*   * |\n   |*   * |\n   | **** |\n   |    * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x8800,\n0x8800,\n0x7800,\n0x0800,\n0x0000,\n0x0000,\n\n/* Character 1096 (0x448):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |* * * |\n   |* * * |\n   |* * * |\n   |***** |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0xa800,\n0xa800,\n0xa800,\n0xf800,\n0x0000,\n0x0000,\n\n/* Character 1097 (0x449):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |* * * |\n   |* * * |\n   |* * * |\n   |***** |\n   |    * |\n   |   *  |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0xa800,\n0xa800,\n0xa800,\n0xf800,\n0x0800,\n0x1000,\n\n/* Character 1098 (0x44a):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |**    |\n   | ***  |\n   | *  * |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0xc000,\n0x7000,\n0x4800,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 1099 (0x44b):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |*   * |\n   |*** * |\n   |*  ** |\n   |*** * |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x8800,\n0xe800,\n0x9800,\n0xe800,\n0x0000,\n0x0000,\n\n/* Character 1100 (0x44c):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | *    |\n   | ***  |\n   | *  * |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x4000,\n0x7000,\n0x4800,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 1101 (0x44d):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |***   |\n   | * *  |\n   |  **  |\n   |***   |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0xe000,\n0x5000,\n0x3000,\n0xe000,\n0x0000,\n0x0000,\n\n/* Character 1102 (0x44e):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |*  *  |\n   |*** * |\n   |*** * |\n   |*  *  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x9000,\n0xe800,\n0xe800,\n0x9000,\n0x0000,\n0x0000,\n\n/* Character 1103 (0x44f):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | ***  |\n   |*  *  |\n   | ***  |\n   |*  *  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7000,\n0x9000,\n0x7000,\n0x9000,\n0x0000,\n0x0000,\n};\n\n/* Character->glyph mapping. */\nstatic const unsigned short _6x9_offset[] = {\n  0,\t/* (0x00) */\n  0,\t/* (0x01) */\n  0,\t/* (0x02) */\n  0,\t/* (0x03) */\n  0,\t/* (0x04) */\n  0,\t/* (0x05) */\n  0,\t/* (0x06) */\n  0,\t/* (0x07) */\n  0,\t/* (0x08) */\n  0,\t/* (0x09) */\n  0,\t/* (0x0a) */\n  0,\t/* (0x0b) */\n  0,\t/* (0x0c) */\n  0,\t/* (0x0d) */\n  0,\t/* (0x0e) */\n  0,\t/* (0x0f) */\n  0,\t/* (0x10) */\n  0,\t/* (0x11) */\n  0,\t/* (0x12) */\n  0,\t/* (0x13) */\n  0,\t/* (0x14) */\n  0,\t/* (0x15) */\n  0,\t/* (0x16) */\n  0,\t/* (0x17) */\n  0,\t/* (0x18) */\n  0,\t/* (0x19) */\n  0,\t/* (0x1a) */\n  0,\t/* (0x1b) */\n  0,\t/* (0x1c) */\n  0,\t/* (0x1d) */\n  0,\t/* (0x1e) */\n  0,\t/* (0x1f) */\n  9,\t/* (0x20) */\n  18,\t/* (0x21) */\n  27,\t/* (0x22) */\n  36,\t/* (0x23) */\n  45,\t/* (0x24) */\n  54,\t/* (0x25) */\n  63,\t/* (0x26) */\n  72,\t/* (0x27) */\n  81,\t/* (0x28) */\n  90,\t/* (0x29) */\n  99,\t/* (0x2a) */\n  108,\t/* (0x2b) */\n  117,\t/* (0x2c) */\n  126,\t/* (0x2d) */\n  135,\t/* (0x2e) */\n  144,\t/* (0x2f) */\n  153,\t/* (0x30) */\n  162,\t/* (0x31) */\n  171,\t/* (0x32) */\n  180,\t/* (0x33) */\n  189,\t/* (0x34) */\n  198,\t/* (0x35) */\n  207,\t/* (0x36) */\n  216,\t/* (0x37) */\n  225,\t/* (0x38) */\n  234,\t/* (0x39) */\n  243,\t/* (0x3a) */\n  252,\t/* (0x3b) */\n  261,\t/* (0x3c) */\n  270,\t/* (0x3d) */\n  279,\t/* (0x3e) */\n  288,\t/* (0x3f) */\n  297,\t/* (0x40) */\n  306,\t/* (0x41) */\n  315,\t/* (0x42) */\n  324,\t/* (0x43) */\n  333,\t/* (0x44) */\n  342,\t/* (0x45) */\n  351,\t/* (0x46) */\n  360,\t/* (0x47) */\n  369,\t/* (0x48) */\n  378,\t/* (0x49) */\n  387,\t/* (0x4a) */\n  396,\t/* (0x4b) */\n  405,\t/* (0x4c) */\n  414,\t/* (0x4d) */\n  423,\t/* (0x4e) */\n  432,\t/* (0x4f) */\n  441,\t/* (0x50) */\n  450,\t/* (0x51) */\n  459,\t/* (0x52) */\n  468,\t/* (0x53) */\n  477,\t/* (0x54) */\n  486,\t/* (0x55) */\n  495,\t/* (0x56) */\n  504,\t/* (0x57) */\n  513,\t/* (0x58) */\n  522,\t/* (0x59) */\n  531,\t/* (0x5a) */\n  540,\t/* (0x5b) */\n  549,\t/* (0x5c) */\n  558,\t/* (0x5d) */\n  567,\t/* (0x5e) */\n  576,\t/* (0x5f) */\n  585,\t/* (0x60) */\n  594,\t/* (0x61) */\n  603,\t/* (0x62) */\n  612,\t/* (0x63) */\n  621,\t/* (0x64) */\n  630,\t/* (0x65) */\n  639,\t/* (0x66) */\n  648,\t/* (0x67) */\n  657,\t/* (0x68) */\n  666,\t/* (0x69) */\n  675,\t/* (0x6a) */\n  684,\t/* (0x6b) */\n  693,\t/* (0x6c) */\n  702,\t/* (0x6d) */\n  711,\t/* (0x6e) */\n  720,\t/* (0x6f) */\n  729,\t/* (0x70) */\n  738,\t/* (0x71) */\n  747,\t/* (0x72) */\n  756,\t/* (0x73) */\n  765,\t/* (0x74) */\n  774,\t/* (0x75) */\n  783,\t/* (0x76) */\n  792,\t/* (0x77) */\n  801,\t/* (0x78) */\n  810,\t/* (0x79) */\n  819,\t/* (0x7a) */\n  828,\t/* (0x7b) */\n  837,\t/* (0x7c) */\n  846,\t/* (0x7d) */\n  855,\t/* (0x7e) */\n  0,\t/* (0x7f) */\n  0,\t/* (0x80) */\n  0,\t/* (0x81) */\n  0,\t/* (0x82) */\n  0,\t/* (0x83) */\n  0,\t/* (0x84) */\n  0,\t/* (0x85) */\n  0,\t/* (0x86) */\n  0,\t/* (0x87) */\n  0,\t/* (0x88) */\n  0,\t/* (0x89) */\n  0,\t/* (0x8a) */\n  0,\t/* (0x8b) */\n  0,\t/* (0x8c) */\n  0,\t/* (0x8d) */\n  0,\t/* (0x8e) */\n  0,\t/* (0x8f) */\n  0,\t/* (0x90) */\n  0,\t/* (0x91) */\n  0,\t/* (0x92) */\n  0,\t/* (0x93) */\n  0,\t/* (0x94) */\n  0,\t/* (0x95) */\n  0,\t/* (0x96) */\n  0,\t/* (0x97) */\n  0,\t/* (0x98) */\n  0,\t/* (0x99) */\n  0,\t/* (0x9a) */\n  0,\t/* (0x9b) */\n  0,\t/* (0x9c) */\n  0,\t/* (0x9d) */\n  0,\t/* (0x9e) */\n  0,\t/* (0x9f) */\n  0,\t/* (0xa0) */\n  0,\t/* (0xa1) */\n  0,\t/* (0xa2) */\n  0,\t/* (0xa3) */\n  0,\t/* (0xa4) */\n  0,\t/* (0xa5) */\n  0,\t/* (0xa6) */\n  0,\t/* (0xa7) */\n  0,\t/* (0xa8) */\n  0,\t/* (0xa9) */\n  0,\t/* (0xaa) */\n  0,\t/* (0xab) */\n  0,\t/* (0xac) */\n  0,\t/* (0xad) */\n  0,\t/* (0xae) */\n  0,\t/* (0xaf) */\n  0,\t/* (0xb0) */\n  0,\t/* (0xb1) */\n  0,\t/* (0xb2) */\n  0,\t/* (0xb3) */\n  0,\t/* (0xb4) */\n  0,\t/* (0xb5) */\n  0,\t/* (0xb6) */\n  0,\t/* (0xb7) */\n  0,\t/* (0xb8) */\n  0,\t/* (0xb9) */\n  0,\t/* (0xba) */\n  0,\t/* (0xbb) */\n  0,\t/* (0xbc) */\n  0,\t/* (0xbd) */\n  0,\t/* (0xbe) */\n  0,\t/* (0xbf) */\n  0,\t/* (0xc0) */\n  0,\t/* (0xc1) */\n  0,\t/* (0xc2) */\n  0,\t/* (0xc3) */\n  0,\t/* (0xc4) */\n  0,\t/* (0xc5) */\n  0,\t/* (0xc6) */\n  0,\t/* (0xc7) */\n  0,\t/* (0xc8) */\n  0,\t/* (0xc9) */\n  0,\t/* (0xca) */\n  0,\t/* (0xcb) */\n  0,\t/* (0xcc) */\n  0,\t/* (0xcd) */\n  0,\t/* (0xce) */\n  0,\t/* (0xcf) */\n  0,\t/* (0xd0) */\n  0,\t/* (0xd1) */\n  0,\t/* (0xd2) */\n  0,\t/* (0xd3) */\n  0,\t/* (0xd4) */\n  0,\t/* (0xd5) */\n  0,\t/* (0xd6) */\n  0,\t/* (0xd7) */\n  0,\t/* (0xd8) */\n  0,\t/* (0xd9) */\n  0,\t/* (0xda) */\n  0,\t/* (0xdb) */\n  0,\t/* (0xdc) */\n  0,\t/* (0xdd) */\n  0,\t/* (0xde) */\n  0,\t/* (0xdf) */\n  0,\t/* (0xe0) */\n  0,\t/* (0xe1) */\n  0,\t/* (0xe2) */\n  0,\t/* (0xe3) */\n  0,\t/* (0xe4) */\n  0,\t/* (0xe5) */\n  0,\t/* (0xe6) */\n  0,\t/* (0xe7) */\n  0,\t/* (0xe8) */\n  0,\t/* (0xe9) */\n  0,\t/* (0xea) */\n  0,\t/* (0xeb) */\n  0,\t/* (0xec) */\n  0,\t/* (0xed) */\n  0,\t/* (0xee) */\n  0,\t/* (0xef) */\n  0,\t/* (0xf0) */\n  0,\t/* (0xf1) */\n  0,\t/* (0xf2) */\n  0,\t/* (0xf3) */\n  0,\t/* (0xf4) */\n  0,\t/* (0xf5) */\n  0,\t/* (0xf6) */\n  0,\t/* (0xf7) */\n  0,\t/* (0xf8) */\n  0,\t/* (0xf9) */\n  0,\t/* (0xfa) */\n  0,\t/* (0xfb) */\n  0,\t/* (0xfc) */\n  0,\t/* (0xfd) */\n  0,\t/* (0xfe) */\n  0,\t/* (0xff) */\n  0,\t/* (0x100) */\n  0,\t/* (0x101) */\n  0,\t/* (0x102) */\n  0,\t/* (0x103) */\n  0,\t/* (0x104) */\n  0,\t/* (0x105) */\n  0,\t/* (0x106) */\n  0,\t/* (0x107) */\n  0,\t/* (0x108) */\n  0,\t/* (0x109) */\n  0,\t/* (0x10a) */\n  0,\t/* (0x10b) */\n  0,\t/* (0x10c) */\n  0,\t/* (0x10d) */\n  0,\t/* (0x10e) */\n  0,\t/* (0x10f) */\n  0,\t/* (0x110) */\n  0,\t/* (0x111) */\n  0,\t/* (0x112) */\n  0,\t/* (0x113) */\n  0,\t/* (0x114) */\n  0,\t/* (0x115) */\n  0,\t/* (0x116) */\n  0,\t/* (0x117) */\n  0,\t/* (0x118) */\n  0,\t/* (0x119) */\n  0,\t/* (0x11a) */\n  0,\t/* (0x11b) */\n  0,\t/* (0x11c) */\n  0,\t/* (0x11d) */\n  0,\t/* (0x11e) */\n  0,\t/* (0x11f) */\n  0,\t/* (0x120) */\n  0,\t/* (0x121) */\n  0,\t/* (0x122) */\n  0,\t/* (0x123) */\n  0,\t/* (0x124) */\n  0,\t/* (0x125) */\n  0,\t/* (0x126) */\n  0,\t/* (0x127) */\n  0,\t/* (0x128) */\n  0,\t/* (0x129) */\n  0,\t/* (0x12a) */\n  0,\t/* (0x12b) */\n  0,\t/* (0x12c) */\n  0,\t/* (0x12d) */\n  0,\t/* (0x12e) */\n  0,\t/* (0x12f) */\n  0,\t/* (0x130) */\n  0,\t/* (0x131) */\n  0,\t/* (0x132) */\n  0,\t/* (0x133) */\n  0,\t/* (0x134) */\n  0,\t/* (0x135) */\n  0,\t/* (0x136) */\n  0,\t/* (0x137) */\n  0,\t/* (0x138) */\n  0,\t/* (0x139) */\n  0,\t/* (0x13a) */\n  0,\t/* (0x13b) */\n  0,\t/* (0x13c) */\n  0,\t/* (0x13d) */\n  0,\t/* (0x13e) */\n  0,\t/* (0x13f) */\n  0,\t/* (0x140) */\n  0,\t/* (0x141) */\n  0,\t/* (0x142) */\n  0,\t/* (0x143) */\n  0,\t/* (0x144) */\n  0,\t/* (0x145) */\n  0,\t/* (0x146) */\n  0,\t/* (0x147) */\n  0,\t/* (0x148) */\n  0,\t/* (0x149) */\n  0,\t/* (0x14a) */\n  0,\t/* (0x14b) */\n  0,\t/* (0x14c) */\n  0,\t/* (0x14d) */\n  0,\t/* (0x14e) */\n  0,\t/* (0x14f) */\n  0,\t/* (0x150) */\n  0,\t/* (0x151) */\n  0,\t/* (0x152) */\n  0,\t/* (0x153) */\n  0,\t/* (0x154) */\n  0,\t/* (0x155) */\n  0,\t/* (0x156) */\n  0,\t/* (0x157) */\n  0,\t/* (0x158) */\n  0,\t/* (0x159) */\n  0,\t/* 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1017,\t/* (0x421) */\n  1026,\t/* (0x422) */\n  1035,\t/* (0x423) */\n  1044,\t/* (0x424) */\n  1053,\t/* (0x425) */\n  1062,\t/* (0x426) */\n  1071,\t/* (0x427) */\n  1080,\t/* (0x428) */\n  1089,\t/* (0x429) */\n  1098,\t/* (0x42a) */\n  1107,\t/* (0x42b) */\n  1116,\t/* (0x42c) */\n  1125,\t/* (0x42d) */\n  1134,\t/* (0x42e) */\n  1143,\t/* (0x42f) */\n  1152,\t/* (0x430) */\n  1161,\t/* (0x431) */\n  1170,\t/* (0x432) */\n  1179,\t/* (0x433) */\n  1188,\t/* (0x434) */\n  1197,\t/* (0x435) */\n  1206,\t/* (0x436) */\n  1215,\t/* (0x437) */\n  1224,\t/* (0x438) */\n  1233,\t/* (0x439) */\n  1242,\t/* (0x43a) */\n  1251,\t/* (0x43b) */\n  1260,\t/* (0x43c) */\n  1269,\t/* (0x43d) */\n  1278,\t/* (0x43e) */\n  1287,\t/* (0x43f) */\n  1296,\t/* (0x440) */\n  1305,\t/* (0x441) */\n  1314,\t/* (0x442) */\n  1323,\t/* (0x443) */\n  1332,\t/* (0x444) */\n  1341,\t/* (0x445) */\n  1350,\t/* (0x446) */\n  1359,\t/* (0x447) */\n  1368,\t/* (0x448) */\n  1377,\t/* (0x449) */\n  1386,\t/* (0x44a) */\n  1395,\t/* (0x44b) */\n  1404,\t/* (0x44c) */\n  1413,\t/* (0x44d) */\n  1422,\t/* (0x44e) */\n  1431,\t/* (0x44f) */\n};\n\n/* Exported structure definition. */\nconst struct gpanel_font_t font_6x9 = {\n  \"6x9\",\n  6,\n  9,\n  7,\n  0,\n  1104,\n  _6x9_bits,\n  _6x9_offset,\n  0,  /* fixed width*/\n  0,\n  sizeof(_6x9_bits) / sizeof(_6x9_bits[0]),\n};\n"
  },
  {
    "path": "share/examples/gpanel/fonts/Makefile",
    "content": "CFLAGS\t\t= -Wall -O -g\nLDFLAGS\t\t= -L/opt/local/lib -lpng\n\nFONTS           = digits32.c \\\n                  digits20.c \\\n                  lucidasans11.c \\\n                  lucidasans15.c \\\n                  lucidasans9.c \\\n                  lucidasans7.c \\\n                  verdana7.c \\\n                  5x7.c \\\n                  6x9.c\n\n# Latin\nCHARSET         = 20_126 164\n\n# Cyrillics: Ё, ё, А-я\n#CHARSET         += 1025 1105 1040_1103\n\nall:\t\t$(FONTS)\n\ncompile:        $(FONTS)\n\t\t$(CC) -c $(FONTS)\n\t\tsize *.o\n\n# Get Lucida_Sans_Unicode.ttf from internet free font collection:\n# http://www.webpagepublicity.com/free-fonts/l/Lucida%20Sans%20Unicode.ttf\n# Use otf2bdf utility from ftp://crl.nmsu.edu/CLR/multiling/General/\n# Under Ubuntu, install otf2bdf package.\ndigits32.c:\tconvbdf ttf/Lucida_Sans_Unicode.ttf\n\t\t-otf2bdf -p 32 -l \"32 48_58\" ttf/Lucida_Sans_Unicode.ttf > digits32.bdf\n\t\t./convbdf -a12 -d15 digits32.bdf\n\t\trm -f digits32.bdf\n\ndigits20.c:\tconvbdf ttf/Lucida_Sans_Unicode.ttf\n\t\t-otf2bdf -p 20 -l \"32 48_58\" ttf/Lucida_Sans_Unicode.ttf > digits20.bdf\n\t\t./convbdf -a9 -d11 digits20.bdf\n\t\trm -f digits20.bdf\n\nlucidasans11.c:\tconvbdf ttf/Lucida_Sans_Unicode.ttf\n\t\t-otf2bdf -p 11 -l \"$(CHARSET)\" ttf/Lucida_Sans_Unicode.ttf > lucidasans11.bdf\n\t\t./convbdf -u164 -a2 -d3 lucidasans11.bdf\n\t\trm -f lucidasans11.bdf\n\nlucidasans15.c:\tconvbdf ttf/Lucida_Sans_Unicode.ttf\n\t\t-otf2bdf -p 15 -l \"$(CHARSET)\" ttf/Lucida_Sans_Unicode.ttf > lucidasans15.bdf\n\t\t./convbdf -u164 -a5 -d5 lucidasans15.bdf\n\t\trm -f lucidasans15.bdf\n\nlucidasans28.c:\tconvbdf ttf/Lucida_Sans_Unicode.ttf\n\t\t-otf2bdf -p 28 -l \"$(CHARSET)\" ttf/Lucida_Sans_Unicode.ttf > lucidasans28.bdf\n\t\t./convbdf -u164 -a11 -d9 lucidasans28.bdf\n\t\trm -f lucidasans28.bdf\n\nlucidasans9.c:\tconvbdf ttf/Lucida_Sans_Unicode.ttf\n\t\t-otf2bdf -p 9 -l \"$(CHARSET)\" ttf/Lucida_Sans_Unicode.ttf > lucidasans9.bdf\n\t\t./convbdf -u164 -a2 -d3 lucidasans9.bdf\n\t\trm -f lucidasans9.bdf\n\nlucidasans7.c:\tconvbdf ttf/Lucida_Sans_Unicode.ttf\n\t\t-otf2bdf -p 7 -l \"$(CHARSET)\" ttf/Lucida_Sans_Unicode.ttf > lucidasans7.bdf\n\t\t./convbdf -u164 -a2 -d3 lucidasans7.bdf\n\t\trm -f lucidasans7.bdf\n\n# Use /usr/share/fonts/truetype/msttcorefonts/Verdana.ttf\nverdana7.c:\tconvbdf ttf/Verdana.ttf\n\t\t-otf2bdf -p 7 -l \"$(CHARSET)\" ttf/Verdana.ttf > verdana7.bdf\n\t\t./convbdf -a2 verdana7.bdf\n\t\trm -f verdana7.bdf\n\n5x7.c:\t\tconvbdf bdf/5x7.bdf\n\t\t./convbdf -u0 -l0x44f -x0xa0-0x40f bdf/5x7.bdf\n\n6x9.c:\t\tconvbdf bdf/6x9.bdf\n\t\t./convbdf -u0 -l0x44f -x0xa0-0x40f bdf/6x9.bdf\n\nclean:\n\t\t-rm -f *~ *.o convbdf\n\nclean-all:      clean\n\t\t-rm -f $(FONTS)\n"
  },
  {
    "path": "share/examples/gpanel/fonts/bdf/5x7.bdf",
    "content": "STARTFONT 2.1\nCOMMENT \"$Id: 5x7.bdf,v 1.38 2006-01-05 20:03:17+00 mgk25 Rel $\"\nCOMMENT \"Send bug reports to Markus Kuhn <http://www.cl.cam.ac.uk/~mgk25/>\"\nFONT -Misc-Fixed-Medium-R-Normal--7-70-75-75-C-50-ISO10646-1\nSIZE 7 75 75\nFONTBOUNDINGBOX 5 7 0 -1\nSTARTPROPERTIES 23\nFONTNAME_REGISTRY \"\"\nFOUNDRY \"Misc\"\nFAMILY_NAME \"Fixed\"\nWEIGHT_NAME \"Medium\"\nSLANT \"R\"\nSETWIDTH_NAME \"Normal\"\nADD_STYLE_NAME \"\"\nPIXEL_SIZE 7\nPOINT_SIZE 70\nRESOLUTION_X 75\nRESOLUTION_Y 75\nSPACING \"C\"\nAVERAGE_WIDTH 50\nCHARSET_REGISTRY \"ISO10646\"\nCHARSET_ENCODING \"1\"\nFONT_ASCENT 6\nFONT_DESCENT 1\nDESTINATION 1\nDEFAULT_CHAR 0\nCOPYRIGHT \"Public domain font.  Share and enjoy.\"\n_XMBDFED_INFO \"Edited with xmbdfed 4.5.\"\nCAP_HEIGHT 6\nX_HEIGHT 4\nENDPROPERTIES\nCHARS 1848\nSTARTCHAR char0\nENCODING 0\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\nA8\n00\n88\n00\nA8\n00\nENDCHAR\nSTARTCHAR space\nENCODING 32\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR exclam\nENCODING 33\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\n20\n00\n20\n00\nENDCHAR\nSTARTCHAR quotedbl\nENCODING 34\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n50\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR numbersign\nENCODING 35\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n50\nF8\n50\nF8\n50\n00\nENDCHAR\nSTARTCHAR dollar\nENCODING 36\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n70\nA0\n70\n28\n70\n00\nENDCHAR\nSTARTCHAR percent\nENCODING 37\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n90\n20\n40\n90\n10\n00\nENDCHAR\nSTARTCHAR ampersand\nENCODING 38\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n40\nA0\n40\nA0\n50\n00\nENDCHAR\nSTARTCHAR quotesingle\nENCODING 39\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR parenleft\nENCODING 40\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n40\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR parenright\nENCODING 41\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n20\n20\n20\n40\n00\nENDCHAR\nSTARTCHAR asterisk\nENCODING 42\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n50\n20\n70\n20\n50\n00\nENDCHAR\nSTARTCHAR plus\nENCODING 43\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n20\nF8\n20\n20\n00\nENDCHAR\nSTARTCHAR comma\nENCODING 44\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n30\n20\n40\nENDCHAR\nSTARTCHAR hyphen\nENCODING 45\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nF0\n00\n00\n00\nENDCHAR\nSTARTCHAR period\nENCODING 46\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n60\n60\n00\nENDCHAR\nSTARTCHAR slash\nENCODING 47\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n10\n20\n40\n80\n00\n00\nENDCHAR\nSTARTCHAR zero\nENCODING 48\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n50\n50\n50\n20\n00\nENDCHAR\nSTARTCHAR one\nENCODING 49\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n60\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR two\nENCODING 50\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n10\n20\n40\nF0\n00\nENDCHAR\nSTARTCHAR three\nENCODING 51\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n10\n60\n10\n90\n60\n00\nENDCHAR\nSTARTCHAR four\nENCODING 52\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n60\nA0\nF0\n20\n20\n00\nENDCHAR\nSTARTCHAR five\nENCODING 53\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nE0\n10\n90\n60\n00\nENDCHAR\nSTARTCHAR six\nENCODING 54\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n80\nE0\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR seven\nENCODING 55\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n10\n20\n20\n40\n40\n00\nENDCHAR\nSTARTCHAR eight\nENCODING 56\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR nine\nENCODING 57\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\n70\n10\n60\n00\nENDCHAR\nSTARTCHAR colon\nENCODING 58\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n60\n60\n00\n60\n60\n00\nENDCHAR\nSTARTCHAR semicolon\nENCODING 59\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n60\n60\n00\n60\n40\n80\nENDCHAR\nSTARTCHAR less\nENCODING 60\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n10\n20\n40\n20\n10\n00\nENDCHAR\nSTARTCHAR equal\nENCODING 61\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF0\n00\nF0\n00\n00\nENDCHAR\nSTARTCHAR greater\nENCODING 62\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n40\n20\n10\n20\n40\n00\nENDCHAR\nSTARTCHAR question\nENCODING 63\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n10\n20\n00\n20\n00\nENDCHAR\nSTARTCHAR at\nENCODING 64\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\nB0\nB0\n80\n60\n00\nENDCHAR\nSTARTCHAR A\nENCODING 65\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR B\nENCODING 66\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\nE0\n90\n90\nE0\n00\nENDCHAR\nSTARTCHAR C\nENCODING 67\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n80\n80\n90\n60\n00\nENDCHAR\nSTARTCHAR D\nENCODING 68\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\n90\n90\n90\nE0\n00\nENDCHAR\nSTARTCHAR E\nENCODING 69\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nE0\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR F\nENCODING 70\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nE0\n80\n80\n80\n00\nENDCHAR\nSTARTCHAR G\nENCODING 71\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n80\nB0\n90\n70\n00\nENDCHAR\nSTARTCHAR H\nENCODING 72\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\nF0\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR I\nENCODING 73\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR J\nENCODING 74\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n10\n10\n10\n90\n60\n00\nENDCHAR\nSTARTCHAR K\nENCODING 75\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nA0\nC0\nC0\nA0\n90\n00\nENDCHAR\nSTARTCHAR L\nENCODING 76\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n80\n80\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR M\nENCODING 77\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nF0\nF0\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR N\nENCODING 78\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nD0\nD0\nB0\nB0\n90\n00\nENDCHAR\nSTARTCHAR O\nENCODING 79\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR P\nENCODING 80\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\n90\nE0\n80\n80\n00\nENDCHAR\nSTARTCHAR Q\nENCODING 81\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\n90\nD0\n60\n10\nENDCHAR\nSTARTCHAR R\nENCODING 82\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\n90\nE0\nA0\n90\n00\nENDCHAR\nSTARTCHAR S\nENCODING 83\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n40\n20\n90\n60\n00\nENDCHAR\nSTARTCHAR T\nENCODING 84\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR U\nENCODING 85\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR V\nENCODING 86\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\n60\n60\n00\nENDCHAR\nSTARTCHAR W\nENCODING 87\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\nF0\nF0\n90\n00\nENDCHAR\nSTARTCHAR X\nENCODING 88\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n60\n60\n90\n90\n00\nENDCHAR\nSTARTCHAR Y\nENCODING 89\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n50\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR Z\nENCODING 90\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n10\n20\n40\n80\nF0\n00\nENDCHAR\nSTARTCHAR bracketleft\nENCODING 91\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n40\n40\n40\n40\n70\n00\nENDCHAR\nSTARTCHAR backslash\nENCODING 92\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n80\n40\n20\n10\n00\n00\nENDCHAR\nSTARTCHAR bracketright\nENCODING 93\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n10\n10\n10\n10\n70\n00\nENDCHAR\nSTARTCHAR asciicircum\nENCODING 94\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR underscore\nENCODING 95\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\nF0\n00\nENDCHAR\nSTARTCHAR grave\nENCODING 96\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR a\nENCODING 97\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR b\nENCODING 98\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n80\nE0\n90\n90\nE0\n00\nENDCHAR\nSTARTCHAR c\nENCODING 99\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n80\n80\n60\n00\nENDCHAR\nSTARTCHAR d\nENCODING 100\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n10\n70\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR e\nENCODING 101\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\nB0\nC0\n60\n00\nENDCHAR\nSTARTCHAR f\nENCODING 102\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n40\nE0\n40\n40\n00\nENDCHAR\nSTARTCHAR g\nENCODING 103\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\n90\n60\n80\n70\nENDCHAR\nSTARTCHAR h\nENCODING 104\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n80\nE0\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR i\nENCODING 105\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n00\n60\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR j\nENCODING 106\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n10\n10\n10\n50\n20\nENDCHAR\nSTARTCHAR k\nENCODING 107\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n80\nA0\nC0\nA0\n90\n00\nENDCHAR\nSTARTCHAR l\nENCODING 108\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR m\nENCODING 109\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nA0\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR n\nENCODING 110\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR o\nENCODING 111\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR p\nENCODING 112\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\n90\n90\nE0\n80\nENDCHAR\nSTARTCHAR q\nENCODING 113\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\n90\n90\n70\n10\nENDCHAR\nSTARTCHAR r\nENCODING 114\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\n90\n80\n80\n00\nENDCHAR\nSTARTCHAR s\nENCODING 115\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\nC0\n30\nE0\n00\nENDCHAR\nSTARTCHAR t\nENCODING 116\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n40\nE0\n40\n40\n30\n00\nENDCHAR\nSTARTCHAR u\nENCODING 117\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR v\nENCODING 118\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n50\n50\n20\n00\nENDCHAR\nSTARTCHAR w\nENCODING 119\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n90\nF0\nF0\n00\nENDCHAR\nSTARTCHAR x\nENCODING 120\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n60\n60\n90\n00\nENDCHAR\nSTARTCHAR y\nENCODING 121\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n90\n50\n20\n40\nENDCHAR\nSTARTCHAR z\nENCODING 122\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF0\n20\n40\nF0\n00\nENDCHAR\nSTARTCHAR braceleft\nENCODING 123\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n20\n60\n20\n20\n10\n00\nENDCHAR\nSTARTCHAR bar\nENCODING 124\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR braceright\nENCODING 125\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n30\n20\n20\n40\n00\nENDCHAR\nSTARTCHAR asciitilde\nENCODING 126\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\nA0\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR space\nENCODING 160\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR exclamdown\nENCODING 161\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n00\n20\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR cent\nENCODING 162\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n70\nA0\nA0\n70\n20\nENDCHAR\nSTARTCHAR sterling\nENCODING 163\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n30\n40\nE0\n40\nB0\n00\nENDCHAR\nSTARTCHAR currency\nENCODING 164\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n88\n70\n50\n70\n88\n00\nENDCHAR\nSTARTCHAR yen\nENCODING 165\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n20\n70\n20\n20\n00\nENDCHAR\nSTARTCHAR brokenbar\nENCODING 166\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n20\n00\n20\n20\n00\nENDCHAR\nSTARTCHAR section\nENCODING 167\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n40\n60\n50\n30\n10\n60\nENDCHAR\nSTARTCHAR dieresis\nENCODING 168\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR copyright\nENCODING 169\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n88\nA8\nC8\nA8\n88\n70\nENDCHAR\nSTARTCHAR ordfeminine\nENCODING 170\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\nA0\n60\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR guillemotleft\nENCODING 171\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n48\n90\n48\n00\n00\nENDCHAR\nSTARTCHAR logicalnot\nENCODING 172\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nF0\n10\n00\n00\nENDCHAR\nSTARTCHAR hyphen\nENCODING 173\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n70\n00\n00\n00\nENDCHAR\nSTARTCHAR registered\nENCODING 174\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n88\nE8\nC8\nC8\n88\n70\nENDCHAR\nSTARTCHAR macron\nENCODING 175\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR degree\nENCODING 176\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n20\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR plusminus\nENCODING 177\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\nF8\n20\n20\nF8\n00\nENDCHAR\nSTARTCHAR twosuperior\nENCODING 178\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n40\n60\n00\n00\n00\nENDCHAR\nSTARTCHAR threesuperior\nENCODING 179\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n60\n20\n60\n00\n00\n00\nENDCHAR\nSTARTCHAR acute\nENCODING 180\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR mu\nENCODING 181\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n90\n90\nE0\n80\nENDCHAR\nSTARTCHAR paragraph\nENCODING 182\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\nD0\nD0\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR periodcentered\nENCODING 183\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n60\n00\n00\n00\nENDCHAR\nSTARTCHAR cedilla\nENCODING 184\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\n20\n40\nENDCHAR\nSTARTCHAR onesuperior\nENCODING 185\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n60\n20\n70\n00\n00\n00\nENDCHAR\nSTARTCHAR ordmasculine\nENCODING 186\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\nA0\n40\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR guillemotright\nENCODING 187\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n48\n90\n00\n00\nENDCHAR\nSTARTCHAR onequarter\nENCODING 188\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n80\n80\n90\n30\n70\n10\nENDCHAR\nSTARTCHAR onehalf\nENCODING 189\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n80\n80\nB0\n10\n20\n30\nENDCHAR\nSTARTCHAR threequarters\nENCODING 190\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nC0\nC0\n40\nD0\n30\n70\n10\nENDCHAR\nSTARTCHAR questiondown\nENCODING 191\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n00\n20\n40\n50\n20\n00\nENDCHAR\nSTARTCHAR Agrave\nENCODING 192\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR Aacute\nENCODING 193\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR Acircumflex\nENCODING 194\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR Atilde\nENCODING 195\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR Adieresis\nENCODING 196\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n60\n90\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR Aring\nENCODING 197\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n60\n90\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR AE\nENCODING 198\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\nA0\nB0\nE0\nA0\nB0\n00\nENDCHAR\nSTARTCHAR Ccedilla\nENCODING 199\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n80\n80\n90\n60\n40\nENDCHAR\nSTARTCHAR Egrave\nENCODING 200\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nE0\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR Eacute\nENCODING 201\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nE0\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR Ecircumflex\nENCODING 202\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nE0\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR Edieresis\nENCODING 203\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nE0\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR Igrave\nENCODING 204\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR Iacute\nENCODING 205\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR Icircumflex\nENCODING 206\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR Idieresis\nENCODING 207\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR Eth\nENCODING 208\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n50\nD0\n50\n50\nE0\n00\nENDCHAR\nSTARTCHAR Ntilde\nENCODING 209\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nB0\n90\nD0\nB0\nB0\n90\n00\nENDCHAR\nSTARTCHAR Ograve\nENCODING 210\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR Oacute\nENCODING 211\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR Ocircumflex\nENCODING 212\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR Otilde\nENCODING 213\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR Odieresis\nENCODING 214\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n60\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR multiply\nENCODING 215\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n60\n60\n90\n00\nENDCHAR\nSTARTCHAR Oslash\nENCODING 216\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\nB0\nB0\nD0\nD0\nE0\n00\nENDCHAR\nSTARTCHAR Ugrave\nENCODING 217\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR Uacute\nENCODING 218\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR Ucircumflex\nENCODING 219\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR Udieresis\nENCODING 220\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n00\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR Yacute\nENCODING 221\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n50\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR Thorn\nENCODING 222\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\nE0\n90\nE0\n80\n80\n00\nENDCHAR\nSTARTCHAR germandbls\nENCODING 223\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\nA0\n90\n90\nA0\n00\nENDCHAR\nSTARTCHAR agrave\nENCODING 224\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR aacute\nENCODING 225\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR acircumflex\nENCODING 226\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR atilde\nENCODING 227\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\nA0\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR adieresis\nENCODING 228\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR aring\nENCODING 229\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n60\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR ae\nENCODING 230\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\nB0\nA0\n70\n00\nENDCHAR\nSTARTCHAR ccedilla\nENCODING 231\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n30\n40\n40\n30\n20\nENDCHAR\nSTARTCHAR egrave\nENCODING 232\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n60\nB0\nC0\n60\n00\nENDCHAR\nSTARTCHAR eacute\nENCODING 233\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n60\nB0\nC0\n60\n00\nENDCHAR\nSTARTCHAR ecircumflex\nENCODING 234\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\nA0\n60\nB0\nC0\n60\n00\nENDCHAR\nSTARTCHAR edieresis\nENCODING 235\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\n00\n60\nB0\nC0\n60\n00\nENDCHAR\nSTARTCHAR igrave\nENCODING 236\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n60\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR iacute\nENCODING 237\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n60\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR icircumflex\nENCODING 238\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n60\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR idieresis\nENCODING 239\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n60\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR eth\nENCODING 240\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n30\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR ntilde\nENCODING 241\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\nA0\nE0\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR ograve\nENCODING 242\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR oacute\nENCODING 243\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR ocircumflex\nENCODING 244\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n00\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR otilde\nENCODING 245\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\nA0\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR odieresis\nENCODING 246\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR divide\nENCODING 247\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n60\n00\nF0\n00\n60\n00\nENDCHAR\nSTARTCHAR oslash\nENCODING 248\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\nB0\nD0\nE0\n00\nENDCHAR\nSTARTCHAR ugrave\nENCODING 249\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n90\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR uacute\nENCODING 250\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n90\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR ucircumflex\nENCODING 251\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n00\n90\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR udieresis\nENCODING 252\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n90\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR yacute\nENCODING 253\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n90\n90\n50\n20\n40\nENDCHAR\nSTARTCHAR thorn\nENCODING 254\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n80\nE0\n90\n90\nE0\n80\nENDCHAR\nSTARTCHAR ydieresis\nENCODING 255\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n90\n90\n50\n20\n40\nENDCHAR\nSTARTCHAR Amacron\nENCODING 256\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR amacron\nENCODING 257\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n00\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR Abreve\nENCODING 258\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR abreve\nENCODING 259\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n60\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR Aogonek\nENCODING 260\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\nF0\n90\n90\n10\nENDCHAR\nSTARTCHAR aogonek\nENCODING 261\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\n90\nB0\n50\n08\nENDCHAR\nSTARTCHAR Cacute\nENCODING 262\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n80\n80\n90\n60\n00\nENDCHAR\nSTARTCHAR cacute\nENCODING 263\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n20\n30\n40\n40\n30\n00\nENDCHAR\nSTARTCHAR Ccircumflex\nENCODING 264\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n80\n80\n90\n60\n00\nENDCHAR\nSTARTCHAR ccircumflex\nENCODING 265\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n00\n60\n80\n80\n60\n00\nENDCHAR\nSTARTCHAR Cdotaccent\nENCODING 266\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n80\n80\n90\n60\n00\nENDCHAR\nSTARTCHAR cdotaccent\nENCODING 267\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n60\n80\n80\n60\n00\nENDCHAR\nSTARTCHAR Ccaron\nENCODING 268\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n80\n80\n90\n60\n00\nENDCHAR\nSTARTCHAR ccaron\nENCODING 269\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\n40\n60\n80\n80\n60\n00\nENDCHAR\nSTARTCHAR Dcaron\nENCODING 270\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\n90\n90\n90\nE0\n00\nENDCHAR\nSTARTCHAR dcaron\nENCODING 271\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\n50\n10\n70\n90\n70\n00\nENDCHAR\nSTARTCHAR Dcroat\nENCODING 272\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\nD0\n90\n90\nE0\n00\nENDCHAR\nSTARTCHAR dcroat\nENCODING 273\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n38\n10\n70\n90\n70\n00\nENDCHAR\nSTARTCHAR Emacron\nENCODING 274\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nE0\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR emacron\nENCODING 275\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n00\n60\nB0\nC0\n60\n00\nENDCHAR\nSTARTCHAR Ebreve\nENCODING 276\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nE0\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR ebreve\nENCODING 277\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n60\n60\nB0\nC0\n60\n00\nENDCHAR\nSTARTCHAR Edotaccent\nENCODING 278\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nE0\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR edotaccent\nENCODING 279\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n60\nB0\nC0\n60\n00\nENDCHAR\nSTARTCHAR Eogonek\nENCODING 280\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nE0\n80\n80\nF0\n40\nENDCHAR\nSTARTCHAR eogonek\nENCODING 281\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\nB0\nC0\n60\n40\nENDCHAR\nSTARTCHAR Ecaron\nENCODING 282\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nE0\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR ecaron\nENCODING 283\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\n40\n60\nB0\nC0\n60\n00\nENDCHAR\nSTARTCHAR Gcircumflex\nENCODING 284\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n80\nB0\n90\n70\n00\nENDCHAR\nSTARTCHAR gcircumflex\nENCODING 285\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n00\n70\n90\n60\n80\n70\nENDCHAR\nSTARTCHAR Gbreve\nENCODING 286\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n80\nB0\n90\n70\n00\nENDCHAR\nSTARTCHAR gbreve\nENCODING 287\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n20\n70\n90\n60\n80\n70\nENDCHAR\nSTARTCHAR Gdotaccent\nENCODING 288\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n80\nB0\n90\n70\n00\nENDCHAR\nSTARTCHAR gdotaccent\nENCODING 289\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n00\n70\n90\n60\n80\n70\nENDCHAR\nSTARTCHAR Gcommaaccent\nENCODING 290\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n80\nB0\n90\n70\n40\nENDCHAR\nSTARTCHAR gcommaaccent\nENCODING 291\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n70\n90\n60\n80\n70\nENDCHAR\nSTARTCHAR Hcircumflex\nENCODING 292\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\nF0\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR hcircumflex\nENCODING 293\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\nA0\n80\nE0\n90\n90\n00\nENDCHAR\nSTARTCHAR Hbar\nENCODING 294\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nF8\n90\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR hbar\nENCODING 295\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\nC0\n80\nE0\n90\n90\n00\nENDCHAR\nSTARTCHAR Itilde\nENCODING 296\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR itilde\nENCODING 297\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\nA0\n60\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR Imacron\nENCODING 298\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR imacron\nENCODING 299\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n00\n60\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR Ibreve\nENCODING 300\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR ibreve\nENCODING 301\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n60\n60\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR Iogonek\nENCODING 302\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n70\n40\nENDCHAR\nSTARTCHAR iogonek\nENCODING 303\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n00\n60\n20\n20\n70\n40\nENDCHAR\nSTARTCHAR Idotaccent\nENCODING 304\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR dotlessi\nENCODING 305\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR IJ\nENCODING 306\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\nD0\nA0\n00\nENDCHAR\nSTARTCHAR ij\nENCODING 307\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n00\n90\n90\n90\nD0\n20\nENDCHAR\nSTARTCHAR Jcircumflex\nENCODING 308\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n10\n10\n10\n90\n60\n00\nENDCHAR\nSTARTCHAR jcircumflex\nENCODING 309\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n00\n20\n20\nA0\n40\nENDCHAR\nSTARTCHAR Kcommaaccent\nENCODING 310\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nA0\nC0\nC0\nA0\n90\n80\nENDCHAR\nSTARTCHAR kcommaaccent\nENCODING 311\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n80\nA0\nC0\nA0\n90\n80\nENDCHAR\nSTARTCHAR kgreenlandic\nENCODING 312\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\nE0\n90\n90\n00\nENDCHAR\nSTARTCHAR Lacute\nENCODING 313\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nA0\n80\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR lacute\nENCODING 314\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nC8\n50\n40\n40\n40\nE0\n00\nENDCHAR\nSTARTCHAR Lcommaaccent\nENCODING 315\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n80\n80\n80\n80\nF0\n80\nENDCHAR\nSTARTCHAR lcommaaccent\nENCODING 316\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n20\n20\n20\n70\n40\nENDCHAR\nSTARTCHAR Lcaron\nENCODING 317\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA8\n90\n80\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR lcaron\nENCODING 318\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA8\n90\n80\n80\n80\n40\n00\nENDCHAR\nSTARTCHAR Ldot\nENCODING 319\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n80\nA0\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR ldot\nENCODING 320\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nC0\n40\n50\n40\n40\nE0\n00\nENDCHAR\nSTARTCHAR Lslash\nENCODING 321\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n80\nC0\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR lslash\nENCODING 322\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n30\n60\n20\n70\n00\nENDCHAR\nSTARTCHAR Nacute\nENCODING 323\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nD0\nD0\nB0\nB0\n90\n00\nENDCHAR\nSTARTCHAR nacute\nENCODING 324\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\nE0\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR Ncommaaccent\nENCODING 325\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nD0\nD0\nB0\nB0\n90\n80\nENDCHAR\nSTARTCHAR ncommaaccent\nENCODING 326\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\n90\n90\n90\n80\nENDCHAR\nSTARTCHAR Ncaron\nENCODING 327\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nD0\nD0\nB0\nB0\n90\n00\nENDCHAR\nSTARTCHAR ncaron\nENCODING 328\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\n40\nE0\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR napostrophe\nENCODING 329\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n00\nE0\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR Eng\nENCODING 330\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nD0\nD0\nB0\nB0\n90\n20\nENDCHAR\nSTARTCHAR eng\nENCODING 331\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\n90\n90\n90\n20\nENDCHAR\nSTARTCHAR Omacron\nENCODING 332\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR omacron\nENCODING 333\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n00\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR Obreve\nENCODING 334\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR obreve\nENCODING 335\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n60\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR Ohungarumlaut\nENCODING 336\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR ohungarumlaut\nENCODING 337\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n48\n90\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR OE\nENCODING 338\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\nA0\nB0\nA0\nA0\n70\n00\nENDCHAR\nSTARTCHAR oe\nENCODING 339\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\nB0\nA0\n70\n00\nENDCHAR\nSTARTCHAR Racute\nENCODING 340\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\n90\nE0\nA0\n90\n00\nENDCHAR\nSTARTCHAR racute\nENCODING 341\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\nE0\n90\n80\n80\n00\nENDCHAR\nSTARTCHAR Rcommaaccent\nENCODING 342\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\n90\nE0\nA0\n90\n80\nENDCHAR\nSTARTCHAR rcommaaccent\nENCODING 343\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\n90\n80\n80\n40\nENDCHAR\nSTARTCHAR Rcaron\nENCODING 344\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\n90\nE0\nA0\n90\n00\nENDCHAR\nSTARTCHAR rcaron\nENCODING 345\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\n40\nE0\n90\n80\n80\n00\nENDCHAR\nSTARTCHAR Sacute\nENCODING 346\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n40\n20\n90\n60\n00\nENDCHAR\nSTARTCHAR sacute\nENCODING 347\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n70\nC0\n30\nE0\n00\nENDCHAR\nSTARTCHAR Scircumflex\nENCODING 348\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n40\n20\n90\n60\n00\nENDCHAR\nSTARTCHAR scircumflex\nENCODING 349\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n00\n70\nC0\n30\nE0\n00\nENDCHAR\nSTARTCHAR Scedilla\nENCODING 350\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n40\n20\n90\n60\n40\nENDCHAR\nSTARTCHAR scedilla\nENCODING 351\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\nC0\n30\nE0\n40\nENDCHAR\nSTARTCHAR Scaron\nENCODING 352\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n40\n20\n90\n60\n00\nENDCHAR\nSTARTCHAR scaron\nENCODING 353\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n20\n70\nC0\n30\nE0\n00\nENDCHAR\nSTARTCHAR Tcommaaccent\nENCODING 354\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n20\n40\nENDCHAR\nSTARTCHAR tcommaaccent\nENCODING 355\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n40\nE0\n40\n40\n30\n40\nENDCHAR\nSTARTCHAR Tcaron\nENCODING 356\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n40\n40\n40\n40\n40\n00\nENDCHAR\nSTARTCHAR tcaron\nENCODING 357\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n20\n40\nE0\n40\n30\n00\nENDCHAR\nSTARTCHAR Tbar\nENCODING 358\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n40\nE0\n40\n40\n40\n00\nENDCHAR\nSTARTCHAR tbar\nENCODING 359\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\nE0\n40\nE0\n40\n30\n00\nENDCHAR\nSTARTCHAR Utilde\nENCODING 360\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR utilde\nENCODING 361\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\nA0\n90\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR Umacron\nENCODING 362\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR umacron\nENCODING 363\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n00\n90\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR Ubreve\nENCODING 364\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR ubreve\nENCODING 365\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n60\n00\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR Uring\nENCODING 366\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uring\nENCODING 367\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n60\n00\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR Uhungarumlaut\nENCODING 368\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uhungarumlaut\nENCODING 369\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n48\n90\n00\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR Uogonek\nENCODING 370\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\n90\n60\n40\nENDCHAR\nSTARTCHAR uogonek\nENCODING 371\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n90\n90\n70\n20\nENDCHAR\nSTARTCHAR Wcircumflex\nENCODING 372\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\nF0\nF0\n90\n00\nENDCHAR\nSTARTCHAR wcircumflex\nENCODING 373\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n00\n90\nF0\nF0\n00\nENDCHAR\nSTARTCHAR Ycircumflex\nENCODING 374\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nA0\nA0\n40\n40\n40\n00\nENDCHAR\nSTARTCHAR ycircumflex\nENCODING 375\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n00\n90\n50\n20\n40\nENDCHAR\nSTARTCHAR Ydieresis\nENCODING 376\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nA0\nA0\n40\n40\n40\n00\nENDCHAR\nSTARTCHAR Zacute\nENCODING 377\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n10\n20\n40\n80\nF0\n00\nENDCHAR\nSTARTCHAR zacute\nENCODING 378\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\nF0\n20\n40\nF0\n00\nENDCHAR\nSTARTCHAR Zdotaccent\nENCODING 379\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n10\n20\n40\n80\nF0\n00\nENDCHAR\nSTARTCHAR zdotaccent\nENCODING 380\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n00\nF0\n20\n40\nF0\n00\nENDCHAR\nSTARTCHAR Zcaron\nENCODING 381\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n10\n20\n40\n80\nF0\n00\nENDCHAR\nSTARTCHAR zcaron\nENCODING 382\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n20\nF0\n20\n40\nF0\n00\nENDCHAR\nSTARTCHAR longs\nENCODING 383\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n20\n60\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR uni0180\nENCODING 384\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\nE0\n40\n60\n50\n60\n00\nENDCHAR\nSTARTCHAR uni0181\nENCODING 385\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n50\n60\n50\n50\n60\n00\nENDCHAR\nSTARTCHAR uni0182\nENCODING 386\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n80\nE0\n90\n90\nE0\n00\nENDCHAR\nSTARTCHAR uni0183\nENCODING 387\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n40\n60\n50\n50\n60\n00\nENDCHAR\nSTARTCHAR uni0184\nENCODING 388\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\nC0\nF0\n48\n48\n70\n00\nENDCHAR\nSTARTCHAR uni0185\nENCODING 389\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\nC0\n60\n50\n50\n60\n00\nENDCHAR\nSTARTCHAR uni0186\nENCODING 390\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n10\n10\n90\n60\n00\nENDCHAR\nSTARTCHAR uni0187\nENCODING 391\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n68\n90\n80\n80\n90\n60\n00\nENDCHAR\nSTARTCHAR uni0188\nENCODING 392\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n10\n60\n80\n80\n60\n00\nENDCHAR\nSTARTCHAR uni0189\nENCODING 393\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n50\nD0\n50\n50\nE0\n00\nENDCHAR\nSTARTCHAR uni018A\nENCODING 394\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n50\n50\n50\n50\n60\n00\nENDCHAR\nSTARTCHAR uni018B\nENCODING 395\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n10\n70\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR uni018C\nENCODING 396\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n10\n30\n50\n50\n30\n00\nENDCHAR\nSTARTCHAR uni018D\nENCODING 397\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n90\n60\n10\n60\nENDCHAR\nSTARTCHAR uni018E\nENCODING 398\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n10\n70\n10\n10\nF0\n00\nENDCHAR\nSTARTCHAR uni018F\nENCODING 399\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n10\nF0\n90\n60\n00\nENDCHAR\nSTARTCHAR uni0190\nENCODING 400\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n40\n80\n90\n60\n00\nENDCHAR\nSTARTCHAR uni0191\nENCODING 401\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n40\n60\n40\n40\n40\n80\nENDCHAR\nSTARTCHAR florin\nENCODING 402\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n40\nE0\n40\n40\n80\nENDCHAR\nSTARTCHAR uni0193\nENCODING 403\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n90\n80\nB0\n90\n70\n00\nENDCHAR\nSTARTCHAR uni0194\nENCODING 404\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n90\n90\n60\n90\n60\n00\nENDCHAR\nSTARTCHAR uni0195\nENCODING 405\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n80\nC8\nA8\nA8\n90\n00\nENDCHAR\nSTARTCHAR uni0196\nENCODING 406\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n20\n20\n20\n10\n00\nENDCHAR\nSTARTCHAR uni0197\nENCODING 407\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n70\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni0198\nENCODING 408\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n80\nC0\nA0\n90\n00\nENDCHAR\nSTARTCHAR uni0199\nENCODING 409\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n80\nA0\nC0\nA0\n90\n00\nENDCHAR\nSTARTCHAR uni019A\nENCODING 410\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n70\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni019B\nENCODING 411\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n30\n60\n20\n50\n50\n00\nENDCHAR\nSTARTCHAR uni019C\nENCODING 412\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\nF0\n50\n00\nENDCHAR\nSTARTCHAR uni019D\nENCODING 413\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n48\n68\n68\n58\n58\n48\n80\nENDCHAR\nSTARTCHAR uni019E\nENCODING 414\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\n90\n90\n90\n10\nENDCHAR\nSTARTCHAR uni019F\nENCODING 415\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\nF0\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR Ohorn\nENCODING 416\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n68\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR ohorn\nENCODING 417\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n08\n70\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni01A2\nENCODING 418\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\nA8\nA8\nA8\nA8\n40\n00\nENDCHAR\nSTARTCHAR uni01A3\nENCODING 419\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\nA8\nA8\n48\n00\nENDCHAR\nSTARTCHAR uni01A4\nENCODING 420\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n50\n50\n60\n40\n40\n00\nENDCHAR\nSTARTCHAR uni01A5\nENCODING 421\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n80\nE0\n90\n90\nE0\n80\nENDCHAR\nSTARTCHAR uni01A6\nENCODING 422\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\nE0\n90\nE0\nC0\nA0\n10\nENDCHAR\nSTARTCHAR uni01A7\nENCODING 423\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n20\n40\n90\n60\n00\nENDCHAR\nSTARTCHAR uni01A8\nENCODING 424\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\n30\nC0\n70\n00\nENDCHAR\nSTARTCHAR uni01A9\nENCODING 425\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\n40\n40\n80\nF0\n00\nENDCHAR\nSTARTCHAR uni01AA\nENCODING 426\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\nA0\n70\n20\n20\n20\n10\nENDCHAR\nSTARTCHAR uni01AB\nENCODING 427\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n40\nE0\n40\n70\n10\n20\nENDCHAR\nSTARTCHAR uni01AC\nENCODING 428\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\nA0\nA0\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR uni01AD\nENCODING 429\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n40\nE0\n40\n40\n30\n00\nENDCHAR\nSTARTCHAR uni01AE\nENCODING 430\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n40\n40\n40\n40\n40\n30\nENDCHAR\nSTARTCHAR Uhorn\nENCODING 431\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n98\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uhorn\nENCODING 432\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n08\n90\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR uni01B1\nENCODING 433\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n88\n88\n88\n88\n70\n00\nENDCHAR\nSTARTCHAR uni01B2\nENCODING 434\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni01B3\nENCODING 435\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n50\n50\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR uni01B4\nENCODING 436\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\nA0\nA0\n40\n80\nENDCHAR\nSTARTCHAR uni01B5\nENCODING 437\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n10\nF0\n40\n80\nF0\n00\nENDCHAR\nSTARTCHAR uni01B6\nENCODING 438\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF0\n70\n40\nF0\n00\nENDCHAR\nSTARTCHAR uni01B7\nENCODING 439\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n20\n60\n10\n10\nE0\n00\nENDCHAR\nSTARTCHAR uni01B8\nENCODING 440\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n40\n60\n80\n80\n70\n00\nENDCHAR\nSTARTCHAR uni01B9\nENCODING 441\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF0\n40\n60\n80\n70\nENDCHAR\nSTARTCHAR uni01BA\nENCODING 442\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF0\n20\n60\n30\nF8\nENDCHAR\nSTARTCHAR uni01BB\nENCODING 443\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n10\nF0\n40\nF0\n00\nENDCHAR\nSTARTCHAR uni01BC\nENCODING 444\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nE0\n90\n10\nE0\n00\nENDCHAR\nSTARTCHAR uni01BD\nENCODING 445\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\n60\n10\n60\n00\nENDCHAR\nSTARTCHAR uni01BE\nENCODING 446\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n70\n20\n10\n60\n00\nENDCHAR\nSTARTCHAR uni01BF\nENCODING 447\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\n90\nA0\nC0\n80\nENDCHAR\nSTARTCHAR uni01C0\nENCODING 448\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n20\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR uni01C1\nENCODING 449\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n50\n50\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR uni01C2\nENCODING 450\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n70\n20\n70\n20\n00\nENDCHAR\nSTARTCHAR uni01C3\nENCODING 451\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n20\n20\n00\n20\n00\nENDCHAR\nSTARTCHAR uni01C4\nENCODING 452\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n18\nD8\nA8\nA8\nB0\nD8\n00\nENDCHAR\nSTARTCHAR uni01C5\nENCODING 453\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD8\nA0\nB8\nA8\nB0\nD8\n00\nENDCHAR\nSTARTCHAR uni01C6\nENCODING 454\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n38\n20\n78\nA8\nB0\n78\n00\nENDCHAR\nSTARTCHAR uni01C7\nENCODING 455\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n88\n88\n88\n88\nA8\nD0\n00\nENDCHAR\nSTARTCHAR uni01C8\nENCODING 456\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n88\n80\n88\n88\n88\nE8\n10\nENDCHAR\nSTARTCHAR uni01C9\nENCODING 457\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nC8\n40\n48\n48\n48\nE8\n10\nENDCHAR\nSTARTCHAR uni01CA\nENCODING 458\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nC8\nA8\nA8\nA8\nA8\nB0\n00\nENDCHAR\nSTARTCHAR uni01CB\nENCODING 459\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nC8\nA0\nA8\nA8\nA8\nA8\n10\nENDCHAR\nSTARTCHAR uni01CC\nENCODING 460\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n08\n00\nC8\nA8\nA8\nA8\n10\nENDCHAR\nSTARTCHAR uni01CD\nENCODING 461\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR uni01CE\nENCODING 462\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n20\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR uni01CF\nENCODING 463\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni01D0\nENCODING 464\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n20\n60\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni01D1\nENCODING 465\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni01D2\nENCODING 466\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\n40\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni01D3\nENCODING 467\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni01D4\nENCODING 468\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n20\n90\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR uni01D5\nENCODING 469\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni01D6\nENCODING 470\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n50\n00\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR uni01D7\nENCODING 471\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni01D8\nENCODING 472\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n70\n00\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR uni01D9\nENCODING 473\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni01DA\nENCODING 474\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n70\n00\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR uni01DB\nENCODING 475\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni01DC\nENCODING 476\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n70\n00\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR uni01DD\nENCODING 477\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n30\nD0\n60\n00\nENDCHAR\nSTARTCHAR uni01DE\nENCODING 478\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR uni01DF\nENCODING 479\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n50\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR uni01E0\nENCODING 480\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR uni01E1\nENCODING 481\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR uni01E2\nENCODING 482\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n70\nA0\nF0\nA0\nB0\n00\nENDCHAR\nSTARTCHAR uni01E3\nENCODING 483\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n00\n70\nB0\nA0\n70\n00\nENDCHAR\nSTARTCHAR uni01E4\nENCODING 484\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n80\nB0\nB8\n70\n00\nENDCHAR\nSTARTCHAR uni01E5\nENCODING 485\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\n90\n60\nB8\n70\nENDCHAR\nSTARTCHAR Gcaron\nENCODING 486\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n80\nB0\n90\n70\n00\nENDCHAR\nSTARTCHAR gcaron\nENCODING 487\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n20\n70\n90\n60\n80\n70\nENDCHAR\nSTARTCHAR uni01E8\nENCODING 488\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nA0\nC0\nC0\nA0\n90\n00\nENDCHAR\nSTARTCHAR uni01E9\nENCODING 489\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nA0\n80\nA0\nC0\nA0\n00\nENDCHAR\nSTARTCHAR uni01EA\nENCODING 490\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\n90\n90\n60\n40\nENDCHAR\nSTARTCHAR uni01EB\nENCODING 491\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n90\n90\n60\n40\nENDCHAR\nSTARTCHAR uni01EC\nENCODING 492\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\n90\n90\n60\n40\nENDCHAR\nSTARTCHAR uni01ED\nENCODING 493\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n00\n60\n90\n90\n60\n40\nENDCHAR\nSTARTCHAR uni01EE\nENCODING 494\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n20\n60\n10\n10\nE0\n00\nENDCHAR\nSTARTCHAR uni01EF\nENCODING 495\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n20\nF0\n20\n60\n10\nE0\nENDCHAR\nSTARTCHAR uni01F0\nENCODING 496\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n20\n00\n20\n20\nA0\n40\nENDCHAR\nSTARTCHAR uni01F1\nENCODING 497\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD8\nA8\nA8\nB0\nB0\nD8\n00\nENDCHAR\nSTARTCHAR uni01F2\nENCODING 498\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nC0\nA0\nB8\nA8\nB0\nD8\n00\nENDCHAR\nSTARTCHAR uni01F3\nENCODING 499\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n78\nA8\nB0\n78\n00\nENDCHAR\nSTARTCHAR uni01F4\nENCODING 500\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n80\nB0\n90\n70\n00\nENDCHAR\nSTARTCHAR uni01F5\nENCODING 501\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n20\n70\n90\n60\n80\n70\nENDCHAR\nSTARTCHAR uni01F6\nENCODING 502\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nA0\nE8\nA8\nA8\n90\n00\nENDCHAR\nSTARTCHAR uni01F7\nENCODING 503\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\nA0\nC0\n80\n80\n00\nENDCHAR\nSTARTCHAR uni01F8\nENCODING 504\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nD0\nD0\nB0\nB0\n90\n00\nENDCHAR\nSTARTCHAR uni01F9\nENCODING 505\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\nE0\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR Aringacute\nENCODING 506\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR aringacute\nENCODING 507\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n60\n60\n90\n70\n00\nENDCHAR\nSTARTCHAR AEacute\nENCODING 508\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\nA0\nB0\nE0\nA0\nB0\n00\nENDCHAR\nSTARTCHAR aeacute\nENCODING 509\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n20\n70\nB0\nA0\n70\n00\nENDCHAR\nSTARTCHAR Oslashacute\nENCODING 510\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\nB0\nB0\nD0\nD0\nE0\n00\nENDCHAR\nSTARTCHAR oslashacute\nENCODING 511\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n20\n70\nB0\nD0\nE0\n00\nENDCHAR\nSTARTCHAR uni0200\nENCODING 512\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR uni0201\nENCODING 513\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\n50\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR uni0202\nENCODING 514\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR uni0203\nENCODING 515\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR uni0204\nENCODING 516\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nE0\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR uni0205\nENCODING 517\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\n50\n60\nB0\nC0\n60\n00\nENDCHAR\nSTARTCHAR uni0206\nENCODING 518\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nE0\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR uni0207\nENCODING 519\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n60\nB0\nC0\n60\n00\nENDCHAR\nSTARTCHAR uni0208\nENCODING 520\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni0209\nENCODING 521\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\n50\n60\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni020A\nENCODING 522\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni020B\nENCODING 523\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n60\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni020C\nENCODING 524\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni020D\nENCODING 525\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\n50\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni020E\nENCODING 526\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni020F\nENCODING 527\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni0210\nENCODING 528\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\n90\nE0\nA0\n90\n00\nENDCHAR\nSTARTCHAR uni0211\nENCODING 529\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\n50\nE0\n90\n80\n80\n00\nENDCHAR\nSTARTCHAR uni0212\nENCODING 530\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\n90\nE0\nA0\n90\n00\nENDCHAR\nSTARTCHAR uni0213\nENCODING 531\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\nE0\n90\n80\n80\n00\nENDCHAR\nSTARTCHAR uni0214\nENCODING 532\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni0215\nENCODING 533\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\n50\n90\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR uni0216\nENCODING 534\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni0217\nENCODING 535\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR Scommaaccent\nENCODING 536\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n40\n20\n90\n60\nC0\nENDCHAR\nSTARTCHAR scommaaccent\nENCODING 537\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\nC0\n30\nE0\nC0\nENDCHAR\nSTARTCHAR Tcommaaccent\nENCODING 538\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n20\n40\nENDCHAR\nSTARTCHAR tcommaaccent\nENCODING 539\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n40\nE0\n40\n40\n30\n40\nENDCHAR\nSTARTCHAR uni021C\nENCODING 540\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n10\n20\n10\nE0\n00\nENDCHAR\nSTARTCHAR uni021D\nENCODING 541\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\nB0\n50\n20\nC0\nENDCHAR\nSTARTCHAR uni021E\nENCODING 542\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\nF0\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR uni021F\nENCODING 543\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\nA0\n80\nE0\n90\n90\n00\nENDCHAR\nSTARTCHAR uni0250\nENCODING 592\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nA0\nD0\n90\nE0\n00\nENDCHAR\nSTARTCHAR uni0251\nENCODING 593\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR uni0252\nENCODING 594\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\n90\n90\nE0\n00\nENDCHAR\nSTARTCHAR uni0253\nENCODING 595\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n80\nE0\n90\n90\nE0\n00\nENDCHAR\nSTARTCHAR uni0254\nENCODING 596\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n10\n10\n60\n00\nENDCHAR\nSTARTCHAR uni0255\nENCODING 597\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n80\nB0\n60\n80\nENDCHAR\nSTARTCHAR uni0256\nENCODING 598\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n10\n70\n90\n90\n70\n18\nENDCHAR\nSTARTCHAR uni0257\nENCODING 599\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n18\n10\n70\n90\n90\n70\n00\nENDCHAR\nSTARTCHAR uni0258\nENCODING 600\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\nD0\n30\n60\n00\nENDCHAR\nSTARTCHAR uni0259\nENCODING 601\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n30\nD0\n60\n00\nENDCHAR\nSTARTCHAR uni025A\nENCODING 602\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n38\nD0\n60\n00\nENDCHAR\nSTARTCHAR uni025B\nENCODING 603\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n30\n20\n40\n30\n00\nENDCHAR\nSTARTCHAR uni025C\nENCODING 604\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n20\n10\n60\n00\nENDCHAR\nSTARTCHAR uni025D\nENCODING 605\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF0\n40\n20\nC0\n00\nENDCHAR\nSTARTCHAR uni025E\nENCODING 606\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\nA0\n90\n60\n00\nENDCHAR\nSTARTCHAR uni025F\nENCODING 607\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n20\n70\n20\nA0\n40\nENDCHAR\nSTARTCHAR uni0260\nENCODING 608\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n08\n70\n90\n70\n10\n60\nENDCHAR\nSTARTCHAR uni0261\nENCODING 609\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\n90\n70\n10\n60\nENDCHAR\nSTARTCHAR uni0262\nENCODING 610\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\n80\n90\n70\n00\nENDCHAR\nSTARTCHAR uni0263\nENCODING 611\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n50\n20\n50\n20\nENDCHAR\nSTARTCHAR uni0264\nENCODING 612\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n20\n50\n20\n00\nENDCHAR\nSTARTCHAR uni0265\nENCODING 613\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n90\n90\n70\n10\nENDCHAR\nSTARTCHAR uni0266\nENCODING 614\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n80\nE0\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR uni0267\nENCODING 615\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n80\nE0\n90\n90\n90\n20\nENDCHAR\nSTARTCHAR uni0268\nENCODING 616\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n00\n20\n70\n20\n70\n00\nENDCHAR\nSTARTCHAR uni0269\nENCODING 617\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR uni026A\nENCODING 618\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\n40\n40\nE0\n00\nENDCHAR\nSTARTCHAR uni026B\nENCODING 619\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n68\nB0\n20\n70\n00\nENDCHAR\nSTARTCHAR uni026C\nENCODING 620\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n60\n70\n20\n70\n00\nENDCHAR\nSTARTCHAR uni026D\nENCODING 621\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n20\n20\n20\n20\n10\nENDCHAR\nSTARTCHAR uni026E\nENCODING 622\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n80\nE0\n90\n90\nA0\n60\nENDCHAR\nSTARTCHAR uni026F\nENCODING 623\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n90\nF0\n50\n00\nENDCHAR\nSTARTCHAR uni0270\nENCODING 624\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n90\nF0\n50\n10\nENDCHAR\nSTARTCHAR uni0271\nENCODING 625\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nA0\nF0\n90\n90\n20\nENDCHAR\nSTARTCHAR uni0272\nENCODING 626\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n50\n50\n50\n80\nENDCHAR\nSTARTCHAR uni0273\nENCODING 627\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nC0\nA0\nA0\nA0\n10\nENDCHAR\nSTARTCHAR uni0274\nENCODING 628\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\nD0\nB0\n90\n00\nENDCHAR\nSTARTCHAR uni0275\nENCODING 629\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n60\n90\nF0\n90\n60\n00\nENDCHAR\nSTARTCHAR uni0276\nENCODING 630\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\nB0\nA0\n70\n00\nENDCHAR\nSTARTCHAR uni0277\nENCODING 631\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n90\nF0\nF0\n00\nENDCHAR\nSTARTCHAR uni0278\nENCODING 632\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n70\nA8\n70\n20\n00\nENDCHAR\nSTARTCHAR uni0279\nENCODING 633\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n10\n10\n90\n70\n00\nENDCHAR\nSTARTCHAR uni027A\nENCODING 634\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n10\n10\n10\n90\n70\n00\nENDCHAR\nSTARTCHAR uni027B\nENCODING 635\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n20\nA0\n60\n30\n00\nENDCHAR\nSTARTCHAR uni027C\nENCODING 636\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\nE0\n90\n80\n80\n80\n80\nENDCHAR\nSTARTCHAR uni027D\nENCODING 637\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\nE0\n90\n80\n80\n80\n40\nENDCHAR\nSTARTCHAR uni027E\nENCODING 638\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n90\n80\n80\n00\nENDCHAR\nSTARTCHAR uni027F\nENCODING 639\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n90\n10\n10\n00\nENDCHAR\nSTARTCHAR uni0280\nENCODING 640\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\n90\nE0\n90\n00\nENDCHAR\nSTARTCHAR uni0281\nENCODING 641\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\nE0\n90\nE0\n00\nENDCHAR\nSTARTCHAR uni0282\nENCODING 642\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\nC0\n30\nE0\n80\nENDCHAR\nSTARTCHAR uni0283\nENCODING 643\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n20\n20\n20\n20\n20\n40\nENDCHAR\nSTARTCHAR uni0284\nENCODING 644\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n20\n20\n20\n70\n20\n40\nENDCHAR\nSTARTCHAR uni0285\nENCODING 645\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\n20\n20\n10\n00\nENDCHAR\nSTARTCHAR uni0286\nENCODING 646\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n20\n20\n20\n70\nA0\n40\nENDCHAR\nSTARTCHAR uni0287\nENCODING 647\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\nC0\n20\n20\n70\n20\n20\nENDCHAR\nSTARTCHAR uni0288\nENCODING 648\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n40\nE0\n40\n40\n40\n30\nENDCHAR\nSTARTCHAR uni0289\nENCODING 649\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\nF0\n90\n70\n00\nENDCHAR\nSTARTCHAR uni028A\nENCODING 650\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni028B\nENCODING 651\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nA0\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni028C\nENCODING 652\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n20\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR uni028D\nENCODING 653\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF0\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR uni028E\nENCODING 654\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n40\nA0\n90\n90\n00\nENDCHAR\nSTARTCHAR uni028F\nENCODING 655\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nA0\n40\n40\n40\n00\nENDCHAR\nSTARTCHAR uni0290\nENCODING 656\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF0\n20\n40\nF0\n10\nENDCHAR\nSTARTCHAR uni0291\nENCODING 657\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF0\n20\n50\nF0\n40\nENDCHAR\nSTARTCHAR uni0292\nENCODING 658\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF0\n20\n60\n10\nE0\nENDCHAR\nSTARTCHAR uni0293\nENCODING 659\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF0\n20\n60\n50\n78\nENDCHAR\nSTARTCHAR uni0294\nENCODING 660\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n60\n10\n30\n20\n20\n00\nENDCHAR\nSTARTCHAR uni0295\nENCODING 661\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n30\n40\n60\n20\n20\n00\nENDCHAR\nSTARTCHAR uni0296\nENCODING 662\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n20\n30\n10\n60\n00\nENDCHAR\nSTARTCHAR uni0297\nENCODING 663\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n50\n40\n40\n50\n20\nENDCHAR\nSTARTCHAR uni0298\nENCODING 664\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n70\n88\nA8\n88\n70\n00\nENDCHAR\nSTARTCHAR uni0299\nENCODING 665\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\nE0\n90\nE0\n00\nENDCHAR\nSTARTCHAR uni029A\nENCODING 666\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n50\n90\n60\n00\nENDCHAR\nSTARTCHAR uni029B\nENCODING 667\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n18\n70\n80\n90\n70\n00\nENDCHAR\nSTARTCHAR uni029C\nENCODING 668\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR uni029D\nENCODING 669\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n00\n20\n20\n70\nA0\n40\nENDCHAR\nSTARTCHAR uni029E\nENCODING 670\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n50\n30\n50\n10\nENDCHAR\nSTARTCHAR uni029F\nENCODING 671\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n80\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR uni02A0\nENCODING 672\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n18\n70\n90\n90\n70\n10\nENDCHAR\nSTARTCHAR uni02A1\nENCODING 673\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n60\n10\n20\n70\n20\n00\nENDCHAR\nSTARTCHAR uni02A2\nENCODING 674\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n30\n40\n20\n70\n20\n00\nENDCHAR\nSTARTCHAR uni02A3\nENCODING 675\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n78\nA8\nB0\n78\n00\nENDCHAR\nSTARTCHAR uni02A4\nENCODING 676\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n78\nA8\nB0\n68\n10\nENDCHAR\nSTARTCHAR uni02A5\nENCODING 677\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n78\nA8\nB8\n78\n00\nENDCHAR\nSTARTCHAR uni02A6\nENCODING 678\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n40\nE8\n50\n48\n30\n00\nENDCHAR\nSTARTCHAR uni02A7\nENCODING 679\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n48\n50\nF0\n50\n50\n30\n20\nENDCHAR\nSTARTCHAR uni02A8\nENCODING 680\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n40\nE8\n50\n50\n38\n10\nENDCHAR\nSTARTCHAR uni02B6\nENCODING 694\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nC0\nA0\nC0\n00\n00\n00\nENDCHAR\nSTARTCHAR uni02B8\nENCODING 696\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n80\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni02B9\nENCODING 697\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\nA0\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR afii57929\nENCODING 700\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n20\n40\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR afii64937\nENCODING 701\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n10\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR circumflex\nENCODING 710\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR caron\nENCODING 711\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n20\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni02C8\nENCODING 712\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR macron\nENCODING 713\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni02CC\nENCODING 716\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\n20\n20\nENDCHAR\nSTARTCHAR uni02D0\nENCODING 720\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n70\n20\n00\n20\n70\n00\nENDCHAR\nSTARTCHAR uni02D6\nENCODING 726\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n20\n70\n20\n00\n00\nENDCHAR\nSTARTCHAR breve\nENCODING 728\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n60\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR dotaccent\nENCODING 729\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR ring\nENCODING 730\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n20\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR ogonek\nENCODING 731\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\n20\n30\nENDCHAR\nSTARTCHAR tilde\nENCODING 732\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\nA0\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR hungarumlaut\nENCODING 733\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n48\n90\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR gravecomb\nENCODING 768\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR acutecomb\nENCODING 769\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0302\nENCODING 770\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR tildecomb\nENCODING 771\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\nA0\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0304\nENCODING 772\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0305\nENCODING 773\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF8\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0306\nENCODING 774\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n60\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0307\nENCODING 775\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0308\nENCODING 776\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR hookabovecomb\nENCODING 777\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni030A\nENCODING 778\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n60\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni030B\nENCODING 779\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n48\n90\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni030C\nENCODING 780\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n20\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni030D\nENCODING 781\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni030E\nENCODING 782\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni030F\nENCODING 783\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n48\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0310\nENCODING 784\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA8\n70\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0311\nENCODING 785\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR dotbelowcomb\nENCODING 803\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\n00\n20\nENDCHAR\nSTARTCHAR uni0324\nENCODING 804\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\n00\n50\nENDCHAR\nSTARTCHAR uni0338\nENCODING 824\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n20\n20\n40\n40\n80\n00\nENDCHAR\nSTARTCHAR uni0340\nENCODING 832\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0341\nENCODING 833\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0374\nENCODING 884\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0375\nENCODING 885\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\n20\n40\nENDCHAR\nSTARTCHAR uni037A\nENCODING 890\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\n00\n40\nENDCHAR\nSTARTCHAR uni037E\nENCODING 894\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n60\n60\n00\n60\n40\n80\nENDCHAR\nSTARTCHAR tonos\nENCODING 900\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR dieresistonos\nENCODING 901\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nB0\n40\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR Alphatonos\nENCODING 902\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n70\n50\n50\n00\nENDCHAR\nSTARTCHAR anoteleia\nENCODING 903\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n60\n00\n00\n00\nENDCHAR\nSTARTCHAR Epsilontonos\nENCODING 904\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nC0\n60\n40\n40\n70\n00\nENDCHAR\nSTARTCHAR Etatonos\nENCODING 905\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n70\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR Iotatonos\nENCODING 906\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nA0\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR Omicrontonos\nENCODING 908\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n50\n20\n00\nENDCHAR\nSTARTCHAR Upsilontonos\nENCODING 910\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n50\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR Omegatonos\nENCODING 911\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n20\n50\n00\nENDCHAR\nSTARTCHAR iotadieresistonos\nENCODING 912\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nB0\n40\n00\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR Alpha\nENCODING 913\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR Beta\nENCODING 914\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\nE0\n90\n90\nE0\n00\nENDCHAR\nSTARTCHAR Gamma\nENCODING 915\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\n80\n80\n80\n80\n00\nENDCHAR\nSTARTCHAR Delta\nENCODING 916\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n60\n90\n90\n90\nF0\n00\nENDCHAR\nSTARTCHAR Epsilon\nENCODING 917\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nE0\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR Zeta\nENCODING 918\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n10\n20\n40\n80\nF0\n00\nENDCHAR\nSTARTCHAR Eta\nENCODING 919\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\nF0\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR Theta\nENCODING 920\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\nF0\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR Iota\nENCODING 921\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR Kappa\nENCODING 922\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nA0\nC0\nC0\nA0\n90\n00\nENDCHAR\nSTARTCHAR Lambda\nENCODING 923\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n60\n60\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR Mu\nENCODING 924\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nF0\nF0\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR Nu\nENCODING 925\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nD0\nD0\nB0\nB0\n90\n00\nENDCHAR\nSTARTCHAR Xi\nENCODING 926\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n00\n60\n00\n00\nF0\n00\nENDCHAR\nSTARTCHAR Omicron\nENCODING 927\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR Pi\nENCODING 928\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n90\n90\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR Rho\nENCODING 929\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\n90\nE0\n80\n80\n00\nENDCHAR\nSTARTCHAR Sigma\nENCODING 931\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\n40\n40\n80\nF0\n00\nENDCHAR\nSTARTCHAR Tau\nENCODING 932\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR Upsilon\nENCODING 933\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n50\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR Phi\nENCODING 934\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n70\n50\n50\n70\n20\n00\nENDCHAR\nSTARTCHAR Chi\nENCODING 935\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n60\n60\n90\n90\n00\nENDCHAR\nSTARTCHAR Psi\nENCODING 936\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n70\n70\n70\n20\n20\n00\nENDCHAR\nSTARTCHAR Omega\nENCODING 937\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n50\n50\n20\n50\n00\nENDCHAR\nSTARTCHAR Iotadieresis\nENCODING 938\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n70\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR Upsilondieresis\nENCODING 939\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\n00\nA0\nA0\n40\n40\n00\nENDCHAR\nSTARTCHAR alphatonos\nENCODING 940\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n20\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR epsilontonos\nENCODING 941\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n20\n70\n20\n40\n30\n00\nENDCHAR\nSTARTCHAR etatonos\nENCODING 942\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\nE0\n90\n90\n90\n10\nENDCHAR\nSTARTCHAR iotatonos\nENCODING 943\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n00\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR upsilondieresistonos\nENCODING 944\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nB0\n40\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR alpha\nENCODING 945\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR beta\nENCODING 946\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\nE0\n90\n90\nE0\n80\nENDCHAR\nSTARTCHAR gamma\nENCODING 947\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n50\n20\n20\n20\nENDCHAR\nSTARTCHAR delta\nENCODING 948\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n80\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR epsilon\nENCODING 949\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\n20\n40\n30\n00\nENDCHAR\nSTARTCHAR zeta\nENCODING 950\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n40\n80\n80\n80\n70\n10\nENDCHAR\nSTARTCHAR eta\nENCODING 951\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\n90\n90\n90\n10\nENDCHAR\nSTARTCHAR theta\nENCODING 952\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n70\n50\n50\n20\n00\nENDCHAR\nSTARTCHAR iota\nENCODING 953\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR kappa\nENCODING 954\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\nA0\nE0\n90\n00\nENDCHAR\nSTARTCHAR lambda\nENCODING 955\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n10\n50\nB0\n90\n90\n00\nENDCHAR\nSTARTCHAR mu\nENCODING 956\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n90\n90\nF0\n80\nENDCHAR\nSTARTCHAR nu\nENCODING 957\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n50\n50\n20\n00\nENDCHAR\nSTARTCHAR xi\nENCODING 958\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n40\n80\n60\n80\n70\n10\nENDCHAR\nSTARTCHAR omicron\nENCODING 959\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR pi\nENCODING 960\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR rho\nENCODING 961\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n90\n90\nE0\n80\nENDCHAR\nSTARTCHAR sigma1\nENCODING 962\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\nC0\n30\n60\n00\nENDCHAR\nSTARTCHAR sigma\nENCODING 963\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\nA0\n90\n60\n00\nENDCHAR\nSTARTCHAR tau\nENCODING 964\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF0\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR upsilon\nENCODING 965\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR phi\nENCODING 966\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n20\n70\n50\n70\n20\nENDCHAR\nSTARTCHAR chi\nENCODING 967\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n60\n60\n90\n90\nENDCHAR\nSTARTCHAR psi\nENCODING 968\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n70\n70\n20\n20\nENDCHAR\nSTARTCHAR omega\nENCODING 969\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n90\nF0\nF0\n00\nENDCHAR\nSTARTCHAR iotadieresis\nENCODING 970\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\n00\n40\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR upsilondieresis\nENCODING 971\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n00\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR omicrontonos\nENCODING 972\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR upsilontonos\nENCODING 973\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR omegatonos\nENCODING 974\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n90\n90\nF0\nF0\n00\nENDCHAR\nSTARTCHAR uni03D0\nENCODING 976\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\nA0\nD0\n90\n60\n00\nENDCHAR\nSTARTCHAR theta1\nENCODING 977\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n70\n10\n90\n60\n00\nENDCHAR\nSTARTCHAR Upsilon1\nENCODING 978\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n50\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR uni03D3\nENCODING 979\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n50\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR uni03D4\nENCODING 980\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n50\n50\n20\n20\n00\nENDCHAR\nSTARTCHAR phi1\nENCODING 981\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n20\n70\n50\n70\n20\nENDCHAR\nSTARTCHAR omega1\nENCODING 982\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF0\n90\nF0\nF0\n00\nENDCHAR\nSTARTCHAR uni03D7\nENCODING 983\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n90\n60\n60\n90\n30\nENDCHAR\nSTARTCHAR uni03DA\nENCODING 986\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n80\n80\n60\n10\n20\nENDCHAR\nSTARTCHAR uni03DB\nENCODING 987\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\nC0\n30\n60\n00\nENDCHAR\nSTARTCHAR uni03DC\nENCODING 988\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nE0\n80\n80\n80\n00\nENDCHAR\nSTARTCHAR uni03DD\nENCODING 989\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\n40\n60\n40\n40\nENDCHAR\nSTARTCHAR uni03DE\nENCODING 990\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n90\nB0\nD0\n90\n10\n00\nENDCHAR\nSTARTCHAR uni03DF\nENCODING 991\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n40\n80\nF0\n10\n20\n20\nENDCHAR\nSTARTCHAR uni03E0\nENCODING 992\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n60\n60\n90\nB0\nB0\n00\nENDCHAR\nSTARTCHAR uni03E1\nENCODING 993\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nC0\n20\n50\nB0\n50\n10\n10\nENDCHAR\nSTARTCHAR uni03F0\nENCODING 1008\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n60\n60\nB0\n00\nENDCHAR\nSTARTCHAR uni03F1\nENCODING 1009\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n90\nE0\n80\n60\nENDCHAR\nSTARTCHAR uni03F2\nENCODING 1010\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n30\n40\n40\n30\n00\nENDCHAR\nSTARTCHAR uni03F3\nENCODING 1011\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n10\n10\n10\n50\n20\nENDCHAR\nSTARTCHAR uni03F4\nENCODING 1012\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\nF0\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni03F5\nENCODING 1013\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n30\n60\n40\n30\n00\nENDCHAR\nSTARTCHAR afii10023\nENCODING 1025\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nE0\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR afii10051\nENCODING 1026\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n40\n60\n50\n50\n10\n20\nENDCHAR\nSTARTCHAR afii10052\nENCODING 1027\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\n80\n80\n80\n80\n00\nENDCHAR\nSTARTCHAR afii10053\nENCODING 1028\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\nC0\n80\n90\n60\n00\nENDCHAR\nSTARTCHAR afii10054\nENCODING 1029\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n40\n20\n90\n60\n00\nENDCHAR\nSTARTCHAR afii10055\nENCODING 1030\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR afii10056\nENCODING 1031\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR afii10057\nENCODING 1032\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n10\n10\n10\n90\n60\n00\nENDCHAR\nSTARTCHAR afii10058\nENCODING 1033\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\nA0\nB0\nA8\nA8\nB0\n00\nENDCHAR\nSTARTCHAR afii10059\nENCODING 1034\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nA0\nF0\nA8\nA8\nB0\n00\nENDCHAR\nSTARTCHAR afii10060\nENCODING 1035\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n40\n60\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR afii10061\nENCODING 1036\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nA0\nC0\nC0\nA0\n90\n00\nENDCHAR\nSTARTCHAR afii10062\nENCODING 1038\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n50\n20\n20\n40\n00\nENDCHAR\nSTARTCHAR afii10145\nENCODING 1039\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n50\n50\n50\n70\n20\nENDCHAR\nSTARTCHAR afii10017\nENCODING 1040\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR afii10018\nENCODING 1041\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n80\nE0\n90\n90\nE0\n00\nENDCHAR\nSTARTCHAR afii10019\nENCODING 1042\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\nE0\n90\n90\nE0\n00\nENDCHAR\nSTARTCHAR afii10020\nENCODING 1043\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\n80\n80\n80\n80\n00\nENDCHAR\nSTARTCHAR afii10021\nENCODING 1044\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n50\n50\n50\n50\nF0\n90\nENDCHAR\nSTARTCHAR afii10022\nENCODING 1045\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nE0\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR afii10024\nENCODING 1046\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA8\nA8\n70\n70\nA8\nA8\n00\nENDCHAR\nSTARTCHAR afii10025\nENCODING 1047\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n10\n60\n10\n90\n60\n00\nENDCHAR\nSTARTCHAR afii10026\nENCODING 1048\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nB0\nB0\nD0\nD0\n90\n00\nENDCHAR\nSTARTCHAR afii10027\nENCODING 1049\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nB0\nB0\nD0\nD0\n90\n00\nENDCHAR\nSTARTCHAR afii10028\nENCODING 1050\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nA0\nC0\nC0\nA0\n90\n00\nENDCHAR\nSTARTCHAR afii10029\nENCODING 1051\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n50\n50\n50\n50\n90\n00\nENDCHAR\nSTARTCHAR afii10030\nENCODING 1052\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nF0\nF0\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR afii10031\nENCODING 1053\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\nF0\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR afii10032\nENCODING 1054\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR afii10033\nENCODING 1055\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n90\n90\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR afii10034\nENCODING 1056\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 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-1\nBITMAP\nE0\n90\nA0\nC0\nA0\n80\n00\nENDCHAR\nSTARTCHAR uni16B3\nENCODING 5811\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n40\n60\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR uni16B7\nENCODING 5815\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n20\n20\n50\n50\n00\nENDCHAR\nSTARTCHAR uni16B8\nENCODING 5816\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n70\nA8\nA8\n70\n50\n00\nENDCHAR\nSTARTCHAR uni16B9\nENCODING 5817\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n50\n50\n60\n40\n40\n00\nENDCHAR\nSTARTCHAR uni16BB\nENCODING 5819\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\nD0\nB0\nD0\nB0\n00\nENDCHAR\nSTARTCHAR uni16BE\nENCODING 5822\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n60\n30\n20\n20\n00\nENDCHAR\nSTARTCHAR uni16C0\nENCODING 5824\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR uni16C4\nENCODING 5828\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n70\nA8\nA8\n70\n20\n00\nENDCHAR\nSTARTCHAR uni16C7\nENCODING 5831\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n30\n28\nA0\n60\n20\n00\nENDCHAR\nSTARTCHAR uni16C8\nENCODING 5832\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nA0\n80\n80\nA0\nD0\n00\nENDCHAR\nSTARTCHAR uni16C9\nENCODING 5833\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA8\nA8\nA8\n70\n20\n20\n00\nENDCHAR\nSTARTCHAR uni16CB\nENCODING 5835\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n90\nB0\nD0\n90\n10\n00\nENDCHAR\nSTARTCHAR uni16CF\nENCODING 5839\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n70\nA8\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR uni16D2\nENCODING 5842\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\nE0\nE0\n90\nE0\n00\nENDCHAR\nSTARTCHAR uni16D6\nENCODING 5846\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n88\nD8\nA8\n88\n88\n88\n00\nENDCHAR\nSTARTCHAR uni16D7\nENCODING 5847\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n88\nD8\nA8\nD8\n88\n88\n00\nENDCHAR\nSTARTCHAR uni16DA\nENCODING 5850\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n60\n50\n40\n40\n40\n00\nENDCHAR\nSTARTCHAR uni16DD\nENCODING 5853\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n20\n50\n50\n20\n50\n00\nENDCHAR\nSTARTCHAR uni16DE\nENCODING 5854\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n88\n88\nD8\nA8\nD8\n88\n00\nENDCHAR\nSTARTCHAR uni16DF\nENCODING 5855\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n50\n20\n50\n50\n00\nENDCHAR\nSTARTCHAR uni16E0\nENCODING 5856\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA8\n70\n20\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR uni16E1\nENCODING 5857\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA8\n70\n70\nA8\n20\n20\n00\nENDCHAR\nSTARTCHAR uni16E2\nENCODING 5858\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n28\n30\n20\n20\n60\nA0\n00\nENDCHAR\nSTARTCHAR uni16E3\nENCODING 5859\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\n70\nA8\nA8\n00\nENDCHAR\nSTARTCHAR uni16E4\nENCODING 5860\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nF0\n90\n90\nF0\n90\n00\nENDCHAR\nSTARTCHAR uni16EB\nENCODING 5867\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR uni16EC\nENCODING 5868\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n20\n00\n20\n00\n00\nENDCHAR\nSTARTCHAR uni16ED\nENCODING 5869\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n20\n50\n00\n00\nENDCHAR\nSTARTCHAR uni1E02\nENCODING 7682\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\nE0\n90\n90\nE0\n00\nENDCHAR\nSTARTCHAR uni1E03\nENCODING 7683\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n80\n80\nE0\n90\nE0\n00\nENDCHAR\nSTARTCHAR uni1E0A\nENCODING 7690\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\n90\n90\n90\nE0\n00\nENDCHAR\nSTARTCHAR uni1E0B\nENCODING 7691\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n10\n10\n70\n90\n70\n00\nENDCHAR\nSTARTCHAR uni1E1E\nENCODING 7710\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nE0\n80\n80\n80\n00\nENDCHAR\nSTARTCHAR uni1E1F\nENCODING 7711\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n20\n40\nE0\n40\n40\n00\nENDCHAR\nSTARTCHAR uni1E40\nENCODING 7744\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\nF0\nF0\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR uni1E41\nENCODING 7745\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n00\nA0\nF0\n90\n90\n00\nENDCHAR\nSTARTCHAR uni1E56\nENCODING 7766\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\n90\nE0\n80\n80\n00\nENDCHAR\nSTARTCHAR uni1E57\nENCODING 7767\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n00\nE0\n90\n90\nE0\n80\nENDCHAR\nSTARTCHAR uni1E60\nENCODING 7776\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n40\n20\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1E61\nENCODING 7777\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n00\n70\nC0\n30\nE0\n00\nENDCHAR\nSTARTCHAR uni1E6A\nENCODING 7786\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR uni1E6B\nENCODING 7787\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n20\n70\n20\n20\n10\n00\nENDCHAR\nSTARTCHAR Wgrave\nENCODING 7808\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\nF0\nF0\n90\n00\nENDCHAR\nSTARTCHAR wgrave\nENCODING 7809\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n00\n90\nF0\nF0\n00\nENDCHAR\nSTARTCHAR Wacute\nENCODING 7810\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\nF0\nF0\n90\n00\nENDCHAR\nSTARTCHAR wacute\nENCODING 7811\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n00\n90\nF0\nF0\n00\nENDCHAR\nSTARTCHAR Wdieresis\nENCODING 7812\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\nF0\nF0\n90\n00\nENDCHAR\nSTARTCHAR wdieresis\nENCODING 7813\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\nA0\n00\n90\nF0\nF0\n00\nENDCHAR\nSTARTCHAR Ygrave\nENCODING 7922\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n50\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR ygrave\nENCODING 7923\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n00\n90\n50\n20\n40\nENDCHAR\nSTARTCHAR uni1F00\nENCODING 7936\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR uni1F01\nENCODING 7937\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n40\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR uni1F02\nENCODING 7938\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n50\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR uni1F03\nENCODING 7939\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR uni1F04\nENCODING 7940\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\n60\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR uni1F05\nENCODING 7941\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nA0\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR uni1F06\nENCODING 7942\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR uni1F07\nENCODING 7943\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR uni1F08\nENCODING 7944\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n70\n50\n50\n00\nENDCHAR\nSTARTCHAR uni1F09\nENCODING 7945\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n70\n50\n50\n00\nENDCHAR\nSTARTCHAR uni1F0A\nENCODING 7946\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n70\n50\n50\n00\nENDCHAR\nSTARTCHAR uni1F0B\nENCODING 7947\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n70\n50\n50\n00\nENDCHAR\nSTARTCHAR uni1F0C\nENCODING 7948\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n70\n50\n50\n00\nENDCHAR\nSTARTCHAR uni1F0D\nENCODING 7949\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n70\n50\n50\n00\nENDCHAR\nSTARTCHAR uni1F0E\nENCODING 7950\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n70\n50\n50\n00\nENDCHAR\nSTARTCHAR uni1F0F\nENCODING 7951\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n70\n50\n50\n00\nENDCHAR\nSTARTCHAR uni1F10\nENCODING 7952\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n10\n70\n20\n40\n30\n00\nENDCHAR\nSTARTCHAR uni1F11\nENCODING 7953\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n20\n70\n20\n40\n30\n00\nENDCHAR\nSTARTCHAR uni1F12\nENCODING 7954\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n50\nE0\n40\n80\n60\n00\nENDCHAR\nSTARTCHAR uni1F13\nENCODING 7955\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\nE0\n40\n80\n60\n00\nENDCHAR\nSTARTCHAR uni1F14\nENCODING 7956\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\n60\nE0\n40\n80\n60\n00\nENDCHAR\nSTARTCHAR uni1F15\nENCODING 7957\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nA0\nE0\n40\n80\n60\n00\nENDCHAR\nSTARTCHAR uni1F18\nENCODING 7960\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nC0\n60\n40\n40\n70\n00\nENDCHAR\nSTARTCHAR uni1F19\nENCODING 7961\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nC0\n60\n40\n40\n70\n00\nENDCHAR\nSTARTCHAR uni1F1A\nENCODING 7962\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nC0\n60\n40\n40\n70\n00\nENDCHAR\nSTARTCHAR uni1F1B\nENCODING 7963\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nC0\n60\n40\n40\n70\n00\nENDCHAR\nSTARTCHAR uni1F1C\nENCODING 7964\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nC0\n60\n40\n40\n70\n00\nENDCHAR\nSTARTCHAR uni1F1D\nENCODING 7965\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nC0\n60\n40\n40\n70\n00\nENDCHAR\nSTARTCHAR uni1F20\nENCODING 7968\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\nE0\n90\n90\n90\n10\nENDCHAR\nSTARTCHAR uni1F21\nENCODING 7969\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n40\nE0\n90\n90\n90\n10\nENDCHAR\nSTARTCHAR uni1F22\nENCODING 7970\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n50\nE0\n90\n90\n90\n10\nENDCHAR\nSTARTCHAR uni1F23\nENCODING 7971\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\nE0\n90\n90\n90\n10\nENDCHAR\nSTARTCHAR uni1F24\nENCODING 7972\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\n60\nE0\n90\n90\n90\n10\nENDCHAR\nSTARTCHAR uni1F25\nENCODING 7973\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nA0\nE0\n90\n90\n90\n10\nENDCHAR\nSTARTCHAR uni1F26\nENCODING 7974\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\nE0\n90\n90\n90\n10\nENDCHAR\nSTARTCHAR uni1F27\nENCODING 7975\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\nE0\n90\n90\n90\n10\nENDCHAR\nSTARTCHAR uni1F28\nENCODING 7976\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n70\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR uni1F29\nENCODING 7977\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n70\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR uni1F2A\nENCODING 7978\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n70\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR uni1F2B\nENCODING 7979\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n70\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR uni1F2C\nENCODING 7980\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n70\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR uni1F2D\nENCODING 7981\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n70\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR uni1F2E\nENCODING 7982\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n70\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR uni1F2F\nENCODING 7983\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n70\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR uni1F30\nENCODING 7984\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n00\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR uni1F31\nENCODING 7985\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n40\n00\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR uni1F32\nENCODING 7986\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n50\n00\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR uni1F33\nENCODING 7987\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\n00\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR uni1F34\nENCODING 7988\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\n60\n00\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR uni1F35\nENCODING 7989\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nA0\n00\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR uni1F36\nENCODING 7990\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n40\n00\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR uni1F37\nENCODING 7991\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n40\n00\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR uni1F38\nENCODING 7992\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nA0\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni1F39\nENCODING 7993\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nA0\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni1F3A\nENCODING 7994\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nA0\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni1F3B\nENCODING 7995\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nA0\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni1F3C\nENCODING 7996\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nA0\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni1F3D\nENCODING 7997\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nA0\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni1F3E\nENCODING 7998\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nA0\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni1F3F\nENCODING 7999\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nA0\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni1F40\nENCODING 8000\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1F41\nENCODING 8001\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n40\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1F42\nENCODING 8002\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n50\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1F43\nENCODING 8003\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1F44\nENCODING 8004\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\n60\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1F45\nENCODING 8005\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nA0\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1F48\nENCODING 8008\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n50\n20\n00\nENDCHAR\nSTARTCHAR uni1F49\nENCODING 8009\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n50\n20\n00\nENDCHAR\nSTARTCHAR uni1F4A\nENCODING 8010\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n50\n20\n00\nENDCHAR\nSTARTCHAR uni1F4B\nENCODING 8011\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n50\n20\n00\nENDCHAR\nSTARTCHAR uni1F4C\nENCODING 8012\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n50\n20\n00\nENDCHAR\nSTARTCHAR uni1F4D\nENCODING 8013\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n50\n20\n00\nENDCHAR\nSTARTCHAR uni1F50\nENCODING 8016\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1F51\nENCODING 8017\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n40\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1F52\nENCODING 8018\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n50\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1F53\nENCODING 8019\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1F54\nENCODING 8020\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\n60\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1F55\nENCODING 8021\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nA0\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1F56\nENCODING 8022\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1F57\nENCODING 8023\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1F59\nENCODING 8025\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n50\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR uni1F5B\nENCODING 8027\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n50\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR uni1F5D\nENCODING 8029\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n50\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR uni1F5F\nENCODING 8031\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n50\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR uni1F60\nENCODING 8032\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n90\n90\nF0\nF0\n00\nENDCHAR\nSTARTCHAR uni1F61\nENCODING 8033\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n40\n90\n90\nF0\nF0\n00\nENDCHAR\nSTARTCHAR uni1F62\nENCODING 8034\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n50\n90\n90\nF0\nF0\n00\nENDCHAR\nSTARTCHAR uni1F63\nENCODING 8035\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\n90\n90\nF0\nF0\n00\nENDCHAR\nSTARTCHAR uni1F64\nENCODING 8036\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\n60\n90\n90\nF0\nF0\n00\nENDCHAR\nSTARTCHAR uni1F65\nENCODING 8037\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nA0\n90\n90\nF0\nF0\n00\nENDCHAR\nSTARTCHAR uni1F66\nENCODING 8038\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n90\n90\nF0\nF0\n00\nENDCHAR\nSTARTCHAR uni1F67\nENCODING 8039\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n90\n90\nF0\nF0\n00\nENDCHAR\nSTARTCHAR uni1F68\nENCODING 8040\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n20\n50\n00\nENDCHAR\nSTARTCHAR uni1F69\nENCODING 8041\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n20\n50\n00\nENDCHAR\nSTARTCHAR uni1F6A\nENCODING 8042\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n20\n50\n00\nENDCHAR\nSTARTCHAR uni1F6B\nENCODING 8043\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n20\n50\n00\nENDCHAR\nSTARTCHAR uni1F6C\nENCODING 8044\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n20\n50\n00\nENDCHAR\nSTARTCHAR uni1F6D\nENCODING 8045\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n20\n50\n00\nENDCHAR\nSTARTCHAR uni1F6E\nENCODING 8046\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n20\n50\n00\nENDCHAR\nSTARTCHAR uni1F6F\nENCODING 8047\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n20\n50\n00\nENDCHAR\nSTARTCHAR uni1F70\nENCODING 8048\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR uni1F71\nENCODING 8049\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n20\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR uni1F72\nENCODING 8050\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n70\n20\n40\n30\n00\nENDCHAR\nSTARTCHAR uni1F73\nENCODING 8051\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n20\n70\n20\n40\n30\n00\nENDCHAR\nSTARTCHAR uni1F74\nENCODING 8052\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n40\nE0\n90\n90\n90\n10\nENDCHAR\nSTARTCHAR uni1F75\nENCODING 8053\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\nE0\n90\n90\n90\n10\nENDCHAR\nSTARTCHAR uni1F76\nENCODING 8054\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n40\n00\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR uni1F77\nENCODING 8055\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n00\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR uni1F78\nENCODING 8056\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n40\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1F79\nENCODING 8057\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1F7A\nENCODING 8058\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1F7B\nENCODING 8059\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1F7C\nENCODING 8060\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n90\n90\nF0\nF0\n00\nENDCHAR\nSTARTCHAR uni1F7D\nENCODING 8061\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n90\n90\nF0\nF0\n00\nENDCHAR\nSTARTCHAR uni1F80\nENCODING 8064\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n70\n90\nB0\n50\n40\nENDCHAR\nSTARTCHAR uni1F81\nENCODING 8065\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n40\n70\n90\nB0\n50\n40\nENDCHAR\nSTARTCHAR uni1F82\nENCODING 8066\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n50\n70\n90\nB0\n50\n40\nENDCHAR\nSTARTCHAR uni1F83\nENCODING 8067\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\n70\n90\nB0\n50\n40\nENDCHAR\nSTARTCHAR uni1F84\nENCODING 8068\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\n60\n70\n90\nB0\n50\n40\nENDCHAR\nSTARTCHAR uni1F85\nENCODING 8069\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nA0\n70\n90\nB0\n50\n40\nENDCHAR\nSTARTCHAR uni1F86\nENCODING 8070\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n70\n90\nB0\n50\n40\nENDCHAR\nSTARTCHAR uni1F87\nENCODING 8071\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n70\n90\nB0\n50\n40\nENDCHAR\nSTARTCHAR uni1F88\nENCODING 8072\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n70\n50\n50\n20\nENDCHAR\nSTARTCHAR uni1F89\nENCODING 8073\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n70\n50\n50\n20\nENDCHAR\nSTARTCHAR uni1F8A\nENCODING 8074\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n70\n50\n50\n20\nENDCHAR\nSTARTCHAR uni1F8B\nENCODING 8075\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n70\n50\n50\n20\nENDCHAR\nSTARTCHAR uni1F8C\nENCODING 8076\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n70\n50\n50\n20\nENDCHAR\nSTARTCHAR uni1F8D\nENCODING 8077\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n70\n50\n50\n20\nENDCHAR\nSTARTCHAR uni1F8E\nENCODING 8078\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n70\n50\n50\n20\nENDCHAR\nSTARTCHAR uni1F8F\nENCODING 8079\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n70\n50\n50\n20\nENDCHAR\nSTARTCHAR uni1F90\nENCODING 8080\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\nE0\n90\n90\n10\n90\nENDCHAR\nSTARTCHAR uni1F91\nENCODING 8081\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n40\nE0\n90\n90\n10\n90\nENDCHAR\nSTARTCHAR uni1F92\nENCODING 8082\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n50\nE0\n90\n90\n10\n90\nENDCHAR\nSTARTCHAR uni1F93\nENCODING 8083\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\nE0\n90\n90\n10\n90\nENDCHAR\nSTARTCHAR uni1F94\nENCODING 8084\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\n60\nE0\n90\n90\n10\n90\nENDCHAR\nSTARTCHAR uni1F95\nENCODING 8085\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nA0\nE0\n90\n90\n10\n90\nENDCHAR\nSTARTCHAR uni1F96\nENCODING 8086\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\nE0\n90\n90\n10\n90\nENDCHAR\nSTARTCHAR uni1F97\nENCODING 8087\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\nE0\n90\n90\n10\n90\nENDCHAR\nSTARTCHAR uni1F98\nENCODING 8088\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n70\n50\n50\n50\n20\nENDCHAR\nSTARTCHAR uni1F99\nENCODING 8089\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n70\n50\n50\n50\n20\nENDCHAR\nSTARTCHAR uni1F9A\nENCODING 8090\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n70\n50\n50\n50\n20\nENDCHAR\nSTARTCHAR uni1F9B\nENCODING 8091\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n70\n50\n50\n50\n20\nENDCHAR\nSTARTCHAR uni1F9C\nENCODING 8092\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n70\n50\n50\n50\n20\nENDCHAR\nSTARTCHAR uni1F9D\nENCODING 8093\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n70\n50\n50\n50\n20\nENDCHAR\nSTARTCHAR uni1F9E\nENCODING 8094\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n70\n50\n50\n50\n20\nENDCHAR\nSTARTCHAR uni1F9F\nENCODING 8095\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n70\n50\n50\n50\n20\nENDCHAR\nSTARTCHAR uni1FA0\nENCODING 8096\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n90\n90\nF0\nF0\n40\nENDCHAR\nSTARTCHAR uni1FA1\nENCODING 8097\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n40\n90\n90\nF0\nF0\n40\nENDCHAR\nSTARTCHAR uni1FA2\nENCODING 8098\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n50\n90\n90\nF0\nF0\n40\nENDCHAR\nSTARTCHAR uni1FA3\nENCODING 8099\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\n90\n90\nF0\nF0\n40\nENDCHAR\nSTARTCHAR uni1FA4\nENCODING 8100\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\n60\n90\n90\nF0\nF0\n40\nENDCHAR\nSTARTCHAR uni1FA5\nENCODING 8101\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nA0\n90\n90\nF0\nF0\n40\nENDCHAR\nSTARTCHAR uni1FA6\nENCODING 8102\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n90\n90\nF0\nF0\n40\nENDCHAR\nSTARTCHAR uni1FA7\nENCODING 8103\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n90\n90\nF0\nF0\n40\nENDCHAR\nSTARTCHAR uni1FA8\nENCODING 8104\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n20\n50\n20\nENDCHAR\nSTARTCHAR uni1FA9\nENCODING 8105\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n20\n50\n20\nENDCHAR\nSTARTCHAR uni1FAA\nENCODING 8106\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n20\n50\n20\nENDCHAR\nSTARTCHAR uni1FAB\nENCODING 8107\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n20\n50\n20\nENDCHAR\nSTARTCHAR uni1FAC\nENCODING 8108\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n20\n50\n20\nENDCHAR\nSTARTCHAR uni1FAD\nENCODING 8109\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n20\n50\n20\nENDCHAR\nSTARTCHAR uni1FAE\nENCODING 8110\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n20\n50\n20\nENDCHAR\nSTARTCHAR uni1FAF\nENCODING 8111\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n20\n50\n20\nENDCHAR\nSTARTCHAR uni1FB0\nENCODING 8112\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n60\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR uni1FB1\nENCODING 8113\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n00\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR uni1FB2\nENCODING 8114\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n70\n90\nB0\n50\n40\nENDCHAR\nSTARTCHAR uni1FB3\nENCODING 8115\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\n90\nB0\n50\n40\nENDCHAR\nSTARTCHAR uni1FB4\nENCODING 8116\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n20\n70\n90\nB0\n50\n40\nENDCHAR\nSTARTCHAR uni1FB6\nENCODING 8118\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n00\n70\n90\nB0\n50\n00\nENDCHAR\nSTARTCHAR uni1FB7\nENCODING 8119\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n00\n70\n90\nB0\n50\n40\nENDCHAR\nSTARTCHAR uni1FB8\nENCODING 8120\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n60\n60\n90\nF0\n90\n00\nENDCHAR\nSTARTCHAR uni1FB9\nENCODING 8121\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n00\n60\n90\nF0\n90\n00\nENDCHAR\nSTARTCHAR uni1FBA\nENCODING 8122\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n70\n50\n50\n00\nENDCHAR\nSTARTCHAR uni1FBB\nENCODING 8123\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n70\n50\n50\n00\nENDCHAR\nSTARTCHAR uni1FBC\nENCODING 8124\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\nF0\n90\n90\n40\nENDCHAR\nSTARTCHAR uni1FBD\nENCODING 8125\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni1FBE\nENCODING 8126\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR uni1FBF\nENCODING 8127\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni1FC0\nENCODING 8128\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni1FC1\nENCODING 8129\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\nA0\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni1FC2\nENCODING 8130\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n40\nE0\n90\n90\n10\n90\nENDCHAR\nSTARTCHAR uni1FC3\nENCODING 8131\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\n90\n90\n10\n90\nENDCHAR\nSTARTCHAR uni1FC4\nENCODING 8132\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\nE0\n90\n90\n10\n90\nENDCHAR\nSTARTCHAR uni1FC6\nENCODING 8134\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n00\nE0\n90\n90\n90\n10\nENDCHAR\nSTARTCHAR uni1FC7\nENCODING 8135\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n00\nE0\n90\n90\n10\n90\nENDCHAR\nSTARTCHAR uni1FC8\nENCODING 8136\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nC0\n60\n40\n40\n70\n00\nENDCHAR\nSTARTCHAR uni1FC9\nENCODING 8137\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nC0\n60\n40\n40\n70\n00\nENDCHAR\nSTARTCHAR uni1FCA\nENCODING 8138\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n70\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR uni1FCB\nENCODING 8139\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n70\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR uni1FCC\nENCODING 8140\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\nF0\n90\n90\n90\n40\nENDCHAR\nSTARTCHAR uni1FCD\nENCODING 8141\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n50\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni1FCE\nENCODING 8142\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\n60\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni1FCF\nENCODING 8143\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n40\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni1FD0\nENCODING 8144\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n60\n40\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR uni1FD1\nENCODING 8145\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n00\n40\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR uni1FD2\nENCODING 8146\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\n20\n00\n20\n20\n10\n00\nENDCHAR\nSTARTCHAR uni1FD3\nENCODING 8147\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nB0\n40\n00\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR uni1FD6\nENCODING 8150\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n00\n40\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR uni1FD7\nENCODING 8151\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\nA0\n00\n40\n40\n20\n00\nENDCHAR\nSTARTCHAR uni1FD8\nENCODING 8152\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n60\n70\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni1FD9\nENCODING 8153\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n00\n70\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni1FDA\nENCODING 8154\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nA0\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni1FDB\nENCODING 8155\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nA0\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni1FDD\nENCODING 8157\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n90\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni1FDE\nENCODING 8158\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nA0\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni1FDF\nENCODING 8159\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n40\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni1FE0\nENCODING 8160\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n60\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1FE1\nENCODING 8161\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n00\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1FE2\nENCODING 8162\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\n20\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1FE3\nENCODING 8163\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nB0\n40\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1FE4\nENCODING 8164\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n60\n90\n90\nE0\n80\nENDCHAR\nSTARTCHAR uni1FE5\nENCODING 8165\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n40\n60\n90\n90\nE0\n80\nENDCHAR\nSTARTCHAR uni1FE6\nENCODING 8166\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n00\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1FE7\nENCODING 8167\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n90\n00\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni1FE8\nENCODING 8168\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n60\nA0\nA0\n40\n40\n00\nENDCHAR\nSTARTCHAR uni1FE9\nENCODING 8169\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n00\nA0\nA0\n40\n40\n00\nENDCHAR\nSTARTCHAR uni1FEA\nENCODING 8170\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n50\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR uni1FEB\nENCODING 8171\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\nD0\n50\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR uni1FEC\nENCODING 8172\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\nD0\n50\n60\n40\n40\n00\nENDCHAR\nSTARTCHAR uni1FED\nENCODING 8173\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD0\n20\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni1FEE\nENCODING 8174\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nB0\n40\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni1FEF\nENCODING 8175\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni1FF2\nENCODING 8178\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n90\n90\nF0\nF0\n40\nENDCHAR\nSTARTCHAR uni1FF3\nENCODING 8179\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n90\nF0\nF0\n40\nENDCHAR\nSTARTCHAR uni1FF4\nENCODING 8180\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n90\n90\nF0\nF0\n40\nENDCHAR\nSTARTCHAR uni1FF6\nENCODING 8182\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n00\n90\n90\nF0\nF0\n00\nENDCHAR\nSTARTCHAR uni1FF7\nENCODING 8183\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n00\n90\n90\nF0\nF0\n40\nENDCHAR\nSTARTCHAR uni1FF8\nENCODING 8184\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n50\n20\n00\nENDCHAR\nSTARTCHAR uni1FF9\nENCODING 8185\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n50\n20\n00\nENDCHAR\nSTARTCHAR uni1FFA\nENCODING 8186\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n20\n50\n00\nENDCHAR\nSTARTCHAR uni1FFB\nENCODING 8187\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\n50\n50\n20\n50\n00\nENDCHAR\nSTARTCHAR uni1FFC\nENCODING 8188\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n50\n50\n20\n50\n20\nENDCHAR\nSTARTCHAR uni1FFD\nENCODING 8189\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni1FFE\nENCODING 8190\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n40\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2010\nENCODING 8208\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n70\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2011\nENCODING 8209\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n70\n00\n00\n00\nENDCHAR\nSTARTCHAR figuredash\nENCODING 8210\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nF0\n00\n00\n00\nENDCHAR\nSTARTCHAR endash\nENCODING 8211\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nF0\n00\n00\n00\nENDCHAR\nSTARTCHAR emdash\nENCODING 8212\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR afii00208\nENCODING 8213\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2016\nENCODING 8214\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n50\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR underscoredbl\nENCODING 8215\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\nF0\n00\nF0\nENDCHAR\nSTARTCHAR quoteleft\nENCODING 8216\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n60\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR quoteright\nENCODING 8217\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n40\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR quotesinglbase\nENCODING 8218\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n60\n20\n40\nENDCHAR\nSTARTCHAR quotereversed\nENCODING 8219\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n40\n20\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR quotedblleft\nENCODING 8220\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\nA0\nA0\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR quotedblright\nENCODING 8221\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\nA0\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR quotedblbase\nENCODING 8222\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n50\n50\nA0\nENDCHAR\nSTARTCHAR uni201F\nENCODING 8223\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nA0\n50\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR dagger\nENCODING 8224\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n70\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR daggerdbl\nENCODING 8225\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n70\n20\n70\n20\n00\nENDCHAR\nSTARTCHAR bullet\nENCODING 8226\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\nF0\nF0\n60\n00\nENDCHAR\nSTARTCHAR uni2023\nENCODING 8227\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n40\n60\n70\n60\n40\n00\nENDCHAR\nSTARTCHAR onedotenleader\nENCODING 8228\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\n20\n00\nENDCHAR\nSTARTCHAR twodotenleader\nENCODING 8229\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\n50\n00\nENDCHAR\nSTARTCHAR ellipsis\nENCODING 8230\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\nA8\n00\nENDCHAR\nSTARTCHAR uni2027\nENCODING 8231\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n60\n00\n00\n00\nENDCHAR\nSTARTCHAR perthousand\nENCODING 8240\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n90\n20\n40\nA8\n28\n00\nENDCHAR\nSTARTCHAR minute\nENCODING 8242\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n40\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR second\nENCODING 8243\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\nA0\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2034\nENCODING 8244\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n70\nE0\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2035\nENCODING 8245\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n40\n20\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2036\nENCODING 8246\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nA0\n50\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2037\nENCODING 8247\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\nE0\n70\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR guilsinglleft\nENCODING 8249\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n20\n40\n20\n00\n00\nENDCHAR\nSTARTCHAR guilsinglright\nENCODING 8250\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\n20\n40\n00\n00\nENDCHAR\nSTARTCHAR exclamdbl\nENCODING 8252\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n50\n50\n00\n50\n00\nENDCHAR\nSTARTCHAR uni203E\nENCODING 8254\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF8\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR fraction\nENCODING 8260\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n10\n20\n40\n80\n00\n00\nENDCHAR\nSTARTCHAR zerosuperior\nENCODING 8304\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n50\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2071\nENCODING 8305\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n00\n20\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR foursuperior\nENCODING 8308\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n60\n70\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR fivesuperior\nENCODING 8309\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n60\n10\n60\n00\n00\n00\nENDCHAR\nSTARTCHAR sixsuperior\nENCODING 8310\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n60\n50\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR sevensuperior\nENCODING 8311\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n10\n20\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR eightsuperior\nENCODING 8312\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n20\n50\n20\n00\n00\nENDCHAR\nSTARTCHAR ninesuperior\nENCODING 8313\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n30\n60\n00\n00\n00\nENDCHAR\nSTARTCHAR uni207A\nENCODING 8314\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n70\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR uni207B\nENCODING 8315\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni207C\nENCODING 8316\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n70\n00\n70\n00\n00\n00\nENDCHAR\nSTARTCHAR parenleftsuperior\nENCODING 8317\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n40\n40\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR parenrightsuperior\nENCODING 8318\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n10\n10\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR nsuperior\nENCODING 8319\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n60\n50\n50\n00\n00\n00\nENDCHAR\nSTARTCHAR zeroinferior\nENCODING 8320\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n20\n50\n50\n20\nENDCHAR\nSTARTCHAR oneinferior\nENCODING 8321\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n20\n60\n20\n70\nENDCHAR\nSTARTCHAR twoinferior\nENCODING 8322\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n60\n20\n40\n60\nENDCHAR\nSTARTCHAR threeinferior\nENCODING 8323\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n60\n60\n20\n60\nENDCHAR\nSTARTCHAR fourinferior\nENCODING 8324\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n20\n60\n70\n20\nENDCHAR\nSTARTCHAR fiveinferior\nENCODING 8325\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n70\n60\n10\n60\nENDCHAR\nSTARTCHAR sixinferior\nENCODING 8326\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n30\n60\n50\n20\nENDCHAR\nSTARTCHAR seveninferior\nENCODING 8327\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n70\n10\n20\n20\nENDCHAR\nSTARTCHAR eightinferior\nENCODING 8328\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n20\n50\n20\n50\n20\nENDCHAR\nSTARTCHAR nineinferior\nENCODING 8329\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n20\n50\n30\n60\nENDCHAR\nSTARTCHAR uni208A\nENCODING 8330\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n20\n70\n20\nENDCHAR\nSTARTCHAR uni208B\nENCODING 8331\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\n70\n00\nENDCHAR\nSTARTCHAR uni208C\nENCODING 8332\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n70\n00\n70\nENDCHAR\nSTARTCHAR parenleftinferior\nENCODING 8333\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n20\n40\n40\n20\nENDCHAR\nSTARTCHAR parenrightinferior\nENCODING 8334\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n20\n10\n10\n20\nENDCHAR\nSTARTCHAR franc\nENCODING 8355\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n80\nD8\nA0\nA0\nA0\n00\nENDCHAR\nSTARTCHAR lira\nENCODING 8356\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n40\nE0\nE0\n40\nB0\n00\nENDCHAR\nSTARTCHAR peseta\nENCODING 8359\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n50\nF8\n70\n40\n40\n00\nENDCHAR\nSTARTCHAR dong\nENCODING 8363\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n38\n70\n90\n90\n70\nF0\nENDCHAR\nSTARTCHAR Euro\nENCODING 8364\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n40\nE0\nE0\n40\n30\n00\nENDCHAR\nSTARTCHAR uni20AF\nENCODING 8367\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n60\nD0\n50\nD0\nE0\n00\nENDCHAR\nSTARTCHAR uni20D0\nENCODING 8400\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\nF8\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni20D1\nENCODING 8401\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\nF8\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni20D2\nENCODING 8402\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\n20\n20\n20\n20\nENDCHAR\nSTARTCHAR uni20D3\nENCODING 8403\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n20\n20\n20\n20\n20\nENDCHAR\nSTARTCHAR uni20D4\nENCODING 8404\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nD0\nD0\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni20D5\nENCODING 8405\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\nB0\nB0\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni20D6\nENCODING 8406\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\nF8\n40\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni20D7\nENCODING 8407\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\nF8\n10\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2102\nENCODING 8450\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\nD0\nC0\nC0\nD0\n60\n00\nENDCHAR\nSTARTCHAR afii61248\nENCODING 8453\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n80\n70\n60\nA0\n50\n20\nENDCHAR\nSTARTCHAR afii61289\nENCODING 8467\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\n30\n20\n20\n50\n00\nENDCHAR\nSTARTCHAR uni2115\nENCODING 8469\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nC8\nC8\nE8\nD8\nC8\nC8\n00\nENDCHAR\nSTARTCHAR afii61352\nENCODING 8470\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nC0\nA0\nA0\nB0\nA8\nB0\n00\nENDCHAR\nSTARTCHAR uni211A\nENCODING 8474\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\nD0\nD0\nD0\nF0\n70\n10\nENDCHAR\nSTARTCHAR uni211D\nENCODING 8477\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\nD0\nD0\nF0\nE0\nD0\n00\nENDCHAR\nSTARTCHAR trademark\nENCODING 8482\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n00\nF8\nA8\nA8\nENDCHAR\nSTARTCHAR uni2124\nENCODING 8484\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n30\n60\n60\nC0\nF0\n00\nENDCHAR\nSTARTCHAR Omega\nENCODING 8486\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n50\n50\n20\n70\n00\nENDCHAR\nSTARTCHAR uni2127\nENCODING 8487\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n50\n50\n50\n20\n00\nENDCHAR\nSTARTCHAR estimated\nENCODING 8494\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\nD8\nE0\n70\n00\nENDCHAR\nSTARTCHAR oneeighth\nENCODING 8539\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n80\n80\nB0\n30\n30\n30\nENDCHAR\nSTARTCHAR threeeighths\nENCODING 8540\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nC0\nC0\n40\nF0\n30\n30\n30\nENDCHAR\nSTARTCHAR fiveeighths\nENCODING 8541\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nC0\n80\n40\nB0\n30\n30\n30\nENDCHAR\nSTARTCHAR seveneighths\nENCODING 8542\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nC0\n40\n80\nB0\n30\n30\n30\nENDCHAR\nSTARTCHAR arrowleft\nENCODING 8592\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\nF0\n40\n00\n00\nENDCHAR\nSTARTCHAR arrowup\nENCODING 8593\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n70\n20\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR arrowright\nENCODING 8594\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n20\nF0\n20\n00\n00\nENDCHAR\nSTARTCHAR arrowdown\nENCODING 8595\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\n20\n70\n20\n00\nENDCHAR\nSTARTCHAR arrowboth\nENCODING 8596\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\nF8\n50\n00\n00\nENDCHAR\nSTARTCHAR arrowupdn\nENCODING 8597\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n70\n20\n20\n70\n20\n00\nENDCHAR\nSTARTCHAR uni21A4\nENCODING 8612\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\nF0\n50\n00\n00\nENDCHAR\nSTARTCHAR uni21A5\nENCODING 8613\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n70\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni21A6\nENCODING 8614\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nA0\nF0\nA0\n00\n00\nENDCHAR\nSTARTCHAR uni21A7\nENCODING 8615\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n70\n20\n00\nENDCHAR\nSTARTCHAR arrowupdnbse\nENCODING 8616\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n70\n20\n20\n70\n20\n70\nENDCHAR\nSTARTCHAR uni21C4\nENCODING 8644\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\nF8\n10\n40\nF8\n40\n00\nENDCHAR\nSTARTCHAR uni21C6\nENCODING 8646\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\nF8\n40\n10\nF8\n10\n00\nENDCHAR\nSTARTCHAR uni21CB\nENCODING 8651\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n40\nF0\n00\nF0\n20\n00\nENDCHAR\nSTARTCHAR uni21CC\nENCODING 8652\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\nF0\n00\nF0\n40\n00\nENDCHAR\nSTARTCHAR arrowdblleft\nENCODING 8656\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n20\n78\n80\n78\n20\n10\nENDCHAR\nSTARTCHAR arrowdblup\nENCODING 8657\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\nD8\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR arrowdblright\nENCODING 8658\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\nF0\n08\nF0\n20\n40\nENDCHAR\nSTARTCHAR arrowdbldown\nENCODING 8659\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n50\nD8\n50\n20\n00\nENDCHAR\nSTARTCHAR arrowdblboth\nENCODING 8660\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n70\n88\n70\n20\n00\nENDCHAR\nSTARTCHAR uni21D5\nENCODING 8661\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\nD8\n50\nD8\n50\n20\nENDCHAR\nSTARTCHAR universal\nENCODING 8704\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\nF0\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni2201\nENCODING 8705\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n40\n40\n50\n20\n00\nENDCHAR\nSTARTCHAR partialdiff\nENCODING 8706\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n10\n30\n50\n50\n20\n00\nENDCHAR\nSTARTCHAR existential\nENCODING 8707\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n10\n70\n10\n10\nF0\n00\nENDCHAR\nSTARTCHAR uni2204\nENCODING 8708\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\nF0\n50\n70\n50\nF0\n40\nENDCHAR\nSTARTCHAR emptyset\nENCODING 8709\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n70\nB0\nD0\nD0\nE0\n80\nENDCHAR\nSTARTCHAR Delta\nENCODING 8710\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n50\n50\n88\nF8\n00\nENDCHAR\nSTARTCHAR gradient\nENCODING 8711\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF8\n88\n50\n50\n20\n20\n00\nENDCHAR\nSTARTCHAR element\nENCODING 8712\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n70\n80\nF0\n80\n70\n00\nENDCHAR\nSTARTCHAR notelement\nENCODING 8713\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n70\nA0\nF0\nA0\n70\n40\nENDCHAR\nSTARTCHAR uni220A\nENCODING 8714\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n30\n40\n70\n40\n30\n00\nENDCHAR\nSTARTCHAR suchthat\nENCODING 8715\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\nE0\n10\nF0\n10\nE0\n00\nENDCHAR\nSTARTCHAR uni220C\nENCODING 8716\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\nE0\n50\nF0\n50\nE0\n80\nENDCHAR\nSTARTCHAR uni220D\nENCODING 8717\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n60\n10\n70\n10\n60\n00\nENDCHAR\nSTARTCHAR uni220E\nENCODING 8718\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\nF0\nF0\nF0\nF0\nF0\n00\nENDCHAR\nSTARTCHAR product\nENCODING 8719\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF8\n50\n50\n50\n50\nD8\n00\nENDCHAR\nSTARTCHAR uni2210\nENCODING 8720\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nD8\n50\n50\n50\n50\nF8\n00\nENDCHAR\nSTARTCHAR summation\nENCODING 8721\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n40\n20\n40\n80\nF0\n00\nENDCHAR\nSTARTCHAR minus\nENCODING 8722\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2213\nENCODING 8723\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF8\n20\n20\nF8\n20\n20\n00\nENDCHAR\nSTARTCHAR uni2214\nENCODING 8724\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n00\n20\n20\nF8\n20\n20\nENDCHAR\nSTARTCHAR fraction\nENCODING 8725\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n10\n20\n40\n80\n80\n00\nENDCHAR\nSTARTCHAR uni2216\nENCODING 8726\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n80\n40\n20\n10\n00\nENDCHAR\nSTARTCHAR asteriskmath\nENCODING 8727\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\nA8\n70\nA8\n20\n00\nENDCHAR\nSTARTCHAR uni2218\nENCODING 8728\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n20\n50\n20\n00\n00\nENDCHAR\nSTARTCHAR periodcentered\nENCODING 8729\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n20\n70\n20\n00\n00\nENDCHAR\nSTARTCHAR radical\nENCODING 8730\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n08\n10\n10\n20\nA0\n40\n00\nENDCHAR\nSTARTCHAR uni221B\nENCODING 8731\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n88\nD0\n90\n20\nA0\n40\n00\nENDCHAR\nSTARTCHAR uni221C\nENCODING 8732\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n88\nD0\n50\n20\nA0\n40\n00\nENDCHAR\nSTARTCHAR proportional\nENCODING 8733\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\nA0\nA0\n50\n00\nENDCHAR\nSTARTCHAR infinity\nENCODING 8734\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\nA8\nA8\n50\n00\nENDCHAR\nSTARTCHAR orthogonal\nENCODING 8735\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n80\n80\n80\nF0\n00\nENDCHAR\nSTARTCHAR angle\nENCODING 8736\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n10\n20\n40\nF0\n00\nENDCHAR\nSTARTCHAR uni2221\nENCODING 8737\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n10\nA0\n40\nF0\n20\nENDCHAR\nSTARTCHAR uni2222\nENCODING 8738\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n50\n60\nA0\n60\n50\n00\nENDCHAR\nSTARTCHAR uni2223\nENCODING 8739\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR uni2224\nENCODING 8740\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n30\n60\n20\n20\n00\nENDCHAR\nSTARTCHAR uni2225\nENCODING 8741\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n50\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR uni2226\nENCODING 8742\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n58\n70\n70\nD0\n50\n00\nENDCHAR\nSTARTCHAR logicaland\nENCODING 8743\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n20\n20\n50\n50\n00\nENDCHAR\nSTARTCHAR logicalor\nENCODING 8744\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n50\n20\n20\n00\nENDCHAR\nSTARTCHAR intersection\nENCODING 8745\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR union\nENCODING 8746\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR integral\nENCODING 8747\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n28\n20\n20\n20\nA0\n40\nENDCHAR\nSTARTCHAR uni222C\nENCODING 8748\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n28\n50\n50\n50\n50\n50\nA0\nENDCHAR\nSTARTCHAR uni222D\nENCODING 8749\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n38\n70\n70\n70\n70\n70\nE0\nENDCHAR\nSTARTCHAR uni222E\nENCODING 8750\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n28\n70\nA8\n70\nA0\n40\nENDCHAR\nSTARTCHAR uni222F\nENCODING 8751\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n28\n50\n70\nD8\n70\n50\nA0\nENDCHAR\nSTARTCHAR uni2230\nENCODING 8752\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n38\n70\n70\nF8\n70\n70\nE0\nENDCHAR\nSTARTCHAR therefore\nENCODING 8756\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n20\n00\n50\n00\n00\nENDCHAR\nSTARTCHAR uni2235\nENCODING 8757\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n00\n20\n00\n00\nENDCHAR\nSTARTCHAR uni2236\nENCODING 8758\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n20\n00\n00\n20\n00\nENDCHAR\nSTARTCHAR uni2237\nENCODING 8759\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n90\n00\n00\n90\n00\nENDCHAR\nSTARTCHAR uni2238\nENCODING 8760\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n20\n00\nF8\n00\n00\nENDCHAR\nSTARTCHAR uni2239\nENCODING 8761\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n10\nC0\n10\n00\n00\nENDCHAR\nSTARTCHAR uni223A\nENCODING 8762\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n90\n00\nF0\n00\n90\n00\nENDCHAR\nSTARTCHAR similar\nENCODING 8764\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n50\nA0\n00\n00\nENDCHAR\nSTARTCHAR uni2243\nENCODING 8771\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n50\nA0\n00\nF0\n00\n00\nENDCHAR\nSTARTCHAR congruent\nENCODING 8773\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\nA0\n00\nF0\n00\nF0\n00\nENDCHAR\nSTARTCHAR approxequal\nENCODING 8776\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n50\nA0\n00\n50\nA0\n00\nENDCHAR\nSTARTCHAR uni2249\nENCODING 8777\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n50\nA0\n20\n50\nA0\n80\nENDCHAR\nSTARTCHAR uni2259\nENCODING 8793\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n00\nF0\n00\nF0\n00\nENDCHAR\nSTARTCHAR uni225A\nENCODING 8794\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n20\n00\nF0\n00\nF0\n00\nENDCHAR\nSTARTCHAR uni225F\nENCODING 8799\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n20\n00\n20\nF0\n00\nF0\nENDCHAR\nSTARTCHAR notequal\nENCODING 8800\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n10\nF0\n20\nF0\n40\n00\nENDCHAR\nSTARTCHAR equivalence\nENCODING 8801\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\nF0\n00\nF0\n00\nF0\n00\nENDCHAR\nSTARTCHAR uni2262\nENCODING 8802\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\nF0\n20\nF0\n20\nF0\n40\nENDCHAR\nSTARTCHAR uni2263\nENCODING 8803\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\n00\nF0\n00\nF0\n00\nF0\nENDCHAR\nSTARTCHAR lessequal\nENCODING 8804\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n20\n40\n20\n10\n70\n00\nENDCHAR\nSTARTCHAR greaterequal\nENCODING 8805\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n20\n10\n20\n40\n70\n00\nENDCHAR\nSTARTCHAR uni226A\nENCODING 8810\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n28\n50\nA0\n50\n28\n00\nENDCHAR\nSTARTCHAR uni226B\nENCODING 8811\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\nA0\n50\n28\n50\nA0\n00\nENDCHAR\nSTARTCHAR propersubset\nENCODING 8834\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\n80\n80\n70\n00\nENDCHAR\nSTARTCHAR propersuperset\nENCODING 8835\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\n10\n10\nE0\n00\nENDCHAR\nSTARTCHAR notsubset\nENCODING 8836\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n70\nA0\nA0\n70\n20\nENDCHAR\nSTARTCHAR uni2285\nENCODING 8837\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n40\nE0\n50\n50\nE0\n40\nENDCHAR\nSTARTCHAR reflexsubset\nENCODING 8838\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n70\n80\n70\n00\nF0\n00\nENDCHAR\nSTARTCHAR reflexsuperset\nENCODING 8839\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\nE0\n10\nE0\n00\nF0\n00\nENDCHAR\nSTARTCHAR uni2288\nENCODING 8840\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n70\nA0\n70\n20\nF0\n20\nENDCHAR\nSTARTCHAR uni2289\nENCODING 8841\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\nE0\n50\nE0\n40\nF0\n40\nENDCHAR\nSTARTCHAR uni228A\nENCODING 8842\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n70\n80\n70\n20\nF0\n20\nENDCHAR\nSTARTCHAR uni228B\nENCODING 8843\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\nE0\n10\nE0\n40\nF0\n40\nENDCHAR\nSTARTCHAR circleplus\nENCODING 8853\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n70\nA8\nF8\nA8\n70\n00\nENDCHAR\nSTARTCHAR uni2296\nENCODING 8854\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n70\n88\nF8\n88\n70\n00\nENDCHAR\nSTARTCHAR circlemultiply\nENCODING 8855\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n70\nD8\nA8\nD8\n70\n00\nENDCHAR\nSTARTCHAR uni2298\nENCODING 8856\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n70\n98\nA8\nC8\n70\n00\nENDCHAR\nSTARTCHAR uni2299\nENCODING 8857\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n70\n88\nA8\n88\n70\n00\nENDCHAR\nSTARTCHAR uni22A2\nENCODING 8866\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n80\n80\nF0\n80\n80\n00\nENDCHAR\nSTARTCHAR uni22A3\nENCODING 8867\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n10\n10\nF0\n10\n10\n00\nENDCHAR\nSTARTCHAR uni22A4\nENCODING 8868\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n20\n20\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR perpendicular\nENCODING 8869\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\n20\n20\n70\n00\nENDCHAR\nSTARTCHAR uni22A6\nENCODING 8870\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n40\n40\n70\n40\n40\n00\nENDCHAR\nSTARTCHAR uni22A7\nENCODING 8871\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n40\n70\n40\n70\n40\n00\nENDCHAR\nSTARTCHAR uni22A8\nENCODING 8872\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n80\nF0\n80\nF0\n80\n00\nENDCHAR\nSTARTCHAR uni22C2\nENCODING 8898\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n90\n90\n90\n90\n90\n00\nENDCHAR\nSTARTCHAR uni22C3\nENCODING 8899\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n90\n90\n90\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR dotmath\nENCODING 8901\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR uni22EE\nENCODING 8942\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n00\n20\n00\n20\n00\nENDCHAR\nSTARTCHAR uni22EF\nENCODING 8943\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nA8\n00\n00\n00\nENDCHAR\nSTARTCHAR uni22F0\nENCODING 8944\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n08\n00\n20\n00\n80\n00\nENDCHAR\nSTARTCHAR uni22F1\nENCODING 8945\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n80\n00\n20\n00\n08\n00\nENDCHAR\nSTARTCHAR uni2300\nENCODING 8960\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n78\n98\nA8\nC8\nF0\n00\nENDCHAR\nSTARTCHAR house\nENCODING 8962\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n50\n88\n88\nF8\n00\nENDCHAR\nSTARTCHAR uni2308\nENCODING 8968\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n40\n40\n40\n40\n40\n00\nENDCHAR\nSTARTCHAR uni2309\nENCODING 8969\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n10\n10\n10\n10\n10\n00\nENDCHAR\nSTARTCHAR uni230A\nENCODING 8970\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n40\n40\n40\n40\n70\n00\nENDCHAR\nSTARTCHAR uni230B\nENCODING 8971\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n10\n10\n10\n10\n70\n00\nENDCHAR\nSTARTCHAR revlogicalnot\nENCODING 8976\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nF0\n80\n00\n00\nENDCHAR\nSTARTCHAR integraltp\nENCODING 8992\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n28\n20\n20\n20\n20\n20\nENDCHAR\nSTARTCHAR integralbt\nENCODING 8993\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\n20\n20\nA0\n40\nENDCHAR\nSTARTCHAR uni23BA\nENCODING 9146\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF8\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni23BB\nENCODING 9147\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\nF8\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni23BC\nENCODING 9148\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\nF8\n00\nENDCHAR\nSTARTCHAR uni23BD\nENCODING 9149\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\n00\nF8\nENDCHAR\nSTARTCHAR uni2409\nENCODING 9225\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nE0\nA0\n70\n20\n20\n00\nENDCHAR\nSTARTCHAR uni240A\nENCODING 9226\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n80\nF0\n20\n30\n20\n00\nENDCHAR\nSTARTCHAR uni240B\nENCODING 9227\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA0\nA0\n78\n50\n10\n10\n00\nENDCHAR\nSTARTCHAR uni240C\nENCODING 9228\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\n80\nF8\nA0\n30\n20\n00\nENDCHAR\nSTARTCHAR uni240D\nENCODING 9229\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n80\nE0\n50\n60\n50\n00\nENDCHAR\nSTARTCHAR uni2423\nENCODING 9251\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n90\nF0\n00\nENDCHAR\nSTARTCHAR uni2424\nENCODING 9252\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nC0\nA0\nA0\nA0\n20\n38\n00\nENDCHAR\nSTARTCHAR SF100000\nENCODING 9472\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2501\nENCODING 9473\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF8\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR SF110000\nENCODING 9474\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\n20\n20\n20\n20\nENDCHAR\nSTARTCHAR uni2503\nENCODING 9475\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\n30\n30\n30\n30\n30\nENDCHAR\nSTARTCHAR uni2504\nENCODING 9476\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nA8\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2505\nENCODING 9477\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nA8\nA8\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2506\nENCODING 9478\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n00\n20\n20\n00\n20\n00\nENDCHAR\nSTARTCHAR uni2507\nENCODING 9479\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n00\n30\n30\n00\n30\n00\nENDCHAR\nSTARTCHAR uni2508\nENCODING 9480\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nA8\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2509\nENCODING 9481\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nA8\nA8\n00\n00\n00\nENDCHAR\nSTARTCHAR uni250A\nENCODING 9482\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n00\n20\n00\n20\n00\n20\nENDCHAR\nSTARTCHAR uni250B\nENCODING 9483\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n00\n30\n00\n30\n00\n30\nENDCHAR\nSTARTCHAR SF010000\nENCODING 9484\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n38\n20\n20\n20\nENDCHAR\nSTARTCHAR uni250D\nENCODING 9485\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n38\n38\n20\n20\n20\nENDCHAR\nSTARTCHAR uni250E\nENCODING 9486\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n38\n30\n30\n30\nENDCHAR\nSTARTCHAR uni250F\nENCODING 9487\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n38\n38\n30\n30\n30\nENDCHAR\nSTARTCHAR SF030000\nENCODING 9488\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nE0\n20\n20\n20\nENDCHAR\nSTARTCHAR uni2511\nENCODING 9489\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\nE0\n20\n20\n20\nENDCHAR\nSTARTCHAR uni2512\nENCODING 9490\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nF0\n30\n30\n30\nENDCHAR\nSTARTCHAR uni2513\nENCODING 9491\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF0\nF0\n30\n30\n30\nENDCHAR\nSTARTCHAR SF020000\nENCODING 9492\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\n38\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2515\nENCODING 9493\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n38\n38\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2516\nENCODING 9494\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\n30\n38\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2517\nENCODING 9495\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\n38\n38\n00\n00\n00\nENDCHAR\nSTARTCHAR SF040000\nENCODING 9496\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\nE0\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2519\nENCODING 9497\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\nE0\nE0\n00\n00\n00\nENDCHAR\nSTARTCHAR uni251A\nENCODING 9498\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\n30\nF0\n00\n00\n00\nENDCHAR\nSTARTCHAR uni251B\nENCODING 9499\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\nF0\nF0\n00\n00\n00\nENDCHAR\nSTARTCHAR SF080000\nENCODING 9500\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\n38\n20\n20\n20\nENDCHAR\nSTARTCHAR uni251D\nENCODING 9501\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n38\n38\n20\n20\n20\nENDCHAR\nSTARTCHAR uni251E\nENCODING 9502\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\n30\n38\n20\n20\n20\nENDCHAR\nSTARTCHAR uni251F\nENCODING 9503\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\n38\n30\n30\n30\nENDCHAR\nSTARTCHAR uni2520\nENCODING 9504\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\n30\n38\n30\n30\n30\nENDCHAR\nSTARTCHAR uni2521\nENCODING 9505\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\n38\n38\n20\n20\n20\nENDCHAR\nSTARTCHAR uni2522\nENCODING 9506\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n38\n38\n30\n30\n30\nENDCHAR\nSTARTCHAR uni2523\nENCODING 9507\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\n38\n38\n30\n30\n30\nENDCHAR\nSTARTCHAR SF090000\nENCODING 9508\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\nE0\n20\n20\n20\nENDCHAR\nSTARTCHAR uni2525\nENCODING 9509\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\nE0\nE0\n20\n20\n20\nENDCHAR\nSTARTCHAR uni2526\nENCODING 9510\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\n30\nF0\n20\n20\n20\nENDCHAR\nSTARTCHAR uni2527\nENCODING 9511\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\nF0\n30\n30\n30\nENDCHAR\nSTARTCHAR uni2528\nENCODING 9512\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\n30\nF0\n30\n30\n30\nENDCHAR\nSTARTCHAR uni2529\nENCODING 9513\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\nF0\nF0\n20\n20\n20\nENDCHAR\nSTARTCHAR uni252A\nENCODING 9514\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\nF0\nF0\n30\n30\n30\nENDCHAR\nSTARTCHAR uni252B\nENCODING 9515\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\nF0\nF0\n30\n30\n30\nENDCHAR\nSTARTCHAR SF060000\nENCODING 9516\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nF8\n20\n20\n20\nENDCHAR\nSTARTCHAR uni252D\nENCODING 9517\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\nF8\n20\n20\n20\nENDCHAR\nSTARTCHAR uni252E\nENCODING 9518\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n38\nF8\n20\n20\n20\nENDCHAR\nSTARTCHAR uni252F\nENCODING 9519\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF8\nF8\n20\n20\n20\nENDCHAR\nSTARTCHAR uni2530\nENCODING 9520\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nF8\n30\n30\n30\nENDCHAR\nSTARTCHAR uni2531\nENCODING 9521\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\nF8\n30\n30\n30\nENDCHAR\nSTARTCHAR uni2532\nENCODING 9522\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n18\nF8\n30\n30\n30\nENDCHAR\nSTARTCHAR uni2533\nENCODING 9523\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF8\nF8\n30\n30\n30\nENDCHAR\nSTARTCHAR SF070000\nENCODING 9524\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2535\nENCODING 9525\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\nE0\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2536\nENCODING 9526\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n38\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2537\nENCODING 9527\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\nF8\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2538\nENCODING 9528\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\n30\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2539\nENCODING 9529\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\nF0\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR uni253A\nENCODING 9530\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\n38\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR uni253B\nENCODING 9531\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\nF8\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR SF050000\nENCODING 9532\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\nF8\n20\n20\n20\nENDCHAR\nSTARTCHAR uni253D\nENCODING 9533\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\nE0\nF8\n20\n20\n20\nENDCHAR\nSTARTCHAR uni253E\nENCODING 9534\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n38\nF8\n20\n20\n20\nENDCHAR\nSTARTCHAR uni253F\nENCODING 9535\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\nF8\nF8\n20\n20\n20\nENDCHAR\nSTARTCHAR uni2540\nENCODING 9536\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\n30\nF8\n20\n20\n20\nENDCHAR\nSTARTCHAR uni2541\nENCODING 9537\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\nF8\n30\n30\n30\nENDCHAR\nSTARTCHAR uni2542\nENCODING 9538\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\n30\nF8\n30\n30\n30\nENDCHAR\nSTARTCHAR uni2543\nENCODING 9539\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\nF0\nF8\n20\n20\n20\nENDCHAR\nSTARTCHAR uni2544\nENCODING 9540\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\n38\nF8\n20\n20\n20\nENDCHAR\nSTARTCHAR uni2545\nENCODING 9541\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\nE0\nF8\n30\n30\n30\nENDCHAR\nSTARTCHAR uni2546\nENCODING 9542\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n38\nF8\n30\n30\n30\nENDCHAR\nSTARTCHAR uni2547\nENCODING 9543\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\nF8\nF8\n20\n20\n20\nENDCHAR\nSTARTCHAR uni2548\nENCODING 9544\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\nF8\nF8\n30\n30\n30\nENDCHAR\nSTARTCHAR uni2549\nENCODING 9545\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\nF0\nF8\n30\n30\n30\nENDCHAR\nSTARTCHAR uni254A\nENCODING 9546\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\n38\nF8\n30\n30\n30\nENDCHAR\nSTARTCHAR uni254B\nENCODING 9547\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\nF8\nF8\n30\n30\n30\nENDCHAR\nSTARTCHAR uni254C\nENCODING 9548\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nD0\n00\n00\n00\nENDCHAR\nSTARTCHAR uni254D\nENCODING 9549\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nD0\nD0\n00\n00\n00\nENDCHAR\nSTARTCHAR uni254E\nENCODING 9550\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\n00\n20\n20\n00\nENDCHAR\nSTARTCHAR uni254F\nENCODING 9551\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\n30\n00\n30\n30\n00\nENDCHAR\nSTARTCHAR SF430000\nENCODING 9552\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF8\n00\nF8\n00\n00\nENDCHAR\nSTARTCHAR SF240000\nENCODING 9553\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n50\n50\n50\n50\n50\nENDCHAR\nSTARTCHAR SF510000\nENCODING 9554\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n38\n20\n38\n20\n20\nENDCHAR\nSTARTCHAR SF520000\nENCODING 9555\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n78\n50\n50\n50\nENDCHAR\nSTARTCHAR SF390000\nENCODING 9556\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n78\n40\n58\n50\n50\nENDCHAR\nSTARTCHAR SF220000\nENCODING 9557\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\n20\nE0\n20\n20\nENDCHAR\nSTARTCHAR SF210000\nENCODING 9558\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nF0\n50\n50\n50\nENDCHAR\nSTARTCHAR SF250000\nENCODING 9559\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF0\n10\nD0\n50\n50\nENDCHAR\nSTARTCHAR SF500000\nENCODING 9560\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n38\n20\n38\n00\n00\nENDCHAR\nSTARTCHAR SF490000\nENCODING 9561\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n50\n78\n00\n00\n00\nENDCHAR\nSTARTCHAR SF380000\nENCODING 9562\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n58\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR SF280000\nENCODING 9563\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\nE0\n20\nE0\n00\n00\nENDCHAR\nSTARTCHAR SF270000\nENCODING 9564\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n50\nF0\n00\n00\n00\nENDCHAR\nSTARTCHAR SF260000\nENCODING 9565\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\nD0\n10\nF0\n00\n00\nENDCHAR\nSTARTCHAR SF360000\nENCODING 9566\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n38\n20\n38\n20\n20\nENDCHAR\nSTARTCHAR SF370000\nENCODING 9567\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n50\n58\n50\n50\n50\nENDCHAR\nSTARTCHAR SF420000\nENCODING 9568\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n58\n40\n58\n50\n50\nENDCHAR\nSTARTCHAR SF190000\nENCODING 9569\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\nE0\n20\nE0\n20\n20\nENDCHAR\nSTARTCHAR SF200000\nENCODING 9570\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n50\nD0\n50\n50\n50\nENDCHAR\nSTARTCHAR SF230000\nENCODING 9571\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\nD0\n10\nD0\n50\n50\nENDCHAR\nSTARTCHAR SF470000\nENCODING 9572\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF8\n00\nF8\n20\n20\nENDCHAR\nSTARTCHAR SF480000\nENCODING 9573\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nF8\n50\n50\n50\nENDCHAR\nSTARTCHAR SF410000\nENCODING 9574\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF8\n00\nD8\n50\n50\nENDCHAR\nSTARTCHAR SF450000\nENCODING 9575\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\nF8\n00\nF8\n00\n00\nENDCHAR\nSTARTCHAR SF460000\nENCODING 9576\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n50\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR SF400000\nENCODING 9577\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\nD8\n00\nF8\n00\n00\nENDCHAR\nSTARTCHAR SF540000\nENCODING 9578\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\nF8\n20\nF8\n20\n20\nENDCHAR\nSTARTCHAR SF530000\nENCODING 9579\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\n50\nF8\n50\n50\n50\nENDCHAR\nSTARTCHAR SF440000\nENCODING 9580\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n50\nD8\n00\nD8\n50\n50\nENDCHAR\nSTARTCHAR uni256D\nENCODING 9581\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n18\n20\n20\n20\nENDCHAR\nSTARTCHAR uni256E\nENCODING 9582\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nC0\n20\n20\n20\nENDCHAR\nSTARTCHAR uni256F\nENCODING 9583\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\nC0\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2570\nENCODING 9584\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\n18\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2571\nENCODING 9585\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n08\n10\n10\n20\n40\n40\n80\nENDCHAR\nSTARTCHAR uni2572\nENCODING 9586\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n40\n40\n20\n10\n10\n08\nENDCHAR\nSTARTCHAR uni2573\nENCODING 9587\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n88\n50\n50\n20\n50\n50\n88\nENDCHAR\nSTARTCHAR uni2574\nENCODING 9588\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nE0\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2575\nENCODING 9589\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2576\nENCODING 9590\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n38\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2577\nENCODING 9591\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n20\n20\n20\n20\nENDCHAR\nSTARTCHAR uni2578\nENCODING 9592\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\nE0\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2579\nENCODING 9593\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\n30\n30\n00\n00\n00\nENDCHAR\nSTARTCHAR uni257A\nENCODING 9594\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n38\n38\n00\n00\n00\nENDCHAR\nSTARTCHAR uni257B\nENCODING 9595\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n30\n30\n30\n30\nENDCHAR\nSTARTCHAR uni257C\nENCODING 9596\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n38\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR uni257D\nENCODING 9597\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n20\n30\n30\n30\n30\nENDCHAR\nSTARTCHAR uni257E\nENCODING 9598\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nE0\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR uni257F\nENCODING 9599\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n30\n30\n30\n20\n20\n20\nENDCHAR\nSTARTCHAR upblock\nENCODING 9600\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF8\nF8\nF8\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2581\nENCODING 9601\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\n00\nF8\nENDCHAR\nSTARTCHAR uni2582\nENCODING 9602\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\nF8\nF8\nENDCHAR\nSTARTCHAR uni2583\nENCODING 9603\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\nF8\nF8\nF8\nENDCHAR\nSTARTCHAR dnblock\nENCODING 9604\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nF8\nF8\nF8\nF8\nENDCHAR\nSTARTCHAR uni2585\nENCODING 9605\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nF8\nF8\nF8\nF8\nENDCHAR\nSTARTCHAR uni2586\nENCODING 9606\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF8\nF8\nF8\nF8\nF8\nENDCHAR\nSTARTCHAR uni2587\nENCODING 9607\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\nF8\nF8\nF8\nF8\nF8\nF8\nENDCHAR\nSTARTCHAR block\nENCODING 9608\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF8\nF8\nF8\nF8\nF8\nF8\nF8\nENDCHAR\nSTARTCHAR uni2589\nENCODING 9609\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nF0\nF0\nF0\nF0\nF0\nF0\nENDCHAR\nSTARTCHAR uni258A\nENCODING 9610\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF0\nF0\nF0\nF0\nF0\nF0\nF0\nENDCHAR\nSTARTCHAR uni258B\nENCODING 9611\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\nE0\nE0\nE0\nE0\nE0\nE0\nENDCHAR\nSTARTCHAR lfblock\nENCODING 9612\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\nE0\nE0\nE0\nE0\nE0\nE0\nENDCHAR\nSTARTCHAR uni258D\nENCODING 9613\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nC0\nC0\nC0\nC0\nC0\nC0\nC0\nENDCHAR\nSTARTCHAR uni258E\nENCODING 9614\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n80\n80\n80\n80\n80\n80\nENDCHAR\nSTARTCHAR uni258F\nENCODING 9615\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\n80\n80\n80\n80\n80\n80\nENDCHAR\nSTARTCHAR rtblock\nENCODING 9616\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n18\n18\n18\n18\n18\n18\n18\nENDCHAR\nSTARTCHAR ltshade\nENCODING 9617\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n10\n40\n10\n40\n10\n00\nENDCHAR\nSTARTCHAR shade\nENCODING 9618\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nA8\n50\nA8\n50\nA8\n50\nA8\nENDCHAR\nSTARTCHAR dkshade\nENCODING 9619\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nB8\nE8\nB8\nE8\nB8\nE8\nF8\nENDCHAR\nSTARTCHAR uni2594\nENCODING 9620\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF8\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2595\nENCODING 9621\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n08\n08\n08\n08\n08\n08\n08\nENDCHAR\nSTARTCHAR uni2596\nENCODING 9622\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\nE0\nE0\nE0\nE0\nENDCHAR\nSTARTCHAR uni2597\nENCODING 9623\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n18\n18\n18\n18\nENDCHAR\nSTARTCHAR uni2598\nENCODING 9624\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\nE0\nE0\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2599\nENCODING 9625\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\nE0\nE0\nF8\nF8\nF8\nF8\nENDCHAR\nSTARTCHAR uni259A\nENCODING 9626\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nE0\nE0\nE0\n18\n18\n18\n18\nENDCHAR\nSTARTCHAR uni259B\nENCODING 9627\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF8\nF8\nF8\nE0\nE0\nE0\nE0\nENDCHAR\nSTARTCHAR uni259C\nENCODING 9628\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF8\nF8\nF8\n18\n18\n18\n18\nENDCHAR\nSTARTCHAR uni259D\nENCODING 9629\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n18\n18\n18\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni259E\nENCODING 9630\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n18\n18\n18\nE0\nE0\nE0\nE0\nENDCHAR\nSTARTCHAR uni259F\nENCODING 9631\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n18\n18\n18\nF8\nF8\nF8\nF8\nENDCHAR\nSTARTCHAR filledbox\nENCODING 9632\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF0\nF0\nF0\nF0\n00\nENDCHAR\nSTARTCHAR H22073\nENCODING 9633\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF0\n90\n90\nF0\n00\nENDCHAR\nSTARTCHAR H18543\nENCODING 9642\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\n70\n70\n00\n00\nENDCHAR\nSTARTCHAR H18551\nENCODING 9643\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n70\n50\n70\n00\n00\nENDCHAR\nSTARTCHAR filledrect\nENCODING 9644\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF8\nF8\nF8\n00\n00\nENDCHAR\nSTARTCHAR uni25AD\nENCODING 9645\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\nF8\n88\nF8\n00\n00\nENDCHAR\nSTARTCHAR uni25AE\nENCODING 9646\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n70\n70\n70\n70\n70\n00\nENDCHAR\nSTARTCHAR triagup\nENCODING 9650\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n70\n70\nF8\nF8\n00\nENDCHAR\nSTARTCHAR uni25B3\nENCODING 9651\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n50\n50\n88\nF8\n00\nENDCHAR\nSTARTCHAR uni25B6\nENCODING 9654\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\nC0\nE0\nF0\nE0\nC0\n80\nENDCHAR\nSTARTCHAR uni25B7\nENCODING 9655\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n80\nC0\nA0\n90\nA0\nC0\n80\nENDCHAR\nSTARTCHAR uni25B8\nENCODING 9656\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n40\n60\n70\n60\n40\n00\nENDCHAR\nSTARTCHAR uni25B9\nENCODING 9657\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n40\n60\n50\n60\n40\n00\nENDCHAR\nSTARTCHAR triagrt\nENCODING 9658\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n80\nE0\nF8\nE0\n80\n00\nENDCHAR\nSTARTCHAR uni25BB\nENCODING 9659\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n80\nE0\n98\nE0\n80\n00\nENDCHAR\nSTARTCHAR triagdn\nENCODING 9660\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF8\nF8\n70\n70\n20\n20\n00\nENDCHAR\nSTARTCHAR uni25BD\nENCODING 9661\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF8\n88\n50\n50\n20\n20\n00\nENDCHAR\nSTARTCHAR uni25C0\nENCODING 9664\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n30\n70\nF0\n70\n30\n10\nENDCHAR\nSTARTCHAR uni25C1\nENCODING 9665\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n30\n50\n90\n50\n30\n10\nENDCHAR\nSTARTCHAR uni25C2\nENCODING 9666\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n10\n30\n70\n30\n10\n00\nENDCHAR\nSTARTCHAR uni25C3\nENCODING 9667\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n10\n30\n50\n30\n10\n00\nENDCHAR\nSTARTCHAR triaglf\nENCODING 9668\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n08\n38\nF8\n38\n08\n00\nENDCHAR\nSTARTCHAR uni25C5\nENCODING 9669\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n08\n38\nC8\n38\n08\n00\nENDCHAR\nSTARTCHAR uni25C6\nENCODING 9670\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n70\nF8\n70\n20\n00\nENDCHAR\nSTARTCHAR lozenge\nENCODING 9674\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n50\n88\n50\n20\n00\nENDCHAR\nSTARTCHAR circle\nENCODING 9675\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n70\n88\n88\n88\n70\n00\nENDCHAR\nSTARTCHAR H18533\nENCODING 9679\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n70\nF8\nF8\nF8\n70\n00\nENDCHAR\nSTARTCHAR invbullet\nENCODING 9688\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF8\nF8\nD8\n88\nD8\nF8\nF8\nENDCHAR\nSTARTCHAR invcircle\nENCODING 9689\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\nF8\nF8\nD8\nA8\nD8\nF8\nF8\nENDCHAR\nSTARTCHAR openbullet\nENCODING 9702\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n60\n90\n90\n60\n00\nENDCHAR\nSTARTCHAR uni2639\nENCODING 9785\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n50\n00\n20\n50\n00\n00\nENDCHAR\nSTARTCHAR smileface\nENCODING 9786\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n50\n00\n50\n20\n00\n00\nENDCHAR\nSTARTCHAR invsmileface\nENCODING 9787\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\nA8\nF8\nA8\nD8\n70\n00\nENDCHAR\nSTARTCHAR sun\nENCODING 9788\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\nA8\n70\nD8\n70\nA8\n20\nENDCHAR\nSTARTCHAR female\nENCODING 9792\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n50\n20\n70\n20\n00\nENDCHAR\nSTARTCHAR uni2641\nENCODING 9793\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n20\n70\n20\n50\n20\n00\nENDCHAR\nSTARTCHAR male\nENCODING 9794\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n38\n18\n68\nA0\n40\n00\n00\nENDCHAR\nSTARTCHAR spade\nENCODING 9824\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n70\nF8\nF8\n20\n70\n00\nENDCHAR\nSTARTCHAR club\nENCODING 9827\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n70\nA8\nF8\nA8\n20\n70\nENDCHAR\nSTARTCHAR heart\nENCODING 9829\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\nF8\nF8\n70\n70\n20\n00\nENDCHAR\nSTARTCHAR diamond\nENCODING 9830\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n70\nF8\nF8\n70\n20\n00\nENDCHAR\nSTARTCHAR uni2669\nENCODING 9833\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n10\n10\n30\n70\n20\n00\nENDCHAR\nSTARTCHAR musicalnote\nENCODING 9834\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n30\n28\n60\nE0\n40\n00\nENDCHAR\nSTARTCHAR musicalnotedbl\nENCODING 9835\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n60\n58\n48\nC8\nD8\n18\n00\nENDCHAR\nSTARTCHAR uni266C\nENCODING 9836\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n70\n68\n58\nC8\nD8\n18\n00\nENDCHAR\nSTARTCHAR uni266D\nENCODING 9837\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n40\n70\n50\n50\n60\n00\nENDCHAR\nSTARTCHAR uni266E\nENCODING 9838\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n70\n50\n50\n70\n10\n00\nENDCHAR\nSTARTCHAR uni266F\nENCODING 9839\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n58\n70\nD8\n70\nD0\n40\nENDCHAR\nSTARTCHAR uni27E8\nENCODING 10216\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n20\n40\n40\n20\n20\n00\nENDCHAR\nSTARTCHAR uni27E9\nENCODING 10217\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n40\n20\n20\n40\n40\n00\nENDCHAR\nSTARTCHAR uni2800\nENCODING 10240\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2801\nENCODING 10241\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2802\nENCODING 10242\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2803\nENCODING 10243\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n40\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2804\nENCODING 10244\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n40\n00\n00\nENDCHAR\nSTARTCHAR uni2805\nENCODING 10245\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n00\n00\n40\n00\n00\nENDCHAR\nSTARTCHAR uni2806\nENCODING 10246\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\n00\n40\n00\n00\nENDCHAR\nSTARTCHAR uni2807\nENCODING 10247\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n40\n00\n40\n00\n00\nENDCHAR\nSTARTCHAR uni2808\nENCODING 10248\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2809\nENCODING 10249\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni280A\nENCODING 10250\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n40\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni280B\nENCODING 10251\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n40\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni280C\nENCODING 10252\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n00\n00\n40\n00\n00\nENDCHAR\nSTARTCHAR uni280D\nENCODING 10253\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n00\n00\n40\n00\n00\nENDCHAR\nSTARTCHAR uni280E\nENCODING 10254\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n40\n00\n40\n00\n00\nENDCHAR\nSTARTCHAR uni280F\nENCODING 10255\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n40\n00\n40\n00\n00\nENDCHAR\nSTARTCHAR uni2810\nENCODING 10256\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n10\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2811\nENCODING 10257\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n10\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2812\nENCODING 10258\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2813\nENCODING 10259\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n50\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2814\nENCODING 10260\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n10\n00\n40\n00\n00\nENDCHAR\nSTARTCHAR uni2815\nENCODING 10261\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n10\n00\n40\n00\n00\nENDCHAR\nSTARTCHAR uni2816\nENCODING 10262\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n00\n40\n00\n00\nENDCHAR\nSTARTCHAR uni2817\nENCODING 10263\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n50\n00\n40\n00\n00\nENDCHAR\nSTARTCHAR uni2818\nENCODING 10264\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n10\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2819\nENCODING 10265\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n10\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni281A\nENCODING 10266\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n50\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni281B\nENCODING 10267\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n50\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni281C\nENCODING 10268\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n10\n00\n40\n00\n00\nENDCHAR\nSTARTCHAR uni281D\nENCODING 10269\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n10\n00\n40\n00\n00\nENDCHAR\nSTARTCHAR uni281E\nENCODING 10270\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n50\n00\n40\n00\n00\nENDCHAR\nSTARTCHAR uni281F\nENCODING 10271\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n50\n00\n40\n00\n00\nENDCHAR\nSTARTCHAR uni2820\nENCODING 10272\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n10\n00\n00\nENDCHAR\nSTARTCHAR uni2821\nENCODING 10273\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n00\n00\n10\n00\n00\nENDCHAR\nSTARTCHAR uni2822\nENCODING 10274\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\n00\n10\n00\n00\nENDCHAR\nSTARTCHAR uni2823\nENCODING 10275\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n40\n00\n10\n00\n00\nENDCHAR\nSTARTCHAR uni2824\nENCODING 10276\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n50\n00\n00\nENDCHAR\nSTARTCHAR uni2825\nENCODING 10277\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n00\n00\n50\n00\n00\nENDCHAR\nSTARTCHAR uni2826\nENCODING 10278\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\n00\n50\n00\n00\nENDCHAR\nSTARTCHAR uni2827\nENCODING 10279\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n40\n00\n50\n00\n00\nENDCHAR\nSTARTCHAR uni2828\nENCODING 10280\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n00\n00\n10\n00\n00\nENDCHAR\nSTARTCHAR uni2829\nENCODING 10281\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n00\n00\n10\n00\n00\nENDCHAR\nSTARTCHAR uni282A\nENCODING 10282\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n40\n00\n10\n00\n00\nENDCHAR\nSTARTCHAR uni282B\nENCODING 10283\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n40\n00\n10\n00\n00\nENDCHAR\nSTARTCHAR uni282C\nENCODING 10284\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n00\n00\n50\n00\n00\nENDCHAR\nSTARTCHAR uni282D\nENCODING 10285\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n00\n00\n50\n00\n00\nENDCHAR\nSTARTCHAR uni282E\nENCODING 10286\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n40\n00\n50\n00\n00\nENDCHAR\nSTARTCHAR uni282F\nENCODING 10287\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n40\n00\n50\n00\n00\nENDCHAR\nSTARTCHAR uni2830\nENCODING 10288\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n10\n00\n10\n00\n00\nENDCHAR\nSTARTCHAR uni2831\nENCODING 10289\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n10\n00\n10\n00\n00\nENDCHAR\nSTARTCHAR uni2832\nENCODING 10290\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n00\n10\n00\n00\nENDCHAR\nSTARTCHAR uni2833\nENCODING 10291\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n50\n00\n10\n00\n00\nENDCHAR\nSTARTCHAR uni2834\nENCODING 10292\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n10\n00\n50\n00\n00\nENDCHAR\nSTARTCHAR uni2835\nENCODING 10293\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n10\n00\n50\n00\n00\nENDCHAR\nSTARTCHAR uni2836\nENCODING 10294\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n00\n50\n00\n00\nENDCHAR\nSTARTCHAR uni2837\nENCODING 10295\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n50\n00\n50\n00\n00\nENDCHAR\nSTARTCHAR uni2838\nENCODING 10296\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n10\n00\n10\n00\n00\nENDCHAR\nSTARTCHAR uni2839\nENCODING 10297\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n10\n00\n10\n00\n00\nENDCHAR\nSTARTCHAR uni283A\nENCODING 10298\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n50\n00\n10\n00\n00\nENDCHAR\nSTARTCHAR uni283B\nENCODING 10299\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n50\n00\n10\n00\n00\nENDCHAR\nSTARTCHAR uni283C\nENCODING 10300\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n10\n00\n50\n00\n00\nENDCHAR\nSTARTCHAR uni283D\nENCODING 10301\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n10\n00\n50\n00\n00\nENDCHAR\nSTARTCHAR uni283E\nENCODING 10302\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n50\n00\n50\n00\n00\nENDCHAR\nSTARTCHAR uni283F\nENCODING 10303\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n50\n00\n50\n00\n00\nENDCHAR\nSTARTCHAR uni2840\nENCODING 10304\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\n00\n40\nENDCHAR\nSTARTCHAR uni2841\nENCODING 10305\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n00\n00\n00\n00\n40\nENDCHAR\nSTARTCHAR uni2842\nENCODING 10306\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\n00\n00\n00\n40\nENDCHAR\nSTARTCHAR uni2843\nENCODING 10307\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n40\n00\n00\n00\n40\nENDCHAR\nSTARTCHAR uni2844\nENCODING 10308\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n40\n00\n40\nENDCHAR\nSTARTCHAR uni2845\nENCODING 10309\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n00\n00\n40\n00\n40\nENDCHAR\nSTARTCHAR uni2846\nENCODING 10310\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\n00\n40\n00\n40\nENDCHAR\nSTARTCHAR uni2847\nENCODING 10311\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n40\n00\n40\n00\n40\nENDCHAR\nSTARTCHAR uni2848\nENCODING 10312\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n00\n00\n00\n00\n40\nENDCHAR\nSTARTCHAR uni2849\nENCODING 10313\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n00\n00\n00\n00\n40\nENDCHAR\nSTARTCHAR uni284A\nENCODING 10314\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n40\n00\n00\n00\n40\nENDCHAR\nSTARTCHAR uni284B\nENCODING 10315\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n40\n00\n00\n00\n40\nENDCHAR\nSTARTCHAR uni284C\nENCODING 10316\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n00\n00\n40\n00\n40\nENDCHAR\nSTARTCHAR uni284D\nENCODING 10317\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n00\n00\n40\n00\n40\nENDCHAR\nSTARTCHAR uni284E\nENCODING 10318\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n40\n00\n40\n00\n40\nENDCHAR\nSTARTCHAR uni284F\nENCODING 10319\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n40\n00\n40\n00\n40\nENDCHAR\nSTARTCHAR uni2850\nENCODING 10320\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n10\n00\n00\n00\n40\nENDCHAR\nSTARTCHAR uni2851\nENCODING 10321\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n10\n00\n00\n00\n40\nENDCHAR\nSTARTCHAR uni2852\nENCODING 10322\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n00\n00\n00\n40\nENDCHAR\nSTARTCHAR uni2853\nENCODING 10323\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n50\n00\n00\n00\n40\nENDCHAR\nSTARTCHAR uni2854\nENCODING 10324\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n10\n00\n40\n00\n40\nENDCHAR\nSTARTCHAR uni2855\nENCODING 10325\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n10\n00\n40\n00\n40\nENDCHAR\nSTARTCHAR uni2856\nENCODING 10326\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n00\n40\n00\n40\nENDCHAR\nSTARTCHAR uni2857\nENCODING 10327\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n50\n00\n40\n00\n40\nENDCHAR\nSTARTCHAR uni2858\nENCODING 10328\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n10\n00\n00\n00\n40\nENDCHAR\nSTARTCHAR uni2859\nENCODING 10329\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n10\n00\n00\n00\n40\nENDCHAR\nSTARTCHAR uni285A\nENCODING 10330\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n50\n00\n00\n00\n40\nENDCHAR\nSTARTCHAR uni285B\nENCODING 10331\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n50\n00\n00\n00\n40\nENDCHAR\nSTARTCHAR uni285C\nENCODING 10332\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n10\n00\n40\n00\n40\nENDCHAR\nSTARTCHAR uni285D\nENCODING 10333\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n10\n00\n40\n00\n40\nENDCHAR\nSTARTCHAR uni285E\nENCODING 10334\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n50\n00\n40\n00\n40\nENDCHAR\nSTARTCHAR uni285F\nENCODING 10335\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n50\n00\n40\n00\n40\nENDCHAR\nSTARTCHAR uni2860\nENCODING 10336\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n10\n00\n40\nENDCHAR\nSTARTCHAR uni2861\nENCODING 10337\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n00\n00\n10\n00\n40\nENDCHAR\nSTARTCHAR uni2862\nENCODING 10338\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\n00\n10\n00\n40\nENDCHAR\nSTARTCHAR uni2863\nENCODING 10339\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n40\n00\n10\n00\n40\nENDCHAR\nSTARTCHAR uni2864\nENCODING 10340\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n50\n00\n40\nENDCHAR\nSTARTCHAR uni2865\nENCODING 10341\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n00\n00\n50\n00\n40\nENDCHAR\nSTARTCHAR uni2866\nENCODING 10342\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\n00\n50\n00\n40\nENDCHAR\nSTARTCHAR uni2867\nENCODING 10343\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n40\n00\n50\n00\n40\nENDCHAR\nSTARTCHAR uni2868\nENCODING 10344\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n00\n00\n10\n00\n40\nENDCHAR\nSTARTCHAR uni2869\nENCODING 10345\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n00\n00\n10\n00\n40\nENDCHAR\nSTARTCHAR uni286A\nENCODING 10346\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n40\n00\n10\n00\n40\nENDCHAR\nSTARTCHAR uni286B\nENCODING 10347\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n40\n00\n10\n00\n40\nENDCHAR\nSTARTCHAR uni286C\nENCODING 10348\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n00\n00\n50\n00\n40\nENDCHAR\nSTARTCHAR uni286D\nENCODING 10349\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n00\n00\n50\n00\n40\nENDCHAR\nSTARTCHAR uni286E\nENCODING 10350\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n40\n00\n50\n00\n40\nENDCHAR\nSTARTCHAR uni286F\nENCODING 10351\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n40\n00\n50\n00\n40\nENDCHAR\nSTARTCHAR uni2870\nENCODING 10352\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n10\n00\n10\n00\n40\nENDCHAR\nSTARTCHAR uni2871\nENCODING 10353\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n10\n00\n10\n00\n40\nENDCHAR\nSTARTCHAR uni2872\nENCODING 10354\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n00\n10\n00\n40\nENDCHAR\nSTARTCHAR uni2873\nENCODING 10355\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n50\n00\n10\n00\n40\nENDCHAR\nSTARTCHAR uni2874\nENCODING 10356\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n10\n00\n50\n00\n40\nENDCHAR\nSTARTCHAR uni2875\nENCODING 10357\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n10\n00\n50\n00\n40\nENDCHAR\nSTARTCHAR uni2876\nENCODING 10358\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n00\n50\n00\n40\nENDCHAR\nSTARTCHAR uni2877\nENCODING 10359\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n50\n00\n50\n00\n40\nENDCHAR\nSTARTCHAR uni2878\nENCODING 10360\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n10\n00\n10\n00\n40\nENDCHAR\nSTARTCHAR uni2879\nENCODING 10361\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n10\n00\n10\n00\n40\nENDCHAR\nSTARTCHAR uni287A\nENCODING 10362\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n50\n00\n10\n00\n40\nENDCHAR\nSTARTCHAR uni287B\nENCODING 10363\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n50\n00\n10\n00\n40\nENDCHAR\nSTARTCHAR uni287C\nENCODING 10364\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n10\n00\n50\n00\n40\nENDCHAR\nSTARTCHAR uni287D\nENCODING 10365\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n10\n00\n50\n00\n40\nENDCHAR\nSTARTCHAR uni287E\nENCODING 10366\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n50\n00\n50\n00\n40\nENDCHAR\nSTARTCHAR uni287F\nENCODING 10367\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n50\n00\n50\n00\n40\nENDCHAR\nSTARTCHAR uni2880\nENCODING 10368\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\n00\n10\nENDCHAR\nSTARTCHAR uni2881\nENCODING 10369\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n00\n00\n00\n00\n10\nENDCHAR\nSTARTCHAR uni2882\nENCODING 10370\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\n00\n00\n00\n10\nENDCHAR\nSTARTCHAR uni2883\nENCODING 10371\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n40\n00\n00\n00\n10\nENDCHAR\nSTARTCHAR uni2884\nENCODING 10372\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n40\n00\n10\nENDCHAR\nSTARTCHAR uni2885\nENCODING 10373\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n00\n00\n40\n00\n10\nENDCHAR\nSTARTCHAR uni2886\nENCODING 10374\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\n00\n40\n00\n10\nENDCHAR\nSTARTCHAR uni2887\nENCODING 10375\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n40\n00\n40\n00\n10\nENDCHAR\nSTARTCHAR uni2888\nENCODING 10376\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n00\n00\n00\n00\n10\nENDCHAR\nSTARTCHAR uni2889\nENCODING 10377\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n00\n00\n00\n00\n10\nENDCHAR\nSTARTCHAR uni288A\nENCODING 10378\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n40\n00\n00\n00\n10\nENDCHAR\nSTARTCHAR uni288B\nENCODING 10379\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n40\n00\n00\n00\n10\nENDCHAR\nSTARTCHAR uni288C\nENCODING 10380\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n00\n00\n40\n00\n10\nENDCHAR\nSTARTCHAR uni288D\nENCODING 10381\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n00\n00\n40\n00\n10\nENDCHAR\nSTARTCHAR uni288E\nENCODING 10382\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n40\n00\n40\n00\n10\nENDCHAR\nSTARTCHAR uni288F\nENCODING 10383\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n40\n00\n40\n00\n10\nENDCHAR\nSTARTCHAR uni2890\nENCODING 10384\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n10\n00\n00\n00\n10\nENDCHAR\nSTARTCHAR uni2891\nENCODING 10385\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n10\n00\n00\n00\n10\nENDCHAR\nSTARTCHAR uni2892\nENCODING 10386\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n00\n00\n00\n10\nENDCHAR\nSTARTCHAR uni2893\nENCODING 10387\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n50\n00\n00\n00\n10\nENDCHAR\nSTARTCHAR uni2894\nENCODING 10388\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n10\n00\n40\n00\n10\nENDCHAR\nSTARTCHAR uni2895\nENCODING 10389\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n10\n00\n40\n00\n10\nENDCHAR\nSTARTCHAR uni2896\nENCODING 10390\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n00\n40\n00\n10\nENDCHAR\nSTARTCHAR uni2897\nENCODING 10391\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n50\n00\n40\n00\n10\nENDCHAR\nSTARTCHAR uni2898\nENCODING 10392\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n10\n00\n00\n00\n10\nENDCHAR\nSTARTCHAR uni2899\nENCODING 10393\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n10\n00\n00\n00\n10\nENDCHAR\nSTARTCHAR uni289A\nENCODING 10394\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n50\n00\n00\n00\n10\nENDCHAR\nSTARTCHAR uni289B\nENCODING 10395\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n50\n00\n00\n00\n10\nENDCHAR\nSTARTCHAR uni289C\nENCODING 10396\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n10\n00\n40\n00\n10\nENDCHAR\nSTARTCHAR uni289D\nENCODING 10397\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n10\n00\n40\n00\n10\nENDCHAR\nSTARTCHAR uni289E\nENCODING 10398\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n50\n00\n40\n00\n10\nENDCHAR\nSTARTCHAR uni289F\nENCODING 10399\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n50\n00\n40\n00\n10\nENDCHAR\nSTARTCHAR uni28A0\nENCODING 10400\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n10\n00\n10\nENDCHAR\nSTARTCHAR uni28A1\nENCODING 10401\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n00\n00\n10\n00\n10\nENDCHAR\nSTARTCHAR uni28A2\nENCODING 10402\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\n00\n10\n00\n10\nENDCHAR\nSTARTCHAR uni28A3\nENCODING 10403\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n40\n00\n10\n00\n10\nENDCHAR\nSTARTCHAR uni28A4\nENCODING 10404\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n50\n00\n10\nENDCHAR\nSTARTCHAR uni28A5\nENCODING 10405\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n00\n00\n50\n00\n10\nENDCHAR\nSTARTCHAR uni28A6\nENCODING 10406\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\n00\n50\n00\n10\nENDCHAR\nSTARTCHAR uni28A7\nENCODING 10407\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n40\n00\n50\n00\n10\nENDCHAR\nSTARTCHAR uni28A8\nENCODING 10408\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n00\n00\n10\n00\n10\nENDCHAR\nSTARTCHAR uni28A9\nENCODING 10409\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n00\n00\n10\n00\n10\nENDCHAR\nSTARTCHAR uni28AA\nENCODING 10410\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n40\n00\n10\n00\n10\nENDCHAR\nSTARTCHAR uni28AB\nENCODING 10411\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n40\n00\n10\n00\n10\nENDCHAR\nSTARTCHAR uni28AC\nENCODING 10412\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n00\n00\n50\n00\n10\nENDCHAR\nSTARTCHAR uni28AD\nENCODING 10413\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n00\n00\n50\n00\n10\nENDCHAR\nSTARTCHAR uni28AE\nENCODING 10414\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n40\n00\n50\n00\n10\nENDCHAR\nSTARTCHAR uni28AF\nENCODING 10415\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n40\n00\n50\n00\n10\nENDCHAR\nSTARTCHAR uni28B0\nENCODING 10416\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n10\n00\n10\n00\n10\nENDCHAR\nSTARTCHAR uni28B1\nENCODING 10417\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n10\n00\n10\n00\n10\nENDCHAR\nSTARTCHAR uni28B2\nENCODING 10418\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n00\n10\n00\n10\nENDCHAR\nSTARTCHAR uni28B3\nENCODING 10419\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n50\n00\n10\n00\n10\nENDCHAR\nSTARTCHAR uni28B4\nENCODING 10420\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n10\n00\n50\n00\n10\nENDCHAR\nSTARTCHAR uni28B5\nENCODING 10421\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n10\n00\n50\n00\n10\nENDCHAR\nSTARTCHAR uni28B6\nENCODING 10422\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n00\n50\n00\n10\nENDCHAR\nSTARTCHAR uni28B7\nENCODING 10423\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n50\n00\n50\n00\n10\nENDCHAR\nSTARTCHAR uni28B8\nENCODING 10424\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n10\n00\n10\n00\n10\nENDCHAR\nSTARTCHAR uni28B9\nENCODING 10425\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n10\n00\n10\n00\n10\nENDCHAR\nSTARTCHAR uni28BA\nENCODING 10426\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n50\n00\n10\n00\n10\nENDCHAR\nSTARTCHAR uni28BB\nENCODING 10427\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n50\n00\n10\n00\n10\nENDCHAR\nSTARTCHAR uni28BC\nENCODING 10428\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n10\n00\n50\n00\n10\nENDCHAR\nSTARTCHAR uni28BD\nENCODING 10429\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n10\n00\n50\n00\n10\nENDCHAR\nSTARTCHAR uni28BE\nENCODING 10430\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n50\n00\n50\n00\n10\nENDCHAR\nSTARTCHAR uni28BF\nENCODING 10431\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n50\n00\n50\n00\n10\nENDCHAR\nSTARTCHAR uni28C0\nENCODING 10432\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n00\n00\n50\nENDCHAR\nSTARTCHAR uni28C1\nENCODING 10433\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n00\n00\n00\n00\n50\nENDCHAR\nSTARTCHAR uni28C2\nENCODING 10434\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\n00\n00\n00\n50\nENDCHAR\nSTARTCHAR uni28C3\nENCODING 10435\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n40\n00\n00\n00\n50\nENDCHAR\nSTARTCHAR uni28C4\nENCODING 10436\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n40\n00\n50\nENDCHAR\nSTARTCHAR uni28C5\nENCODING 10437\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n00\n00\n40\n00\n50\nENDCHAR\nSTARTCHAR uni28C6\nENCODING 10438\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\n00\n40\n00\n50\nENDCHAR\nSTARTCHAR uni28C7\nENCODING 10439\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n40\n00\n40\n00\n50\nENDCHAR\nSTARTCHAR uni28C8\nENCODING 10440\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n00\n00\n00\n00\n50\nENDCHAR\nSTARTCHAR uni28C9\nENCODING 10441\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n00\n00\n00\n00\n50\nENDCHAR\nSTARTCHAR uni28CA\nENCODING 10442\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n40\n00\n00\n00\n50\nENDCHAR\nSTARTCHAR uni28CB\nENCODING 10443\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n40\n00\n00\n00\n50\nENDCHAR\nSTARTCHAR uni28CC\nENCODING 10444\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n00\n00\n40\n00\n50\nENDCHAR\nSTARTCHAR uni28CD\nENCODING 10445\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n00\n00\n40\n00\n50\nENDCHAR\nSTARTCHAR uni28CE\nENCODING 10446\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n40\n00\n40\n00\n50\nENDCHAR\nSTARTCHAR uni28CF\nENCODING 10447\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n40\n00\n40\n00\n50\nENDCHAR\nSTARTCHAR uni28D0\nENCODING 10448\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n10\n00\n00\n00\n50\nENDCHAR\nSTARTCHAR uni28D1\nENCODING 10449\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n10\n00\n00\n00\n50\nENDCHAR\nSTARTCHAR uni28D2\nENCODING 10450\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n00\n00\n00\n50\nENDCHAR\nSTARTCHAR uni28D3\nENCODING 10451\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n50\n00\n00\n00\n50\nENDCHAR\nSTARTCHAR uni28D4\nENCODING 10452\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n10\n00\n40\n00\n50\nENDCHAR\nSTARTCHAR uni28D5\nENCODING 10453\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n10\n00\n40\n00\n50\nENDCHAR\nSTARTCHAR uni28D6\nENCODING 10454\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n00\n40\n00\n50\nENDCHAR\nSTARTCHAR uni28D7\nENCODING 10455\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n50\n00\n40\n00\n50\nENDCHAR\nSTARTCHAR uni28D8\nENCODING 10456\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n10\n00\n00\n00\n50\nENDCHAR\nSTARTCHAR uni28D9\nENCODING 10457\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n10\n00\n00\n00\n50\nENDCHAR\nSTARTCHAR uni28DA\nENCODING 10458\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n50\n00\n00\n00\n50\nENDCHAR\nSTARTCHAR uni28DB\nENCODING 10459\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n50\n00\n00\n00\n50\nENDCHAR\nSTARTCHAR uni28DC\nENCODING 10460\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n10\n00\n40\n00\n50\nENDCHAR\nSTARTCHAR uni28DD\nENCODING 10461\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n10\n00\n40\n00\n50\nENDCHAR\nSTARTCHAR uni28DE\nENCODING 10462\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n50\n00\n40\n00\n50\nENDCHAR\nSTARTCHAR uni28DF\nENCODING 10463\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n50\n00\n40\n00\n50\nENDCHAR\nSTARTCHAR uni28E0\nENCODING 10464\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n10\n00\n50\nENDCHAR\nSTARTCHAR uni28E1\nENCODING 10465\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n00\n00\n10\n00\n50\nENDCHAR\nSTARTCHAR uni28E2\nENCODING 10466\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\n00\n10\n00\n50\nENDCHAR\nSTARTCHAR uni28E3\nENCODING 10467\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n40\n00\n10\n00\n50\nENDCHAR\nSTARTCHAR uni28E4\nENCODING 10468\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n00\n00\n50\n00\n50\nENDCHAR\nSTARTCHAR uni28E5\nENCODING 10469\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n00\n00\n50\n00\n50\nENDCHAR\nSTARTCHAR uni28E6\nENCODING 10470\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n40\n00\n50\n00\n50\nENDCHAR\nSTARTCHAR uni28E7\nENCODING 10471\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n40\n00\n50\n00\n50\nENDCHAR\nSTARTCHAR uni28E8\nENCODING 10472\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n00\n00\n10\n00\n50\nENDCHAR\nSTARTCHAR uni28E9\nENCODING 10473\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n00\n00\n10\n00\n50\nENDCHAR\nSTARTCHAR uni28EA\nENCODING 10474\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n40\n00\n10\n00\n50\nENDCHAR\nSTARTCHAR uni28EB\nENCODING 10475\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n40\n00\n10\n00\n50\nENDCHAR\nSTARTCHAR uni28EC\nENCODING 10476\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n00\n00\n50\n00\n50\nENDCHAR\nSTARTCHAR uni28ED\nENCODING 10477\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n00\n00\n50\n00\n50\nENDCHAR\nSTARTCHAR uni28EE\nENCODING 10478\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n40\n00\n50\n00\n50\nENDCHAR\nSTARTCHAR uni28EF\nENCODING 10479\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n40\n00\n50\n00\n50\nENDCHAR\nSTARTCHAR uni28F0\nENCODING 10480\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n10\n00\n10\n00\n50\nENDCHAR\nSTARTCHAR uni28F1\nENCODING 10481\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n10\n00\n10\n00\n50\nENDCHAR\nSTARTCHAR uni28F2\nENCODING 10482\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n00\n10\n00\n50\nENDCHAR\nSTARTCHAR uni28F3\nENCODING 10483\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n50\n00\n10\n00\n50\nENDCHAR\nSTARTCHAR uni28F4\nENCODING 10484\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n10\n00\n50\n00\n50\nENDCHAR\nSTARTCHAR uni28F5\nENCODING 10485\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n10\n00\n50\n00\n50\nENDCHAR\nSTARTCHAR uni28F6\nENCODING 10486\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n00\n00\n50\n00\n50\n00\n50\nENDCHAR\nSTARTCHAR uni28F7\nENCODING 10487\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n40\n00\n50\n00\n50\n00\n50\nENDCHAR\nSTARTCHAR uni28F8\nENCODING 10488\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n10\n00\n10\n00\n50\nENDCHAR\nSTARTCHAR uni28F9\nENCODING 10489\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n10\n00\n10\n00\n50\nENDCHAR\nSTARTCHAR uni28FA\nENCODING 10490\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n50\n00\n10\n00\n50\nENDCHAR\nSTARTCHAR uni28FB\nENCODING 10491\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n50\n00\n10\n00\n50\nENDCHAR\nSTARTCHAR uni28FC\nENCODING 10492\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n10\n00\n50\n00\n50\nENDCHAR\nSTARTCHAR uni28FD\nENCODING 10493\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n10\n00\n50\n00\n50\nENDCHAR\nSTARTCHAR uni28FE\nENCODING 10494\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n10\n00\n50\n00\n50\n00\n50\nENDCHAR\nSTARTCHAR uni28FF\nENCODING 10495\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\n00\n50\n00\n50\n00\n50\nENDCHAR\nSTARTCHAR fi\nENCODING 64257\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n20\n50\n40\nF0\n50\n50\n00\nENDCHAR\nSTARTCHAR fl\nENCODING 64258\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n30\n50\n50\nF0\n50\n50\n00\nENDCHAR\nSTARTCHAR uniFFFD\nENCODING 65533\nSWIDTH 685 0\nDWIDTH 5 0\nBBX 5 7 0 -1\nBITMAP\n50\nA8\nE8\nD8\nF8\nD8\n70\nENDCHAR\nENDFONT\n"
  },
  {
    "path": "share/examples/gpanel/fonts/bdf/6x9.bdf",
    "content": "STARTFONT 2.1\nCOMMENT $Id: 6x9.bdf,v 1.28 2006-01-05 20:03:17+00 mgk25 Rel $\nCOMMENT Send bug reports to Markus Kuhn <http://www.cl.cam.ac.uk/~mgk25/>\nFONT -Misc-Fixed-Medium-R-Normal--9-90-75-75-C-60-ISO10646-1\nSIZE 9 75 75\nFONTBOUNDINGBOX 6 9 0 -2\nSTARTPROPERTIES 22\nFONTNAME_REGISTRY \"\"\nFOUNDRY \"Misc\"\nFAMILY_NAME \"Fixed\"\nWEIGHT_NAME \"Medium\"\nSLANT \"R\"\nSETWIDTH_NAME \"Normal\"\nADD_STYLE_NAME \"\"\nPIXEL_SIZE 9\nPOINT_SIZE 90\nRESOLUTION_X 75\nRESOLUTION_Y 75\nSPACING \"C\"\nAVERAGE_WIDTH 60\nCHARSET_REGISTRY \"ISO10646\"\nCHARSET_ENCODING \"1\"\nFONT_ASCENT 7\nFONT_DESCENT 2\nDEFAULT_CHAR 0\nCOPYRIGHT \"Public domain font.  Share and enjoy.\"\n_XMBDFED_INFO \"Edited with xmbdfed 4.5.\"\nCAP_HEIGHT 6\nX_HEIGHT 4\nENDPROPERTIES\nCHARS 1296\nSTARTCHAR char0\nENCODING 0\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n28\n40\n08\n40\n08\n50\n00\n00\nENDCHAR\nSTARTCHAR space\nENCODING 32\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR exclam\nENCODING 33\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\n20\n20\n00\n20\n00\n00\nENDCHAR\nSTARTCHAR quotedbl\nENCODING 34\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n50\n50\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR numbersign\nENCODING 35\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n50\nF8\n50\nF8\n50\n50\n00\nENDCHAR\nSTARTCHAR dollar\nENCODING 36\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n70\nA8\nA0\n70\n28\nA8\n70\n20\nENDCHAR\nSTARTCHAR percent\nENCODING 37\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n40\nA8\n48\n10\n20\n48\n54\n08\n00\nENDCHAR\nSTARTCHAR ampersand\nENCODING 38\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n60\n90\n90\n60\n98\n90\n68\n00\nENDCHAR\nSTARTCHAR quotesingle\nENCODING 39\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\n20\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR parenleft\nENCODING 40\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n20\n20\n20\n20\n20\n10\n00\nENDCHAR\nSTARTCHAR parenright\nENCODING 41\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n10\n10\n10\n10\n10\n20\n00\nENDCHAR\nSTARTCHAR asterisk\nENCODING 42\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n88\n50\nF8\n50\n88\n00\n00\nENDCHAR\nSTARTCHAR plus\nENCODING 43\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n20\n20\nF8\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR comma\nENCODING 44\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n30\n10\n10\n20\nENDCHAR\nSTARTCHAR hyphen\nENCODING 45\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\nF8\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR period\nENCODING 46\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n30\n30\n00\n00\nENDCHAR\nSTARTCHAR slash\nENCODING 47\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n08\n08\n10\n20\n40\n40\n00\n00\nENDCHAR\nSTARTCHAR zero\nENCODING 48\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n48\n48\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR one\nENCODING 49\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n60\n20\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR two\nENCODING 50\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n48\n08\n10\n20\n78\n00\n00\nENDCHAR\nSTARTCHAR three\nENCODING 51\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n10\n30\n08\n08\n70\n00\n00\nENDCHAR\nSTARTCHAR four\nENCODING 52\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n30\n50\n90\nF8\n10\n00\n00\nENDCHAR\nSTARTCHAR five\nENCODING 53\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n40\n70\n08\n08\n70\n00\n00\nENDCHAR\nSTARTCHAR six\nENCODING 54\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n40\n70\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR seven\nENCODING 55\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n08\n08\n10\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR eight\nENCODING 56\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n48\n30\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR nine\nENCODING 57\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n48\n48\n38\n08\n30\n00\n00\nENDCHAR\nSTARTCHAR colon\nENCODING 58\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n30\n30\n00\n30\n30\n00\n00\nENDCHAR\nSTARTCHAR semicolon\nENCODING 59\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n30\n30\n00\n30\n10\n10\n20\nENDCHAR\nSTARTCHAR less\nENCODING 60\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n18\n60\n80\n60\n18\n00\n00\nENDCHAR\nSTARTCHAR equal\nENCODING 61\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\nF8\n00\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR greater\nENCODING 62\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\nC0\n30\n08\n30\nC0\n00\n00\nENDCHAR\nSTARTCHAR question\nENCODING 63\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n30\n48\n08\n30\n20\n00\n20\n00\n00\nENDCHAR\nSTARTCHAR at\nENCODING 64\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n90\nA8\nB0\n80\n70\n00\n00\nENDCHAR\nSTARTCHAR A\nENCODING 65\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n50\n88\nF8\n88\n88\n00\n00\nENDCHAR\nSTARTCHAR B\nENCODING 66\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nF0\n88\nF0\n88\n88\nF0\n00\n00\nENDCHAR\nSTARTCHAR C\nENCODING 67\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n48\n40\n40\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR D\nENCODING 68\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n48\n48\n48\n48\n70\n00\n00\nENDCHAR\nSTARTCHAR E\nENCODING 69\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n40\n70\n40\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR F\nENCODING 70\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n40\n70\n40\n40\n40\n00\n00\nENDCHAR\nSTARTCHAR G\nENCODING 71\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n48\n40\n58\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR H\nENCODING 72\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n48\n48\n78\n48\n48\n48\n00\n00\nENDCHAR\nSTARTCHAR I\nENCODING 73\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n20\n20\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR J\nENCODING 74\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n38\n10\n10\n10\n90\n60\n00\n00\nENDCHAR\nSTARTCHAR K\nENCODING 75\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n48\n50\n60\n50\n48\n48\n00\n00\nENDCHAR\nSTARTCHAR L\nENCODING 76\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n40\n40\n40\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR M\nENCODING 77\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n88\nD8\nA8\nA8\n88\n88\n00\n00\nENDCHAR\nSTARTCHAR N\nENCODING 78\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n48\n68\n58\n48\n48\n48\n00\n00\nENDCHAR\nSTARTCHAR O\nENCODING 79\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n88\n88\n88\n88\n70\n00\n00\nENDCHAR\nSTARTCHAR P\nENCODING 80\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n48\n48\n70\n40\n40\n00\n00\nENDCHAR\nSTARTCHAR Q\nENCODING 81\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n48\n48\n68\n58\n30\n08\n00\nENDCHAR\nSTARTCHAR R\nENCODING 82\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n48\n48\n70\n48\n48\n00\n00\nENDCHAR\nSTARTCHAR S\nENCODING 83\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n48\n20\n10\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR T\nENCODING 84\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nF8\n20\n20\n20\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR U\nENCODING 85\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n48\n48\n48\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR V\nENCODING 86\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n48\n48\n48\n78\n30\n30\n00\n00\nENDCHAR\nSTARTCHAR W\nENCODING 87\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n88\n88\nA8\nA8\nD8\n88\n00\n00\nENDCHAR\nSTARTCHAR X\nENCODING 88\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n88\n50\n20\n20\n50\n88\n00\n00\nENDCHAR\nSTARTCHAR Y\nENCODING 89\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n88\n88\n50\n20\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR Z\nENCODING 90\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n08\n10\n20\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR bracketleft\nENCODING 91\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n40\n40\n40\n40\n70\n00\n00\nENDCHAR\nSTARTCHAR backslash\nENCODING 92\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n40\n20\n10\n08\n08\n00\n00\nENDCHAR\nSTARTCHAR bracketright\nENCODING 93\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n10\n10\n10\n10\n70\n00\n00\nENDCHAR\nSTARTCHAR asciicircum\nENCODING 94\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n50\n88\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR underscore\nENCODING 95\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n00\n00\nF8\nENDCHAR\nSTARTCHAR grave\nENCODING 96\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n10\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR a\nENCODING 97\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n38\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR b\nENCODING 98\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n40\n70\n48\n48\n70\n00\n00\nENDCHAR\nSTARTCHAR c\nENCODING 99\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n38\n40\n40\n38\n00\n00\nENDCHAR\nSTARTCHAR d\nENCODING 100\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n08\n08\n38\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR e\nENCODING 101\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n30\n58\n60\n38\n00\n00\nENDCHAR\nSTARTCHAR f\nENCODING 102\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n28\n20\n70\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR g\nENCODING 103\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n30\n48\n48\n38\n08\n30\nENDCHAR\nSTARTCHAR h\nENCODING 104\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n40\n70\n48\n48\n48\n00\n00\nENDCHAR\nSTARTCHAR i\nENCODING 105\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n00\n60\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR j\nENCODING 106\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n30\n10\n10\n10\n50\n20\nENDCHAR\nSTARTCHAR k\nENCODING 107\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n40\n50\n60\n50\n48\n00\n00\nENDCHAR\nSTARTCHAR l\nENCODING 108\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n60\n20\n20\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR m\nENCODING 109\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\nD0\nA8\nA8\n88\n00\n00\nENDCHAR\nSTARTCHAR n\nENCODING 110\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n70\n48\n48\n48\n00\n00\nENDCHAR\nSTARTCHAR o\nENCODING 111\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n30\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR p\nENCODING 112\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n70\n48\n48\n70\n40\n40\nENDCHAR\nSTARTCHAR q\nENCODING 113\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n38\n48\n48\n38\n08\n08\nENDCHAR\nSTARTCHAR r\nENCODING 114\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n50\n68\n40\n40\n00\n00\nENDCHAR\nSTARTCHAR s\nENCODING 115\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n38\n60\n18\n70\n00\n00\nENDCHAR\nSTARTCHAR t\nENCODING 116\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\n70\n20\n28\n10\n00\n00\nENDCHAR\nSTARTCHAR u\nENCODING 117\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n48\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR v\nENCODING 118\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n48\n48\n30\n30\n00\n00\nENDCHAR\nSTARTCHAR w\nENCODING 119\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n88\nA8\nA8\n50\n00\n00\nENDCHAR\nSTARTCHAR x\nENCODING 120\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n48\n30\n30\n48\n00\n00\nENDCHAR\nSTARTCHAR y\nENCODING 121\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n48\n48\n48\n38\n48\n30\nENDCHAR\nSTARTCHAR z\nENCODING 122\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n78\n10\n20\n78\n00\n00\nENDCHAR\nSTARTCHAR braceleft\nENCODING 123\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n20\n40\n20\n20\n10\n00\n00\nENDCHAR\nSTARTCHAR bar\nENCODING 124\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\n20\n20\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR braceright\nENCODING 125\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n40\n20\n20\n10\n20\n20\n40\n00\n00\nENDCHAR\nSTARTCHAR asciitilde\nENCODING 126\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n28\n50\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR space\nENCODING 160\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR exclamdown\nENCODING 161\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n00\n20\n20\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR cent\nENCODING 162\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n10\n38\n50\n50\n38\n10\n00\nENDCHAR\nSTARTCHAR sterling\nENCODING 163\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n48\n40\nF0\n40\n40\nF8\n00\nENDCHAR\nSTARTCHAR currency\nENCODING 164\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\nA8\n50\n88\n50\nA8\n00\n00\nENDCHAR\nSTARTCHAR yen\nENCODING 165\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n88\n50\nF8\n20\nF8\n20\n00\n00\nENDCHAR\nSTARTCHAR brokenbar\nENCODING 166\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\n20\n00\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR section\nENCODING 167\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n38\n40\n30\n48\n30\n08\n70\n00\nENDCHAR\nSTARTCHAR dieresis\nENCODING 168\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR copyright\nENCODING 169\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n78\n84\n94\nA4\n94\n84\n78\n00\n00\nENDCHAR\nSTARTCHAR ordfeminine\nENCODING 170\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n50\n30\n00\n70\n00\n00\n00\nENDCHAR\nSTARTCHAR guillemotleft\nENCODING 171\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n28\n50\nA0\n50\n28\n00\n00\nENDCHAR\nSTARTCHAR logicalnot\nENCODING 172\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n78\n08\n08\n00\n00\nENDCHAR\nSTARTCHAR hyphen\nENCODING 173\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n78\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR registered\nENCODING 174\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n78\n84\nB4\nA4\nA4\n84\n78\n00\n00\nENDCHAR\nSTARTCHAR macron\nENCODING 175\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR degree\nENCODING 176\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n30\n48\n30\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR plusminus\nENCODING 177\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\nF8\n20\n20\n00\nF8\n00\nENDCHAR\nSTARTCHAR twosuperior\nENCODING 178\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n50\n10\n20\n70\n00\n00\n00\nENDCHAR\nSTARTCHAR threesuperior\nENCODING 179\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n60\n10\n20\n10\n60\n00\n00\n00\nENDCHAR\nSTARTCHAR acute\nENCODING 180\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n20\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR mu\nENCODING 181\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n48\n48\n58\n68\n40\n00\nENDCHAR\nSTARTCHAR paragraph\nENCODING 182\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\nE8\nE8\n68\n28\n28\n00\n00\nENDCHAR\nSTARTCHAR periodcentered\nENCODING 183\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n20\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR cedilla\nENCODING 184\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n00\n10\n20\nENDCHAR\nSTARTCHAR onesuperior\nENCODING 185\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n60\n20\n20\n70\n00\n00\n00\nENDCHAR\nSTARTCHAR ordmasculine\nENCODING 186\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n50\n20\n00\n70\n00\n00\n00\nENDCHAR\nSTARTCHAR guillemotright\nENCODING 187\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\nA0\n50\n28\n50\nA0\n00\n00\nENDCHAR\nSTARTCHAR onequarter\nENCODING 188\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n40\nC0\n40\n50\n70\n30\n78\n10\n00\nENDCHAR\nSTARTCHAR onehalf\nENCODING 189\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n40\nC0\n40\n50\n68\n08\n10\n38\n00\nENDCHAR\nSTARTCHAR threequarters\nENCODING 190\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nC0\n20\n40\n30\nF0\n30\n78\n10\n00\nENDCHAR\nSTARTCHAR questiondown\nENCODING 191\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n00\n10\n30\n40\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR Agrave\nENCODING 192\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n40\n20\n20\n50\n70\n88\n88\n00\n00\nENDCHAR\nSTARTCHAR Aacute\nENCODING 193\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n20\n50\n70\n88\n88\n00\n00\nENDCHAR\nSTARTCHAR Acircumflex\nENCODING 194\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n50\n20\n50\n70\n88\n88\n00\n00\nENDCHAR\nSTARTCHAR Atilde\nENCODING 195\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n50\n20\n50\n70\n88\n88\n00\n00\nENDCHAR\nSTARTCHAR Adieresis\nENCODING 196\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n50\n00\n20\n50\n70\n88\n88\n00\n00\nENDCHAR\nSTARTCHAR Aring\nENCODING 197\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n50\n20\n50\n70\n88\n88\n00\n00\nENDCHAR\nSTARTCHAR AE\nENCODING 198\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\nA0\nF0\nA0\nA0\nB8\n00\n00\nENDCHAR\nSTARTCHAR Ccedilla\nENCODING 199\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n48\n40\n40\n48\n30\n10\n20\nENDCHAR\nSTARTCHAR Egrave\nENCODING 200\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n10\n78\n40\n70\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR Eacute\nENCODING 201\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n78\n40\n70\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR Ecircumflex\nENCODING 202\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n28\n78\n40\n70\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR Edieresis\nENCODING 203\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n00\n78\n40\n70\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR Igrave\nENCODING 204\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n40\n20\n70\n20\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR Iacute\nENCODING 205\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n70\n20\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR Icircumflex\nENCODING 206\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n50\n70\n20\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR Idieresis\nENCODING 207\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n50\n00\n70\n20\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR Eth\nENCODING 208\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n48\nE8\n48\n48\n70\n00\n00\nENDCHAR\nSTARTCHAR Ntilde\nENCODING 209\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n50\n48\n68\n58\n48\n48\n00\n00\nENDCHAR\nSTARTCHAR Ograve\nENCODING 210\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n10\n30\n48\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR Oacute\nENCODING 211\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n30\n48\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR Ocircumflex\nENCODING 212\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n28\n30\n48\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR Otilde\nENCODING 213\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n50\n30\n48\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR Odieresis\nENCODING 214\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n00\n30\n48\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR multiply\nENCODING 215\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n88\n50\n20\n50\n88\n00\n00\nENDCHAR\nSTARTCHAR Oslash\nENCODING 216\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n08\n38\n58\n58\n68\n68\n70\n40\n00\nENDCHAR\nSTARTCHAR Ugrave\nENCODING 217\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n10\n48\n48\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR Uacute\nENCODING 218\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n48\n48\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR Ucircumflex\nENCODING 219\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n28\n48\n48\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR Udieresis\nENCODING 220\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n00\n48\n48\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR Yacute\nENCODING 221\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n88\n50\n20\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR Thorn\nENCODING 222\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n70\n48\n48\n70\n40\n00\n00\nENDCHAR\nSTARTCHAR germandbls\nENCODING 223\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n48\n50\n50\n48\n50\n00\n00\nENDCHAR\nSTARTCHAR agrave\nENCODING 224\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n10\n00\n38\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR aacute\nENCODING 225\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n00\n38\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR acircumflex\nENCODING 226\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n28\n00\n38\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR atilde\nENCODING 227\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n50\n00\n38\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR adieresis\nENCODING 228\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n28\n00\n38\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR aring\nENCODING 229\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n28\n10\n38\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR ae\nENCODING 230\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n70\nA8\nB0\n78\n00\n00\nENDCHAR\nSTARTCHAR ccedilla\nENCODING 231\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n38\n40\n40\n38\n10\n20\nENDCHAR\nSTARTCHAR egrave\nENCODING 232\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n10\n00\n30\n58\n60\n38\n00\n00\nENDCHAR\nSTARTCHAR eacute\nENCODING 233\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n00\n30\n58\n60\n38\n00\n00\nENDCHAR\nSTARTCHAR ecircumflex\nENCODING 234\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n28\n00\n30\n58\n60\n38\n00\n00\nENDCHAR\nSTARTCHAR edieresis\nENCODING 235\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n28\n00\n30\n58\n60\n38\n00\n00\nENDCHAR\nSTARTCHAR igrave\nENCODING 236\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n40\n20\n00\n60\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR iacute\nENCODING 237\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n00\n60\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR icircumflex\nENCODING 238\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n50\n00\n60\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR idieresis\nENCODING 239\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n60\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR eth\nENCODING 240\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n18\n30\n08\n38\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR ntilde\nENCODING 241\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n50\n00\n70\n48\n48\n48\n00\n00\nENDCHAR\nSTARTCHAR ograve\nENCODING 242\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n10\n00\n30\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR oacute\nENCODING 243\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n00\n30\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR ocircumflex\nENCODING 244\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n28\n00\n30\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR otilde\nENCODING 245\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n50\n00\n30\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR odieresis\nENCODING 246\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n28\n00\n30\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR divide\nENCODING 247\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n20\n00\nF8\n00\n20\n00\n00\nENDCHAR\nSTARTCHAR oslash\nENCODING 248\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n38\n58\n68\n70\n00\n00\nENDCHAR\nSTARTCHAR ugrave\nENCODING 249\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n10\n00\n48\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR uacute\nENCODING 250\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n00\n48\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR ucircumflex\nENCODING 251\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n28\n00\n48\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR udieresis\nENCODING 252\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n28\n00\n48\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR yacute\nENCODING 253\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n00\n48\n48\n48\n38\n48\n30\nENDCHAR\nSTARTCHAR thorn\nENCODING 254\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n40\n70\n48\n48\n70\n40\n40\nENDCHAR\nSTARTCHAR ydieresis\nENCODING 255\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n28\n00\n48\n48\n48\n38\n48\n30\nENDCHAR\nSTARTCHAR Amacron\nENCODING 256\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n70\n00\n20\n50\n70\n88\n88\n00\n00\nENDCHAR\nSTARTCHAR amacron\nENCODING 257\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n38\n00\n38\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR Abreve\nENCODING 258\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n90\n60\n20\n50\n70\n88\n88\n00\n00\nENDCHAR\nSTARTCHAR abreve\nENCODING 259\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n48\n30\n00\n38\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR Aogonek\nENCODING 260\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n50\n88\nF8\n88\n88\n10\n08\nENDCHAR\nSTARTCHAR aogonek\nENCODING 261\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n38\n48\n48\n38\n10\n08\nENDCHAR\nSTARTCHAR Cacute\nENCODING 262\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n30\n48\n40\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR cacute\nENCODING 263\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n00\n38\n40\n40\n38\n00\n00\nENDCHAR\nSTARTCHAR Ccircumflex\nENCODING 264\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n28\n30\n48\n40\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR ccircumflex\nENCODING 265\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n28\n00\n38\n40\n40\n38\n00\n00\nENDCHAR\nSTARTCHAR Cdotaccent\nENCODING 266\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n00\n30\n48\n40\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR cdotaccent\nENCODING 267\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n38\n40\n40\n38\n00\n00\nENDCHAR\nSTARTCHAR Ccaron\nENCODING 268\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n10\n30\n48\n40\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR ccaron\nENCODING 269\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n10\n00\n38\n40\n40\n38\n00\n00\nENDCHAR\nSTARTCHAR Dcaron\nENCODING 270\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n10\n70\n48\n48\n48\n70\n00\n00\nENDCHAR\nSTARTCHAR dcaron\nENCODING 271\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n50\n28\n08\n38\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR Dcroat\nENCODING 272\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n48\nE8\n48\n48\n70\n00\n00\nENDCHAR\nSTARTCHAR dcroat\nENCODING 273\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n38\n70\n90\n90\n70\n00\n00\nENDCHAR\nSTARTCHAR Emacron\nENCODING 274\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n78\n00\n78\n40\n70\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR emacron\nENCODING 275\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n00\n30\n58\n60\n38\n00\n00\nENDCHAR\nSTARTCHAR Ebreve\nENCODING 276\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n48\n30\n78\n40\n70\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR ebreve\nENCODING 277\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n48\n30\n00\n30\n58\n60\n38\n00\n00\nENDCHAR\nSTARTCHAR Edotaccent\nENCODING 278\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n00\n78\n40\n70\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR edotaccent\nENCODING 279\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n00\n30\n58\n60\n38\n00\n00\nENDCHAR\nSTARTCHAR Eogonek\nENCODING 280\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n40\n70\n40\n40\n78\n20\n10\nENDCHAR\nSTARTCHAR eogonek\nENCODING 281\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n30\n58\n60\n38\n20\n10\nENDCHAR\nSTARTCHAR Ecaron\nENCODING 282\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n10\n78\n40\n70\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR ecaron\nENCODING 283\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n10\n00\n30\n58\n60\n38\n00\n00\nENDCHAR\nSTARTCHAR Gcircumflex\nENCODING 284\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n28\n38\n40\n58\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR gcircumflex\nENCODING 285\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n28\n00\n30\n48\n48\n38\n08\n30\nENDCHAR\nSTARTCHAR Gbreve\nENCODING 286\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n48\n30\n38\n40\n58\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR gbreve\nENCODING 287\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n48\n30\n00\n30\n48\n48\n38\n08\n30\nENDCHAR\nSTARTCHAR Gdotaccent\nENCODING 288\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n00\n38\n40\n58\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR gdotaccent\nENCODING 289\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n30\n48\n48\n38\n08\n30\nENDCHAR\nSTARTCHAR Gcommaaccent\nENCODING 290\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n48\n40\n58\n48\n30\n10\n20\nENDCHAR\nSTARTCHAR gcommaaccent\nENCODING 291\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n20\n30\n48\n48\n38\n08\n30\nENDCHAR\nSTARTCHAR Hcircumflex\nENCODING 292\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n28\n00\n48\n78\n48\n48\n00\n00\nENDCHAR\nSTARTCHAR hcircumflex\nENCODING 293\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\nA8\n80\nE0\n90\n90\n90\n00\n00\nENDCHAR\nSTARTCHAR Hbar\nENCODING 294\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\nF8\n50\n70\n50\n50\n00\n00\nENDCHAR\nSTARTCHAR hbar\nENCODING 295\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\nE0\n70\n48\n48\n48\n00\n00\nENDCHAR\nSTARTCHAR Itilde\nENCODING 296\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n50\n38\n10\n10\n10\n38\n00\n00\nENDCHAR\nSTARTCHAR itilde\nENCODING 297\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n50\n00\n30\n10\n10\n38\n00\n00\nENDCHAR\nSTARTCHAR Imacron\nENCODING 298\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n70\n00\n70\n20\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR imacron\nENCODING 299\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n00\n60\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR Ibreve\nENCODING 300\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n48\n30\n00\n38\n10\n10\n38\n00\n00\nENDCHAR\nSTARTCHAR ibreve\nENCODING 301\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n48\n30\n00\n30\n10\n10\n38\n00\n00\nENDCHAR\nSTARTCHAR Iogonek\nENCODING 302\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n20\n20\n20\n20\n70\n20\n10\nENDCHAR\nSTARTCHAR iogonek\nENCODING 303\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n00\n60\n20\n20\n70\n20\n10\nENDCHAR\nSTARTCHAR Idotaccent\nENCODING 304\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n00\n70\n20\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR dotlessi\nENCODING 305\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n60\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR IJ\nENCODING 306\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nB8\n88\n88\n88\nA8\n90\n00\n00\nENDCHAR\nSTARTCHAR ij\nENCODING 307\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n88\n00\n98\n88\n88\n88\n28\n10\nENDCHAR\nSTARTCHAR Jcircumflex\nENCODING 308\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n28\n38\n10\n10\n90\n60\n00\n00\nENDCHAR\nSTARTCHAR jcircumflex\nENCODING 309\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n28\n00\n30\n10\n10\n10\n50\n20\nENDCHAR\nSTARTCHAR Kcommaaccent\nENCODING 310\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n48\n50\n60\n50\n48\n48\n20\n40\nENDCHAR\nSTARTCHAR kcommaaccent\nENCODING 311\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n40\n50\n60\n50\n48\n20\n40\nENDCHAR\nSTARTCHAR kgreenlandic\nENCODING 312\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n58\n60\n50\n48\n00\n00\nENDCHAR\nSTARTCHAR Lacute\nENCODING 313\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n08\n10\n40\n40\n40\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR lacute\nENCODING 314\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n40\n60\n20\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR Lcommaaccent\nENCODING 315\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n40\n40\n40\n40\n78\n10\n20\nENDCHAR\nSTARTCHAR lcommaaccent\nENCODING 316\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n60\n20\n20\n20\n20\n70\n20\n40\nENDCHAR\nSTARTCHAR Lcaron\nENCODING 317\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n10\n40\n40\n40\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR lcaron\nENCODING 318\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n50\n20\n60\n20\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR Ldot\nENCODING 319\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n40\n50\n40\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR ldot\nENCODING 320\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n60\n20\n28\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR Lslash\nENCODING 321\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n40\n60\nC0\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR lslash\nENCODING 322\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n60\n20\n30\n60\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR Nacute\nENCODING 323\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n48\n68\n58\n48\n48\n00\n00\nENDCHAR\nSTARTCHAR nacute\nENCODING 324\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n00\n70\n48\n48\n48\n00\n00\nENDCHAR\nSTARTCHAR Ncommaaccent\nENCODING 325\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n48\n68\n58\n48\n48\n48\n20\n40\nENDCHAR\nSTARTCHAR ncommaaccent\nENCODING 326\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n70\n48\n48\n48\n20\n40\nENDCHAR\nSTARTCHAR Ncaron\nENCODING 327\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n10\n48\n68\n58\n48\n48\n00\n00\nENDCHAR\nSTARTCHAR ncaron\nENCODING 328\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n50\n20\n00\n70\n48\n48\n48\n00\n00\nENDCHAR\nSTARTCHAR napostrophe\nENCODING 329\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nC0\n40\nB0\n28\n28\n28\n00\n00\nENDCHAR\nSTARTCHAR Eng\nENCODING 330\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n48\n68\n58\n48\n48\n48\n08\n10\nENDCHAR\nSTARTCHAR eng\nENCODING 331\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n70\n48\n48\n48\n08\n10\nENDCHAR\nSTARTCHAR Omacron\nENCODING 332\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nF8\n00\n70\n88\n88\n88\n70\n00\n00\nENDCHAR\nSTARTCHAR omacron\nENCODING 333\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n00\n30\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR Obreve\nENCODING 334\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n88\n70\n70\n88\n88\n88\n70\n00\n00\nENDCHAR\nSTARTCHAR obreve\nENCODING 335\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n48\n30\n00\n30\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR Ohungarumlaut\nENCODING 336\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n48\n90\n70\n88\n88\n88\n70\n00\n00\nENDCHAR\nSTARTCHAR ohungarumlaut\nENCODING 337\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n48\n90\n00\n60\n90\n90\n60\n00\n00\nENDCHAR\nSTARTCHAR OE\nENCODING 338\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\nA0\nB0\nA0\nA0\n78\n00\n00\nENDCHAR\nSTARTCHAR oe\nENCODING 339\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n50\nA8\nB0\n58\n00\n00\nENDCHAR\nSTARTCHAR Racute\nENCODING 340\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n70\n48\n70\n50\n48\n00\n00\nENDCHAR\nSTARTCHAR racute\nENCODING 341\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n00\n50\n68\n40\n40\n00\n00\nENDCHAR\nSTARTCHAR Rcommaaccent\nENCODING 342\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n48\n48\n70\n48\n48\n20\n40\nENDCHAR\nSTARTCHAR rcommaaccent\nENCODING 343\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n50\n68\n40\n40\n20\n40\nENDCHAR\nSTARTCHAR Rcaron\nENCODING 344\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n50\n20\n70\n48\n70\n50\n48\n00\n00\nENDCHAR\nSTARTCHAR rcaron\nENCODING 345\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n50\n20\n00\n50\n68\n40\n40\n00\n00\nENDCHAR\nSTARTCHAR Sacute\nENCODING 346\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n38\n40\n30\n08\n70\n00\n00\nENDCHAR\nSTARTCHAR sacute\nENCODING 347\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n00\n38\n60\n18\n70\n00\n00\nENDCHAR\nSTARTCHAR Scircumflex\nENCODING 348\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n28\n38\n40\n30\n08\n70\n00\n00\nENDCHAR\nSTARTCHAR scircumflex\nENCODING 349\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n28\n00\n38\n60\n18\n70\n00\n00\nENDCHAR\nSTARTCHAR Scedilla\nENCODING 350\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n48\n20\n10\n48\n30\n10\n20\nENDCHAR\nSTARTCHAR scedilla\nENCODING 351\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n38\n60\n18\n70\n10\n20\nENDCHAR\nSTARTCHAR Scaron\nENCODING 352\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n10\n38\n40\n30\n08\n70\n00\n00\nENDCHAR\nSTARTCHAR scaron\nENCODING 353\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n10\n00\n38\n60\n18\n70\n00\n00\nENDCHAR\nSTARTCHAR Tcommaaccent\nENCODING 354\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nF8\n20\n20\n20\n20\n20\n10\n20\nENDCHAR\nSTARTCHAR tcommaaccent\nENCODING 355\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\n70\n20\n28\n10\n10\n20\nENDCHAR\nSTARTCHAR Tcaron\nENCODING 356\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n50\n20\nF8\n20\n20\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR tcaron\nENCODING 357\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n10\n20\n70\n20\n28\n10\n00\n00\nENDCHAR\nSTARTCHAR Tbar\nENCODING 358\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nF8\n20\n20\n70\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR tbar\nENCODING 359\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\n70\n70\n28\n10\n00\n00\nENDCHAR\nSTARTCHAR Utilde\nENCODING 360\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n50\n00\n48\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR utilde\nENCODING 361\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n50\n00\n48\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR Umacron\nENCODING 362\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n78\n00\n48\n48\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR umacron\nENCODING 363\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n00\n48\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR Ubreve\nENCODING 364\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n48\n30\n00\n48\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR ubreve\nENCODING 365\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n48\n30\n00\n48\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR Uring\nENCODING 366\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n30\n48\n30\n48\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR uring\nENCODING 367\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n30\n48\n30\n48\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR Uhungarumlaut\nENCODING 368\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n48\n90\n00\n90\n90\n90\n60\n00\n00\nENDCHAR\nSTARTCHAR uhungarumlaut\nENCODING 369\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n48\n90\n00\n90\n90\n90\n70\n00\n00\nENDCHAR\nSTARTCHAR Uogonek\nENCODING 370\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n48\n48\n48\n48\n48\n30\n20\n10\nENDCHAR\nSTARTCHAR uogonek\nENCODING 371\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n48\n48\n48\n38\n20\n10\nENDCHAR\nSTARTCHAR Wcircumflex\nENCODING 372\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n50\n00\n88\nA8\nD8\n88\n00\n00\nENDCHAR\nSTARTCHAR wcircumflex\nENCODING 373\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n50\n00\n88\nA8\nA8\n50\n00\n00\nENDCHAR\nSTARTCHAR Ycircumflex\nENCODING 374\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n50\n00\n88\n50\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR ycircumflex\nENCODING 375\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n28\n00\n48\n48\n48\n38\n48\n30\nENDCHAR\nSTARTCHAR Ydieresis\nENCODING 376\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n50\n00\n88\n50\n20\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR Zacute\nENCODING 377\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n78\n10\n20\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR zacute\nENCODING 378\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n00\n78\n10\n20\n78\n00\n00\nENDCHAR\nSTARTCHAR Zdotaccent\nENCODING 379\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n00\n78\n10\n20\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR zdotaccent\nENCODING 380\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n78\n10\n20\n78\n00\n00\nENDCHAR\nSTARTCHAR Zcaron\nENCODING 381\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n10\n78\n10\n20\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR zcaron\nENCODING 382\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n10\n00\n78\n10\n20\n78\n00\n00\nENDCHAR\nSTARTCHAR longs\nENCODING 383\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n28\n60\n20\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR uni018F\nENCODING 399\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n48\n08\n78\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR florin\nENCODING 402\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n28\n20\n70\n20\n20\n20\n40\nENDCHAR\nSTARTCHAR Ohorn\nENCODING 416\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n64\n94\n98\n90\n90\n60\n00\n00\nENDCHAR\nSTARTCHAR ohorn\nENCODING 417\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n34\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR Uhorn\nENCODING 431\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n54\n54\n58\n50\n50\n20\n00\n00\nENDCHAR\nSTARTCHAR uhorn\nENCODING 432\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n54\n58\n50\n30\n00\n00\nENDCHAR\nSTARTCHAR uni01B5\nENCODING 437\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n08\n78\n20\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR uni01B6\nENCODING 438\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n78\n78\n20\n78\n00\n00\nENDCHAR\nSTARTCHAR uni01D1\nENCODING 465\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n10\n30\n48\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR uni01D2\nENCODING 466\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n10\n00\n30\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR Gcaron\nENCODING 486\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n10\n38\n40\n58\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR gcaron\nENCODING 487\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n10\n00\n30\n48\n48\n38\n08\n30\nENDCHAR\nSTARTCHAR Aringacute\nENCODING 506\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n50\n20\n50\n70\n50\n00\n00\nENDCHAR\nSTARTCHAR aringacute\nENCODING 507\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n08\n10\n28\n38\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR AEacute\nENCODING 508\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n78\nA0\nF0\nA0\nB8\n00\n00\nENDCHAR\nSTARTCHAR aeacute\nENCODING 509\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n00\n70\nA8\nB0\n78\n00\n00\nENDCHAR\nSTARTCHAR Oslashacute\nENCODING 510\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n08\n10\n38\n58\n68\n68\n70\n00\n00\nENDCHAR\nSTARTCHAR oslashacute\nENCODING 511\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n00\n38\n58\n68\n70\n00\n00\nENDCHAR\nSTARTCHAR Scommaaccent\nENCODING 536\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n48\n20\n10\n48\n30\n10\n20\nENDCHAR\nSTARTCHAR scommaaccent\nENCODING 537\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n38\n60\n18\n70\n10\n20\nENDCHAR\nSTARTCHAR Tcommaaccent\nENCODING 538\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nF8\n20\n20\n20\n20\n20\n10\n20\nENDCHAR\nSTARTCHAR tcommaaccent\nENCODING 539\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\n70\n20\n28\n10\n10\n20\nENDCHAR\nSTARTCHAR uni0258\nENCODING 600\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n30\n68\n18\n70\n00\n00\nENDCHAR\nSTARTCHAR uni0259\nENCODING 601\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n70\n18\n68\n30\n00\n00\nENDCHAR\nSTARTCHAR uni02BB\nENCODING 699\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n20\n30\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR afii57929\nENCODING 700\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n10\n20\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR afii64937\nENCODING 701\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n20\n10\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR circumflex\nENCODING 710\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n50\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR caron\nENCODING 711\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n50\n20\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR macron\nENCODING 713\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR breve\nENCODING 728\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n48\n30\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR dotaccent\nENCODING 729\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR ring\nENCODING 730\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n50\n20\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR ogonek\nENCODING 731\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n00\n20\n10\nENDCHAR\nSTARTCHAR tilde\nENCODING 732\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n50\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR hungarumlaut\nENCODING 733\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n48\n90\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR gravecomb\nENCODING 768\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n40\n20\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR acutecomb\nENCODING 769\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0302\nENCODING 770\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n50\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR tildecomb\nENCODING 771\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n50\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0304\nENCODING 772\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n70\n00\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0305\nENCODING 773\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nF8\n00\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0306\nENCODING 774\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n88\n70\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0307\nENCODING 775\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n00\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0308\nENCODING 776\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n50\n00\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR hookabovecomb\nENCODING 777\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n60\n10\n20\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni030A\nENCODING 778\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n50\n20\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni030B\nENCODING 779\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n48\n90\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni030C\nENCODING 780\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n50\n20\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni030D\nENCODING 781\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n20\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni030E\nENCODING 782\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n50\n50\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni030F\nENCODING 783\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n90\n48\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0310\nENCODING 784\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nA8\n70\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0311\nENCODING 785\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n70\n88\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0312\nENCODING 786\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n30\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0313\nENCODING 787\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n30\n10\n20\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0314\nENCODING 788\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n30\n20\n10\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR dotbelowcomb\nENCODING 803\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n00\n00\n20\nENDCHAR\nSTARTCHAR uni0324\nENCODING 804\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n00\n00\n50\nENDCHAR\nSTARTCHAR uni0374\nENCODING 884\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni0375\nENCODING 885\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n00\n10\n20\nENDCHAR\nSTARTCHAR uni037A\nENCODING 890\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n00\n20\n30\nENDCHAR\nSTARTCHAR uni037E\nENCODING 894\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n30\n30\n00\n30\n10\n10\n20\nENDCHAR\nSTARTCHAR tonos\nENCODING 900\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n20\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR dieresistonos\nENCODING 901\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\nA8\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR Alphatonos\nENCODING 902\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n80\nB0\n48\n48\n78\n48\n48\n00\n00\nENDCHAR\nSTARTCHAR anoteleia\nENCODING 903\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n20\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR Epsilontonos\nENCODING 904\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n80\nB8\n20\n30\n20\n20\n38\n00\n00\nENDCHAR\nSTARTCHAR Etatonos\nENCODING 905\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n80\nA8\n28\n38\n28\n28\n28\n00\n00\nENDCHAR\nSTARTCHAR Iotatonos\nENCODING 906\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n80\nB8\n10\n10\n10\n10\n38\n00\n00\nENDCHAR\nSTARTCHAR Omicrontonos\nENCODING 908\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n80\nB0\n48\n48\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR Upsilontonos\nENCODING 910\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n80\nA8\n28\n28\n10\n10\n10\n00\n00\nENDCHAR\nSTARTCHAR Omegatonos\nENCODING 911\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n80\nB0\n48\n48\n48\n30\n78\n00\n00\nENDCHAR\nSTARTCHAR iotadieresistonos\nENCODING 912\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\nA8\n00\n20\n20\n20\n10\n00\n00\nENDCHAR\nSTARTCHAR Alpha\nENCODING 913\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n50\n88\nF8\n88\n88\n00\n00\nENDCHAR\nSTARTCHAR Beta\nENCODING 914\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nF0\n88\nF0\n88\n88\nF0\n00\n00\nENDCHAR\nSTARTCHAR Gamma\nENCODING 915\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n40\n40\n40\n40\n40\n00\n00\nENDCHAR\nSTARTCHAR Delta\nENCODING 916\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\n50\n50\n88\nF8\n00\n00\nENDCHAR\nSTARTCHAR Epsilon\nENCODING 917\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n40\n70\n40\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR Zeta\nENCODING 918\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n08\n10\n20\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR Eta\nENCODING 919\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n48\n48\n78\n48\n48\n48\n00\n00\nENDCHAR\nSTARTCHAR Theta\nENCODING 920\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n88\nF8\n88\n88\n70\n00\n00\nENDCHAR\nSTARTCHAR Iota\nENCODING 921\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n20\n20\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR Kappa\nENCODING 922\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n48\n50\n60\n50\n48\n48\n00\n00\nENDCHAR\nSTARTCHAR Lambda\nENCODING 923\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\n50\n50\n88\n88\n00\n00\nENDCHAR\nSTARTCHAR Mu\nENCODING 924\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n88\nD8\nA8\nA8\n88\n88\n00\n00\nENDCHAR\nSTARTCHAR Nu\nENCODING 925\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n48\n68\n58\n48\n48\n48\n00\n00\nENDCHAR\nSTARTCHAR Xi\nENCODING 926\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n00\n30\n00\n00\n78\n00\n00\nENDCHAR\nSTARTCHAR Omicron\nENCODING 927\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n88\n88\n88\n88\n70\n00\n00\nENDCHAR\nSTARTCHAR Pi\nENCODING 928\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n48\n48\n48\n48\n48\n00\n00\nENDCHAR\nSTARTCHAR Rho\nENCODING 929\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n48\n48\n70\n40\n40\n00\n00\nENDCHAR\nSTARTCHAR Sigma\nENCODING 931\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n40\n20\n20\n40\n78\n00\n00\nENDCHAR\nSTARTCHAR Tau\nENCODING 932\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nF8\n20\n20\n20\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR Upsilon\nENCODING 933\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n88\n88\n50\n20\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR Phi\nENCODING 934\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n70\nA8\nA8\n70\n20\n00\n00\nENDCHAR\nSTARTCHAR Chi\nENCODING 935\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n88\n50\n20\n20\n50\n88\n00\n00\nENDCHAR\nSTARTCHAR Psi\nENCODING 936\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nA8\nA8\nA8\n70\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR Omega\nENCODING 937\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n88\n88\n88\n50\nD8\n00\n00\nENDCHAR\nSTARTCHAR Iotadieresis\nENCODING 938\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n50\n00\n70\n20\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR Upsilondieresis\nENCODING 939\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n50\n00\n88\n50\n20\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR alphatonos\nENCODING 940\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n08\n10\n00\n38\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR epsilontonos\nENCODING 941\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n08\n10\n00\n30\n58\n60\n38\n00\n00\nENDCHAR\nSTARTCHAR etatonos\nENCODING 942\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n00\nB0\nC8\n88\n88\n08\n08\nENDCHAR\nSTARTCHAR iotatonos\nENCODING 943\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n40\n00\n40\n40\n50\n20\n00\n00\nENDCHAR\nSTARTCHAR upsilondieresistonos\nENCODING 944\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\nA8\n00\n88\n88\n88\n70\n00\n00\nENDCHAR\nSTARTCHAR alpha\nENCODING 945\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n38\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR beta\nENCODING 946\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n48\n70\n48\n48\n70\n40\n40\nENDCHAR\nSTARTCHAR gamma\nENCODING 947\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n88\n88\n50\n50\n20\n20\nENDCHAR\nSTARTCHAR delta\nENCODING 948\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n80\n70\n88\n88\n70\n00\n00\nENDCHAR\nSTARTCHAR epsilon\nENCODING 949\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n30\n58\n60\n38\n00\n00\nENDCHAR\nSTARTCHAR zeta\nENCODING 950\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nF8\n20\n40\n40\n30\n08\n30\n00\nENDCHAR\nSTARTCHAR eta\nENCODING 951\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\nB0\nC8\n88\n88\n08\n08\nENDCHAR\nSTARTCHAR theta\nENCODING 952\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n48\n78\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR iota\nENCODING 953\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n40\n40\n50\n20\n00\n00\nENDCHAR\nSTARTCHAR kappa\nENCODING 954\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n48\n50\n60\n58\n00\n00\nENDCHAR\nSTARTCHAR lambda\nENCODING 955\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n88\n08\n68\n98\n88\n00\n00\nENDCHAR\nSTARTCHAR mu\nENCODING 956\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n88\n88\n98\nE8\n80\n80\nENDCHAR\nSTARTCHAR nu\nENCODING 957\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n88\n88\n50\n20\n00\n00\nENDCHAR\nSTARTCHAR xi\nENCODING 958\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nF8\n20\n40\n70\n80\n70\n08\n10\nENDCHAR\nSTARTCHAR omicron\nENCODING 959\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n30\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR pi\nENCODING 960\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\nF8\n50\n50\n50\n00\n00\nENDCHAR\nSTARTCHAR rho\nENCODING 961\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n70\n88\n88\nF0\n80\n80\nENDCHAR\nSTARTCHAR sigma1\nENCODING 962\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n70\n88\n80\n70\n08\n30\nENDCHAR\nSTARTCHAR sigma\nENCODING 963\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n78\n90\n88\n70\n00\n00\nENDCHAR\nSTARTCHAR tau\nENCODING 964\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n78\n20\n28\n10\n00\n00\nENDCHAR\nSTARTCHAR upsilon\nENCODING 965\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n88\n88\n88\n70\n00\n00\nENDCHAR\nSTARTCHAR phi\nENCODING 966\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n90\nA8\nA8\n70\n20\n20\nENDCHAR\nSTARTCHAR chi\nENCODING 967\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n88\n50\n20\n50\n88\n88\nENDCHAR\nSTARTCHAR psi\nENCODING 968\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\nA8\nA8\nA8\n70\n20\n20\nENDCHAR\nSTARTCHAR omega\nENCODING 969\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n50\n88\nA8\n50\n00\n00\nENDCHAR\nSTARTCHAR iotadieresis\nENCODING 970\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n20\n20\n28\n10\n00\n00\nENDCHAR\nSTARTCHAR upsilondieresis\nENCODING 971\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n88\n88\n88\n70\n00\n00\nENDCHAR\nSTARTCHAR omicrontonos\nENCODING 972\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n00\n70\n88\n88\n70\n00\n00\nENDCHAR\nSTARTCHAR upsilontonos\nENCODING 973\nSWIDTH 640 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982\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\nF8\n88\nA8\n50\n00\n00\nENDCHAR\nSTARTCHAR uni03D7\nENCODING 983\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n00\n88\n48\n70\n88\n08\n30\nENDCHAR\nSTARTCHAR uni03DA\nENCODING 986\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n48\n80\n80\n80\n70\n08\n10\nENDCHAR\nSTARTCHAR uni03DB\nENCODING 987\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n08\n70\n80\n80\n70\n08\n30\nENDCHAR\nSTARTCHAR uni03DC\nENCODING 988\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nF8\n80\n80\nE0\n80\n80\n00\n00\nENDCHAR\nSTARTCHAR uni03DD\nENCODING 989\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n78\n40\n40\n70\n40\n40\nENDCHAR\nSTARTCHAR uni03DE\nENCODING 990\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n80\n88\n98\nA8\nC8\n08\n00\n00\nENDCHAR\nSTARTCHAR uni03DF\nENCODING 991\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n40\n80\nF8\n08\n10\n20\n20\nENDCHAR\nSTARTCHAR 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-2\nBITMAP\n20\n00\nF0\n88\nF0\n88\nF0\n00\n00\nENDCHAR\nSTARTCHAR uni1E03\nENCODING 7683\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n40\n40\n70\n48\n48\n70\n00\n00\nENDCHAR\nSTARTCHAR uni1E0A\nENCODING 7690\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n00\n70\n48\n48\n48\n70\n00\n00\nENDCHAR\nSTARTCHAR uni1E0B\nENCODING 7691\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n08\n08\n38\n48\n48\n38\n00\n00\nENDCHAR\nSTARTCHAR uni1E1E\nENCODING 7710\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n00\n78\n40\n70\n40\n40\n00\n00\nENDCHAR\nSTARTCHAR uni1E1F\nENCODING 7711\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n00\n10\n28\n70\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR uni1E40\nENCODING 7744\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n88\nD8\nA8\nA8\n88\n88\n00\n00\nENDCHAR\nSTARTCHAR uni1E41\nENCODING 7745\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n00\nD0\nA8\nA8\n88\n00\n00\nENDCHAR\nSTARTCHAR uni1E56\nENCODING 7766\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n00\n70\n48\n70\n40\n40\n00\n00\nENDCHAR\nSTARTCHAR uni1E57\nENCODING 7767\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n00\n70\n48\n48\n70\n40\n40\nENDCHAR\nSTARTCHAR uni1E60\nENCODING 7776\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n00\n38\n40\n30\n08\n70\n00\n00\nENDCHAR\nSTARTCHAR uni1E61\nENCODING 7777\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n38\n60\n18\n70\n00\n00\nENDCHAR\nSTARTCHAR uni1E6A\nENCODING 7786\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n00\nF8\n20\n20\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR uni1E6B\nENCODING 7787\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n00\n20\n70\n20\n28\n10\n00\n00\nENDCHAR\nSTARTCHAR Wgrave\nENCODING 7808\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n40\n20\n88\n88\nA8\nD8\n88\n00\n00\nENDCHAR\nSTARTCHAR wgrave\nENCODING 7809\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n40\n20\n00\n88\nA8\nA8\n50\n00\n00\nENDCHAR\nSTARTCHAR Wacute\nENCODING 7810\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n88\n88\nA8\nD8\n88\n00\n00\nENDCHAR\nSTARTCHAR wacute\nENCODING 7811\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n20\n00\n88\nA8\nA8\n50\n00\n00\nENDCHAR\nSTARTCHAR Wdieresis\nENCODING 7812\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n50\n00\n88\n88\nA8\nD8\n88\n00\n00\nENDCHAR\nSTARTCHAR wdieresis\nENCODING 7813\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n88\nA8\nA8\n50\n00\n00\nENDCHAR\nSTARTCHAR Ygrave\nENCODING 7922\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n40\n20\n88\n50\n20\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR ygrave\nENCODING 7923\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n10\n00\n48\n48\n48\n38\n48\n30\nENDCHAR\nSTARTCHAR uni2010\nENCODING 8208\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n78\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2011\nENCODING 8209\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n78\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR figuredash\nENCODING 8210\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\nF8\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR endash\nENCODING 8211\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\nF8\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR emdash\nENCODING 8212\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\nFC\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR afii00208\nENCODING 8213\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\nFC\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2016\nENCODING 8214\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n50\n50\n50\n50\n50\n00\n00\nENDCHAR\nSTARTCHAR underscoredbl\nENCODING 8215\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\nFC\n00\nFC\nENDCHAR\nSTARTCHAR quoteleft\nENCODING 8216\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n20\n30\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR quoteright\nENCODING 8217\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n10\n20\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR quotesinglbase\nENCODING 8218\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n30\n10\n20\nENDCHAR\nSTARTCHAR quotereversed\nENCODING 8219\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n20\n10\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR quotedblleft\nENCODING 8220\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n48\n90\nD8\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR quotedblright\nENCODING 8221\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nD8\n48\n90\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR quotedblbase\nENCODING 8222\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\nD8\n48\n90\nENDCHAR\nSTARTCHAR uni201F\nENCODING 8223\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nD8\n90\n48\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR dagger\nENCODING 8224\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\nF8\n20\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR daggerdbl\nENCODING 8225\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\nF8\n20\nF8\n20\n20\n00\nENDCHAR\nSTARTCHAR bullet\nENCODING 8226\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n30\n78\n78\n30\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2023\nENCODING 8227\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n40\n60\n70\n60\n40\n00\n00\nENDCHAR\nSTARTCHAR onedotenleader\nENCODING 8228\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n20\n00\n00\nENDCHAR\nSTARTCHAR twodotenleader\nENCODING 8229\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n50\n00\n00\nENDCHAR\nSTARTCHAR ellipsis\nENCODING 8230\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\nA8\n00\n00\nENDCHAR\nSTARTCHAR uni2027\nENCODING 8231\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n30\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR perthousand\nENCODING 8240\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n40\nA8\n48\n10\n20\n68\nD4\n28\n00\nENDCHAR\nSTARTCHAR minute\nENCODING 8242\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n10\n20\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR second\nENCODING 8243\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n48\n48\n90\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2034\nENCODING 8244\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n54\n54\nA8\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2035\nENCODING 8245\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\n10\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2036\nENCODING 8246\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n90\n90\n48\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2037\nENCODING 8247\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nA8\nA8\n54\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR guilsinglleft\nENCODING 8249\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n10\n20\n40\n20\n10\n00\n00\nENDCHAR\nSTARTCHAR guilsinglright\nENCODING 8250\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n40\n20\n10\n20\n40\n00\n00\nENDCHAR\nSTARTCHAR exclamdbl\nENCODING 8252\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n50\n50\n50\n00\n50\n00\n00\nENDCHAR\nSTARTCHAR uni203E\nENCODING 8254\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nFC\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR fraction\nENCODING 8260\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n08\n08\n10\n20\n40\n40\n00\n00\nENDCHAR\nSTARTCHAR zerosuperior\nENCODING 8304\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n50\n50\n50\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2071\nENCODING 8305\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n00\n60\n20\n70\n00\n00\n00\nENDCHAR\nSTARTCHAR foursuperior\nENCODING 8308\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n50\n70\n10\n10\n00\n00\n00\nENDCHAR\nSTARTCHAR fivesuperior\nENCODING 8309\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n40\n60\n10\n60\n00\n00\n00\nENDCHAR\nSTARTCHAR sixsuperior\nENCODING 8310\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n40\n60\n50\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR sevensuperior\nENCODING 8311\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n10\n20\n20\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR eightsuperior\nENCODING 8312\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n50\n20\n50\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR ninesuperior\nENCODING 8313\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n50\n30\n10\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR uni207A\nENCODING 8314\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n20\n70\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR uni207B\nENCODING 8315\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n70\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni207C\nENCODING 8316\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n70\n00\n70\n00\n00\n00\nENDCHAR\nSTARTCHAR parenleftsuperior\nENCODING 8317\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n40\n40\n40\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR parenrightsuperior\nENCODING 8318\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n10\n10\n10\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR nsuperior\nENCODING 8319\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n60\n50\n50\n50\n00\n00\n00\nENDCHAR\nSTARTCHAR zeroinferior\nENCODING 8320\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n20\n50\n50\n50\n20\nENDCHAR\nSTARTCHAR oneinferior\nENCODING 8321\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n20\n60\n20\n20\n70\nENDCHAR\nSTARTCHAR twoinferior\nENCODING 8322\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n20\n50\n10\n20\n70\nENDCHAR\nSTARTCHAR threeinferior\nENCODING 8323\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n60\n10\n20\n10\n60\nENDCHAR\nSTARTCHAR fourinferior\nENCODING 8324\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n50\n50\n70\n10\n10\nENDCHAR\nSTARTCHAR fiveinferior\nENCODING 8325\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n70\n40\n60\n10\n60\nENDCHAR\nSTARTCHAR sixinferior\nENCODING 8326\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n20\n40\n60\n50\n20\nENDCHAR\nSTARTCHAR seveninferior\nENCODING 8327\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n70\n10\n20\n20\n20\nENDCHAR\nSTARTCHAR eightinferior\nENCODING 8328\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n20\n50\n20\n50\n20\nENDCHAR\nSTARTCHAR nineinferior\nENCODING 8329\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n20\n50\n30\n10\n20\nENDCHAR\nSTARTCHAR uni208A\nENCODING 8330\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n20\n70\n20\nENDCHAR\nSTARTCHAR uni208B\nENCODING 8331\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n00\n70\n00\nENDCHAR\nSTARTCHAR uni208C\nENCODING 8332\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n70\n00\n70\nENDCHAR\nSTARTCHAR parenleftinferior\nENCODING 8333\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n20\n40\n40\n40\n20\nENDCHAR\nSTARTCHAR parenrightinferior\nENCODING 8334\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n20\n10\n10\n10\n20\nENDCHAR\nSTARTCHAR franc\nENCODING 8355\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nF8\n80\nE8\nB0\nA0\nA0\n00\n00\nENDCHAR\nSTARTCHAR lira\nENCODING 8356\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n48\nE0\n40\nE0\n40\nF8\n00\nENDCHAR\nSTARTCHAR peseta\nENCODING 8359\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n60\n50\nF8\n50\n60\n40\n00\n00\nENDCHAR\nSTARTCHAR dong\nENCODING 8363\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n08\n1C\n38\n48\n48\n38\n00\n78\nENDCHAR\nSTARTCHAR Euro\nENCODING 8364\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n38\n40\nF0\nF0\n40\n38\n00\n00\nENDCHAR\nSTARTCHAR uni20AF\nENCODING 8367\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n40\nE0\n50\n48\n48\nE8\nD0\n00\n00\nENDCHAR\nSTARTCHAR uni20D0\nENCODING 8400\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n40\nF8\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni20D1\nENCODING 8401\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\nF8\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni20D2\nENCODING 8402\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n20\n20\n20\n20\n20\n20\n20\n20\nENDCHAR\nSTARTCHAR uni20D3\nENCODING 8403\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n20\n20\n20\n20\n20\n20\n00\nENDCHAR\nSTARTCHAR uni20D4\nENCODING 8404\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nB0\nC8\nE0\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni20D5\nENCODING 8405\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n68\n98\n38\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni20D6\nENCODING 8406\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n40\nF8\n40\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni20D7\nENCODING 8407\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\nF8\n10\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2102\nENCODING 8450\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\nA8\nA0\nA0\nA8\n70\n00\n00\nENDCHAR\nSTARTCHAR afii61248\nENCODING 8453\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n80\n40\n10\n28\n10\n00\n00\nENDCHAR\nSTARTCHAR afii61289\nENCODING 8467\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n28\n28\n30\n20\n58\n00\n00\nENDCHAR\nSTARTCHAR uni2115\nENCODING 8469\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nC8\nE8\nE8\nD8\nD8\nC8\n00\n00\nENDCHAR\nSTARTCHAR afii61352\nENCODING 8470\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n90\nD0\nD0\nB8\nB4\n98\n00\n00\nENDCHAR\nSTARTCHAR uni211A\nENCODING 8474\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\nA8\nA8\nA8\nA8\n70\n18\n00\nENDCHAR\nSTARTCHAR uni211D\nENCODING 8477\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nF0\nA8\nA8\nB0\nA8\nA8\n00\n00\nENDCHAR\nSTARTCHAR trademark\nENCODING 8482\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nFC\n5C\n54\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2124\nENCODING 8484\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nF8\n28\n50\n50\nA0\nF8\n00\n00\nENDCHAR\nSTARTCHAR Omega\nENCODING 8486\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n88\n88\n88\n50\nD8\n00\n00\nENDCHAR\nSTARTCHAR estimated\nENCODING 8494\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n70\nD8\nF8\nC0\n70\n00\n00\nENDCHAR\nSTARTCHAR oneeighth\nENCODING 8539\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n40\nC0\n40\n50\n68\n10\n28\n10\n00\nENDCHAR\nSTARTCHAR threeeighths\nENCODING 8540\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nC0\n20\n40\n30\nE8\n10\n28\n10\n00\nENDCHAR\nSTARTCHAR fiveeighths\nENCODING 8541\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nE0\n80\nC0\n30\nE8\n10\n28\n10\n00\nENDCHAR\nSTARTCHAR seveneighths\nENCODING 8542\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nE0\n20\n40\n50\n68\n10\n28\n10\n00\nENDCHAR\nSTARTCHAR arrowleft\nENCODING 8592\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n20\n40\nF8\n40\n20\n00\n00\nENDCHAR\nSTARTCHAR arrowup\nENCODING 8593\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n70\nA8\n20\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR arrowright\nENCODING 8594\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n20\n10\nF8\n10\n20\n00\n00\nENDCHAR\nSTARTCHAR arrowdown\nENCODING 8595\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\n20\nA8\n70\n20\n00\n00\nENDCHAR\nSTARTCHAR arrowboth\nENCODING 8596\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n48\nFC\n48\n00\n00\n00\nENDCHAR\nSTARTCHAR arrowupdn\nENCODING 8597\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n70\nA8\n20\nA8\n70\n20\n00\nENDCHAR\nSTARTCHAR uni21A4\nENCODING 8612\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n20\n48\nF8\n48\n20\n00\n00\nENDCHAR\nSTARTCHAR uni21A5\nENCODING 8613\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n70\nA8\n20\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR uni21A6\nENCODING 8614\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n20\n90\nF8\n90\n20\n00\n00\nENDCHAR\nSTARTCHAR uni21A7\nENCODING 8615\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n20\n20\nA8\n70\n20\n00\n00\nENDCHAR\nSTARTCHAR arrowupdnbse\nENCODING 8616\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n70\nA8\n20\nA8\n70\n20\nF8\n00\nENDCHAR\nSTARTCHAR arrowdblleft\nENCODING 8656\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n20\n78\n80\n78\n20\n00\n00\nENDCHAR\nSTARTCHAR arrowdblup\nENCODING 8657\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n50\nD8\n50\n50\n50\n00\n00\nENDCHAR\nSTARTCHAR arrowdblright\nENCODING 8658\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n20\nF0\n08\nF0\n20\n00\n00\nENDCHAR\nSTARTCHAR arrowdbldown\nENCODING 8659\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n50\n50\nD8\n70\n20\n00\n00\nENDCHAR\nSTARTCHAR arrowdblboth\nENCODING 8660\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n30\n78\n84\n78\n30\n00\n00\nENDCHAR\nSTARTCHAR uni21D5\nENCODING 8661\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n70\nD8\n50\nD8\n70\n20\n00\nENDCHAR\nSTARTCHAR universal\nENCODING 8704\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n88\n88\nF8\n88\n50\n20\n00\n00\nENDCHAR\nSTARTCHAR uni2201\nENCODING 8705\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n50\n40\n40\n40\n50\n20\n00\nENDCHAR\nSTARTCHAR partialdiff\nENCODING 8706\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n08\n38\n48\n48\n30\n00\n00\nENDCHAR\nSTARTCHAR existential\nENCODING 8707\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n08\n38\n08\n08\n78\n00\n00\nENDCHAR\nSTARTCHAR uni2204\nENCODING 8708\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n78\n28\n38\n28\n28\n78\n20\n00\nENDCHAR\nSTARTCHAR emptyset\nENCODING 8709\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n98\nA8\nA8\nC8\nF0\n00\n00\nENDCHAR\nSTARTCHAR Delta\nENCODING 8710\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\n50\n50\n88\nF8\n00\n00\nENDCHAR\nSTARTCHAR gradient\nENCODING 8711\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nF8\n88\n50\n50\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR element\nENCODING 8712\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n38\n40\n78\n40\n38\n00\n00\nENDCHAR\nSTARTCHAR notelement\nENCODING 8713\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n38\n50\n78\n50\n38\n10\n00\nENDCHAR\nSTARTCHAR suchthat\nENCODING 8715\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n70\n08\n78\n08\n70\n00\n00\nENDCHAR\nSTARTCHAR uni220C\nENCODING 8716\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n70\n28\n78\n28\n70\n20\n00\nENDCHAR\nSTARTCHAR product\nENCODING 8719\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nF8\n50\n50\n50\n50\n50\n50\n50\n00\nENDCHAR\nSTARTCHAR uni2210\nENCODING 8720\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n50\n50\n50\n50\n50\n50\n50\nF8\n00\nENDCHAR\nSTARTCHAR summation\nENCODING 8721\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nF8\n40\n20\n20\n40\nF8\n00\n00\nENDCHAR\nSTARTCHAR minus\nENCODING 8722\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\nF8\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2213\nENCODING 8723\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nF8\n00\n20\n20\nF8\n20\n20\n00\nENDCHAR\nSTARTCHAR fraction\nENCODING 8725\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n08\n08\n10\n20\n40\n40\n00\n00\nENDCHAR\nSTARTCHAR uni2218\nENCODING 8728\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n20\n50\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR periodcentered\nENCODING 8729\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n20\n70\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR radical\nENCODING 8730\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n0C\n08\n08\n08\n10\nD0\n30\n30\n10\nENDCHAR\nSTARTCHAR proportional\nENCODING 8733\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n28\n50\n50\n28\n00\n00\n00\nENDCHAR\nSTARTCHAR infinity\nENCODING 8734\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n50\nA8\nA8\n50\n00\n00\n00\nENDCHAR\nSTARTCHAR orthogonal\nENCODING 8735\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n80\n80\n80\n80\nF8\n00\n00\nENDCHAR\nSTARTCHAR uni2221\nENCODING 8737\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n50\n20\n50\n90\nF8\n10\n00\nENDCHAR\nSTARTCHAR uni2224\nENCODING 8740\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\n30\n60\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR uni2225\nENCODING 8741\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n50\n50\n50\n50\n50\n00\n00\nENDCHAR\nSTARTCHAR uni2226\nENCODING 8742\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n58\n70\nD0\n50\n50\n00\n00\nENDCHAR\nSTARTCHAR logicaland\nENCODING 8743\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n20\n50\n50\n88\n00\n00\nENDCHAR\nSTARTCHAR logicalor\nENCODING 8744\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n88\n50\n50\n20\n00\n00\nENDCHAR\nSTARTCHAR intersection\nENCODING 8745\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n70\n88\n88\n88\n00\n00\nENDCHAR\nSTARTCHAR union\nENCODING 8746\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n88\n88\n88\n70\n00\n00\nENDCHAR\nSTARTCHAR integral\nENCODING 8747\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n28\n20\n20\n20\n20\n20\nA0\n40\nENDCHAR\nSTARTCHAR uni222E\nENCODING 8750\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n28\n20\n70\nA8\n70\n20\nA0\n40\nENDCHAR\nSTARTCHAR therefore\nENCODING 8756\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n20\n00\n00\n88\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2235\nENCODING 8757\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n88\n00\n00\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2236\nENCODING 8758\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n20\n00\n00\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2237\nENCODING 8759\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n48\n00\n00\n48\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2238\nENCODING 8760\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n20\n00\nF8\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2239\nENCODING 8761\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n08\n00\nE0\n00\n08\n00\n00\nENDCHAR\nSTARTCHAR uni223A\nENCODING 8762\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n88\n00\nF8\n00\n88\n00\n00\nENDCHAR\nSTARTCHAR uni223B\nENCODING 8763\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n10\n00\n28\n50\n00\n20\n00\nENDCHAR\nSTARTCHAR similar\nENCODING 8764\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n28\n50\n00\n00\n00\nENDCHAR\nSTARTCHAR uni223D\nENCODING 8765\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n50\n28\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2243\nENCODING 8771\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n28\n50\n00\n78\n00\n00\nENDCHAR\nSTARTCHAR congruent\nENCODING 8773\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n28\n50\n00\n78\n00\n78\n00\nENDCHAR\nSTARTCHAR approxequal\nENCODING 8776\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n40\nA8\n50\nA8\n10\n00\n00\nENDCHAR\nSTARTCHAR uni2249\nENCODING 8777\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n50\nA8\n70\nA8\n50\n40\n00\nENDCHAR\nSTARTCHAR uni2259\nENCODING 8793\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n50\n00\nF8\n00\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR uni225F\nENCODING 8799\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n60\n10\n20\n00\n20\n00\nF8\n00\nF8\nENDCHAR\nSTARTCHAR notequal\nENCODING 8800\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n10\nF8\n20\nF8\n40\n00\n00\nENDCHAR\nSTARTCHAR equivalence\nENCODING 8801\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\nF8\n00\nF8\n00\nF8\n00\n00\nENDCHAR\nSTARTCHAR uni2262\nENCODING 8802\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\nF8\n20\nF8\n20\nF8\n40\n00\nENDCHAR\nSTARTCHAR uni2263\nENCODING 8803\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nF8\n00\nF8\n00\nF8\n00\nF8\n00\nENDCHAR\nSTARTCHAR lessequal\nENCODING 8804\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n18\n60\n80\n60\n98\n60\n18\n00\nENDCHAR\nSTARTCHAR greaterequal\nENCODING 8805\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nC0\n30\n08\n30\nC8\n30\nC0\n00\nENDCHAR\nSTARTCHAR uni226A\nENCODING 8810\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n28\n50\nA0\n50\n28\n00\n00\nENDCHAR\nSTARTCHAR uni226B\nENCODING 8811\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\nA0\n50\n28\n50\nA0\n00\n00\nENDCHAR\nSTARTCHAR propersubset\nENCODING 8834\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n38\n40\n40\n38\n00\n00\n00\nENDCHAR\nSTARTCHAR propersuperset\nENCODING 8835\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n70\n08\n08\n70\n00\n00\n00\nENDCHAR\nSTARTCHAR notsubset\nENCODING 8836\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n38\n50\n50\n38\n10\n00\n00\nENDCHAR\nSTARTCHAR uni2285\nENCODING 8837\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n70\n28\n28\n70\n20\n00\n00\nENDCHAR\nSTARTCHAR reflexsubset\nENCODING 8838\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n38\n40\n40\n38\n00\n78\n00\n00\nENDCHAR\nSTARTCHAR reflexsuperset\nENCODING 8839\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n08\n08\n70\n00\n78\n00\n00\nENDCHAR\nSTARTCHAR uni2288\nENCODING 8840\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n38\n50\n50\n38\n10\n78\n10\n00\nENDCHAR\nSTARTCHAR uni2289\nENCODING 8841\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n70\n28\n28\n70\n20\n78\n20\n00\nENDCHAR\nSTARTCHAR uni228A\nENCODING 8842\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n38\n40\n40\n38\n10\n78\n20\n00\nENDCHAR\nSTARTCHAR uni228B\nENCODING 8843\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n08\n08\n70\n10\n78\n20\n00\nENDCHAR\nSTARTCHAR circleplus\nENCODING 8853\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n70\nA8\nF8\nA8\n70\n00\n00\nENDCHAR\nSTARTCHAR uni2296\nENCODING 8854\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n70\n88\nF8\n88\n70\n00\n00\nENDCHAR\nSTARTCHAR circlemultiply\nENCODING 8855\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n70\nD8\nA8\nD8\n70\n00\n00\nENDCHAR\nSTARTCHAR uni2298\nENCODING 8856\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n70\n98\nA8\nC8\n70\n00\n00\nENDCHAR\nSTARTCHAR uni2299\nENCODING 8857\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n70\n88\nA8\n88\n70\n00\n00\nENDCHAR\nSTARTCHAR uni22A2\nENCODING 8866\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n80\n80\nF8\n80\n80\n00\n00\nENDCHAR\nSTARTCHAR uni22A3\nENCODING 8867\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n08\n08\nF8\n08\n08\n00\n00\nENDCHAR\nSTARTCHAR uni22A4\nENCODING 8868\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nF8\n20\n20\n20\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR perpendicular\nENCODING 8869\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\n20\n20\n20\nF8\n00\n00\nENDCHAR\nSTARTCHAR uni22A6\nENCODING 8870\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n40\n40\n70\n40\n40\n00\n00\nENDCHAR\nSTARTCHAR uni22A7\nENCODING 8871\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n40\n70\n40\n70\n40\n00\n00\nENDCHAR\nSTARTCHAR uni22A8\nENCODING 8872\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n80\nF8\n80\nF8\n80\n00\n00\nENDCHAR\nSTARTCHAR uni22C0\nENCODING 8896\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n20\n50\n50\n50\n88\n88\n88\n00\nENDCHAR\nSTARTCHAR uni22C1\nENCODING 8897\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n88\n88\n88\n50\n50\n50\n20\n20\n00\nENDCHAR\nSTARTCHAR uni22C2\nENCODING 8898\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n70\n88\n88\n88\n88\n88\n88\n88\n00\nENDCHAR\nSTARTCHAR uni22C3\nENCODING 8899\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n88\n88\n88\n88\n88\n88\n88\n70\n00\nENDCHAR\nSTARTCHAR dotmath\nENCODING 8901\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n20\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni22EE\nENCODING 8942\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n00\n00\n20\n00\n00\n20\n00\nENDCHAR\nSTARTCHAR uni22EF\nENCODING 8943\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\nA8\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni22F0\nENCODING 8944\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n08\n00\n00\n20\n00\n00\n80\n00\nENDCHAR\nSTARTCHAR uni22F1\nENCODING 8945\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n80\n00\n00\n20\n00\n00\n08\n00\nENDCHAR\nSTARTCHAR uni2300\nENCODING 8960\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n78\n98\nA8\nC8\nF0\n00\n00\nENDCHAR\nSTARTCHAR house\nENCODING 8962\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n50\n88\n88\n88\nF8\n00\n00\nENDCHAR\nSTARTCHAR uni2308\nENCODING 8968\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n40\n40\n40\n40\n40\n00\n00\nENDCHAR\nSTARTCHAR uni2309\nENCODING 8969\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n10\n10\n10\n10\n10\n00\n00\nENDCHAR\nSTARTCHAR uni230A\nENCODING 8970\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n40\n40\n40\n40\n70\n00\n00\nENDCHAR\nSTARTCHAR uni230B\nENCODING 8971\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n10\n10\n10\n10\n70\n00\n00\nENDCHAR\nSTARTCHAR revlogicalnot\nENCODING 8976\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n78\n40\n40\n00\n00\nENDCHAR\nSTARTCHAR integraltp\nENCODING 8992\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n08\n14\n10\n10\n10\n10\n10\n10\nENDCHAR\nSTARTCHAR integralbt\nENCODING 8993\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n10\n10\n10\n10\n10\n50\n20\n00\nENDCHAR\nSTARTCHAR uni23BA\nENCODING 9146\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nFC\n00\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni23BB\nENCODING 9147\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\nFC\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni23BC\nENCODING 9148\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\nFC\n00\n00\nENDCHAR\nSTARTCHAR uni23BD\nENCODING 9149\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n00\n00\nFC\nENDCHAR\nSTARTCHAR uni2409\nENCODING 9225\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nA0\nE0\nA0\n00\n38\n10\n10\n00\nENDCHAR\nSTARTCHAR uni240A\nENCODING 9226\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n80\n80\n80\nC0\n38\n20\n30\n20\nENDCHAR\nSTARTCHAR uni240B\nENCODING 9227\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nA0\nA0\n40\n40\n38\n10\n10\n10\nENDCHAR\nSTARTCHAR uni240C\nENCODING 9228\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nE0\n80\nC0\n80\n38\n20\n30\n20\nENDCHAR\nSTARTCHAR uni240D\nENCODING 9229\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n60\n80\n60\n00\n30\n28\n30\n28\nENDCHAR\nSTARTCHAR uni2424\nENCODING 9252\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n90\nD0\nB0\n90\n20\n20\n20\n38\nENDCHAR\nSTARTCHAR SF100000\nENCODING 9472\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\nFC\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2501\nENCODING 9473\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\nFC\nFC\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR SF110000\nENCODING 9474\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n10\n10\n10\n10\n10\n10\n10\n10\nENDCHAR\nSTARTCHAR uni2503\nENCODING 9475\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n30\n30\n30\n30\n30\n30\n30\n30\n30\nENDCHAR\nSTARTCHAR SF010000\nENCODING 9484\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n1C\n10\n10\n10\n10\nENDCHAR\nSTARTCHAR SF030000\nENCODING 9488\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\nF0\n10\n10\n10\n10\nENDCHAR\nSTARTCHAR SF020000\nENCODING 9492\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n10\n10\n10\n1C\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR SF040000\nENCODING 9496\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n10\n10\n10\nF0\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR SF080000\nENCODING 9500\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n10\n10\n10\n1C\n10\n10\n10\n10\nENDCHAR\nSTARTCHAR SF090000\nENCODING 9508\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n10\n10\n10\nF0\n10\n10\n10\n10\nENDCHAR\nSTARTCHAR SF060000\nENCODING 9516\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\nFC\n10\n10\n10\n10\nENDCHAR\nSTARTCHAR SF070000\nENCODING 9524\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n10\n10\n10\nFC\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR SF050000\nENCODING 9532\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n10\n10\n10\nFC\n10\n10\n10\n10\nENDCHAR\nSTARTCHAR uni254C\nENCODING 9548\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\nD8\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni254D\nENCODING 9549\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\nD8\nD8\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni254E\nENCODING 9550\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n10\n10\n10\n00\n10\n10\n10\n00\nENDCHAR\nSTARTCHAR uni254F\nENCODING 9551\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n30\n30\n30\n30\n00\n30\n30\n30\n00\nENDCHAR\nSTARTCHAR SF430000\nENCODING 9552\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\nFC\n00\nFC\n00\n00\n00\nENDCHAR\nSTARTCHAR SF240000\nENCODING 9553\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n28\n28\n28\n28\n28\n28\n28\n28\nENDCHAR\nSTARTCHAR SF510000\nENCODING 9554\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n1C\n10\n1C\n10\n10\n10\nENDCHAR\nSTARTCHAR SF520000\nENCODING 9555\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n3C\n28\n28\n28\n28\nENDCHAR\nSTARTCHAR SF390000\nENCODING 9556\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n3C\n20\n2C\n28\n28\n28\nENDCHAR\nSTARTCHAR SF220000\nENCODING 9557\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\nF0\n10\nF0\n10\n10\n10\nENDCHAR\nSTARTCHAR SF210000\nENCODING 9558\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\nF8\n28\n28\n28\n28\nENDCHAR\nSTARTCHAR SF250000\nENCODING 9559\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\nF8\n08\nE8\n28\n28\n28\nENDCHAR\nSTARTCHAR SF500000\nENCODING 9560\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n10\n10\n1C\n10\n1C\n00\n00\n00\nENDCHAR\nSTARTCHAR SF490000\nENCODING 9561\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n28\n28\n28\n3C\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR SF380000\nENCODING 9562\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n28\n28\n2C\n20\n3C\n00\n00\n00\nENDCHAR\nSTARTCHAR SF280000\nENCODING 9563\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n10\n10\nF0\n10\nF0\n00\n00\n00\nENDCHAR\nSTARTCHAR SF270000\nENCODING 9564\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n28\n28\n28\nF8\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR SF260000\nENCODING 9565\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n28\n28\nE8\n08\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR SF360000\nENCODING 9566\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n10\n10\n1C\n10\n1C\n10\n10\n10\nENDCHAR\nSTARTCHAR SF370000\nENCODING 9567\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n28\n28\n28\n2C\n28\n28\n28\n28\nENDCHAR\nSTARTCHAR SF420000\nENCODING 9568\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n28\n28\n2C\n20\n2C\n28\n28\n28\nENDCHAR\nSTARTCHAR SF190000\nENCODING 9569\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n10\n10\nF0\n10\nF0\n10\n10\n10\nENDCHAR\nSTARTCHAR SF200000\nENCODING 9570\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n28\n28\n28\nE8\n28\n28\n28\n28\nENDCHAR\nSTARTCHAR SF230000\nENCODING 9571\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n28\n28\nE8\n08\nE8\n28\n28\n28\nENDCHAR\nSTARTCHAR SF470000\nENCODING 9572\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\nFC\n00\nFC\n10\n10\n10\nENDCHAR\nSTARTCHAR SF480000\nENCODING 9573\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\nFC\n28\n28\n28\n28\nENDCHAR\nSTARTCHAR SF410000\nENCODING 9574\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\nFC\n00\nEC\n28\n28\n28\nENDCHAR\nSTARTCHAR SF450000\nENCODING 9575\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n10\n10\nFC\n00\nFC\n00\n00\n00\nENDCHAR\nSTARTCHAR SF460000\nENCODING 9576\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n28\n28\n28\nFC\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR SF400000\nENCODING 9577\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n28\n28\nEC\n00\nFC\n00\n00\n00\nENDCHAR\nSTARTCHAR SF540000\nENCODING 9578\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n10\n10\nFC\n10\nFC\n10\n10\n10\nENDCHAR\nSTARTCHAR SF530000\nENCODING 9579\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n28\n28\n28\nFC\n28\n28\n28\n28\nENDCHAR\nSTARTCHAR SF440000\nENCODING 9580\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n28\n28\n28\nEC\n00\nEC\n28\n28\n28\nENDCHAR\nSTARTCHAR uni256D\nENCODING 9581\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n04\n08\n10\n10\n10\nENDCHAR\nSTARTCHAR uni256E\nENCODING 9582\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\nC0\n20\n10\n10\n10\nENDCHAR\nSTARTCHAR uni256F\nENCODING 9583\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n10\n10\n20\nC0\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2570\nENCODING 9584\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n10\n10\n10\n08\n04\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2571\nENCODING 9585\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n04\n04\n08\n10\n10\n20\n40\n40\n80\nENDCHAR\nSTARTCHAR uni2572\nENCODING 9586\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n80\n80\n40\n20\n20\n10\n08\n08\n04\nENDCHAR\nSTARTCHAR uni2573\nENCODING 9587\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n84\n84\n48\n30\n30\n30\n48\n48\n84\nENDCHAR\nSTARTCHAR upblock\nENCODING 9600\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nFC\nFC\nFC\nFC\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2581\nENCODING 9601\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n00\n00\nFC\nENDCHAR\nSTARTCHAR uni2582\nENCODING 9602\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n00\nFC\nFC\nENDCHAR\nSTARTCHAR uni2583\nENCODING 9603\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\nFC\nFC\nFC\nFC\nENDCHAR\nSTARTCHAR dnblock\nENCODING 9604\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\nFC\nFC\nFC\nFC\nFC\nENDCHAR\nSTARTCHAR uni2585\nENCODING 9605\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\nFC\nFC\nFC\nFC\nFC\nFC\nENDCHAR\nSTARTCHAR uni2586\nENCODING 9606\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\nFC\nFC\nFC\nFC\nFC\nFC\nFC\nENDCHAR\nSTARTCHAR uni2587\nENCODING 9607\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nFC\nFC\nFC\nFC\nFC\nFC\nFC\nFC\nENDCHAR\nSTARTCHAR block\nENCODING 9608\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nFC\nFC\nFC\nFC\nFC\nFC\nFC\nFC\nFC\nENDCHAR\nSTARTCHAR uni2589\nENCODING 9609\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nF8\nF8\nF8\nF8\nF8\nF8\nF8\nF8\nF8\nENDCHAR\nSTARTCHAR uni258A\nENCODING 9610\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nF0\nF0\nF0\nF0\nF0\nF0\nF0\nF0\nF0\nENDCHAR\nSTARTCHAR uni258B\nENCODING 9611\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nF0\nF0\nF0\nF0\nF0\nF0\nF0\nF0\nF0\nENDCHAR\nSTARTCHAR lfblock\nENCODING 9612\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nE0\nE0\nE0\nE0\nE0\nE0\nE0\nE0\nE0\nENDCHAR\nSTARTCHAR uni258D\nENCODING 9613\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nC0\nC0\nC0\nC0\nC0\nC0\nC0\nC0\nC0\nENDCHAR\nSTARTCHAR uni258E\nENCODING 9614\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nC0\nC0\nC0\nC0\nC0\nC0\nC0\nC0\nC0\nENDCHAR\nSTARTCHAR uni258F\nENCODING 9615\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n80\n80\n80\n80\n80\n80\n80\n80\n80\nENDCHAR\nSTARTCHAR rtblock\nENCODING 9616\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n1C\n1C\n1C\n1C\n1C\n1C\n1C\n1C\n1C\nENDCHAR\nSTARTCHAR ltshade\nENCODING 9617\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nA8\n00\n54\n00\nA8\n00\n54\n00\nA8\nENDCHAR\nSTARTCHAR shade\nENCODING 9618\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n54\nA8\n54\nA8\n54\nA8\n54\nA8\n54\nENDCHAR\nSTARTCHAR dkshade\nENCODING 9619\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nFC\nA8\nFC\n54\nFC\nA8\nFC\n54\nFC\nENDCHAR\nSTARTCHAR uni2594\nENCODING 9620\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nFC\n00\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2595\nENCODING 9621\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n04\n04\n04\n04\n04\n04\n04\n04\n04\nENDCHAR\nSTARTCHAR uni2596\nENCODING 9622\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\nE0\nE0\nE0\nE0\nE0\nENDCHAR\nSTARTCHAR uni2597\nENCODING 9623\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n1C\n1C\n1C\n1C\n1C\nENDCHAR\nSTARTCHAR uni2598\nENCODING 9624\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nE0\nE0\nE0\nE0\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2599\nENCODING 9625\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nE0\nE0\nE0\nE0\nFC\nFC\nFC\nFC\nFC\nENDCHAR\nSTARTCHAR uni259A\nENCODING 9626\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nE0\nE0\nE0\nE0\n1C\n1C\n1C\n1C\n1C\nENDCHAR\nSTARTCHAR uni259B\nENCODING 9627\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nFC\nFC\nFC\nFC\nE0\nE0\nE0\nE0\nE0\nENDCHAR\nSTARTCHAR uni259C\nENCODING 9628\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nFC\nFC\nFC\nFC\n1C\n1C\n1C\n1C\n1C\nENDCHAR\nSTARTCHAR uni259D\nENCODING 9629\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n1C\n1C\n1C\n1C\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni259E\nENCODING 9630\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n1C\n1C\n1C\n1C\nE0\nE0\nE0\nE0\nE0\nENDCHAR\nSTARTCHAR uni259F\nENCODING 9631\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n1C\n1C\n1C\n1C\nFC\nFC\nFC\nFC\nFC\nENDCHAR\nSTARTCHAR filledbox\nENCODING 9632\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\nF8\nF8\nF8\nF8\nF8\n00\n00\nENDCHAR\nSTARTCHAR H22073\nENCODING 9633\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\nF8\n88\n88\n88\nF8\n00\n00\nENDCHAR\nSTARTCHAR uni25A2\nENCODING 9634\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n70\n88\n88\n88\n70\n00\n00\nENDCHAR\nSTARTCHAR uni25A3\nENCODING 9635\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\nF8\n88\nA8\n88\nF8\n00\n00\nENDCHAR\nSTARTCHAR H18543\nENCODING 9642\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n70\n70\n70\n00\n00\n00\nENDCHAR\nSTARTCHAR H18551\nENCODING 9643\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n70\n50\n70\n00\n00\n00\nENDCHAR\nSTARTCHAR filledrect\nENCODING 9644\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\nF8\nF8\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR uni25AD\nENCODING 9645\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\nF8\n88\nF8\n00\n00\n00\nENDCHAR\nSTARTCHAR uni25AE\nENCODING 9646\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n78\n78\n78\n78\n78\n00\n00\nENDCHAR\nSTARTCHAR uni25AF\nENCODING 9647\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n78\n48\n48\n48\n48\n78\n00\n00\nENDCHAR\nSTARTCHAR uni25B0\nENCODING 9648\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n78\nF8\nF0\n00\n00\n00\nENDCHAR\nSTARTCHAR uni25B1\nENCODING 9649\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n78\n88\nF0\n00\n00\n00\nENDCHAR\nSTARTCHAR triagup\nENCODING 9650\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\n70\n70\nF8\nF8\n00\n00\nENDCHAR\nSTARTCHAR uni25B3\nENCODING 9651\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\n50\n50\n88\nF8\n00\n00\nENDCHAR\nSTARTCHAR uni25B4\nENCODING 9652\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n20\n20\n70\n70\n00\n00\n00\nENDCHAR\nSTARTCHAR uni25B5\nENCODING 9653\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n20\n20\n50\n70\n00\n00\n00\nENDCHAR\nSTARTCHAR uni25B6\nENCODING 9654\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\nC0\nF0\nF8\nF0\nC0\n00\n00\nENDCHAR\nSTARTCHAR uni25B7\nENCODING 9655\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\nC0\nB0\n88\nB0\nC0\n00\n00\nENDCHAR\nSTARTCHAR uni25B8\nENCODING 9656\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n60\n78\n60\n00\n00\n00\nENDCHAR\nSTARTCHAR uni25B9\nENCODING 9657\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n60\n58\n60\n00\n00\n00\nENDCHAR\nSTARTCHAR triagrt\nENCODING 9658\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\nE0\nF8\nE0\n00\n00\n00\nENDCHAR\nSTARTCHAR uni25BB\nENCODING 9659\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\nE0\n98\nE0\n00\n00\n00\nENDCHAR\nSTARTCHAR triagdn\nENCODING 9660\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nF8\nF8\n70\n70\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR uni25BD\nENCODING 9661\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\nF8\n88\n50\n50\n20\n20\n00\n00\nENDCHAR\nSTARTCHAR uni25BE\nENCODING 9662\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n70\n70\n20\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR uni25BF\nENCODING 9663\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n70\n50\n20\n20\n00\n00\n00\nENDCHAR\nSTARTCHAR uni25C0\nENCODING 9664\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n18\n78\nF8\n78\n18\n00\n00\nENDCHAR\nSTARTCHAR uni25C1\nENCODING 9665\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n18\n68\n88\n68\n18\n00\n00\nENDCHAR\nSTARTCHAR uni25C2\nENCODING 9666\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n18\n78\n18\n00\n00\n00\nENDCHAR\nSTARTCHAR uni25C3\nENCODING 9667\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n18\n68\n18\n00\n00\n00\nENDCHAR\nSTARTCHAR triaglf\nENCODING 9668\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n38\nF8\n38\n00\n00\n00\nENDCHAR\nSTARTCHAR uni25C5\nENCODING 9669\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n38\nC8\n38\n00\n00\n00\nENDCHAR\nSTARTCHAR uni25C6\nENCODING 9670\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n30\n78\nFC\n78\n30\n00\n00\nENDCHAR\nSTARTCHAR lozenge\nENCODING 9674\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n50\n50\n88\n50\n50\n20\n00\nENDCHAR\nSTARTCHAR circle\nENCODING 9675\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n70\n88\n88\n88\n70\n00\n00\nENDCHAR\nSTARTCHAR H18533\nENCODING 9679\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n70\nF8\nF8\nF8\n70\n00\n00\nENDCHAR\nSTARTCHAR invbullet\nENCODING 9688\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nFC\nFC\nCC\n84\n84\nCC\nFC\nFC\nFC\nENDCHAR\nSTARTCHAR invcircle\nENCODING 9689\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\nFC\nFC\nCC\nB4\nB4\nCC\nFC\nFC\nFC\nENDCHAR\nSTARTCHAR openbullet\nENCODING 9702\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n30\n48\n48\n30\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2600\nENCODING 9728\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\nA8\n70\nF8\n70\nA8\n20\n00\nENDCHAR\nSTARTCHAR uni2639\nENCODING 9785\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n78\n84\nCC\n84\nB4\nCC\n84\n78\n00\nENDCHAR\nSTARTCHAR smileface\nENCODING 9786\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n78\n84\nCC\n84\nCC\nB4\n84\n78\n00\nENDCHAR\nSTARTCHAR invsmileface\nENCODING 9787\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n78\nFC\nB4\nFC\nB4\nCC\nFC\n78\n00\nENDCHAR\nSTARTCHAR sun\nENCODING 9788\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\nA8\n70\nD8\n70\nA8\n20\n00\nENDCHAR\nSTARTCHAR uni263F\nENCODING 9791\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n88\n70\n88\n88\n70\n20\nF8\n20\n00\nENDCHAR\nSTARTCHAR female\nENCODING 9792\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n70\n88\n88\n70\n20\nF8\n20\n00\nENDCHAR\nSTARTCHAR uni2641\nENCODING 9793\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\nF8\n20\n70\n88\n88\n70\n00\nENDCHAR\nSTARTCHAR male\nENCODING 9794\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n1C\n0C\n14\n70\n88\n88\n70\n00\nENDCHAR\nSTARTCHAR spade\nENCODING 9824\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n70\nF8\nF8\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR uni2661\nENCODING 9825\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\nA8\n88\n88\n50\n20\n00\n00\nENDCHAR\nSTARTCHAR uni2662\nENCODING 9826\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n20\n50\n88\n50\n20\n00\n00\nENDCHAR\nSTARTCHAR club\nENCODING 9827\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n20\n70\nA8\nF8\nA8\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR uni2664\nENCODING 9828\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n50\n88\nF8\n20\n70\n00\n00\nENDCHAR\nSTARTCHAR heart\nENCODING 9829\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\nF8\nF8\nF8\n70\n20\n00\n00\nENDCHAR\nSTARTCHAR diamond\nENCODING 9830\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n20\n70\nF8\n70\n20\n00\n00\nENDCHAR\nSTARTCHAR uni2669\nENCODING 9833\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n10\n10\n10\n70\n60\n00\n00\nENDCHAR\nSTARTCHAR musicalnote\nENCODING 9834\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n30\n28\n20\n20\nE0\nC0\n00\n00\nENDCHAR\nSTARTCHAR musicalnotedbl\nENCODING 9835\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n60\n58\n48\nC8\nD8\n18\n00\n00\nENDCHAR\nSTARTCHAR uni27E8\nENCODING 10216\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n10\n20\n20\n20\n10\n10\n00\nENDCHAR\nSTARTCHAR uni27E9\nENCODING 10217\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n20\n20\n10\n10\n10\n20\n20\n00\nENDCHAR\nSTARTCHAR uni2800\nENCODING 10240\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2801\nENCODING 10241\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2802\nENCODING 10242\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n40\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2803\nENCODING 10243\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n40\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2804\nENCODING 10244\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n40\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2805\nENCODING 10245\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n00\n00\n40\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2806\nENCODING 10246\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n40\n00\n40\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2807\nENCODING 10247\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n40\n00\n40\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2808\nENCODING 10248\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2809\nENCODING 10249\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n00\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni280A\nENCODING 10250\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n40\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni280B\nENCODING 10251\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n40\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni280C\nENCODING 10252\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n00\n00\n40\n00\n00\n00\nENDCHAR\nSTARTCHAR uni280D\nENCODING 10253\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n00\n00\n40\n00\n00\n00\nENDCHAR\nSTARTCHAR uni280E\nENCODING 10254\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n40\n00\n40\n00\n00\n00\nENDCHAR\nSTARTCHAR uni280F\nENCODING 10255\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n40\n00\n40\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2810\nENCODING 10256\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n10\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2811\nENCODING 10257\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n10\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2812\nENCODING 10258\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n50\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2813\nENCODING 10259\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n50\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2814\nENCODING 10260\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n10\n00\n40\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2815\nENCODING 10261\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n10\n00\n40\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2816\nENCODING 10262\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n50\n00\n40\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2817\nENCODING 10263\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n50\n00\n40\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2818\nENCODING 10264\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n10\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2819\nENCODING 10265\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n10\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni281A\nENCODING 10266\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n50\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni281B\nENCODING 10267\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n50\n00\n00\n00\n00\n00\nENDCHAR\nSTARTCHAR uni281C\nENCODING 10268\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n10\n00\n40\n00\n00\n00\nENDCHAR\nSTARTCHAR uni281D\nENCODING 10269\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n10\n00\n40\n00\n00\n00\nENDCHAR\nSTARTCHAR uni281E\nENCODING 10270\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n50\n00\n40\n00\n00\n00\nENDCHAR\nSTARTCHAR uni281F\nENCODING 10271\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n50\n00\n40\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2820\nENCODING 10272\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n10\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2821\nENCODING 10273\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n00\n00\n10\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2822\nENCODING 10274\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n40\n00\n10\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2823\nENCODING 10275\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n40\n00\n10\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2824\nENCODING 10276\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n50\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2825\nENCODING 10277\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n00\n00\n50\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2826\nENCODING 10278\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n40\n00\n50\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2827\nENCODING 10279\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n40\n00\n50\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2828\nENCODING 10280\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n00\n00\n10\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2829\nENCODING 10281\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n00\n00\n10\n00\n00\n00\nENDCHAR\nSTARTCHAR uni282A\nENCODING 10282\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n40\n00\n10\n00\n00\n00\nENDCHAR\nSTARTCHAR uni282B\nENCODING 10283\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n40\n00\n10\n00\n00\n00\nENDCHAR\nSTARTCHAR uni282C\nENCODING 10284\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n00\n00\n50\n00\n00\n00\nENDCHAR\nSTARTCHAR uni282D\nENCODING 10285\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n00\n00\n50\n00\n00\n00\nENDCHAR\nSTARTCHAR uni282E\nENCODING 10286\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n40\n00\n50\n00\n00\n00\nENDCHAR\nSTARTCHAR uni282F\nENCODING 10287\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n40\n00\n50\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2830\nENCODING 10288\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n10\n00\n10\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2831\nENCODING 10289\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n10\n00\n10\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2832\nENCODING 10290\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n50\n00\n10\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2833\nENCODING 10291\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n50\n00\n10\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2834\nENCODING 10292\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n10\n00\n50\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2835\nENCODING 10293\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n10\n00\n50\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2836\nENCODING 10294\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n50\n00\n50\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2837\nENCODING 10295\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n50\n00\n50\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2838\nENCODING 10296\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n10\n00\n10\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2839\nENCODING 10297\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n10\n00\n10\n00\n00\n00\nENDCHAR\nSTARTCHAR uni283A\nENCODING 10298\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n50\n00\n10\n00\n00\n00\nENDCHAR\nSTARTCHAR uni283B\nENCODING 10299\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n50\n00\n10\n00\n00\n00\nENDCHAR\nSTARTCHAR uni283C\nENCODING 10300\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n10\n00\n50\n00\n00\n00\nENDCHAR\nSTARTCHAR uni283D\nENCODING 10301\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n10\n00\n50\n00\n00\n00\nENDCHAR\nSTARTCHAR uni283E\nENCODING 10302\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n50\n00\n50\n00\n00\n00\nENDCHAR\nSTARTCHAR uni283F\nENCODING 10303\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n50\n00\n50\n00\n00\n00\nENDCHAR\nSTARTCHAR uni2840\nENCODING 10304\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2841\nENCODING 10305\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n00\n00\n00\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2842\nENCODING 10306\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n40\n00\n00\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2843\nENCODING 10307\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n40\n00\n00\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2844\nENCODING 10308\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n40\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2845\nENCODING 10309\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n00\n00\n40\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2846\nENCODING 10310\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n40\n00\n40\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2847\nENCODING 10311\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n40\n00\n40\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2848\nENCODING 10312\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n00\n00\n00\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2849\nENCODING 10313\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n00\n00\n00\n00\n40\n00\nENDCHAR\nSTARTCHAR uni284A\nENCODING 10314\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n40\n00\n00\n00\n40\n00\nENDCHAR\nSTARTCHAR uni284B\nENCODING 10315\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n40\n00\n00\n00\n40\n00\nENDCHAR\nSTARTCHAR uni284C\nENCODING 10316\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n00\n00\n40\n00\n40\n00\nENDCHAR\nSTARTCHAR uni284D\nENCODING 10317\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n00\n00\n40\n00\n40\n00\nENDCHAR\nSTARTCHAR uni284E\nENCODING 10318\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n40\n00\n40\n00\n40\n00\nENDCHAR\nSTARTCHAR uni284F\nENCODING 10319\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n40\n00\n40\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2850\nENCODING 10320\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n10\n00\n00\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2851\nENCODING 10321\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n10\n00\n00\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2852\nENCODING 10322\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n50\n00\n00\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2853\nENCODING 10323\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n50\n00\n00\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2854\nENCODING 10324\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n10\n00\n40\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2855\nENCODING 10325\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n10\n00\n40\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2856\nENCODING 10326\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n50\n00\n40\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2857\nENCODING 10327\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n50\n00\n40\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2858\nENCODING 10328\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n10\n00\n00\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2859\nENCODING 10329\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n10\n00\n00\n00\n40\n00\nENDCHAR\nSTARTCHAR uni285A\nENCODING 10330\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n50\n00\n00\n00\n40\n00\nENDCHAR\nSTARTCHAR uni285B\nENCODING 10331\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n50\n00\n00\n00\n40\n00\nENDCHAR\nSTARTCHAR uni285C\nENCODING 10332\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n10\n00\n40\n00\n40\n00\nENDCHAR\nSTARTCHAR uni285D\nENCODING 10333\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n10\n00\n40\n00\n40\n00\nENDCHAR\nSTARTCHAR uni285E\nENCODING 10334\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n50\n00\n40\n00\n40\n00\nENDCHAR\nSTARTCHAR uni285F\nENCODING 10335\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n50\n00\n40\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2860\nENCODING 10336\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n10\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2861\nENCODING 10337\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n00\n00\n10\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2862\nENCODING 10338\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n40\n00\n10\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2863\nENCODING 10339\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n40\n00\n10\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2864\nENCODING 10340\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n50\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2865\nENCODING 10341\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n00\n00\n50\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2866\nENCODING 10342\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n40\n00\n50\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2867\nENCODING 10343\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n40\n00\n50\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2868\nENCODING 10344\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n00\n00\n10\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2869\nENCODING 10345\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n00\n00\n10\n00\n40\n00\nENDCHAR\nSTARTCHAR uni286A\nENCODING 10346\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n40\n00\n10\n00\n40\n00\nENDCHAR\nSTARTCHAR uni286B\nENCODING 10347\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n40\n00\n10\n00\n40\n00\nENDCHAR\nSTARTCHAR uni286C\nENCODING 10348\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n00\n00\n50\n00\n40\n00\nENDCHAR\nSTARTCHAR uni286D\nENCODING 10349\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n00\n00\n50\n00\n40\n00\nENDCHAR\nSTARTCHAR uni286E\nENCODING 10350\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n40\n00\n50\n00\n40\n00\nENDCHAR\nSTARTCHAR uni286F\nENCODING 10351\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n40\n00\n50\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2870\nENCODING 10352\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n10\n00\n10\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2871\nENCODING 10353\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n10\n00\n10\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2872\nENCODING 10354\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n50\n00\n10\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2873\nENCODING 10355\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n50\n00\n10\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2874\nENCODING 10356\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n10\n00\n50\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2875\nENCODING 10357\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n10\n00\n50\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2876\nENCODING 10358\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n50\n00\n50\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2877\nENCODING 10359\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n50\n00\n50\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2878\nENCODING 10360\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n10\n00\n10\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2879\nENCODING 10361\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n10\n00\n10\n00\n40\n00\nENDCHAR\nSTARTCHAR uni287A\nENCODING 10362\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n50\n00\n10\n00\n40\n00\nENDCHAR\nSTARTCHAR uni287B\nENCODING 10363\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n50\n00\n10\n00\n40\n00\nENDCHAR\nSTARTCHAR uni287C\nENCODING 10364\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n10\n00\n50\n00\n40\n00\nENDCHAR\nSTARTCHAR uni287D\nENCODING 10365\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n10\n00\n50\n00\n40\n00\nENDCHAR\nSTARTCHAR uni287E\nENCODING 10366\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n50\n00\n50\n00\n40\n00\nENDCHAR\nSTARTCHAR uni287F\nENCODING 10367\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n50\n00\n50\n00\n40\n00\nENDCHAR\nSTARTCHAR uni2880\nENCODING 10368\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n00\n10\n00\nENDCHAR\nSTARTCHAR uni2881\nENCODING 10369\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n00\n00\n00\n00\n10\n00\nENDCHAR\nSTARTCHAR uni2882\nENCODING 10370\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n40\n00\n00\n00\n10\n00\nENDCHAR\nSTARTCHAR uni2883\nENCODING 10371\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n40\n00\n00\n00\n10\n00\nENDCHAR\nSTARTCHAR uni2884\nENCODING 10372\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n40\n00\n10\n00\nENDCHAR\nSTARTCHAR uni2885\nENCODING 10373\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n00\n00\n40\n00\n10\n00\nENDCHAR\nSTARTCHAR uni2886\nENCODING 10374\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n40\n00\n40\n00\n10\n00\nENDCHAR\nSTARTCHAR uni2887\nENCODING 10375\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n40\n00\n40\n00\n10\n00\nENDCHAR\nSTARTCHAR uni2888\nENCODING 10376\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n00\n00\n00\n00\n10\n00\nENDCHAR\nSTARTCHAR uni2889\nENCODING 10377\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n00\n00\n00\n00\n10\n00\nENDCHAR\nSTARTCHAR uni288A\nENCODING 10378\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n40\n00\n00\n00\n10\n00\nENDCHAR\nSTARTCHAR uni288B\nENCODING 10379\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n40\n00\n00\n00\n10\n00\nENDCHAR\nSTARTCHAR uni288C\nENCODING 10380\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n00\n00\n40\n00\n10\n00\nENDCHAR\nSTARTCHAR uni288D\nENCODING 10381\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n00\n00\n40\n00\n10\n00\nENDCHAR\nSTARTCHAR uni288E\nENCODING 10382\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n40\n00\n40\n00\n10\n00\nENDCHAR\nSTARTCHAR uni288F\nENCODING 10383\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n40\n00\n40\n00\n10\n00\nENDCHAR\nSTARTCHAR uni2890\nENCODING 10384\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n10\n00\n00\n00\n10\n00\nENDCHAR\nSTARTCHAR uni2891\nENCODING 10385\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n10\n00\n00\n00\n10\n00\nENDCHAR\nSTARTCHAR uni2892\nENCODING 10386\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n50\n00\n00\n00\n10\n00\nENDCHAR\nSTARTCHAR uni2893\nENCODING 10387\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n50\n00\n00\n00\n10\n00\nENDCHAR\nSTARTCHAR uni2894\nENCODING 10388\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n10\n00\n40\n00\n10\n00\nENDCHAR\nSTARTCHAR uni2895\nENCODING 10389\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n10\n00\n40\n00\n10\n00\nENDCHAR\nSTARTCHAR uni2896\nENCODING 10390\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n50\n00\n40\n00\n10\n00\nENDCHAR\nSTARTCHAR uni2897\nENCODING 10391\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n50\n00\n40\n00\n10\n00\nENDCHAR\nSTARTCHAR uni2898\nENCODING 10392\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n10\n00\n00\n00\n10\n00\nENDCHAR\nSTARTCHAR uni2899\nENCODING 10393\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n10\n00\n00\n00\n10\n00\nENDCHAR\nSTARTCHAR uni289A\nENCODING 10394\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n50\n00\n00\n00\n10\n00\nENDCHAR\nSTARTCHAR uni289B\nENCODING 10395\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n50\n00\n00\n00\n10\n00\nENDCHAR\nSTARTCHAR uni289C\nENCODING 10396\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n10\n00\n40\n00\n10\n00\nENDCHAR\nSTARTCHAR uni289D\nENCODING 10397\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n10\n00\n40\n00\n10\n00\nENDCHAR\nSTARTCHAR uni289E\nENCODING 10398\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n50\n00\n40\n00\n10\n00\nENDCHAR\nSTARTCHAR uni289F\nENCODING 10399\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n50\n00\n40\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28A0\nENCODING 10400\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n10\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28A1\nENCODING 10401\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n00\n00\n10\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28A2\nENCODING 10402\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n40\n00\n10\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28A3\nENCODING 10403\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n40\n00\n10\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28A4\nENCODING 10404\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n50\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28A5\nENCODING 10405\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n00\n00\n50\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28A6\nENCODING 10406\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n40\n00\n50\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28A7\nENCODING 10407\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n40\n00\n50\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28A8\nENCODING 10408\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n00\n00\n10\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28A9\nENCODING 10409\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n00\n00\n10\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28AA\nENCODING 10410\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n40\n00\n10\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28AB\nENCODING 10411\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n40\n00\n10\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28AC\nENCODING 10412\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n00\n00\n50\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28AD\nENCODING 10413\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n00\n00\n50\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28AE\nENCODING 10414\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n40\n00\n50\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28AF\nENCODING 10415\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n40\n00\n50\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28B0\nENCODING 10416\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n10\n00\n10\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28B1\nENCODING 10417\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n10\n00\n10\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28B2\nENCODING 10418\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n50\n00\n10\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28B3\nENCODING 10419\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n50\n00\n10\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28B4\nENCODING 10420\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n10\n00\n50\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28B5\nENCODING 10421\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n10\n00\n50\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28B6\nENCODING 10422\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n50\n00\n50\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28B7\nENCODING 10423\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n50\n00\n50\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28B8\nENCODING 10424\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n10\n00\n10\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28B9\nENCODING 10425\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n10\n00\n10\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28BA\nENCODING 10426\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n50\n00\n10\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28BB\nENCODING 10427\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n50\n00\n10\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28BC\nENCODING 10428\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n10\n00\n50\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28BD\nENCODING 10429\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n10\n00\n50\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28BE\nENCODING 10430\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n50\n00\n50\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28BF\nENCODING 10431\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n50\n00\n50\n00\n10\n00\nENDCHAR\nSTARTCHAR uni28C0\nENCODING 10432\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n00\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28C1\nENCODING 10433\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n00\n00\n00\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28C2\nENCODING 10434\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n40\n00\n00\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28C3\nENCODING 10435\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n40\n00\n00\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28C4\nENCODING 10436\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n40\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28C5\nENCODING 10437\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n00\n00\n40\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28C6\nENCODING 10438\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n40\n00\n40\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28C7\nENCODING 10439\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n40\n00\n40\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28C8\nENCODING 10440\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n00\n00\n00\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28C9\nENCODING 10441\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n00\n00\n00\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28CA\nENCODING 10442\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n40\n00\n00\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28CB\nENCODING 10443\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n40\n00\n00\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28CC\nENCODING 10444\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n00\n00\n40\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28CD\nENCODING 10445\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n00\n00\n40\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28CE\nENCODING 10446\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n40\n00\n40\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28CF\nENCODING 10447\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n40\n00\n40\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28D0\nENCODING 10448\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n10\n00\n00\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28D1\nENCODING 10449\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n10\n00\n00\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28D2\nENCODING 10450\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n50\n00\n00\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28D3\nENCODING 10451\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n50\n00\n00\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28D4\nENCODING 10452\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n10\n00\n40\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28D5\nENCODING 10453\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n10\n00\n40\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28D6\nENCODING 10454\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n50\n00\n40\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28D7\nENCODING 10455\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n50\n00\n40\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28D8\nENCODING 10456\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n10\n00\n00\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28D9\nENCODING 10457\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n10\n00\n00\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28DA\nENCODING 10458\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n50\n00\n00\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28DB\nENCODING 10459\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n50\n00\n00\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28DC\nENCODING 10460\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n10\n00\n40\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28DD\nENCODING 10461\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n10\n00\n40\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28DE\nENCODING 10462\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n50\n00\n40\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28DF\nENCODING 10463\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n50\n00\n40\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28E0\nENCODING 10464\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n10\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28E1\nENCODING 10465\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n00\n00\n10\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28E2\nENCODING 10466\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n40\n00\n10\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28E3\nENCODING 10467\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n40\n00\n10\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28E4\nENCODING 10468\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n00\n00\n50\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28E5\nENCODING 10469\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n00\n00\n50\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28E6\nENCODING 10470\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n40\n00\n50\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28E7\nENCODING 10471\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n40\n00\n50\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28E8\nENCODING 10472\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n00\n00\n10\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28E9\nENCODING 10473\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n00\n00\n10\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28EA\nENCODING 10474\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n40\n00\n10\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28EB\nENCODING 10475\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n40\n00\n10\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28EC\nENCODING 10476\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n00\n00\n50\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28ED\nENCODING 10477\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n00\n00\n50\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28EE\nENCODING 10478\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n40\n00\n50\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28EF\nENCODING 10479\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n40\n00\n50\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28F0\nENCODING 10480\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n10\n00\n10\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28F1\nENCODING 10481\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n10\n00\n10\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28F2\nENCODING 10482\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n50\n00\n10\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28F3\nENCODING 10483\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n50\n00\n10\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28F4\nENCODING 10484\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n10\n00\n50\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28F5\nENCODING 10485\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n10\n00\n50\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28F6\nENCODING 10486\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n00\n00\n50\n00\n50\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28F7\nENCODING 10487\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n40\n00\n50\n00\n50\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28F8\nENCODING 10488\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n10\n00\n10\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28F9\nENCODING 10489\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n10\n00\n10\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28FA\nENCODING 10490\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n50\n00\n10\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28FB\nENCODING 10491\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n50\n00\n10\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28FC\nENCODING 10492\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n10\n00\n50\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28FD\nENCODING 10493\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n10\n00\n50\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28FE\nENCODING 10494\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n00\n50\n00\n50\n00\n50\n00\nENDCHAR\nSTARTCHAR uni28FF\nENCODING 10495\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n50\n00\n50\n00\n50\n00\n50\n00\nENDCHAR\nSTARTCHAR fi\nENCODING 64257\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n10\n28\n20\n78\n28\n28\n00\n00\nENDCHAR\nSTARTCHAR fl\nENCODING 64258\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n00\n18\n28\n28\n78\n28\n28\n00\n00\nENDCHAR\nSTARTCHAR uniFFFD\nENCODING 65533\nSWIDTH 640 0\nDWIDTH 6 0\nBBX 6 9 0 -2\nBITMAP\n70\nD8\nA8\nE8\nD8\nD8\nF8\nD8\n70\nENDCHAR\nENDFONT\n"
  },
  {
    "path": "share/examples/gpanel/fonts/convbdf.c",
    "content": "/*\n * Convert BDF files to C source\n *\n * Copyright (c) 2002 by Greg Haerr <greg@censoft.com>\n * Copyright (c) 2008-2015 by Serge Vakulenko <vak@cronyx.ru>\n *\n * What fun it is converting font data...\n *\n * 09/17/02 Version 1.0\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <time.h>\n\n/*\n * Glyph image helper macros.\n */\n#define BITS_PER_WORD       (sizeof(unsigned short) * 8)\n#define NIBBLES_PER_WORD    (BITS_PER_WORD/4)\n#define WORDS(bits)         (((bits)+BITS_PER_WORD-1)/BITS_PER_WORD)\n#define BYTES(bits)         (WORDS(bits) * sizeof(unsigned short))\n#define TEST_HIGH_BIT(w)    ((w) >> (BITS_PER_WORD - 1) & 1)\n\n/*\n * Builtin C-based proportional/fixed font structure.\n * Based on The Microwindows Project http://microwindows.org\n */\ntypedef struct {\n    char *  name;           /* font name*/\n    int     maxwidth;       /* max width in pixels*/\n    int     height;         /* height in pixels*/\n    int     ascent;         /* ascent (baseline) height*/\n    int     firstchar;      /* first character in bitmap*/\n    int     size;           /* font size in glyphs*/\n    unsigned short *bits;   /* 16-bit right-padded bitmap data*/\n    unsigned long *offset;  /* offsets into bitmap data*/\n    unsigned char *width;   /* character widths or NULL if fixed*/\n    int     defaultchar;    /* default char (not glyph index)*/\n    long    bits_size;      /* # words of bits[]*/\n\n    /* unused by runtime system, read in by convbdf*/\n    char *  facename;       /* facename of font*/\n    char *  copyright;      /* copyright info for loadable fonts*/\n    int     pixel_size;\n    int     descent;\n    int     fbbw, fbbh, fbbx, fbby;\n} font_t;\n\n#define isprefix(buf,str)   (!strncmp(buf, str, strlen(str)))\n#define strequal(s1,s2)     (!strcmp(s1, s2))\n\n#define EXTRA   300     /* # bytes extra allocation for buggy .bdf files*/\n\nint gen_map = 1;\nint start_char = 0;\nint default_char = 0;\nint exclude_start = 0;\nint exclude_end = 0;\nint limit_char = 65535;\nint ascent_correction = 0;\nint descent_correction = 0;\nchar outfile[256];\n\nvoid        usage(void);\nvoid        getopts(int *pac, char ***pav);\nint         convbdf(char *path);\n\nvoid        free_font(font_t *pf);\nfont_t *    bdf_read_font(char *path);\nint         bdf_read_header(FILE *fp, font_t *pf);\nint         bdf_read_bitmaps(FILE *fp, font_t *pf);\nchar *      bdf_getline(FILE *fp, char *buf, int len);\nunsigned short bdf_hexval(unsigned char *buf, int ndx1, int ndx2);\n\nint         gen_c_source(font_t *pf, char *path);\n\nvoid\nusage(void)\n{\n    fprintf (stderr,\n    \"Usage: convbdf [options] [input-files]\\n\"\n    \"Options:\\n\"\n    \"    -s N   Start output at character encodings >= N\\n\"\n    \"    -l N   Limit output to character encodings <= N\\n\"\n    \"    -x N-M Exclude character range N...M\\n\"\n    \"    -u N   Use code N as default char \\n\"\n    \"    -a N   Decrease ascent by N\\n\"\n    \"    -d N   Decrease descent by N\\n\"\n    \"    -n     Don't generate bitmaps as comments in .c file\\n\"\n    );\n}\n\n/*\n * parse command line options\n */\nvoid\ngetopts(int *pac, char ***pav)\n{\n    char *p;\n    char **av;\n    int ac;\n\n    ac = *pac;\n    av = *pav;\n    while (ac > 0 && av[0][0] == '-') {\n        p = &av[0][1];\n        while( *p)\n            switch(*p++) {\n        case ' ':               /* multiple -args on av[]*/\n            while( *p && *p == ' ')\n                p++;\n            if( *p++ != '-')    /* next option must have dash*/\n                p = \"\";\n            break;              /* proceed to next option*/\n        case 'n':               /* don't gen bitmap comments*/\n            gen_map = 0;\n            break;\n        case 'l':               /* set encoding limit */\n            if (*p) {\n                limit_char = strtol (p, 0, 0);\n                while (*p && *p != ' ')\n                    p++;\n            } else {\n                av++; ac--;\n                if (ac > 0)\n                    limit_char = strtol (av[0], 0, 0);\n            }\n            break;\n        case 'x':               /* exclude encoding range */\n            if (*p) {\n                char *e;\n                exclude_start = strtol (p, &e, 0);\n                if (*e != '-') {\n                    fprintf(stderr, \"Invalud option ignored: %s\\r\\n\", p);\n                    exclude_start = 0;\n                    break;\n                }\n                exclude_end = strtol (e+1, 0, 0);\n                while (*p && *p != ' ')\n                    p++;\n            } else {\n                av++; ac--;\n                if (ac > 0) {\n                    char *e;\n                    exclude_start = strtol (av[0], &e, 0);\n                    if (*e != '-') {\n                        fprintf(stderr, \"Invalud option ignored: %s\\r\\n\", av[0]);\n                        exclude_start = 0;\n                        break;\n                    }\n                    exclude_end = strtol (e+1, 0, 0);\n                }\n            }\n            break;\n        case 's':               /* set encoding start */\n            if (*p) {\n                start_char = strtol (p, 0, 0);\n                while (*p && *p != ' ')\n                    p++;\n            } else {\n                av++; ac--;\n                if (ac > 0)\n                    start_char = strtol (av[0], 0, 0);\n            }\n            break;\n        case 'a':               /* ascent correction */\n            if (*p) {\n                ascent_correction = strtol (p, 0, 0);\n                while (*p && *p != ' ')\n                    p++;\n            } else {\n                av++; ac--;\n                if (ac > 0)\n                    ascent_correction = strtol (av[0], 0, 0);\n            }\n            break;\n        case 'd':               /* descent correction */\n            if (*p) {\n                descent_correction = strtol (p, 0, 0);\n                while (*p && *p != ' ')\n                    p++;\n            } else {\n                av++; ac--;\n                if (ac > 0)\n                    descent_correction = strtol (av[0], 0, 0);\n            }\n            break;\n        case 'u':               /* unknown char */\n            if (*p) {\n                default_char = strtol (p, 0, 0);\n                while (*p && *p != ' ')\n                    p++;\n            } else {\n                av++; ac--;\n                if (ac > 0)\n                    default_char = strtol (av[0], 0, 0);\n            }\n            break;\n        default:\n            fprintf(stderr, \"Unknown option ignored: %c\\r\\n\", *(p-1));\n        }\n        ++av; --ac;\n    }\n    *pac = ac;\n    *pav = av;\n}\n\n/*\n * remove directory prefix and file suffix from full path\n */\nchar *\nbasename(char *path)\n{\n    char *p, *b;\n    static char base[256];\n\n    /* remove prepended path and extension*/\n    b = path;\n    for (p=path; *p; ++p) {\n        if (*p == '/')\n            b = p + 1;\n    }\n    strcpy(base, b);\n    for (p=base; *p; ++p) {\n        if (*p == '.') {\n            *p = 0;\n            break;\n        }\n    }\n    return base;\n}\n\nint\nconvbdf(char *path)\n{\n    font_t *pf;\n    int ret = 0;\n\n    pf = bdf_read_font(path);\n    if (!pf)\n        exit(1);\n\n    strcpy(outfile, basename(path));\n    strcat(outfile, \".c\");\n\n    ret |= gen_c_source(pf, outfile);\n\n    free_font(pf);\n    return ret;\n}\n\nint\nmain(int ac, char **av)\n{\n    int ret = 0;\n\n    ++av; --ac;         /* skip av[0] */\n    getopts(&ac, &av);  /* read command line options */\n\n    if (ac < 1) {\n        usage();\n        exit(1);\n    }\n\n    while (ac > 0) {\n        ret |= convbdf(av[0]);\n        ++av; --ac;\n    }\n\n    exit(ret);\n}\n\n/*\n * free font structure\n */\nvoid\nfree_font(font_t *pf)\n{\n    if (!pf)\n        return;\n    if (pf->name)\n        free(pf->name);\n    if (pf->facename)\n        free(pf->facename);\n    if (pf->bits)\n        free(pf->bits);\n    if (pf->offset)\n        free(pf->offset);\n    if (pf->width)\n        free(pf->width);\n    free(pf);\n}\n\n/*\n * build incore structure from .bdf file\n */\nfont_t *\nbdf_read_font(char *path)\n{\n    FILE *fp;\n    font_t *pf;\n\n    fp = fopen(path, \"rb\");\n    if (!fp) {\n        fprintf(stderr, \"Error opening file: %s\\n\", path);\n        return NULL;\n    }\n\n    pf = (font_t *) calloc(1, sizeof(font_t));\n    if (!pf)\n        goto errout;\n\n    pf->name = strdup(basename(path));\n\n    if (!bdf_read_header(fp, pf)) {\n        fprintf(stderr, \"Error reading font header\\n\");\n        goto errout;\n    }\n\n    if (!bdf_read_bitmaps(fp, pf)) {\n        fprintf(stderr, \"Error reading font bitmaps\\n\");\n        goto errout;\n    }\n\n    fclose(fp);\n    return pf;\n\nerrout:\n    fclose(fp);\n    free_font(pf);\n    return NULL;\n}\n\n/*\n * read bdf font header information, return 0 on error\n */\nint\nbdf_read_header(FILE *fp, font_t *pf)\n{\n    int encoding;\n    int nchars, maxwidth = 0;\n    int firstchar = 65535;\n    int lastchar = -1;\n    char buf[256];\n    char facename[256];\n    char copyright[256];\n\n    /* set certain values to errors for later error checking*/\n    pf->defaultchar = -1;\n    pf->ascent = -1;\n    pf->descent = -1;\n\n    for (;;) {\n        if (!bdf_getline(fp, buf, sizeof(buf))) {\n            fprintf(stderr, \"Error: EOF on file\\n\");\n            return 0;\n        }\n        if (isprefix(buf, \"FONT \")) {       /* not required*/\n            if (sscanf(buf, \"FONT %[^\\n]\", facename) != 1) {\n                fprintf(stderr, \"Error: bad 'FONT'\\n\");\n                return 0;\n            }\n            pf->facename = strdup(facename);\n            continue;\n        }\n        if (isprefix(buf, \"COPYRIGHT \")) {  /* not required*/\n            if (sscanf(buf, \"COPYRIGHT \\\"%[^\\\"]\", copyright) != 1) {\n                fprintf(stderr, \"Error: bad 'COPYRIGHT'\\n\");\n                return 0;\n            }\n            pf->copyright = strdup(copyright);\n            continue;\n        }\n        if (isprefix(buf, \"DEFAULT_CHAR \")) {   /* not required*/\n            if (sscanf(buf, \"DEFAULT_CHAR %d\", &pf->defaultchar) != 1) {\n                fprintf(stderr, \"Error: bad 'DEFAULT_CHAR'\\n\");\n                return 0;\n            }\n        }\n        if (isprefix(buf, \"FONT_DESCENT \")) {\n            if (sscanf(buf, \"FONT_DESCENT %d\", &pf->descent) != 1) {\n                fprintf(stderr, \"Error: bad 'FONT_DESCENT'\\n\");\n                return 0;\n            }\n            continue;\n        }\n        if (isprefix(buf, \"FONT_ASCENT \")) {\n            if (sscanf(buf, \"FONT_ASCENT %d\", &pf->ascent) != 1) {\n                fprintf(stderr, \"Error: bad 'FONT_ASCENT'\\n\");\n                return 0;\n            }\n            continue;\n        }\n        if (isprefix(buf, \"FONTBOUNDINGBOX \")) {\n            if (sscanf(buf, \"FONTBOUNDINGBOX %d %d %d %d\",\n                &pf->fbbw, &pf->fbbh, &pf->fbbx, &pf->fbby) != 4) {\n                fprintf(stderr, \"Error: bad 'FONTBOUNDINGBOX'\\n\");\n                return 0;\n            }\n            continue;\n        }\n        if (isprefix(buf, \"CHARS \")) {\n            if (sscanf(buf, \"CHARS %d\", &nchars) != 1) {\n                fprintf(stderr, \"Error: bad 'CHARS'\\n\");\n                return 0;\n            }\n            continue;\n        }\n\n        /*\n         * Reading ENCODING is necessary to get firstchar/lastchar\n         * which is needed to pre-calculate our offset and widths\n         * array sizes.\n         */\n        if (isprefix(buf, \"ENCODING \")) {\n            if (sscanf(buf, \"ENCODING %d\", &encoding) != 1) {\n                fprintf(stderr, \"Error: bad 'ENCODING'\\n\");\n                return 0;\n            }\n            if (encoding > limit_char || encoding < start_char)\n                continue;\n            if (exclude_start && encoding >= exclude_start && encoding <= exclude_end)\n                continue;\n            if (firstchar > encoding)\n                firstchar = encoding;\n            if (lastchar < encoding)\n                lastchar = encoding;\n            continue;\n        }\n        if (isprefix(buf, \"DWIDTH \")) {\n            int width;\n            if (sscanf(buf, \"DWIDTH %d\", &width) != 1) {\n                fprintf(stderr, \"Error: bad 'DWIDTH' for encoding %d\\n\",\n                    encoding);\n                return 0;\n            }\n            if (maxwidth < width)\n                maxwidth = width;\n            continue;\n        }\n        if (strequal(buf, \"ENDFONT\"))\n            break;\n    }\n\n    /* calc font height*/\n    if (pf->ascent < 0 || pf->descent < 0 || firstchar < 0) {\n        fprintf(stderr, \"Error: Invalid BDF file, requires FONT_ASCENT/FONT_DESCENT/ENCODING\\n\");\n        return 0;\n    }\n    pf->height = pf->ascent + pf->descent;\n\n    /* calc default char*/\n    if (default_char)\n        pf->defaultchar = default_char;\n    if (pf->defaultchar < 0 || pf->defaultchar < firstchar ||\n        pf->defaultchar > limit_char)\n        pf->defaultchar = firstchar;\n\n    /* calc font size (offset/width entries)*/\n    pf->firstchar = firstchar;\n    pf->size = lastchar - firstchar + 1;\n\n    /* initially use font maxwidth * height for bits allocation*/\n    pf->bits_size = nchars * WORDS(maxwidth) * pf->height;\n\n    /* allocate bits, offset, and width arrays*/\n    pf->bits = (unsigned short*) malloc(pf->bits_size * sizeof(unsigned short) + EXTRA);\n    pf->offset = (unsigned long*) malloc(pf->size * sizeof(unsigned long));\n    pf->width = (unsigned char*) malloc(pf->size * sizeof(unsigned char));\n\n    if (!pf->bits || !pf->offset || !pf->width) {\n        fprintf(stderr, \"Error: no memory for font load\\n\");\n        return 0;\n    }\n\n    return 1;\n}\n\n/*\n * read bdf font bitmaps, return 0 on error\n */\nint\nbdf_read_bitmaps(FILE *fp, font_t *pf)\n{\n    long ofs = 0;\n    int maxwidth = 0;\n    int i, k, encoding, width;\n    int bbw, bbh, bbx, bby;\n    int proportional = 0;\n    int encodetable = 0;\n    long l;\n    char buf[256];\n\n    /* reset file pointer*/\n    fseek(fp, 0L, SEEK_SET);\n\n    /* initially mark offsets as not used*/\n    for (i=0; i<pf->size; ++i)\n        pf->offset[i] = -1;\n\n    for (;;) {\n        if (!bdf_getline(fp, buf, sizeof(buf))) {\n            fprintf(stderr, \"Error: EOF on file\\n\");\n            return 0;\n        }\n        if (isprefix(buf, \"STARTCHAR\")) {\n            encoding = width = bbw = bbh = bbx = bby = -1;\n            continue;\n        }\n        if (isprefix(buf, \"ENCODING \")) {\n            if (sscanf(buf, \"ENCODING %d\", &encoding) != 1) {\n                fprintf(stderr, \"Error: bad 'ENCODING'\\n\");\n                return 0;\n            }\n            if (encoding < start_char || encoding > limit_char)\n                encoding = -1;\n            if (exclude_start && encoding >= exclude_start && encoding <= exclude_end)\n                encoding = -1;\n            continue;\n        }\n        if (isprefix(buf, \"DWIDTH \")) {\n            if (sscanf(buf, \"DWIDTH %d\", &width) != 1) {\n                fprintf(stderr, \"Error: bad 'DWIDTH'\\n\");\n                return 0;\n            }\n            /* use font boundingbox width if DWIDTH <= 0*/\n            if (width <= 0)\n                width = pf->fbbw - pf->fbbx;\n            continue;\n        }\n        if (isprefix(buf, \"BBX \")) {\n            if (sscanf(buf, \"BBX %d %d %d %d\", &bbw, &bbh, &bbx, &bby) != 4) {\n                fprintf(stderr, \"Error: bad 'BBX'\\n\");\n                return 0;\n            }\n            continue;\n        }\n        if (strequal(buf, \"BITMAP\")) {\n            unsigned short *ch_bitmap = pf->bits + ofs;\n            int ch_words;\n\n            if (encoding < 0)\n                continue;\n\n            /* set bits offset in encode map*/\n            if (pf->offset[encoding-pf->firstchar] != (unsigned long)-1) {\n                fprintf(stderr, \"Error: duplicate encoding for character %d (0x%02x), ignoring duplicate\\n\",\n                    encoding, encoding);\n                continue;\n            }\n            pf->offset[encoding-pf->firstchar] = ofs;\n\n            /* calc char width*/\n            if (bbx < 0) {\n                width -= bbx;\n                /*if (width > maxwidth)\n                    width = maxwidth;*/\n                bbx = 0;\n            }\n            if (width > maxwidth)\n                maxwidth = width;\n            pf->width[encoding-pf->firstchar] = width;\n\n            /* clear bitmap*/\n            memset(ch_bitmap, 0, BYTES(width) * pf->height);\n\n            ch_words = WORDS(width);\n#define BM(row,col) (*(ch_bitmap + ((row)*ch_words) + (col)))\n\n            /* read bitmaps*/\n            for (i=0; ; ++i) {\n                int hexnibbles;\n\n                if (!bdf_getline(fp, buf, sizeof(buf))) {\n                    fprintf(stderr, \"Error: EOF reading BITMAP data\\n\");\n                    return 0;\n                }\n                if (isprefix(buf, \"ENDCHAR\"))\n                    break;\n\n                hexnibbles = strlen(buf);\n                for (k=0; k<ch_words; ++k) {\n                    int ndx = k * NIBBLES_PER_WORD;\n                    int padnibbles = hexnibbles - ndx;\n                    unsigned short value;\n\n                    if (padnibbles <= 0)\n                        break;\n                    if (padnibbles >= NIBBLES_PER_WORD)\n                        padnibbles = 0;\n\n                    value = bdf_hexval((unsigned char *)buf,\n                        ndx, ndx+NIBBLES_PER_WORD-1-padnibbles);\n                    value <<= padnibbles * NIBBLES_PER_WORD;\n\n                    BM(pf->height - pf->descent - bby - bbh + i, k) |=\n                        value >> bbx;\n                    /* handle overflow into next image word*/\n                    if (bbx) {\n                        BM(pf->height - pf->descent - bby - bbh + i, k+1) =\n                            value << (BITS_PER_WORD - bbx);\n                    }\n                }\n            }\n\n            ofs += WORDS(width) * pf->height;\n\n            continue;\n        }\n        if (strequal(buf, \"ENDFONT\"))\n            break;\n    }\n\n    /* set max width*/\n    pf->maxwidth = maxwidth;\n\n    /* change unused offset/width values to default char values*/\n    for (i=0; i<pf->size; ++i) {\n        int defchar = pf->defaultchar - pf->firstchar;\n\n        if (pf->offset[i] == (unsigned long)-1) {\n            pf->offset[i] = pf->offset[defchar];\n            pf->width[i] = pf->width[defchar];\n        }\n    }\n\n    /* determine whether font doesn't require encode table*/\n    l = 0;\n    for (i=0; i<pf->size; ++i) {\n        if (pf->offset[i] != l) {\n            encodetable = 1;\n            break;\n        }\n        l += WORDS(pf->width[i]) * pf->height;\n    }\n    if (!encodetable) {\n        free(pf->offset);\n        pf->offset = NULL;\n    }\n\n    /* determine whether font is fixed-width*/\n    for (i=0; i<pf->size; ++i) {\n        if (pf->width[i] != maxwidth) {\n            proportional = 1;\n            break;\n        }\n    }\n    if (!proportional) {\n        free(pf->width);\n        pf->width = NULL;\n    }\n\n    /* reallocate bits array to actual bits used*/\n    if (ofs < pf->bits_size) {\n        pf->bits = realloc(pf->bits, ofs * sizeof(unsigned short));\n        pf->bits_size = ofs;\n    } else if (ofs > pf->bits_size) {\n        fprintf(stderr, \"Warning: DWIDTH spec > max FONTBOUNDINGBOX\\n\");\n        if (ofs > pf->bits_size+EXTRA) {\n            fprintf(stderr, \"Error: Not enough bits initially allocated\\n\");\n            return 0;\n        }\n        pf->bits_size = ofs;\n    }\n\n    return 1;\n}\n\n/*\n * read the next non-comment line, returns buf or NULL if EOF\n */\nchar *\nbdf_getline(FILE *fp, char *buf, int len)\n{\n    int c;\n    char *b;\n\n    for (;;) {\n        b = buf;\n        while ((c = getc(fp)) != EOF) {\n            if (c == '\\r')\n                continue;\n            if (c == '\\n')\n                break;\n            if (b - buf >= (len - 1))\n                break;\n            *b++ = c;\n        }\n        *b = '\\0';\n        if (c == EOF && b == buf)\n            return NULL;\n        if (b != buf && !isprefix(buf, \"COMMENT\"))\n            break;\n    }\n    return buf;\n}\n\n/*\n * return hex value of portion of buffer\n */\nunsigned short\nbdf_hexval(unsigned char *buf, int ndx1, int ndx2)\n{\n    unsigned short val = 0;\n    int i, c;\n\n    for (i=ndx1; i<=ndx2; ++i) {\n        c = buf[i];\n        if (c >= '0' && c <= '9')\n            c -= '0';\n        else if (c >= 'A' && c <= 'F')\n            c = c - 'A' + 10;\n        else if (c >= 'a' && c <= 'f')\n            c = c - 'a' + 10;\n        else c = 0;\n        val = (val << 4) | c;\n    }\n    return val;\n}\n\n/*\n * generate C source from in-core font\n */\nint\ngen_c_source(font_t *pf, char *path)\n{\n    FILE *ofp;\n    int i;\n    int did_defaultchar = 0;\n    time_t t = time(0);\n    char buf[256];\n    char obuf[256];\n    char hdr1[] = {\n        \"/* Generated by convbdf on %s. */\\n\"\n        \"#include <sys/gpanel.h>\\n\"\n        \"\\n\"\n        \"/* Font information:\\n\"\n        \"   name: %s\\n\"\n        \"   facename: %s\\n\"\n        \"   w x h: %dx%d\\n\"\n        \"   size: %d\\n\"\n        \"   ascent: %d\\n\"\n        \"   descent: %d\\n\"\n        \"   first char: %d (0x%02x)\\n\"\n        \"   last char: %d (0x%02x)\\n\"\n        \"   default char: %d (0x%02x)\\n\"\n        \"   proportional: %s\\n\"\n        \"   %s\\n\"\n        \"*/\\n\"\n        \"\\n\"\n        \"/* Font character bitmap data. */\\n\"\n        \"static const unsigned short _%s_bits[] = {\\n\"\n    };\n\n    ofp = fopen(path, \"w\");\n    if (!ofp) {\n        fprintf(stderr, \"Can't create %s\\n\", path);\n        return 1;\n    }\n    fprintf(stderr, \"Generating %s\\n\", path);\n\n    strcpy(buf, ctime(&t));\n    buf[strlen(buf)-1] = 0;\n\n    fprintf(ofp, hdr1, buf,\n        pf->name,\n        pf->facename? pf->facename: \"\",\n        pf->maxwidth, pf->height - ascent_correction - descent_correction,\n        pf->size,\n        pf->ascent - ascent_correction, pf->descent - descent_correction,\n        pf->firstchar, pf->firstchar,\n        pf->firstchar+pf->size-1, pf->firstchar+pf->size-1,\n        pf->defaultchar, pf->defaultchar,\n        pf->width? \"yes\": \"no\",\n        pf->copyright? pf->copyright: \"\",\n        pf->name);\n\n    /* generate bitmaps*/\n    for (i=0; i<pf->size; ++i) {\n        int x;\n        int bitcount = 0;\n        int width = pf->width ? pf->width[i] : pf->maxwidth;\n        int height = pf->height - ascent_correction - descent_correction;\n        unsigned short *bits = pf->bits + (pf->offset? pf->offset[i]: (pf->height * i));\n        unsigned short bitvalue = 0;\n\n        /*\n         * Generate bitmap bits only if not this index isn't\n         * the default character in encode map, or the default\n         * character hasn't been generated yet.\n         */\n        if (pf->offset && (pf->offset[i] == pf->offset[pf->defaultchar-pf->firstchar])) {\n            if (did_defaultchar)\n                continue;\n            did_defaultchar = 1;\n        }\n\n        fprintf(ofp, \"\\n/* Character %d (0x%02x):\\n   width %d\",\n            i+pf->firstchar, i+pf->firstchar, width);\n\n        bits += WORDS(width) * ascent_correction;\n        if (gen_map) {\n            fprintf(ofp, \"\\n   +\");\n            for (x=0; x<width; ++x) fprintf(ofp, \"-\");\n            fprintf(ofp, \"+\\n\");\n\n            x = 0;\n            while (height > 0) {\n                if (x == 0) fprintf(ofp, \"   |\");\n\n                if (bitcount <= 0) {\n                    bitcount = BITS_PER_WORD;\n                    bitvalue = *bits++;\n                }\n\n                fprintf(ofp, TEST_HIGH_BIT(bitvalue)? \"*\": \" \");\n\n                bitvalue <<= 1;\n                --bitcount;\n                if (++x == width) {\n                    fprintf(ofp, \"|\\n\");\n                    --height;\n                    x = 0;\n                    bitcount = 0;\n                }\n            }\n            fprintf(ofp, \"   +\");\n            for (x=0; x<width; ++x) fprintf(ofp, \"-\");\n            fprintf(ofp, \"+ */\\n\");\n        } else\n            fprintf(ofp, \" */\\n\");\n\n        bits = pf->bits + (pf->offset? pf->offset[i]: (pf->height * i));\n        bits += WORDS(width) * ascent_correction;\n        height = pf->height - ascent_correction - descent_correction;\n        for (; height>0; --height) {\n            for (x=WORDS(width); x>0; --x) {\n                fprintf(ofp, \"0x%04x,\", *bits++);\n            }\n            fprintf(ofp, \"\\n\");\n        }\n    }\n    fprintf(ofp,    \"};\\n\\n\");\n\n    if (pf->offset) {\n        long offset, default_offset;\n\n        /* output offset table*/\n        fprintf(ofp, \"/* Character->glyph mapping. */\\n\"\n            \"static const unsigned short _%s_offset[] = {\\n\",\n            pf->name);\n        offset = 0;\n        did_defaultchar = 0;\n        default_offset = 0;\n        for (i=0; i<pf->size; ++i) {\n            int width = pf->width ? pf->width[i] : pf->maxwidth;\n            if (pf->offset && (pf->offset[i] ==\n                pf->offset[pf->defaultchar-pf->firstchar])) {\n                if (did_defaultchar) {\n                    fprintf(ofp, \"  %ld,\\t/* (0x%02x) */\\n\",\n                        default_offset,\n                        i + pf->firstchar);\n                    continue;\n                }\n                did_defaultchar = 1;\n                default_offset = offset;\n            }\n            fprintf(ofp, \"  %ld,\\t/* (0x%02x) */\\n\", offset,\n                i + pf->firstchar);\n            offset += WORDS(width) * (pf->height - ascent_correction -\n                descent_correction);\n        }\n        fprintf(ofp, \"};\\n\\n\");\n    }\n\n    /* output width table for proportional fonts*/\n    if (pf->width) {\n        fprintf(ofp,    \"/* Character width data. */\\n\"\n            \"static const unsigned char _%s_width[] = {\\n\",\n            pf->name);\n\n        for (i=0; i<pf->size; ++i)\n            fprintf(ofp, \"  %d,\\t/* (0x%02x) */\\n\",\n                pf->width[i], i+pf->firstchar);\n        fprintf(ofp, \"};\\n\\n\");\n    }\n\n    /* output font_t struct*/\n    if (pf->offset)\n        sprintf(obuf, \"_%s_offset,\", pf->name);\n    else sprintf(obuf, \"0,  /* no encode table*/\");\n    if (pf->width)\n        sprintf(buf, \"_%s_width,\", pf->name);\n    else sprintf(buf, \"0,  /* fixed width*/\");\n    fprintf(ofp,    \"/* Exported structure definition. */\\n\"\n        \"const struct gpanel_font_t font_%s = {\\n\"\n        \"  \\\"%s\\\",\\n\"\n        \"  %d,\\n\"\n        \"  %d,\\n\"\n        \"  %d,\\n\"\n        \"  %d,\\n\"\n        \"  %d,\\n\"\n        \"  _%s_bits,\\n\"\n        \"  %s\\n\"\n        \"  %s\\n\"\n        \"  %d,\\n\"\n        \"  sizeof(_%s_bits) / sizeof(_%s_bits[0]),\\n\"\n        \"};\\n\",\n        pf->name, pf->name,\n        pf->maxwidth, pf->height - ascent_correction - descent_correction,\n        pf->ascent - ascent_correction,\n        pf->firstchar,\n        pf->size,\n        pf->name,\n        obuf,\n        buf,\n        pf->defaultchar,\n        pf->name, pf->name);\n\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/gpanel/fonts/digits20.c",
    "content": "/* Generated by convbdf on Thu Oct  8 21:26:34 2015. */\n#include <sys/gpanel.h>\n\n/* Font information:\n   name: digits20\n   facename: -FreeType-Lucida Sans Unicode-Medium-R-Normal--28-200-100-100-P-111-ISO10646-1\n   w x h: 18x22\n   size: 27\n   ascent: 21\n   descent: 1\n   first char: 32 (0x20)\n   last char: 58 (0x3a)\n   default char: 32 (0x20)\n   proportional: yes\n   Copyright  1993 Bigelow & Holmes Inc. All rights reserved. Pat. Des. 289,420. Pats. Pend.\n*/\n\n/* Font character bitmap data. */\nstatic const unsigned short _digits20_bits[] = {\n\n/* Character 32 (0x20):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 48 (0x30):\n   width 18\n   +------------------+\n   |                  |\n   |       ****       |\n   |     ********     |\n   |    ***    ***    |\n   |   ***      ***   |\n   |   ***      ***   |\n   |   **        **   |\n   |  ***        ***  |\n   |  ***        ***  |\n   |  ***        ***  |\n   |  ***        ***  |\n   |  ***        ***  |\n   |  ***        ***  |\n   |  ***        ***  |\n   |  ***        ***  |\n   |   **        **   |\n   |   ***      ***   |\n   |   ***      ***   |\n   |    ***    ***    |\n   |     ********     |\n   |       ****       |\n   |                  |\n   +------------------+ */\n0x0000,0x0000,\n0x01e0,0x0000,\n0x07f8,0x0000,\n0x0e1c,0x0000,\n0x1c0e,0x0000,\n0x1c0e,0x0000,\n0x1806,0x0000,\n0x3807,0x0000,\n0x3807,0x0000,\n0x3807,0x0000,\n0x3807,0x0000,\n0x3807,0x0000,\n0x3807,0x0000,\n0x3807,0x0000,\n0x3807,0x0000,\n0x1806,0x0000,\n0x1c0e,0x0000,\n0x1c0e,0x0000,\n0x0e1c,0x0000,\n0x07f8,0x0000,\n0x01e0,0x0000,\n0x0000,0x0000,\n\n/* Character 49 (0x31):\n   width 18\n   +------------------+\n   |                  |\n   |       ***        |\n   |    ******        |\n   |    ******        |\n   |       ***        |\n   |       ***        |\n   |       ***        |\n   |       ***        |\n   |       ***        |\n   |       ***        |\n   |       ***        |\n   |       ***        |\n   |       ***        |\n   |       ***        |\n   |       ***        |\n   |       ***        |\n   |       ***        |\n   |       ***        |\n   |       ***        |\n   |       ***        |\n   |       ***        |\n   |                  |\n   +------------------+ */\n0x0000,0x0000,\n0x01c0,0x0000,\n0x0fc0,0x0000,\n0x0fc0,0x0000,\n0x01c0,0x0000,\n0x01c0,0x0000,\n0x01c0,0x0000,\n0x01c0,0x0000,\n0x01c0,0x0000,\n0x01c0,0x0000,\n0x01c0,0x0000,\n0x01c0,0x0000,\n0x01c0,0x0000,\n0x01c0,0x0000,\n0x01c0,0x0000,\n0x01c0,0x0000,\n0x01c0,0x0000,\n0x01c0,0x0000,\n0x01c0,0x0000,\n0x01c0,0x0000,\n0x01c0,0x0000,\n0x0000,0x0000,\n\n/* Character 50 (0x32):\n   width 18\n   +------------------+\n   |                  |\n   |    *******       |\n   |   *********      |\n   |   *     ****     |\n   |           ***    |\n   |           ***    |\n   |           ***    |\n   |           ***    |\n   |           ***    |\n   |          ***     |\n   |         ***      |\n   |        ***       |\n   |       ***        |\n   |      ***         |\n   |     ***          |\n   |    ***           |\n   |   ***            |\n   |   ***            |\n   |  ***             |\n   |  ************    |\n   |  ************    |\n   |                  |\n   +------------------+ */\n0x0000,0x0000,\n0x0fe0,0x0000,\n0x1ff0,0x0000,\n0x1078,0x0000,\n0x001c,0x0000,\n0x001c,0x0000,\n0x001c,0x0000,\n0x001c,0x0000,\n0x001c,0x0000,\n0x0038,0x0000,\n0x0070,0x0000,\n0x00e0,0x0000,\n0x01c0,0x0000,\n0x0380,0x0000,\n0x0700,0x0000,\n0x0e00,0x0000,\n0x1c00,0x0000,\n0x1c00,0x0000,\n0x3800,0x0000,\n0x3ffc,0x0000,\n0x3ffc,0x0000,\n0x0000,0x0000,\n\n/* Character 51 (0x33):\n   width 18\n   +------------------+\n   |                  |\n   |    *******       |\n   |   **********     |\n   |   *      ***     |\n   |           ***    |\n   |           ***    |\n   |           ***    |\n   |           ***    |\n   |          ***     |\n   |         ***      |\n   |     ******       |\n   |     *******      |\n   |          ****    |\n   |           ****   |\n   |            ***   |\n   |            ***   |\n   |            ***   |\n   |           ****   |\n   |   **     ****    |\n   |   **********     |\n   |     ******       |\n   |                  |\n   +------------------+ */\n0x0000,0x0000,\n0x0fe0,0x0000,\n0x1ff8,0x0000,\n0x1038,0x0000,\n0x001c,0x0000,\n0x001c,0x0000,\n0x001c,0x0000,\n0x001c,0x0000,\n0x0038,0x0000,\n0x0070,0x0000,\n0x07e0,0x0000,\n0x07f0,0x0000,\n0x003c,0x0000,\n0x001e,0x0000,\n0x000e,0x0000,\n0x000e,0x0000,\n0x000e,0x0000,\n0x001e,0x0000,\n0x183c,0x0000,\n0x1ff8,0x0000,\n0x07e0,0x0000,\n0x0000,0x0000,\n\n/* Character 52 (0x34):\n   width 18\n   +------------------+\n   |                  |\n   |          ***     |\n   |         ****     |\n   |        *****     |\n   |       ******     |\n   |       ** ***     |\n   |      **  ***     |\n   |     ***  ***     |\n   |    ***   ***     |\n   |    **    ***     |\n   |   **     ***     |\n   |  ***     ***     |\n   | ***      ***     |\n   | ***************  |\n   | ***************  |\n   |          ***     |\n   |          ***     |\n   |          ***     |\n   |          ***     |\n   |          ***     |\n   |          ***     |\n   |                  |\n   +------------------+ */\n0x0000,0x0000,\n0x0038,0x0000,\n0x0078,0x0000,\n0x00f8,0x0000,\n0x01f8,0x0000,\n0x01b8,0x0000,\n0x0338,0x0000,\n0x0738,0x0000,\n0x0e38,0x0000,\n0x0c38,0x0000,\n0x1838,0x0000,\n0x3838,0x0000,\n0x7038,0x0000,\n0x7fff,0x0000,\n0x7fff,0x0000,\n0x0038,0x0000,\n0x0038,0x0000,\n0x0038,0x0000,\n0x0038,0x0000,\n0x0038,0x0000,\n0x0038,0x0000,\n0x0000,0x0000,\n\n/* Character 53 (0x35):\n   width 18\n   +------------------+\n   |                  |\n   |   ***********    |\n   |   ***********    |\n   |   ***            |\n   |   ***            |\n   |   ***            |\n   |   ***            |\n   |   ***            |\n   |   ******         |\n   |   ********       |\n   |        *****     |\n   |          ***     |\n   |           ***    |\n   |           ***    |\n   |           ***    |\n   |           ***    |\n   |           ***    |\n   |          ***     |\n   |         ****     |\n   |   *********      |\n   |   *******        |\n   |                  |\n   +------------------+ */\n0x0000,0x0000,\n0x1ffc,0x0000,\n0x1ffc,0x0000,\n0x1c00,0x0000,\n0x1c00,0x0000,\n0x1c00,0x0000,\n0x1c00,0x0000,\n0x1c00,0x0000,\n0x1f80,0x0000,\n0x1fe0,0x0000,\n0x00f8,0x0000,\n0x0038,0x0000,\n0x001c,0x0000,\n0x001c,0x0000,\n0x001c,0x0000,\n0x001c,0x0000,\n0x001c,0x0000,\n0x0038,0x0000,\n0x0078,0x0000,\n0x1ff0,0x0000,\n0x1fc0,0x0000,\n0x0000,0x0000,\n\n/* Character 54 (0x36):\n   width 18\n   +------------------+\n   |                  |\n   |       ******     |\n   |     **********   |\n   |    ****     **   |\n   |    ***           |\n   |   ***            |\n   |   ***            |\n   |  ***             |\n   |  ***  *****      |\n   |  *** ********    |\n   |  *****    ****   |\n   |  ****      ***   |\n   |  ***        ***  |\n   |  ***        ***  |\n   |  ***        ***  |\n   |  ***        ***  |\n   |   ***       ***  |\n   |   ***      ***   |\n   |    ***    ****   |\n   |     *********    |\n   |       *****      |\n   |                  |\n   +------------------+ */\n0x0000,0x0000,\n0x01f8,0x0000,\n0x07fe,0x0000,\n0x0f06,0x0000,\n0x0e00,0x0000,\n0x1c00,0x0000,\n0x1c00,0x0000,\n0x3800,0x0000,\n0x39f0,0x0000,\n0x3bfc,0x0000,\n0x3e1e,0x0000,\n0x3c0e,0x0000,\n0x3807,0x0000,\n0x3807,0x0000,\n0x3807,0x0000,\n0x3807,0x0000,\n0x1c07,0x0000,\n0x1c0e,0x0000,\n0x0e1e,0x0000,\n0x07fc,0x0000,\n0x01f0,0x0000,\n0x0000,0x0000,\n\n/* Character 55 (0x37):\n   width 18\n   +------------------+\n   |                  |\n   |   *************  |\n   |   *************  |\n   |             ***  |\n   |            ***   |\n   |           ***    |\n   |           ***    |\n   |          ***     |\n   |          **      |\n   |         ***      |\n   |         **       |\n   |        ***       |\n   |       ***        |\n   |       ***        |\n   |      ***         |\n   |      ***         |\n   |     ***          |\n   |     ***          |\n   |     ***          |\n   |    ***           |\n   |    ***           |\n   |                  |\n   +------------------+ */\n0x0000,0x0000,\n0x1fff,0x0000,\n0x1fff,0x0000,\n0x0007,0x0000,\n0x000e,0x0000,\n0x001c,0x0000,\n0x001c,0x0000,\n0x0038,0x0000,\n0x0030,0x0000,\n0x0070,0x0000,\n0x0060,0x0000,\n0x00e0,0x0000,\n0x01c0,0x0000,\n0x01c0,0x0000,\n0x0380,0x0000,\n0x0380,0x0000,\n0x0700,0x0000,\n0x0700,0x0000,\n0x0700,0x0000,\n0x0e00,0x0000,\n0x0e00,0x0000,\n0x0000,0x0000,\n\n/* Character 56 (0x38):\n   width 18\n   +------------------+\n   |                  |\n   |      ******      |\n   |     *********    |\n   |    ***    ****   |\n   |   ***      ***   |\n   |   ***      ***   |\n   |   ***      ***   |\n   |   ****    ***    |\n   |    ****   ***    |\n   |     *******      |\n   |     *******      |\n   |    *** ******    |\n   |   ***    *****   |\n   |   **       ***   |\n   |  ***        ***  |\n   |  ***        ***  |\n   |  ***        ***  |\n   |  ****       ***  |\n   |   ****    ****   |\n   |    **********    |\n   |      ******      |\n   |                  |\n   +------------------+ */\n0x0000,0x0000,\n0x03f0,0x0000,\n0x07fc,0x0000,\n0x0e1e,0x0000,\n0x1c0e,0x0000,\n0x1c0e,0x0000,\n0x1c0e,0x0000,\n0x1e1c,0x0000,\n0x0f1c,0x0000,\n0x07f0,0x0000,\n0x07f0,0x0000,\n0x0efc,0x0000,\n0x1c3e,0x0000,\n0x180e,0x0000,\n0x3807,0x0000,\n0x3807,0x0000,\n0x3807,0x0000,\n0x3c07,0x0000,\n0x1e1e,0x0000,\n0x0ffc,0x0000,\n0x03f0,0x0000,\n0x0000,0x0000,\n\n/* Character 57 (0x39):\n   width 18\n   +------------------+\n   |                  |\n   |      *****       |\n   |    *********     |\n   |   ****    ***    |\n   |   ***      ***   |\n   |  ***       ***   |\n   |  ***        ***  |\n   |  ***        ***  |\n   |  ***        ***  |\n   |  ***        ***  |\n   |   ***      ****  |\n   |   ****    *****  |\n   |    ******** ***  |\n   |      *****  ***  |\n   |             **   |\n   |            ***   |\n   |            ***   |\n   |           ***    |\n   |   **     ***     |\n   |   *********      |\n   |    ******        |\n   |                  |\n   +------------------+ */\n0x0000,0x0000,\n0x03e0,0x0000,\n0x0ff8,0x0000,\n0x1e1c,0x0000,\n0x1c0e,0x0000,\n0x380e,0x0000,\n0x3807,0x0000,\n0x3807,0x0000,\n0x3807,0x0000,\n0x3807,0x0000,\n0x1c0f,0x0000,\n0x1e1f,0x0000,\n0x0ff7,0x0000,\n0x03e7,0x0000,\n0x0006,0x0000,\n0x000e,0x0000,\n0x000e,0x0000,\n0x001c,0x0000,\n0x1838,0x0000,\n0x1ff0,0x0000,\n0x0fc0,0x0000,\n0x0000,0x0000,\n\n/* Character 58 (0x3a):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |   ***   |\n   |   ***   |\n   |   ***   |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |   ***   |\n   |   ***   |\n   |   ***   |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x1c00,\n0x1c00,\n0x1c00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x1c00,\n0x1c00,\n0x1c00,\n0x0000,\n};\n\n/* Character->glyph mapping. */\nstatic const unsigned short _digits20_offset[] = {\n  0,\t/* (0x20) */\n  0,\t/* (0x21) */\n  0,\t/* (0x22) */\n  0,\t/* (0x23) */\n  0,\t/* (0x24) */\n  0,\t/* (0x25) */\n  0,\t/* (0x26) */\n  0,\t/* (0x27) */\n  0,\t/* (0x28) */\n  0,\t/* (0x29) */\n  0,\t/* (0x2a) */\n  0,\t/* (0x2b) */\n  0,\t/* (0x2c) */\n  0,\t/* (0x2d) */\n  0,\t/* (0x2e) */\n  0,\t/* (0x2f) */\n  22,\t/* (0x30) */\n  66,\t/* (0x31) */\n  110,\t/* (0x32) */\n  154,\t/* (0x33) */\n  198,\t/* (0x34) */\n  242,\t/* (0x35) */\n  286,\t/* (0x36) */\n  330,\t/* (0x37) */\n  374,\t/* (0x38) */\n  418,\t/* (0x39) */\n  462,\t/* (0x3a) */\n};\n\n/* Character width data. */\nstatic const unsigned char _digits20_width[] = {\n  9,\t/* (0x20) */\n  9,\t/* (0x21) */\n  9,\t/* (0x22) */\n  9,\t/* (0x23) */\n  9,\t/* (0x24) */\n  9,\t/* (0x25) */\n  9,\t/* (0x26) */\n  9,\t/* (0x27) */\n  9,\t/* (0x28) */\n  9,\t/* (0x29) */\n  9,\t/* (0x2a) */\n  9,\t/* (0x2b) */\n  9,\t/* (0x2c) */\n  9,\t/* (0x2d) */\n  9,\t/* (0x2e) */\n  9,\t/* (0x2f) */\n  18,\t/* (0x30) */\n  18,\t/* (0x31) */\n  18,\t/* (0x32) */\n  18,\t/* (0x33) */\n  18,\t/* (0x34) */\n  18,\t/* (0x35) */\n  18,\t/* (0x36) */\n  18,\t/* (0x37) */\n  18,\t/* (0x38) */\n  18,\t/* (0x39) */\n  9,\t/* (0x3a) */\n};\n\n/* Exported structure definition. */\nconst struct gpanel_font_t font_digits20 = {\n  \"digits20\",\n  18,\n  22,\n  21,\n  32,\n  27,\n  _digits20_bits,\n  _digits20_offset,\n  _digits20_width,\n  32,\n  sizeof(_digits20_bits) / sizeof(_digits20_bits[0]),\n};\n"
  },
  {
    "path": "share/examples/gpanel/fonts/digits32.c",
    "content": "/* Generated by convbdf on Thu Oct  8 21:26:34 2015. */\n#include <sys/gpanel.h>\n\n/* Font information:\n   name: digits32\n   facename: -FreeType-Lucida Sans Unicode-Medium-R-Normal--44-320-100-100-P-170-ISO10646-1\n   w x h: 28x40\n   size: 27\n   ascent: 36\n   descent: 4\n   first char: 32 (0x20)\n   last char: 58 (0x3a)\n   default char: 32 (0x20)\n   proportional: yes\n   Copyright  1993 Bigelow & Holmes Inc. All rights reserved. Pat. Des. 289,420. Pats. Pend.\n*/\n\n/* Font character bitmap data. */\nstatic const unsigned short _digits32_bits[] = {\n\n/* Character 32 (0x20):\n   width 14\n   +--------------+\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   +--------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 48 (0x30):\n   width 28\n   +----------------------------+\n   |                            |\n   |                            |\n   |                            |\n   |           ******           |\n   |         **********         |\n   |        ************        |\n   |       *****    *****       |\n   |      *****      *****      |\n   |     *****        ****      |\n   |     ****         *****     |\n   |     ****          ****     |\n   |    *****          *****    |\n   |    *****          *****    |\n   |    ****            ****    |\n   |   *****            *****   |\n   |   *****            *****   |\n   |   *****            *****   |\n   |   *****            *****   |\n   |   *****            *****   |\n   |   *****            *****   |\n   |   *****            *****   |\n   |   *****            *****   |\n   |   *****            *****   |\n   |   *****            *****   |\n   |   *****            *****   |\n   |   *****            *****   |\n   |    ****            ****    |\n   |    *****          *****    |\n   |    *****          *****    |\n   |     ****          ****     |\n   |     ****         *****     |\n   |     *****        ****      |\n   |      *****      *****      |\n   |       *****    *****       |\n   |        ************        |\n   |         **********         |\n   |           ******           |\n   |                            |\n   |                            |\n   |                            |\n   +----------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x001f,0x8000,\n0x007f,0xe000,\n0x00ff,0xf000,\n0x01f0,0xf800,\n0x03e0,0x7c00,\n0x07c0,0x3c00,\n0x0780,0x3e00,\n0x0780,0x1e00,\n0x0f80,0x1f00,\n0x0f80,0x1f00,\n0x0f00,0x0f00,\n0x1f00,0x0f80,\n0x1f00,0x0f80,\n0x1f00,0x0f80,\n0x1f00,0x0f80,\n0x1f00,0x0f80,\n0x1f00,0x0f80,\n0x1f00,0x0f80,\n0x1f00,0x0f80,\n0x1f00,0x0f80,\n0x1f00,0x0f80,\n0x1f00,0x0f80,\n0x1f00,0x0f80,\n0x0f00,0x0f00,\n0x0f80,0x1f00,\n0x0f80,0x1f00,\n0x0780,0x1e00,\n0x0780,0x3e00,\n0x07c0,0x3c00,\n0x03e0,0x7c00,\n0x01f0,0xf800,\n0x00ff,0xf000,\n0x007f,0xe000,\n0x001f,0x8000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 49 (0x31):\n   width 28\n   +----------------------------+\n   |                            |\n   |                            |\n   |                            |\n   |                            |\n   |            *****           |\n   |        *********           |\n   |        *********           |\n   |        *********           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |            *****           |\n   |                            |\n   |                            |\n   |                            |\n   |                            |\n   +----------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x000f,0x8000,\n0x00ff,0x8000,\n0x00ff,0x8000,\n0x00ff,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x000f,0x8000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 50 (0x32):\n   width 28\n   +----------------------------+\n   |                            |\n   |                            |\n   |                            |\n   |         ********           |\n   |      *************         |\n   |     ***************        |\n   |     *****     ******       |\n   |     **         ******      |\n   |     *           *****      |\n   |                  *****     |\n   |                  *****     |\n   |                  *****     |\n   |                  *****     |\n   |                  *****     |\n   |                  *****     |\n   |                 *****      |\n   |                 *****      |\n   |                *****       |\n   |               ******       |\n   |              ******        |\n   |             ******         |\n   |            ******          |\n   |           *****            |\n   |          *****             |\n   |         *****              |\n   |        *****               |\n   |       *****                |\n   |       ****                 |\n   |      *****                 |\n   |     *****                  |\n   |     ****                   |\n   |    *****                   |\n   |    *******************     |\n   |    *******************     |\n   |    *******************     |\n   |    *******************     |\n   |                            |\n   |                            |\n   |                            |\n   |                            |\n   +----------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x007f,0x8000,\n0x03ff,0xe000,\n0x07ff,0xf000,\n0x07c1,0xf800,\n0x0600,0xfc00,\n0x0400,0x7c00,\n0x0000,0x3e00,\n0x0000,0x3e00,\n0x0000,0x3e00,\n0x0000,0x3e00,\n0x0000,0x3e00,\n0x0000,0x3e00,\n0x0000,0x7c00,\n0x0000,0x7c00,\n0x0000,0xf800,\n0x0001,0xf800,\n0x0003,0xf000,\n0x0007,0xe000,\n0x000f,0xc000,\n0x001f,0x0000,\n0x003e,0x0000,\n0x007c,0x0000,\n0x00f8,0x0000,\n0x01f0,0x0000,\n0x01e0,0x0000,\n0x03e0,0x0000,\n0x07c0,0x0000,\n0x0780,0x0000,\n0x0f80,0x0000,\n0x0fff,0xfe00,\n0x0fff,0xfe00,\n0x0fff,0xfe00,\n0x0fff,0xfe00,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 51 (0x33):\n   width 28\n   +----------------------------+\n   |                            |\n   |                            |\n   |                            |\n   |      **********            |\n   |    ***************         |\n   |    ****************        |\n   |    ****      *******       |\n   |    *           *****       |\n   |                ******      |\n   |                 *****      |\n   |                 *****      |\n   |                 *****      |\n   |                 *****      |\n   |                 *****      |\n   |                *****       |\n   |                *****       |\n   |               *****        |\n   |            ******          |\n   |       **********           |\n   |       *********            |\n   |       ************         |\n   |             *******        |\n   |               ******       |\n   |                 *****      |\n   |                 *****      |\n   |                  *****     |\n   |                  *****     |\n   |                  *****     |\n   |                  *****     |\n   |                  *****     |\n   |                 ******     |\n   |                 *****      |\n   |    *           ******      |\n   |    ****      *******       |\n   |    ****************        |\n   |    **************          |\n   |       *********            |\n   |                            |\n   |                            |\n   |                            |\n   +----------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x03ff,0x0000,\n0x0fff,0xe000,\n0x0fff,0xf000,\n0x0f03,0xf800,\n0x0800,0xf800,\n0x0000,0xfc00,\n0x0000,0x7c00,\n0x0000,0x7c00,\n0x0000,0x7c00,\n0x0000,0x7c00,\n0x0000,0x7c00,\n0x0000,0xf800,\n0x0000,0xf800,\n0x0001,0xf000,\n0x000f,0xc000,\n0x01ff,0x8000,\n0x01ff,0x0000,\n0x01ff,0xe000,\n0x0007,0xf000,\n0x0001,0xf800,\n0x0000,0x7c00,\n0x0000,0x7c00,\n0x0000,0x3e00,\n0x0000,0x3e00,\n0x0000,0x3e00,\n0x0000,0x3e00,\n0x0000,0x3e00,\n0x0000,0x7e00,\n0x0000,0x7c00,\n0x0800,0xfc00,\n0x0f03,0xf800,\n0x0fff,0xf000,\n0x0fff,0xc000,\n0x01ff,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 52 (0x34):\n   width 28\n   +----------------------------+\n   |                            |\n   |                            |\n   |                            |\n   |                            |\n   |                ****        |\n   |               *****        |\n   |              ******        |\n   |              ******        |\n   |             *******        |\n   |            ********        |\n   |           **** ****        |\n   |           ***  ****        |\n   |          ****  ****        |\n   |         ****   ****        |\n   |         ***    ****        |\n   |        ****    ****        |\n   |       ****     ****        |\n   |       ***      ****        |\n   |      ****      ****        |\n   |     ****       ****        |\n   |    ****        ****        |\n   |    ***         ****        |\n   |   ****         ****        |\n   |  ****          ****        |\n   |  **********************    |\n   |  **********************    |\n   |  **********************    |\n   |                ****        |\n   |                ****        |\n   |                ****        |\n   |                ****        |\n   |                ****        |\n   |                ****        |\n   |                ****        |\n   |                ****        |\n   |                ****        |\n   |                            |\n   |                            |\n   |                            |\n   |                            |\n   +----------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0xf000,\n0x0001,0xf000,\n0x0003,0xf000,\n0x0003,0xf000,\n0x0007,0xf000,\n0x000f,0xf000,\n0x001e,0xf000,\n0x001c,0xf000,\n0x003c,0xf000,\n0x0078,0xf000,\n0x0070,0xf000,\n0x00f0,0xf000,\n0x01e0,0xf000,\n0x01c0,0xf000,\n0x03c0,0xf000,\n0x0780,0xf000,\n0x0f00,0xf000,\n0x0e00,0xf000,\n0x1e00,0xf000,\n0x3c00,0xf000,\n0x3fff,0xff00,\n0x3fff,0xff00,\n0x3fff,0xff00,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 53 (0x35):\n   width 28\n   +----------------------------+\n   |                            |\n   |                            |\n   |                            |\n   |                            |\n   |      ***************       |\n   |      ***************       |\n   |      ***************       |\n   |      ***************       |\n   |      ****                  |\n   |      ****                  |\n   |      ****                  |\n   |      ****                  |\n   |      ****                  |\n   |      ****                  |\n   |      ****                  |\n   |      ****                  |\n   |      ********              |\n   |      ***********           |\n   |      ************          |\n   |            *******         |\n   |              ******        |\n   |               ******       |\n   |                *****       |\n   |                ******      |\n   |                 *****      |\n   |                 *****      |\n   |                 *****      |\n   |                 *****      |\n   |                 *****      |\n   |                 *****      |\n   |                *****       |\n   |                *****       |\n   |     *         *****        |\n   |     ***     *******        |\n   |     **************         |\n   |     ************           |\n   |       ********             |\n   |                            |\n   |                            |\n   |                            |\n   +----------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x03ff,0xf800,\n0x03ff,0xf800,\n0x03ff,0xf800,\n0x03ff,0xf800,\n0x03c0,0x0000,\n0x03c0,0x0000,\n0x03c0,0x0000,\n0x03c0,0x0000,\n0x03c0,0x0000,\n0x03c0,0x0000,\n0x03c0,0x0000,\n0x03c0,0x0000,\n0x03fc,0x0000,\n0x03ff,0x8000,\n0x03ff,0xc000,\n0x000f,0xe000,\n0x0003,0xf000,\n0x0001,0xf800,\n0x0000,0xf800,\n0x0000,0xfc00,\n0x0000,0x7c00,\n0x0000,0x7c00,\n0x0000,0x7c00,\n0x0000,0x7c00,\n0x0000,0x7c00,\n0x0000,0x7c00,\n0x0000,0xf800,\n0x0000,0xf800,\n0x0401,0xf000,\n0x0707,0xf000,\n0x07ff,0xe000,\n0x07ff,0x8000,\n0x01fe,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 54 (0x36):\n   width 28\n   +----------------------------+\n   |                            |\n   |                            |\n   |                            |\n   |            *********       |\n   |          *************     |\n   |        ***************     |\n   |       ******      ****     |\n   |      *****           *     |\n   |      ****                  |\n   |     *****                  |\n   |     ****                   |\n   |    *****                   |\n   |    *****                   |\n   |    ****                    |\n   |    ****                    |\n   |   *****     ******         |\n   |   *****   **********       |\n   |   ***** *************      |\n   |   *********    *******     |\n   |   *******        ******    |\n   |   ******          *****    |\n   |   ******          *****    |\n   |   *****            *****   |\n   |   *****            *****   |\n   |   *****            *****   |\n   |   *****            *****   |\n   |    ****            *****   |\n   |    ****            *****   |\n   |    ****            *****   |\n   |    *****           ****    |\n   |     ****          *****    |\n   |     *****         *****    |\n   |      *****       *****     |\n   |       *****     *****      |\n   |        *************       |\n   |         ***********        |\n   |           *******          |\n   |                            |\n   |                            |\n   |                            |\n   +----------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x000f,0xf800,\n0x003f,0xfe00,\n0x00ff,0xfe00,\n0x01f8,0x1e00,\n0x03e0,0x0200,\n0x03c0,0x0000,\n0x07c0,0x0000,\n0x0780,0x0000,\n0x0f80,0x0000,\n0x0f80,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x1f07,0xe000,\n0x1f1f,0xf800,\n0x1f7f,0xfc00,\n0x1ff0,0xfe00,\n0x1fc0,0x3f00,\n0x1f80,0x1f00,\n0x1f80,0x1f00,\n0x1f00,0x0f80,\n0x1f00,0x0f80,\n0x1f00,0x0f80,\n0x1f00,0x0f80,\n0x0f00,0x0f80,\n0x0f00,0x0f80,\n0x0f00,0x0f80,\n0x0f80,0x0f00,\n0x0780,0x1f00,\n0x07c0,0x1f00,\n0x03e0,0x3e00,\n0x01f0,0x7c00,\n0x00ff,0xf800,\n0x007f,0xf000,\n0x001f,0xc000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 55 (0x37):\n   width 28\n   +----------------------------+\n   |                            |\n   |                            |\n   |                            |\n   |                            |\n   |     ********************   |\n   |     ********************   |\n   |     ********************   |\n   |     ********************   |\n   |                    *****   |\n   |                   *****    |\n   |                   ****     |\n   |                  *****     |\n   |                 *****      |\n   |                 *****      |\n   |                *****       |\n   |                ****        |\n   |               *****        |\n   |               ****         |\n   |              *****         |\n   |              ****          |\n   |             *****          |\n   |             ****           |\n   |            *****           |\n   |           *****            |\n   |           *****            |\n   |          *****             |\n   |          *****             |\n   |         *****              |\n   |         *****              |\n   |         *****              |\n   |        *****               |\n   |        *****               |\n   |        *****               |\n   |       *****                |\n   |       *****                |\n   |       *****                |\n   |                            |\n   |                            |\n   |                            |\n   |                            |\n   +----------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x07ff,0xff80,\n0x07ff,0xff80,\n0x07ff,0xff80,\n0x07ff,0xff80,\n0x0000,0x0f80,\n0x0000,0x1f00,\n0x0000,0x1e00,\n0x0000,0x3e00,\n0x0000,0x7c00,\n0x0000,0x7c00,\n0x0000,0xf800,\n0x0000,0xf000,\n0x0001,0xf000,\n0x0001,0xe000,\n0x0003,0xe000,\n0x0003,0xc000,\n0x0007,0xc000,\n0x0007,0x8000,\n0x000f,0x8000,\n0x001f,0x0000,\n0x001f,0x0000,\n0x003e,0x0000,\n0x003e,0x0000,\n0x007c,0x0000,\n0x007c,0x0000,\n0x007c,0x0000,\n0x00f8,0x0000,\n0x00f8,0x0000,\n0x00f8,0x0000,\n0x01f0,0x0000,\n0x01f0,0x0000,\n0x01f0,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 56 (0x38):\n   width 28\n   +----------------------------+\n   |                            |\n   |                            |\n   |                            |\n   |            *******         |\n   |          ***********       |\n   |        **************      |\n   |       ******    ******     |\n   |       ****        *****    |\n   |      ****          ****    |\n   |      ****          ****    |\n   |      ****          ****    |\n   |      ****          ****    |\n   |      ****          ****    |\n   |      *****        ****     |\n   |       *****       ****     |\n   |       ******     ****      |\n   |        *******  ****       |\n   |         ***********        |\n   |          ********          |\n   |         ***********        |\n   |        *************       |\n   |       *****   *******      |\n   |      *****     *******     |\n   |     *****        ******    |\n   |     *****         *****    |\n   |    *****           *****   |\n   |    *****            ****   |\n   |    *****            ****   |\n   |    *****            ****   |\n   |    *****            ****   |\n   |    *****            ****   |\n   |     *****          ****    |\n   |     ******        *****    |\n   |      ******      *****     |\n   |       ***************      |\n   |        *************       |\n   |           *******          |\n   |                            |\n   |                            |\n   |                            |\n   +----------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x000f,0xe000,\n0x003f,0xf800,\n0x00ff,0xfc00,\n0x01f8,0x7e00,\n0x01e0,0x1f00,\n0x03c0,0x0f00,\n0x03c0,0x0f00,\n0x03c0,0x0f00,\n0x03c0,0x0f00,\n0x03c0,0x0f00,\n0x03e0,0x1e00,\n0x01f0,0x1e00,\n0x01f8,0x3c00,\n0x00fe,0x7800,\n0x007f,0xf000,\n0x003f,0xc000,\n0x007f,0xf000,\n0x00ff,0xf800,\n0x01f1,0xfc00,\n0x03e0,0xfe00,\n0x07c0,0x3f00,\n0x07c0,0x1f00,\n0x0f80,0x0f80,\n0x0f80,0x0780,\n0x0f80,0x0780,\n0x0f80,0x0780,\n0x0f80,0x0780,\n0x0f80,0x0780,\n0x07c0,0x0f00,\n0x07e0,0x1f00,\n0x03f0,0x3e00,\n0x01ff,0xfc00,\n0x00ff,0xf800,\n0x001f,0xc000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 57 (0x39):\n   width 28\n   +----------------------------+\n   |                            |\n   |                            |\n   |                            |\n   |          *******           |\n   |        ***********         |\n   |       *************        |\n   |      *****     *****       |\n   |     *****       *****      |\n   |    *****         *****     |\n   |    *****          ****     |\n   |    ****           *****    |\n   |   *****            ****    |\n   |   *****            ****    |\n   |   *****            ****    |\n   |   *****            *****   |\n   |   *****            *****   |\n   |   *****            *****   |\n   |   *****            *****   |\n   |    *****          ******   |\n   |    *****          ******   |\n   |     *****        *******   |\n   |     *******    *********   |\n   |      ************* *****   |\n   |        *********   *****   |\n   |          *****     ****    |\n   |                    ****    |\n   |                   *****    |\n   |                   *****    |\n   |                   ****     |\n   |                  *****     |\n   |                  ****      |\n   |                 *****      |\n   |     *          *****       |\n   |     ****     ******        |\n   |     **************         |\n   |     *************          |\n   |       ********             |\n   |                            |\n   |                            |\n   |                            |\n   +----------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x003f,0x8000,\n0x00ff,0xe000,\n0x01ff,0xf000,\n0x03e0,0xf800,\n0x07c0,0x7c00,\n0x0f80,0x3e00,\n0x0f80,0x1e00,\n0x0f00,0x1f00,\n0x1f00,0x0f00,\n0x1f00,0x0f00,\n0x1f00,0x0f00,\n0x1f00,0x0f80,\n0x1f00,0x0f80,\n0x1f00,0x0f80,\n0x1f00,0x0f80,\n0x0f80,0x1f80,\n0x0f80,0x1f80,\n0x07c0,0x3f80,\n0x07f0,0xff80,\n0x03ff,0xef80,\n0x00ff,0x8f80,\n0x003e,0x0f00,\n0x0000,0x0f00,\n0x0000,0x1f00,\n0x0000,0x1f00,\n0x0000,0x1e00,\n0x0000,0x3e00,\n0x0000,0x3c00,\n0x0000,0x7c00,\n0x0400,0xf800,\n0x0783,0xf000,\n0x07ff,0xe000,\n0x07ff,0xc000,\n0x01fe,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 58 (0x3a):\n   width 14\n   +--------------+\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |     *****    |\n   |     *****    |\n   |     *****    |\n   |     *****    |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |     *****    |\n   |     *****    |\n   |     *****    |\n   |     *****    |\n   |              |\n   |              |\n   |              |\n   |              |\n   +--------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x07c0,\n0x07c0,\n0x07c0,\n0x07c0,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x07c0,\n0x07c0,\n0x07c0,\n0x07c0,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n};\n\n/* Character->glyph mapping. */\nstatic const unsigned short _digits32_offset[] = {\n  0,\t/* (0x20) */\n  0,\t/* (0x21) */\n  0,\t/* (0x22) */\n  0,\t/* (0x23) */\n  0,\t/* (0x24) */\n  0,\t/* (0x25) */\n  0,\t/* (0x26) */\n  0,\t/* (0x27) */\n  0,\t/* (0x28) */\n  0,\t/* (0x29) */\n  0,\t/* (0x2a) */\n  0,\t/* (0x2b) */\n  0,\t/* (0x2c) */\n  0,\t/* (0x2d) */\n  0,\t/* (0x2e) */\n  0,\t/* (0x2f) */\n  40,\t/* (0x30) */\n  120,\t/* (0x31) */\n  200,\t/* (0x32) */\n  280,\t/* (0x33) */\n  360,\t/* (0x34) */\n  440,\t/* (0x35) */\n  520,\t/* (0x36) */\n  600,\t/* (0x37) */\n  680,\t/* (0x38) */\n  760,\t/* (0x39) */\n  840,\t/* (0x3a) */\n};\n\n/* Character width data. */\nstatic const unsigned char _digits32_width[] = {\n  14,\t/* (0x20) */\n  14,\t/* (0x21) */\n  14,\t/* (0x22) */\n  14,\t/* (0x23) */\n  14,\t/* (0x24) */\n  14,\t/* (0x25) */\n  14,\t/* (0x26) */\n  14,\t/* (0x27) */\n  14,\t/* (0x28) */\n  14,\t/* (0x29) */\n  14,\t/* (0x2a) */\n  14,\t/* (0x2b) */\n  14,\t/* (0x2c) */\n  14,\t/* (0x2d) */\n  14,\t/* (0x2e) */\n  14,\t/* (0x2f) */\n  28,\t/* (0x30) */\n  28,\t/* (0x31) */\n  28,\t/* (0x32) */\n  28,\t/* (0x33) */\n  28,\t/* (0x34) */\n  28,\t/* (0x35) */\n  28,\t/* (0x36) */\n  28,\t/* (0x37) */\n  28,\t/* (0x38) */\n  28,\t/* (0x39) */\n  14,\t/* (0x3a) */\n};\n\n/* Exported structure definition. */\nconst struct gpanel_font_t font_digits32 = {\n  \"digits32\",\n  28,\n  40,\n  36,\n  32,\n  27,\n  _digits32_bits,\n  _digits32_offset,\n  _digits32_width,\n  32,\n  sizeof(_digits32_bits) / sizeof(_digits32_bits[0]),\n};\n"
  },
  {
    "path": "share/examples/gpanel/fonts/lucidasans11.c",
    "content": "/* Generated by convbdf on Thu Oct  8 21:26:34 2015. */\n#include <sys/gpanel.h>\n\n/* Font information:\n   name: lucidasans11\n   facename: -FreeType-Lucida Sans Unicode-Medium-R-Normal--15-110-100-100-P-71-ISO10646-1\n   w x h: 14x17\n   size: 133\n   ascent: 14\n   descent: 3\n   first char: 32 (0x20)\n   last char: 164 (0xa4)\n   default char: 164 (0xa4)\n   proportional: yes\n   Copyright  1993 Bigelow & Holmes Inc. All rights reserved. Pat. Des. 289,420. Pats. Pend.\n*/\n\n/* Font character bitmap data. */\nstatic const unsigned short _lucidasans11_bits[] = {\n\n/* Character 32 (0x20):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 33 (0x21):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |     |\n   |  ** |\n   |     |\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x0000,\n0x3000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 34 (0x22):\n   width 6\n   +------+\n   |      |\n   |      |\n   | ** **|\n   | ** **|\n   | ** **|\n   | ** **|\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x6c00,\n0x6c00,\n0x6c00,\n0x6c00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 35 (0x23):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |    *  * |\n   |    *  * |\n   |   *  *  |\n   | ********|\n   |   *  *  |\n   |  ** **  |\n   |  *  *   |\n   |******** |\n   |  *  *   |\n   | *  *    |\n   | *  *    |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0900,\n0x0900,\n0x1200,\n0x7f80,\n0x1200,\n0x3600,\n0x2400,\n0xff00,\n0x2400,\n0x4800,\n0x4800,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 36 (0x24):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |    *    |\n   |  *****  |\n   | ** *  * |\n   | ** *    |\n   | ** *    |\n   |  ***    |\n   |    **   |\n   |    * *  |\n   |    * ** |\n   |    * ** |\n   | *  * ** |\n   |  ****   |\n   |    *    |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0800,\n0x3e00,\n0x6900,\n0x6800,\n0x6800,\n0x3800,\n0x0c00,\n0x0a00,\n0x0b00,\n0x0b00,\n0x4b00,\n0x3c00,\n0x0800,\n0x0000,\n0x0000,\n\n/* Character 37 (0x25):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   | ***     *|\n   |*   *   * |\n   |*   *  *  |\n   |*   * *   |\n   | *** *    |\n   |    *     |\n   |    * *** |\n   |   * *   *|\n   |  *  *   *|\n   | *   *   *|\n   |*     *** |\n   |          |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7040,\n0x8880,\n0x8900,\n0x8a00,\n0x7400,\n0x0800,\n0x0b80,\n0x1440,\n0x2440,\n0x4440,\n0x8380,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 38 (0x26):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   |    ***   |\n   |   ** **  |\n   |   ** **  |\n   |   ** **  |\n   |    ***   |\n   |  ****  **|\n   | **  ** **|\n   | **   * **|\n   | **   *** |\n   |  **   ** |\n   |   **** **|\n   |          |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0e00,\n0x1b00,\n0x1b00,\n0x1b00,\n0x0e00,\n0x3cc0,\n0x66c0,\n0x62c0,\n0x6380,\n0x3180,\n0x1ec0,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 39 (0x27):\n   width 3\n   +---+\n   |   |\n   |   |\n   | **|\n   | **|\n   | **|\n   | **|\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   +---+ */\n0x0000,\n0x0000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 40 (0x28):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |   * |\n   |   * |\n   |  *  |\n   |  *  |\n   | **  |\n   | **  |\n   | **  |\n   | **  |\n   | **  |\n   | **  |\n   |  *  |\n   |  *  |\n   |   * |\n   |   * |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x1000,\n0x1000,\n0x2000,\n0x2000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x2000,\n0x2000,\n0x1000,\n0x1000,\n0x0000,\n\n/* Character 41 (0x29):\n   width 5\n   +-----+\n   |     |\n   |     |\n   | *   |\n   | *   |\n   |  *  |\n   |  *  |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  *  |\n   |  *  |\n   | *   |\n   | *   |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x4000,\n0x4000,\n0x2000,\n0x2000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x2000,\n0x2000,\n0x4000,\n0x4000,\n0x0000,\n\n/* Character 42 (0x2a):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |   *   |\n   | * * * |\n   |  * *  |\n   |  * *  |\n   |  * *  |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1000,\n0x5400,\n0x2800,\n0x2800,\n0x2800,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 43 (0x2b):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |      *     |\n   |      *     |\n   |      *     |\n   |      *     |\n   |  ********* |\n   |      *     |\n   |      *     |\n   |      *     |\n   |      *     |\n   |            |\n   |            |\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0200,\n0x0200,\n0x0200,\n0x0200,\n0x3fe0,\n0x0200,\n0x0200,\n0x0200,\n0x0200,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 44 (0x2c):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   | **  |\n   | **  |\n   |  *  |\n   | *   |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x6000,\n0x6000,\n0x2000,\n0x4000,\n0x0000,\n\n/* Character 45 (0x2d):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   | ******* |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x7f00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 46 (0x2e):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   | **  |\n   | **  |\n   |     |\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x6000,\n0x6000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 47 (0x2f):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |      * |\n   |      * |\n   |     *  |\n   |     *  |\n   |     *  |\n   |    *   |\n   |    *   |\n   |    *   |\n   |   *    |\n   |   *    |\n   |   *    |\n   |  *     |\n   |  *     |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0200,\n0x0200,\n0x0400,\n0x0400,\n0x0400,\n0x0800,\n0x0800,\n0x0800,\n0x1000,\n0x1000,\n0x1000,\n0x2000,\n0x2000,\n0x0000,\n\n/* Character 48 (0x30):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |   ****  |\n   |  **  ** |\n   |  *    * |\n   | **    **|\n   | **    **|\n   | **    **|\n   | **    **|\n   | **    **|\n   |  *    * |\n   |  **  ** |\n   |   ****  |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1e00,\n0x3300,\n0x2100,\n0x6180,\n0x6180,\n0x6180,\n0x6180,\n0x6180,\n0x2100,\n0x3300,\n0x1e00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 49 (0x31):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |   ***   |\n   |    **   |\n   |    **   |\n   |    **   |\n   |    **   |\n   |    **   |\n   |    **   |\n   |    **   |\n   |    **   |\n   |    **   |\n   |    **   |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 50 (0x32):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |  *****  |\n   | *    ** |\n   |      ** |\n   |      ** |\n   |      ** |\n   |     **  |\n   |    **   |\n   |   **    |\n   |  **     |\n   | **      |\n   | ******* |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3e00,\n0x4300,\n0x0300,\n0x0300,\n0x0300,\n0x0600,\n0x0c00,\n0x1800,\n0x3000,\n0x6000,\n0x7f00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 51 (0x33):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |   ****  |\n   |  *   ** |\n   |      ** |\n   |      ** |\n   |     **  |\n   |   ***   |\n   |     **  |\n   |      ** |\n   |      ** |\n   |  *   ** |\n   |   ****  |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1e00,\n0x2300,\n0x0300,\n0x0300,\n0x0600,\n0x1c00,\n0x0600,\n0x0300,\n0x0300,\n0x2300,\n0x1e00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 52 (0x34):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |     **  |\n   |    ***  |\n   |    ***  |\n   |   * **  |\n   |  *  **  |\n   |  *  **  |\n   | *   **  |\n   | ******* |\n   |     **  |\n   |     **  |\n   |     **  |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0600,\n0x0e00,\n0x0e00,\n0x1600,\n0x2600,\n0x2600,\n0x4600,\n0x7f00,\n0x0600,\n0x0600,\n0x0600,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 53 (0x35):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |  ****** |\n   |  **     |\n   |  **     |\n   |  **     |\n   |  ****   |\n   |     **  |\n   |      ** |\n   |      ** |\n   |      ** |\n   |     **  |\n   |  ****   |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3f00,\n0x3000,\n0x3000,\n0x3000,\n0x3c00,\n0x0600,\n0x0300,\n0x0300,\n0x0300,\n0x0600,\n0x3c00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 54 (0x36):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |   ****  |\n   |  **     |\n   |  *      |\n   | **      |\n   | ** **   |\n   | *** **  |\n   | **   ** |\n   | **   ** |\n   | **   ** |\n   |  ** **  |\n   |   ***   |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1e00,\n0x3000,\n0x2000,\n0x6000,\n0x6c00,\n0x7600,\n0x6300,\n0x6300,\n0x6300,\n0x3600,\n0x1c00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 55 (0x37):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |  *******|\n   |        *|\n   |       * |\n   |      ** |\n   |      *  |\n   |     **  |\n   |     *   |\n   |    **   |\n   |    **   |\n   |   **    |\n   |   **    |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3f80,\n0x0080,\n0x0100,\n0x0300,\n0x0200,\n0x0600,\n0x0400,\n0x0c00,\n0x0c00,\n0x1800,\n0x1800,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 56 (0x38):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |   ****  |\n   |  **  ** |\n   |  **  ** |\n   |  **  ** |\n   |   ** *  |\n   |  *****  |\n   | **  *** |\n   | **   ** |\n   | **   ** |\n   | **   ** |\n   |  *****  |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1e00,\n0x3300,\n0x3300,\n0x3300,\n0x1a00,\n0x3e00,\n0x6700,\n0x6300,\n0x6300,\n0x6300,\n0x3e00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 57 (0x39):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |   ***   |\n   |  ** **  |\n   | **   ** |\n   | **   ** |\n   | **   ** |\n   |  ** *** |\n   |   ** ** |\n   |      ** |\n   |      *  |\n   |     **  |\n   |  ****   |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1c00,\n0x3600,\n0x6300,\n0x6300,\n0x6300,\n0x3700,\n0x1b00,\n0x0300,\n0x0200,\n0x0600,\n0x3c00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 58 (0x3a):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |  ** |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |  ** |\n   |     |\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 59 (0x3b):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |  ** |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |  ** |\n   |   * |\n   |  *  |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x1000,\n0x2000,\n0x0000,\n\n/* Character 60 (0x3c):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |          * |\n   |        **  |\n   |      **    |\n   |    **      |\n   |  **        |\n   |    **      |\n   |      **    |\n   |        **  |\n   |          * |\n   |            |\n   |            |\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0020,\n0x00c0,\n0x0300,\n0x0c00,\n0x3000,\n0x0c00,\n0x0300,\n0x00c0,\n0x0020,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 61 (0x3d):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |  ********  |\n   |            |\n   |  ********  |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3fc0,\n0x0000,\n0x3fc0,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 62 (0x3e):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |  *         |\n   |   **       |\n   |     **     |\n   |       **   |\n   |         ** |\n   |       **   |\n   |     **     |\n   |   **       |\n   |  *         |\n   |            |\n   |            |\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x2000,\n0x1800,\n0x0600,\n0x0180,\n0x0060,\n0x0180,\n0x0600,\n0x1800,\n0x2000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 63 (0x3f):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |***** |\n   |    **|\n   |    **|\n   |    **|\n   |   ** |\n   |  **  |\n   |  *   |\n   | **   |\n   | **   |\n   |      |\n   | **   |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0xf800,\n0x0c00,\n0x0c00,\n0x0c00,\n0x1800,\n0x3000,\n0x2000,\n0x6000,\n0x6000,\n0x0000,\n0x6000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 64 (0x40):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |     *****   |\n   |   **     *  |\n   |  **  ***  * |\n   |  *  *  *  * |\n   | *   *  *  * |\n   | *  *   *  * |\n   | *  *   *  * |\n   | *  *  ** *  |\n   | ** *** **   |\n   |  **         |\n   |   *****     |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x07c0,\n0x1820,\n0x3390,\n0x2490,\n0x4490,\n0x4890,\n0x4890,\n0x49a0,\n0x6ec0,\n0x3000,\n0x1f00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 65 (0x41):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   |    **    |\n   |    **    |\n   |   * **   |\n   |   * **   |\n   |   * **   |\n   |  *   **  |\n   |  *   **  |\n   | ******** |\n   | *     ** |\n   | *     ** |\n   |*       **|\n   |          |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0c00,\n0x0c00,\n0x1600,\n0x1600,\n0x1600,\n0x2300,\n0x2300,\n0x7f80,\n0x4180,\n0x4180,\n0x80c0,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 66 (0x42):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   | ******  |\n   | **   ** |\n   | **   ** |\n   | **   ** |\n   | **  **  |\n   | *****   |\n   | **  **  |\n   | **   ** |\n   | **   ** |\n   | **   ** |\n   | ******  |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7e00,\n0x6300,\n0x6300,\n0x6300,\n0x6600,\n0x7c00,\n0x6600,\n0x6300,\n0x6300,\n0x6300,\n0x7e00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 67 (0x43):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   |    *****  |\n   |  ***    * |\n   |  **       |\n   | **        |\n   | **        |\n   | **        |\n   | **        |\n   | **        |\n   |  **       |\n   |  ***    * |\n   |    *****  |\n   |           |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0f80,\n0x3840,\n0x3000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x3000,\n0x3840,\n0x0f80,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 68 (0x44):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   | ******    |\n   | **    **  |\n   | **    **  |\n   | **     ** |\n   | **     ** |\n   | **     ** |\n   | **     ** |\n   | **     ** |\n   | **    **  |\n   | **    **  |\n   | ******    |\n   |           |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7e00,\n0x6180,\n0x6180,\n0x60c0,\n0x60c0,\n0x60c0,\n0x60c0,\n0x60c0,\n0x6180,\n0x6180,\n0x7e00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 69 (0x45):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   | ****** |\n   | **     |\n   | **     |\n   | **     |\n   | **     |\n   | *****  |\n   | **     |\n   | **     |\n   | **     |\n   | **     |\n   | ****** |\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7e00,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x7c00,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x7e00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 70 (0x46):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   | ****** |\n   | **     |\n   | **     |\n   | **     |\n   | **     |\n   | *****  |\n   | **     |\n   | **     |\n   | **     |\n   | **     |\n   | **     |\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7e00,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x7c00,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 71 (0x47):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   |    ****** |\n   |  ***      |\n   |  **       |\n   | **        |\n   | **        |\n   | **        |\n   | **     ** |\n   | **     ** |\n   |  **    ** |\n   |  ***   ** |\n   |    ****** |\n   |           |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0fc0,\n0x3800,\n0x3000,\n0x6000,\n0x6000,\n0x6000,\n0x60c0,\n0x60c0,\n0x30c0,\n0x38c0,\n0x0fc0,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 72 (0x48):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   | **     ** |\n   | **     ** |\n   | **     ** |\n   | **     ** |\n   | **     ** |\n   | ********* |\n   | **     ** |\n   | **     ** |\n   | **     ** |\n   | **     ** |\n   | **     ** |\n   |           |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x60c0,\n0x60c0,\n0x60c0,\n0x60c0,\n0x60c0,\n0x7fc0,\n0x60c0,\n0x60c0,\n0x60c0,\n0x60c0,\n0x60c0,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 73 (0x49):\n   width 4\n   +----+\n   |    |\n   |    |\n   |    |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   |    |\n   |    |\n   |    |\n   +----+ */\n0x0000,\n0x0000,\n0x0000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 74 (0x4a):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |   ** |\n   |   ** |\n   |   ** |\n   |   ** |\n   |   ** |\n   |   ** |\n   |   ** |\n   |   ** |\n   |   ** |\n   |   ** |\n   |   ** |\n   |   ** |\n   |****  |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0xf000,\n0x0000,\n\n/* Character 75 (0x4b):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   | **    *  |\n   | **   *   |\n   | **  *    |\n   | ** *     |\n   | ***      |\n   | ****     |\n   | ** **    |\n   | **  **   |\n   | **  **   |\n   | **   **  |\n   | **    ** |\n   |          |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x6100,\n0x6200,\n0x6400,\n0x6800,\n0x7000,\n0x7800,\n0x6c00,\n0x6600,\n0x6600,\n0x6300,\n0x6180,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 76 (0x4c):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   | **     |\n   | **     |\n   | **     |\n   | **     |\n   | **     |\n   | **     |\n   | **     |\n   | **     |\n   | **     |\n   | **     |\n   | ****** |\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x7e00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 77 (0x4d):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   | **      **  |\n   | ***    ***  |\n   | ***    ***  |\n   | ***    ***  |\n   | * **  * **  |\n   | * **  * **  |\n   | * **  * **  |\n   | *  ** * **  |\n   | *  ***  **  |\n   | *   **  **  |\n   | *       **  |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x6060,\n0x70e0,\n0x70e0,\n0x70e0,\n0x5960,\n0x5960,\n0x5960,\n0x4d60,\n0x4e60,\n0x4660,\n0x4060,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 78 (0x4e):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   | **     *  |\n   | **     *  |\n   | ***    *  |\n   | * **   *  |\n   | * **   *  |\n   | *  **  *  |\n   | *   ** *  |\n   | *   ** *  |\n   | *    ***  |\n   | *     **  |\n   | *     **  |\n   |           |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x6080,\n0x6080,\n0x7080,\n0x5880,\n0x5880,\n0x4c80,\n0x4680,\n0x4680,\n0x4380,\n0x4180,\n0x4180,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 79 (0x4f):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |            |\n   |    ****    |\n   |  **    **  |\n   |  **    **  |\n   | **      ** |\n   | **      ** |\n   | **      ** |\n   | **      ** |\n   | **      ** |\n   |  **    **  |\n   |  **    **  |\n   |    ****    |\n   |            |\n   |            |\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0f00,\n0x30c0,\n0x30c0,\n0x6060,\n0x6060,\n0x6060,\n0x6060,\n0x6060,\n0x30c0,\n0x30c0,\n0x0f00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 80 (0x50):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   | ******  |\n   | **  *** |\n   | **   ** |\n   | **   ** |\n   | **   ** |\n   | **  **  |\n   | *****   |\n   | **      |\n   | **      |\n   | **      |\n   | **      |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7e00,\n0x6700,\n0x6300,\n0x6300,\n0x6300,\n0x6600,\n0x7c00,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 81 (0x51):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |            |\n   |    ****    |\n   |  **    **  |\n   |  **    **  |\n   | **      ** |\n   | **      ** |\n   | **      ** |\n   | **      ** |\n   | **      ** |\n   |  **    **  |\n   |  **    **  |\n   |    ****    |\n   |        **  |\n   |          **|\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0f00,\n0x30c0,\n0x30c0,\n0x6060,\n0x6060,\n0x6060,\n0x6060,\n0x6060,\n0x30c0,\n0x30c0,\n0x0f00,\n0x00c0,\n0x0030,\n0x0000,\n\n/* Character 82 (0x52):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   | ******  |\n   | **   ** |\n   | **   ** |\n   | **   ** |\n   | **  **  |\n   | *****   |\n   | **  **  |\n   | **  **  |\n   | **   ** |\n   | **   ** |\n   | **    **|\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7e00,\n0x6300,\n0x6300,\n0x6300,\n0x6600,\n0x7c00,\n0x6600,\n0x6600,\n0x6300,\n0x6300,\n0x6180,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 83 (0x53):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   | *****  |\n   |**      |\n   |**      |\n   |**      |\n   | ***    |\n   |  ****  |\n   |    *** |\n   |     ** |\n   |     ** |\n   |    **  |\n   |*****   |\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7c00,\n0xc000,\n0xc000,\n0xc000,\n0x7000,\n0x3c00,\n0x0e00,\n0x0600,\n0x0600,\n0x0c00,\n0xf800,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 84 (0x54):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   |**********|\n   |    **    |\n   |    **    |\n   |    **    |\n   |    **    |\n   |    **    |\n   |    **    |\n   |    **    |\n   |    **    |\n   |    **    |\n   |    **    |\n   |          |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0xffc0,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 85 (0x55):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   | **    ** |\n   | **    ** |\n   | **    ** |\n   | **    ** |\n   | **    ** |\n   | **    ** |\n   | **    ** |\n   | **    ** |\n   | **    ** |\n   |  **  **  |\n   |   ****   |\n   |          |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x6180,\n0x6180,\n0x6180,\n0x6180,\n0x6180,\n0x6180,\n0x6180,\n0x6180,\n0x6180,\n0x3300,\n0x1e00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 86 (0x56):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   |**      * |\n   | **    *  |\n   | **    *  |\n   | **    *  |\n   |  **  *   |\n   |  **  *   |\n   |  **  *   |\n   |   ***    |\n   |   ***    |\n   |   ***    |\n   |    *     |\n   |          |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0xc080,\n0x6100,\n0x6100,\n0x6100,\n0x3200,\n0x3200,\n0x3200,\n0x1c00,\n0x1c00,\n0x1c00,\n0x0800,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 87 (0x57):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |**    **    *|\n   |**    **    *|\n   | **   **   * |\n   | **  * **  * |\n   | **  * **  * |\n   | *** * ** ** |\n   |  ** * ** *  |\n   |  ** * ** *  |\n   |  ***   ***  |\n   |   **   **   |\n   |   **   **   |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0xc308,\n0xc308,\n0x6310,\n0x6590,\n0x6590,\n0x75b0,\n0x35a0,\n0x35a0,\n0x38e0,\n0x18c0,\n0x18c0,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 88 (0x58):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |***     *|\n   | **    * |\n   |  **  *  |\n   |  **  *  |\n   |   ***   |\n   |   ***   |\n   |   ***   |\n   |  *  **  |\n   |  *  *** |\n   | *    ** |\n   |*     ***|\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0xe080,\n0x6100,\n0x3200,\n0x3200,\n0x1c00,\n0x1c00,\n0x1c00,\n0x2600,\n0x2700,\n0x4300,\n0x8380,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 89 (0x59):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |**       |\n   | **     *|\n   |  **   * |\n   |  **   * |\n   |   ** *  |\n   |   ** *  |\n   |    **   |\n   |    **   |\n   |    **   |\n   |    **   |\n   |    **   |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0xc040,\n0x6080,\n0x3100,\n0x3100,\n0x1a00,\n0x1a00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 90 (0x5a):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |******** |\n   |      ** |\n   |     **  |\n   |    **   |\n   |    **   |\n   |   **    |\n   |  **     |\n   |  **     |\n   | **      |\n   |**       |\n   |******** |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0xff00,\n0x0300,\n0x0600,\n0x0c00,\n0x0c00,\n0x1800,\n0x3000,\n0x3000,\n0x6000,\n0xc000,\n0xff00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 91 (0x5b):\n   width 5\n   +-----+\n   |     |\n   |     |\n   | *** |\n   | **  |\n   | **  |\n   | **  |\n   | **  |\n   | **  |\n   | **  |\n   | **  |\n   | **  |\n   | **  |\n   | **  |\n   | **  |\n   | **  |\n   | *** |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x7000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x7000,\n0x0000,\n\n/* Character 92 (0x5c):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |  *     |\n   |  *     |\n   |   *    |\n   |   *    |\n   |   *    |\n   |    *   |\n   |    *   |\n   |    *   |\n   |     *  |\n   |     *  |\n   |     *  |\n   |      * |\n   |      * |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x2000,\n0x2000,\n0x1000,\n0x1000,\n0x1000,\n0x0800,\n0x0800,\n0x0800,\n0x0400,\n0x0400,\n0x0400,\n0x0200,\n0x0200,\n0x0000,\n\n/* Character 93 (0x5d):\n   width 5\n   +-----+\n   |     |\n   |     |\n   | *** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   | *** |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x7000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x7000,\n0x0000,\n\n/* Character 94 (0x5e):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |    *    |\n   |    *    |\n   |   * *   |\n   |   * *   |\n   |  *  *   |\n   |  *   *  |\n   |  *   *  |\n   | *     * |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0800,\n0x0800,\n0x1400,\n0x1400,\n0x2400,\n0x2200,\n0x2200,\n0x4100,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 95 (0x5f):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   | ****** |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x7e00,\n0x0000,\n0x0000,\n\n/* Character 96 (0x60):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |   **    |\n   |    **   |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1800,\n0x0c00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 97 (0x61):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |   ***  |\n   |  *  ** |\n   |     ** |\n   |  ***** |\n   | **  ** |\n   | **  ** |\n   | **  ** |\n   |  *** **|\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x1c00,\n0x2600,\n0x0600,\n0x3e00,\n0x6600,\n0x6600,\n0x6600,\n0x3b00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 98 (0x62):\n   width 10\n   +----------+\n   |          |\n   |          |\n   | **       |\n   | **       |\n   | **       |\n   | **       |\n   | ** ***   |\n   | ***  **  |\n   | **    ** |\n   | **    ** |\n   | **    ** |\n   | **    ** |\n   | ***  **  |\n   | ** ***   |\n   |          |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6e00,\n0x7300,\n0x6180,\n0x6180,\n0x6180,\n0x6180,\n0x7300,\n0x6e00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 99 (0x63):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |   **** |\n   |  **    |\n   | **     |\n   | **     |\n   | **     |\n   | **     |\n   |  **    |\n   |   **** |\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x1e00,\n0x3000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x3000,\n0x1e00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 100 (0x64):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |       ** |\n   |       ** |\n   |       ** |\n   |       ** |\n   |   *** ** |\n   |  **  *** |\n   | **    ** |\n   | **    ** |\n   | **    ** |\n   | **    ** |\n   |  **  *** |\n   |   *** ** |\n   |          |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0180,\n0x0180,\n0x0180,\n0x0180,\n0x1d80,\n0x3380,\n0x6180,\n0x6180,\n0x6180,\n0x6180,\n0x3380,\n0x1d80,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 101 (0x65):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |   ****  |\n   |  **  ** |\n   | **   ** |\n   | ******* |\n   | **      |\n   | **      |\n   |  **     |\n   |   ***** |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x1e00,\n0x3300,\n0x6300,\n0x7f00,\n0x6000,\n0x6000,\n0x3000,\n0x1f00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 102 (0x66):\n   width 6\n   +------+\n   |      |\n   |      |\n   |   ***|\n   |  **  |\n   |  **  |\n   |  **  |\n   | **** |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x1c00,\n0x3000,\n0x3000,\n0x3000,\n0x7800,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 103 (0x67):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   |   *** ** |\n   |  **  *** |\n   | **    ** |\n   | **    ** |\n   | **    ** |\n   | **    ** |\n   |  **  *** |\n   |   *** ** |\n   |       ** |\n   |      **  |\n   |  *****   |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x1d80,\n0x3380,\n0x6180,\n0x6180,\n0x6180,\n0x6180,\n0x3380,\n0x1d80,\n0x0180,\n0x0300,\n0x3e00,\n\n/* Character 104 (0x68):\n   width 9\n   +---------+\n   |         |\n   |         |\n   | **      |\n   | **      |\n   | **      |\n   | **      |\n   | ** ***  |\n   | ***  ** |\n   | **   ** |\n   | **   ** |\n   | **   ** |\n   | **   ** |\n   | **   ** |\n   | **   ** |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6e00,\n0x7300,\n0x6300,\n0x6300,\n0x6300,\n0x6300,\n0x6300,\n0x6300,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 105 (0x69):\n   width 4\n   +----+\n   |    |\n   |    |\n   |    |\n   | ** |\n   |    |\n   |    |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   |    |\n   |    |\n   |    |\n   +----+ */\n0x0000,\n0x0000,\n0x0000,\n0x6000,\n0x0000,\n0x0000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 106 (0x6a):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |  ** |\n   |     |\n   |     |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |  ** |\n   |***  |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x0000,\n0x0000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0xe000,\n\n/* Character 107 (0x6b):\n   width 9\n   +---------+\n   |         |\n   |         |\n   | **      |\n   | **      |\n   | **      |\n   | **      |\n   | **   *  |\n   | **  *   |\n   | ** *    |\n   | ***     |\n   | ****    |\n   | ** **   |\n   | **  **  |\n   | **   ** |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6200,\n0x6400,\n0x6800,\n0x7000,\n0x7800,\n0x6c00,\n0x6600,\n0x6300,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 108 (0x6c):\n   width 4\n   +----+\n   |    |\n   |    |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   | ** |\n   |    |\n   |    |\n   |    |\n   +----+ */\n0x0000,\n0x0000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 109 (0x6d):\n   width 14\n   +--------------+\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   | ** ***  ***  |\n   | ***  ***  ** |\n   | **   **   ** |\n   | **   **   ** |\n   | **   **   ** |\n   | **   **   ** |\n   | **   **   ** |\n   | **   **   ** |\n   |              |\n   |              |\n   |              |\n   +--------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x6e70,\n0x7398,\n0x6318,\n0x6318,\n0x6318,\n0x6318,\n0x6318,\n0x6318,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 110 (0x6e):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   | ** ***  |\n   | ***  ** |\n   | **   ** |\n   | **   ** |\n   | **   ** |\n   | **   ** |\n   | **   ** |\n   | **   ** |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x6e00,\n0x7300,\n0x6300,\n0x6300,\n0x6300,\n0x6300,\n0x6300,\n0x6300,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 111 (0x6f):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   |   ****   |\n   |  **  **  |\n   | **    ** |\n   | **    ** |\n   | **    ** |\n   | **    ** |\n   |  **  **  |\n   |   ****   |\n   |          |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x1e00,\n0x3300,\n0x6180,\n0x6180,\n0x6180,\n0x6180,\n0x3300,\n0x1e00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 112 (0x70):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   | ** ***   |\n   | ***  **  |\n   | **    ** |\n   | **    ** |\n   | **    ** |\n   | **    ** |\n   | ***  **  |\n   | ** ***   |\n   | **       |\n   | **       |\n   | **       |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x6e00,\n0x7300,\n0x6180,\n0x6180,\n0x6180,\n0x6180,\n0x7300,\n0x6e00,\n0x6000,\n0x6000,\n0x6000,\n\n/* Character 113 (0x71):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   |   *** ** |\n   |  **  *** |\n   | **    ** |\n   | **    ** |\n   | **    ** |\n   | **    ** |\n   |  **  *** |\n   |   *** ** |\n   |       ** |\n   |       ** |\n   |       ** |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x1d80,\n0x3380,\n0x6180,\n0x6180,\n0x6180,\n0x6180,\n0x3380,\n0x1d80,\n0x0180,\n0x0180,\n0x0180,\n\n/* Character 114 (0x72):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   | ** **|\n   | ***  |\n   | **   |\n   | **   |\n   | **   |\n   | **   |\n   | **   |\n   | **   |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x6c00,\n0x7000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 115 (0x73):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |  ***  |\n   | **    |\n   | **    |\n   |  **   |\n   |   **  |\n   |    ** |\n   |    ** |\n   | ****  |\n   |       |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3800,\n0x6000,\n0x6000,\n0x3000,\n0x1800,\n0x0c00,\n0x0c00,\n0x7800,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 116 (0x74):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |      |\n   | **   |\n   | **   |\n   |***** |\n   | **   |\n   | **   |\n   | **   |\n   | **   |\n   | **   |\n   | **   |\n   |  *** |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x6000,\n0x6000,\n0xf800,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x3800,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 117 (0x75):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   | **   ** |\n   | **   ** |\n   | **   ** |\n   | **   ** |\n   | **   ** |\n   | **   ** |\n   | **  *** |\n   |  *** ** |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x6300,\n0x6300,\n0x6300,\n0x6300,\n0x6300,\n0x6300,\n0x6700,\n0x3b00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 118 (0x76):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |**     *|\n   | **   * |\n   | **   * |\n   | **   * |\n   |  ** *  |\n   |  ** *  |\n   |   **   |\n   |   **   |\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0xc100,\n0x6200,\n0x6200,\n0x6200,\n0x3400,\n0x3400,\n0x1800,\n0x1800,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 119 (0x77):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   | **   *   * |\n   | **  **   * |\n   |  ** *** *  |\n   |  ** *** *  |\n   |  ** * * *  |\n   |  ***  ***  |\n   |   **  **   |\n   |   **  **   |\n   |            |\n   |            |\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x6220,\n0x6620,\n0x3740,\n0x3740,\n0x3540,\n0x39c0,\n0x1980,\n0x1980,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 120 (0x78):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   | ***    * |\n   |  **   *  |\n   |   ** *   |\n   |   ***    |\n   |    ***   |\n   |   * **   |\n   |  *   **  |\n   | *    *** |\n   |          |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x7080,\n0x3100,\n0x1a00,\n0x1c00,\n0x0e00,\n0x1600,\n0x2300,\n0x4380,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 121 (0x79):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |**     *|\n   | **   * |\n   | **   * |\n   | **   * |\n   |  ** *  |\n   |  ** *  |\n   |   **   |\n   |   **   |\n   |   *    |\n   |   *    |\n   |  **    |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0xc100,\n0x6200,\n0x6200,\n0x6200,\n0x3400,\n0x3400,\n0x1800,\n0x1800,\n0x1000,\n0x1000,\n0x3000,\n\n/* Character 122 (0x7a):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   | ******* |\n   |      ** |\n   |     **  |\n   |    **   |\n   |   **    |\n   |  **     |\n   | **      |\n   | ******* |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x7f00,\n0x0300,\n0x0600,\n0x0c00,\n0x1800,\n0x3000,\n0x6000,\n0x7f00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 123 (0x7b):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |  *  |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   |*    |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   |  *  |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x2000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x8000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x2000,\n0x0000,\n\n/* Character 124 (0x7c):\n   width 6\n   +------+\n   |      |\n   |      |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x0000,\n\n/* Character 125 (0x7d):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |  *  |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |    *|\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |  *  |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x2000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x0800,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x2000,\n0x0000,\n\n/* Character 126 (0x7e):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   | **    * |\n   |*  **  * |\n   |*    **  |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x6100,\n0x9900,\n0x8600,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 127 (0x7f):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   |          |\n   |*       * |\n   | * *** *  |\n   |  *   *   |\n   | *     *  |\n   | *     *  |\n   | *     *  |\n   |  *   *   |\n   | * *** *  |\n   |*       * |\n   |          |\n   |          |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x8080,\n0x5d00,\n0x2200,\n0x4100,\n0x4100,\n0x4100,\n0x2200,\n0x5d00,\n0x8080,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n};\n\n/* Character->glyph mapping. */\nstatic const unsigned short _lucidasans11_offset[] = {\n  0,\t/* (0x20) */\n  17,\t/* (0x21) */\n  34,\t/* (0x22) */\n  51,\t/* (0x23) */\n  68,\t/* (0x24) */\n  85,\t/* (0x25) */\n  102,\t/* (0x26) */\n  119,\t/* (0x27) */\n  136,\t/* (0x28) */\n  153,\t/* (0x29) */\n  170,\t/* (0x2a) */\n  187,\t/* (0x2b) */\n  204,\t/* (0x2c) */\n  221,\t/* (0x2d) */\n  238,\t/* (0x2e) */\n  255,\t/* (0x2f) */\n  272,\t/* (0x30) */\n  289,\t/* (0x31) */\n  306,\t/* (0x32) */\n  323,\t/* (0x33) */\n  340,\t/* (0x34) */\n  357,\t/* (0x35) */\n  374,\t/* (0x36) */\n  391,\t/* (0x37) */\n  408,\t/* (0x38) */\n  425,\t/* (0x39) */\n  442,\t/* (0x3a) */\n  459,\t/* (0x3b) */\n  476,\t/* (0x3c) */\n  493,\t/* (0x3d) */\n  510,\t/* (0x3e) */\n  527,\t/* (0x3f) */\n  544,\t/* (0x40) */\n  561,\t/* (0x41) */\n  578,\t/* (0x42) */\n  595,\t/* (0x43) */\n  612,\t/* (0x44) */\n  629,\t/* (0x45) */\n  646,\t/* (0x46) */\n  663,\t/* (0x47) */\n  680,\t/* (0x48) */\n  697,\t/* (0x49) */\n  714,\t/* (0x4a) */\n  731,\t/* (0x4b) */\n  748,\t/* (0x4c) */\n  765,\t/* (0x4d) */\n  782,\t/* (0x4e) */\n  799,\t/* (0x4f) */\n  816,\t/* (0x50) */\n  833,\t/* (0x51) */\n  850,\t/* (0x52) */\n  867,\t/* (0x53) */\n  884,\t/* (0x54) */\n  901,\t/* (0x55) */\n  918,\t/* (0x56) */\n  935,\t/* (0x57) */\n  952,\t/* (0x58) */\n  969,\t/* (0x59) */\n  986,\t/* (0x5a) */\n  1003,\t/* (0x5b) */\n  1020,\t/* (0x5c) */\n  1037,\t/* (0x5d) */\n  1054,\t/* (0x5e) */\n  1071,\t/* (0x5f) */\n  1088,\t/* (0x60) */\n  1105,\t/* (0x61) */\n  1122,\t/* (0x62) */\n  1139,\t/* (0x63) */\n  1156,\t/* (0x64) */\n  1173,\t/* (0x65) */\n  1190,\t/* (0x66) */\n  1207,\t/* (0x67) */\n  1224,\t/* (0x68) */\n  1241,\t/* (0x69) */\n  1258,\t/* (0x6a) */\n  1275,\t/* (0x6b) */\n  1292,\t/* (0x6c) */\n  1309,\t/* (0x6d) */\n  1326,\t/* (0x6e) */\n  1343,\t/* (0x6f) */\n  1360,\t/* (0x70) */\n  1377,\t/* (0x71) */\n  1394,\t/* (0x72) */\n  1411,\t/* (0x73) */\n  1428,\t/* (0x74) */\n  1445,\t/* (0x75) */\n  1462,\t/* (0x76) */\n  1479,\t/* (0x77) */\n  1496,\t/* (0x78) */\n  1513,\t/* (0x79) */\n  1530,\t/* (0x7a) */\n  1547,\t/* (0x7b) */\n  1564,\t/* (0x7c) */\n  1581,\t/* (0x7d) */\n  1598,\t/* (0x7e) */\n  1615,\t/* (0x7f) */\n  1615,\t/* (0x80) */\n  1615,\t/* (0x81) */\n  1615,\t/* (0x82) */\n  1615,\t/* (0x83) */\n  1615,\t/* (0x84) */\n  1615,\t/* (0x85) */\n  1615,\t/* (0x86) */\n  1615,\t/* (0x87) */\n  1615,\t/* (0x88) */\n  1615,\t/* (0x89) */\n  1615,\t/* (0x8a) */\n  1615,\t/* (0x8b) */\n  1615,\t/* (0x8c) */\n  1615,\t/* (0x8d) */\n  1615,\t/* (0x8e) */\n  1615,\t/* (0x8f) */\n  1615,\t/* (0x90) */\n  1615,\t/* (0x91) */\n  1615,\t/* (0x92) */\n  1615,\t/* (0x93) */\n  1615,\t/* (0x94) */\n  1615,\t/* (0x95) */\n  1615,\t/* (0x96) */\n  1615,\t/* (0x97) */\n  1615,\t/* (0x98) */\n  1615,\t/* (0x99) */\n  1615,\t/* (0x9a) */\n  1615,\t/* (0x9b) */\n  1615,\t/* (0x9c) */\n  1615,\t/* (0x9d) */\n  1615,\t/* (0x9e) */\n  1615,\t/* (0x9f) */\n  1615,\t/* (0xa0) */\n  1615,\t/* (0xa1) */\n  1615,\t/* (0xa2) */\n  1615,\t/* (0xa3) */\n  1615,\t/* (0xa4) */\n};\n\n/* Character width data. */\nstatic const unsigned char _lucidasans11_width[] = {\n  5,\t/* (0x20) */\n  5,\t/* (0x21) */\n  6,\t/* (0x22) */\n  9,\t/* (0x23) */\n  9,\t/* (0x24) */\n  10,\t/* (0x25) */\n  10,\t/* (0x26) */\n  3,\t/* (0x27) */\n  5,\t/* (0x28) */\n  5,\t/* (0x29) */\n  7,\t/* (0x2a) */\n  12,\t/* (0x2b) */\n  5,\t/* (0x2c) */\n  9,\t/* (0x2d) */\n  5,\t/* (0x2e) */\n  8,\t/* (0x2f) */\n  9,\t/* (0x30) */\n  9,\t/* (0x31) */\n  9,\t/* (0x32) */\n  9,\t/* (0x33) */\n  9,\t/* (0x34) */\n  9,\t/* (0x35) */\n  9,\t/* (0x36) */\n  9,\t/* (0x37) */\n  9,\t/* (0x38) */\n  9,\t/* (0x39) */\n  5,\t/* (0x3a) */\n  5,\t/* (0x3b) */\n  12,\t/* (0x3c) */\n  12,\t/* (0x3d) */\n  12,\t/* (0x3e) */\n  6,\t/* (0x3f) */\n  13,\t/* (0x40) */\n  10,\t/* (0x41) */\n  9,\t/* (0x42) */\n  11,\t/* (0x43) */\n  11,\t/* (0x44) */\n  8,\t/* (0x45) */\n  8,\t/* (0x46) */\n  11,\t/* (0x47) */\n  11,\t/* (0x48) */\n  4,\t/* (0x49) */\n  6,\t/* (0x4a) */\n  10,\t/* (0x4b) */\n  8,\t/* (0x4c) */\n  13,\t/* (0x4d) */\n  11,\t/* (0x4e) */\n  12,\t/* (0x4f) */\n  9,\t/* (0x50) */\n  12,\t/* (0x51) */\n  9,\t/* (0x52) */\n  8,\t/* (0x53) */\n  10,\t/* (0x54) */\n  10,\t/* (0x55) */\n  10,\t/* (0x56) */\n  13,\t/* (0x57) */\n  9,\t/* (0x58) */\n  9,\t/* (0x59) */\n  9,\t/* (0x5a) */\n  5,\t/* (0x5b) */\n  8,\t/* (0x5c) */\n  5,\t/* (0x5d) */\n  9,\t/* (0x5e) */\n  8,\t/* (0x5f) */\n  9,\t/* (0x60) */\n  8,\t/* (0x61) */\n  10,\t/* (0x62) */\n  8,\t/* (0x63) */\n  10,\t/* (0x64) */\n  9,\t/* (0x65) */\n  6,\t/* (0x66) */\n  10,\t/* (0x67) */\n  9,\t/* (0x68) */\n  4,\t/* (0x69) */\n  5,\t/* (0x6a) */\n  9,\t/* (0x6b) */\n  4,\t/* (0x6c) */\n  14,\t/* (0x6d) */\n  9,\t/* (0x6e) */\n  10,\t/* (0x6f) */\n  10,\t/* (0x70) */\n  10,\t/* (0x71) */\n  6,\t/* (0x72) */\n  7,\t/* (0x73) */\n  6,\t/* (0x74) */\n  9,\t/* (0x75) */\n  8,\t/* (0x76) */\n  12,\t/* (0x77) */\n  10,\t/* (0x78) */\n  8,\t/* (0x79) */\n  9,\t/* (0x7a) */\n  5,\t/* (0x7b) */\n  6,\t/* (0x7c) */\n  5,\t/* (0x7d) */\n  9,\t/* (0x7e) */\n  10,\t/* (0x7f) */\n  10,\t/* (0x80) */\n  10,\t/* (0x81) */\n  10,\t/* (0x82) */\n  10,\t/* (0x83) */\n  10,\t/* (0x84) */\n  10,\t/* (0x85) */\n  10,\t/* (0x86) */\n  10,\t/* (0x87) */\n  10,\t/* (0x88) */\n  10,\t/* (0x89) */\n  10,\t/* (0x8a) */\n  10,\t/* (0x8b) */\n  10,\t/* (0x8c) */\n  10,\t/* (0x8d) */\n  10,\t/* (0x8e) */\n  10,\t/* (0x8f) */\n  10,\t/* (0x90) */\n  10,\t/* (0x91) */\n  10,\t/* (0x92) */\n  10,\t/* (0x93) */\n  10,\t/* (0x94) */\n  10,\t/* (0x95) */\n  10,\t/* (0x96) */\n  10,\t/* (0x97) */\n  10,\t/* (0x98) */\n  10,\t/* (0x99) */\n  10,\t/* (0x9a) */\n  10,\t/* (0x9b) */\n  10,\t/* (0x9c) */\n  10,\t/* (0x9d) */\n  10,\t/* (0x9e) */\n  10,\t/* (0x9f) */\n  10,\t/* (0xa0) */\n  10,\t/* (0xa1) */\n  10,\t/* (0xa2) */\n  10,\t/* (0xa3) */\n  10,\t/* (0xa4) */\n};\n\n/* Exported structure definition. */\nconst struct gpanel_font_t font_lucidasans11 = {\n  \"lucidasans11\",\n  14,\n  17,\n  14,\n  32,\n  133,\n  _lucidasans11_bits,\n  _lucidasans11_offset,\n  _lucidasans11_width,\n  164,\n  sizeof(_lucidasans11_bits) / sizeof(_lucidasans11_bits[0]),\n};\n"
  },
  {
    "path": "share/examples/gpanel/fonts/lucidasans15.c",
    "content": "/* Generated by convbdf on Thu Oct  8 21:26:34 2015. */\n#include <sys/gpanel.h>\n\n/* Font information:\n   name: lucidasans15\n   facename: -FreeType-Lucida Sans Unicode-Medium-R-Normal--21-150-100-100-P-95-ISO10646-1\n   w x h: 20x22\n   size: 133\n   ascent: 18\n   descent: 4\n   first char: 32 (0x20)\n   last char: 164 (0xa4)\n   default char: 164 (0xa4)\n   proportional: yes\n   Copyright  1993 Bigelow & Holmes Inc. All rights reserved. Pat. Des. 289,420. Pats. Pend.\n*/\n\n/* Font character bitmap data. */\nstatic const unsigned short _lucidasans15_bits[] = {\n\n/* Character 32 (0x20):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 33 (0x21):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |       |\n   |       |\n   |  **   |\n   |       |\n   |       |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x0000,\n0x0000,\n0x3000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 34 (0x22):\n   width 8\n   +--------+\n   |        |\n   |        |\n   | **  ** |\n   | **  ** |\n   | **  ** |\n   | **  ** |\n   | **  ** |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x6600,\n0x6600,\n0x6600,\n0x6600,\n0x6600,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 35 (0x23):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |      *   *  |\n   |     **  **  |\n   |     *   *   |\n   |     *   *   |\n   |     *   *   |\n   | ************|\n   |    *   *    |\n   |    *   *    |\n   |    *   *    |\n   |************ |\n   |   *   *     |\n   |   *   *     |\n   |   *   *     |\n   |  **  **     |\n   |  *   *      |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0220,\n0x0660,\n0x0440,\n0x0440,\n0x0440,\n0x7ff8,\n0x0880,\n0x0880,\n0x0880,\n0xfff0,\n0x1100,\n0x1100,\n0x1100,\n0x3300,\n0x2200,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 36 (0x24):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |      *      |\n   |    ******   |\n   |   ** *   *  |\n   |  **  *      |\n   |  **  *      |\n   |  **  *      |\n   |   ** *      |\n   |    ***      |\n   |     ***     |\n   |      ****   |\n   |      * ***  |\n   |      *  **  |\n   |      *  **  |\n   |      *  **  |\n   |  *   * **   |\n   |   ******    |\n   |      *      |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0200,\n0x0fc0,\n0x1a20,\n0x3200,\n0x3200,\n0x3200,\n0x1a00,\n0x0e00,\n0x0700,\n0x03c0,\n0x02e0,\n0x0260,\n0x0260,\n0x0260,\n0x22c0,\n0x1f80,\n0x0200,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 37 (0x25):\n   width 14\n   +--------------+\n   |              |\n   |              |\n   |            * |\n   | ****      ** |\n   | *  *     **  |\n   |**  **    *   |\n   |**  **   *    |\n   |**  **  **    |\n   |**  ** **     |\n   | *  *  *      |\n   | **** *  **** |\n   |     **  *  * |\n   |    **  **  **|\n   |    *   **  **|\n   |   *    **  **|\n   |  **    **  **|\n   | **      *  * |\n   | *       **** |\n   |              |\n   |              |\n   |              |\n   |              |\n   +--------------+ */\n0x0000,\n0x0000,\n0x0008,\n0x7818,\n0x4830,\n0xcc20,\n0xcc40,\n0xccc0,\n0xcd80,\n0x4900,\n0x7a78,\n0x0648,\n0x0ccc,\n0x08cc,\n0x10cc,\n0x30cc,\n0x6048,\n0x4078,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 38 (0x26):\n   width 15\n   +---------------+\n   |               |\n   |               |\n   |               |\n   |      ****     |\n   |    **   **    |\n   |    **   **    |\n   |    **   **    |\n   |    **  **     |\n   |     *****     |\n   |    ****       |\n   |  *** **    ** |\n   | ***   **   ** |\n   | **    ***  ** |\n   | **     **  *  |\n   | **      ****  |\n   |  **     ***   |\n   |  ***    ****  |\n   |    *****  *** |\n   |               |\n   |               |\n   |               |\n   |               |\n   +---------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x03c0,\n0x0c60,\n0x0c60,\n0x0c60,\n0x0cc0,\n0x07c0,\n0x0f00,\n0x3b0c,\n0x718c,\n0x61cc,\n0x60c8,\n0x6078,\n0x3070,\n0x3878,\n0x0f9c,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 39 (0x27):\n   width 5\n   +-----+\n   |     |\n   |     |\n   | *** |\n   | *** |\n   | *** |\n   |  *  |\n   |  *  |\n   |  *  |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x7000,\n0x7000,\n0x7000,\n0x2000,\n0x2000,\n0x2000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 40 (0x28):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |     * |\n   |    ** |\n   |   **  |\n   |   *   |\n   |  **   |\n   |  *    |\n   | **    |\n   | **    |\n   | **    |\n   | **    |\n   | **    |\n   | **    |\n   | **    |\n   |  *    |\n   |  **   |\n   |   *   |\n   |   **  |\n   |    ** |\n   |     * |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0400,\n0x0c00,\n0x1800,\n0x1000,\n0x3000,\n0x2000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x2000,\n0x3000,\n0x1000,\n0x1800,\n0x0c00,\n0x0400,\n0x0000,\n\n/* Character 41 (0x29):\n   width 7\n   +-------+\n   |       |\n   |       |\n   | *     |\n   | **    |\n   |  **   |\n   |   *   |\n   |   **  |\n   |    *  |\n   |    ** |\n   |    ** |\n   |    ** |\n   |    ** |\n   |    ** |\n   |    ** |\n   |    ** |\n   |    *  |\n   |   **  |\n   |   *   |\n   |  **   |\n   | **    |\n   | *     |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x4000,\n0x6000,\n0x3000,\n0x1000,\n0x1800,\n0x0800,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0800,\n0x1800,\n0x1000,\n0x3000,\n0x6000,\n0x4000,\n0x0000,\n\n/* Character 42 (0x2a):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   |    **    |\n   |    **    |\n   | ** ** ** |\n   | ***  *** |\n   |          |\n   |   ****   |\n   |  **  **  |\n   |   *  *   |\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0c00,\n0x0c00,\n0x6d80,\n0x7380,\n0x0000,\n0x1e00,\n0x3300,\n0x1200,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 43 (0x2b):\n   width 17\n   +-----------------+\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   |        *        |\n   |        *        |\n   |        *        |\n   |        *        |\n   |        *        |\n   |        *        |\n   |  *************  |\n   |        *        |\n   |        *        |\n   |        *        |\n   |        *        |\n   |        *        |\n   |        *        |\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   +-----------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0080,0x0000,\n0x0080,0x0000,\n0x0080,0x0000,\n0x0080,0x0000,\n0x0080,0x0000,\n0x0080,0x0000,\n0x3ffe,0x0000,\n0x0080,0x0000,\n0x0080,0x0000,\n0x0080,0x0000,\n0x0080,0x0000,\n0x0080,0x0000,\n0x0080,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 44 (0x2c):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |  ***  |\n   |  ***  |\n   |  ***  |\n   |   **  |\n   |   **  |\n   |  **   |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3800,\n0x3800,\n0x3800,\n0x1800,\n0x1800,\n0x3000,\n0x0000,\n\n/* Character 45 (0x2d):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |  ********* |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3fe0,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 46 (0x2e):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |  ***  |\n   |  ***  |\n   |  ***  |\n   |       |\n   |       |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3800,\n0x3800,\n0x3800,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 47 (0x2f):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   |        *  |\n   |        *  |\n   |       *   |\n   |       *   |\n   |       *   |\n   |      *    |\n   |      *    |\n   |      *    |\n   |      *    |\n   |     *     |\n   |     *     |\n   |     *     |\n   |     *     |\n   |    *      |\n   |    *      |\n   |    *      |\n   |   *       |\n   |   *       |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0080,\n0x0080,\n0x0100,\n0x0100,\n0x0100,\n0x0200,\n0x0200,\n0x0200,\n0x0200,\n0x0400,\n0x0400,\n0x0400,\n0x0400,\n0x0800,\n0x0800,\n0x0800,\n0x1000,\n0x1000,\n0x0000,\n\n/* Character 48 (0x30):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |    *****    |\n   |   **   **   |\n   |  **     **  |\n   |  **     **  |\n   | **       ** |\n   | **       ** |\n   | **       ** |\n   | **       ** |\n   | **       ** |\n   | **       ** |\n   | **       ** |\n   |  **     **  |\n   |  **     **  |\n   |   **   **   |\n   |    *****    |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0f80,\n0x18c0,\n0x3060,\n0x3060,\n0x6030,\n0x6030,\n0x6030,\n0x6030,\n0x6030,\n0x6030,\n0x6030,\n0x3060,\n0x3060,\n0x18c0,\n0x0f80,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 49 (0x31):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |    ****     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0f00,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 50 (0x32):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |   ******    |\n   |  *     **   |\n   |         **  |\n   |         **  |\n   |         **  |\n   |         **  |\n   |        **   |\n   |       **    |\n   |      **     |\n   |     **      |\n   |    **       |\n   |   **        |\n   |   **        |\n   |  **         |\n   |  *********  |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1f80,\n0x20c0,\n0x0060,\n0x0060,\n0x0060,\n0x0060,\n0x00c0,\n0x0180,\n0x0300,\n0x0600,\n0x0c00,\n0x1800,\n0x1800,\n0x3000,\n0x3fe0,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 51 (0x33):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |   *****     |\n   |  *    **    |\n   |        **   |\n   |        **   |\n   |        **   |\n   |       **    |\n   |   *****     |\n   |       ***   |\n   |        **   |\n   |         **  |\n   |         **  |\n   |         **  |\n   |        **   |\n   |  *    ***   |\n   |   *****     |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1f00,\n0x2180,\n0x00c0,\n0x00c0,\n0x00c0,\n0x0180,\n0x1f00,\n0x01c0,\n0x00c0,\n0x0060,\n0x0060,\n0x0060,\n0x00c0,\n0x21c0,\n0x1f00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 52 (0x34):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |        **   |\n   |       ***   |\n   |      * **   |\n   |      * **   |\n   |     *  **   |\n   |    *   **   |\n   |   *    **   |\n   |   *    **   |\n   |  *     **   |\n   | *      **   |\n   | *********** |\n   |        **   |\n   |        **   |\n   |        **   |\n   |        **   |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x00c0,\n0x01c0,\n0x02c0,\n0x02c0,\n0x04c0,\n0x08c0,\n0x10c0,\n0x10c0,\n0x20c0,\n0x40c0,\n0x7ff0,\n0x00c0,\n0x00c0,\n0x00c0,\n0x00c0,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 53 (0x35):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |   ********  |\n   |   **        |\n   |   **        |\n   |   **        |\n   |   **        |\n   |   **        |\n   |   *****     |\n   |       ***   |\n   |        **   |\n   |         **  |\n   |         **  |\n   |         **  |\n   |        **   |\n   |       ***   |\n   |   *****     |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1fe0,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1f00,\n0x01c0,\n0x00c0,\n0x0060,\n0x0060,\n0x0060,\n0x00c0,\n0x01c0,\n0x1f00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 54 (0x36):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |    *****    |\n   |   **    *   |\n   |  **         |\n   |  **         |\n   | **          |\n   | **  ****    |\n   | ** *   **   |\n   | ***     **  |\n   | **      **  |\n   | **      **  |\n   | **      **  |\n   |  *      **  |\n   |  **    **   |\n   |   **   **   |\n   |    ****     |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0f80,\n0x1840,\n0x3000,\n0x3000,\n0x6000,\n0x6780,\n0x68c0,\n0x7060,\n0x6060,\n0x6060,\n0x6060,\n0x2060,\n0x30c0,\n0x18c0,\n0x0f00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 55 (0x37):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |  ********** |\n   |          ** |\n   |         **  |\n   |         *   |\n   |        **   |\n   |       **    |\n   |       *     |\n   |      **     |\n   |      *      |\n   |     **      |\n   |    **       |\n   |    **       |\n   |    **       |\n   |   **        |\n   |   **        |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3ff0,\n0x0030,\n0x0060,\n0x0040,\n0x00c0,\n0x0180,\n0x0100,\n0x0300,\n0x0200,\n0x0600,\n0x0c00,\n0x0c00,\n0x0c00,\n0x1800,\n0x1800,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 56 (0x38):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |     ****    |\n   |    **  **   |\n   |   **    **  |\n   |   **    **  |\n   |   **    **  |\n   |    **  **   |\n   |     ****    |\n   |    ******   |\n   |   **    **  |\n   |  **      ** |\n   |  **      ** |\n   |  **      ** |\n   |  **      ** |\n   |   **    **  |\n   |    ******   |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0780,\n0x0cc0,\n0x1860,\n0x1860,\n0x1860,\n0x0cc0,\n0x0780,\n0x0fc0,\n0x1860,\n0x3030,\n0x3030,\n0x3030,\n0x3030,\n0x1860,\n0x0fc0,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 57 (0x39):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |     ****    |\n   |   **   **   |\n   |   **    **  |\n   |  **      *  |\n   |  **      ** |\n   |  **      ** |\n   |  **      ** |\n   |  **     *** |\n   |   **   * ** |\n   |    ****  ** |\n   |          ** |\n   |         **  |\n   |         **  |\n   |        **   |\n   |   ******    |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0780,\n0x18c0,\n0x1860,\n0x3020,\n0x3030,\n0x3030,\n0x3030,\n0x3070,\n0x18b0,\n0x0f30,\n0x0030,\n0x0060,\n0x0060,\n0x00c0,\n0x1f80,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 58 (0x3a):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |  **   |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |  **   |\n   |       |\n   |       |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 59 (0x3b):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |  **   |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |  **   |\n   |   *   |\n   |   *   |\n   |  *    |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x1000,\n0x1000,\n0x2000,\n0x0000,\n\n/* Character 60 (0x3c):\n   width 17\n   +-----------------+\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   |             *   |\n   |           **    |\n   |         ***     |\n   |        **       |\n   |      **         |\n   |    **           |\n   |  **             |\n   |    **           |\n   |      **         |\n   |        **       |\n   |         ***     |\n   |           **    |\n   |             *   |\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   +-----------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0004,0x0000,\n0x0018,0x0000,\n0x0070,0x0000,\n0x00c0,0x0000,\n0x0300,0x0000,\n0x0c00,0x0000,\n0x3000,0x0000,\n0x0c00,0x0000,\n0x0300,0x0000,\n0x00c0,0x0000,\n0x0070,0x0000,\n0x0018,0x0000,\n0x0004,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 61 (0x3d):\n   width 17\n   +-----------------+\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   |  ************   |\n   |                 |\n   |                 |\n   |  ************   |\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   +-----------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x3ffc,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x3ffc,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 62 (0x3e):\n   width 17\n   +-----------------+\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   |  *              |\n   |   **            |\n   |    ***          |\n   |      **         |\n   |        **       |\n   |          **     |\n   |            **   |\n   |          **     |\n   |        **       |\n   |      **         |\n   |    ***          |\n   |   **            |\n   |  *              |\n   |                 |\n   |                 |\n   |                 |\n   |                 |\n   +-----------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x2000,0x0000,\n0x1800,0x0000,\n0x0e00,0x0000,\n0x0300,0x0000,\n0x00c0,0x0000,\n0x0030,0x0000,\n0x000c,0x0000,\n0x0030,0x0000,\n0x00c0,0x0000,\n0x0300,0x0000,\n0x0e00,0x0000,\n0x1800,0x0000,\n0x2000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 63 (0x3f):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   | *****   |\n   |*    **  |\n   |      ** |\n   |      ** |\n   |      ** |\n   |     **  |\n   |    ***  |\n   |   ***   |\n   |   **    |\n   |  **     |\n   |  **     |\n   |  **     |\n   |         |\n   |         |\n   |  **     |\n   |         |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7c00,\n0x8600,\n0x0300,\n0x0300,\n0x0300,\n0x0600,\n0x0e00,\n0x1c00,\n0x1800,\n0x3000,\n0x3000,\n0x3000,\n0x0000,\n0x0000,\n0x3000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 64 (0x40):\n   width 18\n   +------------------+\n   |                  |\n   |                  |\n   |                  |\n   |       ******     |\n   |     **      **   |\n   |    **        **  |\n   |   *    ****   *  |\n   |  **   *   *    * |\n   |  *   **   *    * |\n   | *    *    *    * |\n   | *   **   **    * |\n   | *   **   **    * |\n   | *   **  ***   *  |\n   | *   ** * **  *   |\n   | **   **  ****    |\n   |  *               |\n   |   **     *       |\n   |     *****        |\n   |                  |\n   |                  |\n   |                  |\n   |                  |\n   +------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x01f8,0x0000,\n0x0606,0x0000,\n0x0c03,0x0000,\n0x10f1,0x0000,\n0x3110,0x8000,\n0x2310,0x8000,\n0x4210,0x8000,\n0x4630,0x8000,\n0x4630,0x8000,\n0x4671,0x0000,\n0x46b2,0x0000,\n0x633c,0x0000,\n0x2000,0x0000,\n0x1820,0x0000,\n0x07c0,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 65 (0x41):\n   width 14\n   +--------------+\n   |              |\n   |              |\n   |              |\n   |      **      |\n   |      ***     |\n   |     * **     |\n   |     * **     |\n   |    *   **    |\n   |    *   **    |\n   |    *    **   |\n   |   *     **   |\n   |   *     **   |\n   |  **********  |\n   |  *       **  |\n   | *         ** |\n   | *         ** |\n   | *         ** |\n   |*           **|\n   |              |\n   |              |\n   |              |\n   |              |\n   +--------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0300,\n0x0380,\n0x0580,\n0x0580,\n0x08c0,\n0x08c0,\n0x0860,\n0x1060,\n0x1060,\n0x3ff0,\n0x2030,\n0x4018,\n0x4018,\n0x4018,\n0x800c,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 66 (0x42):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |            |\n   |  ******    |\n   |  **   **   |\n   |  **    **  |\n   |  **    **  |\n   |  **    **  |\n   |  **    *   |\n   |  **   **   |\n   |  ******    |\n   |  **   ***  |\n   |  **    **  |\n   |  **     ** |\n   |  **     ** |\n   |  **     ** |\n   |  **    **  |\n   |  *******   |\n   |            |\n   |            |\n   |            |\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3f00,\n0x3180,\n0x30c0,\n0x30c0,\n0x30c0,\n0x3080,\n0x3180,\n0x3f00,\n0x31c0,\n0x30c0,\n0x3060,\n0x3060,\n0x3060,\n0x30c0,\n0x3f80,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 67 (0x43):\n   width 15\n   +---------------+\n   |               |\n   |               |\n   |               |\n   |     ******    |\n   |    **     **  |\n   |   **          |\n   |  **           |\n   |  **           |\n   | **            |\n   | **            |\n   | **            |\n   | **            |\n   | **            |\n   |  **           |\n   |  **           |\n   |   **          |\n   |    **      *  |\n   |     *******   |\n   |               |\n   |               |\n   |               |\n   |               |\n   +---------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x07e0,\n0x0c18,\n0x1800,\n0x3000,\n0x3000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x3000,\n0x3000,\n0x1800,\n0x0c08,\n0x07f0,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 68 (0x44):\n   width 16\n   +----------------+\n   |                |\n   |                |\n   |                |\n   |  *********     |\n   |  **      **    |\n   |  **       **   |\n   |  **        **  |\n   |  **        **  |\n   |  **         ** |\n   |  **         ** |\n   |  **         ** |\n   |  **         ** |\n   |  **         ** |\n   |  **        **  |\n   |  **        **  |\n   |  **       **   |\n   |  **      **    |\n   |  ********      |\n   |                |\n   |                |\n   |                |\n   |                |\n   +----------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3fe0,\n0x3030,\n0x3018,\n0x300c,\n0x300c,\n0x3006,\n0x3006,\n0x3006,\n0x3006,\n0x3006,\n0x300c,\n0x300c,\n0x3018,\n0x3030,\n0x3fc0,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 69 (0x45):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   |  *********|\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  ******** |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  *********|\n   |           |\n   |           |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3fe0,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3fc0,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3fe0,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 70 (0x46):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   |  ******** |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  *******  |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |           |\n   |           |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3fc0,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3f80,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 71 (0x47):\n   width 15\n   +---------------+\n   |               |\n   |               |\n   |               |\n   |     ******    |\n   |   ***     **  |\n   |  **           |\n   |  **           |\n   | **            |\n   | **            |\n   | **            |\n   | **            |\n   | **        **  |\n   | **        **  |\n   | **        **  |\n   |  **       **  |\n   |  ***      **  |\n   |   ***     **  |\n   |     *******   |\n   |               |\n   |               |\n   |               |\n   |               |\n   +---------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x07e0,\n0x1c18,\n0x3000,\n0x3000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6018,\n0x6018,\n0x6018,\n0x3018,\n0x3818,\n0x1c18,\n0x07f0,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 72 (0x48):\n   width 15\n   +---------------+\n   |               |\n   |               |\n   |               |\n   |  **        ** |\n   |  **        ** |\n   |  **        ** |\n   |  **        ** |\n   |  **        ** |\n   |  **        ** |\n   |  ************ |\n   |  **        ** |\n   |  **        ** |\n   |  **        ** |\n   |  **        ** |\n   |  **        ** |\n   |  **        ** |\n   |  **        ** |\n   |  **        ** |\n   |               |\n   |               |\n   |               |\n   |               |\n   +---------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x300c,\n0x300c,\n0x300c,\n0x300c,\n0x300c,\n0x300c,\n0x3ffc,\n0x300c,\n0x300c,\n0x300c,\n0x300c,\n0x300c,\n0x300c,\n0x300c,\n0x300c,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 73 (0x49):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |      |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 74 (0x4a):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |     **  |\n   |     **  |\n   |     **  |\n   |     **  |\n   |     **  |\n   |     **  |\n   |     **  |\n   |     **  |\n   |     **  |\n   |     **  |\n   |     **  |\n   |     **  |\n   |     **  |\n   |     **  |\n   |     **  |\n   |     **  |\n   |    **   |\n   |*****    |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0600,\n0x0600,\n0x0600,\n0x0600,\n0x0600,\n0x0600,\n0x0600,\n0x0600,\n0x0600,\n0x0600,\n0x0600,\n0x0600,\n0x0600,\n0x0600,\n0x0600,\n0x0600,\n0x0c00,\n0xf800,\n0x0000,\n\n/* Character 75 (0x4b):\n   width 14\n   +--------------+\n   |              |\n   |              |\n   |              |\n   |  **      *   |\n   |  **     *    |\n   |  **    *     |\n   |  **   *      |\n   |  **  *       |\n   |  **  *       |\n   |  ** *        |\n   |  ****        |\n   |  ** **       |\n   |  **  **      |\n   |  **   **     |\n   |  **    **    |\n   |  **     **   |\n   |  **      **  |\n   |  **       ** |\n   |              |\n   |              |\n   |              |\n   |              |\n   +--------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3020,\n0x3040,\n0x3080,\n0x3100,\n0x3200,\n0x3200,\n0x3400,\n0x3c00,\n0x3600,\n0x3300,\n0x3180,\n0x30c0,\n0x3060,\n0x3030,\n0x3018,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 76 (0x4c):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  *********|\n   |           |\n   |           |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3fe0,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 77 (0x4d):\n   width 18\n   +------------------+\n   |                  |\n   |                  |\n   |                  |\n   |  **         ***  |\n   |  ***        ***  |\n   |  ***       * **  |\n   |  * **      * **  |\n   |  * **      * **  |\n   |  * **     *  **  |\n   |  *  **    *  **  |\n   |  *  **    *  **  |\n   |  *  **   *   **  |\n   |  *   **  *   **  |\n   |  *   **  *   **  |\n   |  *    ***    **  |\n   |  *    ***    **  |\n   |  *    ***    **  |\n   |  *           **  |\n   |                  |\n   |                  |\n   |                  |\n   |                  |\n   +------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x3007,0x0000,\n0x3807,0x0000,\n0x380b,0x0000,\n0x2c0b,0x0000,\n0x2c0b,0x0000,\n0x2c13,0x0000,\n0x2613,0x0000,\n0x2613,0x0000,\n0x2623,0x0000,\n0x2323,0x0000,\n0x2323,0x0000,\n0x21c3,0x0000,\n0x21c3,0x0000,\n0x21c3,0x0000,\n0x2003,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 78 (0x4e):\n   width 16\n   +----------------+\n   |                |\n   |                |\n   |                |\n   |  **         *  |\n   |  ***        *  |\n   |  ****       *  |\n   |  * **       *  |\n   |  *  **      *  |\n   |  *  ***     *  |\n   |  *   ***    *  |\n   |  *    **    *  |\n   |  *    ***   *  |\n   |  *     ***  *  |\n   |  *      **  *  |\n   |  *       ** *  |\n   |  *       ****  |\n   |  *        ***  |\n   |  *         **  |\n   |                |\n   |                |\n   |                |\n   |                |\n   +----------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3004,\n0x3804,\n0x3c04,\n0x2c04,\n0x2604,\n0x2704,\n0x2384,\n0x2184,\n0x21c4,\n0x20e4,\n0x2064,\n0x2034,\n0x203c,\n0x201c,\n0x200c,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 79 (0x4f):\n   width 16\n   +----------------+\n   |                |\n   |                |\n   |                |\n   |     ******     |\n   |    **    **    |\n   |   **      **   |\n   |  **        **  |\n   |  **        **  |\n   | **          ** |\n   | **          ** |\n   | **          ** |\n   | **          ** |\n   | **          ** |\n   |  **        **  |\n   |  **        **  |\n   |   **      **   |\n   |    **    **    |\n   |     ******     |\n   |                |\n   |                |\n   |                |\n   |                |\n   +----------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x07e0,\n0x0c30,\n0x1818,\n0x300c,\n0x300c,\n0x6006,\n0x6006,\n0x6006,\n0x6006,\n0x6006,\n0x300c,\n0x300c,\n0x1818,\n0x0c30,\n0x07e0,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 80 (0x50):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |            |\n   |  *******   |\n   |  **    **  |\n   |  **     ** |\n   |  **     ** |\n   |  **     ** |\n   |  **     ** |\n   |  **    **  |\n   |  **   ***  |\n   |  ******    |\n   |  **        |\n   |  **        |\n   |  **        |\n   |  **        |\n   |  **        |\n   |  **        |\n   |            |\n   |            |\n   |            |\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3f80,\n0x30c0,\n0x3060,\n0x3060,\n0x3060,\n0x3060,\n0x30c0,\n0x31c0,\n0x3f00,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 81 (0x51):\n   width 16\n   +----------------+\n   |                |\n   |                |\n   |                |\n   |     ******     |\n   |    **    **    |\n   |   **      **   |\n   |  **        **  |\n   |  **        **  |\n   | **          ** |\n   | **          ** |\n   | **          ** |\n   | **          ** |\n   | **          ** |\n   |  **        **  |\n   |  **        **  |\n   |   **      **   |\n   |    **    **    |\n   |     ******     |\n   |          ***   |\n   |            *** |\n   |              **|\n   |                |\n   +----------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x07e0,\n0x0c30,\n0x1818,\n0x300c,\n0x300c,\n0x6006,\n0x6006,\n0x6006,\n0x6006,\n0x6006,\n0x300c,\n0x300c,\n0x1818,\n0x0c30,\n0x07e0,\n0x0038,\n0x000e,\n0x0003,\n0x0000,\n\n/* Character 82 (0x52):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |  *******    |\n   |  **    **   |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |  **    **   |\n   |  **   **    |\n   |  ******     |\n   |  **  **     |\n   |  **   **    |\n   |  **    **   |\n   |  **     **  |\n   |  **     **  |\n   |  **      ** |\n   |  **       **|\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3f80,\n0x30c0,\n0x3060,\n0x3060,\n0x3060,\n0x30c0,\n0x3180,\n0x3f00,\n0x3300,\n0x3180,\n0x30c0,\n0x3060,\n0x3060,\n0x3030,\n0x3018,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 83 (0x53):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   |   *****   |\n   |  **    *  |\n   | **        |\n   | **        |\n   | **        |\n   | ****      |\n   |  ****     |\n   |    ****   |\n   |      ***  |\n   |       *** |\n   |        ** |\n   |        ** |\n   |        ** |\n   | *     **  |\n   |  ******   |\n   |           |\n   |           |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1f00,\n0x3080,\n0x6000,\n0x6000,\n0x6000,\n0x7800,\n0x3c00,\n0x0f00,\n0x0380,\n0x01c0,\n0x00c0,\n0x00c0,\n0x00c0,\n0x4180,\n0x3f00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 84 (0x54):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   | ************|\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |      **     |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7ff8,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 85 (0x55):\n   width 15\n   +---------------+\n   |               |\n   |               |\n   |               |\n   |  **       **  |\n   |  **       **  |\n   |  **       **  |\n   |  **       **  |\n   |  **       **  |\n   |  **       **  |\n   |  **       **  |\n   |  **       **  |\n   |  **       **  |\n   |  **       **  |\n   |  **       **  |\n   |  **       **  |\n   |   **     **   |\n   |   **    ***   |\n   |     *****     |\n   |               |\n   |               |\n   |               |\n   |               |\n   +---------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3018,\n0x3018,\n0x3018,\n0x3018,\n0x3018,\n0x3018,\n0x3018,\n0x3018,\n0x3018,\n0x3018,\n0x3018,\n0x3018,\n0x1830,\n0x1870,\n0x07c0,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 86 (0x56):\n   width 14\n   +--------------+\n   |              |\n   |              |\n   |              |\n   |**          * |\n   | **        *  |\n   | **        *  |\n   | **        *  |\n   |  **      *   |\n   |  **      *   |\n   |   **     *   |\n   |   **    *    |\n   |   **    *    |\n   |    **   *    |\n   |    **  *     |\n   |    **  *     |\n   |     ***      |\n   |     ***      |\n   |      **      |\n   |              |\n   |              |\n   |              |\n   |              |\n   +--------------+ */\n0x0000,\n0x0000,\n0x0000,\n0xc008,\n0x6010,\n0x6010,\n0x6010,\n0x3020,\n0x3020,\n0x1820,\n0x1840,\n0x1840,\n0x0c40,\n0x0c80,\n0x0c80,\n0x0700,\n0x0700,\n0x0300,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 87 (0x57):\n   width 18\n   +------------------+\n   |                  |\n   |                  |\n   |                  |\n   |**      **       *|\n   |**      **       *|\n   | **    * **     * |\n   | **    * **     * |\n   | **    * **     * |\n   | ***   * **    ** |\n   |  **   *  **   *  |\n   |  **  *   **   *  |\n   |  **  *   **   *  |\n   |   ** *    ** *   |\n   |   ** *    ** *   |\n   |   ** *    ** *   |\n   |   ***     ** *   |\n   |    **      **    |\n   |    **      **    |\n   |                  |\n   |                  |\n   |                  |\n   |                  |\n   +------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0xc0c0,0x4000,\n0xc0c0,0x4000,\n0x6160,0x8000,\n0x6160,0x8000,\n0x6160,0x8000,\n0x7161,0x8000,\n0x3131,0x0000,\n0x3231,0x0000,\n0x3231,0x0000,\n0x1a1a,0x0000,\n0x1a1a,0x0000,\n0x1a1a,0x0000,\n0x1c1a,0x0000,\n0x0c0c,0x0000,\n0x0c0c,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 88 (0x58):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |***        * |\n   | **       *  |\n   |  **     *   |\n   |  ***    *   |\n   |   **   *    |\n   |    ** *     |\n   |    ***      |\n   |     **      |\n   |     ***     |\n   |    * **     |\n   |   *   **    |\n   |  *    ***   |\n   |  *     **   |\n   | *       **  |\n   |*        *** |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0xe010,\n0x6020,\n0x3040,\n0x3840,\n0x1880,\n0x0d00,\n0x0e00,\n0x0600,\n0x0700,\n0x0b00,\n0x1180,\n0x21c0,\n0x20c0,\n0x4060,\n0x8070,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 89 (0x59):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |**         * |\n   | **       *  |\n   | **       *  |\n   |  **     *   |\n   |   **   *    |\n   |   **   *    |\n   |    ** *     |\n   |    ** *     |\n   |     **      |\n   |     **      |\n   |     **      |\n   |     **      |\n   |     **      |\n   |     **      |\n   |     **      |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0xc010,\n0x6020,\n0x6020,\n0x3040,\n0x1880,\n0x1880,\n0x0d00,\n0x0d00,\n0x0600,\n0x0600,\n0x0600,\n0x0600,\n0x0600,\n0x0600,\n0x0600,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 90 (0x5a):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |  ********** |\n   |          ** |\n   |         **  |\n   |        **   |\n   |        **   |\n   |       **    |\n   |      **     |\n   |     **      |\n   |     **      |\n   |    **       |\n   |   **        |\n   |   **        |\n   |  **         |\n   | **          |\n   | *********** |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3ff0,\n0x0030,\n0x0060,\n0x00c0,\n0x00c0,\n0x0180,\n0x0300,\n0x0600,\n0x0600,\n0x0c00,\n0x1800,\n0x1800,\n0x3000,\n0x6000,\n0x7ff0,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 91 (0x5b):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |  **** |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  **** |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x3c00,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3c00,\n0x0000,\n\n/* Character 92 (0x5c):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   |   *       |\n   |   *       |\n   |    *      |\n   |    *      |\n   |    *      |\n   |     *     |\n   |     *     |\n   |     *     |\n   |     *     |\n   |      *    |\n   |      *    |\n   |      *    |\n   |      *    |\n   |       *   |\n   |       *   |\n   |       *   |\n   |        *  |\n   |        *  |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1000,\n0x1000,\n0x0800,\n0x0800,\n0x0800,\n0x0400,\n0x0400,\n0x0400,\n0x0400,\n0x0200,\n0x0200,\n0x0200,\n0x0200,\n0x0100,\n0x0100,\n0x0100,\n0x0080,\n0x0080,\n0x0000,\n\n/* Character 93 (0x5d):\n   width 7\n   +-------+\n   |       |\n   |       |\n   | ****  |\n   |   **  |\n   |   **  |\n   |   **  |\n   |   **  |\n   |   **  |\n   |   **  |\n   |   **  |\n   |   **  |\n   |   **  |\n   |   **  |\n   |   **  |\n   |   **  |\n   |   **  |\n   |   **  |\n   |   **  |\n   |   **  |\n   |   **  |\n   | ****  |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x7800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x1800,\n0x7800,\n0x0000,\n\n/* Character 94 (0x5e):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |      *      |\n   |      *      |\n   |     ***     |\n   |     * *     |\n   |    ** **    |\n   |    *   *    |\n   |   **   **   |\n   |   *     *   |\n   |  **     **  |\n   |  *       *  |\n   | **       ** |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0200,\n0x0200,\n0x0700,\n0x0500,\n0x0d80,\n0x0880,\n0x18c0,\n0x1040,\n0x3060,\n0x2020,\n0x6030,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 95 (0x5f):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   | ********* |\n   |           |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x7fc0,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 96 (0x60):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |    ***      |\n   |     ***     |\n   |      ***    |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0e00,\n0x0700,\n0x0380,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 97 (0x61):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |   ****     |\n   |  *   **    |\n   |       **   |\n   |       **   |\n   |       **   |\n   |   ******   |\n   |  **   **   |\n   | **    **   |\n   | **    **   |\n   | **   ***   |\n   |  ****  *** |\n   |            |\n   |            |\n   |            |\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x1e00,\n0x2300,\n0x0180,\n0x0180,\n0x0180,\n0x1f80,\n0x3180,\n0x6180,\n0x6180,\n0x6380,\n0x3ce0,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 98 (0x62):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |  **         |\n   |  **         |\n   |  **         |\n   |  **         |\n   |  **         |\n   |  **  ****   |\n   |  ** *   **  |\n   |  ***     ** |\n   |  **      ** |\n   |  **      ** |\n   |  **      ** |\n   |  **      ** |\n   |  **      ** |\n   |  **     **  |\n   |  ***    **  |\n   |  ** ****    |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x33c0,\n0x3460,\n0x3830,\n0x3030,\n0x3030,\n0x3030,\n0x3030,\n0x3030,\n0x3060,\n0x3860,\n0x3780,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 99 (0x63):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |    ****** |\n   |  ***      |\n   |  **       |\n   | **        |\n   | **        |\n   | **        |\n   | **        |\n   | **        |\n   |  **       |\n   |  ***    * |\n   |    *****  |\n   |           |\n   |           |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0fc0,\n0x3800,\n0x3000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x6000,\n0x3000,\n0x3840,\n0x0f80,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 100 (0x64):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |         **  |\n   |         **  |\n   |         **  |\n   |         **  |\n   |         **  |\n   |    **** **  |\n   |  **    ***  |\n   |  **     **  |\n   | **      **  |\n   | **      **  |\n   | **      **  |\n   | **      **  |\n   | **      **  |\n   | **     ***  |\n   |  **   * **  |\n   |   ****  **  |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0060,\n0x0060,\n0x0060,\n0x0060,\n0x0060,\n0x0f60,\n0x30e0,\n0x3060,\n0x6060,\n0x6060,\n0x6060,\n0x6060,\n0x6060,\n0x60e0,\n0x3160,\n0x1e60,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 101 (0x65):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |    *****   |\n   |  **    **  |\n   |  **     ** |\n   | **      ** |\n   | ********** |\n   | **         |\n   | **         |\n   | **         |\n   |  **        |\n   |  ***     * |\n   |    ******  |\n   |            |\n   |            |\n   |            |\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0f80,\n0x30c0,\n0x3060,\n0x6060,\n0x7fe0,\n0x6000,\n0x6000,\n0x6000,\n0x3000,\n0x3820,\n0x0fc0,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 102 (0x66):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |   *****|\n   |  **    |\n   |  **    |\n   |  **    |\n   |  **    |\n   |******* |\n   |  **    |\n   |  **    |\n   |  **    |\n   |  **    |\n   |  **    |\n   |  **    |\n   |  **    |\n   |  **    |\n   |  **    |\n   |  **    |\n   |        |\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x1f00,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0xfe00,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 103 (0x67):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |    **** **  |\n   |  **    ***  |\n   |  **     **  |\n   | **      **  |\n   | **      **  |\n   | **      **  |\n   | **      **  |\n   | **      **  |\n   | **     ***  |\n   |  **   * **  |\n   |   ****  **  |\n   |         **  |\n   |         *   |\n   |  *     **   |\n   |   *****     |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0f60,\n0x30e0,\n0x3060,\n0x6060,\n0x6060,\n0x6060,\n0x6060,\n0x6060,\n0x60e0,\n0x3160,\n0x1e60,\n0x0060,\n0x0040,\n0x20c0,\n0x1f00,\n\n/* Character 104 (0x68):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |  **         |\n   |  **         |\n   |  **         |\n   |  **         |\n   |  **         |\n   |  **  ****   |\n   |  ** *   **  |\n   |  ***    **  |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x33c0,\n0x3460,\n0x3860,\n0x3060,\n0x3060,\n0x3060,\n0x3060,\n0x3060,\n0x3060,\n0x3060,\n0x3060,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 105 (0x69):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |  **  |\n   |      |\n   |      |\n   |      |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |      |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 106 (0x6a):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |    **  |\n   |        |\n   |        |\n   |        |\n   |    **  |\n   |    **  |\n   |    **  |\n   |    **  |\n   |    **  |\n   |    **  |\n   |    **  |\n   |    **  |\n   |    **  |\n   |    **  |\n   |    **  |\n   |    **  |\n   |    **  |\n   |*   *   |\n   | ***    |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0c00,\n0x0000,\n0x0000,\n0x0000,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x0c00,\n0x8800,\n0x7000,\n\n/* Character 107 (0x6b):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |  **        |\n   |  **        |\n   |  **        |\n   |  **        |\n   |  **        |\n   |  **     *  |\n   |  **    *   |\n   |  **   *    |\n   |  **  *     |\n   |  ** *      |\n   |  ****      |\n   |  ** **     |\n   |  **  **    |\n   |  **   **   |\n   |  **    **  |\n   |  **     ** |\n   |            |\n   |            |\n   |            |\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3040,\n0x3080,\n0x3100,\n0x3200,\n0x3400,\n0x3c00,\n0x3600,\n0x3300,\n0x3180,\n0x30c0,\n0x3060,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 108 (0x6c):\n   width 6\n   +------+\n   |      |\n   |      |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |  **  |\n   |      |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 109 (0x6d):\n   width 20\n   +--------------------+\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |  **  ****   ****   |\n   |  ** *   ** *   **  |\n   |  ***    ***    **  |\n   |  **     **     **  |\n   |  **     **     **  |\n   |  **     **     **  |\n   |  **     **     **  |\n   |  **     **     **  |\n   |  **     **     **  |\n   |  **     **     **  |\n   |  **     **     **  |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   +--------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x33c7,0x8000,\n0x3468,0xc000,\n0x3870,0xc000,\n0x3060,0xc000,\n0x3060,0xc000,\n0x3060,0xc000,\n0x3060,0xc000,\n0x3060,0xc000,\n0x3060,0xc000,\n0x3060,0xc000,\n0x3060,0xc000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 110 (0x6e):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |  **  ****   |\n   |  ** *   **  |\n   |  ***    **  |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x33c0,\n0x3460,\n0x3860,\n0x3060,\n0x3060,\n0x3060,\n0x3060,\n0x3060,\n0x3060,\n0x3060,\n0x3060,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 111 (0x6f):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |    *****    |\n   |  ***   ***  |\n   |  **     **  |\n   | **       ** |\n   | **       ** |\n   | **       ** |\n   | **       ** |\n   | **       ** |\n   |  **     **  |\n   |  ***   ***  |\n   |    *****    |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0f80,\n0x38e0,\n0x3060,\n0x6030,\n0x6030,\n0x6030,\n0x6030,\n0x6030,\n0x3060,\n0x38e0,\n0x0f80,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 112 (0x70):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |  **  ****   |\n   |  ** *   **  |\n   |  ***     ** |\n   |  **      ** |\n   |  **      ** |\n   |  **      ** |\n   |  **      ** |\n   |  **      ** |\n   |  **     **  |\n   |  ***    **  |\n   |  ** ****    |\n   |  **         |\n   |  **         |\n   |  **         |\n   |  **         |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x33c0,\n0x3460,\n0x3830,\n0x3030,\n0x3030,\n0x3030,\n0x3030,\n0x3030,\n0x3060,\n0x3860,\n0x3780,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n\n/* Character 113 (0x71):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |    **** **  |\n   |  **    ***  |\n   |  **     **  |\n   | **      **  |\n   | **      **  |\n   | **      **  |\n   | **      **  |\n   | **      **  |\n   | **     ***  |\n   |  **   * **  |\n   |   ****  **  |\n   |         **  |\n   |         **  |\n   |         **  |\n   |         **  |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0f60,\n0x30e0,\n0x3060,\n0x6060,\n0x6060,\n0x6060,\n0x6060,\n0x6060,\n0x60e0,\n0x3160,\n0x1e60,\n0x0060,\n0x0060,\n0x0060,\n0x0060,\n\n/* Character 114 (0x72):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |  **  ** |\n   |  ** *   |\n   |  ***    |\n   |  **     |\n   |  **     |\n   |  **     |\n   |  **     |\n   |  **     |\n   |  **     |\n   |  **     |\n   |  **     |\n   |         |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3300,\n0x3400,\n0x3800,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 115 (0x73):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |   *****   |\n   |  **       |\n   |  **       |\n   |  **       |\n   |  ****     |\n   |    ****   |\n   |      ***  |\n   |       **  |\n   |       **  |\n   |  *   **   |\n   |   ****    |\n   |           |\n   |           |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x1f00,\n0x3000,\n0x3000,\n0x3000,\n0x3c00,\n0x0f00,\n0x0380,\n0x0180,\n0x0180,\n0x2300,\n0x1e00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 116 (0x74):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |  **    |\n   |  **    |\n   | ****** |\n   |  **    |\n   |  **    |\n   |  **    |\n   |  **    |\n   |  **    |\n   |  **    |\n   |  **    |\n   |  **    |\n   |  **    |\n   |   **** |\n   |        |\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3000,\n0x3000,\n0x7e00,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x3000,\n0x1e00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 117 (0x75):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |  **    ***  |\n   |  **   * **  |\n   |   ****  **  |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3060,\n0x3060,\n0x3060,\n0x3060,\n0x3060,\n0x3060,\n0x3060,\n0x3060,\n0x30e0,\n0x3160,\n0x1e60,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 118 (0x76):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |**        *|\n   | **      * |\n   | **      * |\n   | **      * |\n   |  **    *  |\n   |  **    *  |\n   |   **  *   |\n   |   **  *   |\n   |   ** *    |\n   |    ***    |\n   |    ***    |\n   |           |\n   |           |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0xc020,\n0x6040,\n0x6040,\n0x6040,\n0x3080,\n0x3080,\n0x1900,\n0x1900,\n0x1a00,\n0x0e00,\n0x0e00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 119 (0x77):\n   width 16\n   +----------------+\n   |                |\n   |                |\n   |                |\n   |                |\n   |                |\n   |                |\n   |                |\n   |**     **      *|\n   |**     **     * |\n   | **    **     * |\n   | **   * **    * |\n   | **   * **   *  |\n   | ***  *  *   *  |\n   |  ** *   **  *  |\n   |  ** *   ** *   |\n   |  ** *   ** *   |\n   |   **     ***   |\n   |   **     **    |\n   |                |\n   |                |\n   |                |\n   |                |\n   +----------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0xc181,\n0xc182,\n0x6182,\n0x62c2,\n0x62c4,\n0x7244,\n0x3464,\n0x3468,\n0x3468,\n0x1838,\n0x1830,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 120 (0x78):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   | ***       * |\n   |  ***     *  |\n   |   **    *   |\n   |    **  *    |\n   |     ***     |\n   |     ***     |\n   |     ***     |\n   |    *  **    |\n   |   *    **   |\n   |  *     ***  |\n   | *       *** |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x7010,\n0x3820,\n0x1840,\n0x0c80,\n0x0700,\n0x0700,\n0x0700,\n0x0980,\n0x10c0,\n0x20e0,\n0x4070,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 121 (0x79):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |**        *|\n   | **      * |\n   | **      * |\n   | **      * |\n   |  **    *  |\n   |  **    *  |\n   |   **  *   |\n   |   **  *   |\n   |   ** *    |\n   |    ***    |\n   |    ***    |\n   |     *     |\n   |     *     |\n   |    *      |\n   |    *      |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0xc020,\n0x6040,\n0x6040,\n0x6040,\n0x3080,\n0x3080,\n0x1900,\n0x1900,\n0x1a00,\n0x0e00,\n0x0e00,\n0x0400,\n0x0400,\n0x0800,\n0x0800,\n\n/* Character 122 (0x7a):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   | ********** |\n   |         ** |\n   |        **  |\n   |       **   |\n   |      **    |\n   |     **     |\n   |    **      |\n   |   **       |\n   |  **        |\n   | **         |\n   | ********** |\n   |            |\n   |            |\n   |            |\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x7fe0,\n0x0060,\n0x00c0,\n0x0180,\n0x0300,\n0x0600,\n0x0c00,\n0x1800,\n0x3000,\n0x6000,\n0x7fe0,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 123 (0x7b):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |   **  |\n   |  *    |\n   | **    |\n   | **    |\n   | ***   |\n   |  **   |\n   |  **   |\n   |  **   |\n   |  *    |\n   |**     |\n   |  *    |\n   |  **   |\n   |  **   |\n   |  **   |\n   | ***   |\n   | **    |\n   | **    |\n   |  *    |\n   |   **  |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x1800,\n0x2000,\n0x6000,\n0x6000,\n0x7000,\n0x3000,\n0x3000,\n0x3000,\n0x2000,\n0xc000,\n0x2000,\n0x3000,\n0x3000,\n0x3000,\n0x7000,\n0x6000,\n0x6000,\n0x2000,\n0x1800,\n0x0000,\n\n/* Character 124 (0x7c):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x0000,\n\n/* Character 125 (0x7d):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |  **   |\n   |    *  |\n   |    ** |\n   |    ** |\n   |   *** |\n   |   **  |\n   |   **  |\n   |   **  |\n   |    *  |\n   |     **|\n   |    *  |\n   |   **  |\n   |   **  |\n   |   **  |\n   |   *** |\n   |    ** |\n   |    ** |\n   |    *  |\n   |  **   |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x3000,\n0x0800,\n0x0c00,\n0x0c00,\n0x1c00,\n0x1800,\n0x1800,\n0x1800,\n0x0800,\n0x0600,\n0x0800,\n0x1800,\n0x1800,\n0x1800,\n0x1c00,\n0x0c00,\n0x0c00,\n0x0800,\n0x3000,\n0x0000,\n\n/* Character 126 (0x7e):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |  ***     ** |\n   | **  *    ** |\n   | **   **  ** |\n   | **     ***  |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3830,\n0x6430,\n0x6330,\n0x60e0,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 127 (0x7f):\n   width 13\n   +-------------+\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   | *         * |\n   |  * ***** *  |\n   |   **   **   |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |  **     **  |\n   |   **   **   |\n   |  * ***** *  |\n   | *         * |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x4010,\n0x2fa0,\n0x18c0,\n0x3060,\n0x3060,\n0x3060,\n0x3060,\n0x3060,\n0x18c0,\n0x2fa0,\n0x4010,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n};\n\n/* Character->glyph mapping. */\nstatic const unsigned short _lucidasans15_offset[] = {\n  0,\t/* (0x20) */\n  22,\t/* (0x21) */\n  44,\t/* (0x22) */\n  66,\t/* (0x23) */\n  88,\t/* (0x24) */\n  110,\t/* (0x25) */\n  132,\t/* (0x26) */\n  154,\t/* (0x27) */\n  176,\t/* (0x28) */\n  198,\t/* (0x29) */\n  220,\t/* (0x2a) */\n  242,\t/* (0x2b) */\n  286,\t/* (0x2c) */\n  308,\t/* (0x2d) */\n  330,\t/* (0x2e) */\n  352,\t/* (0x2f) */\n  374,\t/* (0x30) */\n  396,\t/* (0x31) */\n  418,\t/* (0x32) */\n  440,\t/* (0x33) */\n  462,\t/* (0x34) */\n  484,\t/* (0x35) */\n  506,\t/* (0x36) */\n  528,\t/* (0x37) */\n  550,\t/* (0x38) */\n  572,\t/* (0x39) */\n  594,\t/* (0x3a) */\n  616,\t/* (0x3b) */\n  638,\t/* (0x3c) */\n  682,\t/* (0x3d) */\n  726,\t/* (0x3e) */\n  770,\t/* (0x3f) */\n  792,\t/* (0x40) */\n  836,\t/* (0x41) */\n  858,\t/* (0x42) */\n  880,\t/* (0x43) */\n  902,\t/* (0x44) */\n  924,\t/* (0x45) */\n  946,\t/* (0x46) */\n  968,\t/* (0x47) */\n  990,\t/* (0x48) */\n  1012,\t/* (0x49) */\n  1034,\t/* (0x4a) */\n  1056,\t/* (0x4b) */\n  1078,\t/* (0x4c) */\n  1100,\t/* (0x4d) */\n  1144,\t/* (0x4e) */\n  1166,\t/* (0x4f) */\n  1188,\t/* (0x50) */\n  1210,\t/* (0x51) */\n  1232,\t/* (0x52) */\n  1254,\t/* (0x53) */\n  1276,\t/* (0x54) */\n  1298,\t/* (0x55) */\n  1320,\t/* (0x56) */\n  1342,\t/* (0x57) */\n  1386,\t/* (0x58) */\n  1408,\t/* (0x59) */\n  1430,\t/* (0x5a) */\n  1452,\t/* (0x5b) */\n  1474,\t/* (0x5c) */\n  1496,\t/* (0x5d) */\n  1518,\t/* (0x5e) */\n  1540,\t/* (0x5f) */\n  1562,\t/* (0x60) */\n  1584,\t/* (0x61) */\n  1606,\t/* (0x62) */\n  1628,\t/* (0x63) */\n  1650,\t/* (0x64) */\n  1672,\t/* (0x65) */\n  1694,\t/* (0x66) */\n  1716,\t/* (0x67) */\n  1738,\t/* (0x68) */\n  1760,\t/* (0x69) */\n  1782,\t/* (0x6a) */\n  1804,\t/* (0x6b) */\n  1826,\t/* (0x6c) */\n  1848,\t/* (0x6d) */\n  1892,\t/* (0x6e) */\n  1914,\t/* (0x6f) */\n  1936,\t/* (0x70) */\n  1958,\t/* (0x71) */\n  1980,\t/* (0x72) */\n  2002,\t/* (0x73) */\n  2024,\t/* (0x74) */\n  2046,\t/* (0x75) */\n  2068,\t/* (0x76) */\n  2090,\t/* (0x77) */\n  2112,\t/* (0x78) */\n  2134,\t/* (0x79) */\n  2156,\t/* (0x7a) */\n  2178,\t/* (0x7b) */\n  2200,\t/* (0x7c) */\n  2222,\t/* (0x7d) */\n  2244,\t/* (0x7e) */\n  2266,\t/* (0x7f) */\n  2266,\t/* (0x80) */\n  2266,\t/* (0x81) */\n  2266,\t/* (0x82) */\n  2266,\t/* (0x83) */\n  2266,\t/* (0x84) */\n  2266,\t/* (0x85) */\n  2266,\t/* (0x86) */\n  2266,\t/* (0x87) */\n  2266,\t/* (0x88) */\n  2266,\t/* (0x89) */\n  2266,\t/* (0x8a) */\n  2266,\t/* (0x8b) */\n  2266,\t/* (0x8c) */\n  2266,\t/* (0x8d) */\n  2266,\t/* (0x8e) */\n  2266,\t/* (0x8f) */\n  2266,\t/* (0x90) */\n  2266,\t/* (0x91) */\n  2266,\t/* (0x92) */\n  2266,\t/* (0x93) */\n  2266,\t/* (0x94) */\n  2266,\t/* (0x95) */\n  2266,\t/* (0x96) */\n  2266,\t/* (0x97) */\n  2266,\t/* (0x98) */\n  2266,\t/* (0x99) */\n  2266,\t/* (0x9a) */\n  2266,\t/* (0x9b) */\n  2266,\t/* (0x9c) */\n  2266,\t/* (0x9d) */\n  2266,\t/* (0x9e) */\n  2266,\t/* (0x9f) */\n  2266,\t/* (0xa0) */\n  2266,\t/* (0xa1) */\n  2266,\t/* (0xa2) */\n  2266,\t/* (0xa3) */\n  2266,\t/* (0xa4) */\n};\n\n/* Character width data. */\nstatic const unsigned char _lucidasans15_width[] = {\n  7,\t/* (0x20) */\n  7,\t/* (0x21) */\n  8,\t/* (0x22) */\n  13,\t/* (0x23) */\n  13,\t/* (0x24) */\n  14,\t/* (0x25) */\n  15,\t/* (0x26) */\n  5,\t/* (0x27) */\n  7,\t/* (0x28) */\n  7,\t/* (0x29) */\n  10,\t/* (0x2a) */\n  17,\t/* (0x2b) */\n  7,\t/* (0x2c) */\n  12,\t/* (0x2d) */\n  7,\t/* (0x2e) */\n  11,\t/* (0x2f) */\n  13,\t/* (0x30) */\n  13,\t/* (0x31) */\n  13,\t/* (0x32) */\n  13,\t/* (0x33) */\n  13,\t/* (0x34) */\n  13,\t/* (0x35) */\n  13,\t/* (0x36) */\n  13,\t/* (0x37) */\n  13,\t/* (0x38) */\n  13,\t/* (0x39) */\n  7,\t/* (0x3a) */\n  7,\t/* (0x3b) */\n  17,\t/* (0x3c) */\n  17,\t/* (0x3d) */\n  17,\t/* (0x3e) */\n  9,\t/* (0x3f) */\n  18,\t/* (0x40) */\n  14,\t/* (0x41) */\n  12,\t/* (0x42) */\n  15,\t/* (0x43) */\n  16,\t/* (0x44) */\n  11,\t/* (0x45) */\n  11,\t/* (0x46) */\n  15,\t/* (0x47) */\n  15,\t/* (0x48) */\n  6,\t/* (0x49) */\n  9,\t/* (0x4a) */\n  14,\t/* (0x4b) */\n  11,\t/* (0x4c) */\n  18,\t/* (0x4d) */\n  16,\t/* (0x4e) */\n  16,\t/* (0x4f) */\n  12,\t/* (0x50) */\n  16,\t/* (0x51) */\n  13,\t/* (0x52) */\n  11,\t/* (0x53) */\n  13,\t/* (0x54) */\n  15,\t/* (0x55) */\n  14,\t/* (0x56) */\n  18,\t/* (0x57) */\n  13,\t/* (0x58) */\n  13,\t/* (0x59) */\n  13,\t/* (0x5a) */\n  7,\t/* (0x5b) */\n  11,\t/* (0x5c) */\n  7,\t/* (0x5d) */\n  13,\t/* (0x5e) */\n  11,\t/* (0x5f) */\n  13,\t/* (0x60) */\n  12,\t/* (0x61) */\n  13,\t/* (0x62) */\n  11,\t/* (0x63) */\n  13,\t/* (0x64) */\n  12,\t/* (0x65) */\n  8,\t/* (0x66) */\n  13,\t/* (0x67) */\n  13,\t/* (0x68) */\n  6,\t/* (0x69) */\n  8,\t/* (0x6a) */\n  12,\t/* (0x6b) */\n  6,\t/* (0x6c) */\n  20,\t/* (0x6d) */\n  13,\t/* (0x6e) */\n  13,\t/* (0x6f) */\n  13,\t/* (0x70) */\n  13,\t/* (0x71) */\n  9,\t/* (0x72) */\n  11,\t/* (0x73) */\n  8,\t/* (0x74) */\n  13,\t/* (0x75) */\n  11,\t/* (0x76) */\n  16,\t/* (0x77) */\n  13,\t/* (0x78) */\n  11,\t/* (0x79) */\n  12,\t/* (0x7a) */\n  7,\t/* (0x7b) */\n  8,\t/* (0x7c) */\n  7,\t/* (0x7d) */\n  13,\t/* (0x7e) */\n  13,\t/* (0x7f) */\n  13,\t/* (0x80) */\n  13,\t/* (0x81) */\n  13,\t/* (0x82) */\n  13,\t/* (0x83) */\n  13,\t/* (0x84) */\n  13,\t/* (0x85) */\n  13,\t/* (0x86) */\n  13,\t/* (0x87) */\n  13,\t/* (0x88) */\n  13,\t/* (0x89) */\n  13,\t/* (0x8a) */\n  13,\t/* (0x8b) */\n  13,\t/* (0x8c) */\n  13,\t/* (0x8d) */\n  13,\t/* (0x8e) */\n  13,\t/* (0x8f) */\n  13,\t/* (0x90) */\n  13,\t/* (0x91) */\n  13,\t/* (0x92) */\n  13,\t/* (0x93) */\n  13,\t/* (0x94) */\n  13,\t/* (0x95) */\n  13,\t/* (0x96) */\n  13,\t/* (0x97) */\n  13,\t/* (0x98) */\n  13,\t/* (0x99) */\n  13,\t/* (0x9a) */\n  13,\t/* (0x9b) */\n  13,\t/* (0x9c) */\n  13,\t/* (0x9d) */\n  13,\t/* (0x9e) */\n  13,\t/* (0x9f) */\n  13,\t/* (0xa0) */\n  13,\t/* (0xa1) */\n  13,\t/* (0xa2) */\n  13,\t/* (0xa3) */\n  13,\t/* (0xa4) */\n};\n\n/* Exported structure definition. */\nconst struct gpanel_font_t font_lucidasans15 = {\n  \"lucidasans15\",\n  20,\n  22,\n  18,\n  32,\n  133,\n  _lucidasans15_bits,\n  _lucidasans15_offset,\n  _lucidasans15_width,\n  164,\n  sizeof(_lucidasans15_bits) / sizeof(_lucidasans15_bits[0]),\n};\n"
  },
  {
    "path": "share/examples/gpanel/fonts/lucidasans28.c",
    "content": "/* Generated by convbdf on Sun Nov 22 13:48:53 2015. */\n#include <sys/gpanel.h>\n\n/* Font information:\n   name: lucidasans28\n   facename: -FreeType-Lucida Sans Unicode-Medium-R-Normal--39-280-100-100-P-174-ISO10646-1\n   w x h: 36x39\n   size: 133\n   ascent: 31\n   descent: 8\n   first char: 32 (0x20)\n   last char: 164 (0xa4)\n   default char: 164 (0xa4)\n   proportional: yes\n   Copyright  1993 Bigelow & Holmes Inc. All rights reserved. Pat. Des. 289,420. Pats. Pend.\n*/\n\n/* Font character bitmap data. */\nstatic const unsigned short _lucidasans28_bits[] = {\n\n/* Character 32 (0x20):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 33 (0x21):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |            |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |            |\n   |            |\n   |            |\n   |            |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 34 (0x22):\n   width 15\n   +---------------+\n   |               |\n   |  ****   ****  |\n   |  ****   ****  |\n   |  ****   ****  |\n   |  ****   ****  |\n   |  ****   ****  |\n   |  ****   ****  |\n   |  ****   ****  |\n   |  ****   ****  |\n   |  ****   ****  |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   +---------------+ */\n0x0000,\n0x3c78,\n0x3c78,\n0x3c78,\n0x3c78,\n0x3c78,\n0x3c78,\n0x3c78,\n0x3c78,\n0x3c78,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 35 (0x23):\n   width 25\n   +-------------------------+\n   |                         |\n   |                         |\n   |                         |\n   |           **     **     |\n   |          ***    ***     |\n   |          **     **      |\n   |          **     **      |\n   |          **     **      |\n   |         ***    ***      |\n   |         ***    ***      |\n   |         **     **       |\n   |         **     **       |\n   |  ********************** |\n   |  ********************** |\n   |        **     **        |\n   |        **     **        |\n   |        **     **        |\n   |       ***    ***        |\n   |       **     **         |\n   |       **     **         |\n   |       **     **         |\n   |**********************   |\n   |**********************   |\n   |      **     **          |\n   |      **     **          |\n   |     ***    ***          |\n   |     **     **           |\n   |     **     **           |\n   |     **     **           |\n   |    ***    ***           |\n   |    **     **            |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0018,0x3000,\n0x0038,0x7000,\n0x0030,0x6000,\n0x0030,0x6000,\n0x0030,0x6000,\n0x0070,0xe000,\n0x0070,0xe000,\n0x0060,0xc000,\n0x0060,0xc000,\n0x3fff,0xff00,\n0x3fff,0xff00,\n0x00c1,0x8000,\n0x00c1,0x8000,\n0x00c1,0x8000,\n0x01c3,0x8000,\n0x0183,0x0000,\n0x0183,0x0000,\n0x0183,0x0000,\n0xffff,0xfc00,\n0xffff,0xfc00,\n0x0306,0x0000,\n0x0306,0x0000,\n0x070e,0x0000,\n0x060c,0x0000,\n0x060c,0x0000,\n0x060c,0x0000,\n0x0e1c,0x0000,\n0x0c18,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 36 (0x24):\n   width 25\n   +-------------------------+\n   |                         |\n   |            **           |\n   |            **           |\n   |          ********       |\n   |        ************     |\n   |      **************     |\n   |      ***** **    **     |\n   |     ****   **           |\n   |     ***    **           |\n   |     ***    **           |\n   |     ***    **           |\n   |     ***    **           |\n   |      ***   **           |\n   |      ***** **           |\n   |       *******           |\n   |        ******           |\n   |         ******          |\n   |           ******        |\n   |            ******       |\n   |            *******      |\n   |            **  ***      |\n   |            **  ****     |\n   |            **   ***     |\n   |            **   ***     |\n   |            **   ***     |\n   |            **   ***     |\n   |    *       **  ***      |\n   |    ****    ** ****      |\n   |    **************       |\n   |     ************        |\n   |        ********         |\n   |            **           |\n   |            **           |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   +-------------------------+ */\n0x0000,0x0000,\n0x000c,0x0000,\n0x000c,0x0000,\n0x003f,0xc000,\n0x00ff,0xf000,\n0x03ff,0xf000,\n0x03ec,0x3000,\n0x078c,0x0000,\n0x070c,0x0000,\n0x070c,0x0000,\n0x070c,0x0000,\n0x070c,0x0000,\n0x038c,0x0000,\n0x03ec,0x0000,\n0x01fc,0x0000,\n0x00fc,0x0000,\n0x007e,0x0000,\n0x001f,0x8000,\n0x000f,0xc000,\n0x000f,0xe000,\n0x000c,0xe000,\n0x000c,0xf000,\n0x000c,0x7000,\n0x000c,0x7000,\n0x000c,0x7000,\n0x000c,0x7000,\n0x080c,0xe000,\n0x0f0d,0xe000,\n0x0fff,0xc000,\n0x07ff,0x8000,\n0x00ff,0x0000,\n0x000c,0x0000,\n0x000c,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 37 (0x25):\n   width 26\n   +--------------------------+\n   |                          |\n   |                          |\n   |                      *** |\n   |   *****              *** |\n   |  ********           ***  |\n   | ****  ****         ***   |\n   | ***    ***        ***    |\n   |***      ***       ***    |\n   |***      ***      ***     |\n   |***      ***     ***      |\n   |***      ***    ***       |\n   |***      ***    ***       |\n   |***      ***   ***        |\n   | ***    ***   ***         |\n   | ****  ****  ***          |\n   |  ********   ***          |\n   |   ******   ***           |\n   |           ***   *****    |\n   |          ***   ********  |\n   |          ***  ****  **** |\n   |         ***   ***    *** |\n   |        ***   ***      ***|\n   |       ***    ***      ***|\n   |       ***    ***      ***|\n   |      ***     ***      ***|\n   |     ***      ***      ***|\n   |    ***       ***      ***|\n   |    ***        ***    *** |\n   |   ***         ****  **** |\n   |  ***           ********  |\n   | ***             ******   |\n   | ***                      |\n   |                          |\n   |                          |\n   |                          |\n   |                          |\n   |                          |\n   |                          |\n   |                          |\n   +--------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0380,\n0x1f00,0x0380,\n0x3fc0,0x0700,\n0x79e0,0x0e00,\n0x70e0,0x1c00,\n0xe070,0x1c00,\n0xe070,0x3800,\n0xe070,0x7000,\n0xe070,0xe000,\n0xe070,0xe000,\n0xe071,0xc000,\n0x70e3,0x8000,\n0x79e7,0x0000,\n0x3fc7,0x0000,\n0x1f8e,0x0000,\n0x001c,0x7c00,\n0x0038,0xff00,\n0x0039,0xe780,\n0x0071,0xc380,\n0x00e3,0x81c0,\n0x01c3,0x81c0,\n0x01c3,0x81c0,\n0x0383,0x81c0,\n0x0703,0x81c0,\n0x0e03,0x81c0,\n0x0e01,0xc380,\n0x1c01,0xe780,\n0x3800,0xff00,\n0x7000,0x7e00,\n0x7000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 38 (0x26):\n   width 27\n   +---------------------------+\n   |                           |\n   |                           |\n   |                           |\n   |          *****            |\n   |        *********          |\n   |       ***********         |\n   |      *****   *****        |\n   |      ****     ****        |\n   |      ****     ****        |\n   |      ****     ****        |\n   |      ****     ****        |\n   |       ****   ****         |\n   |       ****  ****          |\n   |        ********           |\n   |       ********            |\n   |     ********              |\n   |   ***** *****       ****  |\n   |   ****   ****       ****  |\n   |  ****     ****      ****  |\n   | ****      *****     ****  |\n   | ****       ****     ***   |\n   | ****        ****    ***   |\n   | ****        *****  ****   |\n   | ****         ***** ***    |\n   | *****         ********    |\n   |  ****          ******     |\n   |  *****          ****      |\n   |   ******      *******     |\n   |    *******************    |\n   |     ************  *****   |\n   |       ********    ******  |\n   |                           |\n   |                           |\n   |                           |\n   |                           |\n   |                           |\n   |                           |\n   |                           |\n   |                           |\n   +---------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x003e,0x0000,\n0x00ff,0x8000,\n0x01ff,0xc000,\n0x03e3,0xe000,\n0x03c1,0xe000,\n0x03c1,0xe000,\n0x03c1,0xe000,\n0x03c1,0xe000,\n0x01e3,0xc000,\n0x01e7,0x8000,\n0x00ff,0x0000,\n0x01fe,0x0000,\n0x07f8,0x0000,\n0x1f7c,0x0780,\n0x1e3c,0x0780,\n0x3c1e,0x0780,\n0x781f,0x0780,\n0x780f,0x0700,\n0x7807,0x8700,\n0x7807,0xcf00,\n0x7803,0xee00,\n0x7c01,0xfe00,\n0x3c00,0xfc00,\n0x3e00,0x7800,\n0x1f81,0xfc00,\n0x0fff,0xfe00,\n0x07ff,0x9f00,\n0x01fe,0x1f80,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 39 (0x27):\n   width 9\n   +---------+\n   |         |\n   |  *****  |\n   |  *****  |\n   |  *****  |\n   |  *****  |\n   |  *****  |\n   |   ***   |\n   |   ***   |\n   |   ***   |\n   |   ***   |\n   |   ***   |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x3e00,\n0x3e00,\n0x3e00,\n0x3e00,\n0x3e00,\n0x1c00,\n0x1c00,\n0x1c00,\n0x1c00,\n0x1c00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 40 (0x28):\n   width 13\n   +-------------+\n   |             |\n   |          *  |\n   |         **  |\n   |        ***  |\n   |       ****  |\n   |      ****   |\n   |      ***    |\n   |     ***     |\n   |    ****     |\n   |    ***      |\n   |    ***      |\n   |   ****      |\n   |   ****      |\n   |   ***       |\n   |  ****       |\n   |  ****       |\n   |  ****       |\n   |  ****       |\n   |  ****       |\n   |  ****       |\n   |  ****       |\n   |  ****       |\n   |  ****       |\n   |  ****       |\n   |   ***       |\n   |   ****      |\n   |   ****      |\n   |    ***      |\n   |    ***      |\n   |    ****     |\n   |     ***     |\n   |      ***    |\n   |      ****   |\n   |       ****  |\n   |        ***  |\n   |         **  |\n   |          *  |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0020,\n0x0060,\n0x00e0,\n0x01e0,\n0x03c0,\n0x0380,\n0x0700,\n0x0f00,\n0x0e00,\n0x0e00,\n0x1e00,\n0x1e00,\n0x1c00,\n0x3c00,\n0x3c00,\n0x3c00,\n0x3c00,\n0x3c00,\n0x3c00,\n0x3c00,\n0x3c00,\n0x3c00,\n0x3c00,\n0x1c00,\n0x1e00,\n0x1e00,\n0x0e00,\n0x0e00,\n0x0f00,\n0x0700,\n0x0380,\n0x03c0,\n0x01e0,\n0x00e0,\n0x0060,\n0x0020,\n0x0000,\n0x0000,\n\n/* Character 41 (0x29):\n   width 13\n   +-------------+\n   |             |\n   | *           |\n   | **          |\n   | ***         |\n   | ****        |\n   |  ****       |\n   |   ***       |\n   |    ***      |\n   |    ***      |\n   |    ****     |\n   |     ***     |\n   |     ****    |\n   |     ****    |\n   |      ***    |\n   |      ****   |\n   |      ****   |\n   |      ****   |\n   |      ****   |\n   |      ****   |\n   |      ****   |\n   |      ****   |\n   |      ****   |\n   |      ****   |\n   |      ****   |\n   |      ***    |\n   |     ****    |\n   |     ****    |\n   |     ***     |\n   |    ****     |\n   |    ***      |\n   |    ***      |\n   |   ***       |\n   |  ****       |\n   | ****        |\n   | ***         |\n   | **          |\n   | *           |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x4000,\n0x6000,\n0x7000,\n0x7800,\n0x3c00,\n0x1c00,\n0x0e00,\n0x0e00,\n0x0f00,\n0x0700,\n0x0780,\n0x0780,\n0x0380,\n0x03c0,\n0x03c0,\n0x03c0,\n0x03c0,\n0x03c0,\n0x03c0,\n0x03c0,\n0x03c0,\n0x03c0,\n0x03c0,\n0x0380,\n0x0780,\n0x0780,\n0x0700,\n0x0f00,\n0x0e00,\n0x0e00,\n0x1c00,\n0x3c00,\n0x7800,\n0x7000,\n0x6000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 42 (0x2a):\n   width 19\n   +-------------------+\n   |                   |\n   |                   |\n   |                   |\n   |        ***        |\n   |        ***        |\n   |        ***        |\n   |        ***        |\n   |   *    ***    *   |\n   |  ****   *   ****  |\n   |  ******   ******  |\n   |      **   **      |\n   |                   |\n   |       ** **       |\n   |      **   **      |\n   |     ***   ***     |\n   |    ***     ***    |\n   |      *     *      |\n   |                   |\n   |                   |\n   |                   |\n   |                   |\n   |                   |\n   |                   |\n   |                   |\n   |                   |\n   |                   |\n   |                   |\n   |                   |\n   |                   |\n   |                   |\n   |                   |\n   |                   |\n   |                   |\n   |                   |\n   |                   |\n   |                   |\n   |                   |\n   |                   |\n   |                   |\n   +-------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x00e0,0x0000,\n0x00e0,0x0000,\n0x00e0,0x0000,\n0x00e0,0x0000,\n0x10e1,0x0000,\n0x3c47,0x8000,\n0x3f1f,0x8000,\n0x0318,0x0000,\n0x0000,0x0000,\n0x01b0,0x0000,\n0x0318,0x0000,\n0x071c,0x0000,\n0x0e0e,0x0000,\n0x0208,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 43 (0x2b):\n   width 31\n   +-------------------------------+\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |              **               |\n   |              **               |\n   |              **               |\n   |              **               |\n   |              **               |\n   |              **               |\n   |              **               |\n   |              **               |\n   |              **               |\n   |              **               |\n   |    **********************     |\n   |    **********************     |\n   |              **               |\n   |              **               |\n   |              **               |\n   |              **               |\n   |              **               |\n   |              **               |\n   |              **               |\n   |              **               |\n   |              **               |\n   |              **               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   +-------------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0003,0x0000,\n0x0003,0x0000,\n0x0003,0x0000,\n0x0003,0x0000,\n0x0003,0x0000,\n0x0003,0x0000,\n0x0003,0x0000,\n0x0003,0x0000,\n0x0003,0x0000,\n0x0003,0x0000,\n0x0fff,0xffc0,\n0x0fff,0xffc0,\n0x0003,0x0000,\n0x0003,0x0000,\n0x0003,0x0000,\n0x0003,0x0000,\n0x0003,0x0000,\n0x0003,0x0000,\n0x0003,0x0000,\n0x0003,0x0000,\n0x0003,0x0000,\n0x0003,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 44 (0x2c):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |    *****   |\n   |    *****   |\n   |    *****   |\n   |    *****   |\n   |    *****   |\n   |      ***   |\n   |      ***   |\n   |      ***   |\n   |      **    |\n   |     **     |\n   |    **      |\n   |            |\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0f80,\n0x0f80,\n0x0f80,\n0x0f80,\n0x0f80,\n0x0380,\n0x0380,\n0x0380,\n0x0300,\n0x0600,\n0x0c00,\n0x0000,\n0x0000,\n\n/* Character 45 (0x2d):\n   width 23\n   +-----------------------+\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |   *****************   |\n   |   *****************   |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   +-----------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x1fff,0xf000,\n0x1fff,0xf000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 46 (0x2e):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |    *****   |\n   |    *****   |\n   |    *****   |\n   |    *****   |\n   |    *****   |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0f80,\n0x0f80,\n0x0f80,\n0x0f80,\n0x0f80,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 47 (0x2f):\n   width 20\n   +--------------------+\n   |                    |\n   |                    |\n   |                    |\n   |              **    |\n   |              **    |\n   |             **     |\n   |             **     |\n   |             **     |\n   |            **      |\n   |            **      |\n   |            **      |\n   |           ***      |\n   |           **       |\n   |           **       |\n   |           **       |\n   |          **        |\n   |          **        |\n   |          **        |\n   |         **         |\n   |         **         |\n   |         **         |\n   |         **         |\n   |        **          |\n   |        **          |\n   |        **          |\n   |       **           |\n   |       **           |\n   |       **           |\n   |      ***           |\n   |      **            |\n   |      **            |\n   |      **            |\n   |     **             |\n   |     **             |\n   |     **             |\n   |    **              |\n   |    **              |\n   |                    |\n   |                    |\n   +--------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0003,0x0000,\n0x0003,0x0000,\n0x0006,0x0000,\n0x0006,0x0000,\n0x0006,0x0000,\n0x000c,0x0000,\n0x000c,0x0000,\n0x000c,0x0000,\n0x001c,0x0000,\n0x0018,0x0000,\n0x0018,0x0000,\n0x0018,0x0000,\n0x0030,0x0000,\n0x0030,0x0000,\n0x0030,0x0000,\n0x0060,0x0000,\n0x0060,0x0000,\n0x0060,0x0000,\n0x0060,0x0000,\n0x00c0,0x0000,\n0x00c0,0x0000,\n0x00c0,0x0000,\n0x0180,0x0000,\n0x0180,0x0000,\n0x0180,0x0000,\n0x0380,0x0000,\n0x0300,0x0000,\n0x0300,0x0000,\n0x0300,0x0000,\n0x0600,0x0000,\n0x0600,0x0000,\n0x0600,0x0000,\n0x0c00,0x0000,\n0x0c00,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 48 (0x30):\n   width 25\n   +-------------------------+\n   |                         |\n   |                         |\n   |                         |\n   |         ******          |\n   |       **********        |\n   |      ************       |\n   |     *****    *****      |\n   |    ****        ****     |\n   |    ****        ****     |\n   |   ****          ****    |\n   |   ****          ****    |\n   |   ****          ****    |\n   |  ****            ****   |\n   |  ****            ****   |\n   |  ****            ****   |\n   |  ****            ****   |\n   |  ****            ****   |\n   |  ****            ****   |\n   |  ****            ****   |\n   |  ****            ****   |\n   |  ****            ****   |\n   |  ****            ****   |\n   |   ***           ****    |\n   |   ****          ****    |\n   |   ****          ****    |\n   |    ****        ****     |\n   |    ****        ****     |\n   |     *****    *****      |\n   |      ************       |\n   |       **********        |\n   |         ******          |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x007e,0x0000,\n0x01ff,0x8000,\n0x03ff,0xc000,\n0x07c3,0xe000,\n0x0f00,0xf000,\n0x0f00,0xf000,\n0x1e00,0x7800,\n0x1e00,0x7800,\n0x1e00,0x7800,\n0x3c00,0x3c00,\n0x3c00,0x3c00,\n0x3c00,0x3c00,\n0x3c00,0x3c00,\n0x3c00,0x3c00,\n0x3c00,0x3c00,\n0x3c00,0x3c00,\n0x3c00,0x3c00,\n0x3c00,0x3c00,\n0x3c00,0x3c00,\n0x1c00,0x7800,\n0x1e00,0x7800,\n0x1e00,0x7800,\n0x0f00,0xf000,\n0x0f00,0xf000,\n0x07c3,0xe000,\n0x03ff,0xc000,\n0x01ff,0x8000,\n0x007e,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 49 (0x31):\n   width 25\n   +-------------------------+\n   |                         |\n   |                         |\n   |                         |\n   |          ****           |\n   |      ********           |\n   |      ********           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x003c,0x0000,\n0x03fc,0x0000,\n0x03fc,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 50 (0x32):\n   width 25\n   +-------------------------+\n   |                         |\n   |                         |\n   |                         |\n   |        *******          |\n   |     ************        |\n   |    **************       |\n   |    ****     ******      |\n   |    *          ****      |\n   |                ****     |\n   |                ****     |\n   |                ****     |\n   |                ****     |\n   |                ****     |\n   |               *****     |\n   |               ****      |\n   |              ****       |\n   |             *****       |\n   |            *****        |\n   |           *****         |\n   |          *****          |\n   |         ****            |\n   |        ****             |\n   |       ****              |\n   |      ****               |\n   |     *****               |\n   |    *****                |\n   |    ****                 |\n   |   *****                 |\n   |   *****************     |\n   |   *****************     |\n   |   *****************     |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x00fe,0x0000,\n0x07ff,0x8000,\n0x0fff,0xc000,\n0x0f07,0xe000,\n0x0801,0xe000,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0001,0xf000,\n0x0001,0xe000,\n0x0003,0xc000,\n0x0007,0xc000,\n0x000f,0x8000,\n0x001f,0x0000,\n0x003e,0x0000,\n0x0078,0x0000,\n0x00f0,0x0000,\n0x01e0,0x0000,\n0x03c0,0x0000,\n0x07c0,0x0000,\n0x0f80,0x0000,\n0x0f00,0x0000,\n0x1f00,0x0000,\n0x1fff,0xf000,\n0x1fff,0xf000,\n0x1fff,0xf000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 51 (0x33):\n   width 25\n   +-------------------------+\n   |                         |\n   |                         |\n   |                         |\n   |      ********           |\n   |    *************        |\n   |    **************       |\n   |    **       *****       |\n   |              *****      |\n   |               ****      |\n   |               ****      |\n   |               ****      |\n   |               ****      |\n   |              ****       |\n   |              ****       |\n   |            ****         |\n   |       ********          |\n   |       ********          |\n   |       **********        |\n   |            ******       |\n   |              *****      |\n   |               *****     |\n   |                ****     |\n   |                ****     |\n   |                ****     |\n   |                ****     |\n   |               *****     |\n   |    *          ****      |\n   |    ***      ******      |\n   |    **************       |\n   |    *************        |\n   |      ********           |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x03fc,0x0000,\n0x0fff,0x8000,\n0x0fff,0xc000,\n0x0c07,0xc000,\n0x0003,0xe000,\n0x0001,0xe000,\n0x0001,0xe000,\n0x0001,0xe000,\n0x0001,0xe000,\n0x0003,0xc000,\n0x0003,0xc000,\n0x000f,0x0000,\n0x01fe,0x0000,\n0x01fe,0x0000,\n0x01ff,0x8000,\n0x000f,0xc000,\n0x0003,0xe000,\n0x0001,0xf000,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0001,0xf000,\n0x0801,0xe000,\n0x0e07,0xe000,\n0x0fff,0xc000,\n0x0fff,0x8000,\n0x03fc,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 52 (0x34):\n   width 25\n   +-------------------------+\n   |                         |\n   |                         |\n   |                         |\n   |              ****       |\n   |             *****       |\n   |            ******       |\n   |            ******       |\n   |           *******       |\n   |          ********       |\n   |         **** ****       |\n   |         ***  ****       |\n   |        ****  ****       |\n   |       ****   ****       |\n   |       ***    ****       |\n   |      ****    ****       |\n   |     ****     ****       |\n   |    ****      ****       |\n   |    ***       ****       |\n   |   ****       ****       |\n   |  ****        ****       |\n   |  ********************   |\n   |  ********************   |\n   |  ********************   |\n   |              ****       |\n   |              ****       |\n   |              ****       |\n   |              ****       |\n   |              ****       |\n   |              ****       |\n   |              ****       |\n   |              ****       |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0003,0xc000,\n0x0007,0xc000,\n0x000f,0xc000,\n0x000f,0xc000,\n0x001f,0xc000,\n0x003f,0xc000,\n0x007b,0xc000,\n0x0073,0xc000,\n0x00f3,0xc000,\n0x01e3,0xc000,\n0x01c3,0xc000,\n0x03c3,0xc000,\n0x0783,0xc000,\n0x0f03,0xc000,\n0x0e03,0xc000,\n0x1e03,0xc000,\n0x3c03,0xc000,\n0x3fff,0xfc00,\n0x3fff,0xfc00,\n0x3fff,0xfc00,\n0x0003,0xc000,\n0x0003,0xc000,\n0x0003,0xc000,\n0x0003,0xc000,\n0x0003,0xc000,\n0x0003,0xc000,\n0x0003,0xc000,\n0x0003,0xc000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 53 (0x35):\n   width 25\n   +-------------------------+\n   |                         |\n   |                         |\n   |                         |\n   |     **************      |\n   |     **************      |\n   |     **************      |\n   |     ***                 |\n   |     ***                 |\n   |     ***                 |\n   |     ***                 |\n   |     ***                 |\n   |     ***                 |\n   |     ***                 |\n   |     *******             |\n   |     **********          |\n   |     ************        |\n   |           *******       |\n   |              *****      |\n   |               ****      |\n   |               *****     |\n   |                ****     |\n   |                ****     |\n   |                ****     |\n   |                ****     |\n   |                ****     |\n   |               ****      |\n   |              *****      |\n   |     **      *****       |\n   |     *************       |\n   |     ***********         |\n   |       *******           |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x07ff,0xe000,\n0x07ff,0xe000,\n0x07ff,0xe000,\n0x0700,0x0000,\n0x0700,0x0000,\n0x0700,0x0000,\n0x0700,0x0000,\n0x0700,0x0000,\n0x0700,0x0000,\n0x0700,0x0000,\n0x07f0,0x0000,\n0x07fe,0x0000,\n0x07ff,0x8000,\n0x001f,0xc000,\n0x0003,0xe000,\n0x0001,0xe000,\n0x0001,0xf000,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0001,0xe000,\n0x0003,0xe000,\n0x0607,0xc000,\n0x07ff,0xc000,\n0x07ff,0x0000,\n0x01fc,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 54 (0x36):\n   width 25\n   +-------------------------+\n   |                         |\n   |                         |\n   |                         |\n   |           ********      |\n   |         ************    |\n   |       **************    |\n   |      ******       **    |\n   |      ****               |\n   |     ****                |\n   |    ****                 |\n   |    ****                 |\n   |    ****                 |\n   |   ****                  |\n   |   ****    ******        |\n   |   ****  **********      |\n   |   **** ************     |\n   |   *******     ******    |\n   |   ******       *****    |\n   |   *****         *****   |\n   |   ****           ****   |\n   |   ****           ****   |\n   |   ****           ****   |\n   |   ****           ****   |\n   |    ***           ****   |\n   |    ****          ****   |\n   |    ****         ****    |\n   |     ****        ****    |\n   |      ****     *****     |\n   |      *************      |\n   |        **********       |\n   |          ******         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x001f,0xe000,\n0x007f,0xf800,\n0x01ff,0xf800,\n0x03f0,0x1800,\n0x03c0,0x0000,\n0x0780,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x1e00,0x0000,\n0x1e1f,0x8000,\n0x1e7f,0xe000,\n0x1eff,0xf000,\n0x1fc1,0xf800,\n0x1f80,0xf800,\n0x1f00,0x7c00,\n0x1e00,0x3c00,\n0x1e00,0x3c00,\n0x1e00,0x3c00,\n0x1e00,0x3c00,\n0x0e00,0x3c00,\n0x0f00,0x3c00,\n0x0f00,0x7800,\n0x0780,0x7800,\n0x03c1,0xf000,\n0x03ff,0xe000,\n0x00ff,0xc000,\n0x003f,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 55 (0x37):\n   width 25\n   +-------------------------+\n   |                         |\n   |                         |\n   |                         |\n   |    ******************   |\n   |    ******************   |\n   |    ******************   |\n   |    ******************   |\n   |                  ****   |\n   |                 ****    |\n   |                ****     |\n   |                ****     |\n   |               ****      |\n   |               ***       |\n   |              ****       |\n   |              ***        |\n   |             ****        |\n   |            ****         |\n   |            ***          |\n   |           ****          |\n   |           ***           |\n   |          ****           |\n   |         ****            |\n   |         ****            |\n   |        ****             |\n   |        ****             |\n   |       *****             |\n   |       ****              |\n   |       ****              |\n   |      *****              |\n   |      ****               |\n   |      ****               |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0fff,0xfc00,\n0x0fff,0xfc00,\n0x0fff,0xfc00,\n0x0fff,0xfc00,\n0x0000,0x3c00,\n0x0000,0x7800,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0001,0xe000,\n0x0001,0xc000,\n0x0003,0xc000,\n0x0003,0x8000,\n0x0007,0x8000,\n0x000f,0x0000,\n0x000e,0x0000,\n0x001e,0x0000,\n0x001c,0x0000,\n0x003c,0x0000,\n0x0078,0x0000,\n0x0078,0x0000,\n0x00f0,0x0000,\n0x00f0,0x0000,\n0x01f0,0x0000,\n0x01e0,0x0000,\n0x01e0,0x0000,\n0x03e0,0x0000,\n0x03c0,0x0000,\n0x03c0,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 56 (0x38):\n   width 25\n   +-------------------------+\n   |                         |\n   |                         |\n   |                         |\n   |         *******         |\n   |       ************      |\n   |      **************     |\n   |     *****     *****     |\n   |    *****       *****    |\n   |    ****         ****    |\n   |    ****         ****    |\n   |    ****         ****    |\n   |    *****        ***     |\n   |     *****      ****     |\n   |     ******    ****      |\n   |      ******* ****       |\n   |        ********         |\n   |       **********        |\n   |      **** *******       |\n   |     ****    *******     |\n   |    ****       ******    |\n   |    ***         *****    |\n   |   ****          *****   |\n   |   ****           ****   |\n   |   ****           ****   |\n   |   ****           ****   |\n   |   *****          ****   |\n   |    ****         ****    |\n   |    ******     ******    |\n   |     ***************     |\n   |      ************       |\n   |         *******         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x007f,0x0000,\n0x01ff,0xe000,\n0x03ff,0xf000,\n0x07c1,0xf000,\n0x0f80,0xf800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f80,0x7000,\n0x07c0,0xf000,\n0x07e1,0xe000,\n0x03fb,0xc000,\n0x00ff,0x0000,\n0x01ff,0x8000,\n0x03df,0xc000,\n0x0787,0xf000,\n0x0f01,0xf800,\n0x0e00,0xf800,\n0x1e00,0x7c00,\n0x1e00,0x3c00,\n0x1e00,0x3c00,\n0x1e00,0x3c00,\n0x1f00,0x3c00,\n0x0f00,0x7800,\n0x0fc1,0xf800,\n0x07ff,0xf000,\n0x03ff,0xc000,\n0x007f,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 57 (0x39):\n   width 25\n   +-------------------------+\n   |                         |\n   |                         |\n   |                         |\n   |         ******          |\n   |       **********        |\n   |      ************       |\n   |     *****     ****      |\n   |    ****        ****     |\n   |    ****         ****    |\n   |   ****          ****    |\n   |   ****           ***    |\n   |   ****           ****   |\n   |   ****           ****   |\n   |   ****           ****   |\n   |   ****           ****   |\n   |    ****         *****   |\n   |    *****       ******   |\n   |     *****     *******   |\n   |     ************ ****   |\n   |       *********  ****   |\n   |         *****    ****   |\n   |                  ***    |\n   |                 ****    |\n   |                 ****    |\n   |                ****     |\n   |                ****     |\n   |               ****      |\n   |    **       *****       |\n   |    *************        |\n   |    ************         |\n   |      *******            |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x007e,0x0000,\n0x01ff,0x8000,\n0x03ff,0xc000,\n0x07c1,0xe000,\n0x0f00,0xf000,\n0x0f00,0x7800,\n0x1e00,0x7800,\n0x1e00,0x3800,\n0x1e00,0x3c00,\n0x1e00,0x3c00,\n0x1e00,0x3c00,\n0x1e00,0x3c00,\n0x0f00,0x7c00,\n0x0f80,0xfc00,\n0x07c1,0xfc00,\n0x07ff,0xbc00,\n0x01ff,0x3c00,\n0x007c,0x3c00,\n0x0000,0x3800,\n0x0000,0x7800,\n0x0000,0x7800,\n0x0000,0xf000,\n0x0000,0xf000,\n0x0001,0xe000,\n0x0c07,0xc000,\n0x0fff,0x8000,\n0x0fff,0x0000,\n0x03f8,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 58 (0x3a):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 59 (0x3b):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |    ****    |\n   |      **    |\n   |      **    |\n   |      **    |\n   |     **     |\n   |     **     |\n   |    *       |\n   |            |\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0300,\n0x0300,\n0x0300,\n0x0600,\n0x0600,\n0x0800,\n0x0000,\n0x0000,\n\n/* Character 60 (0x3c):\n   width 31\n   +-------------------------------+\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                          *    |\n   |                        ***    |\n   |                      ****     |\n   |                    ****       |\n   |                  ****         |\n   |                ****           |\n   |              ****             |\n   |            ****               |\n   |          ****                 |\n   |        ****                   |\n   |      ****                     |\n   |    ****                       |\n   |      ****                     |\n   |        ****                   |\n   |          ****                 |\n   |            ****               |\n   |              ****             |\n   |                ****           |\n   |                  ****         |\n   |                    ****       |\n   |                      ****     |\n   |                        ***    |\n   |                          *    |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   +-------------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0020,\n0x0000,0x00e0,\n0x0000,0x03c0,\n0x0000,0x0f00,\n0x0000,0x3c00,\n0x0000,0xf000,\n0x0003,0xc000,\n0x000f,0x0000,\n0x003c,0x0000,\n0x00f0,0x0000,\n0x03c0,0x0000,\n0x0f00,0x0000,\n0x03c0,0x0000,\n0x00f0,0x0000,\n0x003c,0x0000,\n0x000f,0x0000,\n0x0003,0xc000,\n0x0000,0xf000,\n0x0000,0x3c00,\n0x0000,0x0f00,\n0x0000,0x03c0,\n0x0000,0x00e0,\n0x0000,0x0020,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 61 (0x3d):\n   width 31\n   +-------------------------------+\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |    ***********************    |\n   |    ***********************    |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |    ***********************    |\n   |    ***********************    |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   +-------------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0fff,0xffe0,\n0x0fff,0xffe0,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0fff,0xffe0,\n0x0fff,0xffe0,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 62 (0x3e):\n   width 31\n   +-------------------------------+\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |    *                          |\n   |    ***                        |\n   |     ****                      |\n   |       ****                    |\n   |         ****                  |\n   |           ****                |\n   |             ****              |\n   |               ****            |\n   |                 ****          |\n   |                   ****        |\n   |                     ****      |\n   |                       ****    |\n   |                     ****      |\n   |                   ****        |\n   |                 ****          |\n   |               ****            |\n   |             ****              |\n   |           ****                |\n   |         ****                  |\n   |       ****                    |\n   |     ****                      |\n   |    ***                        |\n   |    *                          |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   |                               |\n   +-------------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0800,0x0000,\n0x0e00,0x0000,\n0x0780,0x0000,\n0x01e0,0x0000,\n0x0078,0x0000,\n0x001e,0x0000,\n0x0007,0x8000,\n0x0001,0xe000,\n0x0000,0x7800,\n0x0000,0x1e00,\n0x0000,0x0780,\n0x0000,0x01e0,\n0x0000,0x0780,\n0x0000,0x1e00,\n0x0000,0x7800,\n0x0001,0xe000,\n0x0007,0x8000,\n0x001e,0x0000,\n0x0078,0x0000,\n0x01e0,0x0000,\n0x0780,0x0000,\n0x0e00,0x0000,\n0x0800,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 63 (0x3f):\n   width 16\n   +----------------+\n   |                |\n   |                |\n   |                |\n   |   ********     |\n   | *************  |\n   | ************** |\n   | **       ***** |\n   |           *****|\n   |            ****|\n   |            ****|\n   |            ****|\n   |           **** |\n   |           **** |\n   |          ****  |\n   |         ****   |\n   |        ****    |\n   |       ****     |\n   |      ****      |\n   |      ***       |\n   |     ****       |\n   |     ****       |\n   |     ****       |\n   |     ****       |\n   |                |\n   |                |\n   |                |\n   |                |\n   |     ****       |\n   |     ****       |\n   |     ****       |\n   |     ****       |\n   |                |\n   |                |\n   |                |\n   |                |\n   |                |\n   |                |\n   |                |\n   |                |\n   +----------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1fe0,\n0x7ffc,\n0x7ffe,\n0x603e,\n0x001f,\n0x000f,\n0x000f,\n0x000f,\n0x001e,\n0x001e,\n0x003c,\n0x0078,\n0x00f0,\n0x01e0,\n0x03c0,\n0x0380,\n0x0780,\n0x0780,\n0x0780,\n0x0780,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0780,\n0x0780,\n0x0780,\n0x0780,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 64 (0x40):\n   width 33\n   +---------------------------------+\n   |                                 |\n   |                                 |\n   |                                 |\n   |                *******          |\n   |             *************       |\n   |           *****       *****     |\n   |         ****            ****    |\n   |        ***                ***   |\n   |       ***                  **   |\n   |      ***       ********    ***  |\n   |     ***      **********     **  |\n   |    ***      ***     ***     *** |\n   |    **      ***      ***      ** |\n   |   ***     ***       ***      ** |\n   |   **      **        **       ** |\n   |   **     ***        **       ** |\n   |  **      ***       ***       ** |\n   |  **      **       ****       ** |\n   |  **     ***       ***       **  |\n   |  **     ***      ****       **  |\n   |  **     ***     ** **      **   |\n   |  **     ***    **  **     ***   |\n   |  **     ****  *** ***   ****    |\n   |   **     *******  ********      |\n   |   **      ****     *****        |\n   |   ***                           |\n   |    ***                          |\n   |     ***                         |\n   |      *****        **            |\n   |        *************            |\n   |          ********               |\n   |                                 |\n   |                                 |\n   |                                 |\n   |                                 |\n   |                                 |\n   |                                 |\n   |                                 |\n   |                                 |\n   +---------------------------------+ */\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0xfe00,0x0000,\n0x0007,0xffc0,0x0000,\n0x001f,0x01f0,0x0000,\n0x0078,0x0078,0x0000,\n0x00e0,0x001c,0x0000,\n0x01c0,0x000c,0x0000,\n0x0380,0xff0e,0x0000,\n0x0703,0xff06,0x0000,\n0x0e07,0x0707,0x0000,\n0x0c0e,0x0703,0x0000,\n0x1c1c,0x0703,0x0000,\n0x1818,0x0603,0x0000,\n0x1838,0x0603,0x0000,\n0x3038,0x0e03,0x0000,\n0x3030,0x1e03,0x0000,\n0x3070,0x1c06,0x0000,\n0x3070,0x3c06,0x0000,\n0x3070,0x6c0c,0x0000,\n0x3070,0xcc1c,0x0000,\n0x3079,0xdc78,0x0000,\n0x183f,0x9fe0,0x0000,\n0x181e,0x0f80,0x0000,\n0x1c00,0x0000,0x0000,\n0x0e00,0x0000,0x0000,\n0x0700,0x0000,0x0000,\n0x03e0,0x1800,0x0000,\n0x00ff,0xf800,0x0000,\n0x003f,0xc000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n\n/* Character 65 (0x41):\n   width 27\n   +---------------------------+\n   |                           |\n   |                           |\n   |                           |\n   |           ****            |\n   |           *****           |\n   |          ******           |\n   |          ******           |\n   |         ********          |\n   |         *** ****          |\n   |         *** *****         |\n   |        ***   ****         |\n   |        ***   ****         |\n   |       ****   *****        |\n   |       ***     ****        |\n   |       ***     *****       |\n   |      ***       ****       |\n   |      ***       ****       |\n   |     ****       *****      |\n   |     ***         ****      |\n   |     ***         *****     |\n   |    ******************     |\n   |    ******************     |\n   |   ********************    |\n   |   ***             ****    |\n   |   ***             ****    |\n   |  ***               ****   |\n   |  ***               ****   |\n   | ****               *****  |\n   | ***                 ****  |\n   | ***                 ****  |\n   |***                  ***** |\n   |                           |\n   |                           |\n   |                           |\n   |                           |\n   |                           |\n   |                           |\n   |                           |\n   |                           |\n   +---------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x001e,0x0000,\n0x001f,0x0000,\n0x003f,0x0000,\n0x003f,0x0000,\n0x007f,0x8000,\n0x0077,0x8000,\n0x0077,0xc000,\n0x00e3,0xc000,\n0x00e3,0xc000,\n0x01e3,0xe000,\n0x01c1,0xe000,\n0x01c1,0xf000,\n0x0380,0xf000,\n0x0380,0xf000,\n0x0780,0xf800,\n0x0700,0x7800,\n0x0700,0x7c00,\n0x0fff,0xfc00,\n0x0fff,0xfc00,\n0x1fff,0xfe00,\n0x1c00,0x1e00,\n0x1c00,0x1e00,\n0x3800,0x0f00,\n0x3800,0x0f00,\n0x7800,0x0f80,\n0x7000,0x0780,\n0x7000,0x0780,\n0xe000,0x07c0,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 66 (0x42):\n   width 22\n   +----------------------+\n   |                      |\n   |                      |\n   |                      |\n   |    ***********       |\n   |    **************    |\n   |    ***************   |\n   |    ****     ******   |\n   |    ****       *****  |\n   |    ****        ****  |\n   |    ****        ****  |\n   |    ****        ****  |\n   |    ****        ****  |\n   |    ****       ****   |\n   |    ****      ****    |\n   |    ****     ****     |\n   |    ************      |\n   |    ***********       |\n   |    *************     |\n   |    ****    ******    |\n   |    ****       ****   |\n   |    ****        ****  |\n   |    ****        ***** |\n   |    ****         **** |\n   |    ****         **** |\n   |    ****         **** |\n   |    ****         **** |\n   |    ****        ***** |\n   |    ****      ******  |\n   |    ***************   |\n   |    **************    |\n   |    ************      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   +----------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0ffe,0x0000,\n0x0fff,0xc000,\n0x0fff,0xe000,\n0x0f07,0xe000,\n0x0f01,0xf000,\n0x0f00,0xf000,\n0x0f00,0xf000,\n0x0f00,0xf000,\n0x0f00,0xf000,\n0x0f01,0xe000,\n0x0f03,0xc000,\n0x0f07,0x8000,\n0x0fff,0x0000,\n0x0ffe,0x0000,\n0x0fff,0x8000,\n0x0f0f,0xc000,\n0x0f01,0xe000,\n0x0f00,0xf000,\n0x0f00,0xf800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0xf800,\n0x0f03,0xf000,\n0x0fff,0xe000,\n0x0fff,0xc000,\n0x0fff,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 67 (0x43):\n   width 27\n   +---------------------------+\n   |                           |\n   |                           |\n   |                           |\n   |            **********     |\n   |         ****************  |\n   |       ******************  |\n   |      ******        *****  |\n   |     *****             **  |\n   |    *****                  |\n   |    ****                   |\n   |   ****                    |\n   |   ****                    |\n   |  *****                    |\n   |  ****                     |\n   |  ****                     |\n   |  ****                     |\n   |  ****                     |\n   |  ****                     |\n   |  ****                     |\n   |  ****                     |\n   |  ****                     |\n   |  *****                    |\n   |   ****                    |\n   |   *****                   |\n   |    ****                   |\n   |    *****                  |\n   |     *****              *  |\n   |      *******       *****  |\n   |       ******************  |\n   |         ***************   |\n   |           **********      |\n   |                           |\n   |                           |\n   |                           |\n   |                           |\n   |                           |\n   |                           |\n   |                           |\n   |                           |\n   +---------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x000f,0xfc00,\n0x007f,0xff80,\n0x01ff,0xff80,\n0x03f0,0x0f80,\n0x07c0,0x0180,\n0x0f80,0x0000,\n0x0f00,0x0000,\n0x1e00,0x0000,\n0x1e00,0x0000,\n0x3e00,0x0000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x3e00,0x0000,\n0x1e00,0x0000,\n0x1f00,0x0000,\n0x0f00,0x0000,\n0x0f80,0x0000,\n0x07c0,0x0080,\n0x03f8,0x0f80,\n0x01ff,0xff80,\n0x007f,0xff00,\n0x001f,0xf800,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 68 (0x44):\n   width 29\n   +-----------------------------+\n   |                             |\n   |                             |\n   |                             |\n   |    ***************          |\n   |    ******************       |\n   |    *******************      |\n   |    ****         *******     |\n   |    ****            *****    |\n   |    ****             *****   |\n   |    ****              *****  |\n   |    ****               ****  |\n   |    ****               ****  |\n   |    ****               ***** |\n   |    ****                **** |\n   |    ****                **** |\n   |    ****                **** |\n   |    ****                **** |\n   |    ****                **** |\n   |    ****                **** |\n   |    ****                **** |\n   |    ****                **** |\n   |    ****               ****  |\n   |    ****               ****  |\n   |    ****              *****  |\n   |    ****              ****   |\n   |    ****             ****    |\n   |    ****            *****    |\n   |    ****         *******     |\n   |    *******************      |\n   |    *****************        |\n   |    **************           |\n   |                             |\n   |                             |\n   |                             |\n   |                             |\n   |                             |\n   |                             |\n   |                             |\n   |                             |\n   +-----------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0fff,0xe000,\n0x0fff,0xfc00,\n0x0fff,0xfe00,\n0x0f00,0x7f00,\n0x0f00,0x0f80,\n0x0f00,0x07c0,\n0x0f00,0x03e0,\n0x0f00,0x01e0,\n0x0f00,0x01e0,\n0x0f00,0x01f0,\n0x0f00,0x00f0,\n0x0f00,0x00f0,\n0x0f00,0x00f0,\n0x0f00,0x00f0,\n0x0f00,0x00f0,\n0x0f00,0x00f0,\n0x0f00,0x00f0,\n0x0f00,0x00f0,\n0x0f00,0x01e0,\n0x0f00,0x01e0,\n0x0f00,0x03e0,\n0x0f00,0x03c0,\n0x0f00,0x0780,\n0x0f00,0x0f80,\n0x0f00,0x7f00,\n0x0fff,0xfe00,\n0x0fff,0xf800,\n0x0fff,0xc000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 69 (0x45):\n   width 21\n   +---------------------+\n   |                     |\n   |                     |\n   |                     |\n   |    **************** |\n   |    **************** |\n   |    **************** |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    **************   |\n   |    **************   |\n   |    **************   |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    *****************|\n   |    *****************|\n   |    *****************|\n   |                     |\n   |                     |\n   |                     |\n   |                     |\n   |                     |\n   |                     |\n   |                     |\n   |                     |\n   +---------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0fff,0xf000,\n0x0fff,0xf000,\n0x0fff,0xf000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0fff,0xc000,\n0x0fff,0xc000,\n0x0fff,0xc000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0fff,0xf800,\n0x0fff,0xf800,\n0x0fff,0xf800,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 70 (0x46):\n   width 21\n   +---------------------+\n   |                     |\n   |                     |\n   |                     |\n   |    **************** |\n   |    **************** |\n   |    **************** |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    **************   |\n   |    **************   |\n   |    **************   |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |                     |\n   |                     |\n   |                     |\n   |                     |\n   |                     |\n   |                     |\n   |                     |\n   |                     |\n   +---------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0fff,0xf000,\n0x0fff,0xf000,\n0x0fff,0xf000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0fff,0xc000,\n0x0fff,0xc000,\n0x0fff,0xc000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 71 (0x47):\n   width 28\n   +----------------------------+\n   |                            |\n   |                            |\n   |                            |\n   |            **********      |\n   |         ****************   |\n   |       ******************   |\n   |      ******        *****   |\n   |     *****             **   |\n   |    *****                   |\n   |    ****                    |\n   |   ****                     |\n   |   ****                     |\n   |  *****                     |\n   |  ****                      |\n   |  ****                      |\n   |  ****                      |\n   |  ****                      |\n   |  ****                      |\n   |  ****                      |\n   |  ****               ****   |\n   |  ****               ****   |\n   |  *****              ****   |\n   |   ****              ****   |\n   |   *****             ****   |\n   |   *****             ****   |\n   |    *****            ****   |\n   |     *****           ****   |\n   |      *******       *****   |\n   |       ******************   |\n   |         ****************   |\n   |           **********       |\n   |                            |\n   |                            |\n   |                            |\n   |                            |\n   |                            |\n   |                            |\n   |                            |\n   |                            |\n   +----------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x000f,0xfc00,\n0x007f,0xff80,\n0x01ff,0xff80,\n0x03f0,0x0f80,\n0x07c0,0x0180,\n0x0f80,0x0000,\n0x0f00,0x0000,\n0x1e00,0x0000,\n0x1e00,0x0000,\n0x3e00,0x0000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x3c00,0x0780,\n0x3c00,0x0780,\n0x3e00,0x0780,\n0x1e00,0x0780,\n0x1f00,0x0780,\n0x1f00,0x0780,\n0x0f80,0x0780,\n0x07c0,0x0780,\n0x03f8,0x0f80,\n0x01ff,0xff80,\n0x007f,0xff80,\n0x001f,0xf800,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 72 (0x48):\n   width 29\n   +-----------------------------+\n   |                             |\n   |                             |\n   |                             |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    *********************    |\n   |    *********************    |\n   |    *********************    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |    ****             ****    |\n   |                             |\n   |                             |\n   |                             |\n   |                             |\n   |                             |\n   |                             |\n   |                             |\n   |                             |\n   +-----------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0fff,0xff80,\n0x0fff,0xff80,\n0x0fff,0xff80,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0f00,0x0780,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 73 (0x49):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 74 (0x4a):\n   width 15\n   +---------------+\n   |               |\n   |               |\n   |               |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |        ****   |\n   |       ****    |\n   |*     *****    |\n   |**********     |\n   |*********      |\n   |*******        |\n   |               |\n   |               |\n   +---------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x00f0,\n0x01e0,\n0x83e0,\n0xffc0,\n0xff80,\n0xfe00,\n0x0000,\n0x0000,\n\n/* Character 75 (0x4b):\n   width 25\n   +-------------------------+\n   |                         |\n   |                         |\n   |                         |\n   |    ****           ***   |\n   |    ****          ****   |\n   |    ****         ****    |\n   |    ****        ****     |\n   |    ****       ****      |\n   |    ****       ***       |\n   |    ****      ****       |\n   |    ****     ****        |\n   |    ****    ****         |\n   |    ****   ****          |\n   |    ****   ***           |\n   |    ****  ****           |\n   |    **** ****            |\n   |    *********            |\n   |    **** *****           |\n   |    **** *****           |\n   |    ****  *****          |\n   |    ****   *****         |\n   |    ****    *****        |\n   |    ****     *****       |\n   |    ****      *****      |\n   |    ****       *****     |\n   |    ****       *****     |\n   |    ****        *****    |\n   |    ****         *****   |\n   |    ****          *****  |\n   |    ****           ***** |\n   |    ****            *****|\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0f00,0x1c00,\n0x0f00,0x3c00,\n0x0f00,0x7800,\n0x0f00,0xf000,\n0x0f01,0xe000,\n0x0f01,0xc000,\n0x0f03,0xc000,\n0x0f07,0x8000,\n0x0f0f,0x0000,\n0x0f1e,0x0000,\n0x0f1c,0x0000,\n0x0f3c,0x0000,\n0x0f78,0x0000,\n0x0ff8,0x0000,\n0x0f7c,0x0000,\n0x0f7c,0x0000,\n0x0f3e,0x0000,\n0x0f1f,0x0000,\n0x0f0f,0x8000,\n0x0f07,0xc000,\n0x0f03,0xe000,\n0x0f01,0xf000,\n0x0f01,0xf000,\n0x0f00,0xf800,\n0x0f00,0x7c00,\n0x0f00,0x3e00,\n0x0f00,0x1f00,\n0x0f00,0x0f80,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 76 (0x4c):\n   width 21\n   +---------------------+\n   |                     |\n   |                     |\n   |                     |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    ****             |\n   |    *****************|\n   |    *****************|\n   |    *****************|\n   |                     |\n   |                     |\n   |                     |\n   |                     |\n   |                     |\n   |                     |\n   |                     |\n   |                     |\n   +---------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0fff,0xf800,\n0x0fff,0xf800,\n0x0fff,0xf800,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 77 (0x4d):\n   width 34\n   +----------------------------------+\n   |                                  |\n   |                                  |\n   |                                  |\n   |    *****                *****    |\n   |    ******              ******    |\n   |    ******              ******    |\n   |    ******              ******    |\n   |    *******            *******    |\n   |    *******            *******    |\n   |    *******           ********    |\n   |    *** ****          *** ****    |\n   |    *** ****          *** ****    |\n   |    *** *****        **** ****    |\n   |    ***  ****        ***  ****    |\n   |    ***  ****        ***  ****    |\n   |    ***  *****      ****  ****    |\n   |    ***   ****      ***   ****    |\n   |    ***   ****      ***   ****    |\n   |    ***    ****    ***    ****    |\n   |    ***    ****    ***    ****    |\n   |    ***    *****  ****    ****    |\n   |    ***     ****  ***     ****    |\n   |    ***     ****  ***     ****    |\n   |    ***     *********     ****    |\n   |    ***      *******      ****    |\n   |    ***      *******      ****    |\n   |    ***       ******      ****    |\n   |    ***       *****       ****    |\n   |    ***       *****       ****    |\n   |    ***                   ****    |\n   |    ***                   ****    |\n   |                                  |\n   |                                  |\n   |                                  |\n   |                                  |\n   |                                  |\n   |                                  |\n   |                                  |\n   |                                  |\n   +----------------------------------+ */\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0f80,0x007c,0x0000,\n0x0fc0,0x00fc,0x0000,\n0x0fc0,0x00fc,0x0000,\n0x0fc0,0x00fc,0x0000,\n0x0fe0,0x01fc,0x0000,\n0x0fe0,0x01fc,0x0000,\n0x0fe0,0x03fc,0x0000,\n0x0ef0,0x03bc,0x0000,\n0x0ef0,0x03bc,0x0000,\n0x0ef8,0x07bc,0x0000,\n0x0e78,0x073c,0x0000,\n0x0e78,0x073c,0x0000,\n0x0e7c,0x0f3c,0x0000,\n0x0e3c,0x0e3c,0x0000,\n0x0e3c,0x0e3c,0x0000,\n0x0e1e,0x1c3c,0x0000,\n0x0e1e,0x1c3c,0x0000,\n0x0e1f,0x3c3c,0x0000,\n0x0e0f,0x383c,0x0000,\n0x0e0f,0x383c,0x0000,\n0x0e0f,0xf83c,0x0000,\n0x0e07,0xf03c,0x0000,\n0x0e07,0xf03c,0x0000,\n0x0e03,0xf03c,0x0000,\n0x0e03,0xe03c,0x0000,\n0x0e03,0xe03c,0x0000,\n0x0e00,0x003c,0x0000,\n0x0e00,0x003c,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n\n/* Character 78 (0x4e):\n   width 29\n   +-----------------------------+\n   |                             |\n   |                             |\n   |                             |\n   |    ****               ***   |\n   |    *****              ***   |\n   |    ******             ***   |\n   |    ******             ***   |\n   |    *******            ***   |\n   |    ********           ***   |\n   |    *** ****           ***   |\n   |    *** *****          ***   |\n   |    ***  *****         ***   |\n   |    ***   ****         ***   |\n   |    ***   *****        ***   |\n   |    ***    *****       ***   |\n   |    ***     ****       ***   |\n   |    ***     *****      ***   |\n   |    ***      *****     ***   |\n   |    ***       ****     ***   |\n   |    ***       *****    ***   |\n   |    ***        *****   ***   |\n   |    ***         ****   ***   |\n   |    ***         *****  ***   |\n   |    ***          ***** ***   |\n   |    ***           **** ***   |\n   |    ***           ********   |\n   |    ***            *******   |\n   |    ***             ******   |\n   |    ***             ******   |\n   |    ***              *****   |\n   |    ***               ****   |\n   |                             |\n   |                             |\n   |                             |\n   |                             |\n   |                             |\n   |                             |\n   |                             |\n   |                             |\n   +-----------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0f00,0x01c0,\n0x0f80,0x01c0,\n0x0fc0,0x01c0,\n0x0fc0,0x01c0,\n0x0fe0,0x01c0,\n0x0ff0,0x01c0,\n0x0ef0,0x01c0,\n0x0ef8,0x01c0,\n0x0e7c,0x01c0,\n0x0e3c,0x01c0,\n0x0e3e,0x01c0,\n0x0e1f,0x01c0,\n0x0e0f,0x01c0,\n0x0e0f,0x81c0,\n0x0e07,0xc1c0,\n0x0e03,0xc1c0,\n0x0e03,0xe1c0,\n0x0e01,0xf1c0,\n0x0e00,0xf1c0,\n0x0e00,0xf9c0,\n0x0e00,0x7dc0,\n0x0e00,0x3dc0,\n0x0e00,0x3fc0,\n0x0e00,0x1fc0,\n0x0e00,0x0fc0,\n0x0e00,0x0fc0,\n0x0e00,0x07c0,\n0x0e00,0x03c0,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 79 (0x4f):\n   width 30\n   +------------------------------+\n   |                              |\n   |                              |\n   |                              |\n   |           ********           |\n   |        *************         |\n   |       ****************       |\n   |      ******      ******      |\n   |     *****          *****     |\n   |    *****            *****    |\n   |    ****              ****    |\n   |   ****                ****   |\n   |   ****                ****   |\n   |   ****                ****   |\n   |  ****                  ****  |\n   |  ****                  ****  |\n   |  ****                  ****  |\n   |  ****                  ****  |\n   |  ****                  ****  |\n   |  ****                  ****  |\n   |  ****                  ****  |\n   |  ****                  ****  |\n   |   ****                ****   |\n   |   ****                ****   |\n   |   ****                ****   |\n   |    ****              ****    |\n   |    *****            *****    |\n   |     *****          *****     |\n   |      ******      ******      |\n   |       ****************       |\n   |        *************         |\n   |           ********           |\n   |                              |\n   |                              |\n   |                              |\n   |                              |\n   |                              |\n   |                              |\n   |                              |\n   |                              |\n   +------------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x001f,0xe000,\n0x00ff,0xf800,\n0x01ff,0xfe00,\n0x03f0,0x3f00,\n0x07c0,0x0f80,\n0x0f80,0x07c0,\n0x0f00,0x03c0,\n0x1e00,0x01e0,\n0x1e00,0x01e0,\n0x1e00,0x01e0,\n0x3c00,0x00f0,\n0x3c00,0x00f0,\n0x3c00,0x00f0,\n0x3c00,0x00f0,\n0x3c00,0x00f0,\n0x3c00,0x00f0,\n0x3c00,0x00f0,\n0x3c00,0x00f0,\n0x1e00,0x01e0,\n0x1e00,0x01e0,\n0x1e00,0x01e0,\n0x0f00,0x03c0,\n0x0f80,0x07c0,\n0x07c0,0x0f80,\n0x03f0,0x3f00,\n0x01ff,0xfe00,\n0x00ff,0xf800,\n0x001f,0xe000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 80 (0x50):\n   width 22\n   +----------------------+\n   |                      |\n   |                      |\n   |                      |\n   |    ************      |\n   |    **************    |\n   |    ****************  |\n   |    ****      ******  |\n   |    ****        ***** |\n   |    ****         **** |\n   |    ****         **** |\n   |    ****         **** |\n   |    ****         **** |\n   |    ****         **** |\n   |    ****        ***** |\n   |    ****        ****  |\n   |    ****       *****  |\n   |    ****     ******   |\n   |    **************    |\n   |    *************     |\n   |    **********        |\n   |    ****              |\n   |    ****              |\n   |    ****              |\n   |    ****              |\n   |    ****              |\n   |    ****              |\n   |    ****              |\n   |    ****              |\n   |    ****              |\n   |    ****              |\n   |    ****              |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   +----------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0fff,0x0000,\n0x0fff,0xc000,\n0x0fff,0xf000,\n0x0f03,0xf000,\n0x0f00,0xf800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0xf800,\n0x0f00,0xf000,\n0x0f01,0xf000,\n0x0f07,0xe000,\n0x0fff,0xc000,\n0x0fff,0x8000,\n0x0ffc,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 81 (0x51):\n   width 30\n   +------------------------------+\n   |                              |\n   |                              |\n   |                              |\n   |           ********           |\n   |        *************         |\n   |       ****************       |\n   |      ******      ******      |\n   |     *****          *****     |\n   |    *****            *****    |\n   |    ****              ****    |\n   |   ****                ****   |\n   |   ****                ****   |\n   |   ****                ****   |\n   |  ****                  ****  |\n   |  ****                  ****  |\n   |  ****                  ****  |\n   |  ****                  ****  |\n   |  ****                  ****  |\n   |  ****                  ****  |\n   |  ****                  ****  |\n   |  ****                  ****  |\n   |   ****                *****  |\n   |   ****                ****   |\n   |   ****                ****   |\n   |    ****              ****    |\n   |    *****            *****    |\n   |     *****          *****     |\n   |      ******      ******      |\n   |       ****************       |\n   |        *************         |\n   |           ***********        |\n   |                  *******     |\n   |                    ********* |\n   |                      ********|\n   |                        ******|\n   |                           ** |\n   |                              |\n   |                              |\n   |                              |\n   +------------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x001f,0xe000,\n0x00ff,0xf800,\n0x01ff,0xfe00,\n0x03f0,0x3f00,\n0x07c0,0x0f80,\n0x0f80,0x07c0,\n0x0f00,0x03c0,\n0x1e00,0x01e0,\n0x1e00,0x01e0,\n0x1e00,0x01e0,\n0x3c00,0x00f0,\n0x3c00,0x00f0,\n0x3c00,0x00f0,\n0x3c00,0x00f0,\n0x3c00,0x00f0,\n0x3c00,0x00f0,\n0x3c00,0x00f0,\n0x3c00,0x00f0,\n0x1e00,0x01f0,\n0x1e00,0x01e0,\n0x1e00,0x01e0,\n0x0f00,0x03c0,\n0x0f80,0x07c0,\n0x07c0,0x0f80,\n0x03f0,0x3f00,\n0x01ff,0xfe00,\n0x00ff,0xf800,\n0x001f,0xfc00,\n0x0000,0x3f80,\n0x0000,0x0ff8,\n0x0000,0x03fe,\n0x0000,0x00fc,\n0x0000,0x0018,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 82 (0x52):\n   width 25\n   +-------------------------+\n   |                         |\n   |                         |\n   |                         |\n   |    ************         |\n   |    **************       |\n   |    ****************     |\n   |    ****      ******     |\n   |    ****        *****    |\n   |    ****         ****    |\n   |    ****         ****    |\n   |    ****         ****    |\n   |    ****         ****    |\n   |    ****         ****    |\n   |    ****        ****     |\n   |    ****       *****     |\n   |    ****     ******      |\n   |    **************       |\n   |    ************         |\n   |    ************         |\n   |    ****    *****        |\n   |    ****     ****        |\n   |    ****     *****       |\n   |    ****      *****      |\n   |    ****       *****     |\n   |    ****        ****     |\n   |    ****        *****    |\n   |    ****         *****   |\n   |    ****          ****   |\n   |    ****          *****  |\n   |    ****           ***** |\n   |    ****            *****|\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0fff,0x0000,\n0x0fff,0xc000,\n0x0fff,0xf000,\n0x0f03,0xf000,\n0x0f00,0xf800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0xf000,\n0x0f01,0xf000,\n0x0f07,0xe000,\n0x0fff,0xc000,\n0x0fff,0x0000,\n0x0fff,0x0000,\n0x0f0f,0x8000,\n0x0f07,0x8000,\n0x0f07,0xc000,\n0x0f03,0xe000,\n0x0f01,0xf000,\n0x0f00,0xf000,\n0x0f00,0xf800,\n0x0f00,0x7c00,\n0x0f00,0x3c00,\n0x0f00,0x3e00,\n0x0f00,0x1f00,\n0x0f00,0x0f80,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 83 (0x53):\n   width 21\n   +---------------------+\n   |                     |\n   |                     |\n   |                     |\n   |       ********      |\n   |     ************    |\n   |    *************    |\n   |   *****     ****    |\n   |  *****         *    |\n   |  ****               |\n   |  ****               |\n   |  ****               |\n   |  *****              |\n   |  ******             |\n   |   ******            |\n   |    *******          |\n   |     ********        |\n   |      ********       |\n   |        ********     |\n   |          *******    |\n   |            ******   |\n   |             *****   |\n   |              *****  |\n   |               ****  |\n   |               ****  |\n   |               ****  |\n   |               ****  |\n   |  *           ****   |\n   |  ****      ******   |\n   |  ***************    |\n   |  *************      |\n   |    *********        |\n   |                     |\n   |                     |\n   |                     |\n   |                     |\n   |                     |\n   |                     |\n   |                     |\n   |                     |\n   +---------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x01fe,0x0000,\n0x07ff,0x8000,\n0x0fff,0x8000,\n0x1f07,0x8000,\n0x3e00,0x8000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x3e00,0x0000,\n0x3f00,0x0000,\n0x1f80,0x0000,\n0x0fe0,0x0000,\n0x07f8,0x0000,\n0x03fc,0x0000,\n0x00ff,0x0000,\n0x003f,0x8000,\n0x000f,0xc000,\n0x0007,0xc000,\n0x0003,0xe000,\n0x0001,0xe000,\n0x0001,0xe000,\n0x0001,0xe000,\n0x0001,0xe000,\n0x2003,0xc000,\n0x3c0f,0xc000,\n0x3fff,0x8000,\n0x3ffe,0x0000,\n0x0ff8,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 84 (0x54):\n   width 25\n   +-------------------------+\n   |                         |\n   |                         |\n   |                         |\n   |************************ |\n   |************************ |\n   |************************ |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |          ****           |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0xffff,0xff00,\n0xffff,0xff00,\n0xffff,0xff00,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x003c,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 85 (0x55):\n   width 27\n   +---------------------------+\n   |                           |\n   |                           |\n   |                           |\n   |   ****            ****    |\n   |   ****            ****    |\n   |   ****            ****    |\n   |   ****            ****    |\n   |   ****            ****    |\n   |   ****            ****    |\n   |   ****            ****    |\n   |   ****            ****    |\n   |   ****            ****    |\n   |   ****            ****    |\n   |   ****            ****    |\n   |   ****            ****    |\n   |   ****            ****    |\n   |   ****            ****    |\n   |   ****            ****    |\n   |   ****            ****    |\n   |   ****            ****    |\n   |   ****            ****    |\n   |   ****            ****    |\n   |   ****            ****    |\n   |   ****            ****    |\n   |   *****          *****    |\n   |    ****          ****     |\n   |    *****        *****     |\n   |     *****      *****      |\n   |      **************       |\n   |       ************        |\n   |         ********          |\n   |                           |\n   |                           |\n   |                           |\n   |                           |\n   |                           |\n   |                           |\n   |                           |\n   |                           |\n   +---------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x1e00,0x1e00,\n0x1e00,0x1e00,\n0x1e00,0x1e00,\n0x1e00,0x1e00,\n0x1e00,0x1e00,\n0x1e00,0x1e00,\n0x1e00,0x1e00,\n0x1e00,0x1e00,\n0x1e00,0x1e00,\n0x1e00,0x1e00,\n0x1e00,0x1e00,\n0x1e00,0x1e00,\n0x1e00,0x1e00,\n0x1e00,0x1e00,\n0x1e00,0x1e00,\n0x1e00,0x1e00,\n0x1e00,0x1e00,\n0x1e00,0x1e00,\n0x1e00,0x1e00,\n0x1e00,0x1e00,\n0x1e00,0x1e00,\n0x1f00,0x3e00,\n0x0f00,0x3c00,\n0x0f80,0x7c00,\n0x07c0,0xf800,\n0x03ff,0xf000,\n0x01ff,0xe000,\n0x007f,0x8000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 86 (0x56):\n   width 26\n   +--------------------------+\n   |                          |\n   |                          |\n   |                          |\n   | ****                  ***|\n   |  ****                *** |\n   |  ****                *** |\n   |  *****              **** |\n   |   ****              ***  |\n   |   ****              ***  |\n   |    ****            ****  |\n   |    ****            ***   |\n   |    *****           ***   |\n   |     ****          ***    |\n   |     ****          ***    |\n   |     *****        ****    |\n   |      ****        ***     |\n   |      ****        ***     |\n   |       ****      ****     |\n   |       ****      ***      |\n   |       *****     ***      |\n   |        ****    ****      |\n   |        ****    ***       |\n   |         ****   ***       |\n   |         ****  ***        |\n   |         ***** ***        |\n   |          ********        |\n   |          *******         |\n   |          *******         |\n   |           ******         |\n   |           *****          |\n   |            ****          |\n   |                          |\n   |                          |\n   |                          |\n   |                          |\n   |                          |\n   |                          |\n   |                          |\n   |                          |\n   +--------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x7800,0x01c0,\n0x3c00,0x0380,\n0x3c00,0x0380,\n0x3e00,0x0780,\n0x1e00,0x0700,\n0x1e00,0x0700,\n0x0f00,0x0f00,\n0x0f00,0x0e00,\n0x0f80,0x0e00,\n0x0780,0x1c00,\n0x0780,0x1c00,\n0x07c0,0x3c00,\n0x03c0,0x3800,\n0x03c0,0x3800,\n0x01e0,0x7800,\n0x01e0,0x7000,\n0x01f0,0x7000,\n0x00f0,0xf000,\n0x00f0,0xe000,\n0x0078,0xe000,\n0x0079,0xc000,\n0x007d,0xc000,\n0x003f,0xc000,\n0x003f,0x8000,\n0x003f,0x8000,\n0x001f,0x8000,\n0x001f,0x0000,\n0x000f,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 87 (0x57):\n   width 33\n   +---------------------------------+\n   |                                 |\n   |                                 |\n   |                                 |\n   |****           ****           ***|\n   |****           ****          ****|\n   | ****         ******         *** |\n   | ****         ******         *** |\n   | ****         ******         *** |\n   | ****         ******        ***  |\n   |  ****       *******        ***  |\n   |  ****       *** ****       ***  |\n   |  ****       *** ****      ****  |\n   |  *****      *** ****      ***   |\n   |   ****     ***  ****      ***   |\n   |   ****     ***  ****      ***   |\n   |   ****     ***   ****    ***    |\n   |   *****    ***   ****    ***    |\n   |    ****   ***    ****    ***    |\n   |    ****   ***    ****   ****    |\n   |    ****   ***    *****  ***     |\n   |    ***** ****     ****  ***     |\n   |     **** ***      ****  ***     |\n   |     **** ***      **** ***      |\n   |     **** ***      **** ***      |\n   |     ********       *******      |\n   |      ******        *******      |\n   |      ******        ******       |\n   |      ******        ******       |\n   |      ******        ******       |\n   |       ****          ****        |\n   |       ****          ****        |\n   |                                 |\n   |                                 |\n   |                                 |\n   |                                 |\n   |                                 |\n   |                                 |\n   |                                 |\n   |                                 |\n   +---------------------------------+ */\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0xf001,0xe003,0x8000,\n0xf001,0xe007,0x8000,\n0x7803,0xf007,0x0000,\n0x7803,0xf007,0x0000,\n0x7803,0xf007,0x0000,\n0x7803,0xf00e,0x0000,\n0x3c07,0xf00e,0x0000,\n0x3c07,0x780e,0x0000,\n0x3c07,0x781e,0x0000,\n0x3e07,0x781c,0x0000,\n0x1e0e,0x781c,0x0000,\n0x1e0e,0x781c,0x0000,\n0x1e0e,0x3c38,0x0000,\n0x1f0e,0x3c38,0x0000,\n0x0f1c,0x3c38,0x0000,\n0x0f1c,0x3c78,0x0000,\n0x0f1c,0x3e70,0x0000,\n0x0fbc,0x1e70,0x0000,\n0x07b8,0x1e70,0x0000,\n0x07b8,0x1ee0,0x0000,\n0x07b8,0x1ee0,0x0000,\n0x07f8,0x0fe0,0x0000,\n0x03f0,0x0fe0,0x0000,\n0x03f0,0x0fc0,0x0000,\n0x03f0,0x0fc0,0x0000,\n0x03f0,0x0fc0,0x0000,\n0x01e0,0x0780,0x0000,\n0x01e0,0x0780,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n\n/* Character 88 (0x58):\n   width 24\n   +------------------------+\n   |                        |\n   |                        |\n   |                        |\n   |*****              **** |\n   | *****            ****  |\n   |  ****            ***   |\n   |  *****          ****   |\n   |   *****        ****    |\n   |    ****        ***     |\n   |    *****      ****     |\n   |     *****    ****      |\n   |      ****    ***       |\n   |      *****  ****       |\n   |       *********        |\n   |       ********         |\n   |        *******         |\n   |         *****          |\n   |         *****          |\n   |        *******         |\n   |        ********        |\n   |       *********        |\n   |      ****  *****       |\n   |      ***    ****       |\n   |     ****    *****      |\n   |    ****      *****     |\n   |    ***        ****     |\n   |   ****        *****    |\n   |  ****          *****   |\n   |  ***            ****   |\n   | ****            *****  |\n   |****              ***** |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   +------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0xf800,0x1e00,\n0x7c00,0x3c00,\n0x3c00,0x3800,\n0x3e00,0x7800,\n0x1f00,0xf000,\n0x0f00,0xe000,\n0x0f81,0xe000,\n0x07c3,0xc000,\n0x03c3,0x8000,\n0x03e7,0x8000,\n0x01ff,0x0000,\n0x01fe,0x0000,\n0x00fe,0x0000,\n0x007c,0x0000,\n0x007c,0x0000,\n0x00fe,0x0000,\n0x00ff,0x0000,\n0x01ff,0x0000,\n0x03cf,0x8000,\n0x0387,0x8000,\n0x0787,0xc000,\n0x0f03,0xe000,\n0x0e01,0xe000,\n0x1e01,0xf000,\n0x3c00,0xf800,\n0x3800,0x7800,\n0x7800,0x7c00,\n0xf000,0x3e00,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 89 (0x59):\n   width 24\n   +------------------------+\n   |                        |\n   |                        |\n   |                        |\n   |*****              **** |\n   | ****              ***  |\n   | *****            ***   |\n   |  *****          ****   |\n   |  *****          ***    |\n   |   *****        ****    |\n   |    ****       ****     |\n   |    *****      ***      |\n   |     ****     ****      |\n   |     *****    ***       |\n   |      ****   ****       |\n   |      ***** ****        |\n   |       **** ***         |\n   |       ********         |\n   |        ******          |\n   |         ****           |\n   |         ****           |\n   |         ****           |\n   |         ****           |\n   |         ****           |\n   |         ****           |\n   |         ****           |\n   |         ****           |\n   |         ****           |\n   |         ****           |\n   |         ****           |\n   |         ****           |\n   |         ****           |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   +------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0xf800,0x1e00,\n0x7800,0x1c00,\n0x7c00,0x3800,\n0x3e00,0x7800,\n0x3e00,0x7000,\n0x1f00,0xf000,\n0x0f01,0xe000,\n0x0f81,0xc000,\n0x0783,0xc000,\n0x07c3,0x8000,\n0x03c7,0x8000,\n0x03ef,0x0000,\n0x01ee,0x0000,\n0x01fe,0x0000,\n0x00fc,0x0000,\n0x0078,0x0000,\n0x0078,0x0000,\n0x0078,0x0000,\n0x0078,0x0000,\n0x0078,0x0000,\n0x0078,0x0000,\n0x0078,0x0000,\n0x0078,0x0000,\n0x0078,0x0000,\n0x0078,0x0000,\n0x0078,0x0000,\n0x0078,0x0000,\n0x0078,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 90 (0x5a):\n   width 24\n   +------------------------+\n   |                        |\n   |                        |\n   |                        |\n   |   *******************  |\n   |   *******************  |\n   |   *******************  |\n   |                 *****  |\n   |                *****   |\n   |               *****    |\n   |               *****    |\n   |              *****     |\n   |             *****      |\n   |             *****      |\n   |            *****       |\n   |           *****        |\n   |           ****         |\n   |          *****         |\n   |         *****          |\n   |         ****           |\n   |        *****           |\n   |       *****            |\n   |      *****             |\n   |      *****             |\n   |     *****              |\n   |    *****               |\n   |    *****               |\n   |   *****                |\n   |  *****                 |\n   |  ********************  |\n   |  ********************  |\n   |  ********************  |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   +------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x1fff,0xfc00,\n0x1fff,0xfc00,\n0x1fff,0xfc00,\n0x0000,0x7c00,\n0x0000,0xf800,\n0x0001,0xf000,\n0x0001,0xf000,\n0x0003,0xe000,\n0x0007,0xc000,\n0x0007,0xc000,\n0x000f,0x8000,\n0x001f,0x0000,\n0x001e,0x0000,\n0x003e,0x0000,\n0x007c,0x0000,\n0x0078,0x0000,\n0x00f8,0x0000,\n0x01f0,0x0000,\n0x03e0,0x0000,\n0x03e0,0x0000,\n0x07c0,0x0000,\n0x0f80,0x0000,\n0x0f80,0x0000,\n0x1f00,0x0000,\n0x3e00,0x0000,\n0x3fff,0xfc00,\n0x3fff,0xfc00,\n0x3fff,0xfc00,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 91 (0x5b):\n   width 13\n   +-------------+\n   |             |\n   |    ******** |\n   |    ******** |\n   |    ******** |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ******** |\n   |    ******** |\n   |    ******** |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x0ff0,\n0x0ff0,\n0x0ff0,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0ff0,\n0x0ff0,\n0x0ff0,\n0x0000,\n0x0000,\n\n/* Character 92 (0x5c):\n   width 20\n   +--------------------+\n   |                    |\n   |                    |\n   |                    |\n   |    **              |\n   |    **              |\n   |     **             |\n   |     **             |\n   |     **             |\n   |      **            |\n   |      **            |\n   |      **            |\n   |       *            |\n   |       **           |\n   |       **           |\n   |       **           |\n   |        **          |\n   |        **          |\n   |        **          |\n   |         **         |\n   |         **         |\n   |         **         |\n   |         **         |\n   |          **        |\n   |          **        |\n   |          **        |\n   |           **       |\n   |           **       |\n   |           **       |\n   |            *       |\n   |            **      |\n   |            **      |\n   |            **      |\n   |             **     |\n   |             **     |\n   |             **     |\n   |              **    |\n   |              **    |\n   |                    |\n   |                    |\n   +--------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0c00,0x0000,\n0x0c00,0x0000,\n0x0600,0x0000,\n0x0600,0x0000,\n0x0600,0x0000,\n0x0300,0x0000,\n0x0300,0x0000,\n0x0300,0x0000,\n0x0100,0x0000,\n0x0180,0x0000,\n0x0180,0x0000,\n0x0180,0x0000,\n0x00c0,0x0000,\n0x00c0,0x0000,\n0x00c0,0x0000,\n0x0060,0x0000,\n0x0060,0x0000,\n0x0060,0x0000,\n0x0060,0x0000,\n0x0030,0x0000,\n0x0030,0x0000,\n0x0030,0x0000,\n0x0018,0x0000,\n0x0018,0x0000,\n0x0018,0x0000,\n0x0008,0x0000,\n0x000c,0x0000,\n0x000c,0x0000,\n0x000c,0x0000,\n0x0006,0x0000,\n0x0006,0x0000,\n0x0006,0x0000,\n0x0003,0x0000,\n0x0003,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 93 (0x5d):\n   width 13\n   +-------------+\n   |             |\n   | ********    |\n   | ********    |\n   | ********    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   | ********    |\n   | ********    |\n   | ********    |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x7f80,\n0x7f80,\n0x7f80,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x7f80,\n0x7f80,\n0x7f80,\n0x0000,\n0x0000,\n\n/* Character 94 (0x5e):\n   width 25\n   +-------------------------+\n   |                         |\n   |                         |\n   |                         |\n   |            *            |\n   |            *            |\n   |           ***           |\n   |           ***           |\n   |          *****          |\n   |          *****          |\n   |         *** ***         |\n   |         *** ***         |\n   |        ***   ***        |\n   |        ***   ***        |\n   |       ***     ***       |\n   |       ***     ***       |\n   |      ***       ***      |\n   |      ***       ***      |\n   |     ***         ***     |\n   |     ***         ***     |\n   |    ***           ***    |\n   |    ***           ***    |\n   |   ***             ***   |\n   |   ***             ***   |\n   |  ***               ***  |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0008,0x0000,\n0x0008,0x0000,\n0x001c,0x0000,\n0x001c,0x0000,\n0x003e,0x0000,\n0x003e,0x0000,\n0x0077,0x0000,\n0x0077,0x0000,\n0x00e3,0x8000,\n0x00e3,0x8000,\n0x01c1,0xc000,\n0x01c1,0xc000,\n0x0380,0xe000,\n0x0380,0xe000,\n0x0700,0x7000,\n0x0700,0x7000,\n0x0e00,0x3800,\n0x0e00,0x3800,\n0x1c00,0x1c00,\n0x1c00,0x1c00,\n0x3800,0x0e00,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 95 (0x5f):\n   width 20\n   +--------------------+\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |  ****************  |\n   |  ****************  |\n   |  ****************  |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   +--------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x3fff,0xc000,\n0x3fff,0xc000,\n0x3fff,0xc000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 96 (0x60):\n   width 24\n   +------------------------+\n   |                        |\n   |        *****           |\n   |         *****          |\n   |          ****          |\n   |           ****         |\n   |            ****        |\n   |             ****       |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   +------------------------+ */\n0x0000,0x0000,\n0x00f8,0x0000,\n0x007c,0x0000,\n0x003c,0x0000,\n0x001e,0x0000,\n0x000f,0x0000,\n0x0007,0x8000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 97 (0x61):\n   width 22\n   +----------------------+\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |        *******       |\n   |     ***********      |\n   |    *************     |\n   |    ***     ******    |\n   |    *         ****    |\n   |              ****    |\n   |              ****    |\n   |              ****    |\n   |              ****    |\n   |        **********    |\n   |     *************    |\n   |    *****     ****    |\n   |   ****       ****    |\n   |  ****        ****    |\n   |  ****        ****    |\n   |  ****        ****    |\n   |  ****       *****    |\n   |  *****     *******   |\n   |   *********** ****** |\n   |    *********  ****** |\n   |     ******     ***** |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   +----------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x00fe,0x0000,\n0x07ff,0x0000,\n0x0fff,0x8000,\n0x0e0f,0xc000,\n0x0803,0xc000,\n0x0003,0xc000,\n0x0003,0xc000,\n0x0003,0xc000,\n0x0003,0xc000,\n0x00ff,0xc000,\n0x07ff,0xc000,\n0x0f83,0xc000,\n0x1e03,0xc000,\n0x3c03,0xc000,\n0x3c03,0xc000,\n0x3c03,0xc000,\n0x3c07,0xc000,\n0x3e0f,0xe000,\n0x1ffd,0xf800,\n0x0ff9,0xf800,\n0x07e0,0xf800,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 98 (0x62):\n   width 25\n   +-------------------------+\n   |                         |\n   |    ****                 |\n   |    ****                 |\n   |    ****                 |\n   |    ****                 |\n   |    ****                 |\n   |    ****                 |\n   |    ****                 |\n   |    ****                 |\n   |    ****                 |\n   |    ****    ******       |\n   |    ****  **********     |\n   |    **** ************    |\n   |    ********    *****    |\n   |    ******        ****   |\n   |    *****         ****   |\n   |    ****           ****  |\n   |    ****           ****  |\n   |    ****           ****  |\n   |    ****           ****  |\n   |    ****           ****  |\n   |    ****           ****  |\n   |    ****           ****  |\n   |    ****           ****  |\n   |    ****          ****   |\n   |    ****          ****   |\n   |    *****        *****   |\n   |    *******     *****    |\n   |    ****************     |\n   |    **** **********      |\n   |    ****   ******        |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f0f,0xc000,\n0x0f3f,0xf000,\n0x0f7f,0xf800,\n0x0ff0,0xf800,\n0x0fc0,0x3c00,\n0x0f80,0x3c00,\n0x0f00,0x1e00,\n0x0f00,0x1e00,\n0x0f00,0x1e00,\n0x0f00,0x1e00,\n0x0f00,0x1e00,\n0x0f00,0x1e00,\n0x0f00,0x1e00,\n0x0f00,0x1e00,\n0x0f00,0x3c00,\n0x0f00,0x3c00,\n0x0f80,0x7c00,\n0x0fe0,0xf800,\n0x0fff,0xf000,\n0x0f7f,0xe000,\n0x0f1f,0x8000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 99 (0x63):\n   width 20\n   +--------------------+\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |         *******    |\n   |      ************  |\n   |     *************  |\n   |    ******      **  |\n   |   *****            |\n   |   ****             |\n   |   ****             |\n   |  ****              |\n   |  ****              |\n   |  ****              |\n   |  ****              |\n   |  ****              |\n   |  ****              |\n   |  ****              |\n   |   ****             |\n   |   ****             |\n   |    ****            |\n   |    ******      **  |\n   |     *************  |\n   |      ************  |\n   |         *******    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   +--------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x007f,0x0000,\n0x03ff,0xc000,\n0x07ff,0xc000,\n0x0fc0,0xc000,\n0x1f00,0x0000,\n0x1e00,0x0000,\n0x1e00,0x0000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x1e00,0x0000,\n0x1e00,0x0000,\n0x0f00,0x0000,\n0x0fc0,0xc000,\n0x07ff,0xc000,\n0x03ff,0xc000,\n0x007f,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 100 (0x64):\n   width 25\n   +-------------------------+\n   |                         |\n   |                 ****    |\n   |                 ****    |\n   |                 ****    |\n   |                 ****    |\n   |                 ****    |\n   |                 ****    |\n   |                 ****    |\n   |                 ****    |\n   |                 ****    |\n   |        ******   ****    |\n   |      ********** ****    |\n   |     ****************    |\n   |    *****     *******    |\n   |   *****        *****    |\n   |   ****          ****    |\n   |   ****          ****    |\n   |  ****           ****    |\n   |  ****           ****    |\n   |  ****           ****    |\n   |  ****           ****    |\n   |  ****           ****    |\n   |  ****           ****    |\n   |  ****           ****    |\n   |  ****           ****    |\n   |   ****         *****    |\n   |   ****        ******    |\n   |    *****    ********    |\n   |    ************ ****    |\n   |     **********  ****    |\n   |       ******    ****    |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0000,0x7800,\n0x0000,0x7800,\n0x0000,0x7800,\n0x0000,0x7800,\n0x0000,0x7800,\n0x0000,0x7800,\n0x0000,0x7800,\n0x0000,0x7800,\n0x0000,0x7800,\n0x00fc,0x7800,\n0x03ff,0x7800,\n0x07ff,0xf800,\n0x0f83,0xf800,\n0x1f00,0xf800,\n0x1e00,0x7800,\n0x1e00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x1e00,0xf800,\n0x1e01,0xf800,\n0x0f87,0xf800,\n0x0fff,0x7800,\n0x07fe,0x7800,\n0x01f8,0x7800,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 101 (0x65):\n   width 22\n   +----------------------+\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |        ******        |\n   |      **********      |\n   |     ************     |\n   |    ****     *****    |\n   |   ****       ****    |\n   |   ****        ***    |\n   |   ***         ****   |\n   |  ****         ****   |\n   |  *****************   |\n   |  *****************   |\n   |  *****************   |\n   |  ****                |\n   |  ****                |\n   |  *****               |\n   |   ****               |\n   |   *****              |\n   |    ****              |\n   |    ******       **   |\n   |     **************   |\n   |       ************   |\n   |         ********     |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   +----------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x00fc,0x0000,\n0x03ff,0x0000,\n0x07ff,0x8000,\n0x0f07,0xc000,\n0x1e03,0xc000,\n0x1e01,0xc000,\n0x1c01,0xe000,\n0x3c01,0xe000,\n0x3fff,0xe000,\n0x3fff,0xe000,\n0x3fff,0xe000,\n0x3c00,0x0000,\n0x3c00,0x0000,\n0x3e00,0x0000,\n0x1e00,0x0000,\n0x1f00,0x0000,\n0x0f00,0x0000,\n0x0fc0,0x6000,\n0x07ff,0xe000,\n0x01ff,0xe000,\n0x007f,0x8000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 102 (0x66):\n   width 14\n   +--------------+\n   |              |\n   |        ******|\n   |      ********|\n   |     *********|\n   |    *****     |\n   |    ****      |\n   |    ****      |\n   |    ****      |\n   |    ****      |\n   |    ****      |\n   | ************ |\n   | ************ |\n   | ************ |\n   |    ****      |\n   |    ****      |\n   |    ****      |\n   |    ****      |\n   |    ****      |\n   |    ****      |\n   |    ****      |\n   |    ****      |\n   |    ****      |\n   |    ****      |\n   |    ****      |\n   |    ****      |\n   |    ****      |\n   |    ****      |\n   |    ****      |\n   |    ****      |\n   |    ****      |\n   |    ****      |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   |              |\n   +--------------+ */\n0x0000,\n0x00fc,\n0x03fe,\n0x07fe,\n0x0f82,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x7ff8,\n0x7ff8,\n0x7ff8,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 103 (0x67):\n   width 24\n   +------------------------+\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |        ******   ****   |\n   |      *********  ****   |\n   |     ****************   |\n   |    *****     *******   |\n   |   *****        *****   |\n   |   ****          ****   |\n   |   ****          ****   |\n   |  ****           ****   |\n   |  ****           ****   |\n   |  ****           ****   |\n   |  ****           ****   |\n   |  ****           ****   |\n   |  ****           ****   |\n   |  ****           ****   |\n   |  ****           ****   |\n   |   ****         *****   |\n   |   ****        ******   |\n   |    *****    ********   |\n   |    ************ ****   |\n   |     **********  ****   |\n   |       ******    ****   |\n   |                 ****   |\n   |                 ***    |\n   |                ****    |\n   |               *****    |\n   |    **        *****     |\n   |    **************      |\n   |    *************       |\n   |      *********         |\n   +------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x00fc,0x7800,\n0x03fe,0x7800,\n0x07ff,0xf800,\n0x0f83,0xf800,\n0x1f00,0xf800,\n0x1e00,0x7800,\n0x1e00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x1e00,0xf800,\n0x1e01,0xf800,\n0x0f87,0xf800,\n0x0fff,0x7800,\n0x07fe,0x7800,\n0x01f8,0x7800,\n0x0000,0x7800,\n0x0000,0x7000,\n0x0000,0xf000,\n0x0001,0xf000,\n0x0c03,0xe000,\n0x0fff,0xc000,\n0x0fff,0x8000,\n0x03fe,0x0000,\n\n/* Character 104 (0x68):\n   width 24\n   +------------------------+\n   |                        |\n   |    ****                |\n   |    ****                |\n   |    ****                |\n   |    ****                |\n   |    ****                |\n   |    ****                |\n   |    ****                |\n   |    ****                |\n   |    ****                |\n   |    ****     *****      |\n   |    ****   ********     |\n   |    **** ***********    |\n   |    **** ***    *****   |\n   |    *******      ****   |\n   |    ******       ****   |\n   |    *****        ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   +------------------------+ */\n0x0000,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f07,0xc000,\n0x0f1f,0xe000,\n0x0f7f,0xf000,\n0x0f70,0xf800,\n0x0fe0,0x7800,\n0x0fc0,0x7800,\n0x0f80,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 105 (0x69):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |           |\n   |           |\n   |           |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0000,\n0x0000,\n0x0000,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 106 (0x6a):\n   width 15\n   +---------------+\n   |               |\n   |               |\n   |               |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |               |\n   |               |\n   |               |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |       ****    |\n   |*     ****     |\n   |**********     |\n   |*********      |\n   | ******        |\n   +---------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x0000,\n0x0000,\n0x0000,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x01e0,\n0x83c0,\n0xffc0,\n0xff80,\n0x7e00,\n\n/* Character 107 (0x6b):\n   width 23\n   +-----------------------+\n   |                       |\n   |    ****               |\n   |    ****               |\n   |    ****               |\n   |    ****               |\n   |    ****               |\n   |    ****               |\n   |    ****               |\n   |    ****               |\n   |    ****               |\n   |    ****        ***    |\n   |    ****       ****    |\n   |    ****      ****     |\n   |    ****     ****      |\n   |    ****    ****       |\n   |    ****    ****       |\n   |    ****   ****        |\n   |    ****  ****         |\n   |    **** ****          |\n   |    **** ****          |\n   |    *********          |\n   |    **** *****         |\n   |    ****  *****        |\n   |    ****   *****       |\n   |    ****    *****      |\n   |    ****    ******     |\n   |    ****     *****     |\n   |    ****      *****    |\n   |    ****       *****   |\n   |    ****        *****  |\n   |    ****         ***** |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   |                       |\n   +-----------------------+ */\n0x0000,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0xe000,\n0x0f01,0xe000,\n0x0f03,0xc000,\n0x0f07,0x8000,\n0x0f0f,0x0000,\n0x0f0f,0x0000,\n0x0f1e,0x0000,\n0x0f3c,0x0000,\n0x0f78,0x0000,\n0x0f78,0x0000,\n0x0ff8,0x0000,\n0x0f7c,0x0000,\n0x0f3e,0x0000,\n0x0f1f,0x0000,\n0x0f0f,0x8000,\n0x0f0f,0xc000,\n0x0f07,0xc000,\n0x0f03,0xe000,\n0x0f01,0xf000,\n0x0f00,0xf800,\n0x0f00,0x7c00,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 108 (0x6c):\n   width 11\n   +-----------+\n   |           |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |    ****   |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 109 (0x6d):\n   width 36\n   +------------------------------------+\n   |                                    |\n   |                                    |\n   |                                    |\n   |                                    |\n   |                                    |\n   |                                    |\n   |                                    |\n   |                                    |\n   |                                    |\n   |                                    |\n   |    ****    ******       ******     |\n   |    ****   ********     ********    |\n   |    **** ***********  ***********   |\n   |    **** ***    ***** ***    *****  |\n   |    *******      *******      ****  |\n   |    *****        *****        ****  |\n   |    *****        *****        ****  |\n   |    ****         ****         ****  |\n   |    ****         ****         ****  |\n   |    ****         ****         ****  |\n   |    ****         ****         ****  |\n   |    ****         ****         ****  |\n   |    ****         ****         ****  |\n   |    ****         ****         ****  |\n   |    ****         ****         ****  |\n   |    ****         ****         ****  |\n   |    ****         ****         ****  |\n   |    ****         ****         ****  |\n   |    ****         ****         ****  |\n   |    ****         ****         ****  |\n   |    ****         ****         ****  |\n   |                                    |\n   |                                    |\n   |                                    |\n   |                                    |\n   |                                    |\n   |                                    |\n   |                                    |\n   |                                    |\n   +------------------------------------+ */\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0f0f,0xc07e,0x0000,\n0x0f1f,0xe0ff,0x0000,\n0x0f7f,0xf3ff,0x8000,\n0x0f70,0xfb87,0xc000,\n0x0fe0,0x7f03,0xc000,\n0x0f80,0x7c03,0xc000,\n0x0f80,0x7c03,0xc000,\n0x0f00,0x7803,0xc000,\n0x0f00,0x7803,0xc000,\n0x0f00,0x7803,0xc000,\n0x0f00,0x7803,0xc000,\n0x0f00,0x7803,0xc000,\n0x0f00,0x7803,0xc000,\n0x0f00,0x7803,0xc000,\n0x0f00,0x7803,0xc000,\n0x0f00,0x7803,0xc000,\n0x0f00,0x7803,0xc000,\n0x0f00,0x7803,0xc000,\n0x0f00,0x7803,0xc000,\n0x0f00,0x7803,0xc000,\n0x0f00,0x7803,0xc000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n0x0000,0x0000,0x0000,\n\n/* Character 110 (0x6e):\n   width 24\n   +------------------------+\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |    ****     *****      |\n   |    ****   ********     |\n   |    **** ***********    |\n   |    **** ***    *****   |\n   |    *******      ****   |\n   |    ******       ****   |\n   |    *****        ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   +------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0f07,0xc000,\n0x0f1f,0xe000,\n0x0f7f,0xf000,\n0x0f70,0xf800,\n0x0fe0,0x7800,\n0x0fc0,0x7800,\n0x0f80,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 111 (0x6f):\n   width 24\n   +------------------------+\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |         ******         |\n   |      ************      |\n   |     **************     |\n   |    *****      *****    |\n   |   *****        *****   |\n   |   ****          ****   |\n   |   ****          ****   |\n   |  ****            ****  |\n   |  ****            ****  |\n   |  ****            ****  |\n   |  ****            ****  |\n   |  ****            ****  |\n   |  ****            ****  |\n   |  ****            ****  |\n   |   ****          ****   |\n   |   ****          ****   |\n   |   *****        *****   |\n   |    *****      *****    |\n   |     **************     |\n   |      ************      |\n   |         ******         |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   +------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x007e,0x0000,\n0x03ff,0xc000,\n0x07ff,0xe000,\n0x0f81,0xf000,\n0x1f00,0xf800,\n0x1e00,0x7800,\n0x1e00,0x7800,\n0x3c00,0x3c00,\n0x3c00,0x3c00,\n0x3c00,0x3c00,\n0x3c00,0x3c00,\n0x3c00,0x3c00,\n0x3c00,0x3c00,\n0x3c00,0x3c00,\n0x1e00,0x7800,\n0x1e00,0x7800,\n0x1f00,0xf800,\n0x0f81,0xf000,\n0x07ff,0xe000,\n0x03ff,0xc000,\n0x007e,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 112 (0x70):\n   width 25\n   +-------------------------+\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |    ****    ******       |\n   |    ****  **********     |\n   |    **** ************    |\n   |    ********    *****    |\n   |    ******        ****   |\n   |    *****         ****   |\n   |    ****           ****  |\n   |    ****           ****  |\n   |    ****           ****  |\n   |    ****           ****  |\n   |    ****           ****  |\n   |    ****           ****  |\n   |    ****           ****  |\n   |    ****           ****  |\n   |    ****          ****   |\n   |    ****          ****   |\n   |    *****        *****   |\n   |    *******     *****    |\n   |    ****************     |\n   |    **** **********      |\n   |    ****   ******        |\n   |    ****                 |\n   |    ****                 |\n   |    ****                 |\n   |    ****                 |\n   |    ****                 |\n   |    ****                 |\n   |    ****                 |\n   |    ****                 |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0f0f,0xc000,\n0x0f3f,0xf000,\n0x0f7f,0xf800,\n0x0ff0,0xf800,\n0x0fc0,0x3c00,\n0x0f80,0x3c00,\n0x0f00,0x1e00,\n0x0f00,0x1e00,\n0x0f00,0x1e00,\n0x0f00,0x1e00,\n0x0f00,0x1e00,\n0x0f00,0x1e00,\n0x0f00,0x1e00,\n0x0f00,0x1e00,\n0x0f00,0x3c00,\n0x0f00,0x3c00,\n0x0f80,0x7c00,\n0x0fe0,0xf800,\n0x0fff,0xf000,\n0x0f7f,0xe000,\n0x0f1f,0x8000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n0x0f00,0x0000,\n\n/* Character 113 (0x71):\n   width 25\n   +-------------------------+\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |        ******   ****    |\n   |      ********** ****    |\n   |     ****************    |\n   |    *****     *******    |\n   |   *****        *****    |\n   |   ****          ****    |\n   |   ****          ****    |\n   |  ****           ****    |\n   |  ****           ****    |\n   |  ****           ****    |\n   |  ****           ****    |\n   |  ****           ****    |\n   |  ****           ****    |\n   |  ****           ****    |\n   |  ****           ****    |\n   |   ****         *****    |\n   |   ****        ******    |\n   |    *****    ********    |\n   |    ************ ****    |\n   |     **********  ****    |\n   |       ******    ****    |\n   |                 ****    |\n   |                 ****    |\n   |                 ****    |\n   |                 ****    |\n   |                 ****    |\n   |                 ****    |\n   |                 ****    |\n   |                 ****    |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x00fc,0x7800,\n0x03ff,0x7800,\n0x07ff,0xf800,\n0x0f83,0xf800,\n0x1f00,0xf800,\n0x1e00,0x7800,\n0x1e00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x3c00,0x7800,\n0x1e00,0xf800,\n0x1e01,0xf800,\n0x0f87,0xf800,\n0x0fff,0x7800,\n0x07fe,0x7800,\n0x01f8,0x7800,\n0x0000,0x7800,\n0x0000,0x7800,\n0x0000,0x7800,\n0x0000,0x7800,\n0x0000,0x7800,\n0x0000,0x7800,\n0x0000,0x7800,\n0x0000,0x7800,\n\n/* Character 114 (0x72):\n   width 16\n   +----------------+\n   |                |\n   |                |\n   |                |\n   |                |\n   |                |\n   |                |\n   |                |\n   |                |\n   |                |\n   |                |\n   |    ****    *** |\n   |    ****  ***** |\n   |    **** ****** |\n   |    *******     |\n   |    ******      |\n   |    *****       |\n   |    ****        |\n   |    ****        |\n   |    ****        |\n   |    ****        |\n   |    ****        |\n   |    ****        |\n   |    ****        |\n   |    ****        |\n   |    ****        |\n   |    ****        |\n   |    ****        |\n   |    ****        |\n   |    ****        |\n   |    ****        |\n   |    ****        |\n   |                |\n   |                |\n   |                |\n   |                |\n   |                |\n   |                |\n   |                |\n   |                |\n   +----------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0f0e,\n0x0f3e,\n0x0f7e,\n0x0fe0,\n0x0fc0,\n0x0f80,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 115 (0x73):\n   width 20\n   +--------------------+\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |       ******       |\n   |     **********     |\n   |    ***********     |\n   |   *****     **     |\n   |   ****             |\n   |   ****             |\n   |   ****             |\n   |   ******           |\n   |    *******         |\n   |     ********       |\n   |      *********     |\n   |        ********    |\n   |           *****    |\n   |            *****   |\n   |             ****   |\n   |             ****   |\n   |             ****   |\n   |   **      *****    |\n   |   *************    |\n   |   ************     |\n   |     ********       |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   +--------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x01f8,0x0000,\n0x07fe,0x0000,\n0x0ffe,0x0000,\n0x1f06,0x0000,\n0x1e00,0x0000,\n0x1e00,0x0000,\n0x1e00,0x0000,\n0x1f80,0x0000,\n0x0fe0,0x0000,\n0x07f8,0x0000,\n0x03fe,0x0000,\n0x00ff,0x0000,\n0x001f,0x0000,\n0x000f,0x8000,\n0x0007,0x8000,\n0x0007,0x8000,\n0x0007,0x8000,\n0x181f,0x0000,\n0x1fff,0x0000,\n0x1ffe,0x0000,\n0x07f8,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 116 (0x74):\n   width 15\n   +---------------+\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |    ****       |\n   |    ****       |\n   |    ****       |\n   |    ****       |\n   | ************  |\n   | ************  |\n   | ************  |\n   |    ****       |\n   |    ****       |\n   |    ****       |\n   |    ****       |\n   |    ****       |\n   |    ****       |\n   |    ****       |\n   |    ****       |\n   |    ****       |\n   |    ****       |\n   |    ****       |\n   |    ****       |\n   |    ****       |\n   |    ****       |\n   |    *****      |\n   |     ********  |\n   |      *******  |\n   |       ******  |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   |               |\n   +---------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x7ff8,\n0x7ff8,\n0x7ff8,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f00,\n0x0f80,\n0x07f8,\n0x03f8,\n0x01f8,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 117 (0x75):\n   width 24\n   +------------------------+\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****         ****   |\n   |    ****        *****   |\n   |    ****       ******   |\n   |    ****      *******   |\n   |    *****    *** ****   |\n   |     *********** ****   |\n   |      ********   ****   |\n   |       ******    ****   |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   +------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0x7800,\n0x0f00,0xf800,\n0x0f01,0xf800,\n0x0f03,0xf800,\n0x0f87,0x7800,\n0x07ff,0x7800,\n0x03fc,0x7800,\n0x01f8,0x7800,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 118 (0x76):\n   width 20\n   +--------------------+\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |****             ***|\n   | ****           *** |\n   | ****           *** |\n   | *****         **** |\n   |  ****         ***  |\n   |  ****         ***  |\n   |  *****       ***   |\n   |   ****       ***   |\n   |   ****      ****   |\n   |    ****     ***    |\n   |    ****     ***    |\n   |    *****   ***     |\n   |     ****   ***     |\n   |     ****  ****     |\n   |     ***** ***      |\n   |      **** ***      |\n   |      *******       |\n   |       ******       |\n   |       ******       |\n   |       *****        |\n   |        ****        |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   +--------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0xf000,0x7000,\n0x7800,0xe000,\n0x7800,0xe000,\n0x7c01,0xe000,\n0x3c01,0xc000,\n0x3c01,0xc000,\n0x3e03,0x8000,\n0x1e03,0x8000,\n0x1e07,0x8000,\n0x0f07,0x0000,\n0x0f07,0x0000,\n0x0f8e,0x0000,\n0x078e,0x0000,\n0x079e,0x0000,\n0x07dc,0x0000,\n0x03dc,0x0000,\n0x03f8,0x0000,\n0x01f8,0x0000,\n0x01f8,0x0000,\n0x01f0,0x0000,\n0x00f0,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 119 (0x77):\n   width 30\n   +------------------------------+\n   |                              |\n   |                              |\n   |                              |\n   |                              |\n   |                              |\n   |                              |\n   |                              |\n   |                              |\n   |                              |\n   |                              |\n   |****          ****         ***|\n   |*****        *****        ****|\n   | ****        ******       *** |\n   | ****        ******       *** |\n   | ****       *******      **** |\n   |  ****      *******      ***  |\n   |  ****      ********     ***  |\n   |  ****     **** ****    ****  |\n   |  *****    ***  ****    ***   |\n   |   ****    ***  ****    ***   |\n   |   ****   ****  *****  ****   |\n   |   ****   ***    ****  ***    |\n   |    ****  ***    ****  ***    |\n   |    **** ****    **** ****    |\n   |    **** ***     **** ***     |\n   |    ********      *******     |\n   |     *******      *******     |\n   |     ******       ******      |\n   |     ******       ******      |\n   |      *****        *****      |\n   |      ****         ****       |\n   |                              |\n   |                              |\n   |                              |\n   |                              |\n   |                              |\n   |                              |\n   |                              |\n   |                              |\n   +------------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0xf003,0xc01c,\n0xf807,0xc03c,\n0x7807,0xe038,\n0x7807,0xe038,\n0x780f,0xe078,\n0x3c0f,0xe070,\n0x3c0f,0xf070,\n0x3c1e,0xf0f0,\n0x3e1c,0xf0e0,\n0x1e1c,0xf0e0,\n0x1e3c,0xf9e0,\n0x1e38,0x79c0,\n0x0f38,0x79c0,\n0x0f78,0x7bc0,\n0x0f70,0x7b80,\n0x0ff0,0x3f80,\n0x07f0,0x3f80,\n0x07e0,0x3f00,\n0x07e0,0x3f00,\n0x03e0,0x1f00,\n0x03c0,0x1e00,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 120 (0x78):\n   width 24\n   +------------------------+\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |  *****          ****   |\n   |   *****        ****    |\n   |    *****       ***     |\n   |     ****      ****     |\n   |     *****    ****      |\n   |      *****   ****      |\n   |       ***** ****       |\n   |       ***** ***        |\n   |        ********        |\n   |         ******         |\n   |         *****          |\n   |        *******         |\n   |        ********        |\n   |       **** *****       |\n   |      ****  *****       |\n   |      ****   *****      |\n   |     ****     *****     |\n   |    ****       ****     |\n   |    ****       *****    |\n   |   ****         *****   |\n   |  ****           *****  |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   |                        |\n   +------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x3e00,0x7800,\n0x1f00,0xf000,\n0x0f80,0xe000,\n0x0781,0xe000,\n0x07c3,0xc000,\n0x03e3,0xc000,\n0x01f7,0x8000,\n0x01f7,0x0000,\n0x00ff,0x0000,\n0x007e,0x0000,\n0x007c,0x0000,\n0x00fe,0x0000,\n0x00ff,0x0000,\n0x01ef,0x8000,\n0x03cf,0x8000,\n0x03c7,0xc000,\n0x0783,0xe000,\n0x0f01,0xe000,\n0x0f01,0xf000,\n0x1e00,0xf800,\n0x3c00,0x7c00,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 121 (0x79):\n   width 20\n   +--------------------+\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |                    |\n   |****             ***|\n   | ****           *** |\n   | ****           *** |\n   | *****         **** |\n   |  ****         ***  |\n   |  ****         ***  |\n   |  *****       ***   |\n   |   ****       ***   |\n   |   *****     ****   |\n   |    ****     ***    |\n   |    ****     ***    |\n   |    *****   ***     |\n   |     ****   ***     |\n   |     ****  ****     |\n   |      **** ***      |\n   |      **** ***      |\n   |      ********      |\n   |       ******       |\n   |       ******       |\n   |       *****        |\n   |        ****        |\n   |        ****        |\n   |        ***         |\n   |       ****         |\n   |       ***          |\n   |       ***          |\n   |      ****          |\n   |      ***           |\n   |     ****           |\n   +--------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0xf000,0x7000,\n0x7800,0xe000,\n0x7800,0xe000,\n0x7c01,0xe000,\n0x3c01,0xc000,\n0x3c01,0xc000,\n0x3e03,0x8000,\n0x1e03,0x8000,\n0x1f07,0x8000,\n0x0f07,0x0000,\n0x0f07,0x0000,\n0x0f8e,0x0000,\n0x078e,0x0000,\n0x079e,0x0000,\n0x03dc,0x0000,\n0x03dc,0x0000,\n0x03fc,0x0000,\n0x01f8,0x0000,\n0x01f8,0x0000,\n0x01f0,0x0000,\n0x00f0,0x0000,\n0x00f0,0x0000,\n0x00e0,0x0000,\n0x01e0,0x0000,\n0x01c0,0x0000,\n0x01c0,0x0000,\n0x03c0,0x0000,\n0x0380,0x0000,\n0x0780,0x0000,\n\n/* Character 122 (0x7a):\n   width 22\n   +----------------------+\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |   *****************  |\n   |   *****************  |\n   |   *****************  |\n   |              ******  |\n   |             ******   |\n   |             *****    |\n   |            *****     |\n   |           *****      |\n   |          *****       |\n   |         ******       |\n   |        ******        |\n   |       ******         |\n   |       *****          |\n   |      *****           |\n   |     *****            |\n   |    *****             |\n   |   ******             |\n   |  ******              |\n   |  ******************  |\n   |  ******************  |\n   |  ******************  |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   |                      |\n   +----------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x1fff,0xf000,\n0x1fff,0xf000,\n0x1fff,0xf000,\n0x0003,0xf000,\n0x0007,0xe000,\n0x0007,0xc000,\n0x000f,0x8000,\n0x001f,0x0000,\n0x003e,0x0000,\n0x007e,0x0000,\n0x00fc,0x0000,\n0x01f8,0x0000,\n0x01f0,0x0000,\n0x03e0,0x0000,\n0x07c0,0x0000,\n0x0f80,0x0000,\n0x1f80,0x0000,\n0x3f00,0x0000,\n0x3fff,0xf000,\n0x3fff,0xf000,\n0x3fff,0xf000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 123 (0x7b):\n   width 13\n   +-------------+\n   |             |\n   |       ***   |\n   |     *****   |\n   |    ******   |\n   |   ****      |\n   |   ***       |\n   |   ***       |\n   |   ***       |\n   |   ***       |\n   |   ****      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    **       |\n   |   ***       |\n   |*****        |\n   |****         |\n   |*****        |\n   |   ***       |\n   |    **       |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |    ***      |\n   |   ****      |\n   |   ****      |\n   |   ***       |\n   |   ***       |\n   |   ***       |\n   |   ***       |\n   |    ***      |\n   |    ******   |\n   |     *****   |\n   |       ***   |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x01c0,\n0x07c0,\n0x0fc0,\n0x1e00,\n0x1c00,\n0x1c00,\n0x1c00,\n0x1c00,\n0x1e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0c00,\n0x1c00,\n0xf800,\n0xf000,\n0xf800,\n0x1c00,\n0x0c00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x0e00,\n0x1e00,\n0x1e00,\n0x1c00,\n0x1c00,\n0x1c00,\n0x1c00,\n0x0e00,\n0x0fc0,\n0x07c0,\n0x01c0,\n0x0000,\n0x0000,\n\n/* Character 124 (0x7c):\n   width 15\n   +---------------+\n   |               |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |      **       |\n   |               |\n   |               |\n   +---------------+ */\n0x0000,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0300,\n0x0000,\n0x0000,\n\n/* Character 125 (0x7d):\n   width 13\n   +-------------+\n   |             |\n   |  ***        |\n   |  *****      |\n   |  ******     |\n   |     ****    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |     ****    |\n   |     ****    |\n   |     ***     |\n   |     ***     |\n   |     ***     |\n   |     ***     |\n   |     ***     |\n   |      ***    |\n   |       ***** |\n   |        **** |\n   |       ***** |\n   |      ***    |\n   |      **     |\n   |     ***     |\n   |     ***     |\n   |     ***     |\n   |     ***     |\n   |     ***     |\n   |     ****    |\n   |     ****    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |      ***    |\n   |     ***     |\n   |  ******     |\n   |  *****      |\n   |  ***        |\n   |             |\n   |             |\n   +-------------+ */\n0x0000,\n0x3800,\n0x3e00,\n0x3f00,\n0x0780,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0780,\n0x0780,\n0x0700,\n0x0700,\n0x0700,\n0x0700,\n0x0700,\n0x0380,\n0x01f0,\n0x00f0,\n0x01f0,\n0x0380,\n0x0300,\n0x0700,\n0x0700,\n0x0700,\n0x0700,\n0x0700,\n0x0780,\n0x0780,\n0x0380,\n0x0380,\n0x0380,\n0x0380,\n0x0700,\n0x3f00,\n0x3e00,\n0x3800,\n0x0000,\n0x0000,\n\n/* Character 126 (0x7e):\n   width 25\n   +-------------------------+\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |     *****               |\n   |    ********        ***  |\n   |   ***********      ***  |\n   |  ****   *******   ****  |\n   |  ***      ***********   |\n   |  ***        ********    |\n   |               *****     |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x07c0,0x0000,\n0x0ff0,0x0e00,\n0x1ffc,0x0e00,\n0x3c7f,0x1e00,\n0x381f,0xfc00,\n0x3807,0xf800,\n0x0001,0xf000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n\n/* Character 127 (0x7f):\n   width 25\n   +-------------------------+\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |   *                 *   |\n   |  ***               ***  |\n   |   ***    *****    ***   |\n   |    *** ********* ***    |\n   |     ***************     |\n   |      ****     ****      |\n   |     ****       ****     |\n   |     ***         ***     |\n   |    ***           ***    |\n   |    ***           ***    |\n   |    ***           ***    |\n   |    ***           ***    |\n   |    ***           ***    |\n   |     ***         ***     |\n   |     ****       ****     |\n   |      ****     ****      |\n   |     ***************     |\n   |    *** ********* ***    |\n   |   ***    *****    ***   |\n   |  ***               ***  |\n   |   *                 *   |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   |                         |\n   +-------------------------+ */\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x1000,0x0400,\n0x3800,0x0e00,\n0x1c3e,0x1c00,\n0x0eff,0xb800,\n0x07ff,0xf000,\n0x03c1,0xe000,\n0x0780,0xf000,\n0x0700,0x7000,\n0x0e00,0x3800,\n0x0e00,0x3800,\n0x0e00,0x3800,\n0x0e00,0x3800,\n0x0e00,0x3800,\n0x0700,0x7000,\n0x0780,0xf000,\n0x03c1,0xe000,\n0x07ff,0xf000,\n0x0eff,0xb800,\n0x1c3e,0x1c00,\n0x3800,0x0e00,\n0x1000,0x0400,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n0x0000,0x0000,\n};\n\n/* Character->glyph mapping. */\nstatic const unsigned short _lucidasans28_offset[] = {\n  0,\t/* (0x20) */\n  39,\t/* (0x21) */\n  78,\t/* (0x22) */\n  117,\t/* (0x23) */\n  195,\t/* (0x24) */\n  273,\t/* (0x25) */\n  351,\t/* (0x26) */\n  429,\t/* (0x27) */\n  468,\t/* (0x28) */\n  507,\t/* (0x29) */\n  546,\t/* (0x2a) */\n  624,\t/* (0x2b) */\n  702,\t/* (0x2c) */\n  741,\t/* (0x2d) */\n  819,\t/* (0x2e) */\n  858,\t/* (0x2f) */\n  936,\t/* (0x30) */\n  1014,\t/* (0x31) */\n  1092,\t/* (0x32) */\n  1170,\t/* (0x33) */\n  1248,\t/* (0x34) */\n  1326,\t/* (0x35) */\n  1404,\t/* (0x36) */\n  1482,\t/* (0x37) */\n  1560,\t/* (0x38) */\n  1638,\t/* (0x39) */\n  1716,\t/* (0x3a) */\n  1755,\t/* (0x3b) */\n  1794,\t/* (0x3c) */\n  1872,\t/* (0x3d) */\n  1950,\t/* (0x3e) */\n  2028,\t/* (0x3f) */\n  2067,\t/* (0x40) */\n  2184,\t/* (0x41) */\n  2262,\t/* (0x42) */\n  2340,\t/* (0x43) */\n  2418,\t/* (0x44) */\n  2496,\t/* (0x45) */\n  2574,\t/* (0x46) */\n  2652,\t/* (0x47) */\n  2730,\t/* (0x48) */\n  2808,\t/* (0x49) */\n  2847,\t/* (0x4a) */\n  2886,\t/* (0x4b) */\n  2964,\t/* (0x4c) */\n  3042,\t/* (0x4d) */\n  3159,\t/* (0x4e) */\n  3237,\t/* (0x4f) */\n  3315,\t/* (0x50) */\n  3393,\t/* (0x51) */\n  3471,\t/* (0x52) */\n  3549,\t/* (0x53) */\n  3627,\t/* (0x54) */\n  3705,\t/* (0x55) */\n  3783,\t/* (0x56) */\n  3861,\t/* (0x57) */\n  3978,\t/* (0x58) */\n  4056,\t/* (0x59) */\n  4134,\t/* (0x5a) */\n  4212,\t/* (0x5b) */\n  4251,\t/* (0x5c) */\n  4329,\t/* (0x5d) */\n  4368,\t/* (0x5e) */\n  4446,\t/* (0x5f) */\n  4524,\t/* (0x60) */\n  4602,\t/* (0x61) */\n  4680,\t/* (0x62) */\n  4758,\t/* (0x63) */\n  4836,\t/* (0x64) */\n  4914,\t/* (0x65) */\n  4992,\t/* (0x66) */\n  5031,\t/* (0x67) */\n  5109,\t/* (0x68) */\n  5187,\t/* (0x69) */\n  5226,\t/* (0x6a) */\n  5265,\t/* (0x6b) */\n  5343,\t/* (0x6c) */\n  5382,\t/* (0x6d) */\n  5499,\t/* (0x6e) */\n  5577,\t/* (0x6f) */\n  5655,\t/* (0x70) */\n  5733,\t/* (0x71) */\n  5811,\t/* (0x72) */\n  5850,\t/* (0x73) */\n  5928,\t/* (0x74) */\n  5967,\t/* (0x75) */\n  6045,\t/* (0x76) */\n  6123,\t/* (0x77) */\n  6201,\t/* (0x78) */\n  6279,\t/* (0x79) */\n  6357,\t/* (0x7a) */\n  6435,\t/* (0x7b) */\n  6474,\t/* (0x7c) */\n  6513,\t/* (0x7d) */\n  6552,\t/* (0x7e) */\n  6630,\t/* (0x7f) */\n  6630,\t/* (0x80) */\n  6630,\t/* (0x81) */\n  6630,\t/* (0x82) */\n  6630,\t/* (0x83) */\n  6630,\t/* (0x84) */\n  6630,\t/* (0x85) */\n  6630,\t/* (0x86) */\n  6630,\t/* (0x87) */\n  6630,\t/* (0x88) */\n  6630,\t/* (0x89) */\n  6630,\t/* (0x8a) */\n  6630,\t/* (0x8b) */\n  6630,\t/* (0x8c) */\n  6630,\t/* (0x8d) */\n  6630,\t/* (0x8e) */\n  6630,\t/* (0x8f) */\n  6630,\t/* (0x90) */\n  6630,\t/* (0x91) */\n  6630,\t/* (0x92) */\n  6630,\t/* (0x93) */\n  6630,\t/* (0x94) */\n  6630,\t/* (0x95) */\n  6630,\t/* (0x96) */\n  6630,\t/* (0x97) */\n  6630,\t/* (0x98) */\n  6630,\t/* (0x99) */\n  6630,\t/* (0x9a) */\n  6630,\t/* (0x9b) */\n  6630,\t/* (0x9c) */\n  6630,\t/* (0x9d) */\n  6630,\t/* (0x9e) */\n  6630,\t/* (0x9f) */\n  6630,\t/* (0xa0) */\n  6630,\t/* (0xa1) */\n  6630,\t/* (0xa2) */\n  6630,\t/* (0xa3) */\n  6630,\t/* (0xa4) */\n};\n\n/* Character width data. */\nstatic const unsigned char _lucidasans28_width[] = {\n  12,\t/* (0x20) */\n  12,\t/* (0x21) */\n  15,\t/* (0x22) */\n  25,\t/* (0x23) */\n  25,\t/* (0x24) */\n  26,\t/* (0x25) */\n  27,\t/* (0x26) */\n  9,\t/* (0x27) */\n  13,\t/* (0x28) */\n  13,\t/* (0x29) */\n  19,\t/* (0x2a) */\n  31,\t/* (0x2b) */\n  12,\t/* (0x2c) */\n  23,\t/* (0x2d) */\n  12,\t/* (0x2e) */\n  20,\t/* (0x2f) */\n  25,\t/* (0x30) */\n  25,\t/* (0x31) */\n  25,\t/* (0x32) */\n  25,\t/* (0x33) */\n  25,\t/* (0x34) */\n  25,\t/* (0x35) */\n  25,\t/* (0x36) */\n  25,\t/* (0x37) */\n  25,\t/* (0x38) */\n  25,\t/* (0x39) */\n  12,\t/* (0x3a) */\n  12,\t/* (0x3b) */\n  31,\t/* (0x3c) */\n  31,\t/* (0x3d) */\n  31,\t/* (0x3e) */\n  16,\t/* (0x3f) */\n  33,\t/* (0x40) */\n  27,\t/* (0x41) */\n  22,\t/* (0x42) */\n  27,\t/* (0x43) */\n  29,\t/* (0x44) */\n  21,\t/* (0x45) */\n  21,\t/* (0x46) */\n  28,\t/* (0x47) */\n  29,\t/* (0x48) */\n  11,\t/* (0x49) */\n  15,\t/* (0x4a) */\n  25,\t/* (0x4b) */\n  21,\t/* (0x4c) */\n  34,\t/* (0x4d) */\n  29,\t/* (0x4e) */\n  30,\t/* (0x4f) */\n  22,\t/* (0x50) */\n  30,\t/* (0x51) */\n  25,\t/* (0x52) */\n  21,\t/* (0x53) */\n  25,\t/* (0x54) */\n  27,\t/* (0x55) */\n  26,\t/* (0x56) */\n  33,\t/* (0x57) */\n  24,\t/* (0x58) */\n  24,\t/* (0x59) */\n  24,\t/* (0x5a) */\n  13,\t/* (0x5b) */\n  20,\t/* (0x5c) */\n  13,\t/* (0x5d) */\n  25,\t/* (0x5e) */\n  20,\t/* (0x5f) */\n  24,\t/* (0x60) */\n  22,\t/* (0x61) */\n  25,\t/* (0x62) */\n  20,\t/* (0x63) */\n  25,\t/* (0x64) */\n  22,\t/* (0x65) */\n  14,\t/* (0x66) */\n  24,\t/* (0x67) */\n  24,\t/* (0x68) */\n  11,\t/* (0x69) */\n  15,\t/* (0x6a) */\n  23,\t/* (0x6b) */\n  11,\t/* (0x6c) */\n  36,\t/* (0x6d) */\n  24,\t/* (0x6e) */\n  24,\t/* (0x6f) */\n  25,\t/* (0x70) */\n  25,\t/* (0x71) */\n  16,\t/* (0x72) */\n  20,\t/* (0x73) */\n  15,\t/* (0x74) */\n  24,\t/* (0x75) */\n  20,\t/* (0x76) */\n  30,\t/* (0x77) */\n  24,\t/* (0x78) */\n  20,\t/* (0x79) */\n  22,\t/* (0x7a) */\n  13,\t/* (0x7b) */\n  15,\t/* (0x7c) */\n  13,\t/* (0x7d) */\n  25,\t/* (0x7e) */\n  25,\t/* (0x7f) */\n  25,\t/* (0x80) */\n  25,\t/* (0x81) */\n  25,\t/* (0x82) */\n  25,\t/* (0x83) */\n  25,\t/* (0x84) */\n  25,\t/* (0x85) */\n  25,\t/* (0x86) */\n  25,\t/* (0x87) */\n  25,\t/* (0x88) */\n  25,\t/* (0x89) */\n  25,\t/* (0x8a) */\n  25,\t/* (0x8b) */\n  25,\t/* (0x8c) */\n  25,\t/* (0x8d) */\n  25,\t/* (0x8e) */\n  25,\t/* (0x8f) */\n  25,\t/* (0x90) */\n  25,\t/* (0x91) */\n  25,\t/* (0x92) */\n  25,\t/* (0x93) */\n  25,\t/* (0x94) */\n  25,\t/* (0x95) */\n  25,\t/* (0x96) */\n  25,\t/* (0x97) */\n  25,\t/* (0x98) */\n  25,\t/* (0x99) */\n  25,\t/* (0x9a) */\n  25,\t/* (0x9b) */\n  25,\t/* (0x9c) */\n  25,\t/* (0x9d) */\n  25,\t/* (0x9e) */\n  25,\t/* (0x9f) */\n  25,\t/* (0xa0) */\n  25,\t/* (0xa1) */\n  25,\t/* (0xa2) */\n  25,\t/* (0xa3) */\n  25,\t/* (0xa4) */\n};\n\n/* Exported structure definition. */\nconst struct gpanel_font_t font_lucidasans28 = {\n  \"lucidasans28\",\n  36,\n  39,\n  31,\n  32,\n  133,\n  _lucidasans28_bits,\n  _lucidasans28_offset,\n  _lucidasans28_width,\n  164,\n  sizeof(_lucidasans28_bits) / sizeof(_lucidasans28_bits[0]),\n};\n"
  },
  {
    "path": "share/examples/gpanel/fonts/lucidasans7.c",
    "content": "/* Generated by convbdf on Thu Oct  8 21:26:35 2015. */\n#include <sys/gpanel.h>\n\n/* Font information:\n   name: lucidasans7\n   facename: -FreeType-Lucida Sans Unicode-Medium-R-Normal--10-70-100-100-P-48-ISO10646-1\n   w x h: 9x9\n   size: 133\n   ascent: 8\n   descent: 1\n   first char: 32 (0x20)\n   last char: 164 (0xa4)\n   default char: 164 (0xa4)\n   proportional: yes\n   Copyright  1993 Bigelow & Holmes Inc. All rights reserved. Pat. Des. 289,420. Pats. Pend.\n*/\n\n/* Font character bitmap data. */\nstatic const unsigned short _lucidasans7_bits[] = {\n\n/* Character 32 (0x20):\n   width 3\n   +---+\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   +---+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 33 (0x21):\n   width 3\n   +---+\n   |   |\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   |   |\n   | * |\n   |   |\n   +---+ */\n0x0000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n0x4000,\n0x0000,\n\n/* Character 34 (0x22):\n   width 4\n   +----+\n   | * *|\n   | * *|\n   | * *|\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   +----+ */\n0x5000,\n0x5000,\n0x5000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 35 (0x23):\n   width 6\n   +------+\n   |      |\n   |  * * |\n   |  * * |\n   |******|\n   | * *  |\n   |******|\n   | * *  |\n   | * *  |\n   |      |\n   +------+ */\n0x0000,\n0x2800,\n0x2800,\n0xfc00,\n0x5000,\n0xfc00,\n0x5000,\n0x5000,\n0x0000,\n\n/* Character 36 (0x24):\n   width 6\n   +------+\n   |  *   |\n   | **** |\n   |* *   |\n   |* *   |\n   | ***  |\n   |  * * |\n   |  * * |\n   |****  |\n   |  *   |\n   +------+ */\n0x2000,\n0x7800,\n0xa000,\n0xa000,\n0x7000,\n0x2800,\n0x2800,\n0xf000,\n0x2000,\n\n/* Character 37 (0x25):\n   width 7\n   +-------+\n   |       |\n   | *    *|\n   |* *  * |\n   |* * *  |\n   | * * * |\n   |  * * *|\n   | *  * *|\n   |*    * |\n   |       |\n   +-------+ */\n0x0000,\n0x4200,\n0xa400,\n0xa800,\n0x5400,\n0x2a00,\n0x4a00,\n0x8400,\n0x0000,\n\n/* Character 38 (0x26):\n   width 7\n   +-------+\n   |       |\n   |  *    |\n   | * *   |\n   | * *   |\n   | **  * |\n   |*  * * |\n   |*   *  |\n   | *** * |\n   |       |\n   +-------+ */\n0x0000,\n0x2000,\n0x5000,\n0x5000,\n0x6400,\n0x9400,\n0x8800,\n0x7400,\n0x0000,\n\n/* Character 39 (0x27):\n   width 2\n   +--+\n   |* |\n   |* |\n   |* |\n   |  |\n   |  |\n   |  |\n   |  |\n   |  |\n   |  |\n   +--+ */\n0x8000,\n0x8000,\n0x8000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 40 (0x28):\n   width 3\n   +---+\n   |  *|\n   |  *|\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   |  *|\n   |  *|\n   +---+ */\n0x2000,\n0x2000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x2000,\n0x2000,\n\n/* Character 41 (0x29):\n   width 3\n   +---+\n   |*  |\n   |*  |\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   |*  |\n   |*  |\n   +---+ */\n0x8000,\n0x8000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x8000,\n0x8000,\n\n/* Character 42 (0x2a):\n   width 5\n   +-----+\n   |     |\n   | * * |\n   |  *  |\n   | * * |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x5000,\n0x2000,\n0x5000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 43 (0x2b):\n   width 8\n   +--------+\n   |        |\n   |   *    |\n   |   *    |\n   |   *    |\n   |******* |\n   |   *    |\n   |   *    |\n   |   *    |\n   |        |\n   +--------+ */\n0x0000,\n0x1000,\n0x1000,\n0x1000,\n0xfe00,\n0x1000,\n0x1000,\n0x1000,\n0x0000,\n\n/* Character 44 (0x2c):\n   width 3\n   +---+\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   | * |\n   |*  |\n   +---+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x4000,\n0x8000,\n\n/* Character 45 (0x2d):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |      |\n   | **** |\n   |      |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x7800,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 46 (0x2e):\n   width 3\n   +---+\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   | * |\n   |   |\n   +---+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x4000,\n0x0000,\n\n/* Character 47 (0x2f):\n   width 5\n   +-----+\n   |     |\n   |   * |\n   |   * |\n   |  *  |\n   |  *  |\n   |  *  |\n   | *   |\n   | *   |\n   | *   |\n   +-----+ */\n0x0000,\n0x1000,\n0x1000,\n0x2000,\n0x2000,\n0x2000,\n0x4000,\n0x4000,\n0x4000,\n\n/* Character 48 (0x30):\n   width 6\n   +------+\n   |      |\n   | ***  |\n   |*   * |\n   |*   * |\n   |*   * |\n   |*   * |\n   |*   * |\n   | ***  |\n   |      |\n   +------+ */\n0x0000,\n0x7000,\n0x8800,\n0x8800,\n0x8800,\n0x8800,\n0x8800,\n0x7000,\n0x0000,\n\n/* Character 49 (0x31):\n   width 6\n   +------+\n   |      |\n   | **   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |      |\n   +------+ */\n0x0000,\n0x6000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x0000,\n\n/* Character 50 (0x32):\n   width 6\n   +------+\n   |      |\n   |  **  |\n   | *  * |\n   |    * |\n   |   *  |\n   |  *   |\n   | *    |\n   | **** |\n   |      |\n   +------+ */\n0x0000,\n0x3000,\n0x4800,\n0x0800,\n0x1000,\n0x2000,\n0x4000,\n0x7800,\n0x0000,\n\n/* Character 51 (0x33):\n   width 6\n   +------+\n   |      |\n   |  **  |\n   | *  * |\n   |    * |\n   |  **  |\n   |    * |\n   | *  * |\n   |  **  |\n   |      |\n   +------+ */\n0x0000,\n0x3000,\n0x4800,\n0x0800,\n0x3000,\n0x0800,\n0x4800,\n0x3000,\n0x0000,\n\n/* Character 52 (0x34):\n   width 6\n   +------+\n   |      |\n   |   *  |\n   |  **  |\n   | * *  |\n   |*  *  |\n   |***** |\n   |   *  |\n   |   *  |\n   |      |\n   +------+ */\n0x0000,\n0x1000,\n0x3000,\n0x5000,\n0x9000,\n0xf800,\n0x1000,\n0x1000,\n0x0000,\n\n/* Character 53 (0x35):\n   width 6\n   +------+\n   |      |\n   | **** |\n   | *    |\n   | *    |\n   | ***  |\n   |    * |\n   |    * |\n   | ***  |\n   |      |\n   +------+ */\n0x0000,\n0x7800,\n0x4000,\n0x4000,\n0x7000,\n0x0800,\n0x0800,\n0x7000,\n0x0000,\n\n/* Character 54 (0x36):\n   width 6\n   +------+\n   |      |\n   | **** |\n   |*     |\n   |*     |\n   |****  |\n   |*   * |\n   |*   * |\n   | ***  |\n   |      |\n   +------+ */\n0x0000,\n0x7800,\n0x8000,\n0x8000,\n0xf000,\n0x8800,\n0x8800,\n0x7000,\n0x0000,\n\n/* Character 55 (0x37):\n   width 6\n   +------+\n   |      |\n   |***** |\n   |    * |\n   |   *  |\n   |  *   |\n   |  *   |\n   | *    |\n   | *    |\n   |      |\n   +------+ */\n0x0000,\n0xf800,\n0x0800,\n0x1000,\n0x2000,\n0x2000,\n0x4000,\n0x4000,\n0x0000,\n\n/* Character 56 (0x38):\n   width 6\n   +------+\n   |      |\n   | ***  |\n   |*   * |\n   |*   * |\n   | ***  |\n   |*   * |\n   |*   * |\n   | ***  |\n   |      |\n   +------+ */\n0x0000,\n0x7000,\n0x8800,\n0x8800,\n0x7000,\n0x8800,\n0x8800,\n0x7000,\n0x0000,\n\n/* Character 57 (0x39):\n   width 6\n   +------+\n   |      |\n   | ***  |\n   |*   * |\n   |*   * |\n   | **** |\n   |    * |\n   |    * |\n   |****  |\n   |      |\n   +------+ */\n0x0000,\n0x7000,\n0x8800,\n0x8800,\n0x7800,\n0x0800,\n0x0800,\n0xf000,\n0x0000,\n\n/* Character 58 (0x3a):\n   width 3\n   +---+\n   |   |\n   |   |\n   |   |\n   | * |\n   |   |\n   |   |\n   |   |\n   | * |\n   |   |\n   +---+ */\n0x0000,\n0x0000,\n0x0000,\n0x4000,\n0x0000,\n0x0000,\n0x0000,\n0x4000,\n0x0000,\n\n/* Character 59 (0x3b):\n   width 3\n   +---+\n   |   |\n   |   |\n   |   |\n   | * |\n   |   |\n   |   |\n   |   |\n   | * |\n   |*  |\n   +---+ */\n0x0000,\n0x0000,\n0x0000,\n0x4000,\n0x0000,\n0x0000,\n0x0000,\n0x4000,\n0x8000,\n\n/* Character 60 (0x3c):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |      * |\n   |   ***  |\n   | **     |\n   |  ****  |\n   |      * |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0200,\n0x1c00,\n0x6000,\n0x3c00,\n0x0200,\n0x0000,\n\n/* Character 61 (0x3d):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   | ****** |\n   |        |\n   | ****** |\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7e00,\n0x0000,\n0x7e00,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 62 (0x3e):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   | *      |\n   |  ***   |\n   |     ** |\n   |  ****  |\n   | *      |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x4000,\n0x3800,\n0x0600,\n0x3c00,\n0x4000,\n0x0000,\n\n/* Character 63 (0x3f):\n   width 4\n   +----+\n   |    |\n   |*** |\n   |   *|\n   |   *|\n   |  * |\n   | *  |\n   |    |\n   | *  |\n   |    |\n   +----+ */\n0x0000,\n0xe000,\n0x1000,\n0x1000,\n0x2000,\n0x4000,\n0x0000,\n0x4000,\n0x0000,\n\n/* Character 64 (0x40):\n   width 9\n   +---------+\n   |         |\n   |   ****  |\n   | **    * |\n   |*  **  * |\n   |* * *  * |\n   |* *****  |\n   |*        |\n   | ****    |\n   |         |\n   +---------+ */\n0x0000,\n0x1e00,\n0x6100,\n0x9900,\n0xa900,\n0xbe00,\n0x8000,\n0x7800,\n0x0000,\n\n/* Character 65 (0x41):\n   width 7\n   +-------+\n   |       |\n   |   *   |\n   |  * *  |\n   |  * *  |\n   | *   * |\n   | ***** |\n   | *   * |\n   |*     *|\n   |       |\n   +-------+ */\n0x0000,\n0x1000,\n0x2800,\n0x2800,\n0x4400,\n0x7c00,\n0x4400,\n0x8200,\n0x0000,\n\n/* Character 66 (0x42):\n   width 6\n   +------+\n   |      |\n   | ***  |\n   | *  * |\n   | *  * |\n   | ***  |\n   | *  * |\n   | *  * |\n   | ***  |\n   |      |\n   +------+ */\n0x0000,\n0x7000,\n0x4800,\n0x4800,\n0x7000,\n0x4800,\n0x4800,\n0x7000,\n0x0000,\n\n/* Character 67 (0x43):\n   width 7\n   +-------+\n   |       |\n   |  ***  |\n   | *   * |\n   |*      |\n   |*      |\n   |*      |\n   | *   * |\n   |  ***  |\n   |       |\n   +-------+ */\n0x0000,\n0x3800,\n0x4400,\n0x8000,\n0x8000,\n0x8000,\n0x4400,\n0x3800,\n0x0000,\n\n/* Character 68 (0x44):\n   width 7\n   +-------+\n   |       |\n   | ***   |\n   | *  *  |\n   | *   * |\n   | *   * |\n   | *   * |\n   | *  *  |\n   | ***   |\n   |       |\n   +-------+ */\n0x0000,\n0x7000,\n0x4800,\n0x4400,\n0x4400,\n0x4400,\n0x4800,\n0x7000,\n0x0000,\n\n/* Character 69 (0x45):\n   width 5\n   +-----+\n   |     |\n   | ****|\n   | *   |\n   | *   |\n   | *** |\n   | *   |\n   | *   |\n   | ****|\n   |     |\n   +-----+ */\n0x0000,\n0x7800,\n0x4000,\n0x4000,\n0x7000,\n0x4000,\n0x4000,\n0x7800,\n0x0000,\n\n/* Character 70 (0x46):\n   width 5\n   +-----+\n   |     |\n   | ****|\n   | *   |\n   | *   |\n   | *** |\n   | *   |\n   | *   |\n   | *   |\n   |     |\n   +-----+ */\n0x0000,\n0x7800,\n0x4000,\n0x4000,\n0x7000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n\n/* Character 71 (0x47):\n   width 7\n   +-------+\n   |       |\n   |   *** |\n   |  *    |\n   | *     |\n   | *     |\n   | *   * |\n   |  *  * |\n   |   *** |\n   |       |\n   +-------+ */\n0x0000,\n0x1c00,\n0x2000,\n0x4000,\n0x4000,\n0x4400,\n0x2400,\n0x1c00,\n0x0000,\n\n/* Character 72 (0x48):\n   width 7\n   +-------+\n   |       |\n   | *   * |\n   | *   * |\n   | *   * |\n   | ***** |\n   | *   * |\n   | *   * |\n   | *   * |\n   |       |\n   +-------+ */\n0x0000,\n0x4400,\n0x4400,\n0x4400,\n0x7c00,\n0x4400,\n0x4400,\n0x4400,\n0x0000,\n\n/* Character 73 (0x49):\n   width 3\n   +---+\n   |   |\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   |   |\n   +---+ */\n0x0000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n\n/* Character 74 (0x4a):\n   width 4\n   +----+\n   |    |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |**  |\n   +----+ */\n0x0000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0xc000,\n\n/* Character 75 (0x4b):\n   width 7\n   +-------+\n   |       |\n   | *   * |\n   | *  *  |\n   | * *   |\n   | **    |\n   | * *   |\n   | *  *  |\n   | *   * |\n   |       |\n   +-------+ */\n0x0000,\n0x4400,\n0x4800,\n0x5000,\n0x6000,\n0x5000,\n0x4800,\n0x4400,\n0x0000,\n\n/* Character 76 (0x4c):\n   width 5\n   +-----+\n   |     |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   | ****|\n   |     |\n   +-----+ */\n0x0000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x7800,\n0x0000,\n\n/* Character 77 (0x4d):\n   width 9\n   +---------+\n   |         |\n   | *     * |\n   | **   ** |\n   | **   ** |\n   | * * * * |\n   | * * * * |\n   | * * * * |\n   | *  *  * |\n   |         |\n   +---------+ */\n0x0000,\n0x4100,\n0x6300,\n0x6300,\n0x5500,\n0x5500,\n0x5500,\n0x4900,\n0x0000,\n\n/* Character 78 (0x4e):\n   width 7\n   +-------+\n   |       |\n   |*    * |\n   |**   * |\n   |* *  * |\n   |* ** * |\n   |*  * * |\n   |*   ** |\n   |*    * |\n   |       |\n   +-------+ */\n0x0000,\n0x8400,\n0xc400,\n0xa400,\n0xb400,\n0x9400,\n0x8c00,\n0x8400,\n0x0000,\n\n/* Character 79 (0x4f):\n   width 8\n   +--------+\n   |        |\n   |   **   |\n   |  *  *  |\n   | *    * |\n   | *    * |\n   | *    * |\n   |  *  *  |\n   |   **   |\n   |        |\n   +--------+ */\n0x0000,\n0x1800,\n0x2400,\n0x4200,\n0x4200,\n0x4200,\n0x2400,\n0x1800,\n0x0000,\n\n/* Character 80 (0x50):\n   width 6\n   +------+\n   |      |\n   | ***  |\n   | *  * |\n   | *  * |\n   | ***  |\n   | *    |\n   | *    |\n   | *    |\n   |      |\n   +------+ */\n0x0000,\n0x7000,\n0x4800,\n0x4800,\n0x7000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n\n/* Character 81 (0x51):\n   width 8\n   +--------+\n   |        |\n   |   **   |\n   |  *  *  |\n   | *    * |\n   | *    * |\n   | *    * |\n   |  *  *  |\n   |   ***  |\n   |      **|\n   +--------+ */\n0x0000,\n0x1800,\n0x2400,\n0x4200,\n0x4200,\n0x4200,\n0x2400,\n0x1c00,\n0x0300,\n\n/* Character 82 (0x52):\n   width 6\n   +------+\n   |      |\n   | ***  |\n   | *  * |\n   | *  * |\n   | ***  |\n   | * *  |\n   | *  * |\n   | *   *|\n   |      |\n   +------+ */\n0x0000,\n0x7000,\n0x4800,\n0x4800,\n0x7000,\n0x5000,\n0x4800,\n0x4400,\n0x0000,\n\n/* Character 83 (0x53):\n   width 5\n   +-----+\n   |     |\n   | *** |\n   |*    |\n   |*    |\n   | **  |\n   |   * |\n   |   * |\n   |***  |\n   |     |\n   +-----+ */\n0x0000,\n0x7000,\n0x8000,\n0x8000,\n0x6000,\n0x1000,\n0x1000,\n0xe000,\n0x0000,\n\n/* Character 84 (0x54):\n   width 6\n   +------+\n   |      |\n   |***** |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |      |\n   +------+ */\n0x0000,\n0xf800,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x0000,\n\n/* Character 85 (0x55):\n   width 7\n   +-------+\n   |       |\n   | *   * |\n   | *   * |\n   | *   * |\n   | *   * |\n   | *   * |\n   | *   * |\n   |  ***  |\n   |       |\n   +-------+ */\n0x0000,\n0x4400,\n0x4400,\n0x4400,\n0x4400,\n0x4400,\n0x4400,\n0x3800,\n0x0000,\n\n/* Character 86 (0x56):\n   width 7\n   +-------+\n   |       |\n   |*     *|\n   | *   * |\n   | *   * |\n   |  * *  |\n   |  * *  |\n   |  * *  |\n   |   *   |\n   |       |\n   +-------+ */\n0x0000,\n0x8200,\n0x4400,\n0x4400,\n0x2800,\n0x2800,\n0x2800,\n0x1000,\n0x0000,\n\n/* Character 87 (0x57):\n   width 9\n   +---------+\n   |         |\n   |*   *   *|\n   |*   *   *|\n   | * * * * |\n   | * * * * |\n   | * * * * |\n   |  *   *  |\n   |  *   *  |\n   |         |\n   +---------+ */\n0x0000,\n0x8880,\n0x8880,\n0x5500,\n0x5500,\n0x5500,\n0x2200,\n0x2200,\n0x0000,\n\n/* Character 88 (0x58):\n   width 6\n   +------+\n   |      |\n   |*    *|\n   | *  * |\n   |  **  |\n   |  **  |\n   |  **  |\n   | *  * |\n   |*    *|\n   |      |\n   +------+ */\n0x0000,\n0x8400,\n0x4800,\n0x3000,\n0x3000,\n0x3000,\n0x4800,\n0x8400,\n0x0000,\n\n/* Character 89 (0x59):\n   width 6\n   +------+\n   |      |\n   | *   *|\n   |  * * |\n   |  * * |\n   |   *  |\n   |   *  |\n   |   *  |\n   |   *  |\n   |      |\n   +------+ */\n0x0000,\n0x4400,\n0x2800,\n0x2800,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x0000,\n\n/* Character 90 (0x5a):\n   width 6\n   +------+\n   |      |\n   |***** |\n   |    * |\n   |   *  |\n   |  *   |\n   | *    |\n   |*     |\n   |***** |\n   |      |\n   +------+ */\n0x0000,\n0xf800,\n0x0800,\n0x1000,\n0x2000,\n0x4000,\n0x8000,\n0xf800,\n0x0000,\n\n/* Character 91 (0x5b):\n   width 3\n   +---+\n   | **|\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   | **|\n   +---+ */\n0x6000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x6000,\n\n/* Character 92 (0x5c):\n   width 5\n   +-----+\n   |     |\n   | *   |\n   | *   |\n   | *   |\n   |  *  |\n   |  *  |\n   |  *  |\n   |   * |\n   |   * |\n   +-----+ */\n0x0000,\n0x4000,\n0x4000,\n0x4000,\n0x2000,\n0x2000,\n0x2000,\n0x1000,\n0x1000,\n\n/* Character 93 (0x5d):\n   width 3\n   +---+\n   |** |\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   |** |\n   +---+ */\n0xc000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0xc000,\n\n/* Character 94 (0x5e):\n   width 6\n   +------+\n   |      |\n   |   *  |\n   |   *  |\n   |  * * |\n   |  * * |\n   | *   *|\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x1000,\n0x1000,\n0x2800,\n0x2800,\n0x4400,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 95 (0x5f):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |*****|\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0xf800,\n\n/* Character 96 (0x60):\n   width 6\n   +------+\n   |  *   |\n   |   *  |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x2000,\n0x1000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 97 (0x61):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |***   |\n   |   *  |\n   | ***  |\n   |*  *  |\n   | **** |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0xe000,\n0x1000,\n0x7000,\n0x9000,\n0x7800,\n0x0000,\n\n/* Character 98 (0x62):\n   width 6\n   +------+\n   |*     |\n   |*     |\n   |*     |\n   |****  |\n   |*   * |\n   |*   * |\n   |*   * |\n   |****  |\n   |      |\n   +------+ */\n0x8000,\n0x8000,\n0x8000,\n0xf000,\n0x8800,\n0x8800,\n0x8800,\n0xf000,\n0x0000,\n\n/* Character 99 (0x63):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   | *** |\n   |*    |\n   |*    |\n   |*    |\n   | *** |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x7000,\n0x8000,\n0x8000,\n0x8000,\n0x7000,\n0x0000,\n\n/* Character 100 (0x64):\n   width 6\n   +------+\n   |    * |\n   |    * |\n   |    * |\n   | **** |\n   |*   * |\n   |*   * |\n   |*   * |\n   | **** |\n   |      |\n   +------+ */\n0x0800,\n0x0800,\n0x0800,\n0x7800,\n0x8800,\n0x8800,\n0x8800,\n0x7800,\n0x0000,\n\n/* Character 101 (0x65):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   | **  |\n   |*  * |\n   |**** |\n   |*    |\n   | *** |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x6000,\n0x9000,\n0xf000,\n0x8000,\n0x7000,\n0x0000,\n\n/* Character 102 (0x66):\n   width 4\n   +----+\n   |  **|\n   | *  |\n   | *  |\n   |*** |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   |    |\n   +----+ */\n0x3000,\n0x4000,\n0x4000,\n0xe000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n\n/* Character 103 (0x67):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | **** |\n   |*   * |\n   |*   * |\n   |*   * |\n   | **** |\n   |    * |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7800,\n0x8800,\n0x8800,\n0x8800,\n0x7800,\n0x0800,\n\n/* Character 104 (0x68):\n   width 6\n   +------+\n   |*     |\n   |*     |\n   |*     |\n   |* **  |\n   |**  * |\n   |*   * |\n   |*   * |\n   |*   * |\n   |      |\n   +------+ */\n0x8000,\n0x8000,\n0x8000,\n0xb000,\n0xc800,\n0x8800,\n0x8800,\n0x8800,\n0x0000,\n\n/* Character 105 (0x69):\n   width 3\n   +---+\n   |   |\n   | * |\n   |   |\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   |   |\n   +---+ */\n0x0000,\n0x4000,\n0x0000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n\n/* Character 106 (0x6a):\n   width 4\n   +----+\n   |    |\n   |  * |\n   |    |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   +----+ */\n0x0000,\n0x2000,\n0x0000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n\n/* Character 107 (0x6b):\n   width 6\n   +------+\n   | *    |\n   | *    |\n   | *    |\n   | *  * |\n   | * *  |\n   | **   |\n   | * *  |\n   | *  * |\n   |      |\n   +------+ */\n0x4000,\n0x4000,\n0x4000,\n0x4800,\n0x5000,\n0x6000,\n0x5000,\n0x4800,\n0x0000,\n\n/* Character 108 (0x6c):\n   width 3\n   +---+\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   |   |\n   +---+ */\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n\n/* Character 109 (0x6d):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |*** **  |\n   |*  *  * |\n   |*  *  * |\n   |*  *  * |\n   |*  *  * |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0xec00,\n0x9200,\n0x9200,\n0x9200,\n0x9200,\n0x0000,\n\n/* Character 110 (0x6e):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |* **  |\n   |**  * |\n   |*   * |\n   |*   * |\n   |*   * |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0xb000,\n0xc800,\n0x8800,\n0x8800,\n0x8800,\n0x0000,\n\n/* Character 111 (0x6f):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | ***  |\n   |*   * |\n   |*   * |\n   |*   * |\n   | ***  |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7000,\n0x8800,\n0x8800,\n0x8800,\n0x7000,\n0x0000,\n\n/* Character 112 (0x70):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |****  |\n   |*   * |\n   |*   * |\n   |*   * |\n   |****  |\n   |*     |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0xf000,\n0x8800,\n0x8800,\n0x8800,\n0xf000,\n0x8000,\n\n/* Character 113 (0x71):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | **** |\n   |*   * |\n   |*   * |\n   |*   * |\n   | **** |\n   |    * |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7800,\n0x8800,\n0x8800,\n0x8800,\n0x7800,\n0x0800,\n\n/* Character 114 (0x72):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   | * * |\n   | **  |\n   | *   |\n   | *   |\n   | *   |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x5000,\n0x6000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n\n/* Character 115 (0x73):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |**** |\n   |*    |\n   | **  |\n   |   * |\n   |**** |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0xf000,\n0x8000,\n0x6000,\n0x1000,\n0xf000,\n0x0000,\n\n/* Character 116 (0x74):\n   width 4\n   +----+\n   |    |\n   |    |\n   | *  |\n   |*** |\n   | *  |\n   | *  |\n   | *  |\n   | ** |\n   |    |\n   +----+ */\n0x0000,\n0x0000,\n0x4000,\n0xe000,\n0x4000,\n0x4000,\n0x4000,\n0x6000,\n0x0000,\n\n/* Character 117 (0x75):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |*   * |\n   |*   * |\n   |*   * |\n   |*  ** |\n   | ** * |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x8800,\n0x8800,\n0x8800,\n0x9800,\n0x6800,\n0x0000,\n\n/* Character 118 (0x76):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |*   * |\n   | * *  |\n   | * *  |\n   | * *  |\n   |  *   |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x8800,\n0x5000,\n0x5000,\n0x5000,\n0x2000,\n0x0000,\n\n/* Character 119 (0x77):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |*  *  * |\n   |* * * * |\n   |* * * * |\n   | *   *  |\n   | *   *  |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x9200,\n0xaa00,\n0xaa00,\n0x4400,\n0x4400,\n0x0000,\n\n/* Character 120 (0x78):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |*   * |\n   | * *  |\n   |  *   |\n   | * *  |\n   |*   * |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x8800,\n0x5000,\n0x2000,\n0x5000,\n0x8800,\n0x0000,\n\n/* Character 121 (0x79):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |*   * |\n   | * *  |\n   | * *  |\n   | * *  |\n   |  *   |\n   |  *   |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x8800,\n0x5000,\n0x5000,\n0x5000,\n0x2000,\n0x2000,\n\n/* Character 122 (0x7a):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |***** |\n   |   *  |\n   |  *   |\n   | *    |\n   |***** |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0xf800,\n0x1000,\n0x2000,\n0x4000,\n0xf800,\n0x0000,\n\n/* Character 123 (0x7b):\n   width 3\n   +---+\n   | **|\n   | * |\n   | * |\n   | * |\n   |*  |\n   | * |\n   | * |\n   | * |\n   | **|\n   +---+ */\n0x6000,\n0x4000,\n0x4000,\n0x4000,\n0x8000,\n0x4000,\n0x4000,\n0x4000,\n0x6000,\n\n/* Character 124 (0x7c):\n   width 4\n   +----+\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   +----+ */\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n\n/* Character 125 (0x7d):\n   width 3\n   +---+\n   |** |\n   | * |\n   | * |\n   | * |\n   |  *|\n   | * |\n   | * |\n   | * |\n   |** |\n   +---+ */\n0xc000,\n0x4000,\n0x4000,\n0x4000,\n0x2000,\n0x4000,\n0x4000,\n0x4000,\n0xc000,\n\n/* Character 126 (0x7e):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |      |\n   |**  * |\n   |* *** |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0xc800,\n0xb800,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 127 (0x7f):\n   width 6\n   +------+\n   |      |\n   |*    *|\n   | **** |\n   | *  * |\n   | *  * |\n   | **** |\n   |*    *|\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x8400,\n0x7800,\n0x4800,\n0x4800,\n0x7800,\n0x8400,\n0x0000,\n0x0000,\n};\n\n/* Character->glyph mapping. */\nstatic const unsigned short _lucidasans7_offset[] = {\n  0,\t/* (0x20) */\n  9,\t/* (0x21) */\n  18,\t/* (0x22) */\n  27,\t/* (0x23) */\n  36,\t/* (0x24) */\n  45,\t/* (0x25) */\n  54,\t/* (0x26) */\n  63,\t/* (0x27) */\n  72,\t/* (0x28) */\n  81,\t/* (0x29) */\n  90,\t/* (0x2a) */\n  99,\t/* (0x2b) */\n  108,\t/* (0x2c) */\n  117,\t/* (0x2d) */\n  126,\t/* (0x2e) */\n  135,\t/* (0x2f) */\n  144,\t/* (0x30) */\n  153,\t/* (0x31) */\n  162,\t/* (0x32) */\n  171,\t/* (0x33) */\n  180,\t/* (0x34) */\n  189,\t/* (0x35) */\n  198,\t/* (0x36) */\n  207,\t/* (0x37) */\n  216,\t/* (0x38) */\n  225,\t/* (0x39) */\n  234,\t/* (0x3a) */\n  243,\t/* (0x3b) */\n  252,\t/* (0x3c) */\n  261,\t/* (0x3d) */\n  270,\t/* (0x3e) */\n  279,\t/* (0x3f) */\n  288,\t/* (0x40) */\n  297,\t/* (0x41) */\n  306,\t/* (0x42) */\n  315,\t/* (0x43) */\n  324,\t/* (0x44) */\n  333,\t/* (0x45) */\n  342,\t/* (0x46) */\n  351,\t/* (0x47) */\n  360,\t/* (0x48) */\n  369,\t/* (0x49) */\n  378,\t/* (0x4a) */\n  387,\t/* (0x4b) */\n  396,\t/* (0x4c) */\n  405,\t/* (0x4d) */\n  414,\t/* (0x4e) */\n  423,\t/* (0x4f) */\n  432,\t/* (0x50) */\n  441,\t/* (0x51) */\n  450,\t/* (0x52) */\n  459,\t/* (0x53) */\n  468,\t/* (0x54) */\n  477,\t/* (0x55) */\n  486,\t/* (0x56) */\n  495,\t/* (0x57) */\n  504,\t/* (0x58) */\n  513,\t/* (0x59) */\n  522,\t/* (0x5a) */\n  531,\t/* (0x5b) */\n  540,\t/* (0x5c) */\n  549,\t/* (0x5d) */\n  558,\t/* (0x5e) */\n  567,\t/* (0x5f) */\n  576,\t/* (0x60) */\n  585,\t/* (0x61) */\n  594,\t/* (0x62) */\n  603,\t/* (0x63) */\n  612,\t/* (0x64) */\n  621,\t/* (0x65) */\n  630,\t/* (0x66) */\n  639,\t/* (0x67) */\n  648,\t/* (0x68) */\n  657,\t/* (0x69) */\n  666,\t/* (0x6a) */\n  675,\t/* (0x6b) */\n  684,\t/* (0x6c) */\n  693,\t/* (0x6d) */\n  702,\t/* (0x6e) */\n  711,\t/* (0x6f) */\n  720,\t/* (0x70) */\n  729,\t/* (0x71) */\n  738,\t/* (0x72) */\n  747,\t/* (0x73) */\n  756,\t/* (0x74) */\n  765,\t/* (0x75) */\n  774,\t/* (0x76) */\n  783,\t/* (0x77) */\n  792,\t/* (0x78) */\n  801,\t/* (0x79) */\n  810,\t/* (0x7a) */\n  819,\t/* (0x7b) */\n  828,\t/* (0x7c) */\n  837,\t/* (0x7d) */\n  846,\t/* (0x7e) */\n  855,\t/* (0x7f) */\n  855,\t/* (0x80) */\n  855,\t/* (0x81) */\n  855,\t/* (0x82) */\n  855,\t/* (0x83) */\n  855,\t/* (0x84) */\n  855,\t/* (0x85) */\n  855,\t/* (0x86) */\n  855,\t/* (0x87) */\n  855,\t/* (0x88) */\n  855,\t/* (0x89) */\n  855,\t/* (0x8a) */\n  855,\t/* (0x8b) */\n  855,\t/* (0x8c) */\n  855,\t/* (0x8d) */\n  855,\t/* (0x8e) */\n  855,\t/* (0x8f) */\n  855,\t/* (0x90) */\n  855,\t/* (0x91) */\n  855,\t/* (0x92) */\n  855,\t/* (0x93) */\n  855,\t/* (0x94) */\n  855,\t/* (0x95) */\n  855,\t/* (0x96) */\n  855,\t/* (0x97) */\n  855,\t/* (0x98) */\n  855,\t/* (0x99) */\n  855,\t/* (0x9a) */\n  855,\t/* (0x9b) */\n  855,\t/* (0x9c) */\n  855,\t/* (0x9d) */\n  855,\t/* (0x9e) */\n  855,\t/* (0x9f) */\n  855,\t/* (0xa0) */\n  855,\t/* (0xa1) */\n  855,\t/* (0xa2) */\n  855,\t/* (0xa3) */\n  855,\t/* (0xa4) */\n};\n\n/* Character width data. */\nstatic const unsigned char _lucidasans7_width[] = {\n  3,\t/* (0x20) */\n  3,\t/* (0x21) */\n  4,\t/* (0x22) */\n  6,\t/* (0x23) */\n  6,\t/* (0x24) */\n  7,\t/* (0x25) */\n  7,\t/* (0x26) */\n  2,\t/* (0x27) */\n  3,\t/* (0x28) */\n  3,\t/* (0x29) */\n  5,\t/* (0x2a) */\n  8,\t/* (0x2b) */\n  3,\t/* (0x2c) */\n  6,\t/* (0x2d) */\n  3,\t/* (0x2e) */\n  5,\t/* (0x2f) */\n  6,\t/* (0x30) */\n  6,\t/* (0x31) */\n  6,\t/* (0x32) */\n  6,\t/* (0x33) */\n  6,\t/* (0x34) */\n  6,\t/* (0x35) */\n  6,\t/* (0x36) */\n  6,\t/* (0x37) */\n  6,\t/* (0x38) */\n  6,\t/* (0x39) */\n  3,\t/* (0x3a) */\n  3,\t/* (0x3b) */\n  8,\t/* (0x3c) */\n  8,\t/* (0x3d) */\n  8,\t/* (0x3e) */\n  4,\t/* (0x3f) */\n  9,\t/* (0x40) */\n  7,\t/* (0x41) */\n  6,\t/* (0x42) */\n  7,\t/* (0x43) */\n  7,\t/* (0x44) */\n  5,\t/* (0x45) */\n  5,\t/* (0x46) */\n  7,\t/* (0x47) */\n  7,\t/* (0x48) */\n  3,\t/* (0x49) */\n  4,\t/* (0x4a) */\n  7,\t/* (0x4b) */\n  5,\t/* (0x4c) */\n  9,\t/* (0x4d) */\n  7,\t/* (0x4e) */\n  8,\t/* (0x4f) */\n  6,\t/* (0x50) */\n  8,\t/* (0x51) */\n  6,\t/* (0x52) */\n  5,\t/* (0x53) */\n  6,\t/* (0x54) */\n  7,\t/* (0x55) */\n  7,\t/* (0x56) */\n  9,\t/* (0x57) */\n  6,\t/* (0x58) */\n  6,\t/* (0x59) */\n  6,\t/* (0x5a) */\n  3,\t/* (0x5b) */\n  5,\t/* (0x5c) */\n  3,\t/* (0x5d) */\n  6,\t/* (0x5e) */\n  5,\t/* (0x5f) */\n  6,\t/* (0x60) */\n  6,\t/* (0x61) */\n  6,\t/* (0x62) */\n  5,\t/* (0x63) */\n  6,\t/* (0x64) */\n  5,\t/* (0x65) */\n  4,\t/* (0x66) */\n  6,\t/* (0x67) */\n  6,\t/* (0x68) */\n  3,\t/* (0x69) */\n  4,\t/* (0x6a) */\n  6,\t/* (0x6b) */\n  3,\t/* (0x6c) */\n  8,\t/* (0x6d) */\n  6,\t/* (0x6e) */\n  6,\t/* (0x6f) */\n  6,\t/* (0x70) */\n  6,\t/* (0x71) */\n  5,\t/* (0x72) */\n  5,\t/* (0x73) */\n  4,\t/* (0x74) */\n  6,\t/* (0x75) */\n  6,\t/* (0x76) */\n  8,\t/* (0x77) */\n  6,\t/* (0x78) */\n  6,\t/* (0x79) */\n  6,\t/* (0x7a) */\n  3,\t/* (0x7b) */\n  4,\t/* (0x7c) */\n  3,\t/* (0x7d) */\n  6,\t/* (0x7e) */\n  6,\t/* (0x7f) */\n  6,\t/* (0x80) */\n  6,\t/* (0x81) */\n  6,\t/* (0x82) */\n  6,\t/* (0x83) */\n  6,\t/* (0x84) */\n  6,\t/* (0x85) */\n  6,\t/* (0x86) */\n  6,\t/* (0x87) */\n  6,\t/* (0x88) */\n  6,\t/* (0x89) */\n  6,\t/* (0x8a) */\n  6,\t/* (0x8b) */\n  6,\t/* (0x8c) */\n  6,\t/* (0x8d) */\n  6,\t/* (0x8e) */\n  6,\t/* (0x8f) */\n  6,\t/* (0x90) */\n  6,\t/* (0x91) */\n  6,\t/* (0x92) */\n  6,\t/* (0x93) */\n  6,\t/* (0x94) */\n  6,\t/* (0x95) */\n  6,\t/* (0x96) */\n  6,\t/* (0x97) */\n  6,\t/* (0x98) */\n  6,\t/* (0x99) */\n  6,\t/* (0x9a) */\n  6,\t/* (0x9b) */\n  6,\t/* (0x9c) */\n  6,\t/* (0x9d) */\n  6,\t/* (0x9e) */\n  6,\t/* (0x9f) */\n  6,\t/* (0xa0) */\n  6,\t/* (0xa1) */\n  6,\t/* (0xa2) */\n  6,\t/* (0xa3) */\n  6,\t/* (0xa4) */\n};\n\n/* Exported structure definition. */\nconst struct gpanel_font_t font_lucidasans7 = {\n  \"lucidasans7\",\n  9,\n  9,\n  8,\n  32,\n  133,\n  _lucidasans7_bits,\n  _lucidasans7_offset,\n  _lucidasans7_width,\n  164,\n  sizeof(_lucidasans7_bits) / sizeof(_lucidasans7_bits[0]),\n};\n"
  },
  {
    "path": "share/examples/gpanel/fonts/lucidasans9.c",
    "content": "/* Generated by convbdf on Thu Oct  8 21:26:35 2015. */\n#include <sys/gpanel.h>\n\n/* Font information:\n   name: lucidasans9\n   facename: -FreeType-Lucida Sans Unicode-Medium-R-Normal--12-90-100-100-P-60-ISO10646-1\n   w x h: 12x14\n   size: 133\n   ascent: 12\n   descent: 2\n   first char: 32 (0x20)\n   last char: 164 (0xa4)\n   default char: 164 (0xa4)\n   proportional: yes\n   Copyright  1993 Bigelow & Holmes Inc. All rights reserved. Pat. Des. 289,420. Pats. Pend.\n*/\n\n/* Font character bitmap data. */\nstatic const unsigned short _lucidasans9_bits[] = {\n\n/* Character 32 (0x20):\n   width 4\n   +----+\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   +----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 33 (0x21):\n   width 4\n   +----+\n   |    |\n   |    |\n   |    |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   |    |\n   | *  |\n   |    |\n   |    |\n   +----+ */\n0x0000,\n0x0000,\n0x0000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 34 (0x22):\n   width 5\n   +-----+\n   |     |\n   |     |\n   | * * |\n   | * * |\n   | * * |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x5000,\n0x5000,\n0x5000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 35 (0x23):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |   *  * |\n   |  *  *  |\n   | *******|\n   |  *  *  |\n   |  *  *  |\n   |******* |\n   | *  *   |\n   | *  *   |\n   | *  *   |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1200,\n0x2400,\n0x7f00,\n0x2400,\n0x2400,\n0xfe00,\n0x4800,\n0x4800,\n0x4800,\n0x0000,\n0x0000,\n\n/* Character 36 (0x24):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |   *    |\n   |  ****  |\n   | * *    |\n   | * *    |\n   |  **    |\n   |   **   |\n   |   * *  |\n   |   * *  |\n   | * * *  |\n   |  ***   |\n   |   *    |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x1000,\n0x3c00,\n0x5000,\n0x5000,\n0x3000,\n0x1800,\n0x1400,\n0x1400,\n0x5400,\n0x3800,\n0x1000,\n0x0000,\n\n/* Character 37 (0x25):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |        *|\n   | **    * |\n   |*  *  *  |\n   |*  * *   |\n   |*  **    |\n   | ** * ** |\n   |   * *  *|\n   |  *  *  *|\n   | *   *  *|\n   |*     ** |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0080,\n0x6100,\n0x9200,\n0x9400,\n0x9800,\n0x6b00,\n0x1480,\n0x2480,\n0x4480,\n0x8300,\n0x0000,\n0x0000,\n\n/* Character 38 (0x26):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |   **    |\n   |  *  *   |\n   |  *  *   |\n   |   **    |\n   |  **   * |\n   | *  *  * |\n   | *   * * |\n   | **  **  |\n   |  *** ** |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1800,\n0x2400,\n0x2400,\n0x1800,\n0x3100,\n0x4900,\n0x4500,\n0x6600,\n0x3b00,\n0x0000,\n0x0000,\n\n/* Character 39 (0x27):\n   width 3\n   +---+\n   |   |\n   |   |\n   | * |\n   | * |\n   | * |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   +---+ */\n0x0000,\n0x0000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 40 (0x28):\n   width 4\n   +----+\n   |    |\n   |    |\n   |   *|\n   |  * |\n   |  * |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   |  * |\n   |  * |\n   |   *|\n   +----+ */\n0x0000,\n0x0000,\n0x1000,\n0x2000,\n0x2000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x2000,\n0x2000,\n0x1000,\n\n/* Character 41 (0x29):\n   width 4\n   +----+\n   |    |\n   |    |\n   |*   |\n   | *  |\n   | *  |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   | *  |\n   | *  |\n   |*   |\n   +----+ */\n0x0000,\n0x0000,\n0x8000,\n0x4000,\n0x4000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x4000,\n0x4000,\n0x8000,\n\n/* Character 42 (0x2a):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |  *   |\n   |* * * |\n   | * *  |\n   | * *  |\n   | * *  |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x2000,\n0xa800,\n0x5000,\n0x5000,\n0x5000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 43 (0x2b):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   |    *     |\n   |    *     |\n   |    *     |\n   | *******  |\n   |    *     |\n   |    *     |\n   |    *     |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0800,\n0x0800,\n0x0800,\n0x7f00,\n0x0800,\n0x0800,\n0x0800,\n0x0000,\n0x0000,\n\n/* Character 44 (0x2c):\n   width 4\n   +----+\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   | ** |\n   | ** |\n   |  * |\n   | *  |\n   +----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x6000,\n0x6000,\n0x2000,\n0x4000,\n\n/* Character 45 (0x2d):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   | ****** |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x7e00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 46 (0x2e):\n   width 4\n   +----+\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   | ** |\n   | ** |\n   |    |\n   |    |\n   +----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x6000,\n0x6000,\n0x0000,\n0x0000,\n\n/* Character 47 (0x2f):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |    *  |\n   |    *  |\n   |   *   |\n   |   *   |\n   |   *   |\n   |  *    |\n   |  *    |\n   |  *    |\n   | *     |\n   | *     |\n   | *     |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0800,\n0x0800,\n0x1000,\n0x1000,\n0x1000,\n0x2000,\n0x2000,\n0x2000,\n0x4000,\n0x4000,\n0x4000,\n\n/* Character 48 (0x30):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |  ***   |\n   | *   *  |\n   |*     * |\n   |*     * |\n   |*     * |\n   |*     * |\n   |*     * |\n   | *   *  |\n   |  ***   |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3800,\n0x4400,\n0x8200,\n0x8200,\n0x8200,\n0x8200,\n0x8200,\n0x4400,\n0x3800,\n0x0000,\n0x0000,\n\n/* Character 49 (0x31):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   | ***    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x0000,\n0x0000,\n\n/* Character 50 (0x32):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |  ****  |\n   | *    * |\n   |      * |\n   |      * |\n   |     *  |\n   |   **   |\n   |  *     |\n   | *      |\n   | ****** |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3c00,\n0x4200,\n0x0200,\n0x0200,\n0x0400,\n0x1800,\n0x2000,\n0x4000,\n0x7e00,\n0x0000,\n0x0000,\n\n/* Character 51 (0x33):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |  ***   |\n   | *   *  |\n   |     *  |\n   |    *   |\n   |  ***   |\n   |     *  |\n   |     *  |\n   | *   *  |\n   |  ***   |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3800,\n0x4400,\n0x0400,\n0x0800,\n0x3800,\n0x0400,\n0x0400,\n0x4400,\n0x3800,\n0x0000,\n0x0000,\n\n/* Character 52 (0x34):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |     *  |\n   |    **  |\n   |   * *  |\n   |  *  *  |\n   | *   *  |\n   | ****** |\n   |     *  |\n   |     *  |\n   |     *  |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0400,\n0x0c00,\n0x1400,\n0x2400,\n0x4400,\n0x7e00,\n0x0400,\n0x0400,\n0x0400,\n0x0000,\n0x0000,\n\n/* Character 53 (0x35):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   | *****  |\n   | *      |\n   | *      |\n   | ***    |\n   |    *   |\n   |     *  |\n   |     *  |\n   |     *  |\n   | ****   |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7c00,\n0x4000,\n0x4000,\n0x7000,\n0x0800,\n0x0400,\n0x0400,\n0x0400,\n0x7800,\n0x0000,\n0x0000,\n\n/* Character 54 (0x36):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |   **** |\n   |  *     |\n   | *      |\n   | * **   |\n   | **  *  |\n   | *    * |\n   | *    * |\n   |  *  *  |\n   |   **   |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1e00,\n0x2000,\n0x4000,\n0x5800,\n0x6400,\n0x4200,\n0x4200,\n0x2400,\n0x1800,\n0x0000,\n0x0000,\n\n/* Character 55 (0x37):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   | ****** |\n   |      * |\n   |     *  |\n   |    *   |\n   |    *   |\n   |   *    |\n   |   *    |\n   |  *     |\n   |  *     |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7e00,\n0x0200,\n0x0400,\n0x0800,\n0x0800,\n0x1000,\n0x1000,\n0x2000,\n0x2000,\n0x0000,\n0x0000,\n\n/* Character 56 (0x38):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |  ****  |\n   | *    * |\n   | *    * |\n   |  *  *  |\n   |  ****  |\n   | *    * |\n   | *    * |\n   | *    * |\n   |  ****  |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3c00,\n0x4200,\n0x4200,\n0x2400,\n0x3c00,\n0x4200,\n0x4200,\n0x4200,\n0x3c00,\n0x0000,\n0x0000,\n\n/* Character 57 (0x39):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |   **   |\n   |  *  *  |\n   | *    * |\n   | *    * |\n   |  *  ** |\n   |   ** * |\n   |      * |\n   |     *  |\n   | ****   |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1800,\n0x2400,\n0x4200,\n0x4200,\n0x2600,\n0x1a00,\n0x0200,\n0x0400,\n0x7800,\n0x0000,\n0x0000,\n\n/* Character 58 (0x3a):\n   width 4\n   +----+\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   | *  |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   | *  |\n   |    |\n   |    |\n   +----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x4000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 59 (0x3b):\n   width 4\n   +----+\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   | *  |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   | *  |\n   | *  |\n   |*   |\n   +----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x4000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x4000,\n0x4000,\n0x8000,\n\n/* Character 60 (0x3c):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   |        * |\n   |     ***  |\n   |   **     |\n   | **       |\n   |  ***     |\n   |     ***  |\n   |        * |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0080,\n0x0700,\n0x1800,\n0x6000,\n0x3800,\n0x0700,\n0x0080,\n0x0000,\n0x0000,\n\n/* Character 61 (0x3d):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   | ******** |\n   |          |\n   |          |\n   | ******** |\n   |          |\n   |          |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x7f80,\n0x0000,\n0x0000,\n0x7f80,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 62 (0x3e):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   | *        |\n   |  ***     |\n   |     **   |\n   |       ** |\n   |     ***  |\n   |  ***     |\n   | *        |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x4000,\n0x3800,\n0x0600,\n0x0180,\n0x0700,\n0x3800,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 63 (0x3f):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |**** |\n   |    *|\n   |    *|\n   |   * |\n   |  *  |\n   | *   |\n   | *   |\n   |     |\n   | *   |\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0xf000,\n0x0800,\n0x0800,\n0x1000,\n0x2000,\n0x4000,\n0x4000,\n0x0000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 64 (0x40):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   |    ****   |\n   |  **    *  |\n   | *  ***  * |\n   |*  *  *  * |\n   |* *  *   * |\n   |* * **  *  |\n   |* ** ***   |\n   | *         |\n   |  ****     |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0f00,\n0x3080,\n0x4e40,\n0x9240,\n0xa440,\n0xac80,\n0xb700,\n0x4000,\n0x3c00,\n0x0000,\n0x0000,\n\n/* Character 65 (0x41):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |    *    |\n   |   * *   |\n   |   * *   |\n   |  *   *  |\n   |  *   *  |\n   | *     * |\n   | ******* |\n   | *     * |\n   |*       *|\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0800,\n0x1400,\n0x1400,\n0x2200,\n0x2200,\n0x4100,\n0x7f00,\n0x4100,\n0x8080,\n0x0000,\n0x0000,\n\n/* Character 66 (0x42):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   | ****  |\n   | *   * |\n   | *   * |\n   | *  *  |\n   | ***   |\n   | *  *  |\n   | *   * |\n   | *   * |\n   | ****  |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7800,\n0x4400,\n0x4400,\n0x4800,\n0x7000,\n0x4800,\n0x4400,\n0x4400,\n0x7800,\n0x0000,\n0x0000,\n\n/* Character 67 (0x43):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |  *****  |\n   | *     * |\n   |*        |\n   |*        |\n   |*        |\n   |*        |\n   |*        |\n   | *     * |\n   |  *****  |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3e00,\n0x4100,\n0x8000,\n0x8000,\n0x8000,\n0x8000,\n0x8000,\n0x4100,\n0x3e00,\n0x0000,\n0x0000,\n\n/* Character 68 (0x44):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   | ******   |\n   | *     *  |\n   | *      * |\n   | *      * |\n   | *      * |\n   | *      * |\n   | *      * |\n   | *     *  |\n   | ******   |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7e00,\n0x4100,\n0x4080,\n0x4080,\n0x4080,\n0x4080,\n0x4080,\n0x4100,\n0x7e00,\n0x0000,\n0x0000,\n\n/* Character 69 (0x45):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   | ******|\n   | *     |\n   | *     |\n   | *     |\n   | ***** |\n   | *     |\n   | *     |\n   | *     |\n   | ******|\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7e00,\n0x4000,\n0x4000,\n0x4000,\n0x7c00,\n0x4000,\n0x4000,\n0x4000,\n0x7e00,\n0x0000,\n0x0000,\n\n/* Character 70 (0x46):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   | ***** |\n   | *     |\n   | *     |\n   | *     |\n   | ****  |\n   | *     |\n   | *     |\n   | *     |\n   | *     |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7c00,\n0x4000,\n0x4000,\n0x4000,\n0x7800,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 71 (0x47):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |   ***** |\n   |  *      |\n   | *       |\n   | *       |\n   | *       |\n   | *     * |\n   | *     * |\n   |  *    * |\n   |   ***** |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1f00,\n0x2000,\n0x4000,\n0x4000,\n0x4000,\n0x4100,\n0x4100,\n0x2100,\n0x1f00,\n0x0000,\n0x0000,\n\n/* Character 72 (0x48):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   | *     *  |\n   | *     *  |\n   | *     *  |\n   | *     *  |\n   | *******  |\n   | *     *  |\n   | *     *  |\n   | *     *  |\n   | *     *  |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x4100,\n0x4100,\n0x4100,\n0x4100,\n0x7f00,\n0x4100,\n0x4100,\n0x4100,\n0x4100,\n0x0000,\n0x0000,\n\n/* Character 73 (0x49):\n   width 4\n   +----+\n   |    |\n   |    |\n   |    |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   |    |\n   |    |\n   +----+ */\n0x0000,\n0x0000,\n0x0000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 74 (0x4a):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |***  |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0xe000,\n\n/* Character 75 (0x4b):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   | *    * |\n   | *   *  |\n   | *  *   |\n   | * *    |\n   | **     |\n   | * *    |\n   | *  *   |\n   | *   *  |\n   | *    * |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x4200,\n0x4400,\n0x4800,\n0x5000,\n0x6000,\n0x5000,\n0x4800,\n0x4400,\n0x4200,\n0x0000,\n0x0000,\n\n/* Character 76 (0x4c):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   | *     |\n   | *     |\n   | *     |\n   | *     |\n   | *     |\n   | *     |\n   | *     |\n   | *     |\n   | ******|\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x7e00,\n0x0000,\n0x0000,\n\n/* Character 77 (0x4d):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   | **     ** |\n   | **     ** |\n   | * *   * * |\n   | * *   * * |\n   | * *   * * |\n   | *  * *  * |\n   | *  * *  * |\n   | *   *   * |\n   | *       * |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x60c0,\n0x60c0,\n0x5140,\n0x5140,\n0x5140,\n0x4a40,\n0x4a40,\n0x4440,\n0x4040,\n0x0000,\n0x0000,\n\n/* Character 78 (0x4e):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   | **    *  |\n   | **    *  |\n   | * *   *  |\n   | * *   *  |\n   | *  *  *  |\n   | *   * *  |\n   | *   * *  |\n   | *    **  |\n   | *    **  |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x6100,\n0x6100,\n0x5100,\n0x5100,\n0x4900,\n0x4500,\n0x4500,\n0x4300,\n0x4300,\n0x0000,\n0x0000,\n\n/* Character 79 (0x4f):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   |  *****   |\n   | *     *  |\n   |*       * |\n   |*       * |\n   |*       * |\n   |*       * |\n   |*       * |\n   | *     *  |\n   |  *****   |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3e00,\n0x4100,\n0x8080,\n0x8080,\n0x8080,\n0x8080,\n0x8080,\n0x4100,\n0x3e00,\n0x0000,\n0x0000,\n\n/* Character 80 (0x50):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   | ***** |\n   | *    *|\n   | *    *|\n   | *    *|\n   | ***** |\n   | *     |\n   | *     |\n   | *     |\n   | *     |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7c00,\n0x4200,\n0x4200,\n0x4200,\n0x7c00,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 81 (0x51):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   |  *****   |\n   | *     *  |\n   |*       * |\n   |*       * |\n   |*       * |\n   |*       * |\n   |*       * |\n   | *     *  |\n   |  *****   |\n   |      **  |\n   |        **|\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3e00,\n0x4100,\n0x8080,\n0x8080,\n0x8080,\n0x8080,\n0x8080,\n0x4100,\n0x3e00,\n0x0300,\n0x00c0,\n\n/* Character 82 (0x52):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   | *****  |\n   | *    * |\n   | *    * |\n   | *   *  |\n   | ****   |\n   | *  *   |\n   | *   *  |\n   | *    * |\n   | *     *|\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7c00,\n0x4200,\n0x4200,\n0x4400,\n0x7800,\n0x4800,\n0x4400,\n0x4200,\n0x4100,\n0x0000,\n0x0000,\n\n/* Character 83 (0x53):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   | ****  |\n   |*      |\n   |*      |\n   | *     |\n   |  **   |\n   |    *  |\n   |     * |\n   |     * |\n   |*****  |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7800,\n0x8000,\n0x8000,\n0x4000,\n0x3000,\n0x0800,\n0x0400,\n0x0400,\n0xf800,\n0x0000,\n0x0000,\n\n/* Character 84 (0x54):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |******* |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0xfe00,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x0000,\n0x0000,\n\n/* Character 85 (0x55):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   | *     * |\n   | *     * |\n   | *     * |\n   | *     * |\n   | *     * |\n   | *     * |\n   | *     * |\n   | *     * |\n   |  *****  |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x4100,\n0x4100,\n0x4100,\n0x4100,\n0x4100,\n0x4100,\n0x4100,\n0x4100,\n0x3e00,\n0x0000,\n0x0000,\n\n/* Character 86 (0x56):\n   width 9\n   +---------+\n   |         |\n   |         |\n   |         |\n   |*      * |\n   | *    *  |\n   | *    *  |\n   | *    *  |\n   |  *  *   |\n   |  *  *   |\n   |  *  *   |\n   |   **    |\n   |   **    |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x0000,\n0x0000,\n0x8100,\n0x4200,\n0x4200,\n0x4200,\n0x2400,\n0x2400,\n0x2400,\n0x1800,\n0x1800,\n0x0000,\n0x0000,\n\n/* Character 87 (0x57):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   |*    *    *|\n   |*    *    *|\n   | *  * *  * |\n   | *  * *  * |\n   | * ** *  * |\n   | * *   * * |\n   | * *   * * |\n   |  **   **  |\n   |  *     *  |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x8420,\n0x8420,\n0x4a40,\n0x4a40,\n0x5a40,\n0x5140,\n0x5140,\n0x3180,\n0x2080,\n0x0000,\n0x0000,\n\n/* Character 88 (0x58):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |*      *|\n   | *    * |\n   |  *  *  |\n   |  *  *  |\n   |   **   |\n   |  *  *  |\n   |  *  *  |\n   | *    * |\n   |*      *|\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x8100,\n0x4200,\n0x2400,\n0x2400,\n0x1800,\n0x2400,\n0x2400,\n0x4200,\n0x8100,\n0x0000,\n0x0000,\n\n/* Character 89 (0x59):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |*     * |\n   | *   *  |\n   | *   *  |\n   |  * *   |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |   *    |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x8200,\n0x4400,\n0x4400,\n0x2800,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x0000,\n0x0000,\n\n/* Character 90 (0x5a):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |******* |\n   |      * |\n   |     *  |\n   |    *   |\n   |   *    |\n   |  *     |\n   | *      |\n   |*       |\n   |******* |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0xfe00,\n0x0200,\n0x0400,\n0x0800,\n0x1000,\n0x2000,\n0x4000,\n0x8000,\n0xfe00,\n0x0000,\n0x0000,\n\n/* Character 91 (0x5b):\n   width 4\n   +----+\n   |    |\n   |    |\n   | ***|\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | ***|\n   +----+ */\n0x0000,\n0x0000,\n0x7000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x7000,\n\n/* Character 92 (0x5c):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   | *     |\n   | *     |\n   | *     |\n   |  *    |\n   |  *    |\n   |  *    |\n   |   *   |\n   |   *   |\n   |   *   |\n   |    *  |\n   |    *  |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x4000,\n0x4000,\n0x4000,\n0x2000,\n0x2000,\n0x2000,\n0x1000,\n0x1000,\n0x1000,\n0x0800,\n0x0800,\n\n/* Character 93 (0x5d):\n   width 4\n   +----+\n   |    |\n   |    |\n   |*** |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |*** |\n   +----+ */\n0x0000,\n0x0000,\n0xe000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0xe000,\n\n/* Character 94 (0x5e):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |   *    |\n   |   *    |\n   |  * *   |\n   |  * *   |\n   | *   *  |\n   | *   *  |\n   |*     * |\n   |        |\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x1000,\n0x1000,\n0x2800,\n0x2800,\n0x4400,\n0x4400,\n0x8200,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 95 (0x5f):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   | ***** |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x7c00,\n0x0000,\n\n/* Character 96 (0x60):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |   **   |\n   |    **  |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x1800,\n0x0c00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 97 (0x61):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |   **  |\n   |  *  * |\n   |     * |\n   |  **** |\n   | *   * |\n   | *   * |\n   |  *****|\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x1800,\n0x2400,\n0x0400,\n0x3c00,\n0x4400,\n0x4400,\n0x3e00,\n0x0000,\n0x0000,\n\n/* Character 98 (0x62):\n   width 8\n   +--------+\n   |        |\n   |        |\n   | *      |\n   | *      |\n   | *      |\n   | * ***  |\n   | **   * |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *****  |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x4000,\n0x4000,\n0x4000,\n0x5c00,\n0x6200,\n0x4200,\n0x4200,\n0x4200,\n0x4200,\n0x7c00,\n0x0000,\n0x0000,\n\n/* Character 99 (0x63):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |  **** |\n   | *     |\n   | *     |\n   | *     |\n   | *     |\n   | *     |\n   |  **** |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3c00,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x3c00,\n0x0000,\n0x0000,\n\n/* Character 100 (0x64):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |      * |\n   |      * |\n   |      * |\n   |  ***** |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *   ** |\n   |  *** * |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0200,\n0x0200,\n0x0200,\n0x3e00,\n0x4200,\n0x4200,\n0x4200,\n0x4200,\n0x4600,\n0x3a00,\n0x0000,\n0x0000,\n\n/* Character 101 (0x65):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |  ***  |\n   | *   * |\n   | *   * |\n   | ***** |\n   | *     |\n   | *     |\n   |  **** |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3800,\n0x4400,\n0x4400,\n0x7c00,\n0x4000,\n0x4000,\n0x3c00,\n0x0000,\n0x0000,\n\n/* Character 102 (0x66):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |   **|\n   |  *  |\n   |  *  |\n   | ****|\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x1c00,\n0x2000,\n0x2000,\n0x7800,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x0000,\n0x0000,\n\n/* Character 103 (0x67):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |  ***** |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *   ** |\n   |  *** * |\n   |      * |\n   |     *  |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3e00,\n0x4200,\n0x4200,\n0x4200,\n0x4200,\n0x4600,\n0x3a00,\n0x0200,\n0x0400,\n\n/* Character 104 (0x68):\n   width 8\n   +--------+\n   |        |\n   |        |\n   | *      |\n   | *      |\n   | *      |\n   | * ***  |\n   | **   * |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *    * |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x4000,\n0x4000,\n0x4000,\n0x5c00,\n0x6200,\n0x4200,\n0x4200,\n0x4200,\n0x4200,\n0x4200,\n0x0000,\n0x0000,\n\n/* Character 105 (0x69):\n   width 4\n   +----+\n   |    |\n   |    |\n   |    |\n   | *  |\n   |    |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   |    |\n   |    |\n   +----+ */\n0x0000,\n0x0000,\n0x0000,\n0x4000,\n0x0000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 106 (0x6a):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |   * |\n   |     |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x1000,\n0x0000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n\n/* Character 107 (0x6b):\n   width 8\n   +--------+\n   |        |\n   |        |\n   | *      |\n   | *      |\n   | *      |\n   | *   *  |\n   | *  *   |\n   | * *    |\n   | **     |\n   | * *    |\n   | *  *   |\n   | *   *  |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x4000,\n0x4000,\n0x4000,\n0x4400,\n0x4800,\n0x5000,\n0x6000,\n0x5000,\n0x4800,\n0x4400,\n0x0000,\n0x0000,\n\n/* Character 108 (0x6c):\n   width 4\n   +----+\n   |    |\n   |    |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   |    |\n   |    |\n   +----+ */\n0x0000,\n0x0000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 109 (0x6d):\n   width 12\n   +------------+\n   |            |\n   |            |\n   |            |\n   |            |\n   |            |\n   | * **  **   |\n   | **  **  *  |\n   | *   *   *  |\n   | *   *   *  |\n   | *   *   *  |\n   | *   *   *  |\n   | *   *   *  |\n   |            |\n   |            |\n   +------------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x5980,\n0x6640,\n0x4440,\n0x4440,\n0x4440,\n0x4440,\n0x4440,\n0x0000,\n0x0000,\n\n/* Character 110 (0x6e):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   | * ***  |\n   | **   * |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *    * |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x5c00,\n0x6200,\n0x4200,\n0x4200,\n0x4200,\n0x4200,\n0x4200,\n0x0000,\n0x0000,\n\n/* Character 111 (0x6f):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |  ****  |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *    * |\n   |  ****  |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3c00,\n0x4200,\n0x4200,\n0x4200,\n0x4200,\n0x4200,\n0x3c00,\n0x0000,\n0x0000,\n\n/* Character 112 (0x70):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   | * ***  |\n   | **   * |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *****  |\n   | *      |\n   | *      |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x5c00,\n0x6200,\n0x4200,\n0x4200,\n0x4200,\n0x4200,\n0x7c00,\n0x4000,\n0x4000,\n\n/* Character 113 (0x71):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |  ***** |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *   ** |\n   |  *** * |\n   |      * |\n   |      * |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3e00,\n0x4200,\n0x4200,\n0x4200,\n0x4200,\n0x4600,\n0x3a00,\n0x0200,\n0x0200,\n\n/* Character 114 (0x72):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   | * **|\n   | **  |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x5800,\n0x6000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 115 (0x73):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |  ***  |\n   | *     |\n   | *     |\n   |  ***  |\n   |     * |\n   |     * |\n   | ****  |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x3800,\n0x4000,\n0x4000,\n0x3800,\n0x0400,\n0x0400,\n0x7800,\n0x0000,\n0x0000,\n\n/* Character 116 (0x74):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |     |\n   | *   |\n   |**** |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   |  ** |\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x4000,\n0xf000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x3000,\n0x0000,\n0x0000,\n\n/* Character 117 (0x75):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *   ** |\n   |  *** * |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x4200,\n0x4200,\n0x4200,\n0x4200,\n0x4200,\n0x4600,\n0x3a00,\n0x0000,\n0x0000,\n\n/* Character 118 (0x76):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |*     *|\n   | *   * |\n   | *   * |\n   | *   * |\n   |  * *  |\n   |  * *  |\n   |   *   |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x8200,\n0x4400,\n0x4400,\n0x4400,\n0x2800,\n0x2800,\n0x1000,\n0x0000,\n0x0000,\n\n/* Character 119 (0x77):\n   width 10\n   +----------+\n   |          |\n   |          |\n   |          |\n   |          |\n   |          |\n   |*   *   * |\n   |*   *   * |\n   | * * * *  |\n   | * * * *  |\n   | * * * *  |\n   |  *   *   |\n   |  *   *   |\n   |          |\n   |          |\n   +----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x8880,\n0x8880,\n0x5500,\n0x5500,\n0x5500,\n0x2200,\n0x2200,\n0x0000,\n0x0000,\n\n/* Character 120 (0x78):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   | *    * |\n   |  *  *  |\n   |   **   |\n   |   **   |\n   |   **   |\n   |  *  *  |\n   | *    * |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x4200,\n0x2400,\n0x1800,\n0x1800,\n0x1800,\n0x2400,\n0x4200,\n0x0000,\n0x0000,\n\n/* Character 121 (0x79):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   |*     *|\n   | *   * |\n   | *   * |\n   | *   * |\n   |  * *  |\n   |  * *  |\n   |   *   |\n   |   *   |\n   |   *   |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x8200,\n0x4400,\n0x4400,\n0x4400,\n0x2800,\n0x2800,\n0x1000,\n0x1000,\n0x1000,\n\n/* Character 122 (0x7a):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   | ******|\n   |     * |\n   |    *  |\n   |   *   |\n   |  *    |\n   | *     |\n   | ******|\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x7e00,\n0x0400,\n0x0800,\n0x1000,\n0x2000,\n0x4000,\n0x7e00,\n0x0000,\n0x0000,\n\n/* Character 123 (0x7b):\n   width 4\n   +----+\n   |    |\n   |    |\n   |  * |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   |*   |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   |  * |\n   +----+ */\n0x0000,\n0x0000,\n0x2000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x8000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x2000,\n\n/* Character 124 (0x7c):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   +-----+ */\n0x0000,\n0x0000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n\n/* Character 125 (0x7d):\n   width 4\n   +----+\n   |    |\n   |    |\n   | *  |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |   *|\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   | *  |\n   +----+ */\n0x0000,\n0x0000,\n0x4000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x1000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x4000,\n\n/* Character 126 (0x7e):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   | ***  * |\n   | *  *** |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x7200,\n0x4e00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 127 (0x7f):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |        |\n   | * ** * |\n   |  *  *  |\n   | *    * |\n   | *    * |\n   |  *  *  |\n   | * ** * |\n   |        |\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x5a00,\n0x2400,\n0x4200,\n0x4200,\n0x2400,\n0x5a00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n};\n\n/* Character->glyph mapping. */\nstatic const unsigned short _lucidasans9_offset[] = {\n  0,\t/* (0x20) */\n  14,\t/* (0x21) */\n  28,\t/* (0x22) */\n  42,\t/* (0x23) */\n  56,\t/* (0x24) */\n  70,\t/* (0x25) */\n  84,\t/* (0x26) */\n  98,\t/* (0x27) */\n  112,\t/* (0x28) */\n  126,\t/* (0x29) */\n  140,\t/* (0x2a) */\n  154,\t/* (0x2b) */\n  168,\t/* (0x2c) */\n  182,\t/* (0x2d) */\n  196,\t/* (0x2e) */\n  210,\t/* (0x2f) */\n  224,\t/* (0x30) */\n  238,\t/* (0x31) */\n  252,\t/* (0x32) */\n  266,\t/* (0x33) */\n  280,\t/* (0x34) */\n  294,\t/* (0x35) */\n  308,\t/* (0x36) */\n  322,\t/* (0x37) */\n  336,\t/* (0x38) */\n  350,\t/* (0x39) */\n  364,\t/* (0x3a) */\n  378,\t/* (0x3b) */\n  392,\t/* (0x3c) */\n  406,\t/* (0x3d) */\n  420,\t/* (0x3e) */\n  434,\t/* (0x3f) */\n  448,\t/* (0x40) */\n  462,\t/* (0x41) */\n  476,\t/* (0x42) */\n  490,\t/* (0x43) */\n  504,\t/* (0x44) */\n  518,\t/* (0x45) */\n  532,\t/* (0x46) */\n  546,\t/* (0x47) */\n  560,\t/* (0x48) */\n  574,\t/* (0x49) */\n  588,\t/* (0x4a) */\n  602,\t/* (0x4b) */\n  616,\t/* (0x4c) */\n  630,\t/* (0x4d) */\n  644,\t/* (0x4e) */\n  658,\t/* (0x4f) */\n  672,\t/* (0x50) */\n  686,\t/* (0x51) */\n  700,\t/* (0x52) */\n  714,\t/* (0x53) */\n  728,\t/* (0x54) */\n  742,\t/* (0x55) */\n  756,\t/* (0x56) */\n  770,\t/* (0x57) */\n  784,\t/* (0x58) */\n  798,\t/* (0x59) */\n  812,\t/* (0x5a) */\n  826,\t/* (0x5b) */\n  840,\t/* (0x5c) */\n  854,\t/* (0x5d) */\n  868,\t/* (0x5e) */\n  882,\t/* (0x5f) */\n  896,\t/* (0x60) */\n  910,\t/* (0x61) */\n  924,\t/* (0x62) */\n  938,\t/* (0x63) */\n  952,\t/* (0x64) */\n  966,\t/* (0x65) */\n  980,\t/* (0x66) */\n  994,\t/* (0x67) */\n  1008,\t/* (0x68) */\n  1022,\t/* (0x69) */\n  1036,\t/* (0x6a) */\n  1050,\t/* (0x6b) */\n  1064,\t/* (0x6c) */\n  1078,\t/* (0x6d) */\n  1092,\t/* (0x6e) */\n  1106,\t/* (0x6f) */\n  1120,\t/* (0x70) */\n  1134,\t/* (0x71) */\n  1148,\t/* (0x72) */\n  1162,\t/* (0x73) */\n  1176,\t/* (0x74) */\n  1190,\t/* (0x75) */\n  1204,\t/* (0x76) */\n  1218,\t/* (0x77) */\n  1232,\t/* (0x78) */\n  1246,\t/* (0x79) */\n  1260,\t/* (0x7a) */\n  1274,\t/* (0x7b) */\n  1288,\t/* (0x7c) */\n  1302,\t/* (0x7d) */\n  1316,\t/* (0x7e) */\n  1330,\t/* (0x7f) */\n  1330,\t/* (0x80) */\n  1330,\t/* (0x81) */\n  1330,\t/* (0x82) */\n  1330,\t/* (0x83) */\n  1330,\t/* (0x84) */\n  1330,\t/* (0x85) */\n  1330,\t/* (0x86) */\n  1330,\t/* (0x87) */\n  1330,\t/* (0x88) */\n  1330,\t/* (0x89) */\n  1330,\t/* (0x8a) */\n  1330,\t/* (0x8b) */\n  1330,\t/* (0x8c) */\n  1330,\t/* (0x8d) */\n  1330,\t/* (0x8e) */\n  1330,\t/* (0x8f) */\n  1330,\t/* (0x90) */\n  1330,\t/* (0x91) */\n  1330,\t/* (0x92) */\n  1330,\t/* (0x93) */\n  1330,\t/* (0x94) */\n  1330,\t/* (0x95) */\n  1330,\t/* (0x96) */\n  1330,\t/* (0x97) */\n  1330,\t/* (0x98) */\n  1330,\t/* (0x99) */\n  1330,\t/* (0x9a) */\n  1330,\t/* (0x9b) */\n  1330,\t/* (0x9c) */\n  1330,\t/* (0x9d) */\n  1330,\t/* (0x9e) */\n  1330,\t/* (0x9f) */\n  1330,\t/* (0xa0) */\n  1330,\t/* (0xa1) */\n  1330,\t/* (0xa2) */\n  1330,\t/* (0xa3) */\n  1330,\t/* (0xa4) */\n};\n\n/* Character width data. */\nstatic const unsigned char _lucidasans9_width[] = {\n  4,\t/* (0x20) */\n  4,\t/* (0x21) */\n  5,\t/* (0x22) */\n  8,\t/* (0x23) */\n  8,\t/* (0x24) */\n  9,\t/* (0x25) */\n  9,\t/* (0x26) */\n  3,\t/* (0x27) */\n  4,\t/* (0x28) */\n  4,\t/* (0x29) */\n  6,\t/* (0x2a) */\n  10,\t/* (0x2b) */\n  4,\t/* (0x2c) */\n  8,\t/* (0x2d) */\n  4,\t/* (0x2e) */\n  7,\t/* (0x2f) */\n  8,\t/* (0x30) */\n  8,\t/* (0x31) */\n  8,\t/* (0x32) */\n  8,\t/* (0x33) */\n  8,\t/* (0x34) */\n  8,\t/* (0x35) */\n  8,\t/* (0x36) */\n  8,\t/* (0x37) */\n  8,\t/* (0x38) */\n  8,\t/* (0x39) */\n  4,\t/* (0x3a) */\n  4,\t/* (0x3b) */\n  10,\t/* (0x3c) */\n  10,\t/* (0x3d) */\n  10,\t/* (0x3e) */\n  5,\t/* (0x3f) */\n  11,\t/* (0x40) */\n  9,\t/* (0x41) */\n  7,\t/* (0x42) */\n  9,\t/* (0x43) */\n  10,\t/* (0x44) */\n  7,\t/* (0x45) */\n  7,\t/* (0x46) */\n  9,\t/* (0x47) */\n  10,\t/* (0x48) */\n  4,\t/* (0x49) */\n  5,\t/* (0x4a) */\n  8,\t/* (0x4b) */\n  7,\t/* (0x4c) */\n  11,\t/* (0x4d) */\n  10,\t/* (0x4e) */\n  10,\t/* (0x4f) */\n  7,\t/* (0x50) */\n  10,\t/* (0x51) */\n  8,\t/* (0x52) */\n  7,\t/* (0x53) */\n  8,\t/* (0x54) */\n  9,\t/* (0x55) */\n  9,\t/* (0x56) */\n  11,\t/* (0x57) */\n  8,\t/* (0x58) */\n  8,\t/* (0x59) */\n  8,\t/* (0x5a) */\n  4,\t/* (0x5b) */\n  7,\t/* (0x5c) */\n  4,\t/* (0x5d) */\n  8,\t/* (0x5e) */\n  7,\t/* (0x5f) */\n  8,\t/* (0x60) */\n  7,\t/* (0x61) */\n  8,\t/* (0x62) */\n  7,\t/* (0x63) */\n  8,\t/* (0x64) */\n  7,\t/* (0x65) */\n  5,\t/* (0x66) */\n  8,\t/* (0x67) */\n  8,\t/* (0x68) */\n  4,\t/* (0x69) */\n  5,\t/* (0x6a) */\n  8,\t/* (0x6b) */\n  4,\t/* (0x6c) */\n  12,\t/* (0x6d) */\n  8,\t/* (0x6e) */\n  8,\t/* (0x6f) */\n  8,\t/* (0x70) */\n  8,\t/* (0x71) */\n  5,\t/* (0x72) */\n  7,\t/* (0x73) */\n  5,\t/* (0x74) */\n  8,\t/* (0x75) */\n  7,\t/* (0x76) */\n  10,\t/* (0x77) */\n  8,\t/* (0x78) */\n  7,\t/* (0x79) */\n  7,\t/* (0x7a) */\n  4,\t/* (0x7b) */\n  5,\t/* (0x7c) */\n  4,\t/* (0x7d) */\n  8,\t/* (0x7e) */\n  8,\t/* (0x7f) */\n  8,\t/* (0x80) */\n  8,\t/* (0x81) */\n  8,\t/* (0x82) */\n  8,\t/* (0x83) */\n  8,\t/* (0x84) */\n  8,\t/* (0x85) */\n  8,\t/* (0x86) */\n  8,\t/* (0x87) */\n  8,\t/* (0x88) */\n  8,\t/* (0x89) */\n  8,\t/* (0x8a) */\n  8,\t/* (0x8b) */\n  8,\t/* (0x8c) */\n  8,\t/* (0x8d) */\n  8,\t/* (0x8e) */\n  8,\t/* (0x8f) */\n  8,\t/* (0x90) */\n  8,\t/* (0x91) */\n  8,\t/* (0x92) */\n  8,\t/* (0x93) */\n  8,\t/* (0x94) */\n  8,\t/* (0x95) */\n  8,\t/* (0x96) */\n  8,\t/* (0x97) */\n  8,\t/* (0x98) */\n  8,\t/* (0x99) */\n  8,\t/* (0x9a) */\n  8,\t/* (0x9b) */\n  8,\t/* (0x9c) */\n  8,\t/* (0x9d) */\n  8,\t/* (0x9e) */\n  8,\t/* (0x9f) */\n  8,\t/* (0xa0) */\n  8,\t/* (0xa1) */\n  8,\t/* (0xa2) */\n  8,\t/* (0xa3) */\n  8,\t/* (0xa4) */\n};\n\n/* Exported structure definition. */\nconst struct gpanel_font_t font_lucidasans9 = {\n  \"lucidasans9\",\n  12,\n  14,\n  12,\n  32,\n  133,\n  _lucidasans9_bits,\n  _lucidasans9_offset,\n  _lucidasans9_width,\n  164,\n  sizeof(_lucidasans9_bits) / sizeof(_lucidasans9_bits[0]),\n};\n"
  },
  {
    "path": "share/examples/gpanel/fonts/verdana7.c",
    "content": "/* Generated by convbdf on Thu Oct  8 21:26:35 2015. */\n#include <sys/gpanel.h>\n\n/* Font information:\n   name: verdana7\n   facename: -FreeType-Verdana-Medium-R-Normal--10-70-100-100-P-52-ISO10646-1\n   w x h: 11x10\n   size: 133\n   ascent: 8\n   descent: 2\n   first char: 32 (0x20)\n   last char: 164 (0xa4)\n   default char: 32 (0x20)\n   proportional: yes\n   Typeface and data  1996 Microsoft Corporation. All Rights Reserved\n*/\n\n/* Font character bitmap data. */\nstatic const unsigned short _verdana7_bits[] = {\n\n/* Character 32 (0x20):\n   width 4\n   +----+\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   +----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 33 (0x21):\n   width 4\n   +----+\n   |    |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |    |\n   |  * |\n   |    |\n   |    |\n   +----+ */\n0x0000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x0000,\n0x2000,\n0x0000,\n0x0000,\n\n/* Character 34 (0x22):\n   width 5\n   +-----+\n   | * * |\n   | * * |\n   | * * |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   +-----+ */\n0x5000,\n0x5000,\n0x5000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 35 (0x23):\n   width 8\n   +--------+\n   |        |\n   |   * *  |\n   |   * *  |\n   |  ***** |\n   |  *  *  |\n   | *****  |\n   |  * *   |\n   |  * *   |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x1400,\n0x1400,\n0x3e00,\n0x2400,\n0x7c00,\n0x2800,\n0x2800,\n0x0000,\n0x0000,\n\n/* Character 36 (0x24):\n   width 7\n   +-------+\n   |   *   |\n   |   *   |\n   |  **** |\n   | * *   |\n   |  **   |\n   |   **  |\n   |   * * |\n   | ****  |\n   |   *   |\n   |   *   |\n   +-------+ */\n0x1000,\n0x1000,\n0x3c00,\n0x5000,\n0x3000,\n0x1800,\n0x1400,\n0x7800,\n0x1000,\n0x1000,\n\n/* Character 37 (0x25):\n   width 11\n   +-----------+\n   |           |\n   |  **   *   |\n   | *  * *    |\n   | *  * *    |\n   |  ** * **  |\n   |    * *  * |\n   |    * *  * |\n   |   *   **  |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x3100,\n0x4a00,\n0x4a00,\n0x3580,\n0x0a40,\n0x0a40,\n0x1180,\n0x0000,\n0x0000,\n\n/* Character 38 (0x26):\n   width 7\n   +-------+\n   |       |\n   |  **   |\n   | *  *  |\n   | *  *  |\n   |  **  *|\n   | *  * *|\n   | *   * |\n   |  *** *|\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x3000,\n0x4800,\n0x4800,\n0x3200,\n0x4a00,\n0x4400,\n0x3a00,\n0x0000,\n0x0000,\n\n/* Character 39 (0x27):\n   width 3\n   +---+\n   | * |\n   | * |\n   | * |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   |   |\n   +---+ */\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 40 (0x28):\n   width 5\n   +-----+\n   |   * |\n   |  *  |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   |  *  |\n   |   * |\n   +-----+ */\n0x1000,\n0x2000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x2000,\n0x1000,\n\n/* Character 41 (0x29):\n   width 5\n   +-----+\n   | *   |\n   |  *  |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |  *  |\n   | *   |\n   +-----+ */\n0x4000,\n0x2000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x2000,\n0x4000,\n\n/* Character 42 (0x2a):\n   width 7\n   +-------+\n   |   *   |\n   | * * * |\n   |  ***  |\n   | * * * |\n   |   *   |\n   |       |\n   |       |\n   |       |\n   |       |\n   |       |\n   +-------+ */\n0x1000,\n0x5400,\n0x3800,\n0x5400,\n0x1000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 43 (0x2b):\n   width 8\n   +--------+\n   |        |\n   |    *   |\n   |    *   |\n   |    *   |\n   | *******|\n   |    *   |\n   |    *   |\n   |    *   |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0800,\n0x0800,\n0x0800,\n0x7f00,\n0x0800,\n0x0800,\n0x0800,\n0x0000,\n0x0000,\n\n/* Character 44 (0x2c):\n   width 4\n   +----+\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |  * |\n   |  * |\n   | *  |\n   |    |\n   +----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x2000,\n0x2000,\n0x4000,\n0x0000,\n\n/* Character 45 (0x2d):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |     |\n   | *** |\n   |     |\n   |     |\n   |     |\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x7000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 46 (0x2e):\n   width 4\n   +----+\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   |    |\n   | *  |\n   | *  |\n   |    |\n   |    |\n   +----+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 47 (0x2f):\n   width 5\n   +-----+\n   |   * |\n   |   * |\n   |  *  |\n   |  *  |\n   | *   |\n   | *   |\n   | *   |\n   |*    |\n   |*    |\n   |     |\n   +-----+ */\n0x1000,\n0x1000,\n0x2000,\n0x2000,\n0x4000,\n0x4000,\n0x4000,\n0x8000,\n0x8000,\n0x0000,\n\n/* Character 48 (0x30):\n   width 7\n   +-------+\n   |       |\n   |  ***  |\n   | *   * |\n   | *   * |\n   | *   * |\n   | *   * |\n   | *   * |\n   |  ***  |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x3800,\n0x4400,\n0x4400,\n0x4400,\n0x4400,\n0x4400,\n0x3800,\n0x0000,\n0x0000,\n\n/* Character 49 (0x31):\n   width 7\n   +-------+\n   |       |\n   |   *   |\n   | ***   |\n   |   *   |\n   |   *   |\n   |   *   |\n   |   *   |\n   | ***** |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x1000,\n0x7000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x7c00,\n0x0000,\n0x0000,\n\n/* Character 50 (0x32):\n   width 7\n   +-------+\n   |       |\n   |  ***  |\n   | *   * |\n   |     * |\n   |    *  |\n   |   *   |\n   |  *    |\n   | ***** |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x3800,\n0x4400,\n0x0400,\n0x0800,\n0x1000,\n0x2000,\n0x7c00,\n0x0000,\n0x0000,\n\n/* Character 51 (0x33):\n   width 7\n   +-------+\n   |       |\n   |  ***  |\n   | *   * |\n   |     * |\n   |   **  |\n   |     * |\n   | *   * |\n   |  ***  |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x3800,\n0x4400,\n0x0400,\n0x1800,\n0x0400,\n0x4400,\n0x3800,\n0x0000,\n0x0000,\n\n/* Character 52 (0x34):\n   width 7\n   +-------+\n   |       |\n   |    *  |\n   |   **  |\n   |  * *  |\n   | *  *  |\n   | ***** |\n   |    *  |\n   |    *  |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0800,\n0x1800,\n0x2800,\n0x4800,\n0x7c00,\n0x0800,\n0x0800,\n0x0000,\n0x0000,\n\n/* Character 53 (0x35):\n   width 7\n   +-------+\n   |       |\n   | ***** |\n   | *     |\n   | ****  |\n   |     * |\n   |     * |\n   | *   * |\n   |  ***  |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x7c00,\n0x4000,\n0x7800,\n0x0400,\n0x0400,\n0x4400,\n0x3800,\n0x0000,\n0x0000,\n\n/* Character 54 (0x36):\n   width 7\n   +-------+\n   |       |\n   |   **  |\n   |  *    |\n   | *     |\n   | ****  |\n   | *   * |\n   | *   * |\n   |  ***  |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x1800,\n0x2000,\n0x4000,\n0x7800,\n0x4400,\n0x4400,\n0x3800,\n0x0000,\n0x0000,\n\n/* Character 55 (0x37):\n   width 7\n   +-------+\n   |       |\n   | ***** |\n   |     * |\n   |    *  |\n   |    *  |\n   |   *   |\n   |   *   |\n   |  *    |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x7c00,\n0x0400,\n0x0800,\n0x0800,\n0x1000,\n0x1000,\n0x2000,\n0x0000,\n0x0000,\n\n/* Character 56 (0x38):\n   width 7\n   +-------+\n   |       |\n   |  ***  |\n   | *   * |\n   | *   * |\n   |  ***  |\n   | *   * |\n   | *   * |\n   |  ***  |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x3800,\n0x4400,\n0x4400,\n0x3800,\n0x4400,\n0x4400,\n0x3800,\n0x0000,\n0x0000,\n\n/* Character 57 (0x39):\n   width 7\n   +-------+\n   |       |\n   |  ***  |\n   | *   * |\n   | *   * |\n   |  **** |\n   |     * |\n   |    *  |\n   |  **   |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x3800,\n0x4400,\n0x4400,\n0x3c00,\n0x0400,\n0x0800,\n0x3000,\n0x0000,\n0x0000,\n\n/* Character 58 (0x3a):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |  *  |\n   |  *  |\n   |     |\n   |  *  |\n   |  *  |\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x2000,\n0x2000,\n0x0000,\n0x2000,\n0x2000,\n0x0000,\n0x0000,\n\n/* Character 59 (0x3b):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |  *  |\n   |  *  |\n   |     |\n   |  *  |\n   |  *  |\n   | *   |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x2000,\n0x2000,\n0x0000,\n0x2000,\n0x2000,\n0x4000,\n0x0000,\n\n/* Character 60 (0x3c):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |     ** |\n   |   **   |\n   | **     |\n   |   **   |\n   |     ** |\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0600,\n0x1800,\n0x6000,\n0x1800,\n0x0600,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 61 (0x3d):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   | ****** |\n   |        |\n   | ****** |\n   |        |\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7e00,\n0x0000,\n0x7e00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 62 (0x3e):\n   width 8\n   +--------+\n   |        |\n   |        |\n   | **     |\n   |   **   |\n   |     ** |\n   |   **   |\n   | **     |\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x6000,\n0x1800,\n0x0600,\n0x1800,\n0x6000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 63 (0x3f):\n   width 6\n   +------+\n   |      |\n   | ***  |\n   |    * |\n   |    * |\n   |   *  |\n   |  *   |\n   |      |\n   |  *   |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7000,\n0x0800,\n0x0800,\n0x1000,\n0x2000,\n0x0000,\n0x2000,\n0x0000,\n0x0000,\n\n/* Character 64 (0x40):\n   width 10\n   +----------+\n   |          |\n   |   *****  |\n   |  *     * |\n   | *  *** * |\n   | * *  * * |\n   | * *  * * |\n   | * *  * * |\n   | *  ** *  |\n   |  *       |\n   |   ****   |\n   +----------+ */\n0x0000,\n0x1f00,\n0x2080,\n0x4e80,\n0x5280,\n0x5280,\n0x5280,\n0x4d00,\n0x2000,\n0x1e00,\n\n/* Character 65 (0x41):\n   width 7\n   +-------+\n   |       |\n   |   *   |\n   |  * *  |\n   |  * *  |\n   | *   * |\n   | ***** |\n   | *   * |\n   |*     *|\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x1000,\n0x2800,\n0x2800,\n0x4400,\n0x7c00,\n0x4400,\n0x8200,\n0x0000,\n0x0000,\n\n/* Character 66 (0x42):\n   width 7\n   +-------+\n   |       |\n   | ***   |\n   | *  *  |\n   | *  *  |\n   | ****  |\n   | *   * |\n   | *   * |\n   | ****  |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x7000,\n0x4800,\n0x4800,\n0x7800,\n0x4400,\n0x4400,\n0x7800,\n0x0000,\n0x0000,\n\n/* Character 67 (0x43):\n   width 8\n   +--------+\n   |        |\n   |   ***  |\n   |  *   * |\n   | *      |\n   | *      |\n   | *      |\n   |  *   * |\n   |   ***  |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x1c00,\n0x2200,\n0x4000,\n0x4000,\n0x4000,\n0x2200,\n0x1c00,\n0x0000,\n0x0000,\n\n/* Character 68 (0x44):\n   width 8\n   +--------+\n   |        |\n   | ****   |\n   | *   *  |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *   *  |\n   | ****   |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x7800,\n0x4400,\n0x4200,\n0x4200,\n0x4200,\n0x4400,\n0x7800,\n0x0000,\n0x0000,\n\n/* Character 69 (0x45):\n   width 6\n   +------+\n   |      |\n   | **** |\n   | *    |\n   | *    |\n   | **** |\n   | *    |\n   | *    |\n   | **** |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7800,\n0x4000,\n0x4000,\n0x7800,\n0x4000,\n0x4000,\n0x7800,\n0x0000,\n0x0000,\n\n/* Character 70 (0x46):\n   width 6\n   +------+\n   |      |\n   | *****|\n   | *    |\n   | *    |\n   | **** |\n   | *    |\n   | *    |\n   | *    |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x7c00,\n0x4000,\n0x4000,\n0x7800,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 71 (0x47):\n   width 8\n   +--------+\n   |        |\n   |   ***  |\n   | **   * |\n   | *      |\n   | *  *** |\n   | *    * |\n   |  *   * |\n   |   **** |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x1c00,\n0x6200,\n0x4000,\n0x4e00,\n0x4200,\n0x2200,\n0x1e00,\n0x0000,\n0x0000,\n\n/* Character 72 (0x48):\n   width 8\n   +--------+\n   |        |\n   | *    * |\n   | *    * |\n   | *    * |\n   | ****** |\n   | *    * |\n   | *    * |\n   | *    * |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x4200,\n0x4200,\n0x4200,\n0x7e00,\n0x4200,\n0x4200,\n0x4200,\n0x0000,\n0x0000,\n\n/* Character 73 (0x49):\n   width 5\n   +-----+\n   |     |\n   | *** |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   | *** |\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x7000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 74 (0x4a):\n   width 5\n   +-----+\n   |     |\n   |  ** |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |***  |\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x3000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0xe000,\n0x0000,\n0x0000,\n\n/* Character 75 (0x4b):\n   width 7\n   +-------+\n   |       |\n   | *   * |\n   | *  *  |\n   | * *   |\n   | ***   |\n   | *  *  |\n   | *   * |\n   | *    *|\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x4400,\n0x4800,\n0x5000,\n0x7000,\n0x4800,\n0x4400,\n0x4200,\n0x0000,\n0x0000,\n\n/* Character 76 (0x4c):\n   width 6\n   +------+\n   |      |\n   | *    |\n   | *    |\n   | *    |\n   | *    |\n   | *    |\n   | *    |\n   | *****|\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x7c00,\n0x0000,\n0x0000,\n\n/* Character 77 (0x4d):\n   width 9\n   +---------+\n   |         |\n   | **   ** |\n   | **   ** |\n   | * * * * |\n   | * * * * |\n   | *  *  * |\n   | *  *  * |\n   | *     * |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x6300,\n0x6300,\n0x5500,\n0x5500,\n0x4900,\n0x4900,\n0x4100,\n0x0000,\n0x0000,\n\n/* Character 78 (0x4e):\n   width 7\n   +-------+\n   |       |\n   | *   * |\n   | **  * |\n   | * * * |\n   | * * * |\n   | *  ** |\n   | *   * |\n   | *   * |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x4400,\n0x6400,\n0x5400,\n0x5400,\n0x4c00,\n0x4400,\n0x4400,\n0x0000,\n0x0000,\n\n/* Character 79 (0x4f):\n   width 9\n   +---------+\n   |         |\n   |   ***   |\n   |  *   *  |\n   | *     * |\n   | *     * |\n   | *     * |\n   |  *   *  |\n   |   ***   |\n   |         |\n   |         |\n   +---------+ */\n0x0000,\n0x1c00,\n0x2200,\n0x4100,\n0x4100,\n0x4100,\n0x2200,\n0x1c00,\n0x0000,\n0x0000,\n\n/* Character 80 (0x50):\n   width 7\n   +-------+\n   |       |\n   | ****  |\n   | *   * |\n   | *   * |\n   | *   * |\n   | ****  |\n   | *     |\n   | *     |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x7800,\n0x4400,\n0x4400,\n0x4400,\n0x7800,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 81 (0x51):\n   width 9\n   +---------+\n   |         |\n   |   ***   |\n   |  *   *  |\n   | *     * |\n   | *     * |\n   | *     * |\n   |  *   *  |\n   |   ***   |\n   |     *   |\n   |      ** |\n   +---------+ */\n0x0000,\n0x1c00,\n0x2200,\n0x4100,\n0x4100,\n0x4100,\n0x2200,\n0x1c00,\n0x0400,\n0x0300,\n\n/* Character 82 (0x52):\n   width 8\n   +--------+\n   |        |\n   | ****   |\n   | *   *  |\n   | *   *  |\n   | ****   |\n   | *  *   |\n   | *   *  |\n   | *    * |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x7800,\n0x4400,\n0x4400,\n0x7800,\n0x4800,\n0x4400,\n0x4200,\n0x0000,\n0x0000,\n\n/* Character 83 (0x53):\n   width 7\n   +-------+\n   |       |\n   |  ***  |\n   | *   * |\n   | *     |\n   |  ***  |\n   |     * |\n   | *   * |\n   |  ***  |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x3800,\n0x4400,\n0x4000,\n0x3800,\n0x0400,\n0x4400,\n0x3800,\n0x0000,\n0x0000,\n\n/* Character 84 (0x54):\n   width 7\n   +-------+\n   |       |\n   |*******|\n   |   *   |\n   |   *   |\n   |   *   |\n   |   *   |\n   |   *   |\n   |   *   |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0xfe00,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x0000,\n0x0000,\n\n/* Character 85 (0x55):\n   width 8\n   +--------+\n   |        |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *    * |\n   | *    * |\n   |  ****  |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x4200,\n0x4200,\n0x4200,\n0x4200,\n0x4200,\n0x4200,\n0x3c00,\n0x0000,\n0x0000,\n\n/* Character 86 (0x56):\n   width 7\n   +-------+\n   |       |\n   |*     *|\n   | *   * |\n   | *   * |\n   | *   * |\n   |  * *  |\n   |  * *  |\n   |   *   |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x8200,\n0x4400,\n0x4400,\n0x4400,\n0x2800,\n0x2800,\n0x1000,\n0x0000,\n0x0000,\n\n/* Character 87 (0x57):\n   width 11\n   +-----------+\n   |           |\n   | *   *   * |\n   | *   *   * |\n   |  * * * *  |\n   |  * * * *  |\n   |  * * * *  |\n   |   *   *   |\n   |   *   *   |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x4440,\n0x4440,\n0x2a80,\n0x2a80,\n0x2a80,\n0x1100,\n0x1100,\n0x0000,\n0x0000,\n\n/* Character 88 (0x58):\n   width 7\n   +-------+\n   |       |\n   | *   * |\n   | *   * |\n   |  * *  |\n   |   *   |\n   |  * *  |\n   | *   * |\n   | *   * |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x4400,\n0x4400,\n0x2800,\n0x1000,\n0x2800,\n0x4400,\n0x4400,\n0x0000,\n0x0000,\n\n/* Character 89 (0x59):\n   width 7\n   +-------+\n   |       |\n   |*     *|\n   | *   * |\n   |  * *  |\n   |   *   |\n   |   *   |\n   |   *   |\n   |   *   |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x8200,\n0x4400,\n0x2800,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x0000,\n0x0000,\n\n/* Character 90 (0x5a):\n   width 7\n   +-------+\n   |       |\n   | ***** |\n   |     * |\n   |    *  |\n   |   *   |\n   |  *    |\n   | *     |\n   | ***** |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x7c00,\n0x0400,\n0x0800,\n0x1000,\n0x2000,\n0x4000,\n0x7c00,\n0x0000,\n0x0000,\n\n/* Character 91 (0x5b):\n   width 5\n   +-----+\n   | *** |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   | *   |\n   | *** |\n   +-----+ */\n0x7000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x7000,\n\n/* Character 92 (0x5c):\n   width 5\n   +-----+\n   |*    |\n   |*    |\n   | *   |\n   | *   |\n   |  *  |\n   |  *  |\n   |  *  |\n   |   * |\n   |   * |\n   |     |\n   +-----+ */\n0x8000,\n0x8000,\n0x4000,\n0x4000,\n0x2000,\n0x2000,\n0x2000,\n0x1000,\n0x1000,\n0x0000,\n\n/* Character 93 (0x5d):\n   width 5\n   +-----+\n   | *** |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   |   * |\n   | *** |\n   +-----+ */\n0x7000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x7000,\n\n/* Character 94 (0x5e):\n   width 8\n   +--------+\n   |        |\n   |   **   |\n   |  *  *  |\n   | *    * |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x1800,\n0x2400,\n0x4200,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 95 (0x5f):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |******|\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0xfc00,\n\n/* Character 96 (0x60):\n   width 6\n   +------+\n   |  *   |\n   |   *  |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   |      |\n   +------+ */\n0x2000,\n0x1000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 97 (0x61):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |  ***  |\n   |     * |\n   |  **** |\n   | *   * |\n   |  **** |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3800,\n0x0400,\n0x3c00,\n0x4400,\n0x3c00,\n0x0000,\n0x0000,\n\n/* Character 98 (0x62):\n   width 7\n   +-------+\n   | *     |\n   | *     |\n   | *     |\n   | ****  |\n   | *   * |\n   | *   * |\n   | *   * |\n   | ****  |\n   |       |\n   |       |\n   +-------+ */\n0x4000,\n0x4000,\n0x4000,\n0x7800,\n0x4400,\n0x4400,\n0x4400,\n0x7800,\n0x0000,\n0x0000,\n\n/* Character 99 (0x63):\n   width 5\n   +-----+\n   |     |\n   |     |\n   |     |\n   |  ***|\n   | *   |\n   | *   |\n   | *   |\n   |  ***|\n   |     |\n   |     |\n   +-----+ */\n0x0000,\n0x0000,\n0x0000,\n0x3800,\n0x4000,\n0x4000,\n0x4000,\n0x3800,\n0x0000,\n0x0000,\n\n/* Character 100 (0x64):\n   width 7\n   +-------+\n   |     * |\n   |     * |\n   |     * |\n   |  **** |\n   | *   * |\n   | *   * |\n   | *   * |\n   |  **** |\n   |       |\n   |       |\n   +-------+ */\n0x0400,\n0x0400,\n0x0400,\n0x3c00,\n0x4400,\n0x4400,\n0x4400,\n0x3c00,\n0x0000,\n0x0000,\n\n/* Character 101 (0x65):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |  ***  |\n   | *   * |\n   | ***** |\n   | *     |\n   |  **** |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3800,\n0x4400,\n0x7c00,\n0x4000,\n0x3c00,\n0x0000,\n0x0000,\n\n/* Character 102 (0x66):\n   width 4\n   +----+\n   |  **|\n   | *  |\n   | *  |\n   |****|\n   | *  |\n   | *  |\n   | *  |\n   | *  |\n   |    |\n   |    |\n   +----+ */\n0x3000,\n0x4000,\n0x4000,\n0xf000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 103 (0x67):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |  **** |\n   | *   * |\n   | *   * |\n   | *   * |\n   |  **** |\n   |     * |\n   |  ***  |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3c00,\n0x4400,\n0x4400,\n0x4400,\n0x3c00,\n0x0400,\n0x3800,\n\n/* Character 104 (0x68):\n   width 7\n   +-------+\n   | *     |\n   | *     |\n   | *     |\n   | ****  |\n   | *   * |\n   | *   * |\n   | *   * |\n   | *   * |\n   |       |\n   |       |\n   +-------+ */\n0x4000,\n0x4000,\n0x4000,\n0x7800,\n0x4400,\n0x4400,\n0x4400,\n0x4400,\n0x0000,\n0x0000,\n\n/* Character 105 (0x69):\n   width 3\n   +---+\n   |   |\n   | * |\n   |   |\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   |   |\n   |   |\n   +---+ */\n0x0000,\n0x4000,\n0x0000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 106 (0x6a):\n   width 4\n   +----+\n   |    |\n   |  * |\n   |    |\n   | ** |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |  * |\n   |**  |\n   +----+ */\n0x0000,\n0x2000,\n0x0000,\n0x6000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0xc000,\n\n/* Character 107 (0x6b):\n   width 7\n   +-------+\n   | *     |\n   | *     |\n   | *     |\n   | *  *  |\n   | * *   |\n   | ***   |\n   | *  *  |\n   | *   * |\n   |       |\n   |       |\n   +-------+ */\n0x4000,\n0x4000,\n0x4000,\n0x4800,\n0x5000,\n0x7000,\n0x4800,\n0x4400,\n0x0000,\n0x0000,\n\n/* Character 108 (0x6c):\n   width 3\n   +---+\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   | * |\n   |   |\n   |   |\n   +---+ */\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 109 (0x6d):\n   width 11\n   +-----------+\n   |           |\n   |           |\n   |           |\n   | **** ***  |\n   | *   *   * |\n   | *   *   * |\n   | *   *   * |\n   | *   *   * |\n   |           |\n   |           |\n   +-----------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7b80,\n0x4440,\n0x4440,\n0x4440,\n0x4440,\n0x0000,\n0x0000,\n\n/* Character 110 (0x6e):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   | ****  |\n   | *   * |\n   | *   * |\n   | *   * |\n   | *   * |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7800,\n0x4400,\n0x4400,\n0x4400,\n0x4400,\n0x0000,\n0x0000,\n\n/* Character 111 (0x6f):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |  ***  |\n   | *   * |\n   | *   * |\n   | *   * |\n   |  ***  |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3800,\n0x4400,\n0x4400,\n0x4400,\n0x3800,\n0x0000,\n0x0000,\n\n/* Character 112 (0x70):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   | ****  |\n   | *   * |\n   | *   * |\n   | *   * |\n   | ****  |\n   | *     |\n   | *     |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7800,\n0x4400,\n0x4400,\n0x4400,\n0x7800,\n0x4000,\n0x4000,\n\n/* Character 113 (0x71):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   |  **** |\n   | *   * |\n   | *   * |\n   | *   * |\n   |  **** |\n   |     * |\n   |     * |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3c00,\n0x4400,\n0x4400,\n0x4400,\n0x3c00,\n0x0400,\n0x0400,\n\n/* Character 114 (0x72):\n   width 4\n   +----+\n   |    |\n   |    |\n   |    |\n   | * *|\n   | ** |\n   | *  |\n   | *  |\n   | *  |\n   |    |\n   |    |\n   +----+ */\n0x0000,\n0x0000,\n0x0000,\n0x5000,\n0x6000,\n0x4000,\n0x4000,\n0x4000,\n0x0000,\n0x0000,\n\n/* Character 115 (0x73):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   |  *** |\n   | *    |\n   |  **  |\n   |    * |\n   | ***  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x3800,\n0x4000,\n0x3000,\n0x0800,\n0x7000,\n0x0000,\n0x0000,\n\n/* Character 116 (0x74):\n   width 4\n   +----+\n   |    |\n   | *  |\n   | *  |\n   |****|\n   | *  |\n   | *  |\n   | *  |\n   |  **|\n   |    |\n   |    |\n   +----+ */\n0x0000,\n0x4000,\n0x4000,\n0xf000,\n0x4000,\n0x4000,\n0x4000,\n0x3000,\n0x0000,\n0x0000,\n\n/* Character 117 (0x75):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   | *   * |\n   | *   * |\n   | *   * |\n   | *   * |\n   |  **** |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x4400,\n0x4400,\n0x4400,\n0x4400,\n0x3c00,\n0x0000,\n0x0000,\n\n/* Character 118 (0x76):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | *  * |\n   | *  * |\n   | *  * |\n   |  **  |\n   |  **  |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x4800,\n0x4800,\n0x4800,\n0x3000,\n0x3000,\n0x0000,\n0x0000,\n\n/* Character 119 (0x77):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   | *   * |\n   | * * * |\n   | * * * |\n   |  * *  |\n   |  * *  |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x4400,\n0x5400,\n0x5400,\n0x2800,\n0x2800,\n0x0000,\n0x0000,\n\n/* Character 120 (0x78):\n   width 7\n   +-------+\n   |       |\n   |       |\n   |       |\n   | *   * |\n   |  * *  |\n   |   *   |\n   |  * *  |\n   | *   * |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x0000,\n0x4400,\n0x2800,\n0x1000,\n0x2800,\n0x4400,\n0x0000,\n0x0000,\n\n/* Character 121 (0x79):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | *  * |\n   | *  * |\n   | *  * |\n   |  **  |\n   |   *  |\n   |  *   |\n   |  *   |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x4800,\n0x4800,\n0x4800,\n0x3000,\n0x1000,\n0x2000,\n0x2000,\n\n/* Character 122 (0x7a):\n   width 6\n   +------+\n   |      |\n   |      |\n   |      |\n   | **** |\n   |   *  |\n   |  *   |\n   | *    |\n   | **** |\n   |      |\n   |      |\n   +------+ */\n0x0000,\n0x0000,\n0x0000,\n0x7800,\n0x1000,\n0x2000,\n0x4000,\n0x7800,\n0x0000,\n0x0000,\n\n/* Character 123 (0x7b):\n   width 6\n   +------+\n   |    **|\n   |   *  |\n   |   *  |\n   |   *  |\n   |   *  |\n   | **   |\n   |   *  |\n   |   *  |\n   |   *  |\n   |    **|\n   +------+ */\n0x0c00,\n0x1000,\n0x1000,\n0x1000,\n0x1000,\n0x6000,\n0x1000,\n0x1000,\n0x1000,\n0x0c00,\n\n/* Character 124 (0x7c):\n   width 5\n   +-----+\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   |  *  |\n   +-----+ */\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n\n/* Character 125 (0x7d):\n   width 6\n   +------+\n   |**    |\n   |  *   |\n   |  *   |\n   |  *   |\n   |  *   |\n   |   ** |\n   |  *   |\n   |  *   |\n   |  *   |\n   |**    |\n   +------+ */\n0xc000,\n0x2000,\n0x2000,\n0x2000,\n0x2000,\n0x1800,\n0x2000,\n0x2000,\n0x2000,\n0xc000,\n\n/* Character 126 (0x7e):\n   width 8\n   +--------+\n   |        |\n   |        |\n   |        |\n   |  *   * |\n   | * ** * |\n   | *  **  |\n   |        |\n   |        |\n   |        |\n   |        |\n   +--------+ */\n0x0000,\n0x0000,\n0x0000,\n0x2200,\n0x5a00,\n0x4c00,\n0x0000,\n0x0000,\n0x0000,\n0x0000,\n\n/* Character 164 (0xa4):\n   width 7\n   +-------+\n   |       |\n   |       |\n   | *   * |\n   |  ***  |\n   |  * *  |\n   |  ***  |\n   | *   * |\n   |       |\n   |       |\n   |       |\n   +-------+ */\n0x0000,\n0x0000,\n0x4400,\n0x3800,\n0x2800,\n0x3800,\n0x4400,\n0x0000,\n0x0000,\n0x0000,\n};\n\n/* Character->glyph mapping. */\nstatic const unsigned short _verdana7_offset[] = {\n  0,\t/* (0x20) */\n  10,\t/* (0x21) */\n  20,\t/* (0x22) */\n  30,\t/* (0x23) */\n  40,\t/* (0x24) */\n  50,\t/* (0x25) */\n  60,\t/* (0x26) */\n  70,\t/* (0x27) */\n  80,\t/* (0x28) */\n  90,\t/* (0x29) */\n  100,\t/* (0x2a) */\n  110,\t/* (0x2b) */\n  120,\t/* (0x2c) */\n  130,\t/* (0x2d) */\n  140,\t/* (0x2e) */\n  150,\t/* (0x2f) */\n  160,\t/* (0x30) */\n  170,\t/* (0x31) */\n  180,\t/* (0x32) */\n  190,\t/* (0x33) */\n  200,\t/* (0x34) */\n  210,\t/* (0x35) */\n  220,\t/* (0x36) */\n  230,\t/* (0x37) */\n  240,\t/* (0x38) */\n  250,\t/* (0x39) */\n  260,\t/* (0x3a) */\n  270,\t/* (0x3b) */\n  280,\t/* (0x3c) */\n  290,\t/* (0x3d) */\n  300,\t/* (0x3e) */\n  310,\t/* (0x3f) */\n  320,\t/* (0x40) */\n  330,\t/* (0x41) */\n  340,\t/* (0x42) */\n  350,\t/* (0x43) */\n  360,\t/* (0x44) */\n  370,\t/* (0x45) */\n  380,\t/* (0x46) */\n  390,\t/* (0x47) */\n  400,\t/* (0x48) */\n  410,\t/* (0x49) */\n  420,\t/* (0x4a) */\n  430,\t/* (0x4b) */\n  440,\t/* (0x4c) */\n  450,\t/* (0x4d) */\n  460,\t/* (0x4e) */\n  470,\t/* (0x4f) */\n  480,\t/* (0x50) */\n  490,\t/* (0x51) */\n  500,\t/* (0x52) */\n  510,\t/* (0x53) */\n  520,\t/* (0x54) */\n  530,\t/* (0x55) */\n  540,\t/* (0x56) */\n  550,\t/* (0x57) */\n  560,\t/* (0x58) */\n  570,\t/* (0x59) */\n  580,\t/* (0x5a) */\n  590,\t/* (0x5b) */\n  600,\t/* (0x5c) */\n  610,\t/* (0x5d) */\n  620,\t/* (0x5e) */\n  630,\t/* (0x5f) */\n  640,\t/* (0x60) */\n  650,\t/* (0x61) */\n  660,\t/* (0x62) */\n  670,\t/* (0x63) */\n  680,\t/* (0x64) */\n  690,\t/* (0x65) */\n  700,\t/* (0x66) */\n  710,\t/* (0x67) */\n  720,\t/* (0x68) */\n  730,\t/* (0x69) */\n  740,\t/* (0x6a) */\n  750,\t/* (0x6b) */\n  760,\t/* (0x6c) */\n  770,\t/* (0x6d) */\n  780,\t/* (0x6e) */\n  790,\t/* (0x6f) */\n  800,\t/* (0x70) */\n  810,\t/* (0x71) */\n  820,\t/* (0x72) */\n  830,\t/* (0x73) */\n  840,\t/* (0x74) */\n  850,\t/* (0x75) */\n  860,\t/* (0x76) */\n  870,\t/* (0x77) */\n  880,\t/* (0x78) */\n  890,\t/* (0x79) */\n  900,\t/* (0x7a) */\n  910,\t/* (0x7b) */\n  920,\t/* (0x7c) */\n  930,\t/* (0x7d) */\n  940,\t/* (0x7e) */\n  0,\t/* (0x7f) */\n  0,\t/* (0x80) */\n  0,\t/* (0x81) */\n  0,\t/* (0x82) */\n  0,\t/* (0x83) */\n  0,\t/* (0x84) */\n  0,\t/* (0x85) */\n  0,\t/* (0x86) */\n  0,\t/* (0x87) */\n  0,\t/* (0x88) */\n  0,\t/* (0x89) */\n  0,\t/* (0x8a) */\n  0,\t/* (0x8b) */\n  0,\t/* (0x8c) */\n  0,\t/* (0x8d) */\n  0,\t/* (0x8e) */\n  0,\t/* (0x8f) */\n  0,\t/* (0x90) */\n  0,\t/* (0x91) */\n  0,\t/* (0x92) */\n  0,\t/* (0x93) */\n  0,\t/* (0x94) */\n  0,\t/* (0x95) */\n  0,\t/* (0x96) */\n  0,\t/* (0x97) */\n  0,\t/* (0x98) */\n  0,\t/* (0x99) */\n  0,\t/* (0x9a) */\n  0,\t/* (0x9b) */\n  0,\t/* (0x9c) */\n  0,\t/* (0x9d) */\n  0,\t/* (0x9e) */\n  0,\t/* (0x9f) */\n  0,\t/* (0xa0) */\n  0,\t/* (0xa1) */\n  0,\t/* (0xa2) */\n  0,\t/* (0xa3) */\n  950,\t/* (0xa4) */\n};\n\n/* Character width data. */\nstatic const unsigned char _verdana7_width[] = {\n  4,\t/* (0x20) */\n  4,\t/* (0x21) */\n  5,\t/* (0x22) */\n  8,\t/* (0x23) */\n  7,\t/* (0x24) */\n  11,\t/* (0x25) */\n  7,\t/* (0x26) */\n  3,\t/* (0x27) */\n  5,\t/* (0x28) */\n  5,\t/* (0x29) */\n  7,\t/* (0x2a) */\n  8,\t/* (0x2b) */\n  4,\t/* (0x2c) */\n  5,\t/* (0x2d) */\n  4,\t/* (0x2e) */\n  5,\t/* (0x2f) */\n  7,\t/* (0x30) */\n  7,\t/* (0x31) */\n  7,\t/* (0x32) */\n  7,\t/* (0x33) */\n  7,\t/* (0x34) */\n  7,\t/* (0x35) */\n  7,\t/* (0x36) */\n  7,\t/* (0x37) */\n  7,\t/* (0x38) */\n  7,\t/* (0x39) */\n  5,\t/* (0x3a) */\n  5,\t/* (0x3b) */\n  8,\t/* (0x3c) */\n  8,\t/* (0x3d) */\n  8,\t/* (0x3e) */\n  6,\t/* (0x3f) */\n  10,\t/* (0x40) */\n  7,\t/* (0x41) */\n  7,\t/* (0x42) */\n  8,\t/* (0x43) */\n  8,\t/* (0x44) */\n  6,\t/* (0x45) */\n  6,\t/* (0x46) */\n  8,\t/* (0x47) */\n  8,\t/* (0x48) */\n  5,\t/* (0x49) */\n  5,\t/* (0x4a) */\n  7,\t/* (0x4b) */\n  6,\t/* (0x4c) */\n  9,\t/* (0x4d) */\n  7,\t/* (0x4e) */\n  9,\t/* (0x4f) */\n  7,\t/* (0x50) */\n  9,\t/* (0x51) */\n  8,\t/* (0x52) */\n  7,\t/* (0x53) */\n  7,\t/* (0x54) */\n  8,\t/* (0x55) */\n  7,\t/* (0x56) */\n  11,\t/* (0x57) */\n  7,\t/* (0x58) */\n  7,\t/* (0x59) */\n  7,\t/* (0x5a) */\n  5,\t/* (0x5b) */\n  5,\t/* (0x5c) */\n  5,\t/* (0x5d) */\n  8,\t/* (0x5e) */\n  6,\t/* (0x5f) */\n  6,\t/* (0x60) */\n  7,\t/* (0x61) */\n  7,\t/* (0x62) */\n  5,\t/* (0x63) */\n  7,\t/* (0x64) */\n  7,\t/* (0x65) */\n  4,\t/* (0x66) */\n  7,\t/* (0x67) */\n  7,\t/* (0x68) */\n  3,\t/* (0x69) */\n  4,\t/* (0x6a) */\n  7,\t/* (0x6b) */\n  3,\t/* (0x6c) */\n  11,\t/* (0x6d) */\n  7,\t/* (0x6e) */\n  7,\t/* (0x6f) */\n  7,\t/* (0x70) */\n  7,\t/* (0x71) */\n  4,\t/* (0x72) */\n  6,\t/* (0x73) */\n  4,\t/* (0x74) */\n  7,\t/* (0x75) */\n  6,\t/* (0x76) */\n  7,\t/* (0x77) */\n  7,\t/* (0x78) */\n  6,\t/* (0x79) */\n  6,\t/* (0x7a) */\n  6,\t/* (0x7b) */\n  5,\t/* (0x7c) */\n  6,\t/* (0x7d) */\n  8,\t/* (0x7e) */\n  4,\t/* (0x7f) */\n  4,\t/* (0x80) */\n  4,\t/* (0x81) */\n  4,\t/* (0x82) */\n  4,\t/* (0x83) */\n  4,\t/* (0x84) */\n  4,\t/* (0x85) */\n  4,\t/* (0x86) */\n  4,\t/* (0x87) */\n  4,\t/* (0x88) */\n  4,\t/* (0x89) */\n  4,\t/* (0x8a) */\n  4,\t/* (0x8b) */\n  4,\t/* (0x8c) */\n  4,\t/* (0x8d) */\n  4,\t/* (0x8e) */\n  4,\t/* (0x8f) */\n  4,\t/* (0x90) */\n  4,\t/* (0x91) */\n  4,\t/* (0x92) */\n  4,\t/* (0x93) */\n  4,\t/* (0x94) */\n  4,\t/* (0x95) */\n  4,\t/* (0x96) */\n  4,\t/* (0x97) */\n  4,\t/* (0x98) */\n  4,\t/* (0x99) */\n  4,\t/* (0x9a) */\n  4,\t/* (0x9b) */\n  4,\t/* (0x9c) */\n  4,\t/* (0x9d) */\n  4,\t/* (0x9e) */\n  4,\t/* (0x9f) */\n  4,\t/* (0xa0) */\n  4,\t/* (0xa1) */\n  4,\t/* (0xa2) */\n  4,\t/* (0xa3) */\n  7,\t/* (0xa4) */\n};\n\n/* Exported structure definition. */\nconst struct gpanel_font_t font_verdana7 = {\n  \"verdana7\",\n  11,\n  10,\n  8,\n  32,\n  133,\n  _verdana7_bits,\n  _verdana7_offset,\n  _verdana7_width,\n  32,\n  sizeof(_verdana7_bits) / sizeof(_verdana7_bits[0]),\n};\n"
  },
  {
    "path": "share/examples/gpanel/line.c",
    "content": "/*\n * Draw random lines.\n */\n#include <stdio.h>\n#include <sys/gpanel.h>\n\nint xsize, ysize;\n\nint main()\n{\n    char *devname = \"/dev/tft0\";\n    int x0, y0, x1, y1, color;\n\n    if (gpanel_open(devname) < 0) {\n        printf(\"Cannot open %s\\n\", devname);\n        exit(-1);\n    }\n    gpanel_clear(0, &xsize, &ysize);\n    printf(\"Screen size %u x %u.\\n\", xsize, ysize);\n\n    srand(time(0));\n    printf(\"Draw random lines.\\n\");\n    printf(\"Press ^C to stop.\\n\");\n\n    for (;;) {\n        x0 = rand() % xsize;\n        y0 = rand() % ysize;\n        x1 = rand() % xsize;\n        y1 = rand() % ysize;\n        color = rand() << 1;\n        gpanel_line(color, x0, y0, x1, y1);\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/gpanel/pixel.c",
    "content": "/*\n * Draw random pixels.\n */\n#include <stdio.h>\n#include <sys/gpanel.h>\n\nint xsize, ysize;\n\nint main()\n{\n    char *devname = \"/dev/tft0\";\n    int x, y, color;\n\n    if (gpanel_open(devname) < 0) {\n        printf(\"Cannot open %s\\n\", devname);\n        exit(-1);\n    }\n    gpanel_clear(0, &xsize, &ysize);\n    printf(\"Screen size %u x %u.\\n\", xsize, ysize);\n\n    srand(time(0));\n    printf(\"Draw random pixels.\\n\");\n    printf(\"Press ^C to stop.\\n\");\n\n    for (;;) {\n        x = rand() % xsize;\n        y = rand() % ysize;\n        color = rand() << 1;\n        gpanel_pixel(color, x, y);\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/gpanel/rect.c",
    "content": "/*\n * Draw random rectangles.\n */\n#include <stdio.h>\n#include <sys/gpanel.h>\n\nint xsize, ysize;\n\nint main()\n{\n    char *devname = \"/dev/tft0\";\n    int x0, y0, x1, y1, color;\n\n    if (gpanel_open(devname) < 0) {\n        printf(\"Cannot open %s\\n\", devname);\n        exit(-1);\n    }\n    gpanel_clear(0, &xsize, &ysize);\n    printf(\"Screen size %u x %u.\\n\", xsize, ysize);\n\n    srand(time(0));\n    printf(\"Draw random rectangles.\\n\");\n    printf(\"Press ^C to stop.\\n\");\n\n    for (;;) {\n        x0 = rand() % xsize;\n        y0 = rand() % ysize;\n        x1 = rand() % xsize;\n        y1 = rand() % ysize;\n        color = rand() << 1;\n        gpanel_rect(color, x0, y0, x1, y1);\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/gpanel/speed.c",
    "content": "/*\n * Test the gpanel functions for speed.\n */\n#include <stdio.h>\n#include <sys/gpanel.h>\n#include <sys/time.h>\n\n#define NPIXELS     100000\n#define NLINES      3000\n#define NRECT       1000\n#define NCIRCLES    1000\n#define NCHARS      10000\n\nextern const struct gpanel_font_t font_lucidasans15;\n\nint xsize, ysize;\n\n/*\n * Get current time in milliseconds.\n */\nunsigned current_msec()\n{\n    struct timeval t;\n\n    gettimeofday(&t, 0);\n    return t.tv_sec * 1000 + t.tv_usec / 1000;\n}\n\n/*\n * Compute elapsed time in milliseconds.\n */\nunsigned elapsed_msec(unsigned t0)\n{\n    struct timeval t1;\n    unsigned msec;\n\n    gettimeofday (&t1, 0);\n    msec = t1.tv_sec * 1000 + t1.tv_usec / 1000;\n    msec -= t0;\n    if (msec < 1)\n        msec = 1;\n    return msec;\n}\n\nint main()\n{\n    char *devname = \"/dev/tft0\";\n    int x, y, x1, y1, color, i, r, sym;\n    unsigned t0, msec;\n\n    if (gpanel_open(devname) < 0) {\n        printf(\"Cannot open %s\\n\", devname);\n        exit(-1);\n    }\n    gpanel_clear(0, &xsize, &ysize);\n    printf(\"Screen size %u x %u.\\n\", xsize, ysize);\n\n    /* Use fixed seed, for repeatability. */\n    srand(1);\n    printf(\"Graphics speed:\\n\");\n    sync();\n    usleep(500000);\n\n    /*\n     * Pixels.\n     */\n    t0 = current_msec();\n    for (i=0; i<NPIXELS; i++) {\n        x = rand() % xsize;\n        y = rand() % ysize;\n        color = rand() << 1;\n        gpanel_pixel(color, x, y);\n    }\n    msec = elapsed_msec(t0);\n    printf (\" %u pixels/second\\n\", NPIXELS*1000U / msec);\n\n    /*\n     * Lines.\n     */\n    t0 = current_msec();\n    for (i=0; i<NLINES; i++) {\n        x = rand() % xsize;\n        y = rand() % ysize;\n        x1 = rand() % xsize;\n        y1 = rand() % ysize;\n        color = rand() << 1;\n        gpanel_line(color, x, y, x1, y1);\n    }\n    msec = elapsed_msec(t0);\n    printf (\" %u lines/second\\n\", NLINES*1000U / msec);\n\n    /*\n     * Filled rectangles.\n     */\n    t0 = current_msec();\n    for (i=0; i<NRECT; i++) {\n        x = rand() % xsize;\n        y = rand() % ysize;\n        x1 = rand() % xsize;\n        y1 = rand() % ysize;\n        color = rand() << 1;\n        gpanel_fill(color, x, y, x1, y1);\n    }\n    msec = elapsed_msec(t0);\n    printf (\" %u rectangles/second\\n\", NRECT*1000U / msec);\n\n    /*\n     * Circles.\n     */\n    t0 = current_msec();\n    for (i=0; i<NCIRCLES; i++) {\n        x = rand() % xsize;\n        y = rand() % ysize;\n        r = rand() % ysize;\n        color = rand() << 1;\n        gpanel_circle(color, x, y, r);\n    }\n    msec = elapsed_msec(t0);\n    printf (\" %u circles/second\\n\", NCIRCLES*1000U / msec);\n\n    /*\n     * Characters.\n     */\n    t0 = current_msec();\n    for (i=0; i<NCHARS; i++) {\n        x = rand() % xsize;\n        y = rand() % ysize;\n        sym = '!' + rand() % ('~' - ' ');\n        color = rand() << 1;\n        gpanel_char(&font_lucidasans15, color, -1, x, y, sym);\n    }\n    msec = elapsed_msec(t0);\n    printf (\" %u characters/second\\n\", NCHARS*1000U / msec);\n\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/gpanel/tft.c",
    "content": "#include <stdio.h>\n#include <fcntl.h>\n#include <unistd.h>\n#include <sys/ioctl.h>\n#include <sys/gpio.h>\n#include <sys/gpanel.h>\n#include <time.h>\n\n#define BLACK 0x0000\n#define RED   0xF800\n#define GREEN 0x07E0\n#define BLUE  0x001F\n#define WHITE 0xFFFF\n\nint fd = -1;\n\nvoid pixel(unsigned x, unsigned y, unsigned color)\n{\n  struct gpanel_pixel_t param;\n\n  param.color = color;\n  param.x = x;\n  param.y = y;\n  ioctl(fd, GPANEL_PIXEL, &param);\n}\n\nvoid lineh(unsigned x, unsigned y,\n           unsigned length, unsigned color)\n{\n  struct gpanel_line_t param;\n\n  param.color = color;\n  param.x0 = x;\n  param.y0 = y;\n  param.x1 = x + length - 1;\n  param.y1 = y;\n  ioctl(fd, GPANEL_LINE, &param);\n}\n\nvoid linev(unsigned x, unsigned y,\n           unsigned length, unsigned color)\n{\n  struct gpanel_line_t param;\n\n  param.color = color;\n  param.x0 = x;\n  param.y0 = y;\n  param.x1 = x;\n  param.y1 = y + length - 1;\n  ioctl(fd, GPANEL_LINE, &param);\n}\n\nvoid box(unsigned x, unsigned y,\n         unsigned width, unsigned height,\n         unsigned color, int solid)\n{\n  if (solid)\n  {\n    struct gpanel_rect_t param;\n\n    param.color = color;\n    param.x0 = x;\n    param.y0 = y;\n    param.x1 = x + width - 1;\n    param.y1 = y + height - 1;\n    ioctl(fd, GPANEL_FILL, &param);\n  }\n  else\n  {\n    lineh(x, y, width, color);\n    lineh(x, y + height - 1, width, color);\n    linev(x, y, height, color);\n    linev(x + width - 1, y, height, color);\n  }\n}\n\nvoid line(int x1, int y1,\n          int x2, int y2,\n          unsigned short color)\n{\n  int sx, sy, dx1, dy1, dx2, dy2, x, y, m, n, k, cnt;\n\n  sx = x2 - x1;\n  sy = y2 - y1;\n\n  if (sy < 0 || sy == 0 && sx < 0)\n  {\n    k = x1; x1 = x2; x2 = k;\n    k = y1; y1 = y2; y2 = k;\n    sx = -sx;\n    sy = -sy;\n  }\n\n  if (sx > 0) dx1 = 1;\n  else if (sx < 0) dx1 = -1;\n  else dy1 = 0;\n\n  if (sy > 0) dy1 = 1;\n  else if (sy < 0) dy1 = -1;\n  else dy1 = 0;\n\n  m = (sx >= 0) ? sx : -sx;\n  n = (sy >= 0) ? sy : -sy;\n  dx2 = dx1;\n  dy2 = 0;\n\n  if (m < n)\n  {\n    m = (sy >= 0) ? sy : -sy;\n    n = (sx >= 0) ? sx : -sx;\n    dx2 = 0;\n    dy2 = dy1;\n  }\n\n  x = x1; y = y1;\n  cnt = m + 1;\n  k = n / 2;\n\n  while (cnt--)\n  {\n    if (x >= 0 && x < 480 && y >= 0 && y < 320)\n      pixel(x, y, color);\n\n    k += n;\n    if (k < m)\n    {\n      x += dx2;\n      y += dy2;\n    }\n    else\n    {\n      k -= m;\n      x += dx1;\n      y += dy1;\n    }\n  }\n}\n\nint main(int argc, char* argv[])\n{\n  if ((fd = open (\"/dev/tft0\", O_RDWR)) < 0)\n  {\n    perror(\"/dev/tft0\");\n    return 1;\n  }\n\n  if (argc > 1)\n  {\n    if (!strcmp(argv[1], \"-blank\"))\n    {\n      box(0, 0, 480, 320, BLACK, 1);\n      return 0;\n    }\n  }\n\n  for (int y = 0; y < 320; y++)\n    for (int x = 0; x < 480; x++)\n      pixel(x, y, (x<<3) ^ (y<<3));\n\n  sleep(2);\n\n  box(0, 0*100, 480, 100, RED, 1);\n  box(0, 1*100, 480, 100, GREEN, 1);\n  box(0, 2*100, 480, 100, BLUE, 1);\n\n  box(0, 0, 480, 320, WHITE, 0);\n\n  line(0, 0, 479, 319, RED | GREEN);\n  line(479, 0, 0, 319, GREEN | BLUE);\n\n  sleep(2);\n\n//  for (;;) line(rand() & 511, rand() & 511, rand() & 511, rand() & 511, rand());\n\n#if 01\n  time_t t1 = time(NULL), t2;\n  int fps = 0;\n  do\n  {\n    t2 = time(NULL);\n    box(0, 0, 480, 320, rand(), 1);\n    fps++;\n  } while (t2 < t1 + 10);\n\n  printf(\"%d fps\\n\", fps / 10);\n#endif\n\n  sleep(2);\n\n  box(0, 0, 480, 320, BLACK, 1);\n\n  return 0;\n}\n"
  },
  {
    "path": "share/examples/gpanel/tftetris.c",
    "content": "/*\nArduino/RetroBSD Tetris\nCopyright (C) 2015  João André Esteves Vilaça\n\nhttps://github.com/vilaca/Handheld-Color-Console\n\nAdapted for RetroBSD by Alexey Frunze.\nRequired Hardware:\n- PICadillo-35T board\n- Funduino joystick shield v1.a\n\nThis program is free software; you can redistribute it and/or modify\nit under the terms of the GNU General Public License as published by\nthe Free Software Foundation; either version 2 of the License, or\n(at your option) any later version.\n\nThis program is free software; you can redistribute it and/or modify\nit under the terms of the GNU General Public License as published by\nthe Free Software Foundation; either version 2 of the License, or\n(at your option) any later version.\n\nThis program is distributed in the hope that it will be useful,\nbut WITHOUT ANY WARRANTY; without even the implied warranty of\nMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\nGNU General Public License for more details.\n\nYou should have received a copy of the GNU General Public License along\nwith this program; if not, write to the Free Software Foundation, Inc.,\n51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n*/\n\n#include <string.h>\n#include <stdlib.h>\n#include <time.h>\n#include <fcntl.h>\n#include <unistd.h>\n\nvolatile int quit = 0;\nvolatile int jx = 0, jy = 0;\n\n#include <sys/ioctl.h>\n#include <sys/gpio.h>\n#include <sys/time.h>\n#include <sys/gpanel.h>\n\nint fd = -1;\nint fdx = -1;\nint fdy = -1;\n\nstruct timeval start_time;\n\nunsigned long millis(void)\n{\n  static int init;\n  struct timeval t;\n  unsigned long ms;\n  if (!init)\n  {\n    gettimeofday(&start_time, 0);\n    init = 1;\n    return 0;\n  }\n  gettimeofday(&t, 0);\n  ms = (t.tv_sec - start_time.tv_sec) * 1000UL;\n  ms += t.tv_usec / 1000;\n  ms -= start_time.tv_usec / 1000;\n  return ms;\n}\n\nvoid delay(unsigned long ms)\n{\n  usleep(ms * 1000);\n}\n\nvoid lineh(unsigned x, unsigned y,\n           unsigned length, unsigned color)\n{\n  struct gpanel_line_t param;\n\n  param.color = color;\n  param.x0 = x;\n  param.y0 = y;\n  param.x1 = x + length - 1;\n  param.y1 = y;\n  ioctl(fd, GPANEL_LINE, &param);\n}\n\nvoid linev(unsigned x, unsigned y,\n           unsigned length, unsigned color)\n{\n  struct gpanel_line_t param;\n\n  param.color = color;\n  param.x0 = x;\n  param.y0 = y;\n  param.x1 = x;\n  param.y1 = y + length - 1;\n  ioctl(fd, GPANEL_LINE, &param);\n}\n\nvoid box(unsigned x, unsigned y,\n         unsigned width, unsigned height,\n         unsigned color, int solid)\n{\n  if (solid)\n  {\n    struct gpanel_rect_t param;\n\n    param.color = color;\n    param.x0 = x;\n    param.y0 = y;\n    param.x1 = x + width - 1;\n    param.y1 = y + height - 1;\n    ioctl(fd, GPANEL_FILL, &param);\n  }\n  else\n  {\n    lineh(x, y, width, color);\n    lineh(x, y + height - 1, width, color);\n    linev(x, y, height, color);\n    linev(x + width - 1, y, height, color);\n  }\n}\n\nvoid beep(int frq, int d)\n{\n  (void)frq; // TBD???\n  delay(d);\n}\n\nvoid boxb(unsigned x, unsigned y, unsigned w, unsigned h, unsigned short c)\n{\n  box(x, y, w, h - 1, c, 1);\n  box(x, y + h - 1, 1, 1, c, 1);\n}\n\nint Joystick_fire(void)\n{\n  return 0; // TBD???\n}\n\nint Joystick_getX(void)\n{\n  char buf[21] = { 0 };\n  jx = 512;\n  if (read(fdx, buf, sizeof buf - 1) > 0)\n    jx = strtol(buf, 0, 0);\n  jx -= 512;\n  jx = -jx;\n  if (-128 < jx && jx < 128)\n    jx = 0;\n  return jx;\n}\n\nint Joystick_getY(void)\n{\n  char buf[21] = { 0 };\n  jy = 512;\n  if (read(fdy, buf, sizeof buf - 1) > 0)\n    jy = strtol(buf, 0, 0);\n  jy -= 512;\n  jy = -jy;\n  if (-128 < jy && jy < 128)\n    jy = 0;\n  return jy;\n}\n\nvoid Joystick_waitForRelease(int howLong)\n{\n  int c = 0;\n  do\n  {\n    delay(10);\n    c += 10;\n  }\n  while ((Joystick_fire() || Joystick_getY() || Joystick_getX()) && c < howLong);\n}\n\nvoid randomizer(void);\nvoid score(void);\nvoid scoreBoard(void);\nvoid draw(void);\nvoid moveDown(void);\nvoid userInput(unsigned long now);\nvoid chooseNewShape(void);\nint touches(int xi, int yi, int roti);\n\n//TFT resolution 480x320\n#define LCD_WIDTH 480//320//480\n#define LCD_HEIGHT 320//200//320\n\n#define MIN(X, Y) (((X) < (Y)) ? (X) : (Y))\n\n#define FONT_SPACE 6\n#define FONT_X 8\nextern unsigned char simpleFont[][8];\n\nenum\n{\n  BOARD_WIDTH  = 11,\n  BOARD_HEIGHT = 20,\n\n  BLOCK_SIZE   = MIN(LCD_WIDTH / BOARD_WIDTH - 1, LCD_HEIGHT / BOARD_HEIGHT - 1),\n\n  BOARD_LEFT   = (LCD_WIDTH - BOARD_WIDTH * BLOCK_SIZE) / 4 * 3,\n  BOARD_RIGHT  = BOARD_LEFT + BLOCK_SIZE * BOARD_WIDTH,\n  BOARD_TOP    = (LCD_HEIGHT - BOARD_HEIGHT * BLOCK_SIZE) / 2,\n  BOARD_BOTTOM = BOARD_TOP + BOARD_HEIGHT * BLOCK_SIZE\n};\n\n//Basic Colors\n#define BLACK       0x0000\n#define BLUE        0x001f\n#define CYAN        0x07ff\n#define DARKCYAN    0x03EF      /*   0, 128, 128 */\n#define DARKGREEN   0x03E0\n#define DARKGREY    0x7BEF      /* 128, 128, 128 */\n#define GRAY1       0x8410\n#define GRAY2       0x4208\n#define GRAY3       0x2104\n#define GREEN       0x07e0\n#define LIGHTGREEN  0xAFE5      /* 173, 255,  47 */\n#define LIGHTGREY   0xC618      /* 192, 192, 192 */\n#define MAGENTA     0xF81F      /* 255,   0, 255 */\n#define MAROON      0x7800      /* 128,   0,   0 */\n#define NAVY        0x000F      /*   0,   0, 128 */\n#define OLIVE       0x7BE0      /* 128, 128,   0 */\n#define ORANGE      0xFD20      /* 255, 165,   0 */\n#define PURPLE      0x780F      /* 128,   0, 128 */\n#define RED         0xf800\n#define WHITE       0xffff\n#define YELLOW      0xffe0\n\n#define PIT_COLOR   CYAN\n#define BG_COLOR    BLACK\n\ntypedef unsigned char byte;\n\n// used to clear the position from the screen\ntypedef struct\n{\n  byte x, y, rot;\n} Backup;\n\n#define DROP_WAIT_INIT  1100\n\n#define INPUT_WAIT_ROT  200\n#define INPUT_WAIT_MOVE 100\n\n#define INPUT_WAIT_NEW_SHAPE 400\n\n// shapes definitions\n\nbyte l_shape[4][4][2] =\n{\n  { {0, 0}, {0, 1}, {0, 2}, {1, 2} },\n  { {0, 1}, {1, 1}, {2, 0}, {2, 1} },\n  { {0, 0}, {1, 0}, {1, 1}, {1, 2} },\n  { {0, 0}, {0, 1}, {1, 0}, {2, 0} },\n};\n\nbyte j_shape[4][4][2] =\n{\n  { {1, 0}, {1, 1}, {0, 2}, {1, 2} },\n  { {0, 0}, {1, 0}, {2, 0}, {2, 1} },\n  { {0, 0}, {1, 0}, {0, 1}, {0, 2} },\n  { {0, 0}, {0, 1}, {1, 1}, {2, 1} },\n};\n\nbyte o_shape[1][4][2] =\n{\n  { {0, 0}, {0, 1}, {1, 0}, {1, 1} }\n};\n\nbyte s_shape[2][4][2] =\n{\n  { {0, 1}, {1, 0}, {1, 1}, {2, 0} },\n  { {0, 0}, {0, 1}, {1, 1}, {1, 2} }\n};\n\nbyte z_shape[2][4][2] =\n{\n  { {0, 0}, {1, 0}, {1, 1}, {2, 1} },\n  { {1, 0}, {0, 1}, {1, 1}, {0, 2} }\n};\n\nbyte t_shape[4][4][2] =\n{\n  { {0, 0}, {1, 0}, {2, 0}, {1, 1} },\n  { {0, 0}, {0, 1}, {1, 1}, {0, 2} },\n  { {1, 0}, {0, 1}, {1, 1}, {2, 1} },\n  { {1, 0}, {0, 1}, {1, 1}, {1, 2} }\n};\n\nbyte i_shape[2][4][2] =\n{\n  { {0, 0}, {1, 0}, {2, 0}, {3, 0} },\n  { {0, 0}, {0, 1}, {0, 2}, {0, 3} } // TBD??? rotate at the center\n};\n\n// All game shapes and their colors\n\nbyte* all_shapes[7] =\n{\n  l_shape[0][0],\n  j_shape[0][0],\n  o_shape[0][0],\n  s_shape[0][0],\n  z_shape[0][0],\n  t_shape[0][0],\n  i_shape[0][0]\n};\n\n\nunsigned short colors[7] = { ORANGE, BLUE, YELLOW, GREEN, RED, MAGENTA, CYAN };\n\n// how many rotated variations each shape has\nbyte shapes[7] = { 4, 4, 1, 2, 2, 4, 2 };\n\n// game progress\nint lines, level;\n\n// current shapes\nbyte current;\n\n// tetris guidelines have all 7 shapes\n// selected in sequence to avoid\n// long runs without a shape\nbyte next[7];\nbyte next_c;\n\nunsigned long lastInput, lastDrop;\n\nbyte board[BOARD_HEIGHT][BOARD_WIDTH];\n\nbyte x, y, rot;\nBackup old;\n\nint newShape;\n\nunsigned long dropWait;\n\nvoid drawChar(byte ascii, unsigned poX, unsigned poY, unsigned size, unsigned short fgcolor)\n{\n  if ((ascii < 32) || (ascii > 127))\n    ascii = '?' - 32;\n\n  for (int i = 0; i < FONT_X; i++)\n  {\n    byte temp = simpleFont[ascii - 32][i];\n    for (byte f = 0; f < 8; f++)\n      if ((temp >> f) & 1)\n        box(poX + i * size, poY + f * size, size, size, fgcolor, 1);\n  }\n}\n\nvoid drawString(char* string, unsigned poX, unsigned poY, unsigned size, unsigned short fgcolor)\n{\n  while (*string)\n  {\n    drawChar(*string++, poX, poY, size, fgcolor);\n    poX += FONT_SPACE * size;\n  }\n}\n\nvoid drawCenteredString(char* string, unsigned poY, unsigned size, unsigned short fgcolor)\n{\n  unsigned len = strlen(string) * FONT_SPACE * size;\n  unsigned left = (LCD_WIDTH - len) / 2;\n  drawString(string, left, poY, size, fgcolor);\n}\n\nvoid drawNumber(long long_num, unsigned poX, unsigned poY, unsigned size, unsigned short fgcolor)\n{\n  char buf[12], *p = buf + sizeof buf;\n  int neg = long_num < 0;\n  unsigned long n = neg ? -(unsigned long)long_num : (unsigned long)long_num;\n\n  *--p = '\\0';\n\n  do\n  {\n    *--p = '0' + n % 10;\n    n /= 10;\n  } while (n);\n\n  if (neg)\n    *--p = '-';\n\n  drawString(p, poX, poY, size, fgcolor);\n}\n\nvoid bcackground(void)\n{\n  // draw black-blue gradient background\n  for (int i = 0; i < LCD_HEIGHT; i++)\n  {\n    int c = 31 - i * 31 / (LCD_HEIGHT - 1);\n    if (i < BOARD_BOTTOM)\n    {\n      lineh(0, i, BOARD_LEFT - 1, c);\n      lineh(BOARD_RIGHT, i, LCD_WIDTH - BOARD_RIGHT, c);\n    }\n    else\n    {\n      lineh(0, i, LCD_WIDTH, c);\n    }\n  }\n\n  // draw the board left limit\n  linev(BOARD_LEFT - 1, BOARD_TOP, BOARD_BOTTOM - BOARD_TOP, PIT_COLOR);\n\n  // draw the board right limit\n  linev(BOARD_RIGHT - 1, BOARD_TOP, BOARD_BOTTOM - BOARD_TOP, PIT_COLOR);\n\n  // draw the board bottom limit\n  lineh(BOARD_LEFT - 1, BOARD_BOTTOM - 1, BOARD_RIGHT - BOARD_LEFT + 1, PIT_COLOR);\n\n  // draw the grid\n  for (int i = BOARD_LEFT + BLOCK_SIZE - 1; i < BOARD_RIGHT - 1; i += BLOCK_SIZE)\n    linev(i, BOARD_TOP, BOARD_BOTTOM - BOARD_TOP - 1, GRAY2);\n  for (int i = BOARD_TOP + BLOCK_SIZE - 1; i < BOARD_BOTTOM - 1; i += BLOCK_SIZE)\n    lineh(BOARD_LEFT, i, BOARD_RIGHT - BOARD_LEFT - 1, GRAY2);\n}\n\nvoid scoreBoard(void)\n{\n  box(6, 3, 128, 50, BLACK, 1);\n  drawString(\"Level\", 8, 8, 2, YELLOW);\n  drawString(\"Lines\", 8, 32, 2, 0x3f);\n  drawNumber(level, 74, 8, 2, YELLOW);\n  drawNumber(lines, 74, 32, 2, 0x3f);\n  box(5, 2, 130, 52, WHITE, 0);\n}\n\nvoid hint(void)\n{\n  // draw next shape hint box\n  box(30, 100, BLOCK_SIZE * 6, BLOCK_SIZE * 5, BLACK, 1);\n  box(29, 99, BLOCK_SIZE * 6 + 1, BLOCK_SIZE * 5 + 1, WHITE, 0);\n\n  byte* shape = all_shapes[next[next_c]];\n  for (int i = 0; i < 4; i++)\n  {\n    byte* block = shape + i * 2;\n    boxb(30 + BLOCK_SIZE + block[0] * BLOCK_SIZE,\n         100 + BLOCK_SIZE + block[1] * BLOCK_SIZE,\n         BLOCK_SIZE - 1,\n         BLOCK_SIZE - 1,\n         colors[next[next_c]]);\n  }\n}\n\nvoid gameLoop(void)\n{\n  box(0, 0, LCD_WIDTH, LCD_HEIGHT, BG_COLOR, 1);\n\n  // initialize game logic\n  newShape = 1;\n  lines = 0;\n  lastInput = 0;\n  lastDrop = 0;\n  dropWait = DROP_WAIT_INIT;\n  level = 1;\n\n  // clean board\n  for (int i = 0; i < BOARD_WIDTH; i++)\n    for (int j = 0; j < BOARD_HEIGHT; j++)\n      board[j][i] = 0;\n\n  // next shape\n  randomizer();\n\n  bcackground();\n\n  scoreBoard();\n\n  do\n  {\n    // get clock\n    unsigned long now = millis();\n\n    // display new shape\n    if (newShape)\n    {\n      Joystick_waitForRelease(INPUT_WAIT_NEW_SHAPE);\n      newShape = 0;\n\n      // a new shape enters the game\n      chooseNewShape();\n\n      // draw next shape hint box\n      hint();\n\n      // check if new shape is placed over other shape(s)\n      // on the board\n      if (touches(0, 0, 0))\n      {\n        // draw shape to screen\n        draw();\n        // game over\n        return;\n      }\n\n      // draw shape to screen\n      draw();\n    }\n    else\n    {\n      // check if enough time has passed since last time the shape\n      // was moved down the board\n      if (now - lastDrop > dropWait || Joystick_getY() > 0)\n      {\n        // update clock\n        lastDrop = now;\n\n        moveDown();\n      }\n    }\n    if (!newShape && now - lastInput > INPUT_WAIT_MOVE)\n    {\n      userInput(now);\n    }\n  } while (!quit);\n}\n\nvoid chooseNewShape(void)\n{\n  current = next[next_c];\n\n  next_c++;\n\n  if (next_c == 7)\n    randomizer();\n\n  // new shape must be postioned at the middle of\n  // the top of the board\n  // with zero rotation\n  rot = 0;\n  y = 0;\n  x = BOARD_WIDTH / 2 - 1;\n\n  old.rot = rot;\n  old.y = y;\n  old.x = x;\n}\n\nvoid userInput(unsigned long now)\n{\n  int jx = Joystick_getX();\n  if (jx < 0 && x > 0 && !touches(-1, 0, 0))\n  {\n    x--;\n  }\n  else if (jx > 0 && x < BOARD_WIDTH && !touches(1, 0, 0))\n  {\n    x++;\n  }\n  else if (Joystick_fire())\n  {\n    while (!touches(0, 1, 0))\n      y++;\n  }\n  else if (now - lastInput > INPUT_WAIT_ROT)\n  {\n    if (Joystick_getY() < 0 && !touches(0, 0, 1))\n    {\n      rot++;\n      rot %= shapes[current];\n    }\n  }\n  else\n  {\n    return;\n  }\n  lastInput = now;\n  draw();\n}\n\nvoid moveDown(void)\n{\n  // prepare to move down\n  // check if board is clear bellow\n  if (touches(0, 1, 0))\n  {\n    // moving down touches another shape\n    newShape = 1;\n\n    // this shape wont move again\n    // add it to the board\n    byte* shape = all_shapes[current];\n    for (int i = 0; i < 4; i++)\n    {\n      byte* block = shape + (rot * 4 + i) * 2;\n      board[block[1] + y][block[0] + x] = current + 1;\n    }\n\n    // check if lines were made\n    score();\n    beep(1500, 25);\n  }\n  else\n  {\n    // move shape down\n    y++;\n    draw();\n  }\n}\n\nvoid draw(void)\n{\n  byte* shape = all_shapes[current];\n  for (int i = 0; i < 4; i++)\n  {\n    byte* block = shape + (rot * 4 + i) * 2;\n    boxb(BOARD_LEFT + block[0] * BLOCK_SIZE + BLOCK_SIZE * x,\n         BOARD_TOP + block[1] * BLOCK_SIZE + BLOCK_SIZE * y,\n         BLOCK_SIZE - 1,\n         BLOCK_SIZE - 1,\n         colors[current]);\n    board[block[1] + y][block[0] + x] = 255;\n  }\n\n  // erase old\n  for (int i = 0; i < 4; i++)\n  {\n    byte* block = shape + (old.rot * 4 + i) * 2;\n\n    if (board[block[1] + old.y][block[0] + old.x] == 255)\n      continue;\n\n    boxb(BOARD_LEFT + block[0] * BLOCK_SIZE + BLOCK_SIZE * old.x,\n         BOARD_TOP + block[1] * BLOCK_SIZE + BLOCK_SIZE * old.y,\n         BLOCK_SIZE - 1,\n         BLOCK_SIZE - 1,\n         BG_COLOR);\n  }\n\n  for (int i = 0; i < 4; i++)\n  {\n    byte* block = shape + (rot * 4 + i) * 2;\n    board[block[1] + y][block[0] + x] = 0;\n  }\n\n  old.x = x;\n  old.y = y;\n  old.rot = rot;\n}\n\nint touches(int xi, int yi, int roti)\n{\n  byte* shape = all_shapes[current];\n  for (int i = 0; i < 4; i++)\n  {\n    byte* block = shape + (((rot + roti) % shapes[current]) * 4 + i) * 2;\n\n    int x2 = x + block[0] + xi;\n    int y2 = y + block[1] + yi;\n\n    if (y2 == BOARD_HEIGHT || x2 == BOARD_WIDTH || board[y2][x2])\n      return 1;\n  }\n  return 0;\n}\n\nvoid score(void)\n{\n  // we scan a max of 4 lines\n  int ll = y + 3; // BUG!!! was uninitialized\n  if (y + 3 >= BOARD_HEIGHT)\n    ll = BOARD_HEIGHT - 1;\n\n  // scan board from current position\n  for (int l = y; l <= ll; l++)\n  {\n    // check if there's a complete line on the board\n    int line = 1;\n    for (int c = 0; c < BOARD_WIDTH; c++)\n    {\n      if (board[l][c] == 0)\n      {\n        line = 0;\n        break;\n      }\n    }\n\n    if (!line)\n    {\n      // move to next line\n      continue;\n    }\n\n    beep(3000, 50);\n\n    lines++;\n\n    if (lines % 10 == 0)\n    {\n      level++;\n      dropWait /= 2;\n    }\n\n    scoreBoard();\n\n    // move board down\n    for (int row = l; row > 0; row --)\n    {\n      for (int c = 0; c < BOARD_WIDTH; c++)\n      {\n        byte v = board[row - 1][c];\n\n        board[row][c] = v;\n        boxb(BOARD_LEFT + BLOCK_SIZE * c,\n             BOARD_TOP + BLOCK_SIZE * row,\n             BLOCK_SIZE - 1,\n             BLOCK_SIZE - 1,\n             v == 0 ? BLACK : colors[v - 1]);\n      }\n    }\n\n    // clear top line\n    for (int c = 0; c < BOARD_WIDTH; c++)\n      board[0][c] = 0;\n\n    box(BOARD_LEFT,\n        0,\n        BOARD_RIGHT - BOARD_LEFT,\n        BLOCK_SIZE,\n        BLACK,\n        1);\n  }\n\n  delay(350);\n}\n\n// create a sequence of 7 random shapes\nvoid randomizer(void)\n{\n  // randomize 7 shapes\n\n  for (byte i = 0; i < 7; i ++)\n  {\n    int retry;\n    byte shape;\n    do\n    {\n      shape = rand() % 7;\n\n      // check if already in sequence\n\n      retry = 0;\n      for (int j = 0; j < i; j++)\n      {\n        if (shape == next[j])\n        {\n          retry = 1;\n          break;\n        }\n      }\n\n    } while (retry);\n    next[i] = shape;\n  }\n  next_c = 0;\n}\n\nvoid drawPreGameScreen(void)\n{\n  box(0, 0, LCD_WIDTH, LCD_HEIGHT, WHITE, 1);\n  drawCenteredString(\"Tetris\", 40, 8, BLUE);\n  drawCenteredString(\"Move joystick to start\", 110, 2, BLACK);\n  drawCenteredString(\"http://vilaca.eu\", 220, 2, PURPLE);\n}\n\nvoid gameOver(void)\n{\n  box(32, LCD_HEIGHT / 2 - 24, LCD_WIDTH - 64, 48, BLACK, 1);\n  drawCenteredString(\"Game Over\", LCD_HEIGHT / 2 - 16, 4, WHITE);\n  box(32, LCD_HEIGHT / 2 - 24, LCD_WIDTH - 64, 48, RED, 0);\n\n  beep(600, 200);\n  delay(300);\n  beep(600, 200);\n  delay(300);\n  beep(200, 600);\n  delay(1500);\n}\n\nunsigned char simpleFont[][8] =\n{\n  {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},\n  {0x00,0x00,0x5F,0x00,0x00,0x00,0x00,0x00},\n  {0x00,0x00,0x07,0x00,0x07,0x00,0x00,0x00},\n  {0x00,0x14,0x7F,0x14,0x7F,0x14,0x00,0x00},\n  {0x00,0x24,0x2A,0x7F,0x2A,0x12,0x00,0x00},\n  {0x00,0x23,0x13,0x08,0x64,0x62,0x00,0x00},\n  {0x00,0x36,0x49,0x55,0x22,0x50,0x00,0x00},\n  {0x00,0x00,0x05,0x03,0x00,0x00,0x00,0x00},\n  {0x00,0x1C,0x22,0x41,0x00,0x00,0x00,0x00},\n  {0x00,0x41,0x22,0x1C,0x00,0x00,0x00,0x00},\n  {0x00,0x08,0x2A,0x1C,0x2A,0x08,0x00,0x00},\n  {0x00,0x08,0x08,0x3E,0x08,0x08,0x00,0x00},\n  {0x00,0xA0,0x60,0x00,0x00,0x00,0x00,0x00},\n  {0x00,0x08,0x08,0x08,0x08,0x08,0x00,0x00},\n  {0x00,0x60,0x60,0x00,0x00,0x00,0x00,0x00},\n  {0x00,0x20,0x10,0x08,0x04,0x02,0x00,0x00},\n  {0x00,0x3E,0x51,0x49,0x45,0x3E,0x00,0x00},\n  {0x00,0x00,0x42,0x7F,0x40,0x00,0x00,0x00},\n  {0x00,0x62,0x51,0x49,0x49,0x46,0x00,0x00},\n  {0x00,0x22,0x41,0x49,0x49,0x36,0x00,0x00},\n  {0x00,0x18,0x14,0x12,0x7F,0x10,0x00,0x00},\n  {0x00,0x27,0x45,0x45,0x45,0x39,0x00,0x00},\n  {0x00,0x3C,0x4A,0x49,0x49,0x30,0x00,0x00},\n  {0x00,0x01,0x71,0x09,0x05,0x03,0x00,0x00},\n  {0x00,0x36,0x49,0x49,0x49,0x36,0x00,0x00},\n  {0x00,0x06,0x49,0x49,0x29,0x1E,0x00,0x00},\n  {0x00,0x00,0x36,0x36,0x00,0x00,0x00,0x00},\n  {0x00,0x00,0xAC,0x6C,0x00,0x00,0x00,0x00},\n  {0x00,0x08,0x14,0x22,0x41,0x00,0x00,0x00},\n  {0x00,0x14,0x14,0x14,0x14,0x14,0x00,0x00},\n  {0x00,0x41,0x22,0x14,0x08,0x00,0x00,0x00},\n  {0x00,0x02,0x01,0x51,0x09,0x06,0x00,0x00},\n  {0x00,0x32,0x49,0x79,0x41,0x3E,0x00,0x00},\n  {0x00,0x7E,0x09,0x09,0x09,0x7E,0x00,0x00},\n  {0x00,0x7F,0x49,0x49,0x49,0x36,0x00,0x00},\n  {0x00,0x3E,0x41,0x41,0x41,0x22,0x00,0x00},\n  {0x00,0x7F,0x41,0x41,0x22,0x1C,0x00,0x00},\n  {0x00,0x7F,0x49,0x49,0x49,0x41,0x00,0x00},\n  {0x00,0x7F,0x09,0x09,0x09,0x01,0x00,0x00},\n  {0x00,0x3E,0x41,0x41,0x51,0x72,0x00,0x00},\n  {0x00,0x7F,0x08,0x08,0x08,0x7F,0x00,0x00},\n  {0x00,0x41,0x7F,0x41,0x00,0x00,0x00,0x00},\n  {0x00,0x20,0x40,0x41,0x3F,0x01,0x00,0x00},\n  {0x00,0x7F,0x08,0x14,0x22,0x41,0x00,0x00},\n  {0x00,0x7F,0x40,0x40,0x40,0x40,0x00,0x00},\n  {0x00,0x7F,0x02,0x0C,0x02,0x7F,0x00,0x00},\n  {0x00,0x7F,0x04,0x08,0x10,0x7F,0x00,0x00},\n  {0x00,0x3E,0x41,0x41,0x41,0x3E,0x00,0x00},\n  {0x00,0x7F,0x09,0x09,0x09,0x06,0x00,0x00},\n  {0x00,0x3E,0x41,0x51,0x21,0x5E,0x00,0x00},\n  {0x00,0x7F,0x09,0x19,0x29,0x46,0x00,0x00},\n  {0x00,0x26,0x49,0x49,0x49,0x32,0x00,0x00},\n  {0x00,0x01,0x01,0x7F,0x01,0x01,0x00,0x00},\n  {0x00,0x3F,0x40,0x40,0x40,0x3F,0x00,0x00},\n  {0x00,0x1F,0x20,0x40,0x20,0x1F,0x00,0x00},\n  {0x00,0x3F,0x40,0x38,0x40,0x3F,0x00,0x00},\n  {0x00,0x63,0x14,0x08,0x14,0x63,0x00,0x00},\n  {0x00,0x03,0x04,0x78,0x04,0x03,0x00,0x00},\n  {0x00,0x61,0x51,0x49,0x45,0x43,0x00,0x00},\n  {0x00,0x7F,0x41,0x41,0x00,0x00,0x00,0x00},\n  {0x00,0x02,0x04,0x08,0x10,0x20,0x00,0x00},\n  {0x00,0x41,0x41,0x7F,0x00,0x00,0x00,0x00},\n  {0x00,0x04,0x02,0x01,0x02,0x04,0x00,0x00},\n  {0x00,0x80,0x80,0x80,0x80,0x80,0x00,0x00},\n  {0x00,0x01,0x02,0x04,0x00,0x00,0x00,0x00},\n  {0x00,0x20,0x54,0x54,0x54,0x78,0x00,0x00},\n  {0x00,0x7F,0x48,0x44,0x44,0x38,0x00,0x00},\n  {0x00,0x38,0x44,0x44,0x28,0x00,0x00,0x00},\n  {0x00,0x38,0x44,0x44,0x48,0x7F,0x00,0x00},\n  {0x00,0x38,0x54,0x54,0x54,0x18,0x00,0x00},\n  {0x00,0x08,0x7E,0x09,0x02,0x00,0x00,0x00},\n  {0x00,0x18,0xA4,0xA4,0xA4,0x7C,0x00,0x00},\n  {0x00,0x7F,0x08,0x04,0x04,0x78,0x00,0x00},\n  {0x00,0x00,0x7D,0x00,0x00,0x00,0x00,0x00},\n  {0x00,0x80,0x84,0x7D,0x00,0x00,0x00,0x00},\n  {0x00,0x7F,0x10,0x28,0x44,0x00,0x00,0x00},\n  {0x00,0x41,0x7F,0x40,0x00,0x00,0x00,0x00},\n  {0x00,0x7C,0x04,0x18,0x04,0x78,0x00,0x00},\n  {0x00,0x7C,0x08,0x04,0x7C,0x00,0x00,0x00},\n  {0x00,0x38,0x44,0x44,0x38,0x00,0x00,0x00},\n  {0x00,0xFC,0x24,0x24,0x18,0x00,0x00,0x00},\n  {0x00,0x18,0x24,0x24,0xFC,0x00,0x00,0x00},\n  {0x00,0x00,0x7C,0x08,0x04,0x00,0x00,0x00},\n  {0x00,0x48,0x54,0x54,0x24,0x00,0x00,0x00},\n  {0x00,0x04,0x7F,0x44,0x00,0x00,0x00,0x00},\n  {0x00,0x3C,0x40,0x40,0x7C,0x00,0x00,0x00},\n  {0x00,0x1C,0x20,0x40,0x20,0x1C,0x00,0x00},\n  {0x00,0x3C,0x40,0x30,0x40,0x3C,0x00,0x00},\n  {0x00,0x44,0x28,0x10,0x28,0x44,0x00,0x00},\n  {0x00,0x1C,0xA0,0xA0,0x7C,0x00,0x00,0x00},\n  {0x00,0x44,0x64,0x54,0x4C,0x44,0x00,0x00},\n  {0x00,0x08,0x36,0x41,0x00,0x00,0x00,0x00},\n  {0x00,0x00,0x7F,0x00,0x00,0x00,0x00,0x00},\n  {0x00,0x41,0x36,0x08,0x00,0x00,0x00,0x00},\n  {0x00,0x02,0x01,0x01,0x02,0x01,0x00,0x00},\n  {0x00,0x02,0x05,0x05,0x02,0x00,0x00,0x00}\n};\n\nint main(void)\n{\n  // get TFT display handle\n  if ((fd = open(\"/dev/tft0\", O_RDWR)) < 0)\n  {\n    perror(\"/dev/tft0\");\n    return 1;\n  }\n\n  // get joystick's x ADC handle\n  if ((fdx = open(\"/dev/adc0\", O_RDWR)) < 0)\n  {\n    perror(\"/dev/adc0\");\n    return 1;\n  }\n\n  // get joystick's y ADC handle\n  if ((fdy = open(\"/dev/adc1\", O_RDWR)) < 0)\n  {\n    perror(\"/dev/adc1\");\n    return 1;\n  }\n\n  srand(time(NULL));\n\n  drawPreGameScreen();\n  while (!Joystick_fire() && !Joystick_getY() && !Joystick_getX());\n\n  gameLoop();\n  gameOver();\n\n  while (!Joystick_fire() && !Joystick_getY() && !Joystick_getX());\n  box(0, 0, LCD_WIDTH, LCD_HEIGHT, BLACK, 1);\n}\n"
  },
  {
    "path": "share/examples/lex/Makefile",
    "content": "# Lex examples from the source tree:\n#\tawk, lex manpage example, cpp, and ccom.\n\nLEX=\tlex\nLFLAGS=\t-v\n\n# These files require at least 96Kbytes of User RAM.\nSRCS=\tawk.lx.l example.l scanner.l\n\n# These files require at least 120Kbytes of User RAM.\n#SRCS=\tscan.l\n\nall:\n\t-@for src in ${SRCS} ; do \\\n\t\techo \"Generating from: $$src\" ; \\\n\t\t${LEX} ${LFLAGS} $$src ; \\\n\tdone\n\nclean:\n\trm -f a.out [Ee]rrs *.core y.tab.[ch] lex.yy.c\n"
  },
  {
    "path": "share/examples/lex/awk.lx.l",
    "content": "/*\tawk.lx.l\t4.3\t84/12/08\t*/\n\n%Start A str chc sc reg comment\n\n%{\n#include\t\"awk.h\"\n#include\t\"awk.def.h\"\n#define YY_NO_INPUT\t/* defeat lex */\nextern int\tyylval;\nextern int\tmustfld;\n\nint\tlineno\t= 1;\n#define\tCADD\tcbuf[clen++]=yytext[0]; if(clen>=CBUFLEN-1) {yyerror(\"string too long\", cbuf); BEGIN A;}\n#define\tCBUFLEN\t150\nchar\tcbuf[CBUFLEN];\nint\tclen, cflag;\n%}\n\nA\t[a-zA-Z_]\nB\t[a-zA-Z0-9_]\nD\t[0-9]\nWS\t[ \\t]\n\n%%\n        /* witchcraft */\n        /* switch (yybgin-yysvec-1) {\n\tcase 0:\n\t\tBEGIN A;\n\t\tbreak;\n\tcase sc:\n\t\tBEGIN A;\n\t\treturn('}');\n\t} */\n\n<A>^\\n\t\tlineno++;\n<A>^{WS}*#.*\\n\tlineno++;\t/* strip comment lines */\n<A>{WS}\t\t;\n<A,reg>\"\\\\\"\\n\tlineno++;\n<A>\"||\"\t\treturn(BOR);\n<A>BEGIN\treturn(XBEGIN);\n<A>END\t\treturn(XEND);\n<A>PROGEND\treturn(EOF);\n<A>\"&&\"\t\treturn(AND);\n<A>\"!\"\t\treturn(NOT);\n<A>\"!=\"\t\t{ yylval = NE; return(RELOP); }\n<A>\"~\"\t\t{ yylval = MATCH; return(MATCHOP); }\n<A>\"!~\"\t\t{ yylval = NOTMATCH; return(MATCHOP); }\n<A>\"<\"\t\t{ yylval = LT; return(RELOP); }\n<A>\"<=\"\t\t{ yylval = LE; return(RELOP); }\n<A>\"==\"\t\t{ yylval = EQ; return(RELOP); }\n<A>\">=\"\t\t{ yylval = GE; return(RELOP); }\n<A>\">\"\t\t{ yylval = GT; return(RELOP); }\n<A>\">>\"\t\t{ yylval = APPEND; return(RELOP); }\n<A>\"++\"\t\t{ yylval = INCR; return(INCR); }\n<A>\"--\"\t\t{ yylval = DECR; return(DECR); }\n<A>\"+=\"\t\t{ yylval = ADDEQ; return(ASGNOP); }\n<A>\"-=\"\t\t{ yylval = SUBEQ; return(ASGNOP); }\n<A>\"*=\"\t\t{ yylval = MULTEQ; return(ASGNOP); }\n<A>\"/=\"\t\t{ yylval = DIVEQ; return(ASGNOP); }\n<A>\"%=\"\t\t{ yylval = MODEQ; return(ASGNOP); }\n<A>\"=\"\t\t{ yylval = ASSIGN; return(ASGNOP); }\n\n<A>\"$\"{D}+\t{\tif (atoi(yytext+1)==0) {\n\t\t\t\tyylval = (hack)lookup(\"$record\", symtab, 0);\n\t\t\t\treturn(STRING);\n\t\t\t} else {\n\t\t\t\tyylval = fieldadr(atoi(yytext+1));\n\t\t\t\treturn(FIELD);\n\t\t\t}\n\t\t}\n<A>\"$\"{WS}*\t{ return(INDIRECT); }\n<A>NF\t\t{ mustfld=1; yylval = (hack)setsymtab(yytext, EMPTY, 0.0, NUM, symtab); return(VAR); }\n<A>({D}+(\".\"?){D}*|\".\"{D}+)((e|E)(\"+\"|-)?{D}+)?\t{\n\t\tyylval = (hack)setsymtab(yytext, EMPTY, atof(yytext), CON|NUM, symtab); return(NUMBER); }\n<A>\"}\"{WS}*\\n\t{ BEGIN sc; lineno++; return(';'); }\n<A>\"}\"\t\t{ BEGIN sc; return(';'); }\n<A>;\\n\t\t{ lineno++; return(';'); }\n<A>\\n\t\t{ lineno++; return(NL); }\n<A>while\treturn(WHILE);\n<A>for\t\treturn(FOR);\n<A>if\t\treturn(IF);\n<A>else\t\treturn(ELSE);\n<A>next\t\treturn(NEXT);\n<A>exit\t\treturn(EXIT);\n<A>break\treturn(BREAK);\n<A>continue\treturn(CONTINUE);\n<A>print\t{ yylval = PRINT; return(PRINT); }\n<A>printf\t{ yylval = PRINTF; return(PRINTF); }\n<A>sprintf\t{ yylval = SPRINTF; return(SPRINTF); }\n<A>split\t{ yylval = SPLIT; return(SPLIT); }\n<A>substr\treturn(SUBSTR);\n<A>index\treturn(INDEX);\n<A>in\t\treturn(IN);\n<A>getline\treturn(GETLINE);\n<A>length\t{ yylval = FLENGTH; return(FNCN); }\n<A>log\t\t{ yylval = FLOG; return(FNCN); }\n<A>int\t\t{ yylval = FINT; return(FNCN); }\n<A>exp\t\t{ yylval = FEXP; return(FNCN); }\n<A>sqrt\t\t{ yylval = FSQRT; return(FNCN); }\n<A>{A}{B}*\t{ yylval = (hack)setsymtab(yytext, tostring(\"\"), 0.0, STR|NUM, symtab); return(VAR); }\n<A>\\\"\t\t{ BEGIN str; clen=0; }\n\n<A>#\t\t{ BEGIN comment; }\n<comment>\\n\t{ BEGIN A; lineno++; return(NL); }\n<comment>.\t;\n\n<A>.\t\t{ yylval = yytext[0]; return(yytext[0]); }\n\n<reg>\"[\"\t{ BEGIN chc; clen=0; cflag=0; }\n<reg>\"[^\"\t{ BEGIN chc; clen=0; cflag=1; }\n\n<reg>\"?\"\treturn(QUEST);\n<reg>\"+\"\treturn(PLUS);\n<reg>\"*\"\treturn(STAR);\n<reg>\"|\"\treturn(OR);\n<reg>\".\"\treturn(DOT);\n<reg>\"(\"\treturn('(');\n<reg>\")\"\treturn(')');\n<reg>\"^\"\treturn('^');\n<reg>\"$\"\treturn('$');\n<reg>\\\\{D}{D}{D}\t{ sscanf(yytext+1, \"%o\", &yylval); return(CHAR); }\n<reg>\\\\.\t{\tif (yytext[1]=='n') yylval = '\\n';\n\t\t\telse if (yytext[1] == 't') yylval = '\\t';\n\t\t\telse yylval = yytext[1];\n\t\t\treturn(CHAR);\n\t\t}\n<reg>\"/\"\t{ BEGIN A; unput('/'); }\n<reg>\\n\t\t{ yyerror(\"newline in regular expression\"); lineno++; BEGIN A; }\n<reg>.\t\t{ yylval = yytext[0]; return(CHAR); }\n\n<str>\\\"\t\t{ char *s; BEGIN A; cbuf[clen]=0; s = tostring(cbuf);\n\t\tcbuf[clen] = ' '; cbuf[++clen] = 0;\n\t\tyylval = (hack)setsymtab(cbuf, s, 0.0, CON|STR, symtab); return(STRING); }\n<str>\\n\t\t{ yyerror(\"newline in string\"); lineno++; BEGIN A; }\n<str>\"\\\\\\\"\"\t{ cbuf[clen++]='\"'; }\n<str,chc>\"\\\\\"n\t{ cbuf[clen++]='\\n'; }\n<str,chc>\"\\\\\"t\t{ cbuf[clen++]='\\t'; }\n<str,chc>\"\\\\\\\\\"\t{ cbuf[clen++]='\\\\'; }\n<str>.\t\t{ CADD; }\n\n<chc>\"\\\\\"\"]\"\t{ cbuf[clen++]=']'; }\n<chc>\"]\"\t{ BEGIN reg; cbuf[clen]=0; yylval = (hack)tostring(cbuf);\n\t\tif (cflag==0) { return(CCL); }\n\t\telse { return(NCCL); } }\n<chc>\\n\t\t{ yyerror(\"newline in character class\"); lineno++; BEGIN A; }\n<chc>.\t\t{ CADD; }\n\n%%\n\ninput()\n{\n\tregister c;\n\textern char *lexprog;\n\n\tif (yyin == NULL)\n\t\tc = *lexprog++;\n\telse\n\t\tc = getc(yyin);\n\tif (c == '\\n')\n\t\tyylineno++;\n\telse if (c == EOF)\n\t\tc = 0;\n\treturn(c);\n}\n\nstartreg()\n{\n\tBEGIN reg;\n}\n"
  },
  {
    "path": "share/examples/lex/example.l",
    "content": "%%\n[A-Z] putchar(yytext[0]+'a'-'A');\n[ ]+$ ;\n[ ]+  putchar(' ');\n"
  },
  {
    "path": "share/examples/lex/scan.l",
    "content": "%{\n/*\n * Copyright (c) 2002 Anders Magnusson. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. The name of the author may not be used to endorse or promote products\n *    derived from this software without specific prior written permission\n *\n * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\n * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\n * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\n * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\n * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#ifdef CROSS\n#   include </usr/include/stdio.h>\n#   include </usr/include/errno.h>\n#else\n#   include <stdio.h>\n#   include <errno.h>\n#endif\n#include <stdlib.h>\n#include <string.h>\n#include <stdarg.h>\n\n#include \"pass1.h\"\n#include \"cgram.h\"\n%}\n\n\nD\t\t\t[0-9]\nL\t\t\t[a-zA-Z_]\nH\t\t\t[a-fA-F0-9]\nE\t\t\t[Ee][+-]?{D}+\nP\t\t\t[Pp][+-]?{D}+\nFS\t\t\t(f|F|l|L)?i?\nIS\t\t\t(u|U|l|L)*\nUL\t\t\t({L}|\\\\u{H}{H}{H}{H}|\\\\U{H}{H}{H}{H}{H}{H}{H}{H})\n\n%{\nstatic NODE *cvtdig(int radix);\nstatic NODE *charcon(void);\nstatic NODE *wcharcon(void);\nstatic void control(int);\nstatic void pragma(void);\nint notype, parbal, inattr, parlvl;\nstatic int resw(TWORD, int);\n\n#define\tCPP_IDENT \t2\n#define\tCPP_LINE \t3\n#define\tCPP_HASH\t4\n\n#ifdef STABS\n#   define STABS_LINE(x) if (gflag && cftnsp) stabs_line(x)\n#else\n#   define STABS_LINE(x)\n#endif\n#if defined(FLEX_SCANNER) && YY_FLEX_SUBMINOR_VERSION == 31\n/* Hack to avoid unnecessary warnings */\nFILE *yyget_in  (void);\nFILE *yyget_out  (void);\nint yyget_leng  (void);\nchar *yyget_text  (void);\nvoid yyset_in (FILE *);\nvoid yyset_out (FILE *);\nint yyget_debug  (void);\nvoid yyset_debug (int);\nint yylex_destroy  (void);\nextern int yyget_lineno (void);\nextern void yyset_lineno (int);\n#endif\n%}\n\n%%\n\n\"__func__\"\t\t{\n\t\t\t\tif (cftnsp == NULL)\n\t\t\t\t\tuerror(\"__func__ outside function\");\n\t\t\t\tyylval.strp = cftnsp->sname; /* XXX - not C99 */\n\t\t\t\treturn(C_STRING);\n\t\t\t}\n\"asm\"\t\t\t{ return(C_ASM); }\n\"auto\"\t\t\t{ \treturn resw(AUTO, C_CLASS); }\n\"_Bool\"\t\t\t{ \treturn resw(BOOL, C_TYPE); }\n\"break\"\t\t\t{ return(C_BREAK); }\n\"case\"\t\t\t{ return(C_CASE); }\n\"char\"\t\t\t{ \treturn resw(CHAR, C_TYPE); }\n\"_Complex\"\t\t{ \treturn resw(COMPLEX, C_TYPE); }\n\"const\"\t\t\t{ \treturn resw(CON, C_QUALIFIER); }\n\"continue\"\t\t{ return(C_CONTINUE); }\n\"default\"\t\t{ return(C_DEFAULT); }\n\"do\"\t\t\t{ return(C_DO); }\n\"double\"\t\t{ \treturn resw(DOUBLE, C_TYPE); }\n\"else\"\t\t\t{ return(C_ELSE); }\n\"enum\"\t\t\t{ notype=1; return(C_ENUM); }\n\"extern\"\t\t{ \treturn resw(EXTERN, C_CLASS); }\n\"float\"\t\t\t{ \treturn resw(FLOAT, C_TYPE); }\n\"for\"\t\t\t{ return(C_FOR); }\n\"goto\"\t\t\t{ notype=1; return(C_GOTO); }\n\"if\"\t\t\t{ return(C_IF); }\n\"_Imaginary\"\t\t{ \treturn resw(IMAG, C_TYPE); }\n\"inline\"\t\t{ return(C_FUNSPEC); }\n\"int\"\t\t\t{ \treturn resw(INT, C_TYPE); }\n\"long\"\t\t\t{ \treturn resw(LONG, C_TYPE); }\n\"register\"\t\t{ \treturn resw(REGISTER, C_CLASS); }\n\"restrict\"\t\t{ ; /* just ignore */ }\n\"return\"\t\t{ return(C_RETURN); }\n\"short\"\t\t\t{ \treturn resw(SHORT, C_TYPE); }\n\"signed\"\t\t{ \treturn resw(SIGNED, C_TYPE); }\n\"sizeof\"\t\t{ return(C_SIZEOF); }\n\"static\"\t\t{ \treturn resw(STATIC, C_CLASS); }\n\"struct\"\t\t{ yylval.intval = STNAME; notype=1; return(C_STRUCT); }\n\"switch\"\t\t{ return(C_SWITCH); }\n\"typedef\"\t\t{ \treturn resw(TYPEDEF, C_CLASS); }\n\"union\"\t\t\t{ yylval.intval = UNAME; notype=1; return(C_STRUCT); }\n\"unsigned\"\t\t{ \treturn resw(UNSIGNED, C_TYPE); }\n\"void\"\t\t\t{ \treturn resw(VOID, C_TYPE); }\n\"volatile\"\t\t{\treturn resw(VOL, C_QUALIFIER); }\n\"while\"\t\t\t{ return(C_WHILE); }\n\n{UL}({UL}|{D})*\t{ \tstruct symtab *s;\n\t\t\tint i = 0;\n\n\t\t\tyylval.strp = addname(yytext);\n#ifdef GCC_COMPAT\n\t\t\tif ((i = gcc_keyword(yylval.strp, &yylval.nodep)) > 0)\n\t\t\t\treturn i;\n#endif\n\t\t\tif (i == 0) {\n\t\t\t\tif (notype)\n\t\t\t\t\treturn(C_NAME);\n\t\t\t\ts = lookup(yylval.strp, SNOCREAT);\n\t\t\t\treturn s && s->sclass == TYPEDEF ?\n\t\t\t\t    notype=1, C_TYPENAME : C_NAME;\n\t\t\t}\n\t\t}\n\n0[xX]{H}+{IS}?\t\t{ yylval.nodep = cvtdig(16); return(C_ICON); }\n0{D}+{IS}?\t\t{ yylval.nodep = cvtdig(8); return(C_ICON); }\n{D}+{IS}?\t\t{ yylval.nodep = cvtdig(10); return(C_ICON); }\nL'(\\\\.|[^\\\\'])+'\t{ yylval.nodep = wcharcon(); return(C_ICON); }\n'(\\\\.|[^\\\\'])+'\t\t{ yylval.nodep = charcon(); return(C_ICON); }\n\n{D}+{E}{FS}?\t\t{ yylval.nodep = floatcon(yytext); return(C_FCON); }\n{D}*\".\"{D}+({E})?{FS}?\t{ yylval.nodep = floatcon(yytext); return(C_FCON); }\n{D}+\".\"{D}*({E})?{FS}?\t{ yylval.nodep = floatcon(yytext); return(C_FCON); }\n0[xX]{H}*\".\"{H}+{P}{FS}? { yylval.nodep = fhexcon(yytext); return(C_FCON); }\n0[xX]{H}+\".\"{P}{FS}?\t{ yylval.nodep = fhexcon(yytext); return(C_FCON); }\n0[xX]{H}+{P}{FS}?\t{ yylval.nodep = fhexcon(yytext); return(C_FCON); }\n\nL?\\\"(\\\\.|[^\\\\\"])*\\\"\t{ yylval.strp = yytext; return C_STRING; }\n\n\"...\"\t\t\t{ return(C_ELLIPSIS); }\n\">>=\"\t\t\t{ yylval.intval = RSEQ; return(C_ASOP); }\n\"<<=\"\t\t\t{ yylval.intval = LSEQ; return(C_ASOP); }\n\"+=\"\t\t\t{ yylval.intval = PLUSEQ; return(C_ASOP); }\n\"-=\"\t\t\t{ yylval.intval = MINUSEQ; return(C_ASOP); }\n\"*=\"\t\t\t{ yylval.intval = MULEQ; return(C_ASOP); }\n\"/=\"\t\t\t{ yylval.intval = DIVEQ; return(C_ASOP); }\n\"%=\"\t\t\t{ yylval.intval = MODEQ; return(C_ASOP); }\n\"&=\"\t\t\t{ yylval.intval = ANDEQ; return(C_ASOP); }\n\"^=\"\t\t\t{ yylval.intval = EREQ; return(C_ASOP); }\n\"|=\"\t\t\t{ yylval.intval = OREQ; return(C_ASOP); }\n\">>\"\t\t\t{ yylval.intval = RS; return(C_SHIFTOP); }\n\"<<\"\t\t\t{ yylval.intval = LS; return(C_SHIFTOP); }\n\"++\"\t\t\t{ yylval.intval = INCR; return(C_INCOP); }\n\"--\"\t\t\t{ yylval.intval = DECR; return(C_INCOP); }\n\"->\"\t\t\t{ yylval.intval = STREF; return(C_STROP); }\n\"&&\"\t\t\t{ yylval.intval = ANDAND; return(C_ANDAND); }\n\"||\"\t\t\t{ yylval.intval = OROR; return(C_OROR); }\n\"<=\"\t\t\t{ yylval.intval = LE; return(C_RELOP); }\n\">=\"\t\t\t{ yylval.intval = GE; return(C_RELOP); }\n\"==\"\t\t\t{ yylval.intval = EQ; return(C_EQUOP); }\n\"!=\"\t\t\t{ yylval.intval = NE; return(C_EQUOP); }\n\";\"\t\t\t{ notype = 0; return(';'); }\n(\"{\"|\"<%\")\t\t{ notype = 0; return('{'); }\n(\"}\"|\"%>\")\t\t{ if (rpole) notype = 1; return('}'); }\n\",\"\t\t\t{ if (parbal) notype = 0; return(','); }\n\":\"\t\t\t{ return(':'); }\n\"=\"\t\t\t{ return('='); }\n\"(\"\t\t\t{ parbal++; notype = 0; return('('); }\n\")\"\t\t\t{\tparbal--;\n\t\t\t\tif (parbal==0) { notype = 0; }\n\t\t\t\tif (inattr && parlvl == parbal)\n\t\t\t\t\tinattr = 0;\n\t\t\t\treturn(')'); }\n(\"[\"|\"<:\")\t\t{ return('['); }\n(\"]\"|\":>\")\t\t{ return(']'); }\n\".\"\t\t\t{ yylval.intval = DOT; return(C_STROP); }\n\"&\"\t\t\t{ return('&'); }\n\"!\"\t\t\t{ yylval.intval = NOT; return(C_UNOP); }\n\"~\"\t\t\t{ yylval.intval = COMPL; return(C_UNOP); }\n\"-\"\t\t\t{ return('-'); }\n\"+\"\t\t\t{ return('+'); }\n\"*\"\t\t\t{ if (parbal && notype == 0) notype = 1; return('*'); }\n\"/\"\t\t\t{ yylval.intval = DIV; return(C_DIVOP); }\n\"%\"\t\t\t{ yylval.intval = MOD; return(C_DIVOP); }\n\"<\"\t\t\t{ yylval.intval = LT; return(C_RELOP); }\n\">\"\t\t\t{ yylval.intval = GT; return(C_RELOP); }\n\"^\"\t\t\t{ return('^'); }\n\"|\"\t\t\t{ return('|'); }\n\"?\"\t\t\t{ return('?'); }\n^#pragma[ \\t].*\t\t{ pragma(); }\n^#ident[ \\t].*\t\t{ control(CPP_IDENT); }\n^#line[ \\t].*\t\t{ control(CPP_LINE); }\n^#.*\t\t\t{ control(CPP_HASH); }\n\n[ \\t\\v\\f]\t\t{ }\n\"\\n\"\t\t\t{ ++lineno; STABS_LINE(lineno); }\n.\t\t\t{ /* ignore bad characters */ }\n\n%%\n\nint lineno;\nchar *ftitle = \"<stdin>\";\n\nint\nyywrap(void)\n{\n\tif (0) unput(0); /* quiet gcc */\n\treturn(1);\n}\n\nint\nresw(TWORD t, int rv)\n{\n\tif (inattr) {\n\t\tyylval.strp = addname(yytext);\n\t\treturn C_NAME;\n\t}\n\n\tswitch (rv) {\n\tcase C_CLASS:\n\t\tyylval.nodep = block(CLASS, NIL, NIL, t, 0, 0);\n\t\treturn rv;\n\n\tcase C_QUALIFIER:\n\t\tyylval.nodep = block(QUALIFIER, NIL, NIL, 0, 0, 0);\n\t\tyylval.nodep->n_qual = t;\n\t\treturn rv;\n\n\tcase C_TYPE:\n\t\tyylval.nodep = mkty(t, 0, MKAP(t));\n\t\tnotype=1;\n\t\treturn(rv);\n\n\tdefault:\n\t\tcerror(\"resw\");\n\t}\n\treturn 0;\n}\n\n#ifndef SOFTFLOAT\n/*\n * XXX floatcon() and fhexcon() should be in support libraries for\n * the target floating point.\n */\nstatic NODE *\nf2(char *str)\n{\n\tTWORD tw;\n\tNODE *p;\n\tlong double dc;\n\tchar *eptr;\n\tint imag = 0;\n\n#ifdef HAVE_STRTOLD\n\tdc = strtold(str, &eptr); /* XXX - avoid strtod() */\n#else\n\tdc = strtod(str, &eptr); /* XXX - avoid strtod() */\n#endif\n\ttw = DOUBLE;\n\tfor (; *eptr; eptr++) {\n\t\tswitch (*eptr) {\n\t\tcase 'f':\n\t\tcase 'F':\n\t\t\ttw = FLOAT;\n\t\t\tdc = (float)dc;\n\t\t\tbreak;\n\t\tcase 'l':\n\t\tcase 'L':\n\t\t\ttw = LDOUBLE;\n\t\t\tbreak;\n\t\tcase 'i':\n\t\tcase 'I':\n\t\t\timag = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (tw == DOUBLE)\n\t\tdc = (double)dc;\n#ifndef NO_COMPLEX\n\tif (imag)\n\t\ttw += (FIMAG-FLOAT);\n#endif\n\tp = block(FCON, NIL, NIL, tw, 0, MKAP(tw));\n\tp->n_dcon = dc;\n\treturn p;\n}\n\nNODE *\nfloatcon(char *s)\n{\n\treturn f2(s);\n}\n\nstatic int\nh2n(int ch)\n{\n\tif (ch >= '0' && ch <= '9')\n\t\treturn ch - '0';\n\tif (ch >= 'a' && ch <= 'f')\n\t\treturn ch - 'a' + 10;\n\treturn ch - 'A' + 10;\n\n}\n\nNODE *\nfhexcon(char *c)\n{\n\tchar buf[500];\n\tunsigned long long num1, num2;\n\n\t/* XXX - convert it to a decimal float number and use strtod */\n\tc+= 2; /* skip 0x */\n\tfor (num1 = 0; *c != '.' && *c != 'p' && *c != 'P'; c++)\n\t\tnum1 = (num1 << 4) | h2n(*c);\n\tif (*c != '.' && *c != 'p' && *c != 'P')\n\t\tcerror(\"fhexcon\");\n\tnum2 = 0;\n\tif (*c == '.') {\n\t\tc++;\n\t\tfor (; *c != 'p' && *c != 'P'; c++)\n\t\t\tnum2 = (num2 << 4) | h2n(*c);\n\t}\n\tif (*c != 'P' && *c != 'p')\n\t\tcerror(\"fhexcon2\");\n\tc++;\n\tsnprintf(buf, sizeof(buf), \"%llu.%lluE%s\", num1, num2, c);\n\treturn f2(buf);\n}\n#endif\n\nunsigned int\nesccon(char **sptr)\n{\n\tchar *wr = *sptr;\n\tchar *owr;\n\tchar c;\n\tunsigned int val;\n\tint wsz = 4, esccon_warn = 1;\n\n\tswitch (*wr++) {\n\tcase 'a': val = '\\a'; break;\n\tcase 'b': val = '\\b'; break;\n\tcase 'f': val = '\\f'; break;\n\tcase 'n': val = '\\n'; break;\n\tcase 'r': val = '\\r'; break;\n\tcase 't': val = '\\t'; break;\n\tcase 'v': val = '\\v'; break;\n\tcase '\\\"': val = '\\\"'; break;\n\tcase 'x': val = strtoul(wr, &wr, 16); break;\n\t/* ISO/IEC 9099:1999 (E) 6.4.3 */\n\tcase 'U'|(char)0x80:\n\t\tesccon_warn = 0;\n\t\t/* FALLTHROUGH */\n\tcase 'U':\n\t\twsz = 8;\n\t\t/* FALLTHROUGH */\n\tcase 'u':\n\t\towr = wr;\n\t\twhile (wr < (owr + wsz))\n\t\t\tif (*wr == '\\0')\n\t\t\t\tbreak;\n\t\t\telse\n\t\t\t\t++wr;\n\t\tif (wr != (owr + wsz)) {\n\t\t\t/* incomplete */\n\t\t\tval = strtoul(owr, &wr, 16);\n\t\t} else {\n\t\t\tc = owr[wsz];\n\t\t\towr[wsz] = '\\0'; /* prevent it from reading too much */\n\t\t\tval = strtoul(owr, &wr, 16);\n\t\t\towr[wsz] = c;\n\t\t}\n\t\tif (wr != (owr + wsz))\n\t\t\twerror(\"incomplete universal character name\");\n\t\tif (wsz == 4)\n\t\t\tval &= 0xFFFF;\n\t\tif (esccon_warn && ((val >= 0xD800 && val <= 0xDFFF) ||\n\t\t    (val < 0xA0 && val != 0x24 && val != 0x40 && val != 0x60)))\n\t\t\twerror(\"invalid universal character name %04X\", val);\n\t\tbreak;\n\tcase '0': case '1': case '2': case '3': case '4':\n\tcase '5': case '6': case '7':\n\t\tval = wr[-1] - '0';\n\t\tif (*wr >= '0' && *wr <= '7') {\n\t\t\tval = (val << 3) + (*wr++ - '0');\n\t\t\tif (*wr >= '0' && *wr <= '7')\n\t\t\t\tval = (val << 3) + (*wr++ - '0');\n\t\t}\n\t\tbreak;\n\tdefault: val = wr[-1];\n\t}\n\t*sptr = wr;\n\treturn val;\n}\n\nNODE *\ncvtdig(int radix)\n{\n\tNODE *p;\n\tTWORD ntype;\n\tunsigned long long v;\n\tchar *ch = yytext;\n\tint n, numl, numu;\n\n\tif (radix == 16)\n\t\tch += 2; /* Skip 0x */\n\n\tv = 0;\n\twhile ((*ch >= '0' && *ch <= '9') || (*ch >= 'a' && *ch <= 'f') ||\n\t    (*ch >= 'A' && *ch <= 'F')) {\n\t\tv *= radix;\n\t\tn = *ch;\n\t\tn = (n <= '9' ? n - '0' : (n > 'F' ? n - 'a' : n - 'A') + 10);\n\t\tch++;\n\t\tv += n;\n\t}\n\t/* Parse trailing chars */\n\tntype = INT;\n\tnuml = numu = 0;\n\tfor (n = 0; n < 3; n++) {\n\t\tif (*ch == 0)\n\t\t\tbreak;\n\t\tif ((*ch == 'l' || *ch == 'L') && numl < 2)\n\t\t\tntype+=2, numl++;\n\t\telse if ((*ch == 'u' || *ch == 'U') && numu < 1)\n\t\t\tntype = ENUNSIGN(ntype), numu++;\n\t\telse\n\t\t\tbreak;\n\t\tch++;\n\t}\n\tif (*ch)\n\t\tuerror(\"constant has too many '%c'\", *ch);\n\n\tif (ntype == INT) {\n\t\t/* v contains a number. Get type correct */\n\t\tif (v > MAX_LONGLONG && radix != 10)\n\t\t\tntype = ULONGLONG;\n\t\telse if (v > MAX_ULONG)\n\t\t\tntype = LONGLONG;\n\t\telse if (v > MAX_LONG && radix != 10)\n\t\t\tntype = ULONG;\n\t\telse if (v > MAX_UNSIGNED)\n\t\t\tntype = LONG;\n\t\telse if (v > MAX_INT && radix != 10)\n\t\t\tntype = UNSIGNED;\n\t}\n\tntype = ctype(ntype);\n\tp = xbcon(v, NULL, ntype);\n\tASGLVAL(p->n_slval, v);\n\n\treturn p;\n}\n\n/*\n * Convert a character constant to an integer.\n */\nNODE *\ncharcon(void)\n{\n\tint lastcon = 0;\n\tint val, i = 0;\n\tchar *pp = yytext;\n\n\tif (*pp == 'L')\n\t\tpp++;\n\tpp++;\n\twhile (*pp != '\\'') {\n\t\tif (*pp++ == '\\\\') {\n\t\t\tval = esccon(&pp);\n\t\t} else\n\t\t\tval = pp[-1];\n\t\tmakecc(val, i);\n\t\ti++;\n\t}\n\n\tif (i == 0)\n\t\tuerror(\"empty character constant\");\n\tif (i > (SZINT/SZCHAR) || (i>1))\n\t\twerror(\"too many characters in character constant\");\n\treturn bcon(lastcon);\n}\n\nNODE *\nwcharcon(void)\n{\n\tunsigned int lastcon = 0;\n\tunsigned int val, i = 0;\n\tchar *pp = yytext;\n\n\tif (*pp == 'L')\n\t\tpp++;\n\tpp++;\n\twhile (*pp != '\\'') {\n\t\tif (*pp++ == '\\\\') {\n\t\t\tval = esccon(&pp);\n\t\t} else\n\t\t\tval = pp[-1];\n#if WCHAR_SIZE == 2\n\t\tlastcon = (lastcon << 16) | (val & 0xFFFF);\n#else\n\t\tlastcon = val;\n#endif\n\t\ti++;\n\t}\n\n\tif (i == 0)\n\t\tuerror(\"empty wide character constant\");\n\tif (i > 1)\n\t\twerror(\"too many characters in wide character constant\");\n\treturn xbcon(lastcon, NULL, ctype(UNSIGNED));\n}\n\nvoid\ncontrol(int t)\n{\n\tchar *wr = yytext;\n\tchar *eptr;\n\tint val;\n\n\twr++;\t/* Skip initial '#' */\n\tswitch (t) {\n\tcase CPP_IDENT:\n\t\treturn;\t/* Just skip these for now. */\n\n\tcase CPP_LINE:\n\t\twr += 4;\n\t\t/* FALLTHROUGH */\n\tcase CPP_HASH:\n\t\tval = strtol(wr, &eptr, 10);\n\t\tif (wr == eptr)\t/* Illegal string */\n\t\t\tgoto bad;\n\t\twr = eptr;\n\t\tlineno = val - 1;\n\t\twhile (*wr && *wr != '\\\"')\n\t\t\twr++;\n\t\tif (*wr == 0)\n\t\t\treturn;\n\t\tif (*wr++ != '\\\"')\n\t\t\tgoto bad;\n\t\teptr = wr;\n\t\twhile (*wr && *wr != '\\\"')\n\t\t\twr++;\n\t\tif (*wr != '\\\"')\n\t\t\tgoto bad;\n\t\t*wr = 0;\n\t\tftitle = addstring(eptr);\n#ifdef STABS\n\t\tif (gflag)\n\t\t\tstabs_file(ftitle);\n#endif\n\t}\n\treturn;\nbad:\n\twerror(\"%s: illegal control\", yytext);\n}\n\n/*\n * split a pragma string in parts.\n */\nstatic char **\nsplitup(char *str)\n{\n\tchar *s, **ary;\n\tint i;\n\n\t/* count ws. at least needed array size, add 2 to terminate */\n\tfor (i = 2, s = str; *s; s++)\n\t\tif (*s == ' ' || *s == '\\t' ||\n\t\t    *s == '(' || *s == ')' || *s == ',')\n\t\t\ti++;\n\tary = tmpalloc(sizeof(char *)*i);\n\tfor (i = 0, s = strtok(str, \" \\t(,)\"); s; s = strtok(NULL, \" \\t(,)\"))\n\t\tary[i++] = s;\n\tary[i] = NULL;\n\treturn ary;\n}\n\nint pragma_allpacked;\nint pragma_packed, pragma_aligned;\nchar *pragma_renamed;\n\n/*\n * got a full pragma line.  Split it up here.\n */\nstatic void\npragma()\n{\n\tchar **ary;\n\n\tary = splitup(yytext);\n\tif (ary[1] == NULL)\n\t\tgoto bad;\n\tif (strcmp(ary[1], \"pack\") == 0) {\n\t\tpragma_allpacked = ary[2] ? atoi(ary[2]) : 0;\n\t} else if (strcmp(ary[1], \"packed\") == 0) {\n\t\tpragma_packed = ary[2] ? atoi(ary[2]) : 1;\n\t} else if (strcmp(ary[1], \"aligned\") == 0) {\n\t\tpragma_aligned = ary[2] ? atoi(ary[2]) : 1;\n\t} else if (strcmp(ary[1], \"rename\") == 0) {\n\t\tpragma_renamed = newstring(ary[2], strlen(ary[2]));\n\t} else if (strcmp(ary[1], \"GCC\") == 0) {\n\t\t/* pragma_gcc(); Ignored for now */\n\t} else if (strcmp(ary[1], \"weak\") == 0) {\n\t\tstruct symtab *sp = lookup(addname(ary[2]), SNORMAL);\n\t\tsp->sap =\n\t\t    attr_add(sp->sap, gcc_attr_parse(bdty(NAME, \"weak\")));\n\t\tif (ary[3])\n\t\t\tuerror(\"too many arguments to #pragma weak\");\n\t} else if (mypragma(ary)) {\n\t\treturn;\n\t} else {\nbad:\n\t\tif (Wunknown_pragmas)\n\t\t\twerror(\"unknown pragma\");\n\t}\n}\n\nvoid\ncunput(char c)\n{\n\tunput(c);\n}\n"
  },
  {
    "path": "share/examples/lex/scanner.l",
    "content": "%{\n/*\t$Id: scanner.l,v 1.49 2009/02/14 09:23:55 ragge Exp $   */\n\n/*\n * Copyright (c) 2004 Anders Magnusson. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. The name of the author may not be used to endorse or promote products\n *    derived from this software without specific prior written permission\n *\n * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\n * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\n * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\n * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\n * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"config.h\"\n\n#include <stdlib.h>\n#include <string.h>\n#include <ctype.h>\n#ifdef HAVE_UNISTD_H\n#include <unistd.h>\n#endif\n#include <fcntl.h>\n#include <errno.h>\n\n#include \"compat.h\"\n#include \"cpp.h\"\n#include \"y.tab.h\"\n%}\n\n%{\nstatic void cvtdig(int rad);\nstatic int charcon(usch *);\nstatic void elsestmt(void);\nstatic void ifdefstmt(void);\nstatic void ifndefstmt(void);\nstatic void endifstmt(void);\nstatic void ifstmt(void);\nstatic void cpperror(void);\nstatic void pragmastmt(void);\nstatic void undefstmt(void);\nstatic void cpperror(void);\nstatic void elifstmt(void);\nstatic void storepb(void);\nstatic void badop(const char *);\nvoid  include(void);\nvoid  define(void);\n\nextern int yyget_lineno (void);\nextern void yyset_lineno (int);\n\nstatic int inch(void);\n\nstatic int scale, gotdef, contr;\nint inif;\n\n#ifdef FLEX_SCANNER /* should be set by autoconf instead */\nstatic int\nyyinput(char *b, int m)\n{\n\tint c, i;\n\n\tfor (i = 0; i < m; i++) {\n\t\tif ((c = inch()) < 0)\n\t\t\tbreak;\n\t\t*b++ = c;\n\t\tif (c == '\\n') {\n\t\t\ti++;\n\t\t\tbreak;\n\t\t}\n\t}\n\treturn i;\n}\n#undef YY_INPUT\n#undef YY_BUF_SIZE\n#define\tYY_BUF_SIZE (8*65536)\n#define YY_INPUT(b,r,m) (r = yyinput(b, m))\n#ifdef HAVE_CPP_VARARG_MACRO_GCC\n#define fprintf(x, ...) error(__VA_ARGS__)\n#endif\n#define\tECHO putstr((usch *)yytext)\n#undef fileno\n#define fileno(x) 0\n\n#if YY_FLEX_SUBMINOR_VERSION >= 31\n/* Hack to avoid unnecessary warnings */\nFILE *yyget_in\t(void);\nFILE *yyget_out  (void);\nint yyget_leng\t(void);\nchar *yyget_text  (void);\nvoid yyset_in (FILE *  in_str );\nvoid yyset_out (FILE *\tout_str );\nint yyget_debug  (void);\nvoid yyset_debug (int  bdebug );\nint yylex_destroy  (void);\n#endif\n#else\t/* Assume lex here */\n#undef input\n#undef unput\n#define input() inch()\n#define unput(ch) unch(ch)\n#endif\n#define PRTOUT(x) if (YYSTATE || slow) return x; if (!flslvl) putstr((usch *)yytext);\n/* protection against recursion in #include */\n#define MAX_INCLEVEL\t100\nstatic int inclevel;\n%}\n\nD\t[0-9]\nL\t[a-zA-Z_]\nH\t[a-fA-F0-9]\nE\t[Ee][+-]?{D}+\nFS\t(f|F|l|L)\nIS\t(u|U|l|L)*\nWS\t[\\t ]\n\n%s IFR CONTR DEF COMMENT\n\n%%\n\n\"\\n\"\t\t\t{\tint os = YYSTATE;\n\t\t\t\tif (os != IFR)\n\t\t\t\t\tBEGIN 0;\n\t\t\t\tifiles->lineno++;\n\t\t\t\tif (flslvl == 0) {\n\t\t\t\t\tif (ifiles->lineno == 1)\n\t\t\t\t\t\tprtline();\n\t\t\t\t\telse\n\t\t\t\t\t\tputch('\\n');\n\t\t\t\t}\n\t\t\t\tif ((os != 0 || slow) && !contr)\n\t\t\t\t\treturn '\\n';\n\t\t\t\tcontr = 0;\n\t\t\t}\n\n\"\\r\"\t\t\t{ ; /* Ignore CR's */ }\n\n<IFR>\"++\"\t\t{ badop(\"++\"); }\n<IFR>\"--\"\t\t{ badop(\"--\"); }\n<IFR>\"==\"\t\t{ return EQ; }\n<IFR>\"!=\"\t\t{ return NE; }\n<IFR>\"<=\"\t\t{ return LE; }\n<IFR>\"<<\"\t\t{ return LS; }\n<IFR>\">>\"\t\t{ return RS; }\n<IFR>\">=\"\t\t{ return GE; }\n<IFR>\"||\"\t\t{ return OROR; }\n<IFR>\"&&\"\t\t{ return ANDAND; }\n<IFR>\"defined\"\t\t{\tint p, c;\n\t\t\t\tgotdef = 1;\n\t\t\t\tif ((p = c = yylex()) == '(')\n\t\t\t\t\tc = yylex();\n\t\t\t\tif (c != IDENT || (p != IDENT && p != '('))\n\t\t\t\t\terror(\"syntax error\");\n\t\t\t\tif (p == '(' && yylex() != ')')\n\t\t\t\t\terror(\"syntax error\");\n\t\t\t\treturn NUMBER;\n\t\t\t}\n\n<IFR>{WS}+\t\t{ ; }\n<IFR>{L}({L}|{D})*\t{\n\t\t\t\tyylval.node.op = NUMBER;\n\t\t\t\tif (gotdef) {\n\t\t\t\t\tyylval.node.nd_val\n\t\t\t\t\t    = lookup((usch *)yytext, FIND) != 0;\n\t\t\t\t\tgotdef = 0;\n\t\t\t\t\treturn IDENT;\n\t\t\t\t}\n\t\t\t\tyylval.node.nd_val = 0;\n\t\t\t\treturn NUMBER;\n\t\t\t}\n\n[0-9][0-9]*\t\t{\n\t\t\t\tif (slow && !YYSTATE)\n\t\t\t\t\treturn IDENT;\n\t\t\t\tscale = yytext[0] == '0' ? 8 : 10;\n\t\t\t\tgoto num;\n\t\t\t}\n\n0[xX]{H}+{IS}?\t\t{\tscale = 16;\n\t\t\tnum:\tif (YYSTATE == IFR) \n\t\t\t\t\tcvtdig(scale);\n\t\t\t\tPRTOUT(NUMBER);\n\t\t\t}\n0{D}+{IS}?\t\t{ scale = 8; goto num; }\n{D}+{IS}?\t\t{ scale = 10; goto num; }\n'(\\\\.|[^\\\\'])+'\t\t{\n\t\t\t\tif (YYSTATE || slow) {\n\t\t\t\t\tyylval.node.op = NUMBER;\n\t\t\t\t\tyylval.node.nd_val = charcon((usch *)yytext);\n\t\t\t\t\treturn (NUMBER);\n\t\t\t\t}\n\t\t\t\tif (tflag)\n\t\t\t\t\tyyless(1);\n\t\t\t\tif (!flslvl)\n\t\t\t\t\tputstr((usch *)yytext);\n\t\t\t}\n\n<IFR>.\t\t\t{ return yytext[0]; }\n\n{D}+{E}{FS}?\t\t{ PRTOUT(FPOINT); }\n{D}*\".\"{D}+({E})?{FS}?\t{ PRTOUT(FPOINT); }\n{D}+\".\"{D}*({E})?{FS}?\t{ PRTOUT(FPOINT); }\n\n^{WS}*#{WS}*\t\t{\textern int inmac;\n\n\t\t\t\tif (inmac)\n\t\t\t\t\terror(\"preprocessor directive found \"\n\t\t\t\t\t    \"while expanding macro\");\n\t\t\t\tcontr = 1;\n\t\t\t\tBEGIN CONTR;\n\t\t\t}\n{WS}+\t\t\t{ PRTOUT(WSPACE); }\n\n<CONTR>\"ifndef\"\t\t{ contr = 0; ifndefstmt(); }\n<CONTR>\"ifdef\"\t\t{ contr = 0; ifdefstmt(); }\n<CONTR>\"if\"\t\t{ contr = 0; storepb(); BEGIN IFR; ifstmt(); BEGIN 0; }\n<CONTR>\"include\"\t{ contr = 0; BEGIN 0; include(); prtline(); }\n<CONTR>\"else\"\t\t{ contr = 0; elsestmt(); }\n<CONTR>\"endif\"\t\t{ contr = 0; endifstmt(); }\n<CONTR>\"error\"\t\t{ contr = 0; if (slow) return IDENT; cpperror(); BEGIN 0; }\n<CONTR>\"define\"\t\t{ contr = 0; BEGIN DEF; define(); BEGIN 0; }\n<CONTR>\"undef\"\t\t{ contr = 0; if (slow) return IDENT; undefstmt(); }\n<CONTR>\"line\"\t\t{ contr = 0; storepb(); BEGIN 0; line(); }\n<CONTR>\"pragma\"\t\t{ contr = 0; pragmastmt(); BEGIN 0; }\n<CONTR>\"elif\"\t\t{ contr = 0; storepb(); BEGIN IFR; elifstmt(); BEGIN 0; }\n\n\n\n\"//\".*$\t\t\t{ /* if (tflag) yyless(..) */\n\t\t\t\tif (Cflag && !flslvl && !slow)\n\t\t\t\t\tputstr((usch *)yytext);\n\t\t\t\telse if (!flslvl)\n\t\t\t\t\tputch(' ');\n\t\t\t}\n\"/*\"\t\t\t{\tint c, wrn;\n\t\t\t\tint prtcm = Cflag && !flslvl && !slow;\n\t\t\t\textern int readmac;\n\n\t\t\t\tif (Cflag && !flslvl && readmac)\n\t\t\t\t\treturn CMNT;\n\n\t\t\t\tif (prtcm)\n\t\t\t\t\tputstr((usch *)yytext);\n\t\t\t\twrn = 0;\n\t\t\tmore:\twhile ((c = input()) && c != '*') {\n\t\t\t\t\tif (c == '\\n')\n\t\t\t\t\t\tputch(c), ifiles->lineno++;\n\t\t\t\t\telse if (c == 1) /* WARN */\n\t\t\t\t\t\twrn = 1;\n\t\t\t\t\telse if (prtcm)\n\t\t\t\t\t\tputch(c);\n\t\t\t\t}\n\t\t\t\tif (c == 0)\n\t\t\t\t\treturn 0;\n\t\t\t\tif (prtcm)\n\t\t\t\t\tputch(c);\n\t\t\t\tif ((c = input()) && c != '/') {\n\t\t\t\t\tunput(c);\n\t\t\t\t\tgoto more;\n\t\t\t\t}\n\t\t\t\tif (prtcm)\n\t\t\t\t\tputch(c);\n\t\t\t\tif (c == 0)\n\t\t\t\t\treturn 0;\n\t\t\t\tif (!tflag && !Cflag && !flslvl)\n\t\t\t\t\tunput(' ');\n\t\t\t\tif (wrn)\n\t\t\t\t\tunput(1);\n\t\t\t}\n\n<DEF>\"##\"\t\t{ return CONCAT; }\n<DEF>\"#\"\t\t{ return MKSTR; }\n<DEF>\"...\"\t\t{ return ELLIPS; }\n<DEF>\"__VA_ARGS__\"\t{ return VA_ARGS; }\n\nL?\\\"(\\\\.|[^\\\\\"])*\\\"\t{ PRTOUT(STRING); }\n[a-zA-Z_0-9]+\t\t{ /* {L}({L}|{D})* */\n\t\t\t\tstruct symtab *nl;\n\t\t\t\tif (slow)\n\t\t\t\t\treturn IDENT;\n\t\t\t\tif (YYSTATE == CONTR) {\n\t\t\t\t\tif (flslvl == 0) {\n\t\t\t\t\t\t/*error(\"undefined control\");*/\n\t\t\t\t\t\twhile (input() != '\\n')\n\t\t\t\t\t\t\t;\n\t\t\t\t\t\tunput('\\n');\n\t\t\t\t\t\tBEGIN 0;\n\t\t\t\t\t\tgoto xx;\n\t\t\t\t\t} else {\n\t\t\t\t\t\tBEGIN 0; /* do nothing */\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif (flslvl) {\n\t\t\t\t\t; /* do nothing */\n\t\t\t\t} else if (isdigit((int)yytext[0]) == 0 &&\n\t\t\t\t    (nl = lookup((usch *)yytext, FIND)) != 0) {\n\t\t\t\t\tusch *op = stringbuf;\n\t\t\t\t\tputstr(gotident(nl));\n\t\t\t\t\tstringbuf = op;\n\t\t\t\t} else\n\t\t\t\t\tputstr((usch *)yytext);\n\t\t\t\txx: ;\n\t\t\t}\n\n.\t\t\t{\n\t\t\t\tif (contr) {\n\t\t\t\t\twhile (input() != '\\n')\n\t\t\t\t\t\t;\n\t\t\t\t\tunput('\\n');\n\t\t\t\t\tBEGIN 0;\n\t\t\t\t\tcontr = 0;\n\t\t\t\t\tgoto yy;\n\t\t\t\t}\n\t\t\t\tif (YYSTATE || slow)\n\t\t\t\t\treturn yytext[0];\n\t\t\t\tif (yytext[0] == 6) { /* PRAGS */\n\t\t\t\t\tusch *obp = stringbuf;\n\t\t\t\t\textern usch *prtprag(usch *);\n\t\t\t\t\t*stringbuf++ = yytext[0];\n\t\t\t\t\tdo {\n\t\t\t\t\t\t*stringbuf = input();\n\t\t\t\t\t} while (*stringbuf++ != 14);\n\t\t\t\t\tprtprag(obp);\n\t\t\t\t\tstringbuf = obp;\n\t\t\t\t} else {\n\t\t\t\t\tPRTOUT(yytext[0]);\n\t\t\t\t}\n\t\t\t\tyy:;\n\t\t\t}\n\n%%\n\nusch *yyp, yybuf[CPPBUF];\n\nint yylex(void);\nint yywrap(void);\n\nstatic int\ninpch(void)\n{\n\tint len;\n\n\tif (ifiles->curptr < ifiles->maxread)\n\t\treturn *ifiles->curptr++;\n\n\tif ((len = read(ifiles->infil, ifiles->buffer, CPPBUF)) < 0)\n\t\terror(\"read error on file %s\", ifiles->orgfn);\n\tif (len == 0)\n\t\treturn -1;\n\tifiles->curptr = ifiles->buffer;\n\tifiles->maxread = ifiles->buffer + len;\n\treturn inpch();\n}\n\n#define unch(c) *--ifiles->curptr = c\n\nstatic int\ninch(void)\n{\n\tint c;\n\nagain:\tswitch (c = inpch()) {\n\tcase '\\\\': /* continued lines */\nmsdos:\t\tif ((c = inpch()) == '\\n') {\n\t\t\tifiles->lineno++;\n\t\t\tputch('\\n');\n\t\t\tgoto again;\n\t\t} else if (c == '\\r')\n\t\t\tgoto msdos;\n\t\tunch(c);\n\t\treturn '\\\\';\n\tcase '?': /* trigraphs */\n\t\tif ((c = inpch()) != '?') {\n\t\t\tunch(c);\n\t\t\treturn '?';\n\t\t}\n\t\tswitch (c = inpch()) {\n\t\tcase '=': c = '#'; break;\n\t\tcase '(': c = '['; break;\n\t\tcase ')': c = ']'; break;\n\t\tcase '<': c = '{'; break;\n\t\tcase '>': c = '}'; break;\n\t\tcase '/': c = '\\\\'; break;\n\t\tcase '\\'': c = '^'; break;\n\t\tcase '!': c = '|'; break;\n\t\tcase '-': c = '~'; break;\n\t\tdefault:\n\t\t\tunch(c);\n\t\t\tunch('?');\n\t\t\treturn '?';\n\t\t}\n\t\tunch(c);\n\t\tgoto again;\n\tdefault:\n\t\treturn c;\n\t}\n}\n\n/*\n * Let the command-line args be faked defines at beginning of file.\n */\nstatic void\nprinit(struct initar *it, struct includ *ic)\n{\n\tchar *a, *pre, *post;\n\n\tif (it->next)\n\t\tprinit(it->next, ic);\n\tpre = post = NULL; /* XXX gcc */\n\tswitch (it->type) {\n\tcase 'D':\n\t\tpre = \"#define \";\n\t\tif ((a = strchr(it->str, '=')) != NULL) {\n\t\t\t*a = ' ';\n\t\t\tpost = \"\\n\";\n\t\t} else\n\t\t\tpost = \" 1\\n\";\n\t\tbreak;\n\tcase 'U':\n\t\tpre = \"#undef \";\n\t\tpost = \"\\n\";\n\t\tbreak;\n\tcase 'i':\n\t\tpre = \"#include \\\"\";\n\t\tpost = \"\\\"\\n\";\n\t\tbreak;\n\tdefault:\n\t\terror(\"prinit\");\n\t}\n\tstrlcat((char *)ic->buffer, pre, CPPBUF+1);\n\tstrlcat((char *)ic->buffer, it->str, CPPBUF+1);\n\tif (strlcat((char *)ic->buffer, post, CPPBUF+1) >= CPPBUF+1)\n\t\terror(\"line exceeds buffer size\");\n\n\tic->lineno--;\n\twhile (*ic->maxread)\n\t\tic->maxread++;\n}\n\n/*\n * A new file included.\n * If ifiles == NULL, this is the first file and already opened (stdin).\n * Return 0 on success, -1 if file to be included is not found.\n */\nint\npushfile(usch *file)\n{\n\textern struct initar *initar;\n\tstruct includ ibuf;\n\tstruct includ *ic;\n\tint c, otrulvl;\n\n\tic = &ibuf;\n\tic->next = ifiles;\n\n\tslow = 0;\n\tif (file != NULL) {\n\t\tif ((ic->infil = open((char *)file, O_RDONLY)) < 0)\n\t\t\treturn -1;\n\t\tic->orgfn = ic->fname = file;\n\t\tif (++inclevel > MAX_INCLEVEL)\n\t\t\terror(\"Limit for nested includes exceeded\");\n\t} else {\n\t\tic->infil = 0;\n\t\tic->orgfn = ic->fname = (usch *)\"<stdin>\";\n\t}\n\tic->buffer = ic->bbuf+NAMEMAX;\n\tic->curptr = ic->buffer;\n\tifiles = ic;\n\tic->lineno = 1;\n\tic->maxread = ic->curptr;\n\tprtline();\n\tif (initar) {\n\t\t*ic->maxread = 0;\n\t\tprinit(initar, ic);\n\t\tif (dMflag)\n\t\t\twrite(ofd, ic->buffer, strlen((char *)ic->buffer));\n\t\tinitar = NULL;\n\t}\n\n\totrulvl = trulvl;\n\n\tif ((c = yylex()) != 0)\n\t\terror(\"yylex returned %d\", c);\n\n\tif (otrulvl != trulvl || flslvl)\n\t\terror(\"unterminated conditional\");\n\n\tifiles = ic->next;\n\tclose(ic->infil);\n\tinclevel--;\n\treturn 0;\n}\n\n/*\n * Print current position to output file.\n */\nvoid\nprtline()\n{\n\tusch *s, *os = stringbuf;\n\n\tif (Mflag) {\n\t\tif (dMflag)\n\t\t\treturn; /* no output */\n\t\tif (ifiles->lineno == 1) {\n\t\t\ts = sheap(\"%s: %s\\n\", Mfile, ifiles->fname);\n\t\t\twrite(ofd, s, strlen((char *)s));\n\t\t}\n\t} else if (!Pflag)\n\t\tputstr(sheap(\"# %d \\\"%s\\\"\\n\", ifiles->lineno, ifiles->fname));\n\tstringbuf = os;\n}\n\nvoid\ncunput(int c)\n{\n#ifdef CPP_DEBUG\n\textern int dflag;\n\tif (dflag)printf(\": '%c'(%d)\", c > 31 ? c : ' ', c);\n#endif\n\tunput(c);\n}\n\nint yywrap(void) { return 1; }\n\nstatic int\ndig2num(int c)\n{\n\tif (c >= 'a')\n\t\tc = c - 'a' + 10;\n\telse if (c >= 'A')\n\t\tc = c - 'A' + 10;\n\telse\n\t\tc = c - '0';\n\treturn c;\n}\n\n/*\n * Convert string numbers to unsigned long long and check overflow.\n */\nstatic void\ncvtdig(int rad)\n{\n\tunsigned long long rv = 0;\n\tunsigned long long rv2 = 0;\n\tchar *y = yytext;\n\tint c;\n\n\tc = *y++;\n\tif (rad == 16)\n\t\ty++;\n\twhile (isxdigit(c)) {\n\t\trv = rv * rad + dig2num(c);\n\t\t/* check overflow */\n\t\tif (rv / rad < rv2)\n\t\t\terror(\"Constant \\\"%s\\\" is out of range\", yytext);\n\t\trv2 = rv;\n\t\tc = *y++;\n\t}\n\ty--;\n\twhile (*y == 'l' || *y == 'L')\n\t\ty++;\n\tyylval.node.op = *y == 'u' || *y == 'U' ? UNUMBER : NUMBER;\n\tyylval.node.nd_uval = rv;\n\tif ((rad == 8 || rad == 16) && yylval.node.nd_val < 0)\n\t\tyylval.node.op = UNUMBER;\n\tif (yylval.node.op == NUMBER && yylval.node.nd_val < 0)\n\t\t/* too large for signed */\n\t\terror(\"Constant \\\"%s\\\" is out of range\", yytext);\n}\n\nstatic int\ncharcon(usch *p)\n{\n\tint val, c;\n\n\tp++; /* skip first ' */\n\tval = 0;\n\tif (*p++ == '\\\\') {\n\t\tswitch (*p++) {\n\t\tcase 'a': val = '\\a'; break;\n\t\tcase 'b': val = '\\b'; break;\n\t\tcase 'f': val = '\\f'; break;\n\t\tcase 'n': val = '\\n'; break;\n\t\tcase 'r': val = '\\r'; break;\n\t\tcase 't': val = '\\t'; break;\n\t\tcase 'v': val = '\\v'; break;\n\t\tcase '\\\"': val = '\\\"'; break;\n\t\tcase '\\'': val = '\\''; break;\n\t\tcase '\\\\': val = '\\\\'; break;\n\t\tcase 'x':\n\t\t\twhile (isxdigit(c = *p)) {\n\t\t\t\tval = val * 16 + dig2num(c);\n\t\t\t\tp++;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase '0': case '1': case '2': case '3': case '4':\n\t\tcase '5': case '6': case '7':\n\t\t\tp--;\n\t\t\twhile (isdigit(c = *p)) {\n\t\t\t\tval = val * 8 + (c - '0');\n\t\t\t\tp++;\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault: val = p[-1];\n\t\t}\n\n\t} else\n\t\tval = p[-1];\n\treturn val;\n}\n\nstatic void\nchknl(int ignore)\n{\n\tint t;\n\n\tslow = 1;\n\twhile ((t = yylex()) == WSPACE)\n\t\t;\n\tif (t != '\\n') {\n\t\tif (ignore) {\n\t\t\twarning(\"newline expected, got \\\"%s\\\"\", yytext);\n\t\t\t/* ignore rest of line */\n\t\t\twhile ((t = yylex()) && t != '\\n')\n\t\t\t\t;\n\t\t}\n\t\telse\n\t\t\terror(\"newline expected, got \\\"%s\\\"\", yytext);\n\t}\n\tslow = 0;\n}\n\nstatic void\nelsestmt(void)\n{\n\tif (flslvl) {\n\t\tif (elflvl > trulvl)\n\t\t\t;\n\t\telse if (--flslvl!=0) {\n\t\t\tflslvl++;\n\t\t} else {\n\t\t\ttrulvl++;\n\t\t\tprtline();\n\t\t}\n\t} else if (trulvl) {\n\t\tflslvl++;\n\t\ttrulvl--;\n\t} else\n\t\terror(\"If-less else\");\n\tif (elslvl==trulvl+flslvl)\n\t\terror(\"Too many else\");\n\telslvl=trulvl+flslvl;\n\tchknl(1);\n}\n\nstatic void\nifdefstmt(void)\t\t \n{ \n\tint t;\n\n\tif (flslvl) {\n\t\t/* just ignore the rest of the line */\n\t\twhile (input() != '\\n')\n\t\t\t;\n\t\tunput('\\n');\n\t\tyylex();\n\t\tflslvl++;\n\t\treturn;\n\t}\n\tslow = 1;\n\tdo\n\t\tt = yylex();\n\twhile (t == WSPACE);\n\tif (t != IDENT)\n\t\terror(\"bad ifdef\");\n\tslow = 0;\n\tif (flslvl == 0 && lookup((usch *)yytext, FIND) != 0)\n\t\ttrulvl++;\n\telse\n\t\tflslvl++;\n\tchknl(0);\n}\n\nstatic void\nifndefstmt(void)\t  \n{ \n\tint t;\n\n\tslow = 1;\n\tdo\n\t\tt = yylex();\n\twhile (t == WSPACE);\n\tif (t != IDENT)\n\t\terror(\"bad ifndef\");\n\tslow = 0;\n\tif (flslvl == 0 && lookup((usch *)yytext, FIND) == 0)\n\t\ttrulvl++;\n\telse\n\t\tflslvl++;\n\tchknl(0);\n}\n\nstatic void\nendifstmt(void)\t\t \n{\n\tif (flslvl) {\n\t\tflslvl--;\n\t\tif (flslvl == 0)\n\t\t\tprtline();\n\t} else if (trulvl)\n\t\ttrulvl--;\n\telse\n\t\terror(\"If-less endif\");\n\tif (flslvl == 0)\n\t\telflvl = 0;\n\telslvl = 0;\n\tchknl(1);\n}\n\n/*\n * Note! Ugly!\n * Walk over the string s and search for defined, and replace it with \n * spaces and a 1 or 0. \n */\nstatic void\nfixdefined(usch *s)\n{\n\tusch *bc, oc;\n\n\tfor (; *s; s++) {\n\t\tif (*s != 'd')\n\t\t\tcontinue;\n\t\tif (memcmp(s, \"defined\", 7))\n\t\t\tcontinue;\n\t\t/* Ok, got defined, can scratch it now */\n\t\tmemset(s, ' ', 7);\n\t\ts += 7;\n#define\tWSARG(x) (x == ' ' || x == '\\t')\n\t\tif (*s != '(' && !WSARG(*s))\n\t\t\tcontinue;\n\t\twhile (WSARG(*s))\n\t\t\ts++;\n\t\tif (*s == '(')\n\t\t\ts++;\n\t\twhile (WSARG(*s))\n\t\t\ts++;\n#define IDARG(x) ((x>= 'A' && x <= 'Z') || (x >= 'a' && x <= 'z') || (x == '_'))\n#define\tNUMARG(x) (x >= '0' && x <= '9')\n\t\tif (!IDARG(*s))\n\t\t\terror(\"bad defined arg\");\n\t\tbc = s;\n\t\twhile (IDARG(*s) || NUMARG(*s))\n\t\t\ts++;\n\t\toc = *s;\n\t\t*s = 0;\n\t\t*bc = (lookup(bc, FIND) != 0) + '0';\n\t\tmemset(bc+1, ' ', s-bc-1);\n\t\t*s = oc;\n\t}\n}\n\n/*\n * get the full line of identifiers after an #if, pushback a WARN and\n * the line and prepare for expmac() to expand.\n * This is done before switching state.  When expmac is finished,\n * pushback the expanded line, change state and call yyparse.\n */\nstatic void\nstorepb(void)\n{\n\tusch *opb = stringbuf;\n\tint c;\n\n\twhile ((c = input()) != '\\n') {\n\t\tif (c == '/') {\n\t\t\t if ((c = input()) == '*') {\n\t\t\t\t/* ignore comments here whatsoever */\n\t\t\t\tusch *g = stringbuf;\n\t\t\t\tgetcmnt();\n\t\t\t\tstringbuf = g;\n\t\t\t\tcontinue;\n\t\t\t} else if (c == '/') {\n\t\t\t\twhile ((c = input()) && c != '\\n')\n\t\t\t\t\t;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tunput(c);\n\t\t\tc = '/';\n\t\t}\n\t\tsavch(c);\n\t}\n\tcunput('\\n');\n\tsavch(0);\n\tfixdefined(opb); /* XXX can fail if #line? */\n\tcunput(1); /* WARN XXX */\n\tunpstr(opb);\n\tstringbuf = opb;\n\tslow = 1;\n\texpmac(NULL);\n\tslow = 0;\n\t/* line now expanded */\n\twhile (stringbuf > opb)\n\t\tcunput(*--stringbuf);\n}\n\nstatic void\nifstmt(void)\n{\n\tif (flslvl == 0) {\n\t\tslow = 1;\n\t\tif (yyparse())\n\t\t\t++trulvl;\n\t\telse\n\t\t\t++flslvl;\n\t\tslow = 0;\n\t} else\n\t\t++flslvl;\n}\n\nstatic void\nelifstmt(void)\n{\n\tif (flslvl == 0)\n\t\telflvl = trulvl;\n\tif (flslvl) {\n\t\tif (elflvl > trulvl)\n\t\t\t;\n\t\telse if (--flslvl!=0)\n\t\t\t++flslvl;\n\t\telse {\n\t\t\tslow = 1;\n\t\t\tif (yyparse()) {\n\t\t\t\t++trulvl;\n\t\t\t\tprtline();\n\t\t\t} else\n\t\t\t\t++flslvl;\n\t\t\tslow = 0;\n\t\t}\n\t} else if (trulvl) {\n\t\t++flslvl;\n\t\t--trulvl;\n\t} else\n\t\terror(\"If-less elif\");\n}\n\nstatic usch *\nsvinp(void)\n{\n\tint c;\n\tusch *cp = stringbuf;\n\n\twhile ((c = input()) && c != '\\n')\n\t\tsavch(c);\n\tsavch('\\n');\n\tsavch(0);\n\tBEGIN 0;\n\treturn cp;\n}\n\nstatic void\ncpperror(void)\n{\n\tusch *cp;\n\tint c;\n\n\tif (flslvl)\n\t\treturn;\n\tc = yylex();\n\tif (c != WSPACE && c != '\\n')\n\t\terror(\"bad error\");\n\tcp = svinp();\n\tif (flslvl)\n\t\tstringbuf = cp;\n\telse\n\t\terror(\"%s\", cp);\n}\n\nstatic void\nundefstmt(void)\n{\n\tstruct symtab *np;\n\n\tslow = 1;\n\tif (yylex() != WSPACE || yylex() != IDENT)\n\t\terror(\"bad undef\");\n\tif (flslvl == 0 && (np = lookup((usch *)yytext, FIND)))\n\t\tnp->value = 0;\n\tslow = 0;\n\tchknl(0);\n}\n\nstatic void\npragmastmt(void)\n{\n\tint c;\n\n\tslow = 1;\n\tif (yylex() != WSPACE)\n\t\terror(\"bad pragma\");\n\tif (!flslvl)\n\t\tputstr((usch *)\"#pragma \");\n\tdo {\n\t\tc = input();\n\t\tif (!flslvl)\n\t\t\tputch(c);\t/* Do arg expansion instead? */\n\t} while (c && c != '\\n');\n\tifiles->lineno++;\n\tprtline();\n\tslow = 0;\n}\n\nstatic void\nbadop(const char *op)\n{\n\terror(\"invalid operator in preprocessor expression: %s\", op);\n}\n\nint\ncinput()\n{\n\treturn input();\n}\n"
  },
  {
    "path": "share/examples/scheme/prime.scm",
    "content": "(define (square n) (* n n))\n\n(define (divides? a b)\n  (= (remainder b a) 0))\n\n(define (find-divisor n test-divisor)\n  (cond ((> (square test-divisor) n) n)\n        ((divides? test-divisor n) test-divisor)\n        (else (find-divisor n (+ test-divisor 1)))))\n\n(define (smallest-divisor n)\n  (find-divisor n 2))\n\n(define (prime? n)\n  (= n (smallest-divisor n)))\n\n(define (t n)\n  (display n)\n  (if (prime? n)\n    (display '-prime)\n    (display '-compound))\n  (newline))\n\n(t 2)\n(t 20)\n(t 23)\n(t 65)\n(t 67)\n(t 2011)\n"
  },
  {
    "path": "share/examples/sensors/Makefile",
    "content": "PROG    = led2 led3 led7 relay buzzer laser pbuzz irled joystick\n\nall:    $(PROG)\n\nrelay:  relay.c\n\tcc $? -o $@\n\nbuzzer: buzzer.c\n\tcc $? -o $@\n\npbuzz: pbuzz.c\n\tcc $? -o $@\n\nlaser:  laser.c\n\tcc $? -o $@\n\nled2:   led2.c\n\tcc $? -o $@\n\nled3:   led3.c\n\tcc $? -o $@\n\nled7:   led7.c\n\tcc $? -o $@\n\nirled:  irled.c\n\tcc $? -o $@\n\njoystick: joystick.c\n\tcc $? -o $@\n\nclean:\n\trm -f *.o *~ $(PROG)\n"
  },
  {
    "path": "share/examples/sensors/README.txt",
    "content": "Examples for 37-in-1 sensor kit.\n\nFor details, see:\n    https://github.com/sergev/RetroBSD-and-37-Sensor-Kit/wiki\n"
  },
  {
    "path": "share/examples/sensors/buzzer.c",
    "content": "/*\n * Example for RetroBSD on Olimex Duinomite board.\n * Active buzzer is connected to D0 pin of Duinomite board.\n * Use ioctl() calls to poll the user button, and control the buzzer.\n */\n#include <stdio.h>\n#include <sys/ioctl.h>\n#include <sys/gpio.h>\n\n/*\n * Pin D0 is connected to signal RE0 on pic32 chip.\n * User button is connected to signal RD8 on pic32 chip.\n */\n#define MASK_D0     (1 << 0)    /* signal RE0 */\n#define MASK_BUTTON (1 << 8)    /* signal RD8 */\n\nint main()\n{\n    int fd, portb;\n    char *devname = \"/dev/porta\";\n\n    /* Open GPIO driver. */\n    fd = open(devname, 1);\n    if (fd < 0) {\n        perror(devname);\n        return -1;\n    }\n\n    /* Configure pins. */\n    ioctl(fd, GPIO_PORTD | GPIO_CONFIN, MASK_BUTTON);\n    ioctl(fd, GPIO_PORTE | GPIO_CONFOUT, MASK_D0);\n    ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D0);\n\n    for (;;) {\n        /* Poll button at RD8 every 20 msec (active low). */\n        usleep(20000);\n        portb = ioctl(fd, GPIO_PORTD | GPIO_POLL, 0);\n\n        if (~portb & MASK_BUTTON) {\n            /* Enable buzzer at D0. */\n            ioctl(fd, GPIO_PORTE | GPIO_SET, MASK_D0);\n        } else {\n            /* Disable buzzer at D0. */\n            ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D0);\n        }\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/sensors/buzzer.sh",
    "content": "#!/bin/sh\n\n# Set signal RD8 as input, RE0 as output.\necho -------i-------- > /dev/confd\necho ---------------o > /dev/confe\necho ---------------0 > /dev/porte\n\nwhile :\ndo\n    # Poll button (active low)\n    read portd < /dev/portd\n    case $portd in\n    ???????0????????)\n        # Switch buzzer on\n        echo ---------------1 > /dev/porte\n        ;;\n    ???????1????????)\n        # Switch buzzer off\n        echo ---------------0 > /dev/porte\n        ;;\n    esac\ndone\n"
  },
  {
    "path": "share/examples/sensors/irled.c",
    "content": "/*\n * Example for RetroBSD on Olimex Duinomite board.\n * Infrared LED is connected to D0 pin of Duinomite board.\n * Use ioctl() calls to poll the user button, and control the buzzer.\n */\n#include <stdio.h>\n#include <sys/ioctl.h>\n#include <sys/gpio.h>\n\n/*\n * Pin D0 is connected to signal RE0 on pic32 chip.\n * User button is connected to signal RD8 on pic32 chip.\n */\n#define MASK_D0     (1 << 0)    /* signal RE0 */\n#define MASK_BUTTON (1 << 8)    /* signal RD8 */\n\nint main()\n{\n    int fd, portb;\n    char *devname = \"/dev/porta\";\n\n    /* Open GPIO driver. */\n    fd = open(devname, 1);\n    if (fd < 0) {\n        perror(devname);\n        return -1;\n    }\n\n    /* Configure pins. */\n    ioctl(fd, GPIO_PORTD | GPIO_CONFIN, MASK_BUTTON);\n    ioctl(fd, GPIO_PORTE | GPIO_CONFOUT, MASK_D0);\n    ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D0);\n\n    for (;;) {\n        /* Poll button at RD8 (active low). */\n        portb = ioctl(fd, GPIO_PORTD | GPIO_POLL, 0);\n\n        if (~portb & MASK_BUTTON) {\n            /* Transmit a series of three pulses 50 msec each,\n             * repeat every second. */\n            ioctl(fd, GPIO_PORTE | GPIO_SET, MASK_D0);\n            usleep(50000);\n            ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D0);\n            usleep(50000);\n            ioctl(fd, GPIO_PORTE | GPIO_SET, MASK_D0);\n            usleep(50000);\n            ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D0);\n            usleep(50000);\n            ioctl(fd, GPIO_PORTE | GPIO_SET, MASK_D0);\n            usleep(50000);\n            ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D0);\n            usleep(750000);\n        }\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/sensors/joystick.c",
    "content": "/*\n * Example for RetroBSD on Olimex Duinomite board.\n * Joystick is connected to A0, A1 and D7 pin of Duinomite board.\n */\n#include <stdio.h>\n#include <sys/ioctl.h>\n#include <sys/gpio.h>\n\n/*\n * Pin D7 is connected to signal RE7 on pic32 chip.\n */\n#define MASK_BUTTON     (1 << 7)    /* signal RE7 */\n\n/*\n * Read value from analog-to-digital converter.\n * Scale to given max value.\n */\nint readadc(int fd, int max)\n{\n    char buf[16];\n    int val;\n\n    if (read(fd, buf, sizeof(buf)) <= 0) {\n        perror(\"adc\");\n        exit(-1);\n    }\n    val = strtol(buf, 0, 10);\n    return val * max / 1024;\n}\n\nint main()\n{\n    int gpio, adc3, adc4, porte, x, y;\n\n    /* Open GPIO driver. */\n    gpio = open(\"/dev/porta\", 1);\n    if (gpio < 0) {\n        perror(\"/dev/porta\");\n        return -1;\n    }\n\n    /* Open ADC driver. */\n    adc3 = open(\"/dev/adc3\", 0);\n    if (adc3 < 0) {\n        perror(\"/dev/adc3\");\n        return -1;\n    }\n    adc4 = open(\"/dev/adc4\", 0);\n    if (adc4 < 0) {\n        perror(\"/dev/adc4\");\n        return -1;\n    }\n\n    /* Configure D7 pin is input, active low. */\n    ioctl(gpio, GPIO_PORTE | GPIO_CONFIN, MASK_BUTTON);\n\n    /* Clear screen. */\n    printf(\"\\33[2J\");\n\n    for (;;) {\n        /* Poll joystick every 20 msec. */\n        usleep(20000);\n        porte = ioctl(gpio, GPIO_PORTE | GPIO_POLL, 0);\n        x = readadc(adc3, 50);\n        y = readadc(adc4, 25);\n\n        if (~porte & MASK_BUTTON) {\n            /* When button pressed - clear screen. */\n            printf(\"\\33[2J\");\n        }\n        printf(\"\\33[H%u, %u  \", x, y);\n        printf(\"\\33[%u;%uHX\", y, 78 - x);\n        fflush(stdout);\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/sensors/laser.c",
    "content": "/*\n * Example for RetroBSD on Olimex Duinomite board.\n * Laser is connected to D0 pin of Duinomite board.\n * Use ioctl() calls to poll the user button, and control the laser.\n */\n#include <stdio.h>\n#include <sys/ioctl.h>\n#include <sys/gpio.h>\n\n/*\n * Pin D0 is connected to signal RE0 on pic32 chip.\n * User button is connected to signal RD8 on pic32 chip.\n */\n#define MASK_D0     (1 << 0)    /* signal RE0 */\n#define MASK_BUTTON (1 << 8)    /* signal RD8 */\n\nint main()\n{\n    int fd, portb;\n    char *devname = \"/dev/porta\";\n\n    /* Open GPIO driver. */\n    fd = open(devname, 1);\n    if (fd < 0) {\n        perror(devname);\n        return -1;\n    }\n\n    /* Configure pins. */\n    ioctl(fd, GPIO_PORTD | GPIO_CONFIN, MASK_BUTTON);\n    ioctl(fd, GPIO_PORTE | GPIO_CONFOUT, MASK_D0);\n    ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D0);\n\n    for (;;) {\n        /* Poll button at RD8 every 20 msec (active low). */\n        usleep(20000);\n        portb = ioctl(fd, GPIO_PORTD | GPIO_POLL, 0);\n\n        if (~portb & MASK_BUTTON) {\n            /* Enable laser at D0. */\n            ioctl(fd, GPIO_PORTE | GPIO_SET, MASK_D0);\n        } else {\n            /* Disable laser at D0. */\n            ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D0);\n        }\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/sensors/laser.sh",
    "content": "#!/bin/sh\n\n# Set signal RD8 as input, RE0 as output.\necho -------i-------- > /dev/confd\necho ---------------o > /dev/confe\necho ---------------0 > /dev/porte\n\nwhile :\ndo\n    # Poll button (active low)\n    read portd < /dev/portd\n    case $portd in\n    ???????0????????)\n        # Switch relay on\n        echo ---------------1 > /dev/porte\n        ;;\n    ???????1????????)\n        # Switch relay off\n        echo ---------------0 > /dev/porte\n        ;;\n    esac\ndone\n"
  },
  {
    "path": "share/examples/sensors/led2-portio.sh",
    "content": "#!/bin/sh\n#\n# Example for RetroBSD on Olimex Duinomite board.\n# RGB LED is connected to D1 and D0 pins of Duinomite board.\n# Use /dev/porte device to control LED.\n#\n\n# Pins D0 and D1 are connected to signals RE0 and RE1 of pic32 chip.\n# Set up them as output.\nportio -o e0 e1\nportio -c e0 e1\n\nwhile :\ndo\n    portio -c e0 -s e1\n    portio -c e1 -s e0\ndone\n"
  },
  {
    "path": "share/examples/sensors/led2.c",
    "content": "/*\n * Example for RetroBSD on Olimex Duinomite board.\n * RGB LED is connected to D1 and D0 pins of Duinomite board.\n * Use ioctl() calls to control LED.\n */\n#include <stdio.h>\n#include <sys/ioctl.h>\n#include <sys/gpio.h>\n\n/*\n * Pins D0 and D1 are connected to signals RE0 and RE1 of pic32 chip.\n */\n#define MASK_D0     (1 << 0)    /* signal RE0 */\n#define MASK_D1     (1 << 1)    /* signal RE1 */\n\nint main()\n{\n    int fd;\n    char *devname = \"/dev/porta\";\n\n    /* Open GPIO driver. */\n    fd = open(devname, 1);\n    if (fd < 0) {\n        perror(devname);\n        return -1;\n    }\n\n    /* Configure pins as output. */\n    ioctl(fd, GPIO_PORTE | GPIO_CONFOUT, MASK_D0 | MASK_D1);\n    ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D0 | MASK_D1);\n\n    for (;;) {\n        /* Clear D0, set D1. */\n        ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D0);\n        ioctl(fd, GPIO_PORTE | GPIO_SET, MASK_D1);\n        usleep(250000);\n\n        /* Clear D1, set D0. */\n        ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D1);\n        ioctl(fd, GPIO_PORTE | GPIO_SET, MASK_D0);\n        usleep(250000);\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/sensors/led2.sh",
    "content": "#!/bin/sh\n#\n# Example for RetroBSD on Olimex Duinomite board.\n# RGB LED is connected to D1 and D0 pins of Duinomite board.\n# Use /dev/porte device to control LED.\n#\n\n# Pins D0 and D1 are connected to signals RE0 and RE1 of pic32 chip.\n# Set up them as output.\necho --------------oo > /dev/confe\necho --------------00 > /dev/porte\n\nwhile :\ndo\n    echo --------------10 > /dev/porte\n    sleep 1\n    echo --------------01 > /dev/porte\n    sleep 1\ndone\n"
  },
  {
    "path": "share/examples/sensors/led3-portio.sh",
    "content": "#!/bin/sh\n#\n# Example for RetroBSD on Olimex Duinomite board.\n# RGB LED is connected to D7, D6 and D5 pins of Duinomite board.\n# Use portio utility to control LED.\n#\n\n# Pins D5, D6 and D7 are connected to signals RE5, RE6 and RE7 of pic32 chip.\n# Set up them as output.\nportio -o e5-7\nportio -c e5-7\n\nwhile :\ndo\n    portio -c e5 -s e7\n    portio -c e7 -s e6\n    portio -c e6 -s e5\ndone\n"
  },
  {
    "path": "share/examples/sensors/led3.c",
    "content": "/*\n * Example for RetroBSD on Olimex Duinomite board.\n * RGB LED is connected to D7, D6 and D5 pins of Duinomite board.\n * Use ioctl() calls to control LED.\n */\n#include <stdio.h>\n#include <sys/ioctl.h>\n#include <sys/gpio.h>\n\n/*\n * Pins D5, D6 and D7 are connected to signals RE5, RE6 and RE7 of pic32 chip.\n */\n#define MASK_D5     (1 << 5)    /* signal RE5 */\n#define MASK_D6     (1 << 6)    /* signal RE6 */\n#define MASK_D7     (1 << 7)    /* signal RE7 */\n\nint main()\n{\n    int fd;\n    char *devname = \"/dev/porta\";\n\n    /* Open GPIO driver. */\n    fd = open(devname, 1);\n    if (fd < 0) {\n        perror(devname);\n        return -1;\n    }\n\n    /* Configure pins as output. */\n    ioctl(fd, GPIO_PORTE | GPIO_CONFOUT, MASK_D5 | MASK_D6 | MASK_D7);\n    ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D5 | MASK_D6 | MASK_D7);\n\n    for (;;) {\n        /* Clear D5, set D7. */\n        ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D5);\n        ioctl(fd, GPIO_PORTE | GPIO_SET, MASK_D7);\n        usleep(100000);\n\n        /* Clear D7, set D6. */\n        ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D7);\n        ioctl(fd, GPIO_PORTE | GPIO_SET, MASK_D6);\n        usleep(100000);\n\n        /* Clear D6, set D5. */\n        ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D6);\n        ioctl(fd, GPIO_PORTE | GPIO_SET, MASK_D5);\n        usleep(100000);\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/sensors/led3.sh",
    "content": "#!/bin/sh\n#\n# Example for RetroBSD on Olimex Duinomite board.\n# RGB LED is connected to D7, D6 and D5 pins of Duinomite board.\n# Use /dev/porte device to control LED.\n#\n\n# Pins D5, D6 and D7 are connected to signals RE5, RE6 and RE7 of pic32 chip.\n# Set up them as output.\necho --------ooo----- > /dev/confe\necho --------000----- > /dev/porte\n\nwhile :\ndo\n    echo --------100----- > /dev/porte\n    sleep 1\n    echo --------010----- > /dev/porte\n    sleep 1\n    echo --------001----- > /dev/porte\n    sleep 1\ndone\n"
  },
  {
    "path": "share/examples/sensors/led7.c",
    "content": "/*\n * Example for RetroBSD on Olimex Duinomite board.\n * RGB LED is connected to D7, D6 and D5 pins of Duinomite board.\n * Use ioctl() calls to control LED.\n */\n#include <stdio.h>\n#include <sys/ioctl.h>\n#include <sys/gpio.h>\n\n/*\n * Pin D2 is connected to signal RE2 on pic32 chip.\n */\n#define MASK_D2     (1 << 2)    /* signal RE2 */\n\nint main()\n{\n    int fd;\n    char *devname = \"/dev/porta\";\n\n    /* Open GPIO driver. */\n    fd = open(devname, 1);\n    if (fd < 0) {\n        perror(devname);\n        return -1;\n    }\n\n    /* Configure pin as output. */\n    ioctl(fd, GPIO_PORTE | GPIO_CONFOUT, MASK_D2);\n    ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D2);\n\n    for (;;) {\n        /* Set D2. */\n        ioctl(fd, GPIO_PORTE | GPIO_SET, MASK_D2);\n        sleep(15);\n\n        /* Clear D2. */\n        ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D2);\n        sleep(3);\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/sensors/pbuzz.c",
    "content": "/*\n * Example for RetroBSD on Olimex Duinomite board.\n * Passive buzzer is connected to D0 pin of Duinomite board.\n * Use ioctl() calls to poll the user button, and control the buzzer.\n */\n#include <stdio.h>\n#include <sys/ioctl.h>\n#include <sys/gpio.h>\n\n/*\n * Pin D0 is connected to signal RE0 on pic32 chip.\n * User button is connected to signal RD8 on pic32 chip.\n */\n#define MASK_D0     (1 << 0)    /* signal RE0 */\n#define MASK_BUTTON (1 << 8)    /* signal RD8 */\n\nint main()\n{\n    int fd, portb;\n    char *devname = \"/dev/porta\";\n\n    /* Open GPIO driver. */\n    fd = open(devname, 1);\n    if (fd < 0) {\n        perror(devname);\n        return -1;\n    }\n\n    /* Configure pins. */\n    ioctl(fd, GPIO_PORTD | GPIO_CONFIN, MASK_BUTTON);\n    ioctl(fd, GPIO_PORTE | GPIO_CONFOUT, MASK_D0);\n    ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D0);\n\n    for (;;) {\n        /* Poll button at RD8 (active low). */\n        portb = ioctl(fd, GPIO_PORTD | GPIO_POLL, 0);\n\n        if (~portb & MASK_BUTTON) {\n            /* Toggle buzzer at D0. */\n            ioctl(fd, GPIO_PORTE | GPIO_INVERT, MASK_D0);\n            usleep(5000);\n        } else {\n            /* Disable buzzer at D0. */\n            ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D0);\n        }\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/sensors/relay.c",
    "content": "/*\n * Example for RetroBSD on Olimex Duinomite board.\n * Relay is connected to D0 pin of Duinomite board.\n * Use ioctl() calls to poll the user button, and control the relay.\n */\n#include <stdio.h>\n#include <sys/ioctl.h>\n#include <sys/gpio.h>\n\n/*\n * Pin D0 is connected to signal RE0 on pic32 chip.\n * User button is connected to signal RD8 on pic32 chip.\n */\n#define MASK_D0     (1 << 0)    /* signal RE0 */\n#define MASK_BUTTON (1 << 8)    /* signal RD8 */\n\nint main()\n{\n    int fd, portb;\n    char *devname = \"/dev/porta\";\n\n    /* Open GPIO driver. */\n    fd = open(devname, 1);\n    if (fd < 0) {\n        perror(devname);\n        return -1;\n    }\n\n    /* Configure pins. */\n    ioctl(fd, GPIO_PORTD | GPIO_CONFIN, MASK_BUTTON);\n    ioctl(fd, GPIO_PORTE | GPIO_CONFOUT, MASK_D0);\n    ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D0);\n\n    for (;;) {\n        /* Poll button at RD8 every 20 msec (active low). */\n        usleep(20000);\n        portb = ioctl(fd, GPIO_PORTD | GPIO_POLL, 0);\n\n        if (~portb & MASK_BUTTON) {\n            /* Enable relay at D0. */\n            ioctl(fd, GPIO_PORTE | GPIO_SET, MASK_D0);\n        } else {\n            /* Disable relay at D0. */\n            ioctl(fd, GPIO_PORTE | GPIO_CLEAR, MASK_D0);\n        }\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/sensors/relay.sh",
    "content": "#!/bin/sh\n\n# Set signal RD8 as input, RE0 as output.\necho -------i-------- > /dev/confd\necho ---------------o > /dev/confe\necho ---------------0 > /dev/porte\n\nwhile :\ndo\n    # Poll button (active low)\n    read portd < /dev/portd\n    case $portd in\n    ???????0????????)\n        # Switch relay on\n        echo ---------------1 > /dev/porte\n        ;;\n    ???????1????????)\n        # Switch relay off\n        echo ---------------0 > /dev/porte\n        ;;\n    esac\ndone\n"
  },
  {
    "path": "share/examples/smallc/Makefile",
    "content": "CC      = scc\nPROG    = hello primelist primesum test1 test2 test3 gpio adc rain \\\n          webserver q8\n\nall:    $(PROG)\n\nhello:\thello.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) hello.c\n\nprimelist: primelist.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) primelist.c\n\nprimesum: primesum.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) primesum.c\n\nwebserver: webserver.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) webserver.c -lwiznet\n\ngpio:   gpio.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) gpio.c\n\nadc:    adc.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) adc.c\n\nrain:   rain.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) rain.c\n\nq8:     q8.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) q8.c\n\ntest1:\ttest1.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) test1.c\n\ntest2:\ttest2.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) test2.c\n\ntest3:\ttest3.c\n\t$(CC) $(CFLAGS) -o $@ $(LDFLAGS) test3.c\n\nclean:\n\trm -f *.o $(PROG)\n"
  },
  {
    "path": "share/examples/smallc/adc.c",
    "content": "/*\n * Example of reading ADC data.\n */\n#include <fcntl.h>\n\nchar buf[100];\n\nmain()\n{\n    int i, fd, value;\n\n    for (i=0; i<16; i++) {\n        sprintf(buf, \"/dev/adc%d\", i);\n        fd = open(buf, O_RDWR);\n        if (fd < 0) {\n            printf(\"Error: unable to open %s\\n\", buf);\n        } else {\n            if (read(fd, buf, 20) > 0) {\n                value = strtol (buf, 0, 0);\n                printf(\"adc%-2d = %d\\n\", i, value);\n            }\n            close(fd);\n        }\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/smallc/gpio.c",
    "content": "/*\n * Example of polling general purpose i/o pins.\n */\n#include <fcntl.h>\n#include <sys/gpio.h>\n\nmain ()\n{\n    int fd, pnum, value;\n\n    fd = open (\"/dev/porta\", O_RDWR);\n    if (fd < 0) {\n        perror (\"/dev/porta\");\n        return -1;\n    }\n\n    for (pnum=0; pnum<7; pnum++) {\n        value = ioctl (fd, GPIO_POLL | GPIO_PORT (pnum), 0);\n        if (value < 0)\n            perror (\"GPIO_POLL\");\n        printf (\"port%c = 0x%04x\\n\", pnum + 'A', value);\n    }\n    return 0;\n}\n"
  },
  {
    "path": "share/examples/smallc/hello.c",
    "content": "main()\n{\n    printf (\"Hello, SmallC World!\\n\");\n}\n"
  },
  {
    "path": "share/examples/smallc/primelist.c",
    "content": "/*\n * Print the list of prime numbers up to 100.\n */\nmain()\n{\n    int n;\n\n    for (n=2; n<100; ++n) {\n        if (isprime(n)) {\n            printf(\"%d \", n);\n        }\n    }\n    printf(\"\\n\");\n}\n\nisprime(n)\n    int n;\n{\n    int j;\n\n    if (n == 2)\n        return 1;\n\n    if (n % 2 == 0)\n        return 0;\n\n    for (j=3; j*j<=n; j+=2)\n        if (n % j == 0)\n            return 0;\n    return 1;\n}\n"
  },
  {
    "path": "share/examples/smallc/primesum.c",
    "content": "/*\n * Compute the sum of prime numbers up to 10000.\n */\nmain()\n{\n    int sum, n;\n\n    sum = 0;\n    for (n=2; n<10000; ++n) {\n        if (isprime(n)) {\n            sum += n;\n        }\n    }\n    printf(\"Sum of primes less than 10000: %d\\n\", sum);\n}\n\nisprime(n)\n    int n;\n{\n    int j;\n\n    if (n == 2)\n        return 1;\n\n    if (n % 2 == 0)\n        return 0;\n\n    for (j=3; j*j<=n; j+=2)\n        if (n % j == 0)\n            return 0;\n    return 1;\n}\n"
  },
  {
    "path": "share/examples/smallc/q8.c",
    "content": "/*\n * Eight Queens puzzle\n *\n * (C) 2010 by Mark Sproul\n * Open source as per standard Arduino code\n * Modified by Pito 12/2012 for SmallC\n */\n#define TRUE    1\n#define FALSE   0\n\nunsigned int gChessBoard[8];\nunsigned int gLoopCounter;\nint gValidCount;\n\nCheckCurrentBoard()\n{\n    int ii;\n    int jj;\n    int theRow;\n    int theLongRow;\n    int theLongColumns;\n    int bitCount;\n\n    //* we know we have 1 in each row,\n    //* Check for 1 in each column\n    theRow = 0;\n    for (ii=0; ii<8; ii++) {\n        theRow |= gChessBoard[ii];\n    }\n    if (theRow != 0x0ff) {\n        return FALSE;\n    }\n\n    //* we have 1 in each column, now check the diagonals\n    theLongColumns = 0;\n    for (ii=0; ii<8; ii++) {\n        theLongRow = gChessBoard[ii] & 0x0ff;\n        theLongRow = theLongRow << ii;\n\n        theLongColumns |= theLongRow;\n    }\n\n    //* now count the bits\n    bitCount = 0;\n    for (ii=0; ii<16; ii++) {\n        if ((theLongColumns & 0x01) == 0x01) {\n            bitCount++;\n        }\n        theLongColumns = theLongColumns >> 1;\n    }\n\n    if (bitCount != 8) {\n        return FALSE;\n    }\n\n    //* we now have to check the other diagonal\n    theLongColumns = 0;\n    for (ii=0; ii<8; ii++) {\n        theLongRow = gChessBoard[ii] & 0x0ff;\n        theLongRow = theLongRow << 8;\n        theLongRow = theLongRow >> ii;\n\n        theLongColumns |= theLongRow;\n    }\n\n    //* now count the bits\n    bitCount = 0;\n    for (ii=0; ii<16; ii++) {\n        if ((theLongColumns & 0x01) == 0x01) {\n            bitCount++;\n        }\n        theLongColumns = theLongColumns >> 1;\n    }\n\n    if (bitCount != 8) {\n        return FALSE;\n    }\n    return TRUE;\n}\n\nCheckForDone()\n{\n    int ii;\n    int weAreDone;\n    int theRow;\n\n    weAreDone = FALSE;\n\n    //* we know we have 1 in each row,\n    //* Check for 1 in each column\n    theRow = 0;\n    for (ii=0; ii<8; ii++) {\n        theRow |= gChessBoard[ii];\n    }\n\n    if (theRow == 0x01) {\n        weAreDone = TRUE;\n    }\n    return weAreDone;\n}\n\nRotateQueens()\n{\n    int ii;\n    int keepGoing;\n    int theRow;\n\n    ii = 0;\n    keepGoing = TRUE;\n    while (keepGoing && (ii < 8)) {\n        theRow = gChessBoard[ii] & 0x0ff;\n        theRow = (theRow >> 1) & 0x0ff;\n        if (theRow != 0) {\n            gChessBoard[ii] = theRow;\n            keepGoing = FALSE;\n        } else {\n            gChessBoard[ii] = 0x080;\n        }\n        ii++;\n    }\n}\n\nPrintChessBoard()\n{\n    int ii;\n    int jj;\n    int theRow;\n    char textString[32];\n\n    printf(\"\\nLoop= %d\\n\", gLoopCounter);\n    printf(\"Solution count= %d\\n\", gValidCount);\n\n    printf(\"+----------------+\\n\");\n    for (ii=0; ii<8; ii++) {\n        theRow = gChessBoard[ii];\n\n        printf(\"|\");\n        for (jj=0; jj<8; jj++) {\n            if (theRow & 0x080) {\n                printf(\"Q \");\n            } else {\n                printf(\". \");\n            }\n            theRow = theRow << 1;\n        }\n        printf(\"|\\n\");\n    }\n    printf(\"+----------------+\\n\");\n}\n\nmain()\n{\n    int ii;\n\n    printf(\"\\nEight Queens brute force\");\n    printf(\"\\n************************\\n\");\n    //* put the 8 queens on the board, 1 in each row\n    for (ii=0; ii<8; ii++) {\n        gChessBoard[ii] = 0x080;\n    }\n    PrintChessBoard();\n\n    gLoopCounter = 0;\n    gValidCount = 0;\n\n\n    while (1) {\n        gLoopCounter++;\n\n        if (CheckCurrentBoard()) {\n            gValidCount++;\n            PrintChessBoard();\n        } else if ((gLoopCounter % 1000) == 0) {\n            //PrintChessBoard();\n        }\n\n        RotateQueens();\n        if (CheckForDone()) {\n            //int elapsedSeconds;\n            //int elapsedMinutes;\n            //int elapsedHours;\n\n            //elapsedSeconds = millis() / 1000;\n            //elapsedMinutes = elapsedSeconds / 60;\n            //elapsedHours = elapsedMinutes / 60;\n\n            printf(\"----------------------------------\\n\");\n            printf(\"All done\\n\");\n\n            PrintChessBoard();\n            printf(\"----------------------------------\\n\");\n\n            //Serial.print(\"total seconds=\");\n            //Serial.println(elapsedSeconds);\n\n            //Serial.print(\"hours=\");\n            //Serial.println(elapsedHours);\n\n            //Serial.print(\"minutes=\");\n            //Serial.println(elapsedMinutes % 60);\n\n            //Serial.print(\"seconds=\");\n            //Serial.println(elapsedSeconds % 60);\n\n            return (1);\n        }\n    }\n}\n"
  },
  {
    "path": "share/examples/smallc/rain.c",
    "content": "/*\n * Example of using termcap library for SmallC.\n * 11/3/1980 EPS/CITHEP\n *\n * Copyright (c) 1980 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <stdio.h>\n#include <signal.h>\n\n#define CO 80               /* number of columns */\n#define LI 24               /* number of lines */\n\n#define CL \"\\33[H\\33[J\"     /* clear the screen */\n#define CM \"\\33[%u;%uH\"     /* move the cursor to row, column */\n#define BC \"\\b\"             /* move cursor left */\n#define DN \"\\33[B\"          /* move cursor down */\n#define ND \" \"              /* move cursor right */\n\nint xpos[5], ypos[5];\nchar outbuf[BUFSIZ];\n\nmoveto(col, row)\n    int col, row;\n{\n    printf(CM, row, col);\n}\n\nonsig(n)\n    int n;\n{\n    moveto(0, LI - 1);\n    fflush(stdout);\n    _exit(0);\n}\n\nmain()\n{\n    int x, y, j;\n\n    setbuf(stdout, outbuf);\n    for (j = SIGHUP; j <= SIGTERM; j++)\n        if (signal(j, SIG_IGN) != SIG_IGN)\n            signal(j, onsig);\n\n    fputs(CL, stdout);\n    fflush(stdout);\n    for (j = 5; --j >= 0; ) {\n        xpos[j] = 2 + rand() % (CO - 4);\n        ypos[j] = 2 + rand() % (LI - 4);\n    }\n    for (j = 0; ; ) {\n        x = 2 + rand() % (CO - 4);\n        y = 2 + rand() % (LI - 4);\n        moveto(x, y);\n        putchar('.');\n        moveto(xpos[j], ypos[j]);\n        putchar('o');\n        if (j == 0)\n            j = 4;\n        else\n            --j;\n        moveto(xpos[j], ypos[j]);\n        putchar('O');\n        if (j == 0)\n            j = 4;\n        else\n            --j;\n        moveto(xpos[j], ypos[j]-1);\n        putchar('-');\n        fputs(DN, stdout);\n        fputs(BC, stdout);\n        fputs(BC, stdout);\n        fputs(\"|.|\", stdout);\n        fputs(DN, stdout);\n        fputs(BC, stdout);\n        fputs(BC, stdout);\n        putchar('-');\n        if (j == 0)\n            j = 4;\n        else\n            --j;\n        moveto(xpos[j], ypos[j]-2);\n        putchar('-');\n        fputs(DN, stdout);\n        fputs(BC, stdout);\n        fputs(BC, stdout);\n        fputs(\"/ \\\\\", stdout);\n        moveto(xpos[j]-2, ypos[j]);\n        fputs(\"| O |\", stdout);\n        moveto(xpos[j]-1, ypos[j]+1);\n        fputs(\"\\\\ /\", stdout);\n        fputs(DN, stdout);\n        fputs(BC, stdout);\n        fputs(BC, stdout);\n        putchar('-');\n        if (j == 0)\n            j = 4;\n        else\n            --j;\n        moveto(xpos[j], ypos[j]-2);\n        putchar(' ');\n        fputs(DN, stdout);\n        fputs(BC, stdout);\n        fputs(BC, stdout);\n        putchar(' ');\n        fputs(ND, stdout);\n        putchar(' ');\n        moveto(xpos[j]-2, ypos[j]);\n        putchar(' ');\n        fputs(ND, stdout);\n        putchar(' ');\n        fputs(ND, stdout);\n        putchar(' ');\n        moveto(xpos[j]-1, ypos[j]+1);\n        putchar(' ');\n        fputs(ND, stdout);\n        putchar(' ');\n        fputs(DN, stdout);\n        fputs(BC, stdout);\n        fputs(BC, stdout);\n        putchar(' ');\n        xpos[j] = x;\n        ypos[j] = y;\n        fflush(stdout);\n        usleep(100000);\n    }\n}\n"
  },
  {
    "path": "share/examples/smallc/test1.c",
    "content": "int ga[5];\n\nmain()\n{\n    int a, b, c, d;\n    int arr[5];\n    int *pi;\n    char arrc[5];\n    char *pic;\n    int s1, s2;\n    int z;\n    int t;\n    int *pip;\n    int *picp;\n    int e1, e2;\n\n    ga[0] = 10;\n    ga[1] = 20;\n    ga[2] = 30;\n    ga[3] = 40;\n    ga[4] = 50;\n    \n    a = 21;\n    b = 31;\n    c = 71;\n    d = 82;\n\n    arr[0] = 10;\n    arr[1] = 20;\n    arr[2] = 30;\n    arr[3] = 40;\n    arr[4] = 50;\n    pi = &arr[0];\n\n    arrc[0] = 13;\n    arrc[1] = 23;\n    arrc[2] = 33;\n    arrc[3] = 43;\n    arrc[4] = 53;\n    pic = &arrc[0];\n\n    printf(\"          21 + 31 = %d (52)\\n\",   a + b);\n    printf(\"          21 - 31 = %d (-10)\\n\",  a - b);\n    printf(\"          21 & 71 = %d (5)\\n\",    a & c);\n    printf(\"          21 | 82 = %d (87)\\n\",   a | d);\n    printf(\"          21 ^ 82 = %d (71)\\n\",   a ^ d);\n    printf(\"          21 * 82 = %d (1722)\\n\", a * d);\n    printf(\"          82 % 21 = %d (19)\\n\",   d % a);\n    printf(\"          82 / 21 = %d (3)\\n\",    d / a);\n    printf(\"              *pi = %d (10)\\n\",   *pi);\n    printf(\"          *pi + 1 = %d (11)\\n\",   *pi + 1);\n    printf(\"        *(pi + 1) = %d (20)\\n\",   *(pi + 1));\n    printf(\"&arr[3] - &arr[0] = %d (3)\\n\",    &arr[3] - &arr[0]);\n    printf(\"    arr[3]-arr[0] = %d (30)\\n\",   arr[3] - arr[0]);\n    printf(\"    arr[3]+arr[0] = %d (50)\\n\",   arr[3] + arr[0]);\n    printf(\"  &ga[3] - &ga[0] = %d (3)\\n\",    &ga[3] - &ga[0]);\n    printf(\"      ga[3]-ga[0] = %d (30)\\n\",   ga[3] - ga[0]);\n    printf(\"      ga[3]+ga[0] = %d (50)\\n\",   ga[3] + ga[0]);\n    printf(\"\\n\");\n\n    printf(\"               *pic = %d (13)\\n\", *pic);\n    printf(\"           *pic + 1 = %d (14)\\n\", *pic+1);\n    printf(\"         *(pic + 1) = %d (23)\\n\", *(pic+1));\n    printf(\"&arrc[3] - &arrc[0] = %d (3)\\n\",  &arrc[3]-&arrc[0]);\n    printf(\"\\n\");\n\n    s1 = 3;\n    s2 = -200;\n    printf(\"  82 << 3 = %d (656)\\n\",   d << s1);\n    printf(\"  82 >> 3 = %d (10)\\n\",    d >> s1);\n    printf(\"-200 >> 3 = %d (-25)\\n\",   s2 >> s1);\n    printf(\"-200 << 3 = %d (-1600)\\n\", s2 << s1);\n    printf(\"\\n\");\n\n    printf(\"-s1 = %d (-3)\\n\",  -s1);\n    printf(\"-s2 = %d (200)\\n\", -s2);\n    printf(\"\\n\");\n\n    printf(\"~82 = %d (-83)\\n\", ~d);\n    printf(\"\\n\");\n\n    z = 0;\n    printf(\"!82 = %d (0)\\n\", !d);\n    printf(\" !0 = %d (1)\\n\", !z);\n    printf(\"\\n\");\n\n    printf(\" 0 && 0  = %d (0)\\n\", z && z);\n    printf(\" 0 && 21 = %d (0)\\n\", z && a);\n    printf(\" 3 && 21 = %d (1)\\n\", s1 && a);\n    printf(\"21 && 3  = %d (1)\\n\", a && s1);\n    printf(\"\\n\");\n\n    printf(\" 0 || 0  = %d (0)\\n\", z || z);\n    printf(\" 0 || 21 = %d (1)\\n\", z || a);\n    printf(\" 3 || 21 = %d (1)\\n\", s1 || a);\n    printf(\"21 || 3  = %d (1)\\n\", a || s1);\n    printf(\"\\n\");\n\n    pi = 4;\n    printf(\"pi++ = %d (4)\\n\",  pi++);\n    printf(\"  pi = %d (8)\\n\",  pi);\n    printf(\"++pi = %d (12)\\n\", ++pi);\n    printf(\"pi-- = %d (12)\\n\", pi--);\n    printf(\"  pi = %d (8)\\n\",  pi);\n    printf(\"--pi = %d (4)\\n\",  --pi);\n    printf(\"\\n\");\n\n    pic = 4;\n    printf(\"pic++ = %d (4)\\n\", pic++);\n    printf(\"  pic = %d (5)\\n\", pic);\n    printf(\"++pic = %d (6)\\n\", ++pic);\n    printf(\"pic-- = %d (6)\\n\", pic--);\n    printf(\"  pic = %d (5)\\n\", pic);\n    printf(\"--pic = %d (4)\\n\", --pic);\n    printf(\"\\n\");\n\n    t = 4;\n    printf(\"t++ = %d (4)\\n\", t++);\n    printf(\"  t = %d (5)\\n\", t);\n    printf(\"++t = %d (6)\\n\", ++t);\n    printf(\"t-- = %d (6)\\n\", t--);\n    printf(\"  t = %d (5)\\n\", t);\n    printf(\"--t = %d (4)\\n\", --t);\n    printf(\"\\n\");\n\n    t = 4;\n    printf(\" t==4 = %d (1)\\n\", t == 4);\n    printf(\" t==3 = %d (0)\\n\", t == 3);\n    printf(\" t==5 = %d (0)\\n\", t == 5);\n    t = -4;\n    printf(\"t==-4 = %d (1)\\n\", t == -4);\n    printf(\"t==-3 = %d (0)\\n\", t == -3);\n    printf(\"t==-5 = %d (0)\\n\", t == -5);\n    printf(\" t==4 = %d (0)\\n\", t == 4);\n    printf(\" t==3 = %d (0)\\n\", t == 3);\n    printf(\" t==5 = %d (0)\\n\", t == 5);\n    printf(\"\\n\");\n\n    t = 4;\n    printf(\" t!=4 = %d (0)\\n\", t != 4);\n    printf(\" t!=3 = %d (1)\\n\", t != 3);\n    printf(\" t!=5 = %d (1)\\n\", t != 5);\n    t = -4;\n    printf(\"t!=-4 = %d (0)\\n\", t != -4);\n    printf(\"t!=-3 = %d (1)\\n\", t != -3);\n    printf(\"t!=-5 = %d (1)\\n\", t != -5);\n    printf(\" t!=4 = %d (1)\\n\", t != 4);\n    printf(\" t!=3 = %d (1)\\n\", t != 3);\n    printf(\" t!=5 = %d (1)\\n\", t != 5);\n    printf(\"\\n\");\n\n    t = 4;\n    printf(\" t<4 = %d (0)\\n\", t < 4);\n    printf(\" t<3 = %d (0)\\n\", t < 3);\n    printf(\" t<5 = %d (1)\\n\", t < 5);\n    printf(\"t<-1 = %d (0)\\n\", t < -1);\n    printf(\"\\n\");\n\n    printf(\" t<=4 = %d (1)\\n\", t <= 4);\n    printf(\" t<=3 = %d (0)\\n\", t <= 3);\n    printf(\" t<=5 = %d (1)\\n\", t <= 5);\n    printf(\"t<=-1 = %d (0)\\n\", t <= -1);\n    printf(\"\\n\");\n\n    t = 4;\n    printf(\" t>4 = %d (0)\\n\", t > 4);\n    printf(\" t>3 = %d (1)\\n\", t > 3);\n    printf(\" t>5 = %d (0)\\n\", t > 5);\n    printf(\"t>-1 = %d (1)\\n\", t > -1);\n    printf(\"\\n\");\n\n    printf(\" t>=4 = %d (1)\\n\", t >= 4);\n    printf(\" t>=3 = %d (1)\\n\", t >= 3);\n    printf(\" t>=5 = %d (0)\\n\", t >= 5);\n    printf(\"t>=-1 = %d (1)\\n\", t >= -1);\n    printf(\"\\n\");\n\n    pi = -100;\n    printf(\"   pi<4 = %d (0)\\n\", pi < 4);\n    printf(\"   pi<3 = %d (0)\\n\", pi < 3);\n    printf(\"pi<-100 = %d (0)\\n\", pi < -100);\n    printf(\"  pi<-1 = %d (1)\\n\", pi < -1);\n    printf(\"\\n\");\n\n    printf(\"   pi<=4 = %d (0)\\n\", pi <= 4);\n    printf(\"   pi<=3 = %d (0)\\n\", pi <= 3);\n    printf(\"pi<=-100 = %d (1)\\n\", pi <= -100);\n    printf(\"  pi<=-1 = %d (1)\\n\", pi <= -1);\n    printf(\"\\n\");\n\n    pi = -100;\n    printf(\"   pi>4 = %d (1)\\n\", pi > 4);\n    printf(\"   pi>3 = %d (1)\\n\", pi > 3);\n    printf(\"pi>-100 = %d (0)\\n\", pi > -100);\n    printf(\"  pi>-1 = %d (0)\\n\", pi > -1);\n    printf(\"\\n\");\n\n    printf(\"   pi>=4 = %d (1)\\n\", pi >= 4);\n    printf(\"   pi>=3 = %d (1)\\n\", pi >= 3);\n    printf(\"pi>=-100 = %d (1)\\n\", pi >= -100);\n    printf(\"  pi>=-1 = %d (0)\\n\", pi >= -1);\n    printf(\"\\n\");\n\n    pi = &arr[0];\n    pip = &arr[3];\n    printf(\"    *pip - *pi: %d 30\\n\", *pip - *pi);\n    printf(\"      pip - pi: %d 3\\n\",  pip - pi);\n    printf(\"          *pip: %d 40\\n\", *pip);\n    printf(\"    *(pip - 3): %d 10\\n\", *(pip - 3));\n    printf(\"      *&arr[3]: %d 40\\n\", *&arr[3]);\n    printf(\"*(&arr[3] - 3): %d 10\\n\", *(&arr[3]-3));\n}\n\nprintt (t, str)\n    int t;\n    char *str;\n{\n    printf(\"bool test on value %d %s\\n\", t, str);\n}\n"
  },
  {
    "path": "share/examples/smallc/test2.c",
    "content": "#include <fcntl.h>\n\nint aaa;\nint bbb;\nint ccc;\nchar gc;\nchar gbuffer[3];\nint gibuffer[4];\n\nextern errno;\n\nmain()\n{\n    char b;\n    int la;\n    unsigned int u1, u2;\n    int s1, s2;\n    unsigned char uc1, uc2;\n    char sc1, sc2;\n    int fd;\n    char buffer[6];\n    int ibuffer[7];\n\n    printf(\"                sizeof(uc1): %d 1\\n\",  sizeof(uc1));\n    printf(\"                sizeof(sc1): %d 1\\n\",  sizeof(sc1));\n    printf(\"                 sizeof(u1): %d 4\\n\",  sizeof(u1));\n    printf(\"                 sizeof(s1): %d 4\\n\",  sizeof(s1));\n    printf(\"                sizeof(aaa): %d 4\\n\",  sizeof(aaa));\n    printf(\"                sizeof(bbb): %d 4\\n\",  sizeof(bbb));\n    printf(\"                 sizeof(gc): %d 1\\n\",  sizeof(gc));\n    printf(\"             sizeof(buffer): %d 6\\n\",  sizeof(buffer));\n    printf(\"            sizeof(ibuffer): %d 28\\n\", sizeof(ibuffer));\n    printf(\"               sizeof(char): %d 1\\n\",  sizeof(char));\n    printf(\"                sizeof(int): %d 4\\n\",  sizeof(int));\n    printf(\"            sizeof(gbuffer): %d 3\\n\",  sizeof(gbuffer));\n    printf(\"           sizeof(gibuffer): %d 16\\n\", sizeof(gibuffer));\n    // sizeof(ibuffer[0]) is not supported, so the following can be used...\n    printf(\"sizeof(ibuffer)/sizeof(int): %d 7\\n\",  sizeof(ibuffer)/sizeof(int));\n\n    aaa = 1;\n    bbb = 2;\n    la = 4;\n    printf(\"%d 1\\n\", aaa);\n    printf(\"%d 2\\n\", bbb);\n    printf(\"%d 4\\n\", la);\n\n    uc1 = 0x80;\n    sc1 = 0x80;\n    s1 = uc1;\n    s2 = sc1;\n    printf(\"unsigned char (0x80) -> int: %d 128\\n\",  s1);\n    printf(\"  signed char (0x80) -> int: %d -128\\n\", s2);\n\n    u1 = uc1;\n    u2 = sc1;\n    printf(\"unsigned char (0x80) -> unsigned: %d 128\\n\", u1);\n    printf(\"  signed char (0x80) -> unsigned: %d -128\\n\", u2);\n\n    la = errno;\n    printf(\"errno: %d 0\\n\", la);\n\n    write(1, \"abcd \", 5);\n    la = errno;\n    printf(\"errno after good write call: %d 0\\n\", la);\n\n    write(10, \"abcde\", 5);\n    la = errno;\n    printf(\"errno after bad write call: %d 9\\n\", la);\n\n    write(1, \"abcd \", 5);\n    la = errno;\n    printf(\"good write after failed should not overwrite errno: %d 9\\n\", la);\n\n    errno = 0;\n    write(1, \"abcd \", 5);\n    la = errno;\n    printf(\"good write after errno set to zero: %d 0\\n\", la);\n\n    la = write(1, \"abcd \", 5);\n    printf(\"write() return: %d 5\\n\", la);\n\n    la = write(10, \"abcd \", 5);\n    printf(\"write(bad fd) return: %d -1\\n\", la);\n\n    fd = open(\"/a.txt\", O_WRONLY | O_CREAT, 0666);\n    if (fd != -1) {\n        printf(\"open success\\n\");\n        la = write(fd, \"abcd\\n\", 5);\n        if (la == 5) printf(\"write success\\n\"); else  printf(\"write failed\\n\");\n        la = close(fd);\n        if (la != -1) printf(\"close success\\n\"); else printf(\"close failed\\n\");\n    } else {\n        printf(\"open failed\\n\");\n    }\n\n    buffer[0] = 0;\n    buffer[1] = 0;\n    buffer[2] = 0;\n    buffer[3] = 0;\n    buffer[4] = 0;\n    buffer[5] = 0;\n\n    fd = open(\"/a.txt\", O_RDONLY, 0666);\n    if (fd != -1) {\n        printf(\"open success\\n\");\n        la = read(fd, buffer, 5);\n        printf(buffer);\n        if (la == 5) printf(\"read success\\n\"); else  printf(\"read failed\\n\");\n        la = close(fd);\n        if (la != -1) printf(\"close success\\n\"); else printf(\"close failed\\n\");\n    } else {\n        printf(\"open failed\\n\");\n    }\n\n    if (buffer[0] != 'a')  printf(\"data0 readback from file MISMATCH\\n\");\n    if (buffer[1] != 'b')  printf(\"data1 readback from file MISMATCH\\n\");\n    if (buffer[2] != 'c')  printf(\"data2 readback from file MISMATCH\\n\");\n    if (buffer[3] != 'd')  printf(\"data3 readback from file MISMATCH\\n\");\n    if (buffer[4] != '\\n') printf(\"data4 readback from file MISMATCH\\n\");\n\n    if (buffer[0] != 'a' || buffer[1] != 'b' || buffer[2] != 'c' ||\n        buffer[3] != 'd' || buffer[4] != '\\n') {\n        printf(\"data readback from file MISMATCH\\n\");\n    } else {\n        printf(\"data readback from file OK\\n\");\n    }\n}\n"
  },
  {
    "path": "share/examples/smallc/test3.c",
    "content": "main()\n{\n    int t;\n\n    t = 0;\n    if (t) printt(t, \"failure\"); else printt(t, \"success\");\n    t = 1;\n    if (t) printt(t, \"success\"); else printt(t, \"failure\");\n    t = 8;\n    if (t) printt(t, \"success\"); else printt(t, \"failure\");\n    t = -2;\n    if (t) printt(t, \"success\"); else printt(t, \"failure\");\n    printf(\"\\n\");\n\n    t = 4;\n    printf(\"switch test: \");\n    switch (t) {\n    case 3:\n        printf(\"failure\");\n        break;\n    case 4:\n        printf(\"success\");\n        break;\n    case 5:\n        printf(\"failure\");\n        break;\n    }\n    printf(\"\\n\");\n\n    printf(\"switch fallthrough test: \");\n    switch (t) {\n    case 3:\n        printf(\"failure\");\n        break;\n    case 4:\n        printf(\"OKSOFAR: \");\n    case 5:\n        printf(\"success if oksofar printed before this in caps\");\n        break;\n    }\n    printf(\"\\n\");\n}\n\nprintt (t, str)\n    int t;\n    char *str;\n{\n    printf(\"bool test on value %d %s\\n\", t, str);\n}\n"
  },
  {
    "path": "share/examples/smallc/webserver.c",
    "content": "/*\n * Web server, written in SmallC.\n *\n * A simple web server that shows the value of the analog input pins.\n * using an Arduino Wiznet Ethernet shield.\n *\n * 18 Dec 2009 created by David A. Mellis\n *  4 Sep 2010 modified by Tom Igoe\n * 16 Apr 2012 ported to RetroBSD by Serge Vakulenko\n */\n#include <stdio.h>\n#include <fcntl.h>\n#include <sys/gpio.h>\n#include <wiznet.h>\n\nint client [CLIENT_SIZE];\n\nchar buf [80];\n\nmain()\n{\n    /* Initialize the Ethernet server library\n     * with the IP address and port you want to use\n     * (port 80 is default for HTTP). */\n    ethernet_init ();\n    server_init (80);\n\n    for (;;) {\n        /* Listen for incoming clients. */\n        if (server_available (client)) {\n            process_request();\n        }\n    }\n}\n\nprocess_request()\n{\n    int current_line_is_blank;\n    int c, fd, pnum, value;\n\n    /* An http request ends with a blank line. */\n    current_line_is_blank = 1;\n\n    /* Parse the http request. */\n    while (client_connected (client)) {\n        if (client_available (client)) {\n            c = client_getc (client);\n\n            /* If you've gotten to the end of the line (received\n             * a newline character) and the line is blank, the http\n             * request has ended, so you can send a reply. */\n            if (c == '\\n' && current_line_is_blank)\n                break;\n\n            if (c == '\\n') {\n                /* You're starting a new line. */\n                current_line_is_blank = 1;\n            }\n            else if (c != '\\r') {\n                /* You've gotten a character on the current line. */\n                current_line_is_blank = 0;\n            }\n        }\n    }\n\n    /* Send a standard http response header. */\n    client_puts (client, \"HTTP/1.1 200 OK\\n\");\n    client_puts (client, \"Content-Type: text/html\\n\\n\");\n\n    /* Output the value of each digital pin. */\n    fd = open (\"/dev/porta\", O_RDONLY);\n    if (fd < 0) {\n        client_puts (client, \"Failed to open /dev/porta\\n\");\n    } else {\n        for (pnum = 0; pnum < 6; pnum++) {\n            value = ioctl (fd, GPIO_POLL | GPIO_PORT (pnum), 0);\n            sprintf (buf, \"PORT%c = 0x%04x <br />\\n\", pnum+'A', value);\n            client_puts (client, buf);\n        }\n        close (fd);\n    }\n\n    /* Give the web browser time to receive the data. */\n    usleep (1000);\n\n    /* Close the connection. */\n    client_stop (client);\n}\n"
  },
  {
    "path": "share/examples/yacc/Makefile",
    "content": "all: config.c cpy.c egrep.c expr.c gram.c grammar.c parser.c\n\n%.c: %.y\n\tyacc $<\n\tmv y.tab.c $@\n\nclean:\n\trm -f *.c yacc.acts yacc.tmp y.output y.tab.[ch]\n"
  },
  {
    "path": "share/examples/yacc/config.y",
    "content": "%union {\n    char    *str;\n    int     val;\n    struct  file_list *file;\n    struct  idlst *lst;\n}\n\n%token  AND\n%token  ANY\n%token  ARCHITECTURE\n%token  AT\n%token  BOARD\n%token  COMMA\n%token  CONFIG\n%token  CONTROLLER\n%token  CPU\n%token  CSR\n%token  DEVICE\n%token  DRIVE\n%token  DST\n%token  DUMPS\n%token  EQUALS\n%token  FLAGS\n%token  HZ\n%token  INVERT\n%token  LDSCRIPT\n%token  MAJOR\n%token  MAXUSERS\n%token  MINOR\n%token  MINUS\n%token  ON\n%token  OPTIONS\n%token  MAKEOPTIONS\n%token  PINS\n%token  PRIORITY\n%token  SERVICE\n%token  SIGNAL\n%token  ROOT\n%token  SEMICOLON\n%token  SEQUENTIAL\n%token  SIZE\n%token  SWAP\n%token  TIMEZONE\n%token  TRACE\n%token  VECTOR\n\n%token  <str>   ID\n%token  <val>   NUMBER\n%token  <val>   FPNUMBER\n%token  <val>   PIN\n\n%type   <str>   Save_id\n%type   <str>   Opt_value\n%type   <str>   Dev\n%type   <lst>   Id_list\n%type   <val>   optional_size\n%type   <val>   optional_sflag\n%type   <val>   optional_invert\n%type   <str>   device_name\n%type   <val>   major_minor\n%type   <val>   root_device_spec\n%type   <val>   dump_device_spec\n%type   <file>  swap_device_spec\n\n%{\n\n/*\n * Copyright (c) 1988, 1993\n *  The Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *  This product includes software developed by the University of\n *  California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n *  @(#)config.y    8.1 (Berkeley) 6/6/93\n */\n\n#include \"config.h\"\n#include <ctype.h>\n#include <stdio.h>\n\nstruct  device cur;\nstruct  device *curp = 0;\nchar    *temp_id;\nchar    *val_id;\n\nint             yylex(void);\nvoid            yyerror(char *s);\n\nvoid            newdev(struct device *dp);\nvoid            mkconf(char *sysname);\nstruct file_list   *newflist(u_char ftype);\nvoid            mkswap(struct file_list *system, struct file_list *fl,\n                    int size, int flag);\nstruct device  *connect(char *dev, int num);\nstruct device  *huhcon(char *dev);\nvoid            check_nexus(struct device *dev, int num);\nvoid            check_tz(void);\nvoid            checksystemspec(struct file_list *fl);\nvoid            verifysystemspecs(void);\ndev_t          *verifyswap(struct file_list *fl, dev_t checked[],\n                    dev_t *pchecked);\nint             alreadychecked(dev_t dev, dev_t list[], dev_t *last);\nvoid            deverror(char *systemname, char *devtype);\nint             finddev(dev_t dev);\n\n%}\n%%\nConfiguration:\n    Many_specs\n        { verifysystemspecs(); }\n    ;\n\nMany_specs:\n    Many_specs Spec\n        |\n    /* lambda */\n    ;\n\nSpec:\n    Device_spec SEMICOLON\n        { newdev(&cur); }\n        |\n    Config_spec SEMICOLON\n        |\n    TRACE SEMICOLON\n        { do_trace = !do_trace; }\n        |\n    SEMICOLON\n        |\n    error SEMICOLON\n    ;\n\nConfig_spec:\n    ARCHITECTURE Save_id\n        {\n            if (strcmp($2, \"pic32\") == 0) {\n                arch = ARCH_PIC32;\n                archname = \"pic32\";\n            } else if (strcmp($2, \"stm32\") == 0) {\n                arch = ARCH_STM32;\n                archname = \"stm32\";\n            } else\n                yyerror(\"Unknown architecture\");\n        }\n        |\n    CPU Save_id\n        {\n            struct cputype *cp =\n                (struct cputype *)malloc(sizeof (struct cputype));\n            cp->cpu_name = strdup($2);\n            cp->cpu_next = cputype;\n            cputype = cp;\n            free(temp_id);\n        }\n        |\n    OPTIONS Opt_list\n        |\n    MAKEOPTIONS Mkopt_list\n        |\n    BOARD ID\n        { board = strdup($2); }\n        |\n    LDSCRIPT ID\n        { ldscript = strdup($2); }\n        |\n    SIGNAL ID PINS PIN optional_invert\n        {\n            struct signal *s = (struct signal*) malloc(sizeof(struct signal));\n            s->sig_name = strdup($2);\n            s->sig_next = siglist;\n            s->sig_pin = $4;\n            s->sig_invert = $5;\n            siglist = s;\n        }\n        |\n    System_spec\n        |\n    TIMEZONE NUMBER\n        { zone = 60 * $2; check_tz(); }\n        |\n    TIMEZONE NUMBER DST NUMBER\n        { zone = 60 * $2; dst = $4; check_tz(); }\n        |\n    TIMEZONE NUMBER DST\n        { zone = 60 * $2; dst = 1; check_tz(); }\n        |\n    TIMEZONE FPNUMBER\n        { zone = $2; check_tz(); }\n        |\n    TIMEZONE FPNUMBER DST NUMBER\n        { zone = $2; dst = $4; check_tz(); }\n        |\n    TIMEZONE FPNUMBER DST\n        { zone = $2; dst = 1; check_tz(); }\n        |\n    TIMEZONE MINUS NUMBER\n        { zone = -60 * $3; check_tz(); }\n        |\n    TIMEZONE MINUS NUMBER DST NUMBER\n        { zone = -60 * $3; dst = $5; check_tz(); }\n        |\n    TIMEZONE MINUS NUMBER DST\n        { zone = -60 * $3; dst = 1; check_tz(); }\n        |\n    TIMEZONE MINUS FPNUMBER\n        { zone = -$3; check_tz(); }\n        |\n    TIMEZONE MINUS FPNUMBER DST NUMBER\n        { zone = -$3; dst = $5; check_tz(); }\n        |\n    TIMEZONE MINUS FPNUMBER DST\n        { zone = -$3; dst = 1; check_tz(); }\n        |\n    MAXUSERS NUMBER\n        { maxusers = $2; }\n    ;\n\nSystem_spec:\n    System_id System_parameter_list\n        { checksystemspec(*confp); }\n    ;\n\nSystem_id:\n    CONFIG Save_id\n        { mkconf($2); }\n    ;\n\nSystem_parameter_list:\n    System_parameter_list System_parameter\n        |\n    System_parameter\n    ;\n\nSystem_parameter:\n    swap_spec\n        |\n    root_spec\n        |\n    dump_spec\n    ;\n\nswap_spec:\n    SWAP optional_on swap_device_list\n    ;\n\nswap_device_list:\n    swap_device_list AND swap_device\n        |\n    swap_device\n    ;\n\nswap_device:\n    swap_device_spec optional_size optional_sflag\n        { mkswap(*confp, $1, $2, $3); }\n    ;\n\nswap_device_spec:\n    device_name\n        {\n            struct file_list *fl = newflist(SWAPSPEC);\n\n            if (eq($1, \"generic\"))\n                fl->f_fn = $1;\n            else {\n                fl->f_swapdev = nametodev($1, 0);\n                fl->f_fn = devtoname(fl->f_swapdev);\n            }\n            $$ = fl;\n        }\n        |\n    major_minor\n        {\n            struct file_list *fl = newflist(SWAPSPEC);\n\n            fl->f_swapdev = $1;\n            fl->f_fn = devtoname($1);\n            $$ = fl;\n        }\n    ;\n\nroot_spec:\n    ROOT optional_on root_device_spec\n        {\n            struct file_list *fl = *confp;\n\n            if (fl && fl->f_rootdev != NODEV)\n                yyerror(\"extraneous root device specification\");\n            else\n                fl->f_rootdev = $3;\n        }\n    ;\n\nroot_device_spec:\n    device_name\n        { $$ = nametodev($1, 0); }\n        |\n    major_minor\n    ;\n\ndump_spec:\n    DUMPS optional_on dump_device_spec\n        {\n            struct file_list *fl = *confp;\n\n            if (fl && fl->f_dumpdev != NODEV)\n                yyerror(\"extraneous dump device specification\");\n            else\n                fl->f_dumpdev = $3;\n        }\n    ;\n\ndump_device_spec:\n    device_name\n        { $$ = nametodev($1, 0); }\n        |\n    major_minor\n    ;\n\nmajor_minor:\n    MAJOR NUMBER MINOR NUMBER\n        { $$ = makedev($2, $4); }\n    ;\n\noptional_on:\n    ON\n        |\n    /* empty */\n    ;\n\noptional_size:\n    SIZE NUMBER\n        { $$ = $2; }\n        |\n    /* empty */\n        { $$ = 0; }\n    ;\n\noptional_sflag:\n    SEQUENTIAL\n        { $$ = 2; }\n        |\n    /* empty */\n        { $$ = 0; }\n    ;\n\noptional_invert:\n    INVERT\n        { $$ = 1; }\n        |\n    /* empty */\n        { $$ = 0; }\n    ;\n\ndevice_name:\n    Save_id\n        { $$ = $1; }\n        |\n    Save_id NUMBER\n        {\n            char buf[80];\n\n            (void) sprintf(buf, \"%s%d\", $1, $2);\n            $$ = strdup(buf);\n            free($1);\n        }\n        |\n    Save_id NUMBER ID\n        {\n            char buf[80];\n\n            (void) sprintf(buf, \"%s%d%s\", $1, $2, $3);\n            $$ = strdup(buf);\n            free($1);\n        }\n    ;\n\nOpt_list:\n    Opt_list COMMA Option\n        |\n    Option\n    ;\n\nOption:\n    Save_id\n        {\n            struct opt *op = (struct opt *)malloc(sizeof (struct opt));\n            op->op_name = strdup($1);\n            op->op_next = opt;\n            op->op_value = 0;\n            opt = op;\n            free(temp_id);\n        }\n        |\n    Save_id EQUALS Opt_value\n        {\n            struct opt *op = (struct opt *)malloc(sizeof (struct opt));\n            op->op_name = strdup($1);\n            op->op_next = opt;\n            op->op_value = strdup($3);\n            opt = op;\n            free(temp_id);\n            free(val_id);\n        }\n    ;\n\nOpt_value:\n    ID\n        { $$ = val_id = strdup($1); }\n        |\n    NUMBER\n        {\n            char nb[16];\n            (void) sprintf(nb, \"%d\", $1);\n            $$ = val_id = strdup(nb);\n        }\n    ;\n\nSave_id:\n    ID\n        { $$ = temp_id = strdup($1); }\n    ;\n\nMkopt_list:\n    Mkopt_list COMMA Mkoption\n        |\n    Mkoption\n    ;\n\nMkoption:\n    Save_id EQUALS Opt_value\n        {\n            struct opt *op = (struct opt *)malloc(sizeof (struct opt));\n            op->op_name = strdup($1);\n            op->op_next = mkopt;\n            op->op_value = strdup($3);\n            mkopt = op;\n            free(temp_id);\n            free(val_id);\n        }\n    ;\n\nDev:\n    ID\n        { $$ = strdup($1); }\n    ;\n\nDevice_spec:\n    DEVICE Dev_name Dev_info Int_spec\n        { cur.d_type = DEVICE; }\n        |\n    CONTROLLER Dev_name Dev_info Int_spec\n        { cur.d_type = CONTROLLER; }\n        |\n    SERVICE Init_dev Dev\n        {\n            cur.d_name = $3;\n            cur.d_type = SERVICE;\n        }\n        |\n    SERVICE Init_dev Dev NUMBER\n        {\n            cur.d_name = $3;\n            cur.d_type = SERVICE;\n            cur.d_slave = $4;\n        }\n    ;\n\nDev_name:\n    Init_dev Dev NUMBER\n        {\n            cur.d_name = $2;\n            cur.d_unit = $3;\n        }\n        |\n    Init_dev Dev\n        {\n            cur.d_name = $2;\n        }\n    ;\n\nInit_dev:\n    /* lambda */\n        { init_dev(&cur); }\n    ;\n\nDev_info:\n    Con_info Info_list\n        |\n    Info_list\n        |\n    /* lambda */\n    ;\n\nCon_info:\n    AT Dev NUMBER\n        { cur.d_conn = connect($2, $3); }\n    ;\n\nInfo_list:\n    Info_list Info\n        |\n    /* lambda */\n        ;\n\nInfo:\n    CSR NUMBER\n        { cur.d_addr = $2; }\n        |\n    DRIVE NUMBER\n        { cur.d_drive = $2; }\n        |\n    FLAGS NUMBER\n        { cur.d_flags = $2; }\n        |\n    PINS Pin_list\n    ;\n\nInt_spec:\n    VECTOR Id_list\n        { cur.d_vec = $2; }\n        |\n    PRIORITY NUMBER\n        { cur.d_pri = $2; }\n        |\n    /* lambda */\n    ;\n\nId_list:\n    Save_id\n        {\n            struct idlst *a = (struct idlst *)malloc(sizeof(struct idlst));\n            a->id = $1; a->id_next = 0; $$ = a;\n        }\n        |\n    Save_id Id_list\n        {\n            struct idlst *a = (struct idlst *)malloc(sizeof(struct idlst));\n            a->id = $1; a->id_next = $2; $$ = a;\n        }\n    ;\n\nPin_list:\n    PIN\n        { cur.d_pins[cur.d_npins++] = $1; }\n        |\n    PIN COMMA Pin_list\n        { cur.d_pins[cur.d_npins++] = $1; }\n    ;\n%%\n\nvoid\nyyerror(char *s)\n{\n    fprintf(stderr, \"config: line %d: %s\\n\", yyline + 1, s);\n}\n\n/*\n * add a device to the list of devices\n */\nvoid\nnewdev(struct device *dp)\n{\n    register struct device *np;\n\n    np = (struct device *) malloc(sizeof *np);\n    *np = *dp;\n    np->d_next = 0;\n    if (curp == 0)\n        dtab = np;\n    else\n        curp->d_next = np;\n    curp = np;\n}\n\n/*\n * note that a configuration should be made\n */\nvoid\nmkconf(char *sysname)\n{\n    register struct file_list *fl, **flp;\n\n    fl = (struct file_list *) malloc(sizeof *fl);\n    fl->f_type = SYSTEMSPEC;\n    fl->f_needs = sysname;\n    fl->f_rootdev = NODEV;\n    fl->f_dumpdev = NODEV;\n    fl->f_fn = 0;\n    fl->f_next = 0;\n    for (flp = confp; *flp; flp = &(*flp)->f_next)\n        ;\n    *flp = fl;\n    confp = flp;\n}\n\nstruct file_list *\nnewflist(u_char ftype)\n{\n    struct file_list *fl = (struct file_list *)malloc(sizeof (*fl));\n\n    fl->f_type = ftype;\n    fl->f_next = 0;\n    fl->f_swapdev = NODEV;\n    fl->f_swapsize = 0;\n    fl->f_needs = 0;\n    fl->f_fn = 0;\n    return (fl);\n}\n\n/*\n * Add a swap device to the system's configuration\n */\nvoid\nmkswap(struct file_list *system, struct file_list *fl, int size, int flag)\n{\n    register struct file_list **flp;\n\n    if (system == 0 || system->f_type != SYSTEMSPEC) {\n        yyerror(\"\\\"swap\\\" spec precedes \\\"config\\\" specification\");\n        return;\n    }\n    if (size < 0) {\n        yyerror(\"illegal swap partition size\");\n        return;\n    }\n    /*\n     * Append swap description to the end of the list.\n     */\n    flp = &system->f_next;\n    for (; *flp && (*flp)->f_type == SWAPSPEC; flp = &(*flp)->f_next)\n        ;\n    fl->f_next = *flp;\n    *flp = fl;\n    fl->f_swapsize = size;\n    fl->f_swapflag = flag;\n\n    /*\n     * If first swap device for this system,\n     * set up f_fn field to insure swap\n     * files are created with unique names.\n     */\n    if (system->f_fn)\n        return;\n\n    if (eq(fl->f_fn, \"generic\"))\n        system->f_fn = strdup(fl->f_fn);\n    else\n        system->f_fn = strdup(system->f_needs);\n}\n\n/*\n * find the pointer to connect to the given device and number.\n * returns 0 if no such device and prints an error message\n */\nstruct device *\nconnect(char *dev, int num)\n{\n    register struct device *dp;\n\n    if (num == QUES)\n        return (huhcon(dev));\n    for (dp = dtab; dp != 0; dp = dp->d_next) {\n        if ((num != dp->d_unit) || !eq(dev, dp->d_name))\n            continue;\n        if (dp->d_type != CONTROLLER) {\n            (void) sprintf(errbuf,\n                \"%s connected to non-controller\", dev);\n            yyerror(errbuf);\n            return (0);\n        }\n        return (dp);\n    }\n    (void) sprintf(errbuf, \"%s %d not defined\", dev, num);\n    yyerror(errbuf);\n    return (0);\n}\n\n/*\n * connect to an unspecific thing\n */\nstruct device *\nhuhcon(char *dev)\n{\n    register struct device *dp, *dcp;\n    struct device rdev;\n    int oldtype;\n\n    /*\n     * First make certain that there are some of these to wildcard on\n     */\n    for (dp = dtab; dp != 0; dp = dp->d_next)\n        if (eq(dp->d_name, dev))\n            break;\n    if (dp == 0) {\n        (void) sprintf(errbuf, \"no %s's to wildcard\", dev);\n        yyerror(errbuf);\n        return (0);\n    }\n    oldtype = dp->d_type;\n    dcp = dp->d_conn;\n\n    /*\n     * Now see if there is already a wildcard entry for this device\n     * (e.g. Search for a \"uba ?\")\n     */\n    for (; dp != 0; dp = dp->d_next)\n        if (eq(dev, dp->d_name) && dp->d_unit == -1)\n            break;\n    /*\n     * If there isn't, make one because everything needs to be connected\n     * to something.\n     */\n    if (dp == 0) {\n        dp = &rdev;\n        init_dev(dp);\n        dp->d_unit = QUES;\n        dp->d_name = strdup(dev);\n        dp->d_type = oldtype;\n        newdev(dp);\n        dp = curp;\n\n        /*\n         * Connect it to the same thing that other similar things are\n         * connected to, but make sure it is a wildcard unit\n         * (e.g. up connected to sc ?, here we make connect sc? to a\n         * uba?).  If other things like this\n         * aren't connected to anything, then make the same\n         * connection, else call ourself to connect to another\n         * unspecific device.\n         */\n        if (dcp == 0)\n            dp->d_conn = dcp;\n        else\n            dp->d_conn = connect(dcp->d_name, QUES);\n    }\n    return (dp);\n}\n\nvoid\ninit_dev(struct device *dp)\n{\n    dp->d_name = \"OHNO!!!\";\n    dp->d_type = DEVICE;\n    dp->d_conn = 0;\n    dp->d_vec = 0;\n    dp->d_addr = dp->d_flags;\n    dp->d_pri = -1;\n    dp->d_slave = dp->d_drive = dp->d_unit = UNKNOWN;\n    dp->d_port = (char *)0;\n    dp->d_irq = -1;\n    dp->d_drq = -1;\n    dp->d_maddr = 0;\n    dp->d_msize = 0;\n    dp->d_npins = 0;\n    dp->d_flags = 0;\n    dp->d_mask = \"null\";\n}\n\n/*\n * make certain that this is a reasonable type of thing to connect to a nexus\n */\nvoid\ncheck_nexus(struct device *dev, int num)\n{\n    switch (arch) {\n\n    case ARCH_PIC32:\n        break;\n    case ARCH_STM32:\n        break;\n    }\n}\n\n/*\n * Check the timezone to make certain it is sensible\n */\nvoid\ncheck_tz(void)\n{\n    if (abs(zone) > 12 * 60)\n        yyerror(\"timezone is unreasonable\");\n    else\n        hadtz = 1;\n}\n\n/*\n * Check system specification and apply defaulting\n * rules on root, argument, dump, and swap devices.\n */\nvoid\nchecksystemspec(struct file_list *fl)\n{\n    char buf[BUFSIZ];\n    register struct file_list *swap;\n    int generic;\n\n    if (fl == 0 || fl->f_type != SYSTEMSPEC) {\n        yyerror(\"internal error, bad system specification\");\n        exit(1);\n    }\n    swap = fl->f_next;\n    generic = swap && swap->f_type == SWAPSPEC && eq(swap->f_fn, \"generic\");\n    if (fl->f_rootdev == NODEV && !generic) {\n        yyerror(\"no root device specified\");\n        exit(1);\n    }\n\n    /*\n     * Default swap area to be in 'b' partition of root's\n     * device.  If root specified to be other than on 'a'\n     * partition, give warning, something probably amiss.\n     */\n    if (swap == 0 || swap->f_type != SWAPSPEC) {\n        dev_t dev;\n\n        swap = newflist(SWAPSPEC);\n        dev = fl->f_rootdev;\n        if (minor(dev) & 07) {\n            sprintf(buf,\n                \"Warning, swap defaulted to 'b' partition with root on '%c' partition\",\n                (minor(dev) & 07) + 'a' - 1);\n            yyerror(buf);\n        }\n        swap->f_swapdev =\n           makedev(major(dev), (minor(dev) &~ 07) | ('b' - 'a' + 1));\n        swap->f_fn = devtoname(swap->f_swapdev);\n        mkswap(fl, swap, 0, 0);\n    }\n\n    /*\n     * Make sure a generic swap isn't specified, along with\n     * other stuff (user must really be confused).\n     */\n    if (generic) {\n        if (fl->f_rootdev != NODEV)\n            yyerror(\"root device specified with generic swap\");\n        if (fl->f_dumpdev != NODEV)\n            yyerror(\"dump device specified with generic swap\");\n        return;\n    }\n\n    /*\n     * Default dump device and warn if place is not a\n     * swap area.\n     */\n    if (fl->f_dumpdev == NODEV)\n        fl->f_dumpdev = swap->f_swapdev;\n    if (fl->f_dumpdev != swap->f_swapdev) {\n        struct file_list *p = swap->f_next;\n\n        for (; p && p->f_type == SWAPSPEC; p = p->f_next)\n            if (fl->f_dumpdev == p->f_swapdev)\n                return;\n        (void) sprintf(buf,\n            \"Warning: dump device is not a swap partition\");\n        yyerror(buf);\n    }\n}\n\n/*\n * Verify all devices specified in the system specification\n * are present in the device specifications.\n */\nvoid\nverifysystemspecs(void)\n{\n    register struct file_list *fl;\n    dev_t checked[50];\n    register dev_t *pchecked = checked;\n\n    for (fl = conf_list; fl; fl = fl->f_next) {\n        if (fl->f_type != SYSTEMSPEC)\n            continue;\n        if (!finddev(fl->f_rootdev))\n            deverror(fl->f_needs, \"root\");\n        *pchecked++ = fl->f_rootdev;\n        pchecked = verifyswap(fl->f_next, checked, pchecked);\n\n#define samedev(dev1, dev2) \\\n    ((minor(dev1) &~ 07) != (minor(dev2) &~ 07))\n\n        if (!alreadychecked(fl->f_dumpdev, checked, pchecked)) {\n            if (!finddev(fl->f_dumpdev))\n                deverror(fl->f_needs, \"dump\");\n            *pchecked++ = fl->f_dumpdev;\n        }\n    }\n}\n\n/*\n * Do as above, but for swap devices.\n */\ndev_t *\nverifyswap(struct file_list *fl, dev_t checked[], dev_t *pchecked)\n{\n    for (;fl && fl->f_type == SWAPSPEC; fl = fl->f_next) {\n        if (eq(fl->f_fn, \"generic\"))\n            continue;\n        if (alreadychecked(fl->f_swapdev, checked, pchecked))\n            continue;\n        if (!finddev(fl->f_swapdev))\n            fprintf(stderr,\n               \"config: swap device %s not configured\", fl->f_fn);\n        *pchecked++ = fl->f_swapdev;\n    }\n    return (pchecked);\n}\n\n/*\n * Has a device already been checked\n * for it's existence in the configuration?\n */\nint\nalreadychecked(dev_t dev, dev_t *list, dev_t *last)\n{\n    register dev_t *p;\n\n    for (p = list; p < last; p++)\n        if (samedev(*p, dev))\n            return (1);\n    return (0);\n}\n\nvoid\ndeverror(char *systemname, char *devtype)\n{\n\n    fprintf(stderr, \"config: %s: %s device not configured\\n\",\n        systemname, devtype);\n}\n\n/*\n * Look for the device in the list of\n * configured hardware devices.  Must\n * take into account stuff wildcarded.\n */\n/*ARGSUSED*/\nint\nfinddev(dev_t dev)\n{\n    /* punt on this right now */\n    return (1);\n}\n"
  },
  {
    "path": "share/examples/yacc/cpy.y",
    "content": "/*\t$Id: cpy.y,v 1.18 2010/02/25 15:49:00 ragge Exp $\t*/\n\n/*\n * Copyright (c) 2004 Anders Magnusson (ragge@ludd.luth.se).\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. The name of the author may not be used to endorse or promote products\n *    derived from this software without specific prior written permission\n *\n * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\n * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\n * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\n * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\n * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright(C) Caldera International Inc. 2001-2002. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * Redistributions of source code and documentation must retain the above\n * copyright notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * All advertising materials mentioning features or use of this software\n * must display the following acknowledgement:\n * \tThis product includes software developed or owned by Caldera\n *\tInternational, Inc.\n * Neither the name of Caldera International, Inc. nor the names of other\n * contributors may be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * USE OF THE SOFTWARE PROVIDED FOR UNDER THIS LICENSE BY CALDERA\n * INTERNATIONAL, INC. AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED.  IN NO EVENT SHALL CALDERA INTERNATIONAL, INC. BE LIABLE\n * FOR ANY DIRECT, INDIRECT INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OFLIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING\n * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n */\n\n%{\n\n#include \"cpp.h\"\n\nvoid yyerror(const char *);\nint yylex(void);\nint setd(int l, int r);\n\n#define\tEVALUNARY(tok, l, r) l.nd_val = tok r.nd_val; l.op = r.op\n#define\tEVALBIN(tok, d, l, r)\t\\\n\td.op = setd(l.op, r.op); d.nd_val = l.nd_val tok r.nd_val\n#define\tEVALUBIN(tok, d, l, r, t)\t\t\t\t\\\n\td.op = setd(l.op, r.op);\t\t\t\t\\\n\tif (d.op == NUMBER) d.nd_val = l.nd_val tok r.nd_val;\t\\\n\telse d.nd_uval = l.nd_uval tok r.nd_uval;\t\t\\\n\tif (t && d.op) d.op = NUMBER\n#define\tXEVALUBIN(tok, d, l, r)\t\t\t\t\t\\\n\tif (r.nd_val) { EVALUBIN(tok, d, l, r, 0); } else d.op = 0\n%}\n\n%token stop\n%token EQ NE LE GE LS RS\n%token ANDAND OROR IDENT NUMBER UNUMBER DEFINED\n/*\n * The following terminals are not used in the yacc code.\n */\n%token STRING WSPACE CMNT\n\n%left ','\n%right '?' ':'\n%left OROR\n%left ANDAND\n%left '|' '^'\n%left '&'\n%nonassoc EQ NE\n%nonassoc '<' '>' LE GE\n%left LS RS\n%left '+' '-'\n%left '*' '/' '%'\n%right '!' '~' UMINUS\n%left '('\n\n%union {\n\tstruct nd node;\n}\n\n%type <node>\tterm e NUMBER UNUMBER\n\n%%\nS:\te '\\n'\t{\n\t\tif ($1.op == 0)\n\t\t\terror(\"division by zero\");\n\t\treturn $1.nd_val;\n\t}\n\ne:\t  e '*' e\n\t\t{ EVALUBIN(*, $$, $1, $3, 0); }\n\t| e '/' e\n\t\t{ XEVALUBIN(/, $$, $1, $3); }\n\t| e '%' e\n\t\t{ XEVALUBIN(%, $$, $1, $3); }\n\t| e '+' e\n\t\t{ EVALBIN(+, $$, $1, $3); }\n\t| e '-' e\n\t\t{ EVALBIN(-, $$, $1, $3); }\n\t| e LS e\n\t\t{ EVALBIN(<<, $$, $1, $3); }\n\t| e RS e\n\t\t{ EVALUBIN(>>, $$, $1, $3, 0); }\n\t| e '<' e\n\t\t{ EVALUBIN(<, $$, $1, $3, 1); }\n\t| e '>' e\n\t\t{ EVALUBIN(>, $$, $1, $3, 1); }\n\t| e LE e\n\t\t{ EVALUBIN(<=, $$, $1, $3, 1); }\n\t| e GE e\n\t\t{ EVALUBIN(>=, $$, $1, $3, 1); }\n\t| e EQ e\n\t\t{ EVALUBIN(==, $$, $1, $3, 1); }\n\t| e NE e\n\t\t{ EVALUBIN(!=, $$, $1, $3, 1); }\n\t| e '&' e\n\t\t{ EVALBIN(&, $$, $1, $3); }\n\t| e '^' e\n\t\t{ EVALBIN(^, $$, $1, $3); }\n\t| e '|' e\n\t\t{ EVALBIN(|, $$, $1, $3); }\n\t| e ANDAND e {\n\t\t$$ = $1;\n\t\tif ($1.nd_val) {\n\t\t\t$$.op = setd($1.op, $3.op);\n\t\t\t$$.nd_val = ($3.nd_val != 0);\n\t\t}\n\t\tif ($$.op == UNUMBER) $$.op = NUMBER;\n\t}\n\t| e OROR e {\n\t\tif ($1.nd_val != 0) {\n\t\t\t$$.nd_val = ($1.nd_val != 0);\n\t\t\t$$.op = $1.op;\n\t\t} else {\n\t\t\t$$.nd_val = ($3.nd_val != 0);\n\t\t\t$$.op = setd($1.op, $3.op);\n\t\t}\n\t\tif ($$.op == UNUMBER) $$.op = NUMBER;\n\t}\n\t| e '?' e ':' e {\n\t\tif ($1.op == 0)\n\t\t\t$$ = $1;\n\t\telse if ($1.nd_val)\n\t\t\t$$ = $3;\n\t\telse\n\t\t\t$$ = $5;\n\t}\n\t| e ',' e {\n\t\t$$.op = setd($1.op, $3.op);\n\t\t$$.nd_val = $3.nd_val;\n\t\tif ($$.op) $$.op =  $3.op;\n\t}\n\t| term\n\t\t{$$ = $1;}\nterm:\n\t  '-' term %prec UMINUS\n\t\t{ EVALUNARY(-, $$, $2); }\n\t| '+' term %prec UMINUS\n\t\t{$$ = $2;}\n\t| '!' term\n\t\t{ $$.nd_val = ! $2.nd_val; $$.op = $2.op ? NUMBER : 0; }\n\t| '~' term\n\t\t{ EVALUNARY(~, $$, $2); }\n\t| '(' e ')'\n\t\t{$$ = $2;}\n\t| DEFINED '(' NUMBER ')'\n\t\t{$$= $3;}\n\t| DEFINED NUMBER\n\t\t{$$ = $2;}\n\t| NUMBER\n\t\t{$$ = $1;}\n%%\n\nvoid\nyyerror(const char *err)\n{\n\terror(err);\n}\n\n/*\n * Set return type of an expression.\n */\nint\nsetd(int l, int r)\n{\n\tif (!l || !r)\n\t\treturn 0; /* div by zero involved */\n\tif (l == UNUMBER || r == UNUMBER)\n\t\treturn UNUMBER;\n\treturn NUMBER;\n}\n"
  },
  {
    "path": "share/examples/yacc/egrep.y",
    "content": "/*\n * egrep -- print lines containing (or not containing) a regular expression\n *\n *  status returns:\n *      0 - ok, and some matches\n *      1 - ok, but no matches\n *      2 - some error\n */\n%token CHAR DOT CCL NCCL OR CAT STAR PLUS QUEST\n%left OR\n%left CHAR DOT CCL NCCL '('\n%left CAT\n%left STAR PLUS QUEST\n\n%{\n#include <stdio.h>\n#include <stdlib.h>\n#include <fcntl.h>\n#include <unistd.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n\n#define BLKSIZE 8192\n#define MAXLIN 350\n#define MAXPOS 4000\n#define NCHARS 128\n#define NSTATES 128\n#define FINAL -1\n\nvoid    yyerror();\nint     yylex();\nint     nextch();\nvoid    synerror();\nint     enter();\nint     cclenter();\nint     node();\nint     unary();\nvoid    overflo();\nvoid    cfoll();\nvoid    cgotofn();\nint     cstate();\nint     member();\nint     notin();\nvoid    add();\nvoid    follow();\nvoid    execute();\n\nchar gotofn[NSTATES][NCHARS];\nint state[NSTATES];\nchar out[NSTATES];\nint line = 1;\nint name[MAXLIN];\nint left[MAXLIN];\nint right[MAXLIN];\nint parent[MAXLIN];\nint foll[MAXLIN];\nint positions[MAXPOS];\nchar chars[MAXLIN];\nint nxtpos;\nint nxtchar = 0;\nint tmpstat[MAXLIN];\nint initstat[MAXLIN];\nint xstate;\nint count;\nint icount;\nchar *input;\nFILE *exprfile;\n\nlong    lnum;\nint bflag;\nint cflag;\nint fflag;\nint lflag;\nint nflag;\nint hflag   = 1;\nint sflag;\nint vflag;\nint retcode = 0;\nint nfile;\nlong    blkno;\nlong    tln;\nint nsucc;\n\nint f;\nchar    *fname;\n%}\n\n%%\ns:  t\n        { unary(FINAL, $1);\n          line--;\n        }\n    ;\nt:  b r\n        { $$ = node(CAT, $1, $2); }\n    | OR b r OR\n        { $$ = node(CAT, $2, $3); }\n    | OR b r\n        { $$ = node(CAT, $2, $3); }\n    | b r OR\n        { $$ = node(CAT, $1, $2); }\n    ;\nb:\n        { $$ = enter(DOT);\n           $$ = unary(STAR, $$); }\n    ;\nr:  CHAR\n        { $$ = enter($1); }\n    | DOT\n        { $$ = enter(DOT); }\n    | CCL\n        { $$ = cclenter(CCL); }\n    | NCCL\n        { $$ = cclenter(NCCL); }\n    ;\n\nr:  r OR r\n        { $$ = node(OR, $1, $3); }\n    | r r %prec CAT\n        { $$ = node(CAT, $1, $2); }\n    | r STAR\n        { $$ = unary(STAR, $1); }\n    | r PLUS\n        { $$ = unary(PLUS, $1); }\n    | r QUEST\n        { $$ = unary(QUEST, $1); }\n    | '(' r ')'\n        { $$ = $2; }\n    | error\n    ;\n\n%%\n\nvoid\nyyerror(s) int s; {\n    fprintf(stderr, \"egrep: %s\\n\", s);\n    exit(2);\n}\n\nint\nyylex() {\n    extern int yylval;\n    int cclcnt, x;\n    register char c, d;\n    switch(c = nextch()) {\n        case '$':\n        case '^': c = '\\n';\n            goto defchar;\n        case '|': return (OR);\n        case '*': return (STAR);\n        case '+': return (PLUS);\n        case '?': return (QUEST);\n        case '(': return (c);\n        case ')': return (c);\n        case '.': return (DOT);\n        case '\\0': return (0);\n        case '\\n': return (OR);\n        case '[':\n            x = CCL;\n            cclcnt = 0;\n            count = nxtchar++;\n            if ((c = nextch()) == '^') {\n                x = NCCL;\n                c = nextch();\n            }\n            do {\n                if (c == '\\0') synerror();\n                if (c == '-' && cclcnt > 0 && chars[nxtchar-1] != 0) {\n                    if ((d = nextch()) != 0) {\n                        c = chars[nxtchar-1];\n                        while (c < d) {\n                            if (nxtchar >= MAXLIN) overflo();\n                            chars[nxtchar++] = ++c;\n                            cclcnt++;\n                        }\n                        continue;\n                    }\n                }\n                if (nxtchar >= MAXLIN) overflo();\n                chars[nxtchar++] = c;\n                cclcnt++;\n            } while ((c = nextch()) != ']');\n            chars[count] = cclcnt;\n            return (x);\n        case '\\\\':\n            if ((c = nextch()) == '\\0') synerror();\n        defchar:\n        default: yylval = c; return (CHAR);\n    }\n}\n\nint\nnextch() {\n    register char c;\n    if (fflag) {\n        if ((c = getc(exprfile)) == EOF) {\n            fclose(exprfile);\n            return(0);\n        }\n    }\n    else c = *input++;\n    return(c);\n}\n\nvoid\nsynerror() {\n    fprintf(stderr, \"egrep: syntax error\\n\");\n    exit(2);\n}\n\nint\nenter(x) int x; {\n    if(line >= MAXLIN) overflo();\n    name[line] = x;\n    left[line] = 0;\n    right[line] = 0;\n    return(line++);\n}\n\nint\ncclenter(x) int x; {\n    register int linno;\n    linno = enter(x);\n    right[linno] = count;\n    return (linno);\n}\n\nint\nnode(x, l, r) int x, l, r; {\n    if(line >= MAXLIN) overflo();\n    name[line] = x;\n    left[line] = l;\n    right[line] = r;\n    parent[l] = line;\n    parent[r] = line;\n    return(line++);\n}\n\nint\nunary(x, d) int x, d; {\n    if(line >= MAXLIN) overflo();\n    name[line] = x;\n    left[line] = d;\n    right[line] = 0;\n    parent[d] = line;\n    return(line++);\n}\n\nvoid\noverflo() {\n    fprintf(stderr, \"egrep: regular expression too long\\n\");\n    exit(2);\n}\n\nvoid\ncfoll(v) int v; {\n    register int i;\n    if (left[v] == 0) {\n        count = 0;\n        for (i=1; i<=line; i++) tmpstat[i] = 0;\n        follow(v);\n        add(foll, v);\n    }\n    else if (right[v] == 0) cfoll(left[v]);\n    else {\n        cfoll(left[v]);\n        cfoll(right[v]);\n    }\n}\n\nvoid\ncgotofn() {\n    register int c, i, k;\n    int n, s;\n    char symbol[NCHARS];\n    int j, nc, pc, pos;\n    int curpos, num;\n    int number, newpos;\n    count = 0;\n    for (n=3; n<=line; n++) tmpstat[n] = 0;\n    if (cstate(line-1)==0) {\n        tmpstat[line] = 1;\n        count++;\n        out[0] = 1;\n    }\n    for (n=3; n<=line; n++) initstat[n] = tmpstat[n];\n    count--;        /*leave out position 1 */\n    icount = count;\n    tmpstat[1] = 0;\n    add(state, 0);\n    n = 0;\n    for (s=0; s<=n; s++)  {\n        if (out[s] == 1) continue;\n        for (i=0; i<NCHARS; i++) symbol[i] = 0;\n        num = positions[state[s]];\n        count = icount;\n        for (i=3; i<=line; i++) tmpstat[i] = initstat[i];\n        pos = state[s] + 1;\n        for (i=0; i<num; i++) {\n            curpos = positions[pos];\n            if ((c = name[curpos]) >= 0) {\n                if (c < NCHARS) symbol[c] = 1;\n                else if (c == DOT) {\n                    for (k=0; k<NCHARS; k++)\n                        if (k!='\\n') symbol[k] = 1;\n                }\n                else if (c == CCL) {\n                    nc = chars[right[curpos]];\n                    pc = right[curpos] + 1;\n                    for (k=0; k<nc; k++) symbol[chars[pc++]] = 1;\n                }\n                else if (c == NCCL) {\n                    nc = chars[right[curpos]];\n                    for (j = 0; j < NCHARS; j++) {\n                        pc = right[curpos] + 1;\n                        for (k = 0; k < nc; k++)\n                            if (j==chars[pc++]) goto cont;\n                        if (j!='\\n') symbol[j] = 1;\n                        cont:;\n                    }\n                }\n                else printf(\"something's funny\\n\");\n            }\n            pos++;\n        }\n        for (c=0; c<NCHARS; c++) {\n            if (symbol[c] == 1) { /* nextstate(s,c) */\n                count = icount;\n                for (i=3; i <= line; i++) tmpstat[i] = initstat[i];\n                pos = state[s] + 1;\n                for (i=0; i<num; i++) {\n                    curpos = positions[pos];\n                    if ((k = name[curpos]) >= 0)\n                        if (\n                            (k == c)\n                            | (k == DOT)\n                            | (k == CCL && member(c, right[curpos], 1))\n                            | (k == NCCL && member(c, right[curpos], 0))\n                        ) {\n                            number = positions[foll[curpos]];\n                            newpos = foll[curpos] + 1;\n                            for (k=0; k<number; k++) {\n                                if (tmpstat[positions[newpos]] != 1) {\n                                    tmpstat[positions[newpos]] = 1;\n                                    count++;\n                                }\n                                newpos++;\n                            }\n                        }\n                    pos++;\n                } /* end nextstate */\n                if (notin(n)) {\n                    if (n >= NSTATES) overflo();\n                    add(state, ++n);\n                    if (tmpstat[line] == 1) out[n] = 1;\n                    gotofn[s][c] = n;\n                }\n                else {\n                    gotofn[s][c] = xstate;\n                }\n            }\n        }\n    }\n}\n\nint\ncstate(v) int v; {\n    register int b;\n    if (left[v] == 0) {\n        if (tmpstat[v] != 1) {\n            tmpstat[v] = 1;\n            count++;\n        }\n        return(1);\n    }\n    else if (right[v] == 0) {\n        if (cstate(left[v]) == 0) return (0);\n        else if (name[v] == PLUS) return (1);\n        else return (0);\n    }\n    else if (name[v] == CAT) {\n        if (cstate(left[v]) == 0 && cstate(right[v]) == 0) return (0);\n        else return (1);\n    }\n    else { /* name[v] == OR */\n        b = cstate(right[v]);\n        if (cstate(left[v]) == 0 || b == 0) return (0);\n        else return (1);\n    }\n}\n\nint\nmember(symb, set, torf) int symb, set, torf; {\n    register int i, num, pos;\n    num = chars[set];\n    pos = set + 1;\n    for (i=0; i<num; i++)\n        if (symb == chars[pos++]) return (torf);\n    return (!torf);\n}\n\nint\nnotin(n) int n; {\n    register int i, j, pos;\n    for (i=0; i<=n; i++) {\n        if (positions[state[i]] == count) {\n            pos = state[i] + 1;\n            for (j=0; j < count; j++)\n                if (tmpstat[positions[pos++]] != 1) goto nxt;\n            xstate = i;\n            return (0);\n        }\n        nxt: ;\n    }\n    return (1);\n}\n\nvoid\nadd(array, n) int *array, n; {\n    register int i;\n    if (nxtpos + count > MAXPOS) overflo();\n    array[n] = nxtpos;\n    positions[nxtpos++] = count;\n    for (i=3; i <= line; i++) {\n        if (tmpstat[i] == 1) {\n            positions[nxtpos++] = i;\n        }\n    }\n}\n\nvoid\nfollow(v) int v; {\n    int p;\n    if (v == line) return;\n    p = parent[v];\n    switch(name[p]) {\n        case STAR:\n        case PLUS:  cstate(v);\n                follow(p);\n                return;\n\n        case OR:\n        case QUEST: follow(p);\n                return;\n\n        case CAT:   if (v == left[p]) {\n                    if (cstate(right[p]) == 0) {\n                        follow(p);\n                        return;\n                    }\n                }\n                else follow(p);\n                return;\n        case FINAL: if (tmpstat[line] != 1) {\n                    tmpstat[line] = 1;\n                    count++;\n                }\n                return;\n    }\n}\n\nint\nmain(argc, argv)\nint argc;\nchar **argv;\n{\n    while (--argc > 0 && (++argv)[0][0]=='-')\n        switch (argv[0][1]) {\n\n        case 's':\n            sflag++;\n            continue;\n\n        case 'h':\n            hflag = 0;\n            continue;\n\n        case 'b':\n            bflag++;\n            continue;\n\n        case 'c':\n            cflag++;\n            continue;\n\n        case 'e':\n            argc--;\n            argv++;\n            goto out;\n\n        case 'f':\n            fflag++;\n            continue;\n\n        case 'l':\n            lflag++;\n            continue;\n\n        case 'n':\n            nflag++;\n            continue;\n\n        case 'v':\n            vflag++;\n            continue;\n\n        default:\n            fprintf(stderr, \"egrep: unknown flag\\n\");\n            continue;\n        }\nout:\n    if (argc<=0)\n        exit(2);\n    if (fflag) {\n        fname = *argv;\n        exprfile = fopen(fname, \"r\");\n        if (exprfile == (FILE *)NULL) {\n            fprintf(stderr, \"egrep: can't open %s\\n\", fname);\n            exit(2);\n        }\n    }\n    else input = *argv;\n    argc--;\n    argv++;\n\n    yyparse();\n\n    cfoll(line-1);\n    cgotofn();\n    nfile = argc;\n    if (argc<=0) {\n        if (lflag) exit(1);\n        execute(0);\n    }\n    else while (--argc >= 0) {\n        execute(*argv);\n        argv++;\n    }\n    exit(retcode != 0 ? retcode : nsucc == 0);\n}\n\nvoid\nexecute(file)\nchar *file;\n{\n    register char *p;\n    register int cstat;\n    register int ccount;\n    static char *buf;\n    static int blksize;\n    struct stat stb;\n    char *nlp;\n    int istat;\n    if (file) {\n        if ((f = open(file, 0)) < 0) {\n            fprintf(stderr, \"egrep: can't open %s\\n\", file);\n            retcode = 2;\n            return;\n        }\n    }\n    else f = 0;\n    if (buf == NULL) {\n        if (fstat(f, &stb) > 0 && stb.st_blksize > 0)\n            blksize = stb.st_blksize;\n        else\n            blksize = BLKSIZE;\n        buf = (char *)malloc(2*blksize);\n        if (buf == NULL) {\n            fprintf(stderr, \"egrep: no memory for %s\\n\", file);\n            retcode = 2;\n            return;\n        }\n    }\n    ccount = 0;\n    lnum = 1;\n    tln = 0;\n    blkno = 0;\n    p = buf;\n    nlp = p;\n    if ((ccount = read(f,p,blksize))<=0) goto done;\n    istat = cstat = gotofn[0]['\\n'];\n    if (out[cstat]) goto found;\n    for (;;) {\n        cstat = gotofn[cstat][*p&0377]; /* all input chars made positive */\n        if (out[cstat]) {\n        found:  for(;;) {\n                if (*p++ == '\\n') {\n                    if (vflag == 0) {\n                succeed:    nsucc = 1;\n                        if (cflag) tln++;\n                        else if (sflag)\n                            ;   /* ugh */\n                        else if (lflag) {\n                            printf(\"%s\\n\", file);\n                            close(f);\n                            return;\n                        }\n                        else {\n                            if (nfile > 1 && hflag) printf(\"%s:\", file);\n                            if (bflag) printf(\"%ld:\", blkno);\n                            if (nflag) printf(\"%ld:\", lnum);\n                            if (p <= nlp) {\n                                while (nlp < &buf[2*blksize]) putchar(*nlp++);\n                                nlp = buf;\n                            }\n                            while (nlp < p) putchar(*nlp++);\n                        }\n                    }\n                    lnum++;\n                    nlp = p;\n                    if ((out[(cstat=istat)]) == 0) goto brk2;\n                }\n                cfound:\n                if (--ccount <= 0) {\n                    if (p <= &buf[blksize]) {\n                        if ((ccount = read(f, p, blksize)) <= 0) goto done;\n                    }\n                    else if (p == &buf[2*blksize]) {\n                        p = buf;\n                        if ((ccount = read(f, p, blksize)) <= 0) goto done;\n                    }\n                    else {\n                        if ((ccount = read(f, p, &buf[2*blksize]-p)) <= 0) goto done;\n                    }\n                    blkno += ccount / 512;\n                }\n            }\n        }\n        if (*p++ == '\\n') {\n            if (vflag) goto succeed;\n            else {\n                lnum++;\n                nlp = p;\n                if (out[(cstat=istat)]) goto cfound;\n            }\n        }\n        brk2:\n        if (--ccount <= 0) {\n            if (p <= &buf[blksize]) {\n                if ((ccount = read(f, p, blksize)) <= 0) break;\n            }\n            else if (p == &buf[2*blksize]) {\n                p = buf;\n                if ((ccount = read(f, p, blksize)) <= 0) break;\n            }\n            else {\n                if ((ccount = read(f, p, &buf[2*blksize] - p)) <= 0) break;\n            }\n            blkno += ccount / 512;\n        }\n    }\ndone:   close(f);\n    if (cflag) {\n        if (nfile > 1)\n            printf(\"%s:\", file);\n        printf(\"%ld\\n\", tln);\n    }\n}\n"
  },
  {
    "path": "share/examples/yacc/expr.y",
    "content": "/* Yacc productions for \"expr\" command: */\n\n%token OR AND ADD SUBT MULT DIV REM EQ GT GEQ LT LEQ NEQ\n%token A_STRING SUBSTR LENGTH INDEX NOARG MATCH\n\n/* operators listed below in increasing precedence: */\n%left OR\n%left AND\n%left EQ LT GT GEQ LEQ NEQ\n%left ADD SUBT\n%left MULT DIV REM\n%left MCH\n%left MATCH\n%left SUBSTR\n%left LENGTH INDEX\n%%\n\n/* a single `expression' is evaluated and printed: */\n\nexpression: expr NOARG {\n            printf(\"%s\\n\", $1);\n            exit((! strcmp((char*) $1, \"0\") ||\n                  ! strcmp((char*) $1, \"\\0\")) ? 1 : 0);\n            }\n    ;\n\n\nexpr: '(' expr ')'          { $$ = (int) $2; }\n    | expr OR expr          { $$ = (int) conju(OR, $1, $3); }\n    | expr AND expr         { $$ = (int) conju(AND, $1, $3); }\n    | expr EQ expr          { $$ = (int) rel(EQ, $1, $3); }\n    | expr GT expr          { $$ = (int) rel(GT, $1, $3); }\n    | expr GEQ expr         { $$ = (int) rel(GEQ, $1, $3); }\n    | expr LT expr          { $$ = (int) rel(LT, $1, $3); }\n    | expr LEQ expr         { $$ = (int) rel(LEQ, $1, $3); }\n    | expr NEQ expr         { $$ = (int) rel(NEQ, $1, $3); }\n    | expr ADD expr         { $$ = (int) arith(ADD, $1, $3); }\n    | expr SUBT expr        { $$ = (int) arith(SUBT, $1, $3); }\n    | expr MULT expr        { $$ = (int) arith(MULT, $1, $3); }\n    | expr DIV expr         { $$ = (int) arith(DIV, $1, $3); }\n    | expr REM expr         { $$ = (int) arith(REM, $1, $3); }\n    | expr MCH expr         { $$ = (int) match($1, $3); }\n    | MATCH expr expr       { $$ = (int) match($2, $3); }\n    | SUBSTR expr expr expr { $$ = (int) substr($2, $3, $4); }\n    | LENGTH expr           { $$ = (int) length($2); }\n    | INDEX expr expr       { $$ = (int) cindex($2, $3); }\n    | A_STRING\n    ;\n%%\n/*  expression command */\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n\n#define ESIZE   256\n#define error(c)    errxx(c)\n#define EQL(x,y) !strcmp(x,y)\n\nint      yylex();\nchar    *rel();\nchar    *arith();\nchar    *conju();\nchar    *substr();\nchar    *length();\nchar    *cindex();\nchar    *match();\nint      ematch();\nvoid     errxx();\nchar    *compile();\nint      step();\nint      advance();\nvoid     getrnge();\nint      ecmp();\nvoid     yyerror();\n\nchar    **Av;\nint Ac;\nint Argi;\n\nchar Mstring[1][128];\nextern int nbra;\n\nint\nmain(argc, argv)\n    int argc;\n    char **argv;\n{\n    Ac = argc;\n    Argi = 1;\n    Av = argv;\n    yyparse();\n}\n\nchar *operators[] = { \"|\", \"&\", \"+\", \"-\", \"*\", \"/\", \"%\", \":\",\n    \"=\", \"==\", \"<\", \"<=\", \">\", \">=\", \"!=\",\n    \"match\", \"substr\", \"length\", \"index\", \"\\0\" };\nint op[] = { OR, AND, ADD,  SUBT, MULT, DIV, REM, MCH,\n    EQ, EQ, LT, LEQ, GT, GEQ, NEQ,\n    MATCH, SUBSTR, LENGTH, INDEX };\n\nint\nyylex()\n{\n    register char *p;\n    register int i;\n\n    if(Argi >= Ac) return NOARG;\n\n    p = Av[Argi++];\n\n    if(*p == '(' || *p == ')')\n        return (int)*p;\n    for(i = 0; *operators[i]; ++i)\n        if(EQL(operators[i], p))\n            return op[i];\n    yylval = (int) p;\n    return A_STRING;\n}\n\nchar *\nrel(op, r1, r2)\n    int op;\n    register char *r1, *r2;\n{\n    register long i;\n\n    if(ematch(r1, \"-*[0-9]*$\") && ematch(r2, \"[0-9]*$\"))\n        i = atol(r1) - atol(r2);\n    else\n        i = strcmp(r1, r2);\n    switch(op) {\n    case EQ: i = i==0; break;\n    case GT: i = i>0; break;\n    case GEQ: i = i>=0; break;\n    case LT: i = i<0; break;\n    case LEQ: i = i<=0; break;\n    case NEQ: i = i!=0; break;\n    }\n    return i? \"1\": \"0\";\n}\n\nchar *\narith(op, r1, r2)\n    int op;\n    char *r1, *r2;\n{\n    long i1, i2;\n    register char *rv;\n\n    if(!(ematch(r1, \"[0-9]*$\") && ematch(r2, \"[0-9]*$\")))\n        yyerror(\"non-numeric argument\");\n    i1 = atol(r1);\n    i2 = atol(r2);\n\n    switch(op) {\n    case ADD: i1 = i1 + i2; break;\n    case SUBT: i1 = i1 - i2; break;\n    case MULT: i1 = i1 * i2; break;\n    case DIV: i1 = i1 / i2; break;\n    case REM: i1 = i1 % i2; break;\n    }\n    rv = malloc(16);\n    sprintf(rv, \"%D\", i1);\n    return rv;\n}\n\nchar *\nconju(op, r1, r2)\n    int op;\n    char *r1, *r2;\n{\n    register char *rv;\n\n    switch(op) {\n\n    case OR:\n        if(EQL(r1, \"0\")\n        || EQL(r1, \"\"))\n            if(EQL(r2, \"0\")\n            || EQL(r2, \"\"))\n                rv = \"0\";\n            else\n                rv = r2;\n        else\n            rv = r1;\n        break;\n    case AND:\n        if(EQL(r1, \"0\")\n        || EQL(r1, \"\"))\n            rv = \"0\";\n        else if(EQL(r2, \"0\")\n        || EQL(r2, \"\"))\n            rv = \"0\";\n        else\n            rv = r1;\n        break;\n    }\n    return rv;\n}\n\nchar *substr(v, s, w) char *v, *s, *w;\n{\nregister int si, wi;\nregister char *res;\n\n    si = atol(s);\n    wi = atol(w);\n    while(--si) if(*v) ++v;\n\n    res = v;\n\n    while(wi--) if(*v) ++v;\n\n    *v = '\\0';\n    return res;\n}\n\nchar *length(s) register char *s;\n{\n    register int i = 0;\n    register char *rv;\n\n    while(*s++) ++i;\n\n    rv = malloc(8);\n    sprintf(rv, \"%d\", i);\n    return rv;\n}\n\nchar *cindex(s, t) char *s, *t;\n{\n    register int i, j;\n    register char *rv;\n\n    for(i = 0; s[i] ; ++i)\n        for(j = 0; t[j] ; ++j)\n            if(s[i]==t[j]) {\n                sprintf(rv = malloc(8), \"%d\", ++i);\n                return rv;\n            }\n    return \"0\";\n}\n\nchar *\nmatch(s, p)\n    char *s;\n    char *p;\n{\n    register char *rv;\n\n    sprintf(rv = malloc(8), \"%d\", ematch(s, p));\n    if(nbra) {\n        rv = malloc(strlen(Mstring[0])+1);\n        strcpy(rv, Mstring[0]);\n    }\n    return rv;\n}\n\n#define INIT    register char *sp = instring;\n#define GETC()      (*sp++)\n#define PEEKC()     (*sp)\n#define UNGETC(c)   (--sp)\n#define RETURN(c)   return(c)\n#define ERROR(c)    errxx(c)\n\nint\nematch(s, p)\nchar *s;\nregister char *p;\n{\n    static char expbuf[ESIZE];\n    char *compile();\n    register int num;\n    extern char *braslist[], *braelist[], *loc2;\n\n    compile(p, expbuf, &expbuf[ESIZE], 0);\n    if(nbra > 1)\n        yyerror(\"Too many '\\\\('s\");\n    if(advance(s, expbuf)) {\n        if(nbra == 1) {\n            p = braslist[0];\n            num = braelist[0] - p;\n            strncpy(Mstring[0], p, num);\n            Mstring[0][num] = '\\0';\n        }\n        return(loc2-s);\n    }\n    return(0);\n}\n\nvoid\nerrxx(c)\n    int c;\n{\n    yyerror(\"RE error\");\n}\n\n#define CBRA    2\n#define CCHR    4\n#define CDOT    8\n#define CCL 12\n#define CDOL    20\n#define CEOF    22\n#define CKET    24\n#define CBACK   36\n\n#define STAR    01\n#define RNGE    03\n\n#define NBRA    9\n\n#define PLACE(c)    ep[c >> 3] |= bittab[c & 07]\n#define ISTHERE(c)  (ep[c >> 3] & bittab[c & 07])\n\nchar    *braslist[NBRA];\nchar    *braelist[NBRA];\nint nbra;\nchar *loc1, *loc2, *locs;\nint sed;\n\nint circf;\nint low;\nint size;\n\nchar    bittab[] = {\n    1,\n    2,\n    4,\n    8,\n    16,\n    32,\n    64,\n    128\n};\n\nchar *\ncompile(instring, ep, endbuf, seof)\nregister char *ep;\nchar *instring, *endbuf;\nint seof;\n{\n    INIT    /* Dependent declarations and initializations */\n    register int c;\n    register int eof = seof;\n    char *lastep = instring;\n    int cclcnt;\n    char bracket[NBRA], *bracketp;\n    int closed;\n    char neg;\n    int lc;\n    int i, cflg;\n\n    lastep = 0;\n    if((c = GETC()) == eof) {\n        if(*ep == 0 && !sed)\n            ERROR(41);\n        RETURN(ep);\n    }\n    bracketp = bracket;\n    circf = closed = nbra = 0;\n    if (c == '^')\n        circf++;\n    else\n        UNGETC(c);\n    for (;;) {\n        if (ep >= endbuf)\n            ERROR(50);\n        if((c = GETC()) != '*' && ((c != '\\\\') || (PEEKC() != '{')))\n            lastep = ep;\n        if (c == eof) {\n            *ep++ = CEOF;\n            RETURN(ep);\n        }\n        switch (c) {\n\n        case '.':\n            *ep++ = CDOT;\n            continue;\n\n        case '\\n':\n            ERROR(36);\n        case '*':\n            if (lastep==0 || *lastep==CBRA || *lastep==CKET)\n                goto defchar;\n            *lastep |= STAR;\n            continue;\n\n        case '$':\n            if(PEEKC() != eof)\n                goto defchar;\n            *ep++ = CDOL;\n            continue;\n\n        case '[':\n            if(&ep[17] >= endbuf)\n                ERROR(50);\n\n            *ep++ = CCL;\n            lc = 0;\n            for(i = 0; i < 16; i++)\n                ep[i] = 0;\n\n            neg = 0;\n            if((c = GETC()) == '^') {\n                neg = 1;\n                c = GETC();\n            }\n\n            do {\n                if(c == '\\0' || c == '\\n')\n                    ERROR(49);\n                if(c == '-' && lc != 0) {\n                    if ((c = GETC()) == ']') {\n                        PLACE('-');\n                        break;\n                    }\n                    while(lc < c) {\n                        PLACE(lc);\n                        lc++;\n                    }\n                }\n                lc = c;\n                PLACE(c);\n            } while((c = GETC()) != ']');\n            if(neg) {\n                for(cclcnt = 0; cclcnt < 16; cclcnt++)\n                    ep[cclcnt] ^= -1;\n                ep[0] &= 0376;\n            }\n\n            ep += 16;\n\n            continue;\n\n        case '\\\\':\n            switch(c = GETC()) {\n\n            case '(':\n                if(nbra >= NBRA)\n                    ERROR(43);\n                *bracketp++ = nbra;\n                *ep++ = CBRA;\n                *ep++ = nbra++;\n                continue;\n\n            case ')':\n                if(bracketp <= bracket)\n                    ERROR(42);\n                *ep++ = CKET;\n                *ep++ = *--bracketp;\n                closed++;\n                continue;\n\n            case '{':\n                if(lastep == (char *) (0))\n                    goto defchar;\n                *lastep |= RNGE;\n                cflg = 0;\n            nlim:\n                c = GETC();\n                i = 0;\n                do {\n                    if ('0' <= c && c <= '9')\n                        i = 10 * i + c - '0';\n                    else\n                        ERROR(16);\n                } while(((c = GETC()) != '\\\\') && (c != ','));\n                if (i > 255)\n                    ERROR(11);\n                *ep++ = i;\n                if (c == ',') {\n                    if(cflg++)\n                        ERROR(44);\n                    if((c = GETC()) == '\\\\')\n                        *ep++ = 255;\n                    else {\n                        UNGETC(c);\n                        goto nlim; /* get 2'nd number */\n                    }\n                }\n                if(GETC() != '}')\n                    ERROR(45);\n                if(!cflg)   /* one number */\n                    *ep++ = i;\n                else if((ep[-1] & 0377) < (ep[-2] & 0377))\n                    ERROR(46);\n                continue;\n\n            case '\\n':\n                ERROR(36);\n\n            case 'n':\n                c = '\\n';\n                goto defchar;\n\n            default:\n                if(c >= '1' && c <= '9') {\n                    if((c -= '1') >= closed)\n                        ERROR(25);\n                    *ep++ = CBACK;\n                    *ep++ = c;\n                    continue;\n                }\n            }\n            /* Drop through to default to use \\ to turn off special chars */\n\n        defchar:\n        default:\n            lastep = ep;\n            *ep++ = CCHR;\n            *ep++ = c;\n        }\n    }\n}\n\nint\nstep(p1, p2)\nregister char *p1, *p2;\n{\n    register int c;\n\n    if (circf) {\n        loc1 = p1;\n        return(advance(p1, p2));\n    }\n    /* fast check for first character */\n    if (*p2==CCHR) {\n        c = p2[1];\n        do {\n            if (*p1 != c)\n                continue;\n            if (advance(p1, p2)) {\n                loc1 = p1;\n                return(1);\n            }\n        } while (*p1++);\n        return(0);\n    }\n        /* regular algorithm */\n    do {\n        if (advance(p1, p2)) {\n            loc1 = p1;\n            return(1);\n        }\n    } while (*p1++);\n    return(0);\n}\n\nint\nadvance(lp, ep)\nregister char *lp, *ep;\n{\n    register char *curlp;\n    char c;\n    char *bbeg;\n    int ct;\n\n    for (;;) switch (*ep++) {\n\n    case CCHR:\n        if (*ep++ == *lp++)\n            continue;\n        return(0);\n\n    case CDOT:\n        if (*lp++)\n            continue;\n        return(0);\n\n    case CDOL:\n        if (*lp==0)\n            continue;\n        return(0);\n\n    case CEOF:\n        loc2 = lp;\n        return(1);\n\n    case CCL:\n        c = *lp++ & 0177;\n        if(ISTHERE(c)) {\n            ep += 16;\n            continue;\n        }\n        return(0);\n    case CBRA:\n        braslist[*ep++] = lp;\n        continue;\n\n    case CKET:\n        braelist[*ep++] = lp;\n        continue;\n\n    case CCHR|RNGE:\n        c = *ep++;\n        getrnge(ep);\n        while(low--)\n            if(*lp++ != c)\n                return(0);\n        curlp = lp;\n        while(size--)\n            if(*lp++ != c)\n                break;\n        if(size < 0)\n            lp++;\n        ep += 2;\n        goto star;\n\n    case CDOT|RNGE:\n        getrnge(ep);\n        while(low--)\n            if(*lp++ == '\\0')\n                return(0);\n        curlp = lp;\n        while(size--)\n            if(*lp++ == '\\0')\n                break;\n        if(size < 0)\n            lp++;\n        ep += 2;\n        goto star;\n\n    case CCL|RNGE:\n        getrnge(ep + 16);\n        while(low--) {\n            c = *lp++ & 0177;\n            if(!ISTHERE(c))\n                return(0);\n        }\n        curlp = lp;\n        while(size--) {\n            c = *lp++ & 0177;\n            if(!ISTHERE(c))\n                break;\n        }\n        if(size < 0)\n            lp++;\n        ep += 18;       /* 16 + 2 */\n        goto star;\n\n    case CBACK:\n        bbeg = braslist[*ep];\n        ct = braelist[*ep++] - bbeg;\n\n        if(ecmp(bbeg, lp, ct)) {\n            lp += ct;\n            continue;\n        }\n        return(0);\n\n    case CBACK|STAR:\n        bbeg = braslist[*ep];\n        ct = braelist[*ep++] - bbeg;\n        curlp = lp;\n        while(ecmp(bbeg, lp, ct))\n            lp += ct;\n\n        while(lp >= curlp) {\n            if(advance(lp, ep)) return(1);\n            lp -= ct;\n        }\n        return(0);\n\n\n    case CDOT|STAR:\n        curlp = lp;\n        while (*lp++);\n        goto star;\n\n    case CCHR|STAR:\n        curlp = lp;\n        while (*lp++ == *ep);\n        ep++;\n        goto star;\n\n    case CCL|STAR:\n        curlp = lp;\n        do {\n            c = *lp++ & 0177;\n        } while(ISTHERE(c));\n        ep += 16;\n        goto star;\n\n    star:\n        do {\n            if(--lp == locs)\n                break;\n            if (advance(lp, ep))\n                return(1);\n        } while (lp > curlp);\n        return(0);\n\n    }\n}\n\nvoid\ngetrnge(str)\nregister char *str;\n{\n    low = *str++ & 0377;\n    size = *str == 255 ? 20000 : (*str &0377) - low;\n}\n\nint\necmp(a, b, count)\nregister char   *a, *b;\nregister int    count;\n{\n    if(a == b) /* should have been caught in compile() */\n        error(51);\n    while(count--)\n        if(*a++ != *b++)\n            return(0);\n    return(1);\n}\n\nvoid\nyyerror(s)\nchar *s;\n{\n    fprintf(stderr, \"%s\\n\", s);\n    exit(2);\n}\n"
  },
  {
    "path": "share/examples/yacc/gram.y",
    "content": "%{\n#include \"defs.h\"\n\nstruct depblock *pp;\nFSTATIC struct shblock *prevshp;\n\nFSTATIC struct nameblock *lefts[NLEFTS];\nstruct nameblock *leftp;\nFSTATIC int nlefts;\n\nstruct lineblock *lp, *lpp;\nFSTATIC struct depblock *prevdep;\nFSTATIC int sepc;\n\n%}\n\n%token NAME SHELLINE START MACRODEF COLON DOUBLECOLON GREATER\n\n%union {\n    struct shblock *yshblock;\n    struct depblock *ydepblock;\n    struct nameblock *ynameblock;\n}\n\n%type <yshblock> SHELLINE shlist shellist\n%type <ynameblock> NAME namelist\n%type <ydepblock> deplist dlist\n\n%%\n\nfile:\n    | file comline\n    ;\n\ncomline: START\n    | MACRODEF\n    | START namelist deplist shellist {\n        while ( --nlefts >= 0)\n        {\n        leftp = lefts[nlefts];\n        if (leftp->septype == 0)\n            leftp->septype = sepc;\n        else if (leftp->septype != sepc)\n            fprintf(stderr, \"Inconsistent rules lines for `%s'\\n\",\n                leftp->namep);\n        else if (sepc==ALLDEPS && *(leftp->namep)!='.' && $4!=0)\n            {\n            for (lp=leftp->linep; lp->nxtlineblock!=0; lp=lp->nxtlineblock)\n                if (lp->shp)\n                    fprintf(stderr, \"Multiple rules lines for `%s'\\n\",\n                        leftp->namep);\n            }\n\n        lp = ALLOC(lineblock);\n        lp->nxtlineblock = NULL;\n        lp->depp = $3;\n        lp->shp = $4;\n\n        if (! unequal(leftp->namep, \".SUFFIXES\") && $3==0)\n            leftp->linep = 0;\n        else if(leftp->linep == 0)\n            leftp->linep = lp;\n        else {\n            for (lpp = leftp->linep; lpp->nxtlineblock;\n                lpp = lpp->nxtlineblock) ;\n            if (sepc==ALLDEPS && leftp->namep[0]=='.')\n                lpp->shp = 0;\n            lpp->nxtlineblock = lp;\n            }\n        }\n    }\n    | error\n    ;\n\nnamelist: NAME      { lefts[0] = $1; nlefts = 1; }\n    | namelist NAME { lefts[nlefts++] = $2;\n            if (nlefts>=NLEFTS) fatal(\"Too many lefts\"); }\n    ;\n\ndeplist:\n        {\n        char junk[10];\n        sprintf(junk, \"%d\", yylineno);\n        fatal1(\"Must be a separator on rules line %s\", junk);\n        }\n    | dlist\n    ;\n\ndlist: sepchar   { prevdep = 0; $$ = 0; }\n    | dlist NAME {\n              pp = ALLOC(depblock);\n              pp->nxtdepblock = NULL;\n              pp->depname = $2;\n              if(prevdep == 0) $$ = pp;\n              else  prevdep->nxtdepblock = pp;\n              prevdep = pp;\n              }\n    ;\n\nsepchar: COLON      { sepc = ALLDEPS; }\n    | DOUBLECOLON   { sepc = SOMEDEPS; }\n    ;\n\nshellist:    { $$ = 0; }\n    | shlist { $$ = $1; }\n    ;\n\nshlist: SHELLINE      { $$ = $1; prevshp = $1; }\n    | shlist SHELLINE { $$ = $1;\n            prevshp->nxtshblock = $2;\n            prevshp = $2;\n            }\n    ;\n\n%%\n\nchar *zznextc;  /* zero if need another line; otherwise points to next char */\nint yylineno;\nextern FILE * fin;\n\nint retsh(q)\nchar *q;\n{\n    register char *p;\n    struct shblock *sp;\n    char *copys();\n\n    for(p=q+1 ; *p==' '||*p=='\\t' ; ++p)  ;\n\n    sp = ALLOC(shblock);\n    sp->nxtshblock = NULL;\n    sp->shbp = (fin == NULL) ? p : copys(p);\n    yylval.yshblock = sp;\n    zznextc = 0;\n    return(SHELLINE);\n}\n\nint nextlin()\n{\n    static char yytext[INMAX];\n    static char *yytextl = yytext+INMAX;\n    char *text, templin[INMAX];\n    register char c;\n    register char *p, *t;\n    char lastch, *lastchp;\n    int incom;\n    int kc;\n\nagain:\n    incom = NO;\n    zznextc = 0;\n\n    if (fin == NULL) {\n        text = *linesptr++;\n        if (text == 0)\n            return(0);\n        ++yylineno;\n    } else {\n        for (p = text = yytext; p<yytextl; *p++ = kc) {\n            switch (kc = getc(fin)) {\n            case '\\t':\n                if(p != yytext)\n                    break;\n            case ';':\n                incom = YES;\n                break;\n\n            case '#':\n                if(! incom)\n                    kc = '\\0';\n                break;\n\n            case '\\n':\n                ++yylineno;\n                if(p==yytext || p[-1]!='\\\\')\n                    {\n                    *p = '\\0';\n                    goto endloop;\n                    }\n                p[-1] = ' ';\n                while( (kc=getc(fin))=='\\t' || kc==' ' || kc=='\\n')\n                    if(kc == '\\n')\n                        ++yylineno;\n\n                if(kc != EOF)\n                    break;\n            case EOF:\n                *p = '\\0';\n                return(0);\n            }\n        }\n        fatal(\"line too long\");\n    }\nendloop:\n    if ((c = text[0]) == '\\t')\n        return retsh(text);\n\n    if (isalpha(c) || isdigit(c) || c==' ' || c=='.') {\n        for (p=text+1; *p!='\\0'; ) {\n            if (*p == ':')\n                break;\n            else if (*p++ == '=') {\n                eqsign(text);\n                return(MACRODEF);\n            }\n        }\n    }\n\n    /* substitute for macros on dependency line up to the semicolon if any */\n    for (t = yytext ; *t!='\\0' && *t!=';' ; ++t)\n        ;\n\n    lastchp = t;\n    lastch = *t;\n    *t = '\\0';\n\n    subst(yytext, templin);     /* Substitute for macros on dependency lines */\n\n    if (lastch) {\n        for (t = templin ; *t ; ++t)\n            ;\n        *t = lastch;\n        while ((*++t = *++lastchp))\n            ;\n    }\n\n    p = templin;\n    t = yytext;\n    while ((*t++ = *p++))\n        ;\n\n    for (p = zznextc = text ; *p ; ++p )\n        if (*p!=' ' && *p!='\\t')\n            return(START);\n    goto again;\n}\n\nint yylex()\n{\n    register char *p;\n    register char *q;\n    char word[INMAX];\n\n    if (zznextc == 0)\n        return nextlin();\n\n    while (isspace(*zznextc))\n        ++zznextc;\n\n    if (*zznextc == '\\0')\n        return nextlin();\n\n    if (*zznextc == ':') {\n        if (*++zznextc == ':') {\n            ++zznextc;\n            return(DOUBLECOLON);\n        } else\n            return(COLON);\n    }\n\n    if (*zznextc == '>') {\n        ++zznextc;\n        return(GREATER);\n    }\n\n    if (*zznextc == ';')\n        return retsh(zznextc);\n\n    p = zznextc;\n    q = word;\n\n    while (! (funny[(int)*p] & TERMINAL))\n        *q++ = *p++;\n\n    if (p != zznextc) {\n        *q = '\\0';\n        if((yylval.ynameblock=srchname(word))==0)\n            yylval.ynameblock = makename(word);\n        zznextc = p;\n        return(NAME);\n    } else {\n        fprintf(stderr,\"Bad character %c (octal %o), line %d\",\n            *zznextc,*zznextc,yylineno);\n        fatal( (char *) NULL );\n    }\n    return(0);  /* never executed */\n}\n"
  },
  {
    "path": "share/examples/yacc/grammar.y",
    "content": "/*\n * Copyright (c) 1987 by Ed James, UC Berkeley.  All rights reserved.\n *\n * Copy permission is hereby granted provided that this notice is\n * retained on all partial or complete copies.\n *\n * For more info on this and all of my stuff, mail edjames@berkeley.edu.\n */\n\n%token <ival>\tHeightOp\n%token <ival>\tWidthOp\n%token <ival>\tUpdateOp\n%token <ival>\tNewplaneOp\n%token <cval>\tDirOp\n%token <ival>\tConstOp\n%token <ival>\tLineOp\n%token <ival>\tAirportOp\n%token <ival>\tBeaconOp\n%token <ival>\tExitOp\n%union {\n\tint\tival;\n\tchar\tcval;\n}\n\n%{\n#include \"include.h\"\n\nint\terrors = 0;\nint\tline = 1;\n\nint yylex(void);\nint yyerror(char *s);\n%}\n\n%%\nfile:\n\tbunch_of_defs { if (checkdefs() < 0) return (errors); } bunch_of_lines\n\t\t{\n\t\tif (sp->num_exits + sp->num_airports < 2)\n\t\t\tyyerror(\"Need at least 2 airports and/or exits.\");\n\t\treturn (errors);\n\t\t}\n\t;\n\nbunch_of_defs:\n\tdef bunch_of_defs\n\t| def\n\t;\n\ndef:\n\tudef\n\t| ndef\n\t| wdef\n\t| hdef\n\t;\n\nudef:\n\tUpdateOp '=' ConstOp ';'\n\t\t{\n\t\tif (sp->update_secs != 0)\n\t\t\treturn (yyerror(\"Redefinition of 'update'.\"));\n\t\telse if ($3 < 1)\n\t\t\treturn (yyerror(\"'update' is too small.\"));\n\t\telse\n\t\t\tsp->update_secs = $3;\n\t\t}\n\t;\n\nndef:\n\tNewplaneOp '=' ConstOp ';'\n\t\t{\n\t\tif (sp->newplane_time != 0)\n\t\t\treturn (yyerror(\"Redefinition of 'newplane'.\"));\n\t\telse if ($3 < 1)\n\t\t\treturn (yyerror(\"'newplane' is too small.\"));\n\t\telse\n\t\t\tsp->newplane_time = $3;\n\t\t}\n\t;\n\nhdef:\n\tHeightOp '=' ConstOp ';'\n\t\t{\n\t\tif (sp->height != 0)\n\t\t\treturn (yyerror(\"Redefinition of 'height'.\"));\n\t\telse if ($3 < 3)\n\t\t\treturn (yyerror(\"'height' is too small.\"));\n\t\telse\n\t\t\tsp->height = $3;\n\t\t}\n\t;\n\nwdef:\n\tWidthOp '=' ConstOp ';'\n\t\t{\n\t\tif (sp->height != 0)\n\t\t\treturn (yyerror(\"Redefinition of 'width'.\"));\n\t\telse if ($3 < 3)\n\t\t\treturn (yyerror(\"'width' is too small.\"));\n\t\telse\n\t\t\tsp->width = $3;\n\t\t}\n\t;\n\nbunch_of_lines:\n\tline bunch_of_lines\n\t\t{}\n\t| line\n\t\t{}\n\t;\n\nline:\n\tBeaconOp ':' Bpoint_list ';'\n\t\t{}\n\t| ExitOp ':' Epoint_list ';'\n\t\t{}\n\t| LineOp ':' Lline_list ';'\n\t\t{}\n\t| AirportOp ':' Apoint_list ';'\n\t\t{}\n\t;\n\nBpoint_list:\n\tBpoint Bpoint_list\n\t\t{}\n\t| Bpoint\n\t\t{}\n\t;\n\nBpoint:\n\t'(' ConstOp ConstOp ')'\n\t\t{\n\t\tif (sp->num_beacons % REALLOC == 0) {\n\t\t\tif (sp->beacon == NULL)\n\t\t\t\tsp->beacon = (BEACON *) malloc((sp->num_beacons\n\t\t\t\t\t+ REALLOC) * sizeof (BEACON));\n\t\t\telse\n\t\t\t\tsp->beacon = (BEACON *) realloc(sp->beacon,\n\t\t\t\t\t(sp->num_beacons + REALLOC) *\n\t\t\t\t\tsizeof (BEACON));\n\t\t\tif (sp->beacon == NULL)\n\t\t\t\treturn (yyerror(\"No memory available.\"));\n\t\t}\n\t\tsp->beacon[sp->num_beacons].x = $2;\n\t\tsp->beacon[sp->num_beacons].y = $3;\n\t\tcheck_point($2, $3);\n\t\tsp->num_beacons++;\n\t\t}\n\t;\n\nEpoint_list:\n\tEpoint Epoint_list\n\t\t{}\n\t| Epoint\n\t\t{}\n\t;\n\nEpoint:\n\t'(' ConstOp ConstOp DirOp ')'\n\t\t{\n\t\tint\tdir;\n\n\t\tif (sp->num_exits % REALLOC == 0) {\n\t\t\tif (sp->exit == NULL)\n\t\t\t\tsp->exit = (EXIT *) malloc((sp->num_exits +\n\t\t\t\t\tREALLOC) * sizeof (EXIT));\n\t\t\telse\n\t\t\t\tsp->exit = (EXIT *) realloc(sp->exit,\n\t\t\t\t\t(sp->num_exits + REALLOC) *\n\t\t\t\t\tsizeof (EXIT));\n\t\t\tif (sp->exit == NULL)\n\t\t\t\treturn (yyerror(\"No memory available.\"));\n\t\t}\n\t\tdir = dir_no($4);\n\t\tsp->exit[sp->num_exits].x = $2;\n\t\tsp->exit[sp->num_exits].y = $3;\n\t\tsp->exit[sp->num_exits].dir = dir;\n\t\tcheck_edge($2, $3);\n\t\tcheck_edir($2, $3, dir);\n\t\tsp->num_exits++;\n\t\t}\n\t;\n\nApoint_list:\n\tApoint Apoint_list\n\t\t{}\n\t| Apoint\n\t\t{}\n\t;\n\nApoint:\n\t'(' ConstOp ConstOp DirOp ')'\n\t\t{\n\t\tint\tdir;\n\n\t\tif (sp->num_airports % REALLOC == 0) {\n\t\t\tif (sp->airport == NULL)\n\t\t\t\tsp->airport=(AIRPORT *)malloc((sp->num_airports\n\t\t\t\t\t+ REALLOC) * sizeof(AIRPORT));\n\t\t\telse\n\t\t\t\tsp->airport = (AIRPORT *) realloc(sp->airport,\n\t\t\t\t\t(sp->num_airports + REALLOC) *\n\t\t\t\t\tsizeof(AIRPORT));\n\t\t\tif (sp->airport == NULL)\n\t\t\t\treturn (yyerror(\"No memory available.\"));\n\t\t}\n\t\tdir = dir_no($4);\n\t\tsp->airport[sp->num_airports].x = $2;\n\t\tsp->airport[sp->num_airports].y = $3;\n\t\tsp->airport[sp->num_airports].dir = dir;\n\t\tcheck_point($2, $3);\n\t\tcheck_adir($2, $3, dir);\n\t\tsp->num_airports++;\n\t\t}\n\t;\n\nLline_list:\n\tLline Lline_list\n\t\t{}\n\t| Lline\n\t\t{}\n\t;\n\nLline:\n\t'[' '(' ConstOp ConstOp ')' '(' ConstOp ConstOp ')' ']'\n\t\t{\n\t\tif (sp->num_lines % REALLOC == 0) {\n\t\t\tif (sp->line == NULL)\n\t\t\t\tsp->line = (LINE *) malloc((sp->num_lines +\n\t\t\t\t\tREALLOC) * sizeof (LINE));\n\t\t\telse\n\t\t\t\tsp->line = (LINE *) realloc(sp->line,\n\t\t\t\t\t(sp->num_lines + REALLOC) *\n\t\t\t\t\tsizeof (LINE));\n\t\t\tif (sp->line == NULL)\n\t\t\t\treturn (yyerror(\"No memory available.\"));\n\t\t}\n\t\tsp->line[sp->num_lines].p1.x = $3;\n\t\tsp->line[sp->num_lines].p1.y = $4;\n\t\tsp->line[sp->num_lines].p2.x = $7;\n\t\tsp->line[sp->num_lines].p2.y = $8;\n\t\tcheck_line($3, $4, $7, $8);\n\t\tsp->num_lines++;\n\t\t}\n\t;\n%%\n\nvoid check_edge(x, y)\n{\n\tif (!(x == 0) && !(x == sp->width - 1) &&\n\t    !(y == 0) && !(y == sp->height - 1))\n\t\tyyerror(\"edge value not on edge.\");\n}\n\nvoid check_point(x, y)\n{\n\tif (x < 1 || x >= sp->width - 1)\n\t\tyyerror(\"X value out of range.\");\n\tif (y < 1 || y >= sp->height - 1)\n\t\tyyerror(\"Y value out of range.\");\n}\n\nvoid check_linepoint(x, y)\n{\n\tif (x < 0 || x >= sp->width)\n\t\tyyerror(\"X value out of range.\");\n\tif (y < 0 || y >= sp->height)\n\t\tyyerror(\"Y value out of range.\");\n}\n\nvoid check_line(x1, y1, x2, y2)\n{\n\tint\td1, d2;\n\n\tcheck_linepoint(x1, y1);\n\tcheck_linepoint(x2, y2);\n\n\td1 = ABS(x2 - x1);\n\td2 = ABS(y2 - y1);\n\n\tif (!(d1 == d2) && !(d1 == 0) && !(d2 == 0))\n\t\tyyerror(\"Bad line endpoints.\");\n}\n\nint yyerror(char *s)\n{\n\tfprintf(stderr, \"\\\"%s\\\": line %d: %s\\n\", file, line, s);\n\terrors++;\n\n\treturn (errors);\n}\n\nvoid check_edir(x, y, dir)\n{\n\tint\tbad = 0;\n\n\tif (x == sp->width - 1)\n\t\tx = 2;\n\telse if (x != 0)\n\t\tx = 1;\n\tif (y == sp->height - 1)\n\t\ty = 2;\n\telse if (y != 0)\n\t\ty = 1;\n\n\tswitch (x * 10 + y) {\n\tcase 00: if (dir != 3) bad++; break;\n\tcase 01: if (dir < 1 || dir > 3) bad++; break;\n\tcase 02: if (dir != 1) bad++; break;\n\tcase 10: if (dir < 3 || dir > 5) bad++; break;\n\tcase 11: break;\n\tcase 12: if (dir > 1 && dir < 7) bad++; break;\n\tcase 20: if (dir != 5) bad++; break;\n\tcase 21: if (dir < 5) bad++; break;\n\tcase 22: if (dir != 7) bad++; break;\n\tdefault:\n\t\tyyerror(\"Unknown value in checkdir!  Get help!\");\n\t\tbreak;\n\t}\n\tif (bad)\n\t\tyyerror(\"Bad direction for entrance at exit.\");\n}\n\nvoid check_adir(x, y, dir)\n{\n}\n\nint checkdefs()\n{\n\tint\terr = 0;\n\n\tif (sp->width == 0) {\n\t\tyyerror(\"'width' undefined.\");\n\t\terr++;\n\t}\n\tif (sp->height == 0) {\n\t\tyyerror(\"'height' undefined.\");\n\t\terr++;\n\t}\n\tif (sp->update_secs == 0) {\n\t\tyyerror(\"'update' undefined.\");\n\t\terr++;\n\t}\n\tif (sp->newplane_time == 0) {\n\t\tyyerror(\"'newplane' undefined.\");\n\t\terr++;\n\t}\n\tif (err)\n\t\treturn (-1);\n\telse\n\t\treturn (0);\n}\n"
  },
  {
    "path": "share/examples/yacc/parser.y",
    "content": "%token CHAR CCL NCCL STR DELIM SCON ITER NEWE NULLS\n%left SCON '/' NEWE\n%left '|'\n%left '$' '^'\n%left CHAR CCL NCCL '(' '.' STR NULLS\n%left ITER\n%left CAT\n%left '*' '+' '?'\n\n%{\n# include \"ldefs.h\"\n\nint i;\nint j,k;\nint g;\nuchar *p;\n\n#define YYSTYPE union _yystype_\nunion _yystype_\n{\n\tint\ti;\n\tuchar\t*cp;\n};\n%}\n\n%%\n\nacc\t:\tlexinput\n\t{\n# ifdef DEBUG\n\t\tif(debug) sect2dump();\n# endif\n\t}\n\t;\nlexinput:\tdefns delim prods end\n\t|\tdefns delim end\n\t{\n\t\tif(!funcflag)phead2();\n\t\tfuncflag = TRUE;\n\t}\n\t| error\n\t{\n# ifdef DEBUG\n\t\tif(debug) {\n\t\t\tsect1dump();\n\t\t\tsect2dump();\n\t\t\t}\n# endif\n\t\t}\n\t;\nend:\t\tdelim | ;\ndefns:\tdefns STR STR\n\t{\tstrcpy((char*)dp,(char*)$2.cp);\n\t\tdef[dptr] = dp;\n\t\tdp += strlen((char*)$2.cp) + 1;\n\t\tstrcpy((char*)dp,(char*)$3.cp);\n\t\tsubs[dptr++] = dp;\n\t\tif(dptr >= DEFSIZE)\n\t\t\terror(\"Too many definitions\");\n\t\tdp += strlen((char*)$3.cp) + 1;\n\t\tif(dp >= dchar+DEFCHAR)\n\t\t\terror(\"Definitions too long\");\n\t\tsubs[dptr]=def[dptr]=0;\t/* for lookup - require ending null */\n\t}\n\t|\n\t;\ndelim:\tDELIM\n\t{\n# ifdef DEBUG\n\t\tif(sect == DEFSECTION && debug) sect1dump();\n# endif\n\t\tsect++;\n\t\t}\n\t;\nprods:\tprods pr\n\t{\t$$.i = mn2(RNEWE,$1.i,$2.i);\n\t\t}\n\t|\tpr\n\t{\t$$.i = $1.i;}\n\t;\npr:\tr NEWE\n\t{\n\t\tif(divflg == TRUE)\n\t\t\ti = mn1(S1FINAL,casecount);\n\t\telse i = mn1(FINAL,casecount);\n\t\t$$.i = mn2(RCAT,$1.i,i);\n\t\tdivflg = FALSE;\n\t\tcasecount++;\n\t\t}\n\t| error NEWE\n\t{\n# ifdef DEBUG\n\t\tif(debug) sect2dump();\n# endif\n\t\t}\nr:\tCHAR\n\t{\t$$.i = mn0($1.i); }\n\t| STR\n\t{\n\t\tp = $1.cp;\n\t\ti = mn0(*p++);\n\t\twhile(*p)\n\t\t\ti = mn2(RSTR,i,*p++);\n\t\t$$.i = i;\n\t\t}\n\t| '.'\n\t{\tsymbol['\\n'] = 0;\n\t\tif(psave == FALSE){\n\t\t\tp = ccptr;\n\t\t\tpsave = ccptr;\n\t\t\tfor(i=1;i<'\\n';i++){\n\t\t\t\tsymbol[i] = 1;\n\t\t\t\t*ccptr++ = i;\n\t\t\t\t}\n\t\t\tfor(i='\\n'+1;i<NCH;i++){\n\t\t\t\tsymbol[i] = 1;\n\t\t\t\t*ccptr++ = i;\n\t\t\t\t}\n\t\t\t*ccptr++ = 0;\n\t\t\tif(ccptr > ccl+CCLSIZE)\n\t\t\t\terror(\"Too many large character classes\");\n\t\t\t}\n\t\telse\n\t\t\tp = psave;\n\t\t$$.i = mnp(RCCL, p);\n\t\tcclinter(1);\n\t\t}\n\t| CCL\n\t{\t$$.i = mnp(RCCL,$1.cp); }\n\t| NCCL\n\t{\t$$.i = mnp(RNCCL,$1.cp); }\n\t| r '*'\n\t{\t$$.i = mn1(STAR,$1.i); }\n\t| r '+'\n\t{\t$$.i = mn1(PLUS,$1.i); }\n\t| r '?'\n\t{\t$$.i = mn1(QUEST,$1.i); }\n\t| r '|' r\n\t{\t$$.i = mn2(BAR,$1.i,$3.i); }\n\t| r r %prec CAT\n\t{\t$$.i = mn2(RCAT,$1.i,$2.i); }\n\t| r '/' r\n\t{\tif(!divflg){\n\t\t\tj = mn1(S2FINAL,-casecount);\n\t\t\ti = mn2(RCAT,$1.i,j);\n\t\t\t$$.i = mn2(DIV,i,$3.i);\n\t\t\t}\n\t\telse {\n\t\t\t$$.i = mn2(RCAT,$1.i,$3.i);\n\t\t\twarning(\"Extra slash removed\");\n\t\t\t}\n\t\tdivflg = TRUE;\n\t\t}\n\t| r ITER ',' ITER '}'\n\t{\tif($2.i > $4.i){\n\t\t\ti = $2.i;\n\t\t\t$2.i = $4.i;\n\t\t\t$4.i = i;\n\t\t\t}\n\t\tif($4.i <= 0)\n\t\t\twarning(\"Iteration range must be positive\");\n\t\telse {\n\t\t\tj = $1.i;\n\t\t\tfor(k = 2; k<=$2.i;k++)\n\t\t\t\tj = mn2(RCAT,j,dupl($1.i));\n\t\t\tfor(i = $2.i+1; i<=$4.i; i++){\n\t\t\t\tg = dupl($1.i);\n\t\t\t\tfor(k=2;k<=i;k++)\n\t\t\t\t\tg = mn2(RCAT,g,dupl($1.i));\n\t\t\t\tj = mn2(BAR,j,g);\n\t\t\t\t}\n\t\t\t$$.i = j;\n\t\t\t}\n\t}\n\t| r ITER '}'\n\t{\n\t\tif($2.i < 0)warning(\"Can't have negative iteration\");\n\t\telse if($2.i == 0) $$.i = mn0(RNULLS);\n\t\telse {\n\t\t\tj = $1.i;\n\t\t\tfor(k=2;k<=$2.i;k++)\n\t\t\t\tj = mn2(RCAT,j,dupl($1.i));\n\t\t\t$$.i = j;\n\t\t\t}\n\t\t}\n\t| r ITER ',' '}'\n\t{\n\t\t\t\t/* from n to infinity */\n\t\tif($2.i < 0)warning(\"Can't have negative iteration\");\n\t\telse if($2.i == 0) $$.i = mn1(STAR,$1.i);\n\t\telse if($2.i == 1)$$.i = mn1(PLUS,$1.i);\n\t\telse {\t\t/* >= 2 iterations minimum */\n\t\t\tj = $1.i;\n\t\t\tfor(k=2;k<$2.i;k++)\n\t\t\t\tj = mn2(RCAT,j,dupl($1.i));\n\t\t\tk = mn1(PLUS,dupl($1.i));\n\t\t\t$$.i = mn2(RCAT,j,k);\n\t\t\t}\n\t\t}\n\t| SCON r\n\t{\t$$.i = mn2(RSCON,$2.i,(uintptr)$1.cp); }\n\t| '^' r\n\t{\t$$.i = mn1(CARAT,$2.i); }\n\t| r '$'\n\t{\ti = mn0('\\n');\n\t\tif(!divflg){\n\t\t\tj = mn1(S2FINAL,-casecount);\n\t\t\tk = mn2(RCAT,$1.i,j);\n\t\t\t$$.i = mn2(DIV,k,i);\n\t\t\t}\n\t\telse $$.i = mn2(RCAT,$1.i,i);\n\t\tdivflg = TRUE;\n\t\t}\n\t| '(' r ')'\n\t{\t$$.i = $2.i; }\n\t|\tNULLS\n\t{\t$$.i = mn0(RNULLS); }\n\t;\n%%\nint\nyylex(void)\n{\n\tuchar *p;\n\tint c, i;\n\tuchar  *t, *xp;\n\tint n, j, k, x;\n\tstatic int sectbegin;\n\tstatic uchar token[TOKENSIZE];\n\tstatic int iter;\n\n# ifdef DEBUG\n\tyylval.i = 0;\n\tyylval.cp = 0;\n# endif\n\n\tif(sect == DEFSECTION) {\t\t/* definitions section */\n\t\twhile(!eof) {\n\t\t\tif(prev == '\\n'){\t\t/* next char is at beginning of line */\n\t\t\t\tgetl(p=buf);\n\t\t\t\tswitch(*p){\n\t\t\t\tcase '%':\n\t\t\t\t\tswitch(*(p+1)){\n\t\t\t\t\tcase '%':\n\t\t\t\t\t\tlgate();\n\t\t\t\t\t\tfprintf(fout,\"#define YYNEWLINE %d\\n\",'\\n');\n\t\t\t\t\t\tfprintf(fout,\"int\\nyylex(void){\\nint nstr; extern int yyprevious;\\n\");\n\t\t\t\t\t\tsectbegin = TRUE;\n\t\t\t\t\t\ti = treesize*(sizeof(*name)+sizeof(*left)+\n\t\t\t\t\t\t\tsizeof(*right)+sizeof(*nullstr)+sizeof(*parent))+ALITTLEEXTRA;\n\t\t\t\t\t\tp = myalloc(i,1);\n\t\t\t\t\t\tif(p == 0)\n\t\t\t\t\t\t\terror(\"Too little core for parse tree\");\n\t\t\t\t\t\tfree(p);\n\t\t\t\t\t\tname = myalloc(treesize,sizeof(*name));\n\t\t\t\t\t\tleft = myalloc(treesize,sizeof(*left));\n\t\t\t\t\t\tright = myalloc(treesize,sizeof(*right));\n\t\t\t\t\t\tnullstr = myalloc(treesize,sizeof(*nullstr));\n\t\t\t\t\t\tparent = myalloc(treesize,sizeof(*parent));\n\t\t\t\t\t\tptr = myalloc(treesize,sizeof(*ptr));\n\t\t\t\t\t\tif(name == 0 || left == 0 || right == 0 || parent == 0 || nullstr == 0 || ptr == 0)\n\t\t\t\t\t\t\terror(\"Too little core for parse tree\");\n\t\t\t\t\t\treturn(freturn(DELIM));\n\t\t\t\t\tcase 'p': case 'P':\t/* has overridden number of positions */\n\t\t\t\t\t\twhile(*p && !isdigit(*p))p++;\n\t\t\t\t\t\tmaxpos = atol((char*)p);\n# ifdef DEBUG\n\t\t\t\t\t\tif (debug) printf(\"positions (%%p) now %d\\n\",maxpos);\n# endif\n\t\t\t\t\t\tif(report == 2)report = 1;\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\tcase 'n': case 'N':\t/* has overridden number of states */\n\t\t\t\t\t\twhile(*p && !isdigit(*p))p++;\n\t\t\t\t\t\tnstates = atol((char*)p);\n# ifdef DEBUG\n\t\t\t\t\t\tif(debug)printf( \" no. states (%%n) now %d\\n\",nstates);\n# endif\n\t\t\t\t\t\tif(report == 2)report = 1;\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\tcase 'e': case 'E':\t\t/* has overridden number of tree nodes */\n\t\t\t\t\t\twhile(*p && !isdigit(*p))p++;\n\t\t\t\t\t\ttreesize = atol((char*)p);\n# ifdef DEBUG\n\t\t\t\t\t\tif (debug) printf(\"treesize (%%e) now %d\\n\",treesize);\n# endif\n\t\t\t\t\t\tif(report == 2)report = 1;\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\tcase 'o': case 'O':\n\t\t\t\t\t\twhile (*p && !isdigit(*p))p++;\n\t\t\t\t\t\toutsize = atol((char*)p);\n\t\t\t\t\t\tif (report ==2) report=1;\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\tcase 'a': case 'A':\t\t/* has overridden number of transitions */\n\t\t\t\t\t\twhile(*p && !isdigit(*p))p++;\n\t\t\t\t\t\tif(report == 2)report = 1;\n\t\t\t\t\t\tntrans = atol((char*)p);\n# ifdef DEBUG\n\t\t\t\t\t\tif (debug)printf(\"N. trans (%%a) now %d\\n\",ntrans);\n# endif\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\tcase 'k': case 'K': /* overriden packed char classes */\n\t\t\t\t\t\twhile (*p && !isdigit(*p))p++;\n\t\t\t\t\t\tif (report==2) report=1;\n\t\t\t\t\t\tfree(pchar);\n\t\t\t\t\t\tpchlen = atol((char*)p);\n# ifdef DEBUG\n\t\t\t\t\t\tif (debug) printf( \"Size classes (%%k) now %d\\n\",pchlen);\n# endif\n\t\t\t\t\t\tpchar=pcptr=myalloc(pchlen, sizeof(*pchar));\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\tcase '{':\n\t\t\t\t\t\tlgate();\n\t\t\t\t\t\twhile(getl(p) && strcmp((char*)p,\"%}\") != 0)\n\t\t\t\t\t\t\tfprintf(fout, \"%s\\n\",(char*)p);\n\t\t\t\t\t\tif(p[0] == '%') continue;\n\t\t\t\t\t\terror(\"Premature eof\");\n\t\t\t\t\tcase 's': case 'S':\t\t/* start conditions */\n\t\t\t\t\t\tlgate();\n\t\t\t\t\t\twhile(*p && strchr(\" \\t,\", *p) == 0) p++;\n\t\t\t\t\t\tn = TRUE;\n\t\t\t\t\t\twhile(n){\n\t\t\t\t\t\t\twhile(*p && strchr(\" \\t,\", *p)) p++;\n\t\t\t\t\t\t\tt = p;\n\t\t\t\t\t\t\twhile(*p && strchr(\" \\t,\", *p) == 0)p++;\n\t\t\t\t\t\t\tif(!*p) n = FALSE;\n\t\t\t\t\t\t\t*p++ = 0;\n\t\t\t\t\t\t\tif (*t == 0) continue;\n\t\t\t\t\t\t\ti = sptr*2;\n\t\t\t\t\t\t\tfprintf(fout,\"#define %s %d\\n\",(char*)t,i);\n\t\t\t\t\t\t\tstrcpy((char*)sp, (char*)t);\n\t\t\t\t\t\t\tsname[sptr++] = sp;\n\t\t\t\t\t\t\tsname[sptr] = 0;\t/* required by lookup */\n\t\t\t\t\t\t\tif(sptr >= STARTSIZE)\n\t\t\t\t\t\t\t\terror(\"Too many start conditions\");\n\t\t\t\t\t\t\tsp += strlen((char*)sp) + 1;\n\t\t\t\t\t\t\tif(sp >= stchar+STARTCHAR)\n\t\t\t\t\t\t\t\terror(\"Start conditions too long\");\n\t\t\t\t\t\t}\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\tdefault:\n\t\t\t\t\t\twarning(\"Invalid request %s\",p);\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\t}\t/* end of switch after seeing '%' */\n\t\t\t\tcase ' ': case '\\t':\t\t/* must be code */\n\t\t\t\t\tlgate();\n\t\t\t\t\tfprintf(fout, \"%s\\n\",(char*)p);\n\t\t\t\t\tcontinue;\n\t\t\t\tdefault:\t\t/* definition */\n\t\t\t\t\twhile(*p && !isspace(*p)) p++;\n\t\t\t\t\tif(*p == 0)\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\tprev = *p;\n\t\t\t\t\t*p = 0;\n\t\t\t\t\tbptr = p+1;\n\t\t\t\t\tyylval.cp = buf;\n\t\t\t\t\tif(isdigit(buf[0]))\n\t\t\t\t\t\twarning(\"Substitution strings may not begin with digits\");\n\t\t\t\t\treturn(freturn(STR));\n\t\t\t\t}\n\t\t\t}\n\t\t\t/* still sect 1, but prev != '\\n' */\n\t\t\telse {\n\t\t\t\tp = bptr;\n\t\t\t\twhile(*p && isspace(*p)) p++;\n\t\t\t\tif(*p == 0)\n\t\t\t\t\twarning(\"No translation given - null string assumed\");\n\t\t\t\tstrcpy((char*)token, (char*)p);\n\t\t\t\tyylval.cp = token;\n\t\t\t\tprev = '\\n';\n\t\t\t\treturn(freturn(STR));\n\t\t\t}\n\t\t}\n\t\t/* end of section one processing */\n\t} else if(sect == RULESECTION){\t\t/* rules and actions */\n\t\twhile(!eof){\n\t\t\tswitch(c=gch()){\n\t\t\tcase '\\0':\n\t\t\t\treturn(freturn(0));\n\t\t\tcase '\\n':\n\t\t\t\tif(prev == '\\n') continue;\n\t\t\t\tx = NEWE;\n\t\t\t\tbreak;\n\t\t\tcase ' ':\n\t\t\tcase '\\t':\n\t\t\t\tif(sectbegin == TRUE){\n\t\t\t\t\tcpyact();\n\t\t\t\t\twhile((c=gch()) && c != '\\n');\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t\tif(!funcflag)phead2();\n\t\t\t\tfuncflag = TRUE;\n\t\t\t\tfprintf(fout,\"case %d:\\n\",casecount);\n\t\t\t\tif(cpyact())\n\t\t\t\t\tfprintf(fout,\"break;\\n\");\n\t\t\t\twhile((c=gch()) && c != '\\n');\n\t\t\t\tif(peek == ' ' || peek == '\\t' || sectbegin == TRUE){\n\t\t\t\t\twarning(\"Executable statements should occur right after %%\");\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t\tx = NEWE;\n\t\t\t\tbreak;\n\t\t\tcase '%':\n\t\t\t\tif(prev != '\\n') goto character;\n\t\t\t\tif(peek == '{'){\t/* included code */\n\t\t\t\t\tgetl(buf);\n\t\t\t\t\twhile(!eof && getl(buf) && strcmp(\"%}\",(char*)buf) != 0)\n\t\t\t\t\t\tfprintf(fout,\"%s\\n\",(char*)buf);\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t\tif(peek == '%'){\n\t\t\t\t\tgch();\n\t\t\t\t\tgch();\n\t\t\t\t\tx = DELIM;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tgoto character;\n\t\t\tcase '|':\n\t\t\t\tif(peek == ' ' || peek == '\\t' || peek == '\\n'){\n/* XXX Plan 9 uses this line instead ??\tfprintf(fout,\"%d\\n\",30000+casecount++); XXX */\n\t\t\t\t\tfprintf(fout,\"case %d:\\n\",casecount++);\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t\tx = '|';\n\t\t\t\tbreak;\n\t\t\tcase '$':\n\t\t\t\tif(peek == '\\n' || peek == ' ' || peek == '\\t' || peek == '|' || peek == '/'){\n\t\t\t\t\tx = c;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tgoto character;\n\t\t\tcase '^':\n\t\t\t\tif(prev != '\\n' && scon != TRUE) goto character;\t/* valid only at line begin */\n\t\t\t\tx = c;\n\t\t\t\tbreak;\n\t\t\tcase '?':\n\t\t\tcase '+':\n\t\t\tcase '.':\n\t\t\tcase '*':\n\t\t\tcase '(':\n\t\t\tcase ')':\n\t\t\tcase ',':\n\t\t\tcase '/':\n\t\t\t\tx = c;\n\t\t\t\tbreak;\n\t\t\tcase '}':\n\t\t\t\titer = FALSE;\n\t\t\t\tx = c;\n\t\t\t\tbreak;\n\t\t\tcase '{':\t/* either iteration or definition */\n\t\t\t\tif(isdigit(c=gch())){\t/* iteration */\n\t\t\t\t\titer = TRUE;\n\t\t\t\tieval:\n\t\t\t\t\ti = 0;\n\t\t\t\t\twhile(isdigit(c)){\n\t\t\t\t\t\ttoken[i++] = c;\n\t\t\t\t\t\tc = gch();\n\t\t\t\t\t}\n\t\t\t\t\ttoken[i] = 0;\n\t\t\t\t\tyylval.i = atol((char*)token);\n\t\t\t\t\tmunputc(c);\n\t\t\t\t\tx = ITER;\n\t\t\t\t\tbreak;\n\t\t\t\t} else {\t\t/* definition */\n\t\t\t\t\ti = 0;\n\t\t\t\t\twhile(c && c!='}'){\n\t\t\t\t\t\ttoken[i++] = c;\n\t\t\t\t\t\tc = gch();\n\t\t\t\t\t}\n\t\t\t\t\ttoken[i] = 0;\n\t\t\t\t\ti = lookup(token,def);\n\t\t\t\t\tif(i < 0)\n\t\t\t\t\t\twarning(\"Definition %s not found\",token);\n\t\t\t\t\telse\n\t\t\t\t\t\tmunputs(subs[i]);\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\tcase '<':\t\t/* start condition ? */\n\t\t\t\tif(prev != '\\n')\t\t/* not at line begin, not start */\n\t\t\t\t\tgoto character;\n\t\t\t\tt = slptr;\n\t\t\t\tdo {\n\t\t\t\t\ti = 0;\n\t\t\t\t\tc = gch();\n\t\t\t\t\twhile(c != ',' && c && c != '>'){\n\t\t\t\t\t\ttoken[i++] = c;\n\t\t\t\t\t\tc = gch();\n\t\t\t\t\t}\n\t\t\t\t\ttoken[i] = 0;\n\t\t\t\t\tif(i == 0)\n\t\t\t\t\t\tgoto character;\n\t\t\t\t\ti = lookup(token,sname);\n\t\t\t\t\tif(i < 0) {\n\t\t\t\t\t\twarning(\"Undefined start condition %s\",token);\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\t}\n\t\t\t\t\t*slptr++ = i+1;\n\t\t\t\t} while(c && c != '>');\n\t\t\t\t*slptr++ = 0;\n\t\t\t\t/* check if previous value re-usable */\n\t\t\t\tfor (xp=slist; xp<t; ){\n\t\t\t\t\tif (strcmp((char*)xp, (char*)t)==0)\n\t\t\t\t\t\tbreak;\n\t\t\t\t\twhile (*xp++);\n\t\t\t\t}\n\t\t\t\tif (xp<t){\n\t\t\t\t\t/* re-use previous pointer to string */\n\t\t\t\t\tslptr=t;\n\t\t\t\t\tt=xp;\n\t\t\t\t}\n\t\t\t\tif(slptr > slist+STARTSIZE)\t\t/* note not packed ! */\n\t\t\t\t\terror(\"Too many start conditions used\");\n\t\t\t\tyylval.cp = t;\n\t\t\t\tx = SCON;\n\t\t\t\tbreak;\n\t\t\tcase '\"':\n\t\t\t\ti = 0;\n\t\t\t\twhile((c=gch()) && c != '\"' && c != '\\n'){\n\t\t\t\t\tif(c == '\\\\') c = usescape(gch());\n\t\t\t\t\ttoken[i++] = c;\n\t\t\t\t\tif(i > TOKENSIZE){\n\t\t\t\t\t\twarning(\"String too long\");\n\t\t\t\t\t\ti = TOKENSIZE-1;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif(c == '\\n') {\n\t\t\t\t\tyyline--;\n\t\t\t\t\twarning(\"Non-terminated string\");\n\t\t\t\t\tyyline++;\n\t\t\t\t}\n\t\t\t\ttoken[i] = 0;\n\t\t\t\tif(i == 0)x = NULLS;\n\t\t\t\telse if(i == 1){\n\t\t\t\t\tyylval.i = token[0];\n\t\t\t\t\tx = CHAR;\n\t\t\t\t} else {\n\t\t\t\t\tyylval.cp = token;\n\t\t\t\t\tx = STR;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase '[':\n\t\t\t\tfor(i=1;i<NCH;i++) symbol[i] = 0;\n\t\t\t\tx = CCL;\n\t\t\t\tif((c = gch()) == '^'){\n\t\t\t\t\tx = NCCL;\n\t\t\t\t\tc = gch();\n\t\t\t\t}\n\t\t\t\twhile(c != ']' && c){\n\t\t\t\t\tif(c == '\\\\') c = usescape(gch());\n\t\t\t\t\tsymbol[c] = 1;\n\t\t\t\t\tj = c;\n\t\t\t\t\tif((c=gch()) == '-' && peek != ']'){\t\t/* range specified */\n\t\t\t\t\t\tc = gch();\n\t\t\t\t\t\tif(c == '\\\\') c = usescape(gch());\n\t\t\t\t\t\tk = c;\n\t\t\t\t\t\tif(j > k) {\n\t\t\t\t\t\t\tn = j;\n\t\t\t\t\t\t\tj = k;\n\t\t\t\t\t\t\tk = n;\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif(!(('A' <= j && k <= 'Z') ||\n\t\t\t\t\t\t     ('a' <= j && k <= 'z') ||\n\t\t\t\t\t\t     ('0' <= j && k <= '9')))\n\t\t\t\t\t\t\twarning(\"Non-portable Character Class\");\n\t\t\t\t\t\tfor(n=j+1;n<=k;n++)\n\t\t\t\t\t\t\tsymbol[n] = 1;\t\t/* implementation dependent */\n\t\t\t\t\t\tc = gch();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t/* try to pack ccl's */\n\t\t\t\ti = 0;\n\t\t\t\tfor(j=0;j<NCH;j++)\n\t\t\t\t\tif(symbol[j])token[i++] = j;\n\t\t\t\ttoken[i] = 0;\n\t\t\t\tp = ccptr;\n\t\t\t\tif(optim){\n\t\t\t\t\tp = ccl;\n\t\t\t\t\twhile(p <ccptr && strcmp((char*)token,(char*)p) != 0)p++;\n\t\t\t\t}\n\t\t\t\tif(p < ccptr)\t/* found it */\n\t\t\t\t\tyylval.cp = p;\n\t\t\t\telse {\n\t\t\t\t\tyylval.cp = ccptr;\n\t\t\t\t\tstrcpy((char*)ccptr,(char*)token);\n\t\t\t\t\tccptr += strlen((char*)token) + 1;\n\t\t\t\t\tif(ccptr >= ccl+CCLSIZE)\n\t\t\t\t\t\terror(\"Too many large character classes\");\n\t\t\t\t}\n\t\t\t\tcclinter(x==CCL);\n\t\t\t\tbreak;\n\t\t\tcase '\\\\':\n\t\t\t\tc = usescape(gch());\n\t\t\tdefault:\n\t\t\tcharacter:\n\t\t\t\tif(iter){\t/* second part of an iteration */\n\t\t\t\t\titer = FALSE;\n\t\t\t\t\tif('0' <= c && c <= '9')\n\t\t\t\t\t\tgoto ieval;\n\t\t\t\t}\n\t\t\t\tif(isalpha(peek)){\n\t\t\t\t\ti = 0;\n\t\t\t\t\tyylval.cp = token;\n\t\t\t\t\ttoken[i++] = c;\n\t\t\t\t\twhile(isalpha(peek))\n\t\t\t\t\t\ttoken[i++] = gch();\n\t\t\t\t\tif(peek == '?' || peek == '*' || peek == '+')\n\t\t\t\t\t\tmunputc(token[--i]);\n\t\t\t\t\ttoken[i] = 0;\n\t\t\t\t\tif(i == 1){\n\t\t\t\t\t\tyylval.i = token[0];\n\t\t\t\t\t\tx = CHAR;\n\t\t\t\t\t}\n\t\t\t\t\telse x = STR;\n\t\t\t\t} else {\n\t\t\t\t\tyylval.i = c;\n\t\t\t\t\tx = CHAR;\n\t\t\t\t}\n\t\t\t}\n\t\t\tscon = FALSE;\n\t\t\tif(x == SCON)scon = TRUE;\n\t\t\tsectbegin = FALSE;\n\t\t\treturn(freturn(x));\n\t\t}\n\t}\n\t/* section three */\n\tptail();\n# ifdef DEBUG\n\tif(debug)\n\t\tfprintf(fout,\"\\n/*this comes from section three - debug */\\n\");\n# endif\n\twhile(getl(buf) && !eof)\n\t\tfprintf(fout,\"%s\\n\",(char*)buf);\n\treturn(freturn(0));\n}\n/* end of yylex */\n# ifdef DEBUG\nint\nfreturn(int i)\n{\n\tif(yydebug) {\n\t\tprintf(\"now return \");\n\t\tif(i < NCH) allprint(i);\n\t\telse printf(\"%d\",i);\n\t\tprintf(\"   yylval = \");\n\t\tswitch(i){\n\t\t\tcase STR: case CCL: case NCCL:\n\t\t\t\tstrpt(yylval.cp);\n\t\t\t\tbreak;\n\t\t\tcase CHAR:\n\t\t\t\tallprint(yylval.i);\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tprintf(\"%d\",yylval.i);\n\t\t\t\tbreak;\n\t\t}\n\t\tputchar('\\n');\n\t}\n\treturn(i);\n}\n# endif\n"
  },
  {
    "path": "share/man/.gitignore",
    "content": "whatis.db\n"
  },
  {
    "path": "share/man/Makefile",
    "content": "#\n# Copyright (c) 1987 Regents of the University of California.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms are permitted\n# provided that the above copyright notice and this paragraph are\n# duplicated in all such forms and that any documentation,\n# advertising materials, and other materials related to such\n# distribution and use acknowledge that the software was developed\n# by the University of California, Berkeley.  The name of the\n# University may not be used to endorse or promote products derived\n# from this software without specific prior written permission.\n# THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n# IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n# WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n#\n#\t@(#)Makefile\t5.3 (Berkeley) 7/9/88\n#\nTOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nDIRS=\tman1 man2 man3 man4 man5 man6 man7 man8 man9\nCDIRS=\tcat1 cat2 cat3 cat4 cat5 cat6 cat7 cat8 cat9\nLCDIRS=\tcat1 cat2 cat3 cat4 cat5 cat6 cat7 cat8 cat9\n\nall:\n\tfor i in ${DIRS}; do \\\n\t\t${MAKE} -C $$i; \\\n\tdone\n\nwhatis.db:\n\tcp /dev/null whatis_tmp\n\tfor dirext in ${DESTDIR}/usr/share/man/cat* ; do \\\n\techo $$dirext; \\\n\tfor file in `find $$dirext -type f -name '*.0' -print`; do \\\n\t\tsed -n -f makewhatis.sed $$file; \\\n\tdone >> whatis_tmp; \\\n\tdone\n\tsort -u whatis_tmp > whatis.db\n\t-rm -f whatis_tmp\n\ninstall: FRC\n\tfor i in ${DIRS}; do \\\n\t\t${MAKE} -C $$i install; \\\n\tdone\n\t${MAKE} whatis.db\n\tcp whatis.db ${DESTDIR}/usr/share/man/whatis\n\tcp man.template ${DESTDIR}/usr/share/man/man.template\n#\tcp makewhatis.sed ${DESTDIR}/usr/share/man/makewhatis.sed\n#\t${INSTALL} -c -m 755 manroff ${DESTDIR}/usr/share/man/manroff\n\nclean: FRC\n\tfor i in ${DIRS}; do \\\n\t\t${MAKE} -C $$i clean; \\\n\tdone\n\trm -f whatis_tmp whatis.db\n\ndepend:\nlint:\ntags:\nFRC:\n"
  },
  {
    "path": "share/man/makewhatis.sed",
    "content": "#!/bin/sh -\n#\n# Copyright (c) 1988 Regents of the University of California.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms are permitted\n# provided that the above copyright notice and this paragraph are\n# duplicated in all such forms and that any documentation,\n# advertising materials, and other materials related to such\n# distribution and use acknowledge that the software was developed\n# by the University of California, Berkeley.  The name of the\n# University may not be used to endorse or promote products derived\n# from this software without specific prior written permission.\n# THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n# IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n# WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n#\n#\t@(#)makewhatis.sed\t5.3 (Berkeley) 7/9/88\n#\n/(\\([a-zA-Z0-9]*\\).* Manual/ {\n\ts;.*(\\([a-zA-Z0-9]*\\).* Manual.*;\\1;\n\th\n\td\n}\n/^N\bNA\bAM\bME\bE/!d\n\n:name\n\ts;.*;;\n\tN\n\ts;\\n;;\n\t# some twits underline the command name\n\ts;_\b;;g\n\t/^[^\t ]/b print\n\tH\n\tb name\n\n:print\n\tx\n\ts;\\n;;g\n\ts;^  *;;\n\t/-/!d\n\ts;\\([a-z][A-Z]\\)-[\t ][\t ]*;\\1;\n\ts;\\([a-zA-Z0-9,]\\)[\t ][\t ]*;\\1 ;g\n\ts;[^a-zA-Z0-9]*\\([a-zA-Z0-9]*\\)[^a-zA-Z0-9]*\\(.*\\) - \\(.*\\);\\2 (\\1) - \\3;\n\tp\n\td\n"
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    "path": "share/man/man.template",
    "content": ".TH NAME SECTION local\n.SH NAME\n.SH SYNOPSIS\n.SH DESCRIPTION\n.SH FILES\n.SH SEE ALSO\n.SH DIAGNOSTICS\n.SH BUGS\n"
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  {
    "path": "share/man/man0/Makefile",
    "content": "#\n# Copyright (c) 1986 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n#\t@(#)Makefile\t6.2 (Berkeley) 5/15/86\n#\nTOCS=\ttoc1 toc2 toc3 toc3f toc4 toc5 toc6 toc7 toc8 \\\n\ttocx1 tocx2 tocx3 tocx3f tocx4 tocx5 tocx6 tocx7 tocx8\nMACROS=\t-msU\nPRINTER=Pdp\nTROFF=\tditroff -${PRINTER}\n\nall: title.urm.${PRINTER} preface.${PRINTER} intro.${PRINTER} \\\n     toc.${PRINTER} ptx.${PRINTER} title.prm.${PRINTER}\n\tlpr -${PRINTER} -n title.urm.${PRINTER}\n\tlpr -${PRINTER} -n preface.${PRINTER}\n\tlpr -${PRINTER} -n intro.${PRINTER}\n\tlpr -${PRINTER} -n toc.${PRINTER}\n\tlpr -${PRINTER} -n ptx.${PRINTER}\n\tlpr -${PRINTER} -n title.prm.${PRINTER}\n\ntitle.urm.${PRINTER}: title.urm\n\t${TROFF} -t title.urm >title.urm.${PRINTER}\n\npreface.${PRINTER}: preface.ms\n\t${TROFF} ${MACROS} -t preface.ms >preface.${PRINTER}\n\nintro.${PRINTER}: intro.ms\n\t${TROFF} ${MACROS} -t intro.ms >intro.${PRINTER}\n\ntoc.${PRINTER}: toc.in ptxx\n\t${TROFF} -t toc.in >toc.${PRINTER}\n\nptx.${PRINTER}: ptx.in ptxx\n\t${TROFF} -t ptx.in >ptx.${PRINTER}\n\ntitle.prm.${PRINTER}: title.prm ptxx\n\t${TROFF} -t title.prm >title.prm.${PRINTER}\n\nptxx:\n\ttocrc all\n\ttocrc t\n\nclean:\n\trm -f title.urm.[PT]* preface.[PT]* intro.[PT]* toc.[PT]* ptx.[PT]* \\\n\ttitle.prm.[PT]* ${TOCS} ptxx *.spell errs Errs make.out\n"
  },
  {
    "path": "share/man/man0/break",
    "content": "\u0007\n;\n:\n.\n,\n"
  },
  {
    "path": "share/man/man0/cshcmd",
    "content": "csh(1) alias: shell macros.\ncsh(1) bg: place job in background.\ncsh(1) break: exit while/foreach loop.\ncsh(1) breaksw: exit from switch.\ncsh(1) case: selector in switch.\ncsh(1) cd: change directory.\ncsh(1) chdir: change directory.\ncsh(1) continue: cycle in loop.\ncsh(1) default: catchall clause in switch.\ncsh(1) echo: echo arguments.\ncsh(1) else: alternative commands.\ncsh(1) end: terminate loop.\ncsh(1) endif: terminate conditional.\ncsh(1) endsw: terminate switch.\ncsh(1) eval: re-evaluate shell data.\ncsh(1) exec: overlay shell with specified command.\ncsh(1) exit: leave shell.\ncsh(1) fg: bring job into foreground.\ncsh(1) foreach: loop over list of names.\ncsh(1) glob: filename expand argument list.\ncsh(1) goto: command transfer.\ncsh(1) hashstat: print command hashing statistics.\ncsh(1) history: print history event list.\ncsh(1) if: conditional statement.\ncsh(1) jobs: print current job list.\ncsh(1) kill: kill jobs and processes.\ncsh(1) limit: alter per-process resource limitations.\ncsh(1) login: login new user.\ncsh(1) logout: end session.\ncsh(1) nice: run low priority process.\ncsh(1) nohup: run command immune to hangups.\ncsh(1) notify: request immediate notification.\ncsh(1) onintr: process interrupts in command scripts.\ncsh(1) popd: pop shell directory stack.\ncsh(1) pushd: push shell directory stack.\ncsh(1) rehash: recompute command hash table.\ncsh(1) repeat: execute command repeatedly.\ncsh(1) set: change value of shell variable.\ncsh(1) setenv: set variable in environment.\ncsh(1) shift: manipulate argument list.\ncsh(1) source: read commands from file.\ncsh(1) stop: halt a job or process.\ncsh(1) suspend: suspend a shell, resuming its superior.\ncsh(1) switch: multi-way command branch.\ncsh(1) time: time command.\ncsh(1) umask: change or display file creation mask.\ncsh(1) unalias: remove aliases.\ncsh(1) unhash: discard command hash table.\ncsh(1) unlimit: remove resource limitiations.\ncsh(1) unsetenv: remove environment variables.\ncsh(1) unset: discard shell variables.\ncsh(1) wait: wait for background processes to complete.\ncsh(1) while: repeat commands conditionally.\ncsh(1) @: arithmetic on shell variables.\n"
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  {
    "path": "share/man/man0/ignore",
    "content": "-\n\\-\n10\n11\n16\n144\n2\n201\n3\n4014\n6\n7\n77\na\nabout\nacross\nafter\nal\nal\nall\nallow\nam\namong\nan\nand\nand/or\nany\nanother\nare\nB\nback\nbe\nbeen\nbetween\nbits\nby\ndialect\ndo\net\nextreme\nfacts\nfeeds\nfitting\nfor\nfrom\ngeneral\nget\nhas\nhead\nin\ninteger\nintegers\ninterval\ninto\nintro\nis\nit\nits\nknowledge\nlarge\nlast\nlater\nlocal\nlong\nlow\nmap\no\nof\noff\non\nor\nother\nout\npackage\npart\nperiodically\npieces\nprejudice\nproblem\nservice\nsimple\nspecial\nsystem\ntac\nthat\nthe\nthem\nthey\nthis\nto\ntoe\nturn\ntwo\nuntil\nway\nwith\nyet\nyou\nyour\n"
  },
  {
    "path": "share/man/man0/intro.ms",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)intro.ms\t6.3 (Berkeley) 5/14/86\n.\\\"\n.de IR\n\\fI\\\\$1\\^\\fR\\\\$2\n..\n.de RI\n\\fR\\\\$1\\fI\\\\$2\\^\\fR\\\\$3\n..\n.TL\nINTRODUCTION TO USER'S REFERENCE MANUAL\n.OH 'Introduction''- % -'\n.EH '- % -''Introduction'\n.af % i\n.pn 6\n.LP\nThe documentation has been reorganized for 4.3BSD in a format similar\nto the one used for the Usenix 4.2BSD manuals.\nIt is divided into three sets; each set consists of one or more volumes.\nThe abbreviations for the volume names are listed in square brackets;\nthe abbreviations for the manual sections are listed in parenthesis.\n.DS\nI. User's Documents\n\tUser's Reference Manual [URM]\n\t\tCommands (1)\n\t\tGames (6)\n\t\tMacro packages and language conventions (7)\n\tUser's Supplementary Documents [USD]\n\t\tGetting Started\n\t\tBasic Utilities\n\t\tCommunicating with the World\n\t\tText Editing\n\t\tDocument Preparation\n\t\tAmusements\n\nII. Programmer's Documents\n\tProgrammer's Reference Manual [PRM]\n\t\tSystem calls (2)\n\t\tSubroutines (3)\n\t\tSpecial files (4)\n\t\tFile formats and conventions (5)\n\tProgrammer's Supplementary Documents, Volume 1 [PS1]\n\t\tLanguages in common use\n\t\tGeneral Reference\n\t\tProgramming Tools\n\t\tProgramming Libraries\n\tProgrammer's Supplementary Documents, Volume 2 [PS2]\n\t\tDocuments of Historic Interest\n\t\tOther Languages\n\t\tDatabase Management\n\nIII. System Manager's Manual [SMM]\n\tMaintenance commands (8)\n\tSystem Installation and Administration\n\tSupporting Documentation\n.DE\n.LP\nReferences to individual documents are given as ``volume:document'',\nthus USD:1 refers to the first document in the ``User's Supplementary\nDocuments''.\nReferences to manual pages are given as ``\\fIname\\fP(section)'' thus\n.IR sh (1)\nrefers to the shell manual entry in section 1.\n.LP\nThe manual pages give descriptions of the publicly available features of the\n.UX \\s-2/32V\\s0\nsystem, as extended to provide a virtual memory environment\nand other enhancements at the University of California.\nThey do not attempt to provide perspective or tutorial information about the\n.UX\noperating system, its facilities, or its implementation.\nVarious documents on those topics are contained in the\n``UNIX User's Supplementary Documents'' (USD), the\n``UNIX Programmer's Supplementary Documents'' (PS1 and PS2),\nand ``UNIX System Manager's Manual'' (SMM).\nIn particular, for an overview see ``The UNIX Time-Sharing System'' (PS2:1)\nby Ritchie and Thompson; for a tutorial see\n``\\s8UNIX\\s10 for Beginners'' (USD:1) by Kernighan,\nand for an guide to the new features of this virtual version, see\n``Berkeley Software Architecture Manual (4.3 Edition)'' (PS1:6).\n.LP\nWithin the area it surveys, this volume attempts to be timely, complete\nand concise.  Where the latter two objectives conflict,\nthe obvious is often left unsaid in favor of brevity.\nIt is intended that each program be described as it is, not as it should be.\nInevitably, this means that various sections will soon be out of date.\n.LP\nCommands are programs intended to be invoked directly by\nthe user, in contrast to subroutines, that are\nintended to be called by the user's programs.\nUser commands are described in URM section 1.\nCommands generally reside in directory\n.I /bin\n(for\n.IR bin \\|ary\nprograms).\nSome programs also reside in\n.I\n/\\|usr/\\|bin,\n.R\n.I\n/\\|usr/\\|ucb,\n.R\nor\n.I\n/\\|usr/\\|new,\n.R\nto save space in\n.I  /\\|bin.\nThese directories are searched automatically by the command interpreters.\n.LP\nGames have been relegated to URM section 6 and\n.I\n/\\|usr/\\|games,\n.R\nto keep them from contaminating\nthe more staid information of URM section 1.\n.LP\nMiscellaneous collection of information necessary for\nwriting in various specialized languages such as character codes, \nmacro packages for typesetting, etc is contained in URM section 7.\n.LP\nSystem calls are entries into the\n.UX\nsupervisor.  The system call interface is identical to a C language\nprocedure call; the equivalent C procedures are described in PRM section 2.\n.LP\nAn assortment of subroutines is available;\nthey are described in PRM section 3.\nThe primary libraries in which they are kept are described in\n.IR intro (3).\nThe functions are described in terms of C;\nthose that will work with Fortran are described in\n.IR intro (3f).\n.LP\nPRM section 4 discusses the characteristics of\neach system ``file'' that refers to an I/O device.\nThe names in this section refer to the DEC device names for the hardware,\ninstead of the names of the special files themselves.\n.LP\nThe file formats and conventions (PRM section 5)\ndocuments the structure of particular kinds of files;\nfor example, the form of the output of the loader and\nassembler is given.  Excluded are files used by only one command,\nfor example the assembler's intermediate files.\n.LP\nCommands and procedures intended for use primarily by the\nsystem administrator are described in SMM section 8.\nThe commands and files described here are almost all kept in the directory\n.I /\\|etc.\n.LP\nEach section consists of independent entries of a page or so each.\nThe name of the entry is in the upper corners of its pages,\ntogether with the section number, and sometimes a\nletter characteristic of a subcategory, e.g. graphics is 1G,\nand the math library is 3M.\nEntries within each section are alphabetized.\nexcept for PRM section 3f which appears after the rest of PRM section 3.\nThe page numbers of each entry start at 1;\nit is infeasible to number consecutively the pages of \na document like this that is republished in many variant forms.\n.LP\nAll entries are based on a common format;\nnot all subsections always appear.\n.RS\n.LP\nThe\n.I name\nsubsection lists the exact names of the commands and subroutines\ncovered under the entry and gives a short description of their purpose.\n.LP\nThe\n.IR synopsis \"\"\nsummarizes the use of the program being described.\nA few conventions are used, particularly in the Commands subsection:\n.LP\n.RS\n.B Boldface\nwords are considered literals, and are typed just as they appear.\n.LP\nSquare brackets [ ] around an argument show that the argument is optional.\nWhen an argument is given as ``name'', it always refers to a file name.\n.LP\nEllipses ``.\\|.\\|.'' are used to show that the previous argument-prototype\nmay be repeated.\n.LP\nA final convention is used by the commands themselves.\nAn argument beginning with a minus sign ``\\-'' usually means that it is an\noption-specifying argument, even if it appears in a position where\na file name could appear.  Therefore, it is unwise to have files whose\nnames begin with ``\\-''.\n.LP\n.RE\nThe\n.IR description \"\"\nsubsection discusses in detail the subject at hand.\n.LP\nThe\n.IR files \"\"\nsubsection gives the names of files that are built into the program.\n.LP\nA\n.I\nsee also\n.R\nsubsection gives pointers to related information.\n.LP\nA\n.I  diagnostics\nsubsection discusses the diagnostic indications that may be produced.\nMessages that are intended to be self-explanatory are not listed.\n.LP\nThe\n.IR bugs \"\"\nsubsection gives known bugs and sometimes deficiencies.\nOccasionally the suggested fix is also described.\n.LP\n.RE\nAt the beginning of URM is a table of contents,\norganized by section and alphabetically within each section.\nThere is also a permuted index derived from the table of contents.\nWithin each index entry, the title of the writeup to which\nit refers is followed by the appropriate section number in parentheses.\nThis fact is important because there is considerable\nname duplication among the sections, arising principally from commands that\nexist only to exercise a particular system call.\n.SH\nHOW TO GET STARTED\n.LP\nThis section sketches the basic information you need to get started on UNIX;\nhow to log in and log out, how to communicate through your terminal,\nand how to run a program.\nSee ``\\c\n.UX\nfor Beginners'' in (USD:1) for a more complete introduction to the system.\n.LP\n.I\nLogging in.\\ \\ \n.R\nAlmost any ASCII terminal capable of\nfull duplex operation and generating\nthe entire character set can be used.\nYou must have a valid user name,\nwhich may be obtained from the system administration.\nIf you will be accessing UNIX remotely, you will also\nneed to obtain the telephone number for the system that you will be using.\n.LP\nAfter a data connection is established,\nthe login procedure depends on what type of terminal you are using\nand local system conventions.\nIf your terminal is directly connected to the computer,\nit generally runs at 9600 or 19200 baud.\nIf you are using a modem running over a phone line,\nthe terminal must be set at the speed appropriate for the modem you are using,\ntypically 300, 1200, or 2400 baud.\nThe half/full duplex switch should always be set at full-duplex.\n(This switch will often have to be changed\nsince many other systems require half-duplex).\n.LP\nWhen a connection is established, the system types ``login:'';\nyou type your user name, followed by the ``return'' key.\nIf you have a password, the system asks for it\nand suppresses echo to the terminal so the password will not appear.\nAfter you have logged in, the ``return'', ``new line'', or ``linefeed'' keys\nwill give exactly the same results.\nA message-of-the-day usually greets you before your first prompt.\n.LP\nIf the system types out a few garbage characters\nafter you have established a data connection\n(the ``login:'' message at the wrong speed),\ndepress the ``break'' (or ``interrupt'') key.\nThis is a speed-independent signal to\n.UX\nthat a different speed terminal is in use.\nThe system then will type ``login:,'' this time at another speed.\nContinue depressing the break key until ``login:'' appears clearly,\nthen respond with your user name.\n.LP\nFor all these terminals, it is important\nthat you type your name in lower-case if possible; if you type\nupper-case letters,\n.UX\nwill assume that your terminal cannot generate lower-case\nletters and will translate all subsequent lower-case letters to upper case.\n.LP\nThe evidence that you have successfully logged in is that a shell program\nwill type a prompt (``$'' or ``%'') to you.\n(The shells are described below under ``How to run a program.'')\n.LP\nFor more information, consult\n.IR tset (1),\nand\n.IR stty (1),\nwhich tell how to adjust terminal behavior;\n.IR getty (8)\ndiscusses the login sequence in more detail, and\n.IR tty (4)\ndiscusses terminal I/O.\n.LP\n.I\nLogging out.\\ \\ \n.R\nThere are three ways to log out:\n.IP\nBy typing ``logout'' or an end-of-file\nindication (EOT character, control-D) to the shell.\nThe shell will terminate and the ``login:'' message will appear again.\n.IP\nYou can log in directly as another user by giving a\n.IR login (1)\ncommand.\n.IP\nIf worse comes to worse,\nyou can simply hang up the phone; but beware \\- some machines may\nlack the necessary hardware to detect that the phone has been hung up.\nAsk your system administrator if this is a problem on your machine.\n.LP\n.I\nHow to communicate through your terminal.\\ \\ \n.R\nWhen you type characters, a gnome deep in the system\ngathers your characters and saves them in a secret place.\nThe characters will not be given to a program\nuntil you type a return (or newline), as described above in\n.I\nLogging in.\n.R\n.LP\n.UX\nterminal I/O is full-duplex.\nIt has full read-ahead, which means that you can type at any time,\neven while a program is typing at you.\nOf course, if you type during output, the printed output will\nhave the input characters interspersed.\nHowever, whatever you type will be saved up and interpreted in correct sequence.\nThere is a limit to the amount of read-ahead,\nbut it is generous and not likely to be exceeded unless\nthe system is in trouble.\nWhen the read-ahead limit is exceeded, the system\nthrows away all the saved characters (or beeps, if your prompt was a ``%'').\n.LP\nThe delete (DEL) character in typed input kills all the\npreceding characters in the line,\nso typing mistakes can be repaired on a single line.\nAlso, the backspace character (control-H) erases the last character typed.\n.IR Tset (1)\nor\n.IR stty (1)\ncan be used to change these defaults.\nSuccessive uses of backspace erases characters back to, but\nnot beyond, the beginning of the line.\nDEL and backspace can be transmitted to a program by preceding them with ``\\e''.\n(So, to erase ``\\e'', you need two backspaces).\n.LP\nAn\n.I\ninterrupt signal\n.R\nis sent to a program by typing control-C or the ``break'' key\nwhich is not passed to programs.\nThis signal generally causes whatever program you are running to terminate.\nIt is typically used to stop a long printout that you do not want.\nHowever, programs can arrange either to ignore this signal altogether,\nor to be notified when it happens (instead of being terminated).\nThe editor, for example, catches interrupts and stops what it is doing,\ninstead of terminating, so that an interrupt can\nbe used to halt an editor printout without losing the file being edited.\nThe interrupt character can also be changed with\n.IR tset (1)\nor\n.IR stty (1).\n.LP\nIt is also possible to suspend output temporarily using ^S (control-S)\nand later resume output with ^Q (control-Q).\nOutput can be thrown away without interrupting\nthe program by typing ^O (control-O); see\n.IR tty (4).\n.LP\nThe\n.IR quit \"\"\nsignal is generated by typing the \\s8ASCII\\s10 FS character.\n(FS appears many places on different terminals, most commonly\nas control-\\e or control-\\^|\\^.)\nIt not only causes a running program to terminate\nbut also generates a file with the core image of the terminated process.\nQuit is useful for debugging.\n.LP\nBesides adapting to the speed of the terminal,\n.UX\ntries to be intelligent about whether\nyou have a terminal with the newline function\nor whether it must be simulated with carriage-return and line-feed.\nIn the latter case, all input carriage returns\nare turned to newline characters (the standard line delimiter)\nand both a carriage return and a line feed are echoed to the terminal.\nIf you get into the wrong mode, the\n.IR reset (1)\ncommand will rescue you.\nIf the terminal does not appear to be echoing anything that you type,\nit may be stuck in ``no-echo'' or ``raw'' mode.\nTry typing ``(control-J)reset(control-J)'' to recover.\n.LP\nTab characters are used freely in\n.UX\nsource programs.\nIf your terminal does not have the tab function,\nyou can arrange to have them turned into spaces\nduring output, and echoed as spaces during input.\nThe system assumes that tabs are set every eight columns.\nAgain, the\n.IR tset (1)\nor\n.IR stty (1)\ncommand can be used to change these defaults.\n.IR Tset (1)\ncan be used to set the tab stops automatically when necessary.\n.LP\n.I\nHow to run a program; the shells.\\ \\ \n.R\nWhen you have successfully logged in, a program\ncalled a shell is listening to your terminal.\nThe shell reads typed-in lines, splits them up\ninto a command name and arguments, and executes the command.\nA command is simply an executable program.\nThe shell looks in several system directories to find the command.  You can also\nplace commands in your own directory and have the shell find them there.\nThere is nothing special about system-provided\ncommands except that they are kept in a directory where the shell can find them.\n.LP\nThe command name is always the first word on an input line;\nit and its arguments are separated from one another by spaces.\n.LP\nWhen a program terminates, the shell will ordinarily regain control and type \na prompt at you to show that it is ready for another command.\n.LP\nThe shells have many other capabilities, that are described in detail in\nsections\n.IR sh (1)\nand\n.IR csh (1).\nIf the shell prompts you with ``$'', then it is an instance of\n.IR sh (1)\nthe standard shell provided by Bell Labs.\nIf it prompts with ``%'' then it is an instance of\n.IR csh (1),\na shell written at Berkeley.\nThe shells are different for all but the most simple terminal usage.\nMost users at Berkeley choose\n.IR csh (1)\nbecause of the\n.I history\nmechanism and the\n.I alias\nfeature, that greatly enhance its power when used interactively.\n.I Csh\nalso supports the job-control facilities;\nsee\n.IR csh (1)\nor the Csh introduction in USD:4 for details.\n.LP\nYou can change from one shell to the other by using the\n.I chsh (1)\ncommand, which takes effect at your next login.\n.LP\n.I\nThe current directory.\\ \\ \n.R\n.UX\nhas a file system arranged as a hierarchy of directories.\nWhen the system administrator gave you a user name,\nthey also created a directory for you (ordinarily\nwith the same name as your user name).\nWhen you log in, any file name you type is by default in this directory.\nSince you are the owner of this directory, you have\nfull permission to read, write, alter, or destroy its contents.\nPermissions to have your will with other directories\nand files will have been granted or denied to you by their owners.\nAs a matter of observed fact, few\n.UX\nusers protect their files from perusal by other users.\n.LP\nTo change the current directory (but not the set of permissions you\nwere endowed with at login) use\n.IR cd (1).\n.LP\n.I\nPath names.\\ \\ \n.R\nTo refer to files not in the current directory, you must use a path name.\nFull path names begin with ``/\\|'', the name of the root directory of the\nwhole file system.\nAfter the slash comes the name of each directory containing the next\nsub-directory (followed by a ``/\\|'') until finally the file name is reached.\nFor example,\n.I\n/\\^usr/\\^tmp/\\^filex\n.R\nrefers to the file\n.I\nfilex\n.R\nin the directory\n.I\ntmp; tmp\n.R\nis itself a subdirectory of\n.I\nusr; usr\n.R\nsprings directly from the root directory.\n.LP\nIf your current directory has subdirectories,\nthe path names of files therein begin with\nthe name of the subdirectory with no prefixed ``/\\|''.\n.LP\nA path name may be used anywhere a file name is required.\n.LP\nImportant commands that modify the contents of files are\n.IR cp (1),\n.IR mv (1),\nand\n.IR rm (1),\nwhich respectively copy, move (i.e. rename) and remove files.\nTo find out the status of files or directories, use \n.IR ls (1).\nSee\n.IR mkdir (1)\nfor making directories and\n.IR rmdir (1)\nfor destroying them.\n.LP\nFor a fuller discussion of the file system, see\n``A Fast File System for UNIX'' (SMM:14)\nby McKusick, Joy, Leffler, and Fabry.\nIt may also be useful to glance through PRM section 2,\nthat discusses system calls, even if you do not intend\nto deal with the system at that level.\n.LP\n.I\nWriting a program.\\ \\ \n.R\nTo enter the text of a source program into a\n.UX\nfile, use the editor\n.IR ex (1)\nor its display editing alias\n.IR vi (1).\n(The old standard editor\n.IR ed (1)\nis also available.)\nThe principal languages in\n.UX\nare provided by the C compiler\n.IR cc (1),\nthe Fortran compiler\n.IR f77 (1),\nand its derivatives \n.IR efl (1)\nand\n.IR ratfor (1),\nthe Pascal compiler\n.IR pc (1),\nand interpreter\n.IR pi (1),\nand the Lisp system\n.IR lisp (1).\nUser contributed software in the latest\nrelease of the system supports\nAPL, B, the Functional Programming language, and Icon.\nRefer to\n.IR apl (1),\n.IR b (1),\n.IR fp (1),\nand\n.IR icon (1),\nrespectively for more information about each.\nAfter the program text has been entered through the editor\nand written to a file, you can give the file\nto the appropriate language processor as an argument.\nThe output of the language processor\nwill be left on a file in the current directory named ``a.out''.\nIf the output is precious, use\n.IR mv (1)\nto move it to a less exposed name after successful compilation.\n.LP\nWhen you have finally gone through this entire process\nwithout provoking any diagnostics, the resulting program\ncan be run by giving its name to the shell\nin response to the shell (``$'' or ``%'') prompt.\n.LP\nYour programs can receive arguments from the command line\njust as system programs do,\nsee ``UNIX Programming - Second Edition'' (PS2:3),\nor for a more terse description\n.IR execve (2).\n.LP\n.I\nText processing.\\ \\ \n.R\nAlmost all text is entered through the editor\n.IR ex (1)\n(often entered via\n.IR vi (1)).\nThe commands most often used to write text on a terminal are:\n.IR cat (1),\n.IR more (1),\nand\n.IR nroff (1).\n.LP\nThe\n.IR cat (1)\ncommand simply dumps \\s8ASCII\\s10 text\non the terminal, with no processing at all.\n.IR More (1)\nis useful for preventing the output of a command from\nscrolling off the top of your screen.\nIt is also well suited to perusing files.\n.IR Nroff (1)\nis an elaborate text formatting program.\nUsed naked, it requires careful forethought, but for\nordinary documents it has been tamed; see\n.IR me (7)\nand\n.IR ms (7).\n.LP\n.IR Troff (1)\nprepares documents for a Graphics Systems phototypesetter\nor a Versatec Plotter;\nit is similar to \n.IR nroff (1),\nand often works from exactly the same source text.\nIt was used to produce this manual.\n.LP\n.IR Script (1)\nlets you keep a record of your session in a file,\nwhich can then be printed, mailed, etc.\nIt provides the advantages of a hard-copy terminal\neven when using a display terminal.\n.LP\n.I\nStatus inquiries.\\ \\ \n.R\nVarious commands exist to provide you with useful information.\n.IR w (1)\nprints a list of users currently logged in, and what they are doing.\n.IR date (1)\nprints the current time and date.\n.IR ls (1)\nwill list the files in your directory or give\nsummary information about particular files.\n.LP\n.I\nSurprises.\\ \\ \n.R\nCertain commands provide inter-user communication.\nEven if you do not plan to use them, it would be\nwell to learn something about them, because someone else may aim them at you.\n.LP\nTo communicate with another user currently logged in,\n.IR write (1)\nor\n.IR talk (1)\nis used;\n.IR mail (1)\nwill leave a message whose presence will be announced\nto another user when they next log in.\nThe write-ups in the manual also suggest how to respond to\nthe these commands if you are a target.\n.LP\nIf you use\n.IR csh (1)\nthe key ^Z (control-Z) will cause jobs to ``stop''.\nIf this happens before you learn about it,\nyou can simply continue by saying ``fg'' (for foreground) to bring\nthe job back.\n.SH\nCONVERTING FROM 4.2BSD SYSTEMS\n.LP\nA detailed list of changes from the 4.2BSD to the 4.3BSD distributions\nis contained in ``Bug Fixes and Changes in 4.3BSD'' (SMM:12),\nand ``Changes to the Kernel in 4.3BSD'' (SMM:13).\nDetailed conversion procedures are described in\n``Installing and Operating 4.3BSD on the VAX'' (SMM:1);\nit also discusses changes from pre-4.2BSD systems.\n"
  },
  {
    "path": "share/man/man0/preface.ms",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)preface.ms\t6.3 (Berkeley) 5/13/86\n.\\\"\n.nr PS 9\n.nr VS 11\n.vs 11p\n.ps 9p\n.TL\nPREFACE\n.OH 'Preface''- % -'\n.EH '- % -''Preface'\n.af % i\n.LP\nThis update to the 4.2 distribution of August 1983 provides\nsubstantially improved performance, reliability, and security,\nthe addition of Xerox Network System (NS) to the set of networking domains,\nand partial support for the VAX 8600 and MICROVAXII.\n.LP\nWe were greatly assisted by the DEC UNIX Engineering group who\nprovided two full time employees, Miriam Amos and Kevin Dunlap,\nto work at Berkeley. They were responsible for developing and\ndebugging the distributed domain based name server\nand integrating it into the mail system.\nMt Xinu provided the bug list distribution service as well as\ndonating their MICROVAXII port to 4.3BSD.\nDrivers for the MICROVAXII were done by Rick Macklem\nat the University of Guelph.\nSam Leffler provided valuable assistance and advice with many projects.\nKeith Sklower coordinated with William Nesheim and J. Q. Johnson at Cornell, \nand Chris Torek and James O'Toole at the University of Maryland\nto do the Xerox Network Systems implementation.\nRobert Elz at the University of Melbourne contributed greatly\nto the performance work in the kernel.\nDonn Seeley and Jay Lepreau at the University of Utah\nrelentlessly dealt with a miriad of details;\nDonn completed the unfinished performance work on Fortran 77\nand fixed numerous C compiler bugs.\nRalph Campbell handled innumerable questions and problem reports\nand had time left to write rdist.\nGeorge Goble was invaluable in shaking out the bugs on his\nproduction systems long before we were confident enough to\ninflict it on our users.\nBill Shannon at Sun Microsystems has been helpful in \nproviding us with bug fixes and improvements.\nTom Ferrin, in his capacity as Board Member of Usenix Association,\nhandled the logistics of large-scale reproduction\nof the 4.2BSD and 4.3BSD manuals.\nMark Seiden helped with the typesetting and indexing of the 4.3BSD manuals.\nSpecial mention goes to Bob Henry for keeping ucbvax running\nin spite of new and improved software and\nan ever increasing mail, news, and uucp load.\n.LP\nNumerous others contributed their time and energy in creating\nthe user contributed software for the release.\nAs always, we are grateful to the UNIX user community for \nencouragement and support. \n.LP\nOnce again, the financial support of the Defense Advanced Research\nProjects Agency is gratefully acknowledged.\n.sp 1\n.in 4i\n.nf\nM. K. McKusick\nM. J. Karels\nJ. M. Bloom\n.fi\n.in 0\n.sp 2\n.ne 1i\n.ce\n\\fIPreface to the 4.2 Berkeley distribution\\fP\n.sp 1\nThis update to the 4.1 distribution of June 1981 provides support\nfor the VAX 11/730, full networking and interprocess communication\nsupport, an entirely new file system, and many other new features.\nIt is certainly the most ambitious release of software ever prepared\nhere and represents many man-years of work.\nBill Shannon (both at DEC and at Sun Microsystems)\nand Robert Elz of the University\nof Melbourne contributed greatly to this distribution\nthrough new device drivers and painful debugging episodes.\nRob Gurwitz of BBN wrote the initial version of the code upon\nwhich the current networking support is based.\nEric Allman of Britton-Lee donated countless hours to the mail system.\nBill Croft (both at SRI and Sun Microsystems) aided in the\ndebugging and development of the networking facilities.\nDennis Ritchie of Bell Laboratories also\ncontributed greatly to this distribution, providing\nvaluable advise and guidance.  Helge Skrivervik\nworked on the device drivers which enabled\nthe distribution to be delivered with a TU58\nconsole cassette and RX01 console flopppy disk, and\nrewrote major portions of the standalone i/o system\nto support formatting of non-DEC peripherals.\n.LP\nNumerous others contributed their time and energy in organizing\nthe user software for release, while many groups of people on\ncampus suffered patiently through the low spots of development.\nAs always, we are grateful to the UNIX user community for \nencouragement and support. \n.LP\nOnce again, the financial support of the Defense Advanced Research\nProjects Agency is gratefully acknowledged.\n.sp 1\n.in 4i\n.nf\nS. J. Leffler\nW. N. Joy\nM. K. McKusick\n.fi\n.in 0\n.sp 2\n.ne 1i\n.ce\n\\fIPreface to the 4.1 Berkeley distribution\\fP\n.sp 1\nThis update to the fourth distribution of November 1980 provides\nsupport for the VAX 11/750 and for the full interconnect architecture\nof the VAX 11/780.  Robert Elz of the University of Melbourne contributed\ngreatly to this distribution especially in the boot-time system\nconfiguration code;  Bill Shannon of DEC supplied us with the\nimplementation of DEC standard bad block handling.  The research\ngroup at Bell Laboratories and DEC Merrimack provided us with access\nto 11/750's in order to debug its support.\n.LP\nOther individuals too numerous to mention provided us with bug reports,\nfixes and other enhancements which are reflected in the system.  We\nare grateful to the UNIX user community for encouragement and\nsupport.\n.LP\nThe financial support of the Defence Advanced Research Projects Agency\nin support of this work is gratefully acknowledged.\n.sp 1\n.in 4i\n.nf\nW. N. Joy\nR. S. Fabry\nK. Sklower\n.fi\n.in 0\n.sp 2\n.ne 1i\n.ce\n\\fIPreface to the Fourth Berkeley distribution\\fP\n.sp 1\nThis manual reflects the Berkeley system mid-October, 1980.\nA large amount of tuning has been done in the system since the last release;\nwe hope this provides as noticeable an improvement for you as it did for us.\nThis release finds the system in transition; a number of facilities\nhave been added in experimental versions (job control, resource limits)\nand the implementation of others is imminent (shared-segments, higher\nperformance from the file system, etc.).\nApplications which use facilities that are in transition should be aware\nthat some of the system calls and library routines will change\nin the near future.  We have tried to be conscientious and make it\nvery clear where this is likely.\n.LP\nA new group has been formed\nat Berkeley, to assume responsibility for the future\ndevelopment and support of a version of UNIX on the VAX.\nThe group has received funding from the\nDefense Advanced Research Projects Agency (DARPA)\nto supply a standard version of the system to DARPA contractors.\nThe same version of the system will be made available to other licensees\nof UNIX on the VAX for a duplication charge.\nWe gratefully acknowledge\nthe support of this contract.\n.LP\nWe wish to acknowledge the contribution of a number of individuals to\nthe the system.\n.LP\nWe would especially like to thank\nJim Kulp of IIASA,\nLaxenburg Austria and his colleagues,\nwho first put job control facilities into UNIX;\nEric Allman, Robert Henry, Peter Kessler and Kirk McKusick, who\ncontributed major new pieces of software;\nMark Horton, who contributed to the improvement of facilities and\nsubstantially improved the quality of our bit-mapped fonts,\nour hardware support staff:\nBob Kridle,\nAnita Hirsch,\nLen Edmondson\nand\nFred Archibald,\nwho helped us to debug a number of new peripherals;\nKen Arnold who did much of the leg-work in getting this version of the\nmanual prepared, and did the final editing of sections 2-6,\nsome special individuals within Bell Laboratories:\nGreg Chesson,\nStuart Feldman,\nDick Haight,\nHoward Katseff,\nBrian Kernighan,\nTom London,\nJohn Reiser,\nDennis Ritchie,\nKen Thompson,\nand\nPeter Weinberger\nwho helped out by answering questions;\nour excellent local DEC field service people,\nKevin Althaus and Frank Chargois\nwho kept our machine running virtually all the time, and fixed it quickly\nwhen things broke;\nand,\nMike Accetta of Carnegie-Mellon University,\nRobert Elz of the University of Melbourne,\nGeorge Goble of Purdue University,\nand\nDavid Kashtan of the Stanford Research Institute\nfor their technical advice and support.\n.LP\nSpecial thanks to Bill Munson of DEC who helped by augmenting\nour computing facility\nand to Eric Allman for carefully proofreading the\n``last'' draft of the manual and finding the bugs which we knew were\nthere but couldn't see. \n.LP\nWe dedicate this to the memory of David Sakrison, late chairman of our\ndepartment, who gave his support to the establishment of our VAX\ncomputing facility, and to our department as a whole.\n.sp 1\n.in 4i\n.nf\nW. N. Joy\n\\v'-3p'\\h'2p'\\*:\\v'3p'\\h'-2p'O. Babao\\*~glu\nR. S. Fabry\nK. Sklower\n.fi\n.in 0\n.sp 2\n.ne 1i\n.ce\n\\fIPreface to the Third Berkeley distribution\\fP\n.sp 1\nThis manual reflects the state of the Berkeley system, December 1979.\nWe would like to thank all the people at Berkeley who have contributed to\nthe system, and particularly thank\nProf. Richard Fateman for creating and administrating a hospitable environment,\nMark Horton who helped prepare this manual, and\nEric Allman, Bob Kridle, Juan Porcar\nand Richard Tuck for their contributions to the kernel.\n.LP\nThe cooperation of Bell Laboratories in providing us with an early version of\n\\s-2UNIX\\s0/32V is greatly appreciated.  We would especially like to thank\nDr. Charles Roberts of Bell Laboratories for helping us obtain this release,\nand acknowledge\nT. B. London,\nJ. F. Reiser,\nK. Thompson,\nD. M. Ritchie,\nG. Chesson and\nH. P. Katseff\nfor their advice and support.\n.sp 1\n.in 4i\nW. N. Joy\n.br\n\\v'-3p'\\h'2p'\\*:\\v'3p'\\h'-2p'O. Babao\\*~glu\n.in 0\n.sp 2\n.ne 1i\n.ce\n\\fIPreface to the UNIX/32V distribution\\fP\n.sp 1\nThe\n.UX\noperating system for the VAX*-11\n.FS\n*VAX and PDP are Trademarks of Digital Equipment Corporation.\n.FE\nprovides substantially the same facilities as the\n\\s-2UNIX\\s0\nsystem for the PDP*-11.\n.LP\nWe acknowledge the work of many who came before us, and particularly thank\nG. K. Swanson, W. M. Cardoza, D. K. Sharma, and J. F. Jarvis for assistance\nwith the implementation for the VAX-11/780.\n.sp 1\n.in 4i\nT. B. London\n.br\nJ. F. Reiser\n.in 0\n.sp 2\n.ne 1i\n.ce\n\\fIPreface to the Seventh Edition\\fP\n.sp 1\n.LP\nAlthough this Seventh Edition no longer bears their byline,\nKen Thompson and Dennis Ritchie remain the fathers\nand preceptors of the\n\\s-2UNIX\\s0\ntime-sharing system.\nMany of the improvements here described bear their mark.\nAmong many, many other people who have contributed to\nthe further flowering of\n\\s-2UNIX\\s0,\nwe wish especially to\nacknowledge the contributions of\nA. V. Aho,\nS. R. Bourne,\nL. L. Cherry,\nG. L. Chesson,\nS. I. Feldman,\nC. B. Haley,\nR. C. Haight,\nS. C. Johnson,\nM. E. Lesk,\nT. L. Lyon,\nL. E. McMahon,\nR. Morris,\nR. Muha,\nD. A. Nowitz,\nL. Wehr,\nand\nP. J. Weinberger.\nWe appreciate also \nthe effective advice and criticism of\nT. A. Dolotta,\nA. G. Fraser,\nJ. F. Maranzano,\nand\nJ. R. Mashey;\nand we remember the important work of\nthe late Joseph F. Ossanna.\n.sp 1\n.in 4i\nB. W. Kernighan\n.br\nM. D. McIlroy\n.in 0\n"
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  {
    "path": "share/man/man0/ptx.in",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ptx.in\t6.2 (Berkeley) 5/12/86\n.\\\"\n.af % i\n.if t .pn 25\\\"PERMUTED INDEX\n.if n .pn 29\n.tr ~\n.ll 6.5i\n.lt 6.7i\n.po .75i\n.ds ET\\\"\n.de HD\n.po 0\n.lt 7.4i\n.tl ''''\n.lt\n.po\n'sp 18p\n.if o .tl '\\\\*(ET''- % -'\n.if e .tl '- % -''\\\\*(ET'\n'sp 18p\n.ns\n..\n.de FO\n'sp 18p\n.if e .tl '\\s9\\\\*(Dt''\\\\*(Ed\\s0'\n.if o .tl '\\s9\\\\*(Ed''\\\\*(Dt\\s0'\n'bp\n..\n.wh 0 HD\n.wh -60p FO\n.if \\n(nl .bp\n.br\n.ds ET \\s9\\f2Permuted \\|Index\\fP\\s0\n.ds Ed 4.3BSD\n.ds Dt April \\|1986\n.ce\n\\f3PERMUTED \\|INDEX\\fP\n.sp 1v\n.ps 8\n.vs 9p\n.nf\n.cs 3 36\n.\\\"\tbackup from slotput 1, slot, 2\n.de xx\n.ds s1\\\"\n.if \\w\u0002\\\\$2\u0002 .ds s1 ~~\\\"\n.ds s2 ~~~\\\"\n.ds s3\\\"\n.if \\w\u0002\\\\$4\u0002 .ds s3 ~~\\\"\n.ds s4 ~~\\\"\n.ds s5 ~~\\\"\n.ds y \\\\*(s4\\f3\u0001\\fP\\\\*(s5\n.ta 6i-\\w\u0002\\\\*(s5\u0002u\n\\h\"3i-\\w\u0002\\\\$1\\\\*(s1\\\\$2\\\\*(s2\u0002u\"\\\\$1\\\\*(s1\\\\$2\\\\*(s2\\\\$3\\\\*(s3\\\\$4\\\\*y\\\\$5\n..\n.so ptxx\n.cs 3\n.if n .ta 8n 16n 24n 32n 40n 48n 56n 64n 72n 80n\n.if t .ta .5i 1i 1.5i 2i 2.5i 3i 3.5i 4i 4.5i 5i 5.5i 6i 6.5i\n"
  },
  {
    "path": "share/man/man0/ptxx",
    "content": ".xx \"\" \"\" \"@: arithmetic on shell variables.\" \"\" csh(1)\n.xx \"\" \"imp:\" \"1822 network interface.\" \"\" imp(4)\n.xx \"\" \"ddn: DDN Standard Mode X.\" \"25 IMP interface.\" \"\" ddn(4)\n.xx \"\" \"lib2648: subroutines for the HP\" \"2648 graphics terminal.\" \"\" lib2648(3X)\n.xx \"\" \"mset: retrieve ASCII to IBM\" \"3270 keyboard map.\" \"\" mset(1)\n.xx \"\" \"database for mapping ascii keystrokes into IBM\" \"3270 keys.\" \"map3270:\" map3270(5)\n.xx \"\" \"ec:\" \"3Com 10 Mb/s Ethernet interface.\" \"\" ec(4)\n.xx \"\" \"diff3:\" \"3-way differential file comparison.\" \"\" diff3(1)\n.xx \"\" \"openpl et al.: f77 library interface to \\fIplot\\fR\" \"(3X) libraries..\" \"plot:\" plot(3F)\n.xx \"\" \"sendbug: mail a system bug report to\" \"4bsd-bugs.\" \"\" sendbug(1)\n.xx \"\" \"crl: VAX\" \"8600 console RL02 interface.\" \"\" crl(4)\n.xx \"\" \"\" \"aardvark: yet another exploration game.\" \"\" aardvark(6)\n.xx \"\" \"abort:\" \"abnormal termination.\" \"\" abort(3F)\n.xx \"\" \"\" \"abort: abnormal termination.\" \"\" abort(3F)\n.xx \"\" \"\" \"abort: generate a fault.\" \"\" abort(3)\n.xx \"\" \"\" \"abs: integer absolute value.\" \"\" abs(3)\n.xx \"\" \"abs: integer\" \"absolute value.\" \"\" abs(3)\n.xx \"\" \"hypot, cabs: Euclidean distance, complex\" \"absolute value.\" \"\" hypot(3M)\n.xx \"round-to-nearest/\" \"fabs, floor, ceil, rint:\" \"absolute value, floor, ceiling, and\" \"\" floor(3M)\n.xx \"\" \"\" \"ac: login accounting.\" \"\" ac(8)\n.xx \"\" \"\" \"acc: ACC LH/DH IMP interface.\" \"\" acc(4)\n.xx \"\" \"hdh:\" \"ACC IF-11/HDH IMP interface.\" \"\" hdh(4)\n.xx \"\" \"acc:\" \"ACC LH/DH IMP interface.\" \"\" acc(4)\n.xx \"\" \"accept:\" \"accept a connection on a socket.\" \"\" accept(2)\n.xx \"\" \"\" \"accept: accept a connection on a socket.\" \"\" accept(2)\n.xx \"\" \"\" \"access: determine accessability of a file.\" \"\" access(3F)\n.xx \"\" \"\" \"access: determine accessibility of file.\" \"\" access(2)\n.xx \"\" \"getgroups: get group\" \"access list.\" \"\" getgroups(2)\n.xx \"\" \"initgroups: initialize group\" \"access list.\" \"\" initgroups(3)\n.xx \"\" \"setgroups: set group\" \"access list.\" \"\" setgroups(2)\n.xx \"\" \"access: determine\" \"accessability of a file.\" \"\" access(3F)\n.xx \"\" \"access: determine\" \"accessibility of file.\" \"\" access(2)\n.xx \"\" \"ac: login\" \"accounting.\" \"\" ac(8)\n.xx \"\" \"sa, accton: system\" \"accounting.\" \"\" sa(8)\n.xx \"\" \"acct: execution\" \"accounting file.\" \"\" acct(5)\n.xx \"\" \"pac: printer/plotter\" \"accounting information.\" \"\" pac(8)\n.xx \"\" \"acct: turn\" \"accounting on or off.\" \"\" acct(2)\n.xx \"\" \"\" \"acct: execution accounting file.\" \"\" acct(5)\n.xx \"\" \"\" \"acct: turn accounting on or off.\" \"\" acct(2)\n.xx \"\" \"sa,\" \"accton: system accounting.\" \"\" sa(8)\n.xx \"their inverses.\" \"sin, cos, tan, asin,\" \"acos, atan, atan2: trigonometric functions and\" \"\" sin(3M)\n.xx \"\" \"asinh,\" \"acosh, atanh: inverse hyperbolic functions.\" \"\" asinh(3M)\n.xx \"\" \"signal: change the\" \"action for a signal.\" \"\" signal(3F)\n.xx \"\" \"ad: Data Translation\" \"A/D converter.\" \"\" ad(4)\n.xx \"\" \"\" \"ad: Data Translation A/D converter.\" \"\" ad(4)\n.xx \"\" \"fortune: print a random, hopefully interesting,\" \"adage.\" \"\" fortune(6)\n.xx \"\" \"\" \"adb: debugger.\" \"\" adb(1)\n.xx \"\" \"swapon:\" \"add a swap device for interleaved paging/swapping.\" \"\" swapon(2)\n.xx \"\" \"\" \"addbib: create or extend bibliographic database.\" \"\" addbib(1)\n.xx \"\" \"adduser: procedure for\" \"adding new users.\" \"\" adduser(8)\n.xx \"\" \"swapon: specify\" \"additional device for paging and swapping.\" \"\" swapon(8)\n.xx \"\" \"ns_addr, ns_ntoa: Xerox NS(tm)\" \"address conversion routines.\" \"\" ns(3N)\n.xx \"\" \"inet_makeaddr, inet_lnaof, inet_netof: Internet\" \"address manipulation routines.\" \"/inet_ntoa,\" inet(3N)\n.xx \"\" \"loc: return the\" \"address of an object.\" \"\" loc(3F)\n.xx \"\" \"arp:\" \"address resolution display and control.\" \"\" arp(8C)\n.xx \"\" \"arp:\" \"Address Resolution Protocol.\" \"\" arp(4P)\n.xx \"\" \"mailaddr: mail\" \"addressing description.\" \"\" mailaddr(7)\n.xx \"\" \"\" \"adduser: procedure for adding new users.\" \"\" adduser(8)\n.xx \"of the system clock.\" \"\" \"adjtime: correct the time to allow synchronization\" \"\" adjtime(2)\n.xx \"\" \"\" \"adventure: an exploration game.\" \"\" adventure(6)\n.xx \"\" \"battlestar: a tropical\" \"adventure game.\" \"\" battlestar(6)\n.xx \"\" \"flock: apply or remove an\" \"advisory lock on an open file.\" \"\" flock(2)\n.xx \"\" \"yes: be repetitively\" \"affirmative.\" \"\" yes(1)\n.xx \"\" \"basename: strip filename\" \"affixes.\" \"\" basename(1)\n.xx \"\" \"learn: computer\" \"aided instruction about UNIX.\" \"\" learn(1)\n.xx \"\" \"\" \"alarm: execute a subroutine after a specified time.\" \"\" alarm(3F)\n.xx \"\" \"\" \"alarm: schedule signal after specified time.\" \"\" alarm(3C)\n.xx \"\" \"L.aliases: UUCP hostname\" \"alias file.\" \"\" L.aliases(5)\n.xx \"\" \"\" \"alias: shell macros.\" \"\" csh(1)\n.xx \"\" \"unalias: remove\" \"aliases.\" \"\" csh(1)\n.xx \"\" \"\" \"aliases: aliases file for sendmail.\" \"\" aliases(5)\n.xx \"\" \"which: locate a program file including\" \"aliases and paths (\\fIcsh\\fR only).\" \"\" which(1)\n.xx \"\" \"newaliases: rebuild the data base for the mail\" \"aliases file.\" \"\" newaliases(1)\n.xx \"\" \"aliases:\" \"aliases file for sendmail.\" \"\" aliases(5)\n.xx \"\" \"L.\" \"aliases: UUCP hostname alias file.\" \"\" L.aliases(5)\n.xx \"\" \"valloc:\" \"aligned memory allocator.\" \"\" valloc(3C)\n.xx \"\" \"malloc, free, realloc, calloc,\" \"alloca: memory allocator.\" \"\" malloc(3)\n.xx \"\" \"malloc, free, realloc, calloc, alloca: memory\" \"allocator.\" \"\" malloc(3)\n.xx \"\" \"malloc, free, falloc: memory\" \"allocator.\" \"\" malloc(3F)\n.xx \"\" \"valloc: aligned memory\" \"allocator.\" \"\" valloc(3C)\n.xx \"\" \"scandir,\" \"alphasort: scan a directory.\" \"\" scandir(3)\n.xx \"\" \"limit:\" \"alter per-process resource limitations.\" \"\" csh(1)\n.xx \"\" \"renice:\" \"alter priority of running processes.\" \"\" renice(8)\n.xx \"\" \"else:\" \"alternative commands.\" \"\" csh(1)\n.xx \"\" \"lex: generator of lexical\" \"analysis programs.\" \"\" lex(1)\n.xx \"\" \"error:\" \"analyze and disperse compiler error messages.\" \"\" error(1)\n.xx \"\" \"style:\" \"analyze surface characteristics of a document.\" \"\" style(1)\n.xx \"\" \"worms:\" \"animate worms on a display terminal.\" \"\" worms(6)\n.xx \"\" \"rain:\" \"animated raindrops display.\" \"\" rain(6)\n.xx \"\" \"bcd: convert to\" \"antique media.\" \"\" bcd(6)\n.xx \"\" \"sticky: persistent text and\" \"append-only directories.\" \"\" sticky(8)\n.xx \"\" \"apply:\" \"apply a command to a set of arguments.\" \"\" apply(1)\n.xx \"\" \"\" \"apply: apply a command to a set of arguments.\" \"\" apply(1)\n.xx \"\" \"flock:\" \"apply or remove an advisory lock on an open file.\" \"\" flock(2)\n.xx \"\" \"patch: a program for\" \"applying a diff file to an original.\" \"\" patch(1)\n.xx \"\" \"\" \"apropos: locate commands by keyword lookup.\" \"\" apropos(1)\n.xx \"\" \"\" \"ar: archive and library maintainer.\" \"\" ar(1)\n.xx \"\" \"\" \"ar: archive (library) file format.\" \"\" ar(5)\n.xx \"\" \"number: convert\" \"Arabic numerals to English.\" \"\" number(6)\n.xx \"\" \"bc:\" \"arbitrary-precision arithmetic language.\" \"\" bc(1)\n.xx \"graphics/\" \"plot: openpl, erase, label, line, circle,\" \"arc, move, cont, point, linemod, space, closepl:\" \"\" plot(3X)\n.xx \"\" \"tp: manipulate tape\" \"archive.\" \"\" tp(1)\n.xx \"\" \"ar:\" \"archive and library maintainer.\" \"\" ar(1)\n.xx \"\" \"tar: tape\" \"archive file format.\" \"\" tar(5)\n.xx \"\" \"ar:\" \"archive (library) file format.\" \"\" ar(5)\n.xx \"\" \"tar: tape\" \"archiver.\" \"\" tar(1)\n.xx \"\" \"arff, flcopy:\" \"archiver and copier for floppy.\" \"\" arff(8V)\n.xx \"\" \"ranlib: convert\" \"archives to random libraries.\" \"\" ranlib(1)\n.xx \"\" \"\" \"arff, flcopy: archiver and copier for floppy.\" \"\" arff(8V)\n.xx \"\" \"glob: filename expand\" \"argument list.\" \"\" csh(1)\n.xx \"\" \"shift: manipulate\" \"argument list.\" \"\" csh(1)\n.xx \"\" \"varargs: variable\" \"argument list.\" \"\" varargs(3)\n.xx \"\" \"apply: apply a command to a set of\" \"arguments.\" \"\" apply(1)\n.xx \"\" \"echo: echo\" \"arguments.\" \"\" csh(1)\n.xx \"\" \"echo: echo\" \"arguments.\" \"\" echo(1)\n.xx \"\" \"getarg, iargc: return command line\" \"arguments.\" \"\" getarg(3F)\n.xx \"\" \"expr: evaluate\" \"arguments as an expression.\" \"\" expr(1)\n.xx \"\" \"getopt: get option letter from\" \"argv.\" \"\" getopt(3)\n.xx \"\" \"m_out, sdiv, itom: multiple precision integer\" \"arithmetic.\" \"/omin, fmin, m_in, mout, omout, fmout,\" mp(3X)\n.xx \"\" \"traper: trap\" \"arithmetic errors.\" \"\" traper(3F)\n.xx \"\" \"bc: arbitrary-precision\" \"arithmetic language.\" \"\" bc(1)\n.xx \"\" \"@:\" \"arithmetic on shell variables.\" \"\" csh(1)\n.xx \"\" \"\" \"arithmetic: provide drill in number facts.\" \"\" arithmetic(6)\n.xx \"\" \"\" \"arp: address resolution display and control.\" \"\" arp(8C)\n.xx \"\" \"\" \"arp: Address Resolution Protocol.\" \"\" arp(4P)\n.xx \"\" \"ftp:\" \"ARPANET file transfer program.\" \"\" ftp(1C)\n.xx \"\" \"biff: be notified if mail\" \"arrives and who it is from.\" \"\" biff(1)\n.xx \"\" \"readnews: read news\" \"articles.\" \"\" readnews(1)\n.xx \"\" \"vnews: read news\" \"articles.\" \"\" vnews(1)\n.xx \"\" \"expr: evaluate arguments\" \"as an expression.\" \"\" expr(1)\n.xx \"\" \"slattach: attach serial lines\" \"as network interfaces.\" \"\" slattach(8C)\n.xx \"\" \"\" \"as: VAX-11 assembler.\" \"\" as(1)\n.xx \"\" \"gmtime, asctime, timezone: convert date and time to\" \"ASCII.\" \"ctime, localtime,\" ctime(3)\n.xx \"\" \"ascii: map of\" \"ASCII character set.\" \"\" ascii(7)\n.xx \"\" \"od: octal, decimal, hex,\" \"ascii dump.\" \"\" od(1)\n.xx \"\" \"map3270: database for mapping\" \"ascii keystrokes into IBM 3270 keys.\" \"\" map3270(5)\n.xx \"\" \"\" \"ascii: map of ASCII character set.\" \"\" ascii(7)\n.xx \"\" \"fdate: return date and time in an\" \"ASCII string.\" \"\" fdate(3F)\n.xx \"\" \"mset: retrieve\" \"ASCII to IBM 3270 keyboard map.\" \"\" mset(1)\n.xx \"\" \"atof, atoi, atol: convert\" \"ASCII to numbers.\" \"\" atof(3)\n.xx \"\" \"ctime, localtime, gmtime,\" \"asctime, timezone: convert date and time to ASCII.\" \"\" ctime(3)\n.xx \"and their inverses.\" \"sin, cos, tan,\" \"asin, acos, atan, atan2: trigonometric functions\" \"\" sin(3M)\n.xx \"\" \"\" \"asinh, acosh, atanh: inverse hyperbolic functions.\" \"\" asinh(3M)\n.xx \"\" \"as: VAX-11\" \"assembler.\" \"\" as(1)\n.xx \"\" \"a.out:\" \"assembler and link editor output.\" \"\" a.out(5)\n.xx \"\" \"\" \"assert: program verification.\" \"\" assert(3)\n.xx \"\" \"setbuf, setbuffer, setlinebuf:\" \"assign buffering to a stream.\" \"\" setbuf(3S)\n.xx \"\" \"atrm: remove jobs spooled by\" \"at.\" \"\" atrm(1)\n.xx \"\" \"shutdown: close down the system\" \"at a given time.\" \"\" shutdown(8)\n.xx \"\" \"at: execute commands\" \"at a later time.\" \"\" at(1)\n.xx \"\" \"\" \"at: execute commands at a later time.\" \"\" at(1)\n.xx \"\" \"nice, nohup: run a command\" \"at low priority (\\fIsh\\fR only).\" \"\" nice(1)\n.xx \"inverses.\" \"sin, cos, tan, asin, acos,\" \"atan, atan2: trigonometric functions and their\" \"\" sin(3M)\n.xx \"\" \"sin, cos, tan, asin, acos, atan,\" \"atan2: trigonometric functions and their inverses.\" \"\" sin(3M)\n.xx \"\" \"asinh, acosh,\" \"atanh: inverse hyperbolic functions.\" \"\" asinh(3M)\n.xx \"\" \"\" \"atof, atoi, atol: convert ASCII to numbers.\" \"\" atof(3)\n.xx \"\" \"atof,\" \"atoi, atol: convert ASCII to numbers.\" \"\" atof(3)\n.xx \"\" \"atof, atoi,\" \"atol: convert ASCII to numbers.\" \"\" atof(3)\n.xx \"interrupt.\" \"sigpause:\" \"atomically release blocked signals and wait for\" \"\" sigpause(2)\n.xx \"\" \"\" \"atq: print the queue of jobs waiting to be run.\" \"\" atq(1)\n.xx \"\" \"\" \"atrm: remove jobs spooled by at.\" \"\" atrm(1)\n.xx \"\" \"slattach:\" \"attach serial lines as network interfaces.\" \"\" slattach(8C)\n.xx \"\" \"dn: DN-11\" \"autocall unit interface.\" \"\" dn(4)\n.xx \"code.\" \"\" \"autoconf: diagnostics from the autoconfiguration\" \"\" autoconf(4)\n.xx \"\" \"autoconf: diagnostics from the\" \"autoconfiguration code.\" \"\" autoconf(4)\n.xx \"\" \"bugfiler: file bug reports in folders\" \"automatically.\" \"\" bugfiler(8)\n.xx \"\" \"rc: command script for\" \"auto-reboot and daemons.\" \"\" rc(8)\n.xx \"\" \"notes,\" \"autoseq, readnotes: a news system.\" \"\" notes(1)\n.xx \"\" \"wait:\" \"await completion of process.\" \"\" wait(1)\n.xx \"\" \"\" \"awk: pattern scanning and processing language.\" \"\" awk(1)\n.xx \"\" \"\" \"backgammon: the game.\" \"\" backgammon(6)\n.xx \"\" \"bg: place job in\" \"background.\" \"\" csh(1)\n.xx \"\" \"wait: wait for\" \"background processes to complete.\" \"\" csh(1)\n.xx \"\" \"bad144: read/write dec standard 144\" \"bad sector information.\" \"\" bad144(8)\n.xx \"\" \"badsect: create files to contain\" \"bad sectors.\" \"\" badsect(8)\n.xx \"information.\" \"\" \"bad144: read/write dec standard 144 bad sector\" \"\" bad144(8)\n.xx \"\" \"\" \"badsect: create files to contain bad sectors.\" \"\" badsect(8)\n.xx \"\" \"banner: print large\" \"banner on printer.\" \"\" banner(6)\n.xx \"\" \"\" \"banner: print large banner on printer.\" \"\" banner(6)\n.xx \"\" \"gettytab: terminal configuration data\" \"base.\" \"\" gettytab(5)\n.xx \"\" \"hosts: host name data\" \"base.\" \"\" hosts(5)\n.xx \"\" \"networks: network name data\" \"base.\" \"\" networks(5)\n.xx \"\" \"phones: remote host phone number data\" \"base.\" \"\" phones(5)\n.xx \"\" \"printcap: printer capability data\" \"base.\" \"\" printcap(5)\n.xx \"\" \"protocols: protocol name data\" \"base.\" \"\" protocols(5)\n.xx \"\" \"services: service name data\" \"base.\" \"\" services(5)\n.xx \"\" \"termcap: terminal capability data\" \"base.\" \"\" termcap(5)\n.xx \"\" \"vgrindefs: vgrind's language definition data\" \"base.\" \"\" vgrindefs(5)\n.xx \"\" \"newaliases: rebuild the data\" \"base for the mail aliases file.\" \"\" newaliases(1)\n.xx \"\" \"fetch, store, delete, firstkey, nextkey: data\" \"base subroutines.\" \"dbminit,\" dbm(3X)\n.xx \"\" \"dbm_nextkey, dbm_error, dbm_clearerr: data\" \"base subroutines.\" \"/dbm_delete, dbm_firstkey,\" ndbm(3)\n.xx \"\" \"vi: screen oriented (visual) display editor\" \"based on ex.\" \"\" vi(1)\n.xx \"\" \"\" \"basename: strip filename affixes.\" \"\" basename(1)\n.xx \"\" \"\" \"battlestar: a tropical adventure game.\" \"\" battlestar(6)\n.xx \"\" \"\" \"bc: arbitrary-precision arithmetic language.\" \"\" bc(1)\n.xx \"\" \"\" \"bcd: convert to antique media.\" \"\" bcd(6)\n.xx \"\" \"bcopy,\" \"bcmp, bzero, ffs: bit and byte string operations.\" \"\" bstring(3)\n.xx \"operations.\" \"\" \"bcopy, bcmp, bzero, ffs: bit and byte string\" \"\" bstring(3)\n.xx \"\" \"cb: C program\" \"beautifier.\" \"\" cb(1)\n.xx \"\" \"va:\" \"Benson-Varian interface.\" \"\" va(4)\n.xx \"\" \"vfont: font formats for the\" \"Benson-Varian or Versatec.\" \"\" vfont(5)\n.xx \"\" \"j0, j1, jn, y0, y1, yn:\" \"bessel functions.\" \"\" j0(3M)\n.xx \"\" \"\" \"bessel functions: of two kinds for integer orders.\" \"\" bessel(3F)\n.xx \"\" \"random, drandm, irandm:\" \"better random number generator.\" \"\" random(3F)\n.xx \"changing/\" \"random, srandom, initstate, setstate:\" \"better random number generator; routines for\" \"\" random(3)\n.xx \"\" \"\" \"bg: place job in background.\" \"\" csh(1)\n.xx \"bibliographic reference items.\" \"\" \"bib, listrefs: bibliographic formatter; list\" \"\" bib(1)\n.xx \"\" \"addbib: create or extend\" \"bibliographic database.\" \"\" addbib(1)\n.xx \"\" \"roffbib: run off\" \"bibliographic database.\" \"\" roffbib(1)\n.xx \"\" \"sortbib: sort\" \"bibliographic database.\" \"\" sortbib(1)\n.xx \"reference items.\" \"bib, listrefs:\" \"bibliographic formatter; list bibliographic\" \"\" bib(1)\n.xx \"\" \"bib, listrefs: bibliographic formatter; list\" \"bibliographic reference items.\" \"\" bib(1)\n.xx \"\" \"index for a bibliography, find references in a\" \"bibliography.\" \"indxbib, lookbib: build inverted\" lookbib(1)\n.xx \"\" \"indxbib, lookbib: build inverted index for a\" \"bibliography, find references in a bibliography.\" \"\" lookbib(1)\n.xx \"from.\" \"\" \"biff: be notified if mail arrives and who it is\" \"\" biff(1)\n.xx \"\" \"comsat:\" \"biff server.\" \"\" comsat(8C)\n.xx \"\" \"install: install\" \"binaries.\" \"\" install(1)\n.xx \"\" \"whereis: locate source,\" \"binary, and or manual for program.\" \"\" whereis(1)\n.xx \"\" \"find the printable strings in a object, or other\" \"binary, file.\" \"strings:\" strings(1)\n.xx \"\" \"uuencode, uudecode: encode/decode a\" \"binary file for transmission via mail.\" \"\" uuencode(1C)\n.xx \"\" \"fread, fwrite: buffered\" \"binary input/output.\" \"\" fread(3S)\n.xx \"\" \"bind:\" \"bind a name to a socket.\" \"\" bind(2)\n.xx \"\" \"\" \"bind: bind a name to a socket.\" \"\" bind(2)\n.xx \"\" \"\" \"binmail: send or receive mail among users.\" \"\" binmail(1)\n.xx \"\" \"bcopy, bcmp, bzero, ffs:\" \"bit and byte string operations.\" \"\" bstring(3)\n.xx \"functions.\" \"\" \"bit: and, or, xor, not, rshift, lshift bitwise\" \"\" bit(3F)\n.xx \"\" \"bit: and, or, xor, not, rshift, lshift\" \"bitwise functions.\" \"\" bit(3F)\n.xx \"communication (obsolete).\" \"\" \"bk: line discipline for machine-machine\" \"\" bk(4)\n.xx \"\" \"sync: update the super\" \"block.\" \"\" sync(8)\n.xx \"\" \"update: periodically update the super\" \"block.\" \"\" update(8)\n.xx \"\" \"sigblock:\" \"block signals.\" \"\" sigblock(2)\n.xx \"\" \"sigpause: atomically release\" \"blocked signals and wait for interrupt.\" \"\" sigpause(2)\n.xx \"\" \"sum: sum and count\" \"blocks in a file.\" \"\" sum(1)\n.xx \"\" \"boggle: play the game of\" \"boggle.\" \"\" boggle(6)\n.xx \"\" \"\" \"boggle: play the game of boggle.\" \"\" boggle(6)\n.xx \"\" \"ching: the\" \"book of changes and other cookies.\" \"\" ching(6)\n.xx \"\" \"reboot: UNIX\" \"bootstrapping procedures.\" \"\" reboot(8)\n.xx \"\" \"mille: play Mille\" \"Bournes.\" \"\" mille(6)\n.xx \"\" \"switch: multi-way command\" \"branch.\" \"\" csh(1)\n.xx \"login,/\" \"sh, for, case, if, while, \\fB:\\fP, \\fB.\\fP,\" \"break, continue, cd, eval, exec, exit, export,\" \"\" sh(1)\n.xx \"\" \"\" \"break: exit while/foreach loop.\" \"\" csh(1)\n.xx \"\" \"\" \"breaksw: exit from switch.\" \"\" csh(1)\n.xx \"\" \"fg:\" \"bring job into foreground.\" \"\" csh(1)\n.xx \"\" \"\" \"brk, sbrk: change data segment size.\" \"\" brk(2)\n.xx \"\" \"ik: Ikonas frame\" \"buffer, graphics device interface.\" \"\" ik(4)\n.xx \"\" \"fread, fwrite:\" \"buffered binary input/output.\" \"\" fread(3S)\n.xx \"\" \"stdio: standard\" \"buffered input/output package.\" \"\" stdio(3S)\n.xx \"\" \"setbuf, setbuffer, setlinebuf: assign\" \"buffering to a stream.\" \"\" setbuf(3S)\n.xx \"\" \"generate a dump of the operating system's profile\" \"buffers.\" \"kgmon:\" kgmon(8)\n.xx \"\" \"sendbug: mail a system\" \"bug report to 4bsd-bugs.\" \"\" sendbug(1)\n.xx \"\" \"bugfiler: file\" \"bug reports in folders automatically.\" \"\" bugfiler(8)\n.xx \"automatically.\" \"\" \"bugfiler: file bug reports in folders\" \"\" bugfiler(8)\n.xx \"references in a bibliography.\" \"indxbib, lookbib:\" \"build inverted index for a bibliography, find\" \"\" lookbib(1)\n.xx \"\" \"mknod:\" \"build special file.\" \"\" mknod(8)\n.xx \"\" \"config:\" \"build system configuration files.\" \"\" config(8)\n.xx \"\" \"ntohs: convert values between host and network\" \"byte order.\" \"htonl, htons, ntohl,\" byteorder(3N)\n.xx \"\" \"bcopy, bcmp, bzero, ffs: bit and\" \"byte string operations.\" \"\" bstring(3)\n.xx \"\" \"swab: swap\" \"bytes.\" \"\" swab(3)\n.xx \"\" \"bcopy, bcmp,\" \"bzero, ffs: bit and byte string operations.\" \"\" bstring(3)\n.xx \"\" \"cc:\" \"C compiler.\" \"\" cc(1)\n.xx \"\" \"intro: introduction to\" \"C library functions.\" \"\" intro(3)\n.xx \"\" \"cb:\" \"C program beautifier.\" \"\" cb(1)\n.xx \"\" \"indent: indent and format\" \"C program source.\" \"\" indent(1)\n.xx \"\" \"lint: a\" \"C program verifier.\" \"\" lint(1)\n.xx \"\" \"xstr: extract strings from\" \"C programs to implement shared strings.\" \"\" xstr(1)\n.xx \"\" \"mkstr: create an error message file by massaging\" \"C source.\" \"\" mkstr(1)\n.xx \"\" \"hypot,\" \"cabs: Euclidean distance, complex absolute value.\" \"\" hypot(3M)\n.xx \"\" \"\" \"cal: print calendar.\" \"\" cal(1)\n.xx \"\" \"diskpart:\" \"calculate default disk partition sizes.\" \"\" diskpart(8)\n.xx \"\" \"dc: desk\" \"calculator.\" \"\" dc(1)\n.xx \"\" \"cal: print\" \"calendar.\" \"\" cal(1)\n.xx \"\" \"\" \"calendar: reminder service.\" \"\" calendar(1)\n.xx \"\" \"syscall: indirect system\" \"call.\" \"\" syscall(2)\n.xx \"\" \"gprof: display\" \"call graph profile data.\" \"\" gprof(1)\n.xx \"\" \"getuid, getgid: get user or group ID of the\" \"caller.\" \"\" getuid(3F)\n.xx \"\" \"malloc, free, realloc,\" \"calloc, alloca: memory allocator.\" \"\" malloc(3)\n.xx \"\" \"siginterrupt: allow signals to interrupt system\" \"calls.\" \"\" siginterrupt(3)\n.xx \"\" \"intro: introduction to system\" \"calls and error numbers.\" \"\" intro(2)\n.xx \"\" \"canfield, cfscores: the solitaire card game\" \"canfield.\" \"\" canfield(6)\n.xx \"canfield.\" \"\" \"canfield, cfscores: the solitaire card game\" \"\" canfield(6)\n.xx \"\" \"printcap: printer\" \"capability data base.\" \"\" printcap(5)\n.xx \"\" \"termcap: terminal\" \"capability data base.\" \"\" termcap(5)\n.xx \"\" \"canfield, cfscores: the solitaire\" \"card game canfield.\" \"\" canfield(6)\n.xx \"\" \"cribbage: the\" \"card game cribbage.\" \"\" cribbage(6)\n.xx \"cd, eval, exec, exit, export, login,/\" \"sh, for,\" \"case, if, while, \\fB:\\fP, \\fB.\\fP, break, continue,\" \"\" sh(1)\n.xx \"\" \"\" \"case: selector in switch.\" \"\" csh(1)\n.xx \"\" \"tu: VAX-11/730 and VAX-11/750 TU58 console\" \"cassette interface.\" \"\" tu(4)\n.xx \"\" \"uu: TU58/DECtape II UNIBUS\" \"cassette interface.\" \"\" uu(4)\n.xx \"\" \"\" \"cat: catenate and print.\" \"\" cat(1)\n.xx \"\" \"catman: create the\" \"cat files for the manual.\" \"\" catman(8)\n.xx \"\" \"default:\" \"catchall clause in switch.\" \"\" csh(1)\n.xx \"\" \"cat:\" \"catenate and print.\" \"\" cat(1)\n.xx \"\" \"\" \"catman: create the cat files for the manual.\" \"\" catman(8)\n.xx \"\" \"\" \"cb: C program beautifier.\" \"\" cb(1)\n.xx \"\" \"\" \"cbrt, sqrt: cube root, square root.\" \"\" sqrt(3M)\n.xx \"\" \"\" \"cc: C compiler.\" \"\" cc(1)\n.xx \"\" \"\" \"cd: change directory.\" \"\" csh(1)\n.xx \"\" \"\" \"cd: change working directory.\" \"\" cd(1)\n.xx \"\" \"case, if, while, \\fB:\\fP, \\fB.\\fP, break, continue,\" \"cd, eval, exec, exit, export, login, read,/\" \"/for,\" sh(1)\n.xx \"round-to-nearest functions.\" \"fabs, floor,\" \"ceil, rint: absolute value, floor, ceiling, and\" \"\" floor(3M)\n.xx \"\" \"fabs, floor, ceil, rint: absolute value, floor,\" \"ceiling, and round-to-nearest functions.\" \"\" floor(3M)\n.xx \"\" \"canfield,\" \"cfscores: the solitaire card game canfield.\" \"\" canfield(6)\n.xx \"\" \"chdir:\" \"change current working directory.\" \"\" chdir(2)\n.xx \"\" \"brk, sbrk:\" \"change data segment size.\" \"\" brk(2)\n.xx \"\" \"chdir:\" \"change default directory.\" \"\" chdir(3F)\n.xx \"\" \"cd:\" \"change directory.\" \"\" csh(1)\n.xx \"\" \"chdir:\" \"change directory.\" \"\" csh(1)\n.xx \"\" \"ioinit:\" \"change f77 I/O initialization.\" \"\" ioinit(3F)\n.xx \"\" \"chgrp:\" \"change group.\" \"\" chgrp(1)\n.xx \"\" \"chmod:\" \"change mode.\" \"\" chmod(1)\n.xx \"\" \"chmod:\" \"change mode of a file.\" \"\" chmod(3F)\n.xx \"\" \"chmod:\" \"change mode of file.\" \"\" chmod(2)\n.xx \"\" \"umask:\" \"change or display file creation mask.\" \"\" csh(1)\n.xx \"\" \"chown:\" \"change owner.\" \"\" chown(8)\n.xx \"\" \"chown:\" \"change owner and group of a file.\" \"\" chown(2)\n.xx \"\" \"chfn, chsh, passwd:\" \"change password file information.\" \"\" chfn(1)\n.xx \"\" \"chfn, chsh, passwd:\" \"change password file information.\" \"\" chsh(1)\n.xx \"\" \"chfn, chsh, passwd:\" \"change password file information.\" \"\" passwd(1)\n.xx \"\" \"chroot:\" \"change root directory.\" \"\" chroot(2)\n.xx \"\" \"signal:\" \"change the action for a signal.\" \"\" signal(3F)\n.xx \"\" \"rename:\" \"change the name of a file.\" \"\" rename(2)\n.xx \"\" \"set:\" \"change value of shell variable.\" \"\" csh(1)\n.xx \"\" \"cd:\" \"change working directory.\" \"\" cd(1)\n.xx \"\" \"ching: the book of\" \"changes and other cookies.\" \"\" ching(6)\n.xx \"\" \"better random number generator; routines for\" \"changing generators.\" \"/srandom, initstate, setstate:\" random(3)\n.xx \"\" \"pipe: create an interprocess communication\" \"channel.\" \"\" pipe(2)\n.xx \"\" \"ungetc: push\" \"character back into input stream.\" \"\" ungetc(3S)\n.xx \"\" \"iscntrl, isascii, toupper, tolower, toascii:\" \"character classification macros.\" \"/isprint, isgraph,\" ctype(3)\n.xx \"\" \"eqnchar: special\" \"character definitions for eqn.\" \"\" eqnchar(7)\n.xx \"\" \"getc, fgetc: get a\" \"character from a logical unit.\" \"\" getc(3F)\n.xx \"\" \"index, rindex, lnblnk, len: tell about\" \"character objects.\" \"\" index(3F)\n.xx \"\" \"getc, getchar, fgetc, getw: get\" \"character or word from stream.\" \"\" getc(3S)\n.xx \"\" \"putc, putchar, fputc, putw: put\" \"character or word on a stream.\" \"\" putc(3S)\n.xx \"\" \"ascii: map of ASCII\" \"character set.\" \"\" ascii(7)\n.xx \"\" \"putc, fputc: write a\" \"character to a fortran logical unit.\" \"\" putc(3F)\n.xx \"\" \"style: analyze surface\" \"characteristics of a document.\" \"\" style(1)\n.xx \"\" \"tr: translate\" \"characters.\" \"\" tr(1)\n.xx \"\" \"snake, snscore: display\" \"chase game.\" \"\" snake(6)\n.xx \"\" \"\" \"chdir: change current working directory.\" \"\" chdir(2)\n.xx \"\" \"\" \"chdir: change default directory.\" \"\" chdir(3F)\n.xx \"\" \"\" \"chdir: change directory.\" \"\" csh(1)\n.xx \"\" \"dcheck: file system directory consistency\" \"check.\" \"\" dcheck(8)\n.xx \"\" \"icheck: file system storage consistency\" \"check.\" \"\" icheck(8)\n.xx \"\" \"fsck: file system consistency\" \"check and interactive repair.\" \"\" fsck(8)\n.xx \"\" \"checknr:\" \"check nroff/troff files.\" \"\" checknr(1)\n.xx \"\" \"eqn, neqn,\" \"checkeq: typeset mathematics.\" \"\" eqn(1)\n.xx \"\" \"quotacheck: file system quota consistency\" \"checker.\" \"\" quotacheck(8)\n.xx \"\" \"fastboot, fasthalt: reboot/halt the system without\" \"checking the disks.\" \"\" fastboot(8)\n.xx \"\" \"\" \"checknr: check nroff/troff files.\" \"\" checknr(1)\n.xx \"\" \"chess: the game of\" \"chess.\" \"\" chess(6)\n.xx \"\" \"\" \"chess: the game of chess.\" \"\" chess(6)\n.xx \"information.\" \"\" \"chfn, chsh, passwd: change password file\" \"\" chfn(1)\n.xx \"information.\" \"\" \"chfn, chsh, passwd: change password file\" \"\" chsh(1)\n.xx \"information.\" \"\" \"chfn, chsh, passwd: change password file\" \"\" passwd(1)\n.xx \"\" \"\" \"chgrp: change group.\" \"\" chgrp(1)\n.xx \"\" \"\" \"ching: the book of changes and other cookies.\" \"\" ching(6)\n.xx \"\" \"\" \"chmod: change mode.\" \"\" chmod(1)\n.xx \"\" \"\" \"chmod: change mode of a file.\" \"\" chmod(3F)\n.xx \"\" \"\" \"chmod: change mode of file.\" \"\" chmod(2)\n.xx \"\" \"\" \"chown: change owner.\" \"\" chown(8)\n.xx \"\" \"\" \"chown: change owner and group of a file.\" \"\" chown(2)\n.xx \"\" \"\" \"chroot: change root directory.\" \"\" chroot(2)\n.xx \"\" \"chfn,\" \"chsh, passwd: change password file information.\" \"\" chfn(1)\n.xx \"\" \"chfn,\" \"chsh, passwd: change password file information.\" \"\" chsh(1)\n.xx \"\" \"chfn,\" \"chsh, passwd: change password file information.\" \"\" passwd(1)\n.xx \"closepl:/\" \"plot: openpl, erase, label, line,\" \"circle, arc, move, cont, point, linemod, space,\" \"\" plot(3X)\n.xx \"\" \"isascii, toupper, tolower, toascii: character\" \"classification macros.\" \"/isprint, isgraph, iscntrl,\" ctype(3)\n.xx \"\" \"default: catchall\" \"clause in switch.\" \"\" csh(1)\n.xx \"\" \"uuclean: uucp spool directory\" \"clean-up.\" \"\" uuclean(8C)\n.xx \"\" \"\" \"clear: clear terminal screen.\" \"\" clear(1)\n.xx \"\" \"clri:\" \"clear i-node.\" \"\" clri(8)\n.xx \"\" \"clear:\" \"clear terminal screen.\" \"\" clear(1)\n.xx \"\" \"ferror, feof,\" \"clearerr, fileno: stream status inquiries.\" \"\" ferror(3S)\n.xx \"\" \"csh: a shell (command interpreter) with\" \"C-like syntax.\" \"\" csh(1)\n.xx \"\" \"the time to allow synchronization of the system\" \"clock.\" \"adjtime: correct\" adjtime(2)\n.xx \"\" \"kg: KL-11/DL-11W line\" \"clock.\" \"\" kg(4)\n.xx \"\" \"cron:\" \"clock daemon.\" \"\" cron(8)\n.xx \"\" \"\" \"close: delete a descriptor.\" \"\" close(2)\n.xx \"\" \"shutdown:\" \"close down the system at a given time.\" \"\" shutdown(8)\n.xx \"\" \"fclose, fflush:\" \"close or flush a stream.\" \"\" fclose(3S)\n.xx \"\" \"opendir, readdir, telldir, seekdir, rewinddir,\" \"closedir: directory operations.\" \"\" directory(3)\n.xx \"\" \"syslog, openlog,\" \"closelog, setlogmask: control system log.\" \"\" syslog(3)\n.xx \"\" \"circle, arc, move, cont, point, linemod, space,\" \"closepl: graphics interface.\" \"/erase, label, line,\" plot(3X)\n.xx \"\" \"\" \"clri: clear i-node.\" \"\" clri(8)\n.xx \"\" \"L.\" \"cmds: UUCP remote command permissions file.\" \"\" L.cmds(5)\n.xx \"\" \"\" \"cmp: compare two files.\" \"\" cmp(1)\n.xx \"\" \"autoconf: diagnostics from the autoconfiguration\" \"code.\" \"\" autoconf(4)\n.xx \"\" \"pi: Pascal interpreter\" \"code translator.\" \"\" pi(1)\n.xx \"\" \"\" \"col: filter reverse line feeds.\" \"\" col(1)\n.xx \"\" \"\" \"colcrt: filter nroff output for CRT previewing.\" \"\" colcrt(1)\n.xx \"log.\" \"dmesg:\" \"collect system diagnostic messages to form error\" \"\" dmesg(8)\n.xx \"\" \"\" \"colrm: remove columns from a file.\" \"\" colrm(1)\n.xx \"\" \"colrm: remove\" \"columns from a file.\" \"\" colrm(1)\n.xx \"files.\" \"\" \"comm: select or reject lines common to two sorted\" \"\" comm(1)\n.xx \"\" \"exec: overlay shell with specified\" \"command.\" \"\" csh(1)\n.xx \"\" \"time: time\" \"command.\" \"\" csh(1)\n.xx \"\" \"routines for returning a stream to a remote\" \"command.\" \"rcmd, rresvport, ruserok:\" rcmd(3)\n.xx \"\" \"rexec: return stream to a remote\" \"command.\" \"\" rexec(3)\n.xx \"\" \"system: issue a shell\" \"command.\" \"\" system(3)\n.xx \"\" \"system: execute a UNIX\" \"command.\" \"\" system(3F)\n.xx \"\" \"test: condition\" \"command.\" \"\" test(1)\n.xx \"\" \"time: time a\" \"command.\" \"\" time(1)\n.xx \"\" \"nice, nohup: run a\" \"command at low priority (\\fIsh\\fR only).\" \"\" nice(1)\n.xx \"\" \"switch: multi-way\" \"command branch.\" \"\" csh(1)\n.xx \"\" \"uux: unix to unix\" \"command execution.\" \"\" uux(1C)\n.xx \"\" \"rehash: recompute\" \"command hash table.\" \"\" csh(1)\n.xx \"\" \"unhash: discard\" \"command hash table.\" \"\" csh(1)\n.xx \"\" \"hashstat: print\" \"command hashing statistics.\" \"\" csh(1)\n.xx \"\" \"nohup: run\" \"command immune to hangups.\" \"\" csh(1)\n.xx \"\" \"csh: a shell\" \"(command interpreter) with C-like syntax.\" \"\" csh(1)\n.xx \"\" \"whatis: describe what a\" \"command is.\" \"\" whatis(1)\n.xx \"\" \"readonly, set, shift, times, trap, umask, wait:\" \"command language.\" \"/exec, exit, export, login, read,\" sh(1)\n.xx \"\" \"getarg, iargc: return\" \"command line arguments.\" \"\" getarg(3F)\n.xx \"\" \"L.cmds: UUCP remote\" \"command permissions file.\" \"\" L.cmds(5)\n.xx \"\" \"repeat: execute\" \"command repeatedly.\" \"\" csh(1)\n.xx \"\" \"rc:\" \"command script for auto-reboot and daemons.\" \"\" rc(8)\n.xx \"\" \"onintr: process interrupts in\" \"command scripts.\" \"\" csh(1)\n.xx \"\" \"apply: apply a\" \"command to a set of arguments.\" \"\" apply(1)\n.xx \"\" \"goto:\" \"command transfer.\" \"\" csh(1)\n.xx \"\" \"else: alternative\" \"commands.\" \"\" csh(1)\n.xx \"\" \"intro: introduction to\" \"commands.\" \"\" intro(1)\n.xx \"\" \"introduction to system maintenance and operation\" \"commands.\" \"intro:\" intro(8)\n.xx \"\" \"rcsintro: introduction to RCS\" \"commands.\" \"\" rcsintro(1)\n.xx \"\" \"at: execute\" \"commands at a later time.\" \"\" at(1)\n.xx \"\" \"apropos: locate\" \"commands by keyword lookup.\" \"\" apropos(1)\n.xx \"\" \"while: repeat\" \"commands conditionally.\" \"\" csh(1)\n.xx \"\" \"lastcomm: show last\" \"commands executed in reverse order.\" \"\" lastcomm(1)\n.xx \"\" \"source: read\" \"commands from file.\" \"\" csh(1)\n.xx \"\" \"comm: select or reject lines\" \"common to two sorted files.\" \"\" comm(1)\n.xx \"\" \"socket: create an endpoint for\" \"communication.\" \"\" socket(2)\n.xx \"\" \"pipe: create an interprocess\" \"communication channel.\" \"\" pipe(2)\n.xx \"\" \"bk: line discipline for machine-machine\" \"communication (obsolete).\" \"\" bk(4)\n.xx \"\" \"talkd: remote user\" \"communication server.\" \"\" talkd(8C)\n.xx \"\" \"dmc: DEC DMC-11/DMR-11 point-to-point\" \"communications device.\" \"\" dmc(4)\n.xx \"\" \"dh: DH-11/DM-11\" \"communications multiplexer.\" \"\" dh(4)\n.xx \"\" \"dhu: DHU-11\" \"communications multiplexer.\" \"\" dhu(4)\n.xx \"\" \"dz: DZ-11\" \"communications multiplexer.\" \"\" dz(4)\n.xx \"\" \"users:\" \"compact list of users who are on the system.\" \"\" users(1)\n.xx \"\" \"diff: differential file and directory\" \"comparator.\" \"\" diff(1)\n.xx \"\" \"cmp:\" \"compare two files.\" \"\" cmp(1)\n.xx \"\" \"diff3: 3-way differential file\" \"comparison.\" \"\" diff3(1)\n.xx \"\" \"liszt:\" \"compile a Franz Lisp program.\" \"\" liszt(1)\n.xx \"\" \"cc: C\" \"compiler.\" \"\" cc(1)\n.xx \"\" \"f77: Fortran 77\" \"compiler.\" \"\" f77(1)\n.xx \"\" \"pc: Pascal\" \"compiler.\" \"\" pc(1)\n.xx \"\" \"error: analyze and disperse\" \"compiler error messages.\" \"\" error(1)\n.xx \"\" \"yacc: yet another\" \"compiler-compiler.\" \"\" yacc(1)\n.xx \"\" \"fp: Functional Programming language\" \"compiler/interpreter.\" \"\" fp(1)\n.xx \"\" \"wait: wait for background processes to\" \"complete.\" \"\" csh(1)\n.xx \"\" \"wait: await\" \"completion of process.\" \"\" wait(1)\n.xx \"\" \"hypot, cabs: Euclidean distance,\" \"complex absolute value.\" \"\" hypot(3M)\n.xx \"\" \"compress, uncompress, zcat:\" \"compress and expand data.\" \"\" compress(1)\n.xx \"data.\" \"\" \"compress, uncompress, zcat: compress and expand\" \"\" compress(1)\n.xx \"\" \"learn:\" \"computer aided instruction about UNIX.\" \"\" learn(1)\n.xx \"\" \"hangman:\" \"Computer version of the game hangman.\" \"\" hangman(6)\n.xx \"\" \"\" \"comsat: biff server.\" \"\" comsat(8C)\n.xx \"\" \"test:\" \"condition command.\" \"\" test(1)\n.xx \"\" \"endif: terminate\" \"conditional.\" \"\" csh(1)\n.xx \"\" \"if:\" \"conditional statement.\" \"\" csh(1)\n.xx \"\" \"while: repeat commands\" \"conditionally.\" \"\" csh(1)\n.xx \"\" \"\" \"config: build system configuration files.\" \"\" config(8)\n.xx \"\" \"gettytab: terminal\" \"configuration data base.\" \"\" gettytab(5)\n.xx \"\" \"resolver\" \"configuration file.\" \"\" resolver(5)\n.xx \"\" \"config: build system\" \"configuration files.\" \"\" config(8)\n.xx \"\" \"ifconfig:\" \"configure network interface parameters.\" \"\" ifconfig(8C)\n.xx \"\" \"\" \"connect: initiate a connection on a socket.\" \"\" connect(2)\n.xx \"\" \"tip, cu:\" \"connect to a remote system.\" \"\" tip(1C)\n.xx \"\" \"getpeername: get name of\" \"connected peer.\" \"\" getpeername(2)\n.xx \"\" \"socketpair: create a pair of\" \"connected sockets.\" \"\" socketpair(2)\n.xx \"\" \"shutdown: shut down part of a full-duplex\" \"connection.\" \"\" shutdown(2)\n.xx \"\" \"accept: accept a\" \"connection on a socket.\" \"\" accept(2)\n.xx \"\" \"connect: initiate a\" \"connection on a socket.\" \"\" connect(2)\n.xx \"\" \"listen: listen for\" \"connections on a socket.\" \"\" listen(2)\n.xx \"\" \"\" \"cons: VAX-11 console interface.\" \"\" cons(4)\n.xx \"\" \"dcheck: file system directory\" \"consistency check.\" \"\" dcheck(8)\n.xx \"\" \"icheck: file system storage\" \"consistency check.\" \"\" icheck(8)\n.xx \"\" \"fsck: file system\" \"consistency check and interactive repair.\" \"\" fsck(8)\n.xx \"\" \"quotacheck: file system quota\" \"consistency checker.\" \"\" quotacheck(8)\n.xx \"\" \"tu: VAX-11/730 and VAX-11/750 TU58\" \"console cassette interface.\" \"\" tu(4)\n.xx \"\" \"fl:\" \"console floppy interface.\" \"\" fl(4)\n.xx \"\" \"cons: VAX-11\" \"console interface.\" \"\" cons(4)\n.xx \"\" \"crl: VAX 8600\" \"console RL02 interface.\" \"\" crl(4)\n.xx \"\" \"show what versions of object modules were used to\" \"construct a file.\" \"what:\" what(1)\n.xx \"\" \"mkfs:\" \"construct a file system.\" \"\" mkfs(8)\n.xx \"\" \"newfs:\" \"construct a new file system.\" \"\" newfs(8)\n.xx \"\" \"mkproto:\" \"construct a prototype file system.\" \"\" mkproto(8)\n.xx \"\" \"deroff: remove nroff, troff, tbl and eqn\" \"constructs.\" \"\" deroff(1)\n.xx \"\" \"setrlimit: control maximum system resource\" \"consumption.\" \"getrlimit,\" getrlimit(2)\n.xx \"\" \"vlimit: control maximum system resource\" \"consumption.\" \"\" vlimit(3C)\n.xx \"\" \"/openpl, erase, label, line, circle, arc, move,\" \"cont, point, linemod, space, closepl: graphics/\" \"\" plot(3X)\n.xx \"\" \"badsect: create files to\" \"contain bad sectors.\" \"\" badsect(8)\n.xx \"\" \"ls: list\" \"contents of directory.\" \"\" ls(1)\n.xx \"\" \"sigstack: set and/or get signal stack\" \"context.\" \"\" sigstack(2)\n.xx \"\" \"sh, for, case, if, while, \\fB:\\fP, \\fB.\\fP, break,\" \"continue, cd, eval, exec, exit, export, login,/\" \"\" sh(1)\n.xx \"\" \"\" \"continue: cycle in loop.\" \"\" csh(1)\n.xx \"\" \"arp: address resolution display and\" \"control.\" \"\" arp(8C)\n.xx \"\" \"fcntl: file\" \"control.\" \"\" fcntl(2)\n.xx \"\" \"ioctl:\" \"control device.\" \"\" ioctl(2)\n.xx \"\" \"init: process\" \"control initialization.\" \"\" init(8)\n.xx \"\" \"getrlimit, setrlimit:\" \"control maximum system resource consumption.\" \"\" getrlimit(2)\n.xx \"\" \"vlimit:\" \"control maximum system resource consumption.\" \"\" vlimit(3C)\n.xx \"\" \"icmp: Internet\" \"Control Message Protocol.\" \"\" icmp(4P)\n.xx \"\" \"lpc: line printer\" \"control program.\" \"\" lpc(8)\n.xx \"\" \"timedc: timed\" \"control program.\" \"\" timedc(8)\n.xx \"\" \"tcp: Internet Transmission\" \"Control Protocol.\" \"\" tcp(4P)\n.xx \"\" \"syslog, openlog, closelog, setlogmask:\" \"control system log.\" \"\" syslog(3)\n.xx \"\" \"vhangup: virtually ``hangup'' the current\" \"control terminal.\" \"\" vhangup(2)\n.xx \"\" \"uda: UDA-50 disk\" \"controller interface.\" \"\" uda(4)\n.xx \"\" \"up: unibus storage module\" \"controller/drives.\" \"\" up(4)\n.xx \"\" \"term:\" \"conventional names for terminals.\" \"\" term(7)\n.xx \"\" \"ecvt, fcvt, gcvt: output\" \"conversion.\" \"\" ecvt(3)\n.xx \"\" \"long, short: integer object\" \"conversion.\" \"\" long(3F)\n.xx \"\" \"printf, fprintf, sprintf: formatted output\" \"conversion.\" \"\" printf(3S)\n.xx \"\" \"scanf, fscanf, sscanf: formatted input\" \"conversion.\" \"\" scanf(3S)\n.xx \"\" \"units:\" \"conversion program.\" \"\" units(1)\n.xx \"\" \"ns_addr, ns_ntoa: Xerox NS(tm)  address\" \"conversion routines.\" \"\" ns(3N)\n.xx \"\" \"dd:\" \"convert and copy a file.\" \"\" dd(1)\n.xx \"\" \"number:\" \"convert Arabic numerals to English.\" \"\" number(6)\n.xx \"\" \"ranlib:\" \"convert archives to random libraries.\" \"\" ranlib(1)\n.xx \"\" \"atof, atoi, atol:\" \"convert ASCII to numbers.\" \"\" atof(3)\n.xx \"\" \"ctime, localtime, gmtime, asctime, timezone:\" \"convert date and time to ASCII.\" \"\" ctime(3)\n.xx \"\" \"htable:\" \"convert NIC standard format host tables.\" \"\" htable(8)\n.xx \"\" \"bcd:\" \"convert to antique media.\" \"\" bcd(6)\n.xx \"\" \"htonl, htons, ntohl, ntohs:\" \"convert values between host and network byte order.\" \"\" byteorder(3N)\n.xx \"\" \"ad: Data Translation A/D\" \"converter.\" \"\" ad(4)\n.xx \"\" \"ching: the book of changes and other\" \"cookies.\" \"\" ching(6)\n.xx \"\" \"arff, flcopy: archiver and\" \"copier for floppy.\" \"\" arff(8V)\n.xx \"\" \"cp:\" \"copy.\" \"\" cp(1)\n.xx \"\" \"rcp: remote file\" \"copy.\" \"\" rcp(1C)\n.xx \"\" \"uucp: unix to unix\" \"copy.\" \"\" uucp(1C)\n.xx \"\" \"dd: convert and\" \"copy a file.\" \"\" dd(1)\n.xx \"\" \"tcopy:\" \"copy a mag tape.\" \"\" tcopy(1)\n.xx \"\" \"fork: create a\" \"copy of this process.\" \"\" fork(3F)\n.xx \"remainder, exponent manipulations.\" \"\" \"copysign, drem, finite, logb, scalb: copysign,\" \"\" ieee(3M)\n.xx \"\" \"copysign, drem, finite, logb, scalb:\" \"copysign, remainder, exponent manipulations.\" \"\" ieee(3M)\n.xx \"\" \"savecore: save a\" \"core dump of the operating system.\" \"\" savecore(8)\n.xx \"\" \"\" \"core: format of memory image file.\" \"\" core(5)\n.xx \"\" \"gcore: get\" \"core images of running processes.\" \"\" gcore(1)\n.xx \"system clock.\" \"adjtime:\" \"correct the time to allow synchronization of the\" \"\" adjtime(2)\n.xx \"functions and their inverses.\" \"sin,\" \"cos, tan, asin, acos, atan, atan2: trigonometric\" \"\" sin(3M)\n.xx \"\" \"sinh,\" \"cosh, tanh: hyperbolic functions.\" \"\" sinh(3M)\n.xx \"\" \"wc: word\" \"count.\" \"\" wc(1)\n.xx \"\" \"sum: sum and\" \"count blocks in a file.\" \"\" sum(1)\n.xx \"\" \"\" \"cp: copy.\" \"\" cp(1)\n.xx \"\" \"\" \"crash: what happens when the system crashes.\" \"\" crash(8V)\n.xx \"\" \"crash: what happens when the system\" \"crashes.\" \"\" crash(8V)\n.xx \"\" \"\" \"creat: create a new file.\" \"\" creat(2)\n.xx \"\" \"fork:\" \"create a copy of this process.\" \"\" fork(3F)\n.xx \"\" \"creat:\" \"create a new file.\" \"\" creat(2)\n.xx \"\" \"open: open a file for reading or writing, or\" \"create a new file.\" \"\" open(2)\n.xx \"\" \"fork:\" \"create a new process.\" \"\" fork(2)\n.xx \"\" \"socketpair:\" \"create a pair of connected sockets.\" \"\" socketpair(2)\n.xx \"\" \"ctags:\" \"create a tags file.\" \"\" ctags(1)\n.xx \"\" \"socket:\" \"create an endpoint for communication.\" \"\" socket(2)\n.xx \"\" \"mkstr:\" \"create an error message file by massaging C source.\" \"\" mkstr(1)\n.xx \"\" \"pipe:\" \"create an interprocess communication channel.\" \"\" pipe(2)\n.xx \"\" \"badsect:\" \"create files to contain bad sectors.\" \"\" badsect(8)\n.xx \"\" \"addbib:\" \"create or extend bibliographic database.\" \"\" addbib(1)\n.xx \"\" \"catman:\" \"create the cat files for the manual.\" \"\" catman(8)\n.xx \"\" \"umask: change or display file\" \"creation mask.\" \"\" csh(1)\n.xx \"\" \"umask: set file\" \"creation mode mask.\" \"\" umask(2)\n.xx \"\" \"cribbage: the card game\" \"cribbage.\" \"\" cribbage(6)\n.xx \"\" \"\" \"cribbage: the card game cribbage.\" \"\" cribbage(6)\n.xx \"\" \"\" \"crl: VAX 8600 console RL02 interface.\" \"\" crl(4)\n.xx \"\" \"\" \"cron: clock daemon.\" \"\" cron(8)\n.xx \"\" \"lxref: lisp\" \"cross reference program.\" \"\" lxref(1)\n.xx \"\" \"pxref: Pascal\" \"cross-reference program.\" \"\" pxref(1)\n.xx \"\" \"systat: display system statistics on a\" \"crt.\" \"\" systat(1)\n.xx \"\" \"colcrt: filter nroff output for\" \"CRT previewing.\" \"\" colcrt(1)\n.xx \"\" \"more, page: file perusal filter for\" \"crt viewing.\" \"\" more(1)\n.xx \"\" \"\" \"crypt: encode/decode.\" \"\" crypt(1)\n.xx \"\" \"\" \"crypt, setkey, encrypt: DES encryption.\" \"\" crypt(3)\n.xx \"syntax.\" \"\" \"csh: a shell (command interpreter) with C-like\" \"\" csh(1)\n.xx \"\" \"\" \"css: DEC IMP-11A LH/DH IMP interface.\" \"\" css(4)\n.xx \"\" \"pcl: DEC\" \"CSS PCL-11 B Network Interface.\" \"\" pcl(4)\n.xx \"\" \"\" \"ct: phototypesetter interface.\" \"\" ct(4)\n.xx \"\" \"\" \"ctags: create a tags file.\" \"\" ctags(1)\n.xx \"convert date and time to ASCII.\" \"\" \"ctime, localtime, gmtime, asctime, timezone:\" \"\" ctime(3)\n.xx \"\" \"time,\" \"ctime, ltime, gmtime: return system time.\" \"\" time(3F)\n.xx \"\" \"tip,\" \"cu: connect to a remote system.\" \"\" tip(1C)\n.xx \"\" \"cbrt, sqrt:\" \"cube root, square root.\" \"\" sqrt(3M)\n.xx \"\" \"vhangup: virtually ``hangup'' the\" \"current control terminal.\" \"\" vhangup(2)\n.xx \"\" \"gethostid, sethostid: get/set unique identifier of\" \"current host.\" \"\" gethostid(2)\n.xx \"\" \"gethostname, sethostname: get/set name of\" \"current host.\" \"\" gethostname(2)\n.xx \"\" \"hostnm: get name of\" \"current host.\" \"\" hostnm(3F)\n.xx \"\" \"hostid: set or print identifier of\" \"current host system.\" \"\" hostid(1)\n.xx \"\" \"hostname: set or print name of\" \"current host system.\" \"\" hostname(1)\n.xx \"\" \"jobs: print\" \"current job list.\" \"\" csh(1)\n.xx \"\" \"sigsetmask: set\" \"current signal mask.\" \"\" sigsetmask(2)\n.xx \"\" \"whoami: print effective\" \"current user id.\" \"\" whoami(1)\n.xx \"\" \"chdir: change\" \"current working directory.\" \"\" chdir(2)\n.xx \"\" \"getcwd: get pathname of\" \"current working directory.\" \"\" getcwd(3F)\n.xx \"\" \"getwd: get\" \"current working directory pathname.\" \"\" getwd(3)\n.xx \"motion.\" \"\" \"curses: screen functions with ``optimal'' cursor\" \"\" curses(3X)\n.xx \"\" \"curses: screen functions with ``optimal''\" \"cursor motion.\" \"\" curses(3X)\n.xx \"\" \"spline: interpolate smooth\" \"curve.\" \"\" spline(1G)\n.xx \"\" \"continue:\" \"cycle in loop.\" \"\" csh(1)\n.xx \"\" \"cron: clock\" \"daemon.\" \"\" cron(8)\n.xx \"\" \"lpd: line printer\" \"daemon.\" \"\" lpd(8)\n.xx \"\" \"routed: network routing\" \"daemon.\" \"\" routed(8C)\n.xx \"\" \"timed: time server\" \"daemon.\" \"\" timed(8)\n.xx \"\" \"XNSrouted: NS Routing Information Protocol\" \"daemon.\" \"\" XNSrouted(8C)\n.xx \"\" \"rc: command script for auto-reboot and\" \"daemons.\" \"\" rc(8)\n.xx \"\" \"ftpd:\" \"DARPA Internet File Transfer Protocol server.\" \"\" ftpd(8C)\n.xx \"\" \"whois:\" \"DARPA Internet user name directory service.\" \"\" whois(1)\n.xx \"\" \"telnetd:\" \"DARPA TELNET protocol server.\" \"\" telnetd(8C)\n.xx \"\" \"tftpd:\" \"DARPA Trivial File Transfer Protocol server.\" \"\" tftpd(8C)\n.xx \"\" \"compress, uncompress, zcat: compress and expand\" \"data.\" \"\" compress(1)\n.xx \"\" \"eval: re-evaluate shell\" \"data.\" \"\" csh(1)\n.xx \"\" \"gprof: display call graph profile\" \"data.\" \"\" gprof(1)\n.xx \"\" \"prof: display profile\" \"data.\" \"\" prof(1)\n.xx \"\" \"ttys: terminal initialization\" \"data.\" \"\" ttys(5)\n.xx \"\" \"gettytab: terminal configuration\" \"data base.\" \"\" gettytab(5)\n.xx \"\" \"hosts: host name\" \"data base.\" \"\" hosts(5)\n.xx \"\" \"networks: network name\" \"data base.\" \"\" networks(5)\n.xx \"\" \"phones: remote host phone number\" \"data base.\" \"\" phones(5)\n.xx \"\" \"printcap: printer capability\" \"data base.\" \"\" printcap(5)\n.xx \"\" \"protocols: protocol name\" \"data base.\" \"\" protocols(5)\n.xx \"\" \"services: service name\" \"data base.\" \"\" services(5)\n.xx \"\" \"termcap: terminal capability\" \"data base.\" \"\" termcap(5)\n.xx \"\" \"vgrindefs: vgrind's language definition\" \"data base.\" \"\" vgrindefs(5)\n.xx \"\" \"newaliases: rebuild the\" \"data base for the mail aliases file.\" \"\" newaliases(1)\n.xx \"\" \"dbminit, fetch, store, delete, firstkey, nextkey:\" \"data base subroutines.\" \"\" dbm(3X)\n.xx \"\" \"dbm_firstkey, dbm_nextkey, dbm_error, dbm_clearerr:\" \"data base subroutines.\" \"/dbm_store, dbm_delete,\" ndbm(3)\n.xx \"\" \"brk, sbrk: change\" \"data segment size.\" \"\" brk(2)\n.xx \"\" \"null:\" \"data sink.\" \"\" null(4)\n.xx \"\" \"ad:\" \"Data Translation A/D converter.\" \"\" ad(4)\n.xx \"\" \"types: primitive system\" \"data types.\" \"\" types(5)\n.xx \"\" \"addbib: create or extend bibliographic\" \"database.\" \"\" addbib(1)\n.xx \"\" \"roffbib: run off bibliographic\" \"database.\" \"\" roffbib(1)\n.xx \"\" \"sortbib: sort bibliographic\" \"database.\" \"\" sortbib(1)\n.xx \"keys.\" \"map3270:\" \"database for mapping ascii keystrokes into IBM 3270\" \"\" map3270(5)\n.xx \"\" \"join: relational\" \"database operator.\" \"\" join(1)\n.xx \"\" \"idp: Xerox Internet\" \"Datagram Protocol.\" \"\" idp(4P)\n.xx \"\" \"udp: Internet User\" \"Datagram Protocol.\" \"\" udp(4P)\n.xx \"\" \"date: print and set the\" \"date.\" \"\" date(1)\n.xx \"\" \"gettimeofday, settimeofday: get/set\" \"date and time.\" \"\" gettimeofday(2)\n.xx \"\" \"time, ftime: get\" \"date and time.\" \"\" time(3C)\n.xx \"\" \"fdate: return\" \"date and time in an ASCII string.\" \"\" fdate(3F)\n.xx \"\" \"localtime, gmtime, asctime, timezone: convert\" \"date and time to ASCII.\" \"ctime,\" ctime(3)\n.xx \"\" \"touch: update\" \"date last modified of a file.\" \"\" touch(1)\n.xx \"\" \"idate, itime: return\" \"date or time in numerical form.\" \"\" idate(3F)\n.xx \"\" \"\" \"date: print and set the date.\" \"\" date(1)\n.xx \"\" \"dbm_delete, dbm_firstkey, dbm_nextkey, dbm_error,\" \"dbm_clearerr: data base subroutines.\" \"/dbm_store,\" ndbm(3)\n.xx \"dbm_firstkey, dbm_nextkey, dbm_error,/\" \"dbm_open,\" \"dbm_close, dbm_fetch, dbm_store, dbm_delete,\" \"\" ndbm(3)\n.xx \"\" \"dbm_open, dbm_close, dbm_fetch, dbm_store,\" \"dbm_delete, dbm_firstkey, dbm_nextkey, dbm_error,/\" \"\" ndbm(3)\n.xx \"\" \"/dbm_store, dbm_delete, dbm_firstkey, dbm_nextkey,\" \"dbm_error, dbm_clearerr: data base subroutines.\" \"\" ndbm(3)\n.xx \"dbm_nextkey, dbm_error,/\" \"dbm_open, dbm_close,\" \"dbm_fetch, dbm_store, dbm_delete, dbm_firstkey,\" \"\" ndbm(3)\n.xx \"data/\" \"/dbm_close, dbm_fetch, dbm_store, dbm_delete,\" \"dbm_firstkey, dbm_nextkey, dbm_error, dbm_clearerr:\" \"\" ndbm(3)\n.xx \"data base subroutines.\" \"\" \"dbminit, fetch, store, delete, firstkey, nextkey:\" \"\" dbm(3X)\n.xx \"\" \"/dbm_fetch, dbm_store, dbm_delete, dbm_firstkey,\" \"dbm_nextkey, dbm_error, dbm_clearerr: data base/\" \"\" ndbm(3)\n.xx \"dbm_delete, dbm_firstkey, dbm_nextkey, dbm_error,/\" \"\" \"dbm_open, dbm_close, dbm_fetch, dbm_store,\" \"\" ndbm(3)\n.xx \"dbm_error,/\" \"dbm_open, dbm_close, dbm_fetch,\" \"dbm_store, dbm_delete, dbm_firstkey, dbm_nextkey,\" \"\" ndbm(3)\n.xx \"\" \"\" \"dbx: dbx symbol table information.\" \"\" dbx(5)\n.xx \"\" \"\" \"dbx: debugger.\" \"\" dbx(1)\n.xx \"\" \"dbx:\" \"dbx symbol table information.\" \"\" dbx(5)\n.xx \"\" \"\" \"dc: desk calculator.\" \"\" dc(1)\n.xx \"\" \"\" \"dcheck: file system directory consistency check.\" \"\" dcheck(8)\n.xx \"\" \"\" \"dd: convert and copy a file.\" \"\" dd(1)\n.xx \"\" \"\" \"ddn: DDN Standard Mode X.25 IMP interface.\" \"\" ddn(4)\n.xx \"\" \"ddn:\" \"DDN Standard Mode X.25 IMP interface.\" \"\" ddn(4)\n.xx \"\" \"\" \"de: DEC DEUNA 10 Mb/s Ethernet interface.\" \"\" de(4)\n.xx \"\" \"adb:\" \"debugger.\" \"\" adb(1)\n.xx \"\" \"dbx:\" \"debugger.\" \"\" dbx(1)\n.xx \"\" \"pdx: pascal\" \"debugger.\" \"\" pdx(1)\n.xx \"\" \"pcl:\" \"DEC CSS PCL-11 B Network Interface.\" \"\" pcl(4)\n.xx \"\" \"qe:\" \"DEC DEQNA Q-bus 10 Mb/s Ethernet interface.\" \"\" qe(4)\n.xx \"\" \"de:\" \"DEC DEUNA 10 Mb/s Ethernet interface.\" \"\" de(4)\n.xx \"device.\" \"dmc:\" \"DEC DMC-11/DMR-11 point-to-point communications\" \"\" dmc(4)\n.xx \"\" \"css:\" \"DEC IMP-11A LH/DH IMP interface.\" \"\" css(4)\n.xx \"\" \"rx:\" \"DEC RX02 floppy disk interface.\" \"\" rx(4)\n.xx \"\" \"bad144: read/write\" \"dec standard 144 bad sector information.\" \"\" bad144(8)\n.xx \"\" \"tmscp:\" \"DEC TMSCP magtape interface.\" \"\" tmscp(4)\n.xx \"\" \"od: octal,\" \"decimal, hex, ascii dump.\" \"\" od(1)\n.xx \"\" \"tp:\" \"DEC/mag tape formats.\" \"\" tp(5)\n.xx \"\" \"\" \"default: catchall clause in switch.\" \"\" csh(1)\n.xx \"\" \"chdir: change\" \"default directory.\" \"\" chdir(3F)\n.xx \"\" \"diskpart: calculate\" \"default disk partition sizes.\" \"\" diskpart(8)\n.xx \"\" \"vgrindefs: vgrind's language\" \"definition data base.\" \"\" vgrindefs(5)\n.xx \"\" \"eqnchar: special character\" \"definitions for eqn.\" \"\" eqnchar(7)\n.xx \"\" \"stty, gtty: set and get terminal state\" \"(defunct).\" \"\" stty(3C)\n.xx \"\" \"close:\" \"delete a descriptor.\" \"\" close(2)\n.xx \"\" \"dbminit, fetch, store,\" \"delete, firstkey, nextkey: data base subroutines.\" \"\" dbm(3X)\n.xx \"\" \"tail:\" \"deliver the last part of a file.\" \"\" tail(1)\n.xx \"\" \"mesg: permit or\" \"deny messages.\" \"\" mesg(1)\n.xx \"\" \"tset: terminal\" \"dependent initialization.\" \"\" tset(1)\n.xx \"\" \"qe: DEC\" \"DEQNA Q-bus 10 Mb/s Ethernet interface.\" \"\" qe(4)\n.xx \"constructs.\" \"\" \"deroff: remove nroff, troff, tbl and eqn\" \"\" deroff(1)\n.xx \"\" \"crypt, setkey, encrypt:\" \"DES encryption.\" \"\" crypt(3)\n.xx \"\" \"whatis:\" \"describe what a command is.\" \"\" whatis(1)\n.xx \"\" \"mailaddr: mail addressing\" \"description.\" \"\" mailaddr(7)\n.xx \"\" \"getdiskbyname: get disk\" \"description by its name.\" \"\" getdisk(3)\n.xx \"\" \"disktab: disk\" \"description file.\" \"\" disktab(5)\n.xx \"\" \"L-devices: UUCP device\" \"description file.\" \"\" L-devices(5)\n.xx \"\" \"L.sys: UUCP remote host\" \"description file.\" \"\" L.sys(5)\n.xx \"\" \"remote: remote host\" \"description file.\" \"\" remote(5)\n.xx \"\" \"close: delete a\" \"descriptor.\" \"\" close(2)\n.xx \"\" \"dup, dup2: duplicate a\" \"descriptor.\" \"\" dup(2)\n.xx \"\" \"getfstype, setfsent, endfsent: get file system\" \"descriptor file entry.\" \"/getfsspec, getfsfile,\" getfsent(3)\n.xx \"\" \"getdtablesize: get\" \"descriptor table size.\" \"\" getdtablesize(2)\n.xx \"\" \"dc:\" \"desk calculator.\" \"\" dc(1)\n.xx \"\" \"access:\" \"determine accessability of a file.\" \"\" access(3F)\n.xx \"\" \"access:\" \"determine accessibility of file.\" \"\" access(2)\n.xx \"\" \"file:\" \"determine file type.\" \"\" file(1)\n.xx \"\" \"de: DEC\" \"DEUNA 10 Mb/s Ethernet interface.\" \"\" de(4)\n.xx \"\" \"DEC DMC-11/DMR-11 point-to-point communications\" \"device.\" \"dmc:\" dmc(4)\n.xx \"\" \"drum: paging\" \"device.\" \"\" drum(4)\n.xx \"\" \"fold: fold long lines for finite width output\" \"device.\" \"\" fold(1)\n.xx \"\" \"ioctl: control\" \"device.\" \"\" ioctl(2)\n.xx \"\" \"L-devices: UUCP\" \"device description file.\" \"\" L-devices(5)\n.xx \"\" \"swapon: add a swap\" \"device for interleaved paging/swapping.\" \"\" swapon(2)\n.xx \"\" \"swapon: specify additional\" \"device for paging and swapping.\" \"\" swapon(8)\n.xx \"\" \"ik: Ikonas frame buffer, graphics\" \"device interface.\" \"\" ik(4)\n.xx \"\" \"ps: Evans and Sutherland Picture System 2 graphics\" \"device interface.\" \"\" ps(4)\n.xx \"\" \"tb: line discipline for digitizing\" \"devices.\" \"\" tb(4)\n.xx \"\" \"\" \"df: disk free.\" \"\" df(1)\n.xx \"\" \"flmin, flmax, ffrac, dflmin, dflmax,\" \"dffrac, inmax: return extreme values.\" \"\" flmin(3F)\n.xx \"\" \"flmin, flmax, ffrac, dflmin,\" \"dflmax, dffrac, inmax: return extreme values.\" \"\" flmin(3F)\n.xx \"values.\" \"flmin, flmax, ffrac,\" \"dflmin, dflmax, dffrac, inmax: return extreme\" \"\" flmin(3F)\n.xx \"\" \"\" \"dh: DH-11/DM-11 communications multiplexer.\" \"\" dh(4)\n.xx \"\" \"dh:\" \"DH-11/DM-11 communications multiplexer.\" \"\" dh(4)\n.xx \"\" \"\" \"dhu: DHU-11 communications multiplexer.\" \"\" dhu(4)\n.xx \"\" \"dhu:\" \"DHU-11 communications multiplexer.\" \"\" dhu(4)\n.xx \"\" \"dmesg: collect system\" \"diagnostic messages to form error log.\" \"\" dmesg(8)\n.xx \"\" \"autoconf:\" \"diagnostics from the autoconfiguration code.\" \"\" autoconf(4)\n.xx \"\" \"explain: print wordy sentences; thesaurus for\" \"diction.\" \"diction,\" diction(1)\n.xx \"for diction.\" \"\" \"diction, explain: print wordy sentences; thesaurus\" \"\" diction(1)\n.xx \"\" \"\" \"diff: differential file and directory comparator.\" \"\" diff(1)\n.xx \"\" \"patch: a program for applying a\" \"diff file to an original.\" \"\" patch(1)\n.xx \"\" \"\" \"diff3: 3-way differential file comparison.\" \"\" diff3(1)\n.xx \"\" \"diff:\" \"differential file and directory comparator.\" \"\" diff(1)\n.xx \"\" \"diff3: 3-way\" \"differential file comparison.\" \"\" diff3(1)\n.xx \"\" \"tb: line discipline for\" \"digitizing devices.\" \"\" tb(4)\n.xx \"\" \"\" \"dir: format of directories.\" \"\" dir(5)\n.xx \"\" \"dir: format of\" \"directories.\" \"\" dir(5)\n.xx \"\" \"rm, rmdir: remove (unlink) files or\" \"directories.\" \"\" rm(1)\n.xx \"\" \"sticky: persistent text and append-only\" \"directories.\" \"\" sticky(8)\n.xx \"\" \"rmdir, rm: remove (unlink)\" \"directories or files.\" \"\" rmdir(1)\n.xx \"\" \"cd: change working\" \"directory.\" \"\" cd(1)\n.xx \"\" \"chdir: change current working\" \"directory.\" \"\" chdir(2)\n.xx \"\" \"chdir: change default\" \"directory.\" \"\" chdir(3F)\n.xx \"\" \"chroot: change root\" \"directory.\" \"\" chroot(2)\n.xx \"\" \"cd: change\" \"directory.\" \"\" csh(1)\n.xx \"\" \"chdir: change\" \"directory.\" \"\" csh(1)\n.xx \"\" \"getcwd: get pathname of current working\" \"directory.\" \"\" getcwd(3F)\n.xx \"\" \"ls: list contents of\" \"directory.\" \"\" ls(1)\n.xx \"\" \"mkdir: make a\" \"directory.\" \"\" mkdir(1)\n.xx \"\" \"scandir, alphasort: scan a\" \"directory.\" \"\" scandir(3)\n.xx \"\" \"uuclean: uucp spool\" \"directory clean-up.\" \"\" uuclean(8C)\n.xx \"\" \"diff: differential file and\" \"directory comparator.\" \"\" diff(1)\n.xx \"\" \"dcheck: file system\" \"directory consistency check.\" \"\" dcheck(8)\n.xx \"\" \"unlink: remove\" \"directory entry.\" \"\" unlink(2)\n.xx \"\" \"unlink: remove a\" \"directory entry.\" \"\" unlink(3F)\n.xx \"\" \"mkdir: make a\" \"directory file.\" \"\" mkdir(2)\n.xx \"\" \"rmdir: remove a\" \"directory file.\" \"\" rmdir(2)\n.xx \"\" \"mklost+found: make a lost+found\" \"directory for fsck.\" \"\" mklost+found(8)\n.xx \"\" \"pwd: working\" \"directory name.\" \"\" pwd(1)\n.xx \"\" \"readdir, telldir, seekdir, rewinddir, closedir:\" \"directory operations.\" \"opendir,\" directory(3)\n.xx \"\" \"getwd: get current working\" \"directory pathname.\" \"\" getwd(3)\n.xx \"\" \"whois: DARPA Internet user name\" \"directory service.\" \"\" whois(1)\n.xx \"\" \"popd: pop shell\" \"directory stack.\" \"\" csh(1)\n.xx \"\" \"pushd: push shell\" \"directory stack.\" \"\" csh(1)\n.xx \"\" \"quota: display\" \"disc usage and limits.\" \"\" quota(1)\n.xx \"\" \"unhash:\" \"discard command hash table.\" \"\" csh(1)\n.xx \"\" \"unset:\" \"discard shell variables.\" \"\" csh(1)\n.xx \"\" \"tb: line\" \"discipline for digitizing devices.\" \"\" tb(4)\n.xx \"(obsolete).\" \"bk: line\" \"discipline for machine-machine communication\" \"\" bk(4)\n.xx \"\" \"synchronize a file's in-core state with that on\" \"disk.\" \"fsync:\" fsync(2)\n.xx \"\" \"hk: RK6-11/RK06 and RK07 moving head\" \"disk.\" \"\" hk(4)\n.xx \"\" \"uda: UDA-50\" \"disk controller interface.\" \"\" uda(4)\n.xx \"\" \"getdiskbyname: get\" \"disk description by its name.\" \"\" getdisk(3)\n.xx \"\" \"disktab:\" \"disk description file.\" \"\" disktab(5)\n.xx \"\" \"df:\" \"disk free.\" \"\" df(1)\n.xx \"\" \"hp: MASSBUS\" \"disk interface.\" \"\" hp(4)\n.xx \"\" \"rx: DEC RX02 floppy\" \"disk interface.\" \"\" rx(4)\n.xx \"\" \"format: how to format\" \"disk packs.\" \"\" format(8V)\n.xx \"\" \"diskpart: calculate default\" \"disk partition sizes.\" \"\" diskpart(8)\n.xx \"\" \"quota: manipulate\" \"disk quotas.\" \"\" quota(2)\n.xx \"\" \"drtest: standalone\" \"disk test program.\" \"\" drtest(8)\n.xx \"\" \"du: summarize\" \"disk usage.\" \"\" du(1)\n.xx \"\" \"\" \"diskpart: calculate default disk partition sizes.\" \"\" diskpart(8)\n.xx \"\" \"reboot/halt the system without checking the\" \"disks.\" \"fastboot, fasthalt:\" fastboot(8)\n.xx \"\" \"rxformat: format floppy\" \"disks.\" \"\" rxformat(8V)\n.xx \"\" \"\" \"disktab: disk description file.\" \"\" disktab(5)\n.xx \"\" \"mount, umount: mount and\" \"dismount file system.\" \"\" mount(8)\n.xx \"\" \"error: analyze and\" \"disperse compiler error messages.\" \"\" error(1)\n.xx \"\" \"rain: animated raindrops\" \"display.\" \"\" rain(6)\n.xx \"\" \"arp: address resolution\" \"display and control.\" \"\" arp(8C)\n.xx \"\" \"gprof:\" \"display call graph profile data.\" \"\" gprof(1)\n.xx \"\" \"snake, snscore:\" \"display chase game.\" \"\" snake(6)\n.xx \"\" \"quota:\" \"display disc usage and limits.\" \"\" quota(1)\n.xx \"\" \"vi: screen oriented (visual)\" \"display editor based on ex.\" \"\" vi(1)\n.xx \"\" \"umask: change or\" \"display file creation mask.\" \"\" csh(1)\n.xx \"\" \"prof:\" \"display profile data.\" \"\" prof(1)\n.xx \"\" \"systat:\" \"display system statistics on a crt.\" \"\" systat(1)\n.xx \"\" \"sysline:\" \"display system status on status line of a terminal.\" \"\" sysline(1)\n.xx \"\" \"worms: animate worms on a\" \"display terminal.\" \"\" worms(6)\n.xx \"\" \"uulog:\" \"display UUCP log files.\" \"\" uulog(1C)\n.xx \"\" \"jove: an interactive\" \"display-oriented text editor.\" \"\" jove(1)\n.xx \"\" \"hypot, cabs: Euclidean\" \"distance, complex absolute value.\" \"\" hypot(3M)\n.xx \"\" \"rdist: remote file\" \"distribution program.\" \"\" rdist(1)\n.xx \"communications device.\" \"\" \"dmc: DEC DMC-11/DMR-11 point-to-point\" \"\" dmc(4)\n.xx \"\" \"dmc: DEC\" \"DMC-11/DMR-11 point-to-point communications device.\" \"\" dmc(4)\n.xx \"error log.\" \"\" \"dmesg: collect system diagnostic messages to form\" \"\" dmesg(8)\n.xx \"\" \"\" \"dmf: DMF-32, terminal multiplexor.\" \"\" dmf(4)\n.xx \"\" \"dmf:\" \"DMF-32, terminal multiplexor.\" \"\" dmf(4)\n.xx \"\" \"\" \"dmz: DMZ-32 terminal multiplexor.\" \"\" dmz(4)\n.xx \"\" \"dmz:\" \"DMZ-32 terminal multiplexor.\" \"\" dmz(4)\n.xx \"\" \"\" \"dn: DN-11 autocall unit interface.\" \"\" dn(4)\n.xx \"\" \"dn:\" \"DN-11 autocall unit interface.\" \"\" dn(4)\n.xx \"\" \"res_mkquery, res_send, res_init,\" \"dn_comp, dn_expand: resolver routines.\" \"\" resolver(3)\n.xx \"\" \"res_mkquery, res_send, res_init, dn_comp,\" \"dn_expand: resolver routines.\" \"\" resolver(3)\n.xx \"\" \"\" \"doctor: interact with a psychoanalyst.\" \"\" doctor(6)\n.xx \"\" \"style: analyze surface characteristics of a\" \"document.\" \"\" style(1)\n.xx \"\" \"refer: find and insert literature references in\" \"documents.\" \"\" refer(1)\n.xx \"\" \"w: who is on and what they are\" \"doing.\" \"\" w(1)\n.xx \"\" \"named: Internet\" \"domain name server.\" \"\" named(8)\n.xx \"\" \"rogue: Exploring The Dungeons of\" \"Doom.\" \"\" rogue(6)\n.xx \"\" \"shutdown: shut\" \"down part of a full-duplex connection.\" \"\" shutdown(2)\n.xx \"\" \"shutdown: close\" \"down the system at a given time.\" \"\" shutdown(8)\n.xx \"\" \"rand,\" \"drand, irand: return random values.\" \"\" rand(3F)\n.xx \"\" \"random,\" \"drandm, irandm: better random number generator.\" \"\" random(3F)\n.xx \"\" \"graph:\" \"draw a graph.\" \"\" graph(1G)\n.xx \"exponent manipulations.\" \"copysign,\" \"drem, finite, logb, scalb: copysign, remainder,\" \"\" ieee(3M)\n.xx \"\" \"arithmetic: provide\" \"drill in number facts.\" \"\" arithmetic(6)\n.xx \"\" \"ut: UNIBUS TU45 tri-density tape\" \"drive interface.\" \"\" ut(4)\n.xx \"\" \"pty: pseudo terminal\" \"driver.\" \"\" pty(4)\n.xx \"\" \"\" \"drtest: standalone disk test program.\" \"\" drtest(8)\n.xx \"\" \"\" \"drum: paging device.\" \"\" drum(4)\n.xx \"\" \"etime,\" \"dtime: return elapsed execution time.\" \"\" etime(3F)\n.xx \"\" \"\" \"du: summarize disk usage.\" \"\" du(1)\n.xx \"\" \"dump: incremental file system\" \"dump.\" \"\" dump(8)\n.xx \"\" \"od: octal, decimal, hex, ascii\" \"dump.\" \"\" od(1)\n.xx \"\" \"rdump: file system\" \"dump across the network.\" \"\" rdump(8C)\n.xx \"\" \"rrestore: restore a file system\" \"dump across the network.\" \"\" rrestore(8C)\n.xx \"\" \"\" \"dump, dumpdates: incremental dump format.\" \"\" dump(5)\n.xx \"\" \"dumpfs:\" \"dump file system information.\" \"\" dumpfs(8)\n.xx \"\" \"dump, dumpdates: incremental\" \"dump format.\" \"\" dump(5)\n.xx \"\" \"\" \"dump: incremental file system dump.\" \"\" dump(8)\n.xx \"\" \"savecore: save a core\" \"dump of the operating system.\" \"\" savecore(8)\n.xx \"\" \"kgmon: generate a\" \"dump of the operating system's profile buffers.\" \"\" kgmon(8)\n.xx \"\" \"dump,\" \"dumpdates: incremental dump format.\" \"\" dump(5)\n.xx \"\" \"\" \"dumpfs: dump file system information.\" \"\" dumpfs(8)\n.xx \"\" \"zork: the game of\" \"dungeon.\" \"\" zork(6)\n.xx \"\" \"rogue: Exploring The\" \"Dungeons of Doom.\" \"\" rogue(6)\n.xx \"\" \"\" \"dup, dup2: duplicate a descriptor.\" \"\" dup(2)\n.xx \"\" \"dup,\" \"dup2: duplicate a descriptor.\" \"\" dup(2)\n.xx \"\" \"dup, dup2:\" \"duplicate a descriptor.\" \"\" dup(2)\n.xx \"\" \"\" \"dz: DZ-11 communications multiplexer.\" \"\" dz(4)\n.xx \"\" \"dz:\" \"DZ-11 communications multiplexer.\" \"\" dz(4)\n.xx \"\" \"\" \"ec: 3Com 10 Mb/s Ethernet interface.\" \"\" ec(4)\n.xx \"\" \"echo:\" \"echo arguments.\" \"\" csh(1)\n.xx \"\" \"echo:\" \"echo arguments.\" \"\" echo(1)\n.xx \"\" \"\" \"echo: echo arguments.\" \"\" csh(1)\n.xx \"\" \"\" \"echo: echo arguments.\" \"\" echo(1)\n.xx \"\" \"ping: send ICMP\" \"ECHO_REQUEST packets to network hosts.\" \"\" ping(8)\n.xx \"\" \"\" \"ecvt, fcvt, gcvt: output conversion.\" \"\" ecvt(3)\n.xx \"\" \"\" \"ed: text editor.\" \"\" ed(1)\n.xx \"\" \"end, etext,\" \"edata: last locations in program.\" \"\" end(3)\n.xx \"\" \"ex,\" \"edit: text editor.\" \"\" ex(1)\n.xx \"\" \"vipw:\" \"edit the password file.\" \"\" vipw(8)\n.xx \"\" \"edquota:\" \"edit user quotas.\" \"\" edquota(8)\n.xx \"\" \"ed: text\" \"editor.\" \"\" ed(1)\n.xx \"\" \"ex, edit: text\" \"editor.\" \"\" ex(1)\n.xx \"\" \"jove: an interactive display-oriented text\" \"editor.\" \"\" jove(1)\n.xx \"\" \"ld: link\" \"editor.\" \"\" ld(1)\n.xx \"\" \"sed: stream\" \"editor.\" \"\" sed(1)\n.xx \"\" \"vi: screen oriented (visual) display\" \"editor based on ex.\" \"\" vi(1)\n.xx \"\" \"a.out: assembler and link\" \"editor output.\" \"\" a.out(5)\n.xx \"\" \"\" \"edquota: edit user quotas.\" \"\" edquota(8)\n.xx \"\" \"whoami: print\" \"effective current user id.\" \"\" whoami(1)\n.xx \"\" \"setregid: set real and\" \"effective group ID.\" \"\" setregid(2)\n.xx \"\" \"setreuid: set real and\" \"effective user ID's.\" \"\" setreuid(2)\n.xx \"\" \"vfork: spawn new process in a virtual memory\" \"efficient way.\" \"\" vfork(2)\n.xx \"\" \"\" \"efl: Extended Fortran Language.\" \"\" efl(1)\n.xx \"\" \"grep,\" \"egrep, fgrep: search a file for a pattern.\" \"\" grep(1)\n.xx \"\" \"etime, dtime: return\" \"elapsed execution time.\" \"\" etime(3F)\n.xx \"\" \"insque, remque: insert/remove\" \"element from a queue.\" \"\" insque(3)\n.xx \"\" \"soelim:\" \"eliminate \\&.so's from nroff input.\" \"\" soelim(1)\n.xx \"\" \"\" \"else: alternative commands.\" \"\" csh(1)\n.xx \"\" \"\" \"en: Xerox 3 Mb/s Ethernet interface.\" \"\" en(4)\n.xx \"\" \"setquota:\" \"enable/disable quotas on a file system.\" \"\" setquota(2)\n.xx \"\" \"nsip: software network interface\" \"encapsulating ns packets in ip packets..\" \"\" nsip(4)\n.xx \"\" \"uuencode: format of an\" \"encoded uuencode file.\" \"\" uuencode(5)\n.xx \"\" \"crypt:\" \"encode/decode.\" \"\" crypt(1)\n.xx \"mail.\" \"uuencode, uudecode:\" \"encode/decode a binary file for transmission via\" \"\" uuencode(1C)\n.xx \"\" \"crypt, setkey,\" \"encrypt: DES encryption.\" \"\" crypt(3)\n.xx \"\" \"crypt, setkey, encrypt: DES\" \"encryption.\" \"\" crypt(3)\n.xx \"\" \"makekey: generate\" \"encryption key.\" \"\" makekey(8)\n.xx \"\" \"\" \"end, etext, edata: last locations in program.\" \"\" end(3)\n.xx \"\" \"sccs: front\" \"end for the SCCS subsystem.\" \"\" sccs(1)\n.xx \"\" \"logout:\" \"end session.\" \"\" csh(1)\n.xx \"\" \"\" \"end: terminate loop.\" \"\" csh(1)\n.xx \"\" \"/getfsspec, getfsfile, getfstype, setfsent,\" \"endfsent: get file system descriptor file entry.\" \"\" getfsent(3)\n.xx \"\" \"getgrent, getgrgid, getgrnam, setgrent,\" \"endgrent: get group file entry.\" \"\" getgrent(3)\n.xx \"\" \"gethostbyaddr, gethostent, sethostent,\" \"endhostent: get network host entry.\" \"gethostbyname,\" gethostbyname(3N)\n.xx \"\" \"\" \"endif: terminate conditional.\" \"\" csh(1)\n.xx \"\" \"getnetent, getnetbyaddr, getnetbyname, setnetent,\" \"endnetent: get network entry.\" \"\" getnetent(3N)\n.xx \"\" \"socket: create an\" \"endpoint for communication.\" \"\" socket(2)\n.xx \"\" \"getprotobynumber, getprotobyname, setprotoent,\" \"endprotoent: get protocol entry.\" \"getprotoent,\" getprotoent(3N)\n.xx \"\" \"getpwent, getpwuid, getpwnam, setpwent,\" \"endpwent, setpwfile: get password file entry.\" \"\" getpwent(3)\n.xx \"\" \"getservbyport, getservbyname, setservent,\" \"endservent: get service entry.\" \"getservent,\" getservent(3N)\n.xx \"\" \"\" \"endsw: terminate switch.\" \"\" csh(1)\n.xx \"\" \"getttyent, getttynam, setttyent,\" \"endttyent: get ttys file entry.\" \"\" getttyent(3)\n.xx \"\" \"getusershell, setusershell,\" \"endusershell: get legal user shells.\" \"\" getusershell(3)\n.xx \"\" \"number: convert Arabic numerals to\" \"English.\" \"\" number(6)\n.xx \"\" \"xsend, xget,\" \"enroll: secret mail.\" \"\" xsend(1)\n.xx \"\" \"nlist: get\" \"entries from name list.\" \"\" nlist(3)\n.xx \"\" \"logger: make\" \"entries in the system log.\" \"\" logger(1)\n.xx \"\" \"setfsent, endfsent: get file system descriptor file\" \"entry.\" \"getfsent, getfsspec, getfsfile, getfstype,\" getfsent(3)\n.xx \"\" \"getgrnam, setgrent, endgrent: get group file\" \"entry.\" \"getgrent, getgrgid,\" getgrent(3)\n.xx \"\" \"sethostent, endhostent: get network host\" \"entry.\" \"gethostbyname, gethostbyaddr, gethostent,\" gethostbyname(3N)\n.xx \"\" \"getnetbyname, setnetent, endnetent: get network\" \"entry.\" \"getnetent, getnetbyaddr,\" getnetent(3N)\n.xx \"\" \"setprotoent, endprotoent: get protocol\" \"entry.\" \"/getprotobynumber, getprotobyname,\" getprotoent(3N)\n.xx \"\" \"setpwent, endpwent, setpwfile: get password file\" \"entry.\" \"getpwent, getpwuid, getpwnam,\" getpwent(3)\n.xx \"\" \"getservbyname, setservent, endservent: get service\" \"entry.\" \"getservent, getservbyport,\" getservent(3N)\n.xx \"\" \"getttynam, setttyent, endttyent: get ttys file\" \"entry.\" \"getttyent,\" getttyent(3)\n.xx \"\" \"unlink: remove directory\" \"entry.\" \"\" unlink(2)\n.xx \"\" \"unlink: remove a directory\" \"entry.\" \"\" unlink(3F)\n.xx \"\" \"execv, execle, execlp, execvp, exec, execve, exect,\" \"environ: execute a file.\" \"execl,\" execl(3)\n.xx \"\" \"\" \"environ: user environment.\" \"\" environ(7)\n.xx \"\" \"setenv: set variable in\" \"environment.\" \"\" csh(1)\n.xx \"\" \"environ: user\" \"environment.\" \"\" environ(7)\n.xx \"\" \"printenv: print out the\" \"environment.\" \"\" printenv(1)\n.xx \"\" \"window: window\" \"environment.\" \"\" window(1)\n.xx \"\" \"getenv: value for\" \"environment name.\" \"\" getenv(3)\n.xx \"\" \"unsetenv: remove\" \"environment variables.\" \"\" csh(1)\n.xx \"\" \"getenv: get value of\" \"environment variables.\" \"\" getenv(3F)\n.xx \"\" \"eqnchar: special character definitions for\" \"eqn.\" \"\" eqnchar(7)\n.xx \"\" \"deroff: remove nroff, troff, tbl and\" \"eqn constructs.\" \"\" deroff(1)\n.xx \"\" \"\" \"eqn, neqn, checkeq: typeset mathematics.\" \"\" eqn(1)\n.xx \"\" \"\" \"eqnchar: special character definitions for eqn.\" \"\" eqnchar(7)\n.xx \"linemod, space, closepl: graphics/\" \"plot: openpl,\" \"erase, label, line, circle, arc, move, cont, point,\" \"\" plot(3X)\n.xx \"\" \"\" \"erf, erfc: error functions.\" \"\" erf(3M)\n.xx \"\" \"erf,\" \"erfc: error functions.\" \"\" erf(3M)\n.xx \"messages.\" \"\" \"error: analyze and disperse compiler error\" \"\" error(1)\n.xx \"\" \"erf, erfc:\" \"error functions.\" \"\" erf(3M)\n.xx \"\" \"dmesg: collect system diagnostic messages to form\" \"error log.\" \"\" dmesg(8)\n.xx \"\" \"mkstr: create an\" \"error message file by massaging C source.\" \"\" mkstr(1)\n.xx \"\" \"error: analyze and disperse compiler\" \"error messages.\" \"\" error(1)\n.xx \"\" \"perror, sys_errlist, sys_nerr: system\" \"error messages.\" \"\" perror(3)\n.xx \"\" \"perror, gerror, ierrno: get system\" \"error messages.\" \"\" perror(3F)\n.xx \"\" \"intro: introduction to system calls and\" \"error numbers.\" \"\" intro(2)\n.xx \"\" \"spell, spellin, spellout: find spelling\" \"errors.\" \"\" spell(1)\n.xx \"\" \"traper: trap arithmetic\" \"errors.\" \"\" traper(3F)\n.xx \"\" \"end,\" \"etext, edata: last locations in program.\" \"\" end(3)\n.xx \"\" \"de: DEC DEUNA 10 Mb/s\" \"Ethernet interface.\" \"\" de(4)\n.xx \"\" \"ec: 3Com 10 Mb/s\" \"Ethernet interface.\" \"\" ec(4)\n.xx \"\" \"en: Xerox 3 Mb/s\" \"Ethernet interface.\" \"\" en(4)\n.xx \"\" \"ex: Excelan 10 Mb/s\" \"Ethernet interface.\" \"\" ex(4)\n.xx \"\" \"il: Interlan NI1010 10 Mb/s\" \"Ethernet interface.\" \"\" il(4)\n.xx \"\" \"ix: Interlan Np100 10 Mb/s\" \"Ethernet interface.\" \"\" ix(4)\n.xx \"\" \"np: Interlan Np100 10 Mb/s\" \"Ethernet interface.\" \"\" np(4)\n.xx \"\" \"qe: DEC DEQNA Q-bus 10 Mb/s\" \"Ethernet interface.\" \"\" qe(4)\n.xx \"\" \"\" \"etime, dtime: return elapsed execution time.\" \"\" etime(3F)\n.xx \"\" \"hypot, cabs:\" \"Euclidean distance, complex absolute value.\" \"\" hypot(3M)\n.xx \"\" \"/if, while, \\fB:\\fP, \\fB.\\fP, break, continue, cd,\" \"eval, exec, exit, export, login, read, readonly,/\" \"\" sh(1)\n.xx \"\" \"\" \"eval: re-evaluate shell data.\" \"\" csh(1)\n.xx \"\" \"expr:\" \"evaluate arguments as an expression.\" \"\" expr(1)\n.xx \"device interface.\" \"ps:\" \"Evans and Sutherland Picture System 2 graphics\" \"\" ps(4)\n.xx \"\" \"history: print history\" \"event list.\" \"\" csh(1)\n.xx \"\" \"screen oriented (visual) display editor based on\" \"ex.\" \"vi:\" vi(1)\n.xx \"\" \"\" \"ex, edit: text editor.\" \"\" ex(1)\n.xx \"\" \"\" \"ex: Excelan 10 Mb/s Ethernet interface.\" \"\" ex(4)\n.xx \"\" \"lpq: spool queue\" \"examination program.\" \"\" lpq(1)\n.xx \"\" \"uuq:\" \"examine or manipulate the uucp queue.\" \"\" uuq(1C)\n.xx \"\" \"ex:\" \"Excelan 10 Mb/s Ethernet interface.\" \"\" ex(4)\n.xx \"\" \"execl, execv, execle, execlp, execvp,\" \"exec, execve, exect, environ: execute a file.\" \"\" execl(3)\n.xx \"\" \"/while, \\fB:\\fP, \\fB.\\fP, break, continue, cd, eval,\" \"exec, exit, export, login, read, readonly, set,/\" \"\" sh(1)\n.xx \"\" \"\" \"exec: overlay shell with specified command.\" \"\" csh(1)\n.xx \"exect, environ: execute a file.\" \"\" \"execl, execv, execle, execlp, execvp, exec, execve,\" \"\" execl(3)\n.xx \"environ: execute a file.\" \"execl, execv,\" \"execle, execlp, execvp, exec, execve, exect,\" \"\" execl(3)\n.xx \"execute a file.\" \"execl, execv, execle,\" \"execlp, execvp, exec, execve, exect, environ:\" \"\" execl(3)\n.xx \"\" \"execl, execv, execle, execlp, execvp, exec, execve,\" \"exect, environ: execute a file.\" \"\" execl(3)\n.xx \"\" \"execlp, execvp, exec, execve, exect, environ:\" \"execute a file.\" \"execl, execv, execle,\" execl(3)\n.xx \"\" \"execve:\" \"execute a file.\" \"\" execve(2)\n.xx \"\" \"alarm:\" \"execute a subroutine after a specified time.\" \"\" alarm(3F)\n.xx \"\" \"system:\" \"execute a UNIX command.\" \"\" system(3F)\n.xx \"\" \"repeat:\" \"execute command repeatedly.\" \"\" csh(1)\n.xx \"\" \"at:\" \"execute commands at a later time.\" \"\" at(1)\n.xx \"\" \"lastcomm: show last commands\" \"executed in reverse order.\" \"\" lastcomm(1)\n.xx \"\" \"uux: unix to unix command\" \"execution.\" \"\" uux(1C)\n.xx \"\" \"acct:\" \"execution accounting file.\" \"\" acct(5)\n.xx \"\" \"uuxqt: UUCP\" \"execution file interpreter.\" \"\" uuxqt(8C)\n.xx \"\" \"sleep: suspend\" \"execution for an interval.\" \"\" sleep(1)\n.xx \"\" \"sleep: suspend\" \"execution for an interval.\" \"\" sleep(3F)\n.xx \"\" \"sleep: suspend\" \"execution for interval.\" \"\" sleep(3)\n.xx \"\" \"usleep: suspend\" \"execution for interval.\" \"\" usleep(3)\n.xx \"\" \"monitor, monstartup, moncontrol: prepare\" \"execution profile.\" \"\" monitor(3)\n.xx \"\" \"pxp: Pascal\" \"execution profiler.\" \"\" pxp(1)\n.xx \"\" \"rexecd: remote\" \"execution server.\" \"\" rexecd(8C)\n.xx \"\" \"etime, dtime: return elapsed\" \"execution time.\" \"\" etime(3F)\n.xx \"\" \"profil:\" \"execution time profile.\" \"\" profil(2)\n.xx \"\" \"pix: Pascal interpreter and\" \"executor.\" \"\" pix(1)\n.xx \"environ: execute a file.\" \"execl,\" \"execv, execle, execlp, execvp, exec, execve, exect,\" \"\" execl(3)\n.xx \"\" \"execl, execv, execle, execlp, execvp, exec,\" \"execve, exect, environ: execute a file.\" \"\" execl(3)\n.xx \"\" \"\" \"execve: execute a file.\" \"\" execve(2)\n.xx \"file.\" \"execl, execv, execle, execlp,\" \"execvp, exec, execve, exect, environ: execute a\" \"\" execl(3)\n.xx \"\" \"link: make a link to an\" \"existing file.\" \"\" link(3F)\n.xx \"\" \"tunefs: tune up an\" \"existing file system.\" \"\" tunefs(8)\n.xx \"\" \"/\\fB:\\fP, \\fB.\\fP, break, continue, cd, eval, exec,\" \"exit, export, login, read, readonly, set, shift,/\" \"\" sh(1)\n.xx \"\" \"breaksw:\" \"exit from switch.\" \"\" csh(1)\n.xx \"\" \"\" \"exit: leave shell.\" \"\" csh(1)\n.xx \"\" \"\" \"_exit: terminate a process.\" \"\" exit(2)\n.xx \"pending output.\" \"\" \"exit: terminate a process after flushing any\" \"\" exit(3)\n.xx \"\" \"\" \"exit: terminate process with status.\" \"\" exit(3F)\n.xx \"\" \"break:\" \"exit while/foreach loop.\" \"\" csh(1)\n.xx \"logarithm, power.\" \"\" \"exp, expm1, log, log10, log1p, pow: exponential,\" \"\" exp(3M)\n.xx \"\" \"glob: filename\" \"expand argument list.\" \"\" csh(1)\n.xx \"\" \"compress, uncompress, zcat: compress and\" \"expand data.\" \"\" compress(1)\n.xx \"\" \"expand, unexpand:\" \"expand tabs to spaces, and vice versa.\" \"\" expand(1)\n.xx \"versa.\" \"\" \"expand, unexpand: expand tabs to spaces, and vice\" \"\" expand(1)\n.xx \"diction.\" \"diction,\" \"explain: print wordy sentences; thesaurus for\" \"\" diction(1)\n.xx \"\" \"aardvark: yet another\" \"exploration game.\" \"\" aardvark(6)\n.xx \"\" \"adventure: an\" \"exploration game.\" \"\" adventure(6)\n.xx \"\" \"rogue:\" \"Exploring The Dungeons of Doom.\" \"\" rogue(6)\n.xx \"logarithm, power.\" \"exp,\" \"expm1, log, log10, log1p, pow: exponential,\" \"\" exp(3M)\n.xx \"\" \"frexp, ldexp, modf: split into mantissa and\" \"exponent.\" \"\" frexp(3)\n.xx \"\" \"drem, finite, logb, scalb: copysign, remainder,\" \"exponent manipulations.\" \"copysign,\" ieee(3M)\n.xx \"\" \"exp, expm1, log, log10, log1p, pow:\" \"exponential, logarithm, power.\" \"\" exp(3M)\n.xx \"\" \"/\\fB.\\fP, break, continue, cd, eval, exec, exit,\" \"export, login, read, readonly, set, shift, times,/\" \"\" sh(1)\n.xx \"\" \"\" \"expr: evaluate arguments as an expression.\" \"\" expr(1)\n.xx \"\" \"expr: evaluate arguments as an\" \"expression.\" \"\" expr(1)\n.xx \"\" \"re_comp, re_exec: regular\" \"expression handler.\" \"\" regex(3)\n.xx \"\" \"addbib: create or\" \"extend bibliographic database.\" \"\" addbib(1)\n.xx \"\" \"efl:\" \"Extended Fortran Language.\" \"\" efl(1)\n.xx \"strings.\" \"xstr:\" \"extract strings from C programs to implement shared\" \"\" xstr(1)\n.xx \"\" \"\" \"f77: Fortran 77 compiler.\" \"\" f77(1)\n.xx \"\" \"ioinit: change\" \"f77 I/O initialization.\" \"\" ioinit(3F)\n.xx \"libraries..\" \"plot: openpl et al.:\" \"f77 library interface to \\fIplot\\fR (3X)\" \"\" plot(3F)\n.xx \"\" \"tclose, tread, twrite, trewin, tskipf, tstate:\" \"f77 tape I/O.\" \"topen,\" topen(3F)\n.xx \"ceiling, and round-to-nearest functions.\" \"\" \"fabs, floor, ceil, rint: absolute value, floor,\" \"\" floor(3M)\n.xx \"\" \"networking: introduction to networking\" \"facilities.\" \"\" intro(4N)\n.xx \"\" \"signal: simplified software signal\" \"facilities.\" \"\" signal(3C)\n.xx \"\" \"sigvec: software signal\" \"facilities.\" \"\" sigvec(2)\n.xx \"\" \"malloc, free,\" \"falloc: memory allocator.\" \"\" malloc(3F)\n.xx \"\" \"true,\" \"false: provide truth values.\" \"\" true(1)\n.xx \"\" \"\" \"false, true: provide truth values.\" \"\" false(1)\n.xx \"\" \"inet: Internet protocol\" \"family.\" \"\" inet(4F)\n.xx \"\" \"ns: Xerox Network Systems(tm) protocol\" \"family.\" \"\" ns(4F)\n.xx \"checking the disks.\" \"\" \"fastboot, fasthalt: reboot/halt the system without\" \"\" fastboot(8)\n.xx \"the disks.\" \"fastboot,\" \"fasthalt: reboot/halt the system without checking\" \"\" fastboot(8)\n.xx \"\" \"abort: generate a\" \"fault.\" \"\" abort(3)\n.xx \"\" \"trpfpe, fpecnt: trap and repair floating point\" \"faults.\" \"\" trpfpe(3F)\n.xx \"export, login,/\" \"sh, for, case, if, while, \\fB:\\fP,\" \"\\fB.\\fP, break, continue, cd, eval, exec, exit,\" \"\" sh(1)\n.xx \"exit, export, login,/\" \"sh, for, case, if, while,\" \"\\fB:\\fP, \\fB.\\fP, break, continue, cd, eval, exec,\" \"\" sh(1)\n.xx \"\" \"\" \"fclose, fflush: close or flush a stream.\" \"\" fclose(3S)\n.xx \"\" \"\" \"fcntl: file control.\" \"\" fcntl(2)\n.xx \"\" \"ecvt,\" \"fcvt, gcvt: output conversion.\" \"\" ecvt(3)\n.xx \"\" \"\" \"fdate: return date and time in an ASCII string.\" \"\" fdate(3F)\n.xx \"\" \"fopen, freopen,\" \"fdopen: open a stream.\" \"\" fopen(3S)\n.xx \"\" \"ferror,\" \"feof, clearerr, fileno: stream status inquiries.\" \"\" ferror(3S)\n.xx \"inquiries.\" \"\" \"ferror, feof, clearerr, fileno: stream status\" \"\" ferror(3S)\n.xx \"subroutines.\" \"dbminit,\" \"fetch, store, delete, firstkey, nextkey: data base\" \"\" dbm(3X)\n.xx \"\" \"head: give first\" \"few lines.\" \"\" head(1)\n.xx \"\" \"fclose,\" \"fflush: close or flush a stream.\" \"\" fclose(3S)\n.xx \"extreme values.\" \"flmin, flmax,\" \"ffrac, dflmin, dflmax, dffrac, inmax: return\" \"\" flmin(3F)\n.xx \"\" \"bcopy, bcmp, bzero,\" \"ffs: bit and byte string operations.\" \"\" bstring(3)\n.xx \"\" \"\" \"fg: bring job into foreground.\" \"\" csh(1)\n.xx \"\" \"getc,\" \"fgetc: get a character from a logical unit.\" \"\" getc(3F)\n.xx \"\" \"getc, getchar,\" \"fgetc, getw: get character or word from stream.\" \"\" getc(3S)\n.xx \"\" \"gets,\" \"fgets: get a string from a stream.\" \"\" gets(3S)\n.xx \"\" \"grep, egrep,\" \"fgrep: search a file for a pattern.\" \"\" grep(1)\n.xx \"\" \"locate a program file including aliases and paths\" \"(\\fIcsh\\fR only).\" \"which:\" which(1)\n.xx \"\" \"robots:\" \"fight off villainous robots.\" \"\" robots(6)\n.xx \"\" \"access: determine accessibility of\" \"file.\" \"\" access(2)\n.xx \"\" \"access: determine accessability of a\" \"file.\" \"\" access(3F)\n.xx \"\" \"acct: execution accounting\" \"file.\" \"\" acct(5)\n.xx \"\" \"chmod: change mode of\" \"file.\" \"\" chmod(2)\n.xx \"\" \"chmod: change mode of a\" \"file.\" \"\" chmod(3F)\n.xx \"\" \"chown: change owner and group of a\" \"file.\" \"\" chown(2)\n.xx \"\" \"colrm: remove columns from a\" \"file.\" \"\" colrm(1)\n.xx \"\" \"core: format of memory image\" \"file.\" \"\" core(5)\n.xx \"\" \"creat: create a new\" \"file.\" \"\" creat(2)\n.xx \"\" \"source: read commands from\" \"file.\" \"\" csh(1)\n.xx \"\" \"ctags: create a tags\" \"file.\" \"\" ctags(1)\n.xx \"\" \"dd: convert and copy a\" \"file.\" \"\" dd(1)\n.xx \"\" \"disktab: disk description\" \"file.\" \"\" disktab(5)\n.xx \"\" \"execvp, exec, execve, exect, environ: execute a\" \"file.\" \"execl, execv, execle, execlp,\" execl(3)\n.xx \"\" \"execve: execute a\" \"file.\" \"\" execve(2)\n.xx \"\" \"flock: apply or remove an advisory lock on an open\" \"file.\" \"\" flock(2)\n.xx \"\" \"fpr: print Fortran\" \"file.\" \"\" fpr(1)\n.xx \"\" \"group: group\" \"file.\" \"\" group(5)\n.xx \"\" \"L.aliases: UUCP hostname alias\" \"file.\" \"\" L.aliases(5)\n.xx \"\" \"L.cmds: UUCP remote command permissions\" \"file.\" \"\" L.cmds(5)\n.xx \"\" \"L-devices: UUCP device description\" \"file.\" \"\" L-devices(5)\n.xx \"\" \"L-dialcodes: UUCP phone number index\" \"file.\" \"\" L-dialcodes(5)\n.xx \"\" \"link: make a hard link to a\" \"file.\" \"\" link(2)\n.xx \"\" \"link: make a link to an existing\" \"file.\" \"\" link(3F)\n.xx \"\" \"L.sys: UUCP remote host description\" \"file.\" \"\" L.sys(5)\n.xx \"\" \"mkdir: make a directory\" \"file.\" \"\" mkdir(2)\n.xx \"\" \"mknod: make a special\" \"file.\" \"\" mknod(2)\n.xx \"\" \"mknod: build special\" \"file.\" \"\" mknod(8)\n.xx \"\" \"rebuild the data base for the mail aliases\" \"file.\" \"newaliases:\" newaliases(1)\n.xx \"\" \"open a file for reading or writing, or create a new\" \"file.\" \"open:\" open(2)\n.xx \"\" \"passwd: password\" \"file.\" \"\" passwd(5)\n.xx \"\" \"pr: print\" \"file.\" \"\" pr(1)\n.xx \"\" \"remote: remote host description\" \"file.\" \"\" remote(5)\n.xx \"\" \"rename: change the name of a\" \"file.\" \"\" rename(2)\n.xx \"\" \"rename: rename a\" \"file.\" \"\" rename(3F)\n.xx \"\" \"resolver configuration\" \"file.\" \"\" resolver(5)\n.xx \"\" \"rev: reverse lines of a\" \"file.\" \"\" rev(1)\n.xx \"\" \"rmdir: remove a directory\" \"file.\" \"\" rmdir(2)\n.xx \"\" \"size: size of an object\" \"file.\" \"\" size(1)\n.xx \"\" \"the printable strings in a object, or other binary,\" \"file.\" \"strings: find\" strings(1)\n.xx \"\" \"sum: sum and count blocks in a\" \"file.\" \"\" sum(1)\n.xx \"\" \"symlink: make symbolic link to a\" \"file.\" \"\" symlink(2)\n.xx \"\" \"tail: deliver the last part of a\" \"file.\" \"\" tail(1)\n.xx \"\" \"touch: update date last modified of a\" \"file.\" \"\" touch(1)\n.xx \"\" \"uniq: report repeated lines in a\" \"file.\" \"\" uniq(1)\n.xx \"\" \"USERFILE: UUCP pathname permissions\" \"file.\" \"\" USERFILE(5)\n.xx \"\" \"uuencode: format of an encoded uuencode\" \"file.\" \"\" uuencode(5)\n.xx \"\" \"vipw: edit the password\" \"file.\" \"\" vipw(8)\n.xx \"\" \"versions of object modules were used to construct a\" \"file.\" \"what: show what\" what(1)\n.xx \"\" \"diff: differential\" \"file and directory comparator.\" \"\" diff(1)\n.xx \"\" \"bugfiler:\" \"file bug reports in folders automatically.\" \"\" bugfiler(8)\n.xx \"\" \"mkstr: create an error message\" \"file by massaging C source.\" \"\" mkstr(1)\n.xx \"\" \"diff3: 3-way differential\" \"file comparison.\" \"\" diff3(1)\n.xx \"\" \"fcntl:\" \"file control.\" \"\" fcntl(2)\n.xx \"\" \"rcp: remote\" \"file copy.\" \"\" rcp(1C)\n.xx \"\" \"umask: change or display\" \"file creation mask.\" \"\" csh(1)\n.xx \"\" \"umask: set\" \"file creation mode mask.\" \"\" umask(2)\n.xx \"\" \"\" \"file: determine file type.\" \"\" file(1)\n.xx \"\" \"rdist: remote\" \"file distribution program.\" \"\" rdist(1)\n.xx \"\" \"setfsent, endfsent: get file system descriptor\" \"file entry.\" \"/getfsspec, getfsfile, getfstype,\" getfsent(3)\n.xx \"\" \"getgrgid, getgrnam, setgrent, endgrent: get group\" \"file entry.\" \"getgrent,\" getgrent(3)\n.xx \"\" \"setpwent, endpwent, setpwfile: get password\" \"file entry.\" \"getpwent, getpwuid, getpwnam,\" getpwent(3)\n.xx \"\" \"getttynam, setttyent, endttyent: get ttys\" \"file entry.\" \"getttyent,\" getttyent(3)\n.xx \"\" \"grep, egrep, fgrep: search a\" \"file for a pattern.\" \"\" grep(1)\n.xx \"\" \"open: open a\" \"file for reading or writing, or create a new file.\" \"\" open(2)\n.xx \"\" \"aliases: aliases\" \"file for sendmail.\" \"\" aliases(5)\n.xx \"\" \"uuencode, uudecode: encode/decode a binary\" \"file for transmission via mail.\" \"\" uuencode(1C)\n.xx \"\" \"ar: archive (library)\" \"file format.\" \"\" ar(5)\n.xx \"\" \"tar: tape archive\" \"file format.\" \"\" tar(5)\n.xx \"\" \"which: locate a program\" \"file including aliases and paths (\\fIcsh\\fR only).\" \"\" which(1)\n.xx \"\" \"chfn, chsh, passwd: change password\" \"file information.\" \"\" chfn(1)\n.xx \"\" \"chfn, chsh, passwd: change password\" \"file information.\" \"\" chsh(1)\n.xx \"\" \"chfn, chsh, passwd: change password\" \"file information.\" \"\" passwd(1)\n.xx \"\" \"uuxqt: UUCP execution\" \"file interpreter.\" \"\" uuxqt(8C)\n.xx \"\" \"fsplit: split a multi-routine Fortran\" \"file into individual files.\" \"\" fsplit(1)\n.xx \"\" \"split: split a\" \"file into pieces.\" \"\" split(1)\n.xx \"\" \"pmerge: pascal\" \"file merger.\" \"\" pmerge(1)\n.xx \"\" \"mktemp: make a unique\" \"file name.\" \"\" mktemp(3)\n.xx \"\" \"fseek, ftell: reposition a\" \"file on a logical unit.\" \"\" fseek(3F)\n.xx \"\" \"more, page:\" \"file perusal filter for crt viewing.\" \"\" more(1)\n.xx \"\" \"stat, lstat, fstat: get\" \"file status.\" \"\" stat(2)\n.xx \"\" \"stat, lstat, fstat: get\" \"file status.\" \"\" stat(3F)\n.xx \"\" \"mkfs: construct a\" \"file system.\" \"\" mkfs(8)\n.xx \"\" \"mkproto: construct a prototype\" \"file system.\" \"\" mkproto(8)\n.xx \"\" \"mount, umount: mount or remove\" \"file system.\" \"\" mount(2)\n.xx \"\" \"mount, umount: mount and dismount\" \"file system.\" \"\" mount(8)\n.xx \"\" \"newfs: construct a new\" \"file system.\" \"\" newfs(8)\n.xx \"\" \"repquota: summarize quotas for a\" \"file system.\" \"\" repquota(8)\n.xx \"\" \"setquota: enable/disable quotas on a\" \"file system.\" \"\" setquota(2)\n.xx \"\" \"tunefs: tune up an existing\" \"file system.\" \"\" tunefs(8)\n.xx \"repair.\" \"fsck:\" \"file system consistency check and interactive\" \"\" fsck(8)\n.xx \"\" \"getfsfile, getfstype, setfsent, endfsent: get\" \"file system descriptor file entry.\" \"/getfsspec,\" getfsent(3)\n.xx \"\" \"dcheck:\" \"file system directory consistency check.\" \"\" dcheck(8)\n.xx \"\" \"dump: incremental\" \"file system dump.\" \"\" dump(8)\n.xx \"\" \"rdump:\" \"file system dump across the network.\" \"\" rdump(8C)\n.xx \"\" \"rrestore: restore a\" \"file system dump across the network.\" \"\" rrestore(8C)\n.xx \"\" \"hier:\" \"file system hierarchy.\" \"\" hier(7)\n.xx \"\" \"dumpfs: dump\" \"file system information.\" \"\" dumpfs(8)\n.xx \"\" \"quot: summarize\" \"file system ownership.\" \"\" quot(8)\n.xx \"\" \"quotacheck:\" \"file system quota consistency checker.\" \"\" quotacheck(8)\n.xx \"\" \"quotaon, quotaoff: turn\" \"file system quotas on and off.\" \"\" quotaon(8)\n.xx \"\" \"restore: incremental\" \"file system restore.\" \"\" restore(8)\n.xx \"\" \"icheck:\" \"file system storage consistency check.\" \"\" icheck(8)\n.xx \"\" \"mtab: mounted\" \"file system table.\" \"\" mtab(5)\n.xx \"\" \"fs, inode: format of\" \"file system volume.\" \"\" fs(5)\n.xx \"\" \"utime: set\" \"file times.\" \"\" utime(3C)\n.xx \"\" \"utimes: set\" \"file times.\" \"\" utimes(2)\n.xx \"\" \"uusend: send a\" \"file to a remote host.\" \"\" uusend(1C)\n.xx \"\" \"truncate: truncate a\" \"file to a specified length.\" \"\" truncate(2)\n.xx \"\" \"patch: a program for applying a diff\" \"file to an original.\" \"\" patch(1)\n.xx \"\" \"ftp: ARPANET\" \"file transfer program.\" \"\" ftp(1C)\n.xx \"\" \"tftp: trivial\" \"file transfer program.\" \"\" tftp(1C)\n.xx \"\" \"ftpd: DARPA Internet\" \"File Transfer Protocol server.\" \"\" ftpd(8C)\n.xx \"\" \"tftpd: DARPA Trivial\" \"File Transfer Protocol server.\" \"\" tftpd(8C)\n.xx \"\" \"file: determine\" \"file type.\" \"\" file(1)\n.xx \"\" \"basename: strip\" \"filename affixes.\" \"\" basename(1)\n.xx \"\" \"glob:\" \"filename expand argument list.\" \"\" csh(1)\n.xx \"\" \"ferror, feof, clearerr,\" \"fileno: stream status inquiries.\" \"\" ferror(3S)\n.xx \"\" \"checknr: check nroff/troff\" \"files.\" \"\" checknr(1)\n.xx \"\" \"cmp: compare two\" \"files.\" \"\" cmp(1)\n.xx \"\" \"comm: select or reject lines common to two sorted\" \"files.\" \"\" comm(1)\n.xx \"\" \"config: build system configuration\" \"files.\" \"\" config(8)\n.xx \"\" \"find: find\" \"files.\" \"\" find(1)\n.xx \"\" \"split a multi-routine Fortran file into individual\" \"files.\" \"fsplit:\" fsplit(1)\n.xx \"\" \"makedev: make system special\" \"files.\" \"\" makedev(8)\n.xx \"\" \"mv: move or rename\" \"files.\" \"\" mv(1)\n.xx \"\" \"rmdir, rm: remove (unlink) directories or\" \"files.\" \"\" rmdir(1)\n.xx \"\" \"sort: sort or merge\" \"files.\" \"\" sort(1)\n.xx \"\" \"uulog: display UUCP log\" \"files.\" \"\" uulog(1C)\n.xx \"\" \"intro: introduction to special\" \"files and hardware support.\" \"\" intro(4)\n.xx \"\" \"catman: create the cat\" \"files for the manual.\" \"\" catman(8)\n.xx \"\" \"fsync: synchronize a\" \"file's in-core state with that on disk.\" \"\" fsync(2)\n.xx \"\" \"rm, rmdir: remove (unlink)\" \"files or directories.\" \"\" rm(1)\n.xx \"\" \"uucico, uucpd: transfer\" \"files queued by uucp or uux.\" \"\" uucico(8C)\n.xx \"\" \"badsect: create\" \"files to contain bad sectors.\" \"\" badsect(8)\n.xx \"\" \"fstab: static information about the\" \"filesystems.\" \"\" fstab(5)\n.xx \"\" \"more, page: file perusal\" \"filter for crt viewing.\" \"\" more(1)\n.xx \"\" \"colcrt:\" \"filter nroff output for CRT previewing.\" \"\" colcrt(1)\n.xx \"\" \"col:\" \"filter reverse line feeds.\" \"\" col(1)\n.xx \"\" \"plot: graphics\" \"filters.\" \"\" plot(1G)\n.xx \"\" \"refer:\" \"find and insert literature references in documents.\" \"\" refer(1)\n.xx \"\" \"find:\" \"find files.\" \"\" find(1)\n.xx \"\" \"\" \"find: find files.\" \"\" find(1)\n.xx \"\" \"look:\" \"find lines in a sorted list.\" \"\" look(1)\n.xx \"manual.\" \"man:\" \"find manual information by keywords; print out the\" \"\" man(1)\n.xx \"\" \"ttyname, isatty, ttyslot:\" \"find name of a terminal.\" \"\" ttyname(3)\n.xx \"\" \"ttynam, isatty:\" \"find name of a terminal port.\" \"\" ttynam(3F)\n.xx \"\" \"lorder:\" \"find ordering relation for an object library.\" \"\" lorder(1)\n.xx \"\" \"lookbib: build inverted index for a bibliography,\" \"find references in a bibliography.\" \"indxbib,\" lookbib(1)\n.xx \"\" \"spell, spellin, spellout:\" \"find spelling errors.\" \"\" spell(1)\n.xx \"binary, file.\" \"strings:\" \"find the printable strings in a object, or other\" \"\" strings(1)\n.xx \"\" \"\" \"finger: user information lookup program.\" \"\" finger(1)\n.xx \"\" \"\" \"fingerd: remote user information server.\" \"\" fingerd(8C)\n.xx \"manipulations.\" \"copysign, drem,\" \"finite, logb, scalb: copysign, remainder, exponent\" \"\" ieee(3M)\n.xx \"\" \"fold: fold long lines for\" \"finite width output device.\" \"\" fold(1)\n.xx \"\" \"plot: openpl et al.: f77 library interface to\" \"\\fIplot\\fR (3X) libraries..\" \"\" plot(3F)\n.xx \"\" \"head: give\" \"first few lines.\" \"\" head(1)\n.xx \"\" \"dbminit, fetch, store, delete,\" \"firstkey, nextkey: data base subroutines.\" \"\" dbm(3X)\n.xx \"\" \"fish: play ``Go\" \"Fish''.\" \"\" fish(6)\n.xx \"\" \"\" \"fish: play ``Go Fish''.\" \"\" fish(6)\n.xx \"\" \"nice, nohup: run a command at low priority\" \"(\\fIsh\\fR only).\" \"\" nice(1)\n.xx \"\" \"\" \"fl: console floppy interface.\" \"\" fl(4)\n.xx \"\" \"arff,\" \"flcopy: archiver and copier for floppy.\" \"\" arff(8V)\n.xx \"extreme values.\" \"flmin,\" \"flmax, ffrac, dflmin, dflmax, dffrac, inmax: return\" \"\" flmin(3F)\n.xx \"return extreme values.\" \"\" \"flmin, flmax, ffrac, dflmin, dflmax, dffrac, inmax:\" \"\" flmin(3F)\n.xx \"\" \"trpfpe, fpecnt: trap and repair\" \"floating point faults.\" \"\" trpfpe(3F)\n.xx \"\" \"trapov: trap and repair\" \"floating point overflow.\" \"\" trapov(3F)\n.xx \"\" \"infnan: signals invalid\" \"floating-point operations on a VAX (temporary).\" \"\" infnan(3M)\n.xx \"file.\" \"\" \"flock: apply or remove an advisory lock on an open\" \"\" flock(2)\n.xx \"and round-to-nearest functions.\" \"fabs,\" \"floor, ceil, rint: absolute value, floor, ceiling,\" \"\" floor(3M)\n.xx \"\" \"fabs, floor, ceil, rint: absolute value,\" \"floor, ceiling, and round-to-nearest functions.\" \"\" floor(3M)\n.xx \"\" \"arff, flcopy: archiver and copier for\" \"floppy.\" \"\" arff(8V)\n.xx \"\" \"rx: DEC RX02\" \"floppy disk interface.\" \"\" rx(4)\n.xx \"\" \"rxformat: format\" \"floppy disks.\" \"\" rxformat(8V)\n.xx \"\" \"fl: console\" \"floppy interface.\" \"\" fl(4)\n.xx \"\" \"fclose, fflush: close or\" \"flush a stream.\" \"\" fclose(3S)\n.xx \"\" \"\" \"flush: flush output to a logical unit.\" \"\" flush(3F)\n.xx \"\" \"flush:\" \"flush output to a logical unit.\" \"\" flush(3F)\n.xx \"\" \"exit: terminate a process after\" \"flushing any pending output.\" \"\" exit(3)\n.xx \"\" \"/gcd, invert, rpow, msqrt, mcmp, move, min, omin,\" \"fmin, m_in, mout, omout, fmout, m_out, sdiv, itom:/\" \"\" mp(3X)\n.xx \"\" \"/mcmp, move, min, omin, fmin, m_in, mout, omout,\" \"fmout, m_out, sdiv, itom: multiple precision/\" \"\" mp(3X)\n.xx \"\" \"\" \"fmt: simple text formatter.\" \"\" fmt(1)\n.xx \"device.\" \"\" \"fold: fold long lines for finite width output\" \"\" fold(1)\n.xx \"\" \"fold:\" \"fold long lines for finite width output device.\" \"\" fold(1)\n.xx \"\" \"bugfiler: file bug reports in\" \"folders automatically.\" \"\" bugfiler(8)\n.xx \"\" \"vwidth: make troff width table for a\" \"font.\" \"\" vwidth(1)\n.xx \"\" \"vfont:\" \"font formats for the Benson-Varian or Versatec.\" \"\" vfont(5)\n.xx \"\" \"\" \"fopen, freopen, fdopen: open a stream.\" \"\" fopen(3S)\n.xx \"\" \"\" \"foreach: loop over list of names.\" \"\" csh(1)\n.xx \"\" \"fg: bring job into\" \"foreground.\" \"\" csh(1)\n.xx \"\" \"\" \"fork: create a copy of this process.\" \"\" fork(3F)\n.xx \"\" \"\" \"fork: create a new process.\" \"\" fork(2)\n.xx \"\" \"idate, itime: return date or time in numerical\" \"form.\" \"\" idate(3F)\n.xx \"\" \"dmesg: collect system diagnostic messages to\" \"form error log.\" \"\" dmesg(8)\n.xx \"\" \"ar: archive (library) file\" \"format.\" \"\" ar(5)\n.xx \"\" \"dump, dumpdates: incremental dump\" \"format.\" \"\" dump(5)\n.xx \"\" \"tar: tape archive file\" \"format.\" \"\" tar(5)\n.xx \"\" \"indent: indent and\" \"format C program source.\" \"\" indent(1)\n.xx \"\" \"format: how to\" \"format disk packs.\" \"\" format(8V)\n.xx \"\" \"rxformat:\" \"format floppy disks.\" \"\" rxformat(8V)\n.xx \"\" \"htable: convert NIC standard\" \"format host tables.\" \"\" htable(8)\n.xx \"\" \"gettable: get NIC\" \"format host tables from a host.\" \"\" gettable(8C)\n.xx \"\" \"\" \"format: how to format disk packs.\" \"\" format(8V)\n.xx \"vtroff, or troff.\" \"vlp:\" \"Format Lisp programs to be printed with nroff,\" \"\" vlp(1)\n.xx \"\" \"uuencode:\" \"format of an encoded uuencode file.\" \"\" uuencode(5)\n.xx \"\" \"dir:\" \"format of directories.\" \"\" dir(5)\n.xx \"\" \"fs, inode:\" \"format of file system volume.\" \"\" fs(5)\n.xx \"\" \"core:\" \"format of memory image file.\" \"\" core(5)\n.xx \"\" \"tbl:\" \"format tables for nroff or troff.\" \"\" tbl(1)\n.xx \"\" \"tp: DEC/mag tape\" \"formats.\" \"\" tp(5)\n.xx \"\" \"vfont: font\" \"formats for the Benson-Varian or Versatec.\" \"\" vfont(5)\n.xx \"\" \"scanf, fscanf, sscanf:\" \"formatted input conversion.\" \"\" scanf(3S)\n.xx \"\" \"printf, fprintf, sprintf:\" \"formatted output conversion.\" \"\" printf(3S)\n.xx \"\" \"fmt: simple text\" \"formatter.\" \"\" fmt(1)\n.xx \"\" \"bib, listrefs: bibliographic\" \"formatter; list bibliographic reference items.\" \"\" bib(1)\n.xx \"\" \"nroff: text\" \"formatting.\" \"\" nroff(1)\n.xx \"\" \"troff, nroff: text\" \"formatting and typesetting.\" \"\" troff(1)\n.xx \"\" \"ms: text\" \"formatting macros.\" \"\" ms(7)\n.xx \"\" \"me: macros for\" \"formatting papers.\" \"\" me(7)\n.xx \"\" \"f77:\" \"Fortran 77 compiler.\" \"\" f77(1)\n.xx \"\" \"ratfor: rational\" \"Fortran dialect.\" \"\" ratfor(1)\n.xx \"\" \"fpr: print\" \"Fortran file.\" \"\" fpr(1)\n.xx \"\" \"fsplit: split a multi-routine\" \"Fortran file into individual files.\" \"\" fsplit(1)\n.xx \"\" \"efl: Extended\" \"Fortran Language.\" \"\" efl(1)\n.xx \"\" \"intro: introduction to\" \"FORTRAN library functions.\" \"\" intro(3F)\n.xx \"\" \"putc, fputc: write a character to a\" \"fortran logical unit.\" \"\" putc(3F)\n.xx \"\" \"struct: structure\" \"Fortran programs.\" \"\" struct(1)\n.xx \"adage.\" \"\" \"fortune: print a random, hopefully interesting,\" \"\" fortune(6)\n.xx \"login,/\" \"sh, for, case, if, while, \\fB:\\fP, \\fB.\" \"\\fP, break, continue, cd, eval, exec, exit, export,\" \"\" sh(1)\n.xx \"exit, export,/\" \"sh, for, case, if, while, \\fB:\" \"\\fP, \\fB.\\fP, break, continue, cd, eval, exec,\" \"\" sh(1)\n.xx \"compiler/interpreter.\" \"\" \"fp: Functional Programming language\" \"\" fp(1)\n.xx \"\" \"trpfpe,\" \"fpecnt: trap and repair floating point faults.\" \"\" trpfpe(3F)\n.xx \"\" \"\" \"fpr: print Fortran file.\" \"\" fpr(1)\n.xx \"\" \"printf,\" \"fprintf, sprintf: formatted output conversion.\" \"\" printf(3S)\n.xx \"\" \"putc, putchar,\" \"fputc, putw: put character or word on a stream.\" \"\" putc(3S)\n.xx \"\" \"putc,\" \"fputc: write a character to a fortran logical unit.\" \"\" putc(3F)\n.xx \"\" \"puts,\" \"fputs: put a string on a stream.\" \"\" puts(3S)\n.xx \"\" \"ik: Ikonas\" \"frame buffer, graphics device interface.\" \"\" ik(4)\n.xx \"\" \"liszt: compile a\" \"Franz Lisp program.\" \"\" liszt(1)\n.xx \"\" \"\" \"fread, fwrite: buffered binary input/output.\" \"\" fread(3S)\n.xx \"\" \"df: disk\" \"free.\" \"\" df(1)\n.xx \"\" \"malloc,\" \"free, falloc: memory allocator.\" \"\" malloc(3F)\n.xx \"\" \"malloc,\" \"free, realloc, calloc, alloca: memory allocator.\" \"\" malloc(3)\n.xx \"\" \"fopen,\" \"freopen, fdopen: open a stream.\" \"\" fopen(3S)\n.xx \"exponent.\" \"\" \"frexp, ldexp, modf: split into mantissa and\" \"\" frexp(3)\n.xx \"\" \"from: who is my mail\" \"from?.\" \"\" from(1)\n.xx \"\" \"sccs:\" \"front end for the SCCS subsystem.\" \"\" sccs(1)\n.xx \"\" \"\" \"fs, inode: format of file system volume.\" \"\" fs(5)\n.xx \"\" \"scanf,\" \"fscanf, sscanf: formatted input conversion.\" \"\" scanf(3S)\n.xx \"\" \"mklost+found: make a lost+found directory for\" \"fsck.\" \"\" mklost+found(8)\n.xx \"repair.\" \"\" \"fsck: file system consistency check and interactive\" \"\" fsck(8)\n.xx \"\" \"\" \"fseek, ftell: reposition a file on a logical unit.\" \"\" fseek(3F)\n.xx \"\" \"\" \"fseek, ftell, rewind: reposition a stream.\" \"\" fseek(3S)\n.xx \"individual files.\" \"\" \"fsplit: split a multi-routine Fortran file into\" \"\" fsplit(1)\n.xx \"\" \"\" \"fstab: static information about the filesystems.\" \"\" fstab(5)\n.xx \"\" \"stat, lstat,\" \"fstat: get file status.\" \"\" stat(2)\n.xx \"\" \"stat, lstat,\" \"fstat: get file status.\" \"\" stat(3F)\n.xx \"on disk.\" \"\" \"fsync: synchronize a file's in-core state with that\" \"\" fsync(2)\n.xx \"\" \"fseek,\" \"ftell: reposition a file on a logical unit.\" \"\" fseek(3F)\n.xx \"\" \"fseek,\" \"ftell, rewind: reposition a stream.\" \"\" fseek(3S)\n.xx \"\" \"time,\" \"ftime: get date and time.\" \"\" time(3C)\n.xx \"\" \"\" \"ftp: ARPANET file transfer program.\" \"\" ftp(1C)\n.xx \"\" \"\" \"ftpd: DARPA Internet File Transfer Protocol server.\" \"\" ftpd(8C)\n.xx \"\" \"shutdown: shut down part of a\" \"full-duplex connection.\" \"\" shutdown(2)\n.xx \"\" \"tn3270:\" \"full-screen remote login to IBM VM/CMS.\" \"\" tn3270(1)\n.xx \"\" \"lgamma: log gamma\" \"function.\" \"\" lgamma(3M)\n.xx \"compiler/interpreter.\" \"fp:\" \"Functional Programming language\" \"\" fp(1)\n.xx \"\" \"asinh, acosh, atanh: inverse hyperbolic\" \"functions.\" \"\" asinh(3M)\n.xx \"\" \"bit: and, or, xor, not, rshift, lshift bitwise\" \"functions.\" \"\" bit(3F)\n.xx \"\" \"erf, erfc: error\" \"functions.\" \"\" erf(3M)\n.xx \"\" \"value, floor, ceiling, and round-to-nearest\" \"functions.\" \"fabs, floor, ceil, rint: absolute\" floor(3M)\n.xx \"\" \"intro: introduction to C library\" \"functions.\" \"\" intro(3)\n.xx \"\" \"intro: introduction to FORTRAN library\" \"functions.\" \"\" intro(3F)\n.xx \"\" \"j0, j1, jn, y0, y1, yn: bessel\" \"functions.\" \"\" j0(3M)\n.xx \"\" \"math: introduction to mathematical library\" \"functions.\" \"\" math(3M)\n.xx \"\" \"sinh, cosh, tanh: hyperbolic\" \"functions.\" \"\" sinh(3M)\n.xx \"\" \"cos, tan, asin, acos, atan, atan2: trigonometric\" \"functions and their inverses.\" \"sin,\" sin(3M)\n.xx \"\" \"bessel\" \"functions: of two kinds for integer orders.\" \"\" bessel(3F)\n.xx \"\" \"curses: screen\" \"functions with ``optimal'' cursor motion.\" \"\" curses(3X)\n.xx \"\" \"fread,\" \"fwrite: buffered binary input/output.\" \"\" fread(3S)\n.xx \"\" \"aardvark: yet another exploration\" \"game.\" \"\" aardvark(6)\n.xx \"\" \"adventure: an exploration\" \"game.\" \"\" adventure(6)\n.xx \"\" \"backgammon: the\" \"game.\" \"\" backgammon(6)\n.xx \"\" \"battlestar: a tropical adventure\" \"game.\" \"\" battlestar(6)\n.xx \"\" \"hunt: a multi-player multi-terminal\" \"game.\" \"\" hunt(6)\n.xx \"\" \"monop: Monopoly\" \"game.\" \"\" monop(6)\n.xx \"\" \"snake, snscore: display chase\" \"game.\" \"\" snake(6)\n.xx \"\" \"trek: trekkie\" \"game.\" \"\" trek(6)\n.xx \"\" \"worm: Play the growing worm\" \"game.\" \"\" worm(6)\n.xx \"\" \"canfield, cfscores: the solitaire card\" \"game canfield.\" \"\" canfield(6)\n.xx \"\" \"cribbage: the card\" \"game cribbage.\" \"\" cribbage(6)\n.xx \"\" \"hangman: Computer version of the\" \"game hangman.\" \"\" hangman(6)\n.xx \"\" \"boggle: play the\" \"game of boggle.\" \"\" boggle(6)\n.xx \"\" \"chess: the\" \"game of chess.\" \"\" chess(6)\n.xx \"\" \"zork: the\" \"game of dungeon.\" \"\" zork(6)\n.xx \"\" \"wump: the\" \"game of hunt-the-wumpus.\" \"\" wump(6)\n.xx \"\" \"lgamma: log\" \"gamma function.\" \"\" lgamma(3M)\n.xx \"fmin, m_in, mout,/\" \"madd, msub, mult, mdiv, pow,\" \"gcd, invert, rpow, msqrt, mcmp, move, min, omin,\" \"\" mp(3X)\n.xx \"\" \"\" \"gcore: get core images of running processes.\" \"\" gcore(1)\n.xx \"\" \"ecvt, fcvt,\" \"gcvt: output conversion.\" \"\" ecvt(3)\n.xx \"buffers.\" \"kgmon:\" \"generate a dump of the operating system's profile\" \"\" kgmon(8)\n.xx \"\" \"abort:\" \"generate a fault.\" \"\" abort(3)\n.xx \"\" \"makekey:\" \"generate encryption key.\" \"\" makekey(8)\n.xx \"\" \"mkhosts:\" \"generate hashed host table.\" \"\" mkhosts(8)\n.xx \"\" \"mkpasswd:\" \"generate hashed password table.\" \"\" mkpasswd(8)\n.xx \"\" \"lptest:\" \"generate lineprinter ripple pattern.\" \"\" lptest(1)\n.xx \"\" \"ncheck:\" \"generate names from i-numbers.\" \"\" ncheck(8)\n.xx \"\" \"rand, srand: random number\" \"generator.\" \"\" rand(3C)\n.xx \"\" \"random, drandm, irandm: better random number\" \"generator.\" \"\" random(3F)\n.xx \"\" \"lex:\" \"generator of lexical analysis programs.\" \"\" lex(1)\n.xx \"\" \"/srandom, initstate, setstate: better random number\" \"generator; routines for changing generators.\" \"\" random(3)\n.xx \"\" \"random number generator; routines for changing\" \"generators.\" \"/srandom, initstate, setstate: better\" random(3)\n.xx \"\" \"perror,\" \"gerror, ierrno: get system error messages.\" \"\" perror(3F)\n.xx \"\" \"\" \"getarg, iargc: return command line arguments.\" \"\" getarg(3F)\n.xx \"\" \"\" \"getc, fgetc: get a character from a logical unit.\" \"\" getc(3F)\n.xx \"from stream.\" \"\" \"getc, getchar, fgetc, getw: get character or word\" \"\" getc(3S)\n.xx \"stream.\" \"getc,\" \"getchar, fgetc, getw: get character or word from\" \"\" getc(3S)\n.xx \"\" \"\" \"getcwd: get pathname of current working directory.\" \"\" getcwd(3F)\n.xx \"\" \"\" \"getdiskbyname: get disk description by its name.\" \"\" getdisk(3)\n.xx \"\" \"\" \"getdtablesize: get descriptor table size.\" \"\" getdtablesize(2)\n.xx \"\" \"getgid,\" \"getegid: get group identity.\" \"\" getgid(2)\n.xx \"\" \"\" \"getenv: get value of environment variables.\" \"\" getenv(3F)\n.xx \"\" \"\" \"getenv: value for environment name.\" \"\" getenv(3)\n.xx \"\" \"getuid,\" \"geteuid: get user identity.\" \"\" getuid(2)\n.xx \"setfsent, endfsent: get file system descriptor/\" \"\" \"getfsent, getfsspec, getfsfile, getfstype,\" \"\" getfsent(3)\n.xx \"system descriptor file entry.\" \"getfsent, getfsspec,\" \"getfsfile, getfstype, setfsent, endfsent: get file\" \"\" getfsent(3)\n.xx \"endfsent: get file system descriptor/\" \"getfsent,\" \"getfsspec, getfsfile, getfstype, setfsent,\" \"\" getfsent(3)\n.xx \"descriptor file/\" \"getfsent, getfsspec, getfsfile,\" \"getfstype, setfsent, endfsent: get file system\" \"\" getfsent(3)\n.xx \"\" \"getuid,\" \"getgid: get user or group ID of the caller.\" \"\" getuid(3F)\n.xx \"\" \"\" \"getgid, getegid: get group identity.\" \"\" getgid(2)\n.xx \"get group file entry.\" \"\" \"getgrent, getgrgid, getgrnam, setgrent, endgrent:\" \"\" getgrent(3)\n.xx \"file entry.\" \"getgrent,\" \"getgrgid, getgrnam, setgrent, endgrent: get group\" \"\" getgrent(3)\n.xx \"\" \"getgrent, getgrgid,\" \"getgrnam, setgrent, endgrent: get group file entry.\" \"\" getgrent(3)\n.xx \"\" \"\" \"getgroups: get group access list.\" \"\" getgroups(2)\n.xx \"get network host entry.\" \"gethostbyname,\" \"gethostbyaddr, gethostent, sethostent, endhostent:\" \"\" gethostbyname(3N)\n.xx \"sethostent, endhostent: get network host entry.\" \"\" \"gethostbyname, gethostbyaddr, gethostent,\" \"\" gethostbyname(3N)\n.xx \"host entry.\" \"gethostbyname, gethostbyaddr,\" \"gethostent, sethostent, endhostent: get network\" \"\" gethostbyname(3N)\n.xx \"current host.\" \"\" \"gethostid, sethostid: get/set unique identifier of\" \"\" gethostid(2)\n.xx \"host.\" \"\" \"gethostname, sethostname: get/set name of current\" \"\" gethostname(2)\n.xx \"timer.\" \"\" \"getitimer, setitimer: get/set value of interval\" \"\" getitimer(2)\n.xx \"\" \"\" \"getlog: get user's login name.\" \"\" getlog(3F)\n.xx \"\" \"\" \"getlogin: get login name.\" \"\" getlogin(3)\n.xx \"get network entry.\" \"getnetent,\" \"getnetbyaddr, getnetbyname, setnetent, endnetent:\" \"\" getnetent(3N)\n.xx \"entry.\" \"getnetent, getnetbyaddr,\" \"getnetbyname, setnetent, endnetent: get network\" \"\" getnetent(3N)\n.xx \"endnetent: get network entry.\" \"\" \"getnetent, getnetbyaddr, getnetbyname, setnetent,\" \"\" getnetent(3N)\n.xx \"\" \"\" \"getopt: get option letter from argv.\" \"\" getopt(3)\n.xx \"\" \"\" \"getpagesize: get system page size.\" \"\" getpagesize(2)\n.xx \"\" \"\" \"getpass: read a password.\" \"\" getpass(3)\n.xx \"\" \"\" \"getpeername: get name of connected peer.\" \"\" getpeername(2)\n.xx \"\" \"\" \"getpgrp: get process group.\" \"\" getpgrp(2)\n.xx \"\" \"\" \"getpid: get process id.\" \"\" getpid(3F)\n.xx \"\" \"\" \"getpid, getppid: get process identification.\" \"\" getpid(2)\n.xx \"\" \"getpid,\" \"getppid: get process identification.\" \"\" getpid(2)\n.xx \"scheduling priority.\" \"\" \"getpriority, setpriority: get/set program\" \"\" getpriority(2)\n.xx \"protocol entry.\" \"getprotoent, getprotobynumber,\" \"getprotobyname, setprotoent, endprotoent: get\" \"\" getprotoent(3N)\n.xx \"endprotoent: get protocol entry.\" \"getprotoent,\" \"getprotobynumber, getprotobyname, setprotoent,\" \"\" getprotoent(3N)\n.xx \"setprotoent, endprotoent: get protocol entry.\" \"\" \"getprotoent, getprotobynumber, getprotobyname,\" \"\" getprotoent(3N)\n.xx \"\" \"\" \"getpw: get name from uid.\" \"\" getpw(3C)\n.xx \"setpwfile: get password file entry.\" \"\" \"getpwent, getpwuid, getpwnam, setpwent, endpwent,\" \"\" getpwent(3)\n.xx \"password file entry.\" \"getpwent, getpwuid,\" \"getpwnam, setpwent, endpwent, setpwfile: get\" \"\" getpwent(3)\n.xx \"get password file entry.\" \"getpwent,\" \"getpwuid, getpwnam, setpwent, endpwent, setpwfile:\" \"\" getpwent(3)\n.xx \"resource consumption.\" \"\" \"getrlimit, setrlimit: control maximum system\" \"\" getrlimit(2)\n.xx \"utilization.\" \"\" \"getrusage: get information about resource\" \"\" getrusage(2)\n.xx \"\" \"\" \"gets, fgets: get a string from a stream.\" \"\" gets(3S)\n.xx \"entry.\" \"getservent, getservbyport,\" \"getservbyname, setservent, endservent: get service\" \"\" getservent(3N)\n.xx \"endservent: get service entry.\" \"getservent,\" \"getservbyport, getservbyname, setservent,\" \"\" getservent(3N)\n.xx \"setservent, endservent: get service entry.\" \"\" \"getservent, getservbyport, getservbyname,\" \"\" getservent(3N)\n.xx \"\" \"gettimeofday, settimeofday:\" \"get/set date and time.\" \"\" gettimeofday(2)\n.xx \"\" \"gethostname, sethostname:\" \"get/set name of current host.\" \"\" gethostname(2)\n.xx \"\" \"getpriority, setpriority:\" \"get/set program scheduling priority.\" \"\" getpriority(2)\n.xx \"\" \"gethostid, sethostid:\" \"get/set unique identifier of current host.\" \"\" gethostid(2)\n.xx \"\" \"getitimer, setitimer:\" \"get/set value of interval timer.\" \"\" getitimer(2)\n.xx \"\" \"\" \"getsockname: get socket name.\" \"\" getsockname(2)\n.xx \"sockets.\" \"\" \"getsockopt, setsockopt: get and set options on\" \"\" getsockopt(2)\n.xx \"\" \"\" \"gettable: get NIC format host tables from a host.\" \"\" gettable(8C)\n.xx \"\" \"\" \"gettimeofday, settimeofday: get/set date and time.\" \"\" gettimeofday(2)\n.xx \"ttys file entry.\" \"\" \"getttyent, getttynam, setttyent, endttyent: get\" \"\" getttyent(3)\n.xx \"entry.\" \"getttyent,\" \"getttynam, setttyent, endttyent: get ttys file\" \"\" getttyent(3)\n.xx \"\" \"\" \"getty: set terminal mode.\" \"\" getty(8)\n.xx \"\" \"\" \"gettytab: terminal configuration data base.\" \"\" gettytab(5)\n.xx \"\" \"\" \"getuid, geteuid: get user identity.\" \"\" getuid(2)\n.xx \"\" \"\" \"getuid, getgid: get user or group ID of the caller.\" \"\" getuid(3F)\n.xx \"user shells.\" \"\" \"getusershell, setusershell, endusershell: get legal\" \"\" getusershell(3)\n.xx \"\" \"getc, getchar, fgetc,\" \"getw: get character or word from stream.\" \"\" getc(3S)\n.xx \"\" \"\" \"getwd: get current working directory pathname.\" \"\" getwd(3)\n.xx \"\" \"head:\" \"give first few lines.\" \"\" head(1)\n.xx \"\" \"shutdown: close down the system at a\" \"given time.\" \"\" shutdown(8)\n.xx \"\" \"\" \"glob: filename expand argument list.\" \"\" csh(1)\n.xx \"ASCII.\" \"ctime, localtime,\" \"gmtime, asctime, timezone: convert date and time to\" \"\" ctime(3)\n.xx \"\" \"time, ctime, ltime,\" \"gmtime: return system time.\" \"\" time(3F)\n.xx \"\" \"fish: play\" \"``Go Fish''.\" \"\" fish(6)\n.xx \"\" \"setjmp, longjmp: non-local\" \"goto.\" \"\" setjmp(3)\n.xx \"\" \"\" \"goto: command transfer.\" \"\" csh(1)\n.xx \"\" \"\" \"gprof: display call graph profile data.\" \"\" gprof(1)\n.xx \"\" \"graph: draw a\" \"graph.\" \"\" graph(1G)\n.xx \"\" \"\" \"graph: draw a graph.\" \"\" graph(1G)\n.xx \"\" \"gprof: display call\" \"graph profile data.\" \"\" gprof(1)\n.xx \"\" \"ik: Ikonas frame buffer,\" \"graphics device interface.\" \"\" ik(4)\n.xx \"\" \"ps: Evans and Sutherland Picture System 2\" \"graphics device interface.\" \"\" ps(4)\n.xx \"\" \"plot:\" \"graphics filters.\" \"\" plot(1G)\n.xx \"\" \"arc, move, cont, point, linemod, space, closepl:\" \"graphics interface.\" \"/erase, label, line, circle,\" plot(3X)\n.xx \"\" \"plot:\" \"graphics interface.\" \"\" plot(5)\n.xx \"\" \"lib2648: subroutines for the HP 2648\" \"graphics terminal.\" \"\" lib2648(3X)\n.xx \"\" \"\" \"grep, egrep, fgrep: search a file for a pattern.\" \"\" grep(1)\n.xx \"\" \"vgrind:\" \"grind nice listings of programs.\" \"\" vgrind(1)\n.xx \"\" \"chgrp: change\" \"group.\" \"\" chgrp(1)\n.xx \"\" \"getpgrp: get process\" \"group.\" \"\" getpgrp(2)\n.xx \"\" \"killpg: send signal to a process\" \"group.\" \"\" killpg(2)\n.xx \"\" \"setpgrp: set process\" \"group.\" \"\" setpgrp(2)\n.xx \"\" \"getgroups: get\" \"group access list.\" \"\" getgroups(2)\n.xx \"\" \"initgroups: initialize\" \"group access list.\" \"\" initgroups(3)\n.xx \"\" \"setgroups: set\" \"group access list.\" \"\" setgroups(2)\n.xx \"\" \"group:\" \"group file.\" \"\" group(5)\n.xx \"\" \"getgrgid, getgrnam, setgrent, endgrent: get\" \"group file entry.\" \"getgrent,\" getgrent(3)\n.xx \"\" \"\" \"group: group file.\" \"\" group(5)\n.xx \"\" \"setregid: set real and effective\" \"group ID.\" \"\" setregid(2)\n.xx \"\" \"setruid, setgid, setegid, setrgid: set user and\" \"group ID.\" \"setuid, seteuid,\" setuid(3)\n.xx \"\" \"getuid, getgid: get user or\" \"group ID of the caller.\" \"\" getuid(3F)\n.xx \"\" \"getgid, getegid: get\" \"group identity.\" \"\" getgid(2)\n.xx \"\" \"groups: show\" \"group memberships.\" \"\" groups(1)\n.xx \"\" \"chown: change owner and\" \"group of a file.\" \"\" chown(2)\n.xx \"\" \"make: maintain program\" \"groups.\" \"\" make(1)\n.xx \"\" \"\" \"groups: show group memberships.\" \"\" groups(1)\n.xx \"\" \"worm: Play the\" \"growing worm game.\" \"\" worm(6)\n.xx \"\" \"stty,\" \"gtty: set and get terminal state (defunct).\" \"\" stty(3C)\n.xx \"\" \"stop:\" \"halt a job or process.\" \"\" csh(1)\n.xx \"\" \"reboot: reboot system or\" \"halt processor.\" \"\" reboot(2)\n.xx \"\" \"\" \"halt: stop the processor.\" \"\" halt(8)\n.xx \"\" \"rmail:\" \"handle remote mail received via uucp.\" \"\" rmail(1)\n.xx \"\" \"mh: Message\" \"Handler.\" \"\" mh(1)\n.xx \"\" \"re_comp, re_exec: regular expression\" \"handler.\" \"\" regex(3)\n.xx \"\" \"hangman: Computer version of the game\" \"hangman.\" \"\" hangman(6)\n.xx \"\" \"\" \"hangman: Computer version of the game hangman.\" \"\" hangman(6)\n.xx \"\" \"vhangup: virtually\" \"``hangup'' the current control terminal.\" \"\" vhangup(2)\n.xx \"\" \"nohup: run command immune to\" \"hangups.\" \"\" csh(1)\n.xx \"\" \"crash: what\" \"happens when the system crashes.\" \"\" crash(8V)\n.xx \"\" \"link: make a\" \"hard link to a file.\" \"\" link(2)\n.xx \"\" \"intro: introduction to special files and\" \"hardware support.\" \"\" intro(4)\n.xx \"\" \"rehash: recompute command\" \"hash table.\" \"\" csh(1)\n.xx \"\" \"unhash: discard command\" \"hash table.\" \"\" csh(1)\n.xx \"\" \"mkhosts: generate\" \"hashed host table.\" \"\" mkhosts(8)\n.xx \"\" \"mkpasswd: generate\" \"hashed password table.\" \"\" mkpasswd(8)\n.xx \"\" \"hashstat: print command\" \"hashing statistics.\" \"\" csh(1)\n.xx \"\" \"\" \"hashstat: print command hashing statistics.\" \"\" csh(1)\n.xx \"\" \"leave: remind you when you\" \"have to leave.\" \"\" leave(1)\n.xx \"\" \"\" \"hdh: ACC IF-11/HDH IMP interface.\" \"\" hdh(4)\n.xx \"\" \"od: octal, decimal,\" \"hex, ascii dump.\" \"\" od(1)\n.xx \"\" \"\" \"hier: file system hierarchy.\" \"\" hier(7)\n.xx \"\" \"hier: file system\" \"hierarchy.\" \"\" hier(7)\n.xx \"\" \"history: print\" \"history event list.\" \"\" csh(1)\n.xx \"\" \"\" \"history: print history event list.\" \"\" csh(1)\n.xx \"\" \"\" \"hk: RK6-11/RK06 and RK07 moving head disk.\" \"\" hk(4)\n.xx \"\" \"fortune: print a random,\" \"hopefully interesting, adage.\" \"\" fortune(6)\n.xx \"\" \"sethostid: get/set unique identifier of current\" \"host.\" \"gethostid,\" gethostid(2)\n.xx \"\" \"gethostname, sethostname: get/set name of current\" \"host.\" \"\" gethostname(2)\n.xx \"\" \"gettable: get NIC format host tables from a\" \"host.\" \"\" gettable(8C)\n.xx \"\" \"hostnm: get name of current\" \"host.\" \"\" hostnm(3F)\n.xx \"\" \"uusend: send a file to a remote\" \"host.\" \"\" uusend(1C)\n.xx \"\" \"htonl, htons, ntohl, ntohs: convert values between\" \"host and network byte order.\" \"\" byteorder(3N)\n.xx \"\" \"L.sys: UUCP remote\" \"host description file.\" \"\" L.sys(5)\n.xx \"\" \"remote: remote\" \"host description file.\" \"\" remote(5)\n.xx \"\" \"gethostent, sethostent, endhostent: get network\" \"host entry.\" \"gethostbyname, gethostbyaddr,\" gethostbyname(3N)\n.xx \"\" \"hosts:\" \"host name data base.\" \"\" hosts(5)\n.xx \"\" \"phones: remote\" \"host phone number data base.\" \"\" phones(5)\n.xx \"\" \"ruptime: show\" \"host status of local machines.\" \"\" ruptime(1C)\n.xx \"\" \"hostid: set or print identifier of current\" \"host system.\" \"\" hostid(1)\n.xx \"\" \"hostname: set or print name of current\" \"host system.\" \"\" hostname(1)\n.xx \"\" \"mkhosts: generate hashed\" \"host table.\" \"\" mkhosts(8)\n.xx \"\" \"htable: convert NIC standard format\" \"host tables.\" \"\" htable(8)\n.xx \"\" \"gettable: get NIC format\" \"host tables from a host.\" \"\" gettable(8C)\n.xx \"system.\" \"\" \"hostid: set or print identifier of current host\" \"\" hostid(1)\n.xx \"\" \"L.aliases: UUCP\" \"hostname alias file.\" \"\" L.aliases(5)\n.xx \"\" \"\" \"hostname: set or print name of current host system.\" \"\" hostname(1)\n.xx \"\" \"\" \"hostnm: get name of current host.\" \"\" hostnm(3F)\n.xx \"\" \"ping: send ICMP ECHO_REQUEST packets to network\" \"hosts.\" \"\" ping(8)\n.xx \"\" \"uuname: list names of UUCP\" \"hosts.\" \"\" uuname(1C)\n.xx \"\" \"\" \"hosts: host name data base.\" \"\" hosts(5)\n.xx \"\" \"uptime: show\" \"how long system has been up.\" \"\" uptime(1)\n.xx \"\" \"format:\" \"how to format disk packs.\" \"\" format(8V)\n.xx \"\" \"lib2648: subroutines for the\" \"HP 2648 graphics terminal.\" \"\" lib2648(3X)\n.xx \"\" \"\" \"hp: MASSBUS disk interface.\" \"\" hp(4)\n.xx \"interface.\" \"\" \"ht: TM-03/TE-16,TU-45,TU-77 MASSBUS magtape\" \"\" ht(4)\n.xx \"\" \"\" \"htable: convert NIC standard format host tables.\" \"\" htable(8)\n.xx \"host and network byte order.\" \"\" \"htonl, htons, ntohl, ntohs: convert values between\" \"\" byteorder(3N)\n.xx \"and network byte order.\" \"htonl,\" \"htons, ntohl, ntohs: convert values between host\" \"\" byteorder(3N)\n.xx \"\" \"\" \"hunt: a multi-player multi-terminal game.\" \"\" hunt(6)\n.xx \"\" \"wump: the game of\" \"hunt-the-wumpus.\" \"\" wump(6)\n.xx \"\" \"\" \"hy: Network Systems Hyperchannel interface.\" \"\" hy(4)\n.xx \"\" \"asinh, acosh, atanh: inverse\" \"hyperbolic functions.\" \"\" asinh(3M)\n.xx \"\" \"sinh, cosh, tanh:\" \"hyperbolic functions.\" \"\" sinh(3M)\n.xx \"\" \"hy: Network Systems\" \"Hyperchannel interface.\" \"\" hy(4)\n.xx \"value.\" \"\" \"hypot, cabs: Euclidean distance, complex absolute\" \"\" hypot(3M)\n.xx \"\" \"vacation: return\" \"``I am on vacation'' indication.\" \"\" vacation(1)\n.xx \"\" \"getarg,\" \"iargc: return command line arguments.\" \"\" getarg(3F)\n.xx \"\" \"mset: retrieve ASCII to\" \"IBM 3270 keyboard map.\" \"\" mset(1)\n.xx \"\" \"map3270: database for mapping ascii keystrokes into\" \"IBM 3270 keys.\" \"\" map3270(5)\n.xx \"\" \"tn3270: full-screen remote login to\" \"IBM VM/CMS.\" \"\" tn3270(1)\n.xx \"\" \"\" \"icheck: file system storage consistency check.\" \"\" icheck(8)\n.xx \"\" \"ping: send\" \"ICMP ECHO_REQUEST packets to network hosts.\" \"\" ping(8)\n.xx \"\" \"\" \"icmp: Internet Control Message Protocol.\" \"\" icmp(4P)\n.xx \"\" \"getpid: get process\" \"id.\" \"\" getpid(3F)\n.xx \"\" \"setregid: set real and effective group\" \"ID.\" \"\" setregid(2)\n.xx \"\" \"setgid, setegid, setrgid: set user and group\" \"ID.\" \"setuid, seteuid, setruid,\" setuid(3)\n.xx \"\" \"whoami: print effective current user\" \"id.\" \"\" whoami(1)\n.xx \"\" \"getuid, getgid: get user or group\" \"ID of the caller.\" \"\" getuid(3F)\n.xx \"\" \"su: substitute user\" \"id temporarily.\" \"\" su(1)\n.xx \"form.\" \"\" \"idate, itime: return date or time in numerical\" \"\" idate(3F)\n.xx \"\" \"getpid, getppid: get process\" \"identification.\" \"\" getpid(2)\n.xx \"\" \"gethostid, sethostid: get/set unique\" \"identifier of current host.\" \"\" gethostid(2)\n.xx \"\" \"hostid: set or print\" \"identifier of current host system.\" \"\" hostid(1)\n.xx \"\" \"getgid, getegid: get group\" \"identity.\" \"\" getgid(2)\n.xx \"\" \"getuid, geteuid: get user\" \"identity.\" \"\" getuid(2)\n.xx \"\" \"\" \"idp: Xerox Internet Datagram Protocol.\" \"\" idp(4P)\n.xx \"\" \"setreuid: set real and effective user\" \"ID's.\" \"\" setreuid(2)\n.xx \"\" \"perror, gerror,\" \"ierrno: get system error messages.\" \"\" perror(3F)\n.xx \"\" \"\" \"if: conditional statement.\" \"\" csh(1)\n.xx \"\" \"biff: be notified\" \"if mail arrives and who it is from.\" \"\" biff(1)\n.xx \"eval, exec, exit, export, login,/\" \"sh, for, case,\" \"if, while, \\fB:\\fP, \\fB.\\fP, break, continue, cd,\" \"\" sh(1)\n.xx \"\" \"hdh: ACC\" \"IF-11/HDH IMP interface.\" \"\" hdh(4)\n.xx \"\" \"\" \"ifconfig: configure network interface parameters.\" \"\" ifconfig(8C)\n.xx \"\" \"unifdef: remove\" \"ifdef'ed lines.\" \"\" unifdef(1)\n.xx \"\" \"uu: TU58/DECtape\" \"II UNIBUS cassette interface.\" \"\" uu(4)\n.xx \"\" \"\" \"ik: Ikonas frame buffer, graphics device interface.\" \"\" ik(4)\n.xx \"\" \"ik:\" \"Ikonas frame buffer, graphics device interface.\" \"\" ik(4)\n.xx \"\" \"\" \"il: Interlan NI1010 10 Mb/s Ethernet interface.\" \"\" il(4)\n.xx \"\" \"core: format of memory\" \"image file.\" \"\" core(5)\n.xx \"\" \"gcore: get core\" \"images of running processes.\" \"\" gcore(1)\n.xx \"\" \"notify: request\" \"immediate notification.\" \"\" csh(1)\n.xx \"\" \"nohup: run command\" \"immune to hangups.\" \"\" csh(1)\n.xx \"\" \"\" \"imp: 1822 network interface.\" \"\" imp(4)\n.xx \"\" \"\" \"imp: IMP raw socket interface.\" \"\" imp(4P)\n.xx \"\" \"acc: ACC LH/DH\" \"IMP interface.\" \"\" acc(4)\n.xx \"\" \"css: DEC IMP-11A LH/DH\" \"IMP interface.\" \"\" css(4)\n.xx \"\" \"ddn: DDN Standard Mode X.25\" \"IMP interface.\" \"\" ddn(4)\n.xx \"\" \"hdh: ACC IF-11/HDH\" \"IMP interface.\" \"\" hdh(4)\n.xx \"\" \"implog:\" \"IMP log interpreter.\" \"\" implog(8C)\n.xx \"\" \"implogd:\" \"IMP logger process.\" \"\" implogd(8C)\n.xx \"\" \"imp:\" \"IMP raw socket interface.\" \"\" imp(4P)\n.xx \"\" \"css: DEC\" \"IMP-11A LH/DH IMP interface.\" \"\" css(4)\n.xx \"\" \"xstr: extract strings from C programs to\" \"implement shared strings.\" \"\" xstr(1)\n.xx \"\" \"\" \"implog: IMP log interpreter.\" \"\" implog(8C)\n.xx \"\" \"\" \"implogd: IMP logger process.\" \"\" implogd(8C)\n.xx \"\" \"which: locate a program file\" \"including aliases and paths (\\fIcsh\\fR only).\" \"\" which(1)\n.xx \"\" \"fsync: synchronize a file's\" \"in-core state with that on disk.\" \"\" fsync(2)\n.xx \"\" \"dump, dumpdates:\" \"incremental dump format.\" \"\" dump(5)\n.xx \"\" \"dump:\" \"incremental file system dump.\" \"\" dump(8)\n.xx \"\" \"restore:\" \"incremental file system restore.\" \"\" restore(8)\n.xx \"\" \"indent:\" \"indent and format C program source.\" \"\" indent(1)\n.xx \"\" \"\" \"indent: indent and format C program source.\" \"\" indent(1)\n.xx \"\" \"tgetnum, tgetflag, tgetstr, tgoto, tputs: terminal\" \"independent operation routines.\" \"tgetent,\" termcap(3X)\n.xx \"\" \"ptx: permuted\" \"index.\" \"\" ptx(1)\n.xx \"\" \"L-dialcodes: UUCP phone number\" \"index file.\" \"\" L-dialcodes(5)\n.xx \"bibliography.\" \"indxbib, lookbib: build inverted\" \"index for a bibliography, find references in a\" \"\" lookbib(1)\n.xx \"objects.\" \"\" \"index, rindex, lnblnk, len: tell about character\" \"\" index(3F)\n.xx \"\" \"strncat, strcmp, strncmp, strcpy, strncpy, strlen,\" \"index, rindex: string operations.\" \"strcat,\" string(3)\n.xx \"\" \"last:\" \"indicate last logins of users and teletypes.\" \"\" last(1)\n.xx \"\" \"vacation: return ``I am on vacation''\" \"indication.\" \"\" vacation(1)\n.xx \"\" \"syscall:\" \"indirect system call.\" \"\" syscall(2)\n.xx \"\" \"fsplit: split a multi-routine Fortran file into\" \"individual files.\" \"\" fsplit(1)\n.xx \"bibliography, find references in a bibliography.\" \"\" \"indxbib, lookbib: build inverted index for a\" \"\" lookbib(1)\n.xx \"\" \"\" \"inet: Internet protocol family.\" \"\" inet(4F)\n.xx \"inet_lnaof, inet_netof: Internet address/\" \"\" \"inet_addr, inet_network, inet_ntoa, inet_makeaddr,\" \"\" inet(3N)\n.xx \"\" \"\" \"inetd: internet ``super\\-server''.\" \"\" inetd(8)\n.xx \"\" \"inet_addr, inet_network, inet_ntoa, inet_makeaddr,\" \"inet_lnaof, inet_netof: Internet address/\" \"\" inet(3N)\n.xx \"address/\" \"inet_addr, inet_network, inet_ntoa,\" \"inet_makeaddr, inet_lnaof, inet_netof: Internet\" \"\" inet(3N)\n.xx \"\" \"/inet_network, inet_ntoa, inet_makeaddr, inet_lnaof,\" \"inet_netof: Internet address manipulation routines.\" \"\" inet(3N)\n.xx \"inet_netof: Internet address/\" \"inet_addr,\" \"inet_network, inet_ntoa, inet_makeaddr, inet_lnaof,\" \"\" inet(3N)\n.xx \"Internet address/\" \"inet_addr, inet_network,\" \"inet_ntoa, inet_makeaddr, inet_lnaof, inet_netof:\" \"\" inet(3N)\n.xx \"on a VAX (temporary).\" \"\" \"infnan: signals invalid floating-point operations\" \"\" infnan(3M)\n.xx \"\" \"bad144: read/write dec standard 144 bad sector\" \"information.\" \"\" bad144(8)\n.xx \"\" \"chfn, chsh, passwd: change password file\" \"information.\" \"\" chfn(1)\n.xx \"\" \"chfn, chsh, passwd: change password file\" \"information.\" \"\" chsh(1)\n.xx \"\" \"dbx: dbx symbol table\" \"information.\" \"\" dbx(5)\n.xx \"\" \"dumpfs: dump file system\" \"information.\" \"\" dumpfs(8)\n.xx \"\" \"pac: printer/plotter accounting\" \"information.\" \"\" pac(8)\n.xx \"\" \"chfn, chsh, passwd: change password file\" \"information.\" \"\" passwd(1)\n.xx \"\" \"getrusage: get\" \"information about resource utilization.\" \"\" getrusage(2)\n.xx \"\" \"vtimes: get\" \"information about resource utilization.\" \"\" vtimes(3C)\n.xx \"\" \"fstab: static\" \"information about the filesystems.\" \"\" fstab(5)\n.xx \"\" \"man: find manual\" \"information by keywords; print out the manual.\" \"\" man(1)\n.xx \"\" \"finger: user\" \"information lookup program.\" \"\" finger(1)\n.xx \"\" \"miscellaneous: miscellaneous useful\" \"information pages.\" \"\" intro(7)\n.xx \"\" \"XNSrouted: NS Routing\" \"Information Protocol daemon.\" \"\" XNSrouted(8C)\n.xx \"\" \"fingerd: remote user\" \"information server.\" \"\" fingerd(8C)\n.xx \"\" \"\" \"init: process control initialization.\" \"\" init(8)\n.xx \"\" \"\" \"initgroups: initialize group access list.\" \"\" initgroups(3)\n.xx \"\" \"init: process control\" \"initialization.\" \"\" init(8)\n.xx \"\" \"ioinit: change f77 I/O\" \"initialization.\" \"\" ioinit(3F)\n.xx \"\" \"tset: terminal dependent\" \"initialization.\" \"\" tset(1)\n.xx \"\" \"ttys: terminal\" \"initialization data.\" \"\" ttys(5)\n.xx \"\" \"initgroups:\" \"initialize group access list.\" \"\" initgroups(3)\n.xx \"\" \"connect:\" \"initiate a connection on a socket.\" \"\" connect(2)\n.xx \"\" \"popen, pclose:\" \"initiate I/O to/from a process.\" \"\" popen(3)\n.xx \"generator; routines for changing/\" \"random, srandom,\" \"initstate, setstate: better random number\" \"\" random(3)\n.xx \"\" \"flmin, flmax, ffrac, dflmin, dflmax, dffrac,\" \"inmax: return extreme values.\" \"\" flmin(3F)\n.xx \"\" \"clri: clear\" \"i-node.\" \"\" clri(8)\n.xx \"\" \"fs,\" \"inode: format of file system volume.\" \"\" fs(5)\n.xx \"\" \"read, readv: read\" \"input.\" \"\" read(2)\n.xx \"\" \"soelim: eliminate \\&.so's from nroff\" \"input.\" \"\" soelim(1)\n.xx \"\" \"scanf, fscanf, sscanf: formatted\" \"input conversion.\" \"\" scanf(3S)\n.xx \"\" \"ungetc: push character back into\" \"input stream.\" \"\" ungetc(3S)\n.xx \"\" \"fread, fwrite: buffered binary\" \"input/output.\" \"\" fread(3S)\n.xx \"\" \"stdio: standard buffered\" \"input/output package.\" \"\" stdio(3S)\n.xx \"\" \"ferror, feof, clearerr, fileno: stream status\" \"inquiries.\" \"\" ferror(3S)\n.xx \"\" \"refer: find and\" \"insert literature references in documents.\" \"\" refer(1)\n.xx \"\" \"insque, remque:\" \"insert/remove element from a queue.\" \"\" insque(3)\n.xx \"\" \"\" \"insque, remque: insert/remove element from a queue.\" \"\" insque(3)\n.xx \"\" \"install:\" \"install binaries.\" \"\" install(1)\n.xx \"\" \"\" \"install: install binaries.\" \"\" install(1)\n.xx \"\" \"learn: computer aided\" \"instruction about UNIX.\" \"\" learn(1)\n.xx \"\" \"doctor:\" \"interact with a psychoanalyst.\" \"\" doctor(6)\n.xx \"\" \"jove: an\" \"interactive display-oriented text editor.\" \"\" jove(1)\n.xx \"\" \"fsck: file system consistency check and\" \"interactive repair.\" \"\" fsck(8)\n.xx \"\" \"fortune: print a random, hopefully\" \"interesting, adage.\" \"\" fortune(6)\n.xx \"\" \"acc: ACC LH/DH IMP\" \"interface.\" \"\" acc(4)\n.xx \"\" \"cons: VAX-11 console\" \"interface.\" \"\" cons(4)\n.xx \"\" \"crl: VAX 8600 console RL02\" \"interface.\" \"\" crl(4)\n.xx \"\" \"css: DEC IMP-11A LH/DH IMP\" \"interface.\" \"\" css(4)\n.xx \"\" \"ct: phototypesetter\" \"interface.\" \"\" ct(4)\n.xx \"\" \"ddn: DDN Standard Mode X.25 IMP\" \"interface.\" \"\" ddn(4)\n.xx \"\" \"de: DEC DEUNA 10 Mb/s Ethernet\" \"interface.\" \"\" de(4)\n.xx \"\" \"dn: DN-11 autocall unit\" \"interface.\" \"\" dn(4)\n.xx \"\" \"ec: 3Com 10 Mb/s Ethernet\" \"interface.\" \"\" ec(4)\n.xx \"\" \"en: Xerox 3 Mb/s Ethernet\" \"interface.\" \"\" en(4)\n.xx \"\" \"ex: Excelan 10 Mb/s Ethernet\" \"interface.\" \"\" ex(4)\n.xx \"\" \"fl: console floppy\" \"interface.\" \"\" fl(4)\n.xx \"\" \"hdh: ACC IF-11/HDH IMP\" \"interface.\" \"\" hdh(4)\n.xx \"\" \"hp: MASSBUS disk\" \"interface.\" \"\" hp(4)\n.xx \"\" \"ht: TM-03/TE-16,TU-45,TU-77 MASSBUS magtape\" \"interface.\" \"\" ht(4)\n.xx \"\" \"hy: Network Systems Hyperchannel\" \"interface.\" \"\" hy(4)\n.xx \"\" \"ik: Ikonas frame buffer, graphics device\" \"interface.\" \"\" ik(4)\n.xx \"\" \"il: Interlan NI1010 10 Mb/s Ethernet\" \"interface.\" \"\" il(4)\n.xx \"\" \"imp: 1822 network\" \"interface.\" \"\" imp(4)\n.xx \"\" \"imp: IMP raw socket\" \"interface.\" \"\" imp(4P)\n.xx \"\" \"ix: Interlan Np100 10 Mb/s Ethernet\" \"interface.\" \"\" ix(4)\n.xx \"\" \"lo: software loopback network\" \"interface.\" \"\" lo(4)\n.xx \"\" \"mt: TM78/TU-78 MASSBUS magtape\" \"interface.\" \"\" mt(4)\n.xx \"\" \"mtio: UNIX magtape\" \"interface.\" \"\" mtio(4)\n.xx \"\" \"np: Interlan Np100 10 Mb/s Ethernet\" \"interface.\" \"\" np(4)\n.xx \"\" \"pcl: DEC CSS PCL-11 B Network\" \"Interface.\" \"\" pcl(4)\n.xx \"\" \"cont, point, linemod, space, closepl: graphics\" \"interface.\" \"/erase, label, line, circle, arc, move,\" plot(3X)\n.xx \"\" \"plot: graphics\" \"interface.\" \"\" plot(5)\n.xx \"\" \"and Sutherland Picture System 2 graphics device\" \"interface.\" \"ps: Evans\" ps(4)\n.xx \"\" \"qe: DEC DEQNA Q-bus 10 Mb/s Ethernet\" \"interface.\" \"\" qe(4)\n.xx \"\" \"rx: DEC RX02 floppy disk\" \"interface.\" \"\" rx(4)\n.xx \"\" \"tm: TM-11/TE-10 magtape\" \"interface.\" \"\" tm(4)\n.xx \"\" \"tmscp: DEC TMSCP magtape\" \"interface.\" \"\" tmscp(4)\n.xx \"\" \"ts: TS-11 magtape\" \"interface.\" \"\" ts(4)\n.xx \"\" \"tty: general terminal\" \"interface.\" \"\" tty(4)\n.xx \"\" \"tu: VAX-11/730 and VAX-11/750 TU58 console cassette\" \"interface.\" \"\" tu(4)\n.xx \"\" \"uda: UDA-50 disk controller\" \"interface.\" \"\" uda(4)\n.xx \"\" \"ut: UNIBUS TU45 tri-density tape drive\" \"interface.\" \"\" ut(4)\n.xx \"\" \"uu: TU58/DECtape II UNIBUS cassette\" \"interface.\" \"\" uu(4)\n.xx \"\" \"va: Benson-Varian\" \"interface.\" \"\" va(4)\n.xx \"\" \"vp: Versatec\" \"interface.\" \"\" vp(4)\n.xx \"\" \"nsip: software network\" \"interface encapsulating ns packets in ip packets..\" \"\" nsip(4)\n.xx \"\" \"ifconfig: configure network\" \"interface parameters.\" \"\" ifconfig(8C)\n.xx \"\" \"plot: openpl et al.: f77 library\" \"interface to \\fIplot\\fR (3X) libraries..\" \"\" plot(3F)\n.xx \"\" \"telnet: user\" \"interface to the TELNET protocol.\" \"\" telnet(1C)\n.xx \"\" \"slattach: attach serial lines as network\" \"interfaces.\" \"\" slattach(8C)\n.xx \"\" \"il:\" \"Interlan NI1010 10 Mb/s Ethernet interface.\" \"\" il(4)\n.xx \"\" \"ix:\" \"Interlan Np100 10 Mb/s Ethernet interface.\" \"\" ix(4)\n.xx \"\" \"np:\" \"Interlan Np100 10 Mb/s Ethernet interface.\" \"\" np(4)\n.xx \"\" \"swapon: add a swap device for\" \"interleaved paging/swapping.\" \"\" swapon(2)\n.xx \"\" \"sendmail: send mail over the\" \"internet.\" \"\" sendmail(8)\n.xx \"\" \"/inet_ntoa, inet_makeaddr, inet_lnaof, inet_netof:\" \"Internet address manipulation routines.\" \"\" inet(3N)\n.xx \"\" \"icmp:\" \"Internet Control Message Protocol.\" \"\" icmp(4P)\n.xx \"\" \"idp: Xerox\" \"Internet Datagram Protocol.\" \"\" idp(4P)\n.xx \"\" \"named:\" \"Internet domain name server.\" \"\" named(8)\n.xx \"\" \"ftpd: DARPA\" \"Internet File Transfer Protocol server.\" \"\" ftpd(8C)\n.xx \"\" \"ip:\" \"Internet Protocol.\" \"\" ip(4P)\n.xx \"\" \"inet:\" \"Internet protocol family.\" \"\" inet(4F)\n.xx \"\" \"inetd:\" \"internet ``super\\-server''.\" \"\" inetd(8)\n.xx \"\" \"tcp:\" \"Internet Transmission Control Protocol.\" \"\" tcp(4P)\n.xx \"\" \"udp:\" \"Internet User Datagram Protocol.\" \"\" udp(4P)\n.xx \"\" \"whois: DARPA\" \"Internet user name directory service.\" \"\" whois(1)\n.xx \"\" \"spline:\" \"interpolate smooth curve.\" \"\" spline(1G)\n.xx \"\" \"implog: IMP log\" \"interpreter.\" \"\" implog(8C)\n.xx \"\" \"lisp: lisp\" \"interpreter.\" \"\" lisp(1)\n.xx \"\" \"px: Pascal\" \"interpreter.\" \"\" px(1)\n.xx \"\" \"uuxqt: UUCP execution file\" \"interpreter.\" \"\" uuxqt(8C)\n.xx \"\" \"pix: Pascal\" \"interpreter and executor.\" \"\" pix(1)\n.xx \"\" \"pi: Pascal\" \"interpreter code translator.\" \"\" pi(1)\n.xx \"\" \"csh: a shell (command\" \"interpreter) with C-like syntax.\" \"\" csh(1)\n.xx \"\" \"pipe: create an\" \"interprocess communication channel.\" \"\" pipe(2)\n.xx \"\" \"atomically release blocked signals and wait for\" \"interrupt.\" \"sigpause:\" sigpause(2)\n.xx \"\" \"siginterrupt: allow signals to\" \"interrupt system calls.\" \"\" siginterrupt(3)\n.xx \"\" \"onintr: process\" \"interrupts in command scripts.\" \"\" csh(1)\n.xx \"\" \"intro:\" \"introduction to C library functions.\" \"\" intro(3)\n.xx \"\" \"intro:\" \"introduction to commands.\" \"\" intro(1)\n.xx \"\" \"intro:\" \"introduction to FORTRAN library functions.\" \"\" intro(3F)\n.xx \"\" \"math:\" \"introduction to mathematical library functions.\" \"\" math(3M)\n.xx \"\" \"networking:\" \"introduction to networking facilities.\" \"\" intro(4N)\n.xx \"\" \"rcsintro:\" \"introduction to RCS commands.\" \"\" rcsintro(1)\n.xx \"\" \"intro:\" \"introduction to special files and hardware support.\" \"\" intro(4)\n.xx \"\" \"intro:\" \"introduction to system calls and error numbers.\" \"\" intro(2)\n.xx \"commands.\" \"intro:\" \"introduction to system maintenance and operation\" \"\" intro(8)\n.xx \"\" \"ncheck: generate names from\" \"i-numbers.\" \"\" ncheck(8)\n.xx \"(temporary).\" \"infnan: signals\" \"invalid floating-point operations on a VAX\" \"\" infnan(3M)\n.xx \"\" \"asinh, acosh, atanh:\" \"inverse hyperbolic functions.\" \"\" asinh(3M)\n.xx \"\" \"atan, atan2: trigonometric functions and their\" \"inverses.\" \"sin, cos, tan, asin, acos,\" sin(3M)\n.xx \"m_in, mout,/\" \"madd, msub, mult, mdiv, pow, gcd,\" \"invert, rpow, msqrt, mcmp, move, min, omin, fmin,\" \"\" mp(3X)\n.xx \"in a bibliography.\" \"indxbib, lookbib: build\" \"inverted index for a bibliography, find references\" \"\" lookbib(1)\n.xx \"\" \"tread, twrite, trewin, tskipf, tstate: f77 tape\" \"I/O.\" \"topen, tclose,\" topen(3F)\n.xx \"\" \"ioinit: change f77\" \"I/O initialization.\" \"\" ioinit(3F)\n.xx \"\" \"select: synchronous\" \"I/O multiplexing.\" \"\" select(2)\n.xx \"\" \"iostat: report\" \"I/O statistics.\" \"\" iostat(1)\n.xx \"\" \"popen, pclose: initiate\" \"I/O to/from a process.\" \"\" popen(3)\n.xx \"\" \"\" \"ioctl: control device.\" \"\" ioctl(2)\n.xx \"\" \"\" \"ioinit: change f77 I/O initialization.\" \"\" ioinit(3F)\n.xx \"\" \"\" \"iostat: report I/O statistics.\" \"\" iostat(1)\n.xx \"\" \"\" \"ip: Internet Protocol.\" \"\" ip(4P)\n.xx \"\" \"network interface encapsulating ns packets in\" \"ip packets..\" \"nsip: software\" nsip(4)\n.xx \"\" \"rand, drand,\" \"irand: return random values.\" \"\" rand(3F)\n.xx \"\" \"random, drandm,\" \"irandm: better random number generator.\" \"\" random(3F)\n.xx \"\" \"sail: multi-user wooden ships and\" \"iron men.\" \"\" sail(6)\n.xx \"\" \"isalpha, isupper, islower, isdigit, isxdigit,\" \"isalnum, isspace, ispunct, isprint, isgraph,/\" \"\" ctype(3)\n.xx \"isalnum, isspace, ispunct, isprint, isgraph,/\" \"\" \"isalpha, isupper, islower, isdigit, isxdigit,\" \"\" ctype(3)\n.xx \"\" \"/isspace, ispunct, isprint, isgraph, iscntrl,\" \"isascii, toupper, tolower, toascii: character/\" \"\" ctype(3)\n.xx \"\" \"ttynam,\" \"isatty: find name of a terminal port.\" \"\" ttynam(3F)\n.xx \"\" \"ttyname,\" \"isatty, ttyslot: find name of a terminal.\" \"\" ttyname(3)\n.xx \"\" \"/isalnum, isspace, ispunct, isprint, isgraph,\" \"iscntrl, isascii, toupper, tolower, toascii:/\" \"\" ctype(3)\n.xx \"isprint, isgraph,/\" \"isalpha, isupper, islower,\" \"isdigit, isxdigit, isalnum, isspace, ispunct,\" \"\" ctype(3)\n.xx \"\" \"/isxdigit, isalnum, isspace, ispunct, isprint,\" \"isgraph, iscntrl, isascii, toupper, tolower,/\" \"\" ctype(3)\n.xx \"ispunct, isprint, isgraph,/\" \"isalpha, isupper,\" \"islower, isdigit, isxdigit, isalnum, isspace,\" \"\" ctype(3)\n.xx \"\" \"/isdigit, isxdigit, isalnum, isspace, ispunct,\" \"isprint, isgraph, iscntrl, isascii, toupper,/\" \"\" ctype(3)\n.xx \"\" \"/islower, isdigit, isxdigit, isalnum, isspace,\" \"ispunct, isprint, isgraph, iscntrl, isascii,/\" \"\" ctype(3)\n.xx \"\" \"/isupper, islower, isdigit, isxdigit, isalnum,\" \"isspace, ispunct, isprint, isgraph, iscntrl,/\" \"\" ctype(3)\n.xx \"\" \"system:\" \"issue a shell command.\" \"\" system(3)\n.xx \"isspace, ispunct, isprint, isgraph,/\" \"isalpha,\" \"isupper, islower, isdigit, isxdigit, isalnum,\" \"\" ctype(3)\n.xx \"isgraph,/\" \"isalpha, isupper, islower, isdigit,\" \"isxdigit, isalnum, isspace, ispunct, isprint,\" \"\" ctype(3)\n.xx \"\" \"formatter; list bibliographic reference\" \"items.\" \"bib, listrefs: bibliographic\" bib(1)\n.xx \"\" \"idate,\" \"itime: return date or time in numerical form.\" \"\" idate(3F)\n.xx \"\" \"omin, fmin, m_in, mout, omout, fmout, m_out, sdiv,\" \"itom: multiple precision integer arithmetic.\" \"/min,\" mp(3X)\n.xx \"\" \"\" \"ix: Interlan Np100 10 Mb/s Ethernet interface.\" \"\" ix(4)\n.xx \"\" \"\" \"j0, j1, jn, y0, y1, yn: bessel functions.\" \"\" j0(3M)\n.xx \"\" \"j0,\" \"j1, jn, y0, y1, yn: bessel functions.\" \"\" j0(3M)\n.xx \"\" \"j0, j1,\" \"jn, y0, y1, yn: bessel functions.\" \"\" j0(3M)\n.xx \"\" \"bg: place\" \"job in background.\" \"\" csh(1)\n.xx \"\" \"fg: bring\" \"job into foreground.\" \"\" csh(1)\n.xx \"\" \"jobs: print current\" \"job list.\" \"\" csh(1)\n.xx \"\" \"stop: halt a\" \"job or process.\" \"\" csh(1)\n.xx \"\" \"kill: kill\" \"jobs and processes.\" \"\" csh(1)\n.xx \"\" \"lprm: remove\" \"jobs from the line printer spooling queue.\" \"\" lprm(1)\n.xx \"\" \"\" \"jobs: print current job list.\" \"\" csh(1)\n.xx \"\" \"atrm: remove\" \"jobs spooled by at.\" \"\" atrm(1)\n.xx \"\" \"atq: print the queue of\" \"jobs waiting to be run.\" \"\" atq(1)\n.xx \"\" \"\" \"join: relational database operator.\" \"\" join(1)\n.xx \"\" \"\" \"jove: an interactive display-oriented text editor.\" \"\" jove(1)\n.xx \"\" \"msgs: system messages and\" \"junk mail program.\" \"\" msgs(1)\n.xx \"\" \"makekey: generate encryption\" \"key.\" \"\" makekey(8)\n.xx \"\" \"mset: retrieve ASCII to IBM 3270\" \"keyboard map.\" \"\" mset(1)\n.xx \"\" \"database for mapping ascii keystrokes into IBM 3270\" \"keys.\" \"map3270:\" map3270(5)\n.xx \"\" \"map3270: database for mapping ascii\" \"keystrokes into IBM 3270 keys.\" \"\" map3270(5)\n.xx \"\" \"apropos: locate commands by\" \"keyword lookup.\" \"\" apropos(1)\n.xx \"\" \"man: find manual information by\" \"keywords; print out the manual.\" \"\" man(1)\n.xx \"\" \"\" \"kg: KL-11/DL-11W line clock.\" \"\" kg(4)\n.xx \"profile buffers.\" \"\" \"kgmon: generate a dump of the operating system's\" \"\" kgmon(8)\n.xx \"\" \"kill:\" \"kill jobs and processes.\" \"\" csh(1)\n.xx \"\" \"\" \"kill: kill jobs and processes.\" \"\" csh(1)\n.xx \"\" \"\" \"kill: send a signal to a process.\" \"\" kill(3F)\n.xx \"\" \"\" \"kill: send signal to a process.\" \"\" kill(2)\n.xx \"\" \"\" \"kill: terminate a process with extreme prejudice.\" \"\" kill(1)\n.xx \"\" \"\" \"killpg: send signal to a process group.\" \"\" killpg(2)\n.xx \"\" \"bessel functions: of two\" \"kinds for integer orders.\" \"\" bessel(3F)\n.xx \"\" \"kg:\" \"KL-11/DL-11W line clock.\" \"\" kg(4)\n.xx \"\" \"mem,\" \"kmem: main memory.\" \"\" mem(4)\n.xx \"linemod, space, closepl:/\" \"plot: openpl, erase,\" \"label, line, circle, arc, move, cont, point,\" \"\" plot(3X)\n.xx \"\" \"\" \"L.aliases: UUCP hostname alias file.\" \"\" L.aliases(5)\n.xx \"\" \"awk: pattern scanning and processing\" \"language.\" \"\" awk(1)\n.xx \"\" \"bc: arbitrary-precision arithmetic\" \"language.\" \"\" bc(1)\n.xx \"\" \"efl: Extended Fortran\" \"Language.\" \"\" efl(1)\n.xx \"\" \"set, shift, times, trap, umask, wait: command\" \"language.\" \"/exit, export, login, read, readonly,\" sh(1)\n.xx \"\" \"fp: Functional Programming\" \"language compiler/interpreter.\" \"\" fp(1)\n.xx \"\" \"vgrindefs: vgrind's\" \"language definition data base.\" \"\" vgrindefs(5)\n.xx \"order.\" \"\" \"lastcomm: show last commands executed in reverse\" \"\" lastcomm(1)\n.xx \"\" \"\" \"L.cmds: UUCP remote command permissions file.\" \"\" L.cmds(5)\n.xx \"\" \"\" \"ld: link editor.\" \"\" ld(1)\n.xx \"\" \"\" \"L-devices: UUCP device description file.\" \"\" L-devices(5)\n.xx \"\" \"frexp,\" \"ldexp, modf: split into mantissa and exponent.\" \"\" frexp(3)\n.xx \"\" \"\" \"L-dialcodes: UUCP phone number index file.\" \"\" L-dialcodes(5)\n.xx \"\" \"\" \"learn: computer aided instruction about UNIX.\" \"\" learn(1)\n.xx \"\" \"leave: remind you when you have to\" \"leave.\" \"\" leave(1)\n.xx \"\" \"\" \"leave: remind you when you have to leave.\" \"\" leave(1)\n.xx \"\" \"exit:\" \"leave shell.\" \"\" csh(1)\n.xx \"\" \"getusershell, setusershell, endusershell: get\" \"legal user shells.\" \"\" getusershell(3)\n.xx \"\" \"index, rindex, lnblnk,\" \"len: tell about character objects.\" \"\" index(3F)\n.xx \"\" \"truncate: truncate a file to a specified\" \"length.\" \"\" truncate(2)\n.xx \"\" \"getopt: get option\" \"letter from argv.\" \"\" getopt(3)\n.xx \"\" \"\" \"lex: generator of lexical analysis programs.\" \"\" lex(1)\n.xx \"\" \"lex: generator of\" \"lexical analysis programs.\" \"\" lex(1)\n.xx \"\" \"\" \"lgamma: log gamma function.\" \"\" lgamma(3M)\n.xx \"\" \"acc: ACC\" \"LH/DH IMP interface.\" \"\" acc(4)\n.xx \"\" \"css: DEC IMP-11A\" \"LH/DH IMP interface.\" \"\" css(4)\n.xx \"terminal.\" \"\" \"lib2648: subroutines for the HP 2648 graphics\" \"\" lib2648(3X)\n.xx \"\" \"et al.: f77 library interface to \\fIplot\\fR (3X)\" \"libraries..\" \"plot: openpl\" plot(3F)\n.xx \"\" \"ranlib: convert archives to random\" \"libraries.\" \"\" ranlib(1)\n.xx \"\" \"lorder: find ordering relation for an object\" \"library.\" \"\" lorder(1)\n.xx \"\" \"ar: archive\" \"(library) file format.\" \"\" ar(5)\n.xx \"\" \"intro: introduction to C\" \"library functions.\" \"\" intro(3)\n.xx \"\" \"intro: introduction to FORTRAN\" \"library functions.\" \"\" intro(3F)\n.xx \"\" \"math: introduction to mathematical\" \"library functions.\" \"\" math(3M)\n.xx \"\" \"plot: openpl et al.: f77\" \"library interface to \\fIplot\\fR (3X) libraries..\" \"\" plot(3F)\n.xx \"\" \"ar: archive and\" \"library maintainer.\" \"\" ar(1)\n.xx \"\" \"\" \"limit: alter per-process resource limitations.\" \"\" csh(1)\n.xx \"\" \"limit: alter per-process resource\" \"limitations.\" \"\" csh(1)\n.xx \"\" \"unlimit: remove resource\" \"limitiations.\" \"\" csh(1)\n.xx \"\" \"quota: display disc usage and\" \"limits.\" \"\" quota(1)\n.xx \"\" \"getarg, iargc: return command\" \"line arguments.\" \"\" getarg(3F)\n.xx \"space, closepl:/\" \"plot: openpl, erase, label,\" \"line, circle, arc, move, cont, point, linemod,\" \"\" plot(3X)\n.xx \"\" \"kg: KL-11/DL-11W\" \"line clock.\" \"\" kg(4)\n.xx \"\" \"tb:\" \"line discipline for digitizing devices.\" \"\" tb(4)\n.xx \"(obsolete).\" \"bk:\" \"line discipline for machine-machine communication\" \"\" bk(4)\n.xx \"\" \"col: filter reverse\" \"line feeds.\" \"\" col(1)\n.xx \"\" \"sysline: display system status on status\" \"line of a terminal.\" \"\" sysline(1)\n.xx \"\" \"lpr: off\" \"line print.\" \"\" lpr(1)\n.xx \"\" \"lp:\" \"line printer.\" \"\" lp(4)\n.xx \"\" \"lpc:\" \"line printer control program.\" \"\" lpc(8)\n.xx \"\" \"lpd:\" \"line printer daemon.\" \"\" lpd(8)\n.xx \"\" \"lprm: remove jobs from the\" \"line printer spooling queue.\" \"\" lprm(1)\n.xx \"\" \"/erase, label, line, circle, arc, move, cont, point,\" \"linemod, space, closepl: graphics interface.\" \"\" plot(3X)\n.xx \"\" \"lptest: generate\" \"lineprinter ripple pattern.\" \"\" lptest(1)\n.xx \"\" \"head: give first few\" \"lines.\" \"\" head(1)\n.xx \"\" \"unifdef: remove ifdef'ed\" \"lines.\" \"\" unifdef(1)\n.xx \"\" \"slattach: attach serial\" \"lines as network interfaces.\" \"\" slattach(8C)\n.xx \"\" \"comm: select or reject\" \"lines common to two sorted files.\" \"\" comm(1)\n.xx \"\" \"fold: fold long\" \"lines for finite width output device.\" \"\" fold(1)\n.xx \"\" \"uniq: report repeated\" \"lines in a file.\" \"\" uniq(1)\n.xx \"\" \"look: find\" \"lines in a sorted list.\" \"\" look(1)\n.xx \"\" \"rev: reverse\" \"lines of a file.\" \"\" rev(1)\n.xx \"\" \"readlink: read value of a symbolic\" \"link.\" \"\" readlink(2)\n.xx \"\" \"ld:\" \"link editor.\" \"\" ld(1)\n.xx \"\" \"a.out: assembler and\" \"link editor output.\" \"\" a.out(5)\n.xx \"\" \"\" \"link: make a hard link to a file.\" \"\" link(2)\n.xx \"\" \"\" \"link: make a link to an existing file.\" \"\" link(3F)\n.xx \"\" \"link: make a hard\" \"link to a file.\" \"\" link(2)\n.xx \"\" \"symlink: make symbolic\" \"link to a file.\" \"\" symlink(2)\n.xx \"\" \"link: make a\" \"link to an existing file.\" \"\" link(3F)\n.xx \"\" \"ln: make\" \"links.\" \"\" ln(1)\n.xx \"\" \"\" \"lint: a C program verifier.\" \"\" lint(1)\n.xx \"\" \"lxref:\" \"lisp cross reference program.\" \"\" lxref(1)\n.xx \"\" \"lisp:\" \"lisp interpreter.\" \"\" lisp(1)\n.xx \"\" \"\" \"lisp: lisp interpreter.\" \"\" lisp(1)\n.xx \"\" \"liszt: compile a Franz\" \"Lisp program.\" \"\" liszt(1)\n.xx \"troff.\" \"vlp: Format\" \"Lisp programs to be printed with nroff, vtroff, or\" \"\" vlp(1)\n.xx \"\" \"glob: filename expand argument\" \"list.\" \"\" csh(1)\n.xx \"\" \"history: print history event\" \"list.\" \"\" csh(1)\n.xx \"\" \"jobs: print current job\" \"list.\" \"\" csh(1)\n.xx \"\" \"shift: manipulate argument\" \"list.\" \"\" csh(1)\n.xx \"\" \"getgroups: get group access\" \"list.\" \"\" getgroups(2)\n.xx \"\" \"initgroups: initialize group access\" \"list.\" \"\" initgroups(3)\n.xx \"\" \"look: find lines in a sorted\" \"list.\" \"\" look(1)\n.xx \"\" \"nlist: get entries from name\" \"list.\" \"\" nlist(3)\n.xx \"\" \"nm: print name\" \"list.\" \"\" nm(1)\n.xx \"\" \"setgroups: set group access\" \"list.\" \"\" setgroups(2)\n.xx \"\" \"symorder: rearrange name\" \"list.\" \"\" symorder(1)\n.xx \"\" \"varargs: variable argument\" \"list.\" \"\" varargs(3)\n.xx \"\" \"bib, listrefs: bibliographic formatter;\" \"list bibliographic reference items.\" \"\" bib(1)\n.xx \"\" \"ls:\" \"list contents of directory.\" \"\" ls(1)\n.xx \"\" \"uuname:\" \"list names of UUCP hosts.\" \"\" uuname(1C)\n.xx \"\" \"foreach: loop over\" \"list of names.\" \"\" csh(1)\n.xx \"\" \"users: compact\" \"list of users who are on the system.\" \"\" users(1)\n.xx \"\" \"listen:\" \"listen for connections on a socket.\" \"\" listen(2)\n.xx \"\" \"\" \"listen: listen for connections on a socket.\" \"\" listen(2)\n.xx \"\" \"vgrind: grind nice\" \"listings of programs.\" \"\" vgrind(1)\n.xx \"bibliographic reference items.\" \"bib,\" \"listrefs: bibliographic formatter; list\" \"\" bib(1)\n.xx \"\" \"\" \"liszt: compile a Franz Lisp program.\" \"\" liszt(1)\n.xx \"\" \"refer: find and insert\" \"literature references in documents.\" \"\" refer(1)\n.xx \"\" \"\" \"ln: make links.\" \"\" ln(1)\n.xx \"\" \"index, rindex,\" \"lnblnk, len: tell about character objects.\" \"\" index(3F)\n.xx \"\" \"\" \"lo: software loopback network interface.\" \"\" lo(4)\n.xx \"\" \"\" \"loc: return the address of an object.\" \"\" loc(3F)\n.xx \"and time to ASCII.\" \"ctime,\" \"localtime, gmtime, asctime, timezone: convert date\" \"\" ctime(3)\n.xx \"(\\fIcsh\\fR only).\" \"which:\" \"locate a program file including aliases and paths\" \"\" which(1)\n.xx \"\" \"apropos:\" \"locate commands by keyword lookup.\" \"\" apropos(1)\n.xx \"\" \"whereis:\" \"locate source, binary, and or manual for program.\" \"\" whereis(1)\n.xx \"\" \"end, etext, edata: last\" \"locations in program.\" \"\" end(3)\n.xx \"\" \"flock: apply or remove an advisory\" \"lock on an open file.\" \"\" flock(2)\n.xx \"\" \"\" \"lock: reserve a terminal.\" \"\" lock(1)\n.xx \"\" \"collect system diagnostic messages to form error\" \"log.\" \"dmesg:\" dmesg(8)\n.xx \"\" \"logger: make entries in the system\" \"log.\" \"\" logger(1)\n.xx \"\" \"openlog, closelog, setlogmask: control system\" \"log.\" \"syslog,\" syslog(3)\n.xx \"\" \"uulog: display UUCP\" \"log files.\" \"\" uulog(1C)\n.xx \"\" \"lgamma:\" \"log gamma function.\" \"\" lgamma(3M)\n.xx \"\" \"implog: IMP\" \"log interpreter.\" \"\" implog(8C)\n.xx \"power.\" \"exp, expm1,\" \"log, log10, log1p, pow: exponential, logarithm,\" \"\" exp(3M)\n.xx \"\" \"syslogd:\" \"log systems messages.\" \"\" syslogd(8)\n.xx \"\" \"exp, expm1, log,\" \"log10, log1p, pow: exponential, logarithm, power.\" \"\" exp(3M)\n.xx \"\" \"exp, expm1, log, log10,\" \"log1p, pow: exponential, logarithm, power.\" \"\" exp(3M)\n.xx \"\" \"exp, expm1, log, log10, log1p, pow: exponential,\" \"logarithm, power.\" \"\" exp(3M)\n.xx \"manipulations.\" \"copysign, drem, finite,\" \"logb, scalb: copysign, remainder, exponent\" \"\" ieee(3M)\n.xx \"\" \"rwho: who's\" \"logged in on local machines.\" \"\" rwho(1C)\n.xx \"\" \"\" \"logger: make entries in the system log.\" \"\" logger(1)\n.xx \"\" \"implogd: IMP\" \"logger process.\" \"\" implogd(8C)\n.xx \"\" \"flush: flush output to a\" \"logical unit.\" \"\" flush(3F)\n.xx \"\" \"fseek, ftell: reposition a file on a\" \"logical unit.\" \"\" fseek(3F)\n.xx \"\" \"getc, fgetc: get a character from a\" \"logical unit.\" \"\" getc(3F)\n.xx \"\" \"putc, fputc: write a character to a fortran\" \"logical unit.\" \"\" putc(3F)\n.xx \"\" \"rlogin: remote\" \"login.\" \"\" rlogin(1C)\n.xx \"\" \"ac:\" \"login accounting.\" \"\" ac(8)\n.xx \"\" \"\" \"login: login new user.\" \"\" csh(1)\n.xx \"\" \"getlog: get user's\" \"login name.\" \"\" getlog(3F)\n.xx \"\" \"getlogin: get\" \"login name.\" \"\" getlogin(3)\n.xx \"\" \"login:\" \"login new user.\" \"\" csh(1)\n.xx \"\" \"/break, continue, cd, eval, exec, exit, export,\" \"login, read, readonly, set, shift, times, trap,/\" \"\" sh(1)\n.xx \"\" \"utmp, wtmp:\" \"login records.\" \"\" utmp(5)\n.xx \"\" \"rlogind: remote\" \"login server.\" \"\" rlogind(8C)\n.xx \"\" \"\" \"login: sign on.\" \"\" login(1)\n.xx \"\" \"tn3270: full-screen remote\" \"login to IBM VM/CMS.\" \"\" tn3270(1)\n.xx \"\" \"last: indicate last\" \"logins of users and teletypes.\" \"\" last(1)\n.xx \"\" \"\" \"logout: end session.\" \"\" csh(1)\n.xx \"\" \"setjmp,\" \"longjmp: non-local goto.\" \"\" setjmp(3)\n.xx \"\" \"\" \"look: find lines in a sorted list.\" \"\" look(1)\n.xx \"find references in a bibliography.\" \"indxbib,\" \"lookbib: build inverted index for a bibliography,\" \"\" lookbib(1)\n.xx \"\" \"apropos: locate commands by keyword\" \"lookup.\" \"\" apropos(1)\n.xx \"\" \"finger: user information\" \"lookup program.\" \"\" finger(1)\n.xx \"\" \"break: exit while/foreach\" \"loop.\" \"\" csh(1)\n.xx \"\" \"continue: cycle in\" \"loop.\" \"\" csh(1)\n.xx \"\" \"end: terminate\" \"loop.\" \"\" csh(1)\n.xx \"\" \"foreach:\" \"loop over list of names.\" \"\" csh(1)\n.xx \"\" \"lo: software\" \"loopback network interface.\" \"\" lo(4)\n.xx \"library.\" \"\" \"lorder: find ordering relation for an object\" \"\" lorder(1)\n.xx \"\" \"mklost+found: make a\" \"lost+found directory for fsck.\" \"\" mklost+found(8)\n.xx \"\" \"\" \"lp: line printer.\" \"\" lp(4)\n.xx \"\" \"\" \"lpc: line printer control program.\" \"\" lpc(8)\n.xx \"\" \"\" \"lpd: line printer daemon.\" \"\" lpd(8)\n.xx \"\" \"\" \"lpq: spool queue examination program.\" \"\" lpq(1)\n.xx \"\" \"\" \"lpr: off line print.\" \"\" lpr(1)\n.xx \"queue.\" \"\" \"lprm: remove jobs from the line printer spooling\" \"\" lprm(1)\n.xx \"\" \"\" \"lptest: generate lineprinter ripple pattern.\" \"\" lptest(1)\n.xx \"\" \"\" \"ls: list contents of directory.\" \"\" ls(1)\n.xx \"\" \"\" \"lseek: move read/write pointer.\" \"\" lseek(2)\n.xx \"\" \"bit: and, or, xor, not, rshift,\" \"lshift bitwise functions.\" \"\" bit(3F)\n.xx \"\" \"stat,\" \"lstat, fstat: get file status.\" \"\" stat(2)\n.xx \"\" \"stat,\" \"lstat, fstat: get file status.\" \"\" stat(3F)\n.xx \"\" \"\" \"L.sys: UUCP remote host description file.\" \"\" L.sys(5)\n.xx \"\" \"time, ctime,\" \"ltime, gmtime: return system time.\" \"\" time(3F)\n.xx \"\" \"\" \"lxref: lisp cross reference program.\" \"\" lxref(1)\n.xx \"\" \"\" \"m4: macro processor.\" \"\" m4(1)\n.xx \"\" \"bk: line discipline for\" \"machine-machine communication (obsolete).\" \"\" bk(4)\n.xx \"\" \"ruptime: show host status of local\" \"machines.\" \"\" ruptime(1C)\n.xx \"\" \"rwho: who's logged in on local\" \"machines.\" \"\" rwho(1C)\n.xx \"\" \"m4:\" \"macro processor.\" \"\" m4(1)\n.xx \"\" \"alias: shell\" \"macros.\" \"\" csh(1)\n.xx \"\" \"toupper, tolower, toascii: character classification\" \"macros.\" \"/isprint, isgraph, iscntrl, isascii,\" ctype(3)\n.xx \"\" \"ms: text formatting\" \"macros.\" \"\" ms(7)\n.xx \"\" \"me:\" \"macros for formatting papers.\" \"\" me(7)\n.xx \"\" \"man:\" \"macros to typeset manual.\" \"\" man(7)\n.xx \"msqrt, mcmp, move, min, omin, fmin, m_in, mout,/\" \"\" \"madd, msub, mult, mdiv, pow, gcd, invert, rpow,\" \"\" mp(3X)\n.xx \"\" \"tcopy: copy a\" \"mag tape.\" \"\" tcopy(1)\n.xx \"\" \"mt:\" \"magnetic tape manipulating program.\" \"\" mt(1)\n.xx \"\" \"ht: TM-03/TE-16,TU-45,TU-77 MASSBUS\" \"magtape interface.\" \"\" ht(4)\n.xx \"\" \"mt: TM78/TU-78 MASSBUS\" \"magtape interface.\" \"\" mt(4)\n.xx \"\" \"mtio: UNIX\" \"magtape interface.\" \"\" mtio(4)\n.xx \"\" \"tm: TM-11/TE-10\" \"magtape interface.\" \"\" tm(4)\n.xx \"\" \"tmscp: DEC TMSCP\" \"magtape interface.\" \"\" tmscp(4)\n.xx \"\" \"ts: TS-11\" \"magtape interface.\" \"\" ts(4)\n.xx \"\" \"rmt: remote\" \"magtape protocol module.\" \"\" rmt(8C)\n.xx \"\" \"mail: send and receive\" \"mail.\" \"\" mail(1)\n.xx \"\" \"encode/decode a binary file for transmission via\" \"mail.\" \"uuencode, uudecode:\" uuencode(1C)\n.xx \"\" \"xsend, xget, enroll: secret\" \"mail.\" \"\" xsend(1)\n.xx \"\" \"sendbug:\" \"mail a system bug report to 4bsd-bugs.\" \"\" sendbug(1)\n.xx \"\" \"mailaddr:\" \"mail addressing description.\" \"\" mailaddr(7)\n.xx \"\" \"newaliases: rebuild the data base for the\" \"mail aliases file.\" \"\" newaliases(1)\n.xx \"\" \"binmail: send or receive\" \"mail among users.\" \"\" binmail(1)\n.xx \"\" \"biff: be notified if\" \"mail arrives and who it is from.\" \"\" biff(1)\n.xx \"\" \"from: who is my\" \"mail from?.\" \"\" from(1)\n.xx \"\" \"sendmail: send\" \"mail over the internet.\" \"\" sendmail(8)\n.xx \"\" \"msgs: system messages and junk\" \"mail program.\" \"\" msgs(1)\n.xx \"\" \"rmail: handle remote\" \"mail received via uucp.\" \"\" rmail(1)\n.xx \"\" \"\" \"mail: send and receive mail.\" \"\" mail(1)\n.xx \"\" \"\" \"mailaddr: mail addressing description.\" \"\" mailaddr(7)\n.xx \"\" \"mem, kmem:\" \"main memory.\" \"\" mem(4)\n.xx \"\" \"make:\" \"maintain program groups.\" \"\" make(1)\n.xx \"\" \"ar: archive and library\" \"maintainer.\" \"\" ar(1)\n.xx \"\" \"intro: introduction to system\" \"maintenance and operation commands.\" \"\" intro(8)\n.xx \"\" \"mkdir:\" \"make a directory.\" \"\" mkdir(1)\n.xx \"\" \"mkdir:\" \"make a directory file.\" \"\" mkdir(2)\n.xx \"\" \"link:\" \"make a hard link to a file.\" \"\" link(2)\n.xx \"\" \"link:\" \"make a link to an existing file.\" \"\" link(3F)\n.xx \"\" \"mklost+found:\" \"make a lost+found directory for fsck.\" \"\" mklost+found(8)\n.xx \"\" \"mknod:\" \"make a special file.\" \"\" mknod(2)\n.xx \"\" \"mktemp:\" \"make a unique file name.\" \"\" mktemp(3)\n.xx \"\" \"logger:\" \"make entries in the system log.\" \"\" logger(1)\n.xx \"\" \"ln:\" \"make links.\" \"\" ln(1)\n.xx \"\" \"\" \"make: maintain program groups.\" \"\" make(1)\n.xx \"\" \"symlink:\" \"make symbolic link to a file.\" \"\" symlink(2)\n.xx \"\" \"makedev:\" \"make system special files.\" \"\" makedev(8)\n.xx \"\" \"vwidth:\" \"make troff width table for a font.\" \"\" vwidth(1)\n.xx \"\" \"script:\" \"make typescript of terminal session.\" \"\" script(1)\n.xx \"\" \"\" \"makedev: make system special files.\" \"\" makedev(8)\n.xx \"\" \"\" \"makekey: generate encryption key.\" \"\" makekey(8)\n.xx \"\" \"\" \"malloc, free, falloc: memory allocator.\" \"\" malloc(3F)\n.xx \"allocator.\" \"\" \"malloc, free, realloc, calloc, alloca: memory\" \"\" malloc(3)\n.xx \"the manual.\" \"\" \"man: find manual information by keywords; print out\" \"\" man(1)\n.xx \"\" \"\" \"man: macros to typeset manual.\" \"\" man(7)\n.xx \"\" \"shift:\" \"manipulate argument list.\" \"\" csh(1)\n.xx \"\" \"quota:\" \"manipulate disk quotas.\" \"\" quota(2)\n.xx \"\" \"tp:\" \"manipulate tape archive.\" \"\" tp(1)\n.xx \"\" \"route: manually\" \"manipulate the routing tables.\" \"\" route(8C)\n.xx \"\" \"uuq: examine or\" \"manipulate the uucp queue.\" \"\" uuq(1C)\n.xx \"\" \"mt: magnetic tape\" \"manipulating program.\" \"\" mt(1)\n.xx \"\" \"inet_lnaof, inet_netof: Internet address\" \"manipulation routines.\" \"/inet_ntoa, inet_makeaddr,\" inet(3N)\n.xx \"\" \"finite, logb, scalb: copysign, remainder, exponent\" \"manipulations.\" \"copysign, drem,\" ieee(3M)\n.xx \"\" \"frexp, ldexp, modf: split into\" \"mantissa and exponent.\" \"\" frexp(3)\n.xx \"\" \"catman: create the cat files for the\" \"manual.\" \"\" catman(8)\n.xx \"\" \"find manual information by keywords; print out the\" \"manual.\" \"man:\" man(1)\n.xx \"\" \"man: macros to typeset\" \"manual.\" \"\" man(7)\n.xx \"\" \"whereis: locate source, binary, and or\" \"manual for program.\" \"\" whereis(1)\n.xx \"manual.\" \"man: find\" \"manual information by keywords; print out the\" \"\" man(1)\n.xx \"\" \"route:\" \"manually manipulate the routing tables.\" \"\" route(8C)\n.xx \"IBM 3270 keys.\" \"\" \"map3270: database for mapping ascii keystrokes into\" \"\" map3270(5)\n.xx \"\" \"map3270: database for\" \"mapping ascii keystrokes into IBM 3270 keys.\" \"\" map3270(5)\n.xx \"\" \"umask: change or display file creation\" \"mask.\" \"\" csh(1)\n.xx \"\" \"sigsetmask: set current signal\" \"mask.\" \"\" sigsetmask(2)\n.xx \"\" \"umask: set file creation mode\" \"mask.\" \"\" umask(2)\n.xx \"\" \"mkstr: create an error message file by\" \"massaging C source.\" \"\" mkstr(1)\n.xx \"\" \"hp:\" \"MASSBUS disk interface.\" \"\" hp(4)\n.xx \"\" \"ht: TM-03/TE-16,TU-45,TU-77\" \"MASSBUS magtape interface.\" \"\" ht(4)\n.xx \"\" \"mt: TM78/TU-78\" \"MASSBUS magtape interface.\" \"\" mt(4)\n.xx \"functions.\" \"\" \"math: introduction to mathematical library\" \"\" math(3M)\n.xx \"\" \"math: introduction to\" \"mathematical library functions.\" \"\" math(3M)\n.xx \"\" \"eqn, neqn, checkeq: typeset\" \"mathematics.\" \"\" eqn(1)\n.xx \"\" \"getrlimit, setrlimit: control\" \"maximum system resource consumption.\" \"\" getrlimit(2)\n.xx \"\" \"vlimit: control\" \"maximum system resource consumption.\" \"\" vlimit(3C)\n.xx \"\" \"de: DEC DEUNA 10\" \"Mb/s Ethernet interface.\" \"\" de(4)\n.xx \"\" \"ec: 3Com 10\" \"Mb/s Ethernet interface.\" \"\" ec(4)\n.xx \"\" \"en: Xerox 3\" \"Mb/s Ethernet interface.\" \"\" en(4)\n.xx \"\" \"ex: Excelan 10\" \"Mb/s Ethernet interface.\" \"\" ex(4)\n.xx \"\" \"il: Interlan NI1010 10\" \"Mb/s Ethernet interface.\" \"\" il(4)\n.xx \"\" \"ix: Interlan Np100 10\" \"Mb/s Ethernet interface.\" \"\" ix(4)\n.xx \"\" \"np: Interlan Np100 10\" \"Mb/s Ethernet interface.\" \"\" np(4)\n.xx \"\" \"qe: DEC DEQNA Q-bus 10\" \"Mb/s Ethernet interface.\" \"\" qe(4)\n.xx \"\" \"/msub, mult, mdiv, pow, gcd, invert, rpow, msqrt,\" \"mcmp, move, min, omin, fmin, m_in, mout, omout,/\" \"\" mp(3X)\n.xx \"min, omin, fmin, m_in, mout,/\" \"madd, msub, mult,\" \"mdiv, pow, gcd, invert, rpow, msqrt, mcmp, move,\" \"\" mp(3X)\n.xx \"\" \"\" \"me: macros for formatting papers.\" \"\" me(7)\n.xx \"\" \"bcd: convert to antique\" \"media.\" \"\" bcd(6)\n.xx \"\" \"vv: Proteon proNET 10\" \"Megabit ring.\" \"\" vv(4)\n.xx \"\" \"\" \"mem, kmem: main memory.\" \"\" mem(4)\n.xx \"\" \"groups: show group\" \"memberships.\" \"\" groups(1)\n.xx \"\" \"mem, kmem: main\" \"memory.\" \"\" mem(4)\n.xx \"\" \"malloc, free, realloc, calloc, alloca:\" \"memory allocator.\" \"\" malloc(3)\n.xx \"\" \"malloc, free, falloc:\" \"memory allocator.\" \"\" malloc(3F)\n.xx \"\" \"valloc: aligned\" \"memory allocator.\" \"\" valloc(3C)\n.xx \"\" \"vfork: spawn new process in a virtual\" \"memory efficient way.\" \"\" vfork(2)\n.xx \"\" \"core: format of\" \"memory image file.\" \"\" core(5)\n.xx \"\" \"vmstat: report virtual\" \"memory statistics.\" \"\" vmstat(1)\n.xx \"\" \"sail: multi-user wooden ships and iron\" \"men.\" \"\" sail(6)\n.xx \"\" \"sort: sort or\" \"merge files.\" \"\" sort(1)\n.xx \"\" \"pmerge: pascal file\" \"merger.\" \"\" pmerge(1)\n.xx \"\" \"\" \"mesg: permit or deny messages.\" \"\" mesg(1)\n.xx \"\" \"mkstr: create an error\" \"message file by massaging C source.\" \"\" mkstr(1)\n.xx \"\" \"recv, recvfrom, recvmsg: receive a\" \"message from a socket.\" \"\" recv(2)\n.xx \"\" \"send, sendto, sendmsg: send a\" \"message from a socket.\" \"\" send(2)\n.xx \"\" \"mh:\" \"Message Handler.\" \"\" mh(1)\n.xx \"\" \"icmp: Internet Control\" \"Message Protocol.\" \"\" icmp(4P)\n.xx \"\" \"error: analyze and disperse compiler error\" \"messages.\" \"\" error(1)\n.xx \"\" \"mesg: permit or deny\" \"messages.\" \"\" mesg(1)\n.xx \"\" \"perror, sys_errlist, sys_nerr: system error\" \"messages.\" \"\" perror(3)\n.xx \"\" \"perror, gerror, ierrno: get system error\" \"messages.\" \"\" perror(3F)\n.xx \"\" \"psignal, sys_siglist: system signal\" \"messages.\" \"\" psignal(3)\n.xx \"\" \"syslogd: log systems\" \"messages.\" \"\" syslogd(8)\n.xx \"\" \"msgs: system\" \"messages and junk mail program.\" \"\" msgs(1)\n.xx \"\" \"dmesg: collect system diagnostic\" \"messages to form error log.\" \"\" dmesg(8)\n.xx \"\" \"\" \"mh: Message Handler.\" \"\" mh(1)\n.xx \"\" \"mille: play\" \"Mille Bournes.\" \"\" mille(6)\n.xx \"\" \"\" \"mille: play Mille Bournes.\" \"\" mille(6)\n.xx \"\" \"invert, rpow, msqrt, mcmp, move, min, omin, fmin,\" \"m_in, mout, omout, fmout, m_out, sdiv, itom:/\" \"/gcd,\" mp(3X)\n.xx \"\" \"/mdiv, pow, gcd, invert, rpow, msqrt, mcmp, move,\" \"min, omin, fmin, m_in, mout, omout, fmout, m_out,/\" \"\" mp(3X)\n.xx \"pages.\" \"\" \"miscellaneous: miscellaneous useful information\" \"\" intro(7)\n.xx \"\" \"miscellaneous:\" \"miscellaneous useful information pages.\" \"\" intro(7)\n.xx \"\" \"\" \"mkdir: make a directory.\" \"\" mkdir(1)\n.xx \"\" \"\" \"mkdir: make a directory file.\" \"\" mkdir(2)\n.xx \"\" \"\" \"mkfs: construct a file system.\" \"\" mkfs(8)\n.xx \"\" \"\" \"mkhosts: generate hashed host table.\" \"\" mkhosts(8)\n.xx \"\" \"\" \"mklost+found: make a lost+found directory for fsck.\" \"\" mklost+found(8)\n.xx \"\" \"\" \"mknod: build special file.\" \"\" mknod(8)\n.xx \"\" \"\" \"mknod: make a special file.\" \"\" mknod(2)\n.xx \"\" \"\" \"mkpasswd: generate hashed password table.\" \"\" mkpasswd(8)\n.xx \"\" \"\" \"mkproto: construct a prototype file system.\" \"\" mkproto(8)\n.xx \"source.\" \"\" \"mkstr: create an error message file by massaging C\" \"\" mkstr(1)\n.xx \"\" \"\" \"mktemp: make a unique file name.\" \"\" mktemp(3)\n.xx \"\" \"chmod: change\" \"mode.\" \"\" chmod(1)\n.xx \"\" \"getty: set terminal\" \"mode.\" \"\" getty(8)\n.xx \"\" \"umask: set file creation\" \"mode mask.\" \"\" umask(2)\n.xx \"\" \"chmod: change\" \"mode of a file.\" \"\" chmod(3F)\n.xx \"\" \"chmod: change\" \"mode of file.\" \"\" chmod(2)\n.xx \"\" \"ddn: DDN Standard\" \"Mode X.25 IMP interface.\" \"\" ddn(4)\n.xx \"\" \"frexp, ldexp,\" \"modf: split into mantissa and exponent.\" \"\" frexp(3)\n.xx \"\" \"touch: update date last\" \"modified of a file.\" \"\" touch(1)\n.xx \"\" \"rmt: remote magtape protocol\" \"module.\" \"\" rmt(8C)\n.xx \"\" \"up: unibus storage\" \"module controller/drives.\" \"\" up(4)\n.xx \"\" \"what: show what versions of object\" \"modules were used to construct a file.\" \"\" what(1)\n.xx \"\" \"monitor, monstartup,\" \"moncontrol: prepare execution profile.\" \"\" monitor(3)\n.xx \"profile.\" \"\" \"monitor, monstartup, moncontrol: prepare execution\" \"\" monitor(3)\n.xx \"\" \"\" \"monop: Monopoly game.\" \"\" monop(6)\n.xx \"\" \"monop:\" \"Monopoly game.\" \"\" monop(6)\n.xx \"\" \"monitor,\" \"monstartup, moncontrol: prepare execution profile.\" \"\" monitor(3)\n.xx \"\" \"\" \"more, page: file perusal filter for crt viewing.\" \"\" more(1)\n.xx \"\" \"curses: screen functions with ``optimal'' cursor\" \"motion.\" \"\" curses(3X)\n.xx \"\" \"mount, umount:\" \"mount and dismount file system.\" \"\" mount(8)\n.xx \"\" \"mount, umount:\" \"mount or remove file system.\" \"\" mount(2)\n.xx \"\" \"\" \"mount, umount: mount and dismount file system.\" \"\" mount(8)\n.xx \"\" \"\" \"mount, umount: mount or remove file system.\" \"\" mount(2)\n.xx \"\" \"mtab:\" \"mounted file system table.\" \"\" mtab(5)\n.xx \"\" \"/rpow, msqrt, mcmp, move, min, omin, fmin, m_in,\" \"mout, omout, fmout, m_out, sdiv, itom: multiple/\" \"\" mp(3X)\n.xx \"\" \"/move, min, omin, fmin, m_in, mout, omout, fmout,\" \"m_out, sdiv, itom: multiple precision integer/\" \"\" mp(3X)\n.xx \"\" \"plot: openpl, erase, label, line, circle, arc,\" \"move, cont, point, linemod, space, closepl:/\" \"\" plot(3X)\n.xx \"\" \"/mult, mdiv, pow, gcd, invert, rpow, msqrt, mcmp,\" \"move, min, omin, fmin, m_in, mout, omout, fmout,/\" \"\" mp(3X)\n.xx \"\" \"mv:\" \"move or rename files.\" \"\" mv(1)\n.xx \"\" \"lseek:\" \"move read/write pointer.\" \"\" lseek(2)\n.xx \"\" \"hk: RK6-11/RK06 and RK07\" \"moving head disk.\" \"\" hk(4)\n.xx \"\" \"\" \"ms: text formatting macros.\" \"\" ms(7)\n.xx \"\" \"\" \"mset: retrieve ASCII to IBM 3270 keyboard map.\" \"\" mset(1)\n.xx \"\" \"\" \"msgs: system messages and junk mail program.\" \"\" msgs(1)\n.xx \"\" \"madd, msub, mult, mdiv, pow, gcd, invert, rpow,\" \"msqrt, mcmp, move, min, omin, fmin, m_in, mout,/\" \"\" mp(3X)\n.xx \"mcmp, move, min, omin, fmin, m_in, mout,/\" \"madd,\" \"msub, mult, mdiv, pow, gcd, invert, rpow, msqrt,\" \"\" mp(3X)\n.xx \"\" \"\" \"mt: magnetic tape manipulating program.\" \"\" mt(1)\n.xx \"\" \"\" \"mt: TM78/TU-78 MASSBUS magtape interface.\" \"\" mt(4)\n.xx \"\" \"\" \"mtab: mounted file system table.\" \"\" mtab(5)\n.xx \"\" \"\" \"mtio: UNIX magtape interface.\" \"\" mtio(4)\n.xx \"move, min, omin, fmin, m_in, mout,/\" \"madd, msub,\" \"mult, mdiv, pow, gcd, invert, rpow, msqrt, mcmp,\" \"\" mp(3X)\n.xx \"\" \"hunt: a\" \"multi-player multi-terminal game.\" \"\" hunt(6)\n.xx \"\" \"fmin, m_in, mout, omout, fmout, m_out, sdiv, itom:\" \"multiple precision integer arithmetic.\" \"/min, omin,\" mp(3X)\n.xx \"\" \"dh: DH-11/DM-11 communications\" \"multiplexer.\" \"\" dh(4)\n.xx \"\" \"dhu: DHU-11 communications\" \"multiplexer.\" \"\" dhu(4)\n.xx \"\" \"dz: DZ-11 communications\" \"multiplexer.\" \"\" dz(4)\n.xx \"\" \"select: synchronous I/O\" \"multiplexing.\" \"\" select(2)\n.xx \"\" \"dmf: DMF-32, terminal\" \"multiplexor.\" \"\" dmf(4)\n.xx \"\" \"dmz: DMZ-32 terminal\" \"multiplexor.\" \"\" dmz(4)\n.xx \"\" \"fsplit: split a\" \"multi-routine Fortran file into individual files.\" \"\" fsplit(1)\n.xx \"\" \"hunt: a multi-player\" \"multi-terminal game.\" \"\" hunt(6)\n.xx \"\" \"sail:\" \"multi-user wooden ships and iron men.\" \"\" sail(6)\n.xx \"\" \"switch:\" \"multi-way command branch.\" \"\" csh(1)\n.xx \"\" \"\" \"mv: move or rename files.\" \"\" mv(1)\n.xx \"\" \"from: who is\" \"my mail from?.\" \"\" from(1)\n.xx \"\" \"getdiskbyname: get disk description by its\" \"name.\" \"\" getdisk(3)\n.xx \"\" \"getenv: value for environment\" \"name.\" \"\" getenv(3)\n.xx \"\" \"getlog: get user's login\" \"name.\" \"\" getlog(3F)\n.xx \"\" \"getlogin: get login\" \"name.\" \"\" getlogin(3)\n.xx \"\" \"getsockname: get socket\" \"name.\" \"\" getsockname(2)\n.xx \"\" \"mktemp: make a unique file\" \"name.\" \"\" mktemp(3)\n.xx \"\" \"pwd: working directory\" \"name.\" \"\" pwd(1)\n.xx \"\" \"tty: get terminal\" \"name.\" \"\" tty(1)\n.xx \"\" \"hosts: host\" \"name data base.\" \"\" hosts(5)\n.xx \"\" \"networks: network\" \"name data base.\" \"\" networks(5)\n.xx \"\" \"protocols: protocol\" \"name data base.\" \"\" protocols(5)\n.xx \"\" \"services: service\" \"name data base.\" \"\" services(5)\n.xx \"\" \"whois: DARPA Internet user\" \"name directory service.\" \"\" whois(1)\n.xx \"\" \"getpw: get\" \"name from uid.\" \"\" getpw(3C)\n.xx \"\" \"nlist: get entries from\" \"name list.\" \"\" nlist(3)\n.xx \"\" \"nm: print\" \"name list.\" \"\" nm(1)\n.xx \"\" \"symorder: rearrange\" \"name list.\" \"\" symorder(1)\n.xx \"\" \"rename: change the\" \"name of a file.\" \"\" rename(2)\n.xx \"\" \"ttyname, isatty, ttyslot: find\" \"name of a terminal.\" \"\" ttyname(3)\n.xx \"\" \"ttynam, isatty: find\" \"name of a terminal port.\" \"\" ttynam(3F)\n.xx \"\" \"getpeername: get\" \"name of connected peer.\" \"\" getpeername(2)\n.xx \"\" \"gethostname, sethostname: get/set\" \"name of current host.\" \"\" gethostname(2)\n.xx \"\" \"hostnm: get\" \"name of current host.\" \"\" hostnm(3F)\n.xx \"\" \"hostname: set or print\" \"name of current host system.\" \"\" hostname(1)\n.xx \"\" \"named: Internet domain\" \"name server.\" \"\" named(8)\n.xx \"\" \"bind: bind a\" \"name to a socket.\" \"\" bind(2)\n.xx \"\" \"\" \"named: Internet domain name server.\" \"\" named(8)\n.xx \"\" \"foreach: loop over list of\" \"names.\" \"\" csh(1)\n.xx \"\" \"term: conventional\" \"names for terminals.\" \"\" term(7)\n.xx \"\" \"ncheck: generate\" \"names from i-numbers.\" \"\" ncheck(8)\n.xx \"\" \"uuname: list\" \"names of UUCP hosts.\" \"\" uuname(1C)\n.xx \"\" \"\" \"ncheck: generate names from i-numbers.\" \"\" ncheck(8)\n.xx \"\" \"eqn,\" \"neqn, checkeq: typeset mathematics.\" \"\" eqn(1)\n.xx \"\" \"\" \"netstat: show network status.\" \"\" netstat(1)\n.xx \"\" \"rdump: file system dump across the\" \"network.\" \"\" rdump(8C)\n.xx \"\" \"rrestore: restore a file system dump across the\" \"network.\" \"\" rrestore(8C)\n.xx \"\" \"ntohl, ntohs: convert values between host and\" \"network byte order.\" \"htonl, htons,\" byteorder(3N)\n.xx \"\" \"getnetbyname, setnetent, endnetent: get\" \"network entry.\" \"getnetent, getnetbyaddr,\" getnetent(3N)\n.xx \"\" \"gethostent, sethostent, endhostent: get\" \"network host entry.\" \"gethostbyname, gethostbyaddr,\" gethostbyname(3N)\n.xx \"\" \"ping: send ICMP ECHO_REQUEST packets to\" \"network hosts.\" \"\" ping(8)\n.xx \"\" \"imp: 1822\" \"network interface.\" \"\" imp(4)\n.xx \"\" \"lo: software loopback\" \"network interface.\" \"\" lo(4)\n.xx \"\" \"pcl: DEC CSS PCL-11 B\" \"Network Interface.\" \"\" pcl(4)\n.xx \"packets..\" \"nsip: software\" \"network interface encapsulating ns packets in ip\" \"\" nsip(4)\n.xx \"\" \"ifconfig: configure\" \"network interface parameters.\" \"\" ifconfig(8C)\n.xx \"\" \"slattach: attach serial lines as\" \"network interfaces.\" \"\" slattach(8C)\n.xx \"\" \"networks:\" \"network name data base.\" \"\" networks(5)\n.xx \"\" \"routed:\" \"network routing daemon.\" \"\" routed(8C)\n.xx \"\" \"netstat: show\" \"network status.\" \"\" netstat(1)\n.xx \"\" \"hy:\" \"Network Systems Hyperchannel interface.\" \"\" hy(4)\n.xx \"\" \"ns: Xerox\" \"Network Systems(tm) protocol family.\" \"\" ns(4F)\n.xx \"\" \"networking: introduction to\" \"networking facilities.\" \"\" intro(4N)\n.xx \"\" \"\" \"networking: introduction to networking facilities.\" \"\" intro(4N)\n.xx \"\" \"\" \"networks: network name data base.\" \"\" networks(5)\n.xx \"\" \"creat: create a\" \"new file.\" \"\" creat(2)\n.xx \"\" \"open a file for reading or writing, or create a\" \"new file.\" \"open:\" open(2)\n.xx \"\" \"newfs: construct a\" \"new file system.\" \"\" newfs(8)\n.xx \"\" \"fork: create a\" \"new process.\" \"\" fork(2)\n.xx \"\" \"vfork: spawn\" \"new process in a virtual memory efficient way.\" \"\" vfork(2)\n.xx \"\" \"login: login\" \"new user.\" \"\" csh(1)\n.xx \"\" \"adduser: procedure for adding\" \"new users.\" \"\" adduser(8)\n.xx \"aliases file.\" \"\" \"newaliases: rebuild the data base for the mail\" \"\" newaliases(1)\n.xx \"\" \"\" \"newfs: construct a new file system.\" \"\" newfs(8)\n.xx \"\" \"readnews: read\" \"news articles.\" \"\" readnews(1)\n.xx \"\" \"vnews: read\" \"news articles.\" \"\" vnews(1)\n.xx \"\" \"notes, autoseq, readnotes: a\" \"news system.\" \"\" notes(1)\n.xx \"\" \"dbminit, fetch, store, delete, firstkey,\" \"nextkey: data base subroutines.\" \"\" dbm(3X)\n.xx \"\" \"il: Interlan\" \"NI1010 10 Mb/s Ethernet interface.\" \"\" il(4)\n.xx \"\" \"gettable: get\" \"NIC format host tables from a host.\" \"\" gettable(8C)\n.xx \"\" \"htable: convert\" \"NIC standard format host tables.\" \"\" htable(8)\n.xx \"\" \"vgrind: grind\" \"nice listings of programs.\" \"\" vgrind(1)\n.xx \"(\\fIsh\\fR only).\" \"\" \"nice, nohup: run a command at low priority\" \"\" nice(1)\n.xx \"\" \"\" \"nice: run low priority process.\" \"\" csh(1)\n.xx \"\" \"\" \"nice: set program priority.\" \"\" nice(3C)\n.xx \"\" \"\" \"nlist: get entries from name list.\" \"\" nlist(3)\n.xx \"\" \"\" \"nm: print name list.\" \"\" nm(1)\n.xx \"only).\" \"nice,\" \"nohup: run a command at low priority (\\fIsh\\fR\" \"\" nice(1)\n.xx \"\" \"\" \"nohup: run command immune to hangups.\" \"\" csh(1)\n.xx \"\" \"setjmp, longjmp:\" \"non-local goto.\" \"\" setjmp(3)\n.xx \"\" \"bit: and, or, xor,\" \"not, rshift, lshift bitwise functions.\" \"\" bit(3F)\n.xx \"\" \"\" \"notes, autoseq, readnotes: a news system.\" \"\" notes(1)\n.xx \"\" \"notify: request immediate\" \"notification.\" \"\" csh(1)\n.xx \"\" \"biff: be\" \"notified if mail arrives and who it is from.\" \"\" biff(1)\n.xx \"\" \"\" \"notify: request immediate notification.\" \"\" csh(1)\n.xx \"\" \"\" \"np: Interlan Np100 10 Mb/s Ethernet interface.\" \"\" np(4)\n.xx \"\" \"ix: Interlan\" \"Np100 10 Mb/s Ethernet interface.\" \"\" ix(4)\n.xx \"\" \"np: Interlan\" \"Np100 10 Mb/s Ethernet interface.\" \"\" np(4)\n.xx \"\" \"soelim: eliminate \\&.so's from\" \"nroff input.\" \"\" soelim(1)\n.xx \"\" \"tbl: format tables for\" \"nroff or troff.\" \"\" tbl(1)\n.xx \"\" \"colcrt: filter\" \"nroff output for CRT previewing.\" \"\" colcrt(1)\n.xx \"\" \"\" \"nroff: text formatting.\" \"\" nroff(1)\n.xx \"\" \"troff,\" \"nroff: text formatting and typesetting.\" \"\" troff(1)\n.xx \"\" \"deroff: remove\" \"nroff, troff, tbl and eqn constructs.\" \"\" deroff(1)\n.xx \"\" \"vlp: Format Lisp programs to be printed with\" \"nroff, vtroff, or troff.\" \"\" vlp(1)\n.xx \"\" \"checknr: check\" \"nroff/troff files.\" \"\" checknr(1)\n.xx \"\" \"nsip: software network interface encapsulating\" \"ns packets in ip packets..\" \"\" nsip(4)\n.xx \"\" \"XNSrouted:\" \"NS Routing Information Protocol daemon.\" \"\" XNSrouted(8C)\n.xx \"\" \"\" \"ns: Xerox Network Systems(tm) protocol family.\" \"\" ns(4F)\n.xx \"routines.\" \"\" \"ns_addr, ns_ntoa: Xerox NS(tm)  address conversion\" \"\" ns(3N)\n.xx \"packets in ip packets..\" \"\" \"nsip: software network interface encapsulating ns\" \"\" nsip(4)\n.xx \"\" \"ns_addr,\" \"ns_ntoa: Xerox NS(tm)  address conversion routines.\" \"\" ns(3N)\n.xx \"\" \"ns_addr, ns_ntoa: Xerox\" \"NS(tm)  address conversion routines.\" \"\" ns(3N)\n.xx \"network byte order.\" \"htonl, htons,\" \"ntohl, ntohs: convert values between host and\" \"\" byteorder(3N)\n.xx \"order.\" \"htonl, htons, ntohl,\" \"ntohs: convert values between host and network byte\" \"\" byteorder(3N)\n.xx \"\" \"\" \"null: data sink.\" \"\" null(4)\n.xx \"\" \"\" \"number: convert Arabic numerals to English.\" \"\" number(6)\n.xx \"\" \"phones: remote host phone\" \"number data base.\" \"\" phones(5)\n.xx \"\" \"arithmetic: provide drill in\" \"number facts.\" \"\" arithmetic(6)\n.xx \"\" \"rand, srand: random\" \"number generator.\" \"\" rand(3C)\n.xx \"\" \"random, drandm, irandm: better random\" \"number generator.\" \"\" random(3F)\n.xx \"\" \"random, srandom, initstate, setstate: better random\" \"number generator; routines for changing generators.\" \"\" random(3)\n.xx \"\" \"L-dialcodes: UUCP phone\" \"number index file.\" \"\" L-dialcodes(5)\n.xx \"\" \"atof, atoi, atol: convert ASCII to\" \"numbers.\" \"\" atof(3)\n.xx \"\" \"intro: introduction to system calls and error\" \"numbers.\" \"\" intro(2)\n.xx \"\" \"number: convert Arabic\" \"numerals to English.\" \"\" number(6)\n.xx \"\" \"idate, itime: return date or time in\" \"numerical form.\" \"\" idate(3F)\n.xx \"\" \"loc: return the address of an\" \"object.\" \"\" loc(3F)\n.xx \"\" \"long, short: integer\" \"object conversion.\" \"\" long(3F)\n.xx \"\" \"size: size of an\" \"object file.\" \"\" size(1)\n.xx \"\" \"lorder: find ordering relation for an\" \"object library.\" \"\" lorder(1)\n.xx \"\" \"what: show what versions of\" \"object modules were used to construct a file.\" \"\" what(1)\n.xx \"\" \"strings: find the printable strings in a\" \"object, or other binary, file.\" \"\" strings(1)\n.xx \"\" \"index, rindex, lnblnk, len: tell about character\" \"objects.\" \"\" index(3F)\n.xx \"\" \"line discipline for machine-machine communication\" \"(obsolete).\" \"bk:\" bk(4)\n.xx \"\" \"od:\" \"octal, decimal, hex, ascii dump.\" \"\" od(1)\n.xx \"\" \"\" \"od: octal, decimal, hex, ascii dump.\" \"\" od(1)\n.xx \"\" \"/pow, gcd, invert, rpow, msqrt, mcmp, move, min,\" \"omin, fmin, m_in, mout, omout, fmout, m_out, sdiv,/\" \"\" mp(3X)\n.xx \"\" \"/msqrt, mcmp, move, min, omin, fmin, m_in, mout,\" \"omout, fmout, m_out, sdiv, itom: multiple precision/\" \"\" mp(3X)\n.xx \"\" \"\" \"onintr: process interrupts in command scripts.\" \"\" csh(1)\n.xx \"\" \"nohup: run a command at low priority (\\fIsh\\fR\" \"only).\" \"nice,\" nice(1)\n.xx \"\" \"program file including aliases and paths (\\fIcsh\\fR\" \"only).\" \"which: locate a\" which(1)\n.xx \"file.\" \"open:\" \"open a file for reading or writing, or create a new\" \"\" open(2)\n.xx \"\" \"fopen, freopen, fdopen:\" \"open a stream.\" \"\" fopen(3S)\n.xx \"\" \"flock: apply or remove an advisory lock on an\" \"open file.\" \"\" flock(2)\n.xx \"a new file.\" \"\" \"open: open a file for reading or writing, or create\" \"\" open(2)\n.xx \"closedir: directory operations.\" \"\" \"opendir, readdir, telldir, seekdir, rewinddir,\" \"\" directory(3)\n.xx \"\" \"syslog,\" \"openlog, closelog, setlogmask: control system log.\" \"\" syslog(3)\n.xx \"cont, point, linemod, space, closepl:/\" \"plot:\" \"openpl, erase, label, line, circle, arc, move,\" \"\" plot(3X)\n.xx \"(3X) libraries..\" \"plot:\" \"openpl et al.: f77 library interface to \\fIplot\\fR\" \"\" plot(3F)\n.xx \"\" \"savecore: save a core dump of the\" \"operating system.\" \"\" savecore(8)\n.xx \"\" \"kgmon: generate a dump of the\" \"operating system's profile buffers.\" \"\" kgmon(8)\n.xx \"\" \"intro: introduction to system maintenance and\" \"operation commands.\" \"\" intro(8)\n.xx \"\" \"tgetstr, tgoto, tputs: terminal independent\" \"operation routines.\" \"tgetent, tgetnum, tgetflag,\" termcap(3X)\n.xx \"\" \"bcopy, bcmp, bzero, ffs: bit and byte string\" \"operations.\" \"\" bstring(3)\n.xx \"\" \"telldir, seekdir, rewinddir, closedir: directory\" \"operations.\" \"opendir, readdir,\" directory(3)\n.xx \"\" \"strcpy, strncpy, strlen, index, rindex: string\" \"operations.\" \"strcat, strncat, strcmp, strncmp,\" string(3)\n.xx \"\" \"infnan: signals invalid floating-point\" \"operations on a VAX (temporary).\" \"\" infnan(3M)\n.xx \"\" \"join: relational database\" \"operator.\" \"\" join(1)\n.xx \"\" \"curses: screen functions with\" \"``optimal'' cursor motion.\" \"\" curses(3X)\n.xx \"\" \"getopt: get\" \"option letter from argv.\" \"\" getopt(3)\n.xx \"\" \"stty: set terminal\" \"options.\" \"\" stty(1)\n.xx \"\" \"getsockopt, setsockopt: get and set\" \"options on sockets.\" \"\" getsockopt(2)\n.xx \"\" \"ntohs: convert values between host and network byte\" \"order.\" \"htonl, htons, ntohl,\" byteorder(3N)\n.xx \"\" \"lastcomm: show last commands executed in reverse\" \"order.\" \"\" lastcomm(1)\n.xx \"\" \"lorder: find\" \"ordering relation for an object library.\" \"\" lorder(1)\n.xx \"\" \"bessel functions: of two kinds for integer\" \"orders.\" \"\" bessel(3F)\n.xx \"\" \"vi: screen\" \"oriented (visual) display editor based on ex.\" \"\" vi(1)\n.xx \"\" \"patch: a program for applying a diff file to an\" \"original.\" \"\" patch(1)\n.xx \"\" \"a.out: assembler and link editor\" \"output.\" \"\" a.out(5)\n.xx \"\" \"terminate a process after flushing any pending\" \"output.\" \"exit:\" exit(3)\n.xx \"\" \"write, writev: write\" \"output.\" \"\" write(2)\n.xx \"\" \"ecvt, fcvt, gcvt:\" \"output conversion.\" \"\" ecvt(3)\n.xx \"\" \"printf, fprintf, sprintf: formatted\" \"output conversion.\" \"\" printf(3S)\n.xx \"\" \"fold: fold long lines for finite width\" \"output device.\" \"\" fold(1)\n.xx \"\" \"colcrt: filter nroff\" \"output for CRT previewing.\" \"\" colcrt(1)\n.xx \"\" \"flush: flush\" \"output to a logical unit.\" \"\" flush(3F)\n.xx \"\" \"foreach: loop\" \"over list of names.\" \"\" csh(1)\n.xx \"\" \"sendmail: send mail\" \"over the internet.\" \"\" sendmail(8)\n.xx \"\" \"trapov: trap and repair floating point\" \"overflow.\" \"\" trapov(3F)\n.xx \"\" \"exec:\" \"overlay shell with specified command.\" \"\" csh(1)\n.xx \"\" \"chown: change\" \"owner.\" \"\" chown(8)\n.xx \"\" \"chown: change\" \"owner and group of a file.\" \"\" chown(2)\n.xx \"\" \"quot: summarize file system\" \"ownership.\" \"\" quot(8)\n.xx \"\" \"\" \"pac: printer/plotter accounting information.\" \"\" pac(8)\n.xx \"\" \"spp: Xerox Sequenced\" \"Packet Protocol.\" \"\" spp(4P)\n.xx \"\" \"trsp: transliterate sequenced\" \"packet protocol trace.\" \"\" trsp(8C)\n.xx \"\" \"network interface encapsulating ns packets in ip\" \"packets..\" \"nsip: software\" nsip(4)\n.xx \"\" \"nsip: software network interface encapsulating ns\" \"packets in ip packets..\" \"\" nsip(4)\n.xx \"\" \"ping: send ICMP ECHO_REQUEST\" \"packets to network hosts.\" \"\" ping(8)\n.xx \"\" \"format: how to format disk\" \"packs.\" \"\" format(8V)\n.xx \"\" \"more,\" \"page: file perusal filter for crt viewing.\" \"\" more(1)\n.xx \"\" \"getpagesize: get system\" \"page size.\" \"\" getpagesize(2)\n.xx \"\" \"pagesize: print system\" \"page size.\" \"\" pagesize(1)\n.xx \"\" \"miscellaneous: miscellaneous useful information\" \"pages.\" \"\" intro(7)\n.xx \"\" \"\" \"pagesize: print system page size.\" \"\" pagesize(1)\n.xx \"\" \"tk:\" \"paginator for the Tektronix 4014.\" \"\" tk(1)\n.xx \"\" \"swapon: specify additional device for\" \"paging and swapping.\" \"\" swapon(8)\n.xx \"\" \"drum:\" \"paging device.\" \"\" drum(4)\n.xx \"\" \"swapon: add a swap device for interleaved\" \"paging/swapping.\" \"\" swapon(2)\n.xx \"\" \"socketpair: create a\" \"pair of connected sockets.\" \"\" socketpair(2)\n.xx \"\" \"me: macros for formatting\" \"papers.\" \"\" me(7)\n.xx \"\" \"ifconfig: configure network interface\" \"parameters.\" \"\" ifconfig(8C)\n.xx \"\" \"diskpart: calculate default disk\" \"partition sizes.\" \"\" diskpart(8)\n.xx \"\" \"pc:\" \"Pascal compiler.\" \"\" pc(1)\n.xx \"\" \"pxref:\" \"Pascal cross-reference program.\" \"\" pxref(1)\n.xx \"\" \"pdx:\" \"pascal debugger.\" \"\" pdx(1)\n.xx \"\" \"pxp:\" \"Pascal execution profiler.\" \"\" pxp(1)\n.xx \"\" \"pmerge:\" \"pascal file merger.\" \"\" pmerge(1)\n.xx \"\" \"px:\" \"Pascal interpreter.\" \"\" px(1)\n.xx \"\" \"pix:\" \"Pascal interpreter and executor.\" \"\" pix(1)\n.xx \"\" \"pi:\" \"Pascal interpreter code translator.\" \"\" pi(1)\n.xx \"\" \"chfn, chsh,\" \"passwd: change password file information.\" \"\" chfn(1)\n.xx \"\" \"chfn, chsh,\" \"passwd: change password file information.\" \"\" chsh(1)\n.xx \"\" \"chfn, chsh,\" \"passwd: change password file information.\" \"\" passwd(1)\n.xx \"\" \"\" \"passwd: password file.\" \"\" passwd(5)\n.xx \"\" \"getpass: read a\" \"password.\" \"\" getpass(3)\n.xx \"\" \"passwd:\" \"password file.\" \"\" passwd(5)\n.xx \"\" \"vipw: edit the\" \"password file.\" \"\" vipw(8)\n.xx \"\" \"getpwnam, setpwent, endpwent, setpwfile: get\" \"password file entry.\" \"getpwent, getpwuid,\" getpwent(3)\n.xx \"\" \"chfn, chsh, passwd: change\" \"password file information.\" \"\" chfn(1)\n.xx \"\" \"chfn, chsh, passwd: change\" \"password file information.\" \"\" chsh(1)\n.xx \"\" \"chfn, chsh, passwd: change\" \"password file information.\" \"\" passwd(1)\n.xx \"\" \"mkpasswd: generate hashed\" \"password table.\" \"\" mkpasswd(8)\n.xx \"original.\" \"\" \"patch: a program for applying a diff file to an\" \"\" patch(1)\n.xx \"\" \"getwd: get current working directory\" \"pathname.\" \"\" getwd(3)\n.xx \"\" \"getcwd: get\" \"pathname of current working directory.\" \"\" getcwd(3F)\n.xx \"\" \"USERFILE: UUCP\" \"pathname permissions file.\" \"\" USERFILE(5)\n.xx \"\" \"which: locate a program file including aliases and\" \"paths (\\fIcsh\\fR only).\" \"\" which(1)\n.xx \"\" \"grep, egrep, fgrep: search a file for a\" \"pattern.\" \"\" grep(1)\n.xx \"\" \"lptest: generate lineprinter ripple\" \"pattern.\" \"\" lptest(1)\n.xx \"\" \"awk:\" \"pattern scanning and processing language.\" \"\" awk(1)\n.xx \"\" \"\" \"pause: stop until signal.\" \"\" pause(3C)\n.xx \"\" \"\" \"pc: Pascal compiler.\" \"\" pc(1)\n.xx \"\" \"\" \"pcl: DEC CSS PCL-11 B Network Interface.\" \"\" pcl(4)\n.xx \"\" \"pcl: DEC CSS\" \"PCL-11 B Network Interface.\" \"\" pcl(4)\n.xx \"\" \"popen,\" \"pclose: initiate I/O to/from a process.\" \"\" popen(3)\n.xx \"\" \"\" \"pdx: pascal debugger.\" \"\" pdx(1)\n.xx \"\" \"getpeername: get name of connected\" \"peer.\" \"\" getpeername(2)\n.xx \"\" \"exit: terminate a process after flushing any\" \"pending output.\" \"\" exit(3)\n.xx \"\" \"L.cmds: UUCP remote command\" \"permissions file.\" \"\" L.cmds(5)\n.xx \"\" \"USERFILE: UUCP pathname\" \"permissions file.\" \"\" USERFILE(5)\n.xx \"\" \"mesg:\" \"permit or deny messages.\" \"\" mesg(1)\n.xx \"\" \"ptx:\" \"permuted index.\" \"\" ptx(1)\n.xx \"\" \"limit: alter\" \"per-process resource limitations.\" \"\" csh(1)\n.xx \"\" \"\" \"perror, gerror, ierrno: get system error messages.\" \"\" perror(3F)\n.xx \"messages.\" \"\" \"perror, sys_errlist, sys_nerr: system error\" \"\" perror(3)\n.xx \"\" \"sticky:\" \"persistent text and append-only directories.\" \"\" sticky(8)\n.xx \"\" \"more, page: file\" \"perusal filter for crt viewing.\" \"\" more(1)\n.xx \"\" \"phones: remote host\" \"phone number data base.\" \"\" phones(5)\n.xx \"\" \"L-dialcodes: UUCP\" \"phone number index file.\" \"\" L-dialcodes(5)\n.xx \"\" \"\" \"phones: remote host phone number data base.\" \"\" phones(5)\n.xx \"\" \"ct:\" \"phototypesetter interface.\" \"\" ct(4)\n.xx \"\" \"tc:\" \"photoypesetter simulator.\" \"\" tc(1)\n.xx \"\" \"\" \"pi: Pascal interpreter code translator.\" \"\" pi(1)\n.xx \"\" \"ps: Evans and Sutherland\" \"Picture System 2 graphics device interface.\" \"\" ps(4)\n.xx \"hosts.\" \"\" \"ping: send ICMP ECHO_REQUEST packets to network\" \"\" ping(8)\n.xx \"\" \"\" \"pipe: create an interprocess communication channel.\" \"\" pipe(2)\n.xx \"\" \"tee:\" \"pipe fitting.\" \"\" tee(1)\n.xx \"\" \"\" \"pix: Pascal interpreter and executor.\" \"\" pix(1)\n.xx \"\" \"bg:\" \"place job in background.\" \"\" csh(1)\n.xx \"\" \"fish:\" \"play ``Go Fish''.\" \"\" fish(6)\n.xx \"\" \"mille:\" \"play Mille Bournes.\" \"\" mille(6)\n.xx \"\" \"boggle:\" \"play the game of boggle.\" \"\" boggle(6)\n.xx \"\" \"worm:\" \"Play the growing worm game.\" \"\" worm(6)\n.xx \"\" \"\" \"plot: graphics filters.\" \"\" plot(1G)\n.xx \"\" \"\" \"plot: graphics interface.\" \"\" plot(5)\n.xx \"move, cont, point, linemod, space, closepl:/\" \"\" \"plot: openpl, erase, label, line, circle, arc,\" \"\" plot(3X)\n.xx \"\\fIplot\\fR (3X) libraries..\" \"\" \"plot: openpl et al.: f77 library interface to\" \"\" plot(3F)\n.xx \"\" \"\" \"pmerge: pascal file merger.\" \"\" pmerge(1)\n.xx \"\" \"trpfpe, fpecnt: trap and repair floating\" \"point faults.\" \"\" trpfpe(3F)\n.xx \"\" \"/erase, label, line, circle, arc, move, cont,\" \"point, linemod, space, closepl: graphics interface.\" \"\" plot(3X)\n.xx \"\" \"trapov: trap and repair floating\" \"point overflow.\" \"\" trapov(3F)\n.xx \"\" \"lseek: move read/write\" \"pointer.\" \"\" lseek(2)\n.xx \"\" \"dmc: DEC DMC-11/DMR-11\" \"point-to-point communications device.\" \"\" dmc(4)\n.xx \"\" \"uupoll:\" \"poll a remote UUCP site.\" \"\" uupoll(8C)\n.xx \"\" \"popd:\" \"pop shell directory stack.\" \"\" csh(1)\n.xx \"\" \"\" \"popd: pop shell directory stack.\" \"\" csh(1)\n.xx \"\" \"\" \"popen, pclose: initiate I/O to/from a process.\" \"\" popen(3)\n.xx \"\" \"ttynam, isatty: find name of a terminal\" \"port.\" \"\" ttynam(3F)\n.xx \"\" \"exp, expm1, log, log10, log1p,\" \"pow: exponential, logarithm, power.\" \"\" exp(3M)\n.xx \"omin, fmin, m_in, mout,/\" \"madd, msub, mult, mdiv,\" \"pow, gcd, invert, rpow, msqrt, mcmp, move, min,\" \"\" mp(3X)\n.xx \"\" \"log, log10, log1p, pow: exponential, logarithm,\" \"power.\" \"exp, expm1,\" exp(3M)\n.xx \"\" \"\" \"pr: print file.\" \"\" pr(1)\n.xx \"\" \"mout, omout, fmout, m_out, sdiv, itom: multiple\" \"precision integer arithmetic.\" \"/omin, fmin, m_in,\" mp(3X)\n.xx \"\" \"monitor, monstartup, moncontrol:\" \"prepare execution profile.\" \"\" monitor(3)\n.xx \"\" \"colcrt: filter nroff output for CRT\" \"previewing.\" \"\" colcrt(1)\n.xx \"\" \"types:\" \"primitive system data types.\" \"\" types(5)\n.xx \"\" \"cat: catenate and\" \"print.\" \"\" cat(1)\n.xx \"\" \"lpr: off line\" \"print.\" \"\" lpr(1)\n.xx \"\" \"fortune:\" \"print a random, hopefully interesting, adage.\" \"\" fortune(6)\n.xx \"\" \"date:\" \"print and set the date.\" \"\" date(1)\n.xx \"\" \"cal:\" \"print calendar.\" \"\" cal(1)\n.xx \"\" \"hashstat:\" \"print command hashing statistics.\" \"\" csh(1)\n.xx \"\" \"jobs:\" \"print current job list.\" \"\" csh(1)\n.xx \"\" \"whoami:\" \"print effective current user id.\" \"\" whoami(1)\n.xx \"\" \"pr:\" \"print file.\" \"\" pr(1)\n.xx \"\" \"fpr:\" \"print Fortran file.\" \"\" fpr(1)\n.xx \"\" \"history:\" \"print history event list.\" \"\" csh(1)\n.xx \"\" \"hostid: set or\" \"print identifier of current host system.\" \"\" hostid(1)\n.xx \"\" \"banner:\" \"print large banner on printer.\" \"\" banner(6)\n.xx \"\" \"nm:\" \"print name list.\" \"\" nm(1)\n.xx \"\" \"hostname: set or\" \"print name of current host system.\" \"\" hostname(1)\n.xx \"\" \"printenv:\" \"print out the environment.\" \"\" printenv(1)\n.xx \"\" \"man: find manual information by keywords;\" \"print out the manual.\" \"\" man(1)\n.xx \"\" \"pstat:\" \"print system facts.\" \"\" pstat(8)\n.xx \"\" \"pagesize:\" \"print system page size.\" \"\" pagesize(1)\n.xx \"\" \"atq:\" \"print the queue of jobs waiting to be run.\" \"\" atq(1)\n.xx \"\" \"diction, explain:\" \"print wordy sentences; thesaurus for diction.\" \"\" diction(1)\n.xx \"file.\" \"strings: find the\" \"printable strings in a object, or other binary,\" \"\" strings(1)\n.xx \"\" \"\" \"printcap: printer capability data base.\" \"\" printcap(5)\n.xx \"\" \"vlp: Format Lisp programs to be\" \"printed with nroff, vtroff, or troff.\" \"\" vlp(1)\n.xx \"\" \"\" \"printenv: print out the environment.\" \"\" printenv(1)\n.xx \"\" \"banner: print large banner on\" \"printer.\" \"\" banner(6)\n.xx \"\" \"lp: line\" \"printer.\" \"\" lp(4)\n.xx \"\" \"printcap:\" \"printer capability data base.\" \"\" printcap(5)\n.xx \"\" \"lpc: line\" \"printer control program.\" \"\" lpc(8)\n.xx \"\" \"lpd: line\" \"printer daemon.\" \"\" lpd(8)\n.xx \"\" \"lprm: remove jobs from the line\" \"printer spooling queue.\" \"\" lprm(1)\n.xx \"\" \"pac:\" \"printer/plotter accounting information.\" \"\" pac(8)\n.xx \"conversion.\" \"\" \"printf, fprintf, sprintf: formatted output\" \"\" printf(3S)\n.xx \"\" \"setpriority: get/set program scheduling\" \"priority.\" \"getpriority,\" getpriority(2)\n.xx \"\" \"nice: set program\" \"priority.\" \"\" nice(3C)\n.xx \"\" \"nice, nohup: run a command at low\" \"priority (\\fIsh\\fR only).\" \"\" nice(1)\n.xx \"\" \"renice: alter\" \"priority of running processes.\" \"\" renice(8)\n.xx \"\" \"nice: run low\" \"priority process.\" \"\" csh(1)\n.xx \"\" \"adduser:\" \"procedure for adding new users.\" \"\" adduser(8)\n.xx \"\" \"reboot: UNIX bootstrapping\" \"procedures.\" \"\" reboot(8)\n.xx \"\" \"nice: run low priority\" \"process.\" \"\" csh(1)\n.xx \"\" \"stop: halt a job or\" \"process.\" \"\" csh(1)\n.xx \"\" \"_exit: terminate a\" \"process.\" \"\" exit(2)\n.xx \"\" \"fork: create a new\" \"process.\" \"\" fork(2)\n.xx \"\" \"fork: create a copy of this\" \"process.\" \"\" fork(3F)\n.xx \"\" \"implogd: IMP logger\" \"process.\" \"\" implogd(8C)\n.xx \"\" \"kill: send signal to a\" \"process.\" \"\" kill(2)\n.xx \"\" \"kill: send a signal to a\" \"process.\" \"\" kill(3F)\n.xx \"\" \"popen, pclose: initiate I/O to/from a\" \"process.\" \"\" popen(3)\n.xx \"\" \"wait: await completion of\" \"process.\" \"\" wait(1)\n.xx \"\" \"exit: terminate a\" \"process after flushing any pending output.\" \"\" exit(3)\n.xx \"\" \"init:\" \"process control initialization.\" \"\" init(8)\n.xx \"\" \"getpgrp: get\" \"process group.\" \"\" getpgrp(2)\n.xx \"\" \"killpg: send signal to a\" \"process group.\" \"\" killpg(2)\n.xx \"\" \"setpgrp: set\" \"process group.\" \"\" setpgrp(2)\n.xx \"\" \"getpid: get\" \"process id.\" \"\" getpid(3F)\n.xx \"\" \"getpid, getppid: get\" \"process identification.\" \"\" getpid(2)\n.xx \"\" \"vfork: spawn new\" \"process in a virtual memory efficient way.\" \"\" vfork(2)\n.xx \"\" \"onintr:\" \"process interrupts in command scripts.\" \"\" csh(1)\n.xx \"\" \"ps:\" \"process status.\" \"\" ps(1)\n.xx \"\" \"times: get\" \"process times.\" \"\" times(3C)\n.xx \"\" \"wait, wait3: wait for\" \"process to terminate.\" \"\" wait(2)\n.xx \"\" \"wait: wait for a\" \"process to terminate.\" \"\" wait(3F)\n.xx \"\" \"ptrace:\" \"process trace.\" \"\" ptrace(2)\n.xx \"\" \"kill: terminate a\" \"process with extreme prejudice.\" \"\" kill(1)\n.xx \"\" \"exit: terminate\" \"process with status.\" \"\" exit(3F)\n.xx \"\" \"kill: kill jobs and\" \"processes.\" \"\" csh(1)\n.xx \"\" \"gcore: get core images of running\" \"processes.\" \"\" gcore(1)\n.xx \"\" \"renice: alter priority of running\" \"processes.\" \"\" renice(8)\n.xx \"\" \"wait: wait for background\" \"processes to complete.\" \"\" csh(1)\n.xx \"\" \"awk: pattern scanning and\" \"processing language.\" \"\" awk(1)\n.xx \"\" \"halt: stop the\" \"processor.\" \"\" halt(8)\n.xx \"\" \"m4: macro\" \"processor.\" \"\" m4(1)\n.xx \"\" \"reboot: reboot system or halt\" \"processor.\" \"\" reboot(2)\n.xx \"\" \"\" \"prof: display profile data.\" \"\" prof(1)\n.xx \"\" \"\" \"profil: execution time profile.\" \"\" profil(2)\n.xx \"\" \"monitor, monstartup, moncontrol: prepare execution\" \"profile.\" \"\" monitor(3)\n.xx \"\" \"profil: execution time\" \"profile.\" \"\" profil(2)\n.xx \"\" \"kgmon: generate a dump of the operating system's\" \"profile buffers.\" \"\" kgmon(8)\n.xx \"\" \"gprof: display call graph\" \"profile data.\" \"\" gprof(1)\n.xx \"\" \"prof: display\" \"profile data.\" \"\" prof(1)\n.xx \"\" \"pxp: Pascal execution\" \"profiler.\" \"\" pxp(1)\n.xx \"\" \"drtest: standalone disk test\" \"program.\" \"\" drtest(8)\n.xx \"\" \"end, etext, edata: last locations in\" \"program.\" \"\" end(3)\n.xx \"\" \"finger: user information lookup\" \"program.\" \"\" finger(1)\n.xx \"\" \"ftp: ARPANET file transfer\" \"program.\" \"\" ftp(1C)\n.xx \"\" \"liszt: compile a Franz Lisp\" \"program.\" \"\" liszt(1)\n.xx \"\" \"lpc: line printer control\" \"program.\" \"\" lpc(8)\n.xx \"\" \"lpq: spool queue examination\" \"program.\" \"\" lpq(1)\n.xx \"\" \"lxref: lisp cross reference\" \"program.\" \"\" lxref(1)\n.xx \"\" \"msgs: system messages and junk mail\" \"program.\" \"\" msgs(1)\n.xx \"\" \"mt: magnetic tape manipulating\" \"program.\" \"\" mt(1)\n.xx \"\" \"pxref: Pascal cross-reference\" \"program.\" \"\" pxref(1)\n.xx \"\" \"rdist: remote file distribution\" \"program.\" \"\" rdist(1)\n.xx \"\" \"tftp: trivial file transfer\" \"program.\" \"\" tftp(1C)\n.xx \"\" \"timedc: timed control\" \"program.\" \"\" timedc(8)\n.xx \"\" \"units: conversion\" \"program.\" \"\" units(1)\n.xx \"\" \"whereis: locate source, binary, and or manual for\" \"program.\" \"\" whereis(1)\n.xx \"\" \"cb: C\" \"program beautifier.\" \"\" cb(1)\n.xx \"only).\" \"which: locate a\" \"program file including aliases and paths (\\fIcsh\\fR\" \"\" which(1)\n.xx \"\" \"patch: a\" \"program for applying a diff file to an original.\" \"\" patch(1)\n.xx \"\" \"make: maintain\" \"program groups.\" \"\" make(1)\n.xx \"\" \"nice: set\" \"program priority.\" \"\" nice(3C)\n.xx \"\" \"getpriority, setpriority: get/set\" \"program scheduling priority.\" \"\" getpriority(2)\n.xx \"\" \"indent: indent and format C\" \"program source.\" \"\" indent(1)\n.xx \"\" \"assert:\" \"program verification.\" \"\" assert(3)\n.xx \"\" \"lint: a C\" \"program verifier.\" \"\" lint(1)\n.xx \"\" \"fp: Functional\" \"Programming language compiler/interpreter.\" \"\" fp(1)\n.xx \"\" \"lex: generator of lexical analysis\" \"programs.\" \"\" lex(1)\n.xx \"\" \"struct: structure Fortran\" \"programs.\" \"\" struct(1)\n.xx \"\" \"vgrind: grind nice listings of\" \"programs.\" \"\" vgrind(1)\n.xx \"troff.\" \"vlp: Format Lisp\" \"programs to be printed with nroff, vtroff, or\" \"\" vlp(1)\n.xx \"\" \"xstr: extract strings from C\" \"programs to implement shared strings.\" \"\" xstr(1)\n.xx \"\" \"vv: Proteon\" \"proNET 10 Megabit ring.\" \"\" vv(4)\n.xx \"\" \"vv:\" \"Proteon proNET 10 Megabit ring.\" \"\" vv(4)\n.xx \"\" \"arp: Address Resolution\" \"Protocol.\" \"\" arp(4P)\n.xx \"\" \"icmp: Internet Control Message\" \"Protocol.\" \"\" icmp(4P)\n.xx \"\" \"idp: Xerox Internet Datagram\" \"Protocol.\" \"\" idp(4P)\n.xx \"\" \"ip: Internet\" \"Protocol.\" \"\" ip(4P)\n.xx \"\" \"spp: Xerox Sequenced Packet\" \"Protocol.\" \"\" spp(4P)\n.xx \"\" \"tcp: Internet Transmission Control\" \"Protocol.\" \"\" tcp(4P)\n.xx \"\" \"telnet: user interface to the TELNET\" \"protocol.\" \"\" telnet(1C)\n.xx \"\" \"udp: Internet User Datagram\" \"Protocol.\" \"\" udp(4P)\n.xx \"\" \"XNSrouted: NS Routing Information\" \"Protocol daemon.\" \"\" XNSrouted(8C)\n.xx \"\" \"getprotobyname, setprotoent, endprotoent: get\" \"protocol entry.\" \"getprotoent, getprotobynumber,\" getprotoent(3N)\n.xx \"\" \"inet: Internet\" \"protocol family.\" \"\" inet(4F)\n.xx \"\" \"ns: Xerox Network Systems(tm)\" \"protocol family.\" \"\" ns(4F)\n.xx \"\" \"rmt: remote magtape\" \"protocol module.\" \"\" rmt(8C)\n.xx \"\" \"protocols:\" \"protocol name data base.\" \"\" protocols(5)\n.xx \"\" \"ftpd: DARPA Internet File Transfer\" \"Protocol server.\" \"\" ftpd(8C)\n.xx \"\" \"telnetd: DARPA TELNET\" \"protocol server.\" \"\" telnetd(8C)\n.xx \"\" \"tftpd: DARPA Trivial File Transfer\" \"Protocol server.\" \"\" tftpd(8C)\n.xx \"\" \"trpt: transliterate\" \"protocol trace.\" \"\" trpt(8C)\n.xx \"\" \"trsp: transliterate sequenced packet\" \"protocol trace.\" \"\" trsp(8C)\n.xx \"\" \"\" \"protocols: protocol name data base.\" \"\" protocols(5)\n.xx \"\" \"mkproto: construct a\" \"prototype file system.\" \"\" mkproto(8)\n.xx \"\" \"arithmetic:\" \"provide drill in number facts.\" \"\" arithmetic(6)\n.xx \"\" \"false, true:\" \"provide truth values.\" \"\" false(1)\n.xx \"\" \"true, false:\" \"provide truth values.\" \"\" true(1)\n.xx \"device interface.\" \"\" \"ps: Evans and Sutherland Picture System 2 graphics\" \"\" ps(4)\n.xx \"\" \"\" \"ps: process status.\" \"\" ps(1)\n.xx \"\" \"pty:\" \"pseudo terminal driver.\" \"\" pty(4)\n.xx \"\" \"\" \"psignal, sys_siglist: system signal messages.\" \"\" psignal(3)\n.xx \"\" \"\" \"pstat: print system facts.\" \"\" pstat(8)\n.xx \"\" \"doctor: interact with a\" \"psychoanalyst.\" \"\" doctor(6)\n.xx \"\" \"\" \"ptrace: process trace.\" \"\" ptrace(2)\n.xx \"\" \"\" \"ptx: permuted index.\" \"\" ptx(1)\n.xx \"\" \"\" \"pty: pseudo terminal driver.\" \"\" pty(4)\n.xx \"\" \"ungetc:\" \"push character back into input stream.\" \"\" ungetc(3S)\n.xx \"\" \"pushd:\" \"push shell directory stack.\" \"\" csh(1)\n.xx \"\" \"\" \"pushd: push shell directory stack.\" \"\" csh(1)\n.xx \"\" \"puts, fputs:\" \"put a string on a stream.\" \"\" puts(3S)\n.xx \"\" \"putc, putchar, fputc, putw:\" \"put character or word on a stream.\" \"\" putc(3S)\n.xx \"unit.\" \"\" \"putc, fputc: write a character to a fortran logical\" \"\" putc(3F)\n.xx \"on a stream.\" \"\" \"putc, putchar, fputc, putw: put character or word\" \"\" putc(3S)\n.xx \"stream.\" \"putc,\" \"putchar, fputc, putw: put character or word on a\" \"\" putc(3S)\n.xx \"\" \"\" \"puts, fputs: put a string on a stream.\" \"\" puts(3S)\n.xx \"\" \"putc, putchar, fputc,\" \"putw: put character or word on a stream.\" \"\" putc(3S)\n.xx \"\" \"\" \"pwd: working directory name.\" \"\" pwd(1)\n.xx \"\" \"\" \"px: Pascal interpreter.\" \"\" px(1)\n.xx \"\" \"\" \"pxp: Pascal execution profiler.\" \"\" pxp(1)\n.xx \"\" \"\" \"pxref: Pascal cross-reference program.\" \"\" pxref(1)\n.xx \"\" \"qe: DEC DEQNA\" \"Q-bus 10 Mb/s Ethernet interface.\" \"\" qe(4)\n.xx \"\" \"\" \"qe: DEC DEQNA Q-bus 10 Mb/s Ethernet interface.\" \"\" qe(4)\n.xx \"\" \"\" \"qsort: quick sort.\" \"\" qsort(3F)\n.xx \"\" \"\" \"qsort: quicker sort.\" \"\" qsort(3)\n.xx \"\" \"insque, remque: insert/remove element from a\" \"queue.\" \"\" insque(3)\n.xx \"\" \"lprm: remove jobs from the line printer spooling\" \"queue.\" \"\" lprm(1)\n.xx \"\" \"uuq: examine or manipulate the uucp\" \"queue.\" \"\" uuq(1C)\n.xx \"\" \"lpq: spool\" \"queue examination program.\" \"\" lpq(1)\n.xx \"\" \"atq: print the\" \"queue of jobs waiting to be run.\" \"\" atq(1)\n.xx \"\" \"uucico, uucpd: transfer files\" \"queued by uucp or uux.\" \"\" uucico(8C)\n.xx \"\" \"qsort:\" \"quick sort.\" \"\" qsort(3F)\n.xx \"\" \"qsort:\" \"quicker sort.\" \"\" qsort(3)\n.xx \"\" \"\" \"quiz: test your knowledge.\" \"\" quiz(6)\n.xx \"\" \"\" \"quot: summarize file system ownership.\" \"\" quot(8)\n.xx \"\" \"quotacheck: file system\" \"quota consistency checker.\" \"\" quotacheck(8)\n.xx \"\" \"\" \"quota: display disc usage and limits.\" \"\" quota(1)\n.xx \"\" \"\" \"quota: manipulate disk quotas.\" \"\" quota(2)\n.xx \"\" \"\" \"quotacheck: file system quota consistency checker.\" \"\" quotacheck(8)\n.xx \"\" \"quotaon,\" \"quotaoff: turn file system quotas on and off.\" \"\" quotaon(8)\n.xx \"off.\" \"\" \"quotaon, quotaoff: turn file system quotas on and\" \"\" quotaon(8)\n.xx \"\" \"edquota: edit user\" \"quotas.\" \"\" edquota(8)\n.xx \"\" \"quota: manipulate disk\" \"quotas.\" \"\" quota(2)\n.xx \"\" \"repquota: summarize\" \"quotas for a file system.\" \"\" repquota(8)\n.xx \"\" \"setquota: enable/disable\" \"quotas on a file system.\" \"\" setquota(2)\n.xx \"\" \"quotaon, quotaoff: turn file system\" \"quotas on and off.\" \"\" quotaon(8)\n.xx \"\" \"\" \"rain: animated raindrops display.\" \"\" rain(6)\n.xx \"\" \"rain: animated\" \"raindrops display.\" \"\" rain(6)\n.xx \"\" \"\" \"rand, drand, irand: return random values.\" \"\" rand(3F)\n.xx \"\" \"\" \"rand, srand: random number generator.\" \"\" rand(3C)\n.xx \"generator.\" \"\" \"random, drandm, irandm: better random number\" \"\" random(3F)\n.xx \"\" \"fortune: print a\" \"random, hopefully interesting, adage.\" \"\" fortune(6)\n.xx \"\" \"ranlib: convert archives to\" \"random libraries.\" \"\" ranlib(1)\n.xx \"\" \"rand, srand:\" \"random number generator.\" \"\" rand(3C)\n.xx \"\" \"random, drandm, irandm: better\" \"random number generator.\" \"\" random(3F)\n.xx \"\" \"random, srandom, initstate, setstate: better\" \"random number generator; routines for changing/\" \"\" random(3)\n.xx \"number generator; routines for changing/\" \"\" \"random, srandom, initstate, setstate: better random\" \"\" random(3)\n.xx \"\" \"rand, drand, irand: return\" \"random values.\" \"\" rand(3F)\n.xx \"\" \"\" \"ranlib: convert archives to random libraries.\" \"\" ranlib(1)\n.xx \"\" \"\" \"ratfor: rational Fortran dialect.\" \"\" ratfor(1)\n.xx \"\" \"ratfor:\" \"rational Fortran dialect.\" \"\" ratfor(1)\n.xx \"\" \"imp: IMP\" \"raw socket interface.\" \"\" imp(4P)\n.xx \"\" \"\" \"rc: command script for auto-reboot and daemons.\" \"\" rc(8)\n.xx \"stream to a remote command.\" \"\" \"rcmd, rresvport, ruserok: routines for returning a\" \"\" rcmd(3)\n.xx \"\" \"\" \"rcp: remote file copy.\" \"\" rcp(1C)\n.xx \"\" \"rcsintro: introduction to\" \"RCS commands.\" \"\" rcsintro(1)\n.xx \"\" \"\" \"rcsintro: introduction to RCS commands.\" \"\" rcsintro(1)\n.xx \"\" \"\" \"rdist: remote file distribution program.\" \"\" rdist(1)\n.xx \"\" \"\" \"rdump: file system dump across the network.\" \"\" rdump(8C)\n.xx \"\" \"getpass:\" \"read a password.\" \"\" getpass(3)\n.xx \"\" \"source:\" \"read commands from file.\" \"\" csh(1)\n.xx \"\" \"read, readv:\" \"read input.\" \"\" read(2)\n.xx \"\" \"readnews:\" \"read news articles.\" \"\" readnews(1)\n.xx \"\" \"vnews:\" \"read news articles.\" \"\" vnews(1)\n.xx \"\" \"/continue, cd, eval, exec, exit, export, login,\" \"read, readonly, set, shift, times, trap, umask,/\" \"\" sh(1)\n.xx \"\" \"\" \"read, readv: read input.\" \"\" read(2)\n.xx \"\" \"readlink:\" \"read value of a symbolic link.\" \"\" readlink(2)\n.xx \"directory operations.\" \"opendir,\" \"readdir, telldir, seekdir, rewinddir, closedir:\" \"\" directory(3)\n.xx \"\" \"open: open a file for\" \"reading or writing, or create a new file.\" \"\" open(2)\n.xx \"\" \"\" \"readlink: read value of a symbolic link.\" \"\" readlink(2)\n.xx \"\" \"\" \"readnews: read news articles.\" \"\" readnews(1)\n.xx \"\" \"notes, autoseq,\" \"readnotes: a news system.\" \"\" notes(1)\n.xx \"command/\" \"/cd, eval, exec, exit, export, login, read,\" \"readonly, set, shift, times, trap, umask, wait:\" \"\" sh(1)\n.xx \"\" \"read,\" \"readv: read input.\" \"\" read(2)\n.xx \"\" \"bad144:\" \"read/write dec standard 144 bad sector information.\" \"\" bad144(8)\n.xx \"\" \"lseek: move\" \"read/write pointer.\" \"\" lseek(2)\n.xx \"\" \"setregid: set\" \"real and effective group ID.\" \"\" setregid(2)\n.xx \"\" \"setreuid: set\" \"real and effective user ID's.\" \"\" setreuid(2)\n.xx \"\" \"malloc, free,\" \"realloc, calloc, alloca: memory allocator.\" \"\" malloc(3)\n.xx \"\" \"symorder:\" \"rearrange name list.\" \"\" symorder(1)\n.xx \"\" \"\" \"reboot: reboot system or halt processor.\" \"\" reboot(2)\n.xx \"\" \"reboot:\" \"reboot system or halt processor.\" \"\" reboot(2)\n.xx \"\" \"\" \"reboot: UNIX bootstrapping procedures.\" \"\" reboot(8)\n.xx \"\" \"fastboot, fasthalt:\" \"reboot/halt the system without checking the disks.\" \"\" fastboot(8)\n.xx \"\" \"newaliases:\" \"rebuild the data base for the mail aliases file.\" \"\" newaliases(1)\n.xx \"\" \"recv, recvfrom, recvmsg:\" \"receive a message from a socket.\" \"\" recv(2)\n.xx \"\" \"mail: send and\" \"receive mail.\" \"\" mail(1)\n.xx \"\" \"binmail: send or\" \"receive mail among users.\" \"\" binmail(1)\n.xx \"\" \"rmail: handle remote mail\" \"received via uucp.\" \"\" rmail(1)\n.xx \"\" \"\" \"re_comp, re_exec: regular expression handler.\" \"\" regex(3)\n.xx \"\" \"rehash:\" \"recompute command hash table.\" \"\" csh(1)\n.xx \"\" \"utmp, wtmp: login\" \"records.\" \"\" utmp(5)\n.xx \"socket.\" \"\" \"recv, recvfrom, recvmsg: receive a message from a\" \"\" recv(2)\n.xx \"\" \"recv,\" \"recvfrom, recvmsg: receive a message from a socket.\" \"\" recv(2)\n.xx \"\" \"recv, recvfrom,\" \"recvmsg: receive a message from a socket.\" \"\" recv(2)\n.xx \"\" \"eval:\" \"re-evaluate shell data.\" \"\" csh(1)\n.xx \"\" \"re_comp,\" \"re_exec: regular expression handler.\" \"\" regex(3)\n.xx \"documents.\" \"\" \"refer: find and insert literature references in\" \"\" refer(1)\n.xx \"\" \"bibliographic formatter; list bibliographic\" \"reference items.\" \"bib, listrefs:\" bib(1)\n.xx \"\" \"lxref: lisp cross\" \"reference program.\" \"\" lxref(1)\n.xx \"\" \"build inverted index for a bibliography, find\" \"references in a bibliography.\" \"indxbib, lookbib:\" lookbib(1)\n.xx \"\" \"refer: find and insert literature\" \"references in documents.\" \"\" refer(1)\n.xx \"\" \"re_comp, re_exec:\" \"regular expression handler.\" \"\" regex(3)\n.xx \"\" \"\" \"rehash: recompute command hash table.\" \"\" csh(1)\n.xx \"\" \"comm: select or\" \"reject lines common to two sorted files.\" \"\" comm(1)\n.xx \"\" \"lorder: find ordering\" \"relation for an object library.\" \"\" lorder(1)\n.xx \"\" \"join:\" \"relational database operator.\" \"\" join(1)\n.xx \"\" \"sigpause: atomically\" \"release blocked signals and wait for interrupt.\" \"\" sigpause(2)\n.xx \"\" \"strip: remove symbols and\" \"relocation bits.\" \"\" strip(1)\n.xx \"\" \"copysign, drem, finite, logb, scalb: copysign,\" \"remainder, exponent manipulations.\" \"\" ieee(3M)\n.xx \"\" \"leave:\" \"remind you when you have to leave.\" \"\" leave(1)\n.xx \"\" \"calendar:\" \"reminder service.\" \"\" calendar(1)\n.xx \"\" \"ruserok: routines for returning a stream to a\" \"remote command.\" \"rcmd, rresvport,\" rcmd(3)\n.xx \"\" \"rexec: return stream to a\" \"remote command.\" \"\" rexec(3)\n.xx \"\" \"L.cmds: UUCP\" \"remote command permissions file.\" \"\" L.cmds(5)\n.xx \"\" \"rexecd:\" \"remote execution server.\" \"\" rexecd(8C)\n.xx \"\" \"rcp:\" \"remote file copy.\" \"\" rcp(1C)\n.xx \"\" \"rdist:\" \"remote file distribution program.\" \"\" rdist(1)\n.xx \"\" \"uusend: send a file to a\" \"remote host.\" \"\" uusend(1C)\n.xx \"\" \"L.sys: UUCP\" \"remote host description file.\" \"\" L.sys(5)\n.xx \"\" \"remote:\" \"remote host description file.\" \"\" remote(5)\n.xx \"\" \"phones:\" \"remote host phone number data base.\" \"\" phones(5)\n.xx \"\" \"rlogin:\" \"remote login.\" \"\" rlogin(1C)\n.xx \"\" \"rlogind:\" \"remote login server.\" \"\" rlogind(8C)\n.xx \"\" \"tn3270: full-screen\" \"remote login to IBM VM/CMS.\" \"\" tn3270(1)\n.xx \"\" \"rmt:\" \"remote magtape protocol module.\" \"\" rmt(8C)\n.xx \"\" \"rmail: handle\" \"remote mail received via uucp.\" \"\" rmail(1)\n.xx \"\" \"\" \"remote: remote host description file.\" \"\" remote(5)\n.xx \"\" \"rsh:\" \"remote shell.\" \"\" rsh(1C)\n.xx \"\" \"rshd:\" \"remote shell server.\" \"\" rshd(8C)\n.xx \"\" \"tip, cu: connect to a\" \"remote system.\" \"\" tip(1C)\n.xx \"\" \"talkd:\" \"remote user communication server.\" \"\" talkd(8C)\n.xx \"\" \"fingerd:\" \"remote user information server.\" \"\" fingerd(8C)\n.xx \"\" \"uupoll: poll a\" \"remote UUCP site.\" \"\" uupoll(8C)\n.xx \"\" \"unlink:\" \"remove a directory entry.\" \"\" unlink(3F)\n.xx \"\" \"rmdir:\" \"remove a directory file.\" \"\" rmdir(2)\n.xx \"\" \"unalias:\" \"remove aliases.\" \"\" csh(1)\n.xx \"\" \"flock: apply or\" \"remove an advisory lock on an open file.\" \"\" flock(2)\n.xx \"\" \"colrm:\" \"remove columns from a file.\" \"\" colrm(1)\n.xx \"\" \"unlink:\" \"remove directory entry.\" \"\" unlink(2)\n.xx \"\" \"unsetenv:\" \"remove environment variables.\" \"\" csh(1)\n.xx \"\" \"mount, umount: mount or\" \"remove file system.\" \"\" mount(2)\n.xx \"\" \"unifdef:\" \"remove ifdef'ed lines.\" \"\" unifdef(1)\n.xx \"\" \"lprm:\" \"remove jobs from the line printer spooling queue.\" \"\" lprm(1)\n.xx \"\" \"atrm:\" \"remove jobs spooled by at.\" \"\" atrm(1)\n.xx \"\" \"deroff:\" \"remove nroff, troff, tbl and eqn constructs.\" \"\" deroff(1)\n.xx \"\" \"unlimit:\" \"remove resource limitiations.\" \"\" csh(1)\n.xx \"\" \"strip:\" \"remove symbols and relocation bits.\" \"\" strip(1)\n.xx \"\" \"rmdir, rm:\" \"remove (unlink) directories or files.\" \"\" rmdir(1)\n.xx \"\" \"rm, rmdir:\" \"remove (unlink) files or directories.\" \"\" rm(1)\n.xx \"\" \"insque,\" \"remque: insert/remove element from a queue.\" \"\" insque(3)\n.xx \"\" \"rename:\" \"rename a file.\" \"\" rename(3F)\n.xx \"\" \"\" \"rename: change the name of a file.\" \"\" rename(2)\n.xx \"\" \"mv: move or\" \"rename files.\" \"\" mv(1)\n.xx \"\" \"\" \"rename: rename a file.\" \"\" rename(3F)\n.xx \"\" \"\" \"renice: alter priority of running processes.\" \"\" renice(8)\n.xx \"\" \"fsck: file system consistency check and interactive\" \"repair.\" \"\" fsck(8)\n.xx \"\" \"trpfpe, fpecnt: trap and\" \"repair floating point faults.\" \"\" trpfpe(3F)\n.xx \"\" \"trapov: trap and\" \"repair floating point overflow.\" \"\" trapov(3F)\n.xx \"\" \"while:\" \"repeat commands conditionally.\" \"\" csh(1)\n.xx \"\" \"\" \"repeat: execute command repeatedly.\" \"\" csh(1)\n.xx \"\" \"uniq: report\" \"repeated lines in a file.\" \"\" uniq(1)\n.xx \"\" \"repeat: execute command\" \"repeatedly.\" \"\" csh(1)\n.xx \"\" \"yes: be\" \"repetitively affirmative.\" \"\" yes(1)\n.xx \"\" \"iostat:\" \"report I/O statistics.\" \"\" iostat(1)\n.xx \"\" \"uniq:\" \"report repeated lines in a file.\" \"\" uniq(1)\n.xx \"\" \"sendbug: mail a system bug\" \"report to 4bsd-bugs.\" \"\" sendbug(1)\n.xx \"\" \"vmstat:\" \"report virtual memory statistics.\" \"\" vmstat(1)\n.xx \"\" \"bugfiler: file bug\" \"reports in folders automatically.\" \"\" bugfiler(8)\n.xx \"\" \"fseek, ftell:\" \"reposition a file on a logical unit.\" \"\" fseek(3F)\n.xx \"\" \"fseek, ftell, rewind:\" \"reposition a stream.\" \"\" fseek(3S)\n.xx \"\" \"\" \"repquota: summarize quotas for a file system.\" \"\" repquota(8)\n.xx \"\" \"notify:\" \"request immediate notification.\" \"\" csh(1)\n.xx \"\" \"lock:\" \"reserve a terminal.\" \"\" lock(1)\n.xx \"\" \"res_mkquery, res_send,\" \"res_init, dn_comp, dn_expand: resolver routines.\" \"\" resolver(3)\n.xx \"dn_expand: resolver routines.\" \"\" \"res_mkquery, res_send, res_init, dn_comp,\" \"\" resolver(3)\n.xx \"\" \"arp: address\" \"resolution display and control.\" \"\" arp(8C)\n.xx \"\" \"arp: Address\" \"Resolution Protocol.\" \"\" arp(4P)\n.xx \"\" \"\" \"resolver configuration file.\" \"\" resolver(5)\n.xx \"\" \"res_send, res_init, dn_comp, dn_expand:\" \"resolver routines.\" \"res_mkquery,\" resolver(3)\n.xx \"\" \"getrlimit, setrlimit: control maximum system\" \"resource consumption.\" \"\" getrlimit(2)\n.xx \"\" \"vlimit: control maximum system\" \"resource consumption.\" \"\" vlimit(3C)\n.xx \"\" \"limit: alter per-process\" \"resource limitations.\" \"\" csh(1)\n.xx \"\" \"unlimit: remove\" \"resource limitiations.\" \"\" csh(1)\n.xx \"\" \"getrusage: get information about\" \"resource utilization.\" \"\" getrusage(2)\n.xx \"\" \"vtimes: get information about\" \"resource utilization.\" \"\" vtimes(3C)\n.xx \"routines.\" \"res_mkquery,\" \"res_send, res_init, dn_comp, dn_expand: resolver\" \"\" resolver(3)\n.xx \"\" \"restore: incremental file system\" \"restore.\" \"\" restore(8)\n.xx \"\" \"rrestore:\" \"restore a file system dump across the network.\" \"\" rrestore(8C)\n.xx \"\" \"\" \"restore: incremental file system restore.\" \"\" restore(8)\n.xx \"\" \"suspend: suspend a shell,\" \"resuming its superior.\" \"\" csh(1)\n.xx \"\" \"mset:\" \"retrieve ASCII to IBM 3270 keyboard map.\" \"\" mset(1)\n.xx \"\" \"getarg, iargc:\" \"return command line arguments.\" \"\" getarg(3F)\n.xx \"\" \"fdate:\" \"return date and time in an ASCII string.\" \"\" fdate(3F)\n.xx \"\" \"idate, itime:\" \"return date or time in numerical form.\" \"\" idate(3F)\n.xx \"\" \"etime, dtime:\" \"return elapsed execution time.\" \"\" etime(3F)\n.xx \"\" \"flmin, flmax, ffrac, dflmin, dflmax, dffrac, inmax:\" \"return extreme values.\" \"\" flmin(3F)\n.xx \"\" \"sigreturn:\" \"return from signal.\" \"\" sigreturn(2)\n.xx \"\" \"vacation:\" \"return ``I am on vacation'' indication.\" \"\" vacation(1)\n.xx \"\" \"rand, drand, irand:\" \"return random values.\" \"\" rand(3F)\n.xx \"\" \"rexec:\" \"return stream to a remote command.\" \"\" rexec(3)\n.xx \"\" \"time, ctime, ltime, gmtime:\" \"return system time.\" \"\" time(3F)\n.xx \"\" \"loc:\" \"return the address of an object.\" \"\" loc(3F)\n.xx \"\" \"rcmd, rresvport, ruserok: routines for\" \"returning a stream to a remote command.\" \"\" rcmd(3)\n.xx \"\" \"\" \"rev: reverse lines of a file.\" \"\" rev(1)\n.xx \"\" \"col: filter\" \"reverse line feeds.\" \"\" col(1)\n.xx \"\" \"rev:\" \"reverse lines of a file.\" \"\" rev(1)\n.xx \"\" \"lastcomm: show last commands executed in\" \"reverse order.\" \"\" lastcomm(1)\n.xx \"\" \"fseek, ftell,\" \"rewind: reposition a stream.\" \"\" fseek(3S)\n.xx \"\" \"opendir, readdir, telldir, seekdir,\" \"rewinddir, closedir: directory operations.\" \"\" directory(3)\n.xx \"\" \"\" \"rexec: return stream to a remote command.\" \"\" rexec(3)\n.xx \"\" \"\" \"rexecd: remote execution server.\" \"\" rexecd(8C)\n.xx \"\" \"index,\" \"rindex, lnblnk, len: tell about character objects.\" \"\" index(3F)\n.xx \"\" \"strcmp, strncmp, strcpy, strncpy, strlen, index,\" \"rindex: string operations.\" \"strcat, strncat,\" string(3)\n.xx \"\" \"vv: Proteon proNET 10 Megabit\" \"ring.\" \"\" vv(4)\n.xx \"round-to-nearest functions.\" \"fabs, floor, ceil,\" \"rint: absolute value, floor, ceiling, and\" \"\" floor(3M)\n.xx \"\" \"lptest: generate lineprinter\" \"ripple pattern.\" \"\" lptest(1)\n.xx \"\" \"hk: RK6-11/RK06 and\" \"RK07 moving head disk.\" \"\" hk(4)\n.xx \"\" \"hk:\" \"RK6-11/RK06 and RK07 moving head disk.\" \"\" hk(4)\n.xx \"\" \"crl: VAX 8600 console\" \"RL02 interface.\" \"\" crl(4)\n.xx \"\" \"\" \"rlogin: remote login.\" \"\" rlogin(1C)\n.xx \"\" \"\" \"rlogind: remote login server.\" \"\" rlogind(8C)\n.xx \"\" \"rmdir,\" \"rm: remove (unlink) directories or files.\" \"\" rmdir(1)\n.xx \"\" \"\" \"rm, rmdir: remove (unlink) files or directories.\" \"\" rm(1)\n.xx \"\" \"\" \"rmail: handle remote mail received via uucp.\" \"\" rmail(1)\n.xx \"\" \"\" \"rmdir: remove a directory file.\" \"\" rmdir(2)\n.xx \"\" \"rm,\" \"rmdir: remove (unlink) files or directories.\" \"\" rm(1)\n.xx \"\" \"\" \"rmdir, rm: remove (unlink) directories or files.\" \"\" rmdir(1)\n.xx \"\" \"\" \"rmt: remote magtape protocol module.\" \"\" rmt(8C)\n.xx \"\" \"robots: fight off villainous\" \"robots.\" \"\" robots(6)\n.xx \"\" \"\" \"robots: fight off villainous robots.\" \"\" robots(6)\n.xx \"\" \"\" \"roffbib: run off bibliographic database.\" \"\" roffbib(1)\n.xx \"\" \"\" \"rogue: Exploring The Dungeons of Doom.\" \"\" rogue(6)\n.xx \"\" \"cbrt, sqrt: cube root, square\" \"root.\" \"\" sqrt(3M)\n.xx \"\" \"chroot: change\" \"root directory.\" \"\" chroot(2)\n.xx \"\" \"cbrt, sqrt: cube\" \"root, square root.\" \"\" sqrt(3M)\n.xx \"\" \"ceil, rint: absolute value, floor, ceiling, and\" \"round-to-nearest functions.\" \"fabs, floor,\" floor(3M)\n.xx \"\" \"\" \"route: manually manipulate the routing tables.\" \"\" route(8C)\n.xx \"\" \"\" \"routed: network routing daemon.\" \"\" routed(8C)\n.xx \"\" \"inet_netof: Internet address manipulation\" \"routines.\" \"/inet_ntoa, inet_makeaddr, inet_lnaof,\" inet(3N)\n.xx \"\" \"ns_addr, ns_ntoa: Xerox NS(tm)  address conversion\" \"routines.\" \"\" ns(3N)\n.xx \"\" \"res_send, res_init, dn_comp, dn_expand: resolver\" \"routines.\" \"res_mkquery,\" resolver(3)\n.xx \"\" \"tgoto, tputs: terminal independent operation\" \"routines.\" \"tgetent, tgetnum, tgetflag, tgetstr,\" termcap(3X)\n.xx \"\" \"setstate: better random number generator;\" \"routines for changing generators.\" \"/initstate,\" random(3)\n.xx \"command.\" \"rcmd, rresvport, ruserok:\" \"routines for returning a stream to a remote\" \"\" rcmd(3)\n.xx \"\" \"routed: network\" \"routing daemon.\" \"\" routed(8C)\n.xx \"\" \"XNSrouted: NS\" \"Routing Information Protocol daemon.\" \"\" XNSrouted(8C)\n.xx \"\" \"route: manually manipulate the\" \"routing tables.\" \"\" route(8C)\n.xx \"mout,/\" \"madd, msub, mult, mdiv, pow, gcd, invert,\" \"rpow, msqrt, mcmp, move, min, omin, fmin, m_in,\" \"\" mp(3X)\n.xx \"network.\" \"\" \"rrestore: restore a file system dump across the\" \"\" rrestore(8C)\n.xx \"to a remote command.\" \"rcmd,\" \"rresvport, ruserok: routines for returning a stream\" \"\" rcmd(3)\n.xx \"\" \"\" \"rsh: remote shell.\" \"\" rsh(1C)\n.xx \"\" \"\" \"rshd: remote shell server.\" \"\" rshd(8C)\n.xx \"\" \"bit: and, or, xor, not,\" \"rshift, lshift bitwise functions.\" \"\" bit(3F)\n.xx \"\" \"atq: print the queue of jobs waiting to be\" \"run.\" \"\" atq(1)\n.xx \"\" \"nice, nohup:\" \"run a command at low priority (\\fIsh\\fR only).\" \"\" nice(1)\n.xx \"\" \"nohup:\" \"run command immune to hangups.\" \"\" csh(1)\n.xx \"\" \"nice:\" \"run low priority process.\" \"\" csh(1)\n.xx \"\" \"roffbib:\" \"run off bibliographic database.\" \"\" roffbib(1)\n.xx \"\" \"gcore: get core images of\" \"running processes.\" \"\" gcore(1)\n.xx \"\" \"renice: alter priority of\" \"running processes.\" \"\" renice(8)\n.xx \"\" \"\" \"ruptime: show host status of local machines.\" \"\" ruptime(1C)\n.xx \"remote command.\" \"rcmd, rresvport,\" \"ruserok: routines for returning a stream to a\" \"\" rcmd(3)\n.xx \"\" \"\" \"rwho: who's logged in on local machines.\" \"\" rwho(1C)\n.xx \"\" \"\" \"rwhod: system status server.\" \"\" rwhod(8C)\n.xx \"\" \"\" \"rx: DEC RX02 floppy disk interface.\" \"\" rx(4)\n.xx \"\" \"rx: DEC\" \"RX02 floppy disk interface.\" \"\" rx(4)\n.xx \"\" \"\" \"rxformat: format floppy disks.\" \"\" rxformat(8V)\n.xx \"\" \"\" \"sa, accton: system accounting.\" \"\" sa(8)\n.xx \"\" \"\" \"sail: multi-user wooden ships and iron men.\" \"\" sail(6)\n.xx \"\" \"savecore:\" \"save a core dump of the operating system.\" \"\" savecore(8)\n.xx \"\" \"\" \"savecore: save a core dump of the operating system.\" \"\" savecore(8)\n.xx \"\" \"brk,\" \"sbrk: change data segment size.\" \"\" brk(2)\n.xx \"\" \"copysign, drem, finite, logb,\" \"scalb: copysign, remainder, exponent manipulations.\" \"\" ieee(3M)\n.xx \"\" \"scandir, alphasort:\" \"scan a directory.\" \"\" scandir(3)\n.xx \"\" \"\" \"scandir, alphasort: scan a directory.\" \"\" scandir(3)\n.xx \"\" \"\" \"scanf, fscanf, sscanf: formatted input conversion.\" \"\" scanf(3S)\n.xx \"\" \"awk: pattern\" \"scanning and processing language.\" \"\" awk(1)\n.xx \"\" \"\" \"sccs: front end for the SCCS subsystem.\" \"\" sccs(1)\n.xx \"\" \"sccs: front end for the\" \"SCCS subsystem.\" \"\" sccs(1)\n.xx \"\" \"alarm:\" \"schedule signal after specified time.\" \"\" alarm(3C)\n.xx \"\" \"ualarm:\" \"schedule signal after specified time.\" \"\" ualarm(3)\n.xx \"\" \"getpriority, setpriority: get/set program\" \"scheduling priority.\" \"\" getpriority(2)\n.xx \"\" \"clear: clear terminal\" \"screen.\" \"\" clear(1)\n.xx \"\" \"curses:\" \"screen functions with ``optimal'' cursor motion.\" \"\" curses(3X)\n.xx \"ex.\" \"vi:\" \"screen oriented (visual) display editor based on\" \"\" vi(1)\n.xx \"\" \"rc: command\" \"script for auto-reboot and daemons.\" \"\" rc(8)\n.xx \"\" \"\" \"script: make typescript of terminal session.\" \"\" script(1)\n.xx \"\" \"onintr: process interrupts in command\" \"scripts.\" \"\" csh(1)\n.xx \"\" \"/min, omin, fmin, m_in, mout, omout, fmout, m_out,\" \"sdiv, itom: multiple precision integer arithmetic.\" \"\" mp(3X)\n.xx \"\" \"grep, egrep, fgrep:\" \"search a file for a pattern.\" \"\" grep(1)\n.xx \"\" \"xsend, xget, enroll:\" \"secret mail.\" \"\" xsend(1)\n.xx \"\" \"bad144: read/write dec standard 144 bad\" \"sector information.\" \"\" bad144(8)\n.xx \"\" \"badsect: create files to contain bad\" \"sectors.\" \"\" badsect(8)\n.xx \"\" \"\" \"sed: stream editor.\" \"\" sed(1)\n.xx \"\" \"opendir, readdir, telldir,\" \"seekdir, rewinddir, closedir: directory operations.\" \"\" directory(3)\n.xx \"\" \"brk, sbrk: change data\" \"segment size.\" \"\" brk(2)\n.xx \"\" \"comm:\" \"select or reject lines common to two sorted files.\" \"\" comm(1)\n.xx \"\" \"\" \"select: synchronous I/O multiplexing.\" \"\" select(2)\n.xx \"\" \"case:\" \"selector in switch.\" \"\" csh(1)\n.xx \"\" \"uusend:\" \"send a file to a remote host.\" \"\" uusend(1C)\n.xx \"\" \"send, sendto, sendmsg:\" \"send a message from a socket.\" \"\" send(2)\n.xx \"\" \"kill:\" \"send a signal to a process.\" \"\" kill(3F)\n.xx \"\" \"mail:\" \"send and receive mail.\" \"\" mail(1)\n.xx \"\" \"ping:\" \"send ICMP ECHO_REQUEST packets to network hosts.\" \"\" ping(8)\n.xx \"\" \"sendmail:\" \"send mail over the internet.\" \"\" sendmail(8)\n.xx \"\" \"binmail:\" \"send or receive mail among users.\" \"\" binmail(1)\n.xx \"socket.\" \"\" \"send, sendto, sendmsg: send a message from a\" \"\" send(2)\n.xx \"\" \"kill:\" \"send signal to a process.\" \"\" kill(2)\n.xx \"\" \"killpg:\" \"send signal to a process group.\" \"\" killpg(2)\n.xx \"\" \"\" \"sendbug: mail a system bug report to 4bsd-bugs.\" \"\" sendbug(1)\n.xx \"\" \"aliases: aliases file for\" \"sendmail.\" \"\" aliases(5)\n.xx \"\" \"\" \"sendmail: send mail over the internet.\" \"\" sendmail(8)\n.xx \"\" \"send, sendto,\" \"sendmsg: send a message from a socket.\" \"\" send(2)\n.xx \"\" \"send,\" \"sendto, sendmsg: send a message from a socket.\" \"\" send(2)\n.xx \"\" \"diction, explain: print wordy\" \"sentences; thesaurus for diction.\" \"\" diction(1)\n.xx \"\" \"spp: Xerox\" \"Sequenced Packet Protocol.\" \"\" spp(4P)\n.xx \"\" \"trsp: transliterate\" \"sequenced packet protocol trace.\" \"\" trsp(8C)\n.xx \"\" \"slattach: attach\" \"serial lines as network interfaces.\" \"\" slattach(8C)\n.xx \"\" \"comsat: biff\" \"server.\" \"\" comsat(8C)\n.xx \"\" \"fingerd: remote user information\" \"server.\" \"\" fingerd(8C)\n.xx \"\" \"ftpd: DARPA Internet File Transfer Protocol\" \"server.\" \"\" ftpd(8C)\n.xx \"\" \"named: Internet domain name\" \"server.\" \"\" named(8)\n.xx \"\" \"rexecd: remote execution\" \"server.\" \"\" rexecd(8C)\n.xx \"\" \"rlogind: remote login\" \"server.\" \"\" rlogind(8C)\n.xx \"\" \"rshd: remote shell\" \"server.\" \"\" rshd(8C)\n.xx \"\" \"rwhod: system status\" \"server.\" \"\" rwhod(8C)\n.xx \"\" \"talkd: remote user communication\" \"server.\" \"\" talkd(8C)\n.xx \"\" \"telnetd: DARPA TELNET protocol\" \"server.\" \"\" telnetd(8C)\n.xx \"\" \"tftpd: DARPA Trivial File Transfer Protocol\" \"server.\" \"\" tftpd(8C)\n.xx \"\" \"timed: time\" \"server daemon.\" \"\" timed(8)\n.xx \"\" \"\" \"services: service name data base.\" \"\" services(5)\n.xx \"\" \"logout: end\" \"session.\" \"\" csh(1)\n.xx \"\" \"script: make typescript of terminal\" \"session.\" \"\" script(1)\n.xx \"\" \"ascii: map of ASCII character\" \"set.\" \"\" ascii(7)\n.xx \"\" \"stty, gtty:\" \"set and get terminal state (defunct).\" \"\" stty(3C)\n.xx \"\" \"sigstack:\" \"set and/or get signal stack context.\" \"\" sigstack(2)\n.xx \"\" \"\" \"set: change value of shell variable.\" \"\" csh(1)\n.xx \"\" \"sigsetmask:\" \"set current signal mask.\" \"\" sigsetmask(2)\n.xx \"\" \"umask:\" \"set file creation mode mask.\" \"\" umask(2)\n.xx \"\" \"utime:\" \"set file times.\" \"\" utime(3C)\n.xx \"\" \"utimes:\" \"set file times.\" \"\" utimes(2)\n.xx \"\" \"setgroups:\" \"set group access list.\" \"\" setgroups(2)\n.xx \"\" \"apply: apply a command to a\" \"set of arguments.\" \"\" apply(1)\n.xx \"\" \"getsockopt, setsockopt: get and\" \"set options on sockets.\" \"\" getsockopt(2)\n.xx \"\" \"hostid:\" \"set or print identifier of current host system.\" \"\" hostid(1)\n.xx \"\" \"hostname:\" \"set or print name of current host system.\" \"\" hostname(1)\n.xx \"\" \"setpgrp:\" \"set process group.\" \"\" setpgrp(2)\n.xx \"\" \"nice:\" \"set program priority.\" \"\" nice(3C)\n.xx \"\" \"setregid:\" \"set real and effective group ID.\" \"\" setregid(2)\n.xx \"\" \"setreuid:\" \"set real and effective user ID's.\" \"\" setreuid(2)\n.xx \"\" \"eval, exec, exit, export, login, read, readonly,\" \"set, shift, times, trap, umask, wait: command/\" \"/cd,\" sh(1)\n.xx \"\" \"getty:\" \"set terminal mode.\" \"\" getty(8)\n.xx \"\" \"stty:\" \"set terminal options.\" \"\" stty(1)\n.xx \"\" \"tabs:\" \"set terminal tabs.\" \"\" tabs(1)\n.xx \"\" \"date: print and\" \"set the date.\" \"\" date(1)\n.xx \"\" \"setuid, seteuid, setruid, setgid, setegid, setrgid:\" \"set user and group ID.\" \"\" setuid(3)\n.xx \"\" \"setenv:\" \"set variable in environment.\" \"\" csh(1)\n.xx \"a stream.\" \"\" \"setbuf, setbuffer, setlinebuf: assign buffering to\" \"\" setbuf(3S)\n.xx \"stream.\" \"setbuf,\" \"setbuffer, setlinebuf: assign buffering to a\" \"\" setbuf(3S)\n.xx \"\" \"setuid, seteuid, setruid, setgid,\" \"setegid, setrgid: set user and group ID.\" \"\" setuid(3)\n.xx \"\" \"\" \"setenv: set variable in environment.\" \"\" csh(1)\n.xx \"user and group ID.\" \"setuid,\" \"seteuid, setruid, setgid, setegid, setrgid: set\" \"\" setuid(3)\n.xx \"entry.\" \"getfsent, getfsspec, getfsfile, getfstype,\" \"setfsent, endfsent: get file system descriptor file\" \"\" getfsent(3)\n.xx \"\" \"setuid, seteuid, setruid,\" \"setgid, setegid, setrgid: set user and group ID.\" \"\" setuid(3)\n.xx \"\" \"getgrent, getgrgid, getgrnam,\" \"setgrent, endgrent: get group file entry.\" \"\" getgrent(3)\n.xx \"\" \"\" \"setgroups: set group access list.\" \"\" setgroups(2)\n.xx \"\" \"gethostbyname, gethostbyaddr, gethostent,\" \"sethostent, endhostent: get network host entry.\" \"\" gethostbyname(3N)\n.xx \"host.\" \"gethostid,\" \"sethostid: get/set unique identifier of current\" \"\" gethostid(2)\n.xx \"\" \"gethostname,\" \"sethostname: get/set name of current host.\" \"\" gethostname(2)\n.xx \"\" \"getitimer,\" \"setitimer: get/set value of interval timer.\" \"\" getitimer(2)\n.xx \"\" \"\" \"setjmp, longjmp: non-local goto.\" \"\" setjmp(3)\n.xx \"\" \"crypt,\" \"setkey, encrypt: DES encryption.\" \"\" crypt(3)\n.xx \"\" \"setbuf, setbuffer,\" \"setlinebuf: assign buffering to a stream.\" \"\" setbuf(3S)\n.xx \"\" \"syslog, openlog, closelog,\" \"setlogmask: control system log.\" \"\" syslog(3)\n.xx \"\" \"getnetent, getnetbyaddr, getnetbyname,\" \"setnetent, endnetent: get network entry.\" \"\" getnetent(3N)\n.xx \"\" \"\" \"setpgrp: set process group.\" \"\" setpgrp(2)\n.xx \"\" \"getpriority,\" \"setpriority: get/set program scheduling priority.\" \"\" getpriority(2)\n.xx \"\" \"getprotoent, getprotobynumber, getprotobyname,\" \"setprotoent, endprotoent: get protocol entry.\" \"\" getprotoent(3N)\n.xx \"entry.\" \"getpwent, getpwuid, getpwnam,\" \"setpwent, endpwent, setpwfile: get password file\" \"\" getpwent(3)\n.xx \"\" \"getpwent, getpwuid, getpwnam, setpwent, endpwent,\" \"setpwfile: get password file entry.\" \"\" getpwent(3)\n.xx \"\" \"\" \"setquota: enable/disable quotas on a file system.\" \"\" setquota(2)\n.xx \"\" \"\" \"setregid: set real and effective group ID.\" \"\" setregid(2)\n.xx \"\" \"\" \"setreuid: set real and effective user ID's.\" \"\" setreuid(2)\n.xx \"\" \"setuid, seteuid, setruid, setgid, setegid,\" \"setrgid: set user and group ID.\" \"\" setuid(3)\n.xx \"consumption.\" \"getrlimit,\" \"setrlimit: control maximum system resource\" \"\" getrlimit(2)\n.xx \"group ID.\" \"setuid, seteuid,\" \"setruid, setgid, setegid, setrgid: set user and\" \"\" setuid(3)\n.xx \"\" \"getservent, getservbyport, getservbyname,\" \"setservent, endservent: get service entry.\" \"\" getservent(3N)\n.xx \"\" \"getsockopt,\" \"setsockopt: get and set options on sockets.\" \"\" getsockopt(2)\n.xx \"for changing/\" \"random, srandom, initstate,\" \"setstate: better random number generator; routines\" \"\" random(3)\n.xx \"\" \"gettimeofday,\" \"settimeofday: get/set date and time.\" \"\" gettimeofday(2)\n.xx \"\" \"getttyent, getttynam,\" \"setttyent, endttyent: get ttys file entry.\" \"\" getttyent(3)\n.xx \"set user and group ID.\" \"\" \"setuid, seteuid, setruid, setgid, setegid, setrgid:\" \"\" setuid(3)\n.xx \"\" \"getusershell,\" \"setusershell, endusershell: get legal user shells.\" \"\" getusershell(3)\n.xx \"continue, cd, eval, exec, exit, export, login,/\" \"\" \"sh, for, case, if, while, \\fB:\\fP, \\fB.\\fP, break,\" \"\" sh(1)\n.xx \"\" \"xstr: extract strings from C programs to implement\" \"shared strings.\" \"\" xstr(1)\n.xx \"\" \"exit: leave\" \"shell.\" \"\" csh(1)\n.xx \"\" \"rsh: remote\" \"shell.\" \"\" rsh(1C)\n.xx \"\" \"system: issue a\" \"shell command.\" \"\" system(3)\n.xx \"\" \"csh: a\" \"shell (command interpreter) with C-like syntax.\" \"\" csh(1)\n.xx \"\" \"eval: re-evaluate\" \"shell data.\" \"\" csh(1)\n.xx \"\" \"popd: pop\" \"shell directory stack.\" \"\" csh(1)\n.xx \"\" \"pushd: push\" \"shell directory stack.\" \"\" csh(1)\n.xx \"\" \"alias:\" \"shell macros.\" \"\" csh(1)\n.xx \"\" \"suspend: suspend a\" \"shell, resuming its superior.\" \"\" csh(1)\n.xx \"\" \"rshd: remote\" \"shell server.\" \"\" rshd(8C)\n.xx \"\" \"set: change value of\" \"shell variable.\" \"\" csh(1)\n.xx \"\" \"@: arithmetic on\" \"shell variables.\" \"\" csh(1)\n.xx \"\" \"unset: discard\" \"shell variables.\" \"\" csh(1)\n.xx \"\" \"exec: overlay\" \"shell with specified command.\" \"\" csh(1)\n.xx \"\" \"setusershell, endusershell: get legal user\" \"shells.\" \"getusershell,\" getusershell(3)\n.xx \"\" \"\" \"shift: manipulate argument list.\" \"\" csh(1)\n.xx \"\" \"/exec, exit, export, login, read, readonly, set,\" \"shift, times, trap, umask, wait: command language.\" \"\" sh(1)\n.xx \"\" \"sail: multi-user wooden\" \"ships and iron men.\" \"\" sail(6)\n.xx \"\" \"long,\" \"short: integer object conversion.\" \"\" long(3F)\n.xx \"\" \"groups:\" \"show group memberships.\" \"\" groups(1)\n.xx \"\" \"ruptime:\" \"show host status of local machines.\" \"\" ruptime(1C)\n.xx \"\" \"uptime:\" \"show how long system has been up.\" \"\" uptime(1)\n.xx \"\" \"lastcomm:\" \"show last commands executed in reverse order.\" \"\" lastcomm(1)\n.xx \"\" \"netstat:\" \"show network status.\" \"\" netstat(1)\n.xx \"\" \"uusnap:\" \"show snapshot of the UUCP system.\" \"\" uusnap(8C)\n.xx \"construct a file.\" \"what:\" \"show what versions of object modules were used to\" \"\" what(1)\n.xx \"\" \"shutdown:\" \"shut down part of a full-duplex connection.\" \"\" shutdown(2)\n.xx \"\" \"\" \"shutdown: close down the system at a given time.\" \"\" shutdown(8)\n.xx \"connection.\" \"\" \"shutdown: shut down part of a full-duplex\" \"\" shutdown(2)\n.xx \"\" \"\" \"sigblock: block signals.\" \"\" sigblock(2)\n.xx \"calls.\" \"\" \"siginterrupt: allow signals to interrupt system\" \"\" siginterrupt(3)\n.xx \"\" \"login:\" \"sign on.\" \"\" login(1)\n.xx \"\" \"pause: stop until\" \"signal.\" \"\" pause(3C)\n.xx \"\" \"signal: change the action for a\" \"signal.\" \"\" signal(3F)\n.xx \"\" \"sigreturn: return from\" \"signal.\" \"\" sigreturn(2)\n.xx \"\" \"alarm: schedule\" \"signal after specified time.\" \"\" alarm(3C)\n.xx \"\" \"ualarm: schedule\" \"signal after specified time.\" \"\" ualarm(3)\n.xx \"\" \"\" \"signal: change the action for a signal.\" \"\" signal(3F)\n.xx \"\" \"signal: simplified software\" \"signal facilities.\" \"\" signal(3C)\n.xx \"\" \"sigvec: software\" \"signal facilities.\" \"\" sigvec(2)\n.xx \"\" \"sigsetmask: set current\" \"signal mask.\" \"\" sigsetmask(2)\n.xx \"\" \"psignal, sys_siglist: system\" \"signal messages.\" \"\" psignal(3)\n.xx \"\" \"\" \"signal: simplified software signal facilities.\" \"\" signal(3C)\n.xx \"\" \"sigstack: set and/or get\" \"signal stack context.\" \"\" sigstack(2)\n.xx \"\" \"kill: send\" \"signal to a process.\" \"\" kill(2)\n.xx \"\" \"kill: send a\" \"signal to a process.\" \"\" kill(3F)\n.xx \"\" \"killpg: send\" \"signal to a process group.\" \"\" killpg(2)\n.xx \"\" \"sigblock: block\" \"signals.\" \"\" sigblock(2)\n.xx \"\" \"sigpause: atomically release blocked\" \"signals and wait for interrupt.\" \"\" sigpause(2)\n.xx \"(temporary).\" \"infnan:\" \"signals invalid floating-point operations on a VAX\" \"\" infnan(3M)\n.xx \"\" \"siginterrupt: allow\" \"signals to interrupt system calls.\" \"\" siginterrupt(3)\n.xx \"wait for interrupt.\" \"\" \"sigpause: atomically release blocked signals and\" \"\" sigpause(2)\n.xx \"\" \"\" \"sigreturn: return from signal.\" \"\" sigreturn(2)\n.xx \"\" \"\" \"sigsetmask: set current signal mask.\" \"\" sigsetmask(2)\n.xx \"\" \"\" \"sigstack: set and/or get signal stack context.\" \"\" sigstack(2)\n.xx \"\" \"\" \"sigvec: software signal facilities.\" \"\" sigvec(2)\n.xx \"\" \"signal:\" \"simplified software signal facilities.\" \"\" signal(3C)\n.xx \"\" \"tc: photoypesetter\" \"simulator.\" \"\" tc(1)\n.xx \"trigonometric functions and their inverses.\" \"\" \"sin, cos, tan, asin, acos, atan, atan2:\" \"\" sin(3M)\n.xx \"\" \"\" \"sinh, cosh, tanh: hyperbolic functions.\" \"\" sinh(3M)\n.xx \"\" \"null: data\" \"sink.\" \"\" null(4)\n.xx \"\" \"uupoll: poll a remote UUCP\" \"site.\" \"\" uupoll(8C)\n.xx \"\" \"brk, sbrk: change data segment\" \"size.\" \"\" brk(2)\n.xx \"\" \"getdtablesize: get descriptor table\" \"size.\" \"\" getdtablesize(2)\n.xx \"\" \"getpagesize: get system page\" \"size.\" \"\" getpagesize(2)\n.xx \"\" \"pagesize: print system page\" \"size.\" \"\" pagesize(1)\n.xx \"\" \"size:\" \"size of an object file.\" \"\" size(1)\n.xx \"\" \"\" \"size: size of an object file.\" \"\" size(1)\n.xx \"\" \"diskpart: calculate default disk partition\" \"sizes.\" \"\" diskpart(8)\n.xx \"interfaces.\" \"\" \"slattach: attach serial lines as network\" \"\" slattach(8C)\n.xx \"\" \"\" \"sleep: suspend execution for an interval.\" \"\" sleep(1)\n.xx \"\" \"\" \"sleep: suspend execution for an interval.\" \"\" sleep(3F)\n.xx \"\" \"\" \"sleep: suspend execution for interval.\" \"\" sleep(3)\n.xx \"\" \"spline: interpolate\" \"smooth curve.\" \"\" spline(1G)\n.xx \"\" \"\" \"snake, snscore: display chase game.\" \"\" snake(6)\n.xx \"\" \"uusnap: show\" \"snapshot of the UUCP system.\" \"\" uusnap(8C)\n.xx \"\" \"snake,\" \"snscore: display chase game.\" \"\" snake(6)\n.xx \"\" \"accept: accept a connection on a\" \"socket.\" \"\" accept(2)\n.xx \"\" \"bind: bind a name to a\" \"socket.\" \"\" bind(2)\n.xx \"\" \"connect: initiate a connection on a\" \"socket.\" \"\" connect(2)\n.xx \"\" \"listen: listen for connections on a\" \"socket.\" \"\" listen(2)\n.xx \"\" \"recv, recvfrom, recvmsg: receive a message from a\" \"socket.\" \"\" recv(2)\n.xx \"\" \"send, sendto, sendmsg: send a message from a\" \"socket.\" \"\" send(2)\n.xx \"\" \"\" \"socket: create an endpoint for communication.\" \"\" socket(2)\n.xx \"\" \"imp: IMP raw\" \"socket interface.\" \"\" imp(4P)\n.xx \"\" \"getsockname: get\" \"socket name.\" \"\" getsockname(2)\n.xx \"\" \"\" \"socketpair: create a pair of connected sockets.\" \"\" socketpair(2)\n.xx \"\" \"getsockopt, setsockopt: get and set options on\" \"sockets.\" \"\" getsockopt(2)\n.xx \"\" \"socketpair: create a pair of connected\" \"sockets.\" \"\" socketpair(2)\n.xx \"\" \"\" \"soelim: eliminate \\&.so's from nroff input.\" \"\" soelim(1)\n.xx \"\" \"lo:\" \"software loopback network interface.\" \"\" lo(4)\n.xx \"in ip packets..\" \"nsip:\" \"software network interface encapsulating ns packets\" \"\" nsip(4)\n.xx \"\" \"signal: simplified\" \"software signal facilities.\" \"\" signal(3C)\n.xx \"\" \"sigvec:\" \"software signal facilities.\" \"\" sigvec(2)\n.xx \"\" \"canfield, cfscores: the\" \"solitaire card game canfield.\" \"\" canfield(6)\n.xx \"\" \"qsort: quicker\" \"sort.\" \"\" qsort(3)\n.xx \"\" \"qsort: quick\" \"sort.\" \"\" qsort(3F)\n.xx \"\" \"tsort: topological\" \"sort.\" \"\" tsort(1)\n.xx \"\" \"sortbib:\" \"sort bibliographic database.\" \"\" sortbib(1)\n.xx \"\" \"sort:\" \"sort or merge files.\" \"\" sort(1)\n.xx \"\" \"\" \"sort: sort or merge files.\" \"\" sort(1)\n.xx \"\" \"\" \"sortbib: sort bibliographic database.\" \"\" sortbib(1)\n.xx \"\" \"comm: select or reject lines common to two\" \"sorted files.\" \"\" comm(1)\n.xx \"\" \"look: find lines in a\" \"sorted list.\" \"\" look(1)\n.xx \"\" \"soelim: eliminate\" \"\\&.so's from nroff input.\" \"\" soelim(1)\n.xx \"\" \"soelim: eliminate \\&.\" \"so's from nroff input.\" \"\" soelim(1)\n.xx \"\" \"indent: indent and format C program\" \"source.\" \"\" indent(1)\n.xx \"\" \"mkstr: create an error message file by massaging C\" \"source.\" \"\" mkstr(1)\n.xx \"\" \"whereis: locate\" \"source, binary, and or manual for program.\" \"\" whereis(1)\n.xx \"\" \"\" \"source: read commands from file.\" \"\" csh(1)\n.xx \"\" \"line, circle, arc, move, cont, point, linemod,\" \"space, closepl: graphics interface.\" \"/erase, label,\" plot(3X)\n.xx \"\" \"expand, unexpand: expand tabs to\" \"spaces, and vice versa.\" \"\" expand(1)\n.xx \"way.\" \"vfork:\" \"spawn new process in a virtual memory efficient\" \"\" vfork(2)\n.xx \"\" \"exec: overlay shell with\" \"specified command.\" \"\" csh(1)\n.xx \"\" \"truncate: truncate a file to a\" \"specified length.\" \"\" truncate(2)\n.xx \"\" \"alarm: schedule signal after\" \"specified time.\" \"\" alarm(3C)\n.xx \"\" \"alarm: execute a subroutine after a\" \"specified time.\" \"\" alarm(3F)\n.xx \"\" \"ualarm: schedule signal after\" \"specified time.\" \"\" ualarm(3)\n.xx \"\" \"swapon:\" \"specify additional device for paging and swapping.\" \"\" swapon(8)\n.xx \"\" \"\" \"spell, spellin, spellout: find spelling errors.\" \"\" spell(1)\n.xx \"\" \"spell,\" \"spellin, spellout: find spelling errors.\" \"\" spell(1)\n.xx \"\" \"spell, spellin, spellout: find\" \"spelling errors.\" \"\" spell(1)\n.xx \"\" \"spell, spellin,\" \"spellout: find spelling errors.\" \"\" spell(1)\n.xx \"\" \"\" \"spline: interpolate smooth curve.\" \"\" spline(1G)\n.xx \"\" \"split:\" \"split a file into pieces.\" \"\" split(1)\n.xx \"files.\" \"fsplit:\" \"split a multi-routine Fortran file into individual\" \"\" fsplit(1)\n.xx \"\" \"frexp, ldexp, modf:\" \"split into mantissa and exponent.\" \"\" frexp(3)\n.xx \"\" \"\" \"split: split a file into pieces.\" \"\" split(1)\n.xx \"\" \"uuclean: uucp\" \"spool directory clean-up.\" \"\" uuclean(8C)\n.xx \"\" \"lpq:\" \"spool queue examination program.\" \"\" lpq(1)\n.xx \"\" \"atrm: remove jobs\" \"spooled by at.\" \"\" atrm(1)\n.xx \"\" \"lprm: remove jobs from the line printer\" \"spooling queue.\" \"\" lprm(1)\n.xx \"\" \"\" \"spp: Xerox Sequenced Packet Protocol.\" \"\" spp(4P)\n.xx \"\" \"printf, fprintf,\" \"sprintf: formatted output conversion.\" \"\" printf(3S)\n.xx \"\" \"cbrt,\" \"sqrt: cube root, square root.\" \"\" sqrt(3M)\n.xx \"\" \"cbrt, sqrt: cube root,\" \"square root.\" \"\" sqrt(3M)\n.xx \"\" \"rand,\" \"srand: random number generator.\" \"\" rand(3C)\n.xx \"generator; routines for changing/\" \"random,\" \"srandom, initstate, setstate: better random number\" \"\" random(3)\n.xx \"\" \"scanf, fscanf,\" \"sscanf: formatted input conversion.\" \"\" scanf(3S)\n.xx \"\" \"\" \"stab: symbol table types.\" \"\" stab(5)\n.xx \"\" \"popd: pop shell directory\" \"stack.\" \"\" csh(1)\n.xx \"\" \"pushd: push shell directory\" \"stack.\" \"\" csh(1)\n.xx \"\" \"sigstack: set and/or get signal\" \"stack context.\" \"\" sigstack(2)\n.xx \"\" \"drtest:\" \"standalone disk test program.\" \"\" drtest(8)\n.xx \"\" \"bad144: read/write dec\" \"standard 144 bad sector information.\" \"\" bad144(8)\n.xx \"\" \"stdio:\" \"standard buffered input/output package.\" \"\" stdio(3S)\n.xx \"\" \"htable: convert NIC\" \"standard format host tables.\" \"\" htable(8)\n.xx \"\" \"ddn: DDN\" \"Standard Mode X.25 IMP interface.\" \"\" ddn(4)\n.xx \"\" \"\" \"stat, lstat, fstat: get file status.\" \"\" stat(2)\n.xx \"\" \"\" \"stat, lstat, fstat: get file status.\" \"\" stat(3F)\n.xx \"\" \"stty, gtty: set and get terminal\" \"state (defunct).\" \"\" stty(3C)\n.xx \"\" \"fsync: synchronize a file's in-core\" \"state with that on disk.\" \"\" fsync(2)\n.xx \"\" \"if: conditional\" \"statement.\" \"\" csh(1)\n.xx \"\" \"fstab:\" \"static information about the filesystems.\" \"\" fstab(5)\n.xx \"\" \"hashstat: print command hashing\" \"statistics.\" \"\" csh(1)\n.xx \"\" \"iostat: report I/O\" \"statistics.\" \"\" iostat(1)\n.xx \"\" \"vmstat: report virtual memory\" \"statistics.\" \"\" vmstat(1)\n.xx \"\" \"systat: display system\" \"statistics on a crt.\" \"\" systat(1)\n.xx \"\" \"exit: terminate process with\" \"status.\" \"\" exit(3F)\n.xx \"\" \"netstat: show network\" \"status.\" \"\" netstat(1)\n.xx \"\" \"ps: process\" \"status.\" \"\" ps(1)\n.xx \"\" \"stat, lstat, fstat: get file\" \"status.\" \"\" stat(2)\n.xx \"\" \"stat, lstat, fstat: get file\" \"status.\" \"\" stat(3F)\n.xx \"\" \"ferror, feof, clearerr, fileno: stream\" \"status inquiries.\" \"\" ferror(3S)\n.xx \"\" \"sysline: display system status on\" \"status line of a terminal.\" \"\" sysline(1)\n.xx \"\" \"ruptime: show host\" \"status of local machines.\" \"\" ruptime(1C)\n.xx \"\" \"sysline: display system\" \"status on status line of a terminal.\" \"\" sysline(1)\n.xx \"\" \"rwhod: system\" \"status server.\" \"\" rwhod(8C)\n.xx \"\" \"\" \"stdio: standard buffered input/output package.\" \"\" stdio(3S)\n.xx \"directories.\" \"\" \"sticky: persistent text and append-only\" \"\" sticky(8)\n.xx \"\" \"\" \"stop: halt a job or process.\" \"\" csh(1)\n.xx \"\" \"halt:\" \"stop the processor.\" \"\" halt(8)\n.xx \"\" \"pause:\" \"stop until signal.\" \"\" pause(3C)\n.xx \"\" \"icheck: file system\" \"storage consistency check.\" \"\" icheck(8)\n.xx \"\" \"up: unibus\" \"storage module controller/drives.\" \"\" up(4)\n.xx \"subroutines.\" \"dbminit, fetch,\" \"store, delete, firstkey, nextkey: data base\" \"\" dbm(3X)\n.xx \"strlen, index, rindex: string operations.\" \"\" \"strcat, strncat, strcmp, strncmp, strcpy, strncpy,\" \"\" string(3)\n.xx \"rindex: string operations.\" \"strcat, strncat,\" \"strcmp, strncmp, strcpy, strncpy, strlen, index,\" \"\" string(3)\n.xx \"operations.\" \"strcat, strncat, strcmp, strncmp,\" \"strcpy, strncpy, strlen, index, rindex: string\" \"\" string(3)\n.xx \"\" \"fclose, fflush: close or flush a\" \"stream.\" \"\" fclose(3S)\n.xx \"\" \"fopen, freopen, fdopen: open a\" \"stream.\" \"\" fopen(3S)\n.xx \"\" \"fseek, ftell, rewind: reposition a\" \"stream.\" \"\" fseek(3S)\n.xx \"\" \"getchar, fgetc, getw: get character or word from\" \"stream.\" \"getc,\" getc(3S)\n.xx \"\" \"gets, fgets: get a string from a\" \"stream.\" \"\" gets(3S)\n.xx \"\" \"putchar, fputc, putw: put character or word on a\" \"stream.\" \"putc,\" putc(3S)\n.xx \"\" \"puts, fputs: put a string on a\" \"stream.\" \"\" puts(3S)\n.xx \"\" \"setbuffer, setlinebuf: assign buffering to a\" \"stream.\" \"setbuf,\" setbuf(3S)\n.xx \"\" \"ungetc: push character back into input\" \"stream.\" \"\" ungetc(3S)\n.xx \"\" \"sed:\" \"stream editor.\" \"\" sed(1)\n.xx \"\" \"ferror, feof, clearerr, fileno:\" \"stream status inquiries.\" \"\" ferror(3S)\n.xx \"\" \"rcmd, rresvport, ruserok: routines for returning a\" \"stream to a remote command.\" \"\" rcmd(3)\n.xx \"\" \"rexec: return\" \"stream to a remote command.\" \"\" rexec(3)\n.xx \"\" \"fdate: return date and time in an ASCII\" \"string.\" \"\" fdate(3F)\n.xx \"\" \"gets, fgets: get a\" \"string from a stream.\" \"\" gets(3S)\n.xx \"\" \"puts, fputs: put a\" \"string on a stream.\" \"\" puts(3S)\n.xx \"\" \"bcopy, bcmp, bzero, ffs: bit and byte\" \"string operations.\" \"\" bstring(3)\n.xx \"\" \"strncmp, strcpy, strncpy, strlen, index, rindex:\" \"string operations.\" \"strcat, strncat, strcmp,\" string(3)\n.xx \"\" \"extract strings from C programs to implement shared\" \"strings.\" \"xstr:\" xstr(1)\n.xx \"other binary, file.\" \"\" \"strings: find the printable strings in a object, or\" \"\" strings(1)\n.xx \"strings.\" \"xstr: extract\" \"strings from C programs to implement shared\" \"\" xstr(1)\n.xx \"\" \"strings: find the printable\" \"strings in a object, or other binary, file.\" \"\" strings(1)\n.xx \"\" \"basename:\" \"strip filename affixes.\" \"\" basename(1)\n.xx \"\" \"\" \"strip: remove symbols and relocation bits.\" \"\" strip(1)\n.xx \"\" \"strcat, strncat, strcmp, strncmp, strcpy, strncpy,\" \"strlen, index, rindex: string operations.\" \"\" string(3)\n.xx \"index, rindex: string operations.\" \"strcat,\" \"strncat, strcmp, strncmp, strcpy, strncpy, strlen,\" \"\" string(3)\n.xx \"string operations.\" \"strcat, strncat, strcmp,\" \"strncmp, strcpy, strncpy, strlen, index, rindex:\" \"\" string(3)\n.xx \"\" \"strcat, strncat, strcmp, strncmp, strcpy,\" \"strncpy, strlen, index, rindex: string operations.\" \"\" string(3)\n.xx \"\" \"\" \"struct: structure Fortran programs.\" \"\" struct(1)\n.xx \"\" \"struct:\" \"structure Fortran programs.\" \"\" struct(1)\n.xx \"\" \"\" \"stty, gtty: set and get terminal state (defunct).\" \"\" stty(3C)\n.xx \"\" \"\" \"stty: set terminal options.\" \"\" stty(1)\n.xx \"document.\" \"\" \"style: analyze surface characteristics of a\" \"\" style(1)\n.xx \"\" \"\" \"su: substitute user id temporarily.\" \"\" su(1)\n.xx \"\" \"alarm: execute a\" \"subroutine after a specified time.\" \"\" alarm(3F)\n.xx \"\" \"fetch, store, delete, firstkey, nextkey: data base\" \"subroutines.\" \"dbminit,\" dbm(3X)\n.xx \"\" \"dbm_nextkey, dbm_error, dbm_clearerr: data base\" \"subroutines.\" \"/dbm_store, dbm_delete, dbm_firstkey,\" ndbm(3)\n.xx \"\" \"lib2648:\" \"subroutines for the HP 2648 graphics terminal.\" \"\" lib2648(3X)\n.xx \"\" \"su:\" \"substitute user id temporarily.\" \"\" su(1)\n.xx \"\" \"sccs: front end for the SCCS\" \"subsystem.\" \"\" sccs(1)\n.xx \"\" \"sum:\" \"sum and count blocks in a file.\" \"\" sum(1)\n.xx \"\" \"\" \"sum: sum and count blocks in a file.\" \"\" sum(1)\n.xx \"\" \"du:\" \"summarize disk usage.\" \"\" du(1)\n.xx \"\" \"quot:\" \"summarize file system ownership.\" \"\" quot(8)\n.xx \"\" \"repquota:\" \"summarize quotas for a file system.\" \"\" repquota(8)\n.xx \"\" \"sync: update the\" \"super block.\" \"\" sync(8)\n.xx \"\" \"update: periodically update the\" \"super block.\" \"\" update(8)\n.xx \"\" \"sync: update\" \"super-block.\" \"\" sync(2)\n.xx \"\" \"suspend: suspend a shell, resuming its\" \"superior.\" \"\" csh(1)\n.xx \"\" \"inetd: internet\" \"``super\\-server''.\" \"\" inetd(8)\n.xx \"\" \"intro: introduction to special files and hardware\" \"support.\" \"\" intro(4)\n.xx \"\" \"style: analyze\" \"surface characteristics of a document.\" \"\" style(1)\n.xx \"\" \"suspend:\" \"suspend a shell, resuming its superior.\" \"\" csh(1)\n.xx \"\" \"sleep:\" \"suspend execution for an interval.\" \"\" sleep(1)\n.xx \"\" \"sleep:\" \"suspend execution for an interval.\" \"\" sleep(3F)\n.xx \"\" \"sleep:\" \"suspend execution for interval.\" \"\" sleep(3)\n.xx \"\" \"usleep:\" \"suspend execution for interval.\" \"\" usleep(3)\n.xx \"\" \"\" \"suspend: suspend a shell, resuming its superior.\" \"\" csh(1)\n.xx \"interface.\" \"ps: Evans and\" \"Sutherland Picture System 2 graphics device\" \"\" ps(4)\n.xx \"\" \"\" \"swab: swap bytes.\" \"\" swab(3)\n.xx \"\" \"swab:\" \"swap bytes.\" \"\" swab(3)\n.xx \"\" \"swapon: add a\" \"swap device for interleaved paging/swapping.\" \"\" swapon(2)\n.xx \"paging/swapping.\" \"\" \"swapon: add a swap device for interleaved\" \"\" swapon(2)\n.xx \"swapping.\" \"\" \"swapon: specify additional device for paging and\" \"\" swapon(8)\n.xx \"\" \"swapon: specify additional device for paging and\" \"swapping.\" \"\" swapon(8)\n.xx \"\" \"breaksw: exit from\" \"switch.\" \"\" csh(1)\n.xx \"\" \"case: selector in\" \"switch.\" \"\" csh(1)\n.xx \"\" \"default: catchall clause in\" \"switch.\" \"\" csh(1)\n.xx \"\" \"endsw: terminate\" \"switch.\" \"\" csh(1)\n.xx \"\" \"\" \"switch: multi-way command branch.\" \"\" csh(1)\n.xx \"\" \"dbx: dbx\" \"symbol table information.\" \"\" dbx(5)\n.xx \"\" \"stab:\" \"symbol table types.\" \"\" stab(5)\n.xx \"\" \"readlink: read value of a\" \"symbolic link.\" \"\" readlink(2)\n.xx \"\" \"symlink: make\" \"symbolic link to a file.\" \"\" symlink(2)\n.xx \"\" \"strip: remove\" \"symbols and relocation bits.\" \"\" strip(1)\n.xx \"\" \"\" \"symlink: make symbolic link to a file.\" \"\" symlink(2)\n.xx \"\" \"\" \"symorder: rearrange name list.\" \"\" symorder(1)\n.xx \"\" \"\" \"sync: update super-block.\" \"\" sync(2)\n.xx \"\" \"\" \"sync: update the super block.\" \"\" sync(8)\n.xx \"\" \"adjtime: correct the time to allow\" \"synchronization of the system clock.\" \"\" adjtime(2)\n.xx \"disk.\" \"fsync:\" \"synchronize a file's in-core state with that on\" \"\" fsync(2)\n.xx \"\" \"select:\" \"synchronous I/O multiplexing.\" \"\" select(2)\n.xx \"\" \"csh: a shell (command interpreter) with C-like\" \"syntax.\" \"\" csh(1)\n.xx \"\" \"L.\" \"sys: UUCP remote host description file.\" \"\" L.sys(5)\n.xx \"\" \"\" \"syscall: indirect system call.\" \"\" syscall(2)\n.xx \"\" \"perror,\" \"sys_errlist, sys_nerr: system error messages.\" \"\" perror(3)\n.xx \"terminal.\" \"\" \"sysline: display system status on status line of a\" \"\" sysline(1)\n.xx \"system log.\" \"\" \"syslog, openlog, closelog, setlogmask: control\" \"\" syslog(3)\n.xx \"\" \"\" \"syslogd: log systems messages.\" \"\" syslogd(8)\n.xx \"\" \"perror, sys_errlist,\" \"sys_nerr: system error messages.\" \"\" perror(3)\n.xx \"\" \"psignal,\" \"sys_siglist: system signal messages.\" \"\" psignal(3)\n.xx \"\" \"\" \"systat: display system statistics on a crt.\" \"\" systat(1)\n.xx \"\" \"hy: Network\" \"Systems Hyperchannel interface.\" \"\" hy(4)\n.xx \"\" \"syslogd: log\" \"systems messages.\" \"\" syslogd(8)\n.xx \"\" \"kgmon: generate a dump of the operating\" \"system's profile buffers.\" \"\" kgmon(8)\n.xx \"\" \"ns: Xerox Network\" \"Systems(tm) protocol family.\" \"\" ns(4F)\n.xx \"\" \"rehash: recompute command hash\" \"table.\" \"\" csh(1)\n.xx \"\" \"unhash: discard command hash\" \"table.\" \"\" csh(1)\n.xx \"\" \"mkhosts: generate hashed host\" \"table.\" \"\" mkhosts(8)\n.xx \"\" \"mkpasswd: generate hashed password\" \"table.\" \"\" mkpasswd(8)\n.xx \"\" \"mtab: mounted file system\" \"table.\" \"\" mtab(5)\n.xx \"\" \"vwidth: make troff width\" \"table for a font.\" \"\" vwidth(1)\n.xx \"\" \"dbx: dbx symbol\" \"table information.\" \"\" dbx(5)\n.xx \"\" \"getdtablesize: get descriptor\" \"table size.\" \"\" getdtablesize(2)\n.xx \"\" \"stab: symbol\" \"table types.\" \"\" stab(5)\n.xx \"\" \"htable: convert NIC standard format host\" \"tables.\" \"\" htable(8)\n.xx \"\" \"route: manually manipulate the routing\" \"tables.\" \"\" route(8C)\n.xx \"\" \"tbl: format\" \"tables for nroff or troff.\" \"\" tbl(1)\n.xx \"\" \"gettable: get NIC format host\" \"tables from a host.\" \"\" gettable(8C)\n.xx \"\" \"tabs: set terminal\" \"tabs.\" \"\" tabs(1)\n.xx \"\" \"\" \"tabs: set terminal tabs.\" \"\" tabs(1)\n.xx \"\" \"expand, unexpand: expand\" \"tabs to spaces, and vice versa.\" \"\" expand(1)\n.xx \"\" \"ctags: create a\" \"tags file.\" \"\" ctags(1)\n.xx \"\" \"\" \"tail: deliver the last part of a file.\" \"\" tail(1)\n.xx \"\" \"\" \"talk: talk to another user.\" \"\" talk(1)\n.xx \"\" \"talk:\" \"talk to another user.\" \"\" talk(1)\n.xx \"\" \"\" \"talkd: remote user communication server.\" \"\" talkd(8C)\n.xx \"functions and their inverses.\" \"sin, cos,\" \"tan, asin, acos, atan, atan2: trigonometric\" \"\" sin(3M)\n.xx \"\" \"sinh, cosh,\" \"tanh: hyperbolic functions.\" \"\" sinh(3M)\n.xx \"\" \"tcopy: copy a mag\" \"tape.\" \"\" tcopy(1)\n.xx \"\" \"tp: manipulate\" \"tape archive.\" \"\" tp(1)\n.xx \"\" \"tar:\" \"tape archive file format.\" \"\" tar(5)\n.xx \"\" \"tar:\" \"tape archiver.\" \"\" tar(1)\n.xx \"\" \"ut: UNIBUS TU45 tri-density\" \"tape drive interface.\" \"\" ut(4)\n.xx \"\" \"tp: DEC/mag\" \"tape formats.\" \"\" tp(5)\n.xx \"\" \"tclose, tread, twrite, trewin, tskipf, tstate: f77\" \"tape I/O.\" \"topen,\" topen(3F)\n.xx \"\" \"mt: magnetic\" \"tape manipulating program.\" \"\" mt(1)\n.xx \"\" \"\" \"tar: tape archive file format.\" \"\" tar(5)\n.xx \"\" \"\" \"tar: tape archiver.\" \"\" tar(1)\n.xx \"\" \"\" \"tb: line discipline for digitizing devices.\" \"\" tb(4)\n.xx \"\" \"deroff: remove nroff, troff,\" \"tbl and eqn constructs.\" \"\" deroff(1)\n.xx \"\" \"\" \"tbl: format tables for nroff or troff.\" \"\" tbl(1)\n.xx \"\" \"\" \"tc: photoypesetter simulator.\" \"\" tc(1)\n.xx \"tape I/O.\" \"topen,\" \"tclose, tread, twrite, trewin, tskipf, tstate: f77\" \"\" topen(3F)\n.xx \"\" \"\" \"tcopy: copy a mag tape.\" \"\" tcopy(1)\n.xx \"\" \"\" \"tcp: Internet Transmission Control Protocol.\" \"\" tcp(4P)\n.xx \"\" \"\" \"tee: pipe fitting.\" \"\" tee(1)\n.xx \"\" \"tk: paginator for the\" \"Tektronix 4014.\" \"\" tk(1)\n.xx \"\" \"last: indicate last logins of users and\" \"teletypes.\" \"\" last(1)\n.xx \"\" \"index, rindex, lnblnk, len:\" \"tell about character objects.\" \"\" index(3F)\n.xx \"operations.\" \"opendir, readdir,\" \"telldir, seekdir, rewinddir, closedir: directory\" \"\" directory(3)\n.xx \"\" \"telnet: user interface to the\" \"TELNET protocol.\" \"\" telnet(1C)\n.xx \"\" \"telnetd: DARPA\" \"TELNET protocol server.\" \"\" telnetd(8C)\n.xx \"\" \"\" \"telnet: user interface to the TELNET protocol.\" \"\" telnet(1C)\n.xx \"\" \"\" \"telnetd: DARPA TELNET protocol server.\" \"\" telnetd(8C)\n.xx \"\" \"su: substitute user id\" \"temporarily.\" \"\" su(1)\n.xx \"\" \"signals invalid floating-point operations on a VAX\" \"(temporary).\" \"infnan:\" infnan(3M)\n.xx \"\" \"\" \"term: conventional names for terminals.\" \"\" term(7)\n.xx \"\" \"\" \"termcap: terminal capability data base.\" \"\" termcap(5)\n.xx \"\" \"lib2648: subroutines for the HP 2648 graphics\" \"terminal.\" \"\" lib2648(3X)\n.xx \"\" \"lock: reserve a\" \"terminal.\" \"\" lock(1)\n.xx \"\" \"sysline: display system status on status line of a\" \"terminal.\" \"\" sysline(1)\n.xx \"\" \"ttyname, isatty, ttyslot: find name of a\" \"terminal.\" \"\" ttyname(3)\n.xx \"\" \"vhangup: virtually ``hangup'' the current control\" \"terminal.\" \"\" vhangup(2)\n.xx \"\" \"worms: animate worms on a display\" \"terminal.\" \"\" worms(6)\n.xx \"\" \"termcap:\" \"terminal capability data base.\" \"\" termcap(5)\n.xx \"\" \"gettytab:\" \"terminal configuration data base.\" \"\" gettytab(5)\n.xx \"\" \"tset:\" \"terminal dependent initialization.\" \"\" tset(1)\n.xx \"\" \"pty: pseudo\" \"terminal driver.\" \"\" pty(4)\n.xx \"\" \"tgetent, tgetnum, tgetflag, tgetstr, tgoto, tputs:\" \"terminal independent operation routines.\" \"\" termcap(3X)\n.xx \"\" \"ttys:\" \"terminal initialization data.\" \"\" ttys(5)\n.xx \"\" \"tty: general\" \"terminal interface.\" \"\" tty(4)\n.xx \"\" \"getty: set\" \"terminal mode.\" \"\" getty(8)\n.xx \"\" \"dmf: DMF-32,\" \"terminal multiplexor.\" \"\" dmf(4)\n.xx \"\" \"dmz: DMZ-32\" \"terminal multiplexor.\" \"\" dmz(4)\n.xx \"\" \"tty: get\" \"terminal name.\" \"\" tty(1)\n.xx \"\" \"stty: set\" \"terminal options.\" \"\" stty(1)\n.xx \"\" \"ttynam, isatty: find name of a\" \"terminal port.\" \"\" ttynam(3F)\n.xx \"\" \"clear: clear\" \"terminal screen.\" \"\" clear(1)\n.xx \"\" \"script: make typescript of\" \"terminal session.\" \"\" script(1)\n.xx \"\" \"stty, gtty: set and get\" \"terminal state (defunct).\" \"\" stty(3C)\n.xx \"\" \"tabs: set\" \"terminal tabs.\" \"\" tabs(1)\n.xx \"\" \"term: conventional names for\" \"terminals.\" \"\" term(7)\n.xx \"\" \"wait, wait3: wait for process to\" \"terminate.\" \"\" wait(2)\n.xx \"\" \"wait: wait for a process to\" \"terminate.\" \"\" wait(3F)\n.xx \"\" \"_exit:\" \"terminate a process.\" \"\" exit(2)\n.xx \"output.\" \"exit:\" \"terminate a process after flushing any pending\" \"\" exit(3)\n.xx \"\" \"kill:\" \"terminate a process with extreme prejudice.\" \"\" kill(1)\n.xx \"\" \"endif:\" \"terminate conditional.\" \"\" csh(1)\n.xx \"\" \"end:\" \"terminate loop.\" \"\" csh(1)\n.xx \"\" \"exit:\" \"terminate process with status.\" \"\" exit(3F)\n.xx \"\" \"endsw:\" \"terminate switch.\" \"\" csh(1)\n.xx \"\" \"abort: abnormal\" \"termination.\" \"\" abort(3F)\n.xx \"\" \"\" \"test: condition command.\" \"\" test(1)\n.xx \"\" \"drtest: standalone disk\" \"test program.\" \"\" drtest(8)\n.xx \"\" \"quiz:\" \"test your knowledge.\" \"\" quiz(6)\n.xx \"\" \"sticky: persistent\" \"text and append-only directories.\" \"\" sticky(8)\n.xx \"\" \"ed:\" \"text editor.\" \"\" ed(1)\n.xx \"\" \"ex, edit:\" \"text editor.\" \"\" ex(1)\n.xx \"\" \"jove: an interactive display-oriented\" \"text editor.\" \"\" jove(1)\n.xx \"\" \"fmt: simple\" \"text formatter.\" \"\" fmt(1)\n.xx \"\" \"nroff:\" \"text formatting.\" \"\" nroff(1)\n.xx \"\" \"troff, nroff:\" \"text formatting and typesetting.\" \"\" troff(1)\n.xx \"\" \"ms:\" \"text formatting macros.\" \"\" ms(7)\n.xx \"\" \"\" \"tftp: trivial file transfer program.\" \"\" tftp(1C)\n.xx \"\" \"\" \"tftpd: DARPA Trivial File Transfer Protocol server.\" \"\" tftpd(8C)\n.xx \"terminal independent operation routines.\" \"\" \"tgetent, tgetnum, tgetflag, tgetstr, tgoto, tputs:\" \"\" termcap(3X)\n.xx \"independent operation routines.\" \"tgetent, tgetnum,\" \"tgetflag, tgetstr, tgoto, tputs: terminal\" \"\" termcap(3X)\n.xx \"independent operation routines.\" \"tgetent,\" \"tgetnum, tgetflag, tgetstr, tgoto, tputs: terminal\" \"\" termcap(3X)\n.xx \"operation routines.\" \"tgetent, tgetnum, tgetflag,\" \"tgetstr, tgoto, tputs: terminal independent\" \"\" termcap(3X)\n.xx \"routines.\" \"tgetent, tgetnum, tgetflag, tgetstr,\" \"tgoto, tputs: terminal independent operation\" \"\" termcap(3X)\n.xx \"\" \"acos, atan, atan2: trigonometric functions and\" \"their inverses.\" \"sin, cos, tan, asin,\" sin(3M)\n.xx \"\" \"diction, explain: print wordy sentences;\" \"thesaurus for diction.\" \"\" diction(1)\n.xx \"\" \"alarm: schedule signal after specified\" \"time.\" \"\" alarm(3C)\n.xx \"\" \"alarm: execute a subroutine after a specified\" \"time.\" \"\" alarm(3F)\n.xx \"\" \"at: execute commands at a later\" \"time.\" \"\" at(1)\n.xx \"\" \"etime, dtime: return elapsed execution\" \"time.\" \"\" etime(3F)\n.xx \"\" \"gettimeofday, settimeofday: get/set date and\" \"time.\" \"\" gettimeofday(2)\n.xx \"\" \"shutdown: close down the system at a given\" \"time.\" \"\" shutdown(8)\n.xx \"\" \"time, ftime: get date and\" \"time.\" \"\" time(3C)\n.xx \"\" \"time, ctime, ltime, gmtime: return system\" \"time.\" \"\" time(3F)\n.xx \"\" \"ualarm: schedule signal after specified\" \"time.\" \"\" ualarm(3)\n.xx \"\" \"time:\" \"time a command.\" \"\" time(1)\n.xx \"\" \"time:\" \"time command.\" \"\" csh(1)\n.xx \"\" \"\" \"time, ctime, ltime, gmtime: return system time.\" \"\" time(3F)\n.xx \"\" \"\" \"time, ftime: get date and time.\" \"\" time(3C)\n.xx \"\" \"fdate: return date and\" \"time in an ASCII string.\" \"\" fdate(3F)\n.xx \"\" \"idate, itime: return date or\" \"time in numerical form.\" \"\" idate(3F)\n.xx \"\" \"profil: execution\" \"time profile.\" \"\" profil(2)\n.xx \"\" \"timed:\" \"time server daemon.\" \"\" timed(8)\n.xx \"\" \"\" \"time: time a command.\" \"\" time(1)\n.xx \"\" \"\" \"time: time command.\" \"\" csh(1)\n.xx \"\" \"adjtime: correct the\" \"time to allow synchronization of the system clock.\" \"\" adjtime(2)\n.xx \"\" \"gmtime, asctime, timezone: convert date and\" \"time to ASCII.\" \"ctime, localtime,\" ctime(3)\n.xx \"\" \"timedc:\" \"timed control program.\" \"\" timedc(8)\n.xx \"\" \"\" \"timed: time server daemon.\" \"\" timed(8)\n.xx \"\" \"\" \"timedc: timed control program.\" \"\" timedc(8)\n.xx \"\" \"getitimer, setitimer: get/set value of interval\" \"timer.\" \"\" getitimer(2)\n.xx \"\" \"times: get process\" \"times.\" \"\" times(3C)\n.xx \"\" \"utime: set file\" \"times.\" \"\" utime(3C)\n.xx \"\" \"utimes: set file\" \"times.\" \"\" utimes(2)\n.xx \"\" \"\" \"times: get process times.\" \"\" times(3C)\n.xx \"\" \"exit, export, login, read, readonly, set, shift,\" \"times, trap, umask, wait: command language.\" \"/exec,\" sh(1)\n.xx \"\" \"ctime, localtime, gmtime, asctime,\" \"timezone: convert date and time to ASCII.\" \"\" ctime(3)\n.xx \"\" \"\" \"tip, cu: connect to a remote system.\" \"\" tip(1C)\n.xx \"\" \"\" \"tk: paginator for the Tektronix 4014.\" \"\" tk(1)\n.xx \"\" \"\" \"tm: TM-11/TE-10 magtape interface.\" \"\" tm(4)\n.xx \"\" \"ht:\" \"TM-03/TE-16,TU-45,TU-77 MASSBUS magtape interface.\" \"\" ht(4)\n.xx \"\" \"tm:\" \"TM-11/TE-10 magtape interface.\" \"\" tm(4)\n.xx \"\" \"mt:\" \"TM78/TU-78 MASSBUS magtape interface.\" \"\" mt(4)\n.xx \"\" \"\" \"tmscp: DEC TMSCP magtape interface.\" \"\" tmscp(4)\n.xx \"\" \"tmscp: DEC\" \"TMSCP magtape interface.\" \"\" tmscp(4)\n.xx \"\" \"\" \"tn3270: full-screen remote login to IBM VM/CMS.\" \"\" tn3270(1)\n.xx \"\" \"isgraph, iscntrl, isascii, toupper, tolower,\" \"toascii: character classification macros.\" \"/isprint,\" ctype(3)\n.xx \"\" \"popen, pclose: initiate I/O\" \"to/from a process.\" \"\" popen(3)\n.xx \"\" \"/isprint, isgraph, iscntrl, isascii, toupper,\" \"tolower, toascii: character classification macros.\" \"\" ctype(3)\n.xx \"tstate: f77 tape I/O.\" \"\" \"topen, tclose, tread, twrite, trewin, tskipf,\" \"\" topen(3F)\n.xx \"\" \"tsort:\" \"topological sort.\" \"\" tsort(1)\n.xx \"\" \"\" \"touch: update date last modified of a file.\" \"\" touch(1)\n.xx \"\" \"/ispunct, isprint, isgraph, iscntrl, isascii,\" \"toupper, tolower, toascii: character classification/\" \"\" ctype(3)\n.xx \"\" \"\" \"tp: DEC/mag tape formats.\" \"\" tp(5)\n.xx \"\" \"\" \"tp: manipulate tape archive.\" \"\" tp(1)\n.xx \"\" \"tgetent, tgetnum, tgetflag, tgetstr, tgoto,\" \"tputs: terminal independent operation routines.\" \"\" termcap(3X)\n.xx \"\" \"\" \"tr: translate characters.\" \"\" tr(1)\n.xx \"\" \"ptrace: process\" \"trace.\" \"\" ptrace(2)\n.xx \"\" \"trpt: transliterate protocol\" \"trace.\" \"\" trpt(8C)\n.xx \"\" \"trsp: transliterate sequenced packet protocol\" \"trace.\" \"\" trsp(8C)\n.xx \"\" \"goto: command\" \"transfer.\" \"\" csh(1)\n.xx \"\" \"uucico, uucpd:\" \"transfer files queued by uucp or uux.\" \"\" uucico(8C)\n.xx \"\" \"ftp: ARPANET file\" \"transfer program.\" \"\" ftp(1C)\n.xx \"\" \"tftp: trivial file\" \"transfer program.\" \"\" tftp(1C)\n.xx \"\" \"ftpd: DARPA Internet File\" \"Transfer Protocol server.\" \"\" ftpd(8C)\n.xx \"\" \"tftpd: DARPA Trivial File\" \"Transfer Protocol server.\" \"\" tftpd(8C)\n.xx \"\" \"tr:\" \"translate characters.\" \"\" tr(1)\n.xx \"\" \"ad: Data\" \"Translation A/D converter.\" \"\" ad(4)\n.xx \"\" \"pi: Pascal interpreter code\" \"translator.\" \"\" pi(1)\n.xx \"\" \"trpt:\" \"transliterate protocol trace.\" \"\" trpt(8C)\n.xx \"\" \"trsp:\" \"transliterate sequenced packet protocol trace.\" \"\" trsp(8C)\n.xx \"\" \"tcp: Internet\" \"Transmission Control Protocol.\" \"\" tcp(4P)\n.xx \"\" \"uuencode, uudecode: encode/decode a binary file for\" \"transmission via mail.\" \"\" uuencode(1C)\n.xx \"\" \"trpfpe, fpecnt:\" \"trap and repair floating point faults.\" \"\" trpfpe(3F)\n.xx \"\" \"trapov:\" \"trap and repair floating point overflow.\" \"\" trapov(3F)\n.xx \"\" \"traper:\" \"trap arithmetic errors.\" \"\" traper(3F)\n.xx \"\" \"export, login, read, readonly, set, shift, times,\" \"trap, umask, wait: command language.\" \"/exec, exit,\" sh(1)\n.xx \"\" \"\" \"traper: trap arithmetic errors.\" \"\" traper(3F)\n.xx \"\" \"\" \"trapov: trap and repair floating point overflow.\" \"\" trapov(3F)\n.xx \"I/O.\" \"topen, tclose,\" \"tread, twrite, trewin, tskipf, tstate: f77 tape\" \"\" topen(3F)\n.xx \"\" \"\" \"trek: trekkie game.\" \"\" trek(6)\n.xx \"\" \"trek:\" \"trekkie game.\" \"\" trek(6)\n.xx \"\" \"topen, tclose, tread, twrite,\" \"trewin, tskipf, tstate: f77 tape I/O.\" \"\" topen(3F)\n.xx \"\" \"ut: UNIBUS TU45\" \"tri-density tape drive interface.\" \"\" ut(4)\n.xx \"\" \"sin, cos, tan, asin, acos, atan, atan2:\" \"trigonometric functions and their inverses.\" \"\" sin(3M)\n.xx \"\" \"tftp:\" \"trivial file transfer program.\" \"\" tftp(1C)\n.xx \"\" \"tftpd: DARPA\" \"Trivial File Transfer Protocol server.\" \"\" tftpd(8C)\n.xx \"\" \"tbl: format tables for nroff or\" \"troff.\" \"\" tbl(1)\n.xx \"\" \"Lisp programs to be printed with nroff, vtroff, or\" \"troff.\" \"vlp: Format\" vlp(1)\n.xx \"\" \"\" \"troff, nroff: text formatting and typesetting.\" \"\" troff(1)\n.xx \"\" \"deroff: remove nroff,\" \"troff, tbl and eqn constructs.\" \"\" deroff(1)\n.xx \"\" \"vwidth: make\" \"troff width table for a font.\" \"\" vwidth(1)\n.xx \"\" \"battlestar: a\" \"tropical adventure game.\" \"\" battlestar(6)\n.xx \"faults.\" \"\" \"trpfpe, fpecnt: trap and repair floating point\" \"\" trpfpe(3F)\n.xx \"\" \"\" \"trpt: transliterate protocol trace.\" \"\" trpt(8C)\n.xx \"trace.\" \"\" \"trsp: transliterate sequenced packet protocol\" \"\" trsp(8C)\n.xx \"\" \"\" \"true, false: provide truth values.\" \"\" true(1)\n.xx \"\" \"false,\" \"true: provide truth values.\" \"\" false(1)\n.xx \"\" \"truncate:\" \"truncate a file to a specified length.\" \"\" truncate(2)\n.xx \"\" \"\" \"truncate: truncate a file to a specified length.\" \"\" truncate(2)\n.xx \"\" \"false, true: provide\" \"truth values.\" \"\" false(1)\n.xx \"\" \"true, false: provide\" \"truth values.\" \"\" true(1)\n.xx \"\" \"\" \"ts: TS-11 magtape interface.\" \"\" ts(4)\n.xx \"\" \"ts:\" \"TS-11 magtape interface.\" \"\" ts(4)\n.xx \"\" \"\" \"tset: terminal dependent initialization.\" \"\" tset(1)\n.xx \"\" \"topen, tclose, tread, twrite, trewin,\" \"tskipf, tstate: f77 tape I/O.\" \"\" topen(3F)\n.xx \"\" \"\" \"tsort: topological sort.\" \"\" tsort(1)\n.xx \"\" \"topen, tclose, tread, twrite, trewin, tskipf,\" \"tstate: f77 tape I/O.\" \"\" topen(3F)\n.xx \"\" \"\" \"tty: general terminal interface.\" \"\" tty(4)\n.xx \"\" \"\" \"tty: get terminal name.\" \"\" tty(1)\n.xx \"\" \"\" \"ttynam, isatty: find name of a terminal port.\" \"\" ttynam(3F)\n.xx \"\" \"\" \"ttyname, isatty, ttyslot: find name of a terminal.\" \"\" ttyname(3)\n.xx \"\" \"getttyent, getttynam, setttyent, endttyent: get\" \"ttys file entry.\" \"\" getttyent(3)\n.xx \"\" \"\" \"ttys: terminal initialization data.\" \"\" ttys(5)\n.xx \"\" \"ttyname, isatty,\" \"ttyslot: find name of a terminal.\" \"\" ttyname(3)\n.xx \"interface.\" \"\" \"tu: VAX-11/730 and VAX-11/750 TU58 console cassette\" \"\" tu(4)\n.xx \"\" \"ut: UNIBUS\" \"TU45 tri-density tape drive interface.\" \"\" ut(4)\n.xx \"\" \"ht: TM-03/TE-16,\" \"TU-45,TU-77 MASSBUS magtape interface.\" \"\" ht(4)\n.xx \"\" \"tu: VAX-11/730 and VAX-11/750\" \"TU58 console cassette interface.\" \"\" tu(4)\n.xx \"\" \"uu:\" \"TU58/DECtape II UNIBUS cassette interface.\" \"\" uu(4)\n.xx \"\" \"ht: TM-03/TE-16,TU-45,\" \"TU-77 MASSBUS magtape interface.\" \"\" ht(4)\n.xx \"\" \"tunefs:\" \"tune up an existing file system.\" \"\" tunefs(8)\n.xx \"\" \"\" \"tunefs: tune up an existing file system.\" \"\" tunefs(8)\n.xx \"\" \"topen, tclose, tread,\" \"twrite, trewin, tskipf, tstate: f77 tape I/O.\" \"\" topen(3F)\n.xx \"\" \"file: determine file\" \"type.\" \"\" file(1)\n.xx \"\" \"stab: symbol table\" \"types.\" \"\" stab(5)\n.xx \"\" \"types: primitive system data\" \"types.\" \"\" types(5)\n.xx \"\" \"\" \"types: primitive system data types.\" \"\" types(5)\n.xx \"\" \"script: make\" \"typescript of terminal session.\" \"\" script(1)\n.xx \"\" \"man: macros to\" \"typeset manual.\" \"\" man(7)\n.xx \"\" \"eqn, neqn, checkeq:\" \"typeset mathematics.\" \"\" eqn(1)\n.xx \"\" \"troff, nroff: text formatting and\" \"typesetting.\" \"\" troff(1)\n.xx \"\" \"\" \"ualarm: schedule signal after specified time.\" \"\" ualarm(3)\n.xx \"\" \"\" \"uda: UDA-50 disk controller interface.\" \"\" uda(4)\n.xx \"\" \"uda:\" \"UDA-50 disk controller interface.\" \"\" uda(4)\n.xx \"\" \"\" \"udp: Internet User Datagram Protocol.\" \"\" udp(4P)\n.xx \"\" \"getpw: get name from\" \"uid.\" \"\" getpw(3C)\n.xx \"\" \"\" \"ul: do underlining.\" \"\" ul(1)\n.xx \"\" \"\" \"umask: change or display file creation mask.\" \"\" csh(1)\n.xx \"\" \"\" \"umask: set file creation mode mask.\" \"\" umask(2)\n.xx \"\" \"login, read, readonly, set, shift, times, trap,\" \"umask, wait: command language.\" \"/exec, exit, export,\" sh(1)\n.xx \"\" \"mount,\" \"umount: mount and dismount file system.\" \"\" mount(8)\n.xx \"\" \"mount,\" \"umount: mount or remove file system.\" \"\" mount(2)\n.xx \"\" \"\" \"unalias: remove aliases.\" \"\" csh(1)\n.xx \"\" \"compress,\" \"uncompress, zcat: compress and expand data.\" \"\" compress(1)\n.xx \"\" \"ul: do\" \"underlining.\" \"\" ul(1)\n.xx \"\" \"expand,\" \"unexpand: expand tabs to spaces, and vice versa.\" \"\" expand(1)\n.xx \"\" \"\" \"ungetc: push character back into input stream.\" \"\" ungetc(3S)\n.xx \"\" \"\" \"unhash: discard command hash table.\" \"\" csh(1)\n.xx \"\" \"uu: TU58/DECtape II\" \"UNIBUS cassette interface.\" \"\" uu(4)\n.xx \"\" \"up:\" \"unibus storage module controller/drives.\" \"\" up(4)\n.xx \"\" \"ut:\" \"UNIBUS TU45 tri-density tape drive interface.\" \"\" ut(4)\n.xx \"\" \"\" \"unifdef: remove ifdef'ed lines.\" \"\" unifdef(1)\n.xx \"\" \"\" \"uniq: report repeated lines in a file.\" \"\" uniq(1)\n.xx \"\" \"mktemp: make a\" \"unique file name.\" \"\" mktemp(3)\n.xx \"\" \"gethostid, sethostid: get/set\" \"unique identifier of current host.\" \"\" gethostid(2)\n.xx \"\" \"flush: flush output to a logical\" \"unit.\" \"\" flush(3F)\n.xx \"\" \"fseek, ftell: reposition a file on a logical\" \"unit.\" \"\" fseek(3F)\n.xx \"\" \"getc, fgetc: get a character from a logical\" \"unit.\" \"\" getc(3F)\n.xx \"\" \"putc, fputc: write a character to a fortran logical\" \"unit.\" \"\" putc(3F)\n.xx \"\" \"dn: DN-11 autocall\" \"unit interface.\" \"\" dn(4)\n.xx \"\" \"\" \"units: conversion program.\" \"\" units(1)\n.xx \"\" \"learn: computer aided instruction about\" \"UNIX.\" \"\" learn(1)\n.xx \"\" \"reboot:\" \"UNIX bootstrapping procedures.\" \"\" reboot(8)\n.xx \"\" \"system: execute a\" \"UNIX command.\" \"\" system(3F)\n.xx \"\" \"uux: unix to\" \"unix command execution.\" \"\" uux(1C)\n.xx \"\" \"uucp: unix to\" \"unix copy.\" \"\" uucp(1C)\n.xx \"\" \"mtio:\" \"UNIX magtape interface.\" \"\" mtio(4)\n.xx \"\" \"uux:\" \"unix to unix command execution.\" \"\" uux(1C)\n.xx \"\" \"uucp:\" \"unix to unix copy.\" \"\" uucp(1C)\n.xx \"\" \"\" \"unlimit: remove resource limitiations.\" \"\" csh(1)\n.xx \"\" \"rmdir, rm: remove\" \"(unlink) directories or files.\" \"\" rmdir(1)\n.xx \"\" \"rm, rmdir: remove\" \"(unlink) files or directories.\" \"\" rm(1)\n.xx \"\" \"\" \"unlink: remove a directory entry.\" \"\" unlink(3F)\n.xx \"\" \"\" \"unlink: remove directory entry.\" \"\" unlink(2)\n.xx \"\" \"\" \"unset: discard shell variables.\" \"\" csh(1)\n.xx \"\" \"\" \"unsetenv: remove environment variables.\" \"\" csh(1)\n.xx \"\" \"uptime: show how long system has been\" \"up.\" \"\" uptime(1)\n.xx \"\" \"tunefs: tune\" \"up an existing file system.\" \"\" tunefs(8)\n.xx \"\" \"\" \"up: unibus storage module controller/drives.\" \"\" up(4)\n.xx \"\" \"touch:\" \"update date last modified of a file.\" \"\" touch(1)\n.xx \"\" \"\" \"update: periodically update the super block.\" \"\" update(8)\n.xx \"\" \"sync:\" \"update super-block.\" \"\" sync(2)\n.xx \"\" \"sync:\" \"update the super block.\" \"\" sync(8)\n.xx \"\" \"update: periodically\" \"update the super block.\" \"\" update(8)\n.xx \"\" \"\" \"uptime: show how long system has been up.\" \"\" uptime(1)\n.xx \"\" \"du: summarize disk\" \"usage.\" \"\" du(1)\n.xx \"\" \"quota: display disc\" \"usage and limits.\" \"\" quota(1)\n.xx \"\" \"what: show what versions of object modules were\" \"used to construct a file.\" \"\" what(1)\n.xx \"\" \"miscellaneous: miscellaneous\" \"useful information pages.\" \"\" intro(7)\n.xx \"\" \"login: login new\" \"user.\" \"\" csh(1)\n.xx \"\" \"talk: talk to another\" \"user.\" \"\" talk(1)\n.xx \"\" \"write: write to another\" \"user.\" \"\" write(1)\n.xx \"\" \"seteuid, setruid, setgid, setegid, setrgid: set\" \"user and group ID.\" \"setuid,\" setuid(3)\n.xx \"\" \"talkd: remote\" \"user communication server.\" \"\" talkd(8C)\n.xx \"\" \"udp: Internet\" \"User Datagram Protocol.\" \"\" udp(4P)\n.xx \"\" \"environ:\" \"user environment.\" \"\" environ(7)\n.xx \"\" \"whoami: print effective current\" \"user id.\" \"\" whoami(1)\n.xx \"\" \"su: substitute\" \"user id temporarily.\" \"\" su(1)\n.xx \"\" \"getuid, geteuid: get\" \"user identity.\" \"\" getuid(2)\n.xx \"\" \"setreuid: set real and effective\" \"user ID's.\" \"\" setreuid(2)\n.xx \"\" \"finger:\" \"user information lookup program.\" \"\" finger(1)\n.xx \"\" \"fingerd: remote\" \"user information server.\" \"\" fingerd(8C)\n.xx \"\" \"telnet:\" \"user interface to the TELNET protocol.\" \"\" telnet(1C)\n.xx \"\" \"whois: DARPA Internet\" \"user name directory service.\" \"\" whois(1)\n.xx \"\" \"getuid, getgid: get\" \"user or group ID of the caller.\" \"\" getuid(3F)\n.xx \"\" \"edquota: edit\" \"user quotas.\" \"\" edquota(8)\n.xx \"\" \"getusershell, setusershell, endusershell: get legal\" \"user shells.\" \"\" getusershell(3)\n.xx \"\" \"\" \"USERFILE: UUCP pathname permissions file.\" \"\" USERFILE(5)\n.xx \"\" \"adduser: procedure for adding new\" \"users.\" \"\" adduser(8)\n.xx \"\" \"binmail: send or receive mail among\" \"users.\" \"\" binmail(1)\n.xx \"\" \"wall: write to all\" \"users.\" \"\" wall(1)\n.xx \"\" \"last: indicate last logins of\" \"users and teletypes.\" \"\" last(1)\n.xx \"\" \"\" \"users: compact list of users who are on the system.\" \"\" users(1)\n.xx \"\" \"getlog: get\" \"user's login name.\" \"\" getlog(3F)\n.xx \"\" \"users: compact list of\" \"users who are on the system.\" \"\" users(1)\n.xx \"\" \"\" \"usleep: suspend execution for interval.\" \"\" usleep(3)\n.xx \"\" \"\" \"ut: UNIBUS TU45 tri-density tape drive interface.\" \"\" ut(4)\n.xx \"\" \"getrusage: get information about resource\" \"utilization.\" \"\" getrusage(2)\n.xx \"\" \"vtimes: get information about resource\" \"utilization.\" \"\" vtimes(3C)\n.xx \"\" \"\" \"utime: set file times.\" \"\" utime(3C)\n.xx \"\" \"\" \"utimes: set file times.\" \"\" utimes(2)\n.xx \"\" \"\" \"utmp, wtmp: login records.\" \"\" utmp(5)\n.xx \"\" \"\" \"uu: TU58/DECtape II UNIBUS cassette interface.\" \"\" uu(4)\n.xx \"uux.\" \"\" \"uucico, uucpd: transfer files queued by uucp or\" \"\" uucico(8C)\n.xx \"\" \"\" \"uuclean: uucp spool directory clean-up.\" \"\" uuclean(8C)\n.xx \"\" \"rmail: handle remote mail received via\" \"uucp.\" \"\" rmail(1)\n.xx \"\" \"L-devices:\" \"UUCP device description file.\" \"\" L-devices(5)\n.xx \"\" \"uuxqt:\" \"UUCP execution file interpreter.\" \"\" uuxqt(8C)\n.xx \"\" \"L.aliases:\" \"UUCP hostname alias file.\" \"\" L.aliases(5)\n.xx \"\" \"uuname: list names of\" \"UUCP hosts.\" \"\" uuname(1C)\n.xx \"\" \"uulog: display\" \"UUCP log files.\" \"\" uulog(1C)\n.xx \"\" \"uucico, uucpd: transfer files queued by\" \"uucp or uux.\" \"\" uucico(8C)\n.xx \"\" \"USERFILE:\" \"UUCP pathname permissions file.\" \"\" USERFILE(5)\n.xx \"\" \"L-dialcodes:\" \"UUCP phone number index file.\" \"\" L-dialcodes(5)\n.xx \"\" \"uuq: examine or manipulate the\" \"uucp queue.\" \"\" uuq(1C)\n.xx \"\" \"L.cmds:\" \"UUCP remote command permissions file.\" \"\" L.cmds(5)\n.xx \"\" \"L.sys:\" \"UUCP remote host description file.\" \"\" L.sys(5)\n.xx \"\" \"uupoll: poll a remote\" \"UUCP site.\" \"\" uupoll(8C)\n.xx \"\" \"uuclean:\" \"uucp spool directory clean-up.\" \"\" uuclean(8C)\n.xx \"\" \"uusnap: show snapshot of the\" \"UUCP system.\" \"\" uusnap(8C)\n.xx \"\" \"\" \"uucp: unix to unix copy.\" \"\" uucp(1C)\n.xx \"\" \"uucico,\" \"uucpd: transfer files queued by uucp or uux.\" \"\" uucico(8C)\n.xx \"transmission via mail.\" \"uuencode,\" \"uudecode: encode/decode a binary file for\" \"\" uuencode(1C)\n.xx \"\" \"uuencode: format of an encoded\" \"uuencode file.\" \"\" uuencode(5)\n.xx \"\" \"\" \"uuencode: format of an encoded uuencode file.\" \"\" uuencode(5)\n.xx \"transmission via mail.\" \"\" \"uuencode, uudecode: encode/decode a binary file for\" \"\" uuencode(1C)\n.xx \"\" \"\" \"uulog: display UUCP log files.\" \"\" uulog(1C)\n.xx \"\" \"\" \"uuname: list names of UUCP hosts.\" \"\" uuname(1C)\n.xx \"\" \"\" \"uupoll: poll a remote UUCP site.\" \"\" uupoll(8C)\n.xx \"\" \"\" \"uuq: examine or manipulate the uucp queue.\" \"\" uuq(1C)\n.xx \"\" \"\" \"uusend: send a file to a remote host.\" \"\" uusend(1C)\n.xx \"\" \"\" \"uusnap: show snapshot of the UUCP system.\" \"\" uusnap(8C)\n.xx \"\" \"uucico, uucpd: transfer files queued by uucp or\" \"uux.\" \"\" uucico(8C)\n.xx \"\" \"\" \"uux: unix to unix command execution.\" \"\" uux(1C)\n.xx \"\" \"\" \"uuxqt: UUCP execution file interpreter.\" \"\" uuxqt(8C)\n.xx \"\" \"\" \"va: Benson-Varian interface.\" \"\" va(4)\n.xx \"\" \"vacation: return ``I am on\" \"vacation'' indication.\" \"\" vacation(1)\n.xx \"\" \"\" \"vacation: return ``I am on vacation'' indication.\" \"\" vacation(1)\n.xx \"\" \"\" \"valloc: aligned memory allocator.\" \"\" valloc(3C)\n.xx \"\" \"abs: integer absolute\" \"value.\" \"\" abs(3)\n.xx \"\" \"hypot, cabs: Euclidean distance, complex absolute\" \"value.\" \"\" hypot(3M)\n.xx \"functions.\" \"fabs, floor, ceil, rint: absolute\" \"value, floor, ceiling, and round-to-nearest\" \"\" floor(3M)\n.xx \"\" \"getenv:\" \"value for environment name.\" \"\" getenv(3)\n.xx \"\" \"readlink: read\" \"value of a symbolic link.\" \"\" readlink(2)\n.xx \"\" \"getenv: get\" \"value of environment variables.\" \"\" getenv(3F)\n.xx \"\" \"getitimer, setitimer: get/set\" \"value of interval timer.\" \"\" getitimer(2)\n.xx \"\" \"set: change\" \"value of shell variable.\" \"\" csh(1)\n.xx \"\" \"false, true: provide truth\" \"values.\" \"\" false(1)\n.xx \"\" \"dflmin, dflmax, dffrac, inmax: return extreme\" \"values.\" \"flmin, flmax, ffrac,\" flmin(3F)\n.xx \"\" \"rand, drand, irand: return random\" \"values.\" \"\" rand(3F)\n.xx \"\" \"true, false: provide truth\" \"values.\" \"\" true(1)\n.xx \"\" \"htonl, htons, ntohl, ntohs: convert\" \"values between host and network byte order.\" \"\" byteorder(3N)\n.xx \"\" \"\" \"varargs: variable argument list.\" \"\" varargs(3)\n.xx \"\" \"set: change value of shell\" \"variable.\" \"\" csh(1)\n.xx \"\" \"varargs:\" \"variable argument list.\" \"\" varargs(3)\n.xx \"\" \"setenv: set\" \"variable in environment.\" \"\" csh(1)\n.xx \"\" \"@: arithmetic on shell\" \"variables.\" \"\" csh(1)\n.xx \"\" \"unset: discard shell\" \"variables.\" \"\" csh(1)\n.xx \"\" \"unsetenv: remove environment\" \"variables.\" \"\" csh(1)\n.xx \"\" \"getenv: get value of environment\" \"variables.\" \"\" getenv(3F)\n.xx \"\" \"crl:\" \"VAX 8600 console RL02 interface.\" \"\" crl(4)\n.xx \"\" \"signals invalid floating-point operations on a\" \"VAX (temporary).\" \"infnan:\" infnan(3M)\n.xx \"\" \"as:\" \"VAX-11 assembler.\" \"\" as(1)\n.xx \"\" \"cons:\" \"VAX-11 console interface.\" \"\" cons(4)\n.xx \"interface.\" \"tu:\" \"VAX-11/730 and VAX-11/750 TU58 console cassette\" \"\" tu(4)\n.xx \"\" \"tu: VAX-11/730 and\" \"VAX-11/750 TU58 console cassette interface.\" \"\" tu(4)\n.xx \"\" \"assert: program\" \"verification.\" \"\" assert(3)\n.xx \"\" \"lint: a C program\" \"verifier.\" \"\" lint(1)\n.xx \"\" \"expand, unexpand: expand tabs to spaces, and vice\" \"versa.\" \"\" expand(1)\n.xx \"\" \"vfont: font formats for the Benson-Varian or\" \"Versatec.\" \"\" vfont(5)\n.xx \"\" \"vp:\" \"Versatec interface.\" \"\" vp(4)\n.xx \"\" \"hangman: Computer\" \"version of the game hangman.\" \"\" hangman(6)\n.xx \"file.\" \"what: show what\" \"versions of object modules were used to construct a\" \"\" what(1)\n.xx \"Versatec.\" \"\" \"vfont: font formats for the Benson-Varian or\" \"\" vfont(5)\n.xx \"efficient way.\" \"\" \"vfork: spawn new process in a virtual memory\" \"\" vfork(2)\n.xx \"\" \"\" \"vgrind: grind nice listings of programs.\" \"\" vgrind(1)\n.xx \"\" \"\" \"vgrindefs: vgrind's language definition data base.\" \"\" vgrindefs(5)\n.xx \"\" \"vgrindefs:\" \"vgrind's language definition data base.\" \"\" vgrindefs(5)\n.xx \"terminal.\" \"\" \"vhangup: virtually ``hangup'' the current control\" \"\" vhangup(2)\n.xx \"on ex.\" \"\" \"vi: screen oriented (visual) display editor based\" \"\" vi(1)\n.xx \"\" \"encode/decode a binary file for transmission\" \"via mail.\" \"uuencode, uudecode:\" uuencode(1C)\n.xx \"\" \"rmail: handle remote mail received\" \"via uucp.\" \"\" rmail(1)\n.xx \"\" \"expand, unexpand: expand tabs to spaces, and\" \"vice versa.\" \"\" expand(1)\n.xx \"\" \"more, page: file perusal filter for crt\" \"viewing.\" \"\" more(1)\n.xx \"\" \"robots: fight off\" \"villainous robots.\" \"\" robots(6)\n.xx \"\" \"\" \"vipw: edit the password file.\" \"\" vipw(8)\n.xx \"\" \"vfork: spawn new process in a\" \"virtual memory efficient way.\" \"\" vfork(2)\n.xx \"\" \"vmstat: report\" \"virtual memory statistics.\" \"\" vmstat(1)\n.xx \"\" \"vhangup:\" \"virtually ``hangup'' the current control terminal.\" \"\" vhangup(2)\n.xx \"\" \"vi: screen oriented\" \"(visual) display editor based on ex.\" \"\" vi(1)\n.xx \"consumption.\" \"\" \"vlimit: control maximum system resource\" \"\" vlimit(3C)\n.xx \"vtroff, or troff.\" \"\" \"vlp: Format Lisp programs to be printed with nroff,\" \"\" vlp(1)\n.xx \"\" \"tn3270: full-screen remote login to IBM\" \"VM/CMS.\" \"\" tn3270(1)\n.xx \"\" \"\" \"vmstat: report virtual memory statistics.\" \"\" vmstat(1)\n.xx \"\" \"\" \"vnews: read news articles.\" \"\" vnews(1)\n.xx \"\" \"fs, inode: format of file system\" \"volume.\" \"\" fs(5)\n.xx \"\" \"\" \"vp: Versatec interface.\" \"\" vp(4)\n.xx \"\" \"\" \"vtimes: get information about resource utilization.\" \"\" vtimes(3C)\n.xx \"\" \"vlp: Format Lisp programs to be printed with nroff,\" \"vtroff, or troff.\" \"\" vlp(1)\n.xx \"\" \"\" \"vv: Proteon proNET 10 Megabit ring.\" \"\" vv(4)\n.xx \"\" \"\" \"vwidth: make troff width table for a font.\" \"\" vwidth(1)\n.xx \"\" \"\" \"w: who is on and what they are doing.\" \"\" w(1)\n.xx \"\" \"\" \"wait: await completion of process.\" \"\" wait(1)\n.xx \"\" \"read, readonly, set, shift, times, trap, umask,\" \"wait: command language.\" \"/exec, exit, export, login,\" sh(1)\n.xx \"\" \"wait:\" \"wait for a process to terminate.\" \"\" wait(3F)\n.xx \"\" \"wait:\" \"wait for background processes to complete.\" \"\" csh(1)\n.xx \"\" \"sigpause: atomically release blocked signals and\" \"wait for interrupt.\" \"\" sigpause(2)\n.xx \"\" \"wait, wait3:\" \"wait for process to terminate.\" \"\" wait(2)\n.xx \"\" \"\" \"wait: wait for a process to terminate.\" \"\" wait(3F)\n.xx \"\" \"\" \"wait: wait for background processes to complete.\" \"\" csh(1)\n.xx \"\" \"\" \"wait, wait3: wait for process to terminate.\" \"\" wait(2)\n.xx \"\" \"wait,\" \"wait3: wait for process to terminate.\" \"\" wait(2)\n.xx \"\" \"atq: print the queue of jobs\" \"waiting to be run.\" \"\" atq(1)\n.xx \"\" \"\" \"wall: write to all users.\" \"\" wall(1)\n.xx \"\" \"\" \"wc: word count.\" \"\" wc(1)\n.xx \"\" \"what: show what versions of object modules\" \"were used to construct a file.\" \"\" what(1)\n.xx \"\" \"whatis: describe\" \"what a command is.\" \"\" whatis(1)\n.xx \"\" \"crash:\" \"what happens when the system crashes.\" \"\" crash(8V)\n.xx \"used to construct a file.\" \"\" \"what: show what versions of object modules were\" \"\" what(1)\n.xx \"\" \"w: who is on and\" \"what they are doing.\" \"\" w(1)\n.xx \"construct a file.\" \"what: show\" \"what versions of object modules were used to\" \"\" what(1)\n.xx \"\" \"\" \"whatis: describe what a command is.\" \"\" whatis(1)\n.xx \"\" \"crash: what happens\" \"when the system crashes.\" \"\" crash(8V)\n.xx \"\" \"leave: remind you\" \"when you have to leave.\" \"\" leave(1)\n.xx \"program.\" \"\" \"whereis: locate source, binary, and or manual for\" \"\" whereis(1)\n.xx \"paths (\\fIcsh\\fR only).\" \"\" \"which: locate a program file including aliases and\" \"\" which(1)\n.xx \"exec, exit, export, login,/\" \"sh, for, case, if,\" \"while, \\fB:\\fP, \\fB.\\fP, break, continue, cd, eval,\" \"\" sh(1)\n.xx \"\" \"\" \"while: repeat commands conditionally.\" \"\" csh(1)\n.xx \"\" \"break: exit\" \"while/foreach loop.\" \"\" csh(1)\n.xx \"\" \"users: compact list of users\" \"who are on the system.\" \"\" users(1)\n.xx \"\" \"from:\" \"who is my mail from?.\" \"\" from(1)\n.xx \"\" \"w:\" \"who is on and what they are doing.\" \"\" w(1)\n.xx \"\" \"who:\" \"who is on the system.\" \"\" who(1)\n.xx \"\" \"biff: be notified if mail arrives and\" \"who it is from.\" \"\" biff(1)\n.xx \"\" \"\" \"who: who is on the system.\" \"\" who(1)\n.xx \"\" \"\" \"whoami: print effective current user id.\" \"\" whoami(1)\n.xx \"\" \"\" \"whois: DARPA Internet user name directory service.\" \"\" whois(1)\n.xx \"\" \"rwho:\" \"who's logged in on local machines.\" \"\" rwho(1C)\n.xx \"\" \"fold: fold long lines for finite\" \"width output device.\" \"\" fold(1)\n.xx \"\" \"vwidth: make troff\" \"width table for a font.\" \"\" vwidth(1)\n.xx \"\" \"window:\" \"window environment.\" \"\" window(1)\n.xx \"\" \"\" \"window: window environment.\" \"\" window(1)\n.xx \"\" \"fastboot, fasthalt: reboot/halt the system\" \"without checking the disks.\" \"\" fastboot(8)\n.xx \"\" \"sail: multi-user\" \"wooden ships and iron men.\" \"\" sail(6)\n.xx \"\" \"wc:\" \"word count.\" \"\" wc(1)\n.xx \"\" \"getc, getchar, fgetc, getw: get character or\" \"word from stream.\" \"\" getc(3S)\n.xx \"\" \"putc, putchar, fputc, putw: put character or\" \"word on a stream.\" \"\" putc(3S)\n.xx \"\" \"diction, explain: print\" \"wordy sentences; thesaurus for diction.\" \"\" diction(1)\n.xx \"\" \"cd: change\" \"working directory.\" \"\" cd(1)\n.xx \"\" \"chdir: change current\" \"working directory.\" \"\" chdir(2)\n.xx \"\" \"getcwd: get pathname of current\" \"working directory.\" \"\" getcwd(3F)\n.xx \"\" \"pwd:\" \"working directory name.\" \"\" pwd(1)\n.xx \"\" \"getwd: get current\" \"working directory pathname.\" \"\" getwd(3)\n.xx \"\" \"worm: Play the growing\" \"worm game.\" \"\" worm(6)\n.xx \"\" \"\" \"worm: Play the growing worm game.\" \"\" worm(6)\n.xx \"\" \"\" \"worms: animate worms on a display terminal.\" \"\" worms(6)\n.xx \"\" \"worms: animate\" \"worms on a display terminal.\" \"\" worms(6)\n.xx \"\" \"putc, fputc:\" \"write a character to a fortran logical unit.\" \"\" putc(3F)\n.xx \"\" \"write, writev:\" \"write output.\" \"\" write(2)\n.xx \"\" \"wall:\" \"write to all users.\" \"\" wall(1)\n.xx \"\" \"write:\" \"write to another user.\" \"\" write(1)\n.xx \"\" \"\" \"write: write to another user.\" \"\" write(1)\n.xx \"\" \"\" \"write, writev: write output.\" \"\" write(2)\n.xx \"\" \"write,\" \"writev: write output.\" \"\" write(2)\n.xx \"\" \"open: open a file for reading or\" \"writing, or create a new file.\" \"\" open(2)\n.xx \"\" \"utmp,\" \"wtmp: login records.\" \"\" utmp(5)\n.xx \"\" \"\" \"wump: the game of hunt-the-wumpus.\" \"\" wump(6)\n.xx \"\" \"ddn: DDN Standard Mode\" \"X.25 IMP interface.\" \"\" ddn(4)\n.xx \"\" \"en:\" \"Xerox 3 Mb/s Ethernet interface.\" \"\" en(4)\n.xx \"\" \"idp:\" \"Xerox Internet Datagram Protocol.\" \"\" idp(4P)\n.xx \"\" \"ns:\" \"Xerox Network Systems(tm) protocol family.\" \"\" ns(4F)\n.xx \"\" \"ns_addr, ns_ntoa:\" \"Xerox NS(tm)  address conversion routines.\" \"\" ns(3N)\n.xx \"\" \"spp:\" \"Xerox Sequenced Packet Protocol.\" \"\" spp(4P)\n.xx \"\" \"xsend,\" \"xget, enroll: secret mail.\" \"\" xsend(1)\n.xx \"\" \"\" \"XNSrouted: NS Routing Information Protocol daemon.\" \"\" XNSrouted(8C)\n.xx \"\" \"bit: and, or,\" \"xor, not, rshift, lshift bitwise functions.\" \"\" bit(3F)\n.xx \"\" \"\" \"xsend, xget, enroll: secret mail.\" \"\" xsend(1)\n.xx \"shared strings.\" \"\" \"xstr: extract strings from C programs to implement\" \"\" xstr(1)\n.xx \"\" \"j0, j1, jn,\" \"y0, y1, yn: bessel functions.\" \"\" j0(3M)\n.xx \"\" \"j0, j1, jn, y0,\" \"y1, yn: bessel functions.\" \"\" j0(3M)\n.xx \"\" \"\" \"yacc: yet another compiler-compiler.\" \"\" yacc(1)\n.xx \"\" \"\" \"yes: be repetitively affirmative.\" \"\" yes(1)\n.xx \"\" \"j0, j1, jn, y0, y1,\" \"yn: bessel functions.\" \"\" j0(3M)\n.xx \"\" \"compress, uncompress,\" \"zcat: compress and expand data.\" \"\" compress(1)\n.xx \"\" \"\" \"zork: the game of dungeon.\" \"\" zork(6)\n"
  },
  {
    "path": "share/man/man0/title.prm",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)title.prm\t6.2 (Berkeley) 5/15/86\n.\\\"\n.ps 18\n.vs 22\n.sp 2.75i\n.ft B\n.ce 2\nUNIX Programmer's Reference Manual\n(PRM)\n.ps 14\n.vs 16\n.sp |4i\n.ce 2\n4.3 Berkeley Software Distribution\nVirtual VAX\\-11 Version\n.sp |5.75i\n.ft R\n.pt 12\n.vs 16\n.ce\nApril, 1986\n.sp |8.2i\n.ce 5\nComputer Systems Research Group\nComputer Science Division\nDepartment of Electrical Engineering and Computer Science\nUniversity of California\nBerkeley, California  94720\n.bp\n.ll 5.3i\n.in 1.25i\n.hy 0\n.ps 10\n.vs 12p\n.sp |3.35i\nCopyright 1979, 1980, 1983, 1986 Regents of the University of California.\nPermission to copy these documents or any portion thereof as necessary\nfor licensed use of the software is granted to licensees of this\nsoftware, provided this copyright notice and statement of permission\nare included.\n.sp 2\nCopyright 1979, AT&T Bell Laboratories, Incorporated.\nHolders of \\x'-1p'UNIX\\v'-4p'\\s-3TM\\s0\\v'4p'/32V,\nSystem III, or System V software licenses are\npermitted to copy these documents, or any portion of them,\nas necessary for licensed use of the software,\nprovided this copyright notice and statement of permission\nare included.\n.sp 2\nThis manual reflects system enhancements made at Berkeley and sponsored\nin part by the Defense Advanced Research Projects Agency\n(DoD), Arpa Order No. 4871 monitored by the Naval Electronics Systems\nCommand under contract No. N00039-84-C-0089.\nThe views and conclusions contained in these documents are those of the\nauthors and should not be interpreted as representing official policies,\neither expressed or implied, of the Defense Research Projects Agency\nor of the US Government.\n.br\n.ll 6.5i\n.lt 6.5i\n.po .75i\n.in 0i\n.af % i\n.ds ET\\\"\n.de HD\n.po 0\n.lt 7.4i\n.tl ''''\n.lt\n.po\n'sp 18p\n.if o .tl '\\\\*(ET''- % -'\n.if e .tl '- % -''\\\\*(ET'\n'sp 18p\n.ns\n..\n.de FO\n'sp 18p\n.if e .tl '\\s9\\\\*(Dt''\\\\*(Ed\\s0'\n.if o .tl '\\s9\\\\*(Ed''\\\\*(Dt\\s0'\n'bp\n..\n.wh 0 HD\n.wh -60p FO\n.ds ET \\s9\\f2Table \\|of \\|Contents\\fP\\s0\n.ds Ed 4.3BSD\n.ds Dt April \\|1986\n.bp 1\n.ce\n\\f3TABLE \\|OF \\|CONTENTS\\fP\n.nr x .5i\n.in +\\nxu\n.nf\n.ta \\n(.lu-\\nxuR\n.de xx\n\\\\$1\\f3 \\a \\fP\\\\$2\n..\n.de t\n.sp 1v\n.ne .5i\n.cs 3\n.ti -.5i\n.ss 18\n\\f3\\s9\\\\$2. \\\\$3\\s0\\fP\n.ss 12\n.if t .sp .5v\n.cs 3 36\n.so \\\\$1\n..\n.t /usr/man/man0/toc2 2 \"System Calls\"\n.t /usr/man/man0/toc3 3 \"C Library Subroutines\"\n.t /usr/man/man0/toc3f 3F \"Fortran Library\"\n.t /usr/man/man0/toc4 4 \"Special Files\"\n.t /usr/man/man0/toc5 5 \"File Formats\"\n.in -.5i\n.cs 3\n.if n .ta 8n 16n 24n 32n 40n 48n 56n 64n 72n 80n\n.if t .ta .5i 1i 1.5i 2i 2.5i 3i 3.5i 4i 4.5i 5i 5.5i 6i 6.5i\n"
  },
  {
    "path": "share/man/man0/title.urm",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)title.urm\t6.2 (Berkeley) 5/15/86\n.\\\"\n.ps 18\n.vs 22\n.sp 2.75i\n.ft B\n.ce 2\nUNIX User's Reference Manual\n(URM)\n.ps 14\n.vs 16\n.sp |4i\n.ce 2\n4.3 Berkeley Software Distribution\nVirtual VAX\\-11 Version\n.sp |5.75i\n.ft R\n.pt 12\n.vs 16\n.ce\nApril, 1986\n.sp |8.2i\n.ce 5\nComputer Systems Research Group\nComputer Science Division\nDepartment of Electrical Engineering and Computer Science\nUniversity of California\nBerkeley, California  94720\n.bp\n.ll 5.3i\n.in 1.25i\n.hy 0\n.ps 10\n.vs 12p\n.sp |3.35i\nCopyright 1979, 1980, 1983, 1986 Regents of the University of California.\nPermission to copy these documents or any portion thereof as necessary\nfor licensed use of the software is granted to licensees of this\nsoftware, provided this copyright notice and statement of permission\nare included.\n.sp 2\nCopyright 1979, AT&T Bell Laboratories, Incorporated.\nHolders of \\x'-1p'UNIX\\v'-4p'\\s-3TM\\s0\\v'4p'/32V,\nSystem III, or System V software licenses are\npermitted to copy these documents, or any portion of them,\nas necessary for licensed use of the software,\nprovided this copyright notice and statement of permission\nare included.\n.sp 2\nThis manual reflects system enhancements made at Berkeley and sponsored\nin part by the Defense Advanced Research Projects Agency\n(DoD), Arpa Order No. 4871 monitored by the Naval Electronics Systems\nCommand under contract No. N00039-84-C-0089.\nThe views and conclusions contained in these documents are those of the\nauthors and should not be interpreted as representing official policies,\neither expressed or implied, of the Defense Research Projects Agency\nor of the US Government.\n"
  },
  {
    "path": "share/man/man0/toc.in",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)toc.in\t6.2 (Berkeley) 5/12/86\n.\\\"\n.af % i\n.if t .pn 11\\\"TABLE OF CONTENTS\n.if n .pn 15\n.tr ~\n.ll 6.5i\n.lt 6.5i\n.po .75i\n.ds ET\\\"\n.de HD\n.po 0\n.lt 7.4i\n.tl ''''\n.lt\n.po\n'sp 18p\n.if o .tl '\\\\*(ET''- % -'\n.if e .tl '- % -''\\\\*(ET'\n'sp 18p\n.ns\n..\n.de FO\n'sp 18p\n.if e .tl '\\s9\\\\*(Dt''\\\\*(Ed\\s0'\n.if o .tl '\\s9\\\\*(Ed''\\\\*(Dt\\s0'\n'bp\n..\n.wh 0 HD\n.wh -60p FO\n.if \\n(nl .bp\n.br\n.ds ET \\s9\\f2Table \\|of \\|Contents\\fP\\s0\n.ds Ed 4.3BSD\n.ds Dt April \\|1986\n.ce\n\\f3TABLE \\|OF \\|CONTENTS\\fP\n.nr x .5i\n.in +\\nxu\n.nf\n.ta \\n(.lu-\\nxuR\n.de xx\n\\\\$1\\f3 \\a \\fP\\\\$2\n..\n.de t\n.sp 1v\n.ne .5i\n.cs 3\n.ti -.5i\n.ss 18\n\\f3\\s9\\\\$2. \\\\$3\\s0\\fP\n.ss 12\n.if t .sp .5v\n.cs 3 36\n.so \\\\$1\n..\n.t toc1 1 \"Commands and Application Programs\"\n.t toc2 2 \"System Calls\"\n.t toc3 3 \"C Library Subroutines\"\n.t toc3f 3F \"Fortran Library\"\n.t toc4 4 \"Special Files\"\n.t toc5 5 \"File Formats\"\n.t toc6 6 \"Games\"\n.t toc7 7 \"Miscellaneous\"\n.t toc8 8 \"System Maintenance\"\n.in -.5i\n.cs 3\n.if n .ta 8n 16n 24n 32n 40n 48n 56n 64n 72n 80n\n.if t .ta .5i 1i 1.5i 2i 2.5i 3i 3.5i 4i 4.5i 5i 5.5i 6i 6.5i\n"
  },
  {
    "path": "share/man/man0/toc1",
    "content": ".xx \"intro\" \"introduction to commands\"\n.xx \"adb\" \"debugger\"\n.xx \"addbib\" \"create or extend bibliographic database\"\n.xx \"apply\" \"apply a command to a set of arguments\"\n.xx \"apropos\" \"locate commands by keyword lookup\"\n.xx \"ar\" \"archive and library maintainer\"\n.xx \"as\" \"VAX-11 assembler\"\n.xx \"at\" \"execute commands at a later time\"\n.xx \"atq\" \"print the queue of jobs waiting to be run\"\n.xx \"atrm\" \"remove jobs spooled by at\"\n.xx \"awk\" \"pattern scanning and processing language\"\n.xx \"basename\" \"strip filename affixes\"\n.xx \"bc\" \"arbitrary-precision arithmetic language\"\n.xx \"bib\" \"bibliographic formatter; list bibliographic reference items\"\n.xx \"biff\" \"be notified if mail arrives and who it is from\"\n.xx \"binmail\" \"send or receive mail among users\"\n.xx \"cal\" \"print calendar\"\n.xx \"calendar\" \"reminder service\"\n.xx \"cat\" \"catenate and print\"\n.xx \"cb\" \"C program beautifier\"\n.xx \"cc\" \"C compiler\"\n.xx \"cd\" \"change working directory\"\n.xx \"checknr\" \"check nroff/troff files\"\n.xx \"chfn\" \"change password file information\"\n.xx \"chgrp\" \"change group\"\n.xx \"chmod\" \"change mode\"\n.xx \"chsh\" \"change password file information\"\n.xx \"clear\" \"clear terminal screen\"\n.xx \"cmp\" \"compare two files\"\n.xx \"col\" \"filter reverse line feeds\"\n.xx \"colcrt\" \"filter nroff output for CRT previewing\"\n.xx \"colrm\" \"remove columns from a file\"\n.xx \"comm\" \"select or reject lines common to two sorted files\"\n.xx \"compress\" \"compress and expand data\"\n.xx \"cp\" \"copy\"\n.xx \"crypt\" \"encode/decode\"\n.xx \"csh\" \"a shell (command interpreter) with C-like syntax\"\n.xx \"ctags\" \"create a tags file\"\n.xx \"date\" \"print and set the date\"\n.xx \"dbx\" \"debugger\"\n.xx \"dc\" \"desk calculator\"\n.xx \"dd\" \"convert and copy a file\"\n.xx \"deroff\" \"remove nroff, troff, tbl and eqn constructs\"\n.xx \"df\" \"disk free\"\n.xx \"diction\" \"print wordy sentences; thesaurus for diction\"\n.xx \"diff\" \"differential file and directory comparator\"\n.xx \"diff3\" \"3-way differential file comparison\"\n.xx \"du\" \"summarize disk usage\"\n.xx \"echo\" \"echo arguments\"\n.xx \"ed\" \"text editor\"\n.xx \"efl\" \"Extended Fortran Language\"\n.xx \"eqn\" \"typeset mathematics\"\n.xx \"error\" \"analyze and disperse compiler error messages\"\n.xx \"ex\" \"text editor\"\n.xx \"expand\" \"expand tabs to spaces, and vice versa\"\n.xx \"expr\" \"evaluate arguments as an expression\"\n.xx \"f77\" \"Fortran 77 compiler\"\n.xx \"false\" \"provide truth values\"\n.xx \"file\" \"determine file type\"\n.xx \"find\" \"find files\"\n.xx \"finger\" \"user information lookup program\"\n.xx \"fmt\" \"simple text formatter\"\n.xx \"fold\" \"fold long lines for finite width output device\"\n.xx \"fp\" \"Functional Programming language compiler/interpreter\"\n.xx \"fpr\" \"print Fortran file\"\n.xx \"from\" \"who is my mail from?\"\n.xx \"fsplit\" \"split a multi-routine Fortran file into individual files\"\n.xx \"ftp\" \"ARPANET file transfer program\"\n.xx \"gcore\" \"get core images of running processes\"\n.xx \"gprof\" \"display call graph profile data\"\n.xx \"graph\" \"draw a graph\"\n.xx \"grep\" \"search a file for a pattern\"\n.xx \"groups\" \"show group memberships\"\n.xx \"head\" \"give first few lines\"\n.xx \"hostid\" \"set or print identifier of current host system\"\n.xx \"hostname\" \"set or print name of current host system\"\n.xx \"indent\" \"indent and format C program source\"\n.xx \"install\" \"install binaries\"\n.xx \"iostat\" \"report I/O statistics\"\n.xx \"join\" \"relational database operator\"\n.xx \"jove\" \"an interactive display-oriented text editor\"\n.xx \"kill\" \"terminate a process with extreme prejudice\"\n.xx \"last\" \"indicate last logins of users and teletypes\"\n.xx \"lastcomm\" \"show last commands executed in reverse order\"\n.xx \"ld\" \"link editor\"\n.xx \"learn\" \"computer aided instruction about UNIX\"\n.xx \"leave\" \"remind you when you have to leave\"\n.xx \"lex\" \"generator of lexical analysis programs\"\n.xx \"lint\" \"a C program verifier\"\n.xx \"lisp\" \"lisp interpreter\"\n.xx \"liszt\" \"compile a Franz Lisp program\"\n.xx \"ln\" \"make links\"\n.xx \"lock\" \"reserve a terminal\"\n.xx \"logger\" \"make entries in the system log\"\n.xx \"login\" \"sign on\"\n.xx \"look\" \"find lines in a sorted list\"\n.xx \"lookbib\" \"build inverted index for a bibliography, find references in a bibliography\"\n.xx \"lorder\" \"find ordering relation for an object library\"\n.xx \"lpq\" \"spool queue examination program\"\n.xx \"lpr\" \"off line print\"\n.xx \"lprm\" \"remove jobs from the line printer spooling queue\"\n.xx \"lptest\" \"generate lineprinter ripple pattern\"\n.xx \"ls\" \"list contents of directory\"\n.xx \"lxref\" \"lisp cross reference program\"\n.xx \"m4\" \"macro processor\"\n.xx \"mail\" \"send and receive mail\"\n.xx \"make\" \"maintain program groups\"\n.xx \"man\" \"find manual information by keywords; print out the manual\"\n.xx \"mesg\" \"permit or deny messages\"\n.xx \"mh\" \"Message Handler\"\n.xx \"mkdir\" \"make a directory\"\n.xx \"mkstr\" \"create an error message file by massaging C source\"\n.xx \"more\" \"file perusal filter for crt viewing\"\n.xx \"mset\" \"retrieve ASCII to IBM 3270 keyboard map\"\n.xx \"msgs\" \"system messages and junk mail program\"\n.xx \"mt\" \"magnetic tape manipulating program\"\n.xx \"mv\" \"move or rename files\"\n.xx \"netstat\" \"show network status\"\n.xx \"newaliases\" \"rebuild the data base for the mail aliases file\"\n.xx \"nice\" \"run a command at low priority (\\fIsh\\fR only)\"\n.xx \"nm\" \"print name list\"\n.xx \"notes\" \"a news system\"\n.xx \"nroff\" \"text formatting\"\n.xx \"od\" \"octal, decimal, hex, ascii dump\"\n.xx \"pagesize\" \"print system page size\"\n.xx \"passwd\" \"change password file information\"\n.xx \"patch\" \"a program for applying a diff file to an original\"\n.xx \"pc\" \"Pascal compiler\"\n.xx \"pdx\" \"pascal debugger\"\n.xx \"pi\" \"Pascal interpreter code translator\"\n.xx \"pix\" \"Pascal interpreter and executor\"\n.xx \"plot\" \"graphics filters\"\n.xx \"pmerge\" \"pascal file merger\"\n.xx \"pr\" \"print file\"\n.xx \"printenv\" \"print out the environment\"\n.xx \"prof\" \"display profile data\"\n.xx \"ps\" \"process status\"\n.xx \"ptx\" \"permuted index\"\n.xx \"pwd\" \"working directory name\"\n.xx \"px\" \"Pascal interpreter\"\n.xx \"pxp\" \"Pascal execution profiler\"\n.xx \"pxref\" \"Pascal cross-reference program\"\n.xx \"quota\" \"display disc usage and limits\"\n.xx \"ranlib\" \"convert archives to random libraries\"\n.xx \"ratfor\" \"rational Fortran dialect\"\n.xx \"rcp\" \"remote file copy\"\n.xx \"rcsintro\" \"introduction to RCS commands\"\n.xx \"rdist\" \"remote file distribution program\"\n.xx \"readnews\" \"read news articles\"\n.xx \"refer\" \"find and insert literature references in documents\"\n.xx \"rev\" \"reverse lines of a file\"\n.xx \"rlogin\" \"remote login\"\n.xx \"rm\" \"remove (unlink) files or directories\"\n.xx \"rmail\" \"handle remote mail received via uucp\"\n.xx \"rmdir\" \"remove (unlink) directories or files\"\n.xx \"roffbib\" \"run off bibliographic database\"\n.xx \"rsh\" \"remote shell\"\n.xx \"ruptime\" \"show host status of local machines\"\n.xx \"rwho\" \"who's logged in on local machines\"\n.xx \"sccs\" \"front end for the SCCS subsystem\"\n.xx \"script\" \"make typescript of terminal session\"\n.xx \"sed\" \"stream editor\"\n.xx \"sendbug\" \"mail a system bug report to 4bsd-bugs\"\n.xx \"sh\" \"command language\"\n.xx \"size\" \"size of an object file\"\n.xx \"sleep\" \"suspend execution for an interval\"\n.xx \"soelim\" \"eliminate \\&.so's from nroff input\"\n.xx \"sort\" \"sort or merge files\"\n.xx \"sortbib\" \"sort bibliographic database\"\n.xx \"spell\" \"find spelling errors\"\n.xx \"spline\" \"interpolate smooth curve\"\n.xx \"split\" \"split a file into pieces\"\n.xx \"strings\" \"find the printable strings in a object, or other binary, file\"\n.xx \"strip\" \"remove symbols and relocation bits\"\n.xx \"struct\" \"structure Fortran programs\"\n.xx \"stty\" \"set terminal options\"\n.xx \"style\" \"analyze surface characteristics of a document\"\n.xx \"su\" \"substitute user id temporarily\"\n.xx \"sum\" \"sum and count blocks in a file\"\n.xx \"symorder\" \"rearrange name list\"\n.xx \"sysline\" \"display system status on status line of a terminal\"\n.xx \"systat\" \"display system statistics on a crt\"\n.xx \"tabs\" \"set terminal tabs\"\n.xx \"tail\" \"deliver the last part of a file\"\n.xx \"talk\" \"talk to another user\"\n.xx \"tar\" \"tape archiver\"\n.xx \"tbl\" \"format tables for nroff or troff\"\n.xx \"tc\" \"photoypesetter simulator\"\n.xx \"tcopy\" \"copy a mag tape\"\n.xx \"tee\" \"pipe fitting\"\n.xx \"telnet\" \"user interface to the TELNET protocol\"\n.xx \"test\" \"condition command\"\n.xx \"tftp\" \"trivial file transfer program\"\n.xx \"time\" \"time a command\"\n.xx \"tip\" \"connect to a remote system\"\n.xx \"tk\" \"paginator for the Tektronix 4014\"\n.xx \"tn3270\" \"full-screen remote login to IBM VM/CMS\"\n.xx \"touch\" \"update date last modified of a file\"\n.xx \"tp\" \"manipulate tape archive\"\n.xx \"tr\" \"translate characters\"\n.xx \"troff\" \"text formatting and typesetting\"\n.xx \"true\" \"provide truth values\"\n.xx \"tset\" \"terminal dependent initialization\"\n.xx \"tsort\" \"topological sort\"\n.xx \"tty\" \"get terminal name\"\n.xx \"ul\" \"do underlining\"\n.xx \"unifdef\" \"remove ifdef'ed lines\"\n.xx \"uniq\" \"report repeated lines in a file\"\n.xx \"units\" \"conversion program\"\n.xx \"uptime\" \"show how long system has been up\"\n.xx \"users\" \"compact list of users who are on the system\"\n.xx \"uucp\" \"unix to unix copy\"\n.xx \"uuencode\" \"encode/decode a binary file for transmission via mail\"\n.xx \"uulog\" \"display UUCP log files\"\n.xx \"uuname\" \"list names of UUCP hosts\"\n.xx \"uuq\" \"examine or manipulate the uucp queue\"\n.xx \"uusend\" \"send a file to a remote host\"\n.xx \"uux\" \"unix to unix command execution\"\n.xx \"vacation\" \"return ``I am on vacation'' indication\"\n.xx \"vgrind\" \"grind nice listings of programs\"\n.xx \"vi\" \"screen oriented (visual) display editor based on ex\"\n.xx \"vlp\" \"Format Lisp programs to be printed with nroff, vtroff, or troff\"\n.xx \"vmstat\" \"report virtual memory statistics\"\n.xx \"vnews\" \"read news articles\"\n.xx \"vwidth\" \"make troff width table for a font\"\n.xx \"w\" \"who is on and what they are doing\"\n.xx \"wait\" \"await completion of process\"\n.xx \"wall\" \"write to all users\"\n.xx \"wc\" \"word count\"\n.xx \"what\" \"show what versions of object modules were used to construct a file\"\n.xx \"whatis\" \"describe what a command is\"\n.xx \"whereis\" \"locate source, binary, and or manual for program\"\n.xx \"which\" \"locate a program file including aliases and paths (\\fIcsh\\fR only)\"\n.xx \"who\" \"who is on the system\"\n.xx \"whoami\" \"print effective current user id\"\n.xx \"whois\" \"DARPA Internet user name directory service\"\n.xx \"window\" \"window environment\"\n.xx \"write\" \"write to another user\"\n.xx \"xsend\" \"secret mail\"\n.xx \"xstr\" \"extract strings from C programs to implement shared strings\"\n.xx \"yacc\" \"yet another compiler-compiler\"\n.xx \"yes\" \"be repetitively affirmative\"\n"
  },
  {
    "path": "share/man/man0/toc2",
    "content": ".xx \"intro\" \"introduction to system calls and error numbers\"\n.xx \"accept\" \"accept a connection on a socket\"\n.xx \"access\" \"determine accessibility of file\"\n.xx \"acct\" \"turn accounting on or off\"\n.xx \"adjtime\" \"correct the time to allow synchronization of the system clock\"\n.xx \"bind\" \"bind a name to a socket\"\n.xx \"brk\" \"change data segment size\"\n.xx \"chdir\" \"change current working directory\"\n.xx \"chmod\" \"change mode of file\"\n.xx \"chown\" \"change owner and group of a file\"\n.xx \"chroot\" \"change root directory\"\n.xx \"close\" \"delete a descriptor\"\n.xx \"connect\" \"initiate a connection on a socket\"\n.xx \"creat\" \"create a new file\"\n.xx \"dup\" \"duplicate a descriptor\"\n.xx \"execve\" \"execute a file\"\n.xx \"exit\" \"terminate a process\"\n.xx \"fcntl\" \"file control\"\n.xx \"flock\" \"apply or remove an advisory lock on an open file\"\n.xx \"fork\" \"create a new process\"\n.xx \"fsync\" \"synchronize a file's in-core state with that on disk\"\n.xx \"getdtablesize\" \"get descriptor table size\"\n.xx \"getgid\" \"get group identity\"\n.xx \"getgroups\" \"get group access list\"\n.xx \"gethostid\" \"get/set unique identifier of current host\"\n.xx \"gethostname\" \"get/set name of current host\"\n.xx \"getitimer\" \"get/set value of interval timer\"\n.xx \"getpagesize\" \"get system page size\"\n.xx \"getpeername\" \"get name of connected peer\"\n.xx \"getpgrp\" \"get process group\"\n.xx \"getpid\" \"get process identification\"\n.xx \"getpriority\" \"get/set program scheduling priority\"\n.xx \"getrlimit\" \"control maximum system resource consumption\"\n.xx \"getrusage\" \"get information about resource utilization\"\n.xx \"getsockname\" \"get socket name\"\n.xx \"getsockopt\" \"get and set options on sockets\"\n.xx \"gettimeofday\" \"get/set date and time\"\n.xx \"getuid\" \"get user identity\"\n.xx \"ioctl\" \"control device\"\n.xx \"kill\" \"send signal to a process\"\n.xx \"killpg\" \"send signal to a process group\"\n.xx \"link\" \"make a hard link to a file\"\n.xx \"listen\" \"listen for connections on a socket\"\n.xx \"lseek\" \"move read/write pointer\"\n.xx \"mkdir\" \"make a directory file\"\n.xx \"mknod\" \"make a special file\"\n.xx \"mount\" \"mount or remove file system\"\n.xx \"open\" \"open a file for reading or writing, or create a new file\"\n.xx \"pipe\" \"create an interprocess communication channel\"\n.xx \"profil\" \"execution time profile\"\n.xx \"ptrace\" \"process trace\"\n.xx \"quota\" \"manipulate disk quotas\"\n.xx \"read\" \"read input\"\n.xx \"readlink\" \"read value of a symbolic link\"\n.xx \"reboot\" \"reboot system or halt processor\"\n.xx \"recv\" \"receive a message from a socket\"\n.xx \"rename\" \"change the name of a file\"\n.xx \"rmdir\" \"remove a directory file\"\n.xx \"select\" \"synchronous I/O multiplexing\"\n.xx \"send\" \"send a message from a socket\"\n.xx \"setgroups\" \"set group access list\"\n.xx \"setpgrp\" \"set process group\"\n.xx \"setquota\" \"enable/disable quotas on a file system\"\n.xx \"setregid\" \"set real and effective group ID\"\n.xx \"setreuid\" \"set real and effective user ID's\"\n.xx \"shutdown\" \"shut down part of a full-duplex connection\"\n.xx \"sigblock\" \"block signals\"\n.xx \"sigpause\" \"atomically release blocked signals and wait for interrupt\"\n.xx \"sigreturn\" \"return from signal\"\n.xx \"sigsetmask\" \"set current signal mask\"\n.xx \"sigstack\" \"set and/or get signal stack context\"\n.xx \"sigvec\" \"software signal facilities\"\n.xx \"socket\" \"create an endpoint for communication\"\n.xx \"socketpair\" \"create a pair of connected sockets\"\n.xx \"stat\" \"get file status\"\n.xx \"swapon\" \"add a swap device for interleaved paging/swapping\"\n.xx \"symlink\" \"make symbolic link to a file\"\n.xx \"sync\" \"update super-block\"\n.xx \"syscall\" \"indirect system call\"\n.xx \"truncate\" \"truncate a file to a specified length\"\n.xx \"umask\" \"set file creation mode mask\"\n.xx \"unlink\" \"remove directory entry\"\n.xx \"utimes\" \"set file times\"\n.xx \"vfork\" \"spawn new process in a virtual memory efficient way\"\n.xx \"vhangup\" \"virtually ``hangup'' the current control terminal\"\n.xx \"wait\" \"wait for process to terminate\"\n.xx \"write\" \"write output\"\n"
  },
  {
    "path": "share/man/man0/toc3",
    "content": ".xx \"intro\" \"introduction to C library functions\"\n.xx \"abort\" \"generate a fault\"\n.xx \"abs\" \"integer absolute value\"\n.xx \"alarm\" \"schedule signal after specified time\"\n.xx \"asinh\" \"inverse hyperbolic functions\"\n.xx \"assert\" \"program verification\"\n.xx \"atof\" \"convert ASCII to numbers\"\n.xx \"bstring\" \"bit and byte string operations\"\n.xx \"byteorder\" \"convert values between host and network byte order\"\n.xx \"crypt\" \"DES encryption\"\n.xx \"ctime\" \"convert date and time to ASCII\"\n.xx \"ctype\" \"character classification macros\"\n.xx \"curses\" \"screen functions with ``optimal'' cursor motion\"\n.xx \"dbm\" \"data base subroutines\"\n.xx \"directory\" \"directory operations\"\n.xx \"ecvt\" \"output conversion\"\n.xx \"end\" \"last locations in program\"\n.xx \"erf\" \"error functions\"\n.xx \"execl\" \"execute a file\"\n.xx \"exit\" \"terminate a process after flushing any pending output\"\n.xx \"exp\" \"exponential, logarithm, power\"\n.xx \"fclose\" \"close or flush a stream\"\n.xx \"ferror\" \"stream status inquiries\"\n.xx \"floor\" \"absolute value, floor, ceiling, and round-to-nearest functions\"\n.xx \"fopen\" \"open a stream\"\n.xx \"fread\" \"buffered binary input/output\"\n.xx \"frexp\" \"split into mantissa and exponent\"\n.xx \"fseek\" \"reposition a stream\"\n.xx \"getc\" \"get character or word from stream\"\n.xx \"getdisk\" \"get disk description by its name\"\n.xx \"getenv\" \"value for environment name\"\n.xx \"getfsent\" \"get file system descriptor file entry\"\n.xx \"getgrent\" \"get group file entry\"\n.xx \"gethostbyname\" \"get network host entry\"\n.xx \"getlogin\" \"get login name\"\n.xx \"getnetent\" \"get network entry\"\n.xx \"getopt\" \"get option letter from argv\"\n.xx \"getpass\" \"read a password\"\n.xx \"getprotoent\" \"get protocol entry\"\n.xx \"getpw\" \"get name from uid\"\n.xx \"getpwent\" \"get password file entry\"\n.xx \"gets\" \"get a string from a stream\"\n.xx \"getservent\" \"get service entry\"\n.xx \"getttyent\" \"get ttys file entry\"\n.xx \"getusershell\" \"get legal user shells\"\n.xx \"getwd\" \"get current working directory pathname\"\n.xx \"hypot\" \"Euclidean distance, complex absolute value\"\n.xx \"ieee\" \"copysign, remainder, exponent manipulations\"\n.xx \"inet\" \"Internet address manipulation routines\"\n.xx \"infnan\" \"signals invalid floating-point operations on a VAX (temporary)\"\n.xx \"initgroups\" \"initialize group access list\"\n.xx \"insque\" \"insert/remove element from a queue\"\n.xx \"j0\" \"bessel functions\"\n.xx \"lgamma\" \"log gamma function\"\n.xx \"lib2648\" \"subroutines for the HP 2648 graphics terminal\"\n.xx \"malloc\" \"memory allocator\"\n.xx \"math\" \"introduction to mathematical library functions\"\n.xx \"mktemp\" \"make a unique file name\"\n.xx \"monitor\" \"prepare execution profile\"\n.xx \"mp\" \"multiple precision integer arithmetic\"\n.xx \"ndbm\" \"data base subroutines\"\n.xx \"nice\" \"set program priority\"\n.xx \"nlist\" \"get entries from name list\"\n.xx \"ns\" \"Xerox NS(tm)  address conversion routines\"\n.xx \"pause\" \"stop until signal\"\n.xx \"perror\" \"system error messages\"\n.xx \"plot\" \"graphics interface\"\n.xx \"popen\" \"initiate I/O to/from a process\"\n.xx \"printf\" \"formatted output conversion\"\n.xx \"psignal\" \"system signal messages\"\n.xx \"putc\" \"put character or word on a stream\"\n.xx \"puts\" \"put a string on a stream\"\n.xx \"qsort\" \"quicker sort\"\n.xx \"rand\" \"random number generator\"\n.xx \"random\" \"better random number generator; routines for changing generators\"\n.xx \"rcmd\" \"routines for returning a stream to a remote command\"\n.xx \"regex\" \"regular expression handler\"\n.xx \"resolver\" \"resolver routines\"\n.xx \"rexec\" \"return stream to a remote command\"\n.xx \"scandir\" \"scan a directory\"\n.xx \"scanf\" \"formatted input conversion\"\n.xx \"setbuf\" \"assign buffering to a stream\"\n.xx \"setjmp\" \"non-local goto\"\n.xx \"setuid\" \"set user and group ID\"\n.xx \"siginterrupt\" \"allow signals to interrupt system calls\"\n.xx \"signal\" \"simplified software signal facilities\"\n.xx \"sin\" \"trigonometric functions and their inverses\"\n.xx \"sinh\" \"hyperbolic functions\"\n.xx \"sleep\" \"suspend execution for interval\"\n.xx \"sqrt\" \"cube root, square root\"\n.xx \"stdio\" \"standard buffered input/output package\"\n.xx \"string\" \"string operations\"\n.xx \"stty\" \"set and get terminal state (defunct)\"\n.xx \"swab\" \"swap bytes\"\n.xx \"syslog\" \"control system log\"\n.xx \"system\" \"issue a shell command\"\n.xx \"termcap\" \"terminal independent operation routines\"\n.xx \"time\" \"get date and time\"\n.xx \"times\" \"get process times\"\n.xx \"ttyname\" \"find name of a terminal\"\n.xx \"ualarm\" \"schedule signal after specified time\"\n.xx \"ungetc\" \"push character back into input stream\"\n.xx \"usleep\" \"suspend execution for interval\"\n.xx \"utime\" \"set file times\"\n.xx \"valloc\" \"aligned memory allocator\"\n.xx \"varargs\" \"variable argument list\"\n.xx \"vlimit\" \"control maximum system resource consumption\"\n.xx \"vtimes\" \"get information about resource utilization\"\n"
  },
  {
    "path": "share/man/man0/toc3f",
    "content": ".xx \"intro\" \"introduction to FORTRAN library functions\"\n.xx \"abort\" \"abnormal termination\"\n.xx \"access\" \"determine accessability of a file\"\n.xx \"alarm\" \"execute a subroutine after a specified time\"\n.xx \"bessel\" \"of two kinds for integer orders\"\n.xx \"bit\" \"and, or, xor, not, rshift, lshift bitwise functions\"\n.xx \"chdir\" \"change default directory\"\n.xx \"chmod\" \"change mode of a file\"\n.xx \"etime\" \"return elapsed execution time\"\n.xx \"exit\" \"terminate process with status\"\n.xx \"fdate\" \"return date and time in an ASCII string\"\n.xx \"flmin\" \"return extreme values\"\n.xx \"flush\" \"flush output to a logical unit\"\n.xx \"fork\" \"create a copy of this process\"\n.xx \"fseek\" \"reposition a file on a logical unit\"\n.xx \"getarg\" \"return command line arguments\"\n.xx \"getc\" \"get a character from a logical unit\"\n.xx \"getcwd\" \"get pathname of current working directory\"\n.xx \"getenv\" \"get value of environment variables\"\n.xx \"getlog\" \"get user's login name\"\n.xx \"getpid\" \"get process id\"\n.xx \"getuid\" \"get user or group ID of the caller\"\n.xx \"hostnm\" \"get name of current host\"\n.xx \"idate\" \"return date or time in numerical form\"\n.xx \"index\" \"tell about character objects\"\n.xx \"ioinit\" \"change f77 I/O initialization\"\n.xx \"kill\" \"send a signal to a process\"\n.xx \"link\" \"make a link to an existing file\"\n.xx \"loc\" \"return the address of an object\"\n.xx \"long\" \"integer object conversion\"\n.xx \"malloc\" \"memory allocator\"\n.xx \"perror\" \"get system error messages\"\n.xx \"plot\" \"f77 library interface to \\fIplot\\fR (3X) libraries.\"\n.xx \"putc\" \"write a character to a fortran logical unit\"\n.xx \"qsort\" \"quick sort\"\n.xx \"rand\" \"return random values\"\n.xx \"random\" \"better random number generator\"\n.xx \"rename\" \"rename a file\"\n.xx \"signal\" \"change the action for a signal\"\n.xx \"sleep\" \"suspend execution for an interval\"\n.xx \"stat\" \"get file status\"\n.xx \"system\" \"execute a UNIX command\"\n.xx \"time\" \"return system time\"\n.xx \"topen\" \"f77 tape I/O\"\n.xx \"traper\" \"trap arithmetic errors\"\n.xx \"trapov\" \"trap and repair floating point overflow\"\n.xx \"trpfpe\" \"trap and repair floating point faults\"\n.xx \"ttynam\" \"find name of a terminal port\"\n.xx \"unlink\" \"remove a directory entry\"\n.xx \"wait\" \"wait for a process to terminate\"\n"
  },
  {
    "path": "share/man/man0/toc4",
    "content": ".xx \"intro\" \"introduction to special files and hardware support\"\n.xx \"acc\" \"ACC LH/DH IMP interface\"\n.xx \"ad\" \"Data Translation A/D converter\"\n.xx \"arp\" \"Address Resolution Protocol\"\n.xx \"autoconf\" \"diagnostics from the autoconfiguration code\"\n.xx \"bk\" \"line discipline for machine-machine communication (obsolete)\"\n.xx \"cons\" \"VAX-11 console interface\"\n.xx \"crl\" \"VAX 8600 console RL02 interface\"\n.xx \"css\" \"DEC IMP-11A LH/DH IMP interface\"\n.xx \"ct\" \"phototypesetter interface\"\n.xx \"ddn\" \"DDN Standard Mode X.25 IMP interface\"\n.xx \"de\" \"DEC DEUNA 10 Mb/s Ethernet interface\"\n.xx \"dh\" \"DH-11/DM-11 communications multiplexer\"\n.xx \"dhu\" \"DHU-11 communications multiplexer\"\n.xx \"dmc\" \"DEC DMC-11/DMR-11 point-to-point communications device\"\n.xx \"dmf\" \"DMF-32, terminal multiplexor\"\n.xx \"dmz\" \"DMZ-32 terminal multiplexor\"\n.xx \"dn\" \"DN-11 autocall unit interface\"\n.xx \"drum\" \"paging device\"\n.xx \"dz\" \"DZ-11 communications multiplexer\"\n.xx \"ec\" \"3Com 10 Mb/s Ethernet interface\"\n.xx \"en\" \"Xerox 3 Mb/s Ethernet interface\"\n.xx \"ex\" \"Excelan 10 Mb/s Ethernet interface\"\n.xx \"fl\" \"console floppy interface\"\n.xx \"hdh\" \"ACC IF-11/HDH IMP interface\"\n.xx \"hk\" \"RK6-11/RK06 and RK07 moving head disk\"\n.xx \"hp\" \"MASSBUS disk interface\"\n.xx \"ht\" \"TM-03/TE-16,TU-45,TU-77 MASSBUS magtape interface\"\n.xx \"hy\" \"Network Systems Hyperchannel interface\"\n.xx \"icmp\" \"Internet Control Message Protocol\"\n.xx \"idp\" \"Xerox Internet Datagram Protocol\"\n.xx \"ik\" \"Ikonas frame buffer, graphics device interface\"\n.xx \"il\" \"Interlan NI1010 10 Mb/s Ethernet interface\"\n.xx \"imp\" \"1822 network interface\"\n.xx \"imp\" \"IMP raw socket interface\"\n.xx \"inet\" \"Internet protocol family\"\n.xx \"ip\" \"Internet Protocol\"\n.xx \"ix\" \"Interlan Np100 10 Mb/s Ethernet interface\"\n.xx \"kg\" \"KL-11/DL-11W line clock\"\n.xx \"lo\" \"software loopback network interface\"\n.xx \"lp\" \"line printer\"\n.xx \"mem\" \"main memory\"\n.xx \"mt\" \"TM78/TU-78 MASSBUS magtape interface\"\n.xx \"mtio\" \"UNIX magtape interface\"\n.xx \"np\" \"Interlan Np100 10 Mb/s Ethernet interface\"\n.xx \"ns\" \"Xerox Network Systems(tm) protocol family\"\n.xx \"nsip\" \"software network interface encapsulating ns packets in ip packets.\"\n.xx \"null\" \"data sink\"\n.xx \"pcl\" \"DEC CSS PCL-11 B Network Interface\"\n.xx \"ps\" \"Evans and Sutherland Picture System 2 graphics device interface\"\n.xx \"pty\" \"pseudo terminal driver\"\n.xx \"qe\" \"DEC DEQNA Q-bus 10 Mb/s Ethernet interface\"\n.xx \"rx\" \"DEC RX02 floppy disk interface\"\n.xx \"spp\" \"Xerox Sequenced Packet Protocol\"\n.xx \"tb\" \"line discipline for digitizing devices\"\n.xx \"tcp\" \"Internet Transmission Control Protocol\"\n.xx \"tm\" \"TM-11/TE-10 magtape interface\"\n.xx \"tmscp\" \"DEC TMSCP magtape interface\"\n.xx \"ts\" \"TS-11 magtape interface\"\n.xx \"tty\" \"general terminal interface\"\n.xx \"tu\" \"VAX-11/730 and VAX-11/750 TU58 console cassette interface\"\n.xx \"uda\" \"UDA-50 disk controller interface\"\n.xx \"udp\" \"Internet User Datagram Protocol\"\n.xx \"up\" \"unibus storage module controller/drives\"\n.xx \"ut\" \"UNIBUS TU45 tri-density tape drive interface\"\n.xx \"uu\" \"TU58/DECtape II UNIBUS cassette interface\"\n.xx \"va\" \"Benson-Varian interface\"\n.xx \"vp\" \"Versatec interface\"\n.xx \"vv\" \"Proteon proNET 10 Megabit ring\"\n"
  },
  {
    "path": "share/man/man0/toc5",
    "content": ".xx \"L-devices\" \"UUCP device description file\"\n.xx \"L-dialcodes\" \"UUCP phone number index file\"\n.xx \"L.aliases\" \"UUCP hostname alias file\"\n.xx \"L.cmds\" \"UUCP remote command permissions file\"\n.xx \"L.sys\" \"UUCP remote host description file\"\n.xx \"USERFILE\" \"UUCP pathname permissions file\"\n.xx \"a.out\" \"assembler and link editor output\"\n.xx \"acct\" \"execution accounting file\"\n.xx \"aliases\" \"aliases file for sendmail\"\n.xx \"ar\" \"archive (library) file format\"\n.xx \"core\" \"format of memory image file\"\n.xx \"dbx\" \"dbx symbol table information\"\n.xx \"dir\" \"format of directories\"\n.xx \"disktab\" \"disk description file\"\n.xx \"dump\" \"incremental dump format\"\n.xx \"fs\" \"format of file system volume\"\n.xx \"fstab\" \"static information about the filesystems\"\n.xx \"gettytab\" \"terminal configuration data base\"\n.xx \"group\" \"group file\"\n.xx \"hosts\" \"host name data base\"\n.xx \"map3270\" \"database for mapping ascii keystrokes into IBM 3270 keys\"\n.xx \"mtab\" \"mounted file system table\"\n.xx \"networks\" \"network name data base\"\n.xx \"passwd\" \"password file\"\n.xx \"phones\" \"remote host phone number data base\"\n.xx \"plot\" \"graphics interface\"\n.xx \"printcap\" \"printer capability data base\"\n.xx \"protocols\" \"protocol name data base\"\n.xx \"remote\" \"remote host description file\"\n.xx \"resolver\" \"resolver configuration file\"\n.xx \"services\" \"service name data base\"\n.xx \"stab\" \"symbol table types\"\n.xx \"tar\" \"tape archive file format\"\n.xx \"termcap\" \"terminal capability data base\"\n.xx \"tp\" \"DEC/mag tape formats\"\n.xx \"ttys\" \"terminal initialization data\"\n.xx \"types\" \"primitive system data types\"\n.xx \"utmp\" \"login records\"\n.xx \"uuencode\" \"format of an encoded uuencode file\"\n.xx \"vfont\" \"font formats for the Benson-Varian or Versatec\"\n.xx \"vgrindefs\" \"vgrind's language definition data base\"\n"
  },
  {
    "path": "share/man/man0/toc6",
    "content": ".xx \"aardvark\" \"yet another exploration game\"\n.xx \"adventure\" \"an exploration game\"\n.xx \"arithmetic\" \"provide drill in number facts\"\n.xx \"backgammon\" \"the game\"\n.xx \"banner\" \"print large banner on printer\"\n.xx \"battlestar\" \"a tropical adventure game\"\n.xx \"bcd\" \"convert to antique media\"\n.xx \"boggle\" \"play the game of boggle\"\n.xx \"canfield\" \"the solitaire card game canfield\"\n.xx \"chess\" \"the game of chess\"\n.xx \"ching\" \"the book of changes and other cookies\"\n.xx \"cribbage\" \"the card game cribbage\"\n.xx \"doctor\" \"interact with a psychoanalyst\"\n.xx \"fish\" \"play ``Go Fish''\"\n.xx \"fortune\" \"print a random, hopefully interesting, adage\"\n.xx \"hangman\" \"Computer version of the game hangman\"\n.xx \"hunt\" \"a multi-player multi-terminal game\"\n.xx \"mille\" \"play Mille Bournes\"\n.xx \"monop\" \"Monopoly game\"\n.xx \"number\" \"convert Arabic numerals to English\"\n.xx \"quiz\" \"test your knowledge\"\n.xx \"rain\" \"animated raindrops display\"\n.xx \"robots\" \"fight off villainous robots\"\n.xx \"rogue\" \"Exploring The Dungeons of Doom\"\n.xx \"sail\" \"multi-user wooden ships and iron men\"\n.xx \"snake\" \"display chase game\"\n.xx \"trek\" \"trekkie game\"\n.xx \"worm\" \"Play the growing worm game\"\n.xx \"worms\" \"animate worms on a display terminal\"\n.xx \"wump\" \"the game of hunt-the-wumpus\"\n.xx \"zork\" \"the game of dungeon\"\n"
  },
  {
    "path": "share/man/man0/toc7",
    "content": ".xx \"intro\" \"miscellaneous useful information pages\"\n.xx \"ascii\" \"map of ASCII character set\"\n.xx \"environ\" \"user environment\"\n.xx \"eqnchar\" \"special character definitions for eqn\"\n.xx \"hier\" \"file system hierarchy\"\n.xx \"mailaddr\" \"mail addressing description\"\n.xx \"man\" \"macros to typeset manual\"\n.xx \"me\" \"macros for formatting papers\"\n.xx \"ms\" \"text formatting macros\"\n.xx \"term\" \"conventional names for terminals\"\n"
  },
  {
    "path": "share/man/man0/toc8",
    "content": ".xx \"intro\" \"introduction to system maintenance and operation commands\"\n.xx \"XNSrouted\" \"NS Routing Information Protocol daemon\"\n.xx \"ac\" \"login accounting\"\n.xx \"adduser\" \"procedure for adding new users\"\n.xx \"arff\" \"archiver and copier for floppy\"\n.xx \"arp\" \"address resolution display and control\"\n.xx \"bad144\" \"read/write dec standard 144 bad sector information\"\n.xx \"badsect\" \"create files to contain bad sectors\"\n.xx \"bugfiler\" \"file bug reports in folders automatically\"\n.xx \"catman\" \"create the cat files for the manual\"\n.xx \"chown\" \"change owner\"\n.xx \"clri\" \"clear i-node\"\n.xx \"comsat\" \"biff server\"\n.xx \"config\" \"build system configuration files\"\n.xx \"crash\" \"what happens when the system crashes\"\n.xx \"cron\" \"clock daemon\"\n.xx \"dcheck\" \"file system directory consistency check\"\n.xx \"diskpart\" \"calculate default disk partition sizes\"\n.xx \"dmesg\" \"collect system diagnostic messages to form error log\"\n.xx \"drtest\" \"standalone disk test program\"\n.xx \"dump\" \"incremental file system dump\"\n.xx \"dumpfs\" \"dump file system information\"\n.xx \"edquota\" \"edit user quotas\"\n.xx \"fastboot\" \"reboot/halt the system without checking the disks\"\n.xx \"fingerd\" \"remote user information server\"\n.xx \"format\" \"how to format disk packs\"\n.xx \"fsck\" \"file system consistency check and interactive repair\"\n.xx \"ftpd\" \"DARPA Internet File Transfer Protocol server\"\n.xx \"gettable\" \"get NIC format host tables from a host\"\n.xx \"getty\" \"set terminal mode\"\n.xx \"halt\" \"stop the processor\"\n.xx \"htable\" \"convert NIC standard format host tables\"\n.xx \"icheck\" \"file system storage consistency check\"\n.xx \"ifconfig\" \"configure network interface parameters\"\n.xx \"implog\" \"IMP log interpreter\"\n.xx \"implogd\" \"IMP logger process\"\n.xx \"inetd\" \"internet ``super\\-server''\"\n.xx \"init\" \"process control initialization\"\n.xx \"kgmon\" \"generate a dump of the operating system's profile buffers\"\n.xx \"lpc\" \"line printer control program\"\n.xx \"lpd\" \"line printer daemon\"\n.xx \"makedev\" \"make system special files\"\n.xx \"makekey\" \"generate encryption key\"\n.xx \"mkfs\" \"construct a file system\"\n.xx \"mkhosts\" \"generate hashed host table\"\n.xx \"mklost+found\" \"make a lost+found directory for fsck\"\n.xx \"mknod\" \"build special file\"\n.xx \"mkpasswd\" \"generate hashed password table\"\n.xx \"mkproto\" \"construct a prototype file system\"\n.xx \"mount\" \"mount and dismount file system\"\n.xx \"named\" \"Internet domain name server\"\n.xx \"ncheck\" \"generate names from i-numbers\"\n.xx \"newfs\" \"construct a new file system\"\n.xx \"pac\" \"printer/plotter accounting information\"\n.xx \"ping\" \"send ICMP ECHO_REQUEST packets to network hosts\"\n.xx \"pstat\" \"print system facts\"\n.xx \"quot\" \"summarize file system ownership\"\n.xx \"quotacheck\" \"file system quota consistency checker\"\n.xx \"quotaon\" \"turn file system quotas on and off\"\n.xx \"rc\" \"command script for auto-reboot and daemons\"\n.xx \"rdump\" \"file system dump across the network\"\n.xx \"reboot\" \"UNIX bootstrapping procedures\"\n.xx \"renice\" \"alter priority of running processes\"\n.xx \"repquota\" \"summarize quotas for a file system\"\n.xx \"restore\" \"incremental file system restore\"\n.xx \"rexecd\" \"remote execution server\"\n.xx \"rlogind\" \"remote login server\"\n.xx \"rmt\" \"remote magtape protocol module\"\n.xx \"route\" \"manually manipulate the routing tables\"\n.xx \"routed\" \"network routing daemon\"\n.xx \"rrestore\" \"restore a file system dump across the network\"\n.xx \"rshd\" \"remote shell server\"\n.xx \"rwhod\" \"system status server\"\n.xx \"rxformat\" \"format floppy disks\"\n.xx \"sa\" \"system accounting\"\n.xx \"savecore\" \"save a core dump of the operating system\"\n.xx \"sendmail\" \"send mail over the internet\"\n.xx \"shutdown\" \"close down the system at a given time\"\n.xx \"slattach\" \"attach serial lines as network interfaces\"\n.xx \"sticky\" \"persistent text and append-only directories\"\n.xx \"swapon\" \"specify additional device for paging and swapping\"\n.xx \"sync\" \"update the super block\"\n.xx \"syslogd\" \"log systems messages\"\n.xx \"talkd\" \"remote user communication server\"\n.xx \"telnetd\" \"DARPA TELNET protocol server\"\n.xx \"tftpd\" \"DARPA Trivial File Transfer Protocol server\"\n.xx \"timed\" \"time server daemon\"\n.xx \"timedc\" \"timed control program\"\n.xx \"trpt\" \"transliterate protocol trace\"\n.xx \"trsp\" \"transliterate sequenced packet protocol trace\"\n.xx \"tunefs\" \"tune up an existing file system\"\n.xx \"update\" \"periodically update the super block\"\n.xx \"uucico\" \"transfer files queued by uucp or uux\"\n.xx \"uuclean\" \"uucp spool directory clean-up\"\n.xx \"uupoll\" \"poll a remote UUCP site\"\n.xx \"uusnap\" \"show snapshot of the UUCP system\"\n.xx \"uuxqt\" \"UUCP execution file interpreter\"\n.xx \"vipw\" \"edit the password file\"\n"
  },
  {
    "path": "share/man/man0/tocrc",
    "content": "#!/bin/sh -\n#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n#\t@(#)tocrc\t6.2.1 (2.11BSD) 1996/10/25\n#\ntmp=/tmp/toc$$\ntrap \"rm $tmp ; exit\" 2 3 15\nif [ $# -eq 2 -a $1 = \"3\" ]\nthen\n\t: create toc input files for section 3 only\n\n\t(cd ../man3 ; /usr/libexec/getNAME -t `ls *.3 *.3[mnsxc] | sort` | sed \\\n\t\t\t-e 's/.s-2//g' \\\n\t\t\t-e 's/.s-1//g' \\\n\t\t\t-e 's/.s0//g' \\\n\t\t\t-e 's/.s+1//g' \\\n\t\t\t-e 's/  *.-  */: /' \\\n\t\t\t-e 's/ *$/./' \\\n\t\t\t-e 's/.TH.*\t//' \\\n\t\t> ../man0/tocx3 ;\n\t\t/usr/libexec/getNAME -t *.3f | sed \\\n\t\t\t-e 's/.s-2//g' \\\n\t\t\t-e 's/.s-1//g' \\\n\t\t\t-e 's/.s0//g' \\\n\t\t\t-e 's/.s+1//g' \\\n\t\t\t-e 's/  *.-  */: /' \\\n\t\t\t-e 's/ *$/./' \\\n\t\t\t-e 's/.TH.*\t//' \\\n\t\t> ../man0/tocx3f\n\t)\nelif [ $# -eq 2 ]\nthen\n\t: create toc input file for one section only\n\n\t( cd ../man$1 ; /usr/libexec/getNAME -t *.* |\n\t\tsed \\\n\t\t\t-e 's/.s-2//g' \\\n\t\t\t-e 's/.s-1//g' \\\n\t\t\t-e 's/.s0//g' \\\n\t\t\t-e 's/.s+1//g' \\\n\t\t\t-e 's/  *.-  */: /' \\\n\t\t\t-e 's/ *$/./' \\\n\t\t\t-e 's/.TH.*\t//' \\\n\t\t> ../man0/tocx$1\n\t)\nelse case $1 in\n\tall )\n\t\t:   tocx files for all sections and everything else\n\n\t\tfor x in 1 2 3 4 5 6 7 8\n\t\t\tdo\n\t\t\t./$0 $x $x\n\t\t\tdone\n\t\t./$0 t\n\t\t;;\n\tt )\n\t\t:   permuted index and toc files\n\n\t\tif [ ! -f tocx1 ]\n\t\tthen\n\t\t\techo \"tocx* files missing; must run tocrc all first\"\n\t\t\texit\n\t\tfi\n\t\tsed \\\n\t\t\t-e 's/(1c)/(1C)/' \\\n\t\t\t-e 's/(1g)/(1G)/' \\\n\t\t\t-e 's/(3c)/(3C)/' \\\n\t\t\t-e 's/(3m)/(3M)/' \\\n\t\t\t-e 's/(3n)/(3N)/' \\\n\t\t\t-e 's/(3s)/(3S)/' \\\n\t\t\t-e 's/(3x)/(3X)/' \\\n\t\t\t-e 's/(3f)/(3F)/' \\\n\t\t\t-e 's/(4f)/(4F)/' \\\n\t\t\t-e 's/(4n)/(4N)/' \\\n\t\t\t-e 's/(4p)/(4P)/' \\\n\t\t\t-e 's/(8c)/(8C)/' \\\n\t\t\t-e 's/(8v)/(8V)/' \\\n\t\t\t-e '/\"\\.\"/d' \\\n\t\t\ttocx* cshcmd \\\n\t\t> /tmp/cattoc\n\n\t\tptx -r -t -b break -f -w 108 -i ignore \\\n\t\t    /tmp/cattoc ptxx\n\n\t\tfor x in 1 2 3 3f 4 5 6 7 8\n\t\tdo\n\t\t\t< tocx$x grep '^intro' >$tmp\n\t\t\t\tsed \\\n\t\t\t\t-e '2,${' \\\n\t\t\t\t-e '/^intro/d' \\\n\t\t\t\t-e '}' \\\n\t\t\t\t-e 's/ .*://' \\\n\t\t\t\t-e 's/.$//' \\\n\t\t\t\t-e 's/([^)]*) /\" \"/' \\\n\t\t\t\t-e 's/.*/.xx \"&\"/' \\\n\t\t\t\t-e '/\"\"/d' \\\n\t\t\t\t$tmp tocx$x \\\n\t\t\t>toc$x\n\t\tdone\n\t\t;;\n\t* )\n\t\t./$0 $1 $1\n\t\t;;\n\tesac\nfi\nexit\n"
  },
  {
    "path": "share/man/man0/tocx1",
    "content": "adb(1) adb: debugger.\naddbib(1) addbib: create or extend bibliographic database.\napply(1) apply: apply a command to a set of arguments.\napropos(1) apropos: locate commands by keyword lookup.\nar(1) ar: archive and library maintainer.\nas(1) as: VAX-11 assembler.\nat(1) at: execute commands at a later time.\natq(1) atq: print the queue of jobs waiting to be run.\natrm(1) atrm: remove jobs spooled by at.\nawk(1) awk: pattern scanning and processing language.\nbasename(1) basename: strip filename affixes.\nbc(1) bc: arbitrary-precision arithmetic language.\nbib(1) bib, listrefs: bibliographic formatter; list bibliographic reference items.\nbiff(1) biff: be notified if mail arrives and who it is from.\nbinmail(1) binmail: send or receive mail among users.\ncal(1) cal: print calendar.\ncalendar(1) calendar: reminder service.\ncat(1) cat: catenate and print.\ncb(1) cb: C program beautifier.\ncc(1) cc: C compiler.\ncd(1) cd: change working directory.\nchecknr(1) checknr: check nroff/troff files.\nchfn(1) chfn, chsh, passwd: change password file information.\nchgrp(1) chgrp: change group.\nchmod(1) chmod: change mode.\nchsh(1) chfn, chsh, passwd: change password file information.\nclear(1) clear: clear terminal screen.\ncmp(1) cmp: compare two files.\ncol(1) col: filter reverse line feeds.\ncolcrt(1) colcrt: filter nroff output for CRT previewing.\ncolrm(1) colrm: remove columns from a file.\ncomm(1) comm: select or reject lines common to two sorted files.\ncompress(1) compress, uncompress, zcat: compress and expand data.\ncp(1) cp: copy.\ncrypt(1) crypt: encode/decode.\ncsh(1) csh: a shell (command interpreter) with C-like syntax.\nctags(1) ctags: create a tags file.\ndate(1) date: print and set the date.\ndbx(1) dbx: debugger.\ndc(1) dc: desk calculator.\ndd(1) dd: convert and copy a file.\nderoff(1) deroff: remove nroff, troff, tbl and eqn constructs.\ndf(1) df: disk free.\ndiction(1) diction, explain: print wordy sentences; thesaurus for diction.\ndiff(1) diff: differential file and directory comparator.\ndiff3(1) diff3: 3-way differential file comparison.\ndu(1) du: summarize disk usage.\necho(1) echo: echo arguments.\ned(1) ed: text editor.\nefl(1) efl: Extended Fortran Language.\neqn(1) eqn, neqn, checkeq: typeset mathematics.\nerror(1) error: analyze and disperse compiler error messages.\nex(1) ex, edit: text editor.\nexpand(1) expand, unexpand: expand tabs to spaces, and vice versa.\nexpr(1) expr: evaluate arguments as an expression.\nf77(1) f77: Fortran 77 compiler.\nfalse(1) false, true: provide truth values.\nfile(1) file: determine file type.\nfind(1) find: find files.\nfinger(1) finger: user information lookup program.\nfmt(1) fmt: simple text formatter.\nfold(1) fold: fold long lines for finite width output device.\nfp(1) fp: Functional Programming language compiler/interpreter.\nfpr(1) fpr: print Fortran file.\nfrom(1) from: who is my mail from?.\nfsplit(1) fsplit: split a multi-routine Fortran file into individual files.\nftp(1c) ftp: ARPANET file transfer program.\ngcore(1) gcore: get core images of running processes.\ngprof(1) gprof: display call graph profile data.\ngraph(1g) graph: draw a graph.\ngrep(1) grep, egrep, fgrep: search a file for a pattern.\ngroups(1) groups: show group memberships.\nhead(1) head: give first few lines.\nhostid(1) hostid: set or print identifier of current host system.\nhostname(1) hostname: set or print name of current host system.\nindent(1) indent: indent and format C program source.\ninstall(1) install: install binaries.\nintro(1) intro: introduction to commands.\niostat(1) iostat: report I/O statistics.\njoin(1) join: relational database operator.\njove(1) jove: an interactive display-oriented text editor.\nkill(1) kill: terminate a process with extreme prejudice.\nlast(1) last: indicate last logins of users and teletypes.\nlastcomm(1) lastcomm: show last commands executed in reverse order.\nld(1) ld: link editor.\nlearn(1) learn: computer aided instruction about UNIX.\nleave(1) leave: remind you when you have to leave.\nlex(1) lex: generator of lexical analysis programs.\nlint(1) lint: a C program verifier.\nlisp(1) lisp: lisp interpreter.\nliszt(1) liszt: compile a Franz Lisp program.\nln(1) ln: make links.\nlock(1) lock: reserve a terminal.\nlogger(1) logger: make entries in the system log.\nlogin(1) login: sign on.\nlook(1) look: find lines in a sorted list.\nlookbib(1) indxbib, lookbib: build inverted index for a bibliography, find references in a bibliography.\nlorder(1) lorder: find ordering relation for an object library.\nlpq(1) lpq: spool queue examination program.\nlpr(1) lpr: off line print.\nlprm(1) lprm: remove jobs from the line printer spooling queue.\nlptest(1) lptest: generate lineprinter ripple pattern.\nls(1) ls: list contents of directory.\nlxref(1) lxref: lisp cross reference program.\nm4(1) m4: macro processor.\nmail(1) mail: send and receive mail.\nmake(1) make: maintain program groups.\nman(1) man: find manual information by keywords; print out the manual.\nmesg(1) mesg: permit or deny messages.\nmh(1) mh: Message Handler.\nmkdir(1) mkdir: make a directory.\nmkstr(1) mkstr: create an error message file by massaging C source.\nmore(1) more, page: file perusal filter for crt viewing.\nmset(1) mset: retrieve ASCII to IBM 3270 keyboard map.\nmsgs(1) msgs: system messages and junk mail program.\nmt(1) mt: magnetic tape manipulating program.\nmv(1) mv: move or rename files.\nnetstat(1) netstat: show network status.\nnewaliases(1) newaliases: rebuild the data base for the mail aliases file.\nnice(1) nice, nohup: run a command at low priority (\\fIsh\\fR only).\nnm(1) nm: print name list.\nnotes(1) notes, autoseq, readnotes: a news system.\nnroff(1) nroff: text formatting.\nod(1) od: octal, decimal, hex, ascii dump.\npagesize(1) pagesize: print system page size.\npasswd(1) chfn, chsh, passwd: change password file information.\npatch(1) patch: a program for applying a diff file to an original.\npc(1) pc: Pascal compiler.\npdx(1) pdx: pascal debugger.\npi(1) pi: Pascal interpreter code translator.\npix(1) pix: Pascal interpreter and executor.\nplot(1g) plot: graphics filters.\npmerge(1) pmerge: pascal file merger.\npr(1) pr: print file.\nprintenv(1) printenv: print out the environment.\nprof(1) prof: display profile data.\nps(1) ps: process status.\nptx(1) ptx: permuted index.\npwd(1) pwd: working directory name.\npx(1) px: Pascal interpreter.\npxp(1) pxp: Pascal execution profiler.\npxref(1) pxref: Pascal cross-reference program.\nquota(1) quota: display disc usage and limits.\nranlib(1) ranlib: convert archives to random libraries.\nratfor(1) ratfor: rational Fortran dialect.\nrcp(1c) rcp: remote file copy.\nrcsintro(1) rcsintro: introduction to RCS commands.\nrdist(1) rdist: remote file distribution program.\nreadnews(1) readnews: read news articles.\nrefer(1) refer: find and insert literature references in documents.\nrev(1) rev: reverse lines of a file.\nrlogin(1c) rlogin: remote login.\nrm(1) rm, rmdir: remove (unlink) files or directories.\nrmail(1) rmail: handle remote mail received via uucp.\nrmdir(1) rmdir, rm: remove (unlink) directories or files.\nroffbib(1) roffbib: run off bibliographic database.\nrsh(1c) rsh: remote shell.\nruptime(1c) ruptime: show host status of local machines.\nrwho(1c) rwho: who's logged in on local machines.\nsccs(1) sccs: front end for the SCCS subsystem.\nscript(1) script: make typescript of terminal session.\nsed(1) sed: stream editor.\nsendbug(1) sendbug: mail a system bug report to 4bsd-bugs.\nsh(1) sh, for, case, if, while, \\fB:\\fP, \\fB.\\fP, break, continue, cd, eval, exec, exit, export, login, read, readonly, set, shift, times, trap, umask, wait: command language.\nsize(1) size: size of an object file.\nsleep(1) sleep: suspend execution for an interval.\nsoelim(1) soelim: eliminate \\&.so's from nroff input.\nsort(1) sort: sort or merge files.\nsortbib(1) sortbib: sort bibliographic database.\nspell(1) spell, spellin, spellout: find spelling errors.\nspline(1g) spline: interpolate smooth curve.\nsplit(1) split: split a file into pieces.\nstrings(1) strings: find the printable strings in a object, or other binary, file.\nstrip(1) strip: remove symbols and relocation bits.\nstruct(1) struct: structure Fortran programs.\nstty(1) stty: set terminal options.\nstyle(1) style: analyze surface characteristics of a document.\nsu(1) su: substitute user id temporarily.\nsum(1) sum: sum and count blocks in a file.\nsymorder(1) symorder: rearrange name list.\nsysline(1) sysline: display system status on status line of a terminal.\nsystat(1) systat: display system statistics on a crt.\ntabs(1) tabs: set terminal tabs.\ntail(1) tail: deliver the last part of a file.\ntalk(1) talk: talk to another user.\ntar(1) tar: tape archiver.\ntbl(1) tbl: format tables for nroff or troff.\ntc(1) tc: photoypesetter simulator.\ntcopy(1) tcopy: copy a mag tape.\ntee(1) tee: pipe fitting.\ntelnet(1c) telnet: user interface to the TELNET protocol.\ntest(1) test: condition command.\ntftp(1c) tftp: trivial file transfer program.\ntime(1) time: time a command.\ntip(1c) tip, cu: connect to a remote system.\ntk(1) tk: paginator for the Tektronix 4014.\ntn3270(1) tn3270: full-screen remote login to IBM VM/CMS.\ntouch(1) touch: update date last modified of a file.\ntp(1) tp: manipulate tape archive.\ntr(1) tr: translate characters.\ntroff(1) troff, nroff: text formatting and typesetting.\ntrue(1) true, false: provide truth values.\ntset(1) tset: terminal dependent initialization.\ntsort(1) tsort: topological sort.\ntty(1) tty: get terminal name.\nul(1) ul: do underlining.\nunifdef(1) unifdef: remove ifdef'ed lines.\nuniq(1) uniq: report repeated lines in a file.\nunits(1) units: conversion program.\nuptime(1) uptime: show how long system has been up.\nusers(1) users: compact list of users who are on the system.\nuucp(1c) uucp: unix to unix copy.\nuuencode(1c) uuencode, uudecode: encode/decode a binary file for transmission via mail.\nuulog(1c) uulog: display UUCP log files.\nuuname(1c) uuname: list names of UUCP hosts.\nuuq(1c) uuq: examine or manipulate the uucp queue.\nuusend(1c) uusend: send a file to a remote host.\nuux(1c) uux: unix to unix command execution.\nvacation(1) vacation: return ``I am on vacation'' indication.\nvgrind(1) vgrind: grind nice listings of programs.\nvi(1) vi: screen oriented (visual) display editor based on ex.\nvlp(1) vlp: Format Lisp programs to be printed with nroff, vtroff, or troff.\nvmstat(1) vmstat: report virtual memory statistics.\nvnews(1) vnews: read news articles.\nvwidth(1) vwidth: make troff width table for a font.\nw(1) w: who is on and what they are doing.\nwait(1) wait: await completion of process.\nwall(1) wall: write to all users.\nwc(1) wc: word count.\nwhat(1) what: show what versions of object modules were used to construct a file.\nwhatis(1) whatis: describe what a command is.\nwhereis(1) whereis: locate source, binary, and or manual for program.\nwhich(1) which: locate a program file including aliases and paths (\\fIcsh\\fR only).\nwho(1) who: who is on the system.\nwhoami(1) whoami: print effective current user id.\nwhois(1) whois: DARPA Internet user name directory service.\nwindow(1) window: window environment.\nwrite(1) write: write to another user.\nxsend(1) xsend, xget, enroll: secret mail.\nxstr(1) xstr: extract strings from C programs to implement shared strings.\nyacc(1) yacc: yet another compiler-compiler.\nyes(1) yes: be repetitively affirmative.\n"
  },
  {
    "path": "share/man/man0/tocx2",
    "content": "accept(2) accept: accept a connection on a socket.\naccess(2) access: determine accessibility of file.\nacct(2) acct: turn accounting on or off.\nadjtime(2) adjtime: correct the time to allow synchronization of the system clock.\nbind(2) bind: bind a name to a socket.\nbrk(2) brk, sbrk: change data segment size.\nchdir(2) chdir: change current working directory.\nchmod(2) chmod: change mode of file.\nchown(2) chown: change owner and group of a file.\nchroot(2) chroot: change root directory.\nclose(2) close: delete a descriptor.\nconnect(2) connect: initiate a connection on a socket.\ncreat(2) creat: create a new file.\ndup(2) dup, dup2: duplicate a descriptor.\nexecve(2) execve: execute a file.\nexit(2) _exit: terminate a process.\nfcntl(2) fcntl: file control.\nflock(2) flock: apply or remove an advisory lock on an open file.\nfork(2) fork: create a new process.\nfsync(2) fsync: synchronize a file's in-core state with that on disk.\ngetdtablesize(2) getdtablesize: get descriptor table size.\ngetgid(2) getgid, getegid: get group identity.\ngetgroups(2) getgroups: get group access list.\ngethostid(2) gethostid, sethostid: get/set unique identifier of current host.\ngethostname(2) gethostname, sethostname: get/set name of current host.\ngetitimer(2) getitimer, setitimer: get/set value of interval timer.\ngetpagesize(2) getpagesize: get system page size.\ngetpeername(2) getpeername: get name of connected peer.\ngetpgrp(2) getpgrp: get process group.\ngetpid(2) getpid, getppid: get process identification.\ngetpriority(2) getpriority, setpriority: get/set program scheduling priority.\ngetrlimit(2) getrlimit, setrlimit: control maximum system resource consumption.\ngetrusage(2) getrusage: get information about resource utilization.\ngetsockname(2) getsockname: get socket name.\ngetsockopt(2) getsockopt, setsockopt: get and set options on sockets.\ngettimeofday(2) gettimeofday, settimeofday: get/set date and time.\ngetuid(2) getuid, geteuid: get user identity.\nintro(2) intro: introduction to system calls and error numbers.\nioctl(2) ioctl: control device.\nkill(2) kill: send signal to a process.\nkillpg(2) killpg: send signal to a process group.\nlink(2) link: make a hard link to a file.\nlisten(2) listen: listen for connections on a socket.\nlseek(2) lseek: move read/write pointer.\nmkdir(2) mkdir: make a directory file.\nmknod(2) mknod: make a special file.\nmount(2) mount, umount: mount or remove file system.\nopen(2) open: open a file for reading or writing, or create a new file.\npipe(2) pipe: create an interprocess communication channel.\nprofil(2) profil: execution time profile.\nptrace(2) ptrace: process trace.\nquota(2) quota: manipulate disk quotas.\nread(2) read, readv: read input.\nreadlink(2) readlink: read value of a symbolic link.\nreboot(2) reboot: reboot system or halt processor.\nrecv(2) recv, recvfrom, recvmsg: receive a message from a socket.\nrename(2) rename: change the name of a file.\nrmdir(2) rmdir: remove a directory file.\nselect(2) select: synchronous I/O multiplexing.\nsend(2) send, sendto, sendmsg: send a message from a socket.\nsetgroups(2) setgroups: set group access list.\nsetpgrp(2) setpgrp: set process group.\nsetquota(2) setquota: enable/disable quotas on a file system.\nsetregid(2) setregid: set real and effective group ID.\nsetreuid(2) setreuid: set real and effective user ID's.\nshutdown(2) shutdown: shut down part of a full-duplex connection.\nsigblock(2) sigblock: block signals.\nsigpause(2) sigpause: atomically release blocked signals and wait for interrupt.\nsigreturn(2) sigreturn: return from signal.\nsigsetmask(2) sigsetmask: set current signal mask.\nsigstack(2) sigstack: set and/or get signal stack context.\nsigvec(2) sigvec: software signal facilities.\nsocket(2) socket: create an endpoint for communication.\nsocketpair(2) socketpair: create a pair of connected sockets.\nstat(2) stat, lstat, fstat: get file status.\nswapon(2) swapon: add a swap device for interleaved paging/swapping.\nsymlink(2) symlink: make symbolic link to a file.\nsync(2) sync: update super-block.\nsyscall(2) syscall: indirect system call.\ntruncate(2) truncate: truncate a file to a specified length.\numask(2) umask: set file creation mode mask.\nunlink(2) unlink: remove directory entry.\nutimes(2) utimes: set file times.\nvfork(2) vfork: spawn new process in a virtual memory efficient way.\nvhangup(2) vhangup: virtually ``hangup'' the current control terminal.\nwait(2) wait, wait3: wait for process to terminate.\nwrite(2) write, writev: write output.\n"
  },
  {
    "path": "share/man/man0/tocx3",
    "content": "abort(3) abort: generate a fault.\nabs(3) abs: integer absolute value.\nalarm(3c) alarm: schedule signal after specified time.\nasinh(3m) asinh, acosh, atanh: inverse hyperbolic functions.\nassert(3) assert: program verification.\natof(3) atof, atoi, atol: convert ASCII to numbers.\nbstring(3) bcopy, bcmp, bzero, ffs: bit and byte string operations.\nbyteorder(3n) htonl, htons, ntohl, ntohs: convert values between host and network byte order.\ncrypt(3) crypt, setkey, encrypt: DES encryption.\nctime(3) ctime, localtime, gmtime, asctime, timezone: convert date and time to ASCII.\nctype(3) isalpha, isupper, islower, isdigit, isxdigit, isalnum, isspace, ispunct, isprint, isgraph, iscntrl, isascii, toupper, tolower, toascii: character classification macros.\ncurses(3x) curses: screen functions with ``optimal'' cursor motion.\ndbm(3x) dbminit, fetch, store, delete, firstkey, nextkey: data base subroutines.\ndirectory(3) opendir, readdir, telldir, seekdir, rewinddir, closedir: directory operations.\necvt(3) ecvt, fcvt, gcvt: output conversion.\nend(3) end, etext, edata: last locations in program.\nerf(3m) erf, erfc: error functions.\nexecl(3) execl, execv, execle, execlp, execvp, exec, execve, exect, environ: execute a file.\nexit(3) exit: terminate a process after flushing any pending output.\nexp(3m) exp, expm1, log, log10, log1p, pow: exponential, logarithm, power.\nfclose(3s) fclose, fflush: close or flush a stream.\nferror(3s) ferror, feof, clearerr, fileno: stream status inquiries.\nfloor(3m) fabs, floor, ceil, rint: absolute value, floor, ceiling, and round-to-nearest functions.\nfopen(3s) fopen, freopen, fdopen: open a stream.\nfread(3s) fread, fwrite: buffered binary input/output.\nfrexp(3) frexp, ldexp, modf: split into mantissa and exponent.\nfseek(3s) fseek, ftell, rewind: reposition a stream.\ngetc(3s) getc, getchar, fgetc, getw: get character or word from stream.\ngetdisk(3) getdiskbyname: get disk description by its name.\ngetenv(3) getenv: value for environment name.\ngetfsent(3) getfsent, getfsspec, getfsfile, getfstype, setfsent, endfsent: get file system descriptor file entry.\ngetgrent(3) getgrent, getgrgid, getgrnam, setgrent, endgrent: get group file entry.\ngethostbyname(3n) gethostbyname, gethostbyaddr, gethostent, sethostent, endhostent: get network host entry.\ngetlogin(3) getlogin: get login name.\ngetnetent(3n) getnetent, getnetbyaddr, getnetbyname, setnetent, endnetent: get network entry.\ngetopt(3) getopt: get option letter from argv.\ngetpass(3) getpass: read a password.\ngetprotoent(3n) getprotoent, getprotobynumber, getprotobyname, setprotoent, endprotoent: get protocol entry.\ngetpw(3c) getpw: get name from uid.\ngetpwent(3) getpwent, getpwuid, getpwnam, setpwent, endpwent, setpwfile: get password file entry.\ngets(3s) gets, fgets: get a string from a stream.\ngetservent(3n) getservent, getservbyport, getservbyname, setservent, endservent: get service entry.\ngetttyent(3) getttyent, getttynam, setttyent, endttyent: get ttys file entry.\ngetusershell(3) getusershell, setusershell, endusershell: get legal user shells.\ngetwd(3) getwd: get current working directory pathname.\nhypot(3m) hypot, cabs: Euclidean distance, complex absolute value.\nieee(3m) copysign, drem, finite, logb, scalb: copysign, remainder, exponent manipulations.\ninet(3n) inet_addr, inet_network, inet_ntoa, inet_makeaddr, inet_lnaof, inet_netof: Internet address manipulation routines.\ninfnan(3m) infnan: signals invalid floating-point operations on a VAX (temporary).\ninitgroups(3) initgroups: initialize group access list.\ninsque(3) insque, remque: insert/remove element from a queue.\nintro(3) intro: introduction to C library functions.\nj0(3m) j0, j1, jn, y0, y1, yn: bessel functions.\nlgamma(3m) lgamma: log gamma function.\nlib2648(3x) lib2648: subroutines for the HP 2648 graphics terminal.\nmalloc(3) malloc, free, realloc, calloc, alloca: memory allocator.\nmath(3m) math: introduction to mathematical library functions.\nmktemp(3) mktemp: make a unique file name.\nmonitor(3) monitor, monstartup, moncontrol: prepare execution profile.\nmp(3x) madd, msub, mult, mdiv, pow, gcd, invert, rpow, msqrt, mcmp, move, min, omin, fmin, m_in, mout, omout, fmout, m_out, sdiv, itom: multiple precision integer arithmetic.\nndbm(3) dbm_open, dbm_close, dbm_fetch, dbm_store, dbm_delete, dbm_firstkey, dbm_nextkey, dbm_error, dbm_clearerr: data base subroutines.\nnice(3c) nice: set program priority.\nnlist(3) nlist: get entries from name list.\nns(3n) ns_addr, ns_ntoa: Xerox NS(tm)  address conversion routines.\npause(3c) pause: stop until signal.\nperror(3) perror, sys_errlist, sys_nerr: system error messages.\nplot(3x) plot: openpl, erase, label, line, circle, arc, move, cont, point, linemod, space, closepl: graphics interface.\npopen(3) popen, pclose: initiate I/O to/from a process.\nprintf(3s) printf, fprintf, sprintf: formatted output conversion.\npsignal(3) psignal, sys_siglist: system signal messages.\nputc(3s) putc, putchar, fputc, putw: put character or word on a stream.\nputs(3s) puts, fputs: put a string on a stream.\nqsort(3) qsort: quicker sort.\nrand(3c) rand, srand: random number generator.\nrandom(3) random, srandom, initstate, setstate: better random number generator; routines for changing generators.\nrcmd(3) rcmd, rresvport, ruserok: routines for returning a stream to a remote command.\nregex(3) re_comp, re_exec: regular expression handler.\nresolver(3) res_mkquery, res_send, res_init, dn_comp, dn_expand: resolver routines.\nrexec(3) rexec: return stream to a remote command.\nscandir(3) scandir, alphasort: scan a directory.\nscanf(3s) scanf, fscanf, sscanf: formatted input conversion.\nsetbuf(3s) setbuf, setbuffer, setlinebuf: assign buffering to a stream.\nsetjmp(3) setjmp, longjmp: non-local goto.\nsetuid(3) setuid, seteuid, setruid, setgid, setegid, setrgid: set user and group ID.\nsiginterrupt(3) siginterrupt: allow signals to interrupt system calls.\nsignal(3c) signal: simplified software signal facilities.\nsin(3m) sin, cos, tan, asin, acos, atan, atan2: trigonometric functions and their inverses.\nsinh(3m) sinh, cosh, tanh: hyperbolic functions.\nsleep(3) sleep: suspend execution for interval.\nsqrt(3m) cbrt, sqrt: cube root, square root.\nstdio(3s) stdio: standard buffered input/output package.\nstring(3) strcat, strncat, strcmp, strncmp, strcpy, strncpy, strlen, index, rindex: string operations.\nstty(3c) stty, gtty: set and get terminal state (defunct).\nswab(3) swab: swap bytes.\nsyslog(3) syslog, openlog, closelog, setlogmask: control system log.\nsystem(3) system: issue a shell command.\ntermcap(3x) tgetent, tgetnum, tgetflag, tgetstr, tgoto, tputs: terminal independent operation routines.\ntime(3c) time, ftime: get date and time.\ntimes(3c) times: get process times.\nttyname(3) ttyname, isatty, ttyslot: find name of a terminal.\nualarm(3) ualarm: schedule signal after specified time.\nungetc(3s) ungetc: push character back into input stream.\nusleep(3) usleep: suspend execution for interval.\nutime(3c) utime: set file times.\nvalloc(3c) valloc: aligned memory allocator.\nvarargs(3) varargs: variable argument list.\nvlimit(3c) vlimit: control maximum system resource consumption.\nvtimes(3c) vtimes: get information about resource utilization.\n"
  },
  {
    "path": "share/man/man0/tocx3f",
    "content": "abort(3f) abort: abnormal termination.\naccess(3f) access: determine accessability of a file.\nalarm(3f) alarm: execute a subroutine after a specified time.\nbessel(3f) bessel functions: of two kinds for integer orders.\nbit(3f) bit: and, or, xor, not, rshift, lshift bitwise functions.\nchdir(3f) chdir: change default directory.\nchmod(3f) chmod: change mode of a file.\netime(3f) etime, dtime: return elapsed execution time.\nexit(3f) exit: terminate process with status.\nfdate(3f) fdate: return date and time in an ASCII string.\nflmin(3f) flmin, flmax, ffrac, dflmin, dflmax, dffrac, inmax: return extreme values.\nflush(3f) flush: flush output to a logical unit.\nfork(3f) fork: create a copy of this process.\nfseek(3f) fseek, ftell: reposition a file on a logical unit.\ngetarg(3f) getarg, iargc: return command line arguments.\ngetc(3f) getc, fgetc: get a character from a logical unit.\ngetcwd(3f) getcwd: get pathname of current working directory.\ngetenv(3f) getenv: get value of environment variables.\ngetlog(3f) getlog: get user's login name.\ngetpid(3f) getpid: get process id.\ngetuid(3f) getuid, getgid: get user or group ID of the caller.\nhostnm(3f) hostnm: get name of current host.\nidate(3f) idate, itime: return date or time in numerical form.\nindex(3f) index, rindex, lnblnk, len: tell about character objects.\nintro(3f) intro: introduction to FORTRAN library functions.\nioinit(3f) ioinit: change f77 I/O initialization.\nkill(3f) kill: send a signal to a process.\nlink(3f) link: make a link to an existing file.\nloc(3f) loc: return the address of an object.\nlong(3f) long, short: integer object conversion.\nmalloc(3f) malloc, free, falloc: memory allocator.\nperror(3f) perror, gerror, ierrno: get system error messages.\nplot(3f) plot: openpl et al.: f77 library interface to \\fIplot\\fR (3X) libraries..\nputc(3f) putc, fputc: write a character to a fortran logical unit.\nqsort(3f) qsort: quick sort.\nrand(3f) rand, drand, irand: return random values.\nrandom(3f) random, drandm, irandm: better random number generator.\nrename(3f) rename: rename a file.\nsignal(3f) signal: change the action for a signal.\nsleep(3f) sleep: suspend execution for an interval.\nstat(3f) stat, lstat, fstat: get file status.\nsystem(3f) system: execute a UNIX command.\ntime(3f) time, ctime, ltime, gmtime: return system time.\ntopen(3f) topen, tclose, tread, twrite, trewin, tskipf, tstate: f77 tape I/O.\ntraper(3f) traper: trap arithmetic errors.\ntrapov(3f) trapov: trap and repair floating point overflow.\ntrpfpe(3f) trpfpe, fpecnt: trap and repair floating point faults.\nttynam(3f) ttynam, isatty: find name of a terminal port.\nunlink(3f) unlink: remove a directory entry.\nwait(3f) wait: wait for a process to terminate.\n"
  },
  {
    "path": "share/man/man0/tocx4",
    "content": "acc(4) acc: ACC LH/DH IMP interface.\nad(4) ad: Data Translation A/D converter.\narp(4p) arp: Address Resolution Protocol.\nautoconf(4) autoconf: diagnostics from the autoconfiguration code.\nbk(4) bk: line discipline for machine-machine communication (obsolete).\ncons(4) cons: VAX-11 console interface.\ncrl(4) crl: VAX 8600 console RL02 interface.\ncss(4) css: DEC IMP-11A LH/DH IMP interface.\nct(4) ct: phototypesetter interface.\nddn(4) ddn: DDN Standard Mode X.25 IMP interface.\nde(4) de: DEC DEUNA 10 Mb/s Ethernet interface.\ndh(4) dh: DH-11/DM-11 communications multiplexer.\ndhu(4) dhu: DHU-11 communications multiplexer.\ndmc(4) dmc: DEC DMC-11/DMR-11 point-to-point communications device.\ndmf(4) dmf: DMF-32, terminal multiplexor.\ndmz(4) dmz: DMZ-32 terminal multiplexor.\ndn(4) dn: DN-11 autocall unit interface.\ndrum(4) drum: paging device.\ndz(4) dz: DZ-11 communications multiplexer.\nec(4) ec: 3Com 10 Mb/s Ethernet interface.\nen(4) en: Xerox 3 Mb/s Ethernet interface.\nex(4) ex: Excelan 10 Mb/s Ethernet interface.\nfl(4) fl: console floppy interface.\nhdh(4) hdh: ACC IF-11/HDH IMP interface.\nhk(4) hk: RK6-11/RK06 and RK07 moving head disk.\nhp(4) hp: MASSBUS disk interface.\nht(4) ht: TM-03/TE-16,TU-45,TU-77 MASSBUS magtape interface.\nhy(4) hy: Network Systems Hyperchannel interface.\nicmp(4p) icmp: Internet Control Message Protocol.\nidp(4p) idp: Xerox Internet Datagram Protocol.\nik(4) ik: Ikonas frame buffer, graphics device interface.\nil(4) il: Interlan NI1010 10 Mb/s Ethernet interface.\nimp(4) imp: 1822 network interface.\nimp(4p) imp: IMP raw socket interface.\ninet(4f) inet: Internet protocol family.\nintro(4) intro: introduction to special files and hardware support.\nintro(4n) networking: introduction to networking facilities.\nip(4p) ip: Internet Protocol.\nix(4) ix: Interlan Np100 10 Mb/s Ethernet interface.\nkg(4) kg: KL-11/DL-11W line clock.\nlo(4) lo: software loopback network interface.\nlp(4) lp: line printer.\nmem(4) mem, kmem: main memory.\nmt(4) mt: TM78/TU-78 MASSBUS magtape interface.\nmtio(4) mtio: UNIX magtape interface.\nnp(4) np: Interlan Np100 10 Mb/s Ethernet interface.\nns(4f) ns: Xerox Network Systems(tm) protocol family.\nnsip(4) nsip: software network interface encapsulating ns packets in ip packets..\nnull(4) null: data sink.\npcl(4) pcl: DEC CSS PCL-11 B Network Interface.\nps(4) ps: Evans and Sutherland Picture System 2 graphics device interface.\npty(4) pty: pseudo terminal driver.\nqe(4) qe: DEC DEQNA Q-bus 10 Mb/s Ethernet interface.\nrx(4) rx: DEC RX02 floppy disk interface.\nspp(4p) spp: Xerox Sequenced Packet Protocol.\ntb(4) tb: line discipline for digitizing devices.\ntcp(4p) tcp: Internet Transmission Control Protocol.\ntm(4) tm: TM-11/TE-10 magtape interface.\ntmscp(4) tmscp: DEC TMSCP magtape interface.\nts(4) ts: TS-11 magtape interface.\ntty(4) tty: general terminal interface.\ntu(4) tu: VAX-11/730 and VAX-11/750 TU58 console cassette interface.\nuda(4) uda: UDA-50 disk controller interface.\nudp(4p) udp: Internet User Datagram Protocol.\nup(4) up: unibus storage module controller/drives.\nut(4) ut: UNIBUS TU45 tri-density tape drive interface.\nuu(4) uu: TU58/DECtape II UNIBUS cassette interface.\nva(4) va: Benson-Varian interface.\nvp(4) vp: Versatec interface.\nvv(4) vv: Proteon proNET 10 Megabit ring.\n"
  },
  {
    "path": "share/man/man0/tocx5",
    "content": "L-devices(5) L-devices: UUCP device description file.\nL-dialcodes(5) L-dialcodes: UUCP phone number index file.\nL.aliases(5) L.aliases: UUCP hostname alias file.\nL.cmds(5) L.cmds: UUCP remote command permissions file.\nL.sys(5) L.sys: UUCP remote host description file.\nUSERFILE(5) USERFILE: UUCP pathname permissions file.\na.out(5) a.out: assembler and link editor output.\nacct(5) acct: execution accounting file.\naliases(5) aliases: aliases file for sendmail.\nar(5) ar: archive (library) file format.\ncore(5) core: format of memory image file.\ndbx(5) dbx: dbx symbol table information.\ndir(5) dir: format of directories.\ndisktab(5) disktab: disk description file.\ndump(5) dump, dumpdates: incremental dump format.\nfs(5) fs, inode: format of file system volume.\nfstab(5) fstab: static information about the filesystems.\ngettytab(5) gettytab: terminal configuration data base.\ngroup(5) group: group file.\nhosts(5) hosts: host name data base.\nmap3270(5) map3270: database for mapping ascii keystrokes into IBM 3270 keys.\nmtab(5) mtab: mounted file system table.\nnetworks(5) networks: network name data base.\npasswd(5) passwd: password file.\nphones(5) phones: remote host phone number data base.\nplot(5) plot: graphics interface.\nprintcap(5) printcap: printer capability data base.\nprotocols(5) protocols: protocol name data base.\nremote(5) remote: remote host description file.\nresolver(5) resolver configuration file.\nservices(5) services: service name data base.\nstab(5) stab: symbol table types.\ntar(5) tar: tape archive file format.\ntermcap(5) termcap: terminal capability data base.\ntp(5) tp: DEC/mag tape formats.\nttys(5) ttys: terminal initialization data.\ntypes(5) types: primitive system data types.\nutmp(5) utmp, wtmp: login records.\nuuencode(5) uuencode: format of an encoded uuencode file.\nvfont(5) vfont: font formats for the Benson-Varian or Versatec.\nvgrindefs(5) vgrindefs: vgrind's language definition data base.\n"
  },
  {
    "path": "share/man/man0/tocx6",
    "content": "aardvark(6) aardvark: yet another exploration game.\nadventure(6) adventure: an exploration game.\narithmetic(6) arithmetic: provide drill in number facts.\nbackgammon(6) backgammon: the game.\nbanner(6) banner: print large banner on printer.\nbattlestar(6) battlestar: a tropical adventure game.\nbcd(6) bcd: convert to antique media.\nboggle(6) boggle: play the game of boggle.\ncanfield(6) canfield, cfscores: the solitaire card game canfield.\nchess(6) chess: the game of chess.\nching(6) ching: the book of changes and other cookies.\ncribbage(6) cribbage: the card game cribbage.\ndoctor(6) doctor: interact with a psychoanalyst.\nfish(6) fish: play ``Go Fish''.\nfortune(6) fortune: print a random, hopefully interesting, adage.\nhangman(6) hangman: Computer version of the game hangman.\nhunt(6) hunt: a multi-player multi-terminal game.\nmille(6) mille: play Mille Bournes.\nmonop(6) monop: Monopoly game.\nnumber(6) number: convert Arabic numerals to English.\nquiz(6) quiz: test your knowledge.\nrain(6) rain: animated raindrops display.\nrobots(6) robots: fight off villainous robots.\nrogue(6) rogue: Exploring The Dungeons of Doom.\nsail(6) sail: multi-user wooden ships and iron men.\nsnake(6) snake, snscore: display chase game.\ntrek(6) trek: trekkie game.\nworm(6) worm: Play the growing worm game.\nworms(6) worms: animate worms on a display terminal.\nwump(6) wump: the game of hunt-the-wumpus.\nzork(6) zork: the game of dungeon.\n"
  },
  {
    "path": "share/man/man0/tocx7",
    "content": "ascii(7) ascii: map of ASCII character set.\nenviron(7) environ: user environment.\neqnchar(7) eqnchar: special character definitions for eqn.\nhier(7) hier: file system hierarchy.\nintro(7) miscellaneous: miscellaneous useful information pages.\nmailaddr(7) mailaddr: mail addressing description.\nman(7) man: macros to typeset manual.\nme(7) me: macros for formatting papers.\nms(7) ms: text formatting macros.\nterm(7) term: conventional names for terminals.\n"
  },
  {
    "path": "share/man/man0/tocx8",
    "content": "XNSrouted(8c) XNSrouted: NS Routing Information Protocol daemon.\nac(8) ac: login accounting.\nadduser(8) adduser: procedure for adding new users.\narff(8v) arff, flcopy: archiver and copier for floppy.\narp(8c) arp: address resolution display and control.\nbad144(8) bad144: read/write dec standard 144 bad sector information.\nbadsect(8) badsect: create files to contain bad sectors.\nbugfiler(8) bugfiler: file bug reports in folders automatically.\ncatman(8) catman: create the cat files for the manual.\nchown(8) chown: change owner.\nclri(8) clri: clear i-node.\ncomsat(8c) comsat: biff server.\nconfig(8) config: build system configuration files.\ncrash(8v) crash: what happens when the system crashes.\ncron(8) cron: clock daemon.\ndcheck(8) dcheck: file system directory consistency check.\ndiskpart(8) diskpart: calculate default disk partition sizes.\ndmesg(8) dmesg: collect system diagnostic messages to form error log.\ndrtest(8) drtest: standalone disk test program.\ndump(8) dump: incremental file system dump.\ndumpfs(8) dumpfs: dump file system information.\nedquota(8) edquota: edit user quotas.\nfastboot(8) fastboot, fasthalt: reboot/halt the system without checking the disks.\nfingerd(8c) fingerd: remote user information server.\nformat(8v) format: how to format disk packs.\nfsck(8) fsck: file system consistency check and interactive repair.\nftpd(8c) ftpd: DARPA Internet File Transfer Protocol server.\ngettable(8c) gettable: get NIC format host tables from a host.\ngetty(8) getty: set terminal mode.\nhalt(8) halt: stop the processor.\nhtable(8) htable: convert NIC standard format host tables.\nicheck(8) icheck: file system storage consistency check.\nifconfig(8c) ifconfig: configure network interface parameters.\nimplog(8c) implog: IMP log interpreter.\nimplogd(8c) implogd: IMP logger process.\ninetd(8) inetd: internet ``super\\-server''.\ninit(8) init: process control initialization.\nintro(8) intro: introduction to system maintenance and operation commands.\nkgmon(8) kgmon: generate a dump of the operating system's profile buffers.\nlpc(8) lpc: line printer control program.\nlpd(8) lpd: line printer daemon.\nmakedev(8) makedev: make system special files.\nmakekey(8) makekey: generate encryption key.\nmkfs(8) mkfs: construct a file system.\nmkhosts(8) mkhosts: generate hashed host table.\nmklost+found(8) mklost+found: make a lost+found directory for fsck.\nmknod(8) mknod: build special file.\nmkpasswd(8) mkpasswd: generate hashed password table.\nmkproto(8) mkproto: construct a prototype file system.\nmount(8) mount, umount: mount and dismount file system.\nnamed(8) named: Internet domain name server.\nncheck(8) ncheck: generate names from i-numbers.\nnewfs(8) newfs: construct a new file system.\npac(8) pac: printer/plotter accounting information.\nping(8) ping: send ICMP ECHO_REQUEST packets to network hosts.\npstat(8) pstat: print system facts.\nquot(8) quot: summarize file system ownership.\nquotacheck(8) quotacheck: file system quota consistency checker.\nquotaon(8) quotaon, quotaoff: turn file system quotas on and off.\nrc(8) rc: command script for auto-reboot and daemons.\nrdump(8c) rdump: file system dump across the network.\nreboot(8) reboot: UNIX bootstrapping procedures.\nrenice(8) renice: alter priority of running processes.\nrepquota(8) repquota: summarize quotas for a file system.\nrestore(8) restore: incremental file system restore.\nrexecd(8c) rexecd: remote execution server.\nrlogind(8c) rlogind: remote login server.\nrmt(8c) rmt: remote magtape protocol module.\nroute(8c) route: manually manipulate the routing tables.\nrouted(8c) routed: network routing daemon.\nrrestore(8c) rrestore: restore a file system dump across the network.\nrshd(8c) rshd: remote shell server.\nrwhod(8c) rwhod: system status server.\nrxformat(8v) rxformat: format floppy disks.\nsa(8) sa, accton: system accounting.\nsavecore(8) savecore: save a core dump of the operating system.\nsendmail(8) sendmail: send mail over the internet.\nshutdown(8) shutdown: close down the system at a given time.\nslattach(8c) slattach: attach serial lines as network interfaces.\nsticky(8) sticky: persistent text and append-only directories.\nswapon(8) swapon: specify additional device for paging and swapping.\nsync(8) sync: update the super block.\nsyslogd(8) syslogd: log systems messages.\ntalkd(8c) talkd: remote user communication server.\ntelnetd(8c) telnetd: DARPA TELNET protocol server.\ntftpd(8c) tftpd: DARPA Trivial File Transfer Protocol server.\ntimed(8) timed: time server daemon.\ntimedc(8) timedc: timed control program.\ntrpt(8c) trpt: transliterate protocol trace.\ntrsp(8c) trsp: transliterate sequenced packet protocol trace.\ntunefs(8) tunefs: tune up an existing file system.\nupdate(8) update: periodically update the super block.\nuucico(8c) uucico, uucpd: transfer files queued by uucp or uux.\nuuclean(8c) uuclean: uucp spool directory clean-up.\nuupoll(8c) uupoll: poll a remote UUCP site.\nuusnap(8c) uusnap: show snapshot of the UUCP system.\nuuxqt(8c) uuxqt: UUCP execution file interpreter.\nvipw(8) vipw: edit the password file.\n"
  },
  {
    "path": "share/man/man1/Makefile",
    "content": "#\n# Copyright (c) 1987 Regents of the University of California.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms are permitted\n# provided that the above copyright notice and this paragraph are\n# duplicated in all such forms and that any documentation,\n# advertising materials, and other materials related to such\n# distribution and use acknowledge that the software was developed\n# by the University of California, Berkeley.  The name of the\n# University may not be used to endorse or promote products derived\n# from this software without specific prior written permission.\n# THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n# IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n# WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n#\n#\t@(#)Makefile\t1.9 (2.11BSD) 1998/1/24\n#\nTOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nMDIR=\t/usr/share/man/cat1\nSRCS=\tadb.1 addbib.1 apply.1 apropos.1 as.1 at.1 atq.1 atrm.1 \\\n\tawk.1 basename.1 biff.1 binmail.1 cal.1 calendar.1 cat.1 \\\n\tcb.1 cc.1 cd.1 checknr.1 chgrp.1 chmod.1 clear.1 cmp.1 col.1 \\\n\tcolcrt.1 colrm.1 comm.1 compress.1 cp.1 csh.1 ctags.1 date.1 \\\n\tdd.1 deroff.1 df.1 diction.1 diff.1 diff3.1 du.1 echo.1 ed.1 \\\n\tefl.1 eqn.1 error.1 ex.1 expand.1 expr.1 f77.1 false.1 file.1 \\\n\tfind.1 fmt.1 fold.1 fpr.1 from.1 fsplit.1 gcore.1 \\\n\tgraph.1 grep.1 head.1 hostid.1 indent.1 \\\n\tintro.1 join.1 kill.1 last.1 lastcomm.1 \\\n\tlearn.1 leave.1 lex.1 lint.1 lisp.1 ln.1 logger.1 login.1 \\\n\tlook.1 lookbib.1 lorder.1 lpq.1 lpr.1 lprm.1 lptest.1 ls.1 \\\n\tlxref.1 m4.1 mail.1 make.1 man.1 mesg.1 mkdep.1 mkdir.1 mkstr.1 \\\n\tmore.1 mset.1 msgs.1 mt.1 mv.1 netstat.1 newaliases.1 nice.1 nm.1\nSRCS1=\tnroff.1 nslookup.1 od.1 pagesize.1 pdx.1 pi.1 pix.1 \\\n\tplot.1 pmerge.1 pr.1 printenv.1 prof.1 ps.1 ptx.1 pwd.1 px.1 pxp.1 \\\n\tpxref.1 quota.1 ratfor.1 rcp.1 rdist.1 refer.1 rev.1 \\\n\trlogin.1 rm.1 rmail.1 rmdir.1 roffbib.1 rsh.1 ruptime.1 rwho.1 \\\n\tsccs.1 script.1 sed.1 sendbug.1 sh.1 size.1 sleep.1 soelim.1 \\\n\tsort.1 sortbib.1 spell.1 spline.1 split.1 strcompact.1 strings.1 \\\n\tstrip.1 style.1 su.1 sum.1 symcompact.1 symorder.1 \\\n\ttabs.1 tail.1 talk.1 \\\n\ttar.1 tbl.1 tc.1 tcopy.1 tee.1 telnet.1 time.1 \\\n\ttip.1 tk.1 tn3270.1 touch.1 tp.1 tr.1 troff.1 true.1 \\\n\ttsort.1 tty.1 ul.1 unifdef.1 uniq.1 units.1 uptime.1 users.1 \\\n\tuucp.1 uuencode.1 uulog.1 uuname.1 uuq.1 uusend.1 uux.1 \\\n\tvacation.1 vgrind.1 vi.1 vmstat.1 vwidth.1 w.1 wait.1 wall.1 wc.1 \\\n\twhat.1 whatis.1 which.1 who.1 whois.1 window.1 \\\n\twrite.1 xstr.1 yacc.1 yes.1\nOBJS1=\tadb.0 addbib.0 apply.0 apropos.0 as.0 at.0 atq.0 atrm.0 \\\n\tawk.0 basename.0 biff.0 binmail.0 cal.0 calendar.0 cat.0 \\\n\tcb.0 cc.0 cd.0 checknr.0 chgrp.0 chmod.0 clear.0 cmp.0 col.0 \\\n\tcolcrt.0 colrm.0 comm.0 compress.0 cp.0 csh.0 ctags.0 date.0 \\\n\tdd.0 deroff.0 df.0 diction.0 diff.0 diff3.0 du.0 echo.0 ed.0 \\\n\tefl.0 eqn.0 error.0 ex.0 expand.0 expr.0 f77.0 false.0 file.0 \\\n\tfind.0 fmt.0 fold.0 fpr.0 from.0 fsplit.0 gcore.0 \\\n\tgraph.0 grep.0 head.0 hostid.0 indent.0 \\\n\tintro.0 join.0 kill.0 last.0 lastcomm.0 \\\n\tlearn.0 leave.0 lex.0 lint.0 lisp.0 ln.0 logger.0 login.0 \\\n\tlook.0 lookbib.0 lorder.0 lpq.0 lpr.0 lprm.0 lptest.0 ls.0 \\\n\tlxref.0 m4.0 mail.0 make.0 man.0 mesg.0 mkdep.0 mkdir.0 mkstr.0 \\\n\tmore.0 mset.0 msgs.0 mt.0 mv.0 netstat.0 newaliases.0 nice.0 nm.0\nOBJS2=\tnroff.0 nslookup.0 od.0 pagesize.0 pdx.0 pi.0 pix.0 \\\n\tplot.0 pmerge.0 pr.0 printenv.0 prof.0 ps.0 ptx.0 pwd.0 px.0 pxp.0 \\\n\tpxref.0 quota.0 ratfor.0 rcp.0 rdist.0 refer.0 rev.0 \\\n\trlogin.0 rm.0 rmail.0 rmdir.0 roffbib.0 rsh.0 ruptime.0 rwho.0 \\\n\tsccs.0 script.0 sed.0 sendbug.0 sh.0 size.0 sleep.0 soelim.0 \\\n\tsort.0 sortbib.0 spell.0 spline.0 split.0 strcompact.0 strings.0 \\\n\tstrip.0 style.0 su.0 sum.0 symcompact.0 symorder.0 \\\n\ttabs.0 tail.0 talk.0 \\\n\ttar.0 tbl.0 tc.0 tcopy.0 tee.0 telnet.0 time.0 \\\n\ttip.0 tk.0 tn3270.0 touch.0 tp.0 tr.0 troff.0 true.0 \\\n\ttsort.0 tty.0 ul.0 unifdef.0 uniq.0 units.0 uptime.0 users.0 \\\n\tuucp.0 uuencode.0 uulog.0 uuname.0 uuq.0 uusend.0 uux.0 \\\n\tvacation.0 vgrind.0 vi.0 vmstat.0 vwidth.0 w.0 wait.0 wall.0 wc.0 \\\n\twhat.0 whatis.0 which.0 who.0 whois.0 window.0 \\\n\twrite.0 xstr.0 yacc.0 yes.0\n\n.SUFFIXES: .1 .0\n\n.1.0:\n\t${MANROFF} $*.1 > $*.0\n\nall: _make_01 _make_02\n\n_make_01: ${OBJS1}\n\n_make_02: ${OBJS2}\n\n# mandoc accepts and processes the eqn language,\n# and gives cleaner output than \"eqn | nroff\"\n#eqn.0:\n#\teqn eqn.1 | ${MANROFF} > $@\n\nclean: FRC\n\trm -f ${OBJS1}\n\trm -f ${OBJS2}\n\ninstall: _make_01 _make_02\n\tcp ${OBJS1} ${DESTDIR}${MDIR}\n\tcp ${OBJS2} ${DESTDIR}${MDIR}\n\tln -f ${DESTDIR}/${MDIR}/sh.0 ${DESTDIR}${MDIR}/case.0\n\tln -f ${DESTDIR}/${MDIR}/eqn.0 ${DESTDIR}${MDIR}/checkeq.0\n\tln -f ${DESTDIR}${MDIR}/tip.0 ${DESTDIR}${MDIR}/cu.0\n\tln -f ${DESTDIR}${MDIR}/diff.0 ${DESTDIR}${MDIR}/diffh.0\n\tln -f ${DESTDIR}${MDIR}/ex.0 ${DESTDIR}${MDIR}/edit.0\n\tln -f ${DESTDIR}${MDIR}/grep.0 ${DESTDIR}${MDIR}/egrep.0\n\tln -f ${DESTDIR}${MDIR}/diction.0 ${DESTDIR}${MDIR}/explain.0\n\tln -f ${DESTDIR}${MDIR}/grep.0 ${DESTDIR}${MDIR}/fgrep.0\n\tln -f ${DESTDIR}${MDIR}/sh.0 ${DESTDIR}${MDIR}/for.0\n\tln -f ${DESTDIR}${MDIR}/sh.0 ${DESTDIR}${MDIR}/if.0\n\tln -f ${DESTDIR}${MDIR}/lookbib.0 ${DESTDIR}${MDIR}/indxbib.0\n\tln -f ${DESTDIR}${MDIR}/eqn.0 ${DESTDIR}${MDIR}/neqn.0\n\tln -f ${DESTDIR}${MDIR}/nice.0 ${DESTDIR}${MDIR}/nohup.0\n\tln -f ${DESTDIR}${MDIR}/more.0 ${DESTDIR}${MDIR}/page.0\n\tln -f ${DESTDIR}${MDIR}/spell.0 ${DESTDIR}${MDIR}/spellin.0\n\tln -f ${DESTDIR}${MDIR}/spell.0 ${DESTDIR}${MDIR}/spellout.0\n\tln -f ${DESTDIR}${MDIR}/compress.0 ${DESTDIR}${MDIR}/uncompress.0\n\tln -f ${DESTDIR}${MDIR}/expand.0 ${DESTDIR}${MDIR}/unexpand.0\n\tln -f ${DESTDIR}${MDIR}/uuencode.0 ${DESTDIR}${MDIR}/uudecode.0\n\tln -f ${DESTDIR}${MDIR}/sh.0 ${DESTDIR}${MDIR}/while.0\n\tln -f ${DESTDIR}${MDIR}/compress.0 ${DESTDIR}${MDIR}/zcat.0\n\nFRC:\n"
  },
  {
    "path": "share/man/man1/adb.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)adb.1\t6.1.1 (2.11BSD) 1996/10/21\n.\\\"\n.TH ADB 1 \"October 21, 1996\"\n.UC 2\n.SH NAME\nadb \\- debugger (2BSD)\n.SH SYNOPSIS\n.B adb\n[\\fB\\-w\\fR] [ \\fB\\-k\\fR ] [ \\fB-I\\fRdir ] [ objfil [ corfil ] ]\n.ds TW \\v'.25m'\\s+2~\\s-2\\v'-.25m'\n.ds ST *\n.ds IM \\v'.1m'=\\v'-.1m'\\s-2\\h'-.1m'>\\h'.1m'\\s+2\n.ds LE \\(<=\n.ds LT \\s-2<\\s+2\n.ds GT \\s-2>\\s+2\n.SH DESCRIPTION\n.I Adb\nis a general purpose debugging program.\nIt may be used to examine files and to provide\na controlled environment for the execution of UNIX programs.\n.PP\n.I Objfil\nis normally an executable program file, preferably\ncontaining a symbol table; if not then the symbolic features of\n.I  adb\ncannot be used although the file can still be examined.\nThe default for\n.I objfil\nis\n.B  a.out.\n.I Corfil\nis assumed to be a core image file produced after executing\n.IR objfil ;\nthe default for\n.I corfil\nis\n.B  core.\n.PP\nRequests to\n.I  adb\nare read from the standard input and responses are to the standard output.\nIf the\n.B  \\-w\nflag is present then both\n.I  objfil\nand\n.I corfil\nare created if necessary and opened for reading and writing\nso that files can be modified using\n.IR adb .\n.PP\nThe \\fB\\-k\\fP option makes \\fIadb\\fP do UNIX kernel memory\nmapping; it should be used when \\fIcore\\fP is a UNIX crash dump\nor \\fI/dev/mem\\fP.\n.PP\nThe \\fB\\-I\\fP option specifies a directory where files to be read\nwith $< or $<< (see below) will be sought; the default is\n.IR /usr/share/adb .\n.PP\n.I Adb\nignores QUIT; INTERRUPT causes return to the next\n.I adb\ncommand.\n.PP\nIn general requests to\n.I  adb\nare of the form\n.PP\n.if n .ti 16\n.if t .ti 1.6i\n[\\|\\fIaddress\\fR\\|]  [\\|,\n.IR count \\|]\n[\\|\\fIcommand\\fR\\|] [\\|;\\|]\n.PP\nIf\n.I address\nis present then\n.I  dot\nis set to\n.IR address .\nInitially\n.I dot\nis set to 0.  For most commands\n.I count\nspecifies how many times the command will be executed.  The default\n.I count\nis 1.\n.I Address\nand\n.I count\nare expressions.\n.PP\nThe interpretation of an address depends on the context it is used in.\nIf a subprocess is being debugged then addresses are interpreted\nin the usual way in the address space of the subprocess.\nFor further details of address mapping see\n.SM ADDRESSES.\n.SH EXPRESSIONS\n.TP 7.2n\n.B .\nThe value of\n.IR dot .\n.TP 7.2n\n+\nThe value of\n.I dot\nincremented by the current increment.\n.TP 7.2n\n^\nThe value of\n.I dot\ndecremented by the current increment.\n.TP 7.2n\n\"\nThe last\n.I address\ntyped.\n.TP 7.2n\n.I integer\nAn octal number if\n.I integer\nbegins with a 0;\na hexadecimal number if preceded by\n.BR # ;\notherwise a decimal number.\nThis default interpretation of integers may be changed via the $o and $d\ncommands.\n.TP 7.2n\n.IB integer . fraction\nA 32 bit floating point number.\n.TP 7.2n\n.I \\'cccc\\|\\'\nThe ASCII value of up to 4 characters.\n\\e may be used to escape a \\'.\n.TP 7.2n\n.I \\*(LT name\nThe value of\n.IR name ,\nwhich is either a variable name or a register name.\n.I Adb\nmaintains a number of variables (see\n.SM VARIABLES\\*S)\nnamed by single letters or digits.\nIf\n.I name\nis a register name then the value of the register is obtained from\nthe system header in\n.IR corfil .\nThe register names are those printed by the $r command.\n.TP 7.2n\n.I symbol\nA\n.I symbol\nis a sequence of upper or lower case letters, underscores or\ndigits, not starting with a digit.  The backslash character\n.B \\e \nmay be used to escape other characters.  The value of the\n.I symbol\nis taken from the symbol table in\n.IR objfil .\nAn initial \\_ or \\*(TW will be prepended to\n.I symbol\nif needed.\nIf the symbol is a text symbol and\n.I objfil\nis an overlay type, the default is\n.IR \\*(TWsymbol ,\nwhich is the subroutine itself, not the entry interface in the base segment.\n.TP\n.I _ symbol\nIn C, the `true name' of an external symbol begins with _.\nIt may be necessary to utter this name to distinguish it\nfrom internal or hidden variables of a program.\nFor a subroutine in an overlay,\n.I \\*(TWsymbol \nis the actual subroutine,\nand\n.I _symbol\nis the entry point in the base segment (the \"thunk\").\nNote that to explicitly specify the local name,\nthe \\*(TW must be preceeded by a backslash, since \\*(TW is the\nbitwise complement operator:\n.I \\e\\*(TWsymbol\nmust be typed.\n.TP 7.2n\n.IB routine . name\nThe address of the variable\n.I name\nin the specified C routine.  Both\n.I routine\nand\n.I name\nare\n.IR symbols .\nIf\n.I name\nis omitted the value is the address of the most recently activated C stack frame\ncorresponding to\n.IR routine .\n.TP 7.2n\n.RI ( exp \\|)\nThe value of the expression\n.IR exp .\n.LP\n.SM\n.B  \"Monadic\\ operators\"\n.TP 7.2n\n.RI \\*(ST exp\nThe contents of the location addressed by\n.I exp\nin\n.IR corfil .\n.TP 7.2n\n.RI @ exp\nThe contents of the location addressed by\n.I exp\nin\n.IR objfil .\n.TP 7.2n\n.RI \\- exp\nInteger negation.\n.TP 7.2n\n.RI \\*(TW exp\nBitwise complement.\n.LP\n.tr ''\n.B  \"Dyadic\\ operators\"\nare left associative and are less binding than monadic operators.\n.TP 7.2n\n.IR e1 + e2\nInteger addition.\n.TP 7.2n\n.IR e1 \\- e2\nInteger subtraction.\n.TP 7.2n\n.IR e1 \\*(ST e2\nInteger multiplication.\n.TP 7.2n\n.IR e1 % e2\nInteger division.\n.TP 7.2n\n.IR e1 & e2\nBitwise conjunction.\n.TP 7.2n\n.IR e1 \\(bv e2\nBitwise disjunction.\n.TP 7.2n\n.IR e1 # e2\n.I E1\nrounded up to the next multiple of\n.IR e2 .\n.DT\n.SH COMMANDS\nMost commands consist of a verb followed by a modifier or list of modifiers.\nThe following verbs are available.\n(The commands `?' and `/' may be followed by `\\*(ST'; see\n.SM ADDRESSES\nfor further details.)\n.TP .5i\n.RI ? f\nLocations starting at\n.I address\nin\n.I  objfil\nare printed according to the format\n.IR f .\n.I dot\nis incremented by the sum of the increments for each format letter (q.v.).\n.TP\n.RI / f\nLocations starting at\n.I address\nin\n.I  corfil\nare printed according to the format\n.I f\nand\n.I dot\nis incremented as for `?'.\n.TP\n.RI  = f\nThe value of\n.I address\nitself is printed in the styles indicated by the format\n.IR f .\n(For\n.B i \nformat `?' is printed for the parts of the instruction that reference\nsubsequent words.)\n.PP\nA\n.I format\nconsists of one or more characters that specify a style of printing.\nEach format character may be preceded by a decimal integer\nthat is a repeat count for the format character.\nWhile stepping through a format\n.I dot\nis incremented temporarily by the amount given for each format letter.\nIf no format is given then the last format is used.\nThe format letters available are as follows.\n.ta 2.5n .5i\n.RS\n.TP\n.BR o \"\t2\"\nPrint 2 bytes in octal.  All octal numbers output by\n.I adb\nare preceded by 0.\n.br\n.ns\n.TP\n.BR O \"\t4\"\nPrint 4 bytes in octal.\n.br\n.ns\n.TP\n.BR q \"\t2\"\nPrint in signed octal.\n.br\n.ns\n.TP\n.BR Q \"\t4\"\nPrint long signed octal.\n.br\n.ns\n.TP\n.BR d \"\t2\"\nPrint in decimal.\n.br\n.ns\n.TP\n.BR D \"\t4\"\nPrint long decimal.\n.br\n.ns\n.TP\n.BR x \"\t2\"\nPrint 2 bytes in hexadecimal.\n.br\n.ns\n.TP\n.BR X \"\t4\"\nPrint 4 bytes in hexadecimal.\n.br\n.ns\n.TP\n.BR u \"\t2\"\nPrint as an unsigned decimal number.\n.br\n.ns\n.TP\n.BR U \"\t4\"\nPrint long unsigned decimal.\n.br\n.ns\n.TP\n.BR f \"\t4\"\nPrint the 32 bit value as a floating point number.\n.br\n.ns\n.TP\n.BR F \"\t8\"\nPrint double floating point.\n.br\n.ns\n.TP\n.BR b \"\t1\"\nPrint the addressed byte in octal.\n.br\n.ns\n.TP\n.BR c \"\t1\"\nPrint the addressed character.\n.br\n.ns\n.TP\n.BR C \"\t1\"\nPrint the addressed character using\nthe following escape convention.\nthe standard escape convention where control characters\nare printed as ^X and the delete character is printed as ^?.\n.br\n.ns\n.TP\n.BI s \"\tn\"\nPrint the addressed characters until a zero character is reached.\n.br\n.ns\n.TP\n.BI S \"\tn\"\nPrint a string using the ^\\fIX\\fR escape convention (see \\fBC\\fR above).\n.I n\nis the length of the string including its zero terminator.\n.br\n.ns\n.TP\n.BR Y \"\t4\"\nPrint 4 bytes in date format (see\n.IR ctime (3)).\n.br\n.ns\n.TP\n.BR i \"\tn\"\nPrint as machine instructions.\n.I n\nis the number of bytes occupied by the instruction.\nThis style of printing causes variables 1 and 2 to be set\nto the offset parts of the source and destination respectively.\n.br\n.ns\n.TP\n.BR a \"\t0\"\nPrint the value of\n.I dot\nin symbolic form.\nSymbols are checked to ensure that they have an appropriate\ntype as indicated below.\n.LP\n\t/\tlocal or global data symbol\n.br\n\t?\tlocal or global text symbol\n.br\n\t=\tlocal or global absolute symbol\n.TP\n.BR p \"\t2\"\nPrint the addressed value in symbolic form using\nthe same rules for symbol lookup as\n.BR a .\n.br\n.tr ''\n.ns\n.TP\n.BR t \"\t0\"\nWhen preceded by an integer tabs to the next appropriate tab stop.\nFor example,\n.B 8t \nmoves to the next 8-space tab stop.\n.br\n.ns\n.TP\n.BR r \"\t0\"\nPrint a space.\n.br\n.ns\n.TP\n.BR n \"\t0\"\nPrint a newline.\n.br\n.ns\n.tr '\"\n.TP\n.BR '...' \" 0\"\nPrint the enclosed string.\n.br\n.tr ''\n.br\n.ns\n.TP\n.B ^\n.I Dot\nis decremented by the current increment.  Nothing is printed.\n.br\n.ns\n.TP\n+\n.I Dot\nis incremented by 1.  Nothing is printed.\n.br\n.ns\n.TP\n\\-\n.I Dot\nis decremented by 1.  Nothing is printed.\n.RE\n.TP\nnewline\nIf the previous command temporarily incremented\n.IR dot ,\nmake the increment permanent.\nRepeat the previous command with a\n.I count\nof 1.\n.TP\n.RB [ ?/ ] l \"\\fI value mask\\fR\"\nWords starting at\n.I  dot\nare masked with\n.I mask\nand compared with\n.I value\nuntil a match is found.\nIf\n.B L\nis used then the match is for 4 bytes at a time instead of 2.\nIf no match is found then\n.I dot\nis unchanged; otherwise\n.I dot\nis set to the matched location.\nIf\n.I mask\nis omitted then \\-1 is used.\n.TP\n.RB [ ?/ ] w \"\\fI value ...\\fR\"\nWrite the 2-byte\n.I value\ninto the addressed location.  If the command is\n.BR W ,\nwrite 4 bytes.\nOdd addresses are not allowed when writing to the subprocess address space.\n.TP\n[\\fB?/\\fR]\\fBm\\fI b1 e1 f1\\fR[\\fB?/\\fR]\n.br\nNew values for\n.RI ( b1,\\ e1,\\ f1 )\nare recorded.  If less than three expressions are given then\nthe remaining map parameters are left unchanged.\nIf the `?' or `/' is followed by `\\*(ST' then\nthe last segment (\\fIb2\\fR\\|,\\|\\fIe2\\fR\\|,\\|\\fIf2\\fR)\nof the mapping is changed.\nIf the list is terminated by `?' or `/' then the file (\\fIobjfil\\fR or\n.I corfil\nrespectively) is used for subsequent requests.\n(So that, for example, `/m?' will cause `/' to refer to\n.IR objfil .)\n.TP\n.BI \\*(GT name\n.I Dot\nis assigned to the variable or register named.\n.TP\n.B !\nA shell (/bin/sh) is called to read the rest of the line following `!'.\n.TP\n.RI $ modifier\nMiscellaneous commands.  The available \n.I modifiers \nare:\n.RS\n.TP\n.BI < f\nRead commands from the file\n.IR f .\nIf this command is executed in a file, further commands\nin the file are not seen.\nIf\n.I f\nis omitted, the current input stream is terminated.  If a\n.I count\nis given, and is zero, the command will be ignored.\nThe value of the count will be placed in variable\n.I 9\nbefore the first command in\n.I f\nis executed.\n.br\n.ns\n.TP\n.BI << f\nSimilar to\n.B <\nexcept it can be used in a file of commands without\ncausing the file to be closed.  Variable\n.I 9\nis saved during the execution of this command, and restored when it completes.\nThere is a (small) finite limit to the number of\n.B <<\nfiles that can be open at once.\n.br\n.ns\n.TP\n.BI > f\nAppend output to the file\n.IR f ,\nwhich is created if it does not exist.  If\n.I f\nis omitted, output is returned to the terminal.\n.br\n.ns\n.TP\n.B ?\nPrint process id, the signal which caused stoppage or termination,\nas well as the registers as \\fB$r\\fR.  This is the default if\n\\fImodifier\\fR is omitted.\n.br\n.ns\n.TP\n.B r\nPrint the general registers and the instruction addressed by\n.BR pc .\n.I Dot\nis set to \\fBpc\\fR.\n.br\n.ns\n.TP\n.B f\nPrint the floating registers in\nsingle or double length.\nIf the floating point status of\n.B ps\nis set to double (0200 bit)\nthen double length is used anyway.\n.br\n.ns\n.TP\n.B b\nPrint all breakpoints and their associated counts and commands.\n.br\n.ns\n.TP\n.B a\nALGOL 68 stack backtrace.\nIf\n.I address\nis given then it is taken to be the\naddress of the current frame (instead of\n.BR r4 ).\nIf\n.I count\nis given then only the first\n.I count\nframes are printed.\n.br\n.ns\n.TP\n.B c\nC stack backtrace.  If\n.I address\nis given then it is taken as the address of the current frame \ninstead of the contents of the frame\\-pointer register.  If\n.B C \nis used then the names and (16 bit) values of all automatic\nand static variables are printed for each active function.\nIf\n.I count\nis given then only the first\n.I count\nframes are printed.\n.br\n.ns\n.TP\n.B e\nThe names and values of external variables are printed.\n.br\n.ns\n.TP\n.B w\nSet the page width for output to\n.I address\n(default 80).\n.br\n.ns\n.TP\n.B s\nSet the limit for symbol matches to\n.I address\n(default 255).\n.br\n.ns\n.TP\n.B o\nAll integers input are regarded as octal.\n.br\n.ns\n.TP\n.B d\nReset integer input as described in\n.SM EXPRESSIONS.\n.br\n.ns\n.TP\n.B q\nExit from\n.IR adb .\n.br\n.ns\n.TP\n.B v\nPrint all non zero variables in octal.\n.br\n.ns\n.TP\n.B m\nPrint the address map.\n.RE\n.TP\n.BI : modifier\nManage a subprocess.  Available modifiers are:\n.RS\n.TP\n.BI b c\nSet breakpoint at\n.IR address .\nIf\n.I objfil\nis overlaid and\n.I address\nis in the overlay region,\nthe breakpoint is set in the overlay of the symbol mentioned\nif \n.I address\nwas given symbolically, otherwise it is set\nin the current overlay (that in variable c).\nThe breakpoint is executed\n.IR count \\-1\ntimes before causing a stop.\nEach time the breakpoint is encountered the command\n.I c\nis executed.  If this command is omitted or sets\n.I dot\nto zero then the breakpoint causes a stop.\n.TP\n.B d\nDelete breakpoint at\n.IR address .\n.TP\n.B r\nRun\n.I objfil\nas a subprocess.  If\n.I address\nis given explicitly then the program is entered at this point; otherwise\nthe program is entered at its standard entry point.\n.I count\nspecifies how many breakpoints are to be ignored before stopping.\nArguments to the subprocess may be supplied on the same line as the command.\nAn argument starting with < or > causes the standard\ninput or output to be established for the command.\n.TP\n.BI c s\nThe subprocess is continued with signal\n.I s,\nsee\n.IR sigvec (2).\nIf\n.I address\nis given then the subprocess is continued at this address.\nIf no signal is specified then the signal\nthat caused the subprocess to stop is sent.\nBreakpoint skipping is the same as for\n.BR r .\n.TP\n.BI s s\nAs for\n.B c \nexcept that the subprocess is single stepped\n.I count\ntimes.  If there is no current subprocess then\n.I objfil\nis run as a subprocess as for\n.BR r .\nIn this case no signal can be sent; the remainder of the line\nis treated as arguments to the subprocess.\n.TP\n.B k\nThe current subprocess, if any, is terminated.\n.RE\n.SH VARIABLES\n.I Adb\nprovides a number of variables.\nNamed variables are set initially by\n.I  adb\nbut are not used subsequently (except for c).\nNumbered variables are reserved for communication as follows.\n.TP\n0\nThe last value printed.\n.br\n.ns\n.TP\n1\nThe last offset part of an instruction source.\n.br\n.ns\n.TP\n2\nThe previous value of variable 1.\n.br\n.ns\n.TP\n9\nThe count on the last $< or $<< command.\n.PP\nOn entry the following are set from the system header in the\n.IR corfil .\nIf\n.I corfil\ndoes not appear to be a\n.B core \nfile then these values are set from\n.IR objfil .\n.TP\nb\nThe base address of the data segment.\n.br\n.ns\n.TP\nc\nThe current overlay.  This is set from\n.IR corfil ,\nand in turn sets the overlay map.\nThis variable and the map may be changed\nby referring to other overlays symbolically\n(e.g. by examining text in subroutines in other overlays),\nusing the $r command (which resets c from the core file),\nor explicitly (with the command >c).\n.br\n.ns\n.TP\nd\nThe data segment size.\n.br\n.ns\n.TP\ne\nThe entry point.\n.br\n.ns\n.TP\nm\nThe `magic' number (0405, 0407, 0410, 0411, 0430 or 0431).\nThe object is overlaid if m is 0430 or 0431.\n.br\n.ns\n.TP\no\nThe sum of the overlay segment sizes (if overlaid).\n.br\n.ns\n.TP\ns\nThe stack segment size.\n.br\n.ns\n.TP\nt\nThe text segment size.\n.SH ADDRESSES\nThe address in a file associated with\na written address is determined by a mapping associated with that file.\nEach mapping is represented by two or three triples\n.RI ( \"b1, e1, f1\" ),\n.RI ( \"bo, eo, fo\" )\nfor overlaid object files,\nand\n.RI ( \"b2, e2, f2\" )\nand the\n.I file address\ncorresponding to a written\n.I address\nis calculated as follows.\n.PP\n.if t .ti 1.5i\n.if n .ti 8\n.IR b1 \\*(LE address < e1\n\\*(IM\n.IR \"file address\" = address + f1\\-b1,\notherwise,\n.PP\nif overlaid,\n.if t .ti 1.5i\n.if n .ti 8\n.IR bo \\*(LE address < eo\n\\*(IM\n.IR \"file address\" = address + fo\\-bo,\notherwise,\n.PP\n.if t .ti 1.5i\n.if n .ti 8\n.IR b2 \\*(LE address < e2\n\\*(IM\n.IR \"file address\" = address + f2\\-b2,\n.PP\notherwise, the requested\n.I address\nis not legal.  In some cases (e.g. for programs with separated I and D\nspace) the two segments for a file may overlap.  If a\n.B ? \nor\n.B / \nis followed by an\n.B \\*(ST \nthen only the last triple is used.\n.PP\nThe initial setting of both mappings is suitable for normal\n.B a.out \nand\n.B core \nfiles.  If the object file is not of the kind expected then, for both files,\n.I b1\nis set to 0,\n.I e1\nis set to the maximum file size and\n.I f1\nis set to 0; in this way the whole\nfile can be examined with no address translation.\n.PP\nSo that\n.I adb\nmay be used on large files all appropriate values are kept as\nsigned 32 bit integers.\n.SH FILES\na.out\n.br\ncore\n.SH SEE\\ ALSO\ncc(1),\nptrace(2),\na.out(5),\ncore(5)\n.br\n\\fIADB - A Tutorial\\fR, S. R. Bourne\n.SH DIAGNOSTICS\n`Adb' when there is no current command or format.\nComments about inaccessible files, syntax errors,\nabnormal termination of commands, etc.\nExit status is 0, unless last command failed or returned nonzero status.\n.SH BUGS\nWhen single stepping, system calls do not count as an\nexecuted instruction.\n.br\nLocal variables whose names are the same as an external\nvariable may foul up the accessing of the external.\n.br\nLocal variables cannot be accessed in routines that are in overlays.\n.br\nSince no shell is invoked to interpret the arguments of the\n.B :r\ncommand, the customary wild-card and variable expansions cannot occur.\n"
  },
  {
    "path": "share/man/man1/addbib.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)addbib.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH ADDBIB 1 \"April 29, 1985\"\n.UC 5\n.SH NAME\naddbib \\- create or extend bibliographic database\n.SH SYNOPSIS\n\\fBaddbib\\fP  [ \\fB\\-p\\fP  promptfile ]  [ \\fB\\-a\\fP ]  database\n.SH DESCRIPTION\nWhen this program starts up, answering ``y''\nto the initial ``Instructions?'' prompt yields directions;\ntyping ``n'' or \\s-2RETURN\\s0 skips them.\n.I Addbib\nthen prompts for various bibliographic fields,\nreads responses from the terminal,\nand sends output records to a\n.I database.\nA null response (just \\s-2RETURN\\s0) means to leave out that field.\nA minus sign (\\-) means to go back to the previous field.\nA trailing backslash allows a field to be continued on the next line.\nThe repeating ``Continue?'' prompt allows the user\neither to resume by typing ``y'' or \\s-2RETURN\\s0,\nto quit the current session by typing ``n'' or ``q'',\nor to edit the\n.I database\nwith any system editor \\fI(vi, ex, edit, ed).\\fP\n.PP\nThe\n.B \\-a\noption suppresses prompting for an abstract;\nasking for an abstract is the default.\nAbstracts are ended with a \\s-2CTRL\\s0-d.\nThe\n.B \\-p\noption causes\n.I addbib\nto use a new prompting skeleton, defined in\n.I promptfile.\nThis file should contain prompt strings, a tab,\nand the key-letters to be written to the\n.I database.\n.PP\nThe most common key-letters and their meanings are given below.\n.I Addbib\ninsulates you from these key-letters,\nsince it gives you prompts in English,\nbut if you edit the bibliography file later on,\nyou will need to know this information.\n.sp\n.nf\n\t%A\tAuthor's name\n\t%B\tBook containing article referenced\n\t%C\tCity (place of publication)\n\t%D\tDate of publication\n\t%E\tEditor of book containing article referenced\n\t%F\tFootnote number or label (supplied by \\fIrefer\\fP\\|)\n\t%G\tGovernment order number\n\t%H\tHeader commentary, printed before reference\n\t%I\tIssuer (publisher)\n\t%J\tJournal containing article\n\t%K\tKeywords to use in locating reference\n\t%L\tLabel field used by \\fB\\-k\\fP option of \\fIrefer\\fP\n\t%M\tBell Labs Memorandum (undefined)\n\t%N\tNumber within volume\n\t%O\tOther commentary, printed at end of reference\n\t%P\tPage number(s)\n\t%Q\tCorporate or Foreign Author (unreversed)\n\t%R\tReport, paper, or thesis (unpublished)\n\t%S\tSeries title\n\t%T\tTitle of article or book\n\t%V\tVolume number\n\t%X\tAbstract \\(em used by \\fIroffbib\\fP, not by \\fIrefer\\fP\n\t%Y,Z\tignored by \\fIrefer\\fP\n.fi\n.sp\nExcept for `A', each field should be given just once.\nOnly relevant fields should be supplied.\nAn example is:\n.sp\n.nf\n\t%A\tBill Tuthill\n\t%T\tRefer \\(em A Bibliography System\n\t%I\tComputing Services\n\t%C\tBerkeley\n\t%D\t1982\n\t%O\t\\s-1UNX\\s0 4.3.5.\n.fi\n.sp\n.SH FILES\n.DT\npromptfile\toptional file to define prompting\n.SH SEE ALSO\nrefer(1), sortbib(1), roffbib(1), indxbib(1), lookbib(1)\n.SH AUTHORS\nAl Stangenberger, Bill Tuthill\n"
  },
  {
    "path": "share/man/man1/apply.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)apply.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH APPLY 1 \"April 29, 1985\"\n.UC 5\n.SH NAME\napply \\- apply a command to a set of arguments\n.SH SYNOPSIS\n.B apply\n[\n.B \\-a\\fIc\\fP\n] [\n.B \\-\\fIn\\fP\n] command args ...\n.SH DESCRIPTION\n.I Apply\nruns the named\n.I command\non each\nargument\n.I arg\nin turn.\nNormally arguments are chosen singly; the optional number\n.I n\nspecifies the number of arguments to be passed to\n.I command.\nIf\n.I n\nis zero,\n.I command\nis run without arguments once for each\n.I arg.\nCharacter sequences of the form %\\fId\\fP\nin\n.I command,\nwhere\n.I d\nis a digit from 1 to 9,\nare replaced by the\n\\fId\\fP'th following unused\n.I arg.\nIf any such sequences occur,\n.I n\nis ignored,\nand the number of arguments passed to\n.I command\nis the maximum value of\n.I d\nin\n.I command.\nThe character `%' may be changed by the\n.B \\-a\noption.\n.PP\nExamples:\n.RS\napply echo *\n.RE\nis similar to ls(1);\n.RS\napply \\-2 cmp a1 b1 a2 b2 ...\n.RE\ncompares the `a' files to the `b' files;\n.RS\napply \\-0 who 1 2 3 4 5\n.RE\nruns who(1) 5 times; and\n.RS\napply \\(aaln %1 /usr/joe\\(aa *\n.RE\nlinks all files in the current directory to the directory /usr/joe.\n.SH \"SEE ALSO\"\nsh(1)\n.SH AUTHOR\nRob Pike\n.SH BUGS\nShell metacharacters in\n.I command\nmay have bizarre effects; it is best to enclose complicated\ncommands in single quotes \\(aa\\ \\(aa.\n.sp\nThere is no way to pass a literal `%2' if `%' is the\nargument expansion character.\n"
  },
  {
    "path": "share/man/man1/apropos.1",
    "content": ".\\\"\t@(#)apropos.1\t6.4 (Berkeley) 6/5/86\n.\\\"\n.TH APROPOS 1 \"June 5, 1986\"\n.AT 3\n.SH NAME\napropos \\- locate commands by keyword lookup\n.SH SYNOPSIS\n.B apropos\nkeyword ...\n.SH DESCRIPTION\n.I Apropos\nshows which manual sections contain instances of any of the given\nkeywords in their title.\nEach word is considered separately and case of letters is ignored.\nWords which are part of other words are considered; thus, when looking for\ncompile, \\fIapropos\\fP will find all instances of `compiler' also.\nTry\n.IP\napropos password\n.PP\nand\n.IP\napropos editor\n.PP\nIf the line starts `name(section) ...' you can do\n`man section name' to get the documentation for it.\nTry `apropos format' and then `man 3s printf' to get the manual\non the subroutine\n.I printf.\n.PP\n.I Apropos\nis actually just the\n.B \\-k\noption to the\n.IR man (1)\ncommand.\n.SH FILES\n.DT\n/usr/man/whatis\t\tdata base\n.SH \"SEE ALSO\"\nman(1), whatis(1), catman(8)\n.SH AUTHOR\nWilliam Joy\n"
  },
  {
    "path": "share/man/man1/as.1",
    "content": ".TH AS 1 \"March 12, 1994\"\n.UC\n.SH NAME\nas \\- assembler\n.SH SYNOPSIS\n.B as\n[\n.B \\-u\n] [\n.B \\-V\n] [\n.B \\-o\nobjfile\n] file ... \n.SH DESCRIPTION\n.I As\nassembles the concatenation of the named files.\nThe options are:\n.TP\n.B \\-u\nTreat all undefined symbols in the assembly as external globals.\n.TP\n.B \\-\\^V\nProduce an object suitable for loading into an automatic text overlaid\nprogram.\n.TP\n.B \\-\\^o\nUse\n.I objfil\nfor the name of the resultant object.  If this is omitted,\n.I a.out\nis used.  If no errors occurred during the assembly and if\nthere were no unresolved external references, it is made executable.\n.P\nThe special file name\n.B \\-\\-\nserves two purposes.  It signals the end of all options and causes\n.I stdin\nto be read for input.  Thus it is now possible to pipe data to the\nassembler:\n.br\n.sp\n/lib/cpp -E foo.s | sed -e ';^#;/;' | as -o foo.o --\n.br\n.sp\nThe file name\n.B \\-\\-\nmay be placed between normal files, when EOF is detected on \n.I stdin\nthe next file in the argument list is opened and read.\n.br\n.sp\nIf no input files are specified then \n.I stdin\nis read.\n.SH FILES\n/tmp/atm1\ttemporary\n.br\na.out\tobject\n.SH \"SEE ALSO\"\nadb(1), ld(1), nm(1), a.out(5)\n.br\n.I \"UNIX Assembler Manual\"\nby D. M. Ritchie\n.SH DIAGNOSTICS\nWhen\nan input file cannot be read, its name\nfollowed by a question mark is typed and assembly\nceases.\nWhen syntactic or semantic errors occur, a single-character diagnostic is typed out\ntogether with the line number and the file name in which it\noccurred.\nErrors in pass 1 cause cancellation of pass 2.\nThe possible errors are:\n.PP\n.ta 3\n)\tParentheses error\n.br\n]\tParentheses error\n.br\n<\tString not terminated properly\n.br\n*\tIndirection used illegally\n.br\n.li\n\\fB.\\fP\tIllegal assignment to `\\fB.\\fP'\n.br\na\tError in address\n.br\nb\tBranch instruction is odd or too remote\n.br\ne\tError in expression\n.br\nf\tError in local (`f' or `b') type symbol\n.br\ng\tGarbage (unknown) character\n.br\ni\tEnd of file inside an if\n.br\nm\tMultiply defined symbol as label\n.br\no\tWord quantity assembled at odd address\n.br\np\t`\\fB.\\fP' different in pass 1 and 2\n.br\nr\tRelocation error\n.br\nu\tUndefined symbol\n.br\nx\tSyntax error\n.br\n.SH BUGS\nSyntax errors can cause incorrect line numbers\nin following diagnostics.\n"
  },
  {
    "path": "share/man/man1/at.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)at.1\t6.2.1 (2.11BSD) 1996/10/21\n.\\\"\n.TH AT 1 \"October 21, 1996\"\n.UC 4\n.SH NAME\nat \\- execute commands at a later time\n.SH SYNOPSIS\n.B \"at [ -c ] [ -s ] [ -m ]\"\ntime\n[ day ]\n[ file ]\n.SH DESCRIPTION\n.I At\nspools away a copy of the named\n.I file\nto be used as input to\n.IR sh (1)\nor\n.IR csh (1).\nIf the\n.B \\-c\nflag (for \n.IR (csh (1)))\nor the\n.B \\-s\nflag (for\n.IR (sh (1)))\nis specified, then that shell will be used to execute the job;\nif no shell is specified, \nthe current environment shell is used.\nIf no file name is specified, \n.I at\nprompts for commands from standard input until a ^D is typed. \n.PP\nIf the \n.B \\-m\nflag is specified, mail will be sent to the user after the job\nhas been run. If errors occur during execution of the job, then\na copy of the error diagnostics will be sent to the user. If\nno errors occur, then a short message is sent informing the\nuser that no errors occurred.\n.PP\nThe format of the spool file is as follows:\nA four line header that includes the owner of the job, the name of the job,\nthe shell used to run the job, and whether mail will be\nset after the job is executed. The header is followed by a\n.I cd\ncommand to the current directory and a \n.I umask\ncommand to set the modes on any files created by the job.\nThen \n.I at\ncopies all relevant environment variables to the spool file.\nWhen the script is run, it uses the user and group ID\nof the creator of the spool file.\n.PP\nThe\n.I time\nis 1 to 4 digits, with an optional following\n`A', `P', `N' or `M' for\nAM, PM, noon or midnight.\nOne and two digit numbers are taken to be hours, three and four digits\nto be hours and minutes.\nIf no letters follow the digits, a 24 hour clock time is understood.\n.PP\nThe optional\n.I day\nis either\n(1) a month name followed by a day number,\nor\n(2) a day of the week; \nif the word `week' follows, invocation is moved\nseven days further off.\nNames of months and days may be recognizably truncated.\nExamples of legitimate commands are\n.IP\nat 8am jan 24\n.br\nat -c -m 1530 fr week\n.br\nat -s -m 1200n week\n.PP\n.I At\nprograms are executed by periodic execution \nof the command \n.IR\n/usr/libexec/atrun \nfrom \n.IR cron (8).\nThe granularity of\n.I at\ndepends upon the how often atrun is executed.\n.PP\nError output is lost unless redirected or the\n.I \\-m\nflag is requested, in which case a copy of the errors is sent to\nthe user via \n.IR mail (1).\n.SH FILES\n.nf\n/usr/spool/at                spooling area\n/usr/spool/at/yy.ddd.hhhh.*  job file\n/usr/spool/at/past           directory where jobs are executed from\n/usr/spool/at/lasttimedone   last time atrun was run\n/usr/libexec/atrun               executor (run by cron(8))\n.fi\n.SH \"SEE ALSO\"\natq(1),\natrm(1),\ncalendar(1),\nsleep(1),\ncron(8)\n.SH DIAGNOSTICS\nComplains about various syntax errors and times out of range.\n.SH BUGS\nDue to the granularity of the execution of\n.IR /usr/libexec/atrun,\nthere may be bugs in scheduling things almost\nexactly 24 hours into the future.\n\nIf the system crashes, mail is not sent to the user informing them that\nthe job was not completed.\n\nSometimes old spool files are not removed from the directory\n/usr/spool/at/past. This is usually due to a system crash,\nand requires that they be removed by hand.\n"
  },
  {
    "path": "share/man/man1/atq.1",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)atq.1\t6.2 (Berkeley) 5/10/86\n.\\\"\n.TH ATQ 1 \"May 10, 1986\"\n.UC 6\n.SH NAME\natq \\- print the queue of jobs waiting to be run\n.SH SYNOPSIS\n.B atq\n[ -c ] [ -n ] [ name ... ]\n.SH DESCRIPTION\n.I Atq \nprints the queue of jobs that are waiting to be run\nat a later date. These jobs were created with the\n.IR at (1)\ncommand.\nWith no flags, the queue is sorted in the order that\nthe jobs will be executed.\n.PP\nIf the \n.B \\-c \nflag is used, the queue is sorted by the time that the \n.I at \ncommand was given. \n.PP\nThe \n.B \\-n \nflag prints only the total number of files that are currently\nin the queue. \n.PP\nIf a name(s) is provided, only those files belonging to that user(s) are \ndisplayed.\n.SH FILES\n/usr/spool/at\t\tspool area\n.SH \"SEE ALSO\"\nat(1),\natrm(1),\ncron(8)\n"
  },
  {
    "path": "share/man/man1/atrm.1",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)atrm.1\t6.2 (Berkeley) 5/10/86\n.\\\"\n.TH ATRM 1 \"May 10, 1986\"\n.UC 6\n.SH NAME\natrm \\- remove jobs spooled by at\n.SH SYNOPSIS\n.B atrm\n[ -f ] [ -i ] [-] [[ job #] [ name ]... ]\n.SH DESCRIPTION\n.I Atrm \nremoves jobs that were created with the\n.IR at (1)\ncommand.\nWith the\n.B \\-\nflag, all jobs belonging to the person invoking\n.I atrm\nare removed.\nIf a job number(s) is specified, \n.I atrm\nattempts to remove only that job number(s).\n.PP\nIf the \n.B \\-f \nflag is used, all information regarding the \nremoval of the specified jobs is suppressed.\nIf the\n.B \\-i\nflag is used, \n.I atrm\nasks if a job should be removed; a response of 'y' causes the job to be removed.\n.PP\nIf a user(s) name is specified, all \njobs belonging to that user(s) are removed.\nThis form of invoking \n.I atrm\nis useful only to the super-user.\n.SH FILES\n/usr/spool/at\t\tspool area\n.SH \"SEE ALSO\"\nat(1),\natq(1),\ncron(8)\n"
  },
  {
    "path": "share/man/man1/awk.1",
    "content": ".\\\"\t@(#)awk.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH AWK 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nawk \\- pattern scanning and processing language\n.SH SYNOPSIS\n.B awk\n[\n.BI \\-F c\n]\n[ prog ] [ file ] ...\n.SH DESCRIPTION\n.I Awk\nscans each input\n.I file\nfor lines that match any of a set of patterns specified in\n.IR prog .\nWith each pattern in\n.I prog\nthere can be an associated action that will be performed\nwhen a line of a\n.I file\nmatches the pattern.\nThe set of patterns may appear literally as\n.I prog,\nor in a file\nspecified as\n.B \\-f\n.IR file .\n.PP\nFiles are read in order;\nif there are no files, the standard input is read.\nThe file name `\\-'\nmeans the standard input.\nEach line is matched against the\npattern portion of every pattern-action statement;\nthe associated action is performed for each matched pattern.\n.PP\nAn input line is made up of fields separated by white space.\n(This default can be changed by using FS,\n.IR \"vide infra\" \".)\"\nThe fields are denoted $1, $2, ... ;\n$0 refers to the entire line.\n.PP\n.PP\nA pattern-action statement has the form\n.PP\n\tpattern { action }\n.PP\nA missing { action } means print the line;\na missing pattern always matches.\n.PP\nAn action is a sequence of statements.\nA statement can be one of the following:\n.PP\n.nf\n\tif ( conditional ) statement [ else statement ]\n\twhile ( conditional ) statement\n\tfor ( expression ; conditional ; expression ) statement\n\tbreak\n\tcontinue\n\t{ [ statement ] ... }\n\tvariable = expression\n\tprint [ expression-list ] [ >expression ]\n\tprintf format [ , expression-list ] [ >expression ]\n\tnext\t# skip remaining patterns on this input line \n\texit\t# skip the rest of the input\n.fi\n.PP\nStatements are terminated by\nsemicolons, newlines or right braces.\nAn empty expression-list stands for the whole line.\nExpressions take on string or numeric values as appropriate,\nand are built using the operators\n+, \\-, *, /, %,  and concatenation (indicated by a blank).\nThe C operators ++, \\-\\-, +=, \\-=, *=, /=, and %=\nare also available in expressions.\nVariables may be scalars, array elements\n(denoted\nx[i])\nor fields.\nVariables are initialized to the null string.\nArray subscripts may be any string,\nnot necessarily numeric;\nthis allows for a form of associative memory.\nString constants are quoted \"...\".\n.PP\nThe \n.I print\nstatement prints its arguments on the standard output\n(or on a file if \n.I >file\nis present), separated by the current output field separator,\nand terminated by the output record separator.\nThe\n.I printf\nstatement formats its expression list according to the format\n(see\n.IR printf (3S)).\n.PP\nThe built-in function\n.I length\nreturns the length of its argument\ntaken as a string,\nor of the whole line if no argument.\nThere are also built-in functions\n.I exp,\n.I log,\n.I sqrt,\nand\n.IR int .\nThe last truncates its argument to an integer.\n.IR substr(s,\\ m,\\ n)\nreturns the \n.IR n -character\nsubstring of\n.I s\nthat begins at position\n.IR m .\nThe function\n.IR sprintf(fmt,\\ expr,\\ expr,\\ ...)\nformats the expressions\naccording to the\n.IR printf (3S)\nformat given by\n.I fmt\nand returns the resulting string.\n.PP\nPatterns are arbitrary Boolean combinations\n(!, \\(or\\(or, &&, and parentheses) of \nregular expressions and\nrelational expressions.\nRegular expressions must be surrounded\nby slashes and are as in\n.IR egrep .\nIsolated regular expressions\nin a pattern apply to the entire line.\nRegular expressions may also occur in\nrelational expressions.\n.PP\nA pattern may consist of two patterns separated by a comma;\nin this case, the action is performed for all lines\nbetween an occurrence of the first pattern\nand the next occurrence of the second.\n.PP\n.nf\nA relational expression is one of the following:\n.PP\n.nf\n\texpression matchop regular-expression\n\texpression relop expression\n.PP\n.fi\nwhere a relop is any of the six relational operators in C,\nand a matchop is either ~ (for contains)\nor !~ (for does not contain).\nA conditional is an arithmetic expression,\na relational expression,\nor a Boolean combination\nof these.\n.PP\nThe special patterns\nBEGIN\nand\nEND\nmay be used to capture control before the first input line is read\nand after the last.\nBEGIN must be the first pattern, END the last.\n.PP\nA single character\n.I c\nmay be used to separate the fields by starting\nthe program with\n.PP\n\tBEGIN { FS = \"c\" }\n.PP\nor by using the\n.BI \\-F c\noption.\n.PP\nOther variable names with special meanings\ninclude NF, the number of fields in the current record;\nNR, the ordinal number of the current record;\nFILENAME, the name of the current input file;\nOFS, the output field separator (default blank);\nORS, the output record separator (default newline);\nand\nOFMT, the output format for numbers (default \"%.6g\").\n.PP\n.SH EXAMPLES\n.PP\nPrint lines longer than 72 characters:\n.PP\n.nf\n\tlength > 72\n.fi\n.PP\nPrint first two fields in opposite order:\n.PP\n.nf\n\t{ print $2, $1 }\n.fi\n.PP\nAdd up first column, print sum and average:\n.PP\n.nf\n\t\t{ s += $1 }\n\tEND\t{ print \"sum is\", s, \" average is\", s/NR }\n.fi\n.PP\nPrint fields in reverse order:\n.PP\n.nf\n\t{ for (i = NF; i > 0; \\-\\-i) print $i }\n.fi\n.PP\nPrint all lines between start/stop pairs:\n.PP\n.nf\n\t/start/, /stop/\n.fi\n.PP\nPrint all lines whose first field is different from previous one:\n.PP\n.nf\n\t$1 != prev { print; prev = $1 }\n.fi\n.SH SEE ALSO\n.PP\nlex(1), sed(1)\n.br\nA. V. Aho, B. W. Kernighan, P. J. Weinberger,\n.I\nAwk \\- a pattern scanning and processing language\n.SH BUGS\nThere are no explicit conversions between numbers and strings.\nTo force an expression to be treated as a number add 0 to it;\nto force it to be treated as a string concatenate \"\"\nto it.\n"
  },
  {
    "path": "share/man/man1/basename.1",
    "content": ".\\\"\t@(#)basename.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH BASENAME 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nbasename \\- strip filename affixes\n.SH SYNOPSIS\n.B basename\nstring [ suffix ]\n.SH DESCRIPTION\n.I Basename\ndeletes any prefix ending in `/' and the\n.I suffix,\nif present in\n.I string,\nfrom\n.I string,\nand prints the result on the standard output.\nIt is normally used inside substitution marks \\`\\ \\`\nin shell procedures.\n.PP\nThis shell procedure invoked with the argument\n.I /usr/src/bin/cat.c\ncompiles the named file and moves the output to\n.I cat\nin the current directory:\n.IP \"\" 15n\ncc $1\n.br\nmv a.out \\`basename $1 .c\\`\n.SH \"SEE ALSO\"\nsh(1)\n"
  },
  {
    "path": "share/man/man1/biff.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)biff.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH BIFF 1 \"April 29, 1985\"\n.UC 4\n.SH NAME\nbiff \\- be notified if mail arrives and who it is from\n.SH SYNOPSIS\n.B biff\n[\n.B yn\n]\n.SH DESCRIPTION\n.I Biff\ninforms the system whether you want to be notified when mail arrives\nduring the current terminal session.\nThe command\n.IP\n.B \"biff y\"\n.LP\nenables notification; the command\n.IP\n.B \"biff n\"\n.LP\ndisables it.\nWhen mail notification is enabled, the header and first few lines of\nthe message will be printed on your screen whenever mail arrives.\nA ``biff y'' command is often included in the file\n.I \\&.login\nor\n.I \\&.profile\nto be executed at each login.\n.PP\n.I Biff\noperates asynchronously.\nFor synchronous notification use the MAIL variable of\n.IR sh (1)\nor the\n.I mail\nvariable of\n.IR csh (1).\n.SH SEE ALSO\ncsh(1),\nsh(1),\nmail(1),\ncomsat(8C)\n"
  },
  {
    "path": "share/man/man1/binmail.1",
    "content": ".\\\"\t@(#)binmail.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH BINMAIL 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nbinmail \\- send or receive mail among users\n.SH SYNOPSIS\n.B /bin/mail\n[\n.B +\n] [\n.B \\-i\n] [ person ] ...\n.br\n.B /bin/mail\n.B \"[ + ]\"\n[\n.B \\-i\n]\n.B \\-f\nfile\n.LP\n.SH DESCRIPTION\nNote: This is the old version 7 UNIX system mail program.  The default\n.I mail\ncommand is described in\n.IR Mail (1),\nand its binary is in the directory\n.IR /usr/ucb .\n.PP\n.I mail\nwith no argument prints a user's mail, message-by-message,\nin last-in, first-out order; the optional argument\n.B +\ndisplays the mail messages in first-in, first-out order.\nFor each message, it reads a line from the standard input\nto direct disposition of the message.\n.TP\nnewline\nGo on to next message.\n.TP\nd\nDelete message and go on to the next.\n.TP\np\nPrint message again.\n.TP\n\\-\nGo back to previous message.\n.TP\n.RI \"s [\" \" file \" \"] ...\"\nSave the message in the named\n.I files\n(`mbox' default).\n.TP\n.RI \"w [\" \" file \" \"] ...\"\nSave the message, without a header, in the named\n.I files\n(`mbox' default).\n.TP\n.RI \"m [\" \" person \" \"] ...\"\nMail the message to the named\n.I persons\n(yourself is default).\n.TP\nEOT (control-D)\nPut unexamined mail back in the mailbox and stop.\n.TP\nq\nSame as EOT.\n.TP\n.RI ! command\nEscape to the Shell to do\n.IR command .\n.TP\n*\nPrint a command summary.\n.PP\nAn interrupt normally terminates the \n.I mail\ncommand; the mail file is unchanged.  The optional argument\n.B \\(mii\ntells\n.I mail\nto continue after interrupts.\n.PP\nWhen\n.I persons\nare named,\n.I mail\ntakes the standard input up to an end-of-file (or a line with just `.')\nand adds it to each\n.I person's\n`mail' file.  The message is preceded by the sender's name and a postmark.\nLines that look like postmarks are prepended with `>'.  A\n.I person\nis usually a user name recognized by\n.IR  login (1).\nTo denote a recipient on a remote system, prefix \n.I person\nby the system name and exclamation mark (see\n.IR uucp (1C)).\n.PP\nThe\n.B \\-f\noption causes the named file, for example, `mbox',\nto be printed as if it were the mail file.\n.PP\nWhen a user logs in he is informed of the presence of mail.\n.SH FILES\n.ta \\w'/usr/spool/mail/*.lock 'u\n/etc/passwd\tto identify sender and locate persons\n.br\n.li\n/usr/spool/mail/*\tincoming mail for user *\n.br\nmbox\t\tsaved mail\n.br\n/tmp/ma*\ttemp file\n.br\n/usr/spool/mail/*.lock\tlock for mail directory\n.br\ndead.letter\tunmailable text\n.br\n.SH \"SEE ALSO\"\nMail(1), write(1), uucp(1C), uux(1C), xsend(1), sendmail(8)\n.SH BUGS\nRace conditions sometimes result in a failure to remove a lock file.\n.PP\nNormally anybody can read your mail, unless it is sent by\n.IR xsend (1).\nAn installation can overcome this by making\n.I mail\na set-user-id command that owns the mail directory.\n"
  },
  {
    "path": "share/man/man1/cal.1",
    "content": ".\\\"\t@(#)cal.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH CAL 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\ncal \\- print calendar\n.SH SYNOPSIS\n.B cal\n[ month ] year\n.SH DESCRIPTION\n.I Cal\nprints a calendar for the specified year.\nIf a month is also specified, a calendar\njust for that month is printed.\n.I Year\ncan be between 1\nand 9999.\nThe\n.I month\nis a number between 1 and 12.\nThe calendar\nproduced is that for England and her colonies.\n.PP\nTry September 1752.\n.SH BUGS\nThe year is always considered to start in January even though this\nis historically naive.\n.br\nBeware that `cal 78' refers to the early Christian era,\nnot the 20th century.\n"
  },
  {
    "path": "share/man/man1/calendar.1",
    "content": ".\\\"\t@(#)calendar.1\t6.1.1 (2.11BSD) 1996/10/21\n.\\\"\n.TH CALENDAR 1 \"October 21, 1996\"\n.AT 3\n.SH NAME\ncalendar \\- reminder service\n.SH SYNOPSIS\n.B calendar\n[ \\- ]\n.SH DESCRIPTION\n.I Calendar \nconsults the file `calendar' in the current directory\nand prints out lines that contain today's or\ntomorrow's date anywhere in the line.\nMost reasonable month-day dates such as `Dec. 7,'\n`december 7,' `12/7,' etc., are recognized, but not\n`7 December' or `7/12'.\nIf you give the month as ``*''\nwith a date, i.e. ``* 1'', that day in any month will do.\nOn weekends `tomorrow' extends through Monday.\n.PP\nWhen \nan argument is present,\n.I calendar\ndoes its job for every user\nwho has a file `calendar' in his login directory\nand sends him any positive results by\n.IR mail (1).\nNormally this is done daily in the wee hours under control of\n.IR cron (8).\n.PP\nThe file `calendar' is first run through the ``C'' preprocessor,\n.IR /lib/cpp ,\nto include any other calendar files\nspecified with the usual ``#include'' syntax.\nIncluded calendars will usually be shared by all users,\nmaintained and documented by the local administration.\n.SH FILES\ncalendar\n.br\n/usr/libexec/calendar to figure out today's and tomorrow's dates\n.br\n/etc/passwd\n.br\n/tmp/cal*\n.br\n/lib/cpp, egrep, sed, mail as subprocesses\n.SH \"SEE ALSO\"\nat(1), cron(8), mail(1)\n.SH BUGS\n.I Calendar's\nextended idea of `tomorrow' doesn't account for\nholidays.\n"
  },
  {
    "path": "share/man/man1/cat.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)cat.1\t6.2 (Berkeley) 5/5/86\n.\\\"\n.TH CAT 1 \"May 5, 1986\"\n.UC 4\n.SH NAME\ncat \\- catenate and print\n.SH SYNOPSIS\n.B cat\n[\n.B \\-u\n] [\n.B \\-n\n] [\n.B \\-s\n] [\n.B \\-v\n]\nfile ...\n.br\n.SH DESCRIPTION\n.I Cat\nreads each\n.I file\nin sequence and displays it on the standard output.  Thus\n.PP\n.ti +15n\ncat file\n.PP\ndisplays the file on the standard output, and\n.PP\n.ti +15n\ncat file1 file2 >file3\n.PP\nconcatenates the first two files and places the result on the third.\n.PP\nIf no input file is given, or if the argument `\\-' is encountered,\n.I cat\nreads from the standard input file.\nOutput is buffered in the block size recommended by \\fIstat\\fP(2)\nunless the standard output is a terminal,\nwhen it is line buffered.  The\n.B \\-u\noption makes the output completely unbuffered.\n.PP\nThe\n.B \\-n\noption displays the output lines preceded by lines numbers, numbered\nsequentially from 1.  Specifying the \n.B \\-b\noption with the\n.B \\-n\noption omits the line numbers from blank lines.\n.PP\nThe\n.B \\-s\noption crushes out multiple adjacent empty lines so that the\noutput is displayed single spaced.\n.PP\nThe\n.B \\-v\noption displays non-printing characters so that they are visible.\nControl characters print like ^X for control-x; the delete character\n(octal 0177) prints as ^?.\nNon-ascii characters (with the high bit set) are printed as M-\n(for meta) followed by the character of the low 7 bits.  A\n.B \\-e\noption may be given with the\n.B \\-v\noption, which displays a `$' character at the end of each line.\nSpecifying the \n.B \\-t\noption with the\n.B \\-v\noption displays tab characters as ^I.\n.PP\n.SH \"SEE ALSO\"\ncp(1), ex(1), more(1), pr(1), tail(1)\n.SH BUGS\nBeware of `cat a b >a' and `cat a b >b', which destroy\nthe input files before reading them.\n"
  },
  {
    "path": "share/man/man1/cb.1",
    "content": ".\\\"\t@(#)cb.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH CB 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\ncb \\- C program beautifier\n.SH SYNOPSIS\n.B cb\n.SH DESCRIPTION\n.I Cb\nplaces a copy of the C program from the standard input\non the standard output with spacing and indentation\nthat displays the structure of the program.\n"
  },
  {
    "path": "share/man/man1/cc.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)cc.1\t6.2 (Berkeley) 6/7/85\n.\\\"\n.TH CC 1 \"June 7, 1985\"\n.UC 2\n.SH NAME\ncc \\- C compiler (2BSD)\n.SH SYNOPSIS\n.B cc\n[ option ] ... file ...\n.SH DESCRIPTION\n.I Cc\nis the UNIX C compiler.\n.I Cc\naccepts several types of arguments:\n.PP\nArguments whose names end with `.c' are taken to be\nC source programs; they are compiled, and\neach object program is left on the file\nwhose name is that of the source with `.o' substituted\nfor `.c'.\nThe `.o' file is normally deleted, however, if a single\nC program is compiled and loaded all at one go.\n.PP\nIn the same way,\narguments whose names end with `.s' are taken to be assembly source programs\nand are assembled, producing a `.o' file.\n.PP\nThe following options are interpreted by\n.IR cc .\nSee\n.IR ld (1)\nfor load-time options.\n.TP 8\n.B \\-c\nSuppress the loading phase of the compilation, and force\nan object file to be produced even if only one program is compiled.\n.TP\n.B \\-w\nSuppress warning diagnostics.\n.TP\n.B \\-p\nArrange for the compiler to produce code\nwhich counts the number of times each routine is called.\nIf loading takes place, replace the standard startup\nroutine by one which automatically calls\n.IR monitor (3)\nat the start and arranges to write out a\n.I mon.out\nfile at normal termination of execution of the object program.\nAn execution profile can then be generated by\nuse of\n.IR  prof (1).\n.TP\n.SM\n.B \\-O\nInvoke an\nobject-code improver.\n.TP\n.SM\n.B \\-S\nCompile the named C programs, and leave the\nassembler-language output on corresponding files suffixed `.s'.\n.TP\n.SM\n.B \\-M\nRun only the macro preprocessor\non the named C programs,\nrequesting it to generate Makefile dependencies\nand send the result to the standard output.\n.TP\n.SM\n.B \\-E\nRun only the macro preprocessor\non the named C programs, and send the result to the\nstandard output.\n.TP\n.SM\n.B \\-C\nprevent the macro preprocessor from eliding comments.\n.TP\n.BI \\-o \" output\"\nName the final output file\n.IR output .\nIf this option is used the file `a.out' will be left undisturbed.\n.TP\n.SM\n.BI \\-D name=def\n.br\n.ns\n.TP\n.SM\n.BI \\-D \\*Sname\nDefine the\n.I name\nto the preprocessor,\nas if by\n`#define'.\nIf no definition is given, the name is defined as \"1\".\n.TP\n.SM\n.BI \\-U \\*Sname\nRemove any initial definition of\n.IR name .\n.TP\n.SM\n.BI \\-I \\*Sdir\n`#include' files\nwhose names do not begin with `/' are always\nsought first in the directory \nof the\n.I file\nargument,\nthen in directories named in \n.B \\-I\noptions,\nthen in directories on a standard list.\n.TP\n.SM\n.BI \\-L \\*Sdir\nLibrary archives are sought first in\ndirectories named in\n.B \\-L\noptions,\nthen in directories on a standard list.\n.TP\n.SM\n.BI \\-B \\*Sstring\nFind substitute compiler passes in the files named\n.I string\nwith the suffixes cpp, c0, c1 and c2.\nIf \n.I string \nis empty, use a standard backup version.\n.TP\n.BR \\-t [ p012 ]\nFind only the designated compiler passes in the\nfiles whose names are constructed by a\n.B \\-B\noption.\nIn the absence of a\n.B \\-B \noption, the\n.I string\nis taken to be `/usr/c/'.\n.PP\nOther arguments\nare taken\nto be either loader option arguments, or C-compatible\nobject programs, typically produced by an earlier\n.I cc\nrun,\nor perhaps libraries of C-compatible routines.\nThese programs, together with the results of any\ncompilations specified, are loaded (in the order\ngiven) to produce an executable program with name\n.B a.out.\n.SH FILES\n.ta \\w'/usr/c/c[01]  'u\nfile.c\tinput file\n.br\nfile.o\tobject file\n.br\na.out\tloaded output\n.br\n/tmp/ctm?\ttemporary\n.br\n/lib/cpp\tpreprocessor\n.br\n/lib/c[01]\tcompiler\n.br\n/lib/c2\toptional optimizer\n.br\n/lib/crt0.o\truntime startoff\n.br\n/lib/mcrt0.o\tstartoff for profiling\n.br\n/lib/libc.a\tstandard library, see\n.IR intro (3)\n.br\n/usr/lib/libc_p.a\tprofiling library, see\n.IR intro (3)\n.br\n/usr/include\tstandard directory for `#include' files\n.br\nmon.out\tfile produced for analysis by\n.IR prof (1)\n.SH \"SEE ALSO\"\nB. W. Kernighan and D. M. Ritchie,\n.I The C Programming Language,\nPrentice-Hall,\n1978\n.br\nB. W. Kernighan,\n.I\nProgramming in C\\(ema tutorial\n.br\nD. M. Ritchie,\n.I\nC Reference Manual\n.br\nmonitor(3), prof(1), adb(1), ld(1), as(1)\n.SH DIAGNOSTICS\nThe diagnostics produced by C itself are intended to be\nself-explanatory.\nOccasional messages may be produced by the assembler\nor loader.\n.SH BUGS\nThe compiler currently ignores advice to put \n\\fBchar\\fR, \\fBunsigned char\\fR,\n\\fBlong\\fR,\n\\fBfloat\\fR, or \\fBdouble\\fR\nvariables in registers.\n"
  },
  {
    "path": "share/man/man1/cd.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)cd.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH CD 1 \"April 29, 1985\"\n.UC 4\n.SH NAME\ncd \\- change working directory\n.SH SYNOPSIS\n.B cd\ndirectory\n.SH DESCRIPTION\n.I Directory\nbecomes the new working directory.\nThe process must have execute (search)\npermission in\n.IR directory .\n.PP\nBecause a new process is created to execute each command,\n.I cd\nwould be ineffective if it were written as a\nnormal command.  It is therefore recognized and executed\nby the shells.\nIn\n.IR csh (1)\nyou may specify a list of directories in which\n.I directory\nis to be sought as a subdirectory if it is not\na subdirectory of the current directory;\nsee the description of the\n.I cdpath\nvariable in\n.IR csh (1).\n.SH \"SEE ALSO\"\ncsh(1), sh(1), pwd(1), chdir(2)\n"
  },
  {
    "path": "share/man/man1/checknr.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)checknr.1\t6.2 (Berkeley) 5/7/86\n.\\\"\n.TH CHECKNR 1 \"May 7, 1986\"\n.UC 4\n.SH NAME\nchecknr \\- check nroff/troff files\n.SH SYNOPSIS\n.B checknr\n[\n.B \\-s\n] [\n.B \\-f\n] [\n.BR \\-a \".x1.y1.x2.y2. ... .xn.yn\"\n] [\n.BR \\-c \".x1.x2.x3 ... .xn\"\n] [\n\\fIfile\\fP ...\n]\n.SH DESCRIPTION\n.I Checknr\nchecks a list of\n.IR nroff (1)\nor\n.IR troff (1)\ninput files for certain kinds of errors\ninvolving mismatched opening and closing delimiters\nand unknown commands.\nIf no files are specified,\n.I checknr\nchecks the standard input.\nDelimeters checked are:\n.IP (1)\nFont changes using \\efx ... \\efP.\n.IP (2)\nSize changes using \\esx ... \\es0.\n.IP (3)\nMacros that come in open ... close forms, for example,\nthe .TS and .TE macros which must always come in pairs.\n.PP\n.I Checknr\nknows about the\n.IR ms (7)\nand\n.IR me (7)\nmacro packages.\n.PP\nAdditional pairs of macros can be added to the list using the\n.B \\-a\noption.\nThis must be followed by groups of six characters, each group defining\na pair of macros.\nThe six characters are\na period,\nthe first macro name,\nanother period,\nand the second macro name.\nFor example, to define a pair .BS and .ES, use \\-\\fBa\\fP.BS.ES\n.PP\nThe\n.B \\-c\noption defines commands which would otherwise be complained about\nas undefined.\n.PP\nThe\n.B \\-f\noption requests\n.I checknr\nto ignore \\ef font changes.\n.PP\nThe\n.B \\-s\noption requests\n.I checknr\nto ignore \\es size changes.\n.PP\n.I Checknr\nis intended to be used on documents that are prepared with\n.I checknr\nin mind, much the same as\n.I lint.\nIt expects a certain document writing style for \\ef and \\es commands,\nin that each \\efx must be terminated with \\efP and\neach \\esx must be terminated with \\es0.\nWhile it will work to directly go into the next font or explicitly\nspecify the original font or point size,\nand many existing documents actually do this,\nsuch a practice will produce complaints from\n.I checknr.\nSince it is probably better to use the \\efP and \\es0 forms anyway,\nyou should think of this as a contribution to your document\npreparation style.\n.SH SEE\\ ALSO\nnroff(1), troff(1), checkeq(1), ms(7), me(7)\n.SH DIAGNOSTICS\nComplaints about unmatched delimiters.\n.br\nComplaints about unrecognized commands.\n.br\nVarious complaints about the syntax of commands.\n.SH BUGS\nThere is no way to define a 1 character macro name using\n.BR \\-a .\n.br\nDoes not correctly recognize certain reasonable constructs,\nsuch as conditionals.\n"
  },
  {
    "path": "share/man/man1/chgrp.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)chgrp.1\t6.2 (Berkeley) 5/22/86\n.\\\"\n.TH CHGRP 1 \"May 22, 1986\"\n.UC 5\n.SH NAME\nchgrp \\- change group\n.SH SYNOPSIS\n.B chgrp\n[ -f -R ]\ngroup file ...\n.SH DESCRIPTION\n.I Chgrp\nchanges the group-ID of the\n.I files\nto\n.IR group .\nThe group may be either a decimal GID or\na group name found in the group-ID file.\n.PP\nThe user invoking \n.I chgrp\nmust belong\nto the specified group and be the owner of the file, or be the super-user.\n.PP\nNo errors are reported when the\n.B \\-f\n(force) option is given.\n.PP\nWhen the\n.B \\-R\noption is given, \n.I chgrp\nrecursively descends its directory arguments\nsetting the specified group-ID.\nWhen symbolic links are encountered, their group is changed,\nbut they are not traversed.\n.SH FILES\n/etc/group\n.SH \"SEE ALSO\"\nchown(2),\npasswd(5),\ngroup(5)\n"
  },
  {
    "path": "share/man/man1/chmod.1",
    "content": ".\\\"\t@(#)chmod.1\t6.3 (Berkeley) 5/22/86\n.\\\"\n.TH CHMOD 1 \"May 22, 1986\"\n.AT 3\n.SH NAME\nchmod \\- change mode\n.SH SYNOPSIS\n\\fBchmod\\fP [\n.B \\-Rf\n] mode file ...\n.SH DESCRIPTION\nThe mode of each named file is changed according to \\fImode\\fP,\nwhich may be absolute or symbolic.  An absolute \\fImode\\fP\nis an octal number constructed from the OR of the following modes:\n.TP 10\n4000\nset user ID on execution\n.br\n.ns\n.TP 10\n2000\nset group ID on execution\n.br\n.ns\n.TP 10\n1000\nsticky bit, see\n.IR  chmod (2)\n.br\n.ns\n.TP 10\n0400\nread by owner\n.br\n.ns\n.TP 10\n0200\nwrite by owner\n.br\n.ns\n.TP 10\n0100\nexecute (search in directory) by owner\n.br\n.ns\n.TP 10\n0070\nread, write, execute (search) by group\n.br\n.ns\n.TP 10\n0007\nread, write, execute (search) by others\n.LP\nA symbolic \\fImode\\fP has the form:\n.IP\n.RI [ who ]\n\\fIop permission\\fP\n.RI [ \"op permission\" \"] ...\"\n.LP\nThe \\fIwho\\fP part is a combination of the letters \\fBu\\fP\n(for user's permissions), \\fBg\\fP (group) and \\fBo\\fP (other).\nThe letter \\fBa\\fP stands for all, or \\fBugo.\\fP\nIf \\fIwho\\fP is omitted, the default is \\fIa\\fP\nbut the setting of the file creation mask (see umask(2)) is taken into account.\n.LP\n\\fIOp\\fP can be \\fB+\\fP to add \\fIpermission\\fP to the file's mode,\n\\fB\\-\\fP to take away \\fIpermission\\fP and \\fB=\\fP to assign\n\\fIpermission\\fP absolutely (all other bits will be reset).\n.LP\n\\fIPermission\\fP is any combination of the letters \\fBr\\fP (read),\n\\fBw\\fP (write), \\fBx\\fP (execute),\n\\fBX\\fP (set execute only if file is a directory\nor some other execute bit is set),\n\\fBs\\fP (set owner or group id)\nand \\fBt\\fP (save text \\- sticky).\nLetters \\fBu\\fP, \\fBg\\fP, or \\fBo\\fP indicate that \\fIpermission\\fP\nis to be taken from the current mode. \nOmitting \\fIpermission\\fP\nis only useful with \\fB=\\fP to take away all permissions.\n.PP\nWhen the\n.B \\-R\noption is given, \n.I chmod\nrecursively descends its directory arguments\nsetting the mode for each file as described above.\nWhen symbolic links are encountered, their mode is not changed\nand they are not traversed.\n.PP\nIf the\n.B \\-f\noption is given,\n.I chmod\nwill not complain if it fails to change the mode\non a file.\n.SH EXAMPLES\n.LP\nThe first example denies write permission to others,\nthe second makes a file executable by all if it is executable by anyone:\n.IP\nchmod o\\-w file\n.br\nchmod +X file\n.LP\nMultiple symbolic modes separated by commas may be given.\nOperations are performed in the order specified.  The letter\n\\fBs\\fP is only useful with \\fBu\\fP or \\fBg.\\fP\n.LP\nOnly the owner of a file (or the super-user) may change its mode.\n.SH \"SEE ALSO\"\nls(1), chmod(2), stat(2), umask(2), chown(8)\n"
  },
  {
    "path": "share/man/man1/clear.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)clear.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH CLEAR 1 \"April 29, 1985\"\n.UC\n.SH NAME\nclear \\- clear terminal screen\n.SH SYNOPSIS\n.B clear\n.SH DESCRIPTION\n.I Clear\nclears your screen if this is possible.\nIt looks in the environment for the terminal type and then in\n.I /etc/termcap\nto figure out how to clear the screen.\n.SH FILES\n/etc/termcap\tterminal capability data base\n"
  },
  {
    "path": "share/man/man1/cmp.1",
    "content": ".\\\"\t@(#)cmp.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH CMP 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\ncmp \\- compare two files\n.SH SYNOPSIS\n.B cmp\n[\n.B \\-l\n] [\n.B \\-s\n]\nfile1 file2\n.SH DESCRIPTION\nThe two files are\ncompared.\n(If\n.I file1\nis `\\-',\nthe standard input is used.)\nUnder default options,\n.I cmp\nmakes no comment if the files are the same;\nif they differ, it announces the byte and line number\nat which the difference occurred.\nIf one file is an initial subsequence\nof the other, that fact is noted.\n.PP\nOptions:\n.TP 6\n.B  \\-l\nPrint the byte number (decimal) and the\ndiffering bytes (octal) for each difference.\n.TP 6\n.B  \\-s\nPrint nothing for differing files;\nreturn codes only.\n.SH \"SEE ALSO\"\n.DT\ndiff(1), comm(1)\n.SH DIAGNOSTICS\nExit code 0 is returned for identical\nfiles, 1 for different files, and 2 for an\ninaccessible or missing argument.\n"
  },
  {
    "path": "share/man/man1/col.1",
    "content": ".\\\"\t@(#)col.1\t6.2 (Berkeley) 5/16/86\n.\\\"\n.TH COL 1 \"May 16, 1986\"\n.AT 3\n.SH NAME\ncol \\- filter reverse line feeds\n.SH SYNOPSIS\n.B col\n[\n.B \\-bfh\n]\n.SH DESCRIPTION\n.I Col\nreads the standard input and writes the standard output.\nIt performs the line overlays implied by reverse line\nfeeds (ESC-7 in ASCII)\nand by forward and reverse half line feeds (ESC-9 and ESC-8).\n.I Col\nis particularly useful for filtering multicolumn\noutput made with the `.rt' command of\n.I nroff\nand output resulting from use of the\n.IR tbl (1)\npreprocessor.\n.PP\nAlthough\n.I col\naccepts half line motions in its input, it normally does not\nemit them on output.\nInstead, text that would appear between lines is moved to the next lower\nfull line boundary.\nThis treatment can be suppressed by the\n.B \\-f\n(fine) option; in this case\nthe output from\n.I col\nmay contain forward half line feeds (ESC-9), but will still never contain\neither kind of reverse line motion.\n.PP\nIf the\n.B \\-b\noption is given,\n.I col\nassumes that the output device in use is not capable of backspacing.\nIn this case, if several characters are to appear in the same place,\nonly the last one read will be taken.\n.PP\nThe control characters SO (ASCII code 017),\nand SI (016) are assumed\nto start and end text in an alternate character set.\nThe character set (primary or alternate) associated with each printing\ncharacter read is remembered; on output, SO and SI characters are generated\nwhere necessary to maintain the correct treatment of each character.\n.PP\nIf the\n.B \\-h\noption is given,\n.I col\nconverts white space to tabs to shorten printing time.\n.PP\nAll control characters are removed from the input except space,\nbackspace,\ntab, return, newline, ESC (033) followed by one of 7, 8, 9, SI, SO, and VT\n(013).\nThis last character is an alternate form of full reverse line feed, for\ncompatibility with some other hardware conventions.\nAll other non-printing characters are ignored.\n.SH \"SEE ALSO\"\ntroff(1), tbl(1)\n.SH BUGS\nCan't back up more than 128 lines.\n.br\nNo more than 800 characters, including backspaces, on a line.\n"
  },
  {
    "path": "share/man/man1/colcrt.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)colcrt.1\t6.2 (Berkeley) 5/7/86\n.\\\"\n.TH COLCRT 1 \"May 7, 1986\"\n.UC\n.SH NAME\ncolcrt \\- filter nroff output for CRT previewing\n.SH SYNOPSIS\n.B colcrt\n[\n.B \\-\n] [\n.B \\-2\n] [\nfile ...\n]\n.SH DESCRIPTION\n.I Colcrt\nprovides virtual half-line and reverse line feed sequences\nfor terminals without such capability, and on which overstriking\nis destructive.\nHalf-line characters and underlining (changed to dashing `\\-')\nare placed on new lines in between the normal output lines.\n.PP\nThe optional\n.B \\- \nsuppresses all underlining.\nIt is especially useful for previewing\n.I allboxed\ntables from\n.IR  tbl (1).\n.PP\nThe option\n.B \\-2\ncauses all half-lines to be printed, effectively double spacing the output.\nNormally, a minimal space output format is used which will suppress empty\nlines.\nThe program never suppresses two consecutive empty lines, however.\nThe\n.B \\-2\noption is useful for sending output to the line printer when the output\ncontains superscripts and subscripts which would otherwise be invisible.\n.PP\nA typical use of\n.I colcrt\nwould be\n.PP\n.DT\n\ttbl exum2.n | nroff \\-ms | colcrt \\- | more\n.SH \"SEE ALSO\"\nnroff/troff(1), col(1), more(1), ul(1)\n.SH BUGS\nShould fold underlines onto blanks even with the\n`\\fB\\-\\fR'\noption so that\na true underline character would show; if we did this, however,\n.I colcrt\nwouldn't get rid of\n.I cu'd\nunderlining\ncompletely.\n.PP\nCan't back up more than 102 lines.\n.PP\nGeneral overstriking is lost;\nas a special case `|' overstruck with `\\-' or underline becomes `+'.\n.PP\nLines are trimmed to 132 characters.\n.PP\nSome provision should be made for processing superscripts and subscripts\nin documents which are already double-spaced.\n"
  },
  {
    "path": "share/man/man1/colrm.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)colrm.1\t6.2 (Berkeley) 5/7/86\n.\\\"\n.TH COLRM 1 \"May 7, 1986\"\n.UC 4\n.SH NAME\ncolrm \\- remove columns from a file\n.SH SYNOPSIS\n.B colrm\n[\nstartcol\n[\nendcol\n]\n]\n.SH DESCRIPTION\n.I Colrm\nremoves selected columns from a file.  Input is taken from standard input.\nOutput is sent to standard output.\n.PP\nIf called with one parameter the columns\nof each line will be removed starting with the specified column.\nIf called with two parameters the columns from the first column\nto the last column will be removed.\n.PP\nColumn numbering starts with column 1.\n.SH \"SEE ALSO\"\nexpand(1)\n"
  },
  {
    "path": "share/man/man1/comm.1",
    "content": ".\\\"\t@(#)comm.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH COMM 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\ncomm \\- select or reject lines common to two sorted files\n.SH SYNOPSIS\n.B comm\n[\n.B \\-\n[\n.B 123\n]\n] file1 file2\n.SH DESCRIPTION\n.I Comm\nreads\n.I file1\nand\n.I file2,\nwhich should be ordered in ASCII collating sequence,\nand produces a three column output: lines only in\n.I file1;\nlines only in\n.I file2;\nand lines in both files.\nThe filename `\\-' means the standard input.\n.PP\nFlags 1, 2, or 3 suppress printing of the corresponding\ncolumn.\nThus\n.B comm\n.B \\-12\nprints only the lines common to the two files;\n.B comm\n.B \\-23\nprints only lines in the first file but not in the second;\n.B comm\n.B \\-123\nis a no-op.\n.PP\n.SH \"SEE ALSO\"\ncmp(1), diff(1), uniq(1)\n"
  },
  {
    "path": "share/man/man1/compress.1",
    "content": ".\\\"\t@(#)compress.1\t6.5 (Berkeley) 5/11/86\n.\\\"\n.TH COMPRESS 1 \"May 11, 1986\"\n.UC 6\n.SH NAME\ncompress, uncompress, zcat \\- compress and expand data\n.SH SYNOPSIS\n.PU\n.ll +8\n.B compress\n[\n.B \\-f\n] [\n.B \\-v\n] [\n.B \\-c\n] [\n.B \\-b\n.I bits\n] [\n.I \"name \\&...\"\n]\n.ll -8\n.br\n.B uncompress\n[\n.B \\-f\n] [\n.B \\-v\n] [\n.B \\-c\n] [\n.I \"name \\&...\"\n]\n.br\n.B zcat\n[\n.I \"name \\&...\"\n]\n.SH DESCRIPTION\n.I Compress\nreduces the size of the named files using adaptive Lempel-Ziv coding.\nWhenever possible,\neach file is replaced by one with the extension\n.B \"\\&.Z,\"\nwhile keeping the same ownership modes, access and modification times.\nIf no files are specified, the standard input is compressed to the\nstandard output.\nCompressed files can be restored to their original form using\n.I uncompress\nor\n.I zcat.\n.PP\nThe\n.B \\-f\noption will force compression of\n.IR name ,\neven if it does not actually shrink\nor the corresponding\n.IR name .Z\nfile already exists.\nExcept when run in the background under\n.IR /bin/sh ,\nif\n.B \\-f\nis not given the user is prompted as to whether an existing\n.IR name .Z\nfile should be overwritten.\n.PP\nThe\n.B \\-c\n(``cat'') option makes\n.I compress/uncompress\nwrite to the standard output; no files are changed.\nThe nondestructive behavior of\n.I zcat\nis identical to that of\n.I uncompress\n.B \\-c.\n.PP\n.I Compress\nuses the modified Lempel-Ziv algorithm popularized in\n\"A Technique for High Performance Data Compression\",\nTerry A. Welch,\n.I \"IEEE Computer,\"\nvol. 17, no. 6 (June 1984), pp. 8-19.\nCommon substrings in the file are first replaced by 9-bit codes 257 and up.\nWhen code 512 is reached, the algorithm switches to 10-bit codes and\ncontinues to use more bits until the\nlimit specified by the\n.B \\-b\nflag is reached (default 16).\n.I Bits\nmust be between 9 and 16.  The default can be changed in the source to allow\n.I compress\nto be run on a smaller machine.\n.PP\nAfter the\n.I bits\nlimit is attained,\n.I compress\nperiodically checks the compression ratio.  If it is increasing,\n.I compress\ncontinues to use the existing code dictionary.  However,\nif the compression ratio decreases,\n.I compress\ndiscards the table of substrings and rebuilds it from scratch.  This allows\nthe algorithm to adapt to the next \"block\" of the file.\n.PP\nNote that the\n.B \\-b\nflag is omitted for\n.I uncompress,\nsince the \n.I bits\nparameter specified during compression\nis encoded within the output, along with\na magic number to ensure that neither decompression of random data nor\nrecompression of compressed data is attempted. \n.PP\n.ne 8\nThe amount of compression obtained depends on the size of the\ninput, the number of\n.I bits\nper code, and the distribution of common substrings.\nTypically, text such as source code or English\nis reduced by 50\\-60%.\nCompression is generally much better than that achieved by\nHuffman coding (as used in\n.IR pack ),\nor adaptive Huffman coding\n.RI ( compact ),\nand takes less time to compute.\n.PP\nThe\n.B \\-v\noption causes\nthe printing of the percentage reduction of each file.\n.PP\nIf an error occurs, exit status is 1, else\nif the last file was not compressed because it became larger, the status\nis 2; else the status is 0.\n.SH \"DIAGNOSTICS\"\nUsage: compress [\\-fvc] [\\-b maxbits] [file ...]\n.in +8\nInvalid options were specified on the command line.\n.in -8\nMissing maxbits\n.in +8\nMaxbits must follow\n.BR \\-b \\.\n.in -8\n.IR file :\nnot in compressed format\n.in +8\nThe file specified to\n.I uncompress\nhas not been compressed.\n.in -8\n.IR file :\ncompressed with \n.I xx\nbits, can only handle \n.I yy\nbits\n.in +8\n.I File\nwas compressed by a program that could deal with\nmore \n.I bits\nthan the compress code on this machine.\nRecompress the file with smaller\n.IR bits \\.\n.in -8\n.IR file :\nalready has .Z suffix -- no change\n.in +8\nThe file is assumed to be already compressed.\nRename the file and try again.\n.in -8\n.IR file :\nfilename too long to tack on .Z\n.in +8\nThe file cannot be compressed because its name is longer than\n12 characters.\nRename and try again.\nThis message does not occur on BSD systems.\n.in -8\n.I file\nalready exists; do you wish to overwrite (y or n)?\n.in +8\nRespond \"y\" if you want the output file to be replaced; \"n\" if not.\n.in -8\nuncompress: corrupt input\n.in +8\nA SIGSEGV violation was detected which usually means that the input file is\ncorrupted.\n.in -8\nCompression: \n.I \"xx.xx%\"\n.in +8\nPercentage of the input saved by compression.\n(Relevant only for\n.BR \\-v \\.)\n.in -8\n-- not a regular file: unchanged\n.in +8\nWhen the input file is not a regular file,\n(e.g. a directory), it is\nleft unaltered.\n.in -8\n-- has \n.I xx \nother links: unchanged\n.in +8\nThe input file has links; it is left unchanged.  See\n.IR ln \"(1)\"\nfor more information.\n.in -8\n-- file unchanged\n.in +8\nNo savings is achieved by\ncompression.  The input remains virgin.\n.in -8\n.SH \"BUGS\"\nAlthough compressed files are compatible between machines with large memory,\n.BR \\-b \\12\nshould be used for file transfer to architectures with \na small process data space (64KB or less, as exhibited by the DEC PDP\nseries, the Intel 80286, etc.)\n.PP\n.I compress\nshould be more flexible about the existence of the `.Z' suffix.\n"
  },
  {
    "path": "share/man/man1/cp.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)cp.1\t6.2 (Berkeley) 6/8/85\n.\\\"\n.TH CP 1 \"June 8, 1985\"\n.UC 4\n.SH NAME\ncp \\- copy\n.SH SYNOPSIS\n.B cp\n[\n.B \\-ip\n] file1 file2\n.PP\n.B cp\n[\n.B \\-ipr\n] file ... directory\n.SH DESCRIPTION\n.I File1\nis copied onto\n.IR file2 .\nBy default, the mode and owner of  \n.I file2\nare preserved if it already\nexisted; otherwise the mode of the source file modified by the current\n.IR umask (2)\nis used.  The\n.B \\-p\noption causes\n.I cp\nto attempt to preserve (duplicate) in its copies the modification\ntimes and modes of the source files, ignoring the present\n.IR umask .\n.PP\nIn the second form, one or more\n.I files\nare copied into the\n.I directory\nwith their original file-names.\n.PP\n.I Cp\nrefuses to copy a file onto itself.\n.PP\nIf the \n.B \\-i\noption is specified, \n.I cp\nwill prompt the user with the name of the file\nwhenever the copy will cause an old file to be\noverwritten. An answer of 'y' will cause \n.I cp\nto continue. Any other answer will prevent it\nfrom overwriting the file.\n.PP\nIf the\n.B \\-r\noption is specified and any of the source files are directories,\n.I cp\ncopies each subtree rooted at that name; in this case\nthe destination must be a directory.\n.SH \"SEE ALSO\"\ncat(1), mv(1), rcp(1C)\n"
  },
  {
    "path": "share/man/man1/csh.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)csh.1\t6.8.1 (2.11BSD) 1996/11/27\n.\\\"\n.TH CSH 1 \"November 27, 1996\"\n.UC 4\n.de sh\n.br\n.ne 5\n.PP\n\\fB\\\\$1\\fR\n.PP\n..\n.if n .ds ua ^\n.if t .ds ua \\(ua\n.if n .ds aa '\n.if t .ds aa \\(aa\n.if n .ds ga `\n.if t .ds ga \\(ga\n.if t .tr *\\(**\n.SH NAME\ncsh \\- a shell (command interpreter) with C-like syntax\n.SH SYNOPSIS\n.B csh\n[\n.B \\-cef\\^instvVxX\n] [\narg ...\n]\n.SH DESCRIPTION\n.I Csh\nis a first implementation of a command language interpreter\nincorporating a history mechanism (see \\fBHistory Substitutions\\fP),\njob control facilities (see \\fBJobs\\fP), interactive file name\nand user name completion (see \\fBFile Name Completion\\fP),\nand a C-like syntax.\nSo as to be able to use its job control facilities, users of\n.I csh\nmust (and automatically) use the new tty driver fully described in\n.IR tty (4).\nThis new tty driver allows generation of interrupt characters\nfrom the keyboard to tell jobs to stop.  See\n.IR stty (1)\nfor details on setting options in the new tty driver.\n.PP\nAn instance of\n.I csh\nbegins by executing commands from the file `.cshrc' in the\n.I home\ndirectory of the invoker.\nIf this is a login shell then it also executes commands from the file\n`.login' there.\nIt is typical for users on crt's to put the command ``stty crt'' in their\n.I \\&.login\nfile, and to also invoke\n.IR tset (1)\nthere.\n.PP\nIn the normal case, the shell will then begin reading commands from the\nterminal, prompting with `% '.\nProcessing of arguments and the use of the shell to process files\ncontaining command scripts will be described later.\n.PP\nThe shell then repeatedly performs the following actions:\na line of command input is read and broken into\n.IR words .\nThis sequence of words is placed on the command history list and then parsed.\nFinally each command in the current line is executed.\n.PP\nWhen a login shell terminates it executes commands from the file `.logout'\nin the users home directory.\n.sh \"Lexical structure\"\nThe shell splits input lines into words at blanks and tabs with the\nfollowing exceptions.\nThe characters\n`&' `|' `;' `<' `>' `(' `)'\nform separate words.\nIf doubled in `&&', `|\\|\\||', `<<' or `>>' these pairs form single words.\nThese parser metacharacters may be made part of other words, or prevented their\nspecial meaning, by preceding them with `\\e'.\nA newline preceded by a `\\e' is equivalent to a blank.\n.PP\nIn addition strings enclosed in matched pairs of quotations,\n`\\*(aa', `\\*(ga' or `\"',\nform parts of a word; metacharacters in these strings, including blanks\nand tabs, do not form separate words.\nThese quotations have semantics to be described subsequently.\nWithin pairs of `\\'' or `\"' characters a newline preceded by a `\\e' gives\na true newline character.\n.PP\nWhen the shell's input is not a terminal,\nthe character `#' introduces a comment which continues to the end of the\ninput line.\nIt is prevented this special meaning when preceded by `\\e'\nand in quotations using `\\`', `\\'', and `\"'.\n.sh \"Commands\"\nA simple command is a sequence of words, the first of which\nspecifies the command to be executed.\nA simple command or\na sequence of simple commands separated by `|' characters\nforms a pipeline.\nThe output of each command in a pipeline is connected to the input of the next.\nSequences of pipelines may be separated by `;', and are then executed\nsequentially.\nA sequence of pipelines may be executed without immediately \nwaiting for it to terminate by following it with an `&'.\n.PP\nAny of the above may be placed in `(' `)' to form a simple command (which\nmay be a component of a pipeline, etc.)\nIt is also possible to separate pipelines with `|\\|\\||' or `&&' indicating,\nas in the C language,\nthat the second is to be executed only if the first fails or succeeds\nrespectively. (See\n.I Expressions.)\n.sh \"Jobs\"\nThe shell associates a \\fIjob\\fR with each pipeline.  It keeps\na table of current jobs, printed by the\n\\fIjobs\\fR command, and assigns them small integer numbers.  When\na job is started asynchronously with `&', the shell prints a line which looks\nlike:\n.PP\n.DT\n\t[1] 1234\n.PP\nindicating that the job which was started asynchronously was job number\n1 and had one (top-level) process, whose process id was 1234.\n.PP\nIf you are running a job and wish to do something else you may hit the key\n\\fB^Z\\fR (control-Z) which sends a STOP signal to the current job.\nThe shell will then normally indicate that the job has been `Stopped',\nand print another prompt.  You can then manipulate the state of this job,\nputting it in the background with the \\fIbg\\fR command, or run some other\ncommands and then eventually bring the job back into the foreground with\nthe foreground command \\fIfg\\fR.  A \\fB^Z\\fR takes effect immediately and\nis like an interrupt in that pending output and unread input are discarded\nwhen it is typed.  There is another special key \\fB^Y\\fR which does \nnot generate a STOP signal until a program attempts to\n.IR read (2)\nit.\nThis can usefully be typed ahead when you have prepared some commands\nfor a job which you wish to stop after it has read them.\n.PP\nA job being run in the background will stop if it tries to read\nfrom the terminal.  Background jobs are normally allowed to produce output,\nbut this can be disabled by giving the command ``stty tostop''.\nIf you set this\ntty option, then background jobs will stop when they try to produce\noutput like they do when they try to read input.\n.PP\nThere are several ways to refer to jobs in the shell.  The character\n`%' introduces a job name.  If you wish to refer to job number 1, you can\nname it as `%1'.  Just naming a job brings it to the foreground; thus\n`%1' is a synonym for `fg %1', bringing job 1 back into the foreground.\nSimilarly saying `%1 &' resumes job 1 in the background.\nJobs can also be named by prefixes of the string typed in to start them,\nif these prefixes are unambiguous, thus `%ex' would normally restart\na suspended\n.IR ex (1)\njob, if there were only one suspended job whose name began with\nthe string `ex'.  It is also possible to say `%?string'\nwhich specifies a job whose text contains\n.I string,\nif there is only one such job.\n.PP\nThe shell maintains a notion of the current and previous jobs.\nIn output pertaining to jobs, the current job is marked with a `+'\nand the previous job with a `\\-'.  The abbreviation `%+' refers\nto the current job and `%\\-' refers to the previous job.  For close\nanalogy with the syntax of the\n.I history\nmechanism (described below),\n`%%' is also a synonym for the current job.\n.sh \"Status reporting\"\nThis shell learns immediately whenever a process changes state.\nIt normally informs you whenever a job becomes blocked so that\nno further progress is possible, but only just before it prints\na prompt.  This is done so that it does not otherwise disturb your work.\nIf, however, you set the shell variable\n.I notify,\nthe shell will notify you immediately of changes of status in background\njobs.\nThere is also a shell command\n.I notify\nwhich marks a single process so that its status changes will be immediately\nreported.  By default \n.I notify\nmarks the current process;\nsimply say `notify' after starting a background job to mark it.\n.PP\nWhen you try to leave the shell while jobs are stopped, you will\nbe warned that `You have stopped jobs.'  You may use the \\fIjobs\\fR\ncommand to see what they are.  If you do this or immediately try to\nexit again, the shell will not warn you a second time, and the suspended\njobs will be terminated.\n.sh \"File Name Completion\"\nWhen the file name completion feature is enabled by setting\nthe shell variable \\fIfilec\\fP (see \\fBset\\fP), \\fIcsh\\fP will\ninteractively complete file names and user names from unique\nprefixes, when they are input from the terminal followed by\nthe escape character (the escape key, or control-[).  For example,\nif the current directory looks like\n.ta 1i 2i 3i 4i 5i 6i\n.nf\n\tDSC.OLD\tbin\tcmd\tlib\txmpl.c\n\tDSC.NEW\tchaosnet\tcmtest\tmail\txmpl.o\n\tbench\tclass\tdev\tmbox\txmpl.out\n.fi\nand the input is\n.br\n\t% vi ch<escape>\n.br\n\\fIcsh\\fP will complete the prefix ``ch''\nto the only matching file name ``chaosnet'', changing the input\nline to\n.br\n\t% vi chaosnet\n.br\nHowever, given\n.br\n\t% vi D<escape>\n.br\n\\fIcsh\\fP will only expand the input to\n.br\n\t% vi DSC.\n.br\nand will sound the terminal bell to indicate that the expansion is\nincomplete, since there are two file names matching the prefix ``D''.\n.PP\nIf a partial file name is followed by the end-of-file character\n(usually control-D), then, instead of completing the name, \\fIcsh\\fP\nwill list all file names matching the prefix.  For example,\nthe input\n.br\n\t% vi D<control-D>\n.br\ncauses all files beginning with ``D'' to be listed:\n.br\n\tDSC.NEW\tDSC.OLD\n.br\nwhile the input line remains unchanged.\n.PP\nThe same system of escape and end-of-file can also be used to\nexpand partial user names, if the word to be completed\n(or listed) begins with the character ``~''.  For example,\ntyping\n.br\n\tcd ~ro<control-D>\n.br\nmay produce the expansion\n.br\n\tcd ~root\n.PP\nThe use of the terminal bell to signal errors or multiple matches\ncan be inhibited by setting the variable \\fInobeep\\fP.\n.PP\nNormally, all files in the particular directory are candidates\nfor name completion.  Files with certain suffixes can be excluded\nfrom consideration by setting the variable \\fIfignore\\fP to the\nlist of suffixes to be ignored.  Thus, if \\fIfignore\\fP is set by\nthe command\n.br\n\t% set fignore = (.o .out)\n.br\nthen typing\n.br\n\t% vi x<escape>\n.br\nwould result in the completion to\n.br\n\t% vi xmpl.c\n.br\nignoring the files \"xmpl.o\" and \"xmpl.out\".\nHowever, if the only completion possible requires not ignoring these\nsuffixes, then they are not ignored.  In addition, \\fIfignore\\fP\ndoes not affect the listing of file names by control-D.  All files\nare listed regardless of their suffixes.\n.sh Substitutions\nWe now describe the various transformations the shell performs on the\ninput in the order in which they occur.\n.sh \"History substitutions\"\nHistory substitutions place words from previous command input as portions\nof new commands, making it easy to repeat commands, repeat arguments\nof a previous command in the current command, or fix spelling mistakes\nin the previous command with little typing and a high degree of confidence.\nHistory substitutions begin with the character `!' and may begin\n.B anywhere\nin the input stream (with the proviso that they\n.B \"do not\"\nnest.)\nThis `!' may be preceded by an `\\e' to prevent its special meaning; for\nconvenience, a `!' is passed unchanged when it is followed by a blank,\ntab, newline, `=' or `('.\n(History substitutions also occur when an input line begins with `\\*(ua'.\nThis special abbreviation will be described later.)\nAny input line which contains history substitution is echoed on the terminal\nbefore it is executed as it could have been typed without history substitution.\n.PP\nCommands input from the terminal which consist of one or more words\nare saved on the history list.\nThe history substitutions reintroduce sequences of words from these\nsaved commands into the input stream.\nThe size of which is controlled by the\n.I history\nvariable; the previous command is always retained, regardless of its value.\nCommands are numbered sequentially from 1.\n.PP\nFor definiteness, consider the following output from the\n.I history\ncommand:\n.PP\n.DT\n.br\n\t\\09  write michael\n.br\n\t10  ex write.c\n.br\n\t11  cat oldwrite.c\n.br\n\t12  diff *write.c\n.PP\nThe commands are shown with their event numbers.\nIt is not usually necessary to use event numbers, but the current event\nnumber can be made part of the\n.I prompt\nby placing an `!' in the prompt string.\n.PP\nWith the current event 13 we can refer to previous events by event\nnumber `!11', relatively as in `!\\-2' (referring to the same event),\nby a prefix of a command word\nas in `!d' for event 12 or `!wri' for event 9, or by a string contained in\na word in the command as in `!?mic?' also referring to event 9.\nThese forms, without further modification, simply reintroduce the words\nof the specified events, each separated by a single blank.\nAs a special case `!!' refers to the previous command; thus `!!'\nalone is essentially a\n.I redo.\n.PP\nTo select words from an event we can follow the event specification by\na `:' and a designator for the desired words.\nThe words of an input line are numbered from 0,\nthe first (usually command) word being 0, the second word (first argument)\nbeing 1, etc.\nThe basic word designators are:\n.PP\n.DT\n.nf\n\t0\tfirst (command) word\n\t\\fIn\\fR\t\\fIn\\fR\\|'th argument\n\t\\*(ua\tfirst argument,  i.e. `1'\n\t$\tlast argument\n\t%\tword matched by (immediately preceding) ?\\fIs\\fR\\|? search\n\t\\fIx\\fR\\|\\-\\fIy\\fR\trange of words\n\t\\-\\fIy\\fR\tabbreviates `0\\-\\fIy\\fR\\|'\n\t*\tabbreviates `\\*(ua\\-$', or nothing if only 1 word in event\n\t\\fIx\\fR\\|*\tabbreviates `\\fIx\\fR\\|\\-$'\n\t\\fIx\\fR\\|\\-\tlike `\\fIx\\fR\\|*' but omitting word `$'\n.fi\n.PP\nThe `:' separating the event specification from the word designator\ncan be omitted if the argument selector begins with a `\\*(ua', `$', `*'\n`\\-' or `%'.\nAfter the optional word designator can be\nplaced a sequence of modifiers, each preceded by a `:'.\nThe following modifiers are defined:\n.ta .5i 1.2i\n.PP\n.nf\n\th\tRemove a trailing pathname component, leaving the head.\n\tr\tRemove a trailing `.xxx' component, leaving the root name.\n\te\tRemove all but the extension `.xxx' part.\n\ts/\\fIl\\fR\\|/\\fIr\\fR\\|/\tSubstitute \\fIl\\fR for \\fIr\\fR\n\tt\tRemove all leading pathname components, leaving the tail.\n\t&\tRepeat the previous substitution.\n\tg\tApply the change globally, prefixing the above, e.g. `g&'.\n\tp\tPrint the new command but do not execute it.\n\tq\tQuote the substituted words, preventing further substitutions.\n\tx\tLike q, but break into words at blanks, tabs and newlines.\n.fi\n.PP\nUnless preceded by a `g' the modification is applied only to the first\nmodifiable word.  With substitutions, it is an error for no word to be\napplicable.\n.PP\nThe left hand side of substitutions are not regular expressions in the sense\nof the editors, but rather strings.\nAny character may be used as the delimiter in place of `/';\na `\\e' quotes the delimiter into the\n.IR l \"\"\nand\n.IR r \"\"\nstrings.\nThe character `&' in the right hand side is replaced by the text from\nthe left.\nA `\\e' quotes `&' also.\nA null\n.IR l \"\"\nuses the previous string either from a\n.IR l \"\"\nor from a\ncontextual scan string\n.IR s \"\"\nin `!?\\fIs\\fR\\|?'.\nThe trailing delimiter in the substitution may be omitted if a newline\nfollows immediately as may the trailing `?' in a contextual scan.\n.PP\nA history reference may be given without an event specification, e.g. `!$'.\nIn this case the reference is to the previous command unless a previous\nhistory reference occurred on the same line in which case this form repeats\nthe previous reference.\nThus `!?foo?\\*(ua !$' gives the first and last arguments\nfrom the command matching `?foo?'.\n.PP\nA special abbreviation of a history reference occurs when the first\nnon-blank character of an input line is a `\\*(ua'.\nThis is equivalent to `!:s\\*(ua' providing a convenient shorthand for substitutions\non the text of the previous line.\nThus `\\*(ualb\\*(ualib' fixes the spelling of \n`lib'\nin the previous command.\nFinally, a history substitution may be surrounded with `{' and `}'\nif necessary to insulate it from the characters which follow.\nThus, after `ls \\-ld ~paul' we might do `!{l}a' to do `ls \\-ld ~paula',\nwhile `!la' would look for a command starting `la'.\n.PP\n.if n .ul\n\\fBQuotations\\ with\\ \\'\\ and\\ \"\\fR\n.PP\nThe quotation of strings by `\\'' and `\"' can be used\nto prevent all or some of the remaining substitutions.\nStrings enclosed in `\\'' are prevented any further interpretation.\nStrings enclosed in `\"' may be expanded as described below.\n.PP\nIn both cases the resulting text becomes (all or part of) a single word;\nonly in one special case (see\n.I \"Command Substitition\"\nbelow) does a `\"' quoted string yield parts of more than one word;\n`\\'' quoted strings never do.\n.sh \"Alias substitution\"\nThe shell maintains a list of aliases which can be established, displayed\nand modified by the\n.I alias\nand\n.I unalias\ncommands.\nAfter a command line is scanned, it is parsed into distinct commands and\nthe first word of each command, left-to-right, is checked to see if it\nhas an alias.\nIf it does, then the text which is the alias for that command is reread\nwith the history mechanism available\nas though that command were the previous input line.\nThe resulting words replace the\ncommand and argument list.\nIf no reference is made to the history list, then the argument list is\nleft unchanged.\n.PP\nThus if the alias for `ls' is `ls \\-l' the command `ls /usr' would map to\n`ls \\-l /usr', the argument list here being undisturbed.\nSimilarly if the alias for `lookup' was `grep !\\*(ua /etc/passwd' then\n`lookup bill' would map to `grep bill /etc/passwd'.\n.PP\nIf an alias is found, the word transformation of the input text\nis performed and the aliasing process begins again on the reformed input line.\nLooping is prevented if the first word of the new text is the same as the old\nby flagging it to prevent further aliasing.\nOther loops are detected and cause an error.\n.PP\nNote that the mechanism allows aliases to introduce parser metasyntax.\nThus we can `alias print \\'pr \\e!* \\||\\| lpr\\'' to make a command which\n.I pr's\nits arguments to the line printer.\n.sh \"Variable substitution\"\nThe shell maintains a set of variables, each of which has as value a list\nof zero or more words.\nSome of these variables are set by the shell or referred to by it.\nFor instance, the\n.I argv\nvariable is an image of the shell's argument list, and words of this\nvariable's value are referred to in special ways.\n.PP\nThe values of variables may be displayed and changed by using the\n.I set\nand\n.I unset\ncommands.\nOf the variables referred to by the shell a number are toggles;\nthe shell does not care what their value is,\nonly whether they are set or not.\nFor instance, the\n.I verbose\nvariable is a toggle which causes command input to be echoed.\nThe setting of this variable results from the\n.B \\-v\ncommand line option.\n.PP\nOther operations treat variables numerically.\nThe `@' command permits numeric calculations to be performed and the result\nassigned to a variable.\nVariable values are, however, always represented as (zero or more) strings.\nFor the purposes of numeric operations, the null string is considered to be\nzero, and the second and subsequent words of multiword values are ignored.\n.PP\nAfter the input line is aliased and parsed, and before each command\nis executed, variable substitution\nis performed keyed by `$' characters.\nThis expansion can be prevented by preceding the `$' with a `\\e' except\nwithin `\"'s where it\n.B always\noccurs, and within `\\''s where it\n.B never\noccurs.\nStrings quoted by `\\*(ga' are interpreted later (see\n.I \"Command substitution\"\nbelow) so `$' substitution does not occur there until later, if at all.\nA `$' is passed unchanged if followed by a blank, tab, or end-of-line.\n.PP\nInput/output redirections are recognized before variable expansion,\nand are variable expanded separately.\nOtherwise, the command name and entire argument list are expanded together.\nIt is thus possible for the first (command) word to this point to generate\nmore than one word, the first of which becomes the command name,\nand the rest of which become arguments.\n.PP\nUnless enclosed in `\"' or given the `:q' modifier the results of variable\nsubstitution may eventually be command and filename substituted.\nWithin `\"', a variable whose value consists of multiple words expands to a\n(portion of) a single word, with the words of the variables value\nseparated by blanks.\nWhen the `:q' modifier is applied to a substitution\nthe variable will expand to multiple words with each word separated\nby a blank and quoted to prevent later command or filename substitution.\n.PP\nThe following metasequences are provided for introducing variable values into\nthe shell input.\nExcept as noted, it is an error to reference a variable which is not set.\n.HP 5\n$name\n.br\n.ns\n.HP 5\n${name}\n.br\nAre replaced by the words of the value of variable\n.I name,\neach separated by a blank.\nBraces insulate\n.I name\nfrom following characters which would otherwise be part of it.\nShell variables have names consisting of up to 20 letters and digits\nstarting with a letter.  The underscore character is considered a letter.\n.br\nIf\n.I name\nis not a shell variable, but is set in the environment, then\nthat value is returned (but \\fB:\\fR modifiers and the other forms\ngiven below are not available in this case).\n.HP 5\n$name[selector]\n.br\n.ns\n.HP 5\n${name[selector]}\n.br\nMay be used to select only some of the words from the value of\n.I name.\nThe selector is subjected to `$' substitution and may consist of a single\nnumber or two numbers separated by a `\\-'.\nThe first word of a variables value is numbered `1'.\nIf the first number of a range is omitted it defaults to `1'.\nIf the last member of a range is omitted it defaults to `$#name'.\nThe selector `*' selects all words.\nIt is not an error for a range to be empty if the second argument is omitted\nor in range.\n.HP 5\n$#name\n.br\n.ns\n.HP 5\n${#name}\n.br\nGives the number of words in the variable.\nThis is useful for later use in a `[selector]'.\n.HP 5\n$0\n.br\nSubstitutes the name of the file from which command input is being read.\nAn error occurs if the name is not known.\n.HP 5\n$number\n.br\n.ns\n.HP 5\n${number}\n.br\nEquivalent to `$argv[number]'.\n.HP 5\n$*\n.br\nEquivalent to `$argv[*]'.\n.PP\nThe modifiers `:h', `:t', `:r', `:q' and `:x' may be applied to\nthe substitutions above as may `:gh', `:gt' and `:gr'.\nIf braces `{' '}' appear in the command form then the modifiers\nmust appear within the braces.\n.B  \"The current implementation allows only one `:' modifier on each `$' expansion.\"\n.PP\nThe following substitutions may not be modified with `:' modifiers.\n.HP 5\n$?name\n.br\n.ns\n.HP 5\n${?name}\n.br\nSubstitutes the string `1' if name is set, `0' if it is not.\n.HP 5\n$?0\n.br\nSubstitutes `1' if the current input filename is known, `0' if it is not.\n.HP 5\n$$\n.br\nSubstitute the (decimal) process number of the (parent) shell.\n.HP 5\n$<\n.br\nSubstitutes a line from the standard\ninput, with no further interpretation thereafter.  It can be used\nto read from the keyboard in a shell script.\n.sh \"Command and filename substitution\"\nThe remaining substitutions, command and filename substitution,\nare applied selectively to the arguments of builtin commands.\nThis means that portions of expressions which are not evaluated are\nnot subjected to these expansions.\nFor commands which are not internal to the shell, the command\nname is substituted separately from the argument list.\nThis occurs very late,\nafter input-output redirection is performed, and in a child\nof the main shell.\n.sh \"Command substitution\"\nCommand substitution is indicated by a command enclosed in `\\*(ga'.\nThe output from such a command is normally broken into separate words\nat blanks, tabs and newlines, with null words being discarded,\nthis text then replacing the original string.\nWithin `\"'s, only newlines force new words; blanks and tabs are preserved.\n.PP\nIn any case, the single final newline does not force a new word.\nNote that it is thus possible for a command substitution to yield\nonly part of a word, even if the command outputs a complete line.\n.sh \"Filename substitution\"\nIf a word contains any of the characters `*', `?', `[' or `{'\nor begins with the character `~', then that word is a candidate for\nfilename substitution, also known as `globbing'.\nThis word is then regarded as a pattern, and replaced with an alphabetically\nsorted list of file names which match the pattern.\nIn a list of words specifying filename substitution it is an error for\nno pattern to match an existing file name, but it is not required\nfor each pattern to match.\nOnly the metacharacters `*', `?' and `[' imply pattern matching,\nthe characters `~' and `{' being more akin to abbreviations.\n.PP\nIn matching filenames, the character `.' at the beginning of a filename\nor immediately following a `/', as well as the character `/' must\nbe matched explicitly.\nThe character `*' matches any string of characters, including the null\nstring.\nThe character `?' matches any single character.\nThe sequence `[...]' matches any one of the characters enclosed.\nWithin `[...]',\na pair of characters separated by `\\-' matches any character lexically between\nthe two.\n.PP\nThe character `~' at the beginning of a filename is used to refer to home\ndirectories.\nStanding alone, i.e. `~' it expands to the invokers home directory as reflected\nin the value of the variable\n.I home.\nWhen followed by a name consisting of letters, digits and `\\-' characters\nthe shell searches for a user with that name and substitutes their\nhome directory;  thus `~ken' might expand to `/usr/ken' and `~ken/chmach'\nto `/usr/ken/chmach'.\nIf the character `~' is followed by a character other than a letter or `/'\nor appears not at the beginning of a word,\nit is left undisturbed.\n.PP\nThe metanotation `a{b,c,d}e' is a shorthand for `abe ace ade'.\nLeft to right order is preserved, with results of matches being sorted\nseparately at a low level to preserve this order.\nThis construct may be nested.\nThus `~source/s1/{oldls,ls}.c' expands to\n`/usr/source/s1/oldls.c /usr/source/s1/ls.c'\nwhether or not these files exist without any chance of error\nif the home directory for `source' is `/usr/source'.\nSimilarly `../{memo,*box}' might expand to `../memo ../box ../mbox'.\n(Note that `memo' was not sorted with the results of matching `*box'.)\nAs a special case `{', `}' and `{}' are passed undisturbed.\n.sh Input/output\nThe standard input and standard output of a command may be redirected\nwith the following syntax:\n.HP 5\n< name\n.br\nOpen file\n.I name\n(which is first variable, command and filename expanded) as the standard\ninput.\n.HP 5\n<< word\n.br\nRead the shell input up to a line which is identical to\n.I word.\n.I Word\nis not subjected to variable, filename or command substitution,\nand each input line is compared to\n.I word\nbefore any substitutions are done on this input line.\nUnless a quoting `\\e', `\"', `\\*(aa' or `\\*(ga' appears in\n.I word\nvariable and command substitution is performed on the intervening lines,\nallowing `\\e' to quote `$', `\\e' and `\\*(ga'.\nCommands which are substituted have all blanks, tabs, and newlines\npreserved, except for the final newline which is dropped.\nThe resultant text is placed in an anonymous temporary file which\nis given to the command as standard input.\n.HP 5\n> name\n.br\n.ns\n.HP 5\n>! name\n.br\n.ns\n.HP 5\n>& name\n.br\n.ns\n.HP 5\n>&! name\n.br\nThe file\n.I name\nis used as standard output.\nIf the file does not exist then it is created;\nif the file exists, its is truncated, its previous contents being lost.\n.IP\nIf the variable\n.I noclobber\nis set, then the file must not exist or be a character special file (e.g. a\nterminal or `/dev/null') or an error results.\nThis helps prevent accidental destruction of files.\nIn this case the `!' forms can be used and suppress this check.\n.IP\nThe forms involving `&' route the diagnostic output into the specified\nfile as well as the standard output.\n.I Name\nis expanded in the same way as `<' input filenames are.\n.HP 5\n>> name\n.br\n.ns\n.HP 5\n>>& name\n.br\n.ns\n.HP 5\n>>! name\n.br\n.ns\n.HP 5\n>>&! name\n.br\nUses file\n.I name\nas standard output like `>' but places output at the end of the file.\nIf the variable\n.I noclobber\nis set, then it is an error for the file not to exist unless\none of the `!' forms is given.\nOtherwise similar to `>'.\n.PP\nA command receives the environment in which the shell was\ninvoked as modified by the input-output parameters and\nthe presence of the command in a pipeline.\nThus, unlike some previous shells, commands run from a file of shell commands\nhave no access to the text of the commands by default; rather\nthey receive the original standard input of the shell.\nThe `<<' mechanism should be used to present inline data.\nThis permits shell command scripts to function as components of pipelines\nand allows the shell to block read its input.\nNote that the default standard input for a command run detached is\n.B not\nmodified to be the empty file `/dev/null'; rather the standard input\nremains as the original standard input of the shell.  If this is a terminal\nand if the process attempts to read from the terminal, then the process\nwill block and the user will be notified (see\n.B Jobs\nabove).\n.PP\nDiagnostic output may be directed through a pipe with the standard output.\nSimply use the form `|\\|&' rather than just `|'.\n.sh Expressions\nA number of the builtin commands (to be described subsequently)\ntake expressions, in which the operators are similar to those of C, with\nthe same precedence.\nThese expressions appear in the\n.I @,\n.I exit,\n.I if,\nand\n.I while\ncommands.\nThe following operators are available:\n.DT\n.PP\n\t|\\|\\||  &&  |  \\*(ua  &  ==  !=  =~  !~  <=  >=  <  >  <<  >>  +  \\-  *  /  %  !  ~  (  )\n.PP\nHere the precedence increases to the right,\n`==' `!=' `=~' and `!~', `<=' `>=' `<' and `>', `<<' and `>>', `+' and `\\-',\n`*' `/' and `%' being, in groups, at the same level.\nThe `==' `!=' `=~' and `!~' operators compare their arguments as strings;\nall others operate on numbers.\nThe operators `=~' and `!~' are like `!=' and `==' except that the right\nhand side is a\n.I pattern\n(containing, e.g. `*'s, `?'s and instances of `[...]')\nagainst which the left hand operand is matched.  This reduces the\nneed for use of the\n.I switch\nstatement in shell scripts when all that is really needed is pattern matching.\n.PP\nStrings which begin with `0' are considered octal numbers.\nNull or missing arguments are considered `0'.\nThe result of all expressions are strings,\nwhich represent decimal numbers.\nIt is important to note that no two components of an expression can appear\nin the same word; except when adjacent to components of expressions which\nare syntactically significant to the parser (`&' `|' `<' `>' `(' `)')\nthey should be surrounded by spaces.\n.PP\nAlso available in expressions as primitive operands are command executions\nenclosed in `{' and `}'\nand file enquiries of the form `\\-\\fIl\\fR  name' where\n.I  l\nis one of:\n.PP\n.DT\n.nf\n\tr\tread access\n\tw\twrite access\n\tx\texecute access\n\te\texistence\n\to\townership\n\tz\tzero size\n\tf\tplain file\n\td\tdirectory\n.fi\n.PP\nThe specified name is command and filename expanded and then tested\nto see if it has the specified relationship to the real user.\nIf the file does not exist or is inaccessible then all enquiries return\nfalse, i.e. `0'.\nCommand executions succeed, returning true, i.e. `1',\nif the command exits with status 0, otherwise they fail, returning\nfalse, i.e. `0'.\nIf more detailed status information is required then the command\nshould be executed outside of an expression and the variable\n.I status\nexamined.\n.sh \"Control flow\"\nThe shell contains a number of commands which can be used to regulate the\nflow of control in command files (shell scripts) and\n(in limited but useful ways) from terminal input.\nThese commands all operate by forcing the shell to reread or skip in its\ninput and, due to the implementation, restrict the placement of some\nof the commands.\n.PP\nThe\n.I foreach,\n.I switch,\nand\n.I while\nstatements, as well as the\n.I if\\-then\\-else\nform of the\n.I if\nstatement require that the major keywords appear in a single simple command\non an input line as shown below.\n.PP\nIf the shell's input is not seekable,\nthe shell buffers up input whenever a loop is being read\nand performs seeks in this internal buffer to accomplish the rereading\nimplied by the loop.\n(To the extent that this allows, backward goto's will succeed on\nnon-seekable inputs.)\n.sh \"Builtin commands\"\nBuiltin commands are executed within the shell.\nIf a builtin command occurs as any component of a pipeline\nexcept the last then it is executed in a subshell.\n.HP 5\n.B  alias\n.br\n.ns\n.HP 5\n.BR alias \" name\"\n.br\n.ns\n.HP 5\n.BR alias \" name wordlist\"\n.br\nThe first form prints all aliases.\nThe second form prints the alias for name.\nThe final form assigns the specified\n.I wordlist\nas the alias of \n.I name;\n.I wordlist\nis command and filename substituted.\n.I Name\nis not allowed to be\n.I alias\nor\n.I unalias.\n.HP 5\n.B  alloc\n.br\nShows the amount of dynamic memory acquired, broken down into used and\nfree memory.\nWith an argument shows the number of free and used blocks in each size\ncategory.  The categories start at size 8 and double at each step.\nThis command's output may vary across system types, since\nsystems other than the VAX may use a different memory allocator.\n.HP 5\n.B bg\n.br\n.ns\n.HP 5\n\\fBbg\\ %\\fRjob\\ ...\n.br\nPuts the current or specified jobs into the background, continuing them\nif they were stopped.\n.HP 5\n.B  break\n.br\nCauses execution to resume after the\n.I end\nof the nearest enclosing\n.I foreach\nor\n.I while.\nThe remaining commands on the current line are executed.\nMulti-level breaks are thus possible by writing them all on one line.\n.HP 5\n.B  breaksw\n.br\nCauses a break from a\n.I switch,\nresuming after the\n.I endsw.\n.HP 5\n.BR case \" label:\"\n.br\nA label in a\n.I switch\nstatement as discussed below.\n.HP 5\n.B  cd\n.br\n.ns\n.HP 5\n.BR cd \" name\"\n.br\n.ns\n.HP 5\n.B  chdir\n.br\n.ns\n.HP 5\n.BR chdir \" name\"\n.br\nChange the shell's working directory to directory\n.I name.\nIf no argument is given then change to the home directory of the user.\n.br\nIf\n.I name\nis not found as a subdirectory of the current directory (and does not begin\nwith `/', `./' or `../'), then each\ncomponent of the variable\n.I cdpath\nis checked to see if it has a subdirectory\n.I name.\nFinally, if all else fails but\n.I name\nis a shell variable whose value begins with `/', then this\nis tried to see if it is a directory.\n.HP 5\n.B  continue\n.br\nContinue execution of the nearest enclosing\n.I while\nor\n.I foreach.\nThe rest of the commands on the current line are executed.\n.HP 5\n.B  default:\n.br\nLabels the default case in a\n.I switch\nstatement.\nThe default should come after all\n.I case\nlabels.\n.HP 5\n.BR \"dirs\"\n.br\nPrints the directory stack; the top of the stack is at the left,\nthe first directory in the stack being the current directory.\n.HP 5\n.BR echo \" wordlist\"\n.br\n.ns\n.HP 5\n.BR \"echo \\-n\" \" wordlist\"\n.br\nThe specified words are written to the shells standard output, separated\nby spaces, and terminated with a newline unless the\n.B \\-n\noption is specified.\n.HP 5\n.B  else\n.br\n.ns\n.HP 5\n.B  end\n.br\n.ns\n.HP 5\n.B  endif\n.br\n.ns\n.HP 5\n.B  endsw\n.br\nSee the description of the\n.I foreach,\n.I if,\n.I switch,\nand\n.I while\nstatements below.\n.HP 5\n.BR eval \" arg ...\"\n.br\n(As in\n.IR sh (1).)\nThe arguments are read as input to the shell and the resulting\ncommand(s) executed in the context of the current shell.\nThis is usually used to execute commands\ngenerated as the result of command or variable substitution, since\nparsing occurs before these substitutions.  See\n.IR tset (1)\nfor an example of using\n.IR eval .\n.HP 5\n.BR exec \" command\"\n.br\nThe specified command is executed in place of the current shell.\n.HP 5\n.B  exit\n.br\n.ns\n.HP 5\n.BR exit (expr)\n.br\nThe shell exits either with the value of the\n.I status\nvariable (first form) or with the value of the specified\n.I  expr\n(second form).\n.HP 5\n.B fg\n.br\n.ns\n.HP 5\n\\fBfg\\ %\\fRjob\\ ...\n.br\nBrings the current or specified jobs into the foreground, continuing them if\nthey were stopped.\n.HP 5\n.BR foreach \" name (wordlist)\"\n.br\n.ns\n.HP 5\n\\    ...\n.br\n.ns\n.HP 5\n.B  end\n.br\nThe variable\n.I name\nis successively set to each member of\n.I wordlist\nand the sequence of commands between this command and the matching\n.I end\nare executed.\n(Both\n.I foreach\nand\n.I end\nmust appear alone on separate lines.)\n.IP\nThe builtin command\n.I continue\nmay be used to continue the loop prematurely and the builtin\ncommand\n.I break\nto terminate it prematurely.\nWhen this command is read from the terminal, the loop is read up once\nprompting with `?' before any statements in the loop are executed.\nIf you make a mistake typing in a loop at the terminal you can rub it out.\n.HP 5\n.BR glob \" wordlist\"\n.br\nLike\n.I echo\nbut no `\\e' escapes are recognized and words are delimited\nby null characters in the output.\nUseful for programs which wish to use the shell to filename expand a list\nof words.\n.HP 5\n.BR goto \" word\"\n.br\nThe specified\n.I word\nis filename and command expanded to yield a string of the form `label'.\nThe shell rewinds its input as much as possible\nand searches for a line of the form `label:'\npossibly preceded by blanks or tabs.\nExecution continues after the specified line.\n.HP 5\n.BR hashstat\n.br\nPrint a statistics line indicating how effective the internal hash\ntable has been at locating commands (and avoiding\n.IR exec 's).\nAn\n.I exec\nis attempted for each component of the\n.I path\nwhere the hash function indicates a possible hit, and in each component\nwhich does not begin with a `/'.\n.HP 5\n.B  history\n.br\n.ns\n.HP 5\n.BI history \" n\"\n.br\n.ns\n.HP 5\n.BI \"history \\-r\" \" n\"\n.br\n.ns\n.HP 5\n.BI \"history \\-h\" \" n\"\n.br\nDisplays the history event list; if \\fIn\\fR is given only the\n.I n\nmost recent events are printed.\nThe\n.B \\-r\noption reverses the order of printout to be most recent first\nrather than oldest first.\nThe\n.B \\-h\noption causes the history list to be printed without leading numbers.\nThis is used to produce files suitable for sourceing using the \\-h\noption to\n.IR source .\n.HP 5\n.BR if \" (expr) command\"\n.br\nIf the specified expression evaluates true, then the single\n.I  command\nwith arguments is executed.\nVariable substitution on\n.IR command \"\"\nhappens early, at the same\ntime it does for the rest of the\n.I if\ncommand.\n.I Command\nmust be a simple command, not\na pipeline, a command list, or a parenthesized command list.\nInput/output redirection occurs even if\n.I expr\nis false, when command is\n.B not\nexecuted (this is a bug).\n.HP 5\n.BR if \" (expr) \" \"then\"\n.br\n.ns\n.HP 5\n\\    ...\n.br\n.ns\n.HP 5\n.BR else \" \" \"if\\fR (expr2) \\fBthen\"\n.br\n.ns\n.HP 5\n\\    ...\n.br\n.ns\n.HP 5\n.B  else\n.br\n.ns\n.HP 5\n\\    ...\n.br\n.ns\n.HP 5\n.B  endif\n.br\nIf the specified\n.IR expr \"\"\nis true then the commands to the first\n.I else\nare executed; otherwise if\n.IR expr2 \"\"\nis true then the commands to the\nsecond \\fIelse\\fR are executed, etc.\nAny number of\n.I else-if\npairs are possible; only one\n.I endif\nis needed.\nThe\n.I else\npart is likewise optional.\n(The words\n.I else\nand\n.I endif\nmust appear at the beginning of input lines;\nthe\n.I if\nmust appear alone on its input line or after an\n.I else.)\n.HP 5\n.B jobs\n.br\n.ns\n.HP 5\n.B \"jobs \\-l\"\n.br\nLists the active jobs; given the\n.B \\-l\noptions lists process id's in addition to the normal information.\n.HP 5\n\\fBkill %\\fRjob\n.br\n.ns\n.HP 5\n\\fBkill\\ \\-\\fRsig\\ \\fB%\\fRjob\\ ...\n.br\n.ns\n.HP 5\n\\fBkill\\fR\\ pid\n.br\n.ns\n.HP 5\n\\fBkill\\ \\-\\fRsig\\ pid\\ ...\n.br\n.ns\n.HP 5\n\\fBkill\\ \\-l\\fR\n.br\nSends either the TERM (terminate) signal or the\nspecified signal to the specified jobs or processes.\nSignals are either given by number or by names (as given in\n.I /usr/include/signal.h,\nstripped of the prefix ``SIG'').\nThe signal names are listed by ``kill \\-l''.\nThere is no default, saying just `kill' does not\nsend a signal to the current job.\nIf the signal being sent is TERM (terminate) or HUP (hangup),\nthen the job or process will be sent a CONT (continue) signal as well.\n.HP\n\\fBlimit\\fR\n.br\n.ns\n.HP 5\n\\fBlimit\\fR \\fIresource\\fR\n.br\n.ns\n.HP 5\n\\fBlimit\\fR \\fIresource\\fR \\fImaximum-use\\fR\n.br\n.ns\n.HP 5\n\\fBlimit\\ \\-h\\fR\n.br\n.ns\n.HP 5\n\\fBlimit\\ \\-h\\fR \\fIresource\\fR\n.br\n.ns\n.HP 5\n\\fBlimit\\ \\-h\\fR \\fIresource\\fR \\fImaximum-use\\fR\n.br\nLimits the consumption by the current process and each process\nit creates to not individually exceed \\fImaximum-use\\fR on the\nspecified \\fIresource\\fR.  If no \\fImaximum-use\\fR is given, then\nthe current limit is printed; if no \\fIresource\\fR is given, then\nall limitations are given.  If the \\fB\\-h\\fR\nflag is given, the hard limits are used instead of the current\nlimits.  The hard limits impose a ceiling on the values of\nthe current limits.  Only the super-user may raise the hard limits,\nbut a user may lower or raise the current limits within the legal range.\n.IP\nResources controllable currently include \\fIcputime\\fR (the maximum\nnumber of cpu-seconds to be used by each process), \\fIfilesize\\fR\n(the largest single file which can be created), \\fIdatasize\\fR\n(the maximum growth of the data+stack region via\n.IR sbrk (2)\nbeyond the end of the program text), \\fIstacksize\\fR (the maximum\nsize of the automatically-extended stack region), and \\fIcoredumpsize\\fR\n(the size of the largest core dump that will be created).\n.IP\nThe \\fImaximum-use\\fR may be given as a (floating point or integer)\nnumber followed by a scale factor.  For all limits other than \\fIcputime\\fR\nthe default scale is `k' or `kilobytes' (1024 bytes);\na scale factor of `m' or `megabytes' may also be used.\nFor\n.I cputime\nthe default scaling is `seconds', while `m' for minutes\nor `h' for hours, or a time of the form `mm:ss' giving minutes\nand seconds may be used.\n.IP\nFor both \\fIresource\\fR names and scale factors, unambiguous prefixes\nof the names suffice.\n.HP 5\n.B  login\n.br\nTerminate a login shell, replacing it with an instance of\n.B /bin/login.\nThis is one way to log off, included for compatibility with\n.IR sh (1).\n.HP 5\n.B  logout\n.br\nTerminate a login shell.\nEspecially useful if\n.I ignoreeof\nis set.\n.HP 5\n.B  nice\n.br\n.ns\n.HP 5\n.BR nice \" +number\"\n.br\n.ns\n.HP 5\n.BR nice \" command\"\n.br\n.ns\n.HP 5\n.BR nice \" +number command\"\n.br\nThe first form sets the\nscheduling priority\nfor this shell to 4.\nThe second form sets the\npriority\nto the given number.\nThe final two forms run command at priority 4 and\n.I number\nrespectively.\nThe greater the number, the less cpu the process will get.\nThe super-user may specify negative priority by using `nice \\-number ...'.\nCommand is always executed in a sub-shell, and the restrictions\nplaced on commands in simple\n.I if\nstatements apply.\n.HP 5\n.B  nohup\n.br\n.ns\n.HP 5\n.BR \"nohup\" \" command\"\n.br\nThe first form can be used in shell scripts to cause hangups to be\nignored for the remainder of the script.\nThe second form causes the specified command to be run with hangups\nignored.\nAll processes detached with `&' are effectively\n.I nohup'ed.\n.HP 5\n.B notify\n.br\n.ns\n.HP 5\n\\fBnotify\\ %\\fRjob\\ ...\n.br\nCauses the shell to notify the user asynchronously when the status of the\ncurrent or specified jobs changes; normally notification is presented\nbefore a prompt.  This is automatic if the shell variable\n.I notify\nis set.\n.HP 5\n.B  onintr\n.br\n.ns\n.HP 5\n.BR onintr \"  \\-\"\n.br\n.ns\n.HP 5\n.BR onintr \"  label\"\n.br\nControl the action of the shell on interrupts.\nThe first form restores the default action of the shell on interrupts\nwhich is to terminate shell scripts or to return to the terminal command\ninput level.\nThe second form `onintr \\-' causes all interrupts to be ignored.\nThe final form causes the shell to execute a `goto label' when\nan interrupt is received or a child process terminates because\nit was interrupted.\n.IP\nIn any case, if the shell is running detached and interrupts are\nbeing ignored, all forms of\n.I onintr\nhave no meaning and interrupts\ncontinue to be ignored by the shell and all invoked commands.\n.HP 5\n.BR \"popd\"\n.br\n.ns\n.HP 5\n.BR \"popd\" \" +n\"\n.br\nPops the directory stack, returning to the new top directory.\nWith an argument `+\\fIn\\fR' discards the \\fIn\\fR\\|th\nentry in the stack.\nThe elements of the directory stack are numbered from 0 starting at the top.\n.HP 5\n.BR \"pushd\"\n.br\n.ns\n.HP 5\n.BR \"pushd\" \" name\"\n.br\n.ns\n.HP 5\n.BR \"pushd\" \" +n\"\n.br\nWith no arguments,\n.I pushd\nexchanges the top two elements of the directory stack.\nGiven a\n.I name\nargument,\n.I pushd\nchanges to the new directory (ala\n.I cd)\nand pushes the old current working directory\n(as in\n.I csw)\nonto the directory stack.\nWith a numeric argument, rotates the \\fIn\\fR\\|th argument of the directory\nstack around to be the top element and changes to it.  The members\nof the directory stack are numbered from the top starting at 0.\n.HP 5\n.BR rehash\n.br\nCauses the internal hash table of the contents of the directories in\nthe\n.I path\nvariable to be recomputed.  This is needed if new commands are added\nto directories in the\n.I path\nwhile you are logged in.  This should only be necessary if you add\ncommands to one of your own directories, or if a systems programmer\nchanges the contents of one of the system directories.\n.HP 5\n.BR repeat \" count command\"\n.br\nThe specified \n.I command\nwhich is subject to the same restrictions\nas the\n.I command\nin the one line\n.I if\nstatement above,\nis executed\n.I count\ntimes.\nI/O redirections occur exactly once, even if\n.I count\nis 0.\n.HP 5\n.B  set\n.br\n.ns\n.HP 5\n.BR set \" name\"\n.br\n.ns\n.HP 5\n.BR set \" name=word\"\n.br\n.ns\n.HP 5\n.BR set \" name[index]=word\"\n.br\n.ns\n.HP 5\n.BR set \" name=(wordlist)\"\n.br\nThe first form of the command shows the value of all shell variables.\nVariables which have other than a single word as value print as a parenthesized\nword list.\nThe second form sets\n.I name\nto the null string.\nThe third form sets\n.I name\nto the single\n.I word.\nThe fourth form sets\nthe\n.I index'th\ncomponent of name to word;\nthis component must already exist.\nThe final form sets\n.I name\nto the list of words in\n.I wordlist.\nIn all cases the value is command and filename expanded.\n.IP\nThese arguments may be repeated to set multiple values in a single set command.\nNote however, that variable expansion happens for all arguments before any\nsetting occurs.\n.HP 5\n.BR setenv\n.br\n.ns\n.HP 5\n.BR setenv \" name value\"\n.br\n.ns\n.HP 5\n.BR setenv \" name\"\n.br\nThe first form lists all current environment variables.\nThe last form sets the value of environment variable\n.I name\nto be\n.I value,\na single string.  The second form sets\n.I name\nto an empty string.\nThe most commonly used environment variable USER, TERM, and PATH\nare automatically imported to and exported from the\n.I csh\nvariables\n.I user,\n.I term,\nand\n.I path;\nthere is no need to use\n.I setenv\nfor these.\n.HP 5\n.B  shift\n.br\n.ns\n.HP 5\n.BR shift \" variable\"\n.br\nThe members of\n.I argv\nare shifted to the left, discarding\n.I argv[1].\nIt is an error for\n.I argv\nnot to be set or to have less than one word as value.\nThe second form performs the same function on the specified variable.\n.HP 5\n.BR source \" name\"\n.br\n.ns\n.HP 5\n.BR \"source \\-h\" \" name\"\n.br\nThe shell reads commands from\n.I name.\n.I Source\ncommands may be nested; if they are nested too deeply the shell may\nrun out of file descriptors.\nAn error in a\n.I source\nat any level terminates all nested\n.I source\ncommands.\nNormally input during \n.I source\ncommands is not placed on the history list;\nthe \\-h option causes the commands to be placed in the\nhistory list without being executed.\n.HP 5\n.B stop\n.br\n.ns\n.HP 5\n\\fBstop\\ %\\fRjob\\ ...\n.br\nStops the current or specified job which is executing in the background.\n.HP 5\n.B suspend\n.br\n.ns\nCauses the shell to stop in its tracks, much as if it had been sent a stop\nsignal with \\fB^Z\\fR.  This is most often used to stop shells started by\n.IR su (1).\n.HP 5\n.BR switch \" (string)\"\n.br\n.ns\n.HP 5\n.BR case \" str1:\"\n.br\n.ns\n.HP 5\n\\    ...\n.br\n.ns\n.HP 5\n\\   \n.B  breaksw\n.br\n.ns\n.HP 5\n\\&...\n.br\n.ns\n.HP 5\n.B  default:\n.br\n.ns\n.HP 5\n\\    ...\n.br\n.ns\n.HP 5\n\\   \n.B  breaksw\n.br\n.ns\n.HP 5\n.B  endsw\n.br\nEach case label is successively matched, against the specified\n.I string\nwhich is first command and filename expanded.\nThe file metacharacters `*', `?' and `[...]' may be used in the case labels,\nwhich are variable expanded.\nIf none of the labels match before a `default' label is found, then\nthe execution begins after the default label.\nEach case label and the default label must appear at the beginning of a line.\nThe command \n.I breaksw\ncauses execution to continue after the\n.I endsw.\nOtherwise control may fall through case labels and default labels as in C.\nIf no label matches and there is no default, execution continues after\nthe\n.I endsw.\n.HP 5\n.B  time\n.br\n.ns\n.HP 5\n.BR time \" command\"\n.br\nWith no argument, a summary of time used by this shell and its children\nis printed.\nIf arguments are given\nthe specified simple command is timed and a time summary\nas described under the\n.I time\nvariable is printed.  If necessary, an extra shell is created to print the time\nstatistic when the command completes.\n.HP 5\n.B umask\n.br\n.ns\n.HP 5\n.BR umask \" value\"\n.br\nThe file creation mask is displayed (first form) or set to the specified\nvalue (second form).  The mask is given in octal.  Common values for\nthe mask are 002 giving all access to the group and read and execute\naccess to others or 022 giving all access except no write access for\nusers in the group or others.\n.HP 5\n.BR unalias \" pattern\"\n.br\nAll aliases whose names match the specified pattern are discarded.\nThus all aliases are removed by `unalias *'.\nIt is not an error for nothing to be\n.I unaliased.\n.HP 5\n.BR unhash\n.br\nUse of the internal hash table to speed location of executed programs\nis disabled.\n.HP 5\n\\fBunlimit\\fR\n.br\n.ns\n.HP 5\n\\fBunlimit\\fR \\fIresource\\fR\n.br\n.ns\n.HP 5\n\\fBunlimit\\ \\-h\\fR\n.br\n.ns\n.HP 5\n\\fBunlimit\\ \\-h\\fR \\fIresource\\fR\n.br\nRemoves the limitation on \\fIresource\\fR.  If no \\fIresource\\fR\nis specified, then all \\fIresource\\fR limitations are removed.  If\n\\fB\\-h\\fR is given, the corresponding hard limits are removed.  Only the\nsuper-user may do this.\n.HP 5\n.BR unset \" pattern\"\n.br\nAll variables whose names match the specified pattern are removed.\nThus all variables are removed by `unset *'; this has noticeably\ndistasteful side-effects.\nIt is not an error for nothing to be\n.I unset.\n.HP 5\n.BR unsetenv \" pattern\"\n.br\nRemoves all variables whose name match the specified pattern from the\nenvironment.  See also the\n.I setenv\ncommand above and\n.IR printenv (1).\n.HP 5\n.B  wait\n.br\nAll background jobs are waited for.\nIt the shell is interactive, then an interrupt can disrupt the wait,\nat which time the shell prints names and job numbers of all jobs\nknown to be outstanding.\n.HP 5\n.BR while \" (expr)\"\n.br\n.ns\n.HP 5\n\\    ...\n.br\n.ns\n.HP 5\n.B  end\n.br\nWhile the specified expression evaluates non-zero, the commands between\nthe\n.I while\nand the matching end are evaluated.\n.I Break\nand\n.I continue\nmay be used to terminate or continue the loop prematurely.\n(The\n.I while\nand\n.I end\nmust appear alone on their input lines.)\nPrompting occurs here the first time through the loop as for the\n.I foreach\nstatement if the input is a terminal.\n.HP 5\n\\fB%\\fRjob\n.br\nBrings the specified job into the foreground.\n.HP 5\n\\fB%\\fRjob \\fB&\\fR\n.br\nContinues the specified job in the background.\n.HP 5\n.B \"@\"\n.br\n.ns\n.HP 5\n.BR \"@\" \" name = expr\"\n.br\n.ns\n.HP 5\n.BR \"@\" \" name[index] = expr\"\n.br\nThe first form prints the values of all the shell variables.\nThe second form sets the specified\n.I name\nto the value of\n.I expr.\nIf the expression contains `<', `>', `&' or `|' then at least\nthis part of the expression must be placed within `(' `)'.\nThe third form assigns the value of\n.I expr\nto the\n.I index'th\nargument of\n.I name.\nBoth \n.I name\nand its\n.I index'th\ncomponent must already exist.\n.IP\nThe operators `*=', `+=', etc are available as in C.\nThe space separating the name from the assignment operator is optional.\nSpaces are, however, mandatory in separating components of\n.I expr\nwhich would otherwise be single words.\n.IP\nSpecial postfix `++' and `\\-\\|\\-' operators increment and decrement\n.I name\nrespectively, i.e. `@  i++'.\n.sh \"Pre-defined and environment variables\"\nThe following variables have special meaning to the shell.\nOf these,\n.I argv,\n.I cwd,\n.I home,\n.I path,\n.I prompt,\n.I shell\nand\n.I status\nare always set by the shell.\nExcept for\n.I cwd\nand\n.I status\nthis setting occurs only at initialization;\nthese variables will not then be modified unless this is done\nexplicitly by the user.\n.PP\nThis shell copies the environment variable USER into the variable\n.I user,\nTERM into\n.I term,\nand\nHOME into\n.I home,\nand copies these back into the environment whenever the normal\nshell variables are reset.\nThe environment variable PATH is likewise handled; it is not\nnecessary to worry about its setting other than in the file\n.I \\&.cshrc\nas inferior\n.I csh\nprocesses will import the definition of\n.I path\nfrom the environment, and re-export it if you then change it.\n.TP 15\n.B argv\n\\c\nSet to the arguments to the shell, it is from this variable that\npositional parameters are substituted, i.e. `$1' is replaced by\n`$argv[1]', etc.\n.TP 15\n.B cdpath\n\\c\nGives a list of alternate directories searched to find subdirectories\nin\n.I chdir\ncommands.\n.TP 15\n.B cwd\nThe full pathname of the current directory.\n.TP 15\n.B echo\n\\c\nSet when the\n.B \\-x\ncommand line option is given.\nCauses each command and its arguments\nto be echoed just before it is executed.\nFor non-builtin commands all expansions occur before echoing.\nBuiltin commands are echoed before command and filename substitution,\nsince these substitutions are then done selectively.\n.TP 15\n.B filec\nEnable file name completion.\n\\c\n.TP 15\n.B histchars\n\\c\nCan be given a string value to change the characters used in history\nsubstitution.  The first character of its value is used as the\nhistory substitution character, replacing the default character !.\nThe second character of its value replaces the character \\(ua in\nquick substitutions.\n.TP 15\n.B history\n\\c\nCan be given a numeric value to control the size of the history list.\nAny command which has been referenced in this many events will not be\ndiscarded.\nToo large values of\n.I history\nmay run the shell out of memory.\nThe last executed command is always saved on the history list.\n.TP 15\n.B home\n\\c\nThe home directory of the invoker, initialized from the environment.\nThe filename expansion of `\\fB~\\fR' refers to this variable.\n.TP 15\n.B ignoreeof\n\\c\nIf set the shell ignores\nend-of-file from input devices which are terminals.\nThis prevents shells from accidentally being killed by control-D's.\n.TP 15\n.B mail\n\\c\nThe files where the shell checks for mail.\nThis is done after each command completion which will result in a prompt,\nif a specified interval has elapsed.\nThe shell says `You have new mail.'\nif the file exists with an access time not greater than its modify time.\n.IP\nIf the first word of the value of\n.I mail\nis numeric it specifies a different mail checking interval, in seconds,\nthan the default, which is 10 minutes.\n.IP\nIf multiple mail files are specified, then the shell says\n`New mail in\n.IR name '\nwhen there is mail in the file\n.I name.\n.TP 15\n.B noclobber\n\\c\nAs described in the section on\n.I Input/output,\nrestrictions are placed on output redirection to insure that\nfiles are not accidentally destroyed, and that `>>' redirections\nrefer to existing files.\n.TP 15\n.B noglob\n\\c\nIf set, filename expansion is inhibited.\nThis is most useful in shell scripts which are not dealing with filenames,\nor after a list of filenames has been obtained and further expansions\nare not desirable.\n.TP 15\n.B nonomatch\n\\c\nIf set, it is not an error for a filename expansion to not match any\nexisting files; rather the primitive pattern is returned.\nIt is still an error for the primitive pattern to be malformed, i.e.\n`echo [' still gives an error.\n.TP 15\n.B notify\n\\c\nIf set, the shell notifies asynchronously of job completions.  The\ndefault is to rather present job completions just before printing\na prompt.\n.TP 15\n.B path\n\\c\nEach word of the path variable specifies a directory in which\ncommands are to be sought for execution.\nA null word specifies the current directory.\nIf there is no\n.I path\nvariable then only full path names will execute.\nThe usual search path is `.', `/bin' and `/usr/bin', but this\nmay vary from system to system.\nFor the super-user the default search path is `/bin', `/sbin', `/usr/sbin',\nand `/usr/bin'.\nA shell which is given neither the\n.B \\-c\nnor the\n.B \\-t\noption will normally hash the contents of the directories in the\n.I path\nvariable after reading\n.I \\&.cshrc,\nand each time the\n.I path\nvariable is reset.  If new commands are added to these directories\nwhile the shell is active, it may be necessary to give the\n.I rehash\nor the commands may not be found.\n.TP 15\n.B prompt\n\\c\nThe string which is printed before each command is read from\nan interactive terminal input.\nIf a `!' appears in the string it will be replaced by the current event number\nunless a preceding `\\e' is given.\nDefault is `% ', or `# ' for the super-user.\n.TP 15\n.B savehist\n\\c\nis given a numeric value to control the number of entries of the\nhistory list that are saved in ~/.history when the user logs out.\nAny command which has been referenced in this many events will be saved.\nDuring start up the shell sources ~/.history into the history list\nenabling history to be saved across logins.\nToo large values of\n.I savehist\nwill slow down the shell during start up.\n.TP 15\n.B shell\n\\c\nThe file in which the shell resides.\nThis is used in forking shells to interpret files which have execute\nbits set, but which are not executable by the system.\n(See the description of\n.I \"Non-builtin Command Execution\"\nbelow.)\nInitialized to the (system-dependent) home of the shell.\n.TP 15\n.B status\n\\c\nThe status returned by the last command.\nIf it terminated abnormally, then 0200 is added to the status.\nBuiltin commands which fail return exit status `1',\nall other builtin commands set status `0'.\n.TP 15\n.B time\n\\c\nControls automatic timing of commands.\nIf set, then any command which takes more than this many cpu seconds\nwill cause a line giving user, system, and real times and a utilization\npercentage which is the ratio of user plus system times to real time\nto be printed when it terminates.\n.TP 15\n.B verbose\n\\c\nSet by the\n.B \\-v\ncommand line option, causes the words of each command to be printed\nafter history substitution.\n.sh \"Non-builtin command execution\"\nWhen a command to be executed is found to not be a builtin command\nthe shell attempts to execute the command via\n.IR  execve (2).\nEach word in the variable\n.I path\nnames a directory from which the shell will attempt to execute the command.\nIf it is given neither a\n.B \\-c\nnor a\n.B \\-t\noption, the shell will hash the names in these directories into an internal\ntable so that it will only try an\n.I exec\nin a directory if there is a possibility that the command resides there.\nThis greatly speeds command location when a large number of directories\nare present in the search path.\nIf this mechanism has been turned off (via\n.IR unhash ),\nor if the shell was given a\n.B \\-c\nor\n.B \\-t\nargument, and in any case for each directory component of\n.I path\nwhich does not begin with a `/',\nthe shell concatenates with the given command name to form a path name\nof a file which it then attempts to execute.\n.PP\nParenthesized commands are always executed in a subshell.\nThus `(cd ; pwd) ; pwd' prints the\n.I home\ndirectory; leaving you where you were (printing this after the home directory),\nwhile `cd ; pwd' leaves you in the\n.I home\ndirectory.\nParenthesized commands are most often used to prevent\n.I chdir\nfrom affecting the current shell.\n.PP\nIf the file has execute permissions but is not an\nexecutable binary to the system, then it is assumed to be a\nfile containing shell commands and a new shell is spawned to read it.\n.PP\nIf there is an\n.I alias\nfor\n.I shell\nthen the words of the alias will be prepended to the argument list to form\nthe shell command.\nThe first word of the\n.I alias\nshould be the full path name of the shell\n(e.g. `$shell').\nNote that this is a special, late occurring, case of\n.I alias\nsubstitution,\nand only allows words to be prepended to the argument list without modification.\n.sh \"Argument list processing\"\nIf argument 0 to the shell is `\\-' then this\nis a login shell.\nThe flag arguments are interpreted as follows:\n.TP 5\n.B  \\-b\n\\c\nThis flag forces a ``break'' from option processing, causing any further\nshell arguments to be treated as non-option arguments.\nThe remaining arguments will not be interpreted as shell options.\nThis may be used to pass options to a shell script without confusion\nor possible subterfuge.\nThe shell will not run a set-user ID script without this option.\n.TP 5\n.B  \\-c\n\\c\nCommands are read from the (single) following argument which must\nbe present.\nAny remaining arguments are placed in\n.I argv.\n.TP 5\n.B  \\-e\n\\c\nThe shell exits if any invoked command terminates abnormally\nor yields a non-zero exit status.\n.TP 5\n.B  \\-f\n\\c\nThe shell will start faster, because it will neither search for nor\nexecute commands from the file\n`\\&.cshrc' in the invoker's home directory.\n.TP 5\n.B  \\-i\n\\c\nThe shell is interactive and prompts for its top-level input,\neven if it appears to not be a terminal.\nShells are interactive without this option if their inputs\nand outputs are terminals.\n.TP 5\n.B  \\-n\n\\c\nCommands are parsed, but not executed.\nThis aids in syntactic checking of shell scripts.\n.TP 5\n.B  \\-s\n\\c\nCommand input is taken from the standard input.\n.TP 5\n.B  \\-t\n\\c\nA single line of input is read and executed.\nA `\\e' may be used to escape the newline at the end of this\nline and continue onto another line.\n.TP 5\n.B  \\-v\n\\c\nCauses the\n.I verbose\nvariable to be set, with the effect\nthat command input is echoed after history substitution.\n.TP 5\n.B  \\-x\n\\c\nCauses the \n.I echo\nvariable to be set, so that commands are echoed immediately before execution.\n.TP 5\n.B  \\-V\n\\c\nCauses the\n.I verbose\nvariable to be set even before `\\&.cshrc' is executed.\n.TP 5\n.B  \\-X\n\\c\nIs to\n.B \\-x\nas\n.B \\-V\nis to\n.B \\-v.\n.PP\nAfter processing of flag arguments, if arguments remain but none of the\n.B \\-c,\n.B \\-i,\n.B \\-s,\nor\n.B \\-t\noptions was given, the first argument is taken as the name of a file of\ncommands to be executed.\nThe shell opens this file, and saves its name for possible resubstitution\nby `$0'.\nSince many systems use either the standard version 6 or version 7 shells\nwhose shell scripts are not compatible with this shell, the shell will\nexecute such a `standard' shell if the first character of a script\nis not a `#', i.e. if the script does not start with a comment.\nRemaining arguments initialize the variable\n.I argv.\n.sh \"Signal handling\"\nThe shell normally ignores\n.I quit\nsignals.\nJobs running detached (either by `&' or the \\fIbg\\fR or \\fB%... &\\fR\ncommands) are immune to signals generated from the keyboard, including\nhangups.\nOther signals have the values which the shell inherited from its parent.\nThe shells handling of interrupts and terminate signals\nin shell scripts can be controlled by\n.I onintr.\nLogin shells catch the\n.I terminate\nsignal; otherwise this signal is passed on to children from the state in the\nshell's parent.\nIn no case are interrupts allowed when a login shell is reading the file\n`\\&.logout'.\n.SH AUTHOR\nWilliam Joy.\nJob control and directory stack features first implemented by J.E. Kulp of\nI.I.A.S.A, Laxenburg, Austria,\nwith different syntax than that used now.  File name completion\ncode written by Ken Greer, HP Labs.\n.SH FILES\n.ta 1.75i\n.nf\n~/.cshrc\tRead at beginning of execution by each shell.\n~/.login\tRead by login shell, after `.cshrc' at login.\n~/.logout\tRead by login shell, at logout.\n/bin/sh\tStandard shell, for shell scripts not starting with a `#'.\n/tmp/sh*\tTemporary file for `<<'.\n/etc/passwd\tSource of home directories for `~name'.\n.fi\n.SH LIMITATIONS\nWords can be no longer than 1024 characters.\nThe system limits argument lists to 10240 characters.\nThe number of arguments to a command which involves filename expansion\nis limited to 1/6'th the number of characters allowed in an argument list.\nCommand substitutions may substitute no more characters than are\nallowed in an argument list.\nTo detect looping, the shell restricts the number of\n.I alias\nsubstitutions on a single line to 20.\n.SH \"SEE ALSO\"\nsh(1), access(2), execve(2), fork(2), killpg(2), pipe(2), sigvec(2),\numask(2), setrlimit(2), wait(2), tty(4), a.out(5), environ(7),\n`An introduction to the C shell'\n.SH BUGS\nWhen a command is restarted from a stop,\nthe shell prints the directory it started in if this is different\nfrom the current directory; this can be misleading (i.e. wrong)\nas the job may have changed directories internally.\n.PP\nShell builtin functions are not stoppable/restartable.\nCommand sequences of the form `a ; b ; c' are also not handled gracefully\nwhen stopping is attempted.  If you suspend `b', the shell will then\nimmediately execute `c'.  This is especially noticeable if this\nexpansion results from an\n.I alias.\nIt suffices to place the sequence of commands in ()'s to force it to\na subshell, i.e. `( a ; b ; c )'.\n.PP\nControl over tty output after processes are started is primitive;\nperhaps this will inspire someone to work on a good virtual\nterminal interface.  In a virtual terminal interface much more\ninteresting things could be done with output control.\n.PP\nAlias substitution is most often used to clumsily simulate shell procedures;\nshell procedures should be provided rather than aliases.\n.PP\nCommands within loops, prompted for by `?', are not placed in the\n.I history\nlist.\nControl structure should be parsed rather than being recognized as built-in\ncommands.  This would allow control commands to be placed anywhere,\nto be combined with `|', and to be used with `&' and `;' metasyntax.\n.PP\nIt should be possible to use the `:' modifiers on the output of command\nsubstitutions.\nAll and more than one `:' modifier should be allowed on `$' substitutions.\n.PP\nThe way the\n.B filec\nfacility is implemented is ugly and expensive.\n"
  },
  {
    "path": "share/man/man1/ctags.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ctags.1\t6.2 (Berkeley) 5/30/85\n.\\\"\n.TH CTAGS 1 \"May 30, 1985\"\n.UC 4\n.SH NAME\nctags \\- create a tags file\n.SH SYNOPSIS\n.B ctags\n[ \n.B \\-BFatuwvx\n] [\n.B \\-f \n.I tagsfile\n]\nname ...\n.SH DESCRIPTION\n.I Ctags\nmakes a tags file for\n.IR ex (1)\nfrom the specified C, Pascal, Fortran, YACC, lex, and lisp sources.\nA tags file gives the locations of specified objects (in this case\nfunctions and typedefs) in a group of files.  Each line of the tags\nfile contains the object name, the file in which it is defined, and\nan address specification for the object definition. Functions are\nsearched with a pattern, typedefs with a line number. Specifiers are\ngiven in separate fields on the line, separated by blanks or tabs.\nUsing the\n.I tags\nfile,\n.I ex\ncan quickly find these objects definitions.\n.PP\nIf the\n.B \\-x\nflag is given, \n.I ctags\nproduces a list of object names, the line number and file\nname on which each is defined, as well as the text of that line\nand prints this on the standard output.  This is a simple index\nwhich can be printed out as an off-line readable function index.\n.PP\nIf the\n.B \\-v\nflag is given,\nan index of the form expected by\n.IR vgrind (1)\nis produced on the standard output.\nThis listing contains the function name,\nfile name, and page number\n(assuming 64 line pages).\nSince the output will be sorted into lexicographic order,\nit may be desired to run the output through\n.BR \"sort \\-f\" .\nSample use:\n.nf\n\tctags \\-v files | sort \\-f > index\n\tvgrind \\-x index\n.fi\n.PP\nNormally \n.I ctags\nplaces the tag descriptions in a file called\n.IR tags ;\nthis may be overridden with the\n.B \\-f\noption.\n.PP\nFiles whose names end in \n.B \\.c\nor\n.B \\.h\nare assumed to be C source files and are searched for C routine and\nmacro definitions.\nFiles whose names end in\n.B \\.y\nare assumed to be YACC source files.\nFiles whose names end in\n.B \\.l\nare assumed to be either lisp files\nif their first non-blank character is `;', `(', or `[',\nor lex files otherwise.\nOther files are first examined to see if they contain any Pascal or\nFortran routine definitions; if not, they are processed again\nlooking for C definitions.\n.PP\nOther options are:\n.TP 5\n.B \\-F\nuse forward searching patterns (/.../) (default).\n.TP 5\n.B \\-B\nuse backward searching patterns (?...?).\n.TP 5\n.B \\-a\nappend to tags file.\n.TP 5\n.B \\-t\ncreate tags for typedefs.\n.TP 5\n.B \\-w\nsuppressing warning diagnostics.\n.TP 5\n.B \\-u\ncausing the specified files to be\n.I updated\nin tags, that is, all references to them are deleted,\nand the new values are appended to the file.\n(Beware: this option is implemented in a way which is rather slow;\nit is usually faster to simply rebuild the\n.I tags\nfile.)\n.PP\nThe tag\n.I main\nis treated specially in C programs.\nThe tag formed is created by prepending\n.I M\nto the name of the file, with a trailing .c removed, if\nany, and leading pathname components also removed.\nThis makes use of\n.I ctags\npractical in directories with more than one program.\n.SH FILES\n.DT\ntags\t\toutput tags file\n.SH SEE ALSO\nex(1), vi(1)\n.SH AUTHOR\nKen Arnold; FORTRAN added by Jim Kleckner; Bill Joy\nadded Pascal and\n.B \\-x,\nreplacing\n.I cxref;\nC typedefs added by Ed Pelegri-Llopart.\n.SH BUGS\nRecognition of \\fBfunctions\\fR, \\fBsubroutines\\fR and \\fBprocedures\\fR\nfor FORTRAN and Pascal is done is a very simpleminded way.\nNo attempt is made to deal with block structure; if you have two\nPascal procedures in different blocks with the same name you lose.\n.PP\nThe method of deciding whether to look for C or Pascal and FORTRAN\nfunctions is a hack.\n.PP\nDoes not know about #ifdefs.\n.PP\nShould know about Pascal types.\nRelies on the input being well formed to detect typedefs.\nUse of -tx shows only the last line of typedefs.\n\n"
  },
  {
    "path": "share/man/man1/date.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)date.1\t6.5 (Berkeley) 3/24/87\n.\\\"\n.TH DATE 1 \"March 24, 1987\"\n.UC 4\n.SH NAME\ndate \\- print and set the date\n.SH SYNOPSIS\n.B date\n.RB \"[-nu] [-d dst] [-t timezone] [yymmddhhmm [\" . \"ss] ]\"\n.SH DESCRIPTION\nIf no arguments are given, the current date and time are printed.\nProviding an argument will set the desired date; only the superuser\ncan set the date.  The \\fI-d\\fP and \\fI-t\\fP flags set the kernel's\nvalues for daylight savings time and minutes west of GMT.  If \\fIdst\\fP\nis non-zero, future calls to \\fIgettimeofday\\fP(2) will return a non-zero\n\\fItz_dsttime\\fP.  \\fITimezone\\fP provides the number of minutes returned\nby future calls to \\fIgettimeofday\\fP(2) in \\fItz_minuteswest\\fP.  The\n\\fI-u\\fP flag is used to display or set the date in GMT (universal) time.\n.I yy\nrepresents the last two digits of the year;\nthe first\n.I mm\nis the month number;\n.I dd\nis the day number;\n.I hh\nis the hour number (24 hour system);\nthe second\n.I mm\nis the minute number;\n.BI . ss\nis optional and represents the seconds.\nFor example:\n.IP\ndate 8506131627\n.PP\nsets the date to June 13 1985, 4:27 PM.  The year, month and day may\nbe omitted; the default values will be the current ones.  The system\noperates in GMT.  \\fIDate\\fP takes care of the conversion to and from\nlocal standard and daylight-saving time.\n.PP\nIf \n.I timed(8)\nis running to synchronize the clocks of machines in a local\narea network, \\fIdate\\fP sets the time globally on all those\nmachines unless the\n.B \\-n\noption is given.\n.SH FILES\n/usr/adm/wtmp to record time-setting.\nIn /usr/adm/messages, \\fIdate\\fP records the name of the user\nsetting the time.\n.SH SEE ALSO\ngettimeofday(2), utmp(5), timed(8),\n.br\n\\fITSP: The Time Synchronization Protocol for UNIX 4.3BSD\\fP, \nR. Gusella and S. Zatti\n.SH DIAGNOSTICS\nExit status is 0 on success, 1 on complete failure to set the date,\nand 2 on successfully setting the local date but failing globally.\n.PP\nOccasionally, when \\fItimed\\fP synchronizes the time on many hosts, \nthe setting of a new time value may require more than a few seconds.\nOn these occasions, \\fIdate\\fP prints: `Network time being set'.\nThe message `Communication error with timed' occurs when the communication\nbetween \\fIdate\\fP and \\fItimed\\fP fails.\n.SH BUGS\nThe system attempts to keep the date in a format closely compatible\nwith VMS.  VMS, however, uses local time (rather than GMT) and does\nnot understand daylight-saving time.  Thus, if you use both UNIX\nand VMS, VMS will be running on GMT.\n"
  },
  {
    "path": "share/man/man1/dd.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)dd.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH DD 1 \"April 29, 1985\"\n.UC 4\n.SH NAME\ndd \\- convert and copy a file\n.SH SYNOPSIS\n.B dd\n[option=value] ...\n.SH DESCRIPTION\n.I Dd\ncopies the specified input file\nto the specified output with\npossible conversions.\nThe standard input and output are used by default.\nThe input and output block size may be\nspecified to take advantage of raw physical I/O.\n.PP\n.br\n.ns\n.TP 15\n.I option\n.I values\n.br\n.ns\n.TP \nif=\ninput file name; standard input is default\n.br\n.ns\n.TP \nof=\noutput file name; standard output is default\n.br\n.ns\n.TP \n.RI ibs= n\ninput block size\n.I n\nbytes (default 512)\n.br\n.ns\n.TP \n.RI obs= n\noutput block size (default 512)\n.br\n.ns\n.TP \n.RI bs= n\nset both input and output block size,\nsuperseding\n.I ibs\nand\n.I obs;\nalso, if no conversion is specified,\nit is particularly efficient since no copy need be done\n.br\n.ns\n.TP \n.RI cbs= n\nconversion buffer size\n.br\n.ns\n.TP \n.RI skip= n\nskip\n.IR n \"\"\ninput records before starting copy\n.br\n.ns\n.TP\n.RI files= n\ncopy\n.I n\ninput files before terminating (makes sense only\nwhere input is a magtape or similar device).\n.br\n.ns\n.TP \n.RI seek= n\nseek\n.I n\nrecords from beginning of output file before copying\n.br\n.ns\n.TP \ncount=\\fIn\\fR\ncopy only\n.IR n \"\"\ninput records\n.br\n.ns\n.TP \nconv=ascii\n.ds h \\h'\\w'conv='u'\nconvert EBCDIC to ASCII\n.br\n.ns\n.IP \\*hebcdic\nconvert ASCII to EBCDIC\n.br\n.ns\n.IP \\*hibm\nslightly different map of ASCII to EBCDIC\n.br\n.ns\n.IP \\*hblock\nconvert variable length records to fixed length\n.br\n.ns\n.IP \\*hunblock\nconvert fixed length records to variable length\n.br\n.ns\n.IP \\*hlcase\nmap alphabetics to lower case\n.br\n.ns\n.IP \\*hucase\nmap alphabetics to upper case\n.br\n.ns\n.IP \\*hswab\nswap every pair of bytes\n.br\n.ns\n.IP \\*hnoerror\ndo not stop processing on an error\n.br\n.ns\n.IP \\*hsync\npad every input record to\n.I  ibs\n.br\n.ns\n.IP \"\\*h... , ...\"\nseveral comma-separated conversions\n.PP\n.fi\nWhere sizes are specified,\na number of bytes is expected.\nA number may end with\n.B \"k, b\"\nor\n.B w\nto specify multiplication by\n1024, 512, or 2 respectively;\na pair of numbers may be separated by\n.B x\nto indicate a product.\n.PP\n.I Cbs\nis used only if\n.I ascii,\n.I unblock,\n.I ebcdic,\n.I ibm,\nor\n.I block\nconversion is specified.\nIn the first two cases,\n.I cbs\ncharacters are placed into the conversion buffer, any specified\ncharacter mapping is done,\ntrailing blanks trimmed and new-line added\nbefore sending the line to the output.\nIn the latter three cases, characters are read into the\nconversion buffer, and blanks added\nto make up an\noutput record of size\n.IR cbs .\n.PP\nAfter completion,\n.I dd\nreports the number of whole and partial input and output\nblocks.\n.PP\nFor example, to read an EBCDIC tape blocked ten 80-byte\nEBCDIC card images per record into the ASCII file\n.I x:\n.IP\n.nf\ndd if=/dev/rmt0 of=x ibs=800 cbs=80 conv=ascii,lcase\n.fi\n.PP\nNote the use of raw magtape.\n.I Dd\nis especially suited to I/O on the raw\nphysical devices because it allows reading\nand writing in arbitrary record sizes.\n.SH \"SEE ALSO\"\ncp(1), tr(1)\n.SH DIAGNOSTICS\nf+p records in(out): numbers of full and partial records read(written)\n.SH BUGS\nThe ASCII/EBCDIC conversion tables are\ntaken\nfrom the 256 character standard in\nthe CACM Nov, 1968.\nThe `ibm' conversion, while less blessed as a standard,\ncorresponds better to certain IBM print train conventions.\nThere is no universal solution.\n.br\nOne must specify ``conv=noerror,sync'' when copying\nraw disks with bad sectors to insure \n.I dd\nstays synchronized.\n.PP\nCertain combinations of arguments to \n.I conv=\nare permitted.\nHowever, the\n.I block\nor\n.I unblock\noption cannot be combined with\n.IR ascii ,\n.IR ebcdic \"\"\nor\n.IR ibm .\nInvalid combinations\n.I \"silently ignore\"\nall but the last mutually-exclusive keyword.\n"
  },
  {
    "path": "share/man/man1/deroff.1",
    "content": ".\\\"\t@(#)deroff.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH DEROFF 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nderoff \\- remove nroff, troff, tbl and eqn constructs\n.SH SYNOPSIS\n.B deroff\n[\n.B \\-w\n]\nfile ...\n.SH DESCRIPTION\n.I Deroff\nreads each file in sequence and removes all\n.I nroff\nand\n.I troff\ncommand lines, backslash constructions, macro definitions,\n.I eqn\nconstructs (between `.EQ' and `.EN' lines or between delimiters),\nand table descriptions and writes the remainder on the standard output.\n.I Deroff\nfollows chains of included files (`.so' and `.nx' commands);\nif a file has already been included, a `.so' is ignored and a `.nx'\nterminates execution.  If no input file is given,\n.I deroff\nreads from the standard input file.\n.PP\nIf the\n.B \\-w\nflag is given, the output is a word list, one `word' (string of letters,\ndigits, and apostrophes, beginning with a letter; apostrophes are removed)\nper line, and all other characters ignored.\nOtherwise, the output follows the original, with the deletions mentioned above.\n.SH \"SEE ALSO\"\ntroff(1), eqn(1), tbl(1)\n.SH BUGS\n.I Deroff\nis not a complete\n.I troff\ninterpreter, so it can be confused by subtle constructs.\nMost errors result in too much rather than too little output.\n"
  },
  {
    "path": "share/man/man1/df.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)df.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH DF 1 \"April 29, 1985\"\n.UC 4\n.SH NAME\ndf \\- disk free\n.SH SYNOPSIS\n.B df\n[\n.B \\-i\n] [ filesystem ... ] [ file ... ]\n.SH DESCRIPTION\n.I Df\nprints out the amount of free disk space\navailable on the specified\n.I filesystem,\ne.g. ``/dev/rp0a'',\nor on the filesystem in which the specified\n.I file,\ne.g. ``$HOME'',\nis contained.\nIf no file system is specified,\nthe free space on all of\nthe normally mounted file systems\nis printed.\nThe reported numbers are in kilobytes.\n.PP\nOther options are:\n.TP\n.B \\-i\nReport also the number of inodes which are used and free.\n.SH FILES\n/etc/fstab\tlist of normally mounted filesystems\n.SH \"SEE ALSO\"\nfstab(5), icheck(8), quot(8)\n"
  },
  {
    "path": "share/man/man1/diction.1",
    "content": ".\\\"\t@(#)diction.1\t6.2 (Berkeley) 5/10/86\n.\\\"\n.TH DICTION 1 \"May 10, 1986\"\n.AT 3\n.SH NAME\ndiction, explain \\- print wordy sentences; thesaurus for diction\n.SH SYNOPSIS\n.B diction\n[\n.B \\-ml\n] [\n.B \\-mm\n] [\n.B \\-n\n] [\n.B \\-f\npfile ]\nfile ...\n.br\n.B explain\n.LP\n.SH DESCRIPTION\n.I Diction\nfinds all sentences in a document that contain phrases\nfrom a data base of bad or wordy diction.\nEach phrase is bracketed with [ ].\nBecause\n.I diction\nruns\n.I deroff\nbefore looking at the text, formatting\nheader files should be included as part of the input.\nThe default macro package\n.B \\-ms\nmay be overridden with the flag\n.B \\-mm.\nThe flag\n.B \\-ml\nwhich causes \n.B deroff\nto skip lists, should be used if the document contains many lists of\nnon-sentences.\nThe user may supply her/his own pattern file to be used in addition to the default file\nwith\n.B \\-f\n.I pfile.\nIf the flag\n.B \\-n\nis also supplied the default file will be suppressed.\n.PP\n.I Explain\nis an interactive thesaurus for the phrases found by diction.\n.SH \"SEE ALSO\"\nderoff(1)\n.SH BUGS\nUse of non-standard formatting macros may cause\nincorrect sentence breaks.\nIn particular,\n.I diction\ndoesn't grok\n.B \\-me.\n"
  },
  {
    "path": "share/man/man1/diff.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)diff.1\t6.4.1 (2.11BSD) 1996/10/21\n.\\\"\n.TH DIFF 1 \"October 21, 1996\"\n.UC 4\n.SH NAME\ndiff \\- differential file and directory comparator\n.SH SYNOPSIS\n.B diff\n[\n.B \\-l\n] [\n.B \\-r\n] [\n.B \\-s\n] [\n\\fB\\-cefhn\\fR\n] [\n.B \\-biwt\n] dir1 dir2\n.br\n.B diff\n[\n\\fB\\-cefhn\n] [\n\\fB\\-biwt\\fR\n] file1 file2\n.br\n.B diff\n[\n.BI \\-D string\n] [\n.B \\-biw\n]\nfile1 file2\n.SH DESCRIPTION\nIf both arguments are directories,\n.I diff\nsorts the contents of the directories by name, and then runs the\nregular file\n.I diff\nalgorithm (described below)\non text files which are different.\nBinary files which differ,\ncommon subdirectories, and files which appear in only one directory\nare listed.\nOptions when comparing directories are:\n.TP\n.B \\-l\nlong output format; each text file\n.I diff\nis piped through\n.IR pr (1)\nto paginate it,\nother differences are remembered and summarized\nafter all text file differences are reported.\n.TP\n.B \\-r\ncauses application of\n.I diff\nrecursively to common subdirectories encountered.\n.TP\n.B \\-s\ncauses \n.I diff\nto report files which are the same, which are otherwise not mentioned.\n.TP\n.B \\-Sname\nstarts a directory\n.I diff\nin the middle beginning with file\n.I name.\n.PP\nWhen run on regular files, and when comparing text files which differ\nduring directory comparison,\n.I diff\ntells what lines must be changed in the files to bring them into agreement.\nExcept in rare circumstances,\n.I diff\nfinds a smallest sufficient set of file differences.\nIf neither\n.I file1\nnor\n.I file2\nis a directory, then either\nmay be given as `\\-', in which case the standard input is used.\nIf\n.I file1\nis a directory,\nthen a file in that directory whose file-name is the same as the file-name of\n.I file2\nis used (and vice versa).\n.PP\nThere are several options for output format;\nthe default output format contains lines of these forms:\n.IP \"\" 5\n.I n1\na\n.I n3,n4\n.br\n.I n1,n2\nd\n.I n3\n.br\n.I n1,n2\nc\n.I n3,n4\n.PP\nThese lines resemble\n.I ed\ncommands to convert\n.I file1\ninto\n.IR file2 .\nThe numbers after the letters pertain to\n.IR file2 .\nIn fact, by exchanging `a' for `d' and reading backward\none may ascertain equally how to convert \n.I file2\ninto\n.IR file1 .\nAs in \n.I ed,\nidentical pairs where\n.I n1\n=\n.I n2\nor\n.I n3\n=\n.I n4\nare abbreviated as a single number.\n.PP\nFollowing each of these lines come all the lines that are\naffected in the first file flagged by `<', \nthen all the lines that are affected in the second file\nflagged by `>'.\n.PP\nExcept for\n\\fB\\-b, -w, -i\\fP or \\fB-t\\fP\nwhich may be given with any of the others,\nthe following options are mutually exclusive:\n.TP 9\n.B \\-e\nproduces a script of\n.I \"a, c\"\nand \n.I d\ncommands for the editor\n.I ed,\nwhich will recreate\n.I file2\nfrom\n.IR file1 .\nIn connection with\n.BR \\-e ,\nthe following shell program may help maintain\nmultiple versions of a file.\nOnly an ancestral file ($1) and a chain of \nversion-to-version\n.I ed\nscripts ($2,$3,...) made by\n.I diff\nneed be on hand.\nA `latest version' appears on\nthe standard output.\n.IP\n\\ \\ \\ \\ \\ \\ \\ \\ (shift; cat $*; echo \\'1,$p\\') \\(bv ed \\- $1\n.IP\nExtra commands are added to the output when comparing directories with\n.B \\-e,\nso that the result is a\n.IR sh (1)\nscript for converting text files which are common to the two directories\nfrom their state in\n.I dir1\nto their state in\n.I dir2.\n.TP 9\n.B \\-f\nproduces a script similar to that of\n.B \\-e,\nnot useful with\n.I ed,\nand in the opposite order.\n.TP 9\n.B \\-n\nproduces a script similar to that of\n.B \\-e,\nbut in the opposite order and with a count of changed lines on each\ninsert or delete command.  This is the form used by\n.IR rcsdiff (1).\n.TP 9\n.B \\-c\nproduces a diff with lines of context.\nThe default is to present 3 lines of context and may be changed, e.g to 10, by\n.BR \\-c10 \\&.\nWith\n.B \\-c\nthe output format is modified slightly:\nthe output beginning with identification of the files involved and\ntheir creation dates and then each change is separated\nby a line with a dozen *'s.\nThe lines removed from\n.I file1\nare marked with `\\(mi '; those added to\n.I file2\nare marked `+ '.  Lines which are changed from one\nfile to the other are marked in both files with with `! '.\n\nChanges which lie within <context> lines of each other are grouped\ntogether on output.  (This is a change from the previous ``diff -c''\nbut the resulting output is usually much easier to interpret.)\n.TP 9\n.B \\-h\ndoes a fast, half-hearted job.\nIt works only when changed stretches are short\nand well separated,\nbut does work on files of unlimited length.\n.TP\n.B \\-Dstring\ncauses\n.I diff\nto create a merged version of\n.I file1\nand\n.I file2\non the standard output, with C preprocessor controls included so that\na compilation of the result without defining \\fIstring\\fR is equivalent\nto compiling\n.I file1,\nwhile defining\n.I string\nwill yield\n.I file2.\n.TP 9\n.B \\-b\ncauses trailing blanks (spaces and tabs) to be ignored, and other\nstrings of blanks to compare equal.\n.TP 9\n.B \\-w\nis similar to\n.B \\-b\nbut causes whitespace (blanks and tabs) to be totally ignored.  E.g.,\n``if\\ (\\ a\\ ==\\ b\\ )'' will compare equal to ``if(a==b)''.\n.TP 9\n.B \\-i\nignores the case of letters.  E.g., ``A'' will compare equal to ``a''.\n.TP 9\n.B \\-t\nwill expand tabs in output lines.  Normal or\n.B \\-c\noutput adds character(s) to the front of each line which may screw up\nthe indentation of the original source lines and make the output listing\ndifficult to interpret.  This option will preserve the original source's\nindentation.\n.SH FILES\n/tmp/d?????\n.br\n/usr/libexec/diffh for \n.B \\-h\n.br\n/bin/diff for directory diffs\n.br\n/bin/pr\n.SH \"SEE ALSO\"\ncmp(1), cc(1), comm(1), ed(1), diff3(1)\n.SH DIAGNOSTICS\nExit status is 0 for no differences, 1 for some, 2 for trouble.\n.SH BUGS\nEditing scripts produced under the\n.BR \\-e \" or\"\n.BR \\-f \" option are naive about\"\ncreating lines consisting of a single `\\fB.\\fR'.\n.PP\nWhen comparing directories with the\n\\fB\\-b, -w\\fP or \\fB-i\\fP\noptions specified,\n.I diff\nfirst compares the files ala\n.I cmp,\nand then decides to run the\n.I diff\nalgorithm if they are not equal.\nThis may cause a small amount of spurious output if the files\nthen turn out to be identical because the only differences are\ninsignificant blank string or case differences.\n"
  },
  {
    "path": "share/man/man1/diff3.1",
    "content": ".\\\"\t@(#)diff3.1\t6.2.1 (2.11BSD) 1996/10/21\n.\\\"\n.TH DIFF3 1 \"October 21, 1996\"\n.AT 3\n.SH NAME\ndiff3 \\- 3-way differential file comparison\n.SH SYNOPSIS\n.B diff3\n[\n.B \\-exEX3\n]\nfile1 file2 file3\n.SH DESCRIPTION\n.I Diff3\ncompares three versions of a file,\nand publishes disagreeing ranges of text\nflagged with these codes:\n.TP 16\n====\nall three files differ\n.TP 16\n====1\n.IR file1 \" is different\"\n.TP 16\n====2\n.IR file2 \" is different\"\n.TP 16\n====3\n.IR file3 \" is different\"\n.PP\nThe type of change suffered in converting a given range\nof a given file to some other is\nindicated in one of these ways:\n.TP 16\n.IB f \" : \" n1 \" a\"\nText is to be appended after line number\n.I n1\nin file\n.I f,\nwhere\n.I f\n= 1, 2, or 3.\n.TP 16\n.IB f \" : \" n1 \" , \" n2 \" c\"\nText is to be\nchanged in the range line\n.I n1\nto line\n.IR n2 .\nIf \n.I n1\n=\n.I n2,\nthe range may be abbreviated to\n.IR n1 .\n.PP\nThe original contents of the range follows immediately\nafter a\n.B c\nindication.\nWhen the contents of two\nfiles are identical, the contents of the lower-numbered\nfile is suppressed.\n.PP\nUnder the\n.B \\-e\noption,\n.I diff3\npublishes a script for the editor\n.I ed\nthat will incorporate into\n.I file1\nall changes between\n.I file2\nand\n.I file3,\n.IR i.e .\nthe changes that normally would be flagged ==== and ====3.\nOption\n.B \\-x\n(\\fB\\-3\\fR)\nproduces a script to incorporate\nonly changes flagged ==== (====3).\nThe following command will apply the resulting script to\n`file1'.\n.PP\n.ti 16n\n(cat script; echo \\'1,$p\\') \\(bv ed \\- file1\n.PP\nThe\n.B \\-E\nand\n.B \\-X\nare similar to\n.B \\-e\nand\n.BR \\-x ,\nrespectively, but treat overlapping changes (i.e., changes that would\nbe flagged with ==== in the normal listing) differently.  The overlapping\nlines from both files will be inserted by the edit script, bracketed\nby \"<<<<<<\" and \">>>>>>\" lines.\n.PP\nFor example, suppose lines 7-8 are changed in both file1 and file2.\nApplying the edit script generated by the command\n.ce\n\"diff3 -E file1 file2 file3\" \n.br\nto file1 results in the file:\n.RS\n.nf\n\nlines 1-6\nof file1\n<<<<<<< file1\nlines 7-8\nof file1\n=======\nlines 7-8\nof file3\n>>>>>>> file3\nrest of file1\n.fi\n.RE\n.PP\nThe\n.B \\-E\noption is used by RCS\n.IR merge (1)\nto insure that overlapping changes in the merged files are preserved\nand brought to someone's attention.\n.SH FILES\n/tmp/d3?????\n.br\n/usr/libexec/diff3\n.SH \"SEE ALSO\"\ndiff(1)\n.SH BUGS\nText lines that consist of a single `.' will\ndefeat\n.B \\-e.\n"
  },
  {
    "path": "share/man/man1/du.1",
    "content": ".\\\"\t@(#)du.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH DU 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\ndu \\- summarize disk usage\n.SH SYNOPSIS\n.B du\n[\n.B \\-s\n] [\n.B \\-a\n] [ name ... ]\n.SH DESCRIPTION\n.I Du\ngives the number of kilobytes contained in all files\nand, recursively, directories within each specified\ndirectory or file\n.IR name .\nIf\n.I name\nis missing,\n`\\fB.\\fR'\nis used.\n.PP\nThe argument\n.B \\-s\ncauses only the grand total to\nbe given.\nThe argument\n.B \\-a\ncauses an entry to be generated\nfor each file.\nAbsence of either causes an entry to be generated for\neach directory only.\n.PP\nA file which has two links to it is only counted once.\n.SH \"SEE ALSO\"\ndf(1), quot(8)\n.SH BUGS\nNon-directories\ngiven as arguments (not under\n.B \\-a\noption) are not listed.\n.br\nIf there are too many distinct linked files,\n.I du\ncounts the excess files multiply.\n"
  },
  {
    "path": "share/man/man1/echo.1",
    "content": ".\\\"\t@(#)echo.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH ECHO 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\necho \\- echo arguments\n.SH SYNOPSIS\n.B echo\n[\n.B \\-n\n]\n[ arg ] ...\n.SH DESCRIPTION\n.I Echo\nwrites its arguments separated by blanks and terminated by\na newline on the standard output.  If the flag\n.B \\-n\nis used, no newline is added to the output.\n.PP\n.I Echo\nis useful for producing diagnostics in\nshell programs and for writing constant data on pipes.\nTo send diagnostics to the standard error file, do `echo ... 1>&2'.\n"
  },
  {
    "path": "share/man/man1/ed.1",
    "content": ".\\\"\t@(#)ed.1\t6.1.1.1 (Berkeley) 8/12/86\n.\\\"\n.TH ED 1 \"August 12, 1986\"\n.AT 3\n.if t .ds q \\(aa\n.if n .ds q '\n.SH NAME\ned \\- text editor\n.SH SYNOPSIS\n.B ed\n[\n.B \\-\n] [ name ]\n.SH DESCRIPTION\n.I Ed\nis the standard text editor.\n.PP\nIf a\n.I name\nargument is given,\n.I ed\nsimulates an\n.I e\ncommand (see below)\\| on the named file; that is to say,\nthe file is read into\n.I ed's\nbuffer so that it can be edited.\nThe optional\n.B \\-\nsuppresses the printing\nof explanatory output\nand should be used\nwhen the standard input is\nan editor script.\n.PP\n.I Ed\noperates on a copy of any file it is editing; changes made\nin the copy have no effect on the file until a\n.IR w \"\"\n(write)\\|\ncommand is given.\nThe copy of the text being edited resides\nin a temporary file called the \n.IR buffer .\n.PP\nCommands to\n.I ed\nhave a simple and regular structure: zero or\nmore\n.I addresses\nfollowed by a single character\n.I command,\npossibly\nfollowed by parameters to the command.\nThese addresses specify one or more lines in the buffer.\nMissing addresses are supplied by default.\n.PP\nIn general, only one command may appear on a line.\nCertain commands allow the \naddition of text to the buffer.\nWhile\n.I ed\nis accepting text, it is said\nto be in\n.I  \"input mode.\"\nIn this mode, no commands are recognized;\nall input is merely collected.\nInput mode is left by typing a period `\\fB.\\fR' alone at the\nbeginning of a line.\n.PP\n.I Ed\nsupports a limited form of\n.I \"regular expression\"\nnotation.\nA regular expression specifies\na set of strings of characters.\nA member of this set of strings is said to be\n.I matched\nby the regular expression.\nIn the following specification for regular expressions\nthe word `character' means any character but newline.\n.IP 1.\nAny character except a special character\nmatches itself.\nSpecial characters are\nthe regular expression delimiter plus\n.RB \\e\\|[\\| .\nand sometimes ^\\|*\\|$.\n.IP 2.\nA\n.B .\nmatches any character.\n.IP 3.\nA \\e followed by any character except a digit or (\\|) matches that character.\n.IP 4.\nA nonempty string\n.I s\nbracketed\n.RI [ \\|s\\| ]\n(or\n.RI [^ s\\| ])\nmatches any character in (or not in)\n.I s.\nIn \n.I s,\n\\e has no special meaning, and ] may only appear as\nthe first letter.\nA substring \n.I a\\-b,\nwith\n.I a\nand\n.I b\nin ascending ASCII order, stands for the inclusive\nrange of ASCII characters.\n.IP 5.\nA regular expression of form 1-4 followed by * matches a sequence of\n0 or more matches of the regular expression.\n.IP 6.\nA regular expression,\n.I x,\nof form 1-8, bracketed\n.RI \\e( \\|x\\| \\e)\nmatches what\n.I x\nmatches.\n.IP 7.\nA \\e followed by a digit \n.I n\nmatches a copy of the string that the\nbracketed regular expression beginning with the\n.IR n th\n\\e( matched.\n.IP 8.\nA regular expression of form 1-8,\n.I x,\nfollowed by a regular expression of form 1-7,\n.I y\nmatches a match for\n.I x\nfollowed by a match for\n.I y,\nwith the\n.I x\nmatch being as long as possible while still permitting a\n.I y\nmatch.\n.IP 9.\nA regular expression of form 1-8 preceded by ^\n(or followed by $), is constrained to matches that\nbegin at the left (or end at the right) end of a line.\n.IP 10.\nA regular expression of form 1-9 picks out the\nlongest among the leftmost matches in a line.\n.IP 11.\nAn empty regular expression stands for a copy of the\nlast regular expression encountered.\n.PP\nRegular expressions are used in addresses to specify\nlines and in one command\n(see\n.I s\nbelow)\\|\nto specify a portion of a line which is to be replaced.\nIf it is desired to use one of\nthe regular expression metacharacters as an ordinary\ncharacter, that character may be preceded by `\\e'.\nThis also applies to the character bounding the regular\nexpression (often `/')\\| and to `\\e' itself.\n.PP\nTo understand addressing in\n.I ed\nit is necessary to know that at any time there is a\n.I  \"current line.\"\nGenerally speaking, the current line is\nthe last line affected by a command; however,\nthe exact effect on the current line\nis discussed under the description of\nthe command.\nAddresses are constructed as follows.\n.TP\n1.\nThe character `\\fB.\\fR' addresses the current line.\n.TP\n2.\nThe character `$' addresses the last line of the buffer.\n.TP\n3.\nA decimal number\n.I n\naddresses the\n.IR n -th\nline of the buffer.\n.TP\n4.\n`\\(fm\\fIx\\fR' addresses the line marked with the name\n.IR x ,\nwhich must be a lower-case letter.\nLines are marked with the\n.I k\ncommand described below.\n.TP\n5.\nA regular expression enclosed in slashes `/' addresses\nthe line found by searching forward from the current line\nand stopping at the first line containing a\nstring that matches the regular expression.\nIf necessary the search wraps around to the beginning of the\nbuffer.\n.TP\n6.\nA regular expression enclosed in queries `?' addresses\nthe line found by searching backward from the current line\nand stopping at the first line containing\na string that matches the regular expression.\nIf necessary\nthe search wraps around to the end of the buffer.\n.TP\n7.\nAn address followed by a plus sign `+'\nor a minus sign `\\-' followed by a decimal number specifies that address plus\n(resp. minus)\\| the indicated number of lines.\nThe plus sign may be omitted.\n.TP\n8.\nIf an address begins with `+' or `\\-'\nthe addition or subtraction is taken with respect to the current line;\ne.g. `\\-5' is understood to mean `\\fB.\\fR\\-5'.\n.TP\n9.\nIf an address ends with `+' or `\\-',\nthen 1 is added (resp. subtracted).\nAs a consequence of this rule and rule 8,\nthe address `\\-' refers to the line before the current line.\nMoreover,\ntrailing\n`+' and `\\-' characters\nhave cumulative effect, so `\\-\\-' refers to the current\nline less 2.\n.TP\n10.\nTo maintain compatibility with earlier versions of the editor,\nthe character `^' in addresses is \nequivalent to `\\-'.\n.PP\nCommands may require zero, one, or two addresses.\nCommands which require no addresses regard the presence\nof an address as an error.\nCommands which accept one or two addresses\nassume default addresses when insufficient are given.\nIf more addresses are given than such a command requires,\nthe last one or two (depending on what is accepted)\\| are used.\n.PP\nAddresses are separated from each other typically by a comma\n`\\fB,\\fR'.\nThey may also be separated by a semicolon\n`\\fB;\\fR'.\nIn this case the current line `\\fB.\\fR' is set to\nthe previous address before the next address is interpreted.\nThis feature can be used to determine the starting\nline for forward and backward searches (`/', `?')\\|.\nThe second address of any two-address sequence\nmust correspond to a line following the line corresponding to the first address.\nThe special form `%'\nis an abbreviation for the address pair `1,$'.\n.PP\nIn the following list of\n.I ed\ncommands, the default addresses\nare shown in parentheses.\nThe parentheses are not part of\nthe address, but are used to show that the given addresses are\nthe default.\n.PP\nAs mentioned, it is generally illegal for more than one\ncommand to appear on a line.\nHowever, most commands may be suffixed by `p'\nor by `l', in which case\nthe current line is either\nprinted or listed respectively\nin the way discussed below.\nCommands may also be suffixed by `n',\nmeaning the output of the command is to\nbe line numbered.\nThese suffixes may be combined in any order.\n.TP 5\n.RB (\\| .\\| )\\|a\n.br\n.ns\n.TP 5\n<text>\n.br\n.ns\n.TP 5\n.B .\n.br\nThe append command reads the given text\nand appends it after the addressed line.\n`\\fB.\\fR' is left\non the last line input, if there\nwere any, otherwise at the addressed line.\nAddress `0' is legal for this command; text is placed\nat the beginning of the buffer.\n.TP 5\n.RB (\\| .\\| ,\\  .\\| )\\|c\n.br\n.ns\n.TP 5\n<text>\n.br\n.ns\n.TP 5\n.B .\n.br\nThe change\ncommand deletes the addressed lines, then accepts input\ntext which replaces these lines.\n`\\fB.\\fR' is left at the last line input; if there were none,\nit is left at the line preceding the deleted lines.\n.TP 5\n.RB (\\| .\\| ,\\  .\\| )\\|d\nThe delete command deletes the addressed lines from the buffer.\nThe line originally after the last line deleted becomes the current line;\nif the lines deleted were originally at the end,\nthe new last line becomes the current line.\n.TP 5\ne filename\nThe edit\ncommand causes the entire contents of the buffer to be deleted,\nand then the named file to be read in.\n`\\fB.\\fR' is set to the last line of the buffer.\nThe number of characters read is typed.\n`filename' is remembered for possible use as a default file name\nin a subsequent\n.I r\nor\n.I w\ncommand.\nIf `filename' is missing, the remembered name is used.\n.TP 5\nE filename\nThis command is the same as\n.I e,\nexcept that no diagnostic results when no\n.I w\nhas been given since the last buffer alteration.\n.TP 5\nf filename\nThe filename command prints the currently remembered file name.\nIf `filename' is given,\nthe currently remembered file name is changed to `filename'.\n.TP 5\n(1,$)\\|g/regular expression/command list\nIn the global\ncommand, the first step is to mark every line which matches\nthe given regular expression.\nThen for every such line, the\ngiven command list is executed with `\\fB.\\fR' initially set to that line.\nA single command or the first of multiple commands\nappears on the same line with the global command.\nAll lines of a multi-line list except the last line must be ended with `\\e'.\n.I A,\n.I i,\nand\n.I c\ncommands and associated input are permitted;\nthe `\\fB.\\fR' terminating input mode may be omitted if it would be on the\nlast line of the command list.\nThe commands\n.I g\nand\n.I v\nare not permitted in the command list.\n.TP 5\n.RB (\\| .\\| )\\|i\n.ns\n.TP 5\n<text>\n.br\n.ns\n.TP 5\n.B .\n.br\nThis command inserts the given text before the addressed line.\n`\\fB.\\fR' is left at the last line input, or, if there were none,\nat the line before the addressed line.\nThis command differs from the\n.I a\ncommand only in the placement of the\ntext.\n.TP 5\n.RB (\\| .\\| ,\\  . +1)\\|j\nThis command joins the addressed lines into a single line;\nintermediate newlines simply disappear.\n`\\fB.\\fR' is left at the resulting line.\n.TP 5\n( \\fB. \\fR)\\|k\\fIx\\fR\nThe mark command marks the addressed line with\nname\n.I x,\nwhich must be a lower-case letter.\nThe address form `\\(fm\\fIx\\fR' then addresses this line.\n.ne 2.5\n.TP 5\n.RB (\\| .\\| ,\\  .\\| )\\|l\nThe list command\nprints the addressed lines in an unambiguous way:\nnon-graphic characters are\nprinted in two-digit octal,\nand long lines are folded.\nThe\n.I l\ncommand may be placed on the same line after any non-i/o\ncommand.\n.TP 5\n.RB (\\| .\\| ,\\  .\\| )\\|m\\fIa\nThe move command repositions the addressed lines after the line\naddressed by\n.IR a .\nThe last of the moved lines becomes the current line.\n.TP 5\n.RB (\\| .\\| ,\\  .\\| )\\|p\nThe print command prints the addressed lines.\n`\\fB.\\fR'\nis left at the last line printed.\nThe\n.I p\ncommand\nmay\nbe placed on the same line after any non-i/o command.\n.TP\n.RB (\\| .\\| ,\\  .\\| )\\|P\nThis command is a synonym for\n.I p.\n.TP 5\nq\nThe quit command causes\n.I ed\nto exit.\nNo automatic write\nof a file is done.\n.TP 5\nQ\nThis command is the same as\n.I q,\nexcept that no diagnostic results when no\n.I w\nhas been given since the last buffer alteration.\n.TP 5\n($)\\|r filename\nThe read command\nreads in the given file after the addressed line.\nIf no file name is given,\nthe remembered file name, if any, is used\n(see\n.I e\nand\n.I f\ncommands)\\|.\nThe file name is remembered if there was no\nremembered file name already.\nAddress `0' is legal for\n.I r\nand causes the\nfile to be read at the beginning of the buffer.\nIf the read is successful, the number of characters\nread is typed.\n`\\fB.\\fR' is left at the last line read in from the file.\n.TP 5\n(\\| \\fB.\\fR\\|, \\fB.\\fR\\|)\\|s/regular expression/replacement/       or,\n.br\n.ns\n.TP 5\n(\\| \\fB.\\fR\\|, \\fB.\\fR\\|)\\|s/regular expression/replacement/g\nThe substitute command searches each addressed\nline for an occurrence of the specified regular expression.\nOn each line in which a match is found,\nall matched strings are replaced by the replacement specified,\nif the global replacement indicator `g' appears after the command.\nIf the global indicator does not appear, only the first occurrence\nof the matched string is replaced.\nIt is an error for the substitution to fail on all addressed lines.\nAny punctuation character\nmay be used instead of `/' to delimit the regular expression\nand the replacement.\n`\\fB.\\fR' is left at the last line substituted.\n.IP\nAn ampersand `&' appearing in the replacement\nis replaced by the string matching the regular expression.\nThe special meaning of `&' in this context may be\nsuppressed by preceding it by `\\e'.\nThe characters\n.I `\\|\\en'\nwhere\n.I n\nis a digit,\nare replaced by the text matched by the\n.IR n -th\nregular subexpression\nenclosed between `\\e(' and `\\e)'.\nWhen\nnested, parenthesized subexpressions\nare present,\n.I n\nis determined by counting occurrences of `\\e(' starting from the left.\n.IP\nLines may be split by substituting new-line characters into them.\nThe new-line in the\nreplacement string\nmust be escaped by preceding it by `\\e'.\n.IP\nOne or two trailing delimiters may be omitted,\nimplying the `p' suffix.\nThe special form `s' followed by\n.I no\ndelimiters\nrepeats the most recent substitute command\non the addressed lines.\nThe `s' may be followed by the letters\n.B r\n(use the most recent regular expression for the\nleft hand side, instead of the most recent\nleft hand side of a substitute command),\n.B p\n(complement the setting of the\n.I p\nsuffix from the previous substitution), or\n.B g\n(complement the setting of the\n.I g\nsuffix).\nThese letters may be combined in any order.\n.TP 5\n.RB (\\| .\\| ,\\  .\\| )\\|t\\|\\fIa\nThis command acts just like the\n.I m\ncommand, except that a copy of the addressed lines is placed\nafter address\n.I a\n(which may be 0).\n`\\fB.\\fR' is left on the last line of the copy.\n.TP 5\n.RB (\\| .\\| ,\\  .\\| )\\|u\nThe undo command restores the buffer to it's state\nbefore the most recent buffer modifying command.\nThe current line is also restored.\nBuffer modifying commands are\n.I a, c, d, g, i, k, m, r, s, t,\nand\n.I v.\nFor purposes of undo,\n.I g\nand\n.I v\nare considered to be a single buffer modifying command.\nUndo is its own inverse.\n.IP\nWhen\n.I ed\nruns out of memory\n(at about 8000 lines on any 16 bit mini-computer\nsuch as the PDP-11)\nThis full undo is not possible, and\n.I u\ncan only undo the effect of the most recent\nsubstitute on the current line.\nThis restricted undo also applies to editor scripts\nwhen\n.I ed\nis invoked with the\n.B -\noption.\n.TP 5\n(1, $)\\|v/regular expression/command list\nThis command is the same as the global command\n.I g\nexcept that the command list is executed\n.I g\nwith `\\fB.\\fR' initially set to every line\n.I except\nthose\nmatching the regular expression.\n.TP 5\n(1, $)\\|w filename\n.br\nThe write command writes the addressed lines onto\nthe given file.\nIf the file does not exist,\nit is created.\nThe file name is remembered if there was no \nremembered file name already.\nIf no file name is given,\nthe remembered file name, if any, is used\n(see\n.I e\nand\n.I f\ncommands)\\|.\n`\\fB.\\fR' is unchanged.\nIf the command is successful, the number of characters written is\nprinted.\n.TP\n(1, $)\\|W filename\nThis command is the same as\n.I w,\nexcept that the addressed lines are appended to the file.\n.TP 5\n(1, $)\\|wq filename\nThis command is the same as\n.I w\nexcept that afterwards a\n.I q\ncommand is done,\nexiting the editor\nafter the file is written.\n.TP 5\n.RB (\\| .\\| +1)\\|z\tor,\n.br\n.ns\n.TP 5\n.RB (\\| .\\| +1)\\|z\\fIn\nThis command scrolls through the buffer starting at the addressed line.\n22 (or\n.I n,\nif given)\nlines are printed.\nThe last line printed becomes the current line.\nThe value\n.I n\nis sticky, in that it becomes the default for\nfuture\n.I z\ncommands.\n.TP 5\n($)\\|=\nThe line number of the addressed line is typed.\n`\\fB.\\fR' is unchanged by this command.\n.TP 5\n!<shell command>\nThe remainder of the line after the `!' is sent\nto\n.IR sh (1)\nto be interpreted as a command.\n.RB ` . '\nis unchanged.\n.TP 5\n.RB (\\| . +1,\\| . +1)\\|<newline>\nAn address alone on a line causes the addressed line to be printed.\nA blank line alone is equivalent to `.+1p'; it is useful\nfor stepping through text.\nIf two addresses are present with no\nintervening semicolon,\n.I ed\nprints the range of lines.\nIf they are separated by a semicolon,\nthe second line is printed.\n.PP\nIf an interrupt signal (ASCII DEL)\\| is sent,\n.I ed\nprints `?interrupted'\nand returns to its command level.\n.PP\nSome size limitations:\n512 characters per line,\n256 characters per global command list,\n64 characters per file name,\nand, on mini computers,\n128K characters in the temporary file.\nThe limit on the number of lines depends on the amount of core:\neach line takes 2 words.\n.PP\nWhen reading a file,\n.I ed\ndiscards ASCII NUL characters\nand all characters after the last newline.\nIt refuses to read files containing non-ASCII characters.\n.SH FILES\n/tmp/e*\n.br\nedhup: work is saved here if terminal hangs up\n.SH \"SEE ALSO\"\nB. W. Kernighan,\n.I\nA Tutorial Introduction to the ED Text Editor\n.br\nB. W. Kernighan,\n.I Advanced editing on UNIX\n.br\nex(1), sed(1), crypt(1)\n.SH DIAGNOSTICS\n`?name' for inaccessible file;\n`?self-explanatory message'\nfor other errors.\n.PP\nTo protect against throwing away valuable work,\na\n.I q\nor\n.I e\ncommand is considered to be in error, unless a\n.I w\nhas occurred since the last buffer change.\nA second\n.I q\nor\n.I e\nwill be obeyed regardless.\n.SH BUGS\nThe \n.I l\ncommand mishandles DEL.\n.br\nThe\n.I undo\ncommand causes marks to be lost on affected lines.\n"
  },
  {
    "path": "share/man/man1/efl.1",
    "content": ".\\\"\t@(#)efl.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH EFL 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nefl \\- Extended Fortran Language\n.SH SYNOPSIS\n.B efl\n[ option ... ]\n[ filename ... ]\n.SH DESCRIPTION\n.I Efl\ncompiles a program written in the EFL language into clean Fortran.\n.I Efl\nprovides the same control flow constructs as does\n.IR ratfor (1),\nwhich are essentially identical to those in C:\n.TP\nstatement grouping with braces;\ndecision-making with if, if-else, and switch-case;\nwhile,\nfor,\nFortran do,\nrepeat,\nand repeat...until loops;\nmulti-level break and next.\nIn addition, EFL has C-like data structures,\nand more uniform and convenient input/output syntax,\ngeneric functions.\nEFL also provides\nsome syntactic sugar to make programs easier to read and write:\n.TP\nfree form input:\nmultiple statements/line; automatic continuation\nstatement label names (not just numbers),\n.TP\ncomments:\n# this is a comment\n.TP\ntranslation of relationals:\n>, >=, etc., become .GT., .GE., etc.\n.TP\nreturn (expression)\nreturns expression to caller from function\n.TP\ndefine:\ndefine name replacement\n.TP\ninclude:\ninclude filename\n.PP\n.fi\nThe Efl command option\n.B \\-w\nsuppresses warning messages.\nThe option\n.B \\-C\ncauses comments to be copied through to the Fortran output (default);\n.B \\-#\nprevents comments from being copied through.\nIf a command argument contains an embedded equal sign,\nthat argument is treated as if it had appeared in an\n.B option\nstatement at the beginning of the program.\n.I Efl\nis best used with\n.IR f77 (1).\n.SH \"SEE ALSO\"\nf77(1),\nratfor(1).\n.br\nS. I. Feldman,\n.IR \"The Programming Language EFL\",\nBell Labs Computing Science Technical Report #78.\n"
  },
  {
    "path": "share/man/man1/eqn.1",
    "content": ".\\\"\t@(#)eqn.1\t6.2 (Berkeley) 5/9/86\n.\\\"\n.TH EQN 1 \"May 9, 1986\"\n.AT 3\n.EQ\ndelim $$\n.EN\n.SH NAME\neqn, neqn, checkeq \\- typeset mathematics\n.SH SYNOPSIS\n.B eqn\n[\n.BR \\-d xy\n] [\n.BR \\-p n\n] [\n.BR \\-s n\n] [\n.BR \\-f n\n] \n[ file ] ...\n.br\n.B checkeq\n[ file ] ...\n.SH DESCRIPTION\n.I Eqn\nis a\ntroff(1)\npreprocessor\nfor typesetting mathematics\non a Graphic Systems phototypesetter,\n.I neqn\non terminals.\nUsage is almost always\n.PP\n\teqn file ... | troff\n.br\n\tneqn file ... | nroff\n.PP\nIf no files are specified, \nthese programs\nread from the standard input.\nA line beginning with `.EQ' marks the start of an equation;\nthe end of an equation\nis marked by a line beginning with `.EN'.\nNeither of these lines is altered,\nso they may be defined in macro packages\nto get\ncentering, numbering, etc.\nIt is also possible to set two characters as `delimiters';\nsubsequent text between delimiters is also treated as\n.ul\neqn\ninput.\nDelimiters may be set to characters\n.I x\nand\n.I y\nwith the command-line argument\n.BI \\-d xy\nor (more commonly) with\n`delim\n.IR xy '\nbetween .EQ and .EN.\nThe left and right delimiters may be identical.\nDelimiters are turned off by `delim off'.\nAll text that is neither between delimiters nor between .EQ and .EN\nis passed through untouched.\n.PP\nThe program\n.I checkeq\nreports missing or unbalanced delimiters and .EQ/.EN pairs.\n.PP\nTokens within\n.I eqn\nare separated by\nspaces, tabs, newlines, braces, double quotes,\ntildes or circumflexes.\nBraces {} are used for grouping;\ngenerally speaking,\nanywhere a single character like\n.I x\ncould appear, a complicated construction\nenclosed in braces may be used instead.\nTilde ~ represents a full space in the output,\ncircumflex ^ half as much.\n.PP\n.vs 13p\nSubscripts and superscripts are produced with the keywords\n.B sub\nand\n.B sup.\nThus\n.I \"x sub i\" \nmakes\n$x sub i$, \n.I \"a sub i sup 2\"\nproduces\n$a sub i sup 2$,\nand\n.I \"e sup {x sup 2 + y sup 2}\"\ngives\n$e sup {x sup 2 + y sup 2}$.\n.PP\nFractions are made with\n.BR over :\n.I \"a over b\"\nyields $a over b$.\n.PP\n.B sqrt\nmakes square roots:\n.I \"1 over sqrt {ax sup 2 +bx+c}\"\nresults in\n$1 over sqrt {ax sup 2 +bx+c}$ .\n.PP\nThe keywords\n.B from\nand\n.B to\nintroduce lower and upper\nlimits on arbitrary things:\n$lim from {n-> inf} sum from 0 to n x sub i$\nis made with\n.I \"lim from {n\\-> inf } sum from 0 to n x sub i.\"\n.PP\nLeft and right brackets, braces, etc., of the right height are made with\n.B left\nand\n.B right:\n.I \"left [ x sup 2 + y sup 2 over alpha right ] ~=~1\"\nproduces\n$left [ x sup 2 + y sup 2 over alpha right ] ~=~1$.\nThe\n.B right\nclause is optional.\nLegal characters after \n.B left\nand\n.B right\nare braces, brackets, bars,\n.B c\nand\n.B f\nfor ceiling and floor,\nand \"\" for nothing at all (useful for a right-side-only bracket).\n.PP\nVertical piles of things are made with \n.BR pile ,\n.BR lpile ,\n.BR cpile ,\nand\n.BR rpile :\n.I \"pile {a above b above c}\"\nproduces\n$pile {a above b above c}$.\nThere can be an arbitrary number of elements in a pile.\n.B lpile\nleft-justifies,\n.B pile\nand\n.B cpile\ncenter, with different vertical spacing,\nand \n.B rpile\nright justifies.\n.PP\nMatrices are made with\n.BR matrix :\n.I \"matrix { lcol { x sub i above y sub 2 } ccol { 1 above 2 } }\"\nproduces\n$matrix { lcol { x sub i above y sub 2 } ccol { 1 above 2 } }$.\nIn addition, there is\n.B rcol\nfor a right-justified column.\n.PP\n.vs 12p\nDiacritical marks are made with\n.BR dot ,\n.BR dotdot ,\n.BR hat ,\n.BR tilde ,\n.BR bar ,\n.BR vec ,\n.BR dyad ,\nand\n.BR under :\n.I \"x dot = f(t) bar\"\nis\n$x dot = f(t) bar$,\n.I \"y dotdot bar ~=~ n under\"\nis\n$y dotdot bar ~=~ n under$,\nand\n.I \"x vec ~=~ y dyad\"\nis\n$x vec ~=~ y dyad$.\n.PP\nSizes and font can be changed with\n.B size\n.I n\nor\n.B size\n.BI \\(+- n,\n.BR roman ,\n.BR italic ,\n.BR bold ,\nand\n.BR font\n.I n.\nSize and fonts can be changed globally in a document by\n.B gsize\n.I n\nand\n.B gfont\n.IR n ,\nor by the command-line arguments\n.BI \\-s n\nand\n.BI \\-f n.\n.PP\nNormally subscripts and superscripts are reduced by\n3 point sizes from the previous size;\nthis may be changed by the command-line argument\n.BI \\-p n.\n.PP\nSuccessive display arguments can be lined up.\nPlace\n.B mark\nbefore the desired lineup point in the first equation;\nplace\n.B lineup\nat the place that is to line up vertically in subsequent equations.\n.PP\nShorthands may be defined\nor existing keywords redefined with\n.BI define :\n.I \"define thing % replacement %\"\ndefines a new token called\n.I thing\nwhich will be replaced by\n.I replacement\nwhenever it appears thereafter.\nThe \n.I %\nmay be any character that does not occur in\n.I replacement.\n.PP\nKeywords like \n.I sum\n.EQ\n( sum )\n.EN\n.I int\n.EQ\n( int )\n.EN\n.I inf\n.EQ\n( inf )\n.EN\nand shorthands like\n>=\n.EQ\n(>=)\n.EN\n\\->\n.EQ\n(->),\n.EN\nand\n!=\n.EQ\n( != )\n.EN\nare recognized.\nGreek letters are spelled out in the desired case, as in\n.I alpha\nor\n.I GAMMA.\nMathematical words like sin, cos, log are made Roman automatically.\n.IR Troff (1)\nfour-character escapes like \\e(bs (\\(bs)\ncan be used anywhere.\nStrings enclosed in double quotes \"...\"\nare passed through untouched;\nthis permits keywords to be entered as text,\nand can be used to communicate\nwith \n.I troff\nwhen all else fails.\n.SH \"SEE ALSO\"\n.PP\ntroff(1), tbl(1), ms(7), eqnchar(7)\n.br\nB. W. Kernighan and L. L. Cherry,\n.ul\nTypesetting Mathematics\\(emUser's Guide\n.br\nJ. F. Ossanna,\n.ul\nNROFF/TROFF User's Manual\n.SH BUGS\n.PP\nTo embolden digits, parens, etc.,\nit is necessary to quote them,\nas in `bold \"12.3\"'.\n"
  },
  {
    "path": "share/man/man1/error.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)error.1\t6.2.1 (2.11BSD) 1996/10/21\n.\\\"\n.TH ERROR 1 \"October 21, 1996\"\n.UC 4\n.SH NAME\nerror \\- analyze and disperse compiler error messages\n.SH SYNOPSIS\n.B error\n[\n.B \\-n\n] [\n.B \\-s\n] [\n.B \\-q\n] [\n.B \\-v\n] [\n.B \\-t\nsuffixlist\n] [\n.B \\-I\nignorefile\n] [ name ]\n.SH DESCRIPTION\n.I Error\nanalyzes and optionally disperses the diagnostic error messages\nproduced by a number of compilers and language processors to the source\nfile and line where the errors occurred.  It can replace the painful,\ntraditional methods of scribbling abbreviations of errors on paper, and\npermits error messages and source code to be viewed simultaneously\nwithout machinations of multiple windows in a screen editor.\n.PP\n.I Error\nlooks at the error messages,\neither from the specified file \\fIname\\fR\nor from the standard input,\nand attempts to determine which\nlanguage processor produced each error message,\ndetermines the source file and line number to which the error message refers,\ndetermines if the error message is to be ignored or not,\nand inserts the (possibly slightly modified) error message into\nthe source file as a comment on the line preceding to which the\nline the error message refers.\nError messages which can't be categorized by language processor\nor content are not inserted into any file,\nbut are sent to the standard output.\n.I Error\ntouches source files only after all input has been read.\nBy specifying the\n.B \\-q\nquery option,\nthe user is asked to confirm any potentially\ndangerous (such as touching a file) or verbose action.\nOtherwise\n.I error\nproceeds on its merry business.\nIf the\n.B \\-t\ntouch option and associated suffix list is given, \n.I error\nwill restrict itself to touch only those files with suffices\nin the suffix list.\nError also can be asked (by specifying\n.B \\-v)\nto invoke\n.IR vi (1)\non the files in which error messages were inserted; this obviates\nthe need to remember the names of the files with errors.\n.PP\n.I Error\nis intended to be run\nwith its standard input\nconnected via a pipe to the error message source.\nSome language processors put error messages on their standard error file;\nothers put their messages on the standard output.\nHence, both error sources should be piped together into\n.I error.\nFor example, when using the \\fIcsh\\fP syntax,\n.IP\nmake \\-s lint |\\|& error \\-q \\-v\n.LP\nwill analyze all the error messages produced\nby whatever programs\n.I make\nruns when making lint.\n.PP\n.I Error\nknows about the error messages produced by:\n.I make,\n.I cc,\n.I cpp,\n.I ccom,\n.I as,\n.I ld,\n.I lint,\n.I pi,\n.I pc,\n.I f77,\nand\n.I DEC Western Research Modula-2.\n.I Error\nknows a standard format for error messages produced by\nthe language processors,\nso is sensitive to changes in these formats.\nFor all languages except \n.I Pascal,\nerror messages are restricted to be on one line.\nSome error messages refer to more than one line in more than\none files;\n.I error\nwill duplicate the error message and insert it at\nall of the places referenced.\n.PP\n.I Error\nwill do one of six things with error messages.\n.TP 10\n.I synchronize\nSome language processors produce short errors describing\nwhich file it is processing.\n.I Error \nuses these to determine the file name for languages that\ndon't include the file name in each error message.\nThese synchronization messages are consumed entirely by\n.I error.\n.TP 10\n.I discard\nError messages from\n.I lint\nthat refer to one of the two\n.I lint\nlibraries,\n.I /usr/share/lint/llib-lc\nand\n.I /usr/share/lint/llib-port\nare discarded,\nto prevent accidently touching these libraries.\nAgain, these error messages are consumed entirely by\n.I error.\n.TP 10\n.I nullify\nError messages from\n.I lint\ncan be nullified if they refer to a specific function,\nwhich is known to generate diagnostics which are not interesting.\nNullified error messages are not inserted into the source file,\nbut are written to the standard output.\nThe names of functions to ignore are taken from\neither the file named\n.I .errorrc\nin the users's home directory, \nor from the file named by the\n.B \\-I\noption.\nIf the file does not exist,\nno error messages are nullified.\nIf the file does exist, there must be one function\nname per line.\n.TP 10\n.I not file specific\nError messages that can't be intuited are grouped together,\nand written to the standard output before any files are touched.\nThey will not be inserted into any source file.\n.TP 10\n.I file specific\nError message that refer to a specific file,\nbut to no specific line,\nare written to the standard output when\nthat file is touched.\n.TP 10\n.I true errors\nError messages that can be intuited are candidates for\ninsertion into the file to which they refer.\n.PP\nOnly true error messages are candidates for inserting into\nthe file they refer to.\nOther error messages are consumed entirely by\n.I error\nor are written to the standard output.\n.I Error\ninserts the error messages into the source file on the line\npreceding the line the language processor found in error.\nEach error message is turned into a one line comment for the\nlanguage,\nand is internally flagged\nwith the string ``###'' at\nthe beginning of the error,\nand ``%%%'' at the end of the error.\nThis makes pattern searching for errors easier with an editor,\nand allows the messages to be easily removed.\nIn addition, each error message contains the source line number\nfor the line the message refers to.\nA reasonably formatted source program can be recompiled\nwith the error messages still in it,\nwithout having the error messages themselves cause future errors.\nFor poorly formatted source programs in free format languages,\nsuch as C or Pascal,\nit is possible to insert a comment into another comment,\nwhich can wreak havoc with a future compilation.\nTo avoid this, programs with comments and source\non the same line should be formatted\nso that language statements appear before comments.\n.PP\nOptions available with\n.I error\nare:\n.TP 5\n.B \\-n\nDo\n.I not\ntouch any files; all error messages are sent to the\nstandard output.\n.TP 5\n.B \\-q\nThe user is\n.I queried\nwhether s/he wants to touch the file.\nA ``y'' or ``n'' to the question is necessary to continue.\nAbsence of the\n.B \\-q\noption implies that all referenced files\n(except those referring to discarded error messages)\nare to be touched.\n.TP 5\n.B \\-v\nAfter all files have been touched,\noverlay the visual editor\n.I vi\nwith it set up to edit all files touched,\nand positioned in the first touched file at the first error.\nIf\n.I vi \ncan't be found, try\n.I ex\nor\n.I ed\nfrom standard places.\n.TP 5\n.B \\-t\nTake the following argument as a suffix list.\nFiles whose suffixes do not appear in the suffix list are not touched.\nThe suffix list is dot separated, and ``*'' wildcards work.\nThus the suffix list:\n.IP\n\\&     \".c.y.foo*.h\"\n.IP\nallows\n.I error\nto touch files ending with ``.c'', ``.y'', ``.foo*'' and ``.y''.\n.TP 5\n.B \\-s\nPrint out \n.I statistics\nregarding the error categorization.\nNot too useful.\n.PP\n.I Error\ncatches interrupt and terminate signals,\nand if in the insertion phase,\nwill orderly terminate what it is doing.\n.SH AUTHOR\nRobert Henry\n.SH FILES\n.ta 2i\n~/.errorrc\tfunction names to ignore for \\fIlint\\fP error messages\n.br\n/dev/tty\tuser's teletype\n.SH BUGS\n.PP\nOpens the teletype directly to do user querying.\n.PP\nSource files with links make a new copy of the file with\nonly one link to it.\n.PP\nChanging a language processor's format of error messages\nmay cause \n.I error\nto not understand the error message.\n.PP\n.I Error,\nsince it is purely mechanical,\nwill not filter out subsequent errors caused by `floodgating'\ninitiated by one syntactically trivial error.\nHumans are still much better at discarding these related errors.\n.PP\nPascal error messages belong after the lines affected\n(error puts them before).  The alignment of the `\\||\\|' marking\nthe point of error is also disturbed by\n.I error.\n.PP\n.I Error\nwas designed for work on CRT's at reasonably high speed.\nIt is less pleasant on slow speed terminals, and has never been\nused on hardcopy terminals.\n"
  },
  {
    "path": "share/man/man1/ex.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ex.1\t6.4.1 (2.11BSD) 1996/10/21\n.\\\"\n.TH EX 1 \"October 21, 1996\"\n.UC 4\n.SH NAME\nex, edit \\- text editor\n.SH SYNOPSIS\n.B ex\n[\n.B \\-\n] [\n.B \\-v\n] [\n.B \\-t \ntag\n] [\n.B \\-r\n] [\n\\fB+\\fIcommand\\fR\n] [\n.B \\-l\n]\nname ...\n.br\n.B edit\n[\nex options\n]\n.SH DESCRIPTION\n.I Ex\nis the root of a family of editors:\n.I edit,\n.I ex\nand\n.I vi.\n.I Ex\nis a superset of\n.I ed,\nwith the most notable extension being a display editing facility.\nDisplay based editing is the focus of\n.I vi.\n.PP\nIf you have not used\n.I ed,\nor are a casual user, you will find that the editor\n.I edit\nis convenient for you.\nIt avoids some of the complexities of\n.I ex\nused mostly by systems programmers and persons very familiar with\n.I ed.\n.PP\nIf you have a \\s-2CRT\\s0 terminal, you may wish to use a display\nbased editor; in this case\nsee\n.IR vi (1),\nwhich is a command which focuses on the display editing portion of\n.I ex.\n.SH DOCUMENTATION\nThe document\n.I \"Edit: A tutorial\"\n(USD:14) provides a comprehensive introduction to\n.I edit\nassuming no previous knowledge of computers or the \\s-2UNIX\\s0 system.\n.PP\nThe\n.I \"Ex Reference Manual \\- Version 3.7\"\n(USD:16)\nis a comprehensive and complete manual for the command mode features\nof\n.I ex,\nbut you cannot learn to use the editor by reading it.\nFor an introduction to\nmore advanced forms of editing using the command mode of\n.I ex\nsee the editing documents written by Brian Kernighan for the editor\n.I ed;\nthe material in the introductory and advanced documents works also with\n.I ex.\n.PP\n.I \"An Introduction to Display Editing with Vi\"\n(USD:15)\nintroduces the display editor\n.I vi\nand provides reference material on\n.I vi.\nIn addition, the\n.I \"Vi Quick Reference\"\ncard summarizes the commands\nof\n.I vi\nin a useful, functional way, and is useful with the\n.I Introduction.\n.SH FILES\n.DT\n/usr/share/misc/exstrings\t\terror messages\n.br\n/usr/libexec/exrecover\t\trecover command\n.br\n/usr/sbin/expreserve\t\tpreserve command\n.br\n/etc/termcap\t\t\tdescribes capabilities of terminals\n.br\n~/.exrc\t\t\t\teditor startup file\n.br\n/tmp/Ex\\fInnnnn\\fR\t\t\teditor temporary\n.br\n/tmp/Rx\\fInnnnn\\fR\t\t\tnamed buffer temporary\n.br\n/usr/preserve\t\t\tpreservation directory\n.SH SEE ALSO\nawk(1), ed(1), grep(1), sed(1), grep(1), vi(1), termcap(5), environ(7)\n.SH AUTHOR\nOriginally written by William Joy\n.br\nMark Horton has maintained the editor since version 2.7, adding macros,\nsupport for many unusual terminals,\nand other features such as word abbreviation mode.\n.SH BUGS\nThe\n.I undo\ncommand causes all marks to be lost on lines changed and then restored\nif the marked lines were changed.\n.PP\n.I Undo\nnever clears the buffer modified condition.\n.PP\nThe\n.I z\ncommand prints a number of logical rather than physical lines.\nMore than a screen full of output may result if long lines are present.\n.PP\nFile input/output errors don't print a name if the command line \\fB`\\-'\\fR\noption is used.\n.PP\nThere is no easy way to do a single scan ignoring case.\n.PP\nThe editor does not warn if text is placed in named buffers and not used\nbefore exiting the editor.\n.PP\nNull characters are discarded in input files, and cannot appear in resultant\nfiles.\n"
  },
  {
    "path": "share/man/man1/expand.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)expand.1\t6.2 (Berkeley) 5/9/86\n.\\\"\n.TH EXPAND 1 \"May 9, 1986\"\n.UC 4\n.SH NAME\nexpand, unexpand \\- expand tabs to spaces, and vice versa\n.SH SYNOPSIS\n.B expand\n[\n\\-tabstop\n] [\n\\-tab1,tab2,...,tabn\n] [\nfile ...\n]\n.br\n.B unexpand\n[\n.B \\-a\n] [\nfile ...\n]\n.SH DESCRIPTION\n.I Expand\nprocesses the named files or the standard input writing\nthe standard output with tabs changed into blanks.\nBackspace characters are preserved into the output and decrement\nthe column count for tab calculations.\n.I Expand\nis useful for pre-processing character files\n(before sorting, looking at specific columns, etc.) that\ncontain tabs.\n.PP\nIf a single\n.I tabstop\nargument is given, then tabs are set\n.I tabstop\nspaces apart instead of the default 8.\nIf multiple tabstops are given then the tabs are set at those\nspecific columns.\n.PP\n.I Unexpand\nputs tabs back into the data from the standard input or the named\nfiles and writes the result on the standard output.\nBy default, only leading blanks and tabs\nare reconverted to maximal strings of tabs.  If the\n.B \\-a\noption is given, then tabs are inserted whenever they would compress the\nresultant file by replacing two or more characters.\n"
  },
  {
    "path": "share/man/man1/expr.1",
    "content": ".\\\"\t@(#)expr.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH EXPR 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nexpr \\- evaluate arguments as an expression\n.SH SYNOPSIS\n.B expr\narg\n.B .\\|.\\|.\n.SH DESCRIPTION\nThe arguments are taken as an expression.\nAfter evaluation, the result is written on the standard output.\nEach token of the expression is a separate argument.\n.PP\nThe operators and keywords are listed below.\nThe list is in order of increasing precedence,\nwith equal precedence operators grouped.\n.TP\n.I expr | expr\nyields the first\n.I expr\nif it is neither null nor `0', otherwise\nyields the second\n.I expr.\n.TP\n.I expr & expr\nyields the first\n.I expr\nif neither\n.I expr\nis null or `0', otherwise yields `0'.\n.TP\n.I expr relop expr\nwhere\n.I relop is one of\n< <= = != >= >,\nyields `1' if the indicated comparison is true, `0' if false.\nThe comparison is numeric if both\n.I expr\nare integers, otherwise lexicographic.\n.TP\n.IR expr \" + \" expr\n.br\n.ns\n.TP\n.IR expr \" \\- \" expr\n.br\naddition or subtraction of the arguments.\n.TP\n.IR expr \" * \" expr\n.br\n.ns\n.TP\n.IR expr \" / \" expr\n.br\n.ns\n.TP\n.IR expr \" % \" expr\n.br\nmultiplication, division, or remainder of the arguments.\n.TP\n.IR expr \" : \" expr\nThe matching operator compares the string first argument\nwith the regular expression second argument;\nregular expression syntax is the same as that of\n.IR ed (1).\nThe\n\\fB\\\\(\\|.\\|.\\|.\\|\\\\)\\fP\npattern symbols can be used to select a portion of the\nfirst argument.\nOtherwise,\nthe matching operator yields the number of characters matched\n(`0' on failure).\n.TP\n.RI ( \" expr \" )\nparentheses for grouping.\n.PP\nExamples:\n.PP\nTo add 1 to the Shell variable\n.IR a :\n.IP\na=\\`expr $a + 1\\`\n.PP\nTo find the filename part (least significant part)\nof the pathname stored in variable\n.I a,\nwhich may or may not contain `/':\n.IP\nexpr $a : \\'.*/\\e(\\^.*\\e)\\' \\'\\^|\\' $a\n.LP\nNote the quoted Shell metacharacters.\n.SH \"SEE ALSO\"\nsh(1), test(1)\n.SH DIAGNOSTICS\n.I Expr\nreturns the following exit codes:\n.PP\n\t0\tif the expression is neither null nor `0',\n.br\n\t1\tif the expression\nis null or `0',\n.br\n\t2\tfor invalid expressions.\n"
  },
  {
    "path": "share/man/man1/f77.1",
    "content": ".TH F77 1 \"October 22, 1996\"\n.UC\n.SH NAME\nf77 \\- Fortran77 compiler\n.SH SYNTAX\n.B f77\n[ option ] ... file ...\n.SH DESCRIPTION\n.I F77\nis the UNIX Fortran77 compiler.\nIt accepts several types of arguments:\n.PP\nArguments whose names end with `.f' are taken to be\nFortran77 source programs;\nthey are compiled, and\neach object program is left on the file in the current directory\nwhose name is that of the source with `.o' substituted\nfor '.f'.\n.PP\nArguments whose names end with `.r' or `.e' are taken to be Ratfor or EFL\nsource programs, respectively; these are first transformed by the\nappropriate preprocessor, then compiled by f77.\n.PP\nIn the same way,\narguments whose names end with `.c' or `.s' are taken to be C or assembly source programs\nand are compiled or assembled, producing a `.o' file.\n.PP\nThe following options have the same meaning as in \\fIcc\\fP\\|(1).\nSee \\fIld\\fP\\|(1)\nfor load-time options.\n.TP\n.B \\-\\^c\nSuppress loading and produce `.o' files for each source \nfile.\n.TP\n.B \\-\\^p\nPrepare object files for profiling, see \\fIprof\\fP\\|(1)\n.TP\n.SM\n.B \\-\\^O\nInvoke an\nobject-code optimizer.\n.TP\n.SM\n.B \\-\\^S\nCompile the named programs, and leave the\nassembler-language output on corresponding files suffixed `.s'.\n(No `.o' is created.).\n.TP\n.B \\-\\^f\nUse a floating point interpreter (for PDP11's that lack\n11/70-style floating point).\n.TP\n.BR \\-\\^o \" output\"\nName the final output file\n.I output\ninstead of `a.out'.\n.PP\nThe following options are peculiar to\n.IR f77 :\n.TP\n.SM\n.BR \\-\\^onetrip\nCompile DO loops that are performed at least once if reached.\n(Fortran77 DO loops are not performed at all if the upper limit is smaller than the lower limit.)\n.TP\n.BR \\-\\^u\nMake the default type of a variable `undefined' rather than using the default Fortran rules.\n.TP\n.BR \\-\\^C\nCompile code to check that subscripts are within declared array bounds.\n.TP\n.BR \\-\\^w\nSuppress all warning messages.\nIf the option is `\\-w66', only Fortran 66 compatibility warnings are suppressed.\n.TP\n.BR \\-\\^F\nApply EFL and Ratfor preprocessor to relevant files, put the result in the file\nwith the suffix changed to `.f', but do not compile.\n.TP\n.BR \\-\\^m\nApply the M4 preprocessor to each `.r' or `.e' file before transforming\nit with the Ratfor or EFL preprocessor.\n.TP\n.TP\n.BI \\-\\^E x\nUse the string\n.I x\nas an EFL option in processing `.e' files.\n.TP\n.BI \\-\\^R x\nUse the string \n.I x\nas a Ratfor option in processing `.r' files.\n.TP\n.BR \\-\\^U\nDo not convert upper case letters to lower case.\n.TP\n.BR \\-\\^I 2\nMake default integer size 16 bit.\n.TP\n.BR \\-\\^I 4\nMake default integer size 32 bit (default).\n.TP\n.BR \\-\\^v\nVerbose.  Print information showing what compiler is doing.\n.TP\n.BR \\-\\^d\nDebug prints out intermediate information, leaves temporary files in\n\\fI/tmp\\fP and often produces a core file.\n.PP\nOther arguments\nare taken\nto be either loader option arguments, or F77-compatible\nobject programs, typically produced by an earlier\nrun,\nor perhaps libraries of F77-compatible routines.\nThese programs, together with the results of any\ncompilations specified, are loaded (in the order\ngiven) to produce an executable program with name\n`a.out'.\n.SH FILES\n.nf\n.ta 2i\nfile.[fresc]\tinput file\nfile.o\tobject file\na.out\tloaded output\n./fort[pid].?\ttemporary\n/usr/libexec/f77pass1\tcompiler pass 1\n/lib/c1\tcompiler pass 2\n/lib/c2\toptional optimizer\n/usr/lib/libF77.a\tintrinsic function library\n/usr/lib/libI77.a\tFortran I/O library\n/usr/lib/libU77.a\tFortran system call library\n/lib/libc.a\tC library, see section 3\n/temp/fortPID.[xsad SopzA]\ttemporary files\n.fi\n.PP\nDifferent versions of the compiler tools may be used with the following\nflags followed immediately (no space) by the path name of the desired module:\n.PP\n.ta \\w'\\-TM1234567 'u +\\w'macro pack12345  'u\n.nf\n\\-T1\tpass1\t/lib/f77pass1\n\\-T2\tpass2\t/lib/c1\n\\-Ta\tassembler\t/bin/as\n\\-Tl\tloader\t/bin/ld\n\\-TF\tfootname\t/lib/crt0.o\n\\-TM\tmacro pack\tm4\n.fi\n.SH \"SEE ALSO\"\nS. I. Feldman,\nP. J. Weinberger,\n.I\nA Portable Fortran77 Compiler\n.br\ncc(1), ld(1), prof(1)\n.SH DIAGNOSTICS\nThe diagnostics produced by\n.I f77\nitself are intended to be\nself-explanatory.\nOccasional messages may be produced by the loader.\n.TP\n\\-d\ncauses the intermediate files to be saves in \\fI/tmp\\fP and causes the\ncompiler to print out what it is doing.\n.PP\nRun-time diagnostics for the input/output library are as follows:\n.sp\n.nf\n/* 100 */\t\"error in format\"\n\t\tSee error message output for the location\n\t\tof the error in the format. Can be caused\n\t\tby more than 10 levels of nested (), or\n\t\tan extremely long format statement.\n.bp\n/* 101 */\t\"illegal unit number\"\n\t\tIt is illegal to close logical unit 0.\n\t\tNegative unit numbers are not allowed.\n\t\tThe upper limit is system dependent.\n\n/* 102 */\t\"formatted io not allowed\"\n\t\tThe logical unit was opened for\n\t\tunformatted I/O.\n\n/* 103 */\t\"unformatted io not allowed\"\n\t\tThe logical unit was opened for\n\t\tformatted I/O.\n\n/* 104 */\t\"direct io not allowed\"\n\t\tThe logical unit was opened for sequential\n\t\taccess, or the logical record length was\n\t\tspecified as 0.\n\n/* 105 */\t\"sequential io not allowed\"\n\t\tThe logical unit was opened for direct\n\t\taccess I/O.\n\n/* 106 */\t\"can't backspace file\"\n\t\tThe file associated with the logical unit\n\t\tcan't seek. May be a device or a pipe.\n\n/* 107 */\t\"off beginning of record\"\n\t\tThe format specified a left tab off the\n\t\tbeginning of the record.\n\n/* 108 */\t\"can't stat file\"\n\t\tThe system can't return status information\n\t\tabout the file. Perhaps the directory is\n\t\tunreadable.\n\n/* 109 */\t\"no * after repeat count\"\n\t\tRepeat counts in list-directed I/O must be\n\t\tfollowed by an * with no blank spaces.\n\n.DE\n.DS\n/* 110 */\t\"off end of record\"\n\t\tA formatted write tried to go beyond the\n\t\tlogical end-of-record. An unformatted read\n\t\tor write will also cause this.\n\n/* 111 */\t\"truncation failed\"\n\t\tThe truncation of external sequential files\n\t\ton 'close', 'backspace', or 'rewind' tries\n\t\tto do a copy. It failed. Perhaps the temp\n\t\tfile couldn't be created.\n\n/* 112 */\t\"incomprehensible list input\"\n\t\tList input has to be just right.\n\n/* 113 */\t\"out of free space\"\n\t\tThe library dynamically creates buffers for\n\t\tinternal use. You ran out of memory for this.\n\t\tYour program is too big!\n\n/* 114 */\t\"unit not connected\"\n\t\tThe logical unit was not open.\n\n/* 115 */\t\"read unexpected character\"\n\t\tCertain format conversions can't tolerate\n\t\tnon-numeric data. Logical data must be\n\t\tT or F.\n\n/* 116 */\t\"blank logical input field\"\n\n/* 117 */\t\"'new' file exists\"\n\t\tYou tried to open an existing file with\n\t\t\"status='new'\".\n\n/* 118 */\t\"can't find 'old' file\"\n\t\tYou tried to open a nonexistent file\n\t\twith \"status='old'\".\n\n/* 119 */\t\"unknown system error\"\n\t\tShouldn't happen, but .....\n\t\t(Send me a documented example.)\n\n/* 120 */\t\"requires seek ability\"\n\t\tDirect access requires seek ability.\n\t\tSequential unformatted I/O requires seek\n\t\tability on the file due to the special\n\t\tdata structure required. Tabbing left\n\t\talso requires seek ability.\n\n/* 121 */\t\"illegal argument\"\n\t\tCertain arguments to 'open', etc. will be\n\t\tchecked for legitimacy. Often only non-\n\t\tdefault forms are looked for.\n\n/* 122 */\t\"negative repeat count\"\n\n/* 123 */\t\"illegal operation for channel or device\"\n.fi\n.SH BUGS\nThe Fortran66 subset of the language has been\nexercised extensively;\nthe newer features have not.\n.PP\nFortran style read/write routines take up 23 Kbytes of\naddressing space.\n.PP\nThe compiler is not intelligent enough to know when to\nsplit up assemblies and loads. Occasionally this causes\nthe loader \\fIld\\fP\\|(1) to produce the informative \\fBlocal symbol botch\\fP\nerror message when local symbols like argument names are\ndefined with different types. Thus one must split up such\noffensive modules into separate compilations.\n.PP\nAll mathematics for reals is done in double precision.\n.br\nInteger*4 byte alignment is unlike DEC and everyone else's.\n.br\nThere is no symbolic debugger.\n.PP\nThe optimizer should be used with caution.  It is known to occasionally\nproduce incorrect code.\n.SH EXAMPLES\n.TP\n\\fBf77  \\-O  \\-c  myprog.f\\fP\ncreates myprog.o using C optimizer\n.TP\n\\fBf77  \\-i  \\-O myprog.f  another.f  anon.o  \\-lplot\\fP\ncompiles .f files, loads all files using separate i&d space and linking\nin routines in the plot library.\n.TP\n\\fBf77 myprog.f  mine.c  >&errors\\fP\nCompiles and loads both files putting error output into file called errors.  \nThis is the C shell (\\fBcsh\\fP) version.\nThe Bourne shell (\\fBsh\\fP) version is:\n.LP\n\\fBf77  myprog.f  mine.c  2>errors  1>errors\\fP\n"
  },
  {
    "path": "share/man/man1/false.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)false.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH FALSE 1 \"April 29, 1985\"\n.UC 5\n.SH NAME\nfalse, true \\- provide truth values\n.SH SYNOPSIS\n.B true\n.PP\n.B false\n.SH DESCRIPTION\n.I True\nand\n.I false\nare usually used in a Bourne shell script.\nThey test for the appropriate status \"true\" or \"false\" before running \n(or failing to run) a list of commands.  \n.SH EXAMPLE\n.IP\n.nf\n     while false\n     do\n          command list \n     done\n.SH \"SEE ALSO\"\ncsh(1),\nsh(1),\ntrue(1)\n.SH DIAGNOSTICS\n.I False\nhas exit status nonzero.\n"
  },
  {
    "path": "share/man/man1/file.1",
    "content": ".\\\"\t@(#)file.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH FILE 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nfile \\- determine file type\n.SH SYNOPSIS\n.B file\nfile ...\n.SH DESCRIPTION\n.I File\nperforms a series of tests on each argument\nin an attempt to classify it.\nIf an argument appears to be ascii,\n.I file\nexamines the first 512 bytes\nand tries to guess its language.\n.SH BUGS\nIt often makes mistakes.\nIn particular it often suggests that\ncommand files are C programs.\n.PP\nDoes not recognize Pascal or LISP.\n"
  },
  {
    "path": "share/man/man1/find.1",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)find.1\t6.3.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH FIND 1 \"October 11, 1996\"\n.AT 3\n.SH NAME\nfind \\- find files\n.SH SYNOPSIS\n.B find\npathname-list expression\n.br \n.B find\npattern\n.SH DESCRIPTION\nIn the first form above,\n.I find\nrecursively descends\nthe directory hierarchy for\neach pathname in the\n.I pathname-list\n(i.e., one or more pathnames)\nseeking files that match a boolean\n.I expression\nwritten in the primaries given below.\nIn the descriptions, the argument\n.I n\nis used as a decimal integer\nwhere\n.I +n\nmeans more than\n.I n,\n.I \\-n\nmeans less than\n.I n\nand\n.I n\nmeans exactly\n.IR n .\n.PP\nThe second form rapidly searches a database for all pathnames\nwhich match\n.IR pattern .\nUsually the database is recomputed\nweekly and contains the pathnames\nof all files which are publicly accessible.\nIf escaped, normal shell\n\\*(lqglobbing\\*(rq characters (`*', `?', `[', and ']')\nmay be used in\n.IR pattern ,\nbut the matching differs in that no characters\n.RI ( e.g. \" `/')\"\nhave to be matched explicitly.\nAs a special case, a simple\n.I pattern\ncontaining no globbing characters\nis matched as though it were\n.IR *pattern* ;\nif any globbing character appears\nthere are no implicit globbing characters.\n.TP 10n\n.BR \\-name \" filename\"\nTrue if the\n.I filename\nargument matches the current file name.\nNormal\nshell\nargument syntax may be used if escaped (watch out for\n`[', `?' and `*').\n.TP\n.BR \\-perm \" onum\"\nTrue if the file permission flags\nexactly\nmatch the\noctal number\n.I onum\n(see\n.IR  chmod (1)).\nIf\n.I onum\nis prefixed by a minus sign,\nmore flag bits (017777, see\n.IR   stat (2))\nbecome significant and\nthe flags are compared:\n.IR (flags&onum)==onum .\n.TP\n.BR \\-type \" c\"\nTrue if the type of the file\nis\n.I c,\nwhere\n.I c\nis\n.B \"b, c, d, f, l\"\nor\n.B s\nfor\nblock special file, character special file,\ndirectory, plain file, symbolic link, or socket.\n.TP\n.BR \\-links \" n\"\nTrue if the file has\n.I n\nlinks.\n.TP\n.BR \\-user \" uname\"\nTrue if the file belongs to the user\n.I uname\n(login name or numeric user ID).\n.TP\n.B \\-nouser\nTrue if the file belongs to a user\n.I not\nin the /etc/passwd database.\n.TP\n.BR \\-group \" gname\"\nTrue if the file belongs to group\n.I gname\n(group name or numeric group ID).\n.TP\n.B \\-nogroup\nTrue if the file belongs to a group\n.I not\nin the /etc/group database.\n.TP\n.BR \\-size \" n\"\nTrue if the file is\n.I n\nblocks long (512 bytes per block).\n.TP\n.BR \\-inum \" n\"\nTrue if the file has inode number\n.I n.\n.TP\n.BR \\-atime \" n\"\nTrue if the file has been accessed in\n.I n\ndays.\n.TP\n.BR \\-mtime \" n\"\nTrue if the file has been modified in\n.I n\ndays.\n.TP\n.BR \\-exec \" command\"\nTrue if the executed command returns\na zero value as exit status.\nThe end of the command must be punctuated by an escaped\nsemicolon.\nA command argument `{}' is replaced by the\ncurrent pathname.\n.TP\n.BR \\-ok \" command\"\nLike\n.B \\-exec\nexcept that the generated command is written on\nthe standard output, then the standard input is read\nand the command executed only upon response\n.BR y .\n.TP\n.B  \\-print\nAlways true;\ncauses the current pathname to be printed.\n.TP\n.B  \\-ls\nAlways true;\ncauses current pathname to be printed together\nwith its associated statistics.\nThese include (respectively) inode number,\nsize in kilobytes (1024 bytes),\nprotection mode,\nnumber of hard links,\nuser,\ngroup,\nsize in bytes,\nand modification time.\nIf the file is a special file\nthe size field will instead contain the major and minor\ndevice numbers.\nIf the file is a symbolic link the\npathname of the linked-to file is printed preceded by ``->''.\nThe format is identical to that of ``ls -gilds''\n(note however that formatting is done internally,\nwithout executing the ls program).\n.TP\n.BR \\-newer \" file\"\nTrue if\nthe current file has been modified more recently than the argument\n.I file.\n.TP\n.BR \\-cpio \" file\"\nWrite the current file on the argument\n.I file\nin\n.I cpio\nformat.\n.TP\n.B \\-xdev\nAlways true;\ncauses find\n.I not\nto traverse down into a file system different\nfrom the one on which current\n.I argument\npathname resides.\n.PP\nThe primaries may be combined using the following operators\n(in order of decreasing precedence):\n.TP 4\n1)\nA parenthesized group of primaries and operators\n(parentheses are special to the Shell and must be escaped).\n.TP 4\n2)\nThe negation of a primary\n(`!' is the unary\n.I not\noperator).\n.TP 4\n3)\nConcatenation of primaries\n(the\n.I and\noperation\nis implied by the juxtaposition of two primaries).\n.TP 4\n4)\nAlternation of primaries\n.RB \"(`\" \\-o \"' is the\"\n.I or\noperator).\n.SH EXAMPLES\n.PP\nTo find all accessible files whose pathname contains `find':\n.IP\nfind find\n.PP\nTo typeset all variants of manual pages for `ls':\n.IP \nvtroff -man `find '*man*/ls.?'`\n.PP\nTo remove all files named\n`a.out' or `*.o' that have not been accessed for a week:\n.IP \"\" .2i\nfind / \\e( \\-name a.out \\-o \\-name '*.o' \\e) \\-atime +7 \\-exec rm {} \\e\\;\n.SH FILES\n.nf\n.ta \\w'/var/db/find.codes     'u\n/etc/passwd\n/etc/group\n/var/db/find.codes\tcoded pathnames database\n.fi\n.SH \"SEE ALSO\"\nsh(1), test(1), fs(5)\n.br\nRelevant paper in February, 1983 issue of\n.I ;login:.\n.SH BUGS\nThe first form's syntax is painful, and\nthe second form's exact semantics is confusing and\ncan vary from site to site.\n.PP\nMore than one `-newer' option does not work properly.\n"
  },
  {
    "path": "share/man/man1/fmt.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)fmt.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH FMT 1 \"April 29, 1985\"\n.UC\n.SH NAME\nfmt \\- simple text formatter\n.SH SYNOPSIS\n.B fmt\n[\nname ...\n]\n.SH DESCRIPTION\n.I Fmt\nis a simple text formatter which reads the concatenation of input\nfiles (or standard input if none are given) and produces on\nstandard output a version of its input with lines as close to\n72 characters long as possible.  The spacing at the beginning\nof the input lines is preserved in the output, as are blank lines\nand interword spacing.\n.PP\n.I Fmt\nis meant to format mail messages prior to sending, but may also be useful\nfor other simple tasks.\nFor instance,\nwithin visual mode of the\n.I ex\neditor (e.g.\n.IR vi )\nthe command\n.br\n\t!}fmt\n.br\nwill reformat a paragraph,\nevening the lines.\n.SH \"SEE ALSO\"\nnroff(1), mail(1)\n.SH AUTHOR\nKurt Shoens\n.SH BUGS\nThe program was designed to be simple and fast \\- for more complex\noperations, the standard text processors are likely to be more appropriate.\n"
  },
  {
    "path": "share/man/man1/fold.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)fold.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH FOLD 1 \"April 29, 1985\"\n.UC\n.SH NAME\nfold \\- fold long lines for finite width output device\n.SH SYNOPSIS\n.B fold\n[\n\\-width\n] [\nfile ...\n]\n.SH DESCRIPTION\n.I Fold\nis a filter which will fold the contents of the specified files,\nor the standard input if no files are specified,\nbreaking the lines to have maximum width\n.I width.\nThe default for\n.I width\nis 80.\n.I Width\nshould be a multiple of 8 if tabs are present, or the tabs should\nbe expanded using\n.IR expand (1)\nbefore coming to\n.I fold.\n.SH SEE\\ ALSO\nexpand(1)\n.SH BUGS\nIf underlining is present it may be messed up by folding.\n"
  },
  {
    "path": "share/man/man1/fpr.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)fpr.1\t6.2 (Berkeley) 5/7/86\n.\\\"\n.TH FPR 1 \"May 7, 1986\"\n.UC 5\n.ds f. fpr.tbl\n.SH NAME\nfpr \\- print Fortran file\n.SH SYNOPSIS\n.B fpr\n.SH DESCRIPTION\n.I Fpr\nis a filter that transforms files formatted according to\nFortran's carriage control conventions into files formatted\naccording to UNIX line printer conventions.\n.PP\n.I Fpr\ncopies its input onto its output, replacing the carriage\ncontrol characters with characters that will produce the intended\neffects when printed using\n.IR lpr (1).\nThe first character of each line determines the vertical spacing as follows:\n\n.if t \\{\\\n.\\\"\ttbl input for vertical spacing table\n.\\\"\t.TS\n.\\\"\tcenter box;\n.\\\"\tc | l.\n.\\\"\tCharacter\tVertical Space Before Printing\n.\\\"\t_\n.\\\"\tBlank\tOne line\n.\\\"\t0\tTwo lines\n.\\\"\t1\tTo first line of next page\n.\\\"\t+\tNo advance\n.\\\"\t.TE\n.\\\"\tend of tbl input for vertical spacing table\n.\\\"\ttbl output for vertical spacing table\n.TS\n.if \\n+(b.=1 .nr d. \\n(.c-\\n(c.-1\n.de 35\n.ps \\n(.s\n.vs \\n(.vu\n.in \\n(.iu\n.if \\n(.u .fi\n.if \\n(.j .ad\n.if \\n(.j=0 .na\n..\n.nf\n.nr #~ 0\n.if n .nr #~ 0.6n\n.ds #d .d\n.if \\(ts\\n(.z\\(ts\\(ts .ds #d nl\n.fc\n.nr 33 \\n(.s\n.rm 80 81\n.nr 80 0\n.nr 38 \\w\u0002Character\u0002\n.if \\n(80<\\n(38 .nr 80 \\n(38\n.nr 38 \\w\u0002Blank\u0002\n.if \\n(80<\\n(38 .nr 80 \\n(38\n.nr 38 \\w\u00020\u0002\n.if \\n(80<\\n(38 .nr 80 \\n(38\n.nr 38 \\w\u00021\u0002\n.if \\n(80<\\n(38 .nr 80 \\n(38\n.nr 38 \\w\u0002+\u0002\n.if \\n(80<\\n(38 .nr 80 \\n(38\n.80\n.rm 80\n.nr 81 0\n.nr 38 \\w\u0002Vertical Space Before Printing\u0002\n.if \\n(81<\\n(38 .nr 81 \\n(38\n.nr 38 \\w\u0002One line\u0002\n.if \\n(81<\\n(38 .nr 81 \\n(38\n.nr 38 \\w\u0002Two lines\u0002\n.if \\n(81<\\n(38 .nr 81 \\n(38\n.nr 38 \\w\u0002To first line of next page\u0002\n.if \\n(81<\\n(38 .nr 81 \\n(38\n.nr 38 \\w\u0002No advance\u0002\n.if \\n(81<\\n(38 .nr 81 \\n(38\n.81\n.rm 81\n.nr 38 1n\n.nr 79 0\n.nr 40 \\n(79+(1*\\n(38)\n.nr 80 +\\n(40\n.nr 41 \\n(80+(3*\\n(38)\n.nr 81 +\\n(41\n.nr TW \\n(81\n.nr TW +1*\\n(38\n.if t .if (\\n(TW+\\n(.o)>7.65i .tm Table at line 45 file fpr.tbl is too wide - \\n(TW units\n.ne 5v+2p\n.nr #I \\n(.i\n.in +(\\n(.lu-\\n(TWu-\\n(.iu)/2u\n.fc \u0002 \u0003\n.nr #T 0-1\n.nr #a 0-1\n.nr #a 0-1\n.eo\n.de T#\n.ds #d .d\n.if \\(ts\\n(.z\\(ts\\(ts .ds #d nl\n.mk ##\n.nr ## -1v\n.ls 1\n.if \\n(#T>=0 .nr #a \\n(#T\n.if \\n(T. .vs \\n(.vu-\\n(.sp\n.if \\n(T. \\h'|0'\\s\\n(33\\l'|\\n(TWu\\(ul'\\s0\n.if \\n(T. .vs\n.if \\n(#a>=0 .sp -1\n.if \\n(#a>=0 \\h'|0'\\s\\n(33\\h'-\\n(#~u'\\L'|\\n(#au-1v'\\s0\\v'\\n(\\*(#du-\\n(#au+1v'\\h'|\\n(TWu'\n.if \\n(#a>=0 .sp -1\n.if \\n(#a>=0 \\h'(|\\n(41u+|\\n(80u)/2u'\\s\\n(33\\h'-\\n(#~u'\\L'|\\n(#au-1v'\\s0\\v'\\n(\\*(#du-\\n(#au+1v'\\h'|\\n(TWu'\n.if \\n(#a>=0 .sp -1\n.if \\n(#a>=0 \\h'|\\n(TWu'\\s\\n(33\\h'-\\n(#~u'\\L'|\\n(#au-1v'\\s0\\v'\\n(\\*(#du-\\n(#au+1v'\n.ls\n..\n.ec\n.nr 36 \\n(.v\n.vs \\n(.vu-\\n(.sp\n\\h'|0'\\s\\n(33\\l'|\\n(TWu\\(ul'\\s0\n.vs \\n(36u\n.mk #a\n.ta \\n(80u \\n(81u \n.nr 31 \\n(.f\n.nr 35 1m\n\\&\\h'|\\n(40u'\u0002\u0003Character\u0003\u0002\\h'|\\n(41u'\u0002Vertical Space Before Printing\u0003\u0002\n.nr 36 \\n(.v\n.vs \\n(.vu-\\n(.sp\n\\h'|0'\\s\\n(33\\l'|\\n(TWu\\(ul'\\s0\n.vs \\n(36u\n.ta \\n(80u \\n(81u \n.nr 31 \\n(.f\n.nr 35 1m\n\\&\\h'|\\n(40u'\u0002\u0003Blank\u0003\u0002\\h'|\\n(41u'\u0002One line\u0003\u0002\n.ta \\n(80u \\n(81u \n.nr 31 \\n(.f\n.nr 35 1m\n\\&\\h'|\\n(40u'\u0002\u00030\u0003\u0002\\h'|\\n(41u'\u0002Two lines\u0003\u0002\n.ta \\n(80u \\n(81u \n.nr 31 \\n(.f\n.nr 35 1m\n\\&\\h'|\\n(40u'\u0002\u00031\u0003\u0002\\h'|\\n(41u'\u0002To first line of next page\u0003\u0002\n.ta \\n(80u \\n(81u \n.nr 31 \\n(.f\n.nr 35 1m\n\\&\\h'|\\n(40u'\u0002\u0003+\u0003\u0002\\h'|\\n(41u'\u0002No advance\u0003\u0002\n.fc\n.nr T. 1\n.T# 1\n.in \\n(#Iu\n.35\n.nr #a 0\n.TE\n.if \\n-(b.=0 .nr c. \\n(.c-\\n(d.-9\n.\\\"\tend of tbl output for vertical spacing table\n.\\}\n.if n \\{\\\n.nf\n    +---------------+--------------------------------+\n    |   Character   | Vertical Space Before Printing |\n    |---------------+--------------------------------|\n    |     Blank     | One line                       |\n    |       0       | Two lines                      |\n    |       1       | To first line of next page     |\n    |       +       | No advance                     |\n    +---------------+--------------------------------+\n.fi\n.\\}\n\n.PP\nA blank line is treated as if its first\ncharacter is a blank. A blank that appears as a carriage control\ncharacter is deleted. A zero is changed to a newline.  A one is\nchanged to a form feed. The effects of a \"+\" are simulated using\nbackspaces.\n.SH EXAMPLES\na.out | fpr | lpr\n.PP\nfpr < f77.output | lpr\n.SH BUGS\nResults are undefined for input lines longer than 170 characters.\n"
  },
  {
    "path": "share/man/man1/from.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)from.1\t6.2 (Berkeley) 4/20/86\n.\\\"\n.TH FROM 1 \"April 20, 1986\"\n.UC 4\n.SH NAME\nfrom \\- who is my mail from?\n.SH SYNOPSIS\n.B from\n[\n.B \\-s\nsender\n]\n[\nuser\n]\n.SH DESCRIPTION\n.I From\nprints out the mail header lines in your mailbox file\nto show you who your mail is from.\nIf\n.I user\nis specified, then \\fIuser\\fP's mailbox is examined instead of your own.\nIf the -s option is given, then only headers for mail sent by\n.I sender\nare printed.\n.SH FILES\n/usr/spool/mail/*\n.SH \"SEE ALSO\"\nbiff(1), mail(1)\n"
  },
  {
    "path": "share/man/man1/fsplit.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)fsplit.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH FSPLIT 1 \"April 29, 1985\"\n.UC 5\n.SH NAME\nfsplit \\- split a multi-routine Fortran file into individual files\n.SH SYNOPSIS\n.B fsplit\n[ \n.B -e \nefile] ... [ file ]\n.SH DESCRIPTION\n.B Fsplit\ntakes as input either a file or standard input containing Fortran source code.\nIt attempts to split the input into separate routine files of the\nform\n.I name.f,\nwhere\n.I name\nis the name of the program unit (e.g. function, subroutine, block data or\nprogram).  The name for unnamed block data subprograms has the form\n.I blkdtaNNN.f\nwhere NNN is three digits and a file of this name does not already exist.\nFor unnamed main programs the name has the form\n.I mainNNN.f.\nIf there is an error in classifying a program unit, or if\n.I name.f\nalready exists,\nthe program unit will be put in a file of the form \n.I zzzNNN.f\nwhere \n.I zzzNNN.f \ndoes not already exist.\n.PP\nNormally each subprogram unit is split into a separate file.  When the\n.I -e\noption is used, only the specified subprogram units are split into separate\nfiles.  E.g.:\n.nf\n\tfsplit -e readit -e doit prog.f\n.fi\nwill split readit and doit into separate files.\n.SH DIAGNOSTICS\nIf names specified via the \n.I -e\noption are not found, a diagnostic is written to \n.I standard \n.I error.\n.SH AUTHOR\nAsa Romberger and Jerry Berkman\n.SH BUGS\n.I Fsplit\nassumes the subprogram name is on the first noncomment line of the subprogram\nunit.  Nonstandard source formats may confuse \n.I fsplit.\n.PP\nIt is hard to use \n.I -e\nfor unnamed main programs and block data subprograms since you must \npredict the created file name.\n"
  },
  {
    "path": "share/man/man1/gcore.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)gcore.1\t1.1 (2.11BSD GTE) 4/15/94\n.\\\"\n.TH GCORE 1 \"April 15, 1994\"\n.UC 5\n.SH NAME\ngcore \\- get core image of running process\n.SH SYNOPSIS\n.B gcore\n[\\fB-s\\fP][\\fB-c core\\fP] \\fIpid\\fP\n.SH DESCRIPTION\n.I gcore\ncreates a core image of each specified process,\nsuitable for use with\n.IR adb (1).\nBy default the core image is written to the file \\fI<pid>.core\\fP.\n.PP\nThe options are:\n.TP\n\\fB-c\\fP\nWrite the core file to the specified file instead of \\fI<pid>.core\\fP.\n.TP\n\\fB-s\\fP\nStop the process while creating the core image and resume it when done.\nThis makes sure that the core dump will be in a consistent state.  The \nprocess is resumed even if it was already stopped.  Of course, you can\nobtain the same result by manually stopping the process with kill(1).\n.PP\nThe core image name was changed from \\fIcore.<pid>\\fP to \\fI<pid>.core\\fP\nto prevent matching names like \\fIcore.h\\fP and \\fIcore.c\\fP when using\nprograms such as \\fIfind(1)\\fP.\n.SH FILES\n<process-id>.core\tThe core image.\n.SH BUGS\nIf \\fBgcore\\fP encounters an error while creating the core image and\nthe \\fB-s\\fP option was used the process will remain stopped.\n.PP\nSwapped out processes and system processes (the swapper) may not be gcore'd.\n"
  },
  {
    "path": "share/man/man1/graph.1",
    "content": ".\\\"\t@(#)graph.1g\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH GRAPH 1G \"April 29, 1985\"\n.AT 3\n.SH NAME\ngraph \\- draw a graph\n.SH SYNOPSIS\n.B graph\n[ option ] ...\n.SH DESCRIPTION\n.I Graph\nwith no options takes pairs of numbers from the\nstandard input as abscissas and\nordinates of a graph.\nSuccessive points are connected by straight lines.\nThe graph is encoded on the standard output\nfor display by the\n.IR  plot (1G)\nfilters.\n.PP\nIf the coordinates of a point are followed by\na nonnumeric string, that string is printed as a\nlabel beginning on the point.\nLabels may be surrounded with quotes \"...\", in\nwhich case they may be empty or contain blanks\nand numbers;\nlabels never contain newlines.\n.PP\nThe following options are recognized,\neach as a separate argument.\n.TP\n.B  \\-a\nSupply abscissas automatically (they are missing from\nthe input); spacing is given by the next\nargument (default 1).\nA second optional argument is the starting point for\nautomatic abscissas (default 0 or lower limit given by\n.BR \\-x ).\n.TP\n.B  \\-b\nBreak (disconnect) the graph after each label in the input.\n.TP\n.B  \\-c\nCharacter string given by next argument\nis default label for each point.\n.TP\n.B  \\-g\nNext argument is grid style,\n0 no grid, 1 frame with ticks, 2 full grid (default).\n.TP\n.B  \\-l\nNext argument is label for graph.\n.TP\n.B  \\-m\nNext argument is mode (style)\nof connecting lines:\n0 disconnected, 1 connected (default).\nSome devices give distinguishable line styles\nfor other small integers.\n.TP\n.B  \\-s\nSave screen, don't erase before plotting.\n.TP\n\\fB\\-x\\fR [ \\fBl\\fR ]\nIf\n.B l\nis present, x axis is logarithmic.\nNext 1 (or 2) arguments are lower (and upper)\n.IR x \"\"\nlimits.\nThird argument, if present, is grid spacing on \n.I x\naxis.\nNormally these quantities are determined automatically.\n.TP\n\\fB\\-y\\fR [ \\fBl\\fR ]\nSimilarly for\n.IR y .\n.TP\n.B  \\-h\nNext argument is fraction of space for height.\n.TP\n.B  \\-w\nSimilarly for width.\n.TP\n.B  \\-r\nNext argument is fraction of space to move right before plotting.\n.TP\n.B  \\-u\nSimilarly to move up before plotting.\n.TP\n.B  \\-t\nTranspose horizontal and vertical axes.\n(Option\n.B \\-x\nnow applies to the vertical axis.)\n.PP\nA legend indicating grid range is produced\nwith a grid unless the\n.B \\-s\noption is present.\n.PP\nIf a specified lower limit exceeds the upper limit,\nthe axis\nis reversed.\n.SH \"SEE ALSO\"\nspline(1G), plot(1G)\n.SH BUGS\n.I Graph\nstores all points internally and drops those for which\nthere isn't room.\n.br\nSegments that run out of bounds are dropped, not windowed.\n.br\nLogarithmic axes may not be reversed.\n"
  },
  {
    "path": "share/man/man1/grep.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)grep.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH GREP 1 \"April 29, 1985\"\n.UC 4\n.SH NAME\ngrep, egrep, fgrep \\- search a file for a pattern\n.SH SYNOPSIS\n.B grep\n[ option ] ...\nexpression [ file ] ...\n.LP\n.B egrep \n[ option ] ...\n[ expression ]\n[ file ] ...\n.LP\n.B fgrep\n[ option ] ...\n[ strings ]\n[ file ]\n.SH DESCRIPTION\nCommands of the\n.I grep\nfamily search the input\n.I files\n(standard input default) for lines matching a pattern.\nNormally, each line found is copied to the standard output.\n.I Grep\npatterns are limited regular expressions in the style of\n.IR ex (1);\nit uses a compact nondeterministic algorithm.\n.I Egrep\npatterns are full regular expressions; it uses a fast deterministic\nalgorithm that sometimes needs exponential space.\n.I Fgrep\npatterns are fixed strings; it is fast and compact.\nThe following options are recognized.\n.TP\n.B \\-v\nAll lines but those matching are printed.\n.TP\n.B \\-x\n(Exact) only lines matched in their entirety are printed\n.RI ( fgrep\nonly).\n.TP\n.B \\-c\nOnly a count of matching lines is printed.\n.TP\n.B \\-l\nThe names of files with matching lines are listed (once) separated by newlines.\n.TP\n.B \\-n\nEach line is preceded by its relative line number in the file.\n.TP\n.B \\-b\nEach line is preceded by the block number on which it was found.\nThis is sometimes useful in locating disk block numbers by context.\n.TP\n.B \\-i\nThe case of letters is ignored in making comparisons \\(em that is, upper and\nlower case are considered identical.  This applies to \\fIgrep\\fR\\| and\n\\fIfgrep\\fR only.\n.TP\n.B \\-s\nSilent mode.  Nothing is printed (except error messages).\nThis is useful for checking the error status.\n.TP\n.B \\-w\nThe expression is searched for as a word\n(as if surrounded by `\\e<' and `\\e>', see\n.IR ex (1).)\n(\\fIgrep\\fR\\| only)\n.TP\n.BI \\-e \" expression\"\nSame as a simple\n.I expression \nargument, but useful when the\n.I expression\nbegins with a \\-.\n.TP\n.BI \\-f \" file\"\nThe regular expression\n.RI ( egrep )\nor string list\n.RI ( fgrep ) \nis taken from the\n.I file.\n.LP\nIn all cases the file name is shown if there is more than one input file.\nCare should be taken when using the characters $ * [ ^ | ( ) and \\\\ in the\n.I expression\nas they are also meaningful to the Shell.  It is safest to enclose the entire\n.I expression\nargument in single quotes \\' \\'.\n.LP\n.I Fgrep\nsearches for lines that contain one of the (newline-separated)\n.I strings.\n.LP\n.I Egrep\naccepts extended regular expressions.\nIn the following description `character' excludes newline:\n.IP\nA \\e followed by a single character other than newline matches that character.\n.IP\nThe character ^ matches the beginning of a line.\n.IP\nThe character $ matches the end of a line.\n.IP\nA \n.B .\n(period) matches any character.\n.IP\nA single character not otherwise endowed with special\nmeaning matches that character.\n.IP\nA string enclosed in brackets [\\|] matches any single character from the string.\nRanges of ASCII character codes may be abbreviated as in `a\\-z0\\-9'.\nA ]\nmay occur only as the first character of the string.\nA literal \\- must be placed where it can't be mistaken as a range indicator.\n.IP\nA regular expression followed by an * (asterisk) matches a sequence of 0\nor more matches of the regular expression.\nA regular expression followed by a + (plus) matches a sequence of 1 or more\nmatches of the regular expression.\nA regular expression followed by a ? (question mark) matches a sequence of\n0 or 1 matches of the regular expression.\n.IP\nTwo regular expressions concatenated match a match of the first followed\nby a match of the second.\n.IP\nTwo regular expressions separated by | or newline\nmatch either a match for the first or a match for the second.\n.IP\nA regular expression enclosed in parentheses\nmatches a match for the regular expression.\n.LP\nThe order of precedence of operators at the same parenthesis level\nis [\\|] then *+? then concatenation then | and newline.\n.LP\nIdeally there should be only one\n.I grep,\nbut we don't know a single algorithm that spans a wide enough\nrange of space-time tradeoffs.\n.SH \"SEE ALSO\"\nex(1),\nsed(1),\nsh(1)\n.SH DIAGNOSTICS\nExit status is 0 if any matches are found,\n1 if none, 2 for syntax errors or inaccessible files.\n.SH BUGS\nLines are limited to 256 characters; longer lines are truncated.\n"
  },
  {
    "path": "share/man/man1/head.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)head.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH HEAD 1 \"April 29, 1985\"\n.UC\n.SH NAME\nhead \\- give first few lines\n.SH SYNOPSIS\n.B head\n[\n.BR \\- count\n] [\nfile ...\n]\n.SH DESCRIPTION\nThis filter gives the first\n.I count\nlines of each of the specified files, or of the standard input.\nIf\n.I count\nis omitted it defaults to\n10.\n.SH SEE\\ ALSO\ntail(1)\n"
  },
  {
    "path": "share/man/man1/hostid.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)hostid.1\t6.2 (Berkeley) 5/5/86\n.\\\"\n.TH HOSTID 1 \"May 5, 1986\"\n.UC 5\n.SH NAME\nhostid \\- set or print identifier of current host system\n.SH SYNOPSIS\n.B hostid\n[ identifier ]\n.SH DESCRIPTION\nThe\n.I hostid\ncommand prints the identifier of the current host in hexadecimal.\nThis numeric value is expected to be unique across all hosts and\nis commonly set to the host's Internet address.\nThe super-user can set the hostid by giving a hexadecimal\nargument or the hostname;\nthis is usually done in the startup script /etc/rc.local.\n.SH SEE ALSO\ngethostid(2), sethostid(2)\n"
  },
  {
    "path": "share/man/man1/indent.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)indent.1\t6.4 (Berkeley) 9/10/85\n.\\\"\n.TH INDENT 1 \"September 10, 1985\"\n.UC 5\n.SH NAME\nindent \\- indent and format C program source\n.SH SYNOPSIS\n.in +\\w'\\fBindent \\fR'u\n.ti -\\w'\\fBindent \\fR'u\n\\fBindent \\fR [ \\fIinput-file\\fR [ \\fIoutput-file\\fR ] ]\n[\\ \\fB\\-bad\\fR\\ |\\ \\fB\\-nbad\\fR\\ ]\n[\\ \\fB\\-bap\\fR\\ |\\ \\fB\\-nbap\\fR\\ ]\n[\\ \\fB\\-bbb\\fR\\ |\\ \\fB\\-nbbb\\fR\\ ]\n[\\ \\fB\\-bc\\fR\\ |\\ \\fB\\-nbc\\fR\\ ]\n[\\ \\fB\\-bl\\fR\\ |\\ \\fB\\-br\\fR\\ ]\n[\\ \\fB\\-c\\fIn\\fR\\ ]\n[\\ \\fB\\-cd\\fIn\\fR\\ ]\n[\\ \\fB\\-cdb\\fR\\ |\\ \\fB\\-ncdb\\fR\\ ]\n[\\ \\fB\\-ce\\fR\\ |\\ \\fB\\-nce\\fR\\ ]\n[\\ \\fB\\-ci\\fIn\\fR\\ ]\n[\\ \\fB\\-cli\\fIn\\fR\\ ]\n[\\ \\fB\\-d\\fIn\\fR\\ ]\n[\\ \\fB\\-di\\fIn\\fR\\ ]\n[\\ \\fB\\-dj\\fR\\ |\\ \\fB\\-ndj\\fR\\ ]\n[\\ \\fB\\-ei\\fR\\ |\\ \\fB\\-nei\\fR\\ ]\n[\\ \\fB\\-fc1\\fR\\ |\\ \\fB\\-nfc1\\fR\\ ]\n[\\ \\fB\\-i\\fIn\\fR\\ ]\n[\\ \\fB\\-ip\\fR\\ |\\ \\fB\\-nip\\fR\\ ]\n[\\ \\fB\\-l\\fIn\\fR\\ ]\n[\\ \\fB\\-lc\\fIn\\fR\\ ]\n[\\ \\fB\\-lp\\fR\\ |\\ \\fB\\-nlp\\fR\\ ]\n[\\ \\fB\\-npro\\fR\\ ]\n[\\ \\fB\\-pcs\\fR\\ |\\ \\fB\\-npcs\\fR\\ ]\n[\\ \\fB\\-ps\\fR\\ |\\ \\fB\\-nps\\fR\\ ]\n[\\ \\fB\\-psl\\fR\\ |\\ \\fB\\-npsl\\fR\\ ]\n[\\ \\fB\\-sc\\fR\\ |\\ \\fB\\-nsc\\fR\\ ]\n[\\ \\fB\\-sob\\fR\\ |\\ \\fB\\-nsob\\fR\\ ]\n[\\ \\fB\\-st\\fR\\ ]\n[\\ \\fB\\-troff\\fR\\ ]\n[\\ \\fB\\-v\\fR\\ |\\ \\fB\\-nv\\fR\\ ]\n.SH DESCRIPTION\n.IX  indent  \"\"  \"\\fLindent\\fP \\(em format C source\"\n.IX  \"programming tools\"  \"indent\"  \"\"  \"\\fLindent\\fP \\(em format C source\"\n.IX  \"languages\"  \"indent\"  \"\"  \"\\fLindent\\fP \\(em format C source\"\n.IX  \"C programming language\"  \"indent\"  \"\"  \"\\fLindent\\fP \\(em format C source\"\n.IX  \"pretty printer\"  \"indent\"  \"\"  \"\\fLindent\\fP \\(em format C source\"\n.IX  \"format C programs\" \"\" \"format C programs \\(em \\fLindent\\fP\"\n.IX  \"code formatter\"  \"indent\"  \"\"  \"\\fLindent\\fP \\(em format C source\"\n.IX  \"cb\"  \"indent\"  \"\\fLcb\\fP\"  \"try \\fLindent\\fP \\(em format C source\"\n.I Indent\nis a \\fBC\\fR program formatter.  It reformats the \\fBC\\fR program in the\n\\fIinput-file\\fR according to the switches.  The switches which can be\nspecified are described below. They may appear before or after the file\nnames.\n.LP\n\\fBNOTE\\fP: If you only specify an \\fIinput-file\\fR, the formatting is\ndone `in-place', that is, the formatted file is written back into\n.I input-file\nand a backup copy of\n.I input-file\nis written in the current directory.  If\n.I input-file\nis named `/blah/blah/file', the backup file is named\n.RI file .BAK.\n.LP\nIf\n.I output-file\nis specified,\n.I indent\nchecks to make sure it is different from\n.IR input-file .\n.SH OPTIONS\n.LP\nThe options listed below control the formatting style imposed by\n.IR indent .\n.TP 15\n.BR \\-bad , \\-nbad\nIf\n.B \\-bad\nis specified, a blank line is forced after every block of\ndeclarations.  Default:  \n.BR \\-nbad .\n.TP 15\n.BR \\-bap , \\-nbap\nIf\n.B \\-bap\nis specified, a blank line is forced after every procedure body.  Default:\n.B \\-nbap.\n.TP 15\n.BR \\-bbb , \\-nbbb\nIf\n.B \\-bbb\nis specified, a blank line is forced before every block comment.  Default:\n.B \\-nbbb.\n.TP 15\n.BR \\-bc , \\-nbc\nIf\n.B \\-bc\nis specified, then a newline is forced after each comma in a declaration. \n.B \\-nbc\nturns off this option.  The default is\n.BR \\-nbc .\n.TP 15\n.BR \\-br , \\-bl\nSpecifying\n.B \\-bl\nlines up compound statements like this:\n.ne 4\n.nf\n.ft L\n    if (...)\n    {\n        code\n    }\n.ft R\n.fi\nSpecifying\n.B \\-br\n(the default) makes them look like this:\n.ne 3\n.nf\n.ft L\n    if (...) {\n        code\n    }\n.ft R\n.fi\n.LP\n.TP 15\n.BI \\-c n\nThe column in which comments on code start.  The default is 33.  \n.TP 15\n.BI \\-cd n\nThe column in which comments on declarations start.  The default\nis for these comments to start in the same column as those on code.\n.TP 15\n.BI \\-cdb , \\-ncdb\nEnables (disables) the placement of comment delimiters on blank lines.  With\nthis option enabled, comments look like this:\n.nf\n.ft L\n.ne 3\n\t/*\n\t * this is a comment\n\t */\n.ft R\n.fi\nRather than like this:\n.nf\n.ft L\n\t/* this is a comment */\n.ft R\n.fi\nThis only affects block comments, not comments to the right of\ncode. The default is\n.BR \\-cdb .\n.TP 15\n.BI \\-ce , \\-nce\nEnables (disables) forcing `else's to cuddle up to the immediately preceding\n`}'.  The default is\n.BR \\-ce .\n.TP 15\n.BI \\-ci n\nSets the continuation indent to be \\fIn\\fR.  Continuation\nlines will be indented that far from the beginning of the first line of the\nstatement.  Parenthesized expressions have extra indentation added to\nindicate the nesting, unless \\fB\\-lp\\fR is in effect.\n\\fB\\-ci\\fR defaults to the same value as \\fB\\-i\\fR.\n.TP 15\n.BI \\-cli n\nCauses case labels to be indented\n.I n\ntab stops to the right of the containing \\fBswitch\\fR statement.\n\\fB\\-cli0.5\\fR causes case labels to be indented half a tab stop.  The\ndefault is\n.BR \\-cli0 .\n(This is the only option that takes a fractional argument.)\n.TP 15\n.BI \\-d n\nControls the placement of comments which are not to the\nright of code.  Specifying\n.B \\-d1\nmeans that such comments are placed one indentation level to the\nleft of code.  The default\n.B \\-d0\nlines up these comments with the code.  See the section on comment\nindentation below.\n.TP 15\n.BI \\-di n\nSpecifies the indentation, in character positions, from a declaration keyword\nto the following identifier.  The default is\n.BR \\-di16 .\n.TP 15\n.BR \\-dj , \\-ndj\n.B \\-dj\nleft justifies declarations.\n.B \\-ndj\nindents declarations the same as code.  The default is\n.BR \\-ndj .\n.TP 15\n.BI \\-ei , \\-nei\nEnables (disables) special\n.B else-if\nprocessing.  If enabled,\n.BR if \"s\"\nfollowing\n.BR else \"s\"\nwill have the same indentation as the preceding\n.B if\nstatement.  The default is\n.BR \\-ei .\n.TP 15\n.BI \\-fc1 , \\-nfc1\nEnables (disables) the formatting of comments that start in column 1.\nOften, comments whose leading `/' is in column 1 have been carefully\nhand formatted by the programmer.  In such cases, \\fB\\-nfc1\\fR should be\nused.  The default is \\fB\\-fc1\\fR.\n.TP 15\n.BI \\-i n\nThe number of spaces for one indentation level.  The default is 8.\n.TP 15\n.BI \\-ip , \\-nip\nEnables (disables) the indentation of parameter declarations from the left\nmargin.  The default is\n.BR \\-ip .\n.TP 15\n.BI \\-l n\nMaximum length of an output line.  The default is 78.\n.TP 15\n.BI \\-lp , \\-nlp\nLines up code surrounded by parenthesis in continuation lines.  If a line\nhas a left paren which is not closed on that line, then continuation lines\nwill be lined up to start at the character position just after the left\nparen.  For example, here is how a piece of continued code looks with\n\\fB\\-nlp\\fR in effect:\n.ne 2\n.nf\n.ft L\n    p1 = first_procedure(second_procedure(p2, p3),\n        third_procedure(p4, p5));\n.ft R\n.fi\n.ne 5\nWith \\fB\\-lp\\fR in effect (the default) the code looks somewhat clearer:\n.nf\n.ft L\n.ta \\w'    p1 = first_procedure('u\n    p1 = first_procedure(second_procedure(p2, p3),\n\tthird_procedure(p4, p5));\n.ft R\n.fi\n.ne 5\nInserting two more newlines we get:\n.nf\n.ft L\n.ta \\w'    p1 = first_procedure('u +\\w'second_procedure('u\n    p1 = first_procedure(second_procedure(p2,\n\t\tp3),\n.ta \\w'    p1 = first_procedure('u +\\w'third_procedure('u\n\tthird_procedure(p4,\n\t\tp5));\n.ft R\n.fi\n.TP 15\n.B \\-npro\nCauses the profile files, `./.indent.pro' and `~/.indent.pro', to be ignored.\n.TP 15\n.BR \\-pcs , \\-npcs\nIf true (\\fB\\-pcs\\fR) all procedure calls will have a space inserted between\nthe name and the `('.  The default is \n.BR \\-npcs .\n.TP 15\n.BR \\-ps , \\-nps\nIf true (\\fB\\-ps\\fR) the pointer following operator `\\->' will be\nsurrounded by spaces on either side.  The default is\n.BR \\-nps .\n.TP 15\n.BR \\-psl , \\-npsl\nIf true (\\fB\\-psl\\fR) the names of procedures being defined are placed in\ncolumn 1 \\- their types, if any, will be left on the previous lines.  The\ndefault is \n.BR \\-psl .\n.TP 15\n.BR \\-sc , \\-nsc\nEnables (disables) the placement of asterisks (`*'s) at the left edge of all\ncomments.  The default is\n.BR \\-sc .\n.TP 15\n.BR \\-sob , \\-nsob\nIf\n.B \\-sob\nis specified, indent will swallow optional blank lines.  You can use this to\nget rid of blank lines after declarations.  Default:\n.BR \\-nsob .\n.TP 15\n.B \\-st\nCauses\n.B indent\nto take its input from stdin, and put its output to stdout.\n.TP 15\n.BI \\-T typename\nAdds\n.I typename\nto the list of type keywords.  Names accumulate:\n.B \\-T\ncan be specified more than once.  You need to specify all the typenames that\nappear in your program that are defined by \\fBtypedef\\fRs \\- nothing will be\nharmed if you miss a few, but the program won't be formatted as nicely as\nit should.  This sounds like a painful thing to have to do, but it's really\na symptom of a problem in C: \\fBtypedef\\fR causes a syntactic change in the\nlanguage and \\fIindent\\fR can't find all \\fBtypedef\\fRs.\n.TP 15\n.B \\-troff\nCauses\n.B indent\nto format the program for processing by troff.  It will produce a fancy\nlisting in much the same spirit as\n.BR vgrind .\nIf the output file is not specified, the default is standard output,\nrather than formatting in place.\n.TP 15\n.BR \\-v , \\-nv\n.B \\-v\nturns on `verbose' mode;\n.B \\-nv\nturns it off.  When in verbose mode,\n.I indent\nreports when it splits one line of input into two or more lines of output,\nand gives some size statistics at completion. The default is\n.BR \\-nv .\n.SH \"FURTHER DESCRIPTION\"\n.LP\nYou may set up your own `profile' of defaults to\n.I indent\nby creating a file called\n.BI . indent . pro\nin either your login directory and/or the current directory and including\nwhatever switches you like.  Switches in `.indent.pro' in the current\ndirectory override those in your login directory (with the exception of\n.B -T\ntype definitions, which just accumulate).  If\n.I indent\nis run and a profile file exists, then it is read to set up the program's\ndefaults.  The switches should be separated by spaces, tabs or newlines.\nSwitches on the command line, however, override profile switches.\n.LP\n.B Comments\n.LP\n.IR \"`Box' comments\" .\n.I Indent\nassumes that any comment with a dash or star immediately after the start of\ncomment (that is, `/*\\-' or `/**') is a comment surrounded by a box of stars.\nEach line of such a comment is left unchanged, except that its indentation\nmay be adjusted to account for the change in indentation of the first line\nof the comment.\n.LP\n.IR \"Straight text\" .\nAll other comments are treated as straight text.\n.I Indent\nfits as many words (separated by blanks, tabs, or newlines) on a\nline as possible.  Blank lines break paragraphs.\n.LP\n.B Comment indentation\n.LP\nIf a comment is on a line with code it is started in the `comment column',\nwhich is set by the\n.BI \\-c n\ncommand line parameter.  Otherwise, the comment is started at\n.I n\nindentation levels less than where code is currently being placed, where\n.I n\nis specified by the\n.BI \\-d n\ncommand line parameter.  If the code on a line extends past the comment\ncolumn, the comment starts further to the right, and the right margin may be\nautomatically extended in extreme cases.\n.LP\n.B Preprocessor lines\n.LP\nIn general, \\fIindent\\fR leaves preprocessor lines alone.  The only\nreformatting that it will do is to straighten up trailing comments.  It\nleaves embedded comments alone.  Conditional compilation\n(\\fB#ifdef...#endif\\fR) is recognized and \\fIindent\\fR attempts to correctly\ncompensate for the syntactic peculiarities introduced.\n.LP\n.B C syntax\n.LP\n\\fIIndent\\fR understands a substantial amount about the syntax of C, but it\nhas a `forgiving' parser.  It attempts to cope with the usual sorts of\nincomplete and misformed syntax.  In particular, the use of macros like:\n.nf\n.ft L\n        #define forever for(;;)\n.ft R\n.fi\nis handled properly.\n.SH FILES\n.DT\n.br\n\\&./.indent.pro\tprofile file\n.br\n~/.indent.pro\tprofile file\n.SH BUGS\n.I Indent\nhas even more switches than \\fIls\\fR.\n.sp\n.ne 5\nA common mistake that often causes grief is typing:\n.nf\n.ft L\n    indent *.c\n.ft R\n.fi\nto the shell in an attempt to indent all the \\fBC\\fR programs in a directory.\nThis is probably a bug, not a feature.\n"
  },
  {
    "path": "share/man/man1/intro.1",
    "content": ".\\\"\t@(#)intro.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH INTRO 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nintro \\- introduction to commands\n.SH DESCRIPTION\nThis section describes publicly accessible commands in alphabetic order.\nCertain distinctions of purpose are made in the headings:\n.TP\n(1)\nCommands of general utility.\n.TP\n(1C)\nCommands for communication with other systems.\n.TP\n(1G)\nCommands used primarily for graphics and computer-aided design.\n.PP\nN.B.: Commands related to system maintenance used to appear in\nsection 1 manual pages and were distinguished by (1M) at the top of the\npage.  These manual pages now appear in section 8.\n.SH SEE ALSO\nSection (6) for computer games.\n.PP\n.I How to get started,\nin the Introduction.\n.SH DIAGNOSTICS\nUpon termination each command returns two bytes of status,\none supplied by the system giving the cause for\ntermination, and (in the case of `normal' termination)\none supplied by the program, see\n.I wait\nand\n.IR exit (2).\nThe former byte is 0 for normal termination, the latter\nis customarily 0 for successful execution, nonzero\nto indicate troubles such as erroneous parameters, bad or inaccessible data,\nor other inability to cope with the task at hand.\nIt is called variously `exit code', `exit status' or\n`return code', and is described only where special conventions are involved.\n"
  },
  {
    "path": "share/man/man1/join.1",
    "content": ".\\\"\t@(#)join.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH JOIN 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\njoin \\- relational database operator\n.SH SYNOPSIS\n.B join\n[\noptions\n]\nfile1 file2\n.SH DESCRIPTION\n.I Join\nforms, on the standard output,\na join\nof the two relations specified by the lines of\n.I file1\nand\n.IR file2 .\nIf\n.I file1\nis `\\-', the standard input is used.\n.PP\n.I File1\nand \n.I file2\nmust be sorted in increasing ASCII collating\nsequence on the fields\non which they are to be joined,\nnormally the first in each line.\n.PP\nThere is one line in the output \nfor each pair of lines in \n.I file1 \nand \n.I file2\nthat have identical join fields.\nThe output line normally consists of the common field,\nthen the rest of the line from \n.IR file1 ,\nthen the rest of the line from\n.IR file2 .\n.PP\nFields are normally separated by blank, tab or newline.\nIn this case, multiple separators count as one, and\nleading separators are discarded.\n.PP\nThese options are recognized:\n.TP\n.BI \\-a n\nIn addition to the normal output,\nproduce a line for each unpairable line in file\n.IR n ,\nwhere\n.I n\nis 1 or 2.\n.TP\n.BI \\-e \\ s\nReplace empty output fields by string\n.IR s .\n.TP\n.BI \\-j n\\ m\nJoin on the\n.IR m th\nfield of file\n.IR n .\nIf\n.I n\nis missing, use the\n.IR m th\nfield in each file.\n.TP\n.BI \\-o \\ list\nEach output line comprises the fields specified in\n.IR list ,\neach element of which has the form\n.IR n . m ,\nwhere\n.I n\nis a file number and\n.I m\nis a field number.\n.PP\n.TP\n.BI \\-t c\nUse character\n.I c\nas a separator (tab character).\nEvery appearance of\n.I c\nin a line is significant.\n.SH \"SEE ALSO\"\nsort(1), comm(1), awk(1)\n.SH BUGS\nWith default field separation,\nthe collating sequence is that of\n.IR sort\\ \\-b ;\nwith\n.BR \\-t ,\nthe sequence is that of a plain sort.\n.PP\nThe conventions of\n.I join, sort, comm, uniq, look\nand\n.IR awk (1)\nare wildly incongruous.\n"
  },
  {
    "path": "share/man/man1/kill.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)kill.1\t6.2 (Berkeley) 4/20/86\n.\\\"\n.TH KILL 1 \"April 20, 1986\"\n.UC 4\n.SH NAME\nkill \\- terminate a process with extreme prejudice\n.SH SYNOPSIS\n.B kill\n[\n.BR \\- sig\n]\nprocessid ...\n.br\n.B kill\n.B \\-l\n.SH DESCRIPTION\n.I Kill\nsends the TERM (terminate, 15) signal to the specified processes.\nIf a signal name or number preceded by `\\-' is given\nas first argument, that signal is sent instead of\nterminate\n(see\n.IR  sigvec (2)).\nThe signal names are listed by\n`kill \\-l', and are as given in\n.I /usr/include/signal.h,\nstripped of the common SIG prefix.\n.PP\nThe terminate signal will kill processes that do not catch the signal;\n`kill \\-9 ...' is a sure kill, as the KILL (9) signal cannot be caught.\nBy convention, if process number 0 is specified, all members\nin the process group (i.e. processes resulting from \nthe current login) are signaled (but beware: this works only\nif you use\n.IR sh (1);\nnot if you use\n.IR csh (1).)\nNegative process numbers also have special meanings; see\n.IR kill (2)\nfor details.\n.PP\nThe killed processes must belong\nto the current user unless\nhe is the super-user.\n.PP\nThe process number of an asynchronous process\nstarted with `&' is reported by the shell.\nProcess numbers can also be found by using\n.IR ps (1).\n.I Kill\nis a built-in to\n.IR csh (1);\nit allows job specifiers of the form ``%...'' as arguments\nso process id's are not as often used as\n.I kill\narguments.\nSee\n.IR csh (1)\nfor details.\n.SH \"SEE ALSO\"\ncsh(1), ps(1), kill(2), sigvec(2)\n.SH BUGS\nA replacement for ``kill 0''\nfor\n.IR csh (1)\nusers should be provided.\n"
  },
  {
    "path": "share/man/man1/last.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)last.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH LAST 1 \"April 29, 1985\"\n.UC 4\n.SH NAME\nlast \\- indicate last logins of users and teletypes\n.SH SYNOPSIS\n.B last\n[\n\\-f filename\n]\n[\n\\-N\n]\n[\nname ...\n] [\ntty ...\n]\n.SH DESCRIPTION\n.I Last\nwill look back in the\n.I wtmp\nfile which records all logins and logouts for information about\na user, a teletype or any group of users and teletypes.\nArguments specify names of users or teletypes of interest.\nNames of teletypes may be given fully or abbreviated.\nFor example `last 0' is the same as `last tty0'.\nIf multiple arguments are given, the information which applies\nto any of the arguments is printed.  For example `last root console'\nwould list all of \"root's\" sessions as well as all sessions\non the console terminal.\n.I Last\nwill print the sessions of the specified users and teletypes,\nmost recent first, indicating the times at which the session\nbegan, the duration of the session, and the teletype which the\nsession took place on.\nIf the session is still continuing or was cut short by a reboot,\n.I last\nso indicates.\n.PP\nThe pseudo-user\n.B reboot\nlogs in at reboots of the system, thus\n.DT\n.PP\n\tlast reboot\n.PP\nwill give an indication of mean time between reboot.\n.PP\n.I Last\nwith no arguments prints a record of all logins and logouts, in\nreverse order.\nThe \n.B \\-f filename\noption allows the user to examine an alternate\n.I wtmp\nfile.\nThe\n.B \\-N\noption limits the report to N lines.\n.PP\nIf\n.I last\nis interrupted, it indicates how far the search has progressed\nin\n.I wtmp.\nIf interrupted with a quit signal\n(generated by a control-\\e)\n.I last\nindicates how far the search has progressed so far, and the\nsearch continues.\n.SH FILES\n/usr/adm/wtmp\t\tlogin data base\n.br\n/usr/adm/shutdownlog\twhich records shutdowns and reasons for same\n.SH SEE\\ ALSO\nwtmp(5), ac(8), lastcomm(1)\n.SH AUTHOR\nHoward Katseff\n"
  },
  {
    "path": "share/man/man1/lastcomm.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)lastcomm.1\t6.2.1 (2.11BSD) 2/3/05\n.\\\"\n.TH LASTCOMM 1 \"February 3, 1995\"\n.UC 4\n.SH NAME\nlastcomm \\- show last commands executed in reverse order\n.SH SYNOPSIS\n.B lastcomm\n[ -f file ] [ command name ] ... [user name] ... [terminal name] ...\n.SH DESCRIPTION\n.I Lastcomm\ngives information on previously executed commands.\n.sp\nOption:\n.sp\n.TP 10\n\\-f \\fIfile\\fP\nRead from \\fIfile\\fP rather than the default accounting file.\n.PP\nWith no arguments,\n.I lastcomm\nprints information about all the commands recorded\nduring the current accounting file's lifetime.\nIf called with arguments, only accounting entries with a\nmatching command\nname, user name, or terminal name are printed.\nSo, for example,\n.sp\n.ti +0.5i\nlastcomm a.out root ttyd0\n.sp\nwould produce a listing of all the\nexecutions of commands named\n.I a.out\nby user\n.I root\non the terminal\n.IR ttyd0 .\n.PP\nFor each process entry, the following are printed.\n.sp\n.in +0.5i\nThe name of the user who ran the process.\n.br\nFlags, as accumulated by the accounting facilities in the system.\n.br\nThe command name under which the process was called.\n.br\nThe amount of cpu time used by the process (in seconds).\n.br\nThe time the process exited.\n.in -0.5i\n.PP\nThe flags are encoded as follows: ``S'' indicates the command was\nexecuted by the super-user, ``F'' indicates the command ran after\na fork, but without a following \n.IR exec ,\n``C'' indicates the command was run in PDP-11 compatibility mode\n(VAX only),\n``D'' indicates the command terminated with the generation of a\n.I core\nfile, and ``X'' indicates the command was terminated with a signal.\n.SH FILES\n.TP 20\n/usr/adm/acct\nDefault accounting file.\n.SH \"SEE ALSO\"\nlast(1),\nsigvec(2),\nacct(8),\ncore(5)\n"
  },
  {
    "path": "share/man/man1/learn.1",
    "content": ".\\\"\t@(#)learn.1\t6.2.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH LEARN 1 \"October 22, 1996\"\n.AT 3\n.SH NAME\nlearn \\- computer aided instruction about UNIX\n.SH SYNOPSIS\n.B learn\n[\n.BR \\- directory\n]\n[ subject [ lesson ] ]\n.SH DESCRIPTION\n.I Learn\ngives Computer Aided Instruction courses and\npractice in the use of UNIX, the C Shell,\nand the Berkeley text editors.\nTo get started simply type\n.BR learn .\nIf you had used\n.I learn\nbefore and left your last session without completing a subject,\nthe program will use information in $HOME/.learnrc to start you up\nin the same place you left off.\nYour first time through,\n.I learn\nwill ask questions to find out what you want to do.\nSome questions may be bypassed by naming a\n.IR subject ,\nand more yet by naming a\n.IR lesson .\nYou may enter the\n.I lesson\nas a number that\n.I learn\ngave you in a previous session.\nIf you do not know the lesson number,\nyou may enter the\n.I lesson\nas a word, and\n.I learn\nwill look for the first lesson containing it.\nIf the\n.I lesson\nis `\\fB\\-\\fP',\n.I learn\nprompts for each lesson;\nthis is useful for debugging.\n.PP\nThe\n.IR subject \\|'s\npresently handled are\n.if n .sp 1v\n.if t .sp .5v\n.nf\n.in +0.5i\nfiles\neditor\nvi\nmorefiles\nmacros\neqn\nC\n.in -0.5i\n.fi\n.PP\nThere are a few special commands.\nThe command `bye' terminates a \n.I learn\nsession and `where' tells you of your progress,\nwith `where\\0m' telling you more.\nThe command `again' re-displays the text of the lesson\nand `again\\0\\fIlesson\\fP' lets you review\n.IR lesson .\nThere is no way for\n.I learn\nto tell you the answers it expects in English, however,\nthe command `hint' prints the last part of the lesson script\nused to evaluate a response, while `hint m' prints the\nwhole lesson script.\nThis is useful for debugging\nlessons and might possibly give you an idea about what it expects.\n.PP\nThe\n.BI \\- directory\noption allows one to exercise a script in\na nonstandard place.\n.SH FILES\n/usr/share/learn\tsubtree for all dependent directories and files\n.br\n/usr/tmp/pl\\(**\tplaypen directories\n.br\n$HOME/.learnrc\tstartup information\n.SH SEE ALSO\ncsh(1), ex(1)\n.br\nB. W. Kernighan and M. E. Lesk, \\fILEARN \\- Computer-Aided Instruction on UNIX\\fR\n.SH BUGS\nThe main strength of\n.I learn,\nthat it asks the student to use the real UNIX,\nalso makes possible baffling mistakes.\nIt is helpful, especially for nonprogrammers,\nto have a UNIX initiate near at hand during the first\nsessions.\n.PP\nOccasionally lessons are incorrect, sometimes because the local version\nof a command operates in a non-standard way.\nOccasionally a lesson script does not recognize all the different\ncorrect responses, in which case the `hint' command may be useful.\nSuch lessons may be skipped with the `skip' command,\nbut it takes some sophistication to recognize the situation.\n.PP\nTo find a\n.I lesson\ngiven as a word,\n.I learn\ndoes a simple\n.IR fgrep (1)\nthrough the lessons.\nIt is unclear whether this sort\nof subject indexing is better than none.\n.PP\nSpawning a new shell is required for each of many\nuser and internal functions.\n.PP\nThe `vi' lessons are provided separately from the others.\nTo use them see your system administrator.\n"
  },
  {
    "path": "share/man/man1/leave.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)leave.1\t6.2 (Berkeley) 5/7/86\n.\\\"\n.TH LEAVE 1 \"May 7, 1986\"\n.UC\n.SH NAME\nleave \\- remind you when you have to leave\n.SH SYNOPSIS\n.B leave\n[ [+]hhmm ]\n.SH DESCRIPTION\n.I Leave\nwaits until the specified time, then reminds you that you\nhave to leave.\nYou are reminded 5 minutes and 1 minute before the actual\ntime, at the time, and every minute thereafter.\nWhen you log off,\n.I leave\nexits just before it would have\nprinted the next message.\n.PP\nThe time of day is in the form hhmm where hh is a time in\nhours (on a 12 or 24 hour clock).\nAll times are converted to a 12 hour clock, and assumed to\nbe in the next 12 hours.\n.PP\nIf the time is preceeded by `+', the alarm will go off in hours and minutes\nfrom the current time.\n.PP\nIf no argument is given,\n.I leave\nprompts with \"When do you\nhave to leave?\". A reply of newline causes\n.I leave\nto exit,\notherwise the reply is assumed to be a time.\nThis form is suitable for inclusion in a\n.I .login\nor\n.I .profile.\n.PP\nLeave ignores interrupts, quits, and terminates.\nTo get rid of it you should either log off or use ``kill \\-9''\ngiving its process id.\n.SH SEE ALSO\ncalendar(1)\n"
  },
  {
    "path": "share/man/man1/lex.1",
    "content": ".\\\"\t@(#)lex.1\t6.2 (Berkeley) 4/14/86\n.\\\"\n.TH LEX 1 \"April 14, 1986\"\n.AT 3\n.SH NAME\nlex \\- generator of lexical analysis programs\n.SH SYNOPSIS\n.B lex\n[\n.B \\-tvfn\n] [ file ] ...\n.SH DESCRIPTION\n.I Lex\ngenerates programs to be used in simple lexical analyis of text.\nThe input\n.I files\n(standard input default) contain regular expressions\nto be searched for, and actions written in C to be executed when\nexpressions are found.\n.PP\nA C source program, 'lex.yy.c' is generated, to be compiled thus:\n.IP\ncc lex.yy.c \\-ll\n.LP\nThis program, when run, copies unrecognized portions of\nthe input to the output, and executes the associated\nC action for each regular expression that is recognized.\n.PP\nThe options have the following meanings.\n.TP\n.B \\-t\nPlace the result on the standard output instead of in file \"lex.yy.c\".\n.TP\n.B \\-v\nPrint a one-line summary of statistics of the generated analyzer.\n.TP\n.B \\-n\nOpposite of\n.BR \\-v ;\n.B \\-n\nis default.\n.TP\n.B \\-f\n\"Faster\" compilation: don't bother to pack\nthe resulting tables; limited to small programs.\n.SH EXAMPLE\n.IP\nlex lexcommands\n.PP\nwould draw\n.I lex\ninstructions from the file\n.I lexcommands,\nand place the output in\n.I lex.yy.c\n.IP \"\"\n.nf\n.ta \\w'[A\\-Z] 'u\n%%\n[A\\-Z]\tputchar(yytext[0]+\\'a\\'\\-\\'A\\');\n[ ]+$\t;\n[ ]+\tputchar(\\' \\');\n.fi\n.PP\nis an example of a\n.I lex\nprogram that would be put into a\n.I lex\ncommand file.  This program converts upper case to lower,\nremoves blanks at the end of lines,\nand replaces multiple blanks by single blanks.\n.SH \"SEE ALSO\"\nyacc(1), sed(1)\n.br\nM. E. Lesk and E. Schmidt,\n.I LEX \\- Lexical Analyzer Generator\n"
  },
  {
    "path": "share/man/man1/lint.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)lint.1\t6.2.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH LINT 1 \"October 22, 1996\"\n.UC 4\n.SH NAME\nlint \\- a C program verifier\n.SH SYNOPSIS\n.B lint\n[\n.B \\-abchnpuvx\n]\nfile ...\n.SH DESCRIPTION\n.I Lint\nattempts to detect features of the C program\n.I files\nwhich are\nlikely to be bugs, or non-portable, or wasteful.\nIt also checks the type usage of the program more strictly\nthan the compilers.\nAmong the things which are currently found are\nunreachable statements,\nloops not entered at the top,\nautomatic variables declared and not used,\nand logical expressions whose value is constant.\nMoreover, the usage of functions is checked to find\nfunctions which return values in some places and not in others,\nfunctions called with varying numbers of arguments,\nand functions whose values are not used.\n.PP\nBy default, it is assumed that all the\n.I files\nare to be loaded together; they are checked for\nmutual compatibility.\nFunction definitions for certain libraries are available to\n.IR lint ;\nthese libraries are referred to by a\nconventional name,\nsuch as `\\-lm', in the style of\n.IR ld (1).\nArguments ending in\n.I .ln\nare also treated as library files.  To create lint libraries,\nuse the\n.B \\-C\noption:\n.IP\nlint \\-Cfoo files . . .\n.PP\nwhere\n.I files\nare the C sources of library\n.I foo.\nThe result is a file\n.I llib-lfoo.ln\nin the correct library format suitable for linting programs\nusing\n.I foo.\n.PP\nAny number of the options in the following list\nmay be used.\nThe\n.SM\n.BR \\-D \"\\*S,\"\n.SM\n.BR \\-U \"\\*S,\"\nand\n.SM\n.B \\-I\noptions of\n.IR cc (1)\nare also recognized as separate arguments.\n.TP\n.B p\nAttempt to check portability to the\n.I IBM\nand\n.I GCOS\ndialects of C.\n.TP\n.B h\nApply a number of heuristic tests to attempt to\nintuit bugs, improve style, and reduce waste.\n.TP\n.B b\nReport\n.I break\nstatements that cannot be reached.\n(This is not the default because, unfortunately,\nmost\n.I lex\nand many\n.I yacc\noutputs produce dozens of such comments.)\n.TP\n.B v\nSuppress complaints about unused arguments in functions.\n.TP\n.B x\nReport variables referred to by extern declarations,\nbut never used.\n.TP\n.B a\nReport assignments of long values to int variables.\n.TP\n.B c\nComplain about casts which have questionable portability.\n.TP\n.B u\nDo not complain about functions and variables used and not\ndefined, or defined and not used (this is suitable for running\n.I lint\non a subset of files out of a larger program).\n.TP\n.B n\nDo not check compatibility against the standard library.\n.TP\n.B z\nDo not complain about structures that are never defined (e.g.\nusing a structure pointer without knowing its contents.).\n.PP\n.IR Exit (2)\nand other functions which do not return\nare not understood; this causes various lies.\n.PP\nCertain conventional comments in the C source\nwill change the behavior of\n.IR lint :\n.TP\n/*NOTREACHED*/\nat appropriate points\nstops comments about unreachable code.\n.TP\n.RI /*VARARGS n */\nsuppresses\nthe usual checking for variable numbers of arguments\nin the following function declaration.\nThe data types of the first\n.I n\narguments are checked;\na missing\n.I n\nis taken to be 0.\n.TP\n/*NOSTRICT*/\nshuts off strict type checking in the next expression.\n.TP\n/*ARGSUSED*/\nturns on the\n.B \\-v\noption for the next function.\n.TP\n/*LINTLIBRARY*/\nat the beginning of a file shuts off complaints about\nunused functions in this file.\n.SH AUTHOR\nS.C. Johnson.  Lint library construction implemented by Edward Wang.\n.SH FILES\n.ta \\w'/usr/share/lint/llib-port.ln  'u\n/usr/libexec/lint/lint[12]\tprograms\n.br\n/usr/share/lint/llib-lc.ln\tdeclarations for standard functions\n.br\n/usr/share/lint/llib-lc\thuman readable version of above\n.br\n/usr/share/lint/llib-port.ln\tdeclarations for portable functions\n.br\n/usr/share/lint/llib-port\thuman readable . . .\n.br\nllib-l*.ln\tlibrary created with\n.B \\-C\n.SH SEE ALSO\ncc(1)\n.br\nS. C. Johnson,\n.I Lint, a C Program Checker\n.SH BUGS\nThere are some things you just\n.B can't\nget lint to shut up about.\n.PP\n/*NOSTRICT*/\nis not implemented in the current version (alas).\n"
  },
  {
    "path": "share/man/man1/lisp.1",
    "content": ".de lt\n.ta 1.2i 2.4i 3.6i 4.8i 6.0i\n..\n.TH LISP 1 \"February 19, 1987\"\n.UC\n.SH  NAME\nlisp \\- lisp interpreter\n.SH SYNOPSIS\n.B lisp\n.SH DESCRIPTION\n.PP\n.I Lisp\nis a provisional lisp interpreter.\nIt only runs in eval mode. Built in functions are named\nin lower case, and case is distinguished.\nIt is being transmuted from a subset of lisp\nas provided by the Harvard \\s-2UNIX\\s0 lisp in\nuse at \\s-2UCB\\s0, to a subset of \\s-2MIT\\s0's \\s-2MACLISP\\s0.\n.PP\nThe following functions are provided as machine code:\n.LP\nLambda functions:\n.if n .ta 13n 26n 39n 52n 65n\n.if t .lt\n.sp\n.nf\natom\tdptr\tload\tputd\trplacd\nbcdp\tdrain\tnull\tputprop\tset\ncar\teq\tnumberp\tratom\tterpr\ncdr\tequal\toutfile\tread\nclose\teval\tpatom\treadc\nconcat\tget\tpntlen\tretbrk\ncons\tgetd\tportp\treturn\ncont\tinfile\tprint\trplaca\n.fi\n.LP\nNlambda functions (possibly simulating ones which are normally lambdas):\n.if n .ta 13n 26n 39n 52n 65n\n.if t .lt\n.sp\n.nf\nadd1\tdifference\tonep\tquotient\tzerop\nand\texit\tor\treset\nbreak\tgo\tplus\tsetq\ncond\tminus\tproduct\tsub1\ncond\tmod\tprog\tsum\ndef\tnot\tquote\ttimes\n.fi\n.PP\nThe following functions are provided as lisp code (and at the moment\nmust be read in by saying (load 'auxfns):\n.if n .ta 13n 26n 39n 52n 65n\n.if t .lt\n.sp\n.nf\nadd\tcopy\tlength\tnumbp\nappend\tdefevq\tlinelength\tpp_etc\napply*\tdefprop\tmember\treverse\ncharcnt\tdefprop\tmemcar\tterpri\nchrct\tdiff\tmemcdr\nconc\tlast\tnconc\n.fi\n.PP\nAll of the above functions are documented in the ``Harvard Lisp Manual.''\n.PP\nThe following functions are provided as in \\s-2MIT\\s0's \\s-2MACLISP\\s0.\n.if n .ta 13n 26n 39n 52n 65n\n.if t .lt\n.sp\n.nf\nalphalessp\tdo\tmapc\tsetsyntax\napply\texplodec\tmapcar\tthrow\nascii\texploden\tprog2\ttyi\ncatch\tfuncall\tprogn\ttyipeek\ndefun\timplode\tprogv\ttyo\n.fi\n.PP\n``Hairy control structure'' is provided by the Nlambda\n(process\\ \\fIcommand\\ inport\\ outport\\fP)\nwhere \n.I command\nis an atom whose print name is some command that you would wish typed\nat the terminal, e.g. ``neqn\\ |\\ nroff\\ \\-ms'';\nwhere\n.I inport\nand \n.I outport\nare atoms which will be bound to port descriptors for use in\ncommunication with the subprocess.\n.I Inport\nis a port to a pipe which will be read by the subprocess as\nits standard input. If \n.I Inport\nis \\fInil\\fP (or not present), the subprocess inherits the standard\ninput, and lisp waits for the subprocess to die.\nIf\n.I Inport\nis the atom \n.I t\nlisp continues without waiting.\n.SH AUTHORS\nOriginally written by Jeff Levinsky, Mike Curry, and John Breedlove.\nKeith Sklower made it work and is maintaining the current version.\nThe garbage collector was implemented by Bill Rowan.\n.SH SEE ALSO\nHarvard \\s-2UNIX\\s0 Lisp Manual\n.br\nMACLISP Manual\n.br\nUCB Franz Lisp Manual\n.SH \"BUGS\"\nThe status bits for\n.I setsyntax\nare not the same as for \\s-2MACLISP\\s0.\n.PP\nClosing\ndown a pipe doesn't always seem to work correctly.\n.PP\nArrays are not implemented in version 1.\n"
  },
  {
    "path": "share/man/man1/ln.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ln.1\t6.2 (Berkeley) 4/10/86\n.\\\"\n.TH LN 1 \"April 10, 1986\"\n.UC 4\n.SH NAME\nln \\- make links\n.SH SYNOPSIS\n.B ln\n[\n.B \\-s\n]\nsourcename [ targetname ]\n.br\n.B ln\n[\n.B \\-s\n]\nsourcename1 sourcename2 [ sourcename3 ... ] targetdirectory\n.SH DESCRIPTION\nA link is a directory entry referring\nto a file; the same file (together with\nits size, all its protection\ninformation, etc.)\nmay have several links to it.\nThere are two kinds of links: hard links and symbolic links.\n.PP\nBy default\n.I ln\nmakes hard links.\nA hard link to a file is indistinguishable from the\noriginal directory entry; any changes to a\nfile are effective independent of the name used\nto reference the file.\nHard links may not span file systems and may not refer to directories.\n.PP\nThe\n.B \\-s\noption causes\n.I ln\nto create symbolic links.\nA symbolic link contains the name of the file to\nwhich it is linked.  The referenced file is used when an\n.IR open (2)\noperation is performed on the link.\nA\n.IR stat (2)\non a symbolic link will return the linked-to file; an\n.IR lstat (2)\nmust be done to obtain information about the link.\nThe\n.IR readlink (2)\ncall may be used to read the contents of a symbolic link.\nSymbolic links may span file systems and may refer to directories.\n.PP\nGiven one or two arguments,\n.I ln\ncreates a link to an existing file\n.IR sourcename .\nIf\n.I targetname\nis given, the link has that name;\n.I targetname\nmay also be a directory in which to place the link;\notherwise it is placed in the current directory.\nIf only the directory is specified, the link will be made\nto the last component of\n.IR sourcename .\n.PP\nGiven more than two arguments,\n.I ln\nmakes links in \n.I targetdirectory\nto all the named source files.\nThe links made will have the same name as the files being linked to.\n.SH \"SEE ALSO\"\nrm(1), cp(1), mv(1), link(2), readlink(2), stat(2), symlink(2)\n"
  },
  {
    "path": "share/man/man1/logger.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)logger.1\t6.1 (Berkeley) 9/17/85\n.\\\"\n.TH LOGGER 1 \"September 17, 1985\"\n.UC 6\n.SH NAME\nlogger \\- make entries in the system log\n.SH SYNOPSIS\n.B logger\n[\n.B \\-t\ntag\n] [\n.B \\-p\npri\n] [\n.B \\-i\n] [\n.B \\-f\nfile\n] [\nmessage ...\n]\n.SH ARGUMENTS\n.TP 12n\n.BI \\-t \\ tag\nMark every line in the log with the specified\n.IR tag .\n.TP\n.BI \\-p \\ pri\nEnter the message with the specified priority.\nThe priority may be specified numerically\nor as a ``facility.level''\npair.\nFor example, ``\\-p local3.info''\nlogs the message(s) as\n.IR info rmational\nlevel in the\n.I local3\nfacility.\nThe default is ``user.notice.''\n.TP\n.B \\-i\nLog the process id of the logger process\nwith each line.\n.TP\n.BI \\-f \\ file\nLog the specified file.\n.TP\nmessage\nThe message to log;\nif not specified,\nthe\n.B \\-f\nfile or standard input is logged.\n.SH DESCRIPTION\n.I Logger\nprovides a program interface to the\n.IR syslog (3)\nsystem log module.\n.PP\nA message can be given on the command line,\nwhich is logged immediately,\nor a file is read and each line is logged.\n.SH EXAMPLES\nlogger System rebooted\n.PP\nlogger \\-p local0.notice \\-t HOSTIDM \\-f /dev/idmc\n.SH SEE ALSO\nsyslog(3),\nsyslogd(8)\n"
  },
  {
    "path": "share/man/man1/login.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)login.1\t6.2.1 (2.11BSD) 1996/11/27\n.\\\"\n.TH LOGIN 1 \"November 27, 1996\"\n.UC 4\n.SH NAME\nlogin \\- sign on\n.SH SYNOPSIS\n.B login\n[ \\-p ] [ username ]\n.SH DESCRIPTION\nThe\n.I login\ncommand\nis used when a user initially\nsigns on, or it may be used at any time to change\nfrom one user to another.\nThe latter case is the one summarized above and\ndescribed here.\nSee \\*(lqHow to Get Started\\*(rq for how to dial up initially.\n.PP\nIf\n.I login\nis invoked without an argument,\nit asks for a user name, and, if\nappropriate, a password.\nEchoing is turned off (if possible) during the typing of the password,\nso it will not appear on the written record of the\nsession.\n.PP\nAfter a successful login,\naccounting files are updated and\nthe user is informed of the\nexistence of mail.\nThe message of the day is printed,\nas is the time of his last login.\nBoth are suppressed if he has a \\*(lq.hushlogin\\*(rq\nfile in his home directory; this\nis mostly used to make life easier for non-human users, such as\n.IR uucp .\n.PP\n.I Login\ninitializes the user and group IDs and the working directory,\nthen executes a command interpreter (usually\n.IR  csh (1))\naccording to specifications found in a password file.\nArgument 0 of the command interpreter is\nthe name of the command interpreter with\na leading dash (\\*(lq\\-\\*(rq).\n.PP\nLogin also modifies the\nenvironment\n.IR environ (7)\nwith information specifying home directory, command interpreter, terminal\ntype (if available) and user name.\nThe `\\-p' argument causes the remainder of the environment to be preserved,\notherwise any previous environment is discarded.\n.PP\nIf the file /etc/nologin exists,\n.I login\nprints its contents on the user's terminal and exits. This is\nused by\n.IR shutdown (8)\nto stop users logging in when the system is about to go down.\n.PP\nLogin is recognized by\n.IR sh (1)\nand\n.IR csh (1)\nand executed directly (without forking).\n.SH FILES\n.ta \\w'/usr/spool/mail/*\\ \\ 'u\n/var/run/utmp\taccounting\n.br\n/usr/adm/wtmp\taccounting\n.br\n/usr/spool/mail/*\tmail\n.br\n/etc/motd\tmessage-of-the-day\n.br\n/etc/passwd\tpassword file\n.br\n/etc/nologin\tstops logins\n.br\n\\&.hushlogin\tmakes login quieter\n.SH \"SEE ALSO\"\ninit(8), getty(8), mail(1), passwd(1), passwd(5), environ(7),\nshutdown(8), rlogin(1c)\n.SH DIAGNOSTICS\n\\*(lqLogin incorrect,\\*(rq\nif the name or the password is bad.\n.br\n\\*(lqNo Shell\\*(rq, \\*(lqcannot open password file\\*(rq,\n\\*(lqno directory\\*(rq:\nconsult a programming counselor.\n.SH BUGS\nAn undocumented option,\n.B \\-r\nis used by the remote login server,\n.IR rlogind (8C)\nto force\n.I login\nto enter into an initial connection protocol.\n.B \\-h is used by\n.IR telnetd (8C)\nand other servers to list the host from which\nthe connection was received.\n"
  },
  {
    "path": "share/man/man1/look.1",
    "content": ".\\\"\t@(#)look.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH LOOK 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nlook \\- find lines in a sorted list\n.SH SYNOPSIS\n.B look\n[\n.B \\-df\n]\nstring\n[ file ]\n.SH DESCRIPTION\n.I Look\nconsults a sorted\n.I file\nand prints all lines that begin with\n.IR string .\nIt uses binary search.\n.PP\nThe options \n.B d\nand\n.B f\naffect comparisons as in\n.IR  sort (1):\n.TP 4\n.B  d\n`Dictionary' order:\nonly letters, digits,\ntabs and blanks participate in comparisons.\n.TP 4\n.B  f\nFold.\nUpper case letters compare equal to lower case.\n.PP\nIf no\n.I file\nis specified,\n.I /usr/dict/words\nis assumed with collating sequence\n.B \\-df.\n.SH FILES\n/usr/dict/words\n.SH \"SEE ALSO\"\nsort(1), grep(1)\n"
  },
  {
    "path": "share/man/man1/lookbib.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)lookbib.1\t6.1.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH LOOKBIB 1 \"October 22, 1996\"\n.UC 5\n.SH NAME\nindxbib, lookbib \\- build inverted index for a bibliography, find references in a bibliography\n.SH SYNOPSIS\n.B indxbib\ndatabase  ...\n.br\n.B lookbib\n[\n.B \\-n\n] database\n.SH DESCRIPTION\n.I Indxbib\nmakes an inverted index to the named\n.I databases\n(or files) for use by\n.IR lookbib (1)\nand\n.IR refer (1).\nThese files contain bibliographic references\n(or other kinds of information) separated by blank lines.\n.PP\nA bibliographic reference is a set of lines,\nconstituting fields of bibliographic information.\nEach field starts on a line beginning with a ``%'',\nfollowed by a key-letter, then a blank,\nand finally the contents of the field,\nwhich may continue until the next line starting with ``%''.\n.PP\n.I Indxbib \nis a shell script that calls\n/usr/libexec/refer/mkey and /usr/libexec/refer/inv.\nThe first program,\n.I mkey,\ntruncates words to 6 characters,\nand maps upper case to lower case.\nIt also discards words shorter than 3 characters,\nwords among the 100 most common English words,\nand numbers (dates) < 1900 or > 2000.\nThese parameters can be changed; see page 4 of the\n.I Refer\ndocument by Mike Lesk.\nThe second program,\n.I inv,\ncreates an entry file (.ia),\na posting file (.ib), and a tag file (.ic),\nall in the working directory.\n.PP\n.I Lookbib\nuses an inverted index made by\n.I indxbib\nto find sets of bibliographic references.\nIt reads keywords typed after the ``>'' prompt on the terminal,\nand retrieves records containing all these keywords.\nIf nothing matches, nothing is returned except another ``>'' prompt.\n.PP\n.I Lookbib\nwill ask if you need instructions, and will print some brief information if\nyou reply ``y''.  The ``\\-n'' flag turns off the prompt for instructions.\n.PP\nIt is possible to search multiple databases,\nas long as they have a common index made by\n.I indxbib.\nIn that case, only the first argument given to\n.I indxbib\nis specified to\n.I lookbib.\n.PP\nIf\n.I lookbib\ndoes not find the index files (the .i[abc] files),\nit looks for a reference file with the same name as the argument,\nwithout the suffixes.\nIt creates a file with a '.ig' suffix, suitable for use with\n.I fgrep.\nIt then uses this fgrep file to find references.\nThis method is simpler to use, but the .ig file is slower to use\nthan the .i[abc] files, and does not allow the use of multiple reference files.\n.SH FILES\n.IR x .ia,\n.IR x .ib,\n.IR x .ic,\nwhere \n.I x\nis the first argument, or if these are not present, then\n.IR x .ig,\n.IR x\n.SH SEE ALSO\nrefer(1), addbib(1), sortbib(1), roffbib(1), lookbib(1)\n.SH BUGS\nProbably all dates should be indexed,\nsince many disciplines refer to literature\nwritten in the 1800s or earlier.\n"
  },
  {
    "path": "share/man/man1/lorder.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)lorder.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH LORDER 1 \"April 29, 1985\"\n.UC 4\n.SH NAME\nlorder \\- find ordering relation for an object library\n.SH SYNOPSIS\n.B lorder\nfile ...\n.SH DESCRIPTION\nThe input\nis one or more object or library archive (see\n.IR ar (1))\n.I files.\nThe standard output\nis a list of pairs of object file names,\nmeaning that the first file of the pair refers to\nexternal identifiers defined in the second.\nThe output may be processed by\n.IR  tsort (1)\nto find an ordering of\na library suitable for one-pass access by\n.IR  ld (1).\n.PP\nThis brash one-liner intends to build a new library\nfrom existing `.o' files.\n.IP\nar cr library \\`\\|lorder *.o | tsort\\`\n.PP\nThe need for lorder may be vitiated by use of \n.IR ranlib (1),\nwhich converts an ordered archive into a randomly\naccessed library.\n.SH FILES\n*symref, *symdef\n.br\nnm(1), sed(1), sort(1), join(1)\n.SH \"SEE ALSO\"\ntsort(1),\nld(1),\nar(1),\nranlib(1)\n.SH BUGS\nThe names of object files, in and out of libraries, must end with `.o';\nnonsense results otherwise.\n"
  },
  {
    "path": "share/man/man1/lpq.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)lpq.1\t6.2 (Berkeley) 6/5/86\n.\\\"\n.TH LPQ 1 \"June 5, 1986\"\n.UC 5\n.SH NAME\nlpq \\- spool queue examination program\n.SH SYNOPSIS\n.B lpq\n[ +[ n ] ] [ -l ] [ \\-Pprinter ] [ job # ... ] [ user ... ]\n.SH DESCRIPTION\n.I lpq\nexamines the spooling area used by\n.IR lpd (8)\nfor printing\nfiles on the line printer, and reports the status of the specified jobs or\nall jobs associated with a user. \n.I lpq\ninvoked without any arguments\nreports on any jobs currently in the queue.  A\n.B \\-P\nflag may be used\nto specify a particular printer, otherwise the default line printer\nis used (or the value of the PRINTER variable in the environment).\nIf a\n.B \\(pl\nargument is supplied,\n.I lpq\ndisplays the spool queue until it empties.  Supplying a number\nimmediately after the\n.B \\(pl\nsign indicates that\n.I lpq\nshould sleep \\fIn\\fR seconds in between scans of the queue.\nAll other arguments supplied are\ninterpreted as user names or job numbers to filter out only those\njobs of interest.\n.PP\nFor each job submitted (i.e. invocation of \n.IR lpr (1))\n.I lpq\nreports the user's name, current rank in the queue, the\nnames of files comprising the job, the job identifier (a number which\nmay be supplied to\n.IR lprm (1)\nfor removing a specific job), and the total size in bytes.\nThe\n.B \\-l\noption causes information about each of the files comprising the job\nto be printed.\nNormally, only as much information as will fit on one line is displayed.\nJob ordering is dependent on\nthe algorithm used to scan the spooling directory and is supposed\nto be FIFO (First in First Out).\nFile names comprising a job may be unavailable\n(when\n.IR lpr (1)\nis used as a sink in a pipeline) in which case the file\nis indicated as ``(standard input)\".\n.PP\nIf\n.I lpq\nwarns that there is no daemon present (i.e. due to some malfunction),\nthe\n.IR lpc (8)\ncommand can be used to restart the printer daemon.\n.SH FILES\n.nf\n.ta \\w'/etc/termcap            'u\n/etc/termcap\tfor manipulating the screen for repeated display\n/etc/printcap\tto determine printer characteristics\n/usr/spool/*\tthe spooling directory, as determined from printcap\n/usr/spool/*/cf*\tcontrol files specifying jobs\n/usr/spool/*/lock\tthe lock file to obtain the currently active job \n.fi\n.SH \"SEE ALSO\"\nlpr(1),\nlprm(1),\nlpc(8),\nlpd(8)\n.SH BUGS\nDue to the dynamic nature of the information in the spooling directory\nlpq may report unreliably.\nOutput formatting is sensitive to the line length of the terminal;\nthis can results in widely spaced columns.\n.SH DIAGNOSTICS\nUnable to open various files.  The lock file being malformed.  Garbage\nfiles when there is no daemon active, but files in the spooling directory.\n"
  },
  {
    "path": "share/man/man1/lpr.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)lpr.1\t6.1.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH LPR 1 \"October 22, 1996\"\n.UC 4\n.SH NAME\nlpr \\- off line print\n.SH SYNOPSIS\n.B lpr\n[\n.BI \\-P printer\n] [\n.BI \\-# num\n] [\n.B \\-C\n.I class\n] [\n.B \\-J\n.I job\n] [\n.B \\-T\n.I title\n] [\n.B \\-i\n[\n.I numcols\n]] [\n.B \\-1234\n.I font\n] [\n.BI \\-w num\n] [\n.B \\-pltndgvcfrmhs\n] [\nname ...\n]\n.SH DESCRIPTION\n.B Lpr\nuses a spooling daemon to print the named files when facilities\nbecome available.  If no names appear, the standard input is assumed.\nThe\n.B \\-P\noption may be used to force output to a specific printer.  Normally,\nthe default printer is used (site dependent), or the value of the\nenvironment variable PRINTER is used.\n.PP\nThe following single letter options are used to notify the line printer\nspooler that the files are not standard text files. The spooling daemon will\nuse the appropriate filters to print the data accordingly.\n.IP \\fB\\-p\\fP 5\nUse\n.IR pr (1)\nto format the files (equivalent to\n.IR print ).\n.IP \\fB\\-l\\fP 5\nUse a filter which allows control characters to be printed and suppresses\npage breaks.\n.IP \\fB\\-t\\fP 5\nThe files are assumed to contain data from\n.IR troff (1)\n(cat phototypesetter commands).\n.IP \\fB\\-n\\fP 5\nThe files are assumed to contain data from\n.I ditroff\n(device independent troff).\n.IP \\fB\\-d\\fP 5\nThe files are assumed to contain data from\n.IR tex (l)\n(DVI format from Stanford).\n.IP \\fB\\-g\\fP 5\nThe files are assumed to contain standard plot data as produced by the\n.IR plot (3X)\nroutines (see also\n.IR plot (1G)\nfor the filters used by the printer spooler).\n.IP \\fB\\-v\\fP 5\nThe files are assumed to contain a raster image for devices like the\nBenson Varian.\n.IP \\fB\\-c\\fP 5\nThe files are assumed to contain data produced by\n.IR cifplot (l).\n.IP \\fB\\-f\\fP 5\nUse a filter which interprets the first character of each line as a\nstandard FORTRAN carriage control character.\n.PP\nThe remaining single letter options have the following meaning.\n.IP \\fB\\-r\\fP 5\nRemove the file upon completion of spooling or upon completion of\nprinting (with the \\fB\\-s\\fP option).\n.IP \\fB\\-m\\fP 5\nSend mail upon completion.\n.IP \\fB\\-h\\fP 5\nSuppress the printing of the burst page.\n.IP \\fB\\-s\\fP 5\nUse symbolic links.  Usually files are copied to the spool directory.\n.PP \nThe\n.B \\-C\noption takes the following argument as a job classification\nfor use on the burst page.  For example,\n.PP\n.ti +0.5i\nlpr \\-C EECS foo.c\n.PP\ncauses the system name (the name returned by\n.IR hostname (1))\nto be replaced on the burst page by EECS,\nand the file foo.c to be printed.\n.PP\nThe\n.B \\-J\noption takes the following argument as the job name to print on the burst page.\nNormally, the first file's name is used.\n.PP\nThe\n.B \\-T\noption uses the next argument as the title used by\n.IR pr (1)\ninstead of the file name.\n.PP\nTo get multiple copies of output, use the\n.BI \\-# num\noption,\nwhere\n.I num\nis the number of copies desired of each file named.  For example,\n.PP\n.ti +0.5i\nlpr \\-#3 foo.c bar.c more.c\n.PP\nwould result in 3 copies of the file foo.c, followed by 3 copies\nof the file bar.c, etc.  On the other hand, \n.PP\n.ti +0.5i\ncat foo.c bar.c more.c | lpr \\-#3\n.PP\nwill give three copies of the concatenation of the files.\n.PP\nThe\n.B \\-i\noption causes the output to be indented. If the next argument\nis numeric, it is used as the number of blanks to be printed before each\nline; otherwise, 8 characters are printed.\n.PP\nThe\n.B \\-w\noption takes the immediately following number to be\nthe page width for\n.IR pr .\n.PP\nThe\n.B \\-s\noption will use\n.IR symlink (2)\nto link data files rather than trying to copy them so large files can be\nprinted.  This means the files should\nnot be modified or removed until they have been printed.\n.PP\nThe option\n.B \\-1234\nSpecifies a font to be mounted on font position \\fIi\\fR.  The daemon\nwill construct a \\fI.railmag\\fR file referencing\n\\fI/usr/share/vfont/name.size\\fR.\n.SH FILES\n.nf\n.ta \\w'/usr/spool/*/cf*       'u\n/etc/passwd\tpersonal identification\n/etc/printcap\tprinter capabilities data base\n/usr/sbin/lpd\tline printer daemon\n/usr/spool/*\tdirectories used for spooling\n/usr/spool/*/cf*\tdaemon control files\n/usr/spool/*/df*\tdata files specified in \"cf\" files\n/usr/spool/*/tf*\ttemporary copies of \"cf\" files\n.fi\n.SH \"SEE ALSO\"\nlpq(1),\nlprm(1),\npr(1),\nsymlink(2),\nprintcap(5),\nlpc(8),\nlpd(8)\n.SH DIAGNOSTICS\nIf you try to spool too large a file, it will be truncated.\n.I Lpr\nwill object to printing binary files.\nIf a user other than root prints a file and spooling is disabled,\n.I lpr\nwill print a message saying so and will not put jobs in the queue.\nIf a connection to\n.I lpd\non the local machine cannot be made,\n.I lpr\nwill say that the daemon cannot be started.\nDiagnostics may be printed in the daemon's log file\nregarding missing spool files by\n.IR lpd .\n.SH BUGS\nFonts for\n.I troff\nand\n.I tex\nreside on the host with the printer. It is currently not possible to\nuse local font libraries.\n"
  },
  {
    "path": "share/man/man1/lprm.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)lprm.1\t6.1.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH LPRM 1 \"October 22, 1996\"\n.UC 5\n.SH NAME\nlprm \\- remove jobs from the line printer spooling queue\n.SH SYNOPSIS\n.B lprm\n[\n.BI \\-P printer\n] [\n.B \\-\n] [\njob # ...\n] [\nuser ...\n]\n.SH DESCRIPTION\n.I Lprm\nwill remove a job, or jobs, from a printer's spool queue.\nSince the spooling directory is protected from users, using\n.I lprm\nis normally the only method by which a user may remove a job.\n.PP\n.I Lprm\nwithout any arguments will delete the currently active job if it is\nowned by the user who invoked\n.IR lprm .\n.PP\nIf the\n.B \\-\nflag is specified, \n.I lprm\nwill remove all jobs which a user\nowns.  If the super-user employs this flag, the spool queue will\nbe emptied entirely. The owner is determined by the user's login name\nand host name on the machine where the\n.I lpr\ncommand was invoked.\n.PP\nSpecifying a user's name, or list of user names, will cause\n.I lprm\nto attempt to remove any jobs queued belonging to that user\n(or users).  This form of invoking\n.I lprm\nis useful only to the super-user.\n.PP\nA user may dequeue an individual job by specifying its job number.\nThis number may be obtained from the\n.IR lpq (1)\nprogram, e.g.\n.PP\n.nf\n.in +0.5i\n.ta \\w'k0-k9  'u +\\w'Type  'u +\\w'\"/usr/sbin/lpd\"  'u\n.ta \\w'1st: 'u +\\w'(standard input)      \t\t'u\n% lpq \\-l\n\n1st: ken\t[job #013ucbarpa]\n\t(standard input)\t100 bytes\n% lprm 13\n.in -0.5i\n.fi\n.PP\n.I Lprm\nwill announce the names of any files it removes and is silent if\nthere are no jobs in the queue which match the request list.\n.PP\n.I Lprm\nwill kill off an active daemon, if necessary, before removing\nany spooling files.  If a daemon is killed, a new one is\nautomatically restarted upon completion of file removals.\n.PP\nThe\n.B \\-P\noption may be usd to specify the queue associated with a specific\nprinter (otherwise the default printer, or the value of the PRINTER\nvariable in the environment is used).\n.SH FILES\n.nf\n.ta \\w'/usr/spool/*/lock   'u\n/etc/printcap\tprinter characteristics file\n/usr/spool/*\tspooling directories\n/usr/spool/*/lock\tlock file used to obtain the pid of the current\n\tdaemon and the job number of the currently active job\n.fi\n.SH \"SEE ALSO\"\nlpr(1),\nlpq(1),\nlpd(8)\n.SH DIAGNOSTICS\n``Permission denied\" if the user tries to remove files other than his\nown.\n.SH BUGS\nSince there are race conditions possible in the update of the lock file,\nthe currently active job may be incorrectly identified.\n"
  },
  {
    "path": "share/man/man1/lptest.1",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)lptest.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH LPTEST 1 \"April 29, 1985\"\n.UC 6\n.SH NAME\nlptest \\- generate lineprinter ripple pattern\n.SH SYNOPSIS\n.B lptest\n[\n.B length\n[\n.B count\n] ]\n.br\n.SH DESCRIPTION\n.I Lptest\nwrites the traditional \"ripple test\" pattern on standard output.\nIn 96 lines,\nthis pattern will print all 96 printable ASCII characters\nin each position.\nWhile originally created to test printers, it is quite\nuseful for testing terminals,\ndriving terminal ports for debugging purposes,\nor any other task where a quick supply of random data is needed.\n.PP\nThe \n.I length\nargument specifies the output line length if the the default \nlength of 79 is inappropriate.\n.PP\nThe\n.I count\nargument specifies the number of output lines to be generated if\nthe default count of 200 is inappropriate.\nNote that if \n.I count\nis to be specified,\n.I length\nmust be also be specified.\n.SH \"SEE ALSO\"\n.SH BUGS\n"
  },
  {
    "path": "share/man/man1/ls.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ls.1\t6.4.2 (2.11BSD GTE) 1996/12/23\n.\\\"\n.TH LS 1 \"December 20, 1994\"\n.UC\n.SH NAME\nls \\- list contents of directory\n.SH SYNOPSIS\n.B ls\n[\n.B \\-acdfgiloqrstu1ACLFR\n] name ...\n.br\n.SH DESCRIPTION\nFor each directory argument,\n.I ls\nlists the contents of the directory;\nfor each file argument,\n.I ls\nrepeats its name and any other information requested.\nBy default, the output is sorted alphabetically.\nWhen no argument is given, the current directory is listed.\nWhen several arguments are given,\nthe arguments are first sorted appropriately,\nbut file arguments are processed\nbefore directories and their contents.\n.PP\nThere are a large number of options:\n.TP\n.B \\-l\nList in long format, giving mode, number of links, owner,\nsize in bytes, and time of last modification\nfor each file.\n(See below.)\nIf the file is a special file the size field will instead contain\nthe major and minor device numbers.\nIf the file is a symbolic link the pathname of\nthe linked-to file is printed preceded by ``\\->''.\n.TP\n.B \\-o\nInclude the file flags in a long (\\-l) output.\n.TP\n.B \\-g\nInclude the group ownership of the file in a long output.\n.TP\n.B \\-t\nSort by time modified (latest first) instead of\nby name.\n.TP\n.B \\-a\nList all entries; in the absence of this option, entries whose\nnames begin with a period\n.RB ( . )\nare\n.I not\nlisted.\n.TP\n.B \\-s\nGive size in kilobytes of each file.\n.TP\n.B \\-d\nIf argument is a directory, list only its name;\noften used with \\fB\\-l\\fR to get the status of a directory.\n.TP\n.B \\-L\nIf argument is a symbolic link, list the file or directory the link references\nrather than the link itself.\n.TP\n.B \\-r\nReverse the order of sort to get reverse alphabetic\nor oldest first as appropriate.\n.TP\n.B \\-u\nUse time of last access instead of last\nmodification for sorting\n(with the \\fB\\-t\\fP option)\nand/or printing (with the \\fB\\-l\\fP option).\n.TP\n.B \\-c\nUse time of file creation for sorting or printing.\n.TP\n.B \\-i\nFor each file, print the i-number in the first column of the report.\n.TP\n.B \\-f\nOutput is not sorted.\n.TP\n.B \\-F\ncause directories to be marked with a trailing `/',\nsockets with a trailing `=',\nsymbolic links with a trailing `@', and executable\nfiles with a trailing `*'.\n.TP\n.B \\-R\nrecursively list subdirectories encountered.\n.TP\n.B \\-1\nforce one entry per line output format; this is the default when\noutput is not to a terminal.\n.TP\n.B \\-C\nforce multi-column output; this is the default when output is to a terminal.\n.TP\n.B \\-q\nforce printing of non-graphic characters in file names as\nthe character `?'; this is the default when output is to a terminal.\n.PP\nThe mode printed under the\n.B \\-l\noption contains 11 characters\nwhich are interpreted\nas follows:\nthe first character is\n.TP 3\n.B d\nif the entry is a directory;\n.br\n.ns\n.TP 3\n.B b\nif the entry is a block-type special file;\n.br\n.ns\n.TP 3\n.B c\nif the entry is a character-type special file;\n.br\n.ns\n.TP 3\n.B l\nif the entry is a symbolic link;\n.br\n.ns\n.TP\n.B s\nif the entry is a socket, or\n.br\n.ns\n.TP 3\n.B  \\-\nif the entry is a plain file.\n.PP\nThe next 9 characters are interpreted\nas three sets of three bits each.\nThe first set refers to owner permissions;\nthe next refers to permissions to others in the same user-group;\nand the last to all others.\nWithin each set the three characters indicate\npermission respectively to read, to write, or to\nexecute the file as a program.\nFor a directory, `execute' permission is interpreted\nto mean permission to search the directory.\nThe permissions are indicated as follows:\n.TP 3\n.B  r\nif the file is readable;\n.br\n.ns\n.TP 3\n.B  w\nif the file is writable;\n.br\n.ns\n.TP 3\n.B  x\nif the file is executable;\n.br\n.ns\n.TP 3\n.B  \\-\nif the indicated permission is not granted.\n.PP\nThe group-execute permission character is given\nas\n.B s\nif the file has the set-group-id bit set;\nlikewise the user-execute permission character is given\nas\n.B s\nif the file has the set-user-id bit set.\n.PP\nThe last character of the mode (normally `x' or `\\-') is \n.B t\nif the 1000 bit of the mode is on.\nSee\n.IR  chmod (1)\nfor the meaning of this mode.\n.PP\nWhen the sizes of the files in a directory\nare listed, a total count of blocks,\nincluding indirect blocks is printed.\n.SH FILES\n/etc/passwd to get user id's for\n`ls \\-l'.\n.br\n/etc/group to get group id's for\n`ls \\-g'.\n.SH BUGS\nNewline and tab are considered printing characters in file names.\n.PP\nThe output device is assumed to be 80 columns wide.\n.PP\nThe option setting based on whether the output is a teletype is\nundesirable as ``ls\\ \\-s'' is much different than ``ls\\ \\-s\\ |\\ lpr''.\nOn the other hand, not doing this setting would make old shell scripts\nwhich used\n.I ls\nalmost certain losers.\n"
  },
  {
    "path": "share/man/man1/lxref.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)lxref.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH LXREF 1 \"April 29, 1985\"\n.UC 4\n.SH NAME\nlxref \\- lisp cross reference program\n.SH SYNOPSIS\n.B lxref\n[\n.B \\-N\n] xref-file ...\n[ \n.B \\-a \nsource-file ... ]\n.SH DESCRIPTION\n.I Lxref\nreads cross reference file(s) written by the lisp compiler \n.I liszt\nand prints a cross reference listing on the standard output.\n.I Liszt\nwill create a cross reference file during compilation when it is \ngiven the\n.B \\-x\nswitch.\nCross reference files usually end in `.x' and consequently\n.I lxref\nwill append a `.x' to the file names given if necessary.\nThe first option to \n.I lxref\nis a decimal integer, N, which sets the \n.I ignorelevel.\nIf a function is called more than \n.I ignorelevel \ntimes, the cross reference listing will just print the number of calls \ninstead of listing each one of them.\nThe default for\n.I ignorelevel \nis 50.\n.PP\nThe \n.B \\-a\noption causes \n.I lxref\nto put limited cross reference information in the sources named.\n.I lxref\nwill scan the source and when it comes across a definition of a function\n(that is a line beginning with \n.I \"`(def'\"\nit will preceed that line with a list of the functions which call this \nfunction, written as a comment preceeded by \n.I \"`;.. '\".\nAll existing lines beginning with\n.I \"`;.. '\"\nwill be removed from the file.\nIf the source file contains a line beginning\n.I \"`;.-'\"\nthen this will disable this annotation process from this point on until a \n.I \"`;.+'\"\nis seen (however, lines beginning with \n.I \"`;.. '\"\nwill continue to be deleted).\nAfter the annoation is done, the original file\n.I \"`foo.l'\"\nis renamed to\n.I `#.foo.l'\"\nand the new file with annotation is named \n.I \"`foo.l'\"\n.SH AUTHOR\nJohn Foderaro\n.SH SEE ALSO\nlisp(1),\nliszt(1)\n.SH BUGS\n"
  },
  {
    "path": "share/man/man1/m4.1",
    "content": ".\\\"\t@(#)m4.1\t1.0 (2.11BSD GTE) 4/14/94\n.\\\"\n.TH M4 1 \"April 14, 1994\"\n.UC 2\n.SH NAME\nm4 \\- macro processor\n.SH SYNOPSIS\nm4 [ -D\\fBname\\fP[\\fB=value\\fP]] [-U\\fBname\\fP] [files ...]\n.SH DESCRIPTION\n.I m4\nis a macro processor intended as a front end for any language (e.g., C, \nratfor, fortran, lex, and yacc).  \\fIm4\\fP reads from the standard input\nand writes the processed text to the standard output.\nEach of the optional argument files is processed in order.\n.PP\nMacro calls have the form\n.PP\n\tname(arg1,arg2, . . . , argn)\n.br\n.PP\nThe `(' must immediately follow the name of the macro.\nIf a defined macro name is not followed by a `(',\nit is deemed to have no arguments.\nLeading unquoted blanks, tabs, and newlines are ignored while collecting\narguments.  Potential macro names consist of alphabetic letters,\ndigits, and underscore `\\_', where the first character is not a digit.\n.PP\nLeft and right single quotes (\\`\\|\\') are used to quote strings.\nThe value of a quoted string is the string stripped of the quotes.\n.PP\nWhen a macro name is recognized, its arguments are collected by searching\nfor a matching right parenthesis.\nMacro evaluation proceeds normally during the collection of the arguments,\nand any commas or right parentheses which happen to turn up within the value\nof a nested call are as effective as those in the original input text.\nAfter argument collection, the value of the macro is pushed back onto the\ninput stream and rescanned.\n.TP 10\n-D\\fBname\\fP[\\fB=value\\fP]\nDefine the symbol \\fBname\\fP to have some value (or NULL).\n.TP 10\n-U\\fBname\\fP\nUndefine the symbol \\fBname\\fP.\n.PP\n.I m4\nmakes available the following built-in macros.\nThey may be redefined, but once this is done the original meaning is lost.\nTheir values are null unless otherwise stated.\n.TP 10\n.B define\nThe second argument is installed as the value of the macro\nwhose name is the first argument.\nEach occurrence of $\\fIn\\fR in the replacement text, where\n.I n\nis a digit, is replaced by the\n.IR n -th\nargument.  Argument 0 is the name of the macro;\nmissing arguments are replaced by the null string.\n.TP\n.B undefine\nremoves the definition of the macro named in its argument.\n.TP\n.B ifdef\nIf the first argument is defined, the value is the second argument,\notherwise the third.  If there is no third argument, the value is null.\n.TP\n.B changecom\nChange the start and end comment sequences.  The default is the pound\nsign '#' and the newline character.  With no arguments comments\nare turned off.  The maximum legnth for a comment marker is five\ncharacters.\n.TP\n.B changequote\nChange quote characters to the first and second arguments.\n.I Changequote\nwithout arguments restores the original values (i.e., \\`\\|\\').\n.TP\n.B decr\nDecrements the argument by 1.  The argument must be a valid numeric\nstring.\n.TP\n.B divert\n.I m4\nmaintains 10 output streams, numbered 0-9.\nThe final output is the concatenation of the streams in numerical order;\ninitially stream 0 is the current stream.  The\n.I divert\nmacro changes the current output stream to its (digit-string) argument.\nOutput diverted to a stream other than 0 through 9 is discarded.\n.TP\n.B undivert\ncauses immediate output of text from diversions named as\narguments, or all diversions if no argument.\nText may be undiverted into another diversion.\nUndiverting discards the diverted text.\n.TP\n.B defn\nReturns the quoted definition for each argument.  This can be used to\nrename macro definitions (even for builtin macros).\n.TP\n.B divnum\nreturns the value of the current output stream.\n.TP\n.B dnl\nreads and discards characters up to and including the next newline.\n.TP\n.B expr\nThis is an alias for eval.\n.TP\n.B ifelse\nhas three or more arguments.\nIf the first argument is the same string as the second,\nthen the value is the third argument.\nIf not, and if there are more than four arguments, the process is repeated with arguments 4, 5, 6 and 7.\nOtherwise, the value is either the fourth string, or, if it is not present,\nnull.\n.TP\n.B incr\nreturns the value of its argument incremented by 1.\nThe value of the argument is calculated\nby interpreting an initial digit-string as a decimal number.\n.TP\n.B eval\nevaluates its argument as an arithmetic expression, using 32-bit arithmetic.\nOperators include +, \\-, \\(**, /, %, ^ (exponentiation); relationals;\nparentheses.\n.TP\n.B len\nreturns the number of characters in its argument.\n.TP\n.B m4exit\nImmediately exits with the return value specified by the first\nargument, 0 if none.\n.TP\n.B m4wrap\nAllows you to define what happens at the final EOF, usually for cleanup\npurposes.  (e.g., m4wrap(\"cleanup(tempfile)\") causes the macro cleanup\nto be invoked after all processing is done.)\n.TP\n.B index\nreturns the position in its first argument where the second argument\nbegins (zero origin), or \\-1 if the second argument does not occur.\n.TP\n.B substr\nreturns a substring of its first argument.\nThe second argument is a zero origin number selecting the first character;\nthe third argument indicates the length of the substring.\nA missing third argument is taken to be large enough to extend to\nthe end of the first string.\n.TP\n.B translit\ntransliterates the characters in its first argument\nfrom the set given by the second argument to the set given by the third.\nNo abbreviations are permitted.\n.TP\n.B include\nreturns the contents of the file named in the argument.\n.TP\n.B sinclude\nis identical to\n.I include,\nexcept that it says nothing if the file is inaccessible.\n.TP\n.B syscmd\nexecutes the UNIX command given in the first argument.\nNo value is returned.\n.TP\n.B maketemp\nfills in a string of XXXXX in its argument with the current process id.\n.TP\n.B paste\nIncludes the contents of the file specified by the first argument\nwithout any macro processing.  Aborts with an error message if the\nfile cannot be included.\n.TP\n.B popdef\nRestores the pushdef'd definition for each argument.\n.TP\n.B pushdef\nTakes the same arguments as define, but it saves the definition on a \nstack for later retrieval by popdef.\n.TP\n.B shift\nReturns all but the first argument, the remaining arguments are quoted\nand pushed back with commas in between.  The quoting nullifies the effect\nof the extra scan that will subsequently be performed.\n.TP\n.B spaste\nSimilar to paste, except it ignores any errors.\n.TP\n.B syscal\nReturns the return value from the last syscmd.\n.TP\n.B errprint\nprints its argument on the diagnostic output file.\n.TP\n.B dumpdef\nprints current names and definitions,\nfor the named items, or for all if no arguments are given.\n.TP\n.B unix\nA pre-defined macro for testing the OS platform.\n.SH \"SEE ALSO\"\n.DT\nB. W. Kernighan and D. M. Ritchie,\n.I The m4 Macro Processor\n.SH HISTORY\nAn m4 command appeared in Version 6 AT&T UNIX.\n.SH AUTHOR\nOzan Yigit <oz@sis.yorku.ca>\n"
  },
  {
    "path": "share/man/man1/mail.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)mail.1\t6.6.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH MAIL 1 \"October 22, 1996\"\n.UC 4\n.SH NAME\nmail \\- send and receive mail\n.SH SYNOPSIS\n.B mail\n[\n.B \\-v\n]\n[\n.B \\-i\n]\n[\n.B \\-n\n]\n[\n.B \\-s\nsubject\n]\n[\nuser ...\n]\n.br\n.B mail\n[\n.B \\-v\n]\n[\n.B \\-i\n]\n[\n.B \\-n\n]\n.B \\-f\n[\nname\n]\n.br\n.B mail\n[\n.B \\-v\n]\n[\n.B \\-i\n]\n[\n.B \\-n\n]\n.B \\-u\nuser\n.SH INTRODUCTION\n.I Mail\nis a intelligent mail processing system, which has\na command syntax reminiscent of\n.I ed\nwith lines replaced by messages.\n.PP\nThe\n.B \\-v\nflag puts mail into verbose mode; the details of\ndelivery are displayed on the users terminal.\nThe\n.B \\-i\nflag causes tty interrupt signals to be ignored. This is\nparticularly useful when using\n.I mail\non noisy phone lines.\nThe\n.B \\-n\nflag inhibits the reading of /etc/Mail.rc.\n.PP\n.I \"Sending mail.\\ \"\nTo send a message to one or more people,\n.I mail\ncan be invoked with arguments which are the names of people to \nwhom the mail will be sent.  You are then expected to type in \nyour message, followed\nby an \\s-2EOT\\s0 (control\\-D) at the beginning of a line.\nA subject may be specified on the command line by using the\n.B \\-s\nflag. (Only the first argument after the\n.B \\-s\nflag is used as a subject; be careful to quote subjects\ncontaining spaces.)\nThe section below, labeled\n.I \"Replying to or originating mail,\"\ndescribes some features of\n.I mail\navailable to help you compose your letter.\n.PP\n.I \"Reading mail.\\ \"\nIn normal usage\n.I mail\nis given no arguments and checks your mail out of the\npost office, then\nprints out a one line header of each message there.\nThe current message is initially the first message (numbered 1)\nand can be printed using the\n.B print\ncommand (which can be abbreviated \\fBp\\fR).\nYou can move among the messages much as you move between lines in\n.IR ed ,\nwith the commands `+' and `\\-' moving backwards and forwards, and\nsimple numbers.\n.PP\n.I \"Disposing of mail.\\ \"\nAfter examining a message you can\n.B delete\n(\\fBd\\fR)\nthe message or\n.B reply\n(\\fBr\\fR)\nto it.\nDeletion causes the\n.I mail\nprogram to forget about the message.\nThis is not irreversible; the message can be\n.B undeleted\n(\\fBu\\fR)\nby giving its number, or the\n.I mail\nsession can be aborted by giving the\n.B exit\n(\\fBx\\fR)\ncommand.\nDeleted messages will, however, usually disappear never to be seen again.\n.PP\n.I \"Specifying messages.\\ \"\nCommands such as\n.B print\nand\n.B delete\ncan be given a list of message numbers as arguments to apply\nto a number of messages at once.\nThus ``delete 1 2'' deletes messages 1 and 2, while ``delete 1\\-5''\ndeletes messages 1 through 5.\nThe special name ``*'' addresses all messages, and ``$'' addresses\nthe last message; thus the command\n.B top\nwhich prints the first few lines of a message could be used in\n``top *'' to print the first few lines of all messages.\n.PP\n.I \"Replying to or originating mail.\\ \"\nYou can use the\n.B reply\ncommand to\nset up a response to a message, sending it back to the\nperson who it was from.\nText you then type in, up to an end-of-file,\ndefines the contents of the message.\nWhile you are composing a message,\n.I mail\ntreats lines beginning with the character `~' specially.\nFor instance, typing ``~m'' (alone on a line) will place a copy\nof the current message into the response right shifting it by a tabstop.\nOther escapes will set up subject fields, add and delete recipients\nto the message and allow you to escape to an editor to revise the\nmessage or to a shell to run some commands.  (These options\nare given in the summary below.)\n.PP\n.I \"Ending a mail processing session.\\ \"\nYou can end a\n.I mail\nsession with the\n.B quit\n(\\fBq\\fR)\ncommand.\nMessages which have been examined go to your\n.I mbox\nfile unless they have been deleted in which case they are discarded.\nUnexamined messages go back to the post office.\nThe\n.B \\-f\noption causes\n.I mail\nto read in the contents of your\n.I mbox\n(or the specified file)\nfor processing; when you\n.BR quit ,\n.I mail\nwrites undeleted messages back to this file.\nThe\n.B \\-u\nflag is a short way of doing\n\"mail\n.B \\-f\n/usr/spool/mail/user\".\n.PP\n.I \"Personal and systemwide distribution lists.\\ \"\nIt is also possible to create a personal distribution lists so that,\nfor instance, you can send mail to ``cohorts'' and have it go\nto a group of people.\nSuch lists can be defined by placing a line like\n.IP\nalias cohorts bill ozalp jkf mark kridle@ucbcory\n.PP\nin the file \\&.mailrc in your home directory.\nThe current list of such aliases can be displayed with the\n.B alias\n.B (a)\ncommand in\n.IR mail .\nSystem wide distribution lists can be created by editing\n/etc/aliases, see\n.IR aliases (5)\nand\n.IR sendmail (8);\nthese are kept in a different syntax.\nIn mail you send, personal aliases will be expanded in mail sent\nto others so that they will be able to \\fBreply\\fR to the recipients.\nSystem wide \\fIaliases\\fR are not expanded when the mail is sent,\nbut any reply returned to the machine will have the system wide\nalias expanded as all mail goes through\n.IR sendmail .\n.PP\n.I \"Network mail (ARPA, UUCP, Berknet)\\ \"\nSee\n.IR mailaddr(7)\nfor a description of network addresses.\n.PP\n.I Mail\nhas a number of options which can be set in the\n.I \\&.mailrc\nfile to alter its behavior; thus ``set askcc'' enables the ``askcc''\nfeature.  (These options are summarized below.)\n.SH SUMMARY\n(Adapted from the `Mail Reference Manual')\n.PP\nEach command is typed on a line by itself, and may take arguments\nfollowing the command word.  The command need not be typed in its\nentirety \\- the first command which matches the typed prefix is used.\nFor commands which take message lists as arguments, if no message\nlist is given, then the next message forward which satisfies the\ncommand's requirements is used.  If there are no messages forward of\nthe current message, the search proceeds backwards, and if there are no\ngood messages at all,\n.I mail\ntypes ``No applicable messages'' and\naborts the command.\n.TP 12n\n.B \\-\nGoes to the previous message and prints it out.  If given a numeric\nargument\n.IR n ,\ngoes to the\n.IR n -th\nprevious message and prints it.\n.TP\n.B ?\nPrints a brief summary of commands.\n.TP\n.B !\nExecutes the \\s-2UNIX\\s0 shell command which follows.\n.TP\n.B Print\n(\\fBP\\fR)\nLike\n.B print\nbut also prints out ignored header fields. See also\n.B print\n,\n.B ignore\nand\n.B retain.\n.TP\n.B Reply\n(\\fBR\\fR)\nReply to originator. Does not reply to other\nrecipients of the original message.\n.TP\n.B Type\n(\\fBT\\fR)\nIdentical to the\n.B Print\ncommand.\n.TP\n.B alias\n(\\fBa\\fR) With no arguments, prints out all currently-defined aliases.  With one\nargument, prints out that alias.  With more than one argument, creates\nan new or changes an on old alias.\n.TP\n.B alternates\n(\\fBalt\\fR)\nThe\n.B alternates\ncommand is useful if you have accounts on several machines.\nIt can be used to inform\n.I mail\nthat the listed addresses are really you. When you\n.B reply\nto messages,\n.I mail\nwill not send a copy of the message to any of the addresses\nlisted on the\n.I alternates\nlist. If the\n.B alternates\ncommand is given with no argument, the current set of alternate\nnames is displayed.\n.TP\n.B chdir\n(\\fBc\\fR) Changes the user's working directory to that specified, if given.  If\nno directory is given, then changes to the user's login directory.\n.TP\n.B copy\n(\\fBco\\fR)\nThe\n.B copy\ncommand does the same thing that\n.B save \ndoes, except that it does not mark the messages it\nis used on for deletion when you quit.\n.TP\n.B delete\n(\\fBd\\fR) Takes a list of messages as argument and marks them all as deleted.\nDeleted messages will not be saved in\n.IR mbox ,\nnor will they be available for most other commands.  \n.TP\n.B dp\n(also \\fBdt\\fR) Deletes the current message and prints the next message.\nIf there is no next message, \n.I mail\nsays ``at EOF.''\n.TP\n.B edit\n(\\fBe\\fR) Takes a list of messages and points the text editor at each one in\nturn.  On return from the editor, the message is read back in.\n.TP\n.B exit\n(\\fBex\\fR or \\fBx\\fR) Effects an immediate return to the Shell without\nmodifying the user's system mailbox, his\n.I mbox\nfile, or his edit file in\n.BR \\-f .\n.TP\n.B file\n(\\fBfi\\fR)\nThe same as\n.BR folder .\n.TP\n.B folders\nList the names of the folders in your folder directory.\n.TP\n.B folder\n(\\fBfo\\fR)\nThe\n.B folder\ncommand switches to a new mail file or folder. With no\narguments, it tells you which file you are currently reading.\nIf you give it an argument, it will write out changes (such\nas deletions) you have made in the current file and read in\nthe new file. Some special conventions are recognized for\nthe name. # means the previous file, % means your system\nmailbox, %user means user's system mailbox, & means\nyour \\~/mbox file, and +folder means a file in your folder\ndirectory.\n.TP\n.B from\n(\\fBf\\fR) Takes a list of messages and prints their message headers.\n.TP\n.B headers\n(\\fBh\\fR) Lists the current range of headers, which is an 18 message group.  If\na ``+'' argument is given, then the next 18 message group is printed, and if\na ``\\-'' argument is given, the previous 18 message group is printed.\n.TP\n.B help\nA synonym for ?\n.TP\n.B hold\n(\\fBho\\fR, also \\fBpreserve\\fR) Takes a message list and marks each\nmessage therein to be saved in the\nuser's system mailbox instead of in\n.IR mbox .\nDoes not override the\n.B delete\ncommand.\n.TP\n.B ignore\n.B N.B.:\n.I Ignore\nhas been superseded by\n.I retain.\n.br\nAdd the list of header fields named to the\n.IR \"ignored list\" .\nHeader fields in the ignore list are not printed\non your terminal when you print a message. This\ncommand is very handy for suppression of certain machine-generated\nheader fields. The\n.B Type\nand\n.B Print\ncommands can be used to print a message in its entirety, including\nignored fields. If\n.B ignore\nis executed with no arguments, it lists the current set of\nignored fields.\n.TP\n.B mail\n(\\fBm\\fR) Takes as argument login names and distribution group names and sends\nmail to those people.\n.TP\n.B mbox\nIndicate that a list of messages be sent to\n.I mbox\nin your home directory when you quit. This is the default\naction for messages if you do\n.I not\nhave the\n.I hold\noption set.\n.TP\n.B next\n(\\fBn\\fR like \\fB+\\fR or CR) Goes to the next message in sequence and types it.\nWith an argument list, types the next matching message.\n.TP\n.B preserve\n(\\fBpre\\fR)\nA synonym for\n.BR hold .\n.TP\n.B print\n(\\fBp\\fR)\nTakes a message list and types out each message on the user's terminal.\n.TP\n.B quit\n(\\fBq\\fR) Terminates the session, saving all undeleted, unsaved messages in\nthe user's\n.I mbox\nfile in his login directory, preserving all messages marked with\n.B hold\nor\n.B preserve\nor never referenced\nin his system mailbox, and removing all other messages from his system\nmailbox.  If new mail has arrived during the session, the message\n``You have new mail'' is given.  If given while editing a\nmailbox file with the\n.B \\-f\nflag, then the edit file is rewritten.  A return to the Shell is\neffected, unless the rewrite of edit file fails, in which case the user\ncan escape with the\n.B exit\ncommand.\n.TP\n.B reply\n(\\fBr\\fR)\nTakes a message list and sends mail to the sender and all\nrecipients of the specified message.\nThe default message must not be deleted.\n.TP\n.B respond\nA synonym for\n.BR reply .\n.TP\n.B retain\nAdd the list of header fields named to the\n.IR \"retained list\" .\nOnly the header fields in the retain list\nare shown on your terminal when you print a message.\nAll other header fields are suppressed.\nThe\n.B Type\nand\n.B Print\ncommands can be used to print a message in its entirety.\nIf\n.B retain\nis executed with no arguments, it lists the current set of\nretained fields.\n.TP\n.B save\n(\\fBs\\fR) Takes a message list and a filename and appends each message in\nturn to the end of the file.  The filename in quotes, followed by the line\ncount and character count is echoed on the user's terminal.  \n.TP\n.B set\n(\\fBse\\fR) With no arguments, prints all variable values.  Otherwise, sets\noption.  Arguments are of the form\n``option=value''\n(no space before or after =) or\n``option.''\n.TP\n.B shell\n(\\fBsh\\fR) Invokes an interactive version of the shell.\n.TP\n.B size\nTakes a message list and prints out the size in characters of each\nmessage.\n.TP\n.B source\n(\\fBso\\fR)\nThe\n.B source\ncommand reads\n.I mail\ncommands from a file.\n.TP\n.B top\nTakes a message list and prints the top few lines of each.  The number of\nlines printed is controlled by the variable\n.B toplines\nand defaults to five.\n.TP\n.B type\n(\\fBt\\fR) A synonym for\n.BR print .\n.TP\n.B unalias\nTakes a list of names defined by\n.B alias\ncommands and discards the remembered groups of users.  The group names\nno longer have any significance.\n.TP\n.B undelete\n(\\fBu\\fR) Takes a message list and marks each message as\n.I not\nbeing deleted.\n.TP\n.B unread\n(\\fBU\\fR) Takes a message list and marks each message as\n.I not\nhaving been read.\n.TP\n.B unset\nTakes a list of option names and discards their remembered values;\nthe inverse of\n.BR set .\n.TP\n.B visual\n(\\fBv\\fR) Takes a message list and invokes the display editor on each message.\n.TP\n.B write\n(\\fBw\\fR) Similar to\n.BR save ,\nexcept that\n.I only\nthe message body (\\fIwithout\\fP the header) is saved.\nExtremely useful for such tasks as sending and receiving source\nprogram text over the message system.\n.TP\n.B xit\n(\\fBx\\fR) A synonym for\n.BR exit .\n.TP\n.B z\n.I Mail\npresents message headers in windowfuls as described under the\n.B headers\ncommand. You can move\n.IR mail 's\nattention forward to the next window with the\n.B z\ncommand. Also, you can move to the previous window by using\n.BR z\\- .\n.PP\nHere is a summary of the tilde escapes,\nwhich are used when composing messages to perform\nspecial functions.  Tilde escapes are only recognized at the beginning\nof lines.  The name\n``tilde\\ escape''\nis somewhat of a misnomer since the actual escape character can be set\nby the option\n.B escape.\n.TP 12n\n.BR ~! command\nExecute the indicated shell command, then return to the message.\n.TP\n\\fB~b\\fR name ...\nAdd the given names to the list of carbon copy recipients but do not make\nthe names visible in the Cc: line (\"blind\" carbon copy).\n.TP\n\\fB~c\\fR name ...\nAdd the given names to the list of carbon copy recipients.\n.TP\n.B ~d\nRead the file ``dead.letter'' from your home directory into the message.\n.TP\n.B ~e\nInvoke the text editor on the message collected so far.  After the\nediting session is finished, you may continue appending text to the\nmessage.\n.TP\n\\fB~f\\fR messages\nRead the named messages into the message being sent.\nIf no messages are specified, read in the current message.\n.TP\n.B ~h\nEdit the message header fields by typing each one in turn and allowing\nthe user to append text to the end or modify the field by using the\ncurrent terminal erase and kill characters.\n.TP\n\\fB~m\\fR messages\nRead the named messages into the message being sent, shifted right one\ntab.  If no messages are specified, read the current message.\n.TP\n.B ~p\nPrint out the message collected so far, prefaced by the message header\nfields.\n.TP\n.B ~q\nAbort the message being sent, copying the message to\n``dead.letter''\nin your home directory if\n.B save\nis set.\n.TP\n\\fB~r\\fR filename\nRead the named file into the message.\n.TP\n\\fB~s\\fR string\nCause the named string to become the current subject field.\n.TP\n\\fB~t\\fR name ...\nAdd the given names to the direct recipient list.\n.TP\n.B ~v\nInvoke an alternate editor (defined by the VISUAL option) on the\nmessage collected so far.  Usually, the alternate editor will be a\nscreen editor.  After you quit the editor, you may resume appending\ntext to the end of your message.\n.TP\n\\fB~w\\fR filename\nWrite the message onto the named file.\n.TP\n\\fB~\\||\\|\\fRcommand\nPipe the message through the command as a filter.  If the command gives\nno output or terminates abnormally, retain the original text of the\nmessage.  The command\n.IR fmt (1)\nis often used as\n.I command\nto rejustify the message.\n.TP\n.BR ~~ string\nInsert the string of text in the message prefaced by a single ~.  If\nyou have changed the escape character, then you should double\nthat character in order to send it.\n.PP\nOptions are controlled via the\n.B set\nand\n.B unset\ncommands.  Options may be either binary, in which case it is only\nsignificant to see whether they are set or not; or string, in which\ncase the actual value is of interest.\nThe binary options include the following:\n.TP 15n\n.B append\nCauses messages saved in\n.I mbox\nto be appended to the end rather than prepended.\n(This is set in /etc/Mail.rc\non 2.11BSD systems.)\n.TP\n.B ask\nCauses\n.I mail\nto prompt you for the subject of each message you send.  If\nyou respond with simply a newline, no subject field will be sent.\n.TP\n.B askcc\nCauses you to be prompted for additional carbon copy recipients at the\nend of each message.  Responding with a newline indicates your\nsatisfaction with the current list.\n.TP\n.B autoprint\nCauses the\n.B delete\ncommand to behave like\n.B dp\n\\- thus, after deleting a message, the next one will be typed\nautomatically.\n.TP\n.B debug\nSetting the binary option\n.I debug\nis the same as specifying\n.B \\-d\non the command line and causes\n.I mail\nto output all sorts of information useful for debugging\n.IR mail .\n.TP\n.B dot\nThe binary option\n.I dot\ncauses\n.I mail\nto interpret a period alone on a line as the terminator\nof a message you are sending.\n.TP\n.B hold\nThis option is used to hold messages in the system mailbox\nby default.\n.TP\n.B ignore\nCauses interrupt signals from your terminal to be ignored and echoed as\n@'s.\n.TP\n.B ignoreeof\nAn option related to\n.I dot\nis\n.I ignoreeof\nwhich makes\n.I mail\nrefuse to accept a control-d as the end of a message.\n.I Ignoreeof\nalso applies to\n.I mail\ncommand mode.\n.TP\n.B metoo\nUsually, when a group is expanded that contains the sender, the sender\nis removed from the expansion.  Setting this option causes the sender\nto be included in the group.\n.TP\n.B nosave\nNormally, when you abort a message with two \\s-2RUBOUT\\s0,\n.I mail\ncopies the partial letter to the file ``dead.letter''\nin your home directory. Setting the binary option\n.I nosave\nprevents this.\n.TP\n.B Replyall\nReverses the sense of\n.I reply\nand\n.I Reply\ncommands.\n.TP\n.B quiet\nSuppresses the printing of the version when first invoked.\n.TP\n.B verbose\nSetting the option\n.I verbose\nis the same as using the\n.B \\-v\nflag on the command line. When mail runs in verbose mode,\nthe actual delivery of messages is displayed on he users\nterminal.\n.PP\nThe following options have string values:\n.TP 15n\nEDITOR\nPathname of the text editor to use in the\n.B edit\ncommand and ~e escape.  If not defined, then a default editor is used.\n.TP\nPAGER\nPathname of the program to use in the\n.B more\ncommand or when\n.I crt\nvariable is set.  A default paginator is used if this option is\nnot defined.\n.TP\nSHELL\nPathname of the shell to use in the\n.B !\ncommand and the ~! escape.  A default shell is used if this option is\nnot defined.\n.TP\nVISUAL\nPathname of the text editor to use in the\n.B visual\ncommand and ~v escape.\n.TP\n.B crt\nThe valued option\n.I crt\nis used as a threshold to determine how long a message must\nbe before\n.B PAGER\nis used to read it.\n.TP\n.B escape\nIf defined, the first character of this option gives the character to\nuse in the place of ~ to denote escapes.\n.TP\n.B folder\nThe name of the directory to use for storing folders of\nmessages. If this name begins with a `/',\n.I mail\nconsiders it to be an absolute pathname; otherwise, the\nfolder directory is found relative to your home directory.\n.TP\n.B record\nIf defined, gives the pathname of the file used to record all outgoing\nmail.  If not defined, then outgoing mail is not so saved.\n.TP\n.B toplines\nIf defined, gives the number of lines of a message to be printed out\nwith the\n.B top\ncommand; normally, the first five lines are printed.\n.SH FILES\n.if n .ta 2.5i\n.if t .ta 1.8i\n/usr/spool/mail/*\tpost office\n.br\n~/mbox\tyour old mail\n.br\n~/.mailrc\tfile giving initial mail commands\n.br\n/tmp/R#\ttemporary for editor escape\n.br\n/usr/share/misc/Mail.help*\thelp files\n.br\n/etc/Mail.rc\tsystem initialization file\n.br\nMessage*\ttemporary for editing messages\n.SH \"SEE ALSO\"\nbinmail(1), fmt(1), newaliases(1), aliases(5),\n.br\nmailaddr(7), sendmail(8)\n.br\n`The Mail Reference Manual'\n.SH BUGS\nThere are many flags that are not documented here. Most are\nnot useful to the general user.\n.br\nUsually,\n.I mail\nis just a link to\n.IR Mail ,\nwhich can be confusing.\n.SH AUTHOR\nKurt Shoens\n"
  },
  {
    "path": "share/man/man1/make.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)make.1\t6.4 (Berkeley) 8/15/87\n.\\\"\n.TH MAKE 1 \"August 15, 1987\"\n.UC 4\n.SH NAME\nmake \\- maintain program groups\n.SH SYNOPSIS\n.B make\n[\n.B \\-f\nmakefile ] [ option ] ...\nfile ...\n.SH DESCRIPTION\n.I Make\nexecutes commands in\n.I makefile\nto update\none or more target\n.IR names .\n.I Name\nis typically a program.\nIf no\n.B \\-f\noption is present, `makefile' and `Makefile' are\ntried in order.\nIf\n.I makefile\nis `\\-', the standard input is taken.\nMore than one\n.B \\-f\noption may appear.\n.PP\n.I Make\nupdates a target if it depends on prerequisite files\nthat have been modified since the target was last modified,\nor if the target does not exist.\n.PP\n.I Makefile\ncontains a sequence of entries that specify dependencies.\nThe first line of an entry is a\nblank-separated list of targets, then a colon,\nthen a list of prerequisite files.\nText following a semicolon, and all following lines\nthat begin with a tab, are shell commands\nto be executed to update the target.\nIf a name appears on the left of more than one `colon' line, then it depends\non all of the names on the right of the colon on those lines, but only\none command sequence may be specified for it.\nIf a name appears on a line with a double colon\n.B \"::\"\nthen the command sequence following that line is performed\nonly if the name is out of date with respect to the names to the right\nof the double colon, and is not affected by other double colon lines\non which that name may appear.\n.PP\nThe special form of the name:\n.IR a ( b )\nmeans the file named\n.I b\nstored in the archive named\n.I a.\n.PP\nSharp and newline surround comments.\n.PP\nThe following makefile says that `pgm' depends on two\nfiles `a.o' and `b.o', and that they in turn depend on\n`.c' files and a common file `incl'.\n.RS \n.HP\n.PD 0\n.nf\npgm: a.o b.o\ncc a.o b.o \\-lm \\-o pgm\n.HP\na.o: incl a.c\ncc \\-c a.c\n.HP\nb.o: incl b.c\ncc \\-c b.c\n.fi\n.RE\n.PD\n.PP\n.I Makefile\nentries of the form\n.PP\n.IP\nstring1 = string2\n.PP\nare macro definitions.\nSubsequent appearances of \n.RI $( string1 )\nor\n.RI ${ string1 }\nare replaced by\n.IR string2 .\nIf\n.I string1\nis a single character, the parentheses or braces\nare optional.\n.PP\nAll environment variables are assumed to be macro definitions and processed\nas such.  The environment variables are processed before any\n.I makefile\nmacro definitions; thus, macro assignments in a makefile override\nenvironmental variables.  The\n.B \\-e\noption causes the environment to override the macro assignments in a\nmakefile.  Finally, command line options of the form\n.I string1=string2\noverride both environment and makefile macro definitions.\n.PP\n.I Make \ninfers prerequisites for files for which\n.I makefile\ngives no construction commands.\nFor example, a\n`.c' file may be inferred as prerequisite for a `.o' file\nand be compiled to produce the `.o' file.\nThus the preceding example can be done more briefly:\n.RS\n.HP\n.PD 0\n.nf\npgm: a.o b.o\ncc a.o b.o \\-lm \\-o pgm\n.HP\na.o b.o: incl\n.fi\n.RE\n.PD\n.PP\nPrerequisites are inferred according to selected suffixes\nlisted as the `prerequisites' for the special name `.SUFFIXES';\nmultiple lists accumulate;\nan empty list clears what came before.\nOrder is significant; the first possible name for which both\na file and a rule as described in the next paragraph exist\nis inferred.\nThe default list is\n.IP\n\\&.SUFFIXES: .out .o .c .e .r .f .y .l .s .p\n.PP\nThe rule to create a file with suffix\n.I s2\nthat depends on a similarly named file with suffix\n.I s1\nis specified as an entry\nfor the `target'\n.IR s1s2 .\nIn such an entry, the special macro $* stands for\nthe target name with suffix deleted, $@ for the full target name,\n$< for the complete list of prerequisites,\nand\n$? for the list of prerequisites that are out of date.\nFor example, a rule for making\noptimized `.o' files from `.c' files is\n.IP\n\\&.c.o: ; cc \\-c \\-O \\-o $@ $*.c\n.PP\nCertain macros are used by the default inference rules\nto communicate optional arguments to\nany resulting compilations.\nIn particular,\n`CFLAGS' is used for\n.IR cc (1)\noptions,\n`FFLAGS' for\n.IR f77 (1)\noptions,\n`PFLAGS' for\n.IR pc (1)\noptions,\nand `LFLAGS' and `YFLAGS' for \n.I lex\nand\n.IR yacc (1)\noptions.  In addition, the macro `MFLAGS' is filled in\nwith the initial command line options supplied to \n.IR make .\nThis simplifies maintaining a hierarchy of makefiles as\none may then invoke \n.I make\non makefiles in subdirectories and pass along useful options\nsuch as\n.BR \\-k .\n.PP\nAnother special macro is `VPATH'.\nThe `VPATH' macro should be set to a list of directories separated by colons.\nWhen\n.I make\nsearches for a file as a result of a dependency relation, it will\nfirst search the current directory and then each of the directories on the\n`VPATH' list.\nIf the file is found, the actual path to the file will be used, rather than\njust the filename.\nIf `VPATH' is not defined, then only the current directory is searched.\n.PP\nOne use for `VPATH' is when one has several programs that compile from the\nsame source.\nThe source can be kept in one directory and each set of\nobject files (along with a separate\n.IR makefile )\nwould be in a separate subdirectory.\nThe `VPATH' macro would point to the source directory in this case.\n.PP\nCommand lines are executed one at a time, each by its\nown shell.\nA line is printed when it is executed unless\nthe special target `.SILENT'\nis in \n.I makefile,\nor the first character of the command is `@'.\n.PP\nCommands returning nonzero status (see\n.IR intro (1))\ncause\n.I make\nto terminate unless\nthe special target `.IGNORE' is in\n.I makefile\nor the command begins with\n<tab><hyphen>.\n.PP\nInterrupt and quit cause the target to be deleted\nunless the target is a directory or\ndepends on the special name `.PRECIOUS'.\n.PP\nOther options:\n.TP\n.B \\-e\nEnvironmental variables override assignments within makefiles.\n.TP\n.B \\-i\nEquivalent to the special entry `.IGNORE:'.\n.TP\n.B \\-k\nWhen a command returns nonzero status,\nabandon work on the current entry, but\ncontinue on branches that do not depend on the current entry.\n.TP\n.B \\-n\nTrace and print, but do not execute the commands\nneeded to update the targets.\n.TP\n.B \\-t\nTouch, i.e. update the modified date of targets, without\nexecuting any commands.\n.TP\n.B \\-r\nEquivalent to an initial special entry `.SUFFIXES:'\nwith no list.\n.TP \n.B \\-s\nEquivalent to the special entry\n`.SILENT:'.\n.SH FILES\nmakefile, Makefile\n.br\n.SH \"SEE ALSO\"\nsh(1), touch(1), f77(1), pc(1), getenv(3)\n.br\nS. I. Feldman\n.I\nMake \\- A Program for Maintaining Computer Programs\n.SH BUGS\nSome commands return nonzero status inappropriately.\nUse\n.B \\-i\nto overcome the difficulty.\n.br\nCommands that are directly executed by the shell,\nnotably\n.IR  cd (1),\nare ineffectual across newlines in\n.I make.\n.PP\n`VPATH' is intended to act like the System V `VPATH' support,\nbut there is no guarantee that it functions identically.\n"
  },
  {
    "path": "share/man/man1/man.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)man.1\t6.7 (Berkeley) 4/19/88\n.\\\"\n.TH MAN 1 \"April 19, 1988\"\n.UC 4\n.SH NAME\nman \\- print out the manual\n.SH SYNOPSIS\n.br\n.B man\n[\n.B \\-\n] [\n.B -a\n] [\n.B \\-M\n.I path\n] [\nsection\n]\ntitle ...\n.SH DESCRIPTION\n\\fIMan\\fP is the program which provides on-line access to the UNIX manual.\nIf a \\fIsection\\fP specifier is given, \\fIman\\fP looks in that section of\nthe manual for the given \\fItitle\\fP(s).  \\fISection\\fP is either an Arabic\nsection number (``3'' for example), or one of the words ``local'', ``new,''\nor ``old''.  (The abbreviations ``l'', ``n'', and ``o'' are also allowed.)\nIf \\fIsection\\fP is omitted, \\fIman\\fP searches all sections of the manual,\ngiving preference to commands over library subroutines, and displays the\nfirst manual page it finds, if any.  If the \\fI-a\\fP option is supplied,\n\\fIman\\fP displays all applicable manual pages.\n.PP\nNormally \\fIman\\fP checks in standard locations (/usr/man and /usr/local/man)\nfor manual information.  This can be changed by supplying a search path (a\nla the Bourne shell) with the \\fB-M\\fP flag.  The search path is a colon\n(``:'') separated list of directories in which \\fIman\\fP expects to find\nthe standard manual subdirectories.  This search path can also be set with\nthe environmental variable \\fIMANPATH\\fP.\n.PP\nSince some manual pages are intended for use only on certain machines,\n\\fIman\\fP only searches those directories applicable to the current\nmachine.  \\fIMan\\fP's determination of the current machine type can\nbe overridden by setting the environmental variable \\fIMACHINE\\fP.\n.PP\nIf the standard output is a teletype, and the \\fB-\\fP flag is not provided,\n\\fIman\\fP uses \\fImore\\fP(1), or the pager provided by the environmental\nvariable \\fIPAGER\\fP, to display the manual page.\n.PP\nThe FORTRAN version of section 3 of the manual may be specified by supplying\n\\fIman\\fP with the \\fIsection\\fP ``3f''.  Also, a specific section of the\nlocal manual may be specified by appending a number to the \\fIsection\\fP,\ni.e. ``l5'' would indicate section 5 of the local manual.\n.SH FILES\n.nf\n.ta \\w'/usr/local/man/man?/*   'u\n/usr/man\tstandard manual area\n/usr/man/cat?/*\tdirectories containing standard manual pages\n/usr/local/man/cat?/*\tdirectories containing local manual pages\n/usr/src/man\tdirectories containing unformatted manual pages\n.fi\n.SH SEE\\ ALSO\napropos(1), more(1), whatis(1), whereis(1)\n.SH BUGS\nThe manual is supposed to be reproducible either on the\nphototypesetter or on a typewriter, however, on a typewriter,\nsome information is necessarily lost.\n"
  },
  {
    "path": "share/man/man1/mesg.1",
    "content": ".\\\"\t@(#)mesg.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH MESG 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nmesg \\- permit or deny messages\n.SH SYNOPSIS\n.B mesg\n[\n.B n\n] [\n.B y\n]\n.SH DESCRIPTION\n.I Mesg\nwith argument\n.B n\nforbids messages via\n.I  write\nand\n.IR talk (1)\nby revoking non-user\nwrite permission on the user's terminal.\n.I Mesg\nwith argument\n.B y\nreinstates permission.\nAll by itself,\n.I mesg\nreports the current state without changing it.\n.SH FILES\n/dev/tty*\n.SH \"SEE ALSO\"\nwrite(1), talk(1)\n.SH DIAGNOSTICS\nExit status is 0 if messages are receivable,\n1 if not, 2 on error.\n"
  },
  {
    "path": "share/man/man1/mkdep.1",
    "content": ".\\\" Copyright (c) 1987 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)mkdep.1\t1.3 (Berkeley) 6/4/87\n.\\\"\n.TH MKDEP 1 \"June 4, 1987\"\n.UC 5\n.SH NAME\nmkdep \\- construct Makefile dependency list\n.SH SYNOPSIS\n.B mkdep\n[\n.B \\-f makefile\n] [\n.B \\-p\n]\nflags file ...\n.SH DESCRIPTION\n\\fIMkdep\\fP takes a set of flags for the C compiler and a list of C\nsource files as arguments and constructs a set of include file dependencies.\nIt attaches this dependency list to the end of the file ``Makefile''.\nAn example of its use in a makefile might be:\n.nf\n.RS\n\nCFLAGS= -O -I../include -I.\nSRCS= file1.c file2.c\n\ndepend:\n\tmkdep ${CFLAGS} ${SRCS}\n.RE\n.PP\nwhere the macro SRCS is the list of C source files and the macro\nCFLAGS is the list of flags for the C compiler.  The \\fB-f\\fP option\nprovides \\fImkdep\\fP with a name other than ``Makefile'' to be edited.\nIf the \\fB-p\\fP option is provided, \\fImkdep\\fP produces dependencies\nof the form ``program: program.c'' so that subsequent makes will\nproduce \\fIprogram\\fP directly from its C module rather than using an\nintermediate \\fI.o\\fP module.  This is useful in directories that\ncontain many programs, each of whose source is contained in a single\nC module.\n.SH \"SEE ALSO\"\ncc(1), make(1)\n"
  },
  {
    "path": "share/man/man1/mkdir.1",
    "content": ".\\\" Copyright (c) 1989, 1990 The Regents of the University of California.\n.\\\" All rights reserved.\n.\\\"\n.\\\" This code is derived from software contributed to Berkeley by\n.\\\" the Institute of Electrical and Electronics Engineers, Inc.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"\t@(#)mkdir.1\t6.10 (Berkeley) 7/27/91\n.\\\"\n.TH MKDIR 1 \"August 16, 1993\"\n.UC 2\n.SH NAME\nmkdir \\- make directories\n.SH SYNOPSIS\nmkdir [ \\-p \\fBdirectory_name\\fP ... ]\n.SH DESCRIPTION\nMkdir\ncreates the directories named as operands, in the order specified,\nusing mode \\&0777 modified by the current umask(2).\n.PP\nThe options are as follows:\n.TP\n\\-p\nCreate intermediate directories as required.  If this option is not\nspecified, the full path prefix of each operand must already exist.\n.TP\nThe user must have write permission in the parent directory.\n.PP\nMkdir\nexits 0 if successful, and >0 if an error occurred.\n.SH SEE ALSO\nrmdir(1)\n.SH STANDARDS\nMkdir is POSIX 1003.2 compliant.\nThis manual page is derived from the POSIX 1003.2 manual page.\n"
  },
  {
    "path": "share/man/man1/mkstr.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)mkstr.1\t6.2.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH MKSTR 1 \"October 22, 1996\"\n.UC\n.SH NAME\nmkstr \\- create an error message file by massaging C source\n.SH SYNOPSIS\n.B mkstr\n[\n.B \\-\n]\nmessagefile prefix file ...\n.SH DESCRIPTION\n.I Mkstr\nis used to create files of error messages.\nIts use can make programs with large numbers of error diagnostics much\nsmaller, and reduce system overhead in running the program as the\nerror messages do not have to be constantly swapped in and out.\n.PP\n.I Mkstr\nwill process each of the specified\n.I files,\nplacing a massaged version of the input file in a file whose name\nconsists of the specified\n.I prefix \nand the original name.\nA typical usage of\n.I mkstr\nwould be\n.DT\n.PP\n\tmkstr pistrings xx *.c\n.PP\nThis command would cause all the error messages from the C source\nfiles in the current directory to be placed in the file\n.I pistrings\nand processed copies of the source for these files to be placed in\nfiles whose names are prefixed with\n.I xx.\n.PP\nTo process the error messages in the source to the message file\n.I mkstr\nkeys on the string\n\\%`error(\"'\nin the input stream.\nEach time it occurs, the C string starting at the `\"' is placed\nin the message file followed by a null character and a new-line character;\nthe null character terminates the message so it can be easily used\nwhen retrieved, the new-line character makes it possible to sensibly\n.I cat\nthe error message file to see its contents.\nThe massaged copy of the input file then contains a\n.I lseek\npointer into the file which can be used to retrieve the message, i.e.:\n.IP\n.DT\n.nf\n\\fBchar\\fR\tefilname[] =  \"/usr/share/pascal/pi_strings\";\n\\fBint\\fR\tefil = -1;\n.sp\nerror(a1, a2, a3, a4)\n{\n\t\\fBchar\\fR buf[256];\n\n\t\\fBif\\fR (efil < 0) {\n\t\tefil = open(efilname, 0);\n\t\t\\fBif\\fR (efil < 0) {\noops:\n\t\t\tperror(efilname);\n\t\t\texit(1);\n\t\t}\n\t}\n\t\\fBif\\fR (lseek(efil, (long) a1, 0) |\\|| read(efil, buf, 256) <= 0)\n\t\t\\fBgoto\\fR oops;\n\tprintf(buf, a2, a3, a4);\n}\n.fi\n.PP\nThe optional\n.B \\-\ncauses the error messages to be placed at the end of the specified\nmessage file for recompiling part of a large\n.IR mkstr \\|ed\nprogram.\n.SH SEE\\ ALSO\nlseek(2), xstr(1)\n"
  },
  {
    "path": "share/man/man1/more.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)more.1\t6.4.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH MORE 1 \"October 22, 1996\"\n.UC 4\n.SH NAME\nmore, page \\- file perusal filter for crt viewing\n.SH SYNOPSIS\n.B more\n[\n.B \\-cdflsu\n]\n[\n.B \\-\\fIn\\fP\n]\n[\n.B +\\fIlinenumber\\fP \n]\n[\n.B +/\\fIpattern\\fP\n] [ name ...  ]\n.LP\n.B page\n.I \"more options\"\n.SH DESCRIPTION\n.I  More\nis a filter which allows examination of a continuous text\none screenful at a time on a soft-copy terminal.\nIt normally pauses after each screenful, printing --More--\nat the bottom of the screen.\nIf the user then types a carriage return, one more line is displayed.\nIf the user hits a space,\nanother screenful is displayed.  Other possibilities are enumerated later.\n.PP\nThe command line options are:\n.TP\n.I \\-n\nAn integer which is the size (in lines) of the window which\n.I more\nwill use instead of the default.\n.TP\n.B \\-c\n.I More\nwill draw each page by beginning at the top of the screen and erasing \neach line just before it draws on it.\nThis avoids scrolling the screen, making it easier to read while \n.I more \nis writing.\nThis option will be ignored if the terminal does not have the ability\nto clear to the end of a line.\n.TP\n.B \\-d\n.I More\nwill prompt the user with the message \"Press\nspace to continue, \\'q\\' to quit.\" at the end of each screenful,\nand will respond to subsequent illegal user input by\nprinting \"Press \\'h\\' for instructions.\" instead of ringing the bell.\nThis is useful if\n.I more\nis being used as a filter in some setting,\nsuch as a class,\nwhere many users may be unsophisticated.\n.TP\n.B \\-f\nThis causes\n.I more\nto count logical, rather than screen lines.\nThat is, long lines are not folded.\nThis option is recommended if\n.I nroff\noutput is being piped through\n.I ul,\nsince the latter may generate escape sequences.\nThese escape sequences contain characters which would ordinarily occupy\nscreen positions, but which do not print when they are sent to the\nterminal as part of an escape sequence.\nThus\n.I more\nmay think that lines are longer than they actually are, and fold\nlines erroneously.\n.TP\n.B \\-l\nDo\nnot treat ^\\&L (form feed) specially.\nIf this option is not given,\n.I more\nwill pause after any line that contains a ^\\&L, as if the end of a\nscreenful had been reached.\nAlso, if a file begins with a form feed, the screen will be cleared\nbefore the file is printed.\n.TP\n.B \\-s\nSqueeze multiple blank lines from the output, producing only one blank\nline.  Especially helpful when viewing\n.I nroff\noutput, this option maximizes the useful information present on the screen.\n.TP\n.B \\-u\nNormally,\n.I more\nwill handle underlining such as produced by\n.I nroff\nin a manner appropriate to the particular terminal:  if the terminal can\nperform underlining or has a stand-out mode,\n.I more\nwill output appropriate escape sequences to enable underlining or stand-out\nmode for underlined information in the source file.  The\n.I \\-u\noption suppresses this processing.\n.TP\n.B +\\fIlinenumber\\fP\nStart up at \\fIlinenumber\\fP.\n.TP\n.B +/\\fIpattern\\fP\nStart up two lines before the line containing the\nregular expression \\fIpattern\\fP.\n.PP\nIf the program is invoked as\n.I page,\nthen the screen is cleared before each screenful is printed (but only\nif a full screenful is being printed), and\n.I k\n\\- 1 rather\nthan\n.I k\n\\- 2 lines are printed in each screenful, where\n.I k\nis the number of lines the terminal can display.\n.PP\n.I More\nlooks in the file\n.I /etc/termcap\nto determine terminal characteristics,\nand to determine the default window size.\nOn a terminal capable of displaying 24 lines,\nthe default window size is 22 lines.\n.PP\n.I More\nlooks in the environment variable\n.I MORE\nto pre-set any flags desired.  For example, if you prefer to view files using\nthe\n.I \\-c\nmode of operation, the\n.I csh\ncommand\n.I \"setenv MORE -c\"\nor the\n.I sh\ncommand sequence\n.I \"MORE='-c' ; export MORE\"\nwould cause all invocations of\n.I more ,\nincluding invocations by programs such as\n.I man\nand\n.I msgs ,\nto use this mode.\nNormally, the user will place the command sequence which sets up the\n.I MORE\nenvironment variable in the\n.I .cshrc\nor\n.I .profile\nfile.\n.PP\nIf\n.I more\nis reading from a file, rather than a pipe, then a percentage is displayed\nalong with the --More-- prompt.\nThis gives the fraction of the file (in characters, not lines) that has been\nread so far.\n.PP\nOther sequences which may be typed when\n.I more\npauses, and their effects, are as follows (\\fIi\\fP is an optional integer\nargument, defaulting to 1) :\n.PP\n.IP \\fIi\\|\\fP<space>\ndisplay\n.I i\nmore lines, (or another screenful if no argument is given)\n.PP\n.IP ^D\ndisplay 11 more lines (a ``scroll'').\nIf\n.I i\nis given, then the scroll size is set to \\fIi\\|\\fP.\n.PP\n.IP d\nsame as ^D (control-D)\n.PP\n.IP \\fIi\\|\\fPz\nsame as typing a space except that \\fIi\\|\\fP, if present, becomes the new\nwindow size.\n.PP\n.IP \\fIi\\|\\fPs\nskip \\fIi\\|\\fP lines and print a screenful of lines\n.PP\n.IP \\fIi\\|\\fPf\nskip \\fIi\\fP screenfuls and print a screenful of lines\n.PP\n.IP \\fIi\\|\\fPb\nskip back \\fIi\\fP screenfuls and print a screenful of lines\n.PP\n.IP \\fIi\\|\\fP^B\nsame as b\n.PP\n.IP \"q or Q\"\nExit from\n.I more.\n.PP \n.IP =\nDisplay the current line number.\n.PP\n.IP v\nStart up the editor\n.I vi\nat the current line.\n.PP\n.IP h\nHelp command; give a description of all the\n.I more\ncommands.\n.PP\n.IP \\fIi\\|\\fP/expr\nsearch for the \\fIi\\|\\fP-th occurrence of the regular expression \\fIexpr.\\fP\nIf there are less than \\fIi\\fP occurrences of \\fIexpr\\|\\fP,\nand the input is a file (rather than a pipe),\nthen the position in the file remains unchanged.\nOtherwise, a screenful is displayed, starting two lines before the place\nwhere the expression was found.\nThe user's erase and kill characters may be used to edit the regular\nexpression.\nErasing back past the first column cancels the search command.\n.PP\n.IP \\fIi\\|\\fPn\nsearch for the \\fIi\\|\\fP-th occurrence of the last regular expression entered.\n.PP\n.IP \\'\n(single quote) Go to the point from which the last search started.\nIf no search has been performed in the current file, this command\ngoes back to the beginning of the file.\n.PP\n.IP !command\ninvoke a shell with \\fIcommand\\|\\fP. \nThe characters `%' and `!' in \"command\" are replaced with the\ncurrent file name and the previous shell command respectively.\nIf there is no current file name, `%' is not expanded.\nThe sequences \"\\\\%\" and \"\\\\!\" are replaced by \"%\" and \"!\" respectively.\n.PP\n.IP \\fIi\\|\\fP:n\nskip to the \\fIi\\|\\fP-th next file given in the command line\n(skips to last file if n doesn't make sense)\n.PP\n.IP \\fIi\\|\\fP:p\nskip to the \\fIi\\|\\fP-th previous file given in the command line.\nIf this command is given in the middle of printing out a\nfile, then\n.I more\ngoes back to the beginning of the file. If \\fIi\\fP doesn't make sense,\n.I more\nskips back to the first file.\nIf\n.I more\nis not reading from a file, the bell is rung and nothing else happens.\n.PP\n.IP :f\ndisplay the current file name and line number.\n.PP\n.IP \":q or :Q\"\nexit from \n.I more\n(same as q or Q).\n.PP\n.IP .\n(dot) repeat the previous command.\n.PP\nThe commands take effect immediately, i.e., it is not necessary to\ntype a carriage return.\nUp to the time when the command character itself is given,\nthe user may hit the line kill character to cancel the numerical\nargument being formed.\nIn addition, the user may hit the erase character to redisplay the\n--More--(xx%) message.\n.PP\nAt any time when output is being sent to the terminal, the user can\nhit the quit key (normally control\\-\\\\).\n.I More\nwill stop sending output, and will display the usual --More--\nprompt.\nThe user may then enter one of the above commands in the normal manner.\nUnfortunately, some output is lost when this is done, due to the\nfact that any characters waiting in the terminal's output queue\nare flushed when the quit signal occurs.\n.PP\nThe terminal is set to\n.I noecho\nmode by this program so that the output can be continuous.\nWhat you type will thus not show on your terminal, except for the / and !\ncommands.\n.PP\nIf the standard output is not a teletype, then\n.I more\nacts just like\n.I cat,\nexcept that a header is printed before each file (if there is\nmore than one).\n.PP\n.DT\nA sample usage of\n.I more\nin previewing\n.I nroff\noutput would be\n.PP\n\tnroff \\-ms +2 doc.n | more -s\n.SH FILES\n.DT\n/etc/termcap\t\tTerminal data base\n.br\n/usr/share/misc/more.help\tHelp file\n.SH \"SEE ALSO\"\ncsh(1), man(1), msgs(1), script(1), sh(1), environ(7)\n.SH BUGS\nSkipping backwards is too slow on large files.\n"
  },
  {
    "path": "share/man/man1/mset.1",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)mset.1\t1.3.1 (2.11BSD) 1996/11/16\n.\\\"\n.TH MSET 1 \"November 16, 1996\"\n.UC 6\n.SH NAME\nmset \\- retrieve ASCII to IBM 3270 keyboard map\n.SH SYNOPSIS\n.B mset\n.SH DESCRIPTION\n.I Mset\nretrieves mapping information\nfor the ASCII keyboard to IBM 3270 terminal\nspecial functions.\nNormally, these mappings are found\nin\n.I /usr/share/misc/map3270\n(see\n.IR map3270 (5)).\nThis information is used by the\n.I tn3270\ncommand (see\n.IR tn3270 (1)).\n.PP\n.I Mset\ncan be used store the mapping information in the process environment\nin order to avoid scanning\n.I /usr/share/misc/map3270\neach time\n.I tn3270\nis invoked.\nTo do this, place the following command in your\n.I .login\nfile:\n.ti 5n\n.sp\n     set noglob; setenv \\s-1MAP3270\\s0 \"\\(gamset\\(ga\"; unset noglob\n.PP\n.I Mset\nfirst determines the user's terminal type from the environment variable\n.BR TERM .\nNormally\n.I mset\nthen uses the file\n.I /usr/share/misc/map3270\nto find the keyboard mapping for that terminal.\nHowever, if the environment variable\n.B MAP3270\nexists and contains the entry for the specified terminal, then that\ndefinition is used.\nIf the value of\n.B MAP3270\nbegins with a slash (`/') then it is assumed to be the full pathname\nof an alternate mapping file and that file is searched first.\nIn any case, if the mapping for the terminal is not found in\nthe environment, nor in an alternate map file, nor in the standard map file,\nthen the same search is performed for an entry for a terminal type of\n.B unknown.\nIf that search also fails,\nthen a default mapping\nis used.\n.SH FILES\n/usr/share/misc/map3270        keyboard mapping for known terminals\n.SH SEE ALSO\ntn3270(1), map3270(5)\n.SH BUGS\nIf the entry for the specific terminal\nexceeds 1024 bytes, \\fIcsh\\fR(1) will fail\nto set the environment variable.\n.I Mset\nshould probably\ndetect this case and\noutput the path to the\n.I map3270\nfile\ninstead of the terminal entry.\n"
  },
  {
    "path": "share/man/man1/msgs.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)msgs.1\t6.3.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH MSGS 1 \"October 22, 1996\"\n.UC 4\n.SH NAME\nmsgs \\- system messages and junk mail program\n.SH SYNOPSIS\n.B msgs\n[\n.B \\-fhlpq\n] [\nnumber\n] [\n\\-number\n]\n.LP\n.B msgs\n.B \\-s\n.LP\n.B msgs\n.B \\-c\n[\n\\-days\n]\n.SH DESCRIPTION\n.I Msgs\nis used to read system messages.\nThese messages are\nsent by mailing to the login `msgs' and should be short\npieces of information which are suitable to be read once by most users\nof the system.\n.PP\n.I Msgs\nis normally invoked each time you login, by placing it in the file\n.I \\&.login\n.I (\\&.profile\nif you use\n.IR /bin/sh ).\nIt will then prompt you with the source and subject of each new message.\nIf there is no subject line, the first few non-blank lines of the\nmessage will be displayed.\nIf there is more to the message, you will be told how\nlong it is and asked whether you wish to see the rest of the message.\nThe possible responses are:\n.TP 7\n.B y\ntype the rest of the message.\n.TP 7\nRETURN\nsynonym for y.\n.TP 7\n.B n\nskip this message\nand go on to the next message.\n.TP 7\n.B \\-\nredisplay the last message.\n.TP 7\n.B q\ndrops you out of\n.I msgs;\nthe next time you run the program it will pick up where you left off.\n.TP 7\n.B s\nappend the current message to the file ``Messages'' in the current directory;\n`s\\-' will save the previously displayed message. A `s' or `s\\-' may\nbe followed by a space and a file name to receive the message replacing\nthe default ``Messages''.\n.TP 7\n.B m\nor `m\\-' causes a copy of the specified message to be placed in a temporary\nmailbox and \n.IR mail (1)\nto be invoked on that mailbox.\nBoth `m' and `s' accept a numeric argument in place of the `\\-'.\n.PP\n.I Msgs\nkeeps track of the next message you will see by a number in the file\n.I \\&.msgsrc\nin your home directory.\nIn the directory\n.I /usr/msgs\nit keeps a set of files whose names are the (sequential) numbers\nof the messages they represent.\nThe file\n.I /usr/msgs/bounds\nshows the low and high number of the messages in the directory\nso that\n.I msgs\ncan quickly determine if there are no messages for you.\nIf the contents of\n.I bounds\nis incorrect it can be fixed by removing it;\n.I msgs\nwill make a new\n.I bounds\nfile the next time it is run.\n.PP\nThe\n.B \\-s\noption is used for setting up the posting of messages.  The line\n.IP\n.DT\nmsgs: \"| /usr/ucb/msgs \\-s\"\n.PP\nshould be include in\n.I /etc/aliases\nto enable posting of messages.\n.PP\nThe\n.B \\-c\noption is used for performing cleanup on\n.I /usr/msgs.\nAn entry with the\n.B \\-c\noption should be placed in\n.I /etc/crontab\nto run every night.  This will remove all messages over 21 days old.\nA different expiration may be specified on the command line to override\nthe default.\n.PP\nOptions when reading messages include:\n.TP 7\n.B \\-f\nwhich causes it not to say ``No new messages.''.\nThis is useful in your\n.I \\&.login\nfile since this is often the case here.\n.TP 7\n.B \\-q\nQueries whether there are messages, printing\n``There are new messages.'' if there are.\nThe command ``msgs \\-q'' is often used in login scripts.\n.TP 7\n.B \\-h\ncauses\n.I msgs\nto print the first part of messages only.\n.TP 7\n.B \\-l\noption causes only locally originated messages to be reported.\n.TP 7\n\\fInum\\fR\nA message number can be given\non the command line, causing\n.I msgs\nto start at the specified message rather than at the next message\nindicated by your\n.I \\&.msgsrc\nfile.\nThus\n.IP \"\" 7\n    msgs \\-h 1\n.IP \"\" 7\nprints the first part of all messages.\n.TP 7\n.I \"\\-number\"\nwill cause\n.I msgs\nto start\n.I number\nmessages back from the one indicated by your \n.I \\&.msgsrc\nfile, useful for reviews of recent messages.\n.TP 7\n.B \\-p\ncauses long messages to be piped through\n.IR more (1).\n.PP\nWithin\n.I msgs\nyou can also go to any specific message by typing its number when\n.I msgs\nrequests input as to what to do.\n.SH FILES\n.ta 2i\n/usr/msgs/*\tdatabase\n.br\n~/.msgsrc\tnumber of next message to be presented\n.SH AUTHORS\nWilliam Joy\n.br\nDavid Wasley\n.SH SEE ALSO\naliases(5), crontab(5), mail(1), more(1)\n.SH BUGS\n"
  },
  {
    "path": "share/man/man1/mt.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)mt.1\t6.2.1 (2.11BSD) 1995/12/22\n.\\\"\n.TH MT 1 \"December 22, 1995\"\n.UC 4\n.SH NAME\nmt \\- magnetic tape manipulating program\n.SH SYNOPSIS\n.B mt\n[\n.B \\-f\n.I tapename\n]\n.I command\n[\n.I count\n]\n.SH DESCRIPTION\n.I Mt\nis used to give commands to a magnetic tape drive.\nIf a tape name is not specified, the environment variable\nTAPE is used;  if TAPE does not exist,\n.I mt\nuses the device\n.IR /dev/rmt12 .\nNote\nthat\n.I tapename\nmust reference a raw (not block) tape device.\nBy default\n.I mt\nperforms the requested operation once.  Operations\nmay be performed multiple times by specifying\n.IR count .\n.PP\nThe available commands are listed below.  Only as many\ncharacters as are required to uniquely identify a command\nneed be specified.\n.TP\n.BR eof , \" weof\"\nWrite \n.I count\nend-of-file marks at the current position on the tape.\n.TP\n.B fsf\nForward space\n.I count\nfiles.\n.TP\n.B fsr\nForward space \n.I count\nrecords.\n.TP\n.B bsf\nBack space \n.I count\nfiles.\n.TP \n.B bsr\nBack space\n.I count\nrecords.\n.TP\n.B rewind\nRewind the tape\n.RI ( Count\nis ignored). \n.TP\n.BR offline , \" rewoffl\"\nRewind the tape and place the tape unit off-line\n.RI ( Count\nis ignored).\n.TP\n.B status\nPrint status information about the tape unit.\n.TP\n.B cacheon\nEnable the readahead/writebehind cache on the tape unit.\n.TP\n.B cacheoff\nTurn off the readahead/writebehind cache on the tape unit.\n.PP\n.I Mt\nreturns a 0 exit status when the operation(s) were successful,\n1 if the command was unrecognized, and 2 if an operation failed.\n.PP\nThe \n.B cacheon\nand\n.B cacheoff\ncommands currently only apply to the TMSCP driver and then only\nfor certain drives such as the TU81+.  No error is produced by the\nTMSCP driver if the cache commands are used.  Other drivers will \nreturn an error code since they do not recognize the \n.B MTCACHE\nand\n.B MTNOCACHE\nfunctions codes.  See\n.BR mtio (4).\n.SH FILES\n.DT\n/dev/rmt*\tRaw magnetic tape interface\n.SH \"SEE ALSO\"\nmtio(4), tmscp(4), dd(1), ioctl(2), environ(7)\n"
  },
  {
    "path": "share/man/man1/mv.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)mv.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH MV 1 \"April 29, 1985\"\n.UC 4\n.SH NAME\nmv \\- move or rename files\n.SH SYNOPSIS\n.B mv\n[\n.B \\-i\n] [\n.B \\-f\n] [\n.B \\-\n] file1 file2\n.PP\n.B mv\n[\n.B \\-i\n] [\n.B \\-f\n] [\n.B \\-\n] file ... directory\n.SH DESCRIPTION\n.I Mv\nmoves (changes the name of)\n.I file1\nto\n.IR file2 .\n.PP\nIf\n.I file2\nalready exists, it is removed before\n.I file1\nis moved.  If\n.I file2\nhas a mode which forbids writing,\n.I mv\nprints the mode (see\n.IR chmod (2))\nand reads the standard input to obtain a line; if the line begins with\n.B y,\nthe move takes place; if not,\n.I mv\nexits.\n.PP\nIn the second form, one or more\n.I files\n(plain files or directories) are moved to the\n.I directory\nwith their original file-names.\n.PP\n.I Mv\nrefuses to move a file onto itself.\n.PP\nOptions:\n.TP\n.B \\-i\nstands for interactive mode. Whenever a move is to supercede an\nexisting file, the user is prompted by the name of the file\nfollowed by a question mark. If he answers with a line starting\nwith 'y', the move continues. Any other reply prevents the move from\noccurring.\n.TP\n.B \\-f\nstands for force. This option overrides any mode restrictions or the\n\\-i switch.\n.TP\n.B \\-\nmeans interpret all the following arguments to \n.I mv\nas file names.  This allows file names starting with minus.\n.SH \"SEE ALSO\"\ncp(1), ln(1)\n.SH BUGS\nIf\n.I file1\nand\n.I file2\nlie on different file systems,\n.I mv\nmust copy the file and delete the original.\nIn this case the owner name becomes that of the copying process and any\nlinking relationship with other files is lost.\n"
  },
  {
    "path": "share/man/man1/netstat.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)netstat.1\t6.5 (Berkeley) 5/8/86\n.\\\"\n.TH NETSTAT 1 \"May 8, 1986\"\n.UC 5\n.SH NAME\nnetstat \\- show network status\n.SH SYNOPSIS\n.B netstat\n[ \n.B \\-Aan\n] [\n.B \\-f\n.I address_family\n] [\n.I system\n] [\n.I core\n]\n.br\n.B netstat\n[ \n.B \\-himnrs\n] [\n.B \\-f\n.I address_family\n] [\n.I system\n] [\n.I core\n]\n.br\n.B netstat\n[ \n.B \\-n\n] [\n.B \\-I\n.I interface\n]\n.I interval\n[\n.I system\n] [\n.I core\n]\n.SH DESCRIPTION\nThe\n.I netstat \ncommand symbolically displays the contents of various network-related\ndata structures.\nThere are a number of output formats,\ndepending on the options for the information presented.\nThe first form of the command displays a list of active sockets for\neach protocol.\nThe second form presents the contents of one of the other network\ndata structures according to the option selected.\nUsing the third form, with an \n.I interval\nspecified,\n.I netstat\nwill continuously display the information regarding packet\ntraffic on the configured network interfaces.\n.PP\nThe options have the following meaning:\n.TP \n.B \\-A\nWith the default display,\nshow the address of any protocol control blocks associated with sockets; used\nfor debugging.\n.TP\n.B \\-a\nWith the default display,\nshow the state of all sockets; normally sockets used by\nserver processes are not shown.\n.TP\n.B \\-h\nShow the state of the IMP host table.\n.TP\n.B \\-i\nShow the state of interfaces which have been auto-configured\n(interfaces statically configured into a system, but not\nlocated at boot time are not shown).\n.TP\n.BI \\-I \" interface\"\nShow information only about this interface;\nused with an\n.I interval\nas described below.\n.TP\n.B \\-m\nShow statistics recorded by the memory management routines\n(the network manages a private pool of memory buffers).\n.TP\n.B \\-n\nShow network addresses as numbers (normally \n.I netstat\ninterprets addresses and attempts to display them\nsymbolically).\nThis option may be used with any of the display formats.\n.TP\n.B \\-s\nShow per-protocol statistics.\n.TP\n.B \\-r\nShow the routing tables.\nWhen\n.B \\-s\nis also present, show routing statistics instead.\n.TP\n.BI \\-f \" address_family\"\nLimit statistics or address control block reports to those\nof the specified\n.IR address\\ family .\nThe following address families\nare recognized:\n.IR inet ,\nfor\n.BR AF_INET ,\n.IR ns ,\nfor\n.BR AF_NS ,\nand\n.IR unix ,\nfor\n.BR AF_UNIX .\n.PP\nThe arguments, \n.I system\nand\n.I core\nallow substitutes for the defaults ``/vmunix'' and ``/dev/kmem''.\n.PP\nThe default display, for active sockets, shows the local\nand remote addresses, send and receive queue sizes (in bytes), protocol,\nand the internal state of the protocol.\nAddress formats are of the form ``host.port'' or ``network.port''\nif a socket's address specifies a network but no specific host address.\nWhen known the host and network addresses are displayed symbolically\naccording to the data bases\n.I /etc/hosts\nand\n.IR /etc/networks ,\nrespectively.  If a symbolic name for an address is unknown, or if\nthe \n.B \\-n\noption is specified, the address is printed numerically, according\nto the address family.\nFor more information regarding \nthe Internet ``dot format,''\nrefer to \n.IR inet (3N).\nUnspecified,\nor ``wildcard'', addresses and ports appear as ``*''.  \n.PP\nThe interface display provides a table of cumulative\nstatistics regarding packets transferred, errors, and collisions.\nThe network addresses of the interface\nand the maximum transmission unit (``mtu'') are also displayed.\n.PP\nThe routing table display indicates the available routes and\ntheir status.  Each route consists of a destination host or network\nand a gateway to use in forwarding packets.  The flags field shows\nthe state of the route (``U'' if ``up''), whether the route\nis to a gateway (``G''), and whether the route was created dynamically\nby a redirect (``D'').  Direct routes are created for each\ninterface attached to the local host;\nthe gateway field for such entries shows the address of the outgoing interface.\nThe refcnt field gives the\ncurrent number of active uses of the route.  Connection oriented\nprotocols normally hold on to a single route for the duration of\na connection while connectionless protocols obtain a route while sending\nto the same destination.\nThe use field provides a count of the number of packets\nsent using that route.  The interface entry indicates the network\ninterface utilized for the route.\n.PP\nWhen \n.I netstat\nis invoked with an\n.I interval\nargument, it displays a running count of statistics related to\nnetwork interfaces.  This display consists of a\ncolumn for the primary interface\n(the first interface found during autoconfiguration)\nand a column summarizing\ninformation for all interfaces.\nThe primary interface may be replaced with another interface with the\n.I \\-I\noption.\nThe first line of each screen of information contains a summary since the\nsystem was last rebooted.  Subsequent lines of output show values\naccumulated over the preceding interval.\n.SH SEE ALSO\niostat(1),\nvmstat(1),\nhosts(5),\nnetworks(5),\nprotocols(5),\nservices(5),\ntrpt(8C)\n.SH BUGS\nThe notion of errors is ill-defined.  Collisions mean\nsomething else for the IMP.\n"
  },
  {
    "path": "share/man/man1/newaliases.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)newaliases.1\t6.2.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH NEWALIASES 1 \"October 22, 1996\"\n.UC 4\n.SH NAME\nnewaliases \\- rebuild the data base for the mail aliases file\n.SH SYNOPSIS\n.B newaliases\n.SH DESCRIPTION\n.I Newaliases\nrebuilds the random access data base for the mail aliases file\n.IR /etc/aliases .\nIt must be run each time\n.I /etc/aliases\nis changed in order\nfor the change to take effect.\n.SH SEE ALSO\naliases(5), sendmail(8)\n"
  },
  {
    "path": "share/man/man1/nice.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)nice.1\t6.2 (Berkeley) 5/8/86\n.\\\"\n.TH NICE 1 \"May 8, 1986\"\n.UC 4\n.SH NAME\nnice, nohup \\- run a command at low priority (\\fIsh\\fR only)\n.SH SYNOPSIS\n.B nice\n[\n.BI \\- number\n]\ncommand [ arguments ]\n.PP\n.B nohup\ncommand [ arguments ]\n.SH DESCRIPTION\n.I Nice\nexecutes\n.I command\nwith low scheduling priority.\nIf the\n.I number\nargument is present, the priority is incremented (higher\nnumbers mean lower priorities) by that amount up to a limit of 20.\nThe default\n.I number\nis 10.\n.PP\nThe super-user may run commands with\npriority higher than normal\nby using a negative priority,\ne.g. `\\-\\-10'.\n.PP\n.I Nohup\nexecutes\n.I command\nimmune to hangup and terminate signals from the controlling terminal.\nThe priority is incremented by 5.\n.I Nohup\nshould be invoked from the shell with `&' in order to \nprevent it from responding to interrupts by or\nstealing the input from\nthe next person who logs in on the same terminal.\n.SH FILES\nnohup.out\tstandard output and standard error file under\n.I nohup\n.SH \"SEE ALSO\"\ncsh(1), setpriority(2), renice(8)\n.SH DIAGNOSTICS\n.I Nice\nreturns the exit status of the subject command.\n.SH BUGS\n.I Nice\nand\n.I nohup\nare particular to\n.IR sh (1).\nIf you use\n.IR csh (1),\nthen commands executed with ``&'' are automatically immune to hangup\nsignals while in the background.\nThere is a builtin command\n.I nohup\nwhich provides immunity from terminate, but it does not\nredirect output to\n.I nohup.out.\n.PP\n.I Nice\nis built into\n.IR csh (1)\nwith a slightly different syntax than described here.  The form\n``nice +10'' nices to positive nice, and ``nice \\-10'' can be used\nby the super-user to give a process more of the processor.\n"
  },
  {
    "path": "share/man/man1/nm.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)nm.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH NM 1 \"April 29, 1985\"\n.UC 2\n.SH NAME\nnm \\- print name list (2BSD)\n.SH SYNOPSIS\n.B nm\n[\n.B \\-gnopru\n]\n[ file ... ]\n.SH DESCRIPTION\n.I Nm\nprints the name list (symbol table) of each object\n.I file\nin the argument list.  If an argument is an archive, a listing for each object\nfile in the archive will be produced.  If no\n.I file\nis given, the symbols in \"a.out\" are listed.\n.PP\nEach symbol name is preceded by its value (blanks if undefined)\nand one of the letters\n.SM\n.B U\n(undefined),\n.SM\n.B A\n(absolute),\n.SM\n.B  T\n(text segment symbol),\n.SM\n.B D\n(data segment symbol),\n.SM\n.B B\n(bss segment symbol),\n.SM\n.B C\n(common symbol),\nor\n.SM\n.B f\nfile name.\nIf the symbol is local (non-external) the type letter is in lower case.\nIf the file is an overlaid executable, the overlay number is printed\nafter the name.  The number is printed if the symbol is in an overlay\nor if it is the entry point (in the base segment) for a subroutine in\nan overlay.\nThe output is sorted alphabetically.\n.PP\nOptions are:\n.TP\n.B  \\-g\nPrint only global (external) symbols.\n.TP\n.B \\-n\nSort numerically rather than alphabetically.\n.TP\n.B  \\-o\nPrepend file or archive element name to each output line rather than only once.\n.TP\n.B  \\-p\nDon't sort; print in symbol-table order.\n.TP\n.B  \\-r\nSort in reverse order.\n.TP\n.B  \\-u\nPrint only undefined symbols.\n.SH SEE ALSO\nar(1), ar(5), a.out(5), stab(5)\n"
  },
  {
    "path": "share/man/man1/nroff.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)nroff.1\t6.1.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH NROFF 1 \"October 22, 1996\"\n.UC 5\n.SH NAME\nnroff \\- text formatting\n.SH SYNOPSIS\n.B nroff\n[ option ] ...\n[ file ] ...\n.SH DESCRIPTION\n.I Nroff\nformats text in the named\n.I files\nfor typewriter-like devices.  See also \n.I troff(1).\nThe full capabilities of\n.I nroff\nare described in the\n.I Nroff/Troff User's Manual.\n.PP\nIf no\n.I file\nargument is present, the standard input is read.\nAn argument consisting of a single minus\n.RB ( \\- )\nis taken to be a file name corresponding to the standard input.\n.PP\nThe options, which may appear in any order so long as they appear\n.I before\nthe files, are:\n.TP \"\\w'\\f3\\-m\\f1name 'u\"\n.BI \\-o list\nPrint only pages whose page numbers appear in the comma-separated\n.I list\nof numbers and ranges.  A range\n.IB N \\- M\nmeans pages\n.I N\nthrough\n.IR M ;\nan initial\n.I \\-N\nmeans from the beginning to page\n.IR N ;\nand a final\n.IR N \\-\nmeans from\n.I N\nto the end.\n.TP\n.BI \\-n N\nNumber first generated page\n.IR N .\n.TP\n.BI \\-s N\nStop every\n.I N\npages.\n.I Nroff\nwill halt prior to every\n.I N\npages (default\n.IR N =1)\nto allow paper loading or changing, and will resume upon receipt of a newline.\n.TP\n.BI \\-m name\nPrepend the macro file\n.BI /usr/share/tmac/tmac. name\nto the input\n.IR files .\n.TP\n.BI \\-r aN\nSet register\n.I a\n(one-character) to\n.IR N .\n.TP\n.B \\-i\nRead standard input after the input files are exhausted.\n.TP\n.B \\-q\nInvoke the simultaneous input-output mode of the\n.B rd\nrequest.\n.TP\n.BI \\-T name\nPrepare output for specified terminal.  Known\n.I names\nare\n.B 37\nfor the (default) Teletype Corporation Model 37 terminal,\n.B tn300\nfor the GE TermiNet\\ 300 (or any terminal without half-line capability),\n.B 300S\nfor the \\s-1DASI\\s+1-300S,\n.B 300\nfor the \\s-1DASI\\s+1-300,\nand\n.B 450\nfor the \\s-1DASI\\s+1-450 (Diablo Hyterm).\n.TP\n.B \\-e\nProduce equally-spaced words in adjusted lines, using full terminal resolution.\n.TP\n.B \\-h\nUse output tabs during horizontal spacing\nto speed output and reduce output character count.\nTab settings are assumed to be every 8 nominal character widths.\n.SH FILES\n.ta \\w'/usr/share/tmac/tmac.*  'u\n/tmp/ta*\ttemporary file\n.br\n/usr/share/tmac/tmac.*\tstandard macro files\n.br\n/usr/share/term/*\tterminal driving tables for\n.I nroff\n.br\n.SH \"SEE ALSO\"\nJ. F. Ossanna,\n.I Nroff/Troff user's manual\n.br\nB. W. Kernighan,\n.I A TROFF Tutorial\n.br\ntroff(1),\neqn(1),\ntbl(1),\nms(7),\nme(7),\nman(7),\ncol(1)\n"
  },
  {
    "path": "share/man/man1/nslookup.1",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)nslookup.1\t1.2 (Berkeley) 11/21/87\n.\\\"\n.TH NSLOOKUP 1 \"November 21, 1987\"\n.UC 6\n.SH NAME\nnslookup \\- query name servers interactively\n.SH SYNOPSIS\n.B nslookup\n[\n.I host-to-find | \\-\n[\n.I server address | server name\n]] \n.SH DESCRIPTION\n.IR Nslookup\nis a program to query DARPA Internet domain name servers. \nNslookup has two modes: interactive and non-interactive.\nInteractive mode allows the user to query the name server for\ninformation about various  hosts and domains or print a list of hosts \nin the domain. \nNon-interactive mode is used to print just the name and Internet address\nof a host or domain.\n.sp 1\n.SH ARGUMENTS\nInteractive mode is entered in the following cases:\n.IP a) 4\nwhen no arguments are given (the default name server will be used), and\n.IP b) 4\nwhen the first argument is a hyphen (\\-) and the second argument\nis the host name of a name server.\n.LP\nNon-interactive mode is used when the name of the host to be looked up\nis given as the first argument. The optional second argument specifies\na name server.\n.sp 1\n.SH \"INTERACTIVE COMMANDS\"\nCommands may be interrupted at any time by typing a control-C.\nTo exit, type a control-D (EOF).\nThe command line length must be less than 80 characters.\n\\fBN.B.\\fP an unrecognized command will be interpreted as a host name.\n.sp 1\n.IP \"host [server]\"\nLook up information for \\fIhost\\fP using the current default server\nor using \\fIserver\\fP if it is specified.\n.sp 1\n.IP \"\\fBserver\\fP \\fIdomain\\fP\"\n.ns\n.IP \"\\fBlserver\\fP \\fIdomain\\fP\"\nChange the default server to \\fIdomain\\fP. \n\\fBLserver\\fP uses the initial server to look up \ninformation about \\fIdomain\\fP while \\fBserver\\fP\nuses the current default server. \nIf an authoritative answer can't be found, the names of servers\nthat might have the answer are returned.\n.sp 1\n.IP \\fBroot\\fP\nChanges the default server to the server for the root of the domain name space.\nCurrently, the host sri-nic.arpa is used.\n(This command is a synonym for the \\fBlserver sri-nic.arpa\\fP.)\nThe name of the root server can be changed with the \\fBset root\\fP command.\n.sp 1\n.IP \"\\fBfinger\\fP [\\fIname\\fP] [\\fB>\\fP \\fIfilename\\fP]\"\n.ns\n.IP \"\\fBfinger\\fP [\\fIname\\fP] [\\fB>>\\fP \\fIfilename\\fP]\"\nConnects with the finger server on the current host. \nThe current host is defined when a previous lookup for a host\nwas successful and returned address information (see the \n\\fBset querytype=A\\fP command).\n\\fIName\\fP is optional. \n\\fB>\\fP and \\fB>>\\fP can be used to redirect output in the\nusual manner.\n.sp 1\n.IP \"\\fBls\\fP \\fIdomain\\fP [\\fB>\\fP \\fIfilename\\fP]\"\n.ns\n.IP \"\\fBls\\fP \\fIdomain\\fP [\\fB>>\\fP \\fIfilename\\fP]\"\n.ns\n.IP \"\\fBls -a\\fP \\fIdomain\\fP [\\fB>\\fP \\fIfilename\\fP]\"\n.ns\n.IP \"\\fBls -a\\fP \\fIdomain\\fP [\\fB>>\\fP \\fIfilename\\fP]\"\n.ns\n.IP \"\\fBls -h\\fP \\fIdomain\\fP [\\fB>\\fP \\fIfilename\\fP]\"\n.ns\n.IP \"\\fBls -h\\fP \\fIdomain\\fP [\\fB>>\\fP \\fIfilename\\fP]\"\n.IP \"\\fBls -d\\fP \\fIdomain\\fP [\\fB>\\fP \\fIfilename\\fP]\"\n.ns\nList the information available for \\fIdomain\\fP. \nThe default output contains host names and their Internet addresses. \nThe \\fB-a\\fP option lists aliases of hosts in the domain.\nThe \\fB-h\\fP option lists CPU and operating system information for the domain.\nThe \\fB-d\\fP option lists all contents of a zone transfer.\nWhen output is directed to a file, hash marks are printed for every\n50 records received from the server.\n.sp 1\n.IP \"\\fBview\\fP \\fIfilename\\fP\"\nSorts and lists the output of previous \\fBls\\fP command(s) with \\fImore\\fP(1).\n.sp 1\n.IP \"\\fBhelp\\fP\"\n.ns\n.IP \"\\fB?\\fP\"\nPrints a brief summary of commands.\n.sp 1\n.IP \"\\fBset\\fP \\fIkeyword\\fP[=\\fIvalue\\fP]\"\nThis command is used to change state information that affects the lookups.\nValid keywords are:\n.RS\n.IP \"\\fBall\\fP\"\nPrints the current values of the various options to \\fBset\\fP.\nInformation about the  current default server and host is also printed.\n.IP \"\\fB[no]debug\\fP\"\nTurn debugging mode on. A lot more information is printed about the\npacket sent to the server and the resulting answer.\n.br\n(Default = nodebug, abbreviation = [no]deb)\n.IP \"\\fB[no]d2\\fP\"\nTurn exhaustive debugging mode on.\nEssentially all fields of every packet are printed.\n.br\n(Default = nod2)\n.IP \"\\fB[no]defname\\fP\"\nAppend the default domain name to every lookup.\n.br\n(Default = defname, abbreviation = [no]def)\n.IP \"\\fB[no]search\\fP\"\nWith defname, search for each name in parent domains of the current domain.\n.br\n(Default = search)\n.IP \"\\fBdomain=\\fIname\\fR\"\nChange the default domain name to \\fIname\\fP. \nThe default domain name is appended to all lookup requests if \nthe \\fBdefname\\fP option has been set.\nThe search list is set to parents of the domain with at least two components\nin their names.\n.br\n(Default = value in hostname or /etc/resolv.conf, abbreviation = do)\n.IP \"\\fBquerytype=\\fIvalue\\fR\"\n.IP \"\\fBtype=\\fIvalue\\fR\"\nChange the type of information returned from a query to one of:\n.RS\n.IP A 10\nthe host's Internet address (the default).\n.IP CNAME  10\nthe canonical name for an alias. \n.IP HINFO 10\nthe host CPU and operating system type.\n.IP MD 10\nthe mail destination.\n.IP MX 10\nthe mail exchanger.\n.IP MG     10\nthe mail group member.\n.IP MINFO 10\nthe mailbox or mail list information.\n.IP MR     10\nthe mail rename domain name.\n.IP NS     10\nnameserver for the named zone.\n.RE\nOther types specified in the RFC883 document are valid but aren't\nvery useful.\n.br\n(Abbreviation = q)\n.IP \"\\fB[no]recurse\\fP\"\nTell the name server to query other servers if it does not have the\ninformation.\n.br\n(Default = recurse, abbreviation = [no]rec)\n.IP \\fBretry=\\fInumber\\fR\nSet the number of retries to \\fInumber\\fP. \nWhen a reply to a request is not received within a certain \namount of time (changed with \\fBset timeout\\fP), \nthe request is resent. \nThe retry value controls how many times a request is resent before giving up.\n.br\n(Default = 2, abbreviation = ret)\n.IP \\fBroot=\\fIhost\\fR\nChange the name of the root server to \\fIhost\\fP. This\naffects the \\fBroot\\fP command. \n.br\n(Default = sri-nic.arpa, abbreviation = ro)\n.IP \\fBtimeout=\\fInumber\\fR\nChange the time-out interval for waiting for a reply to \\fInumber\\fP seconds.\n.br\n(Default = 10 seconds, abbreviation = t)\n.IP \"\\fB[no]vc\\fP\"\nAlways use a virtual circuit when sending requests to the server.\n.br\n(Default = novc, abbreviation = [no]v)\n.RE\n.SH DIAGNOSTICS\nIf the lookup request was not successful, an error message is printed.\nPossible errors are:\n.IP \"Time-out\"\nThe server did not respond to a request after a certain amount of\ntime (changed with \\fBset timeout=\\fIvalue\\fR) \nand a certain number of retries (changed with \\fBset retry=\\fIvalue\\fR).\n.IP \"No information\"\nDepending on the query type set with the \\fBset querytype\\fP command,\nno information about the host was available, though the host name is\nvalid.\n.IP \"Non-existent domain\"\nThe host or domain name does not exist.\n.IP \"Connection refused\"\n.ns\n.IP \"Network is unreachable\"\nThe connection to the name or finger server could not be made \nat the current time.\nThis error commonly occurs with \\fBfinger\\fP requests. \n.IP \"Server failure\"\nThe name server found an internal inconsistency in its database\nand could not return a valid answer.\n.IP \"Refused\"\nThe name server refused to service the request.\n.sp 1\n.PP\nThe following error should not occur and it indicates a bug in the program.\n.IP \"Format error\"\nThe name server found that the request packet was not in the proper format.\n.sp 1\n.SH FILES\n/etc/resolv.conf\tinitial domain name and name server addresses.\n.SH SEE ALSO\nresolver(3), resolver(5), named(8), RFC882, RFC883\n.SH AUTHOR\nAndrew Cherenson\n"
  },
  {
    "path": "share/man/man1/od.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)od.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH OD 1 \"April 29, 1985\"\n.UC 4\n.SH NAME\nod \\- octal, decimal, hex, ascii dump\n.SH SYNOPSIS\n.B od\n[ \\-format ] [ file ] [ [\\fB+\\fP]offset[\\fB.\\fP][\\fBb\\fP] [label] ]\n.SH DESCRIPTION\n.I Od\ndisplays\n.IR file ,\nor it's standard input,\nin one or more dump formats\nas selected by the first argument.\nIf the first argument is missing,\n.B \\-o\nis the default.\nDumping continues until end-of-file.\n.PP\nThe meanings of the format argument characters are:\n.TP 5\n.B  a\nInterpret bytes as characters and display them with their ACSII names.\nIf the\n.B p\ncharacter is given also, then bytes with even parity are underlined.\nThe\n.B P\ncharacter causes bytes with odd parity to be underlined.\nOtherwise the parity bit is ignored.\n.TP 5\n.B  b\nInterpret bytes as unsigned octal.\n.TP 5\n.B  c\nInterpret bytes as ASCII characters.\nCertain non-graphic characters appear as C escapes:\nnull=\\e0,\nbackspace=\\eb,\nformfeed=\\ef,\nnewline=\\en,\nreturn=\\er,\ntab=\\et;\nothers appear as 3-digit octal numbers.\nBytes with the parity bit set are displayed in octal.\n.TP 5\n.B  d\nInterpret (short) words as unsigned decimal.\n.TP 5\n.B  f\nInterpret long words as floating point.\n.TP 5\n.B  h\nInterpret (short) words as unsigned hexadecimal.\n.TP 5\n.B  i\nInterpret (short) words as signed decimal.\n.TP 5\n.B  l\nInterpret long words as signed decimal.\n.TP 5\n.B  o\nInterpret (short) words as unsigned octal.\n.TP 5\n.BR s [n]\nLook for strings of ascii graphic characters, terminated with a null byte.\n.I N\nspecifies the minimum length string to be recognized.\nBy default, the minimum length is 3 characters.\n.TP 5\n.B  v\nShow all data. By default, display lines that are identical to the last\nline shown are not output, but are indicated with an ``*'' in column 1.\n.TP 5\n.BR w [n]\nSpecifies the number of input bytes to be interpreted and displayed\non each output line. If\n.B w\nis not specified, 16 bytes are read for each display line.\nIf\n.I n\nis not specified, it defaults to 32.\n.TP 5\n.B  x\nInterpret (short) words as hexadecimal.\n.PP\nAn upper case format character implies the long or double precision\nform of the object.\n.PP\nThe\n.I offset\nargument specifies the byte offset\ninto the file where dumping is to commence.\nBy default this argument is interpreted in octal.\nA different radix can be specified;\nIf ``\\fB.\\fR'' is appended to the argument, then\n.I offset\nis interpreted in decimal.\nIf\n.I offset\nbegins with ``\\fBx\\fP'' or ``\\fB0x\\fP'',\nit is interpreted in hexadecimal.\nIf ``\\fBb\\fP'' (``\\fBB\\fP'') is appended, the offset is interpreted\nas a block count, where a block is 512 (1024) bytes.\nIf the\n.I file\nargument is omitted, an\n.I offset\nargument must be preceded by\n.RB `` + ''.\n.PP\nThe radix of the displayed address will be the same as the radix of the\n.IR offset ,\nif specified; otherwise it will be octal.\n.PP\n.I Label\nwill be interpreted as a pseudo-address for the first byte displayed.\nIt will be shown in ``()'' following the file offset.\nIt is intended to be used with\ncore images to indicate the real memory address.\nThe syntax for\n.I label\nis identical to that for\n.IR offset .\n.SH \"SEE ALSO\"\nadb(1)\n.SH BUGS\nA file name argument can't start with ``+''.\nA hexadecimal offset can't be a block count.\nOnly one file name argument can be given.\n.PP\nIt is an historical botch to require specification of object, radix, and\nsign representation in a single character argument.\n"
  },
  {
    "path": "share/man/man1/pagesize.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)pagesize.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH PAGESIZE 1 \"April 29, 1985\"\n.UC 5\n.SH NAME\npagesize \\- print system page size\n.SH SYNOPSIS\n.B pagesize\n.SH DESCRIPTION\n.I Pagesize\nprints the size of a page of memory in bytes, as\nreturned by\n.IR getpagesize (2).\nThis program is useful in constructing portable\nshell scripts.\n.SH SEE ALSO\ngetpagesize(2)\n"
  },
  {
    "path": "share/man/man1/pdx.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)pdx.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH PDX 1 \"April 29, 1985\"\n.UC 5\n.SH NAME\npdx \\- pascal debugger\n.SH SYNOPSIS\npdx [\\fB\\-r\\fP] [\\fIobjfile\\fP]\n.SH DESCRIPTION\n\\fIPdx\\fP is a tool for source level debugging and execution of\nPascal programs.\nThe \\fIobjfile\\fP is an object file produced by the Pascal translator\n\\fIpi\\fP(1).  If no \\fIobjfile\\fP is specified, \\fIpdx\\fP looks\nfor a file named ``obj'' in the current directory.\nThe object file contains a symbol table which includes the name of the\nall the source files translated by \\fIpi\\fP to create it.\nThese files are available for perusal while using the debugger.\n.PP\nIf the file ``.pdxinit'' exists in the current directory, then the\ndebugger commands in it are executed.\n.PP\nThe \\fB\\-r\\fP option causes the \\fIobjfile\\fP to be executed immediately;\nif it terminates successfully \\fIpdx\\fP exits.\nOtherwise it reports the reason for termination\nand offers the user the option of entering the debugger\nor simply letting \\fIpx\\fP continue with a traceback.\nIf \\fB\\-r\\fP is not specified, \\fIpdx\\fP just prompts and waits for a command.\n.PP\nThe commands are:\n.TP\n\\fBrun\\fP [\\fIargs\\fP] [\\fB<\\fP \\fIfilename\\fP] [\\fB>\\fP \\fIfilename\\fP]\nStart executing \\fIobjfile\\fP, passing \\fIargs\\fP as command line arguments;\n\\fB<\\fP or \\fB>\\fP can be used to redirect input or output in the usual manner.\n.TP\n\\fBtrace\\fP [\\fBin\\fP \\fIprocedure/function\\fP] [\\fBif\\fP \\fIcondition\\fP]\n.ns\n.TP\n\\fBtrace\\fP \\fIsource-line-number\\fP [\\fBif\\fP \\fIcondition\\fP]\n.ns\n.TP\n\\fBtrace\\fP \\fIprocedure/function\\fP [\\fBin\\fP \\fIprocedure/function\\fP] [\\fBif\\fP \\fIcondition\\fP]\n.ns\n.TP\n\\fBtrace\\fP \\fIexpression\\fP \\fBat\\fP \\fIsource-line-number\\fP [\\fBif\\fP \\fIcondition\\fP]\n.ns\n.TP\n\\fBtrace\\fP \\fIvariable\\fP [\\fBin\\fP \\fIprocedure/function\\fP] [\\fBif\\fP \\fIcondition\\fP]\nHave tracing information printed when the program is executed.\nA number is associated with the command that is used\nto turn the tracing off (see the \\fBdelete\\fP command).\n.sp 1\nThe first argument describes what is to be traced.\nIf it is a \\fIsource-line-number\\fP, then the line is printed\nimmediately prior to being executed.\nSource line numbers in a file other than the current one\nmust be preceded by the name of the file and a colon, e.g.\n``mumble.p:17''.\n.sp 1\nIf the argument is a procedure or function name then\nevery time it is called, information is printed telling\nwhat routine called it, from what source line it was called,\nand what parameters were passed to it.\nIn addition, its return is noted, and if it's a function\nthen the value it is returning is also printed.\n.sp 1\nIf the argument is an \\fIexpression\\fP with an \\fBat\\fP clause\nthen the value of the expression is printed whenever the\nidentified source line is reached.\n.sp 1\nIf the argument is a variable then the name and value of the variable\nis printed whenever it changes.\nExecution is substantially slower during this form of tracing.\n.sp 1\nIf no argument is specified then all source lines are printed\nbefore they are executed.\nExecution is substantially slower during this form of tracing.\n.sp 1\nThe clause ``\\fBin\\fP \\fIprocedure/function\\fP'' restricts tracing information\nto be printed only while executing inside the given procedure\nor function.\n.sp 1\n\\fICondition\\fP is a Pascal boolean expression and is\nevaluated prior to printing the tracing information;\nif it is false then the information is not printed.\n.sp 1\nThere is no restriction on the amount of information\nthat can be traced.\n.br\n.ne 10\n.IP \"\\fBstop\\fP \\fBif\\fP \\fIcondition\\fP\"\n.ns\n.IP \"\\fBstop\\fP \\fBat\\fP \\fIsource-line-number\\fP [\\fBif\\fP \\fIcondition\\fP]\"\n.ns\n.IP \"\\fBstop\\fP \\fBin\\fP \\fIprocedure/function\\fP [\\fBif\\fP \\fIcondition\\fP]\"\n.ns\n.IP \"\\fBstop\\fP \\fIvariable\\fP [\\fBif\\fP \\fIcondition\\fP]\"\nStop execution when the given line is reached, procedure or function\ncalled, variable changed, or condition true.\n.IP \"\\fBdelete\\fP \\fIcommand-number\\fP\"\nThe trace or stop corresponding to the given number is removed.\nThe numbers associated with traces and stops are printed by\nthe \\fBstatus\\fP command.\n.IP \"\\fBstatus\\fP [\\fB>\\fP \\fIfilename\\fP]\"\nPrint out\nthe currently active \\fBtrace\\fP and \\fBstop\\fP commands.\n.IP \\fBcont\\fP\nContinue execution from where it stopped.\nThis can only be\ndone when the program was stopped by an interrupt\nor through use of the \\fBstop\\fP command.\n.IP \\fBstep\\fP\nExecute one source line.\n.IP \\fBnext\\fP\nExecute up to the next source line.\nThe difference between this and \\fBstep\\fP is that\nif the line contains a call to a procedure or function\nthe \\fBstep\\fP command will stop at the beginning of that\nblock, while the \\fBnext\\fP command will not.\n.IP \"\\fBprint\\fP \\fIexpression\\fP [\\fB,\\fP \\fIexpression\\fP ...]\"\nPrint out the values of the Pascal expressions.\nVariables declared in an outer block but having\nthe same identifier as one in the current block may be\nreferenced as ``\\fIblock-name\\fP\\ \\fB.\\fP\\ \\fIvariable\\fP''.\n.IP \"\\fBwhatis\\fP \\fIidentifier\\fP\"\nPrint the declaration of the given identifier.\n.IP \"\\fBwhich\\fP \\fIidentifier\\fP\"\nPrint the full qualification of the given identifer, i.e.\nthe outer blocks that the identifier is associated with.\n.IP \"\\fBassign\\fP \\fIvariable\\fP \\fIexpression\\fP\"\nAssign the value of the expression to the variable.\n.IP \"\\fBcall\\fP \\fIprocedure(parameters)\\fP\"\nExecute the object code associated with the named procedure or function.\n.IP \\fBhelp\\fP\nPrint out a synopsis of \\fIpdx\\fP commands.\n.IP \\fBgripe\\fP\nInvokes a mail program to send a message to the person in charge of \\fIpdx\\fP.\n.IP \\fBwhere\\fP\nPrint out\na list of the active procedures and functions and the respective source\nline where they are called.\n.TP\n\\fBsource\\fP \\fIfilename\\fP\nRead \\fIpdx\\fP commands from the given \\fIfilename\\fP.\nEspecially useful when the \\fIfilename\\fP has been created by redirecting\na \\fBstatus\\fP command from an earlier debugging session.\n.IP \"\\fBdump\\fP [\\fB>\\fP \\fIfilename\\fP]\"\nPrint the names and values of all active\ndata.\n.IP \"\\fBlist\\fP [\\fIsource-line-number\\fP [\\fB,\\fP \\fIsource-line-number\\fP]]\"\n.ns\n.IP \"\\fBlist\\fP \\fIprocedure/function\\fP\"\nList the lines in the current source file from the first line number to\nthe second inclusive.\nAs in the editor\n``$'' can be used to refer to the last line.\nIf no lines are specified, the entire file is listed.\nIf the name of a procedure or function is given\nlines \\fIn-k\\fP to \\fIn+k\\fP are listed where \\fIn\\fP is the first statement\nin the procedure or function and \\fIk\\fP is small.\n.IP \"\\fBfile\\fP [\\fIfilename\\fP]\"\nChange the current source file name to \\fIfilename\\fP.\nIf none is specified then the current source file name is printed.\n.IP \"\\fBedit\\fP [\\fIfilename\\fP]\"\n.ns\n.IP \"\\fBedit\\fP \\fIprocedure/function-name\\fP\"\nInvoke an editor on \\fIfilename\\fP or the current source file if none\nis specified.\nIf a \\fIprocedure\\fP or \\fIfunction\\fP name is specified,\nthe editor is invoked on the file that contains it.\nWhich editor is invoked by default depends on the installation.\nThe default can be overridden by setting the environment variable\nEDITOR to the name of the desired editor.\n.IP \\fBpi\\fP\nRecompile the program and read in the new symbol table information.\n.IP \"\\fBsh\\fP \\fIcommand-line\\fP\"\nPass the command line to the shell for execution.\nThe SHELL environment variable determines which shell is used.\n.IP \"\\fBalias\\fP \\fInew-command-name\\fP \\fIold-command-name\\fP\"\nThis command makes \\fIpdx\\fP respond to \\fInew-command-name\\fP\nthe way it used to respond to \\fIold-command-name\\fP.\n.IP \"\\fBquit\\fP\"\nExit \\fIpdx\\fP.\n.sp 4\n.PP\nThe following commands deal with the program at the \\fIpx\\fP instruction\nlevel rather than source level.\nThey are not intended for general use.\n.TP\n\\fBtracei\\fP [\\fIaddress\\fP] [\\fBif\\fP \\fIcond\\fP]\n.ns\n.TP\n\\fBtracei\\fP [\\fIvariable\\fP] [\\fBat\\fP \\fIaddress\\fP] [\\fBif\\fP \\fIcond\\fP]\n.ns\n.TP\n\\fBstopi\\fP [\\fIaddress\\fP] [\\fBif\\fP \\fIcond\\fP]\n.ns\n.TP\n\\fBstopi\\fP [\\fBat\\fP] [\\fIaddress\\fP] [\\fBif\\fP \\fIcond\\fP]\nTurn on tracing or set a stop using a \\fIpx\\fP machine\ninstruction addresses.\n.TP\n\\fBxi\\fP \\fIaddress\\fP [\\fB,\\fP \\fIaddress\\fP]\nPrint the instructions starting at the first \\fIaddress\\fP.\nInstructions up to\nthe second \\fIaddress\\fP are printed.\n.TP\n\\fBxd\\fP \\fIaddress\\fP [\\fB,\\fP \\fIaddress\\fP]\nPrint in octal the specified data location(s).\n.SH FILES\n.nr In 25\n.in +\\n(Inn\n.ta \\n(Inn\n.br\n.nr wg 1v\n.ie \\n(.h=\\n(vk .nr wg -\\n(vhu\n.el .nr vh 0\n.if \\n(wg>0 \\{\\\n.sp \\n(wgu\n.nr vh +\\n(wgu \\}\n.nr vk \\n(.h\n.ti -\\n(Inn\n\\&obj\t\\c\nPascal object file\n.br\n.nr wg 0v\n.ie \\n(.h=\\n(vk .nr wg -\\n(vhu\n.el .nr vh 0\n.if \\n(wg>0 \\{\\\n.sp \\n(wgu\n.nr vh +\\n(wgu \\}\n.nr vk \\n(.h\n.ti -\\n(Inn\n\\&\\&.pdxinit\t\\c\n\\fIPdx\\fP initialization file\n.in -\\n(Inn\n.br\n.nr wg 1v\n.ie \\n(.h=\\n(vk .nr wg -\\n(vhu\n.el .nr vh 0\n.if \\n(wg>0 \\{\\\n.sp \\n(wgu\n.nr vh +\\n(wgu \\}\n.nr vk \\n(.h\n.SH SEE ALSO\npi(1), px(1)\n.br\n\\fIAn Introduction to Pdx\\fP\n.SH BUGS\n\\fIPdx\\fP does not understand sets,\nand provides no information about files.\n.sp 1\nThe \\fIwhatis\\fP command doesn't quite work for variant records.\n.sp 1\nBad things will happen if a procedure invoked with\nthe \\fBcall\\fP command does a non-local goto.\n.sp 1\nThe commands \\fBstep\\fP and \\fBnext\\fP should be able to take a \\fIcount\\fP\nthat specifies how many lines to execute.\n.sp 1\nThere should be commands \\fBstepi\\fP and \\fBnexti\\fP that correspond\nto \\fBstep\\fP and \\fBnext\\fP but work at the instruction level.\n.sp 1\nThere should be a way to get an address associated with\na line number, procedure or function, and variable.\n.sp 1\nMost of the command names are too long.\n.sp 1\nThe alias facility is quite weak.\n.sp 1\nA \\fIcsh\\fP-like history capability would improve the situation.\n"
  },
  {
    "path": "share/man/man1/pi.1",
    "content": ".\\\"\t@(#)pi.1\t1.1 (2.11BSD) 1996/10/22\n.TH PI 1 \"October 22, 1996\"\n.UC\n.SH NAME\npi \\- Pascal interpreter code translator\n.SH SYNOPSIS\n.B pi\n[\n.B \\-blnpstuwz\n] [\n.B \\-i\nname ...\n] name.p\n.SH DESCRIPTION\n.I Pi\ntranslates the program in the file\n.I name.p\nleaving interpreter code in the file\n.I obj\nin the current directory.\nThe interpreter code can be executed using\n.I px.\n.I Pix\nperforms the functions of\n.I pi\nand\n.I px\nfor `load and go' Pascal.\n.PP\nThe following flags are interpreted by \n.I pi;\nthe associated options can also be controlled in comments within the program\nas described in the\n.I \"Berkeley Pascal User's Manual.\"\n.TP 6\n.B  \\-\\^b\nBlock buffer the file\n.I output.\n.TP 6\n.B  \\-\\^i\nEnable the listing for\nany specified procedures and functions and while processing any specified\n.B include\nfiles.\n.TP 6\n.B  \\-\\^l\nMake a program listing during translation.\n.TP 6\n.B  \\-\\^n\nBegin each listed\n.B include\nfile on a new page with a banner line.\n.TP 6\n.B  \\-\\^p\nSuppress the post-mortem control flow backtrace\nif an error occurs;\nsuppress statement limit counting.\n.TP 6\n.B  \\-\\^s\nAccept standard Pascal only;\nnon-standard constructs cause warning diagnostics.\n.TP 6\n.B  \\-\\^t\nSuppress runtime tests of subrange variables and treat\n.B assert\nstatements as comments.\n.TP 6\n.B  \\-\\^u\nCard image mode;\nonly the first 72 characters of input lines are used.\n.TP 6\n.B  \\-\\^w\nSuppress warning diagnostics.\n.TP 6\n.B  \\-\\^z\nAllow execution profiling with\n.I pxp\nby generating statement counters, and arranging for the\ncreation of the profile data file\n.I pmon.out\nwhen the resulting object is executed.\n.SH FILES\n.DT\n.ta 2i\nfile.p\tinput file\n.br\nfile.i\t\\fBinclude\\fP file(s)\n.br\n/usr/share/pascal/pi_strings\ttext of the error messages\n.br\n.nf\n/usr/share/pascal/how_pi*\tbasic usage explanation\n.fi\nobj\tinterpreter code output\n.DT\n.SH \"SEE ALSO\"\nBerkeley Pascal User's Manual\n.br\npcc(1), pix(1), px(1), pxp(1), pxref(1)\n.SH DIAGNOSTICS\nFor a basic explanation do\n.IP\n.B\tpi\n.PP\nIn the diagnostic output of the translator,\nlines containing syntax errors are listed with a flag indicating the\npoint of error.\nDiagnostic messages indicate the action which the recovery mechanism\ntook in order to be able to continue parsing.\nSome diagnostics indicate only that the input is `malformed.'\nThis occurs if the recovery can find no simple correction to make the input\nsyntactically valid.\n.PP\nSemantic error diagnostics indicate a line in the source text near the\npoint of error.\nSome errors evoke more than one diagnostic to help pinpoint the error;\nthe follow-up messages begin with an ellipsis `...'.\n.PP\n.ne 8\nThe first character of each error message indicates its class:\n.IP\n.ta 1c 2.i\n\tE\tFatal error; no code will be generated.\n.br\n\te\tNon-fatal error.\n.br\n\tw\tWarning \\- a potential problem.\n.br\n\ts\tNon-standard Pascal construct warning.\n.PP\nIf a severe error occurs which inhibits further processing,\nthe translator will give a diagnostic and then `QUIT'.\n.SH AUTHORS\nCharles B. Haley, William N. Joy, and Ken Thompson\n.SH BUGS\nFormal parameters which are procedures and functions are not supported.\n.PP\nThe keyword\n.B packed\nand the function\n.I dispose\nare recognized but have no effect.\n.PP\nFor clarity,\nsemantic errors should be flagged at an appropriate place in the source text,\nand multiple instances of the `same' semantic error should be summarized\nat the end of a\n.B procedure\nor\n.B function\nrather than evoking many diagnostics.\n.PP\nWhen\n.B include\nfiles are present,\ndiagnostics relating to the last procedure in one file may appear after the\nbeginning of the listing of the next.\n"
  },
  {
    "path": "share/man/man1/pix.1",
    "content": ".\\\"\t@(#)pix.1\t1.1 (2.11BSD) 1996/10/22\n.TH PIX 1 \"October 22, 1996\"\n.UC\n.SH NAME\npix \\- Pascal interpreter and executor\n.SH SYNOPSIS\n.B pix\n[\n.B \\-blnpstuwz\n] [\n.B \\-i\nname ...\n]\nname.p\n[\nargument ...\n]\n.SH DESCRIPTION\n.I Pix\nis a `load and go' version of Pascal which combines\nthe functions of the interpreter code translator\n.I pi\nand the executor\n.IR px .\nIt uses\n.I pi\nto translate the program in the file\n.I name.p\nand, if there were no fatal errors during translation,\ncauses the resulting interpreter code\nto be executed by\n.I px\nwith the specified arguments.\nA temporary file is used for the object code;\nthe file\n.I obj\nis neither created nor destroyed.\n.SH FILES\n.ta 2i\n/usr/bin/pi\tPascal translator\n.br\n/usr/bin/px\tPascal executor\n.br\n/tmp/pix?????\ttemporary files\n.br\n/usr/share/pascal/how_pix\tbasic explanation\n.SH SEE\\ ALSO\nBerkeley Pascal User's Manual\n.br\npi(1), px(1)\n.SH DIAGNOSTICS\nFor a basic explanation do\n.PP\n.DT\n.B\tpix\n.SH AUTHOR\nSusan L. Graham and William N. Joy\n"
  },
  {
    "path": "share/man/man1/plot.1",
    "content": ".\\\"\t@(#)plot.1g\t6.3 (Berkeley) 9/21/85\n.\\\"\n.TH PLOT 1G \"September 21, 1985\"\n.AT 3\n.SH NAME\nplot \\- graphics filters\n.SH SYNOPSIS\n.B plot\n[\n.BR \\-T terminal\n] [\n.BR \\-r resolution\n]\n[ files... ]\n.SH DESCRIPTION\nThese commands read plotting instructions (see\n.IR  plot (5))\nfrom the standard input or the specified\n.IR files ,\nand in general\nproduce plotting instructions suitable for\na particular\n.I terminal\non the standard output.\nThe\n.B \\-r\nflag may be used to specify the device's output resolution\n(currently only the Imagen laser printer understands this option).\n.PP\nIf no\n.I terminal\ntype is specified, the environment parameter $TERM\n(see\n.IR environ (7))\nis used.\nKnown\n.I terminals\nare:\n.TP\n.B 4013\nTektronix 4013 storage scope.\n.TP\n.BR 4014\\  or\\  tek\nTektronix 4014 or 4015 storage scope with Enhanced Graphics Module.\n(Use 4013 for Tektronix 4014 or 4015 without the Enhanced Graphics Module).\n.TP\n.B 450\nDASI Hyterm 450 terminal (Diablo mechanism).\n.TP\n.B 300\nDASI 300 or GSI terminal (Diablo mechanism).\n.TP\n.B 300S\nDASI 300S terminal (Diablo mechanism).\n.TP\n.B aed\nAED 512 color graphics terminal.\n.TP\n.BR bitgraph\\  or\\  bg\nBBN bitgraph graphics terminal.\n.TP\n.B imagen\\ or\\ ip\nImagen laser printer (default 240 dots-per-inch resolution).\n.TP\n.B crt\nAny crt terminal capable of running\n.IR vi (1).\n.TP\n.B dumb\nDumb terminals without cursor addressing or line printers.\n.TP\n.B vt125\nDEC vt125 terminal.\n.TP\n.BR hp2648\\  or\\  hp\\  or\\  hp8\nHewlett Packard 2648 graphics terminal.\n.TP\n.B ver\nVersatec D1200A printer-plotter.\n.TP\n.B var\nBenson Varian printer-plotter.\n.IP\nThese versions of\n.I plot\nuse the\n.B \\-g\noption of\n.IR lpr (1)\nto send the result directly to the plotter device rather than to\nthe standard output.\n.SH FILES\n/usr/bin/t4013\n.br\n/usr/bin/tek\n.br\n/usr/bin/t450\n.br\n/usr/bin/t300\n.br\n/usr/bin/t300s\n.br\n/usr/bin/aedplot\n.br\n/usr/bin/bgplot\n.br\n/usr/bin/crtplot\n.br\n/usr/bin/dumbplot\n.br\n/usr/bin/gigiplot\n.br\n/usr/bin/hpplot\n.br\n/usr/bin/implot\n.br\n/usr/ucb/lpr\n.SH \"SEE ALSO\"\nplot(3X), plot(3F), plot(5), lpr(1)\n"
  },
  {
    "path": "share/man/man1/pmerge.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)pmerge.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH PMERGE 1 \"April 29, 1985\"\n.UC 4\n.SH NAME\npmerge \\- pascal file merger\n.SH SYNOPSIS\n.B pmerge\nname.p ...\n.SH DESCRIPTION\n.I Pmerge\nassembles the named Pascal files into a single standard Pascal program.\nThe resulting program is listed on the standard output.\nIt is intended to be used to merge a collection of separately compiled\nmodules so that they can be run through \n.B pi\n, or exported to other sites.\n.SH FILES\n.ta 1.5i\n/usr/tmp/MG\\(**\tdefault temporary files\n.br\n.SH \"SEE ALSO\"\npc(1),\npi(1),\n.br\nAuxiliary documentation\n.I Berkeley Pascal User's Manual.\n.SH AUTHOR\nM. Kirk McKusick\n.SH BUGS\nVery minimal error checking is done,\nso incorrect programs will produce unpredictable results.\nBlock comments should be placed after the keyword to which they refer\nor they are likely to end up in bizarre places.\n"
  },
  {
    "path": "share/man/man1/pr.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)pr.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH PR 1 \"April 29, 1985\"\n.UC 4\n.SH NAME\npr \\- print file\n.SH SYNOPSIS\n.B pr\n[ option ] ...\n[ file ] ...\n.SH DESCRIPTION\n.I Pr\nproduces a printed listing of one or more\n.I files.\nThe output is separated into pages headed by a date,\nthe name of the file or a specified header, and the page number.\nIf there are no file arguments,\n.I pr\nprints its standard input.\n.PP\nOptions apply to all following files but may be reset\nbetween files:\n.TP\n.BI \\- n\nProduce\n.IR n -column\noutput.\n.TP\n.BI + n\nBegin printing with page\n.I  n.\n.TP\n.B  \\-h\nTake the next argument as a page header.\n.TP\n.BI \\-w n\nFor purposes of multi-column output,\ntake the width of the page to be\n.I n\ncharacters instead of the default 72.\n.TP\n.BI \\-f\nUse formfeeds instead of newlines to separate pages.\nA formfeed is assumed to use up two blank lines at the top of a page.\n(Thus this option does not affect the effective page length.)\n.TP\n.BI \\-l n\nTake the length of the page to be\n.I n\nlines instead of the default 66.\n.TP\n.B  \\-t\nDo not print the 5-line header or the\n5-line trailer normally supplied for each page.\n.TP\n.BI \\-s c\nSeparate columns by the single character\n.I c\ninstead of by the appropriate amount of white space.\nA missing\n.I c\nis taken to be a tab.\n.TP\n.B  \\-m\nPrint all\n.I files\nsimultaneously,\neach in one column,\n.PP\nInter-terminal messages via\n.IR write (1)\nare\nforbidden during a\n.IR pr .\n.SH FILES\n/dev/tty?\nto suspend messages.\n.SH \"SEE ALSO\"\ncat(1)\n.SH DIAGNOSTICS\nThere are no diagnostics when\n.I pr\nis printing on a terminal.\n"
  },
  {
    "path": "share/man/man1/printenv.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)printenv.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH PRINTENV 1 \"April 29, 1985\"\n.UC\n.SH NAME\nprintenv \\- print out the environment\n.SH SYNOPSIS\n.B printenv\n[ name ]\n.SH DESCRIPTION\n.I Printenv\nprints out the values of the variables in the environment.  If a\n.I name\nis specified, only its value is printed.\n.PP\nIf a\n.I name\nis specified and it is not defined in the environment,\n.I printenv\nreturns exit status 1, else it returns status 0.\n.SH SEE ALSO\nsh(1), environ(7), csh(1)\n"
  },
  {
    "path": "share/man/man1/prof.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)prof.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH PROF 1 \"April 29, 1985\"\n.UC 4\n.SH NAME\nprof \\- display profile data\n.SH SYNOPSIS\n.B prof\n[\n.B \\-a\n] [\n.B \\-l\n] [\n.B \\-n\n] [\n.B \\-z\n] [\n.B \\-s\n] [\n.B \\-v\n[\n.BI \\- \"low\\fR [ \\fB\\-\\fIhigh\\fR ]\"\n] ]\n[ a.out\n[ mon.out ... ] ]\n.SH DESCRIPTION\n.I Prof\ninterprets the file\nproduced by the\n.I monitor\nsubroutine.\nUnder default modes,\nthe symbol table in the\nnamed object file\n.I (a.out\ndefault)\nis read and correlated with the\nprofile file\n.I (mon.out\ndefault).\nFor each external symbol, the percentage\nof time spent executing between that symbol\nand the next\nis printed (in decreasing order),\ntogether with the number of times that routine was called\nand the number of milliseconds per call.\nIf more than one profile file is specified,\nthe output represents the sum of the profiles.\n.PP\nIn order for the number of calls to a routine to be tallied,\nthe\n.B \\-p\noption of\n.I cc,\n.I f77\nor\n.I pc\nmust have been given when the file containing the\nroutine was compiled.\nThis option also arranges for the\nprofile file to be produced automatically.\n.PP\nOptions are:\n.TP\n.B \\-a\nall symbols are reported rather than\njust external symbols.\n.TP\n.B \\-l\nthe output is sorted by symbol value.\n.TP\n.B \\-n\nthe output is sorted by number of calls\n.TP\n.B \\-s\na summary profile file is produced in\n.I mon.sum.\nThis is really only useful\nwhen more than one profile file is specified.\n.TP\n.B \\-v\nall printing is suppressed\nand a graphic version of the profile\nis produced\non the standard output for display by the\n.IR  plot (1)\nfilters.\nWhen plotting, the numbers\n.I low\nand \n.I high,\nby default 0 and 100, may be given to cause a selected\npercentage of the profile to be plotted\nwith accordingly higher resolution.\n.TP\n.B \\-z\nroutines which have zero usage (as indicated by call counts\nand accumulated time) are nevertheless printed in the output.\n.SH FILES\n.ta \\w'mon.out  'u\nmon.out\tfor profile\n.br\na.out\t\tfor namelist\n.br\nmon.sum\tfor summary profile\n.SH \"SEE ALSO\"\nmonitor(3), profil(2), cc(1), plot(1G)\n.SH BUGS\nBeware of quantization errors.\n.PP\nIs confused by\n.I f77\nwhich puts the entry points at the bottom of subroutines and functions.\n"
  },
  {
    "path": "share/man/man1/ps.1",
    "content": ".TH PS 1 \"November 17, 1996\"\n.UC\n.SH NAME\nps \\- process status\n.SH SYNOPSIS\n.B ps\n[\n.B acgklnrtuwxU#\n[ core [ swap [ system ] ] ] ]\n.SH DESCRIPTION\n.I Ps\nprints certain indicia about active processes.\nTo get a complete printout on the console or lpr, use\n``ps\\ axlw''\nFor a quick snapshot of system activity,\n``ps\\ au''\nis recommended.\nA hyphen may precede options with no effect.\nThe following options may be specified.\n.TP\n.B a\nasks for information about all processes with terminals (ordinarily\nonly one's own processes are displayed).\n.TP\n.B c\ncauses only the\n.I comm\nfield to be displayed instead of the arguments.\n(The comm field is the tail of the path name of the file\nthe process last exec'ed.)\nThis option speeds up\n.I ps\nsomewhat and reduces the amount of output.\nIt is also more reliable since the process can't scribble on top of it.\n.TP\n.B g\nasks for all processes.\nWithout this option,\n.I ps\nonly prints ``interesting'' processes.\nProcesses are deemed to be uninteresting if they are process group leaders,\nor if their arguments begin with a `\\-'.\nThis normally eliminates shells and getty processes.\n.TP\n.B k\ncauses the file\n.I /usr/sys/core\nis used in place of\n.IR /dev/kmem \" and \" /dev/mem.\nThis is used for\npostmortem system debugging.\n.TP\n.B l\nasks for a long listing.\nThe short listing contains the user name, process ID, tty,\nthe cumulative execution time of the process and an\napproximation to the command line.\n.TP\n.B n\nasks for numeric rather than symbolic wchans.  This flag\nimplies the ``l'' flag.\n.TP\n.B r\nasks for ``raw'' output.\nA non-human readable sequence of structures is output on the standard output.\nThere is one structure for each process, the format is defined by\n<psout.h>\n.TP\n.BI t ttyname\nrestricts output to processes whose controlling tty is the\nspecified ttyname (which should be specified as printed by\n.I ps,\nincluding\n.I t?\nfor processes with no tty).\nThis option must be the last one given.\n.TP\n.B u\nA user oriented output is produced.\nThis includes the\nname of the owner of the process,\nprocess id,\nnice value,\nsize,\ntty,\ncpu time used,\nand the command.\n.TP\n.B w\ntells\n.I ps\nyou are on a wide terminal (132 columns).\n.I Ps\nnormally assumes\nyou are on an 80 column terminal.\nThis information is used to decide how much of long commands to print.\nThe\n.B w\noption may be repeated, e.g.\n.B ww,\nand the entire command, up to 128 characters, will be printed\nwithout regard to terminal width.\n.TP\n.B x\nasks even about processes with no terminal.\n.TP\n.B U\ncauses ps to update a private database where is keeps system\ninformation.  Thus ``ps \\-U'' should be included in the /etc/rc file.\n.TP\n.B #\nA process number may be given,\n(indicated here by #),\nin which case the output\nis restricted to that process.\nThis option must also be last.\n.PP\nA second argument tells\n.I ps\nwhere to look for\n.I core\nif the\n.I k\noption is given, instead of /usr/sys/core.\nA third argument is the name of a swap file to use instead of\nthe default /dev/swap.\nIf a fourth argument is given,\nit is taken to be the file containing the system's namelist.\nOtherwise, ``/unix'' is used.\n.PP\nThe output is sorted by tty, then by process ID.\n.PP\nThe long listing is columnar and contains\n.IP F\nFlags associated with the process.\nThese are defined by #define lines in /usr/include/sys/proc.h.\n.IP S\nThe state of the process.\n0: nonexistent;\nS: sleeping;\nW: waiting;\nR: running;\nI: intermediate;\nZ: terminated;\nT: stopped.\n.IP UID\nThe user id of the process owner.\n.IP PID\nThe process ID of the process;\nas in certain cults it is possible to kill a process\nif you know its true name.\n.IP PPID\nThe process ID of the parent process.\n.IP CPU\nProcessor utilization for scheduling.\n.IP PRI\nThe priority of the\nprocess; high numbers mean low priority.\n.IP NICE\nUsed in priority computation.\n.IP ADDR\nThe memory address of the process if resident,\notherwise the disk address.\n.IP SZ\nThe size in blocks (512 bytes) of the memory image of the process.\n.IP WCHAN\nThe event for which the process is waiting or sleeping;\nif blank, the process is running.\n.IP TTY\nThe controlling tty for the process.\n.IP TIME\nThe cumulative execution time for the process.\n.IP COMMAND\nThe command and its arguments.\n.DT\n.PP\nA process that has exited and has a parent, but has not\nyet been waited for by the parent is marked <defunct>.\n.I Ps\nmakes an educated guess as to the file name\nand arguments given when the process was created\nby examining memory or the swap area.\nThe method is inherently somewhat unreliable and in any event\na process is entitled to destroy this information,\nso the names cannot be counted on too much.\n.SH FILES\n.ta 2i\n/unix\tsystem namelist\n.br\n/dev/kmem\tkernel memory\n.br\n/dev/swap\tswap device\n.br\n/usr/sys/core\tcore file\n.br\n/dev\tsearched to find swap device and tty names\n.br\n/var/run/psdatabase\tsystem namelist and device information\n.SH \"SEE ALSO\"\nkill(1), w(1), pstat(8)\n.SH BUGS\nThings can change while\n.I ps\nis running; the picture it gives is only a close\napproximation to reality.\n...br\n..Some data printed for defunct processes is irrelevant.\n.PP\nSome processes, typically those in the background, are\nprinted with null or garbaged arguments, even though\nthe process has not swapped.\n(Sometimes ps even loses on its own arguments!)\nIn these cases, the name of the command is printed in parentheses.\n.PP\nWhen automatic crash dumps are enabled, /usr/sys/core is not\na sensible default core file name.\n"
  },
  {
    "path": "share/man/man1/ptx.1",
    "content": ".\\\"\t@(#)ptx.1\t6.1.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH PTX 1 \"October 22, 1996\"\n.AT 3\n.SH NAME\nptx \\- permuted index\n.SH SYNOPSIS\n.B ptx\n[ option ] ...\n[ input [ output ] ]\n.SH DESCRIPTION\n.I Ptx\ngenerates a permuted index to file\n.I input\non file\n.I output\n(standard input and output default).\nIt has three phases: the first does the permutation, generating\none line for each keyword in an input line.\nThe keyword is rotated to the front.\nThe permuted file is then\nsorted.\nFinally, the sorted lines are rotated so the keyword\ncomes at the middle of the page.\n.I Ptx\nproduces output in the form:\n.br\n.IP\n\\&.xx \"tail\" \"before keyword\" \"keyword and after\" \"head\"\n.LP\nwhere .xx may be an\n.I nroff\nor\n.IR troff (1)\nmacro\nfor user-defined formatting.\nThe\n.I before keyword\nand\n.I keyword and after\nfields incorporate as much of the line as will fit\naround the keyword when it is printed at the middle of the page.\n.I Tail\nand\n.I head,\nat least one of which is an empty string \"\",\nare wrapped-around pieces small enough to fit\nin the unused space at the opposite end of the line.\nWhen original text must be discarded, `/' marks the spot.\n.PP\nThe following options can be applied:\n.TP\n.BR \\-f\nFold upper and lower case letters for sorting.\n.TP \n.BR \\-t\nPrepare the output for the phototypesetter;\nthe default line length is 100 characters.\n.TP \n.BI \\-w \" n\"\nUse the next argument,\n.I n,\nas the width of the output line.\nThe default line length is 72 characters.\n.TP\n.BI \\-g \" n\"\nUse the next argument,\n.I n,\nas the number of characters to allow for each gap\namong the four parts of the line as finally printed.\nThe default gap is 3 characters.\n.TP \n.BR \\-o \" only\"\nUse as keywords only the words given in the \\fIonly\\fR file.\n.TP \n.BR \\-i \" ignore\"\nDo not use as keywords any words given in the\n.I\nignore\nfile.\nIf the \\fB\\-i\\fR and \\fB\\-o\\fR options are missing, use\n.I /usr/share/misc/eign\nas the \n.I\nignore\nfile.\n.TP \n.BR \\-b \" break\"\nUse the characters in the \n.I\nbreak\nfile to separate words.\nIn any case, tab, newline, and space characters are always used as break characters.\n.TP\n.BR \\-r\nTake any leading nonblank characters of each input line to\nbe a reference identifier (as to a page or chapter)\nseparate from the text of the line.\nAttach that identifier as a 5th field on each output line.\n.PP\nThe index for this manual was generated using\n.I ptx.\n.SH FILES\n/usr/bin/sort\n.br\n/usr/share/misc/eign\n.SH BUGS\nLine length counts do not account for overstriking or\nproportional spacing.\n.br\n"
  },
  {
    "path": "share/man/man1/pwd.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)pwd.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH PWD 1 \"April 29, 1985\"\n.UC 4\n.SH NAME\npwd \\- working directory name\n.SH SYNOPSIS\n.B pwd\n.SH DESCRIPTION\n.I Pwd\nprints the pathname of the working (current) directory.\n.SH \"SEE ALSO\"\ncd(1), csh(1), getwd(3)\n.SH BUGS\nIn\n.IR csh (1)\nthe command\n.I dirs\nis always faster (although it can give a different answer in the rare case\nthat the current directory or a containing directory was moved after\nthe shell descended into it).\n"
  },
  {
    "path": "share/man/man1/px.1",
    "content": ".TH PX 1 \"March 15, 1987\"\n.UC\n.SH NAME\npx \\- Pascal interpreter\n.SH SYNOPSIS\n.B px\n[ obj [ argument ... ] ]\n.SH DESCRIPTION\n.I Px\ninterprets the abstract machine code generated by\n.I pi.\nThe first argument is the file to be interpreted, and defaults\nto\n.IR obj \\|;\nremaining arguments are available to the Pascal program using the\nbuilt-ins\n.I argv\nand\n.I argc.\n.I Px\nis also invoked by\n.I pix\nwhen running `load and go'.\n.PP\nIf the program terminates abnormally an error message and a \ncontrol flow backtrace are printed.\nThe number of statements executed and total execution time\nare printed after normal termination.\nThe\n.B p\noption of\n.I pi\nsuppresses all of this except the message indicating the cause\nof abnormal termination.\n.SH FILES\n.ta 2i\nobj\tdefault object file\n.br\npmon.out\tprofile data file\n.SH \"SEE ALSO\"\nBerkeley Pascal User's Manual\n.br\npi(1), pix(1)\n.SH DIAGNOSTICS\nMost run-time error messages are self-explanatory.\nSome of the more unusual ones are:\n.HP 6\nReference to an inactive file\n.br\nA file other than\n.I input\nor\n.I output\nwas used before a call to\n.I reset\nor\n.I rewrite.\n.HP 6\nStatement count limit exceeded\n.br\nThe limit of 500,000 executed statements\n(which prevents excessive looping or recursion)\nhas been exceeded.\n.HP 6\nBad data found on integer read\n.br\n.ns\n.HP 6\nBad data found on real read\n.br\nUsually, non-numeric input was found for a number.\nFor reals, Pascal requires digits before and after the decimal\npoint so that numbers like `.1' or `21.' evoke the second diagnostic.\n.HP 6\npanic:\n.I  \"Some message\"\n.br\nIndicates a internal inconsistency detected in\n.I px\nprobably due to a Pascal system bug.\n.sh AUTHORS\nCharles B. Haley, William N. Joy, and Ken Thompson\n.SH BUGS\nCalls to the procedures\n.I dispose\nand\n.I linelimit\nare ignored.\n.PP\nPost-mortem traceback is not limited;\ninfinite recursion leads to almost infinite traceback.\n.PP\nBecause interrupts sometimes find the system in the middle of a\n.B procedure\nor\n.B function\nentry or exit,\nthe error backtrace on an interrupt is occasionally meaningless.\nThe current line is, however, always correct;\nonly the call backtrace and the name of the current routine may be lost.\n"
  },
  {
    "path": "share/man/man1/pxp.1",
    "content": ".\\\"\t@(#)pxp.1\t1.1 (2.11BSD) 1996/10/22\n.TH PXP 1 \"October 22, 1996\"\n.UC\n.SH NAME\npxp \\- Pascal execution profiler\n.SH SYNOPSIS\n.B pxp\n[\n.B  \\-acdefjnstuw_\n] [\n.B \\-23456789\n] [\n.B \\-z\n[ name ... ] ] name.p\n.SH DESCRIPTION\n.I Pxp\ncan be used to obtain execution profiles of Pascal programs or\nas a pretty-printer.\nTo produce an execution profile all that is necessary is to translate\nthe program specifying the\n.B z\noption to\n.I pi\nor\n.I pix,\nto execute the program,\nand to then issue the command\n.DT\n.PP\n\t\\fBpxp \\-z\\fP name.p\n.PP\nA reformatted listing is output if none of the\n.BR c ,\n.BR t ,\nor\n.B  z\noptions are specified;\nthus\n.PP\n\t\\fBpxp\\fP old.p > new.p\n.PP\nplaces a pretty-printed version of the program in `old.p' in the file `new.p'.\n.PP\nThe use of the following options of\n.I pxp\nis discussed in sections 2.6, 5.4, 5.5 and 5.10 of the\n.IR \"Berkeley Pascal User's Manual\" \".\"\n.TP 6\n.B  \\-\\^a\nPrint the bodies of all procedures and functions in the profile;\neven those which were never executed.\n.TP 6\n.B  \\-\\^c\nExtract profile data from the file\n.IR core .\n.TP 6\n.B  \\-\\^d\nInclude declaration parts in a profile.\n.TP 6\n.B  \\-\\^e\nEliminate\n.B include\ndirectives when reformatting a file;\nthe\n.B include\nis replaced by the reformatted contents of the specified\nfile.\n.TP 6\n.B  \\-\\^f\nFully parenthesize expressions.\n.TP 6\n.B  \\-\\^j\nLeft justify all procedures and functions.\n.TP 6\n.B  \\-\\^n\nEject a new page \nas each file is included;\nin profiles, print a blank line at the top of the page.\n.TP 6\n.B  \\-\\^s\nStrip comments from the input text.\n.TP 6\n.B  \\-\\^t\nPrint a table summarizing\n.B  procedure\nand\n.B  function\ncall counts.\n.TP 6\n.B  \\-\\^u\nCard image mode; only the first 72 characters of input lines\nare used.\n.TP 6\n.B  \\-\\^w\nSuppress warning diagnostics.\n.TP 6\n.B  \\-\\^z\nGenerate an execution profile.\nIf no\n.IR name \\|s,\nare given the profile is of the entire program.\nIf a list of names is given, then only any specified\n.BR procedure s\nor\n.BR function s\nand the contents of any specified\n.B include\nfiles will appear in the profile.\n.TP 6\n.B  \\-\\^\\_\nUnderline keywords.\n.TP 6\n.BI \\-\\^ d\nWith\n.I  d\na digit, 2 \\(<=\n.IR d \"\"\n\\(<= 9,\ncauses\n.I pxp\nto use\n.IR d \"\"\nspaces as the basic indenting unit.\nThe default is 4.\n.SH FILES\n.ta 2i\nname.p\tinput file\n.br\nname.i\tinclude file(s)\n.br\npmon.out\tprofile data\n.br\ncore\t\tprofile data source with\n.B  \\-c\n.br\n/usr/share/pascal/how_pxp\tinformation on basic usage\n.br\n.ne 8\n.SH \"SEE ALSO\"\nBerkeley Pascal User's Manual\n.br\npi(1),\npx(1)\n.ne 5\n.SH DIAGNOSTICS\nFor a basic explanation do\n.IP\n.DT\n.B\tpxp\n.PP\nError diagnostics include\n`No profile data in file'\nwith the\n.B c\noption if the\n.B z\noption was not enabled to\n.I pi;\n`Not a Pascal system core file'\nif the core is not from a\n.I px\nexecution;\n`Program and count data do not correspond'\nif the program was changed after compilation, before profiling;\nor if the wrong program is specified.\n.SH AUTHOR\nWilliam N. Joy\n.SH BUGS\nDoes not place multiple statements per line.\n"
  },
  {
    "path": "share/man/man1/pxref.1",
    "content": ".TH PXREF 1 \"March 15, 1987\"\n.UC\n.SH NAME\npxref \\- Pascal cross-reference program\n.SH SYNOPSIS\n.B pxref\n[\n.BR \\- \"\"\n]\nname\n.SH DESCRIPTION\n.I Pxref\nmakes a line numbered listing and a cross-reference of identifier usage\nfor the program in\n.I name.\nThe optional `\\fB\\-\\fP' argument suppresses the listing.\nThe keywords\n.B goto\nand\n.B label\nare treated as identifiers for the purpose of the cross-reference.\n.B Include\ndirectives are not processed, but cause the placement of an entry\nindexed by `#include' in the cross-reference.\n.SH \"SEE ALSO\"\nBerkeley Pascal User's Manual\n.SH AUTHOR\nNiklaus Wirth\n.SH BUGS\nIdentifiers are trimmed to 10 characters.\n"
  },
  {
    "path": "share/man/man1/quota.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)quota.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH QUOTA 1 \"April 29, 1985\"\n.UC 5\n.SH NAME\nquota \\- display disc usage and limits\n.SH SYNOPSIS\n.B quota\n[\n.B \\-qv\n] [\nuser\n]\n.SH DESCRIPTION\n.I Quota\ndisplays users' disc usage and limits. \nOnly the super-user may use the optional\n.I user\nargument to view the limits of users other than\nhimself.\n.PP\nThe\n.B \\-q\nflag prints a more terse message,\ncontaining only information\non file systems where usage is over quota.\n.PP\nIf a\n.B \\-v\nflag is supplied, \n.I quota\nwill also display user's quotas on file systems\nwhere no storage is allocated.\n.PP\n.I Quota\nreports only on file systems which have\ndisc quotas. \nIf \n.I quota\nexits with a non-zero status, one or more file\nsystems are over quota.\n.SH \"SEE ALSO\"\nquota(2), quotaon(8)\n"
  },
  {
    "path": "share/man/man1/ratfor.1",
    "content": ".\\\"\t@(#)ratfor.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH RATFOR 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nratfor \\- rational Fortran dialect\n.SH SYNOPSIS\n.B ratfor\n[ option ... ]\n[ filename ... ]\n.SH DESCRIPTION\n.I Ratfor\nconverts a rational dialect of Fortran into ordinary irrational Fortran.\n.I Ratfor\nprovides control flow constructs essentially identical to those in C:\n.TP\nstatement grouping:\n.nf\n{ statement; statement; statement }\n.TP\ndecision-making:\nif (condition) statement [ else statement ]\n.br\nswitch (integer value) {\n\tcase integer:\tstatement\n\t...\n\t[ default: ]\tstatement\n}\n.TP\nloops:\nwhile (condition) statement\nfor (expression; condition; expression) statement\ndo limits statement\nrepeat statement [ until (condition) ]\nbreak\nnext\n.LP\nand some syntactic sugar to make programs easier to read and write:\n.TP\nfree form input:\nmultiple statements/line; automatic continuation\n.TP\ncomments:\n# this is a comment\n.TP\ntranslation of relationals:\n>, >=, etc., become .GT., .GE., etc.\n.TP\nreturn (expression)\nreturns expression to caller from function\n.TP\ndefine:\ndefine name replacement\n.TP\ninclude:\ninclude filename\n.PP\n.fi\n.I Ratfor\nis best used with\n.IR f77 (1).\n.SH \"SEE ALSO\"\nf77(1)\n.br\nB. W. Kernighan and P. J. Plauger,\n.IR \"Software Tools\" ,\nAddison-Wesley, 1976.\n"
  },
  {
    "path": "share/man/man1/rcp.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)rcp.1c\t6.4 (Berkeley) 5/12/86\n.\\\"\n.TH RCP 1C \"May 12, 1986\"\n.UC 5\n.SH NAME\nrcp \\- remote file copy\n.SH SYNOPSIS\n.B rcp\n[\n.B \\-p\n] file1 file2\n.br\n.B rcp\n[\n.B \\-p\n] [\n.B \\-r\n] file ... directory\n.SH DESCRIPTION\n.I Rcp\ncopies files between machines.  Each\n.I file\nor\n.I directory\nargument is either a remote file name of the\nform ``rhost:path'', or a local file name (containing no `:' characters,\nor a `/' before any `:'s).\n.PP\nIf the\n.B \\-r\noption\nis specified and any of the source files are directories,\n.I rcp\ncopies each subtree rooted at that name; in this case\nthe destination must be a directory.\n.PP\nBy default, the mode and owner of\n.I file2\nare preserved if it already existed; otherwise the mode of the source file\nmodified by the\n.IR umask (2)\non the destination host is used.\nThe\n.B \\-p\noption causes\n.I rcp\nto attempt to preserve (duplicate) in its copies the modification\ntimes and modes of the source files, ignoring the\n.IR umask .\n.PP\nIf\n.I path\nis not a full path name, it is interpreted relative to\nyour login directory on \n.IR rhost .\nA \n.I path\non a remote host may be quoted (using \\e, \", or \\(aa)\nso that the metacharacters are interpreted remotely.\n.PP\n.I Rcp\ndoes not prompt for passwords; your current local user name\nmust exist on\n.I rhost\nand allow remote command execution via\n.IR rsh (1C).\n.PP\n.I Rcp\nhandles third party copies, where neither source nor target files\nare on the current machine.\nHostnames may also take the form ``rname@rhost'' to use\n.I rname\nrather than the current user name on the remote host.\nThe destination hostname may also take the form ``rhost.rname'' to\nsupport destination machines that are running 4.2BSD\nversions of\n.I rcp.\n.SH SEE ALSO\ncp(1), ftp(1C), rsh(1C), rlogin(1C)\n.SH BUGS\nDoesn't detect all cases where the target of a copy might\nbe a file in cases where only a directory should be legal.\n.br\nIs confused by any output generated by commands in a\n\\&.login, \\&.profile, or \\&.cshrc file on the remote host.\n"
  },
  {
    "path": "share/man/man1/rdist.1",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)rdist.1\t6.6.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH RDIST 1 \"October 22, 1996\"\n.UC 6\n.ad\n.SH NAME\nrdist \\- remote file distribution program\n.SH SYNOPSIS\n.B rdist\n[ \\-nqbRhivwy ]\n[ \\-f distfile ] [ \\-d var=value ] [ \\-m host ]\n[ name ... ]\n.PP\n.B rdist\n[ \\-nqbRhivwy ] -c name ... [login@]host[:dest]\n.SH DESCRIPTION\n.I Rdist\nis a program to maintain identical copies of files over multiple hosts. \nIt preserves the owner, group, mode, and mtime of files if possible and\ncan update programs that are executing.\n.I Rdist\nreads commands from\n.I distfile\nto direct the updating of files and/or directories.\nIf\n.I distfile\nis `\\-', the standard input is used.\nIf no\n.B \\-f\noption is present, the program looks first for `distfile',\nthen `Distfile' to use as the input.\nIf no names are specified on the command line,\n.I rdist\nwill update all of the files and directories listed in\n.IR distfile .\nOtherwise, the argument is taken to be the name of a file to be updated\nor the label of a command to execute. If label and file names conflict,\nit is assumed to be a label.\nThese may be used together to update specific files\nusing specific commands.\n.PP\nThe\n.B \\-c\noption forces\n.I rdist\nto interpret the remaining arguments as a small\n.IR distfile .\nThe equivalent distfile is as follows.\n.nf\n\n.ti +.5i\n( \\fIname\\fP ... ) -> [\\fIlogin\\fP@]\\fIhost\\fP\n.ti +1i\ninstall\t[\\fIdest\\fP] ;\n\n.fi\n.PP\nOther options:\n.TP\n.B \\-d\nDefine\n.I var\nto have\n.IR value .\nThe\n.B \\-d\noption is used to define or override variable definitions in the\n.IR distfile .\n.I Value\ncan be the empty string, one name, or a list of names surrounded by\nparentheses and separated by tabs and/or spaces.\n.TP\n.B \\-m\nLimit which machines are to be updated. Multiple\n.B -m\narguments can be given to limit updates to a subset of the hosts listed the\n.IR distfile .\n.TP\n.B \\-n\nPrint the commands without executing them. This option is\nuseful for debugging\n.IR distfile .\n.TP\n.B \\-q\nQuiet mode. Files that are being modified are normally\nprinted on standard output. The\n.B \\-q\noption suppresses this.\n.TP\n.B \\-R\nRemove extraneous files. If a directory is being updated, any files that exist\non the remote host that do not exist in the master directory are removed.\nThis is useful for maintaining truely identical copies of directories.\n.TP\n.B \\-h\nFollow symbolic links. Copy the file that the link points to rather than the\nlink itself.\n.TP\n.B \\-i\nIgnore unresolved links.\n.I Rdist\nwill normally try to maintain the link structure of files being transfered\nand warn the user if all the links cannot be found.\n.TP\n.B \\-v\nVerify that the files are up to date on all the hosts. Any files\nthat are out of date will be displayed but no files will be changed\nnor any mail sent.\n.TP\n.B \\-w\nWhole mode. The whole file name is appended to the destination directory\nname. Normally, only the last component of a name is used when renaming files.\nThis will preserve the directory structure of the files being\ncopied instead of flattening the directory structure. For example,\nrenaming a list of files such as ( dir1/f1 dir2/f2 ) to dir3 would create\nfiles dir3/dir1/f1 and dir3/dir2/f2 instead of dir3/f1 and dir3/f2.\n.TP\n.B \\-y\nYounger mode. Files are normally updated if their\n.I mtime\nand\n.I size\n(see\n.IR stat (2))\ndisagree. The\n.B \\-y\noption causes\n.I rdist\nnot to update files that are younger than the master copy.\nThis can be used\nto prevent newer copies on other hosts from being replaced.\nA warning message is printed for files which are newer than the master copy.\n.TP\n.B \\-b\nBinary comparison. Perform a binary comparison and update files if they differ\nrather than comparing dates and sizes.\n.PP\n.I Distfile\ncontains a sequence of entries that specify the files\nto be copied, the destination hosts, and what operations to perform\nto do the updating. Each entry has one of the following formats.\n.nf\n\n.in +.5i\n<variable name> `=' <name list>\n[ label: ] <source list> `\\->' <destination list> <command list>\n[ label: ] <source list> `::' <time_stamp file> <command list>\n.in\n\n.fi\nThe first format is used for defining variables.\nThe second format is used for distributing files to other hosts.\nThe third format is used for making lists of files that have been changed\nsince some given date.\nThe \\fIsource list\\fP specifies a\nlist of files and/or directories on the local host which are to be used\nas the master copy for distribution.\nThe \\fIdestination list\\fP is the list of hosts to which these files are to be\ncopied.  Each file in the source list is added to a list of changes\nif the file is out of date on the host which is being updated (second format) or\nthe file is newer than the time stamp file (third format).\n.PP\nLabels are optional. They are used to identify a command for partial updates.\n.PP\nNewlines, tabs, and blanks are only used as separators and are\notherwise ignored. Comments begin with `#' and end with a newline.\n.PP\nVariables to be expanded begin with `$' followed by one character or\na name enclosed in curly braces (see the examples at the end).\n.PP\nThe source and destination lists have the following format:\n.nf\n\n.ti +.5i\n<name>\nor\n.ti +.5i\n`(' <zero or more names separated by white-space> `)'\n\n.fi\nThe shell meta-characters `[', `]', `{', `}', `*', and `?'\nare recognized and expanded (on the local host only) in the same way as\n.IR csh (1).\nThey can be escaped with a backslash.\nThe `~' character is also expanded in the same way as\n.IR csh\nbut is expanded separately on the local and destination hosts.\nWhen the\n.B \\-w\noption is used with a file name that begins with `~', everything except the\nhome directory is appended to the destination name.\nFile names which do not begin with `/' or `~' use the destination user's\nhome directory as the root directory for the rest of the file name.\n.PP\nThe command list consists of zero or more commands of the following\nformat.\n.nf\n\n.in +.5i\n.ta \\w'install    'u +\\w'name list    'u\n`install'\t<options>\topt_dest_name `;'\n`notify'\t<name list>\t`;'\n`except'\t<name list>\t`;'\n`except_pat'\t<pattern list>\t`;'\n`special'\t<name list>\tstring `;'\n.in\n\n.fi\n.PP\nThe\n.I install\ncommand is used to copy out of date files and/or directories.\nEach source file is copied to each host in the destination list.\nDirectories are recursively copied in the same way.\n.I Opt_dest_name\nis an optional parameter to rename files.\nIf no\n.I install\ncommand appears in the command list or\nthe destination name is not specified,\nthe source file name is used.\nDirectories in the path name will be created if they\ndo not exist on the remote host.\nTo help prevent disasters, a non-empty directory on a target host will\nnever be replaced with a regular file or a symbolic link.\nHowever, under the `\\-R' option a non-empty directory will be removed\nif the corresponding filename is completely absent on the master host.\nThe\n.I options\nare `\\-R', `\\-h', `\\-i', `\\-v', `\\-w', `\\-y', and `\\-b'\nand have the same semantics as\noptions on the command line except they only apply to the files\nin the source list.\nThe login name used on the destination host is the same as the local host\nunless the destination name is of the format ``login@host\".\n.PP\nThe\n.I notify\ncommand is used to mail the list of files updated (and any errors\nthat may have occured) to the listed names.\nIf no `@' appears in the name, the destination host is appended to\nthe name\n(e.g., name1@host, name2@host, ...).\n.PP\nThe\n.I except\ncommand is used to update all of the files in the source list\n.B except\nfor the files listed in \\fIname list\\fP.\nThis is usually used to copy everything in a directory except certain files.\n.PP\nThe\n.I except_pat\ncommand is like the\n.I except\ncommand except that \\fIpattern list\\fP is a list of regular expressions\n(see\n.IR ed (1)\nfor details).\nIf one of the patterns matches some string within a file name, that file will\nbe ignored.\nNote that since `\\e' is a quote character, it must be doubled to become\npart of the regular expression.  Variables are expanded in \\fIpattern list\\fP\nbut not shell file pattern matching characters.  To include a `$', it\nmust be escaped with `\\e'.\n.PP\nThe\n.I special\ncommand is used to specify\n.IR sh (1)\ncommands that are to be executed on the\nremote host after the file in \\fIname list\\fP is updated or installed.\nIf the \\fIname list\\fP is omitted then the shell commands will be executed\nfor every file updated or installed.  The shell variable `FILE' is set\nto the current filename before executing the commands in\n.IR string .\n.I String\nstarts and ends with `\"' and can cross multiple lines in\n.I distfile.\nMultiple commands to the shell should be separated by `;'.\nCommands are executed in the user's home directory on the host\nbeing updated.\nThe\n.I special\ncommand can be used to rebuild private databases, etc.\nafter a program has been updated.\n.PP\nThe following is a small example.\n.nf\n\n.in +.5i\nHOSTS = ( matisse root@arpa)\n\nFILES = ( /bin /lib /usr/bin /usr/games\n\t/usr/include/{*.h,{stand,sys,vax*,pascal,machine}/*.h}\n\t/usr/lib /usr/man/man? /usr/ucb /usr/local/rdist )\n\nEXLIB = ( Mail.rc aliases aliases.dir aliases.pag crontab dshrc\n\tsendmail.cf sendmail.fc sendmail.hf sendmail.st uucp vfont )\n\n${FILES} -> ${HOSTS}\n\tinstall -R ;\n\texcept /usr/lib/${EXLIB} ;\n\texcept /usr/games/lib ;\n\tspecial /usr/sbin/sendmail \"/usr/sbin/sendmail -bz\" ;\n\nsrcs:\n/usr/src/bin -> arpa\n\texcept_pat ( \\e\\e.o\\e$ /SCCS\\e$ ) ;\n\nIMAGEN = (ips dviimp catdvi)\n\nimagen:\n/usr/local/${IMAGEN} -> arpa\n\tinstall /usr/local/lib ;\n\tnotify ralph ;\n\n${FILES} :: stamp.cory\n\tnotify root@cory ;\n.in\n\n.fi\n.SH FILES\n.nf\n.ta \\w'/tmp/rdist*    'u\ndistfile\tinput command file\n/tmp/rdist*\ttemporary file for update lists\n.fi\n.SH \"SEE ALSO\"\nsh(1), csh(1), stat(2)\n.SH DIAGNOSTICS\nA complaint about mismatch of rdist version numbers may really stem\nfrom some problem with starting your shell, e.g., you are in too many groups.\n.SH BUGS\nSource files must reside on the local host where rdist is executed.\n.PP\nThere is no easy way to have a special command executed after all files\nin a directory have been updated.\n.PP\nVariable expansion only works for name lists; there should be a general macro\nfacility.\n.PP\n.I Rdist\naborts on files which have a negative mtime (before Jan 1, 1970).\n.PP\nThere should be a `force' option to allow replacement of non-empty directories\nby regular files or symlinks.  A means of updating file modes and owners\nof otherwise identical files is also needed.\n"
  },
  {
    "path": "share/man/man1/refer.1",
    "content": ".\\\"\t@(#)refer.1\t6.2.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH REFER 1 \"October 22, 1996\"\n.AT 3\n.SH NAME\nrefer \\- find and insert literature references in documents\n.SH SYNOPSIS\n.B refer\n[\n.B \\-a\n] [\n.B \\-b\n] [\n.B \\-c\n] [\n.B \\-e\n] [\n.BI \\-f n\n] [\n.BI \\-k x\n] [\n.BI \\-l m,n\n] [\n.B \\-n\n] [\n.B \\-p\nbib\n] [\n.BI \\-s keys\n] [\n.BI \\-B l.m\n] [\n.B \\-P\n] [\n.B \\-S\n] [ file ... ]\n.SH DESCRIPTION\n.I Refer\nis a preprocessor for\n.I nroff\nor\n.IR troff (1)\nthat finds and formats references for footnotes or endnotes.\nIt is also the base for a series of programs designed to\nindex, search, sort, and print stand-alone bibliographies,\nor other data entered in the appropriate form.\n.PP\nGiven an incomplete citation with sufficiently precise keywords,\n.I refer\nwill search a bibliographic database for references\ncontaining these keywords anywhere in the title, author, journal, etc.\nThe input file (or standard input)\nis copied to standard output,\nexcept for lines between .[ and .] delimiters,\nwhich are assumed to contain keywords,\nand are replaced by information from the bibliographic database.\nThe user may also search different databases,\noverride particular fields, or add new fields.\nThe reference data, from whatever source, are assigned to a set of\n.I troff\nstrings.\nMacro packages such as\n.IR ms (7)\nprint the finished reference text from these strings.\nBy default references are flagged by footnote numbers.\n.PP\nThe following options are available:\n.TP 6\n.BI \\-a n\nReverse the first\n.I n\nauthor names (Jones, J. A. instead of J. A. Jones).\nIf\n.I n\nis omitted all author names are reversed.\n.ns\n.TP\n.B \\-b\nBare mode: do not put any flags in text (neither numbers nor labels).\n.ns\n.TP\n.BI \\-c keys\nCapitalize (with C\\s-2APS\\s0 S\\s-2MALL\\s+2 C\\s-2APS\\s0)\nthe fields whose key-letters are in\n.IR keys .\n.ns\n.TP\n.B \\-e\nInstead of leaving the references where encountered,\naccumulate them until a sequence of the form\n.nf\n\t.[\n\t$LIST$\n\t.]\n.fi\nis encountered, and then write out all references collected so far.\nCollapse references to same source.\n.ns\n.TP\n.BI \\-f n\nSet the footnote number to\n.I n\ninstead of the default of 1 (one).\nWith labels rather than numbers,\nthis flag is a no-op.\n.ns\n.TP\n.BI \\-k x\nInstead of numbering references, use labels as specified in a\nreference data line beginning\n.I %x;\nby default\n.I x\nis\n.B L.\n.ns\n.TP\n.BI \\-l m , n\nInstead of numbering references, use labels made from\nthe senior author's last name and the year of publication.\nOnly the first\n.I m\nletters of the last name\nand the last\n.I n\ndigits of the date are used.\nIf either\n.I m\nor\n.I n\nis omitted the entire name or date respectively is used.\n.ns\n.TP\n.B \\-n\nDo not search the default file /usr/dict/papers/Ind.\nIf there is a REFER environment variable,\nthe specified file will be searched instead of the default file;\nin this case the\n.B \\-n\nflag has no effect.\n.ns\n.TP\n.BI \\-p \\0bib\nTake the next argument\n.I bib\nas a file of references to be searched.\nThe default file is searched last.\n.ns\n.TP\n.BI \\-s keys\nSort references by fields whose key-letters are in the\n.I keys\nstring;\npermute reference numbers in text accordingly.\nImplies\n.BR \\-e .\nThe key-letters in\n.I keys\nmay be followed by a number to indicate how many such fields\nare used, with\n.B +\ntaken as a very large number.\nThe default is\n.B AD\nwhich sorts on the senior author and then date; to sort, for example,\non all authors and then title, use\n.BR -sA+T .\n.ns\n.TP\n.BI \\-B l.m\nBibliography mode.\nTake a file composed of records separated by blank lines,\nand turn them into\n.I troff\ninput.\nLabel\n.I l\nwill be turned into the macro\n.I .m\nwith\n.I l\ndefaulting to\n.B %X\nand\n.I .m\ndefaulting to\n.B .AP\n(annotation paragraph).\n.ns\n.TP\n.B \\-P\nPlace punctuation marks .,:;?! after the reference signal,\nrather than before.\n(Periods and commas used to be done with strings.)\n.ns\n.TP\n.B \\-S\nProduce references in the Natural or Social Science format.\n.PP\nTo use your own references,\nput them in the format described below.\nThey can be searched more rapidly by running\n.IR indxbib (1)\non them before using\n.I refer;\nfailure to index results in a linear search.\nWhen\n.I refer\nis used with the\n.I eqn,\n.I neqn\nor\n.I tbl\npreprocessors\n.I refer\nshould be first, to minimize the volume\nof data passed through pipes.\n.PP\nThe\n.I refer\npreprocessor and associated programs\nexpect input from a file of references\ncomposed of records separated by blank lines.\nA record is a set of lines (fields),\neach containing one kind of information.\nFields start on a line beginning with a ``%'',\nfollowed by a key-letter, then a blank,\nand finally the contents of the field,\nand continue until the next line starting with ``%''.\nThe output ordering and formatting of fields\nis controlled by the macros specified for\n.I nroff/troff\n(for footnotes and endnotes) or\n.I roffbib\n(for stand-alone bibliographies).\nFor a list of the most common key-letters\nand their corresponding fields, see\n.IR addbib (1).\nAn example of a\n.I refer\nentry is given below.\n.SH EXAMPLE\n.PP\n.nf\n%A\tM. E. Lesk\n%T\tSome Applications of Inverted Indexes on the \\s-1UNIX\\s0 System\n%B\t\\s-1UNIX\\s0 Programmer's Manual\n%V\t2b\n%I\tBell Laboratories\n%C\tMurray Hill, NJ\n%D\t1978\n.fi\n.SH FILES\n.ta \\w'/usr/dict/papers\\0\\0'u\n/usr/dict/papers\tdirectory of default publication lists\n.br\n/usr/libexec/refer  \tdirectory of companion programs\n.SH SEE ALSO\naddbib(1), sortbib(1), roffbib(1), indxbib(1), lookbib(1)\n.SH AUTHOR\nMike Lesk\n.SH BUGS\nBlank spaces at the end of lines in bibliography fields\nwill cause the records to sort and reverse incorrectly.\nSorting large numbers of references causes a core dump.\n"
  },
  {
    "path": "share/man/man1/rev.1",
    "content": ".\\\"\t@(#)rev.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH REV 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nrev \\- reverse lines of a file\n.SH SYNOPSIS\n.B rev\n[ file ] ...\n.SH DESCRIPTION\n.I Rev\ncopies the named files to the standard output,\nreversing the order of characters in every line.\nIf no file is specified, the standard input is copied.\n"
  },
  {
    "path": "share/man/man1/rlogin.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)rlogin.1c\t6.8 (Berkeley) 5/12/86\n.\\\"\n.TH RLOGIN 1C \"May 12, 1986\"\n.UC 5\n.SH NAME\nrlogin \\- remote login\n.SH SYNOPSIS\n.B rlogin\nrhost [\n\\fB\\-e\\fR\\fI\\|c\\fR\n] [\n.B \\-8\n] [\n.B \\-L\n] [\n.B \\-l\nusername ]\n.br\nrhost [\n\\fB\\-e\\fR\\fIc\\fR\n] [\n.B \\-8\n] [\n.B \\-L\n] [\n.B \\-l\nusername ]\n.SH DESCRIPTION\n.I Rlogin\nconnects your terminal on the current local host system\n.I lhost\nto the remote host system\n.I rhost.\n.PP\nEach host has a file\n.I /etc/hosts.equiv\nwhich contains a list of \\fIrhost\\fR's with which it shares account names.\n(The host names must be the standard names as described in\n.IR rsh (1C).)\nWhen you\n.I rlogin\nas the same user on an equivalent host, you don't need\nto give a password.\nEach user may also have a private equivalence list in a file \\&.rhosts\nin his login directory.  Each line in this file should contain an \\fIrhost\\fP\nand a \\fIusername\\fP separated by a space, giving additional cases\nwhere logins without passwords are to be permitted.\nIf the originating user is not equivalent to the remote user, then\na login and password will be prompted for on the remote machine as in\n.IR login (1).\nTo avoid some security problems, the \\&.rhosts file must be owned by\neither the remote user or root.\n.PP\nThe remote terminal type is the same as your local\nterminal type (as given in your environment TERM variable).\nThe terminal or window size is also copied to the remote system\nif the server supports the option,\nand changes in size are reflected as well.\nAll echoing takes place at the remote site, so that (except for\ndelays) the rlogin is transparent.  Flow control via ^S and ^Q and\nflushing of input and output on interrupts are handled properly.\nThe optional argument\n.B \\-8\nallows an eight-bit input data path at all times;\notherwise parity bits are stripped except when the remote side's\nstop and start characters are other than ^S/^Q.\nThe argument\n.B \\-L\nallows the rlogin session to be run in litout mode.\nA line of the form ``~.'' disconnects from the remote host, where\n``~'' is the escape character.\nSimilarly, the line ``~^Z'' (where ^Z, control-Z, is the suspend character)\nwill suspend the rlogin session.\nSubstitution of the delayed-suspend character (normally ^Y)\nfor the suspend character suspends the send portion of the rlogin,\nbut allows output from the remote system.\nA different escape character may\nbe specified by the\n.B \\-e\noption.\nThere is no space separating this option flag and the argument\ncharacter.\n.SH SEE ALSO\nrsh(1C)\n.SH FILES\n/usr/hosts/*\t\tfor \\fIrhost\\fP version of the command\n.SH BUGS\nMore of the environment should be propagated.\n"
  },
  {
    "path": "share/man/man1/rm.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)rm.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH RM 1 \"April 29, 1985\"\n.UC 4\n.SH NAME\nrm, rmdir  \\- remove (unlink) files or directories\n.SH SYNOPSIS\n.B rm\n[\n.B \\-f\n] [\n.B \\-r\n] [\n.B \\-i\n] [\n.B \\-\n] file ...\n.PP\n.B rmdir\ndir ...\n.PP\n.SH DESCRIPTION\n.I Rm\nremoves the entries for one or more files from a directory.\nIf an entry was the last link to the file, the file is destroyed.\nRemoval of a file requires write permission in its directory,\nbut neither read nor write permission on the file itself.\n.PP\nIf a file has no write permission and the standard input is a terminal,\nits permissions are printed and a line is read from the standard input.\nIf that line begins with `y' the file is deleted, otherwise the file remains.\nNo questions are asked and no errors are reported when the\n.B \\-f\n(force) option is given.\n.PP\nIf a designated file is a directory,\nan error comment is printed unless the optional argument\n.B \\-r\nhas been used.  In that case,\n.I rm\nrecursively deletes the entire contents of the specified directory,\nand the directory itself.\n.PP\nIf the\n.B \\-i\n(interactive) option is in effect,\n.I rm\nasks whether to delete each file, and, under\n.BR \\-r ,\nwhether to examine each directory.\n.PP\nThe null option\n.B \\-\nindicates that all the arguments following it are to be treated as\nfile names.  This allows the specification of file names starting with\na minus.\n.PP\n.I Rmdir\nremoves entries for the named directories, which must be empty.\n.SH \"SEE ALSO\"\nrm(1), unlink(2), rmdir(2)\n"
  },
  {
    "path": "share/man/man1/rmail.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)rmail.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH RMAIL 1 \"April 29, 1985\"\n.UC 5\n.SH NAME\nrmail \\- handle remote mail received via uucp\n.SH SYNOPSIS\n.B rmail\nuser ...\n.SH DESCRIPTION\n.I Rmail\ninterprets incoming mail received via\n.IR uucp (1C),\ncollapsing ``From'' lines in the form generated\nby \n.IR binmail (1)\ninto a single line of the form ``return-path!sender'',\nand passing the processed mail on to\n.IR sendmail (8).\n.PP\n.I Rmail\nis explicitly designed for use with \n.I uucp\nand\n.IR sendmail .\n.SH \"SEE ALSO\"\nbinmail(1),\nuucp(1C),\nsendmail(8)\n.SH BUGS\n.I Rmail\nshould not reside in /bin.\n"
  },
  {
    "path": "share/man/man1/rmdir.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)rmdir.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH RMDIR 1 \"April 29, 1985\"\n.UC 5\n.SH NAME\nrmdir, rm  \\- remove (unlink) directories or files\n.SH SYNOPSIS\n.B rmdir\ndir ...\n.PP\n.B rm\n[\n.B \\-f\n] [\n.B \\-r\n] [\n.B \\-i\n] [\n.B \\-\n] file ...\n.PP\n.SH DESCRIPTION\n.PP\n.I Rmdir\nremoves entries for the named directories, which must be empty.\n.PP\n.I Rm\nremoves the entries for one or more files from a directory.\nIf an entry was the last link to the file, the file is destroyed.\nRemoval of a file requires write permission in its directory,\nbut neither read nor write permission on the file itself.\n.PP\nIf a file has no write permission and the standard input is a terminal,\nits permissions are printed and a line is read from the standard input.\nIf that line begins with `y' the file is deleted, otherwise the file remains.\nNo questions are asked and no errors are reported when the\n.B \\-f\n(force) option is given.\n.PP\nIf a designated file is a directory,\nan error comment is printed unless the optional argument\n.B \\-r\nhas been used.  In that case,\n.I rm\nrecursively deletes the entire contents of the specified directory,\nand the directory itself.\n.PP\nIf the\n.B \\-i\n(interactive) option is in effect,\n.I rm\nasks whether to delete each file, and, under\n.BR \\-r ,\nwhether to examine each directory.\n.PP\nThe null option\n.B \\-\nindicates that all the arguments following it are to be treated as\nfile names.  This allows the specification of file names starting with\na minus.\n.SH \"SEE ALSO\"\nrm(1), unlink(2), rmdir(2)\n"
  },
  {
    "path": "share/man/man1/roffbib.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)roffbib.1\t6.2.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH ROFFBIB 1 \"October 22, 1996\"\n.UC 5\n.SH NAME\nroffbib \\- run off bibliographic database\n.SH SYNOPSIS\n.B roffbib\n[\n.B \\-e\n] [\n.B \\-h\n] [\n.B \\-n\n] [\n.B \\-o\n] [\n.B \\-r\n] [\n.B \\-s\n] [\n.BI \\-T term\n] [\n.B \\-x\n] [\n.B \\-m\n.I mac\n] [\n.B \\-V\n] [\n.B \\-Q\n] [ file ... ]\n.SH DESCRIPTION\n.I Roffbib\nprints out all records in a bibliographic database,\nin bibliography format rather than as footnotes or endnotes.\nGenerally it is used in conjunction with\n.IR sortbib :\n.LP\n.RS\nsortbib  database | roffbib\n.RE\n.LP\n.I Roffbib\naccepts most of the options understood by\n.IR nroff (1),\nmost importantly the\n.B \\-T\nflag to specify terminal type.\n.PP\nIf abstracts or comments are entered following the %X field key,\n.I roffbib\nwill format them into paragraphs for an annotated bibliography.\nSeveral %X fields may be given if several\nannotation paragraphs are desired.\nThe\n.B \\-x\nflag will suppress the printing of these abstracts.\n.PP\nA user-defined set of macros\nmay be specified after the\n.B \\-m\noption.\nThere should be a space between the\n.B \\-m\nand the macro filename.\nThis set of macros will replace the ones\ndefined in /usr/share/tmac/tmac.bib.\nThe\n.B \\-V\nflag will send output to the Versatec; the\n.B \\-Q\nflag will queue output for the phototypesetter.\n.PP\nFour command-line registers control formatting style\nof the bibliography, much like the number registers of\n.IR ms (7).\nThe command-line argument\n.BR \\-r N1\nwill number\nthe references starting at one (1).\nThe flag\n.BR \\-r V2\nwill double space the biblio\\%graphy,\nwhile\n.BR \\-r V1\nwill double space references\nbut single space annotation paragraphs.\nThe line length can be changed from the default 6.5 inches\nto 6 inches with the\n.BR \\-r L6i\nargument,\nand the page offset can be set from the default of 0\nto one inch by specifying\n.BR \\-r O1i\n(capital O, not zero).\nNote: with the\n.B \\-V\nand\n.B \\-Q\nflags\nthe default page offset is already one inch.\n.SH FILES\n.ta \\w'/usr/share/tmac/tmac.bib\\0\\0'u\n.nf\n/usr/share/tmac/tmac.bib\tfile of macros used by \\fInroff/troff\\fP\n.fi\n.SH SEE ALSO\nrefer(1), addbib(1), sortbib(1), indxbib(1), lookbib(1)\n.SH BUGS\nUsers have to rewrite macros\nto create customized formats.\n"
  },
  {
    "path": "share/man/man1/rsh.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)rsh.1c\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH RSH 1C \"April 29, 1985\"\n.UC 5\n.SH NAME\nrsh \\- remote shell\n.SH SYNOPSIS\n.B rsh\nhost\n[\n.B \\-l\nusername\n] [\n.B \\-n\n] command\n.br\nhost\n[\n.B \\-l\nusername\n] [\n.B \\-n\n] command\n.SH DESCRIPTION\n.I Rsh\nconnects to the specified\n.I host,\nand executes the specified \\fIcommand\\fR.\n.I Rsh\ncopies its standard input to the remote command, the standard\noutput of the remote command to its standard output, and the\nstandard error of the remote command to its standard error.\nInterrupt, quit and terminate signals are propagated to the remote\ncommand; \\fIrsh\\fP normally terminates when the remote command does.\n.PP\nThe remote username used is the same as your local username,\nunless you specify a different remote name with the\n.B \\-l\noption.\nThis remote name must be equivalent (in the sense of\n.IR rlogin (1C))\nto the originating account; no provision\nis made for specifying a password with a command.\n.PP\nIf you omit\n.I command,\nthen instead of executing a single command, you will be logged in\non the remote host using\n.IR rlogin (1C).\n.PP\nShell metacharacters which are not quoted are interpreted\non local machine, while quoted metacharacters are interpreted on\nthe remote machine.\nThus the command\n.PP\n\\ \\ \\ rsh otherhost cat remotefile >> localfile\n.PP\nappends the remote file\n.I remotefile\nto the localfile\n.I localfile,\nwhile\n.PP\n\\ \\ \\ rsh otherhost cat remotefile \">>\" otherremotefile\n.PP\nappends\n.I remotefile\nto\n.I otherremotefile.\n.PP\nHost names are given in the file /etc/hosts.  Each host\nhas one standard name (the first name given in the file), which\nis rather long and unambiguous, and optionally one or more nicknames.\nThe host names for local machines are also commands in the directory\n/usr/hosts; if you put this directory in your search path\nthen the\n.B rsh\ncan be omitted.\n.SH FILES\n.ta 2i\n/etc/hosts\n.br\n/usr/hosts/*\n.DT\n.SH SEE ALSO\nrlogin(1C)\n.SH BUGS\nIf you are using\n.IR csh (1)\nand put a\n.IR rsh (1C)\nin the background without redirecting its input\naway from the terminal, it will block even if no reads\nare posted by the remote command.  If no input is desired\nyou should redirect the input of\n.I rsh\nto /dev/null using the\n.B \\-n\noption.\n.PP\nYou cannot run an interactive command\n(like\n.IR rogue (6)\nor\n.IR vi (1));\nuse\n.IR rlogin (1C).\n.PP\nStop signals stop the local \\fIrsh\\fP process only; this is arguably\nwrong, but currently hard to fix for reasons too complicated to\nexplain here.\n"
  },
  {
    "path": "share/man/man1/ruptime.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ruptime.1c\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH RUPTIME 1C \"April 29, 1985\"\n.UC 5\n.SH NAME\nruptime \\- show host status of local machines\n.SH SYNOPSIS\n.B ruptime\n[\n.B \\-a\n] [\n.B \\-r\n] [\n.B \\-l\n] [\n.B \\-t\n] [\n.B \\-u\n]\n.SH DESCRIPTION\n.I Ruptime\ngives a status line like\n.I uptime\nfor each machine on the local network;\nthese are formed from packets broadcast by each host\non the network once a minute.\n.PP\nMachines for which no\nstatus report has been received for 11 minutes are shown as being down.\n.PP\nUsers idle an hour or more are not counted unless the\n.B \\-a\nflag is given.\n.PP\nNormally, the listing is sorted by host name.\nThe\n.B \\-l ,\n.B \\-t ,\nand\n.B \\-u\nflags specify sorting by\nload average,\nuptime,\nand number of users, respectively.\nThe\n.B \\-r\nflag reverses the sort order.\n.SH FILES\n.DT\n/usr/spool/rwho/whod.*\tdata files\n.SH SEE ALSO\nrwho(1C)\n"
  },
  {
    "path": "share/man/man1/rwho.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)rwho.1c\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH RWHO 1C \"April 29, 1985\"\n.UC 5\n.SH NAME\nrwho \\- who's logged in on local machines\n.SH SYNOPSIS\n.B rwho\n[\n.B \\-a\n]\n.SH DESCRIPTION\nThe\n.I rwho\ncommand produces output similar to\n.I who,\nbut for all machines on the local network.\nIf no report has been\nreceived from a machine for 5 minutes then\n.I rwho\nassumes the machine is down, and does not report users last known\nto be logged into that machine.\n.PP\nIf a users hasn't typed to the system for a minute or more, then\n.I rwho\nreports this idle time.  If a user hasn't typed to the system for\nan hour or more, then\nthe user will be omitted from the output of\n.I rwho\nunless the\n.B \\-a\nflag is given.\n.SH FILES\n/usr/spool/rwho/whod.*\tinformation about other machines\n.SH SEE ALSO\nruptime(1C),\nrwhod(8C)\n.SH BUGS\nThis is unwieldy when the number of machines\non the local net is large.\n"
  },
  {
    "path": "share/man/man1/sccs.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)sccs.1\t2.5 (Berkeley) 5/12/86\n.\\\"\n.TH SCCS 1 \"May 12, 1986\"\n.UC 5\n.SH NAME\nsccs \\- front end for the \\s-1SCCS\\s0 subsystem\n.SH SYNOPSIS\n.B sccs\n[\n.B \\-r\n] [\n.BI \\-d path\n] [\n.BI \\-p path\n] command [ flags ] [ args ]\n.SH DESCRIPTION\n.I Sccs\nis a front end\nto the\n.SM SCCS\nprograms\nthat helps them mesh more cleanly\nwith the rest of UNIX.\nIt also includes the capability to run\n``set user id'' to another user\nto provide additional protection.\n.PP\nBasically,\n.I sccs\nruns the\n.I command\nwith the specified\n.I flags\nand\n.I args.\nEach\nargument\nis normally modified to be prepended\nwith ``SCCS/s.''.\n.PP\nFlags to be interpreted by the\n.I sccs\nprogram must be before the\n.I command\nargument.\nFlags to be passed to the actual\n.SM SCCS\nprogram\nmust come after the\n.I command\nargument.\nThese flags are specific to the command\nand are discussed in the documentation for that command.\n.PP\nBesides the usual\n.SM SCCS\ncommands,\nseveral ``pseudo-commands'' can be issued.\nThese are:\n.IP edit 1i\nEquivalent to ``get \\-e''.\n.IP delget\nPerform a delta on the named files\nand then get new versions.\nThe new versions will have id keywords expanded,\nand will not be editable.\nThe \\-m, \\-p, \\-r, \\-s, and \\-y flags\nwill be passed to delta,\nand the \\-b, \\-c, \\-e, \\-i, \\-k, \\-l, \\-s, and \\-x flags\nwill be passed to get.\n.IP deledit\nEquivalent to ``delget'' except that the\n``get'' phase includes the ``\\-e'' flag.\nThis option is useful for making a ``checkpoint''\nof your current editing phase.\nThe same flags will be passed to delta\nas described above,\nand all the flags listed for ``get''\nabove except \\-e and \\-k\nare passed to ``edit''.\n.IP create\nCreates an\n.SM SCCS\nfile,\ntaking the initial contents from the file of the same name.\nAny flags to ``admin'' are accepted.\nIf the creation is successful,\nthe files are renamed with a comma on the front.\nThese should be removed when you are convinced that\nthe\n.SM SCCS\nfiles have been created successfully.\n.IP fix\nMust be followed by a\n.B \\-r\nflag.\nThis command essentially removes the named delta,\nbut leaves you with a copy of the delta\nwith the changes that were in it.\nIt is useful for fixing small compiler bugs, etc.\nSince it doesn't leave audit trails,\nit should be used carefully.\n.IP clean\nThis routine removes everything from the current directory\nthat can be recreated from SCCS files.\nIt will not remove any files being edited.\nIf the\n.B \\-b\nflag is given, branches are ignored in the determination\nof whether they are being edited;\nthis is dangerous if you are keeping the branches in the\nsame directory.\n.IP unedit\nThis is the opposite of an ``edit''\nor a ``get \\-e''.\nIt should be used with extreme caution,\nsince any changes you made since the get\nwill be irretrievably lost.\n.IP info\nGives a listing of all files being edited.\nIf the\n.B \\-b\nflag is given,\nbranches (i.e.,\n\\s-1SID\\s0's with two or fewer components)\nare ignored.\nIf the\n.B \\-u\nflag is given\n(with an optional argument)\nthen only files being edited by you\n(or the named user)\nare listed.\n.IP check\nLike ``info''\nexcept that nothing is printed if nothing is being edited,\nand a non-zero exit status is returned if anything\nis being edited.\nThe intent is to have this included in an ``install''\nentry in a makefile\nto insure that everything is included into the\n.SM SCCS\nfile\nbefore a version is installed.\n.IP tell\nGives a newline-separated list\nof the files being edited\non the standard output.\nTakes the\n.B \\-b\nand\n.B \\-u\nflags like \n``info'' and ``check''.\n.IP diffs\nGives a ``diff'' listing between the current version of the\nprogram(s) you have out for editing and the versions\nin\n.SM SCCS\nformat.\nThe\n.B \\-r,\n.B \\-c,\n.B \\-i,\n.B \\-x,\nand\n.B \\-t\nflags are passed to\n.I get\\c\n; the\n.B \\-l,\n.B \\-s,\n.B \\-e,\n.B \\-f,\n.B \\-h,\nand\n.B \\-b\noptions are passed to\n.I diff.\nThe\n.B \\-C\nflag is passed to\n.I diff\nas\n.B \\-c.\n.IP print\nThis command prints out verbose information\nabout the named files.\n.PP\nThe\n.B \\-r\nflag runs\n.I sccs\nas the real user\nrather than as whatever effective user\n.I sccs\nis ``set user id'' to.\nThe\n.B \\-d\nflag gives a root directory for the\n.SM SCCS\nfiles.\nThe default is the current directory.\nThe\n.B \\-p\nflag defines the pathname of the directory\nin which the\n.SM SCCS\nfiles will be found;\n``SCCS'' is the default.\nThe\n.B \\-p\nflag differs from the\n.B \\-d\nflag in that the\n.B \\-d\nargument is prepended to the entire pathname\nand the\n.B \\-p\nargument is inserted before the final component of the\npathname.\nFor example,\n``sccs \\-d/x \\-py get a/b''\nwill convert to\n``get /x/a/y/s.b''.\nThe intent here is to create aliases such as\n``alias syssccs sccs -d/usr/src''\nwhich will be used as\n``syssccs get cmd/who.c''.\nAlso, if the environment variable\nPROJECT\nis set,\nits value is used to determine the\n.B \\-d flag.\nIf it begins with a slash,\nit is taken directly;\notherwise,\nthe home directory of a user of that name\nis examined for a subdirectory ``src'' or ``source''.\nIf such a directory is found,\nit is used.\n.PP\nCertain commands (such as\n.IR admin )\ncannot be run ``set user id'' by all users,\nsince this would allow anyone to change the authorizations.\nThese commands are always run as the real user.\n.SH EXAMPLES\n.de BX\n.PP\n.nf\n.in +0.5i\n..\n.de EX\n.fi\n.PP\n..\nTo get a file for editing,\nedit it,\nand produce a new delta:\n.BX\nsccs get \\-e file.c\nex file.c\nsccs delta file.c\n.EX\nTo get a file from another directory:\n.BX\nsccs \\-p/usr/src/sccs/s. get cc.c\n.EX\nor\n.BX\nsccs get /usr/src/sccs/s.cc.c\n.EX\nTo make a delta of a large number of files\nin the current directory:\n.BX\nsccs delta *.c\n.EX\nTo get a list of files being edited that are not on branches:\n.BX\nsccs info \\-b\n.EX\nTo delta everything being edited by you:\n.BX\nsccs delta \\`sccs tell \\-u\\`\n.EX\nIn a makefile, to get source files\nfrom an\n.SM SCCS\nfile if it does not already exist:\n.BX\nSRCS = <list of source files>\n$(SRCS):\n\tsccs get $(REL) $@\n.EX\n.SH \"SEE ALSO\"\nadmin(SCCS),\nchghist(SCCS),\ncomb(SCCS),\ndelta(SCCS),\nget(SCCS),\nhelp(SCCS),\nprt(SCCS),\nrmdel(SCCS),\nsccsdiff(SCCS),\nwhat(SCCS)\n.br\nEric Allman,\n.ul\nAn Introduction to the Source Code Control System\n.SH BUGS\nIt should be able to take directory arguments on pseudo-commands\nlike the\n.SM SCCS\ncommands do.\n"
  },
  {
    "path": "share/man/man1/script.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)script.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH SCRIPT 1 \"April 29, 1985\"\n.UC 4\n.SH NAME\nscript \\- make typescript of terminal session\n.SH SYNOPSIS\n.B script\n[\n.B \\-a\n] [ file ]\n.SH DESCRIPTION\n.I Script\nmakes a typescript of everything printed on your terminal.\nThe typescript is written to \n.IR file ,\nor appended to\n.IR file\nif the\n.B \\-a\noption is given.\nIt can be sent to the line printer later with\n.IR lpr .\nIf no file name is given, the typescript\nis saved in the file\n.IR typescript .\n.PP\nThe script ends when the forked shell exits.\n.PP\nThis program is useful when using a crt and a hard-copy\nrecord of the dialog is desired, as for a student handing\nin a program that was developed on a crt when hard-copy\nterminals are in short supply.\n.SH BUGS\n.I Script\nplaces \n.B everything\nin the log file.  This is not what the naive user expects.\n"
  },
  {
    "path": "share/man/man1/sed.1",
    "content": ".\\\"\t@(#)sed.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH SED 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nsed \\- stream editor\n.SH SYNOPSIS\n.B sed\n[\n.B \\-n\n]\n[\n.B \\-e\nscript ] [\n.B \\-f\nsfile ] [ file ] ...\n.SH DESCRIPTION\n.I Sed\ncopies the named\n.I files\n(standard input default) to the standard output,\nedited according to a script of commands.\nThe\n.B \\-f\noption causes the script to be taken from file\n.IR sfile ;\nthese options accumulate.\nIf there is just one\n.B \\-e\noption and no\n.BR \\-f 's,\nthe flag\n.B \\-e\nmay be omitted.\nThe\n.B \\-n\noption suppresses the default output.\n.PP\nA script consists of editing commands, one per line,\nof the following form:\n.IP\n[address [, address] ] function [arguments]\n.PP\nIn normal operation\n.I sed\ncyclically copies a line of input into a\n.I pattern space\n(unless there is something left after\na `D' command),\napplies in sequence\nall commands whose\n.I addresses\nselect that pattern space,\nand at the end of the script copies the pattern space\nto the standard output (except under\n.BR \\-n )\nand deletes the pattern space.\n.PP\nAn\n.I address\nis either a decimal number that counts\ninput lines cumulatively across files, a `$' that\naddresses the last line of input, or a context address,\n`/regular expression/', in the style of\n.IR ed (1)\nmodified thus:\n.IP\nThe escape sequence `\\en' matches a\nnewline embedded in the pattern space.\n.PP\nA command line with no addresses selects every pattern space.\n.PP\nA command line with\none address selects each pattern space that matches the address.\n.PP\nA command line with\ntwo addresses selects the inclusive range from the first\npattern space that matches the first address through\nthe next pattern space that matches \nthe second.\n(If the second address is a number less than or equal\nto the line number first selected, only one\nline is selected.)\nThereafter the process is repeated, looking again for the\nfirst address.\n.PP\nEditing commands can be applied only to non-selected pattern\nspaces by use of the negation function `!' (below).\n.PP\nIn the following list of functions the \nmaximum number of permissible addresses\nfor each function is indicated in parentheses.\n.PP\nAn argument denoted\n.I text\nconsists of one or more lines,\nall but the last of which end with `\\e' to hide the\nnewline.\nBackslashes in text are treated like backslashes\nin the replacement string of an `s' command,\nand may be used to protect initial blanks and tabs\nagainst the stripping that is done on\nevery script line.\n.PP\nAn argument denoted\n.I rfile\nor\n.I wfile\nmust terminate the command\nline and must be preceded by exactly one blank.\nEach\n.I wfile\nis created before processing begins.\nThere can be at most 10 distinct\n.I wfile\narguments.\n.TP\n(1)\\|a\\e\n.br\n.ns\n.TP\n.I text\n.br\nAppend.\nPlace\n.I text\non the output before\nreading the next input line.\n.TP\n.RI (2)\\|b \" label\"\nBranch to the `:' command bearing the\n.IR label .\nIf\n.I label\nis empty, branch to the end of the script.\n.TP\n(2)\\|c\\e\n.br\n.ns\n.TP\n.I text\n.br\nChange.\nDelete the pattern space.\nWith 0 or 1 address or at the end of a 2-address range, place\n.I text\non the output.\nStart the next cycle.\n.TP\n(2)\\|d\nDelete the pattern space.\nStart the next cycle.\n.TP\n(2)\\|D\nDelete the initial segment of the \npattern space through the first newline.\nStart the next cycle.\n.TP\n(2)\\|g\nReplace the contents of the pattern space\nby the contents of the hold space.\n.TP\n(2)\\|G\nAppend the contents of the hold space to the pattern space.\n.TP\n(2)\\|h\nReplace the contents of the hold space by the contents of the pattern space.\n.TP\n(2)\\|H\nAppend the contents of the pattern space to the hold space.\n.TP\n(1)\\|i\\e\n.br\n.ns\n.TP\n.I text\n.br\nInsert.\nPlace\n.I text\non the standard output.\n.TP\n(2)\\|n\nCopy the pattern space to the standard output.\nReplace the pattern space with the next line of input.\n.TP\n(2)\\|N\nAppend the next line of input to the pattern space\nwith an embedded newline.\n(The current line number changes.)\n.TP\n(2)\\|p\nPrint.\nCopy the pattern space to the standard output.\n.TP\n(2)\\|P\nCopy the initial segment of the pattern space through\nthe first newline to the standard output.\n.TP\n(1)\\|q\nQuit.\nBranch to the end of the script.\nDo not start a new cycle.\n.TP\n.RI (2)\\|r \" rfile\"\nRead the contents of\n.IR rfile .\nPlace them on the output before reading\nthe next input line.\n.TP\n.RI (2)\\|s /regular\\ expression/replacement/flags\nSubstitute the\n.I replacement\nstring for instances of the\n.I regular expression\nin the pattern space.\nAny character may be used instead of `/'.\nFor a fuller description see\n.IR ed (1).\n.I Flags\nis zero or more of\n.RS\n.TP\ng\nGlobal.\nSubstitute for all nonoverlapping instances of the\n.I regular expression\nrather than just the\nfirst one.\n.TP\np\nPrint the pattern space if a replacement was made.\n.TP\n.RI w \" wfile\"\nWrite.\nAppend the pattern space to\n.I wfile\nif a replacement\nwas made.\n.RE\n.TP\n.RI (2)\\|t \" label\"\nTest.\nBranch to the `:' command bearing the\n.I label\nif any\nsubstitutions have been made since the most recent\nreading of an input line or execution of a `t'.\nIf \n.I label\nis empty, branch to the end of the script.\n.TP\n.RI (2)\\|w \" wfile\"\nWrite.\nAppend the pattern space to\n.IR wfile .\n.TP\n.RI (2)\\|x\nExchange the contents of the pattern and hold spaces.\n.TP\n.RI (2)\\|y /string1/string2/\nTransform.\nReplace all occurrences of characters in\n.I string1\nwith the corresponding character in\n.I string2.\nThe lengths of\n.I\nstring1\nand\n.I string2\nmust be equal.\n.TP\n.RI (2)! \" function\"\nDon't.\nApply the\n.I function\n(or group, if\n.I function\nis `{') only to lines\n.I not\nselected by the address(es).\n.TP\n.RI (0)\\|: \" label\"\nThis command does nothing; it bears a\n.I label\nfor `b' and `t' commands to branch to.\n.TP\n(1)\\|=\nPlace the current line number on the standard output as a line.\n.TP\n(2)\\|{\nExecute the following commands through a matching `}'\nonly when the pattern space is selected.\n.TP\n(0)\\|\nAn empty command is ignored.\n.SH SEE ALSO\ned(1), grep(1), awk(1), lex(1)\n"
  },
  {
    "path": "share/man/man1/sendbug.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)sendbug.1\t6.2 (Berkeley) 5/5/86\n.\\\"\n.TH SENDBUG 1 \"May 5, 1986\"\n.UC 5\n.ad\n.SH NAME\nsendbug \\- mail a system bug report to 4bsd-bugs\n.SH SYNOPSIS\n.B sendbug [ address ]\n.SH DESCRIPTION\n.PP\nBug reports sent to `4bsd-bugs@Berkeley.EDU' are intercepted\nby a program which expects bug reports to conform to a standard format.\n.I Sendbug\nis a shell script to help the user compose and mail bug reports\nin the correct format.\n.I Sendbug\nworks by invoking the editor specified by the environment variable\n.I EDITOR\non a temporary copy of the bug report format outline. The user must fill in the\nappropriate fields and exit the editor.  The default editor is\n.IR vi (1).\n.I Sendbug\nthen mails the completed report to `4bsd-bugs@Berkeley.EDU' or the address\nspecified on the command line.\n.SH FILES\n.nf\n.ta \\w'/usr/ucb/bugformat       'u\n/usr/ucb/bugformat\tcontains the bug report outline\n.fi\n.SH \"SEE ALSO\"\nvi(1),\nenviron(7),\nsendmail(8)\n"
  },
  {
    "path": "share/man/man1/sh.1",
    "content": ".\\\"\t@(#)sh.1\t6.3 (Berkeley) 5/5/86\n.\\\"\n.TH SH 1 \"May 5, 1986\"\n.AT 3\n.SH NAME\nsh, for, case, if, while, \\fB:\\fP, \\fB.\\fP, break, continue, cd, eval, exec, exit, export, login, read, readonly, set, shift, times, trap, umask, wait \\- command language\n.SH SYNOPSIS\n.B sh\n[\n.B \\-ceiknrstuvx\n] [ arg ] ...\n.ds OK [\\|\n.ds CK \\|]\n.ds LT \\s-2<\\s0\n.ds GT \\s-2>\\s0\n.ds LE \\s-2<\\s0\n.ds ST *\n.SH DESCRIPTION\n.I Sh\nis a command programming language that executes commands read from a terminal\nor a file.  See\n.B invocation\nfor the meaning of arguments to the shell.\n.PP\n.B Commands.\n.br\nA\n.I simple-command\nis a sequence of non blank\n.I words\nseparated by blanks (a blank is a\n.B tab\nor a\n.BR space ).\nThe first word specifies the name of the command to be executed.\nExcept as specified below the remaining words are passed as arguments\nto the invoked command.\nThe command name is passed as argument 0 (see\n.IR execve (2)).\nThe\n.I value\nof a simple-command is its exit status\nif it terminates normally or 200+\\fIstatus\\fP if it terminates abnormally (see\n.IR sigvec (2)\nfor a list of status values).\n.LP\nA\n.I pipeline\nis a sequence of one or more\n.I commands\nseparated by\n.B \\(or.\nThe standard output of each command but the last is connected by a\n.IR pipe (2)\nto the standard input of the next command.\nEach command is run as a separate process;\nthe shell waits for the last command to terminate.\n.LP\nA\n.I list\nis a sequence of one or more\n.I pipelines\nseparated by\n.BR ; ,\n.BR & ,\n.B &&\nor\n.B \\(or\\|\\(or\nand optionally terminated by\n.B ;\nor\n.BR & .\n.B ;\nand\n.B &\nhave equal precedence which is lower than that of\n.B &&\nand\n.BR \\(or\\|\\(or ,\n.B &&\nand\n.B \\(or\\|\\(or\nalso have equal precedence.\nA semicolon causes sequential execution; an ampersand causes the preceding\n.I pipeline\nto be executed without waiting for it to finish.  The symbol\n.B &&\n.RB ( \\(or\\|\\(or )\ncauses the\n.I list\nfollowing to be executed only if the preceding\n.I pipeline\nreturns a zero (non zero) value.  Newlines may appear in a\n.I list,\ninstead of semicolons, to delimit commands.\n.LP\nA\n.I command\nis either a simple-command or one of the following.\nThe value returned by a command is that of the\nlast simple-command executed in the command.\n.TP\n\\fBfor \\fIname\\fR \\*(OK\\fBin \\fIword\\fR ...\\*(CK \\fBdo \\fIlist \\fBdone\\fR\nEach time a\n.B for\ncommand is executed\n.I name\nis set to the next word in the\n.B for\nword list.\nIf\n.BI in \\ word\n\\&...\nis omitted,\n.B\nin \"$@\"\nis assumed.  Execution ends when there are no more words in the list.\n.TP\n\\fBcase \\fIword \\fBin\\fR \\*(OK\\fIpattern \\fR\\*(OK \\fB\\(or \\fIpattern \\fR\\*(CK ... \\fB) \\fIlist \\fB;;\\fR\\*(CK ... \\fBesac\\fR\nA\n.B case\ncommand executes the\n.I list\nassociated with the first pattern that matches\n.I word.\nThe form of the patterns is the same as that used for file name generation.\n.TP\n\\fBif \\fIlist \\fBthen \\fIlist\\fR \\*(OK\\fBelif \\fIlist \\fBthen \\fIlist\\fR\\*(CK ... \\*(OK\\fBelse \\fIlist\\fR\\*(CK \\fBfi\\fR\nThe\n.I list\nfollowing\n.B if\nis executed and if it returns zero the\n.I list\nfollowing\n.B then\nis executed.  Otherwise, the\n.I list\nfollowing\n.B elif\nis executed and if its value is zero the\n.I list\nfollowing\n.B then\nis executed.  Failing that the\n.B else\n.I list\nis executed.\n.TP\n\\fBwhile \\fIlist\\fR \\*(OK\\fBdo \\fIlist\\fR\\*(CK \\fBdone\\fR\nA\n.B while\ncommand repeatedly executes the\n.B while\n.I list\nand if its value is zero executes the\n.B do\n.I list;\notherwise the loop terminates.  The value returned by a\n.B while\ncommand is that of the last executed command in the\n.B do\n.I list.\n.B until\nmay be used in place of\n.B while\nto negate the loop termination test.\n.TP\n.BI ( \" list \" )\nExecute\n.I list\nin a subshell.\n.TP\n.BI { \" list \" }\n.I list\nis simply executed.\n.LP\nThe following words are only recognized as the first word of a command\nand when not quoted.\n.IP\n.B\nif then else elif fi case in esac for while until do done { }\n.PP\n.B Command substitution.\n.br\nThe standard output from a command enclosed in a pair of back quotes \n.RB ( \\`\\|\\` )\nmay be used as part or all of a word; trailing newlines are removed.\n.PP\n.B Parameter substitution.\n.br\nThe character\n.B $\nis used to introduce substitutable parameters.\nPositional parameters may be assigned values by\n.BR set .\nVariables may be set by writing\n.IP\n.IB name = value\n[\n.IB name = value\n] ...\n.TP\n$\\fB\\|{\\fIparameter\\fB\\|}\\fR\nA\n.I parameter\nis a sequence of letters, digits or underscores (a\n.IR name ),\na digit, or any of the characters\n.B\n* @ # ? \\- $ !\\|.\nThe value, if any, of the parameter is substituted.\nThe braces are required only when\n.I parameter\nis followed by a letter, digit, or underscore\nthat is not to be interpreted as part of its name.  If\n.I parameter\nis a digit, it is a positional parameter.  If\n.I parameter\nis\n.BR * \" or\" \" @\"\nthen all the positional parameters, starting with\n.SM\n.BR $1 ,\nare substituted separated by spaces.\n.SM\n.B $0\nis set from argument zero when the shell is invoked.\n.TP\n$\\fB\\|{\\fIparameter\\|\\-word\\|\\fB}\\fR\nIf\n.I parameter\nis set, substitute its value; otherwise substitute\n.I word.\n.TP\n$\\fB\\|{\\fIparameter\\|\\(eq\\|word\\|\\fB}\\fR\nIf\n.I parameter\nis not set, set it to\n.I word;\nthe value of the parameter is then substituted.\nPositional parameters may not be assigned to in this way.\n.TP\n$\\fB\\|{\\fIparameter\\|?\\|word\\|\\fB}\\fR\nIf\n.I parameter\nis set, substitute its value; otherwise, print\n.I word\nand exit from the shell.  If\n.I word\nis omitted, a standard message is printed.\n.TP\n$\\fB\\|{\\fIparameter\\|\\(plword\\|\\fB}\\fR\nIf\n.I parameter\nis set, substitute\n.I word;\notherwise substitute nothing.\n.LP\nIn the above\n.I word\nis not evaluated unless it is to be used as the substituted string.\n(So that, for example, echo ${d\\-\\'pwd\\'} will only execute\n.I pwd\nif\n.I d\nis unset.)\n.LP\nThe following\n.I parameters\nare automatically set by the shell.\n.RS\n.TP\n.B #\nThe number of positional parameters in decimal.\n.PD 0\n.TP\n.B \\-\nOptions supplied to the shell on invocation or by\n.BR set .\n.TP\n.B ?\nThe value returned by the last executed command in decimal.\n.TP\n.B $\nThe process number of this shell.\n.TP\n.B !\nThe process number of the last background command invoked.\n.PD\n.RE\n.LP\nThe following\n.I parameters\nare used but not set by the shell.\n.RS\n.TP\n.B\n.SM HOME\nThe default argument (home directory) for the\n.B cd\ncommand.\n.PD 0\n.TP\n.B\n.SM PATH\nThe search path for commands (see\n.BR execution ).\n.TP\n.B\n.SM MAIL\nIf this variable is set to the name of\na mail file, the shell informs the user of\nthe arrival of mail in the specified file.\n.SM\n.TP\n.B PS1\nPrimary prompt string, by default '$ '.\n.TP\n.SM\n.B PS2\nSecondary prompt string, by default '> '.\n.TP\n.SM\n.B IFS\nInternal field separators, normally\n.BR space ,\n.BR tab ,\nand\n.BR newline .\n.B IFS\nis ignored if \n.I sh\nis running as root or if the effective user id differs from the real user id.\n.PD\n.RE\n.PP\n.B Blank interpretation.\n.br\nAfter parameter and command substitution,\nany results of substitution are scanned for internal field separator\ncharacters (those found in\n.SM\n.BR $IFS \\*S)\nand split into distinct arguments where such characters are found.\nExplicit null arguments (\"\" or \\'\\') are retained.\nImplicit null arguments (those resulting from\n.I parameters\nthat have no values) are removed.\n.PP\n.B File name generation.\n.br\nFollowing substitution, each command word is scanned for the characters\n.BR * ,\n.B ?\nand\n.B \\*(OK.\nIf one of these characters appears, the word is regarded as a pattern.\nThe word is replaced with alphabetically sorted file names that match the\npattern.  If no file name is found that matches the pattern,\nthe word is left unchanged.  The character\n.B .\nat the start of a file name or immediately following a\n.BR / ,\nand the character\n.BR / ,\nmust be matched explicitly.\n.TP \n.B \\*(ST\nMatches any string, including the null string.\n.PD 0\n.TP \n.B ?\nMatches any single character.\n.TP \n.B \\*(OK...\\*(CK\nMatches any one of the characters enclosed.\nA pair of characters separated by\n.B \\-\nmatches any character lexically between the pair.\n.PD\n.PP\n.B Quoting.\n.br\nThe following characters have a special meaning to the shell\nand cause termination of a word unless quoted.\n.LP\n\t\\fB;   &   (   )   \\(or   \\*(LT   \\*(GT   newline   space   tab\\fP\n.LP\nA character may be\n.I quoted\nby preceding it with a\n.B\n\\\\\\|.\n.B \\\\\\\\newline\nis ignored.\nAll characters enclosed between a pair of quote marks (\\fB\\'\\|\\'\\fP),\nexcept a single quote, are quoted.  Inside double quotes (\\fB\"\\|\"\\fP)\nparameter and command substitution occurs and\n.B\n\\\\\nquotes the characters\n.B\n\\\\ \\' \"\nand\n.BR $ \\|.\n.LP\n.B\n\"$*\"\nis equivalent to\n.SM\n.B\n\"$1 $2 ...\"\nwhereas\n.br\n.B\n\"$@\"\nis equivalent to\n.SM\n.B\n\"$1\" \"$2\" ... .\n.PP\n.B Prompting.\n.br\nWhen used interactively, the shell prompts with the value of\n.SM\nPS1\nbefore reading a command.\nIf at any time a newline is typed and further input is needed\nto complete a command, the secondary prompt\n.RB ( \\s-2$PS2\\s0 )\nis issued.\n.PP\n.B Input output.\n.br\nBefore a command is executed its input and output\nmay be redirected using a special notation interpreted by the shell.\nThe following may appear anywhere in a simple-command\nor may precede or follow a\n.I command\nand are not passed on to the invoked command.\nSubstitution occurs before\n.I word\nor\n.I digit\nis used.\n.TP\n\\*(LT\\fI\\|word\\fP\nUse file\n.I word\nas standard input (file descriptor 0).\n.PD\n.TP\n\\*(GT\\fI\\|word\\fP\nUse file\n.I word\nas standard output (file descriptor 1).\nIf the file does not exist, it is created;\notherwise it is truncated to zero length.\n.TP\n\\*(GT\\*(GT\\fI\\|word\\fP\nUse file\n.I word\nas standard output.\nIf the file exists, output is appended (by seeking to the end);\notherwise the file is created.\n.TP\n\\*(LT\\*(LT\\fI\\|word\\fP\nThe shell input is read up to a line the same as\n.IR word ,\nor end of file.\nThe resulting document becomes the standard input.\nIf any character of\n.I word\nis quoted, no interpretation is placed upon the characters of the document;\notherwise, parameter and command substitution occurs,\n.B\n\\\\newline\nis ignored, and\n.B\n\\\\\nis used to quote the characters\n.B\n\\\\ $ \\'\nand the first character of\n.I word.\n.TP\n\\*(LT\\|&\\|\\fIdigit\\fP\nThe standard input is duplicated from file descriptor\n.I digit;\nsee\n.IR dup (2).\nSimilarly for the standard output using \\*(GT\\|.\n.TP\n\\*(LT\\|&\\|\\-\nThe standard input is closed.\nSimilarly for the standard output using \\*(GT\\|.\n.PD\n.LP\nIf one of the above is preceded by a digit, the\nfile descriptor created is that specified by the digit\n(instead of the default 0 or 1).  For example,\n.LP\n\t\\&... 2\\*(GT&1\n.LP\ncreates file descriptor 2 to be a duplicate\nof file descriptor 1.\n.LP\nIf a command is followed by\n.B &\nthen the default standard input for the command is the empty file\n(/dev/null).\nOtherwise, the environment for the execution of a command contains the\nfile descriptors of the invoking shell as modified by input\noutput specifications.\n.PP\n.B Environment.\n.br\nThe environment is a list of name-value pairs that is passed to\nan executed program in the same way as a normal argument list; see\n.IR execve (2)\nand\n.IR environ (7).\nThe shell interacts with the environment in several ways.\nOn invocation, the shell scans the environment and creates a\n.I parameter\nfor each name found, giving it the corresponding value.\nExecuted commands inherit the same environment.\nIf the user modifies the values of these\n.I parameters\nor creates new ones, none of these affects the environment unless the\n.B export\ncommand is used to bind the shell's\n.I parameter\nto the environment.\nThe environment seen by any executed command is thus composed\nof any unmodified name-value pairs originally inherited by the shell,\nplus any modifications or additions, all of which must be noted in\n.B export\ncommands.\n.LP\nThe environment for any\n.I simple-command\nmay be augmented by prefixing it with one or more assignments to\n.I parameters.\nThus these two lines are equivalent\n.IP\nTERM=450 cmd args\n.br\n(export TERM; TERM=450; cmd args)\n.LP\nIf the\n.B \\-k\nflag is set,\n.I all\nkeyword arguments are placed in the environment,\neven if the occur after the command name.\nThe following prints 'a=b c' and 'c':\n.nf\necho a=b c\nset \\-k\necho a=b c\n.fi\n.PP\n.B Signals.\n.br\nThe INTERRUPT and QUIT signals for an invoked\ncommand are ignored if the command is followed by\n.BR & ;\notherwise signals have the values inherited by the shell from its parent.\n(But see also\n.BR trap. )\n.PP\n.B Execution.\n.br\nEach time a command is executed the above substitutions are carried out.\nExcept for the 'special commands' listed below a new process is created and\nan attempt is made to execute the command via an\n.IR execve (2).\n.LP\nThe shell parameter\n.B\n.SM $PATH\ndefines the search path for the directory containing the command.\nEach alternative directory name is separated by a colon\n.RB ( : ).\nThe default path is\n.BR :/bin:/usr/bin .\nIf the command name contains a /, the search path is not used.\nOtherwise, each directory in the path is searched for an executable file.\nIf the file has execute permission but is not an\n.I a.out\nfile, it is assumed to be a file containing shell commands.\nA subshell (i.e., a separate process) is spawned to read it.\nA parenthesized command is also executed in a subshell.\n.PP\n.B Special commands.\n.br\nThe following commands are executed in the shell process\nand except where specified\nno input output redirection is permitted for such commands.\n.TP\n.B #\nFor non-interactive shells, everything following the\n.B #\nis treated as a comment, i.e. the rest of the line is ignored.\nFor interactive shells, the\n.B #\nhas no special effect.\n.TP\n.B :\nNo effect; the command does nothing.\n.PD 0\n.TP\n.BI . \\ file\nRead and execute commands from\n.I file\nand return.  The search path\n.B\n.SM $PATH\nis used to find the directory containing\n.IR file .\n.TP\n\\fBbreak\\fR \\*(OK\\fIn\\fR\\*(CK\nExit from the enclosing\n.B for\nor\n.B while\nloop, if any.\nIf\n.I n\nis specified, break\n.I n\nlevels.\n.TP\n\\fBcontinue\\fR \\*(OK\\fIn\\fR\\*(CK\nResume the next iteration of the enclosing\n.B for\nor\n.B while\nloop.  If\n.I n\nis specified, resume at the\n.IR n -th\nenclosing loop.\n.TP\n\\fBcd\\fR \\*(OK\\fIarg\\fR\\*(CK\nChange the current directory to\n.I arg.\nThe shell parameter\n.B\n.SM $HOME\nis the default\n.IR arg .\n.TP\n\\fBeval\\fR \\*(OK\\fIarg \\fR...\\*(CK\nThe arguments are read as input to the shell\nand the resulting command(s) executed.\n.TP\n\\fBexec\\fR \\*(OK\\fIarg \\fR...\\*(CK\nThe command specified by the arguments is executed in place of this shell\nwithout creating a new process.\nInput output arguments may appear and if no other\narguments are given cause the shell input output to be modified.\n.TP\n\\fBexit\\fR \\*(OK\\fIn\\fR\\*(CK\nCauses a non interactive shell to exit with the exit status specified by\n.I n.\nIf\n.I n\nis omitted, the exit status is that of the last command executed.\n(An end of file will also exit from the shell.)\n.TP\n\\fBexport\\fR \\*(OK\\fIname\\fR ...\\*(CK\nThe given names are marked for automatic export to the\n.I environment\nof subsequently-executed commands.\nIf no arguments are given, a list of exportable names is printed.\n.TP\n\\fBlogin\\fR \\*(OK\\fIarg\\fR ...\\*(CK\nEquivalent to 'exec login arg ...'.\n.TP\n.BI read \\ name\\ ...\nOne line is read from the standard input;\nsuccessive words of the input are assigned to the variables\n.I name\nin order, with leftover words to the last variable.\nThe return code is 0 unless the end-of-file is encountered.\n.TP\n\\fBreadonly\\fR \\*(OK\\fIname \\fR...\\*(CK\nThe given names are marked readonly and\nthe values of the these names may not be changed\nby subsequent assignment.\nIf no arguments are given, a list of all readonly names is printed.\n.TP\n\\fBset\\fR \\*(OK\\fB\\-eknptuvx\\fR \\*(OK\\fIarg \\fR...\\*(CK\\*(CK\n.RS\n.PD 0\n.TP 3m\n.B \\-e\nIf non interactive, exit immediately if a command fails.\n.TP\n.B \\-k\nAll keyword arguments are placed in the environment for a command,\nnot just those that precede the command name.\n.TP\n.B \\-n\nRead commands but do not execute them.\n.TP\n.B \\-t\nExit after reading and executing one command.\n.TP\n.B \\-u\nTreat unset variables as an error when substituting.\n.TP\n.B \\-v\nPrint shell input lines as they are read.\n.TP\n.B \\-x\nPrint commands and their arguments as they are executed.\n.TP\n.B \\-\nTurn off the\n.B \\-x\nand\n.B \\-v\noptions.\n.PD\n.LP\nThese flags can also be used upon invocation of the shell.\nThe current set of flags may be found in\n.BR $\\- .\n.LP\nRemaining arguments are positional\nparameters and are assigned, in order, to\n.SM\n.BR $1 ,\n.SM\n.BR $2 ,\netc.  If no arguments are given, the values of all names are printed.\n.RE\n.TP\n.B shift\nThe positional parameters from\n.SM\n.BR $2 ...\nare renamed\n.SM\n.BR $1 ...\n.TP\n.B times\nPrint the accumulated user and system times for processes run from the shell.\n.TP\n\\fBtrap\\fR \\*(OK\\fIarg\\fR\\*(CK \\*(OK\\fIn\\fR\\*(CK ...\n.I Arg\nis a command to be read and executed when the shell receives signal(s)\n.I n.\n(Note that\n.I arg\nis scanned once when the trap is set and once when the trap is taken.)\nTrap commands are executed in order of signal number.  If\n.I arg\nis absent, all trap(s)\n.I n\nare reset to their original values.\nIf\n.I arg\nis the null\nstring, this signal is ignored by the shell and by invoked commands.\nIf\n.I n\nis 0, the command\n.I arg\nis executed on exit from the shell, otherwise upon receipt of signal\n.I n\nas numbered in\n.IR sigvec (2).\n.I Trap\nwith no arguments prints a list of commands associated with each signal number.\n.TP\n\\fBumask \\fR[ \\fInnn\\fR ]\nThe user file creation mask is set to the octal value\n.I nnn\n(see\n.IR umask (2)).\nIf\n.I nnn\nis omitted, the current value of the mask is printed.\n.TP\n\\fBwait\\fP \\*(OK\\fIn\\fP\\*(CK\nWait for the specified process and report its termination status.  If\n.I n\nis not given, all currently active child processes are waited for.\nThe return code from this command is that of the process waited for.\n.PD\n.LP\n.PP\n.B Invocation.\n.br\nIf the first character of argument zero is\n.BR \\- ,\ncommands are read from\n.BR \\s-2$HOME\\s0/.\\|profile ,\nif such a file exists.\nCommands are then read as described below.\nThe following flags are interpreted by the shell when it is invoked.\n.PD 0\n.TP 11n\n.BI \\-c \\ string\nIf the\n.B \\-c\nflag is present, commands are read from\n.I string\\|.\n.TP 11n\n.B \\-s\nIf the\n.B \\-s\nflag is present or if no arguments remain\nthen commands are read from the standard input.\nShell output is written to file descriptor 2.\n.TP 11n\n.B \\-i\nIf the\n.B \\-i\nflag is present or\nif the shell input and output are attached to a terminal (as told by\n.IR gtty )\nthen this shell is\n.I interactive.\nIn this case the terminate signal SIGTERM (see\n.IR sigvec (2))\nis ignored (so that 'kill 0'\ndoes not kill an interactive shell) and the interrupt signal\nSIGINT is caught and ignored (so that\n.B wait\nis interruptible).\nIn all cases SIGQUIT is ignored by the shell.\n.PD\n.LP\nThe remaining flags and arguments are described under the\n.B set\ncommand.\n.SH FILES\n.RB $HOME/ . \\^profile\n.br\n/tmp/sh*\n.br\n/dev/null\n.SH SEE ALSO\ncsh(1),\ntest(1),\nexecve(2),\nenviron(7)\n.SH DIAGNOSTICS\nErrors detected by the shell, such as syntax errors cause the shell\nto return a non zero exit status.\nIf the shell is being used non interactively\nthen execution of the shell file is abandoned.\nOtherwise, the shell returns the exit status of\nthe last command executed (see also\n.BR exit ).\n.SH BUGS\nIf \\*(LT\\*(LT is used to provide standard input to an asynchronous\nprocess invoked by &, the shell gets mixed up about naming the input document.\nA garbage file /tmp/sh* is created, and the shell complains about\nnot being able to find the file by another name.\n"
  },
  {
    "path": "share/man/man1/size.1",
    "content": ".\\\"\t@(#)size.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH SIZE 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nsize \\- size of an object file\n.SH SYNOPSIS\n.B size\n[ object ... ]\n.SH DESCRIPTION\n.I Size\nprints the (decimal) number of bytes required by the text, data, and\nbss portions, and their sum in hex and decimal, of each object-file argument.\nIf no file is specified,\n.B a.out\nis used.\n.SH \"SEE ALSO\"\na.out(5)\n"
  },
  {
    "path": "share/man/man1/sleep.1",
    "content": ".\\\"\t@(#)sleep.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH SLEEP 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nsleep \\- suspend execution for an interval\n.SH SYNOPSIS\n.B sleep\ntime\n.SH DESCRIPTION\n.I Sleep\nsuspends execution for\n.I time\nseconds.\nIt is used to execute a command after a certain amount of time as in:\n.PP\n\t(sleep 105; command)&\n.PP\nor to execute a command every so often, as in:\n.PP\n\twhile true\n.br\n\tdo\n.br\n\t\tcommand\n.br\n\t\tsleep 37\n.br\n\tdone\n.SH \"SEE ALSO\"\nsetitimer(2), alarm(3C), sleep(3)\n.SH BUGS\n.I Time\nmust be less than 2,147,483,647 seconds.\n"
  },
  {
    "path": "share/man/man1/soelim.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)soelim.1\t6.2.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH SOELIM 1 \"October 22, 1996\"\n.UC\n.SH NAME\nsoelim \\- eliminate \\&.so's from nroff input\n.SH SYNOPSIS\n.B soelim\n[\nfile ...\n]\n.SH DESCRIPTION\n.I Soelim\nreads the specified files or the standard input and performs the textual\ninclusion implied by the\n.I nroff\ndirectives of the form\n.PP\n.DT\n\t\\&.so somefile\n.PP\nwhen they appear at the beginning of input lines.\nThis is useful since programs such as\n.I tbl\ndo not normally do this; it allows the placement of individual tables\nin separate files to be run as a part of a large document.\n.PP\nAn argument consisting of a single minus\n.RB ( \\- )\nis taken to be\na file name corresponding to the standard input.\n.PP\nNote that inclusion can be suppressed by using `\\'' instead of `\\.', i.e.\n.PP\n.DT\n\t\\'so /usr/share/tmac/tmac.s\n.PP\nA sample usage of\n.I soelim\nwould be\n.PP\n\tsoelim exum?.n | tbl | nroff \\-ms | col | lpr\n.SH SEE\\ ALSO\ncolcrt(1), more(1)\n.SH BUGS\nThe format of the source commands must involve no strangeness \\-\nexactly one blank must precede and no blanks follow the file name.\n"
  },
  {
    "path": "share/man/man1/sort.1",
    "content": ".\\\"\t@(#)sort.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH SORT 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nsort \\- sort or merge files\n.SH SYNOPSIS\n.B sort\n[\n.if t \\fB\\-mubdf\\&inrt\\fIx\\fR\n.if n -mubdfinrt\b\b\b\b\b\b\b\b\b_________x\n]\n[ \\fB+\\fIpos1 \\fR [ \\fB\\-\\fIpos2 \\fR]\n] ...\n[ \n.B \\-o \nname ] [\n.B \\-T\ndirectory ] [ name ] ...\n.SH DESCRIPTION\n.I Sort\nsorts lines of all the named files together and writes the result on\nthe standard output.  The name `\\-' means the standard input.\nIf no input files are named, the standard input is sorted.\n.LP\nThe default sort key is an entire line.\nDefault ordering is lexicographic by bytes in machine collating sequence.\nThe ordering is affected globally by the following options,\none or more of which may appear.\n.TP 5\n.B  b\nIgnore leading blanks (spaces and tabs) in field comparisons.\n.TP 5\n.B  d\n`Dictionary' order: only letters, digits and blanks\nare significant in comparisons.\n.TP 5\n.B  f\nFold upper case letters onto lower case.\n.TP 5\n.B  i\nIgnore characters outside the ASCII range 040-0176 in nonnumeric comparisons.\n.TP 5\n.B  n\nAn initial numeric string, consisting of optional blanks, optional minus sign,\nand zero or more digits with optional decimal point,\nis sorted by arithmetic value.  Option\n.B n\nimplies option\n.B b.\n.TP 5\n.B  r\nReverse the sense of comparisons.\n.TP 5\n.BI t x\n`Tab character' separating fields is\n.IR x .\n.LP\nThe notation\n.BI + \"pos1 \" \"\\-\\fIpos2\"\nrestricts a sort key to a field beginning at\n.I pos1\nand ending just before\n.IR pos2 .\n.I Pos1\nand\n.I pos2\neach have the form\n.IB m . n\\fR,\noptionally followed by one or more of the flags\n.B bdf\\&inr,\nwhere\n.I m\ntells a number of fields to skip from the beginning of the line and\n.I n\ntells a number of characters to skip further.\nIf any flags are present they override all the global\nordering options for this key.  If the\n.B b\noption is in effect\n.I n\nis counted from the first nonblank in the field;\n.B b\nis attached independently to \n.IR pos2 .\nA missing \\&\\fB.\\fIn\\fR means .0; a missing\n.BI \\- pos2\nmeans the end of the line.  Under the\n.BI \\-t x\noption, fields are strings separated by\n.IR x ;\notherwise fields are nonempty nonblank strings separated by blanks.\n.LP\nWhen there are multiple sort keys, later keys\nare compared only after all earlier keys compare equal.\nLines that otherwise compare equal are ordered with all bytes significant.\n.LP\nThese option arguments are also understood:\n.TP 5\n.B c\nCheck that the input file is sorted according to the ordering rules;\ngive no output unless the file is out of sort.\n.TP 5\n.B  m\nMerge only, the input files are already sorted.\n.TP 5\n.B  o\nThe next argument is the name of an output file\nto use instead of the standard output.\nThis file may be the same as one of the inputs.\n.TP 5\n.B T\nThe next argument is the name of a directory in which temporary files\nshould be made.\n.TP 5\n.B  u\nSuppress all but one in each set of equal lines.\nIgnored bytes and bytes outside keys do not participate in this comparison.\n.SH EXAMPLES\n.LP\nPrint in alphabetical order all the unique spellings in a list of words.\nCapitalized words differ from uncapitalized.\n.LP\n.ti +8\nsort \\-u +0f +0 list\n.LP\nPrint the password file\n.RI ( passwd (5))\nsorted by user id number (the 3rd colon-separated field).\n.LP\n.ti +8\nsort \\-t: +2n /etc/passwd\n.LP\nPrint the first instance of each month in an already sorted file\nof (month day) entries.\nThe options\n.B \\-um\nwith just one input file make the choice of a\nunique representative from a set of equal lines predictable.\n.LP\n.ti +8\nsort \\-um +0 \\-1 dates\n.SH FILES\n/usr/tmp/stm*, /tmp/*\tfirst and second tries for\ntemporary files\n.SH \"SEE ALSO\"\nuniq(1),\ncomm(1),\nrev(1),\njoin(1)\n.SH DIAGNOSTICS\nComments and exits with nonzero status for various trouble\nconditions and for disorder discovered under option\n.BR \\-c .\n.SH BUGS\nVery long lines are silently truncated.\n"
  },
  {
    "path": "share/man/man1/sortbib.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)sortbib.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH SORTBIB 1 \"April 29, 1985\"\n.UC 5\n.SH NAME\nsortbib \\- sort bibliographic database\n.SH SYNOPSIS\n.B sortbib\n[\n.BR \\-s KEYS\n] database  ...\n.SH DESCRIPTION\n.I Sortbib\nsorts files of records containing\n.I refer\nkey-letters by user-specified keys.\nRecords may be separated by blank lines,\nor by \\&.[ and \\&.] delimiters,\nbut the two styles may not be mixed together.\nThis program reads through each\n.I database\nand pulls out key fields, which are sorted separately.\nThe sorted key fields contain the file pointer,\nbyte offset, and length of corresponding records.\nThese records are delivered using disk seeks and reads, so\n.I sortbib\nmay not be used in a pipeline to read standard input.\n.PP\nBy default,\n.I sortbib\nalphabetizes by the first %A and the %D fields,\nwhich contain the senior author and date.\nThe\n.B \\-s\noption is used to specify new\n.IR \\s-1KEYS\\s0 .\nFor instance,\n.BR \\-s ATD\nwill sort by author, title, and date,\nwhile\n.BR \\-s A+D\nwill sort by all authors, and date.\nSort keys past the fourth are not meaningful.\nNo more than 16 databases may be sorted together at one time.\nRecords longer than 4096 characters will be truncated.\n.PP\n.I Sortbib\nsorts on the last word on the %A line,\nwhich is assumed to be the author's last name.\nA word in the final position, such as ``jr.'' or ``ed.'',\nwill be ignored if the name beforehand ends with a comma.\nAuthors with two-word last names or unusual constructions\ncan be sorted correctly by using the\n.I nroff\nconvention ``\\e0'' in place of a blank.\nA %Q field is considered to be the same as %A,\nexcept sorting begins with the first, not the last, word.\n.I Sortbib\nsorts on the last word of the %D line, usually the year.\nIt also ignores leading articles (like ``A'' or ``The'')\nwhen sorting by titles in the %T or %J fields;\nit will ignore articles of any modern European language.\nIf a sort-significant field is absent from a record,\n.I sortbib\nplaces that record before other records containing that field.\n.SH SEE ALSO\nrefer(1), addbib(1), roffbib(1), indxbib(1), lookbib(1)\n.SH AUTHORS\nGreg Shenaut, Bill Tuthill\n.SH BUGS\nRecords with missing author fields\nshould probably be sorted by title.\n"
  },
  {
    "path": "share/man/man1/spell.1",
    "content": ".\\\"\t@(#)spell.1\t6.1.1 (2.11BSD)  1996/10/22\n.\\\"\n.TH SPELL 1 \"October 22, 1996\"\n.AT 3\n.SH NAME\nspell, spellin, spellout \\- find spelling errors\n.SH SYNOPSIS\n.B spell\n[\n.B \\-v\n] [\n.B \\-b\n] [\n.B \\-x\n] [\n.B \\-d\nhlist ] [\n.B \\-s\nhstop ] [\n.B \\-h\nspellhist\n] [ file ] ...\n.PP\n.B spellin\n[ list ]\n.PP\n.B spellout\n[\n.B \\-d\n] list\n.SH DESCRIPTION\n.I Spell\ncollects words from the named documents,\nand looks them up in a spelling list.\nWords that neither occur among nor are derivable\n(by applying certain inflections,\nprefixes or suffixes) from words in the spelling list\nare printed on the standard output.\nIf no files are named,\nwords are collected from the standard input.\n.PP\n.I Spell\nignores most\n.I troff,\n.I tbl\nand\n.IR  eqn (1)\nconstructions.\n.PP\nUnder the\n.B \\-v\noption, all words not literally in the spelling list are printed,\nand plausible derivations from spelling list words are indicated.\n.PP\nUnder the \n.B \\-b\noption, British spelling is checked.\nBesides preferring\n.ft I\ncentre, colour, speciality, travelled,\n.ft R\netc.,\nthis option insists upon\n.I -ise\nin words like\n.I standardise,\nFowler and the OED to the contrary notwithstanding.\n.PP\nUnder the \n.B \\-x\noption, every plausible stem is printed with `=' for each word.\n.PP\nThe spelling list is based on many sources.\nWhile it is more haphazard than an ordinary\ndictionary, it is also more effective with\nproper names and popular technical words.\nCoverage of\nthe specialized vocabularies of biology,\nmedicine and chemistry is light.\n.PP\nThe auxiliary files used for the spelling list,\nstop list, and history file may be specified by\narguments following the\n.BR \\-d ,\n.BR \\-s ,\nand\n.B \\-h\noptions.\nThe default files are indicated below.\nCopies of all output\nmay be accumulated in the history file.\nThe stop list filters out misspellings (e.g. thier=thy\\-y+ier)\nthat would otherwise pass.\n.PP\nTwo routines help maintain the hash lists used by\n.I spell.\nBoth expect a set of words, one per line,\nfrom the standard input.\n.I Spellin\ncombines the words from the standard input and the\npreexisting\n.I list\nfile and places a new list on the standard output.\nIf no \n.I list\nfile is specified, the new list is created from scratch.\n.I Spellout\nlooks up each word from the standard input and prints\non the standard output\nthose that are missing from (or present on, with\noption\n.BR \\-d )\nthe hashed\n.I list\nfile.\nFor example, to verify that\n.I hookey\nis not on the default spelling list, add it to your own\nprivate list, and then use it with\n.IR spell ,\n.PP\n.RS\n.nf\necho  hookey  |  spellout  /usr/dict/hlista\necho  hookey  |  spellin  /usr/dict/hlista  >  myhlist\nspell  \\-d  myhlist  huckfinn\n.RE\n.SH FILES\n/usr/dict/hlist[ab]\thashed spelling lists, American & British, default for\n.B \\-d\n.br\n/usr/dict/hstop\t\thashed stop list, default for\n.B \\-s\n.br\n/dev/null\t\thistory file, default for\n.B \\-h\n.br\n/tmp/spell.$$\\(**\t\ttemporary files\n.br\n/usr/libexec/spell\n.br\n.SH SEE ALSO\nderoff(1), sort(1), tee(1), sed(1)\n.SH BUGS\nThe spelling list's coverage is uneven;\nnew installations will probably wish to \nmonitor the output for several months to gather\nlocal additions.\n.br\nBritish spelling was done by an American.\n"
  },
  {
    "path": "share/man/man1/spline.1",
    "content": ".\\\"\t@(#)spline.1g\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH SPLINE 1G \"April 29, 1985\"\n.AT 3\n.SH NAME\nspline \\- interpolate smooth curve\n.SH SYNOPSIS\n.B spline\n[ option ] ...\n.SH DESCRIPTION\n.I Spline\ntakes pairs of numbers from the standard input as abcissas and ordinates\nof a function.\nIt produces a similar set, which\nis approximately equally spaced and\nincludes the input set, on the standard output.\nThe cubic spline output\n(R. W. Hamming,\n.ft I\nNumerical Methods for Scientists and Engineers,\n.ft R\n2nd ed., 349ff)\nhas two continuous derivatives,\nand sufficiently many points to look smooth when plotted, for\nexample by\n.IR  graph (1G).\n.PP\nThe following options are recognized,\neach as a separate argument.\n.TP 5\n.B  \\-a\nSupply abscissas automatically (they are missing from\nthe input); spacing is given by the next\nargument, or is assumed to be 1 if next argument is not a number.\n.TP 5\n.B  \\-k\nThe constant\n.IR k \"\"\nused in the boundary value computation\n.IP\n.if n .ig\n.ti +1.5i\n.ds ' \\h'-\\w'\\(fm\\(fm'u'\n.EQ\n.nr 99 \\n(.s\n.nr 98 \\n(.f\n'ps 10\n.ft I\n.ds 11 \"y\\(fm\\(fm\n.nr 11 \\w'\\*(11'\n.ds 12 \"\\*'\n.nr 12 \\w'\\*(12'\n'ps 8\n.ds 13 \"\\fR0\\fP\n.nr 13 \\w'\\*(13'\n.as 12 \\v'18u'\\s8\\*(13\\|\\s10\\v'-18u'\n'ps 10\n.nr 12 \\n(12+\\n(13+\\w'\\s8\\|'\n.as 11 \"\\*(12\n.nr 11 \\w'\\*(11'\n.ds 12 \"\\|\\|\n.nr 12 \\w'\\*(12'\n.as 11 \"\\*(12\n.nr 11 \\w'\\*(11'\n.ds 12 \"\\|=\\|\n.nr 12 \\w'\\*(12'\n.as 11 \"\\*(12\n.nr 11 \\w'\\*(11'\n.ds 12 \"\\|\\|\n.nr 12 \\w'\\*(12'\n.as 11 \"\\*(12\n.nr 11 \\w'\\*(11'\n.ds 12 \"ky\\(fm\\(fm\n.nr 12 \\w'\\*(12'\n.as 11 \"\\*(12\n.nr 11 \\w'\\*(11'\n.ds 12 \"\\*'\n.nr 12 \\w'\\*(12'\n'ps 8\n.ds 13 \"\\fR1\\fP\n.nr 13 \\w'\\*(13'\n.as 12 \\v'18u'\\s8\\*(13\\|\\s10\\v'-18u'\n'ps 10\n.nr 12 \\n(12+\\n(13+\\w'\\s8\\|'\n.as 11 \"\\*(12\n.nr 11 \\w'\\*(11'\n.ds 12 \",\n.nr 12 \\w'\\*(12'\n.as 11 \"\\*(12\n.nr 11 \\w'\\*(11'\n.ds 12 \"\\|\\|\n.nr 12 \\w'\\*(12'\n.as 11 \"\\*(12\n.nr 11 \\w'\\*(11'\n.ds 12 \"\\|\\|\n.nr 12 \\w'\\*(12'\n.as 11 \"\\*(12\n.nr 11 \\w'\\*(11'\n.ds 12 \"\\|\\|\n.nr 12 \\w'\\*(12'\n.as 11 \"\\*(12\n.nr 11 \\w'\\*(11'\n.ds 12 \"y\\(fm\\(fm\n.nr 12 \\w'\\*(12'\n.as 11 \"\\*(12\n.nr 11 \\w'\\*(11'\n.ds 12 \"\\*'\n.nr 12 \\w'\\*(12'\n'ps 8\n.ds 13 \"n\n.nr 13 \\w'\\*(13'\n.as 12 \\v'18u'\\s8\\*(13\\|\\s10\\v'-18u'\n'ps 10\n.nr 12 \\n(12+\\n(13+\\w'\\s8\\|'\n.as 11 \"\\*(12\n.nr 11 \\w'\\*(11'\n.ds 12 \"\\|\\|\n.nr 12 \\w'\\*(12'\n.as 11 \"\\*(12\n.nr 11 \\w'\\*(11'\n.ds 12 \"\\|=\\|\n.nr 12 \\w'\\*(12'\n.as 11 \"\\*(12\n.nr 11 \\w'\\*(11'\n.ds 12 \"\\|\\|\n.nr 12 \\w'\\*(12'\n.as 11 \"\\*(12\n.nr 11 \\w'\\*(11'\n.ds 12 \"ky\\(fm\\(fm\n.nr 12 \\w'\\*(12'\n.as 11 \"\\*(12\n.nr 11 \\w'\\*(11'\n.ds 12 \"\\*'\n.nr 12 \\w'\\*(12'\n'ps 8\n.ds 13 \"n\\|\\(mi\\|\\fR1\\fP\n.nr 13 \\w'\\*(13'\n.as 12 \\v'18u'\\s8\\*(13\\|\\s10\\v'-18u'\n'ps 10\n.nr 12 \\n(12+\\n(13+\\w'\\s8\\|'\n.as 11 \"\\*(12\n.nr 11 \\w'\\*(11'\n.ds 11 \\x'0'\\fI\\*(11\\s\\n(99\\f\\n(98\n.ne 78u\n\\*(11\n'ps \\n(99\n.ft \\n(98\n.EN\n..\n.if t .ig\n.ce\n(2nd deriv. at end) = k*(2nd deriv. next to end)\n..\n.IP\n.br\nis set by the next argument.\nBy default\n.IR k \"\"\n= 0.\n.TP 5\n.B  \\-n\nSpace output points\nso that approximately\n.I n\nintervals occur between the lower and upper\n.I x\nlimits.\n(Default\n.I n\n= 100.)\n.TP 5\n.B  \\-p\nMake output periodic, i.e. match\nderivatives at ends.\nFirst and last input values should normally agree.\n.TP 5\n.B  \\-x\nNext \n1 (or 2) arguments are lower (and upper) \n.I x\nlimits.\nNormally these limits are calculated from the data.\nAutomatic abcissas start at lower limit\n(default 0).\n.SH \"SEE ALSO\"\ngraph(1G), plot(1G)\n.SH DIAGNOSTICS\nWhen data is not strictly monotone in\n.I x,\n.I spline\nreproduces the input without interpolating extra points.\n.SH BUGS\nA limit of 1000 input points is enforced silently.\n"
  },
  {
    "path": "share/man/man1/split.1",
    "content": ".\\\"\t@(#)split.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH SPLIT 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nsplit \\- split a file into pieces\n.SH SYNOPSIS\n.B split\n[\n.B \\-\\fIn\n]\n[ file [ name ] ]\n.SH DESCRIPTION\n.I Split\nreads\n.I file\nand writes\nit in\n.IR n -line\npieces\n(default 1000), as many as necessary,\nonto\na set of output files.  The name of the first output\nfile is\n.I name\nwith\n.B aa\nappended, and so on\nlexicographically.\nIf no output name is given,\n.B x\nis default.\n.PP\nIf no input file is given, or\nif\n.B \\-\nis given in its stead,\nthen the standard input file is used.\n"
  },
  {
    "path": "share/man/man1/strcompact.1",
    "content": ".\\\" Public domain 1994 - Steven Schultz\n.\\\"\n.\\\"\t@(#)strcompact.1\t1.0 (2.11BSD GTE) 1/25/94\n.\\\"\n.TH STRCOMPACT 1 \"January 25, 1994\"\n.UC 2\n.SH NAME\nstrcompact \\- string compaction for object files\n.SH SYNOPSIS\nstrcompact [ \\fBobject_name\\fP ... ]\n.SH DESCRIPTION\nstrcompact\nscans the symbol and string tables of an object file looking for multiple\nreferences in the symbol table to the same string.  The string offset of\nsymbol table entries is updated to preserve only one copy of the string.\n.PP\n.B\nstrcompact\ncut the size of the kernel string table by about 25%.\n.PP\nThe user must have write permission to the object/executable file.\n.PP\n.B strcompact\nwrites to \\fIstderr\\fP the number of shared strings found.\n.PP\nstrcompact\nexits 0 if successful, and >0 if an error occurred.\n.SH SEE ALSO\nsort(1), symcompact(1), symorder(1), uniq(1)\n.SH BUGS\nExecution speed leaves much to be desired - on a 11/73 it takes about\n4 minutes to process the string table of the kernel.  Fortunately this\nis only done once when the kernel is created.\n.PP\nAlthough\n.B strcompact\nmay be run on .o files as well as executables but this is probably not\nworth the trouble since the linker will not create shared strings in the\nfinal executable.\n"
  },
  {
    "path": "share/man/man1/strings.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)strings.1\t6.2 (Berkeley) 5/12/86\n.\\\"\n.TH STRINGS 1 \"May 12, 1986\"\n.UC\n.SH NAME\nstrings \\- find the printable strings in a object, or other binary, file\n.SH SYNOPSIS\n.B strings\n[\n.B \\-\n] [\n.B \\-o\n] [\n\\fB\\-\\fInumber\\fR\n] file ...\n.SH DESCRIPTION\n.I Strings\nlooks for ascii strings in a binary file.\nA string is any sequence of 4 or more printing characters ending with\na newline or a null.\nUnless the\n.B \\-\nflag is given,\n.I strings\nonly looks in the initialized data space of object files.\nIf the\n.B \\-o\nflag is given, then each string is preceded by its offset in the\nfile (in octal).\nIf the\n\\fB\\-\\fInumber\\fR\nflag is given then number is used as the minimum string length\nrather than 4.\n.PP\n.I Strings\nis useful for identifying random object files and many other things.\n.SH \"SEE ALSO\"\nod(1)\n.SH BUGS\nThe algorithm for identifying strings is extremely primitive.\n"
  },
  {
    "path": "share/man/man1/strip.1",
    "content": ".\\\"\t@(#)strip.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH STRIP 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nstrip \\- remove symbols and relocation bits\n.SH SYNOPSIS\n.B strip\nname ...\n.SH DESCRIPTION\n.I Strip\nremoves the symbol\ntable and relocation bits ordinarily attached to the output\nof the assembler and loader.\nThis is useful to save space after a program has been\ndebugged.\n.PP\nThe effect of\n.I strip\nis the same as use of the\n.B \\-s\noption\nof\n.IR ld .\n.SH FILES\n/tmp/stm?\ttemporary file\n.SH \"SEE ALSO\"\nld(1)\n"
  },
  {
    "path": "share/man/man1/style.1",
    "content": ".\\\"\t@(#)style.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH STYLE 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nstyle  \\-  analyze surface characteristics of a document\n.SH SYNOPSIS\n.B style\n[\n.B \\-ml\n] [\n.B \\-mm\n] [\n.B \\-a\n] [\n.B \\-e\n] [\n.B \\-l\nnum ] [\n.B \\-r\nnum ] [\n.B \\-p\n] [\n.B \\-P\n]\nfile ...\n.LP\n.SH DESCRIPTION\n.I Style\nanalyzes the surface characteristics of the writing style\nof a document.\nIt reports on readability, sentence length and\nstructure, word length and usage, verb type, and sentence openers.\nBecause\n.I style\nruns\n.I deroff\nbefore looking at the text, formatting\nheader files should be included as part of the input.\nThe default macro package\n.B \\-ms\nmay be overridden with the flag\n.B \\-mm.\nThe flag\n.BR \\-ml ,\nwhich causes \n.B deroff\nto skip lists, should be used if the document contains many lists of\nnon-sentences.\nThe other options are used to locate sentences with certain characteristics.\n.TP\n.B \\-a\nprint all sentences with their length and readability index.\n.TP\n.B \\-e\nprint all sentences that begin with an expletive.\n.TP\n.B \\-p\nprint all sentences that contain a passive verb.\n.TP\n.BI \\-l num\nprint all sentences longer than\n.IR num .\n.TP\n.BI \\-r num\nprint all sentences whose readability index is greater than\n.IR num .\n.TP\n.B \\-P\nprint parts of speech of the words in the document.\n.SH \"SEE ALSO\"\nderoff(1), diction(1)\n.SH BUGS\nUse of non-standard formatting macros may cause\nincorrect sentence breaks.\n"
  },
  {
    "path": "share/man/man1/su.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)su.1\t6.2 (Berkeley) 5/5/86\n.\\\"\n.TH SU 1 \"May 5, 1986\"\n.UC\n.SH NAME\nsu \\- substitute user id temporarily\n.SH SYNOPSIS\n.B su\n[ \\-f ] [ \\- ] [ userid ]\n.SH DESCRIPTION\n.I Su\ndemands the password of the specified\n.I userid,\nand if it is given,\nchanges to that \n.I userid\nand invokes the Shell\n.IR sh (1)\nor\n.IR csh (1)\nwithout changing the current directory.\nThe user environment\nis unchanged except for HOME and SHELL,\nwhich are taken from the password file\nfor the user being substituted\n(see\n.IR environ (7)).\nThe new user ID stays in force until the Shell exits.\n.PP\nIf no \n.I userid\nis specified, ``root'' is assumed.\nOnly users in the ``wheel'' group (group 0) can\n.I su\nto ``root'', even with the root password.\nTo remind the super-user of his responsibilities,\nthe Shell substitutes `#' for its usual prompt.\n.PP\nThe\n.B \\-f\noption prevents\n.IR csh (1)\nfrom executing the .cshrc file; thus making\n.I su\nstart up faster.\n.PP\nThe\n.B \\-\noption simulates a full login.\n.SH \"SEE ALSO\"\nsh(1), csh(1)\n"
  },
  {
    "path": "share/man/man1/sum.1",
    "content": ".\\\"\t@(#)sum.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH SUM 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nsum \\- sum and count blocks in a file\n.SH SYNOPSIS\n.B sum\nfile\n.SH DESCRIPTION\n.I Sum\ncalculates and prints a 16-bit checksum for the named file,\nand also prints the number of blocks in the file.\nIt is typically used to look for bad spots, or\nto validate a file communicated over\nsome transmission line.\n.SH \"SEE ALSO\"\nwc(1)\n.SH DIAGNOSTICS\n`Read error'\nis indistinguishable from end of file on\nmost devices; check the block count.\n"
  },
  {
    "path": "share/man/man1/symcompact.1",
    "content": ".\\\" Public domain 1994 - Steven Schultz\n.\\\"\n.\\\"\t@(#)symcompact.1\t1.0 (2.11BSD GTE) 1/25/94\n.\\\"\n.TH SYMCOMPACT 1 \"January 25, 1994\"\n.UC 2\n.SH NAME\nsymcompact \\- string compaction for object files\n.SH SYNOPSIS\nsymcompact [ \\fBobject_name\\fP ... ]\n.SH DESCRIPTION\nsymcompact\nreduces the symbol table size of an executable file.  This is done by\nremoving unnecessary overlay transfer vectors (text symbols beginning with\na tilde).  In a nonoverlaid program there is no need for both the\nunderscore (_foo) and tilde (~foo) text symbol and only the underscore\nform is kept.  For overlaid programs\nif the symbol is in the base segment the tilde form is not needed and again\nonly the underscore form is preserved.  Running \\fBsymcompact\\fP typically\nreduces the kernel symbol table size by 250 or so symbols.\n.PP\nIt is possible to run both \\fBsymcompact\\fP and \\fBstrcompact\\fP to\nachieve an even higher degree of symbol and string table compaction.  The\nnormal sequence is to run \\fBsymcompact\\fP first followed by \\fBstrcompact\\fP.\nIf \\fBsymcompact\\fP runs out of memory it will be necessary to reverse the\norder and run \\fBsymcompact\\fP a second time - see the BUGS note below.\n.PP\nThe user must have write permission to the object/executable file.\n.PP\n.B\nsymcompact\nwrites to \\fIstderr\\fP the count of symbols removed from the symbol table.\n.PP\n.B\nsymcompact\nexits 0 if successful, and >0 if an error occurred.\n.SH SEE ALSO\nsymcompact(1), symorder(1)\n.SH BUGS\nThis program can partially negate the benefits of \\fBstrcompact\\fP because\nmultiple references to identical strings cause additional strings to be\nplaced in the string table.  Running \\fBstrcompact\\fP again after running\nthis program fixes this problem.\n.PP\nThe \\fIregister\\fP local symbol type is removed from the executable/object\nfile.  Since the debugger really doesn't know how to deal with those symbols\nthis is not much of a loss and saves quite a bit of space both in the\nsymbol table and the string table.\n.PP\n.B symcompact\nshould not be run on .o files that will be passed to the linker.  The linker\nwill need the tilde form of the symbol if an overlaid executable is being\ncreated.\n"
  },
  {
    "path": "share/man/man1/symorder.1",
    "content": ".\\\" Copyright (c) 1980, 1990 The Regents of the University of California.\n.\\\" All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)symorder.1\t6.5.1 (2.11BSD GTE) 1/22/94\n.\\\"\n.TH SYMORDER 1 \"January 22, 1994\"\n.UC 4\n.SH NAME\nsymorder \\- rearrange name list\n.SH SYNOPSIS\n.B symorder\nsymlist file\n.SH DESCRIPTION\nThe file\n.IR symlist\ncontains a list of symbols to be found in\n.IR file,\none symbol per line.\n.PP\nThe symbol table of\n.IR file\nis updated in place;\nsymbols read from\n.IR symlist\nare relocated to the beginning of the table and in the order given.\n.PP\nThis program was specifically designed to cut down on the\noverhead of getting symbols from the kernel name list.\n.SH DIAGNOSTICS\nThe\n.IR symorder (1)\nutility exits 0 on success, non zero if an error occurs.\n.SH SEE ALSO\nnm(1), nlist(3), strip(1)\n.SH HISTORY\nThe\n.B symorder\ncommand appeared in 3.0BSD.\n"
  },
  {
    "path": "share/man/man1/tabs.1",
    "content": ".\\\"\t@(#)tabs.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH TABS 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\ntabs \\- set terminal tabs\n.SH SYNOPSIS\n.B tabs\n[\n.B \\-n\n] [\nterminal\n]\n.SH DESCRIPTION\n.I Tabs\nsets the tabs on a variety of terminals.\nVarious terminal names given in\n.IR term (7)\nare recognized;\nthe default is, however, suitable for most 300\nbaud terminals.\nIf the\n.B \\-n\nflag is present then the left\nmargin is not indented as is normal.\n.SH SEE ALSO\nstty(1), term(7)\n.SH BUGS\nIt's much better to use\n.IR tset (1).\n"
  },
  {
    "path": "share/man/man1/tail.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)tail.1\t6.2 (Berkeley) 3/6/86\n.\\\"\n.TH TAIL 1 \"March 6, 1986\"\n.UC 4\n.SH NAME\ntail \\- deliver the last part of a file\n.SH SYNOPSIS\n.B tail\n.if t [ \\(+-number[\\fBlbc\\fR][\\fBfr\\fR] ]\n.if n +\b_number[l\b_b\b_c\b_][r\b_f\b_]\n[ file ]\n.SH DESCRIPTION\n.I Tail\ncopies the named file to the standard output beginning\nat a designated place.\nIf no file is named, the standard input is used.\n.PP\nCopying begins at distance\n.I +number\nfrom the beginning, or\n.I \\-number\nfrom the end of the input.\n.I Number\nis counted in units of lines, blocks or characters,\naccording to the appended option\n.B l,\n.B b\nor\n.B c.\nWhen no units are specified, counting is by lines.\n.PP\nSpecifying\n.B r\ncauses tail to print lines from the end of the file in reverse order.\nThe default for\n.B r\nis to print the entire file this way.\nSpecifying\n.B f\ncauses\n.I tail\nto not quit at end of file, but rather wait and try to read repeatedly\nin hopes that the file will grow.\n.SH \"SEE ALSO\"\ndd(1)\n.SH BUGS\nTails relative to the end of the file\nare treasured up in a buffer, and thus \nare limited in length.\n.PP\nVarious kinds of anomalous behavior may happen\nwith character special files.\n"
  },
  {
    "path": "share/man/man1/talk.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)talk.1\t6.2.1 (2.11BSD) 1996/11/27\n.\\\"\n.TH TALK 1 \"November 27, 1996\"\n.UC 5\n.SH NAME\ntalk \\- talk to another user\n.SH SYNOPSIS\n.B talk\nperson [ ttyname ]\n.SH DESCRIPTION\n.I Talk\nis a visual communication program which\ncopies lines from your terminal to that of\nanother user.\n.PP \nIf you wish to talk to someone on you own machine, then\n.I person\nis just the person's login name. If you wish to talk to\na user on another host, then\n.I person\nis of the form :\n.sp\n.in +2.0i\n.I host!user\n\\ or\n.br\n.I host.user\n\\ or\n.br\n.I host:user\n\\ or\n.br\n.I user@host\n.br\n.in -2.0i\n.sp\nthough\n.I host@user \nis perhaps preferred.\n.PP\nIf you want to talk to a user who is logged in more than once,\nthe\n.I ttyname\nargument may be used to indicate the\nappropriate terminal name.\n.PP\nWhen first called,\nit sends the message\n.PP\n     Message from TalkDaemon@his_machine...\n     talk: connection requested by your_name@your_machine.\n     talk: respond with: talk your_name@your_machine\n.PP\nto the user you wish to talk to. At this point, the recipient\nof the message should reply by \ntyping \n.PP\n     talk \\ your_name@your_machine\n.PP\nIt doesn't matter from \nwhich machine the recipient replies, as long as his login-name is\nthe same.\nOnce communication is established, the two parties may type \nsimultaneously, with their output appearing in separate windows. \nTyping control L will cause the screen to be reprinted, while your \nerase, kill, and word kill characters will work in talk as normal.\nTo exit,\njust type your interrupt character;\n.I talk\nthen moves the cursor to the bottom of the screen and restores \nthe terminal.\n.PP\nPermission to talk may be denied or granted by use of the\n.I mesg\ncommand.\nAt the outset talking is allowed.\nCertain commands, in particular\n.I nroff\nand\n.IR  pr (1)\ndisallow\nmessages in order to prevent messy output.\n.PP\n.SH FILES\n/etc/hosts\tto find the recipient's machine\n.br\n/var/run/utmp\tto find the recipient's tty\n.SH \"SEE ALSO\"\nmesg(1), who(1), mail(1), write(1)\n.SH BUGS\nThe version of \n.IR talk (1)\nreleased with 4.3BSD uses a protocol that is incompatible\nwith the protocol used in the version released with 4.2BSD.\n"
  },
  {
    "path": "share/man/man1/tar.1",
    "content": ".\\\"\t@(#)tar.1\t6.5 (Berkeley) 5/12/86\n.\\\"\n.TH TAR 1 \"May 12, 1986\"\n.AT 3\n.SH NAME\ntar \\- tape archiver\n.SH SYNOPSIS\n.B tar\n[ key ] [ name ... ]\n.SH DESCRIPTION\n.PP\n.I Tar\nsaves and restores multiple files on a single file (usually a magnetic\ntape, but it can be any file).  \n.IR Tar 's\nactions are controlled by the\n.I key\nargument.  The\n.I key\nis a string of characters containing at most one function letter and possibly\none or more function modifiers.  Other arguments to \n.I tar\nare file or directory names specifying which files to dump or restore.\nIn all cases, appearance of a directory name refers to\nthe files and (recursively) subdirectories of that directory.\n.PP\nThe function portion of the key is specified by one of the following letters:\n.TP 8\n.B r\nThe named files are written on the end of the tape.  The\n.B c\nfunction implies this.\n.TP 8\n.B x\nThe named files are extracted from the tape.  If the named file\nmatches a directory whose contents had been written onto the tape, this\ndirectory is (recursively) extracted.  The owner, modification time, and mode\nare restored (if possible).  If no file argument is given, the entire content\nof the tape is extracted.  Note that if multiple entries specifying the same\nfile are on the tape, the last one overwrites all earlier.\n.TP 8\n.B t\nThe names of the specified files are listed each time they occur on\nthe tape.  If no file argument is given, all of the names on the tape\nare listed.\n.TP 8\n.B u\nThe named files are added to the tape if either they are not\nalready there or have been modified since last put on the tape.\n.TP 8\n.B c\nCreate a new tape; writing begins on the beginning of the tape\ninstead of after the last file.  This command implies\n.BR r .\n.PP\nThe following characters may be used in addition to the letter\nwhich selects the function desired.\n.TP 10\n.B o\nOn output, tar normally places information specifying owner and modes\nof directories in the archive.  Former versions of tar, when encountering\nthis information will give error message of the form\n.br\n\t\"<name>/: cannot create\".\n.br\nThis modifier will suppress the directory information.\n.TP 10\n.B p\nThis modifier says to restore files to their original modes,\nignoring the present\n.IR umask (2).\nSetuid and sticky information\nwill also be restored to the super-user.\n.TP 10\n.B 0, ..., 9\nThis modifier selects an alternate drive on which the tape is mounted.\nThe default is drive 0 at 1600 bpi, which is normally /dev/rmt8.\n.TP 10\n.B v\nNormally\n.I tar\ndoes its work silently.  The\n.B v\n(verbose) option makes\n.I tar\nprint the name of each file it treats preceded by the function\nletter.  With the\n.B t\nfunction, the verbose option\ngives more information about the tape entries than just their names.\n.TP 10\n.B w\n.I Tar\nprints the action to be taken followed by file name, then\nwait for user confirmation. If a word beginning with `y'\nis given, the action is done. Any other input means don't do it.\n.TP 10\n.B f\n.I Tar\nuses the next argument as the name of the archive instead of\n/dev/rmt?. If the name of the file is `\\-', tar writes to standard output or\nreads from standard input, whichever is appropriate. Thus,\n.I tar\ncan be used as the head or tail of a filter chain.\n.I Tar\ncan also be used to move hierarchies with the command\n.ce 1\ncd fromdir; tar cf - . | (cd todir; tar xf -)\n.TP 10\n.B b\n.I Tar\nuses the next argument as the blocking factor for tape records. The\ndefault is 20 (the maximum). This option should only be used with raw magnetic\ntape archives (See \n.B f\nabove).  The block size is determined automatically\nwhen reading tapes (key letters `x' and `t').\n.TP 10\n.B l\ntells \n.I tar\nto complain if it cannot resolve all of the links to the\nfiles dumped.  If this is not specified, no error messages are printed.\n.TP 10\n.B m\ntells \n.I tar\nnot to restore the modification times.  The modification time\nwill be the time of extraction.\n.TP 10\n.B h\nForce \n.I tar\nto follow symbolic links as if they were normal files or\ndirectories.  Normally, \n.I tar\ndoes not follow symbolic links.\n.TP 10\n.B B\nForces input and output blocking to 20 blocks per record.  This option\nwas added so that \n.I tar\ncan work across a communications channel where the blocking may not\nbe maintained.\n.TP 10\n.B C\nIf a file name is preceded by \n.BR \\-C ,\nthen \n.I tar\nwill perform a\n.IR chdir (2)\nto that file name.  This allows multiple directories not\nrelated by a close common parent to be archived using short\nrelative path names.  For example, to archive files from /usr/include\nand from /etc, one might use\n.ti +0.5i\ntar c -C /usr include -C / etc\n.PP\nPrevious restrictions dealing with\n.IR tar 's\ninability to properly handle blocked archives have been lifted.\n.PP\n.SH FILES\n/dev/rmt?\n.br\n/tmp/tar*\n.SH \"SEE ALSO\"\ntar(5)\n.SH DIAGNOSTICS\nComplaints about bad key characters and tape read/write errors.\n.br\nComplaints if enough memory is not available to hold the link tables.\n.SH BUGS\nThere is no way to ask for the\n.IR n -th\noccurrence of a file.\n.br\nTape errors are handled ungracefully.\n.br\nThe \n.B u\noption can be slow.\n.br\nThe current limit on file name length is 100 characters.\n.br\nThere is no way selectively to follow symbolic links.\n.br\nWhen extracting tapes created with the\n.B r\nor\n.B u\noptions, directory modification times may not be set correctly.\n"
  },
  {
    "path": "share/man/man1/tbl.1",
    "content": ".\\\"\t@(#)tbl.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH TBL 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\ntbl \\- format tables for nroff or troff\n.SH SYNOPSIS\n.B tbl\n[ files ] ...\n.SH DESCRIPTION\n.I Tbl\nis a preprocessor for formatting tables for\n.I nroff\nor\n.IR troff (1).\nThe input files are copied to the standard output, except for lines between\n.TS and .TE command lines, which are assumed to describe tables\nand are reformatted.\nDetails are given in the \n.IR tbl (1)\nreference manual.\n.SH EXAMPLE\n.PP\nAs an example, letting \\\\t represent a tab (which should be typed as a genuine\ntab) the input\n.IP \"\"\n\\&.TS\n.nf\nc s s\nc c s\nc c c\nl n n.\nHousehold Population\nTown\\\\tHouseholds\n\\\\tNumber\\\\tSize\nBedminster\\\\t789\\\\t3.26\nBernards Twp.\\\\t3087\\\\t3.74\nBernardsville\\\\t2018\\\\t3.30\nBound Brook\\\\t3425\\\\t3.04\nBranchburg\\\\t1644\\\\t3.49\nBridgewater\\\\t7897\\\\t3.81\nFar Hills\\\\t240\\\\t3.19\n\\&.TE\n.LP\n.fi\nyields\n.ne 10\n.IP \" \"\n.TS\n.nr 35 \\n(.u\n.nf\n.nr 79 0n\n.nr 80 \\n(79\n.nr 40 \\n(79\n.nr 38 \\n(79+\\w!Town!\n.if \\n(80<\\n(38 .nr 80 \\n(38\n.nr 38 \\n(79+\\w!!\n.if \\n(80<\\n(38 .nr 80 \\n(38\n.nr 38 \\n(79+\\w!Bedminster!\n.if \\n(80<\\n(38 .nr 80 \\n(38\n.nr 38 \\n(79+\\w!Bernards Twp.!\n.if \\n(80<\\n(38 .nr 80 \\n(38\n.nr 38 \\n(79+\\w!Bernardsville!\n.if \\n(80<\\n(38 .nr 80 \\n(38\n.nr 38 \\n(79+\\w!Bound Brook!\n.if \\n(80<\\n(38 .nr 80 \\n(38\n.nr 38 \\n(79+\\w!Branchburg!\n.if \\n(80<\\n(38 .nr 80 \\n(38\n.nr 38 \\n(79+\\w!Bridgewater!\n.if \\n(80<\\n(38 .nr 80 \\n(38\n.nr 38 \\n(79+\\w!Far Hills!\n.if \\n(80<\\n(38 .nr 80 \\n(38\n.nr 81 \\n(80\n.nr 41 \\n(80\n.nr 38 \\n(80+\\w!Number!\n.if \\n(81<\\n(38 .nr 81 \\n(38\n.nr 31 0\n.nr 32 0\n.nr 38 \\w!789!\n.if \\n(31<\\n(38 .nr 31 \\n(38\n.nr 38 \\w!!\n.if \\n(32<\\n(38 .nr 32 \\n(38\n.nr 38 \\w!3087!\n.if \\n(31<\\n(38 .nr 31 \\n(38\n.nr 38 \\w!!\n.if \\n(32<\\n(38 .nr 32 \\n(38\n.nr 38 \\w!2018!\n.if \\n(31<\\n(38 .nr 31 \\n(38\n.nr 38 \\w!!\n.if \\n(32<\\n(38 .nr 32 \\n(38\n.nr 38 \\w!3425!\n.if \\n(31<\\n(38 .nr 31 \\n(38\n.nr 38 \\w!!\n.if \\n(32<\\n(38 .nr 32 \\n(38\n.nr 38 \\w!1644!\n.if \\n(31<\\n(38 .nr 31 \\n(38\n.nr 38 \\w!!\n.if \\n(32<\\n(38 .nr 32 \\n(38\n.nr 38 \\w!7897!\n.if \\n(31<\\n(38 .nr 31 \\n(38\n.nr 38 \\w!!\n.if \\n(32<\\n(38 .nr 32 \\n(38\n.nr 38 \\w!240!\n.if \\n(31<\\n(38 .nr 31 \\n(38\n.nr 38 \\w!!\n.if \\n(32<\\n(38 .nr 32 \\n(38\n.nr 61 \\n(80+\\n(31\n.nr 38 \\n(61+\\n(32\n.if \\n(38>\\n(81 .nr 81 \\n(38\n.if \\n(38<\\n(81 .nr 61 +(\\n(81-\\n(38)/2\n.nr 82 \\n(81\n.nr 42 \\n(81\n.nr 38 \\n(81+\\w!Size!\n.if \\n(82<\\n(38 .nr 82 \\n(38\n.nr 31 0\n.nr 32 0\n.nr 38 \\w!3!\n.if \\n(31<\\n(38 .nr 31 \\n(38\n.nr 38 \\w!.26!\n.if \\n(32<\\n(38 .nr 32 \\n(38\n.nr 38 \\w!3!\n.if \\n(31<\\n(38 .nr 31 \\n(38\n.nr 38 \\w!.74!\n.if \\n(32<\\n(38 .nr 32 \\n(38\n.nr 38 \\w!3!\n.if \\n(31<\\n(38 .nr 31 \\n(38\n.nr 38 \\w!.30!\n.if \\n(32<\\n(38 .nr 32 \\n(38\n.nr 38 \\w!3!\n.if \\n(31<\\n(38 .nr 31 \\n(38\n.nr 38 \\w!.04!\n.if \\n(32<\\n(38 .nr 32 \\n(38\n.nr 38 \\w!3!\n.if \\n(31<\\n(38 .nr 31 \\n(38\n.nr 38 \\w!.49!\n.if \\n(32<\\n(38 .nr 32 \\n(38\n.nr 38 \\w!3!\n.if \\n(31<\\n(38 .nr 31 \\n(38\n.nr 38 \\w!.81!\n.if \\n(32<\\n(38 .nr 32 \\n(38\n.nr 38 \\w!3!\n.if \\n(31<\\n(38 .nr 31 \\n(38\n.nr 38 \\w!.19!\n.if \\n(32<\\n(38 .nr 32 \\n(38\n.nr 62 \\n(81+\\n(31\n.nr 38 \\n(62+\\n(32\n.if \\n(38>\\n(82 .nr 82 \\n(38\n.if \\n(38<\\n(82 .nr 62 +(\\n(82-\\n(38)/2\n.nr 38 \\n(79+\\w!Household Population!-\\n(82\n.if \\n(38>0 .nr 38 \\n(38/2\n.if \\n(38<0 .nr 38 0\n.nr 61 +1*\\n(38\n.nr 81 +1*\\n(38\n.nr 41 +1*\\n(38\n.nr 62 +2*\\n(38\n.nr 82 +2*\\n(38\n.nr 42 +2*\\n(38\n.nr 38 \\n(80+\\w!Households!-\\n(82\n.if \\n(38>0 .nr 38 \\n(38/1\n.if \\n(38<0 .nr 38 0\n.nr 62 +1*\\n(38\n.nr 82 +1*\\n(38\n.nr 42 +1*\\n(38\n.nr 38 1n\n.nr 41 +3*\\n(38\n.nr 81 +3*\\n(38\n.nr 61 +3*\\n(38\n.if n .if \\n(61%24>0 .nr 61 +12u\n.nr 42 +6*\\n(38\n.nr 82 +6*\\n(38\n.nr 62 +6*\\n(38\n.if n .if \\n(62%24>0 .nr 62 +12u\n.nr TW \\n(82\n.fc ! :\n.ta \\n(82u \n\\&!:Household Population:!\n.ta \\n(80u \\n(82u \n\\&\\h'|\\n(40u'!:Town:!\\h'|\\n(41u'!:Households:!\n.ta \\n(80u \\n(81u \\n(82u \n\\&\\h'|\\n(40u'!::!\\h'|\\n(41u'!:Number:!\\h'|\\n(42u'!:Size:!\n.ta \\n(80u \\n(61u \\n(62u \\n(82u \n\\&\\h'|\\n(40u'!Bedminster:!\\h'|\\n(41u'!:789!\\h'|\\n(42u'!:3!!.26:!\n.ta \\n(80u \\n(61u \\n(62u \\n(82u \n\\&\\h'|\\n(40u'!Bernards Twp.:!\\h'|\\n(41u'!:3087!\\h'|\\n(42u'!:3!!.74:!\n.ta \\n(80u \\n(61u \\n(62u \\n(82u \n\\&\\h'|\\n(40u'!Bernardsville:!\\h'|\\n(41u'!:2018!\\h'|\\n(42u'!:3!!.30:!\n.ta \\n(80u \\n(61u \\n(62u \\n(82u \n\\&\\h'|\\n(40u'!Bound Brook:!\\h'|\\n(41u'!:3425!\\h'|\\n(42u'!:3!!.04:!\n.ta \\n(80u \\n(61u \\n(62u \\n(82u \n\\&\\h'|\\n(40u'!Branchburg:!\\h'|\\n(41u'!:1644!\\h'|\\n(42u'!:3!!.49:!\n.ta \\n(80u \\n(61u \\n(62u \\n(82u \n\\&\\h'|\\n(40u'!Bridgewater:!\\h'|\\n(41u'!:7897!\\h'|\\n(42u'!:3!!.81:!\n.ta \\n(80u \\n(61u \\n(62u \\n(82u \n\\&\\h'|\\n(40u'!Far Hills:!\\h'|\\n(41u'!:240!\\h'|\\n(42u'!:3!!.19:!\n.fc\n.mk ##\n.nr ## -1v\n.if \\n(35>0 .fi\n.TE\n.fi\n.PP\nIf no arguments are given,\n.I tbl\nreads the standard input, so it may be used as a filter.  When \n.I tbl\nis used with\n.I eqn\nor\n.I neqn\nthe\n.I tbl\ncommand should be first, to minimize the volume of data passed through pipes.\n.SH SEE ALSO\ntroff(1), eqn(1)\n.br\nM. E. Lesk,\n.I TBL.\n"
  },
  {
    "path": "share/man/man1/tc.1",
    "content": ".\\\"\t@(#)tc.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH TC 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\ntc \\- photoypesetter simulator\n.SH SYNOPSIS\n.B tc\n[\n.B \\-t\n]\n[\n.B \\-s\\c\nN\n]\n[\n.B \\-p\\c\nL\n]\n[\nfile\n]\n.SH DESCRIPTION\n.I Tc\ninterprets its\ninput (standard input default)\nas device codes for a Graphic Systems phototypesetter (cat).\nThe standard output of\n.I tc\nis intended for a Tektronix 4015 (a 4014 terminal\nwith ASCII and APL character sets).\nThe sixteen typesetter sizes are mapped into the 4014's\nfour sizes;\nthe entire TROFF character set is drawn using the 4014's\ncharacter generator,\nusing overstruck combinations where necessary.\nTypical usage:\n.IP \"\" 15\ntroff \\-t file | tc\n.PP\nAt the end of each page\n.I tc\nwaits for a newline (empty line) from the keyboard before\ncontinuing on to the next page.\nIn this wait state, the command\n.B e\nwill suppress the screen erase before the next page;\n.B s\\c\nN will cause the next N pages to be skipped;\nand\n.B !\\c\nline will send line to the shell.\n.PP\nThe command line options are:\n.TP\n.B  \\-t\nDon't wait between pages; for directing output into a file.\n.TP \n.BR \\-s N\nSkip the first N pages.\n.TP \n.BR \\-p L\nSet page length to L.\nL may include the scale factors\n.B p\n(points),\n.B i\n(inches),\n.B c\n(centimeters),\nand\n.B P\n(picas);\ndefault is picas.\n.TP\n.BI \\(fm\\- l\\ w \\(fm\nMultiply the default aspect ratio, 1.5, of a displayed page\nby\n.I l/w.\n.SH \"SEE ALSO\"\ntroff(1),\nplot(1G)\n.SH BUGS\nFont distinctions are lost.\n.br\n.IR tc 's\ncharacter set is limited to ASCII in just one size.\n.br\nThe aspect ratio option is unbelievable.\n"
  },
  {
    "path": "share/man/man1/tcopy.1",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)tcopy.1\t6.1 (Berkeley) 12/11/85\n.\\\"\n.TH TCOPY 1 \"December 11, 1985\"\n.UC 6\n.SH NAME\ntcopy \\- copy a mag tape\n.SH SYNOPSIS\n.B tcopy src\n[\n.B dest\n]\n.br\n.SH DESCRIPTION\n.I Tcopy\nis designed to copy magnetic tapes.  The only assumption made about\nthe tape is that there are two tape marks at the end.\n.I Tcopy\nwith only a source tape specified will print information about the\nsizes of records and tape files.  If a destination is specified,\nthen, a copy will be made of the source tape.  The blocking on the\ndestination tape will be identical to that used on the source tape.\nCopying a tape will yield the same output as if just printing the\nsizes.\n.SH \"SEE ALSO\"\nmtio(4)\n"
  },
  {
    "path": "share/man/man1/tee.1",
    "content": ".\\\"\t@(#)tee.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH TEE 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\ntee \\- pipe fitting\n.SH SYNOPSIS\n.B tee\n[\n.B \\-i\n] [\n.B \\-a\n]\n[ file ] ...\n.SH DESCRIPTION\n.I Tee\ntranscribes the standard input to the standard\noutput and makes copies in the \n.I files.\nOption\n.B \\-i\nignores interrupts;\noption\n.B \\-a\ncauses the output to be appended to the\n.I files\nrather than overwriting them.\n"
  },
  {
    "path": "share/man/man1/telnet.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)telnet.1c\t6.5 (Berkeley) 5/10/86\n.\\\"\n.TH TELNET 1C \"May 10, 1986\"\n.UC 5\n.SH NAME\ntelnet \\- user interface to the \\s-1TELNET\\s0 protocol\n.SH SYNOPSIS\ntelnet [ host [ port ] ]\n.SH DESCRIPTION\n.I Telnet\nis used to communicate with another host using the\n.B TELNET\nprotocol.\nIf \n.I telnet\nis invoked without arguments, it enters command mode,\nindicated by its prompt (\\*(lqtelnet>\\*(rq).\nIn this mode, it accepts and executes the commands listed below.\nIf it is invoked with arguments, it performs an\n.B open\ncommand (see below) with those arguments.\n.PP\nOnce a connection has been opened,\n.I telnet\nenters an input mode.\nThe input mode entered will be either \\*(lqcharacter at a time\\*(rq\nor \\*(lqline by line\\*(rq\ndepending on what the remote system supports.\n.PP\nIn \\*(lqcharacter at a time\\*(rq mode, most\ntext typed is immediately sent to the remote host for processing.\n.PP\nIn \\*(lqline by line\\*(rq mode, all text is echoed locally,\nand (normally) only completed lines are sent to the remote host.\nThe \\*(lqlocal echo character\\*(rq (initially \\*(lq^E\\*(rq) may be used\nto turn off and on the local echo\n(this would mostly be used to enter passwords\nwithout the password being echoed).\n.PP\nIn either mode, if the\n.I localchars\ntoggle is TRUE (the default in line mode; see below),\nthe user's\n.IR quit ,\n.IR intr ,\nand\n.I flush\ncharacters are trapped locally, and sent as\n.B TELNET\nprotocol sequences to the remote side.\nThere are options (see\n.B toggle\n.I autoflush\nand\n.B toggle\n.I autosynch\nbelow)\nwhich cause this action to flush subsequent output to the terminal\n(until the remote host acknowledges the\n.B TELNET\nsequence) and flush previous terminal input\n(in the case of\n.I quit\nand\n.IR intr ).\n.PP\nWhile connected to a remote host,\n.I telnet\ncommand mode may be entered by typing the\n.I telnet\n\\*(lqescape character\\*(rq (initially \\*(lq^]\\*(rq).\nWhen in command mode, the normal terminal editing conventions are available.\n.PP\n.B COMMANDS\n.PP\nThe following commands are available.\nOnly enough of each command to uniquely identify it need be typed\n(this is also true for arguments to the\n.BR mode ,\n.BR set ,\n.BR toggle ,\nand\n.B display\ncommands).\n.PP\n.TP\n.B open \\fIhost\\fP \\fR[\\fP \\fIport\\fP \\fR]\\fP\n.br\nOpen a connection to the named host.\nIf no port number\nis specified, \n.I telnet\nwill attempt to contact a\n.B TELNET\nserver at the default port.\nThe host specification may be either a host name (see \n.IR hosts (5))\nor an Internet address specified in the \\*(lqdot notation\\*(rq (see\n.IR inet (3N)).\n.TP\n.B close\n.br\nClose a\n.B TELNET\nsession and return to command mode.\n.TP\n.B quit\n.br\nClose any open\n.B TELNET\nsession and exit \n.IR telnet .\nAn end of file (in command mode) will also close a session and exit.\n.TP\n.B z\n.br\nSuspend\n.IR telnet .\nThis command only works when the user is using the \n.IR csh (1).\n.TP\n.B mode \\fItype\\fP\n.br\n.I Type\nis either\n.I line\n(for \\*(lqline by line\\*(rq mode)\nor\n.I character\n(for \\*(lqcharacter at a time\\*(rq mode).\nThe remote host is asked for permission to go into the requested mode.\nIf the remote host is capable of entering that mode, the requested\nmode will be entered.\n.TP\n.B status\n.br\nShow the current status of \n.IR telnet .\nThis includes the peer one is connected to, as well\nas the current mode.\n.TP\n.B display \\fR[\\fP \\fIargument...\\fP \\fR]\\fP\n.br\nDisplays all, or some, of the\n.B set\nand\n.B toggle\nvalues (see below).\n.TP\n.B ? \\fR[\\fP \\fIcommand\\fP \\fR]\\fP\n.br\nGet help.  With no arguments,\n.I telnet\nprints a help summary.\nIf a command is specified, \n.I telnet\nwill print the help information for just that command.\n.TP\n.B send \\fIarguments\\fP\n.br\nSends one or more special character sequences to the remote host.\nThe following are the arguments which may be specified\n(more than one argument may be specified at a time):\n.RS\n.TP\n.I escape\n.br\nSends the current\n.I telnet\nescape character (initially \\*(lq^]\\*(rq).\n.TP\n.I synch\n.br\nSends the\n.B TELNET SYNCH\nsequence.\nThis sequence causes the remote system to discard all previously typed\n(but not yet read) input.\nThis sequence is sent as TCP urgent\ndata (and may not work if the remote system is a 4.2 BSD system -- if\nit doesn't work, a lower case \\*(lqr\\*(rq may be echoed on the terminal).\n.TP\n.I brk\n.br\nSends the\n.B TELNET BRK\n(Break) sequence, which may have significance to the remote\nsystem.\n.TP\n.I ip\n.br\nSends the\n.B TELNET IP\n(Interrupt Process) sequence, which should cause the remote\nsystem to abort the currently running process.\n.TP\n.I ao\n.br\nSends the\n.B TELNET AO\n(Abort Output) sequence, which should cause the remote system to flush\nall output\n.B from\nthe remote system\n.B to\nthe user's terminal.\n.TP\n.I ayt\n.br\nSends the\n.B TELNET AYT\n(Are You There)\nsequence, to which the remote system may or may not choose to respond.\n.TP\n.I ec\n.br\nSends the\n.B TELNET EC\n(Erase Character)\nsequence, which should cause the remote system to erase the last character\nentered.\n.TP\n.I el\n.br\nSends the\n.B TELNET EL\n(Erase Line)\nsequence, which should cause the remote system to erase the line currently\nbeing entered.\n.TP\n.I ga\n.br\nSends the\n.B TELNET GA\n(Go Ahead)\nsequence, which likely has no significance to the remote system.\n.TP\n.I nop\n.br\nSends the\n.B TELNET NOP\n(No OPeration)\nsequence.\n.TP\n.I ?\n.br\nPrints out help information for the\n.B send\ncommand.\n.RE\n.TP\n.B set \\fIargument value\\fP\n.br\nSet any one of a number of\n.I telnet\nvariables to a specific value.\nThe special value \\*(lqoff\\*(rq turns off the function associated with\nthe variable.\nThe values of variables may be interrogated with the\n.B display\ncommand.\nThe variables which may be specified are:\n.RS\n.TP\n.I echo\n.br\nThis is the value (initially \\*(lq^E\\*(rq) which, when in\n\\*(lqline by line\\*(rq mode, toggles between doing local echoing\nof entered characters (for normal processing), and suppressing\nechoing of entered characters (for entering, say, a password).\n.TP\n.I escape\n.br\nThis is the\n.I telnet\nescape character (initially \\*(lq^[\\*(rq) which causes entry\ninto\n.I telnet\ncommand mode (when connected to a remote system).\n.TP\n.I interrupt\n.br\nIf\n.I telnet\nis in\n.I localchars\nmode (see\n.B toggle\n.I localchars\nbelow)\nand the\n.I interrupt\ncharacter is typed, a\n.B TELNET IP\nsequence (see\n.B send\n.I ip\nabove)\nis sent to the remote host.\nThe initial value for the interrupt character is taken to be\nthe terminal's\n.B intr\ncharacter.\n.TP\n.I quit\n.br\nIf\n.I telnet\nis in\n.I localchars\nmode (see\n.B toggle\n.I localchars\nbelow)\nand the\n.I quit\ncharacter is typed, a\n.B TELNET BRK\nsequence (see\n.B send\n.I brk\nabove)\nis sent to the remote host.\nThe initial value for the quit character is taken to be\nthe terminal's\n.B quit\ncharacter.\n.TP\n.I flushoutput\n.br\nIf\n.I telnet\nis in\n.I localchars\nmode (see\n.B toggle\n.I localchars\nbelow)\nand the\n.I flushoutput\ncharacter is typed, a\n.B TELNET AO\nsequence (see\n.B send\n.I ao\nabove)\nis sent to the remote host.\nThe initial value for the flush character is taken to be\nthe terminal's\n.B flush\ncharacter.\n.TP\n.I erase\n.br\nIf\n.I telnet\nis in\n.I localchars\nmode (see\n.B toggle\n.I localchars\nbelow),\n.B and\nif\n.I telnet\nis operating in \\*(lqcharacter at a time\\*(rq mode, then when this\ncharacter is typed, a\n.B TELNET EC\nsequence (see\n.B send\n.I ec\nabove)\nis sent to the remote system.\nThe initial value for the erase character is taken to be\nthe terminal's\n.B erase\ncharacter.\n.TP\n.I kill\n.br\nIf\n.I telnet\nis in\n.I localchars\nmode (see\n.B toggle\n.I localchars\nbelow),\n.B and\nif\n.I telnet\nis operating in \\*(lqcharacter at a time\\*(rq mode, then when this\ncharacter is typed, a\n.B TELNET EL\nsequence (see\n.B send\n.I el\nabove)\nis sent to the remote system.\nThe initial value for the kill character is taken to be\nthe terminal's\n.B kill\ncharacter.\n.TP\n.I eof\n.br\nIf\n.I telnet\nis operating in \\*(lqline by line\\*(rq mode, entering this character\nas the first character on a line will cause this character to be\nsent to the remote system.\nThe initial value of the eof character is taken to be the terminal's\n.B eof\ncharacter.\n.RE\n.TP\n.B toggle \\fIarguments...\\fP\n.br\nToggle (between\nTRUE\nand\nFALSE)\nvarious flags that control how\n.I telnet\nresponds to events.\nMore than one argument may be specified.\nThe state of these flags may be interrogated with the\n.B display\ncommand.\nValid arguments are:\n.RS\n.TP\n.I localchars\n.br\nIf this is\nTRUE,\nthen the\n.IR flush ,\n.IR interrupt ,\n.IR quit ,\n.IR erase ,\nand\n.I kill\ncharacters (see\n.B set\nabove) are recognized locally, and transformed into (hopefully) appropriate\n.B TELNET\ncontrol sequences\n(respectively\n.IR ao ,\n.IR ip ,\n.IR brk ,\n.IR ec ,\nand\n.IR el ;\nsee\n.B send\nabove).\nThe initial value for this toggle is TRUE in \\*(lqline by line\\*(rq mode,\nand FALSE in \\*(lqcharacter at a time\\*(rq mode.\n.TP\n.I autoflush\n.br\nIf\n.I autoflush\nand\n.I localchars\nare both\nTRUE,\nthen when the\n.IR ao ,\n.IR intr ,\nor\n.I quit\ncharacters are recognized (and transformed into\n.B TELNET\nsequences; see\n.B set\nabove for details),\n.I telnet\nrefuses to display any data on the user's terminal\nuntil the remote system acknowledges (via a\n.B TELNET\n.I Timing Mark\noption)\nthat it has processed those\n.B TELNET\nsequences.\nThe initial value for this toggle is TRUE if the terminal user had not\ndone an \"stty noflsh\", otherwise FALSE (see\n.IR stty(1)).\n.TP\n.I autosynch\nIf\n.I autosynch\nand\n.I localchars\nare both\nTRUE,\nthen when either the\n.I intr\nor\n.I quit\ncharacters is typed (see\n.B set\nabove for descriptions of the\n.I intr\nand\n.I quit\ncharacters), the resulting\n.B TELNET\nsequence sent is followed by the\n.B TELNET SYNCH\nsequence.\nThis procedure\n.B should\ncause the remote system to begin throwing away all previously\ntyped input until both of the\n.B TELNET\nsequences have been read and acted upon.\nThe initial value of this toggle is FALSE.\n.TP\n.I crmod\n.br\nToggle carriage return mode.\nWhen this mode is enabled, most carriage return characters received from\nthe remote host will be mapped into a carriage return followed by\na line feed.\nThis mode does not affect those characters typed by the user, only\nthose received from the remote host.\nThis mode is not very useful unless the remote host\nonly sends carriage return, but never line feed.\nThe initial value for this toggle is FALSE.\n.TP\n.I debug\n.br\nToggles socket level debugging (useful only to the\n.IR super user ).\nThe initial value for this toggle is FALSE.\n.TP\n.I options\n.br\nToggles the display of some internal\n.I telnet\nprotocol processing (having to do with\n.B TELNET\noptions).\nThe initial value for this toggle is FALSE.\n.TP\n.I netdata\n.br\nToggles the display of all network data (in hexadecimal format).\nThe initial value for this toggle is FALSE.\n.TP\n.I ?\n.br\nDisplays the legal\n.B toggle\ncommands.\n.RE\n.SH BUGS\n.PP\nThere is no adequate way for dealing with flow control.\n.PP\nOn some remote systems, echo has to be turned off manually when in\n\\*(lqline by line\\*(rq mode.\n.PP\nThere is enough settable state to justify a\n.RI . telnetrc\nfile.\n.PP\nNo capability for a\n.RI . telnetrc\nfile is provided.\n.PP\nIn \\*(lqline by line\\*(rq mode, the terminal's\n.I eof\ncharacter is only recognized (and sent to the remote system)\nwhen it is the first character on a line.\n"
  },
  {
    "path": "share/man/man1/time.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)time.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH TIME 1 \"April 29, 1985\"\n.UC 4\n.SH NAME\ntime \\- time a command\n.SH SYNOPSIS\n.B time\ncommand\n.SH DESCRIPTION\nThe\ngiven command is executed; after it is complete,\n.I time\nprints the elapsed time during the command, the time\nspent in the system, and the time spent in execution\nof the command.\nTimes are reported in seconds.\n.PP\nOn a PDP-11, the execution time can depend on what kind of memory\nthe program happens to land in;\nthe user time in MOS is often half what it is in core.\n.PP\nThe times are printed on the diagnostic output stream.\n.PP\n.I Time\nis built in to\n.IR csh (1),\nusing a different output format.\n.SH BUGS\nElapsed time is accurate to the second,\nwhile the CPU times are measured\nto the 100th second.\nThus the sum of the CPU times can be up to a second larger\nthan the elapsed time.\n.PP\n.I Time\nis a built-in command to\n.IR csh (1),\nwith a much different syntax.  This command is available as\n``/bin/time'' to\n.I csh\nusers.\n"
  },
  {
    "path": "share/man/man1/tip.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)tip.1c\t6.3 (Berkeley) 5/5/86\n.\\\"\n.TH TIP 1C \"May 5, 1986\"\n.UC 4\n.SH NAME\ntip, cu \\- connect to a remote system\n.SH SYNOPSIS\n.B tip\n[\n.B \\-v\n] [\n.BI \\- speed\n] system-name\n.br\n.B tip\n[\n.B \\-v\n] [\n.BI \\- speed\n] phone-number\n.br\n.B cu\nphone-number\n[\n.B \\-t\n] [\n.B \\-s\n.I speed\n] [\n.B \\ -a\n.I acu\n] [\n.B \\-l\n.I line\n] [\n.B \\-#\n]\n.SH DESCRIPTION\n.I Tip\nand\n.I cu\nestablish a full-duplex connection to another machine,\ngiving the appearance of being logged in directly on the\nremote cpu.  It goes without saying that you must have a login\non the machine (or equivalent) to which you wish to connect.\nThe preferred interface is\n.IR tip .\nThe\n.I cu\ninterface is included for those people attached to the\n``call UNIX'' command of version 7.  This manual page\ndescribes only \n.IR tip .\n.PP\nTyped characters are normally transmitted directly to the remote\nmachine (which does the echoing as well).  A tilde (`~') appearing\nas the first character of a line is an escape signal; the following\nare recognized:\n.TP 10\n.B ~^D ~.\nDrop the connection and exit\n(you may still be logged in on the\nremote machine).\n.TP 10\n\\fB~c \\fP [\\fIname\\fP]\nChange directory to name (no argument\nimplies change to your home directory).\n.TP 10\n.B ~!\nEscape to a shell (exiting the shell will\nreturn you to tip).\n.TP 10\n.B ~>\nCopy file from local to remote.\n.I Tip\nprompts for the name of a local file to transmit.\n.TP 10\n.B ~<\nCopy file from remote to local.\n.I Tip\nprompts first for the name of the file to be sent, then for\na command to be executed on the remote machine.\n.TP 10\n\\fB~p\\fP \\fIfrom\\fP [ \\fIto\\fP ]\nSend a file to a remote UNIX host.  The put command causes the remote UNIX\nsystem to run the command string ``cat > 'to''', while\n.I tip\nsends it the ``from''\nfile.  If the ``to'' file isn't specified the ``from'' file name is used.\nThis command is actually a UNIX specific version of the ``~>'' command.\n.TP 10\n\\fB~t\\fP \\fIfrom\\fP [ \\fIto\\fP ]\nTake a file from a remote UNIX host. \nAs in the put command the ``to'' file\ndefaults to the ``from'' file name if it isn't specified. \nThe remote host\nexecutes the command string ``cat 'from';echo ^A'' to send the file to\n.IR tip .\n.TP 10\n.B ~|\nPipe the output from a remote command to a local UNIX process.\nThe command string sent to the local UNIX system is processed by the shell.\n.TP 10\n.B ~$\nPipe the output from a local UNIX process to the remote host.\nThe command string sent to the local UNIX system is processed by the shell.\n.TP 10\n.B ~#\nSend a BREAK to the remote system. \nFor systems which don't support the\nnecessary\n.I ioctl\ncall the break is simulated by a sequence of line speed changes\nand DEL characters.\n.TP 10\n.B ~s\nSet a variable (see the discussion below).\n.TP 10\n.B ~^Z\nStop\n.I tip\n(only available with job control).\n.TP 10\n.B ~^Y\nStop only the ``local side'' of\n.I tip\n(only available with job control);\nthe ``remote side'' of\n.IR tip ,\nthe side that displays output from the remote host, is left running.\n.TP 10\n.B ~?\nGet a summary of the tilde escapes\n.sp\n.PP\n.I Tip\nuses the file /etc/remote to find how to reach a particular\nsystem and to find out how it should operate while talking\nto the system;\nrefer to\n.IR remote (5)\nfor a full description.\nEach system has a default baud rate with which to\nestablish a connection.  If this value is not suitable, the baud rate\nto be used may be specified on the command line, e.g. ``tip -300 mds''.\n.PP\nWhen\n.I tip\nestablishes a connection it sends out a\nconnection message to the remote system; the default value, if any,\nis defined in /etc/remote.\n.PP\nWhen\n.I tip\nprompts for an argument (e.g. during setup of\na file transfer) the line typed may be edited with the standard\nerase and kill characters.  A null line in response to a prompt,\nor an interrupt, will abort the dialogue and return you to the\nremote machine.\n.PP\n.I Tip\nguards against multiple users connecting to a remote system\nby opening modems and terminal lines with exclusive access,\nand by honoring the locking protocol used by\n.IR uucp (1C).\n.PP\nDuring file transfers \n.I tip\nprovides a running count of the number of lines transferred.\nWhen using the ~> and ~< commands, the ``eofread'' and ``eofwrite''\nvariables are used to recognize end-of-file when reading, and\nspecify end-of-file when writing (see below).  File transfers\nnormally depend on tandem mode for flow control.  If the remote\nsystem does not support tandem mode, ``echocheck'' may be set\nto indicate\n.I tip\nshould synchronize with the remote system on the echo of each\ntransmitted character.\n.PP\nWhen\n.I tip\nmust dial a phone number to connect to a system it will print\nvarious messages indicating its actions.\n.I Tip\nsupports the DEC DN-11 and Racal-Vadic 831 auto-call-units;\nthe DEC DF02 and DF03, Ventel 212+, Racal-Vadic 3451, and\nBizcomp 1031 and 1032 integral call unit/modems.\n.PP\n.SM\n.B VARIABLES\n.PP\n.I Tip\nmaintains a set of\n.I variables\nwhich control its operation.\nSome of these variable are read-only to normal users (root is allowed\nto change anything of interest).  Variables may be displayed\nand set through the ``s'' escape.  The syntax for variables is patterned\nafter\n.IR vi (1)\nand\n.IR Mail (1).\nSupplying ``all''\nas an argument to the set command displays all variables readable by\nthe user.  Alternatively, the user may request display of a particular\nvariable by attaching a `?' to the end.  For example ``escape?''\ndisplays the current escape character.\n.PP\nVariables are numeric, string, character, or boolean values.  Boolean\nvariables are set merely by specifying their name; they may be reset\nby prepending a `!' to the name.  Other variable types are set by\nconcatenating an `=' and the value.  The entire assignment must not\nhave any blanks in it.  A single set command may be used to interrogate\nas well as set a number of variables.\nVariables may be initialized at run time by placing set commands\n(without the ``~s'' prefix in a file\n.I .tiprc\nin one's home directory).  The\n.B \\-v\noption causes\n.I tip\nto display the sets as they are made.\nCertain common variables have abbreviations. \nThe following is a list of common variables,\ntheir abbreviations, and their default values.\n.TP\n.B beautify\n.br\n(bool) Discard unprintable characters when a session is being scripted;\nabbreviated \n.IR be .\n.TP\n.B baudrate\n.br\n(num) The baud rate at which the connection was established;\nabbreviated\n.IR ba .\n.TP\n.B dialtimeout\n.br\n(num) When dialing a phone number, the time (in seconds)\nto wait for a connection to be established; abbreviated\n.IR dial .\n.TP\n.B echocheck\n.br\n(bool) Synchronize with the remote host during file transfer by\nwaiting for the echo of the last character transmitted; default is\n.IR off .\n.TP\n.B eofread\n.br\n(str) The set of characters which signify and end-of-tranmission\nduring a ~< file transfer command; abbreviated\n.IR eofr .\n.TP\n.B eofwrite\n.br\n(str) The string sent to indicate end-of-transmission during\na ~> file transfer command; abbreviated\n.IR eofw .\n.TP\n.B eol\n.br\n(str) The set of characters which indicate an end-of-line.\n.I Tip\nwill recognize escape characters only after an end-of-line.\n.TP\n.B escape\n.br\n(char) The command prefix (escape) character; abbreviated\n.IR es ;\ndefault value is `~'.\n.TP\n.B exceptions\n.br\n(str) The set of characters which should not be discarded\ndue to the beautification switch; abbreviated\n.IR ex ;\ndefault value is ``\\et\\en\\ef\\eb''.\n.TP\n.B force\n.br\n(char) The character used to force literal data transmission;\nabbreviated\n.IR fo ;\ndefault value is `^P'.\n.TP\n.B framesize\n.br\n(num) The amount of data (in bytes) to buffer between file system\nwrites when receiving files; abbreviated\n.IR fr .\n.TP\n.B host\n.br\n(str) The name of the host to which you are connected; abbreviated\n.IR ho .\n.TP\n.B prompt\n.br\n(char) The character which indicates and end-of-line on the remote\nhost; abbreviated\n.IR pr ;\ndefault value is `\\en'.  This value is used to synchronize during\ndata transfers.  The count of lines transferred during a file transfer\ncommand is based on recipt of this character.\n.TP\n.B raise\n.br\n(bool) Upper case mapping mode; abbreviated \n.IR ra ;\ndefault value is \n.IR off .\nWhen this mode is enabled, all lower case letters will be mapped to\nupper case by\n.I tip\nfor transmission to the remote machine.\n.TP\n.B raisechar\n.br\n(char) The input character used to toggle upper case mapping mode;\nabbreviated\n.IR rc ;\ndefault value is `^A'.\n.TP\n.B record\n.br\n(str) The name of the file in which a session script is recorded;\nabbreviated\n.IR rec ;\ndefault value is ``tip.record''.\n.TP\n.B script\n.br\n(bool) Session scripting mode; abbreviated\n.IR sc ;\ndefault is \n.IR off .\nWhen\n.I script\nis \n.IR true ,\n.I tip\nwill record everything transmitted by the remote machine in\nthe script record file specified in\n.IR record .\nIf the\n.I beautify\nswitch is on, only printable ASCII characters will be included in\nthe script file (those characters betwee 040 and 0177).  The\nvariable\n.I exceptions\nis used to indicate characters which are an exception to the normal\nbeautification rules.\n.TP\n.B tabexpand\n.br\n(bool) Expand tabs to spaces during file transfers; abbreviated\n.IR tab ;\ndefault value is\n.IR false .\nEach tab is expanded to 8 spaces.\n.TP\n.B verbose\n.br\n(bool) Verbose mode; abbreviated\n.IR verb ;\ndefault is \n.IR true .\nWhen verbose mode is enabled, \n.I tip\nprints messages while dialing, shows the current number\nof lines transferred during a file transfer operations,\nand more.\n.TP\n.B SHELL\n.br\n(str) The name of the shell to use for the ~! command; default\nvalue is ``/bin/sh'', or taken from the environment.\n.TP\n.B HOME\n.br\n(str) The home directory to use for the ~c command; default\nvalue is taken from the environment.\n.PP\n.SH FILES\n.ta \\w'/usr/spool/uucp/LCK..*   'u\n.nf\n/etc/remote\tglobal system descriptions\n/etc/phones\tglobal phone number data base\n${REMOTE}\tprivate system descriptions\n${PHONES}\tprivate phone numbers\n~/.tiprc\tinitialization file.\n/usr/spool/uucp/LCK..*\tlock file to avoid conflicts with \\fIuucp\\fP\n.fi\n.SH DIAGNOSTICS\nDiagnostics are, hopefully, self explanatory.\n.SH \"SEE ALSO\"\nremote(5),\nphones(5)\n.SH BUGS\nThe full set of variables is undocumented and should, probably, be\npaired down.\n"
  },
  {
    "path": "share/man/man1/tk.1",
    "content": ".\\\"\t@(#)tk.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH TK 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\ntk \\- paginator for the Tektronix 4014\n.SH SYNOPSIS\n.B tk\n[\n.B \\-t\n]\n[\n.B \\-\\c\n.I  N\n]\n[\n.B \\-p\\c\n.I  L\n]\n[\nfile\n]\n.SH DESCRIPTION\nThe output of\n.I tk\nis intended for a Tektronix 4014 terminal.\n.I Tk\narranges for 66 lines to fit on the screen,\ndivides the screen into\n.I N\ncolumns,\nand\ncontributes an eight space page offset\nin the (default) single-column case.\nTabs, spaces, and backspaces are collected and plotted\nwhen necessary.\nTeletype Model 37 half- and reverse-line sequences\nare interpreted and plotted.\nAt the end of each page\n.I tk\nwaits for a newline (empty line) from the keyboard before\ncontinuing on to the next page.\nIn this wait state, the command\n.BI ! command\nwill send the\n.I command\nto the shell.\n.PP\nThe command line options are:\n.TP\n.B \\-t\nDon't wait between pages; for directing output into a file.\n.PP\n.TP\n.BI \\- N\nDivide the screen into \\fIN\\fR columns and\nwait after the last column.\n.TP\n.BI \\-p L\nSet page length to \\fIL\\fR\nlines.\n.SH SEE ALSO\npr(1)\n"
  },
  {
    "path": "share/man/man1/tn3270.1",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)tn3270.1\t1.3.1 (2.11BSD) 1996/11/27\n.\\\"\n.TH TN3270 1 \"November 27, 1996\"\n.UC 6\n.SH NAME\ntn3270 \\- full-screen remote login to IBM VM/CMS\n.SH SYNOPSIS\n.B tn3270\nsysname\n.SH DESCRIPTION\n.I Tn3270\npermits a full-screen, full-duplex connection\nfrom a VAX UNIX machine\nto an IBM machine running VM/CMS\ngiving the appearance of being logged in\ndirectly to the remote machine\non an IBM 3270 terminal.\nOf course you must have an account on the machine\nto which you wish to connect in order to log in.\n.I Tn3270\nlooks to the user in many respects\nlike the Yale ASCII Terminal Communication System II.\n.I Tn3270\nis actually a modification of the Arpanet TELNET user interface (see\n.IR telnet (1))\nthat interprets and generates raw 3270 control streams.\n.PP\nEmulation of the 3270 terminal is done in the Unix process.\nThis emulation involves mapping\n3270-style commands from the host\ninto appropriate sequences to control the user's terminal screen.\n.I Tn3270\nuses\n.IR curses (3x)\nand the\n.I /etc/termcap\nfile to do this.\nThe emulation also involves simulating the special 3270 keyboard keys\n(program function keys, etc.)\nby mapping sequences of keystrokes\nfrom the ASCII keyboard into appropriate 3270 control strings.\nThis mapping is terminal dependent and is specified\nin a description file,\n.IR /usr/share/misc/map3270 ,\n(see\n.IR map3270 (5))\nor in an environment variable\n.I MAP3270\n(see\n.IR mset (1)).\nAny special function keys on the ASCII keyboard are used whenever possible.\nIf an entry for the user's terminal\nis not found,\n.I tn3270\nlooks for an entry for the terminal type\n.B unknown.\nIf this is not found,\n.I tn3270\nuses a default keyboard mapping\n(see\n.IR map3270 (5)).\n.PP\nThe first character of each special keyboard mapping sequence \nis either an ASCII escape (ESC),\na control character, or an ASCII delete (DEL).\nIf the user types an unrecognized function key sequence,\n.I tn3270\nsends an ASCII bell (BEL), or a visual bell if\ndefined in the user's termcap entry, to the user's terminal\nand nothing is sent to the IBM host.\n.PP\nIf\n.I tn3270 \nis invoked without specifying a remote host system name,\nit enters local command mode,\nindicated by the prompt ``tn3270>''.\nIn this mode,\n.I tn3270\naccepts and executes\nthe following\ncommands:\n.sp \n.nf\n.ta 0.5i 1.5i\n\topen\tconnect to a remote host\n\tclose\tclose the current connection\n\tquit\texit tn3270\n\tz\tsuspend tn3270\n\tstatus\tprint connection status\n\t?\tprint help information\n.fi\n.sp\nOther common\n.I telnet\ncommands are not available in\n.I tn3270.\n.I Tn3270\ncommand mode may also be entered, after connecting to a host, by typing\na special escape character\n(typically control-C).\n.PP\nWhile in command mode, any host login session is still alive\nbut temporarily suspended.\nThe host login session may be resumed by entering an empty line\n(press the RETURN key)\nin response to the command prompt.\nA session may be terminated by logging off the foreign host,\nor by typing ``quit'' or ``close'' while in local command mode.\n.SH FILES\n/etc/termcap\n.br\n/usr/share/misc/map3270\n.SH AUTHOR\nGreg Minshall\n.SH SEE ALSO\nmset(1), telnet(1), termcap(3x), termcap(5), map3270(5),\n\\fIYale ASCII Terminal Communication\nSystem II Program Description/Operator's Manual\\fR\n(IBM SB30-1911)\n.SH BUGS\nPerformance is slow and uses system resources prodigiously.\n.PP\nNot all 3270 functions are supported,\nnor all Yale enhancements.\n"
  },
  {
    "path": "share/man/man1/touch.1",
    "content": ".\\\"\t@(#)touch.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH TOUCH 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\ntouch \\- update date last modified of a file\n.SH SYNOPSIS\n.B touch\n[\n.B \\-c\n]\n[\n.B \\-f\n]\nfile ...\n.SH DESCRIPTION\n.I Touch\nattempts to set the modified date of each\n.IR file .\nIf a\n.I file\nexists,\nthis is done by reading a character from the file\nand writing it back.\nIf a\n.I file\ndoes not exist,\nan attempt will be made to create it unless the\n.B \\-c\noption is specified.\nThe\n.B \\-f\noption will attempt to force the touch\nin spite of read and write permissions on a\n.IR file .\n.SH SEE\\ ALSO\nutimes(2)\n"
  },
  {
    "path": "share/man/man1/tp.1",
    "content": ".\\\"\t@(#)tp.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH TP 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\ntp \\- manipulate tape archive\n.SH SYNOPSIS\n.B tp\n[ key ] [ name ... ]\n.SH DESCRIPTION\n.PP\n.I Tp\nsaves and restores files\non DECtape or magtape.\nIts actions are controlled by the\n.I key\nargument.\nThe key is a string of characters containing\nat most one function letter and possibly\none or more function modifiers.\nOther arguments to the command are file or directory\nnames specifying which files are to be dumped, restored,\nor listed.\nIn all cases, appearance of a directory name refers to\nthe files and (recursively) subdirectories of that directory.\n.PP\nThe function portion of\nthe key is specified by one of the following letters:\n.TP 8\n.B  r\nThe named files\nare written\non the tape.\nIf files with the same names\nalready exist, they are replaced.\n`Same' is determined by string comparison, so\n`./abc' can never be the same as `/usr/dmr/abc' even\nif `/usr/dmr' is the current directory.\nIf no file argument is given, `\\fB.\\fR' is the default.\n.TP 8\n.B  u\nupdates the tape.\n.B u\nis like\n.B r,\nbut a file is replaced only if its\nmodification date is later than the date stored on the tape;\nthat is to say, if it has changed since it was dumped.\n.B u\nis the default command if none is given.\n.TP 8\n.B  d\ndeletes the named files from\nthe tape.\nAt least one name argument must be given.\nThis function is not permitted on magtapes.\n.TP 8\n.B  x\nextracts the named files from the tape to the file system.\nThe owner and mode are restored.\nIf no file argument is given, the entire contents of the\ntape are extracted.\n.TP 8\n.B  t\nlists the names of the specified files.\nIf no file argument is given,\nthe entire contents of the tape is listed.\n.PP\nThe following characters may be used in addition to the letter\nwhich selects the function desired.\n.TP 10\n.B  m\nSpecifies magtape as opposed to DECtape.\n.TP 10\n.B  0,...,7\nThis\nmodifier selects the drive on which the tape is mounted.\nFor DECtape, \n.B x\nis default; for magtape\n`0' is the default.\n.TP 10\n.B  v\nNormally\n.I tp\ndoes its work silently.\nThe\n.B v\n(verbose)\noption causes it to type the name of each file it treats\npreceded by the function letter.\nWith the\n.B t\nfunction,\n.B v\ngives more information about the\ntape entries than just the name.\n.TP 10\n.B  c\nmeans a fresh dump is being created; the tape directory\nis cleared before beginning.\nUsable only with\n.B r\nand\n.B u.\nThis option is assumed with magtape since\nit is impossible to selectively overwrite\nmagtape.\n.TP 10\n.B  i\nErrors reading and writing the\ntape are noted, but no action is taken.\nNormally, errors cause a return to the command level.\n.TP 10\n.B f\nUse the first named file, rather than a tape,\nas the archive.\nThis option currently acts like \n.BR m ;\n.I i.e.\n.BR r\nimplies \n.BR c ,\nand neither\n.BR d\nnor\n.BR u\nare permitted.\n.TP 10\n.B  w\ncauses\n.I tp\nto pause before treating each file, type\nthe indicative letter and the file name (as with\n.BR v )\nand await the user's response.\nResponse\n.B y\nmeans `yes', so the file is treated.\nNull response\nmeans `no', and the file does not take part\nin whatever is being done.\nResponse\n.B x\nmeans `exit';\nthe\n.I tp\ncommand terminates immediately.\nIn the\n.B x\nfunction,\nfiles previously asked about\nhave been extracted already.\nWith\n.B \"r, u,\"\nand\n.B d\nno change has been made to the tape.\n.PP\n.SH FILES\n/dev/tap?\n.br\n/dev/rmt?\n.SH SEE ALSO\nar(1), tar(1)\n.SH DIAGNOSTICS\nSeveral; the non-obvious one is\n`Phase error', which means the file changed after it was selected for\ndumping but before it was dumped.\n.SH BUGS\nA single file with several links to it is treated like several files.\n.PP\nBinary-coded control information makes\nmagnetic tapes written by\n.I tp\ndifficult to carry to other machines;\n.IR tar (1)\navoids the problem.\n"
  },
  {
    "path": "share/man/man1/tr.1",
    "content": ".\\\"\t@(#)tr.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH TR 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\ntr \\- translate characters\n.SH SYNOPSIS\n.B tr\n[\n.B \\-cds\n] [ string1 [ string2 ] ]\n.SH DESCRIPTION\n.I Tr\ncopies the standard input to the standard output with \nsubstitution or deletion of selected characters.\nInput characters found in \n.I string1\nare mapped into the corresponding characters of\n.IR string2 .\nWhen \n.I string2\nis short it is padded to the length of \n.I string1\nby duplicating its last character.\nAny combination of the options\n.B \\-cds\nmay be used:\n.B \\-c\ncomplements the set of characters in\n.I string1\nwith respect to the universe of characters\nwhose ASCII codes are 01 through 0377 octal;\n.B \\-d\ndeletes all input characters in\n.I string1;\n.B \\-s\nsqueezes all strings of repeated output characters that are\nin \n.I string2\nto single characters.\n.PP\nIn either string the notation\n.IB a \\- b\nmeans a range of characters from\n.I a\nto\n.I b\nin increasing ASCII order.\nThe character\n`\\e' followed by 1, 2 or 3 octal digits stands for the\ncharacter whose ASCII code is given by those digits.\nA `\\e' followed by any other character stands\nfor that character.\n.PP\nThe following example creates a list of all\nthe words in `file1' one per line in `file2',\nwhere a word is taken to be a maximal string of alphabetics.\nThe second string is quoted\nto protect `\\e' from the Shell.\n012 is the ASCII code for newline.\n.IP\ntr \\-cs A\\-Za\\-z \\'\\e012\\' <file1 >file2\n.SH \"SEE ALSO\"\ned(1), ascii(7), expand(1)\n.SH BUGS\nWon't handle ASCII NUL in\n.I string1\nor\n.I string2;\nalways deletes NUL from input.\n"
  },
  {
    "path": "share/man/man1/troff.1",
    "content": ".\\\"\t@(#)troff.1\t6.1.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH TROFF 1 \"October 22, 1996\"\n.AT 3\n.SH NAME\ntroff, nroff \\- text formatting and typesetting\n.SH SYNOPSIS\n.B troff\n[ option ] ...\n[ file ] ...\n.PP\n.B nroff\n[ option ] ...\n[ file ] ...\n.SH DESCRIPTION\n.I Troff\nformats text in the named\n.I files\nfor printing on a Graphic Systems C/A/T phototypesetter;\n.I nroff\nis used for for typewriter-like devices.\nTheir capabilities are described in the\n.I Nroff/Troff user's manual.\n.PP\nIf no\n.I file\nargument is present, the standard input is read.\nAn argument consisting of a single minus\n.RB ( \\- )\nis taken to be a file name corresponding to the standard input.\nThe options, which may appear in any order so long as they appear\nbefore the files, are:\n.TP \"\\w'\\f3\\-m\\f1name 'u\"\n.BI \\-o list\nPrint only pages whose page numbers appear in the comma-separated\n.I list\nof numbers and ranges.\nA range\n.IB N \\- M\nmeans pages\n.I N\nthrough\n.IR M ;\nan initial\n.I \\-N\nmeans from the beginning to page\n.IR N ;\nand a final\n.IR N \\-\nmeans from\n.I N\nto the end.\n.TP\n.BI \\-n N\nNumber first generated page\n.IR N .\n.TP\n.BI \\-s N\nStop every\n.I N\npages.\n.I Nroff\nwill halt prior to every\n.I N\npages (default\n.IR N =1)\nto allow paper loading or changing, and will resume upon receipt of a newline.\n.I Troff\nwill stop the phototypesetter every\n.I N\npages, produce a trailer to allow changing cassettes,\nand resume when the typesetter's start button is pressed.\n.TP\n.BI \\-m name\nPrepend the macro file\n.BI /usr/share/tmac/tmac. name\nto the input\n.IR files .\n.TP\n.BI \\-r aN\nSet register\n.I a\n(one-character) to\n.IR N .\n.TP\n.B \\-i\nRead standard input after the input files are exhausted.\n.TP\n.B \\-q\nInvoke the simultaneous input-output mode of the\n.B rd\nrequest.\n.HP\n.bd I 3\n.I Troff only\n.br\n.bd I\n.TP\n.B \\-t\nDirect output to the standard output instead of the phototypesetter.\n.TP\n.B \\-f\nRefrain from feeding out paper and stopping\nphototypesetter at the end of the run.\n.TP\n.B \\-w\nWait until phototypesetter is available, if currently busy.\n.TP\n.B \\-b\nReport whether the phototypesetter is busy or available.\nNo text processing is done.\n.TP\n.B \\-a\nSend a printable ASCII approximation of the results to the standard output.\n.TP\n.BR \\-p N\nPrint all characters in point size\n.I  N\nwhile retaining all prescribed spacings and motions,\nto reduce phototypesetter elapsed time.\n.TP\n.BI \\-F fontdir\nThe directory\n.I fontdir\ncontains the font width tables instead of the default directory\n/usr/share/fonts. This option can be used to produce output for devices\nbesides the phototypesetter.\n.PP\nIf the file\n.I /usr/adm/tracct\nis writable,\n.I troff\nkeeps phototypesetter accounting records there.\nThe integrity of that file may be secured by making\n.I troff\na 'set user-id' program.\n.SH FILES\n.ta \\w'/usr/share/tmac/tmac.*  'u\n/tmp/ta*\ttemporary file\n.br\n/usr/share/tmac/tmac.*\tstandard macro files\n.br\n/usr/share/term/*\tterminal driving tables for\n.I nroff\n.br\n/usr/share/font/*\tfont width tables for\n.I troff\n.br\n/dev/cat\tphototypesetter\n.br\n/usr/adm/tracct\taccounting statistics for /dev/cat\n.SH \"SEE ALSO\"\nJ. F. Ossanna,\n.I Nroff/Troff user's manual\n.br\nB. W. Kernighan,\n.I\nA TROFF Tutorial\n.br\neqn(1), tbl(1), ms(7), me(7), man(7), col(1)\n"
  },
  {
    "path": "share/man/man1/true.1",
    "content": ".\\\"\t@(#)true.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH TRUE 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\ntrue, false \\- provide truth values\n.SH SYNOPSIS\n.B true\n.PP\n.B false\n.SH DESCRIPTION\n.I True\nand\n.I false\nare usually used in a Bourne shell script.\nThey test for the appropriate status \"true\" or \"false\" before running \n(or failing to run) a list of commands.  \n.SH EXAMPLE\n.IP\n.nf\n     while true \n     do\n          command list \n     done\n.SH \"SEE ALSO\"\ncsh(1),\nsh(1),\nfalse(1)\n.SH DIAGNOSTICS\n.I True \nhas exit status zero.\n"
  },
  {
    "path": "share/man/man1/tsort.1",
    "content": ".\\\"\t@(#)tsort.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH TSORT 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\ntsort \\- topological sort\n.SH SYNOPSIS\n.B tsort\n[ file ]\n.SH DESCRIPTION\n.I Tsort\nproduces on the standard output a totally ordered list of items\nconsistent with a partial ordering of items\nmentioned in the input\n.IR file .\nIf no\n.I file\nis specified, the standard input is understood.\n.PP\nThe input consists of pairs of items (nonempty strings)\nseparated by blanks.\nPairs of different items indicate ordering.\nPairs of identical items indicate presence, but not ordering.\n.SH \"SEE ALSO\"\nlorder(1)\n.SH DIAGNOSTICS\nOdd data: there is an odd number of fields in the input file.\n.SH BUGS\nUses a quadratic algorithm;\nnot worth fixing for the typical use of ordering\na library archive file.\n"
  },
  {
    "path": "share/man/man1/tty.1",
    "content": ".\\\"\t@(#)tty.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH TTY 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\ntty \\- get terminal name\n.SH SYNOPSIS\n.B tty\n[ -s ]\n.SH DESCRIPTION\n.I Tty\nprints the pathname of the user's terminal unless the \\-s\n(silent) is given. In either case, the exit value is zero if the\nstandard input is a terminal and one if it is not.\n.SH DIAGNOSTICS\n`not a tty' if the standard input file is not a terminal.\n"
  },
  {
    "path": "share/man/man1/ul.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ul.1\t6.2 (Berkeley) 5/7/86\n.\\\"\n.TH UL 1 \"May 7, 1986\"\n.UC 4\n.SH NAME\nul \\- do underlining\n.SH SYNOPSIS\n.B ul\n[\n.B \\-i\n] [\n.B \\-t\n.I terminal\n]\n[\n.I name\n\\&...\n]\n.SH DESCRIPTION\n.I Ul\nreads the named files (or standard input if none are given)\nand translates occurrences of underscores to the sequence\nwhich indicates underlining for the terminal in use, as specified\nby the environment variable\nTERM.\nThe\n.B \\-t\noption overrides the terminal kind specified in the environment.\nThe file\n.I /etc/termcap\nis read to determine the appropriate sequences for underlining.\nIf the terminal is incapable of underlining, but is capable of\na standout mode then that is used instead.\nIf the terminal can overstrike,\nor handles underlining automatically,\n.I ul\ndegenerates to\n.IR cat (1).\nIf the terminal cannot underline, underlining is ignored.\n.PP\nThe\n.B \\-i\noption causes\n.I ul\nto indicate underlining onto by a separate line containing appropriate\ndashes `\\-'; this is useful when you want to look at the underlining\nwhich is present in an\n.I nroff\noutput stream on a crt-terminal.\n.SH \"SEE ALSO\"\nman(1), nroff(1), colcrt(1)\n.SH BUGS\n.I Nroff\nusually outputs a series of backspaces and underlines intermixed\nwith the text to indicate underlining.  No attempt is made to optimize\nthe backward motion.\n"
  },
  {
    "path": "share/man/man1/unifdef.1",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)unifdef.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH UNIFDEF 1 \"April 29, 1985\"\n.UC 6\n.SH NAME\nunifdef \\- remove ifdef'ed lines\n.SH SYNOPSIS\n.B unifdef\n[\n.B \\-t\n.B \\-l\n.B \\-c\n.BI \\-D sym\n.BI \\-U sym\n.BI \\-id sym\n.BI \\-iu sym\n] ...  [ file ]\n.SH DESCRIPTION\n.I Unifdef\nis useful for removing ifdef'ed lines from a file while otherwise leaving the\nfile alone.\n.I Unifdef\nis like a stripped-down C preprocessor:\nit is smart enough to deal with the nested ifdefs, comments,\nsingle and double\nquotes of C syntax so that it can do its job, but it doesn't do any including\nor interpretation of macros.\nNeither does it strip out comments, though it recognizes and ignores them.\nYou specify which symbols you want defined\n.BI \\-D sym\nor undefined\n.BI \\-U sym\nand the lines inside those ifdefs will be copied to the output or removed as\nappropriate.\nThe ifdef, ifndef, else, and endif lines associated with\n.I sym\nwill also be removed.\nIfdefs involving symbols you don't specify are untouched and copied out\nalong with their associated\nifdef, else, and endif lines.\nIf an ifdef X occurs nested inside another ifdef X, then the\ninside ifdef is treated as if it were an unrecognized symbol.\nIf the same symbol appears in more than one argument, only the first\noccurrence is significant.\n.PP\nThe\n.B \\-l\noption causes\n.I unifdef\nto replace removed lines with blank lines\ninstead of deleting them.\n.PP\nIf you use ifdefs to delimit non-C lines, such as comments\nor code which is under construction,\nthen you must tell\n.I unifdef\nwhich symbols are used for that purpose so that it won't try to parse\nfor quotes and comments\nin those ifdef'ed lines.\nYou specify that you want the lines inside certain ifdefs to be ignored\nbut copied out with\n.BI \\-id sym\nand\n.BI \\-iu sym\nsimilar to\n.BI \\-D sym\nand\n.BI \\-U sym\nabove.\n.PP\nIf you want to use\n.I unifdef\nfor plain text (not C code), use the\n.B \\-t\noption.\nThis makes\n.I unifdef\nrefrain from attempting to recognize comments and single and double quotes.\n.PP\n.I Unifdef\ncopies its output to\n.I stdout\nand will take its input from\n.I stdin\nif no\n.I file\nargument is given.\nIf the\n.B \\-c\nargument is specified, then the operation of\n.I unifdef\nis complemented,\ni.e. the lines that would have been removed or blanked\nare retained and vice versa.\n.SH \"SEE ALSO\"\ndiff(1)\n.SH DIAGNOSTICS\nPremature EOF, inappropriate else or endif.\n.PP\nExit status is 0 if output is exact copy of input, 1 if not, 2 if trouble.\n.SH BUGS\nDoes not know how to deal with \\fIcpp\\fP consructs such as\n.br\n.sp\n.nf\n\t#if\tdefined(X) || defined(Y)\n.sp\n.fi\n.SH AUTHOR\nDave Yost\n"
  },
  {
    "path": "share/man/man1/uniq.1",
    "content": ".\\\"\t@(#)uniq.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH UNIQ 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nuniq \\- report repeated lines in a file\n.SH SYNOPSIS\n.B uniq\n[\n.B \\-udc\n[\n.BR + n\n] [\n.BR \\- n\n]\n] [ input [ output ] ]\n.SH DESCRIPTION\n.I Uniq\nreads the input file comparing adjacent lines.\nIn the normal case, the second and succeeding copies of repeated lines are\nremoved; the remainder is written on the output file.\nNote that repeated lines must be adjacent in order to be found; see\n.IR  sort (1).\nIf the\n.B \\-u\nflag is used, just the lines that are not repeated\nin the original file are output.  The\n.B \\-d\noption specifies that one copy of just the repeated lines is to be written.\nThe normal mode output is the union of the\n.B \\-u\nand\n.B \\-d\nmode outputs.\n.PP\nThe\n.B \\-c\noption supersedes\n.B \\-u\nand\n.B \\-d\nand generates an output report in default style\nbut with each line preceded by a count of the number of times it occurred.\n.PP\nThe\n.I n\narguments specify skipping an initial portion of each line in the comparison:\n.TP 8\n.BI \\- n\nThe first\n.IR n \nfields together with any blanks before each are ignored.\nA field is defined as a string of non-space, non-tab characters\nseparated by tabs and spaces from its neighbors.\n.TP 8\n.BI + n\nThe first\n.IR n \ncharacters are ignored.  Fields are skipped before characters.\n.PP\n.SH \"SEE ALSO\"\nsort(1), comm(1)\n"
  },
  {
    "path": "share/man/man1/units.1",
    "content": ".\\\"\t@(#)units.1\t6.1.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH UNITS 1 \"October 22, 1996\"\n.AT 3\n.if n .ds / /\n.if t .ds / \\z/\\h'\\w'*'u'\n.SH NAME\nunits \\- conversion program\n.SH SYNOPSIS\n.B units\n.SH DESCRIPTION\n.I Units\nconverts quantities expressed\nin various standard scales to\ntheir equivalents in other scales.\nIt works interactively in this fashion:\n.PP\n.I \"\tYou have:\"\ninch\n.br\n.I \"\tYou want:\"\ncm\n.br\n.I \"\t\t* 2.54000e+00\n.br\n.I \"\t\t\\*/ 3.93701e\\-01\n.PP\nA quantity is specified as a multiplicative combination of\nunits optionally preceded by a numeric multiplier.\nPowers are indicated by suffixed positive integers,\ndivision by the usual sign:\n.PP\n.I \"\tYou have:\"\n15 pounds force/in2\n.br\n.I \"\tYou want:\"\natm\n.br\n.I \"\t\t* 1.02069e+00\"\n.br\n.I \"\t\t\\*/ 9.79730e\\-01\"\n.PP\n.I Units \nonly does multiplicative scale changes.\nThus it can convert Kelvin to Rankine, but not Centigrade to\nFahrenheit.\nMost familiar units,\nabbreviations, and metric prefixes are recognized,\ntogether with a generous leavening of exotica\nand a few constants of nature including:\n.PP\n.nf\n\tpi\tratio of circumference to diameter\n\tc\tspeed of light\n\te\tcharge on an electron\n\tg\tacceleration of gravity \n\tforce\tsame as g\n\tmole\tAvogadro's number\n\twater\tpressure head per unit height of water\n\tau\tastronomical unit\n.PP\n.fi\n`Pound' is a unit of\nmass.\nCompound names are run together, e.g. `lightyear'.\nBritish units that differ from their US counterparts\nare prefixed thus: `brgallon'.\nCurrency is denoted `belgiumfranc', `britainpound', ...\n.PP\nFor a complete list of units, `cat /usr/share/misc/units'.\n.SH FILES\n/usr/share/misc/units\n.SH BUGS\nDon't base your\nfinancial plans on the currency conversions.\n"
  },
  {
    "path": "share/man/man1/uptime.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)uptime.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH UPTIME 1 \"April 29, 1985\"\n.UC\n.SH NAME\nuptime \\- show how long system has been up\n.SH SYNOPSIS\n.B uptime\n.SH DESCRIPTION\nUptime prints the current time, the length of time the system has been up,\nand the average number of jobs in the run queue over the last 1, 5 and\n15 minutes.\nIt is, essentially, the first line of a\n.IR w (1)\ncommand.\n.SH FILES\n/vmunix\tsystem name list\n.SH SEE ALSO\nw(1)\n"
  },
  {
    "path": "share/man/man1/users.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)users.1\t6.1.1 (2.11BSD) 1996/11/27\n.\\\"\n.TH USERS 1 \"November 27, 1996\"\n.UC\n.SH NAME\nusers \\- compact list of users who are on the system\n.SH SYNOPSIS\n.B users\n.SH DESCRIPTION\n.I Users\nlists the login names of the users currently on the system in a compact,\none-line format.\n.SH FILES\n/var/run/utmp\n.SH SEE ALSO\nwho(1)\n"
  },
  {
    "path": "share/man/man1/uucp.1",
    "content": ".\\\"\t@(#)uucp.1\t6.3.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH UUCP 1 \"April 24, 1986\"\n.AT 3\n.SH NAME\nuucp \\- unix to unix copy\n.SH SYNOPSIS\n.B uucp\n[\n.B \\-acCdfmr\n] [\n.BI \\-n user\n] [\n.BI \\-g grade\n] [\n.BI \\-s spool\n] [\n.BI \\-x debug\n] source-file....  destination-file\n.SH DESCRIPTION\n.I Uucp\ncopies files named by the source-file arguments\nto the destination-file argument.\nA file name may be a pathname on your machine, or may \nhave the form\n.IP\nsystem-name!pathname\n.LP\nwhere `system-name' is taken from a list of system names\nthat\n.I uucp\nknows about.\nShell metacharacters ?*[] appearing in the pathname part\nwill be expanded on the appropriate system.\n.PP\nPathnames may be one of:\n.IP (1)\na full pathname;\n.IP (2)\na pathname preceded by\n.BI ~ user;\nwhere\n.I user\nis a userid on the specified system\nand is replaced by that user's login directory;\n.IP (3)\na pathname prefixed by\n.BR ~ ,\nwhere\n.B ~\nis expanded into the system's public directory (usually /usr/spool/uucppublic);\n.IP (4)\na partial pathname, which is prefixed by the current directory.\n.PP\nIf the result is an erroneous pathname for the remote system,\nthe copy will fail.\nIf the destination-file is a directory, the last part of the\nsource-file name is used.\n.ig\nIf a simple\n.I ~user\ndestination is inaccessible to \n.IR uucp ,\ndata is copied to a spool directory and the user\nis notified by\n.IR mail (1).\n..\n.PP\n.I Uucp\npreserves execute permissions across the transmission\nand gives 0666 read and write permissions (see\n.IR chmod (2)).\n.PP\nThe following options are interpreted by\n.IR uucp .\n.TP\n.B \\-a\nAvoid doing a\n.I getwd\nto find the current directory.\n(This is sometimes used for efficiency.)\n.TP \n.B \\-c\nUse the source file when copying out rather than\ncopying the file to the spool directory.\n(This is the default.)\n.TP\n.B \\-C\nCopy the source file to the spool directory and transmit\nthe copy.\n.TP \n.B \\-d\nMake all necessary directories for the file copy.\n(This is the default.)\n.TP\n.B \\-f\nDo not make intermediate directories for the file copy.\n.TP\n.BI \\-g grade\n.I Grade\nis a single letter/number; lower ASCII sequence characters\nwill cause a job to be transmitted earlier during a particular conversation.\nDefault is `n'. By way of comparison,\n.IR uux (1C)\ndefaults to `A'; mail is usually sent at `C'.\n.TP \n.B \\-m\nSend mail to the requester when the copy is complete.\n.TP\n.BI \\-n user\nNotify\n.I user\non remote system (i.e., send\n.I user\nmail) that a file was sent.\n.TP\n.B \\-r\nDo not start the transfer, just queue the job.\n.TP\n.BI \\-s spool\nUse\n.I spool\nas the spool directory instead of the default.\n.TP\n.BI \\-x debug\nTurn on the debugging at level\n.I debug.\n.SH FILES\n/usr/spool/uucp - spool directory\n.br\n/etc/uucp/* - data and configuration files\n.SH SEE ALSO\nuux(1C), mail(1)\n.PP\nD. A. Nowitz and M. E. Lesk,\n.IR \"A Dial-Up Network of UNIX Systems\" .\n.PP\nD. A. Nowitz,\n.IR \"Uucp Implementation Description\" .\n.SH WARNING\nThe domain of remotely accessible files can\n(and for obvious security reasons, usually should)\nbe severely restricted.\nYou will very likely not be able to fetch files\nby pathname;\nask a responsible person on the remote system to\nsend them to you.\nFor the same reasons you will probably not be able\nto send files to arbitrary pathnames.\n.SH BUGS\n.br\nAll files received by\n.I uucp\nwill be owned by the uucp administrator (usually UID 5).\n.PP\nThe \n.B \\-m\noption will only work sending files or receiving\na single file.\n(Receiving multiple files specified by special shell\ncharacters ?*[] will not activate\nthe\n.B \\-m\noption.)\n.PP\nAt present\n.I uucp\ncannot copy to a system several \"hops\" away, that is, a command of\nthe form\n.PP\n.nf\n\tuucp myfile system1!system2!system3!yourfile\n.fi\n.PP\nis not permitted. Use\n.IR uusend (1C)\ninstead.\n.PP\nWhen invoking\n.I uucp\nfrom\n.IR csh (1),\nthe `!' character must be prefixed by the `\\e' escape to inhibit\n.IR csh 's\nhistory mechanism. (Quotes are not sufficient.)\n.PP\n.I Uucp\nrefuses to copy a file that does not give read access to ``other'';\nthat is, the file must have at least 0444 modes.\n"
  },
  {
    "path": "share/man/man1/uuencode.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)uuencode.1c\t6.2 (Berkeley) 4/24/86\n.\\\"\n.TH UUENCODE 1C \"April 24, 1986\"\n.UC 4\n.SH NAME\nuuencode, uudecode \\- encode/decode a binary file for transmission via mail\n.SH SYNOPSIS\n.B uuencode\n[ source ] remotedest |\n.B mail\nsys1!sys2!..!decode\n.br\n.B uudecode\n[ file ]\n.SH DESCRIPTION\n.I Uuencode\nand\n.I uudecode\nare used to send a binary file via uucp (or other) mail.\nThis combination can be used over indirect mail links\neven when\n.IR uusend (1C)\nis not available.\n.PP\n.I Uuencode\ntakes the named source file (default standard input) and\nproduces an encoded version on the standard output.\nThe encoding uses only printing ASCII characters,\nand includes the mode of the file and the\n.I remotedest\nfor recreation on the remote system.\n.PP\n.I Uudecode\nreads an encoded file,\nstrips off any leading and trailing lines added by mailers,\nand recreates the original file with the specified mode and name.\n.PP\nThe intent is that all mail to the user ``decode'' should be filtered\nthrough the\n.I uudecode\nprogram.  This way the file is created automatically\nwithout human intervention.\nThis is possible on the uucp network by either using\n.I sendmail\nor by making\n.I rmail\nbe a link to\n.I Mail\ninstead of\n.IR mail .\nIn each case, an alias must be created in a master file to get\nthe automatic invocation of\n.IR uudecode .\n.PP\nIf these facilities are not available, the file can be sent to a\nuser on the remote machine who can uudecode it manually.\n.PP\nThe encode file has an ordinary text form and can be edited\nby any text editor to change the mode or remote name.\n.SH SEE ALSO\natob(n), uusend(1C), uucp(1C), uux(1C), mail(1), uuencode(5)\n.SH BUGS\nThe file is expanded by 35% (3 bytes become 4 plus control information)\ncausing it to take longer to transmit.\n.PP\nThe user on the remote system who is invoking\n.I uudecode\n(often\n.IR uucp )\nmust have write permission on the specified file.\n"
  },
  {
    "path": "share/man/man1/uulog.1",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)uulog.1c\t6.1 (Berkeley) 4/24/86\n.\\\"\n.TH UULOG 1C \"April 24, 1986\"\n.UC 6\n.SH NAME\nuulog \\- display \\s-1UUCP\\s0 log files\n.SH SYNOPSIS\n.B uulog\n[\n.B \\-s\n.I sys\n] [\n.B \\-u\n.I user\n]\n.SH DESCRIPTION\n.I Uulog\nqueries a log\nof \n.IR uucp (1C)\nand\n.IR uux (1C)\ntransactions in the file\n.B /usr/spool/uucp/\\s-1LOGFILE.\\s0\n.PP\nThe options command \n.I uulog\nto print logging information:\n.TP 8\n.BI \\-s sys\\^\nPrint information about work involving system\n.IR sys .\n.TP 8\n.BI \\-u user\\^\nPrint information about work done for the specified\n.IR user .\n.SH FILES\n/usr/spool/uucp/\\s-1LOGFILE\\s0\n.SH SEE ALSO\nuucp(1C), uux(1C).\n.SH NOTES\nVery early releases of \\s-1UUCP\\s0 used separate log files\nfor each of the \\s-1UUCP\\s0 utilities;\n.I uulog\nwas used to merge the individual logs into a master file.\nThis capability has not been necessary for some time and is\nno longer supported.\n.SH BUGS\n\\s-1UUCP\\s0's recording of which user issued a request is unreliable.\n.PP\n.I Uulog\nis little more than an overspecialized version of\n.IR grep (1).\n"
  },
  {
    "path": "share/man/man1/uuname.1",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)uuname.1c\t6.1 (Berkeley) 4/24/86\n.\\\"\n.TH UUNAME 1C \"April 24, 1986\"\n.UC 6\n.SH NAME\nuuname \\- list names of \\s-1UUCP\\s0 hosts\n.SH SYNOPSIS\n.B uuname\n[\n.B \\-l\n]\n.SH DESCRIPTION\n.I Uuname\nlists the \\s-1UUCP\\s0 names of known systems.\nThe\n.B \\-l\noption returns the local system name; this may differ from the\n.IR hostname (1)\nfor the system if the\n.I hostname\nis very long.\n.SH SEE ALSO\nuucp(1C), uux(1C).\n"
  },
  {
    "path": "share/man/man1/uuq.1",
    "content": ".\\\"\t@(#)uuq.1c\t6.2 (Berkeley) 4/24/86\n.\\\"\n.TH UUQ 1C \"April 24, 1986\"\n.UC 6\n.SH NAME\nuuq \\- examine or manipulate the uucp queue\n.SH SYNOPSIS\n.B uuq\n[\n.B -l\n] [\n.B -h\n] [\n.BI -s system\n] [\n.BI -u user\n] [\n.BI -d jobno\n] [\n.BI -r sdir\n] [\n.BI -b baud\n]\n.SH DESCRIPTION\n.I Uuq\nis used to examine (and possibly delete) entries in the uucp queue.\n.PP\nWhen listing jobs,\n.I uuq\nuses a format reminiscent of\n.IR ls .\nFor the long format,\ninformation for each job listed includes\njob number, number of files to transfer, user who\nspooled the job, number of bytes to send, type of command requested\n(S for sending files, R for receiving files, X for remote uucp),\nand file or command desired.\n.PP\nSeveral options are available:\n.TP 10\n.B \\-h\nPrint only the summary lines for each system.  Summary lines give system\nname, number of jobs for the system, and total number of bytes to send.\n.TP 10\n.B \\-l\nSpecifies a long format listing.  The default is to list only the\njob numbers sorted across the page.\n.TP 10\n.BI \\-s system\nLimit output to jobs for systems whose system names begin with \\fIsystem\\fP.\n.TP 10\n.BI \\-u user\nLimit output to jobs for users whose login names begin with \\fIuser\\fP.\n.TP 10\n.BI \\-d jobno\nDelete job number \\fIjobno\\fP (as obtained from a previous \\fIuuq\\fP command)\nfrom the uucp queue.\nOnly the UUCP Administrator is permitted to delete jobs.\n.TP 10\n.BI \\-r sdir\nLook for files in the spooling directory \\fIsdir\\fP instead of the default\ndirectory.\n.TP 10\n.BI \\-b baud\nUse \\fIbaud\\fP to compute the transfer time instead of the default\n1200 baud.\n.SH FILES\n.ta \\w'/usr/spool/uucp/D.hostname/D.*   'u\n/usr/spool/uucp/\tDefault spool directory\n/usr/spool/uucp/C./C.*\tControl files\n.br\n/usr/spool/uucp/D\\fIhostname\\fP./D.*\tOutgoing data files\n/usr/spool/uucp/X./X.*\tOutgoing execution files\n.SH SEE ALSO\nuucp(1C), uux(1C), uulog(1C), uusnap(8C)\n.SH BUGS\nNo information is available on work requested by the remote machine.\n.PP\nThe user who requests a remote uucp command is unknown.\n.PP\n.B \"Uuq -l\"\ncan be horrendously slow.\n.SH AUTHOR\nLou Salkind, New York University\n"
  },
  {
    "path": "share/man/man1/uusend.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)uusend.1c\t6.2 (Berkeley) 4/24/86\n.\\\"\n.TH UUSEND 1C \"April 24, 1986\"\n.UC 4\n.SH NAME\nuusend \\- send a file to a remote host\n.SH SYNOPSIS\n.B uusend\n[\n.B \\-m\nmode\n]\nsourcefile\nsys1!sys2!..!remotefile\n.SH DESCRIPTION\n.I Uusend\nsends a file to a given location on a remote system.\nThe system need not be directly connected to the local\nsystem, but a chain of\n.IR uucp (1)\nlinks needs to connect the two systems.\n.PP\nIf the\n.B \\-m\noption is specified, the mode of the file on the remote\nend will be taken from the octal number given.\nOtherwise, the mode of the input file will be used.\n.PP\nThe sourcefile\ncan be ``\\-'',\nmeaning to use the standard input.\nBoth of these options are primarily intended for internal use of\n.IR uusend .\n.PP\nThe remotefile can include the ~userid syntax.\n.SH DIAGNOSTICS\nIf anything goes wrong any further away than the first system down\nthe line, you will never hear about it.\n.SH SEE\\ ALSO\nuux(1), uucp(1), uuencode(1)\n.SH BUGS\nThis command should not exist, since\n.I uucp\nshould handle it.\n.PP\nAll systems along the line must have the\n.I uusend\ncommand available and allow remote execution of it.\n.PP\nSome uucp systems have a bug where binary files cannot be the\ninput to a\n.I uux\ncommand.  If this bug exists in any system along the line,\nthe file will show up severly munged.\n"
  },
  {
    "path": "share/man/man1/uux.1",
    "content": ".\\\"\t@(#)uux.1\t6.3.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH UUX 1 \"October 22, 1996\"\n.AT 3\n.SH NAME\nuux \\- unix to unix command execution\n.SH SYNOPSIS\n.B uux\n[\n.B -\n] [\n.B -cClLnprz\n] [\n.BI -a name\n] [\n.BI -g grade\n] [\n.BI -x debug\n]\ncommand-string\n.SH DESCRIPTION\n.I Uux\\^\nwill gather zero or more files from various systems,\nexecute a command on a specified system\nand then send standard output to a file on a specified\nsystem.\n.PP\nThe\n.I command-string\nis made up of one or more arguments that look\nlike a Shell command line,\nexcept that the command and file names\nmay be prefixed by\n.IB system-name !\\fR.\\fP\nA null \\fIsystem-name\\fP is interpreted as the local system.\n.PP\nFile names may be one of\n.IP\n(1) a full path name;\n.IP\n(2) a path name preceded by\n.BI ~ user\nwhere\n.I user\nis a login name on the specified system\nand is replaced by that user's login directory;\n.IP\n(3) a path name prefixed by\n.BR ~;\nwhere\n.B ~\nis expanded to the system's public directory (usually /usr/spool/uucppublic);\n.IP\n(4) a partial pathname, which is prefixed by the current directory.\n.PP\nAs an example, the command\n.IP\nuux \"\\^!diff usg!/usr/dan/file1 pwba!/a4/dan/file2 > !~/dan/file.diff\\^\"\n.PP\nwill get the \\fBfile1\\fP and \\fBfile2\\fP files\nfrom the ``usg'' and ``pwba'' machines,\nexecute a\n.IR diff (1)\ncommand\nand put the results in \\fBfile.diff\\fP in the \nlocal /usr/spool/uucppublic/dan/ directory.\n.PP\nAny special shell characters, such as \\fB<>;|\\fP, should be quoted either\nby quoting the entire \\fIcommand-string\\fP, or quoting the special\ncharacters as individual arguments.\n.PP\n.I Uux\nwill attempt to get all files to the execution system.\nFor files that are output files, the file name must be escaped using\nparentheses.\nFor example, the command\n.IP\nuux a!wc b!/usr/file1 \\\\(c!/usr/file2 \\\\)\n.PP\nget \\fB/usr/file1\\fP from system ``b'' and send it to system ``a'',\nperform a \\fIwc\\fP command on that file\nand send the result of the \n.I wc\ncommand to system ``c''.\n.PP\n.I Uux\\^\nwill notify you by mail if the requested command on the remote\nsystem was disallowed.\nThis notification can be turned off by the \\fB\\-n\\fP option.\n.PP\nThe following \\fIoptions\\fP are interpreted by\n.IR uux :\n.TP .5i\n.B \\-\nThe standard input to\n.I uux\nis made the standard input to the\n.IR command-string .\n.TP .5i\n.BI \\-a name\nUse\n.I name\nas the user identification replacing the initiator user-id.\n.TP .5i\n.B \\-c\nDo not copy local file to the spool directory for transfer to the remote\nmachine (this is the default).\n.TP .5i\n.B \\-C\nForce the copy of local files to the spool directory for transfer.\n.TP .5i\n.BI \\-g grade\n.I Grade\nis a single letter/number, from\n.B 0\nto\n.BR 9 ,\n.B A\nto\n.BR Z ,\nor\n.B a\nto\n.BR z ;\n.B 0\nis the highest, and\n.B z\nis the lowest grade.\nThe default is \n.BR A ;\nby comparison\n.IR uucp (1)\ndefaults to\n.B n\nand mail is usually sent at grade\n.BR C .\nLower grades should be specified for high-volume jobs, such as news.\n.TP .5i\n.B \\-l\nTry and make a link from the original file to the spool directory.\nIf the link cannot be made, copy the file.\n.TP .5i\n.B \\-n\nDo not notify the user when the command completes.\n.TP .5i\n.B \\-p\nSame as \\-:\nThe standard input to\n.I uux\nis made the standard input to the\n.IR command-string .\n.TP .5i\n.B \\-r\nDo not start the file transfer, just queue the job.\n.TP .5i\n.BI \\-x debug\nProduce debugging output on stdout.\nThe debug is a number between 0 and 9;\nhigher numbers give more detailed information. Debugging is permitted\nonly for privileged users (specifically, those with read access to\n.IR L.sys (5) .\n.TP .5i\n.B \\-z\nNotify the user only if the command fails.\n.TP .5i\n.B \\-L\nStart up\n.I uucico\nwith the \\fB-L\\fP flag. This will force\ncalls to be made to local sites only (see\n.IR uucico (8C)).\n.SH FILES\n.PD 0\n.TP 22\n/usr/spool/uucp\nspool directories\n.TP\n/etc/uucp/\\(**\nUUCP configuration data.\n.PD\n.SH SEE ALSO\nuucp(1), uucico(8), uuxqt(8).\n.SH WARNING\nFor security reasons, many installations will\nlimit the list of\ncommands executable on behalf of an incoming request from\n.IR uux .\nMany sites will permit little more than\nthe receipt of mail (see\n.IR mail (1))\nvia \n.IR uux .\n.SH BUGS\nOnly the first command of a shell pipeline may\nhave a\n.IB system-name !\\fR.\nAll other commands are executed on the system of the first\ncommand.\n.PP\nThe use of the shell metacharacter\n.B \\(**\nwill probably not do what you want it to do.\n.PP\nThe shell tokens\n.B <<\nand\n.B >>\nare not implemented.\n.PP\nWhen invoking\n.I uux\nfrom\n.IR csh (1),\nthe `!' character must be prefixed by the `\\\\' escape to inhibit\n.IR csh 's\nhistory mechanism. (Quotes are not sufficient.)\n"
  },
  {
    "path": "share/man/man1/vacation.1",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)vacation.1\t6.2 (Berkeley) 6/16/85\n.\\\"\n.TH VACATION 1 \"June 16, 1985\"\n.UC 6\n.SH NAME\nvacation \\- return ``I am on vacation'' indication\n.SH SYNOPSIS\n.B vacation\n.B \\-I\n.br\n.B vacation\nuser\n.SH DESCRIPTION\n.I Vacation\nreturns a message to the sender of a message\ntelling that you are on vacation.\nThe intended use is in a\n.I \\&.forward\nfile.\nFor example,\nyour\n.I \\&.forward\nfile might have:\n.PP\n.ti +5\n\\eeric, \"|vacation eric\"\n.PP\nwhich would send messages to you\n(assuming your login name was eric)\nand send a message back to the sender.\n.PP\n.I Vacation\nexpects a file\n.I \\&.vacation.msg\nin your home directory containing a message to be sent back\nto each sender.\nIt should be an entire message\n(including headers).\nFor example, it might say:\n.PP\n.in +5\n.nf\nFrom: eric@ucbmonet.Berkeley.EDU (Eric Allman)\nSubject: I am on vacation\nDelivered-By-The-Graces-Of: the Vacation program\n\nI am on vacation until July 22.  If you have something urgent,\nplease contact Joe Kalash <kalash@ucbingres.Berkeley.EDU>.\n\t--eric\n.fi\n.in -5\n.PP\nThis message will only be sent once a week to each unique\nsender.\nThe people who have sent you messages are kept in the files\n.I \\&.vacation.pag\nand\n.I \\&.vacation.dir\nin your home directory.\nThe\n.B \\-I\noption initializes these files,\nand should be executed before you modify your\n.I \\&.forward\nfile.\n.PP\nIf the\n.B \\-I\nflag is not specified,\n.I vacation\nreads the first line from the standard input\nfor a \\s-1UNIX\\s0-style\n``From'' line\nto determine the sender.\nIf this is not present,\na nasty diagnostic is produced.\n.IR Sendmail (8)\nincludes the ``From'' line automatically.\n.PP\nNo message is sent\nif the initial\n``From'' line includes the string\n``-REQUEST@''\nor if a ``Precedence: bulk'' or ``Precedence: junk'' line\nis included in the header.\n.SH SEE\\ ALSO\nsendmail(8)\n"
  },
  {
    "path": "share/man/man1/vgrind.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)vgrind.1\t6.2.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH VGRIND 1 \"October 22, 1996\"\n.UC 4\n.SH NAME\nvgrind \\- grind nice listings of programs\n.SH SYNOPSIS\n.B vgrind\n[\n.B \\-f\n] [\n.B \\-\n] [\n.B \\-t\n] [\n.B \\-n\n] [\n.B \\-x\n] [\n.B \\-W\n] [\n.B \\-sn\n] [\n.B \\-h\nheader\n] [\n.B \\-d\nfile\n] [\n.BI \\-l language\n]\nname ...\n.SH DESCRIPTION\n.I Vgrind\nformats the program sources which are arguments \nin a nice style using\n.IR troff (1)\nComments are placed in italics, keywords in bold face,\nand the name of the current function is listed down the margin of each\npage as it is encountered.\n.PP\n.I Vgrind \nruns in two basic modes, filter mode or regular mode.  In filter mode \n.I vgrind\nacts as a filter in a manner similar to\n.IR tbl (1).\nThe standard input is passed directly to the standard output except\nfor lines bracketed by the \n.I troff-like\nmacros:\n.IP .vS\n- starts processing\n.IP .vE\n- ends processing\n.LP\nThese lines are formatted as described above.  The output from this\nfilter can be passed to \n.I troff \nfor output.  There need be no particular ordering with \n.IR eqn (1)\nor\n.IR tbl (1).\n.PP\nIn regular mode \n.I vgrind\naccepts input files, processes them, and passes them to \n.IR troff (1)\nfor output.  \n.PP\nIn both modes \n.I vgrind\npasses any lines beginning with a decimal point without conversion.\n.PP\nThe options are:\n.IP \\fB\\-f\\fP\nforces filter mode\n.IP \\fB\\-\\fP\nforces input to be taken from standard input (default if\n.B \\fB\\-f\\fP\nis specified )\n.IP \\fB\\-t\\fP\nsimilar to the same option in\n.I troff\ncausing formatted text to go to the standard output\n.IP \\fB\\-n\\fP\nforces no keyword bolding\n.IP \\fB\\-x\\fP\noutputs the index file in a ``pretty'' format. \nThe index file itself is produced whenever \n.I vgrind\nis run with a file called \n.I index\nin the current directory.\nThe index of function\ndefinitions can then be run off by giving \n.I vgrind \nthe\n.B \\-x\noption and the file\n.I index\nas argument.\n.IP \\fB\\-W\\fP\nforces output to the (wide) Versatec printer rather than the (narrow)\nVarian\n.IP \\fB\\-s\\fP\nspecifies a point size to use on output (exactly the same as the argument\nof a .ps)\n.IP \\fB\\-h\\fP\nspecifies a particular header to put on every output page (default is\nthe file name)\n.IP \\fB\\-d\\fP\nspecifies an alternate language definitions\nfile (default is /usr/share/misc/vgrindefs)\n.IP \\fB\\-l\\fP\nspecifies the language to use.  Currently known are PASCAL\n.RB ( \\-lp ),\nMODEL\n.RB ( \\-lm ), C\n.RB ( \\-lc\nor the default), CSH\n.RB ( \\-lcsh ), \nSHELL\n.RB ( \\-lsh ),\nRATFOR\n.RB ( \\-lr ),\nMODULA2\n.RB ( \\-lmod2 ),\nYACC\n.RB ( \\-lyacc ),\nISP\n.RB ( \\-lisp ),\nand ICON\n.RB ( \\-lI ).\n.SH FILES\n.ta 2i\nindex\tfile where source for index is created\n.br\n/usr/share/tmac/tmac.vgrind\tmacro package\n.br\n/usr/libexec/vfontedpr\t\tpreprocessor\n.br\n/usr/share/misc/vgrindefs\t\tlanguage descriptions\n.SH AUTHOR\nDave Presotto & William Joy\n.SH SEE ALSO\nvlp(1),\nvtroff(1),\nvgrindefs(5)\n.SH BUGS\nVfontedpr assumes that a certain programming style is followed:\n.PP\nFor \n.B C\n\\- function names can be preceded on a line only by spaces, tabs, or an\nasterisk.  The parenthesized arguments must also be on the same line.\n.PP\nFor\n.B PASCAL\n\\- function names need to appear on the same line as the keywords\n.I function\nor\n.I procedure.\n.PP\nFor\n.B MODEL\n\\- function names need to appear on the same line as the keywords\n.I is\n.I beginproc.\n.PP\nIf these conventions are not followed, the indexing and marginal function\nname comment mechanisms will fail.\n.sp\nMore generally, arbitrary formatting styles for programs mostly look bad.\nThe use of spaces to align source code fails miserably; if you plan to\n.I vgrind\nyour program you should use tabs.  This is somewhat inevitable since the\nfont used by\n.I vgrind\nis variable width.\n.PP\nThe mechanism of ctags in recognizing functions should be used here.\n.PP\nFilter mode does not work in documents using the \\-me or \\-ms macros.\n(So what use is it anyway?)\n"
  },
  {
    "path": "share/man/man1/vi.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)vi.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH VI 1 \"April 29, 1985\"\n.UC\n.SH NAME\nvi \\- screen oriented (visual) display editor based on ex\n.SH SYNOPSIS\n.B vi\n[\n.B \\-t\ntag\n] [\n.B \\-r\n] [\n\\fB+\\fR\\fIcommand\\fR\n] [\n.B \\-l\n] [\n\\fB\\-w\\fIn\\fR\n]\nname ...\n.SH DESCRIPTION\n.I Vi\n(visual) is a display oriented text editor based on\n.IR ex (1).\n.I Ex\nand\n.I vi\nrun the same code; it is possible to get to\nthe command mode of\n.I ex\nfrom within\n.I vi\nand vice-versa.\n.PP\nThe\n.I \"Vi Quick Reference\"\ncard and the\n.I \"Introduction to Display Editing with Vi\"\nprovide full details on using\n.I vi.\n.SH FILES\nSee\n.IR ex (1).\n.SH SEE ALSO\nex (1), edit (1), ``Vi Quick Reference'' card,\n``An Introduction to Display Editing with Vi''.\n.SH AUTHOR\nWilliam Joy\n.br\nMark Horton added macros to \\fIvisual\\fR mode and is maintaining version 3\n.SH BUGS\nSoftware tabs using \\fB^T\\fR work only immediately after the\n.I autoindent.\n.PP\nLeft and right shifts on intelligent terminals don't make use of\ninsert and delete character operations in the terminal.\n.PP\nThe\n.I wrapmargin\noption can be fooled since it looks at output columns when blanks are typed.\nIf a long word passes through the margin and onto the next line without a \nbreak, then the line won't be broken.\n.PP\nInsert/delete within a line can be slow if tabs are present on intelligent\nterminals, since the terminals need help in doing this correctly.\n.PP\nSaving text on deletes in the named buffers is somewhat inefficient.\n.PP\nThe\n.I source\ncommand does not work when executed as \\fB:source\\fR;\nthere is no way to use the \\fB:append\\fR, \\fB:change\\fR,\nand \\fB:insert\\fR commands, since it is not possible to give\nmore than one line of input to a \\fB:\\fR escape.  To use these\non a \\fB:global\\fR you must \\fBQ\\fR to \\fIex\\fR command mode,\nexecute them, and then reenter the screen editor with\n.I vi\nor\n.I open.\n"
  },
  {
    "path": "share/man/man1/vmstat.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)vmstat.1\t6.3 (Berkeley) 3/15/86\n.\\\"\n.TH VMSTAT 1 \"March 15, 1986\"\n.UC 4\n.de s1\n.if n .sp\n.if t .sp .1i\n..\n.de t1\n.if n .ta 5n\n.if t .ta 1i\n..\n.SH NAME\nvmstat \\- report virtual memory statistics\n.SH SYNOPSIS\n.B vmstat\n[\n.B \\-fsi\n]\n[ drives ]\n[ interval [ count ] ]\n.SH DESCRIPTION\n.I Vmstat\ndelves into the system and normally reports certain statistics kept about\nprocess, virtual memory, disk, trap and cpu activity.\nIf given a\n.B \\-f\nargument, it instead reports on the number of\n.I forks\nand\n.I vforks\nsince system startup and the number of pages of virtual memory involved in each\nkind of fork.\nIf given a\n.B \\-s\nargument, it instead prints the contents\nof the\n.I sum\nstructure, giving the total number of several kinds of paging related\nevents which have occurred since boot.\nIf given a\n.B \\-i\nargument, it instead reports on the number of\n.I interrupts\ntaken by each device since system startup.\n.PP\nIf none of these options are given,\n.I vmstat\nwill report in the first line a summary of the virtual memory activity \nsince the system has been booted.\nIf\n.I interval\nis specified, then successive lines are summaries over the last\n.I interval\nseconds.\n``vmstat 5'' will print what the system is doing every five seconds;\nthis is a good choice of printing interval since this is how often\nsome of the statistics are sampled in the system; others vary every\nsecond, running the output for a while will make it apparent which\nare recomputed every second.\nIf a\n.I count\nis given, the statistics are repeated\n.I count\ntimes.\nThe format fields are:\n.PP\nProcs: information about numbers of processes in various states.\n.s1\n.t1\n.nf\nr\tin run queue\nb\tblocked for resources (i/o, paging, etc.)\nw\trunnable or short sleeper (< 20 secs) but swapped\n.fi\n.s1\nMemory: information about the usage of virtual and real memory.\nVirtual pages are considered active if they belong to processes which\nare running or have run in the last 20 seconds.\nA ``page'' here is 1024 bytes.\n.s1\n.t1\n.nf\navm\tactive virtual pages\nfre\tsize of the free list\n.fi\n.s1\nPage: information about page faults and paging activity.\nThese are averaged each five seconds, and given in units per second.\n.s1\n.t1\n.nf\nre\tpage reclaims (simulating reference bits)\nat\tpages attached (found in free list)\npi\tpages paged in\npo\tpages paged out\nfr\tpages freed per second\nde\tanticipated short term memory shortfall\nsr\tpages scanned by clock algorithm, per-second\n.fi\n.s1\nup/hp/rk/ra: Disk operations per second (this field is system dependent).\nTypically paging will be split across several of the available drives.\nThe number under each of these is the unit number.\n.s1\nFaults: trap/interrupt rate averages per second over last 5 seconds.\n.s1\n.t1\n.nf\nin\t(non clock) device interrupts per second\nsy\tsystem calls per second\ncs\tcpu context switch rate (switches/sec)\n.fi\n.s1\nCpu: breakdown of percentage usage of CPU time\n.s1\n.nf\nus\tuser time for normal and low priority processes\nsy\tsystem time\nid\tcpu idle\n.fi\n.PP\nIf more than 4 disk drives are configured in the system,\n.I vmstat\ndisplays only the first 4 drives, with priority given\nto Massbus disk drives (i.e. if both Unibus and Massbus\ndrives are present and the total number of drives exceeds\n4, then some number of Unibus drives will not be displayed\nin favor of the Massbus drives).  To force\n.I vmstat\nto display specific drives, their names may be supplied on\nthe command line.\n.SH FILES\n/dev/kmem, /vmunix\n.SH SEE ALSO\n.IR systat (1),\n.IR iostat (1)\n.PP\nThe sections starting with ``Interpreting system activity'' in\n.IR \"Installing and Operating 4.2bsd\" .\n"
  },
  {
    "path": "share/man/man1/vwidth.1",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)vwidth.1\t6.1.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH VWIDTH 1 \"October 22, 1996\"\n.UC 5\n.SH NAME\nvwidth \\- make troff width table for a font\n.SH SYNOPSIS\n.B vwidth\nfontfile pointsize > ft\\fIxx\\fP.c\n.br\n.B cc -c ft\\fIxx\\fP.c\nmv ft\\fIxx\\fP.o /usr/share/font/ft\\fIxx\\fP\n.SH DESCRIPTION\n.I Vwidth\ntranslates from the width information stored in the vfont style\nformat to the format expected by troff.\nTroff wants an object file in a.out(5) format.\n(This fact does not seem to be documented anywhere.)\nTroff should look directly in the font file but it doesn't.\n.PP\nVwidth should be used after editing a font with\n.I fed(1).\nIt is not necessary to use vwidth unless you have made a change\nthat would affect the width tables.\nSuch changes include numerically editing the width field,\nadding a new character,\nand moving or copying a character to a new position.\nIt is\n.I not\nalways necessary to use vwidth if the physical width of the glyph\n(e.g. the number of columns in the bit matrix) has changed, but\nif it has changed much the logical width should probably be changed\nand vwidth run.\n.PP\nVwidth produces a C program on its standard output.\nThis program should be run through the C compiler and\nthe object (that is, the .o file) saved.\nThe resulting file should be placed in /usr/share/font\nin the file\n.RI ft xx\nwhere\n.II xx\nis a one or two letter code that is the logical (internal to troff)\nfont name.\nThis name can be found by looking in the file\n.RI /usr/share/fontinfo/ fname *\nwhere\n.I fname\nis the external name of the font.\n.SH \"SEE ALSO\"\nfed(1),\nvfont(5),\ntroff(1),\nvtroff(1)\n.SH BUGS\nProduces the C file using obsolete syntax\nthat the portable C compiler complains about.\n"
  },
  {
    "path": "share/man/man1/w.1",
    "content": ".TH W 1 \"November 28, 1996\"\n.UC\n.SH NAME\nw, uptime  \\- who is on and what they are doing; system time up\n.SH SYNOPSIS\n.B w\n[\n.B \\-hswu\n]\n[\nuser\n]\n.br\n.B uptime\n.SH DESCRIPTION\n.I W\nprints a summary of the current activity on the system,\nincluding what each user is doing.\n.PP\nThe\n.I uptime\ninvocation prints only the header line.\n.PP\nThe heading line shows the current time of day,\nhow long the system has been up,\nthe number of users logged into the system,\nand the load averages.\nThe load average numbers give the number of jobs in the run queue\naveraged over 1, 5 and 15 minutes.\n.PP\nThe fields output are:\nthe users login name,\nthe name of the tty the user is on,\nthe time of day the user logged on,\nthe number of minutes since the user last typed anything,\nthe CPU time used by all processes and their children on that terminal,\nthe CPU time used by the currently active processes,\nthe name and arguments of the current process.\n.PP\nThe\n.B \\-h\nflag suppresses the heading.\nThe\n.B \\-s\nflag asks for a short form of output.\nIn the short form, the tty is abbreviated, the login time and cpu times\nare left off, as are the arguments to commands.\n.PP\nThe\n.B \\-w\nand\n.B \\-u\nflags force the\n.I w\nand\n.I uptime\nactions respectively, regardless of the name the\nprogram is invoked as.\n.PP\nIf a\n.I user\nname is included,\nthe output will be restricted to that user.\n.SH FILES\n.ta 2i\n/var/run/utmp\tfor login names\n.br\n/dev/swap\tsecondary storage\n.SH \"SEE ALSO\"\nfinger(1), ps(1), who(1)\n.SH AUTHOR\nMark Horton\n.SH BUGS\nThe notion of the ``current process'' is muddy.\nThe current algorithm is ``the highest numbered process on\nthe terminal that is not ignoring interrupts,\nor, if there is none, the highest numbered process on the terminal''.\nThis fails, for example, in critical sections of programs\nlike the shell and editor,\nor when faulty programs running in the background\nfork and fail to ignore interrupts.\n(In cases where no process can be found,\n.I w\nprints ``\\-''.)\n.PP\nThe CPU time is only an estimate, in particular, if someone leaves a\nbackground processs running after logging out, the person currently\non that terminal is ``charged'' with the time.\n.PP\nBackground processes are not shown, even though they account for\nmuch of the load on the system.\n.PP\nSometimes processes, typically those in the background, are\nprinted with null or garbaged arguments.\nIn these cases, the name of the command is printed in parentheses.\n"
  },
  {
    "path": "share/man/man1/wait.1",
    "content": ".\\\"\t@(#)wait.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH WAIT 1 \"April 29, 1985\"\n.AT 3\n.SH NAME\nwait \\- await completion of process\n.SH SYNOPSIS\n.B wait\n.SH DESCRIPTION\nWait until all processes started with\n.B &\nhave completed,\nand report on abnormal terminations.\n.PP\nBecause the\n.IR  wait (2)\nsystem call must be executed in the parent process,\nthe Shell itself executes\n.I wait,\nwithout creating a new process.\n.SH \"SEE ALSO\"\nsh(1)\n.SH BUGS\nNot all the processes of a 3- or more-stage\npipeline are children of the Shell, and thus can't be waited for.\n(This bug does not apply to\n.IR csh (1).)\n"
  },
  {
    "path": "share/man/man1/wall.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)wall.1\t6.1.1 (2.11BSD) 1996/11/27\n.\\\"\n.TH WALL 1 \"November 27, 1996\"\n.UC 4\n.SH NAME\nwall \\- write to all users\n.SH SYNOPSIS\n.B wall\n.SH DESCRIPTION\n.I Wall\nreads its standard input until an end-of-file.\nIt then sends this message,\npreceded by\n`Broadcast Message ...',\nto all logged in users.\n.PP\nThe sender should be super-user to override\nany protections the users may have invoked.\n.SH FILES\n/dev/tty?\n.br\n/var/run/utmp\n.SH \"SEE ALSO\"\nmesg(1), write(1)\n.SH DIAGNOSTICS\n`Cannot send to ...' when the open on\na user's tty file fails.\n"
  },
  {
    "path": "share/man/man1/wc.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)wc.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH WC 1 \"April 29, 1985\"\n.UC 4\n.SH NAME\nwc \\- word count\n.SH SYNOPSIS\n.B wc\n[\n.B \\-lwc\n] \n[ name ... ]\n.SH DESCRIPTION\n.PP\n.I Wc\ncounts lines, words and characters \nin the named files, or in the standard input if no name appears.\nA word is a maximal string of characters delimited by spaces, tabs or newlines.\n.PP\nIf an argument beginning with one of ``lwc'' is present,\nthe specified counts (lines, words, or characters)\nare selected by the letters\n.BR l ,\n.BR w ,\nor\n.BR c .\nThe default is\n.BR \\-lwc .\n.SH BUGS\n"
  },
  {
    "path": "share/man/man1/what.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)what.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH WHAT 1 \"April 29, 1985\"\n.UC 4\n.SH NAME\nwhat \\- show what versions of object modules were used to construct a file\n.SH SYNOPSIS\n.B what\nname ...\n.SH DESCRIPTION\n.I What\nreads each file and searches for sequences of the form ``@(#)''\nas inserted by the source code control system.  It then prints the remainder\nof the string after this marker, up to a null character, newline, double\nquote, or ``>'' character.\n.SH BUGS\nAs SCCS is not licensed with UNIX/32V, this is a rewrite of the\n.I what\ncommand which is part of SCCS, and may not behave exactly the same as that\ncommand does.\n"
  },
  {
    "path": "share/man/man1/whatis.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)whatis.1\t6.3 (Berkeley) 5/7/86\n.\\\"\n.TH WHATIS 1 \"May 7, 1986\"\n.UC 4\n.SH NAME\nwhatis \\- describe what a command is\n.SH SYNOPSIS\n.B whatis\ncommand ...\n.SH DESCRIPTION\n.I Whatis\nlooks up a given command and gives the header line from the manual section.\nYou can then run the \n.IR man (1)\ncommand to get more information.\nIf the line starts `name(section) ...' you can do\n`man section name' to get the documentation for it.\nTry `whatis ed' and then you should do `man 1 ed' to get the manual.\n.PP\n.I Whatis\nis actually just the\n.B \\-f\noption to the\n.IR man (1)\ncommand.\n.SH FILES\n.DT\n/usr/man/whatis\tData base\n.SH \"SEE ALSO\"\nman(1), catman(8)\n"
  },
  {
    "path": "share/man/man1/which.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)which.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH WHICH 1 \"April 29, 1985\"\n.UC\n.SH NAME\nwhich \\- locate a program file including aliases and paths (\\fIcsh\\fR only)\n.SH SYNOPSIS\n.B which\n[ name ] ...\n.SH DESCRIPTION\n.I Which\ntakes a list of names and looks for the files which would be\nexecuted had these names been given as commands.\nEach argument is expanded if it is aliased,\nand searched for along the user's path.\nBoth aliases and path are taken from the user's \\&.cshrc file.\n.SH FILES\n.ta 1i\n~/\\&.cshrc\tsource of aliases and path values\n.SH DIAGNOSTICS\nA diagnostic is given for names which are aliased to more than a single\nword,\nor if an executable file with the argument name was not found in the path.\n.SH BUGS\nMust be executed by a csh, since only csh's know about aliases.\n"
  },
  {
    "path": "share/man/man1/who.1",
    "content": ".\\\"\t@(#)who.1\t6.1.1 (2.11BSD) 1996/11/27\n.\\\"\n.TH WHO 1 \"November 27, 1996\"\n.AT 3\n.SH NAME\nwho \\- who is on the system\n.SH SYNOPSIS\n.B who\n[ who-file ] [\n.B \"am I\"\n]\n.SH DESCRIPTION\n.I Who,\nwithout an argument,\nlists the login name, terminal name, and login time\nfor each current UNIX user.\n.PP\nWithout an argument,\n.I who\nexamines the\n.I /var/run/utmp\nfile to obtain its information.\nIf a file is given, that file is examined.\nTypically the given file will be /usr/adm/wtmp,\nwhich contains a record of all the logins since it\nwas created.\nThen\n.I who\nlists\nlogins, logouts, and crashes since the creation of\nthe wtmp file.\nEach login is listed with user name,\nterminal name (with `/dev/'\nsuppressed),\nand date and time.\nWhen an argument is given, logouts produce a similar line without a user name.\nReboots produce a line with `x' in the place of the device name,\nand a fossil time indicative of when the system went down.\n.PP\nWith two arguments,\nas in `who am I' (and also `who are you'),\n.I who\ntells who you are logged in as.\n.SH FILES\n/var/run/utmp\n.SH \"SEE ALSO\"\ngetuid(2), utmp(5)\n"
  },
  {
    "path": "share/man/man1/whois.1",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)whois.1\t6.2 (Berkeley) 6/6/85\n.\\\"\n.TH WHOIS 1 \"June 6, 1985\"\n.UC 6\n.SH NAME\nwhois \\- DARPA Internet user name directory service\n.SH SYNOPSIS\n.B whois\nname\n.SH DESCRIPTION\n.TP\nwhois help\nProduces a helpful message similar to the following:\n.PP\nPlease enter a name or a handle (``ident\"), such as ``Smith\"\nor ``SRI-NIC\".\nStarting with a period forces a name-only search;\nstarting with exclamation point forces handle-only.\nExamples:\n.nf\n\tSmith\t\t\t[looks for name or handle SMITH\t]\n\t!SRI-NIC\t\t\t[looks for handle SRI-NIC only\t]\n\t.Smith, John\t\t[looks for name JOHN SMITH only\t]\n.fi\nAdding ``...\" to the argument will match anything from that point,\ne.g. ``ZU...\" will match ZUL, ZUM, etc.\n.PP\nTo have the ENTIRE membership list of a group or organization,\nif you are asking about a group or org, shown with the record, use\nan asterisk character `*' directly preceding the given argument.\n[CAUTION: If there are a lot of members this will take a long time!]\nYou may of course use exclamation point and asterisk, or a period\nand asterisk together.\n.SH SEE ALSO\nRFC 812:  Nicname/Whois\n"
  },
  {
    "path": "share/man/man1/window.1",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)window.1\t6.5 (Berkeley) 5/12/86\n.\\\"\n.TH WINDOW 1 \"May 12, 1986\"\n.UC 6\n.SH NAME\nwindow \\- window environment\n.SH SYNOPSIS\n.B window\n[\n.B \\-t\n] [\n.B \\-f\n] [\n.B \\-d\n] [\n.B \\-e escape-char\n] [\n.B \\-c command\n]\n.SH DESCRIPTION\n\\fIWindow\\fP implements a window environment on\nASCII terminals.\n.PP\nA window is a rectangular portion of the physical terminal\nscreen associated with a set of processes.  Its size and\nposition can be changed by the user at any time.  Processes\ncommunicate with their window in the same way they normally\ninteract with a terminal--through their standard input, output,\nand diagnostic file descriptors.  The window program handles the\ndetails of redirecting input an output to and from the\nwindows.  At any one time, only one window can receive\ninput from the keyboard, but all windows can simultaneously send output\nto the display.\n.PP\nWindows can overlap and are framed as necessary.  Each window\nis named by one of the digits ``1'' to ``9''.  This one character\nidentifier, as well as a user definable label string, are displayed\nwith the window on the top edge of its frame.  A window can be\ndesignated to be in the \\fIforeground\\fP, in which case it will always be\non top of all normal, non-foreground windows, and can be covered\nonly by other foreground windows.  A window need not be completely\nwithin the edges of the terminal screen.  Thus a large window\n(possibly larger than the screen) may be positioned to show only\na portion of its full size.\n.PP\nEach window has a cursor and a set of control functions.  Most intelligent\nterminal operations such as line and\ncharacter deletion and insertion are supported.  Display modes\nsuch as underlining and reverse video are available if they are\nsupported by the terminal.  In addition,\nsimilar to terminals with multiple pages of memory,\neach window has a text buffer which can have more lines than the window\nitself.\n.SH OPTIONS\nWhen \\fIwindow\\fP starts up, the commands (see long commands below)\ncontained in the file \\fI.windowrc\\fP in the user's home directory are\nexecuted.  If it does not exist, two equal sized windows spanning\nthe terminal screen are created by default.\n.PP\nThe command line options are\n.TP\n.B \\-t\nTurn on terse mode (see \\fIterse\\fP command below).\n.TP\n.B \\-f\nFast.  Don't perform any startup action.\n.TP\n.B \\-d\nIgnore \\fI.windowrc\\fP and create the two default\nwindows instead.\n.TP\n.B \\-e escape-char\nSet the escape character to \\fIescape-char\\fP.  \\fIEscape-char\\fP\ncan be a single character, or in the form \\fI^X\\fP where \\fIX\\fP\nis any character, meaning control-\\fIX\\fP.\n.TP\n.B \\-c command\nExecute the string \\fIcommand\\fP as a long command (see below)\nbefore doing anything else.\n.SH \"PROCESS ENVIRONMENT\"\nWith each newly created window, a shell program is spawned with its\nprocess environment tailored to that window.  Its standard input,\noutput, and diagnostic file descriptors are bound to one end of either\na pseudo-terminal (\\fIpty\\fP (4)) or a UNIX domain socket\n(\\fIsocketpair\\fP (4)).  If a pseudo-terminal is used, then its special\ncharacters and modes (see \\fIstty\\fP (1)) are copied from the physical\nterminal.  A \\fItermcap\\fP (5) entry tailored to this window is created\nand passed as environment (\\fIenviron\\fP (5)) variable\n\\fITERMCAP\\fP.  The termcap entry contains the window's size and\ncharacteristics as well as information from the physical terminal,\nsuch as the existence of underline, reverse video, and other display\nmodes, and the codes produced by the terminal's function keys,\nif any.  In addition, the window size attributes of the pseudo-terminal\nare set to reflect the size of this window, and updated whenever\nit is changed by the user.  In particular, the editor \\fIvi\\fP (1) uses\nthis information to redraw its display.\n.SH OPERATION\n.PP\nDuring normal execution, \\fIwindow\\fP can be in one of two states:\nconversation mode and command mode.  In conversation mode, the\nterminal's real cursor is placed at the cursor position of a particular\nwindow--called the current window--and input from the keyboard is sent\nto the process in that window.  The current window is always\non top of all other windows, except those in foreground.  In addition,\nit is set apart by highlighting its identifier and label in reverse video.\n.PP\nTyping \\fIwindow\\fP's escape character (normally ^P) in conversation\nmode switches it into command mode.  In command mode, the top line of\nthe terminal screen becomes the command prompt window, and \\fIwindow\\fP\ninterprets input from the keyboard as commands to manipulate windows.\n.PP\nThere are two types of commands: short commands are usually one or two\nkey strokes; long commands are strings either typed by the user in the\ncommand window (see the ``:'' command below), or read from a file (see\n\\fIsource\\fP below).\n.SH \"SHORT COMMANDS\"\nBelow, \\fI#\\fP represents one of the digits ``1'' to ``9''\ncorresponding to the windows 1 to 9.  \\fI^X\\fP means control-\\fIX\\fP,\nwhere \\fPX\\fP is any character.  In particular, \\fI^^\\fP is\ncontrol-^.  \\fIEscape\\fP is the escape key, or \\fI^[\\fP.\n.TP\n.B #\nSelect window \\fI#\\fP as the current window\nand return to conversation mode.\n.TP\n.B %#\nSelect window \\fI#\\fP but stay in command mode.\n.TP\n.B ^^\nSelect the previous window and return to conversation\nmode.  This is useful for toggling between two windows.\n.TP\n.B escape\nReturn to conversation mode.\n.TP\n.B ^P\nReturn to conversation mode and write ^P to the\ncurrent window.  Thus, typing two ^P's in conversation\nmode sends one to the current window.  If the \\fIwindow\\fP\nescape is changed to some other character, that\ncharacter takes the place of ^P here.\n.TP\n.B ?\nList a short summary of commands.\n.TP\n.B ^L\nRedraw the screen.\n.TP\n.B q\nExit \\fIwindow\\fP.  Confirmation is requested.\n.TP\n.B ^Z\nSuspend \\fIwindow\\fP.\n.TP\n.B w\nCreate a new window.  The user is prompted for the positions\nof the upper left and lower right corners of the window.\nThe cursor is placed on the screen and the keys ``h'', ``j'',\n``k'', and ``l''\nmove the cursor left, down, up, and right, respectively.\nThe keys ``H'', ``J'', ``K'', and ``L'' move the cursor to the respective\nlimits of the screen.  Typing a number before the movement keys\nrepeats the movement that number of times.  Return enters the cursor position\nas the upper left corner of the window.  The lower right corner\nis entered in the same manner.  During this process,\nthe placement of the new window is indicated by a rectangular\nbox drawn on the screen, corresponding to where the new window\nwill be framed.  Typing escape at any point\ncancels this command.\n.IP\nThis window becomes the current window,\nand is given the first available ID.  The default buffer size\nis used (see \\fInline\\fP command below).\n.IP\nOnly fully visible windows can be created this way.\n.TP\n.B c#\nClose window \\fI#\\fP.  The process in the window is sent\nthe hangup signal (see \\fIkill\\fP (1)).  \\fICsh\\fP (1) should\nhandle this signal correctly and cause no problems.\n.TP\n.B m#\nMove window \\fI#\\fP to another location.  A box in the shape\nof the window is drawn on\nthe screen to indicate the new position of the window, and the same keys as\nthose for the \\fIw\\fP command are used to position the box.  The\nwindow can be moved partially off-screen.\n.TP\n.B M#\nMove window \\fI#\\fP to its previous position.\n.TP\n.B s#\nChange the size of window \\fI#\\fP.  The user is prompted\nto enter the new lower right corner of the window.  A box\nis drawn to indicate the new window size.  The same\nkeys used in \\fIw\\fP and \\fIm\\fP are used to enter the position.\n.TP\n.B S#\nChange window \\fI#\\fP to its previous size.\n.TP\n.B ^Y\nScroll the current window up by one line.\n.TP\n.B ^E\nScroll the current window down by one line.\n.TP\n.B ^U\nScroll the current window up by half the window size.\n.TP\n.B ^D\nScroll the current window down by half the window size.\n.TP\n.B ^B\nScroll the current window up by the full window size.\n.TP\n.B ^F\nScroll the current window down by the full window size.\n.TP\n.B h\nMove the cursor of the current window left by one column.\n.TP\n.B j\nMove the cursor of the current window down by one line.\n.TP\n.B k\nMove the cursor of the current window up by one line.\n.TP\n.B l\nMove the cursor of the current window right by one column.\n.TP\n.B ^S\nStop output in the current window.\n.TP\n.B ^Q\nStart output in the current window.\n.TP\n.B :\nEnter a line to be executed as long commands.  Normal line\nediting characters (erase character, erase word, erase line) are\nsupported.\n.SH \"LONG COMMANDS\"\nLong commands are a sequence of statements\nparsed much like a programming language, with a syntax\nsimilar to that of C.  Numeric and string expressions and variables\nare supported, as well as conditional statements.\n.PP\nThere are two data types: string and number.  A string is a sequence\nof letters or digits beginning with a letter.  ``_'' and ``.'' are\nconsidered letters.  Alternately, non-alphanumeric characters can\nbe included in strings by quoting them in ``\"'' or escaping them\nwith ``\\\\''.  In addition, the ``\\\\'' sequences of C are supported,\nboth inside and outside quotes (e.g., ``\\\\n'' is a new line,\n``\\\\r'' a carriage return).  For example, these are legal strings:\nabcde01234, \"&#$^*&#\", ab\"$#\"cd, ab\\\\$\\\\#cd, \"/usr/ucb/window\".\n.PP\nA number is an integer value in one of three forms:\na decimal number, an octal number preceded by ``0'',\nor a hexadecimal number preceded by ``0x'' or ``0X''.  The natural\nmachine integer size is used (i.e., the signed integer type\nof the C compiler).  As in C, a non-zero number represents\na boolean true.\n.PP\nThe character ``#'' begins a comment which terminates at the\nend of the line.\n.PP\nA statement is either a conditional or an expression.  Expression\nstatements are terminated with a new line or ``;''.  To continue\nan expression on the next line, terminate the first line with ``\\\\''.\n.SH \"CONDITIONAL STATEMENT\"\n\\fIWindow\\fP has a single control structure:\nthe fully bracketed if statement in the form\n.nf\n\tif <expr> then\n\t\t<statement>\n\t\t. . .\n\telsif <expr> then\n\t\t<statement>\n\t\t. . .\n\telse\n\t\t<statement>\n\t\t. . .\n\tendif\n.fi\nThe \\fIelse\\fP and \\fIelsif\\fP parts are optional, and the latter can\nbe repeated any number of times.  \\fI<Expr>\\fP must be numeric.\n.SH EXPRESSIONS\nExpressions in \\fIwindow\\fP are similar to those in the\nC language, with most C operators supported on numeric\noperands.  In addition, some are overloaded to operate on strings.\n.PP\nWhen an expression is used as a statement, its value is discarded\nafter evaluation.  Therefore, only expressions with side\neffects (assignments and function calls) are useful as statements.\n.PP\nSingle valued (no arrays) variables are supported, of both\nnumeric and string values.  Some variables are predefined.  They\nare listed below.\n.PP\nThe operators in order of increasing precedence:\n.TP\n.B <expr1> = <expr2>\nAssignment.  The variable of name \\fI<expr1>\\fP, which must be string valued,\nis assigned the result of \\fI<expr2>\\fP.  Returns the value of \\fI<expr2>\\fP.\n.TP\n.B <expr1> ? <expr2> : <expr3>\nReturns the value of \\fI<expr2>\\fP if \\fI<expr1>\\fP evaluates true\n(non-zero numeric value); returns the value of \\fI<expr3>\\fP otherwise.  Only\none of \\fI<expr2>\\fP and \\fI<expr3>\\fP is evaluated.  \\fI<Expr1>\\fP must\nbe numeric.\n.TP\n.B <expr1> || <expr2>\nLogical or.  Numeric values only.  Short circuit evaluation is supported\n(i.e., if \\fI<expr1>\\fP evaluates true, then \\fI<expr2>\\fP is not evaluated).\n.TP\n.B <expr1> && <expr2>\nLogical and with short circuit evaluation.  Numeric values only.\n.TP\n.B <expr1> | <expr2>\nBitwise or.  Numeric values only.\n.TP\n.B <expr1> ^ <expr2>\nBitwise exclusive or.  Numeric values only.\n.TP\n.B <expr1> & <expr2>\nBitwise and.  Numeric values only.\n.TP\n.B <expr1> == <expr2>, <expr1> != <expr2>\nComparison (equal and not equal, respectively).  The boolean\nresult (either 1 or 0) of the comparison is returned.  The\noperands can be numeric or string valued.  One string operand\nforces the other to be converted to a string in necessary.\n.TP\n.B <expr1> < <expr2>, <expr1> > <expr2>, <expr1> <= <expr2>, <expr1> >= <expr2>\nLess than, greater than, less than or equal to,\ngreater than or equal to.  Both numeric and string values, with\nautomatic conversion as above.\n.TP\n.B <expr1> << <expr2>, <expr1> >> <expr2>\nIf both operands are numbers, \\fI<expr1>\\fP is bit\nshifted left (or right) by \\fI<expr2>\\fP bits.  If \\fI<expr1>\\fP is\na string, then its first (or last) \\fI<expr2>\\fP characters are\nreturns (if \\fI<expr2>\\fP is also a string, then its length is used\nin place of its value).\n.TP\n.B <expr1> + <expr2>, <expr1> - <expr2>\nAddition and subtraction on numbers.  For ``+'', if one\nargument is a string, then the other is converted to a string,\nand the result is the concatenation of the two strings.\n.TP\n.B <expr1> * <expr2>, <expr1> / <expr2>, <expr1> % <expr2>\nMultiplication, division, modulo.  Numbers only.\n.TP\n.B -<expr>, ~<expr>, !<expr>, $<expr>, $?<expr>\nThe first three are unary minus, bitwise complement and logical complement\non numbers only.  The operator, ``$'', takes \\fI<expr>\\fP and returns\nthe value of the variable of that name.  If \\fI<expr>\\fP is numeric\nwith value \\fIn\\fP and it appears within an alias macro (see below),\nthen it refers to the nth argument of the alias invocation.  ``$?''\ntests for the existence of the variable \\fI<expr>\\fP, and returns 1\nif it exists or 0 otherwise.\n.TP\n.B <expr>(<arglist>)\nFunction call.  \\fI<Expr>\\fP must be a string that is the unique\nprefix of the name of a builtin \\fIwindow\\fP function\nor the full name of a user defined alias macro.  In the case of a builtin\nfunction, \\fI<arglist>\\fP can be in one of two forms:\n.br\n\t<expr1>, <expr2>, . . .\n.br\n\targname1 = <expr1>, argname2 = <expr2>, . . .\n.br\nThe two forms can in fact be intermixed, but the result is\nunpredictable.  Most arguments can be omitted; default values will\nbe supplied for them.  The \\fIargnames\\fP can be unique prefixes\nof the the argument names.  The commas separating\narguments are used only to disambiguate, and can usually be omitted.\n.IP\nOnly the first argument form is valid for user defined aliases.  Aliases\nare defined using the \\fIalias\\fP builtin function (see below).  Arguments\nare accessed via a variant of the variable mechanism (see ``$'' operator\nabove).\n.IP\nMost functions return value, but some are used for side effect\nonly and so must be used as statements.  When a function or an alias is used\nas a statement, the parenthesis surrounding\nthe argument list may be omitted.  Aliases return no value.\n.SH \"BUILTIN FUNCTIONS\"\nThe arguments are listed by name in their natural\norder.  Optional arguments are in square brackets (``[ ]'').  Arguments\nthat have no names are in angle brackets (``<>'').\n.TP\n.B alias([<string>], [<string-list>])\nIf no argument is given, all currently defined alias macros are\nlisted.  Otherwise, \\fI<string>\\fP is defined as an alias,\nwith expansion \\fI<string-list>\\fP.  The previous definition of\n\\fI<string>\\fP, if any, is returned.  Default for \\fI<string-list>\\fP\nis no change.\n.TP\n.B close(<window-list>)\nClose the windows specified in \\fI<window-list>\\fP.  If \\fI<window-list>\\fP\nis the word \\fIall\\fP, than all windows are closed.  No value is returned.\n.TP\n.B cursormodes([modes])\nSet the window cursor to \\fImodes\\fP.  \\fIModes\\fP is the bitwise\nor of the mode bits defined as the variables \\fIm_ul\\fP (underline),\n\\fIm_rev\\fP (reverse video), \\fIm_blk\\fP (blinking),\nand \\fIm_grp\\fP (graphics, terminal dependent).  Return\nvalue is the previous modes.  Default is no change.\nFor example, cursor($m_rev|$m_blk) sets the window cursors to blinking\nreverse video.\n.TP\n.B echo([window], [<string-list>])\nWrite the list of strings, \\fI<string-list>\\fP, to \\fIwindow\\fP, separated\nby spaces and terminated with a new line.  The strings are only\ndisplayed in the window, the processes in the window are not\ninvolved (see \\fIwrite\\fP below).  No value is returned.  Default\nis the current window.\n.TP\n.B escape([escapec])\nSet the escape character to \\fIescape-char\\fP.  Returns the old\nescape character as a one character string.  Default is no\nchange.  \\fPEscapec\\fP can be a string of a single character, or\nin the form \\fI^X\\fP, meaning control-\\fIX\\fP.\n.TP\n.B foreground([window], [flag])\nMove \\fIwindow\\fP in or out of foreground.  \\fIFlag\\fP\ncan be one of \\fIon\\fP, \\fIoff\\fP,\n\\fIyes\\fP, \\fIno\\fP, \\fItrue\\fP, or \\fIfalse\\fP, with obvious\nmeanings, or it can be a numeric expression, in which case\na non-zero value is true.  Returns the old foreground flag\nas a number.  Default for \\fIwindow\\fP is the current window,\ndefault for \\fIflag\\fP is no change.\n.TP\n.B label([window], [label])\nSet the label of \\fIwindow\\fP to \\fIlabel\\fP.  Returns the old\nlabel as a string.  Default for \\fIwindow\\fP is the current\nwindow, default for \\fIlabel\\fP is no change.  To turn\noff a label, set it to an empty string (\"\").\n.TP\n.B list()\nNo arguments.  List the identifiers and labels of all windows.  No\nvalue is returned.\n.TP\n.B nline([nline])\nSet the default buffer size to \\fInline\\fP.  Initially, it is\n48 lines.  Returns the old default buffer size.  Default is\nno change.  Using a very large buffer can slow the program down\nconsiderably.\n.TP\n.B select([window])\nMake \\fIwindow\\fP the current window.  The previous current window\nis returned.  Default is no change.\n.TP\n.B shell([<string-list>])\nSet the default window shell program to \\fI<string-list>\\fP.  Returns\nthe first string in the old shell setting.  Default is no change.  Initially,\nthe default shell is taken from the environment variable \\fISHELL\\fP.\n.TP\n.B source(filename)\nRead and execute the long commands in \\fIfilename\\fP.  Returns\n-1 if the file cannot be read, 0 otherwise.\n.TP\n.B terse([flag])\nSet terse mode to \\fIflag\\fP.  In terse mode, the command window\nstays hidden even in command mode, and errors are reported by\nsounding the terminal's bell.  \\fIFlag\\fP can take on the same\nvalues as in \\fIforeground\\fP above.  Returns the old terse flag.\nDefault is no change.\n.TP\n.B unalias(alias)\nUndefine \\fIalias\\fP.  Returns -1 if \\fIalias\\fP does not exist,\n0 otherwise.\n.TP\n.B unset(variable)\nUndefine \\fIvariable\\fP.  Returns -1 if \\fIvariable\\fP does not exist,\n0 otherwise.\n.TP\n.B variables()\nNo arguments.  List all variables.  No value is returned.\n.TP\n.B window([row], [column], [nrow], [ncol], [nline], [frame],\n.B [pty], [mapnl], [shell])\n.br\nOpen a window with upper left corner at \\fIrow\\fP, \\fIcolumn\\fP\nand size \\fInrow\\fP, \\fIncol\\fP.  If \\fInline\\fP is specified,\nthen that many lines are allocated for the text buffer.  Otherwise,\nthe default buffer size is used.  Default values for\n\\fIrow\\fP, \\fIcolumn\\fP, \\fInrow\\fP, and \\fIncol\\fP are, respectively,\nthe upper, left-most, lower, or right-most extremes of the\nscreen.  \\fIFrame\\fP, \\fIpty\\fP, and \\fImapnl\\fP are flag values\ninterpreted in the same way as the argument to \\fIforeground\\fP (see above);\nthey mean, respectively, put a frame around this window (default true),\nallocate pseudo-terminal for this window rather than socketpair (default\ntrue), and map new line characters in this window to carriage return\nand line feed (default true if socketpair is used, false otherwise).\n\\fIShell\\fP is a list of strings that will be used as the shell\nprogram to place in the window (default is the program specified\nby \\fIshell\\fP, see below).  The created window's identifier\nis returned as a number.\n.TP\n.B write([window], [<string-list>])\nSend the list of strings, \\fI<string-list>\\fP, to \\fIwindow\\fP, separated\nby spaces but not terminated with a new line.  The strings are actually\ngiven to the window as input.  No value is returned.  Default\nis the current window.\n.SH \"PREDEFINED VARIABLES\"\nThese variables are for information only.  Redefining them does\nnot affect the internal operation of \\fIwindow\\fP.\n.TP\n.B baud\nThe baud rate as a number between 50 and 38400.\n.TP\n.B modes\nThe display modes (reverse video, underline, blinking, graphics)\nsupported by the physical terminal.  The value of \\fImodes\\fP is\nthe bitwise or of some of the one bit values, \\fIm_blk\\fP, \\fIm_grp\\fP,\n\\fIm_rev\\fP, and \\fIm_ul\\fP (see below).  These values are useful\nin setting the window cursors' modes (see \\fIcursormodes\\fP above).\n.TP\n.B m_blk\nThe blinking mode bit.\n.TP\n.B m_grp\nThe graphics mode bit (not very useful).\n.TP\n.B m_rev\nThe reverse video mode bit.\n.TP\n.B m_ul\nThe underline mode bit.\n.TP\n.B ncol\nThe number of columns on the physical screen.\n.TP\n.B nrow\nThe number of rows on the physical screen.\n.TP\n.B term\nThe terminal type.  The standard name, found in the second name\nfield of the terminal's \\fITERMCAP\\fP entry, is used.\n.SH FILES\n.ta 15\n~/.windowrc\tstartup command file.\n.br\n/dev/[pt]ty[pq]?\tpseudo-terminal devices.\n.SH DIAGNOSTICS\nShould be self explanatory.\n.SH BUGS\n"
  },
  {
    "path": "share/man/man1/write.1",
    "content": ".\\\"\t@(#)write.1\t6.2.1 (2.11BSD) 1996/11/27\n.\\\"\n.TH WRITE 1 \"November 27, 1996\"\n.AT 3\n.SH NAME\nwrite \\- write to another user\n.SH SYNOPSIS\n.B write\nuser [ ttyname ]\n.SH DESCRIPTION\n.I Write\ncopies lines from your terminal to that of\nanother user.\nWhen first called,\nit sends the message\n.PP\n     Message from yourname@yoursystem on yourttyname at time...\n.PP\nThe recipient of the message should write back at this point.\nCommunication continues until an end of file is\nread from the terminal or an interrupt is sent.\nAt that point\n.I write\nwrites `EOT' on the other terminal and exits.\n.PP\nIf you want to write to a user who is logged in more than once,\nthe\n.I ttyname\nargument may be used to indicate the\nappropriate terminal name.\n.PP\nPermission to write may be denied or granted by use of the\n.I mesg\ncommand.\nAt the outset writing is allowed.\nCertain commands, in particular\n.I nroff\nand\n.IR  pr (1)\ndisallow\nmessages in order to prevent messy output.\n.PP\nIf the character `!' is found at the beginning of a line,\n.I write\ncalls the shell\nto execute the rest of the\nline as a command.\n.PP\nThe following protocol is suggested for using\n.IR write :\nwhen you first write to another user, wait for him to\nwrite back before starting to send.\nEach party should end each message with a distinctive\nsignal\\(em\\fB(o)\\fR\nfor `over' is conventional\\(emthat the other may reply.\n.B (oo)\nfor `over and out' is suggested when conversation\nis about to be terminated.\n.SH FILES\n/var/run/utmp\tto find user\n.br\n/bin/sh\t\tto execute `!'\n.SH \"SEE ALSO\"\nmesg(1), who(1), mail(1)\n"
  },
  {
    "path": "share/man/man1/xstr.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)xstr.1\t6.2 (Berkeley) 5/7/86\n.\\\"\n.TH XSTR 1 \"May 7, 1986\"\n.UC\n.SH NAME\nxstr \\- extract strings from C programs to implement shared strings\n.SH SYNOPSIS\n.B xstr\n[\n.B \\-c\n] [\n.B \\-\n] [\nfile\n]\n.SH DESCRIPTION\n.I Xstr\nmaintains a file\n.I strings\ninto which strings in component parts of a large program are hashed.\nThese strings are replaced with references to this common area.\nThis serves to implement shared constant strings, most useful if they\nare also read-only.\n.PP\nThe command\n.PP\n.DT\n\t\\fBxstr \\-c\\fR name\n.PP\nwill extract the strings from the C source in name, replacing\nstring references by expressions of the form (&xstr[number])\nfor some number.\nAn appropriate declaration of\n.I xstr\nis prepended to the file.\nThe resulting C text is placed in the file\n.I x.c,\nto then be compiled.\nThe strings from this file are placed in the\n.I strings\ndata base if they are not there already.\nRepeated strings and strings which are suffices of existing strings\ndo not cause changes to the data base.\n.PP\nAfter all components of a large program have been compiled a file\n.I xs.c\ndeclaring the common\n.I xstr\nspace can be created by a command of the form\n.PP\n.DT\n\t\\fBxstr\\fR\n.PP\nThis\n.I xs.c\nfile should then be compiled and loaded with the rest\nof the program.\nIf possible, the array can be made read-only (shared) saving\nspace and swap overhead.\n.PP\n.I Xstr\ncan also be used on a single file.\nA command\n.PP\n.DT\n\t\\fBxstr\\fR name\n.PP\ncreates files\n.I x.c\nand\n.I xs.c\nas before, without using or affecting any\n.I strings\nfile in the same directory.\n.PP\nIt may be useful to run\n.I xstr\nafter the C preprocessor if any macro definitions yield strings\nor if there is conditional code which contains strings\nwhich may not, in fact, be needed.\n.I Xstr\nreads from its standard input when the argument `\\-' is given.\nAn appropriate command sequence for running\n.I xstr\nafter the C preprocessor is:\n.PP\n.nf\n.DT\n\t\\fBcc \\-E\\fR name.c | \\fBxstr \\-c\\fR \\-\n\t\\fBcc \\-c\\fR x.c\n\t\\fBmv\\fR x.o name.o\n.fi\n.PP\n.I Xstr\ndoes not touch the file\n.I strings\nunless new items are added, thus\n.I make\ncan avoid remaking\n.I xs.o\nunless truly necessary.\n.SH FILES\n.DT\nstrings\t\tData base of strings\n.br\nx.c\t\tMassaged C source\n.br\nxs.c\t\tC source for definition of array `xstr'\n.br\n/tmp/xs*\tTemp file when `xstr name' doesn't touch\n.I strings\n.SH \"SEE ALSO\"\nmkstr(1)\n.SH BUGS\nIf a string is a suffix of another string in the data base,\nbut the shorter string is seen first by\n.I xstr\nboth strings will be placed in the data base, when just\nplacing the longer one there will do.\n"
  },
  {
    "path": "share/man/man1/yacc.1",
    "content": ".\\\"\t@(#)yacc.1\t6.1.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH YACC 1 \"October 22, 1996\"\n.AT 3\n.SH NAME\nyacc \\- yet another compiler-compiler\n.SH SYNOPSIS\n.B yacc\n[\n.B \\-vd\n]\ngrammar\n.SH DESCRIPTION\n.I Yacc\nconverts a context-free grammar into a set of\ntables for a simple automaton which executes an LR(1) parsing\nalgorithm.\nThe grammar may be ambiguous;\nspecified precedence rules are used to break ambiguities.\n.PP\nThe output file,\n.IR y.tab.c ,\nmust be compiled by the C compiler\nto produce a program\n.IR yyparse .\nThis program must be loaded with the lexical analyzer program,\n.IR yylex ,\nas well as\n.I main\nand\n.IR yyerror ,\nan error handling routine.\nThese routines must be supplied by the user;\n.IR Lex (1)\nis useful for creating lexical analyzers usable by\n.IR yacc .\n.PP\nIf the\n.B \\-v\nflag is given, the file\n.I y.output\nis prepared, which contains a description of the parsing tables\nand a report on\nconflicts generated by ambiguities in the grammar.\n.PP\nIf the \\-\\fBd\\fR flag is used, the file\n.I y.tab.h\nis generated with the\n.I define\nstatements that associate the\n.I yacc\\c\n-assigned `token codes' with the user-declared `token names'.\nThis allows source files other than\n.I y.tab.c\nto access the token codes.\n.SH FILES\n.ta \\w'yacc.tmp, yacc.acts 'u\ny.output\n.br\ny.tab.c\n.br\ny.tab.h\tdefines for token names\n.br\nyacc.tmp, yacc.acts\ttemporary files\n.br\n/usr/share/misc/yaccpar\tparser prototype for C programs\n.SH \"SEE ALSO\"\n.IR lex (1)\n.br\n.I \"LR Parsing\"\nby A. V. Aho and S. C. Johnson,\nComputing Surveys, June, 1974.\n.br\n.I \"YACC \\- Yet Another Compiler Compiler\"\nby S. C. Johnson.\n.SH DIAGNOSTICS\nThe number of reduce-reduce and shift-reduce conflicts\nis reported on the standard output;\na more detailed report is\nfound in the\n.I y.output\nfile.\nSimilarly, if some rules are not reachable from the\nstart symbol, this is also reported.\n.SH BUGS\nBecause file names are fixed, at most one\n.I yacc\nprocess can be active in a given directory at\na time.\n"
  },
  {
    "path": "share/man/man1/yes.1",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)yes.1\t6.1 (Berkeley) 4/29/85\n.\\\"\n.TH YES 1 \"April 29, 1985\"\n.UC 4\n.SH NAME\nyes \\- be repetitively affirmative\n.SH SYNOPSIS\n.B yes\n[\n.I expletive\n]\n.SH DESCRIPTION\n.I Yes\nrepeatedly outputs \\*(lqy\\*(rq, or if\n.I expletive\nis given, that is output repeatedly.  Termination is by rubout.\n"
  },
  {
    "path": "share/man/man2/Makefile",
    "content": "#\n# Copyright (c) 1987 Regents of the University of California.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms are permitted\n# provided that the above copyright notice and this paragraph are\n# duplicated in all such forms and that any documentation,\n# advertising materials, and other materials related to such\n# distribution and use acknowledge that the software was developed\n# by the University of California, Berkeley.  The name of the\n# University may not be used to endorse or promote products derived\n# from this software without specific prior written permission.\n# THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n# IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n# WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n#\n#\t@(#)Makefile\t2.11 (2.11BSD) 2000/3/4\n#\nTOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nMDIR=\t/usr/share/man/cat2\nSRCS=\taccept.2 access.2 acct.2 adjtime.2 bind.2 brk.2 chdir.2 chmod.2 \\\n\tchown.2 chroot.2 close.2 connect.2 creat.2 dup.2 execve.2 exit.2 \\\n\tchflags.2 \\\n\tfcntl.2 fetchi.2 flock.2 fork.2 fperr.2 fsync.2 getdtablesize.2 \\\n\tgetgroups.2 gethostid.2 gethostname.2 getitimer.2 \\\n\tgetpagesize.2 getpeername.2 getpgrp.2 getpid.2 getpriority.2 \\\n\tgetrlimit.2 getrusage.2 getsockname.2 getsockopt.2 gettimeofday.2 \\\n\tgetfsstat.2 getlogin.2 \\\n\tgetuid.2 setreuid.2 setuid.2 getgid.2 setregid.2 \\\n\tintro.2 ioctl.2 kill.2 killpg.2 link.2 listen.2 \\\n\tlock.2 lseek.2 mkdir.2 mknod.2 mount.2 nostk.2 open.2 phys.2 \\\n\tpipe.2 profil.2 ptrace.2 quota.2 read.2 readlink.2 reboot.2 \\\n\trecv.2 rename.2 rmdir.2 select.2 send.2 setgroups.2 setpgrp.2 \\\n\tsetquota.2 shutdown.2 sigblock.2 sigpause.2 \\\n\tsigaction.2 sigaltstack.2 sigpending.2 sigprocmask.2 sigsuspend.2 \\\n\tsigreturn.2 sigsetmask.2 sigstack.2 sigwait.2 sigvec.2 socket.2 \\\n\tsocketpair.2 \\\n\tstat.2 statfs.2 swapon.2 symlink.2 sync.2 syscall.2 truncate.2 ucall.2 \\\n\tumask.2 unlink.2 utimes.2 vfork.2 vhangup.2 wait.2 write.2\nOBJS=\taccept.0 access.0 acct.0 adjtime.0 bind.0 brk.0 chdir.0 chmod.0 \\\n\tchown.0 chroot.0 close.0 connect.0 creat.0 dup.0 execve.0 exit.0 \\\n\tchflags.0 \\\n\tfcntl.0 fetchi.0 flock.0 fork.0 fperr.0 fsync.0 getdtablesize.0 \\\n\tgetgroups.0 gethostid.0 gethostname.0 getitimer.0 \\\n\tgetpagesize.0 getpeername.0 getpgrp.0 getpid.0 getpriority.0 \\\n\tgetrlimit.0 getrusage.0 getsockname.0 getsockopt.0 gettimeofday.0 \\\n\tgetfsstat.0 getlogin.0 \\\n\tgetuid.0 setreuid.0 setuid.0 getgid.0 setregid.0 \\\n\tintro.0 ioctl.0 kill.0 killpg.0 link.0 listen.0 \\\n\tlock.0 lseek.0 mkdir.0 mknod.0 mount.0 nostk.0 open.0 phys.0 \\\n\tpipe.0 profil.0 ptrace.0 quota.0 read.0 readlink.0 reboot.0 \\\n\trecv.0 rename.0 rmdir.0 select.0 send.0 setgroups.0 setpgrp.0 \\\n\tsetquota.0 shutdown.0 sigblock.0 sigpause.0 \\\n\tsigaction.0 sigaltstack.0 sigpending.0 sigprocmask.0 sigsuspend.0 \\\n\tsigreturn.0 sigsetmask.0 sigstack.0 sigwait.0 sigvec.0 socket.0 \\\n\tsocketpair.0 \\\n\tstat.0 statfs.0 swapon.0 symlink.0 sync.0 syscall.0 truncate.0 ucall.0 \\\n\tumask.0 unlink.0 utimes.0 vfork.0 vhangup.0 wait.0 write.0\n\n.SUFFIXES: .2 .0\n\n.2.0:\n\t${MANROFF} $*.2 > $*.0\n\nall: _make_01\n\n_make_01: ${OBJS}\n\nclean: FRC\n\trm -f ${OBJS}\n\nP=${DESTDIR}${MDIR}\n\nREM= sbrk.0 dup2.0 fstat.0 lstat.0 readv.0 recvfrom.0 sendmsg.0 recvmsg.0 \\\n\tsendto.0 fstatfs.0 wait3.0 wait4.0 waitpid.0 fchdir.0 fchflags.0 \\\n\tfchmod.0 fchown.0 umount.0 writev.0 getppid.0 ftruncate.0 \\\n\tpselect.0 \\\n\tsethostid.0 setitimer.0 setrlimit.0 setsockopt.0 sethostname.0 \\\n\tsetpriority.0 settimeofday.0 setlogin.0 geteuid.0 setgid.0 \\\n\tseteuid.0 setegid.0 getegid.0\n\ninstall: _make_01\n\tcp ${OBJS} ${P}\n\tln -f ${P}/dup.0 ${P}/dup2.0\n\tln -f ${P}/brk.0 ${P}/sbrk.0\n\tln -f ${P}/stat.0 ${P}/fstat.0\n\tln -f ${P}/stat.0 ${P}/lstat.0\n\tln -f ${P}/read.0 ${P}/readv.0\n\tln -f ${P}/recv.0 ${P}/recvfrom.0\n\tln -f ${P}/recv.0 ${P}/recvmsg.0\n\tln -f ${P}/send.0 ${P}/sendmsg.0\n\tln -f ${P}/send.0 ${P}/sendto.0\n\tln -f ${P}/statfs.0 ${P}/fstatfs.0\n\tln -f ${P}/wait.0 ${P}/wait3.0\n\tln -f ${P}/wait.0 ${P}/wait4.0\n\tln -f ${P}/wait.0 ${P}/waitpid.0\n\tln -f ${P}/chmod.0 ${P}/fchdir.0\n\tln -f ${P}/chflags.0 ${P}/fchflags.0\n\tln -f ${P}/chmod.0 ${P}/fchmod.0\n\tln -f ${P}/chown.0 ${P}/fchown.0\n\tln -f ${P}/mount.0 ${P}/umount.0\n\tln -f ${P}/select.0 ${P}/pselect.0\n\tln -f ${P}/write.0 ${P}/writev.0\n\tln -f ${P}/getpid.0 ${P}/getppid.0\n\tln -f ${P}/truncate.0 ${P}/ftruncate.0\n\tln -f ${P}/gethostid.0 ${P}/sethostid.0\n\tln -f ${P}/getitimer.0 ${P}/setitimer.0\n\tln -f ${P}/getrlimit.0 ${P}/setrlimit.0\n\tln -f ${P}/getsockopt.0 ${P}/setsockopt.0\n\tln -f ${P}/gethostname.0 ${P}/sethostname.0\n\tln -f ${P}/getpriority.0 ${P}/setpriority.0\n\tln -f ${P}/gettimeofday.0 ${P}/settimeofday.0\n\tln -f ${P}/getlogin.0 ${P}/setlogin.0\n\tln -f ${P}/getuid.0 ${P}/geteuid.0\n\tln -f ${P}/getgid.0 ${P}/getegid.0\n\tln -f ${P}/setuid.0 ${P}/setgid.0\n\tln -f ${P}/setuid.0 ${P}/seteuid.0\n\tln -f ${P}/setuid.0 ${P}/setegid.0\n\nFRC:\n"
  },
  {
    "path": "share/man/man2/accept.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)accept.2\t6.3 (Berkeley) 5/22/86\n.\\\"\n.TH ACCEPT 2 \"May 22, 1986\"\n.UC 5\n.SH NAME\naccept \\- accept a connection on a socket\n.SH SYNOPSIS\n.ft B\n.nf\n#include <sys/types.h>\n#include <sys/socket.h>\n.PP\n.ft B\nns = accept(s, addr, addrlen)\nint ns, s;\nstruct sockaddr *addr;\nint *addrlen;\n.fi\n.SH DESCRIPTION\nThe argument\n.I s\nis a socket that has been created with\n.IR socket (2),\nbound to an address with\n.IR bind (2),\nand is listening for connections after a\n.IR listen (2).\n.I Accept\nextracts the first connection\non the queue of pending connections, creates\na new socket with the same properties of \n.I s\nand allocates a new file descriptor,\n.IR ns ,\nfor the socket.  If no pending connections are\npresent on the queue, and the socket is not marked\nas non-blocking,\n.I accept\nblocks the caller until a connection is present.\nIf the socket is marked non-blocking and no pending\nconnections are present on the queue, \n.I accept\nreturns an error as described below.\nThe accepted socket,\n.IR ns ,\nmay not be used\nto accept more connections.  The original socket\n.I s\nremains open.\n.PP\nThe argument\n.I addr\nis a result parameter that is filled in with\nthe address of the connecting entity,\nas known to the communications layer.\nThe exact format of the\n.I addr\nparameter is determined by the domain in which the communication\nis occurring.\nThe \n.I addrlen\nis a value-result parameter; it should initially contain the\namount of space pointed to by\n.IR addr ;\non return it will contain the actual length (in bytes) of the\naddress returned.\nThis call\nis used with connection-based socket types, currently with SOCK_STREAM.\n.PP\nIt is possible to\n.IR select (2)\na socket for the purposes of doing an\n.I accept\nby selecting it for read.\n.SH \"RETURN VALUE\nThe call returns \\-1 on error.  If it succeeds, it returns a non-negative\ninteger that is a descriptor for the accepted socket.\n.SH ERRORS\nThe \\fIaccept\\fP will fail if:\n.TP 20\n[EBADF]\nThe descriptor is invalid.\n.TP 20\n[ENOTSOCK]\nThe descriptor references a file, not a socket.\n.TP 20\n[EOPNOTSUPP]\nThe referenced socket is not of type SOCK_STREAM.\n.TP 20\n[EFAULT]\nThe \\fIaddr\\fP parameter is not in a writable part of the\nuser address space.\n.TP 20\n[EWOULDBLOCK]\nThe socket is marked non-blocking and no connections\nare present to be accepted.\n.SH SEE ALSO\nbind(2), connect(2), listen(2), select(2), socket(2)\n"
  },
  {
    "path": "share/man/man2/access.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)access.2\t6.5 (Berkeley) 5/22/86\n.\\\"\n.TH ACCESS 2 \"May 22, 1986\"\n.UC 4\n.SH NAME\naccess \\- determine accessibility of file\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/file.h>\n.PP\n.ft B\n.ta 1.25i 1.6i\n#define R_OK\t4\t/* test for read permission */\n#define W_OK\t2\t/* test for write permission */\n#define X_OK\t1\t/* test for execute (search) permission */\n#define F_OK\t0\t/* test for presence of file */\n.PP\n.ft B\naccessible = access(path, mode)\nint accessible;\nchar *path;\nint mode;\n.ft R\n.fi\n.SH DESCRIPTION\n.I Access\nchecks the given\nfile\n.I path\nfor accessibility according to\n.IR mode ,\nwhich is an inclusive or of the bits\nR_OK,\nW_OK\nand\nX_OK.\nSpecifying\n.I mode\nas F_OK (i.e., 0)\ntests whether the directories leading to the file can be\nsearched and the file exists.\n.PP\nThe real user ID and the group access list\n(including the real group ID) are\nused in verifying permission, so this call\nis useful to set-UID programs.\n.PP\nNotice that only access bits are checked.\nA directory may be indicated as writable by\n.IR access ,\nbut an attempt to open it for writing will fail\n(although files may be created there);\na file may look executable, but\n.I execve\nwill fail unless it is in proper format.\n.SH \"RETURN VALUE\nIf\n.I path\ncannot be found or if any of the desired access modes would\nnot be granted, then a \\-1 value is returned; otherwise\na 0 value is returned.\n.SH \"ERRORS\nAccess to the file is denied if one or more of the following are true:\n.TP 15\n[ENOTDIR]\nA component of the path prefix is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 255 characters,\nor an entire path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nThe named file does not exist.\n.TP 15\n[EACCES]\nSearch permission is denied for a component of the path prefix.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[EROFS]\nWrite access is requested for a file on a read-only file system.\n.TP 15\n[ETXTBSY]\nWrite access is requested for a pure procedure (shared text)\nfile that is being executed.\n.TP 15\n[EACCES]\nPermission bits of the file mode do not permit the requested\naccess, or search permission is denied on a component of the\npath prefix.  The owner of a file has permission checked with\nrespect to the ``owner'' read, write, and execute mode bits,\nmembers of the file's group other than the owner have permission\nchecked with respect to the ``group'' mode bits, and all\nothers have permissions checked with respect to the ``other''\nmode bits.\n.TP 15\n[EFAULT]\n.I Path\npoints outside the process's allocated address space.\n.TP 15\n[EIO]\nAn I/O error occurred while reading from or writing to the file system.\n.SH \"SEE ALSO\nchmod(2), stat(2)\n"
  },
  {
    "path": "share/man/man2/acct.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)acct.2\t6.4 (Berkeley) 5/22/86\n.\\\"\n.TH ACCT 2 \"May 22, 1986\"\n.UC 4\n.SH NAME\nacct \\- turn accounting on or off\n.SH SYNOPSIS\n.nf\n.ft B\nacct(file)\nchar *file;\n.ft R\n.fi\n.SH DESCRIPTION\nThe system is prepared to write a record\nin an accounting\n.I file\nfor each process as it terminates.\nThis\ncall, with a null-terminated string naming an existing file\nas argument, turns on accounting;\nrecords for each terminating process are appended to\n.IR file .\nAn argument of 0 causes accounting to be turned off.\n.PP\nThe accounting file format is given in\n.IR acct (5).\n.PP\nThis call is permitted only to the super-user.\n.SH NOTES\nAccounting is automatically disabled when the file system the\naccounting file resides on runs out of space; it is enabled when\nspace once again becomes available.\n.SH \"RETURN VALUE\nOn error \\-1 is returned.\nThe file must exist and the call may be exercised only by the super-user.\nIt is erroneous to try to turn on accounting when it is already on.\n.SH ERRORS\n.I Acct\nwill fail if one of the following is true:\n.TP 15\n[EPERM]\nThe caller is not the super-user.\n.TP 15\n[ENOTDIR]\nA component of the path prefix is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 255 characters,\nor an entire path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nThe named file does not exist.\n.TP 15\n[EACCES]\nSearch permission is denied for a component of the path prefix,\nor the path name is not a regular file.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[EROFS]\nThe named file resides on a read-only file system.\n.TP 15\n[EFAULT]\n.I File\npoints outside the process's allocated address space.\n.TP 15\n[EIO]\nAn I/O error occurred while reading from or writing to the file system.\n.SH \"SEE ALSO\"\nacct(5), sa(8)\n.SH BUGS\nNo accounting is produced for programs running\nwhen a crash occurs.\nIn particular non-terminating programs are never\naccounted for.\n"
  },
  {
    "path": "share/man/man2/adjtime.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)adjtime.2\t1.3 (Berkeley) 5/15/86\n.\\\"\n.TH ADJTIME 2 \"May 15, 1986\"\n.UC 6\n.SH NAME\nadjtime \\- correct the time to allow synchronization of the system clock\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/time.h>\n.PP\n.ft B\nadjtime(delta, olddelta)\nstruct timeval *delta; \nstruct timeval *olddelta;\n.fi\n.SH DESCRIPTION\n.I Adjtime\nmakes small adjustments to the system time, as returned by\n.IR gettimeofday (2),\nadvancing or retarding it\nby the time specified by the timeval\n\\fIdelta\\fP.\nIf \\fIdelta\\fP is negative, the clock is\nslowed down by incrementing it more slowly than normal until\nthe correction is complete.\nIf \\fIdelta\\fP is positive, a larger increment than normal\nis used.\nThe skew used to perform the correction is generally a fraction of one percent.\nThus, the time is always\na monotonically increasing function.\nA time correction from an earlier call to \\fIadjtime\\fP\nmay not be finished when \\fIadjtime\\fP is called again.\nIf \\fIolddelta\\fP is non-zero,\nthen the structure pointed to will contain, upon return, the\nnumber of microseconds still to be corrected\nfrom the earlier call.\n.PP\nThis call may be used by time servers that synchronize the clocks\nof computers in a local area network.\nSuch time servers would slow down the clocks of some machines\nand speed up the clocks of others to bring them to the average network time.\n.PP\nThe call \n.IR adjtime (2)\nis restricted to the super-user.\n.SH \"RETURN VALUE\nA return value of 0 indicates that the call succeeded.\nA return value of \\-1 indicates that an error occurred, and in this\ncase an error code is stored in the global variable \\fIerrno\\fP.\n.SH \"ERRORS\nThe following error codes may be set in \\fIerrno\\fP:\n.TP 15\n[EFAULT]\nAn argument points outside the process's allocated address space.\n.TP 15\n[EPERM]\nThe process's effective user ID is not that of the super-user.\n.SH \"SEE ALSO\"\ndate(1), gettimeofday(2), timed(8), timedc(8),\n.br\n\\fITSP: The Time Synchronization Protocol for UNIX 4.3BSD\\fP, \nR. Gusella and S. Zatti\n.SH \"NOTES  (PDP-11)\"\n\\fIAdjtime\\fP(2) calls are executed immediately, not over a\nperiod of time, therefore, the \\fIolddelta\\fP return values for an\n\\fIadjtime\\fP(2) call will always be zero.\n"
  },
  {
    "path": "share/man/man2/bind.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)bind.2\t6.6 (Berkeley) 5/22/86\n.\\\"\n.TH BIND 2 \"May 22, 1986\"\n.UC 5\n.SH NAME\nbind \\- bind a name to a socket\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/types.h>\n#include <sys/socket.h>\n.PP\n.ft B\nbind(s, name, namelen)\nint s;\nstruct sockaddr *name;\nint namelen;\n.fi\n.SH DESCRIPTION\n.I Bind\nassigns a name to an unnamed socket.\nWhen a socket is created \nwith\n.IR socket (2)\nit exists in a name space (address family)\nbut has no name assigned.\n.I Bind\nrequests that\n.IR name \nbe assigned to the socket.\n.SH NOTES\nBinding a name in the UNIX domain creates a socket in the file\nsystem that must be deleted by the caller when it is no longer\nneeded (using\n.IR unlink (2)).\n.PP\nThe rules used in name binding vary between communication domains.\nConsult the manual entries in section 4 for detailed information.\n.SH \"RETURN VALUE\nIf the bind is successful, a 0 value is returned.\nA return value of \\-1 indicates an error, which is\nfurther specified in the global \\fIerrno\\fP.\n.SH ERRORS\nThe \\fIbind\\fP call will fail if:\n.TP 20\n[EBADF]\n\\fIS\\fP is not a valid descriptor.\n.TP 20\n[ENOTSOCK]\n\\fIS\\fP is not a socket.\n.TP 20\n[EADDRNOTAVAIL]\nThe specified address is not available from the local machine.\n.TP 20\n[EADDRINUSE]\nThe specified address is already in use.\n.TP 20\n[EINVAL]\nThe socket is already bound to an address.\n.TP 20\n[EACCES]\nThe requested address is protected, and the current user\nhas inadequate permission to access it.\n.TP 20\n[EFAULT]\nThe \\fIname\\fP parameter is not in a valid part of the user\naddress space.\n.PP\nThe following errors are specific to binding names in the UNIX domain.\n.TP 15\n[ENOTDIR]\nA component of the path prefix is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 255 characters,\nor an entire path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nA prefix component of the path name does not exist.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[EIO]\nAn I/O error occurred while making the directory entry or allocating the inode.\n.TP 15\n[EROFS]\nThe name would reside on a read-only file system.\n.TP 15\n[EISDIR]\nA null pathname was specified.\n.SH SEE ALSO\nconnect(2), listen(2), socket(2), getsockname(2)\n"
  },
  {
    "path": "share/man/man2/brk.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)brk.2\t6.3 (Berkeley) 5/22/86\n.\\\"\n.TH BRK 2 \"May 22, 1986\"\n.UC 4\n.SH NAME\nbrk, sbrk \\- change data segment size\n.SH SYNOPSIS\n.nf\n#include <sys/types.h>\n.PP\n.ft B\nchar *brk(addr)\nchar *addr;\n.PP\n.ft B\nchar *sbrk(incr)\nint incr;\n.fi\n.SH DESCRIPTION\n.I Brk\nsets the system's idea of the lowest data segment \nlocation not used by the program (called the break)\nto\n.I addr\n(rounded up to the next multiple of the system's page size).\nLocations greater than\n.I addr\nand below the stack pointer\nare not in the address space and will thus\ncause a memory violation if accessed.\n.PP\nIn the alternate function\n.IR sbrk ,\n.I incr\nmore bytes are added to the\nprogram's data space and a pointer to the\nstart of the new area is returned.\n.PP\nWhen a program begins execution via\n.I execve\nthe break is set at the\nhighest location defined by the program\nand data storage areas.\nOrdinarily, therefore, only programs with growing\ndata areas need to use\n.IR sbrk .\n.PP\nThe\n.IR getrlimit (2)\nsystem call may be used to determine\nthe maximum permissible size of the\n.I data\nsegment;\nit will not be possible to set the break\nbeyond the\n.I rlim_max\nvalue returned from a call to\n.IR getrlimit ,\ne.g. \\*(lqetext + rlp\\(->rlim_max.\\*(rq\n(see\n.IR end (3)\nfor the definition of\n.IR etext ).\n.SH \"RETURN VALUE\nZero is returned if the \n.I brk\ncould be set;\n\\-1 if the program requests more\nmemory than the system limit.\n.I Sbrk\nreturns \\-1 if the break could not be set.\n.SH ERRORS\n.I Sbrk\nwill fail and no additional memory will be allocated if\none of the following are true:\n.TP 15\n[ENOMEM]\nThe limit, as set by\n.IR setrlimit (2),\nwas exceeded.\n.TP 15\n[ENOMEM]\nThe maximum possible size of a data segment (compiled into the\nsystem) was exceeded.\n.TP 15\n[ENOMEM]\nInsufficient space existed in the swap area\nto support the expansion.\n.SH \"SEE ALSO\"\nexecve(2), getrlimit(2), malloc(3), end(3)\n.SH BUGS\nSetting the break may fail due to a temporary lack of\nswap space.  It is not possible to distinguish this\nfrom a failure caused by exceeding the maximum size of\nthe data segment without consulting \n.IR getrlimit .\n"
  },
  {
    "path": "share/man/man2/chdir.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)chdir.2\t6.3.1 (2.11BSD GTE) 4/21/94\n.\\\"\n.TH CHDIR 2 \"April 21, 1994\"\n.UC 4\n.SH NAME\nchdir, fchdir \\- change current working directory\n.SH SYNOPSIS\n.nf\n.ft B\nchdir(path)\nchar *path;\n\nfchdir(fd)\nint fd;\n.ft R\n.fi\n.SH DESCRIPTION\nThe\n.B path\nargument points to the pathname of a directory.\nThe\n.B fd\nargument is a file descriptor which references a directory.\nThe\n.I chdir\nfunction causes this directory\nto become the current working directory,\nthe starting point for path names not beginning with ``/''.\n.PP\nThe\n.I fchdir\nfunction causes the directory referenced by \\fBfd\\fP to become\nthe current working directory, the starting point for path searches of\npathnames not beginning with a slahs, '/'.\n.PP\nIn order for a directory to become the current directory,\na process must have execute (search) access to the directory.\n.SH \"RETURN VALUE\nUpon successful completion, a value of 0 is returned.\nOtherwise, a value of \\-1 is returned and \\fIerrno\\fP is set to indicate\nthe error.\n.SH ERRORS\n.I Chdir\nwill fail and the current working directory will be unchanged if\none or more of the following are true:\n.TP 15\n[ENOTDIR]\nA component of the path prefix is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 63 characters,\nor an entire path name exceeded 255 characters.\n.TP 15\n[ENOENT]\nThe named directory does not exist.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[EACCES]\nSearch permission is denied for any component of\nthe path name.\n.TP 15\n[EFAULT]\n.I Path\npoints outside the process's allocated address space.\n.TP 15\n[EIO]\nAn I/O error occurred while reading from or writing to the file system.\n.PP\n.I Fchdir\nwill fail and the current working directory will be unchanged if\none or more of the following are true:\n.TP 15\n[EACCES]\nSearch permission is denied for the directory referenced by the\nfile descriptor.\n.TP 15\n[ENOTDIR]\nThe file descriptor \\fBfd\\fP does not reference a directory.\n.TP 15\n[EBADF]\nThe argument \\fBfd\\fP is not a valid file descriptor.\n.SH \"SEE ALSO\"\nchroot(2)\n"
  },
  {
    "path": "share/man/man2/chflags.2",
    "content": ".\\\" Copyright (c) 1989, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"\t@(#)chflags.2\t8.1.1 (2.11BSD GTE) 11/28/94\n.\\\"\n.TH CHFLAGS 2 \"November 28, 1994\"\n.UC 4\n.SH NAME\nchflags, fchflags \\- set file flags\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/stat.h>\n\nint\nchflags(path, flags)\nchar *path;\nu_short flags;\n\nint\nfchflags(fd, flags)\nint fd;\nu_short flags;\n.ft R\n.fi\n.SH DESCRIPTION\nThe file whose name\nis given by\n.B path\nor referenced by the descriptor\n.B fd\nhas its flags changed to\n.B flags .\n.PP\nThe flags specified are formed by\nor'ing\nthe following values\n.PP\n.TP 15\nUF_NODUMP\nDo not dump the file.\n.TP 15\nUF_IMMUTABLE\nThe file may not be changed.\n.TP 15\nUF_APPEND\nThe file may only be appended to.\n.TP 15\nARCHIVED\nFile is archived.\n.TP 15\nSF_IMMUTABLE\nThe file may not be changed.\n.TP 15\nSF_APPEND\nThe file may only be appended to.\n.PP\nThe\n.B UF_IMMUTABLE\nand\n.B UF_APPEND\nflags may be set or unset by either the owner of a file or the super-user.\n.PP\nThe\n.B SF_IMMUTABLE\nand\n.B SF_APPEND\nflags may only be set or unset by the super-user.\nThey may be set at any time, but normally may only be unset when\nthe system is in single-user mode.\n(See\n.I init(8)\nfor details.)\n.SH RETURN VALUES\nUpon successful completion, a value of 0 is returned.\nOtherwise, -1 is returned and the global variable\n.B errno\nis set to indicate the error.\n.SH ERRORS\nChflags\nwill fail if:\n.TP 15\nENOTDIR\nA component of the path prefix is not a directory.\n.TP 15\nEINVAL\nThe pathname contains a character with the high-order bit set.\n.TP 15\nENAMETOOLONG\nA component of a pathname exceeded 63 characters,\nor an entire path name exceeded 255 characters.\n.TP 15\nENOENT\nThe named file does not exist.\n.TP 15\nEACCES\nSearch permission is denied for a component of the path prefix.\n.TP 15\nELOOP\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\nEPERM\nThe effective user ID does not match the owner of the file and\nthe effective user ID is not the super-user.\n.TP 15\nEROFS\nThe named file resides on a read-only file system.\n.TP 15\nEFAULT\n.B path\npoints outside the process's allocated address space.\n.TP 15\nEIO\nAn I/O error occurred while reading from or writing to the file system.\n.PP\nfchflags\nwill fail if:\n.TP 15\nEBADF\nThe descriptor is not valid.\n.TP 15\nEINVAL\n.B fd\nrefers to a socket, not to a file.\n.TP 15\nEPERM\nThe effective user ID does not match the owner of the file and\nthe effective user ID is not the super-user.\n.TP 15\nEROFS\nThe file resides on a read-only file system.\n.TP 15\nEIO\nAn I/O error occurred while reading from or writing to the file system.\n.SH SEE ALSO\nchflags(1), init(8)\n.SH HISTORY\nThe\n.B chflags\nand\n.B fchflags\nfunctions first appeared in 4.4BSD.\n"
  },
  {
    "path": "share/man/man2/chmod.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)chmod.2\t6.5 (Berkeley) 5/13/86\n.\\\"\n.TH CHMOD 2 \"May 13, 1986\"\n.UC 4\n.SH NAME\nchmod \\- change mode of file\n.SH SYNOPSIS\n.nf\n.ft B\nchmod(path, mode)\nchar *path;\nint mode;\n.PP\n.ft B\nfchmod(fd, mode)\nint fd, mode;\n.fi\n.SH DESCRIPTION\nThe file whose name\nis given by \\fIpath\\fP\nor referenced by the descriptor\n.I fd\nhas its mode changed to\n.IR mode .\nModes are constructed by\n.IR or 'ing\ntogether some\ncombination of the following, defined in\n.IR <sys/inode.h> :\n.PP\n.RS\n.nf\n.ta \\w'IWRITE\\ \\ 'u +\\w'04000\\ \\ \\ 'u\nISUID\t04000\tset user ID on execution\nISGID\t02000\tset group ID on execution\nISVTX\t01000\t`sticky bit' (see below)\nIREAD\t00400\tread by owner\nIWRITE\t00200\twrite by owner\nIEXEC\t00100\texecute (search on directory) by owner\n\t00070\tread, write, execute (search) by group\n\t00007\tread, write, execute (search) by others\n.fi\n.RE\n.PP\nIf an executable file is set up for sharing (this is the default)\nthen mode ISVTX (the `sticky bit') prevents the system from\nabandoning the swap-space image of the program-text portion\nof the file when its last user terminates.\nAbility to set this bit on executable files is restricted to the super-user.\n.PP\nIf mode ISVTX (the `sticky bit') is set on a directory,\nan unprivileged user may not delete or rename\nfiles of other users in that directory.\nFor more details of the properties of the sticky bit, see\n.IR sticky (8).\n.PP\nOnly the owner of a file (or the super-user) may change the mode.\n.PP\nWriting or changing the owner of a file\nturns off the set-user-id and set-group-id bits\nunless the user is the super-user.\nThis makes the system somewhat more secure\nby protecting set-user-id (set-group-id) files\nfrom remaining set-user-id (set-group-id) if they are modified,\nat the expense of a degree of compatibility.\n.SH \"RETURN VALUE\nUpon successful completion, a value of 0 is returned.\nOtherwise, a value of \\-1 is returned and\n.I errno\nis set to indicate the error.\n.SH \"ERRORS\n.I Chmod\nwill fail and the file mode will be unchanged if:\n.TP 15\n[ENOTDIR]\nA component of the path prefix is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 255 characters,\nor an entire path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nThe named file does not exist.\n.TP 15\n[EACCES]\nSearch permission is denied for a component of the path prefix.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[EPERM]\nThe effective user ID does not match the owner of the file and\nthe effective user ID is not the super-user.\n.TP 15\n[EROFS]\nThe named file resides on a read-only file system.\n.TP 15\n[EFAULT]\n.I Path\npoints outside the process's allocated address space.\n.TP 15\n[EIO]\nAn I/O error occurred while reading from or writing to the file system.\n.PP\n.I Fchmod\nwill fail if:\n.TP 15\n[EBADF]\nThe descriptor is not valid.\n.TP 15\n[EINVAL]\n.I Fd\nrefers to a socket, not to a file.\n.TP 15\n[EROFS]\nThe file resides on a read-only file system.\n.TP 15\n[EIO]\nAn I/O error occurred while reading from or writing to the file system.\n.SH \"SEE ALSO\"\nchmod(1), open(2), chown(2), stat(2), sticky(8)\n"
  },
  {
    "path": "share/man/man2/chown.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)chown.2\t6.6 (Berkeley) 5/22/86\n.\\\"\n.TH CHOWN 2 \"May 22, 1986\"\n.UC 4\n.SH NAME\nchown \\- change owner and group of a file\n.SH SYNOPSIS\n.nf\n.ft B\nchown(path, owner, group)\nchar *path;\nint owner, group;\n.PP\n.ft B\nfchown(fd, owner, group)\nint fd, owner, group;\n.fi\n.SH DESCRIPTION\nThe file\nthat is named by \\fIpath\\fP or referenced by \\fIfd\\fP\nhas its\n.I owner\nand \n.I group\nchanged as specified.\nOnly the super-user\nmay change the owner of the file,\nbecause if users were able to give files away,\nthey could defeat the file-space accounting procedures.\nThe owner of the file may change the group\nto a group of which he is a member.\n.PP\nOn some systems,\n.I chown\nclears the set-user-id and set-group-id bits\non the file\nto prevent accidental creation of\nset-user-id and set-group-id programs.\n.PP\n.I Fchown\nis particularly useful when used in conjunction\nwith the file locking primitives (see\n.IR flock (2)).\n.PP\nOne of the owner or group id's\nmay be left unchanged by specifying it as \\-1.\n.PP\nIf the final component of\n.I path\nis a symbolic link,\nthe ownership and group of the symbolic link is changed,\nnot the ownership and group of the file or directory to which it points.\n.SH \"RETURN VALUE\nZero is returned if the operation was successful;\n\\-1 is returned if an error occurs, with a more specific\nerror code being placed in the global variable \\fIerrno\\fP.\n.SH \"ERRORS\n.I Chown\nwill fail and the file will be unchanged if:\n.TP 15\n[ENOTDIR]\nA component of the path prefix is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 255 characters,\nor an entire path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nThe named file does not exist.\n.TP 15\n[EACCES]\nSearch permission is denied for a component of the path prefix.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[EPERM]\nThe effective user ID is not the super-user.\n.TP 15\n[EROFS]\nThe named file resides on a read-only file system.\n.TP 15\n[EFAULT]\n.I Path\npoints outside the process's allocated address space.\n.TP 15\n[EIO]\nAn I/O error occurred while reading from or writing to the file system.\n.PP\n.I Fchown\nwill fail if:\n.TP 15\n[EBADF]\n.I Fd\ndoes not refer to a valid descriptor.\n.TP 15\n[EINVAL]\n.I Fd\nrefers to a socket, not a file.\n.TP 15\n[EPERM]\nThe effective user ID is not the super-user.\n.TP 15\n[EROFS]\nThe named file resides on a read-only file system.\n.TP 15\n[EIO]\nAn I/O error occurred while reading from or writing to the file system.\n.SH \"SEE ALSO\"\nchown(8), chgrp(1), chmod(2), flock(2)\n"
  },
  {
    "path": "share/man/man2/chroot.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)chroot.2\t6.3 (Berkeley) 8/26/85\n.\\\"\n.TH CHROOT 2 \"August 26, 1985\"\n.UC 5\n.SH NAME\nchroot \\- change root directory\n.SH SYNOPSIS\n.nf\n.ft B\nchroot(dirname)\nchar *dirname;\n.ft R\n.fi\n.SH DESCRIPTION\n.I Dirname\nis the address of the pathname of a directory, terminated by a null byte.\n.I Chroot\ncauses this directory\nto become the root directory,\nthe starting point for path names beginning with ``/''.\n.PP\nIn order for a directory to become the root directory\na process must have execute (search) access to the directory.\n.PP\nThis call is restricted to the super-user.\n.SH \"RETURN VALUE\nUpon successful completion, a value of 0 is returned.  Otherwise,\na value of \\-1 is returned and \\fIerrno\\fP is set to indicate an error.\n.SH ERRORS\n.I Chroot\nwill fail and the root directory will be unchanged if\none or more of the following are true:\n.TP 15\n[ENOTDIR]\nA component of the path name is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 255 characters,\nor an entire path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nThe named directory does not exist.\n.TP 15\n[EACCES]\nSearch permission is denied for any component of the path name.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[EFAULT]\n.I Path\npoints outside the process's allocated address space.\n.TP 15\n[EIO]\nAn I/O error occurred while reading from or writing to the file system.\n.SH \"SEE ALSO\"\nchdir(2)\n"
  },
  {
    "path": "share/man/man2/close.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)close.2\t6.3 (Berkeley) 5/22/86\n.\\\"\n.TH CLOSE 2 \"May 22, 1986\"\n.UC 4\n.SH NAME\nclose \\- delete a descriptor\n.SH SYNOPSIS\n.B close(d)\n.br\n.B \"int d;\"\n.SH DESCRIPTION\nThe\n\\fIclose\\fP call deletes a descriptor from the per-process object\nreference table.\nIf this is the last reference to the underlying object, then\nit will be deactivated.\nFor example, on the last close of a file\nthe current \\fIseek\\fP pointer associated with the file is lost;\non the last close of a\n.IR socket (2)\nassociated naming information and queued data are discarded;\non the last close of a file holding an advisory lock\nthe lock is released (see further\n.IR flock (2)\\fR).\n.PP\nA close of all of a process's descriptors is automatic on\n.IR exit ,\nbut since\nthere is a limit on the number of active descriptors per process,\n.I close\nis necessary for programs that deal with many descriptors.\n.PP\nWhen a process forks (see\n.IR fork (2)),\nall descriptors for the new child process reference the same\nobjects as they did in the parent before the fork.\nIf a new process is then to be run using\n.IR execve (2),\nthe process would normally inherit these descriptors.  Most\nof the descriptors can be rearranged with\n.IR dup2 (2)\nor deleted with\n.I close\nbefore the\n.I execve\nis attempted, but if some of these descriptors will still\nbe needed if the execve fails, it is necessary to arrange for them\nto be closed if the execve succeeds.\nFor this reason, the call ``fcntl(d, F_SETFD, 1)'' is provided,\nwhich arranges that a descriptor will be closed after a successful\nexecve; the call ``fcntl(d, F_SETFD, 0)'' restores the default,\nwhich is to not close the descriptor.\n.SH \"RETURN VALUE\nUpon successful completion, a value of 0 is returned.\nOtherwise, a value of \\-1 is returned and the global integer variable\n.I errno\nis set to indicate the error.\n.SH ERRORS\n.I Close\nwill fail if:\n.TP 15\n[EBADF]\n\\fID\\fP is not an active descriptor.\n.SH \"SEE ALSO\"\naccept(2), flock(2), open(2), pipe(2), socket(2), socketpair(2),\nexecve(2), fcntl(2)\n"
  },
  {
    "path": "share/man/man2/connect.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)connect.2\t6.6 (Berkeley) 5/22/86\n.\\\"\n.TH CONNECT 2 \"May 22, 1986\"\n.UC 5\n.SH NAME\nconnect \\- initiate a connection on a socket\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/types.h>\n#include <sys/socket.h>\n.PP\n.ft B\nconnect(s, name, namelen)\nint s;\nstruct sockaddr *name;\nint namelen;\n.fi\n.SH DESCRIPTION\nThe parameter\n.I s\nis a socket.\nIf it is of type SOCK_DGRAM,\nthen this call specifies the peer with which the socket is to be associated;\nthis address is that to which datagrams are to be sent,\nand the only address from which datagrams are to be received.\nIf the socket is of type SOCK_STREAM,\nthen this call attempts to make a connection to\nanother socket.\nThe other socket is specified by\n.I name,\nwhich is an address in the communications space of the socket.\nEach communications space interprets the\n.I name\nparameter in its own way.\nGenerally, stream sockets may successfully\n.I connect\nonly once; datagram sockets may use\n.I connect\nmultiple times to change their association.\nDatagram sockets may dissolve the association\nby connecting to an invalid address, such as a null address.\n.SH \"RETURN VALUE\nIf the connection or binding succeeds, then 0 is returned.\nOtherwise a \\-1 is returned, and a more specific error\ncode is stored in \\fIerrno\\fP.\n.SH \"ERRORS\nThe call fails if:\n.TP 20\n[EBADF]\n.I S\nis not a valid descriptor.\n.TP 20\n[ENOTSOCK]\n.I S\nis a descriptor for a file, not a socket.\n.TP 20\n[EADDRNOTAVAIL]\nThe specified address is not available on this machine.\n.TP 20\n[EAFNOSUPPORT]\nAddresses in the specified address family cannot be used with this socket.\n.TP 20\n[EISCONN]\nThe socket is already connected.\n.TP 20\n[ETIMEDOUT]\nConnection establishment timed out without establishing a connection.\n.TP 20\n[ECONNREFUSED]\nThe attempt to connect was forcefully rejected.\n.TP 20\n[ENETUNREACH]\nThe network isn't reachable from this host.\n.TP 20\n[EADDRINUSE]\nThe address is already in use.\n.TP 20\n[EFAULT]\nThe \\fIname\\fP parameter specifies an area outside\nthe process address space.\n.TP 20\n[EINPROGRESS]\nThe socket is non-blocking \nand the connection cannot\nbe completed immediately.\nIt is possible to\n.IR select (2)\nfor completion by selecting the socket for writing.\n.TP 20\n[EALREADY]\nThe socket is non-blocking\nand a previous connection attempt\nhas not yet been completed.\n.PP\nThe following errors are specific to connecting names in the UNIX domain.\nThese errors may not apply in future versions of the UNIX IPC domain.\n.TP 15\n[ENOTDIR]\nA component of the path prefix is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 255 characters,\nor an entire path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nThe named socket does not exist.\n.TP 15\n[EACCES]\nSearch permission is denied for a component of the path prefix.\n.TP 15\n[EACCES]\nWrite access to the named socket is denied.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.SH SEE ALSO\naccept(2), select(2), socket(2), getsockname(2)\n"
  },
  {
    "path": "share/man/man2/creat.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)creat.2\t6.6 (Berkeley) 5/22/86\n.\\\"\n.TH CREAT 2 \"May 22, 1986\"\n.UC 4\n.SH NAME\ncreat \\- create a new file\n.SH SYNOPSIS\n.nf\n.B creat(name, mode)\n.B char *name;\n.fi\n.SH DESCRIPTION\n.B \"This interface is made obsolete by open(2).\n.PP\n.I Creat\ncreates a new file or prepares to rewrite an existing\nfile called \n.IR name ,\ngiven as the address of a null-terminated string.\nIf the file did not exist, it is given\nmode\n.IR mode ,\nas modified by the process's mode mask (see\n.IR umask (2)).\nAlso see\n.IR  chmod (2)\nfor the\nconstruction of the\n.I mode\nargument.\n.PP\nIf the file did exist, its mode and owner remain unchanged\nbut it is truncated to 0 length.\n.PP\nThe file is also opened for writing, and its file descriptor\nis returned.\n.SH NOTES\nThe\n.I mode\ngiven is arbitrary; it need not allow\nwriting.\nThis feature has been used in the past by\nprograms to construct a simple, exclusive locking\nmechanism.  It is replaced by the O_EXCL open\nmode, or \n.IR flock (2)\nfacility.  \n.SH \"RETURN VALUE\nThe value \\-1 is returned if an error occurs.  Otherwise,\nthe call returns a non-negative descriptor that only permits\nwriting.\n.SH ERRORS\n.I Creat\nwill fail and the file will not be created or truncated\nif one of the following occur:\n.TP 15\n[ENOTDIR]\nA component of the path prefix is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 255 characters,\nor an entire path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nThe named file does not exist.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[EACCES]\nSearch permission is denied for a component of the path prefix.\n.TP 15\n[EACCES]\nThe file does not exist and the directory\nin which it is to be created is not writable.\n.TP 15\n[EACCES]\nThe file exists, but it is unwritable.\n.TP 15\n[EISDIR]\nThe file is a directory.\n.TP 15\n[EMFILE]\nThere are already too many files open.\n.TP 15\n[ENFILE]\nThe system file table is full.\n.TP 15\n[ENOSPC]\nThe directory in which the entry for the new file is being placed\ncannot be extended because there is no space left on the file\nsystem containing the directory.\n.TP 15\n[ENOSPC]\nThere are no free inodes on the file system on which the\nfile is being created.\n.TP 15\n[EDQUOT]\nThe directory in which the entry for the new file\nis being placed cannot be extended because the\nuser's quota of disk blocks on the file system\ncontaining the directory has been exhausted.\n.TP 15\n[EDQUOT]\nThe user's quota of inodes on the file system on\nwhich the file is being created has been exhausted.\n.TP 15\n[EROFS]\nThe named file resides on a read-only file system.\n.TP 15\n[ENXIO]\nThe file is a character special or block special file, and\nthe associated device does not exist.\n.TP 15\n[ETXTBSY]\nThe file is a pure procedure (shared text) file that is being\nexecuted.\n.TP 15\n[EIO]\nAn I/O error occurred while making the directory entry or allocating the inode.\n.TP 15\n[EFAULT]\n.I Name\npoints outside the process's allocated address space.\n.TP 15\n[EOPNOTSUPP]\nThe file was a socket (not currently implemented).\n.SH \"SEE ALSO\"\nopen(2), write(2), close(2), chmod(2), umask(2)\n"
  },
  {
    "path": "share/man/man2/dup.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)dup.2\t6.3 (Berkeley) 5/13/86\n.\\\"\n.TH DUP 2 \"May 13, 1986\"\n.UC 4\n.SH NAME\ndup, dup2 \\- duplicate a descriptor\n.SH SYNOPSIS\n.nf\n.ft B\nnewd = dup(oldd)\nint newd, oldd;\n.PP\n.ft B\ndup2(oldd, newd)\nint oldd, newd;\n.fi\n.SH DESCRIPTION\n.I Dup\nduplicates an existing object descriptor.\nThe argument \\fIoldd\\fP is a small non-negative integer index in\nthe per-process descriptor table.  The value must be less\nthan the size of the table, which is returned by\n.IR getdtablesize (2).\nThe new descriptor returned by the call,\n.I newd,\nis the lowest numbered descriptor that is\nnot currently in use by the process.\n.PP\nThe object referenced by the descriptor does not distinguish\nbetween references using \\fIoldd\\fP and \\fInewd\\fP in any way.\nThus if \\fInewd\\fP and \\fIoldd\\fP are duplicate references to an open\nfile,\n.IR read (2),\n.IR write (2)\nand\n.IR lseek (2)\ncalls all move a single pointer into the file,\nand append mode, non-blocking I/O and asynchronous I/O options\nare shared between the references.\nIf a separate pointer into the file is desired, a different\nobject reference to the file must be obtained by issuing an\nadditional\n.IR open (2)\ncall.\nThe close-on-exec flag on the new file descriptor is unset.\n.PP\nIn the second form of the call, the value of\n.IR newd\ndesired is specified.  If this descriptor is already\nin use, the descriptor is first deallocated as if a\n.IR close (2)\ncall had been done first.\n.SH \"RETURN VALUE\nThe value \\-1 is returned if an error occurs in either call.\nThe external variable\n.I errno\nindicates the cause of the error.\n.SH \"ERRORS\n.I Dup\nand\n.I dup2\nfail if:\n.TP 15\n[EBADF]\n\\fIOldd\\fP or\n\\fInewd\\fP is not a valid active descriptor\n.TP 15\n[EMFILE]\nToo many descriptors are active.\n.SH \"SEE ALSO\"\naccept(2),\nopen(2),\nclose(2),\nfcntl(2),\npipe(2),\nsocket(2),\nsocketpair(2),\ngetdtablesize(2)\n"
  },
  {
    "path": "share/man/man2/execve.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)execve.2\t6.7 (Berkeley) 5/22/86\n.\\\"\n.TH EXECVE 2 \"May 22, 1986\"\n.UC 4\n.SH NAME\nexecve \\- execute a file\n.SH SYNOPSIS\n.ft B\nexecve(name, argv, envp)\n.br\nchar *name, *argv[], *envp[];\n.fi\n.SH DESCRIPTION\n.I Execve\ntransforms the calling process into a new process.\nThe new process is constructed from an ordinary file\ncalled the \\fInew process file\\fP.\nThis file is either an executable object file,\nor a file of data for an interpreter.\nAn executable object file consists of an identifying header,\nfollowed by pages of data representing the initial program (text)\nand initialized data pages.  Additional pages may be specified\nby the header to be initialized with zero data.  See\n.IR a.out (5).\n.PP\nAn interpreter file begins with a line of the form ``#! \\fIinterpreter\\fP''.\nWhen an interpreter file is\n.IR execve\\| 'd,\nthe system \\fIexecve\\fP\\|'s the specified \\fIinterpreter\\fP, giving\nit the name of the originally exec'd file as an argument and\nshifting over the rest of the original arguments.\n.PP\nThere can be no return from a successful \\fIexecve\\fP because the calling\ncore image is lost.\nThis is the mechanism whereby different process images become active.\n.PP\nThe argument \\fIargv\\fP is a null-terminated array of character pointers\nto null-terminated character strings.  These strings constitute\nthe argument list to be made available to the new\nprocess.  By convention, at least one argument must be present in\nthis array, and the first element of this array should be\nthe name of the executed program (i.e., the last component of \\fIname\\fP).\n.PP\nThe argument \\fIenvp\\fP is also a null-terminated array of character pointers\nto null-terminated strings.  These strings pass information to the\nnew process that is not directly an argument to the command (see\n.IR environ (7)).\n.PP\nDescriptors open in the calling process remain open in\nthe new process, except for those for which the close-on-exec\nflag is set (see\n.IR close (2)).\nDescriptors that remain open are unaffected by\n.IR execve .\n.PP\nIgnored signals remain ignored across an\n.IR execve ,\nbut signals that are caught are reset to their default values.\nBlocked signals remain blocked regardless of changes to the signal action.\nThe signal stack is reset to be undefined (see\n.IR sigvec (2) \nfor more information).\n.PP\nEach process has\n.I real\nuser and group IDs and an\n.I effective\nuser and group IDs.  The\n.I real\nID identifies the person using the system; the\n.I effective\nID determines his access privileges.\n.I Execve\nchanges the effective user and group ID to\nthe owner of the executed file if the file has the \\*(lqset-user-ID\\*(rq\nor \\*(lqset-group-ID\\*(rq modes.  The\n.I real\nuser ID is not affected.\n.PP\nThe new process also inherits the following attributes from\nthe calling process:\n.PP\n.in +5n\n.nf\n.ta +2i\nprocess ID\tsee \\fIgetpid\\fP\\|(2)\nparent process ID\tsee \\fIgetppid\\fP\\|(2)\nprocess group ID\tsee \\fIgetpgrp\\fP\\|(2)\naccess groups\tsee \\fIgetgroups\\fP\\|(2)\nworking directory\tsee \\fIchdir\\fP\\|(2)\nroot directory\tsee \\fIchroot\\fP\\|(2)\ncontrol terminal\tsee \\fItty\\fP\\|(4)\nresource usages\tsee \\fIgetrusage\\fP\\|(2)\ninterval timers\tsee \\fIgetitimer\\fP\\|(2)\nresource limits\tsee \\fIgetrlimit\\fP\\|(2)\nfile mode mask\tsee \\fIumask\\fP\\|(2)\nsignal mask\tsee \\fIsigvec\\fP\\|(2), \\fIsigmask\\fP\\|(2)\n.in -5n\n.fi\n.PP\nWhen the executed program begins, it is called as follows:\n.PP\n.DT\n.nf\n\tmain(argc, argv, envp)\n\tint argc;\n\tchar **argv, **envp;\n.fi\n.PP\nwhere\n.I argc\nis the number of elements in \\fIargv\\fP\n(the ``arg count'')\nand\n.I argv\nis the array of character pointers\nto the arguments themselves.\n.PP\n.I Envp\nis a pointer to an array of strings that constitute\nthe\n.I environment\nof the process.\nA pointer to this array is also stored in the global variable ``environ''.\nEach string consists of a name, an \\*(lq=\\*(rq, and a null-terminated value.\nThe array of pointers is terminated by a null pointer.\nThe shell\n.IR sh (1)\npasses an environment entry for each global shell variable\ndefined when the program is called.\nSee\n.IR environ (7)\nfor some conventionally\nused names.\n.SH \"RETURN VALUE\nIf\n.I execve\nreturns to the calling process an error has occurred; the\nreturn value will be \\-1 and the global variable\n.I errno\nwill contain an error code.\n.SH ERRORS\n.I Execve\nwill fail and return to the calling process if one or more\nof the following are true:\n.TP 15\n[ENOTDIR]\nA component of the path prefix is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 255 characters,\nor an entire path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nThe new process file does not exist.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[EACCES]\nSearch permission is denied for a component of the path prefix.\n.TP 15\n[EACCES]\nThe new process file is not an ordinary file.\n.TP 15\n[EACCES]\nThe new process file mode denies execute permission.\n.TP 15\n[ENOEXEC]\nThe new process file has the appropriate access\npermission, but has an invalid magic number in its header.\n.TP 15\n[ETXTBSY]\nThe new process file is a pure procedure (shared text)\nfile that is currently open for writing or reading by some process.\n.TP 15\n[ENOMEM]\nThe new process requires more virtual memory than\nis allowed by the imposed maximum\n.RI ( getrlimit (2)).\n.TP 15\n[E2BIG]\nThe number of bytes in the new process's argument list\nis larger than the system-imposed limit.\nThe limit in the system as released is 20480 bytes\n(NCARGS in\n.IR <sys/param.h> .\n.TP 15\n[EFAULT]\nThe new process file is not as long as indicated by\nthe size values in its header.\n.TP 15\n[EFAULT]\n\\fIPath\\fP\\|, \\fIargv\\fP\\|, or \\fIenvp\\fP point\nto an illegal address.\n.TP 15\n[EIO]\nAn I/O error occurred while reading from the file system.\n.SH CAVEATS\nIf a program is\n.I setuid\nto a non-super-user, but is executed when\nthe real \\fIuid\\fP is ``root'', then the program has some of the powers\nof a super-user as well.\n.SH \"SEE ALSO\"\nexit(2), fork(2), execl(3), environ(7)\n"
  },
  {
    "path": "share/man/man2/exit.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)exit.2\t6.4 (Berkeley) 5/22/86\n.\\\"\n.TH EXIT 2 \"May 22, 1986\"\n.UC 4\n.SH NAME\n_exit \\- terminate a process\n.SH SYNOPSIS\n.nf\n.ft B\n_exit(status)\nint status;\n.fi\n.SH DESCRIPTION\n.I _exit\nterminates a process with the following consequences:\n.in +5n\n.PP\nAll of the descriptors open in the calling process are closed.\nThis may entail delays, for example, waiting for output to drain;\na process in this state may not be killed, as it is already dying.\n.PP\nIf the parent process of the calling process is executing a\n.I wait\nor is interested in the SIGCHLD signal,\nthen it is notified of the calling process's termination and\nthe low-order eight bits of \\fIstatus\\fP are made available to it;\nsee\n.IR wait (2).\n.PP\nThe parent process ID of all of the calling process's existing child\nprocesses are also set to 1.  This means that the initialization process\n(see \n.IR intro (2))\ninherits each of these processes as well.\nAny stopped children are restarted with a hangup signal (SIGHUP).\n.in -5n\n.PP\nMost C programs call the library routine\n.IR exit (3),\nwhich performs cleanup actions in the standard I/O library before\ncalling \\fI_exit\\fP\\|.\n.SH \"RETURN VALUE\"\nThis call never returns.\n.SH \"SEE ALSO\"\nfork(2), sigvec(2), wait(2), exit(3)\n"
  },
  {
    "path": "share/man/man2/fcntl.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)fcntl.2\t6.4.1 (2.11BSD GTE) 11/30/94\n.\\\"\n.TH FCNTL 2 \"Nov 30, 1994\"\n.UC 5\n.SH NAME\nfcntl \\- file control\n.SH SYNOPSIS\n.nf\n.ft B\n#include <fcntl.h>\n.PP\n.ft B\nres = fcntl(fd, cmd, arg)\nint res;\nint fd, cmd, arg;\n.ft R\n.SH DESCRIPTION\n.I Fcntl\nprovides for control over descriptors.\nThe argument\n.I fd\nis a descriptor to be operated on by\n.I cmd\nas follows:\n.TP 15\nF_DUPFD\nReturn a new descriptor as follows:\n.IP\nLowest numbered available descriptor greater than or equal to\n.I arg.\n.IP\nSame object references as the original descriptor.\n.IP\nNew descriptor shares the same file pointer if the object\nwas a file.\n.IP\nSame access mode (read, write or read/write).\n.IP\nSame file status flags (i.e., both file descriptors\nshare the same file status flags).\n.IP\nThe close-on-exec flag associated with the new file descriptor\nis set to remain open across\n.IR execv (2)\nsystem calls.\n.TP 15\nF_GETFD\nGet the close-on-exec flag associated with the file descriptor\n.IR fd .\nIf the low-order bit is 0, the file will remain open across\n.IR exec ,\notherwise the file will be closed upon execution of\n.I exec.\n.TP 15\nF_SETFD\nSet the close-on-exec flag associated with\n.I fd\nto the low order bit of\n.I arg\n(0 or 1 as above).\n.TP 15\nF_GETFL\nGet descriptor status flags, as described below.\n.TP 15\nF_SETFL\nSet descriptor status flags.\n.TP 15\nF_GETOWN\nGet the process ID or process group\ncurrently receiving SIGIO and SIGURG\nsignals; process groups are returned\nas negative values.\n.TP\nF_SETOWN\nSet the process or process group\nto receive SIGIO and SIGURG signals;\nprocess groups are specified by supplying\n.I arg\nas negative, otherwise \n.I arg\nis interpreted as a process ID.\n.LP\nThe flags for the F_GETFL and F_SETFL flags are as follows:\n.TP 15\nO_NONBLOCK\nNon-blocking I/O; if no data is available to a\n.I read\ncall, or if a write operation would block,\nthe call returns -1 with the error EWOULDBLOCK.\n.TP\nO_APPEND\nForce each write to append at the end of file;\ncorresponds to the O_APPEND flag of\n.IR open (2).\n.TP\nO_ASYNC\nEnable the SIGIO signal to be sent to the process group\nwhen I/O is possible, e.g.,\nupon availability of data to be read.\n.SH \"RETURN VALUE\nUpon successful completion, the value returned depends on\n.I cmd\nas follows:\n.sp .5v\n.nf\n.ta .25i 1.25i\n\tF_DUPFD\tA new file descriptor.\n\tF_GETFD\tValue of flag (only the low-order bit is defined).\n\tF_GETFL\tValue of flags.\n\tF_GETOWN\tValue of file descriptor owner.\n\tother\tValue other than \\-1.\n.fi\n.sp .5v\nOtherwise, a value of \\-1 is returned and\n.I errno\nis set to indicate the error.\n.SH ERRORS\n.I Fcntl\nwill fail if one or more of the following are true:\n.TP 15\n[EBADF]\n.I Fildes\nis not a valid open file descriptor.\n.TP 15\n[EMFILE]\n.I Cmd\nis F_DUPFD and the maximum allowed number of file descriptors are currently\nopen.\n.TP 15\n[EINVAL]\n.I Cmd\nis F_DUPFD and\n.I arg\nis negative or greater than the maximum allowable number\n(see\n.IR getdtablesize (2)).\n.TP 15\n[ESRCH]\n.I Cmd\nis F_SETOWN and\nthe process ID given as argument is not in use.\n.SH \"SEE ALSO\nclose(2), execve(2), getdtablesize(2), open(2), sigvec(2)\n.SH BUGS\nThe asynchronous I/O facilities of O_NONBLOCK and O_ASYNC\nare currently available only for tty and socket operations.\n"
  },
  {
    "path": "share/man/man2/fetchi.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)fetchi.2\t2.3 (Berkeley) 1/22/87\n.\\\"\n.TH FETCHI 2 \"January 22, 1987\"\n.UC 2\n.SH NAME\nfetchi \\- fetch from user instruction space (2BSD)\n.SH SYNOPSIS\n.nf\n.ft B\nfetchi(addr)\nint *addr;\n.fi\n.ft R\n.SH DESCRIPTION\n.I Fetchi\nfetches the word at\n.I addr\nfrom the caller's instruction space.\nThis system call is required\non PDP-11's with separate instruction\nand data spaces because the\n.I mfpi\ninstruction reads from\nD-space if the current\nand previous modes in the\nprogram status word are\nboth user.\n.SH \"RETURN VALUE\nUpon successful completion the contents of the caller's instruction space at\n.I addr\nare returned.  Otherwise, a value of \\-1 is returned.\n.SH \"ERRORS\n.TP 15\n[EINVAL]\nThe kernel has not been compiled for a processor with separate I/D.\n.TP 15\n[EFAULT]\n.I Addr\npoints to an address not in the process's allocated instruction space.\n.SH BUGS\nThe error indication, \\-1, is a legitimate function value;\n.I errno,\n(see\n.IR intro (2)),\ncan be used to disambiguate.\n.PP\n.I Fetchi\nis a kludge and exists only to circumvent an alleged\nsecurity feature on some DEC PDP-11 processors.\n.PP\n.I Fetchi\nis unique to the PDP-11 and 2BSD; its use is discouraged.\n"
  },
  {
    "path": "share/man/man2/flock.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)flock.2\t6.4 (Berkeley) 5/22/86\n.\\\"\n.TH FLOCK 2 \"May 22, 1986\"\n.UC 5\n.SH NAME\nflock \\- apply or remove an advisory lock on an open file\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/file.h>\n.PP\n.ft B\n.DT\n#define\tLOCK_SH\t1\t/* shared lock */\n#define\tLOCK_EX\t2\t/* exclusive lock */\n#define\tLOCK_NB\t4\t/* don't block when locking */\n#define\tLOCK_UN\t8\t/* unlock */\n.PP\n.ft B\nflock(fd, operation)\nint fd, operation;\n.fi\n.SH DESCRIPTION\n.I Flock\napplies or removes an\n.I advisory\nlock on the file associated with the file descriptor\n.IR fd .\nA lock is applied by specifying an\n.I operation\nparameter that is the inclusive or of\nLOCK_SH or LOCK_EX and, possibly, LOCK_NB.  To unlock\nan existing lock\n.I operation\nshould be LOCK_UN.\n.PP\nAdvisory locks allow cooperating processes to perform\nconsistent operations on files, but do not guarantee\nconsistency (i.e., processes may still access files\nwithout using advisory locks possibly resulting in\ninconsistencies).\n.PP\nThe locking mechanism allows two types of locks:\n.I shared\nlocks and\n.I exclusive\nlocks.\nAt any time multiple shared locks may be applied to a file,\nbut at no time are multiple exclusive, or both shared and exclusive,\nlocks allowed simultaneously on a file.  \n.PP\nA shared lock may be\n.I upgraded\nto an exclusive lock, and vice versa, simply by specifying\nthe appropriate lock type; this results in the previous\nlock being released and the new lock applied (possibly\nafter other processes have gained and released the lock).\n.PP\nRequesting a lock on an object that is already locked\nnormally causes the caller to be blocked until the lock may be\nacquired.  If LOCK_NB is included in\n.IR operation ,\nthen this will not happen; instead the call will fail and\nthe error EWOULDBLOCK will be returned.\n.SH NOTES\nLocks are on files, not file descriptors.  That is, file descriptors\nduplicated through\n.IR dup (2)\nor\n.IR fork (2)\ndo not result in multiple instances of a lock, but rather multiple\nreferences to a single lock.  If a process holding a lock on a file\nforks and the child explicitly unlocks the file, the parent will\nlose its lock.\n.PP\nProcesses blocked awaiting a lock may be awakened by signals.\n.SH \"RETURN VALUE\nZero is returned if the operation was successful;\non an error a \\-1 is returned and an error code is left in\nthe global location \\fIerrno\\fP.\n.SH \"ERRORS\nThe \\fIflock\\fP call fails if:\n.TP 20\n[EWOULDBLOCK]\nThe file is locked and the LOCK_NB option was specified.\n.TP 20\n[EBADF]\nThe argument \\fIfd\\fP is an invalid descriptor.\n.TP 20\n[EINVAL]\nThe argument \\fIfd\\fP refers to an object other than a file.\n.SH \"SEE ALSO\"\nopen(2), close(2), dup(2), execve(2), fork(2)\n"
  },
  {
    "path": "share/man/man2/fork.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)fork.2\t6.4 (Berkeley) 5/22/86\n.\\\"\n.TH FORK 2 \"May 22, 1986\"\n.UC\n.SH NAME\nfork \\- create a new process\n.SH SYNOPSIS\n.ft B\npid = fork()\n.br\nint pid;\n.ft R\n.SH DESCRIPTION\n.I Fork\ncauses creation of a new process.\nThe new process (child process) is an exact copy of the\ncalling process except for the following:\n.in +5n\n.sp\nThe child process has a unique process ID.\n.sp\nThe child process has a different parent process ID (i.e.,\nthe process ID of the parent process).\n.sp\nThe child process has its own copy of the parent's descriptors.\nThese descriptors reference the same underlying objects, so that,\nfor instance, file pointers in file objects are shared between\nthe child and the parent, so that an\n.IR lseek (2)\non a descriptor in the child process can affect a subsequent\n.I read\nor\n.I write\nby the parent.\nThis descriptor copying is also used by the shell to\nestablish standard input and output for newly created processes\nas well as to set up pipes.\n.sp\nThe child processes resource utilizations are set to 0;\nsee\n.IR setrlimit (2).\n.SH \"RETURN VALUE\nUpon successful completion, \\fIfork\\fP returns a value\nof 0 to the child process and returns the process ID of the child\nprocess to the parent process.  Otherwise, a value of \\-1 is returned\nto the parent process, no child process is created, and the global\nvariable \\fIerrno\\fP is set to indicate the error.\n.SH ERRORS\n.I Fork\nwill fail and no child process will be created if one or more of the\nfollowing are true:\n.TP 15\n[EAGAIN]\nThe system-imposed limit on the total\nnumber of processes under execution would be exceeded.\nThis limit is configuration-dependent.\n.TP 15\n[EAGAIN]\nThe system-imposed limit MAXUPRC (\\fI<sys/param.h>) \\fRon the total number of\nprocesses under execution by a single user would be exceeded.\n.TP 15\n[ENOMEM]\nThere is insufficient swap space for the new process.\n.SH \"SEE ALSO\"\nexecve(2), wait(2)\n"
  },
  {
    "path": "share/man/man2/fperr.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)fperr.2\t2.3 (Berkeley) 1/22/87\n.\\\"\n.TH FPERR 2 \"January 22, 1987\"\n.UC 2\n.SH NAME\nfperr \\- get floating-point error registers (2BSD)\n.SH SYNOPSIS\n.nf\n.ft B\n#include <pdp/fperr.h>\n\nstruct fperr\n{\n\tshort\tf_fec;\n\tcaddr_t\tf_fea;\n};\n\nfperr(fpe)\nstruct fperr *fpe;\n.fi\n.ft R\n.SH DESCRIPTION\n.I Fperr\nreturns the contents of the\nfloating-point processor's\nerror registers as they were\nfollowing the last floating exception\ngenerated by the calling process.\nThe registers are stored in the\nstructure pointed to by\n.IR fpe .\n.PP\nThis call is required because the\nerror registers in the PDP-11 floating-point processor\nare read-only.\nThus, they may be changed by some other\nprocess between the time that\nthe current process generates an exception and the\ntime that it reads the registers.\nTherefore, the system saves their state\nat the time of an exception.\n.PP\nThe values returned are\nvalid only after a floating-point\nexception.\n.SH ERRORS\n.TP 15\n[EINVAL]\nThe kernel has not been compiled for a processor with floating point.\n.SH \"SEE ALSO\nEd Gould, Jim Reeds, Vance Vaughan,\n.I UNIX Problems with Floating Point Processors\n.SH BUGS\n.I Fperr\nis unique to the PDP-11 and 2BSD; its use is discouraged.\n"
  },
  {
    "path": "share/man/man2/fsync.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)fsync.2\t6.4 (Berkeley) 5/22/86\n.\\\"\n.TH FSYNC 2 \"May 22, 1986\"\n.UC 5\n.SH NAME\nfsync \\- synchronize a file's in-core state with that on disk\n.SH SYNOPSIS\n.ft B\nfsync(fd)\n.br\nint fd;\n.ft R\n.SH DESCRIPTION\n.I Fsync\ncauses all modified data and attributes of \\fIfd\\fP\nto be moved to a permanent storage device.\nThis normally results in all in-core modified copies\nof buffers for the associated file to be written to a disk.\n.PP\n.I Fsync\nshould be used by programs that require a file to be\nin a known state, for example, in building a simple transaction\nfacility.\n.SH \"RETURN VALUE\nA 0 value is returned on success.  A \\-1 value indicates\nan error.\n.SH \"ERRORS\nThe \\fIfsync\\fP fails if:\n.TP 15\n[EBADF]\n\\fIFd\\fP is not a valid descriptor.\n.TP 15\n[EINVAL]\n\\fIFd\\fP refers to a socket, not to a file.\n.TP 15\n[EIO]\nAn I/O error occurred while reading from or writing to the file system.\n.SH \"SEE ALSO\"\nsync(2), sync(8), update(8)\n"
  },
  {
    "path": "share/man/man2/getdtablesize.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)getdtablesize.2\t6.2 (Berkeley) 6/28/85\n.\\\"\n.TH GETDTABLESIZE 2 \"June 28, 1985\"\n.UC 5\n.SH NAME\ngetdtablesize \\- get descriptor table size\n.SH SYNOPSIS\n.nf\n.ft B\nnfds = getdtablesize()\nint nfds;\n.fi\n.SH DESCRIPTION\nEach process has a fixed size descriptor table,\nwhich is guaranteed to have at least 20 slots.  The entries in\nthe descriptor table are numbered with small integers starting at 0.\nThe call\n.I getdtablesize\nreturns the size of this table.\n.SH \"SEE ALSO\"\nclose(2), dup(2), open(2), select(2)\n"
  },
  {
    "path": "share/man/man2/getfsstat.2",
    "content": ".\\\" Copyright (c) 1989, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"\t@(#)getfsstat.2\t8.1.1 (2.11BSD) 1995/12/24\n.\\\"\n.TH GETFSSTAT 2 \"December 24, 1995\"\n.UC 7\n.SH NAME\n\\fBgetfsstat\\fP \\- get list of all mounted filesystems\n.SH SYNOPSIS\n.B #include <sys/param.h>\n.br\n.B #include <sys/mount.h>\n.sp\n.I int\n.br\n\\fBgetfsstat\\fP(buf,bufsize,flags)\n.br\n.I struct statfs *buf;\n.br\n.I int bufsize;\n.br\n.I int flags;\n.br\n.SH DESCRIPTION\n.BR Getfsstat ()\nreturns information about all mounted filesystems.\n.I Buf\nis a pointer to\n.I statfs\nstructures defined as follows:\n.sp\n.nf\n.cs R 20\n\n#define MNAMELEN 90       /* length of buffer for returned name */\n\nstruct statfs {\nshort   f_type;           /* type of filesystem (see below) */\nshort   f_flags;          /* copy of mount flags */\nshort   f_bsize;          /* fundamental file system block size */\nshort   f_iosize;         /* optimal transfer block size */\nlong    f_blocks;         /* total data blocks in file system */\nlong    f_bfree;          /* free blocks in fs */\nlong    f_bavail;         /* free blocks avail to non-superuser */\nino_t   f_files;          /* total file nodes in file system */\nino_t   f_ffree;          /* free file nodes in fs */\nu_long  f_fsid[2];        /* file system id */\nlong    f_spare[4];       /* spare for later */\nchar    f_mntonname[MNAMELEN];    /* mount point */\nchar    f_mntfromname[MNAMELEN];  /* mounted filesystem */\n};\n/*\n* File system types. - Only UFS is supported so the other types are not\n* given.\n*/\n#define\tMOUNT_NONE\t0\n#define\tMOUNT_UFS\t1\t/* Fast Filesystem */\n.br\n.fi\n.cs R\n.PP\nFields that are undefined for a particular filesystem are set to -1.\nThe buffer is filled with an array of\n.I fsstat\nstructures, one for each mounted filesystem\nup to the size specified by\n.IR bufsize .\n.PP\nIf\n.I buf\nis given as NULL,\n.BR getfsstat ()\nreturns just the number of mounted filesystems.\n.PP\nNormally\n.I flags\nis currently unused.  In 4.4BSD systems the usage is\nspecified as\nMNT_WAIT.\nIf\n.I flags\nis set to\nMNT_NOWAIT,\n.BR getfsstat ()\nwill return the information it has available without requesting\nan update from each filesystem.\nThus, some of the information will be out of date, but\n.BR getfsstat ()\nwill not block waiting for information from a filesystem that is\nunable to respond.\n.SH RETURN VALUES\nUpon successful completion, the number of \n.I fsstat\nstructures is returned.\nOtherwise, -1 is returned and the global variable\n.I errno\nis set to indicate the error.\n.SH ERRORS\n.BR Getfsstat ()\nfails if one or more of the following are true:\n.sp\n.TP 20\n[EFAULT]\n.I Buf\npoints to an invalid address.\n.TP 20\n[EIO]\nAn I/O\nerror occurred while reading from or writing to the filesystem.\n.SH SEE ALSO\nstatfs(2), fstab(5), mount(8)\n.SH HISTORY\nThe\n.B getfsstat\nfunction first appeared in 4.4BSD.\n"
  },
  {
    "path": "share/man/man2/getgid.2",
    "content": ".\\\" Copyright (c) 1983, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)getgid.2\t8.1.1 (2.11BSD) 1997/12/2\n.\\\"\n.TH GETGID 2 \"December 2, 1997\"\n.UC 5\n.SH NAME\n\\fBgetgid\\fP, \\fBgetegid\\fP \\- get group process identification\n.SH SYNOPSIS\n.B #include <sys/types.h>\n.sp\n.nf\n\\fIgid_t\\fP\n\\fBgetgid\\fP()\n.sp\n\\fIgid_t\\fP\n\\fBgetegid\\fP()\n.fi\n.SH DESCRIPTION\nThe\n.B getgid\nfunction returns the real group ID of the calling process,\n.B getegid\nreturns the effective group ID of the calling process.\n.PP\nThe real group ID is specified at login time.\n.PP\nThe real group ID is the group of the user who invoked the program.\nAs the effective group ID gives the process additional permissions\nduring the execution of\n``\\fIset-group-ID\\fP''\nmode processes,\n.B getgid\nis used to determine the real-user-id of the calling process.\n.SH ERRORS\nThe\n.B getgid\nand\n.B getegid\nfunctions are always successful, and no return value is reserved to\nindicate an error.\n.SH SEE ALSO\ngetuid(2), setregid(2), setgid(3)\n.SH STANDARDS\n.B Getgid\nand\n.B getegid\nconform to IEEE Std 1003.1-1988 (``POSIX'').\n"
  },
  {
    "path": "share/man/man2/getgroups.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)getgroups.2\t6.3 (Berkeley) 5/13/86\n.\\\"\n.TH GETGROUPS 2 \"May 13, 1986\"\n.UC 5\n.SH NAME\ngetgroups \\- get group access list\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/param.h>\n.PP\n.ft B\nngroups = getgroups(gidsetlen, gidset)\nint ngroups, gidsetlen, *gidset;\n.fi\n.SH DESCRIPTION\n.I Getgroups\ngets the current group access list of the user process\nand stores it in the array \n.IR gidset .\nThe parameter\n.I gidsetlen\nindicates the number of entries that may be placed in \n.IR gidset.\n.I Getgroups\nreturns the actual number of groups returned in\n.IR gidset .\nNo more than NGROUPS, as defined in\n.RI < sys/param.h >,\nwill ever\nbe returned.\n.SH \"RETURN VALUE\nA successful call returns the number of groups in the group set.\nA value of \\-1 indicates that an error occurred, and the error\ncode is stored in the global variable \\fIerrno\\fP\\|.\n.SH \"ERRORS\nThe possible errors for \\fIgetgroup\\fP are:\n.TP 15\n[EINVAL]\nThe argument\n.I gidsetlen\nis smaller than the number of groups in the group set.\n.TP\n[EFAULT]\nThe argument \\fIgidset\\fP specifies\nan invalid address.\n.SH \"SEE ALSO\nsetgroups(2), initgroups(3X)\n.SH BUGS\nThe\n.I gidset\narray should be of type\n.BR gid_t ,\nbut remains integer for compatibility with earlier systems.\n"
  },
  {
    "path": "share/man/man2/gethostid.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)gethostid.2\t6.3 (Berkeley) 11/28/85\n.\\\"\n.TH GETHOSTID 2 \"November 28, 1985\"\n.UC 5\n.SH NAME\ngethostid, sethostid \\- get/set unique identifier of current host\n.SH SYNOPSIS\n.nf\n.ft B\nhostid = gethostid()\nlong hostid;\n.PP\n.ft B\nsethostid(hostid)\nlong hostid;\n.fi\n.SH DESCRIPTION\n.I Sethostid\nestablishes a 32-bit identifier for the\ncurrent processor that is intended to be unique among all\nUNIX systems in existence.  This is normally a DARPA Internet\naddress for the local machine.  This call is allowed only to the\nsuper-user and is normally performed at boot time.\n.PP\n.I Gethostid\nreturns the 32-bit identifier for the current processor.\n.SH SEE ALSO\nhostid(1), gethostname(2)\n.SH BUGS\n32 bits for the identifier is too small.\n"
  },
  {
    "path": "share/man/man2/gethostname.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)gethostname.2\t6.4 (Berkeley) 5/22/86\n.\\\"\n.TH GETHOSTNAME 2 \"May 22, 1986\"\n.UC 5\n.SH NAME\ngethostname, sethostname \\- get/set name of current host\n.SH SYNOPSIS\n.nf\n.ft B\ngethostname(name, namelen)\nchar *name;\nint namelen;\n.PP\n.ft B\nsethostname(name, namelen)\nchar *name;\nint namelen;\n.fi\n.SH DESCRIPTION\n.I Gethostname\nreturns the standard host name for the current processor, as\npreviously set by\n.IR sethostname . \nThe parameter\n.I namelen\nspecifies the size of the \n.I name\narray.  The returned name is null-terminated unless insufficient\nspace is provided.\n.PP\n.I Sethostname\nsets the name of the host machine to be\n.IR name ,\nwhich has length\n.IR namelen .\nThis call is restricted to the super-user and\nis normally used only when the system is bootstrapped.\n.SH \"RETURN VALUE\nIf the call succeeds a value of 0 is returned.  If the call\nfails, then a value of \\-1 is returned and an error code is\nplaced in the global location \\fIerrno\\fP.\n.SH \"ERRORS\nThe following errors may be returned by these calls:\n.TP 15\n[EFAULT]\nThe \\fIname\\fP or \\fInamelen\\fP parameter gave an\ninvalid address.\n.TP 15\n[EPERM]\nThe caller tried to set the hostname and was not the super-user.\n.SH SEE ALSO\ngethostid(2)\n.SH BUGS\nHost names are limited to MAXHOSTNAMELEN (from\n.IR <sys/param.h> )\ncharacters, currently 64.\n"
  },
  {
    "path": "share/man/man2/getitimer.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)getitimer.2\t6.2 (Berkeley) 8/26/85\n.\\\"\n.TH GETITIMER 2 \"August 26, 1985\"\n.UC 5\n.SH NAME\ngetitimer, setitimer \\- get/set value of interval timer\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/time.h>\n.PP\n.ft B\n#define ITIMER_REAL   \t0\t/* real time intervals */\n#define ITIMER_VIRTUAL\t1\t/* virtual time intervals */\n#define ITIMER_PROF   \t2\t/* user and system virtual time */\n.sp\n.ft B\ngetitimer(which, value)\nint which;\nstruct itimerval *value;\n.PP\n.ft B\nsetitimer(which, value, ovalue)\nint which;\nstruct itimerval *value, *ovalue;\n.fi\n.SH DESCRIPTION\nThe system provides each process with three interval timers,\ndefined in\n.RI < sys/time.h >.\nThe\n.I getitimer\ncall returns the current value for the timer specified in\n.I which\nin the structure at\n.IR value .\nThe\n.I setitimer\ncall sets a timer to the specified\n.I value\n(returning the previous value of the timer if\n.I ovalue\nis nonzero).\n.PP\nA timer value is defined by the \n.I itimerval\nstructure:\n.PP\n.nf\n.RS\n.DT\nstruct itimerval {\n\tstruct\ttimeval it_interval;\t/* timer interval */\n\tstruct\ttimeval it_value;\t/* current value */\n};\n.RE\n.fi\n.PP\nIf\n.I it_value\nis non-zero, it indicates the time to the next timer expiration. \nIf\n.I it_interval\nis non-zero, it specifies a value to be used in reloading \n.I it_value\nwhen the timer expires.\nSetting \n.I it_value\nto 0 disables a timer.  Setting \n.I it_interval\nto 0 causes a timer to be disabled after its next expiration (assuming\n.I it_value\nis non-zero).\n.PP\nTime values smaller than the resolution of the\nsystem clock are rounded up to this resolution\n(on the VAX, 10 milliseconds).\n.PP\nThe ITIMER_REAL timer decrements in real time.  A SIGALRM signal is\ndelivered when this timer expires.\n.PP\nThe ITIMER_VIRTUAL timer decrements in process virtual time.\nIt runs only when the process is executing.  A SIGVTALRM signal\nis delivered when it expires.\n.PP\nThe ITIMER_PROF timer decrements both in process virtual time and\nwhen the system is running on behalf of the process.  It is designed\nto be used by interpreters in statistically profiling the execution\nof interpreted programs.\nEach time the ITIMER_PROF timer expires, the SIGPROF signal is\ndelivered.  Because this signal may interrupt in-progress\nsystem calls, programs using this timer must be prepared to\nrestart interrupted system calls.\n.SH NOTES\nThree macros for manipulating time values are defined in\n.RI < sys/time.h >.\n.I Timerclear\nsets a time value to zero,\n.I timerisset\ntests if a time value is non-zero, and\n.I timercmp\ncompares two time values (beware that >= and <= do not\nwork with this macro).\n.SH \"NOTES  (PDP-11)\"\nOn the PDP-11,\n.I setitimer\nrounds timer values up to seconds resolution.  (This saves some space and\ncomputation in the overburdened PDP-11 kernel.)\n.SH \"RETURN VALUE\nIf the calls succeed, a value of 0 is returned.  If an error occurs,\nthe value \\-1 is returned, and a more precise error code is placed\nin the global variable \\fIerrno\\fP.\n.SH \"ERRORS\nThe possible errors are:\n.TP 15\n[EFAULT]\nThe \\fIvalue\\fP parameter specified a bad address.\n.TP 15\n[EINVAL]\nA \\fIvalue\\fP parameter specified a time was too large\nto be handled.\n.SH \"SEE ALSO\"\nsigvec(2), gettimeofday(2)\n"
  },
  {
    "path": "share/man/man2/getlogin.2",
    "content": ".\\\" Copyright (c) 1989, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"\t@(#)getlogin.2\t8.1.1 (2.11BSD) 1997/9/23\n.\\\"\n.TH GETLOGIN 2 \"September 23, 1997\"\n.UC 5\n.SH NAME\n\\fBgetlogin\\fP, \\fBsetlogin\\fP \\- get/set login name\n.SH SYNOPSIS\n.B #include <unistd.h>\n.sp\n.nf\nchar *\ngetlogin()\n.sp\nint\nsetlogin(name)\n\tchar *name;\n.fi\n.SH DESCRIPTION\nThe\n.B getlogin\nroutine\nreturns the login name of the user associated with the current session,\nas previously set by\n.BR setlogin .\nThe name is normally associated with a login shell\nat the time a session is created,\nand is inherited by all processes descended from the login shell.\n(This is true even if some of those processes assume another user ID,\nfor example when\n\\fBsu\\fP(1)\nis used.)\n.PP\n.B Setlogin\nsets the login name of the user associated with the current session to\n.IR name .\nThis call is restricted to the super-user, and\nis normally used only when a new session is being created on behalf\nof the named user\n(for example, at login time, or when a remote shell is invoked).\n.SH RETURN VALUES\nIf a call to\n.B getlogin\nsucceeds, it returns a pointer to a null-terminated string in a static buffer.\nIf the name has not been set, it returns\n.IR NULL .\nIf a call to\n.B setlogin\nsucceeds, a value of 0 is returned.  If\n.B setlogin\nfails, a value of -1 is returned and an error code is\nplaced in the global location\n.IR errno .\n.SH ERRORS\nThe following errors may be returned by these calls:\n.TP 15\nEFAULT\nThe\n.I name\nparameter gave an invalid address.\n.TP 15\nEINVAL\nThe\n.I name\nparameter pointed to a string that was too long.\nLogin names are limited to\n.I MAXLOGNAME\n(from\n\\fI\\<sys/param.h\\>\\fP)\ncharacters, currently 16.\n.TP 15\nEPERM\nThe caller tried to set the login name and was not the super-user.\n.SH SEE ALSO\nsetsid(2)\n.SH BUGS\nLogin names are limited in length by\n.BR setlogin .\nHowever, lower limits are placed on login names elsewhere in the system\n(UT_NAMESIZE in\n\\fI\\<utmp.h\\>\\fP).\n.PP\nIn earlier versions of the system,\n.B getlogin\nfailed unless the process was associated with a login terminal.\nThe current implementation (using\n.BR setlogin )\nallows getlogin to succeed even when the process has no controlling terminal.\nIn earlier versions of the system, the value returned by\n.B getlogin\ncould not be trusted without checking the user ID.\nPortable programs should probably still make this check.\n.SH HISTORY\nThe\n.B setlogin\nfunction first appeared in 4.4BSD.\nThe\n.B getlogin function was present in V7.\n"
  },
  {
    "path": "share/man/man2/getpagesize.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)getpagesize.2\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH GETPAGESIZE 2 \"May 15, 1985\"\n.UC 5\n.SH NAME\ngetpagesize \\- get system page size\n.SH SYNOPSIS\n.nf\n.ft B\npagesize = getpagesize()\nint pagesize;\n.ft R\n.fi\n.SH DESCRIPTION\n.I Getpagesize\nreturns the number of bytes in a page.\nPage granularity is the granularity of many of the memory\nmanagement calls.\n.PP\nThe page size is a \n.I system\npage size and may not be the same as the underlying\nhardware page size.\n.SH SEE ALSO\nsbrk(2), pagesize(1)\n"
  },
  {
    "path": "share/man/man2/getpeername.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)getpeername.2\t6.2 (Berkeley) 5/13/86\n.\\\"\n.TH GETPEERNAME 2 \"May 13, 1986\"\n.UC 5\n.SH NAME\ngetpeername \\- get name of connected peer\n.SH SYNOPSIS\n.nf\n.PP\n.ft B\ngetpeername(s, name, namelen)\nint s;\nstruct sockaddr *name;\nint *namelen;\n.fi\n.SH DESCRIPTION\n.I Getpeername\nreturns the name of the peer connected to\nsocket\n.IR s .\nThe\n.I namelen\nparameter should be initialized to indicate\nthe amount of space pointed to by\n.IR name .\nOn return it contains the actual size of the name\nreturned (in bytes).\nThe name is truncated if the buffer provided is too small.\n.SH DIAGNOSTICS\nA 0 is returned if the call succeeds, \\-1 if it fails.\n.SH ERRORS\nThe call succeeds unless:\n.TP 15\n[EBADF]\nThe argument \\fIs\\fP is not a valid descriptor.\n.TP 15\n[ENOTSOCK]\nThe argument \\fIs\\fP is a file, not a socket.\n.TP 15\n[ENOTCONN]\nThe socket is not connected.\n.TP 15\n[ENOBUFS]\nInsufficient resources were available in the system\nto perform the operation.\n.TP 15\n[EFAULT]\nThe \n.I name\nparameter points to memory not in a valid part of the\nprocess address space.\n.SH \"SEE ALSO\"\naccept(2), bind(2), socket(2), getsockname(2)\n"
  },
  {
    "path": "share/man/man2/getpgrp.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)getpgrp.2\t6.3 (Berkeley) 8/26/85\n.\\\"\n.TH GETPGRP 2 \"August 26, 1985\"\n.UC 5\n.SH NAME\ngetpgrp \\- get process group\n.SH SYNOPSIS\n.ft B\n.nf\npgrp = getpgrp(pid)\nint pgrp;\nint pid;\n.fi\n.ft R\n.SH DESCRIPTION\nThe process group of the specified process is returned by\n.I getpgrp.\nIf\n.I pid\nis zero, then the call applies to the current process.\n.PP\nProcess groups are used for distribution of signals, and\nby terminals to arbitrate requests for their input: processes\nthat have the same process group as the terminal are foreground\nand may read, while others will block with a signal if they attempt\nto read.\n.PP\nThis call is thus used by programs such as\n.IR csh (1)\nto create\nprocess groups\nin implementing job control.\nThe TIOCGPGRP and TIOCSPGRP calls\ndescribed in\n.IR tty (4)\nare used to get/set the process group of the control terminal.\n.SH \"SEE ALSO\"\nsetpgrp(2), getuid(2), tty(4)\n"
  },
  {
    "path": "share/man/man2/getpid.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)getpid.2\t6.3 (Berkeley) 5/13/86\n.\\\"\n.TH GETPID 2 \"May 13, 1986\"\n.UC 4\n.SH NAME\ngetpid, getppid \\- get process identification\n.SH SYNOPSIS\n.ft B\n.nf\npid = getpid()\nint pid;\n.sp\nppid = getppid()\nint ppid;\n.fi\n.ft R\n.SH DESCRIPTION\n.I Getpid\nreturns\nthe process ID of\nthe current process.\nMost often it is used\nto generate uniquely-named temporary files.\n.PP\n.I Getppid\nreturns the process ID of the parent\nof the current process. \n.SH \"SEE ALSO\ngethostid(2)\n"
  },
  {
    "path": "share/man/man2/getpriority.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)getpriority.2\t6.5 (Berkeley) 5/22/86\n.\\\"\n.TH GETPRIORITY 2 \"May 22, 1986\"\n.UC 4\n.SH NAME\ngetpriority, setpriority \\- get/set program scheduling priority\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/resource.h>\n.PP\n.ft B\nprio = getpriority(which, who)\nint prio, which, who;\n.PP\n.ft B\nsetpriority(which, who, prio)\nint which, who, prio;\n.fi\n.SH DESCRIPTION\nThe scheduling\npriority of the process, process group, or user, as indicated by\n.I which\nand\n.I who\nis obtained with the\n.I getpriority\ncall and set with the\n.I setpriority\ncall.\n.I Which\nis one of PRIO_PROCESS, PRIO_PGRP, or PRIO_USER, and \n.I who\nis interpreted relative to \n.I which\n(a process identifier for PRIO_PROCESS, process group\nidentifier for PRIO_PGRP, and a user ID for PRIO_USER).\nA zero value of\n.I who\ndenotes the current process, process group, or user.\n.I Prio\nis a value in the range \\-20 to 20.  The default priority is 0;\nlower priorities cause more favorable scheduling.\n.PP\nThe\n.I getpriority\ncall returns the highest priority (lowest numerical value)\nenjoyed by any of the specified processes.  The\n.I setpriority\ncall sets the priorities of all of the specified processes\nto the specified value.  Only the super-user may lower priorities.\n.SH \"RETURN VALUE\nSince\n.I getpriority\ncan legitimately return the value \\-1, it is necessary\nto clear the external variable \\fIerrno\\fP prior to the\ncall, then check it afterward to determine\nif a \\-1 is an error or a legitimate value.\nThe\n.I setpriority\ncall returns 0 if there is no error, or\n\\-1 if there is.\n.SH ERRORS\n.I Getpriority\nand\n.I setpriority\nmay return one of the following errors:\n.TP 15\n[ESRCH]\nNo process was located using the \n.I which\nand\n.I who\nvalues specified.\n.TP 15\n[EINVAL]\n.I Which\nwas not one of PRIO_PROCESS, PRIO_PGRP, or PRIO_USER.\n.PP\nIn addition to the errors indicated above,\n.I setpriority\nmay fail with one of the following errors returned:\n.TP 15\n[EPERM]\nA process was located, but neither its effective nor real user\nID matched the effective user ID of the caller.\n.TP 15\n[EACCES]\nA non super-user attempted to lower a process priority.\n.SH \"SEE ALSO\"\nnice(1), fork(2), renice(8)\n"
  },
  {
    "path": "share/man/man2/getrlimit.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)getrlimit.2\t6.3 (Berkeley) 5/13/86\n.\\\"\n.TH GETRLIMIT 2 \"May 13, 1986\"\n.UC 4\n.SH NAME\ngetrlimit, setrlimit \\- control maximum system resource consumption\n.SH SYNOPSIS\n.ft B\n.nf\n#include <sys/time.h>\n#include <sys/resource.h>\n.PP\n.ft B\ngetrlimit(resource, rlp)\nint resource;\nstruct rlimit *rlp;\n.PP\n.ft B\nsetrlimit(resource, rlp)\nint resource;\nstruct rlimit *rlp;\n.fi\n.ft R\n.SH DESCRIPTION\nLimits on the consumption of system resources by the current process\nand each process it creates may be obtained with the\n.I getrlimit\ncall, and set with the\n.I setrlimit\ncall.  \n.PP\nThe\n.I resource\nparameter is one of the following:\n.TP 17\nRLIMIT_CPU\nthe maximum amount of cpu time (in seconds) to be used by\neach process.\n.TP 17\nRLIMIT_FSIZE\nthe largest size, in bytes, of any single file that may be created.\n.TP 17\nRLIMIT_DATA\nthe maximum size, in bytes, of the data segment for a process;\nthis defines how far a program may extend its break with the\n.IR sbrk (2)\nsystem call.\n.TP 17\nRLIMIT_STACK\nthe maximum size, in bytes, of the stack segment for a process;\nthis defines how far a program's stack segment may be extended.\nStack extension is performed automatically by the system.\n.TP 17\nRLIMIT_CORE\nthe largest size, in bytes, of a \n.I core\nfile that may be created.\n.TP 17\nRLIMIT_RSS\nthe maximum size, in bytes, to which a process's resident set size may\ngrow.  This imposes a limit on the amount of physical memory\nto be given to a process; if memory is tight, the system will\nprefer to take memory from processes that are exceeding their\ndeclared resident set size.\n.PP\nA resource limit is specified as a soft limit and a hard limit.\nWhen a soft limit is exceeded a process may receive a signal\n(for example, if the cpu time is exceeded), but it will be allowed\nto continue execution until it reaches the hard limit (or modifies\nits resource limit).  The \n.I rlimit\nstructure is used to specify the hard and soft limits on a resource,\n.PP\n.nf\n.RS\n.DT\nstruct rlimit {\n\tint\trlim_cur;\t/* current (soft) limit */\n\tint\trlim_max;\t/* hard limit */\n};\n.RE\n.fi\n.PP\nOnly the super-user may raise the maximum limits.  Other users\nmay only alter \n.I rlim_cur\nwithin the range from 0 to \n.I rlim_max\nor (irreversibly) lower\n.IR rlim_max .\n.PP\nAn \\*(lqinfinite\\*(rq value for a limit is defined as RLIM_INFINITY\n(0x7\\&f\\&f\\&f\\&f\\&f\\&f\\&f).\n.PP\nBecause this information is stored in the per-process information,\nthis system call must be executed directly by the shell if it\nis to affect all future processes created by the shell;\n.I limit\nis thus a built-in command to\n.IR csh (1).\n.PP\nThe system refuses to extend the data or stack space when the limits\nwould be exceeded in the normal way: a\n.I break\ncall fails if the data space limit is reached.\nWhen the stack limit is reached, the process receives\na segmentation fault (SIGSEGV); if this signal is not\ncaught by a handler using the signal stack, this signal\nwill kill the process.\n.PP\nA file I/O operation that would create a file that is too large\nwill cause a signal SIGXFSZ to be generated; this normally terminates\nthe process, but may be caught.\nWhen the soft cpu time limit is exceeded, a signal SIGXCPU is sent to the\noffending process.\n.SH \"RETURN VALUE\nA 0 return value indicates that the call succeeded, changing\nor returning the resource limit.   A return value of \\-1 indicates\nthat an error occurred, and an error code is stored in the global\nlocation \\fIerrno\\fP.\n.SH \"ERRORS\nThe possible errors are:\n.TP 15\n[EFAULT]\nThe address specified for \\fIrlp\\fP is invalid.\n.TP 15\n[EPERM]\tThe limit specified to \\fIsetrlimit\\fP would have\nraised the maximum limit value, and the caller is not the super-user.\n.SH SEE ALSO\ncsh(1), quota(2), sigvec(2), sigstack(2)\n.SH BUGS\nThere should be \n.I limit\nand\n.I unlimit\ncommands in\n.IR sh (1)\nas well as in\n.IR csh.\n"
  },
  {
    "path": "share/man/man2/getrusage.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)getrusage.2\t6.4 (Berkeley) 5/13/86\n.\\\"\n.TH GETRUSAGE 2 \"May 13, 1986\"\n.UC 4\n.SH NAME\ngetrusage \\- get information about resource utilization\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/time.h>\n#include <sys/resource.h>\n.PP\n.ft B\n.ta \\w'#define 'u +\\w'RUSAGE_CHILDREN  'u +\\w'-1        'u\n#define\tRUSAGE_SELF\t0\t/* calling process */\n#define\tRUSAGE_CHILDREN\t-1\t/* terminated child processes */\n.DT\n.PP\n.ft B\ngetrusage(who, rusage)\nint who;\nstruct rusage *rusage;\n.fi\n.SH DESCRIPTION\n.I Getrusage\nreturns information describing the resources utilized by the current\nprocess, or all its terminated child processes.\nThe\n.I who\nparameter is one of RUSAGE_SELF or RUSAGE_CHILDREN.\nThe buffer to which\n.I rusage\npoints will be filled in with\nthe following structure:\n.PP\n.nf\n.RS\n.ta \\w'struct  'u +\\w'struct  'u +3u*\\w'struct  'u\nstruct\trusage {\n\tstruct timeval ru_utime;\t/* user time used */\n\tstruct timeval ru_stime;\t/* system time used */\n\tlong\tru_maxrss;\n\tlong\tru_ixrss;\t/* integral shared text memory size */\n\tlong\tru_idrss;\t/* integral unshared data size */\n\tlong\tru_isrss;\t/* integral unshared stack size */\n\tlong\tru_minflt;\t/* page reclaims */\n\tlong\tru_majflt;\t/* page faults */\n\tlong\tru_ovly;\t\t/* overlay changes */\n\tlong\tru_nswap;\t/* swaps */\n\tlong\tru_inblock;\t/* block input operations */\n\tlong\tru_oublock;\t/* block output operations */\n\tlong\tru_msgsnd;\t/* messages sent */\n\tlong\tru_msgrcv;\t/* messages received */\n\tlong\tru_nsignals;\t/* signals received */\n\tlong\tru_nvcsw;\t/* voluntary context switches */\n\tlong\tru_nivcsw;\t/* involuntary context switches */\n};\n.RE\n.DT\n.fi\n.PP\nThe fields are interpreted as follows:\n.TP 15\nru_utime\nthe total amount of time spent executing in user mode.\n.TP 15\nru_stime\nthe total amount of time spent in the system executing on behalf\nof the process(es).\n.TP 15\nru_maxrss\nthe maximum resident set size utilized (in kilobytes).\n.TP 15\nru_ixrss\nan \\*(lqintegral\\*(rq value indicating the amount of memory used\nby the text segment\nthat was also shared among other processes.  This value is expressed\nin units of kilobytes * seconds-of-execution and is calculated by\nsumming the number of shared memory pages in use each time the internal\nsystem clock ticks and then averaging over 1 second intervals.\n.TP 15\nru_idrss\nan integral value of the amount of unshared memory residing in the\ndata segment of a process (expressed in units of\nkilobytes * seconds-of-execution).\n.TP 15\nru_isrss\nan integral value of the amount of unshared memory residing in the\nstack segment of a process (expressed in units of\nkilobytes * seconds-of-execution).\n.TP 15\nru_minflt\nthe number of page faults serviced without any I/O activity; here\nI/O activity is avoided by \\*(lqreclaiming\\*(rq a page frame from\nthe list of pages awaiting reallocation.\n.TP 15\nru_majflt\nthe number of page faults serviced that required I/O activity.\n.TP 15\nthe number of times a process requested a text overlay switch \\-\nonly available under 2_10BSD.\n.TP 15\nru_nswap\nthe number of times a process was \\*(lqswapped\\*(rq out of main\nmemory.\n.TP 15\nru_inblock\nthe number of times the file system had to perform input.\n.TP 15\nru_outblock\nthe number of times the file system had to perform output.\n.TP 15\nru_msgsnd\nthe number of IPC messages sent.\n.TP 15\nru_msgrcv\nthe number of IPC messages received.\n.TP 15\nru_nsignals\nthe number of signals delivered.\n.TP 15\nru_nvcsw\nthe number of times a context switch resulted due to a process\nvoluntarily giving up the processor before its time slice was\ncompleted (usually to await availability of a resource).\n.TP 15\nru_nivcsw\nthe number of times a context switch resulted due to a higher\npriority process becoming runnable or because the current process\nexceeded its time slice.\n.SH NOTES\nThe numbers \n.I ru_inblock\nand \n.I ru_outblock\naccount only for real\nI/O; data supplied by the caching mechanism is charged only\nto the first process to read or write the data.\n.SH ERRORS\nThe possible errors for\n.I getrusage\nare:\n.TP 15\n[EINVAL]\nThe\n.I who\nparameter is not a valid value.\n.TP 15\n[EFAULT]\nThe address specified by the\n.I rusage\nparameter is not in a valid part of the process address space.\n.SH SEE ALSO\ngettimeofday(2), wait(2)\n.SH BUGS\nThere is no way to obtain information about a child process\nthat has not yet terminated.\n"
  },
  {
    "path": "share/man/man2/getsockname.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)getsockname.2\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH GETSOCKNAME 2 \"May 15, 1985\"\n.UC 5\n.SH NAME\ngetsockname \\- get socket name\n.SH SYNOPSIS\n.nf\n.PP\n.ft B\ngetsockname(s, name, namelen)\nint s;\nstruct sockaddr *name;\nint *namelen;\n.fi\n.SH DESCRIPTION\n.I Getsockname\nreturns the current \n.I name\nfor the specified socket.  The\n.I namelen\nparameter should be initialized to indicate\nthe amount of space pointed to by\n.IR name .\nOn return it contains the actual size of the name\nreturned (in bytes).\n.SH DIAGNOSTICS\nA 0 is returned if the call succeeds, \\-1 if it fails.\n.SH ERRORS\nThe call succeeds unless:\n.TP 15\n[EBADF]\nThe argument \\fIs\\fP is not a valid descriptor.\n.TP 15\n[ENOTSOCK]\nThe argument \\fIs\\fP is a file, not a socket.\n.TP 15\n[ENOBUFS]\nInsufficient resources were available in the system\nto perform the operation.\n.TP 15\n[EFAULT]\nThe \n.I name\nparameter points to memory not in a valid part of the\nprocess address space.\n.SH \"SEE ALSO\"\nbind(2), socket(2)\n.SH BUGS\nNames bound to sockets in the UNIX domain are inaccessible;\n.I getsockname\nreturns a zero length name.\n"
  },
  {
    "path": "share/man/man2/getsockopt.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)getsockopt.2\t6.4 (Berkeley) 5/23/86\n.\\\"\n.TH GETSOCKOPT 2 \"May 23, 1986\"\n.UC 5\n.SH NAME\ngetsockopt, setsockopt \\- get and set options on sockets\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/types.h>\n#include <sys/socket.h>\n.PP\n.ft B\ngetsockopt(s, level, optname, optval, optlen)\nint s, level, optname;\nchar *optval;\nint *optlen;\n.sp\nsetsockopt(s, level, optname, optval, optlen)\nint s, level, optname;\nchar *optval;\nint optlen;\n.fi\n.SH DESCRIPTION\n.I Getsockopt\nand\n.I setsockopt\nmanipulate\n.I options\nassociated with a socket.  Options may exist at multiple\nprotocol levels; they are always present at the uppermost\n``socket'' level.\n.PP\nWhen manipulating socket options the level at which the\noption resides and the name of the option must be specified.\nTo manipulate options at the ``socket'' level,\n.I level\nis specified as SOL_SOCKET.  To manipulate options at any\nother level the protocol number of the appropriate protocol\ncontrolling the option is supplied.  For example,\nto indicate that an option is to be interpreted by the TCP protocol,\n.I level\nshould be set to the protocol number of TCP; see\n.IR getprotoent (3N).\n.PP\nThe parameters\n.I optval\nand\n.I optlen\nare used to access option values for\n.IR setsockopt .\nFor\n.I getsockopt\nthey identify a buffer in which the value for the\nrequested option(s) are to be returned.  For\n.IR getsockopt ,\n.I optlen\nis a value-result parameter, initially containing the\nsize of the buffer pointed to by\n.IR optval ,\nand modified on return to indicate the actual size of\nthe value returned.  If no option value is\nto be supplied or returned,\n.I optval\nmay be supplied as 0.\n.PP\n.I Optname\nand any specified options are passed uninterpreted to the appropriate\nprotocol module for interpretation.\nThe include file\n.RI < sys/socket.h >\ncontains definitions for ``socket'' level options, described below.\nOptions at other protocol levels vary in format and\nname; consult the appropriate entries in section (4P).\n.PP\nMost socket-level options take an\n.I int\nparameter for\n.IR optval .\nFor\n.IR setsockopt ,\nthe parameter should non-zero to enable a boolean option,\nor zero if the option is to be disabled.\nSO_LINGER uses a\n.I struct linger\nparameter, defined in\n.RI < sys/socket.h >,\nwhich specifies the desired state of the option and the\nlinger interval (see below).\n.PP\nThe following options are recognized at the socket level.\nExcept as noted, each may be examined with\n.I getsockopt\nand set with\n.IR setsockopt .\n.PP\n.RS\n.ta \\w'SO_BROADCAST\\ \\ \\ \\ 'u\n.nf\nSO_DEBUG \ttoggle recording of debugging information\nSO_REUSEADDR\ttoggle local address reuse\nSO_KEEPALIVE\ttoggle keep connections alive\nSO_DONTROUTE\ttoggle routing bypass for outgoing messages\nSO_LINGER \tlinger on close if data present\nSO_BROADCAST\ttoggle permission to transmit broadcast messages\nSO_OOBINLINE\ttoggle reception of out-of-band data in band\nSO_SNDBUF\tset buffer size for output\nSO_RCVBUF\tset buffer size for input\nSO_TYPE\tget the type of the socket (get only)\nSO_ERROR\tget and clear error on the socket (get only)\n.fi\n.RE\n.PP\nSO_DEBUG enables debugging in the underlying protocol modules.\nSO_REUSEADDR indicates that the rules used in validating addresses supplied\nin a\n.IR bind (2)\ncall should allow reuse of local addresses.  SO_KEEPALIVE enables the\nperiodic transmission of messages on a connected socket.  Should the\nconnected party fail to respond to these messages, the connection is\nconsidered broken and processes using the socket are notified via a\nSIGPIPE signal.  SO_DONTROUTE indicates that outgoing messages should\nbypass the standard routing facilities.  Instead, messages are directed\nto the appropriate network interface according to the network portion\nof the destination address.\n.PP\nSO_LINGER controls the action taken when unsent messags\nare queued on socket and a \n.IR close (2)\nis performed.\nIf the socket promises reliable delivery of data and SO_LINGER is set,\nthe system will block the process on the \n.I close\nattempt until it is able to transmit the data or until it decides it\nis unable to deliver the information (a timeout period, termed the\nlinger interval, is specified in the\n.IR setsockopt \ncall when SO_LINGER is requested). \nIf SO_LINGER is disabled and a \n.I close\nis issued, the system will process the close in a manner that allows\nthe process to continue as quickly as possible.\n.PP\nThe option SO_BROADCAST requests permission to send broadcast datagrams\non the socket.\nBroadcast was a privileged operation in earlier versions of the system.\nWith protocols that support out-of-band data, the SO_OOBINLINE option\nrequests that out-of-band data be placed in the normal data input queue\nas received; it will then be accessible with\n.I recv\nor\n.I read\ncalls without the MSG_OOB flag.\nSO_SNDBUF and SO_RCVBUF are options to adjust the normal\nbuffer sizes allocated for output and input buffers, respectively.\nThe buffer size may be increased for high-volume connections,\nor may be decreased to limit the possible backlog of incoming data.\nThe system places an absolute limit on these values.\nFinally, SO_TYPE and SO_ERROR are options used only with\n.IR setsockopt .\nSO_TYPE returns the type of the socket, such as SOCK_STREAM;\nit is useful for servers that inherit sockets on startup.\nSO_ERROR returns any pending error on the socket and clears\nthe error status.\nIt may be used to check for asynchronous errors on connected\ndatagram sockets or for other asynchronous errors.\n.SH \"RETURN VALUE\"\nA 0 is returned if the call succeeds, \\-1 if it fails.\n.SH ERRORS\nThe call succeeds unless:\n.TP 20\n[EBADF]\nThe argument \\fIs\\fP is not a valid descriptor.\n.TP 20\n[ENOTSOCK]\nThe argument \\fIs\\fP is a file, not a socket.\n.TP 20\n[ENOPROTOOPT]\nThe option is unknown at the level indicated.\n.TP 20\n[EFAULT]\nThe address pointed to by \n.I optval\nis not in a valid part of the process address space.\nFor\n.IR getsockopt ,\nthis error may also be returned if\n.I optlen\nis not in a valid part of the process address space.\n.SH \"SEE ALSO\"\nioctl(2), socket(2), getprotoent(3N)\n.SH BUGS\nSeveral of the socket options should be handled at lower levels of the system.\n"
  },
  {
    "path": "share/man/man2/gettimeofday.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)gettimeofday.2\t6.7 (Berkeley) 5/14/86\n.\\\"\n.TH GETTIMEOFDAY 2 \"May 14, 1986\"\n.UC 4\n.SH NAME\ngettimeofday, settimeofday \\- get/set date and time\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/time.h>\n.PP\n.ft B\ngettimeofday(tp, tzp)\nstruct timeval *tp;\nstruct timezone *tzp;\n.PP\n.ft B\nsettimeofday(tp, tzp)\nstruct timeval *tp;\nstruct timezone *tzp;\n.fi\n.SH DESCRIPTION\nThe system's notion of the current Greenwich time and\nthe current time zone\nis obtained with the\n.I gettimeofday\ncall, and set with the\n.I settimeofday\ncall.\nThe time is expressed\nin seconds and microseconds since midnight (0 hour), January 1, 1970.\nThe resolution of the system clock is hardware dependent,\nand the time may be updated continuously or in ``ticks.''\nIf\n.I tzp\nis zero, the time zone information will not be returned or set.\n.PP\nThe structures pointed to by\n.I tp\nand\n.I tzp\nare defined in \n.I <sys/time.h>\nas:\n.PP\n.nf\n.RS\n.DT\nstruct timeval {\n\tlong\ttv_sec;\t\t/* seconds since Jan. 1, 1970 */\n\tlong\ttv_usec;\t\t/* and microseconds */\n};\n.sp 1\nstruct timezone {\n\tint\ttz_minuteswest;\t/* of Greenwich */\n\tint\ttz_dsttime;\t/* type of dst correction to apply */\n};\n.RE\n.fi\n.PP\nThe \n.I timezone\nstructure indicates the local time zone\n(measured in minutes of time westward from Greenwich),\nand a flag that, if nonzero, indicates that\nDaylight Saving time applies locally during\nthe appropriate part of the year.\n.PP\nOnly the super-user may set the time of day or time zone.\n.SH RETURN\nA 0 return value indicates that the call succeeded.\nA \\-1 return value indicates an error occurred, and in this\ncase an error code is stored into the global variable \\fIerrno\\fP.\n.SH \"ERRORS\nThe following error codes may be set in \\fIerrno\\fP:\n.TP 15\n[EFAULT]\nAn argument address referenced invalid memory.\n.TP 15\n[EPERM]\nA user other than the super-user attempted to set the time.\n.SH \"SEE ALSO\"\ndate(1), adjtime(2), ctime(3), timed(8)\n"
  },
  {
    "path": "share/man/man2/getuid.2",
    "content": ".\\\" Copyright (c) 1980, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)getuid.2\t8.1.1 (2.11BSD) 1997/12/2\n.\\\"\n.TH GETUID 2 \"December 2, 1997\"\n.UC 5\n.SH NAME\n\\fBgetuid\\fP, \\fBgeteuid\\fP \\- get user identification\n.SH SYNOPSIS\n.nf\n.B #include <unistd.h>\n.B #include <sys/types.h>\n.sp\n\\fIuid_t\\fP\n\\fBgetuid\\fP()\n.sp\n\\fIuid_t\\fP\n\\fBgeteuid\\fP()\n.fi\n.SH DESCRIPTION\nThe\n.B getuid\nfunction returns the real user ID of the calling process.\nThe\n.B geteuid\nfunction\nreturns the effective user ID of the calling process.\n.PP\nThe real user ID is that of the user who has invoked the program.\nAs the effective user ID\ngives the process additional permissions during\nexecution of ``\\fIset-user-ID\\fP''\nmode processes,\n.B getuid\nis used to determine the real-user-id of the calling process.\n.SH ERRORS\nThe\n.B getuid\nand\n.B geteuid\nfunctions are always successful, and no return value is reserved to\nindicate an error.\n.SH SEE ALSO\ngetgid(2), setreuid(2)\n.SH STANDARDS\n.B Geteuid\nand\n.B getuid\nconform to IEEE Std 1003.1-1988 (``POSIX'').\n"
  },
  {
    "path": "share/man/man2/intro.2",
    "content": ".\\\" Copyright (c) 1980,1983,1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)intro.2\t6.7 (Berkeley) 5/23/86\n.\\\"\n.TH INTRO 2 \"May 23, 1986\"\n.UC 4\n.de en\n.HP\n\\\\$1  \\\\$2  \\\\$3\n.br\n..\n.SH NAME\nintro \\- introduction to system calls and error numbers\n.SH SYNOPSIS\n.B #include <sys/errno.h>\n.SH DESCRIPTION\nThis section describes all of the system calls.  Most\nof these calls have one or more error returns.\nAn error condition is indicated by an otherwise impossible return\nvalue.  This is almost always \\-1; the individual descriptions\nspecify the details.\nNote that a number of system calls overload the meanings of these\nerror numbers, and that the meanings must be interpreted according\nto the type and circumstances of the call.\n.PP\nAs with normal arguments, all return codes and values from\nfunctions are of type integer unless otherwise noted.\nAn error number is also made available in the external\nvariable \\fIerrno\\fP, which is not cleared\non successful calls.\nThus \\fIerrno\\fP should be tested only after an error has occurred.\n.PP\nThe following is a complete list of the errors and their\nnames as given in\n.RI < sys/errno.h >.\n.en 0 \\h'\\w'EIO'u' \"Error 0\nUnused.\n.en 1 EPERM \"Not owner\nTypically this error indicates\nan attempt to modify a file in some way forbidden\nexcept to its owner or super-user.\nIt is also returned for attempts\nby ordinary users to do things\nallowed only to the super-user.\n.en 2 ENOENT \"No such file or directory\nThis error occurs when a file name is specified\nand the file should exist but doesn't, or when one\nof the directories in a path name does not exist.\n.en 3 ESRCH \"No such process\nThe process or process group whose number was given\ndoes not exist, or any such process is already dead.\n.en 4 EINTR \"Interrupted system call\nAn asynchronous signal (such as interrupt or quit)\nthat the user has elected to catch\noccurred during a system call.\nIf execution is resumed\nafter processing the signal\nand the system call is not restarted,\nit will appear as if the interrupted system call\nreturned this error condition.\n.en 5 EIO \"I/O error\nSome physical I/O error occurred during a\n.I read\nor\n.IR write .\nThis error may in some cases occur\non a call following the one to which it actually applies.\n.en 6 ENXIO \"No such device or address\nI/O on a special file refers to a subdevice that does not\nexist,\nor beyond the limits of the device.\nIt may also occur when, for example, an illegal tape drive\nunit number is selected \nor a disk pack is not loaded on a drive.\n.en 7 E2BIG \"Arg list too long\nAn argument list longer than 20480 bytes (or the current limit, NCARGS in\n.IR <sys/param.h> )\nis presented to\n.IR execve .\n.en 8 ENOEXEC \"Exec format error\nA request is made to execute a file\nthat, although it has the appropriate permissions,\ndoes not start with a valid magic number, (see\n.IR a.out (5)).\n.en 9 EBADF \"Bad file number\nEither a file descriptor refers to no\nopen file,\nor a read (resp. write) request is made to\na file that is open only for writing (resp. reading).\n.en 10 ECHILD \"No children\n.I Wait\nand the process has no\nliving or unwaited-for children.\n.en 11 EAGAIN \"No more processes\nIn a\n.I fork,\nthe system's process table is full\nor the user is not allowed to create any more\nprocesses.\n.en 12 ENOMEM \"Not enough memory\nDuring an\n.I execve\nor\n.I break,\na program asks for more core or swap space than the system is\nable to supply,\nor a process size limit would be exceeded.\nA lack of swap space is normally a temporary condition; however,\na lack of core\nis not a temporary condition; the maximum size\nof the text, data, and stack segments is a system parameter.\nSoft limits may be increased to their corresponding hard limits.\n.en 13 EACCES \"Permission denied\nAn attempt was made to access a file in a way forbidden\nby the protection system.\n.en 14 EFAULT \"Bad address\nThe system encountered a hardware fault in attempting to\naccess the arguments of a system call.\n.en 15 ENOTBLK \"Block device required\nA plain file was mentioned where a block device was required,\ne.g., in\n.IR mount .\n.en 16 EBUSY \"Device busy\nAn attempt to mount a device that was already mounted or\nan attempt was made to dismount a device\non which there is an active file\n(open file, current directory, mounted-on file, or active text segment).\nA request was made to an exclusive access device that was already in use.\n.en 17 EEXIST \"File exists\nAn existing file was mentioned in an inappropriate context,\ne.g.,\n.IR link .\n.en 18 EXDEV \"Cross-device link\nA hard link to a file on another device\nwas attempted.\n.en 19 ENODEV \"No such device\nAn attempt was made to apply an inappropriate\nsystem call to a device,\ne.g., to read a write-only device,\nor the device is not configured by the system.\n.en 20 ENOTDIR \"Not a directory\nA non-directory was specified where a directory\nis required,\nfor example, in a path name or\nas an argument to\n.IR chdir .\n.en 21 EISDIR \"Is a directory\nAn attempt to write on a directory.\n.en 22 EINVAL \"Invalid argument\nSome invalid argument:\ndismounting a non-mounted\ndevice,\nmentioning an unknown signal in\n.I signal,\nor some other argument inappropriate for the call.\nAlso set by math functions, (see \n.IR math (3)).\n.en 23 ENFILE \"File table overflow\nThe system's table of open files is full,\nand temporarily no more\n.I opens\ncan be accepted.\n.en 24 EMFILE \"Too many open files\nAs released, the limit on the number of\nopen files per process is 64.\n.IR Getdtablesize (2)\nwill obtain the current limit.\nCustomary configuration limit on most other UNIX systems\nis 20 per process.\n.en 25 ENOTTY \"Inappropriate ioctl for device\nThe file mentioned in an\n.I ioctl\nis not a terminal or one of the\ndevices to which this call applies.\n.en 26 ETXTBSY \"Text file busy\nAn attempt to execute a pure-procedure\nprogram that is currently open for writing.\nAlso an attempt to open for writing a pure-procedure\nprogram that is being executed.\n.en 27 EFBIG \"File too large\nThe size of a file exceeded the maximum (about\n.if t 2\\u\\s-231\\s+2\\d\n.if n 2.1E9\nbytes).\n.en 28 ENOSPC \"No space left on device\nA\n.I write\nto an ordinary file, the creation of a\ndirectory or symbolic link, or the creation of a directory\nentry failed because no more disk blocks are available\non the file system, or the allocation of an inode for a newly\ncreated file failed because no more inodes are available\non the file system.\n.en 29 ESPIPE \"Illegal seek\nAn\n.I lseek\nwas issued to a socket or pipe.\nThis error may also be issued for\nother non-seekable devices.\n.en 30 EROFS \"Read-only file system\nAn attempt to modify a file or directory\nwas made\non a device mounted read-only.\n.en 31 EMLINK \"Too many links\nAn attempt to make more than 32767 hard links to a file.\n.en 32 EPIPE \"Broken pipe\nA write on a pipe or socket for which there is no process\nto read the data.\nThis condition normally generates a signal;\nthe error is returned if the signal is caught or ignored.\n.en 33 EDOM \"Argument too large\nThe argument of a function in the math package (3M)\nis out of the domain of the function.\n.en 34 ERANGE \"Result too large\nThe value of a function in the math package (3M)\nis unrepresentable within machine precision.\n.en 35 EWOULDBLOCK \"Operation would block\"\nAn operation that would cause a process to block was attempted\non an object in non-blocking mode (see \\fIfcntl\\fP(2)).\n.en 36 EINPROGRESS \"Operation now in progress\"\nAn operation that takes a long time to complete (such as\na \\fIconnect\\fP(2)) was attempted on a non-blocking object (see\n\\fIfcntl\\fP(2)).\n.en 37 EALREADY \"Operation already in progress\"\nAn operation was attempted on a non-blocking object that already\nhad an operation in progress.\n.en 38 ENOTSOCK \"Socket operation on non-socket\"\nSelf-explanatory.\n.en 39 EDESTADDRREQ \"Destination address required\"\nA required address was omitted from an operation on a socket.\n.en 40 EMSGSIZE \"Message too long\"\nA message sent on a socket was larger than the internal message buffer\nor some other network limit.\n.en 41 EPROTOTYPE \"Protocol wrong type for socket\"\nA protocol was specified that does not support the semantics of the\nsocket type requested. For example, you cannot use the ARPA Internet\nUDP protocol with type SOCK_STREAM.\n.en 42 ENOPROTOOPT \"Option not supported by protocol \nA bad option or level was specified in a\n.IR getsockopt (2)\nor\n.IR setsockopt (2)\ncall.\n.en 43 EPROTONOSUPPORT \"Protocol not supported\"\nThe protocol has not been configured into the\nsystem or no implementation for it exists.\n.en 44 ESOCKTNOSUPPORT \"Socket type not supported\"\nThe support for the socket type has not been configured into the\nsystem or no implementation for it exists.\n.en 45 EOPNOTSUPP \"Operation not supported on socket\"\nFor example, trying to \\fIaccept\\fP a connection on a datagram socket.\n.en 46 EPFNOSUPPORT \"Protocol family not supported\"\nThe protocol family has not been configured into the\nsystem or no implementation for it exists.\n.en 47 EAFNOSUPPORT \"Address family not supported by protocol family\"\nAn address incompatible with the requested protocol was used.\nFor example, you shouldn't necessarily expect to be able to use NS\naddresses with ARPA Internet protocols.\n.en 48 EADDRINUSE \"Address already in use\"\nOnly one usage of each address is normally permitted.\n.en 49 EADDRNOTAVAIL \"Can't assign requested address\"\nNormally results from an attempt to create a socket with an\naddress not on this machine.\n.en 50 ENETDOWN \"Network is down\"\nA socket operation encountered a dead network.\n.en 51 ENETUNREACH \"Network is unreachable\"\nA socket operation was attempted to an unreachable network.\n.en 52 ENETRESET \"Network dropped connection on reset\"\nThe host you were connected to crashed and rebooted.\n.en 53 ECONNABORTED \"Software caused connection abort\"\nA connection abort was caused internal to your host machine.\n.en 54 ECONNRESET \"Connection reset by peer\"\nA connection was forcibly closed by a peer.  This normally\nresults from a loss of the connection on the remote socket\ndue to a timeout or a reboot.\n.en 55 ENOBUFS \"No buffer space available\"\nAn operation on a socket or pipe was not performed because\nthe system lacked sufficient buffer space or because a queue was full.\n.en 56 EISCONN \"Socket is already connected\"\nA\n.I connect\nrequest was made on an already connected socket; or,\na\n.I sendto\nor\n.I sendmsg\nrequest on a connected socket specified a destination\nwhen already connected.\n.en 57 ENOTCONN \"Socket is not connected\"\nAn request to send or receive data was disallowed because\nthe socket is not connected and (when sending on a  datagram socket)\nno address was supplied.\n.en 58 ESHUTDOWN \"Can't send after socket shutdown\"\nA request to send data was disallowed because the socket\nhad already been shut down with a previous\n.IR shutdown (2)\ncall.\n.en 59 \\fIunused\\fP\n.en 60 ETIMEDOUT \"Connection timed out\"\nA\n.I connect\nor\n.I send\nrequest failed because the connected party did not\nproperly respond after a period of time.  (The timeout\nperiod is dependent on the communication protocol.)\n.en 61 ECONNREFUSED \"Connection refused\"\nNo connection could be made because the target machine actively\nrefused it.  This usually results from trying to connect\nto a service that is inactive on the foreign host.\n.en 62 ELOOP \"Too many levels of symbolic links\"\nA path name lookup involved more than 8 symbolic links.\n.en 63 ENAMETOOLONG \"File name too long\"\nA component of a path name exceeded 255 (MAXNAMELEN) characters, or an entire\npath name exceeded 1023 (MAXPATHLEN-1) characters.\n.en 64 EHOSTDOWN \"Host is down\"\nA socket operation failed because the destination host was down.\n.en 65 EHOSTUNREACH \"Host is unreachable\"\nA socket operation was attempted to an unreachable host.\n.en 66 ENOTEMPTY \"Directory not empty\"\nA directory with entries other than \\*(lq.\\*(rq and \\*(lq..\\*(rq\nwas supplied to a remove directory or rename call.\n...en 67 EPROCLIM \"Too many processes\"\n...en 68 EUSERS \"Too many users\"\n.en 69 EDQUOT \"Disc quota exceeded\"\nA \n.I write\nto an ordinary file, the creation of a\ndirectory or symbolic link, or the creation of a directory\nentry failed because the user's quota of disk blocks was\nexhausted, or the allocation of an inode for a newly\ncreated file failed because the user's quota of inodes\nwas exhausted.\n.SH DEFINITIONS\n.TP 5\nProcess ID\n.br\nEach active process in the system is uniquely identified by a positive\ninteger called a process ID.  The range of this ID is from 0 to 30000.\n.TP 5\nParent process ID\n.br\nA new process is created by a currently active process; (see\n.IR fork (2)).\nThe parent process ID of a process is the process ID of its creator.\n.TP 5\nProcess Group ID\n.br\nEach active process is a member of a process group that is identified by\na positive integer called the process group ID.  This is the process\nID of the group leader.  This grouping permits the signaling of related\nprocesses (see\n.IR killpg (2))\nand the job control mechanisms of\n.IR csh (1).\n.TP 5\nTty Group ID\n.br\nEach active process can be a member of a terminal group that is identified\nby a positive integer called the tty group ID.  This grouping is used\nto arbitrate between multiple jobs contending for the same terminal;\n(see\n.IR csh (1)\nand\n.IR tty (4)).\n.TP 5\nReal User ID and Real Group ID\n.br\nEach user on the system is identified by a positive integer\ntermed the real user ID.\n.IP\nEach user is also a member of one or more groups. \nOne of these groups is distinguished from others and\nused in implementing accounting facilities.  The positive\ninteger corresponding to this distinguished group is termed \nthe real group ID.\n.IP\nAll processes have a real user ID and real group ID.\nThese are initialized from the equivalent attributes\nof the process that created it.\n.TP 5\nEffective User Id, Effective Group Id, and Access Groups\n.br\nAccess to system resources is governed by three values:\nthe effective user ID, the effective group ID, and the\ngroup access list.\n.IP\nThe effective user ID and effective group ID are initially the\nprocess's real user ID and real group ID respectively.  Either\nmay be modified through execution of a set-user-ID or set-group-ID\nfile (possibly by one its ancestors) (see\n.IR execve (2)).\n.IP\nThe group access list is an additional set of group ID's\nused only in determining resource accessibility.  Access checks\nare performed as described below in ``File Access Permissions''.\n.TP 5\nSuper-user\n.br\nA process is recognized as a\n.I super-user\nprocess and is granted special privileges if its effective user ID is 0.\n.TP 5\nSpecial Processes\n.br\nThe processes with a process ID's of 0, 1, and 2 are special.\nProcess 0 is the scheduler.  Process 1 is the initialization process\n.IR init ,\nand is the ancestor of every other process in the system.\nIt is used to control the process structure.\nProcess 2 is the paging daemon.\n.TP 5\nDescriptor\n.br\nAn integer assigned by the system when a file is referenced\nby\n.IR open (2)\nor\n.IR dup (2),\nor when a socket is created by\n.IR pipe (2),\n.IR socket (2)\nor\n.IR socketpair (2),\nwhich uniquely identifies an access path to that file or socket from\na given process or any of its children.\n.TP 5\nFile Name\n.br\nNames consisting of up to 255 (MAXNAMELEN) characters may be used to name\nan ordinary file, special file, or directory.\n.IP\nThese characters may be selected from the set of all ASCII character\nexcluding 0 (null) and the ASCII code for / (slash).  (The parity bit,\nbit 8, must be 0.)\n.IP\nNote that it is generally unwise to use *, ?, [ or ] as part of\nfile names because of the special meaning attached to these characters\nby the shell.\n.TP 5\nPath Name\n.br\nA path name is a null-terminated character string starting with an\noptional slash (/), followed by zero or more directory names separated\nby slashes, optionally followed by a file name.\nThe total length of a path name must be less than 1024 (MAXPATHLEN) characters.\n.IP\nIf a path name begins with a slash, the path search begins at the\n.I root\ndirectory.\nOtherwise, the search begins from the current working directory.\nA slash by itself names the root directory.  A null\npathname refers to the current directory.\n.TP 5\nDirectory\n.br\nA directory is a special type of file that contains entries\nthat are references to other files.\nDirectory entries are called links.  By convention, a directory\ncontains at least two links, . and .., referred to as\n.I dot\nand\n.I dot-dot\nrespectively.  Dot refers to the directory itself and\ndot-dot refers to its parent directory.\n.TP 5\nRoot Directory and Current Working Directory\n.br\nEach process has associated with it a concept of a root directory\nand a current working directory for the purpose of resolving path\nname searches.  A process's root directory need not be the root\ndirectory of the root file system.\n.TP 5\nFile Access Permissions\n.br\nEvery file in the file system has a set of access permissions.\nThese permissions are used in determining whether a process\nmay perform a requested operation on the file (such as opening\na file for writing).  Access permissions are established at the\ntime a file is created.  They may be changed at some later time\nthrough the \n.IR chmod (2)\ncall. \n.IP\nFile access is broken down according to whether a file may be: read,\nwritten, or executed.  Directory files use the execute\npermission to control if the directory may be searched. \n.IP\nFile access permissions are interpreted by the system as\nthey apply to three different classes of users: the owner\nof the file, those users in the file's group, anyone else.\nEvery file has an independent set of access permissions for\neach of these classes.  When an access check is made, the system\ndecides if permission should be granted by checking the access\ninformation applicable to the caller.\n.IP\nRead, write, and execute/search permissions on\na file are granted to a process if:\n.IP\nThe process's effective user ID is that of the super-user.\n.IP\nThe process's effective user ID matches the user ID of the owner\nof the file and the owner permissions allow the access.\n.IP\nThe process's effective user ID does not match the user ID of the\nowner of the file, and either the process's effective\ngroup ID matches the group ID\nof the file, or the group ID of the file is in\nthe process's group access list,\nand the group permissions allow the access.\n.IP\nNeither the effective user ID nor effective group ID\nand group access list of the process\nmatch the corresponding user ID and group ID of the file,\nbut the permissions for ``other users'' allow access.\n.IP\nOtherwise, permission is denied.\n.TP 5\nSockets and Address Families\n.IP\nA socket is an endpoint for communication between processes.\nEach socket has queues for sending and receiving data.\n.IP\nSockets are typed according to their communications properties.\nThese properties include whether messages sent and received\nat a socket require the name of the partner, whether communication\nis reliable, the format used in naming message recipients, etc.\n.IP\nEach instance of the system supports some\ncollection of socket types; consult\n.IR socket (2)\nfor more information about the types available and\ntheir properties.\n.IP\nEach instance of the system supports some number of sets of\ncommunications protocols.  Each protocol set supports addresses\nof a certain format.  An Address Family is the set of addresses\nfor a specific group of protocols.  Each socket has an address\nchosen from the address family in which the socket was created.\n.SH SEE ALSO\nintro(3), perror(3)\n"
  },
  {
    "path": "share/man/man2/ioctl.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ioctl.2\t6.3 (Berkeley) 3/4/86\n.\\\"\n.TH IOCTL 2 \"March 4, 1986\"\n.UC 4\n.SH NAME\nioctl \\- control device\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/ioctl.h>\n.PP\n.ft B\nioctl(d, request, argp)\nint d;\nunsigned long request;\nchar *argp;\n.fi\n.ft R\n.SH DESCRIPTION\n.I Ioctl\nperforms a variety of functions\non open descriptors.  In particular, many operating\ncharacteristics of character special files (e.g. terminals)\nmay be controlled with\n.I ioctl\nrequests.\nThe writeups of various devices in section 4 discuss how\n.I ioctl\napplies to them.\n.PP\nAn  ioctl\n.I request\nhas encoded in it whether the argument is an \\*(lqin\\*(rq parameter\nor \\*(lqout\\*(rq parameter, and the size of the argument \\fIargp\\fP in bytes.\nMacros and defines used in specifying an ioctl\n.I request\nare located in the file\n.IR <sys/ioctl.h> .\n.SH \"RETURN VALUE\nIf an error has occurred, a value of \\-1 is returned and\n.I errno\nis set to indicate the error.\n.SH ERRORS\n.I Ioctl\nwill fail if one or more of the following are true:\n.TP 15\n[EBADF]\n\\fID\\fP is not a valid descriptor.\n.TP 15\n[ENOTTY]\n\\fID\\fP is not associated with a character\nspecial device.\n.TP 15\n[ENOTTY]\nThe specified request does not apply to the kind\nof object that the descriptor \\fId\\fP references.\n.TP 15\n[EINVAL]\n\\fIRequest\\fP or \\fIargp\\fP is not valid.\n.SH \"SEE ALSO\"\nexecve(2), fcntl(2), mt(4), tty(4), intro(4N)\n"
  },
  {
    "path": "share/man/man2/kill.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)kill.2\t6.5 (Berkeley) 5/14/86\n.\\\"\n.TH KILL 2 \"May 14, 1986\"\n.UC 4\n.SH NAME\nkill \\- send signal to a process\n.SH SYNOPSIS\n.ft B\nkill(pid, sig)\n.br\nint pid, sig;\n.SH DESCRIPTION\n.I Kill\nsends the signal \\fIsig\\fP\nto a process, specified by the process number\n.IR pid .\n.I Sig\nmay be one of the signals specified in\n.IR sigvec (2),\nor it may be 0, in which case\nerror checking is performed but no\nsignal is actually sent. \nThis can be used to check the validity of\n.IR pid .\n.PP\nThe sending and receiving processes must\nhave the same effective user ID, otherwise\nthis call is restricted to the super-user.\nA single exception is the signal SIGCONT, which may always be sent\nto any descendant of the current process.\n.PP\nIf the process number is 0,\nthe signal is sent to all processes in the\nsender's process group; this is a variant of\n.IR killpg (2).\n.PP\nIf the process number is \\-1\nand the user is the super-user,\nthe signal is broadcast universally\nexcept to system processes\nand the process sending the signal.\nIf the process number is \\-1\nand the user is not the super-user,\nthe signal is broadcast universally to\nall processes with the same uid as the user\nexcept the process sending the signal.\nNo error is returned if any process could be signaled.\n.PP\nFor compatibility with System V,\nif the process number is negative but not \\-1,\nthe signal is sent to all processes whose process group ID\nis equal to the absolute value of the process number.\nThis is a variant of\n.IR killpg (2).\n.PP\nProcesses may send signals to themselves.\n.SH \"RETURN VALUE\nUpon successful completion, a value of 0 is returned.\nOtherwise, a value of \\-1 is returned and\n.I errno\nis set to indicate the error.\n.SH \"ERRORS\n.I Kill\nwill fail and no signal will be sent if any of the following\noccur:\n.TP 15\n[EINVAL]\n\\fISig\\fP is not a valid signal number.\n.TP 15\n[ESRCH]\nNo process can be found corresponding to that specified by \\fIpid\\fP.\n.TP 15\n[ESRCH]\nThe process id was given as 0\nbut the sending process does not have a process group.\n.TP 15\n[EPERM]\nThe sending process is not the super-user and its effective\nuser id does not match the effective user-id of the receiving process.\nWhen signaling a process group, this error was returned if any members\nof the group could not be signaled.\n.SH \"SEE ALSO\"\ngetpid(2), getpgrp(2), killpg(2), sigvec(2)\n"
  },
  {
    "path": "share/man/man2/killpg.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)killpg.2\t6.3 (Berkeley) 5/14/86\n.\\\"\n.TH KILLPG 2 \"May 14, 1986\"\n.UC 4\n.SH NAME\nkillpg \\- send signal to a process group\n.SH SYNOPSIS\n.ft B\nkillpg(pgrp, sig)\n.br\nint pgrp, sig;\n.ft R\n.SH DESCRIPTION\n.I Killpg\nsends the signal\n.I sig\nto the process group\n.IR pgrp .\nSee\n.IR sigvec (2)\nfor a list of signals.\n.PP\nThe sending process and members of the process group must\nhave the same effective user ID, or\nthe sender must be the super-user.\nAs a single special case the continue signal SIGCONT may be sent\nto any process that is a descendant of the current process.\n.SH \"RETURN VALUE\nUpon successful completion, a value of 0 is returned.  Otherwise,\na value of \\-1 is returned and the global variable \\fIerrno\\fP\nis set to indicate the error.\n.SH \"ERRORS\n\\fIKillpg\\fP will fail and no signal will be sent if any of the\nfollowing occur:\n.TP 15\n[EINVAL]\n\\fISig\\fP is not a valid signal number.\n.TP 15\n[ESRCH]\nNo process can be found in the process group specified by \\fIpgrp\\fP.\n.TP 15\n[ESRCH]\nThe process group was given as 0\nbut the sending process does not have a process group.\n.TP 15\n[EPERM]\nThe sending process is not the super-user and one or more\nof the target processes has an effective user ID different from that\nof the sending process.\n.SH \"SEE ALSO\"\nkill(2), getpgrp(2), sigvec(2)\n"
  },
  {
    "path": "share/man/man2/link.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)link.2\t6.3 (Berkeley) 8/26/85\n.\\\"\n.TH LINK 2 \"August 26, 1985\"\n.UC 4\n.SH NAME\nlink \\- make a hard link to a file\n.SH SYNOPSIS\n.nf\n.ft B\nlink(name1, name2)\nchar *name1, *name2;\n.fi\n.ft R\n.SH DESCRIPTION\nA hard link\nto\n.I name1\nis created;\nthe link has the name\n.IR name2 .\n.I Name1\nmust exist.\n.PP\nWith hard links,\nboth\n.I name1\nand\n.I name2\nmust be in the same file system.\nUnless the caller is the super-user,\n.I name1\nmust not be a directory.\nBoth the old and the new\n.I link\nshare equal access and rights to\nthe underlying object.\n.SH \"RETURN VALUE\nUpon successful completion, a value of 0 is returned.  Otherwise,\na value of \\-1 is returned and\n.I errno\nis set to indicate the error.\n.SH \"ERRORS\n.I Link\nwill fail and no link will be created if one or more of the following\nare true:\n.TP 15\n[ENOTDIR]\nA component of either path prefix is not a directory.\n.TP 15\n[EINVAL]\nEither pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of either pathname exceeded 255 characters,\nor entire length of either path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nA component of either path prefix does not exist.\n.TP 15\n[EACCES]\nA component of either path prefix denies search permission.\n.TP 15\n[EACCES]\nThe requested link requires writing in a directory with a mode\nthat denies write permission.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating one of the pathnames.\n.TP 15\n[ENOENT]\nThe file named by \\fIname1\\fP does not exist.\n.TP 15\n[EEXIST]\nThe link named by \\fIname2\\fP does exist.\n.TP 15\n[EPERM]\nThe file named by \\fIname1\\fP is a directory and the effective\nuser ID is not super-user.\n.TP 15\n[EXDEV]\nThe link named by \\fIname2\\fP and the file named by \\fIname1\\fP\nare on different file systems.\n.TP 15\n[ENOSPC]\nThe directory in which the entry for the new link is being placed\ncannot be extended because there is no space left on the file\nsystem containing the directory.\n.TP 15\n[EDQUOT]\nThe directory in which the entry for the new link\nis being placed cannot be extended because the\nuser's quota of disk blocks on the file system\ncontaining the directory has been exhausted.\n.TP 15\n[EIO]\nAn I/O error occurred while reading from or writing to \nthe file system to make the directory entry.\n.TP 15\n[EROFS]\nThe requested link requires writing in a directory on a read-only file\nsystem.\n.TP 15\n[EFAULT]\nOne of the pathnames specified\nis outside the process's allocated address space.\n.SH \"SEE ALSO\"\nsymlink(2), unlink(2)\n"
  },
  {
    "path": "share/man/man2/listen.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)listen.2\t6.2 (Berkeley) 5/14/86\n.\\\"\n.TH LISTEN 2 \"May 14, 1986\"\n.UC 5\n.SH NAME\nlisten \\- listen for connections on a socket\n.SH SYNOPSIS\n.nf\n.ft B\nlisten(s, backlog)\nint s, backlog;\n.fi\n.SH DESCRIPTION\nTo accept connections, a socket\nis first created with\n.IR socket (2),\na willingness to accept incoming connections and\na queue limit for incoming connections are specified with\n.IR listen (2),\nand then the connections are\naccepted with\n.IR accept (2).\nThe\n.I listen\ncall applies only to sockets of type\nSOCK_STREAM\nor\nSOCK_SEQPACKET.\n.PP\nThe\n.I backlog\nparameter defines the maximum length the queue of\npending connections may grow to.\nIf a connection\nrequest arrives with the queue full the client may\nreceive an error with an indication of ECONNREFUSED,\nor, if the underlying protocol supports retransmission,\nthe request may be ignored so that retries may succeed.\n.SH \"RETURN VALUE\nA 0 return value indicates success; \\-1 indicates an error.\n.SH \"ERRORS\nThe call fails if:\n.TP 20\n[EBADF]\nThe argument \\fIs\\fP is not a valid descriptor.\n.TP 20\n[ENOTSOCK]\nThe argument \\fIs\\fP is not a socket.\n.TP 20\n[EOPNOTSUPP]\nThe socket is not of a type that supports the operation \\fIlisten\\fP.\n.SH \"SEE ALSO\"\naccept(2), connect(2), socket(2)\n.SH BUGS\nThe\n.I backlog\nis currently limited (silently) to 5.\n"
  },
  {
    "path": "share/man/man2/lock.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)lock.2\t2.3 (Berkeley) 1/22/87\n.\\\"\n.TH LOCK 2 \"January 22, 1987\"\n.UC 2\n.SH NAME\nlock \\- lock a process in primary memory (2BSD)\n.SH SYNOPSIS\n.nf\n.ft B\nlock(flag)\nint flag\n.fi\n.ft R\n.SH DESCRIPTION\nIf the\n.I flag\nargument is non-zero,\nthe process executing this call\nwill not be swapped unless it is required to grow.\nIf the argument is zero,\nthe process is\n.RI un lock ed.\nThis call may only be executed by\nthe super-user.\n.SH ERRORS\n.TP 15\n[EPERM]\nThe caller is not the super-user.\n.SH BUGS\n.IR Lock ed\nprocesses interfere with the compaction of primary memory\nand can cause deadlock.\nThis system call is not considered\na permanent part of the system.\n.PP\n.I Lock\nis unique to the PDP-11 and 2BSD; its use is discouraged.\n"
  },
  {
    "path": "share/man/man2/lseek.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)lseek.2\t6.3 (Berkeley) 2/24/86\n.\\\"\n.TH LSEEK 2 \"February 24, 1986\"\n.UC 4\n.SH NAME\nlseek \\- move read/write pointer\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/file.h>\n.PP\n.nf\n.ft B\n.ta 1.25i 1.6i 1.8i\n#define L_SET\t0\t/* set the seek pointer */\n#define L_INCR\t1\t/* increment the seek pointer */\n#define L_XTND\t2\t/* extend the file size */\n.PP\n.ft B\npos = lseek(d, offset, whence)\noff_t pos;\nint d;\noff_t offset;\nint whence;\n.fi\n.ft R\n.SH DESCRIPTION\nThe descriptor \n.I d\nrefers to a file or device open for reading and/or writing.\n.I Lseek\nsets the file pointer of\n.I d\nas follows:\n.IP\nIf\n.I whence\nis L_SET, the pointer is set to\n.I offset\nbytes.\n.IP\nIf\n.I whence\nis L_INCR, the pointer is set to its current location plus\n.IR offset .\n.IP\nIf\n.I whence\nis L_XTND, the pointer is set to the size of the\nfile plus\n.IR offset .\n.PP\nUpon successful completion, the resulting pointer location\nas measured in bytes from beginning of the file is returned.\nSome devices are incapable of seeking.  The value of the pointer\nassociated with such a device is undefined.\n.SH NOTES\nSeeking far beyond the end of a file, then writing,\ncreates a gap or \\*(lqhole\\*(rq, which occupies no\nphysical space and reads as zeros.\n.SH \"RETURN VALUE\nUpon successful completion,\nthe current file pointer value is returned.\nOtherwise,\na value of \\-1 is returned and \\fIerrno\\fP is set to indicate\nthe error.\n.SH \"ERRORS\n.I Lseek\nwill fail and the file pointer will remain unchanged if:\n.TP 15\n[EBADF]\n.I Fildes\nis not an open file descriptor.\n.TP 15\n[ESPIPE]\n.I Fildes\nis associated with a pipe or a socket.\n.TP 15\n[EINVAL]\n.I Whence\nis not a proper value.\n.SH \"SEE ALSO\"\ndup(2), open(2)\n.SH BUGS\nThis document's use of\n.I whence\nis incorrect English, but maintained for historical reasons.\n"
  },
  {
    "path": "share/man/man2/mkdir.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)mkdir.2\t6.4 (Berkeley) 8/26/85\n.\\\"\n.TH MKDIR 2 \"August 26, 1985\"\n.UC 5\n.SH NAME\nmkdir \\- make a directory file\n.SH SYNOPSIS\n.nf\n.ft B\nmkdir(path, mode)\nchar *path;\nint mode;\n.fi\n.ft R\n.SH DESCRIPTION\n.I Mkdir\ncreates a new directory file with name\n.IR path .\nThe mode of the new file\nis initialized from\n.IR mode .\n(The protection part of the mode\nis modified by the process's mode mask; see\n.IR umask (2)).\n.PP\nThe directory's owner ID is set to the process's effective user ID.\nThe directory's group ID is set to that of the parent directory in\nwhich it is created.\n.PP\nThe low-order 9 bits of mode are modified by the process's\nfile mode creation mask: all bits set in the process's file mode\ncreation mask are cleared.  See\n.IR umask (2).\n.SH \"RETURN VALUE\nA 0 return value indicates success.  A \\-1 return value\nindicates an error, and an error code is stored in\n.I errno.\n.SH \"ERRORS\n.I Mkdir\nwill fail and no directory will be created if:\n.TP 15\n[ENOTDIR]\nA component of the path prefix is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 255 characters,\nor an entire path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nA component of the path prefix does not exist.\n.TP 15\n[EACCES]\nSearch permission is denied for a component of the path prefix.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[EPERM]\nThe \\fIpath\\fP argument contains a byte with the high-order bit set.\n.TP 15\n[EROFS]\nThe named file resides on a read-only file system.\n.TP 15\n[EEXIST]\nThe named file exists.\n.TP 15\n[ENOSPC]\nThe directory in which the entry for the new directory is being placed\ncannot be extended because there is no space left on the file\nsystem containing the directory.\n.TP 15\n[ENOSPC]\nThe new directory cannot be created because there\nthere is no space left on the file\nsystem that will contain the directory.\n.TP 15\n[ENOSPC]\nThere are no free inodes on the file system on which the\ndirectory is being created.\n.TP 15\n[EDQUOT]\nThe directory in which the entry for the new directory\nis being placed cannot be extended because the\nuser's quota of disk blocks on the file system\ncontaining the directory has been exhausted.\n.TP 15\n[EDQUOT]\nThe new directory cannot be created because the user's\nquota of disk blocks on the file system that will\ncontain the directory has been exhausted.\n.TP 15\n[EDQUOT]\nThe user's quota of inodes on the file system on\nwhich the directory is being created has been exhausted.\n.TP 15\n[EIO]\nAn I/O error occurred while making the directory entry or allocating the inode.\n.TP 15\n[EIO]\nAn I/O error occurred while reading from or writing to the file system.\n.TP 15\n[EFAULT]\n.I Path\npoints outside the process's allocated address space.\n.SH \"SEE ALSO\"\nchmod(2), stat(2), umask(2)\n"
  },
  {
    "path": "share/man/man2/mknod.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)mknod.2\t6.4 (Berkeley) 5/23/86\n.\\\"\n.TH MKNOD 2 \"May 23, 1986\"\n.UC 4\n.SH NAME\nmknod \\- make a special file\n.SH SYNOPSIS\n.nf\n.ft B\nmknod(path, mode, dev)\nchar *path;\nint mode, dev;\n.fi\n.ft R\n.SH DESCRIPTION\n.I Mknod\ncreates a new file\nwhose name is\n.I path.\nThe mode of the new file\n(including special file bits)\nis initialized from\n.IR mode .\n(The protection part of the mode\nis modified by the process's mode mask (see\n.IR umask (2))).\nThe first block pointer of the i-node\nis initialized from\n.I dev \nand is used to specify which device the special file\nrefers to.\n.PP\nIf mode indicates a block or character special file,\n.I dev\nis a configuration dependent specification of a character or block\nI/O device.  If\n.I mode\ndoes not indicate a block special or character special device,\n.I dev\nis ignored.\n.PP\n.I Mknod\nmay be invoked only by the super-user.\n.SH \"RETURN VALUE\nUpon successful completion a value of 0 is returned.\nOtherwise, a value of \\-1 is returned and \\fIerrno\\fP\nis set to indicate the error.\n.SH ERRORS\n.I Mknod\nwill fail and the file mode will be unchanged if:\n.TP 15\n[ENOTDIR]\nA component of the path prefix is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 255 characters,\nor an entire path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nA component of the path prefix does not exist.\n.TP 15\n[EACCES]\nSearch permission is denied for a component of the path prefix.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[EPERM]\nThe process's effective user ID is not super-user.\n.TP 15\n[EPERM]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[EIO]\nAn I/O error occurred while making the directory entry or allocating the inode.\n.TP 15\n[ENOSPC]\nThe directory in which the entry for the new node is being placed\ncannot be extended because there is no space left on the file\nsystem containing the directory.\n.TP 15\n[ENOSPC]\nThere are no free inodes on the file system on which the\nnode is being created.\n.TP 15\n[EDQUOT]\nThe directory in which the entry for the new node\nis being placed cannot be extended because the\nuser's quota of disk blocks on the file system\ncontaining the directory has been exhausted.\n.TP 15\n[EDQUOT]\nThe user's quota of inodes on the file system on\nwhich the node is being created has been exhausted.\n.TP 15\n[EROFS]\nThe named file resides on a read-only file system.\n.TP 15\n[EEXIST]\nThe named file exists.\n.TP 15\n[EFAULT]\n.I Path\npoints outside the process's allocated address space.\n.SH \"SEE ALSO\"\nchmod(2), stat(2), umask(2)\n"
  },
  {
    "path": "share/man/man2/mount.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)mount.2\t6.3.1 (2.11BSD) 1996/1/25\n.\\\"\n.TH MOUNT 2 \"January 25, 1996\"\n.UC 4\n.SH NAME\nmount, umount \\- mount or remove file system\n.SH SYNOPSIS\n.nf\n.ft B\nmount(special, name, flags)\nchar *special, *name;\nint flags;\n.PP\n.ft B\numount(special)\nchar *special;\n.fi\n.SH DESCRIPTION\n.I Mount\nannounces to the system that a removable file system has\nbeen mounted on\nthe block-structured special file\n.I special;\nfrom now on, references to file\n.I name\nwill refer to\nthe root file on the newly mounted file system.\n.I Special\nand\n.I name\nare pointers to null-terminated strings\ncontaining the appropriate path names.\n.PP\n.I Name\nmust exist already. \n.I Name\nmust be a directory.\nIts old contents\nare inaccessible while the file system\nis mounted.\n.PP\nThe following\n.I flags\nmay be specified to suppress default semantics which\naffect filesystem access.\n.TP 20\nMNT_RDONLY\nThe filesystem should be treated as read-only; Even the \nsuper-user may not write on it.\n.TP 20\nMNT_NOEXEC\nDo not allow files to be executed from the filesystem.\n.TP 20\nMNT_NOSUID\nDo not honor setuid or setgid bits on files when executing them.\n.TP 20\nMNT_NODEV\nDo not interpret special files on the filesystem.\n.TP 20\nMNT_SYNCHRONOUS\nAll I/O to the filesystem should be done synchronously.\n.PP\n.I Umount\nannounces to the system that the\n.I special\nfile is no longer to contain a removable file system.\nThe associated file reverts to its ordinary interpretation.\n.SH \"RETURN VALUE\n.I Mount\nreturns 0 if the action occurred, \\-1 if\n.I special\nis inaccessible or not an appropriate file, if\n.I name\ndoes not exist, if\n.I special\nis already mounted, if\n.I name\nis in use, or if\nthere are already too many\nfile systems mounted.\n.PP\n.I Umount\nreturns 0 if the action occurred; \\-1 if\nif the special file is inaccessible or\ndoes not have a mounted file system,\nor if there are active files in the mounted \nfile system.\n.SH ERRORS\n.I Mount\nwill fail when one of the following occurs:\n.TP 15\n[ENAMETOOLONG]\nA component of either pathname exceeded 255 characters,\nor the entire length of either path name exceeded 1023 characters.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating either pathname.\n.TP 15\n[EPERM]\nThe caller is not the super-user.\n.TP 15\n[ENOENT]\nA component of \\fIname\\fP does not exist.\n.TP 15\n[ENODEV]\nA component of \\fIspecial\\fP does not exist.\n.TP 15\n[ENOTBLK]\n.I Special\nis not a block device.\n.TP 15\n[ENXIO]\nThe major device number of \n.I special\nis out of range (this indicates no device driver exists\nfor the associated hardware).\n.TP 15\n[ENOTDIR]\nA component of \\fIname\\fP is not a directory,\nor a path prefix of \\fIspecial\\fP is not a directory.\n.TP 15\n[EINVAL]\nEither pathname contains a character with the high-order bit set.\n.TP 15\n[EINVAL]\nThe super block for the file system had a bad magic\nnumber or an out of range block size.\n.TP 15\n[EBUSY]\nAnother process currently holds a reference to\n.IR name ,\nor \\fIspecial\\fP is already mounted.\n.TP 15\n[EMFILE]\nNo space remains in the mount table.\n.TP 15\n[ENOMEM]\nNot enough memory was available to read the cylinder\ngroup information for the file system.\n.TP 15\n[EIO]\nAn I/O error occurred while reading the super block or\ncylinder group information.\n.TP 15\n[EFAULT]\n\\fISpecial\\fP or \\fIname\\fP points outside the\nprocess's allocated address space.\n.PP\n.I Umount\nmay fail with one of the following errors:\n.TP 15\n[ENOTDIR]\nA component of the path prefix is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 255 characters,\nor an entire path name exceeded 1023 characters.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[EPERM]\nThe caller is not the super-user.\n.TP 15\n[ENODEV]\n.I Special\ndoes not exist.\n.TP 15\n[ENOTBLK]\n.I Special\nis not a block device.\n.TP 15\n[ENXIO]\nThe major device number of \n.I special\nis out of range (this indicates no device driver exists\nfor the associated hardware).\n.TP 15\n[EINVAL]\nThe requested device is not in the mount table.\n.TP 15\n[EBUSY]\nA process is holding a reference to a file located\non the file system.\n.TP 15\n[EIO]\nAn I/O error occurred while writing the super block or\nother cached file system information.\n.TP 15\n[EFAULT]\n\\fISpecial\\fP points outside the process's allocated address space.\n.SH \"SEE ALSO\"\nmount(8), umount(8)\n.SH BUGS\nSome of the error codes need translation to more obvious messages.\n.PP\nPhysically write-protected and magnetic\ntape file systems must be mounted read-only or\nerrors will occur when access times are updated,\nwhether or not any\nexplicit write is attempted.\n.PP\nMNT_SYNCHRONOUS is not currently implemented in the kernel but may be\nspecified because the kernel ignores it.\n"
  },
  {
    "path": "share/man/man2/nostk.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)nostk.2\t2.3 (Berkeley) 6/24/87\n.\\\"\n.TH NOSTK 2 \"June 24, 1987\"\n.UC 2\n.SH NAME\nnostk \\- allow process to manage its own stack (2BSD)\n.SH SYNOPSYS\n.B nostk();\n.SH DESCRIPTION\n.I Nostk\ninforms the system that the process\nwishes to manage its own stack.\nThe system releases the stack segment(s)\nit has reserved, making\nthem available for allocation\n(via\n.IR brk (2))\nby the user.\n.PP\nC programs should use\n.I nostk\nonly with great caution and understanding\nof the C language calling and stack\nconventions.\nIt is most useful for assembler programs\nthat want to use the entire available\naddress space.\n.SH \"SEE ALSO\"\nstack(5)\n.SH BUGS\n.I Nostk\nis unique to the PDP-11 and 2BSD; its use is discouraged.\n"
  },
  {
    "path": "share/man/man2/open.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)open.2\t6.4.1 (2.11BSD GTE) 11/30/94\n.\\\"\n.TH OPEN 2 \"Nov 30, 1994\"\n.UC 4\n.SH NAME\nopen \\- open a file for reading or writing, or create a new file\n.SH SYNOPSIS\n.nf\n.ft B\n#include <fcntl.h>\n.PP\n.ft B\nopen(path, flags, mode)\nchar *path;\nint flags, mode;\n.fi\n.SH DESCRIPTION\n.I Open\nopens the file\n.I path\nfor reading and/or writing, as specified by the\n.I flags\nargument and returns a descriptor for that file.\nThe\n.I flags\nargument may indicate the file is to be\ncreated if it does not already exist (by specifying the\nO_CREAT flag), in which case the file is created with mode\n.I mode\nas described in\n.IR chmod (2)\nand modified by the process' umask value (see\n.IR umask (2)).\n.PP\n.I Path\nis the address of a string of ASCII characters representing\na path name, terminated by a null character.\nThe flags specified are formed by\n.IR or 'ing\nthe following values\n.PP\n.RS\n O_RDONLY\topen for reading only\n O_WRONLY\topen for writing only\n O_RDWR\topen for reading and writing\n O_NONBLOCK\tdo not block on open\n O_APPEND\tappend on each write\n O_CREAT\tcreate file if it does not exist\n O_TRUNC\ttruncate size to 0\n O_EXCL\terror if create and file exists\n O_NOCTTY\tdo not acquire as controlling terminal\n O_SHLOCK\tatomically obtain a shared lock\n O_EXLOCK\tatomically obtain an exclusive lock\n.RE\n.PP\nOpening a file with O_APPEND set causes each write on the file\nto be appended to the end.  If O_TRUNC is specified and the\nfile exists, the file is truncated to zero length.\nIf O_EXCL is set with O_CREAT, then if the file already\nexists, the open returns an error.  This can be used to\nimplement a simple exclusive access locking mechanism.\nIf O_EXCL is set and the last component of the pathname is\na symbolic link, the open will fail even if the symbolic\nlink points to a non-existent name.\nIf the O_NONBLOCK flag is specified and the open call would result\nin the process being blocked for some reason (e.g. waiting for\ncarrier on a dialup line), the open returns immediately. \nThe first time the process attempts to perform i/o on the open\nfile it will block.\n.PP\nThe flag O_NOCTTY indicates that even if the file is a terminal device,\nthe call should not result in acquiring the terminal device as the \ncontrolling terminal of the caller.  This flag is not the default and\nis currently unimplemented (it will be Real Soon Now).\n.PP\nWhen opening a file, a lock with \n.IR flock(2)\nsemantics can be obtained by\nsetting O_SHLOCK for a shared lock, or O_EXLOCK for an exclusive lock.\nIf creating a file with O_CREAT, the request for the lock will never\nfail.\n.PP\nUpon successful completion a non-negative integer termed a\nfile descriptor is returned.\nThe file pointer used to mark the current position within the\nfile is set to the beginning of the file.\n.PP\nThe new descriptor is set to remain open across\n.IR execve\nsystem calls; see\n.IR close (2).\n.PP\nThe system imposes a limit on the number of file descriptors\nopen simultaneously by one process.\n.IR Getdtablesize (2)\nreturns the current system limit.\n.SH \"ERRORS\nThe named file is opened unless one or more of the\nfollowing are true:\n.TP 15\n[ENOTDIR]\nA component of the path prefix is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 255 characters,\nor an entire path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nO_CREAT is not set and the named file does not exist.\n.TP 15\n[ENOENT]\nA component of the path name that must exist does not exist.\n.TP 15\n[EACCES]\nSearch permission is denied for a component of the path prefix.\n.TP 15\n[EACCES]\nThe required permissions (for reading and/or writing)\nare denied for the named flag.\n.TP 15\n[EACCES]\nO_CREAT is specified,\nthe file does not exist,\nand the directory in which it is to be created\ndoes not permit writing.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[EISDIR]\nThe named file is a directory, and the arguments specify\nit is to be opened for writting.\n.TP 15\n[EROFS]\nThe named file resides on a read-only file system,\nand the file is to be modified.\n.TP 15\n[EMFILE]\nThe system limit for open file descriptors per process has already been reached.\n.TP 15\n[ENFILE]\nThe system file table is full.\n.TP 15\n[ENXIO]\nThe named file is a character special or block\nspecial file, and the device associated with this special file\ndoes not exist.\n.TP 15\n[ENOSPC]\nO_CREAT is specified,\nthe file does not exist,\nand the directory in which the entry for the new file is being placed\ncannot be extended because there is no space left on the file\nsystem containing the directory.\n.TP 15\n[ENOSPC]\nO_CREAT is specified,\nthe file does not exist,\nand there are no free inodes on the file system on which the\nfile is being created.\n.TP 15\n[EDQUOT]\nO_CREAT is specified,\nthe file does not exist,\nand the directory in which the entry for the new fie\nis being placed cannot be extended because the\nuser's quota of disk blocks on the file system\ncontaining the directory has been exhausted.\n.TP 15\n[EDQUOT]\nO_CREAT is specified,\nthe file does not exist,\nand the user's quota of inodes on the file system on\nwhich the file is being created has been exhausted.\n.TP 15\n[EIO]\nAn I/O error occurred while making the directory entry or\nallocating the inode for O_CREAT.\n.TP 15\n[ETXTBSY]\nThe file is a pure procedure (shared text) file that is being\nexecuted and the \\fIopen\\fP call requests write access.\n.TP 15\n[EFAULT]\n.I Path\npoints outside the process's allocated address space.\n.TP 15\n[EEXIST]\nO_CREAT and O_EXCL were specified and the file exists.\n.TP 15\n[EOPNOTSUPP]\nAn attempt was made to open a socket (not currently implemented).\n.SH \"SEE ALSO\"\nchmod(2), close(2), dup(2), getdtablesize(2),\nlseek(2), read(2), write(2), umask(2)\n"
  },
  {
    "path": "share/man/man2/phys.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)phys.2\t2.3 (Berkeley) 1/22/87\n.\\\"\n.TH PHYS 2 \"January 22, 1987\"\n.UC 2\n.SH NAME\nphys \\- allow a process to access physical addresses (2BSD)\n.SH SYNOPSIS\n.nf\n.ft B\nphys(segreg, size, physaddr)\nunsigned int segreg, size, physaddr;\n.fi\n.ft R\n.SH DESCRIPTION\nThe argument\n.I segreg\nspecifies a process virtual (data-space) address\nrange of 8K bytes starting\nat virtual address\n.IR segreg \\(mu8K\nbytes.\nThis address range is mapped into\nphysical address\n.IR physaddr \\(mu64\nbytes.\nOnly the first\n.IR size \\(mu64\nbytes of this mapping is addressable.\nIf\n.I size\nis zero,\nany previous mapping of this\nvirtual address range is nullified.\nFor example,\nthe call\n.PP\n\tphys(7, 1, 0177775);\n.PP\nwill map virtual addresses 0160000-0160077 into\nphysical addresses 017777500-017777577.\nIn particular,\nvirtual address 0160060 is the PDP-11 console\nlocated at physical address 017777560.\n.PP\nThis call may only be executed by the super-user.\n.SH ERRORS\n.TP 15\n[EPERM]\nThe process's effective user ID is not the super-user.\n.TP 15\n[EINVAL]\n.I Segreg\nis less than 0 or greater than 7.\n.TP 15\n[EINVAL]\n.I Size\nis less than 0 or greater than 128.\n.SH \"SEE ALSO\"\nPDP-11 segmentation hardware\n.SH BUGS\n.PP\nOn systems with ENABLE/34(tm) memory mapping boards,\n\\fIphys\\fP cannot be used to map in the I/O page.\n.PP\nThis system call is very dangerous.\nIt is not considered\na permanent part of the system.\n.PP\n.I Phys\nis unique to the PDP-11 and 2BSD; its use is discouraged.\n"
  },
  {
    "path": "share/man/man2/pipe.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)pipe.2\t6.2 (Berkeley) 8/26/85\n.\\\"\n.TH PIPE 2 \"August 26, 1985\"\n.UC 4\n.SH NAME\npipe \\- create an interprocess communication channel\n.SH SYNOPSIS\n.nf\n.ft B\npipe(fildes)\nint fildes[2];\n.fi\n.ft R\n.SH DESCRIPTION\nThe\n.I pipe\nsystem call\ncreates an I/O mechanism called a pipe.\nThe file descriptors returned can\nbe used in read and write operations.\nWhen the pipe is written using the descriptor\n.IR fildes [1]\nup to 4096 bytes of data are buffered\nbefore the writing process is suspended.\nA read using the descriptor\n.IR fildes [0]\nwill pick up the data.\n.PP\nIt is assumed that after the\npipe has been set up,\ntwo (or more)\ncooperating processes\n(created by subsequent\n.I fork\ncalls)\nwill pass data through the\npipe with\n.I read\nand\n.I write\ncalls.\n.PP\nThe shell has a syntax\nto set up a linear array of processes\nconnected by pipes.\n.PP\nRead calls on an empty\npipe (no buffered data) with only one end\n(all write file descriptors closed)\nreturns an end-of-file.\n.PP\nPipes are really a special case of the \n.IR socketpair (2)\ncall and, in fact, are implemented as such in the system.\n.PP\nA signal is generated if a write on a pipe with only one end is attempted.\n.SH \"RETURN VALUE\nThe function value zero is returned if the\npipe was created; \\-1 if an error occurred.\n.SH ERRORS\nThe \\fIpipe\\fP call will fail if:\n.TP 15\n[EMFILE]\nToo many descriptors are active.\n.TP 15\n[ENFILE]\nThe system file table is full.\n.TP 15\n[EFAULT]\nThe \\fIfildes\\fP buffer is in an invalid area of the process's address\nspace.\n.SH \"SEE ALSO\"\nsh(1), read(2), write(2), fork(2), socketpair(2)\n.SH BUGS\nShould more than 4096 bytes be necessary in any\npipe among a loop of processes, deadlock will occur.\n"
  },
  {
    "path": "share/man/man2/profil.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)profil.2\t6.3 (Berkeley) 5/6/87\n.\\\"\n.TH PROFIL 2 \"May 6, 1987\"\n.UC 2\n.SH NAME\nprofil \\- execution time profile\n.SH SYNOPSIS\n.nf\n.B profil(buff, bufsiz, offset, scale)\n.B char *buff;\n.B int bufsiz, offset, scale;\n.fi\n.SH DESCRIPTION\n.I Buff\npoints to an area of core whose length (in bytes) is given by\n.IR bufsiz .\nAfter this call, the user's program counter (pc)\nis examined each clock tick\n(VAX and TAHOE: 100 ticks/second = 10 milliseconds per tick;\n60 ticks/second ~= 16 milliseconds per tick);\n.I offset\nis subtracted from it, and the result multiplied by\n.IR scale .\nIf the resulting number corresponds to a word\ninside\n.I buff,\nthat word is incremented.\n.PP\nThe scale is interpreted as an unsigned,\nfixed-point fraction with 16 bits of fraction:\n0xffff gives a 1-1 mapping of pc's to words\nin\n.I buff;\n0x7fff maps each pair of instruction words\ntogether.\n.PP\nProfiling is turned off by giving a\n.I scale\nof 0 or 1.\nIt is rendered\nineffective by giving a\n.I bufsiz\nof 0.\nProfiling is turned off when an\n.I execve\nis executed, but remains on in child and parent both\nafter a\n.IR fork .\nProfiling is turned off if an update in\n.I buff\nwould cause a memory fault.\n.SH \"RETURN VALUE\nA 0, indicating success, is always returned.\n.SH \"SEE ALSO\"\ngprof(1), prof(1), setitimer(2), monitor(3)\n"
  },
  {
    "path": "share/man/man2/ptrace.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ptrace.2\t6.4 (Berkeley) 5/23/86\n.\\\"\n.TH PTRACE 2 \"May 23, 1986\"\n.UC 4\n.SH NAME\nptrace \\- process trace\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/signal.h>\n#include <sys/ptrace.h>\n.PP\n.ft B\nptrace(request, pid, addr, data)\nint request, pid, *addr, data;\n.fi\n.SH DESCRIPTION\n.I Ptrace\nprovides a means by which a parent process\nmay control the execution of a child process,\nand examine and change its core image.\nIts primary use is for the implementation of breakpoint debugging.\nThere are four arguments whose interpretation\ndepends on a\n.I request\nargument.\nGenerally,\n.I pid\nis the process ID of the traced process,\nwhich must be a child (no more distant descendant)\nof the tracing process.\nA process being traced\nbehaves normally until it encounters some signal\nwhether internally generated\nlike \\*(lqillegal instruction\\*(rq or externally\ngenerated like \\*(lqinterrupt\\*(rq.\nSee\n.IR sigvec (2)\nfor the list.\nThen the traced process enters a stopped state\nand its parent is notified via\n.IR  wait (2).\nWhen the child is in the stopped state,\nits core image can be examined and modified\nusing\n.IR ptrace .\nIf desired, another\n.I ptrace\nrequest can then cause the child either to terminate\nor to continue, possibly ignoring the signal.\n.PP\nThe value of the\n.I request\nargument determines the precise\naction of the call:\n.TP 4\nPT_TRACE_ME\nThis request is the only one used by the child process;\nit declares that the process is to be traced by its parent.\nAll the other arguments are ignored.\nPeculiar results will ensue\nif the parent does not expect to trace the child.\n.TP 4\nPT_READ_I, PT_READ_D\nThe\nword in the child process's address space\nat\n.I addr\nis returned.\nIf I and D space are separated (e.g. historically\non a pdp-11), request PT_READ_I indicates I space,\nPT_READ_D D space.\n.I Addr\nmust be even on some machines.\nThe child must be stopped.\nThe input\n.I data\nis ignored.\n.TP 4\nPT_READ_U\nThe word\nof the system's per-process data area corresponding to\n.I addr\nis returned.\n.I Addr\nmust be even on some machines and less than 512.\nThis space contains the registers and other information about\nthe process;\nits layout corresponds to the\n.I user\nstructure in the system.\n.TP 4\nPT_WRITE_I, PT_WRITE_D\nThe\ngiven\n.I data\nis written at the word in the process's address space corresponding to\n.I addr,\nwhich must be even on some machines.\nNo useful value is returned.\nIf I and D space are separated, request PT_WRITE_I indicates I space, \nPT_WRITE_D D space.\nAttempts to write in pure procedure\nfail if another process is executing the same file.\n.TP 4\nPT_WRITE_U\nThe process's system data is written,\nas it is read with request PT_READ_U.\nOnly a few locations can be written in this way:\nthe general registers,\nthe floating point status and registers,\nand certain bits of the processor status word.\n.TP 4\nPT_CONTINUE\nThe\n.I data\nargument is taken as a signal number\nand the child's execution continues\nat location\n.I addr\nas if it had incurred that signal.\nNormally the signal number will be\neither 0 to indicate that the signal that caused the stop\nshould be ignored,\nor that value fetched out of the\nprocess's image indicating which signal caused\nthe stop.\nIf\n.I addr\nis (int *)1 then execution continues from where it stopped.\n.TP 4\nPT_KILL\nThe traced process terminates.\n.TP 4\nPT_STEP\nExecution continues as in request PT_CONTINUE;\nhowever, as soon as possible after execution of at least one instruction,\nexecution stops again.\nThe signal number from the stop is\nSIGTRAP.\n(On the VAX-11 the T-bit is used and just one instruction\nis executed.)\nThis is part of the mechanism for implementing breakpoints.\n.PP\nAs indicated,\nthese calls\n(except for request PT_TRACE_ME)\ncan be used only when the subject process has stopped.\nThe\n.I wait\ncall is used to determine\nwhen a process stops;\nin such a case the \\*(lqtermination\\*(rq status\nreturned by\n.I wait\nhas the value 0177 to indicate stoppage rather\nthan genuine termination.\n.PP\nTo forestall possible fraud,\n.I ptrace\ninhibits the set-user-id and set-group-id facilities\non subsequent\n.IR  execve (2)\ncalls.\nIf a traced process calls\n.IR execve ,\nit will stop before executing the first instruction of the new image\nshowing signal SIGTRAP.\n.PP\nOn a VAX-11, \\*(lqword\\*(rq also means a 32-bit integer,\nbut the \\*(lqeven\\*(rq\nrestriction does not apply.\n.SH \"RETURN VALUE\nA 0 value is returned if the call succeeds.  If the call fails\nthen a \\-1 is returned and the global variable \\fIerrno\\fP is\nset to indicate the error.\n.SH \"ERRORS\n.TP 15\n[EIO]\nThe request code is invalid.\n.TP 15\n[ESRCH]\nThe specified process does not exist.\n.TP 15\n[EIO]\nThe given signal number is invalid.\n.TP 15\n[EIO]\nThe specified address is out of bounds.\n.TP 15\n[EPERM]\nThe specified process cannot be traced.\n.SH \"SEE ALSO\"\nwait(2), sigvec(2), adb(1)\n.SH \"NOTES  (PDP-11)\"\nOn the PDP-11 the PT_WRITE_U request may also write the child process's\ncurrent overlay number in the system data area; the T-bit is used to single\nstep the processor and just one instruction is executed for the PT_STEP\nrequest; a \\*(lqword\\*(rq means a 16-bit integer, and the \\*(lqeven\\*(rq\nrestriction \\fIdoes\\fP apply.\n.SH BUGS\n.I Ptrace\nis unique and arcane; it should be replaced with a special file that\ncan be opened and read and written.  The control functions could then\nbe implemented with\n.IR ioctl (2)\ncalls on this file.  This would be simpler to understand and have much\nhigher performance.\n.PP\nThe request PT_TRACE_ME call should be able to specify\nsignals that are to be treated normally and not cause a stop.\nIn this way, for example,\nprograms with simulated floating point (which\nuse \\*(lqillegal instruction\\*(rq signals at a very high rate)\ncould be efficiently debugged.\n.PP\nThe error indication, \\-1, is a legitimate function value;\n.I errno,\n(see\n.IR intro (2)),\ncan be used to disambiguate.\n.PP\nIt should be possible to stop a process on occurrence of a system\ncall;\nin this way a completely controlled environment could\nbe provided.\n"
  },
  {
    "path": "share/man/man2/quota.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)quota.2\t6.7 (Berkeley) 5/15/86\n.\\\"\n.TH QUOTA 2 \"May 15, 1986\"\n.UC 5\n.SH NAME\nquota \\- manipulate disk quotas\n.SH SYNOPSIS\n.nf\n.B #include <sys/quota.h>\n.PP\n.B quota(cmd, uid, arg, addr)\n.B int cmd, uid, arg;\n.B char *addr;\n.fi\n.SH DESCRIPTION\nThe\n.I quota\ncall manipulates disk quotas for file systems\nthat have had quotas enabled with\n.IR setquota (2).\nThe\n.I cmd\nparameter indicates a command to be applied to\nthe user ID\n.IR uid .\n.I Arg\nis a command specific argument and\n.I addr\nis the address of an optional, command specific, data structure\nthat is copied in or out of the system.  The interpretation of\n.I arg\nand\n.I addr\nis given with each command below.\n.TP\nQ_SETDLIM\nSet disc quota limits and current usage for the user with ID\n.IR uid .\n.I Arg\nis a major-minor device indicating a particular file system.\n.I Addr\nis a pointer to a struct dqblk structure (defined in \n.RI < sys/quota.h >).\nThis call is restricted to the super-user.\n.TP\nQ_GETDLIM\nGet disc quota limits and current usage for the user with ID\n.IR uid .\nThe remaining parameters are as for Q_SETDLIM.\n.TP\nQ_SETDUSE\nSet disc usage limits for the user with ID\n.IR uid .\n.I Arg\nis a major-minor device indicating a particular file system.\n.I Addr\nis a pointer to a struct dqusage structure (defined in\n.RI < sys/quota.h >).\nThis call is restricted to the super-user.\n.TP\nQ_SYNC\nUpdate the on-disc copy of quota usages.\n.I Arg\nis a major-minor device indicating the file system to be sync'ed.\nIf the\n.I arg\nparameter is specified as NODEV, all file systems that have\ndisc quotas will be sync'ed.\nThe \\fIuid\\fP and \\fIaddr\\fP parameters are ignored.\n.TP\nQ_SETUID\nChange the calling process's quota limits to those of the\nuser with ID\n.IR uid .\nThe \n.I arg\nand\n.I addr\nparameters are ignored.  This call is restricted to the super-user.\n.TP\nQ_SETWARN\nAlter the disc usage warning limits for the user with ID\n.IR uid .\n.I Arg\nis a major-minor device indicating a particular file system.\n.I Addr\nis a pointer to a struct dqwarn structure (defined in\n.RI < sys/quota.h >).\nThis call is restricted to the super-user.\n.TP\nQ_DOWARN\nWarn the user with user ID\n.I uid\nabout excessive disc usage.\nThis call causes the system to check its current disc usage\ninformation and print a message on the terminal of\nthe caller for each file system on which the user is over quota.\nIf the user is under quota, his warning count is reset to MAX_*_WARN\n(defined in\n.RI < sys/quota.h >).\nIf the\n.I arg\nparameter is specified as NODEV, all file systems that have\ndisc quotas will be checked.  Otherwise, \n.I arg\nindicates a specific major-minor device to be checked.\nThis call is restricted to the super-user.\n.SH \"RETURN VALUE\"\nA successful call returns 0,\notherwise the value \\-1 is returned and the global variable\n.I errno\nindicates the reason for the failure.\n.SH ERRORS\nA \\fIquota\\fP call will fail when one of the following occurs:\n.TP 15\n[EINVAL]\nThe kernel has not been compiled with the QUOTA option.\n.TP 15\n[EINVAL]\n.I Cmd\nis invalid.\n.TP 15\n[ESRCH]\nNo disc quota is found for the indicated user.\n.TP 15\n[EPERM]\nThe call is priviledged and the caller was not the super-user.\n.TP 15\n[ENODEV]\nThe \n.I arg\nparameter is being interpreted as a major-minor\ndevice and it indicates an unmounted file system.\n.TP 15\n[EFAULT]\nAn invalid\n.I addr\nis supplied; the associated structure could not be copied in or out\nof the kernel.\n.TP 15\n[EUSERS]\nThe quota table is full.\n.SH \"SEE ALSO\"\nsetquota(2), quotaon(8), quotacheck(8)\n.SH BUGS\nThere should be some way to integrate this call with the resource\nlimit interface provided by\n.IR setrlimit (2)\nand\n.IR getrlimit (2).\n.PP\nThe Australian spelling of\n.I disk\nis used throughout the quota facilities in honor of\nthe implementors.\n"
  },
  {
    "path": "share/man/man2/read.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)read.2\t6.6 (Berkeley) 8/1/87\n.\\\"\n.TH READ 2 \"August 1, 1987\"\n.UC 4\n.SH NAME\nread, readv \\- read input\n.SH SYNOPSIS\n.nf\n.ft B\ncc = read(d, buf, nbytes)\nint cc, d;\nchar *buf;\nunsigned short nbytes;\n.PP\n.ft B\n#include <sys/types.h>\n#include <sys/uio.h>\n.PP\n.ft B\ncc = readv(d, iov, iovcnt)\nint cc, d;\nstruct iovec *iov;\nint iovcnt;\n.fi\n.SH DESCRIPTION\n.I Read\nattempts to read\n.I nbytes\nof data from the object referenced by the descriptor\n.I d\ninto the buffer pointed to by\n.IR buf .\n.I Readv\nperforms the same action, but scatters the input data\ninto the \n.I iovcnt\nbuffers specified by the members of the\n.I iov\narray: iov[0], iov[1], ..., iov[iovcnt\\|\\-\\|1].\n.PP\nFor \n.IR readv ,\nthe \n.I iovec\nstructure is defined as\n.PP\n.nf\n.RS\n.DT\nstruct iovec {\n\tcaddr_t\tiov_base;\n\tu_short\tiov_len;\n};\n.RE\n.fi\n.PP\nEach \n.I iovec\nentry specifies the base address and length of an area\nin memory where data should be placed. \n.I Readv\nwill always fill an area completely before proceeding\nto the next.\n.PP\nOn objects capable of seeking, the\n.I read\nstarts at a position\ngiven by the pointer associated with\n.IR d \n(see\n.IR lseek (2)).\nUpon return from\n.IR read ,\nthe pointer is incremented by the number of bytes actually read.\n.PP\nObjects that are not capable of seeking always read from the current\nposition.  The value of the pointer associated with such an\nobject is undefined.\n.PP\nUpon successful completion,\n.I read\nand\n.I readv\nreturn the number of bytes actually read and placed in the buffer.\nThe system guarantees to read the number of bytes requested if\nthe descriptor references a normal file that has that many bytes left\nbefore the end-of-file, but in no other case.\n.PP\nIf the returned value is 0, then\nend-of-file has been reached.\n.SH \"RETURN VALUE\nIf successful, the\nnumber of bytes actually read is returned.\nOtherwise, a \\-1 is returned and the global variable\n.I errno\nis set to indicate the error.\n.SH \"ERRORS\n.I Read\nand\n.I readv\nwill fail if one or more of the following are true:\n.TP 15\n[EBADF]\n\\fID\\fP is not a valid file or socket descriptor open for reading.\n.TP 15\n[EFAULT]\n\\fIBuf\\fP points outside the allocated address space.\n.TP 15\n[EIO]\nAn I/O error occurred while reading from the file system.\n.TP 15\n[EINTR]\nA read from a slow device was interrupted before\nany data arrived by the delivery of a signal.\n.TP 15\n[EINVAL]\nThe pointer associated with\n.I d\nwas negative.\n.TP 15\n[EWOULDBLOCK]\nThe file was marked for non-blocking I/O,\nand no data were ready to be read.\n.PP\nIn addition, \n.I readv\nmay return one of the following errors:\n.TP 15\n[EINVAL]\n.I Iovcnt\nwas less than or equal to 0, or greater than 16.\n.TP 15\n[EINVAL]\nThe sum of the\n.I iov_len\nvalues in the\n.I iov\narray overflowed a short.\n.TP 15\n[EFAULT]\nPart of the \\fIiov\\fP points outside the process's allocated address space.\n.SH \"SEE ALSO\"\ndup(2), fcntl(2), open(2), pipe(2), select(2), socket(2), socketpair(2)\n"
  },
  {
    "path": "share/man/man2/readlink.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)readlink.2\t6.4 (Berkeley) 8/26/85\n.\\\"\n.TH READLINK 2 \"August 26, 1985\"\n.UC 5\n.SH NAME\nreadlink \\- read value of a symbolic link\n.SH SYNOPSIS\n.nf\n.ft B\ncc = readlink(path, buf, bufsiz)\nint cc;\nchar *path, *buf;\nint bufsiz;\n.fi\n.ft R\n.SH DESCRIPTION\n.I Readlink\nplaces the contents of the symbolic link\n.I name\nin the buffer\n.I buf,\nwhich has size\n.IR bufsiz . \nThe contents of the link are not null terminated when returned.\n.SH \"RETURN VALUE\nThe call returns the count of characters placed in the buffer\nif it succeeds, or a \\-1 if an error occurs, placing the error\ncode in the global variable \\fIerrno\\fP.\n.SH \"ERRORS\n.I Readlink\nwill fail and the file mode will be unchanged if:\n.TP 15\n[ENOTDIR]\nA component of the path prefix is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 255 characters,\nor an entire path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nThe named file does not exist.\n.TP 15\n[EACCES]\nSearch permission is denied for a component of the path prefix.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[EINVAL]\nThe named file is not a symbolic link.\n.TP 15\n[EIO]\nAn I/O error occurred while reading from the file system.\n.TP 15\n[EFAULT]\n.I Buf\nextends outside the process's allocated address space.\n.SH SEE ALSO\nstat(2), lstat(2), symlink(2)\n"
  },
  {
    "path": "share/man/man2/reboot.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)reboot.2\t6.1 (Berkeley) 5/9/85\n.\\\"\n.TH REBOOT 2 \"May 9, 1985\"\n.UC 4\n.SH NAME\nreboot \\- reboot system or halt processor\n.SH SYNOPSIS\n.nf\n.B #include <sys/reboot.h>\n.PP\n.B reboot(howto)\n.B int howto;\n.fi\n.SH DESCRIPTION\n.I Reboot\nreboots the system, and is invoked automatically\nin the event of unrecoverable system failures.\n.I Howto\nis a mask of options passed to the bootstrap program.\nThe system call interface permits only RB_HALT or RB_AUTOBOOT\nto be passed to the reboot program; the other flags\nare used in scripts stored on the console storage media, or used\nin manual bootstrap procedures.\nWhen none of these options (e.g. RB_AUTOBOOT) is given, the system is rebooted\nfrom file \\*(lqvmunix\\*(rq in the root file system of unit 0\nof a disk chosen in a processor specific way.\nAn automatic consistency check of the disks is then normally performed.\n.PP\nThe bits of\n.I howto\nare:\n.TP\nRB_HALT\nthe processor is simply halted; no reboot takes place.\nRB_HALT should be used with caution.\n.TP\nRB_ASKNAME\nInterpreted by the bootstrap program itself, causing it to\ninquire as to what file should be booted.  Normally, the system is\nbooted from the file \\*(lqxx(0,0)vmunix\\*(rq without asking.\n.TP\nRB_SINGLE\nNormally, the reboot procedure involves an automatic disk consistency\ncheck and then multi-user operations.  RB_SINGLE prevents the consistency\ncheck, rather simply booting the system with a single-user shell on\nthe console.\nRB_SINGLE is interpreted by the\n.IR init (8)\nprogram in the newly booted system.\nThis switch is not available from the system call interface.\n.PP\nOnly the super-user may\n.I reboot\na machine.\n.SH \"RETURN VALUES\"\nIf successful, this call never returns.  Otherwise, a \\-1\nis returned and an error is returned in the global variable\n.IR errno .\n.SH ERRORS\n.TP 15\n[EPERM]\nThe caller is not the super-user.\n.SH \"SEE ALSO\"\ncrash(8), halt(8), init(8), reboot(8)\n.SH BUGS\nThe notion of ``console medium'', among other things,\nis specific to the VAX.\n"
  },
  {
    "path": "share/man/man2/recv.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)recv.2\t6.3 (Berkeley) 5/23/86\n.\\\"\n.TH RECV 2 \"May 23, 1986\"\n.UC 5\n.SH NAME\nrecv, recvfrom, recvmsg \\- receive a message from a socket\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/types.h>\n#include <sys/socket.h>\n.PP\n.ft B\ncc = recv(s, buf, len, flags)\nint cc, s;\nchar *buf;\nint len, flags;\n.PP\n.ft B\ncc = recvfrom(s, buf, len, flags, from, fromlen)\nint cc, s;\nchar *buf;\nint len, flags;\nstruct sockaddr *from;\nint *fromlen;\n.PP\n.ft B\ncc = recvmsg(s, msg, flags)\nint cc, s;\nstruct msghdr msg[];\nint flags;\n.ft R\n.SH DESCRIPTION\n.IR Recv ,\n.IR recvfrom ,\nand\n.IR recvmsg\nare used to receive messages from a socket.\n.PP\nThe \n.I recv\ncall is normally used only on a \n.I connected\nsocket (see\n.IR connect (2)),\nwhile \n.I recvfrom\nand \n.I recvmsg\nmay be used to receive data on a socket whether\nit is in a connected state or not.\n.PP\nIf\n.I from\nis non-zero, the source address of the message is filled in.\n.I Fromlen\nis a value-result parameter, initialized to the size of\nthe buffer associated with\n.IR from ,\nand modified on return to indicate the actual size of the\naddress stored there.\nThe length of the message is returned in\n.IR cc .\nIf a message is too long to fit in the supplied buffer,\nexcess bytes may be discarded depending on the type of socket\nthe message is received from (see\n.IR socket (2)).\n.PP\nIf no messages are available at the socket, the\nreceive call waits for a message to arrive, unless\nthe socket is nonblocking (see\n.IR ioctl (2))\nin which case a\n.I cc\nof \\-1 is returned with the external variable errno\nset to EWOULDBLOCK.\n.PP\nThe\n.IR select (2)\ncall may be used to determine when more data arrives.\n.PP\nThe\n.I flags\nargument to a recv call is formed by \n.IR or 'ing\none or more of the values,\n.PP\n.nf\n.RS\n.ta \\w'#define\\ \\ 'u +\\w'MSG_DONTROUTE\\ \\ \\ 'u +\\w'0x\\0\\0\\0\\ \\ 'u\n#define\tMSG_OOB\t0x1\t/* process out-of-band data */\n#define\tMSG_PEEK\t0x2\t/* peek at incoming message */\n.RE\n.fi\n.PP\nThe\n.I recvmsg\ncall uses a \n.I msghdr\nstructure to minimize the number of directly supplied parameters.\nThis structure has the following form, as defined in\n.IR <sys/socket.h> :\n.PP\n.nf\n.RS\n.DT\nstruct msghdr {\n\tcaddr_t\tmsg_name;\t\t/* optional address */\n\tint\tmsg_namelen;\t\t/* size of address */\n\tstruct\tiovec *msg_iov;\t\t/* scatter/gather array */\n\tint\tmsg_iovlen;\t\t/* # elements in msg_iov */\n\tcaddr_t\tmsg_accrights;\t\t/* access rights sent/received */\n\tint\tmsg_accrightslen;\n};\n.RE\n.fi\n.PP\nHere\n.I msg_name\nand\n.I msg_namelen\nspecify the destination address if the socket is unconnected;\n.I msg_name\nmay be given as a null pointer if no names are desired or required.\nThe \n.I msg_iov\nand\n.I msg_iovlen\ndescribe the scatter gather locations, as described in\n.IR read (2).\nA buffer to receive any access rights sent along with the message is specified\nin \n.IR msg_accrights ,\nwhich has length\n.IR msg_accrightslen .\nAccess rights are currently limited to file descriptors,\nwhich each occupy the size of an\n.BR int .\n.SH \"RETURN VALUE\nThese calls return the number of bytes received, or \\-1\nif an error occurred.\n.SH ERRORS\nThe calls fail if:\n.TP 20\n[EBADF]\nThe argument \\fIs\\fP is an invalid descriptor.\n.TP 20\n[ENOTSOCK]\nThe argument \\fIs\\fP is not a socket.\n.TP 20\n[EWOULDBLOCK]\nThe socket is marked non-blocking and the receive operation\nwould block.\n.TP 20\n[EINTR]\nThe receive was interrupted by delivery of a signal before\nany data was available for the receive.\n.TP 20\n[EFAULT]\nThe data was specified to be received into a non-existent\nor protected part of the process address space.\n.SH SEE ALSO\nfcntl(2), read(2), send(2), select(2), getsockopt(2), socket(2)\n"
  },
  {
    "path": "share/man/man2/rename.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)rename.2\t6.4 (Berkeley) 5/22/86\n.\\\"\n.TH RENAME 2 \"May 22, 1986\"\n.UC 5\n.SH NAME\nrename \\- change the name of a file\n.SH SYNOPSIS\n.ft B\n.nf\nrename(from, to)\nchar *from, *to;\n.fi\n.ft R\n.SH DESCRIPTION\n.I Rename\ncauses the link named\n.I from\nto be renamed as\n.IR to .\nIf \n.I to\nexists, then it is first removed.\nBoth \n.I from\nand\n.I to\nmust be of the same type (that is, both directories or both\nnon-directories), and must reside on the same file system.\n.PP\n.I Rename\nguarantees that an instance of\n.I to\nwill always exist, even if the system should crash in\nthe middle of the operation.\n.PP\nIf the final component of\n.I from\nis a symbolic link,\nthe symbolic link is renamed,\nnot the file or directory to which it points.\n.SH CAVEAT\nThe system can deadlock if a loop in the file system graph is present.\nThis loop takes the form of an entry in directory \\*(lqa\\*(rq,\nsay \\*(lqa/foo\\*(rq,\nbeing a hard link to directory \\*(lqb\\*(rq, and an entry in\ndirectory \\*(lqb\\*(rq, say \\*(lqb/bar\\*(rq, being a hard link\nto directory \\*(lqa\\*(rq.\nWhen such a loop exists and two separate processes attempt to\nperform \\*(lqrename a/foo b/bar\\*(rq and \\*(lqrename b/bar a/foo\\*(rq,\nrespectively, \nthe system may deadlock attempting to lock\nboth directories for modification.\nHard links to directories should be\nreplaced by symbolic links by the system administrator.\n.SH \"RETURN VALUE\"\nA 0 value is returned if the operation succeeds, otherwise\n.I rename\nreturns \\-1 and the global variable \n.I errno\nindicates the reason for the failure.\n.SH \"ERRORS\n.I Rename\nwill fail and neither of the argument files will be\naffected if any of the following are true:\n.TP 15\n[EINVAL]\nEither pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of either pathname exceeded 255 characters,\nor the entire length of either path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nA component of the \\fIfrom\\fP path does not exist,\nor a path prefix of \\FIto\\fP does not exist.\n.TP 15\n[EACCES]\nA component of either path prefix denies search permission.\n.TP 15\n[EACCES]\nThe requested link requires writing in a directory with a mode\nthat denies write permission.\n.TP 15\n[EPERM]\nThe directory containing \\fIfrom\\fP is marked sticky,\nand neither the containing directory nor \\fIfrom\\fP\nare owned by the effective user ID.\n.TP 15\n[EPERM]\nThe \\fIto\\fP file exists,\nthe directory containing \\fIto\\fP is marked sticky,\nand neither the containing directory nor \\fIto\\fP\nare owned by the effective user ID.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating either pathname.\n.TP 15\n[ENOTDIR]\nA component of either path prefix is not a directory.\n.TP 15\n[ENOTDIR]\n.I From\nis a directory, but \\fIto\\fP is not a directory.\n.TP 15\n[EISDIR]\n.I To\nis a directory, but \\fIfrom\\fP is not a directory.\n.TP 15\n[EXDEV]\nThe link named by \\fIto\\fP and the file named by \\fIfrom\\fP\nare on different logical devices (file systems).  Note that this error\ncode will not be returned if the implementation permits cross-device\nlinks.\n.TP 15\n[ENOSPC]\nThe directory in which the entry for the new name is being placed\ncannot be extended because there is no space left on the file\nsystem containing the directory.\n.TP 15\n[EDQUOT]\nThe directory in which the entry for the new name\nis being placed cannot be extended because the\nuser's quota of disk blocks on the file system\ncontaining the directory has been exhausted.\n.TP 15\n[EIO]\nAn I/O error occurred while making or updating a directory entry.\n.TP 15\n[EROFS]\nThe requested link requires writing in a directory on a read-only file\nsystem.\n.TP 15\n[EFAULT]\n.I Path\npoints outside the process's allocated address space.\n.TP 15\n[EINVAL]\n.I From\nis a parent directory of\n.IR to ,\nor an attempt is made to rename ``.'' or ``..''.\n.TP 15\n[ENOTEMPTY]\n.I To\nis a directory and is not empty.\n.SH \"SEE ALSO\"\nopen(2)\n"
  },
  {
    "path": "share/man/man2/rmdir.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)rmdir.2\t6.3 (Berkeley) 8/26/85\n.\\\"\n.TH RMDIR 2 \"August 26, 1985\"\n.UC 5\n.SH NAME\nrmdir \\- remove a directory file\n.SH SYNOPSIS\n.nf\n.ft B\nrmdir(path)\nchar *path;\n.fi\n.ft R\n.SH DESCRIPTION\n.I Rmdir\nremoves a directory file\nwhose name is given by\n.I path.\nThe directory must not have any entries other\nthan \\*(lq.\\*(rq and \\*(lq..\\*(rq.\n.SH \"RETURN VALUE\nA 0 is returned if the remove succeeds; otherwise a \\-1 is\nreturned and an error code is stored in the global location \\fIerrno\\fP\\|.\n.SH ERRORS\nThe named file is removed unless one or more of the\nfollowing are true:\n.TP 15\n[ENOTDIR]\nA component of the path is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 255 characters,\nor an entire path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nThe named directory does not exist.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[ENOTEMPTY]\nThe named directory contains files other than ``.'' and ``..'' in it.\n.TP 15\n[EACCES]\nSearch permission is denied for a component of the path prefix.\n.TP 15\n[EACCES]\nWrite permission is denied on the directory containing the link\nto be removed.\n.TP 15\n[EPERM]\nThe directory containing the directory to be removed is marked sticky,\nand neither the containing directory nor the directory to be removed\nare owned by the effective user ID.\n.TP 15\n[EBUSY]\nThe directory to be removed is the mount point\nfor a mounted file system.\n.TP 15\n[EIO]\nAn I/O error occurred while deleting the directory entry\nor deallocating the inode.\n.TP 15\n[EROFS]\nThe directory entry to be removed resides on a read-only file system.\n.TP 15\n[EFAULT]\n.I Path\npoints outside the process's allocated address space.\n.SH \"SEE ALSO\"\nmkdir(2), unlink(2)\n"
  },
  {
    "path": "share/man/man2/select.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)select.2\t6.5.2 (2.11BSD) 2000/3/4\n.\\\"\n.TH SELECT 2 \"March 4, 2000\"\n.UC 5\n.SH NAME\npselect, select \\- synchronous I/O multiplexing\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/types.h>\n#include <sys/time.h>\n#include <sys/select.h>\n#include <signal.h>\n.PP\n.ft B\nnfound = pselect(nfds, readfds, writefds, exceptfds, timeout, sigmask);\nint nfound, nfds;\nfd_set *readfds, *writefds, *exceptfds;\nstruct timespec *timeout;\nsigset_t *sigmask;\n.PP\n.ft B\nnfound = select(nfds, readfds, writefds, exceptfds, timeout)\nint nfound, nfds;\nfd_set *readfds, *writefds, *exceptfds;\nstruct timeval *timeout;\n.PP\n.ft B\nFD_SET(fd, &fdset)\t\nFD_CLR(fd, &fdset)\t\nFD_ISSET(fd, &fdset)\t\nFD_ZERO(&fdset)\t\nint fd;\nfd_set fdset;\n.fi\n.SH DESCRIPTION\n.I Pselect\nand\n.I select\nexamine the I/O descriptor sets whose addresses are passed in\n.IR readfds ,\n.IR writefds ,\nand\n.I exceptfds\nto see if some of their descriptors\nare ready for reading, are ready for writing, or have an exceptional\ncondition pending, respectively.\nThe two functions are identical except for the type and format of the\n.I timeout\nvalue, and the additonal \n.I sigmask\nparameter supplied to the\n.IR pselect ()\ncall.\n.PP\nThe first\n.I nfds\ndescriptors are checked in each set;\ni.e. the descriptors from 0 through\n.IR nfds -1\nin the descriptor sets are examined.\nOn return,\n.I select\nreplaces the given descriptor sets\nwith subsets consisting of those descriptors that are ready\nfor the requested operation.\nThe total number of ready descriptors in all the sets is returned in\n.IR nfound .\n.PP\nThe descriptor sets are stored as bit fields in arrays of integers.\nThe following macros are provided for manipulating such descriptor sets:\n.I \"FD_ZERO(&fdset)\"\ninitializes a descriptor set\n.I fdset\nto the null set.\n.I \"FD_SET(fd, &fdset)\"\nincludes a particular descriptor\n.I fd\nin\n.IR fdset .\n.I \"FD_CLR(fd, &fdset)\"\nremoves\n.I fd\nfrom\n.IR fdset .\n.I \"FD_ISSET(fd, &fdset)\"\nis nonzero if\n.I fd\nis a member of\n.IR fdset ,\nzero otherwise.\nThe behavior of these macros is undefined if\na descriptor value is less than zero or greater than or equal to\n.IR FD_SETSIZE ,\nwhich is normally at least equal\nto the maximum number of descriptors supported by the system.\n.PP\nIf\n.I timeout\nis a non-zero pointer, it specifies a maximum interval to wait for the\nselection to complete.  If \n.I timeout\nis a zero pointer, \n.I select\nblocks indefinitely.  To affect a poll, the\n.I timeout\nargument should be non-zero, pointing to a zero-valued timeval\nstructure.\n.PP\nIf the \n.I sigmask\nparameter to\n.IR pselect ()\nis not NULL, it points to a signal mask that replaces the previous\nsignal mask for the process for the duration of the call,\nand the previous mask is restored upon return; see sigprocmask(3).\nThis is normally used so that signals can be blocked while preparing\nfor a call to\n.IR pselect ()\nand then atomically unblocking the signals while selecting.\n.PP\nAny of\n.IR readfds ,\n.IR writefds ,\nand\n.I exceptfds\nmay be given as zero pointers if no descriptors are of interest.\n.SH \"RETURN VALUE\n.I Select\nreturns the number of ready descriptors that are contained in\nthe descriptor sets,\nor \\-1 if an error occurred.\nIf the time limit expires then\n.I select\nreturns 0.\nIf\n.I select\nreturns with an error,\nincluding one due to an interrupted call,\nthe descriptor sets will be unmodified.\n.SH \"ERRORS\nAn error return from \\fIselect\\fP indicates:\n.TP 15\n[EBADF]\nOne of the descriptor sets specified an invalid descriptor.\n.TP 15\n[EINTR]\nA signal was delivered before the time limit expired and\nbefore any of the selected events occurred.\n.TP 15\n[EINVAL]\nThe specified time limit is invalid.  One of its components is\nnegative or too large.\n.SH SEE ALSO\naccept(2), connect(2), read(2), write(2), recv(2), send(2), getdtablesize(2)\n.SH BUGS\nAlthough the provision of\n.IR getdtablesize (2)\nwas intended to allow user programs to be written independent\nof the kernel limit on the number of open files, the dimension\nof a sufficiently large bit field for select remains a problem.\nThe default size FD_SETSIZE (currently 256) is somewhat larger than\nthe current kernel limit to the number of open files.\nHowever, in order to accommodate programs which might potentially\nuse a larger number of open files with select, it is possible\nto increase this size within a program by providing\na larger definition of FD_SETSIZE before the inclusion of <sys/types.h>.\n.PP\n.I Select\nshould probably return the time remaining from the original timeout,\nif any, by modifying the time value in place.\nThis may be implemented in future versions of the system.\nThus, it is unwise to assume that the timeout value will be unmodified\nby the\n.I select\ncall.\n.PP\nIn 2BSD the timeout is implemented in the kernel using the \\fIcallout\\fP\ntable.  Since a \\fIcallout\\fP structure only has a signed short to \nstore the number of ticks till expiration the maximum value of a kernel\ntimeout is 32767 ticks.  In the US (60hz power) this gives a maximum\ntimeout of approximately 9 minutes.  In countries using 50hz power \nthe maximum timeout is about 13 minutes.\n.PP\n.I struct timespec\non a PDP\\-11 is silly since the hardware has nowhere near microsecond\nmuch less nanosecond clock resolution.\n"
  },
  {
    "path": "share/man/man2/send.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)send.2\t6.3 (Berkeley) 5/14/86\n.\\\"\n.TH SEND 2 \"May 14, 1986\"\n.UC 5\n.SH NAME\nsend, sendto, sendmsg \\- send a message from a socket\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/types.h>\n#include <sys/socket.h>\n.PP\n.ft B\ncc = send(s, msg, len, flags)\nint cc, s;\nchar *msg;\nint len, flags;\n.PP\n.ft B\ncc = sendto(s, msg, len, flags, to, tolen)\nint cc, s;\nchar *msg;\nint len, flags;\nstruct sockaddr *to;\nint tolen;\n.PP\n.ft B\ncc = sendmsg(s, msg, flags)\nint cc, s;\nstruct msghdr msg[];\nint flags;\n.fi\n.SH DESCRIPTION\n.IR Send ,\n.IR sendto ,\nand\n.I sendmsg\nare used to transmit a message to another socket.\n.I Send\nmay be used only when the socket is in a \n.I connected\nstate, while \n.I sendto\nand\n.I sendmsg\nmay be used at any time.\n.PP\nThe address of the target is given by\n.I to\nwith \n.I tolen\nspecifying its size.\nThe length of the message is given by\n.IR len .\nIf the message is too long to pass atomically through the\nunderlying protocol, then the error EMSGSIZE is returned, and\nthe message is not transmitted.\n.PP\nNo indication of failure to deliver is implicit in a\n.IR send .\nReturn values of \\-1 indicate some locally detected errors.\n.PP\nIf no messages space is available at the socket to hold\nthe message to be transmitted, then\n.I send\nnormally blocks, unless the socket has been placed in\nnon-blocking I/O mode.\nThe\n.IR select (2)\ncall may be used to determine when it is possible to\nsend more data.\n.PP\nThe\n.I flags\nparameter may include one or more of the following:\n.PP\n.nf\n.RS\n.ta \\w'#define\\ \\ 'u +\\w'MSG_DONTROUTE\\ \\ \\ 'u +\\w'0x\\0\\0\\0\\ \\ 'u\n#define\tMSG_OOB\t0x1\t/* process out-of-band data */\n#define\tMSG_DONTROUTE\t0x4\t/* bypass routing, use direct interface */\n.RE\n.fi\nThe flag MSG_OOB is used to send \\*(lqout-of-band\\*(rq\ndata on sockets that support this notion (e.g. SOCK_STREAM);\nthe underlying protocol must also support \\*(lqout-of-band\\*(rq data.\nMSG_DONTROUTE is usually used only by diagnostic or routing programs.\n.PP\nSee \n.IR recv (2)\nfor a description of the\n.I msghdr\nstructure.\n.SH \"RETURN VALUE\nThe call returns the number of characters sent, or \\-1\nif an error occurred.\n.SH \"ERRORS\n.TP 20\n[EBADF]\nAn invalid descriptor was specified.\n.TP 20\n[ENOTSOCK]\nThe argument \\fIs\\fP is not a socket.\n.TP 20\n[EFAULT]\nAn invalid user space address was specified for a parameter.\n.TP 20\n[EMSGSIZE]\nThe socket requires that message be sent atomically,\nand the size of the message to be sent made this impossible.\n.TP 20\n[EWOULDBLOCK]\nThe socket is marked non-blocking and the requested operation\nwould block.\n.TP 20\n[ENOBUFS]\nThe system was unable to allocate an internal buffer.\nThe operation may succeed when buffers become available.\n.TP 20\n[ENOBUFS]\nThe output queue for a network interface was full.\nThis generally indicates that the interface has stopped sending,\nbut may be caused by transient congestion.\n.SH SEE ALSO\nfcntl(2), recv(2), select(2), getsockopt(2), socket(2), write(2)\n"
  },
  {
    "path": "share/man/man2/setgroups.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)setgroups.2\t6.3 (Berkeley) 5/13/86\n.\\\"\n.TH SETGROUPS 2 \"May 13, 1986\"\n.UC 5\n.SH NAME\nsetgroups \\- set group access list\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/param.h>\n.PP\n.ft B\nsetgroups(ngroups, gidset)\nint ngroups, *gidset;\n.fi\n.SH DESCRIPTION\n.I Setgroups\nsets the group access list of the current user process\naccording to the array \n.IR gidset .\nThe parameter\n.I ngroups\nindicates the number of entries in the array and must be no\nmore than NGROUPS, as defined in\n.RI < sys/param.h >.\n.PP\nOnly the super-user may set new groups.\n.SH \"RETURN VALUE\nA 0 value is returned on success, \\-1 on error, with\na error code stored in \\fIerrno\\fP.\n.SH \"ERRORS\nThe \\fIsetgroups\\fP call will fail if:\n.TP 15\n[EPERM]\nThe caller is not the super-user.\n.TP 15\n[EFAULT]\nThe address specified for \\fIgidset\\fP is outside the process\naddress space.\n.SH \"SEE ALSO\ngetgroups(2), initgroups(3X)\n.SH BUGS\nThe\n.I gidset\narray should be of type\n.BR gid_t ,\nbut remains integer for compatibility with earlier systems.\n"
  },
  {
    "path": "share/man/man2/setpgrp.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)setpgrp.2\t6.1 (Berkeley) 5/9/85\n.\\\"\n.TH SETPGRP 2 \"May 9, 1985\"\n.UC 4\n.SH NAME\nsetpgrp \\- set process group\n.SH SYNOPSIS\n.ft B\nsetpgrp(pid, pgrp)\n.br\nint pid, pgrp;\n.ft R\n.SH DESCRIPTION\n.I Setpgrp\nsets the process group of the specified process\n.I pid\nto the specified\n.IR pgrp .\nIf\n.I pid\nis zero, then the call applies to the current process.\n.PP\nIf the invoker is not the super-user, then the affected process\nmust have the same effective user-id as the invoker or be a descendant\nof the invoking process.\n.SH \"RETURN VALUE\n.I Setpgrp\nreturns when the operation was successful.  If\nthe request failed, \\-1 is returned and the global\nvariable\n.I errno\nindicates the reason.\n.SH ERRORS\n.I Setpgrp\nwill fail and the process group will not be altered if\none of the following occur:\n.TP 15\n[ESRCH]\nThe requested process does not exist.\n.TP 15\n[EPERM]\nThe effective user ID of the requested process is different\nfrom that of the caller and the process is not a descendent\nof the calling process.\n.SH \"SEE ALSO\"\ngetpgrp(2)\n"
  },
  {
    "path": "share/man/man2/setquota.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)setquota.2\t6.4 (Berkeley) 8/26/85\n.\\\"\n.TH SETQUOTA 2 \"August 26, 1985\"\n.UC 5\n.SH NAME\nsetquota \\- enable/disable quotas on a file system\n.SH SYNOPSIS\n.nf\n.B setquota(special, file)\n.B char *special, *file;\n.fi\n.SH DESCRIPTION\nDisc quotas are enabled or disabled with the\n.I setquota\ncall.\n.I Special\nindicates a block special device on which a\nmounted file system exists.\nIf\n.I file\nis nonzero, it specifies a file in that\nfile system from which to take the quotas.  If\n.I file\nis 0, then quotas are disabled on the file system.\nThe quota file must exist; it is normally created\nwith the \n.IR quotacheck (8)\nprogram.\n.PP\nOnly the super-user may turn quotas on or off.\n.SH \"SEE ALSO\"\nquota(2), quotacheck(8), quotaon(8)\n.SH \"RETURN VALUE\"\nA 0 return value indicates a successful call.  A value\nof \\-1 is returned when an error occurs and \n.I errno\nis set to indicate the reason for failure.\n.SH ERRORS\n.I Setquota\nwill fail when one of the following occurs:\n.TP 15\n[ENOTDIR]\nA component of either path prefix is not a directory.\n.TP 15\n[EINVAL]\nEither pathname contains a character with the high-order bit set.\n.TP 15\n[EINVAL]\nThe kernel has not been compiled with the QUOTA option.\n.TP 15\n[ENAMETOOLONG]\nA component of either pathname exceeded 255 characters,\nor the entire length of either path name exceeded 1023 characters.\n.TP 15\n[ENODEV]\n.I Special\ndoes not exist.\n.TP 15\n[ENOENT]\n.I File\ndoes not exist.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating either pathname.\n.TP 15\n[EPERM]\nThe caller is not the super-user.\n.TP 15\n[ENOTBLK]\n.I Special\nis not a block device.\n.TP 15\n[ENXIO]\nThe major device number of \n.I special\nis out of range (this indicates no device driver exists\nfor the associated hardware).\n.TP 15\n[EROFS]\n.I File\nresides on a read-only file system.\n.TP 15\n[EACCES]\nSearch permission is denied for a component of either path prefix.\n.TP 15\n[EACCES]\n.I File\nresides on a file system different from\n.IR special .\n.TP 15\n[EACCES]\n.I File\nis not a plain file.\n.TP 15\n[EIO]\nAn I/O error occurred while reading from or writing to the file containing\nthe quotas.\n.TP 15\n[EFAULT]\n.I Special\nor \\fIpath\\fP points outside the process's allocated address space.\n.SH BUGS\nThe error codes are in a state of disarray; too many errors\nappear to the caller as one value.\n"
  },
  {
    "path": "share/man/man2/setregid.2",
    "content": ".\\\" Copyright (c) 1980, 1991, 1993, 1994\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)setregid.2\t8.2.1 (2.11BSD) 1997/12/2\n.\\\"\n.TH SETREGID 2 \"December 2, 1997\"\n.UC 5\n.SH NAME\n\\fBsetregid\\fP \\- set real and effective group ID\n.SH SYNOPSIS\n.B #include <unistd.h>\n.sp\n.nf\n\\fIint\\fP\n\\fBsetregid(rgid, egid)\\fP\n\\ \\ \\ \\ \\ gid_t rgid, egid\n.fi\n.SH DESCRIPTION\nThe real and effective group ID's of the current process\nare set to the arguments.\nUnprivileged users may change the real group\nID to the effective group ID and vice-versa; only the super-user may\nmake other changes.\n.PP\nSupplying a value of -1 for either the real or effective\ngroup ID forces the system to substitute the current\nID in place of the -1 parameter.\n.PP\nThe\n.B setregid\nfunction was intended to allow swapping\nthe real and effective group IDs\nin set-group-ID programs to temporarily relinquish the set-group-ID value.\nThis function did not work correctly,\nand its purpose is now better served by the use of the\n.B setegid\nfunction (see setuid(2)).\n.PP\nWhen setting the real and effective group IDs to the same value,\nthe standard\n.B setgid\nfunction is preferred.\n.SH RETURN VALUES\nUpon successful completion, a value of 0 is returned.  Otherwise,\na value of -1 is returned and\n.I errno\nis set to indicate the error.\n.SH ERRORS\n.TP 10\nEPERM\nThe current process is not the super-user and a change\nother than changing the effective group-id to the real group-id\nwas specified.\n.SH SEE ALSO\ngetgid(2), setegid(2), setgid(2), setuid(2)\n.SH HISTORY\nThe\n.B setregid\nfunction call appeared in 4.2BSD\nand was dropped in 4.4BSD.\n"
  },
  {
    "path": "share/man/man2/setreuid.2",
    "content": ".\\\" Copyright (c) 1980, 1991, 1993, 1994\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)setreuid.2\t8.2.1 (2.11BSD) 1997/12/3\n.\\\"\n.TH SETREUID 2 \"December 3, 1997\"\n.UC 4\n.SH NAME\n\\fBsetreuid\\fP \\- set real and effective user ID's\n.SH SYNOPSIS\n.B #include <unistd.h>\n.nf\n.sp\n\\fIint\\fP\n\\fBsetreuid\\fP(ruid, euid)\n\\ \\ \\ \\ uid_t ruid, euid\n.fi\n.SH DESCRIPTION\nThe real and effective user IDs of the\ncurrent process are set according to the arguments.\nIf\n.I ruid\nor \n.I euid\nis -1, the current uid is filled in by the system.\nUnprivileged users may change the real user\nID to the effective user ID and vice-versa; only the super-user may\nmake other changes.\n.PP\nThe\n.B setreuid\nfunction has been used to swap the real and effective user IDs\nin set-user-ID programs to temporarily relinquish the set-user-ID value.\nThis purpose is now better served by the use of the\n.B seteuid\nfunction (see setuid(2)).\n.PP\nWhen setting the real and effective user IDs to the same value,\nthe standard\n.B setuid\nfunction is preferred.\n.SH RETURN VALUES\nUpon successful completion, a value of 0 is returned.  Otherwise,\na value of -1 is returned and\n.I errno\nis set to indicate the error.\n.SH ERRORS\n.TP 10\nEPERM\nThe current process is not the super-user and a change\nother than changing the effective user-id to the real user-id\nwas specified.\n.SH SEE ALSO\ngetuid(2), seteuid(2), setuid(2)\n.SH HISTORY\nThe\n.B setreuid\nfunction call appeared in 4.2BSD\nand was dropped in\n4.4BSD.\n"
  },
  {
    "path": "share/man/man2/setuid.2",
    "content": ".\\\" Copyright (c) 1983, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)setuid.2\t8.1.1 (2.11BSD) 1997/12/3\n.\\\"\n.TH SETUID 2 \"December 3, 1997\"\n.UC 5\n.SH NAME\n\\fBsetuid\\fP, \\fBseteuid\\fP,\\fBsetgid\\fP,\\fBsetegid\\fP \\- set user and group ID\n.SH SYNOPSIS\n.nf\n.B #include <sys/types.h>\n.B #include <unistd.h>\n.sp\n\\fIint\\fP\n\\fBsetuid\\fP(uid)\n\\ \\ \\ \\ uid_t uid\n.sp\n\\fIint\\fP\n\\fBseteuid\\fP(euid)\n\\ \\ \\ \\ uid_t euid\n.sp\n\\fIint\\fP\n\\fBsetgid\\fP(gid)\n\\ \\ \\ \\ gid_t gid\n.sp\n\\fIint\\fP\n\\fBsetegid\\fP(egid)\n\\ \\ \\ \\ gid_t egid\n.fi\n.SH DESCRIPTION\nThe\n.B setuid\nfunction\nsets the real and effective\nuser IDs and the saved set-user-ID of the current process\nto the specified value.\nThe\n.B setuid\nfunction is permitted if the specified ID is equal to the real user ID\nof the process, or if the effective user ID is that of the super user.\n.PP\nThe\n.B setgid\nfunction\nsets the real and effective\ngroup IDs and the saved set-group-ID of the current process\nto the specified value.\nThe\n.B setgid\nfunction is permitted if the specified ID is equal to the real group ID\nof the process, or if the effective user ID is that of the super user.\n.PP\nThe\n.B seteuid\nfunction\n(\\fBsetegid\\fP)\nsets the effective user ID (group ID) of the\ncurrent process.\nThe effective user ID may be set to the value\nof the real user ID or the saved set-user-ID (see\nintro(2)\nand\nexecve(2);\nin this way, the effective user ID of a set-user-ID executable\nmay be toggled by switching to the real user ID, then re-enabled\nby reverting to the set-user-ID value.\nSimilarly, the effective group ID may be set to the value\nof the real group ID or the saved set-user-ID.\n.PP\n.SH RETURN VALUES\nUpon success, these functions return 0;\notherwise \\-1 is returned.\n.PP\nIf the user is not the super user, or the uid\nspecified is not the real, effective ID, or saved ID,\nthese functions return \\-1.\n.SH SEE ALSO\ngetuid(2), getgid(2)\n.SH STANDARDS\nThe\n.B setuid\nand\n.B setgid\nfunctions are compliant with the\nIEEE Std 1003.1-1988 (``POSIX'')\nspecification with\n_POSIX_SAVED_IDS\nnot defined.\nThe\n.B seteuid\nand\n.B setegid\nfunctions are extensions based on the \nPOSIX\nconcept of\n_POSIX_SAVED_IDS ,\nand have been proposed for a future revision of the standard.\n"
  },
  {
    "path": "share/man/man2/shutdown.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)shutdown.2\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH SHUTDOWN 2 \"May 15, 1985\"\n.UC 5\n.SH NAME\nshutdown \\- shut down part of a full-duplex connection\n.SH SYNOPSIS\n.nf\n.ft B\nshutdown(s, how)\nint s, how;\n.fi\n.SH DESCRIPTION\nThe\n.I shutdown\ncall causes all or part of a full-duplex connection on\nthe socket associated with\n.I s\nto be shut down.\nIf \\fIhow\\fP is 0, then further receives will be disallowed.\nIf \\fIhow\\fP is 1, then further sends will be disallowed.\nIf \\fIhow\\fP is 2, then further sends and receives will be disallowed.\n.SH DIAGNOSTICS\nA 0 is returned if the call succeeds, \\-1 if it fails.\n.SH ERRORS\nThe call succeeds unless:\n.TP 15\n[EBADF]\n.I S\nis not a valid descriptor.\n.TP 15\n[ENOTSOCK]\n.I S\nis a file, not a socket.\n.TP 15\n[ENOTCONN]\nThe specified socket is not connected.\n.SH \"SEE ALSO\"\nconnect(2), socket(2)\n"
  },
  {
    "path": "share/man/man2/sigaction.2",
    "content": ".\\\" Copyright (c) 1980, 1990, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"\t@(#)sigaction.2\t8.2.1 (2.11BSD) 1997/9/3\n.\\\"\n.TH SIGACTION 2 \"September 3, 1997\"\n.UC 7\n.SH NAME\n\\fBsigaction\\fP \\- software signal facilities\n.SH SYNOPSIS\n.B #include <signal.h>\n.sp\n.nf\nstruct sigaction {\n\tint     (*sa_handler)();\n\tsigset_t sa_mask;\n\tint\t sa_flags;\n};\n.fi\n.sp\n\\fBsigaction\\fP(sig, act, oact)\n.br\n.I int sig;\n.br\n.I struct sigaction *act;\n.br\n.I struct sigaction *oact;\n.SH DESCRIPTION\nThe system defines a set of signals that may be delivered to a process.\nSignal delivery resembles the occurrence of a hardware interrupt:\nthe signal is blocked from further occurrence, the current process \ncontext is saved, and a new one is built.  A process may specify a\n.I handler\nto which a signal is delivered, or specify that a signal is to be \n.IR ignored .\nA process may also specify that a default action is to be taken\nby the system when a signal occurs.\nA signal may also be\n.IR blocked ,\nin which case its delivery is postponed until it is\n.IR unblocked .\nThe action to be taken on delivery is determined at the time\nof delivery.\nNormally, signal handlers execute on the current stack\nof the process.  This may be changed, on a per-handler basis,\nso that signals are taken on a special\n.IR \"signal stack\" .\n.PP\nSignal routines execute with the signal that caused their\ninvocation\n.IR blocked ,\nbut other signals may yet occur.\nA global \n.IR \"signal mask\"\ndefines the set of signals currently blocked from delivery\nto a process.  The signal mask for a process is initialized\nfrom that of its parent (normally empty).  It\nmay be changed with a\n.BR sigprocmask (2)\ncall, or when a signal is delivered to the process.\n.PP\nWhen a signal\ncondition arises for a process, the signal is added to a set of\nsignals pending for the process.\nIf the signal is not currently\n.I blocked\nby the process then it is delivered to the process.\nSignals may be delivered any time a process enters the operating system\n(e.g., during a system call, page fault or trap, or clock interrupt).\nIf multiple signals are ready to be delivered at the same time,\nany signals that could be caused by traps are delivered first.\nAdditional signals may be processed at the same time, with each\nappearing to interrupt the handlers for the previous signals\nbefore their first instructions.\nThe set of pending signals is returned by the\n.BR sigpending (2)\nfunction.\nWhen a caught signal\nis delivered, the current state of the process is saved,\na new signal mask is calculated (as described below), \nand the signal handler is invoked.  The call to the handler\nis arranged so that if the signal handling routine returns\nnormally the process will resume execution in the context\nfrom before the signal's delivery.\nIf the process wishes to resume in a different context, then it\nmust arrange to restore the previous context itself.\n.PP\nWhen a signal is delivered to a process a new signal mask is\ninstalled for the duration of the process' signal handler\n(or until a\n.B sigprocmask\ncall is made).\nThis mask is formed by taking the union of the current signal mask set,\nthe signal to be delivered, and \nthe signal mask associated with the handler to be invoked.\n.PP\n.B Sigaction\nassigns an action for a specific signal.\nIf\n.I act\nis non-zero, it\nspecifies an action\n(SIG_DFL,\nSIG_IGN,\nor a handler routine) and mask\nto be used when delivering the specified signal.\nIf \n.I oact\nis non-zero, the previous handling information for the signal\nis returned to the user.\n.PP\nOnce a signal handler is installed, it remains installed\nuntil another\n.B sigaction\ncall is made, or an \n.BR execve (2)\nis performed.\nA signal-specific default action may be reset by\nsetting\n.I sa_handler\nto\nSIG_DFL.\nThe defaults are process termination, possibly with core dump;\nno action; stopping the process; or continuing the process.\nSee the signal list below for each signal's default action.\nIf\n.I sa_handler\nis\nSIG_DFL,\nthe default action for the signal is to discard the signal,\nand if a signal is pending,\nthe pending signal is discarded even if the signal is masked.\nIf\n.I sa_handler\nis set to\nSIG_IGN\ncurrent and pending instances\nof the signal are ignored and discarded.\n.PP\nOptions may be specified by setting\n.IR sa_flags .\nIf the\nSA_NOCLDSTOP\nbit is set when installing a catching function\nfor the\nSIGCHLD\nsignal,\nthe\nSIGCHLD\nsignal will be generated only when a child process exits,\nnot when a child process stops.\nFurther, if the\nSA_ONSTACK\nbit is set in\n.IR sa_flags ,\nthe system will deliver the signal to the process on a\n.IR \"signal stack\" ,\nspecified with\n.BR sigstack (2).\n.PP\nIf a signal is caught during the system calls listed below,\nthe call may be forced to terminate\nwith the error\nEINTR,\nthe call may return with a data transfer shorter than requested,\nor the call may be restarted.\nRestart of pending calls is requested\nby setting the\nSA_RESTART\nbit in\n.IR sa_flags .\nThe affected system calls include\n.BR open (2),\n.BR read (2),\n.BR write (2),\n.BR sendto (2),\n.BR recvfrom (2),\n.BR sendmsg (2)\nand\n.BR recvmsg (2)\non a communications channel or a slow device (such as a terminal,\nbut not a regular file)\nand during a\n.BR wait (2)\nor\n.BR ioctl (2).\nHowever, calls that have already committed are not restarted,\nbut instead return a partial success (for example, a short read count).\n.PP\nAfter a\n.BR fork (2)\nor\n.BR vfork (2)\nall signals, the signal mask, the signal stack,\nand the restart/interrupt flags are inherited by the child.\n.PP\n.BR Execve (2)\nreinstates the default\naction for all signals which were caught and\nresets all signals to be caught on the user stack.\nIgnored signals remain ignored;\nthe signal mask remains the same;\nsignals that restart pending system calls continue to do so.\n.PP\nThe following is a list of all signals\nwith names as in the include file\n.RI < signal.h >:\n.LP\n.in +0.5i\n.\\\" BE VERY VERY CAREFUL (and do not cut/paste in an xterm) below.  There are\n.\\\" embedded tabs present.\n.ta \\w'SIGVTALRMxx'u +\\w'terminatexxx'u\nNAME\tAction\tDescription\n.br\nSIGHUP\tterminate\tterminal line hangup\n.br\nSIGINT\tterminate\tinterrupt program\n.br\nSIGQUIT\tcore\tquit program\n.br\nSIGILL\tcore\tillegal instruction\n.br\nSIGTRAP\tcore\ttrace trap\n.br\nSIGIOT\tcore\tabort(2) call (same as SIGABRT)\n.br\nSIGEMT\tcore\temulate instruction executed\n.br\nSIGFPE\tcore\tfloating-point exception\n.br\nSIGKILL\tterminate\tkill program\n.br\nSIGBUS\tcore\tbus error\n.br\nSIGSEGV\tcore\tsegmentation violation\n.br\nSIGSYS\tcore\tsystem call given invalid argument\n.br\nSIGPIPE\tterminate\twrite on a pipe with no reader\n.br\nSIGALRM\tterminate\treal-time timer expired\n.br\nSIGTERM\tterminate\tsoftware termination signal\n.br\nSIGURG\tdiscard\turgent condition present on socket\n.br\nSIGSTOP\tstop\tstop (cannot be caught or ignored)\n.br\nSIGTSTP\tstop\tstop generated from keyboard\n.br\nSIGCONT\tdiscard\tcontinue after stop\n.br\nSIGCHLD\tdiscard\tchild status has changed\n.br\nSIGTTIN\tstop\tbackground read attempted on control terminal\n.br\nSIGTTOU\tstop\tbackground write attemped to control terminal\n.br\nSIGIO\tdiscard\tI/O is possible on a descriptor (see fcntl(2))\n.br\nSIGXCPU\tterminate\tcpu time limit exceeded (see setrlimit(2))\n.br\nSIGXFSZ\tterminate\tfile size limit exceeded (see setrlimit(2))\n.br\nSIGVTALRM\tterminate\tvirtual time alarm (see setitimer(2))\n.br\nSIGPROF\tterminate\tprofiling timer alarm (see setitimer(2))\n.br\nSIGWINCH\tdiscard\tWindow size change\n.br\nSIGINFO\tdiscard\tstatus request from keyboard\n.br\nSIGUSR1\tterminate\tUser defined signal 1\n.br\nSIGUSR2\tterminate\tUser defined signal 2\n.br\n.in -0.5i\n.SH NOTE\nThe mask specified in \n.I act\nis not allowed to block\nSIGKILL\nor\nSIGSTOP.\nThis is done silently by the system.\n.SH RETURN VALUES\nA 0 value indicated that the call succeeded.  A \\-1 return value\nindicates an error occurred and\n.I errno\nis set to indicated the reason.\n.SH EXAMPLE\nThe handler routine can be declared:\n.sp\n.nf\nint handler(sig, code, scp)\nint sig, code;\nstruct sigcontext *scp;\n.fi\n.PP\nHere\n.I sig\nis the signal number, into which the hardware faults and traps are\nmapped.\n.I Code\nis a parameter that is either a constant\nor the code provided by\nthe hardware.\n.I Scp\nis a pointer to the\n.I sigcontext\nstructure (defined in\n.RI < signal.h >,\nused to restore the context from before the signal.\n.SH ERRORS\n.B Sigaction\nwill fail and no new signal handler will be installed if one\nof the following occurs:\n.TP 20\nEFAULT\nEither\n.I act\nor \n.I oact\npoints to memory that is not a valid part of the process\naddress space.\n.TP 20\nEINVAL\n.I Sig\nis not a valid signal number.\n.TP 20\nEINVAL\nAn attempt is made to ignore or supply a handler for\nSIGKILL\nor\nSIGSTOP.\n.SH STANDARDS\nThe\n.B sigaction\nfunction is defined by\nIEEE Std1003.1-1988 (``POSIX'').\nThe\nSA_ONSTACK\nand\nSA_RESTART\nflags are Berkeley extensions,\nas are the signals,\nSIGTRAP,\nSIGEMT,\nSIGBUS,\nSIGSYS,\nSIGURG,\nSIGIO,\nSIGXCPU,\nSIGXFSZ,\nSIGVTALRM,\nSIGPROF,\nSIGWINCH,\nand\nSIGINFO.\nThose signals are available on most\nBSD\\-derived\nsystems.\n.SH BUGS\nThe networking related syscalls are not properly restarted in 2.11BSD.  The\nSIGINFO signal is not implemented in 2.11BSD.\n.SH SEE ALSO\nkill(1),\nfcntl(2),\nptrace(2),\nkill(2),\nsetitimer(2),\nsetrlimit(2),\nsigaction(2),\nsigprocmask(2),\nsigsuspend(2),\nsigblock(2),\nsigsetmask(2),\nsigpause(2),\nsigstack(2),\nsigvec(2),\nsetjmp(3),\nsiginterrupt(3),\nsigsetops(3),\ntty(4)\n"
  },
  {
    "path": "share/man/man2/sigaltstack.2",
    "content": ".\\\" Copyright (c) 1983, 1991, 1992, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)sigaltstack.2\t8.2.1 (2.11BSD) 1997/9/3\n.\\\"\n.TH SIGALTSTACK 2 \"September 3, 1997\"\n.UC 7\n.SH NAME\n\\fBsigaltstack\\fP \\- set and/or get signal stack context\n.SH SYNOPSIS\n.B #include <sys/types.h>\n.br\n.B #include <signal.h>\n.sp\n.nf\nstruct sigaltstack {\n\tcaddr_t ss_base;\n\tint\tss_size;\n\tint     ss_flags;\n};\n.fi\n.sp\n.I int\n.br\n\\fBsigaltstack\\fP(ss, oss)\n.br\n.I struct sigaltstack *ss;\n.br\n.I struct sigaltstack *oss;\n.SH DESCRIPTION\n.B Sigaltstack\nallows users to define an alternate stack on which signals\nare to be processed.\nIf\n.I ss\nis non-zero,\nit specifies a pointer to and the size of a\n.I \"signal stack\"\non which to deliver signals,\nand tells the system if the process is currently executing\non that stack.\nWhen a signal's action indicates its handler\nshould execute on the signal stack (specified with a\n.BR sigaction (2)\ncall), the system checks to see\nif the process is currently executing on that stack.\nIf the process is not currently executing on the signal stack,\nthe system arranges a switch to the signal stack for the\nduration of the signal handler's execution. \n.PP\nIf\nSA_DISABLE\nis set in\n.IR ss_flags ,\n.IR ss_base\nand\n.IR ss_size\nare ignored and the signal stack will be disabled.\nTrying to disable an active stack will cause\n.B sigaltstack\nto return -1 with\n.I errno\nset to\nEINVAL.\nA disabled stack will cause all signals to be\ntaken on the regular user stack.\nIf the stack is later re-enabled then all signals that were specified\nto be processed on an alternate stack will resume doing so.\n.PP\nIf\n.I oss\nis non-zero, the current signal stack state is returned.\nThe\n.I ss_flags\nfield will contain the value\nSA_ONSTACK\nif the process is currently on a signal stack and\nSA_DISABLE\nif the signal stack is currently disabled.\n.SH NOTES\nThe value\nSIGSTKSZ\nis defined to be the number of bytes/chars that would be used to cover\nthe usual case when allocating an alternate stack area.\nThe following code fragment is typically used to allocate an alternate stack.\n.sp\n.nf\nif ((sigstk.ss_base = malloc(SIGSTKSZ)) == NULL)\n\t/* error return */\nsigstk.ss_size = SIGSTKSZ;\nsigstk.ss_flags = 0;\nif (sigaltstack(&sigstk,0) < 0)\n\tperror(\"sigaltstack\");\n.fi\n.sp\nAn alternative approach is provided for programs with signal handlers\nthat require a specific amount of stack space other than the default size.\nThe value\nMINSIGSTKSZ\nis defined to be the number of bytes/chars that is required by\nthe operating system to implement the alternate stack feature.\nIn computing an alternate stack size,\nprograms should add\nMINSIGSTKSZ\nto their stack requirements to allow for the operating system overhead.\n.PP\nSignal stacks are automatically adjusted for the direction of stack\ngrowth and alignment requirements.\nSignal stacks may or may not be protected by the hardware and\nare not ``grown'' automatically as is done for the normal stack.\nIf the stack overflows and this space is not protected\nunpredictable results may occur.\n.SH RETURN VALUES\nUpon successful completion, a value of 0 is returned.\nOtherwise, a value of -1 is returned and \n.I errno\nis set to indicate the error.\n.SH ERRORS\n.B Sigaltstack\nwill fail and the signal stack context will remain unchanged\nif one of the following occurs.\n.TP 20\nEFAULT\nEither\n.I ss\nor\n.I oss\npoints to memory that is not a valid part of the process\naddress space.\n.TP 20\nEINVAL\nAn attempt was made to disable an active stack.\n.TP 20\nENOMEM\nSize of alternate stack area is less than or equal to\nMINSIGSTKSZ .\n.SH SEE ALSO\nsigaction(2), setjmp(3)\n.SH HISTORY\nThe predecessor to\n.BR sigaltstack ,\nthe\n.B sigstack\nsystem call, appeared in 4.2BSD.\n"
  },
  {
    "path": "share/man/man2/sigblock.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)sigblock.2\t6.3.1 (2.11BSD) 97/9/2\n.\\\"\n.TH SIGBLOCK 2 \"September 2, 1997\"\n.UC 5\n.SH NAME\nsigblock \\- block signals\n.SH SYNOPSIS\n.nf\n.B #include <signal.h>\n\n\\fIomask\\fP = \\fBsigblock\\fP(\\fImask\\fP);\nlong \\fIomask, mask\\fP;\n\n\\fImask\\fP = \\fBsigmask\\fP(\\fIsignum\\fP)\nlong \\fImask\\fP;\nint \\fIsignum\\fP;\n.SH DESCRIPTION\n.B This interface is made obsolete by:\nsigprocmask(2).\n.PP\n.B Sigblock\ncauses the signals specified in\n.I mask\nto be added to the set of signals currently\nbeing blocked from delivery.\nSignals are blocked if the\ncorresponding bit in \n.I mask\nis a 1; the macro\n.B sigmask\nis provided to construct the mask for a given\n.IR signum .\n.PP\nIt is not possible to block SIGKILL,\nSIGSTOP, or SIGCONT;  this restriction is silently\nimposed by the system.\n.SH \"RETURN VALUE\nThe previous set of masked signals is returned.\n.SH \"SEE ALSO\"\nkill(2), sigprocmask(2), sigaction(2), sigsetmask(2), sigsetops(2)\n.SH \"HISTORY\"\nThe \\fBsigblock\\fP function call appeared in 4.2BSD and has been\ndeprecated.\n"
  },
  {
    "path": "share/man/man2/sigpause.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)sigpause.2\t6.2.1 (2.11BSD) 97/9/2\n.\\\"\n.TH SIGPAUSE 2 \"September 2, 1997\"\n.UC 4\n.SH NAME\nsigpause \\- atomically release blocked signals and wait for interrupt\n.SH SYNOPSIS\n\\fBsigpause\\fP(\\fIsigmask\\fP)\n.br\nlong \\fIsigmask\\fP;\n.SH DESCRIPTION\n.B This interface is made obsolete by:\nsigsuspend(2).\n.PP\n.B Sigpause()\nassigns \n.I sigmask\nto the set of masked signals\nand then waits for a signal to arrive;\non return the set of masked signals is restored.\n.I Sigmask\nis usually 0L to indicate that no\nsignals are now to be blocked.\n.B Sigpause\nalways terminates by being interrupted, returning \\-1 with\n.I errno\nset to EINTR.\n.SH SEE ALSO\nsigsuspend(2), kill(2), sigaction(2), sigprocmask(2), sigblock(2),\nsigvec(2)\n.SH HISTORY\nThe\n.B sigpause\nfunction call appeared in 4.2BSD and has been deprecated.\n"
  },
  {
    "path": "share/man/man2/sigpending.2",
    "content": ".\\\" Copyright (c) 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" This code is derived from software contributed to Berkeley by\n.\\\" Berkeley Software Design, Inc.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"\t@(#)sigpending.2\t8.3.1 (2.11BSD) 1997/9/3\n.\\\"\n.TH SIGPENDING 2 \"September 3, 1997\"\n.UC 7\n.SH NAME\n\\fBsigpending\\fP \\- get pending signals\n.SH SYNOPSIS\n.B #include <signal.h>\n.sp\n.I int\n.br\n\\fBsigpending\\fP(set)\n.br\n.I sigset_t *set;\n.SH DESCRIPTION\nThe\n.B sigpending\nfunction returns a mask of the signals pending for delivery\nto the calling process in the location indicated by\n.IR set .\nSignals may be pending because they are currently masked,\nor transiently before delivery (although the latter case is not\nnormally detectable).\n.SH RETURN VALUES\nA 0 value indicated that the call succeeded.  A \\-1 return value\nindicates an error occurred and\n.I errno\nis set to indicated the reason.\n.SH ERRORS\nIf\n.B sigpending\nfails then \\fIerrno\\fP will contain one of the following:\n.sp\n.TP 20\n[EFAULT]\n.I set\ncontains an invalid address.\n.SH SEE ALSO\nsigaction(2), sigprocmask(2)\n.SH STANDARDS\nThe\n.B sigpending\nfunction is defined by\nIEEE Std1003.1-1988 (``POSIX'').\n"
  },
  {
    "path": "share/man/man2/sigprocmask.2",
    "content": ".\\\" Copyright (c) 1983, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"\t@(#)sigprocmask.2\t8.1.1 (2.11BSD) 1997/9/3\n.\\\"\n.TH SIGPROCMASK 2 \"September 3, 1997\"\n.UC 7\n.SH NAME\n\\fBsigprocmask\\fP \\- manipulate current signal mask\n.SH SYNOPSIS\n.B #include <signal.h>\n.sp\n.I int\n.br\n\\fBsigprocmask\\fP(how, set, oset)\n.br\n.I int how;\n.br\n.I sigset_t *set;\n.br\n.I sigset_t *oset;\n.sp\n.I sigset_t\n.br\n\\fBsigmask\\fP(signum)\n.br\n.I int signum;\n.SH DESCRIPTION\nThe\n.B sigprocmask\nfunction examines and/or changes the current signal mask (those signals\nthat are blocked from delivery).\nSignals are blocked if they are members of the current signal mask set.\n.PP\nIf\n.I set\nis not null, the action of\n.B sigprocmask\ndepends on the value of the parameter\n.IR how .\nThe signal mask is changed as a function of the specified\n.I set\nand the current mask.\nThe function is specified by\n.I how\nusing one of the following values from\n.RI < signal.h >:\n.TP 20\nSIG_BLOCK\nThe new mask is the union of the current mask and the specified\n.IR set .\n.TP 20\nSIG_UNBLOCK\nThe new mask is the intersection of the current mask\nand the complement of the specified\n.IR set .\n.TP 20\nSIG_SETMASK\nThe current mask is replaced by the specified\n.IR set .\n.PP\nIf\n.I oset\nis not null, it is set to\nthe previous value of the signal mask.\nWhen\n.I set\nis null,\nthe value of\n.I how\nis insignificant and the mask remains unset\nproviding a way to examine the signal mask without modification.\n.PP\nThe system\nquietly disallows\nSIGKILL\nor\nSIGSTOP\nto be blocked.\n.SH RETURN VALUES\nA 0 value indicated that the call succeeded.  A -1 return value\nindicates an error occurred and\n.I errno\nis set to indicated the reason.\n.SH ERRORS\nThe\n.B sigprocmask\ncall will fail and the signal mask will be unchanged if one\nof the following occurs:\n.TP 20\nEINVAL\n.I how\nhas a value other than those listed here.\n.TP 20\nEFAULT\n.I set\nor \n.I oset\ncontain an invalid address.\n.SH SEE ALSO\nkill(2), sigaction(2), sigsetops(3), sigsuspend(2)\n.SH STANDARDS\nThe\n.B sigprocmask\nfunction call is expected to\nconform to\nIEEE Std1003.1-1988 (``POSIX'').\n"
  },
  {
    "path": "share/man/man2/sigreturn.2",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)sigreturn.2\t6.2 (Berkeley) 6/30/85\n.\\\"\n.TH SIGRETURN 2 \"June 30, 1985\"\n.UC 6\n.SH NAME\nsigreturn \\- return from signal\n.SH SYNOPSIS\n.nf\n.B #include <signal.h>\n.PP\n.B struct\tsigcontext {\n.B \tint\tsc_onstack;\n.B \tlong\tsc_mask;\n.B \tint\tsc_sp;\n.B \tint\tsc_fp;\n.B \tint\tsc_ap;\n.B \tint\tsc_pc;\n.B \tint\tsc_ps;\n.B };\n.PP\n.B sigreturn(scp);\n.B struct sigcontext *scp;\n.SH DESCRIPTION\n.I Sigreturn\nallows users to atomically unmask, switch stacks,\nand return from a signal context.\nThe processes signal mask and stack status are\nrestored from the context.\nThe system call does not return;\nthe users stack pointer, frame pointer, argument pointer,\nand processor status longword are restored from the context.\nExecution resumes at the specified pc.\nThis system call is used by the trampoline code, and\n.IR longjmp (3)\nwhen returning from a signal to the previously executing program.\n.SH NOTES\nThis system call is not available in 4.2BSD,\nhence it should not be used if backward compatibility is needed.\n.PP\nThe definition of the\n.I sigcontext\nstructure is machine dependent (the structure cited above is that for a VAX\nrunning 4.3BSD); no program should depend on its internal structure.\n.IR Setjmp (3)\nmay be used to build sigcontext structures in a machine independent manner.\n.SH \"RETURN VALUE\nIf successful, the system call does not return.\nOtherwise, a value of \\-1 is returned and \n.I errno\nis set to indicate the error.\n.SH ERRORS\n.I Sigreturn\nwill fail and the process context will remain unchanged\nif one of the following occurs.\n.TP 15\n[EFAULT]\n.I Scp\npoints to memory that is not a valid part of the process\naddress space.\n.TP\n[EINVAL]\nThe process status longword is invalid or would improperly\nraise the privilege level of the process.\n.SH \"SEE ALSO\"\nsigvec(2), setjmp(3)\n.SH \"NOTES  (PDP-11)\"\nOn the PDP-11 the field \\fIsc_ap\\fP (argument pointer) does not exist and\nthe field \\fIsc_fp\\fP (frame pointer) is the PDP-11 register \\fIr5\\fP.\nAdditionally, three new fields \\fIsc_r0\\fP, \\fIsc_r1\\fP and \\fIsc_ovno\\fP are\npresent on the PDP-11 which hold register values r0 and r1 and the text\noverlay number to restore (see \\fIld\\fP(1)).\n.nf\n.ta \\w' struct 'u +\\w'long  'u +\\w'sc_onstack  'u\n.PP\n.B struct\tsigcontext {\n.B \tint\tsc_onstack;\t\t/* sigstack state to restore */\n.B \tlong\tsc_mask;\t\t/* signal mask to restore */\n.B \tint\tsc_sp;\t\t\t/* sp to restore */\n.B \tint\tsc_fp;\t\t\t/* fp to restore */\n.B \tint\tsc_r1;\t\t\t/* r1 to restore */\n.B \tint\tsc_r0;\t\t\t/* r0 to restore */\n.B \tint\tsc_pc;\t\t\t/* pc to restore */\n.B \tint\tsc_ps;\t\t\t/* psl to restore */\n.B \tint\tsc_ovno\t\t\t/* overlay to restore */\n.B };\n"
  },
  {
    "path": "share/man/man2/sigsetmask.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)sigsetmask.2\t6.3.1 (2.11BSD) 97/9/3\n.\\\"\n.TH SIGSETMASK 2 \"September 3, 1997\"\n.UC 5\n.SH NAME\nsigsetmask \\- set current signal mask\n.SH SYNOPSIS\n.nf\n.B #include <signal.h>\n\n.B omask = sigsetmask(mask);\n.B long omask, mask;\n\n.B mask = sigmask(signum)\n.B long mask;\n.B int signum;\n.SH DESCRIPTION\n.B This interface is made obsolete by:\n.sigprocmask(2).\n.sp\n.I Sigsetmask\nsets the current signal mask (those signals\nthat are blocked from delivery).\nSignals are blocked if the\ncorresponding bit in \n.I mask\nis a 1; the macro\n.I sigmask\nis provided to construct the mask for a given\n.IR signum .\n.PP\nThe system\nquietly disallows SIGKILL, SIGSTOP, or SIGCONT to\nbe blocked.\n.SH \"RETURN VALUE\nThe previous set of masked signals is returned.\n.SH \"SEE ALSO\"\nkill(2), sigvec(2), sigblock(2), sigpause(2)\n.SH HISTORY\nThe\n.B sigsetmask\nfunction call appeared in 4.2BSD and has been deprecated.\n"
  },
  {
    "path": "share/man/man2/sigstack.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)sigstack.2\t6.2.1 (2.11BSD) 97/9/3\n.\\\"\n.TH SIGSTACK 2 \"September 3, 1997\"\n.UC 5\n.SH NAME\nsigstack \\- set and/or get signal stack context\n.SH SYNOPSIS\n.nf\n.B #include <signal.h>\n.PP\n.B struct sigstack {\n.B\tcaddr_t\tss_sp;\n.B\tint\tss_onstack;\n.B };\n.PP\n.B sigstack(ss, oss);\n.B struct sigstack *ss, *oss;\n.SH DESCRIPTION\n.B This interface has been made obsolete by:\nsigaltstack(2).\n.sp\n.I Sigstack\nallows users to define an alternate stack on which signals\nare to be processed.  If\n.I ss\nis non-zero,\nit specifies a\n.I \"signal stack\"\non which to deliver signals\nand tells the system if the process is currently executing\non that stack.  When a signal's action indicates its handler\nshould execute on the signal stack (specified with a\n.IR sigvec (2)\ncall), the system checks to see\nif the process is currently executing on that stack.  If the\nprocess is not currently executing on the signal stack,\nthe system arranges a switch to the signal stack for the\nduration of the signal handler's execution. \nIf\n.I oss\nis non-zero, the current signal stack state is returned.\n.SH NOTES\nSignal stacks are not ``grown'' automatically, as is\ndone for the normal stack.  If the stack overflows\nunpredictable results may occur.\n.SH \"RETURN VALUE\nUpon successful completion, a value of 0 is returned.\nOtherwise, a value of \\-1 is returned and \n.I errno\nis set to indicate the error.\n.SH ERRORS\n.I Sigstack\nwill fail and the signal stack context will remain unchanged\nif one of the following occurs.\n.TP 15\n[EFAULT]\nEither\n.I ss\nor\n.I oss\npoints to memory that is not a valid part of the process\naddress space.\n.SH \"SEE ALSO\"\nsigvec(2), setjmp(3)\n.SH HISTORY\nThe \n.B sigstack \nfunction call appeared in 4.2BSD and has been deprecated.\n"
  },
  {
    "path": "share/man/man2/sigsuspend.2",
    "content": ".\\\" Copyright (c) 1983, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"\t@(#)sigsuspend.2\t8.2.1 (2.11BSD) 1995/9/3\n.\\\"\n.TH SIGSUSPEND 2 \"September 3, 1997\"\n.UC 7\n.SH NAME\n\\fBsigsuspend\\fP \\- atomically release blocked signals and wait for interrupt\n.SH SYNOPSIS\n.B #include <signal.h>\n.sp\n.I int\n.br\n\\fBsigsuspend\\fP(sigmask)\n.br\n.I sigset_t *sigmask\n.SH DESCRIPTION\n.BR Sigsuspend ()\ntemporarily changes the blocked signal mask to the set to which\n.I sigmask\npoints,\nand then waits for a signal to arrive;\non return the previous set of masked signals is restored.\nThe signal mask set\nis usually empty to indicate that all\nsignals are to be unblocked for the duration of the call.\n.PP\nIn normal usage, a signal is blocked using\n.BR sigprocmask (2)\nto begin a critical section, variables modified on the occurrence\nof the signal are examined to determine that there is no work\nto be done, and the process pauses awaiting work by using\n.B sigsuspend\nwith the previous mask returned by\n.BR sigprocmask .\n.SH RETURN VALUES\nThe\n.B sigsuspend\nfunction\nalways terminates by being interrupted, returning -1 with\n.I errno\nset to\nEINTR.  If EFAULT is set in \\fIerrno\\fP then \\fIset\\fP contains an invalid\naddress.\n.SH SEE ALSO\nsigprocmask(2), sigaction(2), sigsetops(3)\n.SH STANDARDS\nThe\n.B sigsuspend\nfunction call\nconforms to\nIEEE Std1003.1-1988 (``POSIX'').\n"
  },
  {
    "path": "share/man/man2/sigvec.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)sigvec.2\t6.3.1 (2.11BSD) 97/9/3\n.\\\"\n.TH SIGVEC 2 \"September 3, 1997\"\n.UC 4\n.ie t .ds d \\(dg\n.el .ds d \\z'|+'\n.ie t .ds b \\(bu\n.el .ds b @\n.SH NAME\nsigvec \\- software signal facilities\n.SH SYNOPSIS\n.nf\n.B #include <signal.h>\n.PP\n.B struct sigvec {\n.B\tint\t(*sv_handler)();\n.B\tlong\tsv_mask;\n.B\tint\tsv_flags;\n.B };\n.PP\n.B sigvec(sig, vec, ovec)\n.B int sig;\n.B struct sigvec *vec, *ovec;\n.fi\n.SH DESCRIPTION\n.B This interface has been made obsolete by:\nsigaction(2).\n.sp\nThe system defines a set of signals that may be delivered to a process.\nSignal delivery resembles the occurence of a hardware interrupt:\nthe signal is blocked from further occurrence, the current process \ncontext is saved, and a new one is built.  A process may specify a\n.I handler\nto which a signal is delivered, or specify that a signal is to be \n.I blocked\nor\n.IR ignored .\nA process may also specify that a default action is to be taken\nby the system when a signal occurs.\nNormally, signal handlers execute on the current stack\nof the process.  This may be changed, on a per-handler basis,\nso that signals are taken on a special\n.IR \"signal stack\" .\n.PP\nAll signals have the same\n.IR priority .\nSignal routines execute with the signal that caused their\ninvocation\n.IR blocked ,\nbut other signals may yet occur.\nA global \n.I \"signal mask\"\ndefines the set of signals currently blocked from delivery\nto a process.  The signal mask for a process is initialized\nfrom that of its parent (normally 0).  It\nmay be changed with a\n.IR sigblock (2)\nor\n.IR sigsetmask (2)\ncall, or when a signal is delivered to the process.\n.PP\nWhen a signal\ncondition arises for a process, the signal is added to a set of\nsignals pending for the process.  If the signal is not currently\n.I blocked\nby the process then it is delivered to the process.  When a signal\nis delivered, the current state of the process is saved,\na new signal mask is calculated (as described below), \nand the signal handler is invoked.  The call to the handler\nis arranged so that if the signal handling routine returns\nnormally the process will resume execution in the context\nfrom before the signal's delivery.\nIf the process wishes to resume in a different context, then it\nmust arrange to restore the previous context itself.\n.PP\nWhen a signal is delivered to a process a new signal mask is\ninstalled for the duration of the process' signal handler\n(or until a\n.I sigblock\nor\n.I sigsetmask\ncall is made).\nThis mask is formed by taking the current signal mask,\nadding the signal to be delivered, and \n.IR or 'ing\nin the signal mask associated with the handler to be invoked.\n.PP\n.I Sigvec\nassigns a handler for a specific signal.  If\n.I vec\nis non-zero, it\nspecifies a handler routine and mask\nto be used when delivering the specified signal.\nFurther, if the SV_ONSTACK bit is set in\n.I sv_flags,\nthe system will deliver the signal to the process on a\n.IR \"signal stack\" ,\nspecified with\n.IR sigstack (2).\nIf \n.I ovec\nis non-zero, the previous handling information for the signal\nis returned to the user.\n.PP\nThe following is a list of all signals\nwith names as in the include file\n.RI < signal.h >:\n.LP\n.nf\n.ta \\w'SIGVTALRM 'u +\\w'15*  'u\nSIGHUP\t1\thangup\nSIGINT\t2\tinterrupt\nSIGQUIT\t3*\tquit\nSIGILL\t4*\tillegal instruction\nSIGTRAP\t5*\ttrace trap\nSIGIOT\t6*\tIOT instruction\nSIGEMT\t7*\tEMT instruction\nSIGFPE\t8*\tfloating point exception\nSIGKILL\t9\tkill (cannot be caught, blocked, or ignored)\nSIGBUS\t10*\tbus error\nSIGSEGV\t11*\tsegmentation violation\nSIGSYS\t12*\tbad argument to system call\nSIGPIPE\t13\twrite on a pipe with no one to read it\nSIGALRM\t14\talarm clock\nSIGTERM\t15\tsoftware termination signal\nSIGURG\t16\\*b\turgent condition present on socket\nSIGSTOP\t17\\*d\tstop (cannot be caught, blocked, or ignored)\nSIGTSTP\t18\\*d\tstop signal generated from keyboard\nSIGCONT\t19\\*b\tcontinue after stop (cannot be blocked)\nSIGCHLD\t20\\*b\tchild status has changed\nSIGTTIN\t21\\*d\tbackground read attempted from control terminal\nSIGTTOU\t22\\*d\tbackground write attempted to control terminal\nSIGIO\t23\\*b\ti/o is possible on a descriptor (see \\fIfcntl\\fP(2))\nSIGXCPU\t24\tcpu time limit exceeded (see \\fIsetrlimit\\fP(2))\nSIGXFSZ\t25\tfile size limit exceeded (see \\fIsetrlimit\\fP(2))\nSIGVTALRM\t26\tvirtual time alarm (see \\fIsetitimer\\fP(2))\nSIGPROF\t27\tprofiling timer alarm (see \\fIsetitimer\\fP(2))\nSIGWINCH\t28\\*b\twindow size change\nSIGUSR1\t30\tuser defined signal 1\nSIGUSR2\t31\tuser defined signal 2\n.fi\n.PP\nThe starred signals in the list above cause a core image\nif not caught or ignored.\n.PP\nOnce a signal handler is installed, it remains installed\nuntil another\n.I sigvec\ncall is made, or an \n.IR execve (2)\nis performed.\nThe default action for a signal may be reinstated by setting\n.I sv_handler\nto SIG_DFL; this default is termination\n(with a core image for starred signals)\nexcept for signals marked with \\*b or \\*d.\nSignals marked with \\*b are discarded if the action\nis SIG_DFL; signals marked\nwith \\*d cause the process to stop.\nIf\n.I sv_handler\nis SIG_IGN the signal is subsequently ignored,\nand pending instances of the signal are discarded.\n.PP\nIf a caught signal occurs during certain system calls,\nthe call is normally restarted.\nThe call can be forced to terminate prematurely with an\nEINTR error return by setting the SV_INTERRUPT bit in\n.I sv_flags.\nThe affected system calls are\n.IR read (2)\nor\n.IR write (2)\non a slow device (such as a terminal; but not a file)\nand during a\n.IR wait (2).\n.PP\nAfter a\n.IR fork (2)\nor\n.IR vfork (2)\nthe child inherits\nall signals, the signal mask, the signal stack,\nand the restart/interrupt flags.\n.PP\n.IR  Execve (2)\nresets all\ncaught signals to default action and\nresets all signals to be caught on the user stack.\nIgnored signals remain ignored;\nthe signal mask remains the same;\nsignals that interrupt system calls continue to do so.\n.SH NOTES\nThe mask specified in \n.I vec\nis not allowed to block SIGKILL, SIGSTOP, or SIGCONT.  This\nis done silently by the system.\n.PP\nThe SV_INTERRUPT flag is not available in 4.2BSD,\nhence it should not be used if backward compatibility is needed.\n.SH \"RETURN VALUE\nA 0 value indicated that the call succeeded.  A \\-1 return value\nindicates an error occurred and\n.I errno\nis set to indicated the reason.\n.SH ERRORS\n.I Sigvec\nwill fail and no new signal handler will be installed if one\nof the following occurs:\n.TP 15\n[EFAULT]\nEither\n.I vec\nor \n.I ovec\npoints to memory that is not a valid part of the process\naddress space.\n.TP 15\n[EINVAL]\n.I Sig\nis not a valid signal number.\n.TP 15\n[EINVAL]\nAn attempt is made to ignore or supply a handler for SIGKILL\nor SIGSTOP.\n.TP 15\n[EINVAL]\nAn attempt is made to ignore SIGCONT (by default SIGCONT\nis ignored).\n.SH \"SEE ALSO\"\nkill(1),\nptrace(2), kill(2),\nsigblock(2), sigsetmask(2), sigpause(2),\nsigstack(2), sigvec(2), setjmp(3), siginterrupt(3), tty(4)\n.SH \"NOTES  (VAX-11)\"\nThe handler routine can be declared:\n.PP\n    handler(sig, code, scp)\n    int sig, code;\n    struct sigcontext *scp;\n.PP\nHere\n.I sig\nis the signal number, into which the hardware faults and traps are\nmapped as defined below. \n.I Code\nis a parameter that is either a constant\nas given below or, for compatibility mode faults, the code provided by\nthe hardware (Compatibility mode faults are distinguished from the\nother SIGILL traps by having PSL_CM set in the psl).\n.I Scp\nis a pointer to the\n.I sigcontext\nstructure (defined in\n.RI < signal.h >),\nused to restore the context from before the signal.\n.PP\nThe following defines the mapping of hardware traps to signals\nand codes.  All of these symbols are defined in\n.RI < signal.h >:\n.LP\n.ta \\w'     Floating/decimal divide by zero   'u +\\w'15*  'u +8n\n.nf\n   Hardware condition\tSignal\tCode\n\nArithmetic traps:\n   Integer overflow\tSIGFPE\tFPE_INTOVF_TRAP\n   Integer division by zero\tSIGFPE\tFPE_INTDIV_TRAP\n   Floating overflow trap\tSIGFPE\tFPE_FLTOVF_TRAP\n   Floating/decimal division by zero\tSIGFPE\tFPE_FLTDIV_TRAP\n   Floating underflow trap\tSIGFPE\tFPE_FLTUND_TRAP\n   Decimal overflow trap\tSIGFPE\tFPE_DECOVF_TRAP\n   Subscript-range\tSIGFPE\tFPE_SUBRNG_TRAP\n   Floating overflow fault\tSIGFPE\tFPE_FLTOVF_FAULT\n   Floating divide by zero fault\tSIGFPE\tFPE_FLTDIV_FAULT\n   Floating underflow fault\tSIGFPE\tFPE_FLTUND_FAULT\nLength access control\tSIGSEGV\nProtection violation\tSIGBUS\nReserved instruction\tSIGILL\tILL_RESAD_FAULT\nCustomer-reserved instr.\tSIGEMT\nReserved operand\tSIGILL\tILL_PRIVIN_FAULT\nReserved addressing\tSIGILL\tILL_RESOP_FAULT\nTrace pending\tSIGTRAP\nBpt instruction\tSIGTRAP\nCompatibility-mode\tSIGILL\thardware supplied code\nChme\tSIGSEGV\nChms\tSIGSEGV\nChmu\tSIGSEGV\n.fi\n.SH \"NOTES  (PDP-11)\"\nThe handler routine can be declared:\n.PP\n    handler(sig, code, scp)\n    int sig, code;\n    struct sigcontext *scp;\n.PP\nHere \\fIsig\\fP is the signal number, into which the hardware faults and\ntraps are mapped as defined below.  \\fICode\\fP is a parameter that is a\nconstant as given below.  \\fIScp\\fP is a pointer to the \\fIsigcontext\\fP\nstructure (defined in <\\fIsignal.h\\fP>), used to restore the context from\nbefore the signal.\n.PP\nThe following defines the mapping of hardware traps to signals\nand codes.  All of these symbols are defined in <\\fIsignal.h\\fP>:\n.LP\n.ta \\w'     Floating/decimal divide by zero   'u +\\w'15*  'u +8n\n.nf\n   Hardware condition\tSignal\tCode\n\nArithmetic traps:\n   Floating overflow trap\tSIGFPE\tFPE_FLTOVF_TRAP\n   Floating/decimal division by zero\tSIGFPE\tFPE_FLTDIV_TRAP\n   Floating underflow trap\tSIGFPE\tFPE_FLTUND_TRAP\n   Decimal overflow trap\tSIGFPE\tFPE_DECOVF_TRAP\n   Illegal return code\tSIGFPE\tFPE_CRAZY\n   Bad op code\tSIGFPE\tFPE_OPCODE_TRAP\n   Bad operand\tSIGFPE\tFPE_OPERAND_TRAP\n   Maintenance trap\tSIGFPE\tFPE_MAINT_TRAP\nLength access control\tSIGSEGV\nProtection violation (odd address)\tSIGBUS\nReserved instruction\tSIGILL\tILL_RESAD_FAULT\nCustomer-reserved instr.\tSIGEMT\nTrace pending\tSIGTRAP\nBpt instruction\tSIGTRAP\n.fi\n.DT\n.PP\nThe handler routine must save any registers it uses and restore them before\nreturning.  On the PDP-11, the kernel saves \\fIr0\\fP and \\fIr1\\fP before\ncalling the handler routine, but expect the handler to save any other\nregisters it uses.  The standard entry code generated by the C compiler for\nhandler routines written in C automatically saves the remaining general\nregisters, but floating point registers are \\fInot\\fP saved.  As a result\nthere is currently no [standard] method for a handler routine written in C\nto perform floating point operations without blowing the interrupted program\nout of the water.\n.SH BUGS\nThis manual page is still confusing.\n"
  },
  {
    "path": "share/man/man2/sigwait.2",
    "content": ".\\\"\t@(#)sigwait.2 1.0 (2.11BSD) 1999/9/10\n.\\\"\n.TH SIGACTION 2 \"September 10, 1999\"\n.UC 7\n.SH NAME\n\\fBsigwait\\fP \\- wait for a signal\n.SH SYNOPSIS\n.B #include <signal.h>\n.sp\nint\n\\fBsigwait\\fP(set, sig)\n.br\n.I sigset_t *set;\n.br\n.I int *sig;\n.SH DESCRIPTION\n.B Sigwait\nchecks for a pending signal in \n.IR set ,\nclears it from the set of pending signals and returns the signal number\nin the location referenced by\n.IR sig .\nIf more than one of the signals contained in\n.I set\nis pending then\n.B sigwait\nselects only one and acts upon it.\nIf no signal contained in\n.I set\nis pending, then\n.B sigwait\nwaits for a signal to arrive.\nAll of the signals contained in\n.I set\nshould be blocked or unpredictable results may occur.\n.SH RETURN VALUES\nThe\n.B sigwait\nfunction returns 0 if successful and the signal number is stored in the\nlocation referenced by\n.IR sig .\n.SH ERRORS\nThe\n.B sigwait\nfunction may return one of the following errors:\n.TP 20\nEINVAL\nThe\n.I set\nargument contains an invalid or unsupported signal number.\n.TP 20\nEFAULT\n.I Sig\npoints to memory that is not a valid part of the process address space.\n.SH SEE ALSO\nsigprocmask(2)\n.SH STANDARDS\nThe\n.B sigwait\nfunction call\nconforms to\nIEEE Std1003.1-1998 (``POSIX'').\n"
  },
  {
    "path": "share/man/man2/socket.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)socket.2\t6.5 (Berkeley) 5/23/86\n.\\\"\n.TH SOCKET 2 \"May 23, 1986\"\n.UC 5\n.SH NAME\nsocket \\- create an endpoint for communication\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/types.h>\n#include <sys/socket.h>\n.PP\n.ft B\ns = socket(domain, type, protocol)\nint s, domain, type, protocol;\n.fi\n.SH DESCRIPTION\n.I Socket\ncreates an endpoint for communication and returns a descriptor.\n.PP\nThe\n.I domain\nparameter specifies a communications domain within which\ncommunication will take place; this selects the protocol family\nwhich should be used.\nThe protocol family generally is the same as the address family\nfor the addresses supplied in later operations on the socket.\nThese families are defined in the include file\n.IR <sys/socket.h> .\nThe currently understood formats are\n.PP\n.RS\n.nf\n.ta 1.25i 1.75i\nPF_UNIX\t(UNIX internal protocols),\nPF_INET\t(ARPA Internet protocols),\nPF_NS\t(Xerox Network Systems protocols), and\nPF_IMPLINK\t(IMP \\*(lqhost at IMP\\*(rq link layer).\n.fi\n.RE\n.PP\nThe socket has the indicated\n.I type,\nwhich specifies the semantics of communication.  Currently\ndefined types are:\n.PP\n.RS\n.nf\nSOCK_STREAM\nSOCK_DGRAM\nSOCK_RAW\nSOCK_SEQPACKET\nSOCK_RDM\n.fi\n.RE\n.PP\nA SOCK_STREAM type provides sequenced, reliable,\ntwo-way connection based byte streams.\nAn out-of-band data transmission mechanism may be supported.\nA SOCK_DGRAM socket supports\ndatagrams (connectionless, unreliable messages of\na fixed (typically small) maximum length).\nA SOCK_SEQPACKET socket may provide a sequenced, reliable,\ntwo-way connection-based data transmission path for datagrams\nof fixed maximum length; a consumer may be required to read\nan entire packet with each read system call.\nThis facility is protocol specific, and presently implemented\nonly for PF_NS.\nSOCK_RAW sockets provide access to internal network protocols and interfaces.\nThe types SOCK_RAW,\nwhich is available only to the super-user, and\nSOCK_RDM, which is planned,\nbut not yet implemented, are not described here.\n.PP\nThe\n.I protocol\nspecifies a particular protocol to be used with the socket.\nNormally only a single protocol exists to support a particular\nsocket type within a given protocol family.  However, it is possible\nthat many protocols may exist, in which case a particular protocol\nmust be specified in this manner.  The protocol number to use is\nparticular to the \\*(lqcommunication domain\\*(rq in which communication\nis to take place; see\n.IR protocols (3N).\n.PP\nSockets of type SOCK_STREAM\nare full-duplex byte streams, similar\nto pipes.  A stream socket must be in a\n.I connected\nstate before any data may be sent or received\non it.  A connection to another socket is created with a\n.IR connect (2)\ncall.  Once connected, data may be transferred using\n.IR read (2)\nand\n.IR write (2)\ncalls or some variant of the \n.IR send (2)\nand\n.IR recv (2)\ncalls.  When a session has been completed a\n.IR close (2)\nmay be performed.\nOut-of-band data may also be transmitted as described in\n.IR send (2)\nand received as described in\n.IR recv (2).\n.PP\nThe communications protocols used to implement a\nSOCK_STREAM insure that data\nis not lost or duplicated.  If a piece of data for which the\npeer protocol has buffer space cannot be successfully transmitted\nwithin a reasonable length of time, then\nthe connection is considered broken and calls\nwill indicate an error with\n\\-1 returns and with ETIMEDOUT as the specific code\nin the global variable errno.\nThe protocols optionally keep sockets \\*(lqwarm\\*(rq by\nforcing transmissions\nroughly every minute in the absence of other activity.\nAn error is then indicated if no response can be\nelicited on an otherwise\nidle connection for a extended period (e.g. 5 minutes).\nA SIGPIPE signal is raised if a process sends\non a broken stream; this causes naive processes,\nwhich do not handle the signal, to exit.\n.PP\nSOCK_SEQPACKET sockets employ the same system calls\nas SOCK_STREAM sockets.  The only difference\nis that \n.IR read (2)\ncalls will return only the amount of data requested,\nand any remaining in the arriving packet will be discarded.\n.PP\nSOCK_DGRAM and SOCK_RAW\nsockets allow sending of datagrams to correspondents\nnamed in\n.IR send (2)\ncalls.  Datagrams are generally received with\n.IR recvfrom (2),\nwhich returns the next datagram with its return address.\n.PP\nAn \n.IR fcntl (2)\ncall can be used to specify a process group to receive\na SIGURG signal when the out-of-band data arrives.\nIt may also enable non-blocking I/O\nand asynchronous notification of I/O events\nvia SIGIO.\n.PP\nThe operation of sockets is controlled by socket level\n.IR options .\nThese options are defined in the file\n.RI < sys/socket.h >.\n.IR Setsockopt (2)\nand\n.IR getsockopt (2)\nare used to set and get options, respectively.\n.SH \"RETURN VALUE\nA \\-1 is returned if an error occurs, otherwise the return\nvalue is a descriptor referencing the socket.\n.SH \"ERRORS\nThe \\fIsocket\\fP call fails if:\n.TP 20\n[EPROTONOSUPPORT]\nThe protocol type or the specified protocol is not supported\nwithin this domain.\n.TP 20\n[EMFILE]\nThe per-process descriptor table is full.\n.TP 20\n[ENFILE]\nThe system file table is full.\n.TP 20\n[EACCESS]\nPermission to create a socket of the specified type and/or protocol\nis denied.\n.TP 20\n[ENOBUFS]\nInsufficient buffer space is available.\nThe socket cannot be created until sufficient resources are freed.\n.SH SEE ALSO\naccept(2), bind(2), connect(2), getsockname(2), getsockopt(2),\nioctl(2), listen(2), read(2), recv(2),\nselect(2), send(2), shutdown(2), socketpair(2), write(2)\n.br\n``An Introductory 4.3BSD Interprocess Communication Tutorial.''\n(reprinted in UNIX Programmer's Supplementary Documents Volume 1, PS1:7)\n``An Advanced 4.3BSD Interprocess Communication Tutorial.''\n(reprinted in UNIX Programmer's Supplementary Documents Volume 1, PS1:8)\n"
  },
  {
    "path": "share/man/man2/socketpair.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)socketpair.2\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH SOCKETPAIR 2 \"May 15, 1985\"\n.UC 5\n.SH NAME\nsocketpair \\- create a pair of connected sockets\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/types.h>\n#include <sys/socket.h>\n.PP\n.ft B\nsocketpair(d, type, protocol, sv)\nint d, type, protocol;\nint sv[2];\n.fi\n.SH DESCRIPTION\nThe\n.I socketpair\ncall creates an unnamed pair of connected sockets in\nthe specified domain\n.IR d ,\nof the specified\n.IR type ,\nand using the optionally specified\n.IR protocol .\nThe descriptors used in referencing the new sockets\nare returned in\n.IR sv [0]\nand\n.IR sv [1].\nThe two sockets are indistinguishable.\n.SH DIAGNOSTICS\nA 0 is returned if the call succeeds, \\-1 if it fails.\n.SH ERRORS\nThe call succeeds unless:\n.TP 20\n[EMFILE]\nToo many descriptors are in use by this process.\n.TP 20\n[EAFNOSUPPORT]\nThe specified address family is not supported on this machine.\n.TP 20\n[EPROTONOSUPPORT]\nThe specified protocol is not supported on this machine.\n.TP 20\n[EOPNOSUPPORT]\nThe specified protocol does not support creation of socket pairs.\n.TP 20\n[EFAULT]\nThe address \\fIsv\\fP does not specify a valid part of the\nprocess address space.\n.SH \"SEE ALSO\"\nread(2), write(2), pipe(2)\n.SH BUGS\nThis call is currently implemented only for the UNIX domain.\n"
  },
  {
    "path": "share/man/man2/stat.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)stat.2\t6.5 (Berkeley) 5/12/86\n.\\\"\n.TH STAT 2 \"May 12, 1986\"\n.UC 4\n.SH NAME\nstat, lstat, fstat \\- get file status\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/types.h>\n#include <sys/stat.h>\n.PP\n.ft B\nstat(path, buf)\nchar *path;\nstruct stat *buf;\n.PP\n.ft B\nlstat(path, buf)\nchar *path;\nstruct stat *buf;\n.PP\n.ft B\nfstat(fd, buf)\nint fd;\nstruct stat *buf;\n.fi\n.ft R\n.SH DESCRIPTION\n.I Stat\nobtains information about the file\n.IR path .\nRead, write or execute\npermission of the named file is not required, but all directories\nlisted in the path name leading to the file must be reachable.\n.PP\n.I Lstat\nis like \\fIstat\\fP except in the case where the named file is a symbolic link,\nin which case\n.I lstat\nreturns information about the link,\nwhile\n.I stat\nreturns information about the file the link references.\n.PP\n.I Fstat\nobtains the same information about an open file\nreferenced by the argument descriptor, such as would\nbe obtained by an \\fIopen\\fP call.\n.PP\n.I Buf\nis a pointer to a\n.I stat\nstructure into which information is placed concerning the file.\nThe contents of the structure pointed to by\n.I buf\n.PP\n.nf\n.ta 1i 1.7i 2.5i\n     struct stat {\n\tdev_t\tst_dev;\t/* device inode resides on */\n\tino_t\tst_ino;\t/* this inode's number */\n\tu_short\tst_mode;\t/* protection */\n\tshort\tst_nlink;\t/* number or hard links to the file */\n\tshort\tst_uid;\t/* user-id of owner */\n\tshort\tst_gid;\t/* group-id of owner */\n\tdev_t\tst_rdev;\t/* the device type, for inode that is device */\n\toff_t\tst_size;\t/* total size of file */\n\ttime_t\tst_atime;\t/* file last access time */\n\tint\tst_spare1;\n\ttime_t\tst_mtime;\t/* file last modify time */\n\tint\tst_spare2;\n\ttime_t\tst_ctime;\t/* file last status change time */\n\tint\tst_spare3;\n\tlong\tst_blksize;\t/* optimal blocksize for file system i/o ops */\n\tlong\tst_blocks;\t/* actual number of blocks allocated */\n\tlong\tst_spare4[2];\n    };\n.fi\n.DT\n.PP\n.TP 12\nst_atime\nTime when file data was last read or modified.  Changed by the following system\ncalls:\n.IR mknod (2),\n.IR utimes (2),\n.IR read (2),\nand\n.IR write (2).\nFor reasons of efficiency, \nst_atime is not set when a directory\nis searched, although this would be more logical.\n.TP 12\nst_mtime\nTime when data was last modified.\nIt is not set by changes of owner, group, link count, or mode.\nChanged by the following system calls:\n.IR mknod (2),\n.IR utimes (2),\n.IR write (2).\n.TP 12\nst_ctime\nTime when file status was last changed.\nIt is set both both by writing and changing the i-node.\nChanged by the following system calls:\n.IR chmod (2)\n.IR chown (2),\n.IR link (2),\n.IR mknod (2),\n.IR rename (2),\n.IR unlink (2),\n.IR utimes (2),\n.IR write (2).\n.PP\nThe status information word \\fIst_mode\\fP has bits:\n.nf\n.in +5n\n.ta 1.6i 2.5i 3i\n#define S_IFMT\t0170000\t/* type of file */\n#define\\ \\ \\ \\ S_IFDIR\t0040000\t/* directory */\n#define\\ \\ \\ \\ S_IFCHR\t0020000\t/* character special */\n#define\\ \\ \\ \\ S_IFBLK\t0060000\t/* block special */\n#define\\ \\ \\ \\ S_IFREG\t0100000\t/* regular */\n#define\\ \\ \\ \\ S_IFLNK\t0120000\t/* symbolic link */\n#define\\ \\ \\ \\ S_IFSOCK\t0140000\t/* socket */\n#define S_ISUID\t0004000\t/* set user id on execution */\n#define S_ISGID\t0002000\t/* set group id on execution */\n#define S_ISVTX\t0001000\t/* save swapped text even after use */\n#define S_IREAD\t0000400\t/* read permission, owner */\n#define S_IWRITE\t0000200\t/* write permission, owner */\n#define S_IEXEC\t0000100\t/* execute/search permission, owner */\n.fi\n.in -5n\n.PP\nThe mode bits 0000070 and 0000007 encode group and\nothers permissions (see\n.IR chmod (2)).\n.SH \"RETURN VALUE\nUpon successful completion a value of 0 is returned.\nOtherwise, a value of \\-1 is returned and\n.I errno\nis set to indicate the error.\n.SH \"ERRORS\n.I Stat\nand\n.I lstat\nwill fail if one or more of the following are true:\n.TP 15\n[ENOTDIR]\nA component of the path prefix is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 255 characters,\nor an entire path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nThe named file does not exist.\n.TP 15\n[EACCES]\nSearch permission is denied for a component of the path prefix.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[EFAULT]\n.I Buf\nor\n.I name\npoints to an invalid address.\n.TP 15\n[EIO]\nAn I/O error occurred while reading from or writing to the file system.\n.PP\n.I Fstat\nwill fail if one or both of the following are true:\n.TP 15\n[EBADF]\n.I Fildes\nis not a valid open file descriptor.\n.TP 15\n[EFAULT]\n.I Buf\npoints to an invalid address.\n.TP 15\n[EIO]\nAn I/O error occurred while reading from or writing to the file system.\n.SH CAVEAT\nThe fields in the stat structure currently marked \n.IR st_spare1 ,\n.IR st_spare2 ,\nand\n.I st_spare3\nare present in preparation for inode time stamps expanding\nto 64 bits.  This, however, can break certain programs that\ndepend on the time stamps being contiguous (in calls to\n.IR utimes (2)).\n.SH \"SEE ALSO\"\nchmod(2), chown(2), utimes(2)\n.SH BUGS\nApplying\n.I fstat\nto a socket (and thus to a pipe)\nreturns a zero'd buffer,\nexcept for the blocksize field,\nand a unique device and inode number.\n"
  },
  {
    "path": "share/man/man2/statfs.2",
    "content": ".\\\" Copyright (c) 1989, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"\t@(#)statfs.2\t8.3.2 (2.11BSD) 1995/12/26\n.\\\"\n.TH STATFS 2 \"December 26, 1995\"\n.UC 7\n.SH NAME\n\\fBstatfs\\fP, \\fBfstatfs\\fP \\- get file system statistics\n.SH SYNOPSIS\n.B #include <sys/param.h>\n.br\n.B #include <sys/mount.h>\n.sp\n.I int\n.br\n\\fBstatfs\\fP(path,buf)\n.br\n.I char *path;\n.br\n.I struct statfs *buf;\n.sp\n.I int\n.br\n\\fBfstatfs\\fP(fd,buf)\n.br\n.I int fd;\n.br\n.I struct statfs *buf;\n.SH DESCRIPTION\n.BR Statfs ()\nreturns information about a mounted file system.\n.I Path\nis the path name of any file within the mounted filesystem.\n.I Buf\nis a pointer to a\n.I statfs\nstructure defined as follows:\n.sp\n.nf\n.cs R 20\n\n#define MNAMELEN 90       /* length of buffer for returned name */\n\nstruct statfs {\nshort   f_type;           /* type of filesystem (see below) */\nshort   f_flags;          /* copy of mount flags */\nshort   f_bsize;          /* fundamental file system block size */\nshort   f_iosize;         /* optimal transfer block size */\nlong    f_blocks;         /* total data blocks in file system */\nlong    f_bfree;          /* free blocks in fs */\nlong    f_bavail;         /* free blocks avail to non-superuser */\nino_t   f_files;          /* total file nodes in file system */\nino_t   f_ffree;          /* free file nodes in fs */\nu_long  f_fsid[2];        /* file system id */\nlong    f_spare[4];       /* spare for later */\nchar    f_mntonname[MNAMELEN];    /* mount point */\nchar    f_mntfromname[MNAMELEN];  /* mounted filesystem */\n};\n/*\n* File system types. - Only UFS is supported so the other types are not\n* given.\n*/\n#define\tMOUNT_UFS\t1\t/* Fast Filesystem */\n.br\n.fi\n.cs R\n.PP\nFields that are undefined for a particular file system are set to -1.\n.BR Fstatfs ()\nreturns the same information about an open file referenced by descriptor\n.IR fd .\n.SH RETURN VALUES\nUpon successful completion, a value of 0 is returned.\nOtherwise, -1 is returned and the global variable\n.I errno\nis set to indicate the error.\n.SH ERRORS\n.BR Statfs ()\nfails if one or more of the following are true:\n.sp\n.TP 20\n[ENOTDIR]\nA component of the path prefix of\n.I Path\nis not a directory.\n.TP 20\n[EINVAL]\n.I path\ncontains a character with the high-order bit set.\n.TP 20\n[ENAMETOOLONG]\nThe length of a component of\n.I path\nexceeds 63 characters,\nor the length of\n.I path\nexceeds 255 characters.\n.TP 20\n[ENOENT]\nThe file referred to by\n.I path\ndoes not exist.\n.TP 20\n[EACCES]\nSearch permission is denied for a component of the path prefix of\n.IR path .\n.TP 20\n[ELOOP]\nToo many symbolic links were encountered in translating\n.IR path .\n.TP 20\n[EFAULT]\n.I Buf\nor\n.I path\npoints to an invalid address.\n.TP 20\n[EIO]\nAn\nI/O\nerror occurred while reading from or writing to the file system.\n.PP\n.BR Fstatfs ()\nfails if one or more of the following are true:\n.sp\n.TP 20\n[EBADF]\n.I Fd\nis not a valid open file descriptor.\n.TP 20\n[EFAULT]\n.I Buf\npoints to an invalid address.\n.TP 20\n[EIO]\nAn\nI/O\nerror occurred while reading from or writing to the file system.\n.SH HISTORY\nThe\n.B statfs\nfunction first appeared in 4.4BSD.\n"
  },
  {
    "path": "share/man/man2/swapon.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)swapon.2\t6.4 (Berkeley) 3/9/86\n.\\\"\n.TH SWAPON 2 \"March 9, 1986\"\n.UC 4\n.SH NAME\nswapon \\- add a swap device for interleaved paging/swapping\n.SH SYNOPSIS\n.nf\n.B swapon(special)\n.B char *special;\n.fi\n.SH DESCRIPTION\n.I Swapon\nmakes the block device \n.I special \navailable to the system for\nallocation for paging and swapping.  The names of potentially\navailable devices are known to the system and defined at system\nconfiguration time.  The size of the swap area on \n.I special \nis calculated at the time the device is first made available\nfor swapping.\n.SH \"RETURN VALUE\nIf an error has occurred, a value of \\-1 is returned and\n.I errno\nis set to indicate the error.\n.SH ERRORS\n.I Swapon\nsucceeds unless:\n.TP 15\n[ENOTDIR]\nA component of the path prefix is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 255 characters,\nor an entire path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nThe named device does not exist.\n.TP 15\n[EACCES]\nSearch permission is denied for a component of the path prefix.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[EPERM]\nThe caller is not the super-user.\n.TP 15\n[ENOTBLK]\n.I Special\nis not a block device.\n.TP 15\n[EBUSY]\nThe device specified by \\fIspecial\\fP has already\nbeen made available for swapping\n.TP 15\n[EINVAL]\nThe device configured by \\fIspecial\\fP was not\nconfigured into the system as a swap device.\n.TP 15\n[ENXIO]\nThe major device number of \n.I special\nis out of range (this indicates no device driver exists\nfor the associated hardware).\n.TP 15\n[EIO]\nAn I/O error occurred while opening the swap device.\n.TP 15\n[EFAULT]\n.I Special\npoints outside the process's allocated address space.\n.SH \"SEE ALSO\"\nswapon(8), config(8)\n.SH BUGS\nThere is no way to stop swapping on a disk so that the pack may be\ndismounted.\n.PP\nThis call will be upgraded in future versions of the system.\n"
  },
  {
    "path": "share/man/man2/symlink.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)symlink.2\t6.3 (Berkeley) 8/26/85\n.\\\"\n.TH SYMLINK 2 \"August 26, 1985\"\n.UC 5\n.SH NAME\nsymlink \\- make symbolic link to a file\n.SH SYNOPSIS\n.nf\n.ft B\nsymlink(name1, name2)\nchar *name1, *name2;\n.fi\n.ft R\n.SH DESCRIPTION\nA symbolic link\n.I name2\nis created to\n.IR name1\n(\\fIname2\\fP is the name of the\nfile created, \\fIname1\\fP is the string\nused in creating the symbolic link).\nEither name may be an arbitrary path name; the files need not\nbe on the same file system.\n.SH \"RETURN VALUE\nUpon successful completion, a zero value is returned.\nIf an error occurs, the error code is stored in \\fIerrno\\fP\nand a \\-1 value is returned.\n.SH \"ERRORS\nThe symbolic link is made unless on or more of the\nfollowing are true:\n.TP 15\n[ENOTDIR]\nA component of the \\fIname2\\fP prefix is not a directory.\n.TP 15\n[EINVAL]\nEither \\fIname1\\fP or \\fIname2\\fP\ncontains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of either pathname exceeded 255 characters,\nor the entire length of either path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nThe named file does not exist.\n.TP 15\n[EACCES]\nA component of the \\fIname2\\fP path prefix denies search permission.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[EEXIST]\n\\fIName2\\fP already exists.\n.TP 15\n[EIO]\nAn I/O error occurred while making the directory entry for \\fIname2\\fP,\nor allocating the inode for \\fIname2\\fP,\nor writing out the link contents of \\fIname2\\fP.\n.TP 15\n[EROFS]\nThe file \\fIname2\\fP would reside on a read-only file system.\n.TP 15\n[ENOSPC]\nThe directory in which the entry for the new symbolic link is being placed\ncannot be extended because there is no space left on the file\nsystem containing the directory.\n.TP 15\n[ENOSPC]\nThe new symbolic link cannot be created because there\nthere is no space left on the file\nsystem that will contain the symbolic link.\n.TP 15\n[ENOSPC]\nThere are no free inodes on the file system on which the\nsymbolic link is being created.\n.TP 15\n[EDQUOT]\nThe directory in which the entry for the new symbolic link\nis being placed cannot be extended because the\nuser's quota of disk blocks on the file system\ncontaining the directory has been exhausted.\n.TP 15\n[EDQUOT]\nThe new symbolic link cannot be created because the user's\nquota of disk blocks on the file system that will\ncontain the symbolic link has been exhausted.\n.TP 15\n[EDQUOT]\nThe user's quota of inodes on the file system on\nwhich the symbolic link is being created has been exhausted.\n.TP 15\n[EIO]\nAn I/O error occurred while making the directory entry or allocating the inode.\n.TP 15\n[EFAULT]\n.I Name1\nor\n.I name2\npoints outside the process's allocated address space.\n.SH \"SEE ALSO\"\nlink(2), ln(1), unlink(2)\n"
  },
  {
    "path": "share/man/man2/sync.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)sync.2\t6.2 (Berkeley) 6/30/85\n.\\\"\n.TH SYNC 2 \"June 30, 1985\"\n.UC 4\n.SH NAME\nsync \\- update super-block\n.SH SYNOPSIS\n.B sync()\n.SH DESCRIPTION\n.I Sync\ncauses all information in core\nmemory that should be on disk to be written out.\nThis includes modified super blocks,\nmodified i-nodes, and delayed block I/O.\n.PP\n.I Sync\nshould be used by programs that examine a file system,\nfor example\n.I \"fsck, df,\"\netc.\n.I Sync\nis mandatory before a boot.\n.SH \"SEE ALSO\"\nfsync(2), sync(8), update(8)\n.SH BUGS\nThe writing, although scheduled, is not necessarily\ncomplete upon return from \n.IR sync .\n"
  },
  {
    "path": "share/man/man2/syscall.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)syscall.2\t6.2 (Berkeley) 4/16/86\n.\\\"\n.TH SYSCALL 2 \"April 16, 1986\"\n.UC 4\n.SH NAME\nsyscall \\- indirect system call\n.SH SYNOPSIS\n.nf\n.ft B\n#include <syscall.h>\n.PP\n.BR \"syscall(number, arg, ...)\" \\  \\  (VAX-11)\n.fi\n.SH DESCRIPTION\n.I Syscall\nperforms the system call whose assembly language\ninterface has the specified\n.I number,\nregister arguments\n.I r0\nand\n.I r1\nand further arguments\n.IR arg .\nSymbolic constants for system calls can be found in the header file\n.I <syscall.h>.\n.PP\nThe r0 value of the system call is returned.\n.SH DIAGNOSTICS\nWhen the C-bit is set,\n.I syscall\nreturns \\-1 and sets the\nexternal variable \n.I errno\n(see\n.IR intro (2)).\n.SH BUGS\nThere is no way to simulate system calls\nsuch as\n.IR pipe (2),\nwhich return values in register r1.\n"
  },
  {
    "path": "share/man/man2/truncate.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)truncate.2\t6.6 (Berkeley) 3/29/86\n.\\\"\n.TH TRUNCATE 2 \"March 29, 1986\"\n.UC 5\n.SH NAME\ntruncate \\- truncate a file to a specified length\n.SH SYNOPSIS\n.nf\n.ft B\ntruncate(path, length)\nchar *path;\noff_t length;\n.PP\n.ft B\nftruncate(fd, length)\nint fd;\noff_t length;\n.fi\n.SH DESCRIPTION\n.I Truncate\ncauses the file named by\n.I path\nor referenced by\n.I fd\nto be truncated to at most\n.I length\nbytes in size.  If the file previously\nwas larger than this size, the extra data\nis lost.\nWith\n.IR ftruncate ,\nthe file must be open for writing.\n.SH \"RETURN VALUES\nA value of 0 is returned if the call succeeds.  If the call\nfails a \\-1 is returned, and the global variable \\fIerrno\\fP\nspecifies the error.\n.SH \"ERRORS\n.I Truncate\nsucceeds unless:\n.TP 15\n[ENOTDIR]\nA component of the path prefix is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 255 characters,\nor an entire path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nThe named file does not exist.\n.TP 15\n[EACCES]\nSearch permission is denied for a component of the path prefix.\n.TP 15\n[EACCES]\nThe named file is not writable by the user.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[EISDIR]\nThe named file is a directory.\n.TP 15\n[EROFS]\nThe named file resides on a read-only file system.\n.TP 15\n[ETXTBSY]\nThe file is a pure procedure (shared text) file that is being executed.\n.TP 15\n[EIO]\nAn I/O error occurred updating the inode.\n.TP 15\n[EFAULT]\n.I Path\npoints outside the process's allocated address space.\n.PP\n.I Ftruncate\nsucceeds unless:\n.TP 15\n[EBADF]\nThe\n.I fd\nis not a valid descriptor.\n.TP 15\n[EINVAL]\nThe\n.I fd\nreferences a socket, not a file.\n.TP 15\n[EINVAL]\nThe\n.I fd\nis not open for writing.\n.SH \"SEE ALSO\"\nopen(2)\n.SH BUGS\nThese calls should be generalized to allow ranges\nof bytes in a file to be discarded.\n"
  },
  {
    "path": "share/man/man2/ucall.2",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ucall.2\t2.3 (Berkeley) 1/22/87\n.\\\"\n.TH UCALL 2 \"January 22, 1987\"\n.UC 2\n.SH NAME\nucall \\- call a kernel subroutine from user mode (2BSD)\n.SH SYNOPSIS\n.nf\n.ft B\n#include <pdp/psl.h>\n#include <sys/types.h>\n\nucall(priority, function, arg0, arg1)\nint priority, arg0, arg1;\ncaddr_t function;\n.fi\n.ft R\n.SH DESCRIPTION\n.I Ucall\ncauses the processor priority to be set to\n.I priority\nand the specified kernel\n.I function\nto be called with arguments\n.IR arg0 \" and \" arg1 .\n.I Priority\nis one of PSL_BR0, \\&..., PSL_BR7.\nProcessor priority is reset to PSL_BR0 when\n.I function\nreturns.\n.PP\n.I Ucall\nis allowed only if the user is the superuser.\nIt is obviously extremely dangerous if misused.\nIt's only current use is\nat system boot time to configure system devices by\ncalling device drivers \\&...\n.SH ERRORS\n.TP 15\n[EPERM]\nThe caller is not the super-user.\n.SH SEE ALSO\nautoconfig(8)\n.SH BUGS\nNo address validations are attempted.\n.PP\n.I Ucall\nis unique to the PDP-11 and 2BSD; its use is discouraged.\n"
  },
  {
    "path": "share/man/man2/umask.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)umask.2\t6.1 (Berkeley) 5/9/85\n.\\\"\n.TH UMASK 2 \"May 9, 1985\"\n.UC 4\n.SH NAME\numask \\- set file creation mode mask\n.SH SYNOPSIS\n.ft B\noumask = umask(numask)\n.br\nint oumask, numask;\n.ft R\n.SH DESCRIPTION\n.I Umask\nsets the process's file mode creation mask to \\fInumask\\fP\nand returns the previous value of the mask.  The low-order\n9 bits of \\fInumask\\fP are used whenever a file is created,\nclearing corresponding bits in the file mode\n(see\n.IR chmod (2)).\nThis clearing allows each user to restrict the default access\nto his files.\n.PP\nThe value is initially 022 (write access for owner only).\nThe mask is inherited by child processes.\n.SH \"RETURN VALUE\nThe previous value of the file mode mask is returned by the call.\n.SH SEE ALSO\nchmod(2), mknod(2), open(2)\n"
  },
  {
    "path": "share/man/man2/unlink.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)unlink.2\t6.2 (Berkeley) 5/22/85\n.\\\"\n.TH UNLINK 2 \"May 22, 1985\"\n.UC 4\n.SH NAME\nunlink \\- remove directory entry\n.SH SYNOPSIS\n.nf\n.ft B\nunlink(path)\nchar *path;\n.fi\n.ft R\n.SH DESCRIPTION\n.I Unlink\nremoves the entry for the file\n.I path\nfrom its directory.\nIf this entry was the last link to the file,\nand no process has the file open, then\nall resources associated with the file are reclaimed.\nIf, however, the file was open in any process, the actual\nresource reclamation is delayed until it is closed,\neven though the directory entry has disappeared.\n.SH \"RETURN VALUE\nUpon successful completion, a value of 0 is returned.\nOtherwise, a value of \\-1 is returned and\n.I errno\nis set to indicate the error.\n.SH \"ERRORS\nThe \\fIunlink\\fP succeeds unless:\n.TP 15\n[ENOTDIR]\nA component of the path prefix is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 255 characters,\nor an entire path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nThe named file does not exist.\n.TP 15\n[EACCES]\nSearch permission is denied for a component of the path prefix.\n.TP 15\n[EACCES]\nWrite permission is denied on the directory containing the link\nto be removed.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[EPERM]\nThe named file is a directory and the effective user ID\nof the process is not the super-user.\n.TP 15\n[EPERM]\nThe directory containing the file is marked sticky,\nand neither the containing directory nor the file to be removed\nare owned by the effective user ID.\n.TP 15\n[EBUSY]\nThe entry to be unlinked is the mount point for a\nmounted file system.\n.TP 15\n[EIO]\nAn I/O error occurred while deleting the directory entry\nor deallocating the inode.\n.TP 15\n[EROFS]\nThe named file resides on a read-only file system.\n.TP 15\n[EFAULT]\n.I Path\npoints outside the process's allocated address space.\n.SH \"SEE ALSO\"\nclose(2), link(2), rmdir(2)\n"
  },
  {
    "path": "share/man/man2/utimes.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)utimes.2\t6.4 (Berkeley) 8/26/85\n.\\\"\n.TH UTIMES 2 \"August 26, 1985\"\n.UC 4\n.SH NAME\nutimes \\- set file times\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/time.h>\n.PP\n.ft B\nutimes(file, tvp)\nchar *file;\nstruct timeval tvp[2];\n.fi\n.SH DESCRIPTION\nThe\n.I utimes\ncall\nuses the\n\\*(lqaccessed\\*(rq and \\*(lqupdated\\*(rq times in that order\nfrom the\n.I tvp\nvector\nto set the corresponding recorded times for\n.I file.\n.PP\nThe caller must be the owner of the file or the super-user.\nThe \\*(lqinode-changed\\*(rq time of the file is set to the current time.\n.SH \"RETURN VALUE\nUpon successful completion, a value of 0 is returned.\nOtherwise, a value of \\-1 is returned and\n.I errno\nis set to indicate the error.\n.SH \"ERRORS\n.I Utime\nwill fail if one or more of the following are true:\n.TP 15\n[ENOTDIR]\nA component of the path prefix is not a directory.\n.TP 15\n[EINVAL]\nThe pathname contains a character with the high-order bit set.\n.TP 15\n[ENAMETOOLONG]\nA component of a pathname exceeded 255 characters,\nor an entire path name exceeded 1023 characters.\n.TP 15\n[ENOENT]\nThe named file does not exist.\n.TP 15\n[ELOOP]\nToo many symbolic links were encountered in translating the pathname.\n.TP 15\n[EPERM]\nThe process is not super-user and not the owner of the file.\n.TP 15\n[EACCES]\nSearch permission is denied for a component of the path prefix.\n.TP 15\n[EROFS]\nThe file system containing the file is mounted read-only.\n.TP 15\n[EFAULT]\n.I File\nor \\fItvp\\fP points outside the process's allocated address space.\n.TP 15\n[EIO]\nAn I/O error occurred while reading or writing the affected inode.\n.SH SEE ALSO\nstat(2)\n"
  },
  {
    "path": "share/man/man2/vfork.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)vfork.2\t6.2 (Berkeley) 6/30/85\n.\\\"\n.TH VFORK 2 \"June 30, 1985\"\n.UC 4\n.SH NAME\nvfork \\- spawn new process in a virtual memory efficient way\n.SH SYNOPSIS\n.B pid = vfork()\n.br\n.B int pid;\n.SH DESCRIPTION\n.I Vfork\ncan be used to create new processes without fully copying the address\nspace of the old process, which is horrendously inefficient in a paged\nenvironment.  It is useful when the purpose of\n.IR fork (2)\nwould have been to create a new system context for an\n.IR execve .\n.I Vfork\ndiffers from\n.I fork\nin that the child borrows the parent's memory and thread of\ncontrol until a call to\n.IR execve (2)\nor an exit (either by a call to\n.IR exit (2)\nor abnormally.)\nThe parent process is suspended while the child is using its resources.\n.PP\n.I Vfork\nreturns 0 in the child's context and (later) the pid of the child in\nthe parent's context.\n.PP\n.I Vfork\ncan normally be used just like\n.I fork.\nIt does not work, however, to return while running in the childs context\nfrom the procedure that called\n.I vfork\nsince the eventual return from\n.I vfork\nwould then return to a no longer existent stack frame.\nBe careful, also, to call\n.I _exit\nrather than\n.I exit\nif you can't\n.IR execve ,\nsince\n.I exit\nwill flush and close standard I/O channels, and thereby mess up the\nparent processes standard I/O data structures.\n(Even with\n.I fork\nit is wrong to call\n.I exit\nsince buffered data would then be flushed twice.)\n.SH SEE ALSO\nfork(2), execve(2), sigvec(2), wait(2),\n.SH DIAGNOSTICS\nSame as for\n.IR fork .\n.SH BUGS\nThis system call will be eliminated when proper system sharing\nmechanisms are implemented. \nUsers should not depend on the memory\nsharing semantics of\n.I vfork\nas it will, in that case, be made synonymous to\n.IR fork .\n.PP\nTo avoid a possible deadlock situation,\nprocesses that are children in the middle\nof a\n.I vfork\nare never sent SIGTTOU or SIGTTIN signals; rather,\noutput or\n.IR ioctl s\nare allowed\nand input attempts result in an end-of-file indication.\n"
  },
  {
    "path": "share/man/man2/vhangup.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)vhangup.2\t6.2 (Berkeley) 6/30/85\n.\\\"\n.TH VHANGUP 2 \"June 30, 1985\"\n.UC 4\n.SH NAME\nvhangup \\- virtually ``hangup'' the current control terminal\n.SH SYNOPSIS\n.B vhangup()\n.SH DESCRIPTION\n.I Vhangup\nis used by the initialization process\n.IR init (8)\n(among others) to arrange that users are given\n\\*(lqclean\\*(rq' terminals at login,\nby revoking access of the previous users' processes to the terminal.\nTo effect this,\n.I vhangup\nsearches the system tables for references to the control terminal\nof the invoking process, revoking access permissions\non each instance of the terminal that it finds.\nFurther attempts to access the terminal by the affected processes\nwill yield i/o errors (EBADF).\nFinally,\na hangup signal (SIGHUP) is sent to the process group of the\ncontrol terminal.\n.SH SEE ALSO\ninit (8)\n.SH BUGS\nAccess to\nthe control terminal via\n.B /dev/tty\nis still possible.\n.PP\nThis call should be replaced by an automatic mechanism that\ntakes place on process exit.\n"
  },
  {
    "path": "share/man/man2/wait.2",
    "content": ".\\\" Copyright (c) 1980, 1991 Regents of the University of California.\n.\\\" All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)wait.2\t6.5 (Berkeley) 3/10/91\n.\\\"\n.TH WAIT 2 \"March 12, 1993\"\n.UC 4\n.SH NAME\nwait, waitpid, wait4, wait3 \\- wait for process terminatation\n.SH SYNOPSIS\n.ft B\n.nf\n#include <sys/types.h>\n#include <sys/wait.h>\n.PP\n.ft B\npid = wait(status)\nint pid;\nunion wait *status;\n.PP\n.ft B\n#include <sys/time.h>\n#include <sys/resource.h>\n.PP\n.ft B\npid = waitpid(wpid, status, options);\nint pid;\nint wpid;\nunion wait *status;\nint options;\n.PP\n.ft B\npid = wait3(status, options, rusage);\nint pid;\nunion wait *status;\nint options;\nstruct rusage *rusage;\n.PP\n.ft B\npid = wait4(wpid, status, options, rusage);\nint pid;\nint wpid;\nunion wait *status;\nint options;\nstruct rusage *rusage;\n.SH DESCRIPTION\nThe\n.I wait\nfunction suspends execution of its calling process until\n.B status\ninformation is available for a terminated child process,\nor a signal is received.\nOn return from a successful \n.I wait\ncall, \nthe\n.B status\narea contains termination information about the process that exited\nas defined below.\n.PP\nThe\n.I wait4\ncall provides a more general interface for programs\nthat need to wait for certain child processes,\nthat need resource utilization statistics accummulated by child processes,\nor that require options.\nThe other wait functions are implemented using\n.I wait4 .\n.PP\nThe\n.B wpid\nparameter specifies the set of child processes for which to wait.\nIf\n.B wpid\nis -1, the call waits for any child process.\nIf\n.B wpid\nis 0,\nthe call waits for any child process in the process group of the caller.\nIf\n.B wpid\nis greater than zero, the call waits for the process with process id\n.B wpid .\nIf\n.B wpid\nis less than -1, the call waits for any process whose process group id\nequals the absolute value of\n.B wpid .\n.PP\nThe\n.B status\nparameter is defined below.  The\n.B options\nparameter contains the bitwise OR of any of the following options.\nThe\n.B WNOHANG\noption\nis used to indicate that the call should not block if\nthere are no processes that wish to report status.\nIf the\n.B WUNTRACED\noption is set,\nchildren of the current process that are stopped\ndue to a\n.B SIGTTIN , SIGTTOU , SIGTSTP ,\nor\n.B SIGSTOP\nsignal also have\ntheir status reported.\n.PP\nIf\n.B rusage\nis non-zero, a summary of the resources used by the terminated\nprocess and all its\nchildren is returned (this information is currently not available\nfor stopped processes).\n.PP\nWhen the\n.B WNOHANG\noption is specified and no processes\nwish to report status, \n.I wait4\nreturns a \nprocess id\nof 0.\n.PP\nThe\n.I waitpid\ncall is identical to\n.I wait4\nwith an\n.B rusage\nvalue of zero.\nThe older\n.I wait3\ncall is the same as\n.I wait4\nwith a\n.B wpid\nvalue of -1.\n.PP\nThe following macros may be used to test the manner of exit of the process.\nOne of the first three macros will evaluate to a non-zero (true) value:\n.sp\n.I WIFEXITED(status)\n\\- True if the process terminated normally by a call to\n.I _exit(2)\nor\n.I exit(2) .\n.sp\n.I WIFSIGNALED(status)\n\\- True if the process terminated due to receipt of a signal.\n.sp\n.I WIFSTOPPED(status)\n\\- True if the process has not terminated, but has stopped and can be restarted.\nThis macro can be true only if the wait call specified the\n.B WUNTRACED\noption\nor if the child process is being traced (see\n\\fIptrace(2)\\fP).\n.PP\nDepending on the values of those macros, the following macros\nproduce the remaining status information about the child process:\n.sp\n.I WEXITSTATUS(status)\n\\- If \\fIWIFEXITED(status)\\fP\nis true, evaluates to the low-order 8 bits\nof the argument passed to \\fI_exit(2)\\fP\nor \\fIexit(2)\\fP\nby the child.\n.sp\n.I WTERMSIG(status)\n\\- If \\fIWIFSIGNALED(status)\\fP\nis true, evaluates to the number of the signal\nthat caused the termination of the process.\n.sp\n.I WCOREDUMP(status)\nIf \\fIWIFSIGNALED(status)\\fP\nis true, evaluates as true if the termination\nof the process was accompanied by the creation of a core file\ncontaining an image of the process when the signal was received.\n.sp\n.I WSTOPSIG(status)\\fP\nIf \\fIWIFSTOPPED(status)\\fP\nis true, evaluates to the number of the signal\nthat caused the process to stop.\n.SH NOTES\nSee\n.I sigvec(2)\nfor a list of termination signals.\nA status of 0 indicates normal termination.\n.PP\nIf a parent process terminates without\nwaiting for all of its child processes to terminate,\nthe remaining child processes are assigned the parent\nprocess 1 ID (the init process ID).\n.PP\nIf a signal is caught while any of the\n.I wait\ncalls is pending,\nthe call may be interrupted or restarted when the signal-catching routine\nreturns,\ndepending on the options in effect for the signal;\nsee \\fIintro(2)\\fP,\nSystem call restart.\n.SH RETURN VALUES\nIf\n.I wait()\nreturns due to a stopped\nor terminated child process, the process ID of the child\nis returned to the calling process.  Otherwise, a value of -1\nis returned and\n.I errno\nis set to indicate the error.\n.PP\nIf\n.I wait4(), wait3() or waitpid()\nreturns due to a stopped\nor terminated child process, the process ID of the child\nis returned to the calling process.\nIf there are no children not previously awaited,\n-1 is returned with\n.I errno\nset to\n.B [ECHILD].\nOtherwise, if\n.B WNOHANG\nis specified and there are\nno stopped or exited children,\n0 is returned.\nIf an error is detected or a caught signal aborts the call,\na value of -1\nis returned and\n.I errno\nis set to indicate the error.\n.SH ERRORS\n.I Wait()\nwill fail and return immediately if:\n.TP 15\n[ECHILD]\nThe calling process has no existing unwaited-for\nchild processes.\n.TP 15\n[EFAULT]\nThe \\fIstatus\\fP or \\fIrusage\\fP arguments point to an illegal address.\n(May not be detected before exit of a child process.)\n.TP 15\n[EINTR]\nThe call was interrupted by a caught signal,\nor the signal had the\n.I SV_INTERRUPT\nflag set.\n.SH STANDARDS\nThe\n.I wait\nand\n.I waitpid\nfunctions are defined by POSIX;\n.I wait4\nand\n.I wait3\nare not specified by POSIX.\nThe\n.I WCOREDUMP\nmacro\nand the ability to restart a pending\n.I wait\ncall are extensions to the POSIX interface.\n.SH SEE ALSO\n.I exit(2) ,\n.I sigvec(2)\n.Sh HISTORY\nA\n.I wait\nfunction call appeared in Version 6 AT&T UNIX.\n"
  },
  {
    "path": "share/man/man2/write.2",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)write.2\t6.5 (Berkeley) 8/1/87\n.\\\"\n.TH WRITE 2 \"August 1, 1987\"\n.UC 4\n.SH NAME\nwrite, writev \\- write output\n.SH SYNOPSIS\n.nf\n.ft B\ncc = write(d, buf, nbytes)\nint cc, d;\nchar *buf;\nunsigned short nbytes;\n.PP\n.ft B\n#include <sys/types.h>\n#include <sys/uio.h>\n.PP\n.ft B\ncc = writev(d, iov, iovcnt)\nint cc, d;\nstruct iovec *iov;\nint iovcnt;\n.fi\n.SH DESCRIPTION\n.I Write\nattempts to write\n.I nbytes\nof data to the object referenced by the descriptor\n.I d\nfrom the buffer pointed to by\n.IR buf .\n.I Writev\nperforms the same action, but gathers the output data\nfrom the \n.I iovcnt\nbuffers specified by the members of the\n.I iov\narray: iov[0], iov[1], ..., iov[iovcnt\\|\\-\\|1].\n.PP\nFor \n.IR writev ,\nthe \n.I iovec\nstructure is defined as\n.PP\n.nf\n.RS\n.DT\nstruct iovec {\n\tcaddr_t\tiov_base;\n\tu_short\tiov_len;\n};\n.RE\n.fi\n.PP\nEach \n.I iovec\nentry specifies the base address and length of an area\nin memory from which data should be written.\n.I Writev\nwill always write a complete area before proceeding\nto the next.\n.PP\nOn objects capable of seeking, the \\fIwrite\\fP starts at a position\ngiven by the pointer associated with\n.IR d ,\nsee\n.IR lseek (2).\nUpon return from\n.IR write ,\nthe pointer is incremented by the number of bytes actually written.\n.PP\nObjects that are not capable of seeking always write from the current\nposition.  The value of the pointer associated with such an object\nis undefined.\n.PP\nIf the real user is not the super-user, then\n.I write\nclears the set-user-id bit on a file.\nThis prevents penetration of system security\nby a user who\n\\*(lqcaptures\\*(rq a writable set-user-id file\nowned by the super-user.\n.PP\nWhen using non-blocking I/O on objects such as sockets that are subject\nto flow control,\n.I write\nand\n.I writev\nmay write fewer bytes than requested;\nthe return value must be noted,\nand the remainder of the operation should be retried when possible.\n.SH \"RETURN VALUE\nUpon successful completion the number of bytes actually written\nis returned.  Otherwise a \\-1 is returned and the global variable\n.I errno\nis set to indicate the error.\n.SH ERRORS\n.I Write\nand\n.I writev\nwill fail and the file pointer will remain unchanged if one or more\nof the following are true:\n.TP 15\n[EBADF]\n\\fID\\fP is not a valid descriptor open for writing.\n.TP 15\n[EPIPE]\nAn attempt is made to write to a pipe that is not open\nfor reading by any process.\n.TP 15\n[EPIPE]\nAn attempt is made to write to a socket of type SOCK_STREAM\nthat is not connected to a peer socket.\n.TP 15\n[EFBIG]\nAn attempt was made to write a file that exceeds the process's\nfile size limit or the maximum file size.\n.TP 15\n[EFAULT]\nPart of \\fIiov\\fP or data to be written to the file\npoints outside the process's allocated address space.\n.TP 15\n[EINVAL]\nThe pointer associated with\n.I d\nwas negative.\n.TP 15\n[ENOSPC]\nThere is no free space remaining on the file system\ncontaining the file.\n.TP 15\n[EDQUOT]\nThe user's quota of disk blocks on the file system\ncontaining the file has been exhausted.\n.TP 15\n[EIO]\nAn I/O error occurred while reading from or writing to the file system.\n.TP 15\n[EWOULDBLOCK]\nThe file was marked for non-blocking I/O,\nand no data could be written immediately.\n.PP\nIn addition, \n.I writev\nmay return one of the following errors:\n.TP 15\n[EINVAL]\n.I Iovcnt\nwas less than or equal to 0, or greater than 16.\n.TP 15\n[EINVAL]\nThe sum of the\n.I iov_len\nvalues in the\n.I iov\narray overflowed a short.\n.SH \"SEE ALSO\"\nfcntl(2), lseek(2), open(2), pipe(2), select(2)\n"
  },
  {
    "path": "share/man/man3/Makefile",
    "content": "#\n# Copyright (c) 1987 Regents of the University of California.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms are permitted\n# provided that the above copyright notice and this paragraph are\n# duplicated in all such forms and that any documentation,\n# advertising materials, and other materials related to such\n# distribution and use acknowledge that the software was developed\n# by the University of California, Berkeley.  The name of the\n# University may not be used to endorse or promote products derived\n# from this software without specific prior written permission.\n# THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n# IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n# WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n#\n#\t@(#)Makefile\t5.4.15 (2.11BSD) 1997/12/8\n#\nTOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nMDIR=\t/usr/share/man/cat3\nSRCS1=\tabort.3 abs.3 alarm.3 asinh.3 assert.3 atof.3 \\\n\tbasename.3 bstring.3 byteorder.3 \\\n\tcompat-sys5.3 crypt.3 ctime.3 ctype.3 curses.3 dbm.3 daemon.3 \\\n\tdevname.3 directory.3 dirname.3 \\\n\tecvt.3 end.3 erf.3 err.3 execl.3 exit.3 \\\n\texp.3 fclose.3 ferror.3 floor.3 \\\n\tfopen.3 fread.3 frexp.3 fseek.3 getc.3 getdisk.3 getenv.3 getfsent.3 \\\n\tgetgrent.3 gethostbyname.3 getnetent.3 getopt.3 getpass.3 \\\n\tgetgrouplist.3 getloadavg.3 getmntinfo.3 getsubopt.3 \\\n\tgetprotoent.3 getpwent.3 gets.3 getservent.3 getttyent.3 \\\n\tgetusershell.3 getwd.3 hypot.3 ieee.3 inet.3 infnan.3 initgroups.3\nSRCS2=\tinsque.3 intro.3 j0.3 l3tol.3 ldfps.3 lgamma.3 lib2648.3 \\\n\tmalloc.3 math.3 mktemp.3 monitor.3 mp.3 ndbm.3 nice.3 nlist.3 ns.3 \\\n\tpause.3 perror.3 plot.3 popen.3 printf.3 psignal.3 putc.3 puts.3 \\\n\tqsort.3 rand.3 random.3 rcmd.3 regex.3 resolver.3 rexec.3 scandir.3 \\\n\tscanf.3 setbuf.3 setjmp.3 siginterrupt.3 signal.3 sin.3 \\\n\tsinh.3 sleep.3 sqrt.3 stdio.3 strftime.3 string.3 strtok.3 stty.3 \\\n\tsetmode.3 setruid.3 sigsetops.3 \\\n\tstrcspn.3 strlcpy.3 strpbrk.3 \\\n\tstrsep.3 strspn.3 strtol.3 strtoul.3 strstr.3 \\\n\tswab.3 sysctl.3 syslog.3 \\\n\tsystem.3 termcap.3 time.3 times.3 ttyname.3 ualarm.3 uname.3 ungetc.3 \\\n\tsyserrlst.3 \\\n\tutime.3 valloc.3 varargs.3\nOBJS1=\tabort.0 abs.0 alarm.0 asinh.0 assert.0 atof.0 \\\n\tbasename.0 bstring.0 byteorder.0 \\\n\tcompat-sys5.0 crypt.0 ctime.0 ctype.0 curses.0 dbm.0 daemon.0 \\\n\tdevname.0 directory.0 dirname.0 \\\n\tecvt.0 end.0 erf.0 err.0 execl.0 exit.0 \\\n\texp.0 fclose.0 ferror.0 floor.0 \\\n\tfopen.0 fread.0 frexp.0 fseek.0 getc.0 getdisk.0 getenv.0 getfsent.0 \\\n\tgetgrent.0 gethostbyname.0 getnetent.0 getopt.0 getpass.0 \\\n\tgetprotoent.0 getpwent.0 gets.0 getservent.0 getttyent.0 \\\n\tgetgrouplist.0 getloadavg.0 getmntinfo.0 getsubopt.0 \\\n\tgetusershell.0 getwd.0 hypot.0 ieee.0 inet.0 infnan.0 initgroups.0\nOBJS2=\tinsque.0 intro.0 j0.0 l3tol.0 ldfps.0 lgamma.0 lib2648.0 \\\n\tmalloc.0 math.0 mktemp.0 monitor.0 mp.0 ndbm.0 nice.0 nlist.0 ns.0 \\\n\tpause.0 perror.0 plot.0 popen.0 printf.0 psignal.0 putc.0 puts.0 \\\n\tqsort.0 rand.0 random.0 rcmd.0 regex.0 resolver.0 rexec.0 scandir.0 \\\n\tscanf.0 setbuf.0 setjmp.0 siginterrupt.0 signal.0 sin.0 \\\n\tsinh.0 sleep.0 sqrt.0 stdio.0 strftime.0 string.0 strtok.0 stty.0 \\\n\tsetmode.0 setruid.0 sigsetops.0 \\\n\tstrcspn.0 strlcpy.0 strpbrk.0 \\\n\tstrsep.0 strspn.0 strtol.0 strtoul.0 strstr.0 \\\n\tswab.0 sysctl.0 syslog.0 \\\n\tsystem.0 termcap.0 time.0 times.0 ttyname.0 ualarm.0 uname.0 ungetc.0 \\\n\tsyserrlst.0 \\\n\tutime.0 valloc.0 varargs.0\nREMO1=\tedata.0 etext.0 j1.0 jn.0 ns_addr.0 ns_ntoa.0 y0.0 y1.0 yn.0 acos.0 \\\n\tasin.0 atan.0 atan2.0 atoi.0 atol.0 cos.0 dbm_clearerr.0 dbm_close.0 \\\n\tdbm_delete.0 dbm_error.0 dbm_fetch.0 dbm_firstkey.0 dbm_nextkey.0 \\\n\tdbm_open.0 dbm_store.0 dbminit.0 delete.0 erfc.0 expm1.0 fcvt.0 \\\n\tfetch.0 firstkey.0 gcvt.0 log.0 log10.0 log1p.0 nextkey.0 pow.0 \\\n\trresvport.0 ruserok.0 store.0 tan.0 addr.0 arc.0 asctime.0 cbrt.0 \\\n\tcircle.0 comp.0 cont.0 copysign.0 cosh.0 drem.0 encrypt.0 environ.0 \\\n\terase.0 execle.0 execlp.0 exect.0 execv.0 execve.0 execvp.0 fgetc.0 \\\n\tfgets.0 finite.0 fputc.0 fputs.0 ftime.0 getchar.0 getw.0 gmtime.0 \\\n\tgtty.0 inet_addr.0 inet_lnaof.0 inet_makeaddr.0 inet_netof.0 \\\n\tinet_network.0 inet_ntoa.0 isalnum.0 isalpha.0 isascii.0 iscntrl.0 \\\n\tisdigit.0 islower.0 isprint.0 ispunct.0 isspace.0 isupper.0 \\\n\tisxdigit.0 label.0 ldexp.0 line.0 linemod.0 localtime.0 logb.0 modf.0 \\\n\tmove.0 network.0 ntoa.0 openpl.0 pclose.0 point.0 putchar.0 putw.0\nREMO2=\tre_comp.0 re_exec.0 scalb.0 setkey.0 space.0 srand.0 tanh.0 \\\n\ttimezone.0 toascii.0 tolower.0 toupper.0 ltol3.0 _longjmp.0 \\\n\t_setjmp.0 acosh.0 alloca.0 atanh.0 cabs.0 calloc.0 ceil.0 \\\n\tcloselog.0 fabs.0 fdopen.0 free.0 freopen.0 fscanf.0 \\\n\tftell.0 fwrite.0 index.0 initstate.0 longjmp.0 mkstemp.0 openlog.0  \\\n\trealloc.0 remque.0 rewind.0 rindex.0 rint.0 \\\n\tsetlogmask.0 setstate.0 setrgid.0 srandom.0 \\\n\tsscanf.0 strcat.0 strcmp.0 strcpy.0 strlen.0 strncat.0 strncmp.0 \\\n\tstrncpy.0 strcasecmp.0 strncasecmp.0 \\\n\tstrerror.0 \\\n\tsprintf.0 vfprintf.0 vprintf.0 vsprintf.0 alphasort.0 bcmp.0 bcopy.0 \\\n\tbzero.0 clearerr.0 feof.0 fflush.0 ffs.0 fileno.0 fprintf.0 gamma.0  \\\n\tgetdiskbyname.0 isatty.0 moncontrol.0 monstartup.0 setbuffer.0 \\\n\tsetlinebuf.0 setvbuf.0 sys_siglist.0 ttyslot.0 endfsent.0 endgrent.0 \\\n\tendpwent.0 getfsfile.0 getfsspec.0 getfstype.0 getgrgid.0\n\nREMO3=\tgetgrnam.0 getpwnam.0 getpwuid.0 setfsent.0 setgrent.0 setpwent.0 \\\n\tsetpwfile.0 tgetent.0 tgetflag.0 tgetnum.0 tgetstr.0 tgoto.0 tputs.0 \\\n\tclosedir.0 endttyent.0 getttynam.0 opendir.0 readdir.0 rewinddir.0 \\\n\tseekdir.0 setttyent.0 telldir.0 endnetent.0 getnetbyaddr.0 \\\n\tgetnetbyname.0 htonl.0 htons.0 ntohl.0 ntohs.0 setnetent.0 \\\n\tendservent.0 getservbyname.0 getservbyport.0 setservent.0 \\\n\tendprotoent.0 endusershell.0 getprotobyname.0 getprotobynumber.0 \\\n\tsetprotoent.0 setusershell.0 endhostent.0 gethostbyaddr.0 gethostent.0 \\\n\tsethostent.0 sethostfile.0 memccpy.0 memchr.0 memcmp.0 memcpy.0 \\\n\tmemset.0 strchr.0 strrchr.0 tmpnam.0 tmpfile.0 \\\n\ttempnam.0 getmode.0 usleep.0 setenv.0 unsetenv.0\n\nREMO4=\tverr.0 errx.0 verrx.0 warn.0 warnx.0 vwarnx.0\n\nREMO5 = sigaddset.0 sigdelset.0 sigemptyset.0 sigfillset.0 sigismember.0\n\n.SUFFIXES: .3 .0\n\n.3.0:\n\t${MANROFF} $*.3 > $*.0\n\nall: _make_01 _make_02\n\n_make_01: ${OBJS1}\n\n_make_02: ${OBJS2}\n\nclean: FRC\n\trm -f ${OBJS1}\n\trm -f ${OBJS2}\n\ninstall: _make_01 _make_02\n\tcp ${OBJS1} ${DESTDIR}${MDIR}\n\tcp ${OBJS2} ${DESTDIR}${MDIR}\n\tfor i in ${REMO4}; do \\\n\t\tln -f ${DESTDIR}/${MDIR}/err.0 ${DESTDIR}${MDIR}/$$i; \\\n\tdone\n\tfor i in ${REMO5}; do \\\n\t\tln -f ${DESTDIR}/${MDIR}/sigsetops.0 ${DESTDIR}${MDIR}/$$i; \\\n\tdone\n\n\tln -f ${DESTDIR}${MDIR}/end.0 ${DESTDIR}${MDIR}/edata.0\n\tln -f ${DESTDIR}${MDIR}/end.0 ${DESTDIR}${MDIR}/etext.0\n\tln -f ${DESTDIR}${MDIR}/j0.0 ${DESTDIR}${MDIR}/j1.0\n\tln -f ${DESTDIR}${MDIR}/j0.0 ${DESTDIR}${MDIR}/jn.0\n\tln -f ${DESTDIR}${MDIR}/ns.0 ${DESTDIR}${MDIR}/ns_addr.0\n\tln -f ${DESTDIR}${MDIR}/ns.0 ${DESTDIR}${MDIR}/ns_ntoa.0\n\tln -f ${DESTDIR}${MDIR}/j0.0 ${DESTDIR}${MDIR}/y0.0\n\tln -f ${DESTDIR}${MDIR}/j0.0 ${DESTDIR}${MDIR}/y1.0\n\tln -f ${DESTDIR}${MDIR}/j0.0 ${DESTDIR}${MDIR}/yn.0\n\tln -f ${DESTDIR}${MDIR}/sin.0 ${DESTDIR}${MDIR}/acos.0\n\tln -f ${DESTDIR}${MDIR}/sin.0 ${DESTDIR}${MDIR}/asin.0\n\tln -f ${DESTDIR}${MDIR}/sin.0 ${DESTDIR}${MDIR}/atan.0\n\tln -f ${DESTDIR}${MDIR}/sin.0 ${DESTDIR}${MDIR}/atan2.0\n\tln -f ${DESTDIR}${MDIR}/atof.0 ${DESTDIR}${MDIR}/atoi.0\n\tln -f ${DESTDIR}${MDIR}/atof.0 ${DESTDIR}${MDIR}/atol.0\n\tln -f ${DESTDIR}${MDIR}/sin.0 ${DESTDIR}${MDIR}/cos.0\n\tln -f ${DESTDIR}${MDIR}/ndbm.0 ${DESTDIR}${MDIR}/dbm_clearerr.0\n\tln -f ${DESTDIR}${MDIR}/ndbm.0 ${DESTDIR}${MDIR}/dbm_close.0\n\tln -f ${DESTDIR}${MDIR}/ndbm.0 ${DESTDIR}${MDIR}/dbm_delete.0\n\tln -f ${DESTDIR}${MDIR}/ndbm.0 ${DESTDIR}${MDIR}/dbm_error.0\n\tln -f ${DESTDIR}${MDIR}/ndbm.0 ${DESTDIR}${MDIR}/dbm_fetch.0\n\tln -f ${DESTDIR}${MDIR}/ndbm.0 ${DESTDIR}${MDIR}/dbm_firstkey.0\n\tln -f ${DESTDIR}${MDIR}/ndbm.0 ${DESTDIR}${MDIR}/dbm_nextkey.0\n\tln -f ${DESTDIR}${MDIR}/ndbm.0 ${DESTDIR}${MDIR}/dbm_open.0\n\tln -f ${DESTDIR}${MDIR}/ndbm.0 ${DESTDIR}${MDIR}/dbm_store.0\n\tln -f ${DESTDIR}${MDIR}/dbm.0 ${DESTDIR}${MDIR}/dbminit.0\n\tln -f ${DESTDIR}${MDIR}/dbm.0 ${DESTDIR}${MDIR}/delete.0\n\tln -f ${DESTDIR}${MDIR}/erf.0 ${DESTDIR}${MDIR}/erfc.0\n\tln -f ${DESTDIR}${MDIR}/exp.0 ${DESTDIR}${MDIR}/expm1.0\n\tln -f ${DESTDIR}${MDIR}/ecvt.0 ${DESTDIR}${MDIR}/fcvt.0\n\tln -f ${DESTDIR}${MDIR}/dbm.0 ${DESTDIR}${MDIR}/fetch.0\n\tln -f ${DESTDIR}${MDIR}/dbm.0 ${DESTDIR}${MDIR}/firstkey.0\n\tln -f ${DESTDIR}${MDIR}/ecvt.0 ${DESTDIR}${MDIR}/gcvt.0\n\tln -f ${DESTDIR}${MDIR}/exp.0 ${DESTDIR}${MDIR}/log.0\n\tln -f ${DESTDIR}${MDIR}/exp.0 ${DESTDIR}${MDIR}/log10.0\n\tln -f ${DESTDIR}${MDIR}/exp.0 ${DESTDIR}${MDIR}/log1p.0\n\tln -f ${DESTDIR}${MDIR}/dbm.0 ${DESTDIR}${MDIR}/nextkey.0\n\tln -f ${DESTDIR}${MDIR}/exp.0 ${DESTDIR}${MDIR}/pow.0\n\tln -f ${DESTDIR}${MDIR}/rcmd.0 ${DESTDIR}${MDIR}/rresvport.0\n\tln -f ${DESTDIR}${MDIR}/rcmd.0 ${DESTDIR}${MDIR}/ruserok.0\n\tln -f ${DESTDIR}${MDIR}/dbm.0 ${DESTDIR}${MDIR}/store.0\n\tln -f ${DESTDIR}${MDIR}/sin.0 ${DESTDIR}${MDIR}/tan.0\n\tln -f ${DESTDIR}${MDIR}/inet.0 ${DESTDIR}${MDIR}/addr.0\n\tln -f ${DESTDIR}${MDIR}/plot.0 ${DESTDIR}${MDIR}/arc.0\n\tln -f ${DESTDIR}${MDIR}/ctime.0 ${DESTDIR}${MDIR}/asctime.0\n\tln -f ${DESTDIR}${MDIR}/sqrt.0 ${DESTDIR}${MDIR}/cbrt.0\n\tln -f ${DESTDIR}${MDIR}/plot.0 ${DESTDIR}${MDIR}/circle.0\n\tln -f ${DESTDIR}${MDIR}/regex.0 ${DESTDIR}${MDIR}/comp.0\n\tln -f ${DESTDIR}${MDIR}/plot.0 ${DESTDIR}${MDIR}/cont.0\n\tln -f ${DESTDIR}${MDIR}/ieee.0 ${DESTDIR}${MDIR}/copysign.0\n\tln -f ${DESTDIR}${MDIR}/sinh.0 ${DESTDIR}${MDIR}/cosh.0\n\tln -f ${DESTDIR}${MDIR}/ieee.0 ${DESTDIR}${MDIR}/drem.0\n\tln -f ${DESTDIR}${MDIR}/crypt.0 ${DESTDIR}${MDIR}/encrypt.0\n\tln -f ${DESTDIR}${MDIR}/execl.0 ${DESTDIR}${MDIR}/environ.0\n\tln -f ${DESTDIR}${MDIR}/plot.0 ${DESTDIR}${MDIR}/erase.0\n\tln -f ${DESTDIR}${MDIR}/execl.0 ${DESTDIR}${MDIR}/execle.0\n\tln -f ${DESTDIR}${MDIR}/execl.0 ${DESTDIR}${MDIR}/execlp.0\n\tln -f ${DESTDIR}${MDIR}/execl.0 ${DESTDIR}${MDIR}/exect.0\n\tln -f ${DESTDIR}${MDIR}/execl.0 ${DESTDIR}${MDIR}/execv.0\n\tln -f ${DESTDIR}${MDIR}/execl.0 ${DESTDIR}${MDIR}/execve.0\n\tln -f ${DESTDIR}${MDIR}/execl.0 ${DESTDIR}${MDIR}/execvp.0\n\tln -f ${DESTDIR}${MDIR}/getc.0 ${DESTDIR}${MDIR}/fgetc.0\n\tln -f ${DESTDIR}${MDIR}/gets.0 ${DESTDIR}${MDIR}/fgets.0\n\tln -f ${DESTDIR}${MDIR}/ieee.0 ${DESTDIR}${MDIR}/finite.0\n\tln -f ${DESTDIR}${MDIR}/putc.0 ${DESTDIR}${MDIR}/fputc.0\n\tln -f ${DESTDIR}${MDIR}/puts.0 ${DESTDIR}${MDIR}/fputs.0\n\tln -f ${DESTDIR}${MDIR}/time.0 ${DESTDIR}${MDIR}/ftime.0\n\tln -f ${DESTDIR}${MDIR}/getc.0 ${DESTDIR}${MDIR}/getchar.0\n\tln -f ${DESTDIR}${MDIR}/getc.0 ${DESTDIR}${MDIR}/getw.0\n\tln -f ${DESTDIR}${MDIR}/ctime.0 ${DESTDIR}${MDIR}/gmtime.0\n\tln -f ${DESTDIR}${MDIR}/stty.0 ${DESTDIR}${MDIR}/gtty.0\n\tln -f ${DESTDIR}${MDIR}/inet.0 ${DESTDIR}${MDIR}/inet_addr.0\n\tln -f ${DESTDIR}${MDIR}/inet.0 ${DESTDIR}${MDIR}/inet_lnaof.0\n\tln -f ${DESTDIR}${MDIR}/inet.0 ${DESTDIR}${MDIR}/inet_makeaddr.0\n\tln -f ${DESTDIR}${MDIR}/inet.0 ${DESTDIR}${MDIR}/inet_netof.0\n\tln -f ${DESTDIR}${MDIR}/inet.0 ${DESTDIR}${MDIR}/inet_network.0\n\tln -f ${DESTDIR}${MDIR}/inet.0 ${DESTDIR}${MDIR}/inet_ntoa.0\n\tln -f ${DESTDIR}${MDIR}/ctype.0 ${DESTDIR}${MDIR}/isalnum.0\n\tln -f ${DESTDIR}${MDIR}/ctype.0 ${DESTDIR}${MDIR}/isalpha.0\n\tln -f ${DESTDIR}${MDIR}/ctype.0 ${DESTDIR}${MDIR}/isascii.0\n\tln -f ${DESTDIR}${MDIR}/ctype.0 ${DESTDIR}${MDIR}/iscntrl.0\n\tln -f ${DESTDIR}${MDIR}/ctype.0 ${DESTDIR}${MDIR}/isdigit.0\n\tln -f ${DESTDIR}${MDIR}/ctype.0 ${DESTDIR}${MDIR}/islower.0\n\tln -f ${DESTDIR}${MDIR}/ctype.0 ${DESTDIR}${MDIR}/isprint.0\n\tln -f ${DESTDIR}${MDIR}/ctype.0 ${DESTDIR}${MDIR}/ispunct.0\n\tln -f ${DESTDIR}${MDIR}/ctype.0 ${DESTDIR}${MDIR}/isspace.0\n\tln -f ${DESTDIR}${MDIR}/ctype.0 ${DESTDIR}${MDIR}/isupper.0\n\tln -f ${DESTDIR}${MDIR}/ctype.0 ${DESTDIR}${MDIR}/isxdigit.0\n\tln -f ${DESTDIR}${MDIR}/plot.0 ${DESTDIR}${MDIR}/label.0\n\tln -f ${DESTDIR}${MDIR}/frexp.0 ${DESTDIR}${MDIR}/ldexp.0\n\tln -f ${DESTDIR}${MDIR}/plot.0 ${DESTDIR}${MDIR}/line.0\n\tln -f ${DESTDIR}${MDIR}/plot.0 ${DESTDIR}${MDIR}/linemod.0\n\tln -f ${DESTDIR}${MDIR}/ctime.0 ${DESTDIR}${MDIR}/localtime.0\n\tln -f ${DESTDIR}${MDIR}/ieee.0 ${DESTDIR}${MDIR}/logb.0\n\tln -f ${DESTDIR}${MDIR}/frexp.0 ${DESTDIR}${MDIR}/modf.0\n\tln -f ${DESTDIR}${MDIR}/plot.0 ${DESTDIR}${MDIR}/move.0\n\tln -f ${DESTDIR}${MDIR}/inet.0 ${DESTDIR}${MDIR}/network.0\n\tln -f ${DESTDIR}${MDIR}/inet.0 ${DESTDIR}${MDIR}/ntoa.0\n\tln -f ${DESTDIR}${MDIR}/plot.0 ${DESTDIR}${MDIR}/openpl.0\n\tln -f ${DESTDIR}${MDIR}/popen.0 ${DESTDIR}${MDIR}/pclose.0\n\tln -f ${DESTDIR}${MDIR}/plot.0 ${DESTDIR}${MDIR}/point.0\n\tln -f ${DESTDIR}${MDIR}/putc.0 ${DESTDIR}${MDIR}/putchar.0\n\tln -f ${DESTDIR}${MDIR}/putc.0 ${DESTDIR}${MDIR}/putw.0\n\tln -f ${DESTDIR}${MDIR}/regex.0 ${DESTDIR}${MDIR}/re_comp.0\n\tln -f ${DESTDIR}${MDIR}/regex.0 ${DESTDIR}${MDIR}/re_exec.0\n\tln -f ${DESTDIR}${MDIR}/ieee.0 ${DESTDIR}${MDIR}/scalb.0\n\tln -f ${DESTDIR}${MDIR}/crypt.0 ${DESTDIR}${MDIR}/setkey.0\n\tln -f ${DESTDIR}${MDIR}/plot.0 ${DESTDIR}${MDIR}/space.0\n\tln -f ${DESTDIR}${MDIR}/rand.0 ${DESTDIR}${MDIR}/srand.0\n\tln -f ${DESTDIR}${MDIR}/sinh.0 ${DESTDIR}${MDIR}/tanh.0\n\tln -f ${DESTDIR}${MDIR}/ctime.0 ${DESTDIR}${MDIR}/timezone.0\n\tln -f ${DESTDIR}${MDIR}/ctype.0 ${DESTDIR}${MDIR}/toascii.0\n\tln -f ${DESTDIR}${MDIR}/ctype.0 ${DESTDIR}${MDIR}/tolower.0\n\tln -f ${DESTDIR}${MDIR}/ctype.0 ${DESTDIR}${MDIR}/toupper.0\n\tln -f ${DESTDIR}${MDIR}/l3tol.0 ${DESTDIR}${MDIR}/ltol3.0\n\tln -f ${DESTDIR}${MDIR}/setjmp.0 ${DESTDIR}${MDIR}/_longjmp.0\n\tln -f ${DESTDIR}${MDIR}/setjmp.0 ${DESTDIR}${MDIR}/_setjmp.0\n\tln -f ${DESTDIR}${MDIR}/asinh.0 ${DESTDIR}${MDIR}/acosh.0\n\tln -f ${DESTDIR}${MDIR}/malloc.0 ${DESTDIR}${MDIR}/alloca.0\n\tln -f ${DESTDIR}${MDIR}/asinh.0 ${DESTDIR}${MDIR}/atanh.0\n\tln -f ${DESTDIR}${MDIR}/hypot.0 ${DESTDIR}${MDIR}/cabs.0\n\tln -f ${DESTDIR}${MDIR}/malloc.0 ${DESTDIR}${MDIR}/calloc.0\n\tln -f ${DESTDIR}${MDIR}/floor.0 ${DESTDIR}${MDIR}/ceil.0\n\tln -f ${DESTDIR}${MDIR}/syslog.0 ${DESTDIR}${MDIR}/closelog.0\n\tln -f ${DESTDIR}${MDIR}/perror.0 ${DESTDIR}${MDIR}/strerror.0\n\tln -f ${DESTDIR}${MDIR}/floor.0 ${DESTDIR}${MDIR}/fabs.0\n\tln -f ${DESTDIR}${MDIR}/fopen.0 ${DESTDIR}${MDIR}/fdopen.0\n\tln -f ${DESTDIR}${MDIR}/malloc.0 ${DESTDIR}${MDIR}/free.0\n\tln -f ${DESTDIR}${MDIR}/fopen.0 ${DESTDIR}${MDIR}/freopen.0\n\tln -f ${DESTDIR}${MDIR}/scanf.0 ${DESTDIR}${MDIR}/fscanf.0\n\tln -f ${DESTDIR}${MDIR}/fseek.0 ${DESTDIR}${MDIR}/ftell.0\n\tln -f ${DESTDIR}${MDIR}/fread.0 ${DESTDIR}${MDIR}/fwrite.0\n\tln -f ${DESTDIR}${MDIR}/string.0 ${DESTDIR}${MDIR}/index.0\n\tln -f ${DESTDIR}${MDIR}/random.0 ${DESTDIR}${MDIR}/initstate.0\n\tln -f ${DESTDIR}${MDIR}/setjmp.0 ${DESTDIR}${MDIR}/longjmp.0\n\tln -f ${DESTDIR}${MDIR}/mktemp.0 ${DESTDIR}${MDIR}/mkstemp.0\n\tln -f ${DESTDIR}${MDIR}/syslog.0 ${DESTDIR}${MDIR}/openlog.0\n\tln -f ${DESTDIR}${MDIR}/malloc.0 ${DESTDIR}${MDIR}/realloc.0\n\tln -f ${DESTDIR}${MDIR}/insque.0 ${DESTDIR}${MDIR}/remque.0\n\tln -f ${DESTDIR}${MDIR}/fseek.0 ${DESTDIR}${MDIR}/rewind.0\n\tln -f ${DESTDIR}${MDIR}/string.0 ${DESTDIR}${MDIR}/rindex.0\n\tln -f ${DESTDIR}${MDIR}/floor.0 ${DESTDIR}${MDIR}/rint.0\n\tln -f ${DESTDIR}${MDIR}/syslog.0 ${DESTDIR}${MDIR}/setlogmask.0\n\tln -f ${DESTDIR}${MDIR}/random.0 ${DESTDIR}${MDIR}/setstate.0\n\tln -f ${DESTDIR}${MDIR}/random.0 ${DESTDIR}${MDIR}/srandom.0\n\tln -f ${DESTDIR}${MDIR}/scanf.0 ${DESTDIR}${MDIR}/sscanf.0\n\tln -f ${DESTDIR}${MDIR}/string.0 ${DESTDIR}${MDIR}/strcat.0\n\tln -f ${DESTDIR}${MDIR}/string.0 ${DESTDIR}${MDIR}/strcmp.0\n\tln -f ${DESTDIR}${MDIR}/string.0 ${DESTDIR}${MDIR}/strcpy.0\n\tln -f ${DESTDIR}${MDIR}/string.0 ${DESTDIR}${MDIR}/strlen.0\n\tln -f ${DESTDIR}${MDIR}/string.0 ${DESTDIR}${MDIR}/strncat.0\n\tln -f ${DESTDIR}${MDIR}/string.0 ${DESTDIR}${MDIR}/strncmp.0\n\tln -f ${DESTDIR}${MDIR}/string.0 ${DESTDIR}${MDIR}/strncpy.0\n\tln -f ${DESTDIR}${MDIR}/string.0 ${DESTDIR}${MDIR}/strcasecmp.0\n\tln -f ${DESTDIR}${MDIR}/string.0 ${DESTDIR}${MDIR}/strncasecmp.0\n\tln -f ${DESTDIR}${MDIR}/strlcpy.0 ${DESTDIR}${MDIR}/strlcat.0\n\tln -f ${DESTDIR}${MDIR}/printf.0 ${DESTDIR}${MDIR}/sprintf.0\n\tln -f ${DESTDIR}${MDIR}/printf.0 ${DESTDIR}${MDIR}/vfprintf.0\n\tln -f ${DESTDIR}${MDIR}/printf.0 ${DESTDIR}${MDIR}/vprintf.0\n\tln -f ${DESTDIR}${MDIR}/printf.0 ${DESTDIR}${MDIR}/vsprintf.0\n\tln -f ${DESTDIR}${MDIR}/scandir.0 ${DESTDIR}${MDIR}/alphasort.0\n\tln -f ${DESTDIR}${MDIR}/bstring.0 ${DESTDIR}${MDIR}/bcmp.0\n\tln -f ${DESTDIR}${MDIR}/bstring.0 ${DESTDIR}${MDIR}/bcopy.0\n\tln -f ${DESTDIR}${MDIR}/bstring.0 ${DESTDIR}${MDIR}/bzero.0\n\tln -f ${DESTDIR}${MDIR}/ferror.0 ${DESTDIR}${MDIR}/clearerr.0\n\tln -f ${DESTDIR}${MDIR}/ferror.0 ${DESTDIR}${MDIR}/feof.0\n\tln -f ${DESTDIR}${MDIR}/fclose.0 ${DESTDIR}${MDIR}/fflush.0\n\tln -f ${DESTDIR}${MDIR}/bstring.0 ${DESTDIR}${MDIR}/ffs.0\n\tln -f ${DESTDIR}${MDIR}/ferror.0 ${DESTDIR}${MDIR}/fileno.0\n\tln -f ${DESTDIR}${MDIR}/printf.0 ${DESTDIR}${MDIR}/fprintf.0\n\tln -f ${DESTDIR}${MDIR}/lgamma.0 ${DESTDIR}${MDIR}/gamma.0\n\tln -f ${DESTDIR}${MDIR}/getdisk.0 ${DESTDIR}${MDIR}/getdiskbyname.0\n\tln -f ${DESTDIR}${MDIR}/ttyname.0 ${DESTDIR}${MDIR}/isatty.0\n\tln -f ${DESTDIR}${MDIR}/monitor.0 ${DESTDIR}${MDIR}/moncontrol.0\n\tln -f ${DESTDIR}${MDIR}/monitor.0 ${DESTDIR}${MDIR}/monstartup.0\n\tln -f ${DESTDIR}${MDIR}/setbuf.0 ${DESTDIR}${MDIR}/setbuffer.0\n\tln -f ${DESTDIR}${MDIR}/setbuf.0 ${DESTDIR}${MDIR}/setlinebuf.0\n\tln -f ${DESTDIR}${MDIR}/setbuf.0 ${DESTDIR}${MDIR}/setvbuf.0\n\tln -f ${DESTDIR}${MDIR}/psignal.0 ${DESTDIR}${MDIR}/sys_siglist.0\n\tln -f ${DESTDIR}${MDIR}/ttyname.0 ${DESTDIR}${MDIR}/ttyslot.0\n\tln -f ${DESTDIR}${MDIR}/getfsent.0 ${DESTDIR}${MDIR}/endfsent.0\n\tln -f ${DESTDIR}${MDIR}/getgrent.0 ${DESTDIR}${MDIR}/endgrent.0\n\tln -f ${DESTDIR}${MDIR}/getpwent.0 ${DESTDIR}${MDIR}/endpwent.0\n\tln -f ${DESTDIR}${MDIR}/getfsent.0 ${DESTDIR}${MDIR}/getfsfile.0\n\tln -f ${DESTDIR}${MDIR}/getfsent.0 ${DESTDIR}${MDIR}/getfsspec.0\n\tln -f ${DESTDIR}${MDIR}/getfsent.0 ${DESTDIR}${MDIR}/getfstype.0\n\tln -f ${DESTDIR}${MDIR}/getgrent.0 ${DESTDIR}${MDIR}/getgrgid.0\n\tln -f ${DESTDIR}${MDIR}/getgrent.0 ${DESTDIR}${MDIR}/getgrnam.0\n\tln -f ${DESTDIR}${MDIR}/getpwent.0 ${DESTDIR}${MDIR}/getpwnam.0\n\tln -f ${DESTDIR}${MDIR}/getpwent.0 ${DESTDIR}${MDIR}/getpwuid.0\n\tln -f ${DESTDIR}${MDIR}/getfsent.0 ${DESTDIR}${MDIR}/setfsent.0\n\tln -f ${DESTDIR}${MDIR}/getgrent.0 ${DESTDIR}${MDIR}/setgrent.0\n\tln -f ${DESTDIR}${MDIR}/getpwent.0 ${DESTDIR}${MDIR}/setpwent.0\n\tln -f ${DESTDIR}${MDIR}/getpwent.0 ${DESTDIR}${MDIR}/setpwfile.0\n\tln -f ${DESTDIR}${MDIR}/termcap.0 ${DESTDIR}${MDIR}/tgetent.0\n\tln -f ${DESTDIR}${MDIR}/termcap.0 ${DESTDIR}${MDIR}/tgetflag.0\n\tln -f ${DESTDIR}${MDIR}/termcap.0 ${DESTDIR}${MDIR}/tgetnum.0\n\tln -f ${DESTDIR}${MDIR}/termcap.0 ${DESTDIR}${MDIR}/tgetstr.0\n\tln -f ${DESTDIR}${MDIR}/termcap.0 ${DESTDIR}${MDIR}/tgoto.0\n\tln -f ${DESTDIR}${MDIR}/termcap.0 ${DESTDIR}${MDIR}/tputs.0\n\tln -f ${DESTDIR}${MDIR}/directory.0 ${DESTDIR}${MDIR}/closedir.0\n\tln -f ${DESTDIR}${MDIR}/getttyent.0 ${DESTDIR}${MDIR}/endttyent.0\n\tln -f ${DESTDIR}${MDIR}/getttyent.0 ${DESTDIR}${MDIR}/getttynam.0\n\tln -f ${DESTDIR}${MDIR}/directory.0 ${DESTDIR}${MDIR}/opendir.0\n\tln -f ${DESTDIR}${MDIR}/directory.0 ${DESTDIR}${MDIR}/readdir.0\n\tln -f ${DESTDIR}${MDIR}/directory.0 ${DESTDIR}${MDIR}/rewinddir.0\n\tln -f ${DESTDIR}${MDIR}/directory.0 ${DESTDIR}${MDIR}/seekdir.0\n\tln -f ${DESTDIR}${MDIR}/getttyent.0 ${DESTDIR}${MDIR}/setttyent.0\n\tln -f ${DESTDIR}${MDIR}/directory.0 ${DESTDIR}${MDIR}/telldir.0\n\tln -f ${DESTDIR}${MDIR}/getnetent.0 ${DESTDIR}${MDIR}/endnetent.0\n\tln -f ${DESTDIR}${MDIR}/getnetent.0 ${DESTDIR}${MDIR}/getnetbyaddr.0\n\tln -f ${DESTDIR}${MDIR}/getnetent.0 ${DESTDIR}${MDIR}/getnetbyname.0\n\tln -f ${DESTDIR}${MDIR}/byteorder.0 ${DESTDIR}${MDIR}/htonl.0\n\tln -f ${DESTDIR}${MDIR}/byteorder.0 ${DESTDIR}${MDIR}/htons.0\n\tln -f ${DESTDIR}${MDIR}/byteorder.0 ${DESTDIR}${MDIR}/ntohl.0\n\tln -f ${DESTDIR}${MDIR}/byteorder.0 ${DESTDIR}${MDIR}/ntohs.0\n\tln -f ${DESTDIR}${MDIR}/getnetent.0 ${DESTDIR}${MDIR}/setnetent.0\n\tln -f ${DESTDIR}${MDIR}/getservent.0 ${DESTDIR}${MDIR}/endservent.0\n\tln -f ${DESTDIR}${MDIR}/getservent.0 ${DESTDIR}${MDIR}/getservbyname.0\n\tln -f ${DESTDIR}${MDIR}/getservent.0 ${DESTDIR}${MDIR}/getservbyport.0\n\tln -f ${DESTDIR}${MDIR}/getservent.0 ${DESTDIR}${MDIR}/setservent.0\n\tln -f ${DESTDIR}${MDIR}/getprotoent.0 ${DESTDIR}${MDIR}/endprotoent.0\n\tln -f ${DESTDIR}${MDIR}/getusershell.0 ${DESTDIR}${MDIR}/endusershell.0\n\tln -f ${DESTDIR}${MDIR}/getprotoent.0 ${DESTDIR}${MDIR}/getprotobyname.0\n\tln -f ${DESTDIR}${MDIR}/getprotoent.0 ${DESTDIR}${MDIR}/getprotobynumber.0\n\tln -f ${DESTDIR}${MDIR}/getprotoent.0 ${DESTDIR}${MDIR}/setprotoent.0\n\tln -f ${DESTDIR}${MDIR}/getusershell.0 ${DESTDIR}${MDIR}/setusershell.0\n\tln -f ${DESTDIR}${MDIR}/gethostbyname.0 ${DESTDIR}${MDIR}/endhostent.0\n\tln -f ${DESTDIR}${MDIR}/gethostbyname.0 ${DESTDIR}${MDIR}/gethostbyaddr.0\n\tln -f ${DESTDIR}${MDIR}/gethostbyname.0 ${DESTDIR}${MDIR}/gethostent.0\n\tln -f ${DESTDIR}${MDIR}/gethostbyname.0 ${DESTDIR}${MDIR}/sethostent.0\n\tln -f ${DESTDIR}${MDIR}/gethostbyname.0 ${DESTDIR}${MDIR}/sethostfile.0\n\tln -f ${DESTDIR}${MDIR}/setmode.0 ${DESTDIR}${MDIR}/getmode.0\n\tln -f ${DESTDIR}${MDIR}/compat-sys5.0 ${DESTDIR}${MDIR}/memccpy.0\n\tln -f ${DESTDIR}${MDIR}/compat-sys5.0 ${DESTDIR}${MDIR}/memchr.0\n\tln -f ${DESTDIR}${MDIR}/compat-sys5.0 ${DESTDIR}${MDIR}/memcmp.0\n\tln -f ${DESTDIR}${MDIR}/compat-sys5.0 ${DESTDIR}${MDIR}/memcpy.0\n\tln -f ${DESTDIR}${MDIR}/compat-sys5.0 ${DESTDIR}${MDIR}/memset.0\n\tln -f ${DESTDIR}${MDIR}/compat-sys5.0 ${DESTDIR}${MDIR}/strchr.0\n\tln -f ${DESTDIR}${MDIR}/compat-sys5.0 ${DESTDIR}${MDIR}/strrchr.0\n\tln -f ${DESTDIR}${MDIR}/compat-sys5.0 ${DESTDIR}${MDIR}/tmpnam.0\n\tln -f ${DESTDIR}${MDIR}/compat-sys5.0 ${DESTDIR}${MDIR}/tmpfile.0\n\tln -f ${DESTDIR}${MDIR}/compat-sys5.0 ${DESTDIR}${MDIR}/tempnam.0\n\tln -f ${DESTDIR}${MDIR}/sleep.0 ${DESTDIR}${MDIR}/usleep.0\n\tln -f ${DESTDIR}${MDIR}/getenv.0 ${DESTDIR}${MDIR}/setenv.0\n\tln -f ${DESTDIR}${MDIR}/getenv.0 ${DESTDIR}${MDIR}/unsetenv.0\n\tln -f ${DESTDIR}${MDIR}/setruid.0 ${DESTDIR}${MDIR}/setrgid.0\n\nFRC:\n"
  },
  {
    "path": "share/man/man3/abort.3",
    "content": ".\\\"\t@(#)abort.3\t6.3 (Berkeley) 5/27/86\n.\\\"\n.TH ABORT 3 \"May 27, 1986\"\n.AT 3\n.SH NAME\nabort \\- generate a fault\n.SH DESCRIPTION\n.I Abort\nexecutes an instruction which is illegal in user mode.\nThis causes a signal that normally terminates\nthe process with a core dump, which may be used for debugging.\n.SH SEE ALSO\nadb(1), sigvec(2), exit(2)\n.SH DIAGNOSTICS\nUsually ``Illegal instruction \\- core dumped'' from the shell.\n.SH BUGS\nThe abort() function does not flush standard I/O buffers.  Use\n\\fIfflush\\fP\\|(3S).\n"
  },
  {
    "path": "share/man/man3/abs.3",
    "content": ".\\\"\t@(#)abs.3\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH ABS 3 \"May 15, 1985\"\n.AT 3\n.SH NAME\nabs \\- integer absolute value\n.SH SYNOPSIS\n.nf\n.B abs(i)\n.B int i;\n.fi\n.SH DESCRIPTION\n.I Abs\nreturns the absolute value of its integer operand.\n.SH SEE ALSO\nfloor(3M) for\n.I fabs\n.SH BUGS\nApplying the \\fIabs\\fP function to the most negative integer generates a\nresult which is the most negative integer.  That is, \n.IP \"abs(0x80000000)\"\n.LP\nreturns 0x80000000 as a result.\n"
  },
  {
    "path": "share/man/man3/alarm.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)alarm.3c\t6.3 (Berkeley) 5/27/86\n.\\\"\n.TH ALARM 3C  \"May 27, 1986\"\n.UC 4\n.SH NAME\nalarm \\- schedule signal after specified time\n.SH SYNOPSIS\n.nf\n.B alarm(seconds)\n.B unsigned seconds;\n.fi\n.SH DESCRIPTION\n.ft B\nThis interface is made obsolete by setitimer(2).\n.ft R\n.PP\n.I Alarm\ncauses signal SIGALRM, see\n.IR sigvec (2),\nto be sent to the invoking process\nin a number of seconds given by the argument.\nUnless caught or ignored, the signal terminates the process.\n.PP\nAlarm requests are not stacked; successive calls reset the alarm clock.\nIf the argument is 0, any alarm request is canceled.\nBecause of scheduling delays,\nresumption of execution of when the signal is\ncaught may be delayed an arbitrary amount.\nThe longest specifiable delay time is 2147483647 seconds.\n.PP\nThe return value is the amount of time previously remaining in the alarm clock.\n.SH \"SEE ALSO\"\nsigpause(2), sigvec(2), signal(3C), sleep(3), ualarm(3), usleep(3)\n"
  },
  {
    "path": "share/man/man3/asinh.3",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)asinh.3m\t6.2 (Berkeley) 5/12/86\n.\\\"\n.TH ASINH 3M  \"May 12, 1986\"\n.UC 6\n.ds up \\fIulp\\fR\n.SH NAME\nasinh, acosh, atanh \\- inverse hyperbolic functions\n.SH SYNOPSIS\n.nf\n.B #include <math.h>\n.PP\n.B double asinh(x)\n.B double x;\n.PP\n.B double acosh(x)\n.B double x;\n.PP\n.B double atanh(x)\n.B double x;\n.fi\n.SH DESCRIPTION\nThese functions compute the designated inverse hyperbolic functions for real\narguments.\n.SH ERROR (due to Roundoff etc.)\nThese functions inherit much of their error from log1p described in\nexp(3M).  On a VAX, acosh is accurate to about 3 \\*(ups,\nasinh and atanh to about 2 \\*(ups.\nAn \\*(up is one \\fIU\\fRnit in the \\fIL\\fRast \\fIP\\fRlace carried.\n.SH DIAGNOSTICS\nAcosh returns the reserved operand on a VAX if the argument is less than 1.\n.PP\nAtanh returns the reserved operand on a VAX if the argument has absolute\nvalue bigger than or equal to 1.\n.SH SEE ALSO\nmath(3M), exp(3M), infnan(3M)\n.SH AUTHOR\nW. Kahan, Kwok\\-Choi Ng\n"
  },
  {
    "path": "share/man/man3/assert.3",
    "content": ".\\\"\t@(#)assert.3\t6.2 (Berkeley) 5/12/86\n.\\\"\n.TH ASSERT 3 \"May 12, 1986\"\n.AT 3\n.SH NAME\nassert \\- program verification\n.SH SYNOPSIS\n.B #include <assert.h>\n.PP\n.B assert(expression)\n.SH DESCRIPTION\n.PP\n.I Assert\nis a macro that indicates\n.I expression\nis expected to be true at this point in the program.\nIt causes an\n.IR exit (2)\nwith a diagnostic comment on the standard output when\n.I expression\nis false (0).\nCompiling with the \n.IR cc (1)\noption\n.SM\n.B \\-DNDEBUG\neffectively deletes\n.I assert\nfrom the program.\n.SH DIAGNOSTICS\n`Assertion failed: file\n.I f\nline\n.I n.'\n.I F\nis the source file and\n.I n\nthe source line number of the\n.I assert\nstatement.\n"
  },
  {
    "path": "share/man/man3/atof.3",
    "content": ".\\\"\t@(#)atof.3\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH ATOF 3  \"May 15, 1985\"\n.AT 3\n.SH NAME\natof, atoi, atol \\- convert ASCII to numbers\n.SH SYNOPSIS\n.nf\n.B double atof(nptr)\n.B char *nptr;\n.PP\n.B atoi(nptr)\n.B char *nptr;\n.PP\n.B long atol(nptr)\n.B char *nptr;\n.fi\n.SH DESCRIPTION\nThese functions convert a string pointed to by\n.I nptr\nto floating, integer, and long integer representation respectively.\nThe first unrecognized character ends the string.\n.PP\n.I Atof\nrecognizes an optional string of spaces, then an optional sign, then\na string of digits optionally containing a decimal\npoint, then an optional `e' or `E' followed by an optionally signed integer.\n.PP\n.I Atoi\nand\n.I atol\nrecognize an optional string of spaces, then an optional sign, then a\nstring of\ndigits.\n.SH SEE ALSO\nscanf(3S)\n.SH BUGS\nThere are no provisions for overflow.\n"
  },
  {
    "path": "share/man/man3/basename.3",
    "content": ".\\\" $OpenBSD: basename.3,v 1.25 2020/10/20 19:30:14 naddy Exp $\n.\\\"\n.\\\" Copyright (c) 1997 Todd C. Miller <millert@openbsd.org>\n.\\\"\n.\\\" Permission to use, copy, modify, and distribute this software for any\n.\\\" purpose with or without fee is hereby granted, provided that the above\n.\\\" copyright notice and this permission notice appear in all copies.\n.\\\"\n.\\\" THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n.\\\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n.\\\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n.\\\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n.\\\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n.\\\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n.\\\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n.\\\"\n.Dd $Mdocdate: October 20 2020 $\n.Dt BASENAME 3\n.Os\n.Sh NAME\n.Nm basename\n.Nd extract the base portion of a pathname\n.Sh SYNOPSIS\n.In libgen.h\n.Ft char *\n.Fn basename \"char *path\"\n.Sh DESCRIPTION\nThe\n.Fn basename\nfunction returns the last component from the pathname pointed to by\n.Ar path ,\ndeleting any trailing\n.Sq \\&/\ncharacters.\nIf\n.Ar path\nconsists entirely of\n.Sq \\&/\ncharacters, a pointer to the string\n.Qq \\&/\nis returned.\nIf\n.Ar path\nis a null pointer or the empty string, a pointer to the string\n.Qq \\&.\nis returned.\n.Sh RETURN VALUES\nOn successful completion,\n.Fn basename\nreturns a pointer to the last component of\n.Ar path .\n.Pp\nIf\n.Fn basename\nfails, a null pointer is returned and the global variable\n.Va errno\nis set to indicate the error.\n.Sh ERRORS\nThe following error codes may be set in\n.Va errno :\n.Bl -tag -width Er\n.It Bq Er ENAMETOOLONG\nThe path component to be returned was larger than\n.Dv PATH_MAX .\n.El\n.Sh SEE ALSO\n.Xr basename 1 ,\n.Xr dirname 1 ,\n.Xr dirname 3\n.Sh STANDARDS\nThe\n.Fn basename\nfunction conforms to the X/Open System Interfaces option of the\n.St -p1003.1-2008\nspecification.\n.Sh HISTORY\nThe\n.Fn basename\nfunction first appeared in\n.Ox 2.2 .\n.Sh AUTHORS\n.An Todd C. Miller\n.Sh CAVEATS\n.Fn basename\nreturns a pointer to internal static storage space that will be overwritten\nby subsequent calls.\n.Pp\nOther vendor implementations of\n.Fn basename\nmay modify the contents of the string passed to\n.Fn basename ;\nthis should be taken into account when writing code which calls this function\nif portability is desired.\n"
  },
  {
    "path": "share/man/man3/bstring.3",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)bstring.3\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH BSTRING 3  \"November 24, 2025\"\n.UC 5\n.SH NAME\nbcopy, bcmp, bzero, ffs \\- bit and byte string operations\n.SH SYNOPSIS\n.nf\n.B bcopy(src, dst, length)\n.B char *src, *dst;\n.B int length;\n.PP\n.B bcmp(b1, b2, length)\n.B char *b1, *b2;\n.B int length;\n.PP\n.B bzero(b, length)\n.B void *b;\n.B size_t length;\n.PP\n.B ffs(i)\n.B long i;\n.fi\n.SH DESCRIPTION\nThe functions\n.IR bcopy ,\n.IR bcmp ,\nand\n.I bzero\noperate on variable length strings of bytes.\nThey do not check for null bytes as the routines in\n.IR string (3)\ndo.\n.PP\n.I Bcopy\ncopies\n.I length\nbytes from string\n.I src\nto the string\n.IR dst .\n.PP\n.I Bcmp\ncompares byte string\n.I b1\nagainst byte string\n.IR b2 ,\nreturning zero if they are identical,\nnon-zero otherwise.  Both strings are\nassumed to be\n.I length\nbytes long.\n.PP\n.I Bzero\nplaces\n.I length\n0 bytes in the string\n.IR b .\n.PP\n.I Ffs\nfind the first bit set in the argument passed it and\nreturns the index of that bit.  Bits are numbered\nstarting at 1.  A return value of 0 indicates the\nvalue passed is zero.\n.SH BUGS\nThe\n.I bcopy\nroutine take parameters backwards from\n.IR strcpy .\n"
  },
  {
    "path": "share/man/man3/byteorder.3",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)byteorder.3n\t6.2 (Berkeley) 5/15/86\n.\\\"\n.TH BYTEORDER 3N \"May 15, 1986\"\n.UC 5\n.SH NAME\nhtonl, htons, ntohl, ntohs \\- convert values between host and network byte order\n.SH SYNOPSIS\n.nf\n.B #include <sys/types.h>\n.B #include <netinet/in.h>\n.PP\n.B netlong = htonl(hostlong);\n.B u_long netlong, hostlong;\n.PP\n.B netshort = htons(hostshort);\n.B u_short netshort, hostshort;\n.PP\n.B hostlong = ntohl(netlong);\n.B u_long hostlong, netlong;\n.PP\n.B hostshort = ntohs(netshort);\n.B u_short hostshort, netshort;\n.fi\n.SH DESCRIPTION\nThese routines convert 16 and 32 bit quantities between network\nbyte order and host byte order.  On machines such as the SUN\nthese routines are defined as null macros in the include file\n.RI < netinet/in.h >.\n.PP\nThese routines are most often used in conjunction with Internet\naddresses and ports as returned by\n.IR gethostbyname (3N)\nand\n.IR getservent (3N).\n.SH \"SEE ALSO\"\ngethostbyname(3N),\ngetservent(3N)\n.SH BUGS\nThe VAX handles bytes backwards from most everyone else in\nthe world.  This is not expected to be fixed in the near future.\n"
  },
  {
    "path": "share/man/man3/compat-sys5.3",
    "content": ".\\\" Copyright (c) 1988 Regents of the University of California.\n.\\\" All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms are permitted\n.\\\" provided that the above copyright notice and this paragraph are\n.\\\" duplicated in all such forms and that any documentation,\n.\\\" advertising materials, and other materials related to such\n.\\\" distribution and use acknowledge that the software was developed\n.\\\" by the University of California, Berkeley.  The name of the\n.\\\" University may not be used to endorse or promote products derived\n.\\\" from this software without specific prior written permission.\n.\\\" THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n.\\\" IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n.\\\" WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n.\\\"\n.\\\"\t@(#)compat-sys5.3\t5.6.1 (2.11BSD) 1996/1/12\n.\\\"\n.TH COMPATS5 3 \"January 12, 1996\"\n.UC 7\n.SH NAME\nmemccpy, memchr, memcmp, memcpy, memset, strchr, strrchr, tempnam,\ntmpfile, tmpnam \\- System V compatibility routines\n.SH SYNOPSIS\n.nf\n.B char *memccpy(from, to, ch, count)\n.B char *from, *to;\n.B int ch, count;\n.PP\n.B char *memchr(str, ch, count)\n.B char *str;\n.B int ch, count;\n.PP\n.B int memcmp(str1, str2, count)\n.B char *str1, *str2;\n.B int count;\n.PP\n.B char *memcpy(from, to, count)\n.B char *from, to;\n.B int count;\n.PP\n.B char *memset(str, ch, count)\n.B char *str;\n.B int ch, count;\n.PP\n.B char *strchr(str, ch);\n.B char *str;\n.B int ch;\n.PP\n.B char *tempnam(tmpdir, prefix)\n.B char *tmpdir, *prefix;\n.PP\n.B char *tmpfile()\n.PP\n.B char *tmpnam(str)\n.B char *str;\n.PP\n.SH COMMENT\nThe \\fI#defines\\fP \\fIP_tmpdir\\fP and \\fIL_tmpnam\\fP, used by the routines\n\\fItempnam\\fP, \\fItmpfile\\fP, and \\fItmpnam\\fP are not available in\n\\fI<stdio.h>\\fP.  If the code requires them, just use:\n.PP\n#include <sys/param.h>\n.br\n#define\tP_tmpdir\t\"/usr/tmp\"\n#define\tL_tmpnam\tMAXPATHLEN\n.PP\nAlso, note that the caveat in the System V manual page that these functions\ncan start recycling previously used names is untrue in this system.\n.SH DESCRIPTION\nThe above routines are available and behave as in System V.\n.PP\n.BR strchr ()\nand\n.BR strrchr ()\nare simply an alternate entry points into \n.BR index ()\nand\n.BR rindex ()\nrespectively.\n"
  },
  {
    "path": "share/man/man3/crypt.3",
    "content": ".\\\"\t@(#)crypt.3\t6.1.1.1 (Berkeley) 8/12/86\n.\\\"\n.TH CRYPT 3  \"August 12, 1986\"\n.AT 3\n.SH NAME\ncrypt, setkey, encrypt \\- DES encryption\n.SH SYNOPSIS\n.nf\n.B char *crypt(key, salt)\n.B char *key, *salt;\n.PP\n.B setkey(key)\n.B char *key;\n.PP\n.B encrypt(block, edflag)\n.B char *block;\n.fi\n.SH DESCRIPTION\n.I Crypt\nis the password encryption routine.\nIt is based on the NBS Data Encryption Standard, with\nvariations intended (among other things) to frustrate use of hardware\nimplementations of the DES for key search.\n.PP\nThe first argument to\n.I crypt\nis normally a user's typed password.\nThe second is a 2-character string chosen from the\nset [a-zA-Z0-9./].\nThe\n.I salt\nstring is used to perturb the DES algorithm in one of 4096\ndifferent ways, after which the password\nis used as the key to encrypt repeatedly a constant string.\nThe returned value points to the encrypted password,\nin the same alphabet as the salt.\nThe first two characters are the salt itself.\n.PP\nThe other entries provide (rather primitive)\naccess to the actual DES algorithm.\nThe argument of\n.I setkey\nis a character array of length 64 containing only the characters\nwith numerical value 0 and 1.\nIf this string is divided into groups of 8,\nthe low-order bit in each group is ignored,\nleading to a 56-bit key which is set into the machine.\n.PP\nThe argument to the\n.I encrypt\nentry is likewise a character array of length 64\ncontaining 0's and 1's.\nThe argument array is modified in place\nto a similar array\nrepresenting the bits of the argument after having been\nsubjected to the DES algorithm using the key set by\n.I setkey.\nThe\n.I edflag\nflag is ignored;\nthe argument can only be encrypted.\n.SH \"SEE ALSO\"\npasswd(1), passwd(5), login(1), getpass(3)\n.SH BUGS\nThe return value\npoints to static data whose content is overwritten\nby each call.\n"
  },
  {
    "path": "share/man/man3/ctime.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ctime.3\t6.7.1 (2.11BSD) 1996/11/27\n.\\\"\n.TH CTIME 3  \"November 27, 1996\"\n.UC 4\n.SH NAME\nctime, localtime, gmtime, asctime, timezone, tzset \\-  convert date and time to ASCII\n.SH SYNOPSIS\n.nf\n.B void tzset()\n.PP\n.B char *ctime(clock)\n.B time_t *clock;\n.PP\n.B #include <time.h>\n.PP\n.B char *asctime(tm)\n.B struct tm *tm;\n.PP\n.B struct tm *localtime(clock)\n.B time_t *clock;\n.PP\n.B struct tm *gmtime(clock)\n.B time_t *clock;\n.PP\n.B char *timezone(zone, dst)\n.fi\n.fi\n.SH DESCRIPTION\n\\fITzset\\fP uses the value of the environment variable \\fBTZ\\fP to\nset up the time conversion information used by \\fIlocaltime\\fP.\n.PP\nIf \\fBTZ\\fP does not appear in the environment, the \\fBTZDEFAULT\\fP\nfile (as defined in \\fItzfile.h\\fP) is used by \\fIlocaltime\\fP.  If\nthis file fails for any reason, the GMT offset as provided by the\nkernel is used.  In this case, DST is ignored, resulting in the time\nbeing incorrect by some amount if DST is currently in effect.  If\nthis fails for any reason, GMT is used.\n.PP\nIf \\fBTZ\\fP appears in the environment but its value is a null string,\nGreenwich Mean Time is used; if \\fBTZ\\fP appears and begins with a\nslash, it is used as the absolute pathname of the \\fItzfile\\fP(5)-format\nfile from which to read the time conversion information; if \\fBTZ\\fP\nappears and begins with a character other than a slash, it's used as\na pathname relative to the system time conversion information directory,\ndefined as \\fBTZDIR\\fP in the include file \\fItzfile.h\\fP.  If\nthis file fails for any reason, GMT is used.\n.PP\nPrograms that always wish to use local wall clock time should explicitly\nremove the environmental variable \\fBTZ\\fP with \\fIunsetenv\\fP(3).\n.PP\n\\fICtime\\fP converts a long integer, pointed to by \\fIclock\\fP,\nsuch as returned by \\fItime\\fP(2) into ASCII and returns a pointer\nto a 26-character string in the following form.  All the fields\nhave constant width.\n.PP\n    Sun Sep 16 01:03:52 1973\\\\n\n.PP\n.I Localtime\nand\n.I gmtime\nreturn pointers to structures containing\nthe broken-down time.\n.I Localtime\ncorrects for the time zone and possible daylight savings time;\n.I gmtime\nconverts directly to GMT, which is the time UNIX uses.\n.I Asctime\nconverts a broken-down time to ASCII and returns a pointer\nto a 26-character string.\n.PP\nThe structure declaration from the include file is:\n.PP\n.RS\n.nf\n.nr .0 .8i+\\w'int tm_isdst'u\n.ta .5i \\n(.0u \\n(.0u+\\w'/* 0-000'u+1n\nstruct tm {\n\tint tm_sec;\t/* 0-59\tseconds */\n\tint tm_min;\t/* 0-59\tminutes */\n\tint tm_hour;\t/* 0-23\thour */\n\tint tm_mday;\t/* 1-31\tday of month */\n\tint tm_mon;\t/* 0-11\tmonth */\n\tint tm_year;\t/* 0-\tyear \\- 1900 */\n\tint tm_wday;\t/* 0-6\tday of week (Sunday = 0) */\n\tint tm_yday;\t/* 0-365\tday of year */\n\tint tm_isdst;\t/* flag:\tdaylight savings time in effect */\n\tchar **tm_zone;\t/* abbreviation of timezone name */\n\tlong tm_gmtoff;\t/* offset from GMT in seconds */\n};\n.fi\n.RE\n.PP\n\\fITm_isdst\\fP is non-zero if a time zone adjustment such as Daylight\nSavings time is in effect.\n.PP\n\\fITm_gmtoff\\fP is the offset (in seconds) of the time represented\nfrom GMT, with positive values indicating East of Greenwich.\n.PP\n\\fITimezone\\fP remains for compatibility reasons only; it's impossible to\nreliably map timezone's arguments (\\fIzone\\fP, a \"minutes west of GMT\" value\nand \\fIdst\\fP, a \"daylight saving time in effect\" flag) to a time zone\nabbreviation.\n.PP\nIf the environmental string \\fITZNAME\\fP exists, \\fItimezone\\fP returns\nits value, unless it consists of two comma separated strings, in which\ncase the second string is returned if \\fIdst\\fP is non-zero, else\nthe first string.  If \\fITZNAME\\fP doesn't exist, \\fIzone\\fP is checked\nfor equality with a built-in table of values, in which case \\fItimezone\\fP\nreturns the time zone or daylight time zone abbreviation associated with\nthat value.  If the requested \\fIzone\\fP does not appear in the table, the\ndifference from GMT is returned; e.g. in Afghanistan,\n\\fItimezone(-(60*4+30), 0)\\fP is appropriate because it is 4:30 ahead of\nGMT, and the string \\fBGMT+4:30\\fP is returned.  Programs that in the\npast used the \\fItimezone\\fP function should return the zone name as\nset by \\fIlocaltime\\fP to assure correctness.\n.SH FILES\n.ta \\w'/usr/share/zoneinfo'u\n/usr/share/zoneinfo\ttime zone information directory\n.br\n/etc/localtime\tlocal time zone file\n.SH SEE ALSO\ngettimeofday(2), getenv(3), time(3), tzfile(5), environ(7)\n.SH NOTE\nThe return values point to static data whose content is overwritten by\neach call.  The \\fBtm_zone\\fP field of a returned \\fBstruct tm\\fP\npoints to a static array of characters, which will also be overwritten\nat the next call (and by calls to \\fItzset\\fP).\n"
  },
  {
    "path": "share/man/man3/ctype.3",
    "content": ".\\\"\t@(#)ctype.3\t6.4 (Berkeley) 5/12/86\n.\\\"\n.TH CTYPE 3  \"May 12, 1986\"\n.AT 3\n.SH NAME\nisalpha, isupper, islower, isdigit, isxdigit, isalnum, isspace, ispunct, isprint, isgraph, iscntrl, isascii, toupper, tolower, toascii \\- character classification macros\n.SH SYNOPSIS\n.B #include <ctype.h>\n.PP\n.B isalpha(c)\n.PP\n.B . . .\n.SH DESCRIPTION\nThese macros classify ASCII-coded integer values\nby table lookup.\nEach is a predicate returning nonzero for true,\nzero for false.\n.I Isascii\nand\n.I toascii\nare defined on all integer values; the rest\nare defined only where \n.I isascii\nis true and on the single non-ASCII value\nEOF (see\n.IR stdio (3S)).\n.TP 15n\n.I isalpha\n.I c\nis a letter\n.TP\n.I isupper\n.I c\nis an upper case letter\n.TP\n.I islower \n.I c\nis a lower case letter\n.TP\n.I isdigit\n.I c\nis a digit\n.TP\n.I isxdigit\n.I c\nis a hex digit\n.TP\n.I isalnum\n.I c\nis an alphanumeric character\n.TP\n.I isspace\n.I c\nis a space, tab, carriage return, newline, vertical tab, or formfeed\n.TP\n.I ispunct\n.I c\nis a punctuation character (neither control nor alphanumeric)\n.TP\n.I isprint\n.I c\nis a printing character, code 040(8) (space) through 0176 (tilde)\n.TP\n.I isgraph\n.I c\nis a printing character, similar to\n.I isprint\nexcept false for space.\n.TP\n.I iscntrl\n.I c\nis a delete character (0177) or ordinary control character\n(less than 040).\n.TP\n.I isascii\n.I c\nis an ASCII character, code less than 0200\n.TP\n.I tolower\n.I c\nis converted to lower case.  Return value is undefined if not \n.I isupper(c).\n.TP\n.I toupper\n.I c\nis converted to upper case.  Return value is undefined if not \n.I islower(c).\n.TP\n.I toascii\n.I c\nis converted to be a valid ascii character.\n.SH \"SEE ALSO\"\nascii(7)\n"
  },
  {
    "path": "share/man/man3/curses.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)curses.3x\t6.3 (Berkeley) 4/23/86\n.\\\"\n.TH CURSES 3X \"April 23, 1986\"\n.UC 4\n.SH NAME\ncurses \\- screen functions with ``optimal'' cursor motion\n.SH SYNOPSIS\n.B cc\n[ flags ] files\n.B \\-lcurses \\-ltermcap\n[ libraries ]\n.SH DESCRIPTION\nThese routines give the user a method of updating screens with reasonable\noptimization.  They keep an image of the current screen,\nand the user sets up an image of a new one.  Then the\n.I refresh()\ntells the routines to make the current screen look like the new one.\nIn order to initialize the routines, the routine\n.I initscr()\nmust be called before any of the other routines that deal with windows and\nscreens are used.  The routine\n.I endwin()\nshould be called before exiting.\n.SH SEE ALSO\n.I \"Screen Updating and Cursor Movement Optimization: A Library Package,\"\nKen Arnold,\n.br\nioctl(2),\ngetenv(3),\ntty(4),\ntermcap(5)\n.SH AUTHOR\nKen Arnold\n.SH FUNCTIONS\n.nf\n.ds w \\fIwin\\fP\n.ds s \\fIstdscr\\fP\n.ta 3i\naddch(ch)\tadd a character to \\*s\naddstr(str)\tadd a string to \\*s\nbox(win,vert,hor)\tdraw a box around a window\ncbreak()\tset cbreak mode\nclear()\tclear \\*s\nclearok(scr,boolf)\tset clear flag for \\fIscr\\fP\nclrtobot()\tclear to bottom on \\*s\nclrtoeol()\tclear to end of line on \\*s\ndelch()\tdelete a character\ndeleteln()\tdelete a line\ndelwin(win)\tdelete \\*w\necho()\tset echo mode\nendwin()\tend window modes\nerase()\terase \\*s\nflusok(win,boolf)\tset flush-on-refresh flag for \\fIwin\\fP\ngetch()\tget a char through \\*s\ngetcap(name)\tget terminal capability \\fIname\\fP\ngetstr(str)\tget a string through \\*s\ngettmode()\tget tty modes\ngetyx(win,y,x)\tget (y,x) co-ordinates\ninch()\tget char at current (y,x) co-ordinates\ninitscr()\tinitialize screens\ninsch(c)\tinsert a char\ninsertln()\tinsert a line\nleaveok(win,boolf)\tset leave flag for \\*w\nlongname(termbuf,name)\tget long name from \\fItermbuf\\fP\nmove(y,x)\tmove to (y,x) on \\*s\nmvcur(lasty,lastx,newy,newx)\tactually move cursor\nnewwin(lines,cols,begin_y,begin_x)\\ \tcreate a new window\nnl()\tset newline mapping\nnocbreak()\tunset cbreak mode\nnoecho()\tunset echo mode\nnonl()\tunset newline mapping\nnoraw()\tunset raw mode\noverlay(win1,win2)\toverlay win1 on win2\noverwrite(win1,win2)\toverwrite win1 on top of win2\nprintw(fmt,arg1,arg2,...)\tprintf on \\*s\nraw()\tset raw mode\nrefresh()\tmake current screen look like \\*s\nresetty()\treset tty flags to stored value\nsavetty()\tstored current tty flags\nscanw(fmt,arg1,arg2,...)\tscanf through \\*s\nscroll(win)\tscroll \\*w one line\nscrollok(win,boolf)\tset scroll flag\nsetterm(name)\tset term variables for name\nstandend()\tend standout mode\nstandout()\tstart standout mode\nsubwin(win,lines,cols,begin_y,begin_x)\\ \tcreate a subwindow\ntouchline(win,y,sx,ex)\tmark line \\fIy\\fP \\fIsx\\fP through \\fIsy\\fP as changed\ntouchoverlap(win1,win2)\tmark overlap of \\fIwin1\\fP on \\fIwin2\\fP as changed\ntouchwin(win)\t\\*(lqchange\\*(rq all of \\*w\nunctrl(ch)\tprintable version of \\fIch\\fP\nwaddch(win,ch)\tadd char to \\*w\nwaddstr(win,str)\tadd string to \\*w\nwclear(win)\tclear \\*w\nwclrtobot(win)\tclear to bottom of \\*w\nwclrtoeol(win)\tclear to end of line on \\*w\nwdelch(win,c)\tdelete char from \\*w\nwdeleteln(win)\tdelete line from \\*w\nwerase(win)\terase \\*w\nwgetch(win)\tget a char through \\*w\nwgetstr(win,str)\tget a string through \\*w\nwinch(win)\tget char at current (y,x) in \\*w\nwinsch(win,c)\tinsert char into \\*w\nwinsertln(win)\tinsert line into \\*w\nwmove(win,y,x)\tset current (y,x) co-ordinates on \\*w\nwprintw(win,fmt,arg1,arg2,...)\\ \tprintf on \\*w\nwrefresh(win)\tmake screen look like \\*w\nwscanw(win,fmt,arg1,arg2,...)\\ \tscanf through \\*w\nwstandend(win)\tend standout mode on \\*w\nwstandout(win)\tstart standout mode on \\*w\n.SH BUGS\n"
  },
  {
    "path": "share/man/man3/daemon.3",
    "content": ".\\\" Copyright (c) 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"\t@(#)daemon.3\t8.1.1 (2.11BSD GTE) 2/5/95\n.TH DAEMON 3 \"February 3, 1995\"\n.UC 4\n.SH NAME\ndaemon \\- run in the background\n.SH SYNOPSIS\n.nf\n.ft B\nint\ndaemon(nochdir, noclose)\n    int nochdir, noclose;\n.ft R\n.fi\n.SH DESCRIPTION\n.PP\nThe\n.B daemon\nfunction is for programs wishing to detach themselves from the\ncontrolling terminal and run in the background as system daemons.\n.PP\nUnless the argument\n.I nochdir\nis non-zero,\n.B daemon\nchanges the current working directory to the root (``/'').\n.PP\nUnless the argument\n.I noclose\nis non-zero,\n.B daemon\nwill redirect standard input, standard output and standard error\nto ``/dev/null''.\n.SH ERRORS\nThe function\n.B daemon\nmay fail and set\n.I errno\nfor any of the errors specified for the library functions\n.IR fork (2) .\n.SH SEE ALSO\nfork(2), ioctl(2).\n.SH HISTORY\nThe\n.B daemon\nfunction first appeared in 4.4BSD.\n"
  },
  {
    "path": "share/man/man3/dbm.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)dbm.3x\t6.3 (Berkeley) 5/12/86\n.\\\"\n.TH DBM 3X  \"May 12, 1986\"\n.UC 4\n.SH NAME\ndbminit, fetch, store, delete, firstkey, nextkey \\- data base subroutines\n.SH SYNOPSIS\n.nf\n.PP\n.B \"#include <dbm.h>\"\n.PP\n.B typedef struct {\n.B \"\tchar *dptr;\"\n.B \"\tint dsize;\"\n.B } datum;\n.PP\n.B dbminit(file)\n.B char *file;\n.PP\n.B datum fetch(key)\n.B datum key;\n.PP\n.B store(key, content)\n.B datum key, content;\n.PP\n.B delete(key)\n.B datum key;\n.PP\n.B datum firstkey()\n.PP\n.B datum nextkey(key)\n.B datum key;\n.SH DESCRIPTION\n.ft B\nNote: the dbm library has been superceded by ndbm(3),\nand is now implemented using ndbm.\n.ft R\nThese functions maintain key/content pairs in a data base.\nThe functions will handle very large (a billion blocks)\ndatabases and will access a keyed item in one or two file system accesses.\nThe functions are obtained with the loader option\n.BR \\-ldbm .\n.PP\n.IR Key s\nand\n.IR content s\nare described by the\n.I datum\ntypedef.  A\n.I datum\nspecifies a string of\n.I dsize\nbytes pointed to by\n.I dptr.\nArbitrary binary data, as well as normal ASCII strings, are allowed.\nThe data base is stored in two files.\nOne file is a directory containing a bit map and has `.dir' as its suffix.\nThe second file contains all data and has `.pag' as its suffix.\n.PP\nBefore a database can be accessed, it must be opened by\n.I dbminit.\nAt the time of this call, the files\n.IB file .dir\nand\n.IB file .pag\nmust exist.\n(An empty database is created by creating zero-length\n`.dir' and `.pag' files.)\n.PP\nOnce open, the data stored under a key is accessed by\n.I fetch\nand data is placed under a key by\n.IR store .\nA key (and its associated contents) is deleted by\n.IR delete .\nA linear pass through all keys in a database may be made,\nin an (apparently) random order, by use of\n.I firstkey\nand\n.IR nextkey .\n.I Firstkey\nwill return the first key in the database.  With any key\n.I nextkey\nwill return the next key in the database.\nThis code will traverse the data base:\n.IP\n.B for\n(key = firstkey(); key.dptr != NULL; key = nextkey(key))\n.SH DIAGNOSTICS\nAll functions that return an\n.I int\nindicate errors with negative values.  A zero return indicates ok.\nRoutines that return a\n.I datum\nindicate errors with a null (0)\n.I dptr.\n.SH SEE ALSO\nndbm(3)\n.SH BUGS\nThe `.pag' file will contain holes so that its apparent size is about\nfour times its actual content.  Older UNIX systems may create real\nfile blocks for these holes when touched.  These files cannot be copied\nby normal means (cp, cat, tp, tar, ar) without filling in the holes.\n.PP\n.I Dptr\npointers returned by these subroutines point into static storage\nthat is changed by subsequent calls.\n.PP\nThe sum of the sizes of a key/content pair must not exceed\nthe internal block size (currently 1024 bytes).\nMoreover all key/content pairs that hash together must fit on a single block.\n.I Store\nwill return an error in the event that a disk block fills with inseparable data.\n.PP\n.I Delete\ndoes not physically reclaim file space,\nalthough it does make it available for reuse.\n.PP\nThe order of keys presented by\n.I firstkey\nand\n.I nextkey\ndepends on a hashing function, not on anything interesting.\n"
  },
  {
    "path": "share/man/man3/devname.3",
    "content": ".\\\" Copyright (c) 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)devname.3\t8.1.1 (2.11BSD GTE) 2/3/95\n.\\\"\n.TH DEVNAME 3 \"February 3, 1995\"\n.UC 4\n.SH NAME\ndevname \\- get device name\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/types.h>\n\nchar *\ndevname(dev, type)\n    dev_t dev;\n    mode_t type;\n.ft R\n.fi\n.SH DESCRIPTION\nThe\n.B devname\nfunction returns a pointer to the name of the block or character\ndevice in\n.IR /dev\nwith a device number of\n.I dev ,\nand a file type matching the one encoded in\n.I type\nwhich must be one of S_IFBLK or S_IFCHR.\nIf no device matches the specified values, or no information is\navailable, the string\n.I ??\nis returned.\n.SH SEE ALSO\nstat(2),\ndev_mkdb(8)\n.SH HISTORY\nThe\n.B devname\nfunction call appeared in 4.4BSD.\n"
  },
  {
    "path": "share/man/man3/directory.3",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)directory.3\t6.2 (Berkeley) 9/24/85\n.\\\"\n.TH DIRECTORY 3 \"September 24, 1985\"\n.UC 5\n.SH NAME\nopendir, readdir, telldir, seekdir, rewinddir, closedir \\- directory operations\n.SH SYNOPSIS\n.B #include <sys/types.h>\n.br\n.B #include <sys/dir.h>\n.PP\n.SM\n.B DIR\n.B *opendir(filename)\n.br\n.B char *filename;\n.PP\n.B struct direct\n.B *readdir(dirp)\n.br\n.SM\n.B DIR\n.B *dirp;\n.PP\n.B long\n.B telldir(dirp)\n.br\n.SM\n.B DIR\n.B *dirp;\n.PP\n.B seekdir(dirp, loc)\n.br\n.SM\n.B DIR\n.B *dirp;\n.br\n.B long loc;\n.PP\n.B rewinddir(dirp)\n.br\n.SM\n.B DIR\n.B *dirp;\n.PP\n.B closedir(dirp)\n.br\n.SM\n.B DIR\n.B *dirp;\n.SH DESCRIPTION\n.I Opendir\nopens the directory named by\n.I filename\nand associates a\n.I directory stream\nwith it.\n.I Opendir\nreturns a pointer to be used to identify the\n.I directory stream\nin subsequent operations.  The pointer\n.SM\n.B NULL\nis returned if\n.I filename\ncannot be accessed, or if it cannot\n.IR malloc (3)\nenough memory to hold the whole thing.\n.PP\n.I Readdir\nreturns a pointer to the next directory entry.  It returns\n.B NULL\nupon reaching the end of the directory or detecting an invalid\n.I seekdir\noperation.\n.PP\n.I Telldir\nreturns the current location associated with the named\n.I directory stream.\n.PP\n.I Seekdir\nsets the position of the next\n.I readdir\noperation on the\n.I directory stream.\nThe new position reverts to the one associated with the\n.I directory stream\nwhen the\n.I telldir\noperation was performed.  Values returned by\n.I telldir\nare good only for the lifetime of the DIR pointer from which they are derived.\nIf the directory is closed and then reopened, the \n.I telldir\nvalue may be invalidated due to undetected directory compaction.\nIt is safe to use a previous\n.I telldir\nvalue immediately after a call to\n.I opendir\nand before any calls to\n.I readdir.\n.PP\n.I Rewinddir\nresets the position of the named\n.I directory stream\nto the beginning of the directory.\n.PP\n.I Closedir\ncloses the named\n.I directory stream\nand frees the structure associated with the DIR pointer.\n.PP\nSample code which searchs a directory for entry ``name'' is:\n.PP\n.br\n\tlen = strlen(name);\n.br\n\tdirp = opendir(\".\");\n.br\n\tfor (dp = readdir(dirp); dp != NULL; dp = readdir(dirp))\n.br\n\t\tif (dp->d_namlen == len && !strcmp(dp->d_name, name)) {\n.br\n\t\t\tclosedir(dirp);\n.br\n\t\t\treturn FOUND;\n.br\n\t\t}\n.br\n\tclosedir(dirp);\n.br\n\treturn NOT_FOUND;\n.SH \"SEE ALSO\"\nopen(2),\nclose(2),\nread(2),\nlseek(2),\ndir(5)\n"
  },
  {
    "path": "share/man/man3/dirname.3",
    "content": ".\\\" $OpenBSD: dirname.3,v 1.24 2020/10/20 19:30:14 naddy Exp $\n.\\\"\n.\\\" Copyright (c) 1997 Todd C. Miller <millert@openbsd.org>\n.\\\"\n.\\\" Permission to use, copy, modify, and distribute this software for any\n.\\\" purpose with or without fee is hereby granted, provided that the above\n.\\\" copyright notice and this permission notice appear in all copies.\n.\\\"\n.\\\" THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n.\\\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n.\\\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n.\\\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n.\\\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n.\\\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n.\\\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n.\\\"\n.Dd $Mdocdate: October 20 2020 $\n.Dt DIRNAME 3\n.Os\n.Sh NAME\n.Nm dirname\n.Nd extract the directory portion of a pathname\n.Sh SYNOPSIS\n.In libgen.h\n.Ft char *\n.Fn dirname \"char *path\"\n.Sh DESCRIPTION\nThe\n.Fn dirname\nfunction is the converse of\n.Xr basename 3 ;\nit returns a pointer to the parent directory of the pathname pointed to by\n.Ar path .\nAny trailing\n.Sq \\&/\ncharacters are not counted as part of the directory\nname.\nIf\n.Ar path\nis a null pointer, the empty string, or contains no\n.Sq \\&/\ncharacters,\n.Fn dirname\nreturns a pointer to the string\n.Qq \\&. ,\nsignifying the current directory.\n.Sh RETURN VALUES\nOn successful completion,\n.Fn dirname\nreturns a pointer to the parent directory of\n.Ar path .\n.Pp\nIf\n.Fn dirname\nfails, a null pointer is returned and the global variable\n.Va errno\nis set to indicate the error.\n.Sh ERRORS\nThe following error codes may be set in\n.Va errno :\n.Bl -tag -width Er\n.It Bq Er ENAMETOOLONG\nThe path component to be returned was larger than\n.Dv PATH_MAX .\n.El\n.Sh SEE ALSO\n.Xr basename 1 ,\n.Xr dirname 1 ,\n.Xr basename 3\n.Sh STANDARDS\nThe\n.Fn dirname\nfunction conforms to the X/Open System Interfaces option of the\n.St -p1003.1-2008\nspecification.\n.Sh HISTORY\nThe\n.Fn dirname\nfunction first appeared in\n.Ox 2.2 .\n.Sh AUTHORS\n.An Todd C. Miller\n.Sh CAVEATS\n.Fn dirname\nreturns a pointer to internal static storage space that will be overwritten\nby subsequent calls.\n.Pp\nOther vendor implementations of\n.Fn dirname\nmay modify the contents of the string passed to\n.Fn dirname ;\nthis should be taken into account when writing code which calls this function\nif portability is desired.\n"
  },
  {
    "path": "share/man/man3/ecvt.3",
    "content": ".\\\"\t@(#)ecvt.3\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH ECVT 3  \"May 15, 1985\"\n.AT 3\n.SH NAME\necvt, fcvt, gcvt \\- output conversion\n.SH SYNOPSIS\n.nf\n.B char *ecvt(value, ndigit, decpt, sign)\n.B double value;\n.B int ndigit, *decpt, *sign;\n.PP\n.B char *fcvt(value, ndigit, decpt, sign)\n.B double value;\n.B int ndigit, *decpt, *sign;\n.PP\n.B char *gcvt(value, ndigit, buf)\n.B double value;\n.B char *buf;\n.fi\n.SH DESCRIPTION\n.I Ecvt\nconverts the \n.I value\nto a null-terminated string of\n.I ndigit\nASCII digits and returns a pointer thereto.\nThe position of the decimal point relative to the\nbeginning of the string is stored indirectly through\n.IR decpt \"\"\n(negative means to the left of the returned digits).\nIf the sign of the result is negative, the word pointed to by\n.IR sign \"\"\nis non-zero, otherwise it is zero.  The low-order digit is rounded.\n.PP\n.IR Fcvt \" is identical to \" \"ecvt\\fR, except that the correct digit\"\nhas been rounded for Fortran F-format output of the number\nof digits specified by\n.IR ndigit .\n.PP\n.I Gcvt\nconverts the\n.I value\nto a null-terminated ASCII string in\n.I buf\nand returns a pointer to \n.I buf.\nIt attempts to produce\n.I ndigit\nsignificant digits in Fortran F format if possible, otherwise E format,\nready for printing.  Trailing zeros may be suppressed.\n.SH \"SEE ALSO\"\nprintf(3)\n.SH BUGS\nThe return values point to static data\nwhose content is overwritten by each call.\n"
  },
  {
    "path": "share/man/man3/end.3",
    "content": ".\\\"\t@(#)end.3\t6.2 (Berkeley) 5/12/86\n.\\\"\n.TH END 3  \"May 12, 1986\"\n.AT 3\n.SH NAME\nend, etext, edata \\- last locations in program\n.SH SYNOPSIS\n.nf\n.B extern end;\n.B extern etext;\n.B extern edata;\n.fi\n.SH DESCRIPTION\nThese names refer neither to routines nor to locations with interesting\ncontents.  The address of\n.I etext\nis the first address above the program text,\n.I edata\nabove the initialized data region, and\n.I end\nabove the uninitialized data region.\n.PP\nWhen execution begins, the program break coincides with\n.I end,\nbut it is reset by the routines\n.IR brk (2),\n.IR malloc (3), \nstandard input/output\n.RI ( stdio (3S)),\nthe profile\n.RB ( \\-p )\noption of \n.IR cc (1),\netc.\nThe current value of the program break is reliably returned by `sbrk(0)',\nsee\n.IR brk (2).\n.SH \"SEE ALSO\"\nbrk(2), malloc(3)\n"
  },
  {
    "path": "share/man/man3/erf.3",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)erf.3m\t6.2 (Berkeley) 5/12/86\n.\\\"\n.TH ERF 3M  \"May 12, 1986\"\n.UC 6\n.SH NAME\nerf, erfc \\- error functions\n.SH SYNOPSIS\n.nf\n.B #include <math.h>\n.PP\n.B double erf(x)\n.B double x;\n.PP\n.B double erfc(x)\n.B double x;\n.fi\n.SH DESCRIPTION\nErf\\|(x) returns the error function of x; where\n.if n \\{\\\n.PP\nerf(x) = 2/sqrt(pi)\\(**\\|integral from 0 to x of exp(\\-t\\(**t) dt. \\}\n.if t \\{\\\nerf\\|(x) := \n(2/\\(sr\\(*p)\\|\\(is\\d\\s8\\z0\\s10\\u\\u\\s8x\\s10\\d\\|exp(\\-t\\u\\s82\\s10\\d)\\|dt. \\}\n.PP\nErfc\\|(x) returns 1.0\\-erf\\|(x).\n.PP\nThe entry for erfc is provided because of the extreme loss\nof relative accuracy if erf\\|(x) is called for large x\nand the result subtracted from 1.\n(e.g. for x = 10, 12 places are lost).\n.SH SEE ALSO\nmath(3M)\n"
  },
  {
    "path": "share/man/man3/err.3",
    "content": ".\\\" Copyright (c) 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"\t@(#)err.3\t8.1.1 (2.11BSD GTE) 2/3/95\n.\\\"\n.TH ERR 3 \"February 3, 1995\"\n.UC 4\n.SH NAME\nerr,\nverr ,\nerrx ,\nverrx ,\nwarn ,\nvwarn ,\nwarnx ,\nvwarnx \\- formatted error messages\n.SH SYNOPSIS\n.nf\n.ft B\nvoid\nerr(eval, fmt, ...)\n    int eval;\n    char *fmt;\n.PP\nvoid\nverr(eval, fmt, args)\n    int eval;\n    char *fmt;\n    va_list args;\n.PP\nvoid\nerrx(eval, fmt, ...)\n    int eval;\n    char *fmt;\n.PP\nvoid\nverrx(eval, fmt, args)\n    int eval\n    char *fmt;\n    va_list args;\n.PP\nvoid\nwarn(fmt, ...)\n    char *fmt;\n.PP\nvoid\nvwarn(fmt, args)\n    char *fmt;\n    va_list args;\n.PP\nvoid\nwarnx(fmt, ...)\n    char *fmt;\n.PP\nvoid\nvwarnx(fmt, args)\n    char *fmt;\n    va_list args;\n.ft R\n.fi\n.SH DESCRIPTION\nThe\n.B err\nand\n.B warn\nfamily of functions display a formatted error message on the standard\nerror output.\nIn all cases, the last component of the program name, a colon character,\nand a space are output.\nIf the\n.I fmt\nargument is not NULL, the formatted error message, a colon character,\nand a space are output.\nIn the case of the\n.BR err ,\n.BR verr ,\n.BR warn ,\nand\n.BR vwarn\nfunctions, the error message string affiliated with the current value of\nthe global variable\n.I errno \nis output.\nIn all cases, the output is followed by a newline character.\n.PP\nThe\n.BR err ,\n.BR verr ,\n.BR errx ,\nand\n.BR verrx\nfunctions do not return, but exit with the value of the argument\n.IR eval .\n.SH EXAMPLES\nDisplay the current errno information string and exit:\n.sp\n.in +1.0i\n.nf\nif ((p = malloc(size)) == NULL)\n\terr(1, NULL);\nif ((fd = open(file_name, O_RDONLY, 0)) == -1)\n\terr(1, \"%s\", file_name);\n.in -1.0i\n.fi\n.PP\nDisplay an error message and exit:\n.sp\n.in +1.0i\n.nf\nif (tm.tm_hour < START_TIME)\n\terrx(1, \"too early, wait until %s\", start_time_string);\n.in -1.0i\n.fi\n.PP\nWarn of an error:\n.sp\n.in +1.0i\n.nf\nif ((fd = open(raw_device, O_RDONLY, 0)) == -1)\n\twarnx(\"%s: %s: trying the block device\",\n\t    raw_device, strerror(errno));\nif ((fd = open(block_device, O_RDONLY, 0)) == -1)\n\terr(1, \"%s\", block_device);\n.in -1.0i\n.fi\n.SH SEE ALSO\nstrerror(3)\n.SH HISTORY\nThe\n.B err\nand\n.B warn\nfunctions first appeared in 4.4BSD.\n"
  },
  {
    "path": "share/man/man3/execl.3",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)execl.3\t6.2 (Berkeley) 8/4/87\n.\\\"\n.TH EXECL 3 \"August 4, 1987\"\n.UC 5\n.SH NAME\nexecl, execv, execle, execlp, execvp, exec, execve, exect, environ \\- execute a file\n.SH SYNOPSIS\n.nf\n.B execl(name, arg0, arg1, ..., argn, 0)\n.B char *name, *arg0, *arg1, ..., *argn;\n.PP\n.B execv(name, argv)\n.B char *name, *argv[];\n.PP\n.B \"execle(name, arg0, arg1, ..., argn, 0, envp)\"\n.B \"char *name, *arg0, *arg1, ..., *argn, *envp[];\"\n.PP\n.B \"exect(name, argv, envp)\n.B \"char *name, *argv[], *envp[];\n.PP\n.B extern char **environ;\n.fi\n.SH DESCRIPTION\nThese routines provide various interfaces to the\n.I execve \nsystem call.  Refer to \n.IR  execve (2)\nfor a description of their properties; only\nbrief descriptions are provided here.\n.PP\n.I Exec\nin all its forms\noverlays the calling process with the named file, then\ntransfers to the\nentry point of the core image of the file.\nThere can be no return from a successful exec; the calling\ncore image is lost.\n.PP\nThe\n.I name\nargument\nis a pointer to the name of the file\nto be executed.\nThe pointers\n.IR arg [ 0 ],\n.IR arg [ 1 \"] ...\"\naddress null-terminated strings.\nConventionally\n.IR arg [ 0 ]\nis the name of the\nfile.\n.PP\nTwo interfaces are available.\n.I execl\nis useful when a known file with known arguments is\nbeing called;\nthe arguments to\n.I execl\nare the character strings\nconstituting the file and the arguments;\nthe first argument is conventionally\nthe same as the file name (or its last component).\nA 0 argument must end the argument list.\n.PP\nThe\n.I execv\nversion is useful when the number of arguments is unknown\nin advance;\nthe arguments to\n.I execv\nare the name of the file to be\nexecuted and a vector of strings containing\nthe arguments.\nThe last argument string must be followed\nby a 0 pointer.\n.PP\nThe\n.I exect\nversion is used when the executed file is to be\nmanipulated with \n.IR ptrace (2).\nThe program is forced to single step a single\ninstruction giving the parent an opportunity to\nmanipulate its state.  On the VAX-11 this is done\nby setting the trace bit in the process status\nlongword.\n.I Exect\nis not available on the PDP-11.\n.PP\nWhen a C program is executed,\nit is called as follows:\n.PP\n.nf\n\tmain(argc, argv, envp)\n\tint argc;\n\tchar **argv, **envp;\n.fi\n.PP\nwhere\n.I argc\nis the argument count\nand\n.I argv \nis an array of character pointers\nto the arguments themselves.\nAs indicated,\n.I argc\nis conventionally at least one\nand the first member of the array points to a\nstring containing the name of the file.\n.PP\n.I Argv\nis directly usable in another\n.I execv\nbecause\n.IR argv [ argc ]\nis 0.\n.PP\n.I Envp\nis a pointer to an array of strings that constitute\nthe\n.I environment\nof the process.\nEach string consists of a name, an \\*(lq=\\*(rq, and a null-terminated value.\nThe array of pointers is terminated by a null pointer.\nThe shell\n.IR sh (1)\npasses an environment entry for each global shell variable\ndefined when the program is called.\nSee\n.IR environ (7)\nfor some conventionally\nused names.\nThe C run-time start-off routine places a copy of\n.I envp\nin the global cell\n.IR environ ,\nwhich is used\nby\n.I execv\nand\n.I execl\nto pass the environment to any subprograms executed by the\ncurrent program.\n.PP\n.I Execlp\nand\n.I execvp\nare called with the same arguments as\n.I execl\nand\n.IR execv ,\nbut duplicate the shell's actions in searching for an executable\nfile in a list of directories.\nThe directory list is obtained from the environment.\n.SH FILES\n.ta \\w'/bin/sh  'u\n/bin/sh\tshell, invoked if command file found\nby\n.I execlp\nor\n.I execvp\n.SH \"SEE ALSO\"\nexecve(2),\nfork(2),\nenviron(7),\ncsh(1)\n.SH DIAGNOSTICS\nIf the file cannot be found,\nif it is not executable,\nif it does not start with a valid magic number (see\n.IR a.out (5)),\nif maximum memory is exceeded,\nor if the arguments require too much space,\na return\nconstitutes the diagnostic;\nthe return value is \\-1.\nEven for the super-user,\nat least one of the execute-permission bits must be set for\na file to be executed.\n.SH BUGS\nIf\n.I execvp\nis called to execute a file that turns out to be a shell\ncommand file,\nand if it is impossible to execute the shell,\nthe values of\n.I argv[0]\nand\n.I argv[\\-1]\nwill be modified before return.\n"
  },
  {
    "path": "share/man/man3/exit.3",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)exit.3\t6.2 (Berkeley) 5/12/86\n.\\\"\n.TH EXIT 3 \"May 12, 1986\"\n.UC 5\n.SH NAME\nexit \\- terminate a process after flushing any pending output\n.SH SYNOPSIS\n.nf\n.ft B\nexit(status)\nint status;\n.fi\n.SH DESCRIPTION\n.I Exit\nterminates a process after calling the Standard I/O library\nfunction\n.I _cleanup\nto flush any buffered output.\n.I Exit\nnever returns.\n.SH \"SEE ALSO\"\nexit(2), intro(3)\n"
  },
  {
    "path": "share/man/man3/exp.3",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)exp.3m\t6.9 (Berkeley) 5/27/86\n.\\\"\n.TH EXP 3M  \"May 27, 1986\"\n.UC 4\n.ds nn \\fINaN\\fR\n.ds up \\fIulp\\fR\n.SH NAME\nexp, expm1, log, log10, log1p, pow \\- exponential, logarithm, power\n.SH SYNOPSIS\n.nf\n.B #include <math.h>\n.PP\n.B double exp(x)\n.B double x;\n.PP\n.B double expm1(x)\n.B double x;\n.PP\n.B double log(x)\n.B double x;\n.PP\n.B double log10(x)\n.B double x;\n.PP\n.B double log1p(x)\n.B double x;\n.PP\n.B double pow(x,y)\n.B double x,y;\n.fi\n.SH DESCRIPTION\n.PP\nExp returns the exponential function of x.\n.PP\nExpm1 returns exp(x)\\-1 accurately even for tiny x.\n.PP\nLog returns the natural logarithm of x.\n.PP\nLog10 returns the logarithm of x to base 10.\n.PP\nLog1p returns log(1+x) accurately even for tiny x.\n.PP\nPow(x,y) returns\n.if n \\\nx**y.\n.if t \\\nx\\u\\s8y\\s10\\d.\n.SH ERROR (due to Roundoff etc.)\nexp(x), log(x), expm1(x) and log1p(x) are accurate to within \nan \\*(up, and log10(x) to within about 2 \\*(ups;\nan \\*(up is one \\fIU\\fRnit in the \\fIL\\fRast \\fIP\\fRlace.\nThe error in pow(x,y) is below about 2 \\*(ups when its\nmagnitude is moderate, but increases as pow(x,y) approaches\nthe over/underflow thresholds until almost as many bits could be\nlost as are occupied by the floating\\-point format's exponent\nfield; that is 8 bits for VAX D and 11 bits for IEEE 754 Double.\nNo such drastic loss has been exposed by testing; the worst\nerrors observed have been below 20 \\*(ups for VAX D,\n300 \\*(ups for IEEE 754 Double.\nModerate values of pow are accurate enough that pow(integer,integer)\nis exact until it is bigger than 2**56 on a VAX, 2**53 for IEEE 754.\n.SH DIAGNOSTICS\nExp, expm1 and pow return the reserved operand on a VAX when the correct\nvalue would overflow, and they set \\fIerrno\\fR to ERANGE.\nPow(x,y) returns the reserved operand on a VAX and sets \\fIerrno\\fR\nto EDOM when x < 0 and y is not an integer.\n.PP\nOn a VAX, \\fIerrno\\fR is set to EDOM and the reserved operand is returned\nby log unless x > 0, by log1p unless x > \\-1.\n.SH NOTES\nThe functions exp(x)\\-1 and log(1+x) are called expm1\nand logp1 in BASIC on the Hewlett\\-Packard HP\\-71B and APPLE\nMacintosh, EXP1 and LN1 in Pascal, exp1 and log1 in C\non APPLE Macintoshes, where they have been provided to make\nsure financial calculations of ((1+x)**n\\-1)/x, namely\nexpm1(n\\(**log1p(x))/x, will be accurate when x is tiny.\nThey also provide accurate inverse hyperbolic functions.\n.PP\nPow(x,0) returns x**0 = 1 for all x including x = 0,\n.if n \\\nInfinity\n.if t \\\n\\(if\n(not found on a VAX), and \\*(nn (the reserved\noperand on a VAX).  Previous implementations of pow may\nhave defined x**0 to be undefined in some or all of these\ncases.  Here are reasons for returning x**0 = 1 always:\n.IP (1) \\w'\\0\\0\\0\\0'u\nAny program that already tests whether x is zero (or\ninfinite or \\*(nn) before computing x**0 cannot care\nwhether 0**0 = 1 or not. Any program that depends\nupon 0**0 to be invalid is dubious anyway since that\nexpression's meaning and, if invalid, its consequences \nvary from one computer system to another.\n.IP (2) \\w'\\0\\0\\0\\0'u\nSome Algebra texts (e.g. Sigler's) define x**0 = 1 for \nall x, including x = 0.\nThis is compatible with the convention that accepts a[0]\nas the value of polynomial\n.ce\np(x) = a[0]\\(**x**0 + a[1]\\(**x**1 + a[2]\\(**x**2 +...+ a[n]\\(**x**n\n.IP\nat x = 0 rather than reject a[0]\\(**0**0 as invalid.\n.IP (3) \\w'\\0\\0\\0\\0'u\nAnalysts will accept 0**0 = 1 despite that x**y can\napproach anything or nothing as x and y approach 0\nindependently.\nThe reason for setting 0**0 = 1 anyway is this:\n.IP\nIf x(z) and y(z) are \\fIany\\fR functions analytic (expandable\nin power series) in z around z = 0, and if there \nx(0) = y(0) = 0, then x(z)**y(z) \\(-> 1 as z \\(-> 0.\n.IP (4) \\w'\\0\\0\\0\\0'u\nIf 0**0 = 1, then\n.if n \\\ninfinity**0 = 1/0**0 = 1 too; and\n.if t \\\n\\(if**0 = 1/0**0 = 1 too; and\nthen \\*(nn**0 = 1 too because x**0 = 1 for all finite\nand infinite x, i.e., independently of x.\n.SH SEE ALSO\nmath(3M), infnan(3M)\n.SH AUTHOR\nKwok\\-Choi Ng, W. Kahan\n"
  },
  {
    "path": "share/man/man3/fclose.3",
    "content": ".\\\"\t@(#)fclose.3s\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH FCLOSE 3S  \"May 15, 1985\"\n.AT 3\n.SH NAME\nfclose, fflush \\- close or flush a stream\n.SH SYNOPSIS\n.B #include <stdio.h>\n.PP\n.B fclose(stream)\n.br\n.SM\n.B FILE\n.B *stream;\n.PP\n.B fflush(stream)\n.br\n.SM\n.B FILE\n.B *stream;\n.SH DESCRIPTION\n.I Fclose\ncauses any buffers for the named\n.I stream\nto be emptied, and the file to be closed.\nBuffers allocated by the standard input/output system\nare freed.\n.PP\n.I Fclose\nis performed automatically upon\ncalling\n.IR  exit (3).\n.PP\n.I Fflush\ncauses any buffered data for the named output\n.I stream\nto be written to that file.\nThe stream remains open.\n.SH \"SEE ALSO\"\nclose(2),\nfopen(3S),\nsetbuf(3S)\n.SH DIAGNOSTICS\nThese routines return\n.SM\n.B EOF\nif\n.I stream\nis not associated with an output file, or\nif buffered data cannot be transferred to that file.\n"
  },
  {
    "path": "share/man/man3/ferror.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ferror.3s\t6.3 (Berkeley) 5/14/86\n.\\\"\n.TH FERROR 3S  \"May 14, 1986\"\n.UC 4\n.SH NAME\nferror, feof, clearerr, fileno \\- stream status inquiries\n.SH SYNOPSIS\n.B #include <stdio.h>\n.PP\n.B feof(stream)\n.br\n.SM\n.B FILE\n.B *stream;\n.PP\n.B ferror(stream)\n.br\n.SM\n.B FILE\n.B *stream\n.PP\n.B clearerr(stream)\n.br\n.SM\n.B FILE\n.B *stream\n.PP\n.B fileno(stream)\n.br\n.SM\n.B FILE\n.B *stream;\n.SH DESCRIPTION\n.I Feof\nreturns non-zero when end of file is read on the named input\n.IR stream ,\notherwise zero.\nUnless cleared by\n.IR clearerr ,\nthe end-of-file indication lasts until\nthe stream is closed.\n.PP\n.I Ferror\nreturns non-zero when an error has occurred reading or writing\nthe named\n.IR stream ,\notherwise zero.\nUnless cleared by\n.IR clearerr ,\nthe error indication lasts until\nthe stream is closed.\n.PP\n.I Clearerr\nresets the error and end-of-file indicators on the named\n.IR stream .\n.PP\n.I Fileno\nreturns the integer file descriptor\nassociated with the\n.IR stream ,\nsee\n.IR open (2).\n.PP\nCurrently all of these functions\nare implemented as macros;\nthey cannot be redeclared.\n.SH \"SEE ALSO\"\nfopen(3S),\nopen(2)\n"
  },
  {
    "path": "share/man/man3/floor.3",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)floor.3m\t6.4 (Berkeley) 5/12/86\n.\\\"\n.TH FLOOR 3M  \"May 12, 1986\"\n.UC 4\n.SH NAME\nfabs, floor, ceil, rint \\- absolute value, floor, ceiling, and\nround-to-nearest functions\n.SH SYNOPSIS\n.nf\n.B #include <math.h>\n.PP\n.B double floor(x)\n.B double x;\n.PP\n.B double ceil(x)\n.B double x;\n.PP\n.B double fabs(x)\n.B double x;\n.PP\n.B double rint(x)\n.B double x;\n.fi\n.SH DESCRIPTION\nFabs returns the absolute value |\\|x\\||.\n.PP\nFloor returns the largest integer no greater than x.\n.PP\nCeil returns the smallest integer no less than x.\n.PP\nRint returns the integer (represented as a double precision number)\nnearest x in the direction of the prevailing rounding mode.\n.SH NOTES\nOn a VAX, rint(x) is equivalent to adding half to the magnitude\nand then rounding towards zero.\n.PP\nIn the default rounding mode, to nearest,\non a machine that conforms to IEEE 754,\nrint(x) is the integer nearest x with the additional stipulation\nthat if |rint(x)\\-x|=1/2 then rint(x) is even.\nOther rounding modes can make rint act like floor, or like ceil,\nor round towards zero.\n.PP\nAnother way to obtain an integer near x is to declare (in C)\n.RS\ndouble x;\\0\\0\\0\\0 int k;\\0\\0\\0\\0k\\0=\\0x;\n.RE\nMost C compilers round x towards 0 to get the integer k, but\nsome do otherwise.\nIf in doubt, use floor, ceil, or rint first, whichever you intend.\nAlso note that, if x is larger than k can accommodate, the value of\nk and the presence or absence of an integer overflow are hard to\npredict.\n.SH SEE ALSO\nabs(3),\nieee(3M),\nmath(3M)\n"
  },
  {
    "path": "share/man/man3/fopen.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)fopen.3s\t6.3 (Berkeley) 5/27/86\n.\\\"\n.TH FOPEN 3S  \"May 27, 1986\"\n.UC 4\n.SH NAME\nfopen, freopen, fdopen \\- open a stream\n.SH SYNOPSIS\n.B #include <stdio.h>\n.PP\n.SM\n.B FILE\n.B *fopen(filename, type)\n.br\n.B char *filename, *type;\n.PP\n.SM\n.B FILE\n.B *freopen(filename, type, stream)\n.br\n.B char *filename, *type;\n.br\n.SM\n.B FILE\n.B *stream;\n.PP\n.SM\n.B FILE\n.B *fdopen(fildes, type)\n.br\n.B char *type;\n.SH DESCRIPTION\n.I Fopen\nopens the file named by\n.I filename\nand associates a stream with it.\n.I Fopen\nreturns a pointer to be used to identify the stream in subsequent operations.\n.PP\n.I Type\nis a character string having one of the following values:\n.TP 5\n\"r\"\nopen for reading\n.ns\n.TP 5\n\"w\"\ncreate for writing\n.ns\n.TP 5\n\"a\"\nappend: open for writing at end of file, or create for writing\n.PP\nIn addition, each\n.I type\nmay be followed by a \"+\" to have the file opened for reading and writing.\n\"r+\" positions the stream at the beginning of the file, \"w+\" creates\nor truncates it, and \"a+\" positions it at the end.  Both reads and writes\nmay be used on read/write streams, with the limitation that an\n.I fseek, rewind,\nor reading an end-of-file must be used between a read and a write or vice-versa.\n.PP\n.I Freopen\nsubstitutes the named file in place of the open\n.IR stream .\nIt returns the original value of\n.IR stream .\nThe original stream is closed.\n.PP\n.I Freopen\nis typically used to attach the preopened constant names,\n.B stdin, stdout, stderr,\nto specified files.\n.PP\n.I Fdopen\nassociates a stream with a file descriptor obtained from\n.I open, dup, creat,\nor\n.IR pipe (2).\nThe\n.I type\nof the stream must agree with the mode of the open file.\n.SH \"SEE ALSO\"\nopen(2),\nfclose(3)\n.SH DIAGNOSTICS\n.I Fopen\nand \n.I freopen\nreturn the pointer\n.SM\n.B NULL\nif\n.I filename\ncannot be accessed,\nif too many files are already open,\nor if other resources needed cannot be allocated.\n.SH BUGS\n.I Fdopen\nis not portable to systems other than UNIX.\n.PP\nThe read/write \n.I types\ndo not exist on all systems.  Those systems without\nread/write modes will probably treat the \n.I type\nas if the \"+\" was not present.  These are unreliable in any event.\n.PP\nIn order to support the same number of open files as does the system,\n.I fopen\nmust allocate additional memory for data structures using\n.I calloc\nafter 20 files have been opened.\nThis confuses some programs which use their own memory allocators.\nAn undocumented routine,\n.IR f_prealloc ,\nmay be called to force immediate allocation of all internal memory\nexcept for buffers.\n"
  },
  {
    "path": "share/man/man3/fread.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)fread.3s\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH FREAD 3S  \"May 15, 1985\"\n.UC 4\n.SH NAME\nfread, fwrite \\- buffered binary input/output\n.SH SYNOPSIS\n.B #include <stdio.h>\n.PP\n.B fread(ptr, sizeof(*ptr), nitems, stream)\n.br\n.SM\n.B FILE\n.B *stream;\n.PP\n.B fwrite(ptr, sizeof(*ptr), nitems, stream)\n.br\n.SM\n.B FILE\n.B *stream;\n.SH DESCRIPTION\n.I Fread\nreads, into a block beginning at\n.IR ptr ,\n.I nitems\nof data of the type of\n.I *ptr\nfrom the named input\n.IR stream .\nIt returns the number of items actually read.\n.PP\nIf\n.I stream\nis\n.B stdin\nand the standard output is line buffered, then any partial output line\nwill be flushed before any call to\n.IR read (2)\nto satisfy the\n.IR fread .\n.PP\n.I Fwrite\nappends at most\n.I nitems\nof data of the type of\n.I *ptr\nbeginning at\n.I ptr\nto the named output\n.IR stream .\nIt returns the number of items actually written.\n.SH \"SEE ALSO\"\nread(2),\nwrite(2),\nfopen(3S),\ngetc(3S),\nputc(3S),\ngets(3S),\nputs(3S),\nprintf(3S),\nscanf(3S)\n.SH DIAGNOSTICS\n.I Fread\nand\n.I fwrite\nreturn\n0\nupon end of file or error.\n"
  },
  {
    "path": "share/man/man3/frexp.3",
    "content": ".\\\"\t@(#)frexp.3\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH FREXP 3 \"May 15, 1985\"\n.AT 3\n.SH NAME\nfrexp, ldexp, modf \\- split into mantissa and exponent\n.SH SYNOPSIS\n.nf\n.B double frexp(value, eptr)\n.B double value;\n.B int *eptr;\n.PP\n.B double ldexp(value, exp)\n.B double value;\n.PP\n.B double modf(value, iptr)\n.B double value, *iptr;\n.SH DESCRIPTION\n.I Frexp\nreturns the mantissa of a double \n.I value\nas a double quantity,\n.I x,\nof magnitude less than 1\nand stores an integer \n.I n\nsuch that\n.I value\n=\n\\fIx\\fP\\|\\(**\\|2\\u\\fIn\\fP\\d\nindirectly through \n.I eptr.\n.PP\n.I Ldexp\nreturns the quantity\n\\fIvalue\\|\\(**\\|2\\u\\fIexp\\fP\\d.\n.PP\n.I Modf\nreturns the positive fractional part of\n.I value\nand stores the integer part indirectly\nthrough \n.I iptr.\n"
  },
  {
    "path": "share/man/man3/fseek.3",
    "content": ".\\\"\t@(#)fseek.3s\t6.3 (Berkeley) 2/24/86\n.\\\"\n.TH FSEEK 3S  \"February 24, 1986\"\n.AT 3\n.SH NAME\nfseek, ftell, rewind \\- reposition a stream\n.SH SYNOPSIS\n.B #include <stdio.h>\n.PP\n.B fseek(stream, offset, ptrname)\n.br\n.SM\n.B FILE\n.B *stream;\n.br\n.B long offset;\n.PP\n.B long ftell(stream)\n.br\n.SM\n.B FILE\n.B *stream;\n.PP\n.B rewind(stream)\n.SH DESCRIPTION\n.I Fseek\nsets the position of the next input or output\noperation on the\n.IR stream .\nThe new position is at the signed distance\n.I offset\nbytes\nfrom the beginning, the current position, or the end of the file,\naccording as \n.I ptrname\nhas the value 0, 1, or 2.\n.PP\n.I Fseek\nundoes any effects of\n.IR  ungetc (3S).\n.PP\n.I Ftell\nreturns the current value of the offset relative to the beginning\nof the file associated with the named\n.IR stream .\nIt is measured in bytes on UNIX;\non some other systems it is a magic cookie,\nand the only foolproof way to obtain an \n.I offset\nfor\n.IR fseek .\n.PP\n.IR Rewind ( stream )\nis equivalent to\n.IR fseek ( stream ,\n0L, 0).\n.SH \"SEE ALSO\"\nlseek(2),\nfopen(3S)\n.SH DIAGNOSTICS\n.I Fseek\nreturns \\-1 for improper seeks, otherwise zero.\n"
  },
  {
    "path": "share/man/man3/getc.3",
    "content": ".\\\"\t@(#)getc.3s\t6.2 (Berkeley) 5/14/86\n.\\\"\n.TH GETC 3S  \"May 14, 1986\"\n.AT 3\n.SH NAME\ngetc, getchar, fgetc, getw \\- get character or word from stream\n.SH SYNOPSIS\n.B #include <stdio.h>\n.PP\n.B int getc(stream)\n.br\n.SM\n.B FILE\n.B *stream;\n.PP\n.B int getchar()\n.PP \n.B int fgetc(stream)\n.br\n.SM\n.B FILE\n.B *stream;\n.PP\n.B int getw(stream)\n.br\n.SM\n.B FILE\n.B *stream;\n.SH DESCRIPTION\n.I Getc\nreturns the next character from the named input\n.IR stream .\n.PP\n.IR Getchar ()\nis identical to \n.IR getc ( stdin ) .\n.PP\n.I Fgetc\nbehaves like \n.IR getc ,\nbut is a genuine function, not a macro;\nit may be used to save object text.\n.PP\n.I Getw\nreturns the next\n.B int\n(a 32-bit integer on a VAX-11) from the named input\n.IR stream .\nIt returns the constant\n.SM\n.B EOF\nupon end of file or error, but since that is a good\ninteger value,\n.I feof\nand\n.IR  ferror (3S)\nshould be used to check the success of\n.IR getw .\n.I Getw\nassumes no special alignment in the file.\n.SH \"SEE ALSO\"\nclearerr(3S),\nfopen(3S),\nputc(3S),\ngets(3S),\nscanf(3S),\nfread(3S),\nungetc(3S)\n.SH DIAGNOSTICS\nThese functions return the integer constant\n.SM\n.B EOF\nat end of file, upon read error,\nor if an attempt is made to read a file not opened by\n.IR fopen .\nThe end-of-file condition is remembered,\neven on a terminal,\nand all subsequent attempts to read will return\n.B EOF\nuntil the condition is cleared with\n.IR clearerr (3S).\n.SH BUGS\nBecause it is implemented as a macro,\n.I getc\ntreats a\n.I stream\nargument with side effects incorrectly.\nIn particular,\n`getc(*f++);'\ndoesn't work sensibly.\n"
  },
  {
    "path": "share/man/man3/getdisk.3",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)getdisk.3\t6.2.1 (2.11BSD) 1995/09/08\n.\\\"\n.TH GETDISKBYNAME 3 \"September 8, 1995\"\n.UC 5\n.SH NAME\ngetdiskbyname \\- get disk description by its name\n.SH SYNOPSIS\n.nf\n.B #include <sys/types.h>\n.B #include <sys/disktab.h>\n.PP\n.B struct disklabel *\n.B getdiskbyname(name)\n.B char *name;\n.fi\n.SH DESCRIPTION\n.I Getdiskbyname\ntakes a disk name (e.g. rm03) and returns a structure\ndescribing its geometry information and the standard\ndisk partition tables.  Information obtained from\nthe \n.IR disktab (5)\nfile has the following form:\n.sp\n.cs R 24\n.nf\n.so /usr/include/sys/disklabel.h\n.fi\n.cs R\n.SH \"SEE ALSO\"\ndisktab(5), disklabel(8)\n.SH BUGS\nThis routine is primarily used when the underlying disk driver does\nnot support labels.  The other use is for supplying default information\nto the\n.IR disklabel (8)\nprogram.\n"
  },
  {
    "path": "share/man/man3/getenv.3",
    "content": ".\\\"\t@(#)getenv.3\t6.4 (Berkeley) 3/20/87\n.\\\"\n.TH GETENV 3 \"March 20, 1987\"\n.AT 3\n.SH NAME\ngetenv, setenv, unsetenv \\- manipulate environmental variables\n.SH SYNOPSIS\n.nf\n.B char *getenv(name)\n.B char *name;\n.PP\n.B setenv(name, value, overwrite)\n.B char *name, value;\n.B int overwrite;\n.PP\n.B void unsetenv(name)\n.B char *name;\n.fi\n.SH DESCRIPTION\n\\fIGetenv\\fP searches the environment list (see \\fIenviron\\fP(7))\nfor a string of the form \\fIname\\fP\\fB=\\fP\\fIvalue\\fP and returns\na pointer to the string \\fIvalue\\fP if such a string is present,\nand 0 (NULL) if it is not.\n.PP\n\\fISetenv\\fP searches the environment list as \\fIgetenv\\fP does; if\nthe string \\fIname\\fP is not found, a string of the form\n\\fIname\\fP\\fB=\\fP\\fIvalue\\fP is added to the environment.  If it is\nfound, and \\fIoverwrite\\fP is non-zero, its value is changed to\n\\fIvalue\\fP.  \\fISetenv\\fP returns 0 on success and -1 on failure,\nwhere failure is caused by an inability to allocate space for the\nenvironment.\n.PP\n\\fIUnsetenv\\fP removes all occurrences of the string \\fIname\\fP from\nthe environment.  There is no library provision for completely removing\nthe current environment.  It is suggested that the following code be\nused to do so.\n.PP\n.nf\n\tstatic char\t*envinit[1];\n\textern char\t**environ;\n\tenviron = envinit;\n.fi\n.PP\nAll of these routines permit, but do not require, a trailing equals\n(``='') sign on \\fIname\\fP or a leading equals sign on \\fIvalue\\fP.\n.SH SEE ALSO\ncsh(1), sh(1), execve(2), environ(7)\n"
  },
  {
    "path": "share/man/man3/getfsent.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)getfsent.3\t6.3 (Berkeley) 5/12/86\n.\\\"\n.TH GETFSENT 3  \"May 12, 1986\"\n.UC 4\n.SH NAME\ngetfsent, getfsspec, getfsfile, getfstype, setfsent, endfsent \\- get file system descriptor file entry\n.SH SYNOPSIS\n.nf\n.B #include <fstab.h>\n.PP\n.B struct fstab *getfsent()\n.PP\n.B struct fstab *getfsspec(spec)\n.B char *spec;\n.PP\n.B struct fstab *getfsfile(file)\n.B char *file;\n.PP\n.B struct fstab *getfstype(type)\n.B char *type;\n.PP\n.B int setfsent()\n.PP\n.B int endfsent()\n.fi\n.SH DESCRIPTION\n.IR Getfsent ,\n.IR getfsspec ,\n.IR getfstype ,\nand\n.I getfsfile\neach return a pointer to an object with the following structure\ncontaining the broken-out fields of a line in the file system description file,\n.IR < fstab.h >.\n.RS\n.PP\n.nf\nstruct fstab {\n\tchar\t*fs_spec;\n\tchar\t*fs_file;\n\tchar\t*fs_type;\n\tint\tfs_freq;\n\tint\tfs_passno;\n};\n.ft R\n.ad\n.fi\n.RE\n.PP\nThe fields have meanings described in\n.IR fstab (5).\n.PP\n.I Getfsent\nreads the next line of the file, opening the file if necessary.\n.PP\n.I Setfsent\nopens and rewinds the file.\n.PP\n.I Endfsent\ncloses the file.\n.PP\n.I Getfsspec\nand\n.I getfsfile\nsequentially search from the beginning of the file until a matching\nspecial file name or file system file name is found,\nor until EOF is encountered.\n.I Getfstype\ndoes likewise, matching on the file system type field.\n.SH FILES\n/etc/fstab\n.SH \"SEE ALSO\"\nfstab(5)\n.SH DIAGNOSTICS\nNull pointer\n(0) returned on EOF or error.\n.SH BUGS\nAll information is contained in a static area so it must be copied if it is\nto be saved.\n"
  },
  {
    "path": "share/man/man3/getgrent.3",
    "content": ".\\\"\t@(#)getgrent.3\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH GETGRENT 3  \"May 15, 1985\"\n.AT 3\n.SH NAME\ngetgrent, getgrgid, getgrnam, setgrent, endgrent \\- get group file entry\n.SH SYNOPSIS\n.nf\n.B #include <grp.h>\n.PP\n.B struct group *getgrent()\n.PP\n.B struct group *getgrgid(gid)\n.B int gid;\n.PP\n.B struct group *getgrnam(name)\n.B char *name;\n.PP\n.B setgrent()\n.PP\n.B endgrent()\n.fi\n.SH DESCRIPTION\n.I Getgrent,\n.I getgrgid\nand\n.I getgrnam\neach return pointers\nto an object\nwith the following structure\ncontaining the broken-out\nfields of a line in the group file.\n.RS\n.PP\n.nf\n.so /usr/include/grp.h\n.fi\n.RE\n.PP\nThe members of this structure are:\n.TP \\w'gr_passwd'u+2n\ngr_name\nThe name of the group.\n.br\n.ns\n.TP \\w'gr_passwd'u+2n\ngr_passwd\nThe encrypted password of the group.\n.br\n.ns\n.TP \\w'gr_passwd'u+2n\ngr_gid\nThe numerical group-ID.\n.br\n.ns\n.TP \\w'gr_passwd'u+2n\ngr_mem\nNull-terminated vector\nof pointers to the individual\nmember names.\n.PP\n.I Getgrent\nsimply reads the next\nline while\n.I getgrgid\nand\n.I getgrnam\nsearch until a matching\n.I gid\nor\n.I name\nis found\n(or until EOF is encountered).\nEach routine picks up\nwhere the others leave off\nso successive calls may be used\nto search the entire file.\n.PP\nA call to\n.I setgrent\nhas the effect of rewinding\nthe group file\nto allow\nrepeated searches.\n.I Endgrent\nmay be called to\nclose the group file\nwhen processing is complete.\n.SH FILES\n/etc/group\n.SH \"SEE ALSO\"\ngetlogin(3), getpwent(3), group(5)\n.SH DIAGNOSTICS\nA null pointer\n(0) is returned on EOF or error.\n.SH BUGS\nAll information\nis contained in a static area\nso it must be copied if it is\nto be saved.\n"
  },
  {
    "path": "share/man/man3/getgrouplist.3",
    "content": ".\\\" Copyright (c) 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)getgrouplist.3\t8.1.1 (2.11BSD) 1997/6/25\n.\\\"\n.TH GETGROUPLIST 3 \"June 25, 1997\"\n.UC 4\n.SH NAME\ngetgrouplist \\- calculate group access list\n.SH SYNOPSIS\n.nf\n.B #include <unistd.h>\n.B int\n\\fBgetgrouplist\\fP(\\fIname, basegid, groups, ngroups\\fP)\n\\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ char\\  *name;\n\\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ gid_t basegid;\n\\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ gid_t *groups;\n\\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ \\ int\\ \\ \\ *ngroups;\n.SH DESCRIPTION\nThe\n.B getgrouplist\nfunction reads through the group file and calculates\nthe group access list for the user specified in\n.IR name .\nThe\n.I basegid\nis automatically included in the groups list.\nTypically this value is given as\nthe group number from the password file.\n.PP\nThe resulting group list is returned in the integer array pointed to by\n.IR groups .\nThe caller specifies the size of the \n.IR groups\narray in the integer pointed to by\n.IR ngroups ;\nthe actual number of groups found is returned in\n.IR ngroups .\n.SH RETURN VALUES\nThe\n.B getgrouplist\nfunction\nreturns \\-1 if the size of the group list is too small to\nhold all the user's groups.\nHere, the group array will be filled with as many groups as will fit.\n.SH FILES\n.TP 12\n/etc/group\ngroup membership list\n.SH SEE ALSO\nsetgroups(2),\ninitgroups(3)\n.SH HISTORY\nThe\n.B getgrouplist\nfunction first appeared in 4.4BSD.\n.SH BUGS\nThe\n.B getgrouplist\nfunction\nuses the routines based on\ngetgrent(3).\nIf the invoking program uses any of these routines,\nthe group structure will\nbe overwritten in the call to\n.BR getgrouplist .\n"
  },
  {
    "path": "share/man/man3/gethostbyname.3",
    "content": ".\\\" Copyright (c) 1983,1987 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)gethostbyname.3\t6.9.1 (2.11BSD) 1996/10/30\n.\\\"\n.TH GETHOSTBYNAME 3 \"October 30, 1996\"\n.UC 5\n.SH NAME\ngethostbyname, gethostbyaddr, gethostent, sethostent, endhostent, herror \\- get network host entry\n.SH SYNOPSIS\n.B \"#include <netdb.h>\n.PP\n.B \"extern int h_errno;\n.PP\n.B \"struct hostent *gethostbyname(name)\n.br\n.B \"char *name;\n.PP\n.B \"struct hostent *gethostbyaddr(addr, len, type)\n.br\n.B \"char *addr; int len, type;\n.PP\n.B \"struct hostent *gethostent()\n.PP\n.B \"sethostent(stayopen)\n.br\n.B \"int stayopen;\n.PP\n.B \"endhostent()\n.PP\n.B \"herror(string)\n.br\n.B \"char *string;\n.PP\n.SH DESCRIPTION\n.I Gethostbyname\nand\n.I gethostbyaddr\neach return a pointer to an object with the\nfollowing structure describing an internet host\nreferenced by name or by address, respectively.\nThis structure contains either the information obtained from the name server,\n.IR named (8),\nor broken-out fields from a line in \n.IR /etc/hosts .\nIf the local name server is not running these routines do a lookup in\n.IR /etc/hosts .\n.RS\n.PP\n.nf\nstruct\thostent {\n\tchar\t*h_name;\t/* official name of host */\n\tchar\t**h_aliases;\t/* alias list */\n\tint\th_addrtype;\t/* host address type */\n\tint\th_length;\t/* length of address */\n\tchar\t**h_addr_list;\t/* list of addresses from name server */\n};\n#define\th_addr  h_addr_list[0]\t/* address, for backward compatibility */\n.ft R\n.ad\n.fi\n.RE\n.PP\nThe members of this structure are:\n.TP \\w'h_addr_list'u+2n\nh_name\nOfficial name of the host.\n.TP \\w'h_addr_list'u+2n\nh_aliases\nA zero terminated array of alternate names for the host.\n.TP \\w'h_addr_list'u+2n\nh_addrtype\nThe type of address being returned; currently always AF_INET.\n.TP \\w'h_addr_list'u+2n\nh_length\nThe length, in bytes, of the address.\n.TP \\w'h_addr_list'u+2n\nh_addr_list\nA zero terminated array of network addresses for the host.\nHost addresses are returned in network byte order.\n.TP \\w'h_addr_list'u+2n\nh_addr\nThe first address in h_addr_list; this is for backward compatiblity.\n.PP\nWhen using the nameserver,\n.I gethostbyname\nwill search for the named host in the current domain and its parents\nunless the name ends in a dot.\nIf the name contains no dot, and if the environment variable ``HOSTALIASES''\ncontains the name of an alias file, the alias file will first be searched\nfor an alias matching the input name.\nSee\n.IR hostname (7)\nfor the domain search procedure and the alias file format.\n.PP\n.I Sethostent\nmay be used to request the use of a connected TCP socket for queries.\nIf the\n.I stayopen\nflag is non-zero,\nthis sets the option to send all queries to the name server using TCP\nand to retain the connection after each call to \n.I gethostbyname\nor\n.IR gethostbyaddr .\nOtherwise, queries are performed using UDP datagrams.\n.PP\n.I Endhostent\ncloses the TCP connection.\n.SH DIAGNOSTICS\n.PP\nError return status from \n.I gethostbyname\nand\n.I gethostbyaddr\nis indicated by return of a null pointer.\nThe external integer\n.IR h_errno\nmay then be checked to see whether this is a temporary failure\nor an invalid or unknown host.\nThe routine\n.I herror\ncan be used to print an error message describing the failure.\nIf its argument\n.I string\nis non-NULL, it is printed, followed by a colon and a space.\nThe error message is printed with a trailing newline.\n.PP\n.IR h_errno\ncan have the following values:\n.RS\n.IP HOST_NOT_FOUND \\w'HOST_NOT_FOUND'u+2n\nNo such host is known.\n.IP TRY_AGAIN \\w'HOST_NOT_FOUND'u+2n\nThis is usually a temporary error\nand means that the local server did not receive\na response from an authoritative server.\nA retry at some later time may succeed.\n.IP NO_RECOVERY \\w'HOST_NOT_FOUND'u+2n\nSome unexpected server failure was encountered.\nThis is a non-recoverable error.\n.IP NO_DATA \\w'HOST_NOT_FOUND'u+2n\nThe requested name is valid but does not have an IP address; \nthis is not a temporary error.  \nThis means that the name is known to the name server but there is no address\nassociated with this name.\nAnother type of request to the name server using this domain name\nwill result in an answer;\nfor example, a mail-forwarder may be registered for this domain.\n.RE\n.SH FILES\n/etc/hosts\n.SH \"SEE ALSO\"\nresolver(3), hosts(5), hostname(7), named(8)\n.SH CAVEAT\n.PP\n.I Gethostent\nis defined, and\n.I sethostent\nand\n.I endhostent\nare redefined,\nwhen\n.IR libc\nis built to use only the routines to lookup in\n.IR /etc/hosts \nand not the name server.\n.PP\n.I Gethostent\nreads the next line of\n.IR /etc/hosts ,\nopening the file if necessary.\n.PP\n.I Sethostent \nis redefined to open and rewind the file.  If the\n.I stayopen\nargument is non-zero,\nthe hosts data base will not be closed after each call to\n.I gethostbyname\nor\n.IR gethostbyaddr .\n.I Endhostent\nis redefined to close the file.\n.SH BUGS\nAll information\nis contained in a static area\nso it must be copied if it is\nto be saved.  Only the Internet\naddress format is currently understood.\n"
  },
  {
    "path": "share/man/man3/getloadavg.3",
    "content": ".\\\" Copyright (c) 1989, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)getloadavg.3\t8.1.1 (2.11BSD GTE) 1/15/95\n.\\\"\n.TH GETLOADAVG 3 \"January 15, 1995\"\n.UC 4\n.SH NAME\ngetloadavg \\- get system load averages\n.SH SYNOPSIS\n.nf\n.B getloadavg(loadavg, nelem)\n       double loadavg[];\n       int    nelem;\n.fi\n.SH DESCRIPTION\nThe\n\\fIgetloadavg\\fP\nfunction returns the number of processes in the system run queue\naveraged over various periods of time.\nUp to\n\\fInelem\\fP\nsamples are retrieved and assigned to successive elements of\n\\fIloadavg\\fP.\nThe system imposes a maximum of 3 samples, representing averages\nover the last 1, 5, and 15 minutes, respectively.\n.SH DIAGNOSTICS\nIf the load average was unobtainable, \\-1 is returned; otherwise,\nthe number of samples actually retrieved is returned.\n.SH SEE ALSO\nuptime(1), sysctl(3), sysctl(8).\n.SH HISTORY\nThe\n.B getloadavg\nfunction appeared in \\fB4.3BSD-Reno\\fP.\n.PP\nThis function replaces the 2.9BSD compatibility routine getla().\n"
  },
  {
    "path": "share/man/man3/getmntinfo.3",
    "content": ".\\\" Copyright (c) 1989, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)getmntinfo.3\t8.1.1 (2.11BSD) 1995/12/26\n.\\\"\n.TH GETMNTINFO 3 \"December 26, 1995\"\n.UC 7\n.SH NAME\n\\fBgetmntinfo\\fP \\- get information about mounted file systems\n.SH SYNOPSIS\n.B #include <sys/param.h>\n.br\n.B #include <sys/mount.h>\n.sp\n.I int\n.br\n\\fBgetmntinfo\\fP(mntbufp,flags)\n.br\n.I struct statfs **mntbufp;\n.br\n.I int flags\n.br\n.SH DESCRIPTION\nThe\n.BR getmntinfo ()\nfunction\nreturns an array of\n.I statfs\nstructures describing each currently mounted file system (see\n.BR statfs (2).\n.PP\nThe\n.BR getmntinfo ()\nfunction\npasses its\n.I flags\nparameter transparently to\n.BR getfsstat (2).\n.SH RETURN VALUES\nOn successful completion,\n.BR getmntinfo ()\nreturns a count of the number of elements in the array.\nThe pointer to the array is stored into\n.IR mntbufp .\n.PP\nIf an error occurs, zero is returned and the external variable\n.I errno\nis set to indicate the error.\nAlthough the pointer \n.I mntbufp\nwill be unmodified, any information previously returned by \n.BR getmntinfo ()\nwill be lost.\n.SH ERRORS\nThe\n.BR getmntinfo ()\nfunction\nmay fail and set errno for any of the errors specified for the library \nroutines\n.BR getfsstat (2)\nor \n.BR malloc (3).\n.SH SEE ALSO\ngetfsstat(2),\nstatfs(2),\nmount(2),\nmount(8)\n.SH HISTORY\nThe\n.BR getmntinfo ()\nfunction first appeared in 4.4BSD.\n.SH BUGS\nThe\n.BR getmntinfo ()\nfunction writes the array of structures to an internal static object\nand returns\na pointer to that object. Subsequent calls to\n.BR getmntinfo ()\nwill modify the same object.\n.PP\nThe memory allocated by\n.BR getmntinfo ()\ncannot be\n.BR free (2)'d\nby the application.\n"
  },
  {
    "path": "share/man/man3/getnetent.3",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)getnetent.3n\t6.3 (Berkeley) 5/19/86\n.\\\"\n.TH GETNETENT 3N \"May 19, 1986\"\n.UC 5\n.SH NAME\ngetnetent, getnetbyaddr, getnetbyname, setnetent, endnetent \\- get network entry\n.SH SYNOPSIS\n.nf\n.ft B\n#include <netdb.h>\n.PP\n.ft B\nstruct netent *getnetent()\n.PP\n.ft B\nstruct netent *getnetbyname(name)\nchar *name;\n.PP\n.ft B\nstruct netent *getnetbyaddr(net, type)\nlong net;\nint type;\n.PP\n.ft B\nsetnetent(stayopen)\nint stayopen;\n.PP\n.ft B\nendnetent()\n.fi\n.SH DESCRIPTION\n.IR Getnetent ,\n.IR getnetbyname ,\nand\n.I getnetbyaddr\neach return a pointer to an object with the\nfollowing structure\ncontaining the broken-out\nfields of a line in the network data base,\n.IR /etc/networks .\n.RS\n.PP\n.nf\nstruct\tnetent {\n\tchar\t\t*n_name;\t/* official name of net */\n\tchar\t\t**n_aliases;\t/* alias list */\n\tint\t\tn_addrtype;\t/* net number type */\n\tunsigned long\tn_net;\t\t/* net number */\n};\n.ft R\n.ad\n.fi\n.RE\n.PP\nThe members of this structure are:\n.TP \\w'n_addrtype'u+2n\nn_name\nThe official name of the network.\n.TP \\w'n_addrtype'u+2n\nn_aliases\nA zero terminated list of alternate names for the network.\n.TP \\w'n_addrtype'u+2n\nn_addrtype\nThe type of the network number returned; currently only AF_INET.\n.TP \\w'n_addrtype'u+2n\nn_net\nThe network number.  Network numbers are returned in machine byte\norder.\n.PP\n.I Getnetent\nreads the next line of the file, opening the file if necessary.\n.PP\n.I Setnetent\nopens and rewinds the file.  If the\n.I stayopen\nflag is non-zero,\nthe net data base will not be closed after each call to \n.I getnetbyname\nor\n.IR getnetbyaddr .\n.PP\n.I Endnetent\ncloses the file.\n.PP\n.I Getnetbyname\nand\n.I getnetbyaddr\nsequentially search from the beginning\nof the file until a matching\nnet name or\nnet address and type is found,\nor until EOF is encountered.\nNetwork numbers are supplied in host order.\n.SH FILES\n/etc/networks\n.SH \"SEE ALSO\"\nnetworks(5)\n.SH DIAGNOSTICS\nNull pointer\n(0) returned on EOF or error.\n.SH BUGS\nAll information\nis contained in a static area\nso it must be copied if it is\nto be saved.  Only Internet network\nnumbers are currently understood.\nExpecting network numbers to fit\nin no more than 32 bits is probably\nnaive.\n"
  },
  {
    "path": "share/man/man3/getopt.3",
    "content": ".\\\" Copyright (c) 1988, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)getopt.3\t8.4.1 (2.11BSD) 1996/1/12\n.\\\"\n.TH GETOPT 3 \"January 12, 1996\"\n.UC 6\n.SH NAME\n\\fBgetopt\\fP \\- get option character from command line argument list\n.SH SYNOPSIS\n.B #include <stdlib.h>\n.sp\n.B extern char *optarg;\n.br\n.B extern int   optind;\n.br\n.B extern int   optopt;\n.br\n.B extern int   opterr;\n.br\n.B extern int   optreset;\n.sp\n.I int\n.br\n\\fBgetopt\\fP(argc, argv, optstring)\n.br\n.I int argc;\n.br\n.I char **argv;\n.br\n.I char *optstring;\n.SH DESCRIPTION\nThe\n.BR getopt ()\nfunction incrementally parses a command line argument list\n.I argv\nand returns the next\n.I known\noption character.\nAn option character is\n.I known\nif it has been specified in the string of accepted option characters,\n.IR optstring .\n.PP\nThe option string\n.I optstring\nmay contain the following elements: individual characters, and\ncharacters followed by a colon to indicate an option argument\nis to follow.\nFor example, an option string\n\"\\&\"\"x\"\"\nrecognizes an option\n``\\-\\fBx\\fP'',\nand an option string\n\"\\&\"\"x:\"\"\nrecognizes an option and argument\n``\\fB\\-x\\fP \\fIargument\\fP''.\nIt does not matter to\n.BR getopt ()\nif a following argument has leading white space.\n.PP\nOn return from\n.BR getopt (),\n.I optarg\npoints to an option argument, if it is anticipated,\nand the variable\n.I optind\ncontains the index to the next\n.I argv\nargument for a subsequent call\nto\n.BR getopt ().\nThe variable\n.I optopt\nsaves the last\n.I known\noption character returned by\n.BR getopt ().\n.PP\nThe variable\n.I opterr\nand\n.I optind\nare both initialized to 1.\nThe\n.I optind\nvariable may be set to another value before a set of calls to\n.BR getopt ()\nin order to skip over more or less argv entries.\n.PP\nIn order to use\n.BR getopt ()\nto evaluate multiple sets of arguments, or to evaluate a single set of\narguments multiple times,\nthe variable\n.I optreset\nmust be set to 1 before the second and each additional set of calls to\n.BR getopt (),\nand the variable\n.I optind\nmust be reinitialized.\n.PP\nThe\n.BR getopt ()\nfunction\nreturns an\n.B EOF\nwhen the argument list is exhausted, or a non-recognized\noption is encountered.\nThe interpretation of options in the argument list may be cancelled\nby the option `\\-\\-'\n(double dash) which causes\n.BR getopt ()\nto signal the end of argument processing and return an\n.BR EOF . \nWhen all options have been processed (i.e., up to the first non-option\nargument),\n.BR getopt ()\nreturns\n.BR EOF .\n.SH DIAGNOSTICS\nIf the\n.BR getopt ()\nfunction encounters a character not found in the string\n.I optarg\nor detects\na missing option argument it writes an error message and returns `?'\nto the\n.IR stderr .\nSetting\n.I opterr\nto a zero will disable these error messages.\nIf\n.I optstring \nhas a leading \n`\\&:'\nthen a missing option argument causes a\n`\\&:'\nto be returned in addition to suppressing any error messages.\n.PP\nOption arguments are allowed to begin with\n`\\-';\nthis is reasonable but\nreduces the amount of error checking possible.\n.SH EXTENSIONS\nThe\n.I optreset\nvariable was added to make it possible to call the\n.BR getopt ()\nfunction multiple times.\nThis is an extension to the\nIEEE Std1003.2 (``POSIX'')\nspecification.\n.SH EXAMPLE\n.nf\n.cs R 24\nextern char *optarg;\nextern int optind;\nint bflag, ch, fd;\n\nbflag = 0;\nwhile ((ch = getopt(argc, argv, \"bf:\")) != EOF)\n\tswitch(ch) {\n\tcase 'b':\n\t\tbflag = 1;\n\t\tbreak;\n\tcase 'f':\n\t\tif ((fd = open(optarg, O_RDONLY, 0)) < 0) {\n\t\t\t(void)fprintf(stderr,\n\t\t\t    \"myname: %s: %s\\en\", optarg, strerror(errno));\n\t\t\texit(1);\n\t\t}\n\t\tbreak;\n\tcase '?':\n\tdefault:\n\t\tusage();\n}\nargc -= optind;\nargv += optind;\n.br\n.cs R\n.fi\n.SH HISTORY\nThe\n.BR getopt ()\nfunction appeared 4.3BSD.\n.SH BUGS\nA single dash ``\\-''\nmay be specified as an character in\n.I optstring ,\nhowever it should\n.B never\nhave an argument associated with it.\nThis allows\n.BR getopt ()\nto be used with programs that expect\n``\\-''\nas an option flag.\nThis practice is wrong, and should not be used in any current development.\nIt is provided for backward compatibility\n.B only .\nBy default, a single dash causes\n.BR getopt ()\nto return\n.BR EOF .\nThis is, we believe, compatible with System V.\n.PP\nIt is also possible to handle digits as option letters.\nThis allows\n.BR getopt ()\nto be used with programs that expect a number\n(``-3'')\nas an option.\nThis practice is wrong, and should not be used in any current development.\nIt is provided for backward compatibility\n.BR only .\nThe following code fragment works in most cases.\n.sp\n.nf\n.cs R 24\nint length;\nchar *p;\n\nwhile ((c = getopt(argc, argv, \"0123456789\")) != EOF)\n\tswitch (c) {\n\tcase '0': case '1': case '2': case '3': case '4':\n\tcase '5': case '6': case '7': case '8': case '9':\n\t\tp = argv[optind - 1];\n\t\tif (p[0] == '-' && p[1] == ch && !p[2])\n\t\t\tlength = atoi(++p);\n\t\telse\n\t\t\tlength = atoi(argv[optind] + 1);\n\t\tbreak;\n\t}\n}\n.cs R\n"
  },
  {
    "path": "share/man/man3/getpass.3",
    "content": ".\\\"\t@(#)getpass.3\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH GETPASS 3  \"May 15, 1985\"\n.AT 3\n.SH NAME\ngetpass \\- read a password\n.SH SYNOPSIS\n.nf\n.B char *getpass(prompt)\n.B char *prompt;\n.fi\n.SH DESCRIPTION\n.I Getpass\nreads a password from the file\n.IR /dev/tty ,\nor if that cannot be opened, from the standard input,\nafter prompting with the null-terminated string\n.I prompt\nand disabling echoing.\nA pointer is returned to a null-terminated string\nof at most 8 characters.\n.SH FILES\n/dev/tty\n.SH \"SEE ALSO\"\ncrypt(3)\n.SH BUGS\nThe return value points to static data\nwhose content is overwritten by each call.\n"
  },
  {
    "path": "share/man/man3/getprotoent.3",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)getprotoent.3n\t6.3 (Berkeley) 5/19/86\n.\\\"\n.TH GETPROTOENT 3N \"May 19, 1986\"\n.UC 5\n.SH NAME\ngetprotoent, getprotobynumber, getprotobyname, setprotoent, endprotoent \\- get protocol entry\n.SH SYNOPSIS\n.nf\n.ft B\n.B #include <netdb.h>\n.PP\n.ft B\nstruct protoent *getprotoent()\n.PP\n.ft B\nstruct protoent *getprotobyname(name)\nchar *name;\n.PP\n.ft B\nstruct protoent *getprotobynumber(proto)\nint proto;\n.PP\n.ft B\nsetprotoent(stayopen)\nint stayopen\n.PP\n.ft B\nendprotoent()\n.fi\n.SH DESCRIPTION\n.IR Getprotoent ,\n.IR getprotobyname ,\nand\n.I getprotobynumber\neach return a pointer to an object with the\nfollowing structure\ncontaining the broken-out\nfields of a line in the network protocol data base,\n.IR /etc/protocols .\n.RS\n.PP\n.nf\nstruct\tprotoent {\n\tchar\t*p_name;\t/* official name of protocol */\n\tchar\t**p_aliases;\t/* alias list */\n\tint\tp_proto;\t/* protocol number */\n};\n.ft R\n.ad\n.fi\n.RE\n.PP\nThe members of this structure are:\n.TP \\w'p_aliases'u+2n\np_name\nThe official name of the protocol.\n.TP \\w'p_aliases'u+2n\np_aliases\nA zero terminated list of alternate names for the protocol.\n.TP \\w'p_aliases'u+2n\np_proto\nThe protocol number.\n.PP\n.I Getprotoent\nreads the next line of the file, opening the file if necessary.\n.PP\n.I Setprotoent\nopens and rewinds the file.  If the\n.I stayopen\nflag is non-zero,\nthe net data base will not be closed after each call to \n.I getprotobyname\nor\n.IR getprotobynumber .\n.PP\n.I Endprotoent\ncloses the file.\n.PP\n.I Getprotobyname\nand\n.I getprotobynumber\nsequentially search from the beginning\nof the file until a matching\nprotocol name or\nprotocol number is found,\nor until EOF is encountered.\n.SH FILES\n/etc/protocols\n.SH \"SEE ALSO\"\nprotocols(5)\n.SH DIAGNOSTICS\nNull pointer\n(0) returned on EOF or error.\n.SH BUGS\nAll information\nis contained in a static area\nso it must be copied if it is\nto be saved.  Only the Internet\nprotocols are currently understood.\n"
  },
  {
    "path": "share/man/man3/getpwent.3",
    "content": ".\\\" Copyright (c) 1988 The Regents of the University of California.\n.\\\" All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms are permitted\n.\\\" provided that the above copyright notice and this paragraph are\n.\\\" duplicated in all such forms and that any documentation,\n.\\\" advertising materials, and other materials related to such\n.\\\" distribution and use acknowledge that the software was developed\n.\\\" by the University of California, Berkeley.  The name of the\n.\\\" University may not be used to endorse or promote products derived\n.\\\" from this software without specific prior written permission.\n.\\\" THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n.\\\" IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n.\\\" WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n.\\\"\n.\\\"\t@(#)getpwent.3\t6.5 (Berkeley) 2/23/89\n.\\\"\n.TH GETPWENT 3  \"February 23, 1989\"\n.AT 3\n.SH NAME\ngetpwent, getpwnam, getpwuid, setpassent,\nsetpwfile, setpwent, endpwent \\- get password file entries\n.SH SYNOPSIS\n.nf\n.B #include <sys/types.h>\n.B #include <pwd.h>\n.PP\n.B struct passwd *getpwent()\n.PP\n.B struct passwd *getpwnam(login)\n.B char *login;\n.PP\n.B struct passwd *getpwuid(uid)\n.B uid_t uid;\n.PP\n.B int setpassent(stayopen)\n.B int stayopen;\n.PP\n.B void setpwfile(file)\n.B char *file;\n.PP\n.B int setpwent()\n.PP\n.B void endpwent()\n.fi\n.SH DESCRIPTION\n.IR Getpwent ,\n.IR getpwuid ,\nand\n.I getpwnam\neach return a pointer to a structure containing the broken-out\nfields of a line in the password file.  This structure is defined\nby the include file\n.IR < pwd.h > ,\nand contains the following fields:\n.PP\n.RS\n.nf\nstruct passwd {\n\tchar\t*pw_name;\t\t\t/* user name */\n\tchar\t*pw_passwd;\t\t/* encrypted password */\n\tuid_t\tpw_uid;\t\t/* user uid */\n\tgid_t\tpw_gid;\t\t/* user gid */\n\ttime_t\tpw_change;\t/* password change time */\n\tchar\t*pw_class;\t\t/* user access class */\n\tchar\t*pw_gecos;\t\t/* Honeywell login info */\n\tchar\t*pw_dir;\t\t\t/* home directory */\n\tchar\t*pw_shell;\t\t/* default shell */\n\ttime_t\tpw_expire;\t/* account expiration */\n};\n.fi\n.RE\n.PP\nThese fields are more completely described in\n.IR passwd (5).\n.PP\n.I Getpwnam\nand\n.I getpwuid\nsearch the password database for a matching user name or user uid,\nrespectively, returning the first one encountered.  Identical\nuser names or user uids may result in undefined behavior.\n.PP\n.I Getpwent\nsequentially reads the password database and is intended for programs\nthat wish to step through the complete list of users.\n.PP\nAll three routines will open the password file for reading, if\nnecessary.\n.PP\n.I Setpwfile\nchanges the default password file to\n.IR file ,\nthus allowing the use of alternate password files.\n.PP\n.I Setpassent\nopens the file or rewinds it if it is already open.  If\n.I stayopen\nis non-zero, file descriptors are left open, significantly speeding\nup subsequent calls.  This functionality is unnecessary for\n.I getpwent\nas it doesn't close its file descriptors by default.  It should also\nbe noted that it is dangerous for long-running programs to use this\nfunctionality as the password file may be updated by\n.IR chpass (1),\n.IR passwd (1),\nor\n.IR vipw (8).\n.PP\n.I Setpwent\nis identical to\n.I setpassent\nwith an argument of zero.\n.PP\n.I Endpwent\ncloses any open files.\n.PP\nThese routines have been written to ``shadow'' the password file, e.g.\nallow only certain programs to have access to the encrypted password.\nThis is done by using the\n.IR mkpasswd (8)\nprogram, which creates\n.IR ndbm (3)\ndatabases that correspond to the password file, with the single exception\nthat, rather than storing the encrypted password in the database, it stores\nthe offset in the password file where the encrypted password may be found.\n.IR Getpwent ,\n.IR getpwnam ,\nand\n.I getpwuid\nwill use the\n.I ndbm\nfiles in preference to the ``real'' password files, only reading the\npassword file itself, to obtain the encrypted password, if the process\nis running with an effective user id equivalent to super-user.\nIf the password file itself is protected, and the\n.I ndbm\nfiles are not, this makes the password available only to programs\nrunning with super-user privileges.\n.SH FILES\n/etc/passwd\n.SH \"SEE ALSO\"\ngetlogin(3), getgrent(3), ndbm(3), passwd(5)\n.SH DIAGNOSTICS\nThe routines\n.IR getpwent ,\n.IR getpwnam ,\nand\n.IR getpwuid ,\nreturn a null pointer on EOF or error.\n.I Setpassent\nand\n.I setpwent\nreturn 0 on failure and 1 on success.\n.I Endpwent\nand\n.I setpwfile\nhave no return value.\n.SH BUGS\nAll information is contained in a static buffer which is overwritten\nby each new call.  It must be copied elsewhere to be retained.\n.PP\nIntermixing calls to\n.IR getpwent\nwith calls to\n.I getpwnam\nor\n.IR getpwuid ,\nor intermixing calls to\n.I getpwnam\nand\n.IR getpwuid ,\nafter using\n.I setpassent\nto require that file descriptors be left open, may result\nin undefined behavior.\n.PP\nThe routines\n.IR getpwent ,\n.IR endpwent ,\n.IR setpassent ,\nand\n.IR setpwent\nare fairly useless in a networked environment and should be\navoided, if possible.\n"
  },
  {
    "path": "share/man/man3/gets.3",
    "content": ".\\\"\t@(#)gets.3s\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH GETS 3S  \"May 15, 1985\"\n.AT 3\n.SH NAME\ngets, fgets \\- get a string from a stream\n.SH SYNOPSIS\n.B #include <stdio.h>\n.PP\n.B char *gets(s)\n.br\n.B char *s;\n.PP\n.B char *fgets(s, n, stream)\n.br\n.B char *s;\n.br\n.SM\n.B FILE\n.B *stream;\n.SH DESCRIPTION\n.I Gets\nreads a string into\n.I s\nfrom the standard input stream\n.BR stdin .\nThe string is terminated by a newline\ncharacter, which is replaced in\n.I s\nby a null character.\n.I Gets\nreturns its argument.\n.PP\n.I Fgets\nreads \n.IR n \\-1\ncharacters, or up through a newline\ncharacter, whichever comes first,\nfrom the\n.I stream\ninto the string\n.IR s .\nThe last character read into\n.I s\nis followed by a null character.\n.I Fgets\nreturns its first argument.\n.SH \"SEE ALSO\"\nputs(3S),\ngetc(3S),\nscanf(3S),\nfread(3S),\nferror(3S)\n.SH DIAGNOSTICS\n.I Gets\nand\n.I fgets\nreturn the constant pointer \n.SM\n.B NULL\nupon end of file or error.\n.SH BUGS\n.I Gets\ndeletes a newline,\n.I fgets\nkeeps it,\nall in the name of backward compatibility.\n"
  },
  {
    "path": "share/man/man3/getservent.3",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)getservent.3n\t6.3 (Berkeley) 5/19/86\n.\\\"\n.TH GETSERVENT 3N \"May 19, 1986\"\n.UC 5\n.SH NAME\ngetservent, getservbyport, getservbyname, setservent, endservent \\- get service entry\n.SH SYNOPSIS\n.nf\n.ft B\n#include <netdb.h>\n.PP\n.ft B\nstruct servent *getservent()\n.PP\n.ft B\nstruct servent *getservbyname(name, proto)\nchar *name, *proto;\n.PP\n.ft B\nstruct servent *getservbyport(port, proto)\nint port; char *proto;\n.PP\n.ft B\nsetservent(stayopen)\nint stayopen\n.PP\n.ft B\nendservent()\n.fi\n.SH DESCRIPTION\n.IR Getservent ,\n.IR getservbyname ,\nand\n.I getservbyport\neach return a pointer to an object with the\nfollowing structure\ncontaining the broken-out\nfields of a line in the network services data base,\n.IR /etc/services .\n.RS\n.PP\n.nf\nstruct\tservent {\n\tchar\t*s_name;\t/* official name of service */\n\tchar\t**s_aliases;\t/* alias list */\n\tint\ts_port;\t\t/* port service resides at */\n\tchar\t*s_proto;\t/* protocol to use */\n};\n.ft R\n.ad\n.fi\n.RE\n.PP\nThe members of this structure are:\n.TP \\w's_aliases'u+2n\ns_name\nThe official name of the service.\n.TP \\w's_aliases'u+2n\ns_aliases\nA zero terminated list of alternate names for the service.\n.TP \\w's_aliases'u+2n\ns_port\nThe port number at which the service resides.\nPort numbers are returned in network byte order.\n.TP \\w's_aliases'u+2n\ns_proto\nThe name of the protocol to use when contacting the\nservice.\n.PP\n.I Getservent\nreads the next line of the file, opening the file if necessary.\n.PP\n.I Setservent\nopens and rewinds the file.  If the\n.I stayopen\nflag is non-zero,\nthe net data base will not be closed after each call to \n.I getservbyname\nor .IR getservbyport .\n.PP\n.I Endservent\ncloses the file.\n.PP\n.I Getservbyname\nand\n.I getservbyport\nsequentially search from the beginning\nof the file until a matching\nprotocol name or\nport number is found,\nor until EOF is encountered.\nIf a protocol name is also supplied (non-NULL),\nsearches must also match the protocol.\n.SH FILES\n/etc/services\n.SH \"SEE ALSO\"\ngetprotoent(3N), services(5)\n.SH DIAGNOSTICS\nNull pointer\n(0) returned on EOF or error.\n.SH BUGS\nAll information\nis contained in a static area\nso it must be copied if it is\nto be saved.  Expecting port\nnumbers to fit in a 32 bit\nquantity is probably naive.\n"
  },
  {
    "path": "share/man/man3/getsubopt.3",
    "content": ".\\\" Copyright (c) 1990, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)getsubopt.3\t8.1.1 (2.11BSD) 1996/1/12\n.\\\"\n.TH GETSUBOPT 3 \"January 12, 1996\"\n.UC 7\n.SH NAME\ngetsubopt \\- get sub options from an argument\n.SH SYNOPSIS\n.ft B\n#include <stdlib.h>\n.sp\nextern char *suboptarg\n.sp\nint\n.br\ngetsubopt(optionp, tokens, valuep)\n.br\nchar **optionp;\n.br\nchar **tokens;\n.br\nchar **valuep;\n.br\n.ft\n.SH DESCRIPTION\nThe\n.BR getsubopt ()\nfunction\nparses a string containing tokens delimited by one or more tab, space or\ncomma\n(`,')\ncharacters.\nIt is intended for use in parsing groups of option arguments provided\nas part of a utility command line.\n.PP\nThe argument\n.I optionp\nis a pointer to a pointer to the string.\nThe argument\n.I tokens\nis a pointer to a\n\\fBNULL\\fP-terminated\narray of pointers to strings.\n.PP\nThe\n.BR getsubopt ()\nfunction\nreturns the zero-based offset of the pointer in the\n.I tokens\narray referencing a string which matches the first token\nin the string, or, \\-1 if the string contains no tokens or\n.I tokens\ndoes not contain a matching string.\n.PP\nIf the token is of the form ``name=value'', the location referenced by\n.I valuep\nwill be set to point to the start of the ``value'' portion of the token.\n.PP\nOn return from\n.BR getsubopt (),\n.I optionp\nwill be set to point to the start of the next token in the string,\nor the null at the end of the string if no more tokens are present.\nThe external variable\n.I suboptarg\nwill be set to point to the start of the current token, or\n.B NULL\nif no\ntokens were present.\nThe argument\n.I valuep\nwill be set to point to the ``value'' portion of the token, or\n.B NULL\nif no ``value'' portion was present.\n.SH EXAMPLE\n.nf\n.cs R 24\nchar *tokens[] = {\n\t#define\tONE\t0\n\t\t\"one\",\n\t#define\tTWO\t1\n\t\t\"two\",\n\tNULL\n};\n\n\\&...\n\nextern char *optarg, *suboptarg;\nchar *options, *value;\n\nwhile ((ch = getopt(argc, argv, \"ab:\")) != \\-1) {\n\tswitch(ch) {\n\tcase 'a':\n\t\t/* process ``a'' option */\n\t\tbreak;\n\tcase 'b':\n\t\toptions = optarg;\n\t\twhile (*options) {\n\t\t\tswitch(getsubopt(&options, tokens, &value)) {\n\t\t\tcase ONE:\n\t\t\t\t/* process ``one'' sub option */\n\t\t\t\tbreak;\n\t\t\tcase TWO:\n\t\t\t\t/* process ``two'' sub option */\n\t\t\t\tif (!value)\n\t\t\t\t\terror(\"no value for two\");\n\t\t\t\ti = atoi(value);\n\t\t\t\tbreak;\n\t\t\tcase \\-1:\n\t\t\t\tif (suboptarg)\n\t\t\t\t\terror(\"illegal sub option %s\",\n\t\t\t\t\t  suboptarg);\n\t\t\t\telse\n\t\t\t\t\terror(\"missing sub option\");\n\t\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\t}\n.br\n.cs R\n.fi\n.SH SEE ALSO\ngetopt(3), strsep(3)\n.SH HISTORY\nThe\n.BR getsubopt ()\nfunction first appeared in 4.4BSD.\n"
  },
  {
    "path": "share/man/man3/getttyent.3",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)getttyent.3\t6.4 (Berkeley) 5/20/86\n.\\\"\n.TH GETTTYENT 3  \"May 20, 1986\"\n.UC 6\n.SH NAME\ngetttyent, getttynam, setttyent, endttyent \\- get ttys file entry\n.SH SYNOPSIS\n.nf\n.B #include <ttyent.h>\n.PP\n.B struct ttyent *getttyent()\n.PP\n.B struct ttyent *getttynam(name)\n.B char *name;\n.PP\n.B setttyent()\n.PP\n.B endttyent()\n.fi\n.SH DESCRIPTION\n.I Getttyent,\nand\n.I getttynam\neach return a pointer to an object with the\nfollowing structure\ncontaining the broken-out\nfields of a line from the tty description file.\n.RS\n.PP\n.nf\n.so /usr/include/ttyent.h\n.ft R\n.ad\n.fi\n.RE\n.PP\n.IP ty_name \\w'ty_comment'u+3\nis the name of the character-special file in the directory ``/dev\".\nFor various reasons, it must reside in the directory ``/dev\".\n.IP ty_getty\nis the command (usually\n.IR getty (8))\nwhich is invoked by\n.I init\nto initialize tty line characteristics.\nIn fact, any arbitrary command can be used;\na typical use is to initiate a terminal emulator in a window system.\n.IP ty_type\nis the name of the default terminal type connected to this tty line. This\nis typically a name from the\n.IR termcap (5)\ndata base.\nThe environment variable `TERM' is initialized with this name by\n.IR getty (8)\nor\n.IR login (1).\n.IP ty_status\nis a mask of bit fields which indicate various actions to be allowed on this\ntty line. The following is a description of each flag.\n.RS\n.IP TTY_ON \\w'TTY_SECURE'u+3\nEnables logins (i.e.,\n.IR init (8)\nwill start the specified ``getty\" command\non this entry).\n.IP TTY_SECURE\nAllows root to login on this terminal. Note that `TTY_ON' must be included\nfor this to be useful.\n.RE\n.IP ty_window\nis the command to execute for a window system\nassociated with the line.  The window system will be started before\nthe command specified in the\n.I ty_getty\nentry is executed.\nIf none is specified, this will be null.\n.IP ty_comment\nis the trailing comment field, if any; a leading delimiter and white space\nwill be removed.\n.PP\n.I Getttyent\nreads the next\nline from the ttys file, opening the file if necessary;\n.I setttyent\nrewinds the file;\n.I endttyent\ncloses it.\n.PP\n.I Getttynam\nsearches from the beginning of the file until a matching\n.I name\nis found\n(or until EOF is encountered).\n.SH FILES\n/etc/ttys\n.SH \"SEE ALSO\"\nlogin(1), ttyslot(3), ttys(5), gettytab(5), termcap(5), getty(8), init(8)\n.SH DIAGNOSTICS\nNull pointer\n(0) returned on EOF or error.\n.SH BUGS\nAll information\nis contained in a static area\nso it must be copied if it is\nto be saved.\n"
  },
  {
    "path": "share/man/man3/getusershell.3",
    "content": ".\\\" Copyright (c) 1985 The Regents of the University of California.\n.\\\" All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms are permitted\n.\\\" provided that the above copyright notice and this paragraph are\n.\\\" duplicated in all such forms and that any documentation,\n.\\\" advertising materials, and other materials related to such\n.\\\" distribution and use acknowledge that the software was developed\n.\\\" by the University of California, Berkeley.  The name of the\n.\\\" University may not be used to endorse or promote products derived\n.\\\" from this software without specific prior written permission.\n.\\\" THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n.\\\" IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n.\\\" WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n.\\\"\n.\\\"\t@(#)getusershell.3\t6.3 (Berkeley) 11/30/88\n.\\\"\n.TH GETUSERSHELL 3  \"November 30, 1988\"\n.UC 6\n.SH NAME\ngetusershell, setusershell, endusershell \\- get legal user shells\n.SH SYNOPSIS\n.nf\n.B char *getusershell()\n.PP\n.B setusershell()\n.PP\n.B endusershell()\n.fi\n.SH DESCRIPTION\n.I Getusershell\nreturns a pointer to a legal user shell as defined by the\nsystem manager in the file \n.IR /etc/shells .\nIf \n.I /etc/shells\nis unreadable or does not exist,\n.I getusershell\nbehaves as if\n.I /bin/sh\nand\n.I /bin/csh\nwere listed in the file.\n.PP\n.I Getusershell\nreads the next\nline (opening the file if necessary);\n.I setusershell\nrewinds the file;\n.I endusershell\ncloses it.\n.SH FILES\n/etc/shells\n.SH \"SEE ALSO\"\nshells(5)\n.SH DIAGNOSTICS\nThe routine\n.I getusershell\nreturns a null pointer (0) on EOF.\n.SH BUGS\nAll information\nis contained in a static area\nso it must be copied if it is\nto be saved.\n"
  },
  {
    "path": "share/man/man3/getwd.3",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)getwd.3\t6.2 (Berkeley) 5/12/86\n.\\\"\n.TH GETWD 3 \"May 12, 1986\"\n.UC 5\n.SH NAME\ngetwd \\- get current working directory pathname\n.SH SYNOPSIS\n.nf\n.B char *getwd(pathname)\n.B char *pathname;\n.fi\n.SH DESCRIPTION\n.I Getwd\ncopies the absolute pathname of the current working directory to\n.I pathname\nand returns a pointer to the result.\n.SH LIMITATIONS\nMaximum pathname length is MAXPATHLEN characters (1024),\nas defined in\n.I <sys/param.h>.\n.SH DIAGNOSTICS\n.I Getwd\nreturns zero and places a message in\n.I pathname\nif an error occurs.\n"
  },
  {
    "path": "share/man/man3/hypot.3",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)hypot.3m\t6.5 (Berkeley) 5/12/86\n.\\\"\n.TH HYPOT 3M  \"May 12, 1986\"\n.UC 4\n.ds up \\fIulp\\fR\n.ds nn \\fINaN\\fR\n.SH NAME\nhypot, cabs \\- Euclidean distance, complex absolute value\n.SH SYNOPSIS\n.nf\n.B #include <math.h>\n.PP\n.B double hypot(x,y)\n.B double x,y;\n.PP\n.B double cabs(z)\n.B struct {double x,y;} z;\n.fi\n.SH DESCRIPTION\nHypot(x,y) and cabs(x,y) return sqrt(x\\(**x+y\\(**y)\ncomputed in such a way that underflow will not happen, and overflow\noccurs only if the final result deserves it.\n.PP\n.if n \\\nhypot(infinity,v) = hypot(v,infinity) = +infinity for all v, \n.if t \\\nhypot(\\(if,v) = hypot(v,\\(if) = +\\(if for all v, \nincluding \\*(nn.\n.SH ERROR (due to Roundoff, etc.)\nBelow 0.97 \\*(ups.  Consequently hypot(5.0,12.0)\\0=\\013.0 exactly;\nin general, hypot and cabs return an integer whenever an\ninteger might be expected.\n.PP\nThe same cannot be said for the shorter and faster version of hypot\nand cabs that is provided in the comments in cabs.c; its error can\nexceed 1.2 \\*(ups.\n.SH NOTES\nAs might be expected, hypot(v,\\*(nn) and hypot(\\*(nn,v) are \\*(nn for all\n\\fIfinite\\fR v; with \"reserved operand\" in place of \"\\*(nn\", the\nsame is true on a VAX.  But programmers on machines other than a VAX\n(it has no\n.if n \\\ninfinity)\n.if t \\\n\\(if)\nmight be surprised at first to discover that\n.if n \\\nhypot(\\(+-infinity,\\*(nn) = +infinity.\n.if t \\\nhypot(\\(+-\\(if,\\*(nn) = +\\(if.\nThis is intentional; it happens because\n.if n \\\nhypot(infinity,v) = +infinity\n.if t \\\nhypot(\\(if,v) = +\\(if\nfor \\fIall\\fR v, finite or infinite.\nHence\n.if n \\\nhypot(infinity,v)\n.if t \\\nhypot(\\(if,v)\nis independent of v.\nUnlike the reserved operand on a VAX, the IEEE \\*(nn is designed to\ndisappear when it turns out to be irrelevant, as it does in\n.if n \\\nhypot(infinity,\\*(nn).\n.if t \\\nhypot(\\(if,\\*(nn).\n.SH SEE ALSO\nmath(3M), sqrt(3M)\n.SH AUTHOR\nW. Kahan\n"
  },
  {
    "path": "share/man/man3/ieee.3",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ieee.3m\t6.2 (Berkeley) 5/12/86\n.\\\"\n.TH IEEE 3M  \"May 12, 1986\"\n.UC 6\n.ds nn \\fINaN\\fR\n.SH NAME\ncopysign, drem, finite, logb, scalb \\- copysign, remainder,\nexponent manipulations\n.SH SYNOPSIS\n.nf\n.B #include <math.h>\n.PP\n.B double copysign(x,y)\n.B double x,y;\n.PP\n.B double drem(x,y)\n.B double x,y;\n.PP\n.B int finite(x)\n.B double x;\n.PP\n.B double logb(x)\n.B double x;\n.PP\n.B double scalb(x,n)\n.B double x;\n.B int n;\n.fi\n.SH DESCRIPTION\nThese functions are required for, or recommended by the IEEE standard\n754 for floating\\-point arithmetic.\n.PP\nCopysign(x,y)\nreturns x with its sign changed to y's.\n.PP\nDrem(x,y) returns the remainder r := x \\- n\\(**y\nwhere n is the integer nearest the exact value of x/y;\nmoreover if |n\\|\\-\\|x/y|\\|=\\|1/2 then n is even.  Consequently\nthe remainder is computed exactly and |r| \\(<= |y|/2.  But\ndrem(x,0) is exceptional; see below under DIAGNOSTICS.\n.PP\n.nf\n.ta \\w'Finite(x)'u+1n +\\w'= 0 otherwise'u+1n\n.if n \\\nFinite(x)\t= 1 just when \\-infinity < x < +infinity,\n.if t \\\nFinite(x)\t= 1 just when \\-\\(if < x < +\\(if,\n.if n \\\n\t= 0 otherwise\t(when |x| = infinity or x is \\*(nn or\n.if t \\\n\t= 0 otherwise\t(when |x| = \\(if or x is \\*(nn or\n\t\t\\0x is the VAX's reserved operand.)\n.ta\n.fi\n.PP\nLogb(x) returns x's exponent n,\na signed integer converted to double\\-precision floating\\-point and so\nchosen that 1\\0\\(<=\\0|x|/2**n\\0<\\02 unless x = 0 or\n(only on machines that conform to IEEE 754)\n.if n \\\n|x| = infinity\n.if t \\\n|x| = \\(if\nor x lies between 0 and the Underflow Threshold; see below under \"BUGS\".\n.PP\nScalb(x,n) = x\\(**(2**n) computed, for integer n, without first computing\n2**n.\n.SH DIAGNOSTICS\nIEEE 754 defines drem(x,0) and\n.if n \\\ndrem(infinity,y)\n.if t \\\ndrem(\\(if,y)\nto be invalid operations that produce a \\*(nn.\nOn a VAX, drem(x,0) returns the reserved operand.  No\n.if n \\\ninfinity\n.if t \\\n\\(if\nexists on a VAX.\n.PP\nIEEE 754 defines\n.if n \\\nlogb(\\(+-infinity) = +infinity and logb(0) = \\-infinity,\n.if t \\\nlogb(\\(+-\\(if) = +\\(if and logb(0) = \\-\\(if, and\nrequires the latter to signal Division\\-by\\-Zero.\nBut on a VAX, logb(0) = 1.0 \\- 2.0**31 = \\-2,147,483,647.0.\nAnd if the correct value of scalb(x,n) would overflow on a VAX,\nit returns the reserved operand and sets \\fIerrno\\fR to ERANGE.\n.SH SEE ALSO\nfloor(3M), math(3M), infnan(3M)\n.SH AUTHOR\nKwok\\-Choi Ng\n.SH BUGS\nShould drem(x,0) and logb(0) on a VAX signal invalidity \nby setting \\fIerrno\\fR = EDOM?  Should  logb(0) return  \\-1.7e38?\n.PP\nIEEE 754 currently specifies that\nlogb(denormalized no.) = logb(tiniest normalized no. > 0)\nbut the consensus has changed to the specification in the new \nproposed IEEE standard p854, namely that logb(x) satisfy \n.RS\n1 \\(<= scalb(|x|,\\-logb(x)) < Radix\\0\\0\\0... = 2 for IEEE 754\n.RE\nfor every x except 0, \n.if n \\\ninfinity\n.if t \\\n\\(if\nand \\*(nn.\nAlmost every program that assumes 754's specification will work\ncorrectly if logb follows 854's specification instead.\n.PP\nIEEE 754 requires copysign(x,\\*(nn) = \\(+-x  but says nothing\nelse about the sign of a \\*(nn.  A \\*(nn (\\fIN\\fRot \\fIa\\fR \\fIN\\fRumber) is\nsimilar in spirit to the VAX's reserved operand, but very\ndifferent in important details.  Since the sign bit of a\nreserved operand makes it look negative,  \n.RS\ncopysign(x,reserved operand) = \\-x;\n.RE\nshould this return the reserved operand instead?\n"
  },
  {
    "path": "share/man/man3/inet.3",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)inet.3n\t6.4 (Berkeley) 5/27/86\n.\\\"\n.TH INET 3N \"May 27, 1986\"\n.UC 5\n.SH NAME\ninet_addr, inet_network, inet_ntoa, inet_makeaddr, inet_lnaof, inet_netof \\- Internet address manipulation routines\n.SH SYNOPSIS\n.nf\n.B \"#include <sys/socket.h>\n.B \"#include <netinet/in.h>\n.B \"#include <arpa/inet.h>\n.PP\n.B \"unsigned long inet_addr(cp)\n.B \"char *cp;\n.PP\n.B \"unsigned long inet_network(cp)\n.B \"char *cp;\n.PP\n.B \"char *inet_ntoa(in)\n.B \"struct in_addr in;\n.PP\n.B \"struct in_addr inet_makeaddr(net, lna)\n.B \"long net, lna;\"\n.PP\n.B \"long inet_lnaof(in)\n.B \"struct in_addr in;\n.PP\n.B \"long inet_netof(in)\n.B \"struct in_addr in;\n.fi\n.SH DESCRIPTION\nThe routines\n.I inet_addr\nand\n.I inet_network\neach interpret character strings representing\nnumbers expressed in the Internet standard \\*(lq.\\*(rq\nnotation, returning numbers suitable for use\nas Internet addresses and Internet network\nnumbers, respectively.  The routine\n.I inet_ntoa\ntakes an Internet address and returns an ASCII\nstring representing the address in \\*(lq.\\*(rq\nnotation.  The routine\n.I inet_makeaddr\ntakes an Internet network number and a local\nnetwork address and constructs an Internet address\nfrom it.  The routines\n.I inet_netof\nand\n.I inet_lnaof\nbreak apart Internet host addresses, returning\nthe network number and local network address part,\nrespectively.\n.PP\nAll Internet address are returned in network\norder (bytes ordered from left to right).\nAll network numbers and local address parts are\nreturned as machine format integer values.\n.SH \"INTERNET ADDRESSES\"\nValues specified using the \\*(lq.\\*(rq notation take one\nof the following forms:\n.RS\n.nf\na.b.c.d\na.b.c\na.b\na\n.RE\n.fi\nWhen four parts are specified, each is interpreted\nas a byte of data and assigned, from left to right,\nto the four bytes of an Internet address.  Note\nthat when an Internet address is viewed as a 32-bit\ninteger quantity on the VAX the bytes referred to\nabove appear as \\*(lqd.c.b.a\\*(rq.  That is, VAX bytes are\nordered from right to left.\n.PP\nWhen a three part address is specified, the last\npart is interpreted as a 16-bit quantity and placed\nin the right most two bytes of the network address.\nThis makes the three part address format convenient\nfor specifying Class B network addresses as\n\\*(lq128.net.host\\*(rq.\n.PP\nWhen a two part address is supplied, the last part\nis interpreted as a 24-bit quantity and placed in\nthe right most three bytes of the network address.\nThis makes the two part address format convenient\nfor specifying Class A network addresses as\n\\*(lqnet.host\\*(rq.\n.PP\nWhen only one part is given, the value is stored\ndirectly in the network address without any byte\nrearrangement.\n.PP\nAll numbers supplied as \\*(lqparts\\*(rq in a \\*(lq.\\*(rq notation\nmay be decimal, octal, or hexadecimal, as specified\nin the C language (i.e., a leading 0x or 0X implies\nhexadecimal; otherwise, a leading 0 implies octal;\notherwise, the number is interpreted as decimal).\n.SH \"SEE ALSO\"\ngethostbyname(3N), getnetent(3N), hosts(5), networks(5),\n.SH DIAGNOSTICS\nThe value \\-1 is returned by\n.I inet_addr\nand\n.I inet_network\nfor malformed requests.\n.SH BUGS\nThe problem of host byte ordering versus network byte ordering is\nconfusing.  A simple way to specify Class C network addresses in a manner\nsimilar to that for Class B and Class A is needed.\nThe string returned by\n.I inet_ntoa\nresides in a static memory area.\n.br\nInet_addr should return a struct in_addr.\n"
  },
  {
    "path": "share/man/man3/infnan.3",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)infnan.3m\t6.4 (Berkeley) 5/27/86\n.\\\"\n.TH INFNAN 3M  \"May 27, 1986\"\n.UC 6\n.ds nn \\fINaN\\fR\n.SH NAME\ninfnan \\- signals invalid floating-point operations on a VAX (temporary)\n.SH SYNOPSIS\n.nf\n.B #include <math.h>\n.PP\n.B double infnan(iarg)\n.B int iarg;\n.SH DESCRIPTION\nAt some time in the future, some of the useful properties of\nthe Infinities and \\*(nns in the IEEE standard 754 for Binary\nFloating\\-Point Arithmetic will be simulated in UNIX on the\nDEC VAX by using its Reserved Operands.  Meanwhile, the\nInvalid, Overflow and Divide\\-by\\-Zero exceptions of the\nIEEE standard are being approximated on a VAX by calls to a\nprocedure \\fIinfnan\\fR in appropriate places in \\fIlibm\\fR.  When\nbetter exception\\-handling is implemented in UNIX, only\n\\fIinfnan\\fR among the codes in \\fIlibm\\fR will have to be changed.\nAnd users of \\fIlibm\\fR can design their own \\fIinfnan\\fR now to\ninsulate themselves from future changes.\n.PP\nWhenever an elementary function code in \\fIlibm\\fR has to\nsimulate one of the aforementioned IEEE exceptions, it calls\ninfnan(iarg) with an appropriate value of \\fIiarg\\fR.  Then a\nreserved operand fault stops computation.  But \\fIinfnan\\fR could\nbe replaced by a function with the same name that returns\nsome plausible value, assigns an apt value to the global\nvariable \\fIerrno\\fR, and allows computation to resume.\nAlternatively, the Reserved Operand Fault Handler could be\nchanged to respond by returning that plausible value, etc.\ninstead of aborting.\n.PP\nIn the table below, the first two columns show various\nexceptions signaled by the IEEE standard, and the default\nresult it prescribes.  The third column shows what value is\ngiven to \\fIiarg\\fR by functions in \\fIlibm\\fR when they\ninvoke infnan(iarg) under analogous circumstances on a VAX.\nCurrently \\fIinfnan\\fR stops computation under all those\ncircumstances.  The last two columns offer an alternative;\nthey suggest a setting for \\fIerrno\\fR and a value for a\nrevised \\fIinfnan\\fR to return.  And a C program to\nimplement that suggestion follows. \n.sp 0.5\n.RS\n.nf\n.ta \\w'Div\\-by\\-0'u+2n +\\w'+Infinity'u+1n +\\w'+ERANGE'u+1n +\\w'ERANGE or EDOM'u+4n +\\w'+HUGE'u+1n\nIEEE\tIEEE\nSignal\tDefault\t\\fIiarg\\fR\t\\fIerrno\\fR\t\\fIinfnan\\fR\n.if t \\{\\\n.sp -0.5\n.ta \\w'Div\\-by\\-0'u+2n+\\w'+Infinity'u+1n+\\w'+ERANGE'u+1n+\\w'ERANGE or EDOM'u+4n+\\w'+HUGE'u+1n\n.tc \\(ru\n\t\n.ta \\w'Div\\-by\\-0'u+2n +\\w'+Infinity'u+1n +\\w'+ERANGE'u+1n +\\w'ERANGE or EDOM'u+4n +\\w'+HUGE'u+1n\n.tc \\}\n.if n \\\n\\l'5i'\nInvalid\t\\*(nn\tEDOM\tEDOM\t0\n.if n \\{\\\nOverflow\t\\(+-Infinity\tERANGE\tERANGE\tHUGE\nDiv\\-by\\-0\t\\(+-Infinity\t\\(+-ERANGE\tERANGE or EDOM\t\\(+-HUGE \\}\n.if t \\{\\\nOverflow\t\\(+-\\(if\tERANGE\tERANGE\tHUGE\nDiv\\-by\\-0\t\\(+-\\(if\t\\(+-ERANGE\tERANGE or EDOM\t\\(+-HUGE \\}\n.sp 0.5\n\t(HUGE = 1.7e38 ... nearly  2.0**127)\n.ta\n.fi\n.RE\n.sp 0.5\n.PP\n.nf\n.ta \\w'\\fBextern int\\fR'u+1n +\\w'\\fBdefault:\\fR'u+1n +\\w'\\fB\\-ERANGE:\\fR'u+1n +\\w'\\fBerrno = ERANGE;\\fR'u+1n\nALTERNATIVE  \\fIinfnan\\fR:\\fB\n.sp 0.5\n#include\t<math.h>\n#include\t<errno.h>\nextern int\terrno ;\ndouble\tinfnan(iarg)\nint\tiarg ;\n{\n\tswitch(iarg) {\n\tcase\t\\0ERANGE:\terrno = ERANGE;\treturn(HUGE);\n\tcase\t\\-ERANGE:\terrno = EDOM;\treturn(\\-HUGE);\n\tdefault:\t\terrno = EDOM;\treturn(0);\n\t}\n}\\fR\n.ta\n.fi\n.SH SEE ALSO\nmath(3M), intro(2), signal(3).\n.PP\nERANGE and EDOM are defined in <errno.h>.  See intro(2)\nfor explanation of EDOM and ERANGE.\n"
  },
  {
    "path": "share/man/man3/initgroups.3",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)initgroups.3\t6.2 (Berkeley) 5/12/86\n.\\\"\n.TH INITGROUPS 3 \"May 12, 1986\"\n.UC 5\n.SH NAME\ninitgroups \\- initialize group access list\n.SH SYNOPSIS\n.B initgroups(name, basegid)\n.br\n.B char *name;\n.br\n.B int basegid;\n.SH DESCRIPTION\n.I Initgroups\nreads through the group file and sets up,\nusing the\n.IR setgroups (2)\ncall, the group access list for the user\nspecified in\n.IR name .\nThe\n.I basegid\nis automatically included in the groups list.\nTypically this value is given as\nthe group number from the password file.\n.SH FILES\n/etc/group\n.SH SEE ALSO\nsetgroups(2)\n.SH DIAGNOSTICS\n.I Initgroups\nreturns \\-1 if it was not invoked by the super-user.\n.SH BUGS\n.I Initgroups\nuses the routines based on\n.IR getgrent (3).\nIf the invoking program uses any of these routines,\nthe group structure will\nbe overwritten in the call to\n.IR initgroups .\n"
  },
  {
    "path": "share/man/man3/insque.3",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)insque.3\t6.2 (Berkeley) 5/20/86\n.\\\"\n.TH INSQUE 3 \"May 20, 1986\"\n.UC 5\n.SH NAME\ninsque, remque \\- insert/remove element from a queue\n.SH SYNOPSIS\n.nf\n.DT\n.ft B\nstruct qelem {\n\tstruct\tqelem *q_forw;\n\tstruct\tqelem *q_back;\n\tchar\tq_data[];\n};\n.PP\n.ft B\ninsque(elem, pred)\nstruct qelem *elem, *pred;\n.PP\n.ft B\nremque(elem)\nstruct qelem *elem;\n.ft R\n.SH DESCRIPTION\n.I Insque\nand \n.I remque\nmanipulate queues built from doubly linked lists.  Each\nelement in the queue must in the form of ``struct qelem''.\n.I Insque\ninserts \n.I elem\nin a queue immediately after \n.IR pred ;\n.I remque\nremoves an entry\n.I elem \nfrom a queue.\n.SH \"SEE ALSO\n``VAX Architecture Handbook'', pp. 228-235.\n"
  },
  {
    "path": "share/man/man3/intro.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)intro.3\t6.8 (Berkeley) 5/27/86\n.\\\"\n.TH INTRO 3 \"May 27, 1986\"\n.UC 4\n.SH NAME\nintro \\- introduction to C library functions\n.SH DESCRIPTION\nThis section describes functions that may be found\nin various libraries.\nThe library functions are those other than the\nfunctions which directly invoke UNIX system primitives, described in section 2.\nMost of these functions are accessible from the C library,\n.IR libc ,\nwhich is automatically loaded by the C compiler\n.IR cc (1),\nand the Pascal compiler\n.IR pc (1).\nThe link editor\n.IR ld (1)\nsearches this library under the `\\-lc' option.\nThe C library also includes all the functions described in section 2.\n.PP\nA subset of these functions are available from Fortran;\nthey are described separately in\n.IR intro (3F).\n.PP\nThe functions described in this section are grouped into various sections:\n.TP\n(3)\nThe straight ``3'' functions are the standard C library functions.\n.TP\n(3N)\nThese functions constitute the internet network library.\n.TP \n(3S)\nThese functions constitute the `standard I/O package', see\n.IR stdio (3S)\nfor more details.\nDeclarations for these functions may be obtained from\nthe include file\n.RI < stdio.h >.\n.TP\n(3C)\nThese routines are included for compatibility with other systems.\nIn particular,\na number of system call interfaces provided in previous releases of\n4BSD have been included for source code compatibility.\nUse of these routines should, for the most part, be avoided.\nThe manual page entry for each compatibility routine\nindicates the proper interface to use. \n.TP\n(3M)\nThese functions constitute the math library,\n.IR libm .\nWhen functions in the math library (see\n.IR math (3M))\nare passed values that are undefined or would generate\nanswers that are out of range,\nthey call the \\fIinfnan\\fP routine.\nBy default this routine returns the VAX reserved floating point value\nwhich causes the process to get a floating point exception (see\n.IR sigvec (2)).\nPrograms that wish to take other action should define their own\nversion of \\fIinfnan\\fP (see\n.IR infnan (3M)\nfor details).\nThe math library is loaded as needed by the Pascal compiler\n.IR pc (1).\nC programs that wish to use this library need to specify the ``\\-lm'' option.\n.TP\n(3X)\nThese functions constitute minor libraries and other miscellaneous\nrun-time facilities.  Most are available only when programming in C.\nThese functions include libraries that provide\ndevice independent plotting functions,\nterminal independent screen management routines\nfor two dimensional non-bitmap display terminals, \nand functions for managing data bases with inverted indexes.\nThese functions are located in separate libraries\nindicated in each manual entry.\n.SH FILES\n.nf\n/lib/libc.a\t\tthe C library\n/usr/lib/libm.a\t\tthe math library\n/usr/lib/libc_p.a\t\tthe C library compiled for profiling\n/usr/lib/libm_p.a\t\tthe math library compiled for profiling\n.fi\n.SH SEE ALSO\nstdio(3S),\nmath(3M),\nintro(2),\ncc(1),\nld(1),\nnm(1)\n.SH \"LIST OF FUNCTIONS\"\n.sp 2\n.nf\n.ta \\w'getprotobynumber'u+2n +\\w'gethostbyname.3n'u+10n\n\\fIName\\fP\t\\fIAppears on Page\\fP\t\\fIDescription\\fP\n.ta \\w'getprotobynumber'u+4n +\\w'gethostbyname.3n'u+4n\n.sp 5p\nabort\tabort.3\tgenerate a fault\nabs\tabs.3\tinteger absolute value\nacos\tsin.3m\tinverse trigonometric function\nacosh\tasinh.3m\tinverse hyperbolic function\nalarm\talarm.3c\tschedule signal after specified time\nalloca\tmalloc.3\tmemory allocator\narc\tplot.3x\tgraphics interface\nasctime\tctime.3\tconvert date and time to ASCII\nasin\tsin.3m\tinverse trigonometric function\nasinh\tasinh.3m\tinverse hyperbolic function\nassert\tassert.3x\tprogram verification\natan\tsin.3m\tinverse trigonometric function\natanh\tasinh.3m\tinverse hyperbolic function\natan2\tsin.3m\tinverse trigonometric function\natof\tatof.3\tconvert ASCII to numbers\natoi\tatof.3\tconvert ASCII to numbers\natol\tatof.3\tconvert ASCII to numbers\nbcmp\tbstring.3\tbit and byte string operations\nbcopy\tbstring.3\tbit and byte string operations\nbzero\tbstring.3\tbit and byte string operations\ncabs\thypot.3m\tcomplex absolute value\ncalloc\tmalloc.3\tmemory allocator\ncbrt\tsqrt.3m\tcube root\nceil\tfloor.3m\tinteger no less than\ncircle\tplot.3x\tgraphics interface\nclearerr\tferror.3s\tstream status inquiries\nclosedir\tdirectory.3\tdirectory operations\ncloselog\tsyslog.3\tcontrol system log\nclosepl\tplot.3x\tgraphics interface\ncont\tplot.3x\tgraphics interface\ncopysign\tieee.3m\tcopy sign bit\ncos\tsin.3m\ttrigonometric function\ncosh\tsinh.3m\thyperbolic function\ncrypt\tcrypt.3\tDES encryption\nctime\tctime.3\tconvert date and time to ASCII\ncurses\tcurses.3x\tscreen functions with ``optimal'' cursor motion\ndbminit\tdbm.3x\tdata base subroutines\ndelete\tdbm.3x\tdata base subroutines\ndrem\tieee.3m\tremainder\necvt\tecvt.3\toutput conversion\nedata\tend.3\tlast locations in program\nencrypt\tcrypt.3\tDES encryption\nend\tend.3\tlast locations in program\nendfsent\tgetfsent.3x\tget file system descriptor file entry\nendgrent\tgetgrent.3\tget group file entry\nendhostent\tgethostbyname.3n\tget network host entry\nendnetent\tgetnetent.3n\tget network entry\nendprotoent\tgetprotoent.3n\tget protocol entry\nendpwent\tgetpwent.3\tget password file entry\nendservent\tgetservent.3n\tget service entry\nenviron\texecl.3\texecute a file\nerase\tplot.3x\tgraphics interface\nerf\terf.3m\terror function\nerfc\terf.3m\tcomplementary error function\netext\tend.3\tlast locations in program\nexec\texecl.3\texecute a file\nexece\texecl.3\texecute a file\nexecl\texecl.3\texecute a file\nexecle\texecl.3\texecute a file\nexeclp\texecl.3\texecute a file\nexect\texecl.3\texecute a file\nexecv\texecl.3\texecute a file\nexecvp\texecl.3\texecute a file\nexit\texit.3\tterminate a process after flushing any pending output\nexp\texp.3m\texponential\nexpm1\texp.3m\texp(x)\\-1\nfabs\tfloor.3m\tabsolute value\nfclose\tfclose.3s\tclose or flush a stream\nfcvt\tecvt.3\toutput conversion\nfeof\tferror.3s\tstream status inquiries\nferror\tferror.3s\tstream status inquiries\nfetch\tdbm.3x\tdata base subroutines\nfflush\tfclose.3s\tclose or flush a stream\nffs\tbstring.3\tbit and byte string operations\nfgetc\tgetc.3s\tget character or word from stream\nfgets\tgets.3s\tget a string from a stream\nfileno\tferror.3s\tstream status inquiries\nfirstkey\tdbm.3x\tdata base subroutines\nfloor\tfloor.3m\tinteger no greater than\nfopen\tfopen.3s\topen a stream\nfprintf\tprintf.3s\tformatted output conversion\nfputc\tputc.3s\tput character or word on a stream\nfputs\tputs.3s\tput a string on a stream\nfread\tfread.3s\tbuffered binary input/output\nfree\tmalloc.3\tmemory allocator\nfrexp\tfrexp.3\tsplit into mantissa and exponent\nfscanf\tscanf.3s\tformatted input conversion\nfseek\tfseek.3s\treposition a stream\nftell\tfseek.3s\treposition a stream\nftime\ttime.3c\tget date and time\nfwrite\tfread.3s\tbuffered binary input/output\ngcvt\tecvt.3\toutput conversion\ngetc\tgetc.3s\tget character or word from stream\ngetchar\tgetc.3s\tget character or word from stream\ngetdiskbyname\tgetdisk.3x\tget disk description by its name\ngetenv\tgetenv.3\tvalue for environment name\ngetfsent\tgetfsent.3x\tget file system descriptor file entry\ngetfsfile\tgetfsent.3x\tget file system descriptor file entry\ngetfsspec\tgetfsent.3x\tget file system descriptor file entry\ngetfstype\tgetfsent.3x\tget file system descriptor file entry\ngetgrent\tgetgrent.3\tget group file entry\ngetgrgid\tgetgrent.3\tget group file entry\ngetgrnam\tgetgrent.3\tget group file entry\ngethostbyaddr\tgethostbyname.3n\tget network host entry\ngethostbyname\tgethostbyname.3n\tget network host entry\ngethostent\tgethostbyname.3n\tget network host entry\ngetlogin\tgetlogin.3\tget login name\ngetnetbyaddr\tgetnetent.3n\tget network entry\ngetnetbyname\tgetnetent.3n\tget network entry\ngetnetent\tgetnetent.3n\tget network entry\ngetpass\tgetpass.3\tread a password\ngetprotobyname\tgetprotoent.3n\tget protocol entry\ngetprotobynumber\tgetprotoent.3n\tget protocol entry\ngetprotoent\tgetprotoent.3n\tget protocol entry\ngetpw\tgetpw.3\tget name from uid\ngetpwent\tgetpwent.3\tget password file entry\ngetpwnam\tgetpwent.3\tget password file entry\ngetpwuid\tgetpwent.3\tget password file entry\ngets\tgets.3s\tget a string from a stream\ngetservbyname\tgetservent.3n\tget service entry\ngetservbyport\tgetservent.3n\tget service entry\ngetservent\tgetservent.3n\tget service entry\ngetw\tgetc.3s\tget character or word from stream\ngetwd\tgetwd.3\tget current working directory pathname\ngmtime\tctime.3\tconvert date and time to ASCII\ngtty\tstty.3c\tset and get terminal state (defunct)\nhtonl\tbyteorder.3n\tconvert values between host and network byte order\nhtons\tbyteorder.3n\tconvert values between host and network byte order\nhypot\thypot.3m\tEuclidean distance\nindex\tstring.3\tstring operations\ninet_addr\tinet.3n\tInternet address manipulation routines\ninet_lnaof\tinet.3n\tInternet address manipulation routines\ninet_makeaddr\tinet.3n\tInternet address manipulation routines\ninet_netof\tinet.3n\tInternet address manipulation routines\ninet_network\tinet.3n\tInternet address manipulation routines\ninfnan\tinfnan.3m\tsignals exceptions\ninitgroups\tinitgroups.3x\tinitialize group access list\ninitstate\trandom.3\tbetter random number generator\ninsque\tinsque.3\tinsert/remove element from a queue\nisalnum\tctype.3\tcharacter classification macros\nisalpha\tctype.3\tcharacter classification macros\nisascii\tctype.3\tcharacter classification macros\nisatty\tttyname.3\tfind name of a terminal\niscntrl\tctype.3\tcharacter classification macros\nisdigit\tctype.3\tcharacter classification macros\nislower\tctype.3\tcharacter classification macros\nisprint\tctype.3\tcharacter classification macros\nispunct\tctype.3\tcharacter classification macros\nisspace\tctype.3\tcharacter classification macros\nisupper\tctype.3\tcharacter classification macros\nj0\tj0.3m\tbessel function\nj1\tj0.3m\tbessel function\njn\tj0.3m\tbessel function\nlabel\tplot.3x\tgraphics interface\nldexp\tfrexp.3\tsplit into mantissa and exponent\nlgamma\tlgamma.3m\tlog gamma function; (formerly gamma.3m)\nlib2648\tlib2648.3x\tsubroutines for the HP 2648 graphics terminal\nline\tplot.3x\tgraphics interface\nlinemod\tplot.3x\tgraphics interface\nlocaltime\tctime.3\tconvert date and time to ASCII\nlog\texp.3m\tnatural logarithm\nlogb\tieee.3m\texponent extraction\nlog10\texp.3m\tlogarithm to base 10\nlog1p\texp.3m\tlog(1+x)\nlongjmp\tsetjmp.3\tnon-local goto\nmalloc\tmalloc.3\tmemory allocator\nmktemp\tmktemp.3\tmake a unique file name\nmodf\tfrexp.3\tsplit into mantissa and exponent\nmoncontrol\tmonitor.3\tprepare execution profile\nmonitor\tmonitor.3\tprepare execution profile\nmonstartup\tmonitor.3\tprepare execution profile\nmove\tplot.3x\tgraphics interface\nnextkey\tdbm.3x\tdata base subroutines\nnice\tnice.3c\tset program priority\nnlist\tnlist.3\tget entries from name list\nntohl\tbyteorder.3n\tconvert values between host and network byte order\nntohs\tbyteorder.3n\tconvert values between host and network byte order\nopendir\tdirectory.3\tdirectory operations\nopenlog\tsyslog.3\tcontrol system log\nopenpl\tplot.3x\tgraphics interface\npause\tpause.3c\tstop until signal\npclose\tpopen.3\tinitiate I/O to/from a process\nperror\tperror.3\tsystem error messages\npoint\tplot.3x\tgraphics interface\npopen\tpopen.3\tinitiate I/O to/from a process\npow\texp.3m\texponential x**y\nprintf\tprintf.3s\tformatted output conversion\npsignal\tpsignal.3\tsystem signal messages\nputc\tputc.3s\tput character or word on a stream\nputchar\tputc.3s\tput character or word on a stream\nputs\tputs.3s\tput a string on a stream\nputw\tputc.3s\tput character or word on a stream\nqsort\tqsort.3\tquicker sort\nrand\trand.3c\trandom number generator\nrandom\trandom.3\tbetter random number generator\nrcmd\trcmd.3x\troutines for returning a stream to a remote command\nre_comp\tregex.3\tregular expression handler\nre_exec\tregex.3\tregular expression handler\nreaddir\tdirectory.3\tdirectory operations\nrealloc\tmalloc.3\tmemory allocator\nremque\tinsque.3\tinsert/remove element from a queue\nrewind\tfseek.3s\treposition a stream\nrewinddir\tdirectory.3\tdirectory operations\nrexec\trexec.3x\treturn stream to a remote command\nrindex\tstring.3\tstring operations\nrint\tfloor.3m\tround to nearest integer\nrresvport\trcmd.3x\troutines for returning a stream to a remote command\nruserok\trcmd.3x\troutines for returning a stream to a remote command\nscalb\tieee.3m\texponent adjustment\nscandir\tscandir.3\tscan a directory\nscanf\tscanf.3s\tformatted input conversion\nseekdir\tdirectory.3\tdirectory operations\nsetbuf\tsetbuf.3s\tassign buffering to a stream\nsetbuffer\tsetbuf.3s\tassign buffering to a stream\nsetegid\tsetuid.3\tset user and group ID\nseteuid\tsetuid.3\tset user and group ID\nsetfsent\tgetfsent.3x\tget file system descriptor file entry\nsetgid\tsetuid.3\tset user and group ID\nsetgrent\tgetgrent.3\tget group file entry\nsethostent\tgethostbyname.3n\tget network host entry\nsetjmp\tsetjmp.3\tnon-local goto\nsetkey\tcrypt.3\tDES encryption\nsetlinebuf\tsetbuf.3s\tassign buffering to a stream\nsetnetent\tgetnetent.3n\tget network entry\nsetprotoent\tgetprotoent.3n\tget protocol entry\nsetpwent\tgetpwent.3\tget password file entry\nsetrgid\tsetuid.3\tset user and group ID\nsetruid\tsetuid.3\tset user and group ID\nsetservent\tgetservent.3n\tget service entry\nsetstate\trandom.3\tbetter random number generator\nsetuid\tsetuid.3\tset user and group ID\nsignal\tsignal.3\tsimplified software signal facilities\nsin\tsin.3m\ttrigonometric function\nsinh\tsinh.3m\thyperbolic function\nsleep\tsleep.3\tsuspend execution for interval\nspace\tplot.3x\tgraphics interface\nsprintf\tprintf.3s\tformatted output conversion\nsqrt\tsqrt.3m\tsquare root\nsrand\trand.3c\trandom number generator\nsrandom\trandom.3\tbetter random number generator\nsscanf\tscanf.3s\tformatted input conversion\nstdio\tintro.3s\tstandard buffered input/output package\nstore\tdbm.3x\tdata base subroutines\nstrcat\tstring.3\tstring operations\nstrcmp\tstring.3\tstring operations\nstrcpy\tstring.3\tstring operations\nstrlen\tstring.3\tstring operations\nstrncat\tstring.3\tstring operations\nstrncmp\tstring.3\tstring operations\nstrncpy\tstring.3\tstring operations\nstty\tstty.3c\tset and get terminal state (defunct)\nswab\tswab.3\tswap bytes\nsys_errlist\tperror.3\tsystem error messages\nsys_nerr\tperror.3\tsystem error messages\nsys_siglist\tpsignal.3\tsystem signal messages\nsyslog\tsyslog.3\tcontrol system log\nsystem\tsystem.3\tissue a shell command\ntan\tsin.3m\ttrigonometric function\ntanh\tsinh.3m\thyperbolic function\ntelldir\tdirectory.3\tdirectory operations\ntgetent\ttermcap.3x\tterminal independent operation routines\ntgetflag\ttermcap.3x\tterminal independent operation routines\ntgetnum\ttermcap.3x\tterminal independent operation routines\ntgetstr\ttermcap.3x\tterminal independent operation routines\ntgoto\ttermcap.3x\tterminal independent operation routines\ntime\ttime.3c\tget date and time\ntimes\ttimes.3c\tget process times\ntimezone\tctime.3\tconvert date and time to ASCII\ntputs\ttermcap.3x\tterminal independent operation routines\nttyname\tttyname.3\tfind name of a terminal\nttyslot\tttyname.3\tfind name of a terminal\nungetc\tungetc.3s\tpush character back into input stream\nutime\tutime.3c\tset file times\nvalloc\tvalloc.3\taligned memory allocator\nvarargs\tvarargs.3\tvariable argument list\nvlimit\tvlimit.3c\tcontrol maximum system resource consumption\nvtimes\tvtimes.3c\tget information about resource utilization\ny0\tj0.3m\tbessel function\ny1\tj0.3m\tbessel function\nyn\tj0.3m\tbessel function\n.fi\n"
  },
  {
    "path": "share/man/man3/j0.3",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)j0.3m\t6.6 (Berkeley) 5/12/86\n.\\\"\n.TH J0 3M  \"May 12, 1986\"\n.UC 4\n.SH NAME\nj0, j1, jn, y0, y1, yn \\- bessel functions\n.SH SYNOPSIS\n.nf\n.B #include <math.h>\n.PP\n.B double j0(x)\n.B double x;\n.PP\n.B double j1(x)\n.B double x;\n.PP\n.B double jn(n,x)\n.B int n;\n.B double x;\n.PP\n.B double y0(x)\n.B double x;\n.PP\n.B double y1(x)\n.B double x;\n.PP\n.B double yn(n,x)\n.B int n;\n.B double x;\n.fi\n.SH DESCRIPTION\nThese functions calculate Bessel functions of the first\nand second kinds for real arguments and integer orders.\n.SH DIAGNOSTICS\nOn a VAX, negative arguments cause y0, y1 and yn\nto return the reserved operand and set \\fIerrno\\fR to EDOM.\n.SH SEE ALSO\nmath(3M), infnan(3M)\n"
  },
  {
    "path": "share/man/man3/l3tol.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)l3tol.3\t2.3 (Berkeley) 1/22/87\n.\\\"\n.TH L3TOL 3 \"January 22, 1987\"\n.UC 2\n.SH NAME\nl3tol, ltol3 \\- convert between 3-byte and long integers (2BSD)\n.SH SYNOPSIS\n.nf\n.ft B\nl3tol(lp, cp, n)\nlong *lp;\nchar *cp;\n\nltol3(cp, lp, n)\nchar *cp;\nlong *lp;\n.fi\n.ft R\n.SH DESCRIPTION\n.I L3tol\nconverts a list of\n.I n\nthree-byte integers packed into a character string\npointed to by \n.I cp\ninto a list of long integers pointed to by\n.IR lp .\n.PP\n.I Ltol3\nperforms the inverse conversion from long integers\n.RI ( lp )\nto three-byte integers\n.RI ( cp ).\n.PP\nThese functions are useful for file-system maintenance under\n2BSD where disk addresses within inodes are three bytes long.\n.SH SEE ALSO\nfs(5)\n.SH BUGS\n.IR l3tol \" and \" ltol3\nare unique to the PDP-11 and 2BSD; their use is discouraged.\n"
  },
  {
    "path": "share/man/man3/ldfps.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ldfps.3\t1.1 (Berkeley) 8/10/88\n.\\\"\n.TH LDFPS 3 \"August 10, 1988\"\n.UC 2\n.SH NAME\nldfps \\- load floating point status register\n.SH SYNOPSIS\n.nf\n.ft B\nvoid ldfps(fps)\nunsigned int fps;\n.ft P\n.fi\n.SH DESCRIPTION\n.I Ldfps\nloads the hardware floating point status register with\n.IR fps .\nSee the PDP-11 hardware handbook for a description of the meaning of the\nvarious bits in\n.IR fps .\n.SH BUGS\n.I Ldfps\nis unique to the PDP-11 and 2BSD; its use is discouraged.\n"
  },
  {
    "path": "share/man/man3/lgamma.3",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)lgamma.3m\t6.2 (Berkeley) 5/12/86\n.\\\"\n.TH LGAMMA 3M  \"May 12, 1986\"\n.UC 6\n.SH NAME\nlgamma \\- log gamma function\n.SH SYNOPSIS\n.nf\n.B #include <math.h>\n.PP\n.B double lgamma(x)\n.B double x;\n.fi\n.SH DESCRIPTION\n.nf\n.ta \\w'Lgamma returns ln\\||\\(*G(x)| where'u+1n +1.7i\n.if t \\{\\\nLgamma returns ln\\||\\(*G(x)| where\t\\(*G(x) = \\(is\\d\\s8\\z0\\s10\\u\\u\\s8\\(if\\s10\\d t\\u\\s8x\\-1\\s10\\d e\\u\\s8\\-t\\s10\\d dt\tfor x > 0 and\n.br\n\t\\(*G(x) = \\(*p/(\\(*G(1\\-x)\\|sin(\\(*px))\tfor x < 1.  \\}\n.if n \\\nLgamma returns ln\\||\\(*G(x)|.\n.ta\n.fi\n.PP\nThe external integer signgam returns the sign of\n\\(*G(x) .\n.SH IDIOSYNCRASIES\nDo \\fBnot\\fR use the expression signgam\\(**exp(lgamma(x))\nto compute g := \\(*G(x).  Instead use a program like this (in C):\n.RS\nlg = lgamma(x); g = signgam\\(**exp(lg);\n.RE\n.PP\nOnly after lgamma has returned can signgam be correct.\nNote too that \\(*G(x) must overflow when x is large enough,\nunderflow when \\-x is large enough, and spawn a division by zero\nwhen x is a nonpositive integer.\n.PP\nOnly in the UNIX math library for C was the name gamma ever attached\nto ln\\(*G.  Elsewhere, for instance in IBM's FORTRAN library, the name\nGAMMA belongs to \\(*G and the name ALGAMA to ln\\(*G in single precision;\nin double the names are DGAMMA and DLGAMA.  Why should C be different?\n.PP\nArchaeological records suggest that C's gamma originally delivered\nln(\\(*G(|x|)).  Later, the program gamma was changed to\ncope with negative arguments x in a more conventional way, but\nthe documentation did not reflect that change correctly.  The most\nrecent change corrects inaccurate values when x is almost a\nnegative integer, and lets \\(*G(x) be computed without\nconditional expressions.  Programmers should not assume that\nlgamma has settled down.\n.PP\nAt some time in the future, the name \\fIgamma\\fR will be rehabilitated\nand used for the gamma function, just as is done in FORTRAN.\nThe reason for this is not so much compatibility with FORTRAN as a\ndesire to achieve greater speed for smaller values of |x| and greater\naccuracy for larger values.\n.PP\nMeanwhile, programmers who have to use the name \\fIgamma\\fR in its former\nsense, for what is now \\fIlgamma\\fR, have two choices:\n.IP 1) \\w'1)\\0'u\nUse the old math library, \\fIlibom\\fR.\n.IP 2) \\w'1)\\0'u\nAdd the following program to your others:\n.RS\n.nf\n\\fB#include <math.h>\ndouble gamma(x)\ndouble x;\n{\n.RS\n\\fBreturn (lgamma(x));\n.RE\n}\\fR\n.RE\n.fi\n.SH DIAGNOSTICS\nThe reserved operand is returned on a VAX for negative integer arguments,\n\\fIerrno\\fR is set to ERANGE; for very large arguments over/underflows will\noccur inside the \\fIlgamma\\fP routine.\n.SH SEE ALSO\nmath(3M), infnan(3M)\n"
  },
  {
    "path": "share/man/man3/lib2648.3",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)lib2648.3x\t6.2 (Berkeley) 5/27/86\n.\\\"\n.TH LIB2648 3X \"May 27, 1986\"\n.UC 5\n.SH NAME\nlib2648 \\- subroutines for the HP 2648 graphics terminal\n.SH SYNOPSIS\n.B #include <stdio.h>\n.sp\n.B \"typedef char\"\n.RB * bitmat ;\n.br\nFILE *trace;\n.sp\ncc file.c\n.B \\-l2648\n.SH DESCRIPTION\n.I Lib2648\nis a general purpose library of subroutines useful\nfor interactive graphics on the Hewlett-Packard 2648 graphics terminal.\nTo use it you must call the routine\n.IR ttyinit ()\nat the beginning of execution,\nand\n.IR done ()\nat the end of execution.\nAll terminal input and output must go through the routines\n.IR rawchar ,\n.IR readline ,\n.IR outchar ,\nand\n.IR outstr .\n.PP\n.I Lib2648\ndoes the necessary ^E/^F handshaking if\n.I \"getenv(``TERM'')\"\nreturns ``hp2648'', as it will if set by\n.IR tset (1).\nAny other value, including for example ``2648'', will disable handshaking.\n.PP\nBit matrix routines are provided to model the graphics memory of the 2648.\nThese routines are generally useful, but are specifically useful for the\n.I update\nfunction which efficiently changes what is on the screen to what is\nsupposed to be on the screen.\nThe primative bit matrix routines are\n.IR newmat ,\n.IR mat ,\nand\n.IR setmat .\n.PP\nThe file\n.IR trace ,\nif non-null, is expected to be a file descriptor as returned by\n.IR fopen .\nIf so,\n.I lib2648\nwill trace the progress of the output by writing onto\nthis file.\nIt is provided to make debugging output feasible for graphics programs without\nmessing up the screen or the escape sequences being sent.\nTypical use of trace will include:\n.nf\n\t\\fBswitch\\fP (argv[1][1]) {\n\t\\fBcase\\fP 'T':\n\t\ttrace = fopen(\"trace\", \"w\");\n\t\t\\fBbreak\\fP;\n\t...\n\t\\fBif\\fP (trace)\n\t\tfprintf(trace, \"x is %d, y is %s\\en\", x, y);\n\t...\n\tdumpmat(\"before update\", xmat);\n.fi\n.SH ROUTINES\n.TP\n.B agoto(x, y)\nMove the alphanumeric cursor to position (x, y),\nmeasured from the upper left corner of the screen.\n.TP\n.B aoff()\nTurn the alphanumeric display off.\n.TP\n.B aon()\nTurn the alphanumeric display on.\n.TP\n.B areaclear(rmin, cmin, rmax, cmax)\nClear the area on the graphics screen bordered by the four arguments.\nIn normal mode the area is set to all black, in inverse video mode\nit is set to all white.\n.TP\n.B beep()\nRing the bell on the terminal.\n.TP\n.B bitcopy(dest, src, rows, cols) bitmat dest, src;\nCopy a\n.I rows\nby\n.I cols\nbit matrix from\n.I src\nto (user provided)\n.I dest.\n.TP\n.B cleara()\nClear the alphanumeric display.\n.TP\n.B clearg()\nClear the graphics display.\nNote that the 2648 will only clear the part of the screen\nthat is visible if zoomed in.\n.TP\n.B curoff()\nTurn the graphics cursor off.\n.TP\n.B curon()\nTurn the graphics cursor on.\n.TP\n.B dispmsg(str, x, y, maxlen) char *str;\nDisplay the message \n.I str\nin graphics text at position\n.I (x, y).\nThe maximum message length is given by\n.IR maxlen ,\nand is needed for dispmsg to know how big an area to clear\nbefore drawing the message.\nThe lower left corner of the first character is at\n.I (x, y).\n.TP\n.B done()\nShould be called before the program exits.\nRestores the tty to normal, turns off graphics screen,\nturns on alphanumeric screen, flushes the standard output, etc.\n.TP\n.B draw(x, y)\nDraw a line from the pen location to\n.I (x, y).\nAs with all graphics coordinates,\n.I (x, y)\nis measured from the bottom left corner of the screen.\n.I (x, y)\ncoordinates represent the first quadrant of the usual Cartesian system.\n.TP\n.B drawbox(r, c, color, rows, cols)\nDraw a rectangular box on the graphics screen.\nThe lower left corner is at location\n.I (r, c).\nThe box is\n.I rows\nrows high and\n.I cols\ncolumns wide.\nThe box is drawn if\n.I color\nis 1, erased if\n.I color\nis 0.\n.I (r, c)\nabsolute coordinates represent row and column on the screen,\nwith the origin at the lower left.\nThey are equivalent to\n.I (x, y)\nexcept for being reversed in order.\n.TP\n.B \"dumpmat(msg, m, rows, cols) char *msg; bitmat m;\"\nIf\n.I trace\nis non-null, write a readable ASCII representation\nof the matrix\n.I m\non\n.I trace.\n.I Msg\nis a label to identify the output.\n.TP\n.B emptyrow(m, rows, cols, r) bitmat m;\nReturns 1 if row\n.I r\nof matrix\n.I m\nis all zero, else returns 0.\nThis routine is provided because it can be implemented more\nefficiently with a knowledge of the internal representation\nthan a series of calls to\n.I mat.\n.TP\n.B error(msg) char *msg;\nDefault error handler.\nCalls\n.I message(msg)\nand returns.\nThis is called by certain routines in\n.IR lib2648 .\nIt is also suitable for calling by the user program.\nIt is probably a good idea for a fancy graphics program\nto supply its own error procedure which uses\n.IR setjmp (3)\nto restart the program.\n.TP\n.B gdefault()\nSet the terminal to the default graphics modes.\n.TP\n.B goff()\nTurn the graphics display off.\n.TP\n.B gon()\nTurn the graphics display on.\n.TP\n.B koff()\nTurn the keypad off.\n.TP\n.B kon()\nTurn the keypad on.\nThis means that most special keys on the terminal (such as the alphanumeric\narrow keys) will transmit an escape sequence instead of doing their function\nlocally.\n.TP\n.B line(x1, y1, x2, y2)\nDraw a line in the current mode from\n.I (x1, y1)\nto\n.I (x2, y2).\nThis is equivalent to\n.I \"move(x1, y1); draw(x2, y2);\"\nexcept that a bug in the terminal involving repeated lines from the\nsame point is compensated for.\n.TP\n.B lowleft()\nMove the alphanumeric cursor to the lower left (home down) position.\n.TP\n.B \"mat(m, rows, cols, r, c) bitmat m;\"\nUsed to retrieve an element from a bit matrix.\nReturns 1 or 0 as the value of the\n.I [r, c]\nelement of the\n.I rows\nby\n.I cols\nmatrix\n.I m.\nBit matrices are numbered\n.I (r, c)\nfrom the upper left corner of the matrix,\nbeginning at (0, 0).\n.I R\nrepresents the row, and\n.I c\nrepresents the column.\n.TP\n.B message(str) char *str;\nDisplay the text message\n.I str\nat the bottom of the graphics screen.\n.TP\n.B \"minmax(g, rows, cols, rmin, cmin, rmax, cmax) bitmat g;\"\n.ti -.5i\n.B int *rmin, *cmin, *rmax, *cmax;\n.br\nFind the smallest rectangle that contains all the 1 (on) elements in\nthe bit matrix g.\nThe coordinates are returned in the variables\npointed to by rmin, cmin, rmax, cmax.\n.TP\n.B move(x, y)\nMove the pen to location\n.I (x, y).\nSuch motion is internal and will not cause output\nuntil a subsequent\n.I sync().\n.TP\n.B movecurs(x, y)\nMove the graphics cursor to location\n.I (x, y).\n.TP\n.B bitmat newmat(rows, cols)\nCreate (with\n.IR malloc (3))\na new bit matrix of size\n.I rows\nby\n.I cols.\nThe value created (e.g. a pointer to the first location) is returned.\nA bit matrix can be freed directly with\n.IR free .\n.TP\n.B outchar(c) char c;\nPrint the character\n.I c\non the standard output.\nAll output to the terminal should go through this routine or\n.IR outstr .\n.TP\n.B outstr(str) char *str;\nPrint the string str on the standard output by repeated calls to\n.I outchar.\n.TP\n.B printg()\nPrint the graphics display on the printer.\nThe printer must be configured as device 6 (the default) on the HPIB.\n.TP\n.B char rawchar()\nRead one character from the terminal and return it.\nThis routine or\n.I readline\nshould be used to get all input,\nrather than\n.IR getchar (3).\n.TP\n.B rboff()\nTurn the rubber band line off.\n.TP\n.B rbon()\nTurn the rubber band line on.\n.TP\n.B char *rdchar(c) char c;\nReturn a readable representation of the character\n.I c.\nIf\n.I c\nis a printing character it returns itself, if a control\ncharacter it is shown in the ^X notation, if negative\nan apostrophe is prepended.  Space returns ^\\`, rubout returns ^?.\n.IP\n.B NOTE:\nA pointer to a static place is returned.\nFor this reason, it will not work to pass rdchar twice to the same\n.IR fprintf / sprintf\ncall.\nYou must instead save one of the values in your own buffer with strcpy.\n.TP\n.B readline(prompt, msg, maxlen) char *prompt, *msg;\nDisplay\n.I prompt\non the bottom line of the graphics display\nand read one line of text from the user, terminated by a newline.\nThe line is placed in the buffer\n.IR msg ,\nwhich has size\n.I maxlen\ncharacters.\nBackspace processing is supported.\n.TP\n.B setclear()\nSet the display to draw lines in erase mode.\n(This is reversed by inverse video mode.)\n.TP\n.B \"setmat(m, rows, cols, r, c, val) bitmat m;\"\nThe basic operation to store a value in an element of a bit matrix.\nThe\n.I [r, c]\nelement of\n.I m\nis set to\n.I val,\nwhich should be either 0 or 1.\n.TP\n.B setset()\nSet the display to draw lines in normal (solid) mode.\n(This is reversed by inverse video mode.)\n.TP\n.B setxor()\nSet the display to draw lines in exclusive or mode.\n.TP\n.B sync()\nForce all accumulated output to be displayed on the screen.\nThis should be followed by fflush(stdout).\nThe cursor is not affected by this function.\nNote that it is normally never necessary to call\n.IR sync ,\nsince\n.I rawchar\nand\n.I readline\ncall\n.I sync()\nand\n.I fflush(stdout)\nautomatically.\n.TP\n.B togvid()\nToggle the state of video.\nIf in normal mode, go into inverse video mode,\nand vice versa.\nThe screen is reversed as well as the\ninternal state of the library.\n.TP\n.B ttyinit()\nSet up the terminal for processing.\nThis routine should be called at the beginning of execution.\nIt places the terminal in CBREAK mode, turns off echo,\nsets the proper modes in the terminal,\nand initializes the library.\n.TP\n.B \"update(mold, mnew, rows, cols, baser, basec) bitmat mold, mnew;\"\nMake whatever changes are needed to make a window on the screen\nlook like\n.IR mnew .\n.I Mold\nis what the window on the screen currently looks like.\nThe window has size\n.I rows\nby\n.IR cols ,\nand the lower left corner on\nthe screen of the window is\n.I [baser, basec].\nNote:\n.I update\nwas not intended to be used for the entire screen.\nIt would work but be very slow and take 64K bytes\nof memory just for mold and mnew.\nIt was intended for 100 by 100 windows with objects in the center\nof them, and is quite fast for such windows.\n.TP\n.B vidinv()\nSet inverse video mode.\n.TP\n.B vidnorm()\nSet normal video mode.\n.TP\n.B zermat(m, rows, cols) bitmat m;\nSet the bit matrix\n.I m\nto all zeros.\n.TP\n.B zoomn(size)\nSet the hardware zoom to value\n.I size,\nwhich can range from 1 to 15.\n.TP\n.B zoomoff()\nTurn zoom off.\nThis forces the screen to zoom level 1 without affecting the\ncurrent internal zoom number.\n.TP\n.B zoomon()\nTurn zoom on.\nThis restores the screen to the previously specified zoom size.\n.SH DIAGNOSTICS\nThe routine\n.I error\nis called when an error is detected.\nThe only error currently detected is overflow of the buffer\nprovided to\n.IR readline .\n.PP\nSubscripts out of bounds to\n.I setmat\nreturn without setting anything.\n.SH FILES\n/usr/lib/lib2648.a\n.SH \"SEE ALSO\"\nfed(1)\n.SH AUTHOR\nMark Horton\n.SH BUGS\nThis library is not supported.\nIt makes no attempt to use all of the features of the terminal,\nonly those needed by fed.\nContributions from users will be accepted for addition to the library.\n.PP\nThe HP 2648 terminal is somewhat unreliable at speeds over 2400 baud,\neven with the ^E/^F handshaking.\nIn an effort to improve reliability, handshaking is done every 32 characters.\n(The manual claims it is only necessary every 80 characters.)\nNonetheless, I/O errors sometimes still occur.\n.PP\nThere is no way to control the amount of debugging output generated\non\n.I trace\nwithout modifying the source to the library.\n"
  },
  {
    "path": "share/man/man3/malloc.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)malloc.3\t6.3 (Berkeley) 5/14/86\n.\\\"\n.TH MALLOC 3  \"May 14, 1986\"\n.UC 4\n.SH NAME\nmalloc, free, realloc, calloc, alloca \\- memory allocator\n.SH SYNOPSIS\n.nf\n.B char *malloc(size)\n.B unsigned size;\n.PP\n.B free(ptr)\n.B char *ptr;\n.PP\n.B char *realloc(ptr, size)\n.B char *ptr;\n.B unsigned size;\n.PP\n.B char *calloc(nelem, elsize)\n.B unsigned nelem, elsize;\n.PP\n.B char *alloca(size)\n.B int size;\n.fi\n.SH DESCRIPTION\n.I Malloc\nand\n.I free\nprovide a general-purpose memory allocation package.\n.I Malloc\nreturns a pointer to a block of at least\n.I size\nbytes beginning on a word boundary.\n.PP\nThe argument to\n.I free\nis a pointer to a block previously allocated by\n.IR malloc ;\nthis space is made available for further allocation,\nbut its contents are left undisturbed.\n.PP\nNeedless to say, grave disorder will result if the space assigned by\n.I malloc\nis overrun or if some random number is handed to\n.IR free .\n.PP\n.I Malloc\nmaintains multiple lists of free blocks according to size,\nallocating space from the appropriate list.\nIt calls\n.I sbrk\n(see\n.IR brk (2))\nto get more memory from the system when there is no\nsuitable space already free.\n.PP\n.I Realloc\nchanges the size of the block pointed to by\n.I ptr\nto\n.I size\nbytes and returns a pointer to the (possibly moved) block.\nThe contents will be unchanged up to the lesser of the new and old sizes.\n.PP\nIn order to be compatible with older versions,\n.I realloc\nalso works if\n.I ptr\npoints to a block freed since the last call of\n.I malloc, realloc\nor\n.IR calloc ;\nsequences of\n.I free, malloc\nand\n.I realloc\nwere previously used to attempt storage compaction.\nThis procedure is no longer recommended.\n.PP\n.I Calloc\nallocates space for an array of\n.I nelem\nelements of size\n.I elsize.\nThe space is initialized to zeros.\n.PP\n.I Alloca\nallocates \n.I size\nbytes of space in the stack frame of the caller.\nThis temporary space is automatically freed on\nreturn.\n.PP\nEach of the allocation routines returns a pointer\nto space suitably aligned (after possible pointer coercion)\nfor storage of any type of object.\nIf the space is of\n.I pagesize\nor larger, the memory returned will be page-aligned.\n.SH SEE ALSO\nbrk(2),\npagesize(2)\n.SH DIAGNOSTICS\n.I Malloc, realloc\nand\n.I calloc\nreturn a null pointer (0) if there is no available memory or if the arena\nhas been detectably corrupted by storing outside the bounds of a block.\n.I Malloc\nmay be recompiled to check the arena very stringently on every transaction;\nthose sites with a source code license may check the source code to see\nhow this can be done.\n.SH BUGS\nWhen\n.I realloc\nreturns 0, the block pointed to by\n.I ptr\nmay be destroyed.\n.PP\nThe current implementation of\n.I malloc\ndoes not always fail gracefully when system\nmemory limits are approached.\nIt may fail to allocate memory when larger free blocks could be broken\nup, or when limits are exceeded because the size is rounded up.\nIt is optimized for sizes that are powers of two.\n.PP\n.I Alloca\nis machine dependent; its use is discouraged.\n"
  },
  {
    "path": "share/man/man3/math.3",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)math.3m\t6.8 (Berkeley) 5/27/86\n.\\\"\n.TH MATH 3M \"May 27, 1986\"\n.UC 4\n.ds up \\fIulp\\fR\n.ds nn \\fINaN\\fR\n.de If\n.if n \\\\\n\\\\$1Infinity\\\\$2\n.if t \\\\\n\\\\$1\\\\(if\\\\$2\n..\n.SH NAME\nmath \\- introduction to mathematical library functions\n.SH DESCRIPTION\nThese functions constitute the C math library,\n.I libm.\nThe link editor searches this library under the \\*(lq\\-lm\\*(rq option.\nDeclarations for these functions may be obtained from the include file\n.RI < math.h >.\nThe Fortran math library is described in ``man 3f intro''.\n.SH \"LIST OF FUNCTIONS\"\n.sp 2\n.nf\n.ta \\w'copysign'u+2n +\\w'infnan.3m'u+10n +\\w'inverse trigonometric func'u\n\\fIName\\fP\t\\fIAppears on Page\\fP\t\\fIDescription\\fP\t\\fIError Bound (ULPs)\\fP\n.ta \\w'copysign'u+4n +\\w'infnan.3m'u+4n +\\w'inverse trigonometric function'u+6nC\n.sp 5p\nacos\tsin.3m\tinverse trigonometric function\t3\nacosh\tasinh.3m\tinverse hyperbolic function\t3\nasin\tsin.3m\tinverse trigonometric function\t3\nasinh\tasinh.3m\tinverse hyperbolic function\t3\natan\tsin.3m\tinverse trigonometric function\t1\natanh\tasinh.3m\tinverse hyperbolic function\t3\natan2\tsin.3m\tinverse trigonometric function\t2\ncabs\thypot.3m\tcomplex absolute value\t1\ncbrt\tsqrt.3m\tcube root\t1\nceil\tfloor.3m\tinteger no less than\t0\ncopysign\tieee.3m\tcopy sign bit\t0\ncos\tsin.3m\ttrigonometric function\t1\ncosh\tsinh.3m\thyperbolic function\t3\ndrem\tieee.3m\tremainder\t0\nerf\terf.3m\terror function\t???\nerfc\terf.3m\tcomplementary error function\t???\nexp\texp.3m\texponential\t1\nexpm1\texp.3m\texp(x)\\-1\t1\nfabs\tfloor.3m\tabsolute value\t0\nfloor\tfloor.3m\tinteger no greater than\t0\nhypot\thypot.3m\tEuclidean distance\t1\ninfnan\tinfnan.3m\tsignals exceptions\nj0\tj0.3m\tbessel function\t???\nj1\tj0.3m\tbessel function\t???\njn\tj0.3m\tbessel function\t???\nlgamma\tlgamma.3m\tlog gamma function; (formerly gamma.3m)\nlog\texp.3m\tnatural logarithm\t1\nlogb\tieee.3m\texponent extraction\t0\nlog10\texp.3m\tlogarithm to base 10\t3\nlog1p\texp.3m\tlog(1+x)\t1\npow\texp.3m\texponential x**y\t60\\-500\nrint\tfloor.3m\tround to nearest integer\t0\nscalb\tieee.3m\texponent adjustment\t0\nsin\tsin.3m\ttrigonometric function\t1\nsinh\tsinh.3m\thyperbolic function\t3\nsqrt\tsqrt.3m\tsquare root\t1\ntan\tsin.3m\ttrigonometric function\t3\ntanh\tsinh.3m\thyperbolic function\t3\ny0\tj0.3m\tbessel function\t???\ny1\tj0.3m\tbessel function\t???\nyn\tj0.3m\tbessel function\t???\n.ta\n.fi\n.SH NOTES\nIn 4.3 BSD, distributed from the University of California\nin late 1985, most of the foregoing functions come in two\nversions, one for the double\\-precision \"D\" format in the\nDEC VAX\\-11 family of computers, another for double\\-precision\narithmetic conforming to the IEEE Standard 754 for Binary\nFloating\\-Point Arithmetic.  The two versions behave very\nsimilarly, as should be expected from programs more accurate\nand robust than was the norm when UNIX was born.  For\ninstance, the programs are accurate to within the numbers\nof \\*(ups tabulated above; an \\*(up is one \\fIU\\fRnit in the \\fIL\\fRast\n\\fIP\\fRlace.  And the programs have been cured of anomalies that\nafflicted the older math library \\fIlibm\\fR in which incidents like\nthe following had been reported:\n.RS\nsqrt(\\-1.0) = 0.0 and log(\\-1.0) = \\-1.7e38.\n.br\ncos(1.0e\\-11) > cos(0.0) > 1.0.\n.br\npow(x,1.0)\n.if n \\\n!=\n.if t \\\n\\(!=\nx when x = 2.0, 3.0, 4.0, ..., 9.0.\n.br\npow(\\-1.0,1.0e10) trapped on Integer Overflow.\n.br\nsqrt(1.0e30) and sqrt(1.0e\\-30) were very slow.\n.RE\nHowever the two versions do differ in ways that have to be\nexplained, to which end the following notes are provided.\n.PP\n\\fBDEC VAX\\-11 D_floating\\-point:\\fR\n.PP\nThis is the format for which the original math library \\fIlibm\\fR\nwas developed, and to which this manual is still principally\ndedicated.  It is \\fIthe\\fR double\\-precision format for the PDP\\-11\nand the earlier VAX\\-11 machines; VAX\\-11s after 1983 were\nprovided with an optional \"G\" format closer to the IEEE\ndouble\\-precision format.  The earlier DEC MicroVAXs have no\nD format, only G double\\-precision. (Why?  Why not?)\n.PP\nProperties of D_floating\\-point:\n.RS\nWordsize: 64 bits, 8 bytes.  Radix: Binary.\n.br\nPrecision: 56\n.if n \\\nsig.\n.if t \\\nsignificant\nbits, roughly like 17\n.if n \\\nsig.\n.if t \\\nsignificant\ndecimals.\n.RS\nIf x and x' are consecutive positive D_floating\\-point\nnumbers (they differ by 1 \\*(up), then\n.br\n1.3e\\-17 < 0.5**56 < (x'\\-x)/x \\(<= 0.5**55 < 2.8e\\-17.\n.RE\n.nf\n.ta \\w'Range:'u+1n +\\w'Underflow threshold'u+1n +\\w'= 2.0**127'u+1n\nRange:\tOverflow threshold\t= 2.0**127\t= 1.7e38.\n\tUnderflow threshold\t= 0.5**128\t= 2.9e\\-39.\n\tNOTE:  THIS RANGE IS COMPARATIVELY NARROW.\n.ta\n.fi\n.RS\nOverflow customarily stops computation.\n.br\nUnderflow is customarily flushed quietly to zero.\n.br\nCAUTION:\n.RS\nIt is possible to have x\n.if n \\\n!=\n.if t \\\n\\(!=\ny and yet\nx\\-y = 0 because of underflow.  Similarly\nx > y > 0 cannot prevent either x\\(**y = 0\nor  y/x = 0 from happening without warning.\n.RE\n.RE\nZero is represented ambiguously.\n.RS\nAlthough 2**55 different representations of zero are accepted by\nthe hardware, only the obvious representation is ever produced.\nThere is no \\-0 on a VAX.\n.RE\n.If\nis not part of the VAX architecture.\n.br\nReserved operands:\n.RS\nof the 2**55 that the hardware\nrecognizes, only one of them is ever produced.\nAny floating\\-point operation upon a reserved\noperand, even a MOVF or MOVD, customarily stops\ncomputation, so they are not much used.\n.RE\nExceptions:\n.RS\nDivisions by zero and operations that\noverflow are invalid operations that customarily\nstop computation or, in earlier machines, produce\nreserved operands that will stop computation.\n.RE\nRounding:\n.RS\nEvery rational operation  (+, \\-, \\(**, /) on a\nVAX (but not necessarily on a PDP\\-11), if not an\nover/underflow nor division by zero, is rounded to\nwithin half an \\*(up, and when the rounding error is\nexactly half an \\*(up then rounding is away from 0.\n.RE\n.RE\n.PP\nExcept for its narrow range, D_floating\\-point is one of the\nbetter computer arithmetics designed in the 1960's.\nIts properties are reflected fairly faithfully in the elementary\nfunctions for a VAX distributed in 4.3 BSD.\nThey over/underflow only if their results have to lie out of range\nor very nearly so, and then they behave much as any rational\narithmetic operation that over/underflowed would behave.\nSimilarly, expressions like log(0) and atanh(1) behave\nlike 1/0; and sqrt(\\-3) and acos(3) behave like 0/0;\nthey all produce reserved operands and/or stop computation!\nThe situation is described in more detail in manual pages.\n.RS\n.ll -0.5i\n\\fIThis response seems excessively punitive, so it is destined\nto be replaced at some time in the foreseeable future by a\nmore flexible but still uniform scheme being developed to\nhandle all floating\\-point arithmetic exceptions neatly.\nSee infnan(3M) for the present state of affairs.\\fR\n.ll +0.5i\n.RE\n.PP\nHow do the functions in 4.3 BSD's new \\fIlibm\\fR for UNIX\ncompare with their counterparts in DEC's VAX/VMS library?\nSome of the VMS functions are a little faster, some are\na little more accurate, some are more puritanical about\nexceptions (like pow(0.0,0.0) and atan2(0.0,0.0)),\nand most occupy much more memory than their counterparts in\n\\fIlibm\\fR.\nThe VMS codes interpolate in large table to achieve\nspeed and accuracy; the \\fIlibm\\fR codes use tricky formulas\ncompact enough that all of them may some day fit into a ROM.\n.PP\nMore important, DEC regards the VMS codes as proprietary\nand guards them zealously against unauthorized use.  But the\n\\fIlibm\\fR codes in 4.3 BSD are intended for the public domain;\nthey may be copied freely provided their provenance is always\nacknowledged, and provided users assist the authors in their\nresearches by reporting experience with the codes.\nTherefore no user of UNIX on a machine whose arithmetic resembles\nVAX D_floating\\-point need use anything worse than the new \\fIlibm\\fR.\n.PP\n\\fBIEEE STANDARD 754 Floating\\-Point Arithmetic:\\fR\n.PP\nThis standard is on its way to becoming more widely adopted\nthan any other design for computer arithmetic.\nVLSI chips that conform to some version of that standard have been\nproduced by a host of manufacturers, among them ...\n.nf\n.ta 0.5i +\\w'Intel i8070, i80287'u+6n\n\tIntel i8087, i80287\tNational Semiconductor  32081\n\tMotorola 68881\tWeitek WTL-1032, ... , -1165\n\tZilog Z8070\tWestern Electric (AT&T) WE32106.\n.ta\n.fi\nOther implementations range from software, done thoroughly\nin the Apple Macintosh, through VLSI in the Hewlett\\-Packard\n9000 series, to the ELXSI 6400 running ECL at 3 Megaflops.\nSeveral other companies have adopted the formats\nof IEEE 754 without, alas, adhering to the standard's way\nof handling rounding and exceptions like over/underflow.\nThe DEC VAX G_floating\\-point format is very similar to the IEEE\n754 Double format, so similar that the C programs for the\nIEEE versions of most of the elementary functions listed\nabove could easily be converted to run on a MicroVAX, though\nnobody has volunteered to do that yet.\n.PP\nThe codes in 4.3 BSD's \\fIlibm\\fR for machines that conform to\nIEEE 754 are intended primarily for the National Semi. 32081\nand WTL 1164/65.  To use these codes with the Intel or Zilog\nchips, or with the Apple Macintosh or ELXSI 6400, is to\nforego the use of better codes provided (perhaps freely) by\nthose companies and designed by some of the authors of the\ncodes above.\nExcept for \\fIatan\\fR, \\fIcabs\\fR, \\fIcbrt\\fR, \\fIerf\\fR,\n\\fIerfc\\fR, \\fIhypot\\fR, \\fIj0\\-jn\\fR, \\fIlgamma\\fR, \\fIpow\\fR\nand \\fIy0\\-yn\\fR,\nthe Motorola 68881 has all the functions in \\fIlibm\\fR on chip,\nand faster and more accurate;\nit, Apple, the i8087, Z8070 and WE32106 all use 64\n.if n \\\nsig.\n.if t \\\nsignificant\nbits.\nThe main virtue of 4.3 BSD's\n\\fIlibm\\fR codes is that they are intended for the public domain;\nthey may be copied freely provided their provenance is always\nacknowledged, and provided users assist the authors in their\nresearches by reporting experience with the codes.\nTherefore no user of UNIX on a machine that conforms to\nIEEE 754 need use anything worse than the new \\fIlibm\\fR.\n.PP\nProperties of IEEE 754 Double\\-Precision:\n.RS\nWordsize: 64 bits, 8 bytes.  Radix: Binary.\n.br\nPrecision: 53\n.if n \\\nsig.\n.if t \\\nsignificant\nbits, roughly like 16\n.if n \\\nsig.\n.if t \\\nsignificant\ndecimals.\n.RS\nIf x and x' are consecutive positive Double\\-Precision\nnumbers (they differ by 1 \\*(up), then\n.br\n1.1e\\-16 < 0.5**53 < (x'\\-x)/x \\(<= 0.5**52 < 2.3e\\-16.\n.RE\n.nf\n.ta \\w'Range:'u+1n +\\w'Underflow threshold'u+1n +\\w'= 2.0**1024'u+1n\nRange:\tOverflow threshold\t= 2.0**1024\t= 1.8e308\n\tUnderflow threshold\t= 0.5**1022\t= 2.2e\\-308\n.ta\n.fi\n.RS\nOverflow goes by default to a signed\n.If \"\" .\n.br\nUnderflow is \\fIGradual,\\fR rounding to the nearest\ninteger multiple of 0.5**1074 = 4.9e\\-324.\n.RE\nZero is represented ambiguously as +0 or \\-0.\n.RS\nIts sign transforms correctly through multiplication or\ndivision, and is preserved by addition of zeros\nwith like signs; but x\\-x yields +0 for every\nfinite x.  The only operations that reveal zero's\nsign are division by zero and copysign(x,\\(+-0).\nIn particular, comparison (x > y, x \\(>= y, etc.)\ncannot be affected by the sign of zero; but if\nfinite x = y then\n.If\n\\&= 1/(x\\-y)\n.if n \\\n!=\n.if t \\\n\\(!=\n\\-1/(y\\-x) =\n.If \\- .\n.RE\n.If\nis signed.\n.RS\nit persists when added to itself\nor to any finite number.  Its sign transforms\ncorrectly through multiplication and division, and\n.If (finite)/\\(+- \\0=\\0\\(+-0\n(nonzero)/0 =\n.If \\(+- .\nBut \n.if n \\\nInfinity\\-Infinity, Infinity\\(**0 and Infinity/Infinity\n.if t \\\n\\(if\\-\\(if, \\(if\\(**0 and \\(if/\\(if\nare, like 0/0 and sqrt(\\-3),\ninvalid operations that produce \\*(nn. ...\n.RE\nReserved operands:\n.RS\nthere are 2**53\\-2 of them, all\ncalled \\*(nn (\\fIN\\fRot \\fIa N\\fRumber).\nSome, called Signaling \\*(nns, trap any floating\\-point operation\nperformed upon them; they are used to mark missing\nor uninitialized values, or nonexistent elements\nof arrays.  The rest are Quiet \\*(nns; they are\nthe default results of Invalid Operations, and\npropagate through subsequent arithmetic operations.\nIf x\n.if n \\\n!=\n.if t \\\n\\(!=\nx then x is \\*(nn; every other predicate\n(x > y, x = y, x < y, ...) is FALSE if \\*(nn is involved.\n.br\nNOTE: Trichotomy is violated by \\*(nn.\n.RS\nBesides being FALSE, predicates that entail ordered\ncomparison, rather than mere (in)equality,\nsignal Invalid Operation when \\*(nn is involved.\n.RE\n.RE\nRounding:\n.RS\nEvery algebraic operation (+, \\-, \\(**, /,\n.if n \\\nsqrt)\n.if t \\\n\\(sr)\nis rounded by default to within half an \\*(up, and\nwhen the rounding error is exactly half an \\*(up then\nthe rounded value's least significant bit is zero.\nThis kind of rounding is usually the best kind,\nsometimes provably so; for instance, for every\nx = 1.0, 2.0, 3.0, 4.0, ..., 2.0**52, we find\n(x/3.0)\\(**3.0 == x and (x/10.0)\\(**10.0 == x and ...\ndespite that both the quotients and the products\nhave been rounded.  Only rounding like IEEE 754\ncan do that.  But no single kind of rounding can be\nproved best for every circumstance, so IEEE 754\nprovides rounding towards zero or towards\n.If +\nor towards\n.If \\-\nat the programmer's option.  And the\nsame kinds of rounding are specified for\nBinary\\-Decimal Conversions, at least for magnitudes\nbetween roughly 1.0e\\-10 and 1.0e37.\n.RE\nExceptions:\n.RS\nIEEE 754 recognizes five kinds of floating\\-point exceptions,\nlisted below in declining order of probable importance.\n.RS\n.nf\n.ta \\w'Invalid Operation'u+6n +\\w'Gradual Underflow'u+2n\nException\tDefault Result\n.tc \\(ru\n\t\t\n.tc\nInvalid Operation\t\\*(nn, or FALSE\n.if n \\{\\\nOverflow\t\\(+-Infinity\nDivide by Zero\t\\(+-Infinity \\}\n.if t \\{\\\nOverflow\t\\(+-\\(if\nDivide by Zero\t\\(+-\\(if \\}\nUnderflow\tGradual Underflow\nInexact\tRounded value\n.ta\n.fi\n.RE\nNOTE:  An Exception is not an Error unless handled\nbadly.  What makes a class of exceptions exceptional\nis that no single default response can be satisfactory\nin every instance.  On the other hand, if a default\nresponse will serve most instances satisfactorily,\nthe unsatisfactory instances cannot justify aborting\ncomputation every time the exception occurs.\n.RE\n.PP\nFor each kind of floating\\-point exception, IEEE 754\nprovides a Flag that is raised each time its exception\nis signaled, and stays raised until the program resets\nit.  Programs may also test, save and restore a flag.\nThus, IEEE 754 provides three ways by which programs\nmay cope with exceptions for which the default result\nmight be unsatisfactory:\n.IP 1) \\w'\\0\\0\\0\\0'u\nTest for a condition that might cause an exception\nlater, and branch to avoid the exception.\n.IP 2) \\w'\\0\\0\\0\\0'u\nTest a flag to see whether an exception has occurred\nsince the program last reset its flag.\n.IP 3) \\w'\\0\\0\\0\\0'u\nTest a result to see whether it is a value that only\nan exception could have produced.\n.RS\nCAUTION: The only reliable ways to discover\nwhether Underflow has occurred are to test whether\nproducts or quotients lie closer to zero than the\nunderflow threshold, or to test the Underflow\nflag.  (Sums and differences cannot underflow in\nIEEE 754; if x\n.if n \\\n!=\n.if t \\\n\\(!=\ny then x\\-y is correct to\nfull precision and certainly nonzero regardless of\nhow tiny it may be.)  Products and quotients that\nunderflow gradually can lose accuracy gradually\nwithout vanishing, so comparing them with zero\n(as one might on a VAX) will not reveal the loss.\nFortunately, if a gradually underflowed value is\ndestined to be added to something bigger than the\nunderflow threshold, as is almost always the case,\ndigits lost to gradual underflow will not be missed\nbecause they would have been rounded off anyway.\nSo gradual underflows are usually \\fIprovably\\fR ignorable.\nThe same cannot be said of underflows flushed to 0.\n.RE\n.PP\nAt the option of an implementor conforming to IEEE 754,\nother ways to cope with exceptions may be provided:\n.IP 4) \\w'\\0\\0\\0\\0'u\nABORT.  This mechanism classifies an exception in\nadvance as an incident to be handled by means\ntraditionally associated with error\\-handling\nstatements like \"ON ERROR GO TO ...\".  Different\nlanguages offer different forms of this statement,\nbut most share the following characteristics:\n.IP \\(em \\w'\\0\\0\\0\\0'u\nNo means is provided to substitute a value for\nthe offending operation's result and resume\ncomputation from what may be the middle of an\nexpression.  An exceptional result is abandoned.\n.IP \\(em \\w'\\0\\0\\0\\0'u\nIn a subprogram that lacks an error\\-handling\nstatement, an exception causes the subprogram to\nabort within whatever program called it, and so\non back up the chain of calling subprograms until\nan error\\-handling statement is encountered or the\nwhole task is aborted and memory is dumped.\n.IP 5) \\w'\\0\\0\\0\\0'u\nSTOP.  This mechanism, requiring an interactive\ndebugging environment, is more for the programmer\nthan the program.  It classifies an exception in\nadvance as a symptom of a programmer's error; the\nexception suspends execution as near as it can to\nthe offending operation so that the programmer can\nlook around to see how it happened.  Quite often\nthe first several exceptions turn out to be quite\nunexceptionable, so the programmer ought ideally\nto be able to resume execution after each one as if\nexecution had not been stopped.\n.IP 6) \\w'\\0\\0\\0\\0'u\n\\&... Other ways lie beyond the scope of this document.\n.RE\n.PP\nThe crucial problem for exception handling is the problem of\nScope, and the problem's solution is understood, but not\nenough manpower was available to implement it fully in time\nto be distributed in 4.3 BSD's \\fIlibm\\fR.  Ideally, each\nelementary function should act as if it were indivisible, or\natomic, in the sense that ...\n.IP i) \\w'iii)'u+2n\nNo exception should be signaled that is not deserved by\nthe data supplied to that function.\n.IP ii) \\w'iii)'u+2n\nAny exception signaled should be identified with that\nfunction rather than with one of its subroutines.\n.IP iii) \\w'iii)'u+2n\nThe internal behavior of an atomic function should not\nbe disrupted when a calling program changes from\none to another of the five or so ways of handling\nexceptions listed above, although the definition\nof the function may be correlated intentionally\nwith exception handling.\n.PP\nIdeally, every programmer should be able \\fIconveniently\\fR to\nturn a debugged subprogram into one that appears atomic to\nits users.  But simulating all three characteristics of an\natomic function is still a tedious affair, entailing hosts\nof tests and saves\\-restores; work is under way to ameliorate\nthe inconvenience.\n.PP\nMeanwhile, the functions in \\fIlibm\\fR are only approximately\natomic.  They signal no inappropriate exception except\npossibly ...\n.RS\nOver/Underflow\n.RS\nwhen a result, if properly computed, might have lain barely within range, and\n.RE\nInexact in \\fIcabs\\fR, \\fIcbrt\\fR, \\fIhypot\\fR, \\fIlog10\\fR and \\fIpow\\fR\n.RS\nwhen it happens to be exact, thanks to fortuitous cancellation of errors.\n.RE\n.RE\nOtherwise, ...\n.RS\nInvalid Operation is signaled only when\n.RS\nany result but \\*(nn would probably be misleading.\n.RE\nOverflow is signaled only when\n.RS\nthe exact result would be finite but beyond the overflow threshold.\n.RE\nDivide\\-by\\-Zero is signaled only when\n.RS\na function takes exactly infinite values at finite operands.\n.RE\nUnderflow is signaled only when\n.RS\nthe exact result would be nonzero but tinier than the underflow threshold.\n.RE\nInexact is signaled only when\n.RS\ngreater range or precision would be needed to represent the exact result.\n.RE\n.RE\n.SH BUGS\nWhen signals are appropriate, they are emitted by certain\noperations within the codes, so a subroutine\\-trace may be\nneeded to identify the function with its signal in case\nmethod 5) above is in use.  And the codes all take the\nIEEE 754 defaults for granted; this means that a decision to\ntrap all divisions by zero could disrupt a code that would\notherwise get correct results despite division by zero.\n.SH SEE ALSO\nAn explanation of IEEE 754 and its proposed extension p854\nwas published in the IEEE magazine MICRO in August 1984 under\nthe title \"A Proposed Radix\\- and Word\\-length\\-independent\nStandard for Floating\\-point Arithmetic\" by W. J. Cody et al.\nThe manuals for Pascal, C and BASIC on the Apple Macintosh\ndocument the features of IEEE 754 pretty well.\nArticles in the IEEE magazine COMPUTER vol. 14 no. 3 (Mar.\n1981), and in the ACM SIGNUM Newsletter Special Issue of\nOct. 1979, may be helpful although they pertain to\nsuperseded drafts of the standard.\n.SH AUTHOR\nW. Kahan, with the help of Z\\-S. Alex Liu, Stuart I. McDonald,\nDr. Kwok\\-Choi Ng, Peter Tang.\n"
  },
  {
    "path": "share/man/man3/mktemp.3",
    "content": ".\\\"\t@(#)mktemp.3\t6.3 (Berkeley) 4/10/87\n.\\\"\n.TH MKTEMP 3  \"April 10, 1987\"\n.AT 3\n.SH NAME\nmktemp \\- make a unique file name\n.SH SYNOPSIS\n.nf\n.B char *mktemp(template)\n.B char *template;\n.sp\n.B mkstemp(template)\n.B char *template;\n.fi\n.SH DESCRIPTION\n\\fIMktemp\\fP creates a unique file name and returns the address of\nthe template.  The template should contain a file name with trailing\n\\fIX\\fP's, normally something like \\fI/tmp/tempXXXXXX\\fP.  The \\fIX\\fP's\nare replaced by the current process number and/or a unique letter\ncombination.  \\fIMkstemp\\fP makes the same replacement to the template\nbut opens the template file and returns a file descriptor open for\nreading and writing.  \\fIMkstemp\\fP avoids the race between testing\nwhether the file exists and opening it for use.  The number of file\nname combinations \\fImktemp\\fP and \\fImkstemp\\fP will try depends on\nthe number of \\fIX\\fP's placed on the end of the template; six \\fIX\\fP's\nwill result in them trying roughly 26 ** 6 combinations.\n.SH \"SEE ALSO\"\naccess(2), getpid(2), open(2)\n.SH DIAGNOSTICS\n\\fIMktemp\\fP returns NULL on failure, \\fImkstemp\\fP returns -1 if no\nsuitable file could be created.\n"
  },
  {
    "path": "share/man/man3/monitor.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)monitor.3\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH MONITOR 3  \"May 15, 1985\"\n.UC 4\n.SH NAME\nmonitor, monstartup, moncontrol \\- prepare execution profile\n.SH SYNOPSIS\n.nf\n.B monitor(lowpc, highpc, buffer, bufsize, nfunc)\n.B int (*lowpc)(), (*highpc)();\n.B short buffer[];\n.sp\n.B monstartup(lowpc, highpc)\n.B int (*lowpc)(), (*highpc)();\n.sp\n.B moncontrol(mode)\n.fi\n.SH DESCRIPTION\nThere are two different forms of monitoring available:\nAn executable program created by:\n.IP  \"\tcc \\-p . . .\"\n.LP\nautomatically includes calls for the \n.IR prof (1)\nmonitor and includes an initial call to its start-up routine\n.I monstartup\nwith default parameters;\n.I monitor\nneed not be called explicitly except to gain fine control over profil \nbuffer allocation.\nAn executable program created by:\n.IP  \"\tcc \\-pg . . .\"\n.LP\nautomatically includes calls for the\n.IR gprof (1)\nmonitor.\n.PP\n.I Monstartup\nis a high level interface to\n.IR profil (2).\n.I Lowpc\nand\n.I highpc\nspecify the address range that is to be sampled; the lowest address sampled\nis that of\n.I lowpc\nand the highest is just below\n.IR highpc .\n.I Monstartup\nallocates space using \n.IR sbrk (2)\nand passes it to\n.I monitor\n(see below) to record a histogram of periodically sampled values of\nthe program counter, and of counts of calls of certain functions, in the buffer.\nOnly calls of functions compiled with the profiling option\n.B \\-p\nof\n.IR cc (1)\nare recorded.\n.PP\nTo profile the entire program, it is sufficient to use\n.PP\n.nf\n\textern etext();\n\t. . .\n\tmonstartup((int) 2, etext);\n.fi\n.PP\n.I Etext\nlies just above all the program text, see\n.IR end (3).\n.PP\nTo stop execution monitoring and write the results on the file\n.I mon.out,\nuse\n.PP\n\tmonitor(0);\n.LP\nthen\n.IR prof (1)\ncan be used to examine the results.\n.PP\n.I Moncontrol\nis used to selectively control profiling within a program.\nThis works with either \n.IR prof (1)\nor\n.IR gprof (1)\ntype profiling.\nWhen the program starts, profiling begins.\nTo stop the collection of histogram ticks and call counts use\n.IR moncontrol (0);\nto resume the collection of histogram ticks and call counts use\n.IR moncontrol (1).\nThis allows the cost of particular operations to be measured.\nNote that an output file will be produced upon program exit\nirregardless of the state of \n.I moncontrol.\n.PP\n.I Monitor\nis a low level interface to\n.IR profil (2).\n.I Lowpc\nand\n.I highpc\nare the addresses of two functions;\n.I buffer\nis the address of a (user supplied) array of\n.I bufsize\nshort integers.  At most\n.I nfunc\ncall counts can be kept.\nFor the results to be significant, especially where there are small, heavily\nused routines, it is suggested that the buffer be no more\nthan a few times smaller than the range of locations sampled.\n.I Monitor\ndivides the buffer into space to record the histogram\nof program counter samples over the range\n.I lowpc\nto\n.IR highpc ,\nand space to record call counts of functions compiled with the \n.B \\-p\noption to\n.IR cc (1).\n.PP\nTo profile the entire program, it is sufficient to use\n.PP\n.nf\n\textern etext();\n\t. . .\n\tmonitor((int) 2, etext, buf, bufsize, nfunc);\n.fi\n.SH FILES\nmon.out\n.SH \"SEE ALSO\"\ncc(1), prof(1), gprof(1), profil(2), sbrk(2)\n"
  },
  {
    "path": "share/man/man3/mp.3",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)mp.3x\t6.4 (Berkeley) 6/4/86\n.\\\"\n.TH MP 3X \"June 4, 1986\"\n.UC 6\n.SH NAME\nmadd, msub, mult, mdiv, pow, gcd, invert, rpow, msqrt, mcmp,\nmove, min, omin, fmin, m_in, mout, omout, fmout, m_out, sdiv, itom\n\\- multiple precision integer arithmetic\n.SH SYNOPSIS\n.nf\n.B #include <mp.h>\n.B #include <stdio.h>\n.PP\n.B \"typedef struct mint { int len; short *val; } MINT;\"\n.PP\n.B madd(a, b, c)\n.B msub(a, b, c)\n.B mult(a, b, c)\n.B mdiv(a, b, q, r)\n.B pow(a, b, m, c)\n.B gcd(a, b, c)\n.B invert(a, b, c)\n.B rpow(a, n, c)\n.B msqrt(a, b, r)\n.B mcmp(a, b)\n.B move(a, b)\n.B min(a)\n.B omin(a)\n.B fmin(a, f)\n.B m_in(a, n, f)\n.B mout(a)\n.B omout(a)\n.B fmout(a, f)\n.B m_out(a, n, f)\n.B MINT *a, *b, *c, *m, \"*q, *r;\"\n.B FILE *f;\n.B int n;\n.PP\n.B sdiv(a, n, q, r)\n.B MINT *a, *q;\n.B short n;\n.B short *r;\n.PP\n.B MINT *itom(n)\n.SH DESCRIPTION\nThese routines perform arithmetic on integers of\narbitrary length.\nThe integers are stored using the defined type\n.IR MINT .\nPointers to a\n.I MINT\ncan be initialized using the function\n.I itom\nwhich sets the initial value to\n.IR n .\nAfter that, space is managed automatically by the routines.\n.PP\n.IR madd , \" msub \" and \" mult\"\nassign to\n.I c\nthe sum, difference and\nproduct, respectively, of\n.IR a \" and \" b .\n.I mdiv\nassigns to\n.IR q \" and \" r\nthe quotient and remainder obtained\nfrom dividing\n.IR a \" by \" b.\n.I sdiv\nis like\n.I mdiv\nexcept that the divisor is a short integer\n.I n\nand the remainder is placed in a short\nwhose address is given as\n.IR r .\n.I msqrt\nproduces the integer square root of\n.IR a \" in \" b\nand places the remainder in\n.IR r .\n.I rpow\ncalculates in\n.I c\nthe value of\n.I a\nraised to the (``regular'' integral) power\n.IR n ,\nwhile\n.I pow\ncalculates this with a full multiple precision exponent\n.I b\nand the result is reduced modulo\n.IR m .\n.I gcd\nreturns the greatest common denominator of\n.IR a \" and \" b \" in \" c ,\nand\n.I invert\ncomputes\n.IR c \" such that \" a*c \" mod \" b \" = 1,\"\nfor\n.IR a \" and \" b\nrelatively prime.\n.I mcmp\nreturns a negative, zero or positive integer value when\n.I a\nis less than, equal to or greater than\n.IR b ,\nrespectively.\n.I move\ncopies\n.IR a \" to \" b .\n.IR min \" and \" mout\ndo decimal input and output while\n.IR omin \" and \" omout\ndo octal input and output.\nMore generally,\n.IR fmin \" and \" fmout\ndo decimal input and output using file\n.IR f ,\nand\n.IR m_in \" and \" m_out\ndo I/O with arbitrary radix\n.IR n .\nOn input, records should have the form of\nstrings of digits terminated by a newline;\noutput records have a similar form.\n.PP\nPrograms which use the multiple-precision arithmetic library\nmust be loaded using the loader flag\n.IR \\-lmp .\n.SH FILES\n.ta 2i\n/usr/include/mp.h\tinclude file\n.br\n/usr/lib/libmp.a\tobject code library\n.SH SEE ALSO\ndc(1), bc(1)\n.SH DIAGNOSTICS\nIllegal operations and running out of memory\nproduce messages and core images.\n.SH BUGS\nBases for input and output should be <= 10.\n.PP\n.IR dc (1)\nand\n.IR bc (1)\ndon't use this library.\n.PP\nThe input and output routines are a crock.\n.PP\n.I pow\nis also the name of a standard math library routine.\n"
  },
  {
    "path": "share/man/man3/ndbm.3",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ndbm.3\t6.6 (Berkeley) 5/20/86\n.\\\"\n.TH NDBM 3  \"May 20, 1986\"\n.UC 6\n.SH NAME\ndbm_open, dbm_close, dbm_fetch, dbm_store, dbm_delete, dbm_firstkey, dbm_nextkey, dbm_error, dbm_clearerr \\- data base subroutines\n.SH SYNOPSIS\n.nf\n.PP\n.ft B\n#include <ndbm.h>\n.PP\n.ft B\ntypedef struct {\n    char *dptr;\n    int dsize;\n} datum;\n.PP\n.ft B\nDBM *dbm_open(file, flags, mode)\n    char *file;\n    int flags, mode;\n.PP\n.ft B\nvoid dbm_close(db)\n    DBM *db;\n.PP\n.ft B\ndatum dbm_fetch(db, key)\n    DBM *db;\n    datum key;\n.PP\n.ft B\nint dbm_store(db, key, content, flags)\n    DBM *db;\n    datum key, content;\n    int flags;\n.PP\n.ft B\nint dbm_delete(db, key)\n    DBM *db;\n    datum key;\n.PP\n.ft B\ndatum dbm_firstkey(db)\n    DBM *db;\n.PP\n.ft B\ndatum dbm_nextkey(db)\n    DBM *db;\n.PP\n.ft B\nint dbm_error(db)\n    DBM *db;\n.PP\n.ft B\nint dbm_clearerr(db)\n    DBM *db;\n.SH DESCRIPTION\nThese functions maintain key/content pairs in a data base.\nThe functions will handle very large (a billion blocks)\ndatabases and will access a keyed item in one or two file system accesses.\nThis package replaces the earlier\n.IR dbm (3x)\nlibrary, which managed only a single database.\n.PP\n.IR Key s\nand\n.IR content s\nare described by the\n.I datum\ntypedef.  A\n.I datum\nspecifies a string of\n.I dsize\nbytes pointed to by\n.I dptr.\nArbitrary binary data, as well as normal ASCII strings, are allowed.\nThe data base is stored in two files.\nOne file is a directory containing a bit map and has `.dir' as its suffix.\nThe second file contains all data and has `.pag' as its suffix.\n.PP\nBefore a database can be accessed, it must be opened by\n.IR dbm_open .\nThis will open and/or create the files\n.IB file .dir\nand\n.IB file .pag\ndepending on the flags parameter (see\n.IR open (2)).\n.PP\nOnce open, the data stored under a key is accessed by\n.I dbm_fetch\nand data is placed under a key by\n.IR dbm_store .\nThe\n.I flags\nfield can be either\n.B DBM_INSERT\nor\n.B DBM_REPLACE.\n.B DBM_INSERT\nwill only insert new entries into the database and will not\nchange an existing entry with the same key.\n.B DBM_REPLACE\nwill replace an existing entry if it has the same key.\nA key (and its associated contents) is deleted by\n.IR dbm_delete .\nA linear pass through all keys in a database may be made,\nin an (apparently) random order, by use of\n.I dbm_firstkey\nand\n.IR dbm_nextkey .\n.I Dbm_firstkey\nwill return the first key in the database.\n.I Dbm_nextkey\nwill return the next key in the database.\nThis code will traverse the data base:\n.IP\n.B for\n(key = dbm_firstkey(db); key.dptr != NULL; key = dbm_nextkey(db))\n.PP\n.I Dbm_error\nreturns non-zero when an error has occurred reading or writing the database.\n.I Dbm_clearerr\nresets the error condition on the named database.\n.SH DIAGNOSTICS\nAll functions that return an\n.I int\nindicate errors with negative values.  A zero return indicates ok.\nRoutines that return a\n.I datum\nindicate errors with a null (0)\n.I dptr.\nIf\n.IR dbm_store\ncalled with a\n.I flags\nvalue of\n.B DBM_INSERT\nfinds an existing entry with the same key\nit returns 1.\n.SH BUGS\nThe `.pag' file will contain holes so that its apparent size is about\nfour times its actual content.  Older UNIX systems may create real\nfile blocks for these holes when touched.  These files cannot be copied\nby normal means (cp, cat, tp, tar, ar) without filling in the holes.\n.PP\n.I Dptr\npointers returned by these subroutines point into static storage\nthat is changed by subsequent calls.\n.PP\nThe sum of the sizes of a key/content pair must not exceed\nthe internal block size (currently 4096 bytes).\nMoreover all key/content pairs that hash together must fit on a single block.\n.I Dbm_store\nwill return an error in the event that a disk block fills with inseparable data.\n.PP\n.I Dbm_delete\ndoes not physically reclaim file space,\nalthough it does make it available for reuse.\n.PP\nThe order of keys presented by\n.I dbm_firstkey\nand\n.I dbm_nextkey\ndepends on a hashing function, not on anything interesting.\n.SH SEE ALSO\ndbm(3X)\n"
  },
  {
    "path": "share/man/man3/nice.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)nice.3c\t6.1 (Berkeley) 5/9/85\n.\\\"\n.TH NICE 3C \"May 9, 1985\"\n.UC 4\n.SH NAME\nnice \\- set program priority\n.SH SYNOPSIS\n.B nice(incr)\n.SH DESCRIPTION\n.ft B\nThis interface is obsoleted by setpriority(2).\n.ft R\n.PP\nThe scheduling\npriority of the process is augmented by\n.IR incr .\nPositive priorities get less\nservice than normal.\nPriority 10 is recommended to users\nwho wish to execute long-running programs\nwithout flak from the administration.\n.PP\nNegative increments are ignored except on behalf of \nthe super-user.\nThe priority is limited to the range\n\\-20 (most urgent) to 20 (least).\n.PP\nThe priority of a process is\npassed to a child process by\n.IR fork (2).\nFor a privileged process to return to normal priority\nfrom an unknown state,\n.I nice\nshould be called successively with arguments\n\\-40 (goes to priority \\-20 because of truncation),\n20 (to get to 0),\nthen 0 (to maintain compatibility with previous versions\nof this call).\n.SH \"SEE ALSO\"\nnice(1), setpriority(2), fork(2), renice(8)\n"
  },
  {
    "path": "share/man/man3/nlist.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)nlist.3\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH NLIST 3  \"May 15, 1985\"\n.UC 4\n.SH NAME\nnlist \\- get entries from name list\n.SH SYNOPSIS\n.nf\n.B #include <nlist.h>\n.PP\n.B nlist(filename, nl)\n.B char *filename;\n.B struct nlist nl[];\n.fi\n.SH DESCRIPTION\n.I Nlist\nexamines the name list in the given executable output file\nand selectively extracts a list of values.\nThe name list consists of an array of structures containing names,\ntypes and values.\nThe list is terminated with a null name.\nEach name is looked up in the name list of the file.\nIf the name is found, the type and value of the\nname are inserted in the next two fields.\nIf the name is not found, both entries are set to 0.\nSee\n.IR a.out (5)\nfor the structure declaration.\n.PP\nThis subroutine is useful for examining the system name list kept in the file\n.BR /vmunix .\nIn this way programs can obtain system addresses that are up to date.\n.SH \"SEE ALSO\"\na.out(5)\n.SH DIAGNOSTICS\nIf the file cannot be found or if it is not a valid namelist \\-1 is returned;\notherwise, the number of unfound namelist entries is returned.\n.PP\nThe type entry is set to 0 if the symbol is not found.\n"
  },
  {
    "path": "share/man/man3/ns.3",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ns.3n\t6.2 (Berkeley) 5/12/86\n.\\\"\n.TH NS 3N \"May 12, 1986\"\n.UC 6\n.SH NAME\nns_addr, ns_ntoa \\- Xerox NS(tm)  address conversion routines\n.SH SYNOPSIS\n.nf\n.B \"#include <sys/types.h>\n.B \"#include <netns/ns.h>\n.PP\n.B \"struct ns_addr ns_addr(cp)\n.B \"char *cp;\n.PP\n.B \"char *ns_ntoa(ns)\n.B \"struct ns_addr ns;\n.fi\n.SH DESCRIPTION\nThe routine\n.I ns_addr\ninterprets character strings representing\nXNS addresses, returning binary information suitable\nfor use in system calls.\n.I ns_ntoa\ntakes XNS addresses and returns ASCII\nstrings representing the address in a\nnotation in common use in the Xerox Development Environment:\n.nf\n\t<network number>.<host number>.<port number>\n.fi\nTrailing zero fields are suppressed, and each number is printed in hexadecimal,\nin a format suitable for input to \n.IR ns_addr .\nAny fields lacking super-decimal digits will have a\ntrailing ``H'' appended.\n.PP\nUnfortunately, no universal standard exists for representing XNS addresses.\nAn effort has been made to insure that\n.I ns_addr\nbe compatible with most formats in common use.\nIt will first separate an address into 1 to 3 fields using a single delimiter\nchosen from\nperiod (``.''),\ncolon (``:'') or pound-sign (``#'').\nEach field is then examined for byte separators (colon or period).\nIf there are byte separators, each subfield separated is taken to be\na small hexadecimal number, and the entirety is taken as a network-byte-ordered\nquantity to be zero extended in the high-network-order bytes.\nNext, the field is inspected for hyphens, in which case\nthe field is assumed to be a number in decimal notation\nwith hyphens separating the millenia.\nNext, the field is assumed to be a number:\nIt is interpreted\nas hexadecimal if there is a leading ``0x'' (as in C),\na trailing ``H'' (as in Mesa), or there are any super-decimal digits present.\nIt is interpreted as octal is there is a leading ``0''\nand there are no super-octal digits.\nOtherwise, it is converted as a decimal number.\n.SH \"SEE ALSO\"\nhosts(5), networks(5),\n.SH DIAGNOSTICS\nNone (see BUGS).\n.SH BUGS\nThe string returned by\n.I ns_ntoa\nresides in a static memory area.\n.br\n.I ns_addr\nshould diagnose improperly formed input, and there should be an unambiguous\nway to recognize this.\n"
  },
  {
    "path": "share/man/man3/pause.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)pause.3c\t6.1 (Berkeley) 5/9/85\n.\\\"\n.TH PAUSE 3C \"May 9, 1985\"\n.UC 4\n.SH NAME\npause \\- stop until signal\n.SH SYNOPSIS\n.B pause()\n.SH DESCRIPTION\n.I Pause\nnever returns normally.\nIt is used to give up control while waiting for\na signal from\n.IR kill (2)\nor an interval timer, see\n.IR setitimer (2).\nUpon termination of a signal handler started during a\n.I pause,\nthe\n.I pause\ncall will return.\n.SH \"RETURN VALUE\nAlways returns \\-1.\n.SH ERRORS\n.I Pause\nalways returns:\n.TP 15\n[EINTR]\nThe call was interrupted.\n.SH \"SEE ALSO\nkill(2), select(2), sigpause(2)\n"
  },
  {
    "path": "share/man/man3/perror.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)perror.3\t6.1.1 (2.11BSD) 1996/3/21\n.\\\"\n.TH PERROR 3  \"March 21, 1996\"\n.UC 4\n.SH NAME\nperror, strerror \\- system error messages\n.SH SYNOPSIS\n.nf\n.B perror(s)\n.B char *s;\n.sp\n.B #include <string.h>\n.sp\n.I char *\n.B strerror(errnum)\n.B int errnum;\n.fi\n.SH DESCRIPTION\nThe\n.B strerror()\nand\n.B perror()\nfunctions look up the error message string corresponding to an error number.\n.PP\nThe \n.B strerror()\nfunction accepts an error number argument\n.I errnum\nand returns a pointer to the corresponding message string.\n.PP\nThe\n.B perror()\nfunction\nfinds the error message corresponding to the current value of the\nglobal variable\n.I errno\n(intro(2)) and writes it, followed by a newline, to the standard error\nfile descriptor.  If the argument \n.I string\nis non-NULL, it is prepended to the message string and separated\nfrom it by a colon and space (`: ').\nIf \n.I string\nis NULL, only the error message string is printed.\n.PP\nIf\n.I errnum\nis not a recognized error number, the error message string\nwill contain ``Unknown error: '' followed by the error number\nin decimal.\n.PP\nThe error messages are stored in a data file now rather than an in memory\narray.  See \n.BR syserror (5).\n.SH \"SEE ALSO\"\nmkerrlst(1),\nintro(2),\npsignal(3),\nstrerror(3),\nsyserror(3),\nsyserror(5)\n.SH BUGS\nThe\n.BR strerror ()\nfunction returns its result in a static buffer which may be\noverwritten by subsequent calls.\n.PP\nThe array\n.B sys_errlist[]\nand the global\n.B sys_nerr\nare\n.B obsolete\nand should not be used.  They have, for the time being, been placed in\nan object library \n.BR liberrlst.a .\n"
  },
  {
    "path": "share/man/man3/plot.3",
    "content": ".\\\"\t@(#)plot.3x\t6.2 (Berkeley) 5/15/86\n.\\\"\n.TH PLOT 3X  \"May 15, 1986\"\n.AT 3\n.SH NAME\nplot: openpl, erase, label, line, circle, arc, move, cont, point, linemod, space, closepl \\- graphics interface\n.SH SYNOPSIS\n.nf\n.B openpl()\n.PP\n.B erase()\n.PP\n.B label(s)\n.B char s[];\n.PP\n.B line(x1, y1, x2, y2)\n.PP\n.B circle(x, y, r)\n.PP\n.B arc(x, y, x0, y0, x1, y1)\n.PP\n.B move(x, y)\n.PP\n.B cont(x, y)\n.PP\n.B point(x, y)\n.PP\n.B linemod(s)\n.B char s[];\n.PP\n.B space(x0, y0, x1, y1)\n.PP\n.B closepl()\n.fi\n.PP\n.ft R\n.SH DESCRIPTION\nThese subroutines generate graphic output in a relatively\ndevice-independent manner.  See\n.IR  plot (5)\nfor a description of their effect.\n.I Openpl\nmust be used before any of the others to open the device for writing.\n.I Closepl\nflushes the output.\n.PP\nString arguments to\n.I label\nand\n.I linemod\nare null-terminated, and do not contain newlines.\n.PP\nVarious flavors of these functions exist for different output devices. \nThey are obtained by the following\n.IR ld (1)\noptions:\n.TP 8n\n.B \\-lplot\ndevice-independent graphics stream on standard output for \n.IR plot (1)\nfilters\n.br\n.ns\n.TP\n.B \\-l300\nGSI 300 terminal\n.br\n.ns\n.TP\n.B \\-l300s\nGSI 300S terminal\n.br\n.ns\n.TP\n.B \\-l450\nGSI 450 terminal\n.br\n.ns\n.TP\n.B \\-l4013\nTektronix 4013 terminal\n.br\n.ns\n.TP\n.B \\-l4014\nTektronix 4014 and 4015 terminals with the Enhanced Graphics Module (Use\n.B \\-l4013\nfor 4014's or 4015's without the Enhanced Graphics Module)\n.br\n.ns\n.TP\n.B \\-lplotaed\nAED 512 color graphics terminal\n.br\n.ns\n.TP\n.B \\-lplotbg\nBBN bitgraph graphics terminal\n.br\n.ns\n.TP\n.B \\-lplotdumb\nDumb terminals without cursor addressing or line printers\n.br\n.ns\n.TP\n.B \\-lplot\nDEC Gigi terminals\n.br\n.ns\n.TP\n.B \\-lvt0\nDEC vt100 terminals\n.br\n.ns\n.TP\n.B \\-lplot2648\nHewlett Packard 2648 graphics terminal\n.br\n.ns\n.TP\n.B \\-lplot7221\nHewlett Packard 7221 graphics terminal\n.br\n.ns\n.TP\n.B \\-lplotimagen\nImagen laser printer (default 240 dots-per-inch resolution).\n.PP\nOn many devices, it is necessary to pause after\n.IR erase (),\notherwise plotting commands are lost.\nThe pause is normally done by the tty driver if at login time,\n.I tset\nfound a\n.I df\nfield in the\n.IR termcap (5)\nentry for the terminal.\nIf a pause is needed but not automatically being generated,\nadd\n.RS\n.nf\nflush(stdout);\nsleep(1);\n.fi\n.RE\nafter each\n.IR erase ().\n.SH \"SEE ALSO\"\nplot(5), plot(1G), plot(3F), graph(1G)\n"
  },
  {
    "path": "share/man/man3/popen.3",
    "content": ".\\\"\t@(#)popen.3\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH POPEN 3 \"May 15, 1985\"\n.AT 3\n.SH NAME\npopen, pclose \\- initiate I/O to/from a process\n.SH SYNOPSIS\n.B #include <stdio.h>\n.PP\n.SM\n.B FILE\n.B *popen(command, type)\n.br\n.B char *command, *type;\n.PP\n.B pclose(stream)\n.br\n.SM\n.B FILE\n.B *stream;\n.SH DESCRIPTION\nThe arguments to \n.I popen\nare pointers to null-terminated strings containing respectively a\nshell command line and an I/O mode, either \"r\" for reading or \"w\" for\nwriting.  It creates a pipe between the calling process and\nthe command to be executed.  The value returned is a stream pointer that\ncan be used (as appropriate) to write to the standard input\nof the command or read from its standard output.\n.PP\nA stream opened by\n.I popen\nshould be closed by\n.IR pclose ,\nwhich waits for the associated process to terminate\nand returns the exit status of the command.\n.PP\nBecause open files are shared, a type \"r\" command may be used as an input\nfilter, and a type \"w\" as an output filter.\n.SH \"SEE ALSO\"\npipe(2),\nfopen(3S),\nfclose(3S),\nsystem(3),\nwait(2),\nsh(1)\n.SH DIAGNOSTICS\n.I Popen\nreturns a null pointer if files or processes cannot be created, or the shell \ncannot be accessed.\n.PP\n.I Pclose\nreturns \\-1 if\n.I stream\nis not associated with a `popened' command.\n.SH BUGS\nBuffered reading before opening an input filter\nmay leave the standard input of that filter mispositioned.\nSimilar problems with an output filter may be\nforestalled by careful buffer flushing, for instance, with\n.I fflush,\nsee\n.IR fclose (3S).\n.LP\n.I Popen\nalways calls\n.IR sh ,\nnever calls\n.IR csh .\n"
  },
  {
    "path": "share/man/man3/printf.3",
    "content": ".\\\"\t@(#)printf.3s\t6.5.1 (2.11BSD) 1995/04/02\n.\\\"\n.TH PRINTF 3S \"August 10, 1988\"\n.AT 3\n.SH NAME\nprintf, fprintf, sprintf, vfprintf, vsprintf \\- formatted output conversion\n.SH SYNOPSIS\n.B #include <stdio.h>\n.PP\n.B char *printf(format\n.RB [ ,\narg ] ...\n.B )\n.br\n.B char *format;\n.PP\n.B char *fprintf(stream, format\n.RB [ ,\narg ] ...\n.B )\n.br\n.SM\n.B FILE\n.B *stream;\n.br\n.B char *format;\n.PP\n.B int sprintf(s, format\n.RB [ ,\narg ] ...\n.B )\n.br\n.B char *s, *format;\n.PP\n.B #include <varargs.h>\n.br\n.B char *vprintf(format, args)\n.br\n.B char *format;\n.br\n.B va_list args;\n.PP\n.B char *vfprintf(stream, format, args)\n.br\n.B FILE *stream;\n.br\n.B char *format;\n.br\n.B va_list args;\n.PP\n.B int vsprintf(s, format, args)\n.br\n.B char *s, *format;\n.br\n.B va_list args;\n.SH DESCRIPTION\n.I Printf\nplaces output on the standard output stream\n.BR stdout .\n.I Fprintf\nplaces output on the named output\n.IR stream .\n.I Sprintf\nplaces `output' in the string\n.IR s ,\nfollowed by the character `\\\\0'.\nAlternate forms, in which the arguments have already been\ncaptured using the variable-length argument facilities of\n.IR varargs (3),\nare available under the names\n.IR vprintf ,\n.IR vfprintf ,\nand\n.IR vsprintf .\n.PP\nEach of these functions converts, formats, and prints its arguments after\nthe first under control of the first argument.\nThe first argument is a character string which contains two types of objects:\nplain characters, which are simply copied to the output stream,\nand conversion specifications, each of which causes conversion and printing\nof the next successive\n.I arg\n.IR printf .\n.PP\nEach conversion specification is introduced by the character\n.BR % .\nThe remainder of the conversion specification includes\nin the following order\n.TP\n.B \\(bu\na minus sign `\\-' which specifies\n.I \"left adjustment\"\nof the converted value in the indicated field;\n.TP\n.B \\(bu\nan optional digit string specifying a\n.I \"field width;\"\nif the converted value has fewer characters than the field width\nit will be blank-padded on the left (or right,\nif the left-adjustment indicator has been given) to make up the field width;\nif the field width begins with a zero,\nzero-padding will be done instead of blank-padding;\n.TP\n.B \\(bu\nan optional period, followed by\nan optional digit string giving a\n.I precision\nwhich specifies the number of digits to appear after the\ndecimal point, for e- and f-conversion, or the maximum number of characters\nto be printed from a string;\n.TP\n.B \\(bu\nthe character\n.B l\nspecifying that a following\n.BR d ,\n.BR o ,\n.BR x ,\nor\n.B u\ncorresponds to a long integer\n.IR arg ;\n.TP\n.B \\(bu\na character which indicates the type of\nconversion to be applied.\n.PP\nA field width or precision may be `*' instead of a digit string.\nIn this case an integer\n.I arg\nsupplies\nthe field width or precision.\n.PP\nThe conversion characters\nand their meanings are\n.TP\n.B dox\nThe integer\n.I arg\nis converted to signed decimal, unsigned octal, or\nunsigned hexadecimal notation respectively.\n.TP\n.B f\nThe float or double\n.I arg\nis converted to decimal notation\nin the style `[\\fB\\-\\fR]ddd.ddd'\nwhere the number of d's after the decimal point\nis equal to the precision specification\nfor the argument.\nIf the precision\nis missing,\n6 digits are given;\nif the precision is explicitly 0, no digits and\nno decimal point are printed.\n.TP\n.B e\nThe float or double\n.I arg\nis converted in the style\n`[\\fB\\-\\fR]d\\fB.\\fRddd\\fBe\\fR\\(+-dd'\nwhere there is one digit before the decimal point and\nthe number after is equal to the\nprecision specification for the argument;\nwhen the precision is missing,\n6 digits are produced.\n.TP\n.B g\nThe float or double\n.I arg\nis printed in style\n.BR d ,\nin style\n.BR f ,\nor in\nstyle\n.BR e ,\nwhichever gives full precision in minimum space.\n.TP\n.B c\nThe character\n.I arg\nis printed.\n.TP\n.B s\n.I Arg\nis taken to be a string (character pointer)\nand characters from the string are printed until\na null character or until\nthe number of characters indicated by the precision\nspecification is reached;\nhowever if the precision is 0 or missing\nall characters up to a null are printed.\n.TP\n.B u\nThe unsigned integer\n.I arg\nis converted to decimal\nand printed (the result will be in the\nrange 0 through MAXUINT, where MAXUINT equals 4294967295 on a VAX-11\nand 65535 on a PDP-11).\n.TP\n.B %\nPrint a `%'; no argument is converted.\n.PP\nIn no case does a non-existent or small field width\ncause truncation of a field;\npadding takes place only if the specified field\nwidth exceeds the actual width.\nCharacters generated by\n.I printf\nare printed as by \n.IR putc (3S).\n.PP\n.SH \"RETURN VALUE\"\nThe functions all return\nthe number of characters printed, or -1 if an error occurred.\n.SH EXAMPLES\n.br\nTo print a date and time in the form `Sunday, July 3, 10:02',\nwhere\n.I weekday\nand\n.I month\nare pointers to null-terminated strings:\n.RS\n.HP\n.nh\nprintf(\"%s, %s %d, %02d:%02d\", weekday, month, day, hour, min);\n.RE\n.hy\n.PP\nTo print\n.if n pi\n.if t \\(*p\nto 5 decimals:\n.IP\nprintf(\"pi = %.5f\", 4*atan(1.0));\n.SH \"SEE ALSO\"\nputc(3S), scanf(3S)\n.SH BUGS\nVery wide fields (>300 characters) fail.\n.LP\nOnly \\fIsprintf\\fP and \\fIvsprintf\\fP return a count of characters \ntransferred.\n.LP\nThe functions still supports \\fI%D\\fP, \\fI%O\\fP, \\fI%U\\fP and \n\\fI%X\\fP.  Do not\nuse these formats, as they will be disappearing real soon now.\n"
  },
  {
    "path": "share/man/man3/psignal.3",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)psignal.3\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH PSIGNAL 3 \"May 15, 1985\"\n.UC 5\n.SH NAME\npsignal, sys_siglist \\- system signal messages\n.SH SYNOPSIS\n.nf\n.B psignal(sig, s)\n.B unsigned sig;\n.B char *s;\n.PP\n.B char *sys_siglist[];\n.fi\n.SH DESCRIPTION\n.I Psignal\nproduces a short message\non the standard error file\ndescribing the indicated signal.\nFirst the argument string\n.I s\nis printed, then a colon, then the name of the signal\nand a new-line.\nMost usefully, the argument string is the name\nof the program which incurred the signal.\nThe signal number should be from among those found\nin\n.IR <signal.h> .\n.PP\nTo simplify variant formatting\nof signal names, the vector of message strings\n.I sys_siglist\nis provided;\nthe signal number\ncan be used as an index in this table to get the\nsignal name without the newline.\nThe define NSIG defined in\n.RI < signal.h >\nis the number of messages provided for in the table;\nit should be checked because new\nsignals may be added to the system before\nthey are added to the table.\n.SH \"SEE ALSO\"\nsigvec(2),\nperror(3)\n"
  },
  {
    "path": "share/man/man3/putc.3",
    "content": ".\\\"\t@(#)putc.3s\t6.2 (Berkeley) 11/6/85\n.\\\"\n.TH PUTC 3S  \"November 6, 1985\"\n.AT 3\n.SH NAME\nputc, putchar, fputc, putw \\- put character or word on a stream\n.SH SYNOPSIS\n.B #include <stdio.h>\n.PP\n.B int putc(c, stream)\n.br\n.B char c;\n.br\n.SM\n.B FILE\n.B *stream;\n.PP\n.B int putchar(c)\n.PP\n.B int fputc(c, stream)\n.br\n.SM\n.B FILE\n.B *stream;\n.PP\n.B int putw(w, stream)\n.br\n.SM\n.B FILE\n.B *stream;\n.SH DESCRIPTION\n.I Putc\nappends the character\n.I c\nto the named output\n.IR stream .\nIt returns the character written.\n.PP\n.IR Putchar ( c )\nis defined as \n.IR putc ( c ,\n.BR stdout ).\n.PP\n.I Fputc\nbehaves like \n.IR putc ,\nbut is a genuine function rather than a macro.\n.PP\n.I Putw\nappends word (that is,\n.BR int )\n.I w\nto the output\n.IR stream .\nIt returns the word written.\n.I Putw\nneither assumes nor causes special alignment in the file.\n.SH \"SEE ALSO\"\nfopen(3S),\nfclose(3S),\ngetc(3S),\nputs(3S),\nprintf(3S),\nfread(3S)\n.SH DIAGNOSTICS\nThese functions return the constant\n.SM\n.B EOF\nupon error.  Since this is a good integer,\n.IR  ferror (3S)\nshould be used to detect \n.I putw\nerrors.\n.SH BUGS\nBecause it is implemented as a macro,\n.I putc\ntreats a\n.I stream\nargument with side effects improperly.  In particular\n.IP \"putc(c, *f++);\"\n.PP\ndoesn't work sensibly.\n.PP\nErrors can occur long after the call to\n.IR putc .\n"
  },
  {
    "path": "share/man/man3/puts.3",
    "content": ".\\\"\t@(#)puts.3s\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH PUTS 3S  \"May 15, 1985\"\n.AT 3\n.SH NAME\nputs, fputs \\- put a string on a stream\n.SH SYNOPSIS\n.B #include <stdio.h>\n.PP\n.B puts(s)\n.br\n.B char *s;\n.PP\n.B fputs(s, stream)\n.br\n.B char *s;\n.br\n.SM\n.B FILE\n.B *stream;\n.SH DESCRIPTION\n.I Puts\ncopies the null-terminated string\n.I s\nto the standard output stream\n.B stdout\nand appends a\nnewline character.\n.PP\n.I Fputs\ncopies the null-terminated string\n.I s\nto the named output\n.IR stream .\n.PP\nNeither routine copies the terminal null character.\n.SH \"SEE ALSO\"\nfopen(3S),\ngets(3S),\nputc(3S),\nprintf(3S),\nferror(3S)\n.br\nfread(3S) for\n.I fwrite\n.SH BUGS\n.I Puts\nappends a newline,\n.I fputs\ndoes not, all in the name of backward compatibility.\n"
  },
  {
    "path": "share/man/man3/qsort.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)qsort.3\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH QSORT 3  \"May 15, 1985\"\n.UC 4\n.SH NAME\nqsort \\- quicker sort\n.SH SYNOPSIS\n.nf\n.B qsort(base, nel, width, compar)\n.B char *base;\n.B int (*compar)();\n.fi\n.SH DESCRIPTION\n.I Qsort\nis an implementation of the quicker-sort algorithm.\nThe first argument is a pointer to the base of the data;\nthe second is the number of elements;\nthe third is the width of an element in bytes;\nthe last is the name of the comparison routine\nto be called with two arguments which are pointers\nto the elements being compared.\nThe routine must return an integer less than, equal to, or greater than 0\naccording as the first argument is to be considered\nless than, equal to, or greater than the second.\n.SH \"SEE ALSO\"\nsort(1)\n"
  },
  {
    "path": "share/man/man3/rand.3",
    "content": ".\\\"\t@(#)rand.3c\t6.2 (Berkeley) 9/29/85\n.\\\"\n.TH RAND 3C \"September 29, 1985\"\n.AT 3\n.SH NAME\nrand, srand \\- random number generator\n.SH SYNOPSIS\n.nf\n.B srand(seed)\n.B int seed;\n.PP\n.B rand()\n.fi\n.SH DESCRIPTION\n.ft B\nThe newer random(3) should be used in new applications;\nrand remains for compatibilty.\n.ft R\n.PP\n.I Rand\nuses a multiplicative congruential\nrandom number generator with period\n.if t 2\\u\\s732\\s0\\d\n.if n 2**32\nto return successive pseudo-random\nnumbers in the range from 0 to\n.if t 2\\u\\s731\\s10\\d\\(mi1.\n.if n (2**31)\\(mi1\non the VAX, and\n.if t 2\\u\\s715\\s10\\d\\(mi1.\n.if n (2**15)\\(mi1\non the PDP-11.\n.PP\nThe generator is reinitialized by calling\n.I srand\nwith 1 as argument.\nIt can be set to a random starting point by calling\n.I srand\nwith whatever you like as argument.\n.SH \"SEE ALSO\"\nrandom(3)\n"
  },
  {
    "path": "share/man/man3/random.3",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)random.3\t6.2 (Berkeley) 9/29/85\n.\\\"\n.TH RANDOM 3 \"September 29, 1985\"\n.UC 5\n.SH NAME\nrandom, srandom, initstate, setstate \\- better random number generator; routines for changing generators\n.SH SYNOPSIS\n.nf\n.B long  random()\n.PP\n.B srandom(seed)\n.B int  seed;\n.PP\n.B char  *initstate(seed, state, n)\n.B unsigned  seed;\n.B char  *state;\n.B int  n;\n.PP\n.B char  *setstate(state)\n.B char  *state;\n.fi\n.SH DESCRIPTION\n.PP\n.I Random\nuses a non-linear additive feedback random number generator employing a\ndefault table of size 31 long integers to return successive pseudo-random\nnumbers in the range from 0 to\n.if t 2\\u\\s731\\s10\\d\\(mi1.\n.if n (2**31)\\(mi1.\nThe period of this random number generator is very large, approximately\n.if t 16\\(mu(2\\u\\s731\\s10\\d\\(mi1).\n.if n 16*((2**31)\\(mi1).\n.PP\n.I Random/srandom\nhave (almost) the same calling sequence and initialization properties as\n.I rand/srand.\nThe difference is that\n.IR rand (3)\nproduces a much less random sequence \\(em in fact, the low dozen bits\ngenerated by rand go through a cyclic pattern.  All the bits generated by\n.I random\nare usable.  For example, ``random()&01'' will produce a random binary\nvalue.\n.PP\nUnlike\n.IR srand ,\n.I srandom\ndoes not return the old seed; the reason for this is that the amount of\nstate information used is much more than a single word.  (Two other\nroutines are provided to deal with restarting/changing random\nnumber generators).  Like\n.IR rand (3),\nhowever,\n.I random\nwill by default produce a sequence of numbers that can be duplicated\nby calling\n.I srandom\nwith \n.I 1\nas the seed.\n.PP\nThe\n.I initstate\nroutine allows a state array, passed in as an argument, to be initialized\nfor future use.  The size of the state array (in bytes) is used by\n.I initstate\nto decide how sophisticated a random number generator it should use -- the\nmore state, the better the random numbers will be.\n(Current \"optimal\" values for the amount of state information are\n8, 32, 64, 128, and 256 bytes; other amounts will be rounded down to\nthe nearest known amount.  Using less than 8 bytes will cause an error).\nThe seed for the initialization (which specifies a starting point for\nthe random number sequence, and provides for restarting at the same\npoint) is also an argument.\n.I Initstate\nreturns a pointer to the previous state information array.\n.PP\nOnce a state has been initialized, the\n.I setstate\nroutine provides for rapid switching between states.\n.I Setstate\nreturns a pointer to the previous state array; its\nargument state array is used for further random number generation\nuntil the next call to\n.I initstate\nor\n.I setstate.\n.PP\nOnce a state array has been initialized, it may be restarted at a\ndifferent point either by calling\n.I initstate\n(with the desired seed, the state array, and its size) or by calling\nboth\n.I setstate\n(with the state array) and\n.I srandom\n(with the desired seed).\nThe advantage of calling both\n.I setstate\nand\n.I srandom\nis that the size of the state array does not have to be remembered after\nit is initialized.\n.PP\nWith 256 bytes of state information, the period of the random number\ngenerator is greater than\n.if t 2\\u\\s769\\s10\\d,\n.if n 2**69\nwhich should be sufficient for most purposes.\n.SH AUTHOR\nEarl T. Cohen\n.SH DIAGNOSTICS\n.PP\nIf\n.I initstate\nis called with less than 8 bytes of state information, or if\n.I setstate\ndetects that the state information has been garbled, error\nmessages are printed on the standard error output.\n.SH \"SEE ALSO\"\nrand(3)\n.SH BUGS\nAbout 2/3 the speed of\n.IR rand (3C).\n"
  },
  {
    "path": "share/man/man3/rcmd.3",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)rcmd.3\t6.7 (Berkeley) 5/14/86\n.\\\"\n.TH RCMD 3 \"May 14, 1986\"\n.UC 5\n.SH NAME\nrcmd, rresvport, ruserok \\- routines for returning a stream to a remote command\n.SH SYNOPSIS\n.nf\n.PP\n.B \"rem = rcmd(ahost, inport, locuser, remuser, cmd, fd2p);\"\n.B char **ahost;\n.B int inport;\n.B \"char *locuser, *remuser, *cmd;\"\n.B int *fd2p;\n.PP\n.B s = rresvport(port);\n.B int *port;\n.PP\n.B \"ruserok(rhost, superuser, ruser, luser);\"\n.B char *rhost;\n.B int superuser;\n.B char *ruser, *luser;\n.fi\n.SH DESCRIPTION\n.I Rcmd\nis a routine used by the super-user to execute a command on\na remote machine using an authentication scheme based\non reserved port numbers.\n.I Rresvport\nis a routine which returns a descriptor to a socket\nwith an address in the privileged port space.\n.I Ruserok\nis a routine used by servers\nto authenticate clients requesting service with\n.IR rcmd .\nAll three functions are present in the same file and are used\nby the\n.IR rshd (8C)\nserver (among others).\n.PP\n.I Rcmd\nlooks up the host\n.I *ahost\nusing\n.IR gethostbyname (3N),\nreturning \\-1 if the host does not exist.\nOtherwise\n.I *ahost\nis set to the standard name of the host\nand a connection is established to a server\nresiding at the well-known Internet port\n.IR inport .\n.PP\nIf the connection succeeds,\na socket in the Internet domain of type SOCK_STREAM\nis returned to the caller, and given to the remote\ncommand as \n.B stdin\nand\n.BR stdout .\nIf\n.I fd2p\nis non-zero, then an auxiliary channel to a control\nprocess will be set up, and a descriptor for it will be placed\nin\n.IR *fd2p .\nThe control process will return diagnostic\noutput from the command (unit 2) on this channel, and will also\naccept bytes on this channel as being UNIX signal numbers, to be\nforwarded to the process group of the command.\nIf\n.I fd2p\nis 0, then the \n.B stderr\n(unit 2 of the remote\ncommand) will be made the same as the \n.B stdout\nand no\nprovision is made for sending arbitrary signals to the remote process,\nalthough you may be able to get its attention by using out-of-band data.\n.PP\nThe protocol is described in detail in\n.IR rshd (8C).\n.PP\nThe\n.I rresvport\nroutine is used to obtain a socket with a privileged\naddress bound to it.  This socket is suitable for use\nby \n.I rcmd\nand several other routines.  Privileged Internet ports are those\nin the range 0 to 1023.  Only the super-user\nis allowed to bind an address of this sort to a socket.\n.PP\n.I Ruserok\ntakes a remote host's name, as returned by a\n.IR gethostbyaddr (3N)\nroutine, two user names and a flag indicating whether\nthe local user's name is that of the super-user.  It then\nchecks the files \n.I /etc/hosts.equiv\nand, possibly, \n.I .rhosts\nin the current working directory (normally the local\nuser's home directory) to see if the request for\nservice is allowed.  A 0 is returned if the machine\nname is listed in the ``hosts.equiv'' file, or the\nhost and remote user name are found in the ``.rhosts''\nfile; otherwise \n.I ruserok\nreturns \\-1.  If the\n.I superuser\nflag is 1, the checking of the ``host.equiv'' file is\nbypassed.\nIf the local domain (as obtained from \\fIgethostname\\fP\\|(2))\nis the same as the remote domain, only the machine name need be specified.\n.SH SEE ALSO\nrlogin(1C),\nrsh(1C),\nintro(2),\nrexec(3),\nrexecd(8C),\nrlogind(8C),\nrshd(8C)\n.SH DIAGNOSTICS\n.I Rcmd\nreturns a valid socket descriptor on success.\nIt returns -1 on error and prints a diagnostic message on the standard error.\n.PP\n.I Rresvport\nreturns a valid, bound socket descriptor on success.\nIt returns -1 on error with the global value\n.I errno\nset according to the reason for failure.\nThe error code EAGAIN is overloaded to mean ``All network ports in use.''\n"
  },
  {
    "path": "share/man/man3/regex.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)regex.3\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH REGEX 3 \"May 15, 1985\"\n.UC\n.SH NAME\nre_comp, re_exec \\- regular expression handler\n.SH SYNOPSIS\n.B char *re_comp(s)\n.br\n.B char *s;\n.PP\n.B re_exec(s)\n.br\n.B char *s;\n.SH DESCRIPTION\n.I Re_comp\ncompiles a string into an internal form suitable for pattern matching. \n.I Re_exec \nchecks the argument string against the last string passed to\n.I re_comp.\n.PP\n.I Re_comp\nreturns 0 if the string\n.I s\nwas compiled successfully; otherwise a string containing an\nerror message is returned. If \n.I re_comp\nis passed 0 or a null string, it returns without changing the currently\ncompiled regular expression.\n.PP\n.I Re_exec\nreturns 1 if the string\n.I s\nmatches the last compiled regular expression, 0 if the string\n.I s\nfailed to match the last compiled regular expression, and \\-1 if the compiled\nregular expression was invalid (indicating an internal error).\n.PP\nThe strings passed to both\n.I re_comp\nand\n.I re_exec\nmay have trailing or embedded newline characters; \nthey are terminated by nulls.\nThe regular expressions recognized are described in the manual entry for \n.IR ed (1),\ngiven the above difference.\n.SH \"SEE ALSO\"\ned(1), ex(1), egrep(1), fgrep(1), grep(1)\n.SH DIAGNOSTICS\n.I Re_exec\nreturns \\-1 for an internal error.\n.PP\n.I Re_comp\nreturns one of the following strings if an error occurs:\n.PP\n.nf\n.in +0.5i\n\\fINo previous regular expression,\nRegular expression too long,\nunmatched \\e(,\nmissing ],\ntoo many \\e(\\e) pairs,\nunmatched \\e).\\fP\n.in -0.5i\n.fi\n"
  },
  {
    "path": "share/man/man3/resolver.3",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)resolver.3\t6.1 (Berkeley) 11/21/87\n.\\\"\n.TH RESOLVER 3 \"November 21, 1987\"\n.UC 4\n.SH NAME\nres_mkquery, res_send, res_init, dn_comp, dn_expand \\- resolver routines\n.SH SYNOPSIS\n.B #include <sys/types.h>\n.br\n.B #include <netinet/in.h>\n.br\n.B #include <arpa/nameser.h>\n.br\n.B #include <resolv.h>\n.PP\n.B \"res_mkquery(op, dname, class, type, data, datalen, newrr, buf, buflen)\"\n.br\n.B int op;\n.br\n.B char *dname;\n.br\n.B int class, type;\n.br\n.B char *data;\n.br\n.B int datalen;\n.br\n.B struct rrec *newrr;\n.br\n.B char *buf;\n.br\n.B int buflen;\n.PP\n.B res_send(msg, msglen, answer, anslen)\n.br\n.B char *msg;\n.br\n.B int msglen;\n.br\n.B char *answer;\n.br\n.B int anslen;\n.PP\n.B res_init()\n.PP\n.B dn_comp(exp_dn, comp_dn, length, dnptrs, lastdnptr)\n.br\n.B char *exp_dn, *comp_dn;\n.br\n.B int length;\n.br\n.B char **dnptrs, **lastdnptr;\n.PP\n.B dn_expand(msg, eomorig, comp_dn, exp_dn, length)\n.br\n.B char *msg, *eomorig, *comp_dn, exp_dn;\n.br\n.B int  length;\n.SH DESCRIPTION\nThese routines are used for making, sending and interpreting packets\nfor use with Internet domain name servers.\nGlobal information that is used by the\nresolver routines is kept in the variable\n.IR _res .\nMost of the values have reasonable defaults and can be ignored.\nOptions\nstored in\n.I _res.options\nare defined in\n.I resolv.h\nand are as follows.\nOptions are stored a simple bit mask containing the bitwise ``or''\nof the options enabled.\n.IP RES_INIT\nTrue if the initial name server address and default domain name are\ninitialized (i.e.,\n.I res_init\nhas been called).\n.IP RES_DEBUG\nPrint debugging messages.\n.IP RES_AAONLY\nAccept authoritative answers only.\nWith this option,\n.I res_send\nshould continue until it finds an authoritative answer or finds an error.\nCurrently this is not implemented.\n.IP RES_USEVC\nUse TCP connections for queries instead of UDP datagrams.\n.IP RES_STAYOPEN\nUsed with RES_USEVC to keep the TCP connection open between\nqueries.\nThis is useful only in programs that regularly do many queries.\nUDP should be the normal mode used.\n.IP RES_IGNTC\nUnused currently (ignore truncation errors, i.e., don't retry with TCP).\n.IP RES_RECURSE\nSet the recursion-desired bit in queries.\nThis is the default.\n(\n.I res_send\ndoes not do iterative queries and expects the name server\nto handle recursion.)\n.IP RES_DEFNAMES\nIf set,\n.I res_mkquery\nwill append the default domain name to single-component names\n(those that do not contain a dot).\nThis is the default.\n.IP RES_DNSRCH\nIf this option is set,\nthe standard host lookup routine\n.IR gethostbyname (3)\nwill search for host names in the current domain and in parent domains; see\n.IR hostname (7).\n.PP\n.I Res_init\n.PP\nreads the initialization file to get the default\ndomain name and the Internet address of the initial hosts\nrunning the name server.\nIf this line does not exist, the host running\nthe resolver is tried.\n.I Res_mkquery\nmakes a standard query message and places it in\n.IR buf .\n.I Res_mkquery\nwill return the size of the query or \\-1 if the query is\nlarger than\n.IR buflen .\n.I Op\nis usually QUERY but can be any of the query types defined in\n.IR nameser.h .\n.I Dname\nis the domain name.\nIf\n.I dname\nconsists of a single label and the RES_DEFNAMES flag is enabled\n(the default), the current domain name will be appended to\n.IR dname .\nThe current domain name is defined by the hostname\nor is specified in a system file; it can be overridden\nby the environment variable LOCALDOMAIN.\n.I Newrr\nis currently unused but is intended for making update messages.\n.PP\n.I Res_send\nsends a query to name servers and returns an answer.\nIt will call\n.I res_init\nif RES_INIT is not set, send the query to the local name server, and\nhandle timeouts and retries.\nThe length of the message is returned, or\n\\-1 if there were errors.\n.PP\n.I Dn_expand\nexpands the compressed domain name\n.I comp_dn\nto a full domain name.  Expanded names are converted to upper case.\n.I Msg\nis a pointer to the beginning of the message,\n.I exp_dn\nis a pointer to a buffer of size\n.I length\nfor the result.\nThe size of compressed name is returned or -1 if there was an error.\n.PP\n.I Dn_comp\ncompresses the domain name\n.I exp_dn\nand stores it in\n.IR comp_dn .\nThe size of the compressed name is returned or -1 if there were errors.\n.I length is the size of the array pointed to by\n.IR comp_dn .\n.I Dnptrs\nis a list of pointers to previously compressed names in the current message.\nThe first pointer points to\nto the beginning of the message and the list ends with NULL.\n.I lastdnptr\nis a pointer to the end of the array pointed to\n.IR dnptrs .\nA side effect is to update the list of pointers for\nlabels inserted into the message by\n.I dn_comp\nas the name is compressed.\nIf\n.I dnptr\nis NULL, names are not compressed.\nIf\n.I lastdnptr\nis NULL, the list of labels is not updated.\n.SH FILES\n/etc/resolv.conf\tsee resolver(5)\n.SH \"SEE ALSO\"\ngethostbyname(3), named(8), resolver(5), hostname(7),\n.br\nRFC882, RFC883, RFC973, RFC974,\n.br\nSMM:11 Name Server Operations Guide for BIND\n"
  },
  {
    "path": "share/man/man3/rexec.3",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)rexec.3\t6.5 (Berkeley) 5/14/86\n.\\\"\n.TH REXEC 3 \"May 14, 1986\"\n.UC 5\n.SH NAME\nrexec \\- return stream to a remote command\n.SH SYNOPSIS\n.nf\n.PP\n.B \"rem = rexec(ahost, inport, user, passwd, cmd, fd2p);\"\n.B char **ahost;\n.B int inport;\n.B \"char *user, *passwd, *cmd;\"\n.B int *fd2p;\n.fi\n.SH DESCRIPTION\n.I Rexec\nlooks up the host\n.I *ahost\nusing\n.IR gethostbyname (3N),\nreturning \\-1 if the host does not exist.\nOtherwise\n.I *ahost\nis set to the standard name of the host.\nIf a username and password are both specified, then these\nare used to authenticate to the foreign host; otherwise\nthe environment and then the user's\n.I .netrc\nfile in his\nhome directory are searched for appropriate information.\nIf all this fails, the user is prompted for the information.\n.PP\nThe port\n.I inport\nspecifies which well-known DARPA Internet port to use for\nthe connection; the call ``getservbyname(\"exec\", \"tcp\")'' (see \n.IR getservent (3N))\nwill return a pointer to a structure, which contains the\nnecessary port.\nThe protocol for connection is described in detail in\n.IR rexecd (8C).\n.PP\nIf the connection succeeds,\na socket in the Internet domain of type SOCK_STREAM is returned to\nthe caller, and given to the remote command as\n.B stdin\nand\n.BR stdout .\nIf\n.I fd2p\nis non-zero, then an auxiliary channel to a control\nprocess will be setup, and a descriptor for it will be placed\nin\n.IR *fd2p .\nThe control process will return diagnostic\noutput from the command (unit 2) on this channel, and will also\naccept bytes on this channel as being UNIX signal numbers, to be\nforwarded to the process group of the command.  The diagnostic\ninformation returned does not include remote authorization failure,\nas the secondary connection is set up after authorization has been\nverified.\nIf\n.I fd2p\nis 0, then the \n.B stderr\n(unit 2 of the remote\ncommand) will be made the same as the \n.B stdout\nand no\nprovision is made for sending arbitrary signals to the remote process,\nalthough you may be able to get its attention by using out-of-band data.\n.SH SEE ALSO\nrcmd(3), rexecd(8C)\n"
  },
  {
    "path": "share/man/man3/scandir.3",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)scandir.3\t6.2 (Berkeley) 9/17/85\n.\\\"\n.TH SCANDIR 3  \"September 17, 1985\"\n.UC 5\n.SH NAME\nscandir, alphasort \\- scan a directory\n.SH SYNOPSIS\n.nf\n.B #include <sys/types.h>\n.B #include <sys/dir.h>\n.PP\n.B scandir(dirname, namelist, select, compar)\n.B char *dirname;\n.B struct direct *(*namelist[]);\n.B int (*select)();\n.B int (*compar)();\n.PP\n.B alphasort(d1, d2)\n.B struct direct **d1, **d2;\n.fi\n.SH DESCRIPTION\n.I Scandir\nreads the directory\n.I dirname\nand builds an array of pointers to directory\nentries using\n.IR malloc (3).\nIt returns the number of entries in the array and a pointer to the\narray through\n.IR namelist .\n.PP\nThe\n.I select\nparameter is a pointer to a user supplied subroutine which is called by\n.I scandir\nto select which entries are to be included in the array.\nThe select routine is passed a\npointer to a directory entry and should return a non-zero\nvalue if the directory entry is to be included in the array.\nIf\n.I select\nis null, then all the directory entries will be included.\n.PP\nThe\n.I compar\nparameter is a pointer to a user supplied subroutine which is passed to\n.IR qsort (3)\nto sort the completed array. If this pointer is null, the array is not sorted.\n.I Alphasort\nis a routine which can be used for the\n.I compar\nparameter to sort the array alphabetically.\n.PP\nThe memory allocated for the array can be deallocated with\n.I free\n(see\n.IR malloc (3))\nby freeing each pointer in the array and the array itself.\n.SH \"SEE ALSO\"\ndirectory(3),\nmalloc(3),\nqsort(3),\ndir(5)\n.SH DIAGNOSTICS\nReturns \\-1 if the directory cannot be opened for reading or if\n.IR malloc (3)\ncannot allocate enough memory to hold all the data structures.\n"
  },
  {
    "path": "share/man/man3/scanf.3",
    "content": ".\\\"\t@(#)scanf.3s\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH SCANF 3S  \"May 15, 1985\"\n.AT 3\n.SH NAME\nscanf, fscanf, sscanf \\- formatted input conversion\n.SH SYNOPSIS\n.B #include <stdio.h>\n.PP\n.B scanf(format\n[ , pointer ] . . .\n.B )\n.br\n.B char *format;\n.PP\n.B fscanf(stream, format\n[ , pointer ] . . .\n.B )\n.br\n.SM\n.B FILE\n.B *stream;\n.br\n.B char *format;\n.PP\n.B sscanf(s, format\n[ , pointer ] . . .\n.B )\n.br\n.B char *s, *format;\n.SH DESCRIPTION\n.I Scanf\nreads from the standard input stream\n.BR stdin .\n.I Fscanf\nreads from the named input\n.IR stream .\n.I Sscanf\nreads from the character string\n.IR s .\nEach function reads characters, interprets\nthem according to a format, and stores the results in its arguments.\nEach expects as arguments\na control string\n.IR format ,\ndescribed below,\nand a set of\n.I pointer\narguments\nindicating where the converted input should be stored.\n.PP\nThe\ncontrol string\nusually contains\nconversion specifications, which are used to direct interpretation\nof input sequences.\nThe control string may contain:\n.TP 4\n1.\nBlanks, tabs or newlines,\nwhich match optional white space in the input.\n.TP 4\n2.\nAn ordinary character (not %) which must match\nthe next character of the input stream.\n.TP 4\n3.\nConversion specifications, consisting of the\ncharacter\n.BR % ,\nan optional assignment suppressing character\n.BR * ,\nan optional numerical maximum field width, and a conversion\ncharacter.\n.PP\nA conversion specification directs the conversion of the\nnext input field; the result\nis placed in the variable pointed to by the corresponding argument,\nunless assignment suppression was\nindicated by\n.BR * .\nAn input field is defined as a string of non-space characters;\nit extends to the next inappropriate character or until the field\nwidth, if specified, is exhausted.\n.PP\nThe conversion character indicates the interpretation of the\ninput field; the corresponding pointer argument must\nusually be of a restricted type.\nThe following conversion characters are legal:\n.TP 4\n.B  %\na single `%' is expected\nin the input at this point;\nno assignment is done.\n.TP 4\n.B  d\na decimal integer is expected;\nthe corresponding argument should be an integer pointer.\n.TP 4\n.B  o\nan octal integer is expected;\nthe corresponding argument should be a integer pointer.\n.TP 4\n.B  x\na hexadecimal integer is expected;\nthe corresponding argument should be an integer pointer.\n.ti -0.2i\n.TP 4\n.B  s\na character string is expected;\nthe corresponding argument should be a character pointer\npointing to an array of characters large enough to accept the\nstring and a terminating `\\e0', which will be added.\nThe input field is terminated by a space character\nor a newline.\n.TP 4\n.B  c\na character is expected; the\ncorresponding argument should be a character pointer.\nThe normal skip over space characters is suppressed\nin this case;\nto read the next non-space character, try\n`%1s'.\nIf a field width is given, the corresponding argument\nshould refer to a character array, and the\nindicated number of characters is read.\n.TP 4\n\\z\\fBe\\v'1'f\\v'-1'\\fR\na\nfloating point number is expected;\nthe next field is converted accordingly and stored through the\ncorresponding argument, which should be a pointer to a\n.IR float .\nThe input format for\nfloating point numbers is\nan optionally signed\nstring of digits\npossibly containing a decimal point, followed by an optional\nexponent field consisting of an E or e followed by an optionally signed integer.\n.TP 4\n.B  [\nindicates a string not to be delimited by space characters.\nThe left bracket is followed by a set of characters and a right\nbracket; the characters between the brackets define a set\nof characters making up the string.\nIf the first character\nis not circumflex (\\|^\\|), the input field\nis all characters until the first character not in the set between\nthe brackets; if the first character\nafter the left bracket is ^, the input field is all characters\nuntil the first character which is in the remaining set of characters\nbetween the brackets.\nThe corresponding argument must point to a character array.\n.PP\nThe conversion characters\n.BR d ,\n.B o\nand\n.B x\nmay be capitalized or preceded by\n.B l\nto indicate that a pointer to\n.B long\nrather than to\n.B int\nis in the argument list.\nSimilarly, the conversion characters\n.B e\nor\n.B f\nmay be capitalized or\npreceded by\n.B l\nto indicate a pointer to \n.B double\nrather than to \n.BR float .\nThe conversion characters\n.BR d ,\n.B o\nand\n.B x\nmay be preceded by\n.B h\nto indicate a pointer to\n.B short\nrather than to\n.BR int .\n.PP\nThe\n.I scanf\nfunctions return the number of successfully matched and assigned input\nitems.\nThis can be used to decide how many input items were found.\nThe constant\n.SM\n.B EOF\nis returned upon end of input; note that this is different\nfrom 0, which means that no conversion was done;\nif conversion was intended, it was frustrated by an\ninappropriate character in the input.\n.PP\nFor example, the call\n.IP \"\" 10\nint i; float x; char name[50];\n.br\nscanf(\"%d%f%s\", &i, &x, name);\n.PP\nwith the input line\n.IP\n25   54.32E\\(mi1  thompson\n.PP\nwill assign to\n.I i\nthe value\n25,\n.I x\nthe value 5.432, and\n.I name\nwill contain\n.IR `thompson\\e0' .\nOr,\n.IP\nint i; float x; char name[50];\n.br\nscanf(\"%2d%f%*d%[1234567890]\", &i, &x, name);\n.PP\nwith input\n.IP\n56789 0123 56a72\n.PP\nwill assign 56 to\n.IR i ,\n789.0 to\n.IR x ,\nskip `0123',\nand place the string `56\\e0' in\n.IR name .\nThe next call to\n.I getchar\nwill return `a'.\n.SH \"SEE ALSO\"\natof(3),\ngetc(3S),\nprintf(3S)\n.SH DIAGNOSTICS\nThe \n.I scanf\nfunctions return\n.SM\n.B EOF\non end of input,\nand a short count for missing or illegal data items.\n.SH BUGS\nThe success of literal matches and suppressed\nassignments is not directly\ndeterminable.\n"
  },
  {
    "path": "share/man/man3/setbuf.3",
    "content": ".\\\" Copyright (c) 1980, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" This code is derived from software contributed to Berkeley by\n.\\\" the American National Standards Committee X3, on Information\n.\\\" Processing Systems.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)setbuf.3\t8.1.1 (2.11BSD) 1997/7/28\n.\\\"\n.TH SETBUF 3 \"July 28, 1997\"\n.UC 4\n.SH NAME\n.BR setbuf ,\n.BR setbuffer ,\n.BR setlinebuf ,\n.BR setvbuf\n\\-stream buffering operations\n.SH SYNOPSIS\n.nf\n.B #include <stdio.h>\n.B #include <sys/types.h>\n.sp\n.B void\n\\fBsetbuf\\fP(\\fIstream\\fP, \\fIbuf\\fP)\n.SM\n\\ \\ \\ \\ \\ \\ \\ FILE\\ *stream;\n\\ \\ \\ \\ \\ \\ \\ char\\ *buf;\n.sp\n.B void\n\\fBsetbuffer\\fP(\\fIstream\\fP, \\fIbuf\\fP, \\fIsize\\fP)\n.SM\n\\ \\ \\ \\ \\ \\ \\ FILE\\ *stream;\n\\ \\ \\ \\ \\ \\ \\ char\\ *buf;\n\\ \\ \\ \\ \\ \\ \\ size_t\\ size;\n.sp\n.B int\n\\fBsetlinebuf\\fP(\\fIstream\\fP)\n.SM\n\\ \\ \\ \\ \\ \\ \\ FILE\\ *stream;\n.sp\n.B int\n.br\n\\fBsetvbuf\\fP(\\fIstream\\fP, \\fIbuf\\fP, \\fImode\\fP, \\fIsize\\fP)\n.SM\n\\ \\ \\ \\ \\ \\ \\ FILE\\ *stream;\n\\ \\ \\ \\ \\ \\ \\ char\\ *buf;\n\\ \\ \\ \\ \\ \\ \\ int\\ mode;\n\\ \\ \\ \\ \\ \\ \\ size_t\\ size\n.fi\n.SH DESCRIPTION\nThe three types of buffering available are unbuffered, block buffered,\nand line buffered.\nWhen an output stream is unbuffered, information appears on the\ndestination file or terminal as soon as written;\nwhen it is block buffered many characters are saved up and written as a block;\nwhen it is line buffered characters are saved up until a newline is\noutput or input is read from any stream attached to a terminal device\n(typically stdin).\nThe function\nfflush(3)\nmay be used to force the block out early.\n(See fclose(3).)\n.PP\nNormally all files are block buffered.\nWhen the first\nI/O\noperation occurs on a file,\nmalloc(3)\nis called,\nand an optimally-sized buffer is obtained.\nIf a stream refers to a terminal\n(as\n.I stdout\nnormally does) it is line buffered.\nThe standard error stream\n.I stderr\nis always unbuffered.\n.PP\nThe\n.B setvbuf\nfunction\nmay be used to alter the buffering behavior of a stream.\nThe\n.I mode\nparameter must be one of the following three macros:\n.PP\n.nf\n.ta .5i 1.5i\n\t_IONBF\tunbuffered\n.sp\n\t_IOLBF\tline buffered\n.sp\n\t_IOFBF\tfully buffered\n.fi\n.PP\nThe\n.I size\nparameter may be given as zero\nto obtain deferred optimal-size buffer allocation as usual.\nIf it is not zero,\nthen except for unbuffered files, the \n.I buf\nargument should point to a buffer at least\n.I size\nbytes long;\nthis buffer will be used instead of the current buffer.\n(If the\n.I size\nargument\nis not zero but\n.I buf\nis\nNULL,\na buffer of the given size will be allocated immediately,\nand released on close.\nThis is an extension to ANSI C;\nportable code should use a size of 0 with any\nNULL buffer.)\n.PP\nThe\n.B setvbuf\nfunction may be used at any time,\nbut may have peculiar side effects\n(such as discarding input or flushing output)\nif the stream is ``active''.\nPortable applications should call it only once on any given stream,\nand before any \nI/O\nis performed.\n.PP\nThe other three calls are, in effect, simply aliases for calls to\n.BR setvbuf .\nExcept for the lack of a return value, the\n.B setbuf\nfunction is exactly equivalent to the call\n.PP\n.in +0.5i\nsetvbuf(stream, buf, buf ? _IOFBF : _IONBF, BUFSIZ);\n.in -0.5i\n.PP\nThe\n.B setbuffer\nfunction\nis the same, except that the size of the buffer is up to the caller,\nrather than being determined by the default\nBUFSIZ.\nThe\n.B setlinebuf\nfunction\nis exactly equivalent to the call:\n.PP\n.in +0.5i\nsetvbuf(stream, (char *)NULL, _IOLBF, 0);\n.in -0.5i\n.SH RETURN VALUES\nThe\n.B setvbuf\nfunction returns 0 on success, or EOF\nif the request cannot be honored\n(note that the stream is still functional in this case).\n.PP\nThe\n.B setlinebuf\nfunction returns what the equivalent\n.B setvbuf\nwould have returned.\n.SH SEE ALSO\nfopen(3),\nfclose(3),\nfread(3),\nmalloc(3),\nputs(3),\nprintf(3)\n.SH STANDARDS\nThe\n.B setbuf\nand\n.B setvbuf\nfunctions\nconform to\nANSI C X3.159\\-1989 (``ANSI C'').\n.SH BUGS\nThe\n.B setbuffer\nand\n.B setlinebuf\nfunctions are not portable to versions of\nBSD\nbefore\n4.2BSD.\nOn\n2BSD\nsystems,\n.B setbuf\nalways uses a 1kb buffer size.\n"
  },
  {
    "path": "share/man/man3/setjmp.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)setjmp.3\t6.2 (Berkeley) 1/9/86\n.\\\"\n.TH SETJMP 3 \"January 9, 1986\"\n.UC 4\n.SH NAME\nsetjmp, longjmp \\- non-local goto\n.SH SYNOPSIS\n.nf\n.B #include <setjmp.h>\n.PP\n.B setjmp(env)\n.B jmp_buf env;\n.PP\n.B longjmp(env, val)\n.B jmp_buf env;\n.PP\n.B _setjmp(env)\n.B jmp_buf env;\n.PP\n.B _longjmp(env, val)\n.B jmp_buf env;\n.fi\n.SH DESCRIPTION\nThese routines are useful for dealing with errors \nand interrupts encountered in\na low-level subroutine of a program.\n.PP\n.I Setjmp \nsaves its stack environment in\n.I env\nfor later use by\n.I longjmp.\nIt returns value 0.\n.PP\n.I Longjmp\nrestores the environment saved by the last call of\n.IR setjmp .\nIt then returns in such a way that execution\ncontinues as if the call of \n.I setjmp\nhad just returned the value\n.I val\nto the function that invoked\n.I setjmp,\nwhich must not itself have returned in the interim.\nAll accessible data have values as of the time\n.I longjmp\nwas called.\n.PP\n.I Setjmp\nand\n.I longjmp\nsave and restore the signal mask\n.IR sigmask (2),\nwhile\n.I _setjmp\nand\n.I _longjmp\nmanipulate only the C stack and registers.\n.SH ERRORS\n.PP\nIf the contents of the\n.B jmp_buf\nare corrupted, or correspond to an environment that has already returned,\n.I longjmp\ncalls the routine \n.IR longjmperror .\nIf\n.I longjmperror\nreturns the program is aborted.\nThe default version of \n.I longjmperror\nprints the message ``longjmp botch'' to standard error and returns.\nUser programs wishing to exit more gracefully can write their own\nversions of \n.IR longjmperror .\n.SH \"SEE ALSO\"\nsigvec(2), sigstack(2), signal(3)\n.SH \"NOTES  (PDP-11)\"\nOn the PDP-11, \\fIlongjmperror\\fP is called as \\fI_ljerr\\fP.  This\ndifference stems from the limited name size of the PDP-11 that requires all\nexternal names to be unique within the first seven characters.  However,\n<\\fIsetjmp.h\\fP> automatically translates \\fIlongjmperror\\fP to \\fIljerror\\fP\nand should be included before any definition \\fIlongjmperror\\fP.\n.PP\nThe PDP-11 implementation also contains a subtle bug that occurs when a\nroutine containing a \\fIsetjmp\\fP has \\fIregister\\fP variables.  The bug\nsometimes causes those variables to be given invalid values when a longjmp\nis made back to the routine.  \\fIRegister\\fP variables should therefore be\navoided in routines containing \\fIsetjmps\\fP.\n.PP\nAnd finally, _longjmp may sometimes die fatally.  Sorry.\n"
  },
  {
    "path": "share/man/man3/setmode.3",
    "content": ".\\\" Copyright (c) 1989, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)setmode.3\t8.2.1 (2.11BSD) 1996/2/20\n.\\\"\n.TH SETMODE 3 \"February 20, 1996\"\n.UC 7\n.SH NAME\n\\fBgetmode\\fP, \\fBsetmode\\fP \\- modify mode bits\n.SH SYNOPSIS\n.B #include <unistd.h>\n.sp\n.B mode_t\n.br\n\\fBgetmode\\fP(set, mode)\n.br\n.I void *set;\n.br\n.I mode_t mode;\n.sp\n.B void *\n.br\n\\fBsetmode\\fP(mode_str)\n.br\n.I char *mode_str;\n.SH DESCRIPTION\nThe\n.B getmode\nfunction\nreturns a copy of the file permission bits\n.I mode\nas altered by the values pointed to by\n.IR set .\nWhile only the mode bits are altered, other parts of the file mode\nmay be examined.\n.PP\nThe\n.B setmode\nfunction\ntakes an absolute (octal) or symbolic value, as described in\nchmod(1),\nas an argument\nand returns a pointer to mode values to be supplied to\n.BR getmode .\nBecause some of the symbolic values are relative to the file\ncreation mask,\n.B setmode\nmay call\numask(2).\nIf this occurs, the file creation mask will be restored before\n.B setmode\nreturns.\nIf the calling program changes the value of its file creation mask\nafter calling\n.BR setmode ,\n.B setmode\nmust be called again if\n.B getmode\nis to modify future file modes correctly.\n.PP\nIf the mode passed to\n.B setmode\nis invalid,\n.B setmode\nreturns\n.BR NULL . \n.SH ERRORS\nThe\n.B setmode\nfunction\nmay fail and set errno for any of the errors specified for the library\nroutine\nmalloc(3).\n.SH SEE ALSO\nchmod(1),\nstat(2),\numask(2),\nmalloc(3)\n.SH HISTORY\nThe\n.B getmode\nand\n.B setmode\nfunctions first appeared in 4.4BSD.\n"
  },
  {
    "path": "share/man/man3/setruid.3",
    "content": ".\\\" Copyright (c) 1983, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)setruid.3\t8.1.1 (2.11BSD) 1997/12/3\n.\\\"\n.TH SETRUID 3 \"December 3, 1997\"\n.UC 4\n.SH NAME\n\\fBsetruid\\fP, \\fBsetrgid\\fP \\- set user and group ID\n.SH SYNOPSIS\n.B #include <sys/types.h>\n.nf\n\\fIint\\fP\n\\fBsetruid\\fP(ruid)\n\\ \\ \\ \\ uid_t ruid\n.sp\n\\fIint\\fP\n\\fBsetrgid\\fP(rgid)\n\\ \\ \\ \\ gid_t rgid\n.fi\n.SH DESCRIPTION\nThe\n.B setruid\nfunction\n(\\fBsetrgid\\fP)\nsets the real user ID (group ID) of the\ncurrent process.\n.SH RETURN VALUES\nUpon success, these functions return 0;\notherwise \\-1 is returned.\n.PP\nIf the user is not the super user, or the uid\nspecified is not the real or effective ID, these\nfunctions return \\-1.\n.PP\nThe use of these calls is not portable.\nTheir use is discouraged; they will be removed in the future.\n.SH SEE ALSO\nsetuid(2), setgid(2), seteuid(2), setegid(2), getuid(2), getgid(2)\n.SH HISTORY\nThe\n.B setruid\nand\n.B setrgid\nsyscalls appeared in 4.2BSD\nand were dropped in\n4.4BSD.\n"
  },
  {
    "path": "share/man/man3/siginterrupt.3",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)siginterrupt.3\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH SIGINTERRUPT 3 \"May 15, 1985\"\n.UC 6\n.SH NAME\nsiginterrupt \\- allow signals to interrupt system calls\n.SH SYNOPSIS\n.nf\n.B siginterrupt(sig, flag);\n.B int sig, flag;\n.SH DESCRIPTION\n.I Siginterrupt\nis used to change the system call restart\nbehavior when a system call is interrupted by the specified signal.\nIf the flag is false (0), then system calls will be restarted if\nthey are interrupted by the specified signal\nand no data has been transferred yet.\nSystem call restart is the default behavior on 4.2 BSD.\n.PP\nIf the flag is true (1), then restarting of system calls is disabled.\nIf a system call is interrupted by the specified signal\nand no data has been transferred,\nthe system call will return -1 with errno set to EINTR.\nInterrupted system calls that have started transferring\ndata will return the amount of data actually transferred.\nSystem call interrupt is the signal behavior found on 4.1 BSD\nand AT&T System V UNIX systems.\n.PP\nNote that the new 4.2 BSD signal handling semantics are not\naltered in any other way.\nMost notably, signal handlers always remain installed until\nexplicitly changed by a subsequent\n.IR sigvec (2)\ncall, and the signal mask operates as documented in\n.IR sigvec (2).\nPrograms may switch between restartable and interruptible\nsystem call operation as often as desired in the execution of a program.\n.PP\nIssuing a\n.IR siginterrupt (3)\ncall during the execution of a signal handler will cause\nthe new action to take place on the next signal to be caught.\n.SH NOTES\nThis library routine uses an extension of the\n.IR sigvec (2)\nsystem call that is not available in 4.2BSD,\nhence it should not be used if backward compatibility is needed.\n.SH \"RETURN VALUE\nA 0 value indicates that the call succeeded.\nA -1 value indicates that an invalid signal number has been supplied.\n.SH \"SEE ALSO\"\nsigvec(2), sigblock(2), sigpause(2), sigsetmask(2).\n"
  },
  {
    "path": "share/man/man3/signal.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)signal.3c\t6.4 (Berkeley) 5/20/86\n.\\\"\n.TH SIGNAL 3C \"May 20, 1986\"\n.UC 4\n.ie t .ds d \\(dg\n.el .ds d \\z'|+'\n.ie t .ds b \\(bu\n.el .ds b @\n.SH NAME\nsignal \\- simplified software signal facilities\n.SH SYNOPSIS\n.nf\n.B #include <signal.h>\n.PP\n.B (*signal(sig, func))()\n.B int (*func)();\n.fi\n.SH DESCRIPTION\n.I Signal\nis a simplified interface to the more general\n.IR sigvec (2)\nfacility.\n.PP\nA signal\nis generated by some abnormal event,\ninitiated by a user at a terminal (quit, interrupt, stop),\nby a program error (bus error, etc.),\nby request of another program (kill),\nor when a process is stopped because it wishes to access\nits control terminal while in the background (see\n.IR tty (4)).\nSignals are optionally generated\nwhen a process resumes after being stopped,\nwhen the status of child processes changes,\nor when input is ready at the control terminal.\nMost signals cause termination of the receiving process if no action\nis taken; some signals instead cause the process receiving them\nto be stopped, or are simply discarded if the process has not\nrequested otherwise.\nExcept for the SIGKILL and SIGSTOP\nsignals, the\n.I signal\ncall allows signals either to be ignored\nor to cause an interrupt to a specified location.\nThe following is a list of all signals with\nnames as in the include file\n.RI < signal.h >:\n.LP\n.nf\n.ta \\w'SIGVTALRM 'u +\\w'15*  'u\nSIGHUP\t1\thangup\nSIGINT\t2\tinterrupt\nSIGQUIT\t3*\tquit\nSIGILL\t4*\tillegal instruction\nSIGTRAP\t5*\ttrace trap\nSIGIOT\t6*\tIOT instruction\nSIGEMT\t7*\tEMT instruction\nSIGFPE\t8*\tfloating point exception\nSIGKILL\t9\tkill (cannot be caught or ignored)\nSIGBUS\t10*\tbus error\nSIGSEGV\t11*\tsegmentation violation\nSIGSYS\t12*\tbad argument to system call\nSIGPIPE\t13\twrite on a pipe with no one to read it\nSIGALRM\t14\talarm clock\nSIGTERM\t15\tsoftware termination signal\nSIGURG\t16\\*b\turgent condition present on socket\nSIGSTOP\t17\\*d\tstop (cannot be caught or ignored)\nSIGTSTP\t18\\*d\tstop signal generated from keyboard\nSIGCONT\t19\\*b\tcontinue after stop\nSIGCHLD\t20\\*b\tchild status has changed\nSIGTTIN\t21\\*d\tbackground read attempted from control terminal\nSIGTTOU\t22\\*d\tbackground write attempted to control terminal\nSIGIO\t23\\*b\ti/o is possible on a descriptor (see \\fIfcntl\\fP(2))\nSIGXCPU\t24\tcpu time limit exceeded (see \\fIsetrlimit\\fP(2))\nSIGXFSZ\t25\tfile size limit exceeded (see \\fIsetrlimit\\fP(2))\nSIGVTALRM\t26\tvirtual time alarm (see \\fIsetitimer\\fP(2))\nSIGPROF\t27\tprofiling timer alarm (see \\fIsetitimer\\fP(2))\nSIGWINCH\t28\\*b\tWindow size change\nSIGUSR1\t30\tUser defined signal 1\nSIGUSR2\t31\tUser defined signal 2\n.fi\n.PP\nThe starred signals in the list above cause a core image\nif not caught or ignored.\n.PP\nIf\n.I func\nis SIG_DFL, the default action\nfor signal\n.I sig\nis reinstated; this default is termination\n(with a core image for starred signals)\nexcept for signals marked with \\*b or \\*d.\nSignals marked with \\*b are discarded if the action\nis SIG_DFL; signals marked\nwith \\*d cause the process to stop.\nIf\n.I func\nis SIG_IGN the signal is subsequently ignored\nand pending instances of the signal are discarded.\nOtherwise, when the signal occurs\nfurther occurrences of the signal are\nautomatically blocked and\n.I func\nis called.\n.PP\nA return from the function unblocks\nthe handled signal and\ncontinues the process at the point it was interrupted.\n\\fBUnlike previous signal facilities, the handler \\fIfunc\\fP\nremains installed after a signal has been delivered.\\fP\n.PP\nIf a caught signal occurs\nduring certain system calls, causing\nthe call to terminate prematurely, the call\nis automatically restarted.\nIn particular this can occur\nduring a\n.I read\nor\n.IR write (2)\non a slow device (such as a terminal; but not a file)\nand during a\n.IR wait (2).\n.PP\nThe value of\n.I signal\nis the previous (or initial)\nvalue of\n.I func\nfor the particular signal.\n.PP\nAfter a\n.IR fork (2)\nor\n.IR vfork (2)\nthe child inherits\nall signals.\n.IR  Execve (2)\nresets all caught signals to the default action;\nignored signals remain ignored.\n.SH \"RETURN VALUE\nThe previous action is returned on a successful call.\nOtherwise, \\-1 is returned and \n.I errno\nis set to indicate the error.\n.SH ERRORS\n.I Signal\nwill fail and no action will take place if one of the\nfollowing occur:\n.TP 15\n[EINVAL]\n.I Sig\nis not a valid signal number.\n.TP 15\n[EINVAL]\nAn attempt is made to ignore or supply a handler for SIGKILL\nor SIGSTOP.\n.TP 15\n[EINVAL]\nAn attempt is made to ignore SIGCONT (by default SIGCONT\nis ignored).\n.SH \"SEE ALSO\"\nkill(1),\nptrace(2), kill(2),\nsigvec(2), sigblock(2), sigsetmask(2), sigpause(2),\nsigstack(2), setjmp(3), tty(4)\n.SH \"NOTES  (VAX-11)\"\nThe handler routine can be declared:\n.PP\n    handler(sig, code, scp)\n.PP\nHere\n.I sig\nis the signal number, into which the hardware faults and traps are\nmapped as defined below.  Code is a parameter which is either a constant\nas given below or, for compatibility mode faults, the code provided by\nthe hardware. \n.I Scp\nis a pointer to the\n.I \"struct sigcontext\"\nused by the system to restore the process context from before\nthe signal.\nCompatibility mode faults are distinguished from the\nother SIGILL traps by having PSL_CM set in the psl.\n.PP\nThe following defines the mapping of hardware traps to signals\nand codes.  All of these symbols are defined in\n.RI < signal.h >:\n.LP\n.ta \\w'     Floating/decimal divide by zero   'u +\\w'15*  'u +8n\n.nf\n   Hardware condition\tSignal\tCode\n\nArithmetic traps:\n   Integer overflow\tSIGFPE\tFPE_INTOVF_TRAP\n   Integer division by zero\tSIGFPE\tFPE_INTDIV_TRAP\n   Floating overflow trap\tSIGFPE\tFPE_FLTOVF_TRAP\n   Floating/decimal division by zero\tSIGFPE\tFPE_FLTDIV_TRAP\n   Floating underflow trap\tSIGFPE\tFPE_FLTUND_TRAP\n   Decimal overflow trap\tSIGFPE\tFPE_DECOVF_TRAP\n   Subscript-range\tSIGFPE\tFPE_SUBRNG_TRAP\n   Floating overflow fault\tSIGFPE\tFPE_FLTOVF_FAULT\n   Floating divide by zero fault\tSIGFPE\tFPE_FLTDIV_FAULT\n   Floating underflow fault\tSIGFPE\tFPE_FLTUND_FAULT\nLength access control\tSIGSEGV\nProtection violation\tSIGBUS\nReserved instruction\tSIGILL\tILL_RESAD_FAULT\nCustomer-reserved instr.\tSIGEMT\nReserved operand\tSIGILL\tILL_PRIVIN_FAULT\nReserved addressing\tSIGILL\tILL_RESOP_FAULT\nTrace pending\tSIGTRAP\nBpt instruction\tSIGTRAP\nCompatibility-mode\tSIGILL\thardware supplied code\nChme\tSIGSEGV\nChms\tSIGSEGV\nChmu\tSIGSEGV\n.fi\n.SH \"NOTES  (PDP-11)\"\nThe handler routine can be declared:\n.PP\n    handler(sig, code, scp)\n    int sig, code;\n    struct sigcontext *scp;\n.PP\nHere \\fIsig\\fP is the signal number, into which the hardware faults and\ntraps are mapped as defined below.  \\fICode\\fP is a parameter that is a\nconstant as given below.  \\fIScp\\fP is a pointer to the \\fIsigcontext\\fP\nstructure (defined in <\\fIsignal.h\\fP>), used to restore the context from\nbefore the signal.\n.PP\nThe following defines the mapping of hardware traps to signals\nand codes.  All of these symbols are defined in <\\fIsignal.h\\fP>:\n.LP\n.ta \\w'     Floating/decimal divide by zero   'u +\\w'15*  'u +8n\n.nf\n   Hardware condition\tSignal\tCode\n\nArithmetic traps:\n   Floating overflow trap\tSIGFPE\tFPE_FLTOVF_TRAP\n   Floating/decimal division by zero\tSIGFPE\tFPE_FLTDIV_TRAP\n   Floating underflow trap\tSIGFPE\tFPE_FLTUND_TRAP\n   Decimal overflow trap\tSIGFPE\tFPE_DECOVF_TRAP\n   Illegal return code\tSIGFPE\tFPE_CRAZY\n   Bad op code\tSIGFPE\tFPE_OPCODE_TRAP\n   Bad operand\tSIGFPE\tFPE_OPERAND_TRAP\n   Maintenance trap\tSIGFPE\tFPE_MAINT_TRAP\nLength access control\tSIGSEGV\nProtection violation (odd address)\tSIGBUS\nReserved instruction\tSIGILL\tILL_RESAD_FAULT\nCustomer-reserved instr.\tSIGEMT\nTrace pending\tSIGTRAP\nBpt instruction\tSIGTRAP\n.fi\n.DT\n.PP\nThe handler routine must save any registers it uses and restore them before\nreturning.  On the PDP-11, the kernel saves \\fIr0\\fP and \\fIr1\\fP before\ncalling the handler routine, but expect the handler to save any other\nregisters it uses.  The standard entry code generated by the C compiler for\nhandler routines written in C automatically saves the remaining general\nregisters, but floating point registers are \\fInot\\fP saved.  As a result\nthere is currently no [standard] method for a handler routine written in C\nto perform floating point operations without blowing the interrupted program\nout of the water.\n"
  },
  {
    "path": "share/man/man3/sigsetops.3",
    "content": ".\\\" Copyright (c) 1983, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)sigsetops.3\t8.1.1 (2.11BSD) 1997/9/3\n.\\\"\n.TH SIGSETOPS 3 \"September 3, 1997\"\n.UC 7\n.SH NAME\n.BR sigemptyset ,\n.BR sigfillset ,\n.BR sigaddset ,\n.BR sigdelset ,\n.BR sigismember\n\\- manipulate signal sets\n.SH SYNOPSIS\n.B #include <signal.h>\n.sp\n\\fBsigemptyset\\fP(set)\n.br\n.I sigset_t *set;\n.sp\n\\fBsigfillset\\fP(set)\n.br\n.I sigset_t *set;\n.sp\n\\fBsigaddset\\fP(set, signo)\n.br\n.I sigset_t *set;\n.br\n.I int signo;\n.sp\n\\fBsigdelset\\fP(set, signo)\n.br\n.I sigset_t *set;\n.br\n.I int signo;\n.sp\n\\fBsigismember\\fP(set, signo)\n.br\n.I sigset_t *set;\n.br\n.I int signo;\n.SH DESCRIPTION\nThese functions manipulate signal sets stored in a\n.I sigset_t .\nEither\n.B sigemptyset\nor\n.B sigfillset\nmust be called for every object of type\n.I sigset_t\nbefore any other use of the object.\n.PP\nThe\n.B sigemptyset\nfunction initializes a signal set to be empty.\n.PP\nThe\n.B sigfillset\nfunction initializes a signal set to contain all signals.\n.PP\nThe\n.B sigaddset\nfunction adds the specified signal\n.I signo\nto the signal set.\n.PP\nThe\n.B sigdelset\nfunction deletes the specified signal\n.I signo\nfrom the signal set.\n.PP\nThe\n.B sigismember\nfunction returns whether a specified signal\n.I signo\nis contained in the signal set.\n.PP\nThese functions\nare provided as macros in the include file\n.RI < signal.h >.\nActual functions are available\nif their names are undefined (with #undef\n\\fBname\\fP).\n.SH RETURN VALUES\nThe\n.B sigismember\nfunction returns 1\nif the signal is a member of the set,\n0 otherwise.\nThe other functions return 0.\n.SH ERRORS\nCurrently no errors are detected.\n.SH SEE ALSO\nkill(2), sigaction(2), sigsuspend(2)\n.SH STANDARDS\nThese functions are defined by\nIEEE Std1003.1-1988 (``POSIX'').\n"
  },
  {
    "path": "share/man/man3/sin.3",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)sin.3m\t6.6 (Berkeley) 5/12/86\n.\\\"\n.TH SIN 3M  \"May 12, 1986\"\n.UC 4\n.de Pi\t\t\\\" PI stuff sign\n.if n \\\\\n\\\\$2pi\\\\$1\n.if t \\\\\n\\\\$2\\\\(*p\\\\$1\n..\n.ds up \\fIulp\\fR\n.SH NAME\nsin, cos, tan, asin, acos, atan, atan2 \\- trigonometric functions\nand their inverses\n.SH SYNOPSIS\n.nf\n.B #include <math.h>\n.PP\n.B double sin(x)\n.B double x;\n.PP\n.B double cos(x)\n.B double x;\n.PP\n.B double tan(x)\n.B double x;\n.PP\n.B double asin(x)\n.B double x;\n.PP\n.B double acos(x)\n.B double x;\n.PP\n.B double atan(x)\n.B double x;\n.PP\n.B double atan2(y,x)\n.B double y,x;\n.fi\n.SH DESCRIPTION\nSin, cos and tan\nreturn trigonometric functions of radian arguments x.\n.PP\nAsin returns the arc sine in the range \n.Pi /2 \\-\nto\n.Pi /2.\n.PP\nAcos returns the arc cosine in the range 0 to\n.Pi .\n.PP\nAtan returns the arc tangent in the range\n.Pi /2 \\-\nto\n.Pi /2.\n.PP\nOn a VAX,\n.nf\n.if n \\{\\\n.ta \\w'atan2(y,x) := 'u+2n +\\w'sign(y)\\(**(pi \\- atan(|y/x|))'u+2n\natan2(y,x) := \tatan(y/x)\tif x > 0,\n\tsign(y)\\(**(pi \\- atan(|y/x|))\tif x < 0,\n\t0\tif x = y = 0, or\n\tsign(y)\\(**pi/2\tif x = 0 != y.  \\}\n.if t \\{\\\n.ta \\w'atan2(y,x) := 'u+2n +\\w'sign(y)\\(**(\\(*p \\- atan(|y/x|))'u+2n\natan2(y,x) := \tatan(y/x)\tif x > 0,\n\tsign(y)\\(**(\\(*p \\- atan(|y/x|))\tif x < 0,\n\t0\tif x = y = 0, or\n\tsign(y)\\(**\\(*p/2\tif x = 0 \\(!= y.  \\}\n.ta\n.fi\n.SH DIAGNOSTICS\nOn a VAX, if |x| > 1 then asin(x) and acos(x)\nwill return reserved operands and \\fIerrno\\fR will be set to EDOM.\n.SH NOTES\nAtan2 defines atan2(0,0) = 0 on a VAX despite that previously\natan2(0,0) may have generated an error message.\nThe reasons for assigning a value to atan2(0,0) are these:\n.IP (1) \\w'\\0\\0\\0\\0'u\nPrograms that test arguments to avoid computing\natan2(0,0) must be indifferent to its value.\nPrograms that require it to be invalid are vulnerable\nto diverse reactions to that invalidity on diverse computer systems. \n.IP (2) \\w'\\0\\0\\0\\0'u\nAtan2 is used mostly to convert from rectangular (x,y)\nto polar\n.if n\\\n(r,theta)\n.if t\\\n(r,\\(*h)\ncoordinates that must satisfy x =\n.if n\\\nr\\(**cos theta\n.if t\\\nr\\(**cos\\(*h\nand y =\n.if n\\\nr\\(**sin theta.\n.if t\\\nr\\(**sin\\(*h.\nThese equations are satisfied when (x=0,y=0)\nis mapped to \n.if n \\\n(r=0,theta=0)\n.if t \\\n(r=0,\\(*h=0)\non a VAX.  In general, conversions to polar coordinates\nshould be computed thus:\n.nf\n.ta 1iR +1n +\\w' := hypot(x,y);'u+0.5i\n.if n \\{\\\n\tr\t:= hypot(x,y);\t... := sqrt(x\\(**x+y\\(**y)\n\ttheta\t:= atan2(y,x).\n.ta \\}\n.if t \\{\\\n\tr\t:= hypot(x,y);\t... := \\(sr(x\\u\\s82\\s10\\d+y\\u\\s82\\s10\\d)\n\t\\(*h\t:= atan2(y,x).\n.ta \\}\n.fi\n.IP (3) \\w'\\0\\0\\0\\0'u\nThe foregoing formulas need not be altered to cope in a\nreasonable way with signed zeros and infinities\non a machine that conforms to IEEE 754;\nthe versions of hypot and atan2 provided for\nsuch a machine are designed to handle all cases.\nThat is why atan2(\\(+-0,\\-0) =\n.Pi , \\(+-\nfor instance.\nIn general the formulas above are equivalent to these:\n.RS\n.nf\n.if n \\\nr := sqrt(x\\(**x+y\\(**y); if r = 0 then x := copysign(1,x);\n.if t \\\nr := \\(sr(x\\(**x+y\\(**y);\\0\\0if r = 0 then x := copysign(1,x);\n.br\n.if n \\\n.ta 1i\n.if t \\\n.ta \\w'if x > 0'u+2n +\\w'then'u+2n\n.if n \\\nif x > 0\tthen theta := 2\\(**atan(y/(r+x))\n.if t \\\nif x > 0\tthen\t\\(*h := 2\\(**atan(y/(r+x))\n.if n \\\n\telse theta := 2\\(**atan((r\\-x)/y);\n.if t \\\n\telse\t\\(*h := 2\\(**atan((r\\-x)/y);\n.fi\n.RE\nexcept if r is infinite then atan2 will yield an\nappropriate multiple of\n.Pi /4\nthat would otherwise have to be obtained by taking limits.\n.SH ERROR (due to Roundoff etc.)\nLet P stand for the number stored in the computer in place of\n.Pi \" = 3.14159 26535 89793 23846 26433 ... .\"\nLet \"trig\" stand for one of \"sin\", \"cos\" or \"tan\".  Then\nthe expression \"trig(x)\" in a program actually produces an\napproximation to\n.Pi /P), trig(x\\(**\nand \"atrig(x)\" approximates\n.Pi )\\(**atrig(x). (P/\nThe approximations are close,  within 0.9 \\*(ups for sin,\ncos and atan, within 2.2 \\*(ups for tan, asin,\nacos and atan2 on a VAX.  Moreover,\n.Pi \\& \"P = \"\nin the codes that run on a VAX.\n\nIn the codes that run on other machines, P differs from\n.Pi\nby a fraction of an \\*(up; the difference matters only if the argument\nx is huge, and even then the difference is likely to be swamped by\nthe uncertainty in x.  Besides, every trigonometric identity that\ndoes not involve\n.Pi\nexplicitly is satisfied equally well regardless of whether\n.Pi . \"P = \"\nFor instance,\n.if n \\\nsin(x)**2+cos(x)**2\\0=\\01\n.if t \\\nsin\\u\\s62\\s10\\d(x)+cos\\u\\s62\\s10\\d(x)\\0=\\01\nand sin(2x)\\0=\\02\\|sin(x)cos(x) to within a few \\*(ups no matter how big\nx may be.  Therefore the difference between P and\n.Pi\nis most unlikely to affect scientific and engineering computations.\n.SH SEE ALSO\nmath(3M), hypot(3M), sqrt(3M), infnan(3M)\n.SH AUTHOR\nRobert P. Corbett, W. Kahan, Stuart\\0I.\\0McDonald, Peter\\0Tang and,\nfor the codes for IEEE 754, Dr. Kwok\\-Choi\\0Ng.\n"
  },
  {
    "path": "share/man/man3/sinh.3",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)sinh.3m\t6.5 (Berkeley) 5/12/86\n.\\\"\n.TH SINH 3M  \"May 12, 1986\"\n.UC 4\n.SH NAME\nsinh, cosh, tanh \\- hyperbolic functions\n.SH SYNOPSIS\n.nf\n.B #include <math.h>\n.PP\n.B double sinh(x)\n.B double x;\n.PP\n.B double cosh(x)\n.B double x;\n.PP\n.B double tanh(x)\n.B double x;\n.fi\n.SH DESCRIPTION\nThese functions compute the designated hyperbolic functions for real arguments.\n.SH ERROR (due to Roundoff etc.)\nBelow 2.4 \\fIulp\\fRs; an \\fIulp\\fR is one \\fIU\\fRnit in the \\fIL\\fRast\n\\fIP\\fRlace.\n.SH DIAGNOSTICS\nSinh and cosh return the reserved operand on a VAX if\nthe correct value would overflow.\n.SH SEE ALSO\nmath(3M), infnan(3M)\n.SH AUTHOR\nW. Kahan, Kwok\\-Choi Ng\n"
  },
  {
    "path": "share/man/man3/sleep.3",
    "content": ".\\\" Copyright (c) 1986, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)sleep.3\t8.1.1 (2.11BSD) 1997/9/26\n.\\\"\n.TH SLEEP 3 \"September 26, 1997\"\n.UC 3\n.SH NAME\n\\fBsleep\\fP, usleep \\- suspend process execution\n.SH SYNOPSIS\n.B #include <unistd.h>\n.sp\n.nf\nunsigned int\nsleep(seconds)\n      unsigned int seconds;\n.sp\nvoid\nusleep(microseconds)\n       long microseconds;\n.fi\n.SH DESCRIPTION\nThe\n.B sleep\nfunction suspends execution of the calling process for\n.I seconds\nof clock time, or until interrupted by a signal.\n.PP\nThe\n.B usleep\nfunction suspends execution of the calling process for\n.I microseconds\nof clock time, or until interrupted by a signal.\n.PP\nSystem activity may lengthen the suspension.\n.SH RETURN VALUES\nThe\n.B sleep\nfunction returns 0, or if interrupted before\n.IR seconds,\nthe amount not slept (the requested time minus the time actually slept)\nin seconds.  The\n.B usleep\nfunction does not return anything (meaningful).\n.SH SEE ALSO\nselect(2)\n.SH COMPATIBILITY\nPrevious implementations of\n.B sleep\nand\n.B usleep\nre-suspended the process if interrupted by a signal.\nThis implementation has been changed to return in that case,\nto conform to POSIX 1003.1-88.\n.PP\nOn the PDP-11 the previous version of \\fBusleep\\fP took a \\fIu_int\\fP as \nthe input parameter.  This has been changed to be \\fIlong\\fP so that\n\\fBusleep\\fP can be used for more than 65 milliseconds (a u_int could only\ncount 65535 microseconds) of sleep.  Thus it is now possible for \n\\fBusleep\\fP to handle longer sleep durations than \\fBsleep\\fP.\n.SH BUGS\nOn the PDP-11 the clock resolution is limited to the line frequency (usually\n60Hz in the U.S.A. and 50Hz elsewhere).\n.SH HISTORY\nA\n.B usleep\nfunction appeared in\n4.3BSD.\nA\n.B sleep\nfunction appeared in V7.\n"
  },
  {
    "path": "share/man/man3/sqrt.3",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)sqrt.3m\t6.2 (Berkeley) 5/12/86\n.\\\"\n.TH SQRT 3M  \"May 12, 1986\"\n.UC 6\n.ds up \\fIulp\\fR\n.SH NAME\ncbrt, sqrt \\- cube root, square root\n.SH SYNOPSIS\n.nf\n.B #include <math.h>\n.PP\n.B double cbrt(x)\n.B double x;\n.PP\n.B double sqrt(x)\n.B double x;\n.fi\n.SH DESCRIPTION\nCbrt(x) returns the cube root of x.\n.PP\nSqrt(x) returns the square root of x.\n.SH DIAGNOSTICS\nOn a VAX, sqrt(negative)\nreturns the reserved operand and sets \\fIerrno\\fR to EDOM .\n.SH ERROR (due to Roundoff etc.)\nCbrt is accurate to within 0.7 \\*(ups.\n.br\nSqrt on a VAX is accurate to within 0.501 \\*(ups.\n.br\nSqrt on a machine that conforms to IEEE 754 is correctly rounded\nin accordance with the rounding mode in force; the error is less than\nhalf an \\*(up in the default mode (round\\-to\\-nearest).\nAn \\*(up is one \\fIU\\fRnit in the \\fIL\\fRast \\fIP\\fRlace carried.\n.SH SEE ALSO\nmath(3M), infnan(3M)\n.SH AUTHOR\nW. Kahan\n"
  },
  {
    "path": "share/man/man3/stdio.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)stdio.3s\t6.2 (Berkeley) 5/13/86\n.\\\"\n.TH STDIO 3S \"May 13, 1986\"\n.UC 4\n.SH NAME\nstdio \\- standard buffered input/output package\n.SH SYNOPSIS\n.B #include <stdio.h>\n.PP\n.SM\n.B FILE\n.B *stdin;\n.br\n.SM\n.B FILE\n.B *stdout;\n.br\n.SM\n.B FILE\n.B *stderr;\n.SH DESCRIPTION\nThe functions described in section 3S constitute a user-level buffering\nscheme.  The in-line macros\n.I getc\nand\n.IR  putc (3S)\nhandle characters quickly.  The higher level routines\n.IR gets ,\n.IR fgets ,\n.IR scanf ,\n.IR fscanf ,\n.IR fread ,\n.IR puts ,\n.IR fputs ,\n.IR printf ,\n.IR fprintf ,\n.IR fwrite\nall use\n.I getc\nand\n.IR putc ;\nthey can be freely intermixed.\n.PP\nA file with associated buffering is called a\n.IR stream ,\nand is declared to be a pointer to a defined type\n.SM\n.BR FILE .\n.IR  Fopen (3S)\ncreates certain descriptive data for a stream\nand returns a pointer to designate the stream in all further transactions.\nThere are three normally open streams with constant pointers declared in\nthe include file and associated with the standard open files:\n.TP 10n\n.B stdin\nstandard input file\n.br\n.ns\n.TP\n.B stdout\nstandard output file\n.br\n.ns\n.TP\n.B stderr\nstandard error file\n.PP\nA constant `pointer'\n.SM\n.B NULL\n(0)\ndesignates no stream at all.\n.PP\nAn integer constant\n.SM\n.B EOF\n(\\-1) is returned upon end of file or error by integer functions that\ndeal with streams.\n.PP\nAny routine that uses the standard input/output package\nmust include the header file\n.RI < stdio.h >\nof pertinent macro definitions.\nThe functions and constants mentioned in sections labeled 3S\nare declared in the include file and need no further declaration.\nThe constants, and the following `functions' are\nimplemented as macros; redeclaration of these names is perilous:\n.IR getc ,\n.IR getchar ,\n.IR putc ,\n.IR putchar ,\n.IR feof ,\n.IR ferror ,\n.IR fileno .\n.SH \"SEE ALSO\"\nopen(2), close(2), read(2), write(2), fread(3S), fseek(3S), f*(3S)\n.SH DIAGNOSTICS\nThe value\n.SM\n.B EOF\nis returned uniformly to indicate that a\n.SM\n.B FILE\npointer has not been initialized with\n.IR fopen ,\ninput (output) has been attempted on an output (input) stream, or a\n.SM\n.B FILE\npointer designates corrupt or otherwise unintelligible\n.SM\n.B FILE\ndata.\n.PP\nFor purposes of efficiency, this implementation of the standard library\nhas been changed to line buffer output to a terminal by default and attempts\nto do this transparently by flushing the output whenever a \n.IR read (2)\nfrom the standard input is necessary.  This is almost always transparent,\nbut may cause confusion or malfunctioning of programs which use\nstandard i/o routines but use\n.IR read (2)\nthemselves to read from the standard input.\n.PP\nIn cases where a large amount of computation is done after printing\npart of a line on an output terminal, it is necessary to\n.IR fflush (3S)\nthe standard output before going off and computing so that the output\nwill appear.\n.SH BUGS\nThe standard buffered functions do not interact well with certain other\nlibrary and system functions, especially \\fIvfork\\fP and \\fIabort\\fP.\n.SH \"LIST OF FUNCTIONS\"\n.sp 2\n.nf\n.ta \\w'setlinebuf'u+2n +\\w'setbuf.3s'u+10n\n\\fIName\\fP\t\\fIAppears on Page\\fP\t\\fIDescription\\fP\n.ta \\w'setlinebuf'u+4n +\\w'setbuf.3s'u+4n\n.sp 5p\nclearerr\tferror.3s\tstream status inquiries\nfclose\tfclose.3s\tclose or flush a stream\nfdopen\tfopen.3s\topen a stream\nfeof\tferror.3s\tstream status inquiries\nferror\tferror.3s\tstream status inquiries\nfflush\tfclose.3s\tclose or flush a stream\nfgetc\tgetc.3s\tget character or word from stream\nfgets\tgets.3s\tget a string from a stream\nfileno\tferror.3s\tstream status inquiries\nfopen\tfopen.3s\topen a stream\nfprintf\tprintf.3s\tformatted output conversion\nfputc\tputc.3s\tput character or word on a stream\nfputs\tputs.3s\tput a string on a stream\nfread\tfread.3s\tbuffered binary input/output\nfreopen\tfopen.3s\topen a stream\nfscanf\tscanf.3s\tformatted input conversion\nfseek\tfseek.3s\treposition a stream\nftell\tfseek.3s\treposition a stream\nfwrite\tfread.3s\tbuffered binary input/output\ngetc\tgetc.3s\tget character or word from stream\ngetchar\tgetc.3s\tget character or word from stream\ngets\tgets.3s\tget a string from a stream\ngetw\tgetc.3s\tget character or word from stream\nprintf\tprintf.3s\tformatted output conversion\nputc\tputc.3s\tput character or word on a stream\nputchar\tputc.3s\tput character or word on a stream\nputs\tputs.3s\tput a string on a stream\nputw\tputc.3s\tput character or word on a stream\nrewind\tfseek.3s\treposition a stream\nscanf\tscanf.3s\tformatted input conversion\nsetbuf\tsetbuf.3s\tassign buffering to a stream\nsetbuffer\tsetbuf.3s\tassign buffering to a stream\nsetlinebuf\tsetbuf.3s\tassign buffering to a stream\nsprintf\tprintf.3s\tformatted output conversion\nsscanf\tscanf.3s\tformatted input conversion\nungetc\tungetc.3s\tpush character back into input stream\n.fi\n"
  },
  {
    "path": "share/man/man3/strcspn.3",
    "content": ".\\\" Copyright (c) 1990, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" This code is derived from software contributed to Berkeley by\n.\\\" Chris Torek and the American National Standards Committee X3,\n.\\\" on Information Processing Systems.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)strcspn.3\t8.1.1 (2.11BSD) 1996/1/12\n.\\\"\n.TH STRCSPN 3 \"January 12, 1996\"\n.UC 7\n.SH NAME\n\\fBstrcspn\\fP \\- span the complement of a string\n.SH SYNOPSIS\n.B #include <string.h>\n.sp\n.B size_t\n.br\n\\fBstrcspn\\fP(s, charset)\n.br\n.I char *s;\n.br\n.I char *charset;\n.SH DESCRIPTION\nThe\n.BR strcspn ()\nfunction\nspans the initial part of the null-terminated string\n.I s\nas long as the characters from\n.I s\ndo not occur in string\n.I charset\n(it\nspans the\n.I complement\nof\n.I charset ) .\n.SH RETURN VALUES\nThe\n.BR strcspn ()\nfunction\nreturns the number of characters spanned.\n.SH SEE ALSO\nindex(3), memchr(3), rindex(3), strchr(3),\nstrpbrk(3),\nstrrchr(3),\nstrsep(3),\nstrspn(3),\nstrstr(3),\nstrtok(3)\n.SH STANDARDS\nThe\n.BR strcspn ()\nfunction\nconforms to\nANSI C X3.159-1989 (``ANSI C'').\n"
  },
  {
    "path": "share/man/man3/strftime.3",
    "content": ".\\\" Copyright (c) 1989, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" This code is derived from software contributed to Berkeley by\n.\\\" the American National Standards Committee X3, on Information\n.\\\" Processing Systems.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)strftime.3\t8.1.1 (2.11BSD) 1995/04/01\n.\\\"\n.TH STRFTIME 3 \"April 1, 1995\"\n.UC 5\n.SH NAME\nstrftime \\- format date and time\n.SH SYNOPSIS\n.B #include <sys/types.h>\n.br\n.B #include <time.h>\n.br\n.B #include <string.h>\n.br\n.sp\n.B size_t strftime(buf, maxsize, format, timeptr)\n.br\n.B char *buf;\n.br\n.B size_t maxsize;\n.br\n.B char *format;\n.br\n.B struct tm *timeptr;\n.PP\n.SH DESCRIPTION\nThe\n.B strftime()\nfunction formats the information from\n.I timeptr\ninto the buffer\n.I buf\naccording to the string pointed to by \\fIformat\\fP.\n.PP\nThe\n.I format\nstring consists of zero or more conversion specifications and\nordinary characters.\nAll ordinary characters are copied directly into the buffer.\nA conversion specification consists of a percent sign\n``%''\nand one other character.\n.PP\nNo more than\n.I maxsize\ncharacters will be placed into the array.\nIf the total number of resulting characters, including the terminating\nnull character, is not more than\n.IR maxsize ,\n.B strftime()\nreturns the number of characters in the array, not counting the\nterminating null.\nOtherwise, zero is returned.\n.PP\nEach conversion specification is replaced by the characters as\nfollows which are then copied into the buffer.\n.IP \\&%A \\w'xxxx'u+3\nis replaced by the full weekday name.\n.IP %a \\w'xxxx'u+3\nis replaced by the abbreviated weekday name, where the abbreviation\nis the first three characters.\n.IP \\&%B \\w'xxxx'u+3\nis replaced by the full month name.\n.IP \"%b or %h\" \\w'xxxx'u+3\nis replaced by the abbreviated month name, where the abbreviation is\nthe first three characters.\n.IP \\&%C \\w'xxxx'u+3\t\nis equivalent to\n``%a %b %e %H:%M:%S %Y''\n(the format produced by\n.IR asctime (3)).\n.IP %c \\w'xxxx'u+3\nis equivalent to\n``%m/%d/%y''.\n.IP \\&%D \\w'xxxx'u+3\nis replaced by the date in the format\n``mm/dd/yy''.\n.IP %d \\w'xxxx'u+3\nis replaced by the day of the month as a decimal number (01-31).\n.IP %e \\w'xxxx'u+3\nis replaced by the day of month as a decimal number (1-31); single\ndigits are preceded by a blank.\n.IP \\&%H \\w'xxxx'u+3\nis replaced by the hour (24-hour clock) as a decimal number (00-23).\n.IP \\&%I \\w'xxxx'u+3\nis replaced by the hour (12-hour clock) as a decimal number (01-12).\n.IP %j \\w'xxxx'u+3\nis replaced by the day of the year as a decimal number (001-366).\n.IP %k \\w'xxxx'u+3\nis replaced by the hour (24-hour clock) as a decimal number (0-23);\nsingle digits are preceded by a blank.\n.IP %l \\w'xxxx'u+3\nis replaced by the hour (12-hour clock) as a decimal number (1-12);\nsingle digits are preceded by a blank.\n.IP \\&%M \\w'xxxx'u+3\nis replaced by the minute as a decimal number (00-59).\n.IP %m \\w'xxxx'u+3\nis replaced by the month as a decimal number (01-12).\n.IP %n \\w'xxxx'u+3\nis replaced by a newline.\n.IP %p \\w'xxxx'u+3\nis replaced by either\n``AM''\nor\n``PM''\nas appropriate.\n.IP \\&%R \\w'xxxx'u+3\nis equivalent to\n``%H:%M''\n.IP %r \\w'xxxx'u+3\nis equivalent to\n``%I:%M:%S %p'' .\n.IP %t \\w'xxxx'u+3\nis replaced by a tab.\n.IP \\&%S \\w'xxxx'u+3\nis replaced by the second as a decimal number (00-60).\n.IP \"\\&%T or \\&%X\" \\w'xxxx'u+3\nis equivalent to\n\"%H:%M:%S\" .\n.IP \\&%U \\w'xxxx'u+3\nis replaced by the week number of the year (Sunday as the first day of\nthe week) as a decimal number (00-53).\n.IP \\&%W \\w'xxxx'u+3\nis replaced by the week number of the year (Monday as the first day of\nthe week) as a decimal number (00-53).\n.IP %w \\w'xxxx'u+3\nis replaced by the weekday (Sunday as the first day of the week)\nas a decimal number (0-6).\n.IP %x \\w'xxxx'u+3\nis equivalent to\n``%m/%d/%y %H:%M:%S'' .\n.IP \\&%Y \\w'xxxx'u+3\nis replaced by the year with century as a decimal number.\n.IP %y \\w'xxxx'u+3\nis replaced by the year without century as a decimal number (00-99).\n.IP \\&%Z \\w'xxxx'u+3\nis replaced by the time zone name.\n.IP %% \\w'xxxx'u+3\nis replaced by\n`%' .\n.PP\n.SH SEE ALSO\n.IR date (1),\n.IR ctime (3),\n.IR printf (1),\n.IR printf (3)\n.SH STANDARDS\nThe\n.B strftime()\nfunction\nconforms to\nANSI X C3.159-1989(``ANSI C'').\n.SH BUGS\nThere is no conversion specification for the phase of the moon.\n"
  },
  {
    "path": "share/man/man3/string.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)string.3\t6.5 (Berkeley) 10/22/87\n.\\\"\n.TH STRING 3  \"October 22, 1987\"\n.UC 4\n.SH NAME\nstrcat, strncat, strcmp, strncmp, strcasecmp, strncasecmp, strcpy,\nstrncpy, strlen, index, rindex \\- string operations\n.SH SYNOPSIS\n.nf\n.B #include <strings.h>\n.PP\n.B char *strcat(s, append)\n.B char *s, *append;\n.PP\n.B char *strncat(s, append, count)\n.B char *s, *append;\n.B int count;\n.PP\n.B strcmp(s1, s2)\n.B char *s1, *s2;\n.PP\n.B strncmp(s1, s2, count)\n.B char *s1, *s2;\n.B int count;\n.PP\n.B strcasecmp(s1, s2)\n.B char *s1, *s2;\n.PP\n.B strncasecmp(s1, s2, count)\n.B char *s1, *s2;\n.B int count;\n.PP\n.B char *strcpy(to, from)\n.B char *to, *from;\n.PP\n.B char *strncpy(to, from, count)\n.B char *to, *from;\n.B int count;\n.PP\n.B strlen(s)\n.B char *s;\n.PP\n.B char *index(s, c)\n.B char *s, c;\n.PP\n.B char *rindex(s, c)\n.B char *s, c;\n.fi\n.SH DESCRIPTION\nThese functions operate on null-terminated strings.\nThey do not check for overflow of any receiving string.\n.PP\n\\fIStrcat\\fP appends a copy of string \\fIappend\\fP to the end of string\n\\fIs\\fP. \\fIStrncat\\fP copies at most \\fIcount\\fP characters.  Both\nreturn a pointer to the null-terminated result.\n.PP\n\\fIStrcmp\\fP compares its arguments and returns an integer greater than,\nequal to, or less than 0, according as \\fIs1\\fP is lexicographically\ngreater than, equal to, or less than \\fIs2\\fP.  \\fIStrncmp\\fP makes the\nsame comparison but looks at at most \\fIcount\\fP characters.\n\\fIStrcasecmp\\fP and \\fIstrncasecmp\\fP are identical in function, but are\ncase insensitive.  The returned lexicographic difference reflects a\nconversion to lower-case.\n.PP\n\\fIStrcpy\\fP copies string \\fIfrom\\fP to \\fIto\\fP, stopping after the\nnull character has been moved.  \\fIStrncpy\\fP copies exactly \\fIcount\\fP\ncharacters, appending nulls if \\fIfrom\\fP is less than \\fIcount\\fP\ncharacters in length; the target may not be null-terminated if the\nlength of \\fIfrom\\fP is \\fIcount\\fP or more.  Both return \\fIto\\fP.\n.PP\n\\fIStrlen\\fP returns the number of non-null characters in \\fIs\\fP.\n.PP\n.I Index\n.RI ( rindex )\nreturns a pointer to the first (last) occurrence of character \n\\fIc\\fP in string \\fIs\\fP or zero if \\fIc\\fP does not occur in\nthe string.  Setting \\fIc\\fP to NULL works.\n"
  },
  {
    "path": "share/man/man3/strlcpy.3",
    "content": ".\\\"\t$OpenBSD: strlcpy.3,v 1.27 2019/01/25 00:19:25 millert Exp $\n.\\\"\n.\\\" Copyright (c) 1998, 2000 Todd C. Miller <millert@openbsd.org>\n.\\\"\n.\\\" Permission to use, copy, modify, and distribute this software for any\n.\\\" purpose with or without fee is hereby granted, provided that the above\n.\\\" copyright notice and this permission notice appear in all copies.\n.\\\"\n.\\\" THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n.\\\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n.\\\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n.\\\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n.\\\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n.\\\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n.\\\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n.\\\"\n.Dd $Mdocdate: January 25 2019 $\n.Dt STRLCPY 3\n.Os\n.Sh NAME\n.Nm strlcpy ,\n.Nm strlcat\n.Nd size-bounded string copying and concatenation\n.Sh SYNOPSIS\n.In string.h\n.Ft size_t\n.Fn strlcpy \"char *dst\" \"const char *src\" \"size_t dstsize\"\n.Ft size_t\n.Fn strlcat \"char *dst\" \"const char *src\" \"size_t dstsize\"\n.Sh DESCRIPTION\nThe\n.Fn strlcpy\nand\n.Fn strlcat\nfunctions copy and concatenate strings with the\nsame input parameters and output result as\n.Xr snprintf 3 .\nThey are designed to be safer, more consistent, and less error\nprone replacements for the easily misused functions\n.Xr strncpy 3\nand\n.Xr strncat 3 .\n.Pp\n.Fn strlcpy\nand\n.Fn strlcat\ntake the full size of the destination buffer and guarantee\nNUL-termination if there is room.\nNote that room for the NUL should be included in\n.Fa dstsize .\n.Pp\n.Fn strlcpy\ncopies up to\n.Fa dstsize\n\\- 1 characters from the string\n.Fa src\nto\n.Fa dst ,\nNUL-terminating the result if\n.Fa dstsize\nis not 0.\n.Pp\n.Fn strlcat\nappends string\n.Fa src\nto the end of\n.Fa dst .\nIt will append at most\n.Fa dstsize\n\\- strlen(dst) \\- 1 characters.\nIt will then NUL-terminate, unless\n.Fa dstsize\nis 0 or the original\n.Fa dst\nstring was longer than\n.Fa dstsize\n(in practice this should not happen\nas it means that either\n.Fa dstsize\nis incorrect or that\n.Fa dst\nis not a proper string).\n.Pp\nIf the\n.Fa src\nand\n.Fa dst\nstrings overlap, the behavior is undefined.\n.Sh RETURN VALUES\nBesides quibbles over the return type\n.Pf ( Va size_t\nversus\n.Va int )\nand signal handler safety\n.Pf ( Xr snprintf 3\nis not entirely safe on some systems), the\nfollowing two are equivalent:\n.Bd -literal -offset indent\nn = strlcpy(dst, src, len);\nn = snprintf(dst, len, \"%s\", src);\n.Ed\n.Pp\nLike\n.Xr snprintf 3 ,\nthe\n.Fn strlcpy\nand\n.Fn strlcat\nfunctions return the total length of the string they tried to create.\nFor\n.Fn strlcpy\nthat means the length of\n.Fa src .\nFor\n.Fn strlcat\nthat means the initial length of\n.Fa dst\nplus\nthe length of\n.Fa src .\n.Pp\nIf the return value is\n.Cm >=\n.Va dstsize ,\nthe output string has been truncated.\nIt is the caller's responsibility to handle this.\n.Sh EXAMPLES\nThe following code fragment illustrates the simple case:\n.Bd -literal -offset indent\nchar *s, *p, buf[BUFSIZ];\n\n\\&...\n\n(void)strlcpy(buf, s, sizeof(buf));\n(void)strlcat(buf, p, sizeof(buf));\n.Ed\n.Pp\nTo detect truncation, perhaps while building a pathname, something\nlike the following might be used:\n.Bd -literal -offset indent\nchar *dir, *file, pname[PATH_MAX];\n\n\\&...\n\nif (strlcpy(pname, dir, sizeof(pname)) >= sizeof(pname))\n\tgoto toolong;\nif (strlcat(pname, file, sizeof(pname)) >= sizeof(pname))\n\tgoto toolong;\n.Ed\n.Pp\nSince it is known how many characters were copied the first time, things\ncan be sped up a bit by using a copy instead of an append:\n.Bd -literal -offset indent\nchar *dir, *file, pname[PATH_MAX];\nsize_t n;\n\n\\&...\n\nn = strlcpy(pname, dir, sizeof(pname));\nif (n >= sizeof(pname))\n\tgoto toolong;\nif (strlcpy(pname + n, file, sizeof(pname) - n) >= sizeof(pname) - n)\n\tgoto toolong;\n.Ed\n.Pp\nHowever, one may question the validity of such optimizations, as they\ndefeat the whole purpose of\n.Fn strlcpy\nand\n.Fn strlcat .\nAs a matter of fact, the first version of this manual page got it wrong.\n.Sh SEE ALSO\n.Xr snprintf 3 ,\n.Xr strncat 3 ,\n.Xr strncpy 3 ,\n.Xr wcslcpy 3\n.Sh HISTORY\n.Fn strlcpy\nand\n.Fn strlcat\nfirst appeared in\n.Ox 2.4 .\n.Sh AUTHORS\n.Fn strlcpy\nand\n.Fn strlcat\nwere created by\n.An Todd C. Miller Aq Mt millert@openbsd.org .\n"
  },
  {
    "path": "share/man/man3/strpbrk.3",
    "content": ".\\\" Copyright (c) 1990, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" This code is derived from software contributed to Berkeley by\n.\\\" Chris Torek and the American National Standards Committee X3,\n.\\\" on Information Processing Systems.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)strpbrk.3\t8.1.1 (2.11BSD) 1996/1/12\n.\\\"\n.TH STRPBRK 3 \"January 12, 1996\"\n.UC 7\n.SH NAME\n\\fBstrpbrk\\fP \\- locate multiple characters in string\n.SH SYNOPSIS\n.B #include <string.h>\n.sp\n.B char *\n.br\n\\fBstrpbrk\\fP(s, charset)\n.br\n.I char *s;\n.br\n.I char *charset;\n.SH DESCRIPTION\nThe\n.BR strpbrk ()\nfunction\nlocates in the null-terminated string\n.I s\nthe first occurrence of any character in the string\n.I charset\nand returns a pointer to this character.\nIf no characters from\n.I charset\noccur anywhere in\n.I s\n.BR strpbrk ()\nreturns NULL.\n.SH SEE ALSO\nindex(3),\nmemchr(3),\nrindex(3),\nstrchr(3),\nstrcspn(3),\nstrrchr(3),\nstrsep(3),\nstrspn(3),\nstrstr(3),\nstrtok(3)\n.SH STANDARDS\nThe\n.BR strpbrk ()\nfunction\nconforms to\nANSI C X3.159-1989 )``ANSI C'').\n"
  },
  {
    "path": "share/man/man3/strsep.3",
    "content": ".\\\" Copyright (c) 1990, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" This code is derived from software contributed to Berkeley by\n.\\\" Chris Torek.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"\t@(#)strsep.3\t8.1.1 (2.11BSD) 1996/1/12\n.\\\"\n.TH STRSEP 3 \"January 12, 1996\"\n.UC 7\n.SH NAME\n\\fBstrsep\\fP \\- separate strings\n.SH SYNOPSIS\n.B #include <string.h>\n.sp\n.B char *\n.br\n\\fBstrsep\\fP(stringp, delim)\n.br\n.I char **stringp;\n.br\n.I char *delim;\n.SH DESCRIPTION\nThe\n.BR strsep ()\nfunction locates, in the string referenced by\n.I *stringp ,\nthe first occurrence of any character in the string\n.I delim\n(or the terminating\n`\\e0'\ncharacter) and replaces it with a\n`\\e0'.\nThe location of the next character after the delimiter character\n(or NULL, if the end of the string was reached) is stored in\n.I *stringp .\nThe original value of\n.I *stringp\nis returned.\n.PP\nAn ``empty'' field, i.e. one caused by two adjacent delimiter characters,\ncan be detected by comparing the location referenced by the pointer returned\nin\n.I *stringp\nto\n`\\e0'.\n.PP\nIf\n.I *stringp\nis initially\n.BR NULL ,\n.BR strsep ()\nreturns\n.BR NULL .\n.SH EXAMPLES\nThe following uses\n.BR strsep ()\nto parse a string, containing tokens delimited by white space, into an\nargument vector:\n.sp\n.nf\n.cs R 24\nchar **ap, *argv[10], *inputstring;\n\nfor (ap = argv; (*ap = strsep(&inputstring, \" \\et\")) != NULL;)\n\tif (**ap != '\\e0')\n\t\t++ap;\n.br\n.cs R\n.fi\n.SH HISTORY\nThe\n.BR strsep ()\nfunction\nis intended as a replacement for the\n.BR strtok ()\nfunction.\nWhile the\n.BR strtok ()\nfunction should be preferred for portability reasons (it conforms to\nANSI C X3.159-1989 (``ANSI C''))\nit is unable to handle empty fields, i.e. detect fields delimited by\ntwo adjacent delimiter characters, or to be used for more than a single\nstring at a time.\nThe\n.BR strsep ()\nfunction first appeared in 4.4BSD.\n"
  },
  {
    "path": "share/man/man3/strspn.3",
    "content": ".\\\" Copyright (c) 1990, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" This code is derived from software contributed to Berkeley by\n.\\\" Chris Torek and the American National Standards Committee X3,\n.\\\" on Information Processing Systems.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)strspn.3\t8.1.1 (2.11BSD) 1996/1/12\n.\\\"\n.TH STRSPN 3 \"January 12, 1996\"\n.UC 7\n.SH NAME\n\\fBstrspn\\fP \\- span a string\n.SH SYNOPSIS\n.B #include <string.h>\n.sp\n.B size_t\n.br\n\\fBstrspn\\fP(s, charset)\n.br\n.I char *s;\n.br\n.I char *charset;\n.SH DESCRIPTION\nThe\n.BR strcspn ()\nfunction\nspans the initial part of the null-terminated string\n.I s\nas long as the characters from\n.I s\noccur in string\n.I charset .\n.SH RETURN VALUES\nThe\n.BR strspn ()\nfunction\nreturns the number of characters spanned.\n.SH SEE ALSO\nindex(3),\nmemchr(3),\nrindex(3),\nstrchr(3),\nstrcspn(3),\nstrpbrk(3),\nstrrchr(3),\nstrsep(3),\nstrstr(3),\nstrtok(3)\n.SH STANDARDS\nThe\n.BR strspn ()\nfunction\nconforms to\nANSI C X3.159-9189 (``ANSI C'').\n"
  },
  {
    "path": "share/man/man3/strstr.3",
    "content": ".\\\" Copyright (c) 1990, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" This code is derived from software contributed to Berkeley by\n.\\\" Chris Torek and the American National Standards Committee X3,\n.\\\" on Information Processing Systems.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)strstr.3\t8.1.1 (2.11BSD) 1996/1/15\n.\\\"\n.TH STRSTR 3 \"January 15, 1996\"\n.UC 7\n.SH NAME\n\\fBstrstr\\fP \\- locate a substring in a string\n.SH SYNOPSIS\n.B #include <string.h>\n.sp\n.B char *\n.br\n.B strstr(big, little)\n.br\n.I  char *big, *little;\n.br\n.SH DESCRIPTION\nThe\n.BR strstr ()\nfunction\nlocates the first occurrence of the null-terminated string\n.I little\nin the null-terminated string\n.IR big .\nIf\n.I little\nis the empty string,\n.BR strstr ()\nreturns\n.IR big ;\nif\n.I little\noccurs nowhere in\n.IR big ,\n.BR strstr ()\nreturns NULL;\notherwise\n.BR strstr ()\nreturns a pointer to the first character of the first occurrence of\n.IR little .\n.SH SEE ALSO\nindex(3),\nmemchr(3),\nrindex(3),\nstrchr(3),\nstrcspn(3),\nstrpbrk(3),\nstrrchr(3),\nstrsep(3),\nstrspn(3),\nstrtok(3)\n.SH STANDARDS\nThe\n.BR strstr ()\nfunction\nconforms to\nANSI C X3/159-1989 (``ANSI C'').\n"
  },
  {
    "path": "share/man/man3/strtok.3",
    "content": ".\\\" Copyright (c) 1988, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" This code is derived from software contributed to Berkeley by\n.\\\" the American National Standards Committee X3, on Information\n.\\\" Processing Systems.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)strtok.3\t8.2.1 (2.11BSD) 1996/1/12\n.\\\"\n.TH STRTOK 3 \"January 12, 1996\"\n.UC 7\n.SH NAME\n\\fBstrtok\\fP \\- string tokens\n.SH SYNOPSIS\n.B #include <string.h>\n.sp\n.B char *\n.br\n\\fBstrtok\\fP(str, sep)\n.br\n.I char *str;\n.br\n.I char *sep;\n.SH DESCRIPTION\n.B This interface is obsoleted by strsep(3).\n.PP\nThe\n.BR strtok ()\nfunction\nis used to isolate sequential tokens in a null-terminated string,\n.I str .\nThese tokens are separated in the string by at least one of the\ncharacters in\n.I sep .\nThe first time that\n.BR strtok ()\nis called,\n.I str\nshould be specified; subsequent calls, wishing to obtain further tokens\nfrom the same string, should pass a null pointer instead.\nThe separator string,\n.I sep ,\nmust be supplied each time, and may change between calls.\n.PP\nThe\n.BR strtok ()\nfunction\nreturns a pointer to the beginning of each subsequent token in the string,\nafter replacing the token itself with a\n.B NUL\ncharacter.\nWhen no more tokens remain, a null pointer is returned.\n.SH SEE ALSO\nindex(3),\nmemchr(3),\nrindex(3),\nstrchr(3),\nstrcspn(3),\nstrpbrk(3),\nstrrchr(3),\nstrsep(3),\nstrspn(3),\nstrstr(3\n.SH STANDARDS\nThe\n.BR strtok ()\nfunction\nconforms to\nANSI C X3.159-1989 (``ANSI C'').\n.SH BUGS\nThere is no way to get tokens from multiple strings simultaneously.\n.PP\nThe System V\n.BR strtok (),\nif handed a string containing only delimiter characters,\nwill not alter the next starting point, so that a call to\n.BR strtok ()\nwith a different (or empty) delimiter string\nmay return a\nnon-\\fBNULL\\fP\nvalue.\nSince this implementation always alters the next starting point,\nsuch a sequence of calls would always return\n.BR NULL .\n"
  },
  {
    "path": "share/man/man3/strtol.3",
    "content": ".\\\" Copyright (c) 1990, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" This code is derived from software contributed to Berkeley by\n.\\\" Chris Torek and the American National Standards Committee X3,\n.\\\" on Information Processing Systems.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)strtol.3\t8.1.1 (2.11BSD) 1996/1/12\n.\\\"\n.TH STRTOL 3 \"January 12, 1996\"\n.UC 7\n.SH NAME\n\\fBstrtol\\fP \\- convert string value to a long\n.SH SYNOPSIS\n.B #include <stdlib.h>\n.br\n.B #include <limits.h>\n.sp\n.B long\n.br\n\\fBstrtol\\fP(nptr, endptr, base)\n.br\n.I char *nptr;\n.br\n.I char **endptr;\n.br\n.I int base;\n.SH DESCRIPTION\nThe\n.BR strtol ()\nfunction\nconverts the string in\n.I nptr\nto a\n.I long\nvalue.\nThe conversion is done according to the given\n.IR base ,\nwhich must be between 2 and 36 inclusive,\nor be the special value 0.\n.PP\nThe string may begin with an arbitrary amount of white space\n(as determined by\nisspace(3))\nfollowed by a single optional\n`+'\nor\n`\\-'\nsign.\nIf\n.I base\nis zero or 16,\nthe string may then include a\n`0x'\nprefix,\nand the number will be read in base 16; otherwise, a zero\n.I base\nis taken as 10 (decimal) unless the next character is\n`0',\nin which case it is taken as 8 (octal).\n.PP\nThe remainder of the string is converted to a\n.I long\nvalue in the obvious manner,\nstopping at the first character which is not a valid digit\nin the given base.\n(In bases above 10, the letter\n`A'\nin either upper or lower case\nrepresents 10,\n`B'\nrepresents 11, and so forth, with\n`Z'\nrepresenting 35.)\n.PP\nIf\n.I endptr\nis non nil,\n.BR strtol ()\nstores the address of the first invalid character in\n.I *endptr .\nIf there were no digits at all, however,\n.BR strtol ()\nstores the original value of\n.I nptr\nin\n.IR *endptr .\n(Thus, if\n.I *nptr\nis not\n`\\e0'\nbut\n.I **endptr\nis\n`\\e0'\non return, the entire string was valid.)\n.SH RETURN VALUES\nThe\n.BR strtol ()\nfunction\nreturns the result of the conversion,\nunless the value would underflow or overflow.\nIf an underflow occurs,\n.BR strtol ()\nreturns\n.BR LONG_MIN .\nIf an overflow occurs,\n.BR strtol ()\nreturns\n.BR LONG_MAX .\nIn both cases,\n.B errno\nis set to\n.B ERANGE .\n.SH ERRORS\n.TP 15\n[ERANGE]\nThe given string was out of range; the value converted has been clamped.\n.SH SEE ALSO\natof(3),\natoi(3),\natol(3),\nstrtoul(3)\n.SH STANDARDS\nThe\n.BR strtol ()\nfunction\nconforms to\nANSI C X3.159-1989 (``ANSI C'').\n.SH BUGS\nIgnores the current locale.\n"
  },
  {
    "path": "share/man/man3/strtoul.3",
    "content": ".\\\" Copyright (c) 1990, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" This code is derived from software contributed to Berkeley by\n.\\\" Chris Torek and the American National Standards Committee X3,\n.\\\" on Information Processing Systems.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)strtoul.3\t8.1.1 (2.11BSD) 1996/1/12\n.\\\"\n.TH STRTOUL 3 \"January 12, 1996\"\n.UC 7\n.SH NAME\n\\fBstrtoul\\fP \\- convert a string to an unsigned long\n.SH SYNOPSIS\n.B #include <stdlib.h>\n.br\n.B #include <limits.h>\n.sp\n.B unsigned long\n.br\n\\fBstrtoul\\fP(nptr, endptr, base)\n.br\n.I char *nptr;\n.br\n.I char **endptr;\n.br\n.I int base;\n.SH DESCRIPTION\nThe\n.BR strtoul ()\nfunction\nconverts the string in\n.I nptr\nto an\n.I unsigned long\nvalue.\nThe conversion is done according to the given\n.IR base ,\nwhich must be between 2 and 36 inclusive,\nor be the special value 0.\n.PP\nThe string may begin with an arbitrary amount of white space\n(as determined by\nisspace(3))\nfollowed by a single optional\n`+'\nor\n`\\-'\nsign.\nIf\n.I base\nis zero or 16,\nthe string may then include a\n`0x'\nprefix,\nand the number will be read in base 16; otherwise, a zero\n.I base\nis taken as 10 (decimal) unless the next character is\n`0',\nin which case it is taken as 8 (octal).\n.PP\nThe remainder of the string is converted to an\n.I unsigned long\nvalue in the obvious manner,\nstopping at the end of the string\nor at the first character that does not produce a valid digit\nin the given base.\n(In bases above 10, the letter\n`A'\nin either upper or lower case\nrepresents 10,\n`B'\nrepresents 11, and so forth, with\n`Z'\nrepresenting 35.)\n.PP\nIf\n.I endptr\nis non nil,\n.BR strtoul ()\nstores the address of the first invalid character in\n.I *endptr .\nIf there were no digits at all, however,\n.BR strtoul ()\nstores the original value of\n.I nptr\nin\n.I *endptr .\n(Thus, if\n.I *nptr\nis not\n`\\e0'\nbut\n.I **endptr\nis\n`\\e0'\non return, the entire string was valid.)\n.SH RETURN VALUES\nThe\n.BR strtoul ()\nfunction\nreturns either the result of the conversion\nor, if there was a leading minus sign,\nthe negation of the result of the conversion,\nunless the original (non-negated) value would overflow;\nin the latter case,\n.BR strtoul ()\nreturns\n.B ULONG_MAX\nand sets the global variable\n.B errno\nto\n.B ERANGE .\n.SH ERRORS\n.TP 15\n[ERANGE]\nThe given string was out of range; the value converted has been clamped.\n.SH SEE ALSO\nstrtol(3)\n.SH STANDARDS\nThe\n.BR strtoul ()\nfunction\nconforms to\nANSI C X3.159-1989 (``ANSI C'').\n.SH BUGS\nIgnores the current locale.\n"
  },
  {
    "path": "share/man/man3/stty.3",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)stty.3c\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH STTY 3C \"May 15, 1985\"\n.UC 5\n.SH NAME\nstty, gtty \\- set and get terminal state (defunct)\n.SH SYNOPSIS\n.nf\n.B #include <sgtty.h>\n.sp\n.B stty(fd, buf)\n.B int fd;\n.B struct sgttyb *buf;\n.sp\n.B gtty(fd, buf)\n.B int fd;\n.B struct sgttyb *buf;\n.fi\n.SH DESCRIPTION\n.ft B\nThis interface is obsoleted by ioctl(2).\n.ft R\n.PP\n.I Stty\nsets the state of the terminal associated with\n.IR fd .\n.I Gtty\nretrieves the state of the terminal associated\nwith\n.IR fd .\nTo set the state of a terminal the call must have\nwrite permission.\n.PP\nThe\n.I stty\ncall is actually ``ioctl(fd, TIOCSETP, buf)'', while\nthe\n.I gtty\ncall is ``ioctl(fd, TIOCGETP, buf)''.\nSee \n.IR ioctl (2)\nand\n.IR tty (4)\nfor an explanation.\n.SH DIAGNOSTICS\nIf the call is successful 0 is returned, otherwise \\-1 is\nreturned and the global variable\n.I errno\ncontains the reason for the failure.\n.SH SEE ALSO\nioctl(2),\ntty(4)\n"
  },
  {
    "path": "share/man/man3/swab.3",
    "content": ".\\\"\t@(#)swab.3\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH SWAB 3  \"May 15, 1985\"\n.AT 3\n.nf\n.SH NAME\nswab \\- swap bytes\n.SH SYNOPSIS\n.nf\n.B swab(from, to, nbytes)\n.B char *from, *to;\n.fi\n.SH DESCRIPTION\n.I Swab\ncopies\n.I nbytes\nbytes pointed to by\n.I from\nto the position pointed to by\n.I to,\nexchanging adjacent even and odd bytes.\nIt is useful for carrying binary data between\nPDP11's and other machines.\n.I Nbytes\nshould be even.\n"
  },
  {
    "path": "share/man/man3/sysctl.3",
    "content": ".\\\" Copyright (c) 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"\t@(#)sysctl.3\t8.1.1 (2.11BSD GTE) 1/13/95\n.\\\"\n.TH SYSCTL 3 \"January 13, 1995\"\n.UC 4\n.SH NAME\nsysctl \\- get or set system information\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/sysctl.h>\n\nint\nsysctl(name, namelen, oldp, *oldlenp, *newp, newlen)\n   int *name;\n   u_int namelen;\n   void *oldp;\n   size_t *oldlenp;\n   void *newp;\n   size_t newlen;\n.ft R\n.fi\n.SH DESCRIPTION\nThe\n\\fBsysctl\\fP\nfunction retrieves system information and allows processes with\nappropriate privileges to set system information.\nThe information available from\n\\fBsysctl\\fP\nconsists of integers, strings, and tables.\nInformation may be retrieved and set from the command interface\nusing the \n\\fIsysctl\\fP(1)\nutility.\n.PP\nUnless explicitly noted below,\n\\fBsysctl\\fP\nreturns a consistent snapshot of the data requested.\nCalls to\n\\fBsysctl\\fP\nare serialized to avoid deadlock.\n.PP\nThe state is described using a ``Management Information Base'' (MIB)\nstyle name, listed in\n\\fIname\\fP,\nwhich is a\n\\fInamelen\\fP\nlength array of integers.\n.PP\nThe information is copied into the buffer specified by\n\\fIoldp\\fP.\nThe size of the buffer is given by the location specified by\n\\fIoldlenp\\fP\nbefore the call,\nand that location gives the amount of data copied after a successful call.\nIf the amount of data available is greater\nthan the size of the buffer supplied,\nthe call supplies as much data as fits in the buffer provided\nand returns with the error code ENOMEM.\nIf the old value is not desired,\n\\fIoldp\\fP\nand\n\\fIoldlenp\\fP\nshould be set to NULL.\n.PP\nThe size of the available data can be determined by calling \n\\fBsysctl\\fP\nwith a NULL parameter for\n\\fIoldp\\fP.\nThe size of the available data will be returned in the location pointed to by\n\\fIoldlenp\\fP.\nFor some operations, the amount of space may change often.\nFor these operations,\nthe system attempts to round up so that the returned size is\nlarge enough for a call to return the data shortly thereafter.\n.PP\nTo set a new value,\n\\fInewp\\fP\nis set to point to a buffer of length\n\\fInewlen\\fP\nfrom which the requested value is to be taken.\nIf a new value is not to be set,\n\\fInewp\\fP\nshould be set to NULL and\n\\fInewlen\\fP\nset to 0.\n.PP\nThe top level names are defined with a CTL_ prefix in\n\\fI<sys/sysctl.h>\\fP,\nand are as follows.\nThe next and subsequent levels down are found in the include files\nlisted here, and described in separate sections below.\n.PP\n.nf\n.ta .25i 1.5i 3.75i 4.5i\n\tName\tNext level names\tDescription\n\tCTL\\_DEBUG\tsys/sysctl.h\tDebugging\n\tCTL\\_FS\tsys/sysctl.h\tFile system\n\tCTL\\_HW\tsys/sysctl.h\tGeneric CPU, I/O\n\tCTL\\_KERN\tsys/sysctl.h\tHigh kernel limits\n\tCTL\\_MACHDEP\tsys/sysctl.h\tMachine dependent\n\tCTL\\_NET\tsys/socket.h\tNetworking\n\tCTL\\_USER\tsys/sysctl.h\tUser-level\n\tCTL\\_VM\tvm/vm_param.h\tVirtual memory\n.fi\n.PP\nFor example, the following retrieves the maximum number of processes allowed\nin the system:\n.sp\n.nf\n.in +.5i\nint mib[2], maxproc;\nsize_t len;\n.sp\nmib[0] = CTL_KERN;\nmib[1] = KERN_MAXPROC;\nlen = sizeof(maxproc);\nsysctl(mib, 2, &maxproc, &len, NULL, 0);\n.in -.5i\n.sp\nTo retrieve the standard search path for the system utilities:\n.sp\n.nf\n.in +.5i\nint mib[2];\nsize_t len;\nchar *p;\n\nmib[0] = CTL_USER;\nmib[1] = USER_CS_PATH;\nsysctl(mib, 2, NULL, &len, NULL, 0);\np = malloc(len);\nsysctl(mib, 2, p, &len, NULL, 0);\n.in -.5i\n.fi\n.SH CTL_DEBUG\nThe debugging variables vary from system to system.\nA debugging variable may be added or deleted without need to recompile\n\\fBsysctl\\fP\nto know about it.\nEach time it runs,\n\\fBsysctl\\fP\ngets the list of debugging variables from the kernel and\ndisplays their current values.\nThe system defines twenty \n\\fIstruct ctldebug\\fP\nvariables named \n\\fIdebug0\\fP\nthrough\n\\fIdebug19\\fP.\nThey are declared as separate variables so that they can be\nindividually initialized at the location of their associated variable.\nThe loader prevents multiple use of the same variable by issuing errors\nif a variable is initialized in more than one place.\nFor example, to export the variable\n\\fIdospecialcheck\\fP\nas a debugging variable, the following declaration would be used:\n.sp\n.nf\n.in +.5i\nint dospecialcheck = 1;\nstruct ctldebug debug5 = { \"dospecialcheck\", &dospecialcheck };\n.in -.5i\n.fi\n.SH CTL_FS\nThere are currently no second level names for the file system.\n.SH CTL_HW\nThe string and integer information available for the CTL_HW level\nis detailed below.\nThe changeable column shows whether a process with appropriate\nprivilege may change the value.\n.sp\n.nf\n.ta .25i 2.75i 3.75i\n\tSecond level name\tType\tChangeable\n\tHW\\_MACHINE\tstring\tno\n\tHW\\_MODEL\tstring\tno\n\tHW\\_NCPU\tinteger\tno\n\tHW\\_BYTEORDER\tinteger\tno\n\tHW\\_PHYSMEM\tinteger\tno\n\tHW\\_USERMEM\tinteger\tno\n\tHW\\_PAGESIZE\tinteger\tno\n.\\\".It HW\\_DISKNAMES\tinteger\tno\n.\\\".It HW\\_DISKSTATS\tinteger\tno\n\tHW\\_MACHINE_ARCH\tstring\tno\n.fi\n.PP\n.ta .5i\nHW_MACHINE\n.br\n\tThe machine class.\n.sp\nHW_MODEL\n.br\n\tThe machine model.\n.sp\nHW_NCPU\n.br\n\tThe number of cpus.\n.sp\nHW_BYTEORDER\n.br\n\tThe byteorder (3412, 4321, or 1234).\n.sp\nHW_PHYSMEM\n.br\n\tThe bytes of physical memory.\n.sp\nHW_USERMEM\n.br\n\tThe bytes of non-kernel memory.\n.sp\nHW_PAGESIZE\n.br\n\tThe software page size.\n.sp\n.\\\".It Fa HW_DISKNAMES\n.\\\".It Fa HW_DISKSTATS\nHW_MACHINE_ARCH\n.br\n\tThe machine architecture.\n.sp\n.SH CTL_KERN\nThe string and integer information available for the CTL_KERN level\nis detailed below.\nThe changeable column shows whether a process with appropriate\nprivilege may change the value.\nThe types of data currently available are process information,\nsystem inodes, the open file entries, routing table entries,\nvirtual memory statistics, load average history, and clock rate\ninformation.\n.sp\n.nf\n.ta .25i 2.75i 4.5i\n\n\tSecond level name\tType\tChangeable\n\tKERN\\_ARGMAX\tinteger\tno\n\tKERN\\_BOOTTIME\tstruct timeval\tno\n\tKERN\\_CHOWN\\_RESTRICTED\tinteger\tno\n\tKERN\\_CLOCKRATE\tstruct clockinfo\tno\n\tKERN\\_FILE\tstruct file\tno\n\tKERN\\_HOSTID\tlong\tyes\n\tKERN\\_HOSTNAME\tstring\tyes\n\tKERN\\_JOB\\_CONTROL\tinteger\tno\n.\\\"KERN\\_LINK\\_MAX\tinteger\tno\n\tKERN\\_MAXFILES\tinteger\tno\n\tKERN\\_MAXPROC\tinteger\tno\n\tKERN\\_MAXINODES\tinteger\tno\n\tKERN\\_MAXTEXTS\tinteger\tno\n.\\\"KERN\\_MAX\\_CANON\tinteger\tno\n.\\\"KERN\\_MAX\\_INPUT\tinteger\tno\n.\\\"KERN\\_NAME\\_MAX\tinteger\tno\n\tKERN\\_NGROUPS\tinteger\tno\n.\\\"KERN\\_NO\\_TRUNC\tinteger\tno\n\tKERN\\_OSRELEASE\tstring\tno\n\tKERN\\_OSREV\tinteger\tno\n\tKERN\\_OSTYPE\tstring\tno\n\tKERN\\_OSVERSION\tstring\tno\n.\\\"KERN\\_PATH\\_MAX\tinteger\tno\n.\\\"KERN\\_PIPE\\_BUF\tinteger\tno\n\tKERN\\_POSIX1\tinteger\tno\n\tKERN\\_PROC\tstruct proc\tno\n\tKERN\\_PROF\tnode\tnot applicable\n\tKERN\\_SAVED\\_IDS\tinteger\tno\n\tKERN\\_SECURELVL\tinteger\traise only\n\tKERN\\_TEXT\tstruct text\tno\n.\\\"KERN\\_VDISABLE\tinteger\tno\n\tKERN\\_VERSION\tstring\tno\n\tKERN\\_INODE\tstruct inode\tno\n.fi\n.PP\nKERN_ARGMAX\n.br\n.in +.5i\nThe maximum bytes of argument to \\fBexec(2)\\fP.\n.sp\n.in -.5i\nKERN_BOOTTIME\n.br\n.in +.5i\nA \\fIstruct timeval\\fP structure is returned.\nThis structure contains the time that the system was booted.\n.sp\n.in -.5i\n.\\\"KERN_CHOWN_RESTRICTED\n.\\\"Return 1 if appropriate privileges are required for the\n.\\\".Xr chown 2\n.\\\"system call, otherwise 0.\nKERN_CLOCKRATE\n.br\n.in +.5i\nA \\fIstruct clockinfo\\fP structure is returned.\nThis structure contains the clock, statistics clock and profiling clock\nfrequencies, and the number of micro-seconds per hz tick.\n.sp\n.in -.5i\nKERN_FILE\n.br\n.in +.5i\nReturn the entire file table as an array of extended \\fIfile\\fP\nstructures.\nEach element of the array contains the kernel address of a file\n\\fIstruct inode *\\fP\nfollowed by the file itself\n\\fIstruct file\\fP.  There can never be more than \\fBKERN_MAXFILES\\fP\ninodes returned.\n.sp\n.in -.5i\nKERN_HOSTID\n.br\n.in +.5i\nGet or set the host id.\n.sp\n.in -.5i\nKERN_HOSTNAME\n.br\n.in +.5i\nGet or set the hostname.\n.sp\n.in -.5i\nKERN_JOB_CONTROL\n.br\n.in +.5i\nReturn 1 if job control is available on this system, otherwise 0.\n.sp\n.in -.5i\n.\\\"KERN_LINK_MAX\n.\\\"The maximum file link count.\nKERN_MAXFILES\n.br\n.in +.5i\nThe maximum number of open files that may be open in the system.\n.sp\n.in -.5i\nKERN_MAXPROC\n.br\n.in +.5i\nThe maximum number of simultaneous processes the system will allow.\n.sp\n.in -.5i\nKERN_MAXINODES\n.br\n.in +.5i\nThe maximum number of inodes available on the system.\n.sp\n.in -.5i\nKERN_MAXTEXTS\n.br\n.in +.5i\nThe maximum number of text structures available on the system.\n.sp\n.in -.5i\n.\\\"KERN_MAX_CANON\n.\\\"The maximum number of bytes in terminal canonical input line.\n.\\\"KERN_MAX_INPUT\n.\\\"The minimum maximum number of bytes for which space is available in\n.\\\"a terminal input queue.\n.\\\"KERN_NAME_MAX\n.\\\"The maximum number of bytes in a file name.\nKERN_NGROUPS\n.br\n.in +.5i\nThe maximum number of supplemental groups.\n.sp\n.in -.5i\n.\\\"KERN_NO_TRUNC\n.\\\"Return 1 if file names longer than KERN_NAME_MAX are truncated.\nKERN_OSRELEASE\n.br\n.in +.5i\nThe system release string.\n.sp\n.in -.5i\nKERN_OSREV\n.br\n.in +.5i\nThe system revision number.\n.sp\n.in -.5i\nKERN_OSTYPE\n.br\n.in +.5i\nThe system type string.\n.sp\n.in -.5i\nKERN_OSVERSION\n.br\n.in +.5i\nThe kernel build version.\n.sp\n.in -.5i\n.\\\"KERN_PATH_MAX\n.\\\"The maximum number of bytes in a pathname.\n.\\\"KERN_PIPE_BUF\n.\\\"The maximum number of bytes which will be written atomically to a pipe.\nKERN_POSIX1\n.br\n.in +.5i\nThe version of ISO/IEC 9945 (POSIX 1003.1) with which the system\nattempts to comply.\n.sp\n.in -.5i\nKERN_PROC\n.br\n.in +.5i\nReturn the entire process table, or a subset of it.\nAn array of\n\\fIstruct kinfo_proc\\fP\nstructures is returned,\nwhose size depends on the current number of such objects in the system.\n.sp\n.in -.5i\nThe third and fourth level names are as follows:\n.sp\n.nf\n.ta .25i 3.0i\n\tThird level name\tFourth level is:\n\tKERN\\_PROC\\_ALL\tNone\n\tKERN\\_PROC\\_PID\tA process ID\n\tKERN\\_PROC\\_PGRP\tA process group\n\tKERN\\_PROC\\_TTY\tA tty device\n\tKERN\\_PROC\\_UID\tA user ID\n\tKERN\\_PROC\\_RUID\tA real user ID\n\tKERN\\_PROF\tReturn kernel profiling information.\n.fi\n.sp\n.in +.5i\nIf the kernel is not compiled for profiling,\nattempts to retrieve any of the KERN_PROF values will\nfail with EOPNOTSUPP.\n.sp\n.in -.5i\nThe third level names for the string and integer profiling information \nis detailed below.\nThe changeable column shows whether a process with appropriate\nprivilege may change the value.\n.sp\n.in +.5i\n.nf\n.ta .25i 2.25i 4.25i\nThird level name\tType\tChangeable\n\tGPROF\\_STATE\tinteger\tyes\n\tGPROF\\_COUNT\tu_short[\\|]\tyes\n\tGPROF\\_FROMS\tu_short[\\|]\tyes\n\tGPROF\\_TOS\tstruct tostruct\tyes\n\tGPROF\\_GMONPARAM\tstruct gmonparam\tno\n.fi\n.PP\nThe variables are as follows:\n.sp\nGPROF_STATE\n.br\n.in +.5i\nReturns GMON_PROF_ON or GMON_PROF_OFF to show that profiling\nis running or stopped.\n.sp\n.in -.5i\nGPROF_COUNT\n.br\n.in +.5i\nArray of statistical program counter counts.\n.sp\n.in -.5i\nGPROF_FROMS\n.br\n.in +.5i\nArray indexed by program counter of call-from points.\n.sp\n.in -.5i\nGPROF_TOS\n.br\n.in +.5i\nArray of\n\\fIstruct tostruct\\fP\ndescribing destination of calls and their counts.\n.sp\n.in -.5i\nGPROF_GMONPARAM\n.br\n.in +.5i\nStructure giving the sizes of the above arrays.\n.in -.5i\n.sp\nKERN_SAVED_IDS\n.br\n.in +.5i\nReturns 1 if saved set-group and saved set-user ID is available.\n.sp\n.in -.5i\n.in -.5i\nKERN_SECURELVL\n.br\n.in +.5i\nThe system security level.\nThis level may be raised by processes with appropriate privilege.\nIt may only be lowered by process 1.\n.sp\n.in -.5i\n.\\\"KERN_VDISABLE\n.\\\"Returns the terminal character disabling value.\nKERN_VERSION\n.br\n.in +.5i\nThe system version string.\n.sp\n.in -.5i\nKERN_INODE\n.br\n.in +.5i\nReturn the entire inode table.\nNote, the inode table is not necessarily a consistent snapshot of\nthe system.\nThe returned data consists of an array whose size depends on the\ncurrent number of such objects in the system.\nEach element of the array contains the kernel address of a inode\n\\fIstruct inode *\\fP\nfollowed by the inode itself\n\\fIstruct inode\\fP.  There can never be more than \\fBKERN_MAXINODES\\fP\ninodes returned.\n.sp\n.in -.5i\nKERN_TEXT\n.br\n.in +.5i\nReturn the entire text table.  The returned data consists of an array whose\nsize depends on the current number of such objects active in the system. \nEach element of the array contains the kernel address of a text\n\\fIstruct text *\\fP followed by the text structure itself\n\\fIstruct text\\fP.  There can never be more structures than returned\nby \\fBKERN_MAXTEXTS\\fP.\n.in -.5i\n.SH CTL_MACHDEP\nThe set of variables defined is architecture dependent.\nMost architectures define at least the following variables.\n.nf\n.sp\n.ta .25i 2.75i 3.75i\n\tSecond level name\tType\tChangeable\n\tCPU_CONSDEV\tdev_t\tno\n.fi\n.SH CTL_NET\nThe string and integer information available for the CTL_NET level\nis detailed below.\nThe changeable column shows whether a process with appropriate\nprivilege may change the value.\n.nf\n.sp\n.ta .25i 2.25i 4.0i\n\tSecond level name\tType\tChangeable\n\tPF\\_ROUTE\trouting messages\tno\n\tPF\\_INET\tinternet values\tyes\n.fi\n.PP\nPF_ROUTE\n.br\n.in +.5i\nReturn the entire routing table or a subset of it.\nThe data is returned as a sequence of routing messages (see\n\\fIroute(4)\\fP\nfor the header file, format and meaning).\nThe length of each message is contained in the message header.\n.in -.5i\n.PP\nThe third level name is a protocol number, which is currently always 0.\nThe fourth level name is an address family, which may be set to 0 to\nselect all address families.\nThe fifth and sixth level names are as follows:\n.nf\n.sp\n.ta .25i 2.75i\n\tFifth level name\tSixth level is:\n\tNET\\_RT\\_FLAGS\trtflags\n\tNET\\_RT\\_DUMP\tNone\n\tNET\\_RT\\_IFLIST\tNone\n.fi\n.sp\nPF_INET\n.br\n.in +.5i\nGet or set various global information about the internet protocols.\nThe third level name is the protocol.\nThe fourth level name is the variable name.\nThe currently defined protocols and names are:\n.sp\n.in -.5i\n.nf\n.ta .25i 2.0i 3.75i 4.75i\n\tProtocol name\tVariable name\tType\tChangeable\n\tip\tforwarding\tinteger\tyes\n\tip\tredirect\tinteger\tyes\n\tip\tttl\tinteger\tyes\n\ticmp\tmaskrepl\tinteger\tyes\n\tudp\tchecksum\tinteger\tyes\n.fi\n.PP\nThe variables are as follows:\n.sp\nip.forwarding\n.br\n.in +.5i\nReturns 1 when IP forwarding is enabled for the host,\nmeaning that the host is acting as a router.\n.sp\n.in -.5i\nip.redirect\n.br\n.in +.5i\nReturns 1 when ICMP redirects may be sent by the host.\nThis option is ignored unless the host is routing IP packets,\nand should normally be enabled on all systems.\n.sp\n.in -.5i\nip.ttl\n.br\n.in +.5i\nThe maximum time-to-live (hop count) value for an IP packet sourced by\nthe system.\nThis value applies to normal transport protocols, not to ICMP.\n.sp\n.in -.5i\nicmp.maskrepl\n.br\n.in +.5i\nReturns 1 if ICMP network mask requests are to be answered.\n.sp\n.in -.5i\nudp.checksum\n.br\n.in +.5i\nReturns 1 when UDP checksums are being computed and checked.\nDisabling UDP checksums is strongly discouraged.\n.sp\n.in -.5i\n.SH CTL_USER\nThe string and integer information available for the CTL_USER level\nis detailed below.\nThe changeable column shows whether a process with appropriate\nprivilege may change the value.\n.sp\n.nf\n.ta .25i 3.0i 4.25i\n\tSecond level name\tType\tChangeable\n\tUSER\\_BC\\_BASE\\_MAX\tinteger\tno\n\tUSER\\_BC\\_DIM\\_MAX\tinteger\tno\n\tUSER\\_BC\\_SCALE\\_MAX\tinteger\tno\n\tUSER\\_BC\\_STRING\\_MAX\tinteger\tno\n\tUSER\\_COLL\\_WEIGHTS\\_MAX\tinteger\tno\n\tUSER\\_CS\\_PATH\tstring\tno\n\tUSER\\_EXPR\\_NEST\\_MAX\tinteger\tno\n\tUSER\\_LINE\\_MAX\tinteger\tno\n\tUSER\\_POSIX2\\_CHAR\\_TERM\tinteger\tno\n\tUSER\\_POSIX2\\_C\\_BIND\tinteger\tno\n\tUSER\\_POSIX2\\_C\\_DEV\tinteger\tno\n\tUSER\\_POSIX2\\_FORT\\_DEV\tinteger\tno\n\tUSER\\_POSIX2\\_FORT\\_RUN\tinteger\tno\n\tUSER\\_POSIX2\\_LOCALEDEF\tinteger\tno\n\tUSER\\_POSIX2\\_SW\\_DEV\tinteger\tno\n\tUSER\\_POSIX2\\_UPE\tinteger\tno\n\tUSER\\_POSIX2\\_VERSION\tinteger\tno\n\tUSER\\_RE\\_DUP\\_MAX\tinteger\tno\n\tUSER\\_STREAM\\_MAX\tinteger\tno\n\tUSER\\_TZNAME\\_MAX\tinteger\tno\n.fi\n.PP\nUSER_BC_BASE_MAX\n.br\n.in +.5i\nThe maximum ibase/obase values in the\n\\fIbc(1)\\fP\nutility.\n.sp\n.in -.5i\nUSER_BC_DIM_MAX\n.br\n.in +.5i\nThe maximum array size in the\n\\fIbc(1)\\fP\nutility.\n.sp\n.in -.5i\nUSER_BC_SCALE_MAX\n.br\n.in +.5i\nThe maximum scale value in the\n\\fIbc(1)\\fP\nutility.\n.sp\n.in -.5i\nUSER_BC_STRING_MAX\n.br\n.in +.5i\nThe maximum string length in the\n\\fIbc(1)\\fP\nutility.\n.sp\n.in -.5i\nUSER_COLL_WEIGHTS_MAX\n.br\n.in +.5i\nThe maximum number of weights that can be assigned to any entry of\nthe LC_COLLATE order keyword in the locale definition file.\n.sp\n.in -.5i\nUSER_CS_PATH\n.br\n.in +.5i\nReturn a value for the\n\\fIPATH\\fP\nenvironment variable that finds all the standard utilities.\n.sp\n.in -.5i\nUSER_EXPR_NEST_MAX\n.br\n.in +.5i\nThe maximum number of expressions that can be nested within\nparenthesis by the\n\\fIexpr(1)\\fP\nutility.\n.sp\n.in -.5i\nUSER_LINE_MAX\n.br\n.in +.5i\nThe maximum length in bytes of a text-processing utility's input\nline.\n.sp\n.in -.5i\nUSER_POSIX2_CHAR_TERM\n.br\n.in +.5i\nReturn 1 if the system supports at least one terminal type capable of\nall operations described in POSIX 1003.2, otherwise 0.\n.sp\n.in -.5i\nUSER_POSIX2_C_BIND\n.br\n.in +.5i\nReturn 1 if the system's C-language development facilities support the\nC-Language Bindings Option, otherwise 0.\n.sp\n.in -.5i\nUSER_POSIX2_C_DEV\n.br\n.in +.5i\nReturn 1 if the system supports the C-Language Development Utilities Option,\notherwise 0.\n.sp\n.in -.5i\nUSER_POSIX2_FORT_DEV\n.br\n.in +.5i\nReturn 1 if the system supports the FORTRAN Development Utilities Option,\notherwise 0.\n.sp\n.in -.5i\nUSER_POSIX2_FORT_RUN\n.br\n.in +.5i\nReturn 1 if the system supports the FORTRAN Runtime Utilities Option,\notherwise 0.\n.sp\n.in -.5i\nUSER_POSIX2_LOCALEDEF\n.br\n.in +.5i\nReturn 1 if the system supports the creation of locales, otherwise 0.\n.sp\n.in -.5i\nUSER_POSIX2_SW_DEV\n.br\n.in +.5i\nReturn 1 if the system supports the Software Development Utilities Option,\notherwise 0.\n.sp\n.in -.5i\nUSER_POSIX2_UPE\n.br\n.in +.5i\nReturn 1 if the system supports the User Portability Utilities Option,\notherwise 0.\n.sp\n.in -.5i\nUSER_POSIX2_VERSION\n.br\n.in +.5i\nThe version of POSIX 1003.2 with which the system attempts to comply.\n.sp\n.in -.5i\nUSER_RE_DUP_MAX\n.br\n.in +.5i\nThe maximum number of repeated occurrences of a regular expression\npermitted when using interval notation.\n.sp\n.in -.5i\nUSER_STREAM_MAX\n.br\n.in +.5i\nThe minimum maximum number of streams that a process may have open\nat any one time.\n.sp\n.in -.5i\nUSER_TZNAME_MAX\n.br\n.in +.5i\nThe minimum maximum number of types supported for the name of a\ntimezone.\n.br\n.in -.5i\n.SH CTL_VM\nThe string and integer information available for the CTL_VM level\nis detailed below.\nThe changeable column shows whether a process with appropriate\nprivilege may change the value.\n.sp\n.nf\n.ta .25i 2.25i 4.0i\n\tSecond level name\tType\tChangeable\n\tVM\\_LOADAVG\tstruct loadavg\tno\n\tVM\\_METER\tstruct vmtotal\tno\n\tVM\\_SWAPMAP\tstruct map\tno\n\tVM\\_COREMAP\tstruct map\tno\n.fi\n.PP\nVM_LOADAVG\n.br\n.in +.5i\nReturn the load average history.\nThe returned data consists of a\n\\fIstruct loadavg\\fP.\n.sp\n.in -.5i\nVM_METER\n.br\n.in +.5i\nReturn the system wide virtual memory statistics.\nThe returned data consists of a\n\\fIstruct vmtotal\\fP.\n.br\n.in -.5i\n.sp\nVM_SWAPMAP\n.br\n.in +.5i\nReturn the swapmap.  The size of this structure is fixed and may be\ndetermined by specifying a \\fBoldlenp\\fP initialized to zero, the kernel\nwill fill in the size of the swapmap.\n.in -.5i\n.sp\nVM_COREMAP\n.br\n.in +.5i\nSame as for swapmap above except that the core allocation map is\nreturned.\n.in -.5i\n.SH RETURN VALUES\nIf the call to\n\\fBsysctl\\fP\nis successful, 0 is returned.\nOtherwise \\-1 is returned and\n\\fIerrno\\fP\nis set appropriately.\n.SH ERRORS\nThe following errors may be reported:\n.TP 15\nEFAULT\nThe buffer\n\\fIname\\fP,\n\\fIoldp\\fP,\n\\fInewp\\fP,\nor length pointer\n\\fIoldlenp\\fP\ncontains an invalid address.\n.TP 15\nEINVAL\nThe\n\\fIname\\fP\narray is less than two or greater than CTL_MAXNAME.\n.TP 15\nEINVAL\nA non-null\n\\fInewp\\fP\nis given and its specified length in\n\\fInewlen\\fP\nis too large or too small.\n.TP 15\nENOMEM\nThe length pointed to by\n\\fIoldlenp\\fP\nis too short to hold the requested value.\n.TP 15\nENOTDIR\nThe\n\\fIname\\fP\narray specifies an intermediate rather than terminal name.\n.TP 15\nEOPNOTSUPP\nThe\n\\fIname\\fP\narray specifies a value that is unknown.\n.TP 15\nEPERM\nAn attempt is made to set a read-only value.\n.TP 15\nEPERM\nA process without appropriate privilege attempts to set a value.\n.SH FILES\n.TP 15\n<sys/sysctl.h>\ndefinitions for top level identifiers, second level kernel and hardware\nidentifiers, and user level identifiers\n.TP 15\n<sys/socket.h>\ndefinitions for second level network identifiers\n.TP 15\n<sys/gmon.h>\ndefinitions for third level profiling identifiers\n.TP 15\n<sys/vmparam.h>\ndefinitions for second level virtual memory identifiers\n.TP 15\n<netinet/in.h>\ndefinitions for third level Internet identifiers and\nfourth level IP identifiers\n.TP 15\n<netinet/icmp_var.h>\ndefinitions for fourth level ICMP identifiers\n.TP 15\n<netinet/udp_var.h>\ndefinitions for fourth level UDP identifiers\n.SH SEE ALSO\n.I sysctl(8)\n.SH HISTORY\nThe\n.B sysctl\nfunction first appeared in 4.4BSD.\n.PP\nThe KERN_TEXT, KERN_MAXTEXTS, VM_SWAPMAP, VM_COREMAP options are\n2.11BSD specific extensions to the 4.4BSD \\fIsysctl\\fP implmentation.\n.PP\nHaving KERN_FILE return the address of the file structure before the\nactual \\fIstruct file\\fP is a 2.11BSD enhancement.  The \\fIinode\\fP\n(\\fIvnode\\fP under 4.4) table was handled this way.\n"
  },
  {
    "path": "share/man/man3/syserrlst.3",
    "content": ".\\\" Public Domain, March 1996, Steven M. Schultz\n.\\\"\n.\\\"\t@(#)syserrlst.3\t1.1 (2.11BSD) 1996/3/26\n.\\\"\n.TH SYSERRLST 3  \"March 26, 1996\"\n.UC 2\n.SH NAME\nsyserrlst, __errlst \\- read system error messages from file\n.SH SYNOPSIS\n.nf\n.B char *\n.B syserrlst(err)\n.B int err;\n.PP\n.B char *\n.B __errlst(err, path);\n.B int err;\n.B char *path;\n.fi\n.SH DESCRIPTION\n.BR Syserrlst (3)\nreads the error message string corresponding to \\fIerr\\fP from the\nfile \\fI/etc/syserrlst\\fP.\n.PP\n.BR __errlst(3)\nreads the error message string corresponding to \\fIerr\\fP from the\nfile \\fIpath\\fP.  The file \\fIpath\\fP must be in the format described\nin \n.BR syserrlst (5).\n.PP\n.B NULL\nis returned if \\fIerr\\fP is out of bounds (negative or greater than the\nhighest message number in \\fI/etc/syserrlst\\fP or \\fIpath\\fP) or if the\nerror message file can not be opened.  It is the\nresponsibility of the caller (\\fBstrerror\\fP(3))\nto check for and properly handle the \\fINULL\\fP return.\n.SH \"RETURN VALUE\"\n.B NULL\nif an error was encountered in opening the error message file, if the\nerror was out of bounds, or if the file did not start with the correct\nmagic number.  Otherwise a \n.B \"char *\"\nis returned pointing to a static buffer containing the text of the error\nmessage.\n.SH ERRORS\n.BR syserrlst (3)\nand\n.BR __errlst (3)\ncan return any of the errors for the\n.BR open (2),\n.BR lseek (2),\nor\n.BR read (2)\nsystem calls.\n.SH \"SEE ALSO\"\nperror(3),\nstrerror(3),\nsyserrlst(5)\n.SH HISTORY\n.BR syserrlst (3),\nand\n.BR __errlst (3)\nwere created for 2.11BSD with the aim of saving 2kb of \\fBData\\fP space\nin programs which called \n.BR perror (3),\nor\n.BR strerror (3).\n.SH BUGS\nThe information is stored in a static buffer.\n"
  },
  {
    "path": "share/man/man3/syslog.3",
    "content": ".\\\" Copyright (c) 1985, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)syslog.3\t8.1.1 (2.11BSD) 1995/04/01\n.\\\"\n.TH SYSLOG 3 \"April 1, 1995\"\n.UC 5\n.SH NAME\nsyslog , vsyslog , openlog , closelog , setlogmask \\- control system log\n.SH SYNOPSIS\n.B #include <syslog.h>\n.br\n.B #include <varargs.h>\n.PP\n.B void syslog(priority, message, ...);\n.br\n.B int priority;\n.br\n.B char *message;\n.PP\n.B void vsyslog(priority, message, args);\n.br\n.B int priority;\n.br\n.B char *message;\n.br\n.B va_list args;\n.PP\n.B void openlog(ident, logopt, facility);\n.br\n.B char *ident;\n.br\n.B int logopt;\n.br\n.B int facility;\n.PP\n.B void closelog();\n.PP\n.B int setlogmask(maskpri);\n.br\n.B int maskpri;\n.SH DESCRIPTION\nThe\n.IR syslog ()\nfunction\nwrites\n.I message\nto the system message logger.\nThe message is then written to the system console, log files,\nlogged-in users, or forwarded to other machines as appropriate. (See\n.IR syslogd (8)).\n.PP\nThe message is identical to a\n.IR printf (3)\nformat string, except that\n.B %m\nis replaced by the current error\nmessage as denoted by the global variable \\fIerrno\\fP.\nSee\n.IR strerror (3)).\nA trailing newline is added if none is present.\n.PP\nThe\n.IR vsyslog ()\nfunction\nis an alternate form in which the arguments have already been captured\nusing the variable-length argument facilities of\n.IR varargs (3).\n.PP\nThe message is tagged with\n.IR priority .\nPriorities are encoded as a\n.I facility\nand a\n.IR level .\nThe facility describes the part of the system\ngenerating the message.\nThe level is selected from the following\n.I ordered\n(high to low) list:\n.IP LOG_EMERG \\w'LOG_AUTHORITY'u+3\nA panic condition.\nThis is normally broadcast to all users.\n.IP LOG_ALERT \\w'LOG_AUTHORITY'u+3\nA condition that should be corrected immediately, such as a corrupted\nsystem database.\n.IP LOG_CRIT \\w'LOG_AUTHORITY'u+3\nCritical conditions, e.g., hard device errors.\n.IP LOG_ERR \\w'LOG_AUTHORITY'u+3\nErrors.\n.IP LOG_WARNING \\w'LOG_AUTHORITY'u+3\nWarning messages.\n.IP LOG_NOTICE \\w'LOG_AUTHORITY'u+3\nConditions that are not error conditions,\nbut should possibly be handled specially.\n.IP LOG_INFO \\w'LOG_AUTHORITY'u+3\nInformational messages.\n.IP LOG_DEBUG \\w'LOG_AUTHORITY'u+3\nMessages that contain information\nnormally of use only when debugging a program.\n.PP\nThe\n.IR openlog ()\nfunction\nprovides for more specialized processing of the messages sent\nby\n.IR syslog ()\nand\n.IR vsyslog ().\nThe parameter\n.I ident\nis a string that will be prepended to every message.\nThe\n.I logopt\nargument\nis a bit field specifying logging options, which is formed by\n.B OR'ing\none or more of the following values:\n.IP LOG_CONS \\w'LOG_AUTHPRIV'u+3\nIf\n.IR syslog\ncannot pass the message to\n.IR syslogd\nit will attempt to write the message to the console (\\fB/dev/console\\fP).\n.IP LOG_NDELAY \\w'LOG_AUTHPRIV'u+3\nOpen the connection to\n.IR syslogd\nimmediately.\nNormally the open is delayed until the first message is logged.\nUseful for programs that need to manage the order in which file\ndescriptors are allocated.\n.IP LOG_PERROR \\w'LOG_AUTHPRIV'u+3\nWrite the message to standard error output as well to the system log.\n.IP LOG_PID \\w'LOG_AUTHPRIV'u+3\nLog the process id with each message: useful for identifying\ninstantiations of daemons.\n.PP\nThe\n.IR facility\nparameter encodes a default facility to be assigned to all messages\nthat do not have an explicit facility encoded:\n.IP LOG_AUTH \\w'LOG_AUTHPRIV'u+3\nThe authorization system:\n.IR login (1),\n.IR su (1),\n.IR getty (8),\netc.\n.IP LOG_AUTHPRIV \\w'LOG_AUTHPRIV'u+3\nThe same as\n.B LOG_AUTH ,\nbut logged to a file readable only by\nselected individuals.\n.IP LOG_CRON \\w'LOG_AUTHPRIV'u+3\nThe clock daemon.\n.IP LOG_DAEMON \\w'LOG_AUTHPRIV'u+3\nSystem daemons, such as\n.IR routed (8),\nthat are not provided for explicitly by other facilities.\n.IP LOG_KERN \\w'LOG_AUTHPRIV'u+3\nMessages generated by the kernel.\nThese cannot be generated by any user processes.\n.IP LOG_LPR \\w'LOG_AUTHPRIV'u+3\nThe line printer spooling system:\n.IR lpr (1),\n.IR lpc (8),\n.IR lpd (8),\netc.\n.IP LOG_MAIL \\w'LOG_AUTHPRIV'u+3\nThe mail system.\n.IP LOG_NEWS \\w'LOG_AUTHPRIV'u+3\nThe network news system.\n.IP LOG_SYSLOG \\w'LOG_AUTHPRIV'u+3\nMessages generated internally by\n.IR syslogd (8).\n.IP LOG_USER \\w'LOG_AUTHPRIV'u+3\nMessages generated by random user processes.\nThis is the default facility identifier if none is specified.\n.IP LOG_UUCP \\w'LOG_AUTHPRIV'u+3\nThe uucp system.\n.IP LOG_LOCAL0 \\w'LOG_AUTHPRIV'u+3\nReserved for local use.\nSimilarly for \\fBLOG_LOCAL1\\fP through \\fBLOG_LOCAL7\\fP.\n.PP\nThe\n.IR closelog\nfunction\ncan be used to close the log file.\n.PP\nThe\n.IR setlogmask\nfunction\nsets the log priority mask to\n.I maskpri\nand returns the previous mask.\nCalls to\n.IR syslog\nwith a priority not set in\n.I maskpri\nare rejected.\nThe mask for an individual priority\n.I pri\nis calculated by the macro\n.IR LOG_MASK (pri).\nThe mask for all priorities up to and including\n.I toppri\nis given by the macro\n.IR LOG_UPTO (toppri).\nThe default allows all priorities to be logged.\n.PP\n.SH RETURN VALUES\nThe routines\n.IR closelog (),\n.IR openlog (),\n.IR syslog ()\nand\n.IR vsyslog ()\nreturn no value.\n.PP\nThe routine\n.IR setlogmask ()\nalways returns the previous log mask level.\n.PP\n.SH EXAMPLES\n.IP \"\" 8\nsyslog(LOG_ALERT, \"who: internal error 23\");\n\nopenlog(\"ftpd\", LOG_PID, LOG_DAEMON);\nsetlogmask(LOG_UPTO(LOG_ERR));\nsyslog(LOG_INFO, \"Connection from host %d\", CallingHost);\n\nsyslog(LOG_INFO|LOG_LOCAL2, \"foobar error: %m\");\n.PP\n.SH SEE ALSO\n.I logger(1), syslogd(8)\n.SH BUGS\nUnder 2.11BSD the logfile \\fB/usr/adm/messages\\fP is used if a non\nnetworking kernel has been booted.  That file must be publically writeable\nin this case.\n.SH HISTORY\nThese\nfunctions appeared in 4.2BSD.\n"
  },
  {
    "path": "share/man/man3/system.3",
    "content": ".\\\"\t@(#)system.3\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH SYSTEM 3 \"May 15, 1985\"\n.AT 3\n.SH NAME\nsystem \\- issue a shell command\n.SH SYNOPSIS\n.nf\n.B system(string)\n.B char *string;\n.fi\n.SH DESCRIPTION\n.I System\ncauses the\n.I string\nto be given to\n.IR  sh (1)\nas input as if the string had been typed as a command\nat a terminal.\nThe current process waits until the shell has\ncompleted, then returns the exit status of the shell.\n.SH \"SEE ALSO\"\npopen(3S),\nexecve(2),\nwait(2)\n.SH DIAGNOSTICS\nExit status 127 indicates the shell couldn't be executed.\n"
  },
  {
    "path": "share/man/man3/termcap.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)termcap.3x\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH TERMCAP 3X \"May 15, 1985\"\n.UC 4\n.SH NAME\ntgetent, tgetnum, tgetflag, tgetstr, tgoto, tputs \\- terminal independent operation routines\n.SH SYNOPSIS\n.nf\n.B char PC;\n.B char *BC;\n.B char *UP;\n.B short ospeed;\n.PP\n.B tgetent(bp, name)\n.B char *bp, *name;\n.PP\n.B tgetnum(id)\n.B char *id;\n.PP\n.B tgetflag(id)\n.B char *id;\n.PP\n.B char *\n.B tgetstr(id, area)\n.B char *id, **area;\n.PP\n.B char *\n.B tgoto(cm, destcol, destline)\n.B char *cm;\n.PP\n.B tputs(cp, affcnt, outc)\n.B register char *cp;\n.B int affcnt;\n.B int (*outc)();\n.fi\n.SH DESCRIPTION\nThese functions extract and use capabilities from the terminal capability data\nbase\n.IR termcap (5).\nThese are low level routines;\nsee\n.IR curses (3X)\nfor a higher level package.\n.PP\n.I Tgetent\nextracts the entry for terminal\n.I name\ninto the buffer at\n.I bp.\n.I Bp\nshould be a character buffer of size\n1024 and must be retained through all subsequent calls\nto\n.I tgetnum,\n.I tgetflag,\nand\n.I tgetstr.\n.I Tgetent\nreturns \\-1 if it cannot open the\n.I termcap\nfile, 0 if the terminal name given does not have an entry,\nand 1 if all goes well.\nIt will look in the environment for a TERMCAP variable.\nIf found, and the value does not begin with a slash,\nand the terminal type\n.B name\nis the same as the environment string TERM,\nthe TERMCAP string is used instead of reading the termcap file.\nIf it does begin with a slash, the string is used as a path name rather than\n.I /etc/termcap.\nThis can speed up entry into programs that call\n.IR tgetent ,\nas well as to help debug new terminal descriptions\nor to make one for your terminal if you can't write the file\n.I /etc/termcap.\n.PP\n.I Tgetnum\ngets the numeric value of capability\n.I id,\nreturning \\-1 if is not given for the terminal.\n.I Tgetflag\nreturns 1 if the specified capability is present in\nthe terminal's entry, 0 if it is not.\n.I Tgetstr\nreturns the string value of the capability\n.I id,\nplaces it in the buffer at\n.I area,\nand advances the\n.I area\npointer.\nIt decodes the abbreviations for this field described in\n.IR termcap (5),\nexcept for cursor addressing and padding information.\n.I Tgetstr\nreturns NULL if the capability was not found.\n.PP\n.I Tgoto\nreturns a cursor addressing string decoded from\n.I cm\nto go to column\n.I destcol\nin line\n.I destline.\nIt uses the external variables\n.B UP\n(from the \\fBup\\fR capability)\nand\n.B BC\n(if \\fBbc\\fR is given rather than \\fBbs\\fR)\nif necessary to avoid placing \\fB\\en\\fR, \\fB^D\\fR or \\fB^@\\fR in\nthe returned string.\n(Programs which call tgoto should be sure to turn off the XTABS bit(s),\nsince\n.I tgoto\nmay now output a tab.\nNote that programs using termcap should in general turn off XTABS\nanyway since some terminals use control I for other functions,\nsuch as nondestructive space.)\nIf a \\fB%\\fR sequence is given which is not understood, then\n.I tgoto\nreturns \\*(lqOOPS\\*(rq.\n.PP\n.I Tputs\ndecodes the leading padding information of the string\n.IR cp ;\n.I affcnt\ngives the number of lines affected by the operation, or 1 if this is\nnot applicable,\n.I outc\nis a routine which is called with each character in turn.\nThe external variable\n.I ospeed\nshould contain the output speed of the terminal as encoded by\n.IR stty (3).\nThe external variable\n.B PC\nshould contain a pad character to be used (from the \\fBpc\\fR capability)\nif a null (\\fB^@\\fR) is inappropriate.\n.SH FILES\n.ta \\w'/usr/lib/libtermcap.a  'u\n/usr/lib/libtermcap.a\t\\-ltermcap library\n.br\n/etc/termcap\tdata base\n.DT\n.SH SEE ALSO\nex(1), curses(3X), termcap(5)\n.SH AUTHOR\nWilliam Joy\n"
  },
  {
    "path": "share/man/man3/time.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)time.3c\t6.1 (Berkeley) 5/9/85\n.\\\"\n.TH TIME 3C \"May 9, 1985\" \n.UC 4\n.SH NAME\ntime, ftime \\- get date and time\n.SH SYNOPSIS\n.nf\n.B long time(0)\n.PP\n.B long time(tloc)\n.B long *tloc;\n.PP\n.B #include <sys/types.h>\n.B #include <sys/timeb.h>\n.B ftime(tp)\n.B struct timeb *tp;\n.fi\n.SH DESCRIPTION\n.ft B\nThese interfaces are obsoleted by gettimeofday(2).\n.ft R\n.PP\n.I Time\nreturns the time since 00:00:00 GMT, Jan. 1, 1970, measured\nin seconds.\n.PP\nIf\n.I tloc\nis nonnull,\nthe return value is also stored in the\nplace to which\n.I tloc\npoints.\n.PP\nThe\n.I ftime\nentry fills in a structure pointed to by its argument,\nas defined by\n.RI < sys/timeb.h >:\n.ta .5i +\\w'unsigned 'u\n.nf\n.IP\n/*\n * Structure returned by ftime system call\n */\nstruct timeb\n{\n        time_t  time;\n        unsigned short millitm;\n        short   timezone;\n        short   dstflag;\n};\n.fi\n.PP\nThe structure contains the time since the epoch in seconds,\nup to 1000 milliseconds of more-precise interval,\nthe local time zone (measured in minutes of time westward from Greenwich),\nand a flag that, if nonzero, indicates that\nDaylight Saving time applies locally during the appropriate part of the year.\n.SH \"SEE ALSO\"\ndate(1), gettimeofday(2), settimeofday(2), ctime(3)\n"
  },
  {
    "path": "share/man/man3/times.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)times.3c\t6.1 (Berkeley) 5/9/85\n.\\\"\n.TH TIMES 3C \"May 9, 1985\"\n.UC 4\n.SH NAME\ntimes \\- get process times\n.SH SYNOPSIS\n.nf\n.B \"#include <sys/types.h>\n.B \"#include <sys/times.h>\n.PP\n.B times(buffer)\n.B struct tms *buffer;\n.fi\n.SH DESCRIPTION\n.ft B\nThis interface is obsoleted by getrusage(2).\n.ft R\n.PP\n.I Times\nreturns time-accounting information\nfor the current process\nand for the terminated child processes\nof the current process.\nAll times are in 1/HZ seconds, where HZ is 60.\n.PP\nThis is the structure returned by\n.IR times :\n.PP\n.nf\n.so /usr/include/sys/times.h\n.PP\n.fi\nThe children times are the sum\nof the children's process times and\ntheir children's times.\n.SH \"SEE ALSO\"\ntime(1), getrusage(2), wait3(2), time(3)\n"
  },
  {
    "path": "share/man/man3/ttyname.3",
    "content": ".\\\"\t@(#)ttyname.3\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH TTYNAME 3  \"May 15, 1985\"\n.AT 3\n.SH NAME\nttyname, isatty, ttyslot \\- find name of a terminal\n.SH SYNOPSIS\n.B char *ttyname(filedes)\n.PP\n.B isatty(filedes)\n.PP\n.B ttyslot()\n.SH DESCRIPTION\n.I Ttyname\nreturns a pointer to the null-terminated path name\nof the terminal device associated with file descriptor\n.I filedes\n(this is a system file descriptor and has nothing to do with the\nstandard I/O FILE typedef).\n.PP\n.I Isatty\nreturns 1 if\n.I filedes\nis associated with a terminal device, 0 otherwise.\n.PP\n.I Ttyslot\nreturns the number of the entry in the\n.IR ttys (5)\nfile for the control terminal of the current process.\n.SH FILES\n/dev/\\(**\n.br\n/etc/ttys\n.SH SEE ALSO\nioctl(2), ttys(5)\n.SH DIAGNOSTICS\n.I Ttyname\nreturns a null pointer (0) if\n.I filedes\ndoes not describe a terminal device in directory `/dev'.\n.PP\n.I Ttyslot\nreturns 0 if `/etc/ttys' is inaccessible or if\nit cannot determine the control terminal.\n.SH BUGS\nThe return value points to static data\nwhose content is overwritten by each call.\n"
  },
  {
    "path": "share/man/man3/ualarm.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)@(#)ualarm.3\t6.4 (Berkeley) 8/26/88\n.\\\"\n.TH UALARM 3  \"August 26, 1988\"\n.UC 6\n.SH NAME\nualarm \\- schedule signal after specified time\n.SH SYNOPSIS\n.nf\n.B unsigned ualarm(value, interval)\n.B unsigned value;\n.B unsigned interval;\n.fi\n.SH DESCRIPTION\n.ft B\nThis is a simplified interface to setitimer(2).\n.ft R\n.PP\n.I Ualarm\ncauses signal SIGALRM, see\n.IR signal (3C),\nto be sent to the invoking process\nin a number of microseconds given by the\n.I value\nargument.\nUnless caught or ignored, the signal terminates the process.\n.PP\nIf the\n.I interval\nargument is non-zero, the SIGALRM signal will be sent\nto the process every\n.I interval\nmicroseconds after the timer expires (e.g. after\n.I value\nmicroseconds have passed).\n.PP\nBecause of scheduling delays,\nresumption of execution of when the signal is\ncaught may be delayed an arbitrary amount.\nThe longest specifiable delay time (on the vax) is 2147483647 microseconds.\n.PP\nThe return value is the amount of time previously remaining in the alarm clock.\n.SH \"SEE ALSO\"\ngetitimer(2), setitimer(2), sigpause(2), sigvec(2), signal(3C), sleep(3),\nalarm(3), usleep(3)\n.SH \"NOTES  (PDP-11)\"\nOn the PDP-11,\n.IR setitimer (2)\nrounds the number of microseconds up to seconds resolution, therefore\n.I ualarm\ndoesn't give you any more resolution than\n.IR alarm (3).\n"
  },
  {
    "path": "share/man/man3/uname.3",
    "content": ".\\\" Copyright (c) 1994\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"\t@(#)uname.3\t8.1.1 (2.11BSD GTE) 2/4/95\n.\\\"\n.TH UNAME 3 \"February 4, 1995\"\n.UC 4\n.SH NAME\nuname \\- get system identification\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/utsname.h>\n\nint\nuname(struct utsname *name);\n.ft R\n.fi\n.SH DESCRIPTION\nThe\n.B uname\nfunction stores nul-terminated strings of information identifying\nthe current system into the structure referenced by\n.IR name .\n.PP\nThe\n.I utsname\nstructure is defined in the\n.I <sys/utsname.h>\nheader file, and contains the following members:\n.TP 15\nsysname\nName of the operating system implementation.\n.TP 15\nnodename\nNetwork name of this machine.\n.TP 15\nrelease\nRelease level of the operating system.\n.TP 15\nversion\nVersion level of the operating system.\n.TP 15\nmachine\nMachine hardware platform.\n.SH RETURN VALUES\nIf\n.B uname\nis successful, 0 is returned, otherwise, -1 is returned and\n.I errno\nis set appropriately.\n.SH ERRORS\nThe\n.B uname\nfunction may fail and set\n.I errno\nfor any of the errors specified for the library function\nsysctl(3).\n.SH SEE ALSO\nuname(1), sysctl(3)\n.SH STANDARDS\nThe\n.B uname\nfunction conforms to\nIEEE Std1003.1-88 (``POSIX'').\n.SH HISTORY\nThe\n.B uname\nfunction first appeared in 4.4BSD.\n"
  },
  {
    "path": "share/man/man3/ungetc.3",
    "content": ".\\\"\t@(#)ungetc.3s\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH UNGETC 3S  \"May 15, 1985\"\n.AT 3\n.SH NAME\nungetc \\- push character back into input stream\n.SH SYNOPSIS\n.B #include <stdio.h>\n.PP\n.B ungetc(c, stream)\n.br\n.SM\n.B FILE\n.B *stream;\n.SH DESCRIPTION\n.I Ungetc\npushes the character\n.I c\nback on an input stream.  That character will be returned by the next\n.I getc\ncall on that stream.\n.I Ungetc \nreturns \n.IR c .\n.PP\nOne character of pushback is guaranteed provided\nsomething has been read from the stream and the stream is actually buffered.\nAttempts to push EOF are rejected.\n.PP\n.IR  Fseek (3S)\nerases all memory of pushed back characters.\n.SH \"SEE ALSO\"\ngetc(3S),\nsetbuf(3S),\nfseek(3S)\n.SH DIAGNOSTICS\n.I Ungetc\nreturns\n.SM\n.B EOF\nif it can't push a character back.\n"
  },
  {
    "path": "share/man/man3/utime.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)utime.3c\t6.1 (Berkeley) 5/9/85\n.\\\"\n.TH UTIME 3C \"May 9, 1985\"\n.UC 4\n.SH NAME\nutime \\- set file times\n.SH SYNOPSIS\n.nf\n.B #include <sys/types.h>\n.PP\n.B utime(file, timep)\n.B char *file;\n.B time_t timep[2];\n.fi\n.SH DESCRIPTION\n.ft B\nThis interface is obsoleted by utimes(2).\n.ft R\n.PP\nThe\n.I utime\ncall\nuses the\n`accessed' and `updated' times in that order\nfrom the\n.I timep\nvector\nto set the corresponding recorded times for\n.IR file .\n.PP\nThe caller must be the owner of the file or the super-user.\nThe `inode-changed' time of the file is set to the current time.\n.SH SEE ALSO\nutimes(2), stat(2)\n"
  },
  {
    "path": "share/man/man3/valloc.3",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)valloc.3c\t6.2 (Berkeley) 5/12/86\n.\\\"\n.TH VALLOC 3C \"May 12, 1986\"\n.UC 3\n.SH NAME\nvalloc \\- aligned memory allocator\n.SH SYNOPSIS\n.nf\n.B char *valloc(size)\n.B unsigned size;\n.fi\n.SH DESCRIPTION\n.ft B\nValloc is obsoleted by the current version of malloc,\nwhich aligns page-sized and larger allocations.\n.ft R\n.PP\n.I Valloc\nallocates\n.I size\nbytes aligned on a page boundary.\nIt is implemented by calling\n.IR malloc (3)\nwith a slightly larger request, saving the true beginning of the block\nallocated, and returning a properly aligned pointer.\n.SH DIAGNOSTICS\n.I Valloc\nreturns a null pointer (0) if there is no available memory\nor if the arena has been detectably corrupted by storing outside the bounds\nof a block.\n.SH BUGS\n.I Vfree\nisn't implemented.\n"
  },
  {
    "path": "share/man/man3/varargs.3",
    "content": ".\\\"\t@(#)varargs.3\t6.3 (Berkeley) 5/15/86\n.\\\"\n.TH VARARGS 3  \"May 15, 1986\"\n.AT 3\n.SH NAME\nvarargs \\- variable argument list\n.SH SYNOPSIS\n.B \"#include <varargs.h>\"\n.PP\n.I function\\c\n.RB ( va_alist )\n.br\n.B va_dcl\n.br\n.B va_list\n.IR pvar ;\n.br\n.B va_start\\c\n.RI ( pvar );\n.br\nf =\n.B va_arg\\c\n.RI ( pvar ,\n.IR type );\n.br\n.B va_end\\c\n.RI ( pvar );\n.SH DESCRIPTION\nThis set of macros provides a means of writing portable procedures that\naccept variable argument lists.\nRoutines having variable argument lists (such as\n.IR printf (3))\nthat do not use varargs are inherently nonportable, since different\nmachines use different argument passing conventions.\n.PP\n.B va_alist\nis used in a function header to declare a variable argument list.\n.PP\n.B va_dcl\nis a declaration for\n.BR va_alist .\nNote that there is no semicolon after\n.B va_dcl.\n.PP\n.B va_list\nis a type which can be used for the variable\n.IR pvar ,\nwhich is used to traverse the list.\nOne such variable must always be declared.\n.PP\n.B va_start\\c\n.RI (pvar)\nis called to initialize\n.I pvar\nto the beginning of the list.\n.PP\n.B va_arg\\c\n.RI ( pvar ,\n.IR type )\nwill return the next argument in the list pointed to by\n.IR pvar .\n.I Type\nis the type to which the expected argument will be converted\nwhen passed as an argument.\nIn standard C, arguments that are\n.B char\nor\n.B short\nshould be accessed as\n.BR int ,\n.B \"unsigned char\nor\n.B \"unsigned short\nare converted to\n.BR \"unsigned int\" ,\nand\n.B float\narguments are converted to\n.BR double .\nDifferent types can be mixed, but it is up\nto the routine to know what type of argument is\nexpected, since it cannot be determined at runtime.\n.PP\n.B va_end\\c\n.RI ( pvar )\nis used to finish up.\n.PP\nMultiple traversals, each bracketed by\n.B va_start\n\\&...\n.B va_end,\nare possible.\n.SH EXAMPLE\n.nf\n\t\\fB#include\\fP <varargs.h>\n\texecl(\\fBva_alist\\fP)\n\t\\fBva_dcl\\fP\n\t{\n\t\t\\fBva_list\\fP ap;\n\t\t\\fBchar\\fP *file;\n\t\t\\fBchar\\fP *args[100];\n\t\t\\fBint\\fP argno = 0;\n\n\t\t\\fBva_start\\fP(ap);\n\t\tfile = \\fBva_arg(ap, \\fBchar\\fP *);\n\t\t\\fBwhile\\fP (args[argno++] = \\fBva_arg\\fP(ap, \\fBchar\\fP *))\n\t\t\t\\fB;\\fP\n\t\t\\fBva_end\\fP(ap);\n\t\t\\fBreturn\\fP execv(file, args);\n\t}\n.fi\n.SH BUGS\nIt is up to the calling routine to determine how many arguments\nthere are, since it is not possible to determine this from the\nstack frame.  For example,\n.I execl\npasses a 0 to signal the end of the list.\n.I Printf\ncan tell how many arguments are supposed to be there by the format.\n.PP\nThe macros\n.I va_start\nand\n.I va_end\nmay be arbitrarily complex;\nfor example,\n.I va_start\nmight contain an opening brace,\nwhich is closed by a matching brace in\n.IR va_end .\nThus, they should only be used where they could\nbe placed within a single complex statement.\n"
  },
  {
    "path": "share/man/man4/Makefile",
    "content": "#\n# Copyright (c) 1987 Regents of the University of California.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms are permitted\n# provided that the above copyright notice and this paragraph are\n# duplicated in all such forms and that any documentation,\n# advertising materials, and other materials related to such\n# distribution and use acknowledge that the software was developed\n# by the University of California, Berkeley.  The name of the\n# University may not be used to endorse or promote products derived\n# from this software without specific prior written permission.\n# THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n# IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n# WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n#\n#\t@(#)Makefile\t5.4.3 (2.11BSD) 1997/5/31\n#\nTOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nMDIR=\t${DESTDIR}/usr/share/man/cat4\nSRCS=\tacc.4 arp.4 bk.4 br.4 cons.4 css.4 de.4 dh.4 dhu.4 dhv.4 \\\n\tdmc.4 dr.4 dz.4  \\\n\tec.4 en.4 fd.4 hk.4 ht.4 hy.4 icmp.4 idp.4 il.4 imp.4 impconf.4 inet.4 \\\n\tintro.4 ip.4 lo.4 lp.4 mem.4 mtio.4 networking.4 ns.4 nsip.4 \\\n\tnull.4 pty.4 qe.4 ra.4 ram.4 rk.4 rl.4 rx.4 si.4 spp.4 sri.4 \\\n\tswap.4 tb.4 tcp.4 tm.4 tmscp.4 ts.4 tty.4 udp.4 vv.4 xp.4\nOBJS=\tacc.0 arp.0 bk.0 br.0 cons.0 css.0 de.0 dh.0 dhu.0 dhv.0 \\\n\tdmc.0 dr.0 \\\n\tdz.0 ec.0 en.0 fd.0 hk.0 ht.0 hy.0 icmp.0 idp.0 il.0 imp.0 impconf.0 \\\n\tinet.0 intro.0 ip.0 lo.0 lp.0 mem.0 mtio.0 networking.0 ns.0 \\\n\tnsip.0 null.0 pty.0 qe.0 ra.0 ram.0 rk.0 rl.0 rx.0 si.0 spp.0 \\\n\tsri.0 swap.0 tb.0 tcp.0 tm.0 tmscp.0 ts.0 tty.0 udp.0 vv.0 xp.0\n\n.SUFFIXES: .4 .0\n\n.4.0:\n\t${MANROFF} $*.4 > $*.0\n\nall: ${OBJS}\n\nclean: FRC\n\trm -f ${OBJS}\n\ninstall: all\n\tcp ${OBJS} ${MDIR}\n\tln -f ${MDIR}/xp.0 ${MDIR}/dvhp.0\n\tln -f ${MDIR}/xp.0 ${MDIR}/hp.0\n\tln -f ${MDIR}/xp.0 ${MDIR}/rm.0\n\tln -f ${MDIR}/xp.0 ${MDIR}/rp.0\n\tln -f ${MDIR}/mem.0 ${MDIR}/kmem.0\n\tln -f ${MDIR}/fd.0 ${MDIR}/stdin.0\n\tln -f ${MDIR}/fd.0 ${MDIR}/stderr.0\n\tln -f ${MDIR}/fd.0 ${MDIR}/stdout.0\n\nFRC:\n"
  },
  {
    "path": "share/man/man4/acc.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)acc.4\t6.1 (Berkeley) 7/26/87\n.\\\"\n.TH ACC 4 \"July 26, 1987\"\n.UC 2\n.SH NAME\nacc \\- ACC LH/DH IMP interface\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNACC\t0\t# ACC LH/DH ARPAnet IMP interface\n\tPLI\tYES\t# LH/DH is connected to a PLI\n.fi\n.ft R\n.SH DESCRIPTION\nThe \n.I acc\ndevice provides a Local Host/Distant Host\ninterface to an IMP.  It is normally used when participating\nin the DARPA Internet.  The controller itself is not accessible\nto users, but instead provides the hardware support to the IMP\ninterface described in\n.IR imp (4).\nWhen configuring, the \n.IR imp ( NIMP )\npseudo-device must also be included.\n.SH DIAGNOSTICS\n.BR \"acc%d: not alive\" .\nThe initialization routine was entered even though the device\ndid not autoconfigure.  This indicates a system problem.\n.PP\n.BR \"acc%d: can't initialize\" .\nInsufficient UNIBUS resources existed to initialize the device.\nThis is likely to occur when the device is run on a buffered\ndata path on an 11/750 and other network interfaces are also\nconfigured to use buffered data paths, or when it is configured\nto use buffered data paths on an 11/730 (which has none).\n.PP\n.BR \"acc%d: imp doesn't respond, icsr=%b\" .\nThe driver attempted to initialize the device, but the IMP\nfailed to respond after 500 tries.  Check the cabling.\n.PP\n.BR \"acc%d: stray xmit interrupt, csr=%b\" .\nAn interrupt occurred when no output had previously been started. \n.PP\n.BR \"acc%d: output error, ocsr=%b, icsr=%b\" .\nThe device indicated a problem sending data on output.\n.PP\n.BR \"acc%d: input error, csr=%b\" .\nThe device indicated a problem receiving data on input.\n.PP\n.BR \"acc%d: bad length=%d\" .\nAn input operation resulted in a data transfer of less than\n0 or more than 1008 bytes of\ndata into memory (according to the word count register).\nThis should never happen as the maximum size of a host-IMP\nmessage is 1008 bytes.\n"
  },
  {
    "path": "share/man/man4/arp.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)arp.4p\t6.2 (Berkeley) 8/1/87\n.\\\"\n.TH ARP 4P \"August 1, 1987\"\n.UC 2\n.SH NAME\narp \\- Address Resolution Protocol\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNETHER\t\\fI1\\fP\t# ether pseudo-device\n.fi\n.ft R\n.SH DESCRIPTION\nARP is a protocol used to dynamically map between DARPA Internet\nand 10Mb/s Ethernet addresses.  It is\nused by all the 10Mb/s Ethernet interface drivers.\nIt is not specific to Internet protocols or to 10Mb/s Ethernet,\nbut this implementation currently supports only that combination.\n.PP\nARP caches Internet-Ethernet address mappings.  When an interface\nrequests a mapping for an address not in the cache, ARP queues the\nmessage which requires the mapping and broadcasts\na message on the associated network requesting the address mapping.\nIf a response is provided, the new mapping is cached and any pending\nmessage is transmitted.\nARP will queue\nat most one packet while waiting for a mapping request to be responded to;\nonly the most recently ``transmitted'' packet is kept.\n.PP\nTo facilitate communications with systems which do not use ARP,\n.IR ioctl \\^s\nare provided to enter and delete entries in the Internet-to-Ethernet tables.\nUsage:\n.LP\n.nf\n.ft B\n\t#include <sys/ioctl.h>\n\t#include <sys/socket.h>\n\t#include <net/if.h>\n\tstruct arpreq arpreq;\n\n\tioctl(s, SIOCSARP, (caddr_t)&arpreq);\n\tioctl(s, SIOCGARP, (caddr_t)&arpreq);\n\tioctl(s, SIOCDARP, (caddr_t)&arpreq);\n.fi\n.ft R\nEach ioctl takes the same structure as an argument.\nSIOCSARP sets an ARP entry, SIOCGARP gets an ARP entry, and SIOCDARP\ndeletes an ARP entry.  These ioctls may be applied to any socket descriptor\n.I s,\nbut only by the super-user.\nThe\n.I arpreq\nstructure contains:\n.LP\n.RS\n.ta \\w'#define\\ \\ 'u +\\w'ATF_USETRAILERS\\ \\ 'u +\\w'0x08\\ \\ \\ \\  'u\n.nf\n/*\n * ARP ioctl request\n */\nstruct arpreq {\n\tstruct sockaddr\tarp_pa;\t\t/* protocol address */\n\tstruct sockaddr\tarp_ha;\t\t/* hardware address */\n\tint\tarp_flags;\t\t/* flags */\n};\n/*  arp_flags field values */\n#define ATF_COM\t\t0x02\t/* completed entry (arp_ha valid) */\n#define\tATF_PERM\t0x04\t/* permanent entry */\n#define\tATF_PUBL\t0x08\t/* publish (respond for other host) */\n#define\tATF_USETRAILERS\t0x10\t/* send trailer packets to host */\n.fi\n.RE\n.LP\nThe address family for the\n.I arp_pa\nsockaddr must be AF_INET; for the \n.I arp_ha\nsockaddr it must be AF_UNSPEC.\nThe only flag bits which may be written are ATF_PERM, ATF_PUBL\nand ATF_USETRAILERS.\nATF_PERM causes the entry to be permanent if the ioctl call succeeds.\nThe peculiar nature of the ARP tables may cause the ioctl to fail if more\nthan 8 (permanent) Internet host addresses hash to the same slot.\nATF_PUBL specifies that the ARP code should respond to ARP requests for the\nindicated host coming from other machines.  This allows a host to act as an\n``ARP server,'' which may be useful in convincing an ARP-only machine to talk\nto a non-ARP machine.\n.PP\nARP is also used to negotiate the use of trailer IP encapsulations;\ntrailers are an alternate encapsulation used to allow efficient packet\nalignment for large packets despite variable-sized headers.\nHosts which wish to receive trailer encapsulations so indicate\nby sending gratuitous ARP translation replies along with replies\nto IP requests; they are also sent in reply to IP translation replies.\nThe negotiation is thus fully symmetrical, in that either or both hosts\nmay request trailers.\nThe ATF_USETRAILERS flag is used to record the receipt of such a reply,\nand enables the transmission of trailer packets to that host.\n.PP\nARP watches passively for hosts impersonating the local host (i.e. a host\nwhich responds to an ARP mapping request for the local host's address).\n.SH DIAGNOSTICS\n.B \"duplicate IP address!! sent from ethernet address: %x:%x:%x:%x:%x:%x.\"\nARP has discovered another host on the local network which responds to\nmapping requests for its own Internet address.\n.SH SEE ALSO\nec(4), de(4), il(4), inet(4F), arp(8C), ifconfig(8C)\n.br\n``An Ethernet Address Resolution Protocol,'' RFC826, Dave Plummer,\nNetwork Information Center, SRI.\n.br\n``Trailer Encapsulations,'' RFC893, S.J. Leffler and M.J. Karels,\nNetwork Information Center, SRI.\n.SH BUGS\nARP packets on the Ethernet use only 42 bytes of data; however, the smallest\nlegal Ethernet packet is 60 bytes (not including CRC).\nSome systems may not enforce the minimum packet size, others will.\n"
  },
  {
    "path": "share/man/man4/bk.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)bk.4\t6.1.1 (2.11BSD) 1996/1/27\n.\\\"\n.TH BK 4 \"January 27, 1996\"\n.UC 4\n.SH NAME\nbk \\- line discipline for machine-machine communication (obsolete)\n.SH SYNOPSIS\n.ft B\n.nf\nNot currently supported under 2.11BSD\n.fi\n.ft R\n.SH DESCRIPTION\nThis line discipline provides a replacement for the old and new\ntty drivers described in\n.IR tty (4)\nwhen high speed output to\nand especially input from another machine is to be transmitted\nover a asynchronous communications line.  The discipline\nwas designed for use by the Berkeley network.\nIt may be suitable for uploading of data from microprocessors into\nthe system.  If you are going to send data over asynchronous\ncommunications lines at high speed into the system, you must\nuse this discipline, as the system otherwise may detect high\ninput data rates on terminal lines and disables the lines;\nin any case the processing of such data when normal terminal\nmechanisms are involved saturates the system.\n.PP\nThe line discipline is enabled by a sequence:\n.PP\n.nf\n.ft B\n\t#include <sgtty.h>\n\tint ldisc = NETLDISC, fildes; ...\n\tioctl(fildes, TIOCSETD, &ldisc);\n.fi\n.ft R\n.PP\nA typical application program then reads a sequence of lines from\nthe terminal port, checking header and sequencing information on each\nline and acknowledging receipt of each line to the sender, who then\ntransmits another line of data.  Typically several hundred bytes of\ndata and a smaller amount of control information will be received on\neach handshake.\n.PP\nThe old standard teletype discipline can be restored by doing:\n.PP\n.nf\n.ft B\n\tldisc = OTTYDISC;\n\tioctl(fildes, TIOCSETD, &ldisc);\n.fi\n.ft R\n.PP\nWhile in networked mode, normal teletype output functions take place.\nThus, if an 8 bit output data path is desired, it is necessary\nto prepare the output line by putting it into RAW mode using\n.IR ioctl (2).\nThis must be done\n.B before\nchanging the discipline with TIOCSETD, as most\n.IR ioctl (2)\ncalls are disabled while in network line-discipline mode.\n.PP\nWhen in network mode, input processing is very limited to reduce overhead.\nCurrently the input path is only 7 bits wide, with newline the only\nrecognized character, terminating an input record.\nEach input record must be read and acknowledged before the next input\nis read as the system refuses to accept any new data when there\nis a record in the buffer.  The buffer is limited in length, but the\nsystem guarantees to always be willing to accept input resulting in\n512 data characters and then the terminating newline.\n.PP\nUser level programs should provide sequencing and checksums on the\ninformation to guarantee accurate data transfer.\n.SH \"SEE ALSO\"\ntty(4)\n.SH DIAGNOSTICS\nNone.\n.SH BUGS\nThe Purdue uploading line discipline, which provides 8 bits and uses\ntimeout's to terminate uploading should be incorporated into the standard\nsystem, as it is much more suitable for microprocessor connections.\n"
  },
  {
    "path": "share/man/man4/br.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)br.4\t6.2 (Berkeley) 8/29/87\n.\\\"\n.TH BR 4 \"August 20, 1988\"\n.UC 2\n.SH NAME\nbr \\- EATON BR1537/BR1711 1538[A,B,C,D] moving head disk\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNBR\t\\fIbr_drives\\fP\t# EATON 1537/1711, EATON 1538A, B, C, D\n\n/etc/dtab:\n.ta .5i +\\w'#Name 'u +\\w'Unit# 'u +\\w'177777 'u +\\w'Vector 'u +\\w'Br 'u +\\w'xxxxxxx 'u +\\w'xxxxxxx 'u\n\t#Name\tUnit#\tAddr\tVector\tBr\tHandler(s)\t\t# Comments\n\\\tbr\t?\t176710\t254\t5\tbrintr\t\t# Eaton 1537/8\n.DT\n\nmajor device number(s):\n\traw: 20\n\tblock: 11\nminor device encoding:\n\tbits 0007 specify partition of BR drive\n\tbits 0070 specify BR drive\n.fi\n.ft R\n.SH DESCRIPTION\nFiles with minor device numbers 0 through 7 refer to various portions\nof drive 0;\nminor devices 8 through 15 refer to drive 1, etc.\nThere are four drive types supported by the Eaton\nBR1537 and BR1711 controllers,\nthese are the 1538A (50 Mb), 1538B (80 Mb), 1538C (200 Mb) and\n1538D (300 Mb).  Capacities are unformatted megabytes.\nThe standard device names begin with ``br'' followed by\nthe drive number and then a letter a-h for partitions 0-7 respectively.\nThe character ? stands here for a drive number in the range 0-7.\n.PP\nThe block files access the disk via the system's normal\nbuffering mechanism and may be read and written without regard to\nphysical disk records.  There is also a `raw' interface\nwhich provides for direct transmission between the disk\nand the user's read or write buffer.\nA single read or write call results in exactly one I/O operation\nand therefore raw I/O is considerably more efficient when\nmany words are transmitted.  The names of the raw files\nconventionally begin with an extra `r.'\n.PP\nIn raw I/O the buffer must begin on a word (even) boundary,\nand counts should be a multiple of 512 bytes (a disk sector).\nLikewise\n.I seek\ncalls should specify a multiple of 512 bytes.\n.SH \"DISK SUPPORT\"\nThe size (in sectors) of the\npseudo-disks on each drive are as follows:\n.nf\n.ta .5i +\\w'disk  'u +\\w'000000  'u +\\w'000000  'u +\\w'000 - 000  'u\n.PP\n.ne 10\n1538A partitions:\n\tdisk\t length\t     cyls\tcomments\n\tbr?a\t  18260\t  0  - 165\t1538A has 22 sec/trk, 5 trk/cyl\n\tbr?b\t  12210\t 166 - 276\n\tbr?c\t  59180  277 - 814\n\tbr?d\t  unused\n\tbr?e\t  unused\n\tbr?f\t  unused\n\tbr?g\t  unused\n\tbr?h\t  89650   0  - 814\n.PP\n.ne 10\n1538B partitions:\n\tdisk\t length\t     cyls\tcomments\n\tbr?a\t  18400\t  0  - 114\t1538B has 32 sec/trk, 5 trk/cyl\n\tbr?b\t  12320\t 115 - 190\n\tbr?c\t  99840  191 - 814\n\tbr?d\t  unused\n\tbr?e\t  unused\n\tbr?f\t  unused\n\tbr?g\t  unused\n\tbr?h\t  99840   0  - 814\n.PP\n.ne 10\n1538C partitions:\n\tdisk\t length\t     cyls\tcomments\n\tbr?a\t  18392\t  0  - 43\t1538C has 22 sec/trk, 19 trk/cyl\n\tbr?b\t  12122\t 44  - 72\n\tbr?c\t 231990  73 - 627\n\tbr?d\t  78166 628 - 814\n\tbr?e\t  unused\n\tbr?f\t  unused\n\tbr?g\t  unused\n\tbr?h\t 340670   0  - 814\n.PP\n.ne 10\n1538D partitions:\n\tdisk\t length\t     cyls\tcomments\n\tbr?a\t  18240\t  0  - 29\t1538D has 32 sec/trk, 19 trk/cyl\n\tbr?b\t  12160\t 30  - 49\n\tbr?c\t 232256  50 - 431\n\tbr?d\t 232256 432 - 813\n\tbr?e\t  unused\n\tbr?f\t  unused\n\tbr?g\t  unused\n\tbr?h\t 495520   0  - 814\n.DT\n.fi\n.SH FILES\n.ta \\w'/dev/MAKEDEV.local  'u\n/dev/br[0-7][a-h]\tblock files\n.br\n/dev/rbr[0-7][a-h]\traw files\n.br\n/dev/MAKEDEV\tscript to create special files\n.br\n/dev/MAKEDEV.local\tscript to localize special files\n.DT\n.SH \"SEE ALSO\"\nra(4),\nram(4),\nrk(4),\nrl(4),\nrx(4),\nsi(4),\nxp(4),\ndtab(5),\nautoconfig(8)\n.SH DIAGNOSTICS\n\\fBbr%d%c: hard error sn%d cs2=%b ds=%b er=%b\\fR.  An unrecoverable\nerror occurred during transfer of the specified sector of the specified\ndisk partition.  The contents of the cs2, ds and er registers are printed\nin octal and symbolically with bits decoded.\nThe error was either unrecoverable, or a large number of retry attempts\n(including offset positioning and drive recalibration) could not\nrecover the error.\n.SH BUGS\nIn raw I/O\n.I read\nand\n.IR write (2)\ntruncate file offsets to 512-byte block boundaries,\nand\n.I write\nscribbles on the tail of incomplete blocks.\nThus,\nin programs that are likely to access raw devices,\n.I read, write\nand\n.IR lseek (2)\nshould always deal in 512-byte multiples.\n.PP\nDEC-standard error logging should be supported.\n.PP\nA program to analyze the logged error information (even in its\npresent reduced form) is needed.\n.PP\nThe partition tables for the file systems should be read off of each\npack, as they are never quite what any single installation would prefer,\nand this would make packs more portable.\n.PP\nOnly the 1538D (300Mb) disk has been used with this driver, the\n.IR disktab (5) \nfile and\n.IR newfs (8)\nprogram only know about the 1538D.\n"
  },
  {
    "path": "share/man/man4/cons.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)cons.4\t6.2 (Berkeley) 7/27/87\n.\\\"\n.TH CONS 4 \"July 27, 1987\"\n.UC 4\n.SH NAME\ncons \\- PDP-11 console interface\n.SH DESCRIPTION\nThe console is available to the processor through the console registers.\nIt acts like a normal terminal, except that typing control-P on the\nconsoles of some PDP-11's puts the console in local console mode with an\nODT (console debugger mode) prompt.  The operation of the console in this\nmode varies per-processor.  See the PDP-11 Processor Handbook for your\nparticular processor.\n.PP\nOn an 11/44 the console can be put into local mode by typing a control-P.\nThe ODT prompt is ``>>>''.  The processor is not stopped by entering\nlocal console mode.  The CPU may be halted with the ``halt'' command,\nwhich may be abbreviated to ``h.'' Conversational mode is re-entered by\nusing the command ``c'' (continue).\n.PP\nOn 11/73 the processor's front panel halt switch must be pressed to put\nthe console into ODT mode.  The ODT prompt is an ``@''.  No characters\ntyped on the console are special while UNIX is in control of the console.\n.SH FILES\n/dev/console\n.SH \"SEE ALSO\"\ntty(4), reboot(8)\n.br\nPDP-11 Hardware Handbook specific to hardware\n"
  },
  {
    "path": "share/man/man4/css.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)css.4\t6.1 (Berkeley) 8/20/87\n.\\\"\n.TH CSS 4 \"August 20, 1987\"\n.UC 2\n.SH NAME\ncss \\- DEC IMP-11A LH/DH IMP interface\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNCSS\t\\fIcss_controllers\\fP\t# DEC/CSS IMP11-A ARPAnet IMP interface\n.fi\n.ft R\n.SH DESCRIPTION\nThe \n.I css\ndevice provides a Local Host/Distant Host\ninterface to an IMP.  It is normally used when participating\nin the DARPA Internet.  The controller itself is not accessible\nto users, but instead provides the hardware support to the IMP\ninterface described in\n.IR imp (4).\nWhen configuring, the \n.IR imp ( NIMP )\npseudo-device is also included.\n.SH DIAGNOSTICS\n.BR \"css%d: not alive\" .\nThe initialization routine was entered even though the device\ndid not autoconfigure.  This is indicates a system problem.\n.PP\n.BR \"css%d: can't initialize\" .\nInsufficient UNIBUS resources existed to initialize the device.\nThis is likely to occur when the device is run on a buffered\ndata path on an 11/750 and other network interfaces are also\nconfigured to use buffered data paths, or when it is configured\nto use buffered data paths on an 11/730 (which has none).\n.PP\n.BR \"css%d: imp doesn't respond, icsr=%b\" .\nThe driver attempted to initialize the device, but the IMP\nfailed to respond after 500 tries.  Check the cabling.\n.PP\n.BR \"css%d: stray output interrupt csr=%b\" .\nAn interrupt occurred when no output had previously been started. \n.PP\n.BR \"css%d: output error, ocsr=%b icsr=%b\" .\nThe device indicated a problem sending data on output.\n.PP\n.BR \"css%d: recv error, csr=%b\" .\nThe device indicated a problem receiving data on input.\n.PP\n.BR \"css%d: bad length=%d\" .\nAn input operation resulted in a data transfer of less than\n0 or more than 1008 bytes of\ndata into memory (according to the word count register).\nThis should never happen as the maximum size of a host-IMP\nmessage is 1008 bytes.\n"
  },
  {
    "path": "share/man/man4/de.4",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)de.4\t6.2 (Berkeley) 8/20/87\n.\\\"\n.TH DE 4 \"August 20, 1987\"\n.UC 2\n.SH NAME\nde \\- DEC DEUNA 10 Mb/s Ethernet interface\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNDE\t\\fIde_controllers\\fP\t# DEUNA\n.fi\n.ft R\n.SH DESCRIPTION\nThe\n.I de\ninterface provides access to a 10 Mb/s Ethernet network through\na Digital Equipment UNIBUS Network Adapter (DEUNA).\n.PP\nEach of the host's network addresses\nis specified at boot time with an SIOCSIFADDR\nioctl.  The\n.I de\ninterface employs the address resolution protocol described in\n.IR arp (4P)\nto dynamically map between Internet and Ethernet addresses on the local\nnetwork.\n.PP\nThe interface normally tries to use a ``trailer'' encapsulation\nto minimize copying data on input and output.\nThe use of trailers is negotiated with ARP.\nThis negotiation may be disabled, on a per-interface basis,\nby setting the IFF_NOTRAILERS\nflag with an SIOCSIFFLAGS ioctl.\n.SH DIAGNOSTICS\n\\fBde%d: hardware address %s\\fP.\nThis is a normal autoconfiguration message noting the 6 byte physical\nethernet address of the adapter.\n.PP\n\\fBde%d: oerror, flags=%b tdrerr=%b (len=%d)\\fP.\nThe hardware indicated an error\nin transmitting a packet to the cable.\nThe status and error flags are reported.\n.PP\n\\fBde%d: ierror, flags=%b lenerr=%b (len=%d)\\fP.\nThe hardware indicated an error\nin reading a packet from the cable.\nThe status and error flags are reported.\n.PP\n\\fBde%d: can't handle af%d\\fP.  The interface was handed\na message with addresses formatted in an unsuitable address\nfamily; the packet was dropped.\n.PP\n\\fBde%d: buffer unavailable\\fP.  The interface received more packets\nthan it had buffers allocated to receive them.\n.PP\n\\fBde%d: address change failed, csr0=%b csr1=%b\\fP.\nThe interface was unable to reprogram\nits physical ethernet address.\nThis may happen with very early models of the interface.\nThis facility is used only when\nthe controller is not the first network interface configured for XNS.\n.PP\nThe following messages indicate a probable hardware error performing\nthe indicated operation during autoconfiguration or initialization.\nThe two control and status registers\nshould indicate the nature of the failure.\nSee the hardware manual for details.\n.PP\n\\fBde%d: reset failed, csr0=%b csr1=%b\\fP.\n.PP\n\\fBde%d: ppcb failed, csr0=%b csr1=%b\\fP.\n.PP\n\\fBde%d: read addr failed, csr0=%b csr1=%b\\fP.\n.PP\n\\fBde%d: wtring failed, csr0=%b csr1=%b\\fP.\n.PP\n\\fBde%d: wtmode failed, csr0=%b csr1=%b\\fP.\n.SH SEE ALSO\nintro(4N), inet(4F), arp(4P)\n"
  },
  {
    "path": "share/man/man4/dh.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)dh.4\t6.4 (2.11BSD) 1997/5/31\n.\\\"\n.TH DH 4 \"May 31, 1997\"\n.UC 2\n.SH NAME\ndh \\- DH-11/DM-11 communications multiplexer\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNDH\t\\fIdh_units\\fP\t# DH11; NDH is in units of boards (16 each)\n\tNDM\t\\fIdm_units\\fP\t# DM11; NDM is in units of boards (16 each)\n\n/etc/dtab:\n.ta .5i +\\w'#Name 'u +\\w'Unit# 'u +\\w'177777 'u +\\w'Vector 'u +\\w'Br 'u +\\w'xxxxxxx 'u +\\w'xxxxxxx 'u\n\t#Name\tUnit#\tAddr\tVector\tBr\tHandler(s)\t\t# Comments\n\tdm\t?\t170500\t310\t4\tdmintr\t\t# dm11 dh modem control\n\tdh\t?\t160020\t320\t5\tdhrint\tdhxint\t# dh11 terminal mux\n.DT\n\nmajor device number(s):\n\traw: 3\nminor device encoding:\n\tbits 0017 specify line on DH unit\n\tbits 0060 specify DH unit\n\tbit  0100 specify RTS/CTS (``hardware'') flowcontrol\n\tbit  0200 specifies non-blocking open (``CD always on'')\n.fi\n.ft R\n.SH DESCRIPTION\nA dh-11 provides 16 communication lines; dm-11's may be optionally\npaired with dh-11's to provide modem control for the lines.\nIf there are fewer dm-11's than dh-11's, the dm-11's are assumed\nto be paired with the first \\fIdm_units\\fP dh-11's.\n.PP\nEach line attached to the DH-11 communications multiplexer\nbehaves as described in\n.IR tty (4).\nInput and output for each line may independently\nbe set to run at any of 16 speeds;\nsee\n.IR tty (4)\nfor the encoding.\n.PP\nBit\n.I 0200\nof the minor device number for DH lines\nmay be set to say that a line is not properly\nconnected, and that the line should be treated as hard-wired with carrier\nalways present.  Thus creating the special character device node \"3, 130\" via\n.I \"mknod /dev/ttyh2 c 3 130\"\nwould cause line ttyh2 to be treated in this way.  Bit\n.I 0100\nof the minor device number enables RTS/CTS (also called ``hardware'') flow\ncontrol. It is enabled by adding 64 to the minor device number:\n.I \"mknod /dev/ttyh2 c 3 194\"\n.PP\nThe\n.I dh\ndriver monitors the rate of input on each board,\nand switches between the use of character-at-a-time interrupts\nand input silos.\nWhile the silo is enabled during periods of high-speed input,\nthe driver polls for input 30 times per second.\n.SH FILES\n.ta \\w'/dev/MAKEDEV.local  'u\n/dev/tty[h-k][0-9a-f]\n.br\n/dev/ttyd[0-9a-f]\n.br\n/dev/MAKEDEV\tscript to create special files\n.br\n/dev/MAKEDEV.local\tscript to localize special files\n.DT\n.SH \"SEE ALSO\"\ntty(4),\ndtab(5),\nautoconfig(8)\n.SH DIAGNOSTICS\n\\fBdh%d NXM\\fR.  No response from UNIBUS on a dma transfer\nwithin a timeout period.  This has never been observed on a PDP-11 and is\na carryover from the VAX driver when it was ported.\nIt is not serious.\n.PP\n\\fBdh%d %d overruns\\fR.  The character input silo overflowed\nbefore it could be serviced.  This message is only printed at line close time.\nIt is not serious but does indicate that the system was not able to keep up\nwith the data flow.\n"
  },
  {
    "path": "share/man/man4/dhu.4",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)dhu.4\t6.2.1 (2.11BSD) 1997/5/31\n.\\\"\n.TH DHU 4 \"May 31, 1997\"\n.UC 2\n.SH NAME\ndhu \\- DHU-11 communications multiplexer\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNDHU\t\\fIdhu_units\\fP\t# DHU11\n\n/etc/dtab:\n.ta .5i +\\w'#Name 'u +\\w'Unit# 'u +\\w'177777 'u +\\w'Vector 'u +\\w'Br 'u +\\w'xxxxxxx 'u +\\w'xxxxxxx 'u\n\t#Name\tUnit#\tAddr\tVector\tBr\tHandler(s)\t\t# Comments\n\tdu\t?\t160020\t310\t5\tdhurint\tdhuxint\t# dhu11 terminal mux\n.DT\n\nmajor device number(s):\n\traw: 4\nminor device encoding:\n\tbits 0017 specify line on DHU unit\n\tbits 0060 specify DHU unit\n\tbit  0100 specify RTS/CTS flow control\n\tbit  0200 specifies non-blocking open (``CD always on'')\n.fi\n.ft R\n.SH DESCRIPTION\nA DHU-11 provides 16 communication lines.\n.PP\nEach line attached to the DHU-11 communications multiplexer\nbehaves as described in\n.IR tty (4).\nInput and output for each line may independently\nbe set to run at any of 13 speeds (50, 200 and 38400 baud are not available);\nsee\n.IR tty (4)\nfor the encoding.\n.PP\nBit\n.I 0200\nof the minor device number for DHU lines\nmay be set to say that a line is not properly\nconnected, and that the line should be treated as hard-wired with carrier\nalways present.  Thus creating the special character device node \"4, 130\" via\n.I \"mknod /dev/ttyS2 c 4 130\"\nwould cause line ttyS2 to be treated in this way.  Turning on bit 6 (adding\n64) to the minor device number via\n.I \"mknod /dev/ttyS2 c 4 194\"\nenables RTS/CTS flow control.\n.PP\nThe DHU-11 driver normally uses input silos\nand delays receiver interrupts by 20 milliseconds\nrather than taking an interrupt on each input character.\n.SH FILES\n/dev/tty[S-Z][0-9a-f]\n.SH \"SEE ALSO\"\ntty(4)\n.SH DIAGNOSTICS\n\\fBdhu(%d,%d) NXM\\fR.  No response from UNIBUS on a DMA transfer\nwithin a timeout period.  This has never been observed on a PDP-11 and is\nbelieved to be a carryover from the VAX driver when it was ported.\nIt is not serious.\n.PP\n\\fBdhu%d %d overruns\\fR.  The character input silo overflowed\nbefore it could be serviced.  This message is printed only at line close time\nrather than on each overrun error.  Kernel printf's are not interrupt driven\nand caused more overruns by blocking interrupts for lengthy periods of time.\n.SH NOTES\nThe driver currently does not make full use of the hardware\ncapabilities of the DHU-11, for dealing with XON/XOFF flow-control or hard-wired\nlines for example.\n.PP\nThe 4 40-way cables are a pain.\n"
  },
  {
    "path": "share/man/man4/dhv.4",
    "content": ".\\\"\n.\\\"\t@(#)dhv.4\t1.0 (2.11BSD) 1997/5/31\n.\\\"\n.TH DHV 4 \"May 31, 1997\"\n.UC 2\n.SH NAME\ndhv \\- DHV-11 communications multiplexer\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNDHV\t\\fIdhv_units\\fP\t# DHV11\n\n/etc/dtab:\n.ta .5i +\\w'#Name 'u +\\w'Unit# 'u +\\w'177777 'u +\\w'Vector 'u +\\w'Br 'u +\\w'xxxxxxx 'u +\\w'xxxxxxx 'u\n\t#Name\tUnit#\tAddr\tVector\tBr\tHandler(s)\t\t# Comments\n\tdhv\t?\t160440\t310\t5\tdhvrint\tdhvxint\t# dhv terminal mux\n.DT\n\nmajor device number(s):\n\traw: 24\nminor device encoding:\n\tbits 0007 specify line on DHV unit\n\tbits 0070 specify DHV unit\n\tbit  0100 specifies RTS/CTS (``hardware'') flowcontrol\n\tbit  0200 specifies non-blocking open (``CD always on'')\n.fi\n.ft R\n.SH DESCRIPTION\nA DHV-11 provides 8 communication lines.\n.PP\nEach line attached to the DHV-11 communications multiplexer\nbehaves as described in\n.IR tty (4).\nInput and output for each line may independently\nbe set to run at any of 13 speeds (50 and 200 baud are not available).  While\n38400 is available the underlying hardware is not fast enough to handle it and\nthere will be pauses/gaps between characters.\n.PP\nBit\n.I 0200\nof the minor device number for DHV lines\nmay be set to say that a line is not properly\nconnected, and that the line should be treated as hard-wired with carrier\nalways present.  Thus creating the special character device node \"4, 130\" via\n.I \"mknod /dev/ttyS2 c 4 130\"\nwould cause line ttyS2 to be treated in this way.  Turning on bit 6 in the\nminor device number via\n.I \"mknod /dev/ttyS2 c 4 194\"\nwould enable RTS/CTS flow control.\n.PP\nThe DHV-11 has an input silo but does \\fBnot\\fP have the programmable\nreceiver delay that the DHU (and DHQ) have.  Thus system services more\ninterrupts (i.e. gets fewer characters per interrupt on average) with a\nDHV-11 than with a DHQ (in DHU mode).\n.SH FILES\n/dev/tty[S-Z][0-9a-f]\n.SH \"SEE ALSO\"\ntty(4)\n.SH DIAGNOSTICS\n\\fBdhv%d,%d NXM\\fR.  No response from QBUS on a DMA transfer\nwithin a timeout period.  This error has never been observed on a PDP-11 and\nis a carryover from the VAX driver when that was ported to 2BSD.\n.PP\n\\fBdhv%d diag %o\\fR.  Diagnostic information from the DHV11.  This has never\nbeen observed.  The DHV-11 hardware manual will be required to decode the \nvalue printed out.\n.PP\n\\fBdhv%d: %d overruns\\fR.  The character input silo overflowed\nbefore it could be serviced.  This message is printed only when the line is\nclosed.  By only printing this when the line is closed further silo overruns \nare avoided (kernel printf statements are not interrupt driven).\n.SH NOTES\nThe DHV lacks the receiver delay that the DHU (and DHQ) have.  Thus it is \nextremely easy (indeed it's almost certain at higher data rates) for a \nDHV-11 to enter an interrupt per character mode and use 70-80% of the cpu.\n"
  },
  {
    "path": "share/man/man4/dmc.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)dmc.4\t6.3.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH DMC 4 \"October 22, 1996\"\n.UC 2\n.SH NAME\ndmc \\- DEC DMC-11/DMR-11 point-to-point communications device\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNDMC\t\\fIdmc_controllers\\fP\t# DMC11\n.fi\n.ft R\n.SH DESCRIPTION\nThe\n.I dmc\ninterface provides access to a point-to-point communications\ndevice which runs at either 1 Mb/s or 56 Kb/s.  DMC-11's communicate\nusing the DEC DDCMP link layer protocol.\n.PP\nThe\n.I dmc\ninterface driver also supports a DEC DMR-11 providing point-to-point\ncommunication running at data rates from 2.4 Kb/s to 1 Mb/s.\nDMR-11's are a more recent design and thus are preferred over DMC-11's.\nThe NXMT and NRCV constants in the driver should be increased in this case,\nas the DMR can accept up to 64 transmit and receive buffers, as opposed\nto 7 for the DMC.\n.PP\nThe configuration flags specify how to set up the device, \n.br\n0 -- full duplex DDCMP (normal mode)\n.br\n1 -- DDCMP Maintence mode (generally useless)\n.br\n2 -- DDCMP Half Duplex, primary station\n.br\n3 -- DDCMP Half Duplex, secondary station\n.ti\n.PP\nSeveral device error counters are available via \"adb\", for\nmore information see the adb script /usr/share/adb/dmcstats, or the\nDMC11 technical manual.\n.PP\nThe host's address must be specified with an SIOCSIFADDR ioctl,\nand the destination address specified with a SIOCSIFDSTADDR ioctl,\nbefore the interface will transmit or receive any packets.\n.SH ROUTING\nThe driver places a HOST entry in the kernel routing tables for the\naddress given in the SIOCSIFDSTADDR ioctl.  To use the DMC as a\nlink between local nets, the route to the remote net must be added manually\nwith the\n.IR route (8)\ncommand, or by the use of the routing process\n.IR routed (8)\non each end of the link.\n.SH DIAGNOSTICS\n.BR \"dmc%d: bad control %o\" .\nA bad parameter was passed to the\n.I dmcload\nroutine.\n.PP\n.BR \"dmc%d: unknown address type %d\" .\nAn input packet was received which contained a type of\naddress unknown to the driver.\n.PP\n.BR \"DMC fatal error 0%o\" .\nA fatal error in DDMCP occurred, causing the device to be restarted.\n.PP\n.BR \"DMC soft error 0%o\" .\nA non-fatal error in DDMCP has occurred. \n.PP\n.BR \"dmc%d: af%d not supported\" . \nThe interface was handed a message which has\naddresses formatted in an unsuitable address family.\n.SH SEE ALSO\nintro(4N), inet(4F)\n.SH BUGS\nThe current version of the driver uses a link-level encapsulation\nso that multiple protocol types may be used.\nIt is thus incompatible with earlier drivers,\nincluding the 4.2BSD version.\n"
  },
  {
    "path": "share/man/man4/dr.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)dr.4\t6.2.1 (2.11BSD) 1996/1/27\n.\\\"\n.TH DR 4 \"January 27, 1996\"\n.UC 2\n.SH NAME\ndr \\- DR11-W general purpose interface driver\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNDR\t\\fIdr11-w_units\\fP\t# DR11-W\n\n/etc/dtab:\n.ta .5i +\\w'#Name 'u +\\w'Unit# 'u +\\w'177777 'u +\\w'Vector 'u +\\w'Br 'u +\\w'xxxxxxx 'u +\\w'xxxxxxx 'u\n\t#Name\tUnit#\tAddr\tVector\tBr\tHandler(s)\t\t# Comments\n\tdr\t?\t172410\t124\t5\tdrintr\t\t# dr11-w (b-bus emulator)\n\tdr\t?\t172430\t130\t5\tdrintr\t\t# dr11-w (gc-bus emulator)\n\tdr\t?\t172450\t134\t5\tdrintr\t\t# dr11-w (em-2 interface)\n.DT\n\nmajor device number(s):\n\traw: 12\nminor device encoding:\n\tbits 0007 specify DR unit\n.fi\n.ft R\n.SH DESCRIPTION\nThe\n.I \"Digital Equipment 1981-82 Peripherals Handbook\"\nstates the following about the DR11-W:\n.RS\n.PP\nThe The DR11-W is a general purpose, direct memory access (DMA) interface to\nthe PDP-11 UNIBUS or VAX UNIBUS.  The DR11-W moves data directly between\nmemory and the UNIBUS to and from the user's peripheral.\n.PP\nIt features:\n.IP \\(bu\nWord or byte transfers.\n.IP \\(bu\nProgrammed or direct memory access (DMA) block transfers.\n.IP \\(bu\nBurst data transfers.\n.IP \\(bu\nUser-controlled transfer rates up to memory speed.\n.PP\nThe DR11-W is a 53-line direct memory access (DMA) interface to the PDP-11\nUNIBUS or VAX UBA, which allows the user to control data transfers between\nthe host processor and a peripheral.  The DR11-W has 32 data lines (for\ntransferring 16-bit parallel data) and 21 control lines (for transferring\ncontrol and status information.\n.PP\nWhen used as an interprocessor buffer (IPB), the DR11-W allows\ndata transfers between two processors.  Interprocessor communication is\naccomplished by attaching one DR11-W to each processor UNIBUS\nor UBA and then cabling the two DR11-Ws together.\n.RE\n.PP\nThere.  Now you know as much about it as I do.\n.PP\nA number of \\fIioctl\\fP(2) calls apply to the dr devices, and\nhave the form\n.RS\n.nf\n.ft B\n#include <pdpuba/drreg.h>\nioctl(fildes, code, arg)\nint *arg;\n.ft R\n.fi\n.RE\nThe applicable codes are:\n.IP DRGTTY 18\nGet DR11-W status.\n.IP DRSTTY 18\nSet flags and function.\n.IP DRSFUN 18\nSet function.\n.IP DRSFLAG 18\nSet flags.\n.IP DRGCSR 18\nGet CSR and WCR.\n.IP DRSSIG 18\nSet signal for ATTN interrupt.\n.IP DRESET 18\nReset DR11-W interface.\n.IP DRSTIME 18\nSet timeout.\n.IP DRCTIME 18\nSet timeout inactive.\n.IP DROUTPUT 18\nPut word in output data register.\n.IP DRINPUT 18\nGet word from input data register.\n.IP DRITIME 18\nDon't ignore errors on timeout.\n.SH FILES\n.ta \\w'/dev/MAKEDEV.local  'u\n/dev/dr[0-7]\tdevice special files\n.br\n/dev/MAKEDEV\tscript to create special files\n.br\n/dev/MAKEDEV.local\tscript to localize special files\n.DT\n.SH \"SEE ALSO\"\ndtab(5),\nautoconfig(8)\n.SH DIAGNOSTICS\n\\fBdr%d: error csr=%b, eir=%b\\fR\n.PP\n\\fBdr%d: timeout error\\fR\n.SH BUGS\nThis interface is only available under 2.9BSD and 2.11BSD.  No documentation\nexists on how to use it.\n"
  },
  {
    "path": "share/man/man4/dz.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)dz.4\t6.2 (Berkeley) 1/28/88\n.\\\"\n.TH DZ 4 \"January 28, 1988\"\n.UC 2\n.SH NAME\ndz \\- DZ-11 communications multiplexer\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNDZ\t\\fIdz_units\\fP\t# DZ11; NDZ is in units of boards (8 each)\n\n/etc/dtab:\n.ta .5i +\\w'#Name 'u +\\w'Unit# 'u +\\w'177777 'u +\\w'Vector 'u +\\w'Br 'u +\\w'xxxxxxx 'u +\\w'xxxxxxx 'u\n\t#Name\tUnit#\tAddr\tVector\tBr\tHandler(s)\t\t# Comments\n\tdz\t?\t160100\t310\t5\tdzrint\tdzdma\t# dz11 terminal mux\n.DT\n\nmajor device number:\n\traw: 2\nminor device encoding:\n\tbits 0007 specify line on DZ unit\n\tbits 0170 specify DZ unit\n\tbit  0200 specifies non-blocking open (``CD always on'')\n.SH DESCRIPTION\nA DZ11 provides 8 communication lines with partial modem control,\nadequate for UNIX dialup use.\nEach line attached to the DZ11 communications multiplexer\nbehaves as described in\n.IR tty (4)\nand may be set to run at any of 16 speeds; see\n.IR tty (4)\nfor the encoding.\n.PP\nBit\n.I 0200\nof the minor device number for DZ lines\nmay be set to say that a line is not properly\nconnected, and that the line should be treated as hard-wired with carrier\nalways present.  Thus creating the special character device node \"2, 130\" via\n.I \"mknod /dev/tty02 c 2 130\"\nwould cause line tty02 to be treated in this way.\n.PP\nThe\n.I dz\ndriver monitors the rate of input on each board,\nand switches between the use of character-at-a-time interrupts\nand input silos.\nWhile the silo is enabled during periods of high-speed input,\nthe driver polls for input 30 times per second.\n.SH FILES\n.ta \\w'/dev/MAKEDEV.local  'u\n/dev/tty[0-9][0-9]\n.br\n/dev/ttyd[0-9a-f]\t\tdialups\n.br\n/dev/MAKEDEV\tscript to create special files\n.br\n/dev/MAKEDEV.local\tscript to localize special files\n.DT\n.SH \"SEE ALSO\"\ntty(4),\ndtab(5),\nautoconfig(8)\n.SH DIAGNOSTICS\n.PP\n\\fBdz%d: silo overflow\\fR.  The 64 character input silo overflowed\nbefore it could be serviced.  This can happen if a hard error occurs\nwhen the CPU is running with elevated priority, as the system will\nthen print a message on the console with interrupts disabled.\nIt is not serious.\n"
  },
  {
    "path": "share/man/man4/ec.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ec.4\t6.4 (Berkeley) 8/20/87\n.\\\"\n.TH EC 4 \"August 20, 1987\"\n.UC 2\n.SH NAME\nec \\- 3Com 10 Mb/s Ethernet interface\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNEC\t\\fIec_controllers\\fP\t# 3Com Ethernet\n.fi\n.ft R\n.SH DESCRIPTION\nThe\n.I ec\ninterface provides access to a 10 Mb/s Ethernet network through\na 3com controller.\n.PP\nThe hardware has 32 kilobytes of dual-ported memory on the UNIBUS. \nThis memory\nis used for internal buffering by the board, and the interface code reads\nthe buffer contents directly through the UNIBUS.\nThe address of this memory is given in the \\fIflags\\fP field\nin the configuration file.\nThe first interface normally has its memory at Unibus address 0.\n.PP\nEach of the host's network addresses\nis specified at boot time with an SIOCSIFADDR\nioctl.  The\n.I ec\ninterface employs the address resolution protocol described in\n.IR arp (4P)\nto dynamically map between Internet and Ethernet addresses on the local\nnetwork.\n.PP\nThe interface normally tries to use a ``trailer'' encapsulation\nto minimize copying data on input and output.\nThe use of trailers is negotiated with ARP.\nThis negotiation may be disabled, on a per-interface basis,\nby setting the IFF_NOTRAILERS\nflag with an SIOCSIFFLAGS ioctl.\n.PP\nThe interface software implements an exponential backoff algorithm\nwhen notified of a collision on the cable.  This algorithm utilizes\na 16-bit mask and the VAX-11's interval timer in calculating a series\nof random backoff values.  The algorithm is as follows:\n.TP 5\n1.\nInitialize the mask to be all 1's.\n.TP 5\n2.\nIf the mask is zero, 16 retries have been made and we give\nup.\n.TP 5\n3.\nShift the mask left one bit and formulate a backoff by\nmasking the interval timer with the smaller of the complement of this mask\nand a 5-bit mask, resulting in a pseudo-random number between 0 and 31.\nThis produces the number of slot times to delay,\nwhere a slot is 51 microseconds.\n.TP 5\n4.\nUse the value calculated in step 3 to delay before retransmitting\nthe packet.\nThe delay is done in a software busy loop.\n.SH DIAGNOSTICS\n.BR \"ec%d: send error\" .\nAfter 16 retransmissions using the\nexponential backoff algorithm described above, the packet\nwas dropped.\n.PP\n.BR \"ec%d: input error (offset=%d)\" .\nThe hardware indicated an error\nin reading a packet off the cable or an illegally sized packet.\nThe buffer offset value is printed for debugging purposes.\n.PP\n.BR \"ec%d: can't handle af%d\" .\nThe interface was handed\na message with addresses formatted in an unsuitable address\nfamily; the packet was dropped.\n.SH SEE ALSO\nintro(4N), inet(4F), arp(4P)\n.SH BUGS\nThe hardware is not capable of talking to itself.  The software\nimplements local sending and broadcast by sending such packets to the\nloop interface.  This is a kludge.\n.PP\nBackoff delays are done in a software busy loop.  This can degrade the\nsystem if the network experiences frequent collisions.\n"
  },
  {
    "path": "share/man/man4/en.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)en.4\t6.2 (Berkeley) 8/20/87\n.\\\"\n.TH EN 4 \"August 20, 1987\"\n.UC 2\n.SH NAME\nen \\- Xerox 3 Mb/s Ethernet interface\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNEN\t\\fIen_controllers\\fP\t# Xerox prototype (3 Mb) Ethernet\n.fi\n.ft R\n.SH DESCRIPTION\nThe\n.I en\ninterface provides access to a 3 Mb/s Ethernet network.\nDue to limitations in the hardware, DMA transfers\nto and from the network must take place in the lower 64K bytes\nof the UNIBUS address space, and thus this must be among the first\nUNIBUS devices enabled after boot.\n.PP\nEach of the host's network addresses\nis specified at boot time with an SIOCSIFADDR\nioctl.  The station address is discovered by probing the on-board Ethernet\naddress register, and is used to verify the protocol addresses.\nNo packets will be sent or accepted until \na network address is supplied.\n.PP\nThe interface software implements an exponential backoff algorithm\nwhen notified of a collision on the cable.  This algorithm utilizes\na 16-bit mask and the VAX-11's interval timer in calculating a series\nof random backoff values.  The algorithm is as follows:\n.TP 5\n1.\nInitialize the mask to be all 1's.\n.TP 5\n2.\nIf the mask is zero, 16 retries have been made and we give\nup.\n.TP 5\n3.\nShift the mask left one bit and formulate a backoff by\nmasking the interval timer with the mask (this is actually\nthe two's complement of the value).\n.TP 5\n4.\nUse the value calculated in step 3 to delay before retransmitting\nthe packet.\n.PP\nThe interface handles both Internet and NS protocol families.\nIt normally tries to use a ``trailer'' encapsulation\nto minimize copying data on input and output.\nThe use of trailers is negotiated with ARP.\nThis negotiation may be disabled, on a per-interface basis,\nby setting the IFF_NOTRAILERS\nflag with an SIOCSIFFLAGS ioctl.\n.SH DIAGNOSTICS\n.BR \"en%d: output error\" .\nThe hardware indicated an error on\nthe previous transmission.\n.PP\n.BR \"en%d: send error\" .\nAfter 16 retransmissions using the\nexponential backoff algorithm described above, the packet\nwas dropped.\n.PP\n.BR \"en%d: input error\" .\nThe hardware indicated an error\nin reading a packet off the cable.\n.PP\n.BR \"en%d: can't handle af%d\" .\nThe interface was handed\na message with addresses formatted in an unsuitable address\nfamily; the packet was dropped.\n.SH SEE ALSO\nintro(4N), inet(4F)\n.SH BUGS\nThe device has insufficient buffering to handle back to\nback packets.  This makes use in a production environment\npainful.\n.PP\nThe hardware does word at a time DMA without byte swapping.\nTo compensate, byte swapping of user data must either be done \nby the user or by the system.  A kludge to byte swap only\nIP packets is provided if the ENF_SWABIPS flag is defined in\nthe driver and set at boot time with an SIOCSIFFLAGS ioctl.\n"
  },
  {
    "path": "share/man/man4/fd.4",
    "content": ".\\\" Copyright (c) 1990, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)fd.4\t8.1.1 (2.11BSD) 1997/2/4\n.\\\"\n.TH FD 4 \"February 4, 1997\"\n.UC 4\n.SH NAME\n.BR fd ,\n.BR stdin ,\n.BR stdout ,\n.BR stderr\nfile descriptor files\n.SH DESCRIPTION\nThe files\n.I /dev/fd/0\nthrough\n.I /dev/fd/#\nrefer to file descriptors which can be accessed through the file\nsystem.\nIf the file descriptor is open and the mode the file is being opened\nwith is a subset of the mode of the existing descriptor, the call:\n.sp\n.in +0.5i\nfd = open(\"/dev/fd/0\", mode);\n.in -0.5i\n.PP\nand the call:\n.sp\n.in +0.5i\nfd = fcntl(0, F_DUPFD, 0);\n.in -0.5i\n.PP\nare equivalent.\n.PP\nOpening the files\n.IR /dev/stdin ,\n.I /dev/stdout\nand\n.I /dev/stderr\nis equivalent to the following calls:\n.sp\n.in +0.5i\nfd = fcntl(STDIN_FILENO,  F_DUPFD, 0);\n.br\nfd = fcntl(STDOUT_FILENO, F_DUPFD, 0);\n.br\nfd = fcntl(STDERR_FILENO, F_DUPFD, 0);\n.in -0.5i\n.PP\nFlags to the\nopen(2)\ncall other than O_RDONLY, O_WRONLY and O_RDWR\nare ignored.\n.SH FILES\n/dev/fd/#\n.br\n/dev/stdin\n.br\n/dev/stdout\n.br\n/dev/stderr\n.SH SEE ALSO\ntty(4)\n"
  },
  {
    "path": "share/man/man4/hk.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)hk.4\t6.4 (2.11BSD GTE) 1997/12/28\n.\\\"\n.TH HK 4 \"December 28, 1997\"\n.UC 2\n.SH NAME\nhk \\- RK6-11/RK06 and RK07 moving head disk\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNHK\t\\fIhk_drives\\fP\t# RK611, RK06/07\n\n/etc/dtab:\n.ta .5i +\\w'#Name 'u +\\w'Unit# 'u +\\w'177777 'u +\\w'Vector 'u +\\w'Br 'u +\\w'xxxxxxx 'u +\\w'xxxxxxx 'u\n\t#Name\tUnit#\tAddr\tVector\tBr\tHandler(s)\t\t# Comments\n\thk\t?\t177440\t210\t5\thkintr\t\t# rk611/711 rk06/07\n.DT\n\nmajor device number(s):\n\traw: 13\n\tblock: 4\nminor device encoding:\n\tbits 0007 specify partition of HK drive\n\tbits 0070 specify HK drive\n.fi\n.ft R\n.SH DESCRIPTION\nFiles with minor device numbers 0 through 7 refer to various portions\nof drive 0;\nminor devices 8 through 15 refer to drive 1, etc.\nThe standard device names begin with ``hk'' followed by\nthe drive number and then a letter a-h for partitions 0-7 respectively.\nThe character ? stands here for a drive number in the range 0-7.\n.PP\nThe block files access the disk via the system's normal\nbuffering mechanism and may be read and written without regard to\nphysical disk records.  There is also a `raw' interface\nwhich provides for direct transmission between the disk\nand the user's read or write buffer.\nA single read or write call results in exactly one I/O operation\nand therefore raw I/O is considerably more efficient when\nmany words are transmitted.  The names of the raw files\nconventionally begin with an extra `r.'\n.PP\nIn raw I/O the buffer must begin on a word (even) boundary,\nand counts should be a multiple of 512 bytes (a disk sector).\nLikewise\n.I seek\ncalls should specify a multiple of 512 bytes.\n.SH \"DISK SUPPORT\"\nDisks must be labeled using either the standalone \\fIdisklabel\\fP program on\nthe boot tape or with the \\fIdisklabel\\fP(8) program.  There are no partition\ntables coded into the \\fIhk\\fP drivers, these must be placed on the drive with\n\\fIdisklabel\\fP.\n.PP\nTraditionally the \\fIhk?a\\fP partition is used for the root filesystem, the\n\\fIb\\fP partition as a swap area and the \\fIc\\fP partition for disk to disk\ncopying (it spans the entire disk).\n.PP\nThe kernel uses the \\fIc\\fP partition to access the bad block\ninformation stored at the end of some packs.  Extreme care must be taken when\ncreating file systems on this partition to avoid overwriting any bad block\ninformation present.  User data should use the \\fIh\\fP partition\nwhich should be at least one track (one cylinder might be best) shorter \nthan the \\fIc\\fP partition.\n.SH FILES\n.ta \\w'/dev/MAKEDEV.local  'u\n/dev/hk[0-7][a-h]\tblock files\n.br\n/dev/rhk[0-7][a-h]\traw files\n.br\n/dev/MAKEDEV\tscript to create special files\n.br\n/dev/MAKEDEV.local\tscript to localize special files\n.DT\n.SH \"SEE ALSO\"\nra(4)\nram(4),\nrk(4),\nrl(4),\nrx(4),\nsi(4),\nxp(4),\ndtab(5),\nautoconfig(8),\ndisklabel(8)\n.SH DIAGNOSTICS\n\\fBhk%d%c: hard error sn%d cs2=%b ds=%b er=%b\\fR.  An unrecoverable\nerror occurred during transfer of the specified sector of the specified\ndisk partition.  The contents of the cs2, ds and er registers are printed\nin octal and symbolically with bits decoded.\nThe error was either unrecoverable, or a large number of retry attempts\n(including offset positioning and drive recalibration) could not\nrecover the error.\n.PP\n\\fBhk%d: write locked\\fP.  The write protect switch was set on the drive\nwhen a write was attempted.  The write operation is not recoverable.\n.PP\n\\fBhk%d: not ready\\fR.  The drive was spun down or off line when it was\naccessed.  The i/o operation is not recoverable.\n.PP\n\\fBhk%d: not ready (came back!)\\fR.  The drive was not ready, but after\nprinting the message about being not ready (which takes a fraction\nof a second) was ready.  The operation is recovered if no further\nerrors occur.\n.PP\n\\fBhk%d%c: soft ecc sn%d\\fP.  A recoverable ECC error occurred on the\nspecified sector of the specified disk partition. \nThis happens normally\na few times a week.  If it happens more frequently than\nthis the sectors where the errors are occuring should be checked to see\nif certain cylinders on the pack, spots on the carriage of the drive\nor heads are indicated.\n.SH BUGS\nIn raw I/O\n.I read\nand\n.IR write (2)\ntruncate file offsets to 512-byte block boundaries,\nand\n.I write\nscribbles on the tail of incomplete blocks.\nThus,\nin programs that are likely to access raw devices,\n.I read, write\nand\n.IR lseek (2)\nshould always deal in 512-byte multiples.\n.PP\nDEC-standard error logging should be supported.\n.PP\nA program to analyze the logged error information (even in its\npresent reduced form) is needed.\n"
  },
  {
    "path": "share/man/man4/ht.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ht.4\t6.2 (Berkeley) 1/28/88\n.\\\"\n.TH HT 4 \"January 28, 1988\"\n.UC 2\n.SH NAME\nht \\- TM-03/TE-16,TU-45,TU-77 MASSBUS magtape interface\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNHT\t\\fIht_drives\\fP\t# TE16, TU45, TU77\n\n/etc/dtab:\n.ta .5i +\\w'#Name 'u +\\w'Unit# 'u +\\w'177777 'u +\\w'Vector 'u +\\w'Br 'u +\\w'xxxxxxx 'u +\\w'xxxxxxx 'u\n\t#Name\tUnit#\tAddr\tVector\tBr\tHandler(s)\t\t# Comments\n\tht\t?\t172440\t224\t5\thtintr\t\t# tu 16 massbus tape\n.DT\n\nmajor device number(s):\n\traw: 6\n\tblock: 0\nminor device encoding:\n\tbits 0003 specify HT drive\n\tbit  0004 specifies no-rewind operation\n\tbit  0010 specifies 1600BPI recording density instead of 800BPI\n.fi\n.ft R\n.SH DESCRIPTION\nThe tm-03/transport combination provides a standard tape drive\ninterface as described in\n.IR mtio (4).\nAll drives provide both 800 and 1600 bpi; the TE-16 runs at 45 ips,\nthe TU-45 at 75 ips, while the TU-77 runs at 125 ips and autoloads tapes.\n.SH FILES\n.ta \\w'/dev/MAKEDEV.local  'u\n/dev/MAKEDEV\tscript to create special files\n.br\n/dev/MAKEDEV.local\tscript to localize special files\n.DT\n.SH \"SEE ALSO\"\nmt(1),\ntar(1),\ntp(1),\nmtio(4),\ntm(4),\nts(4),\ndtab(5),\nautoconfig(8)\n.SH DIAGNOSTICS\n\\fBtu%d: no write ring\\fR.  An attempt was made to write on the tape drive\nwhen no write ring was present; this message is written on the terminal of\nthe user who tried to access the tape.\n.PP\n\\fBtu%d: not online\\fR.  An attempt was made to access the tape while it\nwas offline; this message is written on the terminal of the user\nwho tried to access the tape.\n.PP\n\\fBtu%d: can't change density in mid-tape\\fR.  An attempt was made to write\non a tape at a different density than is already recorded on the tape.\nThis message is written on the terminal of the user who tried to switch\nthe density.\n.PP\n\\fBtu%d: hard error bn%d er=%b ds=%b\\fR.   A tape error occurred\nat block \\fIbn\\fR; the ht error register and drive status register are\nprinted in octal with the bits symbolically decoded.  Any error is\nfatal on non-raw tape; when possible the driver will have retried\nthe operation which failed several times before reporting the error.\n.SH BUGS\nIf any non-data error is encountered on non-raw tape, it refuses to do anything\nmore until closed.\n.PP\nThe system should remember which controlling terminal has the tape drive\nopen and write error messages to that terminal rather than on the console.\n"
  },
  {
    "path": "share/man/man4/hy.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)hy.4\t6.1 (Berkeley) 8/20/87\n.\\\"\n.TH HY 4 \"August 20, 1987\"\n.UC 2\n.SH NAME\nhy \\- Network Systems Hyperchannel interface\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNHY\t\\fihy_controllers\\fP\t# Hyperchannel\n.fi\n.ft R\n.SH DESCRIPTION\nThe\n.I hy\ninterface provides access to a Network\nSystems Corporation Hyperchannel Adapter.\n.PP\nThe network to which the interface is attached\nis specified at boot time with an SIOCSIFADDR ioctl.  \nThe host's address is discovered by reading the adapter status\nregister.  The interface will not transmit or receive\npackets until the network number is known.\n.SH DIAGNOSTICS\n\\fBhy%d: unit number 0x%x port %d type %x microcode level 0x%x\\fP.\nIdentifies the device during autoconfiguration.\n.PP\n\\fBhy%d: can't handle af%d\\fP.  The interface was handed\na message with addresses formatted in an unsuitable address\nfamily; the packet was dropped.\n.PP\n\\fBhy%d: can't initialize\\fP.\nThe interface was unable to allocate UNIBUS resources. This\nis usually due to having too many network devices on an 11/750\nwhere there are only 3 buffered data paths.\n.PP\n\\fBhy%d: NEX - Non Existent Memory\\fP.\nNon existent memory error returned from hardware.\n.PP\n\\fBhy%d:  BAR overflow\\fP.  Bus address register\noverflow error returned from hardware.\n.PP\n\\fBhy%d: Power Off bit set, trying to reset\\fP.\nAdapter has lost power, driver will reset the bit\nand see if power is still out in the adapter.\n.PP\n\\fBhy%d: Power Off Error, network shutdown\\fP.\nPower was really off in the adapter, network\nconnections are dropped.\nSoftware does not shut down the network unless\npower has been off for a while.\n.PP\n\\fBhy%d: RECVD MP > MPSIZE (%d)\\fP.\nA message proper was received that is too big.\nProbable a driver bug.\nShouldn't happen.\n.PP\n\\fBhy%d: xmit error \\- len > hy_olen [%d > %d]\\fP.\nProbable driver error.\nShouldn't happen.\n.PP\n\\fBhy%d: DRIVER BUG \\- INVALID STATE %d\\fP.\nThe driver state machine reached a non-existent state.\nDefinite driver bug.\n.PP\n\\fBhy%d: watchdog timer expired\\fP.\nA command in the adapter has taken too long to complete.\nDriver will abort and retry the command.\n.PP\n\\fBhy%d: adapter power restored\\fP.\nSoftware was able to reset the power off bit,\nindicating that the power has been restored.\n.SH SEE ALSO\nintro(4N), inet(4F)\n.SH BUGS\nIf the adapter does not respond to the status command\nissued during autoconfigure, the adapter is assumed down.\nA reboot is required to recognize it.\n.PP\nThe adapter power fail interrupt seems to occur\nsporadically when power has, in fact, not failed.\nThe driver will believe that power has failed\nonly if it can not reset the power fail latch after\na ``reasonable'' time interval.\nThese seem to appear about 2-4 times a day on some machines.\nThere seems to be no correlation with adapter\nrev level, number of ports used etc. and whether a\nmachine will get these ``bogus powerfails''.\nThey don't seem to cause any real problems so they have\nbeen ignored.\n"
  },
  {
    "path": "share/man/man4/icmp.4",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)icmp.4p\t6.1 (Berkeley) 5/16/86\n.\\\"\n.TH ICMP 4P \"May 16, 1986\"\n.UC 6\n.SH NAME\nicmp \\- Internet Control Message Protocol\n.SH SYNOPSIS\n.B #include <sys/socket.h>\n.br\n.B #include <netinet/in.h>\n.PP\n.B s = socket(AF_INET, SOCK_RAW, proto);\n.SH DESCRIPTION\nICMP is the error and control message protocol used\nby IP and the Internet protocol family.  It may be accessed\nthrough a \\*(lqraw socket\\*(rq for network monitoring\nand diagnostic functions.\nThe\n.I proto\nparameter to the socket call to create an ICMP socket\nis obtained from\n.IR getprotobyname (3N).\nICMP sockets are connectionless,\nand are normally used with the\n.I sendto \nand\n.I recvfrom \ncalls, though the\n.IR connect (2)\ncall may also be used to fix the destination for future\npackets (in which case the \n.IR read (2)\nor\n.IR recv (2)\nand \n.IR write (2)\nor\n.IR send (2)\nsystem calls may be used).\n.PP\nOutgoing packets automatically have an IP header prepended to\nthem (based on the destination address).\nIncoming packets are received with the IP header and options intact.\n.SH DIAGNOSTICS\nA socket operation may fail with one of the following errors returned:\n.TP 15\n[EISCONN]\nwhen trying to establish a connection on a socket which\nalready has one, or when trying to send a datagram with the destination\naddress specified and the socket is already connected;\n.TP 15\n[ENOTCONN]\nwhen trying to send a datagram, but\nno destination address is specified, and the socket hasn't been\nconnected;\n.TP 15\n[ENOBUFS]\nwhen the system runs out of memory for\nan internal data structure;\n.TP 15\n[EADDRNOTAVAIL]\nwhen an attempt is made to create a \nsocket with a network address for which no network interface\nexists.\n.SH SEE ALSO\nsend(2), recv(2), intro(4N), inet(4F), ip(4P)\n"
  },
  {
    "path": "share/man/man4/idp.4",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)idp.4p\t1.1 (Berkeley) 7/30/85\n.\\\"\n.TH IDP 4P \"July 30, 1985\"\n.UC 6\n.SH NAME\nidp \\- Xerox Internet Datagram Protocol\n.SH SYNOPSIS\n.B #include <sys/socket.h>\n.br\n.B #include <netns/ns.h>\n.br\n.B #include <netns/idp.h>\n.PP\n.B s = socket(AF_NS, SOCK_DGRAM, 0);\n.SH DESCRIPTION\nIDP is a simple, unreliable datagram protocol which is used\nto support the SOCK_DGRAM abstraction for the Internet\nprotocol family.  IDP sockets are connectionless, and are\nnormally used with the\n.I sendto \nand\n.IR recvfrom \ncalls, though the\n.IR connect (2)\ncall may also be used to fix the destination for future\npackets (in which case the \n.IR recv (2)\nor\n.IR read (2)\nand \n.IR send (2)\nor\n.IR write(2)\nsystem calls may be used).\n.PP\nXerox protocols are built vertically on top of IDP.\nThus, IDP address formats are identical to those used by\nSPP.\nNote that the IDP port\nspace is the same as the SPP port space (i.e. a IDP port\nmay be \\*(lqconnected\\*(rq to a SPP port, with certain\noptions enabled below).\nIn addition broadcast packets may be sent\n(assuming the underlying network supports\nthis) by using a reserved \\*(lqbroadcast address\\*(rq; this address\nis network interface dependent.\n.SH DIAGNOSTICS\nA socket operation may fail with one of the following errors returned:\n.TP 15\n[EISCONN]\nwhen trying to establish a connection on a socket which\nalready has one, or when trying to send a datagram with the destination\naddress specified and the socket is already connected;\n.TP 15\n[ENOTCONN]\nwhen trying to send a datagram, but\nno destination address is specified, and the socket hasn't been\nconnected;\n.TP 15\n[ENOBUFS]\nwhen the system runs out of memory for\nan internal data structure;\n.TP 15\n[EADDRINUSE]\nwhen an attempt\nis made to create a socket with a port which has already been\nallocated;\n.TP 15\n[EADDRNOTAVAIL]\nwhen an attempt is made to create a \nsocket with a network address for which no network interface\nexists.\n.SH SOCKET OPTIONS\n.TP 15\n[SO_HEADERS_ON_INPUT]\nWhen set, the first 30 bytes of any data returned from a read\nor recv from will be the initial 30 bytes of the IDP packet,\nas described by\n.nf\nstruct idp {\n\tu_short\t\tidp_sum;\n\tu_short\t\tidp_len;\n\tu_char\t\tidp_tc;\n\tu_char\t\tidp_pt;\n\tstruct ns_addr\tidp_dna;\n\tstruct ns_addr\tidp_sna;\n};\n.fi\nThis allows the user to determine the packet type, and whether\nthe packet was a multi-cast packet or directed specifically at\nthe local host.\nWhen requested, gives the current state of the option,\n(NSP_RAWIN or 0).\n.TP 15\n[SO_HEADERS_ON_OUTPUT]\nWhen set, the first 30 bytes of any data sent\nwill be the initial 30 bytes of the IDP packet.\nThis allows the user to determine the packet type, and whether\nthe packet should be multi-cast packet or directed specifically at\nthe local host.\nYou can also misrepresent the sender of the packet.\nWhen requested, gives the current state of the option.\n(NSP_RAWOUT or 0).\n.TP 15\n[SO_DEFAULT_HEADERS]\nThe user provides the kernel an IDP header, from which\nit gleans the Packet Type.\nWhen requested, the kernel will provide an IDP header, showing\nthe default packet type, and local and foreign addresses, if\nconnected.\n.TP 15\n[SO_ALL_PACKETS]\nWhen set, this option defeats automatic processing of Error packets,\nand Sequence Protocol packets.\n.TP 15\n[SO_SEQNO]\nWhen requested, this returns a sequence number which is not likely\nto be repeated until the machine crashes or a very long time has passed.\nIt is useful in constructing Packet Exchange Protocol packets.\n.SH SEE ALSO\nsend(2),\nrecv(2),\nintro(4N),\nns(4F)\n"
  },
  {
    "path": "share/man/man4/il.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)il.4\t6.4 (Berkeley) 8/20/87\n.\\\"\n.TH IL 4 \"August 20, 1987\"\n.UC 2\n.SH NAME\nil \\- Interlan NI1010 10 Mb/s Ethernet interface\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNIL\t\\fIil_controllers\\fP\t# Interlan Ethernet\n.fi\n.ft R\n.SH DESCRIPTION\nThe\n.I il\ninterface provides access to a 10 Mb/s Ethernet network through\nan Interlan 1010 or 1010A controller.\n.PP\nEach of the host's network addresses\nis specified at boot time with an SIOCSIFADDR\nioctl.  The\n.I il\ninterface employs the address resolution protocol described in\n.IR arp (4P)\nto dynamically map between Internet and Ethernet addresses on the local\nnetwork.\n.PP\nThe interface normally tries to use a ``trailer'' encapsulation\nto minimize copying data on input and output.\nThe use of trailers is negotiated with ARP.\nThis negotiation may be disabled, on a per-interface basis,\nby setting the IFF_NOTRAILERS\nflag with an SIOCSIFFLAGS ioctl.\n.SH DIAGNOSTICS\n\\fBil%d: input error\\fP.  The hardware indicated an error\nin reading a packet off the cable or an illegally sized packet.\n.PP\n\\fBil%d: can't handle af%d\\fP.  The interface was handed\na message with addresses formatted in an unsuitable address\nfamily; the packet was dropped.\n.PP\n\\fBil%d: setaddr didn't work\\fP.  The interface was unable to reprogram\nits physical ethernet address.\nThis may happen with very early models of the interface.\nThis facility is used only when\nthe controller is not the first network interface configured for XNS.\nThe oldest interface tested (2.7.1.0.1.45) has never failed in this way.\n.PP\nThe following messages indicate a probable hardware error performing\nthe indicated operation during autoconfiguration or initialization.\nThe status field in the control and status register (the low-order four bits)\nshould indicate the nature of the failure.\nSee the hardware manual for details.\n.PP\n\\fBil%d: reset failed, csr=%b\\fP.\n.PP\n\\fBil%d: status failed, csr=%b\\fP.\n.PP\n\\fBil%d: hardware diag failed, csr=%b\\fP.\n.PP\n\\fBil%d: verifying setaddr, csr=%b\\fP.\n.PP\n\\fBil%d: stray xmit interrupt, csr=%b\\fP.\n.PP\n\\fBil%d: can't initialize\\fP.\n.SH SEE ALSO\nintro(4N), inet(4F), arp(4P)\n"
  },
  {
    "path": "share/man/man4/imp.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)imp.4p\t6.2 (Berkeley) 5/16/86\n.\\\"\n.TH IMP 4P \"May 16, 1986\"\n.UC 5\n.SH NAME\nimp \\- IMP raw socket interface\n.SH SYNOPSIS\n.B #include <sys/socket.h>\n.br\n.B #include <netinet/in.h>\n.br\n.B #include <netimp/if_imp.h>\n.PP\n.B s = socket(AF_IMPLINK, SOCK_RAW, proto);\n.SH DESCRIPTION\nThe raw imp socket provides direct access to the\n.IR imp (4)\nnetwork interface.  Users send packets through\nthe interface using the \n.IR send (2)\ncalls, and receive packets with the\n.IR recv (2),\ncalls.  All outgoing packets must have an 1822 96-bit\nleader on the front.  Likewise, packets received\nby the user will have this leader on the front.  The\n1822 leader and the legal values for the various fields\nare defined in the include file\n.RI < netimp/if_imp.h >.\nThe raw imp interface automatically installs the length\nand destination address in the 1822 leader of all\noutgoing packets; these need not be filled in by the user.\n.PP\nIf the protocol selected,\n.IR proto ,\nis zero,\nthe socket will receive\nall IMP messages except RFNM and incompletes\nwhich are not input data for a kernel protocol.\nIf\n.I proto\nis non-zero,\nonly messages for the specified link type will be received.\n.SH DIAGNOSTICS\nAn operation on a socket may fail with one of the following\nerrors:\n.TP 15\n[EISCONN]\nwhen trying to establish a connection on a socket which\nalready has one, or when trying to send a datagram with the destination\naddress specified and the socket is already connected;\n.TP 15\n[ENOTCONN]\nwhen trying to send a datagram, but\nno destination address is specified, and the socket hasn't been\nconnected;\n.TP 15\n[ENOBUFS]\nwhen the system runs out of memory for\nan internal data structure;\n.TP 15\n[ENOBUFS]\neight messages to the destination host are outstanding,\nand another eight are already queued for output;\n.TP 15\n[EADDRNOTAVAIL]\nwhen an attempt is made to create a \nsocket with a network address for which no network interface\nexists.\n.SH SEE ALSO\nintro(4N), inet(4F), imp(4)\n"
  },
  {
    "path": "share/man/man4/impconf.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)imp.4\t6.2 (Berkeley) 8/2/87\n.\\\"\n.TH IMP 4 \"August 2, 1987\"\n.UC 2\n.SH NAME\nimp \\- 1822 network interface\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNIMP\t\\fIcount\\fP\t# ARPAnet IMP 1822 interface\n.fi\n.ft R\n.SH DESCRIPTION\nThe \n.I imp\ninterface, as described in BBN Report 1822, provides access to an\nintelligent message processor normally used when participating\nin the Department of Defense ARPA network.  The network interface\ncommunicates through a device controller, usually an ACC LH/DH or HDH\nor a DEC IMP-11A, with the IMP.  The interface is \\*(lqreliable\\*(rq and\n\\*(lqflow-controlled\\*(rq by the host-IMP protocol.\n.PP\nTo configure IMP support, at least one of \n.IR acc (4),\n.IR css (4)\nor\n.IR hdh (4)\nmust be included.\nThe\n.I count\nspecifies the total number of IMP connections.\nThe network number on which the interface resides is specified\nat boot time using the SIOCSIFADDR ioctl.  The host number is\ndiscovered through receipt of NOOP messages from the IMP.\n.PP\nThe network interface is always in one of four states: up, down,\ninitializing, or going down.  When the system is\nbooted, the interface is marked down.  If the hardware controller\nis successfully probed, the interface enters the initializing\nstate and transmits three NOOP messages to the IMP.  It then waits\nfor the IMP to respond with two or more NOOP messages in reply.\nWhen it receives these messages it enters the up state.  The ``going\ndown'' state is entered only when notified by the IMP of an impending\nshutdown.  Packets may be sent through the interface only while it\nis in the up state.  Outgoing packets are dropped\nwith the error ENETDOWN returned to the caller if the interface\nis in any other state.\n.SH DIAGNOSTICS\n\\fBimp%d: not configured\\fP.\nA hardware interface could not be attached during autoconfiguration\nbecause too few IMP pseudo-devices were configured.\n.PP\n\\fBimp%d: leader error\\fP.  The IMP reported an error in a leader\n(1822 message header).  This causes the interface to be reset and\nany packets queued up for transmission to be purged.\n.PP\n\\fBimp%d: going down in 30 seconds\\fP.\n.br\n\\fBimp%d: going down for hardware PM\\fP.\n.br\n\\fBimp%d: going down for reload software\\fP.\n.br\n\\fBimp%d: going down for emergency reset\\fP.\nThe Network Control Center (NCC) is manipulating the IMP.  By convention\nthese messages are reported to all hosts on an IMP.\n.PP\n\\fBimp?: host %x, lost %d rfnms\\fP.\nThe IMP had messages outstanding to the host listed,\nbut no RFNM (Request for Next Message) messages were received from the IMP\nin 127 seconds.\nThe software state for that host is reinitialized.\n.PP\n\\fBimp%d: interface reset\\fP.  The host has received an\ninterface reset message from the IMP.\n.PP\n\\fBimp%d: address reset to x%x (%d/%d)\\fP.  The host has received a\nNOOP message which caused it to reset its notion of its\ncurrent address.\nThe Internet address is printed in hexadecimal, with the host and IMP\nnumbers following.\nThis indicates that the address originally set by\n.IR ifconfig (8)\nwas incorrect, that the IMP has undergone an identity crisis,\nor that communication between the IMP and the host is being garbled.\n.PP\n\\fBimp%d: data error\\fP.  The IMP noted an error in data\ntransmitted.  The host-IMP interface is reset and the host\nenters the init state (awaiting NOOP messages).\n.PP\n\\fBimp%d: interface reset\\fP.  The reset process has been\ncompleted.\n.PP\n\\fBimp%d: marked down\\fP.  After receiving a \\*(lqgoing down in\n30 seconds\\*(rq message, and waiting 30 seconds, the host has\nmarked the IMP unavailable.  Before packets may be sent to the\nIMP again, the IMP must notify the host, through a series of\nNOOP messages, that it is back up.\n.PP\n\\fBimp%d: can't handle af%d\\fP.  The interface was handed\na message with addresses formatting in an unsuitable address\nfamily; the packet was dropped.\n.SH SEE ALSO\nintro(4N),\ninet(4F),\nacc(4),\ncss(4),\nhdh(4),\nimplog(8),\nimplogd(8)\n"
  },
  {
    "path": "share/man/man4/inet.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)inet.4f\t6.3 (Berkeley) 8/1/87\n.\\\"\n.TH INET 4F \"August 1, 1987\"\n.UC 5\n.SH NAME\ninet \\- Internet protocol family\n.SH SYNOPSIS\n.B #include <sys/types.h>\n.br\n.B #include <netinet/in.h>\n.SH DESCRIPTION\n.de _d\n.if t .ta .6i 2.1i 2.6i\n.\\\" 2.94 went to 2.6, 3.64 to 3.30\n.if n .ta .84i 2.6i 3.30i\n..\n.de _f\n.if t .ta .5i 1.25i 2.5i\n.\\\" 3.5i went to 3.8i\n.if n .ta .7i 1.75i 3.8i\n..\nThe Internet protocol family is a collection of protocols\nlayered atop the\n.I Internet Protocol\n(IP) transport layer, and utilizing the Internet address format.\nThe Internet family provides protocol support for the\nSOCK_STREAM, SOCK_DGRAM, and SOCK_RAW socket types; the\nSOCK_RAW interface provides access to the IP protocol.\n.SH ADDRESSING\nInternet addresses are four byte quantities, stored in network standard\nformat: layed out as highest to lowest order bytes in memory or ``Big\nEndian'' (the VAX is word and byte reversed, or ``Little Endian''; the\nPDP-11 is byte reversed within each word, or ``Middle Endian'').\nThe include file\n.RI < netinet/in.h >\ndefines this address\nas a discriminated union.\n.PP\nSockets bound to the Internet protocol family utilize\nthe following addressing structure,\n.sp 1\n.nf\n._f\nstruct sockaddr_in {\n\tshort\tsin_family;\n\tu_short\tsin_port;\n\tstruct\tin_addr sin_addr;\n\tchar\tsin_zero[8];\n};\n.sp 1\n.fi\nSockets may be created with the local address INADDR_ANY\nto effect \\*(lqwildcard\\*(rq matching on incoming messages. \nThe address in a\n.IR connect (2)\nor\n.IR sendto (2)\ncall may be given as INADDR_ANY to mean ``this host.''\nThe distinguished address INADDR_BROADCAST\nis allowed as a shorthand for the broadcast address on the primary\nnetwork if the first network configured supports broadcast.\n.SH PROTOCOLS\nThe Internet protocol family is comprised of\nthe IP transport protocol, Internet Control\nMessage Protocol (ICMP), Transmission Control\nProtocol (TCP), and User Datagram Protocol (UDP).\nTCP is used to support the SOCK_STREAM\nabstraction while UDP is used to support the SOCK_DGRAM\nabstraction.  A raw interface to IP is available\nby creating an Internet socket of type SOCK_RAW.\nThe ICMP message protocol is accessible from a raw socket.\n.PP\nThe 32-bit Internet address contains both network and host parts.\nIt is frequency-encoded; the most-significant bit is clear\nin Class A addresses, in which the high-order 8 bits are the network\nnumber.\nClass B addresses use the high-order 16 bits as the network field,\nand Class C addresses have a 24-bit network part.\nSites with a cluster of local networks and a connection to the DARPA\nInternet may chose to use a single network number for the cluster;\nthis is done by using subnet addressing.\nThe local (host) portion of the address is further subdivided\ninto subnet and host parts.\nWithin a subnet, each subnet appears to be an individual network;\nexternally, the entire cluster appears to be a single, uniform\nnetwork requiring only a single routing entry.\nSubnet addressing is enabled and examined by the following\n.IR ioctl (2)\ncommands on a datagram socket in the Internet domain;\nthey have the same form as the\nSIOCIFADDR command (see\n.IR intro (4N)).\n.PP\n.TP 20\nSIOCSIFNETMASK\nSet interface network mask.\nThe network mask defines the network part of the address;\nif it contains more of the address than the address type would indicate,\nthen subnets are in use.\n.TP 20\nSIOCGIFNETMASK\nGet interface network mask.\n.SH SEE ALSO\nioctl(2), socket(2), intro(4N), tcp(4P), udp(4P), ip(4P), icmp(4P)\n.PP\nAn Introductory 4.3BSD Interprocess Communication Tutorial (PS1:7).\n.PP\nAn Advanced 4.3BSD Interprocess Communication Tutorial (PS1:8).\n.SH CAVEAT\nThe Internet protocol support is subject to change as\nthe Internet protocols develop.  Users should not depend\non details of the current implementation, but rather\nthe services exported.\n"
  },
  {
    "path": "share/man/man4/intro.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)intro.4\t6.3.1 (2.11BSD) 1996/1/27\n.\\\"\n.TH INTRO 4 \"January 27, 1996\"\n.UC 4\n.SH NAME\nintro \\- introduction to special files and hardware support\n.SH DESCRIPTION\nThis section describes the special files, related driver functions,\nand networking support\navailable in the system.\nIn this part of the manual, the SYNOPSIS section of\neach configurable device gives a sample specification\nfor use in constructing a system description for the\n.IR /sys/conf/config script,\nthe\n.IR autoconfig (8),\nprogram and descibes the major and minor device numbers and their encoding.\nThe DIAGNOSTICS section lists messages which may appear on the console\nand/or in the system error log\n.I /usr/adm/messages\ndue to errors in device operation.\n.PP\nThis section contains both devices\nwhich may be configured into the system, ``4'' entries,\nand network related information,\n``4N'', ``4P'', and ``4F'' entries;\nThe networking support is introduced in\n.IR intro (4N).\n.SH \"PDP DEVICE SUPPORT\"\nThis section describes the hardware supported on the DEC PDP-11.\nSoftware support for these devices comes in two forms.  A hardware\ndevice may be supported with a character or block\n.IR \"device driver\" ,\nor it may be used within the networking subsystem and have a\n.IR \"network interface driver\" .\nBlock and character devices are accessed through files in the file\nsystem of a special type; c.f.\n.IR mknod (8).\nNetwork interfaces are indirectly accessed through the interprocess\ncommunication facilities provided by the system; see\n.IR socket (2).\n.PP\nA hardware device is identified to the system at configuration time\nand the appropriate device or network interface driver is then compiled\ninto the system.  When the resultant system is booted, the\nautoconfiguration facilities in the system probe for the device\non either the UNIBUS (or Q-bus) or MASSBUS and, if found, enable the software\nsupport for it.  If a device does not respond at autoconfiguration\ntime it is not accessible at any time afterwards.  To\nenable a device which did not autoconfigure, the system will have to\nbe rebooted.\n.PP\nThe autoconfiguration system is described in\n.IR autoconfig (8).\nA list of the supported devices is given below.\n.SH SEE ALSO\nintro(4), networking(4), config(8).\n.SH \"LIST OF DEVICES\"\nThe devices listed below are supported in this incarnation of\nthe system.  Pseudo-devices are not listed.\nListed also are devices which are in various stages of porting to\n2.11BSD from 4.3BSD.\n.PP\nDevices are indicated by their functional interface.\nIf second vendor products provide functionally identical interfaces\nthey should be usable with the supplied software.\n(\\fBBeware, however, that we promise the software works\nONLY with the hardware indicated on the appropriate manual page.\\fP)\nOccasionally, new devices of a similar type may be added\nsimply by creating appropriate table entries in the driver.\n.sp\n.ta 1.0i\n.nf\n.ne 4\n.B \"The following are known to work:\"\nacc\tACC LH/DH IMP communications interface\nde\tDEC DEUNA 10Mb/s Ethernet controller\ndh\tDH-11 emulators, terminal multiplexor\ndhu\tDHU-11 terminal multiplexor\ndz\tDZ-11 terminal multiplexor\nec\t3Com 10Mb/s Ethernet controller\nhk\tRK6-11/RK06 and RK07 moving head disk\nht\tTM03 MASSBUS tape drive interface (with TE-16, TU-45, TU-77)\nil\tInterlan 1010, 1010A, 2010A 10Mb/s Ethernet controller\nlp\tLP-11 parallel line printer interface\nqe\tDEC DEQNA Q-bus 10 Mb/s Ethernet interface\nra\tDEC UDA-50, RQDX, KLESI disk controllers\nrk\tDEC RK05 disk controller\nrl\tDEC RL-11 disk controller\nrx\tDEC RX02 floppy interface\nsi\tSI 9500 disk controller\ntm\tTM-11/TE-10 tape drive interface\ntmscp\tTMSCP-compatible tape controllers (e.g., TU81, TK50)\nts\tTS-11 tape drive interface\nvv\tProteon proNET 10Mb/s and 80Mb/s ring network interface\nxp\tGeneral purpose SMD disk controller\n\n.ne 4\n.B \"The following should work:\"\ndr\tDR-11W general purpose DMA UNIBUS interface\n\n.ne 4\n.B \"The following worked in the past but will probably require work:\"\ncss\tDEC IMP-11A communications interface\ndmc\tDEC DMC-11/DMR-11 point-to-point communications device\nen\tXerox 3Mb/s Ethernet controller (obsolete)\nsri\tDR-11C IMP interface\n\n.ne 4\n.B \"It should be possible to port these from 4.3BSD:\"\nex\tExcelan 10Mb/s Ethernet controller\nix\tInterlan NP-100 10Mb/s Ethernet controller\nnp\tInterlan NP-100 10Mb/s Ethernet controller (intelligent mode)\npcl\tDEC PCL-11 communications interface\n\n.ne 4\n.B \"No idea whether any of the following could be ported:\"\nad\tData translation A/D interface\nct\tC/A/T or APS phototypesetter\nddn\tACC ACP625 DDN Standard Mode X.25 IMP interface\ndmf\tDEC DMF-32 terminal multiplexor and parallel printer interface\ndmz\tDEC DMZ-32 terminal multiplexor\ndn\tDEC DN-11 autodialer interface\nhdh\tACC IF-11/HDH IMP interface\nhp\tMASSBUS disk interface (with RP06, RM03, RM05, etc.)\nhy\tDR-11B or GI-13 interface to an NSC Hyperchannel\nkg\tKL-11/DL-11W line clock\nmt\tTM78 MASSBUS tape drive interface\ntu\tVAX-11/730 TU58 console cassette interface\nun\tDR-11W interface to Ungermann-Bass\nup\tEmulex SC-21V, SC-31 UNIBUS disk controller\nut\tUNIBUS TU-45 tape drive interface\nuu\tTU58 dual cassette drive interface (DL11)\nva\tBenson-Varian printer/plotter interface\nvp\tVersatec printer/plotter interface\n"
  },
  {
    "path": "share/man/man4/ip.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ip.4p\t6.2 (Berkeley) 5/16/86\n.\\\"\n.TH IP 4P \"May 16, 1986\"\n.UC 5\n.SH NAME\nip \\- Internet Protocol\n.SH SYNOPSIS\n.B #include <sys/socket.h>\n.br\n.B #include <netinet/in.h>\n.PP\n.B s = socket(AF_INET, SOCK_RAW, proto);\n.SH DESCRIPTION\nIP is the transport layer protocol used\nby the Internet protocol family.\nOptions may be set at the IP level\nwhen using higher-level protocols that are based on IP\n(such as TCP and UDP).\nIt may also be accessed\nthrough a \\*(lqraw socket\\*(rq when developing new protocols, or\nspecial purpose applications.\n.PP\nA single generic option is supported at the IP level, IP_OPTIONS,\nthat may be used to provide IP options to be transmitted in the IP\nheader of each outgoing packet.\nOptions are set with\n.IR setsockopt (2)\nand examined with\n.IR getsockopt (2).\nThe format of IP options to be sent is that specified by the IP protocol\nspecification, with one exception:\nthe list of addresses for Source Route options must include the first-hop\ngateway at the beginning of the list of gateways.\nThe first-hop gateway address will be extracted from the option list\nand the size adjusted accordingly before use.\nIP options may be used with any socket type in the Internet family.\n.PP\nRaw IP sockets are connectionless,\nand are normally used with the\n.I sendto \nand\n.I recvfrom \ncalls, though the\n.IR connect (2)\ncall may also be used to fix the destination for future\npackets (in which case the \n.IR read (2)\nor\n.IR recv (2)\nand \n.IR write (2)\nor\n.IR send (2)\nsystem calls may be used).\n.PP\nIf\n.I proto\nis 0, the default protocol IPPROTO_RAW is used for outgoing\npackets, and only incoming packets destined for that protocol\nare received.\nIf\n.I proto\nis non-zero, that protocol number will be used on outgoing packets\nand to filter incoming packets.\n.PP\nOutgoing packets automatically have an IP header prepended to\nthem (based on the destination address and the protocol\nnumber the socket is created with).\nIncoming packets are received with IP header and options intact.\n.SH DIAGNOSTICS\nA socket operation may fail with one of the following errors returned:\n.TP 15\n[EISCONN]\nwhen trying to establish a connection on a socket which\nalready has one, or when trying to send a datagram with the destination\naddress specified and the socket is already connected;\n.TP 15\n[ENOTCONN]\nwhen trying to send a datagram, but\nno destination address is specified, and the socket hasn't been\nconnected;\n.TP 15\n[ENOBUFS]\nwhen the system runs out of memory for\nan internal data structure;\n.TP 15\n[EADDRNOTAVAIL]\nwhen an attempt is made to create a \nsocket with a network address for which no network interface\nexists.\n.PP\nThe following errors specific to IP\nmay occur when setting or getting IP options:\n.TP 15\n[EINVAL]\nAn unknown socket option name was given.\n.TP 15\n[EINVAL]\nThe IP option field was improperly formed;\nan option field was shorter than the minimum value\nor longer than the option buffer provided.\n.SH SEE ALSO\ngetsockopt(2), send(2), recv(2), intro(4N), icmp(4P), inet(4F)\n"
  },
  {
    "path": "share/man/man4/lo.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)lo.4\t6.3 (Berkeley) 8/1/87\n.\\\"\n.TH LO 4 \"August 1, 1987\"\n.UC 2\n.SH NAME\nlo \\- software loopback network interface\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNLOOP\t\\fI1\\fP\t# loop-back pseudo-device\n.fi\n.ft R\n.SH DESCRIPTION\nThe\n.I loop\ninterface is a software loopback mechanism which may be\nused for performance analysis, software testing, and/or local\ncommunication.\nAs with other network interfaces, the loopback interface must have\nnetwork addresses assigned for each address family with which it is to be used.\nThese addresses\nmay be set or changed with the SIOCSIFADDR ioctl.\nThe loopback interface should be the last interface configured,\nas protocols may use the order of configuration as an indication of priority.\nThe loopback should \\fBnever\\fP be configured first unless no hardware\ninterfaces exist.\n.SH DIAGNOSTICS\n\\fBlo%d: can't handle af%d\\fP.  The interface was handed\na message with addresses formatted in an unsuitable address\nfamily; the packet was dropped.\n.SH SEE ALSO\nintro(4N), inet(4F), ns(4F)\n.SH BUGS\nPrevious versions of the system enabled the loopback interface\nautomatically, using a nonstandard Internet address (127.1).\nUse of that address is now discouraged; a reserved host address\nfor the local network should be used instead.\n"
  },
  {
    "path": "share/man/man4/lp.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)lp.4\t6.1 (Berkeley) 1/28/88\n.\\\"\n.TH LP 4 \"January 28, 1988\"\n.UC 2\n.SH NAME\nlp \\- line printer\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n.ta .5i +\\w'LP_MAXCOL  'u +\\w'lp_printers  'u\n\tNLP\t\\fIlp_printers\\fP\t# Line Printer\n\tLP_MAXCOL\t\\fI132\\fP\t# Maximum number of columns on line printers\n.DT\n\n/etc/dtab:\n.ta .5i +\\w'#Name 'u +\\w'Unit# 'u +\\w'177777 'u +\\w'Vector 'u +\\w'Br 'u +\\w'xxxxxxx 'u +\\w'xxxxxxx 'u\n\t#Name\tUnit#\tAddr\tVector\tBr\tHandler(s)\t\t# Comments\n\tlp\t?\t177514\t200\t4\tlpintr\t\t# lp-11 line printer\n.DT\n\nmajor device number(s):\n\traw: 5\nminor device encoding:\n\tbit 01 specifies 64-character set (instead of 96-character set)\n\tbits 06 are reserved\n\tbits 0370 specify line printer unit: <lp_unit> * 8\n.fi\n.ft R\n.SH DESCRIPTION\n.I Lp\nprovides the interface to any of the standard\nDEC line printers on an LP-11 parallel interface.\nWhen it is opened or closed, a suitable number\nof page ejects is generated.\nBytes written are printed.\n.PP\nThe unit number of the printer is specified by the minor device\nafter removing the low 3 bits, which act as per-device parameters.\nCurrently only the lowest of the low three bits is interpreted:\nif it is set, the device is treated as having a 64-character set,\nrather than a full 96-character set.\nIn the resulting half-ASCII mode, lower case letters are turned\ninto upper case and certain characters are escaped according to\nthe following table:\n.PP\n.br\n.ns\n.TP 10\n{\n\\o\"-(\"\n.br\n.ns\n.TP 10\n}\n\\o\"-)\"\n.br\n.ns\n.TP 10\n\\`\n\\o\"-\\'\"\n.br\n.ns\n.TP 10\n|\n\\o\"\\-!\"\n.br\n.ns\n.TP 10\n~\n\\o\"\\-^\"\n..\n.PP\nThe driver correctly interprets\ncarriage returns, backspaces, tabs, and form feeds.\nLines longer than the maximum page width are truncated.\nThe page width is specified via the LP_MAXCOL definition,\nset to 132 in the GENERIC distribution.\n.SH FILES\n.ta \\w'/dev/MAKEDEV.local  'u\n/dev/lp\n.br\n/dev/MAKEDEV\tscript to create special files\n.br\n/dev/MAKEDEV.local\tscript to localize special files\n.DT\n.SH \"SEE ALSO\"\nlpr(1),\ndtab(5),\nautoconfig(8)\n.SH DIAGNOSTICS\nNone.\n.SH BUGS\nAlthough the driver supports multiple printers this has never\nbeen tried.\n"
  },
  {
    "path": "share/man/man4/mem.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)mem.4\t6.2 (Berkeley) 1/28/88\n.\\\"\n.TH MEM 4 \"January 28, 1988\"\n.UC 2\n.SH NAME\nmem, kmem \\- main memory\n.SH SYNOPSIS\n.ft B\n.nf\nmajor device number(s):\n\traw: 1\nminor device encoding:\n\tmem: 0;  kmem: 1;  null: 2\n.fi\n.ft R\n.SH DESCRIPTION\n.I Mem\nis a special file that is an image of the main memory\nof the computer.\nIt may be used, for example, to examine\n(and even to patch) the system.\n.PP\nByte addresses in\n.I mem\nare interpreted as physical memory addresses.\nReferences to non-existent locations cause errors to be returned.\n.PP\nThe file\n.I kmem\nis the same as \n.I mem\nexcept that kernel virtual memory\nrather than physical memory is accessed.\nOnly kernel virtual addresses that are mapped to memory are allowed.\nExamining and patching device registers is likely\nto lead to unexpected results when read-only or write-only\nbits are present.\n.PP\nOn PDP-11s, the I/O page\nbegins at location 0160000 of\n.I kmem\nand the per-process data segment for the current process\nbegins at 0140000 and is USIZE clicks (64 bytes each) long.\n.SH FILES\n.ta \\w'/dev/MAKEDEV.local  'u\n/dev/mem\n.br\n/dev/kmem\n.br\n/dev/MAKEDEV\tscript to create special files\n.br\n/dev/MAKEDEV.local\tscript to localize special files\n.DT\n.SH BUGS\n.PP\nOn PDP-11's, specifying an odd kernel or user address, or an odd transfer\ncount is [generally] slower than using all even parameters.\n.PP\nOn machines with ENABLE/34(tm) memory mapping boards\nthe I/O page can be accessed only through \\fIkmem\\fP.\n"
  },
  {
    "path": "share/man/man4/mtio.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)mtio.4\t6.3 (2.11BSD) 1995/12/22\n.\\\"\n.TH MTIO 4 \"December 22, 1995\"\n.UC 2\n.SH NAME\nmtio \\- UNIX magtape interface\n.SH DESCRIPTION\nThe files\n.I \"mt0, ..., mt15\"\nrefer to the UNIX magtape drives,\nwhich may be on the MASSBUS using the TM03 formatter\n.IR ht (4),\nor on the UNIBUS using either the TM11 or TS11 formatters\n.IR tm (4)\nor\n.IR ts (4).\nThe following description applies to any of the transport/controller pairs.\n\nThe files\n.I \"mt0, ..., mt7\"\nare 800bpi (or the transport's lowest density), \n.I \"mt8, ..., mt15\"\nare 1600bpi (or the transport's second density), and\n.I \"mt16, ..., mt23\"\nare 6250bpi (or the transport's third density).\n(But note that only 1600 bpi is available with the TS11.)\nThe files\n.IR \"mt0, ..., mt3\" ,\n.IR \"mt8, ..., mt11\" ,\nand\n.I \"mt16, ..., mt19\"\nare rewound when closed; the others are not.\nWhen a file open for writing is closed, two end-of-files are written.\nIf the tape is not to be rewound\nit is positioned with the head between the two\ntapemarks.\n.PP\nA standard tape consists of a\nseries of 1024 byte records terminated by an\nend-of-file.\nTo the extent possible, the system makes\nit possible, if inefficient, to treat\nthe tape like any other file.\nSeeks have their usual meaning and it is possible\nto read or write a byte at a time.\nWriting in very small units is inadvisable,\nhowever, because it uses most of the tape in record\ngaps.\n.PP\nThe\n.I mt\nfiles discussed above are useful\nwhen it is desired to access the tape in a way\ncompatible with ordinary files.\nWhen foreign tapes are to be dealt with, and especially\nwhen long records are to be read or written, the\n`raw' interface is appropriate.\nThe associated files are named\n.I \"rmt0, ..., rmt23,\"\nbut the same minor-device considerations as for the regular files still apply.\nA number of other ioctl operations are available\non raw magnetic tape.\nThe following definitions are from\n.RI < sys/mtio.h >:\n.PP\n.nf\n/*\n * Structures and definitions for mag tape io control commands\n */\n\n/* structure for MTIOCTOP - mag tape op command */\nstruct\tmtop\t{\n\tshort\tmt_op;\t\t/* operations defined below */\n\tdaddr_t\tmt_count;\t/* how many of them */\n};\n\n/* operations */\n#define MTWEOF\t0\t/* write an end-of-file record */\n#define MTFSF\t1\t/* forward space file */\n#define MTBSF\t2\t/* backward space file */\n#define MTFSR\t3\t/* forward space record */\n#define MTBSR\t4\t/* backward space record */\n#define MTREW\t5\t/* rewind */\n#define MTOFFL\t6\t/* rewind and put the drive offline */\n#define MTNOP\t7\t/* no operation, sets status only */\n#define MTCACHE\t8\t/* enable controller cache */\n#define MTNOCACHE\t9\t/* disable controller cache */\n\n/* structure for MTIOCGET - mag tape get status command */\n\nstruct\tmtget\t{\n\tshort\tmt_type;\t/* type of magtape device */\n/* the following two registers are grossly device dependent */\n\tshort\tmt_dsreg;\t/* ``drive status'' register */\n\tshort\tmt_erreg;\t/* ``error'' register */\n/* end device-dependent registers */\n\tshort\tmt_resid;\t/* residual count */\n/* the following two are not yet implemented */\n\tdaddr_t\tmt_fileno;\t/* file number of current position */\n\tdaddr_t\tmt_blkno;\t/* block number of current position */\n/* end not yet implemented */\n};\n\n/*\n * Constants for mt_type byte.  These are the same\n * for other controllers compatible with the types listed.\n */\n#define\tMT_ISTS\t\t0x01\t\t/* TS-11 */\n#define\tMT_ISHT\t\t0x02\t\t/* TM03 Massbus: TE16, TU45, TU77 */\n#define\tMT_ISTM\t\t0x03\t\t/* TM11/TE10 Unibus */\n#define\tMT_ISMT\t\t0x04\t\t/* TM78/TU78 Massbus */\n#define\tMT_ISUT\t\t0x05\t\t/* SI TU-45 emulation on Unibus */\n#define\tMT_ISCPC\t0x06\t\t/* SUN */\n#define\tMT_ISAR\t\t0x07\t\t/* SUN */\n#define\tMT_ISTMSCP\t0x08\t\t/* DEC TMSCP protocol (TU81, TK50) */\n\n/* mag tape io control commands */\n#define\tMTIOCTOP\t_IOW(m, 1, struct mtop)\t\t/* do a mag tape op */\n#define\tMTIOCGET\t_IOR(m, 2, struct mtget)\t/* get tape status */\n#define MTIOCIEOT\t_IO(m, 3)\t\t\t/* ignore EOT error */\n#define MTIOCEEOT\t_IO(m, 4)\t\t\t/* enable EOT error */\n\n#ifndef KERNEL\n#define\tDEFTAPE\t\"/dev/rmt12\"\n#endif\n.fi\n.ft R\n.PP\nEach\n.I read\nor\n.I write\ncall reads or writes the next record on the tape.\nIn the write case the record has the same length as the\nbuffer given.\nDuring a read, the record size is passed\nback as the number of bytes read, provided it is no greater\nthan the buffer size;\nif the record is long, an error is indicated.\nIn raw tape I/O seeks are ignored.\nA zero byte count is returned when a tape mark is read,\nbut another read will fetch the first record of the\nnew tape file.\n.PP\nThe MTCACHE and MTNOCACHE commands do not apply to all tape drivers.  At\npresent only the TMSCP driver supports those commands and then only for\ndrives such as the TU81+.\n.SH FILES\n/dev/mt?\n.br\n/dev/rmt?\n.SH \"SEE ALSO\"\nmt(1),\ntar(1),\ntp(1),\nht(4),\ntm(4),\nts(4)\n.SH BUGS\nThe status should be returned in a device independent format.\n.PP\nThe special file naming should be redone in a more consistent and\nunderstandable manner.\n"
  },
  {
    "path": "share/man/man4/networking.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)intro.4n\t6.3 (Berkeley) 8/1/87\n.\\\"\n.TH INTRO 4N \"August 1, 1987\"\n.UC 5\n.SH NAME\nnetworking \\- introduction to networking facilities\n.SH SYNOPSIS\n.nf\n.ft B\n#include <sys/socket.h>\n#include <net/route.h>\n#include <net/if.h>\n.fi R\n.fi\n.SH DESCRIPTION\n.de _d\n.if t .ta .6i 2.1i 2.6i\n.\\\" 2.94 went to 2.6, 3.64 to 3.30\n.if n .ta .84i 2.6i 3.30i\n..\n.de _f\n.if t .ta .5i 1.25i 2.5i\n.\\\" 3.5i went to 3.8i\n.if n .ta .7i 1.75i 3.8i\n..\nThis section briefly describes the networking facilities\navailable in the system.\nDocumentation in this part of section\n4 is broken up into three areas:\n.I \"protocol families\n(domains),\n.IR protocols ,\nand\n.IR \"network interfaces\" .\nEntries describing a protocol family are marked ``4F,''\nwhile entries describing protocol use are marked ``4P.''\nHardware support for network interfaces are found\namong the standard ``4'' entries.\n.PP\nAll network protocols are associated with a specific\n.IR \"protocol family\" .\nA protocol family provides basic services to the protocol\nimplementation to allow it to function within a specific\nnetwork environment.  These services may include \npacket fragmentation and reassembly, routing, addressing, and \nbasic transport.  A protocol family may support multiple\nmethods of addressing, though the current protocol implementations\ndo not.  A protocol family is normally comprised of a number\nof protocols, one per\n.IR socket (2)\ntype.  It is not required that a protocol family support\nall socket types.  A protocol family may contain multiple\nprotocols supporting the same socket abstraction. \n.PP\nA protocol supports one of the socket abstractions detailed\nin\n.IR socket (2).\nA specific protocol may be accessed either by creating a\nsocket of the appropriate type and protocol family, or\nby requesting the protocol explicitly when creating a socket.\nProtocols normally accept only one type of address format,\nusually determined by the addressing structure inherent in\nthe design of the protocol family/network architecture.\nCertain semantics of the basic socket abstractions are\nprotocol specific.  All protocols are expected to support\nthe basic model for their particular socket type, but may,\nin addition, provide non-standard facilities or extensions\nto a mechanism.  For example, a protocol supporting the\nSOCK_STREAM\nabstraction may allow more than one byte of out-of-band\ndata to be transmitted per out-of-band message.\n.PP\nA network interface is similar to a device interface.\nNetwork interfaces comprise the lowest layer of the\nnetworking subsystem, interacting with the actual transport\nhardware.  An interface may support one or more protocol\nfamilies and/or address formats.\nThe SYNOPSIS section of each network interface\nentry gives a sample specification\nof the related drivers for use in providing\na system description to the\n.IR /sys/conf/config\nscript.\nThe DIAGNOSTICS section lists messages which may appear on the console\nand/or in the system error log,\n.I /usr/adm/messages\n(see\n.IR syslogd (8)),\ndue to errors in device operation.\n.SH PROTOCOLS\nThe system currently supports the DARPA Internet\nprotocols and the Xerox Network Systems(tm) protocols.\nRaw socket interfaces are provided to the IP protocol\nlayer of the DARPA Internet, to the IMP link layer (1822), and to\nthe IDP protocol of Xerox NS.\nConsult the appropriate manual pages in this section for more\ninformation regarding the support for each protocol family.\n.SH ADDRESSING\nAssociated with each protocol family is an address\nformat.  The following address formats are used by the system (and additional\nformats are defined for possible future implementation):\n.sp 1\n.nf\n._d\n#define\tAF_UNIX\t1\t/* local to host (pipes, portals) */\n#define\tAF_INET\t2\t/* internetwork: UDP, TCP, etc. */\n#define\tAF_IMPLINK\t3\t/* arpanet imp addresses */\n#define\tAF_PUP\t4\t/* pup protocols: e.g. BSP */\n#define\tAF_NS\t6\t/* Xerox NS protocols */\n#define\tAF_HYLINK\t15\t/* NSC Hyperchannel */\n.fi\n.SH ROUTING\nThe network facilities provided limited packet routing.\nA simple set of data structures comprise a ``routing table''\nused in selecting the appropriate network interface when\ntransmitting packets.  This table contains a single entry for\neach route to a specific network or host.  A user process,\nthe routing daemon, maintains this data base with the aid\nof two socket-specific \n.IR ioctl (2)\ncommands, SIOCADDRT and SIOCDELRT.  The commands allow\nthe addition and deletion of a single routing\ntable entry, respectively.  Routing table manipulations may\nonly be carried out by super-user.\n.PP\nA routing table entry has the following form, as defined\nin\n.RI < net/route.h >;\n.sp 1\n._f\n.nf\nstruct rtentry {\n\tu_long\trt_hash;\n\tstruct\tsockaddr rt_dst;\n\tstruct\tsockaddr rt_gateway;\n\tshort\trt_flags;\n\tshort\trt_refcnt;\n\tu_long\trt_use;\n\tstruct\tifnet *rt_ifp;\n};\n.sp 1\n.fi\nwith\n.I rt_flags\ndefined from,\n.sp 1\n.nf\n._d\n#define\tRTF_UP\t0x1\t\t/* route usable */\n#define\tRTF_GATEWAY\t0x2\t\t/* destination is a gateway */\n#define\tRTF_HOST\t0x4\t\t/* host entry (net otherwise) */\n#define\tRTF_DYNAMIC\t0x10\t\t/* created dynamically (by redirect) */\n.fi\n.PP\nRouting table entries come in three flavors: for a specific\nhost, for all hosts on a specific network, for any destination\nnot matched by entries of the first two types (a wildcard route). \nWhen the system is booted and addresses are assigned\nto the network interfaces, each protocol family\ninstalls a routing table entry for each interface when it is ready for traffic.\nNormally the protocol specifies the route\nthrough each interface as a ``direct'' connection to the destination host\nor network.  If the route is direct, the transport layer of\na protocol family usually requests the packet be sent to the\nsame host specified in the packet.  Otherwise, the interface\nis requested to address the packet to the gateway listed in the routing entry\n(i.e. the packet is forwarded).\n.PP\nRouting table entries installed by a user process may not specify\nthe hash, reference count, use, or interface fields; these are filled\nin by the routing routines.  If\na route is in use when it is deleted\n.RI ( rt_refcnt\nis non-zero),\nthe routing entry will be marked down and removed from the routing table,\nbut the resources associated with it will not\nbe reclaimed until all references to it are released. \nThe routing code returns EEXIST if\nrequested to duplicate an existing entry, ESRCH if\nrequested to delete a non-existent entry,\nor ENOBUFS if insufficient resources were available\nto install a new route.\nUser processes read the routing tables through the\n.I /dev/kmem \ndevice.\nThe\n.I rt_use\nfield contains the number of packets sent along the route.\n.PP\nWhen routing a packet,\nthe kernel will first attempt to find a route to the destination host.\nFailing that, a search is made for a route to the network of the destination.\nFinally, any route to a default (``wildcard'') gateway is chosen.\nIf multiple routes are present in the table,\nthe first route found will be used.\nIf no entry is found, the destination is declared to be unreachable.\n.PP\nA wildcard routing entry is specified with a zero\ndestination address value.  Wildcard routes are used\nonly when the system fails to find a route to the\ndestination host and network.  The combination of wildcard\nroutes and routing redirects can provide an economical\nmechanism for routing traffic.\n.SH INTERFACES\nEach network interface in a system corresponds to a\npath through which messages may be sent and received.  A network\ninterface usually has a hardware device associated with it, though\ncertain interfaces such as the loopback interface,\n.IR lo (4),\ndo not.\n.PP\nThe following \n.I ioctl\ncalls may be used to manipulate network interfaces.\nThe\n.I ioctl\nis made on a socket (typically of type SOCK_DGRAM)\nin the desired domain.\nUnless specified otherwise, the request takes an\n.I ifrequest\nstructure as its parameter.  This structure has the form\n.PP\n.nf\n.DT\nstruct\tifreq {\n#define\tIFNAMSIZ\t16\n\tchar\tifr_name[IFNAMSIZ];\t\t/* if name, e.g. \"en0\" */\n\tunion {\n\t\tstruct\tsockaddr ifru_addr;\n\t\tstruct\tsockaddr ifru_dstaddr;\n\t\tstruct\tsockaddr ifru_broadaddr;\n\t\tshort\tifru_flags;\n\t\tint\tifru_metric;\n\t\tcaddr_t\tifru_data;\n\t} ifr_ifru;\n#define\tifr_addr\tifr_ifru.ifru_addr\t/* address */\n#define\tifr_dstaddr\tifr_ifru.ifru_dstaddr\t/* other end of p-to-p link */\n#define\tifr_broadaddr\tifr_ifru.ifru_broadaddr\t/* broadcast address */\n#define\tifr_flags\tifr_ifru.ifru_flags\t/* flags */\n#define\tifr_metric\tifr_ifru.ifru_metric\t/* metric */\n#define\tifr_data\tifr_ifru.ifru_data\t/* for use by interface */\n};\n.fi\n.TP\nSIOCSIFADDR\nSet interface address for protocol family.  Following the address\nassignment, the ``initialization'' routine for\nthe interface is called.\n.TP\nSIOCGIFADDR\nGet interface address for protocol family.\n.TP\nSIOCSIFDSTADDR\nSet point to point address for protocol family and interface.\n.TP\nSIOCGIFDSTADDR\nGet point to point address for protocol family and interface.\n.TP\nSIOCSIFBRDADDR\nSet broadcast address for protocol family and interface.\n.TP\nSIOCGIFBRDADDR\nGet broadcast address for protocol family and interface.\n.TP\nSIOCSIFFLAGS\nSet interface flags field.  If the interface is marked down,\nany processes currently routing packets through the interface\nare notified;\nsome interfaces may be reset so that incoming packets are no longer received.\nWhen marked up again, the interface is reinitialized.\n.TP\nSIOCGIFFLAGS\nGet interface flags.\n.TP\nSIOCSIFMETRIC\nSet interface routing metric.\nThe metric is used only by user-level routers.\n.TP\nSIOCGIFMETRIC\nGet interface metric.\n.TP\nSIOCGIFCONF\nGet interface configuration list.  This request takes an\n.I ifconf\nstructure (see below) as a value-result parameter.  The \n.I ifc_len\nfield should be initially set to the size of the buffer\npointed to by \n.IR ifc_buf .\nOn return it will contain the length, in bytes, of the\nconfiguration list.\n.PP\n.nf\n.DT\n/*\n * Structure used in SIOCGIFCONF request.\n * Used to retrieve interface configuration\n * for machine (useful for programs which\n * must know all networks accessible).\n */\nstruct\tifconf {\n\tint\tifc_len;\t\t/* size of associated buffer */\n\tunion {\n\t\tcaddr_t\tifcu_buf;\n\t\tstruct\tifreq *ifcu_req;\n\t} ifc_ifcu;\n#define\tifc_buf\tifc_ifcu.ifcu_buf\t/* buffer address */\n#define\tifc_req\tifc_ifcu.ifcu_req\t/* array of structures returned */\n};\n.fi\n.SH SEE ALSO\nsocket(2),\nioctl(2),\nintro(4),\nconfig(8),\nrouted(8C)\n"
  },
  {
    "path": "share/man/man4/ns.4",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ns.4f\t1.4 (2.11BSD) 1996/1/27\n.\\\"\n.TH NS 4F \"January 27, 1996\"\n.UC 2\n.SH NAME\nns \\- Xerox Network Systems(tm) protocol family\n.SH SYNOPSIS\n.ft B\n.nf\nNot currently supported under 2.11BSD\n.fi\n.ft R\n.SH DESCRIPTION\n.IX  \"ns device\"  \"\"  \"\\fLns\\fP \\(em Xerox NS protocol family\"\nThe NS protocol family is a collection of protocols\nlayered atop the\n.I Internet Datagram Protocol\n(IDP) transport layer, and using the Xerox NS address formats.\nThe NS family provides protocol support for the\nSOCK_STREAM, SOCK_DGRAM, SOCK_SEQPACKET, and SOCK_RAW socket types; the\nSOCK_RAW interface is a debugging tool, allowing you to trace all packets\nentering, (or with toggling kernel variable, additionally leaving) the local\nhost.\n.SH ADDRESSING\nNS addresses are 12 byte quantities, consisting of a \n4 byte Network number, a 6 byte Host number and a 2 byte port number,\nall stored in network standard format.\n(on the VAX these are word and byte reversed; on the Sun they are not\nreversed).  The include file\n.RI < netns/ns.h >\ndefines the NS address as a structure containing unions (for quicker\ncomparisons).\n.PP\nSockets in the Internet protocol family use the following\naddressing structure:\n.nf\n\nstruct sockaddr_ns {\n\tshort\t\tsns_family;\n\tstruct ns_addr\tsns_addr;\n\tchar\t\tsns_zero[2];\n};\n\nwhere an ns_addr is composed as follows:\n\nunion ns_host {\n\tu_char\t\tc_host[6];\n\tu_short\t\ts_host[3];\n};\n\nunion ns_net {\n\tu_char\t\tc_net[4];\n\tu_short\t\ts_net[2];\n};\n\nstruct ns_addr {\n\tunion ns_net\tx_net;\n\tunion ns_host\tx_host;\n\tu_short\tx_port;\n};\n\n.fi\nSockets may be created with an address of all zeroes to effect\n``wildcard'' matching on incoming messages.\nThe local port address specified in a\n.IR bind (2)\ncall is restricted to be greater than NSPORT_RESERVED\n(=3000, in <netns/ns.h>) unless the creating process is running\nas the super-user, providing a space of protected port numbers.\n.SH PROTOCOLS\nThe NS protocol family supported by the operating system\nis comprised of\nthe Internet Datagram Protocol (IDP)\n.IR idp (4P),\nError Protocol (available through IDP),\nand\nSequenced Packet Protocol (SPP)\n.IR spp (4P).\n.LP\nSPP is used to support the SOCK_STREAM and SOCK_SEQPACKET abstraction,\nwhile IDP is used to support the SOCK_DGRAM abstraction.\nThe Error protocol is responded to by the kernel\nto handle and report errors in protocol processing;\nit is, however,\nonly accessible to user programs through heroic actions.\n.SH SEE ALSO\nintro(3), byteorder(3N), gethostbyname(3N), getnetent(3N),\ngetprotoent(3N), getservent(3N), ns(3N),\nintro(4N), spp(4P), idp(4P), nsip(4)\n.br\nInternet Transport Protocols, Xerox Corporation document XSIS-028112\n.br\nAn Advanced 4.3BSD Interprocess Communication Tutorial\n"
  },
  {
    "path": "share/man/man4/nsip.4",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)nsip.4\t1.2 (2.11BSD) 1996/1/27\n.\\\"\n.TH NSIP 4 \"January 27, 1996\"\n.UC 2\n.SH NAME\nnsip \\- software network interface encapsulating ns packets in ip packets.\n.SH SYNOPSIS\n.ft B\n.nf\n#include <netns/ns_if.h>\n\nNot currently supported under 2.11BSD\n.fi\n.ft R\n.SH DESCRIPTION\nThe\n.I nsip\ninterface is a software mechanism which may be\nused to transmit Xerox NS(tm) packets through otherwise uncooperative\nnetworks.\nIt functions by prepending an IP header, and resubmitting the packet\nthrough the unix IP machinery.\n.LP\nThe super-user can advise the operating system of a willing partner\nby naming an IP address to be associated with an NS address.\nPresently, only specific hosts pairs are allowed, and for each host\npair, an artificial point-to-point interface is constructed.\nAt some future date, IP broadcast addresses or hosts may be paired\nwith NS networks or hosts.\n.LP\nSpecifically, a socket option of SO_NSIP_ROUTE is set on a socket\nof family AF_NS, type SOCK_DGRAM, passing the following structure:\n.nf\n\nstruct nsip_req {\n\tstruct sockaddr rq_ns;\t/* must be ns format destination */\n\tstruct sockaddr rq_ip;\t/* must be ip format gateway */\n\tshort rq_flags;\n};\n\n.SH DIAGNOSTICS\n\\fBnsip%d: can't handle af%d\\fP.  The interface was handed\na message with addresses formatted in an unsuitable address\nfamily; the packet was dropped.\n.SH SEE ALSO\nintro(4N), ns(4F)\n.SH BUGS\nIt is absurd to have a separate pseudo-device for each pt-to-pt\nlink.\nThere is no way to change the IP address for an NS host once the\nthe encapsulation interface is set up.\nThe request should honor flags of RTF_GATEWAY to indicate\nremote networks, and the absence of RTF_UP should be a clue\nto remove that partner.\nThis was intended to postpone the necessity of rewriting reverse ARP\nfor the \n.B en\ndevice, and to allow passing XNS packets through an\nArpanet-Milnet gateway, to facilitate testing between some co-operating\nuniversities.\n"
  },
  {
    "path": "share/man/man4/null.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)null.4\t6.1 (Berkeley) 1/28/88\n.\\\"\n.TH NULL 4 \"January 28, 1988\"\n.UC 2\n.SH NAME\nnull \\- data sink\n.SH SYNOPSIS\n.ft B\n.nf\nmajor device number(s):\n\traw: 1\nminor device encoding:\n\tmem: 0;  kmem: 1;  null: 2\n.fi\n.ft R\n.SH DESCRIPTION\nData written on a null special file is discarded.\n.PP\nReads from a null special file always return 0 bytes.\n.SH FILES\n.ta \\w'/dev/MAKEDEV.local  'u\n/dev/null\n.br\n/dev/MAKEDEV\tscript to create special files\n.br\n/dev/MAKEDEV.local\tscript to localize special files\n.DT\n.SH \"SEE ALSO\"\nmem(4)\n"
  },
  {
    "path": "share/man/man4/pty.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)pty.4\t6.2 (Berkeley) 5/19/86\n.\\\"\n.TH PTY 4 \"May 19, 1986\"\n.UC 5\n.SH NAME\npty \\- pseudo terminal driver\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNPTY\t\\fIptys\\fP\t# pseudo-terminals, in groups of 8\n.fi\n.ft R\n.SH DESCRIPTION\nThe\n.I pty\ndriver provides support for a device-pair termed a\n.IR \"pseudo terminal\" .\nA pseudo terminal is a pair of character devices, a\n.I master\ndevice and a\n.I slave\ndevice.  The slave device provides processes\nan interface identical\nto that described in\n.IR tty (4).\nHowever, whereas all other devices which provide the \ninterface described in\n.IR tty (4)\nhave a hardware device of some sort behind them, the slave\ndevice has, instead, another process manipulating\nit through the master half of the pseudo terminal.\nThat is, anything written on the master device is\ngiven to the slave device as input and anything written\non the slave device is presented as input on the master\ndevice.\n.PP\nIn configuring,\n.I ptys\nspecifies the number of pseudo terminal pairs are configured.\n.PP\nThe following \n.I ioctl\ncalls apply only to pseudo terminals:\n.TP\nTIOCSTOP\nStops output to a terminal (e.g. like typing ^S).  Takes\nno parameter.\n.TP\nTIOCSTART\nRestarts output (stopped by TIOCSTOP or by typing ^S).\nTakes no parameter.\n.TP\nTIOCPKT\nEnable/disable \n.I packet\nmode.  Packet mode is enabled by specifying (by reference)\na nonzero parameter and disabled by specifying (by reference)\na zero parameter.  When applied to the master side of a pseudo\nterminal, each subsequent \n.I read \nfrom the terminal will return data written on the slave part of\nthe pseudo terminal preceded by a zero byte (symbolically\ndefined as TIOCPKT_DATA), or a single byte reflecting control\nstatus information.  In the latter case, the byte is an inclusive-or\nof zero or more of the bits:\n.RS\n.TP\nTIOCPKT_FLUSHREAD\nwhenever the read queue for the terminal is flushed.\n.TP\nTIOCPKT_FLUSHWRITE\nwhenever the write queue for the terminal is flushed.\n.TP\nTIOCPKT_STOP\nwhenever output to the terminal is stopped a la ^S.\n.TP\nTIOCPKT_START\nwhenever output to the terminal is restarted.\n.TP\nTIOCPKT_DOSTOP\nwhenever \n.I t_stopc\nis ^S\nand \n.I t_startc\nis ^Q.\n.TP\nTIOCPKT_NOSTOP\nwhenever the start and stop characters are not ^S/^Q.\n.RE\n.IP\nWhile this mode is in use, the presence of control status information\nto be read from the master side may be detected by a\n.I select\nfor exceptional conditions.\n.IP\nThis mode is used by\n.IR rlogin (1C)\nand\n.IR rlogind (8C)\nto implement a remote-echoed, locally ^S/^Q flow-controlled\nremote login with proper back-flushing of output; it can be\nused by other similar programs.\n.TP\nTIOCUCNTL\nEnable/disable a mode that allows a small number of simple user\n.I ioctl\ncommands to be passed through the pseudo-terminal,\nusing a protocol similar to that of TIOCPKT.\nThe TIOCUCNTL and TIOCPKT modes are mutually exclusive.\nThis mode is enabled from the master side of a pseudo terminal\nby specifying (by reference)\na nonzero parameter and disabled by specifying (by reference)\na zero parameter.\nEach subsequent \n.I read \nfrom the master side will return data written on the slave part of\nthe pseudo terminal preceded by a zero byte,\nor a single byte reflecting a user control operation on the slave side.\nA user control command consists of a special\n.I ioctl\noperation with no data; the command is given as UIOCCMD(\\fIn\\fP),\nwhere \\fIn\\fP is a number in the range 1-255.\nThe operation value \\fIn\\fP will be received as a single byte on the next\n.I read\nfrom the master side.\nThe \\fIioctl\\fP UIOCCMD(0) is a no-op that may be used to probe for\nthe existence of this facility.\nAs with TIOCPKT mode, command operations may be detected with a\n.I select\nfor exceptional conditions.\n.TP\nTIOCREMOTE\nA mode for the master half of a pseudo terminal, independent\nof TIOCPKT.  This mode causes input to the pseudo terminal\nto be flow controlled and not input edited (regardless of the\nterminal mode).  Each write to the control terminal produces\na record boundary for the process reading the terminal.  In\nnormal usage, a write of data is like the data typed as a line\non the terminal; a write of 0 bytes is like typing an end-of-file\ncharacter.  TIOCREMOTE can be used when doing remote line\nediting in a window manager, or whenever flow controlled input\nis required.\n.SH FILES\n.DT\n/dev/pty[p-r][0-9a-f]\tmaster pseudo terminals\n.br\n/dev/tty[p-r][0-9a-f]\tslave pseudo terminals\n.SH DIAGNOSTICS\nNone.\n"
  },
  {
    "path": "share/man/man4/qe.4",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)qe.4\t6.1 (Berkeley) 8/20/87\n.\\\"\n.TH QE 4 \"August 20, 1987\"\n.UC 2\n.SH NAME\nqe \\- DEC DEQNA Q-bus 10 Mb/s Ethernet interface\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNQE\t\\fIqe_controllers\\fP\t# DEQNA\n.fi\n.ft R\n.SH DESCRIPTION\nThe\n.B qe\ninterface provides access to a 10 Mb/s Ethernet network through\nthe DEC DEQNA Q-bus controller.\n.PP\nEach of the host's network addresses\nis specified at boot time with an SIOCSIFADDR\nioctl.  The\n.B qe\ninterface employs the address resolution protocol described in\narp(4P)\nto map dynamically  between Internet and Ethernet addresses on the local\nnetwork.\n.PP\nThe interface normally tries to use a ``trailer'' encapsulation\nto minimize copying data on input and output.\nThe use of trailers is negotiated with ARP.\nThis negotiation may be disabled, on a per-interface basis,\nby setting the IFF_NOTRAILERS\nflag with an SIOCSIFFLAGS ioctl.\n.SH DIAGNOSTICS\n.SH SEE ALSO\ninet(4F), intro(4N), arp(4P)\n"
  },
  {
    "path": "share/man/man4/ra.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ra.4\t6.2.1 (2.11BSD) 1995/06/17\n.\\\"\n.TH RA 4 \"September 6, 1987\"\n.UC 2\n.SH NAME\nra \\- MSCP disk controller interface\n.SH SYNOPSIS\n.ft B\n.nf\n.ta .5i +\\w'NRAC 'u +\\w'ra_controllers 'u\n/sys/conf/SYSTEM:\n\tNRAC\t\\fIra_controllers\\fP\t# NRAD controllers\n\tNRAD\t\\fIra_drives\\fP\t# RX33/50, RC25, RD51/52/53/54, RA60/80/81/82\n.DT\n\n/etc/dtab:\n.ta .5i +\\w'#Name 'u +\\w'Unit# 'u +\\w'177777 'u +\\w'Vector 'u +\\w'Br 'u +\\w'xxxxxxx 'u +\\w'xxxxxxx 'u\n\t#Name\tUnit#\tAddr\tVector\tBr\tHandler(s)\t\t# Comments\n\tra\t?\t172150\t154\t5\traintr\t\t# uda50, rqdx1/2/3\n.DT\n\nmajor device number(s):\n\traw: 14\n\tblock: 5\nminor device encoding:\n\tbits 0007 specify partition of RA drive\n\tbits 0070 specify RA drive\n\tbits 0300 specify RA controller\n.fi\n.ft R\n.SH DESCRIPTION\nThis is a driver for the DEC UDA-50 disk controller\nand for other compatible controllers.\nThe UDA-50 communicates with the host through a packet\noriented protocol termed the Mass Storage Control Protocol (MSCP).\nConsult the file\n.RI < pdp/mscp.h >\nfor a detailed description of this protocol.\n.PP\nFiles with minor device numbers 0 through 7 refer to various portions\nof drive 0;\nminor devices 8 through 15 refer to drive 1, etc.\nThe standard device names begin with ``ra'' followed by\nthe drive number and then a letter a-h for partitions 0-7 respectively.\nThe character ? stands here for a drive number in the range 0-7.\n.PP\nThe block files access the disk via the system's normal\nbuffering mechanism and may be read and written without regard to\nphysical disk records.  There is also a `raw' interface\nwhich provides for direct transmission between the disk\nand the user's read or write buffer.\nA single read or write call results in exactly one I/O operation\nand therefore raw I/O is considerably more efficient when\nmany words are transmitted.  The names of the raw files\nconventionally begin with an extra `r.'\n.PP\nIn raw I/O the buffer must begin on a word (even) boundary,\nand counts should be a multiple of 512 bytes (a disk sector).\nLikewise\n.I seek\ncalls should specify a multiple of 512 bytes.\n.SH \"DISK SUPPORT\"\nThis driver configures the drive type of each drive\nwhen it is first opened.  Partition information is read from the disklabel.\nIf there is no label or the label is corrupt then the 'a' partition is\nused to span the entire drive.\n.PP\nThe ra?a partition is normally used for the root file system,\nthe ra?b partition as a swap area,\nand the ra?c partition for pack-pack copying (it maps the entire disk).\n.SH FILES\n.ta \\w'/dev/MAKEDEV.local  'u\n/dev/ra[0-7][a-h]\n.br\n/dev/rra[0-7][a-h]\n.br\n/dev/MAKEDEV\tscript to create special files\n.br\n.SH SEE ALSO\nhk(4),\nram(4),\nrk(4),\nrl(4),\nrp(4),\nrx(4),\nsi(4),\nxp(4),\ndtab(5),\nautoconfig(8),\ndisklabel(8)\n.SH DIAGNOSTICS\n.BR \"rasa %o, state %d\" .\n(Additional status information given after a hard i/o error.)\nThe values of the UDA-50 status register and the internal\ndriver state are printed.\n.PP\n.BR \"ra%d: interrupt in unknown state %d ignored\" .\nAn interrupt was received when the driver was in an unknown\ninternal state.  Indicates a hardware problem or a driver bug.\n.PP\n.BR \"ra%d: fatal error (%o)\" .\nThe UDA-50 indicated a ``fatal error'' in the status returned\nto the host.  The contents of the status register are displayed.\n.PP\n.BR \"ra%d,%d: OFFLINE\" .\n(Additional status information given after a hard i/o error.)\nA hard i/o error occurred because the drive was not on-line.\nThe attached unit number and the MSCP unit numbers are printed.\n.PP\n.BR \"status %o\" .\n(Additional status information given after a hard i/o error.)\nThe status information returned from the UDA-50 is tacked onto\nthe end of the hard error message printed on the console.\n.PP\n.BR \"ra: unknown packet opcode=0%o\" .\nAn MSCP packet of unknown type was received from the UDA-50.\nCheck the cabling to the controller.\n.PP\nThe following errors are interpretations of MSCP error messages\nreturned by the UDA-50 to the host.\n.PP\n.BR \"ra: %s error, controller error, event 0%o\" .\n.PP\n.BR \"ra: %s error, host memory access error, event 0%o, addr 0%o\" .\n.PP\n.BR \"ra: %s error, disk transfer error, unit %d, grp 0x%x, hdr 0x%x\" .\n.PP\n.BR \"ra: %s error, SDI error, unit %d, event 0%o, hdr 0x%x\" .\n.PP\n.BR \"ra: %s error, small disk error, unit %d, event 0%o, cyl %d\" .\n.PP\n.BR \"ra: %s error, unknown error, unit %d, format 0%o, event 0%o\" .\n.SH BUGS\nIn raw I/O\n.I read\nand\n.IR write (2)\ntruncate file offsets to 512-byte block boundaries,\nand\n.I write\nscribbles on the tail of incomplete blocks.\nThus,\nin programs that are likely to access raw devices,\n.I read, write\nand\n.IR lseek (2)\nshould always deal in 512-byte multiples.\n"
  },
  {
    "path": "share/man/man4/ram.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ram.4\t1.2 (2.11BSD) 1996/1/27\n.\\\"\n.TH RAM 4 \"Januray 27, 1996\"\n.UC 2\n.SH NAME\nram \\- ram disk driver\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNRAM\t\\fIram_size\\fP\t# RAM disk size (512-byte blocks)\n\nmajor device number(s):\n\tblock: 3\nminor device encoding:\n\tmust be zero (0)\n.fi\n.ft R\n.SH DESCRIPTION\nThe\n.I ram\npseudo-device provides a very fast extended memory store.  It's use is\nintended for file systems like\n.I /tmp\nand applications which need to access a reasonably large amount of data\nquickly.\n.PP\nThe amount of memory dedicated to the ram device is controlled by the NRAM\ndefinition in units of 512-byte blocks.  This is also patchable in the\nsystem binary through the variable\n.IR ram_size\n(though a patched system would have to be rebooted before any change took\neffect; see\n.IR adb (1)).\nThis makes it easy to test the effects of different ram disk sizes on\nsystem performance.  It's important to note that any space given to the ram\ndevice is permanently allocated at system boot time.  Dedicating too much\nmemory can adversely affect system performance by forcing the system to\nswap heavily as in a memory poor environment.\n.PP\nThe block file accesses the ram disk via the system's buffering mechanism\nthrough a buffer sharing arrangement with the buffer cache.  It may be read\nand written without regard to physical disk records.  There is no `raw'\ninterface since no speed advantage is gained by such an interface with\nthe ram disk.\n.SH \"DISK SUPPORT\"\nThe\n.I ram\ndriver does not support pseudo-disks (partitions).  The special files\nrefer to the entire `drive' as a single sequentially addressed file.\n.PP\nA typical use for the ram disk would be to mount\n.I /tmp\non it.  Note that if this arrangement is recorded in\n.I /etc/fstab\nthen\n.I /etc/rc\nwill have to be modified slightly to do a\n.IR mkfs (8)\non the ram disk\n.B before\nthe standard file system checks are done.\n.SH FILES\n.ta \\w'/dev/MAKEDEV.local  'u\n/dev/ram\tblock file\n.br\n/dev/MAKEDEV\tscript to create special files\n.br\n/dev/MAKEDEV.local\tscript to localize special files\n.DT\n.SH \"SEE ALSO\"\nhk(4),\nra(4),\nrl(4),\nrk(4),\nrp(4),\nrx(4),\nsi(4),\nxp(4)\ndtab(5),\nautoconfig(8)\n.SH DIAGNOSTICS\n\\fBram: no space\\fR.  There is not enough memory to allocate the space needed\nby the ram disk.  The ram disk is disabled.  Any attempts to access\nit will return an error.\n.PP\n\\fBram: not allocated\\fR.  No memory was allocated to the ram disk and an\nattempt was made to open it.  Either not enough memory was available at\nboot time or the kernel variable\n.I ram_size\nwas set to zero.\n.SH BUGS\nThe\n.I ram\ndriver is only available under 2.11BSD.\n"
  },
  {
    "path": "share/man/man4/rk.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)rk.4\t6.2 (Berkeley) 8/20/87\n.\\\"\n.TH RK 4 \"August 20, 1987\"\n.UC 2\n.SH NAME\nrk \\- RK-11/RK05 disk\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNRK\t\\fIrk_drives\\fP\t# RK05\n\n/etc/dtab:\n.ta .5i +\\w'#Name 'u +\\w'Unit# 'u +\\w'177777 'u +\\w'Vector 'u +\\w'Br 'u +\\w'xxxxxxx 'u +\\w'xxxxxxx 'u\n\t#Name\tUnit#\tAddr\tVector\tBr\tHandler(s)\t\t# Comments\n\trk\t?\t177400\t220\t5\trkintr\t\t# rk05\n.DT\n\nmajor device number(s):\n\traw: 15\n\tblock: 6\nminor device encoding:\n\tspecifies drive: <rk_drive>\n.fi\n.ft R\n.SH DESCRIPTION\nMinor device numbers are drive numbers on one controller.\nThe standard device names begin with ``rk'' followed by\nthe drive number and then the letter \"h\".\nThe character ? stands here for a drive number in the range 0-7.\n.PP\nThe block files access the disk via the system's normal\nbuffering mechanism and may be read and written without regard to\nphysical disk records.  There is also a `raw' interface\nwhich provides for direct transmission between the disk\nand the user's read or write buffer.\nA single read or write call results in exactly one I/O operation\nand therefore raw I/O is considerably more efficient when\nmany words are transmitted.  The names of the raw files\nconventionally begin with an extra `r.'\n.PP\nIn raw I/O the buffer must begin on a word (even) boundary,\nand counts should be a multiple of 512 bytes (a disk sector).\nLikewise\n.I seek\ncalls should specify a multiple of 512 bytes.\n.SH \"DISK SUPPORT\"\nThe\n.I rk\ndriver does not support pseudo-disks (partitions).  Each file\n.I rk?h\nrefers to the entire drive as a single sequentially addressed\nfile.  Each drive has 4872 512-byte blocks.\n.PP\nIt's not clear what one would do with one of these drives if one had one ...\n.SH FILES\n.ta \\w'/dev/MAKEDEV.local  'u\n/dev/rk[0-7]h\tblock files\n.br\n/dev/rrk[0-7]h\traw files\n.br\n/dev/MAKEDEV\tscript to create special files\n.br\n/dev/MAKEDEV.local\tscript to localize special files\n.DT\n.SH \"SEE ALSO\"\nhk(4),\nra(4),\nram(4),\nrl(4),\nrp(4),\nrx(4),\nsi(4),\nxp(4),\ndtab(5),\nautoconfig(8)\n.SH DIAGNOSTICS\n\\fBrk%d: hard error sn%d er=%b ds=%b\\fR.  An unrecoverable\nerror occurred during transfer of the specified sector of the specified\ndisk.  The contents of the two error registers are also printed\nin octal and symbolically with bits decoded.\nThe error was either unrecoverable, or a large number of retry attempts\ncould not recover the error.\n.PP\n\\fBrk%d: write locked\\fR.  The write protect switch was set on the drive\nwhen a write was attempted.  The write operation is not recoverable.\n.SH BUGS\nIn raw I/O\n.I read\nand\n.IR write (2)\ntruncate file offsets to 512-byte block boundaries,\nand\n.I write\nscribbles on the tail of incomplete blocks.\nThus,\nin programs that are likely to access raw devices,\n.I read, write\nand\n.IR lseek (2)\nshould always deal in 512-byte multiples.\n.PP\nDEC-standard error logging should be supported.\n.PP\nA program to analyze the logged error information (even in its\npresent reduced form) is needed.\n"
  },
  {
    "path": "share/man/man4/rl.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)rl.4\t6.2.1 (2.11BSD) 1995/06/17\n.\\\"\n.TH RL 4 \"August 20, 1987\"\n.UC 2\n.SH NAME\nrl \\- RL-11/RL01, RL02 moving-head disk\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNRL\t\\fIrl_drives\\fP\t# RL01/02\n\n/etc/dtab:\n.ta .5i +\\w'#Name 'u +\\w'Unit# 'u +\\w'177777 'u +\\w'Vector 'u +\\w'Br 'u +\\w'xxxxxxx 'u +\\w'xxxxxxx 'u\n\t#Name\tUnit#\tAddr\tVector\tBr\tHandler(s)\t\t# Comments\n\trl\t?\t174400\t160\t5\trlintr\t\t# rl-01/02\n.DT\n\nmajor device number(s):\n\traw: 16\n\tblock: 7\nminor device encoding:\n\tbits 0007 specify partition of RL drive\n\tbits 0070 specify RL drive\n.fi\n.ft R\n.SH DESCRIPTION\nThe block files access the disk via the system's normal\nbuffering mechanism and may be read and written without regard to\nphysical disk records.  There is also a `raw' interface\nwhich provides for direct transmission between the disk\nand the user's read or write buffer.\nA single read or write call results in exactly one I/O operation\nand therefore raw I/O is considerably more efficient when\nmany words are transmitted.  The names of the raw files\nconventionally begin with an extra `r.'\n.PP\nIn raw I/O the buffer must begin on a word (even) boundary,\nand counts should be a multiple of 512 bytes (a disk sector).\nLikewise\n.I seek\ncalls should specify a multiple of 512 bytes.\n.SH \"DISK SUPPORT\"\nThe RL01 drives are each 10240 blocks long\nand the RL02 drives are 20480 blocks long.\n.PP\nOn a RL02 there is room for a full sized root ('a') partition and a\nreasonable sized swap ('b') partition.  The RL01 can only (realistically)\nhave a single 5mb partition.\n.SH FILES\n.ta \\w'/dev/MAKEDEV.local  'u\n/dev/rl[0-3][a-h]\tblock files\n.br\n/dev/rrl[0-3][a-h]\traw files\n.br\n/dev/MAKEDEV\tscript to create special files\n.br\n/dev/MAKEDEV.local\tscript to localize special files\n.DT\n.SH \"SEE ALSO\"\nhk(4),\nra(4),\nram(4),\nrk(4),\nrp(4),\nrx(4),\nsi(4),\nxp(4),\ndtab(5),\nautoconfig(8)\n.SH DIAGNOSTICS\n\\fBrl%d: hard error sn%d cs=%b da=%b\\fR.  An unrecoverable\nerror occurred during transfer of the specified sector of the specified\ndisk.  The contents of the two error registers are also printed\nin octal and symbolically with bits decoded.\nThe error was either unrecoverable, or a large number of retry attempts\ncould not recover the error.\n.PP\n\\fBrl%d: hard error sn%d mp=%b da=%b\\fR.  An unrecoverable drive\nerror occured during transfer of the specified sector of the specified\ndisk.  The contents of the two error registers are also printed\nin octal and symbolically with bits decoded.\nThe error was either unrecoverable, or a large number of retry attempts\ncould not recover the error.\n.PP\n\\fBrl%d: write locked\\fR.  The write protect switch was set on the drive\nwhen a write was attempted.  The write operation is not recoverable.\n.PP\n\\fBrl%d: can't get status\\fR.  A ``get status'' command on the specified\ndrive failed.  The error is unrecoverable.\n.SH BUGS\nIn raw I/O\n.I read\nand\n.IR write (2)\ntruncate file offsets to 512-byte block boundaries,\nand\n.I write\nscribbles on the tail of incomplete blocks.\nThus,\nin programs that are likely to access raw devices,\n.I read, write\nand\n.IR lseek (2)\nshould always deal in 512-byte multiples.\n.PP\nDEC-standard error logging should be supported.\n.PP\nA program to analyze the logged error information (even in its\npresent reduced form) is needed.\n"
  },
  {
    "path": "share/man/man4/rx.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)rx.4\t6.2.1 (2.11BSD) 1996/1/27\n.\\\"\n.TH RX 4 \"January 27, 1996\"\n.UC 2\n.SH NAME\nrx \\- DEC RX02 floppy disk\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNRX\t\\fIrx_units\\fP\t# RX02\n\n/etc/dtab:\n.ta .5i +\\w'#Name 'u +\\w'Unit# 'u +\\w'177777 'u +\\w'Vector 'u +\\w'Br 'u +\\w'xxxxxxx 'u +\\w'xxxxxxx 'u\n\t#Name\tUnit#\tAddr\tVector\tBr\tHandler(s)\t\t# Comments\n\trx\t?\t177170\t264\t5\trxintr\t\t# rx02\n.DT\n\nmajor device number(s):\n\traw: 17\n\tblock: 8\nminor device encoding:\n\tbit 01 specifies drive: <rx_drive>\n\tbit 02 specifies density: single: 0, double: 1\n.fi\n.ft R\n.SH DESCRIPTION\nThe\n.I rx\ndevice provides access to a DEC RX02 floppy disk\nunit with M8256 interface module (RX211 configuration). \nThe RX02 uses 8-inch, single-sided, soft-sectored floppy\ndisks (with pre-formatted industry-standard headers) in\neither single or double density.\n.PP\nFloppy disks handled by the RX02 contain 77 tracks, each with 26\nsectors (for a total of 2,002 sectors).  The sector size is 128\nbytes for single density, 256 bytes for double density.  Single \ndensity disks are compatible with the RX01 floppy disk unit and with\nIBM 3740 Series Diskette 1 systems.  \n.PP\nFiles with minor device numbers 0 and 1 refer to drives 0 and 1\nin single density mode;\nminor devices 2 and 3 refer to drives 0 and 1\nin double density mode.\nThe standard device names begin with ``rx'' followed by\nthe drive number and then a letter a-b for single and double density\naccess to the drive respectively.\nThe character ? stands here for a drive number in the range 0-1.\n.PP\nThe block files access the disk via the system's normal\nbuffering mechanism and may be read and written without regard to\nphysical disk records.  There is also a `raw' interface\nwhich provides for direct transmission between the disk\nand the user's read or write buffer.\nA single read or write call results in exactly one I/O operation\nand therefore raw I/O is considerably more efficient when\nmany words are transmitted.  The names of the raw files\nconventionally begin with an extra `r.'\n.PP\nIn raw I/O the buffer must begin on a word (even) boundary,\nand counts should be a multiple of the disk's sector size\n(either 128 or 256 bytes depending on selected density.)\nLikewise\n.I seek\ncalls should specify a multiple of the disk's sector size.\n.PP\nIn addition to normal (`block' and `raw') i/o, the driver supports\nformatting of disks for either density.\n.SH \"DISK SUPPORT\"\nThe\n.I rx\ndriver does not support pseudo-disks (partitions).  Each file\n.I rx?[ab]\nrefers to the entire drive as a single sequentially addressed\nfile.  The physical disk sector size is 128 bytes for single\ndensity and 256 bytes for double density.  The logical block\nsize is 1024 bytes.  Each diskette has 250 logical blocks in\nsingle density and 500 logical blocks in double density.\n.PP\nThe size and density of the disks are specified as follows:\n.PP\n.nf\n.ta .5i +\\w'rx00  'u +\\w'minor device  'u +\\w'unit  'u\n\tdisk\tminor device\tunit\tdensity\n\trx0a\t0\t0\tsingle\n\trx1a\t1\t1\tsingle\n\trx0b\t2\t0\tdouble\n\trx1b\t3\t1\tdouble\n.DT\n.fi\n.PP\nEven though the storage capacity on a floppy disk is quite\nsmall, it is possible to make file systems on them.\nFor example, the commands\n.nf\n.RS\n% rxformat /dev/rrx0a\n% newfs /dev/rrx0a\n.RE\nand\n.RS\n% rxformat /dev/rrx1b\n% newfs /dev/rrx1b\n.RE\n.fi\nformat and make file systems on the single density disk in the left drive\nand the double density disk in the right drive with\n241 and 486 kbytes available, respectively, for file storage.\nUsing\n.IR tar (1)\ngives somewhat more efficient utilization of the available\nspace for file storage.\nThe RX02 disks are primarily useful for small archives and transfer of\nsmall systems or distributions.\n.PP\nAn\n.IR ioctl (2)\ncall is available is available to format RX02 disks:\n.RS\n.nf\n.ft B\n#include <pdpuba/rxreg.h>\nioctl(fildes, RXIOC_FORMAT)\n.ft R\n.fi\n.RE\nThe density is determined by the device opened.\n.SH FILES\n.ta \\w'/dev/MAKEDEV.local  'u\n/dev/rx[01][ab]\tblock files\n.br\n/dev/rrx[01][ab]\traw files\n.br\n/dev/MAKEDEV\tscript to create special files\n.br\n/dev/MAKEDEV.local\tscript to localize special files\n.DT\n.SH \"SEE ALSO\"\nhk(4),\nra(4),\nram(4),\nrk(4),\nrl(4),\nrp(4),\nsi(4),\nxp(4),\ndtab(5),\nautoconfig(8),\nrxformat(8V)\n.SH DIAGNOSTICS\n\\fBrx2%d: hard error sn%d cs=%b er=%b\\fR.  An unrecoverable\nerror occurred during transfer of the specified sector of the specified\ndisk.  The contents of the two error registers are also printed\nin octal and symbolically with bits decoded.\nThe error was either unrecoverable, or a large number of retry attempts\ncould not recover the error.\n.SH BUGS\nIn raw I/O\n.I read\nand\n.IR write (2)\ntruncate file offsets to disk sector size block boundaries\n(either 128 or 256 bytes depending on the selected density),\nand\n.I write\nscribbles on the tail of incomplete blocks.\nThus,\nin programs that are likely to access raw devices,\n.I read, write\nand\n.IR lseek (2)\nshould always deal in disk sector size multiples.\n.PP\nDEC-standard error logging should be supported.\n.PP\nA program to analyze the logged error information (even in its\npresent reduced form) is needed.\n.PP\nThe 4.3BSD rx driver which supports more capabilities should be ported\nto 2.11BSD.\n"
  },
  {
    "path": "share/man/man4/si.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)si.4\t6.2 (Berkeley) 8/20/87\n.\\\"\n.TH SI 4 \"August 20, 1987\"\n.UC 2\n.SH NAME\nsi \\- SI 9500/CDC 9766 moving head disk\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNSI\t\\fIsi_drives\\fP\t# SI 9500 driver for CDC 9766 disks\n\n/etc/dtab:\n.ta .5i +\\w'#Name 'u +\\w'Unit# 'u +\\w'177777 'u +\\w'Vector 'u +\\w'Br 'u +\\w'xxxxxxx 'u +\\w'xxxxxxx 'u\n\t#Name\tUnit#\tAddr\tVector\tBr\tHandler(s)\t\t# Comments\n\tsi\t?\t176700\t170\t5\tsiintr\t\t# si9500\n.DT\n\nmajor device number(s):\n\traw: 18\n\tblock: 9\nminor device encoding:\n\tbits 0007 specify partition of SI drive\n\tbits 0070 specify SI drive\n.fi\n.ft R\n.SH DESCRIPTION\nFiles with minor device numbers 0 through 7 refer to various portions\nof drive 0;\nminor devices 8 through 15 refer to drive 1, etc.\nThe standard device names begin with ``si'' followed by\nthe drive number and then a letter a-h for partitions 0-7 respectively.\nThe character ? stands here for a drive number in the range 0-7.\n.PP\nThe block files access the disk via the system's normal\nbuffering mechanism and may be read and written without regard to\nphysical disk records.  There is also a `raw' interface\nwhich provides for direct transmission between the disk\nand the user's read or write buffer.\nA single read or write call results in exactly one I/O operation\nand therefore raw I/O is considerably more efficient when\nmany words are transmitted.  The names of the raw files\nconventionally begin with an extra `r.'\n.PP\nIn raw I/O the buffer must begin on a word (even) boundary,\nand counts should be a multiple of 512 bytes (a disk sector).\nLikewise\n.I seek\ncalls should specify a multiple of 512 bytes.\n.SH \"DISK SUPPORT\"\nThe origin and size (in sectors) of the\npseudo-disks on each drive are as follows:\n.PP\n.nf\n.ta .5i +\\w'disk  'u +\\w'000000  'u +\\w'000000  'u +\\w'000 - 000  'u\n.ne 10\nSI 9500/CDC9766 partitions:\n\tdisk\t start\tlength\t     cyls\tcomments\n\txp?a\t     0\t  9120\t  0 -  14\t/\n\txp?b\t  9120\t  9120\t 15 -  29\tswap\n\txp?c\t 18240\t234080\t 30 - 414\n\txp?d\t252320\t247906\t415 - 822*\n\txp?e\t 18240\t164160\t 30 - 299\t/usr\n\txp?f\t182400\t152000\t300 - 549\n\txp?g\t334400\t165826\t550 - 822*\n\txp?h\t     0\t500384\t  0 - 822\twhole pack\n.PP\n.DT\n.fi\n.PP\nThose partitions marked with an asterisk (``*'') actually stop short of the\nindicated ending cylinder to protect any bad block forwarding information\non the packs.  The indicated lengths are correct.  Partition ``h'' must be\nused to access the bad block forwarding area.\n.B N.B.:\nthe\n.I si\ndriver does not support bad block forwarding; the space is reserved in the\nevent bad block forwarding is ever added to the driver.\n.SH FILES\n.ta \\w'/dev/MAKEDEV.local  'u\n/dev/si[0-7][a-h]\tblock files\n.br\n/dev/rsi[0-7][a-h]\traw files\n.br\n/dev/MAKEDEV\tscript to create special files\n.br\n/dev/MAKEDEV.local\tscript to localize special files\n.SH SEE ALSO\nhk(4),\nra(4),\nram(4),\nrk(4),\nrl(4),\nrp(4),\nrx(4),\nxp(4),\ndtab(5),\nautoconfig(8)\n.SH DIAGNOSTICS\n\\fBsi%d%c: hard error sn%d cnr=%b err=%b\\fR.  An unrecoverable\nerror occurred during transfer of the specified sector of the specified\ndisk partition.  The contents of the two error registers are also printed\nin octal and symbolically with bits decoded.\nThe error was either unrecoverable, or a large number of retry attempts\n(including offset positioning and drive recalibration) could not\nrecover the error.\n.PP\n\\fBsi%d%c: hard error sn%d ssr=%b err=%b\\fR.  An unrecoverable\nerror occurred during transfer of the specified sector of the specified\ndisk partition.  The contents of the two error registers are also printed\nin octal and symbolically with bits decoded.\nThe error was either unrecoverable, or a large number of retry attempts\n(including offset positioning and drive recalibration) could not\nrecover the error.\n.SH BUGS\nIn raw I/O\n.I read\nand\n.IR write (2)\ntruncate file offsets to 512-byte block boundaries,\nand\n.I write\nscribbles on the tail of incomplete blocks.\nThus,\nin programs that are likely to access raw devices,\n.I read, write\nand\n.IR lseek (2)\nshould always deal in 512-byte multiples.\n.PP\nThe partition tables for the file systems should be read off of each\npack, as they are never quite what any single installation would prefer,\nand this would make packs more portable.\n"
  },
  {
    "path": "share/man/man4/spp.4",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)spp.4p\t1.2 (Berkeley) 9/17/85\n.\\\"\n.TH SPP 4P \"July 30, 1985\"\n.UC 6\n.SH NAME\nspp \\- Xerox Sequenced Packet Protocol\n.SH SYNOPSIS\n.B #include <sys/socket.h>\n.br\n.B #include <netns/ns.h>\n.br\n.B s = socket(AF_NS, SOCK_STREAM, 0);\n.PP\n.B #include <netns/sp.h>\n.br\n.B s = socket(AF_NS, SOCK_SEQPACKET, 0);\n.SH DESCRIPTION\nThe SPP protocol provides reliable, flow-controlled, two-way\ntransmission of data.  It is a byte-stream protocol used to\nsupport the SOCK_STREAM abstraction.  SPP uses the standard\nNS(tm) address formats.\n.PP\nSockets utilizing the SPP protocol are either \\*(lqactive\\*(rq or\n\\*(lqpassive\\*(rq.  Active sockets initiate connections to passive\nsockets.  By default SPP sockets are created active; to create a\npassive socket the\n.IR listen (2)\nsystem call must be used\nafter binding the socket with the\n.IR bind (2)\nsystem call.  Only\npassive sockets may use the \n.IR accept (2)\ncall to accept incoming connections.  Only active sockets may\nuse the\n.IR connect (2)\ncall to initiate connections.\n.PP\nPassive sockets may \\*(lqunderspecify\\*(rq their location to match\nincoming connection requests from multiple networks.  This\ntechnique, termed \\*(lqwildcard addressing\\*(rq, allows a single\nserver to provide service to clients on multiple networks.\nTo create a socket which listens on all networks, the NS\naddress of all zeroes must be bound.\nThe SPP port may still be specified\nat this time; if the port is not specified the system will assign one.\nOnce a connection has been established the socket's address is\nfixed by the peer entity's location.   The address assigned the\nsocket is the address associated with the network interface\nthrough which packets are being transmitted and received.  Normally\nthis address corresponds to the peer entity's network.\n.LP\nIf the SOCK_SEQPACKET socket type is specified,\neach packet received has the actual 12 byte sequenced packet header\nleft for the user to inspect:\n.nf\nstruct sphdr {\n\tu_char\t\tsp_cc;\t\t/* \\fIconnection control\\fP */\n#define\tSP_EM\t0x10\t\t\t/* \\fIend of message\\fP */\n\tu_char\t\tsp_dt;\t\t/* \\fIdatastream type\\fP */\n\tu_short\t\tsp_sid;\n\tu_short\t\tsp_did;\n\tu_short\t\tsp_seq;\n\tu_short\t\tsp_ack;\n\tu_short\t\tsp_alo;\n};\n.fi\nThis facilitates the implementation of higher level Xerox protocols\nwhich make use of the data stream type field and the end of message bit.\nConversely, the user is required to supply a 12 byte header,\nthe only part of which inspected is the data stream type and end of message\nfields.\n.LP\nFor either socket type,\npackets received with the Attention bit sent are interpreted as\nout of band data.  Data sent with send(..., ..., ..., MSG_OOB)\ncause the attention bit to be set.\n.SH DIAGNOSTICS\nA socket operation may fail with one of the following errors returned:\n.TP 20\n[EISCONN]\nwhen trying to establish a connection on a socket which\nalready has one;\n.TP 20\n[ENOBUFS]\nwhen the system runs out of memory for\nan internal data structure;\n.TP 20\n[ETIMEDOUT]\nwhen a connection was dropped\ndue to excessive retransmissions;\n.TP 20\n[ECONNRESET]\nwhen the remote peer\nforces the connection to be closed;\n.TP 20\n[ECONNREFUSED]\nwhen the remote\npeer actively refuses connection establishment (usually because\nno process is listening to the port);\n.TP 20\n[EADDRINUSE]\nwhen an attempt\nis made to create a socket with a port which has already been\nallocated;\n.TP 20\n[EADDRNOTAVAIL]\nwhen an attempt is made to create a \nsocket with a network address for which no network interface\nexists.\n.SH SOCKET OPTIONS\n.TP 20\nSO_DEFAULT_HEADERS\nwhen set, this determines the data stream type and whether\nthe end of message bit is to be set on every ensuing packet.\n.TP 20\nSO_MTU\nThis specifies the maximum ammount of user data in a single packet.\nThe default is 576 bytes - sizeof(struct spidp).  This quantity\naffects windowing -- increasing it without increasing the amount\nof buffering in the socket will lower the number of unread packets\naccepted.  Anything larger than the default will not be forwarded\nby a bona fide XEROX product internetwork router.\nThe data argument for the setsockopt call must be\nan unsigned short.\n.SH SEE ALSO\nintro(4N), ns(4F)\n.SH BUGS\nThere should be some way to reflect record boundaries in\na stream.\nFor stream mode, there should be an option to get the data stream type of\nthe record the user process is about to receive.\n"
  },
  {
    "path": "share/man/man4/sri.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)sri.4\t6.4 (Berkeley) 8/20/87\n.\\\"\n.TH SRI 4 \"August 20, 1987\"\n.UC 2\n.SH NAME\nsri \\- DR11-C IMP interface\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNSRI\t\\fIsri_controllers\\fP\t# SRI DR11c ARPAnet IMP\n.fi\n.ft R\n.SH DESCRIPTION\n.SH DIAGNOSTICS\n.BR \"sri%d: not alive\" .\nThe initialization routine was entered even though the device\ndid not autoconfigure.  This indicates a system problem.\n.PP\n.BR \"sri%d: can't initialize\" .\nInsufficient UNIBUS resources existed to initialize the device.\nThis is likely to occur when the device is run on a buffered\ndata path on an 11/750 and other network interfaces are also\nconfigured to use buffered data paths, or when it is configured\nto use buffered data paths on an 11/730 (which has none).\n.PP\n.BR \"sri%d: imp doesn't respond, ibf=%b\" .\nThe driver attempted to initialize the device, but the IMP\nfailed to respond after 5 tries.  Check the cabling.\n.PP\n.BR \"sri%d: stray xmit interrupt, csr=%b\" .\nAn interrupt occurred when no output had previously been started. \n.PP\n.BR \"sri%d: output error, csr=%b\" .\nThe device indicated a problem sending data on output.\n.PP\n.BR \"sri%d: input error, ibf=%b\" .\nThe device indicated a problem receiving data on input.\n.PP\n.BR \"sri%d: bad length=%d\" .\nAn input operation resulted in a data transfer of less than\n10 or more than 1008 bytes of\ndata into memory (according to the word count register).\nThis should never happen as the maximum size of a host-IMP\nmessage is 1018 bytes.\n"
  },
  {
    "path": "share/man/man4/swap.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)swap.4\t6.2 (Berkeley) 1/28/88\n.\\\"\n.TH SWAP 4 \"January 28, 1988\"\n.UC 2\n.SH NAME\nswap \\- swap device\n.SH DESCRIPTION\nThis file refers to the swap device in use by the system.\nIt should be linked to the special file for the disk or disk partition\non which the system swaps.\nIt is used by programs that wish to read from\nthe swap device without knowing its real name.\nThe script\n.I /dev/MAKEDEV.local\nnormally is edited by the system builder to set\n.I /dev/swap\nup correctly.\n.SH FILES\n.ta \\w'/dev/MAKEDEV.local  'u\n/dev/swap\n.br\n/dev/MAKEDEV\tscript to create special files\n.br\n/dev/MAKEDEV.local\tscript to localize special files\n.DT\n.SH \"SEE ALSO\"\nps(1),\nw(1)\n\n"
  },
  {
    "path": "share/man/man4/tb.4",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)tb.4\t6.3 (Berkeley) 8/1/87\n.\\\"\n.TH TB 4 \"August 1, 1987\"\n.UC 2\n.SH NAME\ntb \\- line discipline for digitizing devices\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNTB\t\\fI1\\fP\t# RS232 interface for Genisco/Hitachi tablets\n.fi\n.ft R\n.SH DESCRIPTION\nThis line discipline provides a polled interface to many common\ndigitizing devices which are connected to a host through a serial line.\nWhen these devices stream data at high speed, the use of the\nline discipline is critical in minimizing the number of samples\nthat would otherwise be lost due to buffer exhaustion in the\n.IR tty (4)\nhandler.\n.PP\nThe line discipline is enabled by a sequence:\n.PP\n.nf\n.ft B\n\t#include <sys/tablet.h>\n\tint ldisc = TBLDISC, fildes; ...\n\tioctl(fildes, TIOCSETD, &ldisc);\n.fi\n.ft R\n.PP\nA typical application program then polls the digitizing device by\nreading a binary data structure which contains: the current X and\nY positions (in the device coordinate space),\nup-down status of the buttons or pen stylus,\nproximity information (when available), and a count\nof the number of samples received from the input device\nsince it was opened.  In addition, devices such as the\nGTCO append tilt and pressure information to the end of\nthe aforementioned structure.  For the Polhemus 3-D digitizer\nthe structure read is completely different. Refer to the\ninclude file for a complete description.\n.PP\nWhile in tablet mode, normal teletype input and output functions take place.\nThus, if an 8 bit output data path is desired, it is necessary\nto prepare the output line by putting it into RAW mode using\n.IR ioctl (2).\nThis must be done\n.B before\nchanging the discipline with TIOCSETD, as most\n.IR ioctl (2)\ncalls are disabled while in tablet line-discipline mode.\n.PP\nThe line discipline supports\n.IR ioctl (2)\nrequests to get/set the operating mode, and to get/set the tablet type\nand operating mode by \\fIor\\fP-ing the two values together.\n.PP\nThe line discipline supports digitizing devices which are\ncompatible with Hitachi, GTCO, or Polhemus protocol formats.\nFor Hitachi there are several formats with that used in the\nnewer model HDG-1111B the most common.\n.SH \"SEE ALSO\"\ntty(4)\n.SH DIAGNOSTICS\nNone.\n"
  },
  {
    "path": "share/man/man4/tcp.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)tcp.4p\t6.2 (Berkeley) 5/16/86\n.\\\"\n.TH TCP 4P \"May 16, 1986\"\n.UC 5\n.SH NAME\ntcp \\- Internet Transmission Control Protocol\n.SH SYNOPSIS\n.B #include <sys/socket.h>\n.br\n.B #include <netinet/in.h>\n.PP\n.B s = socket(AF_INET, SOCK_STREAM, 0);\n.SH DESCRIPTION\nThe TCP protocol provides reliable, flow-controlled, two-way\ntransmission of data.  It is a byte-stream protocol used to\nsupport the SOCK_STREAM abstraction.  TCP uses the standard\nInternet address format and, in addition, provides a per-host\ncollection of \\*(lqport addresses\\*(rq.  Thus, each address is composed\nof an Internet address specifying the host and network, with\na specific TCP port on the host identifying the peer entity.\n.PP\nSockets utilizing the tcp protocol are either \\*(lqactive\\*(rq or\n\\*(lqpassive\\*(rq.  Active sockets initiate connections to passive\nsockets.  By default TCP sockets are created active; to create a\npassive socket the\n.IR listen (2)\nsystem call must be used\nafter binding the socket with the\n.IR bind (2)\nsystem call.  Only\npassive sockets may use the \n.IR accept (2)\ncall to accept incoming connections.  Only active sockets may\nuse the\n.IR connect (2)\ncall to initiate connections.\n.PP\nPassive sockets may \\*(lqunderspecify\\*(rq their location to match\nincoming connection requests from multiple networks.  This\ntechnique, termed \\*(lqwildcard addressing\\*(rq, allows a single\nserver to provide service to clients on multiple networks.\nTo create a socket which listens on all networks, the Internet\naddress INADDR_ANY\nmust be bound.  The TCP port may still be specified\nat this time; if the port is not specified the system will assign one.\nOnce a connection has been established the socket's address is\nfixed by the peer entity's location.   The address assigned the\nsocket is the address associated with the network interface\nthrough which packets are being transmitted and received.  Normally\nthis address corresponds to the peer entity's network.\n.PP\nTCP supports one socket option which is set with\n.IR setsockopt (2)\nand tested with\n.IR getsockopt (2).\nUnder most circumstances, TCP sends data when it is presented;\nwhen outstanding data has not yet been acknowledged, it gathers\nsmall amounts of output to be sent in a single packet once\nan acknowledgement is received.\nFor a small number of clients, such as window systems\nthat send a stream of mouse events which receive no replies,\nthis packetization may cause significant delays.\nTherefore, TCP provides a boolean option, TCP_NODELAY (from\n.IR <netinet/tcp.h> ,\nto defeat this algorithm.\nThe option level for the\n.I setsockopt\ncall is the protocol number for TCP,\navailable from\n.IR getprotobyname (3N).\n.PP\nOptions at the IP transport level may be used with TCP; see\n.IR ip (4P).\nIncoming connection requests that are source-routed are noted,\nand the reverse source route is used in responding.\n.SH DIAGNOSTICS\nA socket operation may fail with one of the following errors returned:\n.TP 20\n[EISCONN]\nwhen trying to establish a connection on a socket which\nalready has one;\n.TP 20\n[ENOBUFS]\nwhen the system runs out of memory for\nan internal data structure;\n.TP 20\n[ETIMEDOUT]\nwhen a connection was dropped\ndue to excessive retransmissions;\n.TP 20\n[ECONNRESET]\nwhen the remote peer\nforces the connection to be closed;\n.TP 20\n[ECONNREFUSED]\nwhen the remote\npeer actively refuses connection establishment (usually because\nno process is listening to the port);\n.TP 20\n[EADDRINUSE]\nwhen an attempt\nis made to create a socket with a port which has already been\nallocated;\n.TP 20\n[EADDRNOTAVAIL]\nwhen an attempt is made to create a \nsocket with a network address for which no network interface\nexists.\n.SH SEE ALSO\ngetsockopt(2), socket(2), intro(4N), inet(4F), ip(4P)\n"
  },
  {
    "path": "share/man/man4/tm.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)tm.4\t6.1 (Berkeley) 1/28/88\n.\\\"\n.TH TM 4 \"January 28, 1988\"\n.UC 2\n.SH NAME\ntm \\- TM-11/TE-10 magtape interface\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n.ta .5i +\\w'AVIVTM 'u +\\w'tm_drives 'u\n\t# Setting AVIVTM configures the TM driver for the AVIV 800/1600/6250\n \t# controller.  For more details, see /sys/pdpuba/tm.c.\n\tNTM\t\\fItm_drives\\fP\t# TM11\n\tAVIVTM\t\\fIYES\\fP\t# AVIV 800/1600/6250 controller\n\n/etc/dtab:\n.ta .5i +\\w'#Name 'u +\\w'Unit# 'u +\\w'177777 'u +\\w'Vector 'u +\\w'Br 'u +\\w'xxxxxxx 'u +\\w'xxxxxxx 'u\n\t#Name\tUnit#\tAddr\tVector\tBr\tHandler(s)\t\t# Comments\n\ttm\t?\t172520\t224\t5\ttmintr\t\t# tm11 driver\n.DT\n\nmajor device number(s):\n\traw: 7\n\tblock: 1\nminor device encoding:\n\tbits 0003 specify TS drive\n\tbit  0004 specifies no-rewind operation\n\tbits 0030 specify recording density:\n\t\t0000:   800BPI\n\t\t0010:  1600BPI (AVIVTM and some other controllers)\n\t\t0020:  6250BPI (AVIVTM only)\n.fi\n.ft R\n.SH DESCRIPTION\nThe tm-11/te-10 combination provides a standard tape drive\ninterface as described in\n.IR mtio (4).\nThe standard DEC tm-11 operates only at 800 bpi.\nOther controllers of this type may also allow operation at 1600 bpi,\nunder software control or by switching manually.\n.SH FILES\n.ta \\w'/dev/MAKEDEV.local  'u\n/dev/MAKEDEV\tscript to create special files\n.br\n/dev/MAKEDEV.local\tscript to localize special files\n.DT\n.SH \"SEE ALSO\"\nmt(1),\ntar(1),\ntp(1),\nmtio(4),\nht(4),\nts(4),\nmt(4),\ndtab(5),\nautoconfig(8)\n.SH DIAGNOSTICS\n\\fBte%d: no write ring\\fR.  An attempt was made to write on the tape drive\nwhen no write ring was present; this message is written on the terminal of\nthe user who tried to access the tape.\n.PP\n\\fBte%d: not online\\fR.  An attempt was made to access the tape while it\nwas offline; this message is written on the terminal of the user\nwho tried to access the tape.\n.PP\n\\fBte%d: can't change density in mid-tape\\fR.  An attempt was made to write\non a tape at a different density than is already recorded on the tape.\nThis message is written on the terminal of the user who tried to switch\nthe density.\n.PP\n\\fBte%d: hard error bn%d er=%b\\fR.   A tape error occurred\nat block \\fIbn\\fR; the tm error register is\nprinted in octal with the bits symbolically decoded.  Any error is\nfatal on non-raw tape; when possible the driver will have retried\nthe operation which failed several times before reporting the error.\n.PP\n\\fBte%d: lost interrupt\\fR.  A tape operation did not complete\nwithin a reasonable time, most likely because the tape was taken\noff-line during rewind or lost vacuum.  The controller should, but does not,\ngive an interrupt in these cases.  The device will be made available\nagain after this message, but any current open reference to the device\nwill return an error as the operation in progress aborts.\n.SH BUGS\nIf any non-data error is encountered on non-raw tape, it refuses to do anything\nmore until closed.\n"
  },
  {
    "path": "share/man/man4/tmscp.4",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)tmscp.4\t1.2 (2.11BSD) 1995/12/22\n.\\\"\n.TH TMSCP 4 \"December 22, 1995\"\n.UC 2\n.SH NAME\ntmscp \\- DEC TMSCP magtape interface\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\n        NTMSCP       1     # TMSCP controllers\n        NTMS         1     # TMSCP drives\n        TMSCP_DEBUG  NO    # debugging code in in TMSCP drive (EXPENSIVE)\n\n/etc/dtab:\n.ta .5i +\\w'#Name 'u +\\w'Unit# 'u +\\w'177777 'u +\\w'Vector 'u +\\w'Br 'u +\\w'xxxxxxx 'u +\\w'xxxxxxx 'u\n\t#Name\tUnit#\tAddr\tVector\tBr\tHandler(s)\t\t# Comments\n\ttms\t?\t174500\t260\t5\ttmsintr\t\t# tmscp driver\n\ttms\t?\t164334\t0\t5\ttmsintr\t\t# alternate\n.DT\n\nmajor device number(s):\n\n       raw: 23\n       block: 12\n\nminor device encoding:\n\nbit:    |7 | 6 | 5 | 4 | 3 | 2 | 1 | 0|\n        -------------------------------\n         C   C   X   D   D   N   U   U\n\n       C = Controller # (max of 4 controllers)\n       D = Density\n       N = Norewind on close\n       U = Unit (drive) number (max of 4 drives per controller)\n.fi\n.ft R\n.SH DESCRIPTION\nTape controllers compatible with the DEC\nTape Mass Storage Control Protocol (TMSCP) architecture\nsuch as the TU81 and the TK50\nprovide a standard tape drive interface \nas described in\n.IR mtio (4).\nThe controller communicates with the host through a packet\noriented protocol.\nConsult the file\n.IR < pdp/tmscp.h >\nfor a detailed \ndescription of this protocol.\n.SH FILES\n.ta \\w'/dev/MAKEDEV.local  'u\n/dev/MAKEDEV\tscript to create special files\n.br\n/dev/MAKEDEV.local\tscript to localize special files\n.DT\n.PP\nThe vector specified in \\fB/etc/dtab\\fP may be given as an explicit\nvalue in which case \\fIautoconfig(8)\\fP will attempt to allocate the \nspecified vector.  The vector may also be (if the system is at revision\nlevel 100 or higher) given as \\fB0\\fP - in which case \\fIautoconfig(8)\\fP\nwill request the kernel to allocate the next available vector (beginning\nat 01000 and proceeding downward) which \\fIautoconfig(8)\\fP will\ninitialize.\n.PP\nMultiple drives on a single controller are supported.  Multiple controllers\nare also supported.\n.PP\nDensity selection is specified by bits 3 and 4 in the minor device number.\nA value of 0 requests the lowest density of a drive and a value of 3\nthe highest density.  Values of 1 and 2 are essentially equivalent\n(because because TMSCP only defines values for three densities) and\nrequest the middle density (for tri-density tape drives).\n.SH DIAGNOSTICS\n.BR \"tms: !drives\" .\nNot enough drives were declared when the kernel was built.  The NTMS parameter\nin the kernel config file needs to be increased by at least one.\n.PP\n.BR \"tms%d stepN init failed: sa %x\" .\nStep N of the 4 step initialization sequence has failed.\n.PP\n.BR \"tms%d: random intr\" .\nAn unexpected interrupt was received.  This is indicative of some other\ndevice using the same interrupt vector as the TMSCP controller.\nThe interrupt is ignored.\n.PP\n.BR \"tms%d Ver %d Mod %d\" .\nThe version and model number of the controller are displayed when the\ncontroller is initialized.  This is an information message and not an error.\n.PP\n.BR \"tms%d: state %d\" .\nThe controller state is not one of the 4 initialization states or the RUN\nstate.  This indicates a serious problem in the driver and possibly the\nhardware.\n.PP\n.BR \"tms%d:  fatal error %x\" .\nThe controller detected a ``fatal error'' in the status returned\nto the host.  The contents of the status register are displayed.\n.PP\n.BR \"tms%d init fail\" .\nThe controller failed to initialize.  Indicative of a hardware problem.\n.PP\n.BR \"tms%d,%d flush fail\" .\nThe cache failed to flush during a close operation.  Data loss is possible\nin this case.\n.PP\n.BR \"tms%d,%d: sa %x state %d\" .\nA fatal error.  The controller will be reset in an attempt to resume\noperation.\n.PP\n.BR \"tms ioctl\" .\nAn invalid internal ioctl function call has been made.  This is a driver\nbug.\n.PP\n.BR \"tms%d,%d inv end\" .\nAn invalid end (completion) code has been detected.  A drive has returned\n0 as the opcode originally issued.  This is a hardware problem.\n.PP\n.BR \"tms%d,%d bad rsp: %x\" .\nAn unrecognized response has been received.  This is a driver bug.\n.PP\n.BR \"tms%d,%d cache lost\"\nThe cache on the drive has been lost.  Data loss is likely.  Usually due to\na hardware problem.\n.PP\nThe following error is produced when a TMSCP error log datagram is received:\n.sp\n.BR \"tms%d,%d dgram fmt=%x evt=%x grp=%x flg=%x pos=%D\" .\n.PP\nEarlier versions of the driver consumed a noticeable amount of kernel D-space\ndecoding and pretty printing more detailed information.  This has been \nremoved in favor of a shorter message.  In the future an error\nlog daemon will be written and the datagrams from the MSCP and TMSCP\ndrivers passed to it for analysis.\n.SH \"SEE ALSO\"\nmt(1), tar(1), tp(1), mtio(4), tm(4), ts(4), ut(4), dmesg(8), dtab(5),\nautoconfig(8)\n.SH BUGS\nIf any non-data error is encountered on non-raw tape, it refuses to do anything\nmore until closed.\n.PP\nOn quad-density tape drives (the Kennedy 9662 for example) the middle density \nof 3200bpi is not host selectable (it can be manually selected from the\ndrive's front panel) because TMSCP only defines 800, 1600 and 6250bpi.\n"
  },
  {
    "path": "share/man/man4/ts.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ts.4\t6.1 (Berkeley) 1/28/88\n.\\\"\n.TH TS 4 \"January 28, 1988\"\n.UC 2\n.SH NAME\nts \\- TS-11 magtape interface\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNTS\t\\fIts_drives\\fP\t\t# TS11\n\n/etc/dtab:\n.ta .5i +\\w'#Name 'u +\\w'Unit# 'u +\\w'177777 'u +\\w'Vector 'u +\\w'Br 'u +\\w'xxxxxxx 'u +\\w'xxxxxxx 'u\n\t#Name\tUnit#\tAddr\tVector\tBr\tHandler(s)\t\t# Comments\n\tts\t?\t172520\t224\t5\ttsintr\t\t# ts11 driver\n.DT\n\nmajor device number(s):\n\traw: 8\n\tblock: 2\nminor device encoding:\n\tbits 0003 specify TS drive\n\tbit  0004 specifies no-rewind operation\n\tbit  0010 ignored\n.fi\n.ft R\n.SH DESCRIPTION\nThe ts-11 combination provides a standard tape drive\ninterface as described in\n.IR mtio (4).\nThe ts-11 operates only at 1600 bpi, and only one transport\nis possible per controller.\n.SH FILES\n.ta \\w'/dev/MAKEDEV.local  'u\n/dev/MAKEDEV\tscript to create special files\n.br\n/dev/MAKEDEV.local\tscript to localize special files\n.DT\n.SH \"SEE ALSO\"\nmt(1),\ntar(1),\ntp(1),\nmtio(4),\nht(4),\ntm(4),\ndtab(5),\nautoconfig(8)\n.SH DIAGNOSTICS\n\\fBts%d: no write ring\\fR.  An attempt was made to write on the tape drive\nwhen no write ring was present; this message is written on the terminal of\nthe user who tried to access the tape.\n.PP\n\\fBts%d: not online\\fR.  An attempt was made to access the tape while it\nwas offline; this message is written on the terminal of the user\nwho tried to access the tape.\n.PP\n\\fBts%d: hard error bn%d xs0=%b xs1=%b xs2=%b xs3=%b\\fR.\nA hard error occurred on the tape\nat block \\fIbn\\fR; status registers 0-3 are printed in octal and symbolically\ndecoded as bits.\n.PP\n\\fBts%d: addr mod 4 != 0\\fR.\nThe address of a TS-11 command packet was not on an even longword boundary.\n.SH BUGS\nIf any non-data error is encountered on non-raw tape, it refuses to do anything\nmore until closed.\n.PP\nThe device lives at the same address as a tm-11\n.IR tm (4).\n"
  },
  {
    "path": "share/man/man4/tty.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)tty.4\t6.7.2 (2.11BSD GTE) 1997/4/10\n.\\\"\n.TH TTY 4 \"April 10, 1997\"\n.UC 4\n.SH NAME\ntty \\- general terminal interface\n.SH SYNOPSIS\n.B #include <sgtty.h>\n.SH DESCRIPTION\nThis section describes\nboth a particular special file\n.B /dev/tty\nand the terminal drivers used for conversational computing.\n.LP\n.B Line disciplines.\n.PP\nThe system provides different\n.I \"line disciplines\"\nfor controlling communications lines.\nIn this version of the system there are two disciplines available for use\nwith terminals:\n.IP \"old\" 8\nThe old (Version 7) terminal driver.  This is sometimes used when using the\nstandard shell\n.IR sh (1).\n.IP \"new\"\nThe standard Berkeley terminal driver, with features for job control;\nthis must be used when using\n.IR csh (1).\n.LP\nLine discipline switching is accomplished with the TIOCSETD \n.IR ioctl :\n.IP\n.B \"int ldisc = LDISC;\"\n.br\n.B \"ioctl(f, TIOCSETD, &ldisc);\"\n.LP\nwhere LDISC is OTTYDISC for the standard tty driver\nand NTTYDISC for the ``new'' driver.\nThe standard (currently old) tty driver is discipline 0 by convention.\nOther disciplines may exist for special purposes, such as use of communications\nlines for network connections.\nThe current line discipline can be obtained with the TIOCGETD\n.IR ioctl .\nPending input is discarded when the line discipline is changed.\n.PP\nAll of the low-speed asynchronous\ncommunications ports can use any\nof the available line disciplines, no matter what\nhardware is involved.\nThe remainder of this section discusses the\n\\*(lqold\\*(rq and \\*(lqnew\\*(rq disciplines.\n.LP\n.B \"The control terminal.\"\n.LP\nWhen a terminal file is opened, it causes the process to wait until a\nconnection is established.  In practice, user programs seldom open\nthese files; they are opened by\n.IR getty (8)\nor\n.IR rlogind (8C)\nand become a user's standard input and output file.\n.PP\nIf a process which has no control terminal opens a terminal file, then\nthat terminal file becomes the control terminal for that process.\nThe control terminal is thereafter inherited by a child process during a\n.IR fork (2),\neven if the control terminal is closed.\n.LP\nThe file\n.B /dev/tty\nis, in each process, a synonym for a\n.I \"control terminal\"\nassociated with that process.  It is useful for programs that wish to\nbe sure of writing messages on the terminal\nno matter how output has been redirected.\nIt can also be used for programs that demand a file name\nfor output, when typed output is desired\nand it is tiresome to find out which terminal\nis currently in use.\n.LP\nA process can remove the association it has with its controlling\nterminal by opening the file\n.B /dev/tty\nand issuing an\n.IP\n.B \"ioctl(f, TIOCNOTTY, 0);\"\n.LP\nThis is often desirable in server processes.\n.LP\n.B \"Process groups.\"\n.LP\nCommand processors such as\n.IR csh (1)\ncan arbitrate the terminal between different\n.I jobs\nby placing related jobs in a single process group and associating this\nprocess group with the terminal.  A terminal's associated process group\nmay be set using the TIOCSPGRP\n.IR ioctl (2):\n.IP\n.B \"ioctl(fildes, TIOCSPGRP, &pgrp);\"\n.LP\nor examined using TIOCGPGRP, which returns the current\nprocess group in\n.IR pgrp .\nThe new terminal driver aids in this arbitration by restricting access\nto the terminal by processes which are not in the current process group;\nsee\n.B \"Job access control\"\nbelow.\n.LP\n.B \"Modes.\"\n.PP\nThe terminal drivers have three major modes, characterized by the\namount of processing on the input and output characters:\n.IP cooked 10\nThe normal mode.  In this mode lines of input are collected and input editing\nis done.  The edited line is made available when it is completed by\na newline,\nor when the \\fIt_brkc\\fP character (normally undefined)\nor \\fIt_eofc\\fP character (normally an EOT, control-D, hereafter ^D)\nis entered.\nA carriage return is usually made synonymous with newline in this mode,\nand replaced with a newline whenever it is typed.\nAll driver functions\n(input editing, interrupt generation,\noutput processing such as tab expansion, etc.)\nare available in this mode.\n.IP CBREAK 10\nThis mode eliminates the character, word, and line editing input facilities,\nmaking the input character available to the user program as it is typed.\nFlow control, literal-next and interrupt processing are still done in this mode.\nOutput processing is done.\n.IP RAW 10\nThis mode eliminates all input processing and makes all input characters\navailable as they are typed; no output processing is done either.\n.PP\nThe style of input processing can also be very different when\nthe terminal is put in non-blocking I/O mode; see\nthe FNDELAY flag described in\n.IR fcntl (2).\nIn this case a\n.IR read (2)\nfrom the control terminal will never block, but rather\nreturn an error indication (EWOULDBLOCK) if there is no\ninput available.\n.PP\nA process may also request that a SIGIO signal be sent it whenever input\nis present and also whenever output queues fall below the low-water mark.\nTo enable this mode the FASYNC flag should be set using\n.IR fcntl (2).\n.LP\n.B \"Input editing.\"\n.LP\nA UNIX terminal ordinarily operates in full-duplex mode.\nCharacters may be typed at any time,\neven while output is occurring, and are only lost when the\nsystem's character input buffers become completely\nchoked, which is rare,\nor when the user has accumulated the maximum allowed number of\ninput characters that have not yet been read by some program.\nCurrently this limit is 256 characters.\nIn RAW mode, the terminal driver\nthrows away all input and output without notice when the limit is reached.\nIn CBREAK or cooked mode it refuses to accept any further input and,\nif in the new line discipline, rings the terminal bell.\n.PP\nInput characters are normally accepted in either even or odd parity\nwith the parity bit being stripped off before the character is given to\nthe program.  By clearing either the EVEN or ODD bit in the flags word\nit is possible to have input characters with that parity discarded (see the\n\\fBSummary\\fR below.)\n.PP\nIn all of the line disciplines, it is possible to simulate terminal\ninput using the TIOCSTI\n.IR ioctl ,\nwhich takes, as its third argument,\nthe address of a character.  The system pretends that this character\nwas typed on the argument terminal, which must be the control terminal except\nfor the super-user (this call is not in standard version 7 UNIX).\n.PP\nInput characters are normally echoed by putting them in an output queue\nas they arrive.  This may be disabled by clearing the ECHO bit in the\nflags word using the\n.IR stty (3C)\ncall or the TIOCSETN or TIOCSETP\n.IR ioctl s\n(see the \\fBSummary\\fR below).\n.PP\nIn cooked mode, terminal input is processed in units of lines.\nA program attempting\nto read will normally be suspended until an entire line has been\nreceived\n(but see the description of SIGTTIN in \\fBJob access control\\fR\nand of FIONREAD in\n\\fBSummary\\fR, both below.)\nNo matter how many characters are requested\nin the read call, at most one line will be returned.\nIt is not, however, necessary to read a whole line at\nonce; any number of characters may be\nrequested in a read, even one, without losing information.\n.PP\nDuring input, line editing is normally done, with the erase character\n.I sg_erase\n(by default, DELETE)\nlogically erasing the last character typed and the\n.I sg_kill\ncharacter (default, ^U: control-U)\nlogically erasing the entire current input line.\nThese characters\nnever erase beyond the beginning of the current input line or an eof.\n.PP\nThe drivers normally treat either a carriage return or a newline character\nas terminating an input line, replacing the return with a newline and echoing\na return and a line feed.\nIf the CRMOD bit is cleared in the local mode word then the processing\nfor carriage return is disabled, and it is simply echoed as a return,\nand does not terminate cooked mode input.\n.PP\nIn the new driver there is a literal-next character (normally ^V)\nwhich can be typed\nin both cooked and CBREAK mode preceding\n.I any\ncharacter to prevent its special meaning to the terminal handler.\n.PP\nThe new terminal driver also provides two other editing characters in\nnormal mode.  The word-erase character, normally ^W, erases the preceding\nword, but not any spaces before it.  For the purposes of ^W, a word\nis defined as a sequence of non-blank characters, with tabs counted as\nblanks.\nFinally, the reprint character, normally ^R, retypes the pending input beginning\non a new line.  Retyping occurs automatically in cooked mode if characters\nwhich would normally be erased from the screen are fouled by program output.\n.LP\n.B \"Input echoing and redisplay\"\n.LP\nThe terminal driver has several modes \nfor handling the echoing of\nterminal input, controlled by bits in a local mode word.\n.LP\n.I \"Hardcopy terminals.\"\nWhen a hardcopy terminal is in use, the LPRTERA bit is normally set in\nthe local mode word.  Characters which are logically erased are\nthen printed out backwards preceded by `\\e\\|' and followed by `/' in this mode.\n.LP\n.I \"CRT terminals.\"\nWhen a CRT terminal is in use, the LCRTBS bit is normally set in the local\nmode word.  The terminal driver then echoes the proper number of erase\ncharacters when input is erased; in the normal case where the erase\ncharacter is a ^H this causes the cursor of the terminal to back up\nto where it was before the logically erased character was typed.\nIf the input has become fouled due to interspersed asynchronous output,\nthe input is automatically retyped.\n.LP\n.I \"Erasing characters from a CRT.\"\nWhen a CRT terminal is in use, the LCRTERA bit may be set to cause\ninput to be erased from the screen with a \\*(lqbackspace-space-backspace\\*(rq\nsequence when character or word deleting sequences are used.\nA LCRTKIL bit may be set as well, causing the input to\nbe erased in this manner on line kill sequences as well.\n.LP\n.I \"Echoing of control characters.\"\nIf the LCTLECH bit is set in the local state word, then non-printing (control)\ncharacters are normally echoed as ^X (for some X)\nrather than being echoed unmodified; delete is echoed as ^?.\n.LP\nThe normal modes for use on CRT terminals are speed dependent.\nAt speeds less than 1200 baud, the LCRTERA and LCRTKILL processing\nis painfully slow, and\n.IR stty (1)\nnormally just sets LCRTBS and LCTLECH; at\nspeeds of 1200 baud or greater all of these bits are normally set.\n.IR Stty (1)\nsummarizes these option settings and the use of the new terminal\ndriver as\n\\*(lqnewcrt.\\*(rq\n.LP\n.B \"Output processing.\"\n.PP\nWhen one or more\ncharacters are written, they are actually transmitted\nto the terminal as soon as previously-written characters\nhave finished typing.\n(As noted above, input characters are normally \nechoed by putting them in the output queue\nas they arrive.)\nWhen a process produces characters more rapidly than they can be typed,\nit will be suspended when its output queue exceeds some limit.\nWhen the queue has drained down to some threshold\nthe program is resumed.\nEven parity is normally generated on output.\nThe EOT character is not transmitted in cooked mode to prevent terminals\nthat respond to it from hanging up; programs using RAW or CBREAK mode\nshould be careful.\n.PP\nThe terminal drivers provide necessary processing for cooked and CBREAK mode\noutput including parity\ngeneration.\nThe driver will also optionally\nexpand tabs into spaces, where the tab stops are assumed to be set every\neight columns, and optionally convert newlines to carriage returns\nfollowed by newline.  These functions are controlled by bits in the tty\nflags word; see \\fBSummary\\fR below.\n.PP\nFinally, in the new terminal driver, there is a output flush character,\nnormally ^O, which sets the LFLUSHO bit in the local mode word, causing\nsubsequent output to be flushed until it is cleared by a program or more\ninput is typed.  This character has effect in both cooked and CBREAK modes\nand causes pending input to be retyped if there is any pending input.\nAn\n.I ioctl\nto flush the characters in the input or output queues, TIOCFLUSH,\nis also available.\n.LP\n.B \"Flow control.\"\n.PP\nThere are two characters (the stop character, normally ^S, and the\nstart character, normally ^Q) which cause output to be suspended and\nresumed respectively.  Extra stop characters typed when output\nis already stopped have no effect, unless the start and stop characters\nare made the same, in which case output resumes.\n.PP\nA bit in the flags word may be set to put the terminal into TANDEM mode.\nIn this mode the system produces a stop character (default ^S) when\nthe input queue is in danger of overflowing, and a start character (default\n^Q) when the input has drained sufficiently.  This mode is useful\nwhen the terminal is actually another machine that obeys those\nconventions.\n.PP\nIf software flow control is not sufficient (it begins failing above 4800\nbits per second on slow systems) RTS/CTS flow control is now available.  \nHardware flow control causes RTS to be dropped when the remote system (modem)\nshould cease sending and to be raised when additional data can be accepted.\nIf the remote system drops CTS then the local host ceases sending data until\nthe CTS is raised.  Hardware flow control is enabled via the \\fBTIOCLBIS\\fP\n(or TIOCLBIC or TIOCLSET) function and the bit \\fBLRTSCTS\\fP.\n.LP\n.B \"Line control and breaks.\"\n.LP\nThere are several\n.I ioctl\ncalls available to control the state of the terminal line.\nThe TIOCSBRK\n.I ioctl\nwill set the break bit in the hardware interface\ncausing a break condition to exist; this can be cleared (usually after a delay\nwith\n.IR sleep (3))\nby TIOCCBRK.\nBreak conditions in the input are reflected as a null character in RAW mode\nor as the interrupt character in cooked or CBREAK mode.\nThe TIOCCDTR\n.I ioctl\nwill clear the data terminal ready condition; it can\nbe set again by TIOCSDTR.\n.PP\nWhen the carrier signal from the dataset drops (usually\nbecause the user has hung up his terminal) a\nSIGHUP hangup signal is sent to the processes in the distinguished\nprocess group of the terminal; this usually causes them to terminate.\nThe SIGHUP can be suppressed by setting the LNOHANG bit in the local\nstate word of the driver.\nAccess to the terminal by other processes is then normally revoked,\nso any further reads will fail, and programs that read a terminal and test for\nend-of-file on their input will terminate appropriately.\n.PP\nIt is possible to ask that the phone line be hung up on the last close\nwith the TIOCHPCL\n.IR ioctl ;\nthis is normally done on the outgoing lines and dialups.\n.LP\n.B \"Interrupt characters.\"\n.PP\nThere are several characters that generate interrupts in cooked and CBREAK\nmode; all are sent to the processes in the control group of the terminal,\nas if a TIOCGPGRP\n.I ioctl\nwere done to get the process group and then a\n.IR killpg (2)\nsystem call were done,\nexcept that these characters also flush pending input and output when\ntyped at a terminal\n(\\fI\\z'a\\`'la\\fR TIOCFLUSH).\nThe characters shown here are the defaults; the field names in the structures\n(given below)\nare also shown.\nThe characters may be changed.\n.IP ^C\n\\fBt_intrc\\fR (ETX) generates a SIGINT signal.\nThis is the normal way to stop a process which is no longer interesting,\nor to regain control in an interactive program.\n.IP ^\\e\n\\fBt_quitc\\fR (FS) generates a SIGQUIT signal.\nThis is used to cause a program to terminate and produce a core image,\nif possible,\nin the file\n.B core\nin the current directory.\n.IP ^Z\n\\fBt_suspc\\fR (EM) generates a SIGTSTP signal, which is used to suspend\nthe current process group.\n.IP ^Y\n\\fBt_dsuspc\\fR (SUB) generates a SIGTSTP signal as ^Z does, but the\nsignal is sent when a program attempts to read the ^Y, rather than when\nit is typed.\n.LP\n.B \"Job access control.\"\n.PP\nWhen using the new terminal driver,\nif a process which is not in the distinguished process group of its\ncontrol terminal attempts to read from that terminal its process group is\nsent a SIGTTIN signal.  This signal normally causes the members of\nthat process group to stop. \nIf, however, the process is ignoring SIGTTIN, has SIGTTIN blocked,\nor is in the middle of process creation using\n.IR vfork (2)),\nthe read will return \\-1 and set\n.I errno\nto EIO.\n.PP\nWhen using the new terminal driver with the LTOSTOP bit set in the local\nmodes, a process is prohibited from writing on its control terminal if it is\nnot in the distinguished process group for that terminal.\nProcesses which are holding or ignoring SIGTTOU signals\nor which are in the middle of a\n.IR vfork (2)\nare excepted and allowed to produce output.\n.B \"Terminal/window sizes.\"\nIn order to accommodate terminals and workstations with variable-sized\nwindows, the terminal driver provides a mechanism for obtaining and setting\nthe current terminal size.\nThe driver does not use this information internally, but only stores it\nand provides a uniform access mechanism.\nWhen the size is changed, a SIGWINCH signal is sent to the terminal's process\ngroup so that knowledgeable programs may detect size changes.\nThis facility was added in 4.3BSD and is not available in earlier\nversions of the system.\n.LP\n.B \"Summary of modes.\"\n.LP\nUnfortunately, due to the evolution of the terminal driver,\nthere are 4 different structures which contain various portions of the\ndriver data.  The first of these (\\fBsgttyb\\fR)\ncontains that part of the information\nlargely common between version 6 and version 7 UNIX systems.\nThe second contains additional control characters added in version 7.\nThe third is a word of local state added in 4BSD,\nand the fourth is another structure of special characters added for the\nnew driver.  In the future a single structure may be made available\nto programs which need to access all this information; most programs\nneed not concern themselves with all this state.\n.de Ul\n.ie t \\\\$1\\l'|0\\(ul'\n.el \\fI\\\\$1\\fP\n..\n.LP\n.Ul \"Basic modes: sgtty.\"\n.PP\nThe basic\n.IR ioctl s\nuse the structure\ndefined in\n.IR <sgtty.h> :\n.PP\n.ta .5i 1i\n.nf\n.ft 3\nstruct sgttyb {\n\tchar\tsg_ispeed;\n\tchar\tsg_ospeed;\n\tchar\tsg_erase;\n\tchar\tsg_kill;\n\tshort\tsg_flags;\n};\n.ft R\n.fi\n.PP\nThe\n.I sg_ispeed \nand \n.I sg_ospeed\nfields describe the input and output speeds of the\ndevice according to the following table,\nwhich corresponds to the DEC DH-11 interface.\nIf other hardware is used,\nimpossible speed changes are ignored.\nSymbolic values in the table are as defined in\n.IR <sgtty.h> .\n.PP\n.nf\n.ta \\w'B9600   'u +5n\nB0\t0\t(hang up dataphone)\nB50\t1\t50 baud\nB75\t2\t75 baud\nB110\t3\t110 baud\nB134\t4\t134.5 baud\nB150\t5\t150 baud\nB200\t6\t200 baud\nB300\t7\t300 baud\nB600\t8\t600 baud\nB1200\t9\t1200 baud\nB1800\t10\t1800 baud\nB2400\t11\t2400 baud\nB4800\t12\t4800 baud\nB9600\t13\t9600 baud\nEXTA\t14\tExternal A\nEXTB\t15\tExternal B\n.fi\n.DT\n.PP\nCode conversion and line control required for\nIBM 2741's (134.5 baud)\nmust be implemented by the user's\nprogram.\nThe half-duplex line discipline\nrequired for the 202 dataset (1200 baud)\nis not supplied; full-duplex 212 datasets work fine.\n.PP\nThe\n.I sg_erase\nand\n.I sg_kill\nfields of the argument structure\nspecify the erase and kill characters respectively.\n(Defaults are DELETE and ^U.)\n.PP\nThe\n.I sg_flags\nfield of the argument structure\ncontains several bits that determine the\nsystem's treatment of the terminal:\n.PP\n.ta \\w'TANDEM 'u +\\w'0100000 'u\n.nf\nXTABS\t0004000 Expand tabs on output\nEVENP\t0000200\tEven parity allowed on input\nODDP\t0000100\tOdd parity allowed on input\nRAW\t0000040\tRaw mode: wake up on all characters, 8-bit interface\nCRMOD\t0000020\tMap CR into LF; output LF as CR-LF\nECHO\t0000010\tEcho (full duplex)\nCBREAK\t0000002\tReturn each character as soon as typed\nTANDEM\t0000001\tAutomatic inbound xon/xoff flow control\n.DT\n.fi\n.PP\nXTABS,\ncauses tabs to be replaced\nby the appropriate number of spaces on output.\n.PP\nThe flags for even and odd parity control parity checking on input\nand generation on output in cooked and CBREAK mode\n(unless LPASS8 is enabled, see below).\nEven parity is generated on output unless ODDP is set and EVENP\nis clear, in which case odd parity is generated.\nInput characters with the wrong parity, as determined by EVENP and\nODDP, are ignored in cooked and CBREAK mode.\n.PP\nRAW\ndisables all processing save output flushing with LFLUSHO;\nfull 8 bits of input are given as soon as\nit is available; all 8 bits are passed on output.\nA break condition in the input is reported as a null character.\nIf the input queue overflows in raw mode all data in the input and output\nqueues are discarded; this applies to both new and old drivers.\n.PP\nCRMOD causes input carriage returns to be turned into\nnew-lines, and output and echoed new-lines to be output as a carriage return\nfollowed by a line feed.\n.PP\nCBREAK is a sort of half-cooked (rare?) mode.\nPrograms can read each character as soon as typed, instead\nof waiting for a full line;\nall processing is done except the input editing:\ncharacter and word erase and line kill, input reprint,\nand the special treatment of \\e and EOT are disabled.\n.PP\nTANDEM mode causes the system to produce\na stop character (default ^S) whenever the input\nqueue is in danger of overflowing, and a start character\n(default ^Q)\nwhen the input queue has drained sufficiently.\nIt is useful for flow control when the `terminal'\nis really another computer which understands the conventions.\n.LP\n.B Note:\nThe same ``stop'' and ``start'' characters are used for both directions\nof flow control; the\n.I t_stopc\ncharacter is accepted on input as the character that stops output and is\nproduced on output as the character to stop input, and the\n.I t_startc\ncharacter is accepted on input as the character that restarts output and is\nproduced on output as the character to restart input.\n.LP\n.Ul \"Basic ioctls\"\n.PP\nA large number of\n.IR ioctl (2)\ncalls apply to terminals.  Some have the general form:\n.PP\n.B #include <sgtty.h>\n.PP\n.B ioctl(fildes, code, arg)\n.br\n.B struct sgttyb *arg;\n.PP\nThe applicable codes are:\n.IP TIOCGETP 15\nFetch the basic parameters associated with the terminal, and store\nin the pointed-to \\fIsgttyb\\fR structure.\n.IP TIOCSETP\nSet the parameters according to the pointed-to \\fIsgttyb\\fR structure.\nThe interface delays until output is quiescent,\nthen throws away any unread characters,\nbefore changing the modes.\n.IP TIOCSETN\nSet the parameters like TIOCSETP but do not delay or flush input.\nInput is not preserved, however, when changing to or from RAW.\n.PP\nWith the following codes\n.I arg\nis ignored.\n.IP TIOCEXCL 15\nSet \\*(lqexclusive-use\\*(rq mode:\nno further opens are permitted until the file has been closed.\n.IP TIOCNXCL\nTurn off \\*(lqexclusive-use\\*(rq mode.\n.IP TIOCHPCL\nWhen the file is closed for the last time,\nhang up the terminal.\nThis is useful when the line is associated\nwith an ACU used to place outgoing calls.\n.PP\nWith the following codes\n.I arg\nis a pointer to an\n.BR int .\n.IP TIOCGETD 15\n.I arg\nis a pointer to an\n.B int\ninto which is placed the current line discipline number.\n.IP TIOCSETD\n.I arg\nis a pointer to an\n.B int\nwhose value becomes the current line discipline number.\n.IP TIOCFLUSH\nIf the\n.B int\npointed to by\n.I arg\nhas a zero value, all characters waiting in input or output queues are flushed.\nOtherwise, the value of the\n.B int\nis for the FREAD and FWRITE bits defined in\n.BR <sys/file.h> ;\nif the FREAD bit is set, all characters waiting in input queues are flushed,\nand if the FWRITE bit is set, all characters waiting in output queues are\nflushed.\n.LP\nThe remaining calls are not available in vanilla version 7 UNIX.\nIn cases where arguments are required, they are described; \\fIarg\\fR\nshould otherwise be given as 0.\n.IP TIOCSTI 15\nthe argument points to a character which the system\npretends had been typed on the terminal.\n.IP TIOCSBRK 15\nthe break bit is set in the terminal.\n.IP TIOCCBRK\nthe break bit is cleared.\n.IP TIOCSDTR \ndata terminal ready is set.\n.IP TIOCCDTR\ndata terminal ready is cleared.\n.IP TIOCSTOP 15\noutput is stopped as if the ``stop'' character had been typed.\n.IP TIOCSTART\noutput is restarted as if the ``start'' character had been typed.\n.IP TIOCGPGRP\n.I arg\nis a pointer to an\n.B int\ninto which is placed the process group ID of the process group\nfor which this terminal is the control terminal.\n.IP TIOCSPGRP\n.I arg\nis a pointer to an\n.B int\nwhich is the value to which the process group ID\nfor this terminal will be set.\n.IP TIOCOUTQ\nreturns in the\n.B int\npointed to by\n.I arg\nthe number of characters queued for output to the terminal.\n.IP FIONREAD\nreturns in the\n.B long\npointed to by\n.I arg\nthe number of characters immediately readable from the argument descriptor.\nThis works for files, pipes, and terminals.\n.PP\n.Ul Tchars\n.PP\nThe second structure associated with each terminal specifies\ncharacters that are special in both the old and new terminal interfaces:\nThe following structure is defined in\n.IR <sys/ioctl.h> ,\nwhich is automatically included in\n.IR <sgtty.h> :\n.PP\n.nf\n.ft 3\n.ta .5i 1i 2i \nstruct tchars {\n\tchar\tt_intrc;\t/* interrupt */\n\tchar\tt_quitc;\t/* quit */\n\tchar\tt_startc;\t/* start output */\n\tchar\tt_stopc;\t/* stop output */\n\tchar\tt_eofc;\t\t/* end-of-file */\n\tchar\tt_brkc;\t\t/* input delimiter (like nl) */\n};\n.DT\n.fi\n.ft R\n.PP\nThe default values for these characters are\n^C, ^\\e\\|, ^Q, ^S, ^D, and \\-1.\nA character value of \\-1\neliminates the effect of that character.\nThe\n.I t_brkc\ncharacter, by default \\-1,\nacts like a new-line in that it terminates a `line,'\nis echoed, and is passed to the program.\nThe `stop' and `start' characters may be the same,\nto produce a toggle effect.\nIt is probably counterproductive to make\nother special characters (including erase and kill)\nidentical.\nThe applicable\n.I ioctl\ncalls are:\n.IP TIOCGETC 12\nGet the special characters and put them in the specified structure.\n.IP TIOCSETC 12\nSet the special characters to those given in the structure.\n.LP\n.Ul \"Local mode\"\n.PP\nThe third structure associated with each terminal is a local mode word.\nThe bits of the local mode word are:\n.sp\n.nf\nLCRTBS\t000001\tBackspace on erase rather than echoing erase\nLPRTERA\t000002\tPrinting terminal erase mode\nLCRTERA\t000004\tErase character echoes as backspace-space-backspace\nLMDMBUF\t000020\tStop/start output when carrier drops\nLLITOUT\t000040\tSuppress output translations\nLTOSTOP\t000100\tSend SIGTTOU for background output\nLFLUSHO\t000200\tOutput is being flushed\nLNOHANG\t000400\tDon't send hangup when carrier drops\nLRTSCTS\t001000\tRTS/CTS flow control\nLCRTKIL\t002000\tBS-space-BS erase entire line on line kill\nLPASS8\t004000\tPass all 8 bits through on input, in any mode\nLCTLECH\t010000\tEcho input control chars as ^X, delete as ^?\nLPENDIN\t020000\tRetype pending input at next read or input character\nLDECCTQ\t040000\tOnly ^Q restarts output after ^S, like DEC systems\nLNOFLSH\t100000\tInhibit flushing of pending I/O when an interrupt character is typed.\n.fi\n.sp\nThe applicable\n.I ioctl\nfunctions are:\n.IP TIOCLBIS 15\n.I arg\nis a pointer to an\n.B int\nwhose value is a mask containing the bits to be set in the local mode word.\n.IP TIOCLBIC\n.I arg\nis a pointer to an\n.B int\nwhose value is a mask containing the bits to be cleared in the local mode word.\n.IP TIOCLSET\n.I arg\nis a pointer to an\n.B int\nwhose value is stored in the local mode word.\n.IP TIOCLGET\n.I arg\nis a pointer to an\n.B int\ninto which the current local mode word is placed.\n.LP\n.Ul \"Local special chars\"\n.PP\nThe\nfinal control structure associated with each terminal is the\n.I ltchars\nstructure which defines control characters\nfor the new terminal driver.\nIts structure is:\n.nf\n.sp\n.ta .5i 1i 2i\n.ft B\nstruct ltchars {\n\tchar\tt_suspc;\t/* stop process signal */\n\tchar\tt_dsuspc;\t/* delayed stop process signal */\n\tchar\tt_rprntc;\t/* reprint line */\n\tchar\tt_flushc;\t/* flush output (toggles) */\n\tchar\tt_werasc;\t/* word erase */\n\tchar\tt_lnextc;\t/* literal next character */\n};\n.ft R\n.fi\n.sp\nThe default values for these characters are ^Z, ^Y, ^R, ^O, ^W, and ^V.\nA value of \\-1 disables the character.\n.PP\nThe applicable \\fIioctl\\fR functions are:\n.IP TIOCSLTC 12\n.I arg\nis a pointer to an\n.I ltchars\nstructure which defines the new local special characters.\n.IP TIOCGLTC 12\n.I arg\nis a pointer to an\n.I ltchars\nstructure into which is placed the current set of local special characters.\n.LP\n.Ul \"Window/terminal sizes\"\n.PP\nEach terminal has provision for storage of the current terminal or window\nsize in a\n.I winsize\nstructure, with format:\n.nf\n.sp\n.ft B\n.ta .5i +\\w'unsigned short\\ \\ \\ \\ 'u +\\w'ws_ypixel;\\ \\ \\ \\ \\ 'u\nstruct winsize {\n\tunsigned short\tws_row;\t/* rows, in characters */\n\tunsigned short\tws_col;\t/* columns, in characters */\n\tunsigned short\tws_xpixel;\t/* horizontal size, pixels */\n\tunsigned short\tws_ypixel;\t/* vertical size, pixels */\n};\n.ft R\n.fi\n.LP\nA value of 0 in any field is interpreted as ``undefined;''\nthe entire structure is zeroed on final close.\n.PP\nThe applicable \\fIioctl\\fP functions are:\n.IP TIOCGWINSZ\n.I arg\nis a pointer to a\n.B \"struct winsize\"\ninto which will be placed the current terminal or window size information.\n.IP TIOCSWINSZ\n.I arg\nis a pointer to a\n.B \"struct winsize\"\nwhich will be used to set the current terminal or window size information.\nIf the new information is different than the old information,\na SIGWINCH signal will be sent to the terminal's process group.\n.SH FILES\n/dev/tty\n.br\n/dev/tty*\n.br\n/dev/console\n.SH SEE ALSO\ncsh(1),\nstty(1),\ntset(1),\nioctl(2),\nsigvec(2),\nstty(3C),\ngetty(8)\n"
  },
  {
    "path": "share/man/man4/udp.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)udp.4p\t6.2 (Berkeley) 5/16/86\n.\\\"\n.TH UDP 4P \"May 16, 1986\"\n.UC 5\n.SH NAME\nudp \\- Internet User Datagram Protocol\n.SH SYNOPSIS\n.B #include <sys/socket.h>\n.br\n.B #include <netinet/in.h>\n.PP\n.B s = socket(AF_INET, SOCK_DGRAM, 0);\n.SH DESCRIPTION\nUDP is a simple, unreliable datagram protocol which is used\nto support the SOCK_DGRAM abstraction for the Internet\nprotocol family.  UDP sockets are connectionless, and are\nnormally used with the\n.I sendto \nand\n.IR recvfrom \ncalls, though the\n.IR connect (2)\ncall may also be used to fix the destination for future\npackets (in which case the \n.IR recv (2)\nor\n.IR read (2)\nand \n.IR send (2)\nor\n.IR write(2)\nsystem calls may be used).\n.PP\nUDP address formats are identical to those used by\nTCP. In particular UDP provides a port identifier in addition\nto the normal Internet address format.  Note that the UDP port\nspace is separate from the TCP port space (i.e. a UDP port\nmay not be \\*(lqconnected\\*(rq to a TCP port).  In addition broadcast\npackets may be sent (assuming the underlying network supports\nthis) by using a reserved \\*(lqbroadcast address\\*(rq; this address\nis network interface dependent.\n.PP\nOptions at the IP transport level may be used with UDP; see\n.IR ip (4P).\n.SH DIAGNOSTICS\nA socket operation may fail with one of the following errors returned:\n.TP 15\n[EISCONN]\nwhen trying to establish a connection on a socket which\nalready has one, or when trying to send a datagram with the destination\naddress specified and the socket is already connected;\n.TP 15\n[ENOTCONN]\nwhen trying to send a datagram, but\nno destination address is specified, and the socket hasn't been\nconnected;\n.TP 15\n[ENOBUFS]\nwhen the system runs out of memory for\nan internal data structure;\n.TP 15\n[EADDRINUSE]\nwhen an attempt\nis made to create a socket with a port which has already been\nallocated;\n.TP 15\n[EADDRNOTAVAIL]\nwhen an attempt is made to create a \nsocket with a network address for which no network interface\nexists.\n.SH SEE ALSO\ngetsockopt(2), recv(2), send(2), socket(2), intro(4N), inet(4F), ip(4P)\n"
  },
  {
    "path": "share/man/man4/vv.4",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)vv.4\t6.2 (Berkeley) 8/20/87\n.\\\"\n.TH VV 4 \"August 20, 1987\"\n.UC 2\n.SH NAME\nvv \\- Proteon proNET 10 Megabit ring\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n\tNVV\t\\fIvv_controllers\\fP\t# V2LNI (Pronet)\n.fi\n.ft R\n.SH DESCRIPTION\nThe\n.I vv\ninterface provides access to a 10 Mb/s Proteon proNET ring network.\n.PP\nThe network address of the interface must be specified with an\nan SIOCSIFADDR ioctl before data can be transmitted or received.\nIt is only permissible to change the network address while the\ninterface is marked \"down\".\n.PP\nThe host's hardware address is discovered by putting the interface in\ndigital loopback mode (not joining the ring) and sending a broadcast\npacket from which the hardware address is extracted.\n.PP\nTransmit timeouts are detected through use of a watchdog routine.\nLost input interrupts are checked for when packets are sent out.\n.PP\nIf the installation is running CTL boards which use the old broadcast\naddress of 0 instead of the new address of 0xff, the define OLD_BROADCAST\nshould be specified in the driver.\n.PP\nThe driver can use ``trailer'' encapsulation to minimize copying\ndata on input and output.\nThis may be disabled, on a per-interface basis,\nby setting the IFF_NOTRAILERS flag with an SIOCSIFFLAGS ioctl.\n.SH DIAGNOSTICS\n.PP\n\\fBvv%d: host %d\\fP.  The software announces the host\naddress discovered during autoconfiguration.\n.PP\n\\fBvv%d: can't initialize\\fP. The software was unable to\ndiscover the address of this interface, so it deemed\n\"dead\" will not be enabled.\n.PP\n\\fBvv%d: error vvocsr=%b\\fP.  The hardware indicated an error on\nthe previous transmission.\n.PP\n\\fBvv%d: output timeout\\fP.  The token timer has fired and the\ntoken will be recreated.\n.PP\n\\fBvv%d: error vvicsr=%b\\fP.  The hardware indicated an error\nin reading a packet off the ring.\n.PP\n\\fBen%d: can't handle af%d\\fP.  The interface was handed\na message with addresses formatted in an unsuitable address\nfamily; the packet was dropped.\n.PP\n\\fBvv%d: vs_olen=%d\\fP.  The ring output routine has been\nhanded a message with a preposterous length.  This results in\nan immediate \n.IR \"panic: vs_olen\" .\n.SH SEE ALSO\nintro(4N), inet(4F)\n.SH BUGS\nThe encapsulation of trailer packets in the 4.2BSD version of this driver\nwas incorrect (the packet type was in VAX byte order).\nAs a result, the trailer encapsulation in this version is not compatible\nwith the 4.2BSD VAX version.\n"
  },
  {
    "path": "share/man/man4/xp.4",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)xp.4\t6.4 (2.11BSD GTE) 1995/08/14\n.\\\"\n.TH XP 4 \"August 14, 1995\"\n.UC 2\n.SH NAME\nxp \\- generic SMD moving-head disk\n.SH SYNOPSIS\n.ft B\n.nf\n/sys/conf/SYSTEM:\n.ta .5i +\\w'BADSECT 'u +\\w'xp_controllers 'u\n\tNXPC\t\\fIxp_controllers\\fP\t# Number of controllers\n\tNXPD\t\\fIxp_drives\\fP\t\t# RM02/03/05, RP04/05/06, \n\t\t\t\t\t# CDC 9766, Fuji 160, etc.\n\tBADSECT\t\\fINO\\fP\t\t# Bad sector handling (see BUGS)\n.DT\n\n/etc/dtab:\n.ta .5i +\\w'#Name 'u +\\w'Unit# 'u +\\w'177777 'u +\\w'Vector 'u +\\w'Br 'u +\\w'xxxxxxx 'u +\\w'xxxxxxx 'u\n\t#Name\tUnit#\tAddr\tVector\tBr\tHandler(s)\t\t# Comments\n\txp\t?\t176700\t254\t5\txpintr\t\t# xp driver\n.DT\n\nmajor device number(s):\n\traw: 19\n\tblock: 10\nminor device encoding:\n\tbits 0007 specify partition of XP drive\n\tbits 0370 specify XP drive\n.fi\n.ft R\n.SH DESCRIPTION\nThe\n.I xp\ndriver is a generic SMD storage module disk driver.  It can be adapted to\nmost SMD controllers although bootstrapping will not necessarily be\ndirectly possible.  The drives are numbered from 0 to\n.I n\non\ncontroller 0, from\n.IR n +1\nto\n.I m\non controller 1, etc.  The drives may have different geometries.  \n.PP\nThe \\fIxp\\fP\ndriver is unique amoungst 2BSD drivers in its numbering of drives.\nOther drivers (\\fIra\\fP for example) number drives 0 thru 7 on controller\n1, 8 thru 15 on controller 2 and so on.  \\fIxp\\fP on the other hand can\nhave drives 0 and 1 on controller 1, drives 2, 3, 4 and 5 on controller 2 and\ndrives 6, 7 and 8 on controller 3.  This is different from \\fBboot\\fP's\nview of the world, so if you are booting from other than unit 0 you may\nhave to experiment a bit.\n.PP\nFiles with minor device numbers 0 through 7 refer to various portions\nof drive 0;\nminor devices 8 through 15 refer to drive 1, etc.\nThe standard device names begin with ``xp'' followed by\nthe drive number and then a letter a-h for partitions 0-7 respectively.\nThe character ? stands here for a drive number in the range 0-7.\n.PP\nThe block files access the disk via the system's normal\nbuffering mechanism and may be read and written without regard to\nphysical disk records.  There is also a `raw' interface\nwhich provides for direct transmission between the disk\nand the user's read or write buffer.\nA single read or write call results in exactly one I/O operation\nand therefore raw I/O is considerably more efficient when\nmany words are transmitted.  The names of the raw files\nconventionally begin with an extra `r.'\n.PP\nIn raw I/O the buffer must begin on a word (even) boundary,\nand counts should be a multiple of 512 bytes (a disk sector).\nLikewise\n.I lseek\ncalls should specify a multiple of 512 bytes.\n.SH \"DISK SUPPORT\"\nDisks must be labeled using either the standalone \\fIdisklabel\\fP program\non the boot tape or with the\n.IR disklabel (8)\nprogram.  The kernel no longer attempts to determine the drive type and\ngeometry, instead reading this information from the disklabel.  There are\nno partition tables coded into the \\fIxp\\fP driver, these must be placed\non the drive with \\fIdisklabel\\fP.\n.PP\nSpecial files should only be created for the\npartitions that are actually used,\nas the overlap in these addresses could lead to confusion otherwise.\nTraditionally\nthe xp?a partition is normally used for the root file system,\nthe xp?b partition as a swap area,\nand the xp?c partition for pack-pack copying (it maps the entire disk).  \n.SH FILES\n.ta \\w'/dev/MAKEDEV.local  'u\n/dev/xp[0-7][a-h]\tblock files\n.br\n/dev/rxp[0-7][a-h]\traw files\n.br\n/dev/MAKEDEV\tscript to create special files\n.br\n/dev/MAKEDEV.local\tscript to localize special files\n.SH SEE ALSO\nhk(4),\nra(4),\nram(4),\nrk(4),\nrl(4),\nrp(4),\nrx(4),\nsi(4),\ndtab(5),\nautoconfig(8),\nnewfs(8)\n.SH DIAGNOSTICS\n\\fBxp%d%c: hard error sn%d cs2=%b er1=%b\\fR.  An unrecoverable\nerror occurred during transfer of the specified sector of the specified\ndisk partition.  The contents of the two error registers are also printed\nin octal and symbolically with bits decoded.\nThe error was either unrecoverable, or a large number of retry attempts\n(including offset positioning and drive recalibration) could not\nrecover the error.\n.PP\n\\fBxp%d: write locked\\fR.  The write protect switch was set on the drive\nwhen a write was attempted.  The write operation is not recoverable.\n.PP\n\\fBxp%d%c: soft ecc sn%d\\fR.  A recoverable ECC error occurred on the\nspecified sector of the specified disk partition.  This happens normally\na few times a week.  If it happens more frequently than\nthis the sectors where the errors are occurring should be checked to see\nif certain cylinders on the pack, spots on the carriage of the drive\nor heads are indicated.\n.PP\n\\fBxp%d: unknown device type 0%o\\fR.  The number in the drive's drive\ntype register is unknown to the xp driver.\n.SH BUGS\nIn raw I/O\n.I read\nand\n.IR write (2)\ntruncate file offsets to 512-byte block boundaries,\nand\n.I write\nscribbles on the tail of incomplete blocks.\nThus,\nin programs that are likely to access raw devices,\n.I read, write\nand\n.IR lseek (2)\nshould always deal in 512-byte multiples.\n.PP\nDEC-standard error logging should be supported.\n.PP\nThe kernel uses partition 'h' to access the badblock information.  This \nshould have been 'c' except that almost all of the /etc/disktab entries\n(and thus existing systems) use 'h' for this purpose.  Unless you are\nvery careful with \\fIdisklabel\\fP|(8) (to make certain that no data\npartition overlaps the badblock area) you should probably leave BADSECT\nundefined in the kernel config file.\n"
  },
  {
    "path": "share/man/man5/L-devices.5",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)L-devices.5\t6.1.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH L-DEVICES 5 \"October 22, 1996\"\n.UC 6\n.SH NAME\nL-devices \\- UUCP device description file \n.SH DESCRIPTION\nThe L-devices file is consulted by the UUCP daemon\n.IR uucico (8)\nunder the direction of\n.IR L.sys (5)\nfor information on the devices that it may use.\nEach line describes exactly one device.\n.PP\nA line in\n.I L-devices\nhas the form:\n.PP\nCaller  Device  Call_Unit  Class  Dialer  [Expect  Send]....\n.PP\nEach item can be separated by any number of blanks or tabs. Lines beginning\nwith a `#' character are comments; long lines can be continued by appending\na `\\e' character to the end of the line.\n.PP\n.I Caller\ndenotes the type of connection, and must be one of the following:\n.TP 8\n.B ACU\nAutomatic call unit, e.g., autodialing modems such as the Hayes\nSmartmodem 1200 or Novation ``Smart Cat''.\n.TP 8\n.B DIR\nDirect connect; hardwired line (usually RS-232) to a remote system.\n.TP 8\n.B DK\nAT&T Datakit.\n.TP 8\n.B MICOM\nMicom Terminal switch.\n.TP 8\n.B PAD\nX.25 PAD connection.\n.TP 8\n.B PCP\nGTE Telenet PC Pursuit.\n.TP 8\n.B SYTEK\nSytek high-speed dedicated modem port connection.\n.TP 8\n.B TCP\nBerkeley TCP/IP or 3Com UNET connection. These are mutually exclusive.\nNote that listing TCP connections in\n.I L-devices\nis superfluous;\n.I uucico\ndoes not even bother to look here since it has all the information it\nneeds in\n.IR L.sys (5).\n.PP\n.I Device\nis a device file in /dev/ that is opened to use the device. The device\nfile must be owned by UUCP, with access modes of 0600 or better. (See\n.IR chmod (2)).\n.PP\n.I Call_Unit\nis an optional second device file name.\nTrue automatic call units use a separate device file for data and for dialing;\nthe\n.I Device\nfield specifies the data port, while the\n.I Call_unit\nfield specifies the dialing port.\nIf the\n.I Call_unit\nfield is unused, it must not be left empty.\nInsert a dummy entry as a placeholder, such as ``0'' or ``unused.''\n.PP\n.I Class\nis an integer number that\nspecifies the line baud (for dialers and direct lines) or the port number (for\nnetwork connections).\n.PP\nThe\n.I Class\nmay be preceded by a non-numeric prefix.\nThis is to differentiate among devices that have identical\n.I Caller\nand baud, but are distinctly different.\nFor example, ``1200'' could refer to all Bell 212-compatible modems,\n``V1200'' to Racal-Vadic modems, and ``C1200'' to CCITT modems,\nall at 1200 baud.\nSimilarly, ``W1200'' could denote long distance lines, while ``L1200''\ncould refer to local phone lines.\n.PP\n.I Dialer\napplies only to ACU devices. This is the \"brand\" or type of the ACU or modem.\n.TP 8\n.B DF02\nDEC DF02 or DF03 modems.\n.TP 8\n.B DF112\nDec DF112 modems. Use a\n.I Dialer\nfield of\n.B DF112T\nto use tone dialing, or\n.B DF112P\nfor pulse dialing.\n.TP 8\n.B att\nAT&T 2224 2400 baud modem.\n.TP 8\n.B cds224\nConcord Data Systems 224 2400 baud modem.\n.TP 8\n.B dn11\nDEC DN11 Unibus dialer.\n.TP 8\n.B hayes\nHayes Smartmodem 1200 and compatible autodialing modems.\nUse a\n.I Dialer\nfield of\n.B hayestone\nto use tone dialing, or\n.B hayespulse\nfor pulse dialing.\nIt is also permissible to include the letters `T' and `P' in the phone\nnumber (in\n.IR L.sys )\nto change to tone or pulse midway through dialing.\n(Note that a leading `T' or `P' will be interpreted as a dialcode!)\n.TP 8\n.B hayes2400\nHayes Smartmodem 2400 and compatible modems.\nUse a\n.I Dialer\nfield of\n.B hayes2400tone\nto use tone dialing, or\n.B hayes2400pulse\nfor pulse dialing.\n.TP 8\n.B novation\nNovation ``Smart Cat'' autodialing modem.\n.TP 8\n.B penril\nPenril Corp ``Hayes compatible'' modems (they really aren't or\nthey would use the\n.B hayes\nentry.)\n.TP 8\n.B rvmacs\nRacal-Vadic 820 dialer with 831 adapter in a MACS configuration.\n.TP 8\n.B va212\nRacal-Vadic 212 autodialing modem.\n.TP 8\n.B va811s\nRacal-Vadic 811s dialer with 831 adapter.\n.TP 8\n.B va820\nRacal-Vadic 820 dialer with 831 adapter.\n.TP 8\n.B vadic\nRacal-Vadic 3450 and 3451 series autodialing modems.\n.TP 8\n.B ventel\nVentel 212+ autodialing modem.\n.TP 8\n.B vmacs\nRacal-Vadic 811 dialer with 831 adapter in a MACS configuration.\n.PP\n.I Expect/Send\nis an optional\n.I Expect/Send\nscript for getting through a smart port selector,\nor for issuing special commands to the modem.\nThe syntax is identical to that of the Expect/Send script of\n.IR L.sys .\nThe difference is that the\n.I L-devices\nscript is used\n.I before\nthe connection is made, while the\n.I L.sys\nscript is used\n.IR after .\n.SH FILES\n/etc/uucp/L-devices\n.br\n/etc/uucp/UUAIDS/L-devices\tL-devices example\n.SH SEE ALSO\nuucp(1), uux(1), L.sys(5), uucico(8)\n"
  },
  {
    "path": "share/man/man5/L-dialcodes.5",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)L-dialcodes.5\t6.1.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH L-DIALCODES 5 \"October 22, 1996\"\n.UC 6\n.SH NAME\nL-dialcodes \\- UUCP phone number index file \n.SH DESCRIPTION\nThe\n.I L-dialcodes\nfile defines the mapping of strings from the phone number field of\n.IR L.sys (5)\nto actual phone numbers.\n.PP\nEach line in L-dialcodes has the form:\n.PP\n.nf\n\talpha_string  phone_number\n.fi\n.PP\nThe two items can be separated by any number of blanks or tabs. Lines beginning\nwith a `#' character are comments.\n.PP\nA phone number in\n.I L.sys\ncan be preceded by an arbitrary alphabetic character string; the string\nis matched against the list of\n.IR alpha_string s\nin\n.IR L-dialcodes .\nIf a match is found,\n.I phone_number\nis substituted for it. If no match is found, the string is discarded.\n.PP\n.I L-dialcodes\nis commonly used either of two ways:\n.TP 4\n(1)\nThe alphabetic strings are used as prefixes to denote area codes, zones,\nand other commonly used sequences. For example, if\n.I L-dialcodes\nincluded the following lines:\n.PP\n.nf\n\tchi\t1312\n.br\n\tmv\t1415\n.fi\n.PP\nIn\n.I L.sys\nyou could enter:\n.PP\n.nf\n\tchivax Any ACU 1200 chi5551234  ogin:--ogin: nuucp\n.br\n\tmvpyr  Any ACU 1200 mv5556001   ogin:--ogin: Uuucp\n\ninstead of\n\n\tchivax Any ACU 1200 13125551234  ogin:--ogin: nuucp\n.br\n\tmvpyr  Any ACU 1200 14155556001  ogin:--ogin: Uuucp\n.fi\n.TP 4\n(2)\nAll phone numbers are placed in\n.IR L-dialcodes ,\none for each remote site.\n.I L.sys\nthen refers to these by name. For example, if\n.I L-dialcodes\ncontains the following lines:\n.PP\n.nf\n\tchivax\t13125551234\n.br\n\tmvpyr\t14155556601\n.fi\n.PP\nthen\n.I L.sys\ncould have:\n.PP\n.nf\n\tchivax Any ACU 1200 chivax  ogin:--ogin: nuucp\n.br\n\tmvpyr  Any ACU 1200 mvpyr   ogin:--ogin: Uuucp\n.fi\n.PP\nThis scheme allows a site administrator to give users read access to the\ntable of phone numbers, while still protecting the login/password sequences\nin\n.IR L.sys .\n.SH FILES\n.nf\n.ta \\w'/etc/uucp/UUAIDS/L-dialcodes   'u\n/etc/uucp/L-dialcodes\n/etc/uucp/UUAIDS/L-dialcodes\tL-dialcodes example\n.fi\n.SH SEE ALSO\nuucp(1), uux(1), L.sys(5), uucico(8).\n"
  },
  {
    "path": "share/man/man5/L.aliases.5",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)L.aliases.5\t6.2.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH L.ALIASES 5 \"October 22, 1996\"\n.UC 6\n.SH NAME\nL.aliases \\- UUCP hostname alias file\n.SH DESCRIPTION\nThe\n.I L.aliases\nfile defines mapping (aliasing) of system names for uucp.\nThis is intended for compensating for systems that have\nchanged names, or do not provide their entire machine name\n(like most USG systems). It is also useful when a machine's name\nis not obvious or commonly misspelled.\n.PP\nEach line in\n.I L.aliases\nis of the form:\n.PP\n.nf\n\treal_name alias_name\n.fi\n.PP\nAny amount of whitespace may separate the two items.\nLines beginning with a `#' character are comments.\n.PP\nAll occurrences of\n.I alias_name\nare mapped to\n.I real_name\nby\n.IR uucico (8),\n.IR uucp (1),\nand\n.IR uux (1).\nThe mapping occurs regardless of whether the name was typed in by a user\nor provided by a remote site. An exception is the\n.B -s\noption of\n.IR uucico ;\nonly the site's real hostname (the name in\n.IR L.sys (5))\nwill be accepted there.\n.PP\nAliased system names should not be placed in\n.IR L.sys ;\nthey will not be used.\n.SH FILES\n.ta \\w'/etc/uucp/UUAIDS/L.aliases   'u\n.nr\n/etc/uucp/L.aliases\n/etc/uucp/UUAIDS/L.aliases\tL.aliases example\n.fi\n.SH SEE ALSO\nuucp(1), uux(1), L.sys(5), uucico(8)\n"
  },
  {
    "path": "share/man/man5/L.cmds.5",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)L.cmds.5\t6.1.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH L.CMDS 5 \"October 22, 1996\"\n.UC 6\n.SH NAME\nL.cmds \\- UUCP remote command permissions file\n.SH DESCRIPTION\nThe\n.I L.cmds\nfile contains a list of commands, one per line, that are permitted\nfor remote execution via\n.IR uux (1).\n.PP\nThe default search path is /bin:/usr/bin:/usr/ucb. To change the path,\ninclude anywhere in the file a line of the form:\n.PP\n.nf\n\tPATH=/bin:/usr/bin:/usr/ucb\n.fi\n.PP\nNormally, an acknowledgment is mailed back to the requesting\nsite after the command completes. If a command name is suffixed with\n.BR ,Error ,\nthen an acknowledgment will be mailed only if the command fails.\nIf the command is suffixed with\n.BR ,No ,\nthen no acknowledgment will ever be sent. (These correspond with\nthe\n.B \\-z\nand\n.B \\-n\noptions of\n.IR uux ,\nrespectively.)\n.PP\nFor most sites,\n.I L.cmds\nshould only include the lines:\n.PP\n.nf\n\trmail\n\truusend\n.fi\n.PP\nNews sites should add:\n.PP\n.nf\n\tPATH=/bin:/usr/bin:/usr/ucb:/usr/new\n\trnews,Error\n.fi\n.PP\nWhile file names supplied as arguments to\n.I uux\ncommands will be checked against the list of accessible directory trees in\n.IR USERFILE (5),\nthis check can be easily circumvented and should not be depended upon.\nIn other words, it is unwise to include any commands in\n.I L.cmds\nthat accept local file names. In particular,\n.IR sh (1)\nand\n.IR csh (1)\nare extreme risks.\n.PP\nIt is common (but hazardous) to include\n.IR uucp (1)\nin\n.IR L.cmds ;\nsee the NOTES section of\n.IR USERFILE .\n.SH FILES\n.ta \\w'/etc/uucp/UUAIDS/L.cmds   'u\n.nf\n/etc/uucp/L.cmds\n/etc/uucp/UUAIDS/L.cmds\tL.cmds example.\n.fi\n.SH SEE ALSO\nuucp(1), uux(1), USERFILE(5), uucico(8), uuxqt(8)\n"
  },
  {
    "path": "share/man/man5/L.sys.5",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)L.sys.5\t6.1.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH L.SYS 5 \"October 22, 1996\"\n.UC 6\n.SH NAME\nL.sys \\- UUCP remote host description file \n.SH DESCRIPTION\nThe\n.I L.sys\nfile is consulted by the UUCP daemon\n.IR uucico (8)\nfor information on remote systems.\n.I L.sys\nincludes the system name, appropriate times to call, phone numbers, and a \nlogin and password for the remote system.\n.I L.sys\nis thus a privileged file, owned by the UUCP Administrator;\nit is accessible only to the Administrator and to the superuser.\n.PP\nEach line in\n.I L.sys\ndescribes one connection to one remote host, and has the form:\n.PP\n.nf\nSystem  Times  Caller  Class  Device/Phone_Number  [Expect  Send]....\n.fi\n.PP\nFields can be separated by any number of blanks or tabs. Lines beginning\nwith a `#' character are comments; long lines can be continued by appending\na `\\\\' character to the end of the line.\n.PP\nThe first five fields\n.RI ( System\nthrough\n.IR Device/Phone_Number )\nspecify the hardware mechanism that is necessary to make a connection\nto a remote host, such as a modem or network.\n.I Uucico\nsearches from the top down through\n.I L.sys\nto find the desired\n.IR System ;\nit then opens the\n.IR L-devices (5)\nfile and searches for the first available device with the same\n.IR Caller ,\n.IR Class ,\nand (possibly)\n.IR Device .\n(``Available'' means that the device is ready and not being used\nfor something else.) \n.I Uucico\nattempts a connection using that device; if\nthe connection cannot be made (for example, a\ndialer gets a busy signal),\n.I uucico\ntries the next available device. If this also fails, it returns to\n.I L.sys\nto look for another line for the same\n.IR System .\nIf none is found,\n.I uucico\ngives up.\n.PP\n.I System\nis the hostname of the remote system.\nEvery machine with which this system communicates via UUCP should be listed,\nregardless of who calls whom.\nSystems not listed in\n.I L.sys\nwill not be permitted a connection.\nThe local hostname should\n.B not\nappear here for security reasons.\n.PP\n.I Times\nis a comma-separated list of the times of the day and week that \ncalls are permitted to this\n.IR System .  \n.I Times\nis most commonly used\nto restrict long distance telephone calls to those times when\nrates are lower.  List items are constructed as:\n.PP\n.nf\n\t\\fIkeyword\\fPhhmm\\fB-\\fPhhmm\\fB/\\fP\\fIgrade\\fP\\fB;\\fP\\fIretry_time\\fP\n.fi\n.PP\n.I Keyword\nis required, and must be one of:\n.TP 8\n.B Any\nAny time, any day of the week.\n.TP 8\n.B Wk\nAny weekday. In addition,\n.BR Mo ,\n.BR Tu ,\n.BR We ,\n.BR Th ,\n.BR Fr ,\n.BR Sa ,\nand\n.B Su\ncan be used for Monday through Sunday, respectively.\n.TP 8\n.B Evening\nWhen evening telephone rates are in effect, from 1700 to 0800 Monday\nthrough Friday, and all day Saturday and Sunday.\n.B Evening\nis the same as\n.BR Wk1700-0800,Sa,Su .\n.TP 8\n.B Night\nWhen nighttime telephone rates are in effect, from 2300 to 0800 Monday\nthrough Friday, all day Saturday, and from 2300 to 1700 Sunday.\n.B Night\nis the same as\n.BR Any2300-0800,Sa,Su0800-1700 .\n.TP 8\n.B NonPeak\nThis is a slight modification of \n.BR Evening .\nIt matches when the USA X.25 carriers have their lower rate period. This\nis 1800 to 0700 Monday through Friday, and all day Saturday and Sunday.\n.B NonPeak\nis the same as\n.BR Any1800-0700,Sa,Su .\n.TP 8\n.B Never\nNever call; calling into this\n.I System\nis forbidden or impossible.\nThis is intended for polled connections, where the\nremote system calls into the local machine periodically.\nThis is necessary when one of the machines is lacking\neither dial-in or dial-out modems.\n.PP\nThe optional\n.I hhmm-hhmm\nsubfield provides a time range that modifies the keyword.\n.I hhmm\nrefers to\n.I hours\nand\n.I minutes\nin 24-hour time (from 0000 to 2359).\nThe time range is permitted to \"wrap\" around midnight, and will behave in\nthe obvious way. It is invalid to follow the\n.BR Evening ,\n.BR NonPeak ,\nand\n.B Night\nkeywords with a time range.\n.PP\nThe\n.I grade\nsubfield is optional; if present, it is composed of a `/'\n(slash) and single \ncharacter denoting the\n.I grade\nof the connection, from\n.B 0\nto\n.BR 9 ,\n.B A\nto \n.BR Z ,\nor\n.B a\nto\n.BR z .\nThis specifies that only requests of grade\n.I grade\nor better will be transferred during this time.\n(The grade of a request or job is specified when it is queued by\n.I uucp\nor\n.IR uux .)\nBy convention, mail is sent at grade\n.BR C ,\nnews is sent at grade\n.BR d ,\nand uucp copies are sent at grade\n.BR n .\nUnfortunately, some sites do not follow these conventions, so it is\nnot 100% reliable.\n.PP\nThe\n.I retry_time\nsubfield is optional; it must be preceded by a `;' (semicolon) and\nspecifies the time, in minutes, before a failed connection may be\ntried again.\n(This restriction is in addition to any constraints imposed by the rest of the\n.I Time\nfield.)\nBy default, the retry time starts at 10 minutes and gradually increases\nat each failure, until after 26 tries\n.I uucico\ngives up completely (MAX RETRIES). If the retry time is too small,\n.I uucico\nmay run into MAX RETRIES too soon.\n.PP\n.I Caller\nis the type of device used:\n.TP 8\n.B ACU\nAutomatic call unit or auto-dialing modem such as the Hayes\nSmartmodem 1200 or Novation ``Smart Cat''. See\n.I L-devices\nfor a list of supported modems.\n.TP 8\n.B DIR\nDirect connect; hardwired line (usually RS-232) to a remote system.\n.TP 8\n.B MICOM\nMicom Terminal Switch.\n.TP 8\n.B PAD\nX.25 PAD connection.\n.TP 8\n.B PCP\nGTE Telenet PC Pursuit. See\n.I L-devices\nfor configuration  details.\n.TP 8\n.B SYTEK\nSytek high-speed dedicated modem port connection.\n.TP 8\n.B TCP\nBerkeley TCP/IP or 3Com UNET connection. These are mutually exclusive.\nTCP ports do\n.B not\nneed entries in\n.I L-devices\nsince all the necessary information is contained in\n.IR L.sys .\nIf several alternate ports or network connections should be tried,\nuse multiple\n.I L.sys\nentries.\n.PP\n.I Class\nis usually the speed (baud) of the device, typically 300, 1200, or\n2400 for ACU devices and 9600 for direct lines.\nValid values are device dependent, and are specified in the\n.I L\\-devices\nfile.\n.PP\nOn some devices, the baud may be preceded by a\nnon-numeric prefix.  This is used in\n.IR L\\-devices\nto distinguish among devices that have identical\n.I Caller\nand baud, but yet are distinctly different. For example, 1200\ncould refer to all Bell 212-compatible modems, V1200 to\nRacal-Vadic modems, and C1200 to CCITT modems, all at 1200 baud.\n.PP\nOn TCP connections,\n.I Class\nis the port number (an integer number) or a port name from\n.I /etc/services \nthat is used to make the connection. For standard Berkeley TCP/IP,\nUUCP normally uses port number 540.\n.PP\n.I Device/Phone_Number\nvaries based on the\n.I Caller\nfield.  For ACU devices, this is the phone number to dial.\nThe number may include: digits\n.B 0\nthrough\n.BR 9 ;\n.B #\nand\n.B *\nfor dialing those symbols on tone telephone lines;\n.B -\n(hyphen) to pause for a moment, typically two to four seconds;\n.B =\n(equal sign) to wait for a second dial tone (implemented as a pause on\nmany modems). Other characters are modem dependent; generally\nstandard telephone punctuation characters (such as the slash and\nparentheses) are ignored, although\n.I uucico\ndoes not guarantee this.\n.PP\nThe phone number can be preceded by an alphabetic\nstring; the string is indexed and converted through the\n.IR \"L\\-dialcodes\" (5)\nfile.\n.PP\nFor DIR devices, the\n.I Device/Phone_Number\nfield contains the name of the device in\n.I /dev\nthat is used to make the connection. There must be a corresponding\nline in\n.I L\\-devices\nwith identical\n.IR Caller ,\n.IR Class ,\nand\n.I Device\nfields.\n.PP\nFor TCP and other network devices,\n.I Device/Phone_Number\nholds the true network name of the remote system, which may be different\nfrom its UUCP name (although one would hope not).\n.PP\n.I Expect\nand\n.I Send\nrefer to an arbitrarily long set of strings that\nalternately specify what to\n.I expect\nand what to\n.I send\nto login to the remote system once a physical connection has\nbeen established.  A complete set of expect/send strings is referred\nto as an\n.IR \"expect/send script\" .\nThe same syntax is used in the\n.I L\\-devices\nfile to interact with the dialer prior to making a connection; there\nit is referred to as a\n.IR \"chat script\" .\nThe complete format for one\n.I expect/send\npair is:\n.PP\n.nf\n\t\\fIexpect\\fP\\fB-\\fP\\fItimeout\\fP\\fB-\\fP\\fIsend\\fP\\fB-\\fP\\fI\\\nexpect\\fP\\fB-\\fP\\fItimeout   send\\fP\n.fi\n.PP\n.I Expect\nand\n.I Send\nare character strings.\n.I Expect\nis compared against incoming text from the remote host;\n.I send\nis sent back when\n.I expect\nis matched.  By default, the\n.I send\nis followed by a `\\er' (carriage return). If the\n.I expect\nstring is not matched within\n.I timeout\nseconds (default 45), then it is assumed that the match failed.\nThe `\\fIexpect\\fP\\fB-\\fP\\fIsend\\fP\\fB-\\fP\\fIexpect\\fP' notation \nprovides a limited loop mechanism; if the first\n.I expect\nstring fails to match, then the\n.I send\nstring between the hyphens is transmitted, and\n.I uucico\nwaits for the second\n.I expect\nstring. This can be repeated indefinitely. When the last\n.I expect\nstring fails,\n.I uucico\nhangs up and logs that the connection failed. \n.PP\nThe timeout can (optionally) be specified by appending the parameter\n`\\fB~\\fP\\fInn\\fP' to the expect string, when \\fInn\\fR is the timeout\ntime in seconds.\n.PP\nBackslash escapes that may be imbedded in the\n.I expect\nor\n.I send\nstrings include:\n.PP\n.ta .5i +.8i +.8i\n.nf\n\t\\eb\tGenerate a 3/10 second BREAK.\n\t\\eb\\fIn\\fP\tWhere \\fIn\\fP is a single-digit number;\n\t\tgenerate an \\fIn\\fP/10 second BREAK.\n\t\\ec\tSuppress the \\er at the end of a \\fIsend\\fP string.\n\t\\ed\tDelay; pause for 1 second. (\\fISend\\fR only.)\n\t\\er\tCarriage Return.\n\t\\es\tSpace.\n\t\\en\tNewline.\n\t\\exxx\tWhere \\fIxxx\\fP is an octal constant;\n\t\tdenotes the corresponding ASCII character.\n.fi\n.PP\nAs a special case, an empty pair of double-quotes \\fB\"\"\\fP in the\n.I expect\nstring is interpreted as ``expect nothing''; that is, transmit\nthe\n.I send\nstring regardless of what is received. Empty double-quotes\nin the\n.I send\nstring cause a lone `\\er' (carriage return) to be sent.\n.PP\nOne of the following keywords may be substituted for the\n.I send\nstring:\n.PP\n.nf\n\tBREAK\tGenerate a 3/10 second BREAK\n\tBREAK\\fIn\\fP\tGenerate an \\fIn\\fP/10 second BREAK\n\tCR\tSend a Carriage Return (same as \"\").\n\tEOT\tSend an End-Of-Transmission character, ASCII \\e004.\n\t\tNote that this will cause most hosts to hang up.\n\tNL\tSend a Newline.\n\tPAUSE\tPause for 3 seconds.\n\tPAUSE\\fIn\\fP\tPause for \\fIn\\fR seconds.\n\tP_ODD\tUse odd parity on future send strings.\n\tP_ONE\tUse parity one on future send strings.\n\tP_EVEN\tUse even parity on future send strings. (Default)\n\tP_ZERO\tUse parity zero on future send strings.\n.fi\n.PP\nFinally, if the\n.I expect\nstring consists of the keyword\n.BR ABORT ,\nthen the string following is used to arm an abort trap. If that string\nis subsequently received any time prior to the completion of the entire\n.I expect/send\nscript, then\n.I uucico\nwill abort, just as if the\nscript had timed out. This is useful for trapping error messages from\nport selectors or front-end processors such as ``Host Unavailable'' or\n``System is Down.''\n.PP\nFor example:\n.PP\n.nf\n\t\"\"  \"\"  ogin:--ogin:  nuucp  ssword:  ufeedme\n.fi\n.PP\nThis is executed as, ``When the remote system answers,\n.I expect\nnothing.\n.I Send\na carriage return.\n.I Expect\nthe remote to transmit the string `ogin:'. If it doesn't\nwithin 45 seconds, send another carriage return.  When it finally does,\n.I send\nit the string `nuucp'.  Then\n.I expect\nthe string `ssword:'; when that is received,\n.I send\n`ufeedme'.''\n.SH FILES\n/etc/uucp/L.sys\n.br\n/etc/uucp/UUAIDS/L.sys\tL.sys example\n.SH SEE ALSO\nuucp(1), uux(1), L-devices(5), services(5), uucico(8)\n.SH BUGS\n``ABORT'' in the send/expect script is expressed ``backwards,'' that is,\nit should be written ``\n.I expect\n.BR ABORT ''\nbut instead it is ``\n.B ABORT\n.IR expect ''.\n.PP\nSeveral of the backslash escapes in the send/expect strings are confusing\nand/or different from those used by AT&T and Honey-Danber UUCP.\nFor example, `\\eb' requests\na BREAK, while practically everywhere else `\\eb' means backspace.\n`\\et' for tab and `\\ef' for formfeed are not implemented.\n`\\es' is a kludge; it would be more sensible to be able to delimit strings\nwith quotation marks.\n"
  },
  {
    "path": "share/man/man5/Makefile",
    "content": "#\n# Copyright (c) 1987 Regents of the University of California.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms are permitted\n# provided that the above copyright notice and this paragraph are\n# duplicated in all such forms and that any documentation,\n# advertising materials, and other materials related to such\n# distribution and use acknowledge that the software was developed\n# by the University of California, Berkeley.  The name of the\n# University may not be used to endorse or promote products derived\n# from this software without specific prior written permission.\n# THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n# IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n# WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n#\n#\t@(#)Makefile\t5.4.3 (2.11BSD GTE) 1996/3/20\n#\nTOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nMDIR=\t/usr/share/man/cat5\nSRCS=\tL-devices.5 L-dialcodes.5 L.aliases.5 L.cmds.5 L.sys.5 \\\n\tUSERFILE.5 a.out.5 acct.5 aliases.5 core.5 dbx.5 \\\n\tdir.5 disktab.5 dtab.5 dump.5 fs.5 fstab.5 gettytab.5 \\\n\tgroup.5 hosts.5 intro.5 map3270.5 networks.5 passwd.5 \\\n\tphones.5 plot.5 printcap.5 protocols.5 remote.5 resolver.5 \\\n\tservices.5 shells.5 stack.5 tar.5 termcap.5 tp.5 ttys.5 types.5 \\\n\tsyserrlst.5 \\\n\ttzfile.5 utmp.5 uuencode.5 vfont.5 vgrindefs.5\nOBJS=\tL-devices.0 L-dialcodes.0 L.aliases.0 L.cmds.0 L.sys.0 \\\n\tUSERFILE.0 a.out.0 acct.0 aliases.0 core.0 dbx.0 \\\n\tdir.0 disktab.0 dtab.0 dump.0 fs.0 fstab.0 gettytab.0 \\\n\tgroup.0 hosts.0 intro.0 map3270.0 networks.0 passwd.0 \\\n\tphones.0 plot.0 printcap.0 protocols.0 remote.0 resolver.0 \\\n\tservices.0 shells.0 stack.0 tar.0 termcap.0 tp.0 ttys.0 types.0 \\\n\tsyserrlst.0 \\\n\ttzfile.0 utmp.0 uuencode.0 vfont.0 vgrindefs.0\n\n.SUFFIXES: .5 .0\n\n.5.0:\n\t${MANROFF} $*.5 > $*.0\n\nall: _make_01\n\n_make_01: ${OBJS}\n\nclean: FRC\n\trm -f ${OBJS}\n\ninstall: _make_01\n\tcp ${OBJS} ${DESTDIR}${MDIR}\n\tln -f ${DESTDIR}${MDIR}/fs.0 ${DESTDIR}${MDIR}/inode.0\n\tln -f ${DESTDIR}${MDIR}/dump.0 ${DESTDIR}${MDIR}/dumpdates.0\n\tln -f ${DESTDIR}${MDIR}/utmp.0 ${DESTDIR}${MDIR}/wtmp.0\n\nFRC:\n"
  },
  {
    "path": "share/man/man5/USERFILE.5",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)USERFILE.5\t6.1.2 (2.11BSD) 1996/11/27\n.\\\"\n.TH USERFILE 5 \"November 27, 1996\"\n.UC 6\n.SH NAME\nUSERFILE \\- \\s-1UUCP\\s0 pathname permissions file\n.SH DESCRIPTION\nThe\n.I USERFILE\nfile specifies the file system directory trees that are accessible to\nlocal users and to remote systems via \\s-1UUCP\\s0.\n.PP\nEach line in\n.I USERFILE\nis of the form:\n.PP\n[\\fIloginname\\fP]\\fB,\\fP[\\fIsystem\\fP] [ \\fBc\\fP ] \\fIpathname\\fP \\c\n[\\fIpathname\\fP] [\\fIpathname\\fP]\n.PP\nThe first two items are separated by a comma; any number of spaces or\ntabs may separate the remaining items.\nLines beginning with a `#' character are comments.\nA trailing `\\e' indicates that the next line\nis a continuation of the current line. \n.PP\n.I Loginname\nis a login (from\n.IR /etc/passwd )\non the local machine.\n.PP\n.I System\nis the name of a remote machine, the same name used in\n.IR L.sys (5).\n.PP\n.I c\ndenotes the optional\n.I callback\nfield.\nIf a \\fBc\\fP appears here, a remote machine that calls in will be told\nthat callback is requested, and the conversation will be terminated.\nThe local system will then immediately call the remote host back.\n.PP\n.I Pathname\nis a pathname prefix that is permissible for this\n.I login\nand/or\n.IR system .\n.PP\nWhen\n.IR uucico (8)\nruns in master role or\n.IR uucp (1)\nor\n.IR uux (1)\nare run by local users, the permitted pathnames are those on the\nfirst line with a\n.I loginname\nthat matches the name of the user who executed the command.\nIf no such line exists, then the first line with a null (missing)\n.I loginname\nfield is used.\n(Beware:\n.I uucico\nis often run by the superuser or the \\s-1UUCP\\s0 administrator through\n.IR cron (8).)\n.PP\nWhen\n.I uucico\nruns in slave role, the permitted pathnames are those on the\nfirst line with a\n.I system\nfield that matches the hostname of the remote machine.\nIf no such line exists, then the first line with a null (missing)\n.I system\nfield is used.\n.PP\n.IR Uuxqt (8)\nworks differently; it knows neither a login name nor a hostname.\nIt accepts the pathnames on the first line that has a null\n.I system \nfield.\n(This is the same line that is used by\n.I uucico\nwhen it cannot match the remote machine's hostname.)\n.PP\nA line with both\n.I loginname\nand\n.I system\nnull, for example\n.IP\n.B ,  /usr/spool/uucppublic\n.PP\t\ncan be used to conveniently specify the paths for both \"no match\" cases\nif lines earlier in\n.I USERFILE\ndid not define them.\n(This differs from older Berkeley and all USG versions, where each case\nmust be individually specified.\nIf neither case is defined earlier,\na \"null\" line only defines the \"unknown login\" case.)\n.PP\nTo correctly process\n.I loginname\non systems that assign several logins per UID,\nthe following strategy is used to determine the current\n.IR loginname :\n.TP\n1)\nIf the process is attached to a terminal, a login entry exists in\n.IR /var/run/utmp ,\nand the UID for the\n.I utmp\nname matches the current real UID, then\n.IR loginname\nis set to the\n.I utmp\nname.\n.TP\n2)\nIf the\n.B USER\nenvironment variable is defined and the UID for this name matches\nthe current real UID, then\n.IR loginname\nis set to the name in\n.BR USER .\n.TP\n3)\nIf both of the above fail, call\n.IR getpwuid (3)\nto fetch the first name in\n.I /etc/passwd\nthat matches the real UID.\n.TP\n4)\nIf all of the above fail, the utility aborts.\n.SH FILES\n.ta \\w'/etc/uucp/UUAIDS/USERFILE   'u\n.nf\n/etc/uucp/USERFILE\n/etc/uucp/UUAIDS/USERFILE\tUSERFILE example\n.fi\n.SH SEE ALSO\nuucp(1), uux(1), L.cmds(5), L.sys(5), uucico(8), uuxqt(8)\n.SH NOTES\nThe \\s-1UUCP\\s0 utilities\n.RI ( uucico ,\n.IR uucp ,\n.IR uux ,\nand\n.IR uuxqt )\nalways have access to the \\s-1UUCP\\s0 spool files in\n.IR /usr/spool/uucp ,\nregardless of pathnames in\n.IR USERFILE .\n.PP\nIf\n.B uucp\nis listed in\n.IR L.cmds (5),\nthen a remote system will execute\n.I uucp \non the local system with the\n.I USERFILE\nprivileges for its\n.IR login ,\nnot its hostname.\n.PP\n.I Uucico\nfreely switches between master and slave roles during the course of a\nconversation, regardless of the role it was started with.\nThis affects how\n.I USERFILE\nis interpreted.\n.SH WARNING\n.I USERFILE\nrestricts access only on strings that the \\s-1UUCP\\s0 utilities identify\nas being pathnames.\nIf the wrong holes are left in other \\s-1UUCP\\s0 control files (notably\n.IR L.cmds ),\nit can be easy for an intruder to open files anywhere in the file system.\nArguments to\n.IR uucp (1)\nare safe, since it assumes all of its non-option arguments are files.\n.IR Uux (1)\ncannot make such assumptions; hence, it is more dangerous.\n.SH BUGS\nThe\n.I \"\\s-1UUCP\\s0 Implementation Description\"\nexplicitly states that all remote login names must be listed in\n.IR USERFILE .\nThis requirement is not enforced by Berkeley \\s-1UUCP\\s0, although it is\nby USG \\s-1UUCP\\s0.\n.PP\nEarly versions of 4.2BSD\n.IR uuxqt (8)\nerroneously check \\s-1UUCP\\s0 spool files against the\n.I USERFILE\npathname permissions.\nHence, on these systems it is necessary to specify\n.I /usr/spool/uucp\nas a valid path on the\n.I USERFILE\nline used by\n.IR uuxqt .\nOtherwise, all\n.IR uux (1)\nrequests are rejected with a \"PERMISSION DENIED\" message.\n"
  },
  {
    "path": "share/man/man5/a.out.5",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)a.out.5\t2.4 (2.11BSD GTE) 1/9/94\n.\\\"\n.TH A.OUT 5 \"January 9, 1994\"\n.UC 2\n.SH NAME\na.out \\- assembler and link editor output\n.SH SYNOPSIS\n.B #include <a.out.h>\n.SH DESCRIPTION\n.I A.out\nis the output file of the assembler\n.IR as (1)\nand the link editor\n.IR ld (1).\nBoth programs make\n.I a.out\nexecutable if there were no\nerrors and no unresolved external references.\nLayout information as given in the include file for the PDP11 is:\n.PP\n.nf\n.ta \\w'#define  'u +\\w'unsigned int  'u +\\w'ov_siz[NOVL]  'u\n/*\n * Header prepended to each a.out file.\n */\nstruct\texec {\n\tint\ta_magic;\t/* magic number */\n\tunsigned int\ta_text;\t\t/* size of text segment */\n\tunsigned int\ta_data;\t\t/* size of initialized data */\n\tunsigned int\ta_bss;\t\t/* size of uninitialized data */\n\tunsigned int\ta_syms;\t\t/* size of symbol table */\n\tunsigned int\ta_entry; \t/* entry point */\n\tunsigned int\ta_unused;\t/* not used */\n\tunsigned int\ta_flag; \t/* relocation info stripped */\n};\n\n#define\tNOVL\t15\t\t/* number of overlays */\nstruct\tovlhdr {\n\tint\tmax_ovl;\t/* maximum overlay size */\n\tunsigned int\tov_siz[NOVL];\t/* size of i'th overlay */\n};\n\nstruct\txexec {\n\tstruct exec e;\n\tstruct ovlhdr o;\n};\n\n#define\tA_MAGIC1\t0407\t/* normal */\n#define\tA_MAGIC2\t0410\t/* read-only text */\n#define\tA_MAGIC3\t0411\t/* separated I&D */\n#define\tA_MAGIC4\t0405\t/* overlay */\n#define\tA_MAGIC5\t0430\t/* auto-overlay (nonseparate) */\n#define\tA_MAGIC6\t0431\t/* auto-overlay (separate) */\n\n/*\n * Macros which take exec structures as arguments and tell whether\n * the file has a reasonable magic number or offset to text.\n */\n#define\tN_BADMAG(x) \\e\n\t(((x).a_magic)!=A_MAGIC1 && ((x).a_magic)!=A_MAGIC2 && \\e\n\t((x).a_magic)!=A_MAGIC3 && ((x).a_magic)!=A_MAGIC4 && \\e\n\t((x).a_magic)!=A_MAGIC5 && ((x).a_magic)!=A_MAGIC6)\n\n#define\tN_TXTOFF(x) \\e\n\t((x).a_magic==A_MAGIC5 || (x).a_magic==A_MAGIC6 ? \\e\n\tsizeof(struct ovlhdr) + sizeof(struct exec) : sizeof(struct exec))\n\n/*\n * The following were added as part of the new object file format.  They\n * call functions because calculating the sums of overlay sizes was too\n * messy (and verbose) to do 'inline'.\n *\n * NOTE: if the magic number is that of an overlaid object the program\n * must pass an extended header ('xexec') as the argument.\n*/\n\noff_t\tn_stroff(), n_symoff(), n_datoff(), n_dreloc(), n_treloc();\n\n#define\tN_STROFF(e) (n_stroff(&e))\n#define\tN_SYMOFF(e) (n_symoff(&e))\n#define\tN_DATOFF(e) (n_datoff(&e))\n#define\tN_DRELOC(e) (n_dreloc(&e))\n#define\tN_TRELOC(e) (n_treloc(&e))\n.fi\n.PP\nThe file has five sections:\na header, the program text and data,\nrelocation information, a symbol table and a strings table (in that order).\nThe last three may be omitted\nif the program was loaded\nwith the `\\-s' option\nof\n.I ld\nor if the symbols and relocation have been\nremoved by\n.IR strip (1).\n.PP\nIn the header the sizes of each section are given in bytes, but are even.\nThe size of the header is not included in any of the other sizes.\n.PP\nWhen an\n.I a.out\nfile is executed, three or four logical segments are\nset up: the text segment, a possible text overlay segment, the data segment\n(with uninitialized data, which starts off as all 0, following\ninitialized),\nand a stack.\nThe text segment begins at 0\nin the core image; the header is not loaded.\n.PP\n.IR \"Non-overlaid objects\" :\nIf the magic number in the header is A_MAGIC1 (0407),\nit indicates that the text\nsegment is not to be write-protected and shared,\nso the data segment is immediately contiguous\nwith the text segment.\nThis is the oldest kind of executable program and is the default;\nit should not be used for production binaries.\nIf the magic number is A_MAGIC2 (0410),\nthe data segment begins at the first 0 mod 8K byte\nboundary following the text segment,\nand the text segment is not writable by the program;\nif other processes are executing the same file,\nthey will share the text segment.\nIf the magic number is A_MAGIC3 (0411),\nthe text segment is again pure, write-protected, and shared,\nand moreover instruction and data space are separated;\nthe text and data segment both begin at location 0.\nThis format is only runnable on processors which support\nseparate instruction and data space but can provide significantly\nmore data space than an A_MAGIC2 format of the same object.\n.PP\n.I \"Text replacement objects\" :\nIf the magic number is A_MAGIC4 (0405), the text segment\nis overlaid on an existing non-overlaid pure (A_MAGIC2 or A_MAGIC3)\nor text replacement (A_MAGIC4)\ntext segment and the existing data segment is preserved.\nThe text segment of the previous memory image must be the same size as\nthat of the text replacement object being loaded.\nThere is, unfortunately, no loader support to help achieve this requirement.\nThe text replacement format is useful for objects which need a large\namount of data space on non-separate I&D processors.\n.PP\n.I \"Overlaid objects\" :\nIf the magic number is A_MAGIC5 (0430), a base text segment is\nwrite-protected and shared and is followed by a text overlay segment.\nThere are a maximum of NOVL overlays, all pure and shared.\nThe base segment runs from 0 to txtsiz.\nThe overlay region begins at the next 0 mod 8k byte boundary,\nwhich is as large as the largest overlay.\nWhen running, any one of the overlays can be mapped into this region.\nThe data segment begins at the following 0 mod 8k byte boundary.\nIf the magic number is A_MAGIC6 (0431), the situation is the same as for\ntype A_MAGIC5 except that instruction and data spaces are separated\nand both begin at location 0.\nAs with the A_MAGIC3 format, an\n.I a.out\nin A_MAGIC6 format can only be run on a processor which supports\nseparate I&D, but again can provide significantly more data space\nthan A_MAGIC5 format.\nBoth A_MAGIC5 and A_MAGIC6 executable files have a second header between\nthe normal a.out header and the start of the text image;\nit contains the maximum overlay size and the sizes of each of the overlays.\nThe text images of the overlays follow the text in the object file.\n.PP\nThe stack segment will occupy the highest possible locations\nin the core image: growing downwards from 0177776(8).\nThe stack segment is automatically extended as required.\nThe data segment is only extended as requested by\n.IR brk (2).\n.PP\nThe include file \\fBa.out.h\\fP defines \\fI_AOUT_INCLUDE_\\fP, the include\nfile \\fBnlist.h\\fP does not.  This permits compile time initialization\nof the \\fIn_name\\fP field for programs that are not looking at the executable\nheader.\n.sp\nThe layout of a symbol table entry and the principal flag values\nthat distinguish symbol types are given in the include file as follows:\n.PP\n.nf\n.ta \\w'#define  'u +\\w'unsigned int  'u +\\w'n_name[8]  'u\n.PP\nstruct\tnlist {\n#ifdef\t_AOUT_INCLUDE_\n\tunion {\n\t\tchar *n_name;\t/* In memory address of symbol name */\n\t\toff_t n_strx;\t/* String table offset (file) */\n\t} n_un;\n#else\n\tchar\t*n_name;\t/* symbol name (in memory) */\n#endif\n\tu_char\tn_type;\t\t/* Type of symbol - see below */\n\tchar\tn_ovly;\t\t/* Overlay number */\n\tu_int\tn_value;\t/* Symbol value */\n};\n\n/*\n * Simple values for n_type.\n */\n#define\tN_UNDF\t0x0\t\t/* undefined */\n#define\tN_ABS\t0x1\t\t/* absolute */\n#define\tN_TEXT\t0x2\t\t/* text symbol */\n#define\tN_DATA\t0x3\t\t/* data symbol */\n#define\tN_BSS\t0x4\t\t/* bss symbol */\n#define\tN_REG\t0x14\t\t/* register name */\n#define\tN_FN\t0x1f\t\t/* file name symbol */\n\n#define\tN_EXT\t0x20\t\t/* external bit, or'ed in */\n#define\tN_TYPE\t0x1f\t\t/* mask for all the type bits */\n\n/*\n * Format for namelist values.\n */\n#define\tN_FORMAT\t\"%06o\"\n.fi\n.PP\nIf a symbol's type is undefined external,\nand the value field is non-zero,\nthe symbol is interpreted by the loader\n.I ld\nas\nthe name of a common region\nwhose size is indicated by the value of the\nsymbol.\n.PP\nThe value of a word in the text or data which is not\na portion of a reference to an undefined external symbol\nis exactly that value which will appear in memory\nwhen the file is executed.\nIf a word in the text or data\ninvolves a reference to an undefined external symbol,\nas indicated by the relocation information,\nthen the value stored in the file\nis an offset from the associated external symbol.\nWhen the file is processed by the\nlink editor and the external symbol becomes\ndefined, the value of the symbol will\nbe added into the word in the file.\n.PP\nIf relocation\ninformation is present, it amounts to one word per\nword of program text or initialized data.\nThere is no relocation information if the `relocation info stripped'\nflag in the header is on.\nAutomatic-overlay (A_MAGIC5 and A_MAGIC6) files do not contain relocation\ninformation.\n.PP\nBits 1-3 of a relocation word indicate the segment referred\nto by the text or data word associated with the relocation\nword:\n.TP\n000\nabsolute number\n.br\n.ns\n.TP\n002\nreference to text segment\n.br\n.ns\n.TP\n004\nreference to initialized data\n.br\n.ns\n.TP\n006\nreference to uninitialized data (bss)\n.br\n.ns\n.TP\n010\nreference to undefined external symbol\n.PP\nBit 0 of the relocation word indicates, if 1,\nthat the\nreference is relative to the pc (e.g. `clr x');\nif 0,\nthat\nthe reference is to the actual symbol (e.g.,\n`clr *$x').\n.PP\nThe remainder of the relocation word (bits 15-4)\ncontains a symbol number in the case of external\nreferences, and is unused otherwise.\n.PP\nThe string table begins with a longword containing the length of the string\ntable (including the longword itself).  All strings are null terminated.\n.PP\nThe first symbol is numbered 0, the second 1, etc.\n.SH \"SEE ALSO\"\nas(1), ld(1), nm(1), strip(1), nlist(3)\n.SH BUGS\nThe current implementation places a maximum length of 32 characters for \nsymbol names in\n.I a.out\nfiles.  This is (relatively) easily raised with the caveat that the linker\nand other programs which look at symbol tables will slow down even more\nthan they already have.  \n.PP\nThe\n.I 4BSD a.out\nformat has been implemented. This involved modifying the first phase of\nthe C compiler\n.RI ( /lib/c0 ),\nthe assembler\n.RI ( /bin/as ),\nthe debugger\n.RI adb (1), \nthe linker\n.RI ld (1),\nand then simply porting the 4.3BSD/Net\\-2\n.IR ar (1),\n.IR nm (1),\n.IR ranlib (1),\n.IR strip \"(1) and\"\n.IR nlist (3).\n.PP\nAs part of this effort the include file \\fIshort_names.h\\fP has gone away.\n\n"
  },
  {
    "path": "share/man/man5/acct.5",
    "content": ".\\\"\t@(#)acct.5\t6.2 (Berkeley) 5/19/86\n.\\\"\n.TH ACCT 5 \"May 19, 1986\"\n.AT 3\n.SH NAME\nacct \\- execution accounting file\n.SH SYNOPSIS\n.B #include <sys/acct.h>\n.SH DESCRIPTION\nThe\n.IR acct (2)\nsystem call arranges for entries to be made in an accounting file\nfor each process that terminates.\nThe accounting file is a sequence of entries whose layout,\nas defined by the include file is:\n.PP\n.nf\n.ta \\w'typedef 'u +\\w'ACOMPAT  'u +\\w'ac_comm[10];   'u\n.so /usr/include/sys/acct.h\n.fi\n.PP\nIf the process was created by an\n.IR execve (2),\nthe first 10 characters of the filename appear in\n.I ac_comm.\nThe accounting flag contains bits indicating whether\n.IR execve (2)\nwas ever accomplished, and whether the process ever had super-user privileges.\n.SH SEE ALSO\nacct(2), execve(2), sa(8)\n"
  },
  {
    "path": "share/man/man5/aliases.5",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)aliases.5\t6.1.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH ALIASES 5 \"October 22, 1996\"\n.UC 4\n.SH NAME\naliases \\- aliases file for sendmail\n.SH SYNOPSIS\n.B /etc/aliases\n.SH DESCRIPTION\nThis file describes user id aliases used by\n.I /usr/sbin/sendmail.\nIt is formatted as a series of lines of the form\n.in +0.5i\nname: name_1, name2, name_3, . . .\n.in\nThe\n.I name\nis the name to alias, and the\n.I name_n\nare the aliases for that name.\nLines beginning with white space are continuation lines.\nLines beginning with `\\|#\\|' are comments.\n.PP\nAliasing occurs only on local names.\nLoops can not occur, since no message will be sent to any person more than once.\n.LP\nAfter aliasing has been done, local and valid recipients who have a\n``.forward'' file in their home directory have messages forwarded to the\nlist of users defined in that file.\n.PP\nThis is only the raw data file; the actual aliasing information is\nplaced into a binary format in the files\n.I /etc/aliases.dir\nand\n.I /etc/aliases.pag\nusing the program\n.IR newaliases (1).\nA\n.I newaliases\ncommand should be executed each time the aliases file is changed for the\nchange to take effect.\n.SH \"SEE  ALSO\"\nnewaliases(1), dbm(3X), sendmail(8)\n.br\nSENDMAIL Installation and Operation Guide.\n.br\nSENDMAIL An Internetwork Mail Router.\n.SH BUGS\nBecause of restrictions in\n.IR dbm (3X)\na single alias cannot contain more than about 1000 bytes of information.\nYou can get longer aliases by ``chaining''; that is, make the last name in\nthe alias be a dummy name which is a continuation alias.\n"
  },
  {
    "path": "share/man/man5/core.5",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)core.5\t2.3 (Berkeley) 1/26/87\n.\\\"\n.TH CORE 5 \"January 26, 1987\"\n.UC 2\n.SH NAME\ncore \\- format of memory image file\n.SH SYNOPSIS\n.B #include <sys/param.h>\n.SH DESCRIPTION\nThe UNIX System writes out a memory image of a terminated\nprocess when any of various errors occur.  See\n.IR sigvec (2)\nfor the list of reasons; the most common are memory violations, illegal\ninstructions, bus errors, and user-generated quit signals.\nThe memory image is called `core' and is written in the process's\nworking directory (provided it can be; normal access controls apply).\n.PP\nThe core file consists of the\n.I u.\narea, whose size (in 64 byte `clicks') is\ndefined by the USIZE manifest in the\n.RI < sys/param.h >\nfile.  The \n.I u.\narea starts with a \n.I user\nstructure as given in\n.RI < sys/user.h >.\nThe rest of the\n.I u.\narea consists of the kernel stack for the terminated process which includes\n(among other things) the processor registers at the time of the fault;\nsee the system listings for the format of this area.\nThe remainder of the core file consists first of the data pages and then\nthe stack pages of the process image.\nThe amount of data space image in the core file is given (in clicks) by the\nvariable\n.I u_dsize\nin the\n.I u.\narea.\nIf the text segment was not write-only and and shared it is included\nas the first\n.I etext\nbytes of the data image where\n.I etext\nis taken from the symbol table of the object file which generated the\nmemory image.\nThe amount of stack image in the core file is given (in clicks) by the\nvariable \n.I u_ssize\nin the \n.I u.\narea.\n.PP\nIn general the debugger\n.IR adb (1)\nis sufficient to deal with core images.\n.SH \"SEE ALSO\"\nadb(1), sigvec(2), stack(5)\n"
  },
  {
    "path": "share/man/man5/dbx.5",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)dbx.5\t6.2 (Berkeley) 1/12/86\n.\\\"\n.TH DBX 5 \"January 12, 1986\"\n.UC 6\n.SH NAME\ndbx \\- dbx symbol table information\n.SH DESCRIPTION\nThe compiler symbol information generated\nfor \\fIdbx\\fP(1) uses the same structure\nas described in \\fIstab\\fP(5), with additional type and scope information\nappended to a symbol's name.\nThe assembler directive used to describe symbol information\nhas the following format:\n.sp 1\n.ti +8n\n\\fBstabs\\fR ``\\fIstring\\fP'',\\fIkind\\fP,0,\\fIsize\\fP,\\fIvalue\\fP\n.PP\n\\fIString\\fR contains the name, source language type, and scope of the symbol,\n\\fIkind\\fR specifies the memory class\n(e.g., external, static, parameter, local, register), and\n\\fIsize\\fR specifies the byte size of the object, if relevant.\nThe third field (0 above) is unused.\nFor a global variable or a type, \\fIvalue\\fR is unused;\nfor a local variable or parameter, it is the offset from the frame pointer,\nfor a register variable, it is the associated register number.\n.PP\nThe different kinds of stab entries are interpreted by dbx as follows:\n.IP N_GSYM 10\nThe symbol is a global variable (e.g., .comm variable).\nThe variable's address can be found from the corresponding\nld(1) symbol entry, thus the value field for N_GSYM symbols is ignored.\nFor example, a global variable ``x'' will have both an N_GSYM entry and\nan \\fIld\\fP(1) entry (e.g., N_BSS + N_EXT).\nSee \\fIa.out\\fP(5) for details about these other entries.\nof \n.IP N_FUN\nThe symbol is a procedure or function.\nThe size field contains the line number of the entry point.\nThe value field contains the address of the entry point (in the text segment).\n.IP N_STSYM\nThe symbol is a statically allocated variable for which\nan initial value has been specified.\nThe value field contains the address of the variable (in the data segment).\n.IP N_LCSYM\nThe symbol is statically allocated, but not initialized.\n.IP N_RSYM\nThe symbol is a register variable whose value is kept in the register\ndenoted by the value field.\n.IP N_PSYM\nThe symbol is a parameter whose value is pushed on the stack before the call.\nThe value field contains the offset from the argument base pointer\n(on the VAX, the ap register).\n.IP N_LSYM\nThe symbol is a local variable whose value is stored in the most recently\ndefined procedure's stack frame.\nThe value is the (often negative) offset from the frame pointer\n(on the VAX, the fp register).\n.IP \"N_PC, N_MOD2\"\nThe symbol defines separate compilation information\nfor pre-linking checking for Berkeley Pascal and DEC Modula-2 programs\nrespectively.\nFor Pascal, the value field contains the line number\nthat the symbol is defined on.\nThe value field is not used for Modula-2.\n.PP\nMost of the source level information about a symbol\nis stored in the string field of the stab entry.\nSince strings are kept in a separate string table in the a.out file,\nthey can be arbitrarily long.\nThus there are no restrictions on the kind or length of information\nin the string field, and it was not necessary\nto modify the assembler or loader when extending or modifying\nthe format of this information.\n.sp\n.PP\nBelow is a grammar describing the syntax of the symbol string.\nExcept in the case of a constant whose value is a string,\nthere are no blanks in a symbol string.\n.nf\n.ta 1i 2i 3i 4i 5i 6i 7i \n.sp 1\nNAME:\t[a-zA-Z_][a-zA-Z_0-9]*\nINTEGER:\t[-][0-9][0-9]*\nREAL:\t[+-][0-9]*(\\.[0-9][0-9]*|)([eE]([+-]|)[0-9][0-9]*|)\nSTRING:\t``.*''\nBSTRING:\t.*\n\nString:\n    NAME `:' Class\n    `:' Class\n\nClass:\n    `c' `=' Constant `;'\n    Variable\n    Procedure\n    Parameter\n    NamedType\n    `X' ExportInfo\t-- export or import information (for N_MOD2 only)\n\nConstant:\n    `i' INTEGER\n    `r' REAL\n    `c' OrdValue\n    `b' OrdValue\n    `s' STRING\n    `e' TypeId `,' OrdValue\n    `S' TypeId `,' NumElements `,' NumBits `,' BSTRING\n\nOrdValue:\n    INTEGER\n\nNumElements:\n    INTEGER\n\nNumBits:\n    INTEGER\n\nVariable:\n    TypeId\t-- local variable of type TypeId\n    `r' TypeId\t-- register variable of type TypeId\n    `S' TypeId\t-- module variable of type TypeId (static global in C)\n    `V' TypeId\t-- own variable of type TypeId (static local in C)\n    `G' TypeId\t-- global variable of type TypeId\n\nProcedure:\n    Proc\t\t-- top level procedure\n    Proc `,' NAME `,' NAME\t-- local to first NAME,\n\t\t-- second NAME is corresponding ld symbol\n\n.ne 8\nProc:\n    `P'\t-- global procedure\n    `Q'\t-- local procedure (static in C)\n    `I'\t-- internal procedure (different calling sequence)\n    `F' TypeId\t-- function returning type TypeId\n    `f' TypeId\t-- local function\n    `J' TypeId\t-- internal function\n\nParameter:\n    `p' TypeId\t-- value parameter of type TypeId\n    `v' TypeId\t-- reference parameter of type TypeId\n\nNamedType:\n    `t' TypeId\t-- type name for type TypeId\n    `T' TypeId\t-- C structure tag name for struct TypeId\n\nTypeId:\n    INTEGER\t\t-- Unique (per compilation) number of type\n    INTEGER `=' TypeDef\t-- Definition of type number\n    INTEGER `=' TypeAttrs TypeDef\n\n--\n-- Type attributes are extra information associated with a type,\n-- such as alignment constraints or pointer checking semantics.\n-- Dbx interprets some of these, but will ignore rather than complain\n-- about any it does not recognize.  Therefore this is a way to add\n-- extra information for pre-linking checking.\n--\nTypeAttrs:\n    `@' TypeAttrList `;'\n\nTypeAttrList:\n    TypeAttrList `,' TypeAttr\n    TypeAttr\n\nTypeAttr:\n    `a' INTEGER\t-- align boundary\n    `s' INTEGER\t-- size in bits\n    `p' INTEGER\t-- pointer class (e.g., checking)\n    BSTRING\t\t-- something else\n\nTypeDef:\n    INTEGER\n    Subrange\n    Array\n    Record\n    `e' EnumList `;'\t-- enumeration\n    `*' TypeId\t\t-- pointer to TypeId\n    `S' TypeId\t\t-- set of TypeId\n    `d' TypeId\t\t-- file of TypeId\n    ProcedureType\n    `i' NAME `:' NAME `;'\t-- imported type ModuleName:Name\n    `o' NAME `;'\t\t-- opaque type\n    `i' NAME `:' NAME `,' TypeId `;'\n    `o' NAME `,' TypeId `;'\n\nSubrange:\n    `r' TypeId `;' INTEGER `;' INTEGER\n\nArray:\n    `a' TypeId `;' TypeId\t-- array [TypeId] of TypeId\n    `A' TypeId\t\t-- open array of TypeId\n    `D' INTEGER `,' TypeId\t-- N-dim. dynamic array\n    `E' INTEGER `,' TypeId\t-- N-dim. subarray\n\nProcedureType:\n    `f' TypeId `;'\t\t-- C function type\n    `f' TypeId `,' NumParams `;' TParamList `;'\n    `p' NumParams `;' TParamList `;'\n\nNumParams:\n    INTEGER\n\nRecord:\n    `s' ByteSize FieldList `;'\t-- structure/record\n    `u' ByteSize FieldList `;'\t-- C union\n\nByteSize:\n    INTEGER\n\nFieldList :\n    Field\n    FieldList Field\n\nField:\n    NAME `:' TypeId `,' BitOffset `,' BitSize `;'\n\nBitSize:\n    INTEGER\n\nBitOffset:\n    INTEGER\n\nEnumList:\n    Enum\n    EnumList Enum\n\nEnum:\n    NAME `:' OrdValue `,'\n\nParamList:\n    Param\n    ParamList Param\n\nParam:\n    NAME `:' TypeId `,' PassBy `;'\n\nPassBy:\n    INTEGER\n\nTParam:\n    TypeId `,' PassBy `;'\n\nTParamList :\n    TParam\n    TParamList TParam\n\nExport:\n    INTEGER ExportInfo\n\nExportInfo:\n    `t' TypeId\n    `f' TypeId `,' NumParams `;' ParamList `;'\n    `p' NumParams `;' ParamList `;'\n    `v' TypeId\n    `c' `=' Constant\n\n.fi\n.PP\nA `?' indicates that the symbol information is continued in\nthe next stab entry.\nThis directive can only occur where a `;' would otherwise\nseparate the fields of a record or constants in an enumeration.\nIt is useful when the number of elements in one of these lists\nis large.\n.SH \"SEE ALSO\"\ndbx(1), stab(5), a.out(5)\n"
  },
  {
    "path": "share/man/man5/dir.5",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)dir.5\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH DIR 5  \"May 15, 1985\"\n.UC 5\n.SH NAME\ndir \\- format of directories\n.SH SYNOPSIS\n.B #include <sys/types.h>\n.br\n.B #include <sys/dir.h>\n.SH DESCRIPTION\nA directory behaves exactly like an ordinary file, save that no\nuser may write into a directory.\nThe fact that a file is a directory is indicated by\na bit in the flag word of its i-node entry; see\n.IR fs (5).\nThe structure of a directory entry as given in the include file is:\n.RS\n.ta 8n +10n +10n\n.PP\n.nf\n/*\n * A directory consists of some number of blocks of DIRBLKSIZ\n * bytes, where DIRBLKSIZ is chosen such that it can be transferred\n * to disk in a single atomic operation (e.g. 512 bytes on most machines).\n *\n * Each DIRBLKSIZ byte block contains some number of directory entry\n * structures, which are of variable length.  Each directory entry has\n * a struct direct at the front of it, containing its inode number,\n * the length of the entry, and the length of the name contained in\n * the entry.  These are followed by the name padded to a 4 byte boundary\n * with null bytes.  All names are guaranteed null terminated.\n * The maximum length of a name in a directory is MAXNAMLEN.\n *\n * The macro DIRSIZ(dp) gives the amount of space required to represent\n * a directory entry.  Free space in a directory is represented by\n * entries which have dp->d_reclen > DIRSIZ(dp).  All DIRBLKSIZ bytes\n * in a directory block are claimed by the directory entries.  This\n * usually results in the last entry in a directory having a large\n * dp->d_reclen.  When entries are deleted from a directory, the\n * space is returned to the previous entry in the same directory\n * block by increasing its dp->d_reclen.  If the first entry of\n * a directory block is free, then its dp->d_ino is set to 0.\n * Entries other than the first in a directory do not normally have\n * dp->d_ino set to 0.\n */\n\n#define\tDIRBLKSIZ 512\n\n#define MAXNAMLEN 63\n\n/*\n * The DIRSIZ macro gives the minimum record length which will hold\n * the directory entry.  This requires the amount of space in struct direct\n * without the d_name field, plus enough space for the name with a terminating\n * null byte (dp->d_namlen+1), rounded up to a 4 byte boundary.\n */\n#undef DIRSIZ\n#define DIRSIZ(dp) \\e\n    ((((sizeof (struct direct) - (MAXNAMLEN+1)) + (dp)->d_namlen+1) + 3) &~ 3)\n\nstruct\tdirect {\n\tino_t\td_ino;\n\tshort\td_reclen;\n\tshort\td_namlen;\n\tchar\td_name[MAXNAMLEN + 1];\n\t/* typically shorter */\n};\n\nstruct _dirdesc {\n\tint\tdd_fd;\n\tlong\tdd_loc;\n\tlong\tdd_size;\n\tchar\tdd_buf[DIRBLKSIZ];\n};\n.fi\n.RE\n.PP\nBy convention, the first two entries in each directory\nare for `.' and `..'.  The first is an entry for the\ndirectory itself.  The second is for the parent directory.\nThe meaning of `..' is modified for the root directory\nof the master file system (\\*(lq/\\*(rq),\nwhere `..' has the same meaning as `.'.\n.SH \"SEE ALSO\"\nfs(5)\n.SH BUGS\nThe 63 character MAXNAMLEN value is shorter than the 255 characters\nallowed by 4BSD.  This could lead to file name\nportability problems in unusual circumstances.\n.PP\nThe disk format of directories is only slightly different from \nthe 4BSD directory format, the inode number is of type ino_t\nrather than u_long\nto reduce the amount of 32 bit arithmetic in the kernel.\n"
  },
  {
    "path": "share/man/man5/disktab.5",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)disktab.5\t6.4 (Berkeley) 5/17/86\n.\\\"\n.TH DISKTAB 5 \"May 17, 1986\"\n.UC 5\n.SH NAME\ndisktab \\- disk description file\n.SH SYNOPSIS\n.B #include <disktab.h>\n.SH DESCRIPTION\n.I Disktab\nis a simple date base which describes disk geometries and\ndisk partition characteristics.  The format is patterned\nafter the\n.IR termcap (5)\nterminal data base.  Entries in \n.I disktab\nconsist of a number of `:' separated fields.  The\nfirst entry for each disk gives the names which are\nknown for the disk, separated by `|' characters.  The\nlast name given should be a long name fully identifying\nthe disk. \n.PP\nThe following list indicates the normal values\nstored for each disk entry.\n.nf\n\n.ta \\w'Name  'u +\\w'Type  'u\n\\fBName\tType\tDescription\\fP\nns\tnum\tNumber of sectors per track\nnt\tnum\tNumber of tracks per cylinder\nnc\tnum\tTotal number of cylinders on the disk\nb0\tstr\tFilename of block zero primary bootstrap for device\nba\tnum\tBlock size for partition `a' (bytes)\nbd\tnum\tBlock size for partition `d' (bytes)\nbe\tnum\tBlock size for partition `e' (bytes)\nbf\tnum\tBlock size for partition `f' (bytes)\nbg\tnum\tBlock size for partition `g' (bytes)\nbh\tnum\tBlock size for partition `h' (bytes)\nfa\tnum\tFragment size for partition `a' (bytes)\nfd\tnum\tFragment size for partition `d' (bytes)\nfe\tnum\tFragment size for partition `e' (bytes)\nff\tnum\tFragment size for partition `f' (bytes)\nfg\tnum\tFragment size for partition `g' (bytes)\nfh\tnum\tFragment size for partition `h' (bytes)\npa\tnum\tSize of partition `a' in sectors\npb\tnum\tSize of partition `b' in sectors\npc\tnum\tSize of partition `c' in sectors\npd\tnum\tSize of partition `d' in sectors\npe\tnum\tSize of partition `e' in sectors\npf\tnum\tSize of partition `f' in sectors\npg\tnum\tSize of partition `g' in sectors\nph\tnum\tSize of partition `h' in sectors\nse\tnum\tSector size in bytes (default 512)\nsf\tbool\tsupports bad144-style bad sector forwarding\nso\tbool\tpartition offsets in sectors\nty\tstr\tType of disk (e.g. removable, winchester)\n.fi\n.PP\n.I Disktab\nentries may be automatically generated with the\n.I diskpart\nprogram.\n.SH FILES\n/etc/disktab\n.SH \"SEE ALSO\"\nnewfs(8), diskpart(8), getdiskbyname(3)\n.SH BUGS\nThis file shouldn't exist, the information should be\nstored on each disk pack.\n"
  },
  {
    "path": "share/man/man5/dtab.5",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)dtab.5\t2.3 (Berkeley) 1/22/87\n.\\\"\n.TH DTAB 5 \"January 22, 1987\"\n.UC 2\n.SH NAME\ndtab \\- automatic system configuration device table (2BSD)\n.SH DESCRIPTION\nThe\n.I dtab\nfile contains a list of the devices that the\n.IR autoconfig (8)\nprogram will attempt to attach to the system.\n.PP\nEach line describes one device which may be present on the system;\nadditional devices of the same type require additional lines.\nThe line contains at least six fields separated by white space.\nBlank lines and comments can appear anywhere in the file except\nbetween fields; comments\nare delimited by `#' and new line.  The fields are (in order):\n.TP \"\\w'handler(s)  'u\"\ndev\nThe device name, usually two characters\n.TP\nunit\nEither a unit number or a `?' indicating automatic selection of unit numbers.\n.TP\naddr\nThe address of the device's first register, as a 16-bit octal number.\n.TP\nvector\nThe interrupt vector, in octal.\n.TP\nBR\nThe priority at which the device interrupts.\n.TP\nhandler(s)\nOne or more routine names with which the interrupt vector is filled.\n.SH EXAMPLE\n.nf\n.sp\n.DT\n.ta .5i +\\w'dm  ?  'u +\\w'160020  'u +\\w'Vector  'u +\\w'5  'u +\\w'dhrint dhxint   'u\n#               Device Configuration Table\n#    Clock and console are pre-configured and should not be listed here\n#\n# Dev#\tAddr\tVector\tBr\tHandler(s)\t# Comment\nlp\t?\t177514\t200\t4\tlpio\t# lp-11 line printer\nht\t0\t172440\t224\t5\thtintr\t# tu 16 massbus tape\nxp\t?\t176700\t254\t5\txpio\t# xp driver\ndm\t?\t170500\t310\t4\tdmin\t# dm11 dh modem control\ndh\t?\t160020\t320\t5\tdhin dhou\t# dh11 terminal mux\ndz\t?\t160110\t330\t5\tdzin dzdma\t# dz11 terminal mux\n.fi\n.SH FILES\n.ta 2i\n/etc/dtab\tdevice table\n.SH SEE ALSO\nautoconfig(8)\n.SH BUGS\n.I /Etc/dtab\nis unique to the PDP-11 and 2BSD.\n"
  },
  {
    "path": "share/man/man5/dump.5",
    "content": ".TH DUMP 5 \"February 26, 1987\"\n.UC\n.SH NAME\ndump, ddate \\- incremental dump format\n.SH SYNOPSIS\n.B #include <sys/types.h>\n.br\n.B #include <sys/ino.h>\n.br\n.B #include <dumprestor.h>\n.SH DESCRIPTION\nTapes used by\n.I dump\nand\n.IR restor (8)\ncontain:\n.nf\n.IP \"\"\na header record\ntwo groups of bit map records\na group of records describing directories\na group of records describing files\n.fi\n.PP\nThe format of the header record and of the first\nrecord of each description as given in the\ninclude file\n.I <dumprestor.h>\nis:\n.PP\n.nf\n.ta .5i \\w'#define\\ TS_INODE\\ 'u\n#if\tUCB_NKB == 1\n#define NTREC   \t10\n#endif\n#ifndef\tUCB_NKB\n#define NTREC   \t20\n#endif\n#define MLEN    \t16\n#define MSIZ    \t4096\n\n#define TS_TAPE \t1\n#define TS_INODE\t2\n#define TS_BITS \t3\n#define TS_ADDR \t4\n#define TS_END  \t5\n#define TS_CLRI \t6\n#define MAGIC   \t(int)60011\n#define CHECKSUM\t(int)84446\nstruct\tspcl\n{\n\tint\tc_type;\n\ttime_t\tc_date;\n\ttime_t\tc_ddate;\n\tint\tc_volume;\n\tdaddr_t\tc_tapea;\n\tino_t\tc_inumber;\n\tint\tc_magic;\n\tint\tc_checksum;\n\tstruct\tdinode\tc_dinode;\n\tint\tc_count;\n\tchar\tc_addr[BSIZE];\n} spcl;\n\nstruct\tidates\n{\n\tchar\tid_name[16];\n\tchar\tid_incno;\n\ttime_t\tid_ddate;\n};\n.fi\n.PP\n.I NTREC\nis the number of BSIZE (sys/param.h) byte records in a physical\ntape block.\n.I MLEN\nis the number of bits in a bit map word.\n.I MSIZ \nis the number of bit map words.\n.PP\nThe\n.I TS\\_\nentries are used in the\n.I c\\_type\nfield to indicate what sort of header\nthis is.\nThe types and their meanings are as follows:\n.TP \\w'CHECKSUM\\|'u\nTS\\_TAPE\nTape volume label\n.PD 0\n.TP\nTS\\_INODE\nA file or directory follows.\nThe\n.I c\\_dinode\nfield is a copy of the disk inode and contains\nbits telling what sort of file this is.\n.TP\nTS\\_BITS\nA bit map follows.\nThis bit map has a one bit\nfor each inode that was dumped.\n.TP\nTS\\_ADDR\nA subrecord of a file description.\nSee\n.I c\\_addr\nbelow.\n.TP\nTS\\_END\nEnd of tape record.\n.TP\nTS\\_CLRI\nA bit map follows.\nThis bit map contains a zero bit for\nall inodes that were empty on the file system when dumped.\n.TP\nMAGIC\nAll header records have this number in\n.I c\\_magic.\n.TP\nCHECKSUM\nHeader records checksum to this value.\n.PD\n.PP\nThe fields of the header structure are as follows:\n.TP \\w'TS_INODE\\ 'u\nc\\_type\nThe type of the header.\n.PD 0\n.TP\nc\\_date\nThe date the dump was taken.\n.TP\nc\\_ddate\nThe date the file system was dumped from.\n.TP\nc\\_volume\nThe current volume number of the dump.\n.TP\nc\\_tapea\nThe current number of this (512-byte) record.\n.TP\nc\\_inumber\nThe number of the inode being dumped if this\nis of type\n.I TS\\_INODE.\n.TP\nc\\_magic\nThis contains the value\n.I MAGIC\nabove, truncated as needed.\n.TP\nc\\_checksum\nThis contains whatever value is needed to\nmake the record sum to \n.I CHECKSUM.\n.TP\nc\\_dinode\nThis is a copy of the inode as it appears on the\nfile system; see\n.IR filsys (5).\n.TP\nc\\_count\nThe count of characters in\n.I c\\_addr.\n.TP\nc\\_addr\nAn array of characters describing the blocks of the\ndumped file.\nA character is zero if the block associated with that character was not\npresent on the file system, otherwise the character is non-zero.\nIf the block was not present on the file system, no block was dumped;\nthe block will be restored as a hole in the file.\nIf there is not sufficient space in this record to describe\nall of the blocks in a file,\n.I TS\\_ADDR\nrecords will be scattered through the file, each one\npicking up where the last left off.\n.PD\n.PP\nEach volume except the last ends with a tapemark (read as an end\nof file).\nThe last volume ends with a\n.I TS\\_END\nrecord and then the tapemark.\n.PP\nThe structure\n.I idates\ndescribes an entry of the file\n.I /etc/ddate\nwhere dump history is kept.\nThe fields of the structure are:\n.TP \\w'TS_INODE\\ 'u\nid\\_name\nThe dumped file system is\n.RI `/dev/ id\\_nam'.\n.PD 0\n.TP\nid\\_incno\nThe level number of the dump tape;\nsee\n.IR dump (8).\n.TP\nid\\_ddate\nThe date of the incremental dump in system format\nsee\n.IR types (5).\n.PD\n.SH FILES\n/etc/ddate\n.SH \"SEE ALSO\"\nfilsys(5), types(5), dump(8), dumpdir(8), restor(8)\n"
  },
  {
    "path": "share/man/man5/fs.5",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)fs.5\t2.4 (2.11BSD) 1996/1/27\n.\\\"\n.TH FS  5 \"January 27, 1996\"\n.UC 2\n.SH NAME\nfs, inode \\- format of file system volume (2BSD)\n.SH SYNOPSIS\n.B #include <sys/types.h>\n.br\n.B #include <sys/fs.h>\n.br\n.B #include <sys/inode.h>\n.SH DESCRIPTION\nEvery file system storage volume (e.g. disk) has a common format for certain\nvital information.  Every such volume is divided into a certain number of\nblocks.  The block size is DEV_BSIZE bytes; specified in\n.RI < sys/param.h >\n\\- currently 1024.\n.PP\nEach disk drive contains some number of file systems each laid out on a\ncontiguous partition of the disk.  A file system consists of a\n.IR \"boot block\" ,\nfollowed by a\n.IR \"super block\" ,\nfollowed by an\n.IR \"inode area\" ,\nfollowed by a\n.I data block area\nwhich takes up the remainder of the disk partition.  The layout of the super\nblock as defined in\n.RI < sys/fs.h >\nis:\n.PP\n.nf\n.ta \\w'struct 'u +\\w'daddr_t 'u +\\w'fs_fsmnt[MAXMNTLEN]; 'u\n#define MAXMNTLEN 12\n\n/*\n * Structure of the super-block\n */\nstruct fs\n{\n\tu_short\tfs_isize;\t\t/* first block after i-list */\n\tdaddr_t\tfs_fsize;\t\t/* size in blocks of entire volume */\n\tshort\tfs_nfree;\t\t/* number of addresses in fs_free */\n\tdaddr_t\tfs_free[NICFREE];\t/* free block list */\n\tshort\tfs_ninode;\t\t/* number of inodes in fs_inode */\n\tino_t\tfs_inode[NICINOD];\t/* free inode list */\n\tchar\tfs_flock;\t\t/* lock during free list manipulation */\n\tchar\tfs_ilock;\t\t/* lock during i-list manipulation */\n\tchar\tfs_fmod;\t\t/* super block modified flag */\n\tchar\tfs_ronly;\t\t/* mounted read-only flag */\n\ttime_t\tfs_time;\t\t/* last super block update */\n\tdaddr_t\tfs_tfree;\t\t/* total free blocks */\n\tino_t\tfs_tinode;\t\t/* total free inodes */\n\tshort\tfs_step;\t\t/* optimal step in free list pattern */\n\tshort\tfs_cyl;\t\t\t/* number of blocks per pattern */\n\tchar\tfs_fsmnt[MAXMNTLEN];\t/* ordinary file mounted on */\n\tino_t\tfs_lasti;\t\t/* start place for circular search */\n\tino_t\tfs_nbehind;\t\t/* est # free inodes before s_lasti */\n\tu_short\tfs_flags;\t\t/* mount time flags */\n};\n.fi\n.PP\n.IR \"File system\" :\nA file system is described by its super-block.  Block 0 of each file system\npartition is unused and is available to contain a bootstrap program, pack\nlabel, or other information.  Block 1 (SUPERB) is the super block.  The\ninode area starts immediately after the super-block, in block 2.\n.I Fs_isize\nis the address of the first block after the inode area.  Thus the inode area\nis\n.IR fs_isize \\-2\nblocks long.\n.I Fs_fsize\nis the address of the first block not potentially available for allocation\nto a file.  Thus the data block area is\n.I \"fs_fsize \\- fs_isize\"\nblocks long.\n.PP\n.IR \"Super block\" :\nThe path name on which the file system is mounted is maintained in\n.IR fs_fsmnt .\n.IR Fs_flock ,\n.IR fs_ilock ,\n.IR fs_fmod ,\n.IR fs_ronly \" and\"\n.IR fs_flags\nare flags maintained in the in core copy of the super block while its file\nsystem is mounted and their values on disk are immaterial.\n.I Fs_fmod\nis used as a flag to indicate that the super-block has changed and should be\ncopied to the disk during the next periodic update of file system information.\n.I Fs_ronly\nis a write-protection indicator.  It is a copy of the mount flags\n.I fs_flags\nanded with\n.BR MNT_RDONLY (see \\fI/sys/h/mount.h\\fP).\n.PP\n.I Fs_time\nis the last time the super-block of the file system was changed.  During a\nreboot, the\n.I fs_time\nof the super-block for the root file system is used to set the system's idea\nof the time.\n.PP\n.IR Inode :\nThe inode is the focus of all file activity in the UNIX file system.  There\nis a unique inode allocated for each active file, each current directory,\neach mounted-on file, text file, and the root.  An inode is `named' by its\ndevice/i-number pair.\n.PP\nInodes are 64 bytes long, so 16 of them fit into a block if DEV_BSIZE is 1024.\nThe root inode is the root of the file system.  Inode 0 can't be used for\nnormal purposes and historically bad blocks were linked to inode 1, thus the\nroot inode is 2 (inode 1 is no longer used for this purpose, however numerous\ndump tapes make this assumption, so we are stuck with it).  No other i-number\nhas a built-in meaning.\n.PP\nThe format of an inode as given in\n.RI < sys/inode.h >\nis:\n.PP\n.nf\n.ta \\w'struct 'u +\\w'u_short 'u +\\w'di_addr[40]; 'u\n/*\n * Inode structure as it appears on\n * a disk block.\n */\nstruct dinode {\n\tu_short\tdi_mode;\t/* mode and type of file */\n\tshort\tdi_nlink;\t/* number of links to file */\n\tuid_t\tdi_uid;\t\t/* owner's user id */\n\tgid_t\tdi_gid;\t\t/* owner's group id */\n\toff_t\tdi_size;\t/* number of bytes in file */\n\tdaddr_t\tdi_addr[7];\t/* 7 block addresses 4 bytes each */\n\tu_short\tdi_reserved[5];\t/* pad of 10 to make total size 64 */\n\tu_short\tdi_flags;\n\ttime_t\tdi_atime;\t/* time last accessed */\n\ttime_t\tdi_mtime;\t/* time last modified */\n\ttime_t\tdi_ctime;\t/* time created */\n};\n\n/*\n * 28 of the di_addr address bytes are used; 7 addresses of 4\n * bytes each: 4 direct (4Kb directly accessible) and 3 indirect.\n */\n#define NADDR\t7\n\n/* modes */\n\n.ta \\w'#define 'u +\\w'IWRITE 'u +\\w'0170000 'u\n#define\tIFMT\t0170000\t/* type of file */\n#define\tIFCHR\t0020000\t/* character special */\n#define\tIFDIR\t0040000\t/* directory */\n#define\tIFBLK\t0060000\t/* block special */\n#define\tIFREG\t0100000\t/* regular */\n#define\tIFLNK\t0120000\t/* symbolic link */\n#define\tIFSOCK\t0140000\t/* socket */\n#define\tISUID\t04000\t/* set user id on execution */\n#define\tISGID\t02000\t/* set group id on execution */\n#define\tISVTX\t01000\t/* save swapped text even after use */\n#define\tIREAD\t0400\t/* read, write, execute permissions */\n#define\tIWRITE\t0200\n#define\tIEXEC\t0100\n.fi\n.PP\n.I Di_mode\nidentifies the type of file the inode represents; it is encoded identically\nto the\n.IR st_mode \" field of \" stat (2).\n.I Di_nlink\nis the number of directory entries (links) that refer to this inode.\n.I Di_uid\nand\n.I di_gid\nare the owner's user and group IDs.\n.I Di_size\nis the number of bytes in the file.\n.I Di_atime\nand\n.I di_mtime\nare the times of last access and modification of the file contents (read,\nwrite or create);\n.I Di_ctime\nrecords the time of last modification to the inode or to the file, and is\nused to determine whether it should be dumped by\n.IR dump (8).\n.PP\nSpecial files are recognized by their modes.  A block-type special file is\none which can potentially be mounted as a file system; a character-type\nspecial file cannot, though it is not necessarily character-oriented.  For\nspecial files, the first two bytes of the\n.I di_addr\nfield are occupied by the device code\n.RI \"(see \" types (5)).\nThe device codes of block and character special files overlap.\n.PP\nDisk addresses of plain files and directories are kept in the array\n.I di_addr.\nFor a DEV_BSIZE of 1K bytes, 7 addresses are kept in\n.I di_addr\nusing 28 of the 40 bytes.  The first 4 addresses specify device\nblocks directly.  The last 3 addresses are singly, doubly and triply\nindirect and point to blocks containing 256 further block pointers.\nThere are 3 block addresses reserved as a pad to bring the total\nsize of an inode to 64 bytes.\nAll block addresses are of type\n.IR daddr_t \" (see \" types (5)).\n.PP\nFor block\n.I b\nin a file to exist, it is not necessary that all blocks less than\n.I b\nexist.  A zero block number\nindicates that the corresponding block has never been\nallocated.  Such a missing block reads as if it contained all zero bytes.\n.PP\n.IR \"Free block list\" :\nThe free data block list for each volume is maintained as follows.\n.I \"Fs_free[1], ... , fs_free[fs_nfree\\-1],\"\ncontain up to NICFREE free block numbers (NICFREE is a configuration\nconstant defined in\n.RI < sys/param.h \">).\"\n.I Fs_free[0]\nis the block address of the head of a chain of blocks constituting the free\nlist.  The layout of each block of the free chain as defined in\n.RI < sys/fs.h >\nis:\n.PP\n.nf\n.ta \\w'struct 'u +\\w'daddr_t 'u +\\w'df_free[NICFREE]; 'u\nstruct fblk\n{\n\tshort\tdf_nfree;\t\t/* number of addresses in df_free */\n\tdaddr_t\tdf_free[NICFREE];\t/* free block list */\n};\n.fi\n.PP\nThe fields\n.I df_nfree\nand\n.I df_free\nin a free block are used exactly like\n.I fs_nfree\nand \n.I fs_free\nin the super block.\n.PP\nThe algorithm used to allocate a block is:  decrement\n.I fs_nfree,\nand the new block number is\n.I fs_free[fs_nfree].\nIf the new block address is 0, there are no blocks left, so give an error.\nIf\n.I fs_nfree\nbecame 0, read the new block into\n.I fs_nfree\nand \n.I fs_free.\n.PP\nTo free a block: check if\n.I fs_nfree\nis NICFREE; if so, copy\n.I fs_nfree\nand the\n.I fs_free\narray into the newly freed block, write it out, and set\n.I fs_nfree\nto 0.  In any event set\n.I fs_free[fs_nfree]\nto the freed block's address and increment\n.I fs_nfree.\n.PP\n.IR Fs_isize \" and \" fs_fsize\nare used by the system to check for bad block addresses; if an `impossible'\nblock address is allocated from or returned to the free list, a diagnostic\nis written on the console.  Moreover, the free array is cleared, to prevent\nfurther allocation from a presumably corrupted free list.\n.PP\n.IR Fs_step \" and \" fs_cyl\ndetermine the block interleaving of files for fastest access; traditionally\nthese were referred to as\n.IR s_m \" and \" s_n \" respectively.\"\n.I Fs_step\nis the distance between successive blocks and\n.I fs_cyl\nis the number of blocks before the pattern repeats.  A file system's\ninterleaving factors are determined when it is first created by\n.IR mkfs (8).\n.I Mkfs\nlays out the initial free list with these parameters and\n.IR fsck (8)\ncan be used to rebuild the free list optimally (and assign new interleaving\nfactors if necessary).\n.PP\n.IR \"Free inode list\" :\n.I Fs_ninode\nis the number of free inode numbers in the\n.I fs_inode\narray.\n.PP\nTo allocate an inode: if\n.I fs_ninode\nis greater than 0, decrement it and return\n.I fs_inode[fs_ninode].\nIf it was 0, read through the inode area and place the numbers of all free\ninodes (up to NICINOD) into the\n.I fs_inode\narray, then try again.  If a search for free inodes is necessary, the search\nwill start at the beginning of the inode area if\n.I fs_nbehind\n>= 4 \\(mu NICINOD, otherwise starting at\n.I fs_lasti\nand continuing at the beginning of the inode area if NICINOD free inodes\naren't found when the end of the inode area is reached.  When a search\ncompletes the i-number of the first inode of the last block scanned in the\nsearch is left in\n.IR fs_lasti .\n.PP\nTo free an inode, provided\n.I fs_ninode\nis less than NICINODE, place its number into\n.I fs_inode[fs_ninode]\nand increment\n.I fs_ninode.\nIf\n.I fs_ninode\nis already NICINODE, don't bother to enter the freed inode into any table\n.RI ( fs_inode\nis only to speed up the allocation process; the information as to whether\nthe inode is really free or not is maintained in the inode itself).  If the\ni-number of the freed inode is less than\n.I fs_lasti\nincrement\n.IR fs_nbehind .\n.SH \"SEE ALSO\"\nstat(2), dir(5), types(5), dcheck(8), fsck(8), icheck(8), mkfs(8), mount(8)\n.SH BUGS\nIt isn't the\n.IR \"4BSD fast file system\" .\nThe 2BSD file system is a direct descendent of the V7 file system and exists\nlittle changed from that ancestor.  There are many performance holes in the\nfile system.\n.PP\nSome changes from the original V7 file system have resulted in better\nperformance: The larger block size (1Kb as opposed to the 512 byte block\nsize of V7) cuts the average number of system calls necessary to access a\nfile by a factor of two; the smaller (in core) inodes allowed by the smaller\nnumber of direct links kept in inodes saves valuable kernel data space\nallowing the kernel buffer cache to be made larger while sacrificing only\n1Kb of direct file accessing; and starting free inode searches at the\nposition the last search ended cuts the time to gather free inodes\nsignificantly.\n.PP\nHowever, the separation of inodes and data blocks into completely different\nareas of the disk, the handling of the free list, the lack of any file\nallocation layout policy encouraging locality such as that found in the 4BSD\nfile system and the still too small block size often leads to extremely poor\nperformance.\n.PP\nThe separation of inodes and data blocks in the file system means that to\naccess a file a seek will have to be made to the beginning of the disk\npartition containing the file system followed another to the the actual\ndata blocks of the file (often quite distant from the inode area).\n.PP\nThe free list which is laid out at file system creation for optimal file\nblock allocation, becomes scrambled over time on an active file system.\nThis process is slowed down by the kernel which always frees blocks from\nunlink'ed or truncated files in reverse order thereby maintaining strings\nof optimally laid out free blocks in the free list.  Eventually, however,\nsince both freed and allocated blocks use the head of the free list, it's\npossible (and quite probable) to have most of the free list laid out\noptimally with the first portion totally scrambled.  As a trade off, a file\nsystem's free list may be rebuilt fairly frequently via\n.I icheck -s \nor\n.I fsck -s\nand most blocks allocated will be localized as close to the the inode area\nas possible.  Because of this problem, files are sometimes scattered\nacross a file system generating an unpleasant amount of disk arm movement.\nA nasty oscillation also occurs in the free block list when\n.I fs_nfree\nhovers around NICFREE and 0 causing the free array to be constantly written\nout and read back in as blocks are freed and allocated.\n.PP\nFor a more in depth analysis of the 2BSD file system, its shortcomings, and\na description of the changes made for the 4BSD file system see\n\\*(lq\\fBA Fast File System for UNIX\\fR\\*(rq\nby \n.IR \"M. McKusick\" ;\n.IR \"W. Joy\" ;\n.IR \"S. Leffler\" \"; and\"\n.IR \"R. Fabry\" .\n"
  },
  {
    "path": "share/man/man5/fstab.5",
    "content": ".\\\" Copyright (c) 1980, 1989, 1991, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. All advertising materials mentioning features or use of this software\n.\\\"    must display the following acknowledgement:\n.\\\"\tThis product includes software developed by the University of\n.\\\"\tCalifornia, Berkeley and its contributors.\n.\\\" 4. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)fstab.5\t8.1.1 (2.11BSD) 1996/1/15\n.\\\"\n.TH FSTAB 5 \"January 15, 1996\"\n.UC 7\n.SH NAME\n\\fBfstab\\fP \\- static information about the filesystems\n.SH SYNOPSIS\n.B #include <fstab.h>\n.SH DESCRIPTION\nThe file\n.B fstab\ncontains descriptive information about the various file\nsystems.\n.B fstab\nis only read by programs, and not written;\nit is the duty of the system administrator to properly create \nand maintain this file.\nEach filesystem is described on a separate line;\nfields on each line are separated by tabs or spaces.\nThe order of records in\n.B fstab\nis important because\nfsck(8),\nmount(8),\nand\numount(8)\nsequentially iterate through\n.B fstab\ndoing their thing.\n.PP\nThe first field,\n.IR fs_spec ,\ndescribes the block special device or\nremote filesystem to be mounted.\nFor filesystems of type\n.IR ufs ,\nthe special file name is the block special file name, \nand not the character special file name.\nIf a program needs the character special file name,\nthe program must create it by appending a ``r'' after the\nlast ``/'' in the special file name.\n.PP\nThe second field,\n.IR fs_file ,\ndescribes the mount point for the filesystem.\nFor swap partitions, this field should be specified as ``none''.\n.PP\nThe third field,\n.IR fs_vfstype ,\ndescribes the type of the filesystem.\nThe system currently supports only two types of filesystems:\n.TP 15\n.I ufs \na local UNIX filesystem\n.TP 15\n.I swap \na disk partition to be used for swapping\n.PP\nThe fourth field,\n.IR fs_mntops ,\ndescribes the mount options associated with the filesystem.\nIt is formatted as a comma separated list of options.\nIt contains at least the type of mount (see\n.I fs_type\nbelow) plus any additional options\nappropriate to the filesystem type.\n.PP\nIf the option ``quotas'' is specified,\nthe filesystem is automatically processed by the\nquotacheck(8)\ncommand, and user disk quotas are enabled with\nquotaon(8).\nFilesystem quotas are maintained in the file named\n.I quotas\nlocated at the root of the associated filesystem.  This restriction on\nthe location of the quotas file is needlessly imposed by the kernel but\nmay be lifted in the future.\nThus, if the user quota file for\n.I /tmp\nis stored in\n.IR /var/quotas/tmp.user ,\nthis location can be specified as:\n.sp\n.in +.75i\nquotas=/var/quotas/tmp.user\n.br\n.in -0.75i\n.PP\nThe type of the mount is extracted from the\n.I fs_mntops\nfield and stored separately in the\n.I fs_type\nfield (it is not deleted from the\n.I fs_mntops\nfield).\nIf\n.I fs_type\nis ``rw'' or ``ro'' then the filesystem whose name is given in the\n.I fs_file\nfield is normally mounted read-write or read-only on the\nspecified special file.\nIf\n.I fs_type\nis ``sw'' then the special file is made available as a piece of swap\nspace by the\nswapon(8)\ncommand at the end of the system reboot procedure.\nThe fields other than\n.I fs_spec\nand\n.I fs_type\nare unused.\nIf\n.I fs_type\nis specified as ``xx'' the entry is ignored.\nThis is useful to show disk partitions which are currently unused.\n.PP\nThe fifth field,\n.IR fs_freq ,\nis used for these filesystems by the\ndump(8)\ncommand to determine which filesystems need to be dumped.\nIf the fifth field is not present, a value of zero is returned and\ndump(8)\nwill assume that the filesystem does not need to be dumped.\n.PP\nThe sixth field,\n.IR fs_passno ,\nis used by the\nfsck(8)\nprogram to determine the order in which filesystem checks are done\nat reboot time.\nThe root filesystem should be specified with a\n.I fs_passno\nof 1, and other filesystems should have a \n.I fs_passno\nof 2.\nFilesystems within a drive will be checked sequentially,\nbut filesystems on different drives will be checked at the\nsame time to utilize parallelism available in the hardware.\nIf the sixth field is not present or zero,\na value of zero is returned and\nfsck(8)\nwill assume that the filesystem does not need to be checked.\n.br\n.nf\n.cs R 24\n\n#define\tFSTAB_RW\t\"rw\"\t/* read-write device */\n#define\tFSTAB_RO\t\"ro\"\t/* read-only device */\n#define\tFSTAB_SW\t\"sw\"\t/* swap device */\n#define\tFSTAB_XX\t\"xx\"\t/* ignore totally */\n\nstruct fstab {\n\tchar\t*fs_spec;\t/* block special device name */\n\tchar\t*fs_file;\t/* filesystem path prefix */\n\tchar\t*fs_vfstype;\t/* type of filesystem */\n\tchar\t*fs_mntops;\t/* comma separated mount options */\n\tchar\t*fs_type;\t/* rw, ro, sw, or xx */\n\tint\tfs_freq;\t/* dump frequency, in days */\n\tint\tfs_passno;\t/* pass number on parallel dump */\n};\n.fi\n.cs R\n.PP\nThe proper way to read records from\n.I fstab\nis to use the routines\ngetfsent(3),\ngetfsspec(3),\ngetfstype(3),\nand\ngetfsfile(3).\n.SH FILES\n.TP 15\n.I /etc/fstab\nThe file\n.B fstab\nresides in\n.IR /etc .\n.SH SEE ALSO\ngetfsent(3)\n.SH HISTORY\nThe\n.B fstab\nfile format appeared in\n4.0BSD.\n"
  },
  {
    "path": "share/man/man5/gettytab.5",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)gettytab.5\t6.3.1 (2.11BSD) 1997/3/28\n.\\\"\n.TH GETTYTAB 5 \"March 28, 1997\"\n.UC 5\n.SH NAME\ngettytab \\- terminal configuration data base\n.SH SYNOPSIS\n/etc/gettytab\n.SH DESCRIPTION\n.I Gettytab\nis a simplified version of the\n.IR termcap (5)\ndata base\nused to describe terminal lines.\nThe initial terminal login process\n.IR getty (8)\naccesses the\n.I gettytab\nfile each time it starts, allowing simpler\nreconfiguration of terminal characteristics.\nEach entry in the data base\nis used to describe one class of terminals.\n.PP\nThere is a default terminal class,\n.IR default ,\nthat is used to set global defaults for all other classes.\n(That is, the\n.I default \nentry is read, then the entry for the class required\nis used to override particular settings.)\n.SH CAPABILITIES\nRefer to\n.IR termcap (5)\nfor a description of the file layout.\nThe\n.I default\ncolumn below lists defaults obtained if there is\nno entry in the table obtained, nor one in the special\n.I default\ntable.\n.nf\n\n.ta \\w'k0-k9  'u +\\w'Type  'u +\\w'``/bin/login\"  'u\n\\fBName\tType\tDefault\tDescription\\fR\nap\tbool\tfalse\tterminal uses any parity\nbk\tstr\t0377\talternate end of line character (input break)\ncb\tbool\tfalse\tuse crt backspace mode\nce\tbool\tfalse\tuse crt erase algorithm\nck\tbool\tfalse\tuse crt kill algorithm\ncl\tstr\tNULL\tscreen clear sequence\nco\tbool\tfalse\tconsole - add \\\\n after login prompt\nds\tstr\t^Y\tdelayed suspend character\ndx\tbool\tfalse\tset DECCTLQ\nec\tbool\tfalse\tleave echo \\s-2OFF\\s0\nep\tbool\tfalse\tterminal uses even parity\ner\tstr\t^?\terase character\net\tstr\t^D\tend of text (\\s-2EOF\\s0) character\nev\tstr\tNULL\tinitial enviroment\nf0\tnum\tunused\ttty mode flags to write messages\nf1\tnum\tunused\ttty mode flags to read login name\nf2\tnum\tunused\ttty mode flags to leave terminal as\nfl\tstr\t^O\toutput flush character\nhc\tbool\tfalse\tdo \\s-2NOT\\s0 hangup line on last close\nhe\tstr\tNULL\thostname editing string\nhf\tbool\tfalse\tenable hardware (rts/cts) flow control\nhn\tstr\thostname\thostname\nht\tbool\tfalse\tterminal has real tabs\nig\tbool\tfalse\tignore garbage characters in login name\nim\tstr\tNULL\tinitial (banner) message\nin\tstr\t^C\tinterrupt character\nis\tnum\tunused\tinput speed\nkl\tstr\t^U\tkill character\nlc\tbool\tfalse\tterminal has lower case\nlm\tstr\tlogin:\tlogin prompt\nln\tstr\t^V\t``literal next'' character\nlo\tstr\t/bin/login\tprogram to exec when name obtained\nnl\tbool\tfalse\tterminal has (or might have) a newline character\nnx\tstr\tdefault\tnext table (for auto speed selection)\nop\tbool\tfalse\tterminal uses odd parity\nos\tnum\tunused\toutput speed\npc\tstr\t\\\\0\tpad character\npe\tbool\tfalse\tuse printer (hard copy) erase algorithm\npf\tnum\t0\tdelay between first prompt and following flush (seconds)\nps\tbool\tfalse\tline connected to a MICOM port selector\nqu\tstr\t^\\\\\tquit character\nrp\tstr\t^R\tline retype character\nrw\tbool\tfalse\tdo \\s-2NOT\\s0 use raw for input, use cbreak\nsp\tnum\tunused\tline speed (input and output)\nsu\tstr\t^Z\tsuspend character\ntc\tstr\tnone\ttable continuation\nto\tnum\t0\ttimeout (seconds)\ntt\tstr\tNULL\tterminal type (for enviroment)\nub\tbool\tfalse\tdo unbuffered output (of prompts etc)\nwe\tstr\t^W\tword erase character\nxc\tbool\tfalse\tdo \\s-2NOT\\s0 echo control chars as ^X\nxf\tstr\t^S\tXOFF (stop output) character\nxn\tstr\t^Q\tXON (start output) character\n.br\n.fi\n.PP\nIf no line speed is specified, speed will not be altered\nfrom that which prevails when getty is entered.\nSpecifying an input or output speed will override\nline speed for stated direction only.\n.PP\nTerminal modes to be used for the output of the message,\nfor input of the login name,\nand to leave the terminal set as upon completion,\nare derived from the boolean flags specified.\nIf the derivation should prove inadequate,\nany (or all) of these three may be overriden\nwith one of the\n.BR f0 ,\n.BR f1 \", or\"\n.B f2\nnumeric specifications, which can be used to specify\n(usually in octal, with a leading '0')\nthe exact values of the flags.\nLocal (new tty) flags are set in the top 16 bits\nof this (32 bit) value.\n.PP\nShould\n.I getty\nreceive a null character\n(presumed to indicate a line break)\nit will restart using the table indicated by the\n.B nx\nentry. If there is none, it will re-use its original table.\n.PP\nThe\n.B cl\nscreen clear string may be preceded by a (decimal) number\nof milliseconds of delay required (a la termcap).\nThis delay is simulated by repeated use of the pad character\n.BR pc .\n.PP\nThe initial message, and login message,\n.B im\nand\n.B lm\nmay include the character sequence \\fB%h\\fP or \\fB%t\\fP to obtain\nthe hostname or tty name respectively.\n(\\fB%%\\fP obtains a single '%' character.)\nThe hostname is normally obtained from the system,\nbut may be set by the\n.B hn\ntable entry.\nIn either case it may be edited with\n.BR he .\nThe\n.B he\nstring is a sequence of characters, each character that\nis neither '@' nor '#' is copied into the final hostname.\nA '@' in the\n.B he\nstring, causes one character from the real hostname to\nbe copied to the final hostname.\nA '#' in the\n.B he\nstring, causes the next character of the real hostname\nto be skipped.\nSurplus '@' and '#' characters are ignored.\n.PP\nWhen getty execs the login process, given\nin the\n.B lo\nstring (usually \"/bin/login\"), it will have set\nthe enviroment to include the terminal type, as indicated\nby the\n.B tt\nstring (if it exists).\nThe\n.B ev\nstring, can be used to enter additional data into\nthe environment.\nIt is a list of comma separated strings, each of which\nwill presumably be of the form\n.IR name=value .\n.PP\nIf a non-zero timeout is specified, with\n.BR to ,\nthen getty will exit within the indicated\nnumber of seconds, either having\nreceived a login name and passed control\nto\n.IR login ,\nor having received an alarm signal, and exited.\nThis may be useful to hangup dial in lines.\n.PP\nOutput from\n.I getty\nis even parity unless\n.B op\nis specified.\n.B Op\nmay be specified with\n.B ap\nto allow any parity on input, but generate odd parity output.\nNote: this only applies while getty is being run,\nterminal driver limitations prevent a more complete\nimplementation.\n.I Getty\ndoes not check parity of input characters in\n.I RAW\nmode.\n.SH \"SEE ALSO\"\nlogin(1),\ntermcap(5),\ngetty(8).\n.SH BUGS\nThe special characters (erase, kill, etc.) are reset to system defaults\nby\n.IR login (1).\nIn\n.B all\ncases, '#' or '^H' typed in a login name will be treated as\nan erase character, and '@' will be treated as a kill character.\n.PP\nThe delay stuff is a real crock.  It has been removed from the system\nentirely.\nThe\n.B he\ncapability is stupid.\n.PP\n.I Termcap\nformat is horrid, something more rational should\nhave been chosen.\n"
  },
  {
    "path": "share/man/man5/group.5",
    "content": ".\\\"\t@(#)group.5\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH GROUP 5  \"May 15, 1985\"\n.AT 3\n.SH NAME\ngroup \\- group file\n.SH DESCRIPTION\n.I Group\ncontains for each group the\nfollowing information:\n.HP 10\ngroup name\n.br\n.ns\n.HP 10\nencrypted password\n.br\n.ns\n.HP 10\nnumerical group ID\n.br\n.ns\n.HP 10\na comma separated list of all users allowed in the group\n.PP\nThis is an ASCII file.\nThe fields are separated\nby colons;\nEach group is separated from the next by a new-line.\nIf the password field is null, no password is demanded.\n.PP\nThis file resides in directory /etc.\nBecause of the encrypted\npasswords, it can and does have general read\npermission and can be used, for example,\nto map numerical group ID's to names.\n.SH FILES\n/etc/group\n.SH \"SEE ALSO\"\nsetgroups(2), initgroups(3X), crypt(3), passwd(1), passwd(5)\n.SH BUGS\nThe\n.IR passwd (1)\ncommand won't change the passwords.\n"
  },
  {
    "path": "share/man/man5/hosts.5",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)hosts.5\t6.3 (Berkeley) 5/14/86\n.\\\"\n.TH HOSTS 5  \"May 14, 1986\"\n.UC 5\n.SH NAME\nhosts \\- host name data base\n.SH DESCRIPTION\nThe\n.I hosts\nfile contains information regarding\nthe known hosts on the network.\nFor each host a single line should be present\nwith the following information:\n.HP 10\nofficial host name\n.br\n.ns\n.HP 10\nInternet address\n.br\n.ns\n.HP 10\naliases\n.PP\nItems are separated by any number of blanks and/or\ntab characters.  A ``#'' indicates the beginning of\na comment; characters up to the end of the line are\nnot interpreted by routines which search the file.\n.PP\nWhen using the name server\n.IR named (8),\nthis file provides a backup when the name server\nis not running.\nFor the name server, it is suggested that only a few addresses\nbe included in this file.\nThese include  address for the local interfaces that \n.IR ifconfig (8C)\nneeds at boot time and a few machines on the local network.\n.PP\nThis file may be created from the official host\ndata base maintained at the Network Information Control\nCenter (NIC), though local changes may be required\nto bring it up to date regarding unofficial aliases\nand/or unknown hosts.  As the data base maintained at NIC\nis incomplete, use of the name server is recommend for\nsites on the DARPA Internet.\n.PP\nNetwork addresses are specified in the conventional\n``.'' notation using the \\fIinet_addr\\fP() routine\nfrom the Internet address manipulation library,\n.IR inet (3N).\nHost names may contain any printable\ncharacter other than a field delimiter, newline,\nor comment character.\n.SH FILES\n/etc/hosts\n.SH \"SEE ALSO\"\ngethostbyname(3N), ifconfig(8C), named(8)\n.br\nName Server Operations Guide for BIND\n"
  },
  {
    "path": "share/man/man5/intro.5",
    "content": ".\\\"\t$OpenBSD: intro.5,v 1.9 2018/09/30 13:24:32 schwarze Exp $\n.\\\"\n.\\\" Copyright (c) 1999 Hugh Graham\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.Dd May 22, 2025\n.Dt INTRO 5\n.Os\n.Sh NAME\n.Nm intro\n.Nd introduction to file formats\n.Sh DESCRIPTION\nThe manual pages in section 5 contain information related to\nfile formats, including:\n.Pp\n.Bl -bullet -offset indent -compact\n.It\nASCII configuration and resource files\n.It\nsystem binary file structures\n.It\ncomposition of database files\n.El\n.Sh HISTORY\nAn\n.Nm\nmanual for section 5 appeared in\n.Bx Disco\n2.5.\n"
  },
  {
    "path": "share/man/man5/map3270.5",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)map3270.5\t1.3.1 (2.11BSD) 1996/11/27\n.\\\"\n.TH MAP3270 5  \"November 27, 1996\"\n.UC 6\n.SH NAME\nmap3270 \\- database for mapping ascii keystrokes into IBM 3270 keys\n.SH SYNOPSIS\n.B /usr/share/misc/map3270\n.SH DESCRIPTION\nWhen emulating IBM-syle 3270 terminals under UNIX (see \\fItn3270\\fR(1)),\na mapping must be performed between sequences of keys hit on\na user's (ascii) keyboard, and the keys that are\navailable on a 3270.  For example, a 3270 has a key labeled\n.B EEOF\nwhich erases the contents of the current field from the\nlocation of the cursor to the end.\nIn order to accomplish this function,\nthe terminal user and a program emulating a 3270 must\nagree on what keys will be typed\nto invoke the\n.B EEOF\nfunction.\n.PP\nThe requirements for these sequences are:\n.nf\n.ta 4n 9n\n.sp\n\t1.)\tthat the first character of the sequence be outside of the\n\t\tstandard ascii printable characters;\n.sp\n\t2.)\tthat no one sequence \\fIbe\\fR an initial part of another (although\n\t\tsequences may \\fIshare\\fR initial parts).\n.sp\n.fi\n.SH FORMAT\nThe file consists of entries for various terminals.  The first part\nof an entry lists the names of the terminals which use that entry.\nThese names should be the same as in\n.I /etc/termcap\n(see \\fItermcap\\fR(5));\nnote that often the terminals from various termcap entries will all\nuse the same\n.I map3270\nentry; for example, both 925 and 925vb (for\n925 with visual bells) would probably use the same\n.I map3270\nentry.\nAfter the names, separated by vertical bars (`|'), comes a left\nbrace (`{'); the definitions; and, finally, a right brace\n(`}').\n.PP\nThe definitions consist of a reserved keyword (see list below) which\nidentifies the 3270 function (extended as defined below), followed\nby an equal sign (`='), followed by the various ways to generate\nthis particular function, followed by a semi-colon (`;').\nEach way is a sequence of strings of\n.I printable\nascii characters enclosed inside single quotes (`\\(aa');\nvarious ways (options) are separated by vertical bars (`|').\n.PP\nInside the single quotes, a few characters are special.\nA caret\n(`^') specifies that the next character is\nthe ``control'' character of whatever the character is.\nSo, `^a'\nrepresents control-a, ie: hexadecimal 1\n(note that `^A' would generate the same code). \nTo generate\n.B rubout,\none enters `^?'.\nTo represent a control character inside a file\nrequires using the caret to represent a control sequence;\nsimply typing control-A will not work.\nNote: the ctrl-caret sequence\n(to generate a hexadecimal 1E)\nis represented as `^^' (not `^\\e^').\n.PP\nIn addition to the caret, a letter may be preceeded by a backslash (`\\e').\nSince this has little effect for most characters,\nits use is usually not recommended.\nFor the case of a single quote (`\\(aa'), the backslash\nprevents that single quote from terminating the string.\nTo have the backslash be part of the string, it is necessary to\nplace two backslashes ('\\e\\e') in the file.\n.PP\nIn addition, the following characters are special:\n.sp\n.nf\n.in +0.5i\n`\\eE'  means an escape character;\n`\\en'  means newline;\n`\\et'  means tab;\n`\\er'  means carriage return.\n.in -0.5i\n.fi\n.sp\nIt is not necessary for each character in a string\nto be enclosed within single quotes.\n`\\eE\\eE\\eE' means three escape characters.\n.PP\nComments, which may appear anywhere on a line,\nbegin with a hash mark (`#'), and terminate\nat the end of that line.\nHowever, comments cannot begin inside a quoted string;\na hash mark inside a quoted string has no special meaning.\n.PP\n.SH 3270 KEYS SUPPORTED\nThe following is the list of 3270 key names that are supported in this file.\nNote that some of the keys don't really exist on a 3270.\nIn particular, the developers of this file have relied\nextensively on the work at the Yale University Computer Center with\ntheir 3270 emulator which runs in an IBM Series/1 front end.\nThe following list corresponds closely to the functions\nthat the developers of the Yale code offer in their product.\n.sp\n.B In the following list, the\n.B starred (\"*\")\n.B functions are not supported by\n.IR tn3270 (1).\nAn unsupported function will cause\n.IR tn3270(1)\nto send a bell sequence to the user's terminal.\n.sp\n.nf\n        3270 Key Name   Functional description\n\n     (*)LPRT            local print\n        DP              dup character\n        FM              field mark character\n     (*)CURSEL          cursor select\n        RESHOW          redisplay the screen\n        EINP            erase input\n        EEOF            erase end of field\n        DELETE          delete character\n        INSRT           toggle insert mode\n        TAB             field tab\n        BTAB            field back tab\n        COLTAB          column tab\n        COLBAK          column back tab\n        INDENT          indent one tab stop\n        UNDENT          undent one tab stop\n        NL              new line\n        HOME            home the cursor\n        UP              up cursor\n        DOWN            down cursor\n        RIGHT           right cursor\n        LEFT            left cursor\n        SETTAB          set a column tab\n        DELTAB          delete a columntab\n        SETMRG          set left margin\n        SETHOM          set home position\n        CLRTAB          clear all column tabs\n     (*)APLON           apl on\n     (*)APLOFF          apl off\n     (*)APLEND          treat input as ascii\n     (*)PCON            xon/xoff on\n     (*)PCOFF           xon/xoff off\n        DISC            disconnect (suspend)\n     (*)INIT            new terminal type\n     (*)ALTK            alternate keyboard dvorak\n        FLINP           flush input\n        ERASE           erase last character\n        WERASE          erase last word\n        FERASE          erase field\n        SYNCH           we are in synch with the user\n        RESET           reset key-unlock keyboard\n        MASTER_RESET    reset, unlock and redisplay\n     (*)XOFF            please hold output\n     (*)XON             please give me output\n        ESCAPE          enter telnet command mode\n        WORDTAB         tab to beginning of next word\n        WORDBACKTAB     tab to beginning of current/last word\n        WORDEND         tab to end of current/next word\n        FIELDEND        tab to last non-blank of current/next\n                        unprotected (writable) field.\n\n        PA1             program attention 1\n        PA2             program attention 2\n        PA3             program attention 3\n\n        CLEAR           local clear of the 3270 screen\n        TREQ            test request\n        ENTER           enter key\n\n        PFK1            program function key 1\n        PFK2            program function key 2\n        etc.            etc.\n        PFK36           program function key 36\n.SH A SAMPLE ENTRY\nThe following entry is used by\ntn3270(1) when unable to locate a reasonable version in the\nuser's environment and in /usr/share/misc/map3270:\n.sp\n.nf\n        name {          # actual name comes from TERM variable\n        clear = '^z';\n        flinp = '^x';\n        enter = '^m';\n        delete = '^d' | '^?';   # note that '^?' is delete (rubout)\n        synch = '^r';\n        reshow = '^v';\n        eeof = '^e';\n        tab = '^i';\n        btab = '^b';\n        nl = '^n';\n        left = '^h';\n        right = '^l';\n        up = '^k';\n        down = '^j';\n        einp = '^w';\n        reset = '^t';\n        xoff = '^s';\n        xon = '^q';\n        escape = '^c';\n        ferase = '^u';\n        insrt = '\\E ';\n        # program attention keys\n        pa1 = '^p1'; pa2 = '^p2'; pa3 = '^p3';\n        # program function keys\n        pfk1 = '\\eE1'; pfk2 = '\\eE2'; pfk3 = '\\eE3'; pfk4 = '\\eE4';\n        pfk5 = '\\eE5'; pfk6 = '\\eE6'; pfk7 = '\\eE7'; pfk8 = '\\eE8';\n        pfk9 = '\\eE9'; pfk10 = '\\eE0'; pfk11 = '\\eE-'; pfk12 = '\\eE=';\n        pfk13 = '\\eE!'; pfk14 = '\\eE@'; pfk15 = '\\eE#'; pfk16 = '\\eE$';\n        pfk17 = '\\eE%'; pfk18 = '\\eE'; pfk19 = '\\eE&'; pfk20 = '\\eE*';\n        pfk21 = '\\eE('; pfk22 = '\\eE)'; pfk23 = '\\eE_'; pfk24 = '\\eE+';\n        }\n.fi\n.SH \"IBM 3270 KEY DEFINITONS FOR AN ABOVE DEFINITION\"\nThe charts below show the proper keys to emulate\neach 3270 function when using the default key mapping supplied\nwith\n.IR tn3270 (1)\nand\n.IR mset (1).\n.sp\n.nf\n     Command Keys             IBM 3270 Key                  Default Key(s)\n                              Enter                         RETURN\n                              Clear                         control-z\n     Cursor Movement Keys\n                              New Line                      control-n or\n                                                            Home\n                              Tab                           control-i\n                              Back Tab                      control-b\n                              Cursor Left                   control-h\n                              Cursor Right                  control-l\n                              Cursor Up                     control-k\n                              Cursor Down                   control-j or\n                                                            LINE FEED\n     Edit Control Keys\n                              Delete Char                   control-d or\n                                                            RUB\n                              Erase EOF                     control-e\n                              Erase Input                   control-w\n                              Insert Mode                   ESC Space\n                              End Insert                    ESC Space\n     Program Function Keys\n                              PF1                           ESC 1\n                              PF2                           ESC 2\n                              ...                           ...\n                              PF10                          ESC 0\n                              PF11                          ESC -\n                              PF12                          ESC =\n                              PF13                          ESC !\n                              PF14                          ESC @\n                              ...                           ...\n                              PF24                          ESC +\n     Program Attention Keys\n                              PA1                           control-p 1\n                              PA2                           control-p 2\n                              PA3                           control-p 3\n     Local Control Keys\n                              Reset After Error             control-r\n                              Purge Input Buffer            control-x\n                              Keyboard Unlock               control-t\n                              Redisplay Screen              control-v\n     Other Keys\n\t\t\t      Erase current field           control-u\n.fi\n.SH FILES\n/usr/share/misc/map3270\n.SH SEE ALSO\ntn3270(1), mset(1), \\fIYale ASCII Terminal Communication\nSystem II Program Description/Operator's Manual\\fR\n(IBM SB30-1911)\n.SH AUTHOR\nGreg Minshall\n.SH BUGS\n.I Tn3270\ndoesn't yet understand how to process all the functions\navailable in\n.I map3270;\nwhen such a function is requested \n.I tn3270\nwill beep at you.\n.PP\nThe definition of \"word\" (for \"word delete\", \"word tab\") should be a run-time\noption.  Currently it is defined as the kernel tty driver defines it (strings\nof non-blanks); more than one person would rather use the \"vi\" definition\n(strings of specials, strings of alphanumeric).\n"
  },
  {
    "path": "share/man/man5/networks.5",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)networks.5\t6.2 (Berkeley) 5/6/86\n.\\\"\n.TH NETWORKS 5  \"May 6, 1986\"\n.UC 5\n.SH NAME\nnetworks \\- network name data base\n.SH DESCRIPTION\nThe\n.I networks\nfile contains information regarding\nthe known networks which comprise the DARPA Internet.\nFor each network a single line should be present with the following information:\n.HP 10\nofficial network name\n.br\n.ns\n.HP 10\nnetwork number\n.br\n.ns\n.HP 10\naliases\n.PP\nItems are separated by any number of blanks and/or tab characters.\nA ``#'' indicates the beginning of a comment; characters up to the end of\nthe line are not interpreted by routines which search the file.\nThis file is normally created from the official network data base\nmaintained at the Network Information Control Center (NIC), though local\nchanges may be required to bring it up to date regarding unofficial aliases\nand/or unknown networks.\n.PP\nNetwork number may be specified in the conventional\n``.'' notation using the \\fIinet_network\\fP() routine\nfrom the Internet address manipulation library,\n.IR inet (3N).\nNetwork names may contain any printable character other than a field\ndelimiter, newline, or comment character.\n.SH FILES\n/etc/networks\n.SH \"SEE ALSO\"\ngetnetent(3N)\n.SH BUGS\nA name server should be used instead of a static file.\n"
  },
  {
    "path": "share/man/man5/passwd.5",
    "content": ".\\\" Copyright (c) 1988 The Regents of the University of California.\n.\\\" All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms are permitted\n.\\\" provided that the above copyright notice and this paragraph are\n.\\\" duplicated in all such forms and that any documentation,\n.\\\" advertising materials, and other materials related to such\n.\\\" distribution and use acknowledge that the software was developed\n.\\\" by the University of California, Berkeley.  The name of the\n.\\\" University may not be used to endorse or promote products derived\n.\\\" from this software without specific prior written permission.\n.\\\" THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n.\\\" IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n.\\\" WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n.\\\"\n.\\\"\t@(#)passwd.5\t6.5 (Berkeley) 5/8/89\n.\\\"\n.TH PASSWD 5  \"May 8, 1989\"\n.AT 3\n.SH NAME\npasswd \\- password files\n.SH DESCRIPTION\n.I Passwd\nfiles are files consisting of newline separated records, one per user,\ncontaining ten colon (``:'') separated fields.  These fields are as\nfollows:\n.PP\n.RS\n name\t\tuser's login name\n password\t\tuser's \\fIencrypted\\fP password\n uid\t\t\tuser's id\n gid\t\t\tuser's login group id\n class\t\tuser's general classification (unused)\n change\t\tpassword change time\n expire\t\taccount expiration time\n gecos\t\tgeneral information about the user\n home_dir\t\tuser's home directory\n shell\t\tuser's login shell\n.RE\n.PP\nThe\n.I name\nfield is the login used to access the computer account, and the\n.I uid\nfield is the number associated with it.  They should both be unique\nacross the system (and often across a group of systems) since they\ncontrol file access.\n.PP\nWhile it is possible to have multiple entries with identical login names\nand/or identical user id's, it is usually a mistake to do so.  Routines\nthat manipulate these files will often return only one of the multiple\nentries, and that one by random selection.\n.PP\nThe login name must never begin with a hyphen (``-''); also, it is strongly\nsuggested that neither upper-case characters or dots (``.'') be part\nof the name, as this tends to confuse mailers.  No field may contain a\ncolon (``:'') as this has been used historically to separate the fields\nin the user database.\n.PP\nThe password field is the\n.I encrypted\nform of the password.\nIf the\n.I password\nfield is empty, no password will be required to gain access to the\nmachine.  This is almost invariably a mistake.\nBecause these files contain the encrypted user passwords, they should\nnot be readable by anyone without appropriate privileges.\n.PP\nThe group field is the group that the user will be placed in upon login.\nSince this system supports multiple groups (see\n.IR groups (1))\nthis field currently has little special meaning.\n.PP\nThe\n.I class\nfield is currently unused.  In the near future it will be a key to\na\n.IR termcap (5)\nstyle database of user attributes.\n.PP\nThe\n.I change\nfield is the number in seconds, GMT, from the epoch, until the\npassword for the account must be changed.\nThis field may be left empty to turn off the password aging feature.\n.PP\nThe\n.I expire\nfield is the number in seconds, GMT, from the epoch, until the\naccount expires.\nThis field may be left empty to turn off the account aging feature.\n.PP\nThe\n.I gecos\nfield normally contains comma (``,'') separated subfields as follows:\n.PP\n.RS\n name\t\tuser's full name\n office\t\tuser's office number\n wphone\t\tuser's work phone number\n hphone\t\tuser's home phone number\n.RE\n.PP\nThis information is used by the\n.IR finger (1)\nprogram.\n.PP\nThe user's home directory is the full UNIX path name where the user\nwill be placed on login.\n.PP\nThe shell field is the command interpreter the user prefers.\nIf the\n.I shell\nfield is empty, the Bourne shell (\\fI/bin/sh\\fP) is assumed.\n.SH \"SEE ALSO\"\nchpass(1), login(1), passwd(1), getpwent(3), mkpasswd(8), vipw(8) adduser(8)\n.SH BUGS\nUser information should (and eventually will) be stored elsewhere.\n"
  },
  {
    "path": "share/man/man5/phones.5",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)phones.5\t6.2 (Berkeley) 5/16/86\n.\\\"\n.TH PHONES 5 \"May 16, 1986\"\n.UC 5\n.SH NAME\nphones \\- remote host phone number data base\n.SH DESCRIPTION\nThe file /etc/phones contains the system-wide\nprivate phone numbers for the\n.IR tip (1C)\nprogram.  This file is normally unreadable, and so may contain\nprivileged information.  The format of the file is a series of lines\nof the form: <system-name>[\\ \\et]*<phone-number>.  The system name is\none of those defined in the\n.IR remote (5)\nfile and the phone number is constructed from any sequence of\ncharacters terminated only by ``,'' or the end of the line.\nThe ``='' and ``*'' characters are\nindicators to the auto call units to pause and wait for a second dial\ntone (when going through an exchange).  The ``='' is required by the\nDF02-AC and the ``*'' is required by the BIZCOMP 1030.\n.PP\nOnly one phone number per line is permitted.  However, if more than\none line in the file contains the same system name\n.IR tip (1C)\nwill attempt to dial each one in turn, until it establishes a connection.\n.SH FILES\n/etc/phones\n.SH \"SEE ALSO\"\ntip(1C),\nremote(5)\n"
  },
  {
    "path": "share/man/man5/plot.5",
    "content": ".\\\"\t@(#)plot.5\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH PLOT 5  \"May 15, 1985\"\n.AT 3\n.SH NAME\nplot \\- graphics interface\n.SH DESCRIPTION\nFiles of this format are produced by routines\ndescribed in \n.IR plot (3X)\nand\n.IR plot (3F),\nand are interpreted for various devices\nby commands described in\n.IR  plot (1G).\nA graphics file is a stream of plotting instructions.\nEach instruction consists of an ASCII letter\nusually followed by bytes of binary information.\nThe instructions are executed in order.\nA point is designated by\nfour bytes representing\nthe\nx and y\nvalues;\neach value\nis a signed integer.\nThe last designated point in an\n.B \"l, m, n, a,\"\nor\n.B p\ninstruction becomes the `current point'\nfor the next instruction.\nThe\n.B a\nand\n.B c\ninstructions change the current point in a manner dependent\nupon the specific device.\n.PP\nEach of the following descriptions begins with the name\nof the corresponding routine in\n.IR  plot (3X).\n.TP 3\n.B  m\nmove: The next four bytes give a new current point.\n.TP 3\n.B  n\ncont: Draw a line from the current point to\nthe point given by the next four bytes.\n.TP 3\n.B  p\npoint: Plot the point given by the next four bytes.\n.TP 3\n.B  l\nline: Draw a line from the point given by the next\nfour bytes to the point given by the following four bytes.\n.TP 3\n.B  t\nlabel: Place the following ASCII string so that its\nfirst character falls on the current point.\nThe string is terminated by a newline.\n.TP 3\n.B  a\narc:\nThe first four bytes give the center, the next four give the\nstarting point,\nand the last four give the end point of a circular arc.\nThe least significant coordinate of the end point is\nused only to determine the quadrant.\nThe arc is drawn counter-clockwise.\n.TP 3\n.B  c\ncircle:\nThe first four bytes give the center of the circle,\nthe next two the radius.\n.TP 3\n.B  e\nerase: Start another frame of output.\n.TP 3\n.B  f\nlinemod: Take the following string, up to a newline,\nas the style for drawing further lines.\nThe styles are\n`dotted,'\n`solid,' `longdashed,' `shortdashed,' and `dotdashed.'\nEffective only in \n.I plot 4014\nand\n.I plot ver.\n.TP 3\n.B  s\nspace: The next four bytes give\nthe lower left corner of the plotting area;\nthe following four give the upper right corner.\nThe plot will be magnified or reduced to fit\nthe device as closely as possible.\n.IP\nSpace settings that exactly fill the plotting area\nwith unity scaling appear below for\ndevices supported by the filters of\n.IR  plot (1G).\nThe upper limit is just outside the plotting area.\nIn every case the plotting area is taken to be square;\npoints outside may be displayable on\ndevices whose face isn't square.\n.RS\n.TP 10n\n4013\nspace(0, 0, 780, 780);\n.br\n.ns\n.TP 10n\n4014\nspace(0, 0, 3120, 3120);\n.br\n.ns\n.TP \nver\nspace(0, 0, 2048, 2048);\n.br\n.ns\n.TP \n300, 300s\nspace(0, 0, 4096, 4096);\n.br\n.ns\n.TP \n450\nspace(0, 0, 4096, 4096);\n.RE\n.SH \"SEE ALSO\"\nplot(1G), plot(3X), plot(3F), graph(1G)\n"
  },
  {
    "path": "share/man/man5/printcap.5",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)printcap.5\t6.4 (Berkeley) 5/14/86\n.\\\"\n.TH PRINTCAP 5 \"May 14, 1986\"\n.UC 5\n.ad\n.SH NAME\nprintcap \\- printer capability data base\n.SH SYNOPSIS\n/etc/printcap\n.SH DESCRIPTION\n.I Printcap\nis a simplified version of the\n.IR termcap (5)\ndata base\nused to describe line printers.  The spooling system accesses the\n.I printcap\nfile every time it is used, allowing dynamic\naddition and deletion of printers.  Each entry in the data base\nis used to describe one printer.  This data base may not be\nsubstituted for, as is possible for \n.IR termcap ,\nbecause it may allow accounting to be bypassed.\n.PP\nThe default printer is normally \n.IR lp ,\nthough the environment variable PRINTER\nmay be used to override this.  Each spooling utility supports an option,\n.BI \\-P printer,\nto allow explicit naming of a destination printer.\n.PP\nRefer to the\n.ul\n4.3BSD Line Printer Spooler Manual\nfor a complete discussion on how setup the database for a given printer.\n.SH CAPABILITIES\nRefer to\n.IR termcap (5)\nfor a description of the file layout.\n.nf\n\n.ta \\w'k0-k9  'u +\\w'Type  'u +\\w'``/usr/spool/lpd\\'\\'  'u\n\\fBName\tType\tDefault\tDescription\\fR\naf\tstr\tNULL\tname of accounting file\nbr\tnum\tnone\tif lp is a tty, set the baud rate (ioctl call)\ncf\tstr\tNULL\tcifplot data filter\ndf\tstr\tNULL\ttex data filter (DVI format)\nfc\tnum\t0\tif lp is a tty, clear flag bits (sgtty.h)\nff\tstr\t``\\ef''\tstring to send for a form feed\nfo\tbool\tfalse\tprint a form feed when device is opened\nfs\tnum\t0\tlike `fc' but set bits\ngf\tstr\tNULL\tgraph data filter (plot (3X) format)\nhl\tbool\tfalse\tprint the burst header page last\nic\tbool\tfalse\tdriver supports (non standard) ioctl to indent printout\nif\tstr\tNULL\tname of text filter which does accounting\nlf\tstr\t``/dev/console''\terror logging file name\nlo\tstr\t``lock''\tname of lock file\nlp\tstr\t``/dev/lp''\tdevice name to open for output\nmx\tnum\t1000\tmaximum file size (in BUFSIZ blocks), zero = unlimited\nnd\tstr\tNULL\tnext directory for list of queues (unimplemented)\nnf\tstr\tNULL\tditroff data filter (device independent troff)\nof\tstr\tNULL\tname of output filtering program\npc\tnum\t200\tprice per foot or page in hundredths of cents\npl\tnum\t66\tpage length (in lines)\npw\tnum\t132\tpage width (in characters)\npx\tnum\t0\tpage width in pixels (horizontal)\npy\tnum\t0\tpage length in pixels (vertical)\nrf\tstr\tNULL\tfilter for printing FORTRAN style text files\nrg\tstr\tNULL\trestricted group. Only members of group allowed access\nrm\tstr\tNULL\tmachine name for remote printer\nrp\tstr\t``lp''\tremote printer name argument\nrs\tbool\tfalse\trestrict remote users to those with local accounts\nrw\tbool\tfalse\topen the printer device for reading and writing\nsb\tbool\tfalse\tshort banner (one line only)\nsc\tbool\tfalse\tsuppress multiple copies\nsd\tstr\t``/usr/spool/lpd''\tspool directory\nsf\tbool\tfalse\tsuppress form feeds\nsh\tbool\tfalse\tsuppress printing of burst page header\nst\tstr\t``status''\tstatus file name\ntf\tstr\tNULL\ttroff data filter (cat phototypesetter)\ntr\tstr\tNULL\ttrailer string to print when queue empties\nvf\tstr\tNULL\traster image filter\nxc\tnum\t0\tif lp is a tty, clear local mode bits (tty (4))\nxs\tnum\t0\tlike `xc' but set bits\n.fi\n.PP\nIf the local line printer driver supports indentation, the daemon\nmust understand how to invoke it.\n.SH FILTERS\nThe\n.IR lpd (8)\ndaemon creates a pipeline of\n.I filters\nto process files for various printer types.\nThe filters selected depend on the flags passed to\n.IR lpr (1).\nThe pipeline set up is:\n.RS\n.PP\n.nf\n.ta 0.5i +1i\n\\-p\tpr | if\tregular text + \\fIpr\\fP(1)\nnone\tif\tregular text\n\\-c\tcf\tcifplot\n\\-d\tdf\tDVI (tex)\n\\-g\tgf\t\\fIplot\\fP(3)\n\\-n\tnf\tditroff\n\\-f\trf\tFortran\n\\-t\ttf\ttroff\n\\-v\tvf\traster image\n.fi\n.RE\n.PP\nThe\n.B if\nfilter is invoked with arguments:\n.PP\n\t\\fIif\\fP [ \\fB\\-c\\fP ] \\fB\\-w\\fPwidth \\fB\\-l\\fPlength \\fB\\-i\\fPindent \\fB\\-n\\fP login \\fB\\-h\\fP host acct-file\n.PP\nThe\n.B \\-c\nflag is passed only if the\n.B \\-l\nflag (pass control characters literally)\nis specified to\n.IR lpr .\n.I Width\nand\n.I length\nspecify the page width and length\n(from\n.B pw\nand\n.B pl\nrespectively) in characters.\nThe\n.B \\-n\nand\n.B \\-h\nparameters specify the login name and host name of the owner\nof the job respectively.\n.I Acct-file\nis passed from the\n.B af\n.I printcap\nentry.\n.PP\nIf no\n.B if\nis specified,\n.B of\nis used instead,\nwith the distinction that\n.B of\nis opened only once,\nwhile\n.B if\nis opened for every individual job.\nThus,\n.B if\nis better suited to performing accounting.\nThe\n.B of\nis only given the\n.I width\nand\n.I length\nflags.\n.PP\nAll other filters are called as:\n.PP\n\t\\fIfilter\\fP \\fB\\-x\\fPwidth \\fB\\-y\\fPlength \\fB\\-n\\fP login \\fB\\-h\\fP host acct-file\n.PP\nwhere\n.I width\nand\n.I length\nare represented in pixels,\nspecified by the\n.B px\nand\n.B py\nentries respectively.\n.PP\nAll filters take\n.I stdin\nas the file,\n.I stdout\nas the printer,\nmay log either to\n.I stderr\nor using\n.IR syslog (3),\nand must not ignore\n.SM SIGINT.\n.SH LOGGING\nError messages generated by the line printer programs themselves\n(that is, the\n.IR lp *\nprograms)\nare logged by\n.IR syslog (3)\nusing the\n.I LPR\nfacility.\nMessages printed on\n.I stderr\nof one of the filters\nare sent to the corresponding\n.B lf\nfile.\nThe filters may, of course, use\n.I syslog\nthemselves.\n.PP\nError messages sent to the console have a carriage return and a line\nfeed appended to them, rather than just a line feed.\n.SH \"SEE ALSO\"\ntermcap(5),\nlpc(8),\nlpd(8),\npac(8),\nlpr(1),\nlpq(1),\nlprm(1)\n.br\n.ul\n4.3BSD Line Printer Spooler Manual\n"
  },
  {
    "path": "share/man/man5/protocols.5",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)protocols.5\t6.2 (Berkeley) 5/6/86\n.\\\"\n.TH PROTOCOLS 5  \"May 6, 1986\"\n.UC 5\n.SH NAME\nprotocols \\- protocol name data base\n.SH DESCRIPTION\nThe\n.I protocols\nfile contains information regarding the known protocols used in the DARPA\nInternet.  For each protocol a single line should be present\nwith the following information:\n.HP 10\nofficial protocol name\n.br\n.ns\n.HP 10\nprotocol number\n.br\n.ns\n.HP 10\naliases\n.PP\nItems are separated by any number of blanks and/or\ntab characters.  A ``#'' indicates the beginning of\na comment; characters up to the end of the line are\nnot interpreted by routines which search the file.\n.PP\nProtocol names may contain any printable\ncharacter other than a field delimiter, newline,\nor comment character.\n.SH FILES\n/etc/protocols\n.SH \"SEE ALSO\"\ngetprotoent(3N)\n.SH BUGS\nA name server should be used instead of a static file.\n"
  },
  {
    "path": "share/man/man5/remote.5",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)remote.5\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH REMOTE 5 \"May 15, 1985\"\n.UC 5\n.SH NAME\nremote \\- remote host description file\n.SH DESCRIPTION\nThe systems known by\n.IR tip (1C)\nand their attributes are stored in an ASCII file which\nis structured somewhat like the\n.IR termcap (5)\nfile.  Each line in the file provides a description for a single\n.IR system .\nFields are separated by a colon (``:'').\nLines ending in a \\e character with an immediately following newline are\ncontinued on the next line.\n.PP\nThe first entry is the name(s) of the host system.  If there is more\nthan one name for a system, the names are separated by vertical bars.\nAfter the name of the system comes the fields of the description.  A\nfield name followed by an `=' sign indicates a string value follows.  A field\nname followed by a `#' sign indicates a following numeric value.\n.PP\nEntries named ``tip*'' and ``cu*''\nare used as default entries by \n.IR tip ,\nand the\n.I cu\ninterface to \n.IR tip ,\nas follows.  When\n.I tip\nis invoked with only a phone number, it looks for an entry\nof the form ``tip300'', where 300 is the baud rate with\nwhich the connection is to be made.  When the\n.I cu\ninterface is used, entries of the form ``cu300'' are used.\n.SH CAPABILITIES\nCapabilities are either strings (str), numbers (num), or boolean\nflags (bool).  A string capability is specified by \n.IR capability = value ;\ne.g. ``dv=/dev/harris''.  A numeric capability is specified by\n.IR capability # value ;\ne.g. ``xa#99''.  A boolean capability is specified by simply listing\nthe capability.\n.TP 0.5i\n.B at\n(str)\nAuto call unit type.\n.TP 0.5i\n.B br\n(num)\nThe baud rate used in establishing\na connection to the remote host.\nThis is a decimal number. \nThe default baud rate is 300 baud.\n.TP 0.5i\n.B cm\n(str)\nAn initial connection message to be sent\nto the remote host.  For example, if a\nhost is reached through port selector, this\nmight be set to the appropriate sequence\nrequired to switch to the host.\n.TP 0.5i\n.B cu\n(str)\nCall unit if making a phone call.\nDefault is the same as the `dv' field.\n.TP 0.5i\n.B di\n(str)\nDisconnect message sent to the host when a\ndisconnect is requested by the user.\n.TP 0.5i\n.B du\n(bool)\nThis host is on a dial-up line. \n.TP 0.5i\n.B dv\n(str)\nUNIX device(s) to open to establish a connection. \nIf this file refers to a terminal line,\n.IR tip (1C)\nattempts to perform an exclusive open on the device to insure only\none user at a time has access to the port.\n.TP 0.5i\n.B el\n(str)\nCharacters marking an end-of-line. \nThe default is NULL.  `~' escapes are only\nrecognized by\n.I tip\nafter one of the characters in `el',\nor after a carriage-return.\n.TP 0.5i\n.B fs\n(str)\nFrame size for transfers. \nThe default frame size is equal to BUFSIZ.\n.TP 0.5i\n.B hd\n(bool)\nThe host uses half-duplex communication, local\necho should be performed.\n.TP 0.5i\n.B ie\n(str)\nInput end-of-file marks.\nThe default is NULL.\n.TP 0.5i\n.B oe\n(str)\nOutput end-of-file string.\nThe default is NULL.  When \n.I tip\nis transferring a file, this\nstring is sent at end-of-file.\n.TP 0.5i\n.B pa\n(str)\nThe type of parity to use when sending data\nto the host.  This may be one of ``even'',\n``odd'', ``none'', ``zero'' (always set bit 8 to zero),\n``one'' (always set bit 8 to 1).  The default\nis even parity.\n.TP 0.5i\n.B pn\n(str)\nTelephone number(s) for this host.\nIf the telephone number field contains\nan @ sign, \n.I tip\nsearches the file\n.I /etc/phones\nfile for a list of telephone numbers;\nc.f.\n.IR phones (5).\n.TP 0.5i\n.B tc\n(str)\nIndicates that the list of capabilities is continued\nin the named description.  This is used\nprimarily to share common capability information.\n.PP\nHere is a short example showing the use of the capability continuation\nfeature:\n.PP\n.nf\n.ta 0.5i\nUNIX-1200:\\e\n\t:dv=/dev/cau0:el=^D^U^C^S^Q^O@:du:at=ventel:ie=#$%:oe=^D:br#1200:\narpavax|ax:\\e\n\t:pn=7654321%:tc=UNIX-1200\n.fi\n.SH FILES\n/etc/remote\n.SH \"SEE ALSO\"\ntip(1C),\nphones(5)\n"
  },
  {
    "path": "share/man/man5/resolver.5",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)resolver.5\t1.6 (Berkeley) 9/14/87\n.\\\"\n.TH RESOLVER 5 \"September 14, 1987\"\n.UC 4\n.SH NAME\nresolver \\- resolver configuration file\n.SH SYNOPSIS\n/etc/resolv.conf\n.SH DESCRIPTION\n.LP\nThe resolver configuration file contains information that is read\nby the resolver routines the first time they are invoked by a process.\nThe file is designed to be human readable and contains a list of\nname-value pairs that provide various types of resolver information.\n.LP\nOn a normally configured system this file should not be necessary.\nThe only name server to be queried will be on the local machine and \nthe domain name is retrieved from the system.\n.LP\nThe different configuration options are:\n.TP\n\\fBnameserver\\fP\nfollowed by the Internet address (in dot notation) of a name server\nthat the resolver should query.  At least one name server should be\nlisted.  Up to MAXNS (currently 3) name servers may be listed, in that\ncase the resolver library queries tries them in the order listed.\nIf no \\fBnameserver\\fP entries are present,\nthe default is to use the name server on the local machine.\n(The algorithm used is to try a name server, and if the query times out,\ntry the next, until out of name servers,\nthen repeat trying all the name servers\nuntil a maximum number of retries are made).\n.TP\n\\fBdomain\\fP\nfollowed by a domain name, that is\nthe default domain to append to names that do not have a dot in them.\nIf no \\fBdomain\\fP entries are present, the domain returned by\n\\fIgethostname\\fP\\|(2) is used (everything after the first `.').\nFinally, if the host name does not contain a domain part, the root\ndomain is assumed.\n.LP\nThe name value pair must appear on a single line, and the keyword\n(e.g. \\fBnameserver\\fP) must start the line.  The value follows\nthe keyword, separated by white space.\n.SH FILES\n.I /etc/resolv.conf\n.SH SEE ALSO\ngethostbyname(3N), resolver(3), named(8)\n.br\nName Server Operations Guide for BIND\n"
  },
  {
    "path": "share/man/man5/services.5",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)services.5\t6.2 (Berkeley) 5/6/86\n.\\\"\n.TH SERVICES 5  \"May 6, 1986\"\n.UC 5\n.SH NAME\nservices \\- service name data base\n.SH DESCRIPTION\nThe\n.I services\nfile contains information regarding\nthe known services available in the DARPA Internet.\nFor each service a single line should be present\nwith the following information:\n.HP 10\nofficial service name\n.br\n.ns\n.HP 10\nport number\n.br\n.ns\n.HP 10\nprotocol name\n.br\n.ns\n.HP 10\naliases\n.PP\nItems are separated by any number of blanks and/or\ntab characters.  The port number and protocol name\nare considered a single \n.IR item ;\na ``/'' is used to\nseparate the port and protocol (e.g. ``512/tcp'').\nA ``#'' indicates the beginning of\na comment; characters up to the end of the line are\nnot interpreted by routines which search the file.\n.PP\nService names may contain any printable\ncharacter other than a field delimiter, newline,\nor comment character.\n.SH FILES\n/etc/services\n.SH \"SEE ALSO\"\ngetservent(3N)\n.SH BUGS\nA name server should be used instead of a static file.\n"
  },
  {
    "path": "share/man/man5/shells.5",
    "content": ".\\\" Copyright (c) 1986 The Regents of the University of California.\n.\\\" All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms are permitted\n.\\\" provided that the above copyright notice and this paragraph are\n.\\\" duplicated in all such forms and that any documentation,\n.\\\" advertising materials, and other materials related to such\n.\\\" distribution and use acknowledge that the software was developed\n.\\\" by the University of California, Berkeley.  The name of the\n.\\\" University may not be used to endorse or promote products derived\n.\\\" from this software without specific prior written permission.\n.\\\" THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n.\\\" IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n.\\\" WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n.\\\"\n.\\\"\t@(#)shells.5\t5.2 (Berkeley) 2/23/89\n.\\\"\n.TH SHELLS 5 \"February 23, 1989\"\n.UC 5\n.SH NAME\nshells \\- shell database\n.SH DESCRIPTION\nThe\n.I shells\nfile contains a list of the shells on the system.\nFor each shell a single line should be present, consisting of the\nshell's path, relative to root.\n.PP\nA hash mark (``#'') indicates the beginning of a comment; subsequent\ncharacters up to the end of the line are not interpreted by the\nroutines which search the file.\nBlank lines are also ignored.\n.SH FILES\n/etc/shells\n.SH \"SEE ALSO\"\ngetusershell(3)\n"
  },
  {
    "path": "share/man/man5/stack.5",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)stack.5\t2.3 (Berkeley) 6/24/87\n.\\\"\n.TH STACK 5 \"June 24, 1987\"\n.UC 2\n.SH NAME\nstack \\-  2.10BSD PDP-11 C stack frame conventions\n.SH DESCRIPTION\nThe standard C stack frame layout:\n.RS\n.nf\n.ta 8 16 24 32 40 48 56 64\n\n------------------\n|...nth argument |\t\tpush arguments in reverse order\n------------------\n|second argument |\n------------------\n| first argument |\n------------------\t\tJSR PC,*$_FOO\n| return address |\n------------------\t\tJSR R5,CSV\n|  old R5 value  | <----- \n------------------\t|\n|previous overlay|\t|\n|     number\t |\t|\n------------------\t|\n|\tr4\t |\t|\n------------------\t|\n|\tr3\t |\t|\n------------------\t|\n|\tr2\t |\t|\n------------------\t|\n| first local var|\t| This is the top of the stack\n------------------\t| when the called routine ``starts''\n|     routine\t |\t|\n|    allocates\t |\t|\n|     storage\t |\t|\tSUB $n,SP\n|    temporary\t |\t|\n------------------\t|\n| push arguments |\t|\n| of next routine|\t|\n------------------\t|\tJSR PC,*$_BAR\n| return address |\t|\n------------------\t|\tJSR R5,CSV\n| old R5 value---+-------\n------------------\t^\n|previous overlay|\t|\n|     number\t |\t|\n------------------\t|\n| r4/43/r2/...\t |\t|\n------------------\n| and so on..... |\n\n.fi\n.RE\n.DT\n.PP\nThe stack pushes downward through memory addresses.  Overlay numbers saved\nin non-overlaid objects are always zero, but the simplification of not\nhaving to maintain two different stack frame formats more than outweighs\nthe extra few micro seconds (less than four) necessary to save the zero ...\n.PP\nFunctions returning integers leave their return value in R0; functions\nreturning floating constants use FR0; functions returning longs leave\nreturn values in R1/R0 (R0 high word, R1 low); functions returning\nstructures leave a pointer to bss storage (one chunk of which is allocated\nfor each such routine) in R0, and the caller will copy from that bss\nstorage to the local destination.\n.PP\nLocal variables are allocated in such a way that they are referred to as\n``-N(R5)'', arguments are referred to as ``+N(R5)''; arguments start at\n4(R5), the first integer local declared will be at -10(R5).\n.PP\nThe SP normally points at the first word available for parameter pushing.\nA function taking only single word as a parameter can be called simply by\nmoving the parameter into (SP) and calling the function, without having to\nclean the parameter off the stack on return.  Any parameters passed after\nthe first (actually \"Nth\") must be pushed before the call and cleaned off\nafterwards.  If the function has no local variables and calls no functions,\nit will allocate no stack and the word labelled ``first local var'' will be unused.\n.PP\nIt is important to note that routines know how many arguments they pass to a\nfunction, and will adjust the stack accordingly after a function returns.\n.SH NOTE\nThis stack frame format is the same as that used by overlaid objects in\n2.9BSD.\n.SH AUTHOR\nJohn F. Woods, MIT Concouse Computer Center\n"
  },
  {
    "path": "share/man/man5/syserrlst.5",
    "content": ".\\\" Public Domain, March 196, Steven M. Schultz\n.\\\"\n.\\\"\t@(#)syserrlst.5\t1.0 (2.11BSD) 1996/3/7\n.\\\"\n.TH SYSERRLST 5  \"March 7, 1996\"\n.UC 2\n.SH NAME\nsyserrlst \\- error message file format\n.SH DESCRIPTION\n.IR mkerrlst (1),\ncreates error message files in the format described below.\n.PP\nAn ``error message file'' consists of a header, an array of structures\nspecifying the offset and length of each message, and the array of\nmessage strings separated by newlines.\n.PP\nThe message strings are separated by newlines but the newline characters\nare \\fBnot\\fP included in the size of the message.  These newline characters\nserve only to make the file editable or printable (after stripping off the\nheader).\n.PP\nThe file format is:\n.PP\n.nf\n.cs R 20\n/*\n * Definitions used by the 'mkerrlst' program which creates error message \n * files.\n *\n * The format of the file created is:\n *\n *\tstruct\tERRLSTHDR ehdr;\n *\tstruct\tERRLST  emsg[num_of_messages];\n *\tstruct\t{\n *\t\tchar\tmsg[] = \"error message string\";\n *\t\tchar\tlf = '\\n';\n *\t\t} [num_of_messages];\n *\n * Note:  the newlines are NOT included in the message lengths, the newlines\n *        are present to make it easy to 'cat' or 'vi' the file.\n*/\n\n\tstruct\tERRLSTHDR\n\t\t{\n\t\tshort\tmagic;\n\t\tshort\tmaxmsgnum;\n\t\tshort\tmaxmsglen;\n\t\tshort\tpad[5];\t\t/* Reserved */\n\t\t};\n\n\tstruct\tERRLST\n\t\t{\n\t\toff_t\toffmsg;\n\t\tshort\tlenmsg;\n\t\t};\n\n#define\tERRMAGIC\t012345\n.fi\n.cs R\n.SH \"SEE ALSO\"\nmkerrlst(1), syserrlst(3)\n.SH BUGS\nFormat of the file isn't necessarily portable between machines.\n.SH HISTORY\nThis file format is new with 2.11BSD.\n"
  },
  {
    "path": "share/man/man5/tar.5",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)tar.5\t6.2 (Berkeley) 11/7/85\n.\\\"\n.TH TAR 5  \"November 7, 1985\"\n.UC 5\n.SH NAME\ntar \\- tape archive file format\n.SH DESCRIPTION\n.IR Tar ,\n(the tape archive command)\ndumps several files into one, in a medium suitable for transportation.\n.PP\nA ``tar tape'' or file is a series of blocks.  Each block is of size TBLOCK.\nA file on the tape is represented by a header block which describes\nthe file, followed by zero or more blocks which give the contents of the\nfile.  At the end of the tape are two blocks filled with binary\nzeros, as an end-of-file indicator.  \n.PP\nThe blocks are grouped for physical I/O operations.  Each group of\n.I n\nblocks (where\n.I n\nis set by the \n.B b\nkeyletter on the \n.IR tar (1)\ncommand line \\(em default is 20 blocks) is written with a single system\ncall; on nine-track tapes, the result of this write is a single tape\nrecord.  The last group is always written at the full size, so blocks after\nthe two zero blocks contain random data.  On reading, the specified or\ndefault group size is used for the\nfirst read, but if that read returns less than a full tape block, the reduced\nblock size is used for further reads.\n.PP\nThe header block looks like:\n.RS\n.PP\n.nf\n#define TBLOCK\t512\n#define NAMSIZ\t100\n\nunion hblock {\n\tchar dummy[TBLOCK];\n\tstruct header {\n\t\tchar name[NAMSIZ];\n\t\tchar mode[8];\n\t\tchar uid[8];\n\t\tchar gid[8];\n\t\tchar size[12];\n\t\tchar mtime[12];\n\t\tchar chksum[8];\n\t\tchar linkflag;\n\t\tchar linkname[NAMSIZ];\n\t} dbuf;\n};\n.ta \\w'#define 'u +\\w'SARMAG 'u\n.fi\n.RE\n.LP\n.IR Name\nis a null-terminated string.\nThe other fields are zero-filled octal numbers in ASCII.  Each field\n(of width w) contains w-2 digits, a space, and a null, except\n.IR size\nand\n.IR mtime ,\nwhich do not contain the trailing null and\n.IR chksum\nwhich has a null followed by a space.\n.IR Name\nis the name of the file, as specified on the \n.I tar\ncommand line.  Files dumped because they were in a directory which\nwas named in the command line have the directory name as prefix and\n.I /filename\nas suffix.\n.  \\\"Whatever format was used in the command line\n.  \\\"will appear here, such as\n.  \\\".I \\&./yellow\n.  \\\"or\n.  \\\".IR \\&../../brick/./road/.. .\n.  \\\"To retrieve a file from a tar tape, an exact prefix match must be specified,\n.  \\\"including all of the directory prefix information used on the command line\n.  \\\"that dumped the file (if any).\n.IR Mode\nis the file mode, with the top bit masked off.\n.IR Uid\nand\n.IR gid\nare the user and group numbers which own the file.\n.IR Size\nis the size of the file in bytes.  Links and symbolic links are dumped\nwith this field specified as zero.\n.IR Mtime\nis the modification time of the file at the time it was dumped.\n.IR Chksum\nis an octal ASCII value which represents the sum of all the bytes in the\nheader block.  When calculating the checksum, the \n.IR chksum\nfield is treated as if it were all blanks.\n.IR Linkflag\nis NULL if the file is ``normal'' or a special file, ASCII `1'\nif it is an hard link, and ASCII `2'\nif it is a symbolic link.  The name linked-to, if any, is in\n.IR linkname,\nwith a trailing null.\nUnused fields of the header are binary zeros (and are included in the\nchecksum).\n.PP\nThe first time a given i-node number is dumped, it is dumped as a regular\nfile.  The second and subsequent times, it is dumped as a link instead.\nUpon retrieval, if a link entry is retrieved, but not the file it was\nlinked to, an error message is printed and the tape must be manually\nre-scanned to retrieve the linked-to file.\n.PP\nThe encoding of the header is designed to be portable across machines.\n.SH \"SEE ALSO\"\ntar(1)\n.SH BUGS\nNames or linknames longer than NAMSIZ produce error reports and cannot be\ndumped.\n"
  },
  {
    "path": "share/man/man5/termcap.5",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)termcap.5\t6.4 (Berkeley) 5/15/86\n.\\\"\n.ie n \\{\\\n.\tds lq \\&\"\\\"\n.\tds rq \\&\"\\\"\n.\\}\n.el \\{\\\n.\tds rq ''\n.\tds lq ``\n.\\}\n.tr ||\n.tr *\\(**\n.hw trans-parently\n.TH TERMCAP 5 \"May 5, 1986\"\n.UC\n.SH NAME\ntermcap \\- terminal capability data base\n.SH SYNOPSIS\n/etc/termcap\n.SH DESCRIPTION\n.I Termcap\\^\nis a data base describing terminals,\nused,\n.IR e.g. ,\nby\n.IR vi\\^ (1)\nand\n.IR curses\\^ (3X).\nTerminals are described in\n.I termcap\\^\nby giving a set of capabilities that they have and by describing\nhow operations are performed.\nPadding requirements and initialization sequences\nare included in\n.IR termcap\\^ .\n.PP\nEntries in\n.I termcap\\^\nconsist of a number of `:'-separated fields.\nThe first entry for each terminal gives the names that are known for the\nterminal, separated by `|' characters.\nThe first name is always two characters\nlong and is used by older systems which store the terminal type\nin a 16-bit word in a system-wide data base.\nThe second name given is the most common abbreviation for the terminal,\nthe last name given should be a long name fully identifying the terminal,\nand all others are understood as synonyms for the terminal name.\nAll names but the first and last\nshould be in lower case and contain no blanks;\nthe last name may well contain\nupper case and blanks for readability.\n.PP\nTerminal names (except for the last, verbose entry)\nshould be chosen using the following conventions.\nThe particular piece of hardware making up the terminal\nshould have a root name chosen, thus \\*(lqhp2621\\*(rq.\nThis name should not contain hyphens.\nModes that the hardware can be in\nor user preferences\nshould be indicated by appending a hyphen and an indicator of the mode.\nTherefore, a \\*(lqvt100\\*(rq in 132-column mode would be \\*(lqvt100-w\\*(rq.\nThe following suffixes should be used where possible:\n.sp\n.ta\n.ta \\w'\\fBSuffix\\fP\\ \\ \\ 'u +\\w'With automatic margins (usually default)\\ \\ 'u\n.nf\n.if t \\{\\\n.nr Xx \\n(.lu-\\n(.i-\\w'\\fBSuffix\\fP\\ \\ \\ With automatic margins (usually default)\\ \\ vt100-am'u\n.in +\\n(Xxu/2u\n.\\}\n\\fBSuffix\tMeaning\tExample\\fP\n-w\tWide mode (more than 80 columns)\tvt100-w\n-am\tWith automatic margins (usually default)\tvt100-am\n-nam\tWithout automatic margins\tvt100-nam\n-\\fIn\\fP\tNumber of lines on the screen\taaa-60\n-na\tNo arrow keys (leave them in local)\tconcept100-na\n-\\fIn\\^\\fPp\tNumber of pages of memory\tconcept100-4p\n-rv\tReverse video\tconcept100-rv\n.fi\n.SH CAPABILITIES\n.PP\nThe characters in the\n.I Notes\nfield in the table have the following meanings\n(more than one may apply to a capability):\n.PP\n.ta\n.ta \\w'N\\ \\ \\ 'u\n.nf\nN\tindicates numeric parameter(s)\nP\tindicates that padding may be specified\n*\tindicates that padding may be based on the number of lines affected\no\tindicates capability is obsolete\n.fi\n.PP\n\\*(lqObsolete\\*(rq capabilities have no\n.I terminfo\\^\nequivalents,\nsince they were considered useless,\nor are subsumed by other capabilities.\nNew software should not rely on them at all.\n.PP\n.nf\n.ta \\w'\\fBName  \\fP'u +\\w'\\fBType  \\fP'u +\\w'\\fBNotes  \\fP'u\n\\fBName\tType\tNotes\tDescription\\fP\nae\tstr\t(P)\tEnd alternate character set\nAL\tstr\t(NP*)\tAdd \\fIn\\^\\fP new blank lines\nal\tstr\t(P*)\tAdd new blank line\nam\tbool\t\tTerminal has automatic margins\nas\tstr\t(P)\tStart alternate character set\nbc\tstr\t(o)\tBackspace if not \\fB^H\\fP\nbl\tstr\t(P)\tAudible signal (bell)\nbs\tbool\t(o)\tTerminal can backspace with \\fB^H\\fP\nbt\tstr\t(P)\tBack tab\nbw\tbool\t\t\\fBle\\fP (backspace) wraps from column 0 to last column\nCC\tstr\t\tTerminal settable command character in prototype\ncd\tstr\t(P*)\tClear to end of display\nce\tstr\t(P)\tClear to end of line\nch\tstr\t(NP)\tSet cursor column (horizontal position)\ncl\tstr\t(P*)\tClear screen and home cursor\nCM\tstr\t(NP)\tMemory-relative cursor addressing\ncm\tstr\t(NP)\tScreen-relative cursor motion\nco\tnum\t\tNumber of columns in a line (See BUGS section below)\ncr\tstr\t(P)\tCarriage return\ncs\tstr\t(NP)\tChange scrolling region (VT100)\nct\tstr\t(P)\tClear all tab stops\ncv\tstr\t(NP)\tSet cursor row (vertical position)\nda\tbool\t\tDisplay may be retained above the screen\ndB\tnum\t(o)\tMilliseconds of \\fBbs\\fP delay needed (default 0)\ndb\tbool\t\tDisplay may be retained below the screen\nDC\tstr\t(NP*)\tDelete \\fIn\\^\\fP characters\ndC\tnum\t(o)\tMilliseconds of \\fBcr\\fP delay needed (default 0)\ndc\tstr\t(P*)\tDelete character\ndF\tnum\t(o)\tMilliseconds of \\fBff\\fP delay needed (default 0)\nDL\tstr\t(NP*)\tDelete \\fIn\\^\\fP lines\ndl\tstr\t(P*)\tDelete line\ndm\tstr\t\tEnter delete mode\ndN\tnum\t(o)\tMilliseconds of \\fBnl\\fP delay needed (default 0)\nDO\tstr\t(NP*)\tMove cursor down \\fIn\\^\\fP lines\ndo\tstr\t\tDown one line\nds\tstr\t\tDisable status line\ndT\tnum\t(o)\tMilliseconds of horizontal tab delay needed (default 0)\ndV\tnum\t(o)\tMilliseconds of vertical tab delay needed (default 0)\nec\tstr\t(NP)\tErase \\fIn\\^\\fP characters\ned\tstr\t\tEnd delete mode\nei\tstr\t\tEnd insert mode\neo\tbool\t\tCan erase overstrikes with a blank\nEP\tbool\t(o)\tEven parity\nes\tbool\t\tEscape can be used on the status line\nff\tstr\t(P*)\tHardcopy terminal page eject\nfs\tstr\t\tReturn from status line\ngn\tbool\t\tGeneric line type (\\fIe.g.\\fP dialup, switch)\nhc\tbool\t\tHardcopy terminal\nHD\tbool\t(o)\tHalf-duplex\nhd\tstr\t\tHalf-line down (forward 1/2 linefeed)\nho\tstr\t(P)\tHome cursor\nhs\tbool\t\tHas extra \\*(lqstatus line\\*(rq\nhu\tstr\t\tHalf-line up (reverse 1/2 linefeed)\nhz\tbool\t\tCannot print ~s (Hazeltine)\ni1-i3\tstr\t\tTerminal initialization strings (\\fIterminfo\\^\\fP only)\nIC\tstr\t(NP*)\tInsert \\fIn\\^\\fP blank characters\nic\tstr\t(P*)\tInsert character\nif\tstr\t\tName of file containing initialization string\nim\tstr\t\tEnter insert mode\nin\tbool\t\tInsert mode distinguishes nulls\niP\tstr\t\tPathname of program for initialization (\\fIterminfo\\^\\fP only)\nip\tstr\t(P*)\tInsert pad after character inserted\nis\tstr\t\tTerminal initialization string (\\fItermcap\\^\\fP only)\nit\tnum\t\tTabs initially every \\fIn\\^\\fP positions\nK1\tstr\t\tSent by keypad upper left\nK2\tstr\t\tSent by keypad upper right\nK3\tstr\t\tSent by keypad center\nK4\tstr\t\tSent by keypad lower left\nK5\tstr\t\tSent by keypad lower right\nk0-k9\tstr\t\tSent by function keys 0-9\nkA\tstr\t\tSent by insert-line key\nka\tstr\t\tSent by clear-all-tabs key\nkb\tstr\t\tSent by backspace key\nkC\tstr\t\tSent by clear-screen or erase key\nkD\tstr\t\tSent by delete-character key\nkd\tstr\t\tSent by down-arrow key\nkE\tstr\t\tSent by clear-to-end-of-line key\nke\tstr\t\tOut of \\*(lqkeypad transmit\\*(rq mode\nkF\tstr\t\tSent by scroll-forward/down key\nkH\tstr\t\tSent by home-down key\nkh\tstr\t\tSent by home key\nkI\tstr\t\tSent by insert-character or enter-insert-mode key\nkL\tstr\t\tSent by delete-line key\nkl\tstr\t\tSent by left-arrow key\nkM\tstr\t\tSent by insert key while in insert mode\nkm\tbool\t\tHas a \\*(lqmeta\\*(rq key (shift, sets parity bit)\nkN\tstr\t\tSent by next-page key\nkn\tnum\t(o)\tNumber of function (\\fBk0\\fP\\-\\fBk9\\fP) keys (default 0)\nko\tstr\t(o)\tTermcap entries for other non-function keys\nkP\tstr\t\tSent by previous-page key\nkR\tstr\t\tSent by scroll-backward/up key\nkr\tstr\t\tSent by right-arrow key\nkS\tstr\t\tSent by clear-to-end-of-screen key\nks\tstr\t\tPut terminal in \\*(lqkeypad transmit\\*(rq mode\nkT\tstr\t\tSent by set-tab key\nkt\tstr\t\tSent by clear-tab key\nku\tstr\t\tSent by up-arrow key\nl0-l9\tstr\t\tLabels on function keys if not \\*(lqf\\fIn\\^\\fP\\*(rq\nLC\tbool\t(o)\tLower-case only\nLE\tstr\t(NP)\tMove cursor left \\fIn\\^\\fP positions\nle\tstr\t(P)\tMove cursor left one position\nli\tnum\t\tNumber of lines on screen or page (See BUGS section below)\nll\tstr\t\tLast line, first column\nlm\tnum\t\tLines of memory if > \\fBli\\fP (0 means varies)\nma\tstr\t(o)\tArrow key map (used by \\fIvi\\^\\fP version 2 only)\nmb\tstr\t\tTurn on blinking attribute\nmd\tstr\t\tTurn on bold (extra bright) attribute\nme\tstr\t\tTurn off all attributes\nmh\tstr\t\tTurn on half-bright attribute\nmi\tbool\t\tSafe to move while in insert mode\nmk\tstr\t\tTurn on blank attribute (characters invisible)\nml\tstr\t(o)\tMemory lock on above cursor\nmm\tstr\t\tTurn on \\*(lqmeta mode\\*(rq (8th bit)\nmo\tstr\t\tTurn off \\*(lqmeta mode\\*(rq\nmp\tstr\t\tTurn on protected attribute\nmr\tstr\t\tTurn on reverse-video attibute\nms\tbool\t\tSafe to move in standout modes\nmu\tstr\t(o)\tMemory unlock (turn off memory lock)\nnc\tbool\t(o)\tNo correctly-working \\fBcr\\fP (Datamedia 2500, Hazeltine 2000)\nnd\tstr\t\tNon-destructive space (cursor right)\nNL\tbool\t(o)\t\\fB\\\\n\\fP is newline, not line feed\nnl\tstr\t(o)\tNewline character if not \\fB\\\\n\\fP\nns\tbool\t(o)\tTerminal is a \\s-1CRT\\s0 but doesn't scroll\nnw\tstr\t(P)\tNewline (behaves like \\fBcr\\fP followed by \\fBdo\\fP)\nOP\tbool\t(o)\tOdd parity\nos\tbool\t\tTerminal overstrikes\npb\tnum\t\tLowest baud where delays are required\npc\tstr\t\tPad character (default \\s-2NUL\\s0)\npf\tstr\t\tTurn off the printer\npk\tstr\t\tProgram function key \\fIn\\^\\fP to type string \\fIs\\fP (\\fIterminfo\\^\\fP only)\npl\tstr\t\tProgram function key \\fIn\\^\\fP to execute string \\fIs\\fP (\\fIterminfo\\^\\fP only)\npO\tstr\t(N)\tTurn on the printer for \\fIn\\^\\fP bytes\npo\tstr\t\tTurn on the printer\nps\tstr\t\tPrint contents of the screen\npt\tbool\t(o)\tHas hardware tabs (may need to be set with \\fBis\\fP)\npx\tstr\t\tProgram function key \\fIn\\^\\fP to transmit string \\fIs\\fP (\\fIterminfo\\^\\fP only)\nr1-r3\tstr\t\tReset terminal completely to sane modes (\\fIterminfo\\^\\fP only)\nrc\tstr\t(P)\tRestore cursor to position of last \\fBsc\\fP\nrf\tstr\t\tName of file containing reset codes\nRI\tstr\t(NP)\tMove cursor right \\fIn\\^\\fP positions\nrp\tstr\t(NP*)\tRepeat character \\fIc n\\^\\fP times\nrs\tstr\t\tReset terminal completely to sane modes (\\fItermcap\\^\\fP only)\nsa\tstr\t(NP)\tDefine the video attributes\nsc\tstr\t(P)\tSave cursor position\nse\tstr\t\tEnd standout mode\nSF\tstr\t(NP*)\tScroll forward \\fIn\\^\\fP lines\nsf\tstr\t(P)\tScroll text up\nsg\tnum\t\tNumber of garbage chars left by \\fBso\\fP or \\fBse\\fP (default 0)\nso\tstr\t\tBegin standout mode\nSR\tstr\t(NP*)\tScroll backward \\fIn\\^\\fP lines\nsr\tstr\t(P)\tScroll text down\nst\tstr\t\tSet a tab in all rows, current column\nta\tstr\t(P)\tTab to next 8-position hardware tab stop\ntc\tstr\t\tEntry of similar terminal \\- must be last\nte\tstr\t\tString to end programs that use \\fItermcap\\fP\nti\tstr\t\tString to begin programs that use \\fItermcap\\fP\nts\tstr\t(N)\tGo to status line, column \\fIn\\^\\fP\nUC\tbool\t(o)\tUpper-case only\nuc\tstr\t\tUnderscore one character and move past it\nue\tstr\t\tEnd underscore mode\nug\tnum\t\tNumber of garbage chars left by \\fBus\\fP or \\fBue\\fP (default 0)\nul\tbool\t\tUnderline character overstrikes\nUP\tstr\t(NP*)\tMove cursor up \\fIn\\^\\fP lines\nup\tstr\t\tUpline (cursor up)\nus\tstr\t\tStart underscore mode\nvb\tstr\t\tVisible bell (must not move cursor)\nve\tstr\t\tMake cursor appear normal (undo \\fBvs\\fP/\\fBvi\\fP)\nvi\tstr\t\tMake cursor invisible\nvs\tstr\t\tMake cursor very visible\nvt\tnum\t\tVirtual terminal number (not supported on all systems)\nwi\tstr\t(N)\tSet current window\nws\tnum\t\tNumber of columns in status line\nxb\tbool\t\tBeehive (f1=\\s-2ESC\\s0, f2=^C)\nxn\tbool\t\tNewline ignored after 80 cols (Concept)\nxo\tbool\t\tTerminal uses xoff/xon (\\s-2DC3\\s0/\\s-2DC1\\s0) handshaking\nxr\tbool\t(o)\tReturn acts like \\fBce cr nl\\fP (Delta Data)\nxs\tbool\t\tStandout not erased by overwriting (Hewlett-Packard)\nxt\tbool\t\tTabs ruin, magic \\fBso\\fP char (Teleray 1061)\nxx\tbool\t(o)\tTektronix 4025 insert-line\n.fi\n.ta 8n +8n\n.PP\n.B A Sample Entry\n.PP\nThe following entry, which describes the Concept\\-100, is among the more\ncomplex entries in the\n.I termcap\\^\nfile as of this writing.\n.PP\n.nf\nca\\||\\|concept100\\||\\|c100\\||\\|concept\\||\\|c104\\||\\|concept100-4p\\||\\|HDS Concept\\-100:\\e\n\t:al=3*\\eE^R:am:bl=^G:cd=16*\\eE^C:ce=16\\eE^U:cl=2*^L:cm=\\eEa%+ %+ :\\e\n\t:co#80:.cr=9^M:db:dc=16\\eE^A:dl=3*\\eE^B:do=^J:ei=\\eE\\e200:eo:im=\\eE^P:in:\\e\n\t:ip=16*:is=\\eEU\\eEf\\eE7\\eE5\\eE8\\eEl\\eENH\\eEK\\eE\\e200\\eEo&\\e200\\eEo\\e47\\eE:k1=\\eE5:\\e\n\t:k2=\\eE6:k3=\\eE7:kb=^h:kd=\\eE<:ke=\\eEx:kh=\\eE?:kl=\\eE>:kr=\\eE=:ks=\\eEX:\\e\n\t:ku=\\eE;:le=^H:li#24:mb=\\eEC:me=\\eEN\\e200:mh=\\eEE:mi:mk=\\eEH:mp=\\eEI:\\e\n\t:mr=\\eED:nd=\\eE=:pb#9600:rp=0.2*\\eEr%.%+ :se=\\eEd\\eEe:sf=^J:so=\\eEE\\eED:\\e\n\t:.ta=8\\et:te=\\eEv    \\e200\\e200\\e200\\e200\\e200\\e200\\eEp\\er\\en:\\e\n\t:ti=\\eEU\\eEv  8p\\eEp\\er:ue=\\eEg:ul:up=\\eE;:us=\\eEG:\\e\n\t:vb=\\eEk\\e200\\e200\\e200\\e200\\e200\\e200\\e200\\e200\\e200\\e200\\e200\\e200\\e200\\e200\\eEK:\\e\n\t:ve=\\eEw:vs=\\eEW:vt#8:xn:\\e\n\t:bs:cr=^M:dC#9:dT#8:nl=^J:ta=^I:pt:\n.fi\n.PP\nEntries may continue onto multiple lines by giving a \\e as the last\ncharacter of a line, and empty fields\nmay be included for readability (here between the last field on a line\nand the first field on the next).\nComments may be included on lines beginning with \\*(lq#\\*(rq.\n.br\n.ne 5\n.PP\n.B Types of Capabilities\n.PP\nCapabilities in\n.I termcap\\^\nare of three types: Boolean capabilities,\nwhich indicate particular features that the terminal has;\nnumeric capabilities,\ngiving the size of the display or the size of other attributes;\nand string capabilities,\nwhich give character sequences that can be used to perform particular\nterminal operations.\nAll capabilities have two-letter codes.\nFor instance, the fact that\nthe Concept has\n.I automatic margins\n.RI ( i.e. ,\nan automatic return and linefeed\nwhen the end of a line is reached) is indicated by the Boolean capability\n.BR am .\nHence the description of the Concept includes\n.BR am .\n.PP\nNumeric capabilities are followed by the character `#' then the value.\nIn the example above\n.BR co ,\nwhich indicates the number of columns the display has,\ngives the value `80' for the Concept.\n.PP\nFinally, string-valued capabilities, such as\n.B ce\n(clear-to-end-of-line\nsequence) are given by the two-letter code, an `=', then a string\nending at the next following `:'.\nA delay in milliseconds may appear after\nthe `=' in such a capability,\nwhich causes padding characters to be supplied by\n.I tputs\\^\nafter the remainder of the string is sent to provide this delay.\nThe delay can be either a number,\n.I e.g.\n`20', or a number followed by\nan `*',\n.IR i.e. ,\n`3*'.\nAn `*' indicates that the padding required is proportional\nto the number of lines affected by the operation, and the amount given is\nthe per-affected-line padding required.\n(In the case of insert-character,\nthe factor is still the number of\n.I lines\\^\naffected;\nthis is always 1 unless the terminal has\n.B in\nand the software uses it.)\nWhen an `*' is specified, it is sometimes useful to give a delay of the form\n`3.5' to specify a delay per line to tenths of milliseconds.\n(Only one decimal place is allowed.)\n.PP\nA number of escape sequences are provided in the string-valued capabilities\nfor easy encoding of control characters there.\n.B \\eE\nmaps to an \\s-2ESC\\s0\ncharacter,\n.B ^X\nmaps to a control-X for any appropriate X,\nand the sequences\n.B \\en\n.B \\er\n.B \\et\n.B \\eb\n.B \\ef\nmap to linefeed, return, tab, backspace, and formfeed, respectively.\nFinally, characters may be given as three octal digits after a\n.BR \\e ,\nand the characters\n.B ^\nand\n.B \\e\nmay be given as\n.B \\e^\nand\n.BR \\e\\e .\nIf it is necessary to place a\n.B :\nin a capability it must be escaped in\noctal as\n.BR \\e072 .\nIf it is necessary to place a \\s-2NUL\\s0\ncharacter in a string capability it\nmust be encoded as\n.BR \\e200 .\n(The routines that deal with\n.I termcap\\^\nuse C strings and strip the high bits of the output very late, so that\na\n.B \\e200\ncomes out as a\n.B \\e000\nwould.)\n.PP\nSometimes individual capabilities must be commented out.\nTo do this, put a period before the capability name.\nFor example, see the first\n.B cr\nand\n.B ta\nin the example above.\n.br\n.ne 5\n.PP\n.B Preparing Descriptions\n.PP\nWe now outline how to prepare descriptions of terminals.\nThe most effective way to prepare a terminal description is by imitating\nthe description of a similar terminal in\n.I termcap\\^\nand to build up a description gradually, using partial descriptions\nwith\n.I vi\\^\nto check that they are correct.\nBe aware that a very unusual terminal may expose deficiencies in\nthe ability of the\n.I termcap\\^\nfile to describe it\nor bugs in\n.IR vi\\^ .\nTo easily test a new terminal description you can set the environment variable\n.B\n.SM TERMCAP\nto the absolute pathname of a file containing the description you are working\non and programs will look there rather than in\n.IR /etc/termcap\\^ .\n.B\n.SM TERMCAP\ncan also be set to the\n.I termcap\\^\nentry itself\nto avoid reading the file when starting up a program.\n.PP\nTo get the padding for insert-line right\n(if the terminal manufacturer did not document it),\na severe test is to use\n.I vi\\^\nto edit\n.I /etc/passwd\\^\nat 9600 baud, delete roughly 16 lines from the middle of the screen,\nthen hit the `u' key several times quickly.\nIf the display messes up, more padding is usually needed.\nA similar test can be used for insert-character.\n.br\n.ne 5\n.PP\n.B Basic Capabilities\n.PP\nThe number of columns on each line of the display is given by the\n.B co\nnumeric capability.\nIf the display is a \\s-1CRT\\s0, then the\nnumber of lines on the screen is given by the\n.B li\ncapability.\nIf the display wraps around to the beginning of the next line when\nthe cursor reaches the right margin, then it should have the\n.B am\ncapability.\nIf the terminal can clear its screen,\nthe code to do this is given by the\n.B cl\nstring capability.\nIf the terminal overstrikes\n(rather than clearing the position when a character is overwritten),\nit should have the\n.B os\ncapability.\nIf the terminal is a printing terminal,\nwith no soft copy unit,\ngive it both\n.B hc\nand\n.BR os .\n.RB ( os\napplies to storage scope terminals,\nsuch as the Tektronix 4010 series,\nas well as to hard copy and\n.SM APL\nterminals.)\nIf there is a code to move the cursor to the left edge of the current row,\ngive this as\n.BR cr .\n(Normally this will be carriage-return,\n.BR ^M .)\nIf there is a code to produce an audible signal (bell, beep,\n.IR etc.\\^ ),\ngive this as\n.BR bl .\n.PP\nIf there is a code (such as backspace)\nto move the cursor one position to the left,\nthat capability should be given as\n.BR le .\nSimilarly,\ncodes to move to the right, up, and down\nshould be given as\n.BR nd ,\n.BR up ,\nand\n.BR do ,\nrespectively.\nThese\n.I local cursor motions\\^\nshould not alter the text they pass over;\nfor example, you would not normally use\n\\*(lqnd=\\ \\*(rq\nunless the terminal has the\n.B os\ncapability,\nbecause the space would erase the character moved over.\n.PP\nA very important point here is that the local cursor motions encoded\nin\n.I termcap\\^\nhave undefined behavior at the left and top edges of a\n.SM CRT\ndisplay.\nPrograms should never attempt to backspace around the left edge,\nunless\n.B bw\nis given, and never attempt to go up off the top\nusing local cursor motions.\n.PP\nIn order to scroll text up,\na program goes to the bottom left corner of the screen and sends the\n.B sf\n(index) string.\nTo scroll text down,\na program goes to the top left corner of the screen and sends the\n.B sr\n(reverse index) string.\nThe strings\n.B sf\nand\n.B sr\nhave undefined behavior\nwhen not on their respective corners of the screen.\nParameterized versions of the scrolling sequences are\n.B SF\nand\n.BR SR ,\nwhich have the same semantics as\n.B sf\nand\n.B sr\nexcept that they take one parameter\nand scroll that many lines.\nThey also have undefined behavior\nexcept at the appropriate corner of the screen.\n.PP\nThe\n.B am\ncapability tells whether the cursor sticks at the right\nedge of the screen when text is output there,\nbut this does not necessarily apply to\n.B nd\nfrom the last column.\nLeftward local motion is defined from the left edge only when\n.B bw\nis given; then an\n.B le\nfrom the left edge will move to the right edge of the previous row.\nThis is useful for drawing a box around the edge of the screen,\nfor example.\nIf the terminal has switch-selectable automatic margins,\nthe\n.I termcap\\^\ndescription usually assumes that this feature is on,\n.IR i.e. ,\n.BR am .\nIf the terminal has a command\nthat moves to the first column of the next line,\nthat command can be given as\n.B nw\n(newline).\nIt is permissible for this to clear the remainder of the current line,\nso if the terminal has no correctly-working \\s-2CR\\s0 and \\s-2LF\\s0\nit may still be possible to craft a working\n.B nw\nout of one or both of them.\n.PP\nThese capabilities suffice to describe hardcopy and \\*(lqglass-tty\\*(rq terminals.\nThus the Teletype model 33 is described as\n.PP\n.nf\n\tT3\\||\\|tty33\\||\\|33\\||\\|tty\\||\\|Teletype model 33:\\e\n\t\t:bl=^G:co#72:cr=^M:do=^J:hc:os:\n.fi\n.PP\nand the Lear Siegler \\s-1ADM\\s0\\-3 is described as\n.PP\n.nf\n\tl3\\||\\|adm3\\||\\|3\\||\\|LSI \\s-1ADM\\s0-3:\\e\n\t\t:am:bl=^G:cl=^Z:co#80:cr=^M:do=^J:le=^H:li#24:sf=^J:\n.fi\n.br\n.ne 5\n.PP\n.B Parameterized Strings\n.PP\nCursor addressing and other strings requiring parameters\nare described by a\nparameterized string capability, with \n.IR printf\\^ (3S)-like\nescapes\n.B %x\nin it,\nwhile other characters are passed through unchanged.\nFor example, to address the cursor the\n.B cm\ncapability is given, using two parameters: the row and column to move to.\n(Rows and columns are numbered from zero and refer to the physical screen\nvisible to the user, not to any unseen memory.\nIf the terminal has memory-relative cursor addressing,\nthat can be indicated by an analogous\n.B CM\ncapability.)\n.PP\nThe\n.B %\nencodings have the following meanings:\n.PP\n.DT\n.nf\n\t%%\toutput `%'\n\t%d\toutput value as in \\fIprintf\\^\\fP %d\n\t%2\toutput value as in \\fIprintf\\^\\fP %2d\n\t%3\toutput value as in \\fIprintf\\^\\fP %3d\n\t%.\toutput value as in \\fIprintf\\^\\fP %c\n\t%+\\fIx\\fP\tadd \\fIx\\^\\fP to value, then do %.\n\t%>\\fIxy\\fP\tif value > \\fIx\\^\\fP then add \\fIy\\^\\fP, no output\n\t%r\treverse order of two parameters, no output\n\t%i\tincrement by one, no output\n\t%n\texclusive-or all parameters with 0140 (Datamedia 2500)\n\t%B\tBCD (16*(value/10)) + (value%10), no output\n\t%D\tReverse coding (value \\- 2*(value%16)), no output (Delta Data)\n.fi\n.PP\nConsider the Hewlett-Packard 2645, which, to get to row 3 and column 12, needs\nto be sent \\*(lq\\eE&a12c03Y\\*(rq padded for 6 milliseconds.\nNote that the order\nof the row and column coordinates is reversed here\nand that the row and column\nare sent as two-digit integers.\nThus its\n.B cm\ncapability is \\*(lqcm=6\\eE&%r%2c%2Y\\*(rq.\n.PP\nThe Microterm\n.SM ACT-IV\nneeds the current row and column sent\nsimply encoded in binary\npreceded by a\n.BR ^T ,\n\\*(lqcm=^T%.%.\\*(rq.\nTerminals that use \\*(lq%.\\*(rq need to be able to\nbackspace the cursor\n.RB ( le )\nand to move the cursor up one line on the screen\n.RB ( up ).\nThis is necessary because it is not always safe to transmit\n.BR \\en ,\n.BR ^D ,\nand\n.BR \\er ,\nas the system may change or discard them.\n(Programs using\n.I termcap\\^\nmust set terminal modes so that tabs are not expanded, so\n.B \\et\nis safe to send.\nThis turns out to be essential for the Ann Arbor 4080.)\n.PP\nA final example is the Lear Siegler \\s-1ADM\\s0\\-3a,\nwhich offsets row and column\nby a blank character, thus \\*(lqcm=\\eE=%+ %+ \\*(rq.\n.PP\nRow or column absolute cursor addressing\ncan be given as single parameter capabilities\n.B ch\n(horizontal position absolute) and\n.B cv\n(vertical position absolute).\nSometimes these are shorter than the more general two-parameter sequence\n(as with the Hewlett-Packard 2645) and can be used in preference to\n.BR cm .\nIf there are parameterized local motions\n.RI ( e.g. ,\nmove\n.I n\\^\npositions to the right)\nthese can be given as\n.BR DO ,\n.BR LE ,\n.BR RI ,\nand\n.B UP\nwith a single parameter indicating how many positions to move.\nThese are primarily useful if the terminal does not have\n.BR cm ,\nsuch as the Tektronix 4025.\n.br\n.ne 5\n.PP\n.B Cursor Motions\n.PP\nIf the terminal has a fast way to home the cursor\n(to the very upper left corner of the screen), this can be given as\n.BR ho .\nSimilarly, a fast way of getting to the lower left-hand corner\ncan be given as\n.BR ll ;\nthis may involve going up with\n.B up\nfrom the home position,\nbut a program should never do this itself (unless\n.B ll\ndoes), because it can\nmake no assumption about the effect of moving up from the home position.\nNote that the home position is the same as\ncursor address (0,0): to the top left corner of the screen, not of memory.\n(Therefore, the \\*(lq\\eEH\\*(rq sequence on Hewlett-Packard terminals\ncannot be used for\n.BR ho .)\n.br\n.ne 5\n.PP\n.B Area Clears\n.PP\nIf the terminal can clear from the current position to the end of the\nline, leaving the cursor where it is, this should be given as\n.BR ce .\nIf the terminal can clear from the current position to the end of the\ndisplay, this should be given as\n.BR cd .\n.B cd\nmust only be invoked from the first column of a line.\n(Therefore,\nit can be simulated by a request to delete a large number of lines,\nif a true\n.B cd\nis not available.)\n.br\n.ne 5\n.PP\n.B Insert/Delete Line\n.PP\nIf the terminal can open a new blank line\nbefore the line containing the cursor,\nthis should be given as\n.BR al ;\nthis must be invoked only from the first\nposition of a line.\nThe cursor must then appear at the left of the newly blank line.\nIf the terminal can delete the line that the cursor is on, this\nshould be given as\n.BR dl ;\nthis must only be used from the first position on\nthe line to be deleted.\nVersions of\n.B al\nand\n.B dl\nwhich take a single parameter\nand insert or delete that many lines\ncan be given as\n.B AL\nand\n.BR DL .\nIf the terminal has a settable scrolling region\n(like the VT100),\nthe command to set this can be described with the\n.B cs\ncapability,\nwhich takes two parameters: the top and bottom lines of the scrolling region.\nThe cursor position is, alas, undefined after using this command.\nIt is possible to get the effect of insert or delete line\nusing this command \\(em the\n.B sc\nand\n.B rc\n(save and restore cursor) commands are also useful.\nInserting lines at the top or bottom of the screen can also be done using\n.B sr\nor\n.B sf\non many terminals without a true insert/delete line,\nand is often faster even on terminals with those features.\n.PP\nIf the terminal has the ability to define a window as part of memory\nwhich all commands affect, it should be given as the parameterized string\n.BR wi .\nThe four parameters are the starting and ending lines in memory\nand the starting and ending columns in memory, in that order.\n(This\n.I terminfo\\^\ncapability is described for completeness.\nIt is unlikely that any\n.IR termcap\\^ -using\nprogram will support it.)\n.PP\nIf the terminal can retain display memory above the screen, then the\n.B da\ncapability should be given;\nif display memory can be retained\nbelow, then\n.B db\nshould be given.\nThese indicate\nthat deleting a line or scrolling may bring non-blank lines up from below\nor that scrolling back with\n.B sr\nmay bring down non-blank lines.\n.br\n.ne 5\n.PP\n.B Insert/Delete Character\n.PP\nThere are two basic kinds of intelligent terminals with respect to\ninsert/delete character that can be described using\n.IR termcap\\^ .\nThe most common insert/delete character operations affect only the characters\non the current line and shift characters off the end of the line rigidly.\nOther terminals, such as the Concept\\-100 and the Perkin Elmer Owl, make\na distinction between typed and untyped blanks on the screen, shifting\nupon an insert or delete only to an untyped blank on the screen which is\neither eliminated or expanded to two untyped blanks.\nYou can determine\nthe kind of terminal you have by clearing the screen then typing\ntext separated by cursor motions.\nType \\*(lqabc\\ \\ \\ \\ def\\*(rq using local\ncursor motions (not spaces) between the \\*(lqabc\\*(rq and the \\*(lqdef\\*(rq.\nThen position the cursor before the \\*(lqabc\\*(rq and put the terminal in insert\nmode.\nIf typing characters causes the rest of the line to shift\nrigidly and characters to fall off the end, then your terminal does\nnot distinguish between blanks and untyped positions.\nIf the \\*(lqabc\\*(rq\nshifts over to the \\*(lqdef\\*(rq which then move together around the end of the\ncurrent line and onto the next as you insert, then you have the second type of\nterminal and should give the capability \\fBin\\fP, which stands for\n\\*(lqinsert null\\*(rq.\nWhile these are two logically separate attributes\n(one line\n.I vs.\nmulti-line insert mode,\nand special treatment of untyped spaces),\nwe have seen no terminals whose insert\nmode cannot be described with the single attribute.\n.PP\n.I Termcap\\^\ncan describe both terminals that have an insert mode and terminals\nthat send a simple sequence to open a blank position on the current line.\nGive as\n.B im\nthe sequence to get into insert mode.\nGive as\n.B ei\nthe sequence to leave insert mode.\nNow give as\n.B ic\nany sequence that needs to be sent just before\neach character to be inserted.\nMost terminals with a true insert mode\nwill not give\n.BR ic ;\nterminals that use a sequence to open a screen\nposition should give it here.\n(If your terminal has both,\ninsert mode is usually preferable to\n.BR ic .\nDo not give both unless the terminal actually requires both to be used\nin combination.)\nIf post-insert padding is needed, give this as a number of milliseconds\nin\n.B ip\n(a string option).\nAny other sequence that may need to be\nsent after insertion of a single character can also be given in\n.BR ip .\nIf your terminal needs to be placed into an `insert mode'\nand needs a special code preceding each inserted character,\nthen both\n.BR im / ei\nand\n.B ic\ncan be given, and both will be used.\nThe\n.B IC\ncapability, with one parameter\n.IR n\\^ ,\nwill repeat the effects of\n.B ic\n.I n\\^\ntimes.\n.PP\nIt is occasionally necessary to move around while in insert mode\nto delete characters on the same line\n.RI ( e.g. ,\nif there is a tab after\nthe insertion position).\nIf your terminal allows motion while in\ninsert mode, you can give the capability\n.B mi\nto speed up inserting\nin this case.\nOmitting\n.B mi\nwill affect only speed.\nSome terminals\n(notably Datamedia's) must not have\n.B mi\nbecause of the way their\ninsert mode works.\n.PP\nFinally, you can specify\n.B dc\nto delete a single character,\n.B DC\nwith one parameter\n.I n\\^\nto delete\n.I n\\^\ncharacters,\nand delete mode by giving\n.B dm\nand\n.B ed\nto enter and exit delete mode\n(which is any mode the terminal needs to be placed in for\n.B dc\nto work).\n.br\n.ne 5\n.PP\n.B Highlighting, Underlining, and Visible Bells\n.PP\nIf your terminal has one or more kinds of display attributes,\nthese can be represented in a number of different ways.\nYou should choose one display form as\n.IR \"standout mode\" ,\nrepresenting a good high-contrast, easy-on-the-eyes format\nfor highlighting error messages and other attention getters.\n(If you have a choice, reverse video plus half-bright is good,\nor reverse video alone.)\nThe sequences to enter and exit standout mode\nare given as\n.B so\nand\n.BR se ,\nrespectively.\nIf the code to change into or out of standout\nmode leaves one or even two blank spaces or garbage characters on the screen,\nas the TVI 912 and Teleray 1061 do,\nthen\n.B sg\nshould be given to tell how many characters are left.\n.PP\nCodes to begin underlining and end underlining can be given as\n.B us\nand\n.BR ue ,\nrespectively.\nUnderline mode change garbage is specified by\n.BR ug ,\nsimilar to\n.BR sg .\nIf the terminal has a code to underline the current character and move\nthe cursor one position to the right, \nsuch as the Microterm Mime,\nthis can be given as\n.BR uc .\n.PP\nOther capabilities to enter various highlighting modes include\n.B mb\n(blinking),\n.B md\n(bold or extra bright),\n.B mh\n(dim or half-bright),\n.B mk\n(blanking or invisible text),\n.B mp\n(protected),\n.B mr\n(reverse video),\n.B me\n(turn off\n.I all\nattribute modes),\n.B as\n(enter alternate character set mode), and\n.B ae\n(exit alternate character set mode).\nTurning on any of these modes singly may or may not turn off other modes.\n.PP\nIf there is a sequence to set arbitrary combinations of mode,\nthis should be given as\n.B sa\n(set attributes), taking 9 parameters.\nEach parameter is either 0 or 1,\nas the corresponding attributes is on or off.\nThe 9 parameters are, in order: standout, underline, reverse, blink,\ndim, bold, blank, protect, and alternate character set.\nNot all modes need be supported by\n.BR sa ,\nonly those for which corresponding attribute commands exist.\n(It is unlikely that a\n.IR termcap\\^ -using\nprogram will support this capability, which is defined for compatibility\nwith\n.IR terminfo\\^ .)\n.PP\nTerminals with the \\*(lqmagic cookie\\*(rq glitches\n.RB ( sg\nand\n.BR ug ),\nrather than maintaining extra attribute bits for each character cell,\ninstead deposit special \\*(lqcookies\\*(rq,\nor \\*(lqgarbage characters\\*(rq,\nwhen they receive mode-setting sequences,\nwhich affect the display algorithm.\n.PP\nSome terminals,\nsuch as the Hewlett-Packard 2621,\nautomatically leave standout\nmode when they move to a new line or when the cursor is addressed.\nPrograms using standout mode\nshould exit standout mode on such terminals\nbefore moving the cursor or sending a newline.\nOn terminals where this is not a problem,\nthe\n.B ms\ncapability should be present\nto say that this overhead is unnecessary.\n.PP\nIf the terminal has\na way of flashing the screen to indicate an error quietly\n(a bell replacement),\nthis can be given as\n.BR vb ;\nit must not move the cursor.\n.PP\nIf the cursor needs to be made more visible than normal\nwhen it is not on the bottom line\n(to change, for example, a non-blinking underline into an easier-to-find\nblock or blinking underline),\ngive this sequence as\n.BR vs .\nIf there is a way to make the cursor completely invisible, give that as\n.BR vi .\nThe capability\n.BR ve ,\nwhich undoes the effects of both of these modes,\nshould also be given.\n.PP\nIf your terminal correctly displays underlined characters\n(with no special codes needed)\neven though it does not overstrike,\nthen you should give the capability\n.BR ul .\nIf overstrikes are erasable with a blank,\nthis should be indicated by giving\n.BR eo .\n.br\n.ne 5\n.PP\n.B Keypad\n.PP\nIf the terminal has a keypad that transmits codes when the keys are pressed,\nthis information can be given.\nNote that it is not possible to handle\nterminals where the keypad only works in local mode\n(this applies, for example, to the unshifted Hewlett-Packard 2621 keys).\nIf the keypad can be set to transmit or not transmit,\ngive these codes as\n.B ks\nand\n.BR ke .\nOtherwise the keypad is assumed to always transmit.\nThe codes sent by the left-arrow, right-arrow, up-arrow, down-arrow,\nand home keys can be given as\n.BR kl ,\n.BR kr ,\n.BR ku ,\n.BR kd ,\nand\n.BR kh ,\nrespectively.\nIf there are function keys such as f0, f1, ..., f9, the codes they send\ncan be given as\n.BR k0 ,\n.BR k1 , \"\" ...,\n.BR k9 .\nIf these keys have labels other than the default f0 through f9, the labels\ncan be given as\n.BR l0 ,\n.BR l1 , \"\" ...,\n.BR l9 .\nThe codes transmitted by certain other special keys can be given:\n.B kH\n(home down),\n.B kb\n(backspace),\n.B ka\n(clear all tabs),\n.B kt\n(clear the tab stop in this column),\n.B kC\n(clear screen or erase),\n.B kD\n(delete character),\n.B kL\n(delete line),\n.B kM\n(exit insert mode),\n.B kE\n(clear to end of line),\n.B kS\n(clear to end of screen),\n.B kI\n(insert character or enter insert mode),\n.B kA\n(insert line),\n.B kN\n(next page),\n.B kP\n(previous page),\n.B kF\n(scroll forward/down),\n.B kR\n(scroll backward/up), and\n.B kT\n(set a tab stop in this column).\nIn addition, if the keypad has a 3 by 3 array of keys\nincluding the four arrow keys, then the other five keys can be given as\n.BR K1 ,\n.BR K2 ,\n.BR K3 ,\n.BR K4 ,\nand\n.BR K5 .\nThese keys are useful when the effects of a 3 by 3 directional pad are needed.\nThe obsolete\n.B ko\ncapability formerly used to describe \\*(lqother\\*(rq function keys has been\ncompletely supplanted by the above capabilities.\n.PP\nThe\n.B ma\nentry is also used to indicate arrow keys on terminals that have\nsingle-character arrow keys.\nIt is obsolete but still in use in\nversion 2 of\n.I vi\\^\nwhich must be run on some minicomputers due to\nmemory limitations.\nThis field is redundant with\n.BR kl ,\n.BR kr ,\n.BR ku ,\n.BR kd ,\nand\n.BR kh .\nIt consists of groups of two characters.\nIn each group, the first character is what an arrow key sends, and the\nsecond character is the corresponding\n.I vi\\^\ncommand.\nThese commands are\n.B h\nfor\n.BR kl ,\n.B j\nfor\n.BR kd ,\n.B k\nfor\n.BR ku ,\n.B l\nfor\n.BR kr ,\nand\n.B H\nfor\n.BR kh .\nFor example, the Mime would have \\*(lqma=^Hh^Kj^Zk^Xl\\*(rq\nindicating arrow keys left (^H), down (^K), up (^Z), and right (^X).\n(There is no home key on the Mime.)\n.br\n.ne 5\n.PP\n.B Tabs and Initialization\n.PP\nIf the terminal needs to be in a special mode when running\na program that uses these capabilities,\nthe codes to enter and exit this mode can be given as\n.B ti\nand\n.BR te .\nThis arises, for example, from terminals like the Concept with more than\none page of memory.\nIf the terminal has only memory-relative cursor addressing and not\nscreen-relative cursor addressing,\na screen-sized window must be fixed into\nthe display for cursor addressing to work properly.\nThis is also used for the Tektronix 4025, where\n.B ti\nsets the command character to be the one used by\n.IR termcap\\^ .\n.PP\nOther capabilities\ninclude\n.BR is ,\nan initialization string for the terminal,\nand\n.BR if ,\nthe name of a file containing long initialization strings.\nThese strings are expected to set the terminal into modes\nconsistent with the rest of the\n.I termcap\\^\ndescription.\nThey are normally sent to the terminal by the\n.I tset\\^\nprogram each time the user logs in.\nThey will be printed in the following order:\n.BR is ;\nsetting tabs using\n.B ct\nand\n.BR st ;\nand finally\n.BR if .\n.RI ( Terminfo\\^\nuses\n.B i1-i2\ninstead of\n.B is\nand runs the program\n.B iP\nand prints\n.B i3\nafter the other initializations.)\nA pair of sequences that does a harder reset from a totally unknown state\ncan be analogously given as\n.B rs\nand\n.BR if .\nThese strings are output by the\n.I reset\\^\nprogram, which is used when the terminal gets into a wedged state.\n.RI ( Terminfo\\^\nuses\n.B r1-r3\ninstead of\n.BR rs .)\nCommands are normally placed in\n.B rs\nand\n.B rf\nonly if they produce annoying effects on the screen and are not necessary\nwhen logging in.\nFor example, the command to set the VT100 into 80-column mode\nwould normally be part of\n.BR is ,\nbut it causes an annoying glitch of the screen and is not normally needed\nsince the terminal is usually already in 80-column mode.\n.PP\nIf the terminal has hardware tabs,\nthe command to advance to the next tab stop can be given as\n.B ta\n(usually\n.BR ^I ).\nA \\*(lqbacktab\\*(rq command which moves leftward to the previous tab stop\ncan be given as\n.BR bt .\nBy convention,\nif the terminal driver modes indicate that tab stops are being expanded\nby the computer rather than being sent to the terminal,\nprograms should not use\n.B ta\nor\n.B bt\neven if they are present,\nsince the user may not have the tab stops properly set.\nIf the terminal has hardware tabs that are initially set every\n.I n\\^\npositions when the terminal is powered up, then the numeric parameter\n.B it\nis given, showing the number of positions between tab stops.\nThis is normally used by the\n.I tset\\^\ncommand to determine whether to set the driver mode for hardware tab\nexpansion, and whether to set the tab stops.\nIf the terminal has tab stops that can be saved in nonvolatile memory, the\n.I termcap\\^\ndescription can assume that they are properly set.\n.PP\nIf there are commands to set and clear tab stops, they can be given as\n.B ct\n(clear all tab stops) and\n.B st\n(set a tab stop in the current column of every row).\nIf a more complex sequence is needed to set the tabs than can be\ndescribed by this, the sequence can be placed in\n.B is\nor\n.BR if .\n.br\n.ne 5\n.PP\n.B Delays\n.PP\nCertain capabilities control padding in the terminal driver.\nThese are primarily needed by hardcopy terminals and are used by the\n.I tset\\^\nprogram to set terminal driver modes appropriately.\nDelays embedded in the capabilities\n.BR cr ,\n.BR sf ,\n.BR le ,\n.BR ff ,\nand\n.B ta\nwill cause the appropriate delay bits to be set in the terminal driver.\nIf\n.B pb\n(padding baud rate) is given, these values can be ignored at baud rates\nbelow the value of\n.BR pb .\nFor 4.2BSD\n.IR tset\\^ ,\nthe delays are given as numeric capabilities\n.BR dC ,\n.BR dN ,\n.BR dB ,\n.BR dF ,\nand\n.BR dT\ninstead.\n.br\n.ne 5\n.PP\n.B Miscellaneous\n.PP\nIf the terminal requires other than a \\s-2NUL\\s0 (zero) character as a pad,\nthis can be given as\n.BR pc .\nOnly the first character of the\n.B pc\nstring is used.\n.PP\nIf the terminal has commands to save and restore the position of the\ncursor, give them as\n.B sc\nand\n.BR rc .\n.PP\nIf the terminal has an extra \\*(lqstatus line\\*(rq that is not normally used by\nsoftware, this fact can be indicated.\nIf the status line is viewed as an extra line below the bottom line,\nthen the capability\n.B hs\nshould be given.\nSpecial strings to go to a position in the status line and to return\nfrom the status line can be given as\n.B ts\nand\n.BR fs .\n.RB ( fs\nmust leave the cursor position in the same place that it was before\n.BR ts .\nIf necessary, the\n.B sc\nand\n.B rc\nstrings can be included in\n.B ts\nand\n.B fs\nto get this effect.)\nThe capability\n.B ts\ntakes one parameter, which is the column number of the status line\nto which the cursor is to be moved.\nIf escape sequences and other special commands such as tab work while in\nthe status line, the flag\n.B es\ncan be given.\nA string that turns off the status line (or otherwise erases its contents)\nshould be given as\n.BR ds .\nThe status line is normally assumed to be the same width as the\nrest of the screen,\n.IR i.e. ,\n.BR co .\nIf the status line is a different width (possibly because the terminal\ndoes not allow an entire line to be loaded), then its width in columns\ncan be indicated with the numeric parameter\n.BR ws .\n.PP\nIf the terminal can move up or down half a line, this can be\nindicated with\n.B hu\n(half-line up) and\n.B hd\n(half-line down).\nThis is primarily useful for superscripts and subscripts on hardcopy\nterminals.\nIf a hardcopy terminal can eject to the next page (form feed),\ngive this as\n.B ff\n(usually\n.BR ^L ).\n.PP\nIf there is a command to repeat a given character a given number of times\n(to save time transmitting a large number of identical characters),\nthis can be indicated with the parameterized string\n.BR rp .\nThe first parameter is the character to be repeated and the second is\nthe number of times to repeat it.\n(This is a\n.I terminfo\\^\nfeature that is unlikely to be supported by a program that uses\n.IR termcap\\^ .)\n.PP\nIf the terminal has a settable command character, such as the\nTektronix 4025, this can be indicated with\n.BR CC .\nA prototype command character is chosen which is used in all capabilities.\nThis character is given in the\n.B CC\ncapability to identify it.\nThe following convention is supported on some UNIX systems:\nThe environment is to be searched for a\n.B\n.SM CC\nvariable,\nand if found,\nall occurrences of the prototype character are replaced by the character\nin the environment variable.\nThis use of the\n.B\n.SM CC\nenvironment variable\nis a very bad idea, as it conflicts with\n.IR make\\^ (1).\n.PP\nTerminal descriptions that do not represent a specific kind of known\nterminal, such as\n.IR switch\\^ ,\n.IR dialup\\^ ,\n.IR patch\\^ ,\nand\n.IR network\\^ ,\nshould include the\n.B gn\n(generic) capability so that programs can complain that they do not know\nhow to talk to the terminal.\n(This capability does not apply to\n.I virtual\\^\nterminal descriptions for which the escape sequences are known.)\n.PP\nIf the terminal uses xoff/xon (\\s-2DC3\\s0/\\s-2DC1\\s0)\nhandshaking for flow control, give\n.BR xo .\nPadding information should still be included so that routines can make\nbetter decisions about costs, but actual pad characters will not be\ntransmitted.\n.PP\nIf the terminal has a \\*(lqmeta key\\*(rq which acts as a shift key, setting the\n8th bit of any character transmitted, then this fact can be indicated with\n.BR km .\nOtherwise, software will assume that the 8th bit is parity and it will\nusually be cleared.\nIf strings exist to turn this \\*(lqmeta mode\\*(rq on and off, they can be given as\n.B mm\nand\n.BR mo .\n.PP\nIf the terminal has more lines of memory than will fit on the screen at once,\nthe number of lines of memory can be indicated with\n.BR lm .\nAn explicit value of 0 indicates that the number of lines is not fixed,\nbut that there is still more memory than fits on the screen.\n.PP\nIf the terminal is one of those supported by the UNIX system virtual\nterminal protocol, the terminal number can be given as\n.BR vt .\n.PP\nMedia copy strings which control an auxiliary printer\nconnected to the terminal can be given as\n.BR ps :\nprint the contents of the screen;\n.BR pf :\nturn off the printer; and\n.BR po :\nturn on the printer.\nWhen the printer is on, all text sent to the terminal will be sent to the\nprinter.\nIt is undefined whether the text is also displayed on the terminal screen\nwhen the printer is on.\nA variation\n.B pO\ntakes one parameter and leaves the printer on for as many characters as the\nvalue of the parameter, then turns the printer off.\nThe parameter should not exceed 255.\nAll text, including\n.BR pf ,\nis transparently passed to the printer while\n.B pO\nis in effect.\n.PP\nStrings to program function keys can be given as\n.BR pk ,\n.BR pl ,\nand\n.BR px .\nEach of these strings takes two parameters: the function key number\nto program (from 0 to 9) and the string to program it with.\nFunction key numbers out of this range may program undefined keys\nin a terminal-dependent manner.\nThe differences among the capabilities are that\n.B pk\ncauses pressing the given key to be the same as the user typing the given\nstring;\n.B pl\ncauses the string to be executed by the terminal in local mode;\nand\n.B px\ncauses the string to be transmitted to the computer.\nUnfortunately, due to lack of a definition for string parameters in\n.IR termcap\\^ ,\nonly\n.I terminfo\\^\nsupports these capabilities.\n.br\n.ne 5\n.PP\n.B Glitches and Braindamage\n.PP\nHazeltine terminals, which do not allow `~' characters to be displayed,\nshould indicate\n.BR hz .\n.PP\nThe\n.B nc\ncapability, now obsolete, formerly indicated Datamedia terminals,\nwhich echo\n.B \\er \\en\nfor\ncarriage return then ignore a following linefeed.\n.PP\nTerminals that ignore a linefeed immediately after an\n.B am\nwrap, such as the Concept, should indicate\n.BR xn .\n.PP\nIf\n.B ce\nis required to get rid of standout\n(instead of merely writing normal text on top of it),\n.B xs\nshould be given.\n.PP\nTeleray terminals, where tabs turn all characters moved over to blanks,\nshould indicate\n.B xt\n(destructive tabs).\nThis glitch is also taken to mean that it is not possible\nto position the cursor on top of a \\*(lqmagic cookie\\*(rq, and that\nto erase standout mode it is necessary to use delete and insert line.\n.PP\nThe Beehive Superbee, which is unable to correctly transmit the\n\\s-2ESC\\s0 or ^C characters, has\n.BR xb ,\nindicating that the \\*(lqf1\\*(rq key is used for \\s-2ESC\\s0 and \\*(lqf2\\*(rq for ^C.\n(Only certain Superbees have this problem, depending on the ROM.)\n.PP\nOther specific terminal problems may be corrected by adding more\ncapabilities of the form \\fBx\\fIx\\^\\fP.\n.br\n.ne 5\n.PP\n.B Similar Terminals\n.PP\nIf there are two very similar terminals,\none can be defined as being just like the other with certain exceptions.\nThe string capability\n.B tc\ncan be given\nwith the name of the similar terminal.\nThis capability must be\n.IR last\\^ ,\nand the combined length of the entries\nmust not exceed 1024.\nThe capabilities given before\n.B tc\noverride those in the terminal type invoked by\n.BR tc .\nA capability can be canceled by placing\n.B xx@\nto the left of the\n.B tc\ninvocation, where\n.I xx\\^\nis the capability.\nFor example, the entry\n.PP\n\thn\\||\\|2621\\-nl:ks@:ke@:tc=2621:\n.PP\ndefines a \\*(lq2621\\-nl\\*(rq that does not have the\n.B ks\nor\n.B ke\ncapabilities,\nhence does not turn on the function key labels when in visual mode.\nThis is useful for different modes for a terminal, or for different\nuser preferences.\n.SH AUTHOR\nWilliam Joy\n.br\nMark Horton added underlining and keypad support\n.SH FILES\n.DT\n/etc/termcap\tfile containing terminal descriptions\n.SH SEE ALSO\nex(1), more(1), tset(1), ul(1), vi(1), curses(3X), printf(3S), term(7).\n.SH \"CAVEATS AND BUGS\"\n.B Note:\n.I termcap\\^\nwas replaced by\n.I terminfo\\^\nin UNIX System V Release 2.0.\nThe transition will be relatively painless if capabilities flagged as\n\\*(lqobsolete\\*(rq are avoided.\n.PP\nLines and columns are now stored by the kernel as well as in the termcap\nentry.\nMost programs now use the kernel information primarily; the information\nin this file is used only if the kernel does not have any information.\n.PP\n.I Vi\\^\nallows only 256 characters for string capabilities, and the routines\nin \n.IR termlib\\^ (3)\ndo not check for overflow of this buffer.\nThe total length of a single entry (excluding only escaped newlines)\nmay not exceed 1024.\n.PP\nNot all programs support all entries.\n"
  },
  {
    "path": "share/man/man5/tp.5",
    "content": ".\\\"\t@(#)tp.5\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH TP 5  \"May 15, 1985\"\n.AT 3\n.SH NAME\ntp \\- DEC/mag tape formats\n.SH DESCRIPTION\n.I Tp\ndumps files to and extracts files from\nDECtape and magtape.\nThe formats of these tapes are the same except\nthat magtapes have larger directories.\n.PP\nBlock zero contains a\ncopy of a stand-alone bootstrap program.\nSee\n.IR reboot (8).\n.PP\nBlocks 1 through 24\nfor DECtape (1 through 62 for magtape)\ncontain a directory of the tape.\nThere are 192 (resp. 496) entries in the directory;\n8 entries per block;\n64 bytes per entry.\nEach entry has the following format:\n.nf\n.IP \"\"\n.ta 8n +\\w'unsigned short  'u\nstruct {\n\tchar\tpathname[32];\n\tunsigned short\tmode;\n\tchar\tuid;\n\tchar\tgid;\n\tchar\tunused1;\n\tchar\tsize[3];\n\tlong\tmodtime;\n\tunsigned short\ttapeaddr;\n\tchar\tunused2[16];\n\tunsigned short\tchecksum;\n};\n.fi\n.DT\n.PP\nThe path name entry is the path name of the\nfile when put on the tape.\nIf the pathname starts with a zero word,\nthe entry is empty.\nIt is at most 32 bytes long and ends in a null byte.\nMode, uid, gid, size and time modified\nare the same as described under i-nodes \n(see file system\n.IR fs (5)).\nThe tape address is the tape block number of the start of\nthe contents of the file.\nEvery file\nstarts on a block boundary.\nThe file occupies (size+511)/512 blocks\nof continuous tape.\nThe checksum entry has a value such that\nthe sum of the 32 words of the directory entry is zero.\n.PP\nBlocks above 25 (resp. 63) are available for file storage.\n.PP\nA fake entry\nhas a size of zero.\n.SH \"SEE ALSO\"\nfs(5), tp(1)\n.SH BUGS\nThe\n.I pathname, uid, gid,\nand\n.I size\nfields are too small.\n"
  },
  {
    "path": "share/man/man5/ttys.5",
    "content": ".\\\"\t@(#)ttys.5\t6.4.1 (2.11BSD) 1996/11/16\n.\\\"\n.TH TTYS 5  \"November 16, 1996\"\n.AT 3\n.SH NAME\nttys \\- terminal initialization data\n.SH DESCRIPTION\nThe\n.I ttys\nfile contains information that is used by various routines to initialize\nand control the use of terminal special files. This information is read\nwith the\n.IR getttyent (3)\nlibrary routines.\nThere is one line in the \n.I ttys\nfile per special file.\nFields are separated by tabs and/or spaces.\nSome fields may contain more than one word and should be enclosed\nin double quotes.\nBlank lines and comments can appear anywhere in the file; comments\nare delimited by `#' and new line. Unspecified fields default to null.\nThe first field is the terminal's entry in the device directory, /dev.\nThe second field of the file is the command to execute for the line,\ntypically\n.IR getty (8),\nwhich performs such tasks as baud-rate recognition, reading the login name,\nand calling\n.IR login (1).\nIt can be, however, any desired command, for example\nthe start up for a window system terminal emulator or some other\ndaemon process, and can contain multiple words if quoted.\nThe third field is the type of terminal normally connected to that\ntty line, as found in the\n.IR termcap (5)\ndata base file.\nThe remaining fields set flags in the\n.I ty_status\nentry (see\n.IR getttyent (3))\nor specify a window system process that\n.IR init (8)\nwill maintain for the terminal line.\nAs flag values,\nthe strings `on' and `off' specify whether\n.I init\nshould execute the command\ngiven in the second field,\nwhile `secure' in addition to `on' allows root to login on\nthis line.  These flag fields should not be quoted.\nThe string `window=' is followed by a quoted command\nstring which\n.I init\nwill execute before starting\n.IR getty .\nIf the line ends in a comment, the comment is included in the\n.I ty_comment\nfield of the ttyent structure.\n.PP\nSome examples:\n.PP\n.nf\n.ta \\w'console\\ 'u +\\w'\"/usr/libexec/getty std.9600\"\\ \\ \\ 'u +\\w'hp2621-nl\\ \\ \\ \\ 'u +.7i\nconsole\t\"/usr/libexec/getty std.1200\"\tvt100\ton secure\nttyd0\t\"/usr/libexec/getty d1200\"\tdialup\ton\t# 555-1234\nttyh0\t\"/usr/libexec/getty std.9600\"\thp2621-nl\ton\t# 254MC\nttyh1\t\"/usr/libexec/getty std.9600\"\tplugboard\ton\t# John's office\nttyp0\tnone\tnetwork\nttyp1\tnone\tnetwork\toff\nttyv0\t\"/usr/new/xterm -L :0\"\tvs100\ton window=\"/usr/new/Xvs100 0\"\n.fi\n.PP\nThe first example permits root login on the console at 1200 baud,\nthe second allows dialup at 1200 baud without root login,\nthe third and fourth allow login at 9600 baud with terminal types of\n\"hp2621-nl\" and \"plugboard\" respectively,\nthe fifth and sixth line are examples of network pseudo ttys, which\nshould not have\n.I getty\nenabled on them,\nand the last example shows a terminal emulator and window system\nstartup entry.\n.SH FILES\n/etc/ttys\n.SH \"SEE ALSO\"\nlogin(1), getttyent(3), gettytab(5), init(8), getty(8)\n"
  },
  {
    "path": "share/man/man5/types.5",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)types.5\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH TYPES 5 \"May 15, 1985\"\n.UC 4\n.SH NAME\ntypes \\- primitive system data types\n.SH SYNOPSIS\n.B #include <sys/types.h>\n.SH DESCRIPTION\nThe data types defined in the include file\nare used in UNIX system code;\nsome data of these types are accessible to user code:\n.PP\n.nf\n.ta \\w'typedef\\ \\ 'u +\\w'minor(x)\\ \\ 'u +\\w' short\\ \\ 'u\n.so /usr/include/sys/types.h\n.fi\n.PP\nThe form\n.I daddr_t\nis used for disk addresses except in an\ni-node on disk, see\n.IR fs (5).\nTimes are encoded in seconds since 00:00:00 GMT, January 1, 1970.\nThe major and minor parts of a device code\nspecify kind and unit number of a device\nand are installation-dependent.\nOffsets are measured in bytes from the beginning of a file.\nThe\n.I label_t\nvariables are used to save the processor state\nwhile another process is running.\n.SH SEE ALSO\nfs(5), time(3), lseek(2), adb(1)\n"
  },
  {
    "path": "share/man/man5/tzfile.5",
    "content": ".\\\"\t@(#)tzfile.5\t1.2 (Berkeley) 3/11/87\n.\\\"\n.TH TZFILE 5 \"March 11, 1987\"\n.AT 5\n.SH NAME\ntzfile \\- time zone information\n.SH SYNOPSIS\n.B\n#include <tzfile.h>\n.SH DESCRIPTION\nThe time zone information files used by\n.IR tzset (3)\nbegin with bytes reserved for future use,\nfollowed by three four-byte values of type\n.BR long ,\nwritten in a ``standard'' byte order\n(the high-order byte of the value is written first).\nThese values are,\nin order:\n.TP\n.I tzh_timecnt\nThe number of \"transition times\" for which data is stored\nin the file.\n.TP\n.I tzh_typecnt\nThe number of \"local time types\" for which data is stored\nin the file (must not be zero).\n.TP\n.I tzh_charcnt\nThe number of characters of \"time zone abbreviation strings\"\nstored in the file.\n.PP\nThe above header is followed by\n.I tzh_timecnt\nfour-byte values of type\n.BR long ,\nsorted in ascending order.\nThese values are written in ``standard'' byte order.\nEach is used as a transition time (as returned by\n.IR time (2))\nat which the rules for computing local time change.\nNext come\n.I tzh_timecnt\none-byte values of type\n.BR \"unsigned char\" ;\neach one tells which of the different types of ``local time'' types\ndescribed in the file is associated with the same-indexed transition time.\nThese values serve as indices into an array of\n.I ttinfo\nstructures that appears next in the file; \nthese structures are defined as follows:\n.in +.5i\n.sp\n.nf\n.ta .5i +\\w'unsigned int\\0\\0'u\nstruct ttinfo {\t\n\tlong\ttt_gmtoff;\n\tint\ttt_isdst;\n\tunsigned int\ttt_abbrind;\n};\n.in -.5i\n.fi\n.sp\nEach structure is written as a four-byte value for\n.I tt_gmtoff\nof type\n.BR long ,\nin a standard byte order, followed by a one-byte value for\n.I tt_isdst\nand a one-byte value for\n.IR tt_abbrind .\nIn each structure,\n.I tt_gmtoff\ngives the number of seconds to be added to GMT,\n.I tt_isdst\ntells whether\n.I tm_isdst\nshould be set by\n.I localtime (3)\nand\n.I tt_abbrind\nserves as an index into the array of time zone abbreviation characters\nthat follow the\n.I ttinfo\nstructure(s) in the file.\n.PP\n.I Localtime\nuses the first standard-time\n.I ttinfo\nstructure in the file\n(or simply the first\n.I ttinfo\nstructure in the absence of a standard-time structure)\nif either\n.I tzh_timecnt\nis zero or the time argument is less than the first transition time recorded\nin the file.\n.SH SEE ALSO\nctime(3)\n"
  },
  {
    "path": "share/man/man5/utmp.5",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)utmp.5\t6.2.1 (2.11BSD) 1996/11/27\n.\\\"\n.TH UTMP 5  \"November 27, 1996\"\n.UC 4\n.SH NAME\nutmp, wtmp \\- login records\n.SH SYNOPSIS\n.B #include <utmp.h>\n.SH DESCRIPTION\nThe\n.I utmp\nfile records information about who is currently using the system.\nThe file is a sequence of entries with the following\nstructure declared in the include file:\n.RS\n.PP\n.nf\n.so /usr/include/utmp.h\n.fi\n.RE\n.PP\nThis structure gives the name of the special file\nassociated with the user's terminal, the user's login name,\nand the time of the login in the form of\n.IR time (3C).\n.PP\nThe\n.I wtmp\nfile records all logins and logouts.\nA null user name indicates a logout on the associated terminal.\nFurthermore, the terminal name `~' indicates that the\nsystem was rebooted at the indicated time;\nthe adjacent pair of entries with terminal names\n`\\^|\\^' and `{' indicate the system-maintained time just before and just after a\n.I date\ncommand has changed the system's idea of the time.\n.PP\n.I Wtmp\nis maintained by\n.IR login (1)\nand\n.IR init (8).\nNeither of these programs creates the file,\nso if it is removed record-keeping is turned off.  It is summarized by\n.IR ac (8).\n.SH FILES\n/var/run/utmp\n.br\n/usr/adm/wtmp\n.SH \"SEE ALSO\"\nlogin(1), init(8), who(1), ac(8)\n"
  },
  {
    "path": "share/man/man5/uuencode.5",
    "content": ".\\\"\t@(#)uuencode.5\t6.1 (Berkeley) 5/15/85\n.\\\"\n.TH UUENCODE 5 \"May 15, 1985\"\n.AT 3\n.SH NAME\nuuencode \\- format of an encoded uuencode file\n.SH DESCRIPTION\nFiles output by\n.I uuencode(1C)\nconsist of a header line,\nfollowed by a number of body lines,\nand a trailer line.\n.I Uudecode(1C)\nwill ignore any lines preceding the header or\nfollowing the trailer.\nLines preceding a header must not, of course,\nlook like a header.\n.PP\nThe header line is distinguished by having the first\n6 characters \\*(lqbegin\\ \\*(rq.\nThe word\n.I begin\nis followed by a mode (in octal),\nand a string which names the remote file.\nA space separates the three items in the header line.\n.PP\nThe body consists of a number of lines, each at most 62 characters\nlong (including the trailing newline).\nThese consist of a character count,\nfollowed by encoded characters,\nfollowed by a newline.\nThe character count is a single printing character,\nand represents an integer, the number of bytes\nthe rest of the line represents.\nSuch integers are always in the range from 0 to 63 and can\nbe determined by subtracting the character space (octal 40)\nfrom the character.\n.PP\nGroups of 3 bytes are stored in 4 characters, 6 bits per character.\nAll are offset by a space to make the characters printing.\nThe last line may be shorter than the normal 45 bytes.\nIf the size is not a multiple of 3, this fact can be determined\nby the value of the count on the last line.\nExtra garbage will be included to make the character count a multiple\nof 4.\nThe body is terminated by a line with a count of zero.\nThis line consists of one ASCII space.\n.PP\nThe trailer line consists of \\*(lqend\\*(rq on a line by itself.\n.SH \"SEE ALSO\"\nuuencode(1C), uudecode(1C), uusend(1C), uucp(1C), mail(1)\n"
  },
  {
    "path": "share/man/man5/vfont.5",
    "content": ".\\\"\t@(#)vfont.5\t6.2.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH VFONT 5 \"October 22, 1996\"\n.AT 3\n.SH NAME\nvfont \\- font formats for the Benson-Varian or Versatec\n.SH SYNOPSIS\n.B /usr/share/vfont/\\(**\n.SH DESCRIPTION\nThe fonts for the printer/plotters have the following format.\nEach file contains a header, an array of 256 character description\nstructures, and then the bit maps for the characters themselves.\nThe header has the following format:\n.in +5\n.nf\n.sp\n.ta 8n +\\w'unsigned short  'u\nstruct header {\n\tshort\tmagic;\n\tunsigned short\tsize;\n\tshort\tmaxx;\n\tshort\tmaxy;\n\tshort\txtnd;\n} header;\n.fi\n.in -5\n.PP\nThe\n.I magic\nnumber is 0436 (octal).\nThe\n.I maxx,\n.I maxy,\nand\n.I xtnd\nfields are not used at the current time.\n.I Maxx\nand\n.I maxy\nare intended to be the maximum horizontal and vertical size of\nany glyph in the font, in raster lines.\nThe\n.I size\nis the size of the\nbit maps for the characters in bytes.\nBefore the maps for the characters is an array of 256 structures for\neach of the possible characters in the font.\nEach element of the array has the form:\n.in +5\n.nf\n.sp\n.ta 8n +\\w'unsigned short  'u\nstruct dispatch {\n\tunsigned short\taddr;\n\tshort\tnbytes;\n\tchar\tup;\n\tchar\tdown;\n\tchar\tleft;\n\tchar\tright;\n\tshort\twidth;\n};\n.fi\n.in -5\n.PP\nThe\n.I nbytes\nfield is nonzero for characters which actually exist.\nFor such characters, the\n.I addr\nfield is an offset into the rest of the file where the data for\nthat character begins.\nThere are\n.I up+down\nrows of data for each character,\neach of which has\n.I left+right\nbits, rounded up to a number of bytes.\nThe\n.I width\nfield is not used by vcat,\nalthough it is\nto make width tables for\n.IR troff .\nIt represents the logical width of the glyph, in raster lines,\nand shows where the base point of the next glyph would be.\n.SH FILES\n/usr/share/vfont/\\(**\n.SH SEE ALSO\ntroff(1), pti(1), vfontinfo(1)\n"
  },
  {
    "path": "share/man/man5/vgrindefs.5",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)vgrindefs.5\t6.1.1 (2.11BSD) 1996/10/22\n.\\\"\n.tr ||\n.TH VGRINDEFS 5 \"October 22, 1996\"\n.UC 5\n.SH NAME\nvgrindefs \\- vgrind's language definition data base\n.SH SYNOPSIS\n.B /usr/share/misc/vgrindefs\n.SH DESCRIPTION\n.I Vgrindefs\ncontains all language definitions for vgrind.  The data base is\nvery similar to \n.IR termcap (5).\n.SH FIELDS\nThe following table names and describes each field.  \n.PP\n.nf\n.ta \\w'k0-k9  'u +\\w'Type  'u\n\\fBName\tType\tDescription\\fR\npb\tstr\tregular expression for start of a procedure\nbb\tstr\tregular expression for start of a lexical block\nbe\tstr\tregular expression for the end of a lexical block\ncb\tstr\tregular expression for the start of a comment\nce\tstr\tregular expression for the end of a comment\nsb\tstr\tregular expression for the start of a string\nse\tstr\tregular expression for the end of a string\nlb\tstr\tregular expression for the start of a character constant\nle\tstr\tregular expression for the end of a character constant\ntl\tbool\tpresent means procedures are only defined at the top \n\t\tlexical level\noc\tbool\tpresent means upper and lower case are equivalent\nkw\tstr\ta list of keywords separated by spaces\n.fi\n.PP\n.B Example\n.PP\nThe following entry, which describes the C language, is \ntypical of a language entry.\n.PP\n.nf\nC|c:\\\n\t:pb=^\\ed?*?\\ed?\\ep\\ed?\\e(\\ea?\\e):bb={:be=}:cb=/*:ce=*/:sb=\":se=\\ee\":\\e\n\t:lb=':le=\\ee':tl:\\e\n\t:kw=asm auto break case char continue default do double else enum\\e\n\textern float for fortran goto if int long register return short\\e\n\tsizeof static struct switch typedef union unsigned while #define\\e\n\t#else #endif #if #ifdef #ifndef #include #undef # define else endif\\e\n\tif ifdef ifndef include undef:\n.fi\n.PP\nNote that the first field is just the language name (and any variants\nof it).  Thus the C language could be specified to\n.IR vgrind (1)\nas \"c\" or \"C\".\n.PP\nEntries may continue onto multiple lines by giving a \\e as the last\ncharacter of a line.\nCapabilities in\n.I vgrindefs\nare of two types:\nBoolean capabilities which indicate that the language has\nsome particular feature\nand string\ncapabilities which give a regular expression or \nkeyword list.\n.PP\n.B REGULAR EXPRESSIONS\n.PP\n.I Vgrindefs\nuses regular expression which are very similar to those of \n.IR ex (1)\nand\n.IR lex (1).\nThe characters `^', `$', `:' and `\\e'\nare reserved characters and must be\n\"quoted\" with a preceding \\e if they\nare to be included as normal characters.\nThe metasymbols and their meanings are:\n.IP $\nthe end of a line\n.IP ^\nthe beginning of a line\n.IP \\ed\na delimiter (space, tab, newline, start of line)\n.IP \\ea\nmatches any string of symbols (like .* in lex)\n.IP \\ep\nmatches any alphanumeric name.  In a procedure definition (pb) the string\nthat matches this symbol is used as the procedure name.\n.IP ()\ngrouping\n.IP |\nalternation\n.IP ?\nlast item is optional\n.IP \\ee\npreceding any string means that the string will not match an\ninput string if the input string is preceded by an escape character (\\e).\nThis is typically used for languages (like C) which can include the\nstring delimiter in a string b escaping it.\n.PP\nUnlike other regular expressions in the system,  these match words\nand not characters.  Hence something like \"(tramp|steamer)flies?\"\nwould match \"tramp\", \"steamer\", \"trampflies\", or \"steamerflies\".\n.PP\n.B KEYWORD LIST\n.PP\nThe keyword list is just a list of keywords in the language separated\nby spaces.  If the \"oc\" boolean is specified, indicating that upper\nand lower case are equivalent, then all the keywords should be \nspecified in lower case.\n.SH FILES\n.DT\n/usr/share/misc/vgrindefs\tfile containing terminal descriptions\n.SH SEE ALSO\nvgrind(1), troff(1)\n.SH AUTHOR\nDave Presotto\n.SH BUGS\n"
  },
  {
    "path": "share/man/man6/Makefile",
    "content": "#\n# Copyright (c) 1987 Regents of the University of California.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms are permitted\n# provided that the above copyright notice and this paragraph are\n# duplicated in all such forms and that any documentation,\n# advertising materials, and other materials related to such\n# distribution and use acknowledge that the software was developed\n# by the University of California, Berkeley.  The name of the\n# University may not be used to endorse or promote products derived\n# from this software without specific prior written permission.\n# THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n# IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n# WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n#\n#\t@(#)Makefile\t5.4.1 (2.11BSD) 1996/01/26\n#\nTOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nMDIR=\t/usr/share/man/cat6\nSRCS=\tintro.6\nOBJS=\tintro.0\n\n.SUFFIXES: .6 .0\n\n.6.0:\n\t${MANROFF} $*.6 > $*.0\n\nall: _make_01\n\n_make_01: ${OBJS}\n\nclean: FRC\n\trm -f ${OBJS}\n\ninstall: _make_01\n\tcp ${OBJS} ${DESTDIR}${MDIR}\n\nFRC:\n"
  },
  {
    "path": "share/man/man6/intro.6",
    "content": ".\\\"\t$OpenBSD: intro.6,v 1.17 2018/09/30 13:24:33 schwarze Exp $\n.\\\"\n.\\\" Copyright (c) 1999 Hugh Graham\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.Dd May 24, 2025\n.Dt INTRO 6\n.Os\n.Sh NAME\n.Nm intro\n.Nd introduction to the games\n.Sh SYNOPSIS\nWould you like to play a game?\n.Sh DESCRIPTION\nThe manual pages in section 6 contain information about the\nvarious games and diversions optionally installed in\n.Pa /usr/games .\nCurrently available games are:\n.Bl -ohang -offset indent\n.It aclock\nASCII clock for UNIX console.\n.It Xr adventure 6\nAn exploration game.\n.It Xr arithmetic 6\nQuiz on simple arithmetic.\n.It Xr atc 6\nAir traffic controller game.\n.It Xr backgammon 6\nThe backgammon game.\n.It Xr banner 6\nPrint strings in large letters.\n.It Xr battlestar 6\nA tropical adventure game.\n.It Xr bcd 6\nReformat input as punch cards.\n.It Xr boggle 6\nWord search game.\n.It Xr caesar 6\nDecrypt caesar cyphers.\n.It Xr canfield 6\nA version of the solitaire card game.\n.It Xr cfscores 6\nPrint out the current status of a\n.Xr canfield 6\naccount.\n.It Xr cribbage 6\nThe card game cribbage.\n.It factor\nFactor a number.\n.It Xr fish 6\nPlay\n.Dq Go Fish! .\n.It Xr fortune 6\nPrint a random adage.\n.It Xr hangman 6\nPlay hangman.\n.It Xr mille 6\nPlay Mille Bornes.\n.It Xr monop 6\nPlay monopoly.\n.It morse\nReformat input as morse code.\n.It Xr number 6\nConvert Arabic numerals to English.\n.It Xr pig 6\n.\\\" Do not fix the following gibberish and broken link.\n.\\\" According to jmc@, both are intentional exactly as they are.\nEformatray inputway asway Igpay Atinlay.\nEesay\n.Xr igpay 6 .\n.It Xr pom 6\nDisplay the phase of the moon.\n.It Xr ppt 6\nReformat input as paper tape.\n.It primes\nGenerate primes.\n.It Xr quiz 6\nRandom knowledge tests.\n.It Xr rain 6\nAnimated raindrops display.\n.It Xr robots 6\nFight off villainous robots.\n.It Xr rogue 6\nExplore the Dungeons of Doom.\n.It Xr sail 6\nMulti-user wooden ships and iron men.\n.It Xr snake 6\nDisplay chase game.\n.It Xr snscore 6\nSee who wastes time playing\n.Xr snake 6 .\n.It teachgammon\nBackgammon rules and tutorial.\nSee\n.Xr backgammon 6 .\n.It Xr trek 6\nTrekkie game.\n.It Xr worm 6\nPlay the growing worm game.\n.It Xr worms 6\nAnimate worms on a display terminal.\n.It Xr wump 6\nHunt the wumpus in an underground cave.\n.El\n.Sh FILES\n.Bl -tag -width \"/usr/games/libXXX\" -compact\n.It Pa /usr/games\nLocation of games.\n.It Pa /usr/games/lib\nData files for games.\n.El\n.Sh SEE ALSO\n.Xr adventure 6 ,\n.Xr arithmetic 6 ,\n.Xr atc 6 ,\n.Xr backgammon 6 ,\n.Xr banner 6 ,\n.Xr battlestar 6 ,\n.Xr bcd 6 ,\n.Xr boggle 6 ,\n.Xr caesar 6 ,\n.Xr canfield 6 ,\n.Xr cfscores 6 ,\n.Xr cribbage 6 ,\n.Xr fish 6 ,\n.Xr fortune 6 ,\n.Xr hangman 6 ,\n.Xr mille 6 ,\n.Xr monop 6 ,\n.Xr number 6 ,\n.Xr pig 6 ,\n.Xr pom 6 ,\n.Xr ppt 6 ,\n.Xr primes 6 ,\n.Xr quiz 6 ,\n.Xr rain 6 ,\n.Xr robots 6 ,\n.Xr rogue 6 ,\n.Xr sail 6 ,\n.Xr snake 6 ,\n.Xr snscore 6 ,\n.Xr trek 6 ,\n.Xr worm 6 ,\n.Xr worms 6 ,\n.Xr wump 6\n.Sh HISTORY\nAn\n.Nm intro\nmanual for section 6 appeared in\n.Bx Disco\n2.5.\n"
  },
  {
    "path": "share/man/man7/Makefile",
    "content": "#\n# Copyright (c) 1987 Regents of the University of California.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms are permitted\n# provided that the above copyright notice and this paragraph are\n# duplicated in all such forms and that any documentation,\n# advertising materials, and other materials related to such\n# distribution and use acknowledge that the software was developed\n# by the University of California, Berkeley.  The name of the\n# University may not be used to endorse or promote products derived\n# from this software without specific prior written permission.\n# THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n# IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n# WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n#\n#\t@(#)Makefile\t5.4.1 (2.11BSD) 1996/01/26\n#\nTOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nMDIR=\t/usr/share/man/cat7\nSRCS=\tascii.7 environ.7 eqnchar.7 hier.7 hostname.7  intro.7 mailaddr.7 \\\n\tman.7 me.7 ms.7 term.7\nOBJS=\tascii.0 environ.0 eqnchar.0 hier.0 hostname.0 intro.0 mailaddr.0 \\\n\tman.0 me.0 ms.0 term.0\n\n.SUFFIXES: .7 .0\n\n.7.0:\n\t${MANROFF} $*.7 > $*.0\n\nall: _make_01\n\n_make_01: ${OBJS}\n\nclean: FRC\n\trm -f ${OBJS}\n\ninstall: _make_01\n\tcp ${OBJS} ${DESTDIR}${MDIR}\n\tln -f ${DESTDIR}${MDIR}/intro.0 ${DESTDIR}${MDIR}/miscellaneous.0\n\nFRC:\n"
  },
  {
    "path": "share/man/man7/ascii.7",
    "content": ".\\\"\t@(#)ascii.7\t6.1 (Berkeley) 5/20/85\n.\\\"\n.TH ASCII 7 \"May 20, 1985\"\n.AT 3\n.SH NAME\nascii \\- map of ASCII character set\n.SH SYNOPSIS\n.B cat /usr/pub/ascii\n.SH DESCRIPTION\n.I Ascii\nis a map of the ASCII character set, to be printed as needed.\nIt contains:\n.nf\n\n.cs R 20\n|000 nul|001 soh|002 stx|003 etx|004 eot|005 enq|006 ack|007 bel|\n|010 bs |011 ht |012 nl |013 vt |014 np |015 cr |016 so |017 si |\n|020 dle|021 dc1|022 dc2|023 dc3|024 dc4|025 nak|026 syn|027 etb|\n|030 can|031 em |032 sub|033 esc|034 fs |035 gs |036 rs |037 us |\n|040 sp |041  ! |042  \" |043  # |044  $ |045  % |046  & |047  \\' |\n|050  ( |051  ) |052  * |053  + |054  , |055  \\- |056  . |057  / |\n|060  0 |061  1 |062  2 |063  3 |064  4 |065  5 |066  6 |067  7 |\n|070  8 |071  9 |072  : |073  ; |074  < |075  = |076  > |077  ? |\n|100  @ |101  A |102  B |103  C |104  D |105  E |106  F |107  G |\n|110  H |111  I |112  J |113  K |114  L |115  M |116  N |117  O |\n|120  P |121  Q |122  R |123  S |124  T |125  U |126  V |127  W |\n|130  X |131  Y |132  Z |133  [ |134  \\\\ |135  ] |136  ^ |137  _ |\n|140  \\` |141  a |142  b |143  c |144  d |145  e |146  f |147  g |\n|150  h |151  i |152  j |153  k |154  l |155  m |156  n |157  o |\n|160  p |161  q |162  r |163  s |164  t |165  u |166  v |167  w |\n|170  x |171  y |172  z |173  { |174  | |175  } |176  ~ |177 del|\n\n| 00 nul| 01 soh| 02 stx| 03 etx| 04 eot| 05 enq| 06 ack| 07 bel|\n| 08 bs | 09 ht | 0a nl | 0b vt | 0c np | 0d cr | 0e so | 0f si |\n| 10 dle| 11 dc1| 12 dc2| 13 dc3| 14 dc4| 15 nak| 16 syn| 17 etb|\n| 18 can| 19 em | 1a sub| 1b esc| 1c fs | 1d gs | 1e rs | 1f us |\n| 20 sp | 21  ! | 22  \" | 23  # | 24  $ | 25  % | 26  & | 27  \\' |\n| 28  ( | 29  ) | 2a  * | 2b  + | 2c  , | 2d  \\- | 2e  . | 2f  / |\n| 30  0 | 31  1 | 32  2 | 33  3 | 34  4 | 35  5 | 36  6 | 37  7 |\n| 38  8 | 39  9 | 3a  : | 3b  ; | 3c  < | 3d  = | 3e  > | 3f  ? |\n| 40  @ | 41  A | 42  B | 43  C | 44  D | 45  E | 46  F | 47  G |\n| 48  H | 49  I | 4a  J | 4b  K | 4c  L | 4d  M | 4e  N | 4f  O |\n| 50  P | 51  Q | 52  R | 53  S | 54  T | 55  U | 56  V | 57  W |\n| 58  X | 59  Y | 5a  Z | 5b  [ | 5c  \\\\ | 5d  ] | 5e  ^ | 5f  _ |\n| 60  \\` | 61  a | 62  b | 63  c | 64  d | 65  e | 66  f | 67  g |\n| 68  h | 69  i | 6a  j | 6b  k | 6c  l | 6d  m | 6e  n | 6f  o |\n| 70  p | 71  q | 72  r | 73  s | 74  t | 75  u | 76  v | 77  w |\n| 78  x | 79  y | 7a  z | 7b  { | 7c  | | 7d  } | 7e  ~ | 7f del|\n.fi\n.cs R\n.SH FILES\n/usr/pub/ascii\n"
  },
  {
    "path": "share/man/man7/environ.7",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)environ.7\t6.1 (Berkeley) 5/20/85\n.\\\"\n.TH ENVIRON 7 \"May 20, 1985\"\n.UC 5\n.SH NAME\nenviron \\- user environment\n.SH SYNOPSIS\n.B extern char **environ;\n.SH DESCRIPTION\nAn array of strings called the `environment' is made available by\n.IR execve (2)\nwhen a process begins.  By convention these strings have the form\n.RI ` name = value '.\nThe following names are used by various commands:\n.TP \"\\w'TERMCAP 'u\"\nPATH\nThe sequence of directory prefixes that\n.I sh, time,\n.IR nice (1),\netc., apply in searching for a file known by an incomplete path name.\nThe prefixes are separated by `:'.\n.IR Login (1)\nsets PATH=:/usr/ucb:/bin:/usr/bin.\n.TP\nHOME\nA user's login directory, set by\n.IR login (1)\nfrom the password file\n.IR passwd (5).\n.TP\nTERM\nThe kind of terminal for which output is to be prepared.\nThis information is used by commands, such as\n.I nroff\nor\n.IR plot (1G),\nwhich may exploit special terminal capabilities.  See\n.I /etc/termcap\n.RI ( termcap (5))\nfor a list of terminal types.\n.TP\nSHELL\nThe file name of the users login shell.\n.TP\nTERMCAP\nThe string describing the terminal in TERM, or the name of the termcap file, see\n.IR termcap (5), termcap (3X).\n.TP\nEXINIT\nA startup list of commands read by\n.IR ex (1),\n.IR edit (1),\nand\n.IR vi (1).\n.TP\nUSER\nThe login name of the user.\n.TP\nPRINTER\nThe name of the default printer to be used by\n.IR lpr (1),\n.IR lpq (1),\nand\n.IR lprm (1).\n.PP\nFurther names may be placed in the environment by the\n.I export\ncommand and `name=value' arguments in\n.IR sh (1),\nor by the\n.I setenv\ncommand if you use\n.IR csh (1).\nArguments may also be placed in the environment at the point of an\n.IR execve (2).\nIt is unwise to conflict with certain \n.IR sh (1)\nvariables that are frequently exported by `.profile' files:\nMAIL, PS1, PS2, IFS.\n.SH SEE ALSO\ncsh(1),\nex(1),\nlogin(1),\nsh(1),\nexecve(2),\nsystem(3),\ntermcap(3X),\ntermcap(5)\n"
  },
  {
    "path": "share/man/man7/eqnchar.7",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)eqnchar.7\t6.1 (Berkeley) 5/20/85\n.\\\"\n.TH EQNCHAR 7 \"May 20, 1985\"\n.UC 3\n.EQ\ntdefine ciplus % \"\\o'\\(pl\\(ci'\" %\nndefine ciplus % O\b+ %\ntdefine citimes % \"\\o'\\(mu\\(ci'\" %\nndefine citimes % O\bx %\ntdefine =wig % \"\\(eq\\h'-\\w'\\(eq'u-\\w'\\s-2\\(ap'u/2u'\\v'-.4m'\\s-2\\z\\(ap\\(ap\\s+2\\v'.4m'\\h'\\w'\\(eq'u-\\w'\\s-2\\(ap'u/2u'\" %\nndefine =wig % =\b\"~\" %\ntdefine bigstar % \"\\o'\\(pl\\(mu'\" %\nndefine bigstar % X\b|\b- %\ntdefine =dot % \"\\z\\(eq\\v'-.6m'\\h'.2m'\\s+2.\\s-2\\v'.6m'\\h'.1m'\" %\nndefine =dot % = dot %\ntdefine orsign % \"\\s-2\\v'-.15m'\\z\\e\\e\\h'-.05m'\\z\\(sl\\(sl\\v'.15m'\\s+2\" %\nndefine orsign % \\e/ %\ntdefine andsign % \"\\s-2\\v'-.15m'\\z\\(sl\\(sl\\h'-.05m'\\z\\e\\e\\v'.15m'\\s+2\" %\nndefine andsign % /\\e %\ntdefine =del % \"\\v'.3m'\\z=\\v'-.6m'\\h'.3m'\\s-1\\(*D\\s+1\\v'.3m'\" %\nndefine =del % = to DELTA %\ntdefine oppA % \"\\s-2\\v'-.15m'\\z\\e\\e\\h'-.05m'\\z\\(sl\\(sl\\v'-.15m'\\h'-.75m'\\z-\\z-\\h'.2m'\\z-\\z-\\v'.3m'\\h'.4m'\\s+2\" %\nndefine oppA % V\b- %\ntdefine oppE %\"\\s-3\\v'.2m'\\z\\(em\\v'-.5m'\\z\\(em\\v'-.5m'\\z\\(em\\v'.55m'\\h'.9m'\\z\\(br\\z\\(br\\v'.25m'\\s+3\" %\nndefine oppE % E\b/ %\ntdefine incl % \"\\s-1\\z\\(or\\h'-.1m'\\v'-.45m'\\z\\(em\\v'.7m'\\z\\(em\\v'.2m'\\(em\\v'-.45m'\\s+1\" %\nndefine incl % C\b_ %\ntdefine nomem % \"\\o'\\(mo\\(sl'\" %\nndefine nomem % C\b-\b/ %\ntdefine angstrom % \"\\fR\\zA\\v'-.3m'\\h'.2m'\\(de\\v'.3m'\\fP\\h'.2m'\" %\nndefine angstrom % A to o %\ntdefine star %{ roman \"\\v'.5m'\\s+3*\\s-3\\v'-.5m'\"}%\nndefine star % * %\ntdefine || % \\(or\\(or %\ntdefine <wig % \"\\z<\\v'.4m'\\(ap\\v'-.4m'\" %\nndefine <wig %{ < from \"~\" }%\ntdefine >wig % \"\\z>\\v'.4m'\\(ap\\v'-.4m'\" %\nndefine >wig %{ > from \"~\" }%\ntdefine langle % \"\\s-3\\b'\\(sl\\e'\\s0\" %\nndefine langle %<%\ntdefine rangle % \"\\s-3\\b'\\e\\(sl'\\s0\" %\nndefine rangle %>%\ntdefine hbar % \"\\zh\\v'-.6m'\\h'.05m'\\(ru\\v'.6m'\" %\nndefine hbar % h\b\\u-\\d %\nndefine ppd % _\b| %\ntdefine ppd % \"\\o'\\(ru\\s-2\\(or\\s+2'\" %\ntdefine <-> % \"\\o'\\(<-\\(->'\" %\nndefine <-> % \"<-->\" %\ntdefine <=> % \"\\s-2\\z<\\v'.05m'\\h'.2m'\\z=\\h'.55m'=\\h'-.6m'\\v'-.05m'>\\s+2\" %\nndefine <=> % \"<=>\" %\ntdefine |< % \"\\o'<\\(or'\" %\nndefine |< % <\b| %\ntdefine |> % \"\\o'>\\(or'\" %\nndefine |> % |\b> %\ntdefine ang % \"\\v'-.15m'\\z\\s-2\\(sl\\s+2\\v'.15m'\\(ru\" %\nndefine ang % /\b_ %\ntdefine rang % \"\\z\\(or\\h'.15m'\\(ru\" %\nndefine rang % L %\ntdefine 3dot % \"\\v'-.8m'\\z.\\v'.5m'\\z.\\v'.5m'.\\v'-.2m'\" %\nndefine 3dot % .\b\\u.\b\\u.\\d\\d %\ntdefine thf % \".\\v'-.5m'.\\v'.5m'.\" %\nndefine thf % ..\b\\u.\\d %\ntdefine quarter % roman \\(14 %\nndefine quarter % 1/4 %\ntdefine 3quarter % roman \\(34 %\nndefine 3quarter % 3/4 %\ntdefine degree % \\(de %\nndefine degree % nothing sup o %\ntdefine square % \\(sq %\nndefine square % [] %\ntdefine circle % \\(ci %\nndefine circle % O %\ntdefine blot % \"\\fB\\(sq\\fP\" %\nndefine blot % H\bI\bX %\ntdefine bullet % \\(bu %\nndefine bullet % o\bx\be %\ntdefine -wig % \"\\(~=\" %\nndefine -wig % - to \"~\" %\ntdefine wig % \\(ap %\nndefine wig % \"~\" %\ntdefine prop % \\(pt %\nndefine prop % oc %\ntdefine empty % \\(es %\nndefine empty % O\b/ %\ntdefine member % \\(mo %\nndefine member % C\b- %\ntdefine cup % \\(cu %\nndefine cup % U %\ndefine cap % \\(ca %\ndefine subset % \\(sb %\ndefine supset % \\(sp %\ndefine !subset % \\(ib %\ndefine !supset % \\(ip %\n.EN\n.SH NAME\neqnchar \\- special character definitions for eqn\n.SH SYNOPSIS\n.B eqn /usr/pub/eqnchar\n[ files ]\n.B \\(bv troff\n[ options ]\n.PP\n.B neqn /usr/pub/eqnchar\n[ files ]\n.B \\(bv nroff\n[ options ]\n.SH DESCRIPTION\n.I Eqnchar\ncontains\n.I troff\nand\n.I nroff\ncharacter definitions for constructing characters that are not\navailable on the Graphic Systems typesetter.\nThese definitions are primarily intended for use with\n.I eqn\nand\n.IR neqn .\nIt contains definitions for the following characters\n.PP\n.nf\n.ta \\w'angstrom  'u \\n(.lu/3u +\\w'angstrom  'u \\n(.lu*2u/3u +\\w'angstrom  'u\n.EQ\n\"ciplus\"\tciplus\t\"|\\||\"\t||\t\"square\"\tsquare\n.EN\n.EQ\n\"citimes\"\tcitimes\t\"langle\"\tlangle\t\"circle\"\tcircle\n.EN\n.EQ\n\"wig\"\twig\t\"rangle\"\trangle\t\"blot\"\tblot\n.EN\n.EQ\n\"-wig\"\t-wig\t\"hbar\"\thbar\t\"bullet\"\tbullet\n.EN\n.EQ\n\">wig\"\t>wig\t\"ppd\"\tppd\t\"prop\"\tprop\n.EN\n.EQ\n\"<wig\"\t<wig\t\"<->\"\t<->\t\"empty\"\tempty\n.EN\n.EQ\n\"=wig\"\t=wig\t\"<=>\"\t<=>\t\"member\"\tmember\n.EN\n.EQ\n\"star\"\tstar\t\"|\\|<\"\t|<\t\"nomem\"\tnomem\n.EN\n.EQ\n\"bigstar\"\tbigstar\t\"|\\|>\"\t|>\t\"cup\"\tcup\n.EN\n.EQ\n\"=dot\"\t=dot\t\"ang\"\tang\t\"cap\"\tcap\n.EN\n.EQ\n\"orsign\"\torsign\t\"rang\"\trang\t\"incl\"\tincl\n.EN\n.EQ\n\"andsign\"\tandsign\t\"3dot\"\t3dot\t\"subset\"\tsubset\n.EN\n.EQ\n\"=del\"\t=del\t\"thf\"\tthf\t\"supset\"\tsupset\n.EN\n.EQ\n\"oppA\"\toppA\t\"quarter\"\tquarter\t\"!subset\"\t!subset\n.EN\n.EQ\n\"oppE\"\toppE\t\"3quarter\"\t3quarter\t\"!supset\"\t!supset\n.EN\n.EQ\n\"angstrom\"\tangstrom\t\"degree\"\tdegree\n.EN\n.SH FILES\n/usr/pub/eqnchar\n.SH SEE ALSO\ntroff(1), eqn(1)\n"
  },
  {
    "path": "share/man/man7/hier.7",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)hier.7\t6.1 (Berkeley) 5/20/85\n.\\\"\n.TH HIER 7 \"May 20, 1985\"\n.UC 4\n.SH NAME\nhier \\- file system hierarchy\n.SH DESCRIPTION\nThe following outline gives a quick tour through a representative\ndirectory hierarchy.\n.na\n.nh\n.IP /\nroot\n.PD 0\n.IP /vmunix\nthe kernel binary (UNIX itself)\n.IP /lost+found\ndirectory for connecting detached files for\n.IR fsck (8)\n.IP /dev/\ndevices (4)\n.RS\n.IP MAKEDEV\nshell script to create special files\n.IP MAKEDEV.local\nsite specific part of MAKEDEV\n.IP console\nmain console,\n.IR tty (4)\n.IP tty*\nterminals,\n.IR tty (4)\n.IP hp*\ndisks,\n.IR hp (4)\n.IP rhp*\nraw disks,\n.IR hp (4)\n.IP up*\nUNIBUS disks\n.IR up (4)\n.IP ...\n.RE\n.IP /bin/\nutility programs, cf /usr/bin/ (1)\n.RS\n.IP as\nassembler\n.IP cc\nC compiler executive, cf /lib/ccom, /lib/cpp, /lib/c2\n.IP csh\nC shell\n.IP ...\n.RE\n.IP /lib/\nobject libraries and other stuff, cf /usr/lib/\n.RS\n.IP libc.a\nsystem calls, standard I/O, etc. (2,3,3S)\n.IP ...\n.IP ccom\nC compiler proper\n.IP cpp\nC preprocessor\n.IP c2\nC code improver\n.IP ...\n.RE\n.IP /etc/\nessential data and maintenance utilities; sect (8)\n.RS\n.IP dump\ndump program\n.IR dump (8)\n.IP passwd\npassword file,\n.IR passwd (5)\n.IP group\ngroup file,\n.IR group (5)\n.IP motd\nmessage of the day,\n.IR login (1)\n.IP termcap\ndescription of terminal capabilities,\n.IR termcap (5)\n.IP ttytype\ntable of what kind of terminal is on each port,\n.IR ttytype (5)\n.IP mtab\nmounted file table,\n.IR mtab (5)\n.IP dumpdates\ndump history,\n.IR dump (8)\n.IP fstab\nfile system configuration table\n.IR fstab (5)\n.IP disktab\ndisk characteristics and partition tables,\n.IR disktab (5)\n.IP hosts\nhost name to network address mapping file,\n.IR hosts (5)\n.IP networks\nnetwork name to network number mapping file,\n.IR networks (5)\n.IP protocols\nprotocol name to protocol number mapping file,\n.IR protocols (5)\n.IP services\nnetwork services definition file,\n.IR services (5)\n.IP remote\nnames and description of remote hosts for \n.IR tip (1C),\n.IR remote (5)\n.IP phones\nprivate phone numbers for remote hosts, as described in\n.IR phones (5)\n.IP ttys\nproperties of terminals,\n.IR ttys (5)\n.IP getty\npart of\n.IR login ,\n.IR getty (8)\n.IP init\nthe parent of all processes,\n.IR init (8)\n.IP rc\nshell program to bring the system up\n.IP rc.local\nsite dependent portion of \n.I rc\n.IP cron\nthe clock daemon,\n.IR cron (8)\n.IP mount\n.IR mount (8)\n.IP ...\n.RE\n.IP /sys/\nsystem source\n.RS\n.IP h/\nheader (include) files\n.RS\n.IP acct.h\n.IR acct (5)\n.IP stat.h\n.IR stat (2)\n.IP ...\n.RE\n.IP sys/\nmachine independent system source \n.RS\n.IP init_main.c\n.IP uipc_socket.c\n.IP ufs_syscalls.c\n.IP ...\n.RE\n.IP conf/\nsite configuration files\n.RS\n.IP GENERIC\n.IP ...\n.RE\n.IP net/\ngeneral network source\n.IP netinet/\nDARPA Internet network source\n.IP netimp/\nnetwork code related to use of an IMP\n.RS\n.IP if_imp.c\n.IP if_imphost.c\n.IP if_imphost.h\n.IP ...\n.RE\n.IP vax/\nsource specific to the VAX\n.RS\n.IP locore.s\n.IP machdep.c\n.IP ...\n.RE\n.IP vaxuba/\ndevice drivers for hardware which resides on the UNIBUS\n.RS\n.IP uba.c\n.IP dh.c\n.IP up.c\n.IP ...\n.RE\n.IP vaxmba/\ndevice drivers for hardware which resides on the MASBUS\n.RS\n.IP mba.c\n.IP hp.c\n.IP ht.c\n.IP ...\n.RE\n.IP vaxif\nnetwork interface drivers for the VAX\n.RS\n.IP if_en.c\n.IP if_ec.c\n.IP if_vv.c\n.IP ...\n.RE\n.RE\n.IP /tmp/\ntemporary files, usually on a fast device, cf /usr/tmp/\n.RS\n.IP e*\nused by\n.IR ed (1)\n.IP ctm*\nused by \n.IR cc (1)\n.IP ...\n.RE\n.IP /usr/\ngeneral-pupose directory, usually a mounted file system\n.RS\n.IP adm/\nadministrative information\n.RS\n.IP wtmp\nlogin history,\n.IR utmp (5)\n.IP messages\nhardware error messages\n.IP tracct\nphototypesetter accounting,\n.IR troff (1)\n.IP lpacct\nline printer accounting\n.IR lpr (1)\n.IP \"vaacct, vpacct\"\nvarian and versatec accounting\n.IR vpr (1),\n.IR vtroff (1),\n.IR pac (8)\n.RE\n.RE\n.IP /usr\\t/bin\n.RS\nutility programs, to keep /bin/ small\n.IP tmp/\ntemporaries, to keep /tmp/ small\n.RS\n.IP stm*\nused by\n.IR sort (1)\n.IP raster\nused by\n.IR plot (1G)\n.RE\n.IP dict/\nword lists, etc.\n.RS\n.IP words\nprincipal word list, used by\n.IR look (1)\n.IP spellhist\nhistory file for\n.IR spell (1)\n.RE\n.IP games/\n.RS\n.IP hangman\n.IP lib/\nlibrary of stuff for the games\n.RS\n.IP quiz.k/\nwhat\n.IR quiz (6)\nknows\n.RS\n.IP index\ncategory index\n.IP africa\ncountries and capitals\n.IP ...\n.RE\n.IP ...\n.RE\n.IP ...\n.RE\n.IP include/\nstandard #include files\n.RS\n.IP a.out.h\nobject file layout,\n.IR a.out (5)\n.IP stdio.h\nstandard I/O,\n.IR intro (3S)\n.IP math.h\n(3M)\n.IP ...\n.IP sys/\nsystem-defined layouts, cf /sys/h\n.IP net/\nsymbolic link to sys/net\n.IP machine/\nsymbolic link to sys/machine\n.IP ...\n.RE\n.IP lib/\nobject libraries and stuff, to keep /lib/ small\n.RS\n.IP atrun\nscheduler for\n.IR at (1)\n.IP lint/\nutility files for lint\n.RS\n.IP lint[12]\nsubprocesses for\n.IR lint (1)\n.IP llib-lc\ndummy declarations for /lib/libc.a, used by\n.IR lint (1)\n.IP llib-lm\ndummy declarations for /lib/libc.m\n.IP ...\n.RE\n.IP struct/\npasses of\n.IR struct (1)\n.IP ...\n.IP tmac/\nmacros for\n.IR troff (1)\n.RS\n.IP tmac.an\nmacros for\n.IR man (7)\n.IP tmac.s\nmacros for\n.IR ms (7)\n.IP ...\n.RE\n.IP font/\nfonts for\n.IR troff (1)\n.RS\n.IP ftR\nTimes Roman\n.IP ftB\nTimes Bold\n.IP ...\n.RE\n.IP uucp/\nprograms and data for\n.IR uucp (1C)\n.RS\n.IP L.sys\nremote system names and numbers\n.IP uucico\nthe real copy program\n.IP ...\n.RE\n.IP units\nconversion tables for\n.IR units (1)\n.IP eign\nlist of English words to be ignored by\n.IR ptx (1)\n.RE\n.RE\n.br\n.ne 5\n.IP /usr/\\tman/\n.RS\nvolume 1 of this manual,\n.IR man (1)\n.RS\n.IP man0/\ngeneral\n.RS\n.IP intro\nintroduction to volume 1,\n.IR ms (7)\nformat\n.IP xx\ntemplate for manual page\n.RE\n.IP man1/\nchapter 1\n.RS\n.IP as.1\n.IP mount.1m\n.IP ...\n.RE\n.IP ...\n.IP cat1/\npreformatted pages for section 1\n.IP ...\n.RE\n.IP msgs/\nmessages, cf\n.IR msgs (1)\n.RS\n.IP bounds\nhighest and lowest message\n.RE\n.IP new/\nbinaries of new versions of programs\n.IP preserve/\neditor temporaries preserved here after crashes/hangups\n.IP public/\nbinaries of user programs - write permission to everyone\n.IP spool/\ndelayed execution files\n.RS\n.IP at/\nused by \n.IR at (1)\n.IP lpd/\nused by\n.IR lpr (1)\n.RS\n.IP lock\npresent when line printer is active\n.IP cf*\ncopy of file to be printed, if necessary\n.IP df*\ndaemon control file,\n.IR lpd (8)\n.IP tf*\ntransient control file, while \n.I lpr\nis working\n.RE\n.IP uucp/\nwork files and staging area for \n.IR uucp (1C)\n.RS\n.IP LOGFILE\nsummary log\n.IP LOG.*\nlog file for one transaction\n.RE\n.IP mail/\nmailboxes for\n.IR mail (1)\n.RS\n.TP\n.I name\nmail file for user\n.I name\n.TP\n.IR name .lock\nlock file while\n.I name\nis receiving mail\n.RE\n.IP secretmail/\nlike\n.IR mail /\n.IP uucp/\nwork files and staging area for \n.IR uucp (1C)\n.RS\n.IP LOGFILE\nsummary log\n.IP LOG.*\nlog file for one transaction\n.IP mqueue/\nmail queue for \n.IR sendmail (8)\n.RE\n.RE\n.TP\n.I wd\ninitial working directory of a user,\ntypically\n.I wd\nis the user's login name\n.RS\n.TP\n.BR . profile\nset environment for\n.IR sh (1),\n.IR environ (7)\n.TP\n.BR . project\nwhat you are doing (used by (\n.IR finger (1)\n)\n.TP\n.BR . cshrc\nstartup file for\n.IR csh (1)\n.TP\n.BR . exrc\nstartup file for\n.IR ex (1)\n.TP\n.BR . plan\nwhat your short-term plans are (used by\n.IR finger (1)\n)\n.TP\n.BR . netrc\nstartup file for various network programs\n.TP\n.BR . msgsrc\nstartup file for\n.IR msgs (1)\n.TP\n.BR . mailrc\nstartup file for\n.IR mail (1)\n.IP calendar\nuser's datebook for\n.IR calendar (1)\n.RE\n.IP doc/\npapers, mostly in volume 2 of this manual, typically in\n.IR ms (7)\nformat\n.RS\n.IP as/\nassembler manual\n.IP c\nC manual\n.IP ...\n.RE\n.RE\n.RE\n.IP /usr/\\tsrc/\n.RS\n.IP\nsource programs for utilities, etc.\n.RS\n.IP bin/\nsource of commands in /bin\n.RS\n.IP as/\nassembler\n.IP ar.c\nsource for\n.IR ar (1)\n.IP ...\n.RE\n.IP usr.bin/\nsource for commands in /usr/bin\n.RS\n.IP troff/\nsource for\n.I nroff\nand\n.IR troff (1)\n.RS\n.IP font/\nsource for font tables, /usr/lib/font/\n.RS\n.IP ftR.c\nRoman\n.IP ...\n.RE\n.IP term/\nterminal characteristics tables, /usr/lib/term/\n.RS\n.IP tab300.c\nDASI 300\n.IP ...\n.RE\n.IP ...\n.RE\n.RE\n.IP ucb\nsource for programs in /usr/ucb\n.IP games/\nsource for /usr/games\n.IP lib/\nsource for programs and archives in /lib\n.RS\n.IP libc/\nC runtime library\n.RS\n.IP csu/\nstartup and wrapup routines needed with every C program\n.RS\n.IP crt0.s\nregular startup\n.IP mcrt0.s\nmodified startup for\n.I cc \\-p\n.RE\n.IP sys/\nsystem calls (2)\n.RS\n.IP access.s\n.IP brk.s\n.IP ...\n.RE\n.RE\n.IP stdio/\nstandard I/O functions (3S)\n.RS\n.IP fgets.c\n.IP fopen.c\n.IP ...\n.RE\n.IP gen/\nother functions in (3)\n.RS\n.IP abs.c\n.IP ...\n.RE\n.IP net/\nnetwork functions in (3N)\n.RS\n.IP gethostbyname.c\n.IP ...\n.RE\n.RE\n.IP local/\nsource which isn't normally distributed\n.IP new/\nsource for new versions of commands and library routines\n.IP old/\nsource for old versions of commands and library routines\n.IP ucb/\nbinaries of programs developed at UCB\n.RS\n.IP ...\n.IP edit\neditor for beginners\n.IP ex\ncommand editor for experienced users\n.IP ...\n.IP mail\nmail reading/sending subsystem\n.IP man\non line documentation\n.IP ...\n.IP pi\nPascal translator\n.IP px\nPascal interpreter\n.IP ...\n.IP vi\nvisual editor\n.RE\n.RE\n.ad\n.SH SEE ALSO\nls(1),\napropos(1),\nwhatis(1),\nwhereis(1),\nfinger(1),\nwhich(1),\nncheck(8),\nfind(1),\ngrep(1)\n.SH BUGS\nThe position of files is subject to change without notice.\n"
  },
  {
    "path": "share/man/man7/hostname.7",
    "content": ".\\\" Copyright (c) 1987 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)hostname.7\t6.1 (Berkeley) 11/21/87\n.\\\"\n.TH HOSTNAME 7 \"November 21, 1987\"\n.UC 5\n.SH NAME\nhostname \\- host name resolution description\n.SH DESCRIPTION\nHostnames are domains, where a domain is a hierarchical, dot-separated\nlist of subdomains; for example, the machine monet, in the Berkeley\nsubdomain of the EDU subdomain of the ARPANET would be represented as\n.br\n\t\tmonet.Berkeley.EDU\n.br\n(with no trailing dot).\n.PP\nHostnames are often used with network client and server programs,\nwhich must generally translate the name to an address for use.\n(This function is generally performed by the library routine\n.IR gethostbyname (3).)\nHostnames are resolved by the internet name resolver in the following\nfashion.\n.PP\nIf the name consists of a single component, i.e. contains no dot,\nand if the environment variable ``HOSTALIASES'' is set to the name of a file,\nthat file is searched for an string matching the input hostname.\nThe file should consist of lines made up of two white-space separated strings,\nthe first of which is the hostname alias,\nand the second of which is the complete hostname\nto be substituted for that alias.\nIf a case-sensitive match is found between the hostname to be resolved\nand the first field of a line in the file, the substituted name is looked\nup with no further processing.\n.PP\nIf the input name ends with a trailing dot,\nthe trailing dot is removed,\nand the remaining name is looked up with no further processing.\n.PP\nIf the input name does not end with a trailing dot, it is looked up in\nthe local domain and its parent domains until either a match is found\nor fewer than 2 components of the local domain remain.  For example,\nin the domain CS.Berkeley.EDU, the name lithium.CChem will be checked first\nas lithium.CChem.CS.Berkeley.EDU and then as lithium.CChem.Berkeley.EDU.\nLithium.CChem.EDU will not be tried, as the there is only one component\nremaining from the local domain.\n.SH SEE ALSO\ngethostbyname(3), resolver(5), mailaddr(7), named(8), RFC883\n"
  },
  {
    "path": "share/man/man7/intro.7",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)intro.7\t6.1 (Berkeley) 5/20/85\n.\\\"\n.TH INTRO 7  \"May 20, 1985\"\n.UC 5\n.SH NAME\nmiscellaneous \\- miscellaneous useful information pages\n.SH DESCRIPTION\nThis section contains miscellaneous documentation, mostly\nin the area of text processing macro packages for\n.IR troff (1).\n.sp 2\n.nf\n.ta 1.25i\nascii\tmap of ASCII character set\nenviron\tuser environment\neqnchar\tspecial character definitions for eqn\nhier\tfile system hierarchy\nmailaddr\tmail addressing description\nman\tmacros to typeset manual pages\nme\tmacros for formatting papers\nms\tmacros for formatting manuscripts\nterm\tconventional names for terminals\n.fi\n"
  },
  {
    "path": "share/man/man7/mailaddr.7",
    "content": ".\\\" Copyright (c) 1983, 1987 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)mailaddr.7\t6.4 (Berkeley) 7/27/87\n.\\\"\n.TH MAILADDR 7 \"July 27, 1987\"\n.UC 5\n.SH NAME\nmailaddr \\- mail addressing description\n.SH DESCRIPTION\nMail addresses are based on the ARPANET protocol listed at the end of this\nmanual page.  These addresses are in the general format\n.PP\n\t\tuser@domain\n.PP\nwhere a domain is a hierarchical dot separated list of subdomains.  For\nexample, the address\n.PP\n\t\teric@monet.berkeley.edu\n.PP\nis normally interpreted from right to left: the message should go to the\nARPA name tables (which do not correspond exactly to the physical ARPANET),\nthen to the Berkeley gateway, after which it should go to the local host\nmonet.  When the message reaches monet it is delivered to the user ``eric''.\n.PP\nUnlike some other forms of addressing, this does not imply any routing.\nThus, although this address is specified as an ARPA address, it might\ntravel by an alternate route if that were more convenient or efficient.\nFor example, at Berkeley, the associated message would probably go directly\nto monet over the Ethernet rather than going via the Berkeley ARPANET\ngateway.\n.SS Abbreviation.\n.PP\nUnder certain circumstances it may not be necessary to type the entire\ndomain name.  In general, anything following the first dot may be omitted\nif it is the same as the domain from which you are sending the message.\nFor example, a user on ``calder.berkeley.edu'' could send to ``eric@monet''\nwithout adding the ``berkeley.edu'' since it is the same on both sending\nand receiving hosts.\n.PP\nCertain other abbreviations may be permitted as special cases.  For\nexample, at Berkeley, ARPANET hosts may be referenced without adding\nthe ``berkeley.edu'' as long as their names do not conflict with a local\nhost name.\n.SS Compatibility.\n.PP\nCertain old address formats are converted to the new format to provide\ncompatibility with the previous mail system.  In particular,\n.PP\n\t\tuser@host.ARPA\n.PP\nis allowed and\n.PP\n\t\thost:user\n.PP\nis converted to\n.PP\n\t\tuser@host\n.PP\nto be consistent with the \\fIrcp\\fP(1) command.\n.PP\nAlso, the syntax\n.PP\n\t\thost!user\n.PP\nis converted to:\n.PP\n\t\tuser@host.UUCP\n.PP\nThis is normally converted back to the ``host!user'' form before being sent\non for compatibility with older UUCP hosts.\n.PP\nThe current implementation is not able to route messages automatically through\nthe UUCP network.  Until that time you must explicitly tell the mail system\nwhich hosts to send your message through to get to your final destination.\n.SS Case Distinctions.\n.PP\nDomain names (i.e., anything after the ``@'' sign) may be given in any mixture\nof upper and lower case with the exception of UUCP hostnames.  Most hosts\naccept any combination of case in user names, with the notable exception of\nMULTICS sites.\n.SS Route-addrs.\n.PP\nUnder some circumstances it may be necessary to route a message through\nseveral hosts to get it to the final destination.  Normally this routing\nis done automatically, but sometimes it is desirable to route the message\nmanually.  Addresses which show these relays are termed ``route-addrs.''\nThese use the syntax:\n.PP\n\t\t<@hosta,@hostb:user@hostc>\n.PP\nThis specifies that the message should be sent to hosta, from there to hostb,\nand finally to hostc.  This path is forced even if there is a more efficient\npath to hostc.\n.PP\nRoute-addrs occur frequently on return addresses, since these are generally\naugmented by the software at each host.  It is generally possible to ignore\nall but the ``user@domain'' part of the address to determine the actual\nsender.\n.SS Postmaster.\n.PP\nEvery site is required to have a user or user alias designated ``postmaster''\nto which problems with the mail system may be addressed.\n.SS Other Networks.\n.PP\nSome other networks can be reached by giving the name of the network as the\nlast component of the domain.  \\fIThis is not a standard feature\\fP and may\nnot be supported at all sites.  For example, messages to CSNET or BITNET sites\ncan often be sent to ``user@host.CSNET'' or ``user@host.BITNET'' respectively.\n.SH BUGS\nThe RFC822 group syntax (``group:user1,user2,user3;'') is not supported\nexcept in the special case of ``group:;'' because of a conflict with old\nberknet-style addresses.\n.PP\nRoute-Address syntax is grotty.\n.PP\nUUCP- and ARPANET-style addresses do not coexist politely.\n.SH SEE ALSO\nmail(1), sendmail(8);\nCrocker, D. H.,\n.ul\nStandard for the Format of Arpa Internet Text Messages,\nRFC822.\n"
  },
  {
    "path": "share/man/man7/man.7",
    "content": ".\\\"\t@(#)man.7\t6.3.1 (2.11BSD) 1996/10/22\n.\\\"\n.TH MAN 7 \"October 22, 1996\"\n.AT 3\n.SH NAME\nman \\- macros to typeset manual\n.SH SYNOPSIS\n.B\nnroff  \\-man\\\nfile ...\n.PP\n.B\ntroff  \\-man\\\nfile ...\n.SH DESCRIPTION\nThese macros are used to lay out pages of this manual.\nA skeleton page may be found in the file\n/usr/man/man.template.\n.PP\nAny text argument\n.I t\nmay be zero to six words.\nQuotes may be used to include blanks in a `word'.\nIf\n.I text\nis empty,\nspecial treatment is applied to\nthe next input line with text to be printed.\nIn this way\n.BR . I\nmay be used to italicize a whole line, or\n.BR . SM\nmay be\nfollowed by\n.BR . B\nto make small bold letters.\n.PP\nA prevailing indent distance is remembered between\nsuccessive indented paragraphs,\nand is reset to default value upon reaching a non-indented paragraph.\nDefault units for indents\n.I i\nare ens.\n.PP\nType font and size are reset to default values\nbefore each paragraph, and after processing\nfont and size setting macros.\n.PP\nThese strings are predefined by\n.BR \\-man :\n.IP \\e*R\n.if t `\\*R', `(Reg)' in\n.if t .I nroff.\n.if n `(Reg)', trademark symbol in\n.if n .I troff.\n.IP \\e*S\nChange to default type size.\n.SH FILES\n/usr/share/tmac/tmac.an\n.br\n/usr/man/man.template\n.SH SEE ALSO\ntroff(1), man(1)\n.SH BUGS\nRelative indents don't nest.\n.SH REQUESTS\n.ta \\w'.TH n c x v m'u +\\w'Cause 'u +\\w'Argument\\ 'u\n.di xx\n\t\t\t\\ka\n.br\n.di\n.in \\nau\n.ti 0\nRequest\tCause\tIf no\tExplanation\n.ti 0\n\tBreak\tArgument\n.ti 0\n.tr ~.\n~B \\fIt\\fR\tno\t\\fIt\\fR=n.t.l.*\tText\n.I t\nis bold.\n.ti 0\n~BI \\fIt\\fR\tno\t\\fIt\\fR=n.t.l.\tJoin\nwords of\n.I t\nalternating bold and italic.\n.ti 0\n~BR \\fIt\\fR\tno\t\\fIt\\fR=n.t.l.\tJoin\nwords of\n.I t\nalternating bold and Roman.\n.ti 0\n~DT\tno\t.5i 1i...\tRestore default tabs.\n.ti 0\n~HP \\fIi\\fR\tyes\t\\fIi\\fR=p.i.*\tSet prevailing indent to\n.I i.\nBegin paragraph with hanging indent.\n.ti 0\n~I \\fIt\\fR\tno\t\\fIt\\fR=n.t.l.\tText\n.I t\nis italic.\n.ti 0\n~IB \\fIt\\fR\tno\t\\fIt\\fR=n.t.l.\tJoin\nwords of\n.I t\nalternating italic and bold.\n.ti 0\n~IP \\fIx i\\fR\tyes\t\\fIx\\fR=\"\"\tSame as .TP with tag\n.I x.\n.ti 0\n~IR \\fIt\\fR\tno\t\\fIt\\fR=n.t.l.\tJoin\nwords of\n.I t\nalternating italic and Roman.\n.ti 0\n~LP\tyes\t-\tSame as .PP.\n.ti 0\n~PD \\fId\\fR\tno\t\\fId\\fR=.4v\tInterparagraph distance is\n.I d.\n.ti 0\n~PP\tyes\t-\tBegin paragraph.\nSet prevailing indent to .5i.\n.ti 0\n~RE\tyes\t-\tEnd of relative indent.\nSet prevailing indent to amount of starting .RS.\n.ti 0\n~RB \\fIt\\fR\tno\t\\fIt\\fR=n.t.l.\tJoin\nwords of\n.I t\nalternating Roman and bold.\n.ti 0\n~RI \\fIt\\fR\tno\t\\fIt\\fR=n.t.l.\tJoin\nwords of\n.I t\nalternating Roman and italic.\n.ti 0\n~RS \\fIi\\fR\tyes\t\\fIi\\fR=p.i.\tStart relative indent,\nmove left margin in distance\n.I i.\nSet prevailing indent to .5i for nested indents.\n.ti 0\n~SH \\fIt\\fR\tyes\t\\fIt\\fR=n.t.l.\tSubhead.\n.ti 0\n~SM \\fIt\\fR\tno\t\\fIt\\fR=n.t.l.\tText\n.I t\nis small.\n.ti 0\n~TH \\fIn c x v m\\fR\tyes\t-\tBegin page named\n.I n\nof chapter\n.IR c;\n.I x\nis extra commentary, e.g. `local', for page foot center;\n.I v\nalters page foot left, e.g. `4th Berkeley Distribution';\n.I m\nalters page head center, e.g. `Brand X Programmer's Manual'.\nSet prevailing indent and tabs to .5i.\n.ti 0\n~TP \\fIi\\fR\tyes\t\\fIi\\fR=p.i.\tSet prevailing indent to\n.I i.\nBegin indented paragraph\nwith hanging tag given by next text line.\nIf tag doesn't fit, place it on separate line.\n.PP\n.ti 0\n* n.t.l. = next text line; p.i. = prevailing indent\n"
  },
  {
    "path": "share/man/man7/me.7",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)me.7\t6.3.1 (2.11BSD) 1996/10/23\n.\\\"\n.hc %\n.TH ME 7 \"October 23, 1996\"\n.UC 3\n.SH NAME\nme \\- macros for formatting papers\n.SH SYNOPSIS\n.B \"nroff \\-me\"\n[ options ]\nfile ...\n.br\n.B \"troff \\-me\"\n[ options ]\nfile ...\n.SH DESCRIPTION\nThis package of\n.I nroff\nand\n.I troff\nmacro definitions provides a canned formatting\nfacility for tech%nical papers in various formats.\nWhen producing 2-column output on a terminal, filter\nthe output through\n.IR  col (1).\n.PP\nThe macro requests are defined below.\nMany\n.I nroff\nand\n.I troff\nrequests are unsafe in conjunction with\nthis package, however, these requests may be used with\nimpunity after the first .pp:\n.nf\n.IP\n.ta \\w'.sz +n  'u\n\\&.bp\tbegin new page\n\\&.br\tbreak output line here\n\\&.sp n\tinsert n spacing lines\n\\&.ls n\t(line spacing) n=1 single, n=2 double space\n\\&.na\tno alignment of right margin\n\\&.ce n\tcenter next n lines\n\\&.ul n\tunderline next n lines\n\\&.sz +n\tadd n to point size\n.fi\n.PP\nOutput of the\n.I eqn,\n.I neqn,\n.I refer,\nand\n.IR  tbl (1)\npreprocessors\nfor equations and tables is acceptable as input.\n.SH FILES\n/usr/share/tmac/tmac.e\n.br\n/usr/share/me/*\n.SH \"SEE ALSO\"\neqn(1), troff(1), refer(1), tbl(1)\n.br\n\\-me Reference Manual, Eric P. Allman\n.br\nWriting Papers with Nroff Using \\-me\n.tr &.\n.SH REQUESTS\nIn the following list,\n\\*(lqinitialization\\*(rq\nrefers to the first .pp, .lp, .ip, .np, .sh, or .uh macro.\nThis list is incomplete;\nsee\n.I \"The \\-me Reference Manual\"\nfor interesting details.\n.PP\n.ta \\w'.eh \\'x\\'y\\'z\\'  'u +\\w'Initial 'u +\\w'Cause 'u\n.br\n.di x\n\t\t\t\\ka\n.br\n.di\n.in \\nau\n.ti 0\nRequest\tInitial\tCause\tExplanation\n.ti 0\n\tValue\tBreak\n.br\n.in \\nau\n.ti 0\n\\&.(c\t-\tyes\tBegin centered block\n.ti 0\n\\&.(d\t-\tno\tBegin delayed text\n.ti 0\n\\&.(f\t-\tno\tBegin footnote\n.ti 0\n\\&.(l\t-\tyes\tBegin list\n.ti 0\n\\&.(q\t-\tyes\tBegin major quote\n.ti 0\n\\&.(x \\fIx\\fR\t-\tno\tBegin indexed item in index\n.I x\n.ti 0\n\\&.(z\t-\tno\tBegin floating keep\n.ti 0\n\\&.)c\t-\tyes\tEnd centered block\n.ti 0\n\\&.)d\t-\tyes\tEnd delayed text\n.ti 0\n\\&.)f\t-\tyes\tEnd footnote\n.ti 0\n\\&.)l\t-\tyes\tEnd list\n.ti 0\n\\&.)q\t-\tyes\tEnd major quote\n.ti 0\n\\&.)x\t-\tyes\tEnd index item\n.ti 0\n\\&.)z\t-\tyes\tEnd floating keep\n.ti 0\n\\&.++ \\fIm H\\fR\t-\tno\tDefine paper section.\n.I m\ndefines the part of the paper, and can be\n.B C\n(chapter),\n.B A\n(appendix),\n.B P\n(preliminary, e.g., abstract, table of contents, etc.),\n.B B\n(bibliography),\n.B RC\n(chapters renumbered from page one each chapter),\nor\n.B RA\n(appendix renumbered from page one).\n.ti 0\n\\&.+c \\fIT\\fR\t-\tyes\tBegin chapter (or appendix, etc., as\nset by .++).\n.I T\nis the chapter title.\n.ti 0\n\\&.1c\t1\tyes\tOne column format on a new page.\n.ti 0\n\\&.2c\t1\tyes\tTwo column format.\n.ti 0\n\\&.EN\t-\tyes\tSpace after equation\nproduced by\n.I eqn\nor\n.IR neqn .\n.ti 0\n\\&.EQ \\fIx y\\fR\t-\tyes\tPrecede equation; break out and\nadd space.\nEquation number is\n.IR y .\nThe optional argument \\fIx\\fR\nmay be\n.I I\nto indent equation (default),\n.I L\nto left-adjust the equation, or\n.I C\nto center the equation.\n.ti 0\n\\&.GE\t-\tyes\tEnd \\fIgremlin\\fP picture.\n.ti 0\n\\&.GS\t-\tyes\tBegin \\fIgremlin\\fP picture.\n.ti 0\n\\&.PE\t-\tyes\tEnd \\fIpic\\fP picture.\n.ti 0\n\\&.PS\t-\tyes\tBegin \\fIpic\\fP picture.\n.ti 0\n\\&.TE\t-\tyes\tEnd table.\n.ti 0\n\\&.TH\t-\tyes\tEnd heading section of table.\n.ti 0\n\\&.TS \\fIx\\fR\t-\tyes\tBegin table; if \\fIx\\fR is\n.I H\ntable has repeated heading.\n.ti 0\n\\&.ac \\fIA N\\fR\t-\tno\tSet up for ACM style output.\n.I A\nis the Author's name(s),\n.I N\nis the total number of pages.\nMust be given before the first initialization.\n.ti 0\n\\&.b \\fIx\\fR\tno\tno\tPrint\n.I x\nin boldface; if no argument switch to boldface.\n.ti 0\n\\&.ba \\fI+n\\fR\t0\tyes\tAugments the base indent by\n.I n.\nThis indent is used to set the indent on regular text\n(like paragraphs).\n.ti 0\n\\&.bc\tno\tyes\tBegin new column\n.ti 0\n\\&.bi \\fIx\\fR\tno\tno\tPrint\n.I x\nin bold italics (nofill only)\n.ti 0\n\\&.bu\t-\tyes\tBegin bulleted paragraph\n.ti 0\n\\&.bx \\fIx\\fR\tno\tno\tPrint \\fIx\\fR in a box (nofill only).\n.ti 0\n\\&.ef \\fI\\'x\\'y\\'z\\'\\fR\t\\'\\'\\'\\'\tno\tSet even footer to x  y  z\n.ti 0\n\\&.eh \\fI\\'x\\'y\\'z\\'\\fR\t\\'\\'\\'\\'\tno\tSet even header to x  y  z\n.ti 0\n\\&.fo \\fI\\'x\\'y\\'z\\'\\fR\t\\'\\'\\'\\'\tno\tSet footer to x  y  z\n.ti 0\n\\&.hx\t-\tno\tSuppress headers and footers on next page.\n.ti 0\n\\&.he \\fI\\'x\\'y\\'z\\'\\fR\t\\'\\'\\'\\'\tno\tSet header to x  y  z\n.ti 0\n\\&.hl\t-\tyes\tDraw a horizontal line\n.ti 0\n\\&.i \\fIx\\fR\tno\tno\tItalicize\n.I x;\nif\n.I x\nmissing, italic text follows.\n.ti 0\n\\&.ip \\fIx y\\fR\tno\tyes\tStart indented paragraph,\nwith hanging tag\n.IR x .\nIndentation is\n.I y\nens (default 5).\n.ti 0\n\\&.lp\tyes\tyes\tStart left-blocked paragraph.\n.ti 0\n\\&.lo\t-\tno\tRead in a file of local macros of the\nform\n.BI \\&.* x.\nMust be given before initialization.\n.ti 0\n\\&.np\t1\tyes\tStart numbered paragraph.\n.ti 0\n\\&.of \\fI\\'x\\'y\\'z\\'\\fR\t\\'\\'\\'\\'\tno\tSet odd footer to x  y  z\n.ti 0\n\\&.oh \\fI\\'x\\'y\\'z\\'\\fR\t\\'\\'\\'\\'\tno\tSet odd header to x  y  z\n.ti 0\n\\&.pd\t-\tyes\tPrint delayed text.\n.ti 0\n\\&.pp\tno\tyes\tBegin paragraph.\nFirst line indented.\n.ti 0\n\\&.r\tyes\tno\tRoman text follows.\n.ti 0\n\\&.re\t-\tno\tReset tabs to default values.\n.ti 0\n\\&.sc\tno\tno\tRead in a file of special characters\nand diacritical marks.\nMust be given before initialization.\n.ti 0\n\\&.sh \\fIn x\\fR\t-\tyes\tSection head follows,\nfont automatically bold.\n.I n\nis level of section,\n.I x\nis title of section.\n.ti 0\n\\&.sk\tno\tno\tLeave the next page blank.\nOnly one page is remembered ahead.\n.ti 0\n\\&.sm \\fIx\\fR\t-\tno\tSet\n.I x\nin a smaller pointsize.\n.ti 0\n\\&.sz \\fI+n\\fR\t10p\tno\tAugment the point size by\n.I n\npoints.\n.ti 0\n\\&.th\tno\tno\tProduce the paper in thesis format.\nMust be given before initialization.\n.ti 0\n\\&.tp\tno\tyes\tBegin title page.\n.ti 0\n\\&.u \\fIx\\fR\t-\tno\tUnderline argument (even in \\fItroff\\fR).\n(Nofill only).\n.ti 0\n\\&.uh\t-\tyes\tLike .sh but unnumbered.\n.ti 0\n\\&.xp \\fIx\\fR\t-\tno\tPrint index\n.I x.\n"
  },
  {
    "path": "share/man/man7/ms.7",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)ms.7\t6.1.1 (2.11BSD) 1996/10/23\n.\\\"\n.TH MS 7 \"October 23, 1996\"\n.UC 4\n.ds ]W UCB Computer Center\n.SH NAME\nms \\- text formatting macros\n.SH SYNOPSIS\n\\fBnroff  \\-ms\\fP  [ options ]  file  ...\n.br\n\\fBtroff  \\-ms\\fP  [ options ]  file  ...\n.SH DESCRIPTION\nThis package of \\fInroff\\fP\\| and \\fItroff\\fP\\|\nmacro definitions provides a formatting facility\nfor various styles of articles, theses, and books.\nWhen producing 2-column output on a terminal or lineprinter,\nor when reverse line motions are needed,\nfilter the output through \\fIcol\\fP\\|(1).\nAll external \\-ms macros are defined below.\nMany \\fInroff\\fP\\| and \\fItroff\\fP\\| requests\nare unsafe in conjunction with this package.\nHowever, the first four requests below\nmay be used with impunity after initialization,\nand the last two may be used even before initialization:\n.sp .2\n.ta 5n 12n\n.nf\n\t.bp\tbegin new page\n\t.br\tbreak output line\n\t.sp n\tinsert n spacing lines\n\t.ce n\tcenter next n lines\n\t.ls n\tline spacing: n=1 single, n=2 double space\n\t.na\tno alignment of right margin\n.fi\n.sp .2\nFont and point size changes with \\ef and \\es are also allowed;\nfor example, ``\\efIword\\efR'' will italicize \\fIword.\\fP\nOutput of the \\fItbl, eqn,\\fP and \\fIrefer\\fP\\|(1) preprocessors\nfor equations, tables, and references is acceptable as input.\n.SH FILES\n/usr/share/tmac/tmac.x\n.br\n/usr/share/ms/x.???\n.SH \"SEE ALSO\"\neqn(1), refer(1), tbl(1), troff(1)\n.SH REQUESTS\n.if n .in 0\n.ds x \\fIx\\fP\\|\n.ds y \\fIy\\fP\\|\n.ds z \\fI y\\fP\n.ds Y \\fIx y\\fP\n.tr _.\n.ta \\w'MacroNam'u +\\w'InitialVal'u +\\w'Break? 'u\n.sp .3\n.nf\nMacro\tInitial\tBreak?\t\\0 Explanation\nName\tValue\tReset?\n.sp .3\n_AB \\*x\t\\-\ty\tbegin abstract; if \\*x=no don't label abstract\n_AE\t\\-\ty\tend abstract\n_AI\t\\-\ty\tauthor's institution\n_AM\t\\-\tn\tbetter accent mark definitions\n_AU\t\\-\ty\tauthor's name\n_B \\*x\t\\-\tn\tembolden \\*x; if no \\*x, switch to boldface\n_B1\t\\-\ty\tbegin text to be enclosed in a box\n_B2\t\\-\ty\tend boxed text and print it\n_BT\tdate\tn\tbottom title, printed at foot of page\n_BX \\*x\t\\-\tn\tprint word \\*x in a box\n_CM\tif t\tn\tcut mark between pages\n_CT\t\\-\ty,y\tchapter title: page number moved to CF (TM only)\n_DA \\*x\tif n\tn\tforce date \\*x at bottom of page; today if no \\*x\n_DE\t\\-\ty\tend display (unfilled text) of any kind\n_DS \\*Y\tI\ty\tbegin display with keep; \\*x=I,L,C,B; \\*y=indent \n_ID\\*z\t8n,.5i\ty\tindented display with no keep; \\*y=indent\n_LD\t\\-\ty\tleft display with no keep\n_CD\t\\-\ty\tcentered display with no keep\n_BD\t\\-\ty\tblock display; center entire block\n_EF \\*x\t\\-\tn\teven page footer \\*x (3 part as for .tl)\n_EH \\*x\t\\-\tn\teven page header \\*x (3 part as for .tl)\n_EN\t\\-\ty\tend displayed equation produced by \\fIeqn\\fP\n_EQ \\*Y\t\\-\ty\tbreak out equation; \\*x=L,I,C; \\*y=equation number\n_FE\t\\-\tn\tend footnote to be placed at bottom of page\n_FP\t\\-\tn\tnumbered footnote paragraph; may be redefined\n_FS \\*x\t\\-\tn\tstart footnote; \\*x is optional footnote label\n_HD\tundef\tn\toptional page header below header margin\n_I \\*x\t\\-\tn\titalicize \\*x; if no \\*x, switch to italics\n_IP \\*Y\t\\-\ty,y\tindented paragraph, with hanging tag \\*x; \\*y=indent\n_IX \\*Y\t\\-\ty\tindex words \\*x \\*y and so on (up to 5 levels)\n_KE\t\\-\tn\tend keep of any kind\n_KF\t\\-\tn\tbegin floating keep; text fills remainder of page\n_KS\t\\-\ty\tbegin keep; unit kept together on a single page\n_LG\t\\-\tn\tlarger; increase point size by 2\n_LP\t\\-\ty,y\tleft (block) paragraph.\n_MC \\*x\t\\-\ty,y\tmultiple columns; \\*x=column width\n_ND \\*x\tif t\tn\tno date in page footer; \\*x is date on cover\n_NH \\*Y\t\\-\ty,y\tnumbered header; \\*x=level, \\*x=0 resets, \\*x=S sets to \\*y\n_NL\t10p\tn\tset point size back to normal\n_OF \\*x\t\\-\tn\todd page footer \\*x (3 part as for .tl)\n_OH \\*x\t\\-\tn\todd page header \\*x (3 part as for .tl)\n_P1\tif TM\tn\tprint header on 1st page\n_PP\t\\-\ty,y\tparagraph with first line indented\n_PT\t- % -\tn\tpage title, printed at head of page\n_PX \\*x\t\\-\ty\tprint index (table of contents); \\*x=no suppresses title\n_QP\t\\-\ty,y\tquote paragraph (indented and shorter)\n_R\ton\tn\treturn to Roman font\n_RE\t5n\ty,y\tretreat: end level of relative indentation\n_RP \\*x\t\\-\tn\treleased paper format; \\*x=no stops title on 1st page\n_RS\t5n\ty,y\tright shift: start level of relative indentation\n_SH\t\\-\ty,y\tsection header, in boldface\n_SM\t\\-\tn\tsmaller; decrease point size by 2\n_TA\t8n,5n\tn\tset tabs to 8n 16n ... (nroff) 5n 10n ... (troff)\n_TC \\*x\t\\-\ty\tprint table of contents at end; \\*x=no suppresses title\n_TE\t\\-\ty\tend of table processed by \\fItbl\\fP\n_TH\t\\-\ty\tend multi-page header of table\n_TL\t\\-\ty\ttitle in boldface and two points larger\n_TM\toff\tn\tUC Berkeley thesis mode\n_TS \\*x\t\\-\ty,y\tbegin table; if \\*x=H table has multi-page header\n_UL \\*x\t\\-\tn\tunderline \\*x, even in \\fItroff\\fP\n_UX \\*x\t\\-\tn\tUNIX; trademark message first time; \\*x appended\n_XA \\*Y\t\\-\ty\tanother index entry; \\*x=page or no for none; \\*y=indent\n_XE\t\\-\ty\tend index entry (or series of .IX entries)\n_XP\t\\-\ty,y\tparagraph with first line exdented, others indented\n_XS \\*Y\t\\-\ty\tbegin index entry; \\*x=page or no for none; \\*y=indent\n_1C\ton\ty,y\tone column format, on a new page\n_2C\t\\-\ty,y\tbegin two column format\n_]-\t\\-\tn\tbeginning of \\fIrefer\\fP\\| reference\n_[0\t\\-\tn\tend of unclassifiable type of reference\n_[N\t\\-\tn\tN= 1:journal-article, 2:book, 3:book-article, 4:report\n.fi\n.if t .bp\n.DT\n.SH REGISTERS\nFormatting distances can be controlled in \\-ms\nby means of built-in number registers.\nFor example, this sets the line length to 6.5 inches:\n.sp .3\n\t.nr  LL  6.5i\n.sp .3\nHere is a table of number registers and their default values:\n.sp .3\n.nf\n.ta .5i +\\w'Name\\0'u +\\w'paragraph distance 'u +\\w'Takes Effect 'u\n\tName\tRegister Controls\tTakes Effect\tDefault\n.sp .3\n\tPS\tpoint size      \tparagraph\t10\n\tVS\tvertical spacing\tparagraph\t12\n\tLL\tline length     \tparagraph\t6i\n\tLT\ttitle length    \tnext page\tsame as LL\n\tFL\tfootnote length \tnext .FS\t5.5i\n\tPD\tparagraph distance\tparagraph\t1v (if n), .3v (if t)\n\tDD\tdisplay distance\tdisplays\t1v (if n), .5v (if t)\n\tPI\tparagraph indent\tparagraph\t5n\n\tQI\tquote indent    \tnext .QP\t5n\n\tFI\tfootnote indent \tnext .FS\t2n\n\tPO\tpage offset     \tnext page\t0 (if n), \\(ap1i (if t)\n\tHM\theader margin   \tnext page\t1i\n\tFM\tfooter margin   \tnext page\t1i\n\tFF\tfootnote format \tnext .FS\t0 (1, 2, 3 available)\n.fi\n.sp .3\nWhen resetting these values,\nmake sure to specify the appropriate units.\nSetting the line length to 7, for example,\nwill result in output with one character per line.\nSetting FF to 1 suppresses footnote superscripting;\nsetting it to 2 also suppresses indentation of the first line;\nand setting it to 3 produces an .IP-like footnote paragraph.\n.PP\nHere is a list of string registers available in \\-ms;\nthey may be used anywhere in the text:\n.sp .3\n.nf\n.ta .5i 1.1i\n\tName\tString's Function\n.sp .3\n\t\\e*Q\tquote (\" in \\fInroff,\\fP\\| `` in \\fItroff\\fP )\n\t\\e*U \tunquote (\" in \\fInroff,\\fP\\| '' in \\fItroff\\fP )\n\t\\e*\\-\tdash (-- in \\fInroff,\\fP \\(em in \\fItroff\\fP )\n\t\\e*(MO\tmonth (month of the year)\n\t\\e*(DY\tday (current date)\n\t\\e**\tautomatically numbered footnote\n\t\\e*\\'\tacute accent (before letter)\n\t\\e*\\`\tgrave accent (before letter)\n\t\\e*\\d^\t\\ucircumflex (before letter)\n\t\\e*,\tcedilla (before letter)\n\t\\e*:\tumlaut (before letter)\n\t\\e*\\d~\t\\utilde (before letter)\n.fi\n.sp .3\nWhen using the extended accent mark definitions available with .AM,\nthese strings should come after, rather than before,\nthe letter to be accented.\n.SH BUGS\nFloating keeps and regular keeps are diverted to the same space,\nso they cannot be mixed together with predictable results.\n"
  },
  {
    "path": "share/man/man7/term.7",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)term.7\t6.1 (Berkeley) 5/20/85\n.\\\"\n.TH TERM 7 \"May 20, 1985\"\n.UC 4\n.SH NAME\nterm \\- conventional names for terminals\n.SH DESCRIPTION\nCertain commands use these terminal names. They are maintained \nas part of the shell environment (see\n.IR sh (1), environ (7)).\n.LP\n.nf\n.ta \\w'450\\-12\\-8  'u\nadm3a\tLear Seigler Adm-3a\n2621\tHewlett-Packard HP262? series terminals\nhp\tHewlett-Packard HP264? series terminals\nc100\tHuman Designed Systems Concept 100\nh19\tHeathkit H19\nmime\tMicroterm mime in enhanced ACT IV mode\n1620\tDIABLO 1620 (and others using HyType II)\n300\tDASI/DTC/GSI 300 (and others using HyType I)\n33\tTELETYPE\\*R Model 33\n37\tTELETYPE Model 37\n43\tTELETYPE Model 43\n735\tTexas Instruments TI735 (and TI725)\n745\tTexas Instruments TI745\ndumb\tterminals with no special features\ndialup\ta terminal on a phone line with no known characteristics\nnetwork\ta terminal on a network connection with no known characteristics\n4014\tTektronix 4014\nvt52\tDigital Equipment Corp. VT52\n.fi\n.PP\nThe list goes on and on.\nConsult /etc/termcap (see\n.IR termcap (5))\nfor an up-to-date and locally correct list.\n.PP\nCommands whose behavior may depend on the terminal either consult TERM in\nthe environment, or accept arguments of the form\n.BR \\-Tterm,\nwhere\n.I term\nis one of the names given above.\n.SH SEE ALSO\nstty(1),\ntabs(1),\nplot(1G),\nsh(1),\nenviron(7)\nex(1),\nclear(1),\nmore(1),\nul(1),\ntset(1),\ntermcap(5),\ntermcap(3X),\nttytype(5)\n.br\ntroff(1) for\n.I nroff\n.SH BUGS\nThe programs that ought to adhere to this nomenclature do so only fitfully.\n"
  },
  {
    "path": "share/man/man8/Makefile",
    "content": "#\n# Copyright (c) 1987 Regents of the University of California.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms are permitted\n# provided that the above copyright notice and this paragraph are\n# duplicated in all such forms and that any documentation,\n# advertising materials, and other materials related to such\n# distribution and use acknowledge that the software was developed\n# by the University of California, Berkeley.  The name of the\n# University may not be used to endorse or promote products derived\n# from this software without specific prior written permission.\n# THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n# IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n# WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n#\n#\t@(#)Makefile\t5.4.7 (2.11BSD) 1997/1/10\n#\nTOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nMDIR=\t/usr/share/man/cat8\nSRCS=\tXNSrouted.8 adduser.8 autoconfig.8 \\\n\tbugfiler.8 crash.8 \\\n\tboot.8 \\\n\tdrtest.8 dump.8 dumpdir.8 \\\n\tformat.8 fsck.8 \\\n\tgetty.8 htable.8 \\\n\tintro.8 lpc.8 lpd.8 makedev.8 \\\n\tmakekey.8 \\\n\tnamed.8 pac.8 \\\n\trc.8 rdump.8 \\\n\trouted.8 rrestore.8 \\\n\tsendmail.8 \\\n\tsticky.8 sync.8 \\\n\ttimed.8 timedc.8 uucico.8 \\\n\tuuclean.8 uupoll.8 uusnap.8 uuxqt.8\nOBJS=\tXNSrouted.0 adduser.0 autoconfig.0 \\\n\tbugfiler.0 crash.0 \\\n\tboot.0 \\\n\tdrtest.0 dump.0 dumpdir.0 \\\n\tformat.0 fsck.0 \\\n\tgetty.0 htable.0 \\\n\tintro.0 lpc.0 lpd.0 makedev.0 \\\n\tmakekey.0 \\\n\tnamed.0 pac.0 \\\n\trc.0 rdump.0 \\\n\trouted.0 rrestore.0 \\\n\tsendmail.0 \\\n\tsticky.0 sync.0 \\\n\ttimed.0 timedc.0 uucico.0 \\\n\tuuclean.0 uupoll.0 uusnap.0 uuxqt.0\n\n.SUFFIXES: .8 .0\n\n.8.0:\n\t${MANROFF} $*.8 > $*.0\n\nall: _make_01\n\n_make_01: ${OBJS}\n\nclean: FRC\n\trm -f ${OBJS}\n\ninstall: _make_01\n\tcp ${OBJS} ${DESTDIR}${MDIR}\n\tln -f ${DESTDIR}${MDIR}/uucico.0 ${DESTDIR}${MDIR}/uucpd.0\n\nFRC:\n"
  },
  {
    "path": "share/man/man8/XNSrouted.8",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)XNSrouted.8\t\t6.1.1 (2.11BSD) 1996/11/1\n.\\\"\n.TH XNSROUTED 8 \"November 1, 1996\"\n.UC 6\n.SH NAME\nXNSrouted \\- NS Routing Information Protocol daemon\n.SH SYNOPSIS\n.B /sbin/XNSrouted\n[\n.B \\-s\n] [\n.B \\-q\n] [\n.B \\-t\n] [\n.I logfile\n]\n.SH DESCRIPTION\n.I XNSrouted\nis invoked at boot time to manage the Xerox NS routing tables.\nThe NS routing daemon uses the Xerox NS Routing\nInformation Protocol in maintaining up to date kernel routing\ntable entries.\n.PP\nIn normal operation\n.I XNSrouted\nlistens\nfor routing information packets.  If the host is connected to\nmultiple NS networks, it periodically supplies copies\nof its routing tables to any directly connected hosts\nand networks.\n.PP\nWhen\n.I XNSrouted\nis started, it uses the SIOCGIFCONF\n.I ioctl\nto find those\ndirectly connected interfaces configured into the\nsystem and marked ``up'' (the software loopback interface\nis ignored).  If multiple interfaces\nare present, it is assumed the host will forward packets\nbetween networks.\n.I XNSrouted\nthen transmits a \n.I request\npacket on each interface (using a broadcast packet if\nthe interface supports it) and enters a loop, listening\nfor\n.I request\nand\n.I response\npackets from other hosts.\n.PP\nWhen a\n.I request\npacket is received, \n.I XNSrouted\nformulates a reply based on the information maintained in its\ninternal tables.  The\n.I response\npacket generated contains a list of known routes, each marked\nwith a ``hop count'' metric (a count of 16, or greater, is\nconsidered ``infinite'').  The metric associated with each\nroute returned provides a metric\n.IR \"relative to the sender\" .\n.PP\n.I Response\npackets received by\n.I XNSrouted\nare used to update the routing tables if one of the following\nconditions is satisfied:\n.TP\n(1)\nNo routing table entry exists for the destination network\nor host, and the metric indicates the destination is ``reachable''\n(i.e. the hop count is not infinite).\n.TP\n(2)\nThe source host of the packet is the same as the router in the\nexisting routing table entry.  That is, updated information is\nbeing received from the very internetwork router through which\npackets for the destination are being routed.\n.TP\n(3)\nThe existing entry in the routing table has not been updated for\nsome time (defined to be 90 seconds) and the route is at least\nas cost effective as the current route.\n.TP\n(4)\nThe new route describes a shorter route to the destination than\nthe one currently stored in the routing tables; the metric of\nthe new route is compared against the one stored in the table\nto decide this.\n.PP\nWhen an update is applied,\n.I XNSrouted\nrecords the change in its internal tables and generates a\n.I response\npacket to all directly connected hosts and networks.\n.I Routed\nwaits a short period\nof time (no more than 30 seconds) before modifying the kernel's\nrouting tables to allow possible unstable situations to settle.\n.PP\nIn addition to processing incoming packets,\n.I XNSrouted\nalso periodically checks the routing table entries.\nIf an entry has not been updated for 3 minutes, the entry's metric\nis set to infinity and marked for deletion.  Deletions are delayed\nan additional 60 seconds to insure the invalidation is propagated\nto other routers.\n.PP\nHosts acting as internetwork routers gratuitously supply their\nrouting tables every 30 seconds to all directly connected hosts\nand networks.\n.PP\nSupplying the\n.B \\-s\noption forces \n.I XNSrouted\nto supply routing information whether it is acting as an internetwork\nrouter or not.\nThe\n.B \\-q\noption is the opposite of the\n.B \\-s\noption.  If the\n.B \\-t\noption is specified, all packets sent or received are\nprinted on the standard output.  In addition,\n.I XNSrouted\nwill not divorce itself from the controlling terminal\nso that interrupts from the keyboard will kill the process.\nAny other argument supplied is interpreted as the name\nof file in which \n.IR XNSrouted 's\nactions should be logged.  This log contains information\nabout any changes to the routing tables and a history of\nrecent messages sent and received which are related to\nthe changed route.\n.SH \"SEE ALSO\"\n``Internet Transport Protocols'', XSIS 028112, Xerox System Integration\nStandard.\n.br\nidp(4P)\n"
  },
  {
    "path": "share/man/man8/adduser.8",
    "content": ".\\\" Copyright (c) 1980 The Regents of the University of California.\n.\\\" All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms are permitted\n.\\\" provided that the above copyright notice and this paragraph are\n.\\\" duplicated in all such forms and that any documentation,\n.\\\" advertising materials, and other materials related to such\n.\\\" distribution and use acknowledge that the software was developed\n.\\\" by the University of California, Berkeley.  The name of the\n.\\\" University may not be used to endorse or promote products derived\n.\\\" from this software without specific prior written permission.\n.\\\" THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n.\\\" IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n.\\\" WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n.\\\"\n.\\\"\t@(#)adduser.8\t6.6.1 (2.11BSD) 1996/10/23\n.\\\"\n.TH ADDUSER 8 \"October 23, 1996\"\n.UC 4\n.SH NAME\nadduser \\- procedure for adding new users\n.SH DESCRIPTION\nA new user must choose a login name, which must not already appear in\n.IR /etc/passwd or\n.IR /etc/aliases .\nIt must also not begin with the hyphen (``-'') character.\nIt is strongly recommended that it be all lower-case, and not contain\nthe dot (``.'') character, as that tends to confuse mailers.\nAn account can be added by editing a line into the passwd file; this\nmust be done with the password file locked e.g. by using\n.IR chpass (1)\nor\n.IR vipw (8).\n.PP\nA new user is given a group and user id.\nLogin's and user id's should be unique across the system, and often across\na group of systems, since they are used to control file access.\nTypically, users working on similar projects will be put in the same groups.\nAt the University of California, Berkeley, we have groups for system staff,\nfaculty, graduate students, and special groups for large projects.\n.PP\nA skeletal account for a new user \\*(lqernie\\*(rq might look like:\n.IP\nernie::25:30::0:0:Ernie Kovacs,508 Evans Hall,x7925,642-8202:/a/users/ernie:/bin/csh\n.PP\nFor a description of each of these fields, see\n.IR passwd (5).\n.PP\nIt is useful to give new users some help in getting started, supplying\nthem with a few skeletal files such as\n.I \\&.profile\nif they use \\*(lq/bin/sh\\*(rq, or\n.I \\&.cshrc\nand\n.I \\&.login\nif they use \\*(lq/bin/csh\\*(rq.\nThe directory\n\\*(lq/usr/skel\\*(rq contains skeletal definitions of such files.\nNew users should be given copies of these files which, for instance,\nuse\n.IR tset (1)\nautomatically at each login.\n.SH FILES\n.ta 2i\n/etc/master.passwd\tuser database\n.br\n/usr/skel\tskeletal login directory\n.SH SEE ALSO\nchpass(1), finger(1), passwd(1), aliases(5), passwd(5), mkpasswd(8), vipw(8)\n.SH BUGS\nUser information should (and eventually will) be stored elsewhere.\n"
  },
  {
    "path": "share/man/man8/autoconfig.8",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)autoconfig.8\t2.7 (2.11BSD GTE) 1996/5/24\n.\\\"\n.TH AUTOCONFIG 8 \"December 30, 1992\"\n.UC 2\n.SH NAME\nautoconfig \\- configure the running system to the hardware\n.SH SYNOPSIS\n.B \"autoconfig [\\-i ifile] [\\-n nfile] [\\-k kfile] [\\-v] [\\-d] [\\-c]\"\n.SH DESCRIPTION\n.PP\n.I Autoconfig\nis called by\n.IR init (8)\nto configure the currently running system.\nInit checks the exit status of autoconfig to determine if\nthe configuration was successful.\n.I Autoconfig\nreads the device table\n.I /etc/dtab\nfor a list of devices which may be on the system.\nIt first verifies that the kernel has an attach routine\nfor each device (and therefore has a device handler)\nand that the kernel\nhas a probe routine.\nIt then checks each of these devices to see if it is present,\nand if it is,\nattempts to make it interrupt (if possible) to verify that the interrupt\nvector is correct.\nThe interrupt vector is checked to see that it has not previously been used.\nAn interrupt through any of the device's consecutive vectors is sufficient.\n.PP\nDevices which use programmable vectors (MSCP and TMSCP) are permitted\nto have a value of 0 in the dtab vector field.  This special value tells\nautoconfig to call the kernel's get next available vector routine and\nassign that to the device.  For programmable vector devices if the dtab\nvector field is non 0 then the value specified in the dtab file is used.\nIn both cases the driver is called at its xxVec() routine with the vector\nbeing assigned to the device.\n.PP\nIf the address and vector are correct, it then attaches the device\nby passing the address and unit number\nto the kernel's attach routine and setting up the interrupt vector according to\nthe interrupt handlers and priority listed in the device table.\nIf the unit number is given as a '?' in the device table,\nit will be assigned the next available unit number if the device exists.\nIf the device is not present or the vector is incorrect,\nand if the unit number was specified (not a '?'),\nthen the kernel is notified that that unit is not present,\npreventing accesses to a nonexistent device address.\n.PP\nThere are only a few flags which are mostly useful for debugging\nbut for completeness, here they are.\n.TP \"\\w'\\fB\\-k\\fI kfile\\fR  'u\"\n\\fB\\-\\^i\\fI ifile\\fR\nUse\n.I ifile\ninstead of\n.I /etc/dtab\nas the device table.\n.TP\n\\fB\\-\\^n\\fI nfile\\fR\nUse\n.I nfile\ninstead of\n.I /unix\nfor finding the namelist of the currently running kernel.\n.TP\n\\fB\\-\\^k\\fI kfile\\fR\nThe file\n.I kfile\nshould be used instead of\n.I /dev/kmem\nto alter and read kernel memory.\n.TP\n\\fB\\-\\^v\\fR\nVerbose output, indicates reason for rejecting any device in the device\ntable.  Normally only attached devices are reported.\n.TP\n\\fB\\-\\^c\\fR\nReport error messages for devices skipped because of problems with\ntheir interrupt vectors.\n.TP\n\\fB\\-\\^d\\fR\nTurn on debugging mode.  Shows many gory details of autoconfig's internal\nprocessing.\n.SH BUGS\nDevices of the same type must be listed with ascending unit numbers\nor with wildcards.\n.PP\nDisks that could be root devices must have their addresses\nand vectors initialized in the kernel;\nthe kernel uses a root attach entry in the block device switch\nto allow disk drivers to do any probes necessary before autoconfiguration.\n.PP\nMust be run only by\n.IR init (8).\nThere is a flag set in the kernel that autoconfig has already run, running\nautoconfig a second time results in the error:\n.TP\n\"namelist doesn't match running kernel.\"\nAutoconfig attempts to open /dev/kmem for write.  If the kernel is in\nsecurelevel 1 or higher the open of /dev/kmem will fail.\n.SH FILES\n.ta 2i\n/etc/dtab\tdevice table\n.br\n/unix\n.br\n/dev/kmem\n.SH SEE ALSO\nucall(2), \nnlist(3),\ndtab(5)\n"
  },
  {
    "path": "share/man/man8/boot.8",
    "content": ".\\\" Public domain.  May 24, 1996.\n.\\\"\n.\\\"\t@(#)reboot.8\t1.0 (2.11BSD) 1996/5/24\n.\\\"\n.TH BOOT 8 \"May 24, 1996\"\n.UC 2\n.SH NAME\nboot \\- 2.11BSD bootstrap proceedure\n.SH DESCRIPTION\n.PP\nThe 2.11BSD system is started by a two-stage process.  The first is a\nprimary bootstrap (limited to 512 bytes) which is able to read in \nrelatively small stand-alone\nprograms; the second (called\n.IR boot )\nis used to read in the system itself.\n.PP\nThe primary bootstrap must reside in block zero of the\nboot device (the disklabel resides in block one).  It can be read \nin and started by standard ROM cold boot\nroutines or, if necessary, by keying in a small startup routine.  The\nprimary bootstrap is capable of loading \\fBonly\\fP type 0407 executable \nfiles (impure\n(non-shared), non-separate I&D.)\nCopies of the block zero bootstraps are kept in the directory\n.IR /mdec .\n.IR Disklabel (8)\nis normally used to place a copy of the appropriate bootstrap in block zero of\nnew file systems.\n.PP\nThe primary bootstrap loads\n.I boot\nfrom the file system that starts at block 0 of the drive specified to\nthe boot ROM.  Normally the boot device is automatically used as the root\nfilesystem.  This action can be overriden by specifying the \\fB\\-R\\fP command\nto \\fIboot\\fP.\nIf\n.I boot\nis not found the system will hang as the primary boot spins in an endless\nloop trying to find \\fIboot\\fP.\nNo diagnostic message results if the file cannot\nbe found.\n.IP \\(bu\n.BR \"In an emergency\" ,\nthe bootstrap methods described in the paper\n.I \"Installing and Operating 2.11BSD\"\ncan be used to boot from a distribution tape.\n.PP\nThe secondary boot program, called\n.IR boot ,\nactually brings in the system.  When read into location 0 and executed,\n.I boot\nsets up memory management, relocates itself into high memory, and types its\nname and a `:' on the console.  If this is an automatic, unattended reboot,\n.I boot\nwill use a default file specification for the installation, typing the\nfile's name after the prompt.  Otherwise, it reads a file specification\nfrom the console.  Normal line editing characters can be used to make\ncorrections while typing this (see below for file specification format).\nIf only a carriage return is typed, a default name (/unix) will be used.\n.I Boot\nfinds the [specified] file and loads it into memory location zero, sets up\nmemory management as required, and calls the program by executing a `trap'\ninstruction.\n.PP\nFor the system to boot,\n.I /etc/init\nmust exist and be executable; if it is not, the kernel will print a message\nto that effect and loop.  Further, for a single user boot, the files\n.I /bin/sh\nand\n.I /dev/console\nmust also exist and\n.I /bin/sh\nmust be executable (if either of these is missing,\n.I init\nwill attempt multi-user operation).\nFor a multi-user boot the file\n.I /etc/ttys\nmust exist (if missing,\n.I init\nwill attempt single user operation).\n.PP\n.I Init\nruns the\n.IR autoconfig (8)\nprogram to probe for and initialize devices.\n.I Autoconfig\nonly knows to look in \\fI/unix\\fP, thus if an alternate kernel name was\nspecified none of the devices except \\fI/dev/console\\fP and the boot disk\nwill be known.\n.PP\nIf \\fIautoconfig\\fP problems are suspected (or if  you are simply \nvoyeuristic) the \\fBdebug\\fP flag can be turned on by specifying \n\\fB\\-D\\fP to \\fIboot\\fP (see below).\n.PP\nWhen the system is running in single user mode, it starts a single user\nshell on the console which types a `#' prompt.  After doing any file system\nchecks and setting the date\n.RI ( date (1))\na multi-user system can be brought up by typing an EOT (control-d) in\nresponse to the `#' prompt.\n.PP\n.B \"Boot file specification format:\"\nThe file specifications used with\n.I boot\nare of the form:\n.IP\n.I device(ctlr,unit,part)path [-aRrDs]\n.LP\nor\n.IP\n.I \\-bootcommand\n.LP\nwhere\n.TP\n.I device\nis the type of the device to be searched;\n.TP\n.I ctlr\nis the controller number of the disk\n.TP\n.I unit\nis the unit number of the disk or tape;\n.TP\n.I part\nis the partition number of a filesystem on the specified disk\nor the tape file number if the device is a tape.\nThe underlying\ndevice driver \\fBmust\\fP support disklabels and a valid disklabel must be \npresent if \\fIpart\\fP is anything except 0.\n.TP\n.I path\nis the path name of a disk file to be loaded with all mount prefixes\nstripped off\n.RI ( path\nmust be omitted for tape files.)  Tape files are separated by single tape\nmarks.\n.PP\nFlags to \\fIboot\\fP may be specified in either of two places.  At the \n\\fB:\\fP prompt and after the \\fIfile\\fP name.  The options are:\n.TP\n.B \\-a\nAsk for a kernel name.  This is present for symmetry only because in order\nto specify this option you already have to be at the \\fB:\\fP prompt.\n.TP\n.B \\-D\nTurn on the \n.I autoconfig\ndebug flag.\n.TP\n.B \\-R\nforce the kernel to use its compiled in root device rather than adapting\nto the boot device.\n.TP\n.B \\-s\ntell \n.I init\nto enter single user state rather than bringing the system all the way\nup to multi-user mode.\n.B \\-r\nmount the root filesystem read-only.  This is not currently supported by\nthe kernel mostly because pipes are implemented in the filesystem.\n.LP\nCommands (\\fI\\-bootcommand\\fP) to \\fIboot\\fP are:\n.TP 20\n.B \\-bootflags N\nwhere N is a decimal number.\n.TP 20\n.B \\-bootflags flag\nwhere \\fBflag\\fP is from the list above.\n.TP 20\n.B \\-bootdebug N\nwhere N is a decimal number.  This is a general purpose flag word used\nby \\fIboot\\fP and is not passed to the loaded program or kernel.\n.PP\n.I Device\nis one of the following\n.PP\n.nf\n.ne 10\n\txp\tRM02/03/05, RP04/05/06, DIVA, SI Eagle, CDC 9766, Fuji 160\n\trp\tRP03\n\trk\tRK05\n\thk\tRK06/7\n\trl\tRL01/2\n\tsi\tRM05, CDC 9766\n\tra\tRA60/80/81, RX50, RD51/52/53, RC25\n\tht\tTU/TE16\n\ttm\tTU/TE10\n\tts\tTS-11\n.fi\n.PP\nThe stand alone tape drive unit number is specially encoded to specify\nboth unit number and tape density (BPI).  Most tape subsystems either\nautomatically adjust to tape density or have switches on the drives to\nforce the density to a particular setting, but for those which don't the\nfollowing density select mechanisms may be necessary.  The \\fBts\\fP only\noperates at 1600BPI, so there is no special unit density encoding.  The\n\\fBht\\fP will operate at either 800BPI or 1600BPI.  Units 0 through 3\ncorrespond to 800BPI, and 4 through 7 to 1600BPI on drives 0 through 3\nrespectively.  The standard DEC \\fBtm\\fP only supports 800BPI (and hence\ncan't be used with the standard \\*(2B distribution tape), but several\nwidely used \\fBtm\\fP emulators support 1600BPI and even 6250BPI.  Units 0\nthrough 3 correspond to 800BPI, 4 through 7 to 1600BPI, and 8 through 11\nto 6250BPI on drives 0 through 3 respectively.\n.PP\nFor example, to boot a system from unit 0 on an RK07,\ntype \\*(lqhk(0,0)unix\\*(rq to the boot prompt.  The specification\n\\*(lqra(1,0)unix\\*(rq indicates an MSCP disk, unit 1.  The specification\n\\*(lqra(1,0,0)unix\\*(rq indicates an MSCP disk, unit 0 but on controller\n1.\nAnd finally the specification\n\\*(lqts(0,3)\\*(rq would cause the fourth file on a tape threaded on `ts'\ntape drive 0 to be loaded and executed.\n.PP\n.B \"Cold boot loaders:\"\nThe following programs to load and execute the primary bootstrap may be\ninstalled in read-only memories or manually keyed into main memory.  Each\nprogram is position-independent but should be placed well above location 0\nso it will not be overwritten.  Each reads a block from the beginning of a\ndevice into core location zero.  The octal words constituting the program\nare listed on the left.\n.PP\n.nf\n.if n .ta 3 11 15 23 38\n.if t .ta .3i 1i 1.4i 2i 3.5i\n.ne 10\nRK (drive 0):\n\t012700\t\tmov\t$rkda,r0\n\t177412\n\t005040\t\tclr\t\\-(r0)\t/ rkda cleared by start\n\t010040\t\tmov\tr0,\\-(r0)\n\t012740\t\tmov\t$5,\\-(r0)\n\t000005\n\t105710\t1:\ttstb\t(r0)\n\t002376\t\tbge\t1b\n\t005007\t\tclr\tpc\n.PP\n.ne 11\nRP (drive 0)\n\t012700\t\tmov\t$rpmr,r0\n\t176726\n\t005040\t\tclr\t\\-(r0)\n\t005040\t\tclr\t\\-(r0)\n\t005040\t\tclr\t\\-(r0)\n\t010040\t\tmov\tr0,\\-(r0)\n\t012740\t\tmov\t$5,\\-(r0)\n\t000005\n\t105710\t1:\ttstb\t(r0)\n\t002376\t\tbge\t1b\n\t005007\t\tclr\tpc\n.PP\n.ne 7\nTM (drive 0):\n\t012700\t\tmov\t$tmba,r0\n\t172526\n\t010040\t\tmov\tr0,\\-(r0)\n\t012740\t\tmov\t$60003,\\-(r0)\n\t060003\n\t000777\t\tbr\t.\n.DT\n.SH FILES\n.ta \\w'/mdec/xxuboot   'u\n/unix\tsystem code\n.br\n/boot\tsystem bootstrap\n.br\n/etc/init\tsystem process dispatcher\n.br\n/mdec/xxuboot\tsector 0 boot blocks, xx is disk type\n.SH \"SEE ALSO\"\ncrash(8V),\nautoconfig(8),\nreboot(2),\ndisklabel(8),\nfsck(8),\ninit(8)\n"
  },
  {
    "path": "share/man/man8/bugfiler.8",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)bugfiler.8\t6.2.1 (2.11BSD) 1996/10/23\n.\\\"\n.TH BUGFILER 8 \"October 23, 1996\"\n.UC 5\n.SH NAME\nbugfiler \\- file bug reports in folders automatically\n.SH SYNOPSIS\n.B bugfiler\n[ mail directory ]\n.SH DESCRIPTION\n.I Bugfiler\nis a program to automatically intercept bug reports, summarize them and\nstore them in the appropriate sub directories of the mail directory\nspecified on the command line or the (system dependent) default.\nIt is designed to be compatible with the Rand MH mail system.\n.I Bugfiler\nis normally invoked by the mail delivery program through\n.IR aliases (5)\nwith a line such as the following in /etc/aliases.\n.PP\n.DT\n\tbugs:\"|bugfiler /usr/bugs/mail\"\n.PP\nIt reads the message from the standard input or the named file, checks\nthe format and returns mail acknowledging receipt or a message \nindicating the proper format.  Valid reports are then summarized and\nfiled in the appropriate folder; improperly formatted messages\nare filed in a folder named ``errors.''\nProgram maintainers can then log onto the system and\ncheck the summary file for bugs that pertain to them.\nBug reports should be submitted in RFC822 format and\naremust contain the following header lines to be properly indexed:\n.PP\n.DT\n\tDate: <date the report is received>\n.br\n\tFrom: <valid return address>\n.br\n\tSubject: <short summary of the problem>\n.br\n\tIndex: <source directory>/<source file> <version> [Fix]\n.PP\nIn addition, the body of the message must contain a line which\nbegins with ``Description:'' followed by zero or more lines describing the\nproblem in detail and a line beginning with ``Repeat-By:'' followed by zero or\nmore lines describing how to repeat the problem.\nIf the keyword `Fix' is specified in the `Index' line, then there must\nalso be a line beginning with ``Fix:'' followed by a diff of the old and new\nsource files or a description of what was done to fix the problem.\n.PP\nThe `Index' line is the key to the filing mechanism. The source directory\nname must match one of the folder names in the mail directory.\nThe message is then filed in this folder\nand a line appended to the summary file in the following format:\n.PP\n.DT\n\t<folder name>/<message number>\t<Index info>\n.br\n\t\t\t\t\t\t<Subject info>\n.PP\nThe bug report may also be redistributed according to the index.\nIf the file\n.IR maildir /.redist\nexists, it is examined for a line beginning with the index name\nfollowed with a tab.\nThe remainder of this line contains a comma-separated list of mail addresses\nwhich should receive copies of bugs with this index.\nThe list may be continued onto multiple lines by ending each but the last\nwith a backslash (`\\e').\n.SH FILES\n.ta 2.5i\n/usr/sbin/sendmail\tmail delivery program\n.br\n/usr/libexec/unixtomh\tconverts unix mail format to mh format\n.br\nmaildir/.ack\tthe message sent in acknowledgement\n.br\nmaildir/.format\tthe message sent when format errors are detected\n.br\nmaildir/.redist\tthe redistribution list\n.br\nmaildir/summary\tthe summary file\n.br\nmaildir/Bf??????\ttemporary copy of the input message\n.br\nmaildir/Rp??????\ttemporary file for the reply message.\n.SH \"SEE ALSO\"\nmh(1),\nnewaliases(1),\naliases(5)\n.SH BUGS\n.PP\nSince mail can be forwarded in a number of different ways,\n.I bugfiler\ndoes not recognize forwarded mail and will reply/complain to the\nforwarder instead of the original sender unless there is a `Reply-To'\nfield in the header.\n.PP\nDuplicate messages should be discarded or recognized and put somewhere\nelse.\n"
  },
  {
    "path": "share/man/man8/crash.8",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)crash.8v\t6.2 (Berkeley) 5/20/86\n.\\\"\n.TH CRASH 8V \"July 11, 1987\"\n.UC 2\n.SH NAME\ncrash \\- what happens when the system crashes\n.SH DESCRIPTION\nThis section explains what happens when the system crashes\nand (very briefly) how to analyze crash dumps.\n.PP\nWhen the system crashes voluntarily it prints a message of the form\n.IP\npanic: why i gave up the ghost\n.LP\non the console, takes a dump on a mass storage peripheral,\nand then invokes an automatic reboot procedure as\ndescribed in\n.IR reboot (8).\nUnless some unexpected inconsistency is encountered in the state\nof the file systems due to hardware or software failure, the system\nwill then resume multi-user operations.\nIf the automatic file system\ncheck fails, the file systems should be checked and repaired with\n.IR fsck (8)\nbefore continuing.\n.PP\nThe system has a large number of internal consistency checks; if one\nof these fails, then it will panic with a very short message indicating\nwhich one failed.\nIn many instances, this will be the name of the routine which detected\nthe error, or a two-word description of the inconsistency.\nA full understanding of most panic messages requires perusal of the\nsource code for the system.\n.PP\nThe most common cause of system failures is hardware failure, which\ncan reflect itself in different ways.  Here are the messages which\nare most likely, with some hints as to causes.\nLeft unstated in all cases is the possibility that hardware or software\nerror produced the message in some unexpected way.\n.TP\n.B iinit\nThis cryptic panic message results from a failure to mount the root filesystem\nduring the bootstrap process.\nEither the root filesystem has been corrupted,\nor the system is attempting to use the wrong device as root filesystem.\nUsually, an alternate copy of the system binary or an alternate root\nfilesystem can be used to bring up the system to investigate.\n.TP\n.B Can't exec /etc/init\nThis is not a panic message, as reboots are likely to be futile.\nLate in the bootstrap procedure, the system was unable to locate\nand execute the initialization process,\n.IR init (8).\nThe root filesystem is incorrect or has been corrupted, or the mode\nor type of /etc/init forbids execution.\n.TP\n.B hard IO err in swap\nThe system encountered an error trying to write to the swap device\nor an error in reading critical information from a disk drive.\nThe offending disk should be fixed if it is broken or unreliable.\n.TP\n.B timeout table overflow\n.ns\nThis really shouldn't be a panic, but until the data structure\ninvolved is made to be extensible, running out of entries causes a crash.\nIf this happens, make the timeout table bigger.\n(NCALL in param.c)\n.TP\n.B trap type %o\nAn unexpected trap has occurred within the system; the trap types are:\n.PP\n.nf\n0\tbus error\n1\tillegal instruction trap\n2\tBPT/trace trap\n3\tIOT\n4\tpower fail trap (if autoreboot fails)\n5\tEMT\n6\trecursive system call (TRAP instruction)\n7\tprogrammed interrupt request\n11\tprotection fault (segmentation violation)\n12\tparity trap\n.fi\n.PP\nIn some of these cases it is possible for octal 020 to be added into the\ntrap type; this indicates that the processor was in user mode when the\ntrap occurred.\n.PP\nIn addition to the trap type, the system will have\nprinted out three (or four) other numbers:\n.IR ka6 ,\nwhich is the contents of the segmentation\nregister for the area in which the system's stack is kept;\n.IR aps ,\nwhich is the location where the hardware stored\nthe program status word during the trap;\n.IR pc ,\nwhich was the system's program counter when\nit faulted (already incremented to the next word);\n.IR __ovno ,\nthe overlay number of the currently loaded kernel overlay when the trap\noccurred.\n.PP\nThe favorite trap types in system crashes are trap types 0 and 11,\nindicating\na wild reference.  The code is the referenced address, and the pc at the\ntime of the fault is printed.  These problems tend to be easy to track\ndown if they are kernel bugs since the processor stops cold, but random\nflakiness seems to cause this sometimes.\nThe debugger can be used to locate the instruction and subroutine\ncorresponding to the PC value.\nIf that is insufficient to suggest the nature of the problem,\nmore detailed examination of the system status at the time of the trap\nusually can produce an explanation.\n.TP\n.B init died\nThe system initialization process has exited.  This is bad news, as no new\nusers will then be able to log in.  Rebooting is the only fix, so the\nsystem just does it right away.\n.TP\n.B out of mbufs: map full\nThe network has exhausted its private page map for network buffers.\nThis usually indicates that buffers are being lost, and rather than\nallow the system to slowly degrade, it reboots immediately.\nThe map may be made larger if necessary.\n.TP\nout of swap space\nThis really shouldn't be panics but there's no other\nsatisfactory solution.\nThe size of the swap area must be increased.\nThe system attempts to avoid running out of swap by refusing to\nstart new processes when short of swap space (resulting in\n``No more proceses'' messages from the shell).\n.TP\n&remap_area > SEG5\n.ns\n.TP\n_end > SEG5\nThe kernel detected at boot time that an unacceptable portion of\nits data space extended into the region controlled by KDSA5.\nIn the case of the first message, the size of the kernel's data\nsegment (excluding the file, proc, and text tables) must be\ndecreased.  In the latter case, there are two possibilities:\nif &remap_area is not greater than 0120000, the kernel must be\nrecompiled without defining the option NOKA5.  Otherwise, as\nabove, the size of the kernel's data segment must be decreased.\n.PP\nThat completes the list of panic types you are likely to see.\nThere are many other panic messages which are less likely to occur;\nmost of them detect logical inconsistencies within the kernel\nand thus ``cannot happen'' unless some part of the kernel has been modified.\n.PP\nIf the system stops or hangs without a panic, it is possible to stop\nit and take a dump of memory before rebooting.\nA panic can be forced from the console,\nwhich will allow a dump, automatic reboot and file system check.\nThis is accomplished by halting the CPU,\nputting the processor in kernel mode,\nloading the PC with 40,\nand continuing without a reset (use continue, not start).\nTo put the processor in kernel mode, make sure the two high\nbits in the processor status word are zero.\n(you'll need to consult the procesor handbook describing your\nprocessor to determine how to access the PC and PS ...)\nThe message ``panic:  forced from console'' should print, and the\nautomatic reboot will start.\n.PP\nIf this fails\na dump of memory can be made on magtape:\nmount a tape (with write ring!), halt the CPU, load address 044,\nand perform a start (which does a reset).\nThis should write a copy of all of core\non the tape with an EOF mark.\nCaution:\nAny error is taken to mean the end of core has been reached.\nThis means that you must be sure the ring is in,\nthe tape is ready, and the tape is clean and new.\nIf the dump fails, you can try again,\nbut some of the registers will be lost.\nAfter this completes, halt again and reboot.\n.PP\nAfter rebooting, or after an automatic file system check fails,\ncheck and fix the file systems with\n.IR fsck .\nIf the system will not reboot, a runnable system must be obtained\nfrom a backup medium after verifying that the hardware is functioning normally.\nA damaged root file system should be patched while running with an alternate\nroot if possible.\n.PP\nWhen the system crashes if crash dumping was enabled\nit writes (or at least attempts to write)\nan image of memory into the back end of the dump device,\nusually the same as the primary swap\narea.  After the system is rebooted, the program\n.IR savecore (8)\nruns and preserves a copy of this core image and the current\nsystem in a specified directory for later perusal.  See\n.IR savecore (8)\nfor details.\nA magtape dump can be read onto disk with\n.IR dd (1).\n.PP\nTo analyze a dump you should begin by running\n.IR adb (1)\nwith the \n.B \\-k\nflag on the system load image and core dump.\nIf the core image is the result of a panic,\nthe panic message is printed.\nNormally the command\n``$c'' or ``$C''\nwill provide a stack trace from the point of\nthe crash and this will provide a clue as to\nwhat went wrong.\n.IR ps (1)\nand\n.IR pstat (8) can also be used\nto print the process table at the time of the crash via:\n.I \"ps\\ \\-alxk\"\nand\n.IR \"pstat\\ \\-p\" .\nIf the mapping or the stack frame are incorrect, the following\nmagic locations may be examined in an attempt to find out what went wrong.\nThe registers R0, R1, R2, R3, R4, R5, SP, and KDSA6 (or KISA6 for machines\nwithout separate instruction and data)\nare saved at location 04.\nIf the core dump was taken on disk, these values also appear\nat 0300.\nThe value of KDSA6 (KISA6) multiplied by 0100 (8) gives the address\nof the user structure and kernel stack for the running process.\nRelabel these addresses 0140000 through 0142000.\nR5 is C's frame or display pointer.\nStored at (R5) is the old R5 pointing to the previous\nstack frame.\nAt (R5)+2\nis the saved PC of the calling procedure.\nTrace\nthis calling chain\nto an R5 value of 0141756 (0141754 for overlaid kernels), which\nis where the user's R5 is stored.\nIf the chain is broken,\nlook for a plausible\nR5, PC pair and continue from there.\nIn most cases this procedure will give\nan idea of what is wrong.\n.PP\nA more complete discussion\nof system debugging is impossible here.\nSee, however,\n``Using ADB to Debug the UNIX Kernel''.\n.SH \"SEE ALSO\"\nadb(1), ps(1), pstat(1), boot(8), fsck(8), reboot(8), savecore(8)\n.br\n.I \"PDP-11 Processor Handbook\"\nfor various processors for more information about PDP-11 memory management\nand general architecture.\n.br\n.I \"Using ADB to Debug the UNIX Kernel\"\n"
  },
  {
    "path": "share/man/man8/drtest.8",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)drtest.8\t6.2 (Berkeley) 5/19/86\n.\\\"\n.TH DRTEST 8 \"May 19, 1986\"\n.UC 5\n.SH NAME\ndrtest \\- standalone disk test program\n.SH DESCRIPTION\n.PP\n.I Drtest\nis a standalone program used to read a disk \ntrack by track. \nIt was primarily intended as a test program \nfor new standalone drivers, but has shown\nuseful in other contexts as well, such as \nverifying disks and running speed\ntests. For example, when a disk has been formatted\n(by format(8)), you can check that\nhard errors has been taken care of by running \n.IR drtest .\nNo hard errors should be found, but in many cases \nquite a few soft ECC errors will be reported.\n.PP\nWhile\n.I drtest\nis running, the cylinder number is printed on\nthe console for every 10th cylinder read.\n.SH EXAMPLE\nA sample run of \n.I drtest\nis shown below.  \nIn this example (using a 750), \n.I drtest\nis loaded from the root file system;\nusually it\nwill be loaded from the machine's\nconsole storage device.  Boldface means user input.\nAs usual, ``#'' and ``@'' may be used to edit input.\n.nf\n.in +5\n.sp 1\n>>>\\fBB/3\\fR\n%%\nloading hk(0,0)boot \nBoot\n: \\fBhk(0,0)drtest\\fR\nTest program for stand-alone up and hp driver\n.sp 1\nDebugging level (1=bse, 2=ecc, 3=bse+ecc)?\nEnter disk name [type(adapter,unit), e.g. hp(1,3)]? \\fBhp(0,0)\\fR\nDevice data: #cylinders=1024, #tracks=16, #sectors=32\nTesting hp(0,0), chunk size is 16384 bytes.\n\\fI(chunk size is the number of bytes read per disk access)\\fP\nStart ...Make sure hp(0,0) is online\n ...\n\\fI(errors are reported as they occur)\\fP\n ...\n\\fI(...program restarts to allow checking other disks)\\fP\n\\fI(...to abort halt machine with ^P)\\fP\n.in -5\n.fi\n.sp 1\n.SH DIAGNOSTICS\nThe diagnostics are intended to be self explanatory. Note, however, that \nthe device number\nin the diagnostic messages is identified as  \\fItypeX\\fR instead of \n\\fItype(a,u)\\fR where \\fIX\\fR = a*8+u, e.g., hp(1,3) becomes hp11.\n.SH SEE ALSO\nformat(8V), bad144(8)\n.SH AUTHOR\nHelge Skrivervik\n"
  },
  {
    "path": "share/man/man8/dump.8",
    "content": ".\\\"\n.\\\"\t@(#)dump.8\t1.2 (2.11BSD GTE) 1996/11/17\n.\\\"\n.TH DUMP 8 \"November 17, 1996\"\n.UC 4\n.SH NAME\ndump \\- incremental file system dump\n.SH SYNOPSIS\n.B dump\n[0123456789BchfusTdWwn [\\fIargument\\fP\\& ...]] [filesystem]\n.SH DESCRIPTION\n.I Dump\ncopies to magnetic tape all files\nchanged after a certain date\nin the\n.I filesystem.\n.PP\nThe following options are supported by dump:\n.TP 5\n.B  0\\-9\nThis number is the `dump level'.\nAll files modified since the last date stored\nin the file\n.I /etc/dumpdates\nfor the same filesystem at lesser levels\nwill be dumped.\nIf no date is determined by the level,\nthe beginning of time is assumed;\nthus the option\n.B 0\ncauses the entire filesystem to be dumped.\n.TP 5\n.B B records\nThe number of dump records per volume.  This option overrides the\ncalculation of tape size based on length and density.\n.TP 5\n.B c\nThis option requires no further options.  Used to specify that the\ntape is a \\fIcartridge\\fP drive rather than a 9\\-track.\n.TP 5\n.B h level\nHonor the user 'nodump' flags only for dumps at or above the given\n\\fBlevel\\fP.  The default honor level is 1, so that incremental backups\nomit such files but full backups retain them.\n.TP 5\n.B f\nPlace the dump on the next \n.I argument \nfile\ninstead of the tape.  If '-' is given then standard out (stdout) is written\nto.\n.TP 5\n.B u\nIf the dump completes successfully,\nwrite the date of the beginning of the dump on\nfile\n.I /etc/dumpdates.\nThis file records a separate date for\neach filesystem and each dump level.\nThe format of\n.I /etc/dumpdates\nis readable by people, consisting of one\nfree format record per line:\nfilesystem name, increment level\nand\n.I ctime(3)\nformat dump date.  \n.I /etc/dumpdates\nmay be edited to change any of the fields,\nif necessary.\nNote that\n.I /etc/dumpdates\nis in a format different from that which previous versions of\n.I dump\nmaintained in\n.I /etc/ddate,\nalthough the information content is identical.\n.TP 5\n.B s\nThe size of the dump tape is specified in feet.\nThe number of feet is taken from the next\n.I argument.\nWhen the specified size is reached,\n.I dump\nwill wait for reels to be changed.\nThe default tape size is 2300 feet.\n.TP 5\n.B d\nThe density of the tape, expressed in BPI,\nis taken from the next\n.I argument.\nThis is used in calculating the amount of tape\nused per reel. The default is 1600.\n.TP 5\n.B T date\nUse the specified date as the starting time for the dump instead of\nthe time determined from looking in \\fB/etc/dumpdates\\fP.  The format\nof \\fBdate\\fP is the same as that of \\fIctime(3)\\fP.  This option is\nuseful for automated dump scripts that wish to dump over a specific \nperiod of time.  The \\fBT\\fP option is mutually exclusive with the \n\\fBu\\fP option.\n.TP 5\n.B W\n.I Dump\ntells the operator what file systems need to be dumped.\nThis information is gleaned from the files\n.I /etc/dumpdates\nand\n.I /etc/fstab.\nThe\n.B W\noption causes\n.I dump\nto print out, for each file system in\n.I /etc/dumpdates\nthe most recent dump date and level,\nand highlights those file systems that should be dumped.\nIf the \n.B W\noption is set, all other options are ignored, and\n.I dump\nexits immediately.\n.TP 5\n.B w\nIs like W, but prints only those filesystems which need to be dumped.\n.TP 5\n.B n\nWhenever\n.I dump\nrequires operator attention,\nnotify by means similar to a\n.I wall(1)\nall of the operators in the group \\*(lqoperator\\*(rq.\n.PP\nIf no arguments are given,\nthe\n.I key\nis assumed to be\n.B 9u\nand a default file system is dumped\nto the default tape.\n.PP\n.I Dump\nrequires operator intervention on these conditions:\nend of tape,\nend of dump,\ntape write error,\ntape open error or\ndisk read error (if there are more than a threshold of 32).\nIn addition to alerting all operators implied by the\n.B n\nkey,\n.I dump\ninteracts with the operator on \n.I dump's\ncontrol terminal at times when\n.I dump\ncan no longer proceed,\nor if something is grossly wrong.\nAll questions\n.I dump\nposes\n.B must\nbe answered by typing \\*(lqyes\\*(rq or \\*(lqno\\*(rq,\nappropriately.\n.PP\nSince making a dump involves a lot of time and effort for full dumps,\n.I dump\ncheckpoints itself at the start of each tape volume.\nIf writing that volume fails for some reason,\n.I dump\nwill,\nwith operator permission,\nrestart itself from the checkpoint\nafter the old tape has been rewound and removed,\nand a new tape has been mounted.\n.PP\n.I Dump\ntells the operator what is going on at periodic intervals,\nincluding usually low estimates of the number of blocks to write,\nthe number of tapes it will take, the time to completion, and\nthe time to the tape change.\nThe output is verbose,\nso that others know that the terminal\ncontrolling\n.I dump\nis busy,\nand will be for some time.\n.PP\nNow a short suggestion on how to\nperform dumps.\nStart with a full level 0 dump\n.PP\n\tdump 0un\n.PP\nNext, dumps of active file \nsystems are taken on a daily basis,\nusing a modified Tower of Hanoi algorithm,\nwith this sequence of dump levels:\n.ce 1\n3 2 5 4 7 6 9 8 9 9 ...\nFor the daily dumps, a set of 10 tapes per dumped file system\nis used on a cyclical basis.\nEach week, a level 1 dump is taken, and\nthe daily Hanoi sequence repeats with 3.\nFor weekly dumps, a set of 5 tapes per dumped file system is\nused, also on a cyclical basis.\nEach month, a level 0 dump is taken\non a set of fresh tapes that is saved forever.\n.SH FILES\n.nf\n.ta \\w'/etc/dumpdates\\ \\ 'u\n/dev/rxp0a\tdefault filesystem to dump from\n/dev/rmt0\tdefault tape unit to dump to\n/etc/ddate\told format dump date record (obsolete after \\fB\\-J\\fR option)\n/etc/dumpdates\tnew format dump date record \n/etc/fstab\tDump table: file systems and frequency\n/etc/group\tto find group \\fIoperator\\fP\n.fi\n.DT\n.br\n.SH \"SEE ALSO\"\nrestor(8), rdump(8), dump(5), fstab(5), dumpdir(8)\n.SH DIAGNOSTICS\nMany, and verbose.\n.SH BUGS\n.PP\nSizes are based on 1600 BPI blocked tape;\nthe raw magtape device has to be used to approach these densities.\nFewer than 32 read errors on the filesystem are ignored.\nEach reel requires a new process, so parent processes for\nreels already written just hang around until the entire tape\nis written.\n.PP\nIt would be nice if\n.I dump\nknew about the dump sequence,\nkept track of the tapes scribbled on,\ntold the operator which tape to mount when,\nand provided more assistance\nfor the operator running\n.I restor.\n"
  },
  {
    "path": "share/man/man8/dumpdir.8",
    "content": ".TH DUMPDIR 8 \"September 8, 1987\"\n.UC\n.SH NAME\ndumpdir, 512dumpdir \\- print the names of files on a dump tape\n.SH SYNOPSIS\n.I dumpdir\n[\n.B f\nfilename ]\n.br\n.I 512dumpdir\n[\n.B f\nfilename ]\n.SH DESCRIPTION\n.I Dumpdir\nis used to read magtapes dumped with the\n.I dump\ncommand and list the names and inode numbers\nof all the files and directories on the tape.\n.PP\nThe\n.B f\noption causes\n.I filename\nas the name of the tape instead\nof the default.\n.PP\n.I 512dumpdir\nis a version of\n.I dumpdir\nthat can read tapes written from 512-byte block file systems.\n.SH FILES\n.ta 2i\n/dev/rmt1\tdefault file name\n.br\nrst*\ttemporary files\n.SH \"SEE ALSO\"\ndump(8), restor(8)\n.SH DIAGNOSTICS\nIf the dump extends over more than one tape,\nit may ask you to change tapes.\nReply with a newline when the next tape has been mounted.\n.SH BUGS\nThere is redundant information on the tape\nthat could be used in case of tape reading problems.\nUnfortunately,\n.IR dumpdir \" and \" 512dumpdir\ndon't use it.\n"
  },
  {
    "path": "share/man/man8/format.8",
    "content": ".\\\" Copyright (c) 1980,1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)format.8v\t6.4 (Berkeley) 5/22/86\n.\\\"\n.TH FORMAT 8V \"May 22, 1986\"\n.UC 4\n.SH NAME\nformat \\- how to format disk packs\n.SH DESCRIPTION\n.PP\nThere are two ways to format disk packs.  The simplest is to\nuse the\n.I format\nprogram.  The alternative is to use the DEC standard formatting\nsoftware which operates under the DEC diagnostic supervisor. \nThis manual page describes the operation of\n.IR format ,\nthen concludes with some remarks about using the DEC formatter.\n.PP\n.I Format\nis a standalone program used to\nformat and check disks prior to constructing\nfile systems.\nIn addition to the formatting\noperation,\n.I format\nrecords any bad sectors encountered\naccording to DEC standard 144. \nFormatting is performed one track at a\ntime by writing the appropriate\nheaders and a test pattern and then checking\nthe sector by reading and verifying the pattern, using\nthe controller's ECC for error detection.\nA sector is marked bad if an unrecoverable media\nerror is detected, or if a correctable\nECC error too many bits in length\nis detected (such errors are indicated as\n``ECC'' in the summary printed upon\ncompleting the format operation).\nAfter the entire disk\nhas been formatted and checked,\nthe total number of errors are reported,\nany bad sectors and skip sectors are marked,\nand a bad sector forwarding table\nis written to the disk in the first five\neven numbered sectors of the last track.\nIt is also possible to reformat sections of the disk\nin units of tracks.\n.I Format \nmay be used on any UNIBUS or MASSBUS drive\nsupported by the \\fIup\\fP and \\fIhp\\fP device\ndrivers which uses 4-byte headers (everything except RP's).\n.PP\nThe test pattern used during the media check\nmay be selected from one of: 0xf00f (RH750 worst case),\n0xec6d (media worst case), and 0xa5a5 (alternating\n1's and 0's).\nNormally the media worst case pattern is used.\n.PP\n.I Format\nalso has an option to perform an extended \\*(lqsevere burn-in,\\*(rq\nwhich makes a number of passes using different patterns.\nThe number of passes can be selected at run time,\nup to a maximum of 48,\nwith provision for additional passes or termination\nafter the preselected number of passes.\nThis test runs for many hours, depending on the disk and processor.\n.PP\nEach time\n.I format\nis run to format an entire disk,\na completely new bad sector table is generated\nbased on errors encountered while formatting.\nThe device driver, however, will always attempt to\nread any existing bad sector table when the device is\nfirst opened.\nThus, if a disk pack has never previously been formatted,\nor has been formatted with different sectoring,\nfive error messages will be printed when the driver attempts\nto read the bad sector table; these diagnostics should be ignored.\n.PP\nFormatting a 400 megabyte disk on a MASSBUS disk controller\nusually takes about 20 minutes.\nFormatting on a UNIBUS disk controller takes significantly\nlonger.\nFor every hundredth cylinder formatted\n.I format\nprints a message indicating the current cylinder being formatted.\n(This message is just to reassure people that nothing is\nis amiss.)\n.PP\n.I Format\nuses the standard notation of the standalone I/O library\nin identifying a drive to be formatted.  A drive is\nspecified as\n.IR zz ( x , y ),\nwhere \n.I zz\nrefers to the controller type (either\n.I hp\nor\n.IR up ),\n.I x\nis the unit number of the drive;\n8 times the UNIBUS or MASSBUS\nadaptor number plus the MASSBUS drive number or UNIBUS\ndrive unit number; and\n.I y\nis the file system partition\non drive\n.I x\n(this should always be 0). \nFor example, ``hp(1,0)'' indicates that drive\n1 on MASSBUS adaptor 0 should be formatted; while\n``up(10,0)'' indicates that UNIBUS drive 2 on UNIBUS adaptor 1\nshould be formatted.\n.PP\nBefore each formatting attempt, \n.I format\nprompts the user in case debugging should be enabled\nin the appropriate device driver.  A carriage return\ndisables debugging information.\n.PP\n.I Format\nshould be used prior to building file systems (with \n.IR newfs (8))\nto insure that all sectors with uncorrectable media errors\nare remapped.  If a drive develops uncorrectable\ndefects after formatting, either\n.IR bad144 (8)\nor\n.IR badsect (8)\nshould be able to avoid the bad sectors.\n.SH EXAMPLE\nA sample run of \n.I format\nis shown below.  \nIn this example (using a VAX-11/780), \n.I format\nis loaded from the console floppy;\non an 11/750\n.I format\nwill be loaded from the root file system with\n.IR boot (8)\nfollowing a \\*(lqB/3\\*(rq command.\nBoldface means user input.\nAs usual, ``#'' and ``@'' may be used to edit input.\n.nf\n.in +0.5i\n.ta  1i\n.sp 1\n>>>\\fBL FORMAT\\fP\n\tLOAD DONE, 00004400 BYTES LOADED\n>>>\\fBS 2\\fP\nDisk format/check utility\n.sp\nEnable debugging (0=none, 1=bse, 2=ecc, 3=bse+ecc)? \\fB0\\fP\nDevice to format? \\fBhp(8,0)\\fP\n(\\fIerror messages may occur as old bad sector table is read\\fP)\nFormatting drive hp0 on adaptor 1: verify (yes/no)? \\fByes\\fP\nDevice data: #cylinders=842, #tracks=20, #sectors=48\nStarting cylinder (0):\nStarting track (0):\nEnding cylinder (841):\nEnding track (19):\nAvailable test patterns are:\n.in +1.0i\n1 - (f00f) RH750 worst case\n2 - (ec6d) media worst case\n3 - (a5a5) alternating 1's and 0's\n4 - (ffff) Severe burnin (up to 48 passes)\n.in -1.0i\nPattern (one of the above, other to restart)? \\fB2\\fP\nMaximum number of bit errors to allow for soft ECC (3):\nStart formatting...make sure the drive is online\n ...\n(\\fIsoft ecc's and other errors are reported as they occur\\fP)\n ...\n(\\fIif 4 write check errors were found, the program terminates like this...\\fP)\n ...\nErrors:\nBad sector: 0\nWrite check: 4\nHard ECC: 0\nOther hard: 0\nMarked bad: 0\nSkipped: 0\nTotal of 4 hard errors revectored.\nWriting bad sector table at block 808272\t\n(\\fI808272 is the block # of the first block in the bad sector table\\fP)\nDone\n(\\fI...program restarts to allow formatting other disks\\fP)\n(\\fI...to abort halt machine with ^P\\fP)\n.fi\n.sp 1\n.SH DIAGNOSTICS\nThe diagnostics are intended to be self explanatory.\n.SH \"USING DEC SOFTWARE TO FORMAT\"\n.PP\n.B \"Warning:  These instructions are for people with 11/780 CPU's.\"\nThe steps needed for 11/750 or 11/730 cpu's are similar, but not\ncovered in detail here.\n.I\n.PP\nThe formatting procedures are different for each type of disk.  Listed\nhere are the formatting procedures for RK07's, RP0X, and RM0X \ndisks.\n.PP\nYou should shut down UNIX and halt the machine to do any disk formatting.\nMake certain you put in the pack you want formatted.  It is also a good idea\nto spin down or write protect the disks you don't want to format, just in case.\n.PP\n.B \"Formatting an RK07.\"\nLoad the console floppy labeled, \"RX11 VAX DSK LD DEV #1\" in\nthe console disk drive, and type the following commands:\n.RS\n.nf\n>>>BOOT\nDIAGNOSTIC SUPERVISOR.  ZZ-ESSAA-X5.0-119  23-JAN-1980 12:44:40.03\nDS>ATTACH DW780 SBI DW0 3 5\nDS>ATTACH RK611 DMA\nDS>ATTACH RK07 DW0 DMA0\nDS>SELECT DMA0\nDS>LOAD EVRAC\nDS>START/SEC:PACKINIT\n.fi\n.RE\n.PP\n.B \"Formatting an RP0X.\"\nFollow the above procedures except that the\nATTACH and SELECT lines should read:\n.RS\n.nf\nDS>ATTACH RH780 SBI RH0 8 5\nDS>ATTACH RP0X RH0 DBA0\t\t(RP0X is, e.g. RP06)\nDS>SELECT DBA0\n.fi\n.RE\n.PP\nThis is for drive 0 on mba0; use 9 instead of 8 for mba1, etc.\n.PP\n.B \"Formatting an RM0X.\"\nFollow the above procedures except that the\nATTACH and SELECT lines should read:\n.RS\n.nf\nDS>ATTACH RH780 SBI RH0 8 5\nDS>ATTACH RM0X RH0 DRA0\nDS>SELECT DRA0\n.fi\n.RE\n.PP\nDon't forget to put your UNIX console floppy back\nin the floppy disk drive.\n.SH SEE ALSO\nbad144(8),\nbadsect(8),\nnewfs(8)\n.SH BUGS\nAn equivalent facility should be available which operates under\na running UNIX system. \n.PP\nIt should be possible to reformat or verify part or all of a disk,\nthen update the existing bad sector table.\n"
  },
  {
    "path": "share/man/man8/fsck.8",
    "content": ".de us\n\\\\$1\\l'|0\\(ul'\n..\n.TH FSCK 8 \"November 18, 1996\"\n.UC\n.SH NAME\nfsck \\- file system consistency check and interactive repair\n.SH SYNOPSIS\n.B fsck\n.BR \\-p \"[ # ]\"\n[\nfilesystem ...\n]\n.br\n.B fsck\n[\n.B \\-y\n] [\n.B \\-n\n] [\n.BR \\-s X\n] [\n.BR \\-S X\n] [\n.B \\-t\nfilename\n] [\nfilesystem \n] ...\n.SH DESCRIPTION\nThe first form of\n.I fsck\npreens a standard set of file systems or the specified file systems.\nIt is normally used in the script\n.I /etc/rc\nduring automatic reboot.\nIn this case\n.I fsck\nreads the table\n.I /etc/fstab\nto determine which file systems to check.\nIt uses the information there to inspect groups of disks in parallel taking\nmaximum advantage of i/o overlap to check the file systems\nas quickly as possible.\nNormally, the root file system will be checked on pass 1, other\n``root'' (``a'' partition) file systems on pass 2, other\nsmall file systems on separate passes (e.g. the ``d'' file systems\non pass 3 and the ``e'' file systems on pass 4), and finally\nthe large user file systems on the last pass, e.g. pass 5.\nOnly one file system from each disk should be checked in each pass.\nA pass number of 0 in fstab causes a disk to not be checked; similarly\npartitions which are not shown as to be mounted ``rw'' or ``ro''\nare not checked.\nA number or range of numbers may be given after the\n.B \\-p\nto start or end the check at a specified pass number.\nA single number specifies the starting pass (e.g. \\-p2 or \\-p2\\-);\na range specifies the starting and endig passes (\\-p2\\-4).\nA missing start means to start with pass 1 (\\-p\\-2).\nThese can be used to stop fsck to mount a temporary file system\nbefore continuing the check on larger file systems requiring scratch files.\n.PP\nThe system normally takes care that only a restricted class of innocuous\ninconsistencies can happen unless hardware or software failures intervene.\nThese are limited to the following:\n.IP\nUnreferenced inodes\n.ns\n.IP\nLink counts in inodes too large\n.ns\n.IP\nMissing blocks in the free list\n.ns\n.IP\nBlocks in the free list also in files\n.ns\n.IP\nCounts in the superblock wrong\n.ns\n.IP\nAllocated inodes in the free inode list\n.PP\nThese are the only inconsistencies which\n.I fsck\nwith the\n.B \\-p\noption will correct; if it encounters other inconsistencies, it exits\nwith an abnormal return status and an automatic reboot will then fail.\nFor each corrected inconsistency one or more lines will be printed\nidentifying the file system on which the correction will take place,\nand the nature of the correction.  After successfully correcting a file\nsystem,\n.I fsck\nwill print the number of files on that file system and the number of\nused and free blocks.\n.B Warning:\nkernel changes are required to limit the types of inconsistencies,\nand\n.B \"fsck \\-p\"\nmakes assumptions about the kernel's actions in repairing these.\nVmunix, PDP-11 2.9BSD with the UCB_FSFIX option\nand PDP-11 2.10BSD Unix kernels have the\nappropriate modifications;\nthe\n.B \\-p\noption should not be used on other systems.\n.PP\nWithout the\n.B \\-p\noption,\n.I fsck\naudits and interactively repairs inconsistent conditions for file systems. \nIf the file system is inconsistent the operator is prompted for concurrence\nbefore each correction is attempted.\nIt should be noted that a number of the corrective actions which are not\nfixable under the\n.B \\-p\noption will result in some loss\nof data.\nThe amount and severity of data lost may be determined from the diagnostic\noutput.\nThe default action for each consistency correction\nis to wait for the operator to respond \\fByes\\fP or \\fBno\\fP.\nIf the operator does not have write permission \n.I fsck\nwill default to a \n.BR \"\\-n \" action.\n.PP\n.I Fsck\nhas more consistency checks than\nits predecessors\n.IR \"check, dcheck, fcheck, \" \"and\" \" icheck\"\ncombined.\n.PP\nThe following flags are interpreted by\n.I fsck.\n.TP 6\n.B  \\-\\^y\nAssume a yes response to all questions asked by \n.I fsck;\nthis should be used with great caution as this is a free license\nto continue after essentially unlimited trouble has been encountered.\n.TP 6\n.B  \\-\\^n\nAssume a no response to all questions asked by \n.I fsck;\ndo not open the file system for writing.\n.TP 6\n.BR \\-\\^s \\fIX\nIgnore the actual free list and (unconditionally) reconstruct a new\none by rewriting the superblock of the file system.  \nThe file system should be unmounted while this is done; if this\nis not possible, care should be taken that the system is quiescent\nand that it is rebooted immediately afterwards.\nThis precaution is necessary so that the old, bad, in-core copy\nof the superblock will not continue to be used, or written on the file system.\n.IP\nThe\n.BR \\-s \\fIX\noption allows for creating an optimal free list organization.\nThe following forms of\n.I X\nare supported for the following devices:\n.sp\n.nf\n\t\\-s3 (RP03)\n\t\\-s4 (RP04, RP05, RP06)\n\t\\-sBlocks-per-cylinder\\fB:\\fPBlocks-to-skip (for anything else)\n.fi\n.IP \"\" 6\nIf \n.I X\nis not given,\nthe values used when the file system was created\nare used.\nIf these values were not specified, then the value\n.I 400:9\nis used.\n.TP 6\n.BR \\-\\^S \\fIX\nConditionally reconstruct the free list. This option\nis like\n.BR \\-s \\fIX\nabove except that the free list is rebuilt only\nif there were no discrepancies discovered in the\nfile system. Using\n.B \\-S\nwill force a no response to all questions asked\nby\n.I fsck.\nThis option is useful for forcing free list reorganization\non uncontaminated file systems.\n.TP 6\n.B \\-\\^t\nIf\n.I fsck\ncannot obtain enough memory to keep its tables,\nit uses a scratch file. If the \\f3\\-t\\fP option is\nspecified, the file named in the next argument\nis used as the scratch file, if needed. Without the\n.BR \"\\-t \" flag,\n.I fsck\nwill prompt the operator for the name of the\nscratch file. The file chosen should not be on the\nfile system being checked, and if it is not\na special file or did not already exist, it is\nremoved when\n.I fsck\ncompletes.\n.PP\nIf no file systems are given to \n.I fsck\nthen a default list of file systems is read from\nthe file\n.IR /etc/fstab .\n.PP\n.ne 10\nInconsistencies checked are as follows:\n.TP 6\n1.\nBlocks claimed by more than one inode or the free list.\n.br\n.br\n.ns\n.TP 6\n2.\nBlocks claimed by an inode or the free list outside the range of the file system.\n.br\n.br\n.ns\n.TP 6\n3.\nIncorrect link counts.\n.br\n.br\n.ns\n.TP 6\n4.\nSize checks:\n.br\n.ns\n.IP \"\" 12\nDirectory size not 16-byte aligned.\n.br\n.br\n.ns\n.TP 6\n5.\nBad inode format.\n.br\n.br\n.ns\n.TP 6\n6.\nBlocks not accounted for anywhere.\n.br\n.br\n.ns\n.TP 6\n7.\nDirectory checks:\n.br\n.br\n.ns\n.IP \"\" 12\nFile pointing to unallocated inode.\n.br\nInode number out of range.\n.br\n.br\n.ns\n.TP 6\n8.\nSuper Block checks:\n.br\n.br\n.ns\n.IP \"\" 12\nMore than 65536 inodes.\n.br\nMore blocks for inodes than there are in the file system.\n.br\n.br\n.ns\n.TP 6\n9.\nBad free block list format.\n.br\n.br\n.ns\n.TP 6\n10.\nTotal free block and/or free inode count incorrect.\n.br\n.ns\n.TP 6\n11.\nAllocated inodes on the free inode list in the superblock.\n.PP\nOrphaned files and directories (allocated but unreferenced) are,\nwith the operator's concurrence, reconnected by\nplacing them in the \n.I lost+found\ndirectory.\nThe name assigned is the inode number. The only restriction\nis that the directory \n.I lost+found\nmust preexist\nin the root of the file system being checked and\nmust have empty slots in which entries can be made.\nThis can be accomplished manually by making \n.IR lost+found ,\ncopying a number of files to the directory, and then removing them\n(before\n.I\nfsck\nis executed).\n.IR Mkfs (8)\nwill automatically create a\n.I lost+found\ndirectory.\n.PP\nChecking the raw device is almost always faster.\nThe root device should not be checked using the raw device,\nhowever, since it cannot be unmounted.\n.SH FILES\n.ta 2i\n/etc/fstab\tdefault list of file systems to check\n.SH DIAGNOSTICS\nThe diagnostics produced by \n.I fsck\nare intended to be self-explanatory.\nThe exit codes with the\n.B \\-p\noption are 0 (no problems that weren't fixed), 4 (root file system was\nmodified), 8 (problems that couldn't be fixed) and 12\n.RI ( fsck\nwas interrupted).\n.SH \"SEE ALSO\"\nfilsys(5), fstab(5), crash(8), mkfs(8), mklost+found(8), reboot(8)\n.br\nT. J. Kowalski,\n.I \"FSCK \\- The UNIX File System Check Program\"\n.SH BUGS\nInode numbers for\n.BR . \"\"\nand\n.BR .. \"\"\nin each directory should be checked for validity.\n"
  },
  {
    "path": "share/man/man8/getty.8",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)getty.8\t6.4.1 (2.11BSD) 1996/11/17\n.\\\"\n.TH GETTY 8  \"November 17, 1996\"\n.UC 4\n.SH NAME\ngetty  \\- set terminal mode\n.SH SYNOPSIS\n.B getty\n[ type [ tty ] ]\n.SH DESCRIPTION\n.I Getty\nis usually invoked by\n.IR  init (8)\nto open and initialize the tty line, read a login name, and invoke\n.IR login (1).\n.I getty\nattempts to adapt the system to the speed and type of terminal\nbeing used.\n.PP\nThe argument\n.I tty\nis the special device file in /dev to open for the terminal (e.g., ``ttyh0'').\nIf there is no argument or the argument is\n``\\-'', the tty line is assumed to be open as file descriptor 0.\n.PP\nThe\n.I type\nargument can be used to make\n.I getty\ntreat the terminal line specially.\nThis argument is used as an index into the\n.IR gettytab (5)\ndatabase, to determine the characteristics of the line.\nIf there is no argument, or there is no such table, the\n.B default\ntable is used.\nIf there is no\n.B /etc/gettytab\na set of system defaults is used.\nIf indicated by the table located,\n.I getty\nwill clear the terminal screen,\nprint a banner heading,\nand prompt for a login name.\nUsually either the banner of the login prompt will include\nthe system hostname.\nThen the user's name is read, a character at a time.\nIf a null character is received, it is assumed to be the result\nof the user pushing the `break' (`interrupt') key.\nThe speed is usually then\nchanged and the `login:' is typed again;\na second `break' changes the speed again and the `login:'\nis typed once more.\nSuccessive `break' characters cycle through the\nsame standard set of speeds.\n.PP\nThe user's name is terminated by a new-line or\ncarriage-return character.\nThe latter results in the system being set to\ntreat carriage returns appropriately (see\n.IR  tty (4)).\n.PP\nThe user's name is scanned to see if\nit contains any lower-case alphabetic characters; if not,\nand if the name is nonempty, the\nsystem is told to map any future upper-case characters\ninto the corresponding lower-case characters.\n.PP\nFinally,\n.I login\nis called with the user's name as an argument.\n.PP\nMost of the default actions of\n.I getty\ncan be circumvented, or modified, by a suitable\n.I gettytab\ntable.\n.PP\n.I Getty\ncan be set to timeout after some interval,\nwhich will cause dial up lines to hang up\nif the login name is not entered reasonably quickly.\n.SH DIAGNOSTICS\n\\fIttyxx\\fR\\|\\fB: No such device or address\\fR.\n\\fIttyxx\\fR\\|\\fB: No such file or address\\fR.\nA terminal which is turned\non in the \\fIttys\\fR file cannot be opened, likely because the requisite\nlines are either not configured into the system, the associated device\nwas not attached during boot-time system configuration,\nor the special file in /dev does not exist.\n.SH FILES\n/etc/gettytab\n.SH \"SEE ALSO\"\ngettytab(5), init(8), login(1), ioctl(2), tty(4), ttys(5)\n"
  },
  {
    "path": "share/man/man8/htable.8",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)htable.8\t6.3 (Berkeley) 5/22/86\n.\\\"\n.TH HTABLE 8 \"May 22, 1986\"\n.UC 5\n.SH NAME\nhtable \\- convert NIC standard format host tables\n.SH SYNOPSIS\n.B /etc/htable\n[\n.B \\-c\n.I connected-nets\n] [\n.B \\-l\n.I local-nets\n]\n.I file\n.SH DESCRIPTION\n.I Htable\nis used to convert host files in the format specified\nin Internet RFC 810 to the format used by the network\nlibrary routines.  Three files are created as a result\nof running \n.IR htable :\n.IR hosts ,\n.IR networks ,\nand\n.IR gateways .\nThe \n.I hosts\nfile may be used by the \n.IR gethostbyname (3N)\nroutines in mapping host names to addresses\nif the nameserver,\n.IR named (8),\nis not used.\nThe\n.I networks\nfile is used by the\n.IR getnetent (3N)\nroutines in mapping network names to numbers.\nThe\n.I gateways\nfile may be used by the routing daemon\nin identifying ``passive'' Internet gateways;\nsee\n.IR routed (8C)\nfor an explanation.\n.PP\nIf any of the files\n.IR localhosts ,\n.IR localnetworks ,\nor\n.I localgateways\nare present in the current directory,\nthe file's contents is prepended to the\noutput file.\nOf these, only the gateways file is interpreted.\nThis allows sites to maintain local aliases and\nentries which are not normally present in the\nmaster database.\nOnly one gateway to each network will be placed in the gateways file;\na gateway listed in the localgateways file will override any in the\ninput file.\n.PP\nIf the gateways file is to be used,\na list of networks to which the host is directly connected\nis specified with the\n.B \\-c\nflag.\nThe networks, separated by commas,\nmay be given by name or in Internet-standard dot notation,\ne.g.\n.B \\-c\narpanet,128.32,local-ether-net.\n.I Htable\nonly includes gateways\nwhich are directly connected to one of the networks specified,\nor which can be reached from another gateway on a connected net.\n.PP\nIf the\n.B \\-l\noption is given with a list of networks (in the same format as for\n.BR \\-c ),\nthese networks will be treated as ``local,''\nand information about hosts on local networks is\ntaken only from the localhosts file.\nEntries for local hosts from the main database will be omitted.\nThis allows the localhosts file to completely override\nany entries in the input file.\n.PP\n.I Htable\nis best used in conjunction with the\n.IR gettable (8C)\nprogram which retrieves the NIC database from a host.\n.SH \"SEE ALSO\"\nintro(3N),\ngettable(8C),\nnamed(8)\n.SH BUGS\nIf the name-domain system provided network name mapping well as host\nname mapping,\n.I htable\nwould no longer be needed.\n"
  },
  {
    "path": "share/man/man8/intro.8",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)intro.8\t6.3 (Berkeley) 5/29/86\n.\\\"\n.TH INTRO 8 \"May 29, 1986\"\n.UC 5\n.SH NAME\nintro \\- introduction to system maintenance and operation commands\n.SH DESCRIPTION\nThis section contains information related to system operation\nand maintenance.\nIt describes commands used to create new file systems,\n.IR newfs ,\nverify the integrity of the file systems,\n.IR fsck ,\ncontrol disk usage,\n.IR edquota ,\nmaintain system backups,\n.IR dump ,\nand recover files when disks die an untimely death,\n.IR restore .\nThe section \n.I format\nshould be consulted when formatting disk packs.\nNetwork related services are distinguished as 8C.\nThe section\n.I crash\nshould be consulted in understanding how to interpret system\ncrash dumps.\n"
  },
  {
    "path": "share/man/man8/lpc.8",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)lpc.8\t6.1.1 (2.11BSD) 1996/11/1\n.\\\"\n.TH LPC 8 \"November 1, 1996\"\n.UC 5\n.ad\n.SH NAME\nlpc \\- line printer control program\n.SH SYNOPSIS\n.B /usr/sbin/lpc\n[ command [ argument ... ] ]\n.SH DESCRIPTION\n.I Lpc\nis used by the system administrator to control the\noperation of the line printer system.  \nFor each line printer configured in /etc/printcap,\n.I lpc\nmay be used to:\n.IP \\(bu\ndisable or enable a printer,\n.IP \\(bu\ndisable or enable a printer's spooling queue,\n.IP \\(bu\nrearrange the order of jobs in a spooling queue,\n.IP \\(bu\nfind the status of printers, and their associated\nspooling queues and printer dameons.\n.PP\nWithout any arguments,\n.I lpc\nwill prompt for commands from the standard input.\nIf arguments are supplied,\n.IR lpc\ninterprets the first argument as a command and the remaining\narguments as parameters to the command.  The standard input\nmay be redirected causing\n.I lpc\nto read commands from file.\nCommands may be abreviated;\nthe following is the list of recognized commands.\n.TP\n? [ command ... ]\n.TP\nhelp [ command ... ]\n.br\nPrint a short description of each command specified in the argument list,\nor, if no arguments are given, a list of the recognized commands.\n.TP\nabort { all | printer ... }\n.br\nTerminate an active spooling daemon on the local host immediately and\nthen disable printing (preventing new daemons from being started by\n.IR lpr )\nfor the specified printers.\n.TP\nclean { all | printer ... }\n.br\nRemove any temporary files, data files, and control files that cannot\nbe printed (i.e., do not form a complete printer job)\nfrom the specified printer queue(s) on the local machine.\n.TP\ndisable { all | printer ... }\n.br\nTurn the specified printer queues off.  This prevents new\nprinter jobs from being entered into the queue by\n.IR lpr .\n.TP\ndown { all | printer } message ...\n.br\nTurn the specified printer queue off, disable printing and put\n.I message\nin the printer status file. The message doesn't need to be quoted, the\nremaining arguments are treated like\n.IR echo (1).\nThis is normally used to take a printer down and let others know why\n(lpq will indicate the printer is down and print the status message).\n.TP\nenable { all | printer ... }\n.br\nEnable spooling on the local queue for the listed printers. \nThis will allow\n.I lpr\nto put new jobs in the spool queue.\n.TP\nexit\n.TP\nquit\n.br\nExit from lpc.\n.TP\nrestart { all | printer ... }\n.br\nAttempt to start a new printer daemon. \nThis is useful when some abnormal condition causes the daemon to\ndie unexpectedly leaving jobs in the queue.\n.I Lpq\nwill report that there is no daemon present when this condition occurs. \nIf the user is the super-user,\ntry to abort the current daemon first (i.e., kill and restart a stuck daemon).\n.TP\nstart { all | printer ... }\n.br\nEnable printing and start a spooling daemon for the listed printers.\n.TP\nstatus { all | printer ... }\nDisplay the status of daemons and queues on the local machine.\n.TP\nstop { all | printer ... }\n.br\nStop a spooling daemon after the current job completes and disable\nprinting.\n.TP\ntopq printer [ jobnum ... ] [ user ... ]\n.br\nPlace the jobs in the order listed at the top of the printer queue.\n.TP\nup { all | printer ... }\n.br\nEnable everything and start a new printer daemon. Undoes the effects of\n.IR down .\n.SH FILES\n.nf\n.ta \\w'/etc/printcap           'u\n/etc/printcap\tprinter description file\n/usr/spool/*\tspool directories\n/usr/spool/*/lock\tlock file for queue control\n.fi\n.SH \"SEE ALSO\"\nlpd(8),\nlpr(1),\nlpq(1),\nlprm(1),\nprintcap(5)\n.SH DIAGNOSTICS\n.nf\n.ta \\w'?Ambiguous command      'u\n?Ambiguous command\tabreviation matches more than one command\n?Invalid command\tno match was found\n?Privileged command\tcommand can be executed by root only\n.fi\n"
  },
  {
    "path": "share/man/man8/lpd.8",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)lpd.8\t6.3.1 (2.11BSD) 1996/10/23\n.\\\"\n.TH LPD 8 \"October 23, 1996\"\n.UC 5\n.ad\n.SH NAME\nlpd \\- line printer daemon\n.SH SYNOPSIS\n.B /usr/sbin/lpd\n[\n.B \\-l\n] [ port # ]\n.SH DESCRIPTION\n.I Lpd\nis the line printer daemon (spool area handler) and is normally invoked\nat boot time from the\n.IR rc (8)\nfile.  It makes a single pass through the\n.IR printcap (5)\nfile to find out about the existing printers and\nprints any files left after a crash. It then uses the system calls\n.IR listen (2)\nand\n.IR accept (2)\nto receive requests to print files in the queue,\ntransfer files to the spooling area, display the queue,\nor remove jobs from the queue.  In each case, it forks a child to handle\nthe request so the parent can continue to listen for more requests.\nThe Internet port number used to rendezvous\nwith other processes is normally obtained with\n.IR getservbyname (3)\nbut can be changed with the\n.IR port #\nargument.\nThe\n.B \\-l\nflag causes\n.I lpd\nto log valid requests received from the network. This can be useful\nfor debugging purposes.\n.PP\nAccess control is provided by two means. First, All requests must come from\none of the machines listed in the file\n.I /etc/hosts.equiv\nor\n.IR /etc/hosts.lpd .\nSecond, if the ``rs'' capability is specified in the\n.I printcap\nentry for the printer being accessed,\n.I lpr\nrequests will only be honored for those users with accounts on the\nmachine with the printer.\n.PP\nThe file\n.I minfree\nin each spool directory contains the number of disk blocks to leave free\nso that the line printer queue won't completely fill the disk.\nThe\n.I minfree\nfile can be edited with your favorite text editor.\n.PP\nThe file\n.I lock\nin each spool directory is used to prevent multiple daemons from\nbecoming active simultaneously, and to store information\nabout the daemon process for\n.IR lpr (1),\n.IR lpq (1),\nand\n.IR lprm (1).\nAfter the daemon has successfully set the lock, it scans the directory\nfor files beginning with \n.IR cf .\nLines in each\n.I cf\nfile specify files to be printed or non-printing actions to be\nperformed.  Each such line begins with a key character\nto specify what to do with the remainder of the line.\n.in +3\n.IP J\nJob Name.  String to be used for the job name on the burst page.\n.IP C\nClassification.  String to be used for the classification line\non the burst page.\n.IP L\nLiteral.  The line contains identification info from\nthe password file and causes the banner page to be printed.\n.IP T\nTitle.  String to be used as the title for\n.IR pr (1).\n.IP H\nHost Name.  Name of the machine where\n.I lpr\nwas invoked.\n.IP P\nPerson.  Login name of the person who invoked\n.IR lpr .\nThis is used to verify ownership by\n.IR lprm .\n.IP M\nSend mail to the specified user when the current print job completes.\n.IP f\nFormatted File.  Name of a file to print which is already formatted.\n.IP l\nLike ``f'' but passes control characters and does not make page breaks.\n.IP p\nName of a file to print using\n.IR pr (1)\nas a filter.\n.IP t\nTroff File.  The file contains\n.IR troff (1)\noutput (cat phototypesetter commands).\n.IP n\nDitroff File.  The file contains device independent troff\noutput.\n.IP d\nDVI File.  The file contains\n.IR Tex (l)\noutput (DVI format from Standford).\n.IP g\nGraph File.  The file contains data produced by\n.IR plot (3X).\n.IP c\nCifplot File. The file contains data produced by\n.IR cifplot .\n.IP v\nThe file contains a raster image.\n.IP r\nThe file contains text data with FORTRAN carriage control characters.\n.IP 1\nTroff Font R. Name of the font file to use instead of the default.\n.IP 2\nTroff Font I. Name of the font file to use instead of the default.\n.IP 3\nTroff Font B. Name of the font file to use instead of the default.\n.IP 4\nTroff Font S. Name of the font file to use instead of the default.\n.IP W\nWidth. Changes the page width (in characters) used by\n.IR pr (1)\nand the text filters.\n.IP I\nIndent.  The number of characters to indent the output by (in ascii).\n.IP U\nUnlink.  Name of file to remove upon completion of printing.\n.IP N\nFile name.  The name of the file which is being printed, or a blank\nfor the standard input (when \n.I lpr\nis invoked in a pipeline).\n.in -5\n.PP\nIf a file can not be opened, a message will be logged via\n.IR syslog (3)\nusing the\n.I LOG_LPR\nfacility.\n.I Lpd\nwill try up to 20 times\nto reopen a file it expects to be there, after which it will\nskip the file to be printed.\n.PP\n.I Lpd\nuses\n.IR flock (2)\nto provide exclusive access to the lock file and to prevent multiple\ndeamons from becoming active simultaneously.  If the daemon should be killed\nor die unexpectedly, the lock file need not be removed.\nThe lock file is kept in a readable ASCII form\nand contains two lines.\nThe first is the process id of the daemon and the second is the control\nfile name of the current job being printed.  The second line is updated to\nreflect the current status of\n.I lpd\nfor the programs\n.IR lpq (1)\nand\n.IR lprm (1).\n.SH FILES\n.nf\n.ta \\w'/etc/printcap           'u\n/etc/printcap\tprinter description file\n/usr/spool/*\tspool directories\n/usr/spool/*/minfree\tminimum free space to leave\n/dev/lp*\tline printer devices\n/dev/printer\tsocket for local requests\n/etc/hosts.equiv\tlists machine names allowed printer access\n/etc/hosts.lpd\tlists machine names allowed printer access,\n\t\tbut not under same administrative control.\n.fi\n.SH \"SEE ALSO\"\nlpc(8),\npac(1),\nlpr(1),\nlpq(1),\nlprm(1),\nsyslog(3),\nprintcap(5)\n.br\n.ul\n4.2BSD Line Printer Spooler Manual\n"
  },
  {
    "path": "share/man/man8/makedev.8",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)makedev.8\t6.2 (Berkeley) 5/19/86\n.\\\"\n.TH MAKEDEV 8 \"May 19, 1986\"\n.UC 5\n.SH NAME\nmakedev \\- make system special files\n.SH SYNOPSIS\n.B /dev/MAKEDEV \n.IR device ...\n.SH DESCRIPTION\n.I MAKEDEV\nis a shell script normally used to install\nspecial files.  It resides in the \n.I /dev\ndirectory, as this is the normal location of special files.\nArguments to \n.I MAKEDEV\nare usually of the form\n.IR device-name ?\nwhere\n.I device-name\nis one of the supported devices listed in section 4 of the\nmanual and ``?'' is a logical unit number (0-9).  A few\nspecial arguments create assorted collections of devices and are\nlisted below.\n.TP\n.B std\nCreate the\n.I standard\ndevices for the system; e.g. /dev/console, /dev/tty.\nThe VAX-11/780 console floppy device, /dev/floppy, and VAX-11/750\nand VAX-11/730 console cassette device(s), /dev/tu?, are also\ncreated with this entry.\n.TP\n.B local\nCreate those devices specific to the local site.  This\nrequest causes the shell file \n.I /dev/MAKEDEV.local\nto be executed.  Site specific commands, such as those\nused to setup dialup lines as ``ttyd?'' should be included\nin this file.\n.PP\nSince all devices are created using \n.IR mknod (8),\nthis shell script is useful only to the super-user.\n.SH DIAGNOSTICS\nEither self-explanatory, or generated by one of the programs\ncalled from the script.  Use ``sh -x MAKEDEV'' in case of\ntrouble.\n.SH \"SEE ALSO\"\nintro(4),\nconfig(8),\nmknod(8)\n"
  },
  {
    "path": "share/man/man8/makekey.8",
    "content": ".\\\"\t@(#)makekey.8\t6.1.1 (2.11BSD) 1996/10/23\n.\\\"\n.TH MAKEKEY 8 \"October 23, 1996\"\n.AT 3\n.SH NAME\nmakekey \\- generate encryption key\n.SH SYNOPSIS\n.B /usr/sbin/makekey\n.SH DESCRIPTION\n.I Makekey\nimproves the usefulness of encryption schemes depending on a key by\nincreasing the amount of time required to search the key space.  It\nreads 10 bytes from its standard input, and writes 13 bytes on its\nstandard output.  The output depends on the input in a way intended to\nbe difficult to compute (that is, to require a substantial fraction of\na second).\n.PP\nThe first eight input bytes\n(the\n.IR \"input key\" )\ncan be arbitrary ASCII characters.\nThe last two (the\n.IR salt )\nare best chosen from the set of digits, upper- and lower-case\nletters, and `.' and `/'.\nThe salt characters are repeated as the first two characters of the output.\nThe remaining 11 output characters are chosen from the same set as the salt\nand constitute the\n.I \"output key.\"\n.PP\nThe transformation performed is essentially the following:\nthe salt is used to select one of 4096 cryptographic\nmachines all based on the National Bureau of Standards\nDES algorithm, but modified in 4096 different ways.\nUsing the input key as key,\na constant string is fed into the machine and recirculated a number of times.\nThe 64 bits that come out are distributed into the\n66 useful key bits in the result.\n.PP\n.I Makekey\nis intended for programs that perform encryption (for instance,\n.I ed\nand\n.IR crypt (1)).\nUsually makekey's input and output will be pipes.\n.SH SEE ALSO\ncrypt(1), ed(1)\n"
  },
  {
    "path": "share/man/man8/named.8",
    "content": ".\\\" Copyright (c) 1985 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)named.8\t6.5 (Berkeley) 2/28/88\n.\\\"\n.TH NAMED 8 \"February 28, 1988\"\n.UC 4\n.SH NAME\nnamed \\- Internet domain name server\n.SH SYNOPSIS\n.B named\n[\n.B \\-d\n.I debuglevel\n] [\n.B \\-p\n.I port#\n] [{\\-b}\n.I bootfile\n]\n.SH DESCRIPTION\n.I Named\nis the Internet domain name server.\nSee RFC883 for more information on the Internet name-domain system.\nWithout any arguments,\n.I named\nwill read the default boot file\n.IR /etc/named.boot ,\nread any initial data and listen for queries.\n.PP\nOptions are:\n.TP\n.B \\-d\nPrint debugging information.\nA number after the ``d'' determines the level of\nmessages printed.\n.TP\n.B \\-p\nUse a different port number.  The default is the standard port number\nas listed in /etc/services.\n.TP\n.B \\-b\nUse an alternate boot file.  This is optional and allows you to\nspecify a file with a leading dash.\n.PP\nAny additional argument is taken as the name of the boot file.\nThe boot file contains information about where the name server is to get\nits initial data.  If multiple boot files are specified, only the last\nis used.\nLines in the boot file cannot be continued on subsequent lines.\nThe following is a small example:\n.in +2m\n.nf\n\n;\n;\tboot file for name server\n;\ndirectory\t/usr/local/domain\n\n.ta \\w'forwarders\\ 'u +\\w'6.32.128.IN-ADDR.ARPA\\ 'u +\\w'128.32.137.8 128.32.137.3\\ 'u\n; type\tdomain\tsource host/file\t\t\t\tbackup file\n\ncache\t.\t\t\t\t\t\t\troot.cache\nprimary\tBerkeley.EDU\tberkeley.edu.zone\nprimary\t32.128.IN-ADDR.ARPA\tucbhosts.rev\nsecondary\tCC.Berkeley.EDU\t128.32.137.8 128.32.137.3\tcc.zone.bak\nsecondary\t6.32.128.IN-ADDR.ARPA\t128.32.137.8 128.32.137.3\tcc.rev.bak\nprimary\t0.0.127.IN-ADDR.ARPA\t\t\t\t\tlocalhost.rev\nforwarders\t10.0.0.78 10.2.0.78\n; slave\n\n.DT\n.fi\n.in\nThe ``directory'' line causes the server to change its\nworking directory to the directory specified.  This can\nbe important for the correct processing of $INCLUDE files\nin primary zone files.\n.LP\nThe ``cache'' line specifies that data in ``root.cache'' is to be\nplaced in the backup cache.\nIts main use is to specify data such as locations of root domain servers.\nThis cache is not used during normal operation,\nbut is used as ``hints'' to find the current root servers.\nThe file ``root.cache'' is in the same format as ``berkeley.edu.zone''.\nThere can be more than one ``cache'' file specified.\n.\\\"The first such file will be updated under certain conditions to snapshot the\n.\\\"cache (see SIGQUIT below).\n.\\\"The cache line can also have an optional interval argument after\n.\\\"the filename.\n.\\\"If an interval is listed,\n.\\\"it requests the nameserver to dump the cache contents\n.\\\"at that interval (in seconds).\n.\\\"The example above requests the nameserver to dump the cache content\n.\\\"every 3600 seconds (once an hour).\n.\\\"The use of automatic cache file updates is not currently recommended\n.\\\"because of the way the cache is currently managed by the server;\n.\\\"although the entire cache will be dumped for later reloading,\n.\\\"most of the cache contents will be ignored when reloaded.\n.\\\"The exact dump interval will vary\n.\\\"based on the minimum maintence interval time which is typically about\n.\\\"5 minutes.\nThe cache files are processed in such a way as to preserve the\ntime-to-live's\nof data dumped out.  Data for the root nameservers is kept artificially\nvalid if necessary.\n.LP\nThe first ``primary'' line states that the file ``berkeley.edu.zone'' contains\nauthoritative data for the ``Berkeley.EDU'' zone.\nThe file ``berkeley.edu.zone''\ncontains data in the master file format described in RFC883.\nAll domain names are relative to the origin, in this\ncase, ``Berkeley.EDU'' (see below for a more detailed description).\nThe second ``primary'' line states that the file ``ucbhosts.rev'' contains\nauthoritative data for the domain ``32.128.IN-ADDR.ARPA,'' which is used\nto translate addresses in network 128.32 to hostnames.\nEach master file should begin with an SOA record for the zone\n(see below).\n.LP\nThe first ``secondary'' line specifies that all authoritative data\nunder ``CC.Berkeley.EDU'' is to be transferred from the name server\nat 128.32.137.8.  If the transfer fails it will try 128.32.137.3 and\ncontinue trying the addresses, up to 10, listed on this line.\nThe secondary copy is also authoritative for the specified domain.\nThe first non-dotted-quad address on this line will be taken\nas a filename in which to backup the transfered zone.\nThe name server will load the zone from this backup file if it exists\nwhen it boots, providing a complete copy even if the master servers\nare unreachable.\nWhenever a new copy of the domain is received by automatic zone transfer\nfrom one of the master servers, this file will be updated.\nThe second ``secondary'' line states that the address-to-hostname\nmapping for the subnet 128.32.136 should be obtained from the same list\nof master servers as the previous zone.\n.LP\nThe ``forwarders'' line specifies the addresses of sitewide servers\nthat will accept recursive queries from other servers.\nIf the boot file specifies one or more forwarders, then the\nserver will send all queries for data not in the cache to the forwarders first.\nEach forwarder will be asked in turn until an answer is returned\nor the list is exhausted.  If no answer is forthcoming from a\nforwarder, the server will continue as it would have without\nthe forwarders line unless it is in ``slave'' mode.\nThe forwarding facility is useful\nto cause a large sitewide cache to be generated on a master,\nand to reduce traffic over links to outside servers.\nIt can also be used to allow servers to run that do not have\naccess directly to the Internet, but wish to act as though\nthey do.\n.LP\nThe ``slave'' line (shown commented out) is used to put the server\nin slave mode.  In this mode, the server will only make queries to\nforwarders.  This option is normally used on machine that wish to\nrun a server but for physical or administrative reasons cannot\nbe given access to the Internet, but have access to a host that\ndoes have access.\n.LP\nThe ``sortlist'' line can be used to indicate networks that are to be\npreferred over other, unlisted networks.\nQueries for host addresses from hosts on the same network as the server\nwill receive responses with local network addresses listed first,\nthen addresses on the sort list, then other addresses.\nThis line is only acted on at initial startup.\nWhen reloading the nameserver with\na SIGHUP, this line will be ignored.\n.PP\nThe master file consists of control information\nand a list of resource records for objects in the zone\nof the forms:\n.RS\n.nf\n\n$INCLUDE <filename> <opt_domain>\n$ORIGIN <domain>\n<domain> <opt_ttl> <opt_class> <type> <resource_record_data>\n\n.fi\n.RE\nwhere\n.I domain\nis \".\" for root, \"@\" for the current origin, or a standard domain\nname. If\n.I domain\nis a standard domain name that does not end with ``.'', the current origin\nis appended to the domain. Domain names ending with ``.'' are\nunmodified.\nThe\n.I opt_domain\nfield is used to define an origin for the data in an included file.\nIt is equivalent to placing a $ORIGIN statement before the first\nline of the included file.  The field is optional.\nNeither the\n.I opt_domain\nfield nor $ORIGIN statements in the included file modify the current origin\nfor this file.\nThe\n.I opt_ttl\nfield is an optional integer number for the time-to-live field.\nIt defaults to zero, meaning the minimum value specified in the SOA\nrecord for the zone.\nThe\n.I opt_class\nfield is the object address type; currently only one type is supported,\n.BR IN ,\nfor objects connected to the DARPA Internet. \nThe\n.I type\nfield contains one of the following tokens; the data expected in the\n.I resource_record_data\nfield is in parentheses.\n.TP \"\\w'MINFO    'u\"\nA\na host address (dotted quad)\n.IP NS\nan authoritative name server (domain)\n.IP MX\na mail exchanger (domain)\n.IP CNAME\nthe canonical name for an alias (domain)\n.IP SOA\nmarks the start of a zone of authority (domain of originating host,\ndomain address of maintainer, a serial number and the following\nparameters in seconds: refresh, retry, expire and minimum TTL (see RFC883))\n.IP MB\na mailbox domain name (domain)\n.IP MG\na mail group member (domain)\n.IP MR\na mail rename domain name (domain)\n.IP NULL\na null resource record (no format or data)\n.IP WKS\na well know service description (not implemented yet)\n.IP PTR\na domain name pointer (domain)\n.IP HINFO\nhost information (cpu_type OS_type)\n.IP MINFO\nmailbox or mail list information (request_domain error_domain)\n.PP\nResource records normally end at the end of a line,\nbut may be continued across lines between opening and closing parentheses.\nComments are introduced by semicolons and continue to the end of the line.\n.PP\nEach master zone file should begin with an SOA record for the zone.\nAn example SOA record is as follows:\n.LP\n.nf\n@\tIN\tSOA\tucbvax.Berkeley.EDU. rwh.ucbvax.Berkeley.EDU. (\n\t\t\t\t2.89\t; serial\n\t\t\t\t10800\t; refresh\n\t\t\t\t3600\t; retry\n\t\t\t\t3600000\t; expire\n\t\t\t\t86400 )\t; minimum\n.fi\n.LP\nThe SOA lists a serial number, which should be changed each time the master\nfile is changed.\nSecondary servers check the serial number at intervals specified by the refresh\ntime in seconds; if the serial number changes, a zone transfer will be done\nto load the new data.\nIf a master server cannot be contacted when a refresh is due, the retry time\nspecifies the interval at which refreshes should be attempted until successful.\nIf a master server cannot be contacted within the interval given by the\nexpire time, all data from the zone is discarded by secondary servers.\nThe minimum value is the time-to-live used by records in the file\nwith no explicit time-to-live value.\n.SH NOTES\nThe boot file directives ``domain'' and ``suffixes'' have been\nobsoleted by a more useful resolver based implementation of\nsuffixing for partially qualified domain names.  The prior mechanisms\ncould fail under a number of situations, especially when then local\nnameserver did not have complete information.\n.sp\nThe following signals have the specified effect when sent to the\nserver process using the\n.IR kill (1)\ncommand.\n.IP SIGHUP\nCauses server to read named.boot and reload database.\n.IP SIGINT\nDumps current data base and cache to /usr/tmp/named_dump.db\n.\\\".IP SIGQUIT\n.\\\"Causes the server to checkpoint the cache into the first ``cache'' file.\n.IP SIGIOT\nDumps statistics data into /usr/tmp/named.stats if the server is\ncompiled -DSTATS.  Statistics data is appended to the file.\n.IP SIGSYS\nDumps the profiling data in /usr/tmp if the server is compiled\nwith profiling (server forks, chdirs and exits).\n.IP SIGTERM\nDumps the primary and secondary database files.\nUsed to save modified data on shutdown if the\nserver is compiled with dynamic updating enabled.\n.IP SIGUSR1\nTurns on debugging; each SIGUSR1 increments debug level.\n(SIGEMT on older systems without SIGUSR1)\n.IP SIGUSR2\nTurns off debugging completely.\n(SIGFPE on older systems without SIGUSR2)\n.SH FILES\n.nf\n.ta \\w'/usr/tmp/named_dump.db   'u\n/etc/named.boot\tname server configuration boot file\n/var/run/named.pid\tthe process id\n/usr/tmp/named.run\tdebug output\n/usr/tmp/named_dump.db\tdump of the name server database\n/usr/tmp/named.stats\tnameserver statistics data\n.fi\n.SH \"SEE ALSO\"\nkill(1), gethostbyname(3), signal(3), resolver(3), resolver(5), hostname(7),\nRFC882, RFC883, RFC973, RFC974,\n\\fIName Server Operations Guide for BIND\\fR\n"
  },
  {
    "path": "share/man/man8/pac.8",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)pac.8\t6.2.1 (2.11BSD) 1996/11/1\n.\\\"\n.TH PAC 8 \"November 1, 1996\"\n.UC 5\n.SH NAME\npac \\- printer/plotter accounting information\n.SH SYNOPSIS\n.B /usr/sbin/pac\n[\n.B \\-Pprinter\n] [\n.B \\-pprice\n] [\n.B \\-s\n] [\n.B \\-r\n] [\n.B \\-c\n] [\n.B \\-m\n] [ name ... ]\n.SH DESCRIPTION\n.I Pac\nreads the printer/plotter accounting files, accumulating the number\nof pages (the usual case) or feet (for raster devices)\nof paper consumed by each user, and printing out\nhow much each user consumed in pages or feet and dollars.\nIf any\n.I names\nare specified, then statistics are only printed for those users;\nusually, statistics are printed for every user who has used any paper.\n.PP\nThe\n.B \\-P\nflag causes accounting to be done for the named printer.\nNormally, accounting is done for the default printer (site dependent) or\nthe value of the environment variable\n.B PRINTER\nis used.\n.PP\nThe\n.B \\-p\nflag causes the value\n.I price\nto be used for the cost in dollars instead of the default value of 0.02\nor the price specified in\n.IR /etc/printcap.\n.PP\nThe\n.B \\-c\nflag causes the output to be sorted by cost; usually the\noutput is sorted alphabetically by name.\n.PP\nThe\n.B \\-r\nflag reverses the sorting order.\n.PP\nThe\n.B \\-s\nflag causes the accounting information to be summarized on the\nsummary accounting file; this summarization is necessary since on a\nbusy system, the accounting file can grow by several lines per day.\n.PP\nThe\n.B \\-m\nflag causes the host name to be ignored in the accounting file.  This\nallows for a user on multiple machines to have all of his printing\ncharges grouped together.\n.SH FILES\n.ta 2i\n/usr/adm/?acct\traw accounting files\n.br\n/usr/adm/?_sum\tsummary accounting files\n.br\n/etc/printcap\tprinter capability data base\n.SH SEE ALSO\nprintcap(5)\n.SH BUGS\nThe relationship between the computed price and reality is\nas yet unknown.\n"
  },
  {
    "path": "share/man/man8/rc.8",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)rc.8\t6.1 (Berkeley) 4/27/85\n.\\\"\n.TH RC 8 \"April 27, 1985\"\n.UC 4\n.SH NAME\nrc \\- command script for auto-reboot and daemons\n.SH SYNOPSIS\n.B /etc/rc\n.br\n.B /etc/rc.local\n.SH DESCRIPTION\n.I Rc\nis the command script which controls the automatic reboot and\n.I rc.local\nis the script holding commands which are pertinent only\nto a specific site.\n.PP\nWhen an automatic reboot is in progress,\n.I rc\nis invoked with the argument\n.I autoboot\nand runs a\n.I fsck\nwith option\n.B \\-p\nto ``preen'' all the disks of minor inconsistencies resulting\nfrom the last system shutdown and to check for serious inconsistencies\ncaused by hardware or software failure.\nIf this auto-check and repair succeeds, then the second part of\n.I rc\nis run.\n.PP\nThe second part of\n.I rc,\nwhich is run after a auto-reboot succeeds and also if\n.I rc\nis invoked when a single user shell terminates (see\n.IR init (8)),\nstarts all the daemons on the system, preserves editor files\nand clears the scratch directory\n.B /tmp.\n.I Rc.local\nis executed immediately before any other commands after a successful\n.IR fsck .\nNormally, the first commands placed in the\n.I rc.local\nfile define the machine's name, using\n.IR hostname (1),\nand save any possible core image that might have been\ngenerated as a result of a system crash,\n.IR savecore (8).\nThe latter command is included in the\n.I rc.local\nfile because the directory in which core dumps are saved\nis usually site specific.\n.SH SEE ALSO\ninit(8),\nreboot(8),\nsavecore(8)\n.SH BUGS\n"
  },
  {
    "path": "share/man/man8/rdump.8",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)rdump.8\t6.1.1 (2.11BSD) 1996/11/17\n.\\\"\n.TH RDUMP 8 \"November 17, 1996\"\n.UC 5\n.SH NAME\nrdump \\- file system dump across the network\n.SH SYNOPSIS\n.B rdump\n[ key [\n.I argument\n\\&... ] filesystem ]\n.SH DESCRIPTION\n.I Rdump\ncopies to magnetic tape all files\nchanged after a certain date\nin the\n.I filesystem.\nThe command is identical in operation to\n.IR dump (8)\nexcept the \n.I f\nkey should be specified and the file\nsupplied should be of the form\n.IR machine:device .\n.PP\n.I Rdump\ncreates a remote server,\n.IR /usr/sbin/rmt ,\non the client machine to access the tape\ndevice.\n.SH \"SEE ALSO\"\ndump(8),\nrmt(8)\n.SH DIAGNOSTICS\nSame as \n.IR dump (8)\nwith a few extra related to the network.\n"
  },
  {
    "path": "share/man/man8/routed.8",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)routed.8\t6.2.1 (2.11BSD) 1996/11/17\n.\\\"\n.TH ROUTED 8 \"November 17, 1996\"\n.UC 5\n.SH NAME\nrouted \\- network routing daemon\n.SH SYNOPSIS\n.B routed\n[\n.B \\-d\n] [\n.B \\-g\n] [\n.B \\-s\n] [\n.B \\-q\n] [\n.B \\-t\n] [\n.I logfile\n]\n.SH DESCRIPTION\n.I Routed\nis invoked at boot time to manage the network routing tables.\nThe routing daemon uses a variant of the Xerox NS Routing\nInformation Protocol in maintaining up to date kernel routing\ntable entries.\nIt used a generalized protocol capable of use with multiple\naddress types, but is currently used only for Internet routing\nwithin a cluster of networks.\n.PP\nIn normal operation\n.I routed\nlistens on the\n.IR udp (4)\nsocket for the\n.I route\nservice (see\n.IR services (5))\nfor routing information packets.  If the host is an\ninternetwork router, it periodically supplies copies\nof its routing tables to any directly connected hosts\nand networks.\n.PP\nWhen\n.I routed\nis started, it uses the SIOCGIFCONF\n.I ioctl\nto find those\ndirectly connected interfaces configured into the\nsystem and marked ``up'' (the software loopback interface\nis ignored).  If multiple interfaces\nare present, it is assumed that the host will forward packets\nbetween networks.\n.I Routed\nthen transmits a \n.I request\npacket on each interface (using a broadcast packet if\nthe interface supports it) and enters a loop, listening\nfor\n.I request\nand\n.I response\npackets from other hosts.\n.PP\nWhen a\n.I request\npacket is received, \n.I routed\nformulates a reply based on the information maintained in its\ninternal tables.  The\n.I response\npacket generated contains a list of known routes, each marked\nwith a ``hop count'' metric (a count of 16, or greater, is\nconsidered ``infinite'').  The metric associated with each\nroute returned provides a metric\n.IR \"relative to the sender\" .\n.PP\n.I Response\npackets received by\n.I routed\nare used to update the routing tables if one of the following\nconditions is satisfied:\n.TP\n(1)\nNo routing table entry exists for the destination network\nor host, and the metric indicates the destination is ``reachable''\n(i.e. the hop count is not infinite).\n.TP\n(2)\nThe source host of the packet is the same as the router in the\nexisting routing table entry.  That is, updated information is\nbeing received from the very internetwork router through which\npackets for the destination are being routed.\n.TP\n(3)\nThe existing entry in the routing table has not been updated for\nsome time (defined to be 90 seconds) and the route is at least\nas cost effective as the current route.\n.TP\n(4)\nThe new route describes a shorter route to the destination than\nthe one currently stored in the routing tables; the metric of\nthe new route is compared against the one stored in the table\nto decide this.\n.PP\nWhen an update is applied,\n.I routed\nrecords the change in its internal tables and updates the kernel\nrouting table.\nThe change is reflected in the next\n.I response\npacket sent.\n.PP\nIn addition to processing incoming packets,\n.I routed\nalso periodically checks the routing table entries.\nIf an entry has not been updated for 3 minutes, the entry's metric\nis set to infinity and marked for deletion.  Deletions are delayed\nan additional 60 seconds to insure the invalidation is propagated\nthroughout the local internet.\n.PP\nHosts acting as internetwork routers gratuitously supply their\nrouting tables every 30 seconds to all directly connected hosts\nand networks.\nThe response is sent to the broadcast address on nets capable of that function,\nto the destination address on point-to-point links, and to the router's\nown address on other networks.\nThe normal routing tables are bypassed when sending gratuitous responses.\nThe reception of responses on each network is used to determine that the\nnetwork and interface are functioning correctly.\nIf no response is received on an interface, another route may be chosen\nto route around the interface, or the route may be dropped if no alternative\nis available.\n.PP\n.I Routed supports several options:\n.TP\n.B \\-d\nEnable additional debugging information to be logged,\nsuch as bad packets received.\n.TP\n.B \\-g\nThis flag is used on internetwork routers to offer a route\nto the ``default'' destination.\nThis is typically used on a gateway to the Internet,\nor on a gateway that uses another routing protocol whose routes\nare not reported to other local routers.\n.TP\n.B \\-s\nSupplying this\noption forces \n.I routed\nto supply routing information whether it is acting as an internetwork\nrouter or not.\nThis is the default if multiple network interfaces are present,\nor if a point-to-point link is in use.\n.TP\n.B \\-q\nThis\nis the opposite of the\n.B \\-s\noption.\n.TP\n.B \\-t\nIf the\n.B \\-t\noption is specified, all packets sent or received are\nprinted on the standard output.  In addition,\n.I routed\nwill not divorce itself from the controlling terminal\nso that interrupts from the keyboard will kill the process.\n.PP\nAny other argument supplied is interpreted as the name\nof file in which \n.IR routed 's\nactions should be logged.  This log contains information\nabout any changes to the routing tables and, if not tracing all packets,\na history of recent messages sent and received which are related to\nthe changed route.\n.PP\nIn addition to the facilities described above, \n.I routed\nsupports the notion of ``distant''\n.I passive\nand \n.I active\ngateways.  When \n.I routed\nis started up, it reads the file\n.I /etc/gateways\nto find gateways which may not be located using\nonly information from the SIOGIFCONF\n.IR ioctl .\nGateways specified in this manner should be marked passive\nif they are not expected to exchange routing information,\nwhile gateways marked active\nshould be willing to exchange routing information (i.e.\nthey should have a\n.I routed\nprocess running on the machine).\nPassive gateways are maintained in the\nrouting tables forever and information\nregarding their existence is included in\nany routing information transmitted.\nActive gateways are treated equally to network\ninterfaces.  Routing information is distributed\nto the gateway and if no routing information is\nreceived for a period of the time, the associated\nroute is deleted.\nExternal gateways are also passive, but are not placed in the kernel\nrouting table nor are they included in routing updates.\nThe function of external entries is to inform\n.I routed\nthat another routing process\nwill install such a route, and that alternate routes to that destination\nshould not be installed.\nSuch entries are only required when both routers may learn of routes\nto the same destination.\n.PP\nThe \n.I /etc/gateways\nis comprised of a series of lines, each in\nthe following format:\n.PP\n.nf\n< \\fBnet\\fP | \\fBhost\\fP > \\fIname1\\fP \\fBgateway\\fP \\fIname2\\fP \\fBmetric\\fP \\fIvalue\\fP < \\fBpassive\\fP | \\fBactive\\fP | \\fBexternal\\fP >\n.fi\n.PP\nThe \n.B net\nor\n.B host\nkeyword indicates if the route is to a network or specific host.\n.PP\n.I Name1\nis the name of the destination network or host.  This may be a\nsymbolic name located in\n.I /etc/networks\nor\n.I /etc/hosts\n(or, if started after\n.IR named (8),\nknown to the name server), \nor an Internet address specified in ``dot'' notation; see\n.IR inet (3).\n.PP\n.I Name2\nis the name or address of the gateway to which messages should\nbe forwarded.\n.PP\n.I Value\nis a metric indicating the hop count to the destination host\nor network.\n.PP\nOne of the keywords\n.BR passive ,\n.B active\nor\n.B external\nindicates if the gateway should be treated as \n.I passive\nor\n.I active\n(as described above),\nor whether the gateway is external to the scope of the\n.I routed\nprotocol.\n.PP\nInternetwork routers that are directly attached to the Arpanet or Milnet\nshould use the Exterior Gateway Protocol (EGP) to gather routing information\nrather then using a static routing table of passive gateways.\nEGP is required in order to provide routes for local networks to the rest\nof the Internet system.\nSites needing assistance with such configurations\nshould contact the Computer Systems Research Group at Berkeley.\n.SH FILES\n.DT\n/etc/gateways\tfor distant gateways\n.SH \"SEE ALSO\"\n``Internet Transport Protocols'', XSIS 028112, Xerox System Integration\nStandard.\n.br\nudp(4), XNSrouted(8), htable(8)\n.SH BUGS\nThe kernel's routing tables may not correspond to those of\n.I routed\nwhen redirects change or add routes.\nThe only remedy for this is to place the routing\nprocess in the kernel.\n.PP\n.I Routed\nshould incorporate other routing protocols,\nsuch as Xerox NS\n.RI ( XNSrouted (8))\nand EGP.\nUsing separate processes for each requires configuration options\nto avoid redundant or competing routes.\n.PP\n.I Routed\nshould listen to intelligent interfaces, such as an IMP, and\nto error protocols, such as ICMP, to gather more information.\nIt does not always detect unidirectional failures in network interfaces\n(e.g., when the output side fails).\n"
  },
  {
    "path": "share/man/man8/rrestore.8",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)rrestore.8\t6.2.1 (2.11BSD) 1996/11/17\n.\\\"\n.TH RRESTORE 8 \"November 17, 1996\"\n.UC 5\n.SH NAME\nrrestore \\- restore a file system dump across the network\n.SH SYNOPSIS\n.B rrestore\n[ key [\nname ... ]\n.SH DESCRIPTION\n.I Rrestore\nobtains from magnetic tape files\nsaved by a previous\n.IR dump (8).\nThe command is identical in operation to\n.IR restore (8)\nexcept the \n.I f\nkey should be specified and the file\nsupplied should be of the form\n.IR machine:device .\n.PP\n.I Rrestore\ncreates a remote server,\n.IR rmt ,\non the client machine to access the tape\ndevice.\n.SH \"SEE ALSO\"\nrestore(8),\nrmt(8)\n.SH DIAGNOSTICS\nSame as \n.IR restore (8)\nwith a few extra related to the network.\n"
  },
  {
    "path": "share/man/man8/sendmail.8",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)sendmail.8\t6.2.1 (2.11BSD) 1996/10/23\n.\\\"\n.TH SENDMAIL 8 \"October 23, 1996\"\n.UC 4\n.SH NAME\nsendmail \\- send mail over the internet\n.SH SYNOPSIS\n.B /usr/sbin/sendmail\n[\nflags\n] [\naddress ...\n]\n.PP\n.B newaliases\n.PP\n.B mailq\n[\n.B \\-v\n]\n.SH DESCRIPTION\n.I Sendmail\nsends a message to one or more\n.IR recipients ,\nrouting the message over whatever networks\nare necessary.\n.I Sendmail\ndoes internetwork forwarding as necessary\nto deliver the message to the correct place.\n.PP\n.I Sendmail\nis not intended as a user interface routine;\nother programs provide user-friendly\nfront ends;\n.I sendmail\nis used only to deliver pre-formatted messages.\n.PP\nWith no flags,\n.I sendmail\nreads its standard input\nup to an end-of-file\nor a line consisting only of a single dot\nand sends a copy of the message found there\nto all of the addresses listed.\nIt determines the network(s) to use\nbased on the syntax and contents of the addresses.\n.PP\nLocal addresses are looked up in a file\nand aliased appropriately.\nAliasing can be prevented by preceding the address\nwith a backslash.\nNormally the sender is not included in any alias\nexpansions, e.g.,\nif `john' sends to `group',\nand `group' includes `john' in the expansion,\nthen the letter will not be delivered to `john'.\n.PP\nFlags are:\n.TP 1.2i\n.B \\-ba\nGo into \\s-1ARPANET\\s0 mode.\nAll input lines must end with a CR-LF,\nand all messages will be generated with a CR-LF at the end.\nAlso,\nthe ``From:'' and ``Sender:''\nfields are examined for the name of the sender.\n.TP 1.2i\n.B \\-bd\nRun as a daemon.  This requires Berkeley IPC.\n.I Sendmail\nwill fork and run in background\nlistening on socket 25 for incoming SMTP connections.\nThis is normally run from\n.IR /etc/rc .\n.TP 1.2i\n.B \\-bi\nInitialize the alias database.\n.TP 1.2i\n.B \\-bm\nDeliver mail in the usual way (default).\n.TP 1.2i\n.B \\-bp\nPrint a listing of the queue.\n.TP 1.2i\n.B \\-bs\nUse the \\s-2SMTP\\s0 protocol as described in RFC821\non standard input and output.\nThis flag implies all the operations of the\n.B \\-ba\nflag that are compatible with \\s-2SMTP\\s0.\n.TP 1.2i\n.B \\-bt\nRun in address test mode.\nThis mode reads addresses and shows the steps in parsing;\nit is used for debugging configuration tables.\n.TP 1.2i\n.B \\-bv\nVerify names only \\- do not try to collect or deliver a message.\nVerify mode is normally used for validating\nusers or mailing lists.\n.TP 1.2i\n.B \\-bz\nCreate the configuration freeze file.\n.TP 1.2i\n.BI \\-C file\nUse alternate configuration file.\n.I Sendmail\nrefuses to run as root if an alternate configuration file is specified.\nThe frozen configuration file is bypassed.\n.TP 1.2i\n.BI \\-d X\nSet debugging value to\n.I X.\n.TP 1.2i\n.BI \\-F fullname\nSet the full name of the sender.\n.TP 1.2i\n.BI \\-f name\nSets the name of the ``from'' person\n(i.e., the sender of the mail).\n.B \\-f\ncan only be used\nby ``trusted'' users\n(normally\n.I root,\n.I daemon,\nand\n.I network)\nor if the person you are trying to become\nis the same as the person you are.\n.TP 1.2i\n.BI \\-h N\nSet the hop count to\n.I N.\nThe hop count is incremented every time the mail is\nprocessed.\nWhen it reaches a limit,\nthe mail is returned with an error message,\nthe victim of an aliasing loop.\nIf not specified,\n``Received:'' lines in the message are counted.\n.TP 1.2i\n.B \\-n\nDon't do aliasing.\n.TP 1.2i\n.BI \\-o x\\|value\nSet option\n.I x\nto the specified\n.I value.\nOptions are described below.\n.TP 1.2i\n.BI \\-q[ time ]\nProcessed saved messages in the queue at given intervals.\nIf\n.I time\nis omitted,\nprocess the queue once.\n.I Time\nis given as a tagged number,\nwith `s' being seconds,\n`m' being minutes,\n`h' being hours,\n`d' being days,\nand\n`w' being weeks.\nFor example,\n``\\-q1h30m'' or ``\\-q90m''\nwould both set the timeout to one hour thirty minutes.\nIf\n.I time\nis specified,\n.I sendmail\nwill run in background.\nThis option can be used safely with\n.BR \\-bd .\n.TP 1.2i\n.BI \\-r name\nAn alternate and obsolete form of the\n.B \\-f\nflag.\n.TP 1.2i\n.B \\-t\nRead message for recipients.\nTo:, Cc:, and Bcc: lines will be scanned for recipient addresses.\nThe Bcc: line will be deleted before transmission.\nAny addresses in the argument list will be suppressed,\nthat is,\nthey will\n.I not\nreceive copies even if listed in the message header.\n.TP 1.2i\n.B \\-v\nGo into verbose mode.\nAlias expansions will be announced, etc.\n.PP\nThere are also a number of processing options that may be set.\nNormally these will only be used by a system administrator.\nOptions may be set either on the command line\nusing the\n.B \\-o\nflag\nor in the configuration file.\nThese are described in detail in the\n.ul\nSendmail Installation and Operation Guide.\nThe options are:\n.TP 1.2i\n.RI A file\nUse alternate alias file.\n.TP 1.2i\nc\nOn mailers that are considered ``expensive'' to connect to,\ndon't initiate immediate connection.\nThis requires queueing.\n.TP 1.2i\n.RI d x\nSet the delivery mode to\n.I x.\nDelivery modes are\n`i' for interactive (synchronous) delivery,\n`b' for background (asynchronous) delivery,\nand\n`q' for queue only \\- i.e.,\nactual delivery is done the next time the queue is run.\n.TP 1.2i\nD\nTry to automatically rebuild the alias database\nif necessary.\n.TP 1.2i\n.RI e x\nSet error processing to mode\n.I x.\nValid modes are\n`m' to mail back the error message,\n`w' to ``write'' back the error message\n(or mail it back if the sender is not logged in),\n`p' to print the errors on the terminal\n(default),\n`q' to throw away error messages\n(only exit status is returned),\nand `e'\nto do special processing for the BerkNet.\nIf the text of the message is not mailed back\nby\nmodes `m' or `w'\nand if the sender is local to this machine,\na copy of the message is appended to the file\n``dead.letter''\nin the sender's home directory.\n.TP 1.2i\n.RI F mode\nThe mode to use when creating temporary files.\n.TP 1.2i\nf\nSave UNIX-style From lines at the front of messages.\n.TP 1.2i\n.RI g N\nThe default group id to use when calling mailers.\n.TP 1.2i\n.RI H file\nThe SMTP help file.\n.TP 1.2i\ni\nDo not take dots on a line by themselves\nas a message terminator.\n.TP 1.2i\n.RI L n\nThe log level.\n.TP 1.2i\nm\nSend to ``me'' (the sender) also if I am in an alias expansion.\n.TP 1.2i\no\nIf set, this message may have\nold style headers.\nIf not set,\nthis message is guaranteed to have new style headers\n(i.e., commas instead of spaces between addresses).\nIf set, an adaptive algorithm is used that will correctly\ndetermine the header format in most cases.\n.TP 1.2i\n.RI Q queuedir\nSelect the directory in which to queue messages.\n.TP 1.2i\n.RI r timeout\nThe timeout on reads;\nif none is set,\n.I sendmail\nwill wait forever for a mailer.\nThis option violates the word (if not the intent) of the SMTP specification,\nshow the timeout should probably be fairly large.\n.TP 1.2i\n.RI S file\nSave statistics in the named file.\n.TP 1.2i\ns\nAlways instantiate the queue file,\neven under circumstances where it is not strictly necessary.\nThis provides safety against system crashes during delivery.\n.TP 1.2i\n.RI T time\nSet the timeout on undelivered messages in the queue to the specified time.\nAfter delivery has failed\n(e.g., because of a host being down)\nfor this amount of time,\nfailed messages will be returned to the sender.\nThe default is three days.\n.TP 1.2i\n.RI t stz,dtz\nSet the name of the time zone.\n.TP 1.2i\n.RI u N\nSet the default user id for mailers.\n.PP\nIn aliases,\nthe first character of a name may be\na vertical bar to cause interpretation of\nthe rest of the name as a command\nto pipe the mail to.\nIt may be necessary to quote the name\nto keep\n.I sendmail\nfrom suppressing the blanks from between arguments.\nFor example, a common alias is:\n.PP\n\tmsgs: \"|/usr/ucb/msgs -s\"\n.PP\nAliases may also have the syntax ``:include:\\c\n.IR filename ''\nto ask\n.I sendmail\nto read the named file for a list of recipients.\nFor example, an alias such as:\n.PP\n\tpoets: \":include:/usr/local/lib/poets.list\"\n.PP\nwould read\n.I /usr/local/lib/poets.list\nfor the list of addresses making up the group.\n.PP\n.I Sendmail\nreturns an exit status\ndescribing what it did.\nThe codes are defined in\n.RI < sysexits.h >\n.ta 3n +\\w'EX_UNAVAILABLE'u+3n\n.de XX\n.ti \\n(.iu\n..\n.in +\\w'EX_UNAVAILABLE'u+6n\n.XX\n \tEX_OK\tSuccessful completion on all addresses.\n.XX\n \tEX_NOUSER\tUser name not recognized.\n.XX\n \tEX_UNAVAILABLE\tCatchall meaning necessary resources\nwere not available.\n.XX\n \tEX_SYNTAX\tSyntax error in address.\n.XX\n \tEX_SOFTWARE\tInternal software error,\nincluding bad arguments.\n.XX\n \tEX_OSERR\tTemporary operating system error,\nsuch as \\*(lqcannot fork\\*(rq.\n.XX\n \tEX_NOHOST\tHost name not recognized.\n.XX\n\tEX_TEMPFAIL\tMessage could not be sent immediately,\nbut was queued.\n.PP\nIf invoked as\n.I newaliases,\n.I sendmail\nwill rebuild the alias database.\nIf invoked as\n.I mailq,\n.I sendmail\nwill print the contents of the mail queue.\n.SH FILES\nExcept for\n/etc/sendmail.cf,\nthese pathnames are all specified in\n/etc/sendmail.cf.\nThus,\nthese values are only approximations.\n.PP\n.if t .ta 2i\n.if n .ta 3i\n/etc/aliases\traw data for alias names\n.br\n/etc/aliases.pag\n.br\n/etc/aliases.dir\tdata base of alias names\n.br\n/etc/sendmail.cf\tconfiguration file\n.br\n/etc/sendmail.fc\tfrozen configuration\n.br\n/usr/share/misc/sendmail.hf\thelp file\n.br\n/var/log/sendmail.st\tcollected statistics\n.br\n/usr/spool/mqueue/*\ttemp files\n.SH SEE\\ ALSO\nmail(1), rmail(1),\nsyslog(3),\naliases(5), sendmail.cf(5),\nmailaddr(7),\nrc(8);\n.br\nDARPA Internet Request For Comments\nRFC819, RFC821, RFC822;\n.br\n.ul\nSendmail \\- An Internetwork Mail Router\n(SMM:16);\n.br\n.ul\nSendmail Installation and Operation Guide\n(SMM:7)\n"
  },
  {
    "path": "share/man/man8/sticky.8",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)sticky.8\t6.3 (Berkeley) 5/26/86\n.\\\"\n.TH STICKY 8 \"May 26, 1986\"\n.UC 4\n.SH NAME\nsticky \\- persistent text and append-only directories\n.SH DESCRIPTION\nThe\n.I \"sticky bit\"\n(file mode bit 01000, see\n.IR chmod (2))\nis used to indicate special treatment\nfor certain executable files and directories.\n.SH \"STICKY TEXT EXECUTABLE FILES\"\nWhile the `sticky bit'\nis set on a sharable executable file,\nthe text of that file will not be removed from the system swap area.\nThus the file does not have to be fetched from the file system\nupon each execution.\nShareable text segments are normally placed\nin a least-frequently-used cache after use,\nand thus the `sticky bit' has little effect on commonly-used text images.\n.PP\nSharable executable files are made by the\n.B \\-n\nand\n.B \\-z\noptions of\n.IR ld (1).\n.PP\nOnly the super-user can set the sticky bit\non a sharable executable file.\n.SH \"STICKY DIRECTORIES\"\nA directory whose `sticky bit' is set\nbecomes an append-only directory, or, more accurately,\na directory in which the deletion of files is restricted.\nA file in a sticky directory may only be removed or renamed\nby a user if the user has write permission for the directory and\nthe user is the owner of the file, the owner of the directory,\nor the super-user.\nThis feature is usefully applied to directories such as /tmp\nwhich must be publicly writable but\nshould deny users the license to arbitrarily\ndelete or rename each others' files.\n.PP\nAny user may create a sticky directory.\nSee\n.IR chmod (1)\nfor details about modifying file modes.\n.SH BUGS\nSince the text areas of sticky text executables are stashed in the swap area,\nabuse of the feature can cause a system to run out of swap.\n.PP\nNeither\n.IR open (2)\nnor\n.IR mkdir (2)\nwill create a file with the sticky bit set.\n"
  },
  {
    "path": "share/man/man8/sync.8",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)sync.8\t6.2.1 (2.11BSD) 1996/11/27\n.\\\"\n.TH SYNC 8 \"November 27, 1996\"\n.UC 4\n.SH NAME\nsync \\- update the super block\n.SH SYNOPSIS\n.B sync\n.SH DESCRIPTION\n.I Sync\nexecutes the\n.I sync\nsystem primitive.\n.I Sync\ncan be called to insure that all disk writes have been completed before the\nprocessor is halted in a way not suitably done by\n.IR reboot (8)\nor\n.IR halt (8).\nGenerally, it is preferable to use\n.I reboot\nor\n.I halt\nto shut down the system,\nas they may perform additional actions\nsuch as resynchronizing the hardware clock\nand flushing internal caches before performing a final\n.IR sync .\n.PP\nSee\n.IR sync (2)\nfor details on the system primitive.\n.SH \"SEE ALSO\"\nsync(2), fsync(2), halt(8), reboot(8), update(8)\n"
  },
  {
    "path": "share/man/man8/timed.8",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)timed.8\t6.1.1 (2.11BSD) 1996/11/17\n.\\\"\n.TH TIMED 8 \"November 17, 1996\"\n.UC 6\n.ad\n.SH NAME\ntimed \\- time server daemon\n.SH SYNOPSIS\n.B timed\n[ -t ] [ -M ] [ -n network ] [ -i network ]\n.SH DESCRIPTION\n.I Timed\nis the time server daemon and is normally invoked\nat boot time from the\n.IR rc (8)\nfile.  \nIt synchronizes the host's time with the time of other\nmachines in a local area network running \n.IR timed (8).\nThese time servers will slow down the clocks of some machines\nand speed up the clocks of others to bring them to the average network time.\nThe average network time is computed from measurements of clock differences\nusing the ICMP timestamp request message.\n.PP\nThe service provided by \\fItimed\\fP is based  on a master-slave\nscheme.\nWhen\n.IR timed (8)\nis started on a machine, it asks the master for the network time\nand sets the host's clock to that time.\nAfter that, it accepts synchronization messages periodically sent by\nthe master and calls \n.IR adjtime (2)\nto perform the needed corrections on the host's clock.\n.PP\nIt also communicates with\n.IR date (1)\nin order to set the date globally,\nand with \n.IR timedc (8),\na timed control program.\nIf the machine running the master crashes, then the slaves will elect\na new master from among slaves running with the \n.B \\-M\nflag.\nA\n.IR timed\nrunning without the\n.B \\-M\nflag will remain a slave.\nThe \n.B \\-t \nflag enables \\fItimed\\fP to trace the messages it receives in the\nfile /usr/adm/timed.log.\nTracing can be turned on or off by the program\n.IR timedc (8).\n.I Timed\nnormally checks for a master time server on each network to which\nit is connected, except as modified by the options described below.\nIt will request synchronization service from the first master server\nlocated.\nIf permitted by the\n.B \\-M\nflag, it will provide synchronization service on any attached networks\non which no current master server was detected.\nSuch a server propagates the time computed by the top-level master.\nThe \n.B \\-n \nflag, followed by the name of a network which the host is connected to\n(see\n.IR networks (5)),\noverrides the default choice of the\nnetwork addresses made by the program.\nEach time the\n.B \\-n\nflag appears, that network name is added to a list of valid networks.\nAll other networks are ignored.\nThe \n.B \\-i \nflag, followed by the name of a network to which the host is connected\n(see\n.IR networks (5)),\noverrides the default choice of the network addresses made by the program.\nEach time the\n.B \\-i\nflag appears, that network name is added to a list of networks to ignore.\nAll other networks are used by the time daemon.\nThe\n.B \\-n\nand \n.B \\-i\nflags are meaningless if used together.\n.SH FILES\n.nf\n.ta \\w'/usr/adm/timed.masterlog     'u\n/usr/adm/timed.log\t\ttracing file for timed\n/usr/adm/timed.masterlog\tlog file for master timed \n.fi\n.SH \"SEE ALSO\"\ndate(1), adjtime(2), gettimeofday(2), icmp(4P), timedc(8),\n.br\n\\fITSP: The Time Synchronization Protocol for UNIX 4.3BSD\\fP, \nR. Gusella and S. Zatti\n"
  },
  {
    "path": "share/man/man8/timedc.8",
    "content": "\n.\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)timedc.8\t6.1.1 (2.11BSD) 1996/11/17\n.\\\"\n.TH TIMEDC 8 \"November 17, 1996\"\n.UC 6\n.ad\n.SH NAME\ntimedc \\- timed control program\n.SH SYNOPSIS\n.B timedc\n[ command [ argument ... ] ]\n.SH DESCRIPTION\n.I Timedc\nis used to control the operation of the \\fItimed\\fP program.\nIt may be used to:\n.IP \\(bu\nmeasure the differences between machines' clocks,\n.IP \\(bu\nfind the location where the master time server is running,\n.IP \\(bu\nenable or disable tracing of messages received by \\fItimed\\fP, and\n.IP \\(bu\nperform various debugging actions.\n.PP\nWithout any arguments,\n.I timedc\nwill prompt for commands from the standard input.\nIf arguments are supplied,\n.IR timedc\ninterprets the first argument as a command and the remaining\narguments as parameters to the command.  The standard input\nmay be redirected causing\n.I timedc\nto read commands from a file.\nCommands may be abbreviated;\nrecognized commands are:\n.TP\n? [ command ... ]\n.TP\nhelp [ command ... ]\n.br\nPrint a short description of each command specified in the argument list,\nor, if no arguments are given, a list of the recognized commands.\n.TP\nclockdiff host ...\n.br\nCompute the differences between the clock of the host machine\nand the clocks of the machines given as arguments.\n.TP\ntrace { on | off }\n.br\nEnable or disable the tracing of incoming messages to \\fItimed\\fP\nin the file /usr/adm/timed.log.\n.TP\nquit\n.br\nExit from timedc.\n.PP\nOther commands may be included for use in testing and debugging\n.IR timed ;\nthe help command and\nthe program source may be consulted for details.\n.SH FILES\n.nf\n.ta \\w'/usr/adm/masterlog       'u\n/usr/adm/timed.log\t\ttracing file for timed\n/usr/adm/timed.masterlog\tlog file for master timed\n.fi\n.SH \"SEE ALSO\"\ndate(1), adjtime(2), icmp(4P), timed(8), \n.br\n\\fITSP: The Time Synchronization Protocol for UNIX 4.3BSD\\fP, \nR. Gusella and S. Zatti\n.SH DIAGNOSTICS\n.nf\n.ta \\w'?Ambiguous command      'u\n?Ambiguous command\tabbreviation matches more than one command\n?Invalid command\tno match found\n?Privileged command\tcommand can be executed by root only\n.fi\n"
  },
  {
    "path": "share/man/man8/uucico.8",
    "content": ".\\\"\t@(#)uucico.8\t6.3.1 (2.11BSD) 1996/10/23\n.\\\"\n.TH UUCICO 8 \"October 23, 1996\"\n.UC 6\n.SH NAME\nuucico, uucpd \\- transfer files queued by uucp or uux\n.SH SYNOPSIS\n.B /usr/sbin/uucico\n[\n.BI \\-d spooldir\n] [\n.BI \\-g grade\n] [\n.BI \\-r role\n] [\n.B \\-R\n] [\n.BI \\-s system\n] [\n.BI \\-x debug\n] [\n.B \\-L\n] [\n.BI \\-t turnaround\n]\n.PP\n.B /usr/libexec/uucpd\n.SH DESCRIPTION\n.I Uucico\nperforms the actual work involved in transferring files between\nsystems. \n.IR Uucp (1)\nand\n.IR uux (1)\nmerely queue requests for data transfer which\n.I uucico\nprocesses.\n.PP\nThe following options are available.\n.TP 8\n.BI \\-d spooldir\nUse\n.I spooldir\nas the spool directory. The default is /usr/spool/uucp.\n.TP 8\n.BI \\-g grade\nOnly send jobs of grade\n.I grade\nor higher this transfer.\nThe grade of a job is specified when the job is queued by\n.I uucp\nor\n.IR uux .\n.TP 8\n.BI \\-r role\n.I role\nis either 1 or 0; it indicates whether\n.I uucico\nis to start up in \nmaster or slave role, respectively. 1 is used when running \n.I uucico\nby hand or from\n.IR cron (8).\n0 is used when another system calls the local system.\nSlave role is the default.\n.TP 8\n.B \\-R\nReverse roles.  When used with the\n.B \\-r1\noption, this tells the remote system to begin sending its\njobs first, instead of waiting for the local machine to finish.\n.TP 8\n.BI \\-s system\nCall only system\n.IR system .\nIf \n.B \\-s\nis not specified, and \\-r1 is specified,\n.I uucico\nwill attempt to call all systems for which there is work.\nIf\n.B \\-s\nis specified, a call will be made even if there is\nno work for that system. This is useful for polling.\n.TP 8\n.BI \\-x debug\nTurn on debugging at level\n.IR debug .\nLevel 5 is a good start when trying to find out why a call\nfailed. Level 9 is very detailed. Level 99 is absurdly verbose.\nIf\n.I role\nis 1 (master), output is normally written to the standard message\noutput\n.IR stderr .\nIf\n.I stderr\nis unavailable, output is written to\n.RI /usr/spool/uucp/AUDIT/ system.\nWhen\n.I role\nis 0 (slave), debugging output is always written to the AUDIT\nfile.\n.TP 8\n.B \\-L\nOnly call ``local'' sites. A site is considered local if\nthe device-type field in \n.I L.sys\nis one of LOCAL, DIR or TCP.\n.TP 8\n.BI \\-t turnaround\nUse\n.I turnaround\nas the line turnaround time (in minutes) instead of the default 30.  If \n.I turnaround\nis missing or 0, line turnaround will be disabled.\nAfter\n.I uucico\nhas been running in slave role for\n.I turnaround \nminutes, it will attempt to run in master role by negotiating with the\nremote machine.\nIn earlier versions of\n.IR uucico ,\na transfer of many large files in one direction would hold up mail\ngoing in the other direction.\nWith the turnaround code working, the message flow will be more\nbidirectional in the short term.\nThis option only works with newer\n.IR uucico 's\nand is ignored by older ones.\n.PP\nIf\n.I uucico\nreceives a\n.B SIGFPE\n(see\n.IR kill (1)),\nit will toggle the debugging on or off.\n.PP\n.I Uucpd\nis the server for supporting uucp connections over networks.\n.I Uucpd\nlistens for service requests at the port indicated in the ``uucp''\nservice specification; see \\fIservices\\fP\\|(5).\nThe server provides login name and password authentication before starting up\n.I uucico\nfor the rest of the transaction.\n.PP\n.I Uucico\nis commonly used either of two ways: as a daemon run periodically by\n.IR cron (8)\nto call out to remote systems, and as a ``shell'' for remote systems\nwho call in.\nFor calling out periodically, a typical line in\n.I crontab\nwould be:\n.PP\n.nf\n\t0\t*\t*\t*\t*\t/usr/sbin/uucico -r1\n.fi\n.PP\nThis will run\n.I uucico\nevery hour in master role. \nFor each system that has transfer requests queued, \n.I uucico\ncalls the system, logs in, and executes the transfers. The file\n.IR L.sys (5)\nis consulted for information about how to log in, while\n.IR L-devices (5)\nspecifies available lines and modems for calling.\n.PP\nFor remote systems to dial in, an entry in the\n.IR passwd (5)\nfile must be created, with a login ``shell'' of\n.IR uucico .\nFor example:\n.PP\n.nf\n\tnuucp:Password:6:1::/usr/spool/uucppublic:/usr/sbin/uucico\n.fi\n.PP\nThe UID for UUCP remote logins is not critical, so long as it differs from\nthe UUCP Administrative login.\nThe latter owns the UUCP files, and assigning\nthis UID to a remote login would be an extreme security hazard. \n.SH FILES\n.ta \\w'/usr/spool/uucp/D.hostnameX/  'u\n.nf\n/etc/uucp/\tUUCP internal files\n/etc/uucp/L-devices\tLocal device descriptions\n/etc/uucp/L-dialcodes\tPhone numbers and prefixes\n/etc/uucp/L.aliases\tHostname aliases\n/etc/uucp/L.cmds\tRemote command permissions list\n/etc/uucp/L.sys\tHost connection specifications\n/etc/uucp/USERFILE\tRemote directory tree permissions list\n.PP\n/usr/spool/uucp/\tSpool directory\n/usr/spool/uucp/AUDIT/*\tDebugging audit trails\n/usr/spool/uucp/C./\tControl files directory\n/usr/spool/uucp/D./\tIncoming data file directory\n/usr/spool/uucp/D.hostname/\tOutgoing data file directory\n/usr/spool/uucp/D.hostnameX/\tOutgoing execution file directory\n/usr/spool/uucp/CORRUPT/\tPlace for corrupted C. and D. files\n/usr/spool/uucp/ERRLOG\tUUCP internal error log\n/usr/spool/uucp/LOGFILE\tUUCP system activity log\n/usr/spool/uucp/LCK/LCK..*\tDevice lock files\n/usr/spool/uucp/SYSLOG\tFile transfer statistics log\n/usr/spool/uucp/STST/*\tSystem status files\n/usr/spool/uucp/TM./\tFile transfer temp directory\n/usr/spool/uucp/X./\tIncoming execution file directory\n.PP\n/usr/spool/uucppublic\tPublic access directory\n.fi\n.SH SEE ALSO\nuucp(1), uuq(1), uux(1), L-devices(5), L-dialcodes(5), L.aliases(5),\nL.cmds(5), L.sys(5), uuclean(8), uupoll(8), uusnap(8), uuxqt(8)\n.PP\nD. A. Nowitz and M. E. Lesk,\n.IR \"A Dial-Up Network of UNIX Systems\" .\n.PP\nD. A. Nowitz,\n.IR \"Uucp Implementation Description\" .\n"
  },
  {
    "path": "share/man/man8/uuclean.8",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)uuclean.8\t6.3.1 (2.11BSD) 1996/10/23\n.\\\"\n.TH UUCLEAN 8 \"October 23, 1996\"\n.UC 5\n.SH NAME\nuuclean \\- uucp spool directory clean-up\n.SH SYNOPSIS\n.B /etc/uucp/uuclean\n[\n.B -m\n] [\n.BI -n time\n] [\n.BI -p pre\n]\n.SH DESCRIPTION\n.I Uuclean\nwill scan the spool directory for files with the\nspecified prefix and delete all those which are\nolder than the specified number of hours.\n.PP\nThe following options are available.\n.TP 8\n.BI \\-p pre\nScan for files with\n.I pre\nas the file prefix.\nUp to 10\n.B \\-p\narguments may be specified.\n.TP\n.BI \\-n time\nFiles whose age is more than\n.I time\nhours will be deleted if the prefix\ntest is satisfied.\n(default time is 72 hours)\n.TP 8\n.B \\-m\nSend mail to the owner of the file\nwhen it is deleted.\n.TP\n.BI \\-d subdirectory\nOnly the specified subdirectory will be cleaned.\n.PP\nThis program will typically be run daily by\n.IR cron (8).\n.SH FILES\n.TP 22\n/usr/spool/uucp\nSpool directory\n.SH SEE ALSO\nuucp(1), uux(1), uucico(8)\n"
  },
  {
    "path": "share/man/man8/uupoll.8",
    "content": ".\\\" Copyright (c) 1986 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)uupoll.8\t6.1.1 (2.11BSD) 1996/10/23\n.\\\"\n.TH UUPOLL 8 \"October 23, 1996\"\n.UC 6\n.SH NAME\nuupoll \\- poll a remote \\s-1UUCP\\s+1 site\n.SH SYNOPSIS\n.B uupoll\n[\n.BI \\-g grade\n] [\n.B \\-n\n]\n.I system\n.SH DESCRIPTION\n.I Uupoll\nis used to force a poll of a remote system. It queues a null job for the\nremote system and then invokes\n.IR uucico (8).\n.PP\nThe following options are available:\n.TP 8\n.BI \\-g grade\nOnly send jobs of grade\n.I grade\nor higher on this call.\n.TP 8\n.B \\-n\nQueue the null job, but do not invoke\n.IR uucico .\n.PP\n.I Uupoll\nis usually run by\n.IR cron (5)\nor by a user who wants to hurry a job along. A typical entry in\n.I crontab\ncould be:\n.PP\n.nf\n\t0\t0,8,16\t*\t*\t*\t/usr/bin/uupoll ihnp4\n\t0\t4,12,20\t*\t*\t*\t/usr/bin/uupoll ucbvax\n.fi\nThis will poll\n.B ihnp4\nat midnight, 0800, and 1600, and\n.B ucbvax\nat 0400, noon, and 2000.\n.PP\nIf the local machine is already running\n.I uucico\nevery\nhour and has a limited number of outgoing modems, a more elegant approach\nmight be:\n.PP\n.nf\n\t0\t0,8,16\t*\t*\t*\t/usr/bin/uupoll -n ihnp4\n\t0\t4,12,20\t*\t*\t*\t/usr/bin/uupoll -n ucbvax\n\t5\t*\t\t*\t*\t*\t/usr/sbin/uucico -r1\n.fi\nThis will queue null jobs for the remote sites at the top of hour; they\nwill be processed by\n.I uucico\nwhen it runs five minutes later.\n.SH FILES\n.ta \\w'/usr/spool/uucp/   'u\n.nf\n/etc/uucp/\tUUCP internal files\n/usr/spool/uucp/\tSpool directory\n.fi\n.SH SEE ALSO\nuucp(1), uux(1), uucico(8)\n"
  },
  {
    "path": "share/man/man8/uusnap.8",
    "content": ".\\\" Copyright (c) 1983 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)uusnap.8c\t6.2 (Berkeley) 4/24/86\n.\\\"\n.TH UUSNAP 8C \"April 24, 1986\"\n.UC 5\n.SH NAME\nuusnap \\- show snapshot of the UUCP system\n.SH SYNOPSIS\n.B uusnap\n.SH DESCRIPTION\n.I Uusnap\ndisplays in tabular format a synopsis of the current UUCP\nsituation.  The format of each line is as follows:\n.PP\n.ti +10\nsite   N Cmds   N Data   N Xqts   Message\n.PP\nWhere \"site\" is the name of the site with work, \"N\" is a count of\neach of the three possible types of work (command, data, or remote execute),\nand \"Message\" is the current status message for that\nsite as found in the STST file.\n.PP\nIncluded in \"Message\" may be the time left before UUCP can re-try the\ncall, and the count of the number of times that UUCP has tried\n(unsuccessfully) to reach the site.\n.SH SEE ALSO\nuucp(1C), uux(1C), uuq(1C), uucico(8C)\n.br\n.I \"UUCP Implementation Guide\"\n"
  },
  {
    "path": "share/man/man8/uuxqt.8",
    "content": ".\\\" Copyright (c) 1980 Regents of the University of California.\n.\\\" All rights reserved.  The Berkeley software License Agreement\n.\\\" specifies the terms and conditions for redistribution.\n.\\\"\n.\\\"\t@(#)uuxqt.8\t6.1.1 (2.11BSD) 1996/10/23\n.\\\"\n.TH UUXQT 8 \"October 23, 1996\"\n.UC 6\n.SH NAME\nuuxqt \\- \\s-1UUCP\\s+1 execution file interpreter\n.SH SYNOPSIS\n.B /usr/libexec/uuxqt\n[\n.BI \\-x debug\n]\n.SH DESCRIPTION\n.I Uuxqt\ninterprets\n.I \"execution files\"\ncreated on a remote system via\n.IR uux (1)\nand transferred to the local system via\n.IR uucico (8).\nWhen a user uses\n.I uux\nto request remote command execution, it is\n.I uuxqt\nthat actually executes the command. \nNormally,\n.I uuxqt\nis forked from\n.I uucico\nto process queued execution files;\nfor debugging, it may also be run manually by the \\s-1UUCP\\s+1 administrator.\n.PP\n.I Uuxqt\nruns in its own subdirectory,\n.IR /usr/spool/uucp/XTMP .\nIt copies intermediate files to this directory when necessary.\n.SH FILES\n.ta \\w'/usr/spool/uucp/LCK/LCK.XQT   'u\n.nf\n/etc/uucp/L.cmds\tRemote command permissions list\n/etc/uucp/USERFILE\tRemote directory tree permissions list\n/usr/spool/uucp/LOGFILE\tUUCP system activity log\n/usr/spool/uucp/LCK/LCK.XQT\t\\fIUuxqt\\fP lock file\n/usr/spool/uucp/X./\tIncoming execution file directory\n/usr/spool/uucp/XTMP\t\\fIUuxqt\\fP running directory\n.fi\n.SH SEE ALSO\nuucp(1), uux(1), L.cmds(5), USERFILE(5), uucico(8)\n"
  },
  {
    "path": "share/man/man9/Makefile",
    "content": "#\n# Copyright (c) 1987 Regents of the University of California.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms are permitted\n# provided that the above copyright notice and this paragraph are\n# duplicated in all such forms and that any documentation,\n# advertising materials, and other materials related to such\n# distribution and use acknowledge that the software was developed\n# by the University of California, Berkeley.  The name of the\n# University may not be used to endorse or promote products derived\n# from this software without specific prior written permission.\n# THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n# IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n# WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n#\n#\t@(#)Makefile\t5.4.1 (2.11BSD) 1996/01/26\n#\nTOPSRC!=cd ../../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nMDIR=\t/usr/share/man/cat9\nSRCS=\tintro.9 style.9\nOBJS=\tintro.0 style.0\n\n.SUFFIXES: .9 .0\n\n.9.0:\n\t${MANROFF} $*.9 > $*.0\n\nall: _make_01\n\n_make_01: ${OBJS}\n\nclean: FRC\n\trm -f ${OBJS}\n\ninstall: _make_01\n\tcp ${OBJS} ${DESTDIR}${MDIR}\n\nFRC:\n"
  },
  {
    "path": "share/man/man9/intro.9",
    "content": ".\\\"\t$OpenBSD: intro.9,v 1.14 2018/09/30 13:24:33 schwarze Exp $\n.\\\"\n.\\\" Copyright (c) 1996 Michael Shalayeff\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.Dd April 22, 2025\n.Dt INTRO 9\n.Os\n.Sh NAME\n.Nm intro\n.Nd introduction to the kernel internals\n.Sh DESCRIPTION\nThe manual pages in section 9 contain information related to the\ninternal kernel data structures, variables and functions.\n.Sh CODE REFERENCES\nThis section describes places within the\n.Bx Disco\nsource tree where actual code implementing or using kernel internals\ncan be found.\nAll pathnames are relative to\n.Pa /usr/src .\n.Sh HISTORY\nAn\n.Nm\nmanual for section 9 appeared in\n.Bx Disco\n2.5.\n"
  },
  {
    "path": "share/man/man9/style.9",
    "content": ".\\\" Copyright (c) 1995 FreeBSD Inc.\n.\\\" All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL [your name] OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"\t$OpenBSD: style.9,v 1.79 2022/09/11 06:38:11 jmc Exp $\n.\\\"\n.Dd $Mdocdate: September 11 2022 $\n.Dt STYLE 9\n.Os\n.Sh NAME\n.Nm style\n.Nd Kernel source file style guide (KNF)\n.Sh DESCRIPTION\nThis file specifies the preferred style for kernel source files in the\n.Ox\nsource tree.\nIt is also a guide for preferred userspace code style.\nThese guidelines should be followed for all new code.\nIn general, code can be considered\n.Dq new code\nwhen it makes up about 50% or more of the file(s) involved.\nThis is enough to break precedents in the existing code and use the\ncurrent style guidelines.\n.Bd -literal -offset indent\n/*\n * Style guide for the OpenBSD KNF (Kernel Normal Form).\n */\n\n/*\n * VERY important single-line comments look like this.\n */\n\n/* Most single-line comments look like this. */\n\n/*\n * Multi-line comments look like this.  Make them real sentences.\n * Fill them so they look like real paragraphs.\n */\n.Ed\n.Pp\nKernel include files (i.e.,\n.In sys/*.h )\ncome first; normally, you'll need\n.In sys/types.h\nOR\n.In sys/param.h ,\nbut not both!\n.In sys/types.h\nincludes\n.In sys/cdefs.h ,\nand it's okay to depend on that.\n.Bd -literal -offset indent\n#include <sys/types.h>\t/* Non-local includes in brackets. */\n.Ed\n.Pp\nIf it's a network program, put the network include files next.\n.Bd -literal -offset indent\n#include <net/if.h>\n#include <net/if_dl.h>\n#include <net/route.h>\n#include <netinet/in.h>\n.Ed\n.Pp\nThen there's a blank line, followed by the\n.Pa /usr/include\nfiles.\nThe\n.Pa /usr/include\nfiles, for the most part, should be sorted.\n.Pp\nGlobal pathnames are defined in\n.Pa /usr/include/paths.h .\nPathnames local to the program go in\n.Pa pathnames.h\nin the local directory.\n.Bd -literal -offset indent\n#include <paths.h>\n.Ed\n.Pp\nThen there's a blank line, and the user include files.\n.Bd -literal -offset indent\n#include \"pathnames.h\"\t/* Local includes in double quotes. */\n.Ed\n.Pp\nAll non-static functions are prototyped somewhere.\n.Pp\nFunction prototypes for private functions (i.e., functions not used\nelsewhere) go at the top of the first source module.\nIn the kernel, private functions do not require a prototype as long\nas they are defined before they are used.\nIn userspace, functions local to one source module should be declared\n.Ql static .\nThis should not be done in the kernel since it makes it impossible\nto use the kernel debugger.\n.Pp\nFunctions used from other files are prototyped in the\nrelevant include file.\n.Pp\nFunctions that are used locally in more than one module go into a\nseparate header file, e.g.,\n.Pa extern.h .\n.Pp\nPrototypes should not have variable names associated with the types; i.e.,\n.Bd -literal -offset indent\nvoid\tfunction(int);\n.Ed\nnot:\n.Bd -literal -offset indent -compact\nvoid\tfunction(int a);\n.Ed\n.Pp\nPrototypes may have an extra space after a tab to enable function names\nto line up:\n.Bd -literal -offset indent\nstatic char\t*function(int, const char *);\nstatic void\t usage(void);\n.Ed\n.Pp\nThere should be no space between the function name and the argument list.\n.Pp\nUse\n.Li __dead\nfrom\n.In sys/cdefs.h\nfor functions that don't return, i.e.,\n.Bd -literal -offset indent\n__dead void\tabort(void);\n.Ed\n.Pp\nIn header files, put function prototypes within\n.Dv __BEGIN_DECLS / __END_DECLS\nmatching pairs.\nThis makes the header file usable from C++.\n.Pp\nMacros are capitalized and parenthesized, and should avoid side-effects.\nIf they are an inline expansion of a function, the function is defined\nall in lowercase; the macro has the same name all in uppercase.\nIf the macro needs more than a single line, use braces.\nRight-justify the backslashes, as the resulting definition is easier to read.\nIf the macro encapsulates a compound statement, enclose it in a\n.Dq Li do\nloop,\nso that it can safely be used in\n.Dq Li if\nstatements.\nAny final statement-terminating semicolon should be\nsupplied by the macro invocation rather than the macro, to make parsing easier\nfor pretty-printers and editors.\n.Bd -literal -offset indent\n#define\tMACRO(x, y) do {\t\t\t\t\t\\e\n\tvariable = (x) + (y);\t\t\t\t\t\\e\n\t(y) += 2;\t\t\t\t\t\t\\e\n} while (0)\n.Ed\n.Pp\nIf a macro with arguments declares local variables,\nthose variables should use identifiers beginning with two underscores.\nThis is required for macros implementing C and POSIX interfaces\nand recommended for all macros for consistency.\n.Pp\nEnumeration values are all uppercase.\n.Bd -literal -offset indent\nenum enumtype { ONE, TWO } et;\n.Ed\n.Pp\nWhen defining unsigned integers, use\n.Dq \"unsigned int\"\nrather than just\n.Dq \"unsigned\" ;\nthe latter has been a source of confusion in the past.\n.Pp\nWhen declaring variables in structures, declare them sorted by use, then\nby size (largest to smallest), then by alphabetical order.\nThe first category normally doesn't apply, but there are exceptions.\nEach one gets its own line.\nPut a tab after the first word, i.e., use\n.Ql int^Ix;\nand\n.Ql struct^Ifoo *x; .\n.Pp\nMajor structures should be declared at the top of the file in which they\nare used, or in separate header files if they are used in multiple\nsource files.\nUse of the structures should be by separate declarations and should be\n.Dq Li extern\nif they are declared in a header file.\n.Bd -literal -offset indent\nstruct foo {\n\tstruct\tfoo *next;\t/* List of active foo */\n\tstruct\tmumble amumble;\t/* Comment for mumble */\n\tint\tbar;\n};\nstruct foo *foohead;\t\t/* Head of global foo list */\n.Ed\n.Pp\nUse\n.Xr queue 3\nmacros rather than rolling your own lists, whenever possible.\nThus, the previous example would be better written:\n.Bd -literal -offset indent\n#include <sys/queue.h>\nstruct\tfoo {\n\tLIST_ENTRY(foo)\tlink;\t/* Queue macro glue for foo lists */\n\tstruct\tmumble amumble;\t/* Comment for mumble */\n\tint\tbar;\n};\nLIST_HEAD(, foo) foohead;\t/* Head of global foo list */\n.Ed\n.Pp\nAvoid using typedefs for structure types.\nThis makes it impossible\nfor applications to use pointers to such a structure opaquely, which\nis both possible and beneficial when using an ordinary struct tag.\nWhen convention requires a typedef, make its name match the struct tag.\nAvoid typedefs ending in\n.Dq Li \\&_t ,\nexcept as specified in Standard C or by POSIX.\n.Bd -literal -offset indent\n/*\n * All major routines should have a comment briefly describing what\n * they do.  The comment before the \"main\" routine should describe\n * what the program does.\n */\nint\nmain(int argc, char *argv[])\n{\n\tint aflag, bflag, ch, num;\n\tconst char *errstr;\n.Ed\n.Pp\nFor consistency,\n.Xr getopt 3\nshould be used to parse options.\nOptions should be sorted in the\n.Xr getopt 3\ncall and the switch statement, unless\nparts of the switch cascade.\nElements in a switch statement that cascade should have a FALLTHROUGH comment.\nNumerical arguments should be checked for accuracy.\n.Bd -literal -offset indent\nwhile ((ch = getopt(argc, argv, \"abn:\")) != -1) {\n\tswitch (ch) {\t\t/* Indent the switch. */\n\tcase 'a':\t\t/* Don't indent the case. */\n\t\taflag = 1;\n\t\t/* FALLTHROUGH */\n\tcase 'b':\n\t\tbflag = 1;\n\t\tbreak;\n\tcase 'n':\n\t\tnum = strtonum(optarg, 0, INT_MAX, &errstr);\n\t\tif (errstr) {\n\t\t\twarnx(\"number is %s: %s\", errstr, optarg);\n\t\t\tusage();\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tusage();\n\t}\n}\nargc -= optind;\nargv += optind;\n.Ed\n.Pp\nUse a space after keywords\n.Pf ( Li if ,\n.Li while ,\n.Li for ,\n.Li return ,\n.Li switch ) .\nNo braces are\nused for control statements with zero or only a single statement unless that\nstatement is more than a single line, in which case they are permitted.\n.Bd -literal -offset indent\nfor (p = buf; *p != '\\e0'; ++p)\n\tcontinue;\nfor (;;)\n\tstmt;\nfor (;;) {\n\tz = a + really + long + statement + that + needs +\n\t    two + lines + gets + indented + four + spaces +\n\t    on + the + second + and + subsequent + lines;\n}\nfor (;;) {\n\tif (cond)\n\t\tstmt;\n}\n.Ed\n.Pp\nParts of a for loop may be left empty.\n.Bd -literal -offset indent\nfor (; cnt < 15; cnt++) {\n\tstmt1;\n\tstmt2;\n}\n.Ed\n.Pp\nIndentation is an 8 character tab.\nSecond level indents are four spaces.\nAll code should fit in 80 columns.\n.Bd -literal -offset indent\nwhile (cnt < 20)\n\tz = a + really + long + statement + that + needs +\n\t    two + lines + gets + indented + four + spaces +\n\t    on + the + second + and + subsequent + lines;\n.Ed\n.Pp\nDo not add whitespace at the end of a line, and only use tabs\nfollowed by spaces to form the indentation.\nDo not use more spaces than a tab will produce\nand do not use spaces in front of tabs.\n.Pp\nClosing and opening braces go on the same line as the else.\nBraces that aren't necessary may be left out, unless they cause\na compiler warning.\n.Bd -literal -offset indent\nif (test)\n\tstmt;\nelse if (bar) {\n\tstmt;\n\tstmt;\n} else\n\tstmt;\n.Ed\n.Pp\nDo not use spaces after function names.\nCommas have a space after them.\nDo not use spaces after\n.Sq \\&(\nor\n.Sq \\&[\nor preceding\n.Sq \\&]\nor\n.Sq \\&)\ncharacters.\n.Bd -literal -offset indent\nif ((error = function(a1, a2)))\n\texit(error);\n.Ed\n.Pp\nUnary operators don't require spaces; binary operators do.\nDon't use parentheses unless they're required for precedence, the statement\nis confusing without them, or the compiler generates a warning without them.\nRemember that other people may be confused more easily than you.\nDo YOU understand the following?\n.Bd -literal -offset indent\na = b->c[0] + ~d == (e || f) || g && h ? i : j >> 1;\nk = !(l & FLAGS);\n.Ed\n.Pp\nExits should be 0 on success, or non-zero for errors.\n.Bd -literal -offset indent\n/*\n * Avoid obvious comments such as\n * \"Exit 0 on success.\"\n */\nexit(0);\n.Ed\n.Pp\nThe function type should be on a line by itself\npreceding the function.\n.Bd -literal -offset indent\nstatic char *\nfunction(int a1, int a2, float fl, int a4)\n{\n.Ed\n.Pp\nWhen declaring variables in functions, declare them sorted by size (largest to\nsmallest), then in alphabetical order; multiple ones per line are okay.\nIf a line overflows, reuse the type keyword.\n.Pp\nBe careful not to obfuscate the code by initializing variables in\nthe declarations.\nUse this feature only thoughtfully.\nDO NOT use function calls in initializers!\n.Bd -literal -offset indent\nstruct foo one, *two;\ndouble three;\nint *four, five;\nchar *six, seven, eight, nine, ten, eleven, twelve;\n\nfour = myfunction();\n.Ed\n.Pp\nDo not declare functions inside other functions.\n.Pp\nCasts and\n.Fn sizeof\ncalls are not followed by a space.\nNote that\n.Xr indent 1\ndoes not understand this rule.\n.Pp\nUse of the\n.Dq register\nspecifier is discouraged in new code.\nOptimizing compilers such as gcc can generally do a better job\nof choosing which variables to place in registers to improve\ncode performance.\nThe exception to this is in functions containing assembly code where the\n.Dq register\nspecifier is required for proper code generation in the absence of\ncompiler optimization.\n.Pp\nWhen using\n.Fn longjmp\nor\n.Fn vfork\nin a program, the\n.Fl W\nor\n.Fl Wall\nflag should be used to verify that the compiler does not generate\nwarnings such as\n.Bd -literal -offset indent\nwarning: variable `foo' might be clobbered by `longjmp' or `vfork'.\n.Ed\n.Pp\nIf any warnings of this type occur, you must apply the\n.Dq volatile\ntype-qualifier to the variable in question.\nFailure to do so may result in improper code generation when optimization\nis enabled.\nNote that for pointers, the location of\n.Dq volatile\nspecifies if the type-qualifier applies to the pointer, or the thing being\npointed to.\nA volatile pointer is declared with\n.Dq volatile\nto the right of the\n.Dq * .\nExample:\n.Bd -literal -offset indent\nchar *volatile foo;\n.Ed\n.Pp\nsays that\n.Dq foo\nis volatile, but\n.Dq *foo\nis not.\nTo make\n.Dq *foo\nvolatile use the syntax\n.Bd -literal -offset indent\nvolatile char *foo;\n.Ed\n.Pp\nIf both the pointer and the thing pointed to are volatile, use\n.Bd -literal -offset indent\nvolatile char *volatile foo;\n.Ed\n.Pp\n.Dq const\nis also a type-qualifier and the same rules apply.\nThe description of a read-only hardware register might look something like:\n.Bd -literal -offset indent\nconst volatile char *reg;\n.Ed\n.Pp\nGlobal flags set inside signal handlers should be of type\n.Dq volatile sig_atomic_t\nif possible.\nThis guarantees that the variable may be accessed as an atomic entity,\neven when a signal has been delivered.\nGlobal variables of other types (such as structures) are not\nguaranteed to have consistent values when accessed via a signal handler.\n.Pp\n.Dv NULL\nis the preferred null pointer constant.\nUse\n.Dv NULL\ninstead of\n(type\\ *)0 or (type\\ *)NULL in all cases except for arguments to variadic\nfunctions where the compiler does not know the type.\n.Pp\nDon't use\n.Ql \\&!\nfor tests unless it's a boolean, i.e., use\n.Bd -literal -offset indent\nif (*p == '\\e0')\n.Ed\nnot\n.Bd -literal -offset indent -compact\nif (!*p)\n.Ed\n.Pp\nRoutines returning\n.Vt void *\nshould not have their return values cast to any pointer type.\n.Pp\nUse the\n.Xr err 3\nand\n.Xr warn 3\nfamily of functions.\nDon't roll your own!\n.Bd -literal -offset indent\nif ((four = malloc(sizeof(struct foo))) == NULL)\n\terr(1, NULL);\nif ((six = (int *)overflow()) == NULL)\n\terrx(1, \"Number overflowed.\");\nreturn eight;\n.Ed\n.Pp\nAlways use ANSI function definitions.\nLong parameter lists are wrapped with a normal four space indent.\n.Pp\nVariable numbers of arguments should look like this:\n.Bd -literal -offset indent\n#include <stdarg.h>\n\nvoid\nvaf(const char *fmt, ...)\n{\n\tva_list ap;\n\tva_start(ap, fmt);\n\n\tSTUFF;\n\n\tva_end(ap);\n\n\t/* No return needed for void functions. */\n}\n\nstatic void\nusage(void)\n{\n.Ed\n.Pp\nUsage statements should take the same form as the synopsis in manual pages.\nOptions without\noperands come first, in alphabetical order inside a single set of\nbraces, followed by options with operands, in alphabetical order,\neach in braces, followed by required arguments in the order they\nare specified, followed by optional arguments in the order they\nare specified.\n.Pp\nA bar\n.Pq Sq \\&|\nseparates either-or options/arguments,\nand multiple options/arguments which are specified together are\nplaced in a single set of braces.\n.Pp\nIf numbers are used as options, they should be placed first,\nas shown in the example below.\nUppercase letters take precedence over lowercase.\n.Bd -literal -offset indent\n\"usage: f [-12aDde] [-b b_arg] [-m m_arg] req1 req2 [opt1 [opt2]]\\en\"\n\"usage: f [-a | -b] [-c [-de] [-n number]]\\en\"\n.Ed\n.Pp\nThe\n.Xr getprogname 3\nfunction may be used instead of hard-coding the program name.\n.Bd -literal -offset indent\nfprintf(stderr, \"usage: %s [-ab]\\en\", getprogname());\nexit(1);\n.Ed\n.Pp\nNew core kernel code should be reasonably compliant with the style guides.\nThe guidelines for third-party maintained modules and device drivers are more\nrelaxed but at a minimum should be internally consistent with their style.\n.Pp\nWhenever possible, code should be run through a code checker\n(e.g.,\n.Dq Li gcc -Wall -W -Wpointer-arith -Wbad-function-cast ...\\&\nor splint from the ports tree) and produce minimal warnings.\nSince lint has been removed, the only lint-style comment that should\nbe used is FALLTHROUGH, as it's useful to humans.\nOther lint-style comments such as ARGSUSED, LINTED, and NOTREACHED\nmay be deleted.\n.Pp\nNote that documentation follows its own style guide,\nas documented in\n.Xr mdoc 7 .\n.Sh FILES\n.Bl -tag -width \"/usr/share/misc/license.template \" -compact\n.It Pa /usr/share/misc/license.template\nExample license for new code.\n.El\n.Sh SEE ALSO\n.Xr indent 1 ,\n.Xr err 3 ,\n.Xr queue 3 ,\n.Xr warn 3 ,\n.Xr mdoc 7\n.Sh HISTORY\nThis man page is largely based on the src/admin/style/style file from the\n.Bx 4.4 Lite2\nrelease, with updates to reflect the current practice and\ndesire of the\n.Ox\nproject.\n"
  },
  {
    "path": "share/man/manroff",
    "content": "#!/bin/sh -\n#\n# Copyright (c) 1988 Regents of the University of California.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms are permitted\n# provided that the above copyright notice and this paragraph are\n# duplicated in all such forms and that any documentation,\n# advertising materials, and other materials related to such\n# distribution and use acknowledge that the software was developed\n# by the University of California, Berkeley.  The name of the\n# University may not be used to endorse or promote products derived\n# from this software without specific prior written permission.\n# THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR\n# IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED\n# WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n#\n#\t@(#)manroff\t5.1 (Berkeley) 7/14/88\n#\n\nnroff -man -h $*\n"
  },
  {
    "path": "share/misc/Makefile",
    "content": "#\n# Public domain - 1996/10/21 - sms\n#\n#  Makefile for misc data files\n#\nTOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nSRCS\t\t=\n# eign Mail.help Mail.tildehelp units gprof.callg gprof.flat \\\n# vlpmacs mkproto.data\n\nall:\t\t${SRCS}\n\ninstall:\t${SRCS}\n\t\t-mkdir -p ${DESTDIR}/usr/share/misc\n\t\t-chmod a+r,a+x ${DESTDIR}/usr/share/misc\n#\t\t${INSTALL} -c -m 444 ${SRCS} ${DESTDIR}/usr/share/misc\n\nclean:\n\t\trm -f *~\n"
  },
  {
    "path": "share/mk/sys.mk",
    "content": "# Override the default port with:\n# $ make MACHINE=pic32 MACHINE_ARCH=mips\n#\nMACHINE=\tstm32\nMACHINE_ARCH=\tarm\n\nunix=\t\tWe run DiscoBSD.\nOSMAJOR=\t2\nOSMINOR=\t6\nOSREV=\t\t${OSMAJOR}.${OSMINOR}\nOSRev=\t\t${OSMAJOR}_${OSMINOR}\nOSrev=\t\t${OSMAJOR}${OSMINOR}\n\nDESTDIR?=\t${TOPSRC}/distrib/obj/destdir.${MACHINE}\nRELEASE=\t${OSREV}\nBUILD!=\t\tgit rev-list HEAD --count\nVERSION=\t${RELEASE}-${BUILD}\n\nTOOLDIR?=\t${TOPSRC}/tools\nTOOLBINDIR?=\t${TOOLDIR}/bin\n\nHOST_CC?=\tcc\n\n_HOST_OSNAME!=\tuname -s\n\n# libbsd-dev package on Linux in overlay mode.\n_LIBBSD_CFLAGS!=if [ x\"${_HOST_OSNAME}\" = x\"Linux\" ] ; then \\\n\t\t\tpkg-config libbsd-overlay --cflags ; \\\n\t\telse \\\n\t\t\techo \"\" ; \\\n\t\tfi\n\n_LIBBSD_LIBS!=\tif [ x\"${_HOST_OSNAME}\" = x\"Linux\" ] ; then \\\n\t\t\tpkg-config libbsd-overlay --libs ; \\\n\t\telse \\\n\t\t\techo \"\" ; \\\n\t\tfi\n\nGCCPREFIX!=if [ x\"${MACHINE_ARCH}\" = x\"arm\" ] ; then \\\n\t\tif [ x\"${_HOST_OSNAME}\" = x\"OpenBSD\" ] ; then \\\n\t\t\techo \"/usr/local/bin/arm-none-eabi\" ; \\\n\t\telif [ x\"${_HOST_OSNAME}\" = x\"FreeBSD\" ] ; then \\\n\t\t\techo \"/usr/local/gcc-arm-embedded/bin/arm-none-eabi\" ; \\\n\t\telif [ x\"${_HOST_OSNAME}\" = x\"Linux\" ] ; then \\\n\t\t\techo \"/usr/bin/arm-none-eabi\" ; \\\n\t\telse \\\n\t\t\techo \"/does/not/exist\" ; \\\n\t\tfi \\\n\telif [ x\"${MACHINE_ARCH}\" = x\"mips\" ] ; then \\\n\t\tif [ x\"${_HOST_OSNAME}\" = x\"OpenBSD\" ] ; then \\\n\t\t\techo \"/usr/local/bin/mips-elf\" ; \\\n\t\telif [ x\"${_HOST_OSNAME}\" = x\"FreeBSD\" ] ; then \\\n\t\t\techo \"/usr/local/mips-elf/bin/mips-elf\" ; \\\n\t\telif [ x\"${_HOST_OSNAME}\" = x\"Linux\" ] ; then \\\n\t\t\techo \"/usr/local/mips-gcc-4.8.1/bin/mips-elf\" ; \\\n\t\telse \\\n\t\t\techo \"/does/not/exist\" ; \\\n\t\tfi \\\n\telse \\\n\t\techo \"/does/not/exist\" ; \\\n\tfi\n\nCC!=\tif [ x\"${MACHINE_ARCH}\" = x\"arm\" ] ; then \\\n\t\techo \"${GCCPREFIX}-gcc -mcpu=cortex-m4 -mabi=aapcs -mlittle-endian -mthumb -mfloat-abi=soft -nostdinc -I${TOPSRC}/include ${INCLUDES}\" ; \\\n\telif [ x\"${MACHINE_ARCH}\" = x\"mips\" ] ; then \\\n\t\techo \"${GCCPREFIX}-gcc -mips32r2 -EL -msoft-float -nostdinc -I${TOPSRC}/include ${INCLUDES}\" ; \\\n\telse \\\n\t\techo \"/does/not/exist\" ; \\\n\tfi\n\n# Enable mips16e instruction set by default\nCOPTS!=if [ x\"${MACHINE_ARCH}\" = x\"arm\" ] ; then \\\n\t\techo \"-Os -fcommon\" ; \\\n\telif [ x\"${MACHINE_ARCH}\" = x\"mips\" ] ; then \\\n\t\techo \"-Os -fcommon -mips16\" ; \\\n\telse \\\n\t\techo \"\" ; \\\n\tfi\n\nLDWARN!=if [ x\"${MACHINE_ARCH}\" = x\"arm\" ] ; then \\\n\t\tif [ x\"${_HOST_OSNAME}\" = x\"FreeBSD\" ] ; then \\\n\t\t\techo \"\" ; \\\n\t\telse \\\n\t\t\techo \"-Wl,--no-warn-rwx-segments\" ; \\\n\t\tfi \\\n\telse \\\n\t\techo \"-Wl,--no-warn-rwx-segments\" ; \\\n\tfi\n\nCFLAGS=\t${COPTS}\n\nAFLAGS=\t${ASFLAGS}\n\nLDFLAGS=-N -nostartfiles -fno-dwarf2-cfi-asm \\\n\t${LDWARN} \\\n\t-T${TOPSRC}/lib/elf32-${MACHINE_ARCH}.ld \\\n\t${TOPSRC}/lib/crt0.o -L${TOPSRC}/lib\n\nLIBS=\t-lc\nLDLIBS=\t${LIBS}\n\nOBJDUMP!=if [ x\"${MACHINE_ARCH}\" = x\"arm\" ] ; then \\\n\t\techo \"${GCCPREFIX}-objdump -marm -M force-thumb\" ; \\\n\telif [ x\"${MACHINE_ARCH}\" = x\"mips\" ] ; then \\\n\t\techo \"${GCCPREFIX}-objdump -mmips:isa32r2\" ; \\\n\telse \\\n\t\techo \"/does/not/exist\" ; \\\n\tfi\n\nYACC!=\tif [ x\"${_HOST_OSNAME}\" = x\"Linux\" ] ; then \\\n\t\techo \"byacc\" ; \\\n\telse \\\n\t\techo \"yacc\" ; \\\n\tfi\n\nYFLAGS=\t-d\n\nLD=\t\t${GCCPREFIX}-ld\nAR=\t\t${GCCPREFIX}-ar\nRANLIB=\t\t${GCCPREFIX}-ranlib\nSIZE=\t\t${GCCPREFIX}-size\nAS=\t\t${CC} -x assembler-with-cpp -c\n\nLEX=\t\tflex\nINSTALL=\t${TOOLBINDIR}/binstall -U\n\nTAGSFILE=\ttags\n\n#MANROFF=\tnroff -man -h -Tascii\nMANROFF=\tmandoc -Tascii -Ios=\"DiscoBSD ${OSREV}\"\n\nELF2AOUT=\t${TOOLBINDIR}/elf2aout\n\nAOUT_AOUT=\t${TOOLBINDIR}/aout\nAOUT_AR=\t${TOOLBINDIR}/ar\nAOUT_AS=\t${TOOLBINDIR}/as\nAOUT_LD=\t${TOOLBINDIR}/ld\nAOUT_NM=\t${TOOLBINDIR}/nm\nAOUT_RANLIB=\t${TOOLBINDIR}/ranlib\nAOUT_SIZE=\t${TOOLBINDIR}/size\nAOUT_STRIP=\t${TOOLBINDIR}/strip\n"
  },
  {
    "path": "share/zoneinfo/.gitignore",
    "content": "zdump\nzic\n"
  },
  {
    "path": "share/zoneinfo/Makefile",
    "content": "# @(#)Makefile\t1.6 Makefile 1997/12/28\nTOPSRC!=cd ../..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\n# If you want something other than Western United States time used on your\n# system, change the line below (after finding the zone you want in the\n# time zone files, or adding it to a time zone file).\n# Alternately, if you discover you've got the wrong time zone, you can just\n#\tinstall -c -m 444 /usr/share/zoneinfo/right_zone /etc/localtime\n\nLOCALTIME=\tCanada/Mountain\n\n# If you want code inspired by certain emerging standards, add\n#\t-DSTD_INSPIRED\n# to the end of the \"CFLAGS=\" line.\n#\n# If you want to handle solar-time-based time zones, remove the\n# \"#define NOSOLAR\" from the include file usr/include/tzfile.h.\n# (and add solar87 to the DATA= line below).\n\nCFLAGS= -O\nLINTFLAGS=\t-phbaxc\nCC=\t\t${HOST_CC}\nCFLAGS+=\t-Wall -idirafter ${TOPSRC}/include\n\n# libbsd-dev package on Linux in overlay mode.\nCFLAGS+=\t${_LIBBSD_CFLAGS}\nLIBS+=\t\t${_LIBBSD_LIBS}\n\nTZCSRCS=\tzic.c scheck.c ialloc.c\nTZCOBJS=\tzic.o scheck.o ialloc.o\nTZDSRCS=\tzdump.c ialloc.c\nTZDOBJS=\tzdump.o ialloc.o\nSOURCES=\tzic.c zdump.c scheck.c ialloc.c\nDATA=\t\tasia australasia europe etcetera northamerica \\\n\t\tpacificnew systemv\nZICMAN=\t\tzic.0\nZICMANSRC=\tzic.8\nZDUMAN=\t\tzdump.0\nZDUMANSRC=\tzdump.8\nMAN=\t\t$(ZICMAN) $(ZDUMAN)\nMANSRC=\t\t$(ZICMANSRC) $(ZDUMAN)\nSHARDIR=\t${DESTDIR}/usr/share/zoneinfo\nMANDIR=\t\t${DESTDIR}/usr/share/man/cat8\n\nall:\t\tzdump zic ${ZICMAN} ${ZDUMAN}\n\ninstall:\tzic $(DATA) $(MAN)\n\t\t(umask 22; ./zic -v -d ${SHARDIR} $(DATA))\n#\t\t${INSTALL} -c ${ZICMAN} ${MANDIR}/${ZICMAN}\n#\t\t${INSTALL} -c ${ZDUMAN} ${MANDIR}/${ZDUMAN}\n#\t\t${INSTALL} -c -s zic ${DESTDIR}/usr/sbin/zic\n\nzdump.0:\t$(ZDUMANSRC)\n\t\t${MANROFF} ${ZDUMANSRC} > ${ZDUMAN}\n\nzic.0:\t\t$(ZICMANSRC)\n\t\t${MANROFF} ${ZICMANSRC} > ${ZICMAN}\n\nzdump:\t\t$(TZDOBJS)\n\t\t${CC} ${CFLAGS} ${LFLAGS} ${TZDOBJS} -o $@ ${LIBS}\n\nzic:\t\t$(TZCOBJS)\n\t\t${CC} ${CFLAGS} ${LFLAGS} ${TZCOBJS} -o $@ ${LIBS}\n\nlint:\t\t$(TZCSRCS) $(TZDSRCS)\n\t\tlint $(LINTFLAGS) $(CFLAGS) $(TZCSRCS)\n\t\tlint $(LINTFLAGS) $(CFLAGS) $(TZDSRCS)\n\nclean:\n\t\trm -f *.o zdump zic $(ZICMAN) $(ZDUMAN)\n"
  },
  {
    "path": "share/zoneinfo/README",
    "content": "@(#)README\t3.2 1996/11/29\n\nPlease send comments or information to\n\tseismo!elsie!tz\nfor forwarding to folks interested in time zone matters.\n\nBe sure to read the comments in \"Makefile\" and make any changes\nneeded to make things right for your system.\n\nThis version of the time zone software uses a new format\n(based on the work of Guy Harris, a.k.a guy@sun.UUCP)\nfor the time zone information files.  They are stored in a\ndirectory named \"/usr/share/zoneinfo\".\nIf you've already compiled programs with older time zone software,\nyou may need to make a copy of /usr/share/zoneinfo to the old location.\n\nFor better compatability with other versions of time conversion functions,\nthe time zone abbreviation to be used with localtime's return value is now\npointed to by one of the two elements of the (char *) array tzname, rather\nthan by the (char *) tz_abbr.  If you have code that uses tz_abbr, add a\n\t-DTZA_COMPAT\nto the end of the\n\tCFLAGS=\nline in \"Makefile\".\n\nTo use the new functions, use a \"-lz\" option when compiling or linking.\n\nHistorical local time information has been included here not because it\nis particularly useful, but rather to:\n\n*\tgive an idea of the variety of local time rules that have\n\texisted in the past and thus an idea of the variety that may be\n\texpected in the future;\n\n*\tprovide a test of the generality of the local time rule description\n\tsystem.\n\nThe information in the time zone data files is by no means authoritative;\nif you know that the rules are different from those in a file, by all means\nfeel free to change file (and please send the changed version to seismo!elsie!tz\nfor use in the future).  Europeans take note!\n"
  },
  {
    "path": "share/zoneinfo/Theory",
    "content": "@(#)Theory\t3.2 1996/11/29\n\nThese time and date functions are much like the System V Release 2.0 (SVR2)\ntime and date functions; there are a few additions and changes to extend\nthe usefulness of the SVR2 functions:\n\n*\tIn SVR2, time display in a process is controlled by the environment\n\tvariable TZ, which \"must be a three-letter time zone name, followed\n\tby a number representing the difference between local time and\n\tGreenwich Mean Time in hours, followed by an optional three-letter\n\tname for a daylight time zone;\" when the optional daylight time zone is\n\tpresent, \"standard U.S.A. Daylight Savings Time conversion is applied.\"\n\tThis means that SVR2 can't deal with other (for example, Australian) \n\tdaylight savings time rules, or situations where more than two\n\ttime zone abbreviations are used in an area.\n\n*\tIn SVR2, time conversion information is compiled into each program\n\tthat does time conversion.  This means that when time conversion\n\trules change (as in the United States in 1987), all programs that\n\tdo time conversion must be recompiled to ensure proper results.\n\n*\tIn SVR2, time conversion fails for near-minimum or near-maximum\n\ttime_t values when doing conversions for places that don't use GMT.\n\n*\tIn SVR2, there's no tamper-proof way for a process to learn the\n\tsystem's best idea of local wall clock.  (This is important for \n\tapplications that an administrator wants used only at certain times--\n\twithout regard to whether the user has fiddled the \"TZ\" environment\n\tvariable.  While an administrator can \"do everything in GMT\" to get\n\taround the problem, doing so is inconvenient and precludes handling\n\tdaylight savings time shifts--as might be required to limit phone\n\tcalls to off-peak hours.)\n\nThese are the changes that have been made to the SVR2 functions:\n\n*\tThe \"TZ\" environment variable is used in generating the name of a file\n\tfrom which time zone information is read; \"TZ\" is no longer constrained\n\tto be a three-letter time zone name followed by a number of hours and\n\tan optional three-letter daylight time zone name.  The daylight saving\n\ttime rules to be used for a particular time zone are encoded in the\n\ttime zone file; the format of the file allows U.S., Australian, and\n\tother rules to be encoded, and allows for situations where more than\n\ttwo time zone abbreviations are used.\n\n\tIt was recognized that allowing the \"TZ\" environment variable to\n\ttake on values such as \"US/Eastern\" might cause \"old\" programs\n\t(that expect \"TZ\" to have a certain form) to operate incorrectly;\n\tconsideration was given to using some other environment variable\n\t(for example, \"TIMEZONE\") to hold the string used to generate the\n\ttime zone information file name.  In the end, however, it was decided\n\tto continue using \"TZ\":  it is widely used for time zone purposes;\n\tseparately maintaining both \"TZ\" and \"TIMEZONE\" seemed a nuisance;\n\tand systems where \"new\" forms of \"TZ\" might cause problems can simply\n\tgive time zone files names such as \"EST5EDT\" which can be used both by\n\t\"new\" programs (as file names) and \"old\" programs (as zone names and\n\toffsets).\n\n*\tTo handle places where more than two time zone abbreviations are used,\n\tthe functions \"localtime\" and \"gmtime\" set tzname[tmp->tm_isdst]\n\t(where \"tmp\" is the value the function returns) to the time zone\n\tabbreviation to be used.  This differs from SVR2, where the elements\n\tof tzname are only changed as a result of calls to tzset.\n\n*\tSince the \"TZ\" environment variable can now be used to control time\n\tconversion, the \"daylight\" and \"timezone\" variables are no longer\n\tneeded or supported.  (You can use a compile-time option to cause\n\tthese variables to be defined and to be set by \"tzset\"; however, their\n\tvalues will not be used by \"localtime.\")\n\n*\tThe \"localtime\" function has been set up to deliver correct results\n\tfor near-minimum or near-maximum time_t values.  (A comment in the\n\tsource code tells how to get compatibly wrong results).\n\n*\tA function \"tzsetwall\" has been added to arrange for the system's\n\tbest approximation to local wall clock time to be delivered by\n\tsubsequent calls to \"localtime.\"  Source code for portable\n\tapplications that \"must\" run on local wall clock time should call\n\t\"tzsetwall();\" if such code is moved to \"old\" systems that don't provide\n\ttzsetwall, you won't be able to generate an executable program.\n\t(These time zone functions also arrange for local wall clock time to be\n\tused if tzset is called--directly or indirectly--and there's no \"TZ\"\n\tenvironment variable; portable applications should not, however, rely\n\ton this behavior since it's not the way SVR2 systems behave.)\n\nPoints of interest to folks with Version 7 or BSD systems:\n\n*\tThe BSD \"timezone\" function is not present in this package;\n\tit's impossible to reliably map timezone's arguments (a \"minutes west\n\tof GMT\" value and a \"daylight saving time in effect\" flag) to a\n\ttime zone abbreviation, and we refuse to guess. \n\tPrograms that in the past used the timezone function may now examine\n\ttzname[localtime(&clock)->tm_isdst] to learn the correct time\n\tzone abbreviation to use.  Alternatively, use localtime(&clock)->tm_zone\n\tif this has been enabled.\n\n*\tThe BSD gettimeofday function is not used in this package;\n\tthis lets users control the time zone used in doing time conversions.\n\tUsers who don't try to control things (that is, users who do not set\n\tthe environment variable TZ) get the time conversion specified in the\n\tfile \"/etc/localtime\"; see the time zone compiler writeup for\n\tinformation on how to initialize this file.\n\n*\tThe BSD \"dysize\" function is only included if the preprocessor symbol\n\tBSD_COMPAT is defined.  For a year y, the BSD code returns the value\n\t   ((y % 4) == 0) : 366 : 365\n\twhile this code returns the value\n\t   (((y) % 4) == 0 && ((y) % 100) != 0 || ((y) % 400) == 0) ? 366 : 365\n\tThere's a comment in the code telling how to get the BSD value.\n\nThe functions that are conditionally compiled if STD_INSPIRED is defined should,\nat this point, be looked on primarily as food for thought.  They are not in\nany sense \"standard compatible\"--some are not, in fact, specified in *any*\nstandard.  They do, however, represent responses of various authors to\nstandardization proposals.\n\nOther time conversion proposals, in particular the one developed by folks at\nHewlett Packard, offer a wider selection of functions that provide capabilities\nbeyond those provided here.  The absence of such functions from this package\nis not meant to discourage the development, standardization, or use of such\nfunctions.  Rather, their absence reflects the decision to make this package\nclose to SVR2 (with the exceptions outlined above) to ensure its broad\nacceptability.  If more powerful time conversion functions can be standardized,\nso much the better.\n\nIt's probably not wise to standardize everything in this package.\nWhile the command\n\tnroff -man newctime.3\nproduces a document that describes this package, the command\n\tnroff -man -rX3J11 newctime.3\nproduces a document that describes the \"standardizable\" parts.\n"
  },
  {
    "path": "share/zoneinfo/asia",
    "content": "# @(#)asia\t3.1\n# Incorporates data for Singapore from Robert Elz' asia 1.1\n# Zone\tNAME\t\tGMTOFF\tRULES/SAVE\tFORMAT\t[UNTIL]\nZone\tJapan\t\t9:00\t-\t\tJST\nZone\tSingapore\t8:00\t-\t\tSST\n"
  },
  {
    "path": "share/zoneinfo/australasia",
    "content": "# @(#)australasia\t3.1\n# Incorporates updates for Australia from Robert Elz' australia 1.1\n# and further updates from the Australian consulate.\n\n# Australian Data (for states with DST), standard rules\n# Includes shift in 1987 to follow Vic/NSW rules for ending DST,\n# and shift in 1986 to start DST earlier.\n\n# Rule\tNAME\tFROM\tTO\tTYPE\tIN\tON\tAT\tSAVE\tLETTER/S\nRule\tOz\t1971\t1985\t-\tOct\tlastSun\t2:00\t1:00\t-\nRule\tOz\t1986\tmax\t-\tOct\tSun<=24\t2:00\t1:00\t-\nRule\tOz\t1972\tonly\t-\tFeb\t27\t3:00\t0\t-\nRule\tOz\t1973\t1986\t-\tMar\tSun>=1\t3:00\t0\t-\nRule\tOz\t1987\tmax\t-\tMar\tSun<=21\t3:00\t0\t-\n\n# Zone\tNAME\t\t\tGMTOFF\tRULES\tFORMAT\t[UNTIL]\nZone\tAustralia/Tasmania\t10:00\tOz\tEST\nZone\tAustralia/Queensland\t10:00\t-\tEST\t# No DST here\nZone\tAustralia/North\t\t9:30\t-\tCST\t# No DST here\nZone\tAustralia/West\t\t8:00\t-\tWST\t# No DST here\nZone\tAustralia/South\t\t9:30\tOz\tCST\n\n# Victoria and New South Wales made the jump to a later ending date for\n# DST in 1986 rather than 1987.  New South Wales also had another variation\n# in 1983, but the details of that are unknown to the authors at this time.\n\nZone\tAustralia/Victoria\t10:00\tOz\tEST\t1985 Oct lastSun 2:00\n\t\t\t\t10:00\t1:00\tEST\t1986 Mar Sun<=21 3:00\n\t\t\t\t10:00\tOz\tEST\nLink\tAustralia/Victoria\tAustralia/NSW\n\n# New Zealand, from Elz' asia 1.1\n# Elz says \"no guarantees\"\n# Rule\tNAME\tFROM\tTO\tTYPE\tIN\tON\tAT\tSAVE\tLETTER/S\nRule\tNZ\t1974\tmax\t-\tOct\tlastSun\t2:00\t1:00\tD\nRule\tNZ\t1975\tmax\t-\tMar\tSun>=1\t3:00\t0\tS\n\n# Zone\tNAME\t\t\tGMTOFF\tRULES/SAVE\tFORMAT\t[UNTIL]\nZone\tNZ\t\t\t12:00\tNZ\t\tNZ%sT\t# New Zealand\n\n#\n# A footnote here:\n#\n#\t. . .\n#\tDate: Thu, j19 Feb 87 12:02:17 EST\n#\tFrom: Bradley White <seismo!k.cs.cmu.edu!bww>\n#\t. . .\n#\tI am including a description of Australian time zones. . .\n#\tthis stuff is definitely accurate.\n#\t. . .\n#\ta) Australian Eastern Time: (EST = GMT+10:00, EDT = GMT+11:00)\n#\t. . .\n#\tSummer of 86/87 - present (current legislation):\n#\t\tthird Sun Oct 02:00 EST -> third LSun Mar 02:00 EST\n#\n# If this turns out to be true, substitute Sun<=21 (third Sunday in October)\n# for Sun<=24 (next-to-last Sunday in October) above. . .some time before\n# October 1988, the first time it makes a difference.\n#\n"
  },
  {
    "path": "share/zoneinfo/etcetera",
    "content": "# @(#)etcetera\t3.1\n\nZone\tGMT\t\t0\t-\tGMT\n\n#\n# Names for zones that might exist, just so people can set a timezone\n# that's right for their area, even if it doesn't have a name or dst rules\n# (half hour zones are too much to bother with -- when someone asks!)\n#\n\nZone\tGMT-12\t\t-12\t-\tGMT-1200\nZone\tGMT-11\t\t-11\t-\tGMT-1100\nZone\tGMT-10\t\t-10\t-\tGMT-1000\nZone\tGMT-9\t\t-9\t-\tGMT-0900\nZone\tGMT-8\t\t-8\t-\tGMT-0800\nZone\tGMT-7\t\t-7\t-\tGMT-0700\nZone\tGMT-6\t\t-6\t-\tGMT-0600\nZone\tGMT-5\t\t-5\t-\tGMT-0500\nZone\tGMT-4\t\t-4\t-\tGMT-0400\nZone\tGMT-3\t\t-3\t-\tGMT-0300\nZone\tGMT-2\t\t-2\t-\tGMT-0200\nZone\tGMT-1\t\t-1\t-\tGMT-0100\nZone\tGMT+1\t\t1\t-\tGMT+0100\nZone\tGMT+2\t\t2\t-\tGMT+0200\nZone\tGMT+3\t\t3\t-\tGMT+0300\nZone\tGMT+4\t\t4\t-\tGMT+0400\nZone\tGMT+5\t\t5\t-\tGMT+0500\nZone\tGMT+6\t\t6\t-\tGMT+0600\nZone\tGMT+7\t\t7\t-\tGMT+0700\nZone\tGMT+8\t\t8\t-\tGMT+0800\nZone\tGMT+9\t\t9\t-\tGMT+0900\nZone\tGMT+10\t\t10\t-\tGMT+1000\nZone\tGMT+11\t\t11\t-\tGMT+1100\nZone\tGMT+12\t\t12\t-\tGMT+1200\nZone\tGMT+13\t\t13\t-\tGMT+1300\t# GMT+12 with DST\n\nLink\tGMT\t\tUTC\nLink\tGMT\t\tUCT\nLink\tGMT\t\tUniversal\nLink\tGMT\t\tGreenwich\n"
  },
  {
    "path": "share/zoneinfo/europe",
    "content": "# @(#)europe\t3.1\n\n# Europe, updated from 4.3BSD and various contributors\n# International country codes are used to identify countries' rules and\n# zones\n#\n# This data is by no means authoritative; if you think you know better, go\n# ahead and edit the file (and please send any changes to seismo!elsie!tz\n# for general use in the future).  The use of 1986 as starting years below\n# is conservative.\n#\n# One source shows that Bulgaria, Cyprus, Finland, and Greece observe DST from\n# the last Sunday in March to the last Sunday in September in 1986.\n# The source shows Romania changing a day later than everybody else.\n#\n# According to Bernard Sieloff's source, Poland is in the MET time zone but\n# uses the WE DST rules.  The Western USSR uses EET+1 and ME DST rules.\n# Bernard Sieloff's source claims Romania switches on the same day, but at\n# 00:00 standard time (i.e., 01:00 DST).  It also claims that Turkey\n# switches on the same day, but switches on at 01:00 standard time\n# and off at 00:00 standard time (i.e., 01:00 DST)\n\n# Rule\tNAME\tFROM\tTO\tTYPE\tIN\tON\tAT\tSAVE\tLETTER/S\nRule\tEU\t1979\t1995\t-\tSep\tlastSun\t1:00s\t0\t-\nRule\tEU   \t1981\tmax\t-\tMar\tlastSun\t1:00s\t1:00\t\"S\"\nRule\tEU   \t1996\tmax\t-\tOct\tlastSun\t1:00s\t0\t-\n\nRule\tC-Eur\t1979\t1995\t-\tSep\tlastSun\t2:00s\t0\t-\nRule\tC-Eur\t1981\tmax\t-\tMar\tlastSun\t2:00s\t1:00\t\"S\"\nRule\tC-Eur\t1996\tmax\t-\tOct\tlastSun\t2:00s\t0\t-\n\nRule\tTurkey\t1986\tmax\t-\tMar\tlastSun\t1:00\t1:00\t\" DST\"\nRule\tTurkey\t1986\tmax\t-\tSep\tlastSun\t1:00\t0\t-\n\nRule\tW-SU\t1986\tmax\t-\tMar\tlastSun\t2:00s\t1:00\t\" DST\"\nRule\tW-SU\t1986\tmax\t-\tSep\tlastSun\t2:00s\t0\t-\n\n# Zone\tNAME\t\tGMTOFF\tRULES/SAVE\tFORMAT\t[UNTIL]\nZone\tWET\t\t0:00\tEU   \t\tWE%sT\nZone\tCET\t\t1:00\tC-Eur\t\tCE%sT\nZone\tEET\t\t2:00\tEU\t\tEE%sT\nZone\tTurkey\t\t3:00\tTurkey\t\tEE%sT\nZone\tW-SU\t\t3:00\tC-Eur\t\t????\n\n#\n# And now, letters on the subject. . .\n#\n###############################################################################\n#\n# ...\n# Date: Wed, 28 Jan 87 16:56:27 -0100\n# From: seismo!mcvax!cgcha!wtho (Tom Hofmann)\n# Message-Id: <8701281556.AA22174@cgcha.uucp>\n# ...\n# Subject: Time zone handling\n# ...\n#\n# ...the European time rules are...standardized since 1981, when\n# most European counrties started DST.  Before that year, only\n# a few countries (UK, France, Italy) had DST, each according\n# to own national rules.  In 1981, however, DST started on\n# 'Apr firstSun', and not on 'Mar lastSun' as in the following\n# years...\n# But also since 1981 there are some more national exceptions\n# than listed in 'europe': Switzerland, for example, joined DST\n# one year later, Denmark ended DST on 'Oct 1' instead of 'Sep\n# lastSun' in 1981---I don't know how they handle now.\n#\n# Finally, DST ist always from 'Apr 1' to 'Oct 1' in the\n# Soviet Union (as far as I know).\n#\n# Tom Hofmann, Scientific Computer Center, CIBA-GEIGY AG,\n# 4002 Basle, Switzerland\n# UUCP: ...!mcvax!cernvax!cgcha!wtho\n#\n###############################################################################\n#\n# ...\n# Date: Wed, 4 Feb 87 22:35:22 +0100\n# From: seismo!mcvax!cwi.nl!dik (Dik T. Winter)\n# Message-Id: <8702042135.AA23919@zuring.cwi.nl>\n# ...\n# Subject: timezones\n# ...\n#\n# The information from Tom Hofmann is (as far as I know) not entirely correct.\n# After a request from chongo at amdahl I tried to retrieve all information\n# about DST in Europe.  I was able to find all from about 1969.\n#\n# ...standardization\n# on DST in Europe started in about 1977 with switches on first Sunday in\n# April and last Sunday in September.  In UK it was from last but 1 Sunday\n# in march to last Sunday in October.  In 1981 UK joined Europe insofar that\n# the starting day for both shifted to last Sunday in March.  And from 1982\n# the whole of Europe used DST, with switch dates April 1 and October 1 in\n# the Sovjet Union.  In 1985 the SU reverted to standard Europen switch\n# dates.  Note that currently in the UK the switch back date appears not\n# to be the last Sunday in October, but 4 weeks after the last Sunday in\n# September (withness 1982 and 1983 with terminating days October 24 and 23).\n#\n# It should also be remembered that time-zones are not constants; e.g.\n# Portugal switched in 1976 from MET (or CET) to WET with DST, and the UK\n# used MET throughout from 1967 to 1969, and WET with DST before and after\n# that time.  Note also that though there were rules for switch dates not\n# all countries abided to these dates, and many individual deviations\n# occurred, though not since 1982 I believe.  Another note: it is always\n# assumed that DST is 1 hour ahead of normal time, this need not be the\n# case; at least in the Netherlands there have been times when DST was 2 hours\n# in advance of normal time.\n#\n# ...\n# dik t. winter, cwi, amsterdam, nederland\n# INTERNET   : dik@cwi.nl\n# BITNET/EARN: dik@mcvax\n"
  },
  {
    "path": "share/zoneinfo/ialloc.c",
    "content": "/*\n *\t@(#)ialloc.c\t1.1 ialloc.c 3/4/87\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n\n#ifndef alloc_t\n#define alloc_t\tunsigned\n#endif /* !alloc_t */\n\n#ifdef MAL\n#define NULLMAL(x)\t((x) == NULL || (x) == MAL)\n#else /* !MAL */\n#define NULLMAL(x)\t((x) == NULL)\n#endif /* !MAL */\n\nchar *\nimalloc(int n)\n{\n#ifdef MAL\n\tregister char *\tresult;\n\n\tif (n == 0)\n\t\tn = 1;\n\tresult = malloc((alloc_t) n);\n\treturn (result == MAL) ? NULL : result;\n#else /* !MAL */\n\tif (n == 0)\n\t\tn = 1;\n\treturn malloc((alloc_t) n);\n#endif /* !MAL */\n}\n\nchar *\nicalloc(int nelem, int elsize)\n{\n\tif (nelem == 0 || elsize == 0)\n\t\tnelem = elsize = 1;\n\treturn calloc((alloc_t) nelem, (alloc_t) elsize);\n}\n\nchar *\nirealloc(char *pointer, int size)\n{\n\tif (NULLMAL(pointer))\n\t\treturn imalloc(size);\n\tif (size == 0)\n\t\tsize = 1;\n\treturn realloc(pointer, (alloc_t) size);\n}\n\nchar *\nicatalloc(char *old, char *new)\n{\n\tregister char *\tresult;\n\tregister int\toldsize, newsize;\n\n\toldsize = NULLMAL(old) ? 0 : strlen(old);\n\tnewsize = NULLMAL(new) ? 0 : strlen(new);\n\tif ((result = irealloc(old, oldsize + newsize + 1)) != NULL)\n\t\tif (!NULLMAL(new))\n\t\t\t(void)strlcpy(result + oldsize, new, newsize + 1);\n\treturn result;\n}\n\nchar *\nicpyalloc(char *string)\n{\n\treturn icatalloc((char *) NULL, string);\n}\n\nvoid\nifree(char *p)\n{\n\tif (!NULLMAL(p))\n\t\tfree(p);\n}\n"
  },
  {
    "path": "share/zoneinfo/northamerica",
    "content": "# @(#)northamerica\t3.1\n\n# Despite the performance of existing (4.[123]BSD, System V Release 2.0) code,\n# US Daylight Saving Time ended on the last Sunday of *October* in 1974.\n# See, for example, the front page of the Saturday, October 26, 1974\n# and Sunday, October 27, 1974 editions of the Washington Post.\n\n# Note also this from seismo!munnari!kre:\n# \"I recall also being told by someone once that Canada didn't have\n# the DST variations in 74/75 that the US did, but I am not nearly\n# sure enough of this to add anything.\"\n# The above has been confirmed by Bob Devine; we'll go with it here.\n\n# Before the Uniform Time Act of 1966 took effect in 1967, observance of\n# Daylight Saving Time in the US was by local option, except during wartime.\n\n# Rule\tNAME\tFROM\tTO\tTYPE\tIN\tON\tAT\tSAVE\tLETTER/S\nRule\tUS\t1918\t1919\t-\tMar\tlastSun\t2:00\t1:00\tD\nRule\tUS\t1918\t1919\t-\tOct\tlastSun\t2:00\t0\tS\nRule\tUS\t1942\tonly\t-\tFeb\t9\t2:00\t1:00\tW # War\nRule\tUS\t1945\tonly\t-\tSep\t30\t2:00\t0\tS\nRule\tUS\t1967\tmax\t-\tOct\tlastSun\t2:00\t0\tS\nRule\tUS\t1967\t1973\t-\tApr\tlastSun\t2:00\t1:00\tD\nRule\tUS\t1974\tonly\t-\tJan\t6\t2:00\t1:00\tD\nRule\tUS\t1975\tonly\t-\tFeb\t23\t2:00\t1:00\tD\nRule\tUS\t1976\t1986\t-\tApr\tlastSun\t2:00\t1:00\tD\nRule\tUS\t1987\tmax\t-\tApr\tSun>=1\t2:00\t1:00\tD\n\n###############################################################################\n\n# New names\n\n# Zone\tNAME\t\tGMTOFF\tRULES/SAVE\tFORMAT\t [UNTIL]\nZone\tUS/Eastern\t-5:00\tUS\t\tE%sT\nZone\tUS/Central\t-6:00\tUS\t\tC%sT\nZone\tUS/Mountain\t-7:00\tUS\t\tM%sT\nZone\tUS/Pacific\t-8:00\tUS\t\tP%sT\nZone\tUS/Yukon\t-9:00\tUS\t\tY%sT\n\n# Mainland US areas that are always Standard as of 1986.\n\nZone\tUS/East-Indiana\t-5:00\tUS\tE%sT\t1946\n\t\t\t-5:00\t-\tEST\t\t# Always EST as of 1986\nZone\tUS/Arizona\t-7:00\tUS\tM%sT\t1946\n\t\t\t-7:00\t-\tMST\t\t# Always MST as of 1986\n\n# And then there's Hawaii.\n# DST was observed for one day in 1933;\n# Standard time was change by half an hour in 1947;\n# it's always standard as of 1986.\n\nZone\tUS/Hawaii\t-10:30\tUS\tH%sT\t1933 Apr 30 2:00\n\t\t\t-10:30\t1:00\tHDT\t1933 May 1 2:00\n\t\t\t-10:30\tUS\tH%sT\t1947 Jun 8 2:00\n\t\t\t-10:00\t-\tHST\n\n# Old names, for S5 users\n\n# Link\tLINK-FROM\tLINK-TO\nLink\tUS/Eastern\tEST5EDT\nLink\tUS/Central\tCST6CDT\nLink\tUS/Mountain\tMST7MDT\nLink\tUS/Pacific\tPST8PDT\nLink\tUS/East-Indiana\tEST\nLink\tUS/Arizona\tMST\nLink\tUS/Hawaii\tHST\n\n################################################################################\n\n# Canada is reportedly lots easier than the US--leastways since 1951.\n# I don't know what they did before then.\n# 4.3BSD claims that it's perfectly regular.\n# According to a posting in \"comp.bugs.misc\", \"comp.unix.wizards\", etc.\n# on February 8, 1987, by Dave Sherman of the Law Society of Upper Canada,\n# \"...Canada (well, Ontario and at least some of the other provinces) are\n# adopting the new daylight savings time rules...\".  We assume all of\n# Canada is doing so.\n\n# Rule\tNAME\tFROM\tTO\tTYPE\tIN\tON\tAT\tSAVE\tLETTER/S\nRule\tCanada\t1969\tmax\t-\tOct\tlastSun\t2:00\t0\tS\nRule\tCanada\t1969\t1986\t-\tApr\tlastSun\t2:00\t1:00\tD\nRule\tCanada\t1987\tmax\t-\tApr\tSun>=1\t2:00\t1:00\tD\n\n# Zone\tNAME\t\t\tGMTOFF\tRULES/SAVE\tFORMAT\t[UNTIL]\n# Bob Devine says that DST *is* observed in Newfoundland\nZone\tCanada/Newfoundland\t-3:30\tCanada\t\tN%sT\nZone\tCanada/Atlantic\t\t-4:00\tCanada\t\tA%sT\nZone\tCanada/Eastern\t\t-5:00\tCanada\t\tE%sT\nZone\tCanada/Central\t\t-6:00\tCanada\t\tC%sT\nZone\tCanada/Mountain\t\t-7:00\tCanada\t\tM%sT\nZone\tCanada/Pacific\t\t-8:00\tCanada\t\tP%sT\nZone\tCanada/Yukon\t\t-9:00\tCanada\t\tY%sT\n\n################################################################################\n\n# ?Mexico?  !Quien sabe!\n"
  },
  {
    "path": "share/zoneinfo/pacificnew",
    "content": "# @(#)pacificnew\t3.1\n\n# \"Pacific Presidential Election Time\" has been contemplated by the US Congress\n\n# Rule\tNAME\tFROM\tTO\tTYPE\tIN\tON\tAT\tSAVE\tLETTER/S\nRule\tTwilite\t1987\tmax\t-\tApr\tSun>=1\t2:00\t1:00\tD\nRule\tTwilite\t1987\tmax\tuspres\tOct\tlastSun\t2:00\t1:00\tPE\nRule\tTwilite\t1987\tmax\tuspres\tNov\tSun>=7\t2:00\t0\tS\nRule\tTwilite\t1987\tmax\tnonpres\tOct\tlastSun\t2:00\t0\tS\n\n# Zone\tNAME\t\tGMTOFF\tRULES/SAVE\tFORMAT\t[UNTIL]\nZone\tUS/Pacific-New\t-8:00\tUS\t\tP%sT\t1987\n\t\t\t-8:00\tTwilite\t\tP%sT\n"
  },
  {
    "path": "share/zoneinfo/scheck.c",
    "content": "/*\n *\t@(#)scheck.c\t1.1 scheck.c 3/4/87\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <ctype.h>\n#include <string.h>\n\nextern char *\timalloc(int);\n\nchar *\nscheck(char *string, char *format)\n{\n\tregister char *\tfbuf;\n\tregister char *\tfp;\n\tregister char *\ttp;\n\tregister int\tc;\n\tregister char *\tresult;\n\tchar\t\tdummy;\n\n\tresult = \"\";\n\tif (string == NULL || format == NULL)\n\t\treturn result;\n\tfbuf = imalloc(2 * strlen(format) + 4);\n\tif (fbuf == NULL)\n\t\treturn result;\n\tfp = format;\n\ttp = fbuf;\n\twhile ((*tp++ = c = *fp++) != '\\0') {\n\t\tif (c != '%')\n\t\t\tcontinue;\n\t\tif (*fp == '%') {\n\t\t\t*tp++ = *fp++;\n\t\t\tcontinue;\n\t\t}\n\t\t*tp++ = '*';\n\t\tif (*fp == '*')\n\t\t\t++fp;\n\t\twhile (isascii(*fp) && isdigit(*fp))\n\t\t\t*tp++ = *fp++;\n\t\tif (*fp == 'l' || *fp == 'h')\n\t\t\t*tp++ = *fp++;\n\t\telse if (*fp == '[')\n\t\t\tdo *tp++ = *fp++;\n\t\t\t\twhile (*fp != '\\0' && *fp != ']');\n\t\tif ((*tp++ = *fp++) == '\\0')\n\t\t\tbreak;\n\t}\n\t*(tp - 1) = '%';\n\t*tp++ = 'c';\n\t*tp = '\\0';\n\tif (sscanf(string, fbuf, &dummy) != 1)\n\t\tresult = format;\n\tfree(fbuf);\n\treturn result;\n}\n"
  },
  {
    "path": "share/zoneinfo/solar87",
    "content": "# @(#)solar87\t3.1\n\n# So much for footnotes about Saudi Arabia.\n# Apparent noon times below are for Riyadh; your mileage will vary.\n# Times were computed using formulas in the U.S. Naval Observatory's\n# Almanac for Computers 1987; the formulas \"will give EqT to an accuracy of\n# [plus or minus] two seconds during the current year.\"\n#\n# Rounding to the nearest five seconds results in fewer than\n# 256 different \"time types\"--a limit that's faced because time types are\n# stored on disk as unsigned chars.\n\n# Rule\tNAME\tFROM\tTO\tTYPE\tIN\tON\tAT\tSAVE\tLETTER/S\nRule\tsol87\t1987\tonly\t-\tJan\t1\t12:03:20s -0:03:20 -\nRule\tsol87\t1987\tonly\t-\tJan\t2\t12:03:50s -0:03:50 -\nRule\tsol87\t1987\tonly\t-\tJan\t3\t12:04:15s -0:04:15 -\nRule\tsol87\t1987\tonly\t-\tJan\t4\t12:04:45s -0:04:45 -\nRule\tsol87\t1987\tonly\t-\tJan\t5\t12:05:10s -0:05:10 -\nRule\tsol87\t1987\tonly\t-\tJan\t6\t12:05:40s -0:05:40 -\nRule\tsol87\t1987\tonly\t-\tJan\t7\t12:06:05s -0:06:05 -\nRule\tsol87\t1987\tonly\t-\tJan\t8\t12:06:30s -0:06:30 -\nRule\tsol87\t1987\tonly\t-\tJan\t9\t12:06:55s -0:06:55 -\nRule\tsol87\t1987\tonly\t-\tJan\t10\t12:07:20s -0:07:20 -\nRule\tsol87\t1987\tonly\t-\tJan\t11\t12:07:45s -0:07:45 -\nRule\tsol87\t1987\tonly\t-\tJan\t12\t12:08:10s -0:08:10 -\nRule\tsol87\t1987\tonly\t-\tJan\t13\t12:08:30s -0:08:30 -\nRule\tsol87\t1987\tonly\t-\tJan\t14\t12:08:55s -0:08:55 -\nRule\tsol87\t1987\tonly\t-\tJan\t15\t12:09:15s -0:09:15 -\nRule\tsol87\t1987\tonly\t-\tJan\t16\t12:09:35s -0:09:35 -\nRule\tsol87\t1987\tonly\t-\tJan\t17\t12:09:55s -0:09:55 -\nRule\tsol87\t1987\tonly\t-\tJan\t18\t12:10:15s -0:10:15 -\nRule\tsol87\t1987\tonly\t-\tJan\t19\t12:10:35s -0:10:35 -\nRule\tsol87\t1987\tonly\t-\tJan\t20\t12:10:55s -0:10:55 -\nRule\tsol87\t1987\tonly\t-\tJan\t21\t12:11:10s -0:11:10 -\nRule\tsol87\t1987\tonly\t-\tJan\t22\t12:11:30s -0:11:30 -\nRule\tsol87\t1987\tonly\t-\tJan\t23\t12:11:45s -0:11:45 -\nRule\tsol87\t1987\tonly\t-\tJan\t24\t12:12:00s -0:12:00 -\nRule\tsol87\t1987\tonly\t-\tJan\t25\t12:12:15s -0:12:15 -\nRule\tsol87\t1987\tonly\t-\tJan\t26\t12:12:30s -0:12:30 -\nRule\tsol87\t1987\tonly\t-\tJan\t27\t12:12:40s -0:12:40 -\nRule\tsol87\t1987\tonly\t-\tJan\t28\t12:12:55s -0:12:55 -\nRule\tsol87\t1987\tonly\t-\tJan\t29\t12:13:05s -0:13:05 -\nRule\tsol87\t1987\tonly\t-\tJan\t30\t12:13:15s -0:13:15 -\nRule\tsol87\t1987\tonly\t-\tJan\t31\t12:13:25s -0:13:25 -\nRule\tsol87\t1987\tonly\t-\tFeb\t1\t12:13:35s -0:13:35 -\nRule\tsol87\t1987\tonly\t-\tFeb\t2\t12:13:40s -0:13:40 -\nRule\tsol87\t1987\tonly\t-\tFeb\t3\t12:13:50s -0:13:50 -\nRule\tsol87\t1987\tonly\t-\tFeb\t4\t12:13:55s -0:13:55 -\nRule\tsol87\t1987\tonly\t-\tFeb\t5\t12:14:00s -0:14:00 -\nRule\tsol87\t1987\tonly\t-\tFeb\t6\t12:14:05s -0:14:05 -\nRule\tsol87\t1987\tonly\t-\tFeb\t7\t12:14:10s -0:14:10 -\nRule\tsol87\t1987\tonly\t-\tFeb\t8\t12:14:10s -0:14:10 -\nRule\tsol87\t1987\tonly\t-\tFeb\t9\t12:14:15s -0:14:15 -\nRule\tsol87\t1987\tonly\t-\tFeb\t10\t12:14:15s -0:14:15 -\nRule\tsol87\t1987\tonly\t-\tFeb\t11\t12:14:15s -0:14:15 -\nRule\tsol87\t1987\tonly\t-\tFeb\t12\t12:14:15s -0:14:15 -\nRule\tsol87\t1987\tonly\t-\tFeb\t13\t12:14:15s -0:14:15 -\nRule\tsol87\t1987\tonly\t-\tFeb\t14\t12:14:15s -0:14:15 -\nRule\tsol87\t1987\tonly\t-\tFeb\t15\t12:14:10s -0:14:10 -\nRule\tsol87\t1987\tonly\t-\tFeb\t16\t12:14:10s -0:14:10 -\nRule\tsol87\t1987\tonly\t-\tFeb\t17\t12:14:05s -0:14:05 -\nRule\tsol87\t1987\tonly\t-\tFeb\t18\t12:14:00s -0:14:00 -\nRule\tsol87\t1987\tonly\t-\tFeb\t19\t12:13:55s -0:13:55 -\nRule\tsol87\t1987\tonly\t-\tFeb\t20\t12:13:50s -0:13:50 -\nRule\tsol87\t1987\tonly\t-\tFeb\t21\t12:13:45s -0:13:45 -\nRule\tsol87\t1987\tonly\t-\tFeb\t22\t12:13:35s -0:13:35 -\nRule\tsol87\t1987\tonly\t-\tFeb\t23\t12:13:30s -0:13:30 -\nRule\tsol87\t1987\tonly\t-\tFeb\t24\t12:13:20s -0:13:20 -\nRule\tsol87\t1987\tonly\t-\tFeb\t25\t12:13:10s -0:13:10 -\nRule\tsol87\t1987\tonly\t-\tFeb\t26\t12:13:00s -0:13:00 -\nRule\tsol87\t1987\tonly\t-\tFeb\t27\t12:12:50s -0:12:50 -\nRule\tsol87\t1987\tonly\t-\tFeb\t28\t12:12:40s -0:12:40 -\nRule\tsol87\t1987\tonly\t-\tMar\t1\t12:12:30s -0:12:30 -\nRule\tsol87\t1987\tonly\t-\tMar\t2\t12:12:20s -0:12:20 -\nRule\tsol87\t1987\tonly\t-\tMar\t3\t12:12:05s -0:12:05 -\nRule\tsol87\t1987\tonly\t-\tMar\t4\t12:11:55s -0:11:55 -\nRule\tsol87\t1987\tonly\t-\tMar\t5\t12:11:40s -0:11:40 -\nRule\tsol87\t1987\tonly\t-\tMar\t6\t12:11:25s -0:11:25 -\nRule\tsol87\t1987\tonly\t-\tMar\t7\t12:11:15s -0:11:15 -\nRule\tsol87\t1987\tonly\t-\tMar\t8\t12:11:00s -0:11:00 -\nRule\tsol87\t1987\tonly\t-\tMar\t9\t12:10:45s -0:10:45 -\nRule\tsol87\t1987\tonly\t-\tMar\t10\t12:10:30s -0:10:30 -\nRule\tsol87\t1987\tonly\t-\tMar\t11\t12:10:15s -0:10:15 -\nRule\tsol87\t1987\tonly\t-\tMar\t12\t12:09:55s -0:09:55 -\nRule\tsol87\t1987\tonly\t-\tMar\t13\t12:09:40s -0:09:40 -\nRule\tsol87\t1987\tonly\t-\tMar\t14\t12:09:25s -0:09:25 -\nRule\tsol87\t1987\tonly\t-\tMar\t15\t12:09:10s -0:09:10 -\nRule\tsol87\t1987\tonly\t-\tMar\t16\t12:08:50s -0:08:50 -\nRule\tsol87\t1987\tonly\t-\tMar\t17\t12:08:35s -0:08:35 -\nRule\tsol87\t1987\tonly\t-\tMar\t18\t12:08:15s -0:08:15 -\nRule\tsol87\t1987\tonly\t-\tMar\t19\t12:08:00s -0:08:00 -\nRule\tsol87\t1987\tonly\t-\tMar\t20\t12:07:40s -0:07:40 -\nRule\tsol87\t1987\tonly\t-\tMar\t21\t12:07:25s -0:07:25 -\nRule\tsol87\t1987\tonly\t-\tMar\t22\t12:07:05s -0:07:05 -\nRule\tsol87\t1987\tonly\t-\tMar\t23\t12:06:50s -0:06:50 -\nRule\tsol87\t1987\tonly\t-\tMar\t24\t12:06:30s -0:06:30 -\nRule\tsol87\t1987\tonly\t-\tMar\t25\t12:06:10s -0:06:10 -\nRule\tsol87\t1987\tonly\t-\tMar\t26\t12:05:55s -0:05:55 -\nRule\tsol87\t1987\tonly\t-\tMar\t27\t12:05:35s -0:05:35 -\nRule\tsol87\t1987\tonly\t-\tMar\t28\t12:05:15s -0:05:15 -\nRule\tsol87\t1987\tonly\t-\tMar\t29\t12:05:00s -0:05:00 -\nRule\tsol87\t1987\tonly\t-\tMar\t30\t12:04:40s -0:04:40 -\nRule\tsol87\t1987\tonly\t-\tMar\t31\t12:04:25s -0:04:25 -\nRule\tsol87\t1987\tonly\t-\tApr\t1\t12:04:05s -0:04:05 -\nRule\tsol87\t1987\tonly\t-\tApr\t2\t12:03:45s -0:03:45 -\nRule\tsol87\t1987\tonly\t-\tApr\t3\t12:03:30s -0:03:30 -\nRule\tsol87\t1987\tonly\t-\tApr\t4\t12:03:10s -0:03:10 -\nRule\tsol87\t1987\tonly\t-\tApr\t5\t12:02:55s -0:02:55 -\nRule\tsol87\t1987\tonly\t-\tApr\t6\t12:02:35s -0:02:35 -\nRule\tsol87\t1987\tonly\t-\tApr\t7\t12:02:20s -0:02:20 -\nRule\tsol87\t1987\tonly\t-\tApr\t8\t12:02:05s -0:02:05 -\nRule\tsol87\t1987\tonly\t-\tApr\t9\t12:01:45s -0:01:45 -\nRule\tsol87\t1987\tonly\t-\tApr\t10\t12:01:30s -0:01:30 -\nRule\tsol87\t1987\tonly\t-\tApr\t11\t12:01:15s -0:01:15 -\nRule\tsol87\t1987\tonly\t-\tApr\t12\t12:00:55s -0:00:55 -\nRule\tsol87\t1987\tonly\t-\tApr\t13\t12:00:40s -0:00:40 -\nRule\tsol87\t1987\tonly\t-\tApr\t14\t12:00:25s -0:00:25 -\nRule\tsol87\t1987\tonly\t-\tApr\t15\t12:00:10s -0:00:10 -\nRule\tsol87\t1987\tonly\t-\tApr\t16\t11:59:55s 0:00:05 -\nRule\tsol87\t1987\tonly\t-\tApr\t17\t11:59:45s 0:00:15 -\nRule\tsol87\t1987\tonly\t-\tApr\t18\t11:59:30s 0:00:30 -\nRule\tsol87\t1987\tonly\t-\tApr\t19\t11:59:15s 0:00:45 -\nRule\tsol87\t1987\tonly\t-\tApr\t20\t11:59:05s 0:00:55 -\nRule\tsol87\t1987\tonly\t-\tApr\t21\t11:58:50s 0:01:10 -\nRule\tsol87\t1987\tonly\t-\tApr\t22\t11:58:40s 0:01:20 -\nRule\tsol87\t1987\tonly\t-\tApr\t23\t11:58:25s 0:01:35 -\nRule\tsol87\t1987\tonly\t-\tApr\t24\t11:58:15s 0:01:45 -\nRule\tsol87\t1987\tonly\t-\tApr\t25\t11:58:05s 0:01:55 -\nRule\tsol87\t1987\tonly\t-\tApr\t26\t11:57:55s 0:02:05 -\nRule\tsol87\t1987\tonly\t-\tApr\t27\t11:57:45s 0:02:15 -\nRule\tsol87\t1987\tonly\t-\tApr\t28\t11:57:35s 0:02:25 -\nRule\tsol87\t1987\tonly\t-\tApr\t29\t11:57:25s 0:02:35 -\nRule\tsol87\t1987\tonly\t-\tApr\t30\t11:57:15s 0:02:45 -\nRule\tsol87\t1987\tonly\t-\tMay\t1\t11:57:10s 0:02:50 -\nRule\tsol87\t1987\tonly\t-\tMay\t2\t11:57:00s 0:03:00 -\nRule\tsol87\t1987\tonly\t-\tMay\t3\t11:56:55s 0:03:05 -\nRule\tsol87\t1987\tonly\t-\tMay\t4\t11:56:50s 0:03:10 -\nRule\tsol87\t1987\tonly\t-\tMay\t5\t11:56:45s 0:03:15 -\nRule\tsol87\t1987\tonly\t-\tMay\t6\t11:56:40s 0:03:20 -\nRule\tsol87\t1987\tonly\t-\tMay\t7\t11:56:35s 0:03:25 -\nRule\tsol87\t1987\tonly\t-\tMay\t8\t11:56:30s 0:03:30 -\nRule\tsol87\t1987\tonly\t-\tMay\t9\t11:56:25s 0:03:35 -\nRule\tsol87\t1987\tonly\t-\tMay\t10\t11:56:25s 0:03:35 -\nRule\tsol87\t1987\tonly\t-\tMay\t11\t11:56:20s 0:03:40 -\nRule\tsol87\t1987\tonly\t-\tMay\t12\t11:56:20s 0:03:40 -\nRule\tsol87\t1987\tonly\t-\tMay\t13\t11:56:20s 0:03:40 -\nRule\tsol87\t1987\tonly\t-\tMay\t14\t11:56:20s 0:03:40 -\nRule\tsol87\t1987\tonly\t-\tMay\t15\t11:56:20s 0:03:40 -\nRule\tsol87\t1987\tonly\t-\tMay\t16\t11:56:20s 0:03:40 -\nRule\tsol87\t1987\tonly\t-\tMay\t17\t11:56:20s 0:03:40 -\nRule\tsol87\t1987\tonly\t-\tMay\t18\t11:56:20s 0:03:40 -\nRule\tsol87\t1987\tonly\t-\tMay\t19\t11:56:25s 0:03:35 -\nRule\tsol87\t1987\tonly\t-\tMay\t20\t11:56:25s 0:03:35 -\nRule\tsol87\t1987\tonly\t-\tMay\t21\t11:56:30s 0:03:30 -\nRule\tsol87\t1987\tonly\t-\tMay\t22\t11:56:35s 0:03:25 -\nRule\tsol87\t1987\tonly\t-\tMay\t23\t11:56:40s 0:03:20 -\nRule\tsol87\t1987\tonly\t-\tMay\t24\t11:56:45s 0:03:15 -\nRule\tsol87\t1987\tonly\t-\tMay\t25\t11:56:50s 0:03:10 -\nRule\tsol87\t1987\tonly\t-\tMay\t26\t11:56:55s 0:03:05 -\nRule\tsol87\t1987\tonly\t-\tMay\t27\t11:57:00s 0:03:00 -\nRule\tsol87\t1987\tonly\t-\tMay\t28\t11:57:10s 0:02:50 -\nRule\tsol87\t1987\tonly\t-\tMay\t29\t11:57:15s 0:02:45 -\nRule\tsol87\t1987\tonly\t-\tMay\t30\t11:57:25s 0:02:35 -\nRule\tsol87\t1987\tonly\t-\tMay\t31\t11:57:30s 0:02:30 -\nRule\tsol87\t1987\tonly\t-\tJun\t1\t11:57:40s 0:02:20 -\nRule\tsol87\t1987\tonly\t-\tJun\t2\t11:57:50s 0:02:10 -\nRule\tsol87\t1987\tonly\t-\tJun\t3\t11:58:00s 0:02:00 -\nRule\tsol87\t1987\tonly\t-\tJun\t4\t11:58:10s 0:01:50 -\nRule\tsol87\t1987\tonly\t-\tJun\t5\t11:58:20s 0:01:40 -\nRule\tsol87\t1987\tonly\t-\tJun\t6\t11:58:30s 0:01:30 -\nRule\tsol87\t1987\tonly\t-\tJun\t7\t11:58:40s 0:01:20 -\nRule\tsol87\t1987\tonly\t-\tJun\t8\t11:58:50s 0:01:10 -\nRule\tsol87\t1987\tonly\t-\tJun\t9\t11:59:05s 0:00:55 -\nRule\tsol87\t1987\tonly\t-\tJun\t10\t11:59:15s 0:00:45 -\nRule\tsol87\t1987\tonly\t-\tJun\t11\t11:59:30s 0:00:30 -\nRule\tsol87\t1987\tonly\t-\tJun\t12\t11:59:40s 0:00:20 -\nRule\tsol87\t1987\tonly\t-\tJun\t13\t11:59:50s 0:00:10 -\nRule\tsol87\t1987\tonly\t-\tJun\t14\t12:00:05s -0:00:05 -\nRule\tsol87\t1987\tonly\t-\tJun\t15\t12:00:15s -0:00:15 -\nRule\tsol87\t1987\tonly\t-\tJun\t16\t12:00:30s -0:00:30 -\nRule\tsol87\t1987\tonly\t-\tJun\t17\t12:00:45s -0:00:45 -\nRule\tsol87\t1987\tonly\t-\tJun\t18\t12:00:55s -0:00:55 -\nRule\tsol87\t1987\tonly\t-\tJun\t19\t12:01:10s -0:01:10 -\nRule\tsol87\t1987\tonly\t-\tJun\t20\t12:01:20s -0:01:20 -\nRule\tsol87\t1987\tonly\t-\tJun\t21\t12:01:35s -0:01:35 -\nRule\tsol87\t1987\tonly\t-\tJun\t22\t12:01:50s -0:01:50 -\nRule\tsol87\t1987\tonly\t-\tJun\t23\t12:02:00s -0:02:00 -\nRule\tsol87\t1987\tonly\t-\tJun\t24\t12:02:15s -0:02:15 -\nRule\tsol87\t1987\tonly\t-\tJun\t25\t12:02:25s -0:02:25 -\nRule\tsol87\t1987\tonly\t-\tJun\t26\t12:02:40s -0:02:40 -\nRule\tsol87\t1987\tonly\t-\tJun\t27\t12:02:50s -0:02:50 -\nRule\tsol87\t1987\tonly\t-\tJun\t28\t12:03:05s -0:03:05 -\nRule\tsol87\t1987\tonly\t-\tJun\t29\t12:03:15s -0:03:15 -\nRule\tsol87\t1987\tonly\t-\tJun\t30\t12:03:30s -0:03:30 -\nRule\tsol87\t1987\tonly\t-\tJul\t1\t12:03:40s -0:03:40 -\nRule\tsol87\t1987\tonly\t-\tJul\t2\t12:03:50s -0:03:50 -\nRule\tsol87\t1987\tonly\t-\tJul\t3\t12:04:05s -0:04:05 -\nRule\tsol87\t1987\tonly\t-\tJul\t4\t12:04:15s -0:04:15 -\nRule\tsol87\t1987\tonly\t-\tJul\t5\t12:04:25s -0:04:25 -\nRule\tsol87\t1987\tonly\t-\tJul\t6\t12:04:35s -0:04:35 -\nRule\tsol87\t1987\tonly\t-\tJul\t7\t12:04:45s -0:04:45 -\nRule\tsol87\t1987\tonly\t-\tJul\t8\t12:04:55s -0:04:55 -\nRule\tsol87\t1987\tonly\t-\tJul\t9\t12:05:05s -0:05:05 -\nRule\tsol87\t1987\tonly\t-\tJul\t10\t12:05:15s -0:05:15 -\nRule\tsol87\t1987\tonly\t-\tJul\t11\t12:05:20s -0:05:20 -\nRule\tsol87\t1987\tonly\t-\tJul\t12\t12:05:30s -0:05:30 -\nRule\tsol87\t1987\tonly\t-\tJul\t13\t12:05:40s -0:05:40 -\nRule\tsol87\t1987\tonly\t-\tJul\t14\t12:05:45s -0:05:45 -\nRule\tsol87\t1987\tonly\t-\tJul\t15\t12:05:50s -0:05:50 -\nRule\tsol87\t1987\tonly\t-\tJul\t16\t12:06:00s -0:06:00 -\nRule\tsol87\t1987\tonly\t-\tJul\t17\t12:06:05s -0:06:05 -\nRule\tsol87\t1987\tonly\t-\tJul\t18\t12:06:10s -0:06:10 -\nRule\tsol87\t1987\tonly\t-\tJul\t19\t12:06:15s -0:06:15 -\nRule\tsol87\t1987\tonly\t-\tJul\t20\t12:06:15s -0:06:15 -\nRule\tsol87\t1987\tonly\t-\tJul\t21\t12:06:20s -0:06:20 -\nRule\tsol87\t1987\tonly\t-\tJul\t22\t12:06:25s -0:06:25 -\nRule\tsol87\t1987\tonly\t-\tJul\t23\t12:06:25s -0:06:25 -\nRule\tsol87\t1987\tonly\t-\tJul\t24\t12:06:25s -0:06:25 -\nRule\tsol87\t1987\tonly\t-\tJul\t25\t12:06:30s -0:06:30 -\nRule\tsol87\t1987\tonly\t-\tJul\t26\t12:06:30s -0:06:30 -\nRule\tsol87\t1987\tonly\t-\tJul\t27\t12:06:30s -0:06:30 -\nRule\tsol87\t1987\tonly\t-\tJul\t28\t12:06:30s -0:06:30 -\nRule\tsol87\t1987\tonly\t-\tJul\t29\t12:06:25s -0:06:25 -\nRule\tsol87\t1987\tonly\t-\tJul\t30\t12:06:25s -0:06:25 -\nRule\tsol87\t1987\tonly\t-\tJul\t31\t12:06:25s -0:06:25 -\nRule\tsol87\t1987\tonly\t-\tAug\t1\t12:06:20s -0:06:20 -\nRule\tsol87\t1987\tonly\t-\tAug\t2\t12:06:15s -0:06:15 -\nRule\tsol87\t1987\tonly\t-\tAug\t3\t12:06:10s -0:06:10 -\nRule\tsol87\t1987\tonly\t-\tAug\t4\t12:06:05s -0:06:05 -\nRule\tsol87\t1987\tonly\t-\tAug\t5\t12:06:00s -0:06:00 -\nRule\tsol87\t1987\tonly\t-\tAug\t6\t12:05:55s -0:05:55 -\nRule\tsol87\t1987\tonly\t-\tAug\t7\t12:05:50s -0:05:50 -\nRule\tsol87\t1987\tonly\t-\tAug\t8\t12:05:40s -0:05:40 -\nRule\tsol87\t1987\tonly\t-\tAug\t9\t12:05:35s -0:05:35 -\nRule\tsol87\t1987\tonly\t-\tAug\t10\t12:05:25s -0:05:25 -\nRule\tsol87\t1987\tonly\t-\tAug\t11\t12:05:15s -0:05:15 -\nRule\tsol87\t1987\tonly\t-\tAug\t12\t12:05:05s -0:05:05 -\nRule\tsol87\t1987\tonly\t-\tAug\t13\t12:04:55s -0:04:55 -\nRule\tsol87\t1987\tonly\t-\tAug\t14\t12:04:45s -0:04:45 -\nRule\tsol87\t1987\tonly\t-\tAug\t15\t12:04:35s -0:04:35 -\nRule\tsol87\t1987\tonly\t-\tAug\t16\t12:04:25s -0:04:25 -\nRule\tsol87\t1987\tonly\t-\tAug\t17\t12:04:10s -0:04:10 -\nRule\tsol87\t1987\tonly\t-\tAug\t18\t12:04:00s -0:04:00 -\nRule\tsol87\t1987\tonly\t-\tAug\t19\t12:03:45s -0:03:45 -\nRule\tsol87\t1987\tonly\t-\tAug\t20\t12:03:30s -0:03:30 -\nRule\tsol87\t1987\tonly\t-\tAug\t21\t12:03:15s -0:03:15 -\nRule\tsol87\t1987\tonly\t-\tAug\t22\t12:03:00s -0:03:00 -\nRule\tsol87\t1987\tonly\t-\tAug\t23\t12:02:45s -0:02:45 -\nRule\tsol87\t1987\tonly\t-\tAug\t24\t12:02:30s -0:02:30 -\nRule\tsol87\t1987\tonly\t-\tAug\t25\t12:02:15s -0:02:15 -\nRule\tsol87\t1987\tonly\t-\tAug\t26\t12:02:00s -0:02:00 -\nRule\tsol87\t1987\tonly\t-\tAug\t27\t12:01:40s -0:01:40 -\nRule\tsol87\t1987\tonly\t-\tAug\t28\t12:01:25s -0:01:25 -\nRule\tsol87\t1987\tonly\t-\tAug\t29\t12:01:05s -0:01:05 -\nRule\tsol87\t1987\tonly\t-\tAug\t30\t12:00:50s -0:00:50 -\nRule\tsol87\t1987\tonly\t-\tAug\t31\t12:00:30s -0:00:30 -\nRule\tsol87\t1987\tonly\t-\tSep\t1\t12:00:10s -0:00:10 -\nRule\tsol87\t1987\tonly\t-\tSep\t2\t11:59:50s 0:00:10 -\nRule\tsol87\t1987\tonly\t-\tSep\t3\t11:59:35s 0:00:25 -\nRule\tsol87\t1987\tonly\t-\tSep\t4\t11:59:15s 0:00:45 -\nRule\tsol87\t1987\tonly\t-\tSep\t5\t11:58:55s 0:01:05 -\nRule\tsol87\t1987\tonly\t-\tSep\t6\t11:58:35s 0:01:25 -\nRule\tsol87\t1987\tonly\t-\tSep\t7\t11:58:15s 0:01:45 -\nRule\tsol87\t1987\tonly\t-\tSep\t8\t11:57:55s 0:02:05 -\nRule\tsol87\t1987\tonly\t-\tSep\t9\t11:57:30s 0:02:30 -\nRule\tsol87\t1987\tonly\t-\tSep\t10\t11:57:10s 0:02:50 -\nRule\tsol87\t1987\tonly\t-\tSep\t11\t11:56:50s 0:03:10 -\nRule\tsol87\t1987\tonly\t-\tSep\t12\t11:56:30s 0:03:30 -\nRule\tsol87\t1987\tonly\t-\tSep\t13\t11:56:10s 0:03:50 -\nRule\tsol87\t1987\tonly\t-\tSep\t14\t11:55:45s 0:04:15 -\nRule\tsol87\t1987\tonly\t-\tSep\t15\t11:55:25s 0:04:35 -\nRule\tsol87\t1987\tonly\t-\tSep\t16\t11:55:05s 0:04:55 -\nRule\tsol87\t1987\tonly\t-\tSep\t17\t11:54:45s 0:05:15 -\nRule\tsol87\t1987\tonly\t-\tSep\t18\t11:54:20s 0:05:40 -\nRule\tsol87\t1987\tonly\t-\tSep\t19\t11:54:00s 0:06:00 -\nRule\tsol87\t1987\tonly\t-\tSep\t20\t11:53:40s 0:06:20 -\nRule\tsol87\t1987\tonly\t-\tSep\t21\t11:53:15s 0:06:45 -\nRule\tsol87\t1987\tonly\t-\tSep\t22\t11:52:55s 0:07:05 -\nRule\tsol87\t1987\tonly\t-\tSep\t23\t11:52:35s 0:07:25 -\nRule\tsol87\t1987\tonly\t-\tSep\t24\t11:52:15s 0:07:45 -\nRule\tsol87\t1987\tonly\t-\tSep\t25\t11:51:55s 0:08:05 -\nRule\tsol87\t1987\tonly\t-\tSep\t26\t11:51:35s 0:08:25 -\nRule\tsol87\t1987\tonly\t-\tSep\t27\t11:51:10s 0:08:50 -\nRule\tsol87\t1987\tonly\t-\tSep\t28\t11:50:50s 0:09:10 -\nRule\tsol87\t1987\tonly\t-\tSep\t29\t11:50:30s 0:09:30 -\nRule\tsol87\t1987\tonly\t-\tSep\t30\t11:50:10s 0:09:50 -\nRule\tsol87\t1987\tonly\t-\tOct\t1\t11:49:50s 0:10:10 -\nRule\tsol87\t1987\tonly\t-\tOct\t2\t11:49:35s 0:10:25 -\nRule\tsol87\t1987\tonly\t-\tOct\t3\t11:49:15s 0:10:45 -\nRule\tsol87\t1987\tonly\t-\tOct\t4\t11:48:55s 0:11:05 -\nRule\tsol87\t1987\tonly\t-\tOct\t5\t11:48:35s 0:11:25 -\nRule\tsol87\t1987\tonly\t-\tOct\t6\t11:48:20s 0:11:40 -\nRule\tsol87\t1987\tonly\t-\tOct\t7\t11:48:00s 0:12:00 -\nRule\tsol87\t1987\tonly\t-\tOct\t8\t11:47:45s 0:12:15 -\nRule\tsol87\t1987\tonly\t-\tOct\t9\t11:47:25s 0:12:35 -\nRule\tsol87\t1987\tonly\t-\tOct\t10\t11:47:10s 0:12:50 -\nRule\tsol87\t1987\tonly\t-\tOct\t11\t11:46:55s 0:13:05 -\nRule\tsol87\t1987\tonly\t-\tOct\t12\t11:46:40s 0:13:20 -\nRule\tsol87\t1987\tonly\t-\tOct\t13\t11:46:25s 0:13:35 -\nRule\tsol87\t1987\tonly\t-\tOct\t14\t11:46:10s 0:13:50 -\nRule\tsol87\t1987\tonly\t-\tOct\t15\t11:45:55s 0:14:05 -\nRule\tsol87\t1987\tonly\t-\tOct\t16\t11:45:45s 0:14:15 -\nRule\tsol87\t1987\tonly\t-\tOct\t17\t11:45:30s 0:14:30 -\nRule\tsol87\t1987\tonly\t-\tOct\t18\t11:45:20s 0:14:40 -\nRule\tsol87\t1987\tonly\t-\tOct\t19\t11:45:05s 0:14:55 -\nRule\tsol87\t1987\tonly\t-\tOct\t20\t11:44:55s 0:15:05 -\nRule\tsol87\t1987\tonly\t-\tOct\t21\t11:44:45s 0:15:15 -\nRule\tsol87\t1987\tonly\t-\tOct\t22\t11:44:35s 0:15:25 -\nRule\tsol87\t1987\tonly\t-\tOct\t23\t11:44:25s 0:15:35 -\nRule\tsol87\t1987\tonly\t-\tOct\t24\t11:44:20s 0:15:40 -\nRule\tsol87\t1987\tonly\t-\tOct\t25\t11:44:10s 0:15:50 -\nRule\tsol87\t1987\tonly\t-\tOct\t26\t11:44:05s 0:15:55 -\nRule\tsol87\t1987\tonly\t-\tOct\t27\t11:43:55s 0:16:05 -\nRule\tsol87\t1987\tonly\t-\tOct\t28\t11:43:50s 0:16:10 -\nRule\tsol87\t1987\tonly\t-\tOct\t29\t11:43:45s 0:16:15 -\nRule\tsol87\t1987\tonly\t-\tOct\t30\t11:43:45s 0:16:15 -\nRule\tsol87\t1987\tonly\t-\tOct\t31\t11:43:40s 0:16:20 -\nRule\tsol87\t1987\tonly\t-\tNov\t1\t11:43:40s 0:16:20 -\nRule\tsol87\t1987\tonly\t-\tNov\t2\t11:43:35s 0:16:25 -\nRule\tsol87\t1987\tonly\t-\tNov\t3\t11:43:35s 0:16:25 -\nRule\tsol87\t1987\tonly\t-\tNov\t4\t11:43:35s 0:16:25 -\nRule\tsol87\t1987\tonly\t-\tNov\t5\t11:43:35s 0:16:25 -\nRule\tsol87\t1987\tonly\t-\tNov\t6\t11:43:40s 0:16:20 -\nRule\tsol87\t1987\tonly\t-\tNov\t7\t11:43:40s 0:16:20 -\nRule\tsol87\t1987\tonly\t-\tNov\t8\t11:43:45s 0:16:15 -\nRule\tsol87\t1987\tonly\t-\tNov\t9\t11:43:50s 0:16:10 -\nRule\tsol87\t1987\tonly\t-\tNov\t10\t11:43:55s 0:16:05 -\nRule\tsol87\t1987\tonly\t-\tNov\t11\t11:44:00s 0:16:00 -\nRule\tsol87\t1987\tonly\t-\tNov\t12\t11:44:05s 0:15:55 -\nRule\tsol87\t1987\tonly\t-\tNov\t13\t11:44:15s 0:15:45 -\nRule\tsol87\t1987\tonly\t-\tNov\t14\t11:44:20s 0:15:40 -\nRule\tsol87\t1987\tonly\t-\tNov\t15\t11:44:30s 0:15:30 -\nRule\tsol87\t1987\tonly\t-\tNov\t16\t11:44:40s 0:15:20 -\nRule\tsol87\t1987\tonly\t-\tNov\t17\t11:44:50s 0:15:10 -\nRule\tsol87\t1987\tonly\t-\tNov\t18\t11:45:05s 0:14:55 -\nRule\tsol87\t1987\tonly\t-\tNov\t19\t11:45:15s 0:14:45 -\nRule\tsol87\t1987\tonly\t-\tNov\t20\t11:45:30s 0:14:30 -\nRule\tsol87\t1987\tonly\t-\tNov\t21\t11:45:45s 0:14:15 -\nRule\tsol87\t1987\tonly\t-\tNov\t22\t11:46:00s 0:14:00 -\nRule\tsol87\t1987\tonly\t-\tNov\t23\t11:46:15s 0:13:45 -\nRule\tsol87\t1987\tonly\t-\tNov\t24\t11:46:30s 0:13:30 -\nRule\tsol87\t1987\tonly\t-\tNov\t25\t11:46:50s 0:13:10 -\nRule\tsol87\t1987\tonly\t-\tNov\t26\t11:47:10s 0:12:50 -\nRule\tsol87\t1987\tonly\t-\tNov\t27\t11:47:25s 0:12:35 -\nRule\tsol87\t1987\tonly\t-\tNov\t28\t11:47:45s 0:12:15 -\nRule\tsol87\t1987\tonly\t-\tNov\t29\t11:48:05s 0:11:55 -\nRule\tsol87\t1987\tonly\t-\tNov\t30\t11:48:30s 0:11:30 -\nRule\tsol87\t1987\tonly\t-\tDec\t1\t11:48:50s 0:11:10 -\nRule\tsol87\t1987\tonly\t-\tDec\t2\t11:49:10s 0:10:50 -\nRule\tsol87\t1987\tonly\t-\tDec\t3\t11:49:35s 0:10:25 -\nRule\tsol87\t1987\tonly\t-\tDec\t4\t11:50:00s 0:10:00 -\nRule\tsol87\t1987\tonly\t-\tDec\t5\t11:50:25s 0:09:35 -\nRule\tsol87\t1987\tonly\t-\tDec\t6\t11:50:50s 0:09:10 -\nRule\tsol87\t1987\tonly\t-\tDec\t7\t11:51:15s 0:08:45 -\nRule\tsol87\t1987\tonly\t-\tDec\t8\t11:51:40s 0:08:20 -\nRule\tsol87\t1987\tonly\t-\tDec\t9\t11:52:05s 0:07:55 -\nRule\tsol87\t1987\tonly\t-\tDec\t10\t11:52:30s 0:07:30 -\nRule\tsol87\t1987\tonly\t-\tDec\t11\t11:53:00s 0:07:00 -\nRule\tsol87\t1987\tonly\t-\tDec\t12\t11:53:25s 0:06:35 -\nRule\tsol87\t1987\tonly\t-\tDec\t13\t11:53:55s 0:06:05 -\nRule\tsol87\t1987\tonly\t-\tDec\t14\t11:54:25s 0:05:35 -\nRule\tsol87\t1987\tonly\t-\tDec\t15\t11:54:50s 0:05:10 -\nRule\tsol87\t1987\tonly\t-\tDec\t16\t11:55:20s 0:04:40 -\nRule\tsol87\t1987\tonly\t-\tDec\t17\t11:55:50s 0:04:10 -\nRule\tsol87\t1987\tonly\t-\tDec\t18\t11:56:20s 0:03:40 -\nRule\tsol87\t1987\tonly\t-\tDec\t19\t11:56:50s 0:03:10 -\nRule\tsol87\t1987\tonly\t-\tDec\t20\t11:57:20s 0:02:40 -\nRule\tsol87\t1987\tonly\t-\tDec\t21\t11:57:50s 0:02:10 -\nRule\tsol87\t1987\tonly\t-\tDec\t22\t11:58:20s 0:01:40 -\nRule\tsol87\t1987\tonly\t-\tDec\t23\t11:58:50s 0:01:10 -\nRule\tsol87\t1987\tonly\t-\tDec\t24\t11:59:20s 0:00:40 -\nRule\tsol87\t1987\tonly\t-\tDec\t25\t11:59:50s 0:00:10 -\nRule\tsol87\t1987\tonly\t-\tDec\t26\t12:00:20s -0:00:20 -\nRule\tsol87\t1987\tonly\t-\tDec\t27\t12:00:45s -0:00:45 -\nRule\tsol87\t1987\tonly\t-\tDec\t28\t12:01:15s -0:01:15 -\nRule\tsol87\t1987\tonly\t-\tDec\t29\t12:01:45s -0:01:45 -\nRule\tsol87\t1987\tonly\t-\tDec\t30\t12:02:15s -0:02:15 -\nRule\tsol87\t1987\tonly\t-\tDec\t31\t12:02:45s -0:02:45 -\n\n# Riyadh is at about 46 degrees 46 minutes East:  3 hrs, 7 mins, 4 secs\n# Before and after 1987, we'll operate on local mean solar time.\n\n# Zone\tNAME\t\tGMTOFF\tRULES/SAVE\tFORMAT\t[UNTIL]\nZone\tMideast/Riyadh\t3:07:04\t-\t\t??\t1987\n\t\t\t3:07:04\tsol87\t\t??\t1988\n\t\t\t3:07:04\t-\t\t??\n"
  },
  {
    "path": "share/zoneinfo/systemv",
    "content": "# @(#)systemv\t3.1\n\n#\n# Old rules, should the need arise.\n# No attempt is made to handle Newfoundland, since it cannot be expressed\n# using the System V \"TZ\" scheme (half-hour offset), or anything outside\n# North America (no support for non-standard DST start/end dates), nor\n# the change in the DST rules in the US in 1987 (can't split between\n# Canada, with no changes, and the US)\n#\n\n# Rule\tNAME\tFROM\tTO\tTYPE\tIN\tON\tAT\tSAVE\tLETTER/S\nRule\tSystemV\tmin\t1973\t-\tApr\tlastSun\t2:00\t1:00\tD\nRule\tSystemV\tmin\t1973\t-\tOct\tlastSun\t2:00\t0\tS\nRule\tSystemV\t1974\tonly\t-\tJan\t6\t2:00\t1:00\tD\nRule\tSystemV\t1974\tonly\t-\tNov\tlastSun\t2:00\t0\tS\nRule\tSystemV\t1975\tonly\t-\tFeb\t23\t2:00\t1:00\tD\nRule\tSystemV\t1975\tonly\t-\tOct\tlastSun\t2:00\t0\tS\nRule\tSystemV\t1976\tmax\t-\tApr\tlastSun\t2:00\t1:00\tD\nRule\tSystemV\t1976\tmax\t-\tOct\tlastSun\t2:00\t0\tS\n\n# Zone\tNAME\t\tGMTOFF\tRULES/SAVE\tFORMAT\t[UNTIL]\nZone\tSystemV/AST4ADT\t-4:00\tSystemV\t\tA%sT\nZone\tSystemV/EST5EDT\t-5:00\tSystemV\t\tE%sT\nZone\tSystemV/CST6CDT\t-6:00\tSystemV\t\tC%sT\nZone\tSystemV/MST7MDT\t-7:00\tSystemV\t\tM%sT\nZone\tSystemV/PST8PDT\t-8:00\tSystemV\t\tP%sT\nZone\tSystemV/YST9YDT\t-9:00\tSystemV\t\tY%sT\nZone\tSystemV/AST4\t-4:00\t-\t\tAST\nZone\tSystemV/EST5\t-5:00\t-\t\tEST\nZone\tSystemV/CST6\t-6:00\t-\t\tCST\nZone\tSystemV/MST7\t-7:00\t-\t\tMST\nZone\tSystemV/PST8\t-8:00\t-\t\tPST\nZone\tSystemV/YST9\t-9:00\t-\t\tYST\nZone\tSystemV/HST10\t-10:00\t-\t\tHST\n"
  },
  {
    "path": "share/zoneinfo/zdump.8",
    "content": ".TH ZDUMP 8 \"November 30, 1996\"\n.SH NAME\nzdump \\- time zone dumper\n.SH SYNOPSIS\n.B zdump\n[\n.B \\-v\n] [\n.B \\-c\ncutoffyear ] [ zonename ... ]\n.SH DESCRIPTION\n.I Zdump\nprints the current time in each\n.I zonename\nnamed on the command line.\n.PP\nThese options are available:\n.TP\n.B \\-v\nFor each\n.I zonename\non the command line,\nprint the current time,\nthe time at the lowest possible time value,\nthe time one day after the lowest possible time value,\nthe times both one second before and exactly at\neach time at which the rules for computing local time change,\nthe time at the highest possible time value,\nand the time at one day less than the highest possible time value.\nEach line ends with\n.B isdst=1\nif the given time is Daylight Saving Time or\n.B isdst=0\notherwise.\n.TP\n.BI \"\\-c \" cutoffyear\nCut off the verbose output near the start of the given year.\n.SH FILES\n/usr/share/zoneinfo\tstandard zone information directory\n.SH \"SEE ALSO\"\nnewctime(3), tzfile(5), zic(8)\n.. @(#)zdump.8\t3.2\n"
  },
  {
    "path": "share/zoneinfo/zdump.c",
    "content": "/*\n *\t@(#)zdump.c\t1.1 zdump.c 3/4/87\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <sys/types.h>\n#include <time.h>\n#include <getopt.h>\n#include \"tzfile.h\"\n\n#ifndef TRUE\n#define TRUE\t\t1\n#define FALSE\t\t0\n#endif\n\nextern char **environ;\nextern char *tzname[2];\n\nextern char *imalloc(int);\nextern void tzset(void);\n\nstatic int\tlongest;\n\nstatic void\nshow(char *zone, time_t t, int v)\n{\n\tstruct tm *\t\ttmp;\n\n\t(void) printf(\"%-*s  \", longest, zone);\n\tif (v)\n\t\t(void) printf(\"%.24s GMT = \", asctime(gmtime(&t)));\n\ttmp = localtime(&t);\n\t(void) printf(\"%.24s\", asctime(tmp));\n\tif (*tzname[tmp->tm_isdst] != '\\0')\n\t\t(void) printf(\" %s\", tzname[tmp->tm_isdst]);\n\tif (v) {\n\t\t(void) printf(\" isdst=%d\", tmp->tm_isdst);\n\t\t(void) printf(\" gmtoff=%ld\", tmp->tm_gmtoff);\n\t}\n\t(void) printf(\"\\n\");\n}\n\nstatic void\nreaderr(FILE *fp, char *progname, char *filename)\n{\n\t(void) fprintf(stderr, \"%s: Error reading \", progname);\n\tif (ferror(fp))\n\t\tperror(filename);\n\telse\t(void) fprintf(stderr, \"%s: Premature EOF\\n\", filename);\n\texit(1);\n}\n\nstatic long\ntzdecode(char *codep)\n{\n\tregister int\ti;\n\tregister long\tresult;\n\n\tresult = 0;\n\tfor (i = 0; i < 4; ++i)\n\t\tresult = (result << 8) | (codep[i] & 0xff);\n\treturn result;\n}\n\nint\nmain(int argc, char *argv[])\n{\n\tregister FILE *\tfp;\n\tregister int\ti, j, c;\n\tregister int\tvflag;\n\tregister char *\tcutoff;\n\tregister int\tcutyear = 0;\n\tregister long\tcuttime;\n\ttime_t\t\tnow;\n\ttime_t\t\tt;\n\tlong\t\ttimecnt;\n\tchar\t\tbuf[BUFSIZ];\n\n\tvflag = 0;\n\tcutoff = NULL;\n\twhile ((c = getopt(argc, argv, \"c:v\")) == 'c' || c == 'v')\n\t\tif (c == 'v')\n\t\t\tvflag = 1;\n\t\telse\tcutoff = optarg;\n\tif (c != EOF ||\n            (optind == argc - 1 && strcmp(argv[optind], \"=\") == 0)) {\n\t\t(void) fprintf(stderr, \"%s: usage is %s [ -v ] zonename ...\\n\",\n\t\t\targv[0], argv[0]);\n\t\texit(1);\n\t}\n\tif (cutoff != NULL)\n\t\tcutyear = atoi(cutoff);\n\t/*\n\t** VERY approximate.\n\t*/\n\tcuttime = (long) (cutyear - EPOCH_YEAR) *\n\t\tSECS_PER_HOUR * HOURS_PER_DAY * DAYS_PER_NYEAR;\n\t(void) time(&now);\n\tlongest = 0;\n\tfor (i = optind; i < argc; ++i)\n\t\tif (strlen(argv[i]) > longest)\n\t\t\tlongest = strlen(argv[i]);\n\tfor (i = optind; i < argc; ++i) {\n\t\tregister char **\tsaveenv;\n\t\tchar *\t\t\ttzequals;\n\t\tchar *\t\t\tfakeenv[2];\n\n\t\ttzequals = imalloc(strlen(argv[i]) + 4);\n\t\tif (tzequals == NULL) {\n\t\t\t(void) fprintf(stderr, \"%s: can't allocate memory\\n\",\n\t\t\t\targv[0]);\n\t\t\texit(1);\n\t\t}\n\t\t(void)snprintf(tzequals, strlen(argv[i]) + 4, \"TZ=%s\", argv[i]);\n\t\tfakeenv[0] = tzequals;\n\t\tfakeenv[1] = NULL;\n\t\tsaveenv = environ;\n\t\tenviron = fakeenv;\n\t\t(void) tzset();\n\t\tenviron = saveenv;\n\t\tshow(argv[i], now, FALSE);\n\t\tif (!vflag)\n\t\t\tcontinue;\n\t\tif (argv[i][0] == '/')\n\t\t\tfp = fopen(argv[i], \"r\");\n\t\telse {\n\t\t\tj = strlen(TZDIR) + 1 + strlen(argv[i]) + 1;\n\t\t\tif (j > sizeof buf) {\n\t\t\t\t(void) fprintf(stderr,\n\t\t\t\t\t\"%s: timezone name %s/%s is too long\\n\",\n\t\t\t\t\targv[0], TZDIR, argv[i]);\n\t\t\t\texit(1);\n\t\t\t}\n\t\t\t(void)snprintf(buf, sizeof(buf), \"%s/%s\",\n\t\t\t    TZDIR, argv[i]);\n\t\t\tfp = fopen(buf, \"r\");\n\t\t}\n\t\tif (fp == NULL) {\n\t\t\t(void) fprintf(stderr, \"%s: Can't open \", argv[0]);\n\t\t\tperror(argv[i]);\n\t\t\texit(1);\n\t\t}\n\t\t{\n\t\t\tchar\t\tcode[4];\n\n(void) fseek(fp, (long) sizeof ((struct tzhead *) 0)->tzh_reserved, 0);\n\t\t\tif (fread((char *) code, sizeof code, 1, fp) != 1)\n\t\t\t\treaderr(fp, argv[0], argv[i]);\n\t\t\ttimecnt = tzdecode(code);\n\t\t\t(void) fseek(fp, (long) (2 * sizeof code), 1);\n\t\t}\n\t\tt = 0x80000000;\n\t\tif (t > 0)\t\t/* time_t is unsigned */\n\t\t\tt = 0;\n\t\tshow(argv[i], t, TRUE);\n\t\tt += SECS_PER_HOUR * HOURS_PER_DAY;\n\t\tshow(argv[i], t, TRUE);\n\t\twhile (timecnt-- > 0) {\n\t\t\tchar\tcode[4];\n\n\t\t\tif (fread((char *) code, sizeof code, 1, fp) != 1)\n\t\t\t\treaderr(fp, argv[0], argv[i]);\n\t\t\tt = tzdecode(code);\n\t\t\tif (cutoff != NULL && t > cuttime)\n\t\t\t\tbreak;\n\t\t\tshow(argv[i], t - 1, TRUE);\n\t\t\tshow(argv[i], t, TRUE);\n\t\t}\n\t\tif (fclose(fp)) {\n\t\t\t(void) fprintf(stderr, \"%s: Error closing \", argv[0]);\n\t\t\tperror(argv[i]);\n\t\t\texit(1);\n\t\t}\n\t\tt = 0xffffffff;\n\t\tif (t < 0)\t\t/* time_t is signed */\n\t\t\tt = 0x7fffffff ;\n\t\tt -= SECS_PER_HOUR * HOURS_PER_DAY;\n\t\tshow(argv[i], t, TRUE);\n\t\tt += SECS_PER_HOUR * HOURS_PER_DAY;\n\t\tshow(argv[i], t, TRUE);\n\t\tfree(tzequals);\n\t}\n\tif (fflush(stdout) || ferror(stdout)) {\n\t\t(void) fprintf(stderr, \"%s: Error writing standard output \",\n\t\t\targv[0]);\n\t\tperror(\"standard output\");\n\t\texit(1);\n\t}\n\treturn 0;\n}\n"
  },
  {
    "path": "share/zoneinfo/zic.8",
    "content": ".TH ZIC 8 \"November 30, 1996\"\n.SH NAME\nzic \\- time zone compiler\n.SH SYNOPSIS\n.B zic\n[\n.B \\-v\n] [\n.B \\-d\n.I directory\n] [\n.B \\-l\n.I localtime\n] [\n.I filename\n\\&... ]\n.SH DESCRIPTION\n.I Zic\nreads text from the file(s) named on the command line\nand creates the time conversion information files specified in this input.\nIf a\n.I filename\nis\n.BR \\- ,\nthe standard input is read.\n.PP\nThese options are available:\n.TP\n.BI \"\\-d \" directory\nCreate time conversion information files in the named directory rather than\nin the standard directory named below.\n.TP\n.BI \"\\-l \" timezone\nUse the given time zone as local time.\n.I Zic\nwill act as if the file contained a link line of the form\n.sp\n.ti +.5i\nLink\t\\fItimezone\\fP\t\tlocaltime\n.TP\n.B \\-v\nComplain if a year that appears in a data file is outside the range\nof years representable by\n.IR time (2)\nvalues.\n.sp\nInput lines are made up of fields.\nFields are separated from one another by any number of white space characters.\nLeading and trailing white space on input lines is ignored.\nAn unquoted sharp character (#) in the input introduces a comment which extends\nto the end of the line the sharp character appears on.\nWhite space characters and sharp characters may be enclosed in double quotes\n(\") if they're to be used as part of a field.\nAny line that is blank (after comment stripping) is ignored.\nNon-blank lines are expected to be of one of three types:\nrule lines, zone lines, and link lines.\n.PP\nA rule line has the form\n.nf\n.B\n.ti +.5i\n.ta \\w'Rule\\0\\0'u +\\w'NAME\\0\\0'u +\\w'FROM\\0\\0'u +\\w'1973\\0\\0'u +\\w'TYPE\\0\\0'u +\\w'Apr\\0\\0'u +\\w'lastSun\\0\\0'u +\\w'2:00\\0\\0'u +\\w'SAVE\\0\\0'u\n.sp\nRule\tNAME\tFROM\tTO\tTYPE\tIN\tON\tAT\tSAVE\tLETTER/S\n.sp\nFor example:\n.ti +.5i\n.sp\nRule\tUSA\t1969\t1973\t\\-\tApr\tlastSun\t2:00\t1:00\tD\n.sp\n.fi\nThe fields that make up a rule line are:\n.TP \"\\w'LETTER/S'u\"\n.B NAME\nGives the (arbitrary) name of the set of rules this rule is part of.\n.TP\n.B FROM\nGives the first year in which the rule applies.\nThe word\n.B minimum\n(or an abbreviation) means the minimum year with a representable time value.\nThe word\n.B maximum\n(or an abbreviation) means the maximum year with a representable time value.\n.TP\n.B TO\nGives the final year in which the rule applies.\nIn addition to\n.B minimum\nand\n.B maximum\n(as above),\nthe word\n.B only\n(or an abbreviation)\nmay be used to repeat the value of the\n.B FROM\nfield.\n.TP\n.B TYPE\nGives the type of year in which the year applies.\nIf\n.B TYPE\nis\n.B \\-\nthen the rule applies in all years between\n.B FROM\nand\n.B TO\ninclusive;\nif\n.B TYPE\nis\n.BR uspres ,\nthe rule applies in U.S. Presidential election years;\nif\n.B TYPE\nis\n.BR nonpres ,\nthe rule applies in years other than U.S. Presidential election years.\nIf\n.B TYPE\nis something else, then\n.I zic\nexecutes the command\n.ti +.5i\n\\fByearistype\\fP \\fIyear\\fP \\fItype\\fP\n.br\nto check the type of a year:\nan exit status of zero is taken to mean that the year is of the given type;\nan exit status of one is taken to mean that the year is not of the given type.\n.TP\n.B IN\nNames the month in which the rule takes effect.\nMonth names may be abbreviated.\n.TP\n.B ON\nGives the day on which the rule takes effect.\nRecognized forms include:\n.nf\n.in +.5i\n.sp\n.ta \\w'Sun<=25\\0\\0'u\n5\tthe fifth of the month\nlastSun\tthe last Sunday in the month\nlastMon\tthe last Monday in the month\nSun>=8\tfirst Sunday on or after the eighth\nSun<=25\tlast Sunday on or before the 25th\n.fi\n.in -.5i\n.sp\nNames of days of the week may be abbreviated or spelled out in full.\nNote that there must be no spaces within the\n.B ON\nfield.\n.TP\n.B AT\nGives the time of day at which the rule takes affect.\nRecognized forms include:\n.nf\n.in +.5i\n.sp\n.ta \\w'1:28:13\\0\\0'u\n2\ttime in hours\n2:00\ttime in hours and minutes\n15:00\t24-hour format time (for times after noon)\n1:28:14\ttime in hours, minutes, and seconds\n.fi\n.in -.5i\n.sp\nAny of these forms may be followed by the letter\n.B w\nif the given time is local ``wall clock'' time or\n.B s\nif the given time is local ``standard'' time; in the absence of\n.B w\nor\n.BR s ,\nwall clock time is assumed.\n.TP\n.B SAVE\nGives the amount of time to be added to local standard time when the rule is in\neffect.\nThis field has the same format as the\n.B AT\nfield\n(although, of course, the\n.B w\nand\n.B s\nsuffixes are not used).\n.TP\n.B LETTER/S\nGives the ``variable part'' (for example, the ``S'' or ``D'' in ``EST''\nor ``EDT'') of time zone abbreviations to be used when this rule is in effect.\nIf this field is\n.BR \\- ,\nthe variable part is null.\n.PP\nA zone line has the form\n.sp\n.nf\n.ti +.5i\n.ta \\w'Zone\\0\\0'u +\\w'Australia/South\\-west\\0\\0'u +\\w'GMTOFF\\0\\0'u +\\w'RULES/SAVE\\0\\0'u +\\w'FORMAT\\0\\0'u\nZone\tNAME\tGMTOFF\tRULES/SAVE\tFORMAT\t[UNTIL]\n.sp\nFor example:\n.sp\n.ti +.5i\nZone\tAustralia/South\\-west\t9:30\tAus\tCST\t1987 Mar 15 2:00\n.sp\n.fi\nThe fields that make up a zone line are:\n.TP \"\\w'GMTOFF'u\"\n.B NAME\nThe name of the time zone.\nThis is the name used in creating the time conversion information file for the\nzone.\n.TP\n.B GMTOFF\nThe amount of time to add to GMT to get standard time in this zone.\nThis field has the same format as the\n.B AT\nand\n.B SAVE\nfields of rule lines;\nbegin the field with a minus sign if time must be subtracted from GMT.\n.TP\n.B RULES/SAVE\nThe name of the rule(s) that apply in the time zone or,\nalternately, an amount of time to add to local standard time.\nIf this field is\n.B \\-\nthen standard time always applies in the time zone.\n.TP\n.B FORMAT\nThe format for time zone abbreviations in this time zone.\nThe pair of characters\n.B %s\nis used to show where the ``variable part'' of the time zone abbreviation goes.\n.B UNTIL\nThe time at which the GMT offset or the rule(s) change for a location.\nIt is specified as a year, a month, a day, and a time of day.\nIf this is specified,\nthe time zone information is generated from the given GMT offset\nand rule change until the time specified.\n.IP\nThe next line must be a\n``continuation'' line; this has the same form as a zone line except that the\nstring ``Zone'' and the name are omitted, as the continuation line will\nplace information starting at the time specified as the\n.B UNTIL\nfield in the previous line in the file used by the previous line.\nContinuation lines may contain an\n.B UNTIL\nfield, just as zone lines do, indicating that the next line is a further\ncontinuation.\n.PP\nA link line has the form\n.sp\n.nf\n.ti +.5i\n.if t .ta \\w'Link\\0\\0'u +\\w'LINK-FROM\\0\\0'u\n.if n .ta \\w'Link\\0\\0'u +\\w'US/Eastern\\0\\0'u\nLink\tLINK-FROM\tLINK-TO\n.sp\nFor example:\n.sp\n.ti +.5i\nLink\tUS/Eastern\tEST5EDT\n.sp\n.fi\nThe\n.B LINK-FROM\nfield should appear as the\n.B NAME\nfield in some zone line;\nthe\n.B LINK-TO\nfield is used as an alternate name for that zone.\n.PP\nExcept for continuation lines,\nlines may appear in any order in the input.\n.SH NOTE\nFor areas with more than two types of local time,\nyou may need to use local standard time in the\n.B AT\nfield of the earliest transition time's rule to ensure that\nthe earliest transition time recorded in the compiled file is correct.\n.SH FILES\n/usr/share/zoneinfo\tstandard directory used for created files\n.SH \"SEE ALSO\"\nnewctime(3), tzfile(5), zdump(8)\n.. @(#)zic.8\t3.2\n"
  },
  {
    "path": "share/zoneinfo/zic.c",
    "content": "/*\n *\t@(#)zic.c\t1.1 zic.c 3/4/87\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <ctype.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <sys/file.h>\n#include <string.h>\n#include <time.h>\n#include <getopt.h>\n#include \"tzfile.h\"\n\n#ifndef BUFSIZ\n#define BUFSIZ\t1024\n#endif\n\n#ifndef TRUE\n#define TRUE\t1\n#define FALSE\t0\n#endif\n\n/* Forward declaration. */\nstruct rule;\nstruct zone;\n\nextern char *\ticpyalloc(char *string);\nextern char *\timalloc(int n);\nextern char *\tirealloc(char *pointer, int size);\nextern char *\tscheck(char *string, char *format);\n\nstatic void\taddtt(time_t starttime, int type);\nstatic int\taddtype(long gmtoff, char *abbr, int isdst);\nstatic void\tassociate(void);\nstatic int\tcharcnt;\nstatic int\tciequal(char *ap, char *bp);\nstatic long\teitol(int i);\nstatic int\terrors;\nstatic char *\tfilename;\nstatic char **\tgetfields(char *cp);\nstatic long\tgethms(char *string, char *errstring, int signable);\nstatic void\tinfile(char *name);\nstatic void\tinlink(char **fields, int nfields);\nstatic void\tinrule(char **fields, int nfields);\nstatic int\tinzcont(char **fields, int nfields);\nstatic int\tinzone(char **fields, int nfields);\nstatic int\tinzsub(char **fields, int nfields, int iscont);\nstatic int\tlinenum;\nstatic int\tlowerit(int a);\nstatic time_t\tmax_time;\nstatic int\tmax_year;\nstatic time_t\tmin_time;\nstatic int\tmin_year;\nstatic int\tmkdirs(char *name);\nstatic void\tnewabbr(char *string);\nstatic int\tnoise;\nstatic void\tnondunlink(char *name);\nstatic long\toadd(long t1, long t2);\nstatic void\toutzone(struct zone *zpfirst, int zonecount);\nstatic char *\tprogname;\nstatic char *\trfilename;\nstatic int\trlinenum;\nstatic time_t\trpytime(struct rule *rp, int wantedy);\nstatic void\trulesub(struct rule *rp, char *loyearp, char *hiyearp, char *typep,\n\t\t    char *monthp, char *dayp, char *timep);\nstatic void\tsetboundaries(void);\nstatic time_t\ttadd(time_t t1, long t2);\nstatic int\ttimecnt;\nstatic int\ttt_signed;\nstatic int\ttypecnt;\nstatic int\tyearistype(int year, char *type);\n\n/*\n** Line codes.\n*/\n\n#define LC_RULE\t\t0\n#define LC_ZONE\t\t1\n#define LC_LINK\t\t2\n\n/*\n** Which fields are which on a Zone line.\n*/\n\n#define ZF_NAME\t\t1\n#define ZF_GMTOFF\t2\n#define ZF_RULE\t\t3\n#define ZF_FORMAT\t4\n#define ZF_UNTILYEAR\t5\n#define ZF_UNTILMONTH\t6\n#define ZF_UNTILDAY\t7\n#define ZF_UNTILTIME\t8\n#define ZONE_MINFIELDS\t5\n#define ZONE_MAXFIELDS\t9\n\n/*\n** Which fields are which on a Zone continuation line.\n*/\n\n#define ZFC_GMTOFF\t0\n#define ZFC_RULE\t1\n#define ZFC_FORMAT\t2\n#define ZFC_UNTILYEAR\t3\n#define ZFC_UNTILMONTH\t4\n#define ZFC_UNTILDAY\t5\n#define ZFC_UNTILTIME\t6\n#define ZONEC_MINFIELDS\t3\n#define ZONEC_MAXFIELDS\t7\n\n/*\n** Which files are which on a Rule line.\n*/\n\n#define RF_NAME\t\t1\n#define RF_LOYEAR\t2\n#define RF_HIYEAR\t3\n#define RF_COMMAND\t4\n#define RF_MONTH\t5\n#define RF_DAY\t\t6\n#define RF_TOD\t\t7\n#define RF_STDOFF\t8\n#define RF_ABBRVAR\t9\n#define RULE_FIELDS\t10\n\n/*\n** Which fields are which on a Link line.\n*/\n\n#define LF_FROM\t\t1\n#define LF_TO\t\t2\n#define LINK_FIELDS\t3\n\nstruct rule {\n\tchar *\tr_filename;\n\tint\tr_linenum;\n\tchar *\tr_name;\n\n\tint\tr_loyear;\t/* for example, 1986 */\n\tint\tr_hiyear;\t/* for example, 1986 */\n\tchar *\tr_yrtype;\n\n\tint\tr_month;\t/* 0..11 */\n\n\tint\tr_dycode;\t/* see below */\n\tint\tr_dayofmonth;\n\tint\tr_wday;\n\n\tlong\tr_tod;\t\t/* time from midnight */\n\tint\tr_todisstd;\t/* above is standard time if TRUE */\n\t\t\t\t/* above is wall clock time if FALSE */\n\tlong\tr_stdoff;\t/* offset from standard time */\n\tchar *\tr_abbrvar;\t/* variable part of time zone abbreviation */\n\n\tint\tr_todo;\t\t/* a rule to do (used in outzone) */\n\ttime_t\tr_temp;\t\t/* used in outzone */\n};\n\n/*\n**\tr_dycode\t\tr_dayofmonth\tr_wday\n*/\n#define DC_DOM\t\t0\t/* 1..31 */\t/* unused */\n#define DC_DOWGEQ\t1\t/* 1..31 */\t/* 0..6 (Sun..Sat) */\n#define DC_DOWLEQ\t2\t/* 1..31 */\t/* 0..6 (Sun..Sat) */\n\n/*\n** Year synonyms.\n*/\n\n#define YR_MINIMUM\t0\n#define YR_MAXIMUM\t1\n#define YR_ONLY\t\t2\n\nstatic struct rule *\trules;\nstatic int\t\tnrules;\t/* number of rules */\n\nstruct zone {\n\tchar *\t\tz_filename;\n\tint\t\tz_linenum;\n\n\tchar *\t\tz_name;\n\tlong\t\tz_gmtoff;\n\tchar *\t\tz_rule;\n\tchar *\t\tz_format;\n\n\tlong\t\tz_stdoff;\n\n\tstruct rule *\tz_rules;\n\tint\t\tz_nrules;\n\n\tstruct rule\tz_untilrule;\n\ttime_t\t\tz_untiltime;\n};\n\nstatic struct zone *\tzones;\nstatic int\t\tnzones;\t/* number of zones */\n\nstruct link {\n\tchar *\t\tl_filename;\n\tint\t\tl_linenum;\n\tchar *\t\tl_from;\n\tchar *\t\tl_to;\n};\n\nstatic struct link *\tlinks;\nstatic int\t\tnlinks;\n\nstruct lookup {\n\tchar *\t\tl_word;\n\tint\t\tl_value;\n};\n\nstatic struct lookup *\tbyword(char *word, struct lookup *table);\n\nstatic struct lookup\tline_codes[] = {\n\t{ \"Rule\",\tLC_RULE },\n\t{ \"Zone\",\tLC_ZONE },\n\t{ \"Link\",\tLC_LINK },\n\t{ NULL,\t\t0 }\n};\n\nstatic struct lookup\tmon_names[] = {\n\t{ \"January\",\tTM_JANUARY },\n\t{ \"February\",\tTM_FEBRUARY },\n\t{ \"March\",\tTM_MARCH },\n\t{ \"April\",\tTM_APRIL },\n\t{ \"May\",\tTM_MAY },\n\t{ \"June\",\tTM_JUNE },\n\t{ \"July\",\tTM_JULY },\n\t{ \"August\",\tTM_AUGUST },\n\t{ \"September\",\tTM_SEPTEMBER },\n\t{ \"October\",\tTM_OCTOBER },\n\t{ \"November\",\tTM_NOVEMBER },\n\t{ \"December\",\tTM_DECEMBER },\n\t{ NULL,\t\t0 }\n};\n\nstatic struct lookup\twday_names[] = {\n\t{ \"Sunday\",\tTM_SUNDAY },\n\t{ \"Monday\",\tTM_MONDAY },\n\t{ \"Tuesday\",\tTM_TUESDAY },\n\t{ \"Wednesday\",\tTM_WEDNESDAY },\n\t{ \"Thursday\",\tTM_THURSDAY },\n\t{ \"Friday\",\tTM_FRIDAY },\n\t{ \"Saturday\",\tTM_SATURDAY },\n\t{ NULL,\t\t0 }\n};\n\nstatic struct lookup\tlasts[] = {\n\t{ \"last-Sunday\",\tTM_SUNDAY },\n\t{ \"last-Monday\",\tTM_MONDAY },\n\t{ \"last-Tuesday\",\tTM_TUESDAY },\n\t{ \"last-Wednesday\",\tTM_WEDNESDAY },\n\t{ \"last-Thursday\",\tTM_THURSDAY },\n\t{ \"last-Friday\",\tTM_FRIDAY },\n\t{ \"last-Saturday\",\tTM_SATURDAY },\n\t{ NULL,\t\t\t0 }\n};\n\nstatic struct lookup\tbegin_years[] = {\n\t{ \"minimum\",\t\tYR_MINIMUM },\n\t{ \"maximum\",\t\tYR_MAXIMUM },\n\t{ NULL,\t\t\t0 }\n};\n\nstatic struct lookup\tend_years[] = {\n\t{ \"minimum\",\t\tYR_MINIMUM },\n\t{ \"maximum\",\t\tYR_MAXIMUM },\n\t{ \"only\",\t\tYR_ONLY },\n\t{ NULL,\t\t\t0 }\n};\n\nstatic int\tlen_months[2][MONS_PER_YEAR] = {\n\t{ 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 },\n\t{ 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }\n};\n\nstatic int\tlen_years[2] = {\n\tDAYS_PER_NYEAR, DAYS_PER_LYEAR\n};\n\nstatic time_t\t\tats[TZ_MAX_TIMES];\nstatic unsigned char\ttypes[TZ_MAX_TIMES];\nstatic long\t\tgmtoffs[TZ_MAX_TYPES];\nstatic char\t\tisdsts[TZ_MAX_TYPES];\nstatic char\t\tabbrinds[TZ_MAX_TYPES];\nstatic char\t\tchars[TZ_MAX_CHARS];\n\n/*\n** Memory allocation.\n*/\n\nstatic char *\nmemcheck(char *ptr)\n{\n\tif (ptr == NULL) {\n\t\tperror(progname);\n\t\texit(1);\n\t}\n\treturn ptr;\n}\n\n#define emalloc(size)\t\tmemcheck(imalloc(size))\n#define erealloc(ptr, size)\tmemcheck(irealloc(ptr, size))\n#define ecpyalloc(ptr)\t\tmemcheck(icpyalloc(ptr))\n\n/*\n** Error handling.\n*/\n\nstatic void\neats(char *name, int num, char *rname, int rnum)\n{\n\tfilename = name;\n\tlinenum = num;\n\trfilename = rname;\n\trlinenum = rnum;\n}\n\nstatic void\neat(char *name, int num)\n{\n\teats(name, num, (char *) NULL, -1);\n}\n\nstatic void\nerror(char *string)\n{\n\t/*\n\t** Match the format of \"cc\" to allow sh users to\n\t** \tzic ... 2>&1 | error -t \"*\" -v\n\t** on BSD systems.\n\t*/\n\t(void) fprintf(stderr, \"\\\"%s\\\", line %d: %s\",\n\t\tfilename, linenum, string);\n\tif (rfilename != NULL)\n\t\t(void) fprintf(stderr, \" (rule from \\\"%s\\\", line %d)\",\n\t\t\trfilename, rlinenum);\n\t(void) fprintf(stderr, \"\\n\");\n\t++errors;\n}\n\nstatic void\nusage(void)\n{\n\t(void) fprintf(stderr,\n\"%s: usage is %s [ -v ] [ -l localtime ] [ -d directory ] [ filename ... ]\\n\",\n\t\tprogname, progname);\n\texit(1);\n}\n\nstatic char *\tlcltime = NULL;\nstatic char *\tdirectory = NULL;\n\nint\nmain(int argc, char *argv[])\n{\n\tregister int\ti, j;\n\tregister int\tc;\n\n#ifdef unix\n\tumask(umask(022) | 022);\n#endif\n\tprogname = argv[0];\n\twhile ((c = getopt(argc, argv, \"d:l:v\")) != EOF)\n\t\tswitch (c) {\n\t\t\tdefault:\n\t\t\t\tusage();\n\t\t\tcase 'd':\n\t\t\t\tif (directory == NULL)\n\t\t\t\t\tdirectory = optarg;\n\t\t\t\telse {\n\t\t\t\t\t(void) fprintf(stderr,\n\"%s: More than one -d option specified\\n\",\n\t\t\t\t\t\tprogname);\n\t\t\t\t\texit(1);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 'l':\n\t\t\t\tif (lcltime == NULL)\n\t\t\t\t\tlcltime = optarg;\n\t\t\t\telse {\n\t\t\t\t\t(void) fprintf(stderr,\n\"%s: More than one -l option specified\\n\",\n\t\t\t\t\t\tprogname);\n\t\t\t\t\texit(1);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 'v':\n\t\t\t\tnoise = TRUE;\n\t\t\t\tbreak;\n\t\t}\n\tif (optind == argc - 1 && strcmp(argv[optind], \"=\") == 0)\n\t\tusage();\t/* usage message by request */\n\tif (directory == NULL)\n\t\tdirectory = TZDIR;\n\n\tsetboundaries();\n\n\tzones = (struct zone *) emalloc(0);\n\trules = (struct rule *) emalloc(0);\n\tlinks = (struct link *) emalloc(0);\n\tfor (i = optind; i < argc; ++i)\n\t\tinfile(argv[i]);\n\tif (errors)\n\t\texit(1);\n\tassociate();\n\tfor (i = 0; i < nzones; i = j) {\n\t\t/*\n\t\t * Find the next non-continuation zone entry.\n\t\t */\n\t\tfor (j = i + 1; j < nzones && zones[j].z_name == NULL; ++j)\n\t\t\t;\n\t\toutzone(&zones[i], j - i);\n\t}\n\t/*\n\t** We'll take the easy way out on this last part.\n\t*/\n\tif (chdir(directory) != 0) {\n\t\t(void) fprintf(stderr, \"%s: Can't chdir to \", progname);\n\t\tperror(directory);\n\t\texit(1);\n\t}\n\tfor (i = 0; i < nlinks; ++i) {\n\t\tnondunlink(links[i].l_to);\n\t\tif (link(links[i].l_from, links[i].l_to) != 0) {\n\t\t\t(void) fprintf(stderr, \"%s: Can't link %s to \",\n\t\t\t\tprogname, links[i].l_from);\n\t\t\tperror(links[i].l_to);\n\t\t\texit(1);\n\t\t}\n\t}\n\tif (lcltime != NULL) {\n\t\tnondunlink(TZDEFAULT);\n\t\tif (link(lcltime, TZDEFAULT) != 0) {\n\t\t\t(void) fprintf(stderr, \"%s: Can't link %s to \",\n\t\t\t\tprogname, lcltime);\n\t\t\tperror(TZDEFAULT);\n\t\t\texit(1);\n\t\t}\n\t}\n\texit((errors == 0) ? 0 : 1);\n}\n\nstatic void\nsetboundaries(void)\n{\n\tregister time_t bit;\n        struct tm zerotm = {0};\n\n\tfor (bit = 1; bit > 0; bit <<= 1)\n\t\t;\n\tif (bit == 0) {\t\t/* time_t is an unsigned type */\n\t\ttt_signed = FALSE;\n\t\tmin_time = 0;\n\t\tmax_time = ~(time_t) 0;\n\t} else {\n\t\ttt_signed = TRUE;\n\t\tfor (;;) {\n                    min_time = mktime(&zerotm);\n                    if (min_time != -1)\n                        break;\n                    zerotm.tm_year++;\n                }\n                zerotm.tm_year = TZ_MAX_TIMES/2 - 2;\n\t\tfor (;;) {\n                    max_time = mktime(&zerotm);\n                    if (max_time != -1)\n                        break;\n                    zerotm.tm_year--;\n                }\n\t}\n\tmin_year = TM_YEAR_BASE + gmtime(&min_time)->tm_year;\n\tmax_year = TM_YEAR_BASE + gmtime(&max_time)->tm_year;\n}\n\n/*\n** We get to be careful here since there's a fair chance of root running us.\n*/\n\nstatic void\nnondunlink(char *name)\n{\n\tstruct stat\ts;\n\n\tif (stat(name, &s) != 0)\n\t\treturn;\n\tif ((s.st_mode & S_IFMT) == S_IFDIR)\n\t\treturn;\n\t(void) unlink(name);\n}\n\n/*\n** Associate sets of rules with zones.\n*/\n\n/*\n** Sort by rule name.\n*/\n\nstatic int\nrcomp(const void *cp1, const void *cp2)\n{\n\treturn strcmp(((const struct rule *) cp1)->r_name,\n\t\t((const struct rule *) cp2)->r_name);\n}\n\nstatic void\nassociate(void)\n{\n\tregister struct zone *\tzp;\n\tregister struct rule *\trp;\n\tregister int\t\tbase, out;\n\tregister int\t\ti;\n\n\tif (nrules != 0)\n\t\t(void) qsort((char *) rules, nrules, sizeof *rules, rcomp);\n\tfor (i = 0; i < nzones; ++i) {\n\t\tzp = &zones[i];\n\t\tzp->z_rules = NULL;\n\t\tzp->z_nrules = 0;\n\t}\n\tfor (base = 0; base < nrules; base = out) {\n\t\trp = &rules[base];\n\t\tfor (out = base + 1; out < nrules; ++out)\n\t\t\tif (strcmp(rp->r_name, rules[out].r_name) != 0)\n\t\t\t\tbreak;\n\t\tfor (i = 0; i < nzones; ++i) {\n\t\t\tzp = &zones[i];\n\t\t\tif (strcmp(zp->z_rule, rp->r_name) != 0)\n\t\t\t\tcontinue;\n\t\t\tzp->z_rules = rp;\n\t\t\tzp->z_nrules = out - base;\n\t\t}\n\t}\n\tfor (i = 0; i < nzones; ++i) {\n\t\tzp = &zones[i];\n\t\tif (zp->z_nrules == 0) {\n\t\t\t/*\n\t\t\t** Maybe we have a local standard time offset.\n\t\t\t*/\n\t\t\teat(zp->z_filename, zp->z_linenum);\n\t\t\tzp->z_stdoff = gethms(zp->z_rule, \"unruly zone\", TRUE);\n\t\t\t/*\n\t\t\t** Note, though, that if there's no rule,\n\t\t\t** a '%s' in the format is a bad thing.\n\t\t\t*/\n\t\t\tif (index(zp->z_format, '%') != 0)\n\t\t\t\terror(\"%s in ruleless zone\");\n\t\t}\n\t}\n\tif (errors)\n\t\texit(1);\n}\n\nstatic void\ninfile(char *name)\n{\n\tregister FILE *\t\t\tfp;\n\tregister char **\t\tfields;\n\tregister char *\t\t\tcp;\n\tregister struct lookup *\tlp;\n\tregister int\t\t\tnfields;\n\tregister int\t\t\twantcont;\n\tregister int\t\t\tnum;\n\tchar\t\t\t\tbuf[BUFSIZ];\n\n\tif (strcmp(name, \"-\") == 0) {\n\t\tname = \"standard input\";\n\t\tfp = stdin;\n\t} else if ((fp = fopen(name, \"r\")) == NULL) {\n\t\t(void) fprintf(stderr, \"%s: Can't open \", progname);\n\t\tperror(name);\n\t\texit(1);\n\t}\n\twantcont = FALSE;\n\tfor (num = 1; ; ++num) {\n\t\teat(name, num);\n\t\tif (fgets(buf, sizeof buf, fp) != buf)\n\t\t\tbreak;\n\t\tcp = index(buf, '\\n');\n\t\tif (cp == NULL) {\n\t\t\terror(\"line too long\");\n\t\t\texit(1);\n\t\t}\n\t\t*cp = '\\0';\n\t\tfields = getfields(buf);\n\t\tnfields = 0;\n\t\twhile (fields[nfields] != NULL) {\n\t\t\tif (ciequal(fields[nfields], \"-\"))\n\t\t\t\tfields[nfields] = \"\";\n\t\t\t++nfields;\n\t\t}\n\t\tif (nfields == 0) {\n\t\t\t/* nothing to do */\n\t\t} else if (wantcont) {\n\t\t\twantcont = inzcont(fields, nfields);\n\t\t} else {\n\t\t\tlp = byword(fields[0], line_codes);\n\t\t\tif (lp == NULL)\n\t\t\t\terror(\"input line of unknown type\");\n\t\t\telse switch ((int) (lp->l_value)) {\n\t\t\t\tcase LC_RULE:\n\t\t\t\t\tinrule(fields, nfields);\n\t\t\t\t\twantcont = FALSE;\n\t\t\t\t\tbreak;\n\t\t\t\tcase LC_ZONE:\n\t\t\t\t\twantcont = inzone(fields, nfields);\n\t\t\t\t\tbreak;\n\t\t\t\tcase LC_LINK:\n\t\t\t\t\tinlink(fields, nfields);\n\t\t\t\t\twantcont = FALSE;\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\t/* \"cannot happen\" */\n\t\t\t\t\t(void) fprintf(stderr,\n\"%s: panic: Invalid l_value %d\\n\",\n\t\t\t\t\t\tprogname, lp->l_value);\n\t\t\t\t\texit(1);\n\t\t\t}\n\t\t}\n\t\tfree((char *) fields);\n\t}\n\tif (ferror(fp)) {\n\t\t(void) fprintf(stderr, \"%s: Error reading \", progname);\n\t\tperror(filename);\n\t\texit(1);\n\t}\n\tif (fp != stdin && fclose(fp)) {\n\t\t(void) fprintf(stderr, \"%s: Error closing \", progname);\n\t\tperror(filename);\n\t\texit(1);\n\t}\n\tif (wantcont)\n\t\terror(\"expected continuation line not found\");\n}\n\n/*\n** Convert a string of one of the forms\n**\th\t-h \thh:mm\t-hh:mm\thh:mm:ss\t-hh:mm:ss\n** into a number of seconds.\n** A null string maps to zero.\n** Call error with errstring and return zero on errors.\n*/\n\nstatic long\ngethms(char *string, char *errstring, int signable)\n{\n\tint\thh, mm, ss, sign;\n\n\tif (string == NULL || *string == '\\0')\n\t\treturn 0;\n\tif (!signable)\n\t\tsign = 1;\n\telse if (*string == '-') {\n\t\tsign = -1;\n\t\t++string;\n\t} else\tsign = 1;\n\tif (sscanf(string, scheck(string, \"%d\"), &hh) == 1)\n\t\tmm = ss = 0;\n\telse if (sscanf(string, scheck(string, \"%d:%d\"), &hh, &mm) == 2)\n\t\tss = 0;\n\telse if (sscanf(string, scheck(string, \"%d:%d:%d\"),\n\t\t&hh, &mm, &ss) != 3) {\n\t\t\terror(errstring);\n\t\t\treturn 0;\n\t}\n\tif (hh < 0 || hh >= HOURS_PER_DAY ||\n\t\tmm < 0 || mm >= MINS_PER_HOUR ||\n\t\tss < 0 || ss >= SECS_PER_MIN) {\n\t\t\terror(errstring);\n\t\t\treturn 0;\n\t}\n\treturn eitol(sign) *\n\t\t(eitol(hh * MINS_PER_HOUR + mm) *\n\t\teitol(SECS_PER_MIN) + eitol(ss));\n}\n\nstatic void\ninrule(char **fields, int nfields)\n{\n\tstruct rule\tr;\n\n\tif (nfields != RULE_FIELDS) {\n\t\terror(\"wrong number of fields on Rule line\");\n\t\treturn;\n\t}\n\tif (*fields[RF_NAME] == '\\0') {\n\t\terror(\"nameless rule\");\n\t\treturn;\n\t}\n\tr.r_filename = filename;\n\tr.r_linenum = linenum;\n\tr.r_stdoff = gethms(fields[RF_STDOFF], \"invalid saved time\", TRUE);\n\trulesub(&r, fields[RF_LOYEAR], fields[RF_HIYEAR], fields[RF_COMMAND],\n\t\tfields[RF_MONTH], fields[RF_DAY], fields[RF_TOD]);\n\tr.r_name = ecpyalloc(fields[RF_NAME]);\n\tr.r_abbrvar = ecpyalloc(fields[RF_ABBRVAR]);\n\trules = (struct rule *) erealloc((char *) rules,\n\t\t(nrules + 1) * sizeof *rules);\n\trules[nrules++] = r;\n}\n\nstatic int\ninzone(char **fields, int nfields)\n{\n\tregister int\ti;\n\tchar\t\tbuf[132];\n\n\tif (nfields < ZONE_MINFIELDS || nfields > ZONE_MAXFIELDS) {\n\t\terror(\"wrong number of fields on Zone line\");\n\t\treturn FALSE;\n\t}\n\tif (strcmp(fields[ZF_NAME], TZDEFAULT) == 0 && lcltime != NULL) {\n\t\t(void)snprintf(buf, sizeof(buf),\n\t\t\t\"\\\"Zone %s\\\" line and -l option are mutually exclusive\",\n\t\t\tTZDEFAULT);\n\t\terror(buf);\n\t\treturn FALSE;\n\t}\n\tfor (i = 0; i < nzones; ++i)\n\t\tif (zones[i].z_name != NULL &&\n\t\t\tstrcmp(zones[i].z_name, fields[ZF_NAME]) == 0) {\n\t\t\t\t(void)snprintf(buf, sizeof(buf),\n\"duplicate zone name %s (file \\\"%s\\\", line %d)\",\n\t\t\t\t\tfields[ZF_NAME],\n\t\t\t\t\tzones[i].z_filename,\n\t\t\t\t\tzones[i].z_linenum);\n\t\t\t\terror(buf);\n\t\t\t\treturn FALSE;\n\t\t}\n\treturn inzsub(fields, nfields, FALSE);\n}\n\nstatic int\ninzcont(char **fields, int nfields)\n{\n\tif (nfields < ZONEC_MINFIELDS || nfields > ZONEC_MAXFIELDS) {\n\t\terror(\"wrong number of fields on Zone continuation line\");\n\t\treturn FALSE;\n\t}\n\treturn inzsub(fields, nfields, TRUE);\n}\n\nstatic int\ninzsub(char **fields, int nfields, int iscont)\n{\n\tregister char *\tcp;\n\tstruct zone\tz;\n\tregister int\ti_gmtoff, i_rule, i_format;\n\tregister int\ti_untilyear, i_untilmonth;\n\tregister int\ti_untilday, i_untiltime;\n\tregister int\thasuntil;\n\n\tif (iscont) {\n\t\ti_gmtoff = ZFC_GMTOFF;\n\t\ti_rule = ZFC_RULE;\n\t\ti_format = ZFC_FORMAT;\n\t\ti_untilyear = ZFC_UNTILYEAR;\n\t\ti_untilmonth = ZFC_UNTILMONTH;\n\t\ti_untilday = ZFC_UNTILDAY;\n\t\ti_untiltime = ZFC_UNTILTIME;\n\t\tz.z_name = NULL;\n\t} else {\n\t\ti_gmtoff = ZF_GMTOFF;\n\t\ti_rule = ZF_RULE;\n\t\ti_format = ZF_FORMAT;\n\t\ti_untilyear = ZF_UNTILYEAR;\n\t\ti_untilmonth = ZF_UNTILMONTH;\n\t\ti_untilday = ZF_UNTILDAY;\n\t\ti_untiltime = ZF_UNTILTIME;\n\t\tz.z_name = ecpyalloc(fields[ZF_NAME]);\n\t}\n\tz.z_filename = filename;\n\tz.z_linenum = linenum;\n\tz.z_gmtoff = gethms(fields[i_gmtoff], \"invalid GMT offset\", TRUE);\n\tif ((cp = index(fields[i_format], '%')) != 0) {\n\t\tif (*++cp != 's' || index(cp, '%') != 0) {\n\t\t\terror(\"invalid abbreviation format\");\n\t\t\treturn FALSE;\n\t\t}\n\t}\n\tz.z_rule = ecpyalloc(fields[i_rule]);\n\tz.z_format = ecpyalloc(fields[i_format]);\n\thasuntil = nfields > i_untilyear;\n\tif (hasuntil) {\n\t\tz.z_untilrule.r_filename = filename;\n\t\tz.z_untilrule.r_linenum = linenum;\n\t\trulesub(&z.z_untilrule,\n\t\t\tfields[i_untilyear],\n\t\t\t\"only\",\n\t\t\t\"\",\n\t\t\t(nfields > i_untilmonth) ? fields[i_untilmonth] : \"Jan\",\n\t\t\t(nfields > i_untilday) ? fields[i_untilday] : \"1\",\n\t\t\t(nfields > i_untiltime) ? fields[i_untiltime] : \"0\");\n\t\tz.z_untiltime = rpytime(&z.z_untilrule, z.z_untilrule.r_loyear);\n\t\tif (iscont && nzones > 0 && z.z_untiltime < max_time &&\n\t\t\tz.z_untiltime > min_time &&\n\t\t\tzones[nzones - 1].z_untiltime >= z.z_untiltime) {\nerror(\"Zone continuation line end time is not after end time of previous line\");\n\t\t\treturn FALSE;\n\t\t}\n\t}\n\tzones = (struct zone *) erealloc((char *) zones,\n\t\t(nzones + 1) * sizeof *zones);\n\tzones[nzones++] = z;\n\t/*\n\t** If there was an UNTIL field on this line,\n\t** there's more information about the zone on the next line.\n\t*/\n\treturn hasuntil;\n}\n\nstatic void\ninlink(char **fields, int nfields)\n{\n\tstruct link\tl;\n\n\tif (nfields != LINK_FIELDS) {\n\t\terror(\"wrong number of fields on Link line\");\n\t\treturn;\n\t}\n\tif (*fields[LF_FROM] == '\\0') {\n\t\terror(\"blank FROM field on Link line\");\n\t\treturn;\n\t}\n\tif (*fields[LF_TO] == '\\0') {\n\t\terror(\"blank TO field on Link line\");\n\t\treturn;\n\t}\n\tl.l_filename = filename;\n\tl.l_linenum = linenum;\n\tl.l_from = ecpyalloc(fields[LF_FROM]);\n\tl.l_to = ecpyalloc(fields[LF_TO]);\n\tlinks = (struct link *) erealloc((char *) links,\n\t\t(nlinks + 1) * sizeof *links);\n\tlinks[nlinks++] = l;\n}\n\nstatic void\nrulesub(struct rule *rp, char *loyearp, char *hiyearp, char *typep,\n    char *monthp, char *dayp, char *timep)\n{\n\tregister struct lookup *\tlp;\n\tregister char *\t\t\tcp;\n\n\tif ((lp = byword(monthp, mon_names)) == NULL) {\n\t\terror(\"invalid month name\");\n\t\treturn;\n\t}\n\trp->r_month = lp->l_value;\n\trp->r_todisstd = FALSE;\n\tcp = timep;\n\tif (*cp != '\\0') {\n\t\tcp += strlen(cp) - 1;\n\t\tswitch (lowerit(*cp)) {\n\t\t\tcase 's':\n\t\t\t\trp->r_todisstd = TRUE;\n\t\t\t\t*cp = '\\0';\n\t\t\t\tbreak;\n\t\t\tcase 'w':\n\t\t\t\trp->r_todisstd = FALSE;\n\t\t\t\t*cp = '\\0';\n\t\t\t\tbreak;\n\t\t}\n\t}\n\trp->r_tod = gethms(timep, \"invalid time of day\", FALSE);\n\t/*\n\t** Year work.\n\t*/\n\tcp = loyearp;\n\tif ((lp = byword(cp, begin_years)) != NULL) switch ((int) lp->l_value) {\n\t\tcase YR_MINIMUM:\n\t\t\trp->r_loyear = min_year;\n\t\t\tbreak;\n\t\tcase YR_MAXIMUM:\n\t\t\trp->r_loyear = max_year;\n\t\t\tbreak;\n\t\tdefault:\t/* \"cannot happen\" */\n\t\t\t(void) fprintf(stderr,\n\t\t\t\t\"%s: panic: Invalid l_value %d\\n\",\n\t\t\t\tprogname, lp->l_value);\n\t\t\texit(1);\n\t} else if (sscanf(cp, scheck(cp, \"%d\"), &rp->r_loyear) != 1 ||\n\t\trp->r_loyear < min_year || rp->r_loyear > max_year) {\n\t\t\tif (noise)\n\t\t\t\terror(\"invalid starting year\");\n\t\t\tif (rp->r_loyear > max_year)\n\t\t\t\treturn;\n\t}\n\tcp = hiyearp;\n\tif ((lp = byword(cp, end_years)) != NULL) switch ((int) lp->l_value) {\n\t\tcase YR_MINIMUM:\n\t\t\trp->r_hiyear = min_year;\n\t\t\tbreak;\n\t\tcase YR_MAXIMUM:\n\t\t\trp->r_hiyear = max_year;\n\t\t\tbreak;\n\t\tcase YR_ONLY:\n\t\t\trp->r_hiyear = rp->r_loyear;\n\t\t\tbreak;\n\t\tdefault:\t/* \"cannot happen\" */\n\t\t\t(void) fprintf(stderr,\n\t\t\t\t\"%s: panic: Invalid l_value %d\\n\",\n\t\t\t\tprogname, lp->l_value);\n\t\t\texit(1);\n\t} else if (sscanf(cp, scheck(cp, \"%d\"), &rp->r_hiyear) != 1 ||\n\t\trp->r_hiyear < min_year || rp->r_hiyear > max_year) {\n\t\t\tif (noise)\n\t\t\t\terror(\"invalid ending year\");\n\t\t\tif (rp->r_hiyear < min_year)\n\t\t\t\treturn;\n\t}\n\tif (rp->r_hiyear < min_year)\n \t\treturn;\n \tif (rp->r_loyear < min_year)\n \t\trp->r_loyear = min_year;\n \tif (rp->r_hiyear > max_year)\n \t\trp->r_hiyear = max_year;\n\tif (rp->r_loyear > rp->r_hiyear) {\n\t\terror(\"starting year greater than ending year\");\n\t\treturn;\n\t}\n\tif (*typep == '\\0')\n\t\trp->r_yrtype = NULL;\n\telse {\n\t\tif (rp->r_loyear == rp->r_hiyear) {\n\t\t\terror(\"typed single year\");\n\t\t\treturn;\n\t\t}\n\t\trp->r_yrtype = ecpyalloc(typep);\n\t}\n\t/*\n\t** Day work.\n\t** Accept things such as:\n\t**\t1\n\t**\tlast-Sunday\n\t**\tSun<=20\n\t**\tSun>=7\n\t*/\n\tif ((lp = byword(dayp, lasts)) != NULL) {\n\t\trp->r_dycode = DC_DOWLEQ;\n\t\trp->r_wday = lp->l_value;\n\t\trp->r_dayofmonth = len_months[1][rp->r_month];\n\t} else {\n\t\tif ((cp = index(dayp, '<')) != 0)\n\t\t\trp->r_dycode = DC_DOWLEQ;\n\t\telse if ((cp = index(dayp, '>')) != 0)\n\t\t\trp->r_dycode = DC_DOWGEQ;\n\t\telse {\n\t\t\tcp = dayp;\n\t\t\trp->r_dycode = DC_DOM;\n\t\t}\n\t\tif (rp->r_dycode != DC_DOM) {\n\t\t\t*cp++ = 0;\n\t\t\tif (*cp++ != '=') {\n\t\t\t\terror(\"invalid day of month\");\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tif ((lp = byword(dayp, wday_names)) == NULL) {\n\t\t\t\terror(\"invalid weekday name\");\n\t\t\t\treturn;\n\t\t\t}\n\t\t\trp->r_wday = lp->l_value;\n\t\t}\n\t\tif (sscanf(cp, scheck(cp, \"%d\"), &rp->r_dayofmonth) != 1 ||\n\t\t\trp->r_dayofmonth <= 0 ||\n\t\t\t(rp->r_dayofmonth > len_months[1][rp->r_month])) {\n\t\t\t\terror(\"invalid day of month\");\n\t\t\t\treturn;\n\t\t}\n\t}\n}\n\nstatic void\nputtzcode(long val, FILE *fp)\n{\n\tregister int\tc;\n\tregister int\tshift;\n\n\tfor (shift = 24; shift >= 0; shift -= 8) {\n\t\tc = val >> shift;\n\t\t(void) putc(c, fp);\n\t}\n}\n\nstatic void\nwritezone(char *name)\n{\n\tregister FILE *\t\tfp;\n\tregister int\t\ti;\n\tchar\t\t\tfullname[BUFSIZ];\n\n\tif (strlen(directory) + 1 + strlen(name) >= sizeof fullname) {\n\t\t(void) fprintf(stderr,\n\t\t\t\"%s: File name %s/%s too long\\n\", progname,\n\t\t\tdirectory, name);\n\t\texit(1);\n\t}\n\t(void)snprintf(fullname, sizeof(fullname), \"%s/%s\", directory, name);\n\tif ((fp = fopen(fullname, \"w\")) == NULL) {\n\t\tif (mkdirs(fullname) != 0)\n\t\t\texit(1);\n\t\tif ((fp = fopen(fullname, \"w\")) == NULL) {\n\t\t\t(void) fprintf(stderr, \"%s: Can't create \", progname);\n\t\t\tperror(fullname);\n\t\t\texit(1);\n\t\t}\n\t}\n\t(void) fseek(fp, (long) sizeof ((struct tzhead *) 0)->tzh_reserved, 0);\n\tputtzcode(eitol(timecnt), fp);\n\tputtzcode(eitol(typecnt), fp);\n\tputtzcode(eitol(charcnt), fp);\n\tfor (i = 0; i < timecnt; ++i)\n\t\tputtzcode((long) ats[i], fp);\n\tif (timecnt > 0)\n\t\t(void) fwrite((char *) types, sizeof types[0],\n\t\t\t(int) timecnt, fp);\n\tfor (i = 0; i < typecnt; ++i) {\n\t\tputtzcode((long) gmtoffs[i], fp);\n\t\t(void) putc(isdsts[i], fp);\n\t\t(void) putc(abbrinds[i], fp);\n\t}\n\tif (charcnt != 0)\n\t\t(void) fwrite(chars, sizeof chars[0], (int) charcnt, fp);\n\tif (ferror(fp) || fclose(fp)) {\n\t\t(void) fprintf(stderr, \"%s: Write error on \", progname);\n\t\tperror(fullname);\n\t\texit(1);\n\t}\n}\n\nstatic void\noutzone(struct zone *zpfirst, int zonecount)\n{\n\tregister struct zone *\t\tzp;\n\tregister struct rule *\t\trp;\n\tregister int\t\t\ti, j;\n\tregister int\t\t\tusestart, useuntil;\n\tregister time_t\t\t\tstarttime = 0, untiltime = 0;\n\tregister long\t\t\tgmtoff;\n\tregister long\t\t\tstdoff;\n\tregister int\t\t\tyear;\n\tregister long\t\t\tstartoff = 0;\n\tregister int\t\t\tstartisdst;\n\tregister int\t\t\ttype;\n\tchar\t\t\t\tstartbuf[BUFSIZ];\n\n\t/*\n\t** Now. . .finally. . .generate some useful data!\n\t*/\n\ttimecnt = 0;\n\ttypecnt = 0;\n\tcharcnt = 0;\n\t/*\n\t** Two guesses. . .the second may well be corrected later.\n\t*/\n\tgmtoff = zpfirst->z_gmtoff;\n\tstdoff = 0;\n\tfor (i = 0; i < zonecount; ++i) {\n\t\tusestart = i > 0;\n\t\tuseuntil = i < (zonecount - 1);\n\t\tzp = &zpfirst[i];\n\t\teat(zp->z_filename, zp->z_linenum);\n\t\tstartisdst = -1;\n\t\tif (zp->z_nrules == 0) {\n\t\t\ttype = addtype(oadd(zp->z_gmtoff, zp->z_stdoff),\n\t\t\t\tzp->z_format, zp->z_stdoff != 0);\n\t\t\tif (usestart)\n\t\t\t\taddtt(starttime, type);\n\t\t\tgmtoff = zp->z_gmtoff;\n\t\t\tstdoff = zp->z_stdoff;\n\t\t} else for (year = min_year; year <= max_year; ++year) {\n\t\t\tif (useuntil && year > zp->z_untilrule.r_hiyear)\n\t\t\t\tbreak;\n\t\t\t/*\n\t\t\t** Mark which rules to do in the current year.\n\t\t\t** For those to do, calculate rpytime(rp, year);\n\t\t\t*/\n\t\t\tfor (j = 0; j < zp->z_nrules; ++j) {\n\t\t\t\trp = &zp->z_rules[j];\n\t\t\t\teats(zp->z_filename, zp->z_linenum,\n\t\t\t\t\trp->r_filename, rp->r_linenum);\n\t\t\t\trp->r_todo = year >= rp->r_loyear &&\n\t\t\t\t\t\tyear <= rp->r_hiyear &&\n\t\t\t\t\t\tyearistype(year, rp->r_yrtype);\n\t\t\t\tif (rp->r_todo)\n\t\t\t\t\trp->r_temp = rpytime(rp, year);\n\t\t\t}\n\t\t\tfor ( ; ; ) {\n\t\t\t\tregister int\tk;\n\t\t\t\tregister time_t\tjtime, ktime = 0;\n\t\t\t\tregister long\toffset;\n\t\t\t\tchar\t\tbuf[BUFSIZ];\n\n\t\t\t\tif (useuntil) {\n\t\t\t\t\t/*\n\t\t\t\t\t** Turn untiltime into GMT\n\t\t\t\t\t** assuming the current gmtoff and\n\t\t\t\t\t** stdoff values.\n\t\t\t\t\t*/\n\t\t\t\t\toffset = gmtoff;\n\t\t\t\t\tif (!zp->z_untilrule.r_todisstd)\n\t\t\t\t\t\toffset = oadd(offset, stdoff);\n\t\t\t\t\tuntiltime = tadd(zp->z_untiltime,\n\t\t\t\t\t\t-offset);\n\t\t\t\t}\n\t\t\t\t/*\n\t\t\t\t** Find the rule (of those to do, if any)\n\t\t\t\t** that takes effect earliest in the year.\n\t\t\t\t*/\n\t\t\t\tk = -1;\n\t\t\t\tfor (j = 0; j < zp->z_nrules; ++j) {\n\t\t\t\t\trp = &zp->z_rules[j];\n\t\t\t\t\tif (!rp->r_todo)\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\teats(zp->z_filename, zp->z_linenum,\n\t\t\t\t\t\trp->r_filename, rp->r_linenum);\n\t\t\t\t\toffset = gmtoff;\n\t\t\t\t\tif (!rp->r_todisstd)\n\t\t\t\t\t\toffset = oadd(offset, stdoff);\n\t\t\t\t\tjtime = rp->r_temp;\n\t\t\t\t\tif (jtime == min_time ||\n\t\t\t\t\t\tjtime == max_time)\n\t\t\t\t\t\t\tcontinue;\n\t\t\t\t\tjtime = tadd(jtime, -offset);\n\t\t\t\t\tif (k < 0 || jtime < ktime) {\n\t\t\t\t\t\tk = j;\n\t\t\t\t\t\tktime = jtime;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif (k < 0)\n\t\t\t\t\tbreak;\t/* go on to next year */\n\t\t\t\trp = &zp->z_rules[k];\n\t\t\t\trp->r_todo = FALSE;\n\t\t\t\tif (useuntil && ktime >= untiltime)\n\t\t\t\t\tbreak;\n\t\t\t\tif (usestart) {\n\t\t\t\t\tif (ktime < starttime) {\n\t\t\t\t\t\tstdoff = rp->r_stdoff;\n\t\t\t\t\t\tstartoff = oadd(zp->z_gmtoff,\n\t\t\t\t\t\t\trp->r_stdoff);\n\t\t\t\t\t\t(void)snprintf(startbuf,\n\t\t\t\t\t\t\tsizeof(startbuf),\n\t\t\t\t\t\t\tzp->z_format,\n\t\t\t\t\t\t\trp->r_abbrvar);\n\t\t\t\t\t\tstartisdst =\n\t\t\t\t\t\t\trp->r_stdoff != 0;\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\t}\n\t\t\t\t\tif (ktime != starttime &&\n\t\t\t\t\t\tstartisdst >= 0)\naddtt(starttime, addtype(startoff, startbuf, startisdst));\n\t\t\t\t\tusestart = FALSE;\n\t\t\t\t}\n\t\t\t\teats(zp->z_filename, zp->z_linenum,\n\t\t\t\t\trp->r_filename, rp->r_linenum);\n\t\t\t\t(void)snprintf(buf, sizeof(buf), zp->z_format,\n\t\t\t\t\trp->r_abbrvar);\n\t\t\t\toffset = oadd(zp->z_gmtoff, rp->r_stdoff);\n\t\t\t\ttype = addtype(offset, buf, rp->r_stdoff != 0);\n\t\t\t\tif (timecnt != 0 || rp->r_stdoff != 0)\n\t\t\t\t\taddtt(ktime, type);\n\t\t\t\tgmtoff = zp->z_gmtoff;\n\t\t\t\tstdoff = rp->r_stdoff;\n\t\t\t}\n\t\t}\n\t\t/*\n\t\t** Now we may get to set starttime for the next zone line.\n\t\t*/\n\t\tif (useuntil)\n\t\t\tstarttime = tadd(zp->z_untiltime,\n\t\t\t\t-gmtoffs[types[timecnt - 1]]);\n\t}\n\twritezone(zpfirst->z_name);\n}\n\nstatic void\naddtt(time_t starttime, int type)\n{\n\tif (timecnt != 0 && type == types[timecnt - 1])\n\t\treturn;\t/* easy enough! */\n\tif (timecnt >= TZ_MAX_TIMES) {\n\t\terror(\"too many transitions?!\");\n\t\texit(1);\n\t}\n\tats[timecnt] = starttime;\n\ttypes[timecnt] = type;\n\t++timecnt;\n}\n\nstatic int\naddtype(long gmtoff, char *abbr, int isdst)\n{\n\tregister int\ti, j;\n\n\t/*\n\t** See if there's already an entry for this zone type.\n\t** If so, just return its index.\n\t*/\n\tfor (i = 0; i < typecnt; ++i) {\n\t\tif (gmtoff == gmtoffs[i] && isdst == isdsts[i] &&\n\t\t\tstrcmp(abbr, &chars[(int)abbrinds[i]]) == 0)\n\t\t\t\treturn i;\n\t}\n\t/*\n\t** There isn't one; add a new one, unless there are already too\n\t** many.\n\t*/\n\tif (typecnt >= TZ_MAX_TYPES) {\n\t\terror(\"too many local time types\");\n\t\texit(1);\n\t}\n\tgmtoffs[i] = gmtoff;\n\tisdsts[i] = isdst;\n\n\tfor (j = 0; j < charcnt; ++j)\n\t\tif (strcmp(&chars[j], abbr) == 0)\n\t\t\tbreak;\n\tif (j == charcnt)\n\t\tnewabbr(abbr);\n\tabbrinds[i] = j;\n\t++typecnt;\n\treturn i;\n}\n\nstatic int\nyearistype(int year, char *type)\n{\n\tchar\tbuf[BUFSIZ];\n\tint\tresult;\n\n\tif (type == NULL || *type == '\\0')\n\t\treturn TRUE;\n\tif (strcmp(type, \"uspres\") == 0)\n\t\treturn (year % 4) == 0;\n\tif (strcmp(type, \"nonpres\") == 0)\n\t\treturn (year % 4) != 0;\n\t(void)snprintf(buf, sizeof(buf), \"yearistype %d %s\", year, type);\n\tresult = system(buf);\n\tif (result == 0)\n\t\treturn TRUE;\n\tif (result == 1 << 8)\n\t\treturn FALSE;\n\terror(\"Wild result from command execution\");\n\t(void) fprintf(stderr, \"%s: command was '%s', result was %d\\n\",\n\t\tprogname, buf, result);\n\tfor ( ; ; )\n\t\texit(1);\n}\n\nstatic int\nlowerit(int a)\n{\n\treturn (isascii(a) && isupper(a)) ? tolower(a) : a;\n}\n\nstatic int\nciequal(char *ap, char *bp)\t/* case-insensitive equality */\n{\n\twhile (lowerit(*ap) == lowerit(*bp++))\n\t\tif (*ap++ == '\\0')\n\t\t\treturn TRUE;\n\treturn FALSE;\n}\n\nstatic int\nisabbr(char *abbr, char *word)\n{\n\tif (lowerit(*abbr) != lowerit(*word))\n\t\treturn FALSE;\n\t++word;\n\twhile (*++abbr != '\\0')\n\t\tdo if (*word == '\\0')\n\t\t\treturn FALSE;\n\t\t\t\twhile (lowerit(*word++) != lowerit(*abbr));\n\treturn TRUE;\n}\n\nstatic struct lookup *\nbyword(char *word, struct lookup *table)\n{\n\tregister struct lookup *\tfoundlp;\n\tregister struct lookup *\tlp;\n\n\tif (word == NULL || table == NULL)\n\t\treturn NULL;\n\t/*\n\t** Look for exact match.\n\t*/\n\tfor (lp = table; lp->l_word != NULL; ++lp)\n\t\tif (ciequal(word, lp->l_word))\n\t\t\treturn lp;\n\t/*\n\t** Look for inexact match.\n\t*/\n\tfoundlp = NULL;\n\tfor (lp = table; lp->l_word != NULL; ++lp)\n\t\tif (isabbr(word, lp->l_word)) {\n\t\t\tif (foundlp == NULL)\n\t\t\t\tfoundlp = lp;\n\t\t\telse\treturn NULL;\t/* multiple inexact matches */\n                }\n\treturn foundlp;\n}\n\nstatic char **\ngetfields(char *cp)\n{\n\tregister char *\t\tdp;\n\tregister char **\tarray;\n\tregister int\t\tnsubs;\n\n\tif (cp == NULL)\n\t\treturn NULL;\n\tarray = (char **) emalloc((strlen(cp) + 1) * sizeof *array);\n\tnsubs = 0;\n\tfor ( ; ; ) {\n\t\twhile (isascii(*cp) && isspace(*cp))\n\t\t\t++cp;\n\t\tif (*cp == '\\0' || *cp == '#')\n\t\t\tbreak;\n\t\tarray[nsubs++] = dp = cp;\n\t\tdo {\n\t\t\tif ((*dp = *cp++) != '\"')\n\t\t\t\t++dp;\n\t\t\telse while ((*dp = *cp++) != '\"')\n\t\t\t\tif (*dp != '\\0')\n\t\t\t\t\t++dp;\n\t\t\t\telse\terror(\"Odd number of quotation marks\");\n\t\t} while (*cp != '\\0' && *cp != '#' &&\n\t\t\t(!isascii(*cp) || !isspace(*cp)));\n\t\tif (isascii(*cp) && isspace(*cp))\n\t\t\t++cp;\n\t\t*dp = '\\0';\n\t}\n\tarray[nsubs] = NULL;\n\treturn array;\n}\n\nstatic long\noadd(long t1, long t2)\n{\n\tregister long\tt;\n\n\tt = t1 + t2;\n\tif ((t2 > 0 && t <= t1) ||\n            (t2 < 0 && t >= t1)) {\n\t\terror(\"time overflow\");\n\t\texit(1);\n\t}\n\treturn t;\n}\n\nstatic time_t\ntadd(time_t t1, long t2)\n{\n\tregister time_t\tt;\n\n\tif (t1 == max_time && t2 > 0)\n\t\treturn max_time;\n\tif (t1 == min_time && t2 < 0)\n\t\treturn min_time;\n\tt = t1 + t2;\n\tif ((t2 > 0 && t <= t1) ||\n            (t2 < 0 && t >= t1)) {\n\t\terror(\"time overflow\");\n\t\texit(1);\n\t}\n\treturn t;\n}\n\n/*\n** Given a rule, and a year, compute the date - in seconds since January 1,\n** 1970, 00:00 LOCAL time - in that year that the rule refers to.\n*/\n\nstatic time_t\nrpytime(struct rule *rp, int wantedy)\n{\n\tregister int\ty, m, i;\n\tregister long\tdayoff;\t\t\t/* with a nod to Margaret O. */\n\tregister time_t\tt;\n\n\tdayoff = 0;\n\tm = TM_JANUARY;\n\ty = EPOCH_YEAR;\n\twhile (wantedy != y) {\n\t\tif (wantedy > y) {\n\t\t\ti = len_years[isleap(y)];\n\t\t\t++y;\n\t\t} else {\n\t\t\t--y;\n\t\t\ti = -len_years[isleap(y)];\n\t\t}\n\t\tdayoff = oadd(dayoff, eitol(i));\n\t}\n\twhile (m != rp->r_month) {\n\t\ti = len_months[isleap(y)][m];\n\t\tdayoff = oadd(dayoff, eitol(i));\n\t\t++m;\n\t}\n\ti = rp->r_dayofmonth;\n\tif (m == TM_FEBRUARY && i == 29 && !isleap(y)) {\n\t\tif (rp->r_dycode == DC_DOWLEQ)\n\t\t\t--i;\n\t\telse {\n\t\t\terror(\"use of 2/29 in non leap-year\");\n\t\t\texit(1);\n\t\t}\n\t}\n\t--i;\n\tdayoff = oadd(dayoff, eitol(i));\n\tif (rp->r_dycode == DC_DOWGEQ || rp->r_dycode == DC_DOWLEQ) {\n\t\tregister long\twday;\n\n#define LDAYS_PER_WEEK\t((long) DAYS_PER_WEEK)\n\t\twday = eitol(EPOCH_WDAY);\n\t\t/*\n\t\t** Don't trust mod of negative numbers.\n\t\t*/\n\t\tif (dayoff >= 0)\n\t\t\twday = (wday + dayoff) % LDAYS_PER_WEEK;\n\t\telse {\n\t\t\twday -= ((-dayoff) % LDAYS_PER_WEEK);\n\t\t\tif (wday < 0)\n\t\t\t\twday += LDAYS_PER_WEEK;\n\t\t}\n\t\twhile (wday != eitol(rp->r_wday))\n\t\t\tif (rp->r_dycode == DC_DOWGEQ) {\n\t\t\t\tdayoff = oadd(dayoff, (long) 1);\n\t\t\t\tif (++wday >= LDAYS_PER_WEEK)\n\t\t\t\t\twday = 0;\n\t\t\t\t++i;\n\t\t\t} else {\n\t\t\t\tdayoff = oadd(dayoff, (long) -1);\n\t\t\t\tif (--wday < 0)\n\t\t\t\t\twday = LDAYS_PER_WEEK;\n\t\t\t\t--i;\n\t\t\t}\n\t\tif (i < 0 || i >= len_months[isleap(y)][m]) {\n\t\t\terror(\"no day in month matches rule\");\n\t\t\texit(1);\n\t\t}\n\t}\n\tif (dayoff < 0 && !tt_signed) {\n\t\tif (wantedy == rp->r_loyear)\n\t\t\treturn min_time;\n\t\terror(\"time before zero\");\n\t\texit(1);\n\t}\n\tt = (time_t) dayoff * SECS_PER_DAY;\n\t/*\n\t** Cheap overflow check.\n\t*/\n\tif (t / SECS_PER_DAY != dayoff) {\n\t\tif (wantedy == rp->r_hiyear)\n\t\t\treturn max_time;\n\t\tif (wantedy == rp->r_loyear)\n\t\t\treturn min_time;\n\t\terror(\"time overflow\");\n\t\texit(1);\n\t}\n\treturn tadd(t, rp->r_tod);\n}\n\nstatic void\nnewabbr(char *string)\n{\n\tregister int\ti;\n\n\ti = strlen(string) + 1;\n\tif (charcnt + i >= TZ_MAX_CHARS) {\n\t\terror(\"too many, or too long, time zone abbreviations\");\n\t\texit(1);\n\t}\n\t(void)strlcpy(&chars[charcnt], string, sizeof(chars) - charcnt);\n\tcharcnt += eitol(i);\n}\n\nstatic int\nmkdirs(char *name)\n{\n\tregister char *\tcp;\n\n\tif ((cp = name) == NULL || *cp == '\\0')\n\t\treturn 0;\n\twhile ((cp = index(cp + 1,'/')) != 0) {\n\t\t*cp = '\\0';\n\t\tif (access(name,F_OK) && mkdir(name,0755)) {\n\t\t\tperror(name);\n\t\t\treturn -1;\n\t\t}\n\t\t*cp = '/';\n\t}\n\treturn 0;\n}\n\nstatic long\neitol(int i)\n{\n\tlong\tl;\n\n\tl = i;\n\tif ((i < 0 && l >= 0) ||\n            (i == 0 && l != 0) ||\n            (i > 0 && l <= 0)) {\n\t\t(void) fprintf(stderr, \"%s: %d did not sign extend correctly\\n\",\n\t\t\tprogname, i);\n\t\texit(1);\n\t}\n\treturn l;\n}\n\n/*\n** UNIX is a registered trademark of AT&T.\n*/\n"
  },
  {
    "path": "sys/arch/arm/include/cmsis_gcc.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_gcc.h\n * @brief    CMSIS Cortex-M Core Function/Instruction Header File\n * @version  V4.30\n * @date     20. October 2015\n ******************************************************************************/\n/* Copyright (c) 2009 - 2015 ARM LIMITED\n\n   All rights reserved.\n   Redistribution and use in source and binary forms, with or without\n   modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n   *\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n   POSSIBILITY OF SUCH DAMAGE.\n   ---------------------------------------------------------------------------*/\n\n\n#ifndef __CMSIS_GCC_H\n#define __CMSIS_GCC_H\n\n/* ignore some GCC warnings */\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wsign-conversion\"\n#pragma GCC diagnostic ignored \"-Wconversion\"\n#pragma GCC diagnostic ignored \"-Wunused-parameter\"\n#endif\n\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\n{\n  __ASM volatile (\"cpsie i\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\n  Can only be executed in Privileged modes.\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\n{\n  __ASM volatile (\"cpsid i\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\n{\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\n}\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n\n    \\return               xPSR Register value\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\n{\n  register uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp\\n\"  : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp, %0\\n\" : : \"r\" (topOfProcStack) : \"sp\");\n}\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\n{\n  register uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp\\n\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n\n    \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp, %0\\n\" : : \"r\" (topOfMainStack) : \"sp\");\n}\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\n}\n\n\n#if       (__CORTEX_M >= 0x03U)\n\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\n{\n  __ASM volatile (\"cpsie f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\n{\n  __ASM volatile (\"cpsid f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\n{\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (value) : \"memory\");\n}\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)\n{\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (value) : \"memory\");\n}\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n\n#endif /* (__CORTEX_M >= 0x03U) */\n\n\n#if       (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\n{\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\n  uint32_t result;\n\n  /* Empty asm statement works as a scheduling barrier */\n  __ASM volatile (\"\");\n  __ASM volatile (\"VMRS %0, fpscr\" : \"=r\" (result) );\n  __ASM volatile (\"\");\n  return(result);\n#else\n   return(0);\n#endif\n}\n\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\n{\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\n  /* Empty asm statement works as a scheduling barrier */\n  __ASM volatile (\"\");\n  __ASM volatile (\"VMSR fpscr, %0\" : : \"r\" (fpscr) : \"vfpcc\");\n  __ASM volatile (\"\");\n#endif\n}\n\n#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */\n\n\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/* Define macros for porting to both thumb1 and thumb2.\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\n * Otherwise, use general registers, specified by constraint \"r\" */\n#if defined (__thumb__) && !defined (__thumb2__)\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\n#else\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\n#endif\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)\n{\n  __ASM volatile (\"nop\");\n}\n\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)\n{\n  __ASM volatile (\"wfi\");\n}\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n    a low-power state until one of a number of events occurs.\n */\n__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)\n{\n  __ASM volatile (\"wfe\");\n}\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)\n{\n  __ASM volatile (\"sev\");\n}\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)\n{\n  __ASM volatile (\"isb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)\n{\n  __ASM volatile (\"dsb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)\n{\n  __ASM volatile (\"dmb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in integer value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)\n{\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\n  return __builtin_bswap32(value);\n#else\n  uint32_t result;\n\n  __ASM volatile (\"rev %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n#endif\n}\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in two unsigned short values.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rev16 %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n}\n\n\n/**\n  \\brief   Reverse byte order in signed short value\n  \\details Reverses the byte order in a signed short value with sign extension to integer.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)\n{\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n  return (short)__builtin_bswap16(value);\n#else\n  int32_t result;\n\n  __ASM volatile (\"revsh %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n#endif\n}\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    value  Value to rotate\n  \\param [in]    value  Number of Bits to rotate\n  \\return               Rotated value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\n{\n  return (op1 >> op2) | (op1 << (32U - op2));\n}\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)                       __ASM volatile (\"bkpt \"#value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\n{\n  uint32_t result;\n\n#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\n   __ASM volatile (\"rbit %0, %1\" : \"=r\" (result) : \"r\" (value) );\n#else\n  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\n\n  result = value;                      /* r will be reversed bits of v; first get LSB of v */\n  for (value >>= 1U; value; value >>= 1U)\n  {\n    result <<= 1U;\n    result |= value & 1U;\n    s--;\n  }\n  result <<= s;                        /* shift when v's highest bits are zero */\n#endif\n  return(result);\n}\n\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n#define __CLZ             __builtin_clz\n\n\n#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\n\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrexb %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrexb %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\n#endif\n   return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrexh %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrexh %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\n#endif\n   return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldrex %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strexb %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strexh %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strex %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" (value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)\n{\n  __ASM volatile (\"clrex\" ::: \"memory\");\n}\n\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT(ARG1,ARG2) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT(ARG1,ARG2) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrbt %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\n#endif\n   return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrht %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\n#endif\n   return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n   return(result);\n}\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)\n{\n   __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)\n{\n   __ASM volatile (\"strht %1, %0\" : \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)\n{\n   __ASM volatile (\"strt %1, %0\" : \"=Q\" (*addr) : \"r\" (value) );\n}\n\n#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if (__CORTEX_M >= 0x04U)  /* only for Cortex-M4 and above */\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usad8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usada8 %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#define __SSAT16(ARG1,ARG2) \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n#define __USAT16(ARG1,ARG2) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuad %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuadx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlad %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smladx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusdx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsd %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsdx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sel %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n#define __PKHBT(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  __ASM (\"pkhbt %0, %1, %2, lsl %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n\n#define __PKHTB(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  if (ARG3 == 0) \\\n    __ASM (\"pkhtb %0, %1, %2\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2)  ); \\\n  else \\\n    __ASM (\"pkhtb %0, %1, %2, asr %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\n{\n int32_t result;\n\n __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\n return(result);\n}\n\n#endif /* (__CORTEX_M >= 0x04) */\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n#endif /* __CMSIS_GCC_H */\n"
  },
  {
    "path": "sys/arch/arm/include/core_cm4.h",
    "content": "/**************************************************************************//**\n * @file     core_cm4.h\n * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File\n * @version  V4.30\n * @date     20. October 2015\n ******************************************************************************/\n/* Copyright (c) 2009 - 2015 ARM LIMITED\n\n   All rights reserved.\n   Redistribution and use in source and binary forms, with or without\n   modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n   *\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n   POSSIBILITY OF SUCH DAMAGE.\n   ---------------------------------------------------------------------------*/\n\n\n#if   defined ( __ICCARM__ )\n #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM4_H_GENERIC\n#define __CORE_CM4_H_GENERIC\n\n#include <sys/stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M4\n  @{\n */\n\n/*  CMSIS CM4 definitions */\n#define __CM4_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */\n#define __CM4_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */\n#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM4_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */\n\n#define __CORTEX_M                (0x04U)                                      /*!< Cortex-M Core */\n\n\n#if   defined ( __CC_ARM )\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\n  #define __STATIC_INLINE  static __inline\n\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */\n  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */\n  #define __STATIC_INLINE  static __inline\n\n#elif defined ( __GNUC__ )\n  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */\n  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */\n  #define __STATIC_INLINE  static inline\n\n#elif defined ( __ICCARM__ )\n  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */\n  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\n  #define __STATIC_INLINE  static inline\n\n#elif defined ( __TMS470__ )\n  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */\n  #define __STATIC_INLINE  static inline\n\n#elif defined ( __TASKING__ )\n  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */\n  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */\n  #define __STATIC_INLINE  static inline\n\n#elif defined ( __CSMC__ )\n  #define __packed\n  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */\n  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\n  #define __STATIC_INLINE  static inline\n\n#else\n  #error Unknown compiler\n#endif\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #if (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #if (__FPU_PRESENT == 1)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #if (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TMS470__ )\n  #if defined __TI_VFP_SUPPORT__\n    #if (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #if (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"core_cmInstr.h\"                /* Core Instruction Access */\n#include \"core_cmFunc.h\"                 /* Core Function Access */\n#include \"core_cmSimd.h\"                 /* Compiler specific SIMD Intrinsics */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM4_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM4_H_DEPENDANT\n#define __CORE_CM4_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM4_REV\n    #define __CM4_REV               0x0000U\n    #warning \"__CM4_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M4 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */\n    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[24U];\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[24U];\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[24U];\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[24U];\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[56U];\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED5[644U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[5U];\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */\n#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */\n\n#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */\n#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */\n\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\n\n#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\n#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\n\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[29U];\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[6U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Integration Write Register Definitions */\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\n\n/* ITM Integration Read Register Definitions */\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\n\n/* ITM Integration Mode Control Register Definitions */\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Mask Register Definitions */\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\n\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\n\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\n\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\n\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\n\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */\n#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */\n#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\n} MPU_Type;\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if (__FPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and FP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and FP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/*@} end of group CMSIS_FPU */\n#endif\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Cortex-M4 Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\n\n#if (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n#if (__FPU_PRESENT == 1U)\n  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */\n  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */\n#endif\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable External Interrupt\n  \\details Enables a device-specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\n */\n__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\n}\n\n\n/**\n  \\brief   Disable External Interrupt\n  \\details Disables a device-specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\n */\n__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\n  \\param [in]      IRQn  Interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n */\n__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of an external interrupt.\n  \\param [in]      IRQn  Interrupt number. Value cannot be negative.\n */\n__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of an external interrupt.\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\n */\n__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in NVIC and returns the active bit.\n  \\param [in]      IRQn  Interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n */\n__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\n{\n  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of an interrupt.\n  \\note    The priority cannot be set for every core interrupt.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n */\n__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) < 0)\n  {\n    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of an interrupt.\n           The interrupt number can be positive to specify an external (device specific) interrupt,\n           or negative to specify an internal (core) interrupt.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) < 0)\n  {\n    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__STATIC_INLINE void NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM4_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "sys/arch/arm/include/core_cmFunc.h",
    "content": "/**************************************************************************//**\n * @file     core_cmFunc.h\n * @brief    CMSIS Cortex-M Core Function Access Header File\n * @version  V4.30\n * @date     20. October 2015\n ******************************************************************************/\n/* Copyright (c) 2009 - 2015 ARM LIMITED\n\n   All rights reserved.\n   Redistribution and use in source and binary forms, with or without\n   modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n   *\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n   POSSIBILITY OF SUCH DAMAGE.\n   ---------------------------------------------------------------------------*/\n\n\n#if   defined ( __ICCARM__ )\n #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CMFUNC_H\n#define __CORE_CMFUNC_H\n\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n*/\n\n/*------------------ RealView Compiler -----------------*/\n#if   defined ( __CC_ARM )\n  #include \"cmsis_armcc.h\"\n\n/*------------------ ARM Compiler V6 -------------------*/\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #include \"cmsis_armcc_V6.h\"\n\n/*------------------ GNU Compiler ----------------------*/\n#elif defined ( __GNUC__ )\n  #include \"cmsis_gcc.h\"\n\n/*------------------ ICC Compiler ----------------------*/\n#elif defined ( __ICCARM__ )\n  #include <cmsis_iar.h>\n\n/*------------------ TI CCS Compiler -------------------*/\n#elif defined ( __TMS470__ )\n  #include <cmsis_ccs.h>\n\n/*------------------ TASKING Compiler ------------------*/\n#elif defined ( __TASKING__ )\n  /*\n   * The CMSIS functions have been implemented as intrinsics in the compiler.\n   * Please use \"carm -?i\" to get an up to date list of all intrinsics,\n   * Including the CMSIS ones.\n   */\n\n/*------------------ COSMIC Compiler -------------------*/\n#elif defined ( __CSMC__ )\n  #include <cmsis_csm.h>\n\n#endif\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n#endif /* __CORE_CMFUNC_H */\n"
  },
  {
    "path": "sys/arch/arm/include/core_cmInstr.h",
    "content": "/**************************************************************************//**\n * @file     core_cmInstr.h\n * @brief    CMSIS Cortex-M Core Instruction Access Header File\n * @version  V4.30\n * @date     20. October 2015\n ******************************************************************************/\n/* Copyright (c) 2009 - 2015 ARM LIMITED\n\n   All rights reserved.\n   Redistribution and use in source and binary forms, with or without\n   modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n   *\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n   POSSIBILITY OF SUCH DAMAGE.\n   ---------------------------------------------------------------------------*/\n\n\n#if   defined ( __ICCARM__ )\n #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CMINSTR_H\n#define __CORE_CMINSTR_H\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/*------------------ RealView Compiler -----------------*/\n#if   defined ( __CC_ARM )\n  #include \"cmsis_armcc.h\"\n\n/*------------------ ARM Compiler V6 -------------------*/\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #include \"cmsis_armcc_V6.h\"\n\n/*------------------ GNU Compiler ----------------------*/\n#elif defined ( __GNUC__ )\n  #include \"cmsis_gcc.h\"\n\n/*------------------ ICC Compiler ----------------------*/\n#elif defined ( __ICCARM__ )\n  #include <cmsis_iar.h>\n\n/*------------------ TI CCS Compiler -------------------*/\n#elif defined ( __TMS470__ )\n  #include <cmsis_ccs.h>\n\n/*------------------ TASKING Compiler ------------------*/\n#elif defined ( __TASKING__ )\n  /*\n   * The CMSIS functions have been implemented as intrinsics in the compiler.\n   * Please use \"carm -?i\" to get an up to date list of all intrinsics,\n   * Including the CMSIS ones.\n   */\n\n/*------------------ COSMIC Compiler -------------------*/\n#elif defined ( __CSMC__ )\n  #include <cmsis_csm.h>\n\n#endif\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n#endif /* __CORE_CMINSTR_H */\n"
  },
  {
    "path": "sys/arch/arm/include/core_cmSimd.h",
    "content": "/**************************************************************************//**\n * @file     core_cmSimd.h\n * @brief    CMSIS Cortex-M SIMD Header File\n * @version  V4.30\n * @date     20. October 2015\n ******************************************************************************/\n/* Copyright (c) 2009 - 2015 ARM LIMITED\n\n   All rights reserved.\n   Redistribution and use in source and binary forms, with or without\n   modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n   *\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n   POSSIBILITY OF SUCH DAMAGE.\n   ---------------------------------------------------------------------------*/\n\n\n#if   defined ( __ICCARM__ )\n #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CMSIMD_H\n#define __CORE_CMSIMD_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n/*------------------ RealView Compiler -----------------*/\n#if   defined ( __CC_ARM )\n  #include \"cmsis_armcc.h\"\n\n/*------------------ ARM Compiler V6 -------------------*/\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #include \"cmsis_armcc_V6.h\"\n\n/*------------------ GNU Compiler ----------------------*/\n#elif defined ( __GNUC__ )\n  #include \"cmsis_gcc.h\"\n\n/*------------------ ICC Compiler ----------------------*/\n#elif defined ( __ICCARM__ )\n  #include <cmsis_iar.h>\n\n/*------------------ TI CCS Compiler -------------------*/\n#elif defined ( __TMS470__ )\n  #include <cmsis_ccs.h>\n\n/*------------------ TASKING Compiler ------------------*/\n#elif defined ( __TASKING__ )\n  /*\n   * The CMSIS functions have been implemented as intrinsics in the compiler.\n   * Please use \"carm -?i\" to get an up to date list of all intrinsics,\n   * Including the CMSIS ones.\n   */\n\n/*------------------ COSMIC Compiler -------------------*/\n#elif defined ( __CSMC__ )\n  #include <cmsis_csm.h>\n\n#endif\n\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CMSIMD_H */\n"
  },
  {
    "path": "sys/arch/pic32/conf/BAREMETAL.ld",
    "content": "/*\n * Linker script for PIC32 firmware.\n */\nOUTPUT_FORMAT(\"elf32-littlemips\", \"elf32-bigmips\",\n\t      \"elf32-littlemips\")\nOUTPUT_ARCH(mips)\nENTRY(_reset_vector_)\nMEMORY\n{\n  ram                  (rw!x): ORIGIN = 0x80000000, LENGTH = 26K\n  u0area               (rw!x): ORIGIN = 0x80006800, LENGTH = 3K\n  uarea                (rw!x): ORIGIN = 0x80007400, LENGTH = 3K\n  devcfg               (r)   : ORIGIN = 0x9fc02ff0, LENGTH = 16\n\n  /* Required by Microchip C32 linker */\n  kseg0_program_mem    (rx)  : ORIGIN = 0x9D000000, LENGTH = 512K\n  exception_mem        (rx)  : ORIGIN = 0x9D000000, LENGTH = 0x1000\n  kseg0_boot_mem       (rx)  : ORIGIN = 0x9FC00000, LENGTH = 12K-16\n  kseg1_boot_mem       (rx)  : ORIGIN = 0xBFC00000, LENGTH = 0x490\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x20000\n}\n\n/* higher address of the user mode stack */\nu0\t= ORIGIN(u0area);\nu\t= ORIGIN(uarea);\nu_end\t= ORIGIN(uarea) + LENGTH(uarea);\n\nSECTIONS\n{\n  /* Read-only sections, merged into text segment: */\n  . = 0x0000;\n  .interp         : { *(.interp) }\n  .hash           : { *(.hash) }\n  .dynsym         : { *(.dynsym) }\n  .dynstr         : { *(.dynstr) }\n  .gnu.version    : { *(.gnu.version) }\n  .gnu.version_d  : { *(.gnu.version_d) }\n  .gnu.version_r  : { *(.gnu.version_r) }\n  .rel.init       : { *(.rel.init) }\n  .rela.init      : { *(.rela.init) }\n  .rel.text       : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }\n  .rela.text      : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }\n  .rel.fini       : { *(.rel.fini) }\n  .rela.fini      : { *(.rela.fini) }\n  .rel.rodata     : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }\n  .rela.rodata    : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }\n  .rel.data       : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }\n  .rela.data      : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) }\n  .rel.ctors      : { *(.rel.ctors) }\n  .rela.ctors     : { *(.rela.ctors) }\n  .rel.dtors      : { *(.rel.dtors) }\n  .rela.dtors     : { *(.rela.dtors) }\n  .rel.got        : { *(.rel.got) }\n  .rela.got       : { *(.rela.got) }\n  .rel.sdata      : { *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) }\n  .rela.sdata     : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) }\n  .rel.sbss       : { *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) }\n  .rela.sbss      : { *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) }\n  .rel.sdata2     : { *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) }\n  .rela.sdata2    : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) }\n  .rel.sbss2      : { *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) }\n  .rela.sbss2     : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) }\n  .rel.bss        : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }\n  .rela.bss       : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }\n  .rel.plt        : { *(.rel.plt) }\n  .rela.plt       : { *(.rela.plt) }\n  .plt            : { *(.plt) }\n\n  .boot           :\n  {\n    /* Execution starts here. */\n    *(.startup)\n  } > kseg0_boot_mem\n\n  .text           :\n  {\n    /* Exception handlers. */\n    *(.exception)\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    /* .gnu.warning sections are handled specially by elf32.em.  */\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7)\n    __rodata_start = . ;\n    *(.rodata .rodata.* .gnu.linkonce.r.* .rel.dyn)\n    __abiflags = . ;\n    *(.MIPS.abiflags)\n    *(.dinit)\n    /* Align here to ensure that the .text section ends on word boundary. */\n    . = ALIGN (32 / 8);\n    _etext = .;\n  } > kseg0_program_mem\n\n  /* Start data (internal SRAM).  */\n  .data\t\t  : AT (ADDR (.text) + SIZEOF (.text))\n  {\n    __data_start = . ;\n    _gp = .; \t/* We have only 32k RAM on MC-24, so no need for 0x8000 offset. */\n    *(.data .data.* .gnu.linkonce.d.*)\n    /* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  */\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n    *(.eh_frame)\n    _edata = .;\n  } > ram\n\n  /* Device configuration.  */\n  .config         :\n  {\n    *(.config3)\n    *(.config2)\n    *(.config1)\n    *(.config0)\n  } > devcfg\n\n  .bss ADDR (.data) + SIZEOF (.data) (NOLOAD) :\n  {\n   __bss_start = .;\n   *(.dynbss)\n   *(.sbss .sbss.*)\n   *(.scommon)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   /* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.  */\n   . = ALIGN (32 / 8);\n  } > ram\n  __bss_end = . ;\n  _end = .;\n\n/*\n   * RAM functions go at the end of our stack and heap allocation.\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\n   */\n/*\n  .ramfunc : AT (LOADADDR (.data) + SIZEOF (.data))\n  {\n    _ramfunc_begin = . ;\n    *(.ramfunc  .ramfunc.*)\n    . = ALIGN(4) ;\n    _ramfunc_end = . ;\n  } >keram\n  _ramfunc_image_begin = LOADADDR(.ramfunc) ;\n  _ramfunc_length = SIZEOF(.ramfunc) ;\n*/\n\n\n  /* Stabs debugging sections.  */\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  /* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  */\n  /* DWARF 1 */\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  /* GNU DWARF 1 extensions */\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  /* DWARF 1.1 and DWARF 2 */\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  /* DWARF 2 */\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  /* SGI/MIPS DWARF 2 extensions */\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  /DISCARD/ : { *(.MIPS.abiflags) }\n}\n"
  },
  {
    "path": "sys/arch/pic32/conf/Config.generic",
    "content": "#\n# Generic kernel configuration for PIC32 processor.\n#\n# This file contains all the devices and all the options available\n# for the pic32 platform.  It's not expected to be buildable, as some\n# devices and options are mutually exclusive or incompatible.\n# It's intended to be used as a reference or as a starting point\n# when creating configuration for a new board.\n#\n# For details, see http://retrobsd.org/wiki/doku.php/doc/kconfig\n#\narchitecture    \"pic32\"\ncpu             \"PIC32MX7\"                  # Processor variant\nboard           \"MAX32\"                     # Board type\nldscript        \"MAX32.ld\"                  # Linker script\n\nmakeoptions     DEBUG=\"-g\"                  # Debug symbols\n\n# Need to set locally\ntimezone        8 dst\nmaxusers        2\n\n# Standard system options\noptions         \"HZ=100\"                    # Rate of clock interrupt\noptions         \"CPU_KHZ=80000\"             # Oscillator frequency of CPU core\noptions         \"BUS_KHZ=80000\"             # Frequency of peripheral bus\noptions         \"BUS_DIV=1\"                 # Bus clock divisor 1/2/4/8\noptions         \"UCB_METER\"                 # Collect kernel statistics\noptions         \"NPROC=10\"                  # Number of processes, default 25\noptions         \"NBUF=10\"                   # Number of i/o buffers, default 10\noptions         \"NFILE=24\"                  # Number of files, default 24\noptions         \"NINODE=24\"                 # Number of i-nodes, default 24\noptions         \"NMOUNT=2\"                  # Number of mounted filesystems, default 2\noptions         \"SMAPSIZ=NPROC\"             # Size of swap map, default NPROC\noptions         \"HALTREBOOT\"                # Reboot the processor on halt()\noptions         \"KERNEL_HIGHLIGHT\"          # Highlight kernel messages\n\n# LEDs\nsignal          \"LED_DISK\"   pin RF0 invert # disk activity indicator\nsignal          \"LED_SWAP\"   pin RA1 invert # swap activity indicator\nsignal          \"LED_TTY\"    pin RA2 invert # tty activity indicator\nsignal          \"LED_KERNEL\" pin RA3 invert # kernel activity indicator\n\n# Root filesystem at /dev/sd0a, swap at /dev/sd0b\nconfig          unix    root on sd0a\n                        swap on sd0b\n                        dumps on sd0b\n\n# Serial UART ports\ndevice          uart1                       # Serial-to-USB converter\ndevice          uart2\ndevice          uart3\ndevice          uart4\noptions         \"UART_BAUD=115200\"          # default speed\nsignal          \"UART4_ENA\"     pin RB13    # power enable signal\n\n# USB UART ports\ndevice          uartusb                     # USB device mode, CDC function\noptions         \"UARTUSB_BAUD=115200\"       # default speed\noptions         \"USB_AUTOBOOT=YES\"          # don't wait for <Enter> on boot\noptions         \"USB_MAX_EP_NUMBER=3\"       # parameters of USB device...\noptions         \"USB_NUM_STRING_DESCRIPTORS=3\" # ...specific for CDC function\n\n# Console options\noptions         \"CONS_MAJOR=UART_MAJOR\"     # use UART device as console\noptions         \"CONS_MINOR=0\"              # uart1 is /dev/tty0\n\n# SPI ports\ncontroller      spi2                        # SD card\n\n# microSD card\ndevice          sd0     at spi2 pin RC14    # select pin\noptions         \"SD_MHZ=10\"                 # speed 10 MHz\nsignal          \"SD0_ENA\"       pin RA5     # SD card enable signal\n\n# General purpose I/O ports\n# Flags define a mask of available pins\n# For 64-pin devices:\ndevice          gpio1   flags 0xffff    # port B\ndevice          gpio2   flags 0xf000    # port C\ndevice          gpio3   flags 0x0fff    # port D\ndevice          gpio4   flags 0x00ff    # port E\ndevice          gpio5   flags 0x003b    # port F\ndevice          gpio6   flags 0x03cc    # port G\n\n# For 100-pin devices:\ndevice          gpio0   flags 0xc6ff    # port A\ndevice          gpio1   flags 0xffff    # port B\ndevice          gpio2   flags 0xf01e    # port C\ndevice          gpio3   flags 0xffff    # port D\ndevice          gpio4   flags 0x03ff    # port E\ndevice          gpio5   flags 0x313f    # port F\ndevice          gpio6   flags 0xf3cf    # port G\n\nsignal          \"GPIO_CLEAR\"    pin RA5     # clear on startup\n\n# ADC driver\ndevice          adc\n\n# PWM driver\ndevice          pwm\n\n# GLCD driver\ndevice          glcd\n\n# HX8357 driver\ndevice          hxtft\n\n# Skeleton driver\ndevice          skel\n\n# Pseudo terminals\nservice         pty     4\n\n# System log\nservice         log\n\n# Power control\ndevice          power\nsignal          \"POWER_LED\"     pin RA3\nsignal          \"POWER_SWITCH\"  pin RA4\nsignal          \"POWER_CONTROL\" pin RA5\n\n# picga\ncontroller      spi1                        # RAM disk: picga\ndevice          picga0  at spi1 pin RA4     # chip select signal\noptions         \"PICGA_BUS=SPI1CON\"         # TODO: delete this option\nsignal          \"PICGA_CS\" pin RA4          # TODO: delete\n\n# TFT display driver with 8-bit parallel interface.\n# Supported controllers: ST7781, ILI9341, NT35702\ndevice          gpanel\nsignal          \"LCD_RST\"   pin RB10\nsignal          \"LCD_CS\"    pin RB0\nsignal          \"LCD_RD\"    pin RB2\nsignal          \"LCD_RS\"    pin RB8\nsignal          \"LCD_WR\"    pin RB4\nsignal          \"LCD_D0\"    pin RA14\nsignal          \"LCD_D1\"    pin RD3\nsignal          \"LCD_D2\"    pin RE8\nsignal          \"LCD_D3\"    pin RD0\nsignal          \"LCD_D4\"    pin RF0\nsignal          \"LCD_D5\"    pin RD1\nsignal          \"LCD_D6\"    pin RD2\nsignal          \"LCD_D7\"    pin RE9\n\n#--------------------------------------------\n# Custom RAM disk devices\n#\n\n# sdramp - SDRAM block device\n# The volume is divided into two partitions: A and B.\n# Size of partition B is specified as option SDR_SWAP_KBYTES.\n# The rest is partition A.\ndevice          dr0                         # SDRAM on external memory bus\noptions         \"SDR_SWAP_KBYTES=2048\"      # size of partition B\noptions         \"KERNEL_EXECUTABLE_RAM\"     # allow kernel code in RAM area\n\n# sramc - SRAM block device\n# The volume is divided into two partitions: A and B.\n# Size of partition B is specified as option SRAMC_SWAP_KBYTES.\n# The rest is partition A.\ndevice          rc0                         # SRAM via 4-wire CPLD interface\nsignal          \"SRAMC_DATA\"    pin RE0\nsignal          \"SRAMC_LDA\"     pin RC13\nsignal          \"SRAMC_RD\"      pin RF1\nsignal          \"SRAMC_WR\"      pin RF0\noptions         \"SRAMC_SWAP_KBYTES=2048\"    # size of partition B\n\n# mrams - SPI block device\ncontroller      spi1                        # RAM disk: mrams\ndevice          mr0  at spi1\n                pins RA4, RA2, RB14, RB12   # chip select signals\noptions         \"MRAMS_CHIPS=4\"             # number of chips\noptions         \"MRAMS_CHIPSIZE=512\"        # chip size in kbytes\noptions         \"MRAMS_MHZ=10\"              # speed 10 MHz\nsignal          \"MRAMS_LED0\"    pin RF0     # optional LED indicators\nsignal          \"MRAMS_LED1\"    pin RF1\nsignal          \"MRAMS_LED2\"    pin RF2\nsignal          \"MRAMS_LED3\"    pin RF3\n\n# spirams - SPI block device\ncontroller      spi1                        # RAM disk: spirams\ndevice          sr0  at spi1\n                pins RF0,  RF1,  RF2,  RF3, # chip select signals\n                     RF4,  RF5,  RF6,  RF7,\n                     RF8,  RF9,  RF10, RF11,\n                     RF12, RF13, RF14, RF15\noptions         \"SPIRAMS_CHIPSIZE=128\"      # chip size in kbytes\noptions         \"SPIRAMS_CHIPS=16\"          # number of chips\noptions         \"SPIRAMS_MHZ=10\"            # speed 10 MHz\nsignal          \"SPIRAMS_LED0\"  pin RG0     # optional LED indicators\nsignal          \"SPIRAMS_LED1\"  pin RG1\nsignal          \"SPIRAMS_LED2\"  pin RG2\nsignal          \"SPIRAMS_LED3\"  pin RG3\nsignal          \"SPIRAMS_LED4\"  pin RG4\nsignal          \"SPIRAMS_LED5\"  pin RG5\nsignal          \"SPIRAMS_LED6\"  pin RG6\nsignal          \"SPIRAMS_LED7\"  pin RG7\nsignal          \"SPIRAMS_LED8\"  pin RG8\nsignal          \"SPIRAMS_LED9\"  pin RG9\nsignal          \"SPIRAMS_LED10\" pin RG10\nsignal          \"SPIRAMS_LED11\" pin RG11\nsignal          \"SPIRAMS_LED12\" pin RG12\nsignal          \"SPIRAMS_LED13\" pin RG13\nsignal          \"SPIRAMS_LED14\" pin RG14\nsignal          \"SPIRAMS_LED15\" pin RG15\n"
  },
  {
    "path": "sys/arch/pic32/conf/MAX32.ld",
    "content": "/*\n * Linker script for PIC32 firmware using HID bootloader.\n * Flash area for user starts at 9d000000.\n * Start address for user program is 9d001000.\n */\nOUTPUT_FORMAT(\"elf32-littlemips\", \"elf32-bigmips\",\n\t      \"elf32-littlemips\")\nOUTPUT_ARCH(mips)\nENTRY(_reset_vector_)\nMEMORY\n{\n  flash                (rx)  : ORIGIN = 0x9d000000, LENGTH = 512K\n  ram                  (rw!x): ORIGIN = 0x80000000, LENGTH = 26K\n  u0area               (rw!x): ORIGIN = 0x80006800, LENGTH = 3K\n  uarea                (rw!x): ORIGIN = 0x80007400, LENGTH = 3K\n\n  /* Required by Microchip C32 linker */\n  kseg0_program_mem    (rx)  : ORIGIN = 0x9D000000, LENGTH = 0x80000\n  kseg0_boot_mem             : ORIGIN = 0x9FC00000, LENGTH = 0x1000\n  exception_mem              : ORIGIN = 0x9FC01000, LENGTH = 0x1000\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x20000\n}\n\n/* higher address of the user mode stack */\nu0\t= ORIGIN(u0area);\nu\t= ORIGIN(uarea);\nu_end\t= ORIGIN(uarea) + LENGTH(uarea);\n\nSECTIONS\n{\n  .text ORIGIN(flash) :\n  {\n    /* Exception handlers. */\n    *(.exception)\n    . = 0x1000;\n    /* Execution starts here. */\n    *(.startup)\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    /* .gnu.warning sections are handled specially by elf32.em.  */\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7)\n    __rodata_start = . ;\n    *(.rodata .rodata.* .gnu.linkonce.r.* .rel.dyn)\n    __abiflags = . ;\n    *(.MIPS.abiflags)\n    *(.dinit)\n    /* Align here to ensure that the .text section ends on word boundary. */\n    . = ALIGN (32 / 8);\n    _etext = .;\n  } > flash\n\n  /* Start data (internal SRAM).  */\n  .data\t\t  : AT (ADDR (.text) + SIZEOF (.text))\n  {\n    __data_start = . ;\n    _gp = .; \t/* We use only 32k RAM for kernel, so no need for 0x8000 offset. */\n    /* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  */\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n    *(.data .data.* .gnu.linkonce.d.*)\n    *(.eh_frame)\n    _edata = .;\n  } > ram\n\n  .bss ADDR (.data) + SIZEOF (.data) (NOLOAD) :\n  {\n   __bss_start = .;\n   *(.dynbss)\n   *(.sbss .sbss.*)\n   *(.scommon)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   /* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.  */\n   . = ALIGN (32 / 8);\n  } > ram\n  __bss_end = . ;\n  _end = .;\n\n  /* Stabs debugging sections.  */\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  /* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  */\n  /* DWARF 1 */\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  /* GNU DWARF 1 extensions */\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  /* DWARF 1.1 and DWARF 2 */\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  /* DWARF 2 */\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  /* SGI/MIPS DWARF 2 extensions */\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  /DISCARD/ : { *(.MIPS.abiflags) }\n}\n"
  },
  {
    "path": "sys/arch/pic32/conf/MAXIMITE.ld",
    "content": "/*\n * Linker script for PIC32 firmware using HID bootloader.\n * Flash area for user starts at 9d003000.\n * Start address for user program is 9d004000.\n */\nOUTPUT_FORMAT(\"elf32-littlemips\", \"elf32-bigmips\",\n\t      \"elf32-littlemips\")\nOUTPUT_ARCH(mips)\nENTRY(_reset_vector_)\nMEMORY\n{\n  flash                (rx)  : ORIGIN = 0x9d003000, LENGTH = 512K-12K\n  ram                  (rw!x): ORIGIN = 0x80000000, LENGTH = 26K\n  u0area               (rw!x): ORIGIN = 0x80006800, LENGTH = 3K\n  uarea                (rw!x): ORIGIN = 0x80007400, LENGTH = 3K\n\n  /* Required by Microchip C32 linker */\n  kseg0_program_mem    (rx)  : ORIGIN = 0x9D000000, LENGTH = 0x80000\n  kseg0_boot_mem             : ORIGIN = 0x9FC00000, LENGTH = 0x1000\n  exception_mem              : ORIGIN = 0x9FC04000, LENGTH = 0x1000\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x20000\n}\n\n/* higher address of the user mode stack */\nu0\t= ORIGIN(u0area);\nu\t= ORIGIN(uarea);\nu_end\t= ORIGIN(uarea) + LENGTH(uarea);\n\nSECTIONS\n{\n  .text ORIGIN(flash) :\n  {\n    /* Exception handlers. */\n    *(.exception)\n    . = 0x1000;\n    /* Execution starts here. */\n    *(.startup)\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    /* .gnu.warning sections are handled specially by elf32.em.  */\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7)\n    __rodata_start = . ;\n    *(.rodata .rodata.* .gnu.linkonce.r.* .rel.dyn)\n    *(.dinit)\n    /* Align here to ensure that the .text section ends on word boundary. */\n    . = ALIGN (32 / 8);\n    _etext = .;\n  } > flash\n\n  /* Start data (internal SRAM).  */\n  .data\t\t  : AT (ADDR (.text) + SIZEOF (.text))\n  {\n    __data_start = . ;\n    _gp = .; \t/* We use only 32k RAM for kernel, so no need for 0x8000 offset. */\n    /* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  */\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n    *(.data .data.* .gnu.linkonce.d.*)\n    *(.eh_frame)\n    _edata = .;\n  } > ram\n\n  .bss ADDR (.data) + SIZEOF (.data) (NOLOAD) :\n  {\n   __bss_start = .;\n   *(.dynbss)\n   *(.sbss .sbss.*)\n   *(.scommon)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   /* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.  */\n   . = ALIGN (32 / 8);\n  } > ram\n  __bss_end = . ;\n  _end = .;\n\n  /* Stabs debugging sections.  */\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  /* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  */\n  /* DWARF 1 */\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  /* GNU DWARF 1 extensions */\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  /* DWARF 1.1 and DWARF 2 */\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  /* DWARF 2 */\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  /* SGI/MIPS DWARF 2 extensions */\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  /DISCARD/ : { *(.MIPS.abiflags) }\n}\n"
  },
  {
    "path": "sys/arch/pic32/conf/MAXIMITE_COLOR.ld",
    "content": "/*\n * Linker script for PIC32 firmware using HID bootloader.\n * Flash area for user starts at 9d005000.\n * Start address for user program is 9d006000.\n */\nOUTPUT_FORMAT(\"elf32-littlemips\", \"elf32-bigmips\",\n\t      \"elf32-littlemips\")\nOUTPUT_ARCH(mips)\nENTRY(_reset_vector_)\nMEMORY\n{\n  flash                (rx)  : ORIGIN = 0x9d005000, LENGTH = 512K-20K\n  ram                  (rw!x): ORIGIN = 0x80000000, LENGTH = 26K\n  u0area               (rw!x): ORIGIN = 0x80006800, LENGTH = 3K\n  uarea                (rw!x): ORIGIN = 0x80007400, LENGTH = 3K\n\n  /* Required by Microchip C32 linker */\n  kseg0_program_mem    (rx)  : ORIGIN = 0x9D000000, LENGTH = 0x80000\n  kseg0_boot_mem             : ORIGIN = 0x9FC00000, LENGTH = 0x1000\n  exception_mem              : ORIGIN = 0x9FC04000, LENGTH = 0x1000\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x20000\n}\n\n/* higher address of the user mode stack */\nu0\t= ORIGIN(u0area);\nu\t= ORIGIN(uarea);\nu_end\t= ORIGIN(uarea) + LENGTH(uarea);\n\nSECTIONS\n{\n  .text ORIGIN(flash) :\n  {\n    /* Exception handlers. */\n    *(.exception)\n    . = 0x1000;\n    /* Execution starts here. */\n    *(.startup)\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    /* .gnu.warning sections are handled specially by elf32.em.  */\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7)\n    __rodata_start = . ;\n    *(.rodata .rodata.* .gnu.linkonce.r.* .rel.dyn)\n    __abiflags = . ;\n    *(.MIPS.abiflags)\n    *(.dinit)\n    /* Align here to ensure that the .text section ends on word boundary. */\n    . = ALIGN (32 / 8);\n    _etext = .;\n  } > flash\n\n  /* Start data (internal SRAM).  */\n  .data\t\t  : AT (ADDR (.text) + SIZEOF (.text))\n  {\n    __data_start = . ;\n    _gp = .; \t/* We use only 32k RAM for kernel, so no need for 0x8000 offset. */\n    /* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  */\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n    *(.data .data.* .gnu.linkonce.d.*)\n    *(.eh_frame)\n    _edata = .;\n  } > ram\n\n  .bss ADDR (.data) + SIZEOF (.data) (NOLOAD) :\n  {\n   __bss_start = .;\n   *(.dynbss)\n   *(.sbss .sbss.*)\n   *(.scommon)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   /* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.  */\n   . = ALIGN (32 / 8);\n  } > ram\n  __bss_end = . ;\n  _end = .;\n\n  /* Stabs debugging sections.  */\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  /* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  */\n  /* DWARF 1 */\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  /* GNU DWARF 1 extensions */\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  /* DWARF 1.1 and DWARF 2 */\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  /* DWARF 2 */\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  /* SGI/MIPS DWARF 2 extensions */\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  /DISCARD/ : { *(.MIPS.abiflags) }\n}\n"
  },
  {
    "path": "sys/arch/pic32/conf/MMB_MX7.ld",
    "content": "/*\n * Linker script for PIC32 firmware using HID bootloader.\n * Flash area for user starts at 9d000000.\n * Start address for user program is 9d000000.\n */\nOUTPUT_FORMAT(\"elf32-littlemips\", \"elf32-bigmips\",\n\t      \"elf32-littlemips\")\nOUTPUT_ARCH(mips)\nENTRY(_reset_vector_)\nMEMORY\n{\n  flash                (rx)  : ORIGIN = 0x9d000000, LENGTH = 512K\n  ram                  (rw!x): ORIGIN = 0x80000000, LENGTH = 26K\n  u0area               (rw!x): ORIGIN = 0x80006800, LENGTH = 3K\n  uarea                (rw!x): ORIGIN = 0x80007400, LENGTH = 3K\n\n  /* Required by Microchip C32 linker */\n  kseg0_program_mem    (rx)  : ORIGIN = 0x9D000000, LENGTH = 0x80000\n  kseg0_boot_mem             : ORIGIN = 0x9FC00000, LENGTH = 0x1000\n  exception_mem              : ORIGIN = 0x9FC00000, LENGTH = 0x1000\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x20000\n}\n\n/* higher address of the user mode stack */\nu0\t= ORIGIN(u0area);\nu\t= ORIGIN(uarea);\nu_end\t= ORIGIN(uarea) + LENGTH(uarea);\n\nSECTIONS\n{\n  .text ORIGIN(flash) :\n  {\n    /* Exception handlers. */\n    *(.exception)\n    /* Execution starts here. */\n    *(.startup)\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    /* .gnu.warning sections are handled specially by elf32.em.  */\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7)\n    __rodata_start = . ;\n    *(.rodata .rodata.* .gnu.linkonce.r.* .rel.dyn)\n    *(.dinit)\n    /* Align here to ensure that the .text section ends on word boundary. */\n    . = ALIGN (32 / 8);\n    _etext = .;\n  } > flash\n\n  /* Start data (internal SRAM).  */\n  .data\t\t  : AT (ADDR (.text) + SIZEOF (.text))\n  {\n    __data_start = . ;\n    _gp = .; \t/* We use only 32k RAM for kernel, so no need for 0x8000 offset. */\n    /* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  */\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n    *(.data .data.* .gnu.linkonce.d.*)\n    *(.eh_frame)\n    _edata = .;\n  } > ram\n\n  .bss ADDR (.data) + SIZEOF (.data) (NOLOAD) :\n  {\n   __bss_start = .;\n   *(.dynbss)\n   *(.sbss .sbss.*)\n   *(.scommon)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   /* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.  */\n   . = ALIGN (32 / 8);\n  } > ram\n  __bss_end = . ;\n  _end = .;\n\n  /* Stabs debugging sections.  */\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  /* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  */\n  /* DWARF 1 */\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  /* GNU DWARF 1 extensions */\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  /* DWARF 1.1 and DWARF 2 */\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  /* DWARF 2 */\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  /* SGI/MIPS DWARF 2 extensions */\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  /DISCARD/ : { *(.MIPS.abiflags) }\n}\n"
  },
  {
    "path": "sys/arch/pic32/conf/Makefile.inc",
    "content": "BOARD?=\t\tPINGUINO_MICRO\nKERNDIR=\t${TOPSRC}/sys/arch/pic32/compile/${BOARD}\nKERN=\t\tunix\n\ninstallflash:\n\tsudo pic32prog ${KERNDIR}/${KERN}.hex\n\n.PHONY: installflash\n"
  },
  {
    "path": "sys/arch/pic32/conf/Makefile.pic32",
    "content": "#\n# Makefile for DiscoBSD/pic32\n#\n# DEBUG is set to -g by config if debugging is requested (config -g).\n#\n\n# sources are located via $S relative to the compilation directory\nS=\t\t../../../..\n\n_mach?=\t\tpic32\n_arch?=\t\tmips\n_machdir?=\t$S/arch/${_mach}\n_archdir?=\t$S/arch/${_arch}\n_confdir?=\t${_machdir}/conf\n\ninclude\t\t${_confdir}/compiler.mk\n\nINCLUDES=\t-nostdinc -I. -I$S -I$S/arch\nDEPFLAGS=\t-MT $@ -MP -MD -MF .deps/$*.dep\nDEFS=\t\t${INCLUDES} ${PARAM} -DKERNEL ${DEPFLAGS}\nCWARNFLAGS=\t-Wall\n\nCMACHCPU=\t-march=mips32r2 -EL\nCMACHFLAGS=\t-ffreestanding -fno-builtin -fcommon\nCMACHFLAGS+=\t${CMACHCPU}\n\nCOPTS?=\t\t-O\nCFLAGS=\t\t${DEBUG} ${CWARNFLAGS} ${CMACHFLAGS} ${COPTS}\nAFLAGS=\t\t-x assembler-with-cpp ${CWARNFLAGS} ${CMACHFLAGS}\nLDFLAGS=\t-T ${_confdir}/${LDSCRIPT}\nLDFLAGS+=\t-nostdlib -Map=$@.map\nLDADD=\n\n# compile rules: rules are named COMPILE_${SUFFIX}\n# SUFFIX is the file suffix, capitalized (e.g. C for a .c file).\n\nCOMPILE_C=\t${CC} ${CFLAGS} ${DEFS} -c $<\nCOMPILE_S=\t${AS} ${AFLAGS} ${DEFS} -c $<\n\n%OBJS\n\n%CFILES\n\nDEVCFG!=if [ -f devcfg.c ] ; then \\\n\t\techo \"devcfg.o\" ; \\\n\telse \\\n\t\techo \"\" ; \\\n\tfi\n\n# load lines for config \"xxx\" will be emitted as:\n# xxx: ${SYSTEM_DEP} swapxxx.o\n#\t${SYSTEM_LD_HEAD}\n#\t${SYSTEM_LD} swapxxx.o\n#\t${SYSTEM_LD_TAIL}\nSYSTEM_OBJ=\tlocore.o ${OBJS} ioconf.o ${DEVCFG}\nSYSTEM_DEP=\tMakefile ioconf.c machine sys .deps ${SYSTEM_OBJ}\nSYSTEM_LD_HEAD=\tsh $S/conf/newvers.sh > vers.c; ${CC} ${CFLAGS} -c vers.c; rm -f $@\nSYSTEM_LD=\t-@echo ${LD} ${LDFLAGS} '$${SYSTEM_OBJ}' vers.o -o $@ ${LDADD}; \\\n\t\t${LD} ${LDFLAGS} ${SYSTEM_OBJ} vers.o -o $@ ${LDADD}\nSYSTEM_LD_TAIL=\t${SIZE} $@; cp $@ $@.elf; \\\n\t\t${OBJCOPY} -O ihex --change-addresses=0x80000000 $@ $@.hex; \\\n\t\t${OBJCOPY} -O binary -R .boot -R .config $@ $@.bin; \\\n\t\t${OBJDUMP} -d -S $@ > $@.dis\n\n%LOAD\n\nclean:\n\trm -rf .deps unix *.elf *.o *.map *.dis *.bin *.hex machine sys\n\nclean-all: clean\n\trm -f *.h ioconf.c swap*.c vers.c\n\nreconfig ioconf.c: Config $S/../tools/bin/config\n\t$S/../tools/bin/config Config\n\t${MAKE} clean\n\nmachine:\n\tln -s ${_machdir}/include $@\n\nsys:\n\tln -s $S/sys $@\n\n.deps:\n\tmkdir .deps\n\nlocore.o: ${_machdir}/${_mach}/locore.S\n\t${COMPILE_S}\n\nioconf.o: ioconf.c\n\t${COMPILE_C}\n\n%RULES\n\n-include .deps/*.dep\n"
  },
  {
    "path": "sys/arch/pic32/conf/SDRAM32MX.ld",
    "content": "/*\n * Linker script for PIC32 firmware using HID bootloader.\n * Flash area for user starts at 9d005000.\n * Start address for user program is 9d006000.\n */\nOUTPUT_FORMAT(\"elf32-littlemips\", \"elf32-bigmips\",\n\t      \"elf32-littlemips\")\nOUTPUT_ARCH(mips)\nENTRY(_reset_vector_)\nMEMORY\n{\n  flash                (rx)  : ORIGIN = 0x9d005000, LENGTH = 512K-20K\n  ram                  (rw!x): ORIGIN = 0x80000000, LENGTH = 0x62C0\n  u0area               (rw!x): ORIGIN = 0x800062C0, LENGTH = 3K\n  uarea                (rw!x): ORIGIN = 0x80006EC0, LENGTH = 3K\n  keram                (rwx) : ORIGIN = 0x80007AC0, LENGTH = 0x540\n  devcfg               (r)   : ORIGIN = 0x9fc02ff0, LENGTH = 16\n\n  /* Required by Microchip C32 linker */\n  kseg0_program_mem    (rx)  : ORIGIN = 0x9D000000, LENGTH = 0x80000\n  kseg0_boot_mem             : ORIGIN = 0x9FC00000, LENGTH = 0x1000\n  exception_mem              : ORIGIN = 0x9FC06000, LENGTH = 0x1000\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x20000\n}\n\n/* higher address of the user mode stack */\nu0\t= ORIGIN(u0area);\nu\t= ORIGIN(uarea);\nu_end\t= ORIGIN(uarea) + LENGTH(uarea);\n\n_keram_start = ORIGIN(keram);\n_keram_end   = ORIGIN(keram) + LENGTH(keram);\n\nSECTIONS\n{\n  .text ORIGIN(flash) :\n  {\n    /* Exception handlers. */\n    *(.exception)\n    . = 0x1000;\n    /* Execution starts here. */\n    *(.startup)\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    /* .gnu.warning sections are handled specially by elf32.em.  */\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7)\n    __rodata_start = . ;\n    *(.rodata .rodata.* .gnu.linkonce.r.* .rel.dyn)\n    __abiflags = . ;\n    *(.MIPS.abiflags)\n    *(.dinit)\n    /* Align here to ensure that the .text section ends on word boundary. */\n    . = ALIGN (32 / 8);\n    _etext = .;\n  } > flash\n\n  /* Start data (internal SRAM).  */\n  .data\t\t  : AT (ADDR (.text) + SIZEOF (.text))\n  {\n    __data_start = . ;\n    _gp = .; \t/* We use only 32k RAM for kernel, so no need for 0x8000 offset. */\n    /* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  */\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n    *(.data .data.* .gnu.linkonce.d.*)\n    *(.eh_frame)\n    _edata = .;\n  } > ram\n\n  /* Device configuration.  */\n  .config         :\n  {\n    *(.config3)\n    *(.config2)\n    *(.config1)\n    *(.config0)\n  } > devcfg\n\n  .bss ADDR (.data) + SIZEOF (.data) (NOLOAD) :\n  {\n   __bss_start = .;\n   *(.dynbss)\n   *(.sbss .sbss.*)\n   *(.scommon)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   /* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.  */\n   . = ALIGN (32 / 8);\n  } > ram\n  __bss_end = . ;\n  _end = .;\n\n/*\n   * RAM functions go at the end of our stack and heap allocation.\n   * Alignment of 2K required by the boundary register (BMXDKPBA).\n   */\n  .ramfunc : AT (LOADADDR (.data) + SIZEOF (.data))\n  {\n    _ramfunc_begin = . ;\n    *(.ramfunc  .ramfunc.*)\n    . = ALIGN(4) ;\n    _ramfunc_end = . ;\n  } >keram\n  _ramfunc_image_begin = LOADADDR(.ramfunc) ;\n  _ramfunc_length = SIZEOF(.ramfunc) ;\n\n\n  /* Stabs debugging sections.  */\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  /* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  */\n  /* DWARF 1 */\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  /* GNU DWARF 1 extensions */\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  /* DWARF 1.1 and DWARF 2 */\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  /* DWARF 2 */\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  /* SGI/MIPS DWARF 2 extensions */\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  /DISCARD/ : { *(.MIPS.abiflags) }\n}\n"
  },
  {
    "path": "sys/arch/pic32/conf/UBW32.ld",
    "content": "/*\n * Linker script for PIC32 firmware using HID bootloader.\n * Flash area for user starts at 9d005000.\n * Start address for user program is 9d006000.\n */\nOUTPUT_FORMAT(\"elf32-littlemips\", \"elf32-bigmips\",\n\t      \"elf32-littlemips\")\nOUTPUT_ARCH(mips)\nENTRY(_reset_vector_)\nMEMORY\n{\n  flash                (rx)  : ORIGIN = 0x9d005000, LENGTH = 512K-20K\n  ram                  (rw!x): ORIGIN = 0x80000000, LENGTH = 26K\n  u0area               (rw!x): ORIGIN = 0x80006800, LENGTH = 3K\n  uarea                (rw!x): ORIGIN = 0x80007400, LENGTH = 3K\n\n  /* Required by Microchip C32 linker */\n  kseg0_program_mem    (rx)  : ORIGIN = 0x9D000000, LENGTH = 0x80000\n  kseg0_boot_mem             : ORIGIN = 0x9FC00000, LENGTH = 0x1000\n  exception_mem              : ORIGIN = 0x9FC06000, LENGTH = 0x1000\n  kseg1_boot_mem             : ORIGIN = 0xBFC00000, LENGTH = 0\n  kseg1_data_mem       (w!x) : ORIGIN = 0xA0000000, LENGTH = 0x20000\n}\n\n/* higher address of the user mode stack */\nu0\t= ORIGIN(u0area);\nu\t= ORIGIN(uarea);\nu_end\t= ORIGIN(uarea) + LENGTH(uarea);\n\nSECTIONS\n{\n  .text ORIGIN(flash) :\n  {\n    /* Exception handlers. */\n    *(.exception)\n    . = 0x1000;\n    /* Execution starts here. */\n    *(.startup)\n    *(.text .stub .text.* .gnu.linkonce.t.*)\n    /* .gnu.warning sections are handled specially by elf32.em.  */\n    *(.gnu.warning)\n    *(.glue_7t) *(.glue_7)\n    __rodata_start = . ;\n    *(.rodata .rodata.* .gnu.linkonce.r.* .rel.dyn)\n    __abiflags = . ;\n    *(.MIPS.abiflags)\n    *(.dinit)\n    /* Align here to ensure that the .text section ends on word boundary. */\n    . = ALIGN (32 / 8);\n    _etext = .;\n  } > flash\n\n  /* Start data (internal SRAM).  */\n  .data\t\t  : AT (ADDR (.text) + SIZEOF (.text))\n  {\n    __data_start = . ;\n    _gp = .; \t/* We use only 32k RAM for kernel, so no need for 0x8000 offset. */\n    /* We want the small data sections together, so single-instruction offsets\n       can access them all, and initialized data all before uninitialized, so\n       we can shorten the on-disk segment size.  */\n    *(.sdata .sdata.* .gnu.linkonce.s.*)\n    *(.data .data.* .gnu.linkonce.d.*)\n    *(.eh_frame)\n    _edata = .;\n  } > ram\n\n  .bss ADDR (.data) + SIZEOF (.data) (NOLOAD) :\n  {\n   __bss_start = .;\n   *(.dynbss)\n   *(.sbss .sbss.*)\n   *(.scommon)\n   *(.bss .bss.* .gnu.linkonce.b.*)\n   *(COMMON)\n   /* Align here to ensure that the .bss section occupies space up to\n      _end.  Align after .bss to ensure correct alignment even if the\n      .bss section disappears because there are no input sections.  */\n   . = ALIGN (32 / 8);\n  } > ram\n  __bss_end = . ;\n  _end = .;\n\n  /* Stabs debugging sections.  */\n  .stab          0 : { *(.stab) }\n  .stabstr       0 : { *(.stabstr) }\n  .stab.excl     0 : { *(.stab.excl) }\n  .stab.exclstr  0 : { *(.stab.exclstr) }\n  .stab.index    0 : { *(.stab.index) }\n  .stab.indexstr 0 : { *(.stab.indexstr) }\n  .comment       0 : { *(.comment) }\n  /* DWARF debug sections.\n     Symbols in the DWARF debugging sections are relative to the beginning\n     of the section so we begin them at 0.  */\n  /* DWARF 1 */\n  .debug          0 : { *(.debug) }\n  .line           0 : { *(.line) }\n  /* GNU DWARF 1 extensions */\n  .debug_srcinfo  0 : { *(.debug_srcinfo) }\n  .debug_sfnames  0 : { *(.debug_sfnames) }\n  /* DWARF 1.1 and DWARF 2 */\n  .debug_aranges  0 : { *(.debug_aranges) }\n  .debug_pubnames 0 : { *(.debug_pubnames) }\n  /* DWARF 2 */\n  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }\n  .debug_abbrev   0 : { *(.debug_abbrev) }\n  .debug_line     0 : { *(.debug_line) }\n  .debug_frame    0 : { *(.debug_frame) }\n  .debug_str      0 : { *(.debug_str) }\n  .debug_loc      0 : { *(.debug_loc) }\n  .debug_macinfo  0 : { *(.debug_macinfo) }\n  /* SGI/MIPS DWARF 2 extensions */\n  .debug_weaknames 0 : { *(.debug_weaknames) }\n  .debug_funcnames 0 : { *(.debug_funcnames) }\n  .debug_typenames 0 : { *(.debug_typenames) }\n  .debug_varnames  0 : { *(.debug_varnames) }\n  .debug_pubtypes 0 : { *(.debug_pubtypes) }\n  .debug_ranges   0 : { *(.debug_ranges) }\n  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }\n  /DISCARD/ : { *(.MIPS.abiflags) }\n}\n"
  },
  {
    "path": "sys/arch/pic32/conf/compiler.mk",
    "content": "# GCC mips-elf toolchain on OpenBSD, FreeBSD, and Linux\n# ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n# Build the toolchain with the Ports Collection for OpenBSD,\n# as described in the file: tools/openbsd/README.md\n#\n# Build the toolchain from sources for FreeBSD and Linux,\n# as described on page: http://retrobsd.org/wiki/doku.php/doc/toolchain-mips\n\n_HOST_OSNAME!=\tuname -s\n\nMIPS_GCC_PREFIX!= if [ x\"${_HOST_OSNAME}\" = x\"OpenBSD\" ] ; then \\\n\t\t\techo \"/usr/local/bin/mips-elf\" ; \\\n\t\telif [ x\"${_HOST_OSNAME}\" = x\"FreeBSD\" ] ; then \\\n\t\t\techo \"/usr/local/mips-elf/bin/mips-elf\" ; \\\n\t\telif [ x\"${_HOST_OSNAME}\" = x\"Linux\" ] ; then \\\n\t\t\techo \"/usr/local/mips-gcc-4.8.1/bin/mips-elf\" ; \\\n\t\telse \\\n\t\t\techo \"/does/not/exist\" ; \\\n\t\tfi\n\n_AS=\t\t-gcc\n_CC=\t\t-gcc\n_CPP=\t\t-cpp\n_LD=\t\t-ld\n_SIZE=\t\t-size\n_OBJCOPY=\t-objcopy\n_OBJDUMP=\t-objdump\n\nAS=\t\t${MIPS_GCC_PREFIX}${_AS}\nCC=\t\t${MIPS_GCC_PREFIX}${_CC}\nCPP=\t\t${MIPS_GCC_PREFIX}${_CPP}\nLD=\t\t${MIPS_GCC_PREFIX}${_LD}\nSIZE=\t\t${MIPS_GCC_PREFIX}${_SIZE}\nOBJCOPY=\t${MIPS_GCC_PREFIX}${_OBJCOPY}\nOBJDUMP=\t${MIPS_GCC_PREFIX}${_OBJDUMP}\n"
  },
  {
    "path": "sys/arch/pic32/conf/devices.pic32",
    "content": "#\n# List of block devices and majors\n#\nsd      0\nrc      1       # sramc   - SRAM connected via CPLD\ndr      2       # sdramp  - SDRAM at external memory bus\nmr      3       # mrams   - MRAM at SPI port\nsr      5       # spirams - serial RAM at SPI port\n"
  },
  {
    "path": "sys/arch/pic32/conf/files.pic32",
    "content": "#\n# Kernel sources, architecture-agnostic.\n#\nkern/exec_aout.c\t\t\tstandard\nkern/exec_conf.c\t\t\tstandard\nkern/exec_elf.c\t\t\t\tstandard\nkern/exec_script.c\t\t\tstandard\nkern/exec_subr.c\t\t\tstandard\nkern/init_main.c\t\t\tstandard\nkern/init_sysent.c\t\t\tstandard\nkern/kern_clock.c\t\t\tstandard\nkern/kern_descrip.c\t\t\tstandard\nkern/kern_exec.c\t\t\tstandard\nkern/kern_exit.c\t\t\tstandard\nkern/kern_fork.c\t\t\tstandard\nkern/kern_mman.c\t\t\tstandard\nkern/kern_proc.c\t\t\tstandard\nkern/kern_prot.c\t\t\tstandard\nkern/kern_prot2.c\t\t\tstandard\nkern/kern_resource.c\t\t\tstandard\nkern/kern_sig.c\t\t\t\tstandard\nkern/kern_sig2.c\t\t\tstandard\nkern/kern_subr.c\t\t\tstandard\nkern/kern_synch.c\t\t\tstandard\nkern/kern_sysctl.c\t\t\tstandard\nkern/kern_time.c\t\t\tstandard\nkern/subr_log.c\t\t\t\toptional log\nkern/subr_prf.c\t\t\t\tstandard\nkern/subr_rmap.c\t\t\tstandard\nkern/sys_generic.c\t\t\tstandard\nkern/sys_inode.c\t\t\tstandard\nkern/sys_pipe.c\t\t\t\tstandard\nkern/sys_process.c\t\t\tstandard\nkern/syscalls.c\t\t\t\tstandard\nkern/tty.c\t\t\t\tstandard\nkern/tty_pty.c\t\t\t\toptional pty\nkern/tty_subr.c\t\t\t\tstandard\nkern/tty_tty.c\t\t\t\tstandard\nkern/ufs_alloc.c\t\t\tstandard\nkern/ufs_bio.c\t\t\t\tstandard\nkern/ufs_bmap.c\t\t\t\tstandard\nkern/ufs_dsort.c\t\t\tstandard\nkern/ufs_fio.c\t\t\t\tstandard\nkern/ufs_inode.c\t\t\tstandard\nkern/ufs_mount.c\t\t\tstandard\nkern/ufs_namei.c\t\t\tstandard\nkern/ufs_subr.c\t\t\t\tstandard\nkern/ufs_syscalls.c\t\t\tstandard\nkern/ufs_syscalls2.c\t\t\tstandard\nkern/vfs_vnops.c\t\t\tstandard\nkern/vm_sched.c\t\t\t\tstandard\nkern/vm_swap.c\t\t\t\tstandard\nkern/vm_swp.c\t\t\t\tstandard\n\n#\n# Driver sources, architecture-agnostic.\n#\ndev/cons.c\t\t\t\tstandard\ndev/mem.c\t\t\t\tstandard\ndev/swap.c\t\t\t\tstandard\n\n#\n# PIC32 platform.\n#\narch/pic32/pic32/clock.c\t\tstandard\narch/pic32/pic32/conf.c\t\t\tstandard\narch/pic32/pic32/exception.c\t\tstandard\narch/pic32/pic32/machdep.c\t\tstandard\narch/pic32/pic32/sig_machdep.c\t\tstandard\narch/pic32/pic32/sysctl.c\t\tstandard\n\n#\n# PIC32 hardware abstraction layer.\n#\narch/pic32/hal/usb_device.c\t\toptional uartusb\narch/pic32/hal/usb_function_cdc.c\toptional uartusb\n\n#\n# PIC32 drivers.\n#\narch/pic32/dev/adc.c\t\t\toptional adc\narch/pic32/dev/glcd.c\t\t\toptional glcd\narch/pic32/dev/gpanel-ili9341.c\t\toptional gpanel\narch/pic32/dev/gpanel-nt35702.c\t\toptional gpanel\n#arch/pic32/dev/gpanel-s6d04h0.c\toptional gpanel\narch/pic32/dev/gpanel-spi-ili9341.c\toptional sgpanel\narch/pic32/dev/gpanel-spi.c\t\toptional sgpanel\narch/pic32/dev/gpanel-st7781.c\t\toptional gpanel\narch/pic32/dev/gpanel.c\t\t\toptional gpanel\narch/pic32/dev/gpio.c\t\t\toptional gpio\narch/pic32/dev/hx8357.c\t\t\toptional hxtft\narch/pic32/dev/mrams.c\t\t\toptional mr\narch/pic32/dev/picga.c\t\t\toptional picga\narch/pic32/dev/power_control.c\t\toptional power\narch/pic32/dev/pwm.c\t\t\toptional pwm\narch/pic32/dev/sd.c\t\t\toptional sd\narch/pic32/dev/sdram.S\t\t\toptional dr\narch/pic32/dev/sdramp.c\t\t\toptional dr\narch/pic32/dev/skel.c\t\t\toptional skel\narch/pic32/dev/spi.c\t\t\toptional spi\narch/pic32/dev/spi_bus.c\t\toptional spi\narch/pic32/dev/spirams.c\t\toptional sr\narch/pic32/dev/sramc.c\t\t\toptional rc\narch/pic32/dev/uart.c\t\t\toptional uart\narch/pic32/dev/usb_uart.c\t\toptional uartusb\n"
  },
  {
    "path": "sys/arch/pic32/dev/adc.c",
    "content": "/*\n * ADC driver for PIC32.\n *\n * Copyright (C) 2012 Majenko Technologies <matt@majenko.co.uk>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/param.h>\n#include <sys/conf.h>\n#include <sys/user.h>\n#include <sys/ioctl.h>\n#include <sys/systm.h>\n#include <sys/uio.h>\n#include <sys/config.h>\n\n#include <machine/debug.h>\n\n#include <pic32/dev/adc.h>\n\nextern int uwritec(struct uio *);\n\nunsigned short adcactive = 0;\n\nint adc_open(dev_t dev, int flag, int mode)\n{\n    int channel;\n\n    channel = minor(dev);\n    if (channel > ADCMAX)\n        return ENODEV;\n\n    DEBUG1(\"adc%2: opened\\n\",channel);\n\n    AD1PCFG &= ~(1<<channel);\n    if (adcactive == 0)\n    {\n        // Enable and configure the ADC here\n        AD1CSSL = 0xFFFF;\n        AD1CON2 = 0b0000010000111100;\n        AD1CON3 = 0b0000111100001111;\n        AD1CON1 = 0b1000000011100110;\n        // IPC(6) = 0x04040404;\n    }\n\n    adcactive |= (1<<channel);\n    return 0;\n}\n\nint adc_close(dev_t dev, int flag, int mode)\n{\n    int channel;\n\n    channel = minor(dev);\n    if (channel > ADCMAX)\n        return ENODEV;\n\n    AD1PCFG |= (1<<channel);\n    adcactive &= ~(1<<channel);\n    if (adcactive == 0)\n    {\n        // Switch off the ADC here.\n        AD1CSSL = 0x0000;\n        AD1CON1 = 0x0000;\n        asm volatile(\"NOP\");\n        IECCLR(1) = 1<<(PIC32_IRQ_AD1-32);\n    }\n    return 0;\n}\n\n// Return the most recent ADC value\nint adc_read(dev_t dev, struct uio *uio, int flag)\n{\n    int channel;\n    char temp[6];\n    int c;\n    unsigned int lr;\n    int tv;\n\n    channel = minor(dev);\n    if (channel > ADCMAX)\n        return ENODEV;\n\n    lr = *(&ADC1BUF0+(channel<<2));\n\n    c=0;\n    if (lr >= 1000)\n    {\n        tv = lr/1000;\n        temp[c++] = '0' + tv;\n        lr = lr - (tv*1000);\n    }\n    if (lr >= 100 || c > 0)\n    {\n        tv = lr/100;\n        temp[c++] = '0' + tv;\n        lr = lr - (tv*100);\n    }\n    if (lr >= 10 || c>0)\n    {\n        tv = lr/10;\n        temp[c++] = '0' + tv;\n        lr = lr - (tv*10);\n    }\n    temp[c++] = '0' + lr;\n    temp[c++] = '\\n';\n    temp[c] = 0;\n\n    uiomove(temp,strlen(temp), uio);\n\n    return 0;\n}\n\nint adc_write(dev_t dev, struct uio *uio, int flag)\n{\n    return EINVAL;\n}\n\nint adc_ioctl(dev_t dev, register u_int cmd, caddr_t addr, int flag)\n{\n    switch (cmd) {\n    default:\n        return EINVAL;\n    }\n    return 0;\n}\n\n/*\n * Test to see if device is present.\n * Return true if found and initialized ok.\n */\nstatic int\nadcprobe(config)\n    struct conf_device *config;\n{\n    printf(\"adc: %u channels\\n\", ADCMAX);\n    return 1;\n}\n\nstruct driver adcdriver = {\n    \"adc\", adcprobe,\n};\n"
  },
  {
    "path": "sys/arch/pic32/dev/adc.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)adc.h\t1.4 (2.11BSD GTE) 1997/3/28\n */\n\n#ifndef _ADC_H\n#define _ADC_H\n\n#include <sys/ioctl.h>\n#include <sys/uio.h>\n\n#define ADCMAX 15\n\n#ifdef KERNEL\nint adc_open (dev_t dev, int flag, int mode);\nint adc_close (dev_t dev, int flag, int mode);\nint adc_read (dev_t dev, struct uio *uio, int flag);\nint adc_write (dev_t dev, struct uio *uio, int flag);\nint adc_ioctl (dev_t dev, u_int cmd, caddr_t addr, int flag);\n#endif\n\n#endif\n"
  },
  {
    "path": "sys/arch/pic32/dev/glcd.c",
    "content": "/*\n * Graphical GLCD driver for PIC32.\n *\n * Copyright (C) 2012 Majenko Technologies <matt@majenko.co.uk>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/param.h>\n#include <sys/conf.h>\n#include <sys/user.h>\n#include <sys/ioctl.h>\n#include <sys/systm.h>\n#include <sys/uio.h>\n#include <sys/glcd.h>\n#include <sys/config.h>\n\n#include <machine/debug.h>\n\n#define _BC(R,B) (R &= ~(1<<B))\n#define _BS(R,B) (R |= (1<<B))\n\nunsigned char screen[9][128];\n\nunsigned char mode;\nunsigned char screen_x = 0;\nunsigned char screen_y = 0;\n\n#define MODE_TEXT 0\n#define MODE_LOAD 1\n\nconst unsigned char font[] = {\n    0x00, 0x00, 0x00, 0x00, 0x00,// (space)\n    0x00, 0x00, 0x5F, 0x00, 0x00,// !\n    0x00, 0x07, 0x00, 0x07, 0x00,// \"\n    0x14, 0x7F, 0x14, 0x7F, 0x14,// #\n    0x24, 0x2A, 0x7F, 0x2A, 0x12,// $\n    0x23, 0x13, 0x08, 0x64, 0x62,// %\n    0x36, 0x49, 0x55, 0x22, 0x50,// &\n    0x00, 0x05, 0x03, 0x00, 0x00,// '\n    0x00, 0x1C, 0x22, 0x41, 0x00,// (\n    0x00, 0x41, 0x22, 0x1C, 0x00,// )\n    0x08, 0x2A, 0x1C, 0x2A, 0x08,// *\n    0x08, 0x08, 0x3E, 0x08, 0x08,// +\n    0x00, 0x50, 0x30, 0x00, 0x00,// ,\n    0x08, 0x08, 0x08, 0x08, 0x08,// -\n    0x00, 0x60, 0x60, 0x00, 0x00,// .\n    0x20, 0x10, 0x08, 0x04, 0x02,// /\n    0x3E, 0x51, 0x49, 0x45, 0x3E,// 0\n    0x00, 0x42, 0x7F, 0x40, 0x00,// 1\n    0x42, 0x61, 0x51, 0x49, 0x46,// 2\n    0x21, 0x41, 0x45, 0x4B, 0x31,// 3\n    0x18, 0x14, 0x12, 0x7F, 0x10,// 4\n    0x27, 0x45, 0x45, 0x45, 0x39,// 5\n    0x3C, 0x4A, 0x49, 0x49, 0x30,// 6\n    0x01, 0x71, 0x09, 0x05, 0x03,// 7\n    0x36, 0x49, 0x49, 0x49, 0x36,// 8\n    0x06, 0x49, 0x49, 0x29, 0x1E,// 9\n    0x00, 0x36, 0x36, 0x00, 0x00,// :\n    0x00, 0x56, 0x36, 0x00, 0x00,// ;\n    0x00, 0x08, 0x14, 0x22, 0x41,// <\n    0x14, 0x14, 0x14, 0x14, 0x14,// =\n    0x41, 0x22, 0x14, 0x08, 0x00,// >\n    0x02, 0x01, 0x51, 0x09, 0x06,// ?\n    0x32, 0x49, 0x79, 0x41, 0x3E,// @\n    0x7E, 0x11, 0x11, 0x11, 0x7E,// A\n    0x7F, 0x49, 0x49, 0x49, 0x36,// B\n    0x3E, 0x41, 0x41, 0x41, 0x22,// C\n    0x7F, 0x41, 0x41, 0x22, 0x1C,// D\n    0x7F, 0x49, 0x49, 0x49, 0x41,// E\n    0x7F, 0x09, 0x09, 0x01, 0x01,// F\n    0x3E, 0x41, 0x41, 0x51, 0x32,// G\n    0x7F, 0x08, 0x08, 0x08, 0x7F,// H\n    0x00, 0x41, 0x7F, 0x41, 0x00,// I\n    0x20, 0x40, 0x41, 0x3F, 0x01,// J\n    0x7F, 0x08, 0x14, 0x22, 0x41,// K\n    0x7F, 0x40, 0x40, 0x40, 0x40,// L\n    0x7F, 0x02, 0x04, 0x02, 0x7F,// M\n    0x7F, 0x04, 0x08, 0x10, 0x7F,// N\n    0x3E, 0x41, 0x41, 0x41, 0x3E,// O\n    0x7F, 0x09, 0x09, 0x09, 0x06,// P\n    0x3E, 0x41, 0x51, 0x21, 0x5E,// Q\n    0x7F, 0x09, 0x19, 0x29, 0x46,// R\n    0x46, 0x49, 0x49, 0x49, 0x31,// S\n    0x01, 0x01, 0x7F, 0x01, 0x01,// T\n    0x3F, 0x40, 0x40, 0x40, 0x3F,// U\n    0x1F, 0x20, 0x40, 0x20, 0x1F,// V\n    0x7F, 0x20, 0x18, 0x20, 0x7F,// W\n    0x63, 0x14, 0x08, 0x14, 0x63,// X\n    0x03, 0x04, 0x78, 0x04, 0x03,// Y\n    0x61, 0x51, 0x49, 0x45, 0x43,// Z\n    0x00, 0x00, 0x7F, 0x41, 0x41,// [\n    0x02, 0x04, 0x08, 0x10, 0x20,// \"\\\"\n    0x41, 0x41, 0x7F, 0x00, 0x00,// ]\n    0x04, 0x02, 0x01, 0x02, 0x04,// ^\n    0x40, 0x40, 0x40, 0x40, 0x40,// _\n    0x00, 0x01, 0x02, 0x04, 0x00,// `\n    0x20, 0x54, 0x54, 0x54, 0x78,// a\n    0x7F, 0x48, 0x44, 0x44, 0x38,// b\n    0x38, 0x44, 0x44, 0x44, 0x20,// c\n    0x38, 0x44, 0x44, 0x48, 0x7F,// d\n    0x38, 0x54, 0x54, 0x54, 0x18,// e\n    0x08, 0x7E, 0x09, 0x01, 0x02,// f\n    0x08, 0x14, 0x54, 0x54, 0x3C,// g\n    0x7F, 0x08, 0x04, 0x04, 0x78,// h\n    0x00, 0x44, 0x7D, 0x40, 0x00,// i\n    0x20, 0x40, 0x44, 0x3D, 0x00,// j\n    0x00, 0x7F, 0x10, 0x28, 0x44,// k\n    0x00, 0x41, 0x7F, 0x40, 0x00,// l\n    0x7C, 0x04, 0x18, 0x04, 0x78,// m\n    0x7C, 0x08, 0x04, 0x04, 0x78,// n\n    0x38, 0x44, 0x44, 0x44, 0x38,// o\n    0x7C, 0x14, 0x14, 0x14, 0x08,// p\n    0x08, 0x14, 0x14, 0x18, 0x7C,// q\n    0x7C, 0x08, 0x04, 0x04, 0x08,// r\n    0x48, 0x54, 0x54, 0x54, 0x20,// s\n    0x04, 0x3F, 0x44, 0x40, 0x20,// t\n    0x3C, 0x40, 0x40, 0x20, 0x7C,// u\n    0x1C, 0x20, 0x40, 0x20, 0x1C,// v\n    0x3C, 0x40, 0x30, 0x40, 0x3C,// w\n    0x44, 0x28, 0x10, 0x28, 0x44,// x\n    0x0C, 0x50, 0x50, 0x50, 0x3C,// y\n    0x44, 0x64, 0x54, 0x4C, 0x44,// z\n    0x00, 0x08, 0x36, 0x41, 0x00,// {\n    0x00, 0x00, 0x7F, 0x00, 0x00,// |\n    0x00, 0x41, 0x36, 0x08, 0x00,// }\n    0x08, 0x08, 0x2A, 0x1C, 0x08,// ->\n    0x08, 0x1C, 0x2A, 0x08, 0x08 // <-\n};\n\n/*\n * Devices:\n *      /dev/glcd\n *\n * Write to the device outputs to GLCD memory as data.  Use ioctl() to send\n * comands:\n *\n *      ioctl(fd, GLCD_RESET, 0)  - reset the GLCD\n *      ioctl(fd, GLCD_SET_PAGE, page)  - set the page address\n *      ioctl(fd, GLCD_SET_Y, y)  - set the page offset\n *\n */\n\nint abs(int x)\n{\n    if(x>0)\n        return x;\n    return 0-x;\n}\n\nvoid glcd_delay()\n{\n    unsigned long c;\n    for(c=0; c<200; c++)\n        asm(\"nop\");\n}\n\nvoid glcd_write_value(int chip, unsigned char data)\n{\n    _BC(LAT_RW, PIN_RW);\n    _BC(TRIS_DB0, PIN_DB0);\n    _BC(TRIS_DB1, PIN_DB1);\n    _BC(TRIS_DB2, PIN_DB2);\n    _BC(TRIS_DB3, PIN_DB3);\n    _BC(TRIS_DB4, PIN_DB4);\n    _BC(TRIS_DB5, PIN_DB5);\n    _BC(TRIS_DB6, PIN_DB6);\n    _BC(TRIS_DB7, PIN_DB7);\n\n    if(chip==0)\n        _BS(LAT_CS1, PIN_CS1);\n    if(chip==1)\n        _BS(LAT_CS2, PIN_CS2);\n\n    if(data & 0b00000001)\n        _BS(LAT_DB0, PIN_DB0);\n    else\n        _BC(LAT_DB0, PIN_DB0);\n\n    if(data & 0b00000010)\n        _BS(LAT_DB1, PIN_DB1);\n    else\n        _BC(LAT_DB1, PIN_DB1);\n\n    if(data & 0b00000100)\n        _BS(LAT_DB2, PIN_DB2);\n    else\n        _BC(LAT_DB2, PIN_DB2);\n\n    if(data & 0b00001000)\n        _BS(LAT_DB3, PIN_DB3);\n    else\n        _BC(LAT_DB3, PIN_DB3);\n\n    if(data & 0b00010000)\n        _BS(LAT_DB4, PIN_DB4);\n    else\n        _BC(LAT_DB4, PIN_DB4);\n\n    if(data & 0b00100000)\n        _BS(LAT_DB5, PIN_DB5);\n    else\n        _BC(LAT_DB5, PIN_DB5);\n\n    if(data & 0b01000000)\n        _BS(LAT_DB6, PIN_DB6);\n    else\n        _BC(LAT_DB6, PIN_DB6);\n\n    if(data & 0b10000000)\n        _BS(LAT_DB7, PIN_DB7);\n    else\n        _BC(LAT_DB7, PIN_DB7);\n\n    _BS(LAT_E, PIN_E);\n    glcd_delay();\n    _BC(LAT_E, PIN_E);\n    glcd_delay();\n\n    if(chip==0)\n        _BC(LAT_CS1, PIN_CS1);\n    if(chip==1)\n        _BC(LAT_CS2, PIN_CS2);\n}\n\nvoid glcd_write_data(int chip, unsigned char value)\n{\n    _BS(LAT_DI, PIN_DI);\n    glcd_write_value(chip,value);\n}\n\nvoid glcd_write_command(int chip, unsigned char value)\n{\n    _BC(LAT_DI, PIN_DI);\n    glcd_write_value(chip,value);\n}\n\nvoid glcd_init()\n{\n    _BC(TRIS_DI, PIN_DI);\n    _BC(TRIS_RW, PIN_RW);\n    _BC(TRIS_E, PIN_E);\n    _BC(TRIS_DB0, PIN_DB0);\n    _BC(TRIS_DB1, PIN_DB1);\n    _BC(TRIS_DB2, PIN_DB2);\n    _BC(TRIS_DB3, PIN_DB3);\n    _BC(TRIS_DB4, PIN_DB4);\n    _BC(TRIS_DB5, PIN_DB5);\n    _BC(TRIS_DB6, PIN_DB6);\n    _BC(TRIS_DB7, PIN_DB7);\n    _BC(TRIS_CS1, PIN_CS1);\n    _BC(TRIS_CS2, PIN_CS2);\n    _BC(TRIS_RES, PIN_RES);\n\n    _BC(LAT_E, PIN_E);\n    _BC(LAT_CS1, PIN_CS1);\n    _BC(LAT_CS2, PIN_CS2);\n    _BS(LAT_RES, PIN_RES);\n\n    glcd_write_command(0,GLCD_CMD_ON);\n    glcd_write_command(1,GLCD_CMD_ON);\n    glcd_write_command(0,GLCD_CMD_START);\n    glcd_write_command(1,GLCD_CMD_START);\n\n}\n\nvoid glcd_reset()\n{\n    _BC(LAT_RES, PIN_RES);\n    glcd_delay();\n    _BS(LAT_RES, PIN_RES);\n    glcd_init();\n}\n\nvoid glcd_set_page(int chip, int page)\n{\n    glcd_write_command(chip, GLCD_CMD_SET_PAGE | (page & 0x07));\n}\n\nvoid glcd_set_y(int chip, int y)\n{\n    glcd_write_command(chip, GLCD_CMD_SET_Y | (y & 0x63));\n}\n\nvoid glcd_update()\n{\n    unsigned char x,y;\n    for(y=0; y<8; y++)\n    {\n        glcd_set_page(0,y);\n        glcd_set_page(1,y);\n        glcd_set_y(0,0);\n        glcd_set_y(1,0);\n        for(x=0; x<64; x++)\n        {\n            glcd_write_data(0,screen[y][x]);\n            glcd_write_data(1,screen[y][x+64]);\n        }\n    }\n}\n\nvoid glcd_cls()\n{\n    unsigned char x,y;\n    for(y=0; y<8; y++)\n    {\n        for(x=0; x<128; x++)\n        {\n            screen[y][x] = 0;\n        }\n    }\n    screen_x = 0;\n    screen_y = 0;\n}\n\nvoid glcd_load_page()\n{\n    screen_x = 0;\n    screen_y = 0;\n    mode = MODE_LOAD;\n}\n\nint\nglcd_open (dev, flag, mode)\n    dev_t dev;\n{\n    int unit = minor(dev);\n\n    if (unit >= 2)\n        return ENXIO;\n    if (u.u_uid != 0)\n        return EPERM;\n\n    glcd_init();\n    mode = MODE_TEXT;\n    DEBUG(\"glcd%d: Openend\\n\",unit);\n    //screen_x = 0;\n    //screen_y = 0;\n    return 0;\n}\n\nint glcd_close (dev_t dev, int flag, int mode)\n{\n    return 0;\n}\n\nint glcd_read (dev_t dev, struct uio *uio, int flag)\n{\n    // TODO\n    return ENODEV;\n}\n\nvoid glcd_scrollUp(void)\n{\n    unsigned char x, y;\n\n    for (y=0; y<9; y++) {\n        for (x=0; x<128; x++) {\n            screen[y][x] = screen[y][x]>>1;\n            if (y < 8)\n                screen[y][x] |= (screen[y+1][x]<<7);\n        }\n    }\n}\n\nvoid glcd_putc(char c)\n{\n    unsigned int cpos;\n\n    if (c=='\\r') {\n        screen_x = 0;\n        return;\n    }\n\n    if (c=='\\n') {\n        screen_y++;\n        screen_x = 0;\n        if (screen_y>7) {\n            screen_y--;\n            for (cpos=0; cpos<8; cpos++)\n                glcd_scrollUp();\n        }\n        return;\n    }\n\n    if (c == 0x08) {\n        if (screen_x > 0) {\n            screen_x -= 6;\n        } else {\n            if (screen_y > 0) {\n                screen_x = 127-7;\n                screen_y--;\n            }\n        }\n        return;\n    }\n\n    if (c == 0x07) {\n        return;\n    }\n\n    if (c == 0x0C) {\n        glcd_cls();\n        glcd_update();\n        return;\n    }\n\n    if (screen_x > 127-6) {\n        screen_x = 0;\n        screen_y++;\n        if (screen_y > 7) {\n            screen_y--;\n            for (cpos=0; cpos<8; cpos++)\n                glcd_scrollUp();\n        }\n    }\n    cpos = (c - ' ') * 5;\n    screen[screen_y][screen_x++] = font[cpos++];\n    screen[screen_y][screen_x++] = font[cpos++];\n    screen[screen_y][screen_x++] = font[cpos++];\n    screen[screen_y][screen_x++] = font[cpos++];\n    screen[screen_y][screen_x++] = font[cpos++];\n    screen[screen_y][screen_x++] = 0;\n}\n\nvoid glcd_setPixel(int x, int y)\n{\n    unsigned char row;\n    unsigned char pixel;\n    unsigned char mask;\n\n    if (x > 127)\n        return;\n    if (y > 63)\n        return;\n    if (x < 0)\n        return;\n    if (y < 0)\n        return;\n\n    row = y>>3;\n    pixel = y & 0x07;\n\n    mask = 1 << pixel;\n\n    screen[row][x] |= mask;\n}\n\nvoid glcd_clearPixel(int x, int y)\n{\n    unsigned char row;\n    unsigned char pixel;\n    unsigned char mask;\n\n    if (x > 127)\n        return;\n    if (y > 63)\n        return;\n    if (x < 0)\n        return;\n    if (y < 0)\n        return;\n\n    row = y>>3;\n    pixel = y & 0x07;\n\n    mask = 1 << pixel;\n\n    screen[row][x] &= ~mask;\n}\n\nvoid glcd_drawLine(int x, int y, int x2, int y2, unsigned char ink)\n{\n    int w, h;\n    int dx1=0, dy1=0, dx2=0, dy2=0;\n    int longest, shortest;\n    int numerator;\n    int i;\n\n    w = x2 - x;\n    h = y2 - y;\n\n    if (w < 0) {\n        dx1 = -1;\n        dx2 = -1;\n    } else if (w > 0) {\n        dx1 = 1;\n        dx2 = 1;\n    }\n\n    if (h < 0)\n        dy1 = -1;\n    else if (h > 0)\n        dy1 = 1;\n\n    longest = abs(w);\n    shortest = abs(h);\n    if (! (longest>shortest)) {\n        longest = abs(h);\n        shortest = abs(w);\n        if (h < 0)\n            dy2 = -1;\n        else if (h > 0)\n            dy2 = 1;\n        dx2 = 0;\n    }\n\n    numerator = longest >> 1;\n    for (i=0; i<=longest; i++) {\n        if (ink == 1)\n            glcd_setPixel(x, y);\n        else\n            glcd_clearPixel(x, y);\n\n        numerator += shortest;\n        if (! (numerator < longest)) {\n            numerator -= longest;\n            x += dx1;\n            y += dy1;\n        } else {\n            x += dx2;\n            y += dy2;\n        }\n    }\n}\n\nvoid glcd_set_pixel(struct glcd_command *c)\n{\n    glcd_setPixel(c->x1, c->y1);\n}\n\nvoid glcd_clear_pixel(struct glcd_command *c)\n{\n    glcd_clearPixel(c->x1, c->y1);\n}\n\nvoid glcd_draw_line(struct glcd_command *c)\n{\n    glcd_drawLine(c->x1, c->y1, c->x2, c->y2, c->ink);\n}\n\nvoid glcd_draw_box(struct glcd_command *c)\n{\n    glcd_drawLine(c->x1, c->y1, c->x1, c->y2, c->ink);\n    glcd_drawLine(c->x1, c->y1, c->x2, c->y1, c->ink);\n    glcd_drawLine(c->x2, c->y2, c->x1, c->y2, c->ink);\n    glcd_drawLine(c->x2, c->y2, c->x2, c->y1, c->ink);\n}\n\nvoid glcd_draw_filled_box(struct glcd_command *c)\n{\n    unsigned char y;\n    int y1, y2;\n\n    if (c->y1 > c->y2) {\n        y1 = c->y2;\n        y2 = c->y1;\n    } else {\n        y1 = c->y1;\n        y2 = c->y2;\n    }\n\n    for (y=y1; y<=y2; y++) {\n        glcd_drawLine(c->x1, y, c->x2, y, c->ink);\n    }\n}\n\nvoid glcd_goto_xy(struct glcd_command *c)\n{\n    screen_x = c->x1;\n    screen_y = c->y1;\n}\n\nint glcd_write (dev_t dev, struct uio *uio, int flag)\n{\n    struct iovec *iov;\n    int i;\n\n    iov = uio->uio_iov;\n\n    switch (mode) {\n    case MODE_LOAD:\n        for (i=0; i<iov->iov_len; i++) {\n            screen[screen_y][screen_x] = *(iov->iov_base+i);\n            screen_x++;\n            if (screen_x == 128) {\n                screen_y++;\n                if (screen_y == 8) {\n                    mode = MODE_TEXT;\n                    glcd_update();\n                }\n            }\n        }\n        break;\n    case MODE_TEXT:\n        for (i=0; i<iov->iov_len; i++) {\n            glcd_putc(*(iov->iov_base+i));\n        }\n        glcd_update();\n        break;\n    }\n    return 0;\n}\n\nint glcd_ioctl (dev_t dev, register u_int cmd, caddr_t addr, int flag)\n{\n    switch (cmd) {\n    case GLCD_RESET:\n        glcd_reset();\n        break;\n\n    case GLCD_UPDATE:\n        glcd_update();\n        break;\n\n    case GLCD_CLS:\n        glcd_cls();\n        break;\n\n    case GLCD_LOAD_PAGE:\n        glcd_load_page();\n        break;\n\n    case GLCD_SET_PIXEL:\n        glcd_set_pixel((struct glcd_command *)addr);\n        break;\n\n    case GLCD_CLEAR_PIXEL:\n        glcd_clear_pixel((struct glcd_command *)addr);\n        break;\n\n    case GLCD_LINE:\n        glcd_draw_line((struct glcd_command *)addr);\n        break;\n\n    case GLCD_BOX:\n        glcd_draw_box((struct glcd_command *)addr);\n        break;\n\n    case GLCD_FILLED_BOX:\n        glcd_draw_filled_box((struct glcd_command *)addr);\n        break;\n\n    case GLCD_GOTO_XY:\n        glcd_goto_xy((struct glcd_command *)addr);\n        break;\n    }\n    return 0;\n}\n\n/*\n * Test to see if device is present.\n * Return true if found and initialized ok.\n */\nstatic int\nglcdprobe(config)\n    struct conf_device *config;\n{\n    int flags = config->dev_flags;\n\n    printf(\"glcd0: flags %#x\\n\", flags);\n    return 1;\n}\n\nstruct driver glcddriver = {\n    \"glcd\", glcdprobe,\n};\n"
  },
  {
    "path": "sys/arch/pic32/dev/gpanel-ili9341.c",
    "content": "/*\n * Display driver for ILI9341 LCD controller.\n *\n * Copyright (C) 2015 Serge Vakulenko <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/param.h>\n#include <sys/gpanel.h>\n\n#include <pic32/dev/ili9341.h>\n\n/*\n * Write a 8-bit value to the ILI9341 Command register.\n */\nstatic void write_command(int cmd)\n{\n    gpanel_rs_command();\n    gpanel_write_byte(cmd);\n}\n\n/*\n * Write a 8-bit value to the ILI9341 Data register.\n */\nstatic void write_data(int cmd)\n{\n    gpanel_rs_data();\n    gpanel_write_byte(cmd);\n}\n\n/*\n * Set address window.\n */\nstatic void set_window(int x0, int y0, int x1, int y1)\n{\n    write_command(ILI9341_Column_Address_Set);\n    write_data(x0 >> 8);\n    gpanel_write_byte(x0);\n    gpanel_write_byte(x1 >> 8);\n    gpanel_write_byte(x1);\n\n    write_command(ILI9341_Page_Address_Set);\n    write_data(y0 >> 8);\n    gpanel_write_byte(y0);\n    gpanel_write_byte(y1 >> 8);\n    gpanel_write_byte(y1);\n\n    write_command(ILI9341_Memory_Write);\n    gpanel_rs_data();\n}\n\n/*\n * Draw a pixel.\n */\nvoid ili_set_pixel(int x, int y, int color)\n{\n    if (x < 0 || x >= gpanel_width || y < 0 || y >= gpanel_height)\n        return;\n    gpanel_cs_active();\n    set_window(x, y, x, y);\n    gpanel_write_byte(color >> 8);\n    gpanel_write_byte(color);\n    gpanel_cs_idle();\n}\n\n/*\n * Fast block fill operation.\n * Requires set_window() has previously been called to set\n * the fill bounds.\n * 'npixels' is inclusive, MUST be >= 1.\n */\nstatic void flood(int color, int npixels)\n{\n    unsigned blocks, i;\n    unsigned hi = color >> 8,\n             lo = color;\n\n    /* Write first pixel normally, decrement counter by 1. */\n    gpanel_write_byte(hi);\n    gpanel_write_byte(lo);\n    npixels--;\n\n    /* 64 pixels/block. */\n    blocks = npixels >> 6;\n    if (hi == lo) {\n        /* High and low bytes are identical.  Leave prior data\n         * on the port(s) and just toggle the write strobe. */\n        while (blocks--) {\n            /* 64 pixels/block / 4 pixels/pass. */\n            for (i = 16; i > 0; i--) {\n                /* 2 bytes/pixel x 4 pixels. */\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n            }\n        }\n        /* Fill any remaining pixels (1 to 64). */\n        for (i = npixels & 63; i > 0; i--) {\n            gpanel_wr_strobe();\n            gpanel_wr_strobe();\n        }\n    } else {\n        while (blocks--) {\n            /* 64 pixels/block / 4 pixels/pass. */\n            for (i = 16; i > 0; i--) {\n                gpanel_write_byte(hi); gpanel_write_byte(lo);\n                gpanel_write_byte(hi); gpanel_write_byte(lo);\n                gpanel_write_byte(hi); gpanel_write_byte(lo);\n                gpanel_write_byte(hi); gpanel_write_byte(lo);\n            }\n        }\n        for (i = npixels & 63; i > 0; i--) {\n            gpanel_write_byte(hi);\n            gpanel_write_byte(lo);\n        }\n    }\n}\n\n/*\n * Switch the screen orientation.\n */\nstatic void ili9341_set_rotation(int rotation)\n{\n    write_command(ILI9341_Memory_Access_Control);\n    switch (rotation & 3) {\n    case 0:                     /* Portrait */\n        write_data(MADCTL_MX | MADCTL_BGR);\n        gpanel_width  = 240;\n        gpanel_height = 320;\n        break;\n    case 1:                     /* Landscape */\n        write_data(MADCTL_MV | MADCTL_BGR);\n        gpanel_width  = 320;\n        gpanel_height = 240;\n        break;\n    case 2:                     /* Upside down portrait */\n        write_data(MADCTL_MY | MADCTL_BGR);\n        gpanel_width  = 240;\n        gpanel_height = 320;\n        break;\n    case 3:                     /* Upside down landscape */\n        write_data(MADCTL_MX | MADCTL_MY | MADCTL_MV | MADCTL_BGR);\n        gpanel_width  = 320;\n        gpanel_height = 240;\n        break;\n    }\n}\n\n/*\n * Switch the screen orientation.\n */\nstatic void ili9481_set_rotation(int rotation)\n{\n    write_command(ILI9341_Memory_Access_Control);\n    switch (rotation & 3) {\n    case 0:                     /* Portrait */\n        write_data(MADCTL_MX | MADCTL_BGR);\n        gpanel_width  = 320;\n        gpanel_height = 480;\n        break;\n    case 1:                     /* Landscape */\n        write_data(MADCTL_MV | MADCTL_BGR);\n        gpanel_width  = 480;\n        gpanel_height = 320;\n        break;\n    case 2:                     /* Upside down portrait */\n        write_data(MADCTL_MY | MADCTL_BGR);\n        gpanel_width  = 320;\n        gpanel_height = 480;\n        break;\n    case 3:                     /* Upside down landscape */\n        write_data(MADCTL_MX | MADCTL_MY | MADCTL_MV | MADCTL_BGR);\n        gpanel_width  = 480;\n        gpanel_height = 320;\n        break;\n    }\n}\n\nstatic void ili9341_resize(struct gpanel_hw *h, int width, int height)\n{\n    gpanel_cs_active();\n\n    /* Switch screen orientaation. */\n    if (width > height)\n        ili9341_set_rotation(1);    /* Landscape */\n    else if (width < height)\n        ili9341_set_rotation(0);    /* Portrait */\n\n    gpanel_cs_idle();\n}\n\nstatic void ili9481_resize(struct gpanel_hw *h, int width, int height)\n{\n    gpanel_cs_active();\n\n    /* Switch screen orientaation. */\n    if (width > height)\n        ili9481_set_rotation(1);    /* Landscape */\n    else if (width < height)\n        ili9481_set_rotation(0);    /* Portrait */\n\n    gpanel_cs_idle();\n}\n\n/*\n * Fill a rectangle with specified color.\n */\nvoid ili_fill_rectangle(int x0, int y0, int x1, int y1, int color)\n{\n    if (x0 < 0) x0 = 0;\n    if (y0 < 0) x0 = 0;\n    if (x1 < 0) x1 = 0;\n    if (y1 < 0) x1 = 0;\n    if (x0 >= gpanel_width) x0 = gpanel_width-1;\n    if (x1 >= gpanel_width) x1 = gpanel_width-1;\n    if (y0 >= gpanel_height) y0 = gpanel_height-1;\n    if (y1 >= gpanel_height) y1 = gpanel_height-1;\n\n    if (x1 < x0) {\n        int t = x0;\n        x0 = x1;\n        x1 = t;\n    }\n    if (y1 < y0) {\n        int t = y0;\n        y0 = y1;\n        y1 = t;\n    }\n    gpanel_cs_active();\n    set_window(x0, y0, x1, y1);\n    flood(color, (x1 - x0 + 1) * (y1 - y0 + 1));\n    gpanel_cs_idle();\n}\n\n/*\n * Fill a rectangle with user data.\n */\nvoid ili_draw_image(int x, int y, int width, int height,\n    const unsigned short *data)\n{\n    unsigned cnt = width * height;\n    int color;\n\n    gpanel_cs_active();\n    set_window(x, y, x + width - 1, y + height - 1);\n    while (cnt--) {\n        color = *data++;\n        gpanel_write_byte(color >> 8);\n        gpanel_write_byte(color);\n    }\n    gpanel_cs_idle();\n}\n\n/*\n * Draw a glyph of one symbol.\n */\nvoid ili_draw_glyph(const struct gpanel_font_t *font,\n    int color, int background, int x, int y, int width,\n    const unsigned short *bits)\n{\n    int h, w, c;\n    unsigned bitmask = 0;\n\n    if (x + width > gpanel_width ||  y + font->height > gpanel_height)\n        return;\n\n    if (background >= 0) {\n        /*\n         * Clear background.\n         */\n        gpanel_cs_active();\n        set_window(x, y, x + width - 1, y + font->height - 1);\n\n        /* Loop on each glyph row. */\n        for (h=0; h<font->height; h++) {\n            /* Loop on every pixel in the row (left to right). */\n            for (w=0; w<width; w++) {\n                if ((w & 15) == 0)\n                    bitmask = *bits++;\n                else\n                    bitmask <<= 1;\n\n                c = (bitmask & 0x8000) ? color : background;\n                gpanel_write_byte(c >> 8);\n                gpanel_write_byte(c);\n            }\n        }\n        gpanel_cs_idle();\n    } else {\n        /*\n         * Transparent background.\n         */\n        /* Loop on each glyph row. */\n        for (h=0; h<font->height; h++) {\n            /* Loop on every pixel in the row (left to right). */\n            for (w=0; w<width; w++) {\n                if ((w & 15) == 0)\n                    bitmask = *bits++;\n                else\n                    bitmask <<= 1;\n\n                if (bitmask & 0x8000)\n                    ili_set_pixel(x + w, y + h, color);\n            }\n        }\n    }\n}\n\n/*\n * Initialize the LCD controller.\n * Fill the gpanel_hw descriptor.\n */\nvoid ili9341_init_display(struct gpanel_hw *h)\n{\n    /* Use a few NOPs to synchronize after the hard Reset. */\n    gpanel_cs_active();\n    write_command(ILI9341_No_Operation);\n    write_command(ILI9341_No_Operation);\n    write_command(ILI9341_No_Operation);\n    write_command(ILI9341_No_Operation);\n\n    write_command(ILI9341_Sleep_OUT);\n    udelay(150000);\n\n    write_command(ILI9341_Display_OFF);\n\n    write_command(ILI9341_Power_Control_1);\n    write_data(0x23);\n\n    write_command(ILI9341_Power_Control_2);\n    write_data(0x10);\n\n    write_command(ILI9341_VCOM_Control_1);\n    write_data(0x2B);\n    write_data(0x2B);\n\n    write_command(ILI9341_VCOM_Control_2);\n    write_data(0xC0);\n\n    write_command(ILI9341_Pixel_Format_Set);\n    write_data(0x55);\n\n    write_command(ILI9341_Frame_Control_In_Normal_Mode);\n    write_data(0x00);\n    write_data(0x1B);\n\n    write_command(ILI9341_Entry_Mode_Set);\n    write_data(0x07);\n\n    write_command(ILI9341_Display_ON);\n\n    ili9341_set_rotation(1);    /* Landscape */\n    gpanel_cs_idle();\n\n    /*\n     * Fill the gpanel_hw descriptor.\n     */\n    h->name           = \"Ilitek ILI9341\";\n    h->resize         = ili9341_resize;\n    h->set_pixel      = ili_set_pixel;\n    h->fill_rectangle = ili_fill_rectangle;\n    h->draw_image     = ili_draw_image;\n    h->draw_glyph     = ili_draw_glyph;\n}\n\n/*\n * Initialize the LCD controller.\n * Fill the gpanel_hw descriptor.\n */\nvoid ili9481_init_display(struct gpanel_hw *h)\n{\n    /* Use a few NOPs to synchronize after the hard Reset. */\n    gpanel_cs_active();\n    write_command(ILI9341_No_Operation);\n    write_command(ILI9341_No_Operation);\n    write_command(ILI9341_No_Operation);\n    write_command(ILI9341_No_Operation);\n\n    write_command(ILI9341_Sleep_OUT);\n    udelay(150000);\n\n    write_command(ILI9341_NV_Memory_Write);\n    write_data(0x07);\n    write_data(0x42);\n    write_data(0x18);\n\n    write_command(ILI9341_NV_Memory_Protection_Key);\n    write_data(0x00);\n    write_data(0x07);\n    write_data(0x10);\n\n    write_command(ILI9341_NV_Memory_Status_Read);\n    write_data(0x01);\n    write_data(0x02);\n\n    write_command(ILI9341_Power_Control_1);\n    write_data(0x10);\n    write_data(0x3B);\n    write_data(0x00);\n    write_data(0x02);\n    write_data(0x11);\n\n    write_command(ILI9341_VCOM_Control_1);\n    write_data(0x03);\n\n    write_command(ILI9341_Memory_Access_Control);\n    write_data(0x0A);\n\n    write_command(ILI9341_Pixel_Format_Set);\n    write_data(0x55);\n\n    write_command(ILI9341_Column_Address_Set);\n    write_data(0x00);\n    write_data(0x00);\n    write_data(0x01);\n    write_data(0x3F);\n\n    write_command(ILI9341_Page_Address_Set);\n    write_data(0x00);\n    write_data(0x00);\n    write_data(0x01);\n    write_data(0xE0);\n\n    write_command(ILI9341_Display_ON);\n\n    ili9481_set_rotation(1);    /* Landscape */\n    gpanel_cs_idle();\n\n    /*\n     * Fill the gpanel_hw descriptor.\n     */\n    h->name           = \"Ilitek ILI9341\";\n    h->resize         = ili9481_resize;\n    h->set_pixel      = ili_set_pixel;\n    h->fill_rectangle = ili_fill_rectangle;\n    h->draw_image     = ili_draw_image;\n    h->draw_glyph     = ili_draw_glyph;\n}\n"
  },
  {
    "path": "sys/arch/pic32/dev/gpanel-nt35702.c",
    "content": "/*\n * Display driver for NT35702 LCD controller.\n * This controller is partially compatible with ILI9341 chip,\n * so we can reuse most of ili_xxx() routines.\n *\n * Copyright (C) 2015 Serge Vakulenko <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/param.h>\n#include <sys/gpanel.h>\n\n/*\n * NT35702 registers.\n */\n#define NT35702_NOP         0x00    /* No Operation */\n#define NT35702_SWRESET     0x01    /* Software reset */\n#define NT35702_RDDID       0x04    /* Read Display ID */\n#define NT35702_RDDST       0x09    /* Read Display Status */\n#define NT35702_RDDPM       0x0A    /* Read Display Power Mode */\n#define NT35702_RDDMADCTR   0x0B    /* Read Display MADCTR */\n#define NT35702_RDDCOLMOD   0x0C    /* Read Display Pixel Format */\n#define NT35702_RDDIM       0x0D    /* Read Display Image Mode */\n#define NT35702_RDDSM       0x0E    /* Read Display Signal Mode */\n#define NT35702_RDDSDR      0x0F    /* Read Display Self-diagnostic result */\n#define NT35702_SLPIN       0x10    /* Sleep in & booster off */\n#define NT35702_SLPOUT      0x11    /* Sleep out & booster on */\n#define NT35702_PTLON       0x12    /* Partial mode on */\n#define NT35702_NORON       0x13    /* Partial off (Normal) */\n#define NT35702_DSBCTL      0x15    /* Deep Standby mode control */\n#define NT35702_INVOFF      0x20    /* Inversion off (normal) */\n#define NT35702_INVON       0x21    /* Inversion on */\n#define NT35702_DISPOFF     0x28    /* Display off */\n#define NT35702_DISPON      0x29    /* Display on */\n#define NT35702_CASET       0x2A    /* Column address set */\n#define NT35702_RASET       0x2B    /* Row address set */\n#define NT35702_RAMWR       0x2C    /* Memory write */\n#define NT35702_PTLAR       0x30    /* Partial start/end address set */\n#define NT35702_SCRLAR      0x33    /* Scroll area set */\n#define NT35702_TEOFF       0x34    /* Tearing effect line off */\n#define NT35702_TEON        0x35    /* Tearing effect mode set & on */\n#define NT35702_MADCTL      0x36    /* Memory data access control */\n#define NT35702_VSCSAD      0x37    /* Scroll start address of RAM */\n#define NT35702_IDMOFF      0x38    /* Idle mode off */\n#define NT35702_IDMON       0x39    /* Idle mode on */\n#define NT35702_COLMOD      0x3A    /* Interface pixel format */\n#define NT35702_WRDISBV     0x51    /* Write Display Brightness */\n#define NT35702_WRCTRLD     0x53    /* Write CTRL Display */\n#define NT35702_WRCABC      0x55    /* Write Content Adaptive Brightness Control */\n#define NT35702_WRCABCMB    0x5E    /* Write CABC minimum brightness */\n#define NT35702_RDPWM       0x6A    /* Read CABC Brightness */\n#define NT35702_WRPWMF      0x6B    /* Write the PWM Frequency for CABC */\n#define NT35702_CABC_FOR_CE 0x77    /* Force CABC PWM in Some Conditions */\n#define NT35702_CABCDMT     0x79    /* Set Dimming Time Length for CABC */\n#define NT35702_RDID1       0xDA    /* Read IDB */\n#define NT35702_RDID2       0xDB    /* Read ID2 */\n#define NT35702_RDID3       0xDC    /* Read ID3 */\n\n#define NT35702_INVCTR      0xB4    /* Display inversion control */\n#define NT35702_DISSET5     0xB6    /* Display function setting */\n#define NT35702_SDOCTR      0xB7    /* SD output direction control */\n#define NT35702_GDOCTR      0xB8    /* GD output direction control */\n#define NT35702_PWCTR1      0xC0    /* Power control setting\n                                     * VRH: Set the GVDD */\n#define NT35702_PWCTR2      0xC1    /* Power control setting */\n#define NT35702_PWCTR3      0xC2    /* In normal mode (Full colors)\n                                     * AP: adjust the operational amplifier\n                                     * DC: adjust the booster circuit for normal mode */\n#define NT35702_PWCTR4      0xC3    /* In Idle mode (8-colors)\n                                     * AP: adjust the operational amplifier\n                                     * DC: adjust the booster circuit for Idle mode */\n#define NT35702_PWCTR5      0xC4    /* In partial mode + Full colors\n                                     * AP: adjust the operational amplifier\n                                     * DC: adjust the booster circuit for Idle mode */\n#define NT35702_VMCTR1      0xC5    /* VMH: VCOMH voltage control\n                                     * VML: VCOML voltage control */\n#define NT35702_VMOFCTR     0xC7    /* VMF: VCOM offset control */\n#define NT35702_RVMOFCTR    0xC8    /* Read the VMOF value form NV memory */\n#define NT35702_WRID2       0xD1    /* LCM version code\n                                     * Write ID2 value to NV memory */\n#define NT35702_WRID3       0xD2    /* Customer Project code\n                                     * Write ID3 value to NV memory */\n#define NT35702_RDID4       0xD3    /* ID41: IC vendor code\n                                     * ID42: IC part number code\n                                     * ID43 & ID44: chip version code */\n#define NT35702_MTP         0xD4    /* MTP access program enable */\n#define NT35702_EPWRITE     0xD5    /* NV write command */\n#define NT35702_MTPSUP      0xD7    /* MTP speed up */\n#define NT35702_GAMCTRP1    0xE0    /* Gamma adjustment (+ polarity) */\n#define NT35702_GAMCTRN1    0xE1    /* Gamma adjustment (- polarity) */\n#define NT35702_FRMCTR      0xFA    /* Frame rate control */\n#define NT35702_AVDDCLP     0xFD    /* AVDD Clamp Voltage */\n\n/*\n * Memory Access Control register\n */\n#define MADCTL_MY           0x80    /* Row address order */\n#define MADCTL_MX           0x40    /* Column address order */\n#define MADCTL_MV           0x20    /* Row/column exchange */\n#define MADCTL_ML           0x10    /* Vertical refresh order */\n#define MADCTL_BGR          0x08    /* Color filter selector: 0=RGB, 1=BGR */\n#define MADCTL_MH           0x04    /* Horisontal refresh direction: 1=left-to-right */\n\n/*\n * Reuse ILI9341 routines.\n */\nextern void ili_set_pixel(int x, int y, int color);\nextern void ili_fill_rectangle(int x0, int y0, int x1, int y1, int color);\nextern void ili_draw_image(int x, int y, int width, int height,\n    const unsigned short *data);\nextern void ili_draw_glyph(const struct gpanel_font_t *font,\n    int color, int background, int x, int y, int width,\n    const unsigned short *bits);\n\n/*\n * Write a 8-bit value to the NT35702 Command register.\n */\nstatic void write_command(int cmd)\n{\n    gpanel_rs_command();\n    gpanel_write_byte(cmd);\n}\n\n/*\n * Write a 8-bit value to the NT35702 Data register.\n */\nstatic void write_data(int cmd)\n{\n    gpanel_rs_data();\n    gpanel_write_byte(cmd);\n}\n\n/*\n * Switch the screen orientation.\n */\nstatic void set_rotation(int rotation)\n{\n    write_command(NT35702_MADCTL);\n    switch (rotation & 3) {\n    case 0:                     /* Portrait */\n        write_data(MADCTL_MX | MADCTL_MY | MADCTL_BGR);\n        gpanel_width  = 240;\n        gpanel_height = 320;\n        break;\n    case 1:                     /* Landscape */\n        write_data(MADCTL_MY | MADCTL_MV | MADCTL_BGR);\n        gpanel_width  = 320;\n        gpanel_height = 240;\n        break;\n    case 2:                     /* Upside down portrait */\n        write_data(MADCTL_BGR);\n        gpanel_width  = 240;\n        gpanel_height = 320;\n        break;\n    case 3:                     /* Upside down landscape */\n        write_data(MADCTL_MX | MADCTL_MV | MADCTL_BGR);\n        gpanel_width  = 320;\n        gpanel_height = 240;\n        break;\n    }\n}\n\nstatic void nt35702_resize(struct gpanel_hw *h, int width, int height)\n{\n    gpanel_cs_active();\n\n    /* Switch screen orientaation. */\n    if (width > height)\n        set_rotation(1);        /* Landscape */\n    else if (width < height)\n        set_rotation(0);        /* Portrait */\n\n    gpanel_cs_idle();\n}\n\n/*\n * Initialize the LCD controller.\n * Fill the gpanel_hw descriptor.\n */\nvoid nt35702_init_display(struct gpanel_hw *h)\n{\n    gpanel_cs_active();\n    write_command(NT35702_SWRESET);\n    udelay(20000);\n\n    write_command(NT35702_SLPOUT);\n    udelay(120000);\n\n    write_command(NT35702_PWCTR3);\n    write_data(0x05);               // APA2 APA1 APA0   Large\n    write_data(0x00);               // Step-up cycle in Booster circuit 1\n                                    // Step-up cycle in Booster circuit 2,3\n    write_command(NT35702_PWCTR4);\n    write_data(0x05);               // APA2 APA1 APA0   Large\n    write_data(0x00);               // Step-up cycle in Booster circuit 1\n                                    // Step-up cycle in Booster circuit 2,3\n    write_command(NT35702_PWCTR5);\n    write_data(0x05);               // APA2 APA1 APA0   Large\n    write_data(0x00);               // Step-up cycle in Booster circuit 1\n                                    // Step-up cycle in Booster circuit 2,3\n    write_command(NT35702_COLMOD);\n    write_data(0x55);\n\n    write_command(NT35702_MTPSUP);\n    write_data(0x40);\n    write_data(0xE0);\n\n    write_command(NT35702_AVDDCLP);\n    write_data(0x06);\n    write_data(0x11);\n\n    write_command(NT35702_FRMCTR);\n    write_data(0x38);\n    write_data(0x20);\n    write_data(0x1C);\n    write_data(0x10);\n    write_data(0x37);\n    write_data(0x12);\n    write_data(0x22);\n    write_data(0x1E);\n\n    write_command(NT35702_PWCTR1);  // Set GVDD\n    write_data(0x05);\n\n    write_command(NT35702_VMCTR1);  // Set Vcom\n    write_data(0x60);\n    write_data(0x00);\n\n    write_command(NT35702_VMOFCTR); // Set VCOM-OFFSET\n    write_data(0xA9);               // You can fine-tune to improve flicker\n\n    set_rotation(1);                /* Landscape */\n\n    write_command(NT35702_GAMCTRP1);\n    write_data(0x22);\n    write_data(0x23);\n    write_data(0x25);\n    write_data(0x08);\n    write_data(0x10);\n    write_data(0x14);\n    write_data(0x40);\n    write_data(0x7B);\n    write_data(0x50);\n    write_data(0x0B);\n    write_data(0x1B);\n    write_data(0x22);\n    write_data(0x20);\n    write_data(0x2F);\n    write_data(0x37);\n\n    write_command(NT35702_GAMCTRN1);\n    write_data(0x0C);\n    write_data(0x14);\n    write_data(0x23);\n    write_data(0x0E);\n    write_data(0x14);\n    write_data(0x15);\n    write_data(0x36);\n    write_data(0x59);\n    write_data(0x46);\n    write_data(0x0B);\n    write_data(0x1F);\n    write_data(0x27);\n    write_data(0x1F);\n    write_data(0x20);\n    write_data(0x22);\n\n    write_command(NT35702_DISPON);\n\n    write_command(NT35702_RAMWR);\n    gpanel_cs_idle();\n\n    /*\n     * Fill the gpanel_hw descriptor.\n     */\n    h->name           = \"Novatek NT35702\";\n    h->resize         = nt35702_resize;\n    h->set_pixel      = ili_set_pixel;\n    h->fill_rectangle = ili_fill_rectangle;\n    h->draw_image     = ili_draw_image;\n    h->draw_glyph     = ili_draw_glyph;\n}\n"
  },
  {
    "path": "sys/arch/pic32/dev/gpanel-s6d04h0.c",
    "content": "/*\n * Display driver for Samsung S6D04H0 LCD controller.\n *\n * Copyright (C) 2015 Serge Vakulenko <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/param.h>\n#include <sys/gpanel.h>\n\n/*\n * Display size.\n */\nstatic int _width, _height;\n\n/*\n * Level 1 Commands\n */\n#define S6D04H0_No_Operation                            0x00    /* C 0 */\n#define S6D04H0_Software_Reset                          0x01    /* C 0 */\n#define S6D04H0_Read_Display_Identification_Information 0x04    /* R 4 */\n#define S6D04H0_Read_Display_Status                     0x09    /* R 5 */\n#define S6D04H0_Read_Display_Power_Mode                 0x0A    /* R 2 */\n#define S6D04H0_Read_Display_MADCTL                     0x0B    /* R 2 */\n#define S6D04H0_Read_Display_Pixel_Format               0x0C    /* R 2 */\n#define S6D04H0_Read_Display_Image_Mode                 0x0D    /* R 2 */\n#define S6D04H0_Read_Display_Signal_Mode                0x0E    /* R 2 */\n#define S6D04H0_Read_Display_Self_Diagnostic_Result     0x0F    /* R 2 */\n#define S6D04H0_Sleep_In                                0x10    /* C 0 */\n#define S6D04H0_Sleep_Out                               0x11    /* C 0 */\n#define S6D04H0_Partial_Mode_On                         0x12    /* C 0 */\n#define S6D04H0_Normal_Display_Mode_On                  0x13    /* C 0 */\n#define S6D04H0_Display_Inversion_Off                   0x20    /* C 0 */\n#define S6D04H0_Display_Inversion_On                    0x21    /* C 0 */\n#define S6D04H0_Gamma_Set                               0x26    /* W 1 */\n#define S6D04H0_Display_Off                             0x28    /* C 0 */\n#define S6D04H0_Display_On                              0x29    /* C 0 */\n#define S6D04H0_Column_Address_Set                      0x2A    /* W 4 */\n#define S6D04H0_Page_Address_Set                        0x2B    /* W 4 */\n#define S6D04H0_Memory_Write                            0x2C    /* W n */\n#define S6D04H0_Memory_Read                             0x2E    /* R n */\n#define S6D04H0_Partial_Area                            0x30    /* W 4 */\n#define S6D04H0_Vertical_Scrolling_Definition           0x33    /* W 6 */\n#define S6D04H0_Tearing_Effect_Line_Off                 0x34    /* C 0 */\n#define S6D04H0_Tearing_Effect_Line_On                  0x35    /* W 1 */\n#define S6D04H0_Memory_Data_Access_Control              0x36    /* W 1 */\n#define S6D04H0_Vertical_Scrolling_Start_Address        0x37    /* W 2 */\n#define S6D04H0_Idle_Mode_Off                           0x38    /* C 0 */\n#define S6D04H0_Idle_Mode_On                            0x39    /* C 0 */\n#define S6D04H0_Interface_Pixel_Format                  0x3A    /* W 1 */\n#define S6D04H0_Memory_Write_Continue                   0x3C    /* W n */\n#define S6D04H0_Memory_Read_Continue                    0x3E    /* R n */\n#define S6D04H0_Set_Tear_Scanline                       0x44    /* W 2 */\n#define S6D04H0_Get_Scanline                            0x45    /* R 2 */\n#define S6D04H0_Write_Manual_Brightness                 0x51    /* W 1 */\n#define S6D04H0_Read_Display_Brightness                 0x52    /* R 2 */\n#define S6D04H0_Write_BL_Control                        0x53    /* W 1 */\n#define S6D04H0_Read_BL_Control                         0x54    /* R 2 */\n#define S6D04H0_Write_MIE_Mode                          0x55    /* W 1 */\n#define S6D04H0_Read_MIE_Mode                           0x56    /* R 2 */\n#define S6D04H0_Write_Minimum_Brightness                0x5E    /* W 1 */\n#define S6D04H0_Read_Minimum_Brightness                 0x5F    /* R 2 */\n#define S6D04H0_Read_DDB_Start                          0xA1    /* R n */\n#define S6D04H0_Read_DDB_Continue                       0xA8    /* R n */\n#define S6D04H0_Read_ID1                                0xDA    /* R 2 */\n#define S6D04H0_Read_ID2                                0xDB    /* R 2 */\n#define S6D04H0_Read_ID3                                0xDC    /* R 2 */\n\n/*\n * Level 2 Commands\n */\n#define S6D04H0_MIECTL      0xC0    /* W(3)  MIE control */\n#define S6D04H0_BCMODE      0xC1    /* W(1)  MIE control */\n#define S6D04H0_WRMIECTL    0xC2    /* W(9)  MIE control */\n#define S6D04H0_WRBLCTL     0xC3    /* W(2)  MIE control */\n#define S6D04H0_MTPCTL      0xD0    /* W(1)  MTP control */\n#define S6D04H0_MTPACCS     0xD2    /* W(2)  MTP control */\n#define S6D04H0_MTPRD       0xD3    /* R(8)  MTP control */\n#define S6D04H0_DSTB        0xDF    /* W(1)  Deep Standby */\n#define S6D04H0_PASSWD1     0xF0    /* W(2)  Test Key */\n#define S6D04H0_PASSWD2     0xF1    /* W(2)  Test Key */\n#define S6D04H0_DISCTL      0xF2    /* W(17) Display control */\n#define S6D04H0_MANPWRSEQ   0xF3    /* W(5)  Power sequence control */\n#define S6D04H0_PWRCTL      0xF4    /* W(20) Power control */\n#define S6D04H0_VCMCTL      0xF5    /* W(12) VCOM control */\n#define S6D04H0_SRCCTL      0xF6    /* W(9)  Source control */\n#define S6D04H0_IFCTL       0xF7    /* W(4)  Interface control */\n#define S6D04H0_PANELCTL    0xF8    /* W(3)  Gate control */\n#define S6D04H0_GAMMASEL    0xF9    /* W(1)  Gamma selection */\n#define S6D04H0_PGAMMACTL   0xFA    /* W(12) Positive gamma control */\n#define S6D04H0_NGAMMACTL   0xFB    /* W(12) Negative gamma control */\n\n/*\n * Memory Access Control register\n */\n#define MADCTL_MY           0x80\n#define MADCTL_MX           0x40\n#define MADCTL_MV           0x20\n#define MADCTL_ML           0x10\n#define MADCTL_BGR          0x08\n#define MADCTL_MH           0x04\n#define MADCTL_RGB          0x00\n\n/*\n * Write a 8-bit value to the S6D04H0 Command register.\n */\nstatic void write_command(int cmd)\n{\n    gpanel_cs_active();\n    gpanel_rs_command();\n    gpanel_write_byte(cmd);\n    gpanel_cs_idle();\n}\n\n/*\n * Write a 8-bit value to the S6D04H0 Data register.\n */\nstatic void write_data(int cmd)\n{\n    gpanel_cs_active();\n    gpanel_rs_data();\n    gpanel_write_byte(cmd);\n    gpanel_cs_idle();\n}\n\n/*\n * Set address window.\n */\nstatic void set_window(int x0, int y0, int x1, int y1)\n{\n    write_command(S6D04H0_Column_Address_Set);\n    write_data(x0 >> 8);\n    gpanel_write_byte(x0);\n    gpanel_write_byte(x1 >> 8);\n    gpanel_write_byte(x1);\n\n    write_command(S6D04H0_Page_Address_Set);\n    write_data(y0 >> 8);\n    gpanel_write_byte(y0);\n    gpanel_write_byte(y1 >> 8);\n    gpanel_write_byte(y1);\n\n    write_command(S6D04H0_Memory_Write);\n}\n\n/*\n * Draw a pixel.\n */\nstatic void s6d04h0_set_pixel(int x, int y, int color)\n{\n    if (x < 0 || x >= _width || y < 0 || y >= _height)\n        return;\n    set_window(x, y, x, y);\n    write_data(color >> 8);\n    write_data(color);\n}\n\n/*\n * Fast block fill operation.\n * Requires set_window() has previously been called to set\n * the fill bounds.\n * 'npixels' is inclusive, MUST be >= 1.\n */\nstatic void flood(int color, int npixels)\n{\n    unsigned blocks, i;\n    unsigned hi = color >> 8,\n             lo = color;\n\n    /* Write first pixel normally, decrement counter by 1. */\n    gpanel_rs_data();\n    gpanel_write_byte(hi);\n    gpanel_write_byte(lo);\n    npixels--;\n\n    /* 64 pixels/block. */\n    blocks = npixels >> 6;\n    if (hi == lo) {\n        /* High and low bytes are identical.  Leave prior data\n         * on the port(s) and just toggle the write strobe. */\n        while (blocks--) {\n            /* 64 pixels/block / 4 pixels/pass. */\n            for (i = 16; i > 0; i--) {\n                /* 2 bytes/pixel x 4 pixels. */\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n            }\n        }\n        /* Fill any remaining pixels (1 to 64). */\n        for (i = npixels & 63; i > 0; i--) {\n            gpanel_wr_strobe();\n            gpanel_wr_strobe();\n        }\n    } else {\n        while (blocks--) {\n            /* 64 pixels/block / 4 pixels/pass. */\n            for (i = 16; i > 0; i--) {\n                gpanel_write_byte(hi); gpanel_write_byte(lo);\n                gpanel_write_byte(hi); gpanel_write_byte(lo);\n                gpanel_write_byte(hi); gpanel_write_byte(lo);\n                gpanel_write_byte(hi); gpanel_write_byte(lo);\n            }\n        }\n        for (i = npixels & 63; i > 0; i--) {\n            gpanel_write_byte(hi);\n            gpanel_write_byte(lo);\n        }\n    }\n}\n\n/*\n * Switch the screen orientation.\n */\nstatic void set_rotation(int rotation)\n{\n    write_command(S6D04H0_Memory_Data_Access_Control);\n    switch (rotation & 3) {\n    case 0:                     /* Portrait */\n        write_data(MADCTL_MY | MADCTL_BGR);\n        _width  = 240;\n        _height = 320;\n        break;\n    case 1:                     /* Landscape */\n        write_data(MADCTL_MX | MADCTL_MY | MADCTL_MV | MADCTL_BGR);\n        _width  = 320;\n        _height = 240;\n        break;\n    case 2:                     /* Upside down portrait */\n        write_data(MADCTL_MX | MADCTL_BGR);\n        _width  = 240;\n        _height = 320;\n        break;\n    case 3:                     /* Upside down landscape */\n        write_data(MADCTL_MV | MADCTL_BGR);\n        _width  = 320;\n        _height = 240;\n        break;\n    }\n}\n\nstatic void s6d04h0_clear(struct gpanel_hw *h, int color, int width, int height)\n{\n    /* Switch screen orientaation. */\n    if (width > height)\n        set_rotation(1);        /* Landscape */\n    else if (width < height)\n        set_rotation(0);        /* Portrait */\n\n    /* Fill the screen with a color. */\n    set_window(0, 0, _width-1, _height-1);\n    flood(color, _width * _height);\n}\n\n/*\n * Fill a rectangle with specified color.\n */\nstatic void s6d04h0_fill_rectangle(int x0, int y0, int x1, int y1, int color)\n{\n    if (x0 < 0) x0 = 0;\n    if (y0 < 0) x0 = 0;\n    if (x1 < 0) x1 = 0;\n    if (y1 < 0) x1 = 0;\n    if (x0 >= _width) x0 = _width-1;\n    if (x1 >= _width) x1 = _width-1;\n    if (y0 >= _height) y0 = _height-1;\n    if (y1 >= _height) y1 = _height-1;\n\n    if (x1 < x0) {\n        int t = x0;\n        x0 = x1;\n        x1 = t;\n    }\n    if (y1 < y0) {\n        int t = y0;\n        y0 = y1;\n        y1 = t;\n    }\n    set_window(x0, y0, x1, y1);\n    flood(color, (x1 - x0 + 1) * (y1 - y0 + 1));\n}\n\n/*\n * Fill a rectangle with user data.\n */\nstatic void s6d04h0_draw_image(int x, int y, int width, int height,\n    const unsigned short *data)\n{\n    unsigned cnt = width * height;\n    int color;\n\n    set_window(x, y, x + width - 1, y + height - 1);\n    gpanel_rs_data();\n    while (cnt--) {\n        color = *data++;\n        gpanel_write_byte(color >> 8);\n        gpanel_write_byte(color);\n    }\n}\n\n/*\n * Draw a glyph of one symbol.\n */\nstatic void s6d04h0_draw_glyph(const struct gpanel_font_t *font,\n    int color, int background, int x, int y, int width,\n    const unsigned short *bits)\n{\n    int h, w, c;\n    unsigned bitmask = 0;\n\n    if (background >= 0) {\n        /*\n         * Clear background.\n         */\n        set_window(x, y, x + width - 1, y + font->height - 1);\n        gpanel_cs_active();\n        gpanel_rs_data();\n\n        /* Loop on each glyph row. */\n        for (h=0; h<font->height; h++) {\n            /* Loop on every pixel in the row (left to right). */\n            for (w=0; w<width; w++) {\n                if ((w & 15) == 0)\n                    bitmask = *bits++;\n                else\n                    bitmask <<= 1;\n\n                c = (bitmask & 0x8000) ? color : background;\n                gpanel_write_byte(c >> 8);\n                gpanel_write_byte(c);\n            }\n        }\n        gpanel_cs_idle();\n    } else {\n        /*\n         * Transparent background.\n         */\n        /* Loop on each glyph row. */\n        for (h=0; h<font->height; h++) {\n            /* Loop on every pixel in the row (left to right). */\n            for (w=0; w<width; w++) {\n                if ((w & 15) == 0)\n                    bitmask = *bits++;\n                else\n                    bitmask <<= 1;\n\n                if (bitmask & 0x8000)\n                    s6d04h0_set_pixel(x + w, y + h, color);\n            }\n        }\n    }\n}\n\n/*\n * Initialize the LCD controller.\n * Fill the gpanel_hw descriptor.\n */\nvoid s6d04h0_init_display(struct gpanel_hw *h)\n{\n    write_command(S6D04H0_PASSWD1);\n    write_data(0x5A);\n    write_data(0x5A);\n\n    write_command(0xFC);\n    write_data(0x5A);\n    write_data(0x5A);\n\n    write_command(0xFD);\n    write_data(0x00);\n    write_data(0x00);\n    write_data(0x10);\n    write_data(0x14);\n    write_data(0x12);\n    write_data(0x00);\n    write_data(0x04);\n    write_data(0x48);\n    write_data(0x40);\n    write_data(0x16);\n    write_data(0x16);\n\n    write_command(S6D04H0_Tearing_Effect_Line_On);\n\n    write_command(S6D04H0_Display_Off);\n\n    set_rotation(3);\n\n    write_command(S6D04H0_Interface_Pixel_Format);\n    write_data(0x55);\n\n    write_command(S6D04H0_DISCTL);\n    write_data(0x28);\n    write_data(0x5B);\n    write_data(0x7F);\n    write_data(0x08);\n    write_data(0x08);\n    write_data(0x00);\n    write_data(0x00);\n    write_data(0x15);\n    write_data(0x48);\n    write_data(0x04);\n    write_data(0x07);\n    write_data(0x01);\n    write_data(0x00);\n    write_data(0x00);\n    write_data(0x63);\n    write_data(0x08);\n    write_data(0x08);\n\n    write_command(S6D04H0_IFCTL);\n    write_data(0x01);\n    write_data(0x00);\n    write_data(0x10);\n    write_data(0x00);\n\n    write_command(S6D04H0_PANELCTL);\n    write_data(0x33);\n    write_data(0x00);\n    write_data(0x00);\n\n    write_command(S6D04H0_SRCCTL);\n    write_data(0x01);\n    write_data(0x01);\n    write_data(0x07);\n    write_data(0x00);\n    write_data(0x01);\n    write_data(0x0C);\n    write_data(0x03);\n    write_data(0x0C);\n    write_data(0x03);\n\n    write_command(S6D04H0_VCMCTL);\n    write_data(0x00);\n    write_data(0x2E);\n    write_data(0x40);\n    write_data(0x00);\n    write_data(0x00);\n    write_data(0x01);\n    write_data(0x00);\n    write_data(0x00);\n    write_data(0x0D);\n    write_data(0x0D);\n    write_data(0x00);\n    write_data(0x00);\n\n    write_command(S6D04H0_PWRCTL);\n    write_data(0x07);\n    write_data(0x00);\n    write_data(0x00);\n    write_data(0x00);\n    write_data(0x22);\n    write_data(0x64);\n    write_data(0x01);\n    write_data(0x02);\n    write_data(0x2A);\n    write_data(0x4D);\n    write_data(0x06);\n    write_data(0x2A);\n    write_data(0x00);\n    write_data(0x06);\n    write_data(0x00);\n    write_data(0x00);\n    write_data(0x00);\n    write_data(0x00);\n    write_data(0x00);\n    write_data(0x00);\n\n    write_command(S6D04H0_MANPWRSEQ);\n    write_data(0x01);\n\n    write_command(S6D04H0_GAMMASEL);\n    write_data(0x04);\n\n    write_command(S6D04H0_PGAMMACTL);\n    write_data(0x0A);\n    write_data(0x04);\n    write_data(0x0C);\n    write_data(0x19);\n    write_data(0x25);\n    write_data(0x33);\n    write_data(0x2D);\n    write_data(0x27);\n    write_data(0x22);\n    write_data(0x1E);\n    write_data(0x1A);\n    write_data(0x00);\n\n    write_command(S6D04H0_NGAMMACTL);\n    write_data(0x0C);\n    write_data(0x04);\n    write_data(0x19);\n    write_data(0x1E);\n    write_data(0x20);\n    write_data(0x23);\n    write_data(0x18);\n    write_data(0x3D);\n    write_data(0x25);\n    write_data(0x19);\n    write_data(0x0B);\n    write_data(0x00);\n\n    write_command(S6D04H0_GAMMASEL);\n    write_data(0x02);\n\n    write_command(S6D04H0_PGAMMACTL);\n    write_data(0x0A);\n    write_data(0x04);\n    write_data(0x0C);\n    write_data(0x19);\n    write_data(0x25);\n    write_data(0x33);\n    write_data(0x2D);\n    write_data(0x27);\n    write_data(0x22);\n    write_data(0x1E);\n    write_data(0x1A);\n    write_data(0x00);\n\n    write_command(S6D04H0_NGAMMACTL);\n    write_data(0x0C);\n    write_data(0x04);\n    write_data(0x19);\n    write_data(0x1E);\n    write_data(0x20);\n    write_data(0x23);\n    write_data(0x18);\n    write_data(0x3D);\n    write_data(0x25);\n    write_data(0x19);\n    write_data(0x0B);\n    write_data(0x00);\n\n    write_command(S6D04H0_GAMMASEL);\n    write_data(0x01);\n\n    write_command(S6D04H0_PGAMMACTL);\n    write_data(0x0A);\n    write_data(0x04);\n    write_data(0x0C);\n    write_data(0x19);\n    write_data(0x25);\n    write_data(0x33);\n    write_data(0x2D);\n    write_data(0x27);\n    write_data(0x22);\n    write_data(0x1E);\n    write_data(0x1A);\n    write_data(0x00);\n\n    write_command(S6D04H0_NGAMMACTL);\n    write_data(0x0C);\n    write_data(0x04);\n    write_data(0x19);\n    write_data(0x1E);\n    write_data(0x20);\n    write_data(0x23);\n    write_data(0x18);\n    write_data(0x3D);\n    write_data(0x25);\n    write_data(0x19);\n    write_data(0x0B);\n    write_data(0x00);\n\n    write_command(S6D04H0_Sleep_Out);\n    udelay(150000);\n\n    write_command(S6D04H0_PASSWD1);\n    write_data(0xA5);\n    write_data(0xA5);\n\n    write_command(0xFC);\n    write_data(0xA5);\n    write_data(0xA5);\n\n    write_command(S6D04H0_Display_On);\n\n    set_window(0, 0, _width-1, _height-1);\n\n    /*\n     * Fill the gpanel_hw descriptor.\n     */\n    h->name           = \"Samsung S6D04H0\";\n    h->width          = _width;\n    h->height         = _height;\n    h->clear          = s6d04h0_clear;\n    h->set_pixel      = s6d04h0_set_pixel;\n    h->fill_rectangle = s6d04h0_fill_rectangle;\n    h->draw_image     = s6d04h0_draw_image;\n    h->draw_glyph     = s6d04h0_draw_glyph;\n}\n"
  },
  {
    "path": "sys/arch/pic32/dev/gpanel-spi-ili9341.c",
    "content": "/*\n * Display driver for ILI9341 LCD controller.\n *\n * Copyright (C) 2015 Serge Vakulenko <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/param.h>\n#include <sys/gpanel.h>\n\n#include <pic32/dev/ili9341.h>\n\n/*\n * Set address window.\n */\nstatic void set_window(int x0, int y0, int x1, int y1)\n{\n    gpanel_send_command(ILI9341_Column_Address_Set);\n    gpanel_send_data(x0 >> 8);\n    gpanel_send_data(x0);\n    gpanel_send_data(x1 >> 8);\n    gpanel_send_data(x1);\n\n    gpanel_send_command(ILI9341_Page_Address_Set);\n    gpanel_send_data(y0 >> 8);\n    gpanel_send_data(y0);\n    gpanel_send_data(y1 >> 8);\n    gpanel_send_data(y1);\n\n    gpanel_send_command(ILI9341_Memory_Write);\n}\n\n/*\n * Draw a pixel.\n */\nvoid ili9341_set_pixel(int x, int y, int color)\n{\n    if (x < 0 || x >= gpanel_width || y < 0 || y >= gpanel_height)\n        return;\n    gpanel_cs_active();\n    set_window(x, y, x, y);\n    gpanel_send_data(color >> 8);\n    gpanel_send_data(color);\n    gpanel_cs_idle();\n}\n\n/*\n * Fast block fill operation.\n * Requires set_window() has previously been called to set\n * the fill bounds.\n * 'npixels' is inclusive, MUST be >= 1.\n */\nstatic void flood(int color, int npixels)\n{\n    unsigned i;\n    unsigned hi = color >> 8,\n             lo = color;\n\n    for (i = npixels; i > 0; i--) {\n        gpanel_send_data(hi);\n        gpanel_send_data(lo);\n    }\n}\n\n/*\n * Switch the screen orientation.\n */\nstatic void set_rotation(int rotation)\n{\n    gpanel_send_command(ILI9341_Memory_Access_Control);\n    switch (rotation & 3) {\n    case 0:                     /* Portrait */\n        gpanel_send_data(MADCTL_MX | MADCTL_BGR);\n        gpanel_width  = 240;\n        gpanel_height = 320;\n        break;\n    case 1:                     /* Landscape */\n        gpanel_send_data(MADCTL_MV | MADCTL_BGR);\n        gpanel_width  = 320;\n        gpanel_height = 240;\n        break;\n    case 2:                     /* Upside down portrait */\n        gpanel_send_data(MADCTL_MY | MADCTL_BGR);\n        gpanel_width  = 240;\n        gpanel_height = 320;\n        break;\n    case 3:                     /* Upside down landscape */\n        gpanel_send_data(MADCTL_MX | MADCTL_MY | MADCTL_MV | MADCTL_BGR);\n        gpanel_width  = 320;\n        gpanel_height = 240;\n        break;\n    }\n}\n\nstatic void ili9341_resize(struct gpanel_hw *h, int width, int height)\n{\n    gpanel_cs_active();\n\n    /* Switch screen orientaation. */\n    if (width > height)\n        set_rotation(1);        /* Landscape */\n    else if (width < height)\n        set_rotation(0);        /* Portrait */\n\n    gpanel_cs_idle();\n}\n\n/*\n * Fill a rectangle with specified color.\n */\nvoid ili9341_fill_rectangle(int x0, int y0, int x1, int y1, int color)\n{\n    if (x0 < 0) x0 = 0;\n    if (y0 < 0) x0 = 0;\n    if (x1 < 0) x1 = 0;\n    if (y1 < 0) x1 = 0;\n    if (x0 >= gpanel_width) x0 = gpanel_width-1;\n    if (x1 >= gpanel_width) x1 = gpanel_width-1;\n    if (y0 >= gpanel_height) y0 = gpanel_height-1;\n    if (y1 >= gpanel_height) y1 = gpanel_height-1;\n\n    if (x1 < x0) {\n        int t = x0;\n        x0 = x1;\n        x1 = t;\n    }\n    if (y1 < y0) {\n        int t = y0;\n        y0 = y1;\n        y1 = t;\n    }\n    gpanel_cs_active();\n    set_window(x0, y0, x1, y1);\n    flood(color, (x1 - x0 + 1) * (y1 - y0 + 1));\n    gpanel_cs_idle();\n}\n\n/*\n * Fill a rectangle with user data.\n */\nvoid ili9341_draw_image(int x, int y, int width, int height,\n    const unsigned short *data)\n{\n    unsigned cnt = width * height;\n    int color;\n\n    gpanel_cs_active();\n    set_window(x, y, x + width - 1, y + height - 1);\n    while (cnt--) {\n        color = *data++;\n        gpanel_send_data(color >> 8);\n        gpanel_send_data(color);\n    }\n    gpanel_cs_idle();\n}\n\n/*\n * Draw a glyph of one symbol.\n */\nvoid ili9341_draw_glyph(const struct gpanel_font_t *font,\n    int color, int background, int x, int y, int width,\n    const unsigned short *bits)\n{\n    int h, w, c;\n    unsigned bitmask = 0;\n\n    if (x + width > gpanel_width ||  y + font->height > gpanel_height)\n        return;\n\n    if (background >= 0) {\n        /*\n         * Clear background.\n         */\n        gpanel_cs_active();\n        set_window(x, y, x + width - 1, y + font->height - 1);\n\n        /* Loop on each glyph row. */\n        for (h=0; h<font->height; h++) {\n            /* Loop on every pixel in the row (left to right). */\n            for (w=0; w<width; w++) {\n                if ((w & 15) == 0)\n                    bitmask = *bits++;\n                else\n                    bitmask <<= 1;\n\n                c = (bitmask & 0x8000) ? color : background;\n                gpanel_send_data(c >> 8);\n                gpanel_send_data(c);\n            }\n        }\n        gpanel_cs_idle();\n    } else {\n        /*\n         * Transparent background.\n         */\n        /* Loop on each glyph row. */\n        for (h=0; h<font->height; h++) {\n            /* Loop on every pixel in the row (left to right). */\n            for (w=0; w<width; w++) {\n                if ((w & 15) == 0)\n                    bitmask = *bits++;\n                else\n                    bitmask <<= 1;\n\n                if (bitmask & 0x8000)\n                    ili9341_set_pixel(x + w, y + h, color);\n            }\n        }\n    }\n}\n\n/*\n * Initialize the LCD controller.\n * Fill the gpanel_hw descriptor.\n */\nvoid ili9341_init_display(struct gpanel_hw *h)\n{\n    /* Use a few NOPs to synchronize after the hard Reset. */\n    gpanel_cs_active();\n    gpanel_send_command(ILI9341_No_Operation);\n    gpanel_send_command(ILI9341_No_Operation);\n    gpanel_send_command(ILI9341_No_Operation);\n    gpanel_send_command(ILI9341_No_Operation);\n\n    gpanel_send_command(ILI9341_Sleep_OUT);\n    udelay(150000);\n\n    gpanel_send_command(ILI9341_Display_OFF);\n\n    gpanel_send_command(ILI9341_Power_Control_1);\n    gpanel_send_data(0x23);\n\n    gpanel_send_command(ILI9341_Power_Control_2);\n    gpanel_send_data(0x10);\n\n    gpanel_send_command(ILI9341_VCOM_Control_1);\n    gpanel_send_data(0x2B);\n    gpanel_send_data(0x2B);\n\n    gpanel_send_command(ILI9341_VCOM_Control_2);\n    gpanel_send_data(0xC0);\n\n    gpanel_send_command(ILI9341_Pixel_Format_Set);\n    gpanel_send_data(0x55);\n\n    gpanel_send_command(ILI9341_Frame_Control_In_Normal_Mode);\n    gpanel_send_data(0x00);\n    gpanel_send_data(0x1B);\n\n    gpanel_send_command(ILI9341_Entry_Mode_Set);\n    gpanel_send_data(0x07);\n\n    gpanel_send_command(ILI9341_Display_ON);\n\n    set_rotation(1);                /* Landscape */\n    gpanel_cs_idle();\n\n    /*\n     * Fill the gpanel_hw descriptor.\n     */\n    h->name           = \"Ilitek ILI9341\";\n    h->resize         = ili9341_resize;\n    h->set_pixel      = ili9341_set_pixel;\n    h->fill_rectangle = ili9341_fill_rectangle;\n    h->draw_image     = ili9341_draw_image;\n    h->draw_glyph     = ili9341_draw_glyph;\n}\n"
  },
  {
    "path": "sys/arch/pic32/dev/gpanel-spi.c",
    "content": "/*\n * Generic TFT LCD driver with SPI interface.\n * Supported chips: ILI9341.\n *\n * Copyright (C) 2015 Serge Vakulenko <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/param.h>\n#include <sys/conf.h>\n#include <sys/user.h>\n#include <sys/ioctl.h>\n#include <sys/systm.h>\n#include <sys/uio.h>\n#include <sys/tty.h>\n#include <sys/config.h>\n#include <sys/spi.h>\n#include <sys/gpanel.h>\n\n#define SGPANEL_KHZ     10000   /* clock 10 MHz */\n\n/*\n * Descriptor for access to the hardware-level driver.\n */\nstatic struct gpanel_hw hw;\n\n/*\n * Cursor position for text output.\n */\nstatic int _col, _row;\n\n/*\n * ID of the LCD controller chip.\n */\nstatic int _chip_id;\n\n/*\n * Data/command signal pin.\n */\nstatic int _dc;\nstatic int _last_dc = -1;       /* last DC value */\n\nstatic struct spiio _spiio;\n\n/*\n * Display size.\n */\nint gpanel_width, gpanel_height;\n\n/*\n * Control /CS signal.\n */\nvoid gpanel_cs_active() { spi_select(&_spiio); }\nvoid gpanel_cs_idle()   { spi_deselect(&_spiio); }\n\n/*\n * Send a command to the SPI bus.\n */\nint gpanel_send_command(int value)\n{\n    if (_last_dc != 0) {\n        gpio_clr(_dc);\n        _last_dc = 0;\n    }\n    return spi_transfer(&_spiio, value);\n}\n\n/*\n * Send data to the SPI bus.\n */\nint gpanel_send_data(int value)\n{\n    if (_last_dc != 1) {\n        gpio_set(_dc);\n        _last_dc = 1;\n    }\n    return spi_transfer(&_spiio, value);\n}\n\n/*\n * Draw a line.\n */\nstatic void gpanel_draw_line(int x0, int y0, int x1, int y1, int color)\n{\n    int dx, dy, stepx, stepy, fraction;\n\n    if (x0 == x1 || y0 == y1) {\n        hw.fill_rectangle(x0, y0, x1, y1, color);\n        return;\n    }\n\n    /* Use Bresenham's line algorithm. */\n    dy = y1 - y0;\n    if (dy < 0) {\n        dy = -dy;\n        stepy = -1;\n    } else {\n        stepy = 1;\n    }\n    dx = x1 - x0;\n    if (dx < 0) {\n        dx = -dx;\n        stepx = -1;\n    } else {\n        stepx = 1;\n    }\n    dy <<= 1;                           /* dy is now 2*dy */\n    dx <<= 1;                           /* dx is now 2*dx */\n    hw.set_pixel(x0, y0, color);\n    if (dx > dy) {\n        fraction = dy - (dx >> 1);      /* same as 2*dy - dx */\n        while (x0 != x1) {\n            if (fraction >= 0) {\n                y0 += stepy;\n                fraction -= dx;         /* same as fraction -= 2*dx */\n            }\n            x0 += stepx;\n            fraction += dy;             /* same as fraction -= 2*dy */\n            hw.set_pixel(x0, y0, color);\n        }\n    } else {\n        fraction = dx - (dy >> 1);\n        while (y0 != y1) {\n            if (fraction >= 0) {\n                x0 += stepx;\n                fraction -= dy;\n            }\n            y0 += stepy;\n            fraction += dx;\n            hw.set_pixel(x0, y0, color);\n        }\n    }\n}\n\n/*\n * Draw a rectangular frame.\n */\nstatic void gpanel_draw_frame(int x0, int y0, int x1, int y1, int color)\n{\n    hw.fill_rectangle(x0, y0, x1, y0, color);\n    hw.fill_rectangle(x0, y1, x1, y1, color);\n    hw.fill_rectangle(x0, y0, x0, y1, color);\n    hw.fill_rectangle(x1, y0, x1, y1, color);\n}\n\n/*\n * Draw a circle.\n */\nstatic void gpanel_draw_circle(int x0, int y0, int radius, int color)\n{\n    int f = 1 - radius;\n    int ddF_x = 0;\n    int ddF_y = -2 * radius;\n    int x = 0;\n    int y = radius;\n\n    hw.set_pixel(x0, y0 + radius, color);\n    hw.set_pixel(x0, y0 - radius, color);\n    hw.set_pixel(x0 + radius, y0, color);\n    hw.set_pixel(x0 - radius, y0, color);\n    while (x < y) {\n        if (f >= 0) {\n            y--;\n            ddF_y += 2;\n            f += ddF_y;\n        }\n        x++;\n        ddF_x += 2;\n        f += ddF_x + 1;\n        hw.set_pixel(x0 + x, y0 + y, color);\n        hw.set_pixel(x0 - x, y0 + y, color);\n        hw.set_pixel(x0 + x, y0 - y, color);\n        hw.set_pixel(x0 - x, y0 - y, color);\n        hw.set_pixel(x0 + y, y0 + x, color);\n        hw.set_pixel(x0 - y, y0 + x, color);\n        hw.set_pixel(x0 + y, y0 - x, color);\n        hw.set_pixel(x0 - y, y0 - x, color);\n    }\n}\n\n/*\n * Draw a character from a specified font.\n */\nstatic void gpanel_draw_char(const struct gpanel_font_t *font,\n    int color, int background, int sym)\n{\n    unsigned cindex, width;\n    const unsigned short *bits;\n\n    switch (sym) {\n    case '\\n':      /* goto next line */\n        _row += font->height;\n        _col = 0;\n        if (_row > gpanel_height - font->height)\n            _row = 0;\n        return;\n    case '\\r':      /* carriage return - go to begin of line */\n        _col = 0;\n        return;\n    case '\\t':      /* tab replaced by space */\n        sym = ' ';\n        break;\n    }\n\n    if (sym < font->firstchar || sym >= font->firstchar + font->size)\n        sym = font->defaultchar;\n    cindex = sym - font->firstchar;\n\n    /* Get font bitmap depending on fixed pitch or not. */\n    if (font->width) {\n        /* Proportional font. */\n        width = font->width[cindex];\n    } else {\n        /* Fixed width font. */\n        width = font->maxwidth;\n    }\n    if (font->offset) {\n        bits = font->bits + font->offset[cindex];\n    } else {\n        bits = font->bits + cindex * font->height;\n    }\n\n    /* Draw a character. */\n    hw.draw_glyph(font, color, background, _col, _row, width, bits);\n    _col += width;\n}\n\n/*\n * Draw a string of characters.\n * TODO: Decode UTF-8.\n */\nstatic void gpanel_draw_text(const struct gpanel_font_t *font,\n    int color, int background, int x, int y, const char *text)\n{\n    int sym;\n\n    _col = x;\n    _row = y;\n    for (;;) {\n        sym = *text++;\n        if (! sym)\n            break;\n\n        gpanel_draw_char(font, color, background, sym);\n    }\n}\n\nint gpanel_open(dev_t dev, int flag, int mode)\n{\n    if (minor(dev) != 0)\n        return ENODEV;\n    return 0;\n}\n\nint gpanel_close(dev_t dev, int flag, int mode)\n{\n    return 0;\n}\n\nint gpanel_read(dev_t dev, struct uio *uio, int flag)\n{\n    return ENODEV;\n}\n\nint gpanel_write(dev_t dev, struct uio *uio, int flag)\n{\n    return ENODEV;\n}\n\n/*\n * TODO: check whether user pointers are valid.\n */\nint gpanel_ioctl(dev_t dev, register u_int cmd, caddr_t addr, int flag)\n{\n    switch (cmd) {\n        /*\n         * Clear the whole screen with a given color.\n         */\n        case GPANEL_CLEAR: {\n            struct gpanel_clear_t *param = (struct gpanel_clear_t*) addr;\n\n            if (hw.resize != 0)\n                hw.resize(&hw, param->xsize, param->ysize);\n            hw.fill_rectangle(0, 0, gpanel_width - 1, gpanel_height - 1, param->color);\n            param->xsize = gpanel_width;\n            param->ysize = gpanel_height;\n            break;\n        }\n\n        /*\n         * Draw a single pixel.\n         */\n        case GPANEL_PIXEL: {\n            struct gpanel_pixel_t *param = (struct gpanel_pixel_t*) addr;\n\n            hw.set_pixel(param->x, param->y, param->color);\n            break;\n        }\n\n        /*\n         * Draw a line.\n         */\n        case GPANEL_LINE: {\n            struct gpanel_line_t *param = (struct gpanel_line_t*) addr;\n\n            gpanel_draw_line(param->x0, param->y0, param->x1, param->y1, param->color);\n            break;\n        }\n\n        /*\n         * Draw a rectangle frame.\n         */\n        case GPANEL_RECT: {\n            struct gpanel_rect_t *param = (struct gpanel_rect_t*) addr;\n\n            gpanel_draw_frame(param->x0, param->y0, param->x1, param->y1, param->color);\n            break;\n        }\n\n        /*\n         * Fill a rectangle with color.\n         */\n        case GPANEL_FILL: {\n            struct gpanel_rect_t *param = (struct gpanel_rect_t*) addr;\n\n            hw.fill_rectangle(param->x0, param->y0, param->x1, param->y1, param->color);\n            break;\n        }\n\n        /*\n         * Draw a circle.\n         */\n        case GPANEL_CIRCLE: {\n            struct gpanel_circle_t *param = (struct gpanel_circle_t*) addr;\n\n            gpanel_draw_circle(param->x, param->y, param->radius, param->color);\n            break;\n        }\n\n        /*\n         * Fill a rectangular area with the user-supplied data.\n         */\n        case GPANEL_IMAGE: {\n            struct gpanel_image_t *param = (struct gpanel_image_t*) addr;\n\n            hw.draw_image(param->x, param->y, param->width, param->height,\n                param->image);\n            break;\n        }\n\n        /*\n         * Draw a character.\n         */\n        case GPANEL_CHAR: {\n            struct gpanel_char_t *param = (struct gpanel_char_t*) addr;\n\n            _col = param->x;\n            _row = param->y;\n            gpanel_draw_char(param->font, param->color, param->background, param->sym);\n            break;\n        }\n\n        /*\n         * Draw a string of characters.\n         */\n        case GPANEL_TEXT: {\n            struct gpanel_text_t *param = (struct gpanel_text_t*) addr;\n\n            gpanel_draw_text(param->font, param->color, param->background,\n                param->x, param->y, param->text);\n            break;\n        }\n    }\n    return 0;\n}\n\n/*\n * Draw a BSD logo on the screen.\n */\nstatic void draw_logo()\n{\n#define K       7\n#define COLOR_B 0xf81f\n#define COLOR_S 0x07ff\n#define COLOR_D 0xffe0\n\n    int x = gpanel_width/2  - 17*K;\n    int y = gpanel_height/2 + 11*K;\n\n    hw.fill_rectangle(0, 0, gpanel_width - 1, gpanel_height - 1, 0);\n\n    /* B */\n    gpanel_draw_line( 0*K+x, y- 0*K,  0*K+x, y-11*K, COLOR_B);\n    gpanel_draw_line( 0*K+x, y-11*K,  0*K+x, y-22*K, COLOR_B);\n    gpanel_draw_line( 0*K+x, y-22*K, 10*K+x, y-19*K, COLOR_B);\n    gpanel_draw_line(10*K+x, y-19*K,  0*K+x, y-11*K, COLOR_B);\n    gpanel_draw_line( 0*K+x, y-11*K, 10*K+x, y- 8*K, COLOR_B);\n    gpanel_draw_line(10*K+x, y- 8*K,  0*K+x, y- 0*K, COLOR_B);\n\n    /* S */\n    gpanel_draw_line(22*K+x, y-22*K, 12*K+x, y-19*K, COLOR_S);\n    gpanel_draw_line(12*K+x, y-19*K, 22*K+x, y- 8*K, COLOR_S);\n    gpanel_draw_line(22*K+x, y- 8*K, 12*K+x, y- 0*K, COLOR_S);\n\n    /* D */\n    gpanel_draw_line(24*K+x, y-22*K, 24*K+x, y- 0*K, COLOR_D);\n    gpanel_draw_line(24*K+x, y-22*K, 34*K+x, y-19*K, COLOR_D);\n    gpanel_draw_line(34*K+x, y-19*K, 34*K+x, y- 8*K, COLOR_D);\n    gpanel_draw_line(34*K+x, y- 8*K, 24*K+x, y- 0*K, COLOR_D);\n}\n\n/*\n * Read the chip ID register.\n */\nstatic int read_id()\n{\n    int id;\n\n    /* Read ID4 from register #D3.\n     * Use undocumented command #D9 to get access to ID4. */\n    gpanel_cs_active();\n    gpanel_send_command(0xD9);\n    gpanel_send_data(0x11);\n    gpanel_send_command(0xD3);\n    id = gpanel_send_data(0xff) << 16;\n\n    gpanel_send_command(0xD9);\n    gpanel_send_data(0x12);\n    gpanel_send_command(0xD3);\n    id |= gpanel_send_data(0xff) << 8;\n\n    gpanel_send_command(0xD9);\n    gpanel_send_data(0x13);\n    gpanel_send_command(0xD3);\n    id |= gpanel_send_data(0xff);\n    gpanel_cs_idle();\n    return id;\n}\n\n/*\n * Detect the type of the LCD controller, and initialize it.\n * Return true if found and initialized ok.\n */\nstatic int probe(config)\n    struct conf_device *config;\n{\n    int cs;\n    struct spiio *io = &_spiio;\n\n    /* Only one device is allowed. */\n    if (config->dev_unit > 0)\n        return 0;\n    cs = config->dev_pins[0];\n    _dc = config->dev_pins[1];\n    printf(\"sgpanel: port SPI%d, pins cs=R%c%d/dc=R%c%d\\n\",\n        config->dev_ctlr, gpio_portname(cs), gpio_pinno(cs),\n        gpio_portname(_dc), gpio_pinno(_dc));\n\n    if (spi_setup(io, config->dev_ctlr, cs) != 0) {\n        printf(\"sgpanel: cannot open SPI%u port\\n\", config->dev_ctlr);\n        return 0;\n    }\n    spi_brg(io, SGPANEL_KHZ);\n    spi_set(io, PIC32_SPICON_CKE);\n    gpio_set_output(_dc);\n\n    /* Identify the LCD controller chip. */\n    _chip_id = read_id();\n    switch (_chip_id) {\n    default:\n        /* Disable outputs. */\n        gpio_set_input(_dc);\n        gpio_set_input(cs);\n        printf(\"gpanel0: Unknown chip ID = 0x%04x\\n\", _chip_id);\n        return 0;\n\n    case 0x009341:\n        /* Ilitek ILI9341. */\n        ili9341_init_display(&hw);\n        break;\n    }\n    printf(\"gpanel0: <%s> display %ux%u\\n\", hw.name, gpanel_width, gpanel_height);\n    draw_logo();\n    return 1;\n}\n\nstruct driver sgpaneldriver = {\n    \"sgpanel\", probe,\n};\n"
  },
  {
    "path": "sys/arch/pic32/dev/gpanel-st7781.c",
    "content": "/*\n * Display driver for ST7781 LCD controller.\n *\n * Based on code provided by Smoke And Wires\n * https://github.com/Smoke-And-Wires/TFT-Shield-Example-Code\n *\n * Copyright (C) 2015 Serge Vakulenko <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/param.h>\n#include <sys/gpanel.h>\n\n/*\n * Display orientation.\n */\ntypedef enum {\n    PORTRAIT,\n    LANDSCAPE,\n    PORTRAIT_UPSIDE_DOWN,\n    LANDSCAPE_UPSIDE_DOWN,\n} orient_t;\n\nstatic orient_t orientation;\n\n/*\n * ST7781 registers.\n */\n#define ST7781_Driver_ID_Code_Read                  0x00\n#define ST7781_Driver_Output_Control                0x01\n#define ST7781_LCD_Driving_Wave_Control             0x02\n#define ST7781_Entry_Mode                           0x03\n#define ST7781_Resize_Control                       0x04\n#define ST7781_Display_Control_1                    0x07\n#define ST7781_Display_control_2                    0x08\n#define ST7781_Display_Control_3                    0x09\n#define ST7781_Display_Control_4                    0x0A\n#define ST7781_Frame_Marker_Position                0x0D\n#define ST7781_Power_Control_1                      0x10\n#define ST7781_Power_Control_2                      0x11\n#define ST7781_Power_Control_3                      0x12\n#define ST7781_Power_Control_4                      0x13\n#define ST7781_DRAM_Horizontal_Address_Set          0x20\n#define ST7781_DRAM_Vertical_Address_Set            0x21\n#define ST7781_Write_Data_to_DRAM                   0x22\n#define ST7781_Read_Data_from_DRAM                  0x22\n#define ST7781_VCOMH_Control                        0x29\n#define ST7781_Frame_Rate_and_Color_Control         0x2B\n#define ST7781_Gamma_Control_1                      0x30\n#define ST7781_Gamma_Control_2                      0x31\n#define ST7781_Gamma_Control_3                      0x32\n#define ST7781_Gamma_Control_4                      0x35\n#define ST7781_Gamma_Control_5                      0x36\n#define ST7781_Gamma_Control_6                      0x37\n#define ST7781_Gamma_Control_7                      0x38\n#define ST7781_Gamma_Control_8                      0x39\n#define ST7781_Gamma_Control_9                      0x3C\n#define ST7781_Gamma_Control_10                     0x3D\n#define ST7781_Horizontal_Address_Start_Position    0x50\n#define ST7781_Horizontal_Address_End_Position      0x51\n#define ST7781_Vertical_Address_Start_Position      0x52\n#define ST7781_Vertical_Address_End_Position        0x53\n#define ST7781_Gate_Scan_Control_1                  0x60\n#define ST7781_Gate_Scan_Control_2                  0x61\n#define ST7781_Partial_Image_1_Display_Position     0x80\n#define ST7781_Partial_Image_1_Start_Address        0x81\n#define ST7781_Partial_Image_1_End_Address          0x82\n#define ST7781_Partial_Image_2_Display_Position     0x83\n#define ST7781_Partial_Image_2_Start_Address        0x84\n#define ST7781_Partial_Image_2_End_Address          0x85\n#define ST7781_Panel_Interface_Control_1            0x90\n#define ST7781_Panel_Interface_Control_2            0x92\n#define ST7781_EEPROM_ID_Code                       0xD2\n#define ST7781_EEPROM_Control_Status                0xD9\n#define ST7781_EEPROM_Wite_Command                  0xDF\n#define ST7781_EEPROM_Enable                        0xFA\n#define ST7781_EEPROM_VCOM_Offset                   0xFE\n#define ST7781_FAh_FEh_Enable                       0xFF\n\n/* Swap values of two integer variables. */\n#define swapi(x,y) { int _t = x; x = y; y = _t; }\n\n/*\n * Write a 16-bit value to the ST7781 register.\n */\nstatic void write_reg(unsigned reg, unsigned value)\n{\n    gpanel_rs_command();\n    gpanel_write_byte(reg >> 8);\n    gpanel_write_byte(reg);\n    gpanel_rs_data();\n    gpanel_write_byte(value >> 8);\n    gpanel_write_byte(value);\n}\n\nstatic void set_window(int x0, int y0, int x1, int y1)\n{\n    gpanel_cs_active();\n\n    /* Check rotation, move pixel around if necessary. */\n    switch (orientation) {\n    case PORTRAIT:\n        break;\n    case LANDSCAPE:\n        write_reg(ST7781_Entry_Mode, 0x1028);\n        swapi(x0, y0);\n        swapi(x1, y1);\n        x0 = 240 - x0 - 1;\n        x1 = 240 - x1 - 1;\n        swapi(x0, x1);\n        break;\n    case PORTRAIT_UPSIDE_DOWN:\n        write_reg(ST7781_Entry_Mode, 0x1000);\n        x0 = 240 - x0 - 1;\n        x1 = 240 - x1 - 1;\n        swapi(x0, x1);\n        y0 = 320 - y0 - 1;\n        y1 = 320 - y1 - 1;\n        swapi(y0, y1);\n        break;\n    case LANDSCAPE_UPSIDE_DOWN:\n        write_reg(ST7781_Entry_Mode, 0x1018);\n        swapi(x0, y0);\n        swapi(x1, y1);\n        y0 = 320 - y0 - 1;\n        y1 = 320 - y1 - 1;\n        swapi(y0, y1);\n        break;\n    }\n    /* Set address window. */\n    write_reg(ST7781_Horizontal_Address_Start_Position, x0);\n    write_reg(ST7781_Horizontal_Address_End_Position,   x1);\n    write_reg(ST7781_Vertical_Address_Start_Position,   y0);\n    write_reg(ST7781_Vertical_Address_End_Position,     y1);\n\n    /* Set address counter to top left. */\n    write_reg(ST7781_DRAM_Horizontal_Address_Set, x0);\n    write_reg(ST7781_DRAM_Vertical_Address_Set,   y0);\n    gpanel_cs_idle();\n}\n\nstatic void clear_window()\n{\n    gpanel_cs_active();\n    write_reg(ST7781_Entry_Mode, 0x1030);\n    write_reg(ST7781_Horizontal_Address_Start_Position, 0);\n    write_reg(ST7781_Horizontal_Address_End_Position,   240-1);\n    write_reg(ST7781_Vertical_Address_Start_Position,   0);\n    write_reg(ST7781_Vertical_Address_End_Position,     320-1);\n    gpanel_cs_idle();\n}\n\n/*\n * Draw a pixel.\n */\nstatic void st7781_set_pixel(int x, int y, int color)\n{\n    if (x < 0 || x >= gpanel_width || y < 0 || y >= gpanel_height)\n        return;\n\n    /* Check rotation, move pixel around if necessary. */\n    switch (orientation) {\n    case PORTRAIT:\n        break;\n    case LANDSCAPE:\n        swapi(x, y);\n        x = 240 - x - 1;\n        break;\n    case PORTRAIT_UPSIDE_DOWN:\n        x = 240 - x - 1;\n        y = 320 - y - 1;\n        break;\n    case LANDSCAPE_UPSIDE_DOWN:\n        swapi(x, y);\n        y = 320 - y - 1;\n        break;\n    }\n    gpanel_cs_active();\n    write_reg(ST7781_DRAM_Horizontal_Address_Set, x);\n    write_reg(ST7781_DRAM_Vertical_Address_Set,   y);\n    write_reg(ST7781_Write_Data_to_DRAM, color);\n    gpanel_cs_idle();\n}\n\n/*\n * Fast block fill operation.\n * Requires set_window() has previously been called to set\n * the fill bounds.\n * 'npixels' is inclusive, MUST be >= 1.\n */\nstatic void flood(int color, int npixels)\n{\n    unsigned blocks, i;\n    unsigned hi = color >> 8,\n             lo = color;\n\n    gpanel_cs_active();\n    gpanel_rs_command();\n    gpanel_write_byte(0x00); /* High address byte */\n    gpanel_write_byte(ST7781_Write_Data_to_DRAM);\n\n    /* Write first pixel normally, decrement counter by 1. */\n    gpanel_rs_data();\n    gpanel_write_byte(hi);\n    gpanel_write_byte(lo);\n    npixels--;\n\n    /* 64 pixels/block. */\n    blocks = npixels >> 6;\n    if (hi == lo) {\n        /* High and low bytes are identical.  Leave prior data\n         * on the port(s) and just toggle the write strobe. */\n        while (blocks--) {\n            /* 64 pixels/block / 4 pixels/pass. */\n            for (i = 16; i > 0; i--) {\n                /* 2 bytes/pixel x 4 pixels. */\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n                gpanel_wr_strobe();\n            }\n        }\n        /* Fill any remaining pixels (1 to 64). */\n        for (i = npixels & 63; i > 0; i--) {\n            gpanel_wr_strobe();\n            gpanel_wr_strobe();\n        }\n    } else {\n        while (blocks--) {\n            /* 64 pixels/block / 4 pixels/pass. */\n            for (i = 16; i > 0; i--) {\n                gpanel_write_byte(hi); gpanel_write_byte(lo);\n                gpanel_write_byte(hi); gpanel_write_byte(lo);\n                gpanel_write_byte(hi); gpanel_write_byte(lo);\n                gpanel_write_byte(hi); gpanel_write_byte(lo);\n            }\n        }\n        for (i = npixels & 63; i > 0; i--) {\n            gpanel_write_byte(hi);\n            gpanel_write_byte(lo);\n        }\n    }\n    gpanel_cs_idle();\n}\n\n/*\n * Fill a rectangle with specified color.\n */\nstatic void st7781_fill_rectangle(int x0, int y0, int x1, int y1, int color)\n{\n    if (x0 < 0) x0 = 0;\n    if (y0 < 0) x0 = 0;\n    if (x1 < 0) x1 = 0;\n    if (y1 < 0) x1 = 0;\n    if (x0 >= gpanel_width) x0 = gpanel_width-1;\n    if (x1 >= gpanel_width) x1 = gpanel_width-1;\n    if (y0 >= gpanel_height) y0 = gpanel_height-1;\n    if (y1 >= gpanel_height) y1 = gpanel_height-1;\n\n    if (x1 < x0) {\n        int t = x0;\n        x0 = x1;\n        x1 = t;\n    }\n    if (y1 < y0) {\n        int t = y0;\n        y0 = y1;\n        y1 = t;\n    }\n    set_window(x0, y0, x1, y1);\n    flood(color, (x1 - x0 + 1) * (y1 - y0 + 1));\n    clear_window();\n}\n\n/*\n * Fill a rectangle with user data.\n */\nstatic void st7781_draw_image(int x, int y, int width, int height,\n    const unsigned short *data)\n{\n    unsigned cnt = width * height;\n    int color;\n\n    set_window(x, y, x + width - 1, y + height - 1);\n    gpanel_cs_active();\n    gpanel_rs_command();\n    gpanel_write_byte(0x00); /* High address byte */\n    gpanel_write_byte(ST7781_Write_Data_to_DRAM);\n    gpanel_rs_data();\n    while (cnt--) {\n        color = *data++;\n        gpanel_write_byte(color >> 8);\n        gpanel_write_byte(color);\n    }\n    gpanel_cs_idle();\n    clear_window();\n}\n\n/*\n * Draw a glyph of one symbol.\n */\nstatic void st7781_draw_glyph(const struct gpanel_font_t *font,\n    int color, int background, int x, int y, int width,\n    const unsigned short *bits)\n{\n    int h, w, c;\n    unsigned bitmask = 0;\n\n    if (x + width > gpanel_width ||  y + font->height > gpanel_height)\n        return;\n\n    if (background >= 0) {\n        /*\n         * Clear background.\n         */\n        set_window(x, y, x + width - 1, y + font->height - 1);\n        gpanel_cs_active();\n        gpanel_rs_command();\n        gpanel_write_byte(0x00); /* High address byte */\n        gpanel_write_byte(ST7781_Write_Data_to_DRAM);\n        gpanel_rs_data();\n\n        /* Loop on each glyph row. */\n        for (h=0; h<font->height; h++) {\n            /* Loop on every pixel in the row (left to right). */\n            for (w=0; w<width; w++) {\n                if ((w & 15) == 0)\n                    bitmask = *bits++;\n                else\n                    bitmask <<= 1;\n\n                c = (bitmask & 0x8000) ? color : background;\n                gpanel_write_byte(c >> 8);\n                gpanel_write_byte(c);\n            }\n        }\n        gpanel_cs_idle();\n        clear_window();\n    } else {\n        /*\n         * Transparent background.\n         */\n        /* Loop on each glyph row. */\n        for (h=0; h<font->height; h++) {\n            /* Loop on every pixel in the row (left to right). */\n            for (w=0; w<width; w++) {\n                if ((w & 15) == 0)\n                    bitmask = *bits++;\n                else\n                    bitmask <<= 1;\n\n                if (bitmask & 0x8000)\n                    st7781_set_pixel(x + w, y + h, color);\n            }\n        }\n    }\n}\n\n/*\n * Switch the screen orientation.\n */\nstatic void set_rotation(orient_t rotation)\n{\n    orientation = rotation;\n    switch (orientation) {\n    case PORTRAIT:\n        gpanel_width  = 240;\n        gpanel_height = 320;\n        break;\n    case LANDSCAPE:\n        gpanel_width  = 320;\n        gpanel_height = 240;\n        break;\n    case PORTRAIT_UPSIDE_DOWN:\n        gpanel_width  = 240;\n        gpanel_height = 320;\n        break;\n    case LANDSCAPE_UPSIDE_DOWN:\n        gpanel_width  = 320;\n        gpanel_height = 240;\n        break;\n    }\n}\n\nstatic void st7781_resize(struct gpanel_hw *h, int width, int height)\n{\n    gpanel_cs_active();\n\n    /* Switch screen orientaation. */\n    if (width > height)\n        set_rotation(LANDSCAPE);\n    else if (width < height)\n        set_rotation(PORTRAIT);\n\n    gpanel_cs_idle();\n}\n\n/*\n * Initialize the LCD controller.\n * Fill the gpanel_hw descriptor.\n */\nvoid st7781_init_display(struct gpanel_hw *h)\n{\n    /* Initialization of LCD controller. */\n    gpanel_cs_active();\n    write_reg(ST7781_Driver_Output_Control,    0x0100);\n    write_reg(ST7781_LCD_Driving_Wave_Control, 0x0700);\n    write_reg(ST7781_Display_control_2,        0x0302);\n    write_reg(ST7781_Display_Control_3,        0x0000);\n    write_reg(ST7781_Display_Control_4,        0x0008);\n\n    /* Power control registers. */\n    write_reg(ST7781_Power_Control_1, 0x0790);\n    write_reg(ST7781_Power_Control_2, 0x0005);\n    write_reg(ST7781_Power_Control_3, 0x0000);\n    write_reg(ST7781_Power_Control_4, 0x0000);\n\n    /* Power supply startup 1 settings. */\n    write_reg(ST7781_Power_Control_1, 0x12B0);\n    write_reg(ST7781_Power_Control_2, 0x0007);\n\n    /* Power supply startup 2 settings. */\n    write_reg(ST7781_Power_Control_3, 0x008C);\n    write_reg(ST7781_Power_Control_4, 0x1700);\n    write_reg(ST7781_VCOMH_Control,   0x0022);\n\n    /* Gamma cluster settings. */\n    write_reg(ST7781_Gamma_Control_1,  0x0000);\n    write_reg(ST7781_Gamma_Control_2,  0x0505);\n    write_reg(ST7781_Gamma_Control_3,  0x0205);\n    write_reg(ST7781_Gamma_Control_4,  0x0206);\n    write_reg(ST7781_Gamma_Control_5,  0x0408);\n    write_reg(ST7781_Gamma_Control_6,  0x0000);\n    write_reg(ST7781_Gamma_Control_7,  0x0504);\n    write_reg(ST7781_Gamma_Control_8,  0x0206);\n    write_reg(ST7781_Gamma_Control_9,  0x0206);\n    write_reg(ST7781_Gamma_Control_10, 0x0408);\n\n    /* Frame rate settings. */\n    write_reg(ST7781_Gate_Scan_Control_1,       0xA700);\n    write_reg(ST7781_Gate_Scan_Control_2,       0x0001);\n    write_reg(ST7781_Panel_Interface_Control_1, 0x0033); // RTNI setting\n\n    /* Display on. */\n    write_reg(ST7781_Display_Control_1, 0x0133);\n    clear_window();\n\n    /* Screen orientation. */\n    set_rotation(LANDSCAPE);\n\n    /* Fill the gpanel_hw descriptor. */\n    h->name           = \"Sitronix ST7781\";\n    h->resize         = st7781_resize;\n    h->set_pixel      = st7781_set_pixel;\n    h->fill_rectangle = st7781_fill_rectangle;\n    h->draw_image     = st7781_draw_image;\n    h->draw_glyph     = st7781_draw_glyph;\n}\n"
  },
  {
    "path": "sys/arch/pic32/dev/gpanel.c",
    "content": "/*\n * Generic TFT LCD driver for PIC32.\n * Supported chips: ST7781, NT35702, ILI9341.\n *\n * Copyright (C) 2015 Serge Vakulenko <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/param.h>\n#include <sys/conf.h>\n#include <sys/user.h>\n#include <sys/ioctl.h>\n#include <sys/systm.h>\n#include <sys/uio.h>\n#include <sys/tty.h>\n#include <sys/config.h>\n#include <sys/gpanel.h>\n\n/*\n * Descriptor for access to the hardware-level driver.\n */\nstatic struct gpanel_hw hw;\n\n/*\n * Cursor position for text output.\n */\nstatic int _col, _row;\n\n/*\n * ID of the LCD controller chip.\n */\nstatic int _chip_id;\n\n/*\n * Display size.\n */\nint gpanel_width, gpanel_height;\n\n/*\n * Delay for 100 nanoseconds.\n * Needed to match the /WR and /RD timing requirements.\n */\n#if CPU_KHZ <= 10000\n#   define delay100ns()     /* empty */\n#elif CPU_KHZ <= 20000\n#   define delay100ns()     asm volatile(\"nop\")\n#elif CPU_KHZ <= 30000\n#   define delay100ns()     asm volatile(\"nop; nop\")\n#elif CPU_KHZ <= 40000\n#   define delay100ns()     asm volatile(\"nop; nop; nop\")\n#elif CPU_KHZ <= 50000\n#   define delay100ns()     asm volatile(\"nop; nop; nop; nop\")\n#elif CPU_KHZ <= 60000\n#   define delay100ns()     asm volatile(\"nop; nop; nop; nop; nop\")\n#elif CPU_KHZ <= 70000\n#   define delay100ns()     asm volatile(\"nop; nop; nop; nop; nop; nop\")\n#else\n#   define delay100ns()     asm volatile(\"nop; nop; nop; nop; nop; nop; nop; nop\")\n#endif\n\n/*\n * Signal mappings:\n *  /RESET  - reset and initialize the chip.\n *  /CS     - chip select when low.\n *  /RD     - read operation enable.\n *  /WR     - write operation enable.\n *  RS      - command or data mode selection.\n *  D0-D7   - data bus, bidirectional.\n */\n#define RST_IDLE()      LAT_SET(LCD_RST_PORT) = 1<<LCD_RST_PIN\n#define RST_ACTIVE()    LAT_CLR(LCD_RST_PORT) = 1<<LCD_RST_PIN\n\n#define CS_IDLE()       LAT_SET(LCD_CS_PORT) = 1<<LCD_CS_PIN\n#define CS_ACTIVE()     LAT_CLR(LCD_CS_PORT) = 1<<LCD_CS_PIN\n\n#define RD_IDLE()       LAT_SET(LCD_RD_PORT) = 1<<LCD_RD_PIN\n#define RD_ACTIVE()     LAT_CLR(LCD_RD_PORT) = 1<<LCD_RD_PIN\n\n#define WR_IDLE()       LAT_SET(LCD_WR_PORT) = 1<<LCD_WR_PIN\n#define WR_ACTIVE()     LAT_CLR(LCD_WR_PORT) = 1<<LCD_WR_PIN\n\n#define RS_DATA()       LAT_SET(LCD_RS_PORT) = 1<<LCD_RS_PIN\n#define RS_COMMAND()    LAT_CLR(LCD_RS_PORT) = 1<<LCD_RS_PIN\n\n/*\n * Set direction of data bus as output.\n */\nvoid gpanel_write_dir()\n{\n    TRIS_CLR(LCD_D0_PORT) = 1 << LCD_D0_PIN;\n    TRIS_CLR(LCD_D1_PORT) = 1 << LCD_D1_PIN;\n    TRIS_CLR(LCD_D2_PORT) = 1 << LCD_D2_PIN;\n    TRIS_CLR(LCD_D3_PORT) = 1 << LCD_D3_PIN;\n    TRIS_CLR(LCD_D4_PORT) = 1 << LCD_D4_PIN;\n    TRIS_CLR(LCD_D5_PORT) = 1 << LCD_D5_PIN;\n    TRIS_CLR(LCD_D6_PORT) = 1 << LCD_D6_PIN;\n    TRIS_CLR(LCD_D7_PORT) = 1 << LCD_D7_PIN;\n}\n\n/*\n * Set direction of data bus as input.\n */\nvoid gpanel_read_dir()\n{\n    TRIS_SET(LCD_D0_PORT) = 1 << LCD_D0_PIN;\n    TRIS_SET(LCD_D1_PORT) = 1 << LCD_D1_PIN;\n    TRIS_SET(LCD_D2_PORT) = 1 << LCD_D2_PIN;\n    TRIS_SET(LCD_D3_PORT) = 1 << LCD_D3_PIN;\n    TRIS_SET(LCD_D4_PORT) = 1 << LCD_D4_PIN;\n    TRIS_SET(LCD_D5_PORT) = 1 << LCD_D5_PIN;\n    TRIS_SET(LCD_D6_PORT) = 1 << LCD_D6_PIN;\n    TRIS_SET(LCD_D7_PORT) = 1 << LCD_D7_PIN;\n}\n\n/*\n * Control /CS signal.\n */\nvoid gpanel_cs_active() { CS_ACTIVE(); }\nvoid gpanel_cs_idle()   { CS_IDLE(); }\n\n/*\n * Control /RS signal.\n */\nvoid gpanel_rs_command() { RS_COMMAND(); }\nvoid gpanel_rs_data()    { RS_DATA(); }\n\n/*\n * Generate a /WR strobe.\n */\nvoid gpanel_wr_strobe()\n{\n    delay100ns();\n    WR_ACTIVE();\n    delay100ns();\n    WR_IDLE();\n}\n\n/*\n * Send a byte to the data bus.\n */\nvoid gpanel_write_byte(int value)\n{\n    if (value & 1) {\n        LAT_SET(LCD_D0_PORT) = 1 << LCD_D0_PIN;\n    } else {\n        LAT_CLR(LCD_D0_PORT) = 1 << LCD_D0_PIN;\n    }\n    if (value & 2) {\n        LAT_SET(LCD_D1_PORT) = 1 << LCD_D1_PIN;\n    } else {\n        LAT_CLR(LCD_D1_PORT) = 1 << LCD_D1_PIN;\n    }\n    if (value & 4) {\n        LAT_SET(LCD_D2_PORT) = 1 << LCD_D2_PIN;\n    } else {\n        LAT_CLR(LCD_D2_PORT) = 1 << LCD_D2_PIN;\n    }\n    if (value & 8) {\n        LAT_SET(LCD_D3_PORT) = 1 << LCD_D3_PIN;\n    } else {\n        LAT_CLR(LCD_D3_PORT) = 1 << LCD_D3_PIN;\n    }\n    if (value & 0x10) {\n        LAT_SET(LCD_D4_PORT) = 1 << LCD_D4_PIN;\n    } else {\n        LAT_CLR(LCD_D4_PORT) = 1 << LCD_D4_PIN;\n    }\n    if (value & 0x20) {\n        LAT_SET(LCD_D5_PORT) = 1 << LCD_D5_PIN;\n    } else {\n        LAT_CLR(LCD_D5_PORT) = 1 << LCD_D5_PIN;\n    }\n    if (value & 0x40) {\n        LAT_SET(LCD_D6_PORT) = 1 << LCD_D6_PIN;\n    } else {\n        LAT_CLR(LCD_D6_PORT) = 1 << LCD_D6_PIN;\n    }\n    if (value & 0x80) {\n        LAT_SET(LCD_D7_PORT) = 1 << LCD_D7_PIN;\n    } else {\n        LAT_CLR(LCD_D7_PORT) = 1 << LCD_D7_PIN;\n    }\n    WR_ACTIVE();\n    delay100ns();\n    WR_IDLE();\n}\n\n/*\n * Read a byte from the data bus.\n */\nint gpanel_read_byte()\n{\n    int value = 0;\n\n    RD_ACTIVE();\n    delay100ns();\n    if (PORT_VAL(LCD_D0_PORT) & (1 << LCD_D0_PIN)) value |= 1;\n    if (PORT_VAL(LCD_D1_PORT) & (1 << LCD_D1_PIN)) value |= 2;\n    if (PORT_VAL(LCD_D2_PORT) & (1 << LCD_D2_PIN)) value |= 4;\n    if (PORT_VAL(LCD_D3_PORT) & (1 << LCD_D3_PIN)) value |= 8;\n    if (PORT_VAL(LCD_D4_PORT) & (1 << LCD_D4_PIN)) value |= 0x10;\n    if (PORT_VAL(LCD_D5_PORT) & (1 << LCD_D5_PIN)) value |= 0x20;\n    if (PORT_VAL(LCD_D6_PORT) & (1 << LCD_D6_PIN)) value |= 0x40;\n    if (PORT_VAL(LCD_D7_PORT) & (1 << LCD_D7_PIN)) value |= 0x80;\n    RD_IDLE();\n    return value;\n}\n\n/*\n * Read a 16-bit value from the specified chip register.\n */\nstatic int read_reg16(int reg)\n{\n    unsigned value;\n\n    CS_ACTIVE();\n    RS_COMMAND();\n    gpanel_write_byte(reg >> 8);    /* Need 2 bytes of address for ST7781 */\n    gpanel_write_byte(reg);\n    gpanel_read_dir();              /* Switch data bus to input */\n    RS_DATA();\n    value = gpanel_read_byte() << 8;\n    value |= gpanel_read_byte();\n    gpanel_write_dir();             /* Restore data bus as output */\n    CS_IDLE();\n    return value;\n}\n\n/*\n * Read a 32-bit value from the specified chip register.\n */\nstatic int read_reg32(int reg)\n{\n    unsigned value;\n\n    CS_ACTIVE();\n    RS_COMMAND();\n    gpanel_write_byte(reg);\n    gpanel_read_dir();              /* Switch data bus to input */\n    RS_DATA();\n    value = gpanel_read_byte() << 24;\n    value |= gpanel_read_byte() << 16;\n    value |= gpanel_read_byte() << 8;\n    value |= gpanel_read_byte();\n    gpanel_write_dir();             /* Restore data bus as output */\n    CS_IDLE();\n    return value;\n}\n\n/*\n * Draw a line.\n */\nstatic void gpanel_draw_line(int x0, int y0, int x1, int y1, int color)\n{\n    int dx, dy, stepx, stepy, fraction;\n\n    if (x0 == x1 || y0 == y1) {\n        hw.fill_rectangle(x0, y0, x1, y1, color);\n        return;\n    }\n\n    /* Use Bresenham's line algorithm. */\n    dy = y1 - y0;\n    if (dy < 0) {\n        dy = -dy;\n        stepy = -1;\n    } else {\n        stepy = 1;\n    }\n    dx = x1 - x0;\n    if (dx < 0) {\n        dx = -dx;\n        stepx = -1;\n    } else {\n        stepx = 1;\n    }\n    dy <<= 1;                           /* dy is now 2*dy */\n    dx <<= 1;                           /* dx is now 2*dx */\n    hw.set_pixel(x0, y0, color);\n    if (dx > dy) {\n        fraction = dy - (dx >> 1);      /* same as 2*dy - dx */\n        while (x0 != x1) {\n            if (fraction >= 0) {\n                y0 += stepy;\n                fraction -= dx;         /* same as fraction -= 2*dx */\n            }\n            x0 += stepx;\n            fraction += dy;             /* same as fraction -= 2*dy */\n            hw.set_pixel(x0, y0, color);\n        }\n    } else {\n        fraction = dx - (dy >> 1);\n        while (y0 != y1) {\n            if (fraction >= 0) {\n                x0 += stepx;\n                fraction -= dy;\n            }\n            y0 += stepy;\n            fraction += dx;\n            hw.set_pixel(x0, y0, color);\n        }\n    }\n}\n\n/*\n * Draw a rectangular frame.\n */\nstatic void gpanel_draw_frame(int x0, int y0, int x1, int y1, int color)\n{\n    hw.fill_rectangle(x0, y0, x1, y0, color);\n    hw.fill_rectangle(x0, y1, x1, y1, color);\n    hw.fill_rectangle(x0, y0, x0, y1, color);\n    hw.fill_rectangle(x1, y0, x1, y1, color);\n}\n\n/*\n * Draw a circle.\n */\nstatic void gpanel_draw_circle(int x0, int y0, int radius, int color)\n{\n    int f = 1 - radius;\n    int ddF_x = 0;\n    int ddF_y = -2 * radius;\n    int x = 0;\n    int y = radius;\n\n    hw.set_pixel(x0, y0 + radius, color);\n    hw.set_pixel(x0, y0 - radius, color);\n    hw.set_pixel(x0 + radius, y0, color);\n    hw.set_pixel(x0 - radius, y0, color);\n    while (x < y) {\n        if (f >= 0) {\n            y--;\n            ddF_y += 2;\n            f += ddF_y;\n        }\n        x++;\n        ddF_x += 2;\n        f += ddF_x + 1;\n        hw.set_pixel(x0 + x, y0 + y, color);\n        hw.set_pixel(x0 - x, y0 + y, color);\n        hw.set_pixel(x0 + x, y0 - y, color);\n        hw.set_pixel(x0 - x, y0 - y, color);\n        hw.set_pixel(x0 + y, y0 + x, color);\n        hw.set_pixel(x0 - y, y0 + x, color);\n        hw.set_pixel(x0 + y, y0 - x, color);\n        hw.set_pixel(x0 - y, y0 - x, color);\n    }\n}\n\n/*\n * Draw a character from a specified font.\n */\nstatic void gpanel_draw_char(const struct gpanel_font_t *font,\n    int color, int background, int sym)\n{\n    unsigned cindex, width;\n    const unsigned short *bits;\n\n    switch (sym) {\n    case '\\n':      /* goto next line */\n        _row += font->height;\n        _col = 0;\n        if (_row > gpanel_height - font->height)\n            _row = 0;\n        return;\n    case '\\r':      /* carriage return - go to begin of line */\n        _col = 0;\n        return;\n    case '\\t':      /* tab replaced by space */\n        sym = ' ';\n        break;\n    }\n\n    if (sym < font->firstchar || sym >= font->firstchar + font->size)\n        sym = font->defaultchar;\n    cindex = sym - font->firstchar;\n\n    /* Get font bitmap depending on fixed pitch or not. */\n    if (font->width) {\n        /* Proportional font. */\n        width = font->width[cindex];\n    } else {\n        /* Fixed width font. */\n        width = font->maxwidth;\n    }\n    if (font->offset) {\n        bits = font->bits + font->offset[cindex];\n    } else {\n        bits = font->bits + cindex * font->height;\n    }\n\n    /* Draw a character. */\n    hw.draw_glyph(font, color, background, _col, _row, width, bits);\n    _col += width;\n}\n\n/*\n * Draw a string of characters.\n * TODO: Decode UTF-8.\n */\nstatic void gpanel_draw_text(const struct gpanel_font_t *font,\n    int color, int background, int x, int y, const char *text)\n{\n    int sym;\n\n    _col = x;\n    _row = y;\n    for (;;) {\n        sym = *text++;\n        if (! sym)\n            break;\n\n        gpanel_draw_char(font, color, background, sym);\n    }\n}\n\nint gpanel_open(dev_t dev, int flag, int mode)\n{\n    if (minor(dev) != 0)\n        return ENODEV;\n    return 0;\n}\n\nint gpanel_close(dev_t dev, int flag, int mode)\n{\n    return 0;\n}\n\nint gpanel_read(dev_t dev, struct uio *uio, int flag)\n{\n    return ENODEV;\n}\n\nint gpanel_write(dev_t dev, struct uio *uio, int flag)\n{\n    return ENODEV;\n}\n\n/*\n * TODO: check whether user pointers are valid.\n */\nint gpanel_ioctl(dev_t dev, register u_int cmd, caddr_t addr, int flag)\n{\n    switch (cmd) {\n        /*\n         * Clear the whole screen with a given color.\n         */\n        case GPANEL_CLEAR: {\n            struct gpanel_clear_t *param = (struct gpanel_clear_t*) addr;\n\n            if (hw.resize != 0)\n                hw.resize(&hw, param->xsize, param->ysize);\n            hw.fill_rectangle(0, 0, gpanel_width - 1, gpanel_height - 1, param->color);\n            param->xsize = gpanel_width;\n            param->ysize = gpanel_height;\n            break;\n        }\n\n        /*\n         * Draw a single pixel.\n         */\n        case GPANEL_PIXEL: {\n            struct gpanel_pixel_t *param = (struct gpanel_pixel_t*) addr;\n\n            hw.set_pixel(param->x, param->y, param->color);\n            break;\n        }\n\n        /*\n         * Draw a line.\n         */\n        case GPANEL_LINE: {\n            struct gpanel_line_t *param = (struct gpanel_line_t*) addr;\n\n            gpanel_draw_line(param->x0, param->y0, param->x1, param->y1, param->color);\n            break;\n        }\n\n        /*\n         * Draw a rectangle frame.\n         */\n        case GPANEL_RECT: {\n            struct gpanel_rect_t *param = (struct gpanel_rect_t*) addr;\n\n            gpanel_draw_frame(param->x0, param->y0, param->x1, param->y1, param->color);\n            break;\n        }\n\n        /*\n         * Fill a rectangle with color.\n         */\n        case GPANEL_FILL: {\n            struct gpanel_rect_t *param = (struct gpanel_rect_t*) addr;\n\n            hw.fill_rectangle(param->x0, param->y0, param->x1, param->y1, param->color);\n            break;\n        }\n\n        /*\n         * Draw a circle.\n         */\n        case GPANEL_CIRCLE: {\n            struct gpanel_circle_t *param = (struct gpanel_circle_t*) addr;\n\n            gpanel_draw_circle(param->x, param->y, param->radius, param->color);\n            break;\n        }\n\n        /*\n         * Fill a rectangular area with the user-supplied data.\n         */\n        case GPANEL_IMAGE: {\n            struct gpanel_image_t *param = (struct gpanel_image_t*) addr;\n\n            hw.draw_image(param->x, param->y, param->width, param->height,\n                param->image);\n            break;\n        }\n\n        /*\n         * Draw a character.\n         */\n        case GPANEL_CHAR: {\n            struct gpanel_char_t *param = (struct gpanel_char_t*) addr;\n\n            _col = param->x;\n            _row = param->y;\n            gpanel_draw_char(param->font, param->color, param->background, param->sym);\n            break;\n        }\n\n        /*\n         * Draw a string of characters.\n         */\n        case GPANEL_TEXT: {\n            struct gpanel_text_t *param = (struct gpanel_text_t*) addr;\n\n            gpanel_draw_text(param->font, param->color, param->background,\n                param->x, param->y, param->text);\n            break;\n        }\n    }\n    return 0;\n}\n\n/*\n * Draw a BSD logo on the screen.\n */\nstatic void draw_logo()\n{\n#define K       7\n#define COLOR_B 0xf81f\n#define COLOR_S 0x07ff\n#define COLOR_D 0xffe0\n\n    int x = gpanel_width/2  - 17*K;\n    int y = gpanel_height/2 + 11*K;\n\n    hw.fill_rectangle(0, 0, gpanel_width - 1, gpanel_height - 1, 0);\n\n    /* B */\n    gpanel_draw_line( 0*K+x, y- 0*K,  0*K+x, y-11*K, COLOR_B);\n    gpanel_draw_line( 0*K+x, y-11*K,  0*K+x, y-22*K, COLOR_B);\n    gpanel_draw_line( 0*K+x, y-22*K, 10*K+x, y-19*K, COLOR_B);\n    gpanel_draw_line(10*K+x, y-19*K,  0*K+x, y-11*K, COLOR_B);\n    gpanel_draw_line( 0*K+x, y-11*K, 10*K+x, y- 8*K, COLOR_B);\n    gpanel_draw_line(10*K+x, y- 8*K,  0*K+x, y- 0*K, COLOR_B);\n\n    /* S */\n    gpanel_draw_line(22*K+x, y-22*K, 12*K+x, y-19*K, COLOR_S);\n    gpanel_draw_line(12*K+x, y-19*K, 22*K+x, y- 8*K, COLOR_S);\n    gpanel_draw_line(22*K+x, y- 8*K, 12*K+x, y- 0*K, COLOR_S);\n\n    /* D */\n    gpanel_draw_line(24*K+x, y-22*K, 24*K+x, y- 0*K, COLOR_D);\n    gpanel_draw_line(24*K+x, y-22*K, 34*K+x, y-19*K, COLOR_D);\n    gpanel_draw_line(34*K+x, y-19*K, 34*K+x, y- 8*K, COLOR_D);\n    gpanel_draw_line(34*K+x, y- 8*K, 24*K+x, y- 0*K, COLOR_D);\n}\n\n/*\n * Read the the chip ID register.\n * Some controllers have a register #0\n * programmed with unique chip ID.\n */\nstatic int read_id()\n{\n    int id, retry;\n\n    /* Some controllers have a register #0\n     * programmed with unique chip ID. */\n    id = read_reg16(0);\n    if (id != 0)\n        return id;\n\n    /* Try ID from register #4. */\n    id = read_reg32(4) & 0xffffff;\n    if (id != 0)\n        return id;\n\n    /* Try ID from register #D3.\n     * Might need to wait until the register becomes alive after Reset. */\n    for (retry=0; retry<5; retry++) {\n        id = read_reg32(0xD3) & 0xffffff;\n        if (id != 0)\n            return id;\n        udelay(50000);\n    }\n    return 0;\n}\n\n/*\n * Detect the type of the LCD controller, and initialize it.\n * Return true if found and initialized ok.\n */\nstatic int probe(config)\n    struct conf_device *config;\n{\n    /*\n     * Set all control bits to high (idle).\n     * Signals are active low.\n     */\n    CS_IDLE();\n    WR_IDLE();\n    RD_IDLE();\n    RST_IDLE();\n\n    /* Enable outputs. */\n    TRIS_CLR(LCD_CS_PORT) = 1 << LCD_CS_PIN;\n    TRIS_CLR(LCD_RS_PORT) = 1 << LCD_RS_PIN;\n    TRIS_CLR(LCD_WR_PORT) = 1 << LCD_WR_PIN;\n    TRIS_CLR(LCD_RD_PORT) = 1 << LCD_RD_PIN;\n    TRIS_CLR(LCD_RST_PORT) = 1 << LCD_RST_PIN;\n    gpanel_write_dir();\n\n    /* Reset the chip. */\n    RST_ACTIVE();\n    udelay(1000);\n    RST_IDLE();\n    udelay(1000);\n\n    /* Read the the chip ID register.\n     * Some controllers have a register #0\n     * programmed with unique chip ID. */\n    _chip_id = read_id();\n    switch (_chip_id) {\n    default:\n        printf(\"gpanel0: Unknown chip ID = 0x%04x\\n\", _chip_id);\n        goto failed;\n\n    case 0x7783:\n        /* Sitronix ST7781. */\n        st7781_init_display(&hw);\n        break;\n\n    case 0x009341:\n        /* Ilitek ILI9341. */\n        ili9341_init_display(&hw);\n        break;\n\n    case 0x012200:\n        /* Ilitek ILI9481. */\n        ili9481_init_display(&hw);\n        break;\n\n    case 0x388000:\n        /* Novatek NT35702. */\n        nt35702_init_display(&hw);\n        break;\n    }\n    printf(\"gpanel0: <%s> display %ux%u\\n\", hw.name, gpanel_width, gpanel_height);\n    draw_logo();\n    return 1;\n\nfailed:\n    /* Disable outputs. */\n    gpanel_read_dir();\n    TRIS_SET(LCD_CS_PORT) = 1 << LCD_CS_PIN;\n    TRIS_SET(LCD_RS_PORT) = 1 << LCD_RS_PIN;\n    TRIS_SET(LCD_WR_PORT) = 1 << LCD_WR_PIN;\n    TRIS_SET(LCD_RD_PORT) = 1 << LCD_RD_PIN;\n    TRIS_SET(LCD_RST_PORT) = 1 << LCD_RST_PIN;\n    return 0;\n}\n\nstruct driver gpaneldriver = {\n    \"gpanel\", probe,\n};\n"
  },
  {
    "path": "sys/arch/pic32/dev/gpio.c",
    "content": "/*\n * GPIO driver for PIC32.\n *\n * Copyright (C) 2012 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/param.h>\n#include <sys/conf.h>\n#include <sys/user.h>\n#include <sys/ioctl.h>\n#include <sys/gpio.h>\n#include <sys/systm.h>\n#include <sys/uio.h>\n#include <sys/config.h>\n\n/*\n * Devices:\n *      /dev/porta ... /dev/portg\n *      /dev/confa ... /dev/confg\n *\n * Example:\n *      echo ....oiiid....iiii > /dev/confa\n *      echo ....1...0........ > /dev/porta\n *\n * Write to /dev/confX:\n *      'i' - configure the corresponding port pin as an input;\n *      'o' - configure the corresponding port pin as an output;\n *      'd' - configure the corresponding port pin as an open-drain output;\n *      'x' - deconfigure the corresponding port pin;\n *      '.' - no action.\n *\n * Write to /dev/portX:\n *      '0' - set output pin low;\n *      '1' - set output pin high;\n *      '+' - invert the value of output pin;\n *      '.' - no action.\n *\n * Use ioctl() on any of devices to control pins from the user program.\n *      ioctl(fd, GPIO_PORTA |  GPIO_CONFIN, mask)  - configure as input\n *      ioctl(fd, GPIO_PORTB |  GPIO_CONFOUT,mask)  - configure as output\n *      ioctl(fd, GPIO_PORTC |  GPIO_CONFOD, mask)  - configure as open drain\n *      ioctl(fd, GPIO_PORTD |  GPIO_DECONF, mask)  - deconfigure\n *      ioctl(fd, GPIO_PORTE |  GPIO_STORE,  val)   - set values of all pins\n *      ioctl(fd, GPIO_PORTF |  GPIO_SET,    mask)  - set to 1 by mask\n *      ioctl(fd, GPIO_PORTG |  GPIO_CLEAR,  mask)  - set to 0 by mask\n *      ioctl(fd, GPIO_PORT(0)| GPIO_INVERT, mask)  - invert by mask\n * val= ioctl(fd, GPIO_PORT(1)| GPIO_POLL,   0)     - get input values\n *\n * Several operations can be combined in one call.\n * For example, to toggle pin A2 high thew low, and get value\n * of all PORTA pins:\n * val = ioctl(fd, GPIO_PORTA | GPIO_SET | GPIO_CLEAR | GPIO_POLL, 1<<3);\n */\n#define NGPIO           7               /* Ports A, B, C, D, E, F, G */\n#define NPINS           16              /* Number of pins per port */\n\n#define MINOR_CONF      0x40            /* Minor mask: /dev/confX */\n#define MINOR_UNIT      0x07            /* Minor mask: unit number */\n\n/*\n * Some pins are actually not available in hardware.\n * Here are masks of real pins.\n */\n#define MASK(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p) \\\n    (a<<15 | b<<14 | c<<13 | d<<12 | e<<11 | f<<10 | g<<9 | h<<8 | \\\n     i<<7  | j<<6  | k<<5  | l<<4  | m<<3  | n<<2  | o<<1 | p)\n\n/*\n * Mask of configured pins, default empty.\n */\nu_int gpio_confmask [NGPIO];\n\n/*\n * To enable debug output, comment out the first line,\n * and uncomment the second line.\n */\n#define PRINTDBG(...) /*empty*/\n//#define PRINTDBG printf\n\nstatic void\ngpio_print (dev, buf)\n    dev_t dev;\n    char *buf;\n{\n    u_int unit = minor(dev) & MINOR_UNIT;\n    register struct gpioreg *reg = unit + (struct gpioreg*) &TRISA;\n    register u_int mask, conf, tris;\n    register char c;\n\n    conf = gpio_confmask[unit];\n    tris = reg->tris;\n    if (minor(dev) & MINOR_CONF) {\n        /* /dev/confX device: port configuration mask */\n        u_int odc = reg->odc;\n        for (mask=1<<(NPINS-1); mask; mask>>=1) {\n            if (! (conf & mask))\n                c = '-';\n            else if (tris & mask)\n                c = 'i';\n            else\n                c = (odc & mask) ? 'd' : 'o';\n            *buf++ = c;\n        }\n    } else {\n        /* /dev/portX device: port value mask */\n        u_int lat = reg->lat;\n        u_int port = reg->port;\n        for (mask=1<<(NPINS-1); mask; mask>>=1) {\n            if (! (conf & mask))\n                c = '-';\n            else if (tris & mask)\n                c = (port & mask) ? '1' : '0';\n            else\n                c = (lat & mask) ? '1' : '0';\n            *buf++ = c;\n        }\n    }\n    *buf++ = '\\n';\n    *buf = 0;\n}\n\nstatic void\ngpio_parse (dev, buf)\n    dev_t dev;\n    char *buf;\n{\n    u_int unit = minor(dev) & MINOR_UNIT;\n    register struct gpioreg *reg = unit + (struct gpioreg*) &TRISA;\n    register u_int mask;\n    register char c;\n\n    if (minor(dev) & MINOR_CONF) {\n        /* /dev/confX device: port configuration mask */\n        for (mask=1<<(NPINS-1); mask; mask>>=1) {\n            c = *buf++;\n            if (c <= ' ' || c > '~')\n                break;\n\n            if (c == 'x' || c == 'X') {\n                gpio_confmask[unit] &= ~mask;\n                reg->trisset = mask;\n            } else if (c == 'i' || c == 'I') {\n                gpio_confmask[unit] |= mask;\n                reg->trisset = mask;\n            } else if (c == 'o' || c == 'O') {\n                gpio_confmask[unit] |= mask;\n                reg->odcclr = mask;\n                reg->trisclr = mask;\n            } else if (c == 'd' || c == 'D') {\n                gpio_confmask[unit] |= mask;\n                reg->odcset = mask;\n                reg->trisclr = mask;\n            }\n        }\n    } else {\n        /* /dev/portX device: port value mask */\n        u_int conf = gpio_confmask[unit];\n        u_int tris = reg->tris;\n        for (mask=1<<(NPINS-1); mask; mask>>=1) {\n            c = *buf++;\n            if (c <= ' ' || c > '~')\n                break;\n\n            if (! (conf & mask) || (tris & mask))\n                continue;\n\n            if (c == '0')\n                reg->latclr = mask;\n            else\n                reg->latset = mask;\n        }\n    }\n}\n\nint\ngpioopen (dev, flag, mode)\n    dev_t dev;\n    int flag;\n    int mode;\n{\n    register u_int unit = minor(dev) & MINOR_UNIT;\n\n    if (unit >= NGPIO)\n        return ENXIO;\n    if (u.u_uid != 0)\n        return EPERM;\n    return 0;\n}\n\nint\ngpioclose (dev, flag, mode)\n    dev_t dev;\n    int flag;\n    int mode;\n{\n    return 0;\n}\n\nint\ngpioread (dev, uio, flag)\n    dev_t dev;\n    struct uio *uio;\n    int flag;\n{\n    register struct iovec *iov;\n    register u_int cnt = NPINS + 1;\n    char buf [20];\n\n    /* I/o size should be large enough. */\n    iov = uio->uio_iov;\n    if (iov->iov_len < cnt)\n        return EIO;\n\n    /* Read only cnt bytes. */\n    if (uio->uio_offset >= cnt)\n        return 0;\n    cnt -= uio->uio_offset;\n\n    /* Print port status to buffer. */\n    gpio_print (dev, buf);\n    //PRINTDBG (\"gpioread -> %s\", buf);\n\n    bcopy (buf + uio->uio_offset, iov->iov_base, cnt);\n    iov->iov_base += cnt;\n    iov->iov_len -= cnt;\n    uio->uio_resid -= cnt;\n    uio->uio_offset += cnt;\n    return 0;\n}\n\nint\ngpiowrite (dev, uio, flag)\n    dev_t dev;\n    struct uio *uio;\n    int flag;\n{\n    register struct iovec *iov = uio->uio_iov;\n    register u_int cnt = NPINS;\n    char buf [20];\n\n    /* I/o size should be large enough. */\n    if (iov->iov_len < cnt)\n        return EIO;\n\n    bcopy (iov->iov_base, buf, cnt);\n    iov->iov_base += cnt;\n    iov->iov_len -= cnt;\n    uio->uio_resid -= cnt;\n    uio->uio_offset += cnt;\n\n    PRINTDBG (\"gpiowrite ('%s')\\n\", buf);\n    gpio_parse (dev, buf);\n    return 0;\n}\n\n/*\n * Display a picture on LoL shield.\n * Duration in milliseconds is specified.\n */\nstatic void\ngpio_lol (msec, data)\n    u_int msec;\n    const short *data;\n{\n    /* Number of control pins for LoL Shield. */\n    #define LOL_NPINS   12\n\n    /* Number of rows on LoL Shield. */\n    #define LOL_NROW    9\n\n    /* Number of columns on LoL Shield. */\n    #define LOL_NCOL    14\n\n    /* Sequence of pins to set high during refresh cycle. */\n    static const unsigned high [LOL_NPINS] = {\n        1 << 10,        /* PB10 - labeled D13 on board (connect to A5) */\n        1 << 9,         /* PB9  - D12 (connect to A4) */\n        1 << 7,         /* PB7  - D11 (connect to A3) */\n        1 << 6,         /* PB6  - D10 (connect to A2) */\n        1 << 4,         /* PB4  - D9 (connect to A1) */\n        1 << 11,        /* PB11 - D8 */\n        0x10000 << 7,   /* PE7  - D7 */\n        0x10000 << 6,   /* PE6  - D6 */\n        0x10000 << 5,   /* PE5  - D5 */\n        0x10000 << 4,   /* PE4  - D4 */\n        0x10000 << 3,   /* PE3  - D3 */\n        0x10000 << 2,   /* PE2  - D2 */\n    };\n\n    /* Remap pixels to pin indexes. */\n    static const unsigned char lol_map [LOL_NROW*LOL_NCOL*2] =\n    {\n        0,8,0,7,0,6,0,5,0,4,0,3,0,2,0,1,0,9,9,0,0,10,10,0,0,11,11,0,\n        1,8,1,7,1,6,1,5,1,4,1,3,1,2,1,0,1,9,9,1,1,10,10,1,1,11,11,1,\n        2,8,2,7,2,6,2,5,2,4,2,3,2,1,2,0,2,9,9,2,2,10,10,2,2,11,11,2,\n        3,8,3,7,3,6,3,5,3,4,3,2,3,1,3,0,3,9,9,3,3,10,10,3,3,11,11,3,\n        4,8,4,7,4,6,4,5,4,3,4,2,4,1,4,0,4,9,9,4,4,10,10,4,4,11,11,4,\n        5,8,5,7,5,6,5,4,5,3,5,2,5,1,5,0,5,9,9,5,5,10,10,5,5,11,11,5,\n        6,8,6,7,6,5,6,4,6,3,6,2,6,1,6,0,6,9,9,6,6,10,10,6,6,11,11,6,\n        7,8,7,6,7,5,7,4,7,3,7,2,7,1,7,0,7,9,9,7,7,10,10,7,7,11,11,7,\n        8,7,8,6,8,5,8,4,8,3,8,2,8,1,8,0,8,9,9,8,8,10,10,8,8,11,11,8,\n    };\n\n    unsigned row, mask, bmask, emask;\n    const unsigned char *map;\n    unsigned low [LOL_NPINS];\n\n    /* Clear pin masks. */\n    for (row = 0; row < LOL_NPINS; row++)\n        low [row] = 0;\n\n    /* Convert image to array of pin masks. */\n    for (row = 0; row < LOL_NROW; row++) {\n        mask = *data++ & ((1 << LOL_NCOL) - 1);\n        map = &lol_map [row * LOL_NCOL * 2];\n        while (mask != 0) {\n            if (mask & 1) {\n                low [map[0]] |= high [map[1]];\n            }\n            map += 2;\n            mask >>= 1;\n        }\n    }\n    bmask = high[0] | high[1] | high[2] | high[3] | high[4] | high[5];\n    emask = (high[6] | high[7] | high[8] | high[9] | high[10] |\n         high[11]) >> 16;\n\n    /* Display the image. */\n    if (msec < 1)\n        msec = 20;\n    while (msec-- > 0) {\n        for (row = 0; row < LOL_NPINS; row++) {\n            /* Set all pins to tristate. */\n            TRISBSET = bmask;\n            TRISESET = emask;\n\n            /* Set one pin to high. */\n            mask = high [row];\n            if (row < 6) {\n                TRISBCLR = mask;\n                LATBSET = mask;\n            } else {\n                mask >>= 16;\n                TRISECLR = mask;\n                LATESET = mask;\n            }\n\n            /* Set other pins to low. */\n            mask = low [row];\n            TRISBCLR = mask;\n            LATBCLR = mask;\n            mask >>= 16;\n            TRISECLR = mask;\n            LATECLR = mask;\n\n            /* Pause to make it visible. */\n            udelay (1000 / LOL_NPINS);\n        }\n    }\n\n    /* Turn display off. */\n    TRISBSET = bmask;\n    TRISESET = emask;\n}\n\n/*\n * Commands:\n * GPIO_CONFIN  - configure as input\n * GPIO_CONFOUT - configure as output\n * GPIO_CONFOD  - configure as open drain\n * GPIO_DECONF  - deconfigure\n * GPIO_STORE   - store all outputs\n * GPIO_SET     - set to 1 by mask\n * GPIO_CLEAR   - set to 0 by mask\n * GPIO_INVERT  - invert by mask\n * GPIO_POLL    - poll\n *\n * Use GPIO_PORT(n) to set port number.\n */\nint\ngpioioctl (dev, cmd, addr, flag)\n    dev_t dev;\n    register u_int cmd;\n    caddr_t addr;\n    int flag;\n{\n    register u_int unit, mask, value;\n    register struct gpioreg *reg;\n\n    PRINTDBG (\"gpioioctl (cmd=%08x, addr=%08x, flag=%d)\\n\", cmd, addr, flag);\n    unit = cmd & 0xff;\n    cmd &= ~0xff;\n    if (cmd == GPIO_LOL) {\n        /* display 9x14 image on a lol shield  */\n        if (baduaddr (addr) || baduaddr (addr + LOL_NROW*2 - 1))\n            return EFAULT;\n        gpio_lol (unit, (const short*) addr);\n        return 0;\n    }\n\n    if ((cmd & (IOC_INOUT | IOC_VOID)) != IOC_VOID ||\n        ((cmd >> 8) & 0xff) != 'g')\n        return EINVAL;\n    if (unit >= NGPIO)\n        return ENXIO;\n\n    reg = unit + (struct gpioreg*) &TRISA;\n    mask = (u_int) addr & 0xffff;\n    if (cmd & GPIO_COMMAND & (GPIO_CONFIN | GPIO_CONFOUT | GPIO_CONFOD))\n        mask = mask;\n    else\n        mask &= gpio_confmask[unit];\n\n    if (cmd & GPIO_COMMAND & GPIO_CONFIN) {\n        /* configure as input */\n        PRINTDBG (\"TRIS%cSET %p := %04x\\n\", unit+'A', &reg->trisset, mask);\n        reg->trisset = mask;\n        gpio_confmask[unit] |= mask;\n\n        /* skip output-only bits */\n        gpio_confmask[unit] ^= mask & ~reg->tris;\n    }\n    if (cmd & GPIO_COMMAND & (GPIO_CONFOUT | GPIO_CONFOD)) {\n        if (cmd & GPIO_COMMAND & GPIO_CONFOUT) {\n            /* configure as output */\n            PRINTDBG (\"ODC%cCLR %p := %04x\\n\", unit+'A', &reg->odcclr, mask);\n            reg->odcclr = mask;\n        } else {\n            /* configure as open drain */\n            PRINTDBG (\"ODC%cSET %p := %04x\\n\", unit+'A', &reg->odcset, mask);\n            reg->odcset = mask;\n        }\n        PRINTDBG (\"TRIS%cCLR %p := %04x\\n\", unit+'A', &reg->trisclr, mask);\n        reg->trisclr = mask;\n        gpio_confmask[unit] |= mask;\n\n        /* skip input-only bits */\n        gpio_confmask[unit] ^= mask & reg->tris;\n    }\n    if (cmd & GPIO_COMMAND & GPIO_DECONF) {\n        /* deconfigure */\n        gpio_confmask[unit] &= ~mask;\n    }\n    if (cmd & GPIO_COMMAND & GPIO_STORE) {\n        /* store all outputs */\n        value = reg->lat;\n        PRINTDBG (\"LAT%c %p -> %04x\\n\", unit+'A', &reg->lat, value);\n        value &= ~gpio_confmask[unit];\n        value |= mask;\n        PRINTDBG (\"LAT%c %p := %04x\\n\", unit+'A', &reg->lat, value);\n        reg->lat = value;\n    }\n    if (cmd & GPIO_COMMAND & GPIO_SET) {\n        /* set to 1 by mask */\n        PRINTDBG (\"LAT%cSET %p := %04x\\n\", unit+'A', &reg->latset, mask);\n        reg->latset = mask;\n    }\n    if (cmd & GPIO_COMMAND & GPIO_CLEAR) {\n        /* set to 0 by mask */\n        PRINTDBG (\"LAT%cCLR %p := %04x\\n\", unit+'A', &reg->latclr, mask);\n        reg->latclr = mask;\n    }\n    if (cmd & GPIO_COMMAND & GPIO_INVERT) {\n        /* invert by mask */\n        PRINTDBG (\"LAT%cINV %p := %04x\\n\", unit+'A', &reg->latinv, mask);\n        reg->latinv = mask;\n    }\n    if (cmd & GPIO_COMMAND & GPIO_POLL) {\n        /* send current pin values to user */\n        value = reg->port;\n        PRINTDBG (\"PORT%c %p -> %04x\\n\", unit+'A', &reg->port, value);\n        u.u_rval = value;\n    }\n    return 0;\n}\n\n/*\n * Test to see if device is present.\n * Return true if found and initialized ok.\n */\nstatic int\ngpioprobe(config)\n    struct conf_device *config;\n{\n    int unit = config->dev_unit;\n    int flags = config->dev_flags;\n    char buf[20];\n\n    if (unit < 0 || unit >= NGPIO)\n        return 0;\n\n    gpio_confmask[unit] = flags;\n\n    gpio_print(unit | MINOR_CONF, buf);\n    printf(\"gpio%u: port%c, pins %s\", unit, unit + 'A', buf);\n    return 1;\n}\n\nstruct driver gpiodriver = {\n    \"gpio\", gpioprobe,\n};\n"
  },
  {
    "path": "sys/arch/pic32/dev/hx8357.c",
    "content": "/*\n * HX8357 TFT driver for PIC32.\n *\n * Copyright (C) 2014 Majenko Technologies <matt@majenko.co.uk>\n * Copyright (C) 2015 Serge Vakulenko <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/param.h>\n#include <sys/conf.h>\n#include <sys/user.h>\n#include <sys/ioctl.h>\n#include <sys/systm.h>\n#include <sys/uio.h>\n#include <sys/tty.h>\n#include <sys/config.h>\n#include <sys/gpanel.h>\n\n#define HX8357_EXIT_SLEEP_MODE              0x11\n#define HX8357_SET_DISPLAY_OFF              0x28\n#define HX8357_SET_DISPLAY_ON               0x29\n#define HX8357_SET_COLUMN_ADDRESS           0x2A\n#define HX8357_SET_PAGE_ADDRESS             0x2B\n#define HX8357_WRITE_MEMORY_START           0x2C\n#define HX8357_READ_MEMORY_START            0x2E\n#define HX8357_SET_TEAR_ON                  0x35\n#define HX8357_SET_ADDRESS_MODE             0x36\n#define HX8357_SET_PIXEL_FORMAT             0x3A\n#define HX8357_WRITE_MEMORY_CONTINUE        0x3C\n#define HX8357_READ_MEMORY_CONTINUE         0x3E\n#define HX8357_SET_INTERNAL_OSCILLATOR      0xB0\n#define HX8357_SET_POWER_CONTROL            0xB1\n#define HX8357_SET_DISPLAY_MODE             0xB4\n#define HX8357_SET_VCOM_VOLTAGE             0xB6\n#define HX8357_ENABLE_EXTENSION_COMMAND     0xB9\n#define HX8357_SET_PANEL_DRIVING            0xC0    // not documented!\n#define HX8357_SET_PANEL_CHARACTERISTIC     0xCC\n#define HX8357_SET_GAMMA_CURVE              0xE0\n\n/*\n * Display size.\n */\nstatic int _width, _height;\n\n/*\n * Cursor position for text output.\n */\nstatic int _col, _row;\n\nstatic void writeCommand(int c)\n{\n    while (PMMODE & PIC32_PMMODE_BUSY);\n    PMADDR = 0x0000;\n    PMDIN = c;\n}\n\nstatic void writeData(int c)\n{\n    while (PMMODE & PIC32_PMMODE_BUSY);\n    PMADDR = 0x0001;\n    PMDIN = c;\n}\n\nstatic inline void initDisplay()\n{\n    PMCONCLR = PIC32_PMCON_ON;\n    udelay(1);\n\n    PMCONSET = PIC32_PMCON_PTWREN | PIC32_PMCON_PTRDEN;\n    PMCONCLR = PIC32_PMCON_CSF;\n    PMAEN = 0x0001;             // Enable PMA0 pin for RS pin and CS1 as CS\n    PMMODE = PIC32_PMMODE_MODE16 | PIC32_PMMODE_MODE_MAST2;\n    PMADDR = 0;\n    PMCONSET = PIC32_PMCON_ON;\n\n    writeCommand(HX8357_EXIT_SLEEP_MODE);   //Sleep Out\n    udelay(150000);\n    writeCommand(HX8357_ENABLE_EXTENSION_COMMAND);\n    writeData(0xFF);\n    writeData(0x83);\n    writeData(0x57);\n    udelay(1000);\n    writeCommand(HX8357_SET_POWER_CONTROL);\n    writeData(0x00);\n    writeData(0x12);\n    writeData(0x12);\n    writeData(0x12);\n    writeData(0xC3);\n    writeData(0x44);\n    udelay(1000);\n    writeCommand(HX8357_SET_DISPLAY_MODE);\n    writeData(0x02);\n    writeData(0x40);\n    writeData(0x00);\n    writeData(0x2A);\n    writeData(0x2A);\n    writeData(0x20);\n    writeData(0x91);\n    udelay(1000);\n    writeCommand(HX8357_SET_VCOM_VOLTAGE);\n    writeData(0x38);\n    udelay(1000);\n    writeCommand(HX8357_SET_INTERNAL_OSCILLATOR);\n    writeData(0x68);\n    writeCommand(0xE3);                     //Unknown Command\n    writeData(0x2F);\n    writeData(0x1F);\n    writeCommand(0xB5);                     //Set BGP\n    writeData(0x01);\n    writeData(0x01);\n    writeData(0x67);\n    writeCommand(HX8357_SET_PANEL_DRIVING);\n    writeData(0x70);\n    writeData(0x70);\n    writeData(0x01);\n    writeData(0x3C);\n    writeData(0xC8);\n    writeData(0x08);\n    udelay(1000);\n    writeCommand(0xC2);                     // Set Gate EQ\n    writeData(0x00);\n    writeData(0x08);\n    writeData(0x04);\n    udelay(1000);\n    writeCommand(HX8357_SET_PANEL_CHARACTERISTIC);\n    writeData(0x09);\n    udelay(1000);\n    writeCommand(HX8357_SET_GAMMA_CURVE);\n    writeData(0x01);\n    writeData(0x02);\n    writeData(0x03);\n    writeData(0x05);\n    writeData(0x0E);\n    writeData(0x22);\n    writeData(0x32);\n    writeData(0x3B);\n    writeData(0x5C);\n    writeData(0x54);\n    writeData(0x4C);\n    writeData(0x41);\n    writeData(0x3D);\n    writeData(0x37);\n    writeData(0x31);\n    writeData(0x21);\n    writeData(0x01);\n    writeData(0x02);\n    writeData(0x03);\n    writeData(0x05);\n    writeData(0x0E);\n    writeData(0x22);\n    writeData(0x32);\n    writeData(0x3B);\n    writeData(0x5C);\n    writeData(0x54);\n    writeData(0x4C);\n    writeData(0x41);\n    writeData(0x3D);\n    writeData(0x37);\n    writeData(0x31);\n    writeData(0x21);\n    writeData(0x00);\n    writeData(0x01);\n    udelay(1000);\n    writeCommand(HX8357_SET_PIXEL_FORMAT);  //COLMOD RGB888\n    writeData(0x55);\n    writeCommand(HX8357_SET_ADDRESS_MODE);\n    writeData(0x00);\n    writeCommand(HX8357_SET_TEAR_ON);       //TE ON\n    writeData(0x00);\n    udelay(10000);\n    writeCommand(HX8357_SET_DISPLAY_ON);    //Display On\n    udelay(10000);\n    writeCommand(HX8357_WRITE_MEMORY_START); //Write SRAM Data\n}\n\nstatic void setAddrWindow(int x0, int y0, int x1, int y1)\n{\n    writeCommand(HX8357_SET_COLUMN_ADDRESS); // Column addr set\n    writeData(x0 >> 8);\n    writeData(x0);                          // XSTART\n    writeData(x1 >> 8);\n    writeData(x1);                          // XEND\n\n    writeCommand(HX8357_SET_PAGE_ADDRESS);  // Row addr set\n    writeData(y0 >> 8);\n    writeData(y0);                          // YSTART\n    writeData(y1 >> 8);\n    writeData(y1);                          // YEND\n\n    writeCommand(HX8357_WRITE_MEMORY_START); //Write SRAM Data\n}\n\nstatic void setRotation(int rotation)\n{\n    writeCommand(HX8357_SET_ADDRESS_MODE);\n    switch (rotation & 3) {\n    case 0:                     /* Portrait */\n        writeData(0x0000);\n        _width  = 320;\n        _height = 480;\n        break;\n    case 1:                     /* Landscape */\n        writeData(0x0060);\n        _width  = 480;\n        _height = 320;\n        break;\n    case 2:                     /* Upside down portrait */\n        writeData(0x00C0);\n        _width  = 320;\n        _height = 480;\n        break;\n    case 3:                     /* Upside down landscape */\n        writeData(0x00A0);\n        _width  = 480;\n        _height = 320;\n        break;\n    }\n}\n\n/*\n * Draw a pixel.\n */\nstatic void setPixel(int x, int y, int color)\n{\n    if (x < 0 || x >= _width || y < 0 || y >= _height)\n        return;\n    setAddrWindow(x, y, x+1, y+1);\n    while (PMMODE & PIC32_PMMODE_BUSY);\n    PMADDR = 0x0001;\n    PMDIN = color;\n}\n\n/*\n * Fill a rectangle with specified color.\n */\nstatic void fillRectangle(int x0, int y0, int x1, int y1, int color)\n{\n    int x, y;\n\n    if (x0 < 0) x0 = 0;\n    if (y0 < 0) x0 = 0;\n    if (x1 < 0) x1 = 0;\n    if (y1 < 0) x1 = 0;\n    if (x0 >= _width) x0 = _width-1;\n    if (x1 >= _width) x1 = _width-1;\n    if (y0 >= _height) y0 = _height-1;\n    if (y1 >= _height) y1 = _height-1;\n\n    if (x1 < x0) {\n        int t = x0;\n        x0 = x1;\n        x1 = t;\n    }\n    if (y1 < y0) {\n        int t = y0;\n        y0 = y1;\n        y1 = t;\n    }\n    setAddrWindow(x0, y0, x1, y1);\n\n    while (PMMODE & PIC32_PMMODE_BUSY);\n    PMADDR = 0x0001;\n    for (y=y0; y<=y1; y++) {\n        for (x=x0; x<=x1; x++) {\n            while (PMMODE & PIC32_PMMODE_BUSY);\n            PMDIN = color;\n        }\n    }\n}\n\n/*\n * Fill a rectangle with user data.\n */\nstatic void drawImage(int x, int y, int width, int height,\n    const unsigned short *data)\n{\n    unsigned cnt = width * height;\n\n    setAddrWindow(x, y, x + width - 1, y + height - 1);\n    while (PMMODE & PIC32_PMMODE_BUSY);\n    PMADDR = 0x0001;\n    while (cnt--) {\n        while (PMMODE & PIC32_PMMODE_BUSY);\n        PMDIN = *data++;\n    }\n}\n\n/*\n * Draw a line.\n */\nstatic void drawLine(int x0, int y0, int x1, int y1, int color)\n{\n    int dx, dy, stepx, stepy, fraction;\n\n    if (x0 == x1 || y0 == y1) {\n        fillRectangle(x0, y0, x1, y1, color);\n        return;\n    }\n\n    /* Use Bresenham's line algorithm. */\n    dy = y1 - y0;\n    if (dy < 0) {\n        dy = -dy;\n        stepy = -1;\n    } else {\n        stepy = 1;\n    }\n    dx = x1 - x0;\n    if (dx < 0) {\n        dx = -dx;\n        stepx = -1;\n    } else {\n        stepx = 1;\n    }\n    dy <<= 1;                           /* dy is now 2*dy */\n    dx <<= 1;                           /* dx is now 2*dx */\n    setPixel(x0, y0, color);\n    if (dx > dy) {\n        fraction = dy - (dx >> 1);      /* same as 2*dy - dx */\n        while (x0 != x1) {\n            if (fraction >= 0) {\n                y0 += stepy;\n                fraction -= dx;         /* same as fraction -= 2*dx */\n            }\n            x0 += stepx;\n            fraction += dy;             /* same as fraction -= 2*dy */\n            setPixel(x0, y0, color);\n        }\n    } else {\n        fraction = dx - (dy >> 1);\n        while (y0 != y1) {\n            if (fraction >= 0) {\n                x0 += stepx;\n                fraction -= dy;\n            }\n            y0 += stepy;\n            fraction += dx;\n            setPixel(x0, y0, color);\n        }\n    }\n}\n\n/*\n * Draw a rectangular frame.\n */\nstatic void drawFrame(int x0, int y0, int x1, int y1, int color)\n{\n    fillRectangle(x0, y0, x1, y0, color);\n    fillRectangle(x0, y1, x1, y1, color);\n    fillRectangle(x0, y0, x0, y1, color);\n    fillRectangle(x1, y0, x1, y1, color);\n}\n\n/*\n * Draw a circle.\n */\nstatic void drawCircle(int x0, int y0, int radius, int color)\n{\n    int f = 1 - radius;\n    int ddF_x = 0;\n    int ddF_y = -2 * radius;\n    int x = 0;\n    int y = radius;\n\n    setPixel(x0, y0 + radius, color);\n    setPixel(x0, y0 - radius, color);\n    setPixel(x0 + radius, y0, color);\n    setPixel(x0 - radius, y0, color);\n    while (x < y) {\n        if (f >= 0) {\n            y--;\n            ddF_y += 2;\n            f += ddF_y;\n        }\n        x++;\n        ddF_x += 2;\n        f += ddF_x + 1;\n        setPixel(x0 + x, y0 + y, color);\n        setPixel(x0 - x, y0 + y, color);\n        setPixel(x0 + x, y0 - y, color);\n        setPixel(x0 - x, y0 - y, color);\n        setPixel(x0 + y, y0 + x, color);\n        setPixel(x0 - y, y0 + x, color);\n        setPixel(x0 + y, y0 - x, color);\n        setPixel(x0 - y, y0 - x, color);\n    }\n}\n\n/*\n * Start a new line: increase row.\n */\nstatic void newLine(const struct gpanel_font_t *font)\n{\n    _col = 0;\n    _row += font->height;\n    if (_row > _height - font->height)\n        _row = 0;\n}\n\n/*\n * Draw a glyph of one symbol.\n */\nvoid drawGlyph(const struct gpanel_font_t *font,\n    int color, int background, int width, const unsigned short *bits)\n{\n    int h, w;\n    unsigned bitmask = 0;\n\n    if (background >= 0) {\n        /*\n         * Clear background.\n         */\n        setAddrWindow(_col, _row, _col + width - 1, _row + font->height - 1);\n        while (PMMODE & PIC32_PMMODE_BUSY);\n        PMADDR = 0x0001;\n\n        /* Loop on each glyph row. */\n        for (h=0; h<font->height; h++) {\n            /* Loop on every pixel in the row (left to right). */\n            for (w=0; w<width; w++) {\n                if ((w & 15) == 0)\n                    bitmask = *bits++;\n                else\n                    bitmask <<= 1;\n\n                while (PMMODE & PIC32_PMMODE_BUSY)\n                    ;\n                if (bitmask & 0x8000)\n                    PMDIN = color;\n                else\n                    PMDIN = background;\n            }\n        }\n    } else {\n        /*\n         * Transparent background.\n         */\n        /* Loop on each glyph row. */\n        for (h=0; h<font->height; h++) {\n            /* Loop on every pixel in the row (left to right). */\n            for (w=0; w<width; w++) {\n                if ((w & 15) == 0)\n                    bitmask = *bits++;\n                else\n                    bitmask <<= 1;\n\n                if (bitmask & 0x8000)\n                    setPixel(_col + w, _row + h, color);\n            }\n        }\n    }\n}\n\n/*\n * Draw a character from a specified font.\n */\nstatic void drawChar(const struct gpanel_font_t *font,\n    int color, int background, int sym)\n{\n    unsigned cindex, width;\n    const unsigned short *bits;\n\n    switch (sym) {\n    case '\\n':      /* goto next line */\n        newLine(font);\n        return;\n    case '\\r':      /* carriage return - go to begin of line */\n        _col = 0;\n        return;\n    case '\\t':      /* tab replaced by space */\n        sym = ' ';\n        break;\n    }\n\n    if (sym < font->firstchar || sym >= font->firstchar + font->size)\n        sym = font->defaultchar;\n    cindex = sym - font->firstchar;\n\n    /* Get font bitmap depending on fixed pitch or not. */\n    if (font->width) {\n        /* Proportional font. */\n        width = font->width[cindex];\n    } else {\n        /* Fixed width font. */\n        width = font->maxwidth;\n    }\n    if (font->offset) {\n        bits = font->bits + font->offset[cindex];\n    } else {\n        bits = font->bits + cindex * font->height;\n    }\n\n    /* Scrolling. */\n    if (_col > _width - width) {\n        newLine(font);\n    }\n\n    /* Draw a character. */\n    drawGlyph(font, color, background, width, bits);\n    _col += width;\n}\n\n/*\n * Draw a string of characters.\n * TODO: Decode UTF-8.\n */\nstatic void drawText(const struct gpanel_font_t *font,\n    int color, int background, int x, int y, const char *text)\n{\n    int sym;\n\n    _col = x;\n    _row = y;\n    for (;;) {\n        sym = *text++;\n        if (! sym)\n            break;\n\n        drawChar(font, color, background, sym);\n    }\n}\n\nint gpanel_open(dev_t dev, int flag, int mode)\n{\n    if (minor(dev) != 0)\n        return ENODEV;\n    return 0;\n}\n\nint gpanel_close(dev_t dev, int flag, int mode)\n{\n    return 0;\n}\n\nint gpanel_read(dev_t dev, struct uio *uio, int flag)\n{\n    return ENODEV;\n}\n\nint gpanel_write(dev_t dev, struct uio *uio, int flag)\n{\n    return ENODEV;\n}\n\n/*\n * TODO: check whether user pointers are valid.\n */\nint gpanel_ioctl(dev_t dev, register u_int cmd, caddr_t addr, int flag)\n{\n    switch (cmd) {\n        /*\n         * Clear the whole screen with a given color.\n         */\n        case GPANEL_CLEAR: {\n            struct gpanel_clear_t *param = (struct gpanel_clear_t*) addr;\n\n            if (param->xsize != _width || param->ysize != _height) {\n                /* Change the screen orientation. */\n                if (param->xsize > param->ysize) {\n                    /* Landscape */\n                    setRotation(1);\n                } else if (param->xsize < param->ysize) {\n                    /* Portrait */\n                    setRotation(0);\n                }\n            }\n            fillRectangle(0, 0, _width, _height, param->color);\n            param->xsize = _width;\n            param->ysize = _height;\n            break;\n        }\n\n        /*\n         * Draw a single pixel.\n         */\n        case GPANEL_PIXEL: {\n            struct gpanel_pixel_t *param = (struct gpanel_pixel_t*) addr;\n\n            setPixel(param->x, param->y, param->color);\n            break;\n        }\n\n        /*\n         * Draw a line.\n         */\n        case GPANEL_LINE: {\n            struct gpanel_line_t *param = (struct gpanel_line_t*) addr;\n\n            drawLine(param->x0, param->y0, param->x1, param->y1, param->color);\n            break;\n        }\n\n        /*\n         * Draw a rectangle frame.\n         */\n        case GPANEL_RECT: {\n            struct gpanel_rect_t *param = (struct gpanel_rect_t*) addr;\n\n            drawFrame(param->x0, param->y0, param->x1, param->y1, param->color);\n            break;\n        }\n\n        /*\n         * Fill a rectangle with color.\n         */\n        case GPANEL_FILL: {\n            struct gpanel_rect_t *param = (struct gpanel_rect_t*) addr;\n\n            fillRectangle(param->x0, param->y0, param->x1, param->y1, param->color);\n            break;\n        }\n\n        /*\n         * Draw a circle.\n         */\n        case GPANEL_CIRCLE: {\n            struct gpanel_circle_t *param = (struct gpanel_circle_t*) addr;\n\n            drawCircle(param->x, param->y, param->radius, param->color);\n            break;\n        }\n\n        /*\n         * Fill a rectangular area with the user-supplied data.\n         */\n        case GPANEL_IMAGE: {\n            struct gpanel_image_t *param = (struct gpanel_image_t*) addr;\n\n            drawImage(param->x, param->y, param->width, param->height,\n                param->image);\n            break;\n        }\n\n        /*\n         * Draw a character.\n         */\n        case GPANEL_CHAR: {\n            struct gpanel_char_t *param = (struct gpanel_char_t*) addr;\n\n            _col = param->x;\n            _row = param->y;\n            drawChar(param->font, param->color, param->background, param->sym);\n            break;\n        }\n\n        /*\n         * Draw a string of characters.\n         */\n        case GPANEL_TEXT: {\n            struct gpanel_text_t *param = (struct gpanel_text_t*) addr;\n\n            drawText(param->font, param->color, param->background,\n                param->x, param->y, param->text);\n            break;\n        }\n    }\n    return 0;\n}\n\n/*\n * Test to see if device is present.\n * Return true if found and initialized ok.\n */\nstatic int\nhxtftprobe(config)\n    struct conf_device *config;\n{\n    initDisplay();\n    setRotation(1);\n    printf(\"hxtft0: display %ux%u\\n\", _width, _height);\n    return 1;\n}\n\nstruct driver hxtftdriver = {\n    \"hxtft\", hxtftprobe,\n};\n"
  },
  {
    "path": "sys/arch/pic32/dev/ili9341.h",
    "content": "/*\n * ILI9341 registers.\n */\n#define ILI9341_No_Operation                                0x00\n#define ILI9341_Software_Reset                              0x01\n#define ILI9341_Read_Display_Identification_Information     0x04\n#define ILI9341_Read_Display_Status                         0x09\n#define ILI9341_Read_Display_Power_Mode                     0x0A\n#define ILI9341_Read_Display_MADCTL                         0x0B\n#define ILI9341_Read_Display_Pixel_Format                   0x0C\n#define ILI9341_Read_Display_Image_Format                   0x0D\n#define ILI9341_Read_Display_Signal_Mode                    0x0E\n#define ILI9341_Read_Display_Self_Diagnostic_Result         0x0F\n#define ILI9341_Enter_Sleep_Mode                            0x10\n#define ILI9341_Sleep_OUT                                   0x11\n#define ILI9341_Partial_Mode_ON                             0x12\n#define ILI9341_Normal_Display_Mode_ON                      0x13\n#define ILI9341_Display_Inversion_OFF                       0x20\n#define ILI9341_Display_Inversion_ON                        0x21\n#define ILI9341_Gamma_Set                                   0x26\n#define ILI9341_Display_OFF                                 0x28\n#define ILI9341_Display_ON                                  0x29\n#define ILI9341_Column_Address_Set                          0x2A\n#define ILI9341_Page_Address_Set                            0x2B\n#define ILI9341_Memory_Write                                0x2C\n#define ILI9341_Color_SET                                   0x2D\n#define ILI9341_Memory_Read                                 0x2E\n#define ILI9341_Partial_Area                                0x30\n#define ILI9341_Vertical_Scrolling_Definition               0x33\n#define ILI9341_Tearing_Effect_Line_OFF                     0x34\n#define ILI9341_Tearing_Effect_Line_ON                      0x35\n#define ILI9341_Memory_Access_Control                       0x36\n#define ILI9341_Vertical_Scrolling_Start_Address            0x37\n#define ILI9341_Idle_Mode_OFF                               0x38\n#define ILI9341_Idle_Mode_ON                                0x39\n#define ILI9341_Pixel_Format_Set                            0x3A\n#define ILI9341_Write_Memory_Continue                       0x3C\n#define ILI9341_Read_Memory_Continue                        0x3E\n#define ILI9341_Set_Tear_Scanline                           0x44\n#define ILI9341_Get_Scanline                                0x45\n#define ILI9341_Write_Display_Brightness                    0x51\n#define ILI9341_Read_Display_Brightness                     0x52\n#define ILI9341_Write_CTRL_Display                          0x53\n#define ILI9341_Read_CTRL_Display                           0x54\n#define ILI9341_Write_Content_Adaptive_Brightness_Control   0x55\n#define ILI9341_Read_Content_Adaptive_Brightness_Control    0x56\n#define ILI9341_Write_CABC_Minimum_Brightness               0x5E\n#define ILI9341_Read_CABC_Minimum_Brightness                0x5F\n#define ILI9341_Read_ID1                                    0xDA\n#define ILI9341_Read_ID2                                    0xDB\n#define ILI9341_Read_ID3                                    0xDC\n#define ILI9341_RGB_Interface_Signal_Control                0xB0\n#define ILI9341_Frame_Control_In_Normal_Mode                0xB1\n#define ILI9341_Frame_Control_In_Idle_Mode                  0xB2\n#define ILI9341_Frame_Control_In_Partial_Mode               0xB3\n#define ILI9341_Display_Inversion_Control                   0xB4\n#define ILI9341_Blanking_Porch_Control                      0xB5\n#define ILI9341_Display_Function_Control                    0xB6\n#define ILI9341_Entry_Mode_Set                              0xB7\n#define ILI9341_Backlight_Control_1                         0xB8\n#define ILI9341_Backlight_Control_2                         0xB9\n#define ILI9341_Backlight_Control_3                         0xBA\n#define ILI9341_Backlight_Control_4                         0xBB\n#define ILI9341_Backlight_Control_5                         0xBC\n#define ILI9341_Backlight_Control_7                         0xBE\n#define ILI9341_Backlight_Control_8                         0xBF\n#define ILI9341_Power_Control_1                             0xC0\n#define ILI9341_Power_Control_2                             0xC1\n#define ILI9341_VCOM_Control_1                              0xC5\n#define ILI9341_VCOM_Control_2                              0xC7\n#define ILI9341_NV_Memory_Write                             0xD0\n#define ILI9341_NV_Memory_Protection_Key                    0xD1\n#define ILI9341_NV_Memory_Status_Read                       0xD2\n#define ILI9341_Read_ID4                                    0xD3\n#define ILI9341_Positive_Gamma_Correction                   0xE0\n#define ILI9341_Negative_Gamma_Correction                   0xE1\n#define ILI9341_Digital_Gamma_Control_1                     0xE2\n#define ILI9341_Digital_Gamma_Control_2                     0xE3\n#define ILI9341_Interface_Control                           0xF6\n\n/*\n * Memory Access Control register\n */\n#define MADCTL_MY           0x80    /* Row address order */\n#define MADCTL_MX           0x40    /* Column address order */\n#define MADCTL_MV           0x20    /* Row/column exchange */\n#define MADCTL_ML           0x10    /* Vertical refresh order */\n#define MADCTL_BGR          0x08    /* Color filter selector: 0=RGB, 1=BGR */\n#define MADCTL_MH           0x04    /* Horisontal refresh direction: 1=left-to-right */\n"
  },
  {
    "path": "sys/arch/pic32/dev/kbd.c",
    "content": "/*\n *\n * RetroBSD - PS2 keyboard driver for the Maximite PIC32 board\n *\n * Copyright (C) 2011 Rob Judd <judd@ob-wan.com>\n * All rights reserved.  The three clause (\"New\" or \"Modified\")\n * Berkeley software License Agreement specifies the terms and\n * conditions for redistribution.\n *\n */\n\n/*\n../kbd.c: In function 'initKBD':\n../kbd.c:155:8: error: request for member 'ON' in something not a structure or union\n../kbd.c:156:8: error: request for member 'CNPUE15' in something not a structure or union\n../kbd.c:157:8: error: request for member 'CNPUE16' in something not a structure or union\n../kbd.c: In function 'readKBD':\n../kbd.c:173:9: error: request for member 'RD7' in something not a structure or union\n../kbd.c:174:9: error: request for member 'RD6' in something not a structure or union\n *\n * This driver uses a 20uS timer, probably too fast\n */\n\n#include <sys/types.h>\n\n#include <machine/io.h>\n\n#include <pic32/dev/kbd.h>\n\n//#define TRACE   printf\n#ifndef TRACE\n#define TRACE(...)\n#endif\n\n// I2C registers\nstruct kbdreg {\n    //\n};\n\n#define USASCII         1\n//#define RUSSIAN         1\n\n#define true  1\n#define false 0\n#define PS2CLOCK        1//PORTD.RD6\n#define PS2DATA         2//PORTD.RD7\n#define QUEUE_SIZE      256\n\nextern volatile char in_queue[QUEUE_SIZE];\nextern volatile int in_queue_head, in_queue_tail;\nvolatile int abort;\n\n#define POLL            20*(CPU_KHZ/1000)   // # clock cycles for 20uS between keyboard reads\n#define TIMEOUT         500*(CPU_KHZ/1000)  // # clock cycles for 500uS timeout\n\nenum {PS2START, PS2BIT, PS2PARITY, PS2STOP};\n\n// Keyboard state machine and buffer\nint state;\nunsigned char key_buff;\nint key_state, key_count, key_parity, key_timer;\n\n// IBM keyboard scancode set 2 - Special Keys\n#define F1      0x0e\n#define F2      0x0f\n#define F3      0x10\n#define F4      0x11\n#define F5      0x12\n#define F6      0x13\n#define F7      0x14                        // maps to F5\n#define F8      0x15\n#define F9      0x16\n#define F10     0x17\n#define F11     0x18\n#define F12     0x19\n\n#define NUM     0x00\n#define BKSP    0x08\n#define TAB     0x09\n#define L_ALT   0x11\n#define L_SHF   0x12\n#define L_CTL   0x14\n#define CAPS    0x58\n#define R_SHF   0x59\n#define ENTER   0x0d\n#define ESC     0x1b\n#define SCRL    0x7e\n\n#ifdef USASCII\n//\n// Map of standard keyboard, US ASCII layout\n//\nconst char lowerKey[128]={\n    0,    F9,     0,    F5,    F3,    F1,    F2,   F12,     //00\n    0,   F10,    F8,    F6,    F4,   TAB,   '`',     0,     //08\n    0,     0, L_SHF,     0, L_CTL,   'q',   '1',     0,     //10\n    0,     0,   'z',   's',   'a',   'w',   '2',     0,     //18\n    0,   'c',   'x',   'd',   'e',   '4',   '3',     0,     //20\n    0,   ' ',   'v',   'f',   't',   'r',   '5',     0,     //28\n    0,   'n',   'b',   'h',   'g',   'y',   '6',     0,     //30\n    0,     0,   'm',   'j',   'u',   '7',   '8',     0,     //38\n    0,   ',',   'k',   'i',   'o',   '0',   '9',     0,     //40\n    0,   '.',   '/',   'l',   ';',   'p',   '-',     0,     //48\n    0,     0,  '\\'',     0,   '[',   '=',     0,     0,     //50\n CAPS, R_SHF, ENTER,   ']',     0,  '\\\\',     0,     0,     //58\n    0,     0,     0,     0,     0,     0,   BKSP,    0,     //60\n    0,   '1',     0,   '4',   '7',     0,     0,     0,     //68\n  '0',   '.',   '2',   '5',   '6',   '8',   ESC,   NUM,     //70\n  F11,   '+',   '3',   '-',   '*',   '9',     0,     0      //78\n};\n\nconst char upperKey[128] = {\n    0,    F9,     0,    F5,    F3,    F1,    F2,   F12,     //00\n    0,   F10,    F8,    F6,    F4,   TAB,   '~',     0,     //08\n    0,     0, L_SHF,     0, L_CTL,   'Q',   '!',     0,     //10\n    0,     0,   'Z',   'S',   'A',   'W',   '@',     0,     //18\n    0,   'C',   'X',   'D',   'E',   '$',   '#',     0,     //20\n    0,   ' ',   'V',   'F',   'T',   'R',   '%',     0,     //28\n    0,   'N',   'B',   'H',   'G',   'Y',   '^',     0,     //30\n    0,     0,   'M',   'J',   'U',   '&',   '*',     0,     //38\n    0,   '<',   'K',   'I',   'O',   ')',   '(',     0,     //40\n    0,   '>',   '?',   'L',   ':',   'P',   '_',     0,     //48\n    0,     0,  '\\\"',     0,   '{',   '+',     0,     0,     //50\n CAPS, R_SHF, ENTER,   '}',     0,   '|',     0,     0,     //58\n    0,     0,     0,     0,     0,     0,   BKSP,    0,     //60\n    0,   '1',     0,   '4',   '7',     0,     0,     0,     //68\n  '0',   '.',   '2',   '5',   '6',   '8',   ESC,   NUM,     //70\n  F11,   '+',   '3',   '-',   '*',   '9',     0,     0      //78\n};\n#elif defined RUSSIAN\n//\n// Map of standard keyboard, Russian Windows layout\n//\nconst char lowerKey[128]={\n    0,    F9,     0,    F5,    F3,    F1,    F2,   F12,     //00\n    0,   F10,    F8,    F6,    F4,   TAB,   'ё',     0,     //08\n    0,     0, L_SHF,     0, L_CTL,   'й',   '1',     0,     //10\n    0,     0,   'я',   'ы',   'ф',   'ц',   '2',     0,     //18\n    0,   'с',   'ч',   'в',   'у',   '4',   '3',     0,     //20\n    0,   ' ',   'м',   'а',   'е',   'к',   '5',     0,     //28\n    0,   'т',   'и',   'р',   'п',   'н',   '6',     0,     //30\n    0,     0,   'ь',   'о',   'г',   '7',   '8',     0,     //38\n    0,   'б',   'л',   'ш',   'щ',   '0',   '9',     0,     //40\n    0,   'ю',   '.',   'д',   'ж',   'з',   '-',     0,     //48\n    0,     0,   'э',     0,   'х',   '=',     0,     0,     //50\n CAPS, R_SHF, ENTER,   'ъ',     0,  '\\\\',     0,     0,     //58\n    0,     0,     0,     0,     0,     0,  BKSP,     0,     //60\n    0,   '1',     0,   '4',   '7',     0,     0,     0,     //68\n  '0',   ',',   '2',   '5',   '6',   '8',   ESC,   NUM,     //70\n  F11,   '+',   '3',   '-',   '*',   '9',     0,     0      //78\n};\n\nconst char upperKey[128] = {\n    0,    F9,     0,    F5,    F3,    F1,    F2,   F12,     //00\n    0,   F10,    F8,    F6,    F4,   TAB,   'Ё',     0,     //08\n    0,     0, L_SHF,     0, L_CTL,   'Й',   '!',     0,     //10\n    0,     0,   'Я',   'Ы',   'Ф',   'Ц',  '\\\"',     0,     //18\n    0,   'С',   'Ч',   'В',   'У',   ';',   '№',     0,     //20\n    0,   ' ',   'М',   'А',   'Е',   'К',   '%',     0,     //28\n    0,   'Т',   'И',   'Р',   'П',   'Н',   ':',     0,     //30\n    0,     0,   'Ь',   'О',   'Г',   '?',   '*',     0,     //38\n    0,   'Б',   'Л',   'Ш',   'Щ',   ')',   '(',     0,     //40\n    0,   'Ю',   ',',   'Д',   'Ж',   'З',   '_',     0,     //48\n    0,     0,   'Э',     0,   'Х',   '+',     0,     0,     //50\n CAPS, R_SHF, ENTER,   'Ъ',     0,   '/',     0,     0,     //58\n    0,     0,     0,     0,     0,     0,   BKSP,    0,     //60\n    0,   '1',     0,   '4',   '7',     0,     0,     0,     //68\n  '0',   ',',   '2',   '5',   '6',   '8',   ESC,   NUM,     //70\n  F11,   '+',   '3',   '-',   '*',   '9',     0,     0      //78\n};\n#endif\n\n/*\n    Standard PC init sequence:\n\n    Keyboard: AA  Self-test passed                ;Keyboard controller init\n    Host:     ED  Set/Reset Status Indicators\n    Keyboard: FA  Acknowledge\n    Host:     00  Turn off all LEDs\n    Keyboard: FA  Acknowledge\n    Host:     F2  Read ID\n    Keyboard: FA  Acknowledge\n    Keyboard: AB  First byte of ID\n    Host:     ED  Set/Reset Status Indicators     ;BIOS init\n    Keyboard: FA  Acknowledge\n    Host:     02  Turn on Num Lock LED\n    Keyboard: FA  Acknowledge\n    Host:     F3  Set Typematic Rate/Delay        ;Windows init\n    Keyboard: FA  Acknowledge\n    Host:     20  500 ms / 30.0 reports/sec\n    Keyboard: FA  Acknowledge\n    Host:     F4  Enable\n    Keyboard: FA  Acknowledge\n    Host:     F3  Set Typematic Rate/delay\n    Keyboard: FA  Acknowledge\n    Host:     00  250 ms / 30.0 reports/sec\n    Keyboard: FA  Acknowledge\n*/\n\nchar init_kbd(void)\n{\n\t// enable pullups on the clock and data lines.\n\t// This stops them from floating and generating random chars when no keyboard is attached\n// \tCNCON.ON = 1;                           // turn on Change Notice for interrupt\n// \tCNPUE.CNPUE15 = 1;                      // turn on the pullup for pin D6 also called CN15\n// \tCNPUE.CNPUE16 = 1;                      // turn on the pullup for pin D7 also called CN16\n\n \treturn false;\n}\n\nvoid read_kbd(void)\n{\n    int data = PS2DATA;\n    int clock = PS2CLOCK;\n    static char key_up = false;\n    static unsigned char code = 0;\n    static unsigned then = 0;\n    unsigned now = mips_read_c0_register (C0_COUNT, 0);\n\n    // Is it time to poll the keyboard yet?\n    if ((int) (now - then) < POLL)\n        return;\n\telse\n    \tthen = now;\n\n    if (key_state) {                                            // if clock was high, key_state = 1\n        if (!clock) {                                           // PS2CLOCK == 0, falling edge detected\n            key_state = 0;                                      // transition to state 0\n            key_timer = TIMEOUT;                                // restart the counter\n\n            switch(state){\n            default:\n            case PS2START:\n                if(!data) {                                     // PS2DATA == 0\n                    key_count = 8;                              // init bit counter\n                    key_parity = 0;                             // init parity check\n                    code = 0;\n                    state = PS2BIT;\n                }\n                break;\n\n            case PS2BIT:\n                code >>= 1;                                     // shift in data bit\n                if(data)                                        // PS2DATA == 1\n                    code |= 0x80;\n                key_parity ^= code;\n                if (--key_count == 0)\n                    state = PS2PARITY;                          // all bits read\n                break;\n\n            case PS2PARITY:\n                if(data)\n                    key_parity ^= 0x80;\n                if(key_parity & 0x80)                           // parity odd, continue\n                    state = PS2STOP;\n                else\n                    state = PS2START;\n                break;\n\n            case PS2STOP:\n                if(data) {\n                    if(code == 0xf0)\n                    \t key_up = true;\n                    else {\n\n                        char chr;\n                        static char LShift = 0;\n                        static char RShift = 0;\n                        static char LCtrl = 0;\n                        static char LAlt = 0;\n                        static char CapsLock = 0;\n\n                        if(key_up) {                            // check for special key release\n                            key_up = false;\n                            switch(code) {\n                                case L_SHF: LShift = 0;\n                                case R_SHF: RShift = 0;\n                                case L_CTL: LCtrl = 0;\n                                case L_ALT: LAlt = 0;\n                            }\n                            goto exit;\n                        } else {                                // check for special key press\n                            switch(code) {\n                                case L_SHF: LShift = 1;\n                                case R_SHF: RShift = 1;\n                                case L_CTL: LCtrl = 1;\n                                case L_ALT: LAlt = 1;\n                                case CAPS:  CapsLock = !CapsLock;\n                                default: break;\n                            goto exit;\n                            }\n                        }\n\n                        if(LShift || RShift)                        // get the ASCII code\n                            chr = lowerKey[code%128];\n                        else\n                            chr = upperKey[code%128];\n\n                        if(!chr)                                    // it was an unmapped key\n                            break;\n\n                        if(CapsLock && chr >= 'a' && chr <= 'z')    // check for altered keys\n                            chr -= 32;\n                        if(LCtrl)\n                            chr &= 0x1F;\n\n                        in_queue[in_queue_head] = chr;\n                        in_queue_head = (in_queue_head + 1) % QUEUE_SIZE;\n\n                        if(chr == 3) {                              // check for CTL-C\n                            in_queue_head = in_queue_tail = 0;\n                            abort = true;\n                        }\n\n//\t\t\tPrintSignonToUSB = false;                   // show that the keyboard is in use\n\n                        LAlt = LAlt;                                // not used yet\n                    } // if key_up\nexit:\n                code = 0;\n                } // if(data)\n                state = PS2START;\n\n            } // switch(state)\n\n        } // if(!clock)\n\n    } else // if(key_state)\n        key_state = 1;                                          // PS2CLOCK == 1, rising edge detected\n\n    if ((key_timer -= POLL) <= 0)\n        state = PS2START;                                       // timeout, reset state machine\n\n    return;\n}\n\nchar write_kbd(u_char data)\n{\n\n    // do something here\n\n    return false;\n}\n"
  },
  {
    "path": "sys/arch/pic32/dev/kbd.h",
    "content": "/*\n *\n * RetroBSD - PS2 keyboard driver for the Maximite PIC32 board\n *\n * Copyright (C) 2011 Rob Judd <judd@ob-wan.com>\n * All rights reserved.  The three clause (\"New\" or \"Modified\")\n * Berkeley software License Agreement specifies the terms and\n * conditions for redistribution.\n *\n */\n\n#ifndef __KBD_H__\n#define __KBD_H__\n\n\nextern char init_kbd(void);\nextern void read_kbd(void);\nextern char write_kbd(u_char data);\n\n#endif // __KBD_H__\n"
  },
  {
    "path": "sys/arch/pic32/dev/mrams.c",
    "content": "/*\n * Disk driver for serial MRAM chips connected via SPI port.\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/buf.h>\n#include <sys/errno.h>\n#include <sys/dk.h>\n#include <sys/disk.h>\n#include <sys/spi.h>\n#include <sys/config.h>\n\n#include <machine/debug.h>\n\n#include <pic32/dev/mrams.h>\n\n#define MRAM_WREN       0x06\n#define MRAM_WRDI       0x04\n#define MRAM_RDSR       0x05\n#define MRAM_WRSR       0x01\n#define MRAM_READ       0x03\n#define MRAM_WRITE      0x02\n#define MRAM_SLEEP      0xB9\n#define MRAM_WAKE       0xAB\n\n#ifndef MRAMS_MHZ\n#define MRAMS_MHZ       13\n#endif\n\nstruct spiio mrams_io[MRAMS_CHIPS];\n\nint mrams_dkindex;                      /* disk index for statistics */\n\n/*\n * Size of RAM disk.\n */\n#define MRAMS_TOTAL_KBYTES  (MRAMS_CHIPS * MRAMS_CHIPSIZE)\n\n#define MRBSIZE         1024\n#define MRBLOG2         10\n\nunsigned int mr_read_block(unsigned int chip, unsigned int address, unsigned int length, char *data)\n{\n    register unsigned int cs = 0;\n    struct spiio *io = &mrams_io[chip];\n\n    switch (chip) {\n    case 0:\n        #ifdef MRAMS_LED0_PORT\n        TRIS_CLR(MRAMS_LED0_PORT) = 1<<MRAMS_LED0_PIN;\n        LAT_SET(MRAMS_LED0_PORT) = 1<<MRAMS_LED0_PIN;\n        #endif\n        break;\n    case 1:\n        #ifdef MRAMS_LED1_PORT\n        TRIS_CLR(MRAMS_LED1_PORT) = 1<<MRAMS_LED1_PIN;\n        LAT_SET(MRAMS_LED1_PORT) = 1<<MRAMS_LED1_PIN;\n        #endif\n        break;\n    case 2:\n        #ifdef MRAMS_LED2_PORT\n        TRIS_CLR(MRAMS_LED2_PORT) = 1<<MRAMS_LED2_PIN;\n        LAT_SET(MRAMS_LED2_PORT) = 1<<MRAMS_LED2_PIN;\n        #endif\n        break;\n    case 3:\n        #ifdef MRAMS_LED3_PORT\n        TRIS_CLR(MRAMS_LED3_PORT) = 1<<MRAMS_LED3_PIN;\n        LAT_SET(MRAMS_LED3_PORT) = 1<<MRAMS_LED3_PIN;\n        #endif\n        break;\n    }\n\n    spi_select(io);\n    spi_transfer(io, MRAM_READ);\n    spi_transfer(io, address>>16);\n    spi_transfer(io, address>>8);\n    spi_transfer(io, address);\n\n    // If the length is a multiple of 32 bits, then do a 32 bit transfer\n#if 0\n    if ((length & 3) == 0)\n        spi_bulk_read_32(io, length, data);\n    else if ((length & 1) == 0)\n        spi_bulk_read_16(io, length, data);\n    else\n#endif\n    spi_bulk_read(io, length, (unsigned char *)data);\n    spi_deselect(io);\n\n    switch (chip) {\n    case 0:\n        #ifdef MRAMS_LED0_PORT\n        LAT_CLR(MRAMS_LED0_PORT) = 1<<MRAMS_LED0_PIN;\n        #endif\n        break;\n    case 1:\n        #ifdef MRAMS_LED1_PORT\n        LAT_CLR(MRAMS_LED1_PORT) = 1<<MRAMS_LED1_PIN;\n        #endif\n        break;\n    case 2:\n        #ifdef MRAMS_LED2_PORT\n        LAT_CLR(MRAMS_LED2_PORT) = 1<<MRAMS_LED2_PIN;\n        #endif\n        break;\n    case 3:\n        #ifdef MRAMS_LED3_PORT\n        LAT_CLR(MRAMS_LED3_PORT) = 1<<MRAMS_LED3_PIN;\n        #endif\n        break;\n    }\n    return cs;\n}\n\nint mrams_read(unsigned int offset, char *data, unsigned int bcount)\n{\n    register unsigned int chip;\n    register unsigned int toread;\n    register unsigned int address;\n    register unsigned int pass = 0;\n\n    while (bcount > 0) {\n        pass++;\n        toread = bcount;\n        if (toread > MRBSIZE)\n            toread = MRBSIZE;\n\n        chip = offset / MRAMS_CHIPSIZE;\n\n        address = (offset<<10) - (chip * (MRAMS_CHIPSIZE*1024));\n\n        if (chip >= MRAMS_CHIPS) {\n            printf(\"!!!EIO\\n\");\n            return EIO;\n        }\n        mr_read_block(chip, address, toread, data);\n        bcount -= toread;\n        offset += (toread>>MRBLOG2);\n        data += toread;\n    }\n    return 1;\n}\n\nunsigned int mr_write_block(unsigned int chip, unsigned int address, unsigned int length, char *data)\n{\n    struct spiio *io = &mrams_io[chip];\n    register unsigned int cs = 0;\n    char blank __attribute__((unused));\n\n    switch (chip) {\n    case 0:\n        #ifdef MRAMS_LED0_PORT\n        TRIS_CLR(MRAMS_LED0_PORT) = 1<<MRAMS_LED0_PIN;\n        LAT_SET(MRAMS_LED0_PORT) = 1<<MRAMS_LED0_PIN;\n        #endif\n        break;\n    case 1:\n        #ifdef MRAMS_LED1_PORT\n        TRIS_CLR(MRAMS_LED1_PORT) = 1<<MRAMS_LED1_PIN;\n        LAT_SET(MRAMS_LED1_PORT) = 1<<MRAMS_LED1_PIN;\n        #endif\n        break;\n    case 2:\n        #ifdef MRAMS_LED2_PORT\n        TRIS_CLR(MRAMS_LED2_PORT) = 1<<MRAMS_LED2_PIN;\n        LAT_SET(MRAMS_LED2_PORT) = 1<<MRAMS_LED2_PIN;\n        #endif\n        break;\n    case 3:\n        #ifdef MRAMS_LED3_PORT\n        TRIS_CLR(MRAMS_LED3_PORT) = 1<<MRAMS_LED3_PIN;\n        LAT_SET(MRAMS_LED3_PORT) = 1<<MRAMS_LED3_PIN;\n        #endif\n        break;\n    }\n\n    spi_select(io);\n    spi_transfer(io, MRAM_WRITE);\n    spi_transfer(io, address>>16);\n    spi_transfer(io, address>>8);\n    spi_transfer(io, address);\n\n#if 0\n    if ((length & 3) == 0)\n        spi_bulk_write_32(io, length, data);\n    else if ((length & 1) == 0)\n        spi_bulk_write_16(io, length, data);\n    else\n#endif\n    spi_bulk_write(io, length, (unsigned char *)data);\n    spi_deselect(io);\n\n    switch (chip) {\n    case 0:\n        #ifdef MRAMS_LED0_PORT\n        LAT_CLR(MRAMS_LED0_PORT) = 1<<MRAMS_LED0_PIN;\n        #endif\n        break;\n    case 1:\n        #ifdef MRAMS_LED1_PORT\n        LAT_CLR(MRAMS_LED1_PORT) = 1<<MRAMS_LED1_PIN;\n        #endif\n        break;\n    case 2:\n        #ifdef MRAMS_LED2_PORT\n        LAT_CLR(MRAMS_LED2_PORT) = 1<<MRAMS_LED2_PIN;\n        #endif\n        break;\n    case 3:\n        #ifdef MRAMS_LED3_PORT\n        LAT_CLR(MRAMS_LED3_PORT) = 1<<MRAMS_LED3_PIN;\n        #endif\n        break;\n    }\n    return cs;\n}\n\nint mrams_write(unsigned int offset, char *data, unsigned bcount)\n{\n    register unsigned int chip;\n    register unsigned int address;\n    register unsigned int towrite;\n    register unsigned int pass = 0;\n\n    while (bcount > 0) {\n        pass++;\n        towrite = bcount;\n        if (towrite > MRBSIZE)\n            towrite = MRBSIZE;\n\n        chip = offset / MRAMS_CHIPSIZE;\n        address = (offset<<10) - (chip * (MRAMS_CHIPSIZE*MRBSIZE));\n\n        if (chip >= MRAMS_CHIPS) {\n            printf(\"!!!EIO\\n\");\n            return EIO;\n        }\n\n        mr_write_block(chip, address, towrite, data);\n        bcount -= towrite;\n        offset += (towrite>>MRBLOG2);\n        data += towrite;\n    }\n    return 1;\n}\n\n/*\n * Initialize hardware.\n */\nstatic int mrams_init(int spi_port, int cs0, int cs1, int cs2, int cs3)\n{\n    struct spiio *io = &mrams_io[0];\n\n    if (spi_setup(io, spi_port, cs0) != 0) {\n        printf(\"mr0: cannot open SPI%u port\\n\", spi_port);\n        return 0;\n    }\n    spi_brg(io, MRAMS_MHZ * 1000);\n    spi_set(io, PIC32_SPICON_CKE);\n    spi_select(io);\n    spi_transfer(io, MRAM_WREN);\n    spi_deselect(io);\n\n#if MRAMS_CHIPS >= 1\n    spi_setup(io+1, spi_port, cs1);\n\n    spi_brg(io+1, MRAMS_MHZ * 1000);\n    spi_set(io+1, PIC32_SPICON_CKE);\n    spi_select(io+1);\n    spi_transfer(io+1, MRAM_WREN);\n    spi_deselect(io+1);\n#endif\n#if MRAMS_CHIPS >= 2\n    spi_setup(io+2, spi_port, cs2);\n\n    spi_brg(io+2, MRAMS_MHZ * 1000);\n    spi_set(io+2, PIC32_SPICON_CKE);\n    spi_select(io+2);\n    spi_transfer(io+2, MRAM_WREN);\n    spi_deselect(io+2);\n#endif\n#if MRAMS_CHIPS >= 3\n    spi_setup(io+3, spi_port, cs3);\n\n    spi_brg(io+3, MRAMS_MHZ * 1000);\n    spi_set(io+3, PIC32_SPICON_CKE);\n    spi_select(io+3);\n    spi_transfer(io+3, MRAM_WREN);\n    spi_deselect(io+3);\n#endif\n\n    printf(\"mr0: size %dKB, speed %d Mbit/sec\\n\",\n        MRAMS_CHIPS * MRAMS_CHIPSIZE, spi_get_brg(io) / 1000);\n    return 1;\n}\n\n/*\n * Open the disk.\n */\nint mrams_open(dev_t dev, int flag, int mode)\n{\n    return 0;\n}\n\nint mrams_close(dev_t dev, int flag, int mode)\n{\n    return 0;\n}\n\n/*\n * Return the size of the device in kbytes.\n */\ndaddr_t mrams_size(dev_t dev)\n{\n    return MRAMS_TOTAL_KBYTES;\n}\n\nvoid mrams_strategy(struct buf *bp)\n{\n    int offset = bp->b_blkno;\n    long nblk = btod(bp->b_bcount);\n    int s;\n\n    /*\n     * Determine the size of the transfer, and make sure it is\n     * within the boundaries of the partition.\n     */\n    if (bp->b_blkno + nblk > MRAMS_TOTAL_KBYTES) {\n        /* if exactly at end of partition, return an EOF */\n        if (bp->b_blkno == MRAMS_TOTAL_KBYTES) {\n            bp->b_resid = bp->b_bcount;\n            biodone(bp);\n            return;\n        }\n        /* or truncate if part of it fits */\n        nblk = MRAMS_TOTAL_KBYTES - bp->b_blkno;\n        if (nblk <= 0) {\n            bp->b_error = EINVAL;\n            bp->b_flags |= B_ERROR;\n            biodone(bp);\n            return;\n        }\n        bp->b_bcount = nblk << DEV_BSHIFT;\n    }\n\n    led_control(LED_SWAP, 1);\n\n    s = splbio();\n#ifdef UCB_METER\n    if (mrams_dkindex >= 0) {\n        dk_busy |= 1 << mrams_dkindex;\n        dk_xfer[mrams_dkindex]++;\n        dk_bytes[mrams_dkindex] += bp->b_bcount;\n    }\n#endif\n\n    if (bp->b_flags & B_READ) {\n        mrams_read(offset, bp->b_addr, bp->b_bcount);\n    } else {\n        mrams_write(offset, bp->b_addr, bp->b_bcount);\n    }\n\n    biodone(bp);\n    led_control(LED_SWAP, 0);\n#ifdef UCB_METER\n    if (mrams_dkindex >= 0)\n        dk_busy &= ~(1 << mrams_dkindex);\n#endif\n    splx(s);\n}\n\nint mrams_ioctl(dev_t dev, u_int cmd, caddr_t addr, int flag)\n{\n    int error = 0;\n\n    switch (cmd) {\n\n    case DIOCGETMEDIASIZE:\n        /* Get disk size in kbytes. */\n        *(int*) addr = MRAMS_TOTAL_KBYTES;\n        break;\n\n    default:\n        error = EINVAL;\n        break;\n    }\n    return error;\n}\n\n/*\n * Test to see if device is present.\n * Return true if found and initialized ok.\n */\nstatic int\nmrams_probe(config)\n    struct conf_device *config;\n{\n    int cs0 = config->dev_pins[0];\n    int cs1 = config->dev_pins[1];\n    int cs2 = config->dev_pins[2];\n    int cs3 = config->dev_pins[3];\n\n    /* Only one device unit is supported. */\n    if (config->dev_unit != 0)\n        return 0;\n\n    printf(\"mr0: port SPI%d, pins cs0=R%c%d/cs1=R%c%d/cs2=R%c%d/cs3=R%c%d\\n\",\n        config->dev_ctlr,\n        gpio_portname(cs0), gpio_pinno(cs0),\n        gpio_portname(cs1), gpio_pinno(cs1),\n        gpio_portname(cs2), gpio_pinno(cs2),\n        gpio_portname(cs3), gpio_pinno(cs3));\n\n    if (mrams_init(config->dev_ctlr, cs0, cs1, cs2, cs3) != 0)\n        return 0;\n\n#ifdef UCB_METER\n    dk_alloc(&mrams_dkindex, 1, \"mr0\");\n#endif\n    return 1;\n}\n\nstruct driver mrdriver = {\n    \"mr\", mrams_probe,\n};\n"
  },
  {
    "path": "sys/arch/pic32/dev/mrams.h",
    "content": "#ifndef _MRAMS_H\n#define _MRAMS_H\n\n#ifdef KERNEL\nextern int mrams_open(dev_t dev, int flag, int mode);\nextern int mrams_close(dev_t dev, int flag, int mode);\nextern daddr_t mrams_size(dev_t dev);\nextern void mrams_strategy(struct buf *bp);\nextern int mrams_ioctl (dev_t dev, u_int cmd, caddr_t addr, int flag);\n#endif\n\n#endif\n"
  },
  {
    "path": "sys/arch/pic32/dev/picga.c",
    "content": "/*\n * PICGA driver for PIC32.\n *\n * Copyright (C) 2012 Majenko Technologies <matt@majenko.co.uk>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/param.h>\n#include <sys/conf.h>\n#include <sys/user.h>\n#include <sys/ioctl.h>\n#include <sys/systm.h>\n#include <sys/uio.h>\n#include <sys/picga.h>\n#include <sys/spi.h>\n\n#include <machine/debug.h>\n\nextern int uwritec(struct uio *);\n\nstruct spiio picga_io;\n\nvoid\nblockdelay(u_int v)\n{\n\tfor (; v > 0; v--)\n\t\tasm volatile(\"nop\");\n}\n\nvoid\npicga_command(u_char cmd, u_char len, void *data)\n{\n\tstruct spiio *io = &picga_io;\n\n\tchar *p = (char *)data;\n\n\tspi_select(io);\n\tblockdelay(3000);\n\tspi_transfer(io, cmd);\n\tblockdelay(3000);\n\tspi_transfer(io, len);\n\tblockdelay(3000);\n\tspi_transfer(io, 0);\n\tblockdelay(3000);\n\n\twhile (len > 0) {\n\t\tspi_transfer(io, *p++);\n\t\tblockdelay(3000);\n\t\tlen--;\n\t}\n\n\tblockdelay(3000);\n\tspi_deselect(io);\n\tblockdelay(3000);\n}\n\nint\npicga_open(dev_t dev, int flag, int mode)\n{\n\tint channel;\n\tstruct spiio *io = &picga_io;\n\tstruct intval i;\n\tstruct coord2 j;\n\n\tchannel = minor(dev);\n\tif (channel > 0)\n\t\treturn ENODEV;\n\n\tif (spi_setup(io, PICGA_BUS, (u_int *)&PICGA_CS_PORT, PICGA_CS_PIN) != 0)\n\t\treturn ENODEV;\n\n\tspi_brg(io, 500);\n\n\ti.value = 0x01;\n\tpicga_command(SPI_FGCOLOR, sizeof(struct intval), &i);\n\ti.value = 0x00;\n\tpicga_command(SPI_BGCOLOR, sizeof(struct intval), &i);\n\ti.value = FONT_TOPAZ;\n\tpicga_command(SPI_FONT, sizeof(struct intval), &i);\n\tj.x = 0;\n\tj.y = 0;\n\tpicga_command(SPI_CLUT, sizeof(struct coord2), &j);\n\tj.x = 1;\n\tj.y = 0xFFFF;\n\tpicga_command(SPI_CLUT, sizeof(struct coord2), &j);\n\n\treturn 0;\n}\n\nint\npicga_close(dev_t dev, int flag, int mode)\n{\n\tint channel;\n\n\tchannel = minor(dev);\n\tif (channel > 0)\n\t\treturn ENODEV;\n\n\treturn 0;\n}\n\n/* Return the most recent ADC value. */\nint\npicga_read(dev_t dev, struct uio *uio, int flag)\n{\n\treturn EPERM;\n}\n\n/* Trigger an ADC conversion. */\nint\npicga_write(dev_t dev, struct uio *uio, int flag)\n{\n\tint channel;\n\tchar t[100];\n\tint p = 0;\n\tchar c;\n\n\tchannel = minor(dev);\n\tif (channel > 0)\n\t\treturn ENODEV;\n\n\twhile (uio->uio_iov->iov_len > 0) {\n\t\tp = 0;\n\t\twhile (p < 90 && uio->uio_iov->iov_len > 0) {\n\t\t\tc = uwritec(uio);\n\t\t\tt[p++] = c;\n\t\t\tt[p] = 0;\n\t\t\tif (c == '\\n')\n\t\t\t\tbreak;\n\t\t}\n\t\tpicga_command(SPI_PRINT, p, t);\n\t\tblockdelay(50000);\n\t}\n\n\treturn 0;\n}\n\nint\npicga_ioctl(dev_t dev, u_int cmd, caddr_t addr, int flag)\n{\n\tprintf(\"IOCTL %08X\\n\", cmd);\n\n\tswitch (cmd) {\n\tcase PICGA_CLS:\n\t\tprintf(\"CLS command\\n\");\n\t\tpicga_command(SPI_CLS, 0, NULL);\n\t\tbreak;\n\tdefault:\n\t\treturn EINVAL;\n\t}\n\n\treturn 0;\n}\n"
  },
  {
    "path": "sys/arch/pic32/dev/power_control.c",
    "content": "#include <sys/param.h>\n#include <sys/conf.h>\n#include <sys/user.h>\n#include <sys/systm.h>\n#include <sys/reboot.h>\n\n#include <machine/machparam.h>\n\nvolatile unsigned int psCounter;\nint countdown;\n\n#define COUNTDOWN 5\n\nvoid power_off()\n{\n    TRIS_CLR(POWER_CONTROL_PORT) = 1<<POWER_CONTROL_PIN;\n    LAT_SET(POWER_CONTROL_PORT) = 1<<POWER_CONTROL_PIN;\n}\n\nvoid power_switch_check()\n{\n    if (PORT_VAL(POWER_SWITCH_PORT) & (1<<POWER_SWITCH_PIN)) {\n        countdown = COUNTDOWN;\n        psCounter = 0;\n        if (psCounter > 0) {\n            LAT_SET(POWER_LED_PORT) = 1<<POWER_LED_PIN;\n            printf(\"power: switch released - power down aborted\\n\");\n        }\n    } else {\n        psCounter++;\n    }\n\n    if (psCounter == 20) {\n        if (countdown == 0) {\n            printf(\"power: powering off\\n\");\n            boot(0,RB_HALT | RB_POWEROFF);\n        }\n\n        psCounter = 0;\n        printf(\"power: powering down in %d\\n\",countdown);\n        countdown--;\n\n#ifdef POWER_LED_PORT\n        if (countdown%2 == 0) {\n            LAT_SET(POWER_LED_PORT) = 1<<POWER_LED_PIN;\n        } else {\n            LAT_CLR(POWER_LED_PORT) = 1<<POWER_LED_PIN;\n        }\n#endif\n    }\n}\n\nvoid power_init()\n{\n    psCounter = 0;\n    countdown = COUNTDOWN;\n#ifdef POWER_CONTROL_PORT\n    TRIS_CLR(POWER_CONTROL_PORT) = 1<<POWER_CONTROL_PIN;\n    LAT_CLR(POWER_CONTROL_PORT) = 1<<POWER_CONTROL_PIN;\n#endif\n\n#ifdef POWER_SWITCH_PORT\n    TRIS_SET(POWER_SWITCH_PORT) = 1<<POWER_SWITCH_PIN;\n#endif\n\n#ifdef POWER_LED_PORT\n    TRIS_CLR(POWER_LED_PORT) = 1<<POWER_LED_PIN;\n    LAT_SET(POWER_LED_PORT) = 1<<POWER_LED_PIN;\n#endif\n}\n"
  },
  {
    "path": "sys/arch/pic32/dev/pwm.c",
    "content": "/*\n * Pulse Width Modulation driver for PIC32.\n * Using Output Compare peripherals.\n *\n * Devices:\n *      /dev/pwmX\n *\n * Copyright (C) 2012 Majenko Technologies <matt@majenko.co.uk>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/param.h>\n#include <sys/conf.h>\n#include <sys/user.h>\n#include <sys/ioctl.h>\n#include <sys/systm.h>\n#include <sys/uio.h>\n#include <sys/pwm.h>\n#include <sys/config.h>\n\n#include <machine/debug.h>\n\n#define _BC(R,B) (R &= ~(1<<B))\n#define _BS(R,B) (R |= (1<<B))\n\nstruct pwm_state state[PWM_MAX_DEV];\n\nint pwm_set_mode(int unit, int mode)\n{\n    switch (mode) {\n    case PWM_MODE_PWM:\n        _BS(T2CON,15);      // ON\n        _BC(T2CON,6);\n        _BC(T2CON,5);       // >- 1:1 prescale\n        _BC(T2CON,4);\n        _BC(T2CON,3);       // 16 bit timer\n        _BC(T2CON,1);       // Internal clock source\n        PR2 = 0xFFFF;\n        switch (unit) {\n        case 0:\n            _BS(OC1CON,15); // ON\n            _BC(OC1CON,5);  // 16 bit\n            _BC(OC1CON,3);  // TMR2\n            _BS(OC1CON,2);  //\n            _BS(OC1CON,1);  //  >- PWM Mode, no fault pin\n            _BC(OC1CON,0);  //\n            state[0].mode = PWM_MODE_PWM;\n            break;\n        case 1:\n            _BS(OC2CON,15); // ON\n            _BC(OC2CON,5);  // 16 bit\n            _BC(OC2CON,3);  // TMR2\n            _BS(OC2CON,2);  //\n            _BS(OC2CON,1);  //  >- PWM Mode, no fault pin\n            _BC(OC2CON,0);  //\n            state[1].mode = PWM_MODE_PWM;\n            break;\n        case 2:\n            _BS(OC3CON,15); // ON\n            _BC(OC3CON,5);  // 16 bit\n            _BC(OC3CON,3);  // TMR2\n            _BS(OC3CON,2);  //\n            _BS(OC3CON,1);  //  >- PWM Mode, no fault pin\n            _BC(OC3CON,0);  //\n            state[2].mode = PWM_MODE_PWM;\n            break;\n        case 3:\n            _BS(OC4CON,15); // ON\n            _BC(OC4CON,5);  // 16 bit\n            _BC(OC4CON,3);  // TMR2\n            _BS(OC4CON,2);  //\n            _BS(OC4CON,1);  //  >- PWM Mode, no fault pin\n            _BC(OC4CON,0);  //\n            state[3].mode = PWM_MODE_PWM;\n            break;\n        case 4:\n            _BS(OC5CON,15); // ON\n            _BC(OC5CON,5);  // 16 bit\n            _BC(OC5CON,3);  // TMR2\n            _BS(OC5CON,2);  //\n            _BS(OC5CON,1);  //  >- PWM Mode, no fault pin\n            _BC(OC5CON,0);  //\n            state[4].mode = PWM_MODE_PWM;\n            break;\n        default:\n            return EINVAL;\n        }\n        DEBUG(\"pwm%d: Mode set to PWM\\n\",unit);\n        break;\n    default:\n        return EINVAL;\n    }\n    return 0;\n}\n\nint pwm_duty(int unit, unsigned int duty)\n{\n    if (state[unit].mode != PWM_MODE_PWM)\n        return EINVAL;\n\n    switch (unit) {\n    case 0:\n        OC1RS = duty;\n        break;\n    case 1:\n        OC2RS = duty;\n        break;\n    case 2:\n        OC3RS = duty;\n        break;\n    case 3:\n        OC4RS = duty;\n        break;\n    case 4:\n        OC5RS = duty;\n        break;\n    default:\n        return EINVAL;\n    }\n    DEBUG(\"pwm%d: Duty set to %d\\n\",unit,duty);\n    return 0;\n}\n\nint\npwm_open (dev, flag, mode)\n    dev_t dev;\n    int flag;\n    int mode;\n{\n    int unit = minor(dev);\n\n    if (unit >= PWM_MAX_DEV)\n        return ENXIO;\n    if (u.u_uid != 0)\n        return EPERM;\n    DEBUG(\"pwm%d: Opened\\n\",unit);\n    return 0;\n}\n\nint\npwm_close (dev, flag, mode)\n    dev_t dev;\n    int flag;\n    int mode;\n{\n    return 0;\n}\n\nint\npwm_read (dev, uio, flag)\n    dev_t dev;\n    struct uio *uio;\n    int flag;\n{\n    // TODO\n    return ENODEV;\n}\n\nint pwm_write (dev_t dev, struct uio *uio, int flag)\n{\n    return ENODEV;\n}\n\nint\npwm_ioctl (dev, cmd, addr, flag)\n    dev_t dev;\n    register u_int cmd;\n    caddr_t addr;\n    int flag;\n{\n    int unit;\n    int *val;\n    val = (int *)addr;\n\n    unit = minor(dev);\n\n    if (unit >= PWM_MAX_DEV)\n        return ENODEV;\n\n    if (cmd == PWM_SET_MODE) {\n        return pwm_set_mode(unit, *val);\n    }\n\n    if (cmd == PWM_DUTY) {\n        return pwm_duty(unit, (unsigned int) *val);\n    }\n    return 0;\n}\n\n/*\n * Test to see if device is present.\n * Return true if found and initialized ok.\n */\nstatic int\npwmprobe(config)\n    struct conf_device *config;\n{\n    printf(\"pwm: %u channels\\n\", PWM_MAX_DEV);\n    return 1;\n}\n\nstruct driver pwmdriver = {\n    \"pwm\", pwmprobe,\n};\n"
  },
  {
    "path": "sys/arch/pic32/dev/sd.c",
    "content": "/*\n * SD or SDHC card connected to SPI port.\n *\n * Up to two cards can be connected to the same SPI port.\n * PC-compatible partition table is supported.\n * The following device numbers are used:\n *\n * Major Minor Device  Partition\n * ----------------------------------------------\n *   0     0     sd0   Main SD card, whole volume\n *   0     1     sd0a  1-st partition, usually root FS\n *   0     2     sd0b  2-nd partition, usually swap\n *   0     3     sd0c  3-rd partition\n *   0     4     sd0d  4-th partition\n *   0     8     sd1   Second SD card, whole volume\n *   0     9     sd1a  1-st partition\n *   0     10    sd1b  2-nd partition\n *   0     11    sd1c  3-rd partition\n *   0     12    sd1d  4-th partition\n *\n * Copyright (C) 2010-2015 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/buf.h>\n#include <sys/errno.h>\n#include <sys/dk.h>\n#include <sys/disk.h>\n#include <sys/spi.h>\n#include <sys/config.h>\n\n#include <pic32/dev/sd.h>\n\n/*\n * Two SD/MMC disks on SPI.\n * Signals for SPI1:\n *      D0  - SDO1\n *      D10 - SCK1\n *      C4  - SDI1\n */\n#define NSD             2\n#define SECTSIZE        512\n#define SPI_ENHANCED            /* use SPI fifo */\n#ifndef SD_MHZ\n#define SD_MHZ          12      /* set 12.5Mhz; really 13.33MHz */\n#endif\n#ifndef SD_FAST_MHZ\n#define SD_FAST_MHZ     25      /* up to 25Mhz is allowed by the spec */\n#endif\n\n#define TIMO_WAIT_WDONE 400000\n#define TIMO_WAIT_WIDLE 300000\n#define TIMO_WAIT_CMD   100000\n#define TIMO_WAIT_WDATA 30000\n#define TIMO_READ       90000\n#define TIMO_SEND_OP    8000\n#define TIMO_CMD        7000\n#define TIMO_SEND_CSD   6000\n#define TIMO_WAIT_WSTOP 5000\n\n#define sdunit(dev)     ((minor(dev) & 8) >> 3)\n#define sdpart(dev)     ((minor(dev) & 7))\n#define RAWPART         0               /* 'x' partition */\n\n#define NPARTITIONS     4\n\n/*\n * Driver's data per disk drive.\n */\nstruct disk {\n    /*\n     * Partition table.\n     */\n    struct diskpart part[NPARTITIONS+1];\n\n    /*\n     * Card type.\n     */\n    int     card_type;\n#define TYPE_UNKNOWN    0\n#define TYPE_SD_LEGACY  1\n#define TYPE_SD_II      2\n#define TYPE_SDHC       3\n\n    struct spiio spiio;         /* interface to SPI port */\n    int     label_writable;     /* is sector 0 writable? */\n    int     dkindex;            /* disk index for statistics */\n    u_int   openpart;           /* all partitions open on this drive */\n    u_char  ocr[4];             /* operation condition register */\n    u_char  csd[16];            /* card-specific data */\n    u_short group[6];           /* function group bitmasks */\n    int     ma;                 /* power consumption */\n};\n\nstruct disk sddrives[NSD];      /* Table of units */\n\nint sd_timo_cmd;                /* Max timeouts, for sysctl */\nint sd_timo_send_op;\nint sd_timo_send_csd;\nint sd_timo_read;\nint sd_timo_wait_cmd;\nint sd_timo_wait_wdata;\nint sd_timo_wait_wdone;\nint sd_timo_wait_wstop;\nint sd_timo_wait_widle;\n\n/*\n * Definitions for MMC/SDC commands.\n */\n#define CMD_GO_IDLE             0       /* CMD0 */\n#define CMD_SEND_OP_MMC         1       /* CMD1 (MMC) */\n#define CMD_SWITCH_FUNC         6\n#define CMD_SEND_IF_COND        8\n#define CMD_SEND_CSD            9\n#define CMD_SEND_CID            10\n#define CMD_STOP                12\n#define CMD_SEND_STATUS         13      /* CMD13 */\n#define CMD_SET_BLEN            16\n#define CMD_READ_SINGLE         17\n#define CMD_READ_MULTIPLE       18\n#define CMD_SET_BCOUNT          23      /* (MMC) */\n#define CMD_SET_WBECNT          23      /* ACMD23 (SDC) */\n#define CMD_WRITE_SINGLE        24\n#define CMD_WRITE_MULTIPLE      25\n#define CMD_SEND_OP_SDC         41      /* ACMD41 (SDC) */\n#define CMD_APP                 55      /* CMD55 */\n#define CMD_READ_OCR            58\n\n#define DATA_START_BLOCK        0xFE    /* start data for single block */\n#define STOP_TRAN_TOKEN         0xFD    /* stop token for write multiple */\n#define WRITE_MULTIPLE_TOKEN    0xFC    /* start data for write multiple */\n\n/*\n * Release the card's /CS signal.\n * Add extra clocks after a deselect.\n */\nstatic void card_release(struct spiio *io)\n{\n    spi_deselect(io);\n    spi_transfer(io, 0xFF);\n}\n\n/*\n * Wait while busy, up to 300 msec.\n */\nstatic void card_wait_ready(int unit, int limit, int *maxcount)\n{\n    int i;\n    struct spiio *io = &sddrives[unit].spiio;\n\n    spi_transfer(io, 0xFF);\n    for (i=0; i<limit; i++)\n    {\n        if (spi_transfer(io, 0xFF) == 0xFF)\n        {\n            if (*maxcount < i)\n                *maxcount = i;\n            return;\n        }\n    }\n    printf(\"sd%d: wait_ready(%d) failed\\n\", unit, limit);\n}\n\n/*\n * Send a command and address to SD media.\n * Return response:\n *   FF - timeout\n *   00 - command accepted\n *   01 - command received, card in idle state\n *\n * Other codes:\n *   bit 0 = Idle state\n *   bit 1 = Erase Reset\n *   bit 2 = Illegal command\n *   bit 3 = Communication CRC error\n *   bit 4 = Erase sequence error\n *   bit 5 = Address error\n *   bit 6 = Parameter error\n *   bit 7 = Always 0\n */\nstatic int card_cmd(unsigned int unit, unsigned int cmd, unsigned int addr)\n{\n    int i, reply;\n    struct spiio *io = &sddrives[unit].spiio;\n\n    /* Wait for not busy, up to 300 msec. */\n    if (cmd != CMD_GO_IDLE)\n        card_wait_ready(unit, TIMO_WAIT_CMD, &sd_timo_wait_cmd);\n\n    /* Send a comand packet (6 bytes). */\n    spi_transfer(io, cmd | 0x40);\n    spi_transfer(io, addr >> 24);\n    spi_transfer(io, addr >> 16);\n    spi_transfer(io, addr >> 8);\n    spi_transfer(io, addr);\n\n    /* Send cmd checksum for CMD_GO_IDLE.\n     * For all other commands, CRC is ignored. */\n    if (cmd == CMD_GO_IDLE)\n        spi_transfer(io, 0x95);\n    else if (cmd == CMD_SEND_IF_COND)\n        spi_transfer(io, 0x87);\n    else\n        spi_transfer(io, 0xFF);\n\n    /* Wait for a response. */\n    for (i=0; i<TIMO_CMD; i++)\n    {\n        reply = spi_transfer(io, 0xFF);\n        if (! (reply & 0x80))\n        {\n            if (sd_timo_cmd < i)\n                sd_timo_cmd = i;\n            return reply;\n        }\n    }\n    if (cmd != CMD_GO_IDLE)\n    {\n        printf(\"sd%d: card_cmd timeout, cmd=%02x, addr=%08x, reply=%02x\\n\",\n            unit, cmd, addr, reply);\n    }\n    return reply;\n}\n\n/*\n * Initialize a card.\n * Return nonzero if successful.\n */\nstatic int card_init(int unit)\n{\n    int i, reply;\n    int timeout = 4;\n    struct spiio *io = &sddrives[unit].spiio;\n    struct disk *du = &sddrives[unit];\n\n    /* Slow speed: 250 kHz */\n    spi_brg(io, 250);\n\n    du->card_type = TYPE_UNKNOWN;\n    do {\n        /* Unselect the card. */\n        card_release(io);\n\n        /* Send 80 clock cycles for start up. */\n        for (i=0; i<10; i++)\n            spi_transfer(io, 0xFF);\n\n        /* Select the card and send a single GO_IDLE command. */\n        spi_select(io);\n        timeout--;\n        reply = card_cmd(unit, CMD_GO_IDLE, 0);\n\n    } while (reply != 1 && timeout != 0);\n\n    card_release(io);\n    if (reply != 1)\n    {\n        /* It must return Idle. */\n        return 0;\n    }\n\n    /* Check SD version. */\n    spi_select(io);\n    reply = card_cmd(unit, CMD_SEND_IF_COND, 0x1AA);\n    if (reply & 4)\n    {\n        /* Illegal command: card type 1. */\n        card_release(io);\n        du->card_type = TYPE_SD_LEGACY;\n    } else {\n        u_char response[4];\n        response[0] = spi_transfer(io, 0xFF);\n        response[1] = spi_transfer(io, 0xFF);\n        response[2] = spi_transfer(io, 0xFF);\n        response[3] = spi_transfer(io, 0xFF);\n        card_release(io);\n        if (response[3] != 0xAA)\n        {\n            printf(\"sd%d: cannot detect card type, response=%02x-%02x-%02x-%02x\\n\",\n                unit, response[0], response[1], response[2], response[3]);\n            return 0;\n        }\n        du->card_type = TYPE_SD_II;\n    }\n\n    /* Send repeatedly SEND_OP until Idle terminates. */\n    for (i=0; ; i++)\n    {\n        spi_select(io);\n        card_cmd(unit, CMD_APP, 0);\n        reply = card_cmd(unit, CMD_SEND_OP_SDC,\n                         (du->card_type == TYPE_SD_II) ? 0x40000000 : 0);\n        spi_select(io);\n        if (reply == 0)\n            break;\n        if (i >= TIMO_SEND_OP)\n        {\n            /* Init timed out. */\n            printf(\"card_init: SEND_OP timed out, reply = %d\\n\", reply);\n            return 0;\n        }\n    }\n    if (sd_timo_send_op < i)\n        sd_timo_send_op = i;\n\n    /* If SD2 read OCR register to check for SDHC card. */\n    if (du->card_type == TYPE_SD_II)\n    {\n        spi_select(io);\n        reply = card_cmd(unit, CMD_READ_OCR, 0);\n        if (reply != 0)\n        {\n            card_release(io);\n            printf(\"sd%d: READ_OCR failed, reply=%02x\\n\", unit, reply);\n            return 0;\n        }\n        du->ocr[0] = spi_transfer(io, 0xFF);\n        du->ocr[1] = spi_transfer(io, 0xFF);\n        du->ocr[2] = spi_transfer(io, 0xFF);\n        du->ocr[3] = spi_transfer(io, 0xFF);\n        card_release(io);\n        if ((du->ocr[0] & 0xC0) == 0xC0)\n        {\n            du->card_type = TYPE_SDHC;\n        }\n    }\n    /* Fast speed. */\n    spi_brg(io, SD_MHZ * 1000);\n    return 1;\n}\n\n/*\n * Get disk size in 512-byte sectors.\n * Return nonzero if successful.\n */\nstatic int card_size(int unit)\n{\n    unsigned csize, n;\n    int reply, i;\n    int nsectors;\n    struct spiio *io = &sddrives[unit].spiio;\n    struct disk *du = &sddrives[unit];\n\n    spi_select(io);\n    reply = card_cmd(unit, CMD_SEND_CSD, 0);\n    if (reply != 0) {\n        /* Command rejected. */\n        card_release(io);\n        return 0;\n    }\n\n    /* Wait for a response. */\n    for (i=0; ; i++) {\n        reply = spi_transfer(io, 0xFF);\n        if (reply == DATA_START_BLOCK)\n            break;\n        if (i >= TIMO_SEND_CSD) {\n            /* Command timed out. */\n            card_release(io);\n            printf(\"sd%d: card_size: SEND_CSD timed out, reply = %d\\n\",\n                unit, reply);\n            return 0;\n        }\n    }\n    if (sd_timo_send_csd < i)\n        sd_timo_send_csd = i;\n\n    /* Read data. */\n    for (i=0; i<16; i++) {\n        du->csd[i] = spi_transfer(io, 0xFF);\n    }\n    /* Ignore CRC. */\n    spi_transfer(io, 0xFF);\n    spi_transfer(io, 0xFF);\n\n    /* Disable the card. */\n    card_release(io);\n\n    /* CSD register has different structure\n     * depending upon protocol version. */\n    switch (du->csd[0] >> 6) {\n    case 1:                     /* SDC ver 2.00 */\n        csize = du->csd[9] + (du->csd[8] << 8) + 1;\n        nsectors = csize << 10;\n        break;\n    case 0:                     /* SDC ver 1.XX or MMC. */\n        n = (du->csd[5] & 15) + ((du->csd[10] & 128) >> 7) +\n            ((du->csd[9] & 3) << 1) + 2;\n        csize = (du->csd[8] >> 6) + (du->csd[7] << 2) +\n            ((du->csd[6] & 3) << 10) + 1;\n        nsectors = csize << (n - 9);\n        break;\n    default:                    /* Unknown version. */\n        return 0;\n    }\n    return nsectors;\n}\n\n/*\n * Use CMD6 to enable high-speed mode.\n */\nstatic void card_high_speed(int unit)\n{\n    int reply, i;\n    struct spiio *io = &sddrives[unit].spiio;\n    struct disk *du = &sddrives[unit];\n    unsigned char status[64];\n\n    /* Here we set HighSpeed 50MHz.\n     * We do not tackle the power and io driver strength yet. */\n    spi_select(io);\n    reply = card_cmd(unit, CMD_SWITCH_FUNC, 0x80000001);\n    if (reply != 0) {\n        /* Command rejected. */\n        card_release(io);\n        return;\n    }\n\n    /* Wait for a response. */\n    for (i=0; ; i++) {\n        reply = spi_transfer(io, 0xFF);\n        if (reply == DATA_START_BLOCK)\n            break;\n        if (i >= 5000) {\n            /* Command timed out. */\n            card_release(io);\n            printf(\"sd%d: card_size: SWITCH_FUNC timed out, reply = %d\\n\",\n                unit, reply);\n            return;\n        }\n    }\n\n    /* Read 64-byte status. */\n    for (i=0; i<64; i++)\n        status[i] = spi_transfer(io, 0xFF);\n    card_release(io);\n\n    if ((status[16] & 0xF) == 1) {\n        /* The card has switched to high-speed mode. */\n        spi_brg(io, SD_FAST_MHZ * 1000);\n    }\n\n    /* Save function group information for later use. */\n    du->ma = status[0] << 8 | status[1];\n    du->group[0] = status[12] << 8 | status[13];\n    du->group[1] = status[10] << 8 | status[11];\n    du->group[2] = status[8] << 8 | status[9];\n    du->group[3] = status[6] << 8 | status[7];\n    du->group[4] = status[4] << 8 | status[5];\n    du->group[5] = status[2] << 8 | status[3];\n\n    printf(\"sd%d: function groups %x/%x/%x/%x/%x/%x\", unit,\n        du->group[0] & 0x7fff, du->group[1] & 0x7fff,\n        du->group[2] & 0x7fff, du->group[3] & 0x7fff,\n        du->group[4] & 0x7fff, du->group[5] & 0x7fff);\n    if (du->ma > 0)\n        printf(\", max current %u mA\", du->ma);\n    printf(\"\\n\");\n}\n\n/*\n * Read a block of data.\n * Return nonzero if successful.\n */\nstatic int card_read(int unit, unsigned int offset, char *data, unsigned int bcount)\n{\n    int reply, i;\n    struct spiio *io = &sddrives[unit].spiio;\n    struct disk *du = &sddrives[unit];\n\n    /* Send read-multiple command. */\n    spi_select(io);\n    if (du->card_type != TYPE_SDHC)\n        offset <<= 9;\n    reply = card_cmd(unit, CMD_READ_MULTIPLE, offset<<1);\n    if (reply != 0)\n    {\n        /* Command rejected. */\n        printf(\"sd%d: card_read: bad READ_MULTIPLE reply = %d, offset = %08x\\n\",\n            unit, reply, offset<<1);\n        card_release(io);\n        return 0;\n    }\n\nagain:\n    /* Wait for a response. */\n    for (i=0; ; i++)\n    {\n        int x = spl0();\n        reply = spi_transfer(io, 0xFF);\n        splx(x);\n        if (reply == DATA_START_BLOCK)\n            break;\n        if (i >= TIMO_READ)\n        {\n            /* Command timed out. */\n            printf(\"sd%d: card_read: READ_MULTIPLE timed out, reply = %d\\n\",\n                unit, reply);\n            card_release(io);\n            return 0;\n        }\n    }\n    if (sd_timo_read < i)\n        sd_timo_read = i;\n\n    /* Read data. */\n    if (bcount >= SECTSIZE)\n    {\n        spi_bulk_read_32_be(io, SECTSIZE, data);\n        data += SECTSIZE;\n    } else {\n        spi_bulk_read(io, bcount, (unsigned char *)data);\n        data += bcount;\n        for (i=bcount; i<SECTSIZE; i++)\n            spi_transfer(io, 0xFF);\n    }\n    /* Ignore CRC. */\n    spi_transfer(io, 0xFF);\n    spi_transfer(io, 0xFF);\n\n    if (bcount > SECTSIZE)\n    {\n        /* Next sector. */\n        bcount -= SECTSIZE;\n        goto again;\n    }\n\n    /* Stop a read-multiple sequence. */\n    card_cmd(unit, CMD_STOP, 0);\n    card_release(io);\n    return 1;\n}\n\n/*\n * Write a block of data.\n * Return nonzero if successful.\n */\nstatic int card_write(int unit, unsigned offset, char *data, unsigned bcount)\n{\n    unsigned reply, i;\n    struct spiio *io = &sddrives[unit].spiio;\n    struct disk *du = &sddrives[unit];\n\n    /* Send pre-erase count. */\n    spi_select(io);\n    card_cmd(unit, CMD_APP, 0);\n    reply = card_cmd(unit, CMD_SET_WBECNT, (bcount + SECTSIZE - 1) / SECTSIZE);\n    if (reply != 0)\n    {\n        /* Command rejected. */\n        card_release(io);\n        printf(\"sd%d: card_write: bad SET_WBECNT reply = %02x, count = %u\\n\",\n            unit, reply, (bcount + SECTSIZE - 1) / SECTSIZE);\n        return 0;\n    }\n\n    /* Send write-multiple command. */\n    if (du->card_type != TYPE_SDHC)\n        offset <<= 9;\n    reply = card_cmd(unit, CMD_WRITE_MULTIPLE, offset<<1);\n    if (reply != 0)\n    {\n        /* Command rejected. */\n        card_release(io);\n        printf(\"sd%d: card_write: bad WRITE_MULTIPLE reply = %02x\\n\", unit, reply);\n        return 0;\n    }\n    card_release(io);\nagain:\n    /* Select, wait while busy. */\n    spi_select(io);\n    card_wait_ready(unit, TIMO_WAIT_WDATA, &sd_timo_wait_wdata);\n\n    /* Send data. */\n    spi_transfer(io, WRITE_MULTIPLE_TOKEN);\n    if (bcount >= SECTSIZE)\n    {\n        spi_bulk_write_32_be(io, SECTSIZE, data);\n        data += SECTSIZE;\n    } else {\n        spi_bulk_write(io, bcount, (unsigned char *)data);\n        data += bcount;\n        for (i=bcount; i<SECTSIZE; i++)\n            spi_transfer(io, 0xFF);\n    }\n    /* Send dummy CRC. */\n    spi_transfer(io, 0xFF);\n    spi_transfer(io, 0xFF);\n\n    /* Check if data accepted. */\n    reply = spi_transfer(io, 0xFF);\n    if ((reply & 0x1f) != 0x05)\n    {\n        /* Data rejected. */\n        card_release(io);\n        printf(\"sd%d: card_write: data rejected, reply = %02x\\n\", unit, reply);\n        return 0;\n    }\n\n    /* Wait for write completion. */\n    int x = spl0();\n    card_wait_ready(unit, TIMO_WAIT_WDONE, &sd_timo_wait_wdone);\n    splx(x);\n    card_release(io);\n\n    if (bcount > SECTSIZE)\n    {\n        /* Next sector. */\n        bcount -= SECTSIZE;\n        goto again;\n    }\n\n    /* Stop a write-multiple sequence. */\n    spi_select(io);\n    card_wait_ready(unit, TIMO_WAIT_WSTOP, &sd_timo_wait_wstop);\n    spi_transfer(io, STOP_TRAN_TOKEN);\n    card_wait_ready(unit, TIMO_WAIT_WIDLE, &sd_timo_wait_widle);\n    card_release(io);\n    return 1;\n}\n\n/*\n * Detect a card.\n */\nstatic int sd_setup(int unit)\n{\n    struct spiio *io = &sddrives[unit].spiio;\n    struct disk *du = &sddrives[unit];\n    u_short buf[256];\n\n#ifdef SD0_ENA_PORT\n    /* On Duinomite Mega board, pin B13 set low\n     * enables a +3.3V power to SD card. */\n    if (unit == 0) {\n        LAT_CLR(SD0_ENA_PORT) = 1 << SD0_ENA_PIN;\n        udelay(1000);\n    }\n#endif\n\n#ifdef SD1_ENA_PORT\n    /* On Duinomite Mega board, pin B13 set low\n     * enables a +3.3V power to SD card. */\n    if (unit == 1) {\n        LAT_CLR(SD1_ENA_PORT) = 1 << SD1_ENA_PIN;\n        udelay(1000);\n    }\n#endif\n\n    if (! card_init(unit)) {\n        printf(\"sd%d: no SD/MMC card detected\\n\", unit);\n        return 0;\n    }\n    /* Get the size of raw partition. */\n    bzero(du->part, sizeof(du->part));\n    du->part[RAWPART].dp_offset = 0;\n    du->part[RAWPART].dp_nsectors = card_size(unit);\n    if (du->part[RAWPART].dp_nsectors == 0) {\n        printf(\"sd%d: cannot get card size\\n\", unit);\n        return 0;\n    }\n\n    /* Switch to the high speed mode, if possible. */\n    if (du->csd[4] & 0x40) {\n        /* Class 10 card: switch to high-speed mode.\n         * SPI interface of pic32 allows up to 25MHz clock rate. */\n        card_high_speed(unit);\n    }\n    printf(\"sd%d: type %s, size %u kbytes, speed %u Mbit/sec\\n\", unit,\n        (du->card_type == TYPE_SDHC) ? \"SDHC\" :\n        (du->card_type == TYPE_SD_II) ? \"II\" : \"I\",\n        du->part[RAWPART].dp_nsectors / 2,\n        spi_get_brg(io) / 1000);\n\n    /* Read partition table. */\n    int s = splbio();\n    if (! card_read(unit, 0, (char*)buf, sizeof(buf))) {\n        splx(s);\n        printf(\"sd%d: cannot read partition table\\n\", unit);\n        return 0;\n    }\n    splx(s);\n    if (buf[255] == MBR_MAGIC) {\n        bcopy(&buf[223], &du->part[1], 64);\n#if 1\n        int i;\n        for (i=1; i<=NPARTITIONS; i++) {\n            if (du->part[i].dp_type != 0)\n                printf(\"sd%d%c: partition type %02x, sector %u, size %u kbytes\\n\",\n                    unit, i+'a'-1, du->part[i].dp_type,\n                    du->part[i].dp_offset,\n                    du->part[i].dp_nsectors / 2);\n        }\n#endif\n    }\n    return 1;\n}\n\n/*\n * Disable power to the SD card.\n */\nstatic void sd_release(int unit)\n{\n    struct disk *du = &sddrives[unit];\n\n    /* Forget the partition table. */\n    du->part[RAWPART].dp_nsectors = 0;\n\n#ifdef SD0_ENA_PORT\n    /* On Duinomite Mega board, pin B13 set low\n     * enables a +3.3V power to SD card. */\n    if (unit == 0) {\n        /* Enable SD0 phy - pin is assumed to be active low */\n        TRIS_CLR(SD0_ENA_PORT) = 1 << SD0_ENA_PIN;\n        LAT_SET(SD0_ENA_PORT) = 1 << SD0_ENA_PIN;\n        udelay(1000);\n    }\n#endif\n\n#ifdef SD1_ENA_PORT\n    /* On Duinomite Mega board, pin B13 set low\n     * enables a +3.3V power to SD card. */\n    if (unit == 1) {\n        /* Enable SD1 phy - pin is assumed to be active low */\n        TRIS_CLR(SD1_ENA_PORT) = 1 << SD1_ENA_PIN;\n        LAT_SET(SD1_ENA_PORT) = 1 << SD1_ENA_PIN;\n        udelay(1000);\n    }\n#endif\n}\n\nint sdopen(dev_t dev, int flags, int mode)\n{\n    int unit = sdunit(dev);\n    int part = sdpart(dev);\n    struct disk *du = &sddrives[unit];\n    unsigned mask, i;\n\n    if (unit >= NSD || part > NPARTITIONS)\n        return ENXIO;\n\n    /*\n     * Setup the SD card interface.\n     */\n    if (du->part[RAWPART].dp_nsectors == 0) {\n        if (! sd_setup(unit)) {\n            return ENODEV;\n        }\n    }\n    mask = 1 << part;\n\n    /*\n     * Warn if a partion is opened\n     * that overlaps another partition which is open\n     * unless one is the \"raw\" partition (whole disk).\n     */\n    if (part != RAWPART && (du->openpart & mask) == 0) {\n        unsigned start = du->part[part].dp_offset;\n        unsigned end = start + du->part[part].dp_nsectors;\n\n        /* Check for overlapped partitions. */\n        for (i=0; i<=NPARTITIONS; i++) {\n            struct diskpart *pp = &du->part[i];\n\n            if (i == part || i == RAWPART)\n                continue;\n\n            if (pp->dp_offset + pp->dp_nsectors <= start ||\n                pp->dp_offset >= end)\n                continue;\n\n            if (du->openpart & (1 << i))\n                printf(\"sd%d%c: overlaps open partition (sd%d%c)\\n\",\n                    unit, part + 'a' - 1,\n                    unit, pp - du->part + 'a' - 1);\n        }\n    }\n    du->openpart |= mask;\n    return 0;\n}\n\nint sdclose(dev_t dev, int mode, int flag)\n{\n    int unit = sdunit(dev);\n    int part = sdpart(dev);\n    struct disk *du = &sddrives[unit];\n\n    if (unit >= NSD || part > NPARTITIONS)\n        return ENODEV;\n\n    du->openpart &= ~(1 << part);\n    if (du->openpart == 0) {\n        /* All partitions closed.\n         * Release the SD card. */\n        sd_release(unit);\n    }\n    return 0;\n}\n\n/*\n * Get disk size in kbytes.\n * Return nonzero if successful.\n */\ndaddr_t sdsize(dev_t dev)\n{\n    int unit = sdunit(dev);\n    int part = sdpart(dev);\n    struct disk *du = &sddrives[unit];\n\n    if (unit >= NSD || part > NPARTITIONS || du->openpart == 0)\n        return 0;\n\n    return du->part[part].dp_nsectors >> 1;\n}\n\nvoid sdstrategy(struct buf *bp)\n{\n    int unit = sdunit(bp->b_dev);\n    struct disk *du = &sddrives[unit];\n    struct diskpart *p = &du->part[sdpart(bp->b_dev)];\n    int part_size = p->dp_nsectors >> 1;\n    int offset = bp->b_blkno;\n    long nblk = btod(bp->b_bcount);\n    int s;\n\n    /*\n     * Determine the size of the transfer, and make sure it is\n     * within the boundaries of the partition.\n     */\n    offset += p->dp_offset >> 1;\n    if (offset == 0 &&\n        ! (bp->b_flags & B_READ) && ! du->label_writable)\n    {\n        /* Write to partition table not allowed. */\n        bp->b_error = EROFS;\nbad:    bp->b_flags |= B_ERROR;\n        biodone(bp);\n        return;\n    }\n    if (bp->b_blkno + nblk > part_size) {\n        /* if exactly at end of partition, return an EOF */\n        if (bp->b_blkno == part_size) {\n            bp->b_resid = bp->b_bcount;\n            biodone(bp);\n            return;\n        }\n        /* or truncate if part of it fits */\n        nblk = part_size - bp->b_blkno;\n        if (nblk <= 0) {\n            bp->b_error = EINVAL;\n            goto bad;\n        }\n        bp->b_bcount = nblk << DEV_BSHIFT;\n    }\n\n    if (bp->b_dev == swapdev) {\n        led_control(LED_SWAP, 1);\n    } else {\n        led_control(LED_DISK, 1);\n    }\n\n    s = splbio();\n#ifdef UCB_METER\n    if (du->dkindex >= 0) {\n        dk_busy |= 1 << du->dkindex;\n        dk_xfer[du->dkindex]++;\n        dk_bytes[du->dkindex] += bp->b_bcount;\n    }\n#endif\n\n    if (bp->b_flags & B_READ) {\n        card_read(unit, offset, bp->b_addr, bp->b_bcount);\n    } else {\n        card_write(unit, offset, bp->b_addr, bp->b_bcount);\n    }\n\n    biodone(bp);\n    if (bp->b_dev == swapdev) {\n        led_control(LED_SWAP, 0);\n    } else {\n        led_control(LED_DISK, 0);\n    }\n#ifdef UCB_METER\n    if (du->dkindex >= 0)\n        dk_busy &= ~(1 << du->dkindex);\n#endif\n    splx(s);\n}\n\nint sdioctl(dev_t dev, u_int cmd, caddr_t addr, int flag)\n{\n    int unit = sdunit(dev);\n    int part = sdpart(dev);\n    struct diskpart *dp;\n    int i, error = 0;\n\n    switch (cmd) {\n\n    case DIOCGETMEDIASIZE:\n        /* Get disk size in kbytes. */\n        dp = &sddrives[unit].part[part];\n        *(int*) addr = dp->dp_nsectors >> 1;\n        break;\n\n    case DIOCREINIT:\n        for (i=0; i<=NPARTITIONS; i++)\n            bflush(makedev(major(dev), i));\n        sd_setup(unit);\n        break;\n\n    case DIOCGETPART:\n        /* Get partition table entry. */\n        dp = &sddrives[unit].part[part];\n        *(struct diskpart*) addr = *dp;\n        break;\n\n    default:\n        error = EINVAL;\n        break;\n    }\n    return error;\n}\n\n/*\n * Test to see if device is present.\n * Return true if found and initialized ok.\n */\nstatic int\nsd_probe(config)\n    struct conf_device *config;\n{\n    int unit = config->dev_unit;\n    int cs = config->dev_pins[0];\n    struct spiio *io = &sddrives[unit].spiio;\n    const char *ctlr_name = config->dev_cdriver->d_name;\n    int ctlr_num = config->dev_ctlr;\n\n    if (unit < 0 || unit >= NSD)\n        return 0;\n    printf(\"sd%u: port %s%d, pin cs=R%c%d\\n\", unit,\n        ctlr_name, ctlr_num, gpio_portname(cs), gpio_pinno(cs));\n\n    if (spi_setup(io, ctlr_num, cs) != 0) {\n        printf(\"sd%u: cannot open %s%u port\\n\", unit, ctlr_name, ctlr_num);\n        return 0;\n    }\n\n    /* Disable power to the SD card. */\n    sd_release(unit);\n\n    spi_brg(io, 250);\n    spi_set(io, PIC32_SPICON_CKE);\n\n#ifdef UCB_METER\n    dk_alloc(&sddrives[unit].dkindex, 1, (unit == 0) ? \"sd0\" : \"sd1\");\n#endif\n    return 1;\n}\n\nstruct driver sddriver = {\n    \"sd\", sd_probe,\n};\n"
  },
  {
    "path": "sys/arch/pic32/dev/sd.h",
    "content": "#ifndef _SD_H\n#define _SD_H\n\n#ifdef KERNEL\nextern int sdopen(dev_t dev, int flag, int mode);\nextern int sdclose(dev_t dev, int flag, int mode);\nextern daddr_t sdsize(dev_t dev);\nextern void sdstrategy(struct buf *bp);\nextern int sdioctl (dev_t dev, u_int cmd, caddr_t addr, int flag);\n#endif\n\n#endif\n"
  },
  {
    "path": "sys/arch/pic32/dev/sdram.S",
    "content": "/*\n * SDRAM Access Routines for PIC32.\n *\n * Retromaster - 10.05.2010\n *\n * This file is in the public domain. You can use, modify, and distribute the source code\n * and executable programs based on the source code. This file is provided \"as is\" and\n * without any express or implied warranties whatsoever. Use at your own risk!\n *\n * Changes by jmcgee for inclusion in the retrobsd project.\n */\n\n/* SDRAM Used: HY57V281620 */\n\n/*\n * See rd_sdramp_config.h for sdramp port/pin configuration\n */\n#include <pic32/dev/sdramp_config.h>\n\n/* Offsets (from TRISA) for the various port control registers */\n#define TRIS_OFFSET   0x0\n#define PORT_OFFSET   (PORTA-TRISA)\n#define LAT_OFFSET    (LATA-TRISA)\n#define ODCF_OFFSET   (ODCA-TRISA)\n\n/* Offsets (from TRISA) for the various io port bit manipulator registers */\n#define NOP_OP_OFFSET 0x0\n#define CLR_OP_OFFSET (TRISACLR-TRISA)\n#define SET_OP_OFFSET (TRISASET-TRISA)\n#define INV_OP_OFFSET (TRISAINV-TRISA)\n\n        /* Global Symbols */\n        .globl sdram_init\n        .globl sdram_read\n        .globl sdram_write\n        .globl sdram_active\n        .globl sdram_auto_refresh\n        .globl sdram_precharge\n        .globl sdram_precharge_all\n        .globl sdram_sleep\n        .globl sdram_wake\n        .globl sdram_bank\n\n        .type sdram_init, @function\n        .type sdram_read, @function\n        .type sdram_write, @function\n        .type sdram_active, @function\n        .type sdram_auto_refresh, @function\n        .type sdram_precharge, @function\n        .type sdram_precharge_all, @function\n        .type sdram_sleep, @function\n        .type sdram_wake, @function\n        .type sdram_bank, @function\n\n    /*\n     * This code MUST execute from ram and the ram MUST be configured\n     * for zero wait states. Interrupts MUST disabled before\n     * calling any of these functions, and any DMA MUST also be\n     * disabled.\n     *\n     * Also, the peripheral bus divisor must be set to 1.\n     */\n\n        .section .ramfunc,\"ax\",@progbits\n\n    /* No instruction reordering */\n\n        .set noreorder\n\n#define clock4 nop;nop;nop;nop\n#define clock3 nop;nop;nop\n#define clock2 nop;nop\n#define clock1 nop\n\n/*\n * The SDRAM clock is output from the output compare unit.\n * This macro synchronizes with that clock so that we are\n * sure to have at least two clock cycles to issue control\n * line changes and access the data bus before the rising\n * edge.\n */\n\n#define sync_clock \\\n        la      $t8, TMR2;      \\\n        li      $v0, 2;         \\\n        lw      $v1, ($t8);     \\\n        bge     $v1, $v0, 1f;   \\\n        nop;                    \\\n        nop;                    \\\n        nop;                    \\\n    1:                          \\\n        nop;\n\n/*\n * Initializes the SDRAM.\n * Should be called once sometime after startup\n * C Prototype:\n * extern __attribute__((far)) void sdram_init();\n * This should only be called from sdram_init_c,\n * which does all of the preliminary setup.\n */\n\nsdram_init:\n\n        /* Initialize address lines */\n        la      $t0, TRISA      /* base of io addresses */\n\n        /* Get ready for the commands we are about to issue. */\n        li      $t4, (1<<SDR_CONTROL_CAS_BIT)\n        li      $t5, (1<<SDR_CONTROL_WE_BIT)\n\n        /* Mode Register: CL:2, BL:8 (0x23) */\n        /*li    $t6, 0x1810*/\n        //li    $t3, (1<<SDR_ADDRESS_LB_A1_BIT)|(1<<SDR_ADDRESS_LB_A0_BIT)\n        //li    $t6, (1<<SDR_ADDRESS_A5_BIT)\n\n        li      $t7, CONTROL_ALL_MASK\n        li      $t8, (1<<SDR_ADDRESS_A10_BIT)   /* A10 */\n\n        sw      $t8, (SDR_ADDRESS_PORT-TRISA) + LAT_OFFSET + SET_OP_OFFSET($t0) /* A10 = 1 for Precharge ALL */\n\n        sync_clock\n\n        .set nomacro\n\n        /* Precharge All */\n        sw      $t7, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + CLR_OP_OFFSET($t0) /* LLLL */\n        sw      $t4, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + SET_OP_OFFSET($t0) /* LLHL */\n        clock2\n\n        /* Auto Refresh 1 */\n        sw      $t4, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + CLR_OP_OFFSET($t0) /* LLLL */\n        sw      $t5, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + SET_OP_OFFSET($t0) /* LLLH */\n        clock2\n\n        /* Auto Refresh 2 */\n        clock4\n\n        /* Auto Refresh 3 */\n        clock4\n\n        /* Auto Refresh 4 */\n        clock4\n\n        /* Auto Refresh 5 */\n        li      $t4, ADDRESS_LB_MASK\n        li      $t5, ADDRESS_MASK\n        clock2\n\n        /* Auto Refresh 6 */\n        sw      $t4, (SDR_ADDRESS_LB_PORT-TRISA) + LAT_OFFSET + CLR_OP_OFFSET($t0)\n        sw      $t5, (SDR_ADDRESS_PORT-TRISA) + LAT_OFFSET + CLR_OP_OFFSET($t0)\n        clock2\n\n        /* Mode Register: CL:2, BL:8 (0x23) */\n\n        /* Auto Refresh 7 */\n        li      $t4, (1<<SDR_ADDRESS_LB_A1_BIT)|(1<<SDR_ADDRESS_LB_A0_BIT)\n        sw      $t4, (SDR_ADDRESS_LB_PORT-TRISA) + LAT_OFFSET + SET_OP_OFFSET($t0)\n        clock2\n\n        /* Auto Refresh 8 */\n        li      $t4, (1<<SDR_ADDRESS_A5_BIT)\n        sw      $t4, (SDR_ADDRESS_PORT-TRISA) + LAT_OFFSET + SET_OP_OFFSET($t0)\n        clock2\n\n        /* Load Mode Register */\n        sw      $t7, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + CLR_OP_OFFSET($t0)\n        clock3\n\n        /* Command Inhibit */\n        sw      $t7, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + SET_OP_OFFSET($t0)\n        clock3\n\n        /* Command Inhibit */\n        clock4\n\n        .set macro\n\n        jr      $ra\n        nop\n\n        /*.end sdram_init*/\n\n\n/*\n * Sends ACTIVE command\n * C Prototype:\n * extern __attribute__((far)) void sdram_active();\n * Responsiblity of caller to output row address before calling this function.\n * See sdram_active_c( unsigned );\n */\nsdram_active:\n\n        la      $t0, TRISA              /* Port Base */\n        li      $t7, (1<<SDR_CONTROL_CS_BIT)|(1<<SDR_CONTROL_RAS_BIT)\n\n        sync_clock\n\n        .set nomacro\n\n        /* Active */\n        sw      $t7, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0)\n        clock3\n\n        /* Command Inhibit */\n        sw      $t7, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0)\n        clock3\n\n        /* Command Inhibit */\n        clock4\n\n        .set macro\n\n        jr      $ra\n        nop\n\n\n/*\n * Sends WRITE command\n * C Prototype:\n * extern __attribute__((far)) void sdram_write(uint64_t val);\n * Each pseudo column contains 8 bytes of data (consists of 8 ram columns)\n * Responsiblity of caller to output pseudo column address before calling this function.\n * See sdram_write_c( unsigned, uint64_t );\n */\n\nsdram_write:\n\n        la      $t0, TRISA              /* Port Base */\n        li      $t4, 0xFF\n        li      $t7, (1<<SDR_CONTROL_CS_BIT) | (1<<SDR_CONTROL_CAS_BIT) | (1<<SDR_CONTROL_WE_BIT)\n\n\n//#ifdef SDRAM_FPGA_DIR_SUPPORT\n//      li      $t3, (1<<SDR_DATA_DIR_BIT)\n//      sw      $t3, (SDR_DATA_DIR_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0)\n//#endif\n\n        /* Set data lines */\n        srl     $t5, $a0, 24\n        sb      $t5, (SDR_DATA_PORT-TRISA) + LAT_OFFSET + NOP_OP_OFFSET($t0)\n\n        sync_clock\n\n        .set nomacro\n\n        /* Write */\n        sw      $t7, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* LHLL */\n        sw      $t4, (SDR_DATA_PORT-TRISA) + TRIS_OFFSET + CLR_OP_OFFSET($t0)   /* 1 - enable data lines */\n        srl     $t5, $a0, 16\n        clock1\n\n        /* Command Inhibit */\n        sw      $t7, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* HHHH */\n        sb      $t5, (SDR_DATA_PORT-TRISA) + LAT_OFFSET + NOP_OP_OFFSET($t0)    /* 2 */\n        srl     $t5, $a0, 8\n        clock1\n\n        /* Command Inhibit */\n        sb      $t5, (SDR_DATA_PORT-TRISA) + LAT_OFFSET + NOP_OP_OFFSET($t0)    /* 3 */\n        clock3\n\n        /* Command Inhibit */\n        sb      $a0, (SDR_DATA_PORT-TRISA) + LAT_OFFSET + NOP_OP_OFFSET($t0)    /* 4 */\n        srl     $t5, $a1, 24\n        clock2\n\n        /* Command Inhibit */\n        sb      $t5, (SDR_DATA_PORT-TRISA) + LAT_OFFSET + NOP_OP_OFFSET($t0)    /* 5 */\n        srl     $t5, $a1, 16\n        clock2\n\n        /* Command Inhibit */\n        sb      $t5, (SDR_DATA_PORT-TRISA) + LAT_OFFSET + NOP_OP_OFFSET($t0)    /* 6 */\n        srl     $t5, $a1, 8\n        clock2\n\n        /* Command Inhibit */\n        sb      $t5, (SDR_DATA_PORT-TRISA) + LAT_OFFSET + NOP_OP_OFFSET($t0)    /* 7 */\n        clock3\n\n        /* Command Inhibit */\n        sb      $a1, (SDR_DATA_PORT-TRISA) + LAT_OFFSET + NOP_OP_OFFSET($t0)    /* 8 */\n        clock3\n\n        sw      $t4, (SDR_DATA_PORT-TRISA) + LAT_OFFSET + CLR_OP_OFFSET($t0)   /* PIC32 errata - thanks Pito. */\n        sw      $t4, (SDR_DATA_PORT-TRISA) + TRIS_OFFSET + SET_OP_OFFSET($t0)   /* Data lines input again */\n\n        .set macro\n\n//#ifdef SDRAM_FPGA_DIR_SUPPORT\n//      clock4\n//      li      $t3, (1<<SDR_DATA_DIR_BIT)\n//      sw      $t3, (SDR_DATA_DIR_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0)\n//#endif\n\n\n        jr      $ra\n        nop\n\n\n/*\n * Sends READ command\n * C Prototype:\n * extern __attribute__((far)) uint64_t sdram_read();\n * Each pseudo column contains 8 bytes of data (consists of 8 ram columns)\n * Responsiblity of caller to output pseudo column address before calling this function.\n * See sdram_read_c()\n */\nsdram_read:\n\n        la      $t0, TRISA              /* Port Base */\n        li      $t7, (1<<SDR_CONTROL_CS_BIT) | (1<<SDR_CONTROL_CAS_BIT)\n\n        sync_clock\n\n        .set nomacro\n\n        /* Read */\n        sw      $t7, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* LHLH */\n        clock3\n\n        /* Command Inhibit */\n        sw      $t7, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* HHHH */\n        clock3\n\n        /* Command Inhibit */\n        clock3\n        lbu     $v0, (SDR_DATA_PORT-TRISA) + PORT_OFFSET + NOP_OP_OFFSET($t0)       /* 1 */\n\n        /* Command Inhibit */\n        clock3\n        lbu     $t5, (SDR_DATA_PORT-TRISA) + PORT_OFFSET + NOP_OP_OFFSET($t0)       /* 2 */\n\n        /* Command Inhibit */\n        sll     $v0, $v0, 8\n        or      $v0, $v0, $t5\n        clock1\n        lbu     $t5, (SDR_DATA_PORT-TRISA) + PORT_OFFSET + NOP_OP_OFFSET($t0)       /* 3 */\n\n        /* Command Inhibit */\n        sll     $v0, $v0, 8\n        or      $v0, $v0, $t5\n        clock1\n        lbu     $t5, (SDR_DATA_PORT-TRISA) + PORT_OFFSET + NOP_OP_OFFSET($t0)       /* 4 */\n\n        /* Command Inhibit */\n        sll     $v0, $v0, 8\n        or      $v0, $v0, $t5\n        clock1\n        lbu     $v1, (SDR_DATA_PORT-TRISA) + PORT_OFFSET + NOP_OP_OFFSET($t0)       /* 5 */\n\n        /* Command Inhibit */\n        clock3\n        lbu     $t5, (SDR_DATA_PORT-TRISA) + PORT_OFFSET + NOP_OP_OFFSET($t0)       /* 6 */\n\n        /* Command Inhibit */\n        sll     $v1, $v1, 8\n        or      $v1, $v1, $t5\n        clock1\n        lbu     $t5, (SDR_DATA_PORT-TRISA) + PORT_OFFSET + NOP_OP_OFFSET($t0)       /* 7 */\n\n        /* Command Inhibit */\n        sll     $v1, $v1, 8\n        or      $v1, $v1, $t5\n        clock1\n        lbu     $t5, (SDR_DATA_PORT-TRISA) + PORT_OFFSET + NOP_OP_OFFSET($t0)       /* 8 */\n\n        /* Command Inhibit */\n        sll     $v1, $v1, 8\n        or      $v1, $v1, $t5\n\n        .set macro\n\n        jr      $ra\n        nop\n\n\n/*\n * Sends PRECHARGE ALL command\n * C Prototype:\n * extern __attribute__((far)) void sdram_precharge_all(void);\n */\nsdram_precharge_all:\n\n        la      $t0, TRISA                      /* Port Base */\n        li      $t3, (1<<SDR_ADDRESS_A10_BIT)   /* A10 */\n        li      $t4, (1<<SDR_CONTROL_CS_BIT) | (1<<SDR_CONTROL_RAS_BIT) | (1<<SDR_CONTROL_WE_BIT)\n\n        sw      $t3, (SDR_ADDRESS_PORT-TRISA) + LAT_OFFSET + SET_OP_OFFSET($t0) /* A10 = 1 for Precharge ALL */\n\n        sync_clock\n\n        .set nomacro\n\n        /* Precharge All */\n        sw      $t4, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* LLHL */\n        clock3\n\n        /* Command Inhibit */\n        sw      $t4, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* LLLL */\n        clock3\n\n        .set macro\n\n        jr      $ra\n        nop\n\n\n/*\n * Sends PRECHARGE command\n * C Prototype:\n * extern __attribute__((far)) void sdram_precharge(void);\n */\nsdram_precharge:\n\n        la      $t0, TRISA                      /* Port Base */\n        li      $t3, (1<<SDR_ADDRESS_A10_BIT)   /* A10 */\n        li      $t4, (1<<SDR_CONTROL_CS_BIT) | (1<<SDR_CONTROL_RAS_BIT) | (1<<SDR_CONTROL_WE_BIT)\n\n        sw      $t3, (SDR_ADDRESS_PORT-TRISA) + LAT_OFFSET + CLR_OP_OFFSET($t0) /* A10 = 0 for Precharge */\n\n        sync_clock\n\n        .set nomacro\n\n        /* Precharge All */\n        sw      $t4, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* LLHL */\n        clock3\n\n        /* Command Inhibit */\n        sw      $t4, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* LLLL */\n        clock3\n\n        .set macro\n\n        jr      $ra\n        nop\n\n\n/*\n * Sends AUTO REFRESH command\n * All banks must be in PRECHARGEd state\n * C Prototype:\n * extern __attribute__((far)) void sdram_auto_refresh(void);\n */\nsdram_auto_refresh:\n\n        la      $t0, TRISA              /* Port Base */\n        li      $t4, (1<<SDR_CONTROL_CS_BIT)|(1<<SDR_CONTROL_RAS_BIT)|(1<<SDR_CONTROL_CAS_BIT)\n\n        sync_clock\n\n        .set nomacro\n\n        /* Auto Refresh */\n        sw      $t4, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* LLLH */\n        clock3\n\n        /* Command Inhibit */\n        sw      $t4, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* LLLL */\n        clock3\n\n        .set macro\n\n        jr      $ra\n        nop\n\n/*\n * Puts the SDRAM into the self refresh mode.\n * SDRAM retains data in this state.\n * C Prototype:\n * extern __attribute__((far)) void sdram_sleep(void);\n */\nsdram_sleep:\n\n        la      $t0, TRISA              /* Port Base */\n        li      $t1, (1<<SDR_CKE_BIT)\n        li      $t4, (1<<SDR_CONTROL_CS_BIT)|(1<<SDR_CONTROL_RAS_BIT)|(1<<SDR_CONTROL_CAS_BIT)\n\n        sync_clock\n\n        .set nomacro\n\n        /* Auto Refresh */\n        sw      $t4, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* LLLH */\n        sw      $t1, (SDR_CKE_PORT-TRISA) + LAT_OFFSET + CLR_OP_OFFSET($t0)     /* CKE low */\n        clock2\n\n        /* Command Inhibit */\n        sw      $t4, (SDR_CONTROL_PORT-TRISA) + LAT_OFFSET + INV_OP_OFFSET($t0) /* LLLL */\n        clock3\n\n        .set macro\n\n        jr      $ra\n        nop\n\n/*\n * Takes the SDRAM out of the self refresh mode.\n * Parameters: none\n * C Prototype:\n * extern __attribute__((far)) void sdram_wake(void);\n */\nsdram_wake:\n\n        la      $t0, TRISA              /* Port Base */\n        li      $t1, (1<<SDR_CKE_BIT)\n\n        sync_clock\n\n        .set nomacro\n\n        /* Command Inhibit */\n        sw      $t1, (SDR_CKE_PORT-TRISA) + LAT_OFFSET + SET_OP_OFFSET($t0) /* CKE low */\n        clock3\n\n        /* Command Inhibit */\n        clock4\n\n        /* Command Inhibit */\n        clock4\n\n        .set macro\n\n        jr      $ra\n        nop\n"
  },
  {
    "path": "sys/arch/pic32/dev/sdram.h",
    "content": "/*\n * SDRAM Access Routines for PIC32.\n *\n * Retromaster - 10.05.2010\n *\n * This file is in the public domain. You can use, modify, and distribute the source code\n * and executable programs based on the source code. This file is provided \"as is\" and\n * without any express or implied warranties whatsoever. Use at your own risk!\n *\n * Changes by jmcgee for inclusion in the retrobsd project.\n */\n\n#ifndef SDRAM_H\n#define SDRAM_H\n\n#ifdef KERNEL\n\ntypedef unsigned short uint16_t;\ntypedef unsigned char uint8_t;\ntypedef unsigned long long uint64_t;\n\nextern __attribute__((far)) void sdram_init();\nextern __attribute__((far)) void sdram_active();\nextern __attribute__((far)) void sdram_write(uint64_t val);\nextern __attribute__((far)) uint64_t sdram_read();\nextern __attribute__((far)) void sdram_auto_refresh(void);\nextern __attribute__((far)) void sdram_precharge(void);\nextern __attribute__((far)) void sdram_precharge_all(void);\nextern __attribute__((far)) void sdram_sleep(void);\nextern __attribute__((far)) void sdram_wake(void);\n\n#endif\n\n#endif\n"
  },
  {
    "path": "sys/arch/pic32/dev/sdramp.c",
    "content": "/*\n * Driver for external SDRAM-based swap device.\n *\n * See sdram.S for information on interface to sdram\n *\n * This code could use a bit of optimization.\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/buf.h>\n#include <sys/errno.h>\n#include <sys/dk.h>\n#include <sys/ioctl.h>\n#include <sys/disk.h>\n#include <sys/config.h>\n\n#include <pic32/dev/sdram.h>\n#include <pic32/dev/sdramp.h>\n\n/*\n * See rd_sdramp_config.h for sdramp port/pin configuration\n */\n#include <pic32/dev/sdramp_config.h>\n\nint sdramp_dkindex = -1;                /* Statistics slot number */\n\n/*\n * physical specs of SDRAM chip\n */\n#define RAM_COLS                512\n\n#if SDR_ADDRESS_LINES == 13\n#define RAM_ROWS                (4096*2)\n#elif SDR_ADDRESS_LINES == 12\n#define RAM_ROWS                4096\n#elif SDR_ADDRESS_LINES == 11\n#define RAM_ROWS                2048\n#else\n#error Invalid Configuration - SDR_ADDRESS_LINES\n#endif\n\n#define RAM_BANKS               4\n\n/*\n * RAM_BURST_COUNT MUST be match the number of bytes\n * read/written by each call to sdram_read/sdram_write\n */\n#define RAM_BURST_COUNT         8\n\n/*\n * CHUNK_SIZE number of bytes in each \"chunk\"\n */\n#define CHUNK_SIZE              32\n\n#define RAM_BURST_GROUP_COUNT   4\n\n#define BLOCKS_PER_ROW          (RAM_COLS / CHUNK_SIZE)\n\n/*\n * Size of the whole disk in kbytes.\n */\n#define SDR_TOTAL_KBYTES    ((1<<SDR_ADDRESS_LINES) / 2 * 4 * SDR_DATA_BYTES)\n\nstatic char swaptemp[CHUNK_SIZE];\n\n/*\n * Used to specify partition table for ramdisk from Makefile\n */\n#define RAMDISK_PARTSPEC(n,t,s,l) \\\n    m->partitions[n].type = t; \\\n    m->partitions[n].lbastart = s; \\\n    m->partitions[n].lbalength = l;\n\n// FIXME - FOLLOWING shared with gpio.c - needs to be made common\n\nstruct ocreg {\n    volatile unsigned con;      /* ? */\n    volatile unsigned conclr;\n    volatile unsigned conset;\n    volatile unsigned coninv;\n    volatile unsigned r;        /* ? */\n    volatile unsigned rclr;\n    volatile unsigned rset;\n    volatile unsigned rinv;\n    volatile unsigned rs;       /* ? */\n    volatile unsigned rsclr;\n    volatile unsigned rsset;\n    volatile unsigned rsinv;\n};\n\nstatic void sdram_bank_c(unsigned bank)\n{\n    // In order to keep unnecessary noise from occuring on the\n    // address lines, don't use the hardware set/clear functions.\n    // Rather, read the latch value, change it, and write it back.\n\n    struct gpioreg * bankport = (struct gpioreg *)&SDR_BANK_PORT;\n    unsigned v = bankport->lat;\n    v &= ~(BANK_BITMASK << SDR_BANK_0_BIT);\n    v |= (bank & BANK_BITMASK) << SDR_BANK_0_BIT;\n    bankport->lat = v;\n}\n\nstatic void sdram_upperlowerbyte(unsigned bit)\n{\n    struct gpioreg * dqm_port = (struct gpioreg *)&SDR_DQM_PORT;\n#ifdef SDR_DQM_UDQM_BIT\n\n    if (bit == 0) {\n        dqm_port->latset = (1<<SDR_DQM_UDQM_BIT);\n        dqm_port->latclr = (1<<SDR_DQM_LDQM_BIT);\n    } else {\n        dqm_port->latset = (1<<SDR_DQM_LDQM_BIT);\n        dqm_port->latclr = (1<<SDR_DQM_UDQM_BIT);\n    }\n\n//  dqm_port->latset = (1<<SDR_DQM_UDQM_BIT);\n//  dqm_port->latclr = (1<<SDR_DQM_LDQM_BIT);\n#else\n    dqm_port->latclr = (1<<SDR_DQM_LDQM_BIT);\n#endif\n}\n\nstatic void sdram_init_c()\n{\n    struct gpioreg * bank_port = (struct gpioreg *)&SDR_BANK_PORT;\n    struct gpioreg * dqm_port = (struct gpioreg *)&SDR_DQM_PORT;\n    struct gpioreg * address_lb_port = (struct gpioreg *)&SDR_ADDRESS_LB_PORT;\n    struct gpioreg * address_port = (struct gpioreg *)&SDR_ADDRESS_PORT;\n    struct gpioreg * data_port = (struct gpioreg *)&SDR_DATA_PORT;\n    struct gpioreg * control_port = (struct gpioreg *)&SDR_CONTROL_PORT;\n    struct gpioreg * cke_port = (struct gpioreg *)&SDR_CKE_PORT;\n    struct ocreg * ocr_reg = (struct ocreg *)&SDR_OCR;\n\n    // make f13 a ground pin?\n    address_lb_port->latclr = (1<<13) | (1<<8);\n    address_lb_port->trisclr = (1<<13) | (1<<8);\n\n    address_lb_port->trisclr = ADDRESS_LB_MASK;\n    address_port->trisclr = ADDRESS_MASK;\n\n    /* AD1PCFGSET = 0xFFFF; */\n    bank_port->trisclr = BANK_ALL_MASK;\n\n#ifdef SDR_DQM_UDQM_BIT\n    dqm_port->latset = (1<<SDR_DQM_UDQM_BIT);\n#endif\n    dqm_port->latclr = (1<<SDR_DQM_LDQM_BIT);\n    dqm_port->trisclr = SDR_DQM_MASK;\n\n    /* All address lines low */\n    address_lb_port->latclr = ADDRESS_LB_MASK;\n    address_port->latclr = ADDRESS_MASK;\n\n    bank_port->latclr = BANK_ALL_MASK;\n\n    /* Initialize data lines */\n    data_port->trisset = 0xff;\n\n    /* Initialize SDRAM control lines */\n    control_port->trisclr = CONTROL_ALL_MASK;\n\n    /* Command Inhibit */\n    control_port->latset = CONTROL_ALL_MASK;\n\n    /* Initialize CKE line */\n    cke_port->trisclr = (1<<SDR_CKE_BIT);\n\n    /* CKE low */\n    cke_port->latclr = (1<<SDR_CKE_BIT);\n\n#ifdef SDRAM_FPGA_DIR_SUPPORT\n    struct gpioreg * data_dir_port = (struct gpioreg *)&SDR_DATA_DIR_PORT;\n    data_dir_port->latset = (1<<SDR_DATA_DIR_BIT);\n    data_dir_port->trisclr = (1<<SDR_DATA_DIR_BIT);\n#endif\n\n    /* SDRAM clock output */\n\n    /* Initialize Timer2 */\n    T2CON = 0;\n    TMR2 = 0;\n    PR2 = 3;\n    T2CONSET = 0x8000;\n\n    /* Initialize OC device */\n    ocr_reg->con = 0;\n    ocr_reg->rs = 1;\n    ocr_reg->r = 3;\n    ocr_reg->con = 0x8005;\n\n    /* Clock output starts here */\n\n    /* SD-RAM initialization delay */\n    unsigned cc_start, cc_now;\n    asm volatile(\"mfc0 %0, $9\" : \"=r\" (cc_start));\n    do {\n        asm volatile(\"mfc0 %0, $9\" : \"=r\" (cc_now));\n    } while (cc_now - cc_start < 500);\n\n    /* CKE high */\n    cke_port->latset = (1<<SDR_CKE_BIT);\n\n    /* Delay some more */\n\n    asm volatile(\"mfc0 %0, $9\" : \"=r\" (cc_start));\n    do {\n        asm volatile(\"mfc0 %0, $9\" : \"=r\" (cc_now));\n    } while (cc_now - cc_start < 3000);\n\n    /* finish up in assembly routine */\n    sdram_init();\n}\n\nstatic void sdram_output_addr(unsigned addr)\n{\n    struct gpioreg * address_lb_port = (struct gpioreg *)&SDR_ADDRESS_LB_PORT;\n    struct gpioreg * address_port = (struct gpioreg *)&SDR_ADDRESS_PORT;\n    address_lb_port->lat = (address_lb_port->lat & ~ADDRESS_LB_MASK) | ((addr & 0x7) << SDR_ADDRESS_LB_A0_BIT);\n    address_port->lat = (address_port->lat & ~ADDRESS_MASK)\n        | ((addr & (ADDRESS_MASK<<(3-SDR_ADDRESS_A3_BIT))) >> (3-SDR_ADDRESS_A3_BIT));\n}\n\nstatic void sdram_active_c(unsigned row_address)\n{\n    sdram_output_addr(row_address);\n    sdram_active();\n}\n\nstatic void sdram_write_c(uint16_t coladdr, uint64_t val)\n{\n    sdram_output_addr(coladdr);\n    sdram_write(val);\n}\n\nstatic uint64_t sdram_read_c(uint16_t coladdr)\n{\n    sdram_output_addr(coladdr);\n    return sdram_read();\n}\n\nstatic void\nread_chunk_from_sdram(uint64_t* dest, unsigned int blockNumber)\n{\n    int startColumn = (blockNumber & (BLOCKS_PER_ROW - 1)) * CHUNK_SIZE; // / RAM_BURST_COUNT;\n    int rowAndBank = blockNumber / BLOCKS_PER_ROW;\n    int row = rowAndBank & (RAM_ROWS - 1);\n    int bank = rowAndBank / RAM_ROWS;\n    int sbank = bank / 4;\n    bank  = bank & 0b011;\n    int col = startColumn;\n\n    sdram_upperlowerbyte(sbank);\n\n    while (col < startColumn + CHUNK_SIZE/*/RAM_BURST_COUNT*/) {\n        int x = mips_intr_disable();\n        sdram_wake();\n        sdram_bank_c(bank);\n        sdram_active_c(row);\n        int i;\n        for (i = 0; i < RAM_BURST_GROUP_COUNT; i++) {\n            *dest++ = sdram_read_c(col);\n            col += RAM_BURST_COUNT;\n        }\n        sdram_precharge();\n        sdram_precharge_all();\n        sdram_sleep();\n\n        mips_intr_restore (x);\n\n        asm volatile (\"nop\");\n    }\n}\n\nstatic void\nwrite_chunk_to_sdram(uint64_t* src, unsigned int blockNumber)\n{\n    int startColumn = (blockNumber & (BLOCKS_PER_ROW - 1)) * CHUNK_SIZE; /// RAM_BURST_COUNT;\n    int rowAndBank = blockNumber / BLOCKS_PER_ROW;\n    int row = rowAndBank & (RAM_ROWS - 1);\n    int bank = rowAndBank / RAM_ROWS;\n    int sbank = bank / 4;\n    bank  = bank & 0b011;\n\n    sdram_upperlowerbyte(sbank);\n\n    int col = startColumn;\n    while (col < startColumn + CHUNK_SIZE /*/RAM_BURST_COUNT*/) {\n        int x = mips_intr_disable();\n\n        sdram_wake();\n        sdram_bank_c(bank);\n        sdram_active_c(row);\n        int i;\n        for (i = 0; i < RAM_BURST_GROUP_COUNT; i++) {\n            sdram_write_c(col, *src++);\n            col += RAM_BURST_COUNT;\n        }\n        sdram_precharge();\n        sdram_precharge_all();\n        sdram_sleep();\n\n        mips_intr_restore (x);\n\n        asm volatile (\"nop\");\n    }\n}\n\n/*\n * Read a block of data.\n */\nstatic int\nsdramp_read(unsigned blockno, char* data, unsigned nbytes)\n{\n    blockno = blockno * (DEV_BSIZE/CHUNK_SIZE);\n\n    while (nbytes >= CHUNK_SIZE) {\n        read_chunk_from_sdram((uint64_t*) swaptemp, blockno);\n        bcopy(swaptemp, data, CHUNK_SIZE);\n        data += CHUNK_SIZE;\n        blockno += 1;\n        nbytes -= CHUNK_SIZE;\n    }\n\n    if (nbytes) {\n        read_chunk_from_sdram((uint64_t*) swaptemp, blockno);\n        bcopy(swaptemp, data, nbytes);\n    }\n    return 1;\n}\n\n/*\n * Write a block of data.\n */\nstatic int\nsdramp_write (unsigned blockno, char *data, unsigned nbytes)\n{\n    blockno = blockno * (DEV_BSIZE/CHUNK_SIZE);\n\n    while (nbytes >= CHUNK_SIZE) {\n        bcopy(data, swaptemp, CHUNK_SIZE);\n        int x = mips_intr_disable();\n        write_chunk_to_sdram((uint64_t*) swaptemp, blockno);\n        mips_intr_restore(x);\n        data += CHUNK_SIZE;\n        blockno += 1;\n        nbytes -= CHUNK_SIZE;\n    }\n    if (nbytes) {\n        read_chunk_from_sdram((uint64_t*) swaptemp, blockno);\n        bcopy(data, swaptemp, nbytes);\n        int x = mips_intr_disable();\n        write_chunk_to_sdram((uint64_t*) swaptemp, blockno);\n        mips_intr_restore(x);\n    }\n    return 1;\n}\n\nint sdramp_open(dev_t dev, int flag, int mode)\n{\n    return 0;\n}\n\nint sdramp_close(dev_t dev, int flag, int mode)\n{\n    return 0;\n}\n\n/*\n * Return a size of partition in kbytes.\n * The memory is divided into two partitions: A and B.\n * Size of partition B is specified in the kernel config file\n * as option SDR_SWAP_KBYTES.\n */\ndaddr_t sdramp_size(dev_t dev)\n{\n    switch (minor(dev)) {\n    case 0:\n        /* Whole disk. */\n        return SDR_TOTAL_KBYTES;\n    case 1:\n        /* Partition A: filesystem. */\n        return SDR_TOTAL_KBYTES - SDR_SWAP_KBYTES;\n    case 2:\n    default:\n        /* Partition B: swap space. */\n        return SDR_SWAP_KBYTES;\n    }\n}\n\nvoid sdramp_strategy(struct buf *bp)\n{\n    int offset = bp->b_blkno;\n    long nblk = btod(bp->b_bcount);\n    int part_offset, part_size, s;\n\n    /* Compute partition size and offset. */\n    part_size = sdramp_size(bp->b_dev);\n    if (minor(bp->b_dev) < 2) {\n        /* Partition A or a whole disk. */\n        part_offset = 0;\n    } else {\n        /* Partition B: swap space. */\n        part_offset = SDR_TOTAL_KBYTES - part_size;\n    }\n\n    /*\n     * Determine the size of the transfer, and make sure it is\n     * within the boundaries of the partition.\n     */\n    offset += part_offset;\n    if (bp->b_blkno + nblk > part_size) {\n        /* if exactly at end of partition, return an EOF */\n        if (bp->b_blkno == part_size) {\n            bp->b_resid = bp->b_bcount;\n            biodone(bp);\n            return;\n        }\n        /* or truncate if part of it fits */\n        nblk = part_size - bp->b_blkno;\n        if (nblk <= 0) {\n            bp->b_error = EINVAL;\n            bp->b_flags |= B_ERROR;\n            biodone(bp);\n            return;\n        }\n        bp->b_bcount = nblk << DEV_BSHIFT;\n    }\n\n    if (bp->b_dev == swapdev) {\n        led_control(LED_SWAP, 1);\n    } else {\n        led_control(LED_DISK, 1);\n    }\n\n    s = splbio();\n#ifdef UCB_METER\n    if (sdramp_dkindex >= 0) {\n        dk_busy |= 1 << sdramp_dkindex;\n        dk_xfer[sdramp_dkindex]++;\n        dk_bytes[sdramp_dkindex] += bp->b_bcount;\n    }\n#endif\n\n    if (bp->b_flags & B_READ) {\n        sdramp_read(offset, bp->b_addr, bp->b_bcount);\n    } else {\n        sdramp_write(offset, bp->b_addr, bp->b_bcount);\n    }\n\n    biodone(bp);\n    if (bp->b_dev == swapdev) {\n        led_control(LED_SWAP, 0);\n    } else {\n        led_control(LED_DISK, 0);\n    }\n#ifdef UCB_METER\n    if (sdramp_dkindex >= 0)\n        dk_busy &= ~(1 << sdramp_dkindex);\n#endif\n    splx(s);\n}\n\nint sdramp_ioctl(dev_t dev, u_int cmd, caddr_t addr, int flag)\n{\n    int error = 0;\n\n    switch (cmd) {\n\n    case DIOCGETMEDIASIZE:\n        /* Get disk size in kbytes. */\n        *(int*) addr = sdramp_size(dev);\n        break;\n\n    default:\n        error = EINVAL;\n        break;\n    }\n    return error;\n}\n\n/*\n * Test to see if device is present.\n * Return true if found and initialized ok.\n */\nstatic int\nsdrampprobe(config)\n    struct conf_device *config;\n{\n    /* Only one device unit is supported. */\n    if (config->dev_unit != 0)\n        return 0;\n\n    printf(\"dr0: total %u kbytes, swap space %u kbytes\\n\",\n        SDR_TOTAL_KBYTES, SDR_SWAP_KBYTES);\n\n    int x = mips_intr_disable();\n    sdram_init_c();\n    mips_intr_restore(x);\n\n#ifdef UCB_METER\n    dk_alloc(&sdramp_dkindex, 1, \"dr0\");\n#endif\n    return 1;\n}\n\nstruct driver sdrampdriver = {\n    \"sdramp\", sdrampprobe,\n};\n"
  },
  {
    "path": "sys/arch/pic32/dev/sdramp.h",
    "content": "#ifndef _SDRAMP_H\n#define _SDRAMP_H\n\n#ifdef KERNEL\nextern int sdramp_open(dev_t dev, int flag, int mode);\nextern int sdramp_close(dev_t dev, int flag, int mode);\nextern daddr_t sdramp_size(dev_t dev);\nextern void sdramp_strategy(struct buf *bp);\nextern int sdramp_ioctl (dev_t dev, u_int cmd, caddr_t addr, int flag);\n#endif\n\n#endif\n"
  },
  {
    "path": "sys/arch/pic32/dev/sdramp_config.h",
    "content": "#ifndef RD_SDRAMP_CONFIG_H_\n\n#include <machine/pic32mx.h>\n\n/* TODO: better support for different sized sdram chips, 16 bit support */\n\n/*\n * Number of physical address lines on sdram chip\n * one of 11, 12, 13\n */\n#define SDR_ADDRESS_LINES       12\n\n/*\n * Ram data width in bytes - 1 (8 bit) or 2 (16 bit)\n *\n * NOT USED YET\n */\n#define SDR_DATA_BYTES          2\n\n/*\n * Upper/Lower Byte selection\n */\n#define SDR_DQM_PORT TRISA\n\n#if SDR_DATA_BYTES == 2\n#define SDR_DQM_UDQM_BIT        6\n#endif\n#define SDR_DQM_LDQM_BIT        7\n\n/*\n * Bank Selection\n * BA0 is connected to SDR_BANK_0_BIT\n * BA1 is connected to SDR_BANK_0_BIT + 1\n *\n * So, if SDR_BANK_0_BIT is 4, then bit 5\n * must be connected to BA1.\n */\n\n#define SDR_BANK_PORT           TRISG\n#define SDR_BANK_0_BIT          0\n\n/*\n * Clock Enable\n *\n * Connect to CKE on sdram\n */\n#define SDR_CKE_PORT            TRISD\n#define SDR_CKE_BIT             11\n\n/*\n * Control Lines\n *\n * Connect to /WE, /CAS, /CS and /RAS pins on sdram\n */\n#define SDR_CONTROL_PORT        TRISG\n#define SDR_CONTROL_WE_BIT      15\n#define SDR_CONTROL_CAS_BIT     13\n#define SDR_CONTROL_CS_BIT      14\n#define SDR_CONTROL_RAS_BIT     12\n\n/*\n * Address Lines\n *\n * At present, the port can be changed, but\n * changing the address line bits is unsupported.\n */\n\n#define SDR_ADDRESS_LB_PORT     TRISF\n#define SDR_ADDRESS_PORT        TRISD\n\n/***** WARNING - DO NOT CHANGE WITHOUT ALSO CHANGING CODE TO MATCH *****/\n#define SDR_ADDRESS_LB_A0_BIT   0\n#define SDR_ADDRESS_LB_A1_BIT   1\n#define SDR_ADDRESS_LB_A2_BIT   2\n\n#define SDR_ADDRESS_A3_BIT      1\n#define SDR_ADDRESS_A4_BIT      2\n#define SDR_ADDRESS_A5_BIT      3\n#define SDR_ADDRESS_A6_BIT      4\n#define SDR_ADDRESS_A7_BIT      5\n#define SDR_ADDRESS_A8_BIT      6\n#define SDR_ADDRESS_A9_BIT      7\n\n#if SDR_ADDRESS_LINES >= 11\n#define SDR_ADDRESS_A10_BIT     8\n#endif\n\n#if SDR_ADDRESS_LINES >= 12\n#define SDR_ADDRESS_A11_BIT     9\n#endif\n\n#if SDR_ADDRESS_LINES >= 13\n#define SDR_ADDRESS_A12_BIT     10\n#endif\n\n/***** END WARNING *****/\n\n/*\n * Data Lines\n *\n * The low 8 bits (bits 0-7) must be used\n * and connected to the data lines on the sdram.\n * The specific order in which the 8 pins are\n * connected to the data pins of the sdram is\n * not significant, unless you wish for a neat\n * and tidy design that is easy connect to a\n * logic analyzer for debugging purposes.\n */\n\n#define SDR_DATA_PORT           TRISE\n\n/*\n * Output Compare\n *\n * Currently supporting OC1CON or OC4CON\n * Timer2 is used in all cases.\n * The appropriate pin should be connected to CLK on the sdram.\n * OC1CON - RD0\n * OC4CON - RD3\n */\n\n#define SDR_OCR                 OC1CON\n\n/*\n * Additional sdram connections\n *\n * Power and ground as appropriate.\n */\n\n\n/***************************************************************/\n\n/*\n * Anthing following should not normally need to be modified.\n * There are here in order to share definitions between C and ASM.\n */\n\n#ifdef SDR_ADDRESS_A10_BIT\n#define SDR_ADDRESS_A10_BITMASK (1<<SDR_ADDRESS_A10_BIT)\n#else\n#define SDR_ADDRESS_A10_BITMASK 0\n#endif\n\n#ifdef SDR_ADDRESS_A11_BIT\n#define SDR_ADDRESS_A11_BITMASK (1<<SDR_ADDRESS_A11_BIT)\n#else\n#define SDR_ADDRESS_A11_BITMASK 0\n#endif\n\n#ifdef SDR_ADDRESS_A12_BIT\n#define SDR_ADDRESS_A12_BITMASK (1<<SDR_ADDRESS_A12_BIT)\n#else\n#define SDR_ADDRESS_A12_BITMASK 0\n#endif\n\n#define ADDRESS_LB_MASK                                                                 \\\n        ((1<<SDR_ADDRESS_LB_A0_BIT)|(1<<SDR_ADDRESS_LB_A1_BIT)|(1<<SDR_ADDRESS_LB_A2_BIT))\n\n#define ADDRESS_MASK                                                                    \\\n        ((1<<SDR_ADDRESS_A3_BIT)|(1<<SDR_ADDRESS_A4_BIT)|(1<<SDR_ADDRESS_A5_BIT)|       \\\n         (1<<SDR_ADDRESS_A6_BIT)|(1<<SDR_ADDRESS_A7_BIT)|(1<<SDR_ADDRESS_A8_BIT)|       \\\n         (1<<SDR_ADDRESS_A9_BIT)| \\\n         SDR_ADDRESS_A10_BITMASK| \\\n         SDR_ADDRESS_A11_BITMASK| \\\n         SDR_ADDRESS_A12_BITMASK)\n\n#define CONTROL_ALL_MASK                                        \\\n        ((1<<SDR_CONTROL_CS_BIT)|(1<<SDR_CONTROL_RAS_BIT)|      \\\n         (1<<SDR_CONTROL_CAS_BIT)|(1<<SDR_CONTROL_WE_BIT))\n\n#define BANK_BITMASK 3\n#define BANK_ALL_MASK (BANK_BITMASK << SDR_BANK_0_BIT)\n\n#ifdef SDR_DQM_UDQM_BIT\n#define SDR_DQM_MASK \\\n        ((1<<SDR_DQM_LDQM_BIT)|(1<<SDR_DQM_UDQM_BIT))\n#else\n#define SDR_DQM_MASK \\\n        (1<<SDR_DQM_LDQM_BIT)\n#endif\n\n#endif\n"
  },
  {
    "path": "sys/arch/pic32/dev/skel.c",
    "content": "/*\n * Skeleton for a character device driver.\n *\n * Copyright (C) 2015 Serge Vakulenko\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/param.h>\n#include <sys/conf.h>\n#include <sys/user.h>\n#include <sys/ioctl.h>\n#include <sys/systm.h>\n#include <sys/uio.h>\n#include <sys/skel.h>\n\n#define NSKEL   5       /* Ports 1...5 */\n\n/*\n * To enable debug output, uncomment the first line.\n */\n#define PRINTDBG printf\n#ifndef PRINTDBG\n#   define PRINTDBG(...) /*empty*/\n#endif\n\n/*\n * Open /dev/skel# device.\n */\nint skeldev_open(dev_t dev, int flag, int mode)\n{\n    int unit = minor(dev);\n\n    if (unit >= NSKEL)\n        return ENXIO;\n\n    if (u.u_uid != 0)\n        return EPERM;\n\n    // TODO: initialize the port.\n    PRINTDBG(\"--- %s() unit=%u, flag=%d, mode=%d\\n\", __func__, unit, flag, mode);\n    return 0;\n}\n\n/*\n * Close device.\n */\nint skeldev_close(dev_t dev, int flag, int mode)\n{\n    int unit = minor(dev);\n\n    if (u.u_uid != 0)\n        return EPERM;\n\n    // TODO: disable the port.\n    PRINTDBG(\"--- %s() unit=%u, flag=%d, mode=%d\\n\", __func__, unit, flag, mode);\n    return 0;\n}\n\n/*\n * Read data from device.\n */\nint skeldev_read(dev_t dev, struct uio *uio, int flag)\n{\n    int unit = minor(dev);\n\n    // TODO: read data from port to user program.\n    PRINTDBG(\"--- %s() unit=%u, flag=%d\\n\", __func__, unit, flag);\n    return 0;\n}\n\n/*\n * Write data to device.\n */\nint skeldev_write(dev_t dev, struct uio *uio, int flag)\n{\n    int unit = minor(dev);\n\n    // TODO: write data from user program to port.\n    PRINTDBG(\"--- %s() unit=%u, flag=%d\\n\", __func__, unit, flag);\n    return 0;\n}\n\n/*\n * Control operations:\n *      SKELCTL_SETMODE - set device mode\n *      SKELCTL_IO(n)   - perform R/W transaction of n bytes\n */\nint skeldev_ioctl(dev_t dev, u_int cmd, caddr_t addr, int flag)\n{\n    int unit = minor(dev);\n    int nbytes;\n\n    PRINTDBG(\"--- %s() unit=%u, cmd=0x%08x, addr=0x%08x, flag=%d\\n\", __func__, unit, cmd, addr, flag);\n    switch (cmd & ~(IOCPARM_MASK << 16)) {\n    default:\n        return ENODEV;\n\n    case SKELCTL_SETMODE:\n        // TODO: set device mode.\n        PRINTDBG(\"--- SETMODE 0x%x\\n\", (unsigned) addr);\n        return 0;\n\n    case SKELCTL_IO(0):         /* transfer n bytes */\n        nbytes = (cmd >> 16) & IOCPARM_MASK;\n        if (baduaddr(addr) || baduaddr(addr + nbytes - 1))\n            return EFAULT;\n\n        // TODO: transfer nbytes from device to addr.\n        PRINTDBG(\"--- Transfer nbytes=%u to addr=0x%08x\\n\", addr);\n        break;\n    }\n    return 0;\n}\n"
  },
  {
    "path": "sys/arch/pic32/dev/spi.c",
    "content": "/*\n * Generic SPI driver for PIC32.\n *\n * Copyright (C) 2012 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/param.h>\n#include <sys/conf.h>\n#include <sys/user.h>\n#include <sys/ioctl.h>\n#include <sys/systm.h>\n#include <sys/uio.h>\n#include <sys/config.h>\n#include <sys/spi.h>\n\n#define NSPI    4       /* Ports SPI1...SPI4 */\n\n/*\n * To enable debug output, uncomment the first line.\n */\n//#define PRINTDBG printf\n#ifndef PRINTDBG\n#   define PRINTDBG(...) /*empty*/\n#endif\n\nstruct spiio spi_io[NSPI];      /* Data for SPI driver */\n\n/*\n * Open /dev/spi# device.\n * Use default SPI parameters:\n * - rate 250 kHz;\n * - no sleect pin.\n */\nint spidev_open(dev_t dev, int flag, int mode)\n{\n    int channel = minor(dev);\n    struct spiio *io = &spi_io[channel];\n\n    if (channel >= NSPI)\n        return ENXIO;\n\n    if (u.u_uid != 0)\n            return EPERM;\n\n    if (! io->bus)\n        return ENODEV;\n    return 0;\n}\n\nint spidev_close(dev_t dev, int flag, int mode)\n{\n    int channel = minor(dev);\n\n    if (channel >= NSPI)\n        return ENXIO;\n\n    if (u.u_uid != 0)\n            return EPERM;\n\n    return 0;\n}\n\nint spidev_read(dev_t dev, struct uio *uio, int flag)\n{\n    return 0;\n}\n\nint spidev_write(dev_t dev, struct uio *uio, int flag)\n{\n    return 0;\n}\n\n/*\n * SPI control operations:\n * - SPICTL_SETMODE   - set clock polarity and phase\n * - SPICTL_SETRATE   - set data rate in kHz\n * - SPICTL_SETSELPIN - set select pin\n * - SPICTL_IO8(n)    - n*8 bit RW transaction\n * - SPICTL_IO16(n)   - n*16 bit RW transaction\n * - SPICTL_IO32(n)   - n*32 bit RW transaction\n * - SPICTL_IO8R(n)    - n*8 bit R transaction\n * - SPICTL_IO16R(n)   - n*16 bit R transaction\n * - SPICTL_IO32R(n)   - n*32 bit R transaction\n * - SPICTL_IO8W(n)    - n*8 bit W transaction\n * - SPICTL_IO16W(n)   - n*16 bit W transaction\n * - SPICTL_IO32W(n)   - n*32 bit W transaction\n * - SPICTL_IO32RB(n)   - n*32 bit RB transaction (B - swaps byte's order)\n * - SPICTL_IO32WB(n)   - n*32 bit WB transaction\n * - SPICTL_IO32B(n)   - n*32 bit B transaction\n */\nint spidev_ioctl(dev_t dev, u_int cmd, caddr_t addr, int flag)\n{\n    int channel = minor(dev);\n    struct spiio *io = &spi_io[channel];\n    unsigned char *cval = (unsigned char *)addr;\n    int nelem;\n    static unsigned volatile *const tris[8] = {\n        0, &TRISA,&TRISB,&TRISC,&TRISD,&TRISE,&TRISF,&TRISG,\n    };\n    int portnum;\n\n    //PRINTDBG(\"spi%d: ioctl(cmd=%08x, addr=%08x)\\n\", channel+1, cmd, addr);\n    if (channel >= NSPI)\n        return ENXIO;\n\n    switch (cmd & ~(IOCPARM_MASK << 16)) {\n    default:\n        return ENODEV;\n\n    case SPICTL_SETMODE:        /* set SPI mode */\n        /*      --- Clock ----\n         * Mode Polarity Phase\n         *   0     0       0\n         *   1     0       1\n         *   2     1       0\n         *   3     1       1\n         */\n        if ((unsigned) addr & 1)\n            spi_set(io, PIC32_SPICON_CKE);\n        if ((unsigned) addr & 2)\n            spi_set(io, PIC32_SPICON_CKP);\n        return 0;\n\n    case SPICTL_SETRATE:        /* set clock rate, kHz */\n        spi_brg(io, (unsigned int) addr);\n        return 0;\n\n    case SPICTL_SETSELPIN:      /* set select pin */\n        portnum = ((unsigned int) addr >> 8) & 7;\n        if (! portnum)\n            return 0;\n        spi_set_cspin(io, (unsigned*) tris[portnum], (unsigned) addr & 15);\n        return 0;\n\n    case SPICTL_IO8(0):         /* transfer n*8 bits */\n        spi_select(io);\n        nelem = (cmd >> 16) & IOCPARM_MASK;\n        if (baduaddr(addr) || baduaddr(addr + nelem - 1))\n            return EFAULT;\n        spi_bulk_rw(io, nelem, cval);\n        spi_deselect(io);\n        break;\n\n    case SPICTL_IO16(0):        /* transfer n*16 bits */\n        spi_select(io);\n        nelem = (cmd >> 16) & IOCPARM_MASK;\n        if (((unsigned) addr & 1) ||\n            baduaddr(addr) || baduaddr(addr + nelem*2 - 1))\n            return EFAULT;\n        spi_bulk_rw_16(io, nelem<<1, (char *)addr);\n        spi_deselect(io);\n        break;\n\n    case SPICTL_IO32(0):        /* transfer n*32 bits */\n        spi_select(io);\n        nelem = (cmd >> 16) & IOCPARM_MASK;\n        if (((unsigned) addr & 3) ||\n            baduaddr(addr) || baduaddr(addr + nelem*4 - 1))\n            return EFAULT;\n        spi_bulk_rw_32(io, nelem<<2, (char *)addr);\n        spi_deselect(io);\n        break;\n\n// IM: added R and W and BE modes\n    case SPICTL_IO8R(0):         /* transfer n*8 bits */\n        spi_select(io);\n        nelem = (cmd >> 16) & IOCPARM_MASK;\n        if (baduaddr(addr) || baduaddr(addr + nelem - 1))\n            return EFAULT;\n        spi_bulk_read(io, nelem, cval);\n        spi_deselect(io);\n        break;\n\n    case SPICTL_IO16R(0):        /* transfer n*16 bits */\n        spi_select(io);\n        nelem = (cmd >> 16) & IOCPARM_MASK;\n        if (((unsigned) addr & 1) ||\n            baduaddr(addr) || baduaddr(addr + nelem*2 - 1))\n            return EFAULT;\n        spi_bulk_read_16(io, nelem<<1, (char *)addr);\n        spi_deselect(io);\n        break;\n\n    case SPICTL_IO32R(0):        /* transfer n*32 bits */\n        spi_select(io);\n        nelem = (cmd >> 16) & IOCPARM_MASK;\n        if (((unsigned) addr & 3) ||\n            baduaddr(addr) || baduaddr(addr + nelem*4 - 1))\n            return EFAULT;\n        spi_bulk_read_32(io, nelem<<2, (char *)addr);\n        spi_deselect(io);\n        break;\n\n    case SPICTL_IO8W(0):         /* transfer n*8 bits */\n        spi_select(io);\n        nelem = (cmd >> 16) & IOCPARM_MASK;\n        if (baduaddr(addr) || baduaddr(addr + nelem - 1))\n            return EFAULT;\n        spi_bulk_write(io, nelem, cval);\n        spi_deselect(io);\n        break;\n\n    case SPICTL_IO16W(0):        /* transfer n*16 bits */\n        spi_select(io);\n        nelem = (cmd >> 16) & IOCPARM_MASK;\n        if (((unsigned) addr & 1) ||\n            baduaddr(addr) || baduaddr(addr + nelem*2 - 1))\n            return EFAULT;\n        spi_bulk_write_16(io, nelem<<1, (char *)addr);\n        spi_deselect(io);\n        break;\n\n    case SPICTL_IO32W(0):        /* transfer n*32 bits */\n        spi_select(io);\n        nelem = (cmd >> 16) & IOCPARM_MASK;\n        if (((unsigned) addr & 3) ||\n            baduaddr(addr) || baduaddr(addr + nelem*4 - 1))\n            return EFAULT;\n        spi_bulk_write_32(io, nelem<<2, (char *)addr);\n        spi_deselect(io);\n        break;\n\n    case SPICTL_IO32RB(0):        /* transfer n*32 bits */\n        spi_select(io);\n        nelem = (cmd >> 16) & IOCPARM_MASK;\n        if (((unsigned) addr & 3) ||\n            baduaddr(addr) || baduaddr(addr + nelem*4 - 1))\n            return EFAULT;\n        spi_bulk_read_32_be(io, nelem<<2, (char *)addr);\n        spi_deselect(io);\n        break;\n\n    case SPICTL_IO32WB(0):        /* transfer n*32 bits */\n        spi_select(io);\n        nelem = (cmd >> 16) & IOCPARM_MASK;\n        if (((unsigned) addr & 3) ||\n            baduaddr(addr) || baduaddr(addr + nelem*4 - 1))\n            return EFAULT;\n        spi_bulk_write_32_be(io, nelem<<2, (char *)addr);\n        spi_deselect(io);\n        break;\n\n    case SPICTL_IO32B(0):        /* transfer n*32 bits */\n        spi_select(io);\n        nelem = (cmd >> 16) & IOCPARM_MASK;\n        if (((unsigned) addr & 3) ||\n            baduaddr(addr) || baduaddr(addr + nelem*4 - 1))\n            return EFAULT;\n        spi_bulk_write_32_be(io, nelem<<2, (char *)addr);\n        spi_deselect(io);\n        break;\n    }\n    return 0;\n}\n\n/*\n * Test to see if device is present.\n * Return true if found and initialized ok.\n * SPI ports are always present, if configured.\n */\nstatic int\nspiprobe(config)\n    struct conf_ctlr *config;\n{\n    int channel = config->ctlr_unit - 1;\n    struct spiio *io = &spi_io[channel];\n    int sdi, sdo, sck;\n    static const int sdi_tab[NSPI] = {\n        GPIO_PIN('C',4),    /* SDI1 */\n        GPIO_PIN('G',7),    /* SDI2 */\n        GPIO_PIN('D',2),    /* SDI3: 64pin - RD2, 100pin - RF2 */\n        GPIO_PIN('F',4),    /* SDI4 */\n    };\n    static const int sdo_tab[NSPI] = {\n        GPIO_PIN('D',0),    /* SDO1 */\n        GPIO_PIN('G',8),    /* SDO2 */\n        GPIO_PIN('D',3),    /* SDO3: 64pin - RD3, 100pin - RF8 */\n        GPIO_PIN('F',5),    /* SDO4 */\n    };\n    static const int sck_tab[NSPI] = {\n        GPIO_PIN('D',10),   /* SCK1 */\n        GPIO_PIN('G',6),    /* SCK2 */\n        GPIO_PIN('D',1),    /* SCK3: 64pin - RD1, 100pin - RD15 */\n        GPIO_PIN('D',10),   /* SCK4 */\n    };\n\n    if (channel < 0 || channel >= NSPI)\n        return 0;\n    sdi = sdi_tab[channel];\n    sdo = sdo_tab[channel];\n    sck = sck_tab[channel];\n    if (channel+1 == 3 && cpu_pins > 64) {\n        /* Port SPI3 has different pin assignment for 100-pin packages. */\n        sdi = GPIO_PIN('F',2);\n        sdo = GPIO_PIN('F',8);\n        sck = GPIO_PIN('D',15);\n    }\n    printf(\"spi%u: pins sdi=R%c%d/sdo=R%c%d/sck=R%c%d\\n\", channel+1,\n        gpio_portname(sdi), gpio_pinno(sdi),\n        gpio_portname(sdo), gpio_pinno(sdo),\n        gpio_portname(sck), gpio_pinno(sck));\n\n    if (spi_setup(io, channel+1, 0) != 0) {\n        printf(\"spi%u: setup failed\\n\", channel+1);\n        return 0;\n    }\n    return 1;\n}\n\nstruct driver spidriver = {\n    \"spi\", spiprobe,\n};\n"
  },
  {
    "path": "sys/arch/pic32/dev/spi_bus.c",
    "content": "#include <sys/param.h>\n#include <sys/conf.h>\n#include <sys/user.h>\n#include <sys/ioctl.h>\n#include <sys/systm.h>\n#include <sys/uio.h>\n#include <sys/spi.h>\n\n#define NSPI    4       /* Ports SPI1...SPI4 */\n\nstatic struct spireg *const spi_base[NSPI] = {\n    (struct spireg*) &SPI1CON,\n    (struct spireg*) &SPI2CON,\n    (struct spireg*) &SPI3CON,\n    (struct spireg*) &SPI4CON,\n};\n\n//\n// Default SPI bus speed\n//\n#ifndef SPI_MHZ\n#define SPI_MHZ 10\n#endif\n\n//\n// Open an SPI device in default mode.  Use further function calls to\n// set baud rate, clock phase, etc.\n// Returns an integer for the number of the device (ala fd).\n// Returns -1 if no devices are available.\n//\nint spi_setup(struct spiio *io, int channel, int cs)\n{\n    unsigned *tris = 0;\n    int pin = 0;\n\n    if (channel <= 0 || channel > NSPI)\n        return ENXIO;\n\n    if (cs != 0) {\n        /* Compute the port address and pin index of the chip select signal. */\n        int port = (cs >> 4) - 1;\n        tris = (unsigned*) (port + (struct gpioreg*) &TRISA);\n        pin = cs & 15;\n    }\n\n    // Set up the device\n    io->bus = spi_base[channel-1];\n    io->cs_tris = tris;\n    io->cs_pin = pin;\n    io->baud = (BUS_KHZ / SPI_MHZ / 1000 + 1) / 2 - 1;\n    io->mode = PIC32_SPICON_MSTEN | PIC32_SPICON_ON;\n\n    if (tris) {\n        // Configure the CS pin\n        LAT_SET(*tris) = 1<<pin;\n        TRIS_CLR(*tris) = 1<<pin;\n    }\n    return 0;\n}\n\nvoid spi_set_cspin(struct spiio *io, unsigned int *tris, unsigned int pin)\n{\n    // Revert the old CS pin to an input (release it)\n    if (io->cs_tris) {\n        // Configure the CS pin\n        TRIS_SET(*io->cs_tris) = 1<<pin;\n    }\n\n    io->cs_tris = tris;\n    io->cs_pin = pin;\n    if (tris) {\n        // Configure the CS pin\n        LAT_SET(*tris) = 1<<pin;\n        TRIS_CLR(*tris) = 1<<pin;\n    }\n}\n\n//\n// Assert the CS pin of a device.\n// Not only do we set the CS pin, but before we do so we also reconfigure\n// the SPI bus to the required settings for this device.\n//\nvoid spi_select(struct spiio *io)\n{\n    if (io->cs_tris == NULL)\n        return;\n\n    io->bus->brg = io->baud;\n    io->bus->con = io->mode;\n\n    LAT_CLR(*io->cs_tris) = 1 << io->cs_pin;\n}\n\n//\n// Deassert the CS pin of a device.\n//\nvoid spi_deselect(struct spiio *io)\n{\n    if (io->cs_tris == NULL)\n        return;\n\n    LAT_SET(*io->cs_tris) = 1 << io->cs_pin;\n}\n\n//\n// Set a mode setting or two - just updates the internal records, the\n// actual mode is changed next time the CS is asserted\n//\nvoid spi_set(struct spiio *io, unsigned int set)\n{\n    io->mode |= set;\n}\n\n//\n// Clear a mode setting or two - just updates the internal records, the\n// actual mode is changed next time the CS is asserted\n//\nvoid spi_clr(struct spiio *io, unsigned int set)\n{\n    io->mode &= ~set;\n}\n\n//\n// Return the current status of the SPI bus for the device in question\n// Just returns the ->stat entry in the register set.\n//\nunsigned int spi_status(struct spiio *io)\n{\n    return io->bus->stat;\n}\n\n//\n// Transfer one word of data, and return the read word of\n// data.  The actual number of bits sent depends on the\n// mode of the transfer.\n// This is blocking, and waits for the transfer to complete\n// before returning.  Times out after a certain period.\n//\nunsigned char spi_transfer(struct spiio *io, unsigned char data)\n{\n    struct spireg *reg = io->bus;\n    unsigned int to = 100000;\n\n    if (! reg)\n        return 0xF1;\n\n    reg->con = io->mode;\n    reg->brg = io->baud;\n\n    reg->buf = data;\n    while ((--to > 0) && ! (reg->stat & PIC32_SPISTAT_SPIRBF))\n        asm volatile (\"nop\");\n\n    if (to  == 0)\n        return 0xF2;\n\n    return reg->buf;\n}\n\n//\n// Write a huge chunk of data as fast and as efficiently as\n// possible.  Switches in to 32-bit mode regardless, and uses\n// the enhanced buffer mode.\n// Data should be a multiple of 32 bits.\n//\nvoid spi_bulk_write_32_be(struct spiio *io, unsigned int len, char *data)\n{\n    struct spireg *reg = io->bus;\n    int *data32 = (int *)data;\n    unsigned int words = len >> 2;\n    unsigned int nread;\n    unsigned int nwritten;\n\n    if (! reg)\n        return;\n\n    nread = 0;\n    nwritten = words;\n\n    reg->conset = PIC32_SPICON_MODE32 | PIC32_SPICON_ENHBUF;\n    while (nread < words)\n    {\n        if (nwritten > 0 && ! (reg->stat & PIC32_SPISTAT_SPITBF))\n        {\n            reg->buf = mips_bswap(*data32++);\n            nwritten--;\n        }\n\n        if (! (reg->stat & PIC32_SPISTAT_SPIRBE))\n        {\n            (void) reg->buf;\n            nread++;\n        }\n    }\n    reg->con = io->mode;\n}\n\nvoid spi_bulk_write_32(struct spiio *io, unsigned int len, char *data)\n{\n    struct spireg *reg = io->bus;\n    int *data32 = (int *)data;\n    unsigned int words = len >> 2;\n    unsigned int nread;\n    unsigned int nwritten;\n\n    if (! reg)\n        return;\n\n    nread = 0;\n    nwritten = words;\n\n    reg->conset = PIC32_SPICON_MODE32 | PIC32_SPICON_ENHBUF;\n    while (nread < words)\n    {\n        if (nwritten > 0 && ! (reg->stat & PIC32_SPISTAT_SPITBF))\n        {\n            reg->buf = *data32++;\n            nwritten--;\n        }\n\n        if (! (reg->stat & PIC32_SPISTAT_SPIRBE))\n        {\n            (void) reg->buf;\n            nread++;\n        }\n    }\n    reg->con = io->mode;\n}\n\nvoid spi_bulk_write_16(struct spiio *io, unsigned int len, char *data)\n{\n    struct spireg *reg = io->bus;\n    short *data16 = (short *)data;\n    unsigned int words = len >> 1;\n    unsigned int nread;\n    unsigned int nwritten;\n\n    if (! reg)\n        return;\n\n    nread = 0;\n    nwritten = words;\n\n    reg->conset = PIC32_SPICON_MODE16 | PIC32_SPICON_ENHBUF;\n    while (nread < words)\n    {\n        if (nwritten > 0 && ! (reg->stat & PIC32_SPISTAT_SPITBF))\n        {\n            reg->buf = *data16++;\n            nwritten--;\n        }\n\n        if (! (reg->stat & PIC32_SPISTAT_SPIRBE))\n        {\n            (void) reg->buf;\n            nread++;\n        }\n    }\n    reg->con = io->mode;\n}\n\nvoid spi_bulk_write(struct spiio *io, unsigned int len, unsigned char *data)\n{\n    unsigned char *data8 = data;\n    unsigned int i;\n    unsigned char out;\n\n    for (i=0; i<len; i++) {\n        out = *data8;\n        spi_transfer(io, out);\n        data8++;\n    }\n}\n\n//\n// Read a huge chunk of data as fast and as efficiently as\n// possible.  Switches in to 32-bit mode regardless, and uses\n// the enhanced buffer mode.\n// Data should be a multiple of 32 bits.\n//\nvoid spi_bulk_read_32_be(struct spiio *io, unsigned int len, char *data)\n{\n    struct spireg *reg = io->bus;\n    int *data32 = (int *)data;\n    unsigned int words = len >> 2;\n    unsigned int nread;\n    unsigned int nwritten;\n\n    if (! reg)\n        return;\n\n    nread = 0;\n    nwritten = words;\n\n    reg->conset = PIC32_SPICON_MODE32 | PIC32_SPICON_ENHBUF;\n    while (nread < words)\n    {\n        if (nwritten > 0 && ! (reg->stat & PIC32_SPISTAT_SPITBF))\n        {\n            reg->buf = ~0;\n            nwritten--;\n        }\n\n        if (! (reg->stat & PIC32_SPISTAT_SPIRBE))\n        {\n            *data32++ = mips_bswap(reg->buf);\n            nread++;\n        }\n    }\n    reg->con = io->mode;\n}\n\nvoid spi_bulk_read_32(struct spiio *io, unsigned int len, char *data)\n{\n    struct spireg *reg = io->bus;\n    int *data32 = (int *)data;\n    unsigned int words = len >> 2;\n    unsigned int nread;\n    unsigned int nwritten;\n\n    if (! reg)\n        return;\n\n    nread = 0;\n    nwritten = words;\n\n    reg->conset = PIC32_SPICON_MODE32 | PIC32_SPICON_ENHBUF;\n    while (nread < words)\n    {\n        if (nwritten > 0 && ! (reg->stat & PIC32_SPISTAT_SPITBF))\n        {\n            reg->buf = ~0;\n            nwritten--;\n        }\n\n        if (! (reg->stat & PIC32_SPISTAT_SPIRBE))\n        {\n            *data32++ = reg->buf;\n            nread++;\n        }\n    }\n    reg->con = io->mode;\n}\n\nvoid spi_bulk_read_16(struct spiio *io, unsigned int len, char *data)\n{\n    struct spireg *reg = io->bus;\n    short *data16 = (short *)data;\n    unsigned int words = len >> 1;\n    unsigned int nread;\n    unsigned int nwritten;\n\n    if (! reg)\n        return;\n\n    nread = 0;\n    nwritten = words;\n\n    reg->conset = PIC32_SPICON_MODE16 | PIC32_SPICON_ENHBUF;\n    while (nread < words)\n    {\n        if (nwritten > 0 && ! (reg->stat & PIC32_SPISTAT_SPITBF))\n        {\n            reg->buf = ~0;\n            nwritten--;\n        }\n\n        if (! (reg->stat & PIC32_SPISTAT_SPIRBE))\n        {\n            *data16++ = mips_bswap(reg->buf);\n            nread++;\n        }\n    }\n    reg->con = io->mode;\n}\n\nvoid spi_bulk_read(struct spiio *io, unsigned int len, unsigned char *data)\n{\n    unsigned char *data8 = data;\n    unsigned int i;\n    unsigned char in,out;\n\n    for (i=0; i<len; i++) {\n        out = 0xFF;\n        in = spi_transfer(io, out);\n        *data8 = in;\n        data8++;\n    }\n}\n\nvoid spi_bulk_rw_32_be(struct spiio *io, unsigned int len, char *data)\n{\n    struct spireg *reg = io->bus;\n    int *read32 = (int *)data;\n    int *write32 = (int *)data;\n    unsigned int words = len >> 2;\n    unsigned int nread;\n    unsigned int nwritten;\n\n    if (! reg)\n        return;\n\n    nread = 0;\n    nwritten = words;\n\n    reg->conset = PIC32_SPICON_MODE32 | PIC32_SPICON_ENHBUF;\n    while (nread < words)\n    {\n        if (nwritten > 0 && ! (reg->stat & PIC32_SPISTAT_SPITBF))\n        {\n            reg->buf = *write32++;\n            nwritten--;\n        }\n\n        if (! (reg->stat & PIC32_SPISTAT_SPIRBE))\n        {\n            *read32++ = mips_bswap(reg->buf);\n            nread++;\n        }\n    }\n    reg->con = io->mode;\n}\n\nvoid spi_bulk_rw_32(struct spiio *io, unsigned int len, char *data)\n{\n    struct spireg *reg = io->bus;\n    int *read32 = (int *)data;\n    int *write32 = (int *)data;\n    unsigned int words = len >> 2;\n    unsigned int nread;\n    unsigned int nwritten;\n\n    if (! reg)\n        return;\n\n    nread = 0;\n    nwritten = words;\n\n    reg->conset = PIC32_SPICON_MODE32 | PIC32_SPICON_ENHBUF;\n    while (nread < words)\n    {\n        if (nwritten > 0 && ! (reg->stat & PIC32_SPISTAT_SPITBF))\n        {\n            reg->buf = *write32++;\n            nwritten--;\n        }\n\n        if (! (reg->stat & PIC32_SPISTAT_SPIRBE))\n        {\n            *read32++ = reg->buf;\n            nread++;\n        }\n    }\n    reg->con = io->mode;\n}\n\nvoid spi_bulk_rw_16(struct spiio *io, unsigned int len, char *data)\n{\n    struct spireg *reg = io->bus;\n    short *read16 = (short *)data;\n    short *write16 = (short *)data;\n    unsigned int words = len >> 1;\n    unsigned int nread;\n    unsigned int nwritten;\n\n    if (! reg)\n        return;\n\n    nread = 0;\n    nwritten = words;\n\n    reg->conset = PIC32_SPICON_MODE16 | PIC32_SPICON_ENHBUF;\n    while (nread < words)\n    {\n        if (nwritten > 0 && ! (reg->stat & PIC32_SPISTAT_SPITBF))\n        {\n            reg->buf = *write16++;\n            nwritten--;\n        }\n\n        if (! (reg->stat & PIC32_SPISTAT_SPIRBE))\n        {\n            *read16++ = mips_bswap(reg->buf);\n            nread++;\n        }\n    }\n    reg->con = io->mode;\n}\n\nvoid spi_bulk_rw(struct spiio *io, unsigned int len, unsigned char *data)\n{\n    unsigned char *data8 = data;\n    unsigned int i;\n    unsigned char in,out;\n\n    for (i=0; i<len; i++) {\n        out = *data8;\n        in = spi_transfer(io, out);\n        *data8 = in;\n        data8++;\n    }\n}\n\n//\n// Set the SPI baud rate for a device (in KHz)\n//\nvoid spi_brg(struct spiio *io, unsigned int baud)\n{\n    io->baud = (BUS_KHZ / baud + 1) / 2 - 1;\n}\n\n//\n// Return the name of the SPI bus for a device\n//\nchar *spi_name(struct spiio *io)\n{\n    if (io->bus == spi_base[0])\n        return \"SPI1\";\n\n    if (io->bus == spi_base[1])\n        return \"SPI2\";\n\n    if (io->bus == spi_base[2])\n        return \"SPI3\";\n\n    if (io->bus == spi_base[3])\n        return \"SPI4\";\n\n    return \"SPI?\";\n}\n\n//\n// Return the port name of the CS pin for a device\n//\nchar spi_csname(struct spiio *io)\n{\n    switch ((unsigned)io->cs_tris) {\n    case (unsigned)&TRISA: return 'A';\n    case (unsigned)&TRISB: return 'B';\n    case (unsigned)&TRISC: return 'C';\n    case (unsigned)&TRISD: return 'D';\n    case (unsigned)&TRISE: return 'E';\n    case (unsigned)&TRISF: return 'F';\n    case (unsigned)&TRISG: return 'G';\n    }\n    return '?';\n}\n\nint spi_cspin(struct spiio *io)\n{\n    return io->cs_pin;\n}\n\nunsigned int spi_get_brg(struct spiio *io)\n{\n    return BUS_KHZ / (io->baud + 1) / 2;\n}\n"
  },
  {
    "path": "sys/arch/pic32/dev/spirams.c",
    "content": "/*\n * Disk driver for serial RAM chips connected via SPI port.\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/buf.h>\n#include <sys/errno.h>\n#include <sys/dk.h>\n#include <sys/disk.h>\n#include <sys/spi.h>\n#include <sys/config.h>\n\n#include <machine/debug.h>\n\n#include <pic32/dev/spirams.h>\n\n#define SPIRAM_WREN     0x06\n#define SPIRAM_WRDI     0x04\n#define SPIRAM_RDSR     0x05\n#define SPIRAM_WRSR     0x01\n#define SPIRAM_READ     0x03\n#define SPIRAM_WRITE    0x02\n#define SPIRAM_SLEEP    0xB9\n#define SPIRAM_WAKE     0xAB\n\n#ifndef SPIRAMS_MHZ\n#define SPIRAMS_MHZ     10\n#endif\n\nstruct spiio spirams_io[SPIRAMS_CHIPS];\n\nint spirams_dkindex;                    /* disk index for statistics */\n\n/*\n * Size of RAM disk.\n */\n#define SPIRAMS_TOTAL_KBYTES    (SPIRAMS_CHIPS * SPIRAMS_CHIPSIZE)\n\n#define MRBSIZE         1024\n#define MRBLOG2         10\n\nunsigned int spir_read_block(unsigned int chip, unsigned int address, unsigned int length, char *data)\n{\n    struct spiio *io = &spirams_io[chip];\n    register unsigned int cs = 0;\n\n    switch (chip) {\n    case 0:\n        #ifdef SPIRAMS_LED0_PORT\n        TRIS_CLR(SPIRAMS_LED0_PORT) = 1<<SPIRAMS_LED0_PIN;\n        LAT_SET(SPIRAMS_LED0_PORT) = 1<<SPIRAMS_LED0_PIN;\n        #endif\n        break;\n    case 1:\n        #ifdef SPIRAMS_LED1_PORT\n        TRIS_CLR(SPIRAMS_LED1_PORT) = 1<<SPIRAMS_LED1_PIN;\n        LAT_SET(SPIRAMS_LED1_PORT) = 1<<SPIRAMS_LED1_PIN;\n        #endif\n        break;\n    case 2:\n        #ifdef SPIRAMS_LED2_PORT\n        TRIS_CLR(SPIRAMS_LED2_PORT) = 1<<SPIRAMS_LED2_PIN;\n        LAT_SET(SPIRAMS_LED2_PORT) = 1<<SPIRAMS_LED2_PIN;\n        #endif\n        break;\n    case 3:\n        #ifdef SPIRAMS_LED3_PORT\n        TRIS_CLR(SPIRAMS_LED3_PORT) = 1<<SPIRAMS_LED3_PIN;\n        LAT_SET(SPIRAMS_LED3_PORT) = 1<<SPIRAMS_LED3_PIN;\n        #endif\n        break;\n    case 4:\n        #ifdef SPIRAMS_LED4_PORT\n        TRIS_CLR(SPIRAMS_LED4_PORT) = 1<<SPIRAMS_LED4_PIN;\n        LAT_SET(SPIRAMS_LED4_PORT) = 1<<SPIRAMS_LED4_PIN;\n        #endif\n        break;\n    case 5:\n        #ifdef SPIRAMS_LED5_PORT\n        TRIS_CLR(SPIRAMS_LED5_PORT) = 1<<SPIRAMS_LED5_PIN;\n        LAT_SET(SPIRAMS_LED5_PORT) = 1<<SPIRAMS_LED5_PIN;\n        #endif\n        break;\n    case 6:\n        #ifdef SPIRAMS_LED6_PORT\n        TRIS_CLR(SPIRAMS_LED6_PORT) = 1<<SPIRAMS_LED6_PIN;\n        LAT_SET(SPIRAMS_LED6_PORT) = 1<<SPIRAMS_LED6_PIN;\n        #endif\n        break;\n    case 7:\n        #ifdef SPIRAMS_LED7_PORT\n        TRIS_CLR(SPIRAMS_LED7_PORT) = 1<<SPIRAMS_LED7_PIN;\n        LAT_SET(SPIRAMS_LED7_PORT) = 1<<SPIRAMS_LED7_PIN;\n        #endif\n        break;\n    case 8:\n        #ifdef SPIRAMS_LED8_PORT\n        TRIS_CLR(SPIRAMS_LED8_PORT) = 1<<SPIRAMS_LED8_PIN;\n        LAT_SET(SPIRAMS_LED8_PORT) = 1<<SPIRAMS_LED8_PIN;\n        #endif\n        break;\n    case 9:\n        #ifdef SPIRAMS_LED9_PORT\n        TRIS_CLR(SPIRAMS_LED9_PORT) = 1<<SPIRAMS_LED9_PIN;\n        LAT_SET(SPIRAMS_LED9_PORT) = 1<<SPIRAMS_LED9_PIN;\n        #endif\n        break;\n    case 10:\n        #ifdef SPIRAMS_LED10_PORT\n        TRIS_CLR(SPIRAMS_LED10_PORT) = 1<<SPIRAMS_LED10_PIN;\n        LAT_SET(SPIRAMS_LED10_PORT) = 1<<SPIRAMS_LED10_PIN;\n        #endif\n        break;\n    case 11:\n        #ifdef SPIRAMS_LED11_PORT\n        TRIS_CLR(SPIRAMS_LED11_PORT) = 1<<SPIRAMS_LED11_PIN;\n        LAT_SET(SPIRAMS_LED11_PORT) = 1<<SPIRAMS_LED11_PIN;\n        #endif\n        break;\n    case 12:\n        #ifdef SPIRAMS_LED12_PORT\n        TRIS_CLR(SPIRAMS_LED12_PORT) = 1<<SPIRAMS_LED12_PIN;\n        LAT_SET(SPIRAMS_LED12_PORT) = 1<<SPIRAMS_LED12_PIN;\n        #endif\n        break;\n    case 13:\n        #ifdef SPIRAMS_LED13_PORT\n        TRIS_CLR(SPIRAMS_LED13_PORT) = 1<<SPIRAMS_LED13_PIN;\n        LAT_SET(SPIRAMS_LED13_PORT) = 1<<SPIRAMS_LED13_PIN;\n        #endif\n        break;\n    case 14:\n        #ifdef SPIRAMS_LED14_PORT\n        TRIS_CLR(SPIRAMS_LED14_PORT) = 1<<SPIRAMS_LED14_PIN;\n        LAT_SET(SPIRAMS_LED14_PORT) = 1<<SPIRAMS_LED14_PIN;\n        #endif\n        break;\n    case 15:\n        #ifdef SPIRAMS_LED15_PORT\n        TRIS_CLR(SPIRAMS_LED15_PORT) = 1<<SPIRAMS_LED15_PIN;\n        LAT_SET(SPIRAMS_LED15_PORT) = 1<<SPIRAMS_LED15_PIN;\n        #endif\n        break;\n    }\n\n    spi_select(io);\n    spi_transfer(io, SPIRAM_READ);\n    spi_transfer(io, address >> 16);\n    spi_transfer(io, address >> 8);\n    spi_transfer(io, address);\n\n    // If the length is a multiple of 32 bits, then do a 32 bit transfer\n#if 0\n    if ((length & 3) == 0)\n        spi_bulk_read_32(io, length, data);\n    else if ((length & 1) == 0)\n        spi_bulk_read_16(io, length, data);\n    else\n#endif\n    spi_bulk_read(io, length, (unsigned char *)data);\n    spi_deselect(io);\n\n    switch (chip) {\n    case 0:\n        #ifdef SPIRAMS_LED0_PORT\n        LAT_CLR(SPIRAMS_LED0_PORT) = 1<<SPIRAMS_LED0_PIN;\n        #endif\n        break;\n    case 1:\n        #ifdef SPIRAMS_LED1_PORT\n        LAT_CLR(SPIRAMS_LED1_PORT) = 1<<SPIRAMS_LED1_PIN;\n        #endif\n        break;\n    case 2:\n        #ifdef SPIRAMS_LED2_PORT\n        LAT_CLR(SPIRAMS_LED2_PORT) = 1<<SPIRAMS_LED2_PIN;\n        #endif\n        break;\n    case 3:\n        #ifdef SPIRAMS_LED3_PORT\n        LAT_CLR(SPIRAMS_LED3_PORT) = 1<<SPIRAMS_LED3_PIN;\n        #endif\n        break;\n    }\n    return cs;\n}\n\nint spirams_read(unsigned int offset, char *data, unsigned int bcount)\n{\n    register unsigned int chip;\n    register unsigned int toread;\n    register unsigned int address;\n    register unsigned int pass = 0;\n\n    while (bcount > 0) {\n        pass++;\n        toread = bcount;\n        if (toread > MRBSIZE)\n            toread = MRBSIZE;\n\n        chip = offset / SPIRAMS_CHIPSIZE;\n\n        address = (offset<<10) - (chip * (SPIRAMS_CHIPSIZE*1024));\n\n        if (chip >= SPIRAMS_CHIPS) {\n            printf(\"!!!EIO\\n\");\n            return EIO;\n        }\n        spir_read_block(chip, address, toread, data);\n        bcount -= toread;\n        offset += (toread>>MRBLOG2);\n        data += toread;\n    }\n    return 1;\n}\n\nunsigned int spir_write_block(unsigned int chip, unsigned int address, unsigned int length, char *data)\n{\n    struct spiio *io = &spirams_io[chip];\n    register unsigned int cs = 0;\n    char blank __attribute__((unused));\n\n    switch (chip) {\n    case 0:\n        #ifdef SPIRAMS_LED0_PORT\n        TRIS_CLR(SPIRAMS_LED0_PORT) = 1<<SPIRAMS_LED0_PIN;\n        LAT_SET(SPIRAMS_LED0_PORT) = 1<<SPIRAMS_LED0_PIN;\n        #endif\n        break;\n    case 1:\n        #ifdef SPIRAMS_LED1_PORT\n        TRIS_CLR(SPIRAMS_LED1_PORT) = 1<<SPIRAMS_LED1_PIN;\n        LAT_SET(SPIRAMS_LED1_PORT) = 1<<SPIRAMS_LED1_PIN;\n        #endif\n        break;\n    case 2:\n        #ifdef SPIRAMS_LED2_PORT\n        TRIS_CLR(SPIRAMS_LED2_PORT) = 1<<SPIRAMS_LED2_PIN;\n        LAT_SET(SPIRAMS_LED2_PORT) = 1<<SPIRAMS_LED2_PIN;\n        #endif\n        break;\n    case 3:\n        #ifdef SPIRAMS_LED3_PORT\n        TRIS_CLR(SPIRAMS_LED3_PORT) = 1<<SPIRAMS_LED3_PIN;\n        LAT_SET(SPIRAMS_LED3_PORT) = 1<<SPIRAMS_LED3_PIN;\n        #endif\n        break;\n    }\n\n    spi_select(io);\n    spi_transfer(io, SPIRAM_WRITE);\n    spi_transfer(io, address >> 16);\n    spi_transfer(io, address >> 8);\n    spi_transfer(io, address);\n\n#if 0\n    if ((length & 3) == 0)\n        spi_bulk_write_32(io, length, data);\n    else if ((length & 1) == 0)\n        spi_bulk_write_16(io, length, data);\n    else\n#endif\n    spi_bulk_write(io, length, (unsigned char *)data);\n    spi_deselect(io);\n\n    switch (chip) {\n    case 0:\n        #ifdef SPIRAMS_LED0_PORT\n        LAT_CLR(SPIRAMS_LED0_PORT) = 1<<SPIRAMS_LED0_PIN;\n        #endif\n        break;\n    case 1:\n        #ifdef SPIRAMS_LED1_PORT\n        LAT_CLR(SPIRAMS_LED1_PORT) = 1<<SPIRAMS_LED1_PIN;\n        #endif\n        break;\n    case 2:\n        #ifdef SPIRAMS_LED2_PORT\n        LAT_CLR(SPIRAMS_LED2_PORT) = 1<<SPIRAMS_LED2_PIN;\n        #endif\n        break;\n    case 3:\n        #ifdef SPIRAMS_LED3_PORT\n        LAT_CLR(SPIRAMS_LED3_PORT) = 1<<SPIRAMS_LED3_PIN;\n        #endif\n        break;\n    }\n    return cs;\n}\n\nint spirams_write (unsigned int offset, char *data, unsigned bcount)\n{\n    register unsigned int chip;\n    register unsigned int address;\n    register unsigned int towrite;\n    register unsigned int pass = 0;\n\n    while (bcount > 0) {\n        pass++;\n        towrite = bcount;\n        if (towrite > MRBSIZE)\n            towrite = MRBSIZE;\n\n        chip = offset / SPIRAMS_CHIPSIZE;\n        address = (offset<<10) - (chip * (SPIRAMS_CHIPSIZE*MRBSIZE));\n\n        if (chip >= SPIRAMS_CHIPS) {\n            printf(\"!!!EIO\\n\");\n            return EIO;\n        }\n\n        spir_write_block(chip, address, towrite, data);\n        bcount -= towrite;\n        offset += (towrite>>MRBLOG2);\n        data += towrite;\n    }\n    return 1;\n}\n\n/*\n * Initialize hardware.\n */\nstatic int spirams_init(int spi_port, char cs[])\n{\n    struct spiio *io = &spirams_io[0];\n\n    if (spi_setup(io, spi_port, cs[0]) != 0) {\n        printf(\"sr0: cannot open SPI%u port\\n\", spi_port);\n        return 0;\n    }\n    spi_brg(io, SPIRAMS_MHZ * 1000);\n    spi_set(io, PIC32_SPICON_CKE);\n\n#if SPIRAMS_CHIPS >= 1\n    spi_setup(io+1, spi_port, cs[1]);\n\n    spi_brg(io+1, SPIRAMS_MHZ * 1000);\n    spi_set(io+1, PIC32_SPICON_CKE);\n#endif\n#if SPIRAMS_CHIPS >= 2\n    spi_setup(io+2, spi_port, cs[2]);\n\n    spi_brg(io+2, SPIRAMS_MHZ * 1000);\n    spi_set(io+2, PIC32_SPICON_CKE);\n#endif\n#if SPIRAMS_CHIPS >= 3\n    spi_setup(io+3, spi_port, cs[3]);\n\n    spi_brg(io+3, SPIRAMS_MHZ * 1000);\n    spi_set(io+3, PIC32_SPICON_CKE);\n#endif\n#if SPIRAMS_CHIPS >= 4\n    spi_setup(io+4, spi_port, cs[4]);\n\n    spi_brg(io+4, SPIRAMS_MHZ * 1000);\n    spi_set(io+4, PIC32_SPICON_CKE);\n#endif\n#if SPIRAMS_CHIPS >= 5\n    spi_setup(io+5, spi_port, cs[5]);\n\n    spi_brg(io+5, SPIRAMS_MHZ * 1000);\n    spi_set(io+5, PIC32_SPICON_CKE);\n#endif\n#if SPIRAMS_CHIPS >= 6\n    spi_setup(io+6, spi_port, cs[6]);\n\n    spi_brg(io+6, SPIRAMS_MHZ * 1000);\n    spi_set(io+6, PIC32_SPICON_CKE);\n#endif\n#if SPIRAMS_CHIPS >= 7\n    spi_setup(io+7, spi_port, cs[7]);\n\n    spi_brg(io+7, SPIRAMS_MHZ * 1000);\n    spi_set(io+7, PIC32_SPICON_CKE);\n#endif\n#if SPIRAMS_CHIPS >= 8\n    spi_setup(io+8, spi_port, cs[8]);\n\n    spi_brg(io+8, SPIRAMS_MHZ * 1000);\n    spi_set(io+8, PIC32_SPICON_CKE);\n#endif\n#if SPIRAMS_CHIPS >= 9\n    spi_setup(io+9, spi_port, cs[9]);\n\n    spi_brg(io+9, SPIRAMS_MHZ * 1000);\n    spi_set(io+9, PIC32_SPICON_CKE);\n#endif\n#if SPIRAMS_CHIPS >= 10\n    spi_setup(io+10, spi_port, cs[10]);\n\n    spi_brg(io+10, SPIRAMS_MHZ * 1000);\n    spi_set(io+10, PIC32_SPICON_CKE);\n#endif\n#if SPIRAMS_CHIPS >= 11\n    spi_setup(io+11, spi_port, cs[11]);\n\n    spi_brg(io+11, SPIRAMS_MHZ * 1000);\n    spi_set(io+11, PIC32_SPICON_CKE);\n#endif\n#if SPIRAMS_CHIPS >= 12\n    spi_setup(io+12, spi_port, cs[12]);\n\n    spi_brg(io+12, SPIRAMS_MHZ * 1000);\n    spi_set(io+12, PIC32_SPICON_CKE);\n#endif\n#if SPIRAMS_CHIPS >= 13\n    spi_setup(io+13, spi_port, cs[13]);\n\n    spi_brg(io+13, SPIRAMS_MHZ * 1000);\n    spi_set(io+13, PIC32_SPICON_CKE);\n#endif\n#if SPIRAMS_CHIPS >= 14\n    spi_setup(io+14, spi_port, cs[14]);\n\n    spi_brg(io+14, SPIRAMS_MHZ * 1000);\n    spi_set(io+14, PIC32_SPICON_CKE);\n#endif\n#if SPIRAMS_CHIPS >= 15\n    spi_setup(io+15, spi_port, cs[15]);\n\n    spi_brg(io+15, SPIRAMS_MHZ * 1000);\n    spi_set(io+15, PIC32_SPICON_CKE);\n#endif\n\n    printf(\"spirams0: size %dKB, speed %d Mbit/sec\\n\",\n        SPIRAMS_CHIPS * SPIRAMS_CHIPSIZE, spi_get_brg(io) / 1000);\n    return 1;\n}\n\n/*\n * Open the disk.\n */\nint spirams_open(dev_t dev, int flag, int mode)\n{\n    return 0;\n}\n\nint spirams_close(dev_t dev, int flag, int mode)\n{\n    return 0;\n}\n\n/*\n * Return the size of the device in kbytes.\n */\ndaddr_t spirams_size(dev_t dev)\n{\n    return SPIRAMS_TOTAL_KBYTES;\n}\n\nvoid spirams_strategy(struct buf *bp)\n{\n    int offset = bp->b_blkno;\n    long nblk = btod(bp->b_bcount);\n    int s;\n\n    /*\n     * Determine the size of the transfer, and make sure it is\n     * within the boundaries of the partition.\n     */\n    if (bp->b_blkno + nblk > SPIRAMS_TOTAL_KBYTES) {\n        /* if exactly at end of partition, return an EOF */\n        if (bp->b_blkno == SPIRAMS_TOTAL_KBYTES) {\n            bp->b_resid = bp->b_bcount;\n            biodone(bp);\n            return;\n        }\n        /* or truncate if part of it fits */\n        nblk = SPIRAMS_TOTAL_KBYTES - bp->b_blkno;\n        if (nblk <= 0) {\n            bp->b_error = EINVAL;\n            bp->b_flags |= B_ERROR;\n            biodone(bp);\n            return;\n        }\n        bp->b_bcount = nblk << DEV_BSHIFT;\n    }\n\n    led_control(LED_SWAP, 1);\n\n    s = splbio();\n#ifdef UCB_METER\n    if (spirams_dkindex >= 0) {\n        dk_busy |= 1 << spirams_dkindex;\n        dk_xfer[spirams_dkindex]++;\n        dk_bytes[spirams_dkindex] += bp->b_bcount;\n    }\n#endif\n\n    if (bp->b_flags & B_READ) {\n        spirams_read(offset, bp->b_addr, bp->b_bcount);\n    } else {\n        spirams_write(offset, bp->b_addr, bp->b_bcount);\n    }\n\n    biodone(bp);\n    led_control(LED_SWAP, 0);\n#ifdef UCB_METER\n    if (spirams_dkindex >= 0)\n        dk_busy &= ~(1 << spirams_dkindex);\n#endif\n    splx(s);\n}\n\nint spirams_ioctl(dev_t dev, u_int cmd, caddr_t addr, int flag)\n{\n    int error = 0;\n\n    switch (cmd) {\n\n    case DIOCGETMEDIASIZE:\n        /* Get disk size in kbytes. */\n        *(int*) addr = SPIRAMS_TOTAL_KBYTES;\n        break;\n\n    default:\n        error = EINVAL;\n        break;\n    }\n    return error;\n}\n\n/*\n * Test to see if device is present.\n * Return true if found and initialized ok.\n */\nstatic int\nspirams_probe(config)\n    struct conf_device *config;\n{\n    int i;\n\n    /* Only one device unit is supported. */\n    if (config->dev_unit != 0)\n        return 0;\n\n    printf(\"sr0: port SPI%d, pins \", config->dev_ctlr);\n    for (i=0; i<SPIRAMS_CHIPS; i++) {\n        int cs = config->dev_pins[i];\n        if (i > 0)\n            printf(\"/\");\n        if (i == 7)\n            printf(\"\\n                     \");\n        printf(\"R%c%d\", gpio_portname(cs), gpio_pinno(cs));\n    }\n    printf(\"\\n\");\n    if (spirams_init(config->dev_ctlr, config->dev_pins) != 0)\n        return 0;\n\n#ifdef UCB_METER\n    dk_alloc(&spirams_dkindex, 1, \"sr0\");\n#endif\n    return 1;\n}\n\nstruct driver srdriver = {\n    \"sr\", spirams_probe,\n};\n"
  },
  {
    "path": "sys/arch/pic32/dev/spirams.h",
    "content": "#ifndef _SPIRAMS_H\n#define _SPIRAMS_H\n\n#ifdef KERNEL\nextern int spirams_open(dev_t dev, int flag, int mode);\nextern int spirams_close(dev_t dev, int flag, int mode);\nextern daddr_t spirams_size(dev_t dev);\nextern void spirams_strategy(struct buf *bp);\nextern int spirams_ioctl (dev_t dev, u_int cmd, caddr_t addr, int flag);\n#endif\n\n#endif\n"
  },
  {
    "path": "sys/arch/pic32/dev/sramc.c",
    "content": "/*\n * Driver for external SRAM-CPLD based Swap and Filesystem devices\n *\n * This version is for 8MB RAMDISK v.1.1 and compatible\n * Pito 7.4.2014 - PIC32MX PMP bus version\n * Under by retrobsd.org used Licence\n * No warranties of any kind\n *\n * Interface:\n *  PMD<7:0> - connected to PMP data bus\n *  PMRD      - fetch a byte from memory to data<7:0>, increment address, PMRD\n *  PMWR      - write a byte data[7:0] to memory, increment address, PMWR\n *  PMA0      - HIGH - write Address from data<3:0> in 6 steps: high nibble ... low nibble\n *            - LOW - write/read Data\n *\n * Signals PMRD, PMWR are active LOW and idle HIGH\n * Signal PMA0 is LOW when accessing RAM Data, and HIGH when accessing RAM Addresses\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/buf.h>\n#include <sys/errno.h>\n#include <sys/dk.h>\n#include <sys/ioctl.h>\n#include <sys/disk.h>\n#include <sys/config.h>\n\n#include <machine/debug.h>\n\n#include <pic32/dev/sramc.h>\n\nint sramc_dkindex = -1;                 /* Statistics slot number */\n\n/*\n * Size of RAM disk.\n */\n#define SRAMC_TOTAL_KBYTES      8192    /* 4096 for 4MB ramdisk */\n\n// Ramdisk v.1.1. wiring\n// PMP         RAMDISK\n// ===================\n// PMD<D0-D7>  D0-D7\n// PMRD        /RD\n// PMWR        /WR\n// PMA<0>      /DATA\n\n// RD and WR pulses duration settings\n// Minimal recommended settings, increase them when unstable\n// No warranties of any kind\n// for 120MHz clock, 70ns PSRAM, Ramdisk v.1.1.\n#define ADR_PULSE  1\n#define WR_PULSE   5\n#define RD_PULSE   11\n\n// for 80MHz clock, 70ns PSRAM, Ramdisk v.1.1.\n//#define ADR_PULSE 1\n//#define WR_PULSE 3\n//#define RD_PULSE 8\n\n// for 120MHz clock, 55ns SRAM\n//#define ADR_PULSE 1\n//#define WR_PULSE 3\n//#define RD_PULSE 6\n\n// for 80MHz clock, 55ns SRAM\n//#define ADR_PULSE 1\n//#define WR_PULSE 2\n//#define RD_PULSE 4\n\ntypedef union {\n    unsigned value;\n    struct {\n        unsigned nib1 : 4;  // lowest nibble\n        unsigned nib2 : 4;\n        unsigned nib3 : 4;\n        unsigned nib4 : 4;\n        unsigned nib5 : 4;\n        unsigned nib6 : 4;\n        unsigned nib7 : 4;\n        unsigned nib8 : 4;  // highest nibble\n    };\n} nybbles;\n\n/*\n * Load the 24 bit address to Ramdisk.\n *\n */\ninline static void\ndev_load_address(addr)\n        unsigned addr;\n{\n    nybbles temp;\n    temp.value = addr;\n\n    while (PMMODE & 0x8000);            // Poll - if busy, wait\n\n    PMADDR = 1;                         // set ADR mode (1) to write the Address\n\n    PMMODE = 0b10<<8 | (ADR_PULSE<<2);  // full ADR speed\n\n    PMDIN = temp.nib6;                  /* write 4 bits */\n\n    while (PMMODE & 0x8000);            // Poll - if busy, wait\n    PMDIN = temp.nib5;                  /* write 4 bits */\n\n    while (PMMODE & 0x8000);            // Poll - if busy, wait\n    PMDIN = temp.nib4;                  /* write 4 bits */\n\n    while (PMMODE & 0x8000);            // Poll - if busy, wait\n    PMDIN = temp.nib3;                  /* write 4 bits */\n\n    while (PMMODE & 0x8000);            // Poll - if busy, wait\n    PMDIN = temp.nib2;                  /* write 4 bits */\n\n    while (PMMODE & 0x8000);            // Poll - if busy, wait\n    PMDIN = temp.nib1;                  /* write 4 bits */\n}\n\n/*\n * Return a size of partition in kbytes.\n * The memory is divided into two partitions: A and B.\n * Size of partition B is specified in the kernel config file\n * as option SRAMC_SWAP_KBYTES.\n */\ndaddr_t sramc_size(dev_t dev)\n{\n    switch (minor(dev)) {\n    case 0:\n        /* Whole disk. */\n        return SRAMC_TOTAL_KBYTES;\n    case 1:\n        /* Partition A: filesystem. */\n        return SRAMC_TOTAL_KBYTES - SRAMC_SWAP_KBYTES;\n    case 2:\n    default:\n        /* Partition B: swap space. */\n        return SRAMC_SWAP_KBYTES;\n    }\n}\n\n/*\n * Read a block of data.\n */\nstatic int sramc_read(unsigned int blockno, char *data, unsigned int nbytes)\n{\n    int i;\n\n    //DEBUG9(\"sramc%d: read block %u, length %u bytes, addr %p\\n\", major(dev), blockno, nbytes, data);\n\n    dev_load_address(blockno * DEV_BSIZE);\n\n    /* Read data. */\n\n    while (PMMODE & 0x8000);            // Poll - if busy, wait\n\n    PMADDR = 0;                         // set DATA mode (0)\n\n    PMMODE = 0b10<<8 | (RD_PULSE<<2);   // read slowly\n\n    PMDIN; // Read the PMDIN to clear previous data and latch new data\n\n    for (i=0; i<nbytes; i++) {\n        while (PMMODE & 0x8000);        // Poll - if busy, wait before reading\n        *data++ = PMDIN;                /* read a byte of data */\n    }\n    return 1;\n}\n\n/*\n * Write a block of data.\n */\nstatic int sramc_write(unsigned int blockno, char *data, unsigned int nbytes)\n{\n    unsigned i;\n\n    //DEBUG9(\"sramc%d: write block %u, length %u bytes, addr %p\\n\", major(dev), blockno, nbytes, data);\n\n    dev_load_address(blockno * DEV_BSIZE);\n\n    /* Write data. */\n\n    while (PMMODE & 0x8000);            // Poll - if busy, wait\n\n    PMADDR = 0;                         // set DATA mode (0)\n\n    PMMODE = 0b10<<8 | (WR_PULSE<<2);   // faster with write\n\n    for (i=0; i<nbytes; i++) {\n        while (PMMODE & 0x8000);        // Poll - if busy, wait\n        PMDIN = *data++;                /* write a byte of data */\n    }\n    return 1;\n}\n\n/*\n * Init the disk.\n */\nstatic void sramc_init()\n{\n    // Initialize PMP hardware\n\n    PMCON = 0;                          // disable PMP\n    asm volatile (\"nop\");               // Errata\n\n    PMCON = 1<<9 | 1<<8;                // Enable RD and WR\n\n    //        MODE  WAITB  WAITM  WAITE\n    PMMODE = (2<<8) | 0 | (14<<2) | 0;  // Mode2 Master 8bit\n\n    PMAEN = 1;                          // PMA<0>, use A0 only\n\n    PMADDR = 0;                         // start with DATA mode\n\n    PMCONSET = 1<<15;                   // PMP enabled\n    asm volatile (\"nop\");\n\n    // make a couple of dummy reads - it refreshes the cpld internals a little bit :)\n    while (PMMODE & 0x8000);            // Poll - if busy, wait before reading\n    PMDIN;                              /* read a byte of data */\n    while (PMMODE & 0x8000);            // Poll - if busy, wait before reading\n    PMDIN;                              /* read a byte of data */\n\n    PMADDR = 1;                         // go with with ADDRESS mode now\n\n    DEBUG3(\"sramc: init done\\n\");\n}\n\n/*\n * Open the disk.\n */\nint sramc_open(dev_t dev, int flag, int mode)\n{\n    DEBUG3(\"sramc: open\\n\");\n    return 0;\n}\n\nint sramc_close(dev_t dev, int flag, int mode)\n{\n    return 0;\n}\n\nvoid sramc_strategy(struct buf *bp)\n{\n    int offset = bp->b_blkno;\n    long nblk = btod(bp->b_bcount);\n    int part_offset, part_size, s;\n\n    /* Compute partition size and offset. */\n    part_size = sramc_size(bp->b_dev);\n    if (minor(bp->b_dev) < 2) {\n        /* Partition A or a whole disk. */\n        part_offset = 0;\n    } else {\n        /* Partition B: swap space. */\n        part_offset = SRAMC_TOTAL_KBYTES - part_size;\n    }\n\n    /*\n     * Determine the size of the transfer, and make sure it is\n     * within the boundaries of the partition.\n     */\n    offset += part_offset;\n    if (bp->b_blkno + nblk > part_size) {\n        /* if exactly at end of partition, return an EOF */\n        if (bp->b_blkno == part_size) {\n            bp->b_resid = bp->b_bcount;\n            biodone(bp);\n            return;\n        }\n        /* or truncate if part of it fits */\n        nblk = part_size - bp->b_blkno;\n        if (nblk <= 0) {\n            bp->b_error = EINVAL;\n            bp->b_flags |= B_ERROR;\n            biodone(bp);\n            return;\n        }\n        bp->b_bcount = nblk << DEV_BSHIFT;\n    }\n\n    if (bp->b_dev == swapdev) {\n        led_control(LED_SWAP, 1);\n    } else {\n        led_control(LED_DISK, 1);\n    }\n\n    s = splbio();\n#ifdef UCB_METER\n    if (sramc_dkindex >= 0) {\n        dk_busy |= 1 << sramc_dkindex;\n        dk_xfer[sramc_dkindex]++;\n        dk_bytes[sramc_dkindex] += bp->b_bcount;\n    }\n#endif\n\n    if (bp->b_flags & B_READ) {\n        sramc_read(offset, bp->b_addr, bp->b_bcount);\n    } else {\n        sramc_write(offset, bp->b_addr, bp->b_bcount);\n    }\n\n    biodone(bp);\n    if (bp->b_dev == swapdev) {\n        led_control(LED_SWAP, 0);\n    } else {\n        led_control(LED_DISK, 0);\n    }\n#ifdef UCB_METER\n    if (sramc_dkindex >= 0)\n        dk_busy &= ~(1 << sramc_dkindex);\n#endif\n    splx(s);\n}\n\nint sramc_ioctl(dev_t dev, u_int cmd, caddr_t addr, int flag)\n{\n    int error = 0;\n\n    switch (cmd) {\n\n    case DIOCGETMEDIASIZE:\n        /* Get disk size in kbytes. */\n        *(int*) addr = sramc_size(dev);\n        break;\n\n    default:\n        error = EINVAL;\n        break;\n    }\n    return error;\n}\n\n/*\n * Test to see if device is present.\n * Return true if found and initialized ok.\n */\nstatic int\nsramcprobe(config)\n    struct conf_device *config;\n{\n    /* Only one device unit is supported. */\n    if (config->dev_unit != 0)\n        return 0;\n\n    printf(\"rc0: total %u kbytes, swap space %u kbytes\\n\",\n        SRAMC_TOTAL_KBYTES, SRAMC_SWAP_KBYTES);\n\n    sramc_init();\n\n#ifdef UCB_METER\n    dk_alloc(&sramc_dkindex, 1, \"rc0\");\n#endif\n    return 1;\n}\n\nstruct driver rcdriver = {\n    \"sramc\", sramcprobe,\n};\n"
  },
  {
    "path": "sys/arch/pic32/dev/sramc.h",
    "content": "#ifndef _SRAMC_H\n#define _SRAMC_H\n\n#ifdef KERNEL\nextern int sramc_open(dev_t dev, int flag, int mode);\nextern int sramc_close(dev_t dev, int flag, int mode);\nextern daddr_t sramc_size(dev_t dev);\nextern void sramc_strategy(struct buf *bp);\nextern int sramc_ioctl (dev_t dev, u_int cmd, caddr_t addr, int flag);\n#endif\n\n#endif\n"
  },
  {
    "path": "sys/arch/pic32/dev/uart.c",
    "content": "/*\n * UART driver for PIC32.\n *\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)cons.c\t1.3 (2.11BSD GTE) 1997/4/25\n */\n\n#include <sys/param.h>\n#include <sys/conf.h>\n#include <sys/user.h>\n#include <sys/ioctl.h>\n#include <sys/tty.h>\n#include <sys/systm.h>\n#include <sys/config.h>\n\n#include <pic32/dev/uart.h>\n\n#define CONCAT(x,y) x ## y\n#define BBAUD(x) CONCAT(B,x)\n\n#ifndef UART_BAUD\n#define UART_BAUD 115200\n#endif\n\n/*\n * PIC32 UART registers.\n */\nstruct uartreg {\n    volatile unsigned mode;     /* Mode */\n    volatile unsigned modeclr;\n    volatile unsigned modeset;\n    volatile unsigned modeinv;\n    volatile unsigned sta;      /* Status and control */\n    volatile unsigned staclr;\n    volatile unsigned staset;\n    volatile unsigned stainv;\n    volatile unsigned txreg;    /* Transmit */\n    volatile unsigned unused1;\n    volatile unsigned unused2;\n    volatile unsigned unused3;\n    volatile unsigned rxreg;    /* Receive */\n    volatile unsigned unused4;\n    volatile unsigned unused5;\n    volatile unsigned unused6;\n    volatile unsigned brg;      /* Baud rate */\n    volatile unsigned brgclr;\n    volatile unsigned brgset;\n    volatile unsigned brginv;\n};\n\nstatic struct uartreg *const uart[NUART] = {\n    (struct uartreg*) &U1MODE,\n    (struct uartreg*) &U2MODE,\n    (struct uartreg*) &U3MODE,\n    (struct uartreg*) &U4MODE,\n    (struct uartreg*) &U5MODE,\n    (struct uartreg*) &U6MODE\n};\n\n/*\n * UART interrupt numbers.\n */\nstruct uart_irq {\n    int     er;\n    int     rx;\n    int     tx;\n};\n\nstatic const struct uart_irq uirq[NUART] = {\n    { PIC32_IRQ_U1E, PIC32_IRQ_U1RX, PIC32_IRQ_U1TX },\n    { PIC32_IRQ_U2E, PIC32_IRQ_U2RX, PIC32_IRQ_U2TX },\n    { PIC32_IRQ_U3E, PIC32_IRQ_U3RX, PIC32_IRQ_U3TX },\n    { PIC32_IRQ_U4E, PIC32_IRQ_U4RX, PIC32_IRQ_U4TX },\n    { PIC32_IRQ_U5E, PIC32_IRQ_U5RX, PIC32_IRQ_U5TX },\n    { PIC32_IRQ_U6E, PIC32_IRQ_U6RX, PIC32_IRQ_U6TX },\n};\n\nstruct tty uartttys[NUART];\n\nstatic unsigned speed_bps [NSPEEDS] = {\n    0,       50,      75,      150,     200,    300,     600,     1200,\n    1800,    2400,    4800,    9600,    19200,  38400,   57600,   115200,\n    230400,  460800,  500000,  576000,  921600, 1000000, 1152000, 1500000,\n    2000000, 2500000, 3000000, 3500000, 4000000\n};\n\nvoid cnstart (struct tty *tp);\n\n/*\n * Setup UART registers.\n * Compute the divisor for 115.2 kbaud.\n */\nvoid uartinit(int unit)\n{\n    register struct uartreg *reg;\n\n    if (unit >= NUART)\n        return;\n\n    switch(unit) {\n    case 0:\n#ifdef UART1_ENA_PORT\n        /* Enable UART1 phy - pin is assumed to be active low */\n        TRIS_CLR(UART1_ENA_PORT) = 1 << UART1_ENA_PIN;\n        LAT_CLR(UART1_ENA_PORT) = 1 << UART1_ENA_PIN;\n        udelay(2500);\n#endif\n        break;\n    case 1:\n#ifdef UART2_ENA_PORT\n        /* Enable UART2 phy - pin is assumed to be active low */\n        TRIS_CLR(UART2_ENA_PORT) = 1 << UART2_ENA_PIN;\n        LAT_CLR(UART2_ENA_PORT) = 1 << UART2_ENA_PIN;\n        udelay(2500);\n#endif\n        break;\n    case 2:\n#ifdef UART3_ENA_PORT\n        /* Enable UART3 phy - pin is assumed to be active low */\n        TRIS_CLR(UART3_ENA_PORT) = 1 << UART3_ENA_PIN;\n        LAT_CLR(UART3_ENA_PORT) = 1 << UART3_ENA_PIN;\n        udelay(2500);\n#endif\n        break;\n    case 3:\n#ifdef UART4_ENA_PORT\n        /* Enable UART4 phy - pin is assumed to be active low */\n        TRIS_CLR(UART4_ENA_PORT) = 1 << UART4_ENA_PIN;\n        LAT_CLR(UART4_ENA_PORT) = 1 << UART4_ENA_PIN;\n        udelay(2500);\n#endif\n        break;\n    case 4:\n#ifdef UART5_ENA_PORT\n        /* Enable UART5 phy - pin is assumed to be active low */\n        TRIS_CLR(UART5_ENA_PORT) = 1 << UART5_ENA_PIN;\n        LAT_CLR(UART5_ENA_PORT) = 1 << UART5_ENA_PIN;\n        udelay(2500);\n#endif\n        break;\n    case 5:\n#ifdef UART6_ENA_PORT\n        /* Enable UART6 phy - pin is assumed to be active low */\n        TRIS_CLR(UART6_ENA_PORT) = 1 << UART6_ENA_PIN;\n        LAT_CLR(UART6_ENA_PORT) = 1 << UART6_ENA_PIN;\n        udelay(2500);\n#endif\n        break;\n    }\n\n    reg = uart[unit];\n    reg->brg = PIC32_BRG_BAUD (BUS_KHZ * 1000, UART_BAUD);\n    reg->sta = 0;\n    reg->mode =\n        PIC32_UMODE_PDSEL_8NPAR |   /* 8-bit data, no parity */\n        PIC32_UMODE_ON;             /* UART Enable */\n    reg->staset =\n        PIC32_USTA_URXEN |          /* Receiver Enable */\n        PIC32_USTA_UTXEN;           /* Transmit Enable */\n}\n\nint uartopen(dev_t dev, int flag, int mode)\n{\n    register struct uartreg *reg;\n    register struct tty *tp;\n    register int unit = minor(dev);\n\n    if (unit >= NUART)\n        return (ENXIO);\n\n    tp = &uartttys[unit];\n    if (! tp->t_addr)\n        return (ENXIO);\n\n    reg = (struct uartreg*) tp->t_addr;\n    tp->t_oproc = uartstart;\n    if ((tp->t_state & TS_ISOPEN) == 0) {\n        if (tp->t_ispeed == 0) {\n            tp->t_ispeed = BBAUD(UART_BAUD);\n            tp->t_ospeed = BBAUD(UART_BAUD);\n        }\n        ttychars(tp);\n        tp->t_state = TS_ISOPEN | TS_CARR_ON;\n        tp->t_flags = ECHO | XTABS | CRMOD | CRTBS | CRTERA | CTLECH | CRTKIL;\n    }\n    if ((tp->t_state & TS_XCLUDE) && u.u_uid != 0)\n        return (EBUSY);\n\n    reg->sta = 0;\n    reg->brg = PIC32_BRG_BAUD (BUS_KHZ * 1000, speed_bps [tp->t_ospeed]);\n    reg->mode = PIC32_UMODE_PDSEL_8NPAR |\n                PIC32_UMODE_ON;\n    reg->staset = PIC32_USTA_URXEN | PIC32_USTA_UTXEN;\n\n    /* Enable receive interrupt. */\n    if (uirq[unit].rx < 32) {\n            IECSET(0) = 1 << uirq[unit].rx;\n    } else if (uirq[unit].rx < 64) {\n            IECSET(1) = 1 << (uirq[unit].rx-32);\n    } else {\n            IECSET(2) = 1 << (uirq[unit].rx-64);\n    }\n    return ttyopen(dev, tp);\n}\n\n/*ARGSUSED*/\nint\nuartclose (dev_t dev, int flag, int mode)\n{\n    register int unit = minor(dev);\n    register struct tty *tp = &uartttys[unit];\n\n    if (! tp->t_addr)\n        return ENODEV;\n\n    ttywflush(tp);\n    ttyclose(tp);\n    return(0);\n}\n\n/*ARGSUSED*/\nint\nuartread (dev, uio, flag)\n    dev_t dev;\n    struct uio *uio;\n    int flag;\n{\n    register int unit = minor(dev);\n    register struct tty *tp = &uartttys[unit];\n\n    if (! tp->t_addr)\n        return ENODEV;\n\n    return ttread(tp, uio, flag);\n}\n\n/*ARGSUSED*/\nint\nuartwrite (dev, uio, flag)\n    dev_t dev;\n    struct uio *uio;\n    int flag;\n{\n    register int unit = minor(dev);\n    register struct tty *tp = &uartttys[unit];\n\n    if (! tp->t_addr)\n        return ENODEV;\n\n    return ttwrite(tp, uio, flag);\n}\n\nint\nuartselect (dev, rw)\n    register dev_t dev;\n    int rw;\n{\n    register int unit = minor(dev);\n    register struct tty *tp = &uartttys[unit];\n\n    if (! tp->t_addr)\n        return ENODEV;\n\n    return (ttyselect (tp, rw));\n}\n\n/*ARGSUSED*/\nint\nuartioctl (dev, cmd, addr, flag)\n    dev_t dev;\n    register u_int cmd;\n    caddr_t addr;\n    int flag;\n{\n    register int unit = minor(dev);\n    register struct tty *tp = &uartttys[unit];\n    register int error;\n\n    if (! tp->t_addr)\n        return ENODEV;\n\n    error = ttioctl(tp, cmd, addr, flag);\n    if (error < 0)\n        error = ENOTTY;\n    return (error);\n}\n\nvoid\nuartintr (dev)\n    dev_t dev;\n{\n    register int c;\n    register int unit = minor(dev);\n    register struct tty *tp = &uartttys[unit];\n    register struct uartreg *reg = (struct uartreg *)tp->t_addr;\n\n    if (! tp->t_addr)\n        return;\n\n    /* Receive */\n    while (reg->sta & PIC32_USTA_URXDA) {\n        c = reg->rxreg;\n        ttyinput(c, tp);\n    }\n    if (reg->sta & PIC32_USTA_OERR)\n        reg->staclr = PIC32_USTA_OERR;\n\n    if (uirq[unit].rx < 32) {\n        IFSCLR(0) = (1 << uirq[unit].rx) | (1 << uirq[unit].er);\n    } else if (uirq[unit].rx < 64) {\n        IFSCLR(1) = (1 << (uirq[unit].rx-32)) | (1 << (uirq[unit].er-32));\n    } else {\n        IFSCLR(2) = (1 << (uirq[unit].rx-64)) | (1 << (uirq[unit].er-64));\n    }\n\n    /* Transmit */\n    if (reg->sta & PIC32_USTA_TRMT) {\n        led_control (LED_TTY, 0);\n\n        if (uirq[unit].tx < 32) {\n            IECCLR(0) = 1 << uirq[unit].tx;\n            IFSCLR(0) = 1 << uirq[unit].tx;\n        } else if (uirq[unit].tx < 64) {\n            IECCLR(1) = 1 << (uirq[unit].tx - 32);\n            IFSCLR(1) = 1 << (uirq[unit].tx - 32);\n        } else {\n            IECCLR(2) = 1 << (uirq[unit].tx - 64);\n            IFSCLR(2) = 1 << (uirq[unit].tx - 64);\n        }\n\n        if (tp->t_state & TS_BUSY) {\n            tp->t_state &= ~TS_BUSY;\n            ttstart(tp);\n        }\n    }\n}\n\nvoid uartstart (register struct tty *tp)\n{\n    register struct uartreg *reg = (struct uartreg*) tp->t_addr;\n    register int c, s;\n    register int unit = minor(tp->t_dev);\n\n    if (! tp->t_addr)\n        return;\n\n    s = spltty();\n    if (tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) {\nout:    /* Disable transmit_interrupt. */\n        led_control (LED_TTY, 0);\n        splx (s);\n        return;\n    }\n    ttyowake(tp);\n    if (tp->t_outq.c_cc == 0)\n        goto out;\n\n    if (reg->sta & PIC32_USTA_TRMT) {\n        c = getc(&tp->t_outq);\n        reg->txreg = c & 0xff;\n        tp->t_state |= TS_BUSY;\n    }\n\n    /* Enable transmit interrupt. */\n    if (uirq[unit].tx < 32) {\n        IECSET(0) = 1 << uirq[unit].tx;\n    } else if (uirq[unit].tx < 64) {\n        IECSET(1) = 1 << (uirq[unit].tx - 32);\n    } else {\n        IECSET(2) = 1 << (uirq[unit].tx - 64);\n    }\n    led_control (LED_TTY, 1);\n    splx (s);\n}\n\nvoid uartputc(dev_t dev, char c)\n{\n    int unit = minor(dev);\n    struct tty *tp = &uartttys[unit];\n    register struct uartreg *reg = uart[unit];\n    register int s, timo;\n\n    s = spltty();\nagain:\n    /*\n     * Try waiting for the console tty to come ready,\n     * otherwise give up after a reasonable time.\n     */\n    timo = 30000;\n    while ((reg->sta & PIC32_USTA_TRMT) == 0)\n        if (--timo == 0)\n            break;\n\n    if (tp->t_state & TS_BUSY) {\n        uartintr (dev);\n        goto again;\n    }\n    led_control (LED_TTY, 1);\n    reg->txreg = c;\n\n    timo = 30000;\n    while ((reg->sta & PIC32_USTA_TRMT) == 0)\n        if (--timo == 0)\n            break;\n\n    /* Clear TX interrupt. */\n    if (uirq[unit].tx < 32) {\n        IECCLR(0) = 1 << uirq[unit].tx;\n    } else if (uirq[unit].tx < 64) {\n        IECCLR(1) = 1 << (uirq[unit].tx - 32);\n    } else {\n        IECCLR(2) = 1 << (uirq[unit].tx - 64);\n    }\n    led_control(LED_TTY, 0);\n    splx(s);\n}\n\nchar uartgetc(dev_t dev)\n{\n    int unit = minor(dev);\n    register struct uartreg *reg = uart[unit];\n    int s, c;\n\n    s = spltty();\n    for (;;) {\n        /* Wait for key pressed. */\n        if (reg->sta & PIC32_USTA_URXDA) {\n            c = reg->rxreg;\n            break;\n        }\n    }\n\n    if (uirq[unit].rx < 32) {\n        IFSCLR(0) = (1 << uirq[unit].rx) | (1 << uirq[unit].er);\n    } else if (uirq[unit].rx < 64) {\n        IFSCLR(1) = (1 << (uirq[unit].rx-32)) | (1 << (uirq[unit].er-32));\n    } else {\n        IFSCLR(2) = (1 << (uirq[unit].rx-64)) | (1 << (uirq[unit].er-64));\n    }\n    splx(s);\n    return (unsigned char) c;\n}\n\n/*\n * Test to see if device is present.\n * Return true if found and initialized ok.\n */\nstatic int\nuartprobe(config)\n    struct conf_device *config;\n{\n    int unit = config->dev_unit - 1;\n    int is_console = (CONS_MAJOR == UART_MAJOR &&\n                      CONS_MINOR == unit);\n    int rx, tx;\n    static const int rx_tab[NUART] = {\n        GPIO_PIN('D',2),    /* U1RX: 64pin - RD2, 100pin - RF2 */\n        GPIO_PIN('F',4),    /* U2RX */\n        GPIO_PIN('G',7),    /* U3RX */\n        GPIO_PIN('D',9),    /* U4RX: 64pin - RD9, 100pin - RD14 */\n        GPIO_PIN('B',8),    /* U5RX: 64pin - RB8, 100pin - RF12 */\n        GPIO_PIN('G',9),    /* U6RX */\n    };\n    static const int tx_tab[NUART] = {\n        GPIO_PIN('D',3),    /* U1TX: 64pin - RD3, 100pin - RF8 */\n        GPIO_PIN('F',5),    /* U2TX */\n        GPIO_PIN('G',8),    /* U3TX */\n        GPIO_PIN('D',1),    /* U4TX: 64pin - RD1, 100pin - RD15 */\n        GPIO_PIN('B',14),   /* U5TX: 64pin - RB14, 100pin - RF13 */\n        GPIO_PIN('G',6),    /* U6TX */\n    };\n\n    if (unit < 0 || unit >= NUART)\n        return 0;\n    rx = rx_tab[unit];\n    tx = tx_tab[unit];\n    if (cpu_pins > 64) {\n        /* Ports UART1, UART4 and UART5 have different pin assignments\n         * for 100-pin packages. */\n        switch (unit + 1) {\n        case 1:\n            rx = GPIO_PIN('F',2);\n            tx = GPIO_PIN('F',8);\n            break;\n        case 4:\n            rx = GPIO_PIN('D',14);\n            tx = GPIO_PIN('D',15);\n            break;\n        case 5:\n            rx = GPIO_PIN('F',12);\n            tx = GPIO_PIN('F',13);\n            break;\n        }\n    }\n    printf(\"uart%d: pins rx=R%c%d/tx=R%c%d, interrupts %u/%u/%u\", unit+1,\n        gpio_portname(rx), gpio_pinno(rx),\n        gpio_portname(tx), gpio_pinno(tx),\n        uirq[unit].er, uirq[unit].rx, uirq[unit].tx);\n    if (is_console)\n        printf(\", console\");\n    printf(\"\\n\");\n\n    /* Initialize the device. */\n    uartttys[unit].t_addr = (caddr_t) uart[unit];\n    if (! is_console)\n        uartinit(unit);\n    return 1;\n}\n\nstruct driver uartdriver = {\n    \"uart\", uartprobe,\n};\n"
  },
  {
    "path": "sys/arch/pic32/dev/uart.h",
    "content": "#ifndef _UART_H\n#define _UART_H\n\n#define NUART 6\n\n#ifdef KERNEL\n\nvoid uartinit(int unit);\nint uartopen(dev_t dev, int flag, int mode);\nint uartclose(dev_t dev, int flag, int mode);\nint uartread(dev_t dev, struct uio * uio, int flag);\nint uartwrite(dev_t dev, struct uio *uio, int flag);\nint uartselect(dev_t dev, int rw);\nint uartioctl(dev_t dev, u_int cmd, caddr_t addr, int flag);\nvoid uartintr(dev_t dev);\nvoid uartstart(struct tty *tp);\nvoid uartputc(dev_t dev, char c);\nchar uartgetc(dev_t dev);\n\nextern struct tty uartttys[NUART];\n\n#endif\n\n#endif\n"
  },
  {
    "path": "sys/arch/pic32/dev/usb_uart.c",
    "content": "/*\n * Console driver via USB.\n *\n * Copyright (C) 2011 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/param.h>\n#include <sys/conf.h>\n#include <sys/systm.h>\n#include <sys/user.h>\n#include <sys/ioctl.h>\n#include <sys/tty.h>\n#include <sys/config.h>\n\n#include <machine/pic32mx.h>\n\n#include <pic32/hal/usb_device.h>\n#include <pic32/hal/usb_function_cdc.h>\n\n#define CONCAT(x,y) x ## y\n#define BBAUD(x) CONCAT(B,x)\n\n#ifndef UARTUSB_BAUD\n#define UARTUSB_BAUD 115200\n#endif\n\nstatic unsigned speed_bps [NSPEEDS] = {\n    0,      50,     75,     150,    200,    300,    600,    1200,\n    1800,   2400,   4800,   9600,   19200,  38400,  57600,  115200,\n    230400, 460800, 500000, 576000, 921600, 1000000, 1152000, 1500000,\n    2000000, 2500000, 3000000, 3500000, 4000000\n};\n\n\nstruct tty usbttys [1];\n\nvoid usbstart (struct tty *tp);\nint usbopen (dev_t dev, int flag, int mode);\n\n/*\n * Initialize USB module SFRs and firmware variables to known state.\n * Enable interrupts.\n */\nvoid usbinit()\n{\n    usb_device_init();\n    IECSET(1) = 1 << (PIC32_IRQ_USB - 32);\n\n#if !defined(USB_AUTOBOOT)\n    /* Wait for any user input. */\n    while (! cdc_consume(0))\n#endif\n        usb_device_tasks();\n}\n\nint usbopen (dev_t dev, int flag, int mode)\n{\n    register struct tty *tp = &usbttys[0];\n\n    tp->t_oproc = usbstart;\n\n    if ((tp->t_state & TS_ISOPEN) == 0) {\n        tp->t_ispeed = BBAUD(UARTUSB_BAUD);\n        tp->t_ospeed = BBAUD(UARTUSB_BAUD);\n        ttychars(tp);\n        tp->t_state = TS_ISOPEN | TS_CARR_ON;\n        tp->t_flags = ECHO | XTABS | CRMOD | CRTBS | CRTERA | CTLECH | CRTKIL;\n    }\n    if ((tp->t_state & TS_XCLUDE) && u.u_uid != 0)\n        return (EBUSY);\n\n    if (tp->t_ispeed == 0) {\n        tp->t_ispeed = BBAUD(UARTUSB_BAUD);\n        tp->t_ospeed = BBAUD(UARTUSB_BAUD);\n    }\n    cdc_set_line_coding(speed_bps[tp->t_ospeed], NUM_STOP_BITS_1, PARITY_NONE, 8);\n    return ttyopen (dev, tp);\n}\n\nint usbclose (dev, flag, mode)\n    dev_t dev;\n    int flag;\n    int mode;\n{\n    register struct tty *tp = &usbttys[0];\n\n    ttywflush(tp);\n    ttyclose (tp);\n    return 0;\n}\n\nint usbread (dev, uio, flag)\n    dev_t dev;\n    struct uio *uio;\n    int flag;\n{\n    register struct tty *tp = &usbttys[0];\n\n    return ttread (tp, uio, flag);\n}\n\nint usbwrite (dev, uio, flag)\n    dev_t dev;\n    struct uio *uio;\n    int flag;\n{\n    register struct tty *tp = &usbttys[0];\n\n    return ttwrite (tp, uio, flag);\n}\n\nint usbioctl (dev, cmd, addr, flag)\n    dev_t dev;\n    register u_int cmd;\n    caddr_t addr;\n    int flag;\n{\n    register struct tty *tp = &usbttys[0];\n    register int error;\n\n    error = ttioctl (tp, cmd, addr, flag);\n    if (error < 0)\n            error = ENOTTY;\n    return error;\n}\n\nint usbselect (dev, rw)\n    register dev_t dev;\n    int rw;\n{\n    register struct tty *tp = &usbttys[0];\n\n    return ttyselect (tp, rw);\n}\n\nvoid usbstart (tp)\n    register struct tty *tp;\n{\n    register int s;\n\n    s = spltty();\n    if (tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) {\nout:    /* Disable transmit_interrupt. */\n        led_control (LED_TTY, 0);\n        splx (s);\n        return;\n    }\n    ttyowake(tp);\n    if (tp->t_outq.c_cc == 0)\n        goto out;\n    if (cdc_is_tx_ready()) {\n        while (tp->t_outq.c_cc != 0) {\n            int c = getc (&tp->t_outq);\n            if (cdc_putc (c) == 0)\n                break;\n        }\n        cdc_tx_service();\n        tp->t_state |= TS_BUSY;\n    }\n    led_control (LED_TTY, 1);\n    splx (s);\n}\n\n/*\n * Put a symbol on console terminal.\n */\nvoid usbputc(dev_t dev, char c)\n{\n    register int s;\n\n    s = spltty();\n    while (! cdc_is_tx_ready()) {\n        usb_device_tasks();\n        cdc_tx_service();\n    }\n    led_control (LED_TTY, 1);\n    cdc_putc (c);\n    cdc_tx_service();\n\n    while (! cdc_is_tx_ready()) {\n        cdc_tx_service();\n        usb_device_tasks();\n    }\n\n    led_control (LED_TTY, 0);\n    splx (s);\n}\n\nstatic int getc_data;\n\n/*\n * Receive a character for getc.\n */\nstatic void store_char (int c)\n{\n    getc_data = (unsigned char) c;\n}\n\n/*\n * Receive a symbol from console terminal.\n */\nchar usbgetc(dev_t dev)\n{\n    register int s;\n\n    s = spltty();\n    for (getc_data = -1; getc_data < 0; ) {\n        usb_device_tasks();\n        cdc_consume (store_char);\n        cdc_tx_service();\n    }\n    splx (s);\n    return getc_data;\n}\n\n/*\n * Receive a character from CDC.\n */\nstatic void usb_rx (int c)\n{\n    register struct tty *tp = &usbttys[0];\n\n    if ((tp->t_state & TS_ISOPEN) == 0)\n        return;\n    ttyinput (c, tp);\n}\n\n/*\n * Check bus status and service USB interrupts.\n */\nvoid usbintr (int chan)\n{\n    register struct tty *tp = &usbttys[0];\n\n    // Must call this function from interrupt or periodically.\n    usb_device_tasks();\n\n    // Check that USB connection is established.\n    if (usb_device_state < CONFIGURED_STATE ||\n        (U1PWRC & PIC32_U1PWRC_USUSPEND))\n        return;\n\n    // Receive data from user.\n    cdc_consume (usb_rx);\n\n    if (cdc_is_tx_ready()) {\n        // Transmitter empty.\n        led_control (LED_TTY, 0);\n\n        if (tp->t_state & TS_BUSY) {\n            tp->t_state &= ~TS_BUSY;\n            ttstart (tp);\n        }\n    }\n\n    // Transmit data to user.\n    cdc_tx_service();\n}\n\n/*\n * Test to see if device is present.\n * Return true if found and initialized ok.\n */\nstatic int\nusbprobe(config)\n    struct conf_device *config;\n{\n    int is_console = (CONS_MAJOR == UARTUSB_MAJOR);\n\n    printf(\"uartusb: port USB, interrupt %u\", PIC32_VECT_USB);\n    if (is_console)\n        printf(\", console\");\n    printf(\"\\n\");\n    return 1;\n}\n\nstruct driver uartusbdriver = {\n    \"uartusb\", usbprobe,\n};\n\n/*\n * USB Callback Functions\n */\n\n/*\n * This function is called when the device becomes initialized.\n * It should initialize the endpoints for the device's usage\n * according to the current configuration.\n */\nvoid usbcb_init_ep()\n{\n    cdc_init_ep();\n}\n\n/*\n * Process device-specific SETUP requests.\n */\nvoid usbcb_check_other_req()\n{\n    cdc_check_request();\n}\n\n#if 0\n/*\n * Wake up a host PC.\n */\nvoid usb_send_resume (void)\n{\n    /* Start RESUME signaling. */\n    U1CON |= PIC32_U1CON_RESUME;\n\n    /* Set RESUME line for 1-13 ms. */\n    udelay (5000);\n\n    U1CON &= ~PIC32_U1CON_RESUME;\n}\n#endif\n\n#ifndef CONSOLE_VID\n#   define CONSOLE_VID 0x04D8   // Vendor ID: Microchip\n#endif\n#ifndef CONSOLE_PID\n#   define CONSOLE_PID 0x000A   // Product ID: CDC RS-232 Emulation Demo\n#endif\n\n/*\n * Device Descriptor\n */\nconst USB_DEVICE_DESCRIPTOR usb_device = {\n    sizeof(usb_device),     // Size of this descriptor in bytes\n    USB_DESCRIPTOR_DEVICE,  // DEVICE descriptor type\n    0x0200,                 // USB Spec Release Number in BCD format\n    CDC_DEVICE,             // Class Code\n    0x00,                   // Subclass code\n    0x00,                   // Protocol code\n    USB_EP0_BUFF_SIZE,      // Max packet size for EP0, see usb_config.h\n    CONSOLE_VID,            // Vendor ID\n    CONSOLE_PID,            // Product ID\n    0x0100,                 // Device release number in BCD format\n    0x01,                   // Manufacturer string index\n    0x02,                   // Product string index\n    0x00,                   // Device serial number string index\n    0x01                    // Number of possible configurations\n};\n\n/*\n * Configuration 1 Descriptor\n */\nconst unsigned char usb_config1_descriptor[] =\n{\n    /* Configuration Descriptor */\n    9,                                  // sizeof(USB_CFG_DSC)\n    USB_DESCRIPTOR_CONFIGURATION,       // CONFIGURATION descriptor type\n    67, 0,                              // Total length of data for this cfg\n    2,                                  // Number of interfaces in this cfg\n    1,                                  // Index value of this configuration\n    0,                                  // Configuration string index\n    _DEFAULT | _SELF,                   // Attributes, see usb_device.h\n    150,                                // Max power consumption (2X mA)\n\n    /* Interface Descriptor */\n    9,                                  // sizeof(USB_INTF_DSC)\n    USB_DESCRIPTOR_INTERFACE,           // INTERFACE descriptor type\n    0,                                  // Interface Number\n    0,                                  // Alternate Setting Number\n    1,                                  // Number of endpoints in this intf\n    COMM_INTF,                          // Class code\n    ABSTRACT_CONTROL_MODEL,             // Subclass code\n    V25TER,                             // Protocol code\n    0,                                  // Interface string index\n\n    /* CDC Class-Specific Descriptors */\n    sizeof(USB_CDC_HEADER_FN_DSC),\n    CS_INTERFACE,\n    DSC_FN_HEADER,\n    0x10,0x01,\n\n    sizeof(USB_CDC_ACM_FN_DSC),\n    CS_INTERFACE,\n    DSC_FN_ACM,\n    USB_CDC_ACM_FN_DSC_VAL,\n\n    sizeof(USB_CDC_UNION_FN_DSC),\n    CS_INTERFACE,\n    DSC_FN_UNION,\n    CDC_COMM_INTF_ID,\n    CDC_DATA_INTF_ID,\n\n    sizeof(USB_CDC_CALL_MGT_FN_DSC),\n    CS_INTERFACE,\n    DSC_FN_CALL_MGT,\n    0x00,\n    CDC_DATA_INTF_ID,\n\n    /* Endpoint Descriptor */\n    7,                                  // sizeof(USB_EP_DSC)\n    USB_DESCRIPTOR_ENDPOINT,            // Endpoint Descriptor\n    _EP02_IN,                           // EndpointAddress\n    _INTERRUPT,                         // Attributes\n    0x08, 0x00,                         // size\n    0x02,                               // Interval\n\n    /* Interface Descriptor */\n    9,                                  // sizeof(USB_INTF_DSC)\n    USB_DESCRIPTOR_INTERFACE,           // INTERFACE descriptor type\n    1,                                  // Interface Number\n    0,                                  // Alternate Setting Number\n    2,                                  // Number of endpoints in this intf\n    DATA_INTF,                          // Class code\n    0,                                  // Subclass code\n    NO_PROTOCOL,                        // Protocol code\n    0,                                  // Interface string index\n\n    /* Endpoint Descriptor */\n    7,                                  // sizeof(USB_EP_DSC)\n    USB_DESCRIPTOR_ENDPOINT,            // Endpoint Descriptor\n    _EP03_OUT,                          // EndpointAddress\n    _BULK,                              // Attributes\n    0x40, 0x00,                         // size\n    0x00,                               // Interval\n\n    /* Endpoint Descriptor */\n    7,                                  // sizeof(USB_EP_DSC)\n    USB_DESCRIPTOR_ENDPOINT,            // Endpoint Descriptor\n    _EP03_IN,                           // EndpointAddress\n    _BULK,                              // Attributes\n    0x40, 0x00,                         // size\n    0x00,                               // Interval\n};\n\n\n/*\n * Language code string descriptor.\n */\nstatic const USB_STRING_INIT(1) string0_descriptor = {\n    sizeof(string0_descriptor),\n    USB_DESCRIPTOR_STRING,\n    { 0x0409 }                          /* US English */\n};\n\n/*\n * Manufacturer string descriptor\n */\nstatic const USB_STRING_INIT(25) string1_descriptor = {\n    sizeof(string1_descriptor),\n    USB_DESCRIPTOR_STRING,\n    { 'M','i','c','r','o','c','h','i','p',' ',\n      'T','e','c','h','n','o','l','o','g','y',\n      ' ','I','n','c','.', },\n};\n\n/*\n * Product string descriptor\n */\nstatic const USB_STRING_INIT(16) string2_descriptor = {\n    sizeof(string2_descriptor),\n    USB_DESCRIPTOR_STRING,\n    { 'R','e','t','r','o','B','S','D',' ','C',\n      'o','n','s','o','l','e', },\n};\n\n/*\n * Array of configuration descriptors\n */\nconst unsigned char *const usb_config[] = {\n    (const unsigned char *const) &usb_config1_descriptor,\n};\n\n/*\n * Array of string descriptors\n */\nconst unsigned char *const usb_string[USB_NUM_STRING_DESCRIPTORS] = {\n    (const unsigned char *const) &string0_descriptor,\n    (const unsigned char *const) &string1_descriptor,\n    (const unsigned char *const) &string2_descriptor,\n};\n"
  },
  {
    "path": "sys/arch/pic32/dev/usb_uart.h",
    "content": "/*\n * Console driver via USB.\n *\n * Copyright (C) 2011 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#ifndef _USB_UART_H\n#define _USB_UART_H\n\n#define USB_MAJOR 13\n\nextern struct tty usbttys[1];\nextern void usbinit();\nextern int usbopen(dev_t dev, int flag, int mode);\nextern int usbclose(dev_t dev, int flag, int mode);\nextern int usbread(dev_t dev, struct uio *uio, int flag);\nextern int usbwrite(dev_t dev, struct uio *uio, int flag);\nextern int usbioctl(dev_t dev, register u_int cmd, caddr_t addr, int flag);\nextern int usbselect(dev_t dev, int rw);\nextern void usbstart (register struct tty *tp);\nextern void usbputc(dev_t dev, char c);\nextern char usbgetc(dev_t dev);\nextern void usbintr(int chan);\n\n#endif\n"
  },
  {
    "path": "sys/arch/pic32/hal/usb_ch9.h",
    "content": "/*\n * USB Chapter 9 Protocol (Header File)\n *\n * This file defines data structures, constants, and macros that are used to\n * to support the USB Device Framework protocol described in Chapter 9 of the\n * USB 2.0 specification.\n *\n * The software supplied herewith by Microchip Technology Incorporated\n * (the 'Company') for its PICmicro(R) Microcontroller is intended and\n * supplied to you, the Company's customer, for use solely and\n * exclusively on Microchip PICmicro Microcontroller products. The\n * software is owned by the Company and/or its supplier, and is\n * protected under applicable copyright laws. All rights are reserved.\n * Any use in violation of the foregoing restrictions may subject the\n * user to criminal sanctions under applicable laws, as well as to\n * civil liability for the breach of the terms and conditions of this\n * license.\n *\n * THIS SOFTWARE IS PROVIDED IN AN 'AS IS' CONDITION. NO WARRANTIES,\n * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED\n * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\n * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT,\n * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR\n * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n */\n#ifndef _USB_CH9_H_\n#define _USB_CH9_H_\n\n//\n// Section: USB Descriptors\n//\n#define USB_DESCRIPTOR_DEVICE           0x01    // bDescriptorType for a Device Descriptor.\n#define USB_DESCRIPTOR_CONFIGURATION    0x02    // bDescriptorType for a Configuration Descriptor.\n#define USB_DESCRIPTOR_STRING           0x03    // bDescriptorType for a String Descriptor.\n#define USB_DESCRIPTOR_INTERFACE        0x04    // bDescriptorType for an Interface Descriptor.\n#define USB_DESCRIPTOR_ENDPOINT         0x05    // bDescriptorType for an Endpoint Descriptor.\n#define USB_DESCRIPTOR_DEVICE_QUALIFIER 0x06    // bDescriptorType for a Device Qualifier.\n#define USB_DESCRIPTOR_OTHER_SPEED      0x07    // bDescriptorType for a Other Speed Configuration.\n#define USB_DESCRIPTOR_INTERFACE_POWER  0x08    // bDescriptorType for Interface Power.\n#define USB_DESCRIPTOR_OTG              0x09    // bDescriptorType for an OTG Descriptor.\n\n/*\n * USB Device Descriptor Structure\n *\n * This struct defines the structure of a USB Device Descriptor.  Note that this\n * structure may need to be packed, or even accessed as bytes, to properly access\n * the correct fields when used on some device architectures.\n */\ntypedef struct __attribute__ ((packed)) _USB_DEVICE_DESCRIPTOR\n{\n    unsigned char bLength;              // Length of this descriptor.\n    unsigned char bDescriptorType;      // DEVICE descriptor type (USB_DESCRIPTOR_DEVICE).\n    unsigned short bcdUSB;              // USB Spec Release Number (BCD).\n    unsigned char bDeviceClass;         // Class code (assigned by the USB-IF). 0xFF-Vendor specific.\n    unsigned char bDeviceSubClass;      // Subclass code (assigned by the USB-IF).\n    unsigned char bDeviceProtocol;      // Protocol code (assigned by the USB-IF). 0xFF-Vendor specific.\n    unsigned char bMaxPacketSize0;      // Maximum packet size for endpoint 0.\n    unsigned short idVendor;            // Vendor ID (assigned by the USB-IF).\n    unsigned short idProduct;           // Product ID (assigned by the manufacturer).\n    unsigned short bcdDevice;           // Device release number (BCD).\n    unsigned char iManufacturer;        // Index of String Descriptor describing the manufacturer.\n    unsigned char iProduct;             // Index of String Descriptor describing the product.\n    unsigned char iSerialNumber;        // Index of String Descriptor with the device's serial number.\n    unsigned char bNumConfigurations;   // Number of possible configurations.\n} USB_DEVICE_DESCRIPTOR;\n\n\n/*\n * USB Configuration Descriptor Structure\n *\n * This struct defines the structure of a USB Configuration Descriptor.  Note that this\n * structure may need to be packed, or even accessed as bytes, to properly access\n * the correct fields when used on some device architectures.\n */\ntypedef struct __attribute__ ((packed)) _USB_CONFIGURATION_DESCRIPTOR\n{\n    unsigned char bLength;              // Length of this descriptor.\n    unsigned char bDescriptorType;      // CONFIGURATION descriptor type (USB_DESCRIPTOR_CONFIGURATION).\n    unsigned short wTotalLength;        // Total length of all descriptors for this configuration.\n    unsigned char bNumInterfaces;       // Number of interfaces in this configuration.\n    unsigned char bConfigurationValue;  // Value of this configuration (1 based).\n    unsigned char iConfiguration;       // Index of String Descriptor describing the configuration.\n    unsigned char bmAttributes;         // Configuration characteristics.\n    unsigned char bMaxPower;            // Maximum power consumed by this configuration.\n} USB_CONFIGURATION_DESCRIPTOR;\n\n// Attributes bits\n#define USB_CFG_DSC_REQUIRED    0x80                            // Required attribute\n#define USB_CFG_DSC_SELF_PWR    (0x40 | USB_CFG_DSC_REQUIRED)   // Device is self powered.\n#define USB_CFG_DSC_REM_WAKE    (0x20 | USB_CFG_DSC_REQUIRED)   // Device can request remote wakup\n\n\n/*\n * USB Interface Descriptor Structure\n *\n * This struct defines the structure of a USB Interface Descriptor.  Note that this\n * structure may need to be packed, or even accessed as bytes, to properly access\n * the correct fields when used on some device architectures.\n */\ntypedef struct __attribute__ ((packed)) _USB_INTERFACE_DESCRIPTOR\n{\n    unsigned char bLength;              // Length of this descriptor.\n    unsigned char bDescriptorType;      // INTERFACE descriptor type (USB_DESCRIPTOR_INTERFACE).\n    unsigned char bInterfaceNumber;     // Number of this interface (0 based).\n    unsigned char bAlternateSetting;    // Value of this alternate interface setting.\n    unsigned char bNumEndpoints;        // Number of endpoints in this interface.\n    unsigned char bInterfaceClass;      // Class code (assigned by the USB-IF).  0xFF-Vendor specific.\n    unsigned char bInterfaceSubClass;   // Subclass code (assigned by the USB-IF).\n    unsigned char bInterfaceProtocol;   // Protocol code (assigned by the USB-IF).  0xFF-Vendor specific.\n    unsigned char iInterface;           // Index of String Descriptor describing the interface.\n} USB_INTERFACE_DESCRIPTOR;\n\n\n// *****************************************************************************\n/* USB Endpoint Descriptor Structure\n\nThis struct defines the structure of a USB Endpoint Descriptor.  Note that this\nstructure may need to be packed, or even accessed as bytes, to properly access\nthe correct fields when used on some device architectures.\n*/\ntypedef struct __attribute__ ((packed)) _USB_ENDPOINT_DESCRIPTOR\n{\n    unsigned char bLength;          // Length of this descriptor.\n    unsigned char bDescriptorType;  // ENDPOINT descriptor type (USB_DESCRIPTOR_ENDPOINT).\n    unsigned char bEndpointAddress; // Endpoint address. Bit 7 indicates direction (0=OUT, 1=IN).\n    unsigned char bmAttributes;     // Endpoint transfer type.\n    unsigned short wMaxPacketSize;  // Maximum packet size.\n    unsigned char bInterval;        // Polling interval in frames.\n} USB_ENDPOINT_DESCRIPTOR;\n\n\n// Endpoint Direction\n#define EP_DIR_IN           0x80    // Data flows from device to host\n#define EP_DIR_OUT          0x00    // Data flows from host to device\n\n\n// ******************************************************************\n// USB Endpoint Attributes\n// ******************************************************************\n\n// Section: Transfer Types\n#define EP_ATTR_CONTROL     (0<<0)  // Endoint used for control transfers\n#define EP_ATTR_ISOCH       (1<<0)  // Endpoint used for isochronous transfers\n#define EP_ATTR_BULK        (2<<0)  // Endpoint used for bulk transfers\n#define EP_ATTR_INTR        (3<<0)  // Endpoint used for interrupt transfers\n\n// Section: Synchronization Types (for isochronous enpoints)\n#define EP_ATTR_NO_SYNC     (0<<2)  // No Synchronization\n#define EP_ATTR_ASYNC       (1<<2)  // Asynchronous\n#define EP_ATTR_ADAPT       (2<<2)  // Adaptive synchronization\n#define EP_ATTR_SYNC        (3<<2)  // Synchronous\n\n// Section: Usage Types (for isochronous endpoints)\n#define EP_ATTR_DATA        (0<<4)  // Data Endpoint\n#define EP_ATTR_FEEDBACK    (1<<4)  // Feedback endpoint\n#define EP_ATTR_IMP_FB      (2<<4)  // Implicit Feedback data EP\n\n// Section: Max Packet Sizes\n#define EP_MAX_PKT_INTR_LS  8       // Max low-speed interrupt packet\n#define EP_MAX_PKT_INTR_FS  64      // Max full-speed interrupt packet\n#define EP_MAX_PKT_ISOCH_FS 1023    // Max full-speed isochronous packet\n#define EP_MAX_PKT_BULK_FS  64      // Max full-speed bulk packet\n#define EP_LG_PKT_BULK_FS   32      // Large full-speed bulk packet\n#define EP_MED_PKT_BULK_FS  16      // Medium full-speed bulk packet\n#define EP_SM_PKT_BULK_FS   8       // Small full-speed bulk packet\n\n\n// *****************************************************************************\n/* USB OTG Descriptor Structure\n\nThis struct defines the structure of a USB OTG Descriptor.  Note that this\nstructure may need to be packed, or even accessed as bytes, to properly access\nthe correct fields when used on some device architectures.\n*/\ntypedef struct __attribute__ ((packed)) _USB_OTG_DESCRIPTOR\n{\n    unsigned char bLength;          // Length of this descriptor.\n    unsigned char bDescriptorType;  // OTG descriptor type (USB_DESCRIPTOR_OTG).\n    unsigned char bmAttributes;     // OTG attributes.\n} USB_OTG_DESCRIPTOR;\n\n\n// ******************************************************************\n// Section: USB String Descriptor Structure\n// ******************************************************************\n// This structure describes the USB string descriptor.  The string\n// descriptor provides user-readable information about various aspects of\n// the device.  The first string desriptor (string descriptor zero (0)),\n// provides a list of the number of languages supported by the set of\n// string descriptors for this device instead of an actual string.\n//\n// Note: The strings are in 2-byte-per-character unicode, not ASCII.\n//\n// Note: This structure only describes the \"header\" of the string\n// descriptor.  The actual data (either the language ID array or the\n// array of unicode characters making up the string, must be allocated\n// immediately following this header with no padding between them.\n\ntypedef struct __attribute__ ((packed)) _USB_STRING_DSC\n{\n    unsigned char bLength;          // Size of this descriptor\n    unsigned char bDescriptorType;  // Type, USB_DSC_STRING\n\n} USB_STRING_DESCRIPTOR;\n\n#define USB_STRING_INIT(nchars) struct {\\\n    unsigned char bLength;          \\\n    unsigned char bDescriptorType;  \\\n    unsigned short string[nchars];  \\\n}\n\n\n// ******************************************************************\n// Section: USB Device Qualifier Descriptor Structure\n// ******************************************************************\n// This structure describes the device qualifier descriptor.  The device\n// qualifier descriptor provides overall device information if the device\n// supports \"other\" speeds.\n//\n// Note: A high-speed device may support \"other\" speeds (ie. full or low).\n// If so, it may need to implement the the device qualifier and other\n// speed descriptors.\n\ntypedef struct __attribute__ ((packed)) _USB_DEVICE_QUALIFIER_DESCRIPTOR\n{\n    unsigned char bLength;              // Size of this descriptor\n    unsigned char bType;                // Type, always USB_DESCRIPTOR_DEVICE_QUALIFIER\n    unsigned short bcdUSB;              // USB spec version, in BCD\n    unsigned char bDeviceClass;         // Device class code\n    unsigned char bDeviceSubClass;      // Device sub-class code\n    unsigned char bDeviceProtocol;      // Device protocol\n    unsigned char bMaxPacketSize0;      // EP0, max packet size\n    unsigned char bNumConfigurations;   // Number of \"other-speed\" configurations\n    unsigned char bReserved;            // Always zero (0)\n\n} USB_DEVICE_QUALIFIER_DESCRIPTOR;\n\n\n// ******************************************************************\n// Section: USB Setup Packet Structure\n// ******************************************************************\n// This structure describes the data contained in a USB standard device\n// request's setup packet.  It is the data packet sent from the host to\n// the device to control and configure the device.\n//\n// Note: Refer to the USB 2.0 specification for additional details on the\n// usage of the setup packet and standard device requests.\n\ntypedef struct __attribute__ ((packed))\n{\n    union                               // offset   description\n    {                                   // ------   ------------------------\n        unsigned char bmRequestType;    //   0      Bit-map of request type\n        struct {\n            unsigned recipient:  5;     //          Recipient of the request\n            unsigned type:       2;     //          Type of request\n            unsigned direction:  1;     //          Direction of data X-fer\n        };\n    } requestInfo;\n\n    unsigned char bRequest;             //   1      Request type\n    unsigned short wValue;              //   2      Depends on bRequest\n    unsigned short wIndex;              //   4      Depends on bRequest\n    unsigned short wLength;             //   6      Depends on bRequest\n\n} SETUP_PKT, *PSETUP_PKT;\n\n\n//\n// Section: USB Specification Constants\n//\n\n// Section: Valid PID Values\n#define PID_OUT                             0x1     // PID for an OUT token\n#define PID_ACK                             0x2     // PID for an ACK handshake\n#define PID_DATA0                           0x3     // PID for DATA0 data\n#define PID_PING                            0x4     // Special PID PING\n#define PID_SOF                             0x5     // PID for a SOF token\n#define PID_NYET                            0x6     // PID for a NYET handshake\n#define PID_DATA2                           0x7     // PID for DATA2 data\n#define PID_SPLIT                           0x8     // Special PID SPLIT\n#define PID_IN                              0x9     // PID for a IN token\n#define PID_NAK                             0xA     // PID for a NAK handshake\n#define PID_DATA1                           0xB     // PID for DATA1 data\n#define PID_PRE                             0xC     // Special PID PRE (Same as PID_ERR)\n#define PID_ERR                             0xC     // Special PID ERR (Same as PID_PRE)\n#define PID_SETUP                           0xD     // PID for a SETUP token\n#define PID_STALL                           0xE     // PID for a STALL handshake\n#define PID_MDATA                           0xF     // PID for MDATA data\n\n#define PID_MASK_DATA                       0x03    // Data PID mask\n#define PID_MASK_DATA_SHIFTED               (PID_MASK_DATA << 2) // Data PID shift to proper position\n\n// Section: USB Token Types\n#define USB_TOKEN_OUT                       0x01    // U1TOK - OUT token\n#define USB_TOKEN_IN                        0x09    // U1TOK - IN token\n#define USB_TOKEN_SETUP                     0x0D    // U1TOK - SETUP token\n\n// Section: OTG Descriptor Constants\n\n#define OTG_HNP_SUPPORT                     0x02    // OTG Descriptor bmAttributes - HNP support flag\n#define OTG_SRP_SUPPORT                     0x01    // OTG Descriptor bmAttributes - SRP support flag\n\n// Section: Endpoint Directions\n\n#define USB_IN_EP                           0x80    // IN endpoint mask\n#define USB_OUT_EP                          0x00    // OUT endpoint mask\n\n// Section: Standard Device Requests\n\n#define USB_REQUEST_GET_STATUS              0       // Standard Device Request - GET STATUS\n#define USB_REQUEST_CLEAR_FEATURE           1       // Standard Device Request - CLEAR FEATURE\n#define USB_REQUEST_SET_FEATURE             3       // Standard Device Request - SET FEATURE\n#define USB_REQUEST_SET_ADDRESS             5       // Standard Device Request - SET ADDRESS\n#define USB_REQUEST_GET_DESCRIPTOR          6       // Standard Device Request - GET DESCRIPTOR\n#define USB_REQUEST_SET_DESCRIPTOR          7       // Standard Device Request - SET DESCRIPTOR\n#define USB_REQUEST_GET_CONFIGURATION       8       // Standard Device Request - GET CONFIGURATION\n#define USB_REQUEST_SET_CONFIGURATION       9       // Standard Device Request - SET CONFIGURATION\n#define USB_REQUEST_GET_INTERFACE           10      // Standard Device Request - GET INTERFACE\n#define USB_REQUEST_SET_INTERFACE           11      // Standard Device Request - SET INTERFACE\n#define USB_REQUEST_SYNCH_FRAME             12      // Standard Device Request - SYNCH FRAME\n\n#define USB_FEATURE_ENDPOINT_HALT           0       // CLEAR/SET FEATURE - Endpoint Halt\n#define USB_FEATURE_DEVICE_REMOTE_WAKEUP    1       // CLEAR/SET FEATURE - Device remote wake-up\n#define USB_FEATURE_TEST_MODE               2       // CLEAR/SET FEATURE - Test mode\n\n// Section: Setup Data Constants\n\n#define USB_SETUP_HOST_TO_DEVICE            0x00    // Device Request bmRequestType transfer direction - host to device transfer\n#define USB_SETUP_DEVICE_TO_HOST            0x80    // Device Request bmRequestType transfer direction - device to host transfer\n#define USB_SETUP_TYPE_STANDARD             0x00    // Device Request bmRequestType type - standard\n#define USB_SETUP_TYPE_CLASS                0x20    // Device Request bmRequestType type - class\n#define USB_SETUP_TYPE_VENDOR               0x40    // Device Request bmRequestType type - vendor\n#define USB_SETUP_RECIPIENT_DEVICE          0x00    // Device Request bmRequestType recipient - device\n#define USB_SETUP_RECIPIENT_INTERFACE       0x01    // Device Request bmRequestType recipient - interface\n#define USB_SETUP_RECIPIENT_ENDPOINT        0x02    // Device Request bmRequestType recipient - endpoint\n#define USB_SETUP_RECIPIENT_OTHER           0x03    // Device Request bmRequestType recipient - other\n\n// Section: OTG SET FEATURE Constants\n\n#define OTG_FEATURE_B_HNP_ENABLE            3       // SET FEATURE OTG - Enable B device to perform HNP\n#define OTG_FEATURE_A_HNP_SUPPORT           4       // SET FEATURE OTG - A device supports HNP\n#define OTG_FEATURE_A_ALT_HNP_SUPPORT       5       // SET FEATURE OTG - Another port on the A device supports HNP\n\n// Section: USB Endpoint Transfer Types\n\n#define USB_TRANSFER_TYPE_CONTROL           0x00    // Endpoint is a control endpoint.\n#define USB_TRANSFER_TYPE_ISOCHRONOUS       0x01    // Endpoint is an isochronous endpoint.\n#define USB_TRANSFER_TYPE_BULK              0x02    // Endpoint is a bulk endpoint.\n#define USB_TRANSFER_TYPE_INTERRUPT         0x03    // Endpoint is an interrupt endpoint.\n\n// Section: Standard Feature Selectors for CLEAR_FEATURE Requests\n#define USB_FEATURE_ENDPOINT_STALL          0       // Endpoint recipient\n#define USB_FEATURE_DEVICE_REMOTE_WAKEUP    1       // Device recipient\n#define USB_FEATURE_TEST_MODE               2       // Device recipient\n\n\n// Section: USB Class Code Definitions\n#define USB_HUB_CLASSCODE                   0x09    //  Class code for a hub.\n\n#endif  // _USB_CH9_H_\n"
  },
  {
    "path": "sys/arch/pic32/hal/usb_device.c",
    "content": "/*\n * This file contains functions, macros, definitions, variables,\n * datatypes, etc. that are required for usage with the MCHPFSUSB device\n * stack. This file should be included in projects that use the device stack.\n *\n * The software supplied herewith by Microchip Technology Incorporated\n * (the 'Company') for its PIC(R) Microcontroller is intended and\n * supplied to you, the Company's customer, for use solely and\n * exclusively on Microchip PIC Microcontroller products. The\n * software is owned by the Company and/or its supplier, and is\n * protected under applicable copyright laws. All rights are reserved.\n * Any use in violation of the foregoing restrictions may subject the\n * user to criminal sanctions under applicable laws, as well as to\n * civil liability for the breach of the terms and conditions of this license.\n *\n * THIS SOFTWARE IS PROVIDED IN AN 'AS IS' CONDITION. NO WARRANTIES,\n * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED\n * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\n * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT,\n * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR\n * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n */\n#include <machine/pic32mx.h>\n#include <pic32/hal/usb_device.h>\n\n#if (USB_PING_PONG_MODE != USB_PING_PONG__FULL_PING_PONG)\n    #error \"PIC32 only supports full ping pong mode.\"\n#endif\n\nunsigned usb_device_state;\nunsigned usb_active_configuration;\nstatic unsigned char usb_alternate_interface[USB_MAX_NUM_INT];\nstatic volatile BDT_ENTRY *pBDTEntryEP0OutCurrent;\nstatic volatile BDT_ENTRY *pBDTEntryEP0OutNext;\nstatic volatile BDT_ENTRY *pBDTEntryOut[USB_MAX_EP_NUMBER+1];\nstatic volatile BDT_ENTRY *pBDTEntryIn[USB_MAX_EP_NUMBER+1];\nstatic unsigned short_packet_status;\nstatic unsigned control_transfer_state;\nstatic unsigned ustat_saved;\nIN_PIPE usb_in_pipe[1];\nOUT_PIPE usb_out_pipe[1];\nint usb_remote_wakeup;\n\n/*\n * Section A: Buffer Descriptor Table\n * - 0x400 - 0x4FF(max)\n * - USB_MAX_EP_NUMBER is defined in target.cfg\n */\nvolatile BDT_ENTRY usb_buffer [(USB_MAX_EP_NUMBER + 1) * 4] __attribute__ ((aligned (512)));\n\n/*\n * Section B: EP0 Buffer Space\n */\nvolatile CTRL_TRF_SETUP usb_setup_pkt;           // 8-byte only\n\n// Buffer for control transfer data\nstatic volatile unsigned char ctrl_trf_data [USB_EP0_BUFF_SIZE];\n\n/*\n * This function initializes the device stack\n * it in the default state\n *\n * The USB module will be completely reset including\n * all of the internal variables, registers, and\n * interrupt flags.\n */\nvoid usb_device_init(void)\n{\n    unsigned i;\n\n    // Clear all USB error flags\n    U1EIR = 0xFF;\n\n    // Clears all USB interrupts\n    U1IR = 0xFF;\n\n    U1EIE = 0x9F;                   // Unmask all USB error interrupts\n    U1IE = PIC32_U1I_URST |         // Unmask Reset interrupt\n           PIC32_U1I_IDLE |         // Unmask Idle interrupt\n           PIC32_U1I_UERR |         // Unmask Error interrupt\n           PIC32_U1I_TRN;           // Transaction Complete Interrupt\n\n    // Power up the module\n    U1PWRC |= PIC32_U1PWRC_USBPWR;\n\n    // Set the address of the BDT (if applicable)\n    U1BDTP1 = (unsigned) usb_buffer >> 8;\n\n    // Reset all of the Ping Pong buffers\n    U1CON |= PIC32_U1CON_PPBRST;\n    U1CON &= ~PIC32_U1CON_PPBRST;\n\n    // Reset to default address\n    U1ADDR = 0x00;\n\n    // Clear all of the endpoint control registers\n    for (i=1; i<USB_MAX_EP_NUMBER; i++)\n        U1EP(i) = 0;\n\n    // Clear all of the BDT entries\n    for (i=0; i<(sizeof(usb_buffer)/sizeof(BDT_ENTRY)); i++) {\n       usb_buffer[i].Val = 0x00;\n    }\n\n    // Initialize EP0 as a Ctrl EP\n    U1EP(0) = EP_CTRL | USB_HANDSHAKE_ENABLED;\n\n    // Flush any pending transactions\n    while (U1IR & PIC32_U1I_TRN) {\n        U1IR = PIC32_U1I_TRN;\n    }\n\n    //clear all of the internal pipe information\n    usb_in_pipe[0].info.Val = 0;\n    usb_out_pipe[0].info.Val = 0;\n    usb_out_pipe[0].wCount = 0;\n\n    // Make sure packet processing is enabled\n    U1CON &= ~PIC32_U1CON_PKTDIS;\n\n    // Get ready for the first packet\n    pBDTEntryIn[0] = (volatile BDT_ENTRY*) &usb_buffer[EP0_IN_EVEN];\n\n    // Clear active configuration\n    usb_active_configuration = 0;\n\n    // Indicate that we are now in the detached state\n    usb_device_state = DETACHED_STATE;\n}\n\n/*\n * This function is the main state machine of the\n * USB device side stack.  This function should be\n * called periodically to receive and transmit\n * packets through the stack.  This function should\n * be called  preferably once every 100us\n * during the enumeration process.  After the\n * enumeration process this function still needs to\n * be called periodically to respond to various\n * situations on the bus but is more relaxed in its\n * time requirements.  This function should also\n * be called at least as fast as the OUT data\n * expected from the PC.\n */\nvoid usb_device_tasks(void)\n{\n    unsigned i;\n\n#ifdef USB_SUPPORT_OTG\n    // SRP Time Out Check\n    if (USBOTGSRPIsReady())\n    {\n        if (USBT1MSECIF && USBT1MSECIE)\n        {\n            if (USBOTGGetSRPTimeOutFlag())\n            {\n                if (USBOTGIsSRPTimeOutExpired())\n                {\n                    USB_OTGEventHandler(0,OTG_EVENT_SRP_FAILED,0,0);\n                }\n            }\n            // Clear Interrupt Flag\n            *USBT1MSECIFReg = 1 << USBT1MSECIFBitNum;\n        }\n    }\n    // If Session Is Started Then\n    else {\n        // If SRP Is Ready\n        if (USBOTGSRPIsReady())\n        {\n            // Clear SRPReady\n            USBOTGClearSRPReady();\n\n            // Clear SRP Timeout Flag\n            USBOTGClearSRPTimeOutFlag();\n\n            // Indicate Session Started\n            UART2PrintString( \"\\r\\n***** USB OTG B Event - Session Started  *****\\r\\n\" );\n        }\n    }\n#endif\n\n    // if we are in the detached state\n    if (usb_device_state == DETACHED_STATE)\n    {\n        // Disable module & detach from bus\n        U1CON = 0;\n\n        // Mask all USB interrupts\n        U1IE = 0;\n\n        // Enable module & attach to bus\n        while (! (U1CON & PIC32_U1CON_USBEN)) {\n            U1CON |= PIC32_U1CON_USBEN;\n        }\n\n        // moved to the attached state\n        usb_device_state = ATTACHED_STATE;\n\n        // Enable/set things like: pull ups, full/low-speed mode,\n        // set the ping pong mode, and set internal transceiver\n        SetConfigurationOptions();\n\n#ifdef USB_SUPPORT_OTG\n        U1OTGCON = USB_OTG_DPLUS_ENABLE | USB_OTG_ENABLE;\n#endif\n    }\n\n    if (usb_device_state == ATTACHED_STATE) {\n        /*\n         * After enabling the USB module, it takes some time for the\n         * voltage on the D+ or D- line to rise high enough to get out\n         * of the SE0 condition. The USB Reset interrupt should not be\n         * unmasked until the SE0 condition is cleared. This helps\n         * prevent the firmware from misinterpreting this unique event\n         * as a USB bus reset from the USB host.\n         */\n        U1IR = 0;                       // Clear all USB interrupts\n        U1IE = 0;                       // Mask all USB interrupts\n        U1IE = PIC32_U1I_URST |         // Unmask RESET interrupt\n               PIC32_U1I_IDLE;          // Unmask IDLE interrupt\n        usb_device_state = POWERED_STATE;\n    }\n\n#ifdef USB_SUPPORT_OTG\n    // If ID Pin Changed State\n    if (USBIDIF && USBIDIE)\n    {\n        // Re-detect & Initialize\n        USBOTGInitialize();\n\n        *USBIDIFReg = 1 << USBIDIFBitNum;\n    }\n#endif\n\n    /*\n     * Task A: Service USB Activity Interrupt\n     */\n    if ((U1OTGIR & PIC32_U1OTGI_ACTV) && (U1OTGIE & PIC32_U1OTGI_ACTV))\n    {\n#if defined(USB_SUPPORT_OTG)\n        U1OTGIR = PIC32_U1OTGI_ACTV;\n#else\n        usb_wake_from_suspend();\n#endif\n    }\n\n    /*\n     * Pointless to continue servicing if the device is in suspend mode.\n     */\n    if (U1PWRC & PIC32_U1PWRC_USUSPEND) {\n        return;\n    }\n\n    /*\n     * Task B: Service USB Bus Reset Interrupt.\n     * When bus reset is received during suspend, ACTVIF will be set first,\n     * once the UCON_SUSPND is clear, then the URSTIF bit will be asserted.\n     * This is why URSTIF is checked after ACTVIF.\n     *\n     * The USB reset flag is masked when the USB state is in\n     * DETACHED_STATE or ATTACHED_STATE, and therefore cannot\n     * cause a USB reset event during these two states.\n     */\n    if ((U1IR & PIC32_U1I_URST) && (U1IE & PIC32_U1I_URST))\n    {\n        usb_device_init();\n        usb_device_state = DEFAULT_STATE;\n\n        /*\n         * Bug Fix: Feb 26, 2007 v2.1 (#F1)\n         *********************************************************************\n         * In the original firmware, if an OUT token is sent by the host\n         * before a SETUP token is sent, the firmware would respond with an ACK.\n         * This is not a correct response, the firmware should have sent a STALL.\n         * This is a minor non-compliance since a compliant host should not\n         * send an OUT before sending a SETUP token. The fix allows a SETUP\n         * transaction to be accepted while stalling OUT transactions.\n         * */\n        usb_buffer[EP0_OUT_EVEN].ADR = ConvertToPhysicalAddress (&usb_setup_pkt);\n        usb_buffer[EP0_OUT_EVEN].CNT = USB_EP0_BUFF_SIZE;\n        usb_buffer[EP0_OUT_EVEN].STAT.Val &= ~_STAT_MASK;\n        usb_buffer[EP0_OUT_EVEN].STAT.Val |= _USIE|_DAT0|_DTSEN|_BSTALL;\n\n#ifdef USB_SUPPORT_OTG\n         // Disable HNP\n         USBOTGDisableHnp();\n\n         // Deactivate HNP\n         USBOTGDeactivateHnp();\n#endif\n    }\n\n    /*\n     * Task C: Service other USB interrupts\n     */\n    if ((U1IR & PIC32_U1I_IDLE) && (U1IE & PIC32_U1I_IDLE))\n    {\n#ifdef USB_SUPPORT_OTG\n        // If Suspended, Try to switch to Host\n        USBOTGSelectRole(ROLE_HOST);\n#else\n        usb_suspend();\n#endif\n        U1IR = PIC32_U1I_IDLE;\n    }\n\n    if (U1IR & PIC32_U1I_SOF)\n    {\n        if (U1IE & PIC32_U1I_SOF)\n            usbcb_sof_handler();    // Required callback, see usbcallbacks.c\n        U1IR = PIC32_U1I_SOF;\n    }\n\n    if ((U1IR & PIC32_U1I_STALL) && (U1IE & PIC32_U1I_STALL))\n    {\n        usb_stall_handler();\n    }\n\n    if ((U1IR & PIC32_U1I_UERR) && (U1IE & PIC32_U1I_UERR))\n    {\n        usbcb_error_handler();  // Required callback, see usbcallbacks.c\n        U1EIR = 0xFF;           // This clears UERRIF\n    }\n\n    /*\n     * Pointless to continue servicing if the host has not sent a bus reset.\n     * Once bus reset is received, the device transitions into the DEFAULT\n     * state and is ready for communication.\n     */\n    if (usb_device_state < DEFAULT_STATE)\n        return;\n\n    /*\n     * Task D: Servicing USB Transaction Complete Interrupt\n     */\n    if (U1IE & PIC32_U1I_TRN)\n    {\n        // Drain or deplete the USAT FIFO entries.\n        // If the USB FIFO ever gets full, USB bandwidth\n        // utilization can be compromised, and the device\n        // won't be able to receive SETUP packets.\n        for (i = 0; i < 4; i++) {\n            if (! (U1IR & PIC32_U1I_TRN))\n                break;                      // USTAT FIFO must be empty.\n\n            ustat_saved = U1STAT;\n            U1IR = PIC32_U1I_TRN;\n\n            /*\n             * usb_ctrl_ep_service only services transactions over EP0.\n             * It ignores all other EP transactions.\n             */\n            usb_ctrl_ep_service();\n        }\n    }\n}\n\n/*\n * This function handles the event of a STALL occuring on the bus\n */\nvoid usb_stall_handler(void)\n{\n    /*\n     * Does not really have to do anything here,\n     * even for the control endpoint.\n     * All BDs of Endpoint 0 are owned by SIE right now,\n     * but once a Setup Transaction is received, the ownership\n     * for EP0_OUT will be returned to CPU.\n     * When the Setup Transaction is serviced, the ownership\n     * for EP0_IN will then be forced back to CPU by firmware.\n     */\n\n    /* v2b fix */\n    if (U1EP(0) & PIC32_U1EP_EPSTALL)\n    {\n        // UOWN - if 0, owned by CPU, if 1, owned by SIE\n        if (pBDTEntryEP0OutCurrent->STAT.Val == _USIE &&\n            pBDTEntryIn[0]->STAT.Val == (_USIE | _BSTALL))\n        {\n            // Set ep0Bo to stall also\n            pBDTEntryEP0OutCurrent->STAT.Val = _USIE|_DAT0|_DTSEN|_BSTALL;\n        }\n        // Clear stall status\n        U1EP(0) &= ~PIC32_U1EP_EPSTALL;\n    }\n\n    U1IR = PIC32_U1I_STALL;\n}\n\n/*\n * This function handles if the host tries to suspend the device\n */\nvoid usb_suspend(void)\n{\n    /*\n     * NOTE: Do not clear UIR_ACTVIF here!\n     * Reason:\n     * ACTVIF is only generated once an IDLEIF has been generated.\n     * This is a 1:1 ratio interrupt generation.\n     * For every IDLEIF, there will be only one ACTVIF regardless of\n     * the number of subsequent bus transitions.\n     *\n     * If the ACTIF is cleared here, a problem could occur when:\n     * [       IDLE       ][bus activity ->\n     * <--- 3 ms ----->     ^\n     *                ^     ACTVIF=1\n     *                IDLEIF=1\n     *  #           #           #           #   (#=Program polling flags)\n     *                          ^\n     *                          This polling loop will see both\n     *                          IDLEIF=1 and ACTVIF=1.\n     *                          However, the program services IDLEIF first\n     *                          because ACTIVIE=0.\n     *                          If this routine clears the only ACTIVIF,\n     *                          then it can never get out of the suspend\n     *                          mode.\n     */\n\n    U1OTGIE |= PIC32_U1OTGI_ACTV;   // Enable bus activity interrupt\n    U1IR = PIC32_U1I_IDLE;\n\n    /*\n     * At this point the PIC can go into sleep,idle, or\n     * switch to a slower clock, etc.  This should be done in the\n     * usbcb_suspend() if necessary.\n     */\n    usbcb_suspend();             // Required callback, see usbcallbacks.c\n}\n\n/*\n * Wake up the USB module from suspend.\n */\nvoid usb_wake_from_suspend(void)\n{\n    /*\n     * If using clock switching, the place to restore the original\n     * microcontroller core clock frequency is in the usbcb_wake_from_suspend() callback\n     */\n    usbcb_wake_from_suspend(); // Required callback, see usbcallbacks.c\n\n    U1OTGIE &= ~PIC32_U1OTGI_ACTV;\n\n    /*\n    Bug Fix: Feb 26, 2007 v2.1\n    *********************************************************************\n    The ACTVIF bit cannot be cleared immediately after the USB module wakes\n    up from Suspend or while the USB module is suspended. A few clock cycles\n    are required to synchronize the internal hardware state machine before\n    the ACTIVIF bit can be cleared by firmware. Clearing the ACTVIF bit\n    before the internal hardware is synchronized may not have an effect on\n    the value of ACTVIF. Additonally, if the USB module uses the clock from\n    the 96 MHz PLL source, then after clearing the SUSPND bit, the USB\n    module may not be immediately operational while waiting for the 96 MHz\n    PLL to lock.\n    */\n    U1OTGIR = PIC32_U1OTGI_ACTV;\n}\n\n/*\n * usb_ctrl_ep_service checks for three transaction\n * types that it knows how to service and services them:\n * 1. EP0 SETUP\n * 2. EP0 OUT\n * 3. EP0 IN\n * It ignores all other types (i.e. EP1, EP2, etc.)\n *\n * PreCondition: USTAT is loaded with a valid endpoint address.\n */\nvoid usb_ctrl_ep_service(void)\n{\n    // If the last packet was a EP0 OUT packet\n    if ((ustat_saved & USTAT_EP0_PP_MASK) == USTAT_EP0_OUT_EVEN)\n    {\n        // Point to the EP0 OUT buffer of the buffer that arrived\n        pBDTEntryEP0OutCurrent = (volatile BDT_ENTRY*)\n            &usb_buffer [(ustat_saved & USTAT_EP_MASK) >> 2];\n\n        // Set the next out to the current out packet\n        pBDTEntryEP0OutNext = pBDTEntryEP0OutCurrent;\n\n        // Toggle it to the next ping pong buffer (if applicable)\n        *(unsigned char*)&pBDTEntryEP0OutNext ^= USB_NEXT_EP0_OUT_PING_PONG;\n\n        // If the current EP0 OUT buffer has a SETUP token\n        if (pBDTEntryEP0OutCurrent->STAT.PID == SETUP_TOKEN)\n        {\n            // Handle the control transfer\n            usb_ctrl_trf_setup_handler();\n        } else {\n            // Handle the DATA transfer\n            usb_ctrl_trf_out_handler();\n        }\n    } else if ((ustat_saved & USTAT_EP0_PP_MASK) == USTAT_EP0_IN)\n    {\n        // Otherwise the transmission was and EP0 IN\n        // so take care of the IN transfer\n        usb_ctrl_trf_in_handler();\n    }\n}\n\n/*\n * This routine is a task dispatcher and has 3 stages.\n * 1. It initializes the control transfer state machine.\n * 2. It calls on each of the module that may know how to\n *    service the Setup Request from the host.\n *    Module Example: USBD, HID, CDC, MSD, ...\n *    A callback function, usbcb_check_other_req(),\n *    is required to call other module handlers.\n * 3. Once each of the modules has had a chance to check if\n *    it is responsible for servicing the request, stage 3\n *    then checks direction of the transfer to determine how\n *    to prepare EP0 for the control transfer.\n *    Refer to usb_ctrl_ep_service_complete() for more details.\n *\n * PreCondition: usb_setup_pkt buffer is loaded with valid USB Setup Data\n *\n * Microchip USB Firmware has three different states for\n * the control transfer state machine:\n * 1. WAIT_SETUP\n * 2. CTRL_TRF_TX\n * 3. CTRL_TRF_RX\n * Refer to firmware manual to find out how one state\n * is transitioned to another.\n *\n * A Control Transfer is composed of many USB transactions.\n * When transferring data over multiple transactions,\n * it is important to keep track of data source, data\n * destination, and data count. These three parameters are\n * stored in pSrc, pDst, and wCount. A flag is used to\n * note if the data source is from ROM or RAM.\n */\nvoid usb_ctrl_trf_setup_handler(void)\n{\n    //if the SIE currently owns the buffer\n    if (pBDTEntryIn[0]->STAT.UOWN != 0)\n    {\n        // give control back to the CPU\n        // Compensate for after a STALL\n        pBDTEntryIn[0]->STAT.Val = _UCPU;\n    }\n\n    // Keep track of if a short packet has been sent yet or not\n    short_packet_status = SHORT_PKT_NOT_USED;\n\n    /* Stage 1 */\n    control_transfer_state = WAIT_SETUP;\n\n    usb_in_pipe[0].wCount = 0;\n    usb_in_pipe[0].info.Val = 0;\n\n    /* Stage 2 */\n    usb_check_std_request();\n    usbcb_check_other_req();   // Required callback, see usbcallbacks.c\n\n    /* Stage 3 */\n    usb_ctrl_ep_service_complete();\n}\n\n/*\n * This routine handles an OUT transaction according to\n * which control transfer state is currently active.\n *\n * Note that if the the control transfer was from\n * host to device, the session owner should be notified\n * at the end of each OUT transaction to service the\n * received data.\n */\nvoid usb_ctrl_trf_out_handler(void)\n{\n    if (control_transfer_state == CTRL_TRF_RX)\n    {\n        usb_ctrl_trf_rx_service();\n    }\n    else    // CTRL_TRF_TX\n    {\n        usb_prepare_for_next_setup_trf();\n    }\n}\n\n/*\n * This routine handles an IN transaction according to\n * which control transfer state is currently active.\n *\n * A Set Address Request must not change the acutal address\n * of the device until the completion of the control\n * transfer. The end of the control transfer for Set Address\n * Request is an IN transaction. Therefore it is necessary\n * to service this unique situation when the condition is\n * right. Macro mUSBCheckAdrPendingState is defined in\n * usb9.h and its function is to specifically service this event.\n */\nvoid usb_ctrl_trf_in_handler(void)\n{\n    unsigned lastDTS;\n\n    lastDTS = pBDTEntryIn[0]->STAT.DTS;\n\n    //switch to the next ping pong buffer\n    *(unsigned char*)&pBDTEntryIn[0] ^= USB_NEXT_EP0_IN_PING_PONG;\n\n    //mUSBCheckAdrPendingState();       // Must check if in ADR_PENDING_STATE\n    if (usb_device_state == ADR_PENDING_STATE)\n    {\n        U1ADDR = usb_setup_pkt.bDevADR;\n        if (U1ADDR > 0)\n        {\n            usb_device_state = ADDRESS_STATE;\n        }\n        else\n        {\n            usb_device_state = DEFAULT_STATE;\n        }\n    }//end if\n\n\n    if (control_transfer_state == CTRL_TRF_TX)\n    {\n        pBDTEntryIn[0]->ADR = ConvertToPhysicalAddress (ctrl_trf_data);\n        usb_ctrl_trf_tx_service();\n\n        /* v2b fix */\n        if (short_packet_status == SHORT_PKT_SENT)\n        {\n            // If a short packet has been sent, don't want to send any more,\n            // stall next time if host is still trying to read.\n            pBDTEntryIn[0]->STAT.Val = _USIE|_BSTALL;\n        } else {\n            if (lastDTS == 0) {\n                pBDTEntryIn[0]->STAT.Val = _USIE|_DAT1|_DTSEN;\n            } else {\n                pBDTEntryIn[0]->STAT.Val = _USIE|_DAT0|_DTSEN;\n            }\n        }\n    } else {\n        // CTRL_TRF_RX\n        usb_prepare_for_next_setup_trf();\n    }\n}\n\n/*\n * The routine forces EP0 OUT to be ready for a new\n * Setup transaction, and forces EP0 IN to be owned by CPU.\n */\nvoid usb_prepare_for_next_setup_trf(void)\n{\n    /*\n    Bug Fix: Feb 26, 2007 v2.1\n    *********************************************************************\n    Facts:\n    A Setup Packet should never be stalled. (USB 2.0 Section 8.5.3)\n    If a Setup PID is detected by the SIE, the DTSEN setting is ignored.\n    This causes a problem at the end of a control write transaction.\n    In usb_ctrl_ep_service_complete(), during a control write (Host to Device),\n    the EP0_OUT is setup to write any data to the ctrl_trf_data buffer.\n    If <SETUP[0]><IN[1]> is completed and usb_ctrl_trf_in_handler() is not\n    called before the next <SETUP[0]> is received, then the latest Setup\n    data will be written to the ctrl_trf_data buffer instead of the usb_setup_pkt\n    buffer.\n\n    If usb_ctrl_trf_in_handler() was called before the latest <SETUP[0]> is\n    received, then there would be no problem,\n    because usb_prepare_for_next_setup_trf() would have been called and updated\n    ep0Bo.ADR to point to the usb_setup_pkt buffer.\n\n    Work around:\n    Check for the problem as described above and copy the Setup data from\n    ctrl_trf_data to usb_setup_pkt.\n    */\n    if ((control_transfer_state == CTRL_TRF_RX) &&\n       (U1CON & PIC32_U1CON_PKTDIS) &&\n       (pBDTEntryEP0OutCurrent->CNT == sizeof(CTRL_TRF_SETUP)) &&\n       (pBDTEntryEP0OutCurrent->STAT.PID == SETUP_TOKEN) &&\n       (pBDTEntryEP0OutNext->STAT.UOWN == 0))\n    {\n        unsigned setup_cnt;\n\n        pBDTEntryEP0OutNext->ADR = ConvertToPhysicalAddress(&usb_setup_pkt);\n\n        // The Setup data was written to the ctrl_trf_data buffer, must copy\n        // it back to the usb_setup_pkt buffer so that it can be processed correctly\n        // by usb_ctrl_trf_setup_handler().\n        for(setup_cnt = 0; setup_cnt < sizeof(CTRL_TRF_SETUP); setup_cnt++)\n        {\n            *(((unsigned char*) &usb_setup_pkt) + setup_cnt) =\n                *(((unsigned char*) &ctrl_trf_data) + setup_cnt);\n        }\n    /* End v3b fix */\n    } else {\n        control_transfer_state = WAIT_SETUP;\n        pBDTEntryEP0OutNext->CNT = USB_EP0_BUFF_SIZE;      // Defined in target.cfg\n        pBDTEntryEP0OutNext->ADR = ConvertToPhysicalAddress(&usb_setup_pkt);\n\n        /*\n        Bug Fix: Feb 26, 2007 v2.1 (#F1)\n        *********************************************************************\n        In the original firmware, if an OUT token is sent by the host\n        before a SETUP token is sent, the firmware would respond with an ACK.\n        This is not a correct response, the firmware should have sent a STALL.\n        This is a minor non-compliance since a compliant host should not\n        send an OUT before sending a SETUP token. The fix allows a SETUP\n        transaction to be accepted while stalling OUT transactions.\n        */\n        //ep0Bo.Stat.Val = _USIE|_DAT0|_DTSEN;        // Removed\n        pBDTEntryEP0OutNext->STAT.Val = _USIE|_DAT0|_DTSEN|_BSTALL;  //Added #F1\n\n        /*\n        Bug Fix: Feb 26, 2007 v2.1 (#F3)\n        *********************************************************************\n        In the original firmware, if an IN token is sent by the host\n        before a SETUP token is sent, the firmware would respond with an ACK.\n        This is not a correct response, the firmware should have sent a STALL.\n        This is a minor non-compliance since a compliant host should not\n        send an IN before sending a SETUP token.\n\n        Comment why this fix (#F3) is interfering with fix (#AF1).\n        */\n        pBDTEntryIn[0]->STAT.Val = _UCPU;             // Should be removed\n\n        {\n            BDT_ENTRY* p;\n\n            p = (BDT_ENTRY*)(((unsigned int)pBDTEntryIn[0])^USB_NEXT_EP0_IN_PING_PONG);\n            p->STAT.Val = _UCPU;\n        }\n\n        //ep0Bi.Stat.Val = _USIE|_BSTALL;   // Should be added #F3\n    }\n\n    //if someone is still expecting data from the control transfer\n    //  then make sure to terminate that request and let them know that\n    //  they are done\n    if (usb_out_pipe[0].info.bits.busy == 1) {\n        if (usb_out_pipe[0].pFunc != 0) {\n            usb_out_pipe[0].pFunc();\n        }\n        usb_out_pipe[0].info.bits.busy = 0;\n    }\n\n}//end usb_prepare_for_next_setup_trf\n\n/*\n * This routine checks the setup data packet to see\n * if it knows how to handle it\n */\nvoid usb_check_std_request(void)\n{\n    if (usb_setup_pkt.RequestType != STANDARD) return;\n\n    switch (usb_setup_pkt.bRequest) {\n    case SET_ADR:\n        usb_in_pipe[0].info.bits.busy = 1;            // This will generate a zero length packet\n        usb_device_state = ADR_PENDING_STATE;     // Update state only\n        /* See usb_ctrl_trf_in_handler() for the next step */\n        break;\n    case GET_DSC:\n        usb_std_get_dsc_handler();\n        break;\n    case SET_CFG:\n        usb_std_set_cfg_handler();\n        break;\n    case GET_CFG:\n        usb_in_pipe[0].pSrc.bRam = (unsigned char*)&usb_active_configuration; // Set Source\n        usb_in_pipe[0].info.bits.ctrl_trf_mem = _RAM;   // Set memory type\n        usb_in_pipe[0].wCount |= 0xff;                  // Set data count\n        usb_in_pipe[0].info.bits.busy = 1;\n        break;\n    case GET_STATUS:\n        usb_std_get_status_handler();\n        break;\n    case CLR_FEATURE:\n    case SET_FEATURE:\n        usb_std_feature_req_handler();\n        break;\n    case GET_INTF:\n        usb_in_pipe[0].pSrc.bRam = (unsigned char*)&usb_alternate_interface +\n            usb_setup_pkt.bIntfID;                      // Set source\n        usb_in_pipe[0].info.bits.ctrl_trf_mem = _RAM;   // Set memory type\n        usb_in_pipe[0].wCount |= 0xff;                  // Set data count\n        usb_in_pipe[0].info.bits.busy = 1;\n        break;\n    case SET_INTF:\n        usb_in_pipe[0].info.bits.busy = 1;\n        usb_alternate_interface[usb_setup_pkt.bIntfID] = usb_setup_pkt.bAltID;\n        break;\n    case SET_DSC:\n        usbcb_std_set_dsc_handler();\n        break;\n    case SYNCH_FRAME:\n    default:\n        break;\n    }\n}\n\n/*\n * This routine handles the standard SET & CLEAR\n * FEATURES requests\n */\nvoid usb_std_feature_req_handler(void)\n{\n    BDT_ENTRY *p;\n    unsigned int *pUEP;\n\n#ifdef USB_SUPPORT_OTG\n    if ((usb_setup_pkt.bFeature == OTG_FEATURE_B_HNP_ENABLE)&&\n        (usb_setup_pkt.Recipient == RCPT_DEV))\n    {\n        usb_in_pipe[0].info.bits.busy = 1;\n        if (usb_setup_pkt.bRequest == SET_FEATURE)\n            USBOTGEnableHnp();\n        else\n            USBOTGDisableHnp();\n    }\n\n    if ((usb_setup_pkt.bFeature == OTG_FEATURE_A_HNP_SUPPORT)&&\n        (usb_setup_pkt.Recipient == RCPT_DEV))\n    {\n        usb_in_pipe[0].info.bits.busy = 1;\n        if (usb_setup_pkt.bRequest == SET_FEATURE)\n            USBOTGEnableSupportHnp();\n        else\n            USBOTGDisableSupportHnp();\n    }\n\n\n    if ((usb_setup_pkt.bFeature == OTG_FEATURE_A_ALT_HNP_SUPPORT)&&\n        (usb_setup_pkt.Recipient == RCPT_DEV))\n    {\n        usb_in_pipe[0].info.bits.busy = 1;\n        if (usb_setup_pkt.bRequest == SET_FEATURE)\n            USBOTGEnableAltHnp();\n        else\n            USBOTGDisableAltHnp();\n    }\n#endif\n    if ((usb_setup_pkt.bFeature == DEVICE_REMOTE_WAKEUP)&&\n       (usb_setup_pkt.Recipient == RCPT_DEV))\n    {\n        usb_in_pipe[0].info.bits.busy = 1;\n        if (usb_setup_pkt.bRequest == SET_FEATURE)\n            usb_remote_wakeup = 1;\n        else\n            usb_remote_wakeup = 0;\n    }\n\n    if ((usb_setup_pkt.bFeature == ENDPOINT_HALT)&&\n       (usb_setup_pkt.Recipient == RCPT_EP)&&\n       (usb_setup_pkt.EPNum != 0))\n    {\n        usb_in_pipe[0].info.bits.busy = 1;\n        /* Must do address calculation here */\n\n        if (usb_setup_pkt.EPDir == 0)\n        {\n            p = (BDT_ENTRY*)pBDTEntryOut[usb_setup_pkt.EPNum];\n        } else {\n            p = (BDT_ENTRY*)pBDTEntryIn[usb_setup_pkt.EPNum];\n        }\n\n        //if it was a SET_FEATURE request\n        if (usb_setup_pkt.bRequest == SET_FEATURE)\n        {\n            // Then STALL the endpoint\n            p->STAT.Val = _USIE|_BSTALL;\n        } else {\n            // If it was not a SET_FEATURE\n            // point to the appropriate UEP register\n            pUEP = (unsigned int*) &U1EP(0);\n            pUEP += usb_setup_pkt.EPNum * 4;\n\n            //Clear the STALL bit in the UEP register\n            *pUEP &= ~UEP_STALL;\n\n            if (usb_setup_pkt.EPDir == 1) // IN\n            {\n                // If the endpoint is an IN endpoint then we\n                // need to return it to the CPU and reset the\n                // DTS bit so that the next transfer is correct\n#if (USB_PING_PONG_MODE == USB_PING_PONG__ALL_BUT_EP0) || \\\n    (USB_PING_PONG_MODE == USB_PING_PONG__FULL_PING_PONG)\n                p->STAT.Val = _UCPU | _DAT0;\n                // toggle over the to the next buffer\n                *(unsigned char*)&p ^= USB_NEXT_PING_PONG;\n                p->STAT.Val = _UCPU | _DAT1;\n#else\n                p->STAT.Val = _UCPU | _DAT1;\n#endif\n            } else {\n                // If the endpoint was an OUT endpoint then we\n                // need to give control of the endpoint back to\n                // the SIE so that the function driver can\n                // receive the data as they expected.  Also need\n                // to set the DTS bit so the next packet will be\n                // correct\n#if (USB_PING_PONG_MODE == USB_PING_PONG__ALL_BUT_EP0) || \\\n    (USB_PING_PONG_MODE == USB_PING_PONG__FULL_PING_PONG)\n                p->STAT.Val = _USIE|_DAT0|_DTSEN;\n                //toggle over the to the next buffer\n                *(unsigned char*)&p ^= USB_NEXT_PING_PONG;\n                p->STAT.Val = _USIE|_DAT1|_DTSEN;\n#else\n                p->STAT.Val = _USIE|_DAT1|_DTSEN;\n#endif\n            }\n        }\n    }\n}\n\n/*\n * This routine handles the standard GET_DESCRIPTOR request.\n */\nvoid usb_std_get_dsc_handler(void)\n{\n    if (usb_setup_pkt.bmRequestType == 0x80)\n    {\n        usb_in_pipe[0].info.Val = USB_INPIPES_ROM | USB_INPIPES_BUSY | USB_INPIPES_INCLUDE_ZERO;\n\n        switch(usb_setup_pkt.bDescriptorType)\n        {\n            case USB_DESCRIPTOR_DEVICE:\n                usb_in_pipe[0].pSrc.bRom = (const unsigned char*) &usb_device;\n                usb_in_pipe[0].wCount = sizeof(usb_device);\n                break;\n            case USB_DESCRIPTOR_CONFIGURATION:\n                usb_in_pipe[0].pSrc.bRom = usb_config [usb_setup_pkt.bDscIndex];\n                usb_in_pipe[0].wCount = *(usb_in_pipe[0].pSrc.wRom+1);                // Set data count\n                break;\n            case USB_DESCRIPTOR_STRING:\n#if defined(USB_NUM_STRING_DESCRIPTORS)\n                if (usb_setup_pkt.bDscIndex < USB_NUM_STRING_DESCRIPTORS)\n#else\n                if (1)\n#endif\n                {\n                    //Get a pointer to the String descriptor requested\n                    usb_in_pipe[0].pSrc.bRom = usb_string [usb_setup_pkt.bDscIndex];\n                    // Set data count\n                    usb_in_pipe[0].wCount = *usb_in_pipe[0].pSrc.bRom;\n                }\n                else\n                {\n                    usb_in_pipe[0].info.Val = 0;\n                }\n                break;\n            default:\n                usb_in_pipe[0].info.Val = 0;\n                break;\n        }//end switch\n    }//end if\n}//end usb_std_get_dsc_handler\n\n/*\n * This routine handles the standard GET_STATUS request\n */\nvoid usb_std_get_status_handler(void)\n{\n    ctrl_trf_data[0] = 0;                 // Initialize content\n    ctrl_trf_data[1] = 0;\n\n    switch(usb_setup_pkt.Recipient)\n    {\n        case RCPT_DEV:\n            usb_in_pipe[0].info.bits.busy = 1;\n            /*\n             * [0]: bit0: Self-Powered Status [0] Bus-Powered [1] Self-Powered\n             *      bit1: RemoteWakeup        [0] Disabled    [1] Enabled\n             */\n            ctrl_trf_data[0] |= 1;          // self powered\n\n            if (usb_remote_wakeup == 1) {\n                ctrl_trf_data[0] |= 2;\n            }\n            break;\n        case RCPT_INTF:\n            usb_in_pipe[0].info.bits.busy = 1;  // No data to update\n            break;\n        case RCPT_EP:\n            usb_in_pipe[0].info.bits.busy = 1;\n            /*\n             * [0]: bit0: Halt Status [0] Not Halted [1] Halted\n             */\n            {\n                BDT_ENTRY *p;\n\n                if (usb_setup_pkt.EPDir == 0)\n                {\n                    p = (BDT_ENTRY*)pBDTEntryOut[usb_setup_pkt.EPNum];\n                } else {\n                    p = (BDT_ENTRY*)pBDTEntryIn[usb_setup_pkt.EPNum];\n                }\n\n                if (p->STAT.Val & _BSTALL)      // Use _BSTALL as a bit mask\n                    ctrl_trf_data[0] = 1;       // Set bit0\n                break;\n            }\n    }//end switch\n\n    if (usb_in_pipe[0].info.bits.busy == 1)\n    {\n        usb_in_pipe[0].pSrc.bRam = (unsigned char*) &ctrl_trf_data; // Set Source\n        usb_in_pipe[0].info.bits.ctrl_trf_mem = _RAM;               // Set memory type\n        usb_in_pipe[0].wCount &= ~0xff;\n        usb_in_pipe[0].wCount |= 2;                                 // Set data count\n    }\n}\n\n/*\n * This routine wrap up the ramaining tasks in servicing\n * a Setup Request. Its main task is to set the endpoint\n * controls appropriately for a given situation. See code\n * below.\n * There are three main scenarios:\n * a) There was no handler for the Request, in this case\n *    a STALL should be sent out.\n * b) The host has requested a read control transfer,\n *    endpoints are required to be setup in a specific way.\n * c) The host has requested a write control transfer, or\n *    a control data stage is not required, endpoints are\n *    required to be setup in a specific way.\n *\n * Packet processing is resumed by clearing PKTDIS bit.\n */\nvoid usb_ctrl_ep_service_complete(void)\n{\n    /*\n     * PKTDIS bit is set when a Setup Transaction is received.\n     * Clear to resume packet processing.\n     */\n    U1CON &= ~PIC32_U1CON_PKTDIS;\n\n    if (usb_in_pipe[0].info.bits.busy == 0)\n    {\n        if (usb_out_pipe[0].info.bits.busy == 1)\n        {\n            control_transfer_state = CTRL_TRF_RX;\n            /*\n             * Control Write:\n             * <SETUP[0]><OUT[1]><OUT[0]>...<IN[1]> | <SETUP[0]>\n             *\n             * 1. Prepare IN EP to respond to early termination\n             *\n             *    This is the same as a Zero Length Packet Response\n             *    for control transfer without a data stage\n             */\n            pBDTEntryIn[0]->CNT = 0;\n            pBDTEntryIn[0]->STAT.Val = _USIE|_DAT1|_DTSEN;\n\n            /*\n             * 2. Prepare OUT EP to receive data.\n             */\n            pBDTEntryEP0OutNext->CNT = USB_EP0_BUFF_SIZE;\n            pBDTEntryEP0OutNext->ADR = ConvertToPhysicalAddress (&ctrl_trf_data);\n            pBDTEntryEP0OutNext->STAT.Val = _USIE|_DAT1|_DTSEN;\n        } else {\n            /*\n             * If no one knows how to service this request then stall.\n             * Must also prepare EP0 to receive the next SETUP transaction.\n             */\n            pBDTEntryEP0OutNext->CNT = USB_EP0_BUFF_SIZE;\n            pBDTEntryEP0OutNext->ADR = ConvertToPhysicalAddress(&usb_setup_pkt);\n\n            /* v2b fix */\n            pBDTEntryEP0OutNext->STAT.Val = _USIE|_DAT0|_DTSEN|_BSTALL;\n            pBDTEntryIn[0]->STAT.Val = _USIE|_BSTALL;\n        }\n    } else {\n        // A module has claimed ownership of the control transfer session.\n        if (usb_out_pipe[0].info.bits.busy == 0)\n        {\n            if (usb_setup_pkt.DataDir == DEV_TO_HOST)\n            {\n                if (usb_setup_pkt.wLength < usb_in_pipe[0].wCount)\n                {\n                        usb_in_pipe[0].wCount = usb_setup_pkt.wLength;\n                }\n                usb_ctrl_trf_tx_service();\n                control_transfer_state = CTRL_TRF_TX;\n                /*\n                 * Control Read:\n                 * <SETUP[0]><IN[1]><IN[0]>...<OUT[1]> | <SETUP[0]>\n                 * 1. Prepare OUT EP to respond to early termination\n                 *\n                 * NOTE:\n                 * If something went wrong during the control transfer,\n                 * the last status stage may not be sent by the host.\n                 * When this happens, two different things could happen\n                 * depending on the host.\n                 * a) The host could send out a RESET.\n                 * b) The host could send out a new SETUP transaction\n                 *    without sending a RESET first.\n                 * To properly handle case (b), the OUT EP must be setup\n                 * to receive either a zero length OUT transaction, or a\n                 * new SETUP transaction.\n                 *\n                 * Furthermore, the Cnt byte should be set to prepare for\n                 * the SETUP data (8-byte or more), and the buffer address\n                 * should be pointed to usb_setup_pkt.\n                 */\n                pBDTEntryEP0OutNext->CNT = USB_EP0_BUFF_SIZE;\n                pBDTEntryEP0OutNext->ADR = ConvertToPhysicalAddress(&usb_setup_pkt);\n                pBDTEntryEP0OutNext->STAT.Val = _USIE;           // Note: DTSEN is 0!\n\n                pBDTEntryEP0OutCurrent->CNT = USB_EP0_BUFF_SIZE;\n                pBDTEntryEP0OutCurrent->ADR = (unsigned char*)&usb_setup_pkt;\n                pBDTEntryEP0OutCurrent->STAT.Val = _USIE;           // Note: DTSEN is 0!\n\n                /*\n                 * 2. Prepare IN EP to transfer data, Cnt should have\n                 *    been initialized by responsible request owner.\n                 */\n                pBDTEntryIn[0]->ADR = ConvertToPhysicalAddress (&ctrl_trf_data);\n                pBDTEntryIn[0]->STAT.Val = _USIE|_DAT1|_DTSEN;\n\n            } else {  // (usb_setup_pkt.DataDir == HOST_TO_DEVICE)\n\n                control_transfer_state = CTRL_TRF_RX;\n                /*\n                 * Control Write:\n                 * <SETUP[0]><OUT[1]><OUT[0]>...<IN[1]> | <SETUP[0]>\n                 *\n                 * 1. Prepare IN EP to respond to early termination\n                 *\n                 *    This is the same as a Zero Length Packet Response\n                 *    for control transfer without a data stage\n                 */\n                pBDTEntryIn[0]->CNT = 0;\n                pBDTEntryIn[0]->STAT.Val = _USIE|_DAT1|_DTSEN;\n\n                /*\n                 * 2. Prepare OUT EP to receive data.\n                 */\n                pBDTEntryEP0OutNext->CNT = USB_EP0_BUFF_SIZE;\n                pBDTEntryEP0OutNext->ADR = ConvertToPhysicalAddress (&ctrl_trf_data);\n                pBDTEntryEP0OutNext->STAT.Val = _USIE|_DAT1|_DTSEN;\n            }\n        }\n    }\n}\n\n\n/*\n * This routine should be called from only two places.\n * One from usb_ctrl_ep_service_complete() and one from\n * usb_ctrl_trf_in_handler(). It takes care of managing a\n * transfer over multiple USB transactions.\n *\n * This routine works with isochronous endpoint larger than\n * 256 bytes and is shown here as an example of how to deal\n * with BC9 and BC8. In reality, a control endpoint can never\n * be larger than 64 bytes.\n *\n * PreCondition: pSrc, wCount, and usb_stat.ctrl_trf_mem are setup properly.\n */\nvoid usb_ctrl_trf_tx_service(void)\n{\n    unsigned byteToSend;\n    unsigned char *dst;\n\n    /*\n     * First, have to figure out how many byte of data to send.\n     */\n    if (usb_in_pipe[0].wCount < USB_EP0_BUFF_SIZE)\n    {\n        byteToSend = usb_in_pipe[0].wCount;\n\n        /* v2b fix */\n        if (short_packet_status == SHORT_PKT_NOT_USED) {\n            short_packet_status = SHORT_PKT_PENDING;\n\n        } else if (short_packet_status == SHORT_PKT_PENDING) {\n            short_packet_status = SHORT_PKT_SENT;\n        }\n        /* end v2b fix for this section */\n    }\n    else\n    {\n        byteToSend = USB_EP0_BUFF_SIZE;\n    }\n\n    /*\n     * Next, load the number of bytes to send to BC9..0 in buffer descriptor\n     */\n    pBDTEntryIn[0]->CNT = byteToSend;\n\n    /*\n     * Subtract the number of bytes just about to be sent from the total.\n     */\n    usb_in_pipe[0].wCount = usb_in_pipe[0].wCount - byteToSend;\n\n    // Set destination pointer\n    dst = (unsigned char*) ctrl_trf_data;\n\n    // Determine type of memory source\n    if (usb_in_pipe[0].info.bits.ctrl_trf_mem == USB_INPIPES_ROM)\n    {\n        while (byteToSend)\n        {\n            *dst++ = *usb_in_pipe[0].pSrc.bRom++;\n            byteToSend--;\n        }\n    } else { // RAM\n        while (byteToSend)\n        {\n            *dst++ = *usb_in_pipe[0].pSrc.bRam++;\n            byteToSend--;\n        }\n    }\n}\n\n/*\n * *** This routine is only partially complete. Check for\n * new version of the firmware.\n *\n * PreCondition: pDst and wCount are setup properly.\n *               pSrc is always &ctrl_trf_data\n *               usb_stat.ctrl_trf_mem is always _RAM.\n *               wCount should be set to 0 at the start of each control transfer.\n */\nvoid usb_ctrl_trf_rx_service(void)\n{\n    unsigned byteToRead, i;\n\n    byteToRead = pBDTEntryEP0OutCurrent->CNT;\n\n    /*\n     * Accumulate total number of bytes read\n     */\n    if (byteToRead > usb_out_pipe[0].wCount)\n    {\n        byteToRead = usb_out_pipe[0].wCount;\n    } else {\n        usb_out_pipe[0].wCount = usb_out_pipe[0].wCount - byteToRead;\n    }\n\n    for(i=0;i<byteToRead;i++)\n    {\n        *usb_out_pipe[0].pDst.bRam++ = ctrl_trf_data[i];\n    }//end while(byteToRead)\n\n    //If there is more data to read\n    if (usb_out_pipe[0].wCount > 0)\n    {\n        /*\n         * Don't have to worry about overwriting _KEEP bit\n         * because if _KEEP was set, TRNIF would not have been\n         * generated in the first place.\n         */\n        pBDTEntryEP0OutNext->CNT = USB_EP0_BUFF_SIZE;\n        pBDTEntryEP0OutNext->ADR = ConvertToPhysicalAddress (&ctrl_trf_data);\n        if (pBDTEntryEP0OutCurrent->STAT.DTS == 0)\n        {\n            pBDTEntryEP0OutNext->STAT.Val = _USIE|_DAT1|_DTSEN;\n        } else {\n            pBDTEntryEP0OutNext->STAT.Val = _USIE|_DAT0|_DTSEN;\n        }\n    } else {\n        pBDTEntryEP0OutNext->ADR = ConvertToPhysicalAddress(&usb_setup_pkt);\n        if (usb_out_pipe[0].pFunc != 0) {\n            usb_out_pipe[0].pFunc();\n        }\n        usb_out_pipe[0].info.bits.busy = 0;\n    }\n\n    // reset ep0Bo.Cnt to USB_EP0_BUFF_SIZE\n\n}//end usb_ctrl_trf_rx_service\n\n/*\n * This routine first disables all endpoints by\n * clearing UEP registers. It then configures\n * (initializes) endpoints by calling the callback\n * function usbcb_init_ep().\n */\nvoid usb_std_set_cfg_handler(void)\n{\n    unsigned i;\n\n    // This will generate a zero length packet\n    usb_in_pipe[0].info.bits.busy = 1;\n\n    // disable all endpoints except endpoint 0\n    for (i=1; i<USB_MAX_EP_NUMBER; i++)\n        U1EP(i) = 0;\n\n    // clear the alternate interface settings\n    for (i=0; i<USB_MAX_NUM_INT; i++)\n        usb_alternate_interface[i] = 0;\n\n    // set the current configuration\n    usb_active_configuration = usb_setup_pkt.bConfigurationValue;\n\n    // if the configuration value == 0\n    if (usb_setup_pkt.bConfigurationValue == 0)\n    {\n        // Go back to the addressed state\n        usb_device_state = ADDRESS_STATE;\n    } else {\n        // Otherwise go to the configured state\n        usb_device_state = CONFIGURED_STATE;\n\n        // initialize the required endpoints\n        usb_init_ep ((const unsigned char*) usb_config [usb_active_configuration - 1]);\n        usbcb_init_ep();\n    }\n}\n\n/*\n * This function will configure the specified endpoint.\n *\n * Input: unsigned EPNum - the endpoint to be configured\n *        unsigned direction - the direction to be configured\n */\nvoid usb_configure_endpoint (unsigned epnum, unsigned direction)\n{\n    volatile BDT_ENTRY* handle;\n\n    handle = (volatile BDT_ENTRY*) &usb_buffer[EP0_OUT_EVEN];\n    handle += BD(epnum, direction, 0) / sizeof(BDT_ENTRY);\n\n    handle->STAT.UOWN = 0;\n\n    if (direction == 0) {\n        pBDTEntryOut[epnum] = handle;\n    } else {\n        pBDTEntryIn[epnum] = handle;\n    }\n\n#if (USB_PING_PONG_MODE == USB_PING_PONG__FULL_PING_PONG)\n    handle->STAT.DTS = 0;\n    (handle+1)->STAT.DTS = 1;\n#elif (USB_PING_PONG_MODE == USB_PING_PONG__NO_PING_PONG)\n    //Set DTS to one because the first thing we will do\n    //when transmitting is toggle the bit\n    handle->STAT.DTS = 1;\n#elif (USB_PING_PONG_MODE == USB_PING_PONG__EP0_OUT_ONLY)\n    if (epnum != 0)\n    {\n        handle->STAT.DTS = 1;\n    }\n#elif (USB_PING_PONG_MODE == USB_PING_PONG__ALL_BUT_EP0)\n    if (epnum != 0)\n    {\n        handle->STAT.DTS = 0;\n        (handle+1)->STAT.DTS = 1;\n    }\n#endif\n}\n\n/*\n * This function will enable the specified endpoint with the specified\n * options.\n *\n * Typical Usage:\n * <code>\n * void usbcb_init_ep(void)\n * {\n *     usb_enable_endpoint(MSD_DATA_IN_EP,USB_IN_ENABLED|USB_OUT_ENABLED|USB_HANDSHAKE_ENABLED|USB_DISALLOW_SETUP);\n *     USBMSDInit();\n * }\n * </code>\n *\n * In the above example endpoint number MSD_DATA_IN_EP is being configured\n * for both IN and OUT traffic with handshaking enabled. Also since\n * MSD_DATA_IN_EP is not endpoint 0 (MSD does not allow this), then we can\n * explicitly disable SETUP packets on this endpoint.\n *\n * Input:\n *   unsigned ep -       the endpoint to be configured\n *   unsigned options -  optional settings for the endpoint. The options should\n *                   be ORed together to form a single options string. The\n *                   available optional settings for the endpoint. The\n *                   options should be ORed together to form a single options\n *                   string. The available options are the following\\:\n *                   * USB_HANDSHAKE_ENABLED enables USB handshaking (ACK,\n *                     NAK)\n *                   * USB_HANDSHAKE_DISABLED disables USB handshaking (ACK,\n *                     NAK)\n *                   * USB_OUT_ENABLED enables the out direction\n *                   * USB_OUT_DISABLED disables the out direction\n *                   * USB_IN_ENABLED enables the in direction\n *                   * USB_IN_DISABLED disables the in direction\n *                   * USB_ALLOW_SETUP enables control transfers\n *                   * USB_DISALLOW_SETUP disables control transfers\n *                   * USB_STALL_ENDPOINT STALLs this endpoint\n */\nvoid usb_enable_endpoint (unsigned ep, unsigned options)\n{\n    // Set the options to the appropriate endpoint control register\n    unsigned int *p = (unsigned int*) (&U1EP(0) + (4 * ep));\n\n    *p = options;\n\n    if (options & USB_OUT_ENABLED) {\n        usb_configure_endpoint(ep, 0);\n    }\n    if (options & USB_IN_ENABLED) {\n        usb_configure_endpoint(ep, 1);\n    }\n}\n\n/*\n * STALLs the specified endpoint\n *\n * Input:\n *   unsigned ep - the endpoint the data will be transmitted on\n *   unsigned dir - the direction of the transfer\n */\nvoid usb_stall_endpoint (unsigned ep, unsigned dir)\n{\n    BDT_ENTRY *p;\n\n    if (ep == 0) {\n        /*\n         * If no one knows how to service this request then stall.\n         * Must also prepare EP0 to receive the next SETUP transaction.\n         */\n        pBDTEntryEP0OutNext->CNT = USB_EP0_BUFF_SIZE;\n        pBDTEntryEP0OutNext->ADR = ConvertToPhysicalAddress(&usb_setup_pkt);\n\n        /* v2b fix */\n        pBDTEntryEP0OutNext->STAT.Val = _USIE|_DAT0|_DTSEN|_BSTALL;\n        pBDTEntryIn[0]->STAT.Val = _USIE|_BSTALL;\n    } else {\n        p = (BDT_ENTRY*) &usb_buffer[EP(ep, dir, 0)];\n        p->STAT.Val |= _BSTALL | _USIE;\n\n        //If the device is in FULL or ALL_BUT_EP0 ping pong modes\n        //then stall that entry as well\n#if (USB_PING_PONG_MODE == USB_PING_PONG__FULL_PING_PONG) || \\\n    (USB_PING_PONG_MODE == USB_PING_PONG__ALL_BUT_EP0)\n\n        p = (BDT_ENTRY*) &usb_buffer[EP(ep, dir, 1)];\n        p->STAT.Val |= _BSTALL | _USIE;\n#endif\n    }\n}\n\n/*\n * Transfers one packet over the USB.\n *\n * Input:\n *   unsigned ep - the endpoint the data will be transmitted on\n *   unsigned dir - the direction of the transfer\n *                  This value is either OUT_FROM_HOST or IN_TO_HOST\n *   unsigned char* data - pointer to the data to be sent\n *   unsigned len - length of the data needing to be sent\n */\nUSB_HANDLE usb_transfer_one_packet (unsigned ep, unsigned dir,\n    unsigned char* data, unsigned len)\n{\n    USB_HANDLE handle;\n\n    // If the direction is IN\n    if (dir != 0) {\n        // point to the IN BDT of the specified endpoint\n        handle = pBDTEntryIn[ep];\n    } else {\n        // else point to the OUT BDT of the specified endpoint\n        handle = pBDTEntryOut[ep];\n    }\n\n    //Toggle the DTS bit if required\n#if (USB_PING_PONG_MODE == USB_PING_PONG__NO_PING_PONG)\n    handle->STAT.Val ^= _DTSMASK;\n#elif (USB_PING_PONG_MODE == USB_PING_PONG__EP0_OUT_ONLY)\n    if (ep != 0) {\n        handle->STAT.Val ^= _DTSMASK;\n    }\n#endif\n\n    //Set the data pointer, data length, and enable the endpoint\n    handle->ADR = ConvertToPhysicalAddress(data);\n    handle->CNT = len;\n    handle->STAT.Val &= _DTSMASK;\n    handle->STAT.Val |= _USIE | _DTSEN;\n\n    // Point to the next buffer for ping pong purposes.\n    if (dir != 0) {\n        // toggle over the to the next buffer for an IN endpoint\n        *(unsigned char*)&pBDTEntryIn[ep] ^= USB_NEXT_PING_PONG;\n    } else {\n        // toggle over the to the next buffer for an OUT endpoint\n        *(unsigned char*)&pBDTEntryOut[ep] ^= USB_NEXT_PING_PONG;\n    }\n    return handle;\n}\n\n/*\n * USB Callback Functions\n */\n/*\n * Call back that is invoked when a USB suspend is detected.\n */\nvoid __attribute__((weak))\nusbcb_suspend()\n{\n    /* Empty. */\n}\n\n/*\n * This call back is invoked when a wakeup from USB suspend is detected.\n */\nvoid __attribute__((weak))\nusbcb_wake_from_suspend()\n{\n    /* Empty. */\n}\n\n/*\n * Called when start-of-frame packet arrives, every 1 ms.\n */\nvoid __attribute__((weak))\nusbcb_sof_handler()\n{\n    /* Empty. */\n}\n\n/*\n * Called on any USB error interrupt, for debugging purposes.\n */\nvoid __attribute__((weak))\nusbcb_error_handler()\n{\n    /* Empty. */\n}\n\n/*\n * Handle a SETUP SET_DESCRIPTOR request (optional).\n */\nvoid __attribute__((weak))\nusbcb_std_set_dsc_handler()\n{\n    /* Empty. */\n}\n"
  },
  {
    "path": "sys/arch/pic32/hal/usb_device.h",
    "content": "/*\n * USB Device header file\n *\n * This file, with its associated C source file, provides the main substance of\n * the USB device side stack.  These files will receive, transmit, and process\n * various USB commands as well as take action when required for various events\n * that occur on the bus.\n *\n * The software supplied herewith by Microchip Technology Incorporated\n * (the 'Company') for its PIC(R) Microcontroller is intended and\n * supplied to you, the Company's customer, for use solely and\n * exclusively on Microchip PIC Microcontroller products. The\n * software is owned by the Company and/or its supplier, and is\n * protected under applicable copyright laws. All rights are reserved.\n * Any use in violation of the foregoing restrictions may subject the\n * user to criminal sanctions under applicable laws, as well as to\n * civil liability for the breach of the terms and conditions of this\n * license.\n *\n * THIS SOFTWARE IS PROVIDED IN AN 'AS IS' CONDITION. NO WARRANTIES,\n * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED\n * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\n * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT,\n * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR\n * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n */\n#ifndef USBDEVICE_H\n#define USBDEVICE_H\n\n#include <pic32/hal/usb_ch9.h>\n#include <pic32/hal/usb_hal_pic32.h>\n\n/*\n * USB Endpoint Definitions\n * USB Standard EP Address Format: DIR:X:X:X:EP3:EP2:EP1:EP0\n * This is used in the descriptors. See usbcfg.c\n *\n * NOTE: Do not use these values for checking against USTAT.\n * To check against USTAT, use values defined in usbd.h.\n */\n#define _EP_IN          0x80\n#define _EP_OUT         0x00\n#define _EP01_OUT       0x01\n#define _EP01_IN        0x81\n#define _EP02_OUT       0x02\n#define _EP02_IN        0x82\n#define _EP03_OUT       0x03\n#define _EP03_IN        0x83\n#define _EP04_OUT       0x04\n#define _EP04_IN        0x84\n#define _EP05_OUT       0x05\n#define _EP05_IN        0x85\n#define _EP06_OUT       0x06\n#define _EP06_IN        0x86\n#define _EP07_OUT       0x07\n#define _EP07_IN        0x87\n#define _EP08_OUT       0x08\n#define _EP08_IN        0x88\n#define _EP09_OUT       0x09\n#define _EP09_IN        0x89\n#define _EP10_OUT       0x0A\n#define _EP10_IN        0x8A\n#define _EP11_OUT       0x0B\n#define _EP11_IN        0x8B\n#define _EP12_OUT       0x0C\n#define _EP12_IN        0x8C\n#define _EP13_OUT       0x0D\n#define _EP13_IN        0x8D\n#define _EP14_OUT       0x0E\n#define _EP14_IN        0x8E\n#define _EP15_OUT       0x0F\n#define _EP15_IN        0x8F\n\n/* Configuration Attributes */\n#define _DEFAULT        (0x01 << 7)     // Default Value (Bit 7 is set)\n#define _SELF           (0x01 << 6)     // Self-powered (Supports if set)\n#define _RWU            (0x01 << 5)     // Remote Wakeup (Supports if set)\n#define _HNP            (0x01 << 1)     // HNP (Supports if set)\n#define _SRP            (0x01)          // SRP (Supports if set)\n\n/* Endpoint Transfer Type */\n#define _CTRL           0x00            // Control Transfer\n#define _ISO            0x01            // Isochronous Transfer\n#define _BULK           0x02            // Bulk Transfer\n#define _INTERRUPT      0x03            // Interrupt Transfer\n\n/* Isochronous Endpoint Synchronization Type */\n#define _NS             (0x00 << 2)     // No Synchronization\n#define _AS             (0x01 << 2)     // Asynchronous\n#define _AD             (0x02 << 2)     // Adaptive\n#define _SY             (0x03 << 2)     // Synchronous\n\n/* Isochronous Endpoint Usage Type */\n#define _DE             (0x00 << 4)     // Data endpoint\n#define _FE             (0x01 << 4)     // Feedback endpoint\n#define _IE             (0x02 << 4)     // Implicit feedback Data endpoint\n\n#define _ROM            USB_INPIPES_ROM\n#define _RAM            USB_INPIPES_RAM\n\n//These are the directional indicators used for the usb_transfer_one_packet()\n//  function.\n#define OUT_FROM_HOST   0\n#define IN_TO_HOST      1\n\n/*\n * CTRL_TRF_SETUP: Every setup packet has 8 bytes.  This structure\n * allows direct access to the various members of the control\n * transfer.\n */\ntypedef union __attribute__ ((packed)) _CTRL_TRF_SETUP\n{\n    /* Standard Device Requests */\n    struct __attribute__ ((packed))\n    {\n        unsigned char bmRequestType; //from table 9-2 of USB2.0 spec\n        unsigned char bRequest;     //from table 9-2 of USB2.0 spec\n        unsigned short wValue;      //from table 9-2 of USB2.0 spec\n        unsigned short wIndex;      //from table 9-2 of USB2.0 spec\n        unsigned short wLength;     //from table 9-2 of USB2.0 spec\n    };\n    struct __attribute__ ((packed))\n    {\n        unsigned :8;\n        unsigned :8;\n        unsigned short W_Value;     //from table 9-2 of USB2.0 spec, allows byte/bitwise access\n        unsigned short W_Index;     //from table 9-2 of USB2.0 spec, allows byte/bitwise access\n        unsigned short W_Length;    //from table 9-2 of USB2.0 spec, allows byte/bitwise access\n    };\n    struct __attribute__ ((packed))\n    {\n        unsigned Recipient:5;       //Device,Interface,Endpoint,Other\n        unsigned RequestType:2;     //Standard,Class,Vendor,Reserved\n        unsigned DataDir:1;         //Host-to-device,Device-to-host\n        unsigned :8;\n        unsigned char bFeature;     //DEVICE_REMOTE_WAKEUP,ENDPOINT_HALT\n        unsigned :8;\n        unsigned :8;\n        unsigned :8;\n        unsigned :8;\n        unsigned :8;\n    };\n    struct __attribute__ ((packed))\n    {\n        unsigned :8;\n        unsigned :8;\n        unsigned char bDscIndex;        //For Configuration and String DSC Only\n        unsigned char bDescriptorType;  //Device,Configuration,String\n        unsigned short wLangID;         //Language ID\n        unsigned :8;\n        unsigned :8;\n    };\n    struct __attribute__ ((packed))\n    {\n        unsigned :8;\n        unsigned :8;\n        unsigned char bDevADR;      //Device Address 0-127\n        unsigned char bDevADRH;     //Must equal zero\n        unsigned :8;\n        unsigned :8;\n        unsigned :8;\n        unsigned :8;\n    };\n    struct __attribute__ ((packed))\n    {\n        unsigned :8;\n        unsigned :8;\n        unsigned char bConfigurationValue;  //Configuration Value 0-255\n        unsigned char bCfgRSD;              //Must equal zero (Reserved)\n        unsigned :8;\n        unsigned :8;\n        unsigned :8;\n        unsigned :8;\n    };\n    struct __attribute__ ((packed))\n    {\n        unsigned :8;\n        unsigned :8;\n        unsigned char bAltID;       //Alternate Setting Value 0-255\n        unsigned char bAltID_H;     //Must equal zero\n        unsigned char bIntfID;      //Interface Number Value 0-255\n        unsigned char bIntfID_H;    //Must equal zero\n        unsigned :8;\n        unsigned :8;\n    };\n    struct __attribute__ ((packed))\n    {\n        unsigned :8;\n        unsigned :8;\n        unsigned :8;\n        unsigned :8;\n        unsigned char bEPID;        //Endpoint ID (Number & Direction)\n        unsigned char bEPID_H;      //Must equal zero\n        unsigned :8;\n        unsigned :8;\n    };\n    struct __attribute__ ((packed))\n    {\n        unsigned :8;\n        unsigned :8;\n        unsigned :8;\n        unsigned :8;\n        unsigned EPNum:4;           //Endpoint Number 0-15\n        unsigned :3;\n        unsigned EPDir:1;           //Endpoint Direction: 0-OUT, 1-IN\n        unsigned :8;\n        unsigned :8;\n        unsigned :8;\n    };\n\n    /* End: Standard Device Requests */\n\n} CTRL_TRF_SETUP;\n\n// Defintion of the PIPE structure\n//  This structure is used to keep track of data that is sent out\n//  of the stack automatically.\ntypedef struct __attribute__ ((packed))\n{\n    union __attribute__ ((packed))\n    {\n        //Various options of pointers that are available to\n        // get the data from\n        unsigned char *bRam;\n        const unsigned char *bRom;\n        unsigned short *wRam;\n        const unsigned short *wRom;\n    } pSrc;\n    union __attribute__ ((packed))\n    {\n        struct __attribute__ ((packed))\n        {\n            //is this transfer from RAM or ROM?\n            unsigned ctrl_trf_mem          :1;\n            unsigned reserved              :5;\n            //include a zero length packet after\n            //data is done if data_size%ep_size = 0?\n            unsigned includeZero           :1;\n            //is this PIPE currently in use\n            unsigned busy                  :1;\n        } bits;\n        unsigned char Val;\n    } info;\n    unsigned short wCount;\n} IN_PIPE;\n\n#define CTRL_TRF_RETURN void\n#define CTRL_TRF_PARAMS void\ntypedef struct __attribute__ ((packed))\n{\n    union __attribute__ ((packed))\n    {\n        //Various options of pointers that are available to\n        // get the data from\n        unsigned char *bRam;\n        unsigned short *wRam;\n    } pDst;\n    union __attribute__ ((packed))\n    {\n        struct __attribute__ ((packed))\n        {\n            unsigned reserved              :7;\n            //is this PIPE currently in use\n            unsigned busy                  :1;\n        } bits;\n        unsigned char Val;\n    } info;\n    unsigned short wCount;\n    CTRL_TRF_RETURN (*pFunc)(CTRL_TRF_PARAMS);\n} OUT_PIPE;\n\n//Various options for setting the PIPES\n#define USB_INPIPES_ROM            0x00     //Data comes from RAM\n#define USB_INPIPES_RAM            0x01     //Data comes from ROM\n#define USB_INPIPES_BUSY           0x80     //The PIPE is busy\n#define USB_INPIPES_INCLUDE_ZERO   0x40     //include a trailing zero packet\n#define USB_INPIPES_NO_DATA        0x00     //no data to send\n#define USB_INPIPES_NO_OPTIONS     0x00     //no options set\n\n#define USB_EP0_ROM            USB_INPIPES_ROM\n#define USB_EP0_RAM            USB_INPIPES_RAM\n#define USB_EP0_BUSY           USB_INPIPES_BUSY\n#define USB_EP0_INCLUDE_ZERO   USB_INPIPES_INCLUDE_ZERO\n#define USB_EP0_NO_DATA        USB_INPIPES_NO_DATA\n#define USB_EP0_NO_OPTIONS     USB_INPIPES_NO_OPTIONS\n\n/*\n * Standard Request Codes\n * USB 2.0 Spec Ref Table 9-4\n */\n#define GET_STATUS  0\n#define CLR_FEATURE 1\n#define SET_FEATURE 3\n#define SET_ADR     5\n#define GET_DSC     6\n#define SET_DSC     7\n#define GET_CFG     8\n#define SET_CFG     9\n#define GET_INTF    10\n#define SET_INTF    11\n#define SYNCH_FRAME 12\n\n/* Section: Standard Feature Selectors */\n#define DEVICE_REMOTE_WAKEUP    0x01\n#define ENDPOINT_HALT           0x00\n\n/* Section: USB Device States - To be used with [BYTE usb_device_state] */\n\n/* Detached is the state in which the device is not attached to the bus.  When\n * in the detached state a device should not have any pull-ups attached to either\n * the D+ or D- line.  This defintions is a return value of the\n * function usb_get_device_state()\n */\n#define DETACHED_STATE          0x00\n\n/* Attached is the state in which the device is attached ot the bus but the\n * hub/port that it is attached to is not yet configured. This defintions is a\n * return value of the function usb_get_device_state()\n */\n#define ATTACHED_STATE          0x01\n\n/* Powered is the state in which the device is attached to the bus and the\n * hub/port that it is attached to is configured. This defintions is a return\n * value of the function usb_get_device_state()\n */\n#define POWERED_STATE           0x02\n\n/* Default state is the state after the device receives a RESET command from\n * the host. This defintions is a return value of the function usb_get_device_state()\n */\n#define DEFAULT_STATE           0x04\n\n/* Address pending state is not an official state of the USB defined states.\n * This state is internally used to indicate that the device has received a\n * SET_ADDRESS command but has not received the STATUS stage of the transfer yet.\n * The device is should not switch addresses until after the STATUS stage is\n * complete.  This defintions is a return value of the function\n * usb_get_device_state()\n */\n#define ADR_PENDING_STATE       0x08\n\n/* Address is the state in which the device has its own specific address on the\n * bus. This defintions is a return value of the function usb_get_device_state().\n */\n#define ADDRESS_STATE           0x10\n\n/* Configured is the state where the device has been fully enumerated and is\n * operating on the bus.  The device is now allowed to excute its application\n * specific tasks.  It is also allowed to increase its current consumption to the\n * value specified in the configuration descriptor of the current configuration.\n * This defintions is a return value of the function usb_get_device_state().\n */\n#define CONFIGURED_STATE        0x20\n\n/* UCFG Initialization Parameters */\n#define SetConfigurationOptions()   {U1CNFG1 = 0;}\n\n/* UEPn Initialization Parameters */\n#define EP_CTRL         0x0C    // Cfg Control pipe for this ep\n#define EP_OUT          0x18    // Cfg OUT only pipe for this ep\n#define EP_IN           0x14    // Cfg IN only pipe for this ep\n#define EP_OUT_IN       0x1C    // Cfg both OUT & IN pipes for this ep\n#define HSHK_EN         0x01    // Enable handshake packet\n                                // Handshake should be disable for isoch\n\n#define USB_HANDSHAKE_ENABLED   0x01\n#define USB_HANDSHAKE_DISABLED  0x00\n\n#define USB_OUT_ENABLED         0x08\n#define USB_OUT_DISABLED        0x00\n\n#define USB_IN_ENABLED          0x04\n#define USB_IN_DISABLED         0x00\n\n#define USB_ALLOW_SETUP         0x00\n#define USB_DISALLOW_SETUP      0x10\n\n#define USB_STALL_ENDPOINT      0x02\n\n// USB_HANDLE is a pointer to an entry in the BDT.  This pointer can be used\n// to read the length of the last transfer, the status of the last transfer,\n// and various other information.  Insure to initialize USB_HANDLE objects\n// to NULL so that they are in a known state during their first usage.\n#define USB_HANDLE volatile BDT_ENTRY*\n\n// PIC32 supports only full ping-pong mode.\n#define USB_PING_PONG_MODE USB_PING_PONG__FULL_PING_PONG\n\n/* Size of buffer for end-point EP0.\n * Valid Options: 8, 16, 32, or 64 bytes.\n * Using larger options take more SRAM, but\n * does not provide much advantage in most types\n * of applications.  Exceptions to this, are applications\n * that use EP0 IN or OUT for sending large amounts of\n * application related data.\n */\n#ifndef USB_EP0_BUFF_SIZE\n#   define USB_EP0_BUFF_SIZE    8\n#endif\n\n/*\n * Only one interface by default.\n */\n#ifndef USB_MAX_NUM_INT\n#   define USB_MAX_NUM_INT      1\n#endif\n\n// Definitions for the BDT\nextern volatile BDT_ENTRY usb_buffer[(USB_MAX_EP_NUMBER + 1) * 4];\n\n// Device descriptor\nextern const USB_DEVICE_DESCRIPTOR usb_device;\n\n// Array of configuration descriptors\nextern const unsigned char *const usb_config[];\nextern const unsigned char usb_config1_descriptor[];\n\n// Array of string descriptors\nextern const unsigned char *const usb_string[];\n\n// Buffer for control transfers\nextern volatile CTRL_TRF_SETUP usb_setup_pkt;           // 8-byte only\n\n/* Control Transfer States */\n#define WAIT_SETUP              0\n#define CTRL_TRF_TX             1\n#define CTRL_TRF_RX             2\n\n/* v2.1 fix - Short Packet States - Used by Control Transfer Read  - CTRL_TRF_TX */\n#define SHORT_PKT_NOT_USED      0\n#define SHORT_PKT_PENDING       1\n#define SHORT_PKT_SENT          2\n\n/* USB PID: Token Types - See chapter 8 in the USB specification */\n#define SETUP_TOKEN             0x0D    // 0b00001101\n#define OUT_TOKEN               0x01    // 0b00000001\n#define IN_TOKEN                0x09    // 0b00001001\n\n/* bmRequestType Definitions */\n#define HOST_TO_DEV             0\n#define DEV_TO_HOST             1\n\n#define STANDARD                0x00\n#define CLASS                   0x01\n#define VENDOR                  0x02\n\n#define RCPT_DEV                0\n#define RCPT_INTF               1\n#define RCPT_EP                 2\n#define RCPT_OTH                3\n\nextern unsigned usb_device_state;\nextern unsigned usb_active_configuration;\nextern IN_PIPE usb_in_pipe[1];\nextern OUT_PIPE usb_out_pipe[1];\n\n/*\n  Function:\n        void usb_device_tasks(void)\n\n  Summary:\n    This function is the main state machine of the USB device side stack.\n    This function should be called periodically to receive and transmit\n    packets through the stack. This function should be called preferably\n    once every 100us during the enumeration process. After the enumeration\n    process this function still needs to be called periodically to respond\n    to various situations on the bus but is more relaxed in its time\n    requirements. This function should also be called at least as fast as\n    the OUT data expected from the PC.\n\n  Description:\n    This function is the main state machine of the USB device side stack.\n    This function should be called periodically to receive and transmit\n    packets through the stack. This function should be called preferably\n    once every 100us during the enumeration process. After the enumeration\n    process this function still needs to be called periodically to respond\n    to various situations on the bus but is more relaxed in its time\n    requirements. This function should also be called at least as fast as\n    the OUT data expected from the PC.\n\n    Typical usage:\n    <code>\n    void main(void)\n    {\n        usb_device_init();\n        while (1)\n        {\n            usb_device_tasks();\n            if ((usb_get_device_state() \\< CONFIGURED_STATE) || usb_is_device_suspended())\n            {\n                // Either the device is not configured or we are suspended\n                // so we don't want to do execute any application code\n                continue;   //go back to the top of the while loop\n            } else {\n                // Otherwise we are free to run user application code.\n                UserApplication();\n            }\n        }\n    }\n    </code>\n\n  Conditions:\n    None\n  Remarks:\n    This function should be called preferably once every 100us during the\n    enumeration process. After the enumeration process this function still\n    needs to be called periodically to respond to various situations on the\n    bus but is more relaxed in its time requirements.\n  */\nvoid usb_device_tasks(void);\n\n/*\n    Function:\n        void usb_device_init(void)\n\n    Description:\n        This function initializes the device stack it in the default state. The\n        USB module will be completely reset including all of the internal\n        variables, registers, and interrupt flags.\n\n    Precondition:\n        This function must be called before any of the other USB Device\n        functions can be called, including usb_device_tasks().\n\n    Parameters:\n        None\n\n    Return Values:\n        None\n\n    Remarks:\n        None\n\n  */\nvoid usb_device_init(void);\n\n/*\n  Function:\n        int usb_get_remote_wakeup_status(void)\n\n  Summary:\n    This function indicates if remote wakeup has been enabled by the host.\n    Devices that support remote wakeup should use this function to\n    determine if it should send a remote wakeup.\n\n  Description:\n    This function indicates if remote wakeup has been enabled by the host.\n    Devices that support remote wakeup should use this function to\n    determine if it should send a remote wakeup.\n\n    If a device does not support remote wakeup (the Remote wakeup bit, bit\n    5, of the bmAttributes field of the Configuration descriptor is set to\n    1), then it should not send a remote wakeup command to the PC and this\n    function is not of any use to the device. If a device does support\n    remote wakeup then it should use this function as described below.\n\n    If this function returns FALSE and the device is suspended, it should\n    not issue a remote wakeup (resume).\n\n    If this function returns TRUE and the device is suspended, it should\n    issue a remote wakeup (resume).\n\n    A device can add remote wakeup support by having the _RWU symbol added\n    in the configuration descriptor (located in the usb_descriptors.c file\n    in the project). This done in the 8th byte of the configuration\n    descriptor. For example:\n\n    <code lang=\"c\">\n    const unsigned char configDescriptor1[]={\n        0x09,                           // Size\n        USB_DESCRIPTOR_CONFIGURATION,   // descriptor type\n        DESC_CONFIG_WORD(0x0022),       // Total length\n        1,                              // Number of interfaces\n        1,                              // Index value of this cfg\n        0,                              // Configuration string index\n        _DEFAULT | _SELF | _RWU,        // Attributes, see usb_device.h\n        50,                             // Max power consumption in 2X mA(100mA)\n\n        //The rest of the configuration descriptor should follow\n    </code>\n\n    For more information about remote wakeup, see the following section of\n    the USB v2.0 specification available at www.usb.org:\n        * Section 9.2.5.2\n        * Table 9-10\n        * Section 7.1.7.7\n        * Section 9.4.5\n\n  Conditions:\n    None\n\n  Return Values:\n    TRUE -   Remote Wakeup has been enabled by the host\n    FALSE -  Remote Wakeup is not currently enabled\n\n  Remarks:\n    None\n\n  */\n#define usb_get_remote_wakeup_status() usb_remote_wakeup\n\n/*\n  Function:\n        unsigned usb_get_device_state(void)\n\n  Summary:\n    This function will return the current state of the device on the USB.\n    This function should return CONFIGURED_STATE before an application\n    tries to send information on the bus.\n  Description:\n    This function returns the current state of the device on the USB. This\n    \\function is used to determine when the device is ready to communicate\n    on the bus. Applications should not try to send or receive data until\n    this function returns CONFIGURED_STATE.\n\n    It is also important that applications yield as much time as possible\n    to the usb_device_tasks() function as possible while the this function\n    \\returns any value between ATTACHED_STATE through CONFIGURED_STATE.\n\n    For more information about the various device states, please refer to\n    the USB specification section 9.1 available from www.usb.org.\n\n    Typical usage:\n    <code>\n    void main(void)\n    {\n        usb_device_init();\n        while(1)\n        {\n            usb_device_tasks();\n            if ((usb_get_device_state() \\< CONFIGURED_STATE) || usb_is_device_suspended())\n            {\n                //Either the device is not configured or we are suspended\n                //  so we don't want to do execute any application code\n                continue;   //go back to the top of the while loop\n            }\n            else\n            {\n                //Otherwise we are free to run user application code.\n                UserApplication();\n            }\n        }\n    }\n    </code>\n  Conditions:\n    None\n  Return Values:\n    DETACHED_STATE -     The device is not attached to the bus\n    ATTACHED_STATE -     The device is attached to the bus but\n    POWERED_STATE -      The device is not officially in the powered state\n    DEFAULT_STATE -      The device has received a RESET from the host\n    ADR_PENDING_STATE -  The device has received the SET_ADDRESS command but\n                         hasn't received the STATUS stage of the command so\n                         it is still operating on address 0.\n    ADDRESS_STATE -      The device has an address assigned but has not\n                         received a SET_CONFIGURATION command yet or has\n                         received a SET_CONFIGURATION with a configuration\n                         number of 0 (deconfigured)\n    CONFIGURED_STATE -   the device has received a non\\-zero\n                         SET_CONFIGURATION command is now ready for\n                         communication on the bus.\n  Remarks:\n    None\n  */\n#define usb_get_device_state() usb_device_state\n\n/*\n  Function:\n        int usb_is_device_suspended(void)\n\n  Summary:\n    This function indicates if this device is currently suspended. When a\n    device is suspended it will not be able to transfer data over the bus.\n  Description:\n    This function indicates if this device is currently suspended. When a\n    device is suspended it will not be able to transfer data over the bus.\n    This function can be used by the application to skip over section of\n    code that do not need to exectute if the device is unable to send data\n    over the bus.\n\n    Typical usage:\n    <code>\n       void main(void)\n       {\n           usb_device_init();\n           while(1)\n           {\n               usb_device_tasks();\n               if ((usb_get_device_state() \\< CONFIGURED_STATE) || usb_is_device_suspended())\n               {\n                   //Either the device is not configured or we are suspended\n                   //  so we don't want to do execute any application code\n                   continue;   //go back to the top of the while loop\n               }\n               else\n               {\n                   //Otherwise we are free to run user application code.\n                   UserApplication();\n               }\n           }\n       }\n    </code>\n  Conditions:\n    None\n  Return Values:\n    TRUE -   this device is suspended.\n    FALSE -  this device is not suspended.\n  Remarks:\n    None\n */\n#define usb_is_device_suspended() (U1PWRC & PIC32_U1PWRC_USUSPEND)\n\nvoid usb_ctrl_ep_service (void);\nvoid usb_ctrl_trf_setup_handler (void);\nvoid usb_ctrl_trf_in_handler (void);\nvoid usb_check_std_request (void);\nvoid usb_std_get_dsc_handler (void);\nvoid usb_ctrl_ep_service_complete (void);\nvoid usb_ctrl_trf_tx_service (void);\nvoid usb_prepare_for_next_setup_trf (void);\nvoid usb_ctrl_trf_rx_service (void);\nvoid usb_std_set_cfg_handler (void);\nvoid usb_std_get_status_handler (void);\nvoid usb_std_feature_req_handler (void);\nvoid usb_ctrl_trf_out_handler (void);\n\nvoid usb_wake_from_suspend (void);\nvoid usb_suspend (void);\nvoid usb_stall_handler (void);\nvolatile USB_HANDLE usb_transfer_one_packet (unsigned ep, unsigned dir, unsigned char* data, unsigned len);\nvoid usb_enable_endpoint (unsigned ep, unsigned options);\nvoid usb_configure_endpoint (unsigned EPNum, unsigned direction);\n\n#if defined(USB_DYNAMIC_EP_CONFIG)\n    void usb_init_ep(unsigned char const* pConfig);\n#else\n    #define usb_init_ep(a)\n#endif\n\n/* Section: CALLBACKS */\n\n/*\n  Function:\n      void usbcb_suspend(void)\n\n  Summary:\n    Call back that is invoked when a USB suspend is detected.\n  Description:\n    Call back that is invoked when a USB suspend is detected.\n\n    \\Example power saving code. Insert appropriate code here for the\n    desired application behavior. If the microcontroller will be put to\n    sleep, a process similar to that shown below may be used:\n\n    \\Example Psuedo Code:\n    <code>\n    ConfigureIOPinsForLowPower();\n    SaveStateOfAllInterruptEnableBits();\n    DisableAllInterruptEnableBits();\n\n    //should enable at least USBActivityIF as a wake source\n    EnableOnlyTheInterruptsWhichWillBeUsedToWakeTheMicro();\n\n    Sleep();\n\n    //Preferrably, this should be done in the\n    //  usbcb_wake_from_suspend() function instead.\n    RestoreStateOfAllPreviouslySavedInterruptEnableBits();\n\n    //Preferrably, this should be done in the\n    //  usbcb_wake_from_suspend() function instead.\n    RestoreIOPinsToNormal();\n    </code>\n\n    IMPORTANT NOTE: Do not clear the USBActivityIF (ACTVIF) bit here. This\n    bit is cleared inside the usb_device.c file. Clearing USBActivityIF\n    here will cause things to not work as intended.\n  Conditions:\n    None\n\n    Paramters: None\n  Side Effects:\n    None\n\n    Remark: None\n  */\nvoid usbcb_suspend (void);\n\n/*\n Function:\n   void usbcb_wake_from_suspend (void)\n\n Summary:\n   This call back is invoked when a wakeup from USB suspend\n   is detected.\n\n Description:\n   The host may put USB peripheral devices in low power\n   suspend mode (by \"sending\" 3+ms of idle).  Once in suspend\n   mode, the host may wake the device back up by sending non-\n   idle state signalling.\n\n   This call back is invoked when a wakeup from USB suspend\n   is detected.\n\n   If clock switching or other power savings measures were taken when\n   executing the usbcb_suspend() function, now would be a good time to\n   switch back to normal full power run mode conditions.  The host allows\n   a few milliseconds of wakeup time, after which the device must be\n   fully back to normal, and capable of receiving and processing USB\n   packets.  In order to do this, the USB module must receive proper\n   clocking (IE: 48MHz clock must be available to SIE for full speed USB\n   operation).\n\n PreCondition:  None\n\n Parameters:    None\n\n Return Values: None\n\n Remarks:       None\n */\nvoid usbcb_wake_from_suspend (void);\n\n/*\n  Function:\n    void usbcb_sof_handler (void)\n\n  Summary:\n    This callback is called when a SOF packet is received by the host.\n    (optional)\n\n  Description:\n    This callback is called when a SOF packet is received by the host.\n    (optional)\n\n    The USB host sends out a SOF packet to full-speed\n    devices every 1 ms. This interrupt may be useful\n    for isochronous pipes. End designers should\n    implement callback routine as necessary.\n\n  PreCondition:\n    None\n\n  Parameters:\n    None\n\n  Return Values:\n    None\n\n  Remarks:\n    None\n */\nvoid usbcb_sof_handler (void);\n\n/*\n  Function:\n    void usbcb_error_handler (void)\n\n  Summary:\n    This callback is called whenever a USB error occurs. (optional)\n\n  Description:\n    This callback is called whenever a USB error occurs. (optional)\n\n    The purpose of this callback is mainly for\n    debugging during development. Check UEIR to see\n    which error causes the interrupt.\n\n  PreCondition:\n    None\n\n  Parameters:\n    None\n\n  Return Values:\n    None\n\n  Remarks:\n    No need to clear UEIR to 0 here.\n    Callback caller is already doing that.\n\n    Typically, user firmware does not need to do anything special\n    if a USB error occurs.  For example, if the host sends an OUT\n    packet to your device, but the packet gets corrupted (ex:\n    because of a bad connection, or the user unplugs the\n    USB cable during the transmission) this will typically set\n    one or more USB error interrupt flags.  Nothing specific\n    needs to be done however, since the SIE will automatically\n    send a \"NAK\" packet to the host.  In response to this, the\n    host will normally retry to send the packet again, and no\n    data loss occurs.  The system will typically recover\n    automatically, without the need for application firmware\n    intervention.\n\n    Nevertheless, this callback function is provided, such as\n    for debugging purposes.\n */\nvoid usbcb_error_handler (void);\n\n/*\n  Function:\n      void usbcb_check_other_req (void)\n\n  Summary:\n    This function is called whenever a request comes over endpoint 0 (the\n    control endpoint) that the stack does not know how to handle.\n  Description:\n    When SETUP packets arrive from the host, some firmware must process the\n    request and respond appropriately to fulfill the request. Some of the\n    SETUP packets will be for standard USB \"chapter 9\" (as in, fulfilling\n    chapter 9 of the official USB specifications) requests, while others\n    may be specific to the USB device class that is being implemented. For\n    \\example, a HID class device needs to be able to respond to \"GET\n    REPORT\" type of requests. This is not a standard USB chapter 9 request,\n    and therefore not handled by usb_device.c. Instead this request should\n    be handled by class specific firmware, such as that contained in\n    usb_function_hid.c.\n\n    Typical Usage:\n    <code>\n    void usbcb_check_other_req (void)\n    {\n        //Since the stack didn't handle the request I need to check\n        //  my class drivers to see if it is for them\n        USBCheckMSDRequest();\n    }\n    </code>\n  Conditions:\n    None\n  Remarks:\n    None\n  */\nvoid usbcb_check_other_req (void);\n\n/*\n  Function:\n    void usbcb_std_set_dsc_handler (void)\n\n  Summary:\n    This callback is called when a SET_DESCRIPTOR request is received (optional)\n\n  Description:\n    The usbcb_std_set_dsc_handler() callback function is\n    called when a SETUP, bRequest: SET_DESCRIPTOR request\n    arrives.  Typically SET_DESCRIPTOR requests are\n    not used in most applications, and it is\n    optional to support this type of request.\n\n  PreCondition:\n    None\n\n  Parameters:\n    None\n\n  Return Values:\n    None\n\n  Remark:            None\n */\nvoid usbcb_std_set_dsc_handler (void);\n\n/*\n  Function:\n      void usbcb_init_ep (void)\n\n  Summary:\n    This function is called whenever the device receives a\n    SET_CONFIGURATION request.\n  Description:\n    This function is called when the device becomes initialized, which\n    occurs after the host sends a SET_CONFIGURATION (wValue not = 0)\n    request. This callback function should initialize the endpoints for the\n    device's usage according to the current configuration.\n\n    Typical Usage:\n    <code>\n    void usbcb_init_ep (void)\n    {\n        usb_enable_endpoint(MSD_DATA_IN_EP,USB_IN_ENABLED|USB_OUT_ENABLED|USB_HANDSHAKE_ENABLED|USB_DISALLOW_SETUP);\n        USBMSDInit();\n    }\n    </code>\n  Conditions:\n    None\n  Remarks:\n    None\n  */\nvoid usbcb_init_ep (void);\n\n/*\n  Function:\n        void usbcb_send_resume (void)\n\n  Summary:\n    This function should be called to initiate a remote wakeup. (optional)\n  Description:\n    The USB specifications allow some types of USB peripheral devices to\n    wake up a host PC (such as if it is in a low power suspend to RAM\n    state). This can be a very useful feature in some USB applications,\n    such as an Infrared remote control receiver. If a user presses the\n    \"power\" button on a remote control, it is nice that the IR receiver can\n    detect this signalling, and then send a USB \"command\" to the PC to wake\n    up.\n\n    The usbcb_send_resume() \"callback\" function is used to send this special\n    USB signalling which wakes up the PC. This function may be called by\n    application firmware to wake up the PC. This function should only be\n    called when:\n\n      1. The USB driver used on the host PC supports the remote wakeup\n         capability.\n      2. The USB configuration descriptor indicates the device is remote\n         wakeup capable in the bmAttributes field. (see usb_descriptors.c and\n         _RWU)\n      3. The USB host PC is currently sleeping, and has previously sent\n         your device a SET FEATURE setup packet which \"armed\" the remote wakeup\n         capability. (see usb_get_remote_wakeup_status())\n\n    This callback should send a RESUME signal that has the period of\n    1-15ms.\n\n    Typical Usage:\n    <code>\n    if ((usb_device_state == CONFIGURED_STATE)\n        &amp;&amp; usb_is_device_suspended()\n        &amp;&amp; (usb_get_remote_wakeup_status() == TRUE))\n    {\n        if (ButtonPressed)\n        {\n            // Wake up the USB module from suspend\n            usb_wake_from_suspend();\n\n            // Issue a remote wakeup command on the bus\n            usbcb_send_resume();\n        }\n    }\n    </code>\n  Conditions:\n    None\n  Remarks:\n    A user can switch to primary first by calling usbcb_wake_from_suspend() if\n    required/desired.\n\n    The modifiable section in this routine should be changed to meet the\n    application needs. Current implementation temporary blocks other\n    functions from executing for a period of 1-13 ms depending on the core\n    frequency.\n\n    According to USB 2.0 specification section 7.1.7.7, \"The remote wakeup\n    device must hold the resume signaling for at lest 1 ms but for no more\n    than 15 ms.\" The idea here is to use a delay counter loop, using a\n    common value that would work over a wide range of core frequencies.\n    That value selected is 1800. See table below:\n    <table>\n    Core Freq(MHz)   MIP (for PIC18)   RESUME Signal Period (ms)\n    ---------------  ----------------  --------------------------\n    48               12                1.05\n    4                1                 12.6\n    </table>\n      * These timing could be incorrect when using code optimization or\n        extended instruction mode, or when having other interrupts enabled.\n        Make sure to verify using the MPLAB SIM's Stopwatch and verify the\n        actual signal on an oscilloscope.\n      * These timing numbers should be recalculated when using PIC24 or\n        PIC32 as they have different clocking structures.\n      * A timer can be used in place of the blocking loop if desired.\n\n*/\nvoid usbcb_send_resume (void);\n\n/*\n  Function:\n    void usbcb_ep0_data_received(void)\n\n  Summary:\n    This function is called whenever a EP0 data\n    packet is received. (optional)\n\n  Description:\n    This function is called whenever a EP0 data\n    packet is received.  This gives the user (and\n    thus the various class examples a way to get\n    data that is received via the control endpoint.\n    This function needs to be used in conjunction\n    with the usbcb_check_other_req() function since\n    the usbcb_check_other_req() function is the apps\n    method for getting the initial control transfer\n    before the data arrives.\n\n  PreCondition:\n    ENABLE_EP0_DATA_RECEIVED_CALLBACK must be\n    defined already (in target.cfg)\n\n  Parameters:\n    None\n\n  Return Values:\n    None\n\n  Remarks:\n    None\n*/\nvoid usbcb_ep0_data_received (void);\n\n\n\n\n/* Section: MACROS */\n\n#define DESC_CONFIG_BYTE(a) (a)\n#define DESC_CONFIG_WORD(a) (a&0xFF),((a>>8)&0xFF)\n#define DESC_CONFIG_DWORD(a) (a&0xFF),((a>>8)&0xFF),((a>>16)&0xFF),((a>>24)&0xFF)\n\n/*\n  Function:\n    int usb_handle_busy(USB_HANDLE handle)\n\n  Summary:\n    Checks to see if the input handle is busy\n\n  Description:\n    Checks to see if the input handle is busy\n\n    Typical Usage\n    <code>\n    //make sure that the last transfer isn't busy by checking the handle\n    if (! usb_handle_busy(handle))\n    {\n        //Send the data contained in the INPacket[] array out on\n        //  endpoint USBGEN_EP_NUM\n        handle = USBGenWrite (USBGEN_EP_NUM, (unsigned char*) &INPacket[0],  sizeof(INPacket));\n    }\n    </code>\n\n  Conditions:\n    None\n  Input:\n    USB_HANDLE handle -  handle of the transfer that you want to check the\n                         status of\n  Return Values:\n    TRUE -   The specified handle is busy\n    FALSE -  The specified handle is free and available for a transfer\n  Remarks:\n    None\n  */\n#define usb_handle_busy(handle) (handle != 0 && handle->STAT.UOWN)\n\n/*\n    Function:\n        unsigned short usb_handle_get_length(USB_HANDLE handle)\n\n    Summary:\n        Retrieves the length of the destination buffer of the input\n        handle\n\n    Description:\n        Retrieves the length of the destination buffer of the input\n        handle\n\n    PreCondition:\n        None\n\n    Parameters:\n        USB_HANDLE handle - the handle to the transfer you want the\n        address for.\n\n    Return Values:\n        unsigned short - length of the current buffer that the input handle\n        points to.  If the transfer is complete then this is the\n        length of the data transmitted or the length of data\n        actually received.\n\n    Remarks:\n        None\n\n */\n#define usb_handle_get_length(handle) (handle->CNT)\n\n/*\n    Function:\n        unsigned short usb_handle_get_addr(USB_HANDLE)\n\n    Summary:\n        Retrieves the address of the destination buffer of the input\n        handle\n\n    Description:\n        Retrieves the address of the destination buffer of the input\n        handle\n\n    PreCondition:\n        None\n\n    Parameters:\n        USB_HANDLE handle - the handle to the transfer you want the\n        address for.\n\n    Return Values:\n        unsigned short - address of the current buffer that the input handle\n        points to.\n\n    Remarks:\n        None\n\n */\n#define usb_handle_get_addr(handle) (handle->ADR)\n\n/*\n    Function:\n        void usb_ep0_set_source_ram(unsigned char* src)\n\n    Summary:\n        Sets the address of the data to send over the\n        control endpoint\n\n    PreCondition:\n        None\n\n    Paramters:\n        src - address of the data to send\n\n    Return Values:\n        None\n\n    Remarks:\n        None\n\n */\n#define usb_ep0_set_source_ram(src) usb_in_pipe[0].pSrc.bRam = src\n\n/*\n    Function:\n        void usb_ep0_set_source_rom(unsigned char* src)\n\n    Summary:\n        Sets the address of the data to send over the\n        control endpoint\n\n    PreCondition:\n        None\n\n    Parameters:\n        src - address of the data to send\n\n    Return Values:\n        None\n\n    Remarks:\n        None\n\n */\n#define usb_ep0_set_source_rom(src) usb_in_pipe[0].pSrc.bRom = src\n\n/*\n    Function:\n        void usb_ep0_transmit(unsigned char options)\n\n    Summary:\n        Sets the address of the data to send over the\n        control endpoint\n\n    PreCondition:\n        None\n\n    Paramters:\n        options - the various options that you want\n                  when sending the control data. Options are:\n                       USB_INPIPES_ROM\n                       USB_INPIPES_RAM\n                       USB_INPIPES_BUSY\n                       USB_INPIPES_INCLUDE_ZERO\n                       USB_INPIPES_NO_DATA\n                       USB_INPIPES_NO_OPTIONS\n\n    Return Values:\n        None\n\n    Remarks:\n        None\n\n */\n#define usb_ep0_transmit(options) usb_in_pipe[0].info.Val = options | USB_INPIPES_BUSY\n\n/*\n    Function:\n        void usb_ep0_set_size(unsigned short size)\n\n    Summary:\n        Sets the size of the data to send over the\n        control endpoint\n\n    PreCondition:\n        None\n\n    Parameters:\n        size - the size of the data needing to be transmitted\n\n    Return Values:\n        None\n\n    Remarks:\n        None\n\n */\n#define usb_ep0_set_size(size) usb_in_pipe[0].wCount = size\n\n/*\n    Function:\n        void usb_ep0_send_ram_ptr(unsigned char* src, unsigned short size, unsigned char Options)\n\n    Summary:\n        Sets the source, size, and options of the data\n        you wish to send from a RAM source\n\n    PreCondition:\n        None\n\n    Parameters:\n        src - address of the data to send\n        size - the size of the data needing to be transmitted\n        options - the various options that you want\n        when sending the control data. Options are:\n        USB_INPIPES_ROM\n        USB_INPIPES_RAM\n        USB_INPIPES_BUSY\n        USB_INPIPES_INCLUDE_ZERO\n        USB_INPIPES_NO_DATA\n        USB_INPIPES_NO_OPTIONS\n\n    Return Values:\n        None\n\n    Remarks:\n        None\n\n */\n#define usb_ep0_send_ram_ptr(src,size,options)  {usb_ep0_set_source_ram(src);usb_ep0_set_size(size);usb_ep0_transmit(options | USB_EP0_RAM);}\n\n/*\n    Function:\n        void usb_ep0_send_rom_ptr(unsigned char* src, unsigned short size, unsigned char Options)\n\n    Summary:\n        Sets the source, size, and options of the data\n        you wish to send from a ROM source\n\n    PreCondition:\n        None\n\n    Parameters:\n        src - address of the data to send\n        size - the size of the data needing to be transmitted\n        options - the various options that you want\n        when sending the control data. Options are:\n        USB_INPIPES_ROM\n        USB_INPIPES_RAM\n        USB_INPIPES_BUSY\n        USB_INPIPES_INCLUDE_ZERO\n        USB_INPIPES_NO_DATA\n        USB_INPIPES_NO_OPTIONS\n\n    Return Values:\n        None\n\n    Remarks:\n        None\n\n */\n#define usb_ep0_send_rom_ptr(src,size,options)  {usb_ep0_set_source_rom(src);usb_ep0_set_size(size);usb_ep0_transmit(options | USB_EP0_ROM);}\n\n/*\n    Function:\n        USB_HANDLE usb_tx_one_packet(unsigned char ep, unsigned char* data, unsigned short len)\n\n    Summary:\n        Sends the specified data out the specified endpoint\n\n    PreCondition:\n        None\n\n    Parameters:\n        ep - the endpoint you want to send the data out of\n        data - the data that you wish to send\n        len - the length of the data that you wish to send\n\n    Return Values:\n        USB_HANDLE - a handle for the transfer.  This information\n        should be kept to track the status of the transfer\n\n    Remarks:\n        None\n\n */\n#define usb_tx_one_packet(ep, data, len)    usb_transfer_one_packet(ep, IN_TO_HOST, data, len)\n\n/*\n    Function:\n        void usb_rx_one_packet(unsigned char ep, unsigned char* data, unsigned short len)\n\n    Summary:\n        Receives the specified data out the specified endpoint\n\n    PreCondition:\n        None\n\n    Parameters:\n        ep - the endpoint you want to receive the data into\n        data - where the data will go when it arrives\n        len - the length of the data that you wish to receive\n\n    Return Values:\n        None\n\n    Remarks:\n        None\n\n */\n#define usb_rx_one_packet(ep, data, len)    usb_transfer_one_packet(ep, OUT_FROM_HOST, data, len)\n\n/*\n    Function:\n        void usb_stall_endpoint(unsigned ep, unsigned dir)\n\n    Summary:\n         STALLs the specified endpoint\n\n    PreCondition:\n        None\n\n    Parameters:\n        unsigned char ep - the endpoint the data will be transmitted on\n        unsigned char dir - the direction of the transfer\n\n    Return Values:\n        None\n\n    Remarks:\n        None\n */\nvoid usb_stall_endpoint(unsigned ep, unsigned dir);\n\n#if (USB_PING_PONG_MODE == USB_PING_PONG__NO_PING_PONG)\n    #define USB_NEXT_EP0_OUT_PING_PONG 0x0000   // Used in USB Device Mode only\n    #define USB_NEXT_EP0_IN_PING_PONG 0x0000    // Used in USB Device Mode only\n    #define USB_NEXT_PING_PONG 0x0000           // Used in USB Device Mode only\n    #define EP0_OUT_EVEN    0                   // Used in USB Device Mode only\n    #define EP0_OUT_ODD     0                   // Used in USB Device Mode only\n    #define EP0_IN_EVEN     1                   // Used in USB Device Mode only\n    #define EP0_IN_ODD      1                   // Used in USB Device Mode only\n    #define EP1_OUT_EVEN    2                   // Used in USB Device Mode only\n    #define EP1_OUT_ODD     2                   // Used in USB Device Mode only\n    #define EP1_IN_EVEN     3                   // Used in USB Device Mode only\n    #define EP1_IN_ODD      3                   // Used in USB Device Mode only\n    #define EP2_OUT_EVEN    4                   // Used in USB Device Mode only\n    #define EP2_OUT_ODD     4                   // Used in USB Device Mode only\n    #define EP2_IN_EVEN     5                   // Used in USB Device Mode only\n    #define EP2_IN_ODD      5                   // Used in USB Device Mode only\n    #define EP3_OUT_EVEN    6                   // Used in USB Device Mode only\n    #define EP3_OUT_ODD     6                   // Used in USB Device Mode only\n    #define EP3_IN_EVEN     7                   // Used in USB Device Mode only\n    #define EP3_IN_ODD      7                   // Used in USB Device Mode only\n    #define EP4_OUT_EVEN    8                   // Used in USB Device Mode only\n    #define EP4_OUT_ODD     8                   // Used in USB Device Mode only\n    #define EP4_IN_EVEN     9                   // Used in USB Device Mode only\n    #define EP4_IN_ODD      9                   // Used in USB Device Mode only\n    #define EP5_OUT_EVEN    10                  // Used in USB Device Mode only\n    #define EP5_OUT_ODD     10                  // Used in USB Device Mode only\n    #define EP5_IN_EVEN     11                  // Used in USB Device Mode only\n    #define EP5_IN_ODD      11                  // Used in USB Device Mode only\n    #define EP6_OUT_EVEN    12                  // Used in USB Device Mode only\n    #define EP6_OUT_ODD     12                  // Used in USB Device Mode only\n    #define EP6_IN_EVEN     13                  // Used in USB Device Mode only\n    #define EP6_IN_ODD      13                  // Used in USB Device Mode only\n    #define EP7_OUT_EVEN    14                  // Used in USB Device Mode only\n    #define EP7_OUT_ODD     14                  // Used in USB Device Mode only\n    #define EP7_IN_EVEN     15                  // Used in USB Device Mode only\n    #define EP7_IN_ODD      15                  // Used in USB Device Mode only\n    #define EP8_OUT_EVEN    16                  // Used in USB Device Mode only\n    #define EP8_OUT_ODD     16                  // Used in USB Device Mode only\n    #define EP8_IN_EVEN     17                  // Used in USB Device Mode only\n    #define EP8_IN_ODD      17                  // Used in USB Device Mode only\n    #define EP9_OUT_EVEN    18                  // Used in USB Device Mode only\n    #define EP9_OUT_ODD     18                  // Used in USB Device Mode only\n    #define EP9_IN_EVEN     19                  // Used in USB Device Mode only\n    #define EP9_IN_ODD      19                  // Used in USB Device Mode only\n    #define EP10_OUT_EVEN   20                  // Used in USB Device Mode only\n    #define EP10_OUT_ODD    20                  // Used in USB Device Mode only\n    #define EP10_IN_EVEN    21                  // Used in USB Device Mode only\n    #define EP10_IN_ODD     21                  // Used in USB Device Mode only\n    #define EP11_OUT_EVEN   22                  // Used in USB Device Mode only\n    #define EP11_OUT_ODD    22                  // Used in USB Device Mode only\n    #define EP11_IN_EVEN    23                  // Used in USB Device Mode only\n    #define EP11_IN_ODD     23                  // Used in USB Device Mode only\n    #define EP12_OUT_EVEN   24                  // Used in USB Device Mode only\n    #define EP12_OUT_ODD    24                  // Used in USB Device Mode only\n    #define EP12_IN_EVEN    25                  // Used in USB Device Mode only\n    #define EP12_IN_ODD     25                  // Used in USB Device Mode only\n    #define EP13_OUT_EVEN   26                  // Used in USB Device Mode only\n    #define EP13_OUT_ODD    26                  // Used in USB Device Mode only\n    #define EP13_IN_EVEN    27                  // Used in USB Device Mode only\n    #define EP13_IN_ODD     27                  // Used in USB Device Mode only\n    #define EP14_OUT_EVEN   28                  // Used in USB Device Mode only\n    #define EP14_OUT_ODD    28                  // Used in USB Device Mode only\n    #define EP14_IN_EVEN    29                  // Used in USB Device Mode only\n    #define EP14_IN_ODD     29                  // Used in USB Device Mode only\n    #define EP15_OUT_EVEN   30                  // Used in USB Device Mode only\n    #define EP15_OUT_ODD    30                  // Used in USB Device Mode only\n    #define EP15_IN_EVEN    31                  // Used in USB Device Mode only\n    #define EP15_IN_ODD     31                  // Used in USB Device Mode only\n\n    #define EP(ep,dir,pp) (2*ep+dir)            // Used in USB Device Mode only\n\n    #define BD(ep,dir,pp)   ((8 * ep) + (4 * dir))      // Used in USB Device Mode only\n\n#elif (USB_PING_PONG_MODE == USB_PING_PONG__EP0_OUT_ONLY)\n    #define USB_NEXT_EP0_OUT_PING_PONG 0x0004\n    #define USB_NEXT_EP0_IN_PING_PONG 0x0000\n    #define USB_NEXT_PING_PONG 0x0000\n    #define EP0_OUT_EVEN    0\n    #define EP0_OUT_ODD     1\n    #define EP0_IN_EVEN     2\n    #define EP0_IN_ODD      2\n    #define EP1_OUT_EVEN    3\n    #define EP1_OUT_ODD     3\n    #define EP1_IN_EVEN     4\n    #define EP1_IN_ODD      4\n    #define EP2_OUT_EVEN    5\n    #define EP2_OUT_ODD     5\n    #define EP2_IN_EVEN     6\n    #define EP2_IN_ODD      6\n    #define EP3_OUT_EVEN    7\n    #define EP3_OUT_ODD     7\n    #define EP3_IN_EVEN     8\n    #define EP3_IN_ODD      8\n    #define EP4_OUT_EVEN    9\n    #define EP4_OUT_ODD     9\n    #define EP4_IN_EVEN     10\n    #define EP4_IN_ODD      10\n    #define EP5_OUT_EVEN    11\n    #define EP5_OUT_ODD     11\n    #define EP5_IN_EVEN     12\n    #define EP5_IN_ODD      12\n    #define EP6_OUT_EVEN    13\n    #define EP6_OUT_ODD     13\n    #define EP6_IN_EVEN     14\n    #define EP6_IN_ODD      14\n    #define EP7_OUT_EVEN    15\n    #define EP7_OUT_ODD     15\n    #define EP7_IN_EVEN     16\n    #define EP7_IN_ODD      16\n    #define EP8_OUT_EVEN    17\n    #define EP8_OUT_ODD     17\n    #define EP8_IN_EVEN     18\n    #define EP8_IN_ODD      18\n    #define EP9_OUT_EVEN    19\n    #define EP9_OUT_ODD     19\n    #define EP9_IN_EVEN     20\n    #define EP9_IN_ODD      20\n    #define EP10_OUT_EVEN   21\n    #define EP10_OUT_ODD    21\n    #define EP10_IN_EVEN    22\n    #define EP10_IN_ODD     22\n    #define EP11_OUT_EVEN   23\n    #define EP11_OUT_ODD    23\n    #define EP11_IN_EVEN    24\n    #define EP11_IN_ODD     24\n    #define EP12_OUT_EVEN   25\n    #define EP12_OUT_ODD    25\n    #define EP12_IN_EVEN    26\n    #define EP12_IN_ODD     26\n    #define EP13_OUT_EVEN   27\n    #define EP13_OUT_ODD    27\n    #define EP13_IN_EVEN    28\n    #define EP13_IN_ODD     28\n    #define EP14_OUT_EVEN   29\n    #define EP14_OUT_ODD    29\n    #define EP14_IN_EVEN    30\n    #define EP14_IN_ODD     30\n    #define EP15_OUT_EVEN   31\n    #define EP15_OUT_ODD    31\n    #define EP15_IN_EVEN    32\n    #define EP15_IN_ODD     32\n\n    #define EP(ep,dir,pp) (2*ep+dir+(((ep==0)&&(dir==0))?pp:2))\n    #define BD(ep,dir,pp) (4*(ep+dir+(((ep==0)&&(dir==0))?pp:2)))\n\n#elif (USB_PING_PONG_MODE == USB_PING_PONG__FULL_PING_PONG)\n    #define USB_NEXT_EP0_OUT_PING_PONG 0x0008\n    #define USB_NEXT_EP0_IN_PING_PONG 0x0008\n    #define USB_NEXT_PING_PONG 0x0008\n\n    #define EP0_OUT_EVEN    0\n    #define EP0_OUT_ODD     1\n    #define EP0_IN_EVEN     2\n    #define EP0_IN_ODD      3\n    #define EP1_OUT_EVEN    4\n    #define EP1_OUT_ODD     5\n    #define EP1_IN_EVEN     6\n    #define EP1_IN_ODD      7\n    #define EP2_OUT_EVEN    8\n    #define EP2_OUT_ODD     9\n    #define EP2_IN_EVEN     10\n    #define EP2_IN_ODD      11\n    #define EP3_OUT_EVEN    12\n    #define EP3_OUT_ODD     13\n    #define EP3_IN_EVEN     14\n    #define EP3_IN_ODD      15\n    #define EP4_OUT_EVEN    16\n    #define EP4_OUT_ODD     17\n    #define EP4_IN_EVEN     18\n    #define EP4_IN_ODD      19\n    #define EP5_OUT_EVEN    20\n    #define EP5_OUT_ODD     21\n    #define EP5_IN_EVEN     22\n    #define EP5_IN_ODD      23\n    #define EP6_OUT_EVEN    24\n    #define EP6_OUT_ODD     25\n    #define EP6_IN_EVEN     26\n    #define EP6_IN_ODD      27\n    #define EP7_OUT_EVEN    28\n    #define EP7_OUT_ODD     29\n    #define EP7_IN_EVEN     30\n    #define EP7_IN_ODD      31\n    #define EP8_OUT_EVEN    32\n    #define EP8_OUT_ODD     33\n    #define EP8_IN_EVEN     34\n    #define EP8_IN_ODD      35\n    #define EP9_OUT_EVEN    36\n    #define EP9_OUT_ODD     37\n    #define EP9_IN_EVEN     38\n    #define EP9_IN_ODD      39\n    #define EP10_OUT_EVEN   40\n    #define EP10_OUT_ODD    41\n    #define EP10_IN_EVEN    42\n    #define EP10_IN_ODD     43\n    #define EP11_OUT_EVEN   44\n    #define EP11_OUT_ODD    45\n    #define EP11_IN_EVEN    46\n    #define EP11_IN_ODD     47\n    #define EP12_OUT_EVEN   48\n    #define EP12_OUT_ODD    49\n    #define EP12_IN_EVEN    50\n    #define EP12_IN_ODD     51\n    #define EP13_OUT_EVEN   52\n    #define EP13_OUT_ODD    53\n    #define EP13_IN_EVEN    54\n    #define EP13_IN_ODD     55\n    #define EP14_OUT_EVEN   56\n    #define EP14_OUT_ODD    57\n    #define EP14_IN_EVEN    58\n    #define EP14_IN_ODD     59\n    #define EP15_OUT_EVEN   60\n    #define EP15_OUT_ODD    61\n    #define EP15_IN_EVEN    62\n    #define EP15_IN_ODD     63\n\n    #define EP(ep,dir,pp) (4*ep+2*dir+pp)\n\n    #define BD(ep,dir,pp) (8*(4*ep+2*dir+pp))\n\n#elif (USB_PING_PONG_MODE == USB_PING_PONG__ALL_BUT_EP0)\n    #define USB_NEXT_EP0_OUT_PING_PONG 0x0000\n    #define USB_NEXT_EP0_IN_PING_PONG 0x0000\n    #define USB_NEXT_PING_PONG 0x0004\n    #define EP0_OUT_EVEN    0\n    #define EP0_OUT_ODD     0\n    #define EP0_IN_EVEN     1\n    #define EP0_IN_ODD      1\n    #define EP1_OUT_EVEN    2\n    #define EP1_OUT_ODD     3\n    #define EP1_IN_EVEN     4\n    #define EP1_IN_ODD      5\n    #define EP2_OUT_EVEN    6\n    #define EP2_OUT_ODD     7\n    #define EP2_IN_EVEN     8\n    #define EP2_IN_ODD      9\n    #define EP3_OUT_EVEN    10\n    #define EP3_OUT_ODD     11\n    #define EP3_IN_EVEN     12\n    #define EP3_IN_ODD      13\n    #define EP4_OUT_EVEN    14\n    #define EP4_OUT_ODD     15\n    #define EP4_IN_EVEN     16\n    #define EP4_IN_ODD      17\n    #define EP5_OUT_EVEN    18\n    #define EP5_OUT_ODD     19\n    #define EP5_IN_EVEN     20\n    #define EP5_IN_ODD      21\n    #define EP6_OUT_EVEN    22\n    #define EP6_OUT_ODD     23\n    #define EP6_IN_EVEN     24\n    #define EP6_IN_ODD      25\n    #define EP7_OUT_EVEN    26\n    #define EP7_OUT_ODD     27\n    #define EP7_IN_EVEN     28\n    #define EP7_IN_ODD      29\n    #define EP8_OUT_EVEN    30\n    #define EP8_OUT_ODD     31\n    #define EP8_IN_EVEN     32\n    #define EP8_IN_ODD      33\n    #define EP9_OUT_EVEN    34\n    #define EP9_OUT_ODD     35\n    #define EP9_IN_EVEN     36\n    #define EP9_IN_ODD      37\n    #define EP10_OUT_EVEN   38\n    #define EP10_OUT_ODD    39\n    #define EP10_IN_EVEN    40\n    #define EP10_IN_ODD     41\n    #define EP11_OUT_EVEN   42\n    #define EP11_OUT_ODD    43\n    #define EP11_IN_EVEN    44\n    #define EP11_IN_ODD     45\n    #define EP12_OUT_EVEN   46\n    #define EP12_OUT_ODD    47\n    #define EP12_IN_EVEN    48\n    #define EP12_IN_ODD     49\n    #define EP13_OUT_EVEN   50\n    #define EP13_OUT_ODD    51\n    #define EP13_IN_EVEN    52\n    #define EP13_IN_ODD     53\n    #define EP14_OUT_EVEN   54\n    #define EP14_OUT_ODD    55\n    #define EP14_IN_EVEN    56\n    #define EP14_IN_ODD     57\n    #define EP15_OUT_EVEN   58\n    #define EP15_OUT_ODD    59\n    #define EP15_IN_EVEN    60\n    #define EP15_IN_ODD     61\n\n    #define EP(ep,dir,pp) (4*ep+2*dir+((ep==0)?0:(pp-2)))\n    #define BD(ep,dir,pp) (4*(4*ep+2*dir+((ep==0)?0:(pp-2))))\n\n#else\n    #error \"No ping pong mode defined.\"\n#endif\n\nextern int usb_remote_wakeup;\n\n#endif //USBD_H\n"
  },
  {
    "path": "sys/arch/pic32/hal/usb_function_cdc.c",
    "content": "/*\n * This file contains all of functions, macros, definitions, variables,\n * datatypes, etc. that are required for usage with the CDC function\n * driver. This file should be included in projects that use the CDC\n * \\function driver.\n *\n * The software supplied herewith by Microchip Technology Incorporated\n * (the 'Company') for its PIC(R) Microcontroller is intended and\n * supplied to you, the Company's customer, for use solely and\n * exclusively on Microchip PIC Microcontroller products. The\n * software is owned by the Company and/or its supplier, and is\n * protected under applicable copyright laws. All rights are reserved.\n * Any use in violation of the foregoing restrictions may subject the\n * user to criminal sanctions under applicable laws, as well as to\n * civil liability for the breach of the terms and conditions of this license.\n *\n * THIS SOFTWARE IS PROVIDED IN AN 'AS IS' CONDITION. NO WARRANTIES,\n * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED\n * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\n * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT,\n * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR\n * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n */\n#include <machine/pic32mx.h>\n#include <pic32/hal/usb_device.h>\n#include <pic32/hal/usb_function_cdc.h>\n\nunsigned cdc_trf_state;         // States are defined cdc.h\nunsigned cdc_tx_len;            // total tx length\n\nLINE_CODING cdc_line_coding;    // Buffer to store line coding information\n\nstatic USB_HANDLE data_out;\nstatic USB_HANDLE data_in;\n\nstatic CONTROL_SIGNAL_BITMAP control_signal_bitmap;\n\nstatic volatile unsigned char cdc_data_rx [CDC_DATA_OUT_EP_SIZE];\nstatic volatile unsigned char cdc_data_tx [CDC_DATA_IN_EP_SIZE];\n\n/*\n * SEND_ENCAPSULATED_COMMAND and GET_ENCAPSULATED_RESPONSE are required\n * requests according to the CDC specification.\n * However, it is not really being used here, therefore a dummy buffer is\n * used for conformance.\n */\n#define DUMMY_LENGTH    0x08\n\nstatic unsigned char dummy_encapsulated_cmd_response [DUMMY_LENGTH];\n\n/*\n * This routine checks the setup data packet to see if it\n * knows how to handle it.\n */\nvoid cdc_check_request()\n{\n    /*\n     * If request recipient is not an interface then return\n     */\n    if (usb_setup_pkt.Recipient != RCPT_INTF)\n        return;\n\n    /*\n     * If request type is not class-specific then return\n     */\n    if (usb_setup_pkt.RequestType != CLASS)\n        return;\n\n    /*\n     * Interface ID must match interface numbers associated with\n     * CDC class, else return\n     */\n    if (usb_setup_pkt.bIntfID != CDC_COMM_INTF_ID &&\n        usb_setup_pkt.bIntfID != CDC_DATA_INTF_ID)\n        return;\n\n    switch (usb_setup_pkt.bRequest)\n    {\n    case SEND_ENCAPSULATED_COMMAND:\n        // send the packet\n        usb_in_pipe[0].pSrc.bRam = (unsigned char*) &dummy_encapsulated_cmd_response;\n        usb_in_pipe[0].wCount = DUMMY_LENGTH;\n        usb_in_pipe[0].info.bits.ctrl_trf_mem = USB_INPIPES_RAM;\n        usb_in_pipe[0].info.bits.busy = 1;\n        break;\n\n    case GET_ENCAPSULATED_RESPONSE:\n        // Populate dummy_encapsulated_cmd_response first.\n        usb_in_pipe[0].pSrc.bRam = (unsigned char*) &dummy_encapsulated_cmd_response;\n        usb_in_pipe[0].info.bits.busy = 1;\n        break;\n\n    case SET_LINE_CODING:\n        usb_out_pipe[0].wCount = usb_setup_pkt.wLength;\n        usb_out_pipe[0].pDst.bRam = (unsigned char*) &cdc_line_coding._byte[0];\n        usb_out_pipe[0].pFunc = 0;\n        usb_out_pipe[0].info.bits.busy = 1;\n        break;\n\n    case GET_LINE_CODING:\n        usb_ep0_send_ram_ptr ((unsigned char*) &cdc_line_coding,\n            LINE_CODING_LENGTH, USB_EP0_INCLUDE_ZERO);\n        break;\n\n    case SET_CONTROL_LINE_STATE:\n        control_signal_bitmap._byte = (unsigned char)usb_setup_pkt.W_Value;\n        CONFIGURE_RTS(control_signal_bitmap.CARRIER_CONTROL);\n        CONFIGURE_DTR(control_signal_bitmap.DTE_PRESENT);\n        usb_in_pipe[0].info.bits.busy = 1;\n        break;\n    }\n}\n\n/*\n * This function initializes the CDC function driver. This function sets\n * the default line coding (baud rate, bit parity, number of data bits,\n * and format). This function also enables the endpoints and prepares for\n * the first transfer from the host.\n *\n * This function should be called after the SET_CONFIGURATION command.\n * This is most simply done by calling this function from the\n * usbcb_init_ep() function.\n *\n * Usage:\n *     void usbcb_init_ep()\n *     {\n *         cdc_init_ep();\n *     }\n */\nvoid cdc_init_ep()\n{\n    // Abstract line coding information\n    cdc_line_coding.dwDTERate = 115200; // baud rate\n    cdc_line_coding.bCharFormat = 0;    // 1 stop bit\n    cdc_line_coding.bParityType = 0;    // None\n    cdc_line_coding.bDataBits = 8;      // 5,6,7,8, or 16\n\n    cdc_trf_state = CDC_TX_READY;\n    cdc_tx_len = 0;\n\n    /*\n     * Do not have to init Cnt of IN pipes here.\n     * Reason:  Number of BYTEs to send to the host\n     *          varies from one transaction to\n     *          another. Cnt should equal the exact\n     *          number of BYTEs to transmit for\n     *          a given IN transaction.\n     *          This number of BYTEs will only\n     *          be known right before the data is\n     *          sent.\n     */\n    usb_enable_endpoint (CDC_COMM_EP, USB_IN_ENABLED |\n        USB_HANDSHAKE_ENABLED | USB_DISALLOW_SETUP);\n    usb_enable_endpoint (CDC_DATA_EP, USB_IN_ENABLED | USB_OUT_ENABLED |\n        USB_HANDSHAKE_ENABLED | USB_DISALLOW_SETUP);\n\n    data_out = usb_rx_one_packet (CDC_DATA_EP,\n        (unsigned char*) &cdc_data_rx, sizeof(cdc_data_rx));\n    data_in = 0;\n}\n\n/*\n * Get received data.\n */\nint cdc_consume (void (*func) (int))\n{\n    unsigned len;\n\n    if (! data_out || usb_handle_busy (data_out))\n        return 0;\n\n    /*\n     * Pass received data to user function.\n     */\n    len = usb_handle_get_length (data_out);\n    if (func != 0) {\n        unsigned n;\n        for (n=0; n<len; n++)\n            func (cdc_data_rx[n]);\n    }\n\n    /*\n     * Prepare dual-ram buffer for next OUT transaction\n     */\n    data_out = usb_rx_one_packet (CDC_DATA_EP,\n            (unsigned char*) &cdc_data_rx, sizeof(cdc_data_rx));\n    return len;\n}\n\n/*\n * Send a symbol to the USB.\n * Return a number of free bytes in transmit buffer.\n *\n * Usage:\n *      if (cdc_is_tx_ready()) {\n *          do {\n *              space = cdc_putc (data[i++]);\n *          } while (space > 0);\n *      }\n * Conditions:\n *   cdc_is_tx_ready() must return TRUE. This indicates that the last\n *   transfer is complete and is ready to receive a new block of data.\n */\nint cdc_putc (int c)\n{\n    if (cdc_trf_state != CDC_TX_READY || cdc_tx_len >= sizeof(cdc_data_tx))\n        return 0;\n\n    cdc_data_tx [cdc_tx_len++] = c;\n    return sizeof(cdc_data_tx) - cdc_tx_len;\n}\n\n/*\n * cdc_tx_service handles device-to-host transaction(s). This function\n * should be called once per Main Program loop after the device reaches\n * the configured state.\n *\n * Usage:\n *   void main()\n *   {\n *       usb_device_init();\n *       while (1)\n *       {\n *           usb_device_tasks();\n *           if (USBGetDeviceState() < CONFIGURED_STATE || USBIsDeviceSuspended())\n *           {\n *               // Either the device is not configured or we are suspended\n *               // so we don't want to do execute any application code\n *               continue;   // go back to the top of the while loop\n *           } else {\n *               // Keep trying to send data to the PC as required\n *               cdc_tx_service();\n *\n *               // Run application code.\n *               UserApplication();\n *           }\n *       }\n *   }\n */\nvoid cdc_tx_service()\n{\n    // Check that USB connection is established.\n    if (usb_device_state < CONFIGURED_STATE ||\n        (U1PWRC & PIC32_U1PWRC_USUSPEND))\n        return;\n\n    if (usb_handle_busy(data_in))\n        return;\n    /*\n     * Completing stage is necessary while [ mCDCUSartTxIsBusy()==1 ].\n     * By having this stage, user can always check cdc_trf_state,\n     * and not having to call mCDCUsartTxIsBusy() directly.\n     */\n    if (cdc_trf_state == CDC_TX_COMPLETING) {\n        cdc_trf_state = CDC_TX_READY;\n        cdc_tx_len = 0;\n    }\n\n    /*\n     * If CDC_TX_BUSY_ZLP state, send zero length packet\n     */\n    if (cdc_trf_state == CDC_TX_BUSY_ZLP)\n    {\n        data_in = usb_tx_one_packet (CDC_DATA_EP, 0, 0);\n        cdc_trf_state = CDC_TX_COMPLETING;\n        return;\n    }\n\n    /*\n     * Send a next packet.\n     */\n    if (cdc_trf_state == CDC_TX_READY && cdc_tx_len > 0) {\n        /*\n         * Determine if a zero length packet state is necessary.\n         * See explanation in USB Specification 2.0: Section 5.8.3\n         */\n        if (cdc_tx_len == CDC_DATA_IN_EP_SIZE)\n            cdc_trf_state = CDC_TX_BUSY_ZLP;\n        else\n            cdc_trf_state = CDC_TX_COMPLETING;\n\n        data_in = usb_tx_one_packet (CDC_DATA_EP, (unsigned char*)&cdc_data_tx, cdc_tx_len);\n    }\n}\n"
  },
  {
    "path": "sys/arch/pic32/hal/usb_function_cdc.h",
    "content": "/*\n * USB CDC Function Driver File\n *\n * This file contains all of functions, macros, definitions, variables,\n * datatypes, etc. that are required for usage with the CDC function\n * driver. This file should be included in projects that use the CDC\n * \\function driver.  This file should also be included into the\n * usb_descriptors.c file and any other user file that requires access to the\n * CDC interface.\n *\n * The software supplied herewith by Microchip Technology Incorporated\n * (the 'Company') for its PIC(R) Microcontroller is intended and\n * supplied to you, the Company's customer, for use solely and\n * exclusively on Microchip PIC Microcontroller products. The\n * software is owned by the Company and/or its supplier, and is\n * protected under applicable copyright laws. All rights are reserved.\n * Any use in violation of the foregoing restrictions may subject the\n * user to criminal sanctions under applicable laws, as well as to\n * civil liability for the breach of the terms and conditions of this license.\n *\n * THIS SOFTWARE IS PROVIDED IN AN 'AS IS' CONDITION. NO WARRANTIES,\n * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED\n * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\n * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT,\n * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR\n * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n */\n#ifndef CDC_H\n#define CDC_H\n\n/*\n * Default CDC configuration.\n */\n#ifndef CDC_COMM_INTF_ID\n#   define CDC_COMM_INTF_ID     0x0\n#endif\n#ifndef CDC_COMM_EP\n#   define CDC_COMM_EP          2\n#endif\n#ifndef CDC_COMM_IN_EP_SIZE\n#   define CDC_COMM_IN_EP_SIZE  8\n#endif\n#ifndef CDC_DATA_INTF_ID\n#   define CDC_DATA_INTF_ID     0x01\n#endif\n#ifndef CDC_DATA_EP\n#   define CDC_DATA_EP          3\n#endif\n#ifndef CDC_DATA_OUT_EP_SIZE\n#   define CDC_DATA_OUT_EP_SIZE 64\n#endif\n#ifndef CDC_DATA_IN_EP_SIZE\n#   define CDC_DATA_IN_EP_SIZE  64\n#endif\n\n/* Class-Specific Requests */\n#define SEND_ENCAPSULATED_COMMAND   0x00\n#define GET_ENCAPSULATED_RESPONSE   0x01\n#define SET_COMM_FEATURE            0x02\n#define GET_COMM_FEATURE            0x03\n#define CLEAR_COMM_FEATURE          0x04\n#define SET_LINE_CODING             0x20\n#define GET_LINE_CODING             0x21\n#define SET_CONTROL_LINE_STATE      0x22\n#define SEND_BREAK                  0x23\n\n/* Notifications *\n * Note: Notifications are polled over\n * Communication Interface (Interrupt Endpoint)\n */\n#define NETWORK_CONNECTION          0x00\n#define RESPONSE_AVAILABLE          0x01\n#define SERIAL_STATE                0x20\n\n\n/* Device Class Code */\n#define CDC_DEVICE                  0x02\n\n/* Communication Interface Class Code */\n#define COMM_INTF                   0x02\n\n/* Communication Interface Class SubClass Codes */\n#define ABSTRACT_CONTROL_MODEL      0x02\n\n/* Communication Interface Class Control Protocol Codes */\n#define V25TER                      0x01    // Common AT commands (\"Hayes(TM)\")\n\n\n/* Data Interface Class Codes */\n#define DATA_INTF                   0x0A\n\n/* Data Interface Class Protocol Codes */\n#define NO_PROTOCOL                 0x00    // No class specific protocol required\n\n/* Communication Feature Selector Codes */\n#define ABSTRACT_STATE              0x01\n#define COUNTRY_SETTING             0x02\n\n/* Functional Descriptors */\n/* Type Values for the bDscType Field */\n#define CS_INTERFACE                0x24\n#define CS_ENDPOINT                 0x25\n\n/* bDscSubType in Functional Descriptors */\n#define DSC_FN_HEADER               0x00\n#define DSC_FN_CALL_MGT             0x01\n#define DSC_FN_ACM                  0x02    // ACM - Abstract Control Management\n#define DSC_FN_DLM                  0x03    // DLM - Direct Line Managment\n#define DSC_FN_TELEPHONE_RINGER     0x04\n#define DSC_FN_RPT_CAPABILITIES     0x05\n#define DSC_FN_UNION                0x06\n#define DSC_FN_COUNTRY_SELECTION    0x07\n#define DSC_FN_TEL_OP_MODES         0x08\n#define DSC_FN_USB_TERMINAL         0x09\n/* more.... see Table 25 in USB CDC Specification 1.1 */\n\n/* CDC Bulk IN transfer states */\n#define CDC_TX_READY                0\n#define CDC_TX_BUSY_ZLP             2       // ZLP: Zero Length Packet\n#define CDC_TX_COMPLETING           3\n\n#if defined(USB_CDC_SUPPORT_HARDWARE_FLOW_CONTROL)\n    #define CONFIGURE_RTS(a) UART_RTS = a;\n    #define CONFIGURE_DTR(a) UART_DTR = a;\n#else\n    #define CONFIGURE_RTS(a)\n    #define CONFIGURE_DTR(a)\n#endif\n\n#define USB_CDC_ACM_FN_DSC_VAL      0x02\n\n/*\n * Function:\n *     void cdc_set_baud_rate(unsigned int baudRate)\n *\n * Summary:\n *     This macro is used set the baud rate reported back to the host during\n *     a get line coding request. (optional)\n *\n * Description:\n *     This macro is used set the baud rate reported back to the host during\n *     a get line coding request.\n *\n *     Typical Usage:\n *     <code>\n *         cdc_set_baud_rate(19200);\n *     </code>\n *\n *     This function is optional for CDC devices that do not actually convert\n *     the USB traffic to a hardware UART.\n *\n * Parameters:\n *     unsigned int baudRate - The desired baudrate\n */\n#define cdc_set_baud_rate(baudRate) { cdc_line_coding.dwDTERate = baudRate; }\n\n/*\n * Function:\n *     void cdc_set_character_format (unsigned charFormat)\n *\n * Summary:\n *     This macro is used manually set the character format reported back to\n *     the host during a get line coding request. (optional)\n *\n * Description:\n *     This macro is used manually set the character format reported back to\n *     the host during a get line coding request.\n *\n *     Typical Usage:\n *     <code>\n *         cdc_set_character_format(NUM_STOP_BITS_1);\n *     </code>\n *\n *     This function is optional for CDC devices that do not actually convert\n *     the USB traffic to a hardware UART.\n *\n * Parameters:\n *     unsigned charFormat - number of stop bits.  Available options are:\n *      * NUM_STOP_BITS_1 - 1 Stop bit\n *      * NUM_STOP_BITS_1_5 - 1.5 Stop bits\n *      * NUM_STOP_BITS_2 - 2 Stop bits\n */\n#define cdc_set_character_format(charFormat) { cdc_line_coding.bCharFormat = charFormat; }\n#define NUM_STOP_BITS_1     0   // 1 stop bit\n#define NUM_STOP_BITS_1_5   1   // 1.5 stop bit\n#define NUM_STOP_BITS_2     2   // 2 stop bit\n\n/*\n * Function:\n *     void cdc_set_parity (unsigned parityType)\n *\n * Summary:\n *     This function is used manually set the parity format reported back to\n *     the host during a get line coding request. (optional)\n *\n * Description:\n *     This macro is used manually set the parity format reported back to\n *     the host during a get line coding request.\n *\n *     Typical Usage:\n *     <code>\n *         cdc_set_parity(PARITY_NONE);\n *     </code>\n *\n *     This function is optional for CDC devices that do not actually convert\n *     the USB traffic to a hardware UART.\n *\n * Parameters:\n *     unsigned parityType - Type of parity.  The options are the following:\n *         * PARITY_NONE\n *         * PARITY_ODD\n *         * PARITY_EVEN\n *         * PARITY_MARK\n *         * PARITY_SPACE\n */\n#define cdc_set_parity(parityType) { cdc_line_coding.bParityType = parityType; }\n#define PARITY_NONE     0   // no parity\n#define PARITY_ODD      1   // odd parity\n#define PARITY_EVEN     2   // even parity\n#define PARITY_MARK     3   // mark parity\n#define PARITY_SPACE    4   // space parity\n\n/*\n * Function:\n *     void cdc_set_data_size (unsigned dataBits)\n *\n * Summary:\n *     This function is used manually set the number of data bits reported back\n *     to the host during a get line coding request. (optional)\n *\n * Description:\n *     This function is used manually set the number of data bits reported back\n *     to the host during a get line coding request.\n *\n *     Typical Usage:\n *     <code>\n *         cdc_set_data_size(8);\n *     </code>\n *\n *     This function is optional for CDC devices that do not actually convert\n *     the USB traffic to a hardware UART.\n *\n * Parameters:\n *     unsigned dataBits - number of data bits.  The options are 5, 6, 7, 8, or 16.\n */\n#define cdc_set_data_size(dataBits) { cdc_line_coding.bDataBits = dataBits; }\n\n/*\n * Function:\n *     void cdc_set_line_coding(unsigned int baud, unsigned format, unsigned parity, unsigned dataSize)\n *\n * Summary:\n *     This function is used to manually set the data reported back\n *     to the host during a get line coding request. (optional)\n *\n * Description:\n *     This function is used to manually set the data reported back\n *     to the host during a get line coding request.\n *\n *     Typical Usage:\n *     <code>\n *         cdc_set_line_coding(19200, NUM_STOP_BITS_1, PARITY_NONE, 8);\n *     </code>\n *\n *     This function is optional for CDC devices that do not actually convert\n *     the USB traffic to a hardware UART.\n *\n * Parameters:\n *     unsigned baud - The desired baudrate\n *     unsigned format - number of stop bits.  Available options are:\n *      * NUM_STOP_BITS_1 - 1 Stop bit\n *      * NUM_STOP_BITS_1_5 - 1.5 Stop bits\n *      * NUM_STOP_BITS_2 - 2 Stop bits\n *     unsigned parity - Type of parity.  The options are the following:\n *         * PARITY_NONE\n *         * PARITY_ODD\n *         * PARITY_EVEN\n *         * PARITY_MARK\n *         * PARITY_SPACE\n *     unsigned dataSize - number of data bits.  The options are 5, 6, 7, 8, or 16.\n */\n#define cdc_set_line_coding(baud, format, parity, dataSize) {\\\n            cdc_set_baud_rate(baud);\\\n            cdc_set_character_format(format);\\\n            cdc_set_parity(parity);\\\n            cdc_set_data_size(dataSize);\\\n        }\n\n/*\n * Function:\n *     bool_t cdc_is_tx_ready(void)\n *\n * Summary:\n *     This macro is used to check if the CDC class is ready\n *     to send more data.\n *\n * Description:\n *     This macro is used to check if the CDC class is ready\n *     to send more data.\n *\n *     Typical Usage:\n *     <code>\n *         if (cdc_is_tx_ready())\n *         {\n *             cdc_putrs (\"Hello World\");\n *         }\n *     </code>\n */\n#define cdc_is_tx_ready()   (cdc_trf_state == CDC_TX_READY)\n\n/*\n * S T R U C T U R E S\n */\n\n/* Line Coding Structure */\n#define LINE_CODING_LENGTH          0x07\n\ntypedef union _LINE_CODING\n{\n    struct\n    {\n        unsigned char _byte[LINE_CODING_LENGTH];\n    };\n    struct\n    {\n        unsigned long dwDTERate;          // Complex data structure\n        unsigned char bCharFormat;\n        unsigned char bParityType;\n        unsigned char bDataBits;\n    };\n} LINE_CODING;\n\ntypedef union _CONTROL_SIGNAL_BITMAP\n{\n    unsigned char _byte;\n    struct\n    {\n        unsigned DTE_PRESENT:1;       // [0] Not Present  [1] Present\n        unsigned CARRIER_CONTROL:1;   // [0] Deactivate   [1] Activate\n    };\n} CONTROL_SIGNAL_BITMAP;\n\n\n/* Functional Descriptor Structure - See CDC Specification 1.1 for details */\n\n/* Header Functional Descriptor */\ntypedef struct __attribute__((packed)) _USB_CDC_HEADER_FN_DSC\n{\n    unsigned char bFNLength;\n    unsigned char bDscType;\n    unsigned char bDscSubType;\n    unsigned short bcdCDC;\n} USB_CDC_HEADER_FN_DSC;\n\n/* Abstract Control Management Functional Descriptor */\ntypedef struct __attribute__((packed)) _USB_CDC_ACM_FN_DSC\n{\n    unsigned char bFNLength;\n    unsigned char bDscType;\n    unsigned char bDscSubType;\n    unsigned char bmCapabilities;\n} USB_CDC_ACM_FN_DSC;\n\n/* Union Functional Descriptor */\ntypedef struct __attribute__((packed)) _USB_CDC_UNION_FN_DSC\n{\n    unsigned char bFNLength;\n    unsigned char bDscType;\n    unsigned char bDscSubType;\n    unsigned char bMasterIntf;\n    unsigned char bSaveIntf0;\n} USB_CDC_UNION_FN_DSC;\n\n/* Call Management Functional Descriptor */\ntypedef struct __attribute__((packed)) _USB_CDC_CALL_MGT_FN_DSC\n{\n    unsigned char bFNLength;\n    unsigned char bDscType;\n    unsigned char bDscSubType;\n    unsigned char bmCapabilities;\n    unsigned char bDataInterface;\n} USB_CDC_CALL_MGT_FN_DSC;\n\ntypedef union __attribute__((packed)) _CDC_NOTICE\n{\n    LINE_CODING GetLineCoding;\n    LINE_CODING SetLineCoding;\n    unsigned char packet[CDC_COMM_IN_EP_SIZE];\n} CDC_NOTICE, *PCDC_NOTICE;\n\n/*\n * E X T E R N S\n */\nextern unsigned cdc_rx_len;\nextern unsigned cdc_tx_len;\nextern unsigned cdc_trf_state;\n\nextern LINE_CODING cdc_line_coding;\n\n/*\n * Public Prototypes\n */\nvoid cdc_check_request (void);\nvoid cdc_init_ep (void);\nvoid cdc_tx_service (void);\nint cdc_putc (int c);\nint cdc_consume (void (*func) (int));\n\n#endif //CDC_H\n"
  },
  {
    "path": "sys/arch/pic32/hal/usb_function_hid.c",
    "content": "/*\n * USB HID Function Driver File\n *\n * This file contains all of functions, macros, definitions, variables,\n * datatypes, etc. that are required for usage with the HID function\n * driver. This file should be included in projects that use the HID\n * function driver.\n *\n * The software supplied herewith by Microchip Technology Incorporated\n * (the 'Company') for its PIC(R) Microcontroller is intended and\n * supplied to you, the Company's customer, for use solely and\n * exclusively on Microchip PIC Microcontroller products. The\n * software is owned by the Company and/or its supplier, and is\n * protected under applicable copyright laws. All rights are reserved.\n * Any use in violation of the foregoing restrictions may subject the\n * user to criminal sanctions under applicable laws, as well as to\n * civil liability for the breach of the terms and conditions of this license.\n *\n * THIS SOFTWARE IS PROVIDED IN AN 'AS IS' CONDITION. NO WARRANTIES,\n * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED\n * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\n * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT,\n * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR\n * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n */\n#include <pic32/hal/usb_device.h>\n#include <pic32/hal/usb_function_hid.h>\n\nunsigned char hid_idle_rate;\nunsigned char hid_active_protocol;  // [0] Boot Protocol [1] Report Protocol\n\n/*\n * Section C: non-EP0 Buffer Space\n */\nvolatile unsigned char hid_report_out[HID_INT_OUT_EP_SIZE];\nvolatile unsigned char hid_report_in[HID_INT_IN_EP_SIZE];\nvolatile unsigned char hid_report_feature [HID_FEATURE_REPORT_BYTES];\n\n/*\n * Check to see if the HID supports a specific Output or Feature report.\n *\n * Return: 1 if it's a supported Input report\n *         2 if it's a supported Output report\n *         3 if it's a supported Feature report\n *         0 for all other cases\n */\nstatic unsigned char report_supported (void)\n{\n    // Find out if an Output or Feature report has arrived on the control pipe.\n    usb_device_tasks();\n\n    switch (usb_setup_pkt.W_Value >> 8) {\n    case 0x01:                  // Input report\n        switch (usb_setup_pkt.W_Value & 0xff) {\n        case 0x00: return 1;    // Report ID 0\n        default:   return 0;    // Other report IDs not supported.\n        }\n    case 0x02:          // Output report\n        switch (usb_setup_pkt.W_Value & 0xff) {\n        case 0x00: return 2;    // Report ID 0\n        default:   return 0;    // Other report IDs not supported.\n        }\n    case 0x03:                  // Feature report\n        switch (usb_setup_pkt.W_Value & 0xff) {\n        case 0x00: return 3;    // Report ID 0\n        default:   return 0;    // Other report IDs not supported.\n        }\n    default:\n        return 0;\n    }\n}\n\n/*\n * Check to see if an Output or Feature report has arrived\n * on the control pipe. If yes, extract and use the data.\n */\nstatic void report_handler (void)\n{\n    unsigned char count = 0;\n\n    // Find out if an Output or Feature report has arrived on the control pipe.\n    // Get the report type from the Setup packet.\n\n    switch (usb_setup_pkt.W_Value >> 8) {\n    case 0x02:                  // Output report\n        switch (usb_setup_pkt.W_Value & 0xff) {\n        case 0:                 // Report ID 0\n            // This example application copies the Output report data\n            // to hid_report_in.\n            // (Assumes Input and Output reports are the same length.)\n            // A \"real\" application would do something more useful with the data.\n            // wCount holds the number of bytes read in the Data stage.\n            // This example assumes the report fits in one transaction.\n\n            for (count=0; count <= HID_OUTPUT_REPORT_BYTES - 1; count++) {\n                hid_report_in[count] = hid_report_out[count];\n            }\n            break;\n        }\n        break;\n\n    case 0x03:                  // Feature report\n        // Get the report ID from the Setup packet.\n        switch (usb_setup_pkt.W_Value & 0xff) {\n        case 0:                 // Report ID 0\n            // The Feature report data is in hid_report_feature.\n            // This example application just sends the data back in the next\n            // Get_Report request for a Feature report.\n            // wCount holds the number of bytes read in the Data stage.\n            // This example assumes the report fits in one transaction.\n            // The Feature report uses a single buffer so to send the same data back\n            // in the next IN Feature report, there is nothing to copy.\n            // The data is in hid_report_feature[HID_FEATURE_REPORT_BYTES]\n            break;\n        }\n        break;\n    }\n}\n\n/*\n * This routine handles HID specific request that happen on EP0.  These\n * include, but are not limited to, requests for the HID report\n * descriptors.  This function should be called from the\n * USBCBCheckOtherReq() call back function whenever using an HID device.\n *\n * Typical Usage:\n *      void USBCBCheckOtherReq(void)\n *      {\n *          // Since the stack didn't handle the request I need\n *          // to check my class drivers to see if it is for them\n *          hid_check_request();\n *      }\n */\nvoid hid_check_request (void)\n{\n    if (usb_setup_pkt.Recipient != RCPT_INTF)\n        return;\n    if (usb_setup_pkt.bIntfID != HID_INTF_ID)\n        return;\n\n    /*\n     * There are two standard requests that hid.c may support.\n     * 1. GET_DSC(DSC_HID,DSC_RPT,DSC_PHY);\n     * 2. SET_DSC(DSC_HID,DSC_RPT,DSC_PHY);\n     */\n    if (usb_setup_pkt.bRequest == GET_DSC) {\n        switch (usb_setup_pkt.bDescriptorType) {\n        case DSC_HID:\n            if (usb_active_configuration == 1) {\n                usb_ep0_send_rom_ptr ((const unsigned char*)\n                    &usb_config1_descriptor + 18,\n                    sizeof(USB_HID_DSC)+3,\n                    USB_EP0_INCLUDE_ZERO);\n            }\n            break;\n        case DSC_RPT:\n            if (usb_active_configuration == 1) {\n                usb_ep0_send_rom_ptr ((const unsigned char*)\n                    &hid_rpt01[0],\n                    HID_RPT01_SIZE,     // See target.cfg\n                    USB_EP0_INCLUDE_ZERO);\n            }\n            break;\n        case DSC_PHY:\n            usb_ep0_transmit (USB_EP0_NO_DATA);\n            break;\n        }\n    }\n\n    if (usb_setup_pkt.RequestType != CLASS)\n        return;\n\n    switch (usb_setup_pkt.bRequest) {\n    case GET_REPORT:\n        switch (report_supported()) {\n        case 1:                 // Input Report\n            usb_in_pipe[0].pSrc.bRam = (unsigned char*) &hid_report_in[0];\n            usb_in_pipe[0].info.bits.ctrl_trf_mem = _RAM;       // Set memory type\n            usb_in_pipe[0].wCount = HID_INPUT_REPORT_BYTES;     // Set data count\n            usb_in_pipe[0].info.bits.busy = 1;\n            break;\n        case 3:                 // Feature Report\n            usb_in_pipe[0].pSrc.bRam = (unsigned char*) &hid_report_feature[0];\n            usb_in_pipe[0].info.bits.ctrl_trf_mem = _RAM;       // Set memory type\n            usb_in_pipe[0].wCount = HID_FEATURE_REPORT_BYTES;   // Set data count\n            usb_in_pipe[0].info.bits.busy = 1;\n            break;\n        }\n        break;\n    case SET_REPORT:\n        switch (report_supported()) {\n        case 2:                 // Output Report\n            usb_out_pipe[0].wCount = usb_setup_pkt.wLength;\n            usb_out_pipe[0].pFunc = report_handler;\n            usb_out_pipe[0].pDst.bRam = (unsigned char*) &hid_report_out[0];\n            usb_out_pipe[0].info.bits.busy = 1;\n            break;\n        case 3:                 // Feature Report\n            usb_out_pipe[0].wCount = usb_setup_pkt.wLength;\n            usb_out_pipe[0].pFunc = report_handler;\n            usb_out_pipe[0].pDst.bRam = (unsigned char*) &hid_report_feature[0];\n            usb_out_pipe[0].info.bits.busy = 1;\n            break;\n        }\n        break;\n    case GET_IDLE:\n        usb_ep0_send_ram_ptr (&hid_idle_rate, 1, USB_EP0_INCLUDE_ZERO);\n        break;\n    case SET_IDLE:\n        usb_ep0_transmit (USB_EP0_NO_DATA);\n        hid_idle_rate = usb_setup_pkt.W_Value >> 8;\n        break;\n    case GET_PROTOCOL:\n        usb_ep0_send_ram_ptr (&hid_active_protocol, 1, USB_EP0_NO_OPTIONS);\n        break;\n    case SET_PROTOCOL:\n        usb_ep0_transmit (USB_EP0_NO_DATA);\n        hid_active_protocol = usb_setup_pkt.W_Value & 0xff;\n        break;\n    }\n}\n"
  },
  {
    "path": "sys/arch/pic32/hal/usb_function_hid.h",
    "content": "/*\n * USB HID Function Driver File\n *\n * This file contains all of functions, macros, definitions, variables,\n * datatypes, etc. that are required for usage with the HID function\n * driver. This file should be included in projects that use the HID\n * function driver.  This file should also be included into the\n * usb_descriptors.c file and any other user file that requires access to the\n * HID interface.\n *\n * The software supplied herewith by Microchip Technology Incorporated\n * (the 'Company') for its PIC(R) Microcontroller is intended and\n * supplied to you, the Company's customer, for use solely and\n * exclusively on Microchip PIC Microcontroller products. The\n * software is owned by the Company and/or its supplier, and is\n * protected under applicable copyright laws. All rights are reserved.\n * Any use in violation of the foregoing restrictions may subject the\n * user to criminal sanctions under applicable laws, as well as to\n * civil liability for the breach of the terms and conditions of this license.\n *\n * THIS SOFTWARE IS PROVIDED IN AN 'AS IS' CONDITION. NO WARRANTIES,\n * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED\n * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\n * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT,\n * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR\n * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n */\n#ifndef HID_H\n#define HID_H\n\n/*\n * Default HID configuration.\n */\n#ifndef HID_EP\n#   define HID_EP               1\n#endif\n#ifndef HID_INTF_ID\n#   define HID_INTF_ID          0x00\n#endif\n#ifndef HID_BD_OUT\n#   define HID_BD_OUT           USB_EP_1_OUT\n#endif\n#ifndef HID_INT_OUT_EP_SIZE\n#   define HID_INT_OUT_EP_SIZE  3\n#endif\n#ifndef HID_BD_IN\n#   define HID_BD_IN            USB_EP_1_IN\n#endif\n#ifndef HID_INT_IN_EP_SIZE\n#   define HID_INT_IN_EP_SIZE   3\n#endif\n#ifndef HID_NUM_OF_DSC\n#   define HID_NUM_OF_DSC       1\n#endif\n#ifndef HID_RPT01_SIZE\n#   define HID_RPT01_SIZE       47\n#endif\n\n/* Class-Specific Requests */\n#define GET_REPORT              0x01\n#define GET_IDLE                0x02\n#define GET_PROTOCOL            0x03\n#define SET_REPORT              0x09\n#define SET_IDLE                0x0A\n#define SET_PROTOCOL            0x0B\n\n/* Class Descriptor Types */\n#define DSC_HID                 0x21\n#define DSC_RPT                 0x22\n#define DSC_PHY                 0x23\n\n/* Protocol Selection */\n#define BOOT_PROTOCOL           0x00\n#define RPT_PROTOCOL            0x01\n\n/* HID Interface Class Code */\n#define HID_INTF                0x03\n\n/* HID Interface Class SubClass Codes */\n#define BOOT_INTF_SUBCLASS      0x01\n\n/* HID Interface Class Protocol Codes */\n#define HID_PROTOCOL_NONE       0x00\n#define HID_PROTOCOL_KEYBOARD   0x01\n#define HID_PROTOCOL_MOUSE      0x02\n\nextern const unsigned char hid_rpt01 [HID_RPT01_SIZE];\nextern volatile unsigned char hid_report_out[HID_INT_OUT_EP_SIZE];\nextern volatile unsigned char hid_report_in[HID_INT_IN_EP_SIZE];\nextern volatile unsigned char hid_report_feature[HID_FEATURE_REPORT_BYTES];\n\n//\n// USB HID Descriptor header as detailed in section\n// \"6.2.1 HID Descriptor\" of the HID class definition specification\n//\ntypedef struct _USB_HID_DSC_HEADER\n{\n    unsigned char bDescriptorType;      // offset 9\n    unsigned short wDscLength;          // offset 10\n\n} USB_HID_DSC_HEADER;\n\n//\n// USB HID Descriptor header as detailed in section\n// \"6.2.1 HID Descriptor\" of the HID class definition specification\n//\ntypedef struct _USB_HID_DSC\n{\n    unsigned char bLength;              // offset 0\n    unsigned char bDescriptorType;      // offset 1\n    unsigned short bcdHID;              // offset 2\n    unsigned char bCountryCode;         // offset 4\n    unsigned char bNumDsc;              // offset 5\n\n} USB_HID_DSC;\n\nvoid hid_check_request(void);\n\n#endif // HID_H\n"
  },
  {
    "path": "sys/arch/pic32/hal/usb_hal_pic32.h",
    "content": "/*\n * USB Hardware Abstraction Layer (HAL)  (Header File)\n *\n * This file abstracts the hardware interface.  The USB stack firmware can be\n * compiled to work on different USB microcontrollers, such as PIC18 and PIC24.\n * The USB related special function registers and bit names are generally very\n * similar between the device families, but small differences in naming exist.\n *\n * In order to make the same set of firmware work accross the device families,\n * when modifying SFR contents, a slightly abstracted name is used, which is\n * then \"mapped\" to the appropriate real name in the usb_hal_picxx.h header.\n *\n * Make sure to include the correct version of the usb_hal_picxx.h file for\n * the microcontroller family which will be used.\n *\n * The software supplied herewith by Microchip Technology Incorporated\n * (the 'Company') for its PICmicro(R) Microcontroller is intended and\n * supplied to you, the Company's customer, for use solely and\n * exclusively on Microchip PICmicro Microcontroller products. The\n * software is owned by the Company and/or its supplier, and is\n * protected under applicable copyright laws. All rights are reserved.\n * Any use in violation of the foregoing restrictions may subject the\n * user to criminal sanctions under applicable laws, as well as to\n * civil liability for the breach of the terms and conditions of this\n * license.\n *\n * THIS SOFTWARE IS PROVIDED IN AN 'AS IS' CONDITION. NO WARRANTIES,\n * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED\n * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\n * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT,\n * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR\n * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n */\n#ifndef USB_HAL_PIC32_H\n#define USB_HAL_PIC32_H\n\n/* Buffer Descriptor Status Register Initialization Parameters */\n\n//The _BSTALL definition is changed from 0x04 to 0x00 to\n// fix a difference in the PIC18 and PIC24 definitions of this\n// bit.  This should be changed back once the definitions are\n// synced.\n#define _BSTALL     0x04        //Buffer Stall enable\n#define _DTSEN      0x08        //Data Toggle Synch enable\n#define _DAT0       0x00        //DATA0 packet expected next\n#define _DAT1       0x40        //DATA1 packet expected next\n#define _DTSMASK    0x40        //DTS Mask\n#define _USIE       0x80        //SIE owns buffer\n#define _UCPU       0x00        //CPU owns buffer\n\n#define _STAT_MASK  0xFC\n\n// Buffer Descriptor Status Register layout.\ntypedef union __attribute__ ((packed)) _BD_STAT\n{\n    struct __attribute__ ((packed)){\n        unsigned            :2;\n        unsigned    BSTALL  :1;     //Buffer Stall Enable\n        unsigned    DTSEN   :1;     //Data Toggle Synch Enable\n        unsigned            :2;     //Reserved - write as 00\n        unsigned    DTS     :1;     //Data Toggle Synch Value\n        unsigned    UOWN    :1;     //USB Ownership\n    };\n    struct __attribute__ ((packed)){\n        unsigned            :2;\n        unsigned    PID0    :1;\n        unsigned    PID1    :1;\n        unsigned    PID2    :1;\n        unsigned    PID3    :1;\n\n    };\n    struct __attribute__ ((packed)){\n        unsigned            :2;\n        unsigned    PID     :4;     //Packet Identifier\n    };\n    unsigned short  Val;\n} BD_STAT;\n\n// BDT Entry Layout\ntypedef union __attribute__ ((packed))__BDT\n{\n    struct __attribute__ ((packed))\n    {\n        BD_STAT     STAT;\n        unsigned    CNT:10;\n        unsigned char *ADR;         //Buffer Address\n    };\n    struct __attribute__ ((packed))\n    {\n        unsigned    res  :16;\n        unsigned    count:10;\n    };\n    unsigned int    w[2];\n    unsigned short  v[4];\n    unsigned long long Val;\n} BDT_ENTRY;\n\n#define USTAT_EP0_PP_MASK   ~0x04\n#define USTAT_EP_MASK       0xFC\n#define USTAT_EP0_OUT       0x00\n#define USTAT_EP0_OUT_EVEN  0x00\n#define USTAT_EP0_OUT_ODD   0x04\n\n#define USTAT_EP0_IN        0x08\n#define USTAT_EP0_IN_EVEN   0x08\n#define USTAT_EP0_IN_ODD    0x0C\n\n#define UEP_STALL 0x0002\n\n//#define USB_PING_PONG__NO_PING_PONG   0x00\n//#define USB_PING_PONG__EP0_OUT_ONLY   0x01\n#define USB_PING_PONG__FULL_PING_PONG   0x02\n//#define USB_PING_PONG__ALL_BUT_EP0    0x03\n\n/*\n * Translate virtual address to physical one.\n * Only for fixed mapping.\n */\nstatic inline void *ConvertToPhysicalAddress (volatile void *addr)\n{\n    unsigned virt = (unsigned) addr;\n    unsigned phys;\n\n    if (virt & 0x80000000) {\n        if (virt & 0x40000000) {\n            // kseg2 or kseg3 - no mapping\n            phys = virt;\n        } else {\n            // kseg0 or kseg1, cut bits A[31:29]\n            phys = virt & 0x1fffffff;\n        }\n    } else {\n        // kuseg\n        phys = virt + 0x40000000;\n    }\n    return (void*) phys;\n}\n\n/*\n * This macro is used to disable the USB module\n */\n#define usb_module_disable() {\\\n        U1CON = 0;\\\n        U1IE = 0;\\\n        U1OTGIE = 0;\\\n        U1PWR |= PIC32_U1PWR_USBPWR;\\\n        usb_device_state = DETACHED_STATE;\\\n}\n#endif\n"
  },
  {
    "path": "sys/arch/pic32/include/_float.h",
    "content": "#ifndef _MACHINE__FLOAT_H_\n#define _MACHINE__FLOAT_H_\n\n/* Characteristics of IEEE floating types */\n\n#define FLT_RADIX       2\n#define FLT_ROUNDS      1\n\n/*\n * These values provide information pertaining to the float type.\n */\n#define FLT_EPSILON     1.19209290E-07F /* b**(1-p) */\n#define FLT_MAX         3.40282347E+38F /* (1-b**(-p))*b**emax */\n#define FLT_MIN         1.17549435E-38F /* b**(emin-1) */\n#define FLT_DIG         6               /* floor((p-1)*log10(b))+(b == 10) */\n#define FLT_MANT_DIG    24              /* p */\n#define FLT_MAX_10_EXP  38              /* floor(log10((1-b**(-p))*b**emax)) */\n#define FLT_MAX_EXP     128             /* emax */\n#define FLT_MIN_10_EXP  (-37)           /* ceil(log10(b**(emin-1))) */\n#define FLT_MIN_EXP     (-125)          /* emin */\n\n/*\n * These values provide information pertaining to the double type.\n */\n#define DBL_EPSILON     2.2204460492503131E-16\n#define DBL_MAX         1.7976931348623157E+308\n#define DBL_MIN         2.2250738585072014E-308\n#define DBL_DIG         15\n#define DBL_MANT_DIG    53\n#define DBL_MAX_10_EXP  308\n#define DBL_MAX_EXP     1024\n#define DBL_MIN_10_EXP  (-307)\n#define DBL_MIN_EXP     (-1021)\n\n/*\n * These values provide information pertaining to the long double type.\n */\n#define LDBL_EPSILON    DBL_EPSILON\n#define LDBL_MAX        DBL_MAX\n#define LDBL_MIN        DBL_MIN\n#define LDBL_DIG        DBL_DIG\n#define LDBL_MANT_DIG   DBL_MANT_DIG\n#define LDBL_MAX_10_EXP DBL_MAX_10_EXP\n#define LDBL_MAX_EXP    DBL_MAX_EXP\n#define LDBL_MIN_10_EXP DBL_MIN_10_EXP\n#define LDBL_MIN_EXP    DBL_MIN_EXP\n\n#endif /* _MACHINE__FLOAT_H_ */\n"
  },
  {
    "path": "sys/arch/pic32/include/cpu.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)cpu.h\t1.5 (2.11BSD GTE) 1998/4/3\n */\n\n/*\n * CTL_MACHDEP definitions.\n */\n#define CPU_CONSDEV             1       /* dev_t: console terminal device */\n#define CPU_ERRMSG              2       /* get error message by errno */\n#define CPU_NLIST               3       /* get name address */\n#define CPU_TIMO_CMD            4\n#define CPU_TIMO_SEND_OP        5\n#define CPU_TIMO_SEND_CSD       6\n#define CPU_TIMO_READ           7\n#define CPU_TIMO_WAIT_CMD       8\n#define CPU_TIMO_WAIT_WDATA     9\n#define CPU_TIMO_WAIT_WDONE     10\n#define CPU_TIMO_WAIT_WSTOP     11\n#define CPU_TIMO_WAIT_WIDLE     12\n#define CPU_FREQ_KHZ            13      /* processor clock in kHz */\n#define CPU_BUS_KHZ             14      /* i/o bus clock in kHz */\n#define CPU_MAXID               15      /* number of valid machdep ids */\n\n#ifndef KERNEL\n#define CTL_MACHDEP_NAMES { \\\n    { 0, 0 }, \\\n    { \"console_device\", CTLTYPE_STRUCT }, \\\n    { 0, 0 }, \\\n    { 0, 0 }, \\\n    { \"sd_timeout_cmd\", CTLTYPE_INT }, \\\n    { \"sd_timeout_send_op\", CTLTYPE_INT }, \\\n    { \"sd_timeout_send_csd\", CTLTYPE_INT }, \\\n    { \"sd_timeout_read\", CTLTYPE_INT }, \\\n    { \"sd_timeout_wait_cmd\", CTLTYPE_INT }, \\\n    { \"sd_timeout_wait_wdata\", CTLTYPE_INT }, \\\n    { \"sd_timeout_wait_wdone\", CTLTYPE_INT }, \\\n    { \"sd_timeout_wait_wstop\", CTLTYPE_INT }, \\\n    { \"sd_timeout_wait_widle\", CTLTYPE_INT }, \\\n    { \"cpu_khz\", CTLTYPE_INT }, \\\n    { \"bus_khz\", CTLTYPE_INT }, \\\n}\n#endif\n"
  },
  {
    "path": "sys/arch/pic32/include/debug.h",
    "content": "#ifndef _DEBUG_H\n#define _DEBUG_H\n\n#define DEBUG(...)\n#define DEBUG1(...)\n#define DEBUG2(...)\n#define DEBUG3(...)\n#define DEBUG4(...)\n#define DEBUG5(...)\n#define DEBUG6(...)\n#define DEBUG7(...)\n#define DEBUG8(...)\n#define DEBUG9(...)\n\n#ifdef GLOBAL_DEBUG\n#undef DEBUG\n#define DEBUG(...) printf(__VA_ARGS__)\n\n#if (GLOBAL_DEBUG>=1)\n#undef DEBUG1\n#define DEBUG1(...) printf(__VA_ARGS__)\n#endif\n\n#if (GLOBAL_DEBUG>=2)\n#undef DEBUG2\n#define DEBUG2(...) printf(__VA_ARGS__)\n#endif\n\n#if (GLOBAL_DEBUG>=3)\n#undef DEBUG3\n#define DEBUG3(...) printf(__VA_ARGS__)\n#endif\n\n#if (GLOBAL_DEBUG>=4)\n#undef DEBUG4\n#define DEBUG4(...) printf(__VA_ARGS__)\n#endif\n\n#if (GLOBAL_DEBUG>=5)\n#undef DEBUG5\n#define DEBUG5(...) printf(__VA_ARGS__)\n#endif\n\n#if (GLOBAL_DEBUG>=6)\n#undef DEBUG6\n#define DEBUG6(...) printf(__VA_ARGS__)\n#endif\n\n#if (GLOBAL_DEBUG>=7)\n#undef DEBUG7\n#define DEBUG7(...) printf(__VA_ARGS__)\n#endif\n\n#if (GLOBAL_DEBUG>=8)\n#undef DEBUG8\n#define DEBUG8(...) printf(__VA_ARGS__)\n#endif\n\n#if (GLOBAL_DEBUG>=9)\n#undef DEBUG9\n#define DEBUG9(...) printf(__VA_ARGS__)\n#endif\n\n#endif\n\n#define SETVAL(X) \\\n    TRISECLR = 0b0000000011111111; \\\n    LATECLR =  0b0000000011111111; \\\n    LATESET =  (X & 0xFF)\n/*\n    TRISFCLR = 0b0000000000110000; \\\n    LATFCLR =  0b0000000000110000; \\\n    TRISBCLR = 0b1111111000000000; \\\n    LATBCLR =  0b1111111000000000; \\\n    LATBCLR =  0b0000001000000000; \\\n    LATFSET = ((X & 0x01) << 5) | ((X & 0x02) << 3); \\\n    LATBSET = ((X & 0x04) << 13) | ((X & 0x08) << 11) | ((X & 0x10) << 9) | ((X & 0x20) << 7) | ((X & 0x40) << 5) | ((X & 0x80) << 3); \\\n    LATBSET =  0b0000001000000000;\n*/\n\n#define LED_ON(X,Y) TRIS_CLR(X) = 1<<(Y); LAT_SET(X) = 1<<(Y);\n#define LED_OFF(X,Y) TRIS_CLR(X) = 1<<(Y); LAT_CLR(X) = 1<<(Y);\n\n#endif\n"
  },
  {
    "path": "sys/arch/pic32/include/elf_machdep.h",
    "content": "/*\t$NetBSD: elf_machdep.h,v 1.20 2017/11/06 19:17:43 christos Exp $\t*/\n\n/*-\n * Copyright (c) 2013 The NetBSD Foundation, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS\n * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\n * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n */\n#ifndef _MIPS_ELF_MACHDEP_H_\n#define\t_MIPS_ELF_MACHDEP_H_\n\n#ifdef _LP64\n#define\tKERN_ELFSIZE\t\t64\n#define\tARCH_ELFSIZE\t\t64\t/* MD native binary size */\n#define ELFSIZE\t\t\t\t64\n#else\n#define\tKERN_ELFSIZE\t\t32\n#define\tARCH_ELFSIZE\t\t32\t/* MD native binary size */\n#define ELFSIZE\t\t\t\t32\n#endif\n\n#if ELFSIZE == 32\n#define\tELF32_MACHDEP_ID_CASES\t\t\t\t\t\t\\\n\t\tcase EM_MIPS:\t\t\t\t\t\t\\\n\t\t\tbreak;\n\n#define\tELF32_MACHDEP_ID\tEM_MIPS\n#elif ELFSIZE == 64\n#define\tELF64_MACHDEP_ID_CASES\t\t\t\t\t\t\\\n\t\tcase EM_MIPS:\t\t\t\t\t\t\\\n\t\t\tbreak;\n\n#define\tELF64_MACHDEP_ID\tEM_MIPS\n#endif\n\n/* mips relocs. */\n\n#define\tR_MIPS_NONE\t\t0\n#define\tR_MIPS_16\t\t1\n#define\tR_MIPS_32\t\t2\n#define\tR_MIPS_REL32\t\t3\n#define\tR_MIPS_REL\t\tR_MIPS_REL32\n#define\tR_MIPS_26\t\t4\n#define\tR_MIPS_HI16\t\t5\t/* high 16 bits of symbol value */\n#define\tR_MIPS_LO16\t\t6\t/* low 16 bits of symbol value */\n#define\tR_MIPS_GPREL16\t\t7\t/* GP-relative reference  */\n#define\tR_MIPS_LITERAL\t\t8\t/* Reference to literal section  */\n#define\tR_MIPS_GOT16\t\t9\t/* Reference to global offset table */\n#define\tR_MIPS_GOT\t\tR_MIPS_GOT16\n#define\tR_MIPS_PC16\t\t10\t/* 16 bit PC relative reference */\n#define\tR_MIPS_CALL16 \t\t11\t/* 16 bit call thru glbl offset tbl */\n#define\tR_MIPS_CALL\t\tR_MIPS_CALL16\n#define\tR_MIPS_GPREL32\t\t12\n\n/* 13, 14, 15 are not defined at this point. */\n#define\tR_MIPS_UNUSED1\t\t13\n#define\tR_MIPS_UNUSED2\t\t14\n#define\tR_MIPS_UNUSED3\t\t15\n\n/*\n * The remaining relocs are apparently part of the 64-bit Irix ELF ABI.\n */\n#define\tR_MIPS_SHIFT5\t\t16\n#define\tR_MIPS_SHIFT6\t\t17\n\n#define\tR_MIPS_64\t\t18\n#define\tR_MIPS_GOT_DISP\t\t19\n#define\tR_MIPS_GOT_PAGE\t\t20\n#define\tR_MIPS_GOT_OFST\t\t21\n#define\tR_MIPS_GOT_HI16\t\t22\n#define\tR_MIPS_GOT_LO16\t\t23\n#define\tR_MIPS_SUB\t\t24\n#define\tR_MIPS_INSERT_A\t\t25\n#define\tR_MIPS_INSERT_B\t\t26\n#define\tR_MIPS_DELETE\t\t27\n#define\tR_MIPS_HIGHER\t\t28\n#define\tR_MIPS_HIGHEST\t\t29\n#define\tR_MIPS_CALL_HI16\t30\n#define\tR_MIPS_CALL_LO16\t31\n#define\tR_MIPS_SCN_DISP\t\t32\n#define\tR_MIPS_REL16\t\t33\n#define\tR_MIPS_ADD_IMMEDIATE\t34\n#define\tR_MIPS_PJUMP\t\t35\n#define\tR_MIPS_RELGOT\t\t36\n#define\tR_MIPS_JALR\t\t37\n/* TLS relocations */\n\n#define\tR_MIPS_TLS_DTPMOD32\t38\t/* Module number 32 bit */\n#define\tR_MIPS_TLS_DTPREL32\t39\t/* Module-relative offset 32 bit */\n#define\tR_MIPS_TLS_DTPMOD64\t40\t/* Module number 64 bit */\n#define\tR_MIPS_TLS_DTPREL64\t41\t/* Module-relative offset 64 bit */\n#define\tR_MIPS_TLS_GD\t\t42\t/* 16 bit GOT offset for GD */\n#define\tR_MIPS_TLS_LDM\t\t43\t/* 16 bit GOT offset for LDM */\n#define\tR_MIPS_TLS_DTPREL_HI16\t44\t/* Module-relative offset, high 16 bits */\n#define\tR_MIPS_TLS_DTPREL_LO16\t45\t/* Module-relative offset, low 16 bits */\n#define\tR_MIPS_TLS_GOTTPREL\t46\t/* 16 bit GOT offset for IE */\n#define\tR_MIPS_TLS_TPREL32\t47\t/* TP-relative offset, 32 bit */\n#define\tR_MIPS_TLS_TPREL64\t48\t/* TP-relative offset, 64 bit */\n#define\tR_MIPS_TLS_TPREL_HI16\t49\t/* TP-relative offset, high 16 bits */\n#define\tR_MIPS_TLS_TPREL_LO16\t50\t/* TP-relative offset, low 16 bits */\n\n#define\tR_MIPS_max\t\t51\n\n#define\tR_TYPE(name)\t\t__CONCAT(R_MIPS_,name)\n\n#define\tR_MIPS16_min\t\t100\n#define\tR_MIPS16_26\t\t100\n#define\tR_MIPS16_GPREL\t\t101\n#define\tR_MIPS16_GOT16\t\t102\n#define\tR_MIPS16_CALL16\t\t103\n#define\tR_MIPS16_HI16\t\t104\n#define\tR_MIPS16_LO16\t\t105\n#define\tR_MIPS16_max\t\t106\n\n#define\tR_MIPS_COPY\t\t126\n#define\tR_MIPS_JUMP_SLOT\t127\n\n/* mips dynamic tags */\n\n#define\tDT_MIPS_RLD_VERSION\t0x70000001\n#define\tDT_MIPS_TIME_STAMP\t0x70000002\n#define\tDT_MIPS_ICHECKSUM\t0x70000003\n#define\tDT_MIPS_IVERSION\t0x70000004\n#define\tDT_MIPS_FLAGS\t\t0x70000005\n#define\tDT_MIPS_BASE_ADDRESS\t0x70000006\n#define\tDT_MIPS_CONFLICT\t0x70000008\n#define\tDT_MIPS_LIBLIST\t\t0x70000009\n#define\tDT_MIPS_CONFLICTNO\t0x7000000b\n#define\tDT_MIPS_LOCAL_GOTNO\t0x7000000a\t/* number of local got ents */\n#define\tDT_MIPS_LIBLISTNO\t0x70000010\n#define\tDT_MIPS_SYMTABNO\t0x70000011\t/* number of .dynsym entries */\n#define\tDT_MIPS_UNREFEXTNO\t0x70000012\n#define\tDT_MIPS_GOTSYM\t\t0x70000013\t/* first dynamic sym in got */\n#define\tDT_MIPS_HIPAGENO\t0x70000014\n#define\tDT_MIPS_RLD_MAP\t\t0x70000016\t/* address of loader map */\n#define\tDT_MIPS_PLTGOT\t\t0x70000032\n#define\tDT_MIPS_RWPLT\t\t0x70000034\n\n/*\n * ELF Flags\n */\n#define\tEF_MIPS_PIC\t\t0x00000002\t/* Contains PIC code */\n#define\tEF_MIPS_CPIC\t\t0x00000004\t/* STD PIC calling sequence */\n#define\tEF_MIPS_ABI2\t\t0x00000020\t/* N32 */\n\n#define\tEF_MIPS_ARCH_ASE\t0x0f000000\t/* Architectural extensions */\n#define\tEF_MIPS_ARCH_MDMX\t0x08000000\t/* MDMX multimedia extension */\n#define\tEF_MIPS_ARCH_M16\t0x04000000\t/* MIPS-16 ISA extensions */\n\n#define\tEF_MIPS_ARCH\t\t0xf0000000\t/* Architecture field */\n#define\tEF_MIPS_ARCH_1\t\t0x00000000\t/* -mips1 code */\n#define\tEF_MIPS_ARCH_2\t\t0x10000000\t/* -mips2 code */\n#define\tEF_MIPS_ARCH_3\t\t0x20000000\t/* -mips3 code */\n#define\tEF_MIPS_ARCH_4\t\t0x30000000\t/* -mips4 code */\n#define\tEF_MIPS_ARCH_5\t\t0x40000000\t/* -mips5 code */\n#define\tEF_MIPS_ARCH_32\t\t0x50000000\t/* -mips32 code */\n#define\tEF_MIPS_ARCH_64\t\t0x60000000\t/* -mips64 code */\n#define\tEF_MIPS_ARCH_32R2\t0x70000000\t/* -mips32r2 code */\n#define\tEF_MIPS_ARCH_64R2\t0x80000000\t/* -mips64r2 code */\n\n#define\tEF_MIPS_ABI\t\t0x0000f000\n#define\tEF_MIPS_ABI_O32\t\t0x00001000\n#define\tEF_MIPS_ABI_O64\t\t0x00002000\n#define\tEF_MIPS_ABI_EABI32\t0x00003000\n#define\tEF_MIPS_ABI_EABI64\t0x00004000\n\n#if defined(__MIPSEB__)\n#define\tELF32_MACHDEP_ENDIANNESS\tELFDATA2MSB\n#define\tELF64_MACHDEP_ENDIANNESS\tELFDATA2MSB\n#elif defined(__MIPSEL__)\n#define\tELF32_MACHDEP_ENDIANNESS\tELFDATA2LSB\n#define\tELF64_MACHDEP_ENDIANNESS\tELFDATA2LSB\n#elif !defined(HAVE_NBTOOL_CONFIG_H)\n#error neither __MIPSEL__ nor __MIPSEB__ are defined.\n#endif\n\n/*\n * Tell the kernel ELF exec code not to try relocating the interpreter\n * (ld.so) for dynamically-linked ELF binaries.\n */\n#ifdef _KERNEL\n#define ELF_INTERP_NON_RELOCATABLE\n#endif\n\n#endif /* _MIPS_ELF_MACHDEP_H_ */\n"
  },
  {
    "path": "sys/arch/pic32/include/frame.h",
    "content": "/*\n * Copyright (c) 2021 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#ifndef _MACHINE_FRAME_H_\n#define _MACHINE_FRAME_H_\n\nstruct\ttrapframe {\n\tu_int\ttf_r1;\n\tu_int\ttf_r2;\n\tu_int\ttf_r3;\n\tu_int\ttf_r4;\n\tu_int\ttf_r5;\n\tu_int\ttf_r6;\n\tu_int\ttf_r7;\n\tu_int\ttf_r8;\n\tu_int\ttf_r9;\n\tu_int\ttf_r10;\n\tu_int\ttf_r11;\n\tu_int\ttf_r12;\n\tu_int\ttf_r13;\n\tu_int\ttf_r14;\n\tu_int\ttf_r15;\n\tu_int\ttf_r16;\n\tu_int\ttf_r17;\n\tu_int\ttf_r18;\n\tu_int\ttf_r19;\n\tu_int\ttf_r20;\n\tu_int\ttf_r21;\n\tu_int\ttf_r22;\n\tu_int\ttf_r23;\n\tu_int\ttf_r24;\n\tu_int\ttf_r25;\n\tu_int\ttf_gp;\n\tu_int\ttf_sp;\n\tu_int\ttf_fp;\n\tu_int\ttf_ra;\n\tu_int\ttf_lo;\n\tu_int\ttf_hi;\n\tu_int\ttf_status;\n\tu_int\ttf_pc;\n};\n\n#endif /* !_MACHINE_FRAME_H_ */\n"
  },
  {
    "path": "sys/arch/pic32/include/io.h",
    "content": "/*\n * Hardware register defines for MIPS32 architecture.\n *\n * Copyright (C) 2008-2010 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#ifdef PIC32MX4\n#   include \"machine/pic32mx.h\"\n#endif\n#ifdef PIC32MX7\n#   include \"machine/pic32mx.h\"\n#endif\n\n/*\n * Offsets of register values in saved context.\n */\n#define FRAME_R1        0\n#define FRAME_R2        1\n#define FRAME_R3        2\n#define FRAME_R4        3\n#define FRAME_R5        4\n#define FRAME_R6        5\n#define FRAME_R7        6\n#define FRAME_R8        7\n#define FRAME_R9        8\n#define FRAME_R10       9\n#define FRAME_R11       10\n#define FRAME_R12       11\n#define FRAME_R13       12\n#define FRAME_R14       13\n#define FRAME_R15       14\n#define FRAME_R16       15\n#define FRAME_R17       16\n#define FRAME_R18       17\n#define FRAME_R19       18\n#define FRAME_R20       19\n#define FRAME_R21       20\n#define FRAME_R22       21\n#define FRAME_R23       22\n#define FRAME_R24       23\n#define FRAME_R25       24\n#define FRAME_GP        25\n#define FRAME_SP        26\n#define FRAME_FP        27\n#define FRAME_RA        28\n#define FRAME_LO        29\n#define FRAME_HI        30\n#define FRAME_STATUS    31\n#define FRAME_PC        32\n\n#define FRAME_WORDS     33\n\n#ifndef __ASSEMBLER__\n\n#ifndef KERNEL\n/*\n * 2BSD system call extensions: use with care.\n */\n\n/*\n * Read peripheral register.\n */\nunsigned ufetch (unsigned addr);\n\n/*\n * Write peripheral register.\n */\nunsigned ustore (unsigned addr, unsigned value);\n\n/*\n * Call a kernel function.\n */\nunsigned ucall (int priority, void *address, int arg1, int arg2);\n\n#endif /* KERNEL */\n\n/*\n * Set value of stack pointer register.\n */\nstatic void inline __attribute__ ((always_inline))\nmips_set_stack_pointer (void *x)\n{\n    asm volatile (\n    \"move   $sp, %0\"\n    : : \"r\" (x) : \"sp\");\n}\n\n/*\n * Get value of stack pointer register.\n */\nstatic inline __attribute__ ((always_inline))\nvoid *mips_get_stack_pointer ()\n{\n    void *x;\n\n    asm volatile (\n    \"move   %0, $sp\"\n    : \"=r\" (x));\n    return x;\n}\n\n/*\n * Read C0 coprocessor register.\n */\n#define mips_read_c0_register(reg,sel) \\\n    ({  int __value; \\\n        asm volatile ( \\\n        \"mfc0   %0, $%1, %2\" \\\n        : \"=r\" (__value) : \"K\" (reg), \"K\" (sel)); \\\n        __value; \\\n    })\n\n/*\n * Write C0 coprocessor register.\n */\n#define mips_write_c0_register(reg, sel, value) \\\n    do { \\\n        asm volatile ( \\\n        \"mtc0   %z0, $%1, %2 \\n ehb\" \\\n        : : \"r\" ((unsigned int) (value)), \"K\" (reg), \"K\" (sel)); \\\n    } while (0)\n\n/*\n * Disable the hardware interrupts,\n * saving the interrupt state into the supplied variable.\n */\nstatic int inline __attribute__ ((always_inline))\nmips_intr_disable ()\n{\n    int status;\n    asm volatile (\"di   %0\" : \"=r\" (status));\n    return status;\n}\n\n/*\n * Restore the hardware interrupt mode using the saved interrupt state.\n */\nstatic void inline __attribute__ ((always_inline))\nmips_intr_restore (int x)\n{\n    /* C0_STATUS */\n    mips_write_c0_register (12, 0, x);\n}\n\n/*\n * Explicit hazard barrier.\n */\nstatic void inline __attribute__ ((always_inline))\nmips_ehb()\n{\n    asm volatile (\"ehb\");\n}\n\n/*\n * Enable hardware interrupts.\n */\nstatic int inline __attribute__ ((always_inline))\nmips_intr_enable ()\n{\n    int status;\n    asm volatile (\"ei   %0\" : \"=r\" (status));\n    return status;\n}\n\n/*\n * Count a number of leading (most significant) zero bits in a word.\n */\nstatic int inline __attribute__ ((always_inline))\nmips_clz (unsigned x)\n{\n    int n;\n\n    asm volatile (\"clz  %0, %1\"\n        : \"=r\" (n) : \"r\" (x));\n    return n;\n}\n\n/*\n * Swap bytes in a word: ABCD to DCBA.\n */\nstatic unsigned inline __attribute__ ((always_inline))\nmips_bswap (unsigned x)\n{\n    int n;\n\n    asm volatile (\n    \"wsbh   %0, %1 \\n\"\n    \"rotr   %0, 16\"\n        : \"=r\" (n) : \"r\" (x));\n    return n;\n}\n#endif /* __ASSEMBLER__ */\n"
  },
  {
    "path": "sys/arch/pic32/include/limits.h",
    "content": "/*\n * Copyright (c) 1988, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n *\t@(#)limits.h\t8.3.1 (2.11BSD) 1996/1/11\n */\n\n#define CHAR_BIT        8               /* number of bits in a char */\n\n/*\n * According to ANSI (section 2.2.4.2), the values below must be usable by\n * #if preprocessing directives.  Additionally, the expression must have the\n * same type as would an expression that is an object of the corresponding\n * type converted according to the integral promotions.  The subtraction for\n * INT_MIN and LONG_MIN is so the value is not unsigned; 2147483648 is an\n * unsigned int for 32-bit two's complement ANSI compilers (section 3.1.3.2).\n * These numbers work for pcc as well.  The UINT_MAX and ULONG_MAX values\n * are written as hex so that GCC will be quiet about large integer constants.\n */\n#define SCHAR_MAX       127             /* min value for a signed char */\n#define SCHAR_MIN       (-128)          /* max value for a signed char */\n\n#define UCHAR_MAX       255             /* max value for an unsigned char */\n#define CHAR_MAX        127             /* max value for a char */\n#define CHAR_MIN        (-128)          /* min value for a char */\n\n#define USHRT_MAX       65535           /* max value for an unsigned short */\n#define SHRT_MAX        32767           /* max value for a short */\n#define SHRT_MIN        (-32768)        /* min value for a short */\n\n#define UINT_MAX        0xffffffff      /* max value for an unsigned int */\n#define INT_MAX         2147483647      /* max value for an int */\n#define INT_MIN         (-2147483647-1) /* min value for an int */\n\n#define ULONG_MAX       0xffffffff      /* max value for an unsigned long */\n#define LONG_MAX        2147483647L     /* max value for a long */\n#define LONG_MIN        (-2147483647L-1L)       /* min value for a long */\n\n#define SSIZE_MAX       INT_MAX         /* max value for a ssize_t */\n#define SIZE_T_MAX      UINT_MAX        /* max value for a size_t */\n"
  },
  {
    "path": "sys/arch/pic32/include/machparam.h",
    "content": "/*\n * Machine dependent constants for MIPS32.\n *\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)machparam.h\t1.4 (2.11BSD GTE) 1998/9/15\n */\n\n#ifndef ENDIAN\n\n#define MACHINE         \"pic32\"\n#define MACHINE_ARCH    \"mips\"\n\n/*\n * Definitions for byte order,\n * according to byte significance from low address to high.\n */\n#define LITTLE          1234            /* least-significant byte first (vax) */\n#define BIG             4321            /* most-significant byte first */\n#define PDP             3412            /* LSB first in word, MSW first in long (pdp) */\n#define ENDIAN          LITTLE          /* byte order on pic32 */\n\n/*\n * The time for a process to be blocked before being very swappable.\n * This is a number of seconds which the system takes as being a non-trivial\n * amount of real time.  You probably shouldn't change this;\n * it is used in subtle ways (fractions and multiples of it are, that is, like\n * half of a ``long time'', almost a long time, etc.)\n * It is related to human patience and other factors which don't really\n * change over time.\n */\n#define MAXSLP          20\n\n/*\n * Clock ticks per second. The HZ value must be an integer factor of 1000.\n */\n#ifndef HZ\n#define HZ              200\n#endif\n\n/*\n * System parameter formulae.\n */\n#ifndef NBUF\n#define NBUF            10                      /* number of i/o buffers */\n#endif\n#ifndef MAXUSERS\n#define MAXUSERS        1                       /* number of user logins */\n#endif\n#ifndef NPROC\n#define NPROC           25                      /* number of processes */\n#endif\n#ifndef NINODE\n#define NINODE          24\n#endif\n#ifndef NFILE\n#define NFILE           24\n#endif\n#define NNAMECACHE      (NINODE * 11/10)\n#define NCALL           (16 + 2 * MAXUSERS)\n#define NCLIST          32                      /* number or CBSIZE blocks */\n#ifndef SMAPSIZ\n#define SMAPSIZ         NPROC                   /* size of swap allocation map */\n#endif\n\n/*\n * Disk blocks.\n */\n#define DEV_BSIZE       1024            /* the same as MAXBSIZE */\n#define DEV_BSHIFT      10              /* log2(DEV_BSIZE) */\n#define DEV_BMASK       (DEV_BSIZE-1)\n\n/* Bytes to disk blocks */\n#define btod(x)         (((x) + DEV_BSIZE-1) >> DEV_BSHIFT)\n\n/*\n * On PIC32, there are total 512 kbytes of flash and 128 kbytes of RAM.\n * We reserve for kernel 192 kbytes of flash and 32 kbytes of RAM.\n */\n#define FLASH_SIZE              (512*1024)\n#define DATA_SIZE               (128*1024)\n\n#define KERNEL_FLASH_SIZE       (192*1024)\n\n#ifdef KERNEL_EXECUTABLE_RAM\nextern void _keram_start(), _keram_end();\n#define KERAM_SIZE ((unsigned)((char*)&_keram_end-(char*)&_keram_start))\n#define KERNEL_DATA_SIZE        (32*1024-KERAM_SIZE)\n#else\n#define KERNEL_DATA_SIZE        (32*1024)\n#endif\n\n#define KERNEL_FLASH_START      0x9d000000\n#define KERNEL_FLASH_END        (KERNEL_FLASH_START + KERNEL_FLASH_SIZE)\n\n#define USER_FLASH_START        (KERNEL_FLASH_END)\n#define USER_FLASH_END          (KERNEL_FLASH_START + FLASH_SIZE)\n\n#define KERNEL_DATA_START       0x80000000\n#define KERNEL_DATA_END         (KERNEL_DATA_START + KERNEL_DATA_SIZE)\n\n#ifdef KERNEL_EXECUTABLE_RAM\n#define USER_DATA_START         (0x7f000000 + KERNEL_DATA_SIZE+KERAM_SIZE)\n#else\n#define USER_DATA_START         (0x7f000000 + KERNEL_DATA_SIZE)\n#endif\n\n#define USER_DATA_END           (0x7f000000 + DATA_SIZE)\n\n#define stacktop(siz)           (USER_DATA_END)\n#define stackbas(siz)           (USER_DATA_END-(siz))\n\n/*\n * User area: a user structure, followed by the kernel\n * stack.  The number for USIZE is determined empirically.\n *\n * Note that the SBASE and STOP constants are only used by the assembly code,\n * but are defined here to localize information about the user area's\n * layout (see pdp/genassym.c).  Note also that a networking stack is always\n * allocated even for non-networking systems.  This prevents problems with\n * applications having to be recompiled for networking versus non-networking\n * systems.\n */\n#define USIZE           3072\n#define SSIZE           2048            /* initial stack size (bytes) */\n\n/*\n * Collect kernel statistics by default.\n */\n#if !defined(UCB_METER) && !defined(NO_UCB_METER)\n#define UCB_METER\n#endif\n\n#ifdef KERNEL\n#include \"machine/io.h\"\n\n/*\n * Macros to decode processor status word.\n */\n#define USERMODE(ps)    (((ps) & ST_UM) != 0)\n#define BASEPRI(ps)     (CA_RIPL(ps) == 0)\n\n#define splbio()        mips_intr_disable()\n#define spltty()        mips_intr_disable()\n#define splclock()      mips_intr_disable()\n#define splhigh()       mips_intr_disable()\n#define splnet()        mips_intr_enable()\n#define splsoftclock()  mips_intr_enable()\n#define spl0()          mips_intr_enable()\n#define splx(s)         mips_intr_restore(s)\n\n#define noop()          asm volatile(\"nop\")\n\n/*\n * Wait for something to happen.\n */\nvoid idle(void);\n\n/*\n * Microsecond delay routine.\n */\nvoid udelay(unsigned usec);\n\n/*\n * Setup system timer for `hz' timer interrupts per second.\n */\nvoid clkstart(void);\n\n/*\n * Control LEDs, installed on the board.\n */\n#define LED_MISC4       0x80\n#define LED_MISC3       0x40\n#define LED_MISC2       0x20\n#define LED_MISC1       0x10\n#define LED_TTY         0x08\n#define LED_SWAP        0x04\n#define LED_DISK        0x02\n#define LED_KERNEL      0x01\n\nvoid led_control(int mask, int on);\n\n/*\n * Port i/o access, relative to TRIS base.\n */\n#define TRIS_VAL(p)     (&p)[0]\n#define TRIS_CLR(p)     (&p)[1]\n#define TRIS_SET(p)     (&p)[2]\n#define TRIS_INV(p)     (&p)[3]\n#define PORT_VAL(p)     (&p)[4]\n#define PORT_CLR(p)     (&p)[5]\n#define PORT_SET(p)     (&p)[6]\n#define PORT_INV(p)     (&p)[7]\n#define LAT_VAL(p)      (&p)[8]\n#define LAT_CLR(p)      (&p)[9]\n#define LAT_SET(p)      (&p)[10]\n#define LAT_INV(p)      (&p)[11]\n\n/*\n * SD timeouts, for sysctl.\n */\nextern int sd_timo_cmd;\nextern int sd_timo_send_op;\nextern int sd_timo_send_csd;\nextern int sd_timo_read;\nextern int sd_timo_wait_cmd;\nextern int sd_timo_wait_wdata;\nextern int sd_timo_wait_wdone;\nextern int sd_timo_wait_wstop;\nextern int sd_timo_wait_widle;\n\n/*\n * GPIO pins.\n */\nvoid gpio_set_input(int pin);\nvoid gpio_set_output(int pin);\nvoid gpio_set(int pin);\nvoid gpio_clr(int pin);\nint gpio_get(int pin);\n\nchar gpio_portname(int pin);\nint gpio_pinno(int pin);\n\n/* Convert port name/signal into a pin number. */\n#define GPIO_PIN(x,n) (((x)-'A'+1) << 4 | (n))\n\n/*\n * CPU package type: 64 pins or 100 pins.\n */\nextern int cpu_pins;\n\n#endif /* KERNEL */\n\n#endif /* ENDIAN */\n"
  },
  {
    "path": "sys/arch/pic32/include/pic32mx.h",
    "content": "/*\n * Hardware register defines for all Microchip PIC32MX microcontrollers.\n *\n * Copyright (C) 2010 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#ifndef _IO_PIC32MX_H\n#define _IO_PIC32MX_H\n\n/*--------------------------------------\n * Coprocessor 0 registers.\n */\n#define C0_HWRENA       7       /* Enable RDHWR in non-privileged mode */\n#define C0_BADVADDR     8       /* Virtual address of last exception */\n#define C0_COUNT        9       /* Processor cycle count */\n#define C0_COMPARE      11      /* Timer interrupt control */\n#define C0_STATUS       12      /* Processor status and control */\n#define C0_INTCTL       12      /* Select 1: interrupt control */\n#define C0_SRSCTL       12      /* Select 2: GPR shadow set control */\n#define C0_SRSMAP       12      /* Select 3: vector to shadow set mapping */\n#define C0_CAUSE        13      /* Cause of last exception */\n#define C0_EPC          14      /* Program counter at last exception */\n#define C0_PRID         15      /* Processor identification (read only) */\n#define C0_EBASE        15      /* Select 1: exception base address */\n#define C0_CONFIG       16      /* Configuration */\n#define C0_CONFIG1      16      /* Select 1: configuration 1 */\n#define C0_CONFIG2      16      /* Select 2: configuration 2 */\n#define C0_CONFIG3      16      /* Select 3: configuration 3 */\n#define C0_DEBUG        23      /* Debug control and status */\n#define C0_DEPC         24      /* Program counter at last debug exception */\n#define C0_ERROREPC     30      /* Program counter at last error */\n#define C0_DESAVE       31      /* Debug handler scratchpad register */\n\n/*\n * Status register.\n */\n#define ST_CU0          0x10000000      /* Access to coprocessor 0 allowed (in user mode) */\n#define ST_RP           0x08000000      /* Enable reduced power mode */\n#define ST_RE           0x02000000      /* Reverse endianness (in user mode) */\n#define ST_BEV          0x00400000      /* Exception vectors: bootstrap */\n#define ST_SR           0x00100000      /* Soft reset */\n#define ST_NMI          0x00080000      /* NMI reset */\n#define ST_IPL(x)       ((x) << 10)     /* Current interrupt priority level */\n#define ST_UM           0x00000010      /* User mode */\n#define ST_ERL          0x00000004      /* Error level */\n#define ST_EXL          0x00000002      /* Exception level */\n#define ST_IE           0x00000001      /* Interrupt enable */\n\n/*\n * Cause register.\n */\n#define CA_BD           0x80000000      /* Exception occured in delay slot */\n#define CA_TI           0x40000000      /* Timer interrupt is pending */\n#define CA_CE           0x30000000      /* Coprocessor exception */\n#define CA_DC           0x08000000      /* Disable COUNT register */\n#define CA_IV           0x00800000      /* Use special interrupt vector 0x200 */\n#define CA_RIPL(r)      ((r)>>10 & 63)  /* Requested interrupt priority level */\n#define CA_IP1          0x00020000      /* Request software interrupt 1 */\n#define CA_IP0          0x00010000      /* Request software interrupt 0 */\n#define CA_EXC_CODE     0x0000007c      /* Exception code */\n\n#define CA_Int          0               /* Interrupt */\n#define CA_AdEL         (4 << 2)        /* Address error, load or instruction fetch */\n#define CA_AdES         (5 << 2)        /* Address error, store */\n#define CA_IBE          (6 << 2)        /* Bus error, instruction fetch */\n#define CA_DBE          (7 << 2)        /* Bus error, load or store */\n#define CA_Sys          (8 << 2)        /* Syscall */\n#define CA_Bp           (9 << 2)        /* Breakpoint */\n#define CA_RI           (10 << 2)       /* Reserved instruction */\n#define CA_CPU          (11 << 2)       /* Coprocessor unusable */\n#define CA_Ov           (12 << 2)       /* Arithmetic overflow */\n#define CA_Tr           (13 << 2)       /* Trap */\n\n#define DB_DBD          (1 << 31)       /* Debug exception in a branch delay slot */\n#define DB_DM           (1 << 30)       /* Debug mode */\n#define DB_NODCR        (1 << 29)       /* No dseg present */\n#define DB_LSNM         (1 << 28)       /* Load/stores in dseg go to main memory */\n#define DB_DOZE         (1 << 27)       /* Processor was in low-power mode */\n#define DB_HALT         (1 << 26)       /* Internal system bus clock was running */\n#define DB_COUNTDM      (1 << 25)       /* Count register is running in Debug mode */\n#define DB_IBUSEP       (1 << 24)       /* Instruction fetch bus error exception */\n#define DB_DBUSEP       (1 << 21)       /* Data access bus error exception */\n#define DB_IEXI         (1 << 20)       /* Imprecise error exception */\n#define DB_VER          (7 << 15)       /* EJTAG version number */\n#define DB_DEXCCODE     (0x1f << 10)    /* Cause of exception in Debug mode */\n#define DB_SST          (1 << 8)        /* Single step exception enabled */\n#define DB_DIBImpr      (1 << 6)        /* Imprecise debug instruction break */\n#define DB_DINT         (1 << 5)        /* Debug interrupt exception */\n#define DB_DIB          (1 << 4)        /* Debug instruction break exception */\n#define DB_DDBS         (1 << 3)        /* Debug data break exception on store */\n#define DB_DDBL         (1 << 2)        /* Debug data break exception on load */\n#define DB_DBP          (1 << 1)        /* Debug software breakpoint exception */\n#define DB_DSS          (1 << 0)        /* Debug single-step exception */\n\n/*--------------------------------------\n * Peripheral registers.\n */\n#ifdef __ASSEMBLER__\n#define PIC32_R(a)              (0xBF800000 + (a))\n#else\n#define PIC32_R(a)              *(volatile unsigned*)(0xBF800000 + (a))\n#endif\n\n/*--------------------------------------\n * UART registers.\n */\n#define U1MODE          PIC32_R (0x6000) /* Mode */\n#define U1MODECLR       PIC32_R (0x6004)\n#define U1MODESET       PIC32_R (0x6008)\n#define U1MODEINV       PIC32_R (0x600C)\n#define U1STA           PIC32_R (0x6010) /* Status and control */\n#define U1STACLR        PIC32_R (0x6014)\n#define U1STASET        PIC32_R (0x6018)\n#define U1STAINV        PIC32_R (0x601C)\n#define U1TXREG         PIC32_R (0x6020) /* Transmit */\n#define U1RXREG         PIC32_R (0x6030) /* Receive */\n#define U1BRG           PIC32_R (0x6040) /* Baud rate */\n#define U1BRGCLR        PIC32_R (0x6044)\n#define U1BRGSET        PIC32_R (0x6048)\n#define U1BRGINV        PIC32_R (0x604C)\n\n#ifdef PIC32MX4\n#define U2MODE          PIC32_R (0x6200) /* Mode */\n#define U2MODECLR       PIC32_R (0x6204)\n#define U2MODESET       PIC32_R (0x6208)\n#define U2MODEINV       PIC32_R (0x620C)\n#define U2STA           PIC32_R (0x6210) /* Status and control */\n#define U2STACLR        PIC32_R (0x6214)\n#define U2STASET        PIC32_R (0x6218)\n#define U2STAINV        PIC32_R (0x621C)\n#define U2TXREG         PIC32_R (0x6220) /* Transmit */\n#define U2RXREG         PIC32_R (0x6230) /* Receive */\n#define U2BRG           PIC32_R (0x6240) /* Baud rate */\n#define U2BRGCLR        PIC32_R (0x6244)\n#define U2BRGSET        PIC32_R (0x6248)\n#define U2BRGINV        PIC32_R (0x624C)\n#endif\n#ifdef PIC32MX7\n#define U4MODE          PIC32_R (0x6200) /* Mode */\n#define U4MODECLR       PIC32_R (0x6204)\n#define U4MODESET       PIC32_R (0x6208)\n#define U4MODEINV       PIC32_R (0x620C)\n#define U4STA           PIC32_R (0x6210) /* Status and control */\n#define U4STACLR        PIC32_R (0x6214)\n#define U4STASET        PIC32_R (0x6218)\n#define U4STAINV        PIC32_R (0x621C)\n#define U4TXREG         PIC32_R (0x6220) /* Transmit */\n#define U4RXREG         PIC32_R (0x6230) /* Receive */\n#define U4BRG           PIC32_R (0x6240) /* Baud rate */\n#define U4BRGCLR        PIC32_R (0x6244)\n#define U4BRGSET        PIC32_R (0x6248)\n#define U4BRGINV        PIC32_R (0x624C)\n\n#define U3MODE          PIC32_R (0x6400) /* Mode */\n#define U3MODECLR       PIC32_R (0x6404)\n#define U3MODESET       PIC32_R (0x6408)\n#define U3MODEINV       PIC32_R (0x640C)\n#define U3STA           PIC32_R (0x6410) /* Status and control */\n#define U3STACLR        PIC32_R (0x6414)\n#define U3STASET        PIC32_R (0x6418)\n#define U3STAINV        PIC32_R (0x641C)\n#define U3TXREG         PIC32_R (0x6420) /* Transmit */\n#define U3RXREG         PIC32_R (0x6430) /* Receive */\n#define U3BRG           PIC32_R (0x6440) /* Baud rate */\n#define U3BRGCLR        PIC32_R (0x6444)\n#define U3BRGSET        PIC32_R (0x6448)\n#define U3BRGINV        PIC32_R (0x644C)\n\n#define U6MODE          PIC32_R (0x6600) /* Mode */\n#define U6MODECLR       PIC32_R (0x6604)\n#define U6MODESET       PIC32_R (0x6608)\n#define U6MODEINV       PIC32_R (0x660C)\n#define U6STA           PIC32_R (0x6610) /* Status and control */\n#define U6STACLR        PIC32_R (0x6614)\n#define U6STASET        PIC32_R (0x6618)\n#define U6STAINV        PIC32_R (0x661C)\n#define U6TXREG         PIC32_R (0x6620) /* Transmit */\n#define U6RXREG         PIC32_R (0x6630) /* Receive */\n#define U6BRG           PIC32_R (0x6640) /* Baud rate */\n#define U6BRGCLR        PIC32_R (0x6644)\n#define U6BRGSET        PIC32_R (0x6648)\n#define U6BRGINV        PIC32_R (0x664C)\n\n#define U2MODE          PIC32_R (0x6800) /* Mode */\n#define U2MODECLR       PIC32_R (0x6804)\n#define U2MODESET       PIC32_R (0x6808)\n#define U2MODEINV       PIC32_R (0x680C)\n#define U2STA           PIC32_R (0x6810) /* Status and control */\n#define U2STACLR        PIC32_R (0x6814)\n#define U2STASET        PIC32_R (0x6818)\n#define U2STAINV        PIC32_R (0x681C)\n#define U2TXREG         PIC32_R (0x6820) /* Transmit */\n#define U2RXREG         PIC32_R (0x6830) /* Receive */\n#define U2BRG           PIC32_R (0x6840) /* Baud rate */\n#define U2BRGCLR        PIC32_R (0x6844)\n#define U2BRGSET        PIC32_R (0x6848)\n#define U2BRGINV        PIC32_R (0x684C)\n\n#define U5MODE          PIC32_R (0x6A00) /* Mode */\n#define U5MODECLR       PIC32_R (0x6A04)\n#define U5MODESET       PIC32_R (0x6A08)\n#define U5MODEINV       PIC32_R (0x6A0C)\n#define U5STA           PIC32_R (0x6A10) /* Status and control */\n#define U5STACLR        PIC32_R (0x6A14)\n#define U5STASET        PIC32_R (0x6A18)\n#define U5STAINV        PIC32_R (0x6A1C)\n#define U5TXREG         PIC32_R (0x6A20) /* Transmit */\n#define U5RXREG         PIC32_R (0x6A30) /* Receive */\n#define U5BRG           PIC32_R (0x6A40) /* Baud rate */\n#define U5BRGCLR        PIC32_R (0x6A44)\n#define U5BRGSET        PIC32_R (0x6A48)\n#define U5BRGINV        PIC32_R (0x6A4C)\n#endif\n\n/*\n * UART Mode register.\n */\n#define PIC32_UMODE_STSEL       0x0001  /* 2 Stop bits */\n#define PIC32_UMODE_PDSEL       0x0006  /* Bitmask: */\n#define PIC32_UMODE_PDSEL_8NPAR 0x0000  /* 8-bit data, no parity */\n#define PIC32_UMODE_PDSEL_8EVEN 0x0002  /* 8-bit data, even parity */\n#define PIC32_UMODE_PDSEL_8ODD  0x0004  /* 8-bit data, odd parity */\n#define PIC32_UMODE_PDSEL_9NPAR 0x0006  /* 9-bit data, no parity */\n#define PIC32_UMODE_BRGH        0x0008  /* High Baud Rate Enable */\n#define PIC32_UMODE_RXINV       0x0010  /* Receive Polarity Inversion */\n#define PIC32_UMODE_ABAUD       0x0020  /* Auto-Baud Enable */\n#define PIC32_UMODE_LPBACK      0x0040  /* UARTx Loopback Mode */\n#define PIC32_UMODE_WAKE        0x0080  /* Wake-up on start bit during Sleep Mode */\n#define PIC32_UMODE_UEN         0x0300  /* Bitmask: */\n#define PIC32_UMODE_UEN_RTS     0x0100  /* Using UxRTS pin */\n#define PIC32_UMODE_UEN_RTSCTS  0x0200  /* Using UxCTS and UxRTS pins */\n#define PIC32_UMODE_UEN_BCLK    0x0300  /* Using UxBCLK pin */\n#define PIC32_UMODE_RTSMD       0x0800  /* UxRTS Pin Simplex mode */\n#define PIC32_UMODE_IREN        0x1000  /* IrDA Encoder and Decoder Enable bit */\n#define PIC32_UMODE_SIDL        0x2000  /* Stop in Idle Mode */\n#define PIC32_UMODE_FRZ         0x4000  /* Freeze in Debug Exception Mode */\n#define PIC32_UMODE_ON          0x8000  /* UART Enable */\n\n/*\n * UART Control and status register.\n */\n#define PIC32_USTA_URXDA        0x00000001 /* Receive Data Available (read-only) */\n#define PIC32_USTA_OERR         0x00000002 /* Receive Buffer Overrun */\n#define PIC32_USTA_FERR         0x00000004 /* Framing error detected (read-only) */\n#define PIC32_USTA_PERR         0x00000008 /* Parity error detected (read-only) */\n#define PIC32_USTA_RIDLE        0x00000010 /* Receiver is idle (read-only) */\n#define PIC32_USTA_ADDEN        0x00000020 /* Address Detect mode */\n#define PIC32_USTA_URXISEL      0x000000C0 /* Bitmask: receive interrupt is set when... */\n#define PIC32_USTA_URXISEL_NEMP 0x00000000 /* ...receive buffer is not empty */\n#define PIC32_USTA_URXISEL_HALF 0x00000040 /* ...receive buffer becomes 1/2 full */\n#define PIC32_USTA_URXISEL_3_4  0x00000080 /* ...receive buffer becomes 3/4 full */\n#define PIC32_USTA_TRMT         0x00000100 /* Transmit shift register is empty (read-only) */\n#define PIC32_USTA_UTXBF        0x00000200 /* Transmit buffer is full (read-only) */\n#define PIC32_USTA_UTXEN        0x00000400 /* Transmit Enable */\n#define PIC32_USTA_UTXBRK       0x00000800 /* Transmit Break */\n#define PIC32_USTA_URXEN        0x00001000 /* Receiver Enable */\n#define PIC32_USTA_UTXINV       0x00002000 /* Transmit Polarity Inversion */\n#define PIC32_USTA_UTXISEL      0x0000C000 /* Bitmask: TX interrupt is generated when... */\n#define PIC32_USTA_UTXISEL_1    0x00000000 /* ...the transmit buffer contains at least one empty space */\n#define PIC32_USTA_UTXISEL_ALL  0x00004000 /* ...all characters have been transmitted */\n#define PIC32_USTA_UTXISEL_EMP  0x00008000 /* ...the transmit buffer becomes empty */\n#define PIC32_USTA_ADDR         0x00FF0000 /* Automatic Address Mask */\n#define PIC32_USTA_ADM_EN       0x01000000 /* Automatic Address Detect */\n\n/*\n * Compute the 16-bit baud rate divisor, given\n * the bus frequency and baud rate.\n * Round to the nearest integer.\n */\n#define PIC32_BRG_BAUD(fr,bd)   ((((fr)/8 + (bd)) / (bd) / 2) - 1)\n\n/*--------------------------------------\n * Port A-G registers.\n */\n#define TRISA           PIC32_R (0x86000) /* Port A: mask of inputs */\n#define TRISACLR        PIC32_R (0x86004)\n#define TRISASET        PIC32_R (0x86008)\n#define TRISAINV        PIC32_R (0x8600C)\n#define PORTA           PIC32_R (0x86010) /* Port A: read inputs, write outputs */\n#define PORTACLR        PIC32_R (0x86014)\n#define PORTASET        PIC32_R (0x86018)\n#define PORTAINV        PIC32_R (0x8601C)\n#define LATA            PIC32_R (0x86020) /* Port A: read/write outputs */\n#define LATACLR         PIC32_R (0x86024)\n#define LATASET         PIC32_R (0x86028)\n#define LATAINV         PIC32_R (0x8602C)\n#define ODCA            PIC32_R (0x86030) /* Port A: open drain configuration */\n#define ODCACLR         PIC32_R (0x86034)\n#define ODCASET         PIC32_R (0x86038)\n#define ODCAINV         PIC32_R (0x8603C)\n\n#define TRISB           PIC32_R (0x86040) /* Port B: mask of inputs */\n#define TRISBCLR        PIC32_R (0x86044)\n#define TRISBSET        PIC32_R (0x86048)\n#define TRISBINV        PIC32_R (0x8604C)\n#define PORTB           PIC32_R (0x86050) /* Port B: read inputs, write outputs */\n#define PORTBCLR        PIC32_R (0x86054)\n#define PORTBSET        PIC32_R (0x86058)\n#define PORTBINV        PIC32_R (0x8605C)\n#define LATB            PIC32_R (0x86060) /* Port B: read/write outputs */\n#define LATBCLR         PIC32_R (0x86064)\n#define LATBSET         PIC32_R (0x86068)\n#define LATBINV         PIC32_R (0x8606C)\n#define ODCB            PIC32_R (0x86070) /* Port B: open drain configuration */\n#define ODCBCLR         PIC32_R (0x86074)\n#define ODCBSET         PIC32_R (0x86078)\n#define ODCBINV         PIC32_R (0x8607C)\n\n#define TRISC           PIC32_R (0x86080) /* Port C: mask of inputs */\n#define TRISCCLR        PIC32_R (0x86084)\n#define TRISCSET        PIC32_R (0x86088)\n#define TRISCINV        PIC32_R (0x8608C)\n#define PORTC           PIC32_R (0x86090) /* Port C: read inputs, write outputs */\n#define PORTCCLR        PIC32_R (0x86094)\n#define PORTCSET        PIC32_R (0x86098)\n#define PORTCINV        PIC32_R (0x8609C)\n#define LATC            PIC32_R (0x860A0) /* Port C: read/write outputs */\n#define LATCCLR         PIC32_R (0x860A4)\n#define LATCSET         PIC32_R (0x860A8)\n#define LATCINV         PIC32_R (0x860AC)\n#define ODCC            PIC32_R (0x860B0) /* Port C: open drain configuration */\n#define ODCCCLR         PIC32_R (0x860B4)\n#define ODCCSET         PIC32_R (0x860B8)\n#define ODCCINV         PIC32_R (0x860BC)\n\n#define TRISD           PIC32_R (0x860C0) /* Port D: mask of inputs */\n#define TRISDCLR        PIC32_R (0x860C4)\n#define TRISDSET        PIC32_R (0x860C8)\n#define TRISDINV        PIC32_R (0x860CC)\n#define PORTD           PIC32_R (0x860D0) /* Port D: read inputs, write outputs */\n#define PORTDCLR        PIC32_R (0x860D4)\n#define PORTDSET        PIC32_R (0x860D8)\n#define PORTDINV        PIC32_R (0x860DC)\n#define LATD            PIC32_R (0x860E0) /* Port D: read/write outputs */\n#define LATDCLR         PIC32_R (0x860E4)\n#define LATDSET         PIC32_R (0x860E8)\n#define LATDINV         PIC32_R (0x860EC)\n#define ODCD            PIC32_R (0x860F0) /* Port D: open drain configuration */\n#define ODCDCLR         PIC32_R (0x860F4)\n#define ODCDSET         PIC32_R (0x860F8)\n#define ODCDINV         PIC32_R (0x860FC)\n\n#define TRISE           PIC32_R (0x86100) /* Port E: mask of inputs */\n#define TRISECLR        PIC32_R (0x86104)\n#define TRISESET        PIC32_R (0x86108)\n#define TRISEINV        PIC32_R (0x8610C)\n#define PORTE           PIC32_R (0x86110) /* Port E: read inputs, write outputs */\n#define PORTECLR        PIC32_R (0x86114)\n#define PORTESET        PIC32_R (0x86118)\n#define PORTEINV        PIC32_R (0x8611C)\n#define LATE            PIC32_R (0x86120) /* Port E: read/write outputs */\n#define LATECLR         PIC32_R (0x86124)\n#define LATESET         PIC32_R (0x86128)\n#define LATEINV         PIC32_R (0x8612C)\n#define ODCE            PIC32_R (0x86130) /* Port E: open drain configuration */\n#define ODCECLR         PIC32_R (0x86134)\n#define ODCESET         PIC32_R (0x86138)\n#define ODCEINV         PIC32_R (0x8613C)\n\n#define TRISF           PIC32_R (0x86140) /* Port F: mask of inputs */\n#define TRISFCLR        PIC32_R (0x86144)\n#define TRISFSET        PIC32_R (0x86148)\n#define TRISFINV        PIC32_R (0x8614C)\n#define PORTF           PIC32_R (0x86150) /* Port F: read inputs, write outputs */\n#define PORTFCLR        PIC32_R (0x86154)\n#define PORTFSET        PIC32_R (0x86158)\n#define PORTFINV        PIC32_R (0x8615C)\n#define LATF            PIC32_R (0x86160) /* Port F: read/write outputs */\n#define LATFCLR         PIC32_R (0x86164)\n#define LATFSET         PIC32_R (0x86168)\n#define LATFINV         PIC32_R (0x8616C)\n#define ODCF            PIC32_R (0x86170) /* Port F: open drain configuration */\n#define ODCFCLR         PIC32_R (0x86174)\n#define ODCFSET         PIC32_R (0x86178)\n#define ODCFINV         PIC32_R (0x8617C)\n\n#define TRISG           PIC32_R (0x86180) /* Port G: mask of inputs */\n#define TRISGCLR        PIC32_R (0x86184)\n#define TRISGSET        PIC32_R (0x86188)\n#define TRISGINV        PIC32_R (0x8618C)\n#define PORTG           PIC32_R (0x86190) /* Port G: read inputs, write outputs */\n#define PORTGCLR        PIC32_R (0x86194)\n#define PORTGSET        PIC32_R (0x86198)\n#define PORTGINV        PIC32_R (0x8619C)\n#define LATG            PIC32_R (0x861A0) /* Port G: read/write outputs */\n#define LATGCLR         PIC32_R (0x861A4)\n#define LATGSET         PIC32_R (0x861A8)\n#define LATGINV         PIC32_R (0x861AC)\n#define ODCG            PIC32_R (0x861B0) /* Port G: open drain configuration */\n#define ODCGCLR         PIC32_R (0x861B4)\n#define ODCGSET         PIC32_R (0x861B8)\n#define ODCGINV         PIC32_R (0x861BC)\n\n#ifndef __ASSEMBLER__\n/*\n * PIC32 port i/o registers.\n */\nstruct gpioreg {\n    volatile unsigned tris;     /* Mask of inputs */\n    volatile unsigned trisclr;\n    volatile unsigned trisset;\n    volatile unsigned trisinv;\n    volatile unsigned port;     /* Read inputs, write outputs */\n    volatile unsigned portclr;\n    volatile unsigned portset;\n    volatile unsigned portinv;\n    volatile unsigned lat;      /* Read/write outputs */\n    volatile unsigned latclr;\n    volatile unsigned latset;\n    volatile unsigned latinv;\n    volatile unsigned odc;      /* Open drain configuration */\n    volatile unsigned odcclr;\n    volatile unsigned odcset;\n    volatile unsigned odcinv;\n};\n#endif\n\n#define CNCON           PIC32_R (0x861C0) /* Interrupt-on-change control */\n#define CNCONCLR        PIC32_R (0x861C4)\n#define CNCONSET        PIC32_R (0x861C8)\n#define CNCONINV        PIC32_R (0x861CC)\n#define CNEN            PIC32_R (0x861D0) /* Input change interrupt enable */\n#define CNENCLR         PIC32_R (0x861D4)\n#define CNENSET         PIC32_R (0x861D8)\n#define CNENINV         PIC32_R (0x861DC)\n#define CNPUE           PIC32_R (0x861E0) /* Input pin pull-up enable */\n#define CNPUECLR        PIC32_R (0x861E4)\n#define CNPUESET        PIC32_R (0x861E8)\n#define CNPUEINV        PIC32_R (0x861EC)\n\n/*--------------------------------------\n * A/D Converter registers.\n */\n#define AD1CON1         PIC32_R (0x9000) /* Control register 1 */\n#define AD1CON1CLR      PIC32_R (0x9004)\n#define AD1CON1SET      PIC32_R (0x9008)\n#define AD1CON1INV      PIC32_R (0x900C)\n#define AD1CON2         PIC32_R (0x9010) /* Control register 2 */\n#define AD1CON2CLR      PIC32_R (0x9014)\n#define AD1CON2SET      PIC32_R (0x9018)\n#define AD1CON2INV      PIC32_R (0x901C)\n#define AD1CON3         PIC32_R (0x9020) /* Control register 3 */\n#define AD1CON3CLR      PIC32_R (0x9024)\n#define AD1CON3SET      PIC32_R (0x9028)\n#define AD1CON3INV      PIC32_R (0x902C)\n#define AD1CHS          PIC32_R (0x9040) /* Channel select */\n#define AD1CHSCLR       PIC32_R (0x9044)\n#define AD1CHSSET       PIC32_R (0x9048)\n#define AD1CHSINV       PIC32_R (0x904C)\n#define AD1CSSL         PIC32_R (0x9050) /* Input scan selection */\n#define AD1CSSLCLR      PIC32_R (0x9054)\n#define AD1CSSLSET      PIC32_R (0x9058)\n#define AD1CSSLINV      PIC32_R (0x905C)\n#define AD1PCFG         PIC32_R (0x9060) /* Port configuration */\n#define AD1PCFGCLR      PIC32_R (0x9064)\n#define AD1PCFGSET      PIC32_R (0x9068)\n#define AD1PCFGINV      PIC32_R (0x906C)\n#define ADC1BUF0        PIC32_R (0x9070) /* Result words */\n#define ADC1BUF1        PIC32_R (0x9080)\n#define ADC1BUF2        PIC32_R (0x9090)\n#define ADC1BUF3        PIC32_R (0x90A0)\n#define ADC1BUF4        PIC32_R (0x90B0)\n#define ADC1BUF5        PIC32_R (0x90C0)\n#define ADC1BUF6        PIC32_R (0x90D0)\n#define ADC1BUF7        PIC32_R (0x90E0)\n#define ADC1BUF8        PIC32_R (0x90F0)\n#define ADC1BUF9        PIC32_R (0x9100)\n#define ADC1BUFA        PIC32_R (0x9110)\n#define ADC1BUFB        PIC32_R (0x9120)\n#define ADC1BUFC        PIC32_R (0x9130)\n#define ADC1BUFD        PIC32_R (0x9140)\n#define ADC1BUFE        PIC32_R (0x9150)\n#define ADC1BUFF        PIC32_R (0x9160)\n\n/*--------------------------------------\n * Parallel master port registers.\n */\n#define PMCON           PIC32_R (0x7000) /* Control */\n#define PMCONCLR        PIC32_R (0x7004)\n#define PMCONSET        PIC32_R (0x7008)\n#define PMCONINV        PIC32_R (0x700C)\n#define PMMODE          PIC32_R (0x7010) /* Mode */\n#define PMMODECLR       PIC32_R (0x7014)\n#define PMMODESET       PIC32_R (0x7018)\n#define PMMODEINV       PIC32_R (0x701C)\n#define PMADDR          PIC32_R (0x7020) /* Address */\n#define PMADDRCLR       PIC32_R (0x7024)\n#define PMADDRSET       PIC32_R (0x7028)\n#define PMADDRINV       PIC32_R (0x702C)\n#define PMDOUT          PIC32_R (0x7030) /* Data output */\n#define PMDOUTCLR       PIC32_R (0x7034)\n#define PMDOUTSET       PIC32_R (0x7038)\n#define PMDOUTINV       PIC32_R (0x703C)\n#define PMDIN           PIC32_R (0x7040) /* Data input */\n#define PMDINCLR        PIC32_R (0x7044)\n#define PMDINSET        PIC32_R (0x7048)\n#define PMDININV        PIC32_R (0x704C)\n#define PMAEN           PIC32_R (0x7050) /* Pin enable */\n#define PMAENCLR        PIC32_R (0x7054)\n#define PMAENSET        PIC32_R (0x7058)\n#define PMAENINV        PIC32_R (0x705C)\n#define PMSTAT          PIC32_R (0x7060) /* Status (slave only) */\n#define PMSTATCLR       PIC32_R (0x7064)\n#define PMSTATSET       PIC32_R (0x7068)\n#define PMSTATINV       PIC32_R (0x706C)\n\n/*\n * PMP Control register.\n */\n#define PIC32_PMCON_RDSP        0x0001 /* Read strobe polarity active-high */\n#define PIC32_PMCON_WRSP        0x0002 /* Write strobe polarity active-high */\n#define PIC32_PMCON_CS1P        0x0008 /* Chip select 0 polarity active-high */\n#define PIC32_PMCON_CS2P        0x0010 /* Chip select 1 polarity active-high */\n#define PIC32_PMCON_ALP         0x0020 /* Address latch polarity active-high */\n#define PIC32_PMCON_CSF         0x00C0 /* Chip select function bitmask: */\n#define PIC32_PMCON_CSF_NONE    0x0000 /* PMCS2 and PMCS1 as A[15:14] */\n#define PIC32_PMCON_CSF_CS2     0x0040 /* PMCS2 as chip select */\n#define PIC32_PMCON_CSF_CS21    0x0080 /* PMCS2 and PMCS1 as chip select */\n#define PIC32_PMCON_PTRDEN      0x0100 /* Read/write strobe port enable */\n#define PIC32_PMCON_PTWREN      0x0200 /* Write enable strobe port enable */\n#define PIC32_PMCON_PMPTTL      0x0400 /* TTL input buffer select */\n#define PIC32_PMCON_ADRMUX      0x1800 /* Address/data mux selection bitmask: */\n#define PIC32_PMCON_ADRMUX_NONE 0x0000 /* Address and data separate */\n#define PIC32_PMCON_ADRMUX_AD   0x0800 /* Lower address on PMD[7:0], high on PMA[15:8] */\n#define PIC32_PMCON_ADRMUX_D8   0x1000 /* All address on PMD[7:0] */\n#define PIC32_PMCON_ADRMUX_D16  0x1800 /* All address on PMD[15:0] */\n#define PIC32_PMCON_SIDL        0x2000 /* Stop in idle */\n#define PIC32_PMCON_FRZ         0x4000 /* Freeze in debug exception */\n#define PIC32_PMCON_ON          0x8000 /* Parallel master port enable */\n\n/*\n * PMP Mode register.\n */\n#define PIC32_PMMODE_WAITE(x)   ((x)<<0) /* Wait states: data hold after RW strobe */\n#define PIC32_PMMODE_WAITM(x)   ((x)<<2) /* Wait states: data RW strobe */\n#define PIC32_PMMODE_WAITB(x)   ((x)<<6) /* Wait states: data setup to RW strobe */\n#define PIC32_PMMODE_MODE       0x0300  /* Mode select bitmask: */\n#define PIC32_PMMODE_MODE_SLAVE 0x0000  /* Legacy slave */\n#define PIC32_PMMODE_MODE_SLENH 0x0100  /* Enhanced slave */\n#define PIC32_PMMODE_MODE_MAST2 0x0200  /* Master mode 2 */\n#define PIC32_PMMODE_MODE_MAST1 0x0300  /* Master mode 1 */\n#define PIC32_PMMODE_MODE16     0x0400  /* 16-bit mode */\n#define PIC32_PMMODE_INCM       0x1800  /* Address increment mode bitmask: */\n#define PIC32_PMMODE_INCM_NONE  0x0000  /* No increment/decrement */\n#define PIC32_PMMODE_INCM_INC   0x0800  /* Increment address */\n#define PIC32_PMMODE_INCM_DEC   0x1000  /* Decrement address */\n#define PIC32_PMMODE_INCM_SLAVE 0x1800  /* Slave auto-increment */\n#define PIC32_PMMODE_IRQM       0x6000  /* Interrupt request bitmask: */\n#define PIC32_PMMODE_IRQM_DIS   0x0000  /* No interrupt generated */\n#define PIC32_PMMODE_IRQM_END   0x2000  /* Interrupt at end of read/write cycle */\n#define PIC32_PMMODE_IRQM_A3    0x4000  /* Interrupt on address 3 */\n#define PIC32_PMMODE_BUSY       0x8000  /* Port is busy */\n\n/*\n * PMP Address register.\n */\n#define PIC32_PMADDR_PADDR      0x3FFF /* Destination address */\n#define PIC32_PMADDR_CS1        0x4000 /* Chip select 1 is active */\n#define PIC32_PMADDR_CS2        0x8000 /* Chip select 2 is active */\n\n/*\n * PMP status register (slave only).\n */\n#define PIC32_PMSTAT_OB0E       0x0001 /* Output buffer 0 empty */\n#define PIC32_PMSTAT_OB1E       0x0002 /* Output buffer 1 empty */\n#define PIC32_PMSTAT_OB2E       0x0004 /* Output buffer 2 empty */\n#define PIC32_PMSTAT_OB3E       0x0008 /* Output buffer 3 empty */\n#define PIC32_PMSTAT_OBUF       0x0040 /* Output buffer underflow */\n#define PIC32_PMSTAT_OBE        0x0080 /* Output buffer empty */\n#define PIC32_PMSTAT_IB0F       0x0100 /* Input buffer 0 full */\n#define PIC32_PMSTAT_IB1F       0x0200 /* Input buffer 1 full */\n#define PIC32_PMSTAT_IB2F       0x0400 /* Input buffer 2 full */\n#define PIC32_PMSTAT_IB3F       0x0800 /* Input buffer 3 full */\n#define PIC32_PMSTAT_IBOV       0x4000 /* Input buffer overflow */\n#define PIC32_PMSTAT_IBF        0x8000 /* Input buffer full */\n\n/*--------------------------------------\n * USB registers.\n */\n#define U1OTGIR         PIC32_R (0x85040) /* OTG interrupt flags */\n#define U1OTGIE         PIC32_R (0x85050) /* OTG interrupt enable */\n#define U1OTGSTAT       PIC32_R (0x85060) /* Comparator and pin status */\n#define U1OTGCON        PIC32_R (0x85070) /* Resistor and pin control */\n#define U1PWRC          PIC32_R (0x85080) /* Power control */\n#define U1IR            PIC32_R (0x85200) /* Pending interrupt */\n#define U1IE            PIC32_R (0x85210) /* Interrupt enable */\n#define U1EIR           PIC32_R (0x85220) /* Pending error interrupt */\n#define U1EIE           PIC32_R (0x85230) /* Error interrupt enable */\n#define U1STAT          PIC32_R (0x85240) /* Status FIFO */\n#define U1CON           PIC32_R (0x85250) /* Control */\n#define U1ADDR          PIC32_R (0x85260) /* Address */\n#define U1BDTP1         PIC32_R (0x85270) /* Buffer descriptor table pointer 1 */\n#define U1FRML          PIC32_R (0x85280) /* Frame counter low */\n#define U1FRMH          PIC32_R (0x85290) /* Frame counter high */\n#define U1TOK           PIC32_R (0x852A0) /* Host control */\n#define U1SOF           PIC32_R (0x852B0) /* SOF counter */\n#define U1BDTP2         PIC32_R (0x852C0) /* Buffer descriptor table pointer 2 */\n#define U1BDTP3         PIC32_R (0x852D0) /* Buffer descriptor table pointer 3 */\n#define U1CNFG1         PIC32_R (0x852E0) /* Debug and idle */\n#define U1EP(n)         PIC32_R (0x85300 + (n << 4)) /* Endpoint control */\n\n/*\n * USB Control register.\n */\n#define PIC32_U1CON_USBEN       0x0001 /* USB module enable (device mode) */\n#define PIC32_U1CON_SOFEN       0x0001 /* SOF sent every 1 ms (host mode) */\n#define PIC32_U1CON_PPBRST      0x0002 /* Ping-pong buffers reset */\n#define PIC32_U1CON_RESUME      0x0004 /* Resume signaling enable */\n#define PIC32_U1CON_HOSTEN      0x0008 /* Host mode enable */\n#define PIC32_U1CON_USBRST      0x0010 /* USB reset */\n#define PIC32_U1CON_PKTDIS      0x0020 /* Packet transfer disable */\n#define PIC32_U1CON_TOKBUSY     0x0020 /* Token busy indicator */\n#define PIC32_U1CON_SE0         0x0040 /* Single ended zero detected */\n#define PIC32_U1CON_JSTATE      0x0080 /* Live differential receiver JSTATE flag */\n\n/*\n * USB Power control register.\n */\n#define PIC32_U1PWRC_USBPWR     0x0001 /* USB operation enable */\n#define PIC32_U1PWRC_USUSPEND   0x0002 /* USB suspend mode */\n#define PIC32_U1PWRC_USLPGRD    0x0010 /* USB sleep entry guard */\n#define PIC32_U1PWRC_UACTPND    0x0080 /* UAB activity pending */\n\n/*\n * USB Pending interrupt register.\n * USB Interrupt enable register.\n */\n#define PIC32_U1I_DETACH        0x0001 /* Detach (host mode) */\n#define PIC32_U1I_URST          0x0001 /* USB reset (device mode) */\n#define PIC32_U1I_UERR          0x0002 /* USB error condition */\n#define PIC32_U1I_SOF           0x0004 /* SOF token  */\n#define PIC32_U1I_TRN           0x0008 /* Token processing complete */\n#define PIC32_U1I_IDLE          0x0010 /* Idle detect */\n#define PIC32_U1I_RESUME        0x0020 /* Resume */\n#define PIC32_U1I_ATTACH        0x0040 /* Peripheral attach */\n#define PIC32_U1I_STALL         0x0080 /* STALL handshake */\n\n/*\n * USB OTG interrupt flags register.\n * USB OTG interrupt enable register.\n */\n#define PIC32_U1OTGI_VBUSVD     0x0001 /* A-device Vbus change */\n#define PIC32_U1OTGI_SESEND     0x0004 /* B-device Vbus change */\n#define PIC32_U1OTGI_SESVD      0x0008 /* Session valid change */\n#define PIC32_U1OTGI_ACTV       0x0010 /* Bus activity indicator */\n#define PIC32_U1OTGI_LSTATE     0x0020 /* Line state stable */\n#define PIC32_U1OTGI_T1MSEC     0x0040 /* 1 millisecond timer expired */\n#define PIC32_U1OTGI_ID         0x0080 /* ID state change */\n\n#define PIC32_U1OTGSTAT_VBUSVD  0x0001 /*  */\n#define PIC32_U1OTGSTAT_SESEND  0x0004 /*  */\n#define PIC32_U1OTGSTAT_SESVD   0x0008 /*  */\n#define PIC32_U1OTGSTAT_LSTATE  0x0020 /*  */\n#define PIC32_U1OTGSTAT_ID      0x0080 /*  */\n\n#define PIC32_U1OTGCON_VBUSDIS  0x0001 /*  */\n#define PIC32_U1OTGCON_VBUSCHG  0x0002 /*  */\n#define PIC32_U1OTGCON_OTGEN    0x0004 /*  */\n#define PIC32_U1OTGCON_VBUSON   0x0008 /*  */\n#define PIC32_U1OTGCON_DMPULDWN 0x0010 /*  */\n#define PIC32_U1OTGCON_DPPULDWN 0x0020 /*  */\n#define PIC32_U1OTGCON_DMPULUP  0x0040 /*  */\n#define PIC32_U1OTGCON_DPPULUP  0x0080 /*  */\n\n#define PIC32_U1EI_PID          0x0001 /*  */\n#define PIC32_U1EI_CRC5         0x0002 /*  */\n#define PIC32_U1EI_EOF          0x0002 /*  */\n#define PIC32_U1EI_CRC16        0x0004 /*  */\n#define PIC32_U1EI_DFN8         0x0008 /*  */\n#define PIC32_U1EI_BTO          0x0010 /*  */\n#define PIC32_U1EI_DMA          0x0020 /*  */\n#define PIC32_U1EI_BMX          0x0040 /*  */\n#define PIC32_U1EI_BTS          0x0080 /*  */\n\n#define PIC32_U1STAT_PPBI       0x0004 /*  */\n#define PIC32_U1STAT_DIR        0x0008 /*  */\n#define PIC32_U1STAT_ENDPT(x)   (((x) >> 4) & 0xF) /*  */\n\n#define PIC32_U1ADDR_DEVADDR    0x007F /*  */\n#define PIC32_U1ADDR_USBADDR0   0x0001 /*  */\n#define PIC32_U1ADDR_DEVADDR1   0x0002 /*  */\n#define PIC32_U1ADDR_DEVADDR2   0x0004 /*  */\n#define PIC32_U1ADDR_DEVADDR3   0x0008 /*  */\n#define PIC32_U1ADDR_DEVADDR4   0x0010 /*  */\n#define PIC32_U1ADDR_DEVADDR5   0x0020 /*  */\n#define PIC32_U1ADDR_DEVADDR6   0x0040 /*  */\n#define PIC32_U1ADDR_LSPDEN     0x0080 /*  */\n\n#define PIC32_U1FRML_FRM0       0x0001 /*  */\n#define PIC32_U1FRML_FRM1       0x0002 /*  */\n#define PIC32_U1FRML_FRM2       0x0004 /*  */\n#define PIC32_U1FRML_FRM3       0x0008 /*  */\n#define PIC32_U1FRML_FRM4       0x0010 /*  */\n#define PIC32_U1FRML_FRM5       0x0020 /*  */\n#define PIC32_U1FRML_FRM6       0x0040 /*  */\n#define PIC32_U1FRML_FRM7       0x0080 /*  */\n\n#define PIC32_U1FRMH_FRM8       0x0001 /*  */\n#define PIC32_U1FRMH_FRM9       0x0002 /*  */\n#define PIC32_U1FRMH_FRM10      0x0004 /*  */\n\n#define PIC32_U1TOK_EP0         0x0001 /*  */\n#define PIC32_U1TOK_EP          0x000F /*  */\n#define PIC32_U1TOK_EP1         0x0002 /*  */\n#define PIC32_U1TOK_EP2         0x0004 /*  */\n#define PIC32_U1TOK_EP3         0x0008 /*  */\n#define PIC32_U1TOK_PID0        0x0010 /*  */\n#define PIC32_U1TOK_PID         0x00F0 /*  */\n#define PIC32_U1TOK_PID1        0x0020 /*  */\n#define PIC32_U1TOK_PID2        0x0040 /*  */\n#define PIC32_U1TOK_PID3        0x0080 /*  */\n\n#define PIC32_U1CNFG1_USBSIDL   0x0010 /*  */\n#define PIC32_U1CNFG1_USBFRZ    0x0020 /*  */\n#define PIC32_U1CNFG1_UOEMON    0x0040 /*  */\n#define PIC32_U1CNFG1_UTEYE     0x0080 /*  */\n\n#define PIC32_U1EP_EPHSHK       0x0001 /*  */\n#define PIC32_U1EP_EPSTALL      0x0002 /*  */\n#define PIC32_U1EP_EPTXEN       0x0004 /*  */\n#define PIC32_U1EP_EPRXEN       0x0008 /*  */\n#define PIC32_U1EP_EPCONDIS     0x0010 /*  */\n#define PIC32_U1EP_RETRYDIS     0x0040 /*  */\n#define PIC32_U1EP_LSPD         0x0080 /*  */\n\n/* DB status field values */\n#define PIC32_DB_BSTALL         (1 << 2)\n#define PIC32_DB_DTS            (1 << 3)\n#define PIC32_DB_NINC           (1 << 4)\n#define PIC32_DB_KEEP           (1 << 5)\n#define PIC32_DB_DATA1          (1 << 6)\n#define PIC32_DB_UOWN           (1 << 7)\n#define PIC32_DB_GET_PID(x)     (((x) >> 2) & 0xF)\n#define PIC32_DB_SET_PID(x)     (((x) & 0xF) << 2)\n#define PIC32_DB_GET_COUNT(x)   (((x) >> 16) & 0x3FF)\n#define PIC32_DB_SET_COUNT(x)   (((x) & 0x3FF) << 16)\n\n/*--------------------------------------\n * SPI registers.\n */\n#ifdef PIC32MX4\n#define SPI1CON         PIC32_R (0x5800) /* Control */\n#define SPI1CONCLR      PIC32_R (0x5804)\n#define SPI1CONSET      PIC32_R (0x5808)\n#define SPI1CONINV      PIC32_R (0x580C)\n#define SPI1STAT        PIC32_R (0x5810) /* Status */\n#define SPI1STATCLR     PIC32_R (0x5814)\n#define SPI1STATSET     PIC32_R (0x5818)\n#define SPI1STATINV     PIC32_R (0x581C)\n#define SPI1BUF         PIC32_R (0x5820) /* Transmit and receive buffer */\n#define SPI1BRG         PIC32_R (0x5830) /* Baud rate generator */\n#define SPI1BRGCLR      PIC32_R (0x5834)\n#define SPI1BRGSET      PIC32_R (0x5838)\n#define SPI1BRGINV      PIC32_R (0x583C)\n#endif\n#ifdef PIC32MX7\n#define SPI3CON         PIC32_R (0x5800) /* Control */\n#define SPI3CONCLR      PIC32_R (0x5804)\n#define SPI3CONSET      PIC32_R (0x5808)\n#define SPI3CONINV      PIC32_R (0x580C)\n#define SPI3STAT        PIC32_R (0x5810) /* Status */\n#define SPI3STATCLR     PIC32_R (0x5814)\n#define SPI3STATSET     PIC32_R (0x5818)\n#define SPI3STATINV     PIC32_R (0x581C)\n#define SPI3BUF         PIC32_R (0x5820) /* Transmit and receive buffer */\n#define SPI3BRG         PIC32_R (0x5830) /* Baud rate generator */\n#define SPI3BRGCLR      PIC32_R (0x5834)\n#define SPI3BRGSET      PIC32_R (0x5838)\n#define SPI3BRGINV      PIC32_R (0x583C)\n\n#define SPI4CON         PIC32_R (0x5C00) /* Control */\n#define SPI4CONCLR      PIC32_R (0x5C04)\n#define SPI4CONSET      PIC32_R (0x5C08)\n#define SPI4CONINV      PIC32_R (0x5C0C)\n#define SPI4STAT        PIC32_R (0x5C10) /* Status */\n#define SPI4STATCLR     PIC32_R (0x5C14)\n#define SPI4STATSET     PIC32_R (0x5C18)\n#define SPI4STATINV     PIC32_R (0x5C1C)\n#define SPI4BUF         PIC32_R (0x5C20) /* Transmit and receive buffer */\n#define SPI4BRG         PIC32_R (0x5C30) /* Baud rate generator */\n#define SPI4BRGCLR      PIC32_R (0x5C34)\n#define SPI4BRGSET      PIC32_R (0x5C38)\n#define SPI4BRGINV      PIC32_R (0x5C3C)\n\n#define SPI1CON         PIC32_R (0x5E00) /* Control */\n#define SPI1CONCLR      PIC32_R (0x5E04)\n#define SPI1CONSET      PIC32_R (0x5E08)\n#define SPI1CONINV      PIC32_R (0x5E0C)\n#define SPI1STAT        PIC32_R (0x5E10) /* Status */\n#define SPI1STATCLR     PIC32_R (0x5E14)\n#define SPI1STATSET     PIC32_R (0x5E18)\n#define SPI1STATINV     PIC32_R (0x5E1C)\n#define SPI1BUF         PIC32_R (0x5E20) /* Transmit and receive buffer */\n#define SPI1BRG         PIC32_R (0x5E30) /* Baud rate generator */\n#define SPI1BRGCLR      PIC32_R (0x5E34)\n#define SPI1BRGSET      PIC32_R (0x5E38)\n#define SPI1BRGINV      PIC32_R (0x5E3C)\n#endif\n\n#define SPI2CON         PIC32_R (0x5A00) /* Control */\n#define SPI2CONCLR      PIC32_R (0x5A04)\n#define SPI2CONSET      PIC32_R (0x5A08)\n#define SPI2CONINV      PIC32_R (0x5A0C)\n#define SPI2STAT        PIC32_R (0x5A10) /* Status */\n#define SPI2STATCLR     PIC32_R (0x5A14)\n#define SPI2STATSET     PIC32_R (0x5A18)\n#define SPI2STATINV     PIC32_R (0x5A1C)\n#define SPI2BUF         PIC32_R (0x5A20) /* Transmit and receive buffer */\n#define SPI2BRG         PIC32_R (0x5A30) /* Baud rate generator */\n#define SPI2BRGCLR      PIC32_R (0x5A34)\n#define SPI2BRGSET      PIC32_R (0x5A38)\n#define SPI2BRGINV      PIC32_R (0x5A3C)\n\n#ifndef __ASSEMBLER__\nstruct spireg {\n    volatile unsigned con;      /* Control */\n    volatile unsigned conclr;\n    volatile unsigned conset;\n    volatile unsigned coninv;\n    volatile unsigned stat;     /* Status */\n    volatile unsigned statclr;\n    volatile unsigned statset;\n    volatile unsigned statinv;\n    volatile unsigned buf;      /* Transmit and receive buffer */\n    volatile unsigned unused1;\n    volatile unsigned unused2;\n    volatile unsigned unused3;\n    volatile unsigned brg;      /* Baud rate generator */\n    volatile unsigned brgclr;\n    volatile unsigned brgset;\n    volatile unsigned brginv;\n};\n#endif\n\n/*\n * SPI Control register.\n */\n#define PIC32_SPICON_MSTEN      0x00000020      /* Master mode */\n#define PIC32_SPICON_CKP        0x00000040      /* Idle clock is high level */\n#define PIC32_SPICON_SSEN       0x00000080      /* Slave mode: SSx pin enable */\n#define PIC32_SPICON_CKE        0x00000100      /* Output data changes on\n                                                 * transition from active clock\n                                                 * state to Idle clock state */\n#define PIC32_SPICON_SMP        0x00000200      /* Master mode: input data sampled\n                                                 * at end of data output time. */\n#define PIC32_SPICON_MODE16     0x00000400      /* 16-bit data width */\n#define PIC32_SPICON_MODE32     0x00000800      /* 32-bit data width */\n#define PIC32_SPICON_DISSDO     0x00001000      /* SDOx pin is not used */\n#define PIC32_SPICON_SIDL       0x00002000      /* Stop in Idle mode */\n#define PIC32_SPICON_FRZ        0x00004000      /* Freeze in Debug mode */\n#define PIC32_SPICON_ON         0x00008000      /* SPI Peripheral is enabled */\n#define PIC32_SPICON_ENHBUF     0x00010000      /* Enhanced buffer enable */\n#define PIC32_SPICON_SPIFE      0x00020000      /* Frame synchronization pulse\n                                                 * coincides with the first bit clock */\n#define PIC32_SPICON_FRMPOL     0x20000000      /* Frame pulse is active-high */\n#define PIC32_SPICON_FRMSYNC    0x40000000      /* Frame sync pulse input (Slave mode) */\n#define PIC32_SPICON_FRMEN      0x80000000      /* Framed SPI support */\n\n/*\n * SPI Status register.\n */\n#define PIC32_SPISTAT_SPIRBF    0x00000001      /* Receive buffer is full */\n#define PIC32_SPISTAT_SPITBF    0x00000002      /* Transmit buffer is full */\n#define PIC32_SPISTAT_SPITBE    0x00000008      /* Transmit buffer is empty */\n#define PIC32_SPISTAT_SPIRBE    0x00000020      /* Receive buffer is empty */\n#define PIC32_SPISTAT_SPIROV    0x00000040      /* Receive overflow flag */\n#define PIC32_SPISTAT_SPIBUSY   0x00000800      /* SPI is busy */\n\n/*--------------------------------------\n * DMA controller registers.\n */\n#define DMACON          PIC32_R (0x83000)       /* DMA Control */\n#define DMACONCLR       PIC32_R (0x83004)\n#define DMACONSET       PIC32_R (0x83008)\n#define DMACONINV       PIC32_R (0x8300C)\n#define DMASTAT         PIC32_R (0x83010)       /* DMA Status */\n#define DMAADDR         PIC32_R (0x83020)       /* DMA Address */\n/* TODO: other DMA registers. */\n\n/*--------------------------------------\n * System controller registers.\n */\n#define OSCCON          PIC32_R (0xf000)        /* Oscillator Control */\n#define OSCCONCLR       PIC32_R (0xf004)\n#define OSCCONSET       PIC32_R (0xf008)\n#define OSCCONINV       PIC32_R (0xf00C)\n#define OSCTUN          PIC32_R (0xf010)\n#define DDPCON          PIC32_R (0xf200)        /* Debug Data Port Control */\n#define DEVID           PIC32_R (0xf220)\n#define SYSKEY          PIC32_R (0xf230)\n#define RCON            PIC32_R (0xf600)\n#define RCONCLR         PIC32_R (0xf604)\n#define RCONSET         PIC32_R (0xf608)\n#define RCONINV         PIC32_R (0xf60C)\n#define RSWRST          PIC32_R (0xf610)\n#define RSWRSTCLR       PIC32_R (0xf614)\n#define RSWRSTSET       PIC32_R (0xf618)\n#define RSWRSTINV       PIC32_R (0xf61C)\n\n/*\n * Oscillator control register.\n */\n#define PIC32_OSCCON_OSWEN      0x00000001 /* Oscillator switch enable */\n#define PIC32_OSCCON_SOSCEN     0x00000002 /* Secondary oscillator enable */\n#define PIC32_OSCCON_UFRCEN     0x00000004 /* USB FRC clock enable */\n#define PIC32_OSCCON_CF         0x00000008 /* Clock fail detect */\n#define PIC32_OSCCON_SLPEN      0x00000010 /* Sleep mode enable */\n#define PIC32_OSCCON_LOCK       0x00000020 /* PLL lock status */\n#define PIC32_OSCCON_ULOCK      0x00000040 /* USB PLL lock status */\n#define PIC32_OSCCON_CLKLOCK    0x00000080 /* Clock selection lock enable */\n#define PIC32_OSCCON_NOSC       0x00000700 /* New oscillator selection */\n#define PIC32_OSCCON_COSC       0x00007000 /* Current oscillator selection */\n#define PIC32_OSCCON_PLLMULT    0x00070000 /* PLL multiplier */\n#define PIC32_OSCCON_PBDIV_MASK 0x00180000 /* Peripheral bus clock divisor */\n#define PIC32_OSCCON_PBDIV_1    0x00000000 /* SYSCLK / 1 */\n#define PIC32_OSCCON_PBDIV_2    0x00080000 /* SYSCLK / 2 */\n#define PIC32_OSCCON_PBDIV_4    0x00100000 /* SYSCLK / 4 */\n#define PIC32_OSCCON_PBDIV_8    0x00180000 /* SYSCLK / 8 */\n#define PIC32_OSCCON_SOSCRDY    0x00400000 /* Secondary oscillator ready */\n#define PIC32_OSCCON_FRCDIV     0x07000000 /* Fast internal RC clock divider */\n#define PIC32_OSCCON_PLLODIV    0x38000000 /* Output divider for PLL */\n\n/*\n * Reset control register.\n */\n#define PIC32_RCON_POR          0x00000001\n#define PIC32_RCON_BOR          0x00000002\n#define PIC32_RCON_IDLE         0x00000004\n#define PIC32_RCON_SLEEP        0x00000008\n#define PIC32_RCON_WDTO         0x00000010\n#define PIC32_RCON_SWR          0x00000040\n#define PIC32_RCON_EXTR         0x00000080\n#define PIC32_RCON_VREGS        0x00000100\n#define PIC32_RCON_CMR          0x00000200\n\n/*--------------------------------------\n * Prefetch cache controller registers.\n */\n#define CHECON          PIC32_R (0x84000)       /* Prefetch cache control */\n#define CHECONCLR       PIC32_R (0x84004)\n#define CHECONSET       PIC32_R (0x84008)\n#define CHECONINV       PIC32_R (0x8400C)\n/* TODO: other prefetch registers. */\n\n/*--------------------------------------\n * Bus matrix control registers.\n */\n#define BMXCON          PIC32_R (0x82000)       /* Memory configuration */\n#define BMXCONCLR       PIC32_R (0x82004)\n#define BMXCONSET       PIC32_R (0x82008)\n#define BMXCONINV       PIC32_R (0x8200C)\n#define BMXDKPBA        PIC32_R (0x82010)       /* Data RAM kernel program base address */\n#define BMXDUDBA        PIC32_R (0x82020)       /* Data RAM user data base address */\n#define BMXDUPBA        PIC32_R (0x82030)       /* Data RAM user program base address */\n#define BMXDRMSZ        PIC32_R (0x82040)       /* Data RAM size */\n#define BMXPUPBA        PIC32_R (0x82050)       /* Program Flash user program base address */\n#define BMXPFMSZ        PIC32_R (0x82060)       /* Program Flash size */\n#define BMXBOOTSZ       PIC32_R (0x82070)       /* Boot Flash size */\n\n/*--------------------------------------\n * Non-volatile memory control registers.\n */\n#define NVMCON          PIC32_R (0x0F400)\n#define NVMCONCLR       PIC32_R (0x0F404)\n#define NVMCONSET       PIC32_R (0x0F408)\n#define NVMCONINV       PIC32_R (0x0F40C)\n#define NVMKEY          PIC32_R (0x0F410)\n#define NVMADDR         PIC32_R (0x0F420)\n#define NVMADDRCLR      PIC32_R (0x0F424)\n#define NVMADDRSET      PIC32_R (0x0F428)\n#define NVMADDRINV      PIC32_R (0x0F42C)\n#define NVMDATA         PIC32_R (0x0F430)\n#define NVMSRCADDR      PIC32_R (0x0F440)\n\n#define PIC32_NVMCON_NVMOP      0x0000000F\n#define PIC32_NVMCON_NOP                 0 /* No operation */\n#define PIC32_NVMCON_WORD_PGM            1 /* Word program */\n#define PIC32_NVMCON_ROW_PGM             3 /* Row program */\n#define PIC32_NVMCON_PAGE_ERASE          4 /* Page erase */\n\n#define PIC32_NVMCON_LVDSTAT    0x00000800\n#define PIC32_NVMCON_LVDERR     0x00001000\n#define PIC32_NVMCON_WRERR      0x00002000\n#define PIC32_NVMCON_WREN       0x00004000\n#define PIC32_NVMCON_WR         0x00008000\n\n\n/*\n * Timer2 registers\n */\n#define T2CON           PIC32_R (0x0800)\n#define T2CONSET        PIC32_R (0x0808)\n#define TMR2            PIC32_R (0x0810)\n#define PR2             PIC32_R (0x0820)\n\n/*\n * Output compare registers\n */\n#define OC1CON          PIC32_R (0x3000)\n#define OC1R            PIC32_R (0x3010)\n#define OC1RS           PIC32_R (0x3020)\n#define OC4CON          PIC32_R (0x3600)\n#define OC4R            PIC32_R (0x3610)\n#define OC4RS           PIC32_R (0x3620)\n\n#define BLRKEY      *(volatile unsigned*)(0x80000000)\n\n/*--------------------------------------\n * Configuration registers.\n */\n#define DEVCFG0         *(volatile unsigned*)0x9fc02ffc\n#define DEVCFG1         *(volatile unsigned*)0x9fc02ff8\n#define DEVCFG2         *(volatile unsigned*)0x9fc02ff4\n#define DEVCFG3         *(volatile unsigned*)0x9fc02ff0\n\n#define PIC32_DEVCFG(cfg0, cfg1, cfg2, cfg3) \\\n    asm (\".section .config\"); \\\n    unsigned __DEVCFG0 __attribute__ ((section (\".config0\"))) = (cfg0) ^ 0x7fffffff; \\\n    unsigned __DEVCFG1 __attribute__ ((section (\".config1\"))) = (cfg1) | DEVCFG1_UNUSED; \\\n    unsigned __DEVCFG2 __attribute__ ((section (\".config2\"))) = (cfg2) | DEVCFG2_UNUSED; \\\n    unsigned __DEVCFG3 __attribute__ ((section (\".config3\"))) = (cfg3) | DEVCFG3_UNUSED\n\n/*\n * Config0 register at 1fc02ffc, inverted.\n */\n#define DEVCFG0_DEBUG_MASK      0x00000003 /* Debugger enable bits */\n#define DEVCFG0_DEBUG_DISABLED  0x00000000 /* Debugger disabled */\n#define DEVCFG0_DEBUG_ENABLED   0x00000002 /* Debugger enabled */\n#define DEVCFG0_ICESEL          0x00000008 /* Use PGC1/PGD1 (default PGC2/PGD2) */\n#define DEVCFG0_PWP_MASK        0x000ff000 /* Program flash write protect */\n#define DEVCFG0_BWP             0x01000000 /* Boot flash write protect */\n#define DEVCFG0_CP              0x10000000 /* Code protect */\n\n/*\n * Config1 register at 1fc02ff8.\n */\n#define DEVCFG1_UNUSED          0xff600858\n#define DEVCFG1_FNOSC_MASK      0x00000007 /* Oscillator selection */\n#define DEVCFG1_FNOSC_FRC       0x00000000 /* Fast RC */\n#define DEVCFG1_FNOSC_FRCDIVPLL 0x00000001 /* Fast RC with divide-by-N and PLL */\n#define DEVCFG1_FNOSC_PRI       0x00000002 /* Primary oscillator XT, HS, EC */\n#define DEVCFG1_FNOSC_PRIPLL    0x00000003 /* Primary with PLL */\n#define DEVCFG1_FNOSC_SEC       0x00000004 /* Secondary oscillator */\n#define DEVCFG1_FNOSC_LPRC      0x00000005 /* Low-power RC */\n#define DEVCFG1_FNOSC_FRCDIV    0x00000007 /* Fast RC with divide-by-N */\n#define DEVCFG1_FSOSCEN         0x00000020 /* Secondary oscillator enable */\n#define DEVCFG1_IESO            0x00000080 /* Internal-external switch over */\n#define DEVCFG1_POSCMOD_MASK    0x00000300 /* Primary oscillator config */\n#define DEVCFG1_POSCMOD_EXT     0x00000000 /* External mode */\n#define DEVCFG1_POSCMOD_XT      0x00000100 /* XT oscillator */\n#define DEVCFG1_POSCMOD_HS      0x00000200 /* HS oscillator */\n#define DEVCFG1_POSCMOD_DISABLE 0x00000300 /* Disabled */\n#define DEVCFG1_OSCIOFNC        0x00000400 /* CLKO output active */\n#define DEVCFG1_FPBDIV_MASK     0x00003000 /* Peripheral bus clock divisor */\n#define DEVCFG1_FPBDIV_1        0x00000000 /* SYSCLK / 1 */\n#define DEVCFG1_FPBDIV_2        0x00001000 /* SYSCLK / 2 */\n#define DEVCFG1_FPBDIV_4        0x00002000 /* SYSCLK / 4 */\n#define DEVCFG1_FPBDIV_8        0x00003000 /* SYSCLK / 8 */\n#define DEVCFG1_FCKM_DISABLE    0x00004000 /* Fail-safe clock monitor disable */\n#define DEVCFG1_FCKS_DISABLE    0x00008000 /* Clock switching disable */\n#define DEVCFG1_WDTPS_MASK      0x001f0000 /* Watchdog postscale */\n#define DEVCFG1_WDTPS_1         0x00000000 /* 1:1 */\n#define DEVCFG1_WDTPS_2         0x00010000 /* 1:2 */\n#define DEVCFG1_WDTPS_4         0x00020000 /* 1:4 */\n#define DEVCFG1_WDTPS_8         0x00030000 /* 1:8 */\n#define DEVCFG1_WDTPS_16        0x00040000 /* 1:16 */\n#define DEVCFG1_WDTPS_32        0x00050000 /* 1:32 */\n#define DEVCFG1_WDTPS_64        0x00060000 /* 1:64 */\n#define DEVCFG1_WDTPS_128       0x00070000 /* 1:128 */\n#define DEVCFG1_WDTPS_256       0x00080000 /* 1:256 */\n#define DEVCFG1_WDTPS_512       0x00090000 /* 1:512 */\n#define DEVCFG1_WDTPS_1024      0x000a0000 /* 1:1024 */\n#define DEVCFG1_WDTPS_2048      0x000b0000 /* 1:2048 */\n#define DEVCFG1_WDTPS_4096      0x000c0000 /* 1:4096 */\n#define DEVCFG1_WDTPS_8192      0x000d0000 /* 1:8192 */\n#define DEVCFG1_WDTPS_16384     0x000e0000 /* 1:16384 */\n#define DEVCFG1_WDTPS_32768     0x000f0000 /* 1:32768 */\n#define DEVCFG1_WDTPS_65536     0x00100000 /* 1:65536 */\n#define DEVCFG1_WDTPS_131072    0x00110000 /* 1:131072 */\n#define DEVCFG1_WDTPS_262144    0x00120000 /* 1:262144 */\n#define DEVCFG1_WDTPS_524288    0x00130000 /* 1:524288 */\n#define DEVCFG1_WDTPS_1048576   0x00140000 /* 1:1048576 */\n#define DEVCFG1_FWDTEN          0x00800000 /* Watchdog enable */\n#define WDTCON      PIC32_R (0x0000)   /* Watchdog timer control */\n#define WDTCONCLR   PIC32_R (0x0004)   /* Watchdog timer control */\n#define WDTCONSET   PIC32_R (0x0008)   /* Watchdog timer control */\n\n\n/*\n * Config2 register at 1fc02ff4.\n */\n#define DEVCFG2_UNUSED          0xfff87888\n#define DEVCFG2_FPLLIDIV_MASK   0x00000007 /* PLL input divider */\n#define DEVCFG2_FPLLIDIV_1      0x00000000 /* 1x */\n#define DEVCFG2_FPLLIDIV_2      0x00000001 /* 2x */\n#define DEVCFG2_FPLLIDIV_3      0x00000002 /* 3x */\n#define DEVCFG2_FPLLIDIV_4      0x00000003 /* 4x */\n#define DEVCFG2_FPLLIDIV_5      0x00000004 /* 5x */\n#define DEVCFG2_FPLLIDIV_6      0x00000005 /* 6x */\n#define DEVCFG2_FPLLIDIV_10     0x00000006 /* 10x */\n#define DEVCFG2_FPLLIDIV_12     0x00000007 /* 12x */\n#define DEVCFG2_FPLLMUL_MASK    0x00000070 /* PLL multiplier */\n#define DEVCFG2_FPLLMUL_15      0x00000000 /* 15x */\n#define DEVCFG2_FPLLMUL_16      0x00000010 /* 16x */\n#define DEVCFG2_FPLLMUL_17      0x00000020 /* 17x */\n#define DEVCFG2_FPLLMUL_18      0x00000030 /* 18x */\n#define DEVCFG2_FPLLMUL_19      0x00000040 /* 19x */\n#define DEVCFG2_FPLLMUL_20      0x00000050 /* 20x */\n#define DEVCFG2_FPLLMUL_21      0x00000060 /* 21x */\n#define DEVCFG2_FPLLMUL_24      0x00000070 /* 24x */\n#define DEVCFG2_UPLLIDIV_MASK   0x00000700 /* USB PLL input divider */\n#define DEVCFG2_UPLLIDIV_1      0x00000000 /* 1x */\n#define DEVCFG2_UPLLIDIV_2      0x00000100 /* 2x */\n#define DEVCFG2_UPLLIDIV_3      0x00000200 /* 3x */\n#define DEVCFG2_UPLLIDIV_4      0x00000300 /* 4x */\n#define DEVCFG2_UPLLIDIV_5      0x00000400 /* 5x */\n#define DEVCFG2_UPLLIDIV_6      0x00000500 /* 6x */\n#define DEVCFG2_UPLLIDIV_10     0x00000600 /* 10x */\n#define DEVCFG2_UPLLIDIV_12     0x00000700 /* 12x */\n#define DEVCFG2_UPLLDIS         0x00008000 /* Disable USB PLL */\n#define DEVCFG2_FPLLODIV_MASK   0x00070000 /* Default postscaler for PLL */\n#define DEVCFG2_FPLLODIV_1      0x00000000 /* 1x */\n#define DEVCFG2_FPLLODIV_2      0x00010000 /* 2x */\n#define DEVCFG2_FPLLODIV_4      0x00020000 /* 4x */\n#define DEVCFG2_FPLLODIV_8      0x00030000 /* 8x */\n#define DEVCFG2_FPLLODIV_16     0x00040000 /* 16x */\n#define DEVCFG2_FPLLODIV_32     0x00050000 /* 32x */\n#define DEVCFG2_FPLLODIV_64     0x00060000 /* 64x */\n#define DEVCFG2_FPLLODIV_256    0x00070000 /* 256x */\n\n/*\n * Config3 register at 1fc02ff0.\n */\n#define DEVCFG3_UNUSED          0x38f80000\n#define DEVCFG3_USERID_MASK     0x0000ffff /* User-defined ID */\n#define DEVCFG3_USERID(x)       ((x) & 0xffff)\n#define DEVCFG3_FSRSSEL_MASK    0x00070000 /* SRS select */\n#define DEVCFG3_FSRSSEL_ALL     0x00000000 /* All irqs assigned to shadow set */\n#define DEVCFG3_FSRSSEL_1       0x00010000 /* Assign irq priority 1 to shadow set */\n#define DEVCFG3_FSRSSEL_2       0x00020000 /* Assign irq priority 2 to shadow set */\n#define DEVCFG3_FSRSSEL_3       0x00030000 /* Assign irq priority 3 to shadow set */\n#define DEVCFG3_FSRSSEL_4       0x00040000 /* Assign irq priority 4 to shadow set */\n#define DEVCFG3_FSRSSEL_5       0x00050000 /* Assign irq priority 5 to shadow set */\n#define DEVCFG3_FSRSSEL_6       0x00060000 /* Assign irq priority 6 to shadow set */\n#define DEVCFG3_FSRSSEL_7       0x00070000 /* Assign irq priority 7 to shadow set */\n#define DEVCFG3_FMIIEN          0x01000000 /* Ethernet MII enable */\n#define DEVCFG3_FETHIO          0x02000000 /* Ethernet pins default */\n#define DEVCFG3_FCANIO          0x04000000 /* CAN pins default */\n#define DEVCFG3_FUSBIDIO        0x40000000 /* USBID pin: controlled by USB */\n#define DEVCFG3_FVBUSONIO       0x80000000 /* VBuson pin: controlled by USB */\n\n/*--------------------------------------\n * Interrupt controller registers.\n */\n#define INTCON          PIC32_R (0x81000)       /* Interrupt Control */\n#define INTCONCLR       PIC32_R (0x81004)\n#define INTCONSET       PIC32_R (0x81008)\n#define INTCONINV       PIC32_R (0x8100C)\n#define INTSTAT         PIC32_R (0x81010)       /* Interrupt Status */\n#define IPTMR           PIC32_R (0x81020)       /* Temporal Proximity Timer */\n#define IPTMRCLR        PIC32_R (0x81024)\n#define IPTMRSET        PIC32_R (0x81028)\n#define IPTMRINV        PIC32_R (0x8102C)\n#define IFS(n)          PIC32_R (0x81030+((n)<<4)) /* IFS(0..2) - Interrupt Flag Status */\n#define IFSCLR(n)       PIC32_R (0x81034+((n)<<4))\n#define IFSSET(n)       PIC32_R (0x81038+((n)<<4))\n#define IFSINV(n)       PIC32_R (0x8103C+((n)<<4))\n#define IEC(n)          PIC32_R (0x81060+((n)<<4)) /* IEC(0..2) - Interrupt Enable Control */\n#define IECCLR(n)       PIC32_R (0x81064+((n)<<4))\n#define IECSET(n)       PIC32_R (0x81068+((n)<<4))\n#define IECINV(n)       PIC32_R (0x8106C+((n)<<4))\n#define IPC(n)          PIC32_R (0x81090+((n)<<4)) /* IPC(0..12) - Interrupt Priority Control */\n#define IPCCLR(n)       PIC32_R (0x81094+((n)<<4))\n#define IPCSET(n)       PIC32_R (0x81098+((n)<<4))\n#define IPCINV(n)       PIC32_R (0x8109C+((n)<<4))\n\n/*\n * Interrupt Control register.\n */\n#define PIC32_INTCON_INT0EP     0x0001  /* External interrupt 0 polarity rising edge */\n#define PIC32_INTCON_INT1EP     0x0002  /* External interrupt 1 polarity rising edge */\n#define PIC32_INTCON_INT2EP     0x0004  /* External interrupt 2 polarity rising edge */\n#define PIC32_INTCON_INT3EP     0x0008  /* External interrupt 3 polarity rising edge */\n#define PIC32_INTCON_INT4EP     0x0010  /* External interrupt 4 polarity rising edge */\n#define PIC32_INTCON_TPC(x)     ((x)<<8) /* Temporal proximity group priority */\n#define PIC32_INTCON_MVEC       0x1000  /* Multi-vectored mode */\n#define PIC32_INTCON_FRZ        0x4000  /* Freeze in debug mode */\n#define PIC32_INTCON_SS0        0x8000  /* Single vector has a shadow register set */\n\n/*\n * Interrupt Status register.\n */\n#define PIC32_INTSTAT_VEC(s)    ((s) & 0xFF)    /* Interrupt vector */\n#define PIC32_INTSTAT_SRIPL(s)  ((s) >> 8 & 7)  /* Requested priority level */\n#define PIC32_INTSTAT_SRIPL_MASK 0x0700\n\n/*\n * Interrupt Prority Control register.\n */\n#define PIC32_IPC_IS0(x)        (x)             /* Interrupt 0 subpriority */\n#define PIC32_IPC_IP0(x)        ((x)<<2)        /* Interrupt 0 priority */\n#define PIC32_IPC_IS1(x)        ((x)<<8)        /* Interrupt 1 subpriority */\n#define PIC32_IPC_IP1(x)        ((x)<<10)       /* Interrupt 1 priority */\n#define PIC32_IPC_IS2(x)        ((x)<<16)       /* Interrupt 2 subpriority */\n#define PIC32_IPC_IP2(x)        ((x)<<18)       /* Interrupt 2 priority */\n#define PIC32_IPC_IS3(x)        ((x)<<24)       /* Interrupt 3 subpriority */\n#define PIC32_IPC_IP3(x)        ((x)<<26)       /* Interrupt 3 priority */\n\n/*\n * IRQ numbers for PIC32MX3xx/4xx/5xx/6xx/7xx\n */\n#define PIC32_IRQ_CT        0   /* Core Timer Interrupt */\n#define PIC32_IRQ_CS0       1   /* Core Software Interrupt 0 */\n#define PIC32_IRQ_CS1       2   /* Core Software Interrupt 1 */\n#define PIC32_IRQ_INT0      3   /* External Interrupt 0 */\n#define PIC32_IRQ_T1        4   /* Timer1 */\n#define PIC32_IRQ_IC1       5   /* Input Capture 1 */\n#define PIC32_IRQ_OC1       6   /* Output Compare 1 */\n#define PIC32_IRQ_INT1      7   /* External Interrupt 1 */\n#define PIC32_IRQ_T2        8   /* Timer2 */\n#define PIC32_IRQ_IC2       9   /* Input Capture 2 */\n#define PIC32_IRQ_OC2       10  /* Output Compare 2 */\n#define PIC32_IRQ_INT2      11  /* External Interrupt 2 */\n#define PIC32_IRQ_T3        12  /* Timer3 */\n#define PIC32_IRQ_IC3       13  /* Input Capture 3 */\n#define PIC32_IRQ_OC3       14  /* Output Compare 3 */\n#define PIC32_IRQ_INT3      15  /* External Interrupt 3 */\n#define PIC32_IRQ_T4        16  /* Timer4 */\n#define PIC32_IRQ_IC4       17  /* Input Capture 4 */\n#define PIC32_IRQ_OC4       18  /* Output Compare 4 */\n#define PIC32_IRQ_INT4      19  /* External Interrupt 4 */\n#define PIC32_IRQ_T5        20  /* Timer5 */\n#define PIC32_IRQ_IC5       21  /* Input Capture 5 */\n#define PIC32_IRQ_OC5       22  /* Output Compare 5 */\n#define PIC32_IRQ_SPI1E     23  /* SPI1 Fault */\n#define PIC32_IRQ_SPI1TX    24  /* SPI1 Transfer Done */\n#define PIC32_IRQ_SPI1RX    25  /* SPI1 Receive Done */\n\n#define PIC32_IRQ_SPI3E     26  /* SPI3 Fault */\n#define PIC32_IRQ_SPI3TX    27  /* SPI3 Transfer Done */\n#define PIC32_IRQ_SPI3RX    28  /* SPI3 Receive Done */\n#define PIC32_IRQ_U1E       26  /* UART1 Error */\n#define PIC32_IRQ_U1RX      27  /* UART1 Receiver */\n#define PIC32_IRQ_U1TX      28  /* UART1 Transmitter */\n#define PIC32_IRQ_I2C3B     26  /* I2C3 Bus Collision Event */\n#define PIC32_IRQ_I2C3S     27  /* I2C3 Slave Event */\n#define PIC32_IRQ_I2C3M     28  /* I2C3 Master Event */\n\n#define PIC32_IRQ_I2C1B     29  /* I2C1 Bus Collision Event */\n#define PIC32_IRQ_I2C1S     30  /* I2C1 Slave Event */\n#define PIC32_IRQ_I2C1M     31  /* I2C1 Master Event */\n#define PIC32_IRQ_CN        32  /* Input Change Interrupt */\n#define PIC32_IRQ_AD1       33  /* ADC1 Convert Done */\n#define PIC32_IRQ_PMP       34  /* Parallel Master Port */\n#define PIC32_IRQ_CMP1      35  /* Comparator Interrupt */\n#define PIC32_IRQ_CMP2      36  /* Comparator Interrupt */\n\n#define PIC32_IRQ_SPI2E     37  /* SPI2 Fault */\n#define PIC32_IRQ_SPI2TX    38  /* SPI2 Transfer Done */\n#define PIC32_IRQ_SPI2RX    39  /* SPI2 Receive Done */\n#define PIC32_IRQ_U3E       37  /* UART3 Error */\n#define PIC32_IRQ_U3RX      38  /* UART3 Receiver */\n#define PIC32_IRQ_U3TX      39  /* UART3 Transmitter */\n#define PIC32_IRQ_I2C4B     37  /* I2C4 Bus Collision Event */\n#define PIC32_IRQ_I2C4S     38  /* I2C4 Slave Event */\n#define PIC32_IRQ_I2C4M     39  /* I2C4 Master Event */\n\n#define PIC32_IRQ_SPI4E     40  /* SPI4 Fault */\n#define PIC32_IRQ_SPI4TX    41  /* SPI4 Transfer Done */\n#define PIC32_IRQ_SPI4RX    42  /* SPI4 Receive Done */\n#define PIC32_IRQ_U2E       40  /* UART2 Error */\n#define PIC32_IRQ_U2RX      41  /* UART2 Receiver */\n#define PIC32_IRQ_U2TX      42  /* UART2 Transmitter */\n#define PIC32_IRQ_I2C5B     40  /* I2C5 Bus Collision Event */\n#define PIC32_IRQ_I2C5S     41  /* I2C5 Slave Event */\n#define PIC32_IRQ_I2C5M     42  /* I2C5 Master Event */\n\n#define PIC32_IRQ_I2C2B     43  /* I2C2 Bus Collision Event */\n#define PIC32_IRQ_I2C2S     44  /* I2C2 Slave Event */\n#define PIC32_IRQ_I2C2M     45  /* I2C2 Master Event */\n#define PIC32_IRQ_FSCM      46  /* Fail-Safe Clock Monitor */\n#define PIC32_IRQ_RTCC      47  /* Real-Time Clock and Calendar */\n#define PIC32_IRQ_DMA0      48  /* DMA Channel 0 */\n#define PIC32_IRQ_DMA1      49  /* DMA Channel 1 */\n#define PIC32_IRQ_DMA2      50  /* DMA Channel 2 */\n#define PIC32_IRQ_DMA3      51  /* DMA Channel 3 */\n#define PIC32_IRQ_DMA4      52  /* DMA Channel 4 */\n#define PIC32_IRQ_DMA5      53  /* DMA Channel 5 */\n#define PIC32_IRQ_DMA6      54  /* DMA Channel 6 */\n#define PIC32_IRQ_DMA7      55  /* DMA Channel 7 */\n#define PIC32_IRQ_FCE       56  /* Flash Control Event */\n#define PIC32_IRQ_USB       57  /* USB */\n#define PIC32_IRQ_CAN1      58  /* Control Area Network 1 */\n#define PIC32_IRQ_CAN2      59  /* Control Area Network 2 */\n#define PIC32_IRQ_ETH       60  /* Ethernet Interrupt */\n#define PIC32_IRQ_IC1E      61  /* Input Capture 1 Error */\n#define PIC32_IRQ_IC2E      62  /* Input Capture 2 Error */\n#define PIC32_IRQ_IC3E      63  /* Input Capture 3 Error */\n#define PIC32_IRQ_IC4E      64  /* Input Capture 4 Error */\n#define PIC32_IRQ_IC5E      65  /* Input Capture 5 Error */\n#define PIC32_IRQ_PMPE      66  /* Parallel Master Port Error */\n#define PIC32_IRQ_U4E       67  /* UART4 Error */\n#define PIC32_IRQ_U4RX      68  /* UART4 Receiver */\n#define PIC32_IRQ_U4TX      69  /* UART4 Transmitter */\n#define PIC32_IRQ_U6E       70  /* UART6 Error */\n#define PIC32_IRQ_U6RX      71  /* UART6 Receiver */\n#define PIC32_IRQ_U6TX      72  /* UART6 Transmitter */\n#define PIC32_IRQ_U5E       73  /* UART5 Error */\n#define PIC32_IRQ_U5RX      74  /* UART5 Receiver */\n#define PIC32_IRQ_U5TX      75  /* UART5 Transmitter */\n\n/*\n * Interrupt vector numbers for PIC32MX3xx/4xx/5xx/6xx/7xx\n */\n#define PIC32_VECT_CT       0   /* Core Timer Interrupt */\n#define PIC32_VECT_CS0      1   /* Core Software Interrupt 0 */\n#define PIC32_VECT_CS1      2   /* Core Software Interrupt 1 */\n#define PIC32_VECT_INT0     3   /* External Interrupt 0 */\n#define PIC32_VECT_T1       4   /* Timer1 */\n#define PIC32_VECT_IC1      5   /* Input Capture 1 */\n#define PIC32_VECT_OC1      6   /* Output Compare 1 */\n#define PIC32_VECT_INT1     7   /* External Interrupt 1 */\n#define PIC32_VECT_T2       8   /* Timer2 */\n#define PIC32_VECT_IC2      9   /* Input Capture 2 */\n#define PIC32_VECT_OC2      10  /* Output Compare 2 */\n#define PIC32_VECT_INT2     11  /* External Interrupt 2 */\n#define PIC32_VECT_T3       12  /* Timer3 */\n#define PIC32_VECT_IC3      13  /* Input Capture 3 */\n#define PIC32_VECT_OC3      14  /* Output Compare 3 */\n#define PIC32_VECT_INT3     15  /* External Interrupt 3 */\n#define PIC32_VECT_T4       16  /* Timer4 */\n#define PIC32_VECT_IC4      17  /* Input Capture 4 */\n#define PIC32_VECT_OC4      18  /* Output Compare 4 */\n#define PIC32_VECT_INT4     19  /* External Interrupt 4 */\n#define PIC32_VECT_T5       20  /* Timer5 */\n#define PIC32_VECT_IC5      21  /* Input Capture 5 */\n#define PIC32_VECT_OC5      22  /* Output Compare 5 */\n#define PIC32_VECT_SPI1     23  /* SPI1 */\n\n#define PIC32_VECT_SPI3     24  /* SPI3 */\n#define PIC32_VECT_U1       24  /* UART1 */\n#define PIC32_VECT_I2C3     24  /* I2C3 */\n\n#define PIC32_VECT_I2C1     25  /* I2C1 */\n#define PIC32_VECT_CN       26  /* Input Change Interrupt */\n#define PIC32_VECT_AD1      27  /* ADC1 Convert Done */\n#define PIC32_VECT_PMP      28  /* Parallel Master Port */\n#define PIC32_VECT_CMP1     29  /* Comparator Interrupt */\n#define PIC32_VECT_CMP2     30  /* Comparator Interrupt */\n\n#define PIC32_VECT_SPI2     31  /* SPI2 */\n#define PIC32_VECT_U3       31  /* UART3 */\n#define PIC32_VECT_I2C4     31  /* I2C4 */\n\n#define PIC32_VECT_SPI4     32  /* SPI4 */\n#define PIC32_VECT_U2       32  /* UART2 */\n#define PIC32_VECT_I2C5     32  /* I2C5 */\n\n#define PIC32_VECT_I2C2     33  /* I2C2 */\n#define PIC32_VECT_FSCM     34  /* Fail-Safe Clock Monitor */\n#define PIC32_VECT_RTCC     35  /* Real-Time Clock and Calendar */\n#define PIC32_VECT_DMA0     36  /* DMA Channel 0 */\n#define PIC32_VECT_DMA1     37  /* DMA Channel 1 */\n#define PIC32_VECT_DMA2     38  /* DMA Channel 2 */\n#define PIC32_VECT_DMA3     39  /* DMA Channel 3 */\n#define PIC32_VECT_DMA4     40  /* DMA Channel 4 */\n#define PIC32_VECT_DMA5     41  /* DMA Channel 5 */\n#define PIC32_VECT_DMA6     42  /* DMA Channel 6 */\n#define PIC32_VECT_DMA7     43  /* DMA Channel 7 */\n#define PIC32_VECT_FCE      44  /* Flash Control Event */\n#define PIC32_VECT_USB      45  /* USB */\n#define PIC32_VECT_CAN1     46  /* Control Area Network 1 */\n#define PIC32_VECT_CAN2     47  /* Control Area Network 2 */\n#define PIC32_VECT_ETH      48  /* Ethernet Interrupt */\n#define PIC32_VECT_U4       49  /* UART4 */\n#define PIC32_VECT_U6       50  /* UART6 */\n#define PIC32_VECT_U5       51  /* UART5 */\n\n#endif /* _IO_PIC32MX_H */\n"
  },
  {
    "path": "sys/arch/pic32/include/setjmp.h",
    "content": "/*\n * Copyright (c) 2022 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#ifndef _MACHINE_SETJMP_H_\n#define _MACHINE_SETJMP_H_\n\n/*\n * Total 14 words for MIPS architecture:\n * Twelve for registers:\n *\tenv[0-11]:\t$s0-$s8, $ra, $gp, $sp\n * Two for signal mask:\n *\tenv[12]:\tsavesigs\n *\tenv[13]:\tsignal mask\n */\n#define _JBLEN 14\n\n#endif /* !_MACHINE_SETJMP_H_ */\n"
  },
  {
    "path": "sys/arch/pic32/include/signal.h",
    "content": "/*\n * Copyright (c) 2021 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#ifndef _MACHINE_SIGNAL_H_\n#define _MACHINE_SIGNAL_H_\n\n/*\n * Information pushed on stack when a signal is delivered.\n * This is used by the kernel to restore state following\n * execution of the signal handler.  It is also made available\n * to the handler to allow it to properly restore state if\n * a non-standard exit is performed.\n */\nstruct\tsigcontext {\n\tint\tsc_onstack;\t/* sigstack state to restore */\n\tlong\tsc_mask;\t/* signal mask to restore */\n\tint\tsc_r1;\t\t/* r1 to restore */\n\tint\tsc_r2;\t\t/* and other registers */\n\tint\tsc_r3;\n\tint\tsc_r4;\n\tint\tsc_r5;\n\tint\tsc_r6;\n\tint\tsc_r7;\n\tint\tsc_r8;\n\tint\tsc_r9;\n\tint\tsc_r10;\n\tint\tsc_r11;\n\tint\tsc_r12;\n\tint\tsc_r13;\n\tint\tsc_r14;\n\tint\tsc_r15;\n\tint\tsc_r16;\n\tint\tsc_r17;\n\tint\tsc_r18;\n\tint\tsc_r19;\n\tint\tsc_r20;\n\tint\tsc_r21;\n\tint\tsc_r22;\n\tint\tsc_r23;\n\tint\tsc_r24;\n\tint\tsc_r25;\n\tint\tsc_gp;\n\tint\tsc_sp;\t\t/* sp to restore */\n\tint\tsc_fp;\n\tint\tsc_ra;\n\tint\tsc_lo;\n\tint\tsc_hi;\n\tint\tsc_pc;\t\t/* pc to restore */\n};\n\n#endif /* !_MACHINE_SIGNAL_H_ */\n"
  },
  {
    "path": "sys/arch/pic32/include/types.h",
    "content": "/*\n * Copyright (c) 2022 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#ifndef\t_MIPS_TYPES_H_\n#define\t_MIPS_TYPES_H_\n\ntypedef\tstruct label_t {\n\tunsigned val[12];\t\t/* regs S0-S8, RA, GP and SP */\n} label_t;\n\n#endif\t/* !_MIPS_TYPES_H_ */\n"
  },
  {
    "path": "sys/arch/pic32/pic32/clock.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)clock.c\t1.1 (2.10BSD Berkeley) 12/1/86\n */\n\n#include <sys/param.h>\n#include <machine/pic32mx.h>\n\n/*\n * Setup core timer for `hz' timer interrupts per second.\n */\nvoid\nclkstart(void)\n{\n\tu_int count = mips_read_c0_register(C0_COUNT, 0);\n\n\tmips_write_c0_register(C0_COMPARE, 0,\n\t    count + (CPU_KHZ * 1000 / HZ + 1) / 2);\n\n\tIECSET(0) = 1 << PIC32_IRQ_CT;\n}\n"
  },
  {
    "path": "sys/arch/pic32/pic32/conf.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)conf.c\t3.2 (2.11BSD GTE) 1997/11/12\n */\n\n#include <sys/param.h>\n#include <sys/conf.h>\n#include <sys/buf.h>\n#include <sys/time.h>\n#include <sys/ioctl.h>\n#include <sys/resource.h>\n#include <sys/inode.h>\n#include <sys/proc.h>\n#include <sys/clist.h>\n#include <sys/tty.h>\n#include <sys/systm.h>\n#include <sys/errno.h>\n\n#include <sys/gpanel.h>\n#include <sys/gpio.h>\n#include <sys/spi.h>\n#include <sys/swap.h>\n\n#include <pic32/dev/uart.h>\n\n#ifdef SD_ENABLED\n#include <pic32/dev/sd.h>\n#endif\n\n#ifdef RC_ENABLED\n#include <pic32/dev/sramc.h>\n#endif\n\n#ifdef DR_ENABLED\n#include <pic32/dev/sdramp.h>\n#endif\n\n#ifdef MR_ENABLED\n#include <pic32/dev/mrams.h>\n#endif\n\n#ifdef SR_ENABLED\n#include <pic32/dev/spirams.h>\n#endif\n\n#ifdef UARTUSB_ENABLED\n#include <pic32/dev/usb_uart.h>\n#endif\n\n#ifdef ADC_ENABLED\n#include <pic32/dev/adc.h>\n#endif\n\n#ifdef GLCD_ENABLED\n#include <sys/glcd.h>\n#endif\n\n#ifdef PWM_ENABLED\n#include <sys/pwm.h>\n#endif\n\n#ifdef PICGA_ENABLED\n#include <sys/picga.h>\n#endif\n\n#ifdef PTY_ENABLED\n#include <sys/pty.h>\n#endif\n\n#ifdef SKEL_ENABLED\n#include <sys/skel.h>\n#endif\n\n#define __unused\t__attribute__((__unused__))\t/* XXX */\n\nint\nnullopen(dev_t dev __unused, int flag __unused, int mode __unused)\n{\n\treturn 0;\n}\n\nint\nnullclose(dev_t dev __unused, int flag __unused, int mode __unused)\n{\n\treturn 0;\n}\n\nint\nnoopen(dev_t dev __unused, int flag __unused, int mode __unused)\n{\n\treturn ENXIO;\n}\n\nint\nnoclose(dev_t dev __unused, int flag __unused, int mode __unused)\n{\n\treturn ENXIO;\n}\n\nint\nnorw(dev_t dev __unused, struct uio *uio __unused, int flag __unused)\n{\n\treturn 0;\n}\n\nint\nnoioctl(dev_t dev __unused, u_int cmd __unused, caddr_t data __unused,\n    int flag __unused)\n{\n\treturn EIO;\n}\n\nint\nnullstop(struct tty *tp __unused, int flag __unused)\n{\n\treturn 0;\n}\n\n/*\n * root attach routine.\n */\ndaddr_t\nnosize(dev_t dev __unused)\n{\n\treturn 0;\n}\n\n#define NOBDEV \\\n\t\tnoopen,\t\tnoclose,\tnostrategy, \\\n\t\tnosize,\t\tnoioctl,\t0\n\n/*\n * The RetroDisks require the same master number as the disk entry in the\n * rdisk.c file.  A bit of a bind, but it means that the RetroDisk\n * devices must be numbered from master 0 upwards.\n */\nconst struct bdevsw bdevsw[] = {\n\t{\t/* 0 - sd */\n#ifdef SD_ENABLED\n\t\tsdopen,\t\tsdclose,\tsdstrategy,\n\t\tsdsize,\t\tsdioctl,\t0\n#else\n\t\tNOBDEV\n#endif\n\t},\n\t{\t/* 1 - sramc */\n#ifdef RC_ENABLED\n\t\tsramc_open,\tsramc_close,\tsramc_strategy,\n\t\tsramc_size,\tsramc_ioctl,\t0\n#else\n\t\tNOBDEV\n#endif\n\t},\n\t{\t/* 2 - sdramp */\n#ifdef DR_ENABLED\n\t\tsdramp_open,\tsdramp_close,\tsdramp_strategy,\n\t\tsdramp_size,\tsdramp_ioctl,\t0\n#else\n\t\tNOBDEV\n#endif\n\t},\n\t{\t/* 3 - mrams */\n#ifdef MR_ENABLED\n\t\tmrams_open,\tmrams_close,\tmrams_strategy,\n\t\tmrams_size,\tmrams_ioctl,\t0\n#else\n\t\tNOBDEV\n#endif\n\t},\n\t{\t/* 4 - swap */\n\t\tswopen,\t\tswclose,\tswstrategy,\n\t\tswsize,\t\tswcioctl,\t0\n\t},\n\t{\t/* 5 - spirams */\n#ifdef SR_ENABLED\n\t\tspirams_open,\tspirams_close,\tspirams_strategy,\n\t\tspirams_size,\tspirams_ioctl,\t0\n#else\n\t\tNOBDEV\n#endif\n\t},\n\n\t/*\n\t * End the list with a blank entry.\n\t */\n\t{ 0 },\n};\n\nconst int nblkdev = sizeof(bdevsw) / sizeof(bdevsw[0]) - 1;\n\n#define NOCDEV \\\n\t\tnoopen,\t\tnoclose,\tnorw,\t\tnorw, \\\n\t\tnoioctl,\tnullstop,\t0,\t\tseltrue, \\\n\t\tnostrategy,\t0,\t\t0,\n\nconst struct cdevsw cdevsw[] = {\n\t/*\n\t * Static drivers - every system has these:\n\t */\n\t{\t/* 0 - console */\n\t\tcnopen,\t\tcnclose,\tcnread,\t\tcnwrite,\n\t\tcnioctl,\tnullstop,\tcnttys,\t\tcnselect,\n\t\tnostrategy,\t0,\t\t0,\n\t},\n\t{\t/* 1 - mem, kmem, null, zero */\n#if MEM_MAJOR != 1\n#error Wrong MEM_MAJOR value!\n#endif\n\t\tnullopen,\tnullclose,\tmmrw,\t\tmmrw,\n\t\tnoioctl,\tnullstop,\t0,\t\tseltrue,\n\t\tnostrategy,\t0,\t\t0,\n\t},\n\t{\t/* 2 - tty */\n\t\tsyopen,\t\tnullclose,\tsyread,\t\tsywrite,\n\t\tsyioctl,\tnullstop,\t0,\t\tsyselect,\n\t\tnostrategy,\t0,\t\t0,\n\t},\n\t{\t/* 3 - fd */\n\t\tfdopen,\t\tnullclose,\tnorw,\t\tnorw,\n\t\tnoioctl,\tnullstop,\t0,\t\tseltrue,\n\t\tnostrategy,\t0,\t\t0,\n\t},\n\t{\t/* 4 - temp (temporary allocation in swap space) */\n\t\tswcopen,\tswcclose,\tswcread,\tswcwrite,\n\t\tswcioctl,\tnullstop,\t0,\t\tseltrue,\n\t\tnostrategy,\t0,\t\t0,\n\t},\n\n\t/*\n\t * Optional drivers from here on:\n\t */\n\t{\t/* 5 - log */\n#ifdef LOG_ENABLED\n\t\tlogopen,\tlogclose,\tlogread,\tnorw,\n\t\tlogioctl,\tnullstop,\t0,\t\tlogselect,\n\t\tnostrategy,\t0,\t\t0,\n#else\n\t\tNOCDEV\n#endif\n\t},\n\t{\t/* 6 - tty uart */\n#if UART_MAJOR != 6\n#error Wrong UART_MAJOR value!\n#endif\n#if defined(UART1_ENABLED) || defined(UART2_ENABLED) || \\\n    defined(UART3_ENABLED) || defined(UART4_ENABLED) || \\\n    defined(UART5_ENABLED) || defined(UART6_ENABLED)\n\t\tuartopen,\tuartclose,\tuartread,\tuartwrite,\n\t\tuartioctl,\tnullstop,\tuartttys,\tuartselect,\n\t\tnostrategy,\tuartgetc,\tuartputc,\n#else\n\t\tNOCDEV\n#endif\n\t},\n\t{\t/* 7 - tty usb */\n#if UARTUSB_MAJOR != 7\n#error Wrong UARTUSB_MAJOR value!\n#endif\n#ifdef UARTUSB_ENABLED\n\t\tusbopen,\tusbclose,\tusbread,\tusbwrite,\n\t\tusbioctl,\tnullstop,\tusbttys,\tusbselect,\n\t\tnostrategy,\tusbgetc,\tusbputc,\n#else\n\t\tNOCDEV\n#endif\n\t},\n\t{\t/* 8, 9 - pty */\n#ifdef PTY_ENABLED\n\t\tptsopen,\tptsclose,\tptsread,\tptswrite,\n\t\tptyioctl,\tnullstop,\tpt_tty,\t\tptcselect,\n\t\tnostrategy,\t0,\t\t0,\n\t},\n\t{\n\t\tptcopen,\tptcclose,\tptcread,\tptcwrite,\n\t\tptyioctl,\tnullstop,\tpt_tty,\t\tptcselect,\n\t\tnostrategy,\t0,\t\t0,\n#else\n\t\tNOCDEV\n\t},\n\t{\n\t\tNOCDEV\n#endif\n\t},\n\t{\t/* 10 - gpio */\n#if defined(GPIO_ENABLED) || defined(GPIO1_ENABLED) || \\\n    defined(GPIO2_ENABLED) || defined(GPIO3_ENABLED) || \\\n    defined(GPIO4_ENABLED) || defined(GPIO5_ENABLED) || \\\n    defined(GPIO6_ENABLED)\n\t\tgpioopen,\tgpioclose,\tgpioread,\tgpiowrite,\n\t\tgpioioctl,\tnullstop,\t0,\t\tseltrue,\n\t\tnostrategy,\t0,\t\t0,\n#else\n\t\tNOCDEV\n#endif\n\t},\n\t{\t/* 11 - adc */\n#ifdef ADC_ENABLED\n\t\tadc_open,\tadc_close,\tadc_read,\tadc_write,\n\t\tadc_ioctl,\tnullstop,\t0,\t\tseltrue,\n\t\tnostrategy,\t0,\t\t0,\n#else\n\t\tNOCDEV\n#endif\n\t},\n\t{\t/* 12 - spi */\n#if defined(SPI1_ENABLED) || defined(SPI2_ENABLED) || \\\n    defined(SPI3_ENABLED) || defined(SPI4_ENABLED)\n\t\tspidev_open,\tspidev_close,\tspidev_read,\tspidev_write,\n\t\tspidev_ioctl,\tnullstop,\t0,\t\tseltrue,\n\t\tnostrategy,\t0,\t\t0,\n#else\n\t\tNOCDEV\n#endif\n\t},\n\t{\t/* 13 - glcd */\n#ifdef GLCD_ENABLED\n\t\tglcd_open,\tglcd_close,\tglcd_read,\tglcd_write,\n\t\tglcd_ioctl,\tnullstop,\t0,\t\tseltrue,\n\t\tnostrategy,\t0,\t\t0,\n#else\n\t\tNOCDEV\n#endif\n\t},\n\t{\t/* 14 - pwm */\n#ifdef PWM_ENABLED\n\t\tpwm_open,\tpwm_close,\tpwm_read,\tpwm_write,\n\t\tpwm_ioctl,\tnullstop,\t0,\t\tseltrue,\n\t\tnostrategy,\t0,\t\t0,\n#else\n\t\tNOCDEV\n#endif\n\t},\n\t{\t/* 15 - picga */\t/* Ignore this for now - it's WIP. */\n#ifdef PICGA_ENABLED\n\t\tpicga_open,\tpicga_close,\tpicga_read,\tpicga_write,\n\t\tpicga_ioctl,\tnullstop,\t0,\t\tseltrue,\n\t\tnostrategy,\t0,\t\t0,\n#else\n\t\tNOCDEV\n#endif\n\t},\n\t{\t/* 16 - hxtft, gpanel, sgpanel */\n\t\t/*\n\t\t * All LCD display drivers share the same device.\n\t\t * Only one such driver can be present in the kernel.\n\t\t */\n#if GPANEL_MAJOR != 16\n#error Wrong GPANEL_MAJOR value!\n#endif\n#if defined(HXTFT_ENABLED) || defined(GPANEL_ENABLED) || \\\n    defined(SGPANEL_ENABLED)\n\t\tgpanel_open,\tgpanel_close,\tgpanel_read,\tgpanel_write,\n\t\tgpanel_ioctl,\tnullstop,\t0,\t\tseltrue,\n\t\tnostrategy,\t0,\t\t0,\n#else\n\t\tNOCDEV\n#endif\n\t},\n\t{\t/* 17 - skel */\n#ifdef SKEL_ENABLED\n\t\tskeldev_open,\tskeldev_close,\tskeldev_read,\tskeldev_write,\n\t\tskeldev_ioctl,\tnullstop,\t0,\t\tseltrue,\n\t\tnostrategy,\t0,\t\t0,\n#else\n\t\tNOCDEV\n#endif\n\t},\n\n\t/*\n\t * End the list with a blank entry.\n\t */\n\t{ 0 },\n};\n\nconst int nchrdev = sizeof(cdevsw) / sizeof(cdevsw[0]) - 1;\n\n/*\n * Routine that identifies /dev/mem and /dev/kmem.\n *\n * A minimal stub routine can always return 0.\n */\nint\niskmemdev(dev_t dev)\n{\n\tif (major(dev) == 1 && (minor(dev) == 0 || minor(dev) == 1))\n\t\treturn 1;\n\n\treturn 0;\n}\n\n/*\n * Routine to determine if a device is a disk.\n *\n * A minimal stub routine can always return 0.\n */\nint\nisdisk(dev_t dev, int type)\n{\n\tif (type != IFBLK)\n\t\treturn 0;\n\n\tswitch (major(dev)) {\n\tcase 0:\t\t\t\t/* rd0 */\n\tcase 1:\t\t\t\t/* rd1 */\n\tcase 2:\t\t\t\t/* rd2 */\n\tcase 3:\t\t\t\t/* rd3 */\n\tcase 4:\t\t\t\t/* sw */\n\t\treturn 1;\n\tdefault:\n\t\treturn 0;\n\t}\n\t/* NOTREACHED */\n}\n\n/*\n * Routine to convert from character to block device number.\n * A minimal stub routine can always return NODEV.\n */\nint\nchrtoblk(dev_t dev __unused)\n{\n\treturn NODEV;\n}\n"
  },
  {
    "path": "sys/arch/pic32/pic32/exception.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)trap.c\t1.6 (2.11BSD) 1999/9/13\n */\n\n#include <sys/param.h>\n#include <sys/signalvar.h>\n#include <sys/systm.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/vm.h>\n#include <sys/tty.h>\n\n#include <pic32/dev/uart.h>\n#include <pic32/dev/usb_uart.h>\n\n#include <machine/frame.h>\n\n#if 0\n#define TRACE_EXCEPTIONS\n#endif\n\n#ifdef POWER_ENABLED\nextern void power_switch_check();\n#endif\n\n/*\n * Copy of COP0 Debug register, saved by exception handler (in locore.S).\n */\nint c0_debug;\n\nvolatile unsigned int ct_ticks = 0;\n\n#ifdef TRACE_EXCEPTIONS\nstatic void\nprint_args(narg, arg0, arg1, arg2, arg3, arg4, arg5)\n{\n    void print_arg(val) {\n        if (val & 0xff000000)\n            printf(\"%08x\", val);\n        else\n            printf(\"%u\", val);\n    }\n\n    print_arg(arg0);\n    if (narg > 1) { printf(\", \"); print_arg(arg1); }\n    if (narg > 2) { printf(\", \"); print_arg(arg2); }\n    if (narg > 3) { printf(\", \"); print_arg(arg3); }\n    if (narg > 4) { printf(\", \"); print_arg(arg4); }\n    if (narg > 5) { printf(\", \"); print_arg(arg5); }\n}\n#endif\n\n/*\n * Translate interrupt vector number to IRQ mask.\n */\nstatic const unsigned mask_by_vector[] = {\n    (1 << PIC32_IRQ_CT),            /* 0  - Core Timer Interrupt */\n    (1 << PIC32_IRQ_CS0),           /* 1  - Core Software Interrupt 0 */\n    (1 << PIC32_IRQ_CS1),           /* 2  - Core Software Interrupt 1 */\n    (1 << PIC32_IRQ_INT0),          /* 3  - External Interrupt 0 */\n    (1 << PIC32_IRQ_T1),            /* 4  - Timer1 */\n    (1 << PIC32_IRQ_IC1),           /* 5  - Input Capture 1 */\n    (1 << PIC32_IRQ_OC1),           /* 6  - Output Compare 1 */\n    (1 << PIC32_IRQ_INT1),          /* 7  - External Interrupt 1 */\n    (1 << PIC32_IRQ_T2),            /* 8  - Timer2 */\n    (1 << PIC32_IRQ_IC2),           /* 9  - Input Capture 2 */\n    (1 << PIC32_IRQ_OC2),           /* 10 - Output Compare 2 */\n    (1 << PIC32_IRQ_INT2),          /* 11 - External Interrupt 2 */\n    (1 << PIC32_IRQ_T3),            /* 12 - Timer3 */\n    (1 << PIC32_IRQ_IC3),           /* 13 - Input Capture 3 */\n    (1 << PIC32_IRQ_OC3),           /* 14 - Output Compare 3 */\n    (1 << PIC32_IRQ_INT3),          /* 15 - External Interrupt 3 */\n    (1 << PIC32_IRQ_T4),            /* 16 - Timer4 */\n    (1 << PIC32_IRQ_IC4),           /* 17 - Input Capture 4 */\n    (1 << PIC32_IRQ_OC4),           /* 18 - Output Compare 4 */\n    (1 << PIC32_IRQ_INT4),          /* 19 - External Interrupt 4 */\n    (1 << PIC32_IRQ_T5),            /* 20 - Timer5 */\n    (1 << PIC32_IRQ_IC5),           /* 21 - Input Capture 5 */\n    (1 << PIC32_IRQ_OC5),           /* 22 - Output Compare 5 */\n    (1 << PIC32_IRQ_SPI1E)       |  /* 23 - SPI1 */\n    (1 << PIC32_IRQ_SPI1TX)      |\n    (1 << PIC32_IRQ_SPI1RX),\n\n    (1 << PIC32_IRQ_U1E)         |  /* 24 - UART1 */\n    (1 << PIC32_IRQ_U1RX)        |\n    (1 << PIC32_IRQ_U1TX)        |\n    (1 << PIC32_IRQ_SPI3E)       |  /* 24 - SPI3 */\n    (1 << PIC32_IRQ_SPI3TX)      |\n    (1 << PIC32_IRQ_SPI3RX)      |\n    (1 << PIC32_IRQ_I2C3B)       |  /* 24 - I2C3 */\n    (1 << PIC32_IRQ_I2C3S)       |\n    (1 << PIC32_IRQ_I2C3M),\n\n    (1 << PIC32_IRQ_I2C1B)       |  /* 25 - I2C1 */\n    (1 << PIC32_IRQ_I2C1S)       |\n    (1 << PIC32_IRQ_I2C1M),\n    (1 << (PIC32_IRQ_CN-32)),       /* 26 - Input Change Interrupt */\n    (1 << (PIC32_IRQ_AD1-32)),      /* 27 - ADC1 Convert Done */\n    (1 << (PIC32_IRQ_PMP-32)),      /* 28 - Parallel Master Port */\n    (1 << (PIC32_IRQ_CMP1-32)),     /* 29 - Comparator Interrupt */\n    (1 << (PIC32_IRQ_CMP2-32)),     /* 30 - Comparator Interrupt */\n\n    (1 << (PIC32_IRQ_U3E-32))    |  /* 31 - UART3 */\n    (1 << (PIC32_IRQ_U3E-32))    |\n    (1 << (PIC32_IRQ_U3E-32))    |\n    (1 << (PIC32_IRQ_SPI2E-32))  |  /* 31 - SPI2 */\n    (1 << (PIC32_IRQ_SPI2TX-32)) |\n    (1 << (PIC32_IRQ_SPI2RX-32)) |\n    (1 << (PIC32_IRQ_I2C4B-32))  |  /* 31 - I2C4 */\n    (1 << (PIC32_IRQ_I2C4S-32))  |\n    (1 << (PIC32_IRQ_I2C4M-32)),\n\n    (1 << (PIC32_IRQ_U2E-32))    |  /* 32 - UART2 */\n    (1 << (PIC32_IRQ_U2RX-32))   |\n    (1 << (PIC32_IRQ_U2TX-32))   |\n    (1 << (PIC32_IRQ_SPI4E-32))  |  /* 32 - SPI4 */\n    (1 << (PIC32_IRQ_SPI4TX-32)) |\n    (1 << (PIC32_IRQ_SPI4RX-32)) |\n    (1 << (PIC32_IRQ_I2C5B-32))  |  /* 32 - I2C5 */\n    (1 << (PIC32_IRQ_I2C5S-32))  |\n    (1 << (PIC32_IRQ_I2C5M-32)),\n\n    (1 << (PIC32_IRQ_I2C2B-32))  |  /* 33 - I2C2 */\n    (1 << (PIC32_IRQ_I2C2S-32))  |\n    (1 << (PIC32_IRQ_I2C2M-32)),\n    (1 << (PIC32_IRQ_FSCM-32)),     /* 34 - Fail-Safe Clock Monitor */\n    (1 << (PIC32_IRQ_RTCC-32)),     /* 35 - Real-Time Clock and Calendar */\n    (1 << (PIC32_IRQ_DMA0-32)),     /* 36 - DMA Channel 0 */\n    (1 << (PIC32_IRQ_DMA1-32)),     /* 37 - DMA Channel 1 */\n    (1 << (PIC32_IRQ_DMA2-32)),     /* 38 - DMA Channel 2 */\n    (1 << (PIC32_IRQ_DMA3-32)),     /* 39 - DMA Channel 3 */\n    (1 << (PIC32_IRQ_DMA4-32)),     /* 40 - DMA Channel 4 */\n    (1 << (PIC32_IRQ_DMA5-32)),     /* 41 - DMA Channel 5 */\n    (1 << (PIC32_IRQ_DMA6-32)),     /* 42 - DMA Channel 6 */\n    (1 << (PIC32_IRQ_DMA7-32)),     /* 43 - DMA Channel 7 */\n    (1 << (PIC32_IRQ_FCE-32)),      /* 44 - Flash Control Event */\n    (1 << (PIC32_IRQ_USB-32)),      /* 45 - USB */\n    (1 << (PIC32_IRQ_CAN1-32)),     /* 46 - Control Area Network 1 */\n    (1 << (PIC32_IRQ_CAN2-32)),     /* 47 - Control Area Network 2 */\n    (1 << (PIC32_IRQ_ETH-32)),      /* 48 - Ethernet Controller */\n    (1 << (PIC32_IRQ_U4E-64))    |  /* 49 - UART4 */\n    (1 << (PIC32_IRQ_U4RX-64))   |\n    (1 << (PIC32_IRQ_U4TX-64)),\n    (1 << (PIC32_IRQ_U6E-64))    |  /* 50 - UART6 */\n    (1 << (PIC32_IRQ_U6RX-64))   |\n    (1 << (PIC32_IRQ_U6TX-64)),\n    (1 << (PIC32_IRQ_U5E-64))    |  /* 51 - UART5 */\n    (1 << (PIC32_IRQ_U5RX-64))   |\n    (1 << (PIC32_IRQ_U5TX-64))\n};\n\nstatic void\ndumpregs(frame)\n    struct trapframe *frame;\n{\n    unsigned int cause;\n    const char *code = 0;\n    unsigned *stacktop = (unsigned*) 0x80007ffc;\n    unsigned *p = (unsigned*) frame;\n\n    printf(\"\\n*** 0x%08x: exception \", frame->tf_pc);\n\n    cause = mips_read_c0_register(C0_CAUSE, 0);\n    switch (cause & CA_EXC_CODE) {\n    case CA_Int:    code = \"Interrupt\"; break;\n    case CA_AdEL:   code = \"Address Load\"; break;\n    case CA_AdES:   code = \"Address Save\"; break;\n    case CA_IBE:    code = \"Bus fetch\"; break;\n    case CA_DBE:    code = \"Bus load/store\"; break;\n    case CA_Sys:    code = \"Syscall\"; break;\n    case CA_Bp:     code = \"Breakpoint\"; break;\n    case CA_RI:     code = \"Reserved Instruction\"; break;\n    case CA_CPU:    code = \"Coprocessor Unusable\"; break;\n    case CA_Ov:     code = \"Arithmetic Overflow\"; break;\n    case CA_Tr:     code = \"Trap\"; break;\n    }\n    if (code)\n        printf(\"'%s'\\n\", code);\n    else\n        printf(\"%d\\n\", cause >> 2 & 31);\n\n    switch (cause & CA_EXC_CODE) {\n    case CA_AdEL:\n    case CA_AdES:\n        printf(\"*** badvaddr = 0x%08x\\n\",\n            mips_read_c0_register(C0_BADVADDR, 0));\n    }\n\n    printf(\"*** stack frame at %8x\\n\", frame);\n    while (p <= stacktop) {\n        printf(\" %8x\", *p++);\n        if (p <= stacktop)\n            printf(\" %8x\", *p++);\n        if (p <= stacktop)\n            printf(\" %8x\", *p++);\n        if (p <= stacktop)\n            printf(\" %8x\", *p++);\n        printf(\"\\n\");\n    }\n\n    printf(\"*** registers:\\n\");\n    printf(\"                t0 = %8x   s0 = %8x   t8 = %8x   lo = %8x\\n\",\n        frame->tf_r8, frame->tf_r16, frame->tf_r24, frame->tf_lo);\n    printf(\"at = %8x   t1 = %8x   s1 = %8x   t9 = %8x   hi = %8x\\n\",\n        frame->tf_r1, frame->tf_r9, frame->tf_r17, frame->tf_r25,\n        frame->tf_hi);\n    printf(\"v0 = %8x   t2 = %8x   s2 = %8x               status = %8x\\n\",\n        frame->tf_r2, frame->tf_r10, frame->tf_r18, frame->tf_status);\n    printf(\"v1 = %8x   t3 = %8x   s3 = %8x                cause = %8x\\n\",\n        frame->tf_r3, frame->tf_r11, frame->tf_r19, cause);\n    printf(\"a0 = %8x   t4 = %8x   s4 = %8x   gp = %8x  epc = %8x\\n\",\n        frame->tf_r4, frame->tf_r12, frame->tf_r20, frame->tf_gp,\n        frame->tf_pc);\n    printf(\"a1 = %8x   t5 = %8x   s5 = %8x   sp = %8x\\n\",\n        frame->tf_r5, frame->tf_r13, frame->tf_r21, frame->tf_sp);\n    printf(\"a2 = %8x   t6 = %8x   s6 = %8x   fp = %8x\\n\",\n        frame->tf_r6, frame->tf_r14, frame->tf_r22, frame->tf_fp);\n    printf(\"a3 = %8x   t7 = %8x   s7 = %8x   ra = %8x\\n\",\n        frame->tf_r7, frame->tf_r15, frame->tf_r23, frame->tf_ra);\n}\n\n/*\n * User mode flag added to cause code if exception is from user space.\n */\n#define USER        1\n\n/*\n * Called from locore.S when a processor exception occurs.\n * The argument is the array of registers saved on the system stack\n * by the hardware and software during the exception processing.\n */\nvoid\nexception(frame)\n    struct trapframe *frame;\n{\n    register int psig;\n    time_t syst;\n    unsigned c, irq, status, cause, sp;\n\n    led_control(LED_KERNEL, 1);\n    if ((unsigned) frame < (unsigned) &u + sizeof(u)) {\n        dumpregs(frame);\n        panic(\"stack overflow\");\n        /*NOTREACHED*/\n    }\n    /* Switch to kernel mode, keep interrupts disabled. */\n    status = frame->tf_status;\n    mips_write_c0_register(C0_STATUS, 0,\n        status & ~(ST_UM | ST_EXL | ST_IE));\n\n    if (c0_debug & DB_DM) {\n        cause = CA_Bp;\n        c0_debug = 0;\n        /* TODO: save DBD bit */\n    } else {\n        cause = mips_read_c0_register(C0_CAUSE, 0);\n        cause &= CA_EXC_CODE;\n    }\n    if (USERMODE(status))\n        cause |= USER;\n\n    syst = u.u_ru.ru_stime;\n\n    switch (cause) {\n\n    /*\n     * Exception.\n     */\n    default:\n#ifdef UCB_METER\n        cnt.v_trap++;\n#endif\n        switch (cause) {\n        default:                /* Unknown exception: fatal kernel error */\n            dumpregs(frame);\n            panic(\"unexpected exception\");\n            /*NOTREACHED*/\n        case CA_IBE + USER:     /* Bus error, instruction fetch */\n        case CA_DBE + USER:     /* Bus error, load or store */\n            printf(\"*** 0x%08x: %s: bus error\\n\", frame->tf_pc, u.u_comm);\n            psig = SIGBUS;\n            break;\n        case CA_RI + USER:      /* Reserved instruction */\n            psig = SIGILL;\n            break;\n        case CA_Bp + USER:      /* Breakpoint */\n            psig = SIGTRAP;\n            break;\n        case CA_Tr + USER:      /* Trap */\n            psig = SIGIOT;\n            break;\n        case CA_CPU + USER:     /* Coprocessor unusable */\n            psig = SIGEMT;\n            break;\n        case CA_Ov:             /* Arithmetic overflow */\n        case CA_Ov + USER:\n            psig = SIGFPE;\n            break;\n        case CA_AdEL + USER:    /* Address error, load or instruction fetch */\n        case CA_AdES + USER:    /* Address error, store */\n            printf(\"*** 0x%08x: %s: bad address 0x%08x\\n\",\n                frame->tf_pc, u.u_comm, mips_read_c0_register(C0_BADVADDR, 0));\n            psig = SIGSEGV;\n            break;\n        }\n        /* Enable interrupts. */\n        mips_intr_enable();\n        break;\n\n    /*\n     * Hardware interrupt.\n     */\n    case CA_Int:                /* Interrupt */\n    case CA_Int + USER:\n#ifdef UCB_METER\n        cnt.v_intr++;\n#endif\n        /* Get the current irq number */\n        c = INTSTAT;\n        if ((c & PIC32_INTSTAT_SRIPL_MASK) == 0) {\n            /* printf(\"*** unexpected interrupt: INTSTAT %08x\\n\", c); */\n            goto ret;\n        }\n        irq = PIC32_INTSTAT_VEC(c);\n\n\n        /* Handle the interrupt. */\n        switch (irq) {\n        case PIC32_VECT_CT:     /* Core Timer */\n            ct_ticks++;\n            /* Increment COMPARE register. */\n            IFSCLR(0) = 1 << PIC32_IRQ_CT;\n            c = mips_read_c0_register(C0_COMPARE, 0);\n            do {\n                c += (CPU_KHZ * 1000 / HZ + 1) / 2;\n                mips_write_c0_register(C0_COMPARE, 0, c);\n            } while ((int) (c - (unsigned)mips_read_c0_register(C0_COUNT, 0)) < 0);\n            hardclock((caddr_t) frame->tf_pc, status);\n\n#ifdef POWER_ENABLED\n            power_switch_check();\n#endif\n\n#ifdef UARTUSB_ENABLED\n            /* Poll USB on every timer tick. */\n            usbintr(0);\n#endif\n            break;\n#ifdef UART1_ENABLED\n        case PIC32_VECT_U1:     /* UART1 */\n            uartintr(makedev(UART_MAJOR, 0));\n            break;\n#endif\n#ifdef UART2_ENABLED\n        case PIC32_VECT_U2:     /* UART2 */\n            uartintr(makedev(UART_MAJOR, 1));\n            break;\n#endif\n#ifdef UART3_ENABLED\n        case PIC32_VECT_U3:     /* UART3 */\n            uartintr(makedev(UART_MAJOR, 2));\n            break;\n#endif\n#ifdef UART4_ENABLED\n        case PIC32_VECT_U4:     /* UART4 */\n            uartintr(makedev(UART_MAJOR, 3));\n            break;\n#endif\n#ifdef UART5_ENABLED\n        case PIC32_VECT_U5:     /* UART5 */\n            uartintr(makedev(UART_MAJOR, 4));\n            break;\n#endif\n#ifdef UART6_ENABLED\n        case PIC32_VECT_U6:     /* UART6 */\n            uartintr(makedev(UART_MAJOR, 5));\n            break;\n#endif\n#ifdef UARTUSB_ENABLED\n        case PIC32_VECT_USB:    /* USB */\n            IFSCLR(1) = 1 << (PIC32_IRQ_USB - 32);\n            usbintr(0);\n            break;\n#endif\n\n        default:\n            /* Disable the irq, to avoid loops */\n            printf(\"*** irq %u\\n\", irq);\n            if (irq < PIC32_VECT_CN) {\n                IECCLR(0) = mask_by_vector [irq];\n                IFSCLR(0) = mask_by_vector [irq];\n            } else {\n                IECCLR(1) = mask_by_vector [irq];\n                IFSCLR(1) = mask_by_vector [irq];\n            }\n            break;\n        }\n        if ((cause & USER) && runrun) {\n            /* Need to switch processes: in user mode only.\n             * Enable interrupts first. */\n/* MADSCIFI start new code */\n            /* u.u_error = 0; */\n            u.u_frame = frame;\n            u.u_code = frame->tf_pc;            /* For signal handler */\n\n            /* Check stack. */\n            sp = frame->tf_sp;\n            if (sp < u.u_procp->p_daddr + u.u_dsize) {\n                /* Process has trashed its stack; give it an illegal\n                 * instruction violation to halt it in its tracks. */\n                panic(\"unexpected exception 2\");\n                psig = SIGSEGV;\n                break;\n            }\n            if (u.u_procp->p_ssize < USER_DATA_END - sp) {\n                /* Expand stack. */\n                u.u_procp->p_ssize = USER_DATA_END - sp;\n                u.u_procp->p_saddr = sp;\n                u.u_ssize = u.u_procp->p_ssize;\n            }\n/* MADSCIFI end new code */\n\n            mips_intr_enable();\n            goto out;\n        }\n        goto ret;\n\n    /*\n     * System call.\n     */\n    case CA_Sys + USER:         /* Syscall */\n#ifdef UCB_METER\n        cnt.v_syscall++;\n#endif\n        /* Enable interrupts. */\n        mips_intr_enable();\n        u.u_error = 0;\n        u.u_frame = frame;\n        u.u_code = frame->tf_pc;            /* For signal handler */\n\n        /* Check stack. */\n        sp = frame->tf_sp;\n        if (sp < u.u_procp->p_daddr + u.u_dsize) {\n            /* Process has trashed its stack; give it an illegal\n             * instruction violation to halt it in its tracks. */\n            psig = SIGSEGV;\n            break;\n        }\n        if (u.u_procp->p_ssize < USER_DATA_END - sp) {\n            /* Expand stack. */\n            u.u_procp->p_ssize = USER_DATA_END - sp;\n            u.u_procp->p_saddr = sp;\n            u.u_ssize = u.u_procp->p_ssize;\n        }\n\n        /* Original pc for restarting syscalls */\n        int opc = frame->tf_pc;             /* opc points at syscall */\n        frame->tf_pc = opc + 3*NBPW;        /* no errors - skip 2 next instructions */\n\n        const struct sysent *callp = &sysent[0];\n        int code = (*(u_int*) opc >> 6) & 0377; /* bottom 8 bits are index */\n        if (code < nsysent)\n            callp += code;\n\n        if (callp->sy_narg) {\n            u.u_arg[0] = frame->tf_r4;      /* $a0 */\n            u.u_arg[1] = frame->tf_r5;      /* $a1 */\n            u.u_arg[2] = frame->tf_r6;      /* $a2 */\n            u.u_arg[3] = frame->tf_r7;      /* $a3 */\n            if (callp->sy_narg > 4) {\n                unsigned addr = (frame->tf_sp + 16) & ~3;\n                if (! baduaddr((caddr_t) addr))\n                    u.u_arg[4] = *(unsigned*) addr;\n            }\n            if (callp->sy_narg > 5) {\n                unsigned addr = (frame->tf_sp + 20) & ~3;\n                if (! baduaddr((caddr_t) addr))\n                    u.u_arg[5] = *(unsigned*) addr;\n            }\n        }\n#ifdef TRACE_EXCEPTIONS\n        printf(\"--- (%u)syscall: %s (\", u.u_procp->p_pid,\n            syscallnames [code >= nsysent ? 0 : code]);\n        if (callp->sy_narg > 0)\n            print_args(callp->sy_narg, u.u_arg[0], u.u_arg[1],\n                u.u_arg[2], u.u_arg[3], u.u_arg[4], u.u_arg[5]);\n        printf(\") at %08x\\n\", opc);\n#endif\n        u.u_rval = 0;\n        if (setjmp(&u.u_qsave) == 0) {\n            (*callp->sy_call)();\n        }\n        switch (u.u_error) {\n        case 0:\n#ifdef TRACE_EXCEPTIONS\n            printf(\"    (%u)syscall returned %u\\n\", u.u_procp->p_pid, u.u_rval);\n#endif\n            frame->tf_r2 = u.u_rval;        /* $v0 - result */\n            break;\n        case ERESTART:\n#ifdef TRACE_EXCEPTIONS\n            printf(\"    (%u)syscall restarted at %#x\\n\", u.u_procp->p_pid, opc);\n#endif\n            frame->tf_pc = opc;             /* return to syscall */\n            break;\n        case EJUSTRETURN:                   /* return from signal handler */\n#ifdef TRACE_EXCEPTIONS\n            printf(\"    (%u)jump to %#x, stack %#x\\n\",\n                u.u_procp->p_pid, frame->tf_pc, frame->tf_sp);\n#endif\n            break;\n        default:\n#ifdef TRACE_EXCEPTIONS\n            printf(\"    (%u)syscall failed, errno %d\\n\", u.u_procp->p_pid, u.u_error);\n#endif\n            frame->tf_pc = opc + NBPW;      /* return to next instruction */\n            frame->tf_r2 = -1;              /* $v0 - result */\n            frame->tf_r8 = u.u_error;       /* $t0 - errno */\n            break;\n        }\n        goto out;\n    }\n    /* From this point and further the interrupts must be enabled. */\n    psignal(u.u_procp, psig);\n\nout:\n    userret(frame->tf_pc, syst);\n\nret:\n    led_control(LED_KERNEL, 0);\n}\n\nvoid sc_msec()\n{\n    u.u_rval = ct_ticks * (1000 / HZ);\n}\n"
  },
  {
    "path": "sys/arch/pic32/pic32/locore.S",
    "content": "#\n# Startup code for Microchip PIC32 microcontrollers.\n# Using HID bootloader.\n#\n# Copyright (C) 2010 Serge Vakulenko, <serge@vak.ru>\n#\n# Permission to use, copy, modify, and distribute this software\n# and its documentation for any purpose and without fee is hereby\n# granted, provided that the above copyright notice appear in all\n# copies and that both that the copyright notice and this\n# permission notice and warranty disclaimer appear in supporting\n# documentation, and that the name of the author not be used in\n# advertising or publicity pertaining to distribution of the\n# software without specific, written prior permission.\n#\n# The author disclaim all warranties with regard to this\n# software, including all implied warranties of merchantability\n# and fitness.  In no event shall the author be liable for any\n# special, indirect or consequential damages or any damages\n# whatsoever resulting from loss of use, data or profits, whether\n# in an action of contract, negligence or other tortious action,\n# arising out of or in connection with the use or performance of\n# this software.\n#\n#include <machine/io.h>\n\n#define UBASE   0x7f008000      /* User space base address */\n\n                .set    noreorder\n                .set    mips32r2\n                .set    nomips16\n\n                .extern u\n                .extern u_end\n                .extern u0\n                .extern main\n                .extern exception\n\n#---------------------------------------\n# Reset vector: main entry point\n#\n                .section .startup,\"ax\",@progbits\n                .org    0\n                .type   _reset_vector_, @function\n_reset_vector_: .globl  _reset_vector_\n\n                .set    noat\n                move    $1, $zero                       # Clear all regs\n                move    $2, $zero\n                move    $3, $zero\n                move    $4, $zero\n                move    $5, $zero\n                move    $6, $zero\n                move    $7, $zero\n                move    $8, $zero\n                move    $9, $zero\n                move    $10, $zero\n                move    $11, $zero\n                move    $12, $zero\n                move    $13, $zero\n                move    $14, $zero\n                move    $15, $zero\n                move    $16, $zero\n                move    $17, $zero\n                move    $18, $zero\n                move    $19, $zero\n                move    $20, $zero\n                move    $21, $zero\n                move    $22, $zero\n                move    $23, $zero\n                move    $24, $zero\n                move    $25, $zero\n                move    $26, $zero\n                move    $27, $zero\n                move    $28, $zero\n                move    $29, $zero\n                move    $30, $zero\n                move    $31, $zero\n                mtlo    $zero\n                mthi    $zero\n                .set    at\n\n                la      $sp, u_end - 16                 # Stack at end of U area\n                la      $a0, main\n                jalr    $a0                             # Jump to main()\n                lui     $gp, 0x8000                     # Set global pointer (delay slot)\n\n                la      $k0, UBASE\n                mtc0    $k0, $C0_EPC                    # Entry to user code.\n\n                mfc0    $k0, $C0_STATUS\n                ori     $k0, $k0, ST_UM | ST_EXL | ST_IE # Set user mode and enable interrupts\n                mtc0    $k0, $C0_STATUS                 # Put SR back\n                eret                                    # PC <= EPC; EXL <= 0\n                nop                                     # just to be safe\n\n\n#---------------------------------------\n# Secondary entry point for RetroBSD bootloader.\n#\n                .section .exception,\"ax\",@progbits\n_exception_base_: .globl _exception_base_\n\n                .org    0\n                .type   _entry_vector_, @function\n_entry_vector_: .globl  _entry_vector_\n                la      $k0, _reset_vector_\n                jr      $k0\n                nop\n\n/*\n * Data for bootloader.\n */\n                .org    0xf8\n                .type   _ebase, @object\n_ebase:         .word   0x9d000000                      # EBase value\n\n                .type   _imgptr, @object\n_imgptr:        .word   -1                              # Image header pointer\n\n\n#---------------------------------------\n# Exception vector: handle exceptions\n#\n                .org    0x180\n                .type   _exception_vector_, @function\n_exception_vector_: .globl _exception_vector_\n\n                b       _interrupt_vector_\n                nop\n\n#---------------------------------------\n# Interrupt vector: handle interrupts\n#\n                .org    0x200\n                .type   _interrupt_vector_, @function\n_interrupt_vector_: .globl _interrupt_vector_\n\n                mfc0    $k0, $C0_STATUS\n                andi    $k1, $k0, ST_UM                 # Check user mode\n                beqz    $k1, kernel_exception\n                move    $k1, $sp\n\n                #\n                # Exception in user mode: switch stack.\n                #\nuser_exception:\n                la      $sp, u_end                      # Stack at end of U area\nkernel_exception:\n                addi    $sp, -16-FRAME_WORDS*4          # Allocate space for registers\nsave_regs:\n                sw      $k0, (16+FRAME_STATUS*4) ($sp)\n                sw      $k1, (16+FRAME_SP*4) ($sp)\n\n                .set    noat\n                sw      $1, (16+FRAME_R1*4) ($sp)       # Save general registers\n                sw      $2, (16+FRAME_R2*4) ($sp)\n                sw      $3, (16+FRAME_R3*4) ($sp)\n                sw      $4, (16+FRAME_R4*4) ($sp)\n                sw      $5, (16+FRAME_R5*4) ($sp)\n                sw      $6, (16+FRAME_R6*4) ($sp)\n                sw      $7, (16+FRAME_R7*4) ($sp)\n                sw      $8, (16+FRAME_R8*4) ($sp)\n                sw      $9, (16+FRAME_R9*4) ($sp)\n                sw      $10, (16+FRAME_R10*4) ($sp)\n                sw      $11, (16+FRAME_R11*4) ($sp)\n                sw      $12, (16+FRAME_R12*4) ($sp)\n                sw      $13, (16+FRAME_R13*4) ($sp)\n                sw      $14, (16+FRAME_R14*4) ($sp)\n                sw      $15, (16+FRAME_R15*4) ($sp)\n                sw      $16, (16+FRAME_R16*4) ($sp)\n                sw      $17, (16+FRAME_R17*4) ($sp)\n                sw      $18, (16+FRAME_R18*4) ($sp)\n                sw      $19, (16+FRAME_R19*4) ($sp)\n                sw      $20, (16+FRAME_R20*4) ($sp)\n                sw      $21, (16+FRAME_R21*4) ($sp)\n                sw      $22, (16+FRAME_R22*4) ($sp)\n                sw      $23, (16+FRAME_R23*4) ($sp)\n                sw      $24, (16+FRAME_R24*4) ($sp)\n                sw      $25, (16+FRAME_R25*4) ($sp)\n                # Skip $26 - K0\n                # Skip $27 - K1\n                sw      $28, (16+FRAME_GP*4) ($sp)\n                # Skip $29 - SP\n                sw      $30, (16+FRAME_FP*4) ($sp)\n                sw      $31, (16+FRAME_RA*4) ($sp)\n                .set    at\n\n                mfhi    $k0                             # Save special registers\n                sw      $k0, (16+FRAME_HI*4) ($sp)\n\n                mflo    $k0\n                sw      $k0, (16+FRAME_LO*4) ($sp)\n\n                mfc0    $k0, $C0_EPC\n                sw      $k0, (16+FRAME_PC*4) ($sp)\n\n                move    $a0, $sp\n                addi    $a0, 16                         # Arg 0: saved regs.\n                jal     exception                       # Call C code.\n                lui     $gp, 0x8000                     # Set global pointer (delay slot)\n\n                #\n                # Restore CPU state and return from interrupt.\n                #\nrestore_regs:\n                lw      $a0, (16+FRAME_LO*4) ($sp)      # Load HI, LO registers\n                mtlo    $a0\n                lw      $a0, (16+FRAME_HI*4) ($sp)\n                mthi    $a0\n\n                .set    noat\n                lw      $1, (16+FRAME_R1*4) ($sp)       # Load general registers\n                lw      $2, (16+FRAME_R2*4) ($sp)\n                lw      $3, (16+FRAME_R3*4) ($sp)\n                lw      $4, (16+FRAME_R4*4) ($sp)\n                lw      $5, (16+FRAME_R5*4) ($sp)\n                lw      $6, (16+FRAME_R6*4) ($sp)\n                lw      $7, (16+FRAME_R7*4) ($sp)\n                lw      $8, (16+FRAME_R8*4) ($sp)\n                lw      $9, (16+FRAME_R9*4) ($sp)\n                lw      $10, (16+FRAME_R10*4) ($sp)\n                lw      $11, (16+FRAME_R11*4) ($sp)\n                lw      $12, (16+FRAME_R12*4) ($sp)\n                lw      $13, (16+FRAME_R13*4) ($sp)\n                lw      $14, (16+FRAME_R14*4) ($sp)\n                lw      $15, (16+FRAME_R15*4) ($sp)\n                lw      $16, (16+FRAME_R16*4) ($sp)\n                lw      $17, (16+FRAME_R17*4) ($sp)\n                lw      $18, (16+FRAME_R18*4) ($sp)\n                lw      $19, (16+FRAME_R19*4) ($sp)\n                lw      $20, (16+FRAME_R20*4) ($sp)\n                lw      $21, (16+FRAME_R21*4) ($sp)\n                lw      $22, (16+FRAME_R22*4) ($sp)\n                lw      $23, (16+FRAME_R23*4) ($sp)\n                lw      $24, (16+FRAME_R24*4) ($sp)\n                lw      $25, (16+FRAME_R25*4) ($sp)\n                # Skip $26 - K0\n                # Skip $27 - K1\n                lw      $28, (16+FRAME_GP*4) ($sp)\n                # Skip $29 - SP\n                lw      $30, (16+FRAME_FP*4) ($sp)\n                .set    at\n\n                # Do not use k0/k1 here, as interrupts are still enabled\n                lw      $31, (16+FRAME_STATUS*4) ($sp)  # K0 = saved status\n                ori     $31, ST_EXL                     # Set EXL\n                mtc0    $31, $C0_STATUS                 # put SR back: disable interrupts\n                ehb\n\n                lw      $k0, (16+FRAME_PC*4) ($sp)      # K0 = EPC\n                mtc0    $k0, $C0_EPC                    # put PC in EPC\n                ext     $k1, $31, 27, 1                 # get RP bit: single-step request\n\n                lw      $31, (16+FRAME_RA*4) ($sp)\n                lw      $sp, (16+FRAME_SP*4) ($sp)      # Restore stack\n\n                # Return from exception\n                bnez    $k1, debug_request              # single-step request\n                eret                                    # PC <= EPC; EXL <= 0\ndebug_request:\n                sdbbp                                   # enter debug mode\n\n#---------------------------------------\n# Debug exception processing.\n#\n                .org    0x480\n                .type   _debug_vector_, @function\n_debug_vector_: .globl _debug_vector_\n\n                mfc0    $k0, $C0_DEPC\n                la      $k1, debug_request\n                bne     $k0, $k1, single_step_done\n                nop\n\n                # single step request\n                mfc0    $k0, $C0_DEBUG\n                ori     $k0, DB_SST                     # set SST bit\n                mtc0    $k0, $C0_DEBUG\n\n                mfc0    $k1, $C0_EPC\n                mtc0    $k1, $C0_DEPC                   # DEPC <= EPC\n                mfc0    $k0, $C0_STATUS\n                xori    $k0, ST_EXL                     # Clear EXL\n                mtc0    $k0, $C0_STATUS\n                deret                                   # PC <= DEPC; DM <= 0\n                # A single instruction of the user program\n                # is executed here, then jump to _debug_vector_\n                # with updated DEPC.\n                # Continue below.\nsingle_step_done:\n                mtc0    $k0, $C0_EPC                    # EPC <= DEPC\n\n                la      $k1, _exception_vector_\n                mtc0    $k1, $C0_DEPC                   # DEPC <= exception handler\n\n                mfc0    $k0, $C0_DEBUG\n                sw      $k0, c0_debug                   # save Debug register\n                ori     $k0, DB_SST\n                xori    $k0, DB_SST                     # clear SST bit\n                mtc0    $k0, $C0_DEBUG\n\n                mfc0    $k1, $C0_STATUS\n                ori     $k1, ST_EXL                     # Set EXL\n                mtc0    $k1, $C0_STATUS\n                deret                                   # PC <= DEPC; DM <= 0\n\n#---------------------------------------\n# Icode is copied out to process 1 to exec /sbin/init.\n# If the exec fails, process 1 exits.\n#\n                .globl  icode, icodeend, initflags\n                .type   icode, @function\n                .type   icodeend, @function\n                .type   etcinit, @object\n                .type   argv, @object\nicode:\n                la      $a0, UBASE\n                move    $a1, $a0\n                addi    $a0, etcinit - icode\n                addi    $a1, argv - icode\n                syscall 11                              # SYS_execv\n                move    $a0, $v0\n                syscall 1                               # SYS_exit\netcinit:\n                .ascii  \"/sbin/init\\0\"\n                .align  2\ninitflags:\n                .ascii  \"-\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"         # space for options\nargv:\n                .word   etcinit + 6 - icode + UBASE     # address of \"init\\0\"\n                .word   initflags - icode + UBASE       # init options\n                .word   0\n\nicodeend:       nop\n\n#---------------------------------------\n# int setjmp (label_t *env);\n#\n# Setjmp(env) will save the process' current register variables, stack\n# and program counter context and return a zero.\n#\n                .type   setjmp, @function\nsetjmp:         .globl  setjmp\n                sw      $s0, (0 * 4) ($a0)              # save register variables s0-s8\n                sw      $s1, (1 * 4) ($a0)\n                sw      $s2, (2 * 4) ($a0)\n                sw      $s3, (3 * 4) ($a0)\n                sw      $s4, (4 * 4) ($a0)\n                sw      $s5, (5 * 4) ($a0)\n                sw      $s6, (6 * 4) ($a0)\n                sw      $s7, (7 * 4) ($a0)\n                sw      $s8, (8 * 4) ($a0)              # frame pointer\n                sw      $ra, (9 * 4) ($a0)              # return address\n                sw      $gp, (10 * 4) ($a0)             # global data pointer\n                sw      $sp, (11 * 4) ($a0)             # stack pointer\n                j       $ra\n                move    $v0, $zero                      # return a zero for the setjmp call\n\n#---------------------------------------\n# void longjmp (memaddr uaddr, label_t *env);\n#\n# Longjmp(uaddr, env) will generate a \"return(1)\" from the last\n# call to setjmp(env) by mapping in the user structure pointed to by uaddr,\n# restoring the context saved by setjmp in env and returning a \"1\".\n# Note that registers are recovered statically from the env buffer.\n# Stack is not used.\n#\n# This longjmp differs from the longjmp found in the standard library -\n# it's actually closer to the resume routine of the 4.3BSD kernel.\n#\n                .type   longjmp, @function\nlongjmp:        .globl  longjmp\n\n                di                              # can't let anything in till we get a valid stack...\n\n                la      $v0, u                  # pointer to &u\n                beq     $v0, $a0, 2f            # if uaddr == &u...\n                nop                             # ...no need to remap U area\n\n                la      $a3, u_end              # pointer to &u + USIZE\n                la      $a0, u0                 # pointer to &u0\n\n                lw      $v1, 0($v0)             # u.u_procp\n                sw      $a0, 60($v1)            # u.u_procp->p_addr = &u0\n\n                # exchange contents of u and u0\n                move    $v1, $v0\n1:\n                lw      $t1, 0($v1)\n                lw      $t0, 0($a0)\n                sw      $t0, 0($v1)\n                sw      $t1, 0($a0)\n                lw      $t1, 4($v1)\n                lw      $t0, 4($a0)\n                sw      $t0, 4($v1)\n                sw      $t1, 4($a0)\n                lw      $t1, 8($v1)\n                lw      $t0, 8($a0)\n                sw      $t0, 8($v1)\n                sw      $t1, 8($a0)\n                lw      $t1, 12($v1)\n                lw      $t0, 12($a0)\n                sw      $t0, 12($v1)\n                sw      $t1, 12($a0)\n                addiu   $v1, $v1, 16\n                bne     $a3, $v1, 1b\n                addiu   $a0, $a0, 16\n\n                lw      $v1, 0($v0)             # u.u_procp\n                sw      $v0, 60($v1)            # u.u_procp->p_addr = &u\n2:\n                lw      $s0, (0 * 4) ($a1)      # restore register variables s0-s8\n                lw      $s1, (1 * 4) ($a1)\n                lw      $s2, (2 * 4) ($a1)\n                lw      $s3, (3 * 4) ($a1)\n                lw      $s4, (4 * 4) ($a1)\n                lw      $s5, (5 * 4) ($a1)\n                lw      $s6, (6 * 4) ($a1)\n                lw      $s7, (7 * 4) ($a1)\n                lw      $s8, (8 * 4) ($a1)      # frame pointer\n                lw      $ra, (9 * 4) ($a1)      # return address\n                lw      $gp, (10 * 4) ($a1)     # global data pointer\n                lw      $sp, (11 * 4) ($a1)     # stack pointer\n\n                ei                              # release interrupts\n                j       $ra                     # transfer back to setjmp()\n                li      $v0, 1                  # return value of 1\n"
  },
  {
    "path": "sys/arch/pic32/pic32/machdep.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)machdep.c\t2.4 (2.11BSD) 1999/9/13\n */\n\n#include <sys/param.h>\n#include <sys/dir.h>\n#include <sys/inode.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/fs.h>\n#include <sys/map.h>\n#include <sys/buf.h>\n#include <sys/file.h>\n#include <sys/clist.h>\n#include <sys/callout.h>\n#include <sys/reboot.h>\n#include <sys/msgbuf.h>\n#include <sys/namei.h>\n#include <sys/mount.h>\n#include <sys/systm.h>\n#include <sys/config.h>\n#include <sys/tty.h>\n\n#include <pic32/dev/uart.h>\n#include <pic32/dev/usb_uart.h>\n\n#ifdef UARTUSB_ENABLED\n#   include <pic32/hal/usb_device.h>\n#   include <pic32/hal/usb_function_cdc.h>\n#endif\n\n#ifdef POWER_ENABLED\nextern void power_init();\nextern void power_off();\n#endif\n\n#ifdef LED_TTY_INVERT\n#define LED_TTY_ON()        LAT_CLR(LED_TTY_PORT) = 1 << LED_TTY_PIN\n#define LED_TTY_OFF()       LAT_SET(LED_TTY_PORT) = 1 << LED_TTY_PIN\n#else\n#define LED_TTY_ON()        LAT_SET(LED_TTY_PORT) = 1 << LED_TTY_PIN\n#define LED_TTY_OFF()       LAT_CLR(LED_TTY_PORT) = 1 << LED_TTY_PIN\n#endif\n\n#ifdef LED_DISK_INVERT\n#define LED_DISK_ON()       LAT_CLR(LED_DISK_PORT) = 1 << LED_DISK_PIN\n#define LED_DISK_OFF()      LAT_SET(LED_DISK_PORT) = 1 << LED_DISK_PIN\n#else\n#define LED_DISK_ON()       LAT_SET(LED_DISK_PORT) = 1 << LED_DISK_PIN\n#define LED_DISK_OFF()      LAT_CLR(LED_DISK_PORT) = 1 << LED_DISK_PIN\n#endif\n\n#ifdef LED_KERNEL_INVERT\n#define LED_KERNEL_ON()     LAT_CLR(LED_KERNEL_PORT) = 1 << LED_KERNEL_PIN\n#define LED_KERNEL_OFF()    LAT_SET(LED_KERNEL_PORT) = 1 << LED_KERNEL_PIN\n#else\n#define LED_KERNEL_ON()     LAT_SET(LED_KERNEL_PORT) = 1 << LED_KERNEL_PIN\n#define LED_KERNEL_OFF()    LAT_CLR(LED_KERNEL_PORT) = 1 << LED_KERNEL_PIN\n#endif\n\n#ifdef LED_SWAP_INVERT\n#define LED_SWAP_ON()       LAT_CLR(LED_SWAP_PORT) = 1 << LED_SWAP_PIN\n#define LED_SWAP_OFF()      LAT_SET(LED_SWAP_PORT) = 1 << LED_SWAP_PIN\n#else\n#define LED_SWAP_ON()       LAT_SET(LED_SWAP_PORT) = 1 << LED_SWAP_PIN\n#define LED_SWAP_OFF()      LAT_CLR(LED_SWAP_PORT) = 1 << LED_SWAP_PIN\n#endif\n\n#ifdef LED_MISC1_INVERT\n#define LED_MISC1_ON()      LAT_CLR(LED_MISC1_PORT) = 1 << LED_MISC1_PIN\n#define LED_MISC1_OFF()     LAT_SET(LED_MISC1_PORT) = 1 << LED_MISC1_PIN\n#else\n#define LED_MISC1_ON()      LAT_SET(LED_MISC1_PORT) = 1 << LED_MISC1_PIN\n#define LED_MISC1_OFF()     LAT_CLR(LED_MISC1_PORT) = 1 << LED_MISC1_PIN\n#endif\n\n#ifdef LED_MISC2_INVERT\n#define LED_MISC2_ON()      LAT_CLR(LED_MISC2_PORT) = 1 << LED_MISC2_PIN\n#define LED_MISC2_OFF()     LAT_SET(LED_MISC2_PORT) = 1 << LED_MISC2_PIN\n#else\n#define LED_MISC2_ON()      LAT_SET(LED_MISC2_PORT) = 1 << LED_MISC2_PIN\n#define LED_MISC2_OFF()     LAT_CLR(LED_MISC2_PORT) = 1 << LED_MISC2_PIN\n#endif\n\n#ifdef LED_MISC3_INVERT\n#define LED_MISC3_ON()      LAT_CLR(LED_MISC3_PORT) = 1 << LED_MISC3_PIN\n#define LED_MISC3_OFF()     LAT_SET(LED_MISC3_PORT) = 1 << LED_MISC3_PIN\n#else\n#define LED_MISC3_ON()      LAT_SET(LED_MISC3_PORT) = 1 << LED_MISC3_PIN\n#define LED_MISC3_OFF()     LAT_CLR(LED_MISC3_PORT) = 1 << LED_MISC3_PIN\n#endif\n\n#ifdef LED_MISC4_INVERT\n#define LED_MISC4_ON()      LAT_CLR(LED_MISC4_PORT) = 1 << LED_MISC4_PIN\n#define LED_MISC4_OFF()     LAT_SET(LED_MISC4_PORT) = 1 << LED_MISC4_PIN\n#else\n#define LED_MISC4_ON()      LAT_SET(LED_MISC4_PORT) = 1 << LED_MISC4_PIN\n#define LED_MISC4_OFF()     LAT_CLR(LED_MISC4_PORT) = 1 << LED_MISC4_PIN\n#endif\n\nchar    machine[] = MACHINE;            /* from <machine/machparam.h> */\nchar    machine_arch[] = MACHINE_ARCH;  /* from <machine/machparam.h> */\nchar    cpu_model[64];\n\nint     hz = HZ;\nint     usechz = (1000000L + HZ - 1) / HZ;\n#ifdef TIMEZONE\nstruct  timezone tz = { TIMEZONE, DST };\n#else\nstruct  timezone tz = { 8*60, 1 };\n#endif\nint     nproc = NPROC;\n\nstruct  namecache namecache [NNAMECACHE];\nchar    bufdata [NBUF * MAXBSIZE];\nstruct  inode inode [NINODE];\nstruct  callout callout [NCALL];\nstruct  mount mount [NMOUNT];\nstruct  buf buf [NBUF], bfreelist [BQUEUES];\nstruct  bufhd bufhash [BUFHSZ];\nstruct  cblock cfree [NCLIST];\nstruct  proc proc [NPROC];\nstruct  file file [NFILE];\n\n/*\n * Remove the ifdef/endif to run the kernel in unsecure mode even when in\n * a multiuser state.  Normally 'init' raises the security level to 1\n * upon transitioning to multiuser.  Setting the securelevel to -1 prevents\n * the secure level from being raised by init.\n */\n#ifdef  PERMANENTLY_INSECURE\nint securelevel = -1;\n#else\nint securelevel = 0;\n#endif\n\nstruct mapent   swapent[SMAPSIZ];\nstruct map  swapmap[1] = {\n    { swapent,\n      &swapent[SMAPSIZ],\n      \"swapmap\" },\n};\n\nint waittime = -1;\n\n/* CPU package type: 64 pins or 100 pins. */\nint cpu_pins;\n\nstatic int\nnodump(dev)\n    dev_t dev;\n{\n    printf(\"\\ndumping to dev %o off %D: not implemented\\n\", dumpdev, dumplo);\n    return 0;\n}\n\nint (*dump)(dev_t) = nodump;\n\ndev_t   pipedev;\ndaddr_t dumplo = (daddr_t) 1024;\n\n/*\n * Check whether button 1 is pressed.\n */\nstatic inline int\nbutton1_pressed()\n{\n#ifdef BUTTON1_PORT\n    int val;\n\n    TRIS_SET(BUTTON1_PORT) = 1 << BUTTON1_PIN;\n    val = PORT_VAL(BUTTON1_PORT);\n#ifdef BUTTON1_INVERT\n    val = ~val;\n#endif\n    return (val >> BUTTON1_PIN) & 1;\n#else\n    return 0;\n#endif\n}\n\n/*\n * Machine dependent startup code\n */\nvoid\nstartup()\n{\n    extern void _etext(), _exception_base_();\n    extern unsigned __data_start;\n\n    /* Initialize STATUS register: master interrupt disable.\n     * Setup interrupt vector base. */\n    mips_write_c0_register(C0_STATUS, 0, ST_CU0 | ST_BEV);\n    mips_write_c0_register(C0_EBASE, 1, _exception_base_);\n    mips_write_c0_register(C0_STATUS, 0, ST_CU0);\n\n    /* Set vector spacing: not used really, but must be nonzero. */\n    mips_write_c0_register(C0_INTCTL, 1, 32);\n\n    /* Clear CAUSE register: use special interrupt vector 0x200. */\n    mips_write_c0_register(C0_CAUSE, 0, CA_IV);\n\n    /* Setup memory. */\n    BMXPUPBA = 512 << 10;               /* Kernel Flash memory size */\n#ifdef KERNEL_EXECUTABLE_RAM\n    /*\n     * Set boundry for kernel executable ram on smallest\n     * 2k boundry required to allow the keram segment to fit.\n     * This means that there is possibly some u0area ramspace that\n     * is executable, but as it is isolated from userspace this\n     * should be ok, given the apparent goals of this project.\n     */\n    extern void _keram_start(), _keram_end();\n    unsigned keram_size = (((char*)&_keram_end-(char*)&_keram_start+(2<<10))/(2<<10)*(2<<10));\n    BMXDKPBA = ((32<<10)-keram_size);   /* Kernel RAM size */\n    BMXDUDBA = BMXDKPBA+(keram_size);   /* Executable RAM in kernel */\n#else\n    BMXDKPBA = 32 << 10;                /* Kernel RAM size */\n    BMXDUDBA = BMXDKPBA;                /* Zero executable RAM in kernel */\n#endif\n    BMXDUPBA = BMXDUDBA;                /* All user RAM is executable */\n\n    /*\n     * Setup interrupt controller.\n     */\n    INTCON = 0;                         /* Interrupt Control */\n    IPTMR = 0;                          /* Temporal Proximity Timer */\n\n    /* Interrupt Flag Status */\n    IFS(0) = PIC32_IPC_IP0(2) | PIC32_IPC_IP1(1) |\n             PIC32_IPC_IP2(1) | PIC32_IPC_IP3(1) |\n             PIC32_IPC_IS0(0) | PIC32_IPC_IS1(0) |\n             PIC32_IPC_IS2(0) | PIC32_IPC_IS3(0) ;\n    IFS(1) = 0;\n    IFS(2) = 0;\n\n    /* Interrupt Enable Control */\n    IEC(0) = 0;\n    IEC(1) = 0;\n    IEC(2) = 0;\n\n    /* Interrupt Priority Control */\n    unsigned ipc = PIC32_IPC_IP0(1) | PIC32_IPC_IP1(1) |\n                   PIC32_IPC_IP2(1) | PIC32_IPC_IP3(1) |\n                   PIC32_IPC_IS0(0) | PIC32_IPC_IS1(0) |\n                   PIC32_IPC_IS2(0) | PIC32_IPC_IS3(0) ;\n    IPC(0) = ipc;\n    IPC(1) = ipc;\n    IPC(2) = ipc;\n    IPC(3) = ipc;\n    IPC(4) = ipc;\n    IPC(5) = ipc;\n    IPC(6) = ipc;\n    IPC(7) = ipc;\n    IPC(8) = ipc;\n    IPC(9) = ipc;\n    IPC(10) = ipc;\n    IPC(11) = ipc;\n    IPC(12) = ipc;\n\n    /*\n     * Setup wait states.\n     */\n    CHECON = 2;\n    BMXCONCLR = 0x40;\n    CHECONSET = 0x30;\n\n    /* Disable JTAG port, to use it for i/o. */\n    DDPCON = 0;\n\n    /* Use all B ports as digital. */\n    AD1PCFG = ~0;\n\n    /* Config register: enable kseg0 caching. */\n    mips_write_c0_register(C0_CONFIG, 0,\n    mips_read_c0_register(C0_CONFIG, 0) | 3);\n\n    /* Kernel mode, interrupts disabled.  */\n    mips_write_c0_register(C0_STATUS, 0, ST_CU0);\n    mips_ehb();\n\n    /*\n     * Configure LED pins.\n     */\n#ifdef LED_TTY_PORT                     /* Terminal i/o */\n    LED_TTY_OFF();\n    TRIS_CLR(LED_TTY_PORT) = 1 << LED_TTY_PIN;\n#endif\n#ifdef LED_DISK_PORT                    /* Disk i/o */\n    LED_DISK_OFF();\n    TRIS_CLR(LED_DISK_PORT) = 1 << LED_DISK_PIN;\n#endif\n#ifdef LED_KERNEL_PORT                  /* Kernel activity */\n    LED_KERNEL_OFF();\n    TRIS_CLR(LED_KERNEL_PORT) = 1 << LED_KERNEL_PIN;\n#endif\n#ifdef LED_SWAP_PORT                    /* Auxiliary */\n    LED_SWAP_OFF();\n    TRIS_CLR(LED_SWAP_PORT) = 1 << LED_SWAP_PIN;\n#endif\n#ifdef GPIO_CLEAR_PORT                  /* Clear pin */\n    LAT_CLR(GPIO_CLEAR_PORT) = 1 << GPIO_CLEAR_PIN;\n    TRIS_CLR(GPIO_CLEAR_PORT) = 1 << GPIO_CLEAR_PIN;\n#endif\n#ifdef POWER_ENABLED\n    power_init();\n#endif\n\n    /* SETVAL(0); */\n\n    /* Initialize .data + .bss segments by zeroes. */\n    bzero(&__data_start, KERNEL_DATA_SIZE - 96);\n\n#if __MPLABX__\n    /* Microchip C32 compiler generates a .dinit table with\n     * initialization values for .data segment. */\n    extern const unsigned _dinit_addr[];\n    unsigned const *dinit = &_dinit_addr[0];\n    for (;;) {\n        char *dst = (char*) (*dinit++);\n        if (dst == 0)\n            break;\n\n        unsigned nbytes = *dinit++;\n        unsigned fmt = *dinit++;\n        if (fmt == 0) {                 /* Clear */\n            do {\n                *dst++ = 0;\n            } while (--nbytes > 0);\n        } else {                        /* Copy */\n            char *src = (char*) dinit;\n            do {\n                *dst++ = *src++;\n            } while (--nbytes > 0);\n            dinit = (unsigned*) ((unsigned) (src + 3) & ~3);\n        }\n    }\n#else\n    /* Copy the .data image from flash to ram.\n     * Linker places it at the end of .text segment. */\n    extern unsigned _edata;\n    unsigned *src = (unsigned*) &_etext;\n    unsigned *dest = &__data_start;\n    unsigned *limit = &_edata;\n    while (dest < limit) {\n        /* printf(\"copy %08x from (%08x) to (%08x)\\n\", *src, src, dest); */\n        *dest++ = *src++;\n    }\n\n#ifdef KERNEL_EXECUTABLE_RAM\n    /* Copy code that must run out of ram (due to timing restrictions)\n     * from flash to the executable section of kernel ram.\n     * This was added to support swap on sdram */\n\n    extern void _ramfunc_image_begin();\n    extern void _ramfunc_begin();\n    extern void _ramfunc_end();\n\n    unsigned *src1 = (unsigned*) &_ramfunc_image_begin;\n    unsigned *dest1 = (unsigned*)&_ramfunc_begin;\n    unsigned *limit1 = (unsigned*)&_ramfunc_end;\n    /* printf(\"copy from (%08x) to (%08x)\\n\", src1, dest1); */\n    while (dest1 < limit1) {\n        *dest1++ = *src1++;\n    }\n#endif\n#endif /* __MPLABX__ */\n\n    /*\n     * Setup peripheral bus clock divisor.\n     */\n    unsigned osccon = OSCCON & ~PIC32_OSCCON_PBDIV_MASK;\n#if BUS_DIV == 1\n    osccon |= PIC32_OSCCON_PBDIV_1;\n#elif BUS_DIV == 2\n    osccon |= PIC32_OSCCON_PBDIV_2;\n#elif BUS_DIV == 4\n    osccon |= PIC32_OSCCON_PBDIV_4;\n#elif BUS_DIV == 8\n    osccon |= PIC32_OSCCON_PBDIV_8;\n#else\n#error Incorrect BUS_DIV value!\n#endif\n    /* Unlock access to OSCCON register */\n    SYSKEY = 0;\n    SYSKEY = 0xaa996655;\n    SYSKEY = 0x556699aa;\n\n    OSCCON = osccon;\n\n    /*\n     * Early setup for console devices.\n     */\n#if CONS_MAJOR == UART_MAJOR\n    uartinit(CONS_MINOR);\n#endif\n#if CONS_MAJOR == UARTUSB_MAJOR\n    usbinit();\n#endif\n\n    /* Get total RAM size. */\n    physmem = BMXDRMSZ;\n\n    /*\n     * When button 1 is pressed - boot to single user mode.\n     */\n    boothowto = 0;\n    if (button1_pressed()) {\n        boothowto |= RB_SINGLE;\n    }\n}\n\nstatic void cpuidentify()\n{\n    unsigned devid = DEVID, osccon = OSCCON;\n    static const char pllmult[]  = { 15, 16, 17, 18, 19, 20, 21, 24 };\n    static const char plldiv[]   = { 1, 2, 3, 4, 5, 6, 10, 12 };\n    static const char *poscmod[] = { \"external\", \"XT crystal\",\n                                     \"HS crystal\", \"(disabled)\" };\n\n    printf(\"cpu: \");\n    switch (devid & 0x0fffffff) {\n    case 0x04307053:\n        cpu_pins = 100;\n        copystr(\"795F512L\", cpu_model, sizeof(cpu_model), NULL);\n        printf(\"795F512L\");\n        break;\n    case 0x0430E053:\n        cpu_pins = 64;\n        copystr(\"795F512H\", cpu_model, sizeof(cpu_model), NULL);\n        printf(\"795F512H\");\n        break;\n    case 0x04341053:\n        cpu_pins = 100;\n        copystr(\"695F512L\", cpu_model, sizeof(cpu_model), NULL);\n        printf(\"695F512L\");\n        break;\n    case 0x04325053:\n        cpu_pins = 64;\n        copystr(\"695F512H\", cpu_model, sizeof(cpu_model), NULL);\n        printf(\"695F512H\");\n        break;\n    default:\n        /* Assume 100-pin package. */\n        copystr(\"PIC32 device unknown\", cpu_model, sizeof(cpu_model), NULL);\n        cpu_pins = 100;\n        printf(\"DevID %08x\", devid);\n    }\n    printf(\" %u MHz, bus %u MHz\\n\", CPU_KHZ/1000, BUS_KHZ/1000);\n\n    /* COSC: current oscillator selection bits */\n    printf(\"oscillator: \");\n    switch (osccon >> 12 & 7) {\n    case 0:\n        printf(\"internal Fast RC\\n\");\n        break;\n    case 1:\n        printf(\"internal Fast RC, PLL div 1:%d mult x%d\\n\",\n            plldiv [DEVCFG2 & 7], pllmult [osccon >> 16 & 7]);\n        break;\n    case 2:\n        printf(\"%s\\n\", poscmod [DEVCFG1 >> 8 & 3]);\n        break;\n    case 3:\n        printf(\"%s, PLL div 1:%d mult x%d\\n\",\n            poscmod [DEVCFG1 >> 8 & 3],\n            plldiv [DEVCFG2 & 7], pllmult [osccon >> 16 & 7]);\n        break;\n    case 4:\n        printf(\"secondary\\n\");\n        break;\n    case 5:\n        printf(\"internal Low-Power RC\\n\");\n        break;\n    case 6:\n        printf(\"internal Fast RC, divided 1:16\\n\");\n        break;\n    case 7:\n        printf(\"internal Fast RC, divided\\n\");\n        break;\n    }\n}\n\n/*\n * Check whether the controller has been successfully initialized.\n */\nstatic int\nis_controller_alive(driver, unit)\n    struct driver *driver;\n    int unit;\n{\n    struct conf_ctlr *ctlr;\n\n    /* No controller - that's OK. */\n    if (driver == 0)\n        return 1;\n\n    for (ctlr = conf_ctlr_init; ctlr->ctlr_driver; ctlr++) {\n        if (ctlr->ctlr_driver == driver &&\n            ctlr->ctlr_unit == unit &&\n            ctlr->ctlr_alive)\n        {\n            return 1;\n        }\n    }\n    return 0;\n}\n\n/*\n * Configure all controllers and devices as specified\n * in the kernel configuration file.\n */\nvoid\nconfig(void)\n{\n    struct conf_ctlr *ctlr;\n    struct conf_device *dev;\n\n    cpuidentify();\n\n    /* Probe and initialize controllers first. */\n    for (ctlr = conf_ctlr_init; ctlr->ctlr_driver; ctlr++) {\n        if ((*ctlr->ctlr_driver->d_init)(ctlr)) {\n            ctlr->ctlr_alive = 1;\n        }\n    }\n\n    /* Probe and initialize devices. */\n    for (dev = conf_device_init; dev->dev_driver; dev++) {\n        if (is_controller_alive(dev->dev_cdriver, dev->dev_ctlr)) {\n            if ((*dev->dev_driver->d_init)(dev)) {\n                dev->dev_alive = 1;\n            }\n        }\n    }\n}\n\n/*\n * Sit and wait for something to happen...\n */\nvoid\nidle()\n{\n    /* Indicate that no process is running. */\n    noproc = 1;\n\n    /* Set SPL low so we can be interrupted. */\n    int x = spl0();\n\n    /* Wait for something to happen. */\n    asm volatile (\"wait\");\n\n    /* Restore previous SPL. */\n    splx(x);\n}\n\nvoid\nboot(dev, howto)\n    register dev_t dev;\n    register int howto;\n{\n    if ((howto & RB_NOSYNC) == 0 && waittime < 0 && bfreelist[0].b_forw) {\n        register struct fs *fp;\n        register struct buf *bp;\n        int iter, nbusy;\n\n        /*\n         * Force the root filesystem's superblock to be updated,\n         * so the date will be as current as possible after\n         * rebooting.\n         */\n        fp = getfs(rootdev);\n        if (fp)\n            fp->fs_fmod = 1;\n        waittime = 0;\n        printf(\"syncing disks... \");\n        (void) splnet();\n        sync();\n        for (iter = 0; iter < 20; iter++) {\n            nbusy = 0;\n            for (bp = &buf[NBUF]; --bp >= buf; )\n                if (bp->b_flags & B_BUSY)\n                    nbusy++;\n            if (nbusy == 0)\n                break;\n            printf(\"%d \", nbusy);\n            udelay(40000L * iter);\n        }\n        printf(\"done\\n\");\n    }\n    (void) splhigh();\n    if (! (howto & RB_HALT)) {\n        if ((howto & RB_DUMP) && dumpdev != NODEV) {\n            /*\n             * Take a dump of memory by calling (*dump)(),\n             * which must correspond to dumpdev.\n             * It should dump from dumplo blocks to the end\n             * of memory or to the end of the logical device.\n             */\n            (*dump)(dumpdev);\n        }\n        /* Restart from dev, howto */\n#ifdef UARTUSB_ENABLED\n        /* Disable USB module, and wait awhile for the USB cable\n         * capacitance to discharge down to disconnected (SE0) state.\n         */\n        U1CON = 0x0000;\n        udelay(1000);\n\n        /* Stop DMA */\n        if (! (DMACON & 0x1000)) {\n            DMACONSET = 0x1000;\n            while (DMACON & 0x800)\n                continue;\n        }\n#endif\n        /* Unlock access to reset register */\n        SYSKEY = 0;\n        SYSKEY = 0xaa996655;\n        SYSKEY = 0x556699aa;\n\n        /* Reset microcontroller */\n        RSWRSTSET = 1;\n        (void) RSWRST;\n    }\n    printf(\"halted\\n\");\n\n    if (howto & RB_BOOTLOADER) {\n        printf(\"entering bootloader\\n\");\n        BLRKEY = 0x12345678;\n        /* Unlock access to reset register */\n        SYSKEY = 0;\n        SYSKEY = 0xaa996655;\n        SYSKEY = 0x556699aa;\n\n        /* Reset microcontroller */\n        RSWRSTSET = 1;\n        (void) RSWRST;\n    }\n\n#ifdef HALTREBOOT\n    printf(\"press any key to reboot...\");\n    cngetc();\n\n    /* Unlock access to reset register */\n    SYSKEY = 0;\n    SYSKEY = 0xaa996655;\n    SYSKEY = 0x556699aa;\n\n    /* Reset microcontroller */\n    RSWRSTSET = 1;\n    (void) RSWRST;\n#endif\n\n    for (;;) {\n#ifdef UARTUSB_ENABLED\n        usb_device_tasks();\n        cdc_consume(0);\n        cdc_tx_service();\n#else\n#ifdef POWER_ENABLED\n        if (howto & RB_POWEROFF)\n            power_off();\n#endif\n        asm volatile (\"wait\");\n#endif\n    }\n    /*NOTREACHED*/\n}\n\n/*\n * Microsecond delay routine for MIPS processor.\n *\n * We rely on a hardware register Count, which is increased\n * every next clock cycle, i.e. at rate CPU_KHZ/2 per millisecond.\n */\nvoid\nudelay(usec)\n    u_int usec;\n{\n    unsigned now = mips_read_c0_register(C0_COUNT, 0);\n    unsigned final = now + usec * (CPU_KHZ / 1000) / 2;\n\n    for (;;) {\n        now = mips_read_c0_register(C0_COUNT, 0);\n\n        /* This comparison is valid only when using a signed type. */\n        if ((int) (now - final) >= 0)\n            break;\n    }\n}\n\n/*\n * Control LEDs, installed on the board.\n */\nvoid led_control(int mask, int on)\n{\n#ifdef LED_SWAP_PORT\n    if (mask & LED_SWAP) {       /* Auxiliary */\n        if (on) LED_SWAP_ON();\n        else    LED_SWAP_OFF();\n    }\n#endif\n#ifdef LED_DISK_PORT\n    if (mask & LED_DISK) {      /* Disk i/o */\n        if (on) LED_DISK_ON();\n        else    LED_DISK_OFF();\n    }\n#endif\n#ifdef LED_KERNEL_PORT\n    if (mask & LED_KERNEL) {    /* Kernel activity */\n        if (on) LED_KERNEL_ON();\n        else    LED_KERNEL_OFF();\n    }\n#endif\n#ifdef LED_TTY_PORT\n    if (mask & LED_TTY) {       /* Terminal i/o */\n        if (on) LED_TTY_ON();\n        else    LED_TTY_OFF();\n    }\n#endif\n}\n\n/*\n * Increment user profiling counters.\n */\nvoid addupc(caddr_t pc, struct uprof *pbuf, int ticks)\n{\n    unsigned indx;\n\n    if (pc < (caddr_t) pbuf->pr_off)\n        return;\n\n    indx = pc - (caddr_t) pbuf->pr_off;\n    indx = (indx * pbuf->pr_scale) >> 16;\n    if (indx >= pbuf->pr_size)\n        return;\n\n    pbuf->pr_base[indx] += ticks;\n}\n\n/*\n * Find the index of the least significant set bit in the 32-bit word.\n * If LSB bit is set - return 1.\n * If only MSB bit is set - return 32.\n * Return 0 when no bit is set.\n */\nint\nffs(i)\n    u_long i;\n{\n    if (i != 0)\n        i = 32 - mips_clz(i & -i);\n    return i;\n}\n\n/*\n * Copy a null terminated string from one point to another.\n * Returns zero on success, ENOENT if maxlength exceeded.\n * If lencopied is non-zero, *lencopied gets the length of the copy\n * (including the null terminating byte).\n */\nint\ncopystr(src, dest, maxlength, lencopied)\n    register caddr_t src, dest;\n    register u_int maxlength, *lencopied;\n{\n    caddr_t dest0 = dest;\n    int error = ENOENT;\n\n    if (maxlength != 0) {\n        while ((*dest++ = *src++) != '\\0') {\n            if (--maxlength == 0) {\n                /* Failed. */\n                goto done;\n            }\n        }\n        /* Succeeded. */\n        error = 0;\n    }\ndone:\n    if (lencopied != 0)\n        *lencopied = dest - dest0;\n    return error;\n}\n\n/*\n * Calculate the length of a string.\n */\nsize_t\nstrlen(s)\n    register const char *s;\n{\n    const char *s0 = s;\n\n    while (*s++ != '\\0')\n        ;\n    return s - s0 - 1;\n}\n\n/*\n * Return 0 if a user address is valid.\n * There are two memory regions allowed for user: flash and RAM.\n */\nint\nbaduaddr(addr)\n    register caddr_t addr;\n{\n    if (addr >= (caddr_t) USER_FLASH_START &&\n        addr < (caddr_t) USER_FLASH_END)\n        return 0;\n    if (addr >= (caddr_t) USER_DATA_START &&\n        addr < (caddr_t) USER_DATA_END)\n        return 0;\n    return 1;\n}\n\n/*\n * Return 0 if a kernel address is valid.\n * There are two memory regions allowed for kernel: RAM and flash.\n */\nint\nbadkaddr(addr)\n    register caddr_t addr;\n{\n    if (addr >= (caddr_t) KERNEL_DATA_START &&\n        addr < (caddr_t) KERNEL_DATA_END)\n        return 0;\n    if (addr >= (caddr_t) KERNEL_FLASH_START &&\n        addr < (caddr_t) KERNEL_FLASH_END)\n        return 0;\n    return 1;\n}\n\n/*\n * Insert the specified element into a queue immediately after\n * the specified predecessor element.\n */\nvoid insque(void *element, void *predecessor)\n{\n    struct que {\n        struct que *q_next;\n        struct que *q_prev;\n    };\n    register struct que *e = (struct que *) element;\n    register struct que *prev = (struct que *) predecessor;\n\n    e->q_prev = prev;\n    e->q_next = prev->q_next;\n    prev->q_next->q_prev = e;\n    prev->q_next = e;\n}\n\n/*\n * Remove the specified element from the queue.\n */\nvoid remque(void *element)\n{\n    struct que {\n        struct que *q_next;\n        struct que *q_prev;\n    };\n    register struct que *e = (struct que *) element;\n\n    e->q_prev->q_next = e->q_next;\n    e->q_next->q_prev = e->q_prev;\n}\n\n/*\n * Compare strings.\n */\nint strncmp(const char *s1, const char *s2, size_t n)\n{\n    register int ret, tmp;\n\n    if (n == 0)\n        return 0;\n    do {\n        ret = *s1++ - (tmp = *s2++);\n    } while ((ret == 0) && (tmp != 0) && --n);\n    return ret;\n}\n\n/* Nonzero if pointer is not aligned on a \"sz\" boundary.  */\n#define UNALIGNED(p, sz)    ((unsigned) (p) & ((sz) - 1))\n\n/*\n * Copy data from the memory region pointed to by src0 to the memory\n * region pointed to by dst0.\n * If the regions overlap, the behavior is undefined.\n */\nvoid\nbcopy(const void *src0, void *dst0, size_t nbytes)\n{\n    unsigned char *dst = dst0;\n    const unsigned char *src = src0;\n    unsigned *aligned_dst;\n    const unsigned *aligned_src;\n\n    /* printf(\"bcopy(%08x, %08x, %d)\\n\", src0, dst0, nbytes); */\n    /* If the size is small, or either SRC or DST is unaligned,\n     * then punt into the byte copy loop.  This should be rare.  */\n    if (nbytes >= 4*sizeof(unsigned) &&\n        ! UNALIGNED(src, sizeof(unsigned)) &&\n        ! UNALIGNED(dst, sizeof(unsigned))) {\n        aligned_dst = (unsigned*) dst;\n        aligned_src = (const unsigned*) src;\n\n        /* Copy 4X unsigned words at a time if possible.  */\n        while (nbytes >= 4*sizeof(unsigned)) {\n            *aligned_dst++ = *aligned_src++;\n            *aligned_dst++ = *aligned_src++;\n            *aligned_dst++ = *aligned_src++;\n            *aligned_dst++ = *aligned_src++;\n            nbytes -= 4*sizeof(unsigned);\n        }\n\n        /* Copy one unsigned word at a time if possible.  */\n        while (nbytes >= sizeof(unsigned)) {\n            *aligned_dst++ = *aligned_src++;\n            nbytes -= sizeof(unsigned);\n        }\n\n        /* Pick up any residual with a byte copier.  */\n        dst = (unsigned char*) aligned_dst;\n        src = (const unsigned char*) aligned_src;\n    }\n\n    while (nbytes--)\n        *dst++ = *src++;\n}\n\nvoid *\nmemcpy(void *dst, const void *src, size_t nbytes)\n{\n    bcopy(src, dst, nbytes);\n    return dst;\n}\n\n/*\n * Fill the array with zeroes.\n */\nvoid\nbzero(void *dst0, size_t nbytes)\n{\n    unsigned char *dst;\n    unsigned *aligned_dst;\n\n    dst = (unsigned char*) dst0;\n    while (UNALIGNED(dst, sizeof(unsigned))) {\n        *dst++ = 0;\n        if (--nbytes == 0)\n            return;\n    }\n    if (nbytes >= sizeof(unsigned)) {\n        /* If we get this far, we know that nbytes is large and dst is word-aligned. */\n        aligned_dst = (unsigned*) dst;\n\n        while (nbytes >= 4*sizeof(unsigned)) {\n            *aligned_dst++ = 0;\n            *aligned_dst++ = 0;\n            *aligned_dst++ = 0;\n            *aligned_dst++ = 0;\n            nbytes -= 4*sizeof(unsigned);\n        }\n        while (nbytes >= sizeof(unsigned)) {\n            *aligned_dst++ = 0;\n            nbytes -= sizeof(unsigned);\n        }\n        dst = (unsigned char*) aligned_dst;\n    }\n\n    /* Pick up the remainder with a bytewise loop.  */\n    while (nbytes--)\n        *dst++ = 0;\n}\n\n/*\n * Compare not more than nbytes of data pointed to by m1 with\n * the data pointed to by m2. Return an integer greater than, equal to or\n * less than zero according to whether the object pointed to by\n * m1 is greater than, equal to or less than the object\n * pointed to by m2.\n */\nint\nbcmp(const void *m1, const void *m2, size_t nbytes)\n{\n    const unsigned char *s1 = (const unsigned char*) m1;\n    const unsigned char *s2 = (const unsigned char*) m2;\n    const unsigned *aligned1, *aligned2;\n\n    /* If the size is too small, or either pointer is unaligned,\n     * then we punt to the byte compare loop.  Hopefully this will\n     * not turn up in inner loops.  */\n    if (nbytes >= 4*sizeof(unsigned) &&\n        ! UNALIGNED(s1, sizeof(unsigned)) &&\n        ! UNALIGNED(s2, sizeof(unsigned))) {\n        /* Otherwise, load and compare the blocks of memory one\n           word at a time.  */\n        aligned1 = (const unsigned*) s1;\n        aligned2 = (const unsigned*) s2;\n        while (nbytes >= sizeof(unsigned)) {\n            if (*aligned1 != *aligned2)\n                break;\n            aligned1++;\n            aligned2++;\n            nbytes -= sizeof(unsigned);\n        }\n\n        /* check remaining characters */\n        s1 = (const unsigned char*) aligned1;\n        s2 = (const unsigned char*) aligned2;\n    }\n    while (nbytes--) {\n        if (*s1 != *s2)\n            return *s1 - *s2;\n        s1++;\n        s2++;\n    }\n    return 0;\n}\n\nint\ncopyout(caddr_t from, caddr_t to, u_int nbytes)\n{\n    /* printf(\"copyout(from=%p, to=%p, nbytes=%u)\\n\", from, to, nbytes); */\n    if (baduaddr(to) || baduaddr(to + nbytes - 1))\n        return EFAULT;\n    bcopy(from, to, nbytes);\n    return 0;\n}\n\nint copyin (caddr_t from, caddr_t to, u_int nbytes)\n{\n    if (baduaddr(from) || baduaddr(from + nbytes - 1))\n        return EFAULT;\n    bcopy(from, to, nbytes);\n    return 0;\n}\n\n/*\n * Routines for access to general purpose I/O pins.\n */\nstatic const char pin_name[16] = \"?ABCDEFG????????\";\n\nvoid gpio_set_input(int pin)\n{\n    struct gpioreg *port = (struct gpioreg*) &TRISA;\n\n    port += (pin >> 4 & 15) - 1;\n    port->trisset = (1 << (pin & 15));\n}\n\nvoid gpio_set_output(int pin)\n{\n    struct gpioreg *port = (struct gpioreg*) &TRISA;\n\n    port += (pin >> 4 & 15) - 1;\n    port->trisclr = (1 << (pin & 15));\n}\n\nvoid gpio_set(int pin)\n{\n    struct gpioreg *port = (struct gpioreg*) &TRISA;\n\n    port += (pin >> 4 & 15) - 1;\n    port->latset = (1 << (pin & 15));\n}\n\nvoid gpio_clr(int pin)\n{\n    struct gpioreg *port = (struct gpioreg*) &TRISA;\n\n    port += (pin >> 4 & 15) - 1;\n    port->latclr = (1 << (pin & 15));\n}\n\nint gpio_get(int pin)\n{\n    struct gpioreg *port = (struct gpioreg*) &TRISA;\n\n    port += (pin >> 4 & 15) - 1;\n    return ((port->port & (1 << (pin & 15))) ? 1 : 0);\n}\n\nchar gpio_portname(int pin)\n{\n    return pin_name[(pin >> 4) & 15];\n}\n\nint gpio_pinno(int pin)\n{\n    return pin & 15;\n}\n"
  },
  {
    "path": "sys/arch/pic32/pic32/sig_machdep.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)machdep.c\t2.4 (2.11BSD) 1999/9/13\n */\n\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/signalvar.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/buf.h>\n#include <sys/map.h>\n#include <sys/syslog.h>\n#include <machine/frame.h>\n\n#if 0\n#define DIAGNOSTIC\n#endif\n\n/*\n * Send an interrupt to process.\n *\n * Stack is set up to allow trampoline code stored at u.u_sigtramp (as\n * specified by the user process) to call the user's real signal catch\n * routine, followed by sys sigreturn to the sigreturn routine below\n * (see lib/libc/mips/sys/sigaction.S).  After sigreturn resets the signal\n * mask, the stack, and the frame pointer, it returns to the user specified\n * pc and regs.\n */\nvoid\nsendsig (p, sig, mask)\n    sig_t p;\n    int sig;\n    long mask;\n{\n    struct sigframe {\n        int     sf_space [4];\n        struct  sigcontext sf_sc;\n    };\n    struct trapframe *regs = u.u_frame;\n    register struct sigframe *sfp;\n    int oonstack;\n\n#ifdef DIAGNOSTIC\n    printf(\"(%u)sendsig %d, mask=%#x, handler=%#x, tramp=%#x\\n\",\n        u.u_procp->p_pid, sig, mask, p, u.u_sigtramp);\n#endif\n    oonstack = u.u_sigstk.ss_flags & SA_ONSTACK;\n\n    /*\n     * Allocate and validate space for the signal frame.\n     */\n    if ((u.u_psflags & SAS_ALTSTACK) &&\n         ! (u.u_sigstk.ss_flags & SA_ONSTACK) &&\n        (u.u_sigonstack & sigmask(sig))) {\n        sfp = (struct sigframe*) (u.u_sigstk.ss_base +\n            u.u_sigstk.ss_size);\n        u.u_sigstk.ss_flags |= SA_ONSTACK;\n    } else\n        sfp = (struct sigframe*) regs->tf_sp;\n\n    sfp--;\n    if (! (u.u_sigstk.ss_flags & SA_ONSTACK)) {\n        if ((caddr_t) sfp < (caddr_t) u.u_procp->p_daddr + u.u_dsize) {\n            /*\n             * Process has trashed its stack; give it an illegal\n             * instruction violation to halt it in its tracks.\n             */\n            fatalsig(SIGILL);\n            return;\n        }\n        if (u.u_procp->p_ssize < USER_DATA_END - (unsigned) sfp) {\n            u.u_procp->p_ssize = USER_DATA_END - (unsigned) sfp;\n            u.u_procp->p_saddr = (unsigned) sfp;\n            u.u_ssize = u.u_procp->p_ssize;\n        }\n    }\n\n    /*\n     * Build the signal context to be used by sigreturn.\n     */\n    sfp->sf_sc.sc_onstack = oonstack;\n    sfp->sf_sc.sc_mask = mask;\n    sfp->sf_sc.sc_r1  = regs->tf_r1;\n    sfp->sf_sc.sc_r2  = regs->tf_r2;\n    sfp->sf_sc.sc_r3  = regs->tf_r3;\n    sfp->sf_sc.sc_r4  = regs->tf_r4;\n    sfp->sf_sc.sc_r5  = regs->tf_r5;\n    sfp->sf_sc.sc_r6  = regs->tf_r6;\n    sfp->sf_sc.sc_r7  = regs->tf_r7;\n    sfp->sf_sc.sc_r8  = regs->tf_r8;\n    sfp->sf_sc.sc_r9  = regs->tf_r9;\n    sfp->sf_sc.sc_r10 = regs->tf_r10;\n    sfp->sf_sc.sc_r11 = regs->tf_r11;\n    sfp->sf_sc.sc_r12 = regs->tf_r12;\n    sfp->sf_sc.sc_r13 = regs->tf_r13;\n    sfp->sf_sc.sc_r14 = regs->tf_r14;\n    sfp->sf_sc.sc_r15 = regs->tf_r15;\n    sfp->sf_sc.sc_r16 = regs->tf_r16;\n    sfp->sf_sc.sc_r17 = regs->tf_r17;\n    sfp->sf_sc.sc_r18 = regs->tf_r18;\n    sfp->sf_sc.sc_r19 = regs->tf_r19;\n    sfp->sf_sc.sc_r20 = regs->tf_r20;\n    sfp->sf_sc.sc_r21 = regs->tf_r21;\n    sfp->sf_sc.sc_r22 = regs->tf_r22;\n    sfp->sf_sc.sc_r23 = regs->tf_r23;\n    sfp->sf_sc.sc_r24 = regs->tf_r24;\n    sfp->sf_sc.sc_r25 = regs->tf_r25;\n    sfp->sf_sc.sc_gp  = regs->tf_gp;\n    sfp->sf_sc.sc_sp  = regs->tf_sp;\n    sfp->sf_sc.sc_fp  = regs->tf_fp;\n    sfp->sf_sc.sc_ra  = regs->tf_ra;\n    sfp->sf_sc.sc_lo  = regs->tf_lo;\n    sfp->sf_sc.sc_hi  = regs->tf_hi;\n    sfp->sf_sc.sc_pc  = regs->tf_pc;\n\n    /* Call signal handler */\n    regs->tf_r4 = sig;                      /* $a0 - signal number */\n    regs->tf_r5 = u.u_code;                 /* $a1 - code */\n    regs->tf_r6 = (int) &sfp->sf_sc;        /* $a2 - address of sigcontext */\n    regs->tf_ra = (int) u.u_sigtramp;       /* $ra - sigtramp */\n    regs->tf_sp = (int) sfp;\n    regs->tf_pc = (int) p;\n#ifdef DIAGNOSTIC\n    printf(\"    ...call handler %p (sig=%d, code=%#x, context=%p)\\n\",\n        p, sig, u.u_code, &sfp->sf_sc);\n    printf(\"    ...stack=%p, return to %p\\n\", sfp, u.u_sigtramp);\n#endif\n}\n\n/*\n * System call to cleanup state after a signal\n * has been taken.  Reset signal mask and\n * stack state from context left by sendsig (above).\n * Return to previous pc and ps as specified by\n * context left by sendsig. Check carefully to\n * make sure that the user has not modified the\n * ps to gain improper priviledges or to cause\n * a machine fault.\n */\nvoid\nsigreturn()\n{\n    struct trapframe *regs = u.u_frame;\n    register struct sigcontext *scp =\n        (struct sigcontext*) (regs->tf_sp + 16);\n\n#ifdef DIAGNOSTIC\n    printf(\"(%u)sigreturn stack=%#x, context=%p\\n\",\n        u.u_procp->p_pid, regs->tf_sp, scp);\n#endif\n    if (baduaddr ((caddr_t) scp) ||\n        baduaddr ((caddr_t) scp + sizeof(*scp))) {\n        u.u_error = EFAULT;\n        return;\n    }\n    u.u_error = EJUSTRETURN;\n    if (scp->sc_onstack & SA_ONSTACK)\n        u.u_sigstk.ss_flags |= SA_ONSTACK;\n    else\n        u.u_sigstk.ss_flags &= ~SA_ONSTACK;\n    u.u_procp->p_sigmask = scp->sc_mask & ~sigcantmask;\n\n    /* Return from signal handler */\n    regs->tf_r1 = scp->sc_r1;\n    regs->tf_r2 = scp->sc_r2;\n    regs->tf_r3 = scp->sc_r3;\n    regs->tf_r4 = scp->sc_r4;\n    regs->tf_r5 = scp->sc_r5;\n    regs->tf_r6 = scp->sc_r6;\n    regs->tf_r7 = scp->sc_r7;\n    regs->tf_r8 = scp->sc_r8;\n    regs->tf_r9 = scp->sc_r9;\n    regs->tf_r10 = scp->sc_r10;\n    regs->tf_r11 = scp->sc_r11;\n    regs->tf_r12 = scp->sc_r12;\n    regs->tf_r13 = scp->sc_r13;\n    regs->tf_r14 = scp->sc_r14;\n    regs->tf_r15 = scp->sc_r15;\n    regs->tf_r16 = scp->sc_r16;\n    regs->tf_r17 = scp->sc_r17;\n    regs->tf_r18 = scp->sc_r18;\n    regs->tf_r19 = scp->sc_r19;\n    regs->tf_r20 = scp->sc_r20;\n    regs->tf_r21 = scp->sc_r21;\n    regs->tf_r22 = scp->sc_r22;\n    regs->tf_r23 = scp->sc_r23;\n    regs->tf_r24 = scp->sc_r24;\n    regs->tf_r25 = scp->sc_r25;\n    regs->tf_gp = scp->sc_gp;\n    regs->tf_sp = scp->sc_sp;\n    regs->tf_fp = scp->sc_fp;\n    regs->tf_ra = scp->sc_ra;\n    regs->tf_lo = scp->sc_lo;\n    regs->tf_hi = scp->sc_hi;\n    regs->tf_pc = scp->sc_pc;\n#ifdef DIAGNOSTIC\n    printf(\"    ...to %#x, stack %#x\\n\", regs->tf_pc, regs->tf_sp);\n#endif\n}\n"
  },
  {
    "path": "sys/arch/pic32/pic32/sysctl.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)kern_pdp.c\t1.4 (2.11BSD) 1998/5/12\n */\n\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/ioctl.h>\n#include <sys/proc.h>\n#include <sys/kernel.h>\n#include <sys/file.h>\n#include <sys/inode.h>\n#include <sys/sysctl.h>\n#include <machine/cpu.h>\n#include <sys/tty.h>\n#include <sys/systm.h>\n#include <sys/dk.h>\n#include <sys/vmsystm.h>\n#include <sys/ptrace.h>\n#include <sys/namei.h>\n#include <sys/vmmeter.h>\n#include <sys/map.h>\n#include <sys/conf.h>\n#ifdef PTY_ENABLED\n#   include <sys/pty.h>\n#endif\n\n/*\n * Errno messages.\n */\nstatic const char *errlist[] = {\n    \"Undefined error: 0\",                   /*  0 - ENOERROR */\n    \"Operation not permitted\",              /*  1 - EPERM */\n    \"No such file or directory\",            /*  2 - ENOENT */\n    \"No such process\",                      /*  3 - ESRCH */\n    \"Interrupted system call\",              /*  4 - EINTR */\n    \"Input/output error\",                   /*  5 - EIO */\n    \"Device not configured\",                /*  6 - ENXIO */\n    \"Argument list too long\",               /*  7 - E2BIG */\n    \"Exec format error\",                    /*  8 - ENOEXEC */\n    \"Bad file descriptor\",                  /*  9 - EBADF */\n    \"No child processes\",                   /* 10 - ECHILD */\n    \"No more processes\",                    /* 11 - EAGAIN */\n    \"Cannot allocate memory\",               /* 12 - ENOMEM */\n    \"Permission denied\",                    /* 13 - EACCES */\n    \"Bad address\",                          /* 14 - EFAULT */\n    \"Block device required\",                /* 15 - ENOTBLK */\n    \"Device busy\",                          /* 16 - EBUSY */\n    \"File exists\",                          /* 17 - EEXIST */\n    \"Cross-device link\",                    /* 18 - EXDEV */\n    \"Operation not supported by device\",    /* 19 - ENODEV */\n    \"Not a directory\",                      /* 20 - ENOTDIR */\n    \"Is a directory\",                       /* 21 - EISDIR */\n    \"Invalid argument\",                     /* 22 - EINVAL */\n    \"Too many open files in system\",        /* 23 - ENFILE */\n    \"Too many open files\",                  /* 24 - EMFILE */\n    \"Inappropriate ioctl for device\",       /* 25 - ENOTTY */\n    \"Text file busy\",                       /* 26 - ETXTBSY */\n    \"File too large\",                       /* 27 - EFBIG */\n    \"No space left on device\",              /* 28 - ENOSPC */\n    \"Illegal seek\",                         /* 29 - ESPIPE */\n    \"Read-only file system\",                /* 30 - EROFS */\n    \"Too many links\",                       /* 31 - EMLINK */\n    \"Broken pipe\",                          /* 32 - EPIPE */\n\n/* math software */\n    \"Numerical argument out of domain\",     /* 33 - EDOM */\n    \"Result too large\",                     /* 34 - ERANGE */\n\n/* non-blocking and interrupt i/o */\n    \"Resource temporarily unavailable\",     /* 35 - EWOULDBLOCK */\n    \"Operation now in progress\",            /* 36 - EINPROGRESS */\n    \"Operation already in progress\",        /* 37 - EALREADY */\n\n/* ipc/network software -- argument errors */\n    \"Socket operation on non-socket\",       /* 38 - ENOTSOCK */\n    \"Destination address required\",         /* 39 - EDESTADDRREQ */\n    \"Message too long\",                     /* 40 - EMSGSIZE */\n    \"Protocol wrong type for socket\",       /* 41 - EPROTOTYPE */\n    \"Protocol not available\",               /* 42 - ENOPROTOOPT */\n    \"Protocol not supported\",               /* 43 - EPROTONOSUPPORT */\n    \"Socket type not supported\",            /* 44 - ESOCKTNOSUPPORT */\n    \"Operation not supported\",              /* 45 - EOPNOTSUPP */\n    \"Protocol family not supported\",        /* 46 - EPFNOSUPPORT */\n                                            /* 47 - EAFNOSUPPORT */\n    \"Address family not supported by protocol family\",\n    \"Address already in use\",               /* 48 - EADDRINUSE */\n    \"Can't assign requested address\",       /* 49 - EADDRNOTAVAIL */\n\n/* ipc/network software -- operational errors */\n    \"Network is down\",                      /* 50 - ENETDOWN */\n    \"Network is unreachable\",               /* 51 - ENETUNREACH */\n    \"Network dropped connection on reset\",  /* 52 - ENETRESET */\n    \"Software caused connection abort\",     /* 53 - ECONNABORTED */\n    \"Connection reset by peer\",             /* 54 - ECONNRESET */\n    \"No buffer space available\",            /* 55 - ENOBUFS */\n    \"Socket is already connected\",          /* 56 - EISCONN */\n    \"Socket is not connected\",              /* 57 - ENOTCONN */\n    \"Can't send after socket shutdown\",     /* 58 - ESHUTDOWN */\n    \"Too many references: can't splice\",    /* 59 - ETOOMANYREFS */\n    \"Operation timed out\",                  /* 60 - ETIMEDOUT */\n    \"Connection refused\",                   /* 61 - ECONNREFUSED */\n\n    \"Too many levels of symbolic links\",    /* 62 - ELOOP */\n    \"File name too long\",                   /* 63 - ENAMETOOLONG */\n\n/* should be rearranged */\n    \"Host is down\",                         /* 64 - EHOSTDOWN */\n    \"No route to host\",                     /* 65 - EHOSTUNREACH */\n    \"Directory not empty\",                  /* 66 - ENOTEMPTY */\n\n/* quotas & mush */\n    \"Too many processes\",                   /* 67 - EPROCLIM */\n    \"Too many users\",                       /* 68 - EUSERS */\n    \"Disc quota exceeded\",                  /* 69 - EDQUOT */\n\n/* Network File System */\n    \"Stale NFS file handle\",                /* 70 - ESTALE */\n    \"Too many levels of remote in path\",    /* 71 - EREMOTE */\n    \"RPC struct is bad\",                    /* 72 - EBADRPC */\n    \"RPC version wrong\",                    /* 73 - ERPCMISMATCH */\n    \"RPC prog. not avail\",                  /* 74 - EPROGUNAVAIL */\n    \"Program version wrong\",                /* 75 - EPROGMISMATCH */\n    \"Bad procedure for program\",            /* 76 - EPROCUNAVAIL */\n\n    \"No locks available\",                   /* 77 - ENOLCK */\n    \"Function not implemented\",             /* 78 - ENOSYS */\n    \"Inappropriate file type or format\",    /* 79 - EFTYPE */\n    \"Authentication error\",                 /* 80 - EAUTH */\n    \"Need authenticator\",                   /* 81 - ENEEDAUTH */\n};\n\n/*\n * Kernel symbol name list.\n */\nstatic const struct {\n    const char *name;\n    int addr;\n} nlist[] = {\n    { \"_boottime\",      (int) &boottime     },  /* vmstat */\n    { \"_cnttys\",        (int) &cnttys       },  /* pstat */\n    { \"_cp_time\",       (int) &cp_time      },  /* iostat  vmstat */\n    { \"_dk_busy\",       (int) &dk_busy      },  /* iostat */\n    { \"_dk_name\",       (int) &dk_name      },  /* iostat  vmstat */\n    { \"_dk_ndrive\",     (int) &dk_ndrive    },  /* iostat  vmstat */\n    { \"_dk_unit\",       (int) &dk_unit      },  /* iostat  vmstat */\n    { \"_dk_bytes\",      (int) &dk_bytes     },  /* iostat */\n    { \"_dk_xfer\",       (int) &dk_xfer      },  /* iostat  vmstat */\n    { \"_file\",          (int) &file         },  /* pstat */\n    { \"_forkstat\",      (int) &forkstat     },  /* vmstat */\n#ifdef UCB_METER\n    { \"_freemem\",       (int) &freemem      },  /* vmstat */\n#endif\n    { \"_hz\",            (int) &hz           },  /* ps */\n    { \"_inode\",         (int) &inode        },  /* pstat */\n    { \"_ipc\",           (int) &ipc          },  /* ps */\n    { \"_lbolt\",         (int) &lbolt        },  /* ps */\n    { \"_memlock\",       (int) &memlock      },  /* ps */\n    { \"_nchstats\",      (int) &nchstats     },  /* vmstat */\n    { \"_nproc\",         (int) &nproc        },  /* ps      pstat */\n    { \"_nswap\",         (int) &nswap        },  /* pstat */\n    { \"_proc\",          (int) &proc         },  /* ps      pstat */\n    { \"_runin\",         (int) &runin        },  /* ps */\n    { \"_runout\",        (int) &runout       },  /* ps */\n    { \"_selwait\",       (int) &selwait      },  /* ps */\n    { \"_swapmap\",       (int) &swapmap      },  /* pstat */\n    { \"_tk_nin\",        (int) &tk_nin       },  /* iostat */\n    { \"_tk_nout\",       (int) &tk_nout      },  /* iostat */\n    { \"_total\",         (int) &total        },  /* vmstat */\n    { \"_u\",             (int) &u            },  /* ps */\n#ifdef PTY_ENABLED\n    { \"_npty\",          (int) &npty         },  /* pstat */\n    { \"_pt_tty\",        (int) &pt_tty       },  /* pstat */\n#endif\n#ifdef UCB_METER\n    { \"_rate\",          (int) &rate         },  /* vmstat */\n    { \"_sum\",           (int) &sum          },  /* vmstat */\n#endif\n    { \"_bdevsw\",        (int) &bdevsw       },  /* devupdate */\n    { \"_cdevsw\",        (int) &cdevsw       },  /* devupdate */\n    { \"_nblkdev\",       (int) &nblkdev      },  /* devupdate */\n    { \"_nchrdev\",       (int) &nchrdev      },  /* devupdate */\n    { 0, 0 },\n};\n\n/*\n * ucall allows user level code to call various kernel functions.\n * Autoconfig uses it to call the probe and attach routines of the\n * various device drivers.\n */\nvoid\nucall()\n{\n    register struct a {\n        int priority;\n        int (*routine)();\n        int arg1;\n        int arg2;\n    } *uap = (struct a *)u.u_arg;\n    int s;\n\n    if (!suser())\n        return;\n    switch (uap->priority) {\n    case 0:\n        s = spl0();\n        break;\n    default:\n        s = splhigh();\n        break;\n    }\n    u.u_rval = (*uap->routine) (uap->arg1, uap->arg2);\n    splx(s);\n}\n\n/*\n * Fetch the word at addr from flash memory or i/o port.\n * This system call is required on PIC32 because in user mode\n * the access to flash memory region is not allowed.\n */\nvoid\nufetch()\n{\n    unsigned addr = *(unsigned*) u.u_arg & ~3;\n\n    /* Check root privileges */\n    if (! suser())\n        return;\n\n    /* Low memory address - assume peripheral i/o space.  */\n    if (addr < 0x90000)\n        addr += 0xbf800000;\n\n    /* Check address */\n    if (! (addr >= 0x9d000000 && addr < 0x9d000000 + FLASH_SIZE) &&\n        ! (addr >= 0xbd000000 && addr < 0xbd000000 + FLASH_SIZE) &&\n\n        /* Boot flash memory */\n        ! (addr >= 0x9fc00000 && addr < 0x9fc00000 + 12*1024) &&\n        ! (addr >= 0xbfc00000 && addr < 0xbfc00000 + 12*1024) &&\n\n        /* Peripheral registers */\n        ! (addr >= 0xbf800000 && addr < 0xbf810000) &&\n        ! (addr >= 0xbf880000 && addr < 0xbf890000)) {\n        u.u_error = EFAULT;\n        return;\n    }\n    u.u_rval = *(unsigned*) addr;\n}\n\n/*\n * Store the word at addr of i/o port.\n */\nvoid\nustore()\n{\n    register struct a {\n        unsigned addr;\n        unsigned value;\n    } *uap = (struct a *)u.u_arg;\n    unsigned addr = uap->addr & ~3;\n\n    /* Check root privileges */\n    if (! suser())\n        return;\n\n    /* Low memory address - assume peripheral i/o space.  */\n    if (addr < 0x90000)\n        addr += 0xbf800000;\n\n    /* Check address */\n    if (! (addr >= 0xbf800000 && addr < 0xbf810000) &&\n        ! (addr >= 0xbf880000 && addr < 0xbf890000)) {\n        u.u_error = EFAULT;\n        return;\n    }\n    *(unsigned*) addr = uap->value;\n}\n\n/*\n * This was moved here when the TMSCP portion was added.  At that time it\n * became (even more) system specific and didn't belong in kern_sysctl.c\n */\nint\ncpu_sysctl (name, namelen, oldp, oldlenp, newp, newlen)\n    int *name;\n    u_int namelen;\n    void *oldp;\n    size_t *oldlenp;\n    void *newp;\n    size_t newlen;\n{\n    int i, khz;\n    dev_t dev;\n\n    switch (name[0]) {\n    case CPU_CONSDEV:\n        if (namelen != 1)\n            return ENOTDIR;\n        dev = makedev(CONS_MAJOR, CONS_MINOR);\n        return sysctl_rdstruct (oldp, oldlenp, newp, &dev, sizeof dev);\n#if NTMSCP > 0\n    case CPU_TMSCP:\n        /* All sysctl names at this level are terminal */\n        if (namelen != 2)\n            return ENOTDIR;\n        switch (name[1]) {\n        case TMSCP_CACHE:\n            return sysctl_int (oldp, oldlenp, newp,\n                newlen, &tmscpcache);\n        case TMSCP_PRINTF:\n            return sysctl_int (oldp, oldlenp, newp,\n                newlen, &tmscpprintf);\n        default:\n        }\n#endif\n    case CPU_ERRMSG:\n        if (namelen != 2)\n            return ENOTDIR;\n        if (name[1] < 1 ||\n            name[1] >= sizeof(errlist) / sizeof(errlist[0]))\n            return EOPNOTSUPP;\n        return sysctl_string(oldp, oldlenp, 0, 0,\n            (char*) errlist[name[1]],\n            1 + strlen(errlist[name[1]]));\n\n    case CPU_NLIST:\n        for (i=0; nlist[i].name; i++) {\n            if (strncmp (newp, nlist[i].name, newlen) == 0) {\n                int addr = nlist[i].addr;\n                if (! oldp)\n                    return 0;\n                if (*oldlenp < sizeof(int))\n                    return ENOMEM;\n                *oldlenp = sizeof(int);\n                return copyout ((caddr_t) &addr, (caddr_t) oldp, sizeof(int));\n            }\n        }\n        return EOPNOTSUPP;\n\n    case CPU_TIMO_CMD:\n        return sysctl_int(oldp, oldlenp, newp, newlen, &sd_timo_cmd);\n    case CPU_TIMO_SEND_OP:\n        return sysctl_int(oldp, oldlenp, newp, newlen, &sd_timo_send_op);\n    case CPU_TIMO_SEND_CSD:\n        return sysctl_int(oldp, oldlenp, newp, newlen, &sd_timo_send_csd);\n    case CPU_TIMO_READ:\n        return sysctl_int(oldp, oldlenp, newp, newlen, &sd_timo_read);\n    case CPU_TIMO_WAIT_CMD:\n        return sysctl_int(oldp, oldlenp, newp, newlen, &sd_timo_wait_cmd);\n    case CPU_TIMO_WAIT_WDATA:\n        return sysctl_int(oldp, oldlenp, newp, newlen, &sd_timo_wait_wdata);\n    case CPU_TIMO_WAIT_WDONE:\n        return sysctl_int(oldp, oldlenp, newp, newlen, &sd_timo_wait_wdone);\n    case CPU_TIMO_WAIT_WSTOP:\n        return sysctl_int(oldp, oldlenp, newp, newlen, &sd_timo_wait_wstop);\n    case CPU_TIMO_WAIT_WIDLE:\n        return sysctl_int(oldp, oldlenp, newp, newlen, &sd_timo_wait_widle);\n\n    case CPU_FREQ_KHZ:\n        if (namelen != 1)\n            return ENOTDIR;\n        khz = CPU_KHZ;\n        return sysctl_rdstruct (oldp, oldlenp, newp, &khz, sizeof khz);\n    case CPU_BUS_KHZ:\n        if (namelen != 1)\n            return ENOTDIR;\n        khz = BUS_KHZ;\n        return sysctl_rdstruct (oldp, oldlenp, newp, &khz, sizeof khz);\n\n    default:\n        return EOPNOTSUPP;\n    }\n    /* NOTREACHED */\n}\n"
  },
  {
    "path": "sys/arch/stm32/conf/Makefile.inc",
    "content": "#BOARD?=\t\tF405WEACTCORE\n#BOARD?=\t\tF411RENUCLEO\nBOARD?=\t\tF412GDISCO\n#BOARD?=\t\tF412WEACTCORE\n#BOARD?=\t\tF413HDISCO\n#BOARD?=\t\tF446RENUCLEO\n#BOARD?=\t\tF446WEACTCORE\n#BOARD?=\t\tF469IDISCO\n#BOARD?=\t\tF4DISCOVERY\n#BOARD?=\t\tF4VEDEVEBOX\nKERNDIR=\t${TOPSRC}/sys/arch/stm32/compile/${BOARD}\nKERN=\t\tunix\n\nCONFSCRIPT!=if [ x\"${BOARD}\" = x\"F405WEACTCORE\" ] ; then \\\n\t\techo \"board/st_nucleo_f4.cfg\" ; \\\n\telif [ x\"${BOARD}\" = x\"F411RENUCLEO\" ] ; then \\\n\t\techo \"board/st_nucleo_f4.cfg\" ; \\\n\telif [ x\"${BOARD}\" = x\"F412GDISCO\" ] ; then \\\n\t\techo \"board/stm32f412g-disco.cfg\" ; \\\n\telif [ x\"${BOARD}\" = x\"F412WEACTCORE\" ] ; then \\\n\t\techo \"board/st_nucleo_f4.cfg\" ; \\\n\telif [ x\"${BOARD}\" = x\"F413HDISCO\" ] ; then \\\n\t\techo \"board/stm32f413h-disco.cfg\" ; \\\n\telif [ x\"${BOARD}\" = x\"F446RENUCLEO\" ] ; then \\\n\t\techo \"board/st_nucleo_f4.cfg\" ; \\\n\telif [ x\"${BOARD}\" = x\"F446WEACTCORE\" ] ; then \\\n\t\techo \"board/st_nucleo_f4.cfg\" ; \\\n\telif [ x\"${BOARD}\" = x\"F469IDISCO\" ] ; then \\\n\t\techo \"board/stm32f469i-disco.cfg\" ; \\\n\telif [ x\"${BOARD}\" = x\"F4DISCOVERY\" ] ; then \\\n\t\techo \"board/stm32f4discovery.cfg\" ; \\\n\telif [ x\"${BOARD}\" = x\"F4VEDEVEBOX\" ] ; then \\\n\t\techo \"board/stm32f4discovery.cfg\" ; \\\n\telse \\\n\t\techo \"does/not/exist\" ; \\\n\tfi\n\nhelp:\n\t@echo \"Targets are:\" 1>&2\n\t@echo \"    ocd, gdb-ocd\" 1>&2\n\t@echo \"\" 1>&2\n\t@echo \"=== Debugging elf file in Circuit Board ===\" 1>&2\n\t@echo \"Run 'make ocd' in one terminal\" 1>&2\n\t@echo \"Run 'make gdb-ocd' in another terminal\" 1>&2\n\t@echo \"Enter 'c' in gdb to run the elf file\" 1>&2\n\t@echo \"Enter 'mon reset halt' in gdb to reset the cpu\" 1>&2\n\t@echo \"Enter 'load' in gdb to upload the elf file\" 1>&2\n\nocd:\n\tsudo openocd -f \"${CONFSCRIPT}\"\n\ngdb-ocd:\n\tarm-none-eabi-gdb -q \\\n\t\t-ex 'cd ${KERNDIR}' \\\n\t\t-ex 'target extended-remote :3333' \\\n\t\t-ex 'mon reset halt' \\\n\t\t-ex 'load' \\\n\t\t${KERNDIR}/${KERN}\n\n.PHONY: help ocd gdb-ocd\n"
  },
  {
    "path": "sys/arch/stm32/conf/Makefile.stm32",
    "content": "#\n# Makefile for DiscoBSD/stm32\n#\n# DEBUG is set to -g by config if debugging is requested (config -g).\n#\n\n# sources are located via $S relative to the compilation directory\nS=\t\t../../../..\n\n_mach?=\t\tstm32\n_arch?=\t\tarm\n_machdir?=\t$S/arch/${_mach}\n_archdir?=\t$S/arch/${_arch}\n_confdir?=\t${_machdir}/conf\n\ninclude\t\t${_confdir}/compiler.mk\n\nINCLUDES=\t-nostdinc -I. -I$S -I$S/arch -I${_archdir}/include\nDEPFLAGS=\t-MT $@ -MP -MD -MF .deps/$*.dep\nDEFS=\t\t${INCLUDES} ${PARAM} -DKERNEL ${DEPFLAGS}\nCWARNFLAGS=\t-Wall\n\nCMACHCPU=\t-mcpu=cortex-m4\nCMACHFLAGS=\t-ffreestanding -fno-builtin -fcommon\nCMACHFLAGS+=\t-mfloat-abi=soft\nCMACHFLAGS+=\t-mthumb -mabi=aapcs -mlittle-endian\nCMACHFLAGS+=\t${CMACHCPU}\n\nCOPTS?=\t\t-O\nCFLAGS=\t\t${DEBUG} ${CWARNFLAGS} ${CMACHFLAGS} ${COPTS}\nAFLAGS=\t\t-x assembler-with-cpp ${CWARNFLAGS} ${CMACHFLAGS}\nLDFLAGS=\t-T ${_confdir}/${LDSCRIPT} -T ${_confdir}/kern.ldscript\nLDFLAGS+=\t-nostdlib -Map=$@.map -z noexecstack\nLDADD=\n\n# compile rules: rules are named COMPILE_${SUFFIX}\n# SUFFIX is the file suffix, capitalized (e.g. C for a .c file).\n\nCOMPILE_C=\t${CC} ${CFLAGS} ${DEFS} -c $<\nCOMPILE_S=\t${AS} ${AFLAGS} ${DEFS} -c $<\n\n%OBJS\n\n%CFILES\n\n# load lines for config \"xxx\" will be emitted as:\n# xxx: ${SYSTEM_DEP} swapxxx.o\n#\t${SYSTEM_LD_HEAD}\n#\t${SYSTEM_LD} swapxxx.o\n#\t${SYSTEM_LD_TAIL}\nSYSTEM_OBJ=\tlocore0.o locore.o ${OBJS} ioconf.o\nSYSTEM_DEP=\tMakefile ioconf.c machine sys .deps ${SYSTEM_OBJ}\nSYSTEM_LD_HEAD=\tsh $S/conf/newvers.sh > vers.c; ${CC} ${CFLAGS} -c vers.c; rm -f $@\nSYSTEM_LD=\t-@echo ${LD} ${LDFLAGS} '$${SYSTEM_OBJ}' vers.o -o $@ ${LDADD}; \\\n\t\t${LD} ${LDFLAGS} ${SYSTEM_OBJ} vers.o -o $@ ${LDADD}\nSYSTEM_LD_TAIL=\t${SIZE} $@; cp $@ $@.elf; \\\n\t\t${OBJCOPY} -O ihex $@ $@.hex; \\\n\t\t${OBJCOPY} -O binary $@ $@.bin; \\\n\t\t${OBJDUMP} -d -S $@ > $@.dis\n\n%LOAD\n\nclean:\n\trm -rf .deps unix *.elf *.o *.map *.dis *.bin *.hex machine sys\n\nclean-all: clean\n\trm -f *.h ioconf.c swap*.c vers.c\n\nreconfig ioconf.c: Config $S/../tools/bin/config\n\t$S/../tools/bin/config Config\n\t${MAKE} clean\n\nmachine:\n\tln -s ${_machdir}/include $@\n\nsys:\n\tln -s $S/sys $@\n\n.deps:\n\tmkdir .deps\n\nlocore.o: ${_machdir}/${_mach}/locore.S\n\t${COMPILE_S}\n\nlocore0.o: ${_machdir}/${_mach}/locore0.S\n\t${COMPILE_S}\n\nioconf.o: ioconf.c\n\t${COMPILE_C}\n\n%RULES\n\n-include .deps/*.dep\n"
  },
  {
    "path": "sys/arch/stm32/conf/STM32F407XE.ld",
    "content": "/*\n * Kernel memory linker script for STM32F407XE.\n */\n\nMEMORY {\n    FLASH  (rx)   : ORIGIN = 0x08000000, LENGTH = 512K  /* 0x0800 0000 - 0x0807 FFFF */\n\n    RAM    (rw!x) : ORIGIN = 0x10000000, LENGTH = 58K   /* 0x1000 0000 - 0x1000 E7FF */\n    U0AREA (rw!x) : ORIGIN = 0x1000E800, LENGTH = 3K    /* 0x1000 E800 - 0x1000 F3FF */\n    UAREA  (rw!x) : ORIGIN = 0x1000F400, LENGTH = 3k    /* 0x1000 F400 - 0x1000 FFFF */\n\n    USERRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K   /* 0x2000 0000 - 0x2001 7FFF */\n}\n"
  },
  {
    "path": "sys/arch/stm32/conf/STM32F407XG.ld",
    "content": "/*\n * Kernel memory linker script for STM32F407XG.\n */\n\nMEMORY {\n    FLASH  (rx)   : ORIGIN = 0x08000000, LENGTH = 1024K /* 0x0800 0000 - 0x080F FFFF */\n\n    RAM    (rw!x) : ORIGIN = 0x10000000, LENGTH = 58K   /* 0x1000 0000 - 0x1000 E7FF */\n    U0AREA (rw!x) : ORIGIN = 0x1000E800, LENGTH = 3K    /* 0x1000 E800 - 0x1000 F3FF */\n    UAREA  (rw!x) : ORIGIN = 0x1000F400, LENGTH = 3k    /* 0x1000 F400 - 0x1000 FFFF */\n\n    USERRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K   /* 0x2000 0000 - 0x2001 7FFF */\n}\n"
  },
  {
    "path": "sys/arch/stm32/conf/STM32F411XE.ld",
    "content": "/*\n * Kernel memory linker script for STM32F411XE.\n */\n\nMEMORY {\n    FLASH  (rx)   : ORIGIN = 0x08000000, LENGTH = 512K  /* 0x0800 0000 - 0x0807 FFFF */\n\n    RAM    (rw!x) : ORIGIN = 0x20018000, LENGTH = 26K   /* 0x2001 8000 - 0x2001 E7FF */\n    U0AREA (rw!x) : ORIGIN = 0x2001E800, LENGTH = 3K    /* 0x2001 E800 - 0x2001 F3FF */\n    UAREA  (rw!x) : ORIGIN = 0x2001F400, LENGTH = 3k    /* 0x2001 F400 - 0x2001 FFFF */\n\n    USERRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K - 0x80   /* 0x2000 0000 - 0x2001 7F7F */\n/*  USERRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K *//* 0x2000 0000 - 0x2001 7FFF */\n}\n"
  },
  {
    "path": "sys/arch/stm32/conf/STM32F412XE.ld",
    "content": "/*\n * Kernel memory linker script for STM32F412XE.\n */\n\nMEMORY {\n    FLASH  (rx)   : ORIGIN = 0x08000000, LENGTH = 512K  /* 0x0800 0000 - 0x0807 FFFF */\n\n    RAM    (rw!x) : ORIGIN = 0x20038000, LENGTH = 26K   /* 0x2003 8000 - 0x2003 E7FF */\n    U0AREA (rw!x) : ORIGIN = 0x2003E800, LENGTH = 3K    /* 0x2003 E800 - 0x2003 F3FF */\n    UAREA  (rw!x) : ORIGIN = 0x2003F400, LENGTH = 3k    /* 0x2003 F400 - 0x2003 FFFF */\n\n    USERRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K   /* 0x2000 0000 - 0x2001 7FFF */\n}\n"
  },
  {
    "path": "sys/arch/stm32/conf/STM32F412XG.ld",
    "content": "/*\n * Kernel memory linker script for STM32F412XG.\n */\n\nMEMORY {\n    FLASH  (rx)   : ORIGIN = 0x08000000, LENGTH = 1024K /* 0x0800 0000 - 0x080F FFFF */\n\n    RAM    (rw!x) : ORIGIN = 0x20038000, LENGTH = 26K   /* 0x2003 8000 - 0x2003 E7FF */\n    U0AREA (rw!x) : ORIGIN = 0x2003E800, LENGTH = 3K    /* 0x2003 E800 - 0x2003 F3FF */\n    UAREA  (rw!x) : ORIGIN = 0x2003F400, LENGTH = 3k    /* 0x2003 F400 - 0x2003 FFFF */\n\n    USERRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K   /* 0x2000 0000 - 0x2001 7FFF */\n}\n"
  },
  {
    "path": "sys/arch/stm32/conf/STM32F413XH.ld",
    "content": "/*\n * Kernel memory linker script for STM32F413XH.\n */\n\nMEMORY {\n    FLASH  (rx)   : ORIGIN = 0x08000000, LENGTH = 1536K /* 0x0800 0000 - 0x080F FFFF */\n\n    RAM    (rw!x) : ORIGIN = 0x10000000, LENGTH = 58K   /* 0x1000 0000 - 0x1000 E7FF */\n    U0AREA (rw!x) : ORIGIN = 0x1000E800, LENGTH = 3K    /* 0x1000 E800 - 0x1000 F3FF */\n    UAREA  (rw!x) : ORIGIN = 0x1000F400, LENGTH = 3k    /* 0x1000 F400 - 0x1000 FFFF */\n\n    USERRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K   /* 0x2000 0000 - 0x2001 7FFF */\n}\n"
  },
  {
    "path": "sys/arch/stm32/conf/STM32F446XE.ld",
    "content": "/*\n * Kernel memory linker script for STM32F446XE.\n */\n\nMEMORY {\n    FLASH  (rx)   : ORIGIN = 0x08000000, LENGTH = 512K  /* 0x0800 0000 - 0x0807 FFFF */\n\n    RAM    (rw!x) : ORIGIN = 0x20018000, LENGTH = 26K   /* 0x2001 8000 - 0x2001 E7FF */\n    U0AREA (rw!x) : ORIGIN = 0x2001E800, LENGTH = 3K    /* 0x2001 E800 - 0x2001 F3FF */\n    UAREA  (rw!x) : ORIGIN = 0x2001F400, LENGTH = 3k    /* 0x2001 F400 - 0x2001 FFFF */\n\n    USERRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K - 0x80   /* 0x2000 0000 - 0x2001 7F7F */\n/*  USERRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K *//* 0x2000 0000 - 0x2001 7FFF */\n}\n"
  },
  {
    "path": "sys/arch/stm32/conf/STM32F469XI.ld",
    "content": "/*\n * Kernel memory linker script for STM32F469XI.\n */\n\nMEMORY {\n    FLASH  (rx)   : ORIGIN = 0x08000000, LENGTH = 1024K /* 0x0800 0000 - 0x080F FFFF */\n\n    RAM    (rw!x) : ORIGIN = 0x10000000, LENGTH = 58K   /* 0x1000 0000 - 0x1000 E7FF */\n    U0AREA (rw!x) : ORIGIN = 0x1000E800, LENGTH = 3K    /* 0x1000 E800 - 0x1000 F3FF */\n    UAREA  (rw!x) : ORIGIN = 0x1000F400, LENGTH = 3k    /* 0x1000 F400 - 0x1000 FFFF */\n\n    USERRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 112K  /* 0x2000 0000 - 0x2001 BFFF */\n}\n"
  },
  {
    "path": "sys/arch/stm32/conf/compiler.mk",
    "content": "# GCC arm-none-eabi toolchain on OpenBSD, FreeBSD, and Linux\n# ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\n_HOST_OSNAME!=\tuname -s\n\nARM_GCC_PREFIX!=if [ x\"${_HOST_OSNAME}\" = x\"OpenBSD\" ] ; then \\\n\t\t\techo \"/usr/local/bin/arm-none-eabi\" ; \\\n\t\telif [ x\"${_HOST_OSNAME}\" = x\"FreeBSD\" ] ; then \\\n\t\t\techo \"/usr/local/gcc-arm-embedded/bin/arm-none-eabi\" ; \\\n\t\telif [ x\"${_HOST_OSNAME}\" = x\"Linux\" ] ; then \\\n\t\t\techo \"/usr/bin/arm-none-eabi\" ; \\\n\t\telse \\\n\t\t\techo \"/does/not/exist\" ; \\\n\t\tfi\n\n_AS=\t\t-gcc\n_CC=\t\t-gcc\n_CPP=\t\t-cpp\n_LD=\t\t-ld\n_SIZE=\t\t-size\n_OBJCOPY=\t-objcopy\n_OBJDUMP=\t-objdump\n\nAS=\t\t${ARM_GCC_PREFIX}${_AS}\nCC=\t\t${ARM_GCC_PREFIX}${_CC}\nCPP=\t\t${ARM_GCC_PREFIX}${_CPP}\nLD=\t\t${ARM_GCC_PREFIX}${_LD}\nSIZE=\t\t${ARM_GCC_PREFIX}${_SIZE}\nOBJCOPY=\t${ARM_GCC_PREFIX}${_OBJCOPY}\nOBJDUMP=\t${ARM_GCC_PREFIX}${_OBJDUMP}\n"
  },
  {
    "path": "sys/arch/stm32/conf/devices.stm32",
    "content": "#\n# List of block devices and majors\n#\nsd      0\n"
  },
  {
    "path": "sys/arch/stm32/conf/files.stm32",
    "content": "#\n# Kernel sources, architecture-agnostic.\n#\nkern/exec_aout.c\t\t\tstandard\nkern/exec_conf.c\t\t\tstandard\nkern/exec_elf.c\t\t\t\tstandard\nkern/exec_script.c\t\t\tstandard\nkern/exec_subr.c\t\t\tstandard\nkern/init_main.c\t\t\tstandard\nkern/init_sysent.c\t\t\tstandard\nkern/kern_clock.c\t\t\tstandard\nkern/kern_descrip.c\t\t\tstandard\nkern/kern_exec.c\t\t\tstandard\nkern/kern_exit.c\t\t\tstandard\nkern/kern_fork.c\t\t\tstandard\nkern/kern_mman.c\t\t\tstandard\nkern/kern_proc.c\t\t\tstandard\nkern/kern_prot.c\t\t\tstandard\nkern/kern_prot2.c\t\t\tstandard\nkern/kern_resource.c\t\t\tstandard\nkern/kern_sig.c\t\t\t\tstandard\nkern/kern_sig2.c\t\t\tstandard\nkern/kern_subr.c\t\t\tstandard\nkern/kern_synch.c\t\t\tstandard\nkern/kern_sysctl.c\t\t\tstandard\nkern/kern_time.c\t\t\tstandard\nkern/subr_log.c\t\t\t\toptional log\nkern/subr_prf.c\t\t\t\tstandard\nkern/subr_rmap.c\t\t\tstandard\nkern/sys_generic.c\t\t\tstandard\nkern/sys_inode.c\t\t\tstandard\nkern/sys_pipe.c\t\t\t\tstandard\nkern/sys_process.c\t\t\tstandard\nkern/syscalls.c\t\t\t\tstandard\nkern/tty.c\t\t\t\tstandard\nkern/tty_pty.c\t\t\t\toptional pty\nkern/tty_subr.c\t\t\t\tstandard\nkern/tty_tty.c\t\t\t\tstandard\nkern/ufs_alloc.c\t\t\tstandard\nkern/ufs_bio.c\t\t\t\tstandard\nkern/ufs_bmap.c\t\t\t\tstandard\nkern/ufs_dsort.c\t\t\tstandard\nkern/ufs_fio.c\t\t\t\tstandard\nkern/ufs_inode.c\t\t\tstandard\nkern/ufs_mount.c\t\t\tstandard\nkern/ufs_namei.c\t\t\tstandard\nkern/ufs_subr.c\t\t\t\tstandard\nkern/ufs_syscalls.c\t\t\tstandard\nkern/ufs_syscalls2.c\t\t\tstandard\nkern/vfs_vnops.c\t\t\tstandard\nkern/vm_sched.c\t\t\t\tstandard\nkern/vm_swap.c\t\t\t\tstandard\nkern/vm_swp.c\t\t\t\tstandard\n\n#\n# Driver sources, architecture-agnostic.\n#\ndev/cons.c\t\t\t\tstandard\ndev/mem.c\t\t\t\tstandard\ndev/swap.c\t\t\t\tstandard\n\n#\n# STM32 platform.\n#\narch/stm32/stm32/clock.c\t\tstandard\narch/stm32/stm32/conf.c\t\t\tstandard\narch/stm32/stm32/fault.c\t\tstandard\narch/stm32/stm32/machdep.c\t\tstandard\narch/stm32/stm32/mpu.c\t\t\tstandard\narch/stm32/stm32/sig_machdep.c\t\tstandard\narch/stm32/stm32/syscall.c\t\tstandard\narch/stm32/stm32/sysctl.c\t\tstandard\narch/stm32/stm32/systick.c\t\tstandard\n\n#\n# STM32 hardware abstraction layer.\n#\narch/stm32/hal/stm32f4xx_hal.c\t\tstandard\narch/stm32/hal/stm32f4xx_hal_sd.c\toptional sdio\narch/stm32/hal/stm32f4xx_hal_spi.c\toptional spi\n#arch/stm32/hal/stm32f4xx_ll_rcc.c\tstandard\narch/stm32/hal/stm32f4xx_ll_sdmmc.c\toptional sdio\n#arch/stm32/hal/stm32f4xx_ll_usart.c\toptional uart\narch/stm32/hal/stm32f4xx_ll_utils.c\tstandard\narch/stm32/hal/system_stm32f4xx.c\tstandard\n\n#\n# STM32 drivers.\n#\narch/stm32/dev/sd.c\t\t\toptional sd\narch/stm32/dev/sdio.c\t\t\toptional sdio\narch/stm32/dev/sdio_card.c\t\toptional sd\narch/stm32/dev/spi.c\t\t\toptional spi\narch/stm32/dev/uart.c\t\t\toptional uart\n\n#\n# STM32 BSP LED and Button drivers for boards.\n#\narch/stm32/dev/stm32_bsp.c\t\toptional bsp\n\n#\n# STM32 SDIO SD driver for boards.\n#\narch/stm32/dev/stm32_sdio_sd.c\t\toptional sdio\n\n#\n# STM32 SPI SD driver for ADAFRUIT_SD_ID254 board.\n#\narch/stm32/dev/stm32_adafruit_sd.c\toptional spi\narch/stm32/dev/stm32f4xx_nucleo_sd.c\toptional spi\n"
  },
  {
    "path": "sys/arch/stm32/conf/kern.ldscript",
    "content": "/*\n * Kernel common linker script for STM32.\n */\n\n/*\n * On STM32, a minimum of 128 kbytes of flash and 128 kbytes of RAM is needed.\n * Reserve for the kernel at least 128 kbytes of flash and 32 kbytes of RAM.\n * Reserve for userland at least 96 kbytes of RAM.\n */\n\n__kernel_flash_start\t= ORIGIN(FLASH);\n__kernel_flash_end\t= ORIGIN(FLASH) + LENGTH(FLASH);\n__kernel_data_start\t= ORIGIN(RAM);\n__kernel_data_end\t= ORIGIN(RAM) + LENGTH(RAM);\n__user_data_start\t= ORIGIN(USERRAM);\n__user_data_end\t\t= ORIGIN(USERRAM) + LENGTH(USERRAM);\n\nu0\t\t\t= ORIGIN(U0AREA);\nu\t\t\t= ORIGIN(UAREA);\nu_end\t\t\t= ORIGIN(UAREA) + LENGTH(UAREA);\n_estack\t\t\t= ORIGIN(UAREA) + LENGTH(UAREA);\n\nENTRY(Reset_Handler)\n\nSECTIONS {\n\t.text : {\n\t\tKEEP(*(.isr_vector))\n\t\t. = ALIGN(8);\n\t\t*(.text*)\n\t\t. = ALIGN(8);\n\t\t*(.rodata*)\n\t} > FLASH\n\n\t.ARM.extab : {\n\t\t*(.ARM.extab* .gnu.linkonce.armextab.*)\n\t} > FLASH\n\n\t.ARM.exidx : {\n\t\t__exidx_start = .;\n\t\t*(.ARM.exidx* .gnu.linkonce.armexidx.*)\n\t\t__exidx_end = .;\n\t} > FLASH\n\t__etext = .;\n\n\t_sidata = .;\n\t.data : {\n\t\t__data_start__ = .;\n\t\t_sdata = .;\n\t\t*(.data*)\n\t\t. = ALIGN(8);\n\t\t__data_end__ = .;\n\t\t_edata = .;\n\t} > RAM AT > FLASH\n\n\t.bss : {\n\t\t. = ALIGN(8);\n\t\t__bss_start__ = .;\n\t\t_sbss = .;\n\t\t*(.bss*)\n\t\t*(COMMON)\n\t\t. = ALIGN(8);\n\t\t__bss_end__ = .;\n\t\t_ebss = .;\n\t} > RAM\n}\n"
  },
  {
    "path": "sys/arch/stm32/dev/sd.c",
    "content": "/*\n * SD or SDHC card connected to SPI or SDIO port.\n *\n * Up to two cards can be connected to the same SPI port.\n * PC-compatible partition table is supported.\n * The following device numbers are used:\n *\n * Major Minor Device  Partition\n * ----------------------------------------------\n *   0     0     sd0   Main SD card, whole volume\n *   0     1     sd0a  1-st partition, usually root FS\n *   0     2     sd0b  2-nd partition, usually swap\n *   0     3     sd0c  3-rd partition\n *   0     4     sd0d  4-th partition\n *   0     8     sd1   Second SD card, whole volume\n *   0     9     sd1a  1-st partition\n *   0     10    sd1b  2-nd partition\n *   0     11    sd1c  3-rd partition\n *   0     12    sd1d  4-th partition\n *\n * Copyright (C) 2010-2015 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/buf.h>\n#include <sys/errno.h>\n#include <sys/dk.h>\n#include <sys/disk.h>\n#include <sys/config.h>\n\n#include <stm32/dev/sd.h>\n#include <stm32/dev/sdio_card.h>\n\n#define sdunit(dev)     ((minor(dev) & 8) >> 3)\n#define sdpart(dev)     ((minor(dev) & 7))\n#define RAWPART         0               /* 'x' partition */\n\n/*\n * Detect a card.\n */\nstatic int\nsd_setup(int unit)\n{\n    struct disk *du = &sddrives[unit];\n    u_short buf[256];\n\n    if (! card_init(unit)) {\n        printf(\"sd%d: no SD/MMC card detected\\n\", unit);\n        return 0;\n    }\n    /* Get the size of raw partition. */\n    bzero(du->part, sizeof(du->part));\n    du->part[RAWPART].dp_offset = 0;\n    du->part[RAWPART].dp_nsectors = card_size(unit);\n    if (du->part[RAWPART].dp_nsectors == 0) {\n        printf(\"sd%d: cannot get card size\\n\", unit);\n        return 0;\n    }\n\n    printf(\"sd%d: type %s, size %u kbytes\\n\", unit,\n        (du->card_type == TYPE_SDHC) ? \"SDHC\" :\n        (du->card_type == TYPE_SD_II) ? \"II\" : \"I\",\n        du->part[RAWPART].dp_nsectors / 2);\n\n    /* Read partition table. */\n    int s = splbio();\n    if (! card_read(unit, 0, (char*)buf, sizeof(buf))) {\n        splx(s);\n        printf(\"sd%d: cannot read partition table\\n\", unit);\n        return 0;\n    }\n    splx(s);\n    if (buf[255] == MBR_MAGIC) {\n        bcopy(&buf[223], &du->part[1], 64);\n        int i;\n        for (i=1; i<=NPARTITIONS; i++) {\n            if (du->part[i].dp_type != 0)\n                printf(\"sd%d%c: partition type %02x, sector %u, size %u kbytes\\n\",\n                    unit, i+'a'-1, du->part[i].dp_type,\n                    du->part[i].dp_offset,\n                    du->part[i].dp_nsectors / 2);\n        }\n    }\n    return 1;\n}\n\n/*\n * Disable the SD card.\n */\nstatic void\nsd_release(int unit)\n{\n    struct disk *du = &sddrives[unit];\n\n    card_release(unit);\n\n    /* Forget the partition table. */\n    du->part[RAWPART].dp_nsectors = 0;\n}\n\n/*\n * sd block device\n */\n\nint\nsdopen(dev_t dev, int flags, int mode)\n{\n    int unit = sdunit(dev);\n    int part = sdpart(dev);\n    struct disk *du = &sddrives[unit];\n    unsigned mask, i;\n\n    if (unit >= NSD || part > NPARTITIONS)\n        return ENXIO;\n\n    /*\n     * Setup the SD card interface.\n     */\n    if (du->part[RAWPART].dp_nsectors == 0) {\n        if (! sd_setup(unit)) {\n            return ENODEV;\n        }\n    }\n    mask = 1 << part;\n\n    /*\n     * Warn if a partion is opened\n     * that overlaps another partition which is open\n     * unless one is the \"raw\" partition (whole disk).\n     */\n    if (part != RAWPART && (du->openpart & mask) == 0) {\n        unsigned start = du->part[part].dp_offset;\n        unsigned end = start + du->part[part].dp_nsectors;\n\n        /* Check for overlapped partitions. */\n        for (i=0; i<=NPARTITIONS; i++) {\n            struct diskpart *pp = &du->part[i];\n\n            if (i == part || i == RAWPART)\n                continue;\n\n            if (pp->dp_offset + pp->dp_nsectors <= start ||\n                pp->dp_offset >= end)\n                continue;\n\n            if (du->openpart & (1 << i))\n                printf(\"sd%d%c: overlaps open partition (sd%d%c)\\n\",\n                    unit, part + 'a' - 1,\n                    unit, pp - du->part + 'a' - 1);\n        }\n    }\n    du->openpart |= mask;\n    return 0;\n}\n\nint\nsdclose(dev_t dev, int mode, int flag)\n{\n    int unit = sdunit(dev);\n    int part = sdpart(dev);\n    struct disk *du = &sddrives[unit];\n\n    if (unit >= NSD || part > NPARTITIONS)\n        return ENODEV;\n\n    du->openpart &= ~(1 << part);\n    if (du->openpart == 0) {\n        /* All partitions closed.\n         * Release the SD card. */\n        sd_release(unit);\n    }\n    return 0;\n}\n\n/*\n * Get disk size in kbytes.\n * Return nonzero if successful.\n */\ndaddr_t\nsdsize(dev_t dev)\n{\n    int unit = sdunit(dev);\n    int part = sdpart(dev);\n    struct disk *du = &sddrives[unit];\n\n    if (unit >= NSD || part > NPARTITIONS || du->openpart == 0)\n        return 0;\n\n    return du->part[part].dp_nsectors >> 1;\n}\n\nvoid\nsdstrategy(struct buf *bp)\n{\n    int unit = sdunit(bp->b_dev);\n    struct disk *du = &sddrives[unit];\n    struct diskpart *p = &du->part[sdpart(bp->b_dev)];\n    int part_size = p->dp_nsectors >> 1;\n    int offset = bp->b_blkno;\n    long nblk = btod(bp->b_bcount);\n    int s;\n\n    /*\n     * Determine the size of the transfer, and make sure it is\n     * within the boundaries of the partition.\n     */\n    offset += p->dp_offset >> 1;\n    if (offset == 0 &&\n        ! (bp->b_flags & B_READ) && ! du->label_writable)\n    {\n        /* Write to partition table not allowed. */\n        bp->b_error = EROFS;\nbad:    bp->b_flags |= B_ERROR;\n        biodone(bp);\n        return;\n    }\n    if (bp->b_blkno + nblk > part_size) {\n        /* if exactly at end of partition, return an EOF */\n        if (bp->b_blkno == part_size) {\n            bp->b_resid = bp->b_bcount;\n            biodone(bp);\n            return;\n        }\n        /* or truncate if part of it fits */\n        nblk = part_size - bp->b_blkno;\n        if (nblk <= 0) {\n            bp->b_error = EINVAL;\n            goto bad;\n        }\n        bp->b_bcount = nblk << DEV_BSHIFT;\n    }\n\n    if (bp->b_dev == swapdev) {\n        led_control(LED_SWAP, 1);\n    } else {\n        led_control(LED_DISK, 1);\n    }\n\n    s = splbio();\n#ifdef UCB_METER\n    if (du->dkindex >= 0) {\n        dk_busy |= 1 << du->dkindex;\n        dk_xfer[du->dkindex]++;\n        dk_bytes[du->dkindex] += bp->b_bcount;\n    }\n#endif\n\n    if (bp->b_flags & B_READ) {\n        card_read(unit, offset, bp->b_addr, bp->b_bcount);\n    } else {\n        card_write(unit, offset, bp->b_addr, bp->b_bcount);\n    }\n\n    biodone(bp);\n    if (bp->b_dev == swapdev) {\n        led_control(LED_SWAP, 0);\n    } else {\n        led_control(LED_DISK, 0);\n    }\n#ifdef UCB_METER\n    if (du->dkindex >= 0)\n        dk_busy &= ~(1 << du->dkindex);\n#endif\n    splx(s);\n}\n\nint\nsdioctl(dev_t dev, u_int cmd, caddr_t addr, int flag)\n{\n    int unit = sdunit(dev);\n    int part = sdpart(dev);\n    struct diskpart *dp;\n    int i, error = 0;\n\n    switch (cmd) {\n\n    case DIOCGETMEDIASIZE:\n        /* Get disk size in kbytes. */\n        dp = &sddrives[unit].part[part];\n        *(int*) addr = dp->dp_nsectors >> 1;\n        break;\n\n    case DIOCREINIT:\n        for (i=0; i<=NPARTITIONS; i++)\n            bflush(makedev(major(dev), i));\n        sd_setup(unit);\n        break;\n\n    case DIOCGETPART:\n        /* Get partition table entry. */\n        dp = &sddrives[unit].part[part];\n        *(struct diskpart*) addr = *dp;\n        break;\n\n    default:\n        error = EINVAL;\n        break;\n    }\n    return error;\n}\n\n/*\n * Test to see if device is present.\n * Return true if found and initialized ok.\n */\nstatic int\nsd_probe(config)\n    struct conf_device *config;\n{\n    int unit = config->dev_unit;\n    const char *ctlr_name = config->dev_cdriver->d_name;\n    int ctlr_num = config->dev_ctlr;\n\n    if (unit < 0 || unit >= NSD)\n        return 0;\n    printf(\"sd%u: port %s%d\\n\", unit, ctlr_name, ctlr_num);\n\n    if (! card_init(unit)) {\n        printf(\"sd%u: cannot open %s%u port\\n\", unit, ctlr_name, ctlr_num);\n        return 0;\n    }\n\n    /* Disable the SD card. */\n    sd_release(unit);\n\n#ifdef UCB_METER\n    dk_alloc(&sddrives[unit].dkindex, 1, (unit == 0) ? \"sd0\" : \"sd1\");\n#endif\n    return 1;\n}\n\nstruct driver sddriver = {\n    \"sd\", sd_probe,\n};\n"
  },
  {
    "path": "sys/arch/stm32/dev/sd.h",
    "content": "#ifndef _SD_H\n#define _SD_H\n\n#include <sys/disk.h>\n\n/*\n * Driver's data per disk drive.\n */\nstruct disk {\n    /*\n     * Partition table.\n     */\n#define NPARTITIONS     4\n    struct  diskpart part[NPARTITIONS+1];\n\n#define TYPE_UNKNOWN    0\n#define TYPE_SD_LEGACY  1\n#define TYPE_SD_II      2\n#define TYPE_SDHC       3\n    int     card_type;\n    int     label_writable;     /* is sector 0 writable? */\n    int     dkindex;            /* disk index for statistics */\n    u_int   openpart;           /* all partitions open on this drive */\n    u_char  ocr[4];             /* operation condition register */\n    u_char  csd[16];            /* card-specific data */\n    u_short group[6];           /* function group bitmasks */\n    int     ma;                 /* power consumption */\n};\n\nstruct disk sddrives[NSD];      /* Table of units */\n\n#ifdef KERNEL\nextern int      sdopen(dev_t dev, int flag, int mode);\nextern int      sdclose(dev_t dev, int flag, int mode);\nextern void     sdstrategy(struct buf *bp);\nextern daddr_t  sdsize(dev_t dev);\nextern int      sdioctl(dev_t dev, u_int cmd, caddr_t addr, int flag);\n#endif /* KERNEL */\n\n#endif /* _SD_H */\n"
  },
  {
    "path": "sys/arch/stm32/dev/sdio.c",
    "content": "/*\n * SDIO driver for STM32.\n */\n#include <sys/param.h>\n#include <sys/uio.h>\n#include <sys/config.h>\n\n#include <stm32/dev/sdio.h>\n\nint\nsdio_open(dev_t dev, int flag, int mode)\n{\n    return (0);\n}\n\nint\nsdio_close(dev_t dev, int flag, int mode)\n{\n    return (0);\n}\n\nint\nsdio_read(dev_t dev, struct uio *uio, int flag)\n{\n    return (0);\n}\n\nint\nsdio_write(dev_t dev, struct uio *uio, int flag)\n{\n    return (0);\n}\n\nint\nsdio_ioctl(dev_t dev, u_int cmd, caddr_t addr, int flag)\n{\n    return (0);\n}\n\nstatic int\nsdio_probe(struct conf_ctlr *config)\n{\n    return (1);\n}\n\nstruct driver sdiodriver = {\n    \"sdio\", sdio_probe,\n};\n"
  },
  {
    "path": "sys/arch/stm32/dev/sdio.h",
    "content": "#ifndef _MACHINE_SDIO_H_\n#define _MACHINE_SDIO_H_\n\n#ifdef KERNEL\nint sdio_open(dev_t dev, int flag, int mode);\nint sdio_close(dev_t dev, int flag, int mode);\nint sdio_read(dev_t dev, struct uio *uio, int flag);\nint sdio_write(dev_t dev, struct uio *uio, int flag);\nint sdio_ioctl(dev_t dev, u_int cmd, caddr_t addr, int flag);\n#endif /* KERNEL */\n\n#endif /* _MACHINE_SDIO_H_ */\n"
  },
  {
    "path": "sys/arch/stm32/dev/sdio_card.c",
    "content": "/*\n * Copyright (c) 2021 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include <sys/param.h>\n#include <sys/systm.h>\n\n#include <stm32/dev/sd.h>\n#include <stm32/dev/sdio_card.h>\n#include <stm32/dev/stm32_bsp_sd.h>\n\n#include <machine/debug.h>\n\n#define SECTSIZE        512\n\nextern struct disk sddrives[NSD];\n\n/*\n * Initialize a card.\n * Return nonzero if successful.\n */\nint\ncard_init(int unit)\n{\n    struct disk *du = &sddrives[unit];\n    BSP_SD_CardInfo ci;\n\n    if (BSP_SD_Init() != BSP_SD_OK) {\n        return 0;\n    }\n\n    BSP_SD_GetCardInfo(&ci);\n#if 0 // XXX SD CARD TYPE\n    du->card_type = ci.CardType;\n#endif // XXX SD CARD TYPE\n    du->card_type = TYPE_SDHC; // XXX SD CARD TYPE\n\n    return 1;\n}\n\n/*\n * Get disk size in 512-byte sectors.\n * Return nonzero if successful.\n */\nint\ncard_size(int unit)\n{\n    BSP_SD_CardInfo ci;\n\n    BSP_SD_GetCardInfo(&ci);\n\n    return ci.LogBlockNbr;\n}\n\n/*\n * Read a block of data.\n * Return nonzero if successful.\n */\nint\ncard_read(int unit, unsigned int offset, char *data, unsigned int bcount)\n{\n    int nblocks;\n    uint8_t SD_state = BSP_SD_OK;\n\n    if ((bcount % SECTSIZE) == 0) {\n        nblocks = bcount / SECTSIZE;\n    } else {\n        nblocks = (bcount / SECTSIZE) + 1;\n    }\n\n    DEBUG(\"card_read:  bcount: %d\\tnblocks: %d\\tbcount \\% %d: %d\\n\",\n      bcount, nblocks, SECTSIZE, bcount % SECTSIZE);\n\n    SD_state = BSP_SD_ReadBlocks((uint32_t *)data, offset << 1, nblocks, SD_DATATIMEOUT);\n\n    if (SD_state != BSP_SD_OK) {\n        printf(\"card_read:  read failed\\n\");\n        return 0;\n    }\n\n    return 1;\n}\n\n/*\n * Write a block of data.\n * Return nonzero if successful.\n */\nint\ncard_write(int unit, unsigned offset, char *data, unsigned bcount)\n{\n    int nblocks;\n    uint8_t SD_state = BSP_SD_OK;\n\n    if ((bcount % SECTSIZE) == 0) {\n        nblocks = bcount / SECTSIZE;\n    } else {\n        nblocks = (bcount / SECTSIZE) + 1;\n    }\n\n    DEBUG(\"card_write: bcount: %d\\tnblocks: %d\\tbcount \\% %d: %d\\n\",\n      bcount, nblocks, SECTSIZE, bcount % SECTSIZE);\n\n    SD_state = BSP_SD_WriteBlocks((uint32_t *)data, offset << 1, nblocks, SD_DATATIMEOUT);\n\n    /* Wait for write completion. */\n    int x = spl0();\n    while (BSP_SD_GetCardState() != BSP_SD_OK)\n        ;\n    splx(x);\n\n    if (SD_state != BSP_SD_OK) {\n        printf(\"card_write: write failed\\n\");\n        return 0;\n    }\n\n    return 1;\n}\n\n/*\n * Disable the SD card.\n */\nvoid\ncard_release(int unit)\n{\n    BSP_SD_DeInit();\n}\n"
  },
  {
    "path": "sys/arch/stm32/dev/sdio_card.h",
    "content": "#ifndef _MACHINE_SDIO_CARD_H_\n#define _MACHINE_SDIO_CARD_H_\n\n#ifdef KERNEL\nint     card_init(int unit);\nint     card_size(int unit);\nint     card_read(int unit, unsigned int offset, char *data, unsigned int bcount);\nint     card_write(int unit, unsigned offset, char *data, unsigned bcount);\nvoid    card_release(int unit);\n#endif /* KERNEL */\n\n#endif /* _MACHINE_SDIO_CARD_H_ */\n"
  },
  {
    "path": "sys/arch/stm32/dev/spi.c",
    "content": "/*\n * SPI driver for STM32.\n */\n#include <sys/param.h>\n#include <sys/uio.h>\n#include <sys/config.h>\n\n#include <stm32/dev/spi.h>\n\nint\nspi_open(dev_t dev, int flag, int mode)\n{\n\treturn (0);\n}\n\nint\nspi_close(dev_t dev, int flag, int mode)\n{\n\treturn (0);\n}\n\nint\nspi_read(dev_t dev, struct uio *uio, int flag)\n{\n\treturn (0);\n}\n\nint\nspi_write(dev_t dev, struct uio *uio, int flag)\n{\n\treturn (0);\n}\n\nint\nspi_ioctl(dev_t dev, u_int cmd, caddr_t addr, int flag)\n{\n\treturn (0);\n}\n\nstatic int\nspi_probe(struct conf_ctlr *config)\n{\n\treturn (1);\n}\n\nstruct driver spidriver = {\n\t\"spi\", spi_probe,\n};\n"
  },
  {
    "path": "sys/arch/stm32/dev/spi.h",
    "content": "#ifndef _MACHINE_SPI_H_\n#define _MACHINE_SPI_H_\n\n#ifdef KERNEL\nint\tspi_open(dev_t dev, int flag, int mode);\nint\tspi_close(dev_t dev, int flag, int mode);\nint\tspi_read(dev_t dev, struct uio *uio, int flag);\nint\tspi_write(dev_t dev, struct uio *uio, int flag);\nint\tspi_ioctl(dev_t dev, u_int cmd, caddr_t addr, int flag);\n#endif /* KERNEL */\n\n#endif /* _MACHINE_SPI_H_ */\n"
  },
  {
    "path": "sys/arch/stm32/dev/stm32_adafruit_sd.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32_adafruit_sd.c\n  * @author  MCD Application Team\n  * @version V3.0.3\n  * @date    30-April-2018\n  * @brief   This file provides a set of functions needed to manage the SD card\n  *          mounted on the Adafruit MicroSD Breakout Board+ (reference ID 254),\n  *          that is used with the STM32 Nucleo board through SPI interface.\n  *          It implements a high level communication layer for read and write\n  *          from/to this memory. The needed STM32XXxx hardware resources (SPI and\n  *          GPIO) are defined in stm32XXxx_nucleo_sd.h file, and the initialization is\n  *          performed in SD_IO_Init() function declared in stm32XXxx_nucleo_sd.c\n  *          file.\n  *          You can easily tailor this driver to any other development board,\n  *          by just adapting the defines for hardware resources and\n  *          SD_IO_Init() function.\n  *\n  *          +-------------------------------------------------------+\n  *          |                     Pin assignment                    |\n  *          +-------------------------+---------------+-------------+\n  *          |  STM32XXxx SPI Pins     |     SD        |    Pin      |\n  *          +-------------------------+---------------+-------------+\n  *          | SD_SPI_CS_PIN           |   ChipSelect  |    1        |\n  *          | SD_SPI_MOSI_PIN / MOSI  |   DataIn      |    2        |\n  *          |                         |   GND         |    3 (0 V)  |\n  *          |                         |   VDD         |    4 (3.3 V)|\n  *          | SD_SPI_SCK_PIN / SCLK   |   Clock       |    5        |\n  *          |                         |   GND         |    6 (0 V)  |\n  *          | SD_SPI_MISO_PIN / MISO  |   DataOut     |    7        |\n  *          +-------------------------+---------------+-------------+\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* File Info : -----------------------------------------------------------------\n                                   User NOTES\n1. How to use this driver:\n--------------------------\n   - This driver does not need a specific component driver for the micro SD device\n     to be included with.\n\n2. Driver description:\n---------------------\n  + Initialization steps:\n     o Initialize the micro SD card using the BSP_SD_Init() function.\n     o Checking the SD card presence is not managed.\n     o The function BSP_SD_GetCardInfo() is used to get the micro SD card information\n       which is stored in the structure \"BSP_SD_CardInfo\".\n\n  + Micro SD card operations\n     o The micro SD card can be accessed with read/write block(s) operations once\n       it is ready for access. The access can be performed in polling\n       mode by calling the functions BSP_SD_ReadBlocks()/BSP_SD_WriteBlocks().\n\n     o The SD erase block(s) is performed using the function BSP_SD_Erase() with\n       specifying the number of blocks to erase.\n     o The SD runtime status is returned when calling the function BSP_SD_GetCardState().\n\n------------------------------------------------------------------------------*/\n\n/* To be defined only if provided with the Adafruit MicroSD Breakout Board+ */\n/* https://www.adafruit.com/product/254 */\n#ifdef SPI_SD_ENABLED                   /* Kernel Config 'options' definition. */\n\n/* Includes ------------------------------------------------------------------*/\n#include <sys/param.h>\n#include <sys/systm.h>\n\n#include <stm32/dev/stm32_bsp_sd.h>\n\n/* Private typedef -----------------------------------------------------------*/\n\ntypedef struct {\n  uint8_t r1;\n  uint8_t r2;\n  uint8_t r3;\n  uint8_t r4;\n  uint8_t r5;\n} SD_CmdAnswer_typedef;\n\n/* Private define ------------------------------------------------------------*/\n\n#define SD_BLOCK_SIZE           0x200\n\n#define SD_DUMMY_BYTE            0xFF\n\n#define SD_MAX_FRAME_LENGTH        17    /* Length = 16 + 1 */\n#define SD_CMD_LENGTH               6\n\n#define SD_MAX_TRY                100    /* Number of try */\n\n#define SD_CSD_STRUCT_V1          0x2    /* CSD struct version V1 */\n#define SD_CSD_STRUCT_V2          0x1    /* CSD struct version V2 */\n\n\n/**\n  * @brief  SD answer format\n  */\ntypedef enum {\n SD_ANSWER_R1_EXPECTED,\n SD_ANSWER_R1B_EXPECTED,\n SD_ANSWER_R2_EXPECTED,\n SD_ANSWER_R3_EXPECTED,\n SD_ANSWER_R4R5_EXPECTED,\n SD_ANSWER_R7_EXPECTED,\n}SD_Answer_type;\n\n/**\n  * @brief  Start Data tokens:\n  *         Tokens (necessary because at nop/idle (and CS active) only 0xff is\n  *         on the data/command line)\n  */\n#define SD_TOKEN_START_DATA_SINGLE_BLOCK_READ    0xFE  /* Data token start byte, Start Single Block Read */\n#define SD_TOKEN_START_DATA_MULTIPLE_BLOCK_READ  0xFE  /* Data token start byte, Start Multiple Block Read */\n#define SD_TOKEN_START_DATA_SINGLE_BLOCK_WRITE   0xFE  /* Data token start byte, Start Single Block Write */\n#define SD_TOKEN_START_DATA_MULTIPLE_BLOCK_WRITE 0xFD  /* Data token start byte, Start Multiple Block Write */\n#define SD_TOKEN_STOP_DATA_MULTIPLE_BLOCK_WRITE  0xFD  /* Data token stop byte, Stop Multiple Block Write */\n\n/**\n  * @brief  Commands: CMDxx = CMD-number | 0x40\n  */\n#define SD_CMD_GO_IDLE_STATE          0   /* CMD0 = 0x40  */\n#define SD_CMD_SEND_OP_COND           1   /* CMD1 = 0x41  */\n#define SD_CMD_SEND_IF_COND           8   /* CMD8 = 0x48  */\n#define SD_CMD_SEND_CSD               9   /* CMD9 = 0x49  */\n#define SD_CMD_SEND_CID               10  /* CMD10 = 0x4A */\n#define SD_CMD_STOP_TRANSMISSION      12  /* CMD12 = 0x4C */\n#define SD_CMD_SEND_STATUS            13  /* CMD13 = 0x4D */\n#define SD_CMD_SET_BLOCKLEN           16  /* CMD16 = 0x50 */\n#define SD_CMD_READ_SINGLE_BLOCK      17  /* CMD17 = 0x51 */\n#define SD_CMD_READ_MULT_BLOCK        18  /* CMD18 = 0x52 */\n#define SD_CMD_SET_BLOCK_COUNT        23  /* CMD23 = 0x57 */\n#define SD_CMD_WRITE_SINGLE_BLOCK     24  /* CMD24 = 0x58 */\n#define SD_CMD_WRITE_MULT_BLOCK       25  /* CMD25 = 0x59 */\n#define SD_CMD_PROG_CSD               27  /* CMD27 = 0x5B */\n#define SD_CMD_SET_WRITE_PROT         28  /* CMD28 = 0x5C */\n#define SD_CMD_CLR_WRITE_PROT         29  /* CMD29 = 0x5D */\n#define SD_CMD_SEND_WRITE_PROT        30  /* CMD30 = 0x5E */\n#define SD_CMD_SD_ERASE_GRP_START     32  /* CMD32 = 0x60 */\n#define SD_CMD_SD_ERASE_GRP_END       33  /* CMD33 = 0x61 */\n#define SD_CMD_UNTAG_SECTOR           34  /* CMD34 = 0x62 */\n#define SD_CMD_ERASE_GRP_START        35  /* CMD35 = 0x63 */\n#define SD_CMD_ERASE_GRP_END          36  /* CMD36 = 0x64 */\n#define SD_CMD_UNTAG_ERASE_GROUP      37  /* CMD37 = 0x65 */\n#define SD_CMD_ERASE                  38  /* CMD38 = 0x66 */\n#define SD_CMD_SD_APP_OP_COND         41  /* CMD41 = 0x69 */\n#define SD_CMD_APP_CMD                55  /* CMD55 = 0x77 */\n#define SD_CMD_READ_OCR               58  /* CMD55 = 0x79 */\n\n/**\n  * @brief  SD responses and error flags\n  */\ntypedef enum\n{\n/* R1 answer value */\n  SD_R1_NO_ERROR            = (0x00),\n  SD_R1_IN_IDLE_STATE       = (0x01),\n  SD_R1_ERASE_RESET         = (0x02),\n  SD_R1_ILLEGAL_COMMAND     = (0x04),\n  SD_R1_COM_CRC_ERROR       = (0x08),\n  SD_R1_ERASE_SEQUENCE_ERROR= (0x10),\n  SD_R1_ADDRESS_ERROR       = (0x20),\n  SD_R1_PARAMETER_ERROR     = (0x40),\n\n/* R2 answer value */\n  SD_R2_NO_ERROR            = 0x00,\n  SD_R2_CARD_LOCKED         = 0x01,\n  SD_R2_LOCKUNLOCK_ERROR    = 0x02,\n  SD_R2_ERROR               = 0x04,\n  SD_R2_CC_ERROR            = 0x08,\n  SD_R2_CARD_ECC_FAILED     = 0x10,\n  SD_R2_WP_VIOLATION        = 0x20,\n  SD_R2_ERASE_PARAM         = 0x40,\n  SD_R2_OUTOFRANGE          = 0x80,\n\n/**\n  * @brief  Data response error\n  */\n  SD_DATA_OK                = (0x05),\n  SD_DATA_CRC_ERROR         = (0x0B),\n  SD_DATA_WRITE_ERROR       = (0x0D),\n  SD_DATA_OTHER_ERROR       = (0xFF)\n} SD_Error;\n\n/* Private macro -------------------------------------------------------------*/\n\n/* Private variables ---------------------------------------------------------*/\n\n/* flag_SDHC :\n      0 : Standard capacity\n      1 : High capacity\n*/\nuint16_t flag_SDHC = 0;\n\n/* Private function prototypes -----------------------------------------------*/\n\nstatic uint8_t SD_GetCSDRegister(SD_CSD* Csd);\nstatic uint8_t SD_GetCIDRegister(SD_CID* Cid);\nstatic SD_CmdAnswer_typedef SD_SendCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc, uint8_t Answer);\nstatic uint8_t SD_GetDataResponse(void);\nstatic uint8_t SD_ReadData(void);\nstatic uint8_t SD_WaitData(uint8_t data);\nstatic uint8_t SD_GoIdleState(void);\n\n/* Public functions ----------------------------------------------------------*/\n\n/**\n  * @brief  Initializes the SD/SD communication.\n  * @param  None\n  * @retval The SD Response:\n  *         - BSP_SD_ERROR: Sequence failed\n  *         - BSP_SD_OK: Sequence succeed\n  */\nuint8_t\nBSP_SD_Init(void)\n{\n  /* Configure IO functionalities for SD pin */\n  SD_IO_Init();\n\n  /* SD initialized and set to SPI mode properly */\n  return SD_GoIdleState();\n}\n\n/**\n  * @brief  DeInitializes the SD/SD communication.\n  * @retval The SD Response:\n  *         - BSP_SD_ERROR: Sequence failed\n  *         - BSP_SD_OK: Sequence succeed\n  */\nuint8_t\nBSP_SD_DeInit(void)\n{\n  uint8_t sd_state = BSP_SD_OK;\n\n  return  sd_state;\n}\n\n/**\n  * @brief  Reads block(s) from a specified address in the SD card, in polling mode.\n  * @param  pData: Pointer to the buffer that will contain the data to transmit\n  * @param  ReadAddr: Address from where data is to be read. The address is counted\n  *                   in blocks of 512bytes\n  * @param  NumOfBlocks: Number of SD blocks to read\n  * @param  Timeout: This parameter is used for compatibility with BSP implementation\n  * @retval SD status\n  */\nuint8_t\nBSP_SD_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t Timeout)\n{\n  uint32_t offset = 0;\n  uint32_t addr;\n  uint8_t retr = BSP_SD_ERROR;\n  uint8_t ptr[sizeof(uint8_t) * SD_BLOCK_SIZE];\n  SD_CmdAnswer_typedef response;\n\n  /* Send CMD16 (SD_CMD_SET_BLOCKLEN) to set the size of the block and\n     Check if the SD acknowledged the set block length command: R1 response (0x00: no errors) */\n  response = SD_SendCmd(SD_CMD_SET_BLOCKLEN, SD_BLOCK_SIZE, 0xFF, SD_ANSWER_R1_EXPECTED);\n  SD_IO_CSState(1);\n  SD_IO_WriteByte(SD_DUMMY_BYTE);\n  if ( response.r1 != SD_R1_NO_ERROR)\n  {\n     goto error;\n  }\n\n  bzero(ptr, sizeof(uint8_t) * SD_BLOCK_SIZE);\n\n  /* Initialize the address */\n  addr = (ReadAddr * ((flag_SDHC == 1) ? 1 : SD_BLOCK_SIZE));\n\n  /* Data transfer */\n  while (NumOfBlocks--)\n  {\n    /* Send CMD17 (SD_CMD_READ_SINGLE_BLOCK) to read one block */\n    /* Check if the SD acknowledged the read block command: R1 response (0x00: no errors) */\n    response = SD_SendCmd(SD_CMD_READ_SINGLE_BLOCK, addr, 0xFF, SD_ANSWER_R1_EXPECTED);\n    if ( response.r1 != SD_R1_NO_ERROR)\n    {\n      goto error;\n    }\n\n    /* Now look for the data token to signify the start of the data */\n    if (SD_WaitData(SD_TOKEN_START_DATA_SINGLE_BLOCK_READ) == BSP_SD_OK)\n    {\n      /* Read the SD block data : read NumByteToRead data */\n      SD_IO_WriteReadData(ptr, (uint8_t*)pData + offset, SD_BLOCK_SIZE);\n\n      /* Set next read address*/\n      offset += SD_BLOCK_SIZE;\n      addr = ((flag_SDHC == 1) ? (addr + 1) : (addr + SD_BLOCK_SIZE));\n\n      /* get CRC bytes (not really needed by us, but required by SD) */\n      SD_IO_WriteByte(SD_DUMMY_BYTE);\n      SD_IO_WriteByte(SD_DUMMY_BYTE);\n    }\n    else\n    {\n      goto error;\n    }\n\n    /* End the command data read cycle */\n    SD_IO_CSState(1);\n    SD_IO_WriteByte(SD_DUMMY_BYTE);\n  }\n\n  retr = BSP_SD_OK;\n\nerror:\n  /* Send dummy byte: 8 Clock pulses of delay */\n  SD_IO_CSState(1);\n  SD_IO_WriteByte(SD_DUMMY_BYTE);\n\n  /* Return the response */\n  return retr;\n}\n\n/**\n  * @brief  Writes block(s) to a specified address in the SD card, in polling mode.\n  * @param  pData: Pointer to the buffer that will contain the data to transmit\n  * @param  WriteAddr: Address from where data is to be written. The address is counted\n  *                   in blocks of 512bytes\n  * @param  NumOfBlocks: Number of SD blocks to write\n  * @param  Timeout: This parameter is used for compatibility with BSP implementation\n  * @retval SD status\n  */\nuint8_t\nBSP_SD_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32_t Timeout)\n{\n  uint32_t offset = 0;\n  uint32_t addr;\n  uint8_t retr = BSP_SD_ERROR;\n  uint8_t ptr[sizeof(uint8_t) * SD_BLOCK_SIZE];\n  SD_CmdAnswer_typedef response;\n\n  /* Send CMD16 (SD_CMD_SET_BLOCKLEN) to set the size of the block and\n     Check if the SD acknowledged the set block length command: R1 response (0x00: no errors) */\n  response = SD_SendCmd(SD_CMD_SET_BLOCKLEN, SD_BLOCK_SIZE, 0xFF, SD_ANSWER_R1_EXPECTED);\n  SD_IO_CSState(1);\n  SD_IO_WriteByte(SD_DUMMY_BYTE);\n  if ( response.r1 != SD_R1_NO_ERROR)\n  {\n    goto error;\n  }\n\n  /* Initialize the address */\n  addr = (WriteAddr * ((flag_SDHC == 1) ? 1 : SD_BLOCK_SIZE));\n\n  /* Data transfer */\n  while (NumOfBlocks--)\n  {\n    /* Send CMD24 (SD_CMD_WRITE_SINGLE_BLOCK) to write blocks  and\n       Check if the SD acknowledged the write block command: R1 response (0x00: no errors) */\n    response = SD_SendCmd(SD_CMD_WRITE_SINGLE_BLOCK, addr, 0xFF, SD_ANSWER_R1_EXPECTED);\n    if (response.r1 != SD_R1_NO_ERROR)\n    {\n      goto error;\n    }\n\n    /* Send dummy byte for NWR timing : one byte between CMDWRITE and TOKEN */\n    SD_IO_WriteByte(SD_DUMMY_BYTE);\n    SD_IO_WriteByte(SD_DUMMY_BYTE);\n\n    /* Send the data token to signify the start of the data */\n    SD_IO_WriteByte(SD_TOKEN_START_DATA_SINGLE_BLOCK_WRITE);\n\n    /* Write the block data to SD */\n    SD_IO_WriteReadData((uint8_t*)pData + offset, ptr, SD_BLOCK_SIZE);\n\n    /* Set next write address */\n    offset += SD_BLOCK_SIZE;\n    addr = ((flag_SDHC == 1) ? (addr + 1) : (addr + SD_BLOCK_SIZE));\n\n    /* Put CRC bytes (not really needed by us, but required by SD) */\n    SD_IO_WriteByte(SD_DUMMY_BYTE);\n    SD_IO_WriteByte(SD_DUMMY_BYTE);\n\n    /* Read data response */\n    if (SD_GetDataResponse() != SD_DATA_OK)\n    {\n      /* Set response value to failure */\n      goto error;\n    }\n\n    SD_IO_CSState(1);\n    SD_IO_WriteByte(SD_DUMMY_BYTE);\n  }\n  retr = BSP_SD_OK;\n\nerror:\n  /* Send dummy byte: 8 Clock pulses of delay */\n  SD_IO_CSState(1);\n  SD_IO_WriteByte(SD_DUMMY_BYTE);\n\n  /* Return the response */\n  return retr;\n}\n\n/**\n  * @brief  Erases the specified memory area of the given SD card.\n  * @param  StartAddr: Start address in Blocks (Size of a block is 512bytes)\n  * @param  EndAddr: End address in Blocks (Size of a block is 512bytes)\n  * @retval SD status\n  */\nuint8_t\nBSP_SD_Erase(uint32_t StartAddr, uint32_t EndAddr)\n{\n  uint8_t retr = BSP_SD_ERROR;\n  SD_CmdAnswer_typedef response;\n\n  /* Send CMD32 (Erase group start) and check if the SD acknowledged the erase command: R1 response (0x00: no errors) */\n  response = SD_SendCmd(SD_CMD_SD_ERASE_GRP_START, (StartAddr) * (flag_SDHC == 1 ? 1 : SD_BLOCK_SIZE), 0xFF, SD_ANSWER_R1_EXPECTED);\n  SD_IO_CSState(1);\n  SD_IO_WriteByte(SD_DUMMY_BYTE);\n  if (response.r1 == SD_R1_NO_ERROR)\n  {\n    /* Send CMD33 (Erase group end) and Check if the SD acknowledged the erase command: R1 response (0x00: no errors) */\n    response = SD_SendCmd(SD_CMD_SD_ERASE_GRP_END, (EndAddr*512) * (flag_SDHC == 1 ? 1 : SD_BLOCK_SIZE), 0xFF, SD_ANSWER_R1_EXPECTED);\n    SD_IO_CSState(1);\n    SD_IO_WriteByte(SD_DUMMY_BYTE);\n    if (response.r1 == SD_R1_NO_ERROR)\n    {\n      /* Send CMD38 (Erase) and Check if the SD acknowledged the erase command: R1 response (0x00: no errors) */\n      response = SD_SendCmd(SD_CMD_ERASE, 0, 0xFF, SD_ANSWER_R1B_EXPECTED);\n      if (response.r1 == SD_R1_NO_ERROR)\n      {\n        retr = BSP_SD_OK;\n      }\n      SD_IO_CSState(1);\n      SD_IO_WriteByte(SD_DUMMY_BYTE);\n    }\n  }\n\n  /* Return the response */\n  return retr;\n}\n\n/**\n  * @brief  Returns the SD status.\n  * @param  None\n  * @retval The SD status.\n  */\nuint8_t\nBSP_SD_GetCardState(void)\n{\n  SD_CmdAnswer_typedef retr;\n\n  /* Send CMD13 (SD_SEND_STATUS) to get SD status */\n  retr = SD_SendCmd(SD_CMD_SEND_STATUS, 0, 0xFF, SD_ANSWER_R2_EXPECTED);\n  SD_IO_CSState(1);\n  SD_IO_WriteByte(SD_DUMMY_BYTE);\n\n  /* Find SD status according to card state */\n  if(( retr.r1 == SD_R1_NO_ERROR) && ( retr.r2 == SD_R2_NO_ERROR))\n  {\n    return BSP_SD_OK;\n  }\n\n  return BSP_SD_ERROR;\n}\n\n/**\n  * @brief  Returns information about specific card.\n  * @param  pCardInfo: Pointer to a BSP_SD_CardInfo structure that contains all SD\n  *         card information.\n  * @retval The SD Response:\n  *         - BSP_SD_ERROR: Sequence failed\n  *         - BSP_SD_OK: Sequence succeed\n  */\nuint8_t\nBSP_SD_GetCardInfo(BSP_SD_CardInfo *pCardInfo)\n{\n  uint8_t status;\n\n  status = SD_GetCSDRegister(&(pCardInfo->Csd));\n  status|= SD_GetCIDRegister(&(pCardInfo->Cid));\n  if(flag_SDHC == 1 )\n  {\n    pCardInfo->LogBlockSize = 512;\n    pCardInfo->CardBlockSize = 512;\n    pCardInfo->CardCapacity = (pCardInfo->Csd.version.v2.DeviceSize + 1) * 1024 * pCardInfo->LogBlockSize;\n    pCardInfo->LogBlockNbr = (pCardInfo->CardCapacity) / (pCardInfo->LogBlockSize);\n  }\n  else\n  {\n    pCardInfo->CardCapacity = (pCardInfo->Csd.version.v1.DeviceSize + 1) ;\n    pCardInfo->CardCapacity *= (1 << (pCardInfo->Csd.version.v1.DeviceSizeMul + 2));\n    pCardInfo->LogBlockSize = 512;\n    pCardInfo->CardBlockSize = 1 << (pCardInfo->Csd.RdBlockLen);\n    pCardInfo->CardCapacity *= pCardInfo->CardBlockSize;\n    pCardInfo->LogBlockNbr = (pCardInfo->CardCapacity) / (pCardInfo->LogBlockSize);\n  }\n\n  return status;\n}\n\n/* Private functions ---------------------------------------------------------*/\n\n/**\n  * @brief  Reads the SD card CSD register.\n  *         Reading the contents of the CSD register in SPI mode is a simple\n  *         read-block transaction.\n  * @param  Csd: pointer on an CSD register structure\n  * @retval SD status\n  */\nuint8_t\nSD_GetCSDRegister(SD_CSD* Csd)\n{\n  uint16_t counter = 0;\n  uint8_t CSD_Tab[16];\n  uint8_t retr = BSP_SD_ERROR;\n  SD_CmdAnswer_typedef response;\n\n  /* Send CMD9 (CSD register) and Wait for response in the R1 format (0x00 is no errors) */\n  response = SD_SendCmd(SD_CMD_SEND_CSD, 0, 0xFF, SD_ANSWER_R1_EXPECTED);\n  if(response.r1 == SD_R1_NO_ERROR)\n  {\n    if (SD_WaitData(SD_TOKEN_START_DATA_SINGLE_BLOCK_READ) == BSP_SD_OK)\n    {\n      for (counter = 0; counter < 16; counter++)\n      {\n        /* Store CSD register value on CSD_Tab */\n        CSD_Tab[counter] = SD_IO_WriteByte(SD_DUMMY_BYTE);\n      }\n\n      /* Get CRC bytes (not really needed by us, but required by SD) */\n      SD_IO_WriteByte(SD_DUMMY_BYTE);\n      SD_IO_WriteByte(SD_DUMMY_BYTE);\n\n      /*************************************************************************\n        CSD header decoding\n      *************************************************************************/\n\n      /* Byte 0 */\n      Csd->CSDStruct = (CSD_Tab[0] & 0xC0) >> 6;\n      Csd->Reserved1 =  CSD_Tab[0] & 0x3F;\n\n      /* Byte 1 */\n      Csd->TAAC = CSD_Tab[1];\n\n      /* Byte 2 */\n      Csd->NSAC = CSD_Tab[2];\n\n      /* Byte 3 */\n      Csd->MaxBusClkFrec = CSD_Tab[3];\n\n      /* Byte 4/5 */\n      Csd->CardComdClasses = (CSD_Tab[4] << 4) | ((CSD_Tab[5] & 0xF0) >> 4);\n      Csd->RdBlockLen = CSD_Tab[5] & 0x0F;\n\n      /* Byte 6 */\n      Csd->PartBlockRead   = (CSD_Tab[6] & 0x80) >> 7;\n      Csd->WrBlockMisalign = (CSD_Tab[6] & 0x40) >> 6;\n      Csd->RdBlockMisalign = (CSD_Tab[6] & 0x20) >> 5;\n      Csd->DSRImpl         = (CSD_Tab[6] & 0x10) >> 4;\n\n      /*************************************************************************\n        CSD v1/v2 decoding\n      *************************************************************************/\n\n      if(flag_SDHC == 0)\n      {\n        Csd->version.v1.Reserved1 = ((CSD_Tab[6] & 0x0C) >> 2);\n\n        Csd->version.v1.DeviceSize =  ((CSD_Tab[6] & 0x03) << 10)\n                                    |  (CSD_Tab[7] << 2)\n                                    | ((CSD_Tab[8] & 0xC0) >> 6);\n        Csd->version.v1.MaxRdCurrentVDDMin = (CSD_Tab[8] & 0x38) >> 3;\n        Csd->version.v1.MaxRdCurrentVDDMax = (CSD_Tab[8] & 0x07);\n        Csd->version.v1.MaxWrCurrentVDDMin = (CSD_Tab[9] & 0xE0) >> 5;\n        Csd->version.v1.MaxWrCurrentVDDMax = (CSD_Tab[9] & 0x1C) >> 2;\n        Csd->version.v1.DeviceSizeMul = ((CSD_Tab[9] & 0x03) << 1)\n                                       |((CSD_Tab[10] & 0x80) >> 7);\n      }\n      else\n      {\n        Csd->version.v2.Reserved1 = ((CSD_Tab[6] & 0x0F) << 2) | ((CSD_Tab[7] & 0xC0) >> 6);\n        Csd->version.v2.DeviceSize= ((CSD_Tab[7] & 0x3F) << 16) | (CSD_Tab[8] << 8) | CSD_Tab[9];\n        Csd->version.v2.Reserved2 = ((CSD_Tab[10] & 0x80) >> 8);\n      }\n\n      Csd->EraseSingleBlockEnable = (CSD_Tab[10] & 0x40) >> 6;\n      Csd->EraseSectorSize   = ((CSD_Tab[10] & 0x3F) << 1)\n                              |((CSD_Tab[11] & 0x80) >> 7);\n      Csd->WrProtectGrSize   = (CSD_Tab[11] & 0x7F);\n      Csd->WrProtectGrEnable = (CSD_Tab[12] & 0x80) >> 7;\n      Csd->Reserved2         = (CSD_Tab[12] & 0x60) >> 5;\n      Csd->WrSpeedFact       = (CSD_Tab[12] & 0x1C) >> 2;\n      Csd->MaxWrBlockLen     = ((CSD_Tab[12] & 0x03) << 2)\n                              |((CSD_Tab[13] & 0xC0) >> 6);\n      Csd->WriteBlockPartial = (CSD_Tab[13] & 0x20) >> 5;\n      Csd->Reserved3         = (CSD_Tab[13] & 0x1F);\n      Csd->FileFormatGroup   = (CSD_Tab[14] & 0x80) >> 7;\n      Csd->CopyFlag          = (CSD_Tab[14] & 0x40) >> 6;\n      Csd->PermWrProtect     = (CSD_Tab[14] & 0x20) >> 5;\n      Csd->TempWrProtect     = (CSD_Tab[14] & 0x10) >> 4;\n      Csd->FileFormat        = (CSD_Tab[14] & 0x0C) >> 2;\n      Csd->Reserved4         = (CSD_Tab[14] & 0x03);\n      Csd->crc               = (CSD_Tab[15] & 0xFE) >> 1;\n      Csd->Reserved5         = (CSD_Tab[15] & 0x01);\n\n      retr = BSP_SD_OK;\n    }\n  }\n\n  /* Send dummy byte: 8 Clock pulses of delay */\n  SD_IO_CSState(1);\n  SD_IO_WriteByte(SD_DUMMY_BYTE);\n\n  /* Return the response */\n  return retr;\n}\n\n/**\n  * @brief  Reads the SD card CID register.\n  *         Reading the contents of the CID register in SPI mode is a simple\n  *         read-block transaction.\n  * @param  Cid: pointer on an CID register structure\n  * @retval SD status\n  */\nuint8_t\nSD_GetCIDRegister(SD_CID* Cid)\n{\n  uint32_t counter = 0;\n  uint8_t CID_Tab[16];\n  uint8_t retr = BSP_SD_ERROR;\n  SD_CmdAnswer_typedef response;\n\n  /* Send CMD10 (CID register) and Wait for response in the R1 format (0x00 is no errors) */\n  response = SD_SendCmd(SD_CMD_SEND_CID, 0, 0xFF, SD_ANSWER_R1_EXPECTED);\n  if(response.r1 == SD_R1_NO_ERROR)\n  {\n    if (SD_WaitData(SD_TOKEN_START_DATA_SINGLE_BLOCK_READ) == BSP_SD_OK)\n    {\n      for (counter = 0; counter < 16; counter++)\n      {\n        /* Store CID register value on CID_Tab */\n        CID_Tab[counter] = SD_IO_WriteByte(SD_DUMMY_BYTE);\n      }\n\n      /* Get CRC bytes (not really needed by us, but required by SD) */\n      SD_IO_WriteByte(SD_DUMMY_BYTE);\n      SD_IO_WriteByte(SD_DUMMY_BYTE);\n\n      /* Byte 0 */\n      Cid->ManufacturerID = CID_Tab[0];\n\n      /* Byte 1 */\n      Cid->OEM_AppliID = CID_Tab[1] << 8;\n\n      /* Byte 2 */\n      Cid->OEM_AppliID |= CID_Tab[2];\n\n      /* Byte 3 */\n      Cid->ProdName1 = CID_Tab[3] << 24;\n\n      /* Byte 4 */\n      Cid->ProdName1 |= CID_Tab[4] << 16;\n\n      /* Byte 5 */\n      Cid->ProdName1 |= CID_Tab[5] << 8;\n\n      /* Byte 6 */\n      Cid->ProdName1 |= CID_Tab[6];\n\n      /* Byte 7 */\n      Cid->ProdName2 = CID_Tab[7];\n\n      /* Byte 8 */\n      Cid->ProdRev = CID_Tab[8];\n\n      /* Byte 9 */\n      Cid->ProdSN = CID_Tab[9] << 24;\n\n      /* Byte 10 */\n      Cid->ProdSN |= CID_Tab[10] << 16;\n\n      /* Byte 11 */\n      Cid->ProdSN |= CID_Tab[11] << 8;\n\n      /* Byte 12 */\n      Cid->ProdSN |= CID_Tab[12];\n\n      /* Byte 13 */\n      Cid->Reserved1 |= (CID_Tab[13] & 0xF0) >> 4;\n      Cid->ManufactDate = (CID_Tab[13] & 0x0F) << 8;\n\n      /* Byte 14 */\n      Cid->ManufactDate |= CID_Tab[14];\n\n      /* Byte 15 */\n      Cid->CID_CRC = (CID_Tab[15] & 0xFE) >> 1;\n      Cid->Reserved2 = 1;\n\n      retr = BSP_SD_OK;\n    }\n  }\n\n  /* Send dummy byte: 8 Clock pulses of delay */\n  SD_IO_CSState(1);\n  SD_IO_WriteByte(SD_DUMMY_BYTE);\n\n  /* Return the response */\n  return retr;\n}\n\n/**\n  * @brief  Sends 5 bytes command to the SD card and get response\n  * @param  Cmd: The user expected command to send to SD card.\n  * @param  Arg: The command argument.\n  * @param  Crc: The CRC.\n  * @param  Answer: SD_ANSWER_NOT_EXPECTED or SD_ANSWER_EXPECTED\n  * @retval SD status\n  */\nSD_CmdAnswer_typedef\nSD_SendCmd(uint8_t Cmd, uint32_t Arg, uint8_t Crc, uint8_t Answer)\n{\n  uint8_t frame[SD_CMD_LENGTH], frameout[SD_CMD_LENGTH];\n  SD_CmdAnswer_typedef retr = {0xFF, 0xFF , 0xFF, 0xFF, 0xFF};\n\n  /* R1 Length = NCS(0)+ 6 Bytes command + NCR(min1 max8) + 1 Bytes answer + NEC(0) = 15bytes */\n  /* R1b identical to R1 + Busy information                                                   */\n  /* R2 Length = NCS(0)+ 6 Bytes command + NCR(min1 max8) + 2 Bytes answer + NEC(0) = 16bytes */\n\n  /* Prepare Frame to send */\n  frame[0] = (Cmd | 0x40);         /* Construct byte 1 */\n  frame[1] = (uint8_t)(Arg >> 24); /* Construct byte 2 */\n  frame[2] = (uint8_t)(Arg >> 16); /* Construct byte 3 */\n  frame[3] = (uint8_t)(Arg >> 8);  /* Construct byte 4 */\n  frame[4] = (uint8_t)(Arg);       /* Construct byte 5 */\n  frame[5] = (Crc | 0x01);         /* Construct byte 6 */\n\n  /* Send the command */\n  SD_IO_CSState(0);\n  SD_IO_WriteReadData(frame, frameout, SD_CMD_LENGTH); /* Send the Cmd bytes */\n\n  switch(Answer)\n  {\n  case SD_ANSWER_R1_EXPECTED:\n    retr.r1 = SD_ReadData();\n    break;\n  case SD_ANSWER_R1B_EXPECTED:\n    retr.r1 = SD_ReadData();\n    retr.r2 = SD_IO_WriteByte(SD_DUMMY_BYTE);\n    /* Set CS High */\n    SD_IO_CSState(1);\n    HAL_Delay(1);\n    /* Set CS Low */\n    SD_IO_CSState(0);\n\n    /* Wait IO line return 0xFF */\n    while (SD_IO_WriteByte(SD_DUMMY_BYTE) != 0xFF);\n    break;\n  case SD_ANSWER_R2_EXPECTED:\n    retr.r1 = SD_ReadData();\n    retr.r2 = SD_IO_WriteByte(SD_DUMMY_BYTE);\n    break;\n  case SD_ANSWER_R3_EXPECTED:\n  case SD_ANSWER_R7_EXPECTED:\n    retr.r1 = SD_ReadData();\n    retr.r2 = SD_IO_WriteByte(SD_DUMMY_BYTE);\n    retr.r3 = SD_IO_WriteByte(SD_DUMMY_BYTE);\n    retr.r4 = SD_IO_WriteByte(SD_DUMMY_BYTE);\n    retr.r5 = SD_IO_WriteByte(SD_DUMMY_BYTE);\n    break;\n  default:\n    break;\n  }\n  return retr;\n}\n\n/**\n  * @brief  Gets the SD card data response and check the busy flag.\n  * @param  None\n  * @retval The SD status: Read data response xxx0<status>1\n  *         - status 010: Data accepted\n  *         - status 101: Data rejected due to a crc error\n  *         - status 110: Data rejected due to a Write error.\n  *         - status 111: Data rejected due to other error.\n  */\nuint8_t\nSD_GetDataResponse(void)\n{\n  uint8_t dataresponse;\n  uint8_t rvalue = SD_DATA_OTHER_ERROR;\n\n  dataresponse = SD_IO_WriteByte(SD_DUMMY_BYTE);\n  SD_IO_WriteByte(SD_DUMMY_BYTE); /* read the busy response byte*/\n\n  /* Mask unused bits */\n  switch (dataresponse & 0x1F)\n  {\n  case SD_DATA_OK:\n    rvalue = SD_DATA_OK;\n\n    /* Set CS High */\n    SD_IO_CSState(1);\n    /* Set CS Low */\n    SD_IO_CSState(0);\n\n    /* Wait IO line return 0xFF */\n    while (SD_IO_WriteByte(SD_DUMMY_BYTE) != 0xFF);\n    break;\n  case SD_DATA_CRC_ERROR:\n    rvalue =  SD_DATA_CRC_ERROR;\n    break;\n  case SD_DATA_WRITE_ERROR:\n    rvalue = SD_DATA_WRITE_ERROR;\n    break;\n  default:\n    break;\n  }\n\n  /* Return response */\n  return rvalue;\n}\n\n/**\n  * @brief  Waits a data until a value different from SD_DUMMY_BITE\n  * @param  None\n  * @retval the value read\n  */\nuint8_t\nSD_ReadData(void)\n{\n  uint8_t timeout = 0x08;\n  uint8_t readvalue;\n\n  /* Check if response is got or a timeout is happen */\n  do {\n    readvalue = SD_IO_WriteByte(SD_DUMMY_BYTE);\n    timeout--;\n\n  }while ((readvalue == SD_DUMMY_BYTE) && timeout);\n\n  /* Right response got */\n  return readvalue;\n}\n\n/**\n  * @brief  Waits a data from the SD card\n  * @param  data : Expected data from the SD card\n  * @retval BSP_SD_OK or BSP_SD_TIMEOUT\n  */\nuint8_t\nSD_WaitData(uint8_t data)\n{\n  uint16_t timeout = 0xFFFF;\n  uint8_t readvalue;\n\n  /* Check if response is got or a timeout is happen */\n\n  do {\n    readvalue = SD_IO_WriteByte(SD_DUMMY_BYTE);\n    timeout--;\n  }while ((readvalue != data) && timeout);\n\n  if (timeout == 0)\n  {\n    /* After time out */\n    return BSP_SD_TIMEOUT;\n  }\n\n  /* Right response got */\n  return BSP_SD_OK;\n}\n\n/**\n  * @brief  Put the SD in Idle state.\n  * @param  None\n  * @retval SD status\n  */\nuint8_t\nSD_GoIdleState(void)\n{\n  SD_CmdAnswer_typedef response;\n  __IO uint8_t counter = 0;\n  /* Send CMD0 (SD_CMD_GO_IDLE_STATE) to put SD in SPI mode and\n     wait for In Idle State Response (R1 Format) equal to 0x01 */\n  do{\n    counter++;\n    response = SD_SendCmd(SD_CMD_GO_IDLE_STATE, 0, 0x95, SD_ANSWER_R1_EXPECTED);\n    SD_IO_CSState(1);\n    SD_IO_WriteByte(SD_DUMMY_BYTE);\n    if(counter >= SD_MAX_TRY)\n    {\n      return BSP_SD_ERROR;\n    }\n  }\n  while(response.r1 != SD_R1_IN_IDLE_STATE);\n\n\n  /* Send CMD8 (SD_CMD_SEND_IF_COND) to check the power supply status\n     and wait until response (R7 Format) equal to 0xAA and */\n  response = SD_SendCmd(SD_CMD_SEND_IF_COND, 0x1AA, 0x87, SD_ANSWER_R7_EXPECTED);\n  SD_IO_CSState(1);\n  SD_IO_WriteByte(SD_DUMMY_BYTE);\n  if((response.r1  & SD_R1_ILLEGAL_COMMAND) == SD_R1_ILLEGAL_COMMAND)\n  {\n    /* Initialize card V1 */\n    do\n    {\n      /* Initialize card V1 */\n      /* Send CMD55 (SD_CMD_APP_CMD) before any ACMD command: R1 response (0x00: no errors) */\n      response = SD_SendCmd(SD_CMD_APP_CMD, 0x00000000, 0xFF, SD_ANSWER_R1_EXPECTED);\n      SD_IO_CSState(1);\n      SD_IO_WriteByte(SD_DUMMY_BYTE);\n\n      /* Send ACMD41 (SD_CMD_SD_APP_OP_COND) to initialize SDHC or SDXC cards: R1 response (0x00: no errors) */\n      response = SD_SendCmd(SD_CMD_SD_APP_OP_COND, 0x00000000, 0xFF, SD_ANSWER_R1_EXPECTED);\n      SD_IO_CSState(1);\n      SD_IO_WriteByte(SD_DUMMY_BYTE);\n    }\n    while(response.r1 == SD_R1_IN_IDLE_STATE);\n    flag_SDHC = 0;\n  }\n  else if(response.r1 == SD_R1_IN_IDLE_STATE)\n  {\n      /* Initialize card V2 */\n    do {\n\n      /* Send CMD55 (SD_CMD_APP_CMD) before any ACMD command: R1 response (0x00: no errors) */\n      response = SD_SendCmd(SD_CMD_APP_CMD, 0, 0xFF, SD_ANSWER_R1_EXPECTED);\n      SD_IO_CSState(1);\n      SD_IO_WriteByte(SD_DUMMY_BYTE);\n\n      /* Send ACMD41 (SD_CMD_SD_APP_OP_COND) to initialize SDHC or SDXC cards: R1 response (0x00: no errors) */\n      response = SD_SendCmd(SD_CMD_SD_APP_OP_COND, 0x40000000, 0xFF, SD_ANSWER_R1_EXPECTED);\n      SD_IO_CSState(1);\n      SD_IO_WriteByte(SD_DUMMY_BYTE);\n    }\n    while(response.r1 == SD_R1_IN_IDLE_STATE);\n\n    if((response.r1 & SD_R1_ILLEGAL_COMMAND) == SD_R1_ILLEGAL_COMMAND)\n    {\n      do {\n        /* Send CMD55 (SD_CMD_APP_CMD) before any ACMD command: R1 response (0x00: no errors) */\n        response = SD_SendCmd(SD_CMD_APP_CMD, 0, 0xFF, SD_ANSWER_R1_EXPECTED);\n        SD_IO_CSState(1);\n        SD_IO_WriteByte(SD_DUMMY_BYTE);\n        if(response.r1 != SD_R1_IN_IDLE_STATE)\n        {\n          return BSP_SD_ERROR;\n        }\n        /* Send ACMD41 (SD_CMD_SD_APP_OP_COND) to initialize SDHC or SDXC cards: R1 response (0x00: no errors) */\n        response = SD_SendCmd(SD_CMD_SD_APP_OP_COND, 0x00000000, 0xFF, SD_ANSWER_R1_EXPECTED);\n        SD_IO_CSState(1);\n        SD_IO_WriteByte(SD_DUMMY_BYTE);\n      }\n      while(response.r1 == SD_R1_IN_IDLE_STATE);\n    }\n\n    /* Send CMD58 (SD_CMD_READ_OCR) to initialize SDHC or SDXC cards: R3 response (0x00: no errors) */\n    response = SD_SendCmd(SD_CMD_READ_OCR, 0x00000000, 0xFF, SD_ANSWER_R3_EXPECTED);\n    SD_IO_CSState(1);\n    SD_IO_WriteByte(SD_DUMMY_BYTE);\n    if(response.r1 != SD_R1_NO_ERROR)\n    {\n      return BSP_SD_ERROR;\n    }\n    flag_SDHC = (response.r2 & 0x40) >> 6;\n  }\n  else\n  {\n    return BSP_SD_ERROR;\n  }\n\n  return BSP_SD_OK;\n}\n\n#endif /* SPI_SD_ENABLED */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/dev/stm32_bsp.c",
    "content": "/*\n * Copyright (c) 2022 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include <stm32/dev/stm32_bsp.h>\n\n#include <stm32/hal/stm32f4xx_ll_gpio.h>\n\nstruct bsp_gpio {\n\tGPIO_TypeDef\t*port;\n\tuint32_t\t pin;\n\tuint32_t\t invert;\n};\n\nstatic const struct bsp_gpio led[LED_COUNT] = {\n#ifdef LED1_GPIO_PORT\n\t{ LED1_GPIO_PORT, LED1_PIN, LED1_INVERT },\n#endif\n#ifdef LED2_GPIO_PORT\n\t{ LED2_GPIO_PORT, LED2_PIN, LED2_INVERT },\n#endif\n#ifdef LED3_GPIO_PORT\n\t{ LED3_GPIO_PORT, LED3_PIN, LED3_INVERT },\n#endif\n#ifdef LED4_GPIO_PORT\n\t{ LED4_GPIO_PORT, LED4_PIN, LED4_INVERT },\n#endif\n};\n\nstatic const struct bsp_gpio button[BUTTON_COUNT] = {\n#ifdef BUTTON_USER_GPIO_PORT\n\t{ BUTTON_USER_GPIO_PORT, BUTTON_USER_PIN, BUTTON_USER_INVERT },\n#endif\n};\n\nvoid\nBSP_LED_Init(Led_TypeDef Led)\n{\n\tGPIO_TypeDef *port = led[Led].port;\n\tuint32_t pin = led[Led].pin;\n\tuint32_t invert = led[Led].invert;\n\n\tLL_GPIO_EnableClock(port);\n\n\tLL_GPIO_SetPinMode(port, pin, LL_GPIO_MODE_OUTPUT);\n\tLL_GPIO_SetPinSpeed(port, pin, LL_GPIO_SPEED_FREQ_HIGH);\n\tLL_GPIO_SetPinOutputType(port, pin, LL_GPIO_OUTPUT_PUSHPULL);\n\n\tif (invert) {\n\t\tLL_GPIO_SetPinPull(port, pin, LL_GPIO_PULL_NO);\n\t} else {\n\t\tLL_GPIO_SetPinPull(port, pin, LL_GPIO_PULL_UP);\n\t}\n\n\tBSP_LED_Off(Led);\n}\n\nvoid\nBSP_LED_On(Led_TypeDef Led)\n{\n\tGPIO_TypeDef *port = led[Led].port;\n\tuint32_t pin = led[Led].pin;\n\tuint32_t invert = led[Led].invert;\n\n\tif (invert) {\n\t\tLL_GPIO_ResetOutputPin(port, pin);\n\t} else {\n\t\tLL_GPIO_SetOutputPin(port, pin);\n\t}\n}\n\nvoid\nBSP_LED_Off(Led_TypeDef Led)\n{\n\tGPIO_TypeDef *port = led[Led].port;\n\tuint32_t pin = led[Led].pin;\n\tuint32_t invert = led[Led].invert;\n\n\tif (invert) {\n\t\tLL_GPIO_SetOutputPin(port, pin);\n\t} else {\n\t\tLL_GPIO_ResetOutputPin(port, pin);\n\t}\n}\n\nvoid\nBSP_LED_Toggle(Led_TypeDef Led)\n{\n\tGPIO_TypeDef *port = led[Led].port;\n\tuint32_t pin = led[Led].pin;\n\n\tLL_GPIO_TogglePin(port, pin);\n}\n\nvoid\nBSP_PB_Init(Button_TypeDef Button)\n{\n\tGPIO_TypeDef *port = button[Button].port;\n\tuint32_t pin = button[Button].pin;\n\tuint32_t invert = button[Button].invert;\n\n\tLL_GPIO_EnableClock(port);\n\n\tLL_GPIO_SetPinMode(port, pin, LL_GPIO_MODE_INPUT);\n\tLL_GPIO_SetPinSpeed(port, pin, LL_GPIO_SPEED_FREQ_HIGH);\n\n\tif (invert) {\n\t\tLL_GPIO_SetPinPull(port, pin, LL_GPIO_PULL_NO);\n\t} else {\n\t\tLL_GPIO_SetPinPull(port, pin, LL_GPIO_PULL_DOWN);\n\t}\n}\n\nuint32_t\nBSP_PB_GetState(Button_TypeDef Button)\n{\n\tGPIO_TypeDef *port = button[Button].port;\n\tuint32_t pin = button[Button].pin;\n\tuint32_t invert = button[Button].invert;\n\tuint32_t level = LL_GPIO_ReadInputPort(port) & pin;\n\n\tif (invert) {\n\t\treturn ((level == 0) ? 1 : 0);\n\t} else {\n\t\treturn ((level == 0) ? 0 : 1);\n\t}\n}\n"
  },
  {
    "path": "sys/arch/stm32/dev/stm32_bsp.h",
    "content": "/*\n * Copyright (c) 2022 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#ifndef\t_MACHINE_STM32_BSP_H_\n#define\t_MACHINE_STM32_BSP_H_\n\n#ifdef\tKERNEL\n\n#include <stm32/hal/stm32f4xx_hal.h>\n\ntypedef enum {\n#ifdef LED1_GPIO_PORT\n\tLED1,\n#endif\n#ifdef LED2_GPIO_PORT\n\tLED2,\n#endif\n#ifdef LED3_GPIO_PORT\n\tLED3,\n#endif\n#ifdef LED4_GPIO_PORT\n\tLED4,\n#endif\n\tLED_COUNT\n} Led_TypeDef;\n\ntypedef enum {\n#ifdef BUTTON_USER_GPIO_PORT\n\tBUTTON_USER,\n#endif\n\tBUTTON_COUNT\n} Button_TypeDef;\n\nvoid\t\tBSP_LED_Init(Led_TypeDef Led);\nvoid\t\tBSP_LED_On(Led_TypeDef Led);\nvoid\t\tBSP_LED_Off(Led_TypeDef Led);\nvoid\t\tBSP_LED_Toggle(Led_TypeDef Led);\nvoid\t\tBSP_PB_Init(Button_TypeDef Button);\nuint32_t\tBSP_PB_GetState(Button_TypeDef Button);\n\n#endif\t/* KERNEL */\n\n#endif\t/* !_MACHINE_STM32_BSP_H_ */\n"
  },
  {
    "path": "sys/arch/stm32/dev/stm32_bsp_sd.h",
    "content": "/*\n * Copyright (c) 2016, 2017 STMicroelectronics\n *\n * Redistribution and use in source and binary forms, with or without modification,\n * are permitted provided that the following conditions are met:\n *   1. Redistributions of source code must retain the above copyright notice,\n *      this list of conditions and the following disclaimer.\n *   2. Redistributions in binary form must reproduce the above copyright notice,\n *      this list of conditions and the following disclaimer in the documentation\n *      and/or other materials provided with the distribution.\n *   3. Neither the name of STMicroelectronics nor the names of its contributors\n *      may be used to endorse or promote products derived from this software\n *      without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef\t_MACHINE_STM32_BSP_SD_H_\n#define\t_MACHINE_STM32_BSP_SD_H_\n\n#include <stm32/hal/stm32f4xx_hal.h>\n\n#define\tSD_DATATIMEOUT\t((uint32_t)100000000)\n\nenum {\n\tBSP_SD_OK = 0x00,\n\tBSP_SD_ERROR = 0x01,\n\tBSP_SD_TIMEOUT\n};\n\nenum {\n\tSD_TRANSFER_OK = 0x00,\n\tSD_TRANSFER_BUSY = 0x01\n};\n\n#ifdef\tSPI_SD_ENABLED\t\t\t/* Kernel Config 'options' definition. */\n\ntypedef struct {\n\tuint8_t\t\tReserved1:2;\t\t/* Reserved */\n\tuint16_t\tDeviceSize:12;\t\t/* Device Size */\n\tuint8_t\t\tMaxRdCurrentVDDMin:3;\t/* Max. read current @ VDD min */\n\tuint8_t\t\tMaxRdCurrentVDDMax:3;\t/* Max. read current @ VDD max */\n\tuint8_t\t\tMaxWrCurrentVDDMin:3;\t/* Max. write current @ VDD min */\n\tuint8_t\t\tMaxWrCurrentVDDMax:3;\t/* Max. write current @ VDD max */\n\tuint8_t\t\tDeviceSizeMul:3;\t/* Device size multiplier */\n} struct_v1;\n\ntypedef struct {\n\tuint8_t\t\tReserved1:6;\t\t/* Reserved */\n\tuint32_t\tDeviceSize:22;\t\t/* Device Size */\n\tuint8_t\t\tReserved2:1;\t\t/* Reserved */\n} struct_v2;\n\ntypedef struct {\n\t/* Header part */\n\tuint8_t\t\tCSDStruct:2;\t\t/* CSD structure */\n\tuint8_t\t\tReserved1:6;\t\t/* Reserved */\n\tuint8_t\t\tTAAC:8;\t\t\t/* Data read access-time 1 */\n\tuint8_t\t\tNSAC:8;\t\t\t/* Data read access-time 2 in CLK cycles */\n\tuint8_t\t\tMaxBusClkFrec:8;\t/* Max. bus clock frequency */\n\tuint16_t\tCardComdClasses:12;\t/* Card command classes */\n\tuint8_t\t\tRdBlockLen:4;\t\t/* Max. read data block length */\n\tuint8_t\t\tPartBlockRead:1;\t/* Partial blocks for read allowed */\n\tuint8_t\t\tWrBlockMisalign:1;\t/* Write block misalignment */\n\tuint8_t\t\tRdBlockMisalign:1;\t/* Read block misalignment */\n\tuint8_t\t\tDSRImpl:1;\t\t/* DSR implemented */\n\n\t/* v1 or v2 struct */\n\tunion csd_version {\n\t\tstruct_v1\tv1;\n\t\tstruct_v2\tv2;\n\t} version;\n\n\tuint8_t\t\tEraseSingleBlockEnable:1;\t/* Erase single block enable */\n\tuint8_t\t\tEraseSectorSize:7;\t/* Erase group size multiplier */\n\tuint8_t\t\tWrProtectGrSize:7;\t/* Write protect group size */\n\tuint8_t\t\tWrProtectGrEnable:1;\t/* Write protect group enable */\n\tuint8_t\t\tReserved2:2;\t\t/* Reserved */\n\tuint8_t\t\tWrSpeedFact:3;\t\t/* Write speed factor */\n\tuint8_t\t\tMaxWrBlockLen:4;\t/* Max. write data block length */\n\tuint8_t\t\tWriteBlockPartial:1;\t/* Partial blocks for write allowed */\n\tuint8_t\t\tReserved3:5;\t\t/* Reserved */\n\tuint8_t\t\tFileFormatGroup:1;\t/* File format group */\n\tuint8_t\t\tCopyFlag:1;\t\t/* Copy flag (OTP) */\n\tuint8_t\t\tPermWrProtect:1;\t/* Permanent write protection */\n\tuint8_t\t\tTempWrProtect:1;\t/* Temporary write protection */\n\tuint8_t\t\tFileFormat:2;\t\t/* File Format */\n\tuint8_t\t\tReserved4:2;\t\t/* Reserved */\n\tuint8_t\t\tcrc:7;\t\t\t/* Reserved */\n\tuint8_t\t\tReserved5:1;\t\t/* always 1 */\n} SD_CSD;\n\ntypedef struct {\n\t__IO uint8_t\tManufacturerID;\t\t/* ManufacturerID */\n\t__IO uint16_t\tOEM_AppliID;\t\t/* OEM/Application ID */\n\t__IO uint32_t\tProdName1;\t\t/* Product Name part1 */\n\t__IO uint8_t\tProdName2;\t\t/* Product Name part2 */\n\t__IO uint8_t\tProdRev;\t\t/* Product Revision */\n\t__IO uint32_t\tProdSN;\t\t\t/* Product Serial Number */\n\t__IO uint8_t\tReserved1;\t\t/* Reserved1 */\n\t__IO uint16_t\tManufactDate;\t\t/* Manufacturing Date */\n\t__IO uint8_t\tCID_CRC;\t\t/* CID CRC */\n\t__IO uint8_t\tReserved2;\t\t/* always 1 */\n} SD_CID;\n\ntypedef struct {\n\tSD_CSD\t\tCsd;\n\tSD_CID\t\tCid;\n\tuint32_t\tCardCapacity;\t\t/*!< Card Capacity */\n\tuint32_t\tCardBlockSize;\t\t/*!< Card Block Size */\n\tuint32_t\tLogBlockNbr;\t\t/*!< Specifies the Card logical Capacity in blocks */\n\tuint32_t\tLogBlockSize;\t\t/*!< Specifies logical block size in bytes */\n} SD_CardInfo;\n\n#define\tBSP_SD_CardInfo\tSD_CardInfo\n\n/* Link external functions for SD Card peripheral */\nextern void\tSD_IO_Init(void);\nextern void\tSD_IO_CSState(uint8_t state);\nextern void\tSD_IO_WriteReadData(const uint8_t *DataIn, uint8_t *DataOut, uint16_t DataLength);\nextern uint8_t\tSD_IO_WriteByte(uint8_t Data);\n\n/* Link function for HAL delay */\nvoid\tHAL_Delay(__IO uint32_t Delay);\n\n#endif\t/* SPI_SD_ENABLED */\n\n#ifdef\tSDIO_ENABLED\t\t\t/* Kernel Config 'controller' definition. */\n\n#define\tBSP_SD_CardInfo\tHAL_SD_CardInfoTypeDef\n\nvoid\tBSP_SD_MspInit(SD_HandleTypeDef *hsd, void *Params);\nvoid\tBSP_SD_MspDeInit(SD_HandleTypeDef *hsd, void *Params);\n\n#endif\t/* SDIO_ENABLED */\n\nuint8_t\tBSP_SD_Init(void);\nuint8_t\tBSP_SD_DeInit(void);\nuint8_t\tBSP_SD_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t Timeout);\nuint8_t\tBSP_SD_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32_t Timeout);\nuint8_t\tBSP_SD_Erase(uint32_t StartAddr, uint32_t EndAddr);\nuint8_t\tBSP_SD_GetCardState(void);\nuint8_t\tBSP_SD_GetCardInfo(BSP_SD_CardInfo *pCardInfo);\n\n#endif\t/* !_MACHINE_STM32_BSP_SD_H_ */\n"
  },
  {
    "path": "sys/arch/stm32/dev/stm32_sdio_sd.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32_sdio_sd.c\n  * @author  MCD Application Team\n  * @version V2.0.0\n  * @date    27-January-2017\n  * @brief   This file includes the SDIO driver for micro SD cards on boards.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* File Info : -----------------------------------------------------------------\n                                   User NOTES\n1. How To use this driver:\n--------------------------\n   - This driver is used to drive the external micro SD card mounted on boards.\n   - This driver does not need a specific component driver for the micro SD device\n     to be included with.\n\n2. Driver description:\n---------------------\n  + Initialization steps:\n     o Initialize the micro SD card using the BSP_SD_Init() function. This\n       function includes the MSP layer hardware resources initialization and the\n       SDIO interface configuration to interface with the external micro SD. It\n       also includes the micro SD initialization sequence.\n     o Checking the SD card presence is not managed.\n     o The function BSP_SD_GetCardInfo() is used to get the micro SD card information\n       which is stored in the structure \"BSP_SD_CardInfo\".\n\n     + Micro SD card operations\n        o The micro SD card can be accessed with read/write block(s) operations once\n          it is ready for access. The access can be performed whether using the polling\n          mode by calling the functions BSP_SD_ReadBlocks()/BSP_SD_WriteBlocks(), or by DMA\n          transfer using the functions BSP_SD_ReadBlocks_DMA()/BSP_SD_WriteBlocks_DMA()\n        o The DMA transfer complete is used with interrupt mode. Once the SD transfer\n          is complete, the SD interrupt is handled using the function BSP_SD_IRQHandler(),\n          the DMA Tx/Rx transfer complete are handled using the functions\n          BSP_SD_DMA_Tx_IRQHandler()/BSP_SD_DMA_Rx_IRQHandler(). The corresponding user callbacks\n          are implemented by the user at application level.\n        o The SD erase block(s) is performed using the function BSP_SD_Erase() with\n          specifying the number of blocks to erase.\n        o The SD runtime status is returned when calling the function BSP_SD_GetCardState().\n\n------------------------------------------------------------------------------*/\n\n#ifdef SDIO_ENABLED                     /* Kernel Config 'controller' definition. */\n\n/* Includes ------------------------------------------------------------------*/\n#include <stm32/dev/stm32_bsp_sd.h>\n\n#include <stm32/hal/stm32f4xx_ll_bus.h>\n#include <stm32/hal/stm32f4xx_ll_gpio.h>\n\nSD_HandleTypeDef uSdHandle;\n\n/**\n  * @brief  Initializes the SD card device.\n  * @retval SD status\n  */\nuint8_t\nBSP_SD_Init(void)\n{\n  uint8_t sd_state = BSP_SD_OK;\n\n  /* PLLSAI is dedicated to LCD periph. Do not use it to get 48MHz. */\n\n  /* uSD device interface configuration */\n  uSdHandle.Instance = SDIO;\n\n  uSdHandle.Init.ClockEdge           = SDIO_CLOCK_EDGE_RISING;\n  uSdHandle.Init.ClockBypass         = SDIO_CLOCK_BYPASS_DISABLE;\n  uSdHandle.Init.ClockPowerSave      = SDIO_CLOCK_POWER_SAVE_DISABLE;\n  uSdHandle.Init.BusWide             = SDIO_BUS_WIDE_1B;\n  uSdHandle.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_ENABLE;\n\n#if defined(SDIO_XFER_CLK_DIV)       /* Kernel Config 'options' definition. */\n  uSdHandle.Init.ClockDiv            = SDIO_XFER_CLK_DIV;\n#else                                /* Default in stm32f4xx_ll_sdmmc.h */\n  uSdHandle.Init.ClockDiv            = SDIO_TRANSFER_CLK_DIV;\n#endif\n\n  /* Msp SD initialization */\n  BSP_SD_MspInit(&uSdHandle, NULL);\n\n  /* HAL SD initialization */\n  if (HAL_SD_Init(&uSdHandle) != HAL_OK) {\n    sd_state = BSP_SD_ERROR;\n  }\n\n  /* Configure SD Bus width */\n  if (sd_state == BSP_SD_OK) {\n    /* Enable wide operation */\n    if (HAL_SD_ConfigWideBusOperation(&uSdHandle, SDIO_BUS_WIDE_4B) != HAL_OK) {\n      sd_state = BSP_SD_ERROR;\n    } else {\n      sd_state = BSP_SD_OK;\n    }\n  }\n  return  sd_state;\n}\n\n/**\n  * @brief  DeInitializes the SD card device.\n  * @retval SD status\n  */\nuint8_t\nBSP_SD_DeInit(void)\n{\n  uint8_t sd_state = BSP_SD_OK;\n\n  uSdHandle.Instance = SDIO;\n\n  /* HAL SD deinitialization */\n  if (HAL_SD_DeInit(&uSdHandle) != HAL_OK) {\n    sd_state = BSP_SD_ERROR;\n  }\n\n  /* Msp SD deinitialization */\n  uSdHandle.Instance = SDIO;\n  BSP_SD_MspDeInit(&uSdHandle, NULL);\n\n  return  sd_state;\n}\n\n/**\n  * @brief  Reads block(s) from a specified address in an SD card, in polling mode.\n  * @param  pData: Pointer to the buffer that will contain the data to transmit\n  * @param  ReadAddr: Address from where data is to be read\n  * @param  NumOfBlocks: Number of SD blocks to read\n  * @param  Timeout: Timeout for read operation\n  * @retval SD status\n  */\nuint8_t\nBSP_SD_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t Timeout)\n{\n  if (HAL_SD_ReadBlocks(&uSdHandle, (uint8_t *)pData, ReadAddr, NumOfBlocks, Timeout) != HAL_OK) {\n    return BSP_SD_ERROR;\n  } else {\n    return BSP_SD_OK;\n  }\n}\n\n/**\n  * @brief  Writes block(s) to a specified address in an SD card, in polling mode.\n  * @param  pData: Pointer to the buffer that will contain the data to transmit\n  * @param  WriteAddr: Address from where data is to be written\n  * @param  NumOfBlocks: Number of SD blocks to write\n  * @param  Timeout: Timeout for write operation\n  * @retval SD status\n  */\nuint8_t\nBSP_SD_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32_t Timeout)\n{\n  if (HAL_SD_WriteBlocks(&uSdHandle, (uint8_t *)pData, WriteAddr, NumOfBlocks, Timeout) != HAL_OK) {\n    return BSP_SD_ERROR;\n  } else {\n    return BSP_SD_OK;\n  }\n}\n\n/**\n  * @brief  Erases the specified memory area of the given SD card.\n  * @param  StartAddr: Start byte address\n  * @param  EndAddr: End byte address\n  * @retval SD status\n  */\nuint8_t\nBSP_SD_Erase(uint32_t StartAddr, uint32_t EndAddr)\n{\n  if (HAL_SD_Erase(&uSdHandle, StartAddr, EndAddr) != HAL_OK) {\n    return BSP_SD_ERROR;\n  } else {\n    return BSP_SD_OK;\n  }\n}\n\n/**\n  * @brief  Gets the current SD card data status.\n  * @retval Data transfer state.\n  *          This value can be one of the following values:\n  *            @arg  SD_TRANSFER_OK: No data transfer is acting\n  *            @arg  SD_TRANSFER_BUSY: Data transfer is acting\n  */\nuint8_t\nBSP_SD_GetCardState(void)\n{\n  return((HAL_SD_GetCardState(&uSdHandle) == HAL_SD_CARD_TRANSFER ) ? SD_TRANSFER_OK : SD_TRANSFER_BUSY);\n}\n\n/**\n  * @brief  Get SD information about specific SD card.\n  * @param  pCardInfo: Pointer to BSP_SD_CardInfo structure\n  * @retval SD status\n  */\nuint8_t\nBSP_SD_GetCardInfo(BSP_SD_CardInfo *pCardInfo)\n{\n  uint8_t status;\n\n  /* Get SD card Information */\n  status = HAL_SD_GetCardInfo(&uSdHandle, pCardInfo);\n\n  return status;\n}\n\nstruct gpio_pin {\n\tGPIO_TypeDef\t*port;\n\tchar\t\t port_name;\n\tuint32_t\t pin;\n\tuint32_t\t mode;\n\tuint32_t\t speed;\n\tuint32_t\t pull;\n\tuint32_t\t af;\n\tuint32_t\t out_type;\n};\n\nstruct sdio_inst {\n#define\tNUM_PINS\t6\n\tstruct gpio_pin\tpins[NUM_PINS];\n\tint\t\tprio;\n\tint\t\tirq;\n};\n\nstatic const struct sdio_inst sdio = {\n#define\tPIN2\t\tLL_GPIO_PIN_2\n#define\tPIN6\t\tLL_GPIO_PIN_6\n#define\tPIN8\t\tLL_GPIO_PIN_8\n#define\tPIN9\t\tLL_GPIO_PIN_9\n#define\tPIN10\t\tLL_GPIO_PIN_10\n#define\tPIN11\t\tLL_GPIO_PIN_11\n#define\tPIN12\t\tLL_GPIO_PIN_12\n#define\tAF12\t\tLL_GPIO_AF_12\n#define\tALT\t\tLL_GPIO_MODE_ALTERNATE\n#define\tVH\t\tLL_GPIO_SPEED_FREQ_VERY_HIGH\n#define\tPUP\t\tLL_GPIO_PULL_UP\n#define\tOPP\t\tLL_GPIO_OUTPUT_PUSHPULL\n\t{\n\t\t{ GPIOC, 'C', PIN8,  ALT, VH, PUP, AF12, OPP },\t/* D0 */\n\t\t{ GPIOC, 'C', PIN9,  ALT, VH, PUP, AF12, OPP },\t/* D1 */\n\t\t{ GPIOC, 'C', PIN10, ALT, VH, PUP, AF12, OPP },\t/* D2 */\n\t\t{ GPIOC, 'C', PIN11, ALT, VH, PUP, AF12, OPP },\t/* D3 */\n\t\t{ GPIOC, 'C', PIN12, ALT, VH, PUP, AF12, OPP },\t/* CLK */\n#ifdef STM32F413xx\n\t\t{ GPIOA, 'A', PIN6,  ALT, VH, PUP, AF12, OPP },\t/* CMD */\n#else\n\t\t{ GPIOD, 'D', PIN2,  ALT, VH, PUP, AF12, OPP },\t/* CMD */\n#endif\n\t}, IPL_BIO, SDIO_IRQn\n};\n\n/**\n  * @brief  Initializes the SD MSP.\n  * @param  hsd: SD handle\n  * @param  Params : pointer on additional configuration parameters, can be NULL.\n  */\n__weak void\nBSP_SD_MspInit(SD_HandleTypeDef *hsd, void *Params)\n{\n\tint i;\n\tint num_pins = sizeof(sdio.pins) / sizeof(sdio.pins[0]);\n\n\t/* Enable SDIO clock. */\n\tLL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SDIO);\n\n\t/* Enable GPIO clocks and configure GPIO pins. */\n\tfor (i = 0; i < num_pins; ++i) {\n\t\tGPIO_TypeDef\t*port = sdio.pins[i].port;\n\t\tuint32_t\t pin = sdio.pins[i].pin;\n\n\t\tLL_GPIO_EnableClock(port);\n\t\tLL_GPIO_SetPinMode(port, pin, sdio.pins[i].mode);\n\t\tLL_GPIO_SetPinSpeed(port, pin, sdio.pins[i].speed);\n\t\tLL_GPIO_SetPinPull(port, pin, sdio.pins[i].pull);\n\t\tLL_GPIO_SetAFPin(port, pin, sdio.pins[i].af);\n\t\tLL_GPIO_SetPinOutputType(port, pin, sdio.pins[i].out_type);\n\t}\n\n\t/* NVIC configuration for SDIO interrupts. */\n\tarm_intr_set_priority(sdio.irq, sdio.prio);\n\tarm_intr_enable_irq(sdio.irq);\n}\n\n/**\n  * @brief  DeInitializes the SD MSP.\n  * @param  hsd: SD handle\n  * @param  Params : pointer on additional configuration parameters, can be NULL.\n  */\n__weak void\nBSP_SD_MspDeInit(SD_HandleTypeDef *hsd, void *Params)\n{\n\t/* Disable NVIC for SDIO interrupts. */\n\tarm_intr_disable_irq(sdio.irq);\n\n\t/* Disable SDIO clock. */\n\tLL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SDIO);\n}\n\n#endif /* SDIO_ENABLED */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/dev/stm32f4xx_nucleo_sd.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_nucleo_sd.c\n  * @author  MCD Application Team\n  * @version V1.2.6\n  * @date    27-January-2017\n  * @brief   This file provides set of firmware functions to manage:\n  *          - MicroSD available on Adafruit MicroSD Breakout Board+ (ID 254)\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include <stm32/dev/stm32f4xx_nucleo_sd.h>\n\n/**\n * @brief BUS variables\n */\n\n#ifdef HAL_SPI_MODULE_ENABLED\n\nuint32_t SpixTimeout = NUCLEO_SPIx_TIMEOUT_MAX; /*<! Value of Timeout when SPI communication fails */\nstatic SPI_HandleTypeDef hnucleo_Spi;\n\nstatic void       SPIx_Init(void);\nstatic void       SPIx_WriteReadData(const uint8_t *DataIn, uint8_t *DataOut, uint16_t DataLength);\nstatic void       SPIx_Error(void);\nstatic void       SPIx_MspInit(SPI_HandleTypeDef *hspi);\n\n/******************************************************************************\n                            BUS OPERATIONS\n*******************************************************************************/\n\n/******************************* SPI ********************************/\n\n/**\n  * @brief  Initializes SPI MSP.\n  */\nstatic void\nSPIx_MspInit(SPI_HandleTypeDef *hspi)\n{\n  /*** Configure the GPIOs ***/\n  /* Enable GPIO clock */\n  LL_GPIO_EnableClock(NUCLEO_SPIx_SCK_GPIO_PORT);\n  LL_GPIO_EnableClock(NUCLEO_SPIx_MISO_MOSI_GPIO_PORT);\n\n  /* Configure SPI SCK */\n  LL_GPIO_SetPinMode(NUCLEO_SPIx_SCK_GPIO_PORT, NUCLEO_SPIx_SCK_PIN, LL_GPIO_MODE_ALTERNATE);\n  LL_GPIO_SetAFPin(NUCLEO_SPIx_SCK_GPIO_PORT, NUCLEO_SPIx_SCK_PIN, NUCLEO_SPIx_SCK_AF);\n  LL_GPIO_SetPinSpeed(NUCLEO_SPIx_SCK_GPIO_PORT, NUCLEO_SPIx_SCK_PIN, LL_GPIO_SPEED_FREQ_HIGH);\n  LL_GPIO_SetPinPull(NUCLEO_SPIx_SCK_GPIO_PORT, NUCLEO_SPIx_SCK_PIN, LL_GPIO_PULL_UP);\n\n  /* Configure SPI MOSI */\n  LL_GPIO_SetPinMode(NUCLEO_SPIx_MISO_MOSI_GPIO_PORT, NUCLEO_SPIx_MOSI_PIN, LL_GPIO_MODE_ALTERNATE);\n  LL_GPIO_SetAFPin(NUCLEO_SPIx_MISO_MOSI_GPIO_PORT, NUCLEO_SPIx_MOSI_PIN, NUCLEO_SPIx_MISO_MOSI_AF);\n  LL_GPIO_SetPinSpeed(NUCLEO_SPIx_MISO_MOSI_GPIO_PORT, NUCLEO_SPIx_MOSI_PIN, LL_GPIO_SPEED_FREQ_HIGH);\n  LL_GPIO_SetPinPull(NUCLEO_SPIx_MISO_MOSI_GPIO_PORT, NUCLEO_SPIx_MOSI_PIN, LL_GPIO_PULL_DOWN);\n\n  /* Configure SPI MISO */\n  LL_GPIO_SetPinMode(NUCLEO_SPIx_MISO_MOSI_GPIO_PORT, NUCLEO_SPIx_MISO_PIN, LL_GPIO_MODE_ALTERNATE);\n  LL_GPIO_SetAFPin(NUCLEO_SPIx_MISO_MOSI_GPIO_PORT, NUCLEO_SPIx_MISO_PIN, NUCLEO_SPIx_MISO_MOSI_AF);\n  LL_GPIO_SetPinSpeed(NUCLEO_SPIx_MISO_MOSI_GPIO_PORT, NUCLEO_SPIx_MISO_PIN, LL_GPIO_SPEED_FREQ_HIGH);\n  LL_GPIO_SetPinPull(NUCLEO_SPIx_MISO_MOSI_GPIO_PORT, NUCLEO_SPIx_MISO_PIN, LL_GPIO_PULL_DOWN);\n\n  /*** Configure the SPI peripheral ***/\n  /* Enable SPI clock */\n  NUCLEO_SPIx_CLK_ENABLE();\n}\n\n/**\n  * @brief  Initializes SPI HAL.\n  */\nstatic void\nSPIx_Init(void)\n{\n  if (HAL_SPI_GetState(&hnucleo_Spi) == HAL_SPI_STATE_RESET) {\n    /* SPI Config */\n    hnucleo_Spi.Instance = NUCLEO_SPIx;\n      /* SPI baudrate is set to 12,5 MHz maximum (APB1/SPI_BaudRatePrescaler = 100/8 = 12,5 MHz)\n         to verify these constraints:\n          - SD card SPI interface max baudrate is 25MHz for write/read\n          - PCLK2 max frequency is 100 MHz\n       */\n    hnucleo_Spi.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;\n    hnucleo_Spi.Init.Direction = SPI_DIRECTION_2LINES;\n    hnucleo_Spi.Init.CLKPhase = SPI_PHASE_2EDGE;\n    hnucleo_Spi.Init.CLKPolarity = SPI_POLARITY_HIGH;\n    hnucleo_Spi.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\n    hnucleo_Spi.Init.CRCPolynomial = 7;\n    hnucleo_Spi.Init.DataSize = SPI_DATASIZE_8BIT;\n    hnucleo_Spi.Init.FirstBit = SPI_FIRSTBIT_MSB;\n    hnucleo_Spi.Init.NSS = SPI_NSS_SOFT;\n    hnucleo_Spi.Init.TIMode = SPI_TIMODE_DISABLE;\n    hnucleo_Spi.Init.Mode = SPI_MODE_MASTER;\n\n    SPIx_MspInit(&hnucleo_Spi);\n    HAL_SPI_Init(&hnucleo_Spi);\n  }\n}\n\n/**\n  * @brief  SPI Write a byte to device\n  * @param  DataIn: value to be written\n  * @param  DataOut: value to be read\n  * @param  DataLength: length of data\n  */\nstatic void\nSPIx_WriteReadData(const uint8_t *DataIn, uint8_t *DataOut, uint16_t DataLength)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  status = HAL_SPI_TransmitReceive(&hnucleo_Spi, (uint8_t*) DataIn, DataOut, DataLength, SpixTimeout);\n\n  /* Check the communication status */\n  if (status != HAL_OK) {\n    /* Execute user timeout callback */\n    SPIx_Error();\n  }\n}\n\n/**\n  * @brief  SPI error treatment function.\n  */\nstatic void\nSPIx_Error(void)\n{\n  /* De-initialize the SPI communication BUS */\n  HAL_SPI_DeInit(&hnucleo_Spi);\n\n  /* Re-Initiaize the SPI communication BUS */\n  SPIx_Init();\n}\n\n/* To be defined only if provided with the Adafruit MicroSD Breakout Board+ */\n/* https://www.adafruit.com/product/254 */\n#ifdef SPI_SD_ENABLED                   /* Kernel Config 'options' definition. */\n\n/******************************************************************************\n                            LINK OPERATIONS\n*******************************************************************************/\n\n/********************************* LINK SD ************************************/\n/**\n  * @brief  Initializes the SD Card and put it into StandBy State (Ready for\n  *         data transfer).\n  */\nvoid\nSD_IO_Init(void)\n{\n  uint8_t counter;\n\n  /* SD_CS_GPIO Periph clock enable */\n  LL_GPIO_EnableClock(SD_CS_GPIO_PORT);\n\n  /* Configure SD_CS_PIN pin: SD Card CS pin */\n  LL_GPIO_SetPinMode(SD_CS_GPIO_PORT, SD_CS_PIN, LL_GPIO_MODE_OUTPUT);\n  LL_GPIO_SetAFPin(SD_CS_GPIO_PORT, SD_CS_PIN, NUCLEO_SPIx_MISO_MOSI_AF);\n  LL_GPIO_SetPinSpeed(SD_CS_GPIO_PORT, SD_CS_PIN, LL_GPIO_SPEED_FREQ_HIGH);\n  LL_GPIO_SetPinPull(SD_CS_GPIO_PORT, SD_CS_PIN, LL_GPIO_PULL_UP);\n  LL_GPIO_SetPinOutputType(SD_CS_GPIO_PORT, SD_CS_PIN, LL_GPIO_OUTPUT_PUSHPULL);\n\n  /*------------Put SD in SPI mode--------------*/\n  /* SD SPI Config */\n  SPIx_Init();\n\n  /* SD chip select high */\n  SD_CS_HIGH();\n\n  /* Send dummy byte 0xFF, 10 times with CS high */\n  /* Rise CS and MOSI for 80 clocks cycles */\n  for (counter = 0; counter <= 9; counter++) {\n    /* Send dummy byte 0xFF */\n    SD_IO_WriteByte(0xFF);\n  }\n}\n\n/**\n  * @brief Set the SD_CS pin.\n  * @param val: pin value.\n  */\nvoid\nSD_IO_CSState(uint8_t val)\n{\n  if (val == 1) {\n    SD_CS_HIGH();\n  } else {\n    SD_CS_LOW();\n  }\n}\n\n/**\n  * @brief Write a byte on the SD.\n  * @param  DataIn: value to be written\n  * @param  DataOut: value to be read\n  * @param  DataLength: length of data\n  */\nvoid\nSD_IO_WriteReadData(const uint8_t *DataIn, uint8_t *DataOut, uint16_t DataLength)\n{\n  /* Send the byte */\n  SPIx_WriteReadData(DataIn, DataOut, DataLength);\n}\n\n/**\n  * @brief  Writes a byte on the SD.\n  * @param  Data: byte to send.\n  */\nuint8_t\nSD_IO_WriteByte(uint8_t Data)\n{\n  uint8_t tmp;\n  /* Send the byte */\n  SPIx_WriteReadData(&Data, &tmp, 1);\n  return tmp;\n}\n\n#endif /* SPI_SD_ENABLED */\n\n#endif /* HAL_SPI_MODULE_ENABLED */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/dev/stm32f4xx_nucleo_sd.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_nucleo_sd.h\n  * @author  MCD Application Team\n  * @version V1.2.6\n  * @date    27-January-2017\n  * @brief   This file contains definitions for:\n  *          - MicroSD available on Adafruit MicroSD Breakout Board+ (ID 254)\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n#ifndef __STM32F4XX_NUCLEO_SD_H\n#define __STM32F4XX_NUCLEO_SD_H\n\n#include <stm32/hal/stm32f4xx_hal.h>\n#include <stm32/hal/stm32f4xx_ll_bus.h>\n#include <stm32/hal/stm32f4xx_ll_gpio.h>\n\n#ifdef HAL_SPI_MODULE_ENABLED\n\n/* Maximum Timeout values for flags waiting loops. These timeouts are not based\n   on accurate values, they just guarantee that the application will not remain\n   stuck if the SPI communication is corrupted.\n   You may modify these timeout values depending on CPU frequency and application\n   conditions (interrupts routines ...). */\n#define NUCLEO_SPIx_TIMEOUT_MAX                         1000\n\n/* To be defined only if provided with the Adafruit MicroSD Breakout Board+ */\n/* https://www.adafruit.com/product/254 */\n#ifdef SPI_SD_ENABLED                   /* Kernel Config 'options' definition. */\n\n/* SD IO functions */\nvoid              SD_IO_Init(void);\nvoid              SD_IO_CSState(uint8_t state);\nvoid              SD_IO_WriteReadData(const uint8_t *DataIn, uint8_t *DataOut, uint16_t DataLength);\nuint8_t           SD_IO_WriteByte(uint8_t Data);\n\n#endif /* SPI_SD_ENABLED */\n\n#ifdef F4DISCOVERY                      /* Kernel Config 'board' definition. */\n/* SPI2: CS PB12, SCK PB13, MISO PB14, MOSI PB15 */\n\n#define NUCLEO_SPIx                                     SPI2\n#define NUCLEO_SPIx_CLK_ENABLE()                        LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2)\n\n#define NUCLEO_SPIx_SCK_AF                              ((uint32_t)LL_GPIO_AF_5)\n#define NUCLEO_SPIx_SCK_PIN                             ((uint32_t)LL_GPIO_PIN_13)\n#define NUCLEO_SPIx_SCK_GPIO_PORT                       ((GPIO_TypeDef *)GPIOB)\n\n#define NUCLEO_SPIx_MISO_MOSI_AF                        ((uint32_t)LL_GPIO_AF_5)\n#define NUCLEO_SPIx_MISO_PIN                            ((uint32_t)LL_GPIO_PIN_14)\n#define NUCLEO_SPIx_MOSI_PIN                            ((uint32_t)LL_GPIO_PIN_15)\n#define NUCLEO_SPIx_MISO_MOSI_GPIO_PORT                 ((GPIO_TypeDef *)GPIOB)\n\n#define SD_CS_PIN                                       ((uint32_t)LL_GPIO_PIN_12)\n#define SD_CS_GPIO_PORT                                 ((GPIO_TypeDef *)GPIOB)\n\n#define SD_CS_LOW()                                     LL_GPIO_ResetOutputPin(SD_CS_GPIO_PORT, SD_CS_PIN)\n#define SD_CS_HIGH()                                    LL_GPIO_SetOutputPin(SD_CS_GPIO_PORT, SD_CS_PIN)\n\n#endif /* F4DISCOVERY */\n\n#if defined(F411RENUCLEO) || defined(F446RENUCLEO)      /* Kernel Config 'board' definition. */\n\n#define NUCLEO_SPIx                                     SPI1\n#define NUCLEO_SPIx_CLK_ENABLE()                        LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1)\n\n#define NUCLEO_SPIx_SCK_AF                              ((uint32_t)LL_GPIO_AF_5)\n#define NUCLEO_SPIx_SCK_PIN                             ((uint32_t)LL_GPIO_PIN_5)\n#define NUCLEO_SPIx_SCK_GPIO_PORT                       ((GPIO_TypeDef *)GPIOA)\n\n#define NUCLEO_SPIx_MISO_MOSI_AF                        ((uint32_t)LL_GPIO_AF_5)\n#define NUCLEO_SPIx_MISO_PIN                            ((uint32_t)LL_GPIO_PIN_6)\n#define NUCLEO_SPIx_MOSI_PIN                            ((uint32_t)LL_GPIO_PIN_7)\n#define NUCLEO_SPIx_MISO_MOSI_GPIO_PORT                 ((GPIO_TypeDef *)GPIOA)\n\n#define SD_CS_PIN                                       ((uint32_t)LL_GPIO_PIN_6)\n#define SD_CS_GPIO_PORT                                 ((GPIO_TypeDef *)GPIOB)\n\n#define SD_CS_LOW()                                     LL_GPIO_ResetOutputPin(SD_CS_GPIO_PORT, SD_CS_PIN)\n#define SD_CS_HIGH()                                    LL_GPIO_SetOutputPin(SD_CS_GPIO_PORT, SD_CS_PIN)\n\n#endif /* F411RENUCLEO || F446RENUCLEO */\n\n#ifdef F469IDISCO                       /* Kernel Config 'board' definition. */\n\n#define NUCLEO_SPIx                                     SPI2\n#define NUCLEO_SPIx_CLK_ENABLE()                        LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2)\n\n#define NUCLEO_SPIx_SCK_AF                              ((uint32_t)LL_GPIO_AF_5)\n#define NUCLEO_SPIx_SCK_PIN                             ((uint32_t)LL_GPIO_PIN_3)\n#define NUCLEO_SPIx_SCK_GPIO_PORT                       ((GPIO_TypeDef *)GPIOD)\n\n#define NUCLEO_SPIx_MISO_MOSI_AF                        ((uint32_t)LL_GPIO_AF_5)\n#define NUCLEO_SPIx_MISO_PIN                            ((uint32_t)LL_GPIO_PIN_14)\n#define NUCLEO_SPIx_MOSI_PIN                            ((uint32_t)LL_GPIO_PIN_15)\n#define NUCLEO_SPIx_MISO_MOSI_GPIO_PORT                 ((GPIO_TypeDef *)GPIOB)\n\n#define SD_CS_PIN                                       ((uint32_t)LL_GPIO_PIN_6)\n#define SD_CS_GPIO_PORT                                 ((GPIO_TypeDef *)GPIOH)\n\n#define SD_CS_LOW()                                     LL_GPIO_ResetOutputPin(SD_CS_GPIO_PORT, SD_CS_PIN)\n#define SD_CS_HIGH()                                    LL_GPIO_SetOutputPin(SD_CS_GPIO_PORT, SD_CS_PIN)\n\n#endif /* F469IDISCO */\n\n#endif /* HAL_SPI_MODULE_ENABLED */\n\n#endif /* __STM32F4XX_NUCLEO_SD_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/dev/uart.c",
    "content": "/*\n * UART driver for STM32.\n *\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)cons.c\t1.3 (2.11BSD GTE) 1997/4/25\n */\n\n#include <sys/param.h>\n#include <sys/conf.h>\n#include <sys/user.h>\n#include <sys/ioctl.h>\n#include <sys/tty.h>\n#include <sys/systm.h>\n#include <sys/config.h>\n\n#include <stm32/dev/uart.h>\n\n#include <stm32/hal/stm32f4xx_ll_bus.h>\n#include <stm32/hal/stm32f4xx_ll_gpio.h>\n#include <stm32/hal/stm32f4xx_ll_usart.h>\n\n#define CONCAT(x,y) x ## y\n#define BBAUD(x) CONCAT(B,x)\n\n#ifndef UART_BAUD\n#define UART_BAUD 115200\n#endif\n\n/*\n * STM32 USART/UART port.\n */\nstruct uart_port {\n    GPIO_TypeDef        *port;\n    char                 port_name;\n    u_long               pin;\n};\n\n/*\n * STM32 USART/UART instance.\n */\nstruct uart_inst {\n    USART_TypeDef       *inst;\n    struct               uart_port tx;\n    struct               uart_port rx;\n    u_int                apb_div;\n    u_int                af;\n};\n\n/*\n * STM32 USART/UART.\n */\nstatic const struct uart_inst uart[NUART] = {\n#define PIN0             LL_GPIO_PIN_0\n#define PIN2             LL_GPIO_PIN_2\n#define PIN3             LL_GPIO_PIN_3\n#define PIN6             LL_GPIO_PIN_6\n#define PIN7             LL_GPIO_PIN_7\n#define PIN9             LL_GPIO_PIN_9\n#define PIN10            LL_GPIO_PIN_10\n#define PIN11            LL_GPIO_PIN_11\n#define PIN14            LL_GPIO_PIN_14\n#define AF7              LL_GPIO_AF_7\n#define AF8              LL_GPIO_AF_8\n#ifdef STM32F405xx\n    { USART1, { GPIOA, 'A', PIN9 }, { GPIOA, 'A', PIN10 }, 2, AF7 },\n    { USART2, { GPIOA, 'A', PIN2 }, { GPIOA, 'A', PIN3 }, 4, AF7 },\n    { /* USART3 */ },\n    { /* UART4 */ },\n    { /* UART5 */ },\n    { /* USART6 */ },\n#endif\n#ifdef STM32F407xx\n    { USART1, { GPIOA, 'A', PIN9 }, { GPIOA, 'A', PIN10 }, 2, AF7 },\n    { USART2, { GPIOA, 'A', PIN2 }, { GPIOA, 'A', PIN3 }, 4, AF7 },\n    { /* USART3 */ },\n    { /* UART4 */ },\n    { /* UART5 */ },\n    { /* USART6 */ },\n#endif\n#ifdef STM32F411xE\n    { /* USART1 */ },\n    { USART2, { GPIOA, 'A', PIN2 }, { GPIOA, 'A', PIN3 }, 2, AF7 },\n    { /* none */ },\n    { /* none */ },\n    { /* none */ },\n    { /* USART6 */ },\n#endif\n#ifdef STM32F412Rx\n    { USART1, { GPIOA, 'A', PIN9 }, { GPIOA, 'A', PIN10 }, 2, AF7 },\n    { /* USART2 */ },\n    { /* USART3 */ },\n    { /* none */ },\n    { /* none */ },\n    { /* USART6 */ },\n#endif\n#ifdef STM32F412Zx\n    { /* USART1 */ },\n    { USART2, { GPIOA, 'A', PIN2 }, { GPIOA, 'A', PIN3 }, 2, AF7 },\n    { /* USART3 */ },\n    { /* none */ },\n    { /* none */ },\n    { USART6, { GPIOG, 'G', PIN14 }, { GPIOG, 'G', PIN9 }, 1, AF8 },\n#endif\n#ifdef STM32F413xx\n    { /* USART1 */ },\n    { /* USART2 */ },\n    { /* USART3 */ },\n    { /* UART4 */ },\n    { /* UART5 */ },\n    { USART6, { GPIOG, 'G', PIN14 }, { GPIOG, 'G', PIN9 }, 1, AF8 },\n#endif\n#ifdef STM32F446xx\n    { USART1, { GPIOA, 'A', PIN9 }, { GPIOA, 'A', PIN10 }, 2, AF7 },\n    { USART2, { GPIOA, 'A', PIN2 }, { GPIOA, 'A', PIN3 }, 2, AF7 },\n    { /* USART3 */ },\n    { /* UART4 */ },\n    { /* UART5 */ },\n    { /* USART6 */ },\n#endif\n#ifdef STM32F469xx\n    { /* USART1 */ },\n    { /* USART2 */ },\n    { USART3, { GPIOB, 'B', PIN10 }, { GPIOB, 'B', PIN11 }, 2, AF7 },\n    { /* UART4 */ },\n    { /* UART5 */ },\n    { USART6, { GPIOC, 'C', PIN6  }, { GPIOC, 'C', PIN7  }, 2, AF8 },\n#endif\n};\n\nstruct tty uartttys[NUART];\n\n#if 0 // XXX UART\nstatic unsigned speed_bps [NSPEEDS] = {\n    0,       50,      75,      150,     200,    300,     600,     1200,\n    1800,    2400,    4800,    9600,    19200,  38400,   57600,   115200,\n    230400,  460800,  500000,  576000,  921600, 1000000, 1152000, 1500000,\n    2000000, 2500000, 3000000, 3500000, 4000000\n};\n#endif // XXX UART\n\nvoid cnstart(struct tty *tp);\n\nvoid\nUSART1_IRQHandler(void)\n{\n    uartintr(makedev(UART_MAJOR, 0));   /* USART1 */\n}\n\nvoid\nUSART2_IRQHandler(void)\n{\n    uartintr(makedev(UART_MAJOR, 1));   /* USART2 */\n}\n\nvoid\nUSART3_IRQHandler(void)\n{\n    uartintr(makedev(UART_MAJOR, 2));   /* USART3 */\n}\n\nvoid\nUART4_IRQHandler(void)\n{\n    uartintr(makedev(UART_MAJOR, 3));   /* UART4 */\n}\n\nvoid\nUART5_IRQHandler(void)\n{\n    uartintr(makedev(UART_MAJOR, 4));   /* UART5 */\n}\n\nvoid\nUSART6_IRQHandler(void)\n{\n    uartintr(makedev(UART_MAJOR, 5));   /* USART6 */\n}\n\n/*\n * Setup USART/UART.\n */\nvoid\nuartinit(int unit)\n{\n    register USART_TypeDef      *inst;\n    register GPIO_TypeDef       *tx_port;\n    register u_int               tx_pin;\n    register GPIO_TypeDef       *rx_port;\n    register u_int               rx_pin;\n    register u_int               apb_div;\n    register u_int               af;\n\n    if (unit < 0 || unit >= NUART)\n        return;\n\n    inst    = uart[unit].inst;\n    tx_port = uart[unit].tx.port;\n    tx_pin  = uart[unit].tx.pin;\n    rx_port = uart[unit].rx.port;\n    rx_pin  = uart[unit].rx.pin;\n    apb_div = uart[unit].apb_div;\n    af      = uart[unit].af;\n\n    /*\n     * Configure and enable USART/UART NVIC interrupts.\n     * Enable GPIO port peripheral clock and USART/UART peripheral clock.\n     */\n    switch (unit) {\n    case 0:     /* USART1 */\n#ifdef USART1\n        arm_intr_set_priority(USART1_IRQn, IPL_TTY);\n        arm_intr_enable_irq(USART1_IRQn);\n\n#ifdef STM32F405xx\n        /* USART1: APB2 84 MHz AF7: TX on PA.09, RX on PA.10 */\n        LL_GPIO_EnableClock(GPIOA);\n        LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1);\n#endif\n#ifdef STM32F407xx\n        /* USART1: APB2 84 MHz AF7: TX on PA.09, RX on PA.10 */\n        LL_GPIO_EnableClock(GPIOA);\n        LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1);\n#endif\n#ifdef STM32F412Rx\n        /* USART1: APB2 100 MHz AF7: TX on PA.09, RX on PA.10 */\n        LL_GPIO_EnableClock(GPIOA);\n        LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1);\n#endif\n#ifdef STM32F446xx\n        /* USART1: APB2 90 MHz AF7: TX on PA.09, RX on PA.10 */\n        LL_GPIO_EnableClock(GPIOA);\n        LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1);\n#endif\n\n#endif /* USART1 */\n        break;\n\n    case 1:     /* USART2 */\n#ifdef USART2\n        arm_intr_set_priority(USART2_IRQn, IPL_TTY);\n        arm_intr_enable_irq(USART2_IRQn);\n\n#ifdef STM32F405xx\n        /* USART2: APB1 42 MHz AF7: TX on PA.02, RX on PA.03 */\n        LL_GPIO_EnableClock(GPIOA);\n        LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2);\n#endif\n#ifdef STM32F407xx\n        /* USART2: APB1 42 MHz AF7: TX on PA.02, RX on PA.03 */\n        LL_GPIO_EnableClock(GPIOA);\n        LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2);\n#endif\n#ifdef STM32F411xE\n        /* USART2: APB1 50 MHz AF7: TX on PA.02, RX on PA.03 */\n        LL_GPIO_EnableClock(GPIOA);\n        LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2);\n#endif\n#ifdef STM32F412Zx\n        /* USART2: APB1 50 MHz AF7: TX on PA.02, RX on PA.03 */\n        LL_GPIO_EnableClock(GPIOA);\n        LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2);\n#endif\n#ifdef STM32F446xx\n        /* USART2: APB1 45 MHz AF7: TX on PA.02, RX on PA.03 */\n        LL_GPIO_EnableClock(GPIOA);\n        LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2);\n#endif\n\n#endif /* USART2 */\n        break;\n\n    case 2:     /* USART3 */\n#ifdef USART3\n        arm_intr_set_priority(USART3_IRQn, IPL_TTY);\n        arm_intr_enable_irq(USART3_IRQn);\n\n#ifdef STM32F469xx\n        /* USART3: AHB1/APB1, 45 MHz, AF7, TX on PB.10, RX on PB.11 */\n        LL_GPIO_EnableClock(GPIOB);\n        LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART3);\n#endif\n\n#endif /* USART3 */\n        break;\n\n    case 3:     /* UART4 */\n#ifdef UART4\n        arm_intr_set_priority(UART4_IRQn, IPL_TTY);\n        arm_intr_enable_irq(UART4_IRQn);\n#endif /* UART4 */\n        break;\n\n    case 4:     /* UART5 */\n#ifdef UART5\n        arm_intr_set_priority(UART5_IRQn, IPL_TTY);\n        arm_intr_enable_irq(UART5_IRQn);\n#endif /* UART5 */\n        break;\n\n    case 5:     /* USART6 */\n#ifdef USART6\n        arm_intr_set_priority(USART6_IRQn, IPL_TTY);\n        arm_intr_enable_irq(USART6_IRQn);\n\n#ifdef STM32F412Zx\n        /* USART6: AHB1/APB2, 100 MHz AF8: TX on PG.14, RX on PG.09 */\n        LL_GPIO_EnableClock(GPIOG);\n        LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART6);\n#endif\n#ifdef STM32F413xx\n        /* USART6: AHB1/APB2, 100 MHz, AF8, TX on PG.14, RX on PG.09 */\n        LL_GPIO_EnableClock(GPIOG);\n        LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART6);\n#endif\n#ifdef STM32F469xx\n        /* USART6: AHB1/APB2, 90 MHz, AF8, TX on PC.06, RX on PC.07 */\n        /* USART6: CN12 Ext: 3V3 Pin 1, GND Pin 2, TX Pin 6, RX Pin 8 */\n        LL_GPIO_EnableClock(GPIOC);\n        LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART6);\n#endif\n\n#endif /* USART6 */\n        break;\n\n    default:\n        break;\n    }\n\n    /* Config Tx Pin as: Alt func, High Speed, Push pull, Pull up */\n    LL_GPIO_SetPinMode(tx_port, tx_pin, LL_GPIO_MODE_ALTERNATE);\n    LL_GPIO_SetAFPin(tx_port, tx_pin, af);\n    LL_GPIO_SetPinSpeed(tx_port, tx_pin, LL_GPIO_SPEED_FREQ_HIGH);\n    LL_GPIO_SetPinOutputType(tx_port, tx_pin, LL_GPIO_OUTPUT_PUSHPULL);\n    LL_GPIO_SetPinPull(tx_port, tx_pin, LL_GPIO_PULL_UP);\n\n    /* Config Rx Pin as: Alt func, High Speed, Push pull, Pull up */\n    LL_GPIO_SetPinMode(rx_port, rx_pin, LL_GPIO_MODE_ALTERNATE);\n    LL_GPIO_SetAFPin(rx_port, rx_pin, af);\n    LL_GPIO_SetPinSpeed(rx_port, rx_pin, LL_GPIO_SPEED_FREQ_HIGH);\n    LL_GPIO_SetPinOutputType(rx_port, rx_pin, LL_GPIO_OUTPUT_PUSHPULL);\n    LL_GPIO_SetPinPull(rx_port, rx_pin, LL_GPIO_PULL_UP);\n\n    /* Transmit/Receive, 8 data bit, 1 start bit, 1 stop bit, no parity. */\n    LL_USART_Disable(inst);\n    LL_USART_SetTransferDirection(inst, LL_USART_DIRECTION_TX_RX);\n    LL_USART_ConfigCharacter(inst,\n        LL_USART_DATAWIDTH_8B, LL_USART_PARITY_NONE, LL_USART_STOPBITS_1);\n    LL_USART_SetBaudRate(inst,\n        SystemCoreClock/apb_div, LL_USART_OVERSAMPLING_16, UART_BAUD);\n    LL_USART_Enable(inst);\n}\n\nint\nuartopen(dev_t dev, int flag, int mode)\n{\n    register struct uart_inst *uip;\n    register struct tty *tp;\n    register int unit = minor(dev);\n\n    if (unit < 0 || unit >= NUART)\n        return (ENXIO);\n\n    tp = &uartttys[unit];\n    if (! tp->t_addr)\n        return (ENXIO);\n\n    uip = (struct uart_inst *)tp->t_addr;\n    tp->t_oproc = uartstart;\n    if ((tp->t_state & TS_ISOPEN) == 0) {\n        if (tp->t_ispeed == 0) {\n            tp->t_ispeed = BBAUD(UART_BAUD);\n            tp->t_ospeed = BBAUD(UART_BAUD);\n        }\n        ttychars(tp);\n        tp->t_state = TS_ISOPEN | TS_CARR_ON;\n        tp->t_flags = ECHO | XTABS | CRMOD | CRTBS | CRTERA | CTLECH | CRTKIL;\n    }\n    if ((tp->t_state & TS_XCLUDE) && u.u_uid != 0)\n        return (EBUSY);\n\n    // XXX Clear USART state, then set up new state.\n    LL_USART_Enable(uip->inst);\n    LL_USART_EnableDirectionRx(uip->inst);\n    LL_USART_EnableDirectionTx(uip->inst);\n#if 0 // XXX\n    reg->sta = 0;\n    reg->brg = PIC32_BRG_BAUD (BUS_KHZ * 1000, speed_bps [tp->t_ospeed]);\n    reg->mode = PIC32_UMODE_PDSEL_8NPAR |\n                PIC32_UMODE_ON;\n    reg->staset = PIC32_USTA_URXEN | PIC32_USTA_UTXEN;\n#endif // XXX\n\n    /* Enable receive interrupt. */\n    LL_USART_EnableIT_RXNE(uip->inst);\n\n    return ttyopen(dev, tp);\n}\n\n/*ARGSUSED*/\nint\nuartclose(dev_t dev, int flag, int mode)\n{\n    register int unit = minor(dev);\n    register struct tty *tp = &uartttys[unit];\n\n    if (! tp->t_addr)\n        return ENODEV;\n\n    ttywflush(tp);\n    ttyclose(tp);\n    return(0);\n}\n\n/*ARGSUSED*/\nint\nuartread(dev_t dev, struct uio *uio, int flag)\n{\n    register int unit = minor(dev);\n    register struct tty *tp = &uartttys[unit];\n\n    if (! tp->t_addr)\n        return ENODEV;\n\n    return ttread(tp, uio, flag);\n}\n\n/*ARGSUSED*/\nint\nuartwrite(dev_t dev, struct uio *uio, int flag)\n{\n    register int unit = minor(dev);\n    register struct tty *tp = &uartttys[unit];\n\n    if (! tp->t_addr)\n        return ENODEV;\n\n    return ttwrite(tp, uio, flag);\n}\n\nint\nuartselect(dev_t dev, int rw)\n{\n    register int unit = minor(dev);\n    register struct tty *tp = &uartttys[unit];\n\n    if (! tp->t_addr)\n        return ENODEV;\n\n    return (ttyselect (tp, rw));\n}\n\n/*ARGSUSED*/\nint\nuartioctl(dev_t dev, u_int cmd, caddr_t addr, int flag)\n{\n    register int unit = minor(dev);\n    register struct tty *tp = &uartttys[unit];\n    register int error;\n\n    if (! tp->t_addr)\n        return ENODEV;\n\n    error = ttioctl(tp, cmd, addr, flag);\n    if (error < 0)\n        error = ENOTTY;\n    return (error);\n}\n\nvoid\nuartintr(dev_t dev)\n{\n    register int c;\n    register int unit = minor(dev);\n    register struct tty *tp = &uartttys[unit];\n    register struct uart_inst *uip;\n\n    if (! tp->t_addr)\n        return;\n\n    uip = (struct uart_inst *)tp->t_addr;\n\n    /* Receive */\n    while (LL_USART_IsActiveFlag_RXNE(uip->inst)) {\n        c = LL_USART_ReceiveData8(uip->inst);\n        ttyinput(c, tp);\n    }\n\n#if 0 // XXX\n    /* XXX Receive Buffer Overrun */\n    if (reg->sta & PIC32_USTA_OERR)\n        reg->staclr = PIC32_USTA_OERR;\n#endif // XXX\n\n    /* RXNE flag was cleared by reading DR register */\n\n    /* Transmit */\n    if (LL_USART_IsActiveFlag_TXE(uip->inst)) {\n        led_control(LED_TTY, 0);\n\n        /* Disable transmit interrupt. */\n        LL_USART_DisableIT_TXE(uip->inst);\n\n        if (tp->t_state & TS_BUSY) {\n            tp->t_state &= ~TS_BUSY;\n            ttstart(tp);\n        }\n    }\n}\n\n/*\n * Start (restart) transmission on the given line.\n */\nvoid\nuartstart(struct tty *tp)\n{\n    register struct uart_inst *uip;\n    register int c, s;\n\n    if (! tp->t_addr)\n        return;\n\n    uip = (struct uart_inst *)tp->t_addr;\n\n    /*\n     * Must hold interrupts in following code to prevent\n     * state of the tp from changing.\n     */\n    s = spltty();\n    /*\n     * If it is currently active, or delaying, no need to do anything.\n     */\n    if (tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) {\nout:\n        led_control(LED_TTY, 0);\n        splx(s);\n        return;\n    }\n\n    /*\n     * Wake up any sleepers.\n     */\n    ttyowake(tp);\n\n    /*\n     * Now restart transmission unless the output queue is empty.\n     */\n    if (tp->t_outq.c_cc == 0)\n        goto out;\n\n    if (LL_USART_IsActiveFlag_TXE(uip->inst)) {\n        c = getc(&tp->t_outq);\n        LL_USART_TransmitData8(uip->inst, c & 0xff);\n        tp->t_state |= TS_BUSY;\n    }\n\n    /* Enable transmit interrupt. */\n    LL_USART_EnableIT_TXE(uip->inst);\n\n    led_control(LED_TTY, 1);\n    splx(s);\n}\n\nvoid\nuartputc(dev_t dev, char c)\n{\n    int unit = minor(dev);\n    struct tty *tp = &uartttys[unit];\n    register const struct uart_inst *uip = &uart[unit];\n    register int s, timo;\n\n    s = spltty();\nagain:\n    /*\n     * Try waiting for the console tty to come ready,\n     * otherwise give up after a reasonable time.\n     */\n    timo = 30000;\n    while (!LL_USART_IsActiveFlag_TXE(uip->inst))\n        if (--timo == 0)\n            break;\n\n    if (tp->t_state & TS_BUSY) {\n        uartintr(dev);\n        goto again;\n    }\n    led_control(LED_TTY, 1);\n    LL_USART_ClearFlag_TC(uip->inst);\n    LL_USART_TransmitData8(uip->inst, c);\n\n    timo = 30000;\n    while (!LL_USART_IsActiveFlag_TC(uip->inst))\n        if (--timo == 0)\n            break;\n\n    led_control(LED_TTY, 0);\n    splx(s);\n}\n\nchar\nuartgetc(dev_t dev)\n{\n    int unit = minor(dev);\n    register const struct uart_inst *uip = &uart[unit];\n    int s, c;\n\n    s = spltty();\n    for (;;) {\n        /* Wait for key pressed. */\n        if (LL_USART_IsActiveFlag_RXNE(uip->inst)) {\n            c = LL_USART_ReceiveData8(uip->inst);\n            break;\n        }\n    }\n\n    /* RXNE flag was cleared by reading DR register */\n\n    splx(s);\n    return (unsigned char) c;\n}\n\n/*\n * Test to see if device is present.\n * Return true if found and initialized ok.\n */\nstatic int\nuartprobe(struct conf_device *config)\n{\n    int unit = config->dev_unit - 1;\n    int is_console = (CONS_MAJOR == UART_MAJOR &&\n                      CONS_MINOR == unit);\n\n    if (unit < 0 || unit >= NUART)\n        return 0;\n\n    printf(\"uart%d: pins tx=P%c%d/rx=P%c%d, af=%d\", unit+1,\n        uart[unit].tx.port_name, ffs(uart[unit].tx.pin)-1,\n        uart[unit].rx.port_name, ffs(uart[unit].rx.pin)-1,\n        uart[unit].af);\n\n    if (is_console)\n        printf(\", console\");\n    printf(\"\\n\");\n\n    /* Initialize the device. */\n    uartttys[unit].t_addr = (caddr_t) &uart[unit];\n    if (! is_console)\n        uartinit(unit);\n\n    return 1;\n}\n\nstruct driver uartdriver = {\n    \"uart\", uartprobe,\n};\n"
  },
  {
    "path": "sys/arch/stm32/dev/uart.h",
    "content": "#ifndef _UART_H\n#define _UART_H\n\n#define NUART   6\n\n#ifdef KERNEL\n\nvoid            uartinit(int unit);\nint             uartopen(dev_t dev, int flag, int mode);\nint             uartclose(dev_t dev, int flag, int mode);\nint             uartread(dev_t dev, struct uio *uio, int flag);\nint             uartwrite(dev_t dev, struct uio *uio, int flag);\nint             uartselect(dev_t dev, int rw);\nint             uartioctl(dev_t dev, u_int cmd, caddr_t addr, int flag);\nvoid            uartintr(dev_t dev);\nvoid            uartstart(struct tty *tp);\nvoid            uartputc(dev_t dev, char c);\nchar            uartgetc(dev_t dev);\n\nextern struct   tty uartttys[NUART];\n\n#endif /* KERNEL */\n\n#endif /* !_UART_H */\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32_assert.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32_assert.h\n  * @author  MCD Application Team\n  * @version V1.0.0\n  * @date    17-February-2017\n  * @brief   STM32 assert template file.\n  *          This file should be copied to the application folder and renamed\n  *          to stm32_assert.h.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32_ASSERT_H\n#define __STM32_ASSERT_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/* Includes ------------------------------------------------------------------*/\n/* Exported macro ------------------------------------------------------------*/\n#ifdef  USE_FULL_ASSERT\n/**\n  * @brief  The assert_param macro is used for function's parameters check.\n  * @param  expr: If expr is false, it calls assert_failed function\n  *         which reports the name of the source file and the source\n  *         line number of the call that failed.\n  *         If expr is true, it returns no value.\n  * @retval None\n  */\n  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))\n/* Exported functions ------------------------------------------------------- */\n  void assert_failed(uint8_t* file, uint32_t line);\n#else\n  #define assert_param(expr) ((void)0U)\n#endif /* USE_FULL_ASSERT */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32_ASSERT_H */\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f405xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f405xx.h\n  * @author  MCD Application Team\n  * @version V2.6.4\n  * @date    06-December-2019\n  * @brief   CMSIS STM32F405xx Device Peripheral Access Layer Header File.\n  *\n  *          This file contains:\n  *           - Data structures and the address mapping for all peripherals\n  *           - peripherals registers declarations and bits definition\n  *           - Macros to access peripheral's registers hardware\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS_Device\n  * @{\n  */\n\n/** @addtogroup stm32f405xx\n  * @{\n  */\n\n#ifndef __STM32F405xx_H\n#define __STM32F405xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Configuration_section_for_CMSIS\n  * @{\n  */\n\n/**\n  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals\n  */\n#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */\n#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */\n#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */\n#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */\n#define __FPU_PRESENT             1U       /*!< FPU present                                   */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_interrupt_number_definition\n  * @{\n  */\n\n/**\n * @brief STM32F4XX Interrupt Number Definition, according to the selected device\n *        in @ref Library_configuration_section\n */\ntypedef enum\n{\n/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */\n  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */\n  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */\n  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */\n  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */\n  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */\n/******  STM32 specific Interrupt Numbers **********************************************************************/\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */\n  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */\n  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\n  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\n  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\n  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\n  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\n  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\n  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\n  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\n  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\n  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */\n  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */\n  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */\n  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */\n  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */\n  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */\n  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */\n  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */\n  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */\n  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */\n  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */\n  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\n  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */\n  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */\n  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\n  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\n  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */\n  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */\n  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */\n  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\n  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */\n  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */\n  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */\n  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\n  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */\n  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */\n  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */\n  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */\n  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */\n  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */\n  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */\n  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */\n  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */\n  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */\n  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */\n  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */\n  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */\n  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */\n  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */\n  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */\n  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */\n  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */\n  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\n  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\n  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */\n  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */\n  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */\n  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */\n  RNG_IRQn                    = 80,     /*!< RNG global Interrupt                                              */\n  FPU_IRQn                    = 81      /*!< FPU global interrupt                                               */\n} IRQn_Type;\n/* Legacy define */\n#define  HASH_RNG_IRQn      RNG_IRQn\n\n/**\n  * @}\n  */\n\n#include \"core_cm4.h\"             /* Cortex-M4 processor and core peripherals */\n#include \"system_stm32f4xx.h\"\n#include <sys/stdint.h>\n\n/** @addtogroup Peripheral_registers_structures\n  * @{\n  */\n\n/**\n  * @brief Analog to Digital Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */\n  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */\n  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */\n  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */\n  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */\n  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\n  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\n  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\n  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\n  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */\n  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */\n  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */\n  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */\n  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */\n  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/\n  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */\n  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */\n  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */\n  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */\n  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */\n} ADC_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */\n  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */\n  __IO uint32_t CDR;    /*!< ADC common regular data register for dual\n                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */\n} ADC_Common_TypeDef;\n\n\n/**\n  * @brief Controller Area Network TxMailBox\n  */\n\ntypedef struct\n{\n  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */\n  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\n  __IO uint32_t TDLR; /*!< CAN mailbox data low register */\n  __IO uint32_t TDHR; /*!< CAN mailbox data high register */\n} CAN_TxMailBox_TypeDef;\n\n/**\n  * @brief Controller Area Network FIFOMailBox\n  */\n\ntypedef struct\n{\n  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */\n  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\n  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\n  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\n} CAN_FIFOMailBox_TypeDef;\n\n/**\n  * @brief Controller Area Network FilterRegister\n  */\n\ntypedef struct\n{\n  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\n  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\n} CAN_FilterRegister_TypeDef;\n\n/**\n  * @brief Controller Area Network\n  */\n\ntypedef struct\n{\n  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */\n  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */\n  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */\n  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */\n  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */\n  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */\n  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */\n  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */\n  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */\n  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */\n  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */\n  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */\n  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */\n  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */\n  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */\n  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */\n  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */\n  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */\n  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */\n  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */\n  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */\n  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */\n} CAN_TypeDef;\n\n/**\n  * @brief CRC calculation unit\n  */\n\ntypedef struct\n{\n  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */\n  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */\n  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */\n  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */\n  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */\n} CRC_TypeDef;\n\n/**\n  * @brief Digital to Analog Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */\n  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */\n  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\n  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */\n  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */\n  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\n  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */\n  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */\n  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */\n  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */\n  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */\n  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */\n  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */\n  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */\n} DAC_TypeDef;\n\n/**\n  * @brief Debug MCU\n  */\n\ntypedef struct\n{\n  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */\n  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */\n  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */\n  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */\n}DBGMCU_TypeDef;\n\n\n/**\n  * @brief DMA Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;     /*!< DMA stream x configuration register      */\n  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */\n  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */\n  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */\n  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */\n  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */\n} DMA_Stream_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */\n  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */\n  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */\n  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\n} DMA_TypeDef;\n\n/**\n  * @brief External Interrupt/Event Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */\n  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */\n  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */\n  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\n  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */\n  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */\n} EXTI_TypeDef;\n\n/**\n  * @brief FLASH Registers\n  */\n\ntypedef struct\n{\n  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */\n  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */\n  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */\n  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */\n  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */\n  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */\n  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */\n} FLASH_TypeDef;\n\n\n\n/**\n  * @brief Flexible Static Memory Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\n} FSMC_Bank1_TypeDef;\n\n/**\n  * @brief Flexible Static Memory Controller Bank1E\n  */\n\ntypedef struct\n{\n  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\n} FSMC_Bank1E_TypeDef;\n\n/**\n  * @brief Flexible Static Memory Controller Bank2\n  */\n\ntypedef struct\n{\n  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */\n  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */\n  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */\n  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */\n  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */\n  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */\n  uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */\n  uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */\n  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */\n  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */\n  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */\n  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */\n  uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */\n  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */\n} FSMC_Bank2_3_TypeDef;\n\n/**\n  * @brief Flexible Static Memory Controller Bank4\n  */\n\ntypedef struct\n{\n  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */\n  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */\n  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */\n  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */\n  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */\n} FSMC_Bank4_TypeDef;\n\n/**\n  * @brief General Purpose I/O\n  */\n\ntypedef struct\n{\n  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */\n  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */\n  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */\n  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\n  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */\n  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */\n  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */\n  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */\n  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\n} GPIO_TypeDef;\n\n/**\n  * @brief System configuration controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */\n  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */\n  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\n  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */\n  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */\n} SYSCFG_TypeDef;\n\n/**\n  * @brief Inter-integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */\n  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */\n  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */\n  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */\n  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */\n  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */\n  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */\n  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */\n} I2C_TypeDef;\n\n/**\n  * @brief Independent WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */\n  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */\n  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */\n  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */\n} IWDG_TypeDef;\n\n\n/**\n  * @brief Power Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */\n  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */\n} PWR_TypeDef;\n\n/**\n  * @brief Reset and Clock Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */\n  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */\n  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */\n  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */\n  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */\n  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */\n  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */\n  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */\n  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */\n  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */\n  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */\n  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */\n  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */\n  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */\n  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */\n  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */\n  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */\n  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\n  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\n  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\n  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */\n  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\n  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\n  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */\n  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */\n  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */\n  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */\n  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */\n  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */\n} RCC_TypeDef;\n\n/**\n  * @brief Real-Time Clock\n  */\n\ntypedef struct\n{\n  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */\n  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */\n  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */\n  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */\n  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */\n  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */\n  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */\n  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */\n  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */\n  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */\n  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */\n  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */\n  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */\n  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */\n  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */\n  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */\n  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */\n  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */\n  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */\n  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */\n  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */\n  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */\n  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */\n  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */\n  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */\n  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */\n  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */\n  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */\n  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */\n  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */\n  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */\n  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */\n  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */\n  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */\n  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */\n  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */\n  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */\n  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */\n  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */\n  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */\n} RTC_TypeDef;\n\n/**\n  * @brief SD host Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t POWER;                 /*!< SDIO power control register,    Address offset: 0x00 */\n  __IO uint32_t CLKCR;                 /*!< SDI clock control register,     Address offset: 0x04 */\n  __IO uint32_t ARG;                   /*!< SDIO argument register,         Address offset: 0x08 */\n  __IO uint32_t CMD;                   /*!< SDIO command register,          Address offset: 0x0C */\n  __IO const uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */\n  __IO const uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */\n  __IO const uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */\n  __IO const uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */\n  __IO const uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */\n  __IO uint32_t DTIMER;                /*!< SDIO data timer register,       Address offset: 0x24 */\n  __IO uint32_t DLEN;                  /*!< SDIO data length register,      Address offset: 0x28 */\n  __IO uint32_t DCTRL;                 /*!< SDIO data control register,     Address offset: 0x2C */\n  __IO const uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */\n  __IO const uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */\n  __IO uint32_t ICR;                   /*!< SDIO interrupt clear register,  Address offset: 0x38 */\n  __IO uint32_t MASK;                  /*!< SDIO mask register,             Address offset: 0x3C */\n  uint32_t      RESERVED0[2];          /*!< Reserved, 0x40-0x44                                  */\n  __IO const uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */\n  uint32_t      RESERVED1[13];         /*!< Reserved, 0x4C-0x7C                                  */\n  __IO uint32_t FIFO;                  /*!< SDIO data FIFO register,        Address offset: 0x80 */\n} SDIO_TypeDef;\n\n/**\n  * @brief Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */\n  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */\n  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */\n  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\n  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */\n  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */\n  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */\n  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */\n} SPI_TypeDef;\n\n\n/**\n  * @brief TIM\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */\n  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */\n  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */\n  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */\n  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */\n  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\n  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\n  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */\n  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */\n  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */\n  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */\n  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */\n  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */\n  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */\n  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */\n  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */\n  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */\n  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */\n  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */\n  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */\n} TIM_TypeDef;\n\n/**\n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */\n  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */\n  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */\n  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */\n  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */\n  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */\n  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */\n} USART_TypeDef;\n\n/**\n  * @brief Window WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */\n  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */\n  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */\n} WWDG_TypeDef;\n\n/**\n  * @brief RNG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */\n  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */\n  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */\n} RNG_TypeDef;\n\n/**\n  * @brief USB_OTG_Core_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */\n  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */\n  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */\n  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */\n  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */\n  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */\n  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */\n  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */\n  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */\n  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */\n  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */\n  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */\n  uint32_t Reserved30[2];             /*!< Reserved                                     030h */\n  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */\n  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */\n  uint32_t  Reserved40[48];           /*!< Reserved                                0x40-0xFF */\n  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */\n  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                        */\n} USB_OTG_GlobalTypeDef;\n\n/**\n  * @brief USB_OTG_device_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */\n  __IO uint32_t DCTL;            /*!< dev Control Register         804h */\n  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */\n  uint32_t Reserved0C;           /*!< Reserved                     80Ch */\n  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */\n  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */\n  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */\n  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */\n  uint32_t  Reserved20;          /*!< Reserved                     820h */\n  uint32_t Reserved9;            /*!< Reserved                     824h */\n  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */\n  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */\n  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */\n  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */\n  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */\n  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */\n  uint32_t Reserved40;           /*!< dedicated EP mask            840h */\n  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */\n  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */\n  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */\n} USB_OTG_DeviceTypeDef;\n\n/**\n  * @brief USB_OTG_IN_Endpoint-Specific_Register\n  */\ntypedef struct\n{\n  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */\n  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */\n  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */\n  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\n  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\n} USB_OTG_INEndpointTypeDef;\n\n/**\n  * @brief USB_OTG_OUT_Endpoint-Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */\n  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */\n  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */\n  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\n} USB_OTG_OUTEndpointTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Mode_Register_Structures\n  */\ntypedef struct\n{\n  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */\n  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */\n  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */\n  uint32_t Reserved40C;           /*!< Reserved                             40Ch */\n  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */\n  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */\n  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */\n} USB_OTG_HostTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Channel_Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */\n  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */\n  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */\n  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */\n  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */\n  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */\n  uint32_t Reserved[2];           /*!< Reserved                                      */\n} USB_OTG_HostChannelTypeDef;\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_memory_map\n  * @{\n  */\n#define FLASH_BASE            0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region                         */\n#define CCMDATARAM_BASE       0x10000000UL /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */\n#define SRAM1_BASE            0x20000000UL /*!< SRAM1(112 KB) base address in the alias region                              */\n#define SRAM2_BASE            0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region                              */\n#define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */\n#define BKPSRAM_BASE          0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region                         */\n#define FSMC_R_BASE           0xA0000000UL /*!< FSMC registers base address                                                */\n#define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region                          */\n#define SRAM2_BB_BASE         0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region                           */\n#define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */\n#define BKPSRAM_BB_BASE       0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region                      */\n#define FLASH_END             0x080FFFFFUL /*!< FLASH end address                                                          */\n#define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */\n#define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */\n#define CCMDATARAM_END        0x1000FFFFUL /*!< CCM data RAM end address                                                   */\n\n/* Legacy defines */\n#define SRAM_BASE             SRAM1_BASE\n#define SRAM_BB_BASE          SRAM1_BB_BASE\n\n/*!< Peripheral memory map */\n#define APB1PERIPH_BASE       PERIPH_BASE\n#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)\n#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)\n#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)\n\n/*!< APB1 peripherals */\n#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)\n#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)\n#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)\n#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)\n#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)\n#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)\n#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)\n#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)\n#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)\n#define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)\n#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)\n#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)\n#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400UL)\n#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)\n#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)\n#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000UL)\n#define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)\n#define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)\n#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)\n#define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)\n#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)\n#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)\n#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)\n#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)\n#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)\n#define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)\n#define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)\n\n/*!< APB2 peripherals */\n#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)\n#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)\n#define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)\n#define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)\n#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)\n#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100UL)\n#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200UL)\n#define ADC123_COMMON_BASE    (APB2PERIPH_BASE + 0x2300UL)\n/* Legacy define */\n#define ADC_BASE               ADC123_COMMON_BASE\n#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)\n#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)\n#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)\n#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)\n#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)\n#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)\n#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)\n\n/*!< AHB1 peripherals */\n#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)\n#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)\n#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)\n#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)\n#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)\n#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)\n#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)\n#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)\n#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000UL)\n#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)\n#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)\n#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)\n#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)\n#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)\n#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)\n#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)\n#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)\n#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)\n#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)\n#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)\n#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)\n#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)\n#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)\n#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)\n#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)\n#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)\n#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)\n#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)\n#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)\n#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)\n\n/*!< AHB2 peripherals */\n#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800UL)\n\n/*!< FSMC Bankx registers base address */\n#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000UL)\n#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104UL)\n#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060UL)\n#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0UL)\n\n\n/*!< Debug MCU registers base address */\n#define DBGMCU_BASE           0xE0042000UL\n/*!< USB registers base address */\n#define USB_OTG_HS_PERIPH_BASE               0x40040000UL\n#define USB_OTG_FS_PERIPH_BASE               0x50000000UL\n\n#define USB_OTG_GLOBAL_BASE                  0x000UL\n#define USB_OTG_DEVICE_BASE                  0x800UL\n#define USB_OTG_IN_ENDPOINT_BASE             0x900UL\n#define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL\n#define USB_OTG_EP_REG_SIZE                  0x20UL\n#define USB_OTG_HOST_BASE                    0x400UL\n#define USB_OTG_HOST_PORT_BASE               0x440UL\n#define USB_OTG_HOST_CHANNEL_BASE            0x500UL\n#define USB_OTG_HOST_CHANNEL_SIZE            0x20UL\n#define USB_OTG_PCGCCTL_BASE                 0xE00UL\n#define USB_OTG_FIFO_BASE                    0x1000UL\n#define USB_OTG_FIFO_SIZE                    0x1000UL\n\n#define UID_BASE                     0x1FFF7A10UL           /*!< Unique device ID register base address */\n#define FLASHSIZE_BASE               0x1FFF7A22UL           /*!< FLASH Size register base address       */\n#define PACKAGE_BASE                 0x1FFF7BF0UL           /*!< Package size register base address     */\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_declaration\n  * @{\n  */\n#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\n#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\n#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\n#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\n#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\n#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\n#define TIM12               ((TIM_TypeDef *) TIM12_BASE)\n#define TIM13               ((TIM_TypeDef *) TIM13_BASE)\n#define TIM14               ((TIM_TypeDef *) TIM14_BASE)\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\n#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\n#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\n#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)\n#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\n#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\n#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)\n#define USART2              ((USART_TypeDef *) USART2_BASE)\n#define USART3              ((USART_TypeDef *) USART3_BASE)\n#define UART4               ((USART_TypeDef *) UART4_BASE)\n#define UART5               ((USART_TypeDef *) UART5_BASE)\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\n#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\n#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\n#define CAN1                ((CAN_TypeDef *) CAN1_BASE)\n#define CAN2                ((CAN_TypeDef *) CAN2_BASE)\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\n#define DAC1                ((DAC_TypeDef *) DAC_BASE)\n#define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */\n#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\n#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\n#define USART1              ((USART_TypeDef *) USART1_BASE)\n#define USART6              ((USART_TypeDef *) USART6_BASE)\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\n#define ADC2                ((ADC_TypeDef *) ADC2_BASE)\n#define ADC3                ((ADC_TypeDef *) ADC3_BASE)\n#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)\n/* Legacy define */\n#define ADC                  ADC123_COMMON\n#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\n#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\n#define TIM9                ((TIM_TypeDef *) TIM9_BASE)\n#define TIM10               ((TIM_TypeDef *) TIM10_BASE)\n#define TIM11               ((TIM_TypeDef *) TIM11_BASE)\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\n#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\n#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\n#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)\n#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\n#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\n#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\n#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\n#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\n#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\n#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\n#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\n#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\n#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\n#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\n#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\n#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\n#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\n#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\n#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\n#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\n#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\n#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\n#define RNG                 ((RNG_TypeDef *) RNG_BASE)\n#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)\n#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)\n#define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)\n#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)\n#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\n#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\n#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_constants\n  * @{\n  */\n\n  /** @addtogroup Peripheral_Registers_Bits_Definition\n  * @{\n  */\n\n/******************************************************************************/\n/*                         Peripheral Registers_Bits_Definition               */\n/******************************************************************************/\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Analog to Digital Converter                         */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define ADC_MULTIMODE_SUPPORT                                                  /*!<ADC Multimode feature available on specific devices */\n\n/********************  Bit definition for ADC_SR register  ********************/\n#define ADC_SR_AWD_Pos            (0U)\n#define ADC_SR_AWD_Msk            (0x1UL << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */\n#define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */\n#define ADC_SR_EOC_Pos            (1U)\n#define ADC_SR_EOC_Msk            (0x1UL << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */\n#define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */\n#define ADC_SR_JEOC_Pos           (2U)\n#define ADC_SR_JEOC_Msk           (0x1UL << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */\n#define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */\n#define ADC_SR_JSTRT_Pos          (3U)\n#define ADC_SR_JSTRT_Msk          (0x1UL << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */\n#define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */\n#define ADC_SR_STRT_Pos           (4U)\n#define ADC_SR_STRT_Msk           (0x1UL << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */\n#define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */\n#define ADC_SR_OVR_Pos            (5U)\n#define ADC_SR_OVR_Msk            (0x1UL << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */\n#define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */\n\n/*******************  Bit definition for ADC_CR1 register  ********************/\n#define ADC_CR1_AWDCH_Pos         (0U)\n#define ADC_CR1_AWDCH_Msk         (0x1FUL << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */\n#define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\n#define ADC_CR1_AWDCH_0           (0x01UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */\n#define ADC_CR1_AWDCH_1           (0x02UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */\n#define ADC_CR1_AWDCH_2           (0x04UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */\n#define ADC_CR1_AWDCH_3           (0x08UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */\n#define ADC_CR1_AWDCH_4           (0x10UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */\n#define ADC_CR1_EOCIE_Pos         (5U)\n#define ADC_CR1_EOCIE_Msk         (0x1UL << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */\n#define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */\n#define ADC_CR1_AWDIE_Pos         (6U)\n#define ADC_CR1_AWDIE_Msk         (0x1UL << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */\n#define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */\n#define ADC_CR1_JEOCIE_Pos        (7U)\n#define ADC_CR1_JEOCIE_Msk        (0x1UL << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */\n#define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */\n#define ADC_CR1_SCAN_Pos          (8U)\n#define ADC_CR1_SCAN_Msk          (0x1UL << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */\n#define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */\n#define ADC_CR1_AWDSGL_Pos        (9U)\n#define ADC_CR1_AWDSGL_Msk        (0x1UL << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */\n#define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */\n#define ADC_CR1_JAUTO_Pos         (10U)\n#define ADC_CR1_JAUTO_Msk         (0x1UL << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */\n#define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */\n#define ADC_CR1_DISCEN_Pos        (11U)\n#define ADC_CR1_DISCEN_Msk        (0x1UL << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */\n#define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */\n#define ADC_CR1_JDISCEN_Pos       (12U)\n#define ADC_CR1_JDISCEN_Msk       (0x1UL << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */\n#define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */\n#define ADC_CR1_DISCNUM_Pos       (13U)\n#define ADC_CR1_DISCNUM_Msk       (0x7UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */\n#define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\n#define ADC_CR1_DISCNUM_0         (0x1UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */\n#define ADC_CR1_DISCNUM_1         (0x2UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */\n#define ADC_CR1_DISCNUM_2         (0x4UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */\n#define ADC_CR1_JAWDEN_Pos        (22U)\n#define ADC_CR1_JAWDEN_Msk        (0x1UL << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */\n#define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */\n#define ADC_CR1_AWDEN_Pos         (23U)\n#define ADC_CR1_AWDEN_Msk         (0x1UL << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */\n#define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */\n#define ADC_CR1_RES_Pos           (24U)\n#define ADC_CR1_RES_Msk           (0x3UL << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */\n#define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */\n#define ADC_CR1_RES_0             (0x1UL << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */\n#define ADC_CR1_RES_1             (0x2UL << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */\n#define ADC_CR1_OVRIE_Pos         (26U)\n#define ADC_CR1_OVRIE_Msk         (0x1UL << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */\n#define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */\n\n/*******************  Bit definition for ADC_CR2 register  ********************/\n#define ADC_CR2_ADON_Pos          (0U)\n#define ADC_CR2_ADON_Msk          (0x1UL << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */\n#define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */\n#define ADC_CR2_CONT_Pos          (1U)\n#define ADC_CR2_CONT_Msk          (0x1UL << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */\n#define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */\n#define ADC_CR2_DMA_Pos           (8U)\n#define ADC_CR2_DMA_Msk           (0x1UL << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */\n#define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */\n#define ADC_CR2_DDS_Pos           (9U)\n#define ADC_CR2_DDS_Msk           (0x1UL << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */\n#define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */\n#define ADC_CR2_EOCS_Pos          (10U)\n#define ADC_CR2_EOCS_Msk          (0x1UL << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */\n#define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */\n#define ADC_CR2_ALIGN_Pos         (11U)\n#define ADC_CR2_ALIGN_Msk         (0x1UL << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */\n#define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */\n#define ADC_CR2_JEXTSEL_Pos       (16U)\n#define ADC_CR2_JEXTSEL_Msk       (0xFUL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */\n#define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */\n#define ADC_CR2_JEXTSEL_0         (0x1UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */\n#define ADC_CR2_JEXTSEL_1         (0x2UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */\n#define ADC_CR2_JEXTSEL_2         (0x4UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */\n#define ADC_CR2_JEXTSEL_3         (0x8UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */\n#define ADC_CR2_JEXTEN_Pos        (20U)\n#define ADC_CR2_JEXTEN_Msk        (0x3UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */\n#define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\n#define ADC_CR2_JEXTEN_0          (0x1UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */\n#define ADC_CR2_JEXTEN_1          (0x2UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */\n#define ADC_CR2_JSWSTART_Pos      (22U)\n#define ADC_CR2_JSWSTART_Msk      (0x1UL << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */\n#define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */\n#define ADC_CR2_EXTSEL_Pos        (24U)\n#define ADC_CR2_EXTSEL_Msk        (0xFUL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */\n#define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\n#define ADC_CR2_EXTSEL_0          (0x1UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */\n#define ADC_CR2_EXTSEL_1          (0x2UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */\n#define ADC_CR2_EXTSEL_2          (0x4UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */\n#define ADC_CR2_EXTSEL_3          (0x8UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */\n#define ADC_CR2_EXTEN_Pos         (28U)\n#define ADC_CR2_EXTEN_Msk         (0x3UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */\n#define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\n#define ADC_CR2_EXTEN_0           (0x1UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */\n#define ADC_CR2_EXTEN_1           (0x2UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */\n#define ADC_CR2_SWSTART_Pos       (30U)\n#define ADC_CR2_SWSTART_Msk       (0x1UL << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */\n#define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */\n\n/******************  Bit definition for ADC_SMPR1 register  *******************/\n#define ADC_SMPR1_SMP10_Pos       (0U)\n#define ADC_SMPR1_SMP10_Msk       (0x7UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */\n#define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\n#define ADC_SMPR1_SMP10_0         (0x1UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */\n#define ADC_SMPR1_SMP10_1         (0x2UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */\n#define ADC_SMPR1_SMP10_2         (0x4UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */\n#define ADC_SMPR1_SMP11_Pos       (3U)\n#define ADC_SMPR1_SMP11_Msk       (0x7UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */\n#define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\n#define ADC_SMPR1_SMP11_0         (0x1UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */\n#define ADC_SMPR1_SMP11_1         (0x2UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */\n#define ADC_SMPR1_SMP11_2         (0x4UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */\n#define ADC_SMPR1_SMP12_Pos       (6U)\n#define ADC_SMPR1_SMP12_Msk       (0x7UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */\n#define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\n#define ADC_SMPR1_SMP12_0         (0x1UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */\n#define ADC_SMPR1_SMP12_1         (0x2UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */\n#define ADC_SMPR1_SMP12_2         (0x4UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */\n#define ADC_SMPR1_SMP13_Pos       (9U)\n#define ADC_SMPR1_SMP13_Msk       (0x7UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */\n#define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\n#define ADC_SMPR1_SMP13_0         (0x1UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */\n#define ADC_SMPR1_SMP13_1         (0x2UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */\n#define ADC_SMPR1_SMP13_2         (0x4UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */\n#define ADC_SMPR1_SMP14_Pos       (12U)\n#define ADC_SMPR1_SMP14_Msk       (0x7UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */\n#define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\n#define ADC_SMPR1_SMP14_0         (0x1UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */\n#define ADC_SMPR1_SMP14_1         (0x2UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */\n#define ADC_SMPR1_SMP14_2         (0x4UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */\n#define ADC_SMPR1_SMP15_Pos       (15U)\n#define ADC_SMPR1_SMP15_Msk       (0x7UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */\n#define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\n#define ADC_SMPR1_SMP15_0         (0x1UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */\n#define ADC_SMPR1_SMP15_1         (0x2UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */\n#define ADC_SMPR1_SMP15_2         (0x4UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */\n#define ADC_SMPR1_SMP16_Pos       (18U)\n#define ADC_SMPR1_SMP16_Msk       (0x7UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */\n#define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\n#define ADC_SMPR1_SMP16_0         (0x1UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */\n#define ADC_SMPR1_SMP16_1         (0x2UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */\n#define ADC_SMPR1_SMP16_2         (0x4UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */\n#define ADC_SMPR1_SMP17_Pos       (21U)\n#define ADC_SMPR1_SMP17_Msk       (0x7UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */\n#define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\n#define ADC_SMPR1_SMP17_0         (0x1UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */\n#define ADC_SMPR1_SMP17_1         (0x2UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */\n#define ADC_SMPR1_SMP17_2         (0x4UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */\n#define ADC_SMPR1_SMP18_Pos       (24U)\n#define ADC_SMPR1_SMP18_Msk       (0x7UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */\n#define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\n#define ADC_SMPR1_SMP18_0         (0x1UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */\n#define ADC_SMPR1_SMP18_1         (0x2UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */\n#define ADC_SMPR1_SMP18_2         (0x4UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */\n\n/******************  Bit definition for ADC_SMPR2 register  *******************/\n#define ADC_SMPR2_SMP0_Pos        (0U)\n#define ADC_SMPR2_SMP0_Msk        (0x7UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */\n#define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\n#define ADC_SMPR2_SMP0_0          (0x1UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */\n#define ADC_SMPR2_SMP0_1          (0x2UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */\n#define ADC_SMPR2_SMP0_2          (0x4UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */\n#define ADC_SMPR2_SMP1_Pos        (3U)\n#define ADC_SMPR2_SMP1_Msk        (0x7UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */\n#define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\n#define ADC_SMPR2_SMP1_0          (0x1UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */\n#define ADC_SMPR2_SMP1_1          (0x2UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */\n#define ADC_SMPR2_SMP1_2          (0x4UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */\n#define ADC_SMPR2_SMP2_Pos        (6U)\n#define ADC_SMPR2_SMP2_Msk        (0x7UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */\n#define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\n#define ADC_SMPR2_SMP2_0          (0x1UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */\n#define ADC_SMPR2_SMP2_1          (0x2UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */\n#define ADC_SMPR2_SMP2_2          (0x4UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */\n#define ADC_SMPR2_SMP3_Pos        (9U)\n#define ADC_SMPR2_SMP3_Msk        (0x7UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */\n#define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\n#define ADC_SMPR2_SMP3_0          (0x1UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */\n#define ADC_SMPR2_SMP3_1          (0x2UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */\n#define ADC_SMPR2_SMP3_2          (0x4UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */\n#define ADC_SMPR2_SMP4_Pos        (12U)\n#define ADC_SMPR2_SMP4_Msk        (0x7UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */\n#define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\n#define ADC_SMPR2_SMP4_0          (0x1UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */\n#define ADC_SMPR2_SMP4_1          (0x2UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */\n#define ADC_SMPR2_SMP4_2          (0x4UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */\n#define ADC_SMPR2_SMP5_Pos        (15U)\n#define ADC_SMPR2_SMP5_Msk        (0x7UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */\n#define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\n#define ADC_SMPR2_SMP5_0          (0x1UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */\n#define ADC_SMPR2_SMP5_1          (0x2UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */\n#define ADC_SMPR2_SMP5_2          (0x4UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */\n#define ADC_SMPR2_SMP6_Pos        (18U)\n#define ADC_SMPR2_SMP6_Msk        (0x7UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */\n#define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\n#define ADC_SMPR2_SMP6_0          (0x1UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */\n#define ADC_SMPR2_SMP6_1          (0x2UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */\n#define ADC_SMPR2_SMP6_2          (0x4UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */\n#define ADC_SMPR2_SMP7_Pos        (21U)\n#define ADC_SMPR2_SMP7_Msk        (0x7UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */\n#define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\n#define ADC_SMPR2_SMP7_0          (0x1UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */\n#define ADC_SMPR2_SMP7_1          (0x2UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */\n#define ADC_SMPR2_SMP7_2          (0x4UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */\n#define ADC_SMPR2_SMP8_Pos        (24U)\n#define ADC_SMPR2_SMP8_Msk        (0x7UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */\n#define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\n#define ADC_SMPR2_SMP8_0          (0x1UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */\n#define ADC_SMPR2_SMP8_1          (0x2UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */\n#define ADC_SMPR2_SMP8_2          (0x4UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */\n#define ADC_SMPR2_SMP9_Pos        (27U)\n#define ADC_SMPR2_SMP9_Msk        (0x7UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */\n#define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\n#define ADC_SMPR2_SMP9_0          (0x1UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */\n#define ADC_SMPR2_SMP9_1          (0x2UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */\n#define ADC_SMPR2_SMP9_2          (0x4UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */\n\n/******************  Bit definition for ADC_JOFR1 register  *******************/\n#define ADC_JOFR1_JOFFSET1_Pos    (0U)\n#define ADC_JOFR1_JOFFSET1_Msk    (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */\n\n/******************  Bit definition for ADC_JOFR2 register  *******************/\n#define ADC_JOFR2_JOFFSET2_Pos    (0U)\n#define ADC_JOFR2_JOFFSET2_Msk    (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */\n\n/******************  Bit definition for ADC_JOFR3 register  *******************/\n#define ADC_JOFR3_JOFFSET3_Pos    (0U)\n#define ADC_JOFR3_JOFFSET3_Msk    (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */\n\n/******************  Bit definition for ADC_JOFR4 register  *******************/\n#define ADC_JOFR4_JOFFSET4_Pos    (0U)\n#define ADC_JOFR4_JOFFSET4_Msk    (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */\n\n/*******************  Bit definition for ADC_HTR register  ********************/\n#define ADC_HTR_HT_Pos            (0U)\n#define ADC_HTR_HT_Msk            (0xFFFUL << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */\n#define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */\n\n/*******************  Bit definition for ADC_LTR register  ********************/\n#define ADC_LTR_LT_Pos            (0U)\n#define ADC_LTR_LT_Msk            (0xFFFUL << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */\n#define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */\n\n/*******************  Bit definition for ADC_SQR1 register  *******************/\n#define ADC_SQR1_SQ13_Pos         (0U)\n#define ADC_SQR1_SQ13_Msk         (0x1FUL << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */\n#define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\n#define ADC_SQR1_SQ13_0           (0x01UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */\n#define ADC_SQR1_SQ13_1           (0x02UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */\n#define ADC_SQR1_SQ13_2           (0x04UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */\n#define ADC_SQR1_SQ13_3           (0x08UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */\n#define ADC_SQR1_SQ13_4           (0x10UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */\n#define ADC_SQR1_SQ14_Pos         (5U)\n#define ADC_SQR1_SQ14_Msk         (0x1FUL << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */\n#define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\n#define ADC_SQR1_SQ14_0           (0x01UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */\n#define ADC_SQR1_SQ14_1           (0x02UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */\n#define ADC_SQR1_SQ14_2           (0x04UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */\n#define ADC_SQR1_SQ14_3           (0x08UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */\n#define ADC_SQR1_SQ14_4           (0x10UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */\n#define ADC_SQR1_SQ15_Pos         (10U)\n#define ADC_SQR1_SQ15_Msk         (0x1FUL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */\n#define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\n#define ADC_SQR1_SQ15_0           (0x01UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */\n#define ADC_SQR1_SQ15_1           (0x02UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */\n#define ADC_SQR1_SQ15_2           (0x04UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */\n#define ADC_SQR1_SQ15_3           (0x08UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */\n#define ADC_SQR1_SQ15_4           (0x10UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */\n#define ADC_SQR1_SQ16_Pos         (15U)\n#define ADC_SQR1_SQ16_Msk         (0x1FUL << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\n#define ADC_SQR1_SQ16_0           (0x01UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR1_SQ16_1           (0x02UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR1_SQ16_2           (0x04UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR1_SQ16_3           (0x08UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR1_SQ16_4           (0x10UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR1_L_Pos            (20U)\n#define ADC_SQR1_L_Msk            (0xFUL << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */\n#define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */\n#define ADC_SQR1_L_0              (0x1UL << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */\n#define ADC_SQR1_L_1              (0x2UL << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */\n#define ADC_SQR1_L_2              (0x4UL << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */\n#define ADC_SQR1_L_3              (0x8UL << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */\n\n/*******************  Bit definition for ADC_SQR2 register  *******************/\n#define ADC_SQR2_SQ7_Pos          (0U)\n#define ADC_SQR2_SQ7_Msk          (0x1FUL << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\n#define ADC_SQR2_SQ7_0            (0x01UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR2_SQ7_1            (0x02UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR2_SQ7_2            (0x04UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR2_SQ7_3            (0x08UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR2_SQ7_4            (0x10UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR2_SQ8_Pos          (5U)\n#define ADC_SQR2_SQ8_Msk          (0x1FUL << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\n#define ADC_SQR2_SQ8_0            (0x01UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR2_SQ8_1            (0x02UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR2_SQ8_2            (0x04UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR2_SQ8_3            (0x08UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR2_SQ8_4            (0x10UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR2_SQ9_Pos          (10U)\n#define ADC_SQR2_SQ9_Msk          (0x1FUL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\n#define ADC_SQR2_SQ9_0            (0x01UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR2_SQ9_1            (0x02UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR2_SQ9_2            (0x04UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR2_SQ9_3            (0x08UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR2_SQ9_4            (0x10UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR2_SQ10_Pos         (15U)\n#define ADC_SQR2_SQ10_Msk         (0x1FUL << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\n#define ADC_SQR2_SQ10_0           (0x01UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR2_SQ10_1           (0x02UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR2_SQ10_2           (0x04UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR2_SQ10_3           (0x08UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR2_SQ10_4           (0x10UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR2_SQ11_Pos         (20U)\n#define ADC_SQR2_SQ11_Msk         (0x1FUL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */\n#define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\n#define ADC_SQR2_SQ11_0           (0x01UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */\n#define ADC_SQR2_SQ11_1           (0x02UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */\n#define ADC_SQR2_SQ11_2           (0x04UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */\n#define ADC_SQR2_SQ11_3           (0x08UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */\n#define ADC_SQR2_SQ11_4           (0x10UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */\n#define ADC_SQR2_SQ12_Pos         (25U)\n#define ADC_SQR2_SQ12_Msk         (0x1FUL << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */\n#define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\n#define ADC_SQR2_SQ12_0           (0x01UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */\n#define ADC_SQR2_SQ12_1           (0x02UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */\n#define ADC_SQR2_SQ12_2           (0x04UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */\n#define ADC_SQR2_SQ12_3           (0x08UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */\n#define ADC_SQR2_SQ12_4           (0x10UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_SQR3 register  *******************/\n#define ADC_SQR3_SQ1_Pos          (0U)\n#define ADC_SQR3_SQ1_Msk          (0x1FUL << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\n#define ADC_SQR3_SQ1_0            (0x01UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR3_SQ1_1            (0x02UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR3_SQ1_2            (0x04UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR3_SQ1_3            (0x08UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR3_SQ1_4            (0x10UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR3_SQ2_Pos          (5U)\n#define ADC_SQR3_SQ2_Msk          (0x1FUL << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\n#define ADC_SQR3_SQ2_0            (0x01UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR3_SQ2_1            (0x02UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR3_SQ2_2            (0x04UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR3_SQ2_3            (0x08UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR3_SQ2_4            (0x10UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR3_SQ3_Pos          (10U)\n#define ADC_SQR3_SQ3_Msk          (0x1FUL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\n#define ADC_SQR3_SQ3_0            (0x01UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR3_SQ3_1            (0x02UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR3_SQ3_2            (0x04UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR3_SQ3_3            (0x08UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR3_SQ3_4            (0x10UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR3_SQ4_Pos          (15U)\n#define ADC_SQR3_SQ4_Msk          (0x1FUL << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */\n#define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\n#define ADC_SQR3_SQ4_0            (0x01UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */\n#define ADC_SQR3_SQ4_1            (0x02UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */\n#define ADC_SQR3_SQ4_2            (0x04UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */\n#define ADC_SQR3_SQ4_3            (0x08UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */\n#define ADC_SQR3_SQ4_4            (0x10UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */\n#define ADC_SQR3_SQ5_Pos          (20U)\n#define ADC_SQR3_SQ5_Msk          (0x1FUL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */\n#define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\n#define ADC_SQR3_SQ5_0            (0x01UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */\n#define ADC_SQR3_SQ5_1            (0x02UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */\n#define ADC_SQR3_SQ5_2            (0x04UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */\n#define ADC_SQR3_SQ5_3            (0x08UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */\n#define ADC_SQR3_SQ5_4            (0x10UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */\n#define ADC_SQR3_SQ6_Pos          (25U)\n#define ADC_SQR3_SQ6_Msk          (0x1FUL << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */\n#define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\n#define ADC_SQR3_SQ6_0            (0x01UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */\n#define ADC_SQR3_SQ6_1            (0x02UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */\n#define ADC_SQR3_SQ6_2            (0x04UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */\n#define ADC_SQR3_SQ6_3            (0x08UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */\n#define ADC_SQR3_SQ6_4            (0x10UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_JSQR register  *******************/\n#define ADC_JSQR_JSQ1_Pos         (0U)\n#define ADC_JSQR_JSQ1_Msk         (0x1FUL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */\n#define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */\n#define ADC_JSQR_JSQ1_0           (0x01UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */\n#define ADC_JSQR_JSQ1_1           (0x02UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */\n#define ADC_JSQR_JSQ1_2           (0x04UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */\n#define ADC_JSQR_JSQ1_3           (0x08UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */\n#define ADC_JSQR_JSQ1_4           (0x10UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */\n#define ADC_JSQR_JSQ2_Pos         (5U)\n#define ADC_JSQR_JSQ2_Msk         (0x1FUL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */\n#define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\n#define ADC_JSQR_JSQ2_0           (0x01UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */\n#define ADC_JSQR_JSQ2_1           (0x02UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */\n#define ADC_JSQR_JSQ2_2           (0x04UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */\n#define ADC_JSQR_JSQ2_3           (0x08UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */\n#define ADC_JSQR_JSQ2_4           (0x10UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */\n#define ADC_JSQR_JSQ3_Pos         (10U)\n#define ADC_JSQR_JSQ3_Msk         (0x1FUL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */\n#define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\n#define ADC_JSQR_JSQ3_0           (0x01UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */\n#define ADC_JSQR_JSQ3_1           (0x02UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */\n#define ADC_JSQR_JSQ3_2           (0x04UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */\n#define ADC_JSQR_JSQ3_3           (0x08UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */\n#define ADC_JSQR_JSQ3_4           (0x10UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */\n#define ADC_JSQR_JSQ4_Pos         (15U)\n#define ADC_JSQR_JSQ4_Msk         (0x1FUL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */\n#define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\n#define ADC_JSQR_JSQ4_0           (0x01UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */\n#define ADC_JSQR_JSQ4_1           (0x02UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */\n#define ADC_JSQR_JSQ4_2           (0x04UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */\n#define ADC_JSQR_JSQ4_3           (0x08UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */\n#define ADC_JSQR_JSQ4_4           (0x10UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */\n#define ADC_JSQR_JL_Pos           (20U)\n#define ADC_JSQR_JL_Msk           (0x3UL << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */\n#define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */\n#define ADC_JSQR_JL_0             (0x1UL << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */\n#define ADC_JSQR_JL_1             (0x2UL << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */\n\n/*******************  Bit definition for ADC_JDR1 register  *******************/\n#define ADC_JDR1_JDATA_Pos        (0U)\n#define ADC_JDR1_JDATA_Msk        (0xFFFFUL << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR2 register  *******************/\n#define ADC_JDR2_JDATA_Pos        (0U)\n#define ADC_JDR2_JDATA_Msk        (0xFFFFUL << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR3 register  *******************/\n#define ADC_JDR3_JDATA_Pos        (0U)\n#define ADC_JDR3_JDATA_Msk        (0xFFFFUL << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR4 register  *******************/\n#define ADC_JDR4_JDATA_Pos        (0U)\n#define ADC_JDR4_JDATA_Msk        (0xFFFFUL << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */\n\n/********************  Bit definition for ADC_DR register  ********************/\n#define ADC_DR_DATA_Pos           (0U)\n#define ADC_DR_DATA_Msk           (0xFFFFUL << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */\n#define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */\n#define ADC_DR_ADC2DATA_Pos       (16U)\n#define ADC_DR_ADC2DATA_Msk       (0xFFFFUL << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */\n#define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */\n\n/*******************  Bit definition for ADC_CSR register  ********************/\n#define ADC_CSR_AWD1_Pos          (0U)\n#define ADC_CSR_AWD1_Msk          (0x1UL << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */\n#define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */\n#define ADC_CSR_EOC1_Pos          (1U)\n#define ADC_CSR_EOC1_Msk          (0x1UL << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */\n#define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */\n#define ADC_CSR_JEOC1_Pos         (2U)\n#define ADC_CSR_JEOC1_Msk         (0x1UL << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */\n#define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */\n#define ADC_CSR_JSTRT1_Pos        (3U)\n#define ADC_CSR_JSTRT1_Msk        (0x1UL << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */\n#define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */\n#define ADC_CSR_STRT1_Pos         (4U)\n#define ADC_CSR_STRT1_Msk         (0x1UL << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */\n#define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */\n#define ADC_CSR_OVR1_Pos          (5U)\n#define ADC_CSR_OVR1_Msk          (0x1UL << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */\n#define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */\n#define ADC_CSR_AWD2_Pos          (8U)\n#define ADC_CSR_AWD2_Msk          (0x1UL << ADC_CSR_AWD2_Pos)                   /*!< 0x00000100 */\n#define ADC_CSR_AWD2              ADC_CSR_AWD2_Msk                             /*!<ADC2 Analog watchdog flag */\n#define ADC_CSR_EOC2_Pos          (9U)\n#define ADC_CSR_EOC2_Msk          (0x1UL << ADC_CSR_EOC2_Pos)                   /*!< 0x00000200 */\n#define ADC_CSR_EOC2              ADC_CSR_EOC2_Msk                             /*!<ADC2 End of conversion */\n#define ADC_CSR_JEOC2_Pos         (10U)\n#define ADC_CSR_JEOC2_Msk         (0x1UL << ADC_CSR_JEOC2_Pos)                  /*!< 0x00000400 */\n#define ADC_CSR_JEOC2             ADC_CSR_JEOC2_Msk                            /*!<ADC2 Injected channel end of conversion */\n#define ADC_CSR_JSTRT2_Pos        (11U)\n#define ADC_CSR_JSTRT2_Msk        (0x1UL << ADC_CSR_JSTRT2_Pos)                 /*!< 0x00000800 */\n#define ADC_CSR_JSTRT2            ADC_CSR_JSTRT2_Msk                           /*!<ADC2 Injected channel Start flag */\n#define ADC_CSR_STRT2_Pos         (12U)\n#define ADC_CSR_STRT2_Msk         (0x1UL << ADC_CSR_STRT2_Pos)                  /*!< 0x00001000 */\n#define ADC_CSR_STRT2             ADC_CSR_STRT2_Msk                            /*!<ADC2 Regular channel Start flag */\n#define ADC_CSR_OVR2_Pos          (13U)\n#define ADC_CSR_OVR2_Msk          (0x1UL << ADC_CSR_OVR2_Pos)                   /*!< 0x00002000 */\n#define ADC_CSR_OVR2              ADC_CSR_OVR2_Msk                             /*!<ADC2 DMA overrun  flag */\n#define ADC_CSR_AWD3_Pos          (16U)\n#define ADC_CSR_AWD3_Msk          (0x1UL << ADC_CSR_AWD3_Pos)                   /*!< 0x00010000 */\n#define ADC_CSR_AWD3              ADC_CSR_AWD3_Msk                             /*!<ADC3 Analog watchdog flag */\n#define ADC_CSR_EOC3_Pos          (17U)\n#define ADC_CSR_EOC3_Msk          (0x1UL << ADC_CSR_EOC3_Pos)                   /*!< 0x00020000 */\n#define ADC_CSR_EOC3              ADC_CSR_EOC3_Msk                             /*!<ADC3 End of conversion */\n#define ADC_CSR_JEOC3_Pos         (18U)\n#define ADC_CSR_JEOC3_Msk         (0x1UL << ADC_CSR_JEOC3_Pos)                  /*!< 0x00040000 */\n#define ADC_CSR_JEOC3             ADC_CSR_JEOC3_Msk                            /*!<ADC3 Injected channel end of conversion */\n#define ADC_CSR_JSTRT3_Pos        (19U)\n#define ADC_CSR_JSTRT3_Msk        (0x1UL << ADC_CSR_JSTRT3_Pos)                 /*!< 0x00080000 */\n#define ADC_CSR_JSTRT3            ADC_CSR_JSTRT3_Msk                           /*!<ADC3 Injected channel Start flag */\n#define ADC_CSR_STRT3_Pos         (20U)\n#define ADC_CSR_STRT3_Msk         (0x1UL << ADC_CSR_STRT3_Pos)                  /*!< 0x00100000 */\n#define ADC_CSR_STRT3             ADC_CSR_STRT3_Msk                            /*!<ADC3 Regular channel Start flag */\n#define ADC_CSR_OVR3_Pos          (21U)\n#define ADC_CSR_OVR3_Msk          (0x1UL << ADC_CSR_OVR3_Pos)                   /*!< 0x00200000 */\n#define ADC_CSR_OVR3              ADC_CSR_OVR3_Msk                             /*!<ADC3 DMA overrun  flag */\n\n/* Legacy defines */\n#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1\n#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2\n#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3\n\n/*******************  Bit definition for ADC_CCR register  ********************/\n#define ADC_CCR_MULTI_Pos         (0U)\n#define ADC_CCR_MULTI_Msk         (0x1FUL << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */\n#define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */\n#define ADC_CCR_MULTI_0           (0x01UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */\n#define ADC_CCR_MULTI_1           (0x02UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */\n#define ADC_CCR_MULTI_2           (0x04UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */\n#define ADC_CCR_MULTI_3           (0x08UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */\n#define ADC_CCR_MULTI_4           (0x10UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */\n#define ADC_CCR_DELAY_Pos         (8U)\n#define ADC_CCR_DELAY_Msk         (0xFUL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */\n#define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */\n#define ADC_CCR_DELAY_0           (0x1UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */\n#define ADC_CCR_DELAY_1           (0x2UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */\n#define ADC_CCR_DELAY_2           (0x4UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */\n#define ADC_CCR_DELAY_3           (0x8UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */\n#define ADC_CCR_DDS_Pos           (13U)\n#define ADC_CCR_DDS_Msk           (0x1UL << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */\n#define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */\n#define ADC_CCR_DMA_Pos           (14U)\n#define ADC_CCR_DMA_Msk           (0x3UL << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */\n#define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */\n#define ADC_CCR_DMA_0             (0x1UL << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */\n#define ADC_CCR_DMA_1             (0x2UL << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */\n#define ADC_CCR_ADCPRE_Pos        (16U)\n#define ADC_CCR_ADCPRE_Msk        (0x3UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */\n#define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */\n#define ADC_CCR_ADCPRE_0          (0x1UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */\n#define ADC_CCR_ADCPRE_1          (0x2UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */\n#define ADC_CCR_VBATE_Pos         (22U)\n#define ADC_CCR_VBATE_Msk         (0x1UL << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */\n#define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */\n#define ADC_CCR_TSVREFE_Pos       (23U)\n#define ADC_CCR_TSVREFE_Msk       (0x1UL << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */\n#define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */\n\n/*******************  Bit definition for ADC_CDR register  ********************/\n#define ADC_CDR_DATA1_Pos         (0U)\n#define ADC_CDR_DATA1_Msk         (0xFFFFUL << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */\n#define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */\n#define ADC_CDR_DATA2_Pos         (16U)\n#define ADC_CDR_DATA2_Msk         (0xFFFFUL << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */\n#define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */\n\n/* Legacy defines */\n#define ADC_CDR_RDATA_MST         ADC_CDR_DATA1\n#define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Controller Area Network                            */\n/*                                                                            */\n/******************************************************************************/\n/*!<CAN control and status registers */\n/*******************  Bit definition for CAN_MCR register  ********************/\n#define CAN_MCR_INRQ_Pos       (0U)\n#define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */\n#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */\n#define CAN_MCR_SLEEP_Pos      (1U)\n#define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */\n#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */\n#define CAN_MCR_TXFP_Pos       (2U)\n#define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */\n#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */\n#define CAN_MCR_RFLM_Pos       (3U)\n#define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */\n#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */\n#define CAN_MCR_NART_Pos       (4U)\n#define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */\n#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */\n#define CAN_MCR_AWUM_Pos       (5U)\n#define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */\n#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */\n#define CAN_MCR_ABOM_Pos       (6U)\n#define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */\n#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */\n#define CAN_MCR_TTCM_Pos       (7U)\n#define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */\n#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */\n#define CAN_MCR_RESET_Pos      (15U)\n#define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */\n#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */\n#define CAN_MCR_DBF_Pos        (16U)\n#define CAN_MCR_DBF_Msk        (0x1UL << CAN_MCR_DBF_Pos)                       /*!< 0x00010000 */\n#define CAN_MCR_DBF            CAN_MCR_DBF_Msk                                 /*!<bxCAN Debug freeze */\n/*******************  Bit definition for CAN_MSR register  ********************/\n#define CAN_MSR_INAK_Pos       (0U)\n#define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */\n#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */\n#define CAN_MSR_SLAK_Pos       (1U)\n#define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */\n#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */\n#define CAN_MSR_ERRI_Pos       (2U)\n#define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */\n#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */\n#define CAN_MSR_WKUI_Pos       (3U)\n#define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */\n#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */\n#define CAN_MSR_SLAKI_Pos      (4U)\n#define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */\n#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */\n#define CAN_MSR_TXM_Pos        (8U)\n#define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */\n#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */\n#define CAN_MSR_RXM_Pos        (9U)\n#define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */\n#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */\n#define CAN_MSR_SAMP_Pos       (10U)\n#define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */\n#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */\n#define CAN_MSR_RX_Pos         (11U)\n#define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */\n#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */\n\n/*******************  Bit definition for CAN_TSR register  ********************/\n#define CAN_TSR_RQCP0_Pos      (0U)\n#define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */\n#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */\n#define CAN_TSR_TXOK0_Pos      (1U)\n#define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */\n#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */\n#define CAN_TSR_ALST0_Pos      (2U)\n#define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */\n#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */\n#define CAN_TSR_TERR0_Pos      (3U)\n#define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */\n#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */\n#define CAN_TSR_ABRQ0_Pos      (7U)\n#define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */\n#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */\n#define CAN_TSR_RQCP1_Pos      (8U)\n#define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */\n#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */\n#define CAN_TSR_TXOK1_Pos      (9U)\n#define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */\n#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */\n#define CAN_TSR_ALST1_Pos      (10U)\n#define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */\n#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */\n#define CAN_TSR_TERR1_Pos      (11U)\n#define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */\n#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */\n#define CAN_TSR_ABRQ1_Pos      (15U)\n#define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */\n#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */\n#define CAN_TSR_RQCP2_Pos      (16U)\n#define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */\n#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */\n#define CAN_TSR_TXOK2_Pos      (17U)\n#define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */\n#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */\n#define CAN_TSR_ALST2_Pos      (18U)\n#define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */\n#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */\n#define CAN_TSR_TERR2_Pos      (19U)\n#define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */\n#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */\n#define CAN_TSR_ABRQ2_Pos      (23U)\n#define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */\n#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */\n#define CAN_TSR_CODE_Pos       (24U)\n#define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */\n#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */\n\n#define CAN_TSR_TME_Pos        (26U)\n#define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */\n#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */\n#define CAN_TSR_TME0_Pos       (26U)\n#define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */\n#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */\n#define CAN_TSR_TME1_Pos       (27U)\n#define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */\n#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */\n#define CAN_TSR_TME2_Pos       (28U)\n#define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */\n#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */\n\n#define CAN_TSR_LOW_Pos        (29U)\n#define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */\n#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */\n#define CAN_TSR_LOW0_Pos       (29U)\n#define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */\n#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */\n#define CAN_TSR_LOW1_Pos       (30U)\n#define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */\n#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */\n#define CAN_TSR_LOW2_Pos       (31U)\n#define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */\n#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */\n\n/*******************  Bit definition for CAN_RF0R register  *******************/\n#define CAN_RF0R_FMP0_Pos      (0U)\n#define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */\n#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */\n#define CAN_RF0R_FULL0_Pos     (3U)\n#define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */\n#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */\n#define CAN_RF0R_FOVR0_Pos     (4U)\n#define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */\n#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */\n#define CAN_RF0R_RFOM0_Pos     (5U)\n#define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */\n#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */\n\n/*******************  Bit definition for CAN_RF1R register  *******************/\n#define CAN_RF1R_FMP1_Pos      (0U)\n#define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */\n#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */\n#define CAN_RF1R_FULL1_Pos     (3U)\n#define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */\n#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */\n#define CAN_RF1R_FOVR1_Pos     (4U)\n#define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */\n#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */\n#define CAN_RF1R_RFOM1_Pos     (5U)\n#define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */\n#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */\n\n/********************  Bit definition for CAN_IER register  *******************/\n#define CAN_IER_TMEIE_Pos      (0U)\n#define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */\n#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */\n#define CAN_IER_FMPIE0_Pos     (1U)\n#define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */\n#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE0_Pos      (2U)\n#define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */\n#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE0_Pos     (3U)\n#define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */\n#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_FMPIE1_Pos     (4U)\n#define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */\n#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE1_Pos      (5U)\n#define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */\n#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE1_Pos     (6U)\n#define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */\n#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)\n#define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */\n#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */\n#define CAN_IER_EPVIE_Pos      (9U)\n#define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */\n#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */\n#define CAN_IER_BOFIE_Pos      (10U)\n#define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */\n#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */\n#define CAN_IER_LECIE_Pos      (11U)\n#define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */\n#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */\n#define CAN_IER_ERRIE_Pos      (15U)\n#define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */\n#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */\n#define CAN_IER_WKUIE_Pos      (16U)\n#define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */\n#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */\n#define CAN_IER_SLKIE_Pos      (17U)\n#define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */\n#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)\n\n/********************  Bit definition for CAN_ESR register  *******************/\n#define CAN_ESR_EWGF_Pos       (0U)\n#define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */\n#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */\n#define CAN_ESR_EPVF_Pos       (1U)\n#define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */\n#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */\n#define CAN_ESR_BOFF_Pos       (2U)\n#define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */\n#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */\n\n#define CAN_ESR_LEC_Pos        (4U)\n#define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */\n#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */\n#define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */\n#define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */\n#define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */\n\n#define CAN_ESR_TEC_Pos        (16U)\n#define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */\n#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */\n#define CAN_ESR_REC_Pos        (24U)\n#define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */\n#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */\n\n/*******************  Bit definition for CAN_BTR register  ********************/\n#define CAN_BTR_BRP_Pos        (0U)\n#define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */\n#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */\n#define CAN_BTR_TS1_Pos        (16U)\n#define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */\n#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */\n#define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */\n#define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */\n#define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */\n#define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */\n#define CAN_BTR_TS2_Pos        (20U)\n#define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */\n#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */\n#define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */\n#define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */\n#define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */\n#define CAN_BTR_SJW_Pos        (24U)\n#define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */\n#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */\n#define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */\n#define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */\n#define CAN_BTR_LBKM_Pos       (30U)\n#define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */\n#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */\n#define CAN_BTR_SILM_Pos       (31U)\n#define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */\n#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */\n\n\n/*!<Mailbox registers */\n/******************  Bit definition for CAN_TI0R register  ********************/\n#define CAN_TI0R_TXRQ_Pos      (0U)\n#define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI0R_RTR_Pos       (1U)\n#define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI0R_IDE_Pos       (2U)\n#define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI0R_EXID_Pos      (3U)\n#define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI0R_STID_Pos      (21U)\n#define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/******************  Bit definition for CAN_TDT0R register  *******************/\n#define CAN_TDT0R_DLC_Pos      (0U)\n#define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT0R_TGT_Pos      (8U)\n#define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT0R_TIME_Pos     (16U)\n#define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/******************  Bit definition for CAN_TDL0R register  *******************/\n#define CAN_TDL0R_DATA0_Pos    (0U)\n#define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL0R_DATA1_Pos    (8U)\n#define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL0R_DATA2_Pos    (16U)\n#define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL0R_DATA3_Pos    (24U)\n#define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/******************  Bit definition for CAN_TDH0R register  *******************/\n#define CAN_TDH0R_DATA4_Pos    (0U)\n#define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH0R_DATA5_Pos    (8U)\n#define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH0R_DATA6_Pos    (16U)\n#define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH0R_DATA7_Pos    (24U)\n#define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI1R register  *******************/\n#define CAN_TI1R_TXRQ_Pos      (0U)\n#define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI1R_RTR_Pos       (1U)\n#define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI1R_IDE_Pos       (2U)\n#define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI1R_EXID_Pos      (3U)\n#define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI1R_STID_Pos      (21U)\n#define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT1R register  ******************/\n#define CAN_TDT1R_DLC_Pos      (0U)\n#define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT1R_TGT_Pos      (8U)\n#define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT1R_TIME_Pos     (16U)\n#define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL1R register  ******************/\n#define CAN_TDL1R_DATA0_Pos    (0U)\n#define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL1R_DATA1_Pos    (8U)\n#define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL1R_DATA2_Pos    (16U)\n#define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL1R_DATA3_Pos    (24U)\n#define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH1R register  ******************/\n#define CAN_TDH1R_DATA4_Pos    (0U)\n#define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH1R_DATA5_Pos    (8U)\n#define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH1R_DATA6_Pos    (16U)\n#define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH1R_DATA7_Pos    (24U)\n#define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI2R register  *******************/\n#define CAN_TI2R_TXRQ_Pos      (0U)\n#define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI2R_RTR_Pos       (1U)\n#define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI2R_IDE_Pos       (2U)\n#define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI2R_EXID_Pos      (3U)\n#define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_TI2R_STID_Pos      (21U)\n#define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT2R register  ******************/\n#define CAN_TDT2R_DLC_Pos      (0U)\n#define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT2R_TGT_Pos      (8U)\n#define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT2R_TIME_Pos     (16U)\n#define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL2R register  ******************/\n#define CAN_TDL2R_DATA0_Pos    (0U)\n#define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL2R_DATA1_Pos    (8U)\n#define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL2R_DATA2_Pos    (16U)\n#define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL2R_DATA3_Pos    (24U)\n#define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH2R register  ******************/\n#define CAN_TDH2R_DATA4_Pos    (0U)\n#define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH2R_DATA5_Pos    (8U)\n#define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH2R_DATA6_Pos    (16U)\n#define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH2R_DATA7_Pos    (24U)\n#define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI0R register  *******************/\n#define CAN_RI0R_RTR_Pos       (1U)\n#define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI0R_IDE_Pos       (2U)\n#define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI0R_EXID_Pos      (3U)\n#define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_RI0R_STID_Pos      (21U)\n#define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT0R register  ******************/\n#define CAN_RDT0R_DLC_Pos      (0U)\n#define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT0R_FMI_Pos      (8U)\n#define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT0R_TIME_Pos     (16U)\n#define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL0R register  ******************/\n#define CAN_RDL0R_DATA0_Pos    (0U)\n#define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL0R_DATA1_Pos    (8U)\n#define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL0R_DATA2_Pos    (16U)\n#define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL0R_DATA3_Pos    (24U)\n#define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH0R register  ******************/\n#define CAN_RDH0R_DATA4_Pos    (0U)\n#define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH0R_DATA5_Pos    (8U)\n#define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH0R_DATA6_Pos    (16U)\n#define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH0R_DATA7_Pos    (24U)\n#define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI1R register  *******************/\n#define CAN_RI1R_RTR_Pos       (1U)\n#define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI1R_IDE_Pos       (2U)\n#define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI1R_EXID_Pos      (3U)\n#define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_RI1R_STID_Pos      (21U)\n#define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT1R register  ******************/\n#define CAN_RDT1R_DLC_Pos      (0U)\n#define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT1R_FMI_Pos      (8U)\n#define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT1R_TIME_Pos     (16U)\n#define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL1R register  ******************/\n#define CAN_RDL1R_DATA0_Pos    (0U)\n#define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL1R_DATA1_Pos    (8U)\n#define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL1R_DATA2_Pos    (16U)\n#define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL1R_DATA3_Pos    (24U)\n#define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH1R register  ******************/\n#define CAN_RDH1R_DATA4_Pos    (0U)\n#define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH1R_DATA5_Pos    (8U)\n#define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH1R_DATA6_Pos    (16U)\n#define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH1R_DATA7_Pos    (24U)\n#define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*!<CAN filter registers */\n/*******************  Bit definition for CAN_FMR register  ********************/\n#define CAN_FMR_FINIT_Pos      (0U)\n#define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */\n#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */\n#define CAN_FMR_CAN2SB_Pos     (8U)\n#define CAN_FMR_CAN2SB_Msk     (0x3FUL << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */\n#define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */\n\n/*******************  Bit definition for CAN_FM1R register  *******************/\n#define CAN_FM1R_FBM_Pos       (0U)\n#define CAN_FM1R_FBM_Msk       (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */\n#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */\n#define CAN_FM1R_FBM0_Pos      (0U)\n#define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */\n#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */\n#define CAN_FM1R_FBM1_Pos      (1U)\n#define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */\n#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */\n#define CAN_FM1R_FBM2_Pos      (2U)\n#define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */\n#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */\n#define CAN_FM1R_FBM3_Pos      (3U)\n#define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */\n#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */\n#define CAN_FM1R_FBM4_Pos      (4U)\n#define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */\n#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */\n#define CAN_FM1R_FBM5_Pos      (5U)\n#define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */\n#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */\n#define CAN_FM1R_FBM6_Pos      (6U)\n#define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */\n#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */\n#define CAN_FM1R_FBM7_Pos      (7U)\n#define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */\n#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */\n#define CAN_FM1R_FBM8_Pos      (8U)\n#define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */\n#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */\n#define CAN_FM1R_FBM9_Pos      (9U)\n#define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */\n#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */\n#define CAN_FM1R_FBM10_Pos     (10U)\n#define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */\n#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */\n#define CAN_FM1R_FBM11_Pos     (11U)\n#define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */\n#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */\n#define CAN_FM1R_FBM12_Pos     (12U)\n#define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */\n#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */\n#define CAN_FM1R_FBM13_Pos     (13U)\n#define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */\n#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */\n#define CAN_FM1R_FBM14_Pos     (14U)\n#define CAN_FM1R_FBM14_Msk     (0x1UL << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */\n#define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */\n#define CAN_FM1R_FBM15_Pos     (15U)\n#define CAN_FM1R_FBM15_Msk     (0x1UL << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */\n#define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */\n#define CAN_FM1R_FBM16_Pos     (16U)\n#define CAN_FM1R_FBM16_Msk     (0x1UL << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */\n#define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */\n#define CAN_FM1R_FBM17_Pos     (17U)\n#define CAN_FM1R_FBM17_Msk     (0x1UL << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */\n#define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */\n#define CAN_FM1R_FBM18_Pos     (18U)\n#define CAN_FM1R_FBM18_Msk     (0x1UL << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */\n#define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */\n#define CAN_FM1R_FBM19_Pos     (19U)\n#define CAN_FM1R_FBM19_Msk     (0x1UL << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */\n#define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */\n#define CAN_FM1R_FBM20_Pos     (20U)\n#define CAN_FM1R_FBM20_Msk     (0x1UL << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */\n#define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */\n#define CAN_FM1R_FBM21_Pos     (21U)\n#define CAN_FM1R_FBM21_Msk     (0x1UL << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */\n#define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */\n#define CAN_FM1R_FBM22_Pos     (22U)\n#define CAN_FM1R_FBM22_Msk     (0x1UL << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */\n#define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */\n#define CAN_FM1R_FBM23_Pos     (23U)\n#define CAN_FM1R_FBM23_Msk     (0x1UL << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */\n#define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */\n#define CAN_FM1R_FBM24_Pos     (24U)\n#define CAN_FM1R_FBM24_Msk     (0x1UL << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */\n#define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */\n#define CAN_FM1R_FBM25_Pos     (25U)\n#define CAN_FM1R_FBM25_Msk     (0x1UL << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */\n#define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */\n#define CAN_FM1R_FBM26_Pos     (26U)\n#define CAN_FM1R_FBM26_Msk     (0x1UL << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */\n#define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */\n#define CAN_FM1R_FBM27_Pos     (27U)\n#define CAN_FM1R_FBM27_Msk     (0x1UL << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */\n#define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */\n\n/*******************  Bit definition for CAN_FS1R register  *******************/\n#define CAN_FS1R_FSC_Pos       (0U)\n#define CAN_FS1R_FSC_Msk       (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */\n#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */\n#define CAN_FS1R_FSC0_Pos      (0U)\n#define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */\n#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */\n#define CAN_FS1R_FSC1_Pos      (1U)\n#define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */\n#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */\n#define CAN_FS1R_FSC2_Pos      (2U)\n#define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */\n#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */\n#define CAN_FS1R_FSC3_Pos      (3U)\n#define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */\n#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */\n#define CAN_FS1R_FSC4_Pos      (4U)\n#define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */\n#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */\n#define CAN_FS1R_FSC5_Pos      (5U)\n#define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */\n#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */\n#define CAN_FS1R_FSC6_Pos      (6U)\n#define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */\n#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */\n#define CAN_FS1R_FSC7_Pos      (7U)\n#define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */\n#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */\n#define CAN_FS1R_FSC8_Pos      (8U)\n#define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */\n#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */\n#define CAN_FS1R_FSC9_Pos      (9U)\n#define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */\n#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */\n#define CAN_FS1R_FSC10_Pos     (10U)\n#define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */\n#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */\n#define CAN_FS1R_FSC11_Pos     (11U)\n#define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */\n#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */\n#define CAN_FS1R_FSC12_Pos     (12U)\n#define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */\n#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */\n#define CAN_FS1R_FSC13_Pos     (13U)\n#define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */\n#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */\n#define CAN_FS1R_FSC14_Pos     (14U)\n#define CAN_FS1R_FSC14_Msk     (0x1UL << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */\n#define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */\n#define CAN_FS1R_FSC15_Pos     (15U)\n#define CAN_FS1R_FSC15_Msk     (0x1UL << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */\n#define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */\n#define CAN_FS1R_FSC16_Pos     (16U)\n#define CAN_FS1R_FSC16_Msk     (0x1UL << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */\n#define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */\n#define CAN_FS1R_FSC17_Pos     (17U)\n#define CAN_FS1R_FSC17_Msk     (0x1UL << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */\n#define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */\n#define CAN_FS1R_FSC18_Pos     (18U)\n#define CAN_FS1R_FSC18_Msk     (0x1UL << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */\n#define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */\n#define CAN_FS1R_FSC19_Pos     (19U)\n#define CAN_FS1R_FSC19_Msk     (0x1UL << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */\n#define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */\n#define CAN_FS1R_FSC20_Pos     (20U)\n#define CAN_FS1R_FSC20_Msk     (0x1UL << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */\n#define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */\n#define CAN_FS1R_FSC21_Pos     (21U)\n#define CAN_FS1R_FSC21_Msk     (0x1UL << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */\n#define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */\n#define CAN_FS1R_FSC22_Pos     (22U)\n#define CAN_FS1R_FSC22_Msk     (0x1UL << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */\n#define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */\n#define CAN_FS1R_FSC23_Pos     (23U)\n#define CAN_FS1R_FSC23_Msk     (0x1UL << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */\n#define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */\n#define CAN_FS1R_FSC24_Pos     (24U)\n#define CAN_FS1R_FSC24_Msk     (0x1UL << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */\n#define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */\n#define CAN_FS1R_FSC25_Pos     (25U)\n#define CAN_FS1R_FSC25_Msk     (0x1UL << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */\n#define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */\n#define CAN_FS1R_FSC26_Pos     (26U)\n#define CAN_FS1R_FSC26_Msk     (0x1UL << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */\n#define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */\n#define CAN_FS1R_FSC27_Pos     (27U)\n#define CAN_FS1R_FSC27_Msk     (0x1UL << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */\n#define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */\n\n/******************  Bit definition for CAN_FFA1R register  *******************/\n#define CAN_FFA1R_FFA_Pos      (0U)\n#define CAN_FFA1R_FFA_Msk      (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */\n#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */\n#define CAN_FFA1R_FFA0_Pos     (0U)\n#define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */\n#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */\n#define CAN_FFA1R_FFA1_Pos     (1U)\n#define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */\n#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */\n#define CAN_FFA1R_FFA2_Pos     (2U)\n#define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */\n#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */\n#define CAN_FFA1R_FFA3_Pos     (3U)\n#define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */\n#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */\n#define CAN_FFA1R_FFA4_Pos     (4U)\n#define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */\n#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */\n#define CAN_FFA1R_FFA5_Pos     (5U)\n#define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */\n#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */\n#define CAN_FFA1R_FFA6_Pos     (6U)\n#define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */\n#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */\n#define CAN_FFA1R_FFA7_Pos     (7U)\n#define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */\n#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */\n#define CAN_FFA1R_FFA8_Pos     (8U)\n#define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */\n#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */\n#define CAN_FFA1R_FFA9_Pos     (9U)\n#define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */\n#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */\n#define CAN_FFA1R_FFA10_Pos    (10U)\n#define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */\n#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */\n#define CAN_FFA1R_FFA11_Pos    (11U)\n#define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */\n#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */\n#define CAN_FFA1R_FFA12_Pos    (12U)\n#define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */\n#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */\n#define CAN_FFA1R_FFA13_Pos    (13U)\n#define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */\n#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */\n#define CAN_FFA1R_FFA14_Pos    (14U)\n#define CAN_FFA1R_FFA14_Msk    (0x1UL << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */\n#define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */\n#define CAN_FFA1R_FFA15_Pos    (15U)\n#define CAN_FFA1R_FFA15_Msk    (0x1UL << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */\n#define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */\n#define CAN_FFA1R_FFA16_Pos    (16U)\n#define CAN_FFA1R_FFA16_Msk    (0x1UL << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */\n#define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */\n#define CAN_FFA1R_FFA17_Pos    (17U)\n#define CAN_FFA1R_FFA17_Msk    (0x1UL << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */\n#define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */\n#define CAN_FFA1R_FFA18_Pos    (18U)\n#define CAN_FFA1R_FFA18_Msk    (0x1UL << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */\n#define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */\n#define CAN_FFA1R_FFA19_Pos    (19U)\n#define CAN_FFA1R_FFA19_Msk    (0x1UL << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */\n#define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */\n#define CAN_FFA1R_FFA20_Pos    (20U)\n#define CAN_FFA1R_FFA20_Msk    (0x1UL << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */\n#define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */\n#define CAN_FFA1R_FFA21_Pos    (21U)\n#define CAN_FFA1R_FFA21_Msk    (0x1UL << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */\n#define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */\n#define CAN_FFA1R_FFA22_Pos    (22U)\n#define CAN_FFA1R_FFA22_Msk    (0x1UL << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */\n#define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */\n#define CAN_FFA1R_FFA23_Pos    (23U)\n#define CAN_FFA1R_FFA23_Msk    (0x1UL << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */\n#define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */\n#define CAN_FFA1R_FFA24_Pos    (24U)\n#define CAN_FFA1R_FFA24_Msk    (0x1UL << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */\n#define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */\n#define CAN_FFA1R_FFA25_Pos    (25U)\n#define CAN_FFA1R_FFA25_Msk    (0x1UL << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */\n#define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */\n#define CAN_FFA1R_FFA26_Pos    (26U)\n#define CAN_FFA1R_FFA26_Msk    (0x1UL << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */\n#define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */\n#define CAN_FFA1R_FFA27_Pos    (27U)\n#define CAN_FFA1R_FFA27_Msk    (0x1UL << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */\n#define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */\n\n/*******************  Bit definition for CAN_FA1R register  *******************/\n#define CAN_FA1R_FACT_Pos      (0U)\n#define CAN_FA1R_FACT_Msk      (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */\n#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */\n#define CAN_FA1R_FACT0_Pos     (0U)\n#define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */\n#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */\n#define CAN_FA1R_FACT1_Pos     (1U)\n#define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */\n#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */\n#define CAN_FA1R_FACT2_Pos     (2U)\n#define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */\n#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */\n#define CAN_FA1R_FACT3_Pos     (3U)\n#define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */\n#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */\n#define CAN_FA1R_FACT4_Pos     (4U)\n#define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */\n#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */\n#define CAN_FA1R_FACT5_Pos     (5U)\n#define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */\n#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */\n#define CAN_FA1R_FACT6_Pos     (6U)\n#define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */\n#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */\n#define CAN_FA1R_FACT7_Pos     (7U)\n#define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */\n#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */\n#define CAN_FA1R_FACT8_Pos     (8U)\n#define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */\n#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */\n#define CAN_FA1R_FACT9_Pos     (9U)\n#define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */\n#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */\n#define CAN_FA1R_FACT10_Pos    (10U)\n#define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */\n#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */\n#define CAN_FA1R_FACT11_Pos    (11U)\n#define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */\n#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */\n#define CAN_FA1R_FACT12_Pos    (12U)\n#define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */\n#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */\n#define CAN_FA1R_FACT13_Pos    (13U)\n#define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */\n#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */\n#define CAN_FA1R_FACT14_Pos    (14U)\n#define CAN_FA1R_FACT14_Msk    (0x1UL << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */\n#define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */\n#define CAN_FA1R_FACT15_Pos    (15U)\n#define CAN_FA1R_FACT15_Msk    (0x1UL << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */\n#define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */\n#define CAN_FA1R_FACT16_Pos    (16U)\n#define CAN_FA1R_FACT16_Msk    (0x1UL << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */\n#define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */\n#define CAN_FA1R_FACT17_Pos    (17U)\n#define CAN_FA1R_FACT17_Msk    (0x1UL << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */\n#define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */\n#define CAN_FA1R_FACT18_Pos    (18U)\n#define CAN_FA1R_FACT18_Msk    (0x1UL << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */\n#define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */\n#define CAN_FA1R_FACT19_Pos    (19U)\n#define CAN_FA1R_FACT19_Msk    (0x1UL << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */\n#define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */\n#define CAN_FA1R_FACT20_Pos    (20U)\n#define CAN_FA1R_FACT20_Msk    (0x1UL << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */\n#define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */\n#define CAN_FA1R_FACT21_Pos    (21U)\n#define CAN_FA1R_FACT21_Msk    (0x1UL << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */\n#define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */\n#define CAN_FA1R_FACT22_Pos    (22U)\n#define CAN_FA1R_FACT22_Msk    (0x1UL << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */\n#define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */\n#define CAN_FA1R_FACT23_Pos    (23U)\n#define CAN_FA1R_FACT23_Msk    (0x1UL << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */\n#define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */\n#define CAN_FA1R_FACT24_Pos    (24U)\n#define CAN_FA1R_FACT24_Msk    (0x1UL << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */\n#define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */\n#define CAN_FA1R_FACT25_Pos    (25U)\n#define CAN_FA1R_FACT25_Msk    (0x1UL << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */\n#define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */\n#define CAN_FA1R_FACT26_Pos    (26U)\n#define CAN_FA1R_FACT26_Msk    (0x1UL << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */\n#define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */\n#define CAN_FA1R_FACT27_Pos    (27U)\n#define CAN_FA1R_FACT27_Msk    (0x1UL << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */\n#define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */\n\n\n/*******************  Bit definition for CAN_F0R1 register  *******************/\n#define CAN_F0R1_FB0_Pos       (0U)\n#define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R1_FB1_Pos       (1U)\n#define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R1_FB2_Pos       (2U)\n#define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R1_FB3_Pos       (3U)\n#define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R1_FB4_Pos       (4U)\n#define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R1_FB5_Pos       (5U)\n#define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R1_FB6_Pos       (6U)\n#define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R1_FB7_Pos       (7U)\n#define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R1_FB8_Pos       (8U)\n#define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R1_FB9_Pos       (9U)\n#define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R1_FB10_Pos      (10U)\n#define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R1_FB11_Pos      (11U)\n#define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R1_FB12_Pos      (12U)\n#define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R1_FB13_Pos      (13U)\n#define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R1_FB14_Pos      (14U)\n#define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R1_FB15_Pos      (15U)\n#define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R1_FB16_Pos      (16U)\n#define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R1_FB17_Pos      (17U)\n#define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R1_FB18_Pos      (18U)\n#define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R1_FB19_Pos      (19U)\n#define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R1_FB20_Pos      (20U)\n#define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R1_FB21_Pos      (21U)\n#define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R1_FB22_Pos      (22U)\n#define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R1_FB23_Pos      (23U)\n#define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R1_FB24_Pos      (24U)\n#define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R1_FB25_Pos      (25U)\n#define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R1_FB26_Pos      (26U)\n#define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R1_FB27_Pos      (27U)\n#define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R1_FB28_Pos      (28U)\n#define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R1_FB29_Pos      (29U)\n#define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R1_FB30_Pos      (30U)\n#define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R1_FB31_Pos      (31U)\n#define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R1 register  *******************/\n#define CAN_F1R1_FB0_Pos       (0U)\n#define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R1_FB1_Pos       (1U)\n#define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R1_FB2_Pos       (2U)\n#define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R1_FB3_Pos       (3U)\n#define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R1_FB4_Pos       (4U)\n#define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R1_FB5_Pos       (5U)\n#define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R1_FB6_Pos       (6U)\n#define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R1_FB7_Pos       (7U)\n#define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R1_FB8_Pos       (8U)\n#define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R1_FB9_Pos       (9U)\n#define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R1_FB10_Pos      (10U)\n#define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R1_FB11_Pos      (11U)\n#define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R1_FB12_Pos      (12U)\n#define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R1_FB13_Pos      (13U)\n#define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R1_FB14_Pos      (14U)\n#define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R1_FB15_Pos      (15U)\n#define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R1_FB16_Pos      (16U)\n#define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R1_FB17_Pos      (17U)\n#define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R1_FB18_Pos      (18U)\n#define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R1_FB19_Pos      (19U)\n#define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R1_FB20_Pos      (20U)\n#define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R1_FB21_Pos      (21U)\n#define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R1_FB22_Pos      (22U)\n#define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R1_FB23_Pos      (23U)\n#define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R1_FB24_Pos      (24U)\n#define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R1_FB25_Pos      (25U)\n#define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R1_FB26_Pos      (26U)\n#define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R1_FB27_Pos      (27U)\n#define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R1_FB28_Pos      (28U)\n#define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R1_FB29_Pos      (29U)\n#define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R1_FB30_Pos      (30U)\n#define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R1_FB31_Pos      (31U)\n#define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R1 register  *******************/\n#define CAN_F2R1_FB0_Pos       (0U)\n#define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R1_FB1_Pos       (1U)\n#define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R1_FB2_Pos       (2U)\n#define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R1_FB3_Pos       (3U)\n#define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R1_FB4_Pos       (4U)\n#define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R1_FB5_Pos       (5U)\n#define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R1_FB6_Pos       (6U)\n#define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R1_FB7_Pos       (7U)\n#define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R1_FB8_Pos       (8U)\n#define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R1_FB9_Pos       (9U)\n#define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R1_FB10_Pos      (10U)\n#define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R1_FB11_Pos      (11U)\n#define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R1_FB12_Pos      (12U)\n#define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R1_FB13_Pos      (13U)\n#define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R1_FB14_Pos      (14U)\n#define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R1_FB15_Pos      (15U)\n#define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R1_FB16_Pos      (16U)\n#define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R1_FB17_Pos      (17U)\n#define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R1_FB18_Pos      (18U)\n#define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R1_FB19_Pos      (19U)\n#define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R1_FB20_Pos      (20U)\n#define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R1_FB21_Pos      (21U)\n#define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R1_FB22_Pos      (22U)\n#define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R1_FB23_Pos      (23U)\n#define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R1_FB24_Pos      (24U)\n#define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R1_FB25_Pos      (25U)\n#define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R1_FB26_Pos      (26U)\n#define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R1_FB27_Pos      (27U)\n#define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R1_FB28_Pos      (28U)\n#define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R1_FB29_Pos      (29U)\n#define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R1_FB30_Pos      (30U)\n#define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R1_FB31_Pos      (31U)\n#define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R1 register  *******************/\n#define CAN_F3R1_FB0_Pos       (0U)\n#define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R1_FB1_Pos       (1U)\n#define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R1_FB2_Pos       (2U)\n#define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R1_FB3_Pos       (3U)\n#define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R1_FB4_Pos       (4U)\n#define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R1_FB5_Pos       (5U)\n#define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R1_FB6_Pos       (6U)\n#define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R1_FB7_Pos       (7U)\n#define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R1_FB8_Pos       (8U)\n#define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R1_FB9_Pos       (9U)\n#define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R1_FB10_Pos      (10U)\n#define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R1_FB11_Pos      (11U)\n#define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R1_FB12_Pos      (12U)\n#define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R1_FB13_Pos      (13U)\n#define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R1_FB14_Pos      (14U)\n#define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R1_FB15_Pos      (15U)\n#define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R1_FB16_Pos      (16U)\n#define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R1_FB17_Pos      (17U)\n#define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R1_FB18_Pos      (18U)\n#define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R1_FB19_Pos      (19U)\n#define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R1_FB20_Pos      (20U)\n#define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R1_FB21_Pos      (21U)\n#define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R1_FB22_Pos      (22U)\n#define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R1_FB23_Pos      (23U)\n#define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R1_FB24_Pos      (24U)\n#define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R1_FB25_Pos      (25U)\n#define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R1_FB26_Pos      (26U)\n#define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R1_FB27_Pos      (27U)\n#define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R1_FB28_Pos      (28U)\n#define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R1_FB29_Pos      (29U)\n#define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R1_FB30_Pos      (30U)\n#define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R1_FB31_Pos      (31U)\n#define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R1 register  *******************/\n#define CAN_F4R1_FB0_Pos       (0U)\n#define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R1_FB1_Pos       (1U)\n#define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R1_FB2_Pos       (2U)\n#define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R1_FB3_Pos       (3U)\n#define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R1_FB4_Pos       (4U)\n#define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R1_FB5_Pos       (5U)\n#define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R1_FB6_Pos       (6U)\n#define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R1_FB7_Pos       (7U)\n#define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R1_FB8_Pos       (8U)\n#define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R1_FB9_Pos       (9U)\n#define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R1_FB10_Pos      (10U)\n#define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R1_FB11_Pos      (11U)\n#define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R1_FB12_Pos      (12U)\n#define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R1_FB13_Pos      (13U)\n#define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R1_FB14_Pos      (14U)\n#define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R1_FB15_Pos      (15U)\n#define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R1_FB16_Pos      (16U)\n#define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R1_FB17_Pos      (17U)\n#define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R1_FB18_Pos      (18U)\n#define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R1_FB19_Pos      (19U)\n#define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R1_FB20_Pos      (20U)\n#define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R1_FB21_Pos      (21U)\n#define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R1_FB22_Pos      (22U)\n#define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R1_FB23_Pos      (23U)\n#define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R1_FB24_Pos      (24U)\n#define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R1_FB25_Pos      (25U)\n#define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R1_FB26_Pos      (26U)\n#define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R1_FB27_Pos      (27U)\n#define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R1_FB28_Pos      (28U)\n#define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R1_FB29_Pos      (29U)\n#define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R1_FB30_Pos      (30U)\n#define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R1_FB31_Pos      (31U)\n#define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R1 register  *******************/\n#define CAN_F5R1_FB0_Pos       (0U)\n#define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R1_FB1_Pos       (1U)\n#define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R1_FB2_Pos       (2U)\n#define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R1_FB3_Pos       (3U)\n#define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R1_FB4_Pos       (4U)\n#define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R1_FB5_Pos       (5U)\n#define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R1_FB6_Pos       (6U)\n#define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R1_FB7_Pos       (7U)\n#define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R1_FB8_Pos       (8U)\n#define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R1_FB9_Pos       (9U)\n#define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R1_FB10_Pos      (10U)\n#define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R1_FB11_Pos      (11U)\n#define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R1_FB12_Pos      (12U)\n#define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R1_FB13_Pos      (13U)\n#define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R1_FB14_Pos      (14U)\n#define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R1_FB15_Pos      (15U)\n#define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R1_FB16_Pos      (16U)\n#define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R1_FB17_Pos      (17U)\n#define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R1_FB18_Pos      (18U)\n#define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R1_FB19_Pos      (19U)\n#define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R1_FB20_Pos      (20U)\n#define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R1_FB21_Pos      (21U)\n#define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R1_FB22_Pos      (22U)\n#define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R1_FB23_Pos      (23U)\n#define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R1_FB24_Pos      (24U)\n#define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R1_FB25_Pos      (25U)\n#define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R1_FB26_Pos      (26U)\n#define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R1_FB27_Pos      (27U)\n#define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R1_FB28_Pos      (28U)\n#define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R1_FB29_Pos      (29U)\n#define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R1_FB30_Pos      (30U)\n#define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R1_FB31_Pos      (31U)\n#define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R1 register  *******************/\n#define CAN_F6R1_FB0_Pos       (0U)\n#define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R1_FB1_Pos       (1U)\n#define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R1_FB2_Pos       (2U)\n#define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R1_FB3_Pos       (3U)\n#define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R1_FB4_Pos       (4U)\n#define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R1_FB5_Pos       (5U)\n#define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R1_FB6_Pos       (6U)\n#define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R1_FB7_Pos       (7U)\n#define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R1_FB8_Pos       (8U)\n#define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R1_FB9_Pos       (9U)\n#define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R1_FB10_Pos      (10U)\n#define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R1_FB11_Pos      (11U)\n#define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R1_FB12_Pos      (12U)\n#define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R1_FB13_Pos      (13U)\n#define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R1_FB14_Pos      (14U)\n#define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R1_FB15_Pos      (15U)\n#define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R1_FB16_Pos      (16U)\n#define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R1_FB17_Pos      (17U)\n#define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R1_FB18_Pos      (18U)\n#define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R1_FB19_Pos      (19U)\n#define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R1_FB20_Pos      (20U)\n#define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R1_FB21_Pos      (21U)\n#define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R1_FB22_Pos      (22U)\n#define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R1_FB23_Pos      (23U)\n#define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R1_FB24_Pos      (24U)\n#define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R1_FB25_Pos      (25U)\n#define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R1_FB26_Pos      (26U)\n#define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R1_FB27_Pos      (27U)\n#define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R1_FB28_Pos      (28U)\n#define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R1_FB29_Pos      (29U)\n#define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R1_FB30_Pos      (30U)\n#define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R1_FB31_Pos      (31U)\n#define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R1 register  *******************/\n#define CAN_F7R1_FB0_Pos       (0U)\n#define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R1_FB1_Pos       (1U)\n#define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R1_FB2_Pos       (2U)\n#define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R1_FB3_Pos       (3U)\n#define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R1_FB4_Pos       (4U)\n#define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R1_FB5_Pos       (5U)\n#define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R1_FB6_Pos       (6U)\n#define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R1_FB7_Pos       (7U)\n#define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R1_FB8_Pos       (8U)\n#define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R1_FB9_Pos       (9U)\n#define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R1_FB10_Pos      (10U)\n#define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R1_FB11_Pos      (11U)\n#define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R1_FB12_Pos      (12U)\n#define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R1_FB13_Pos      (13U)\n#define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R1_FB14_Pos      (14U)\n#define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R1_FB15_Pos      (15U)\n#define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R1_FB16_Pos      (16U)\n#define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R1_FB17_Pos      (17U)\n#define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R1_FB18_Pos      (18U)\n#define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R1_FB19_Pos      (19U)\n#define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R1_FB20_Pos      (20U)\n#define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R1_FB21_Pos      (21U)\n#define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R1_FB22_Pos      (22U)\n#define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R1_FB23_Pos      (23U)\n#define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R1_FB24_Pos      (24U)\n#define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R1_FB25_Pos      (25U)\n#define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R1_FB26_Pos      (26U)\n#define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R1_FB27_Pos      (27U)\n#define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R1_FB28_Pos      (28U)\n#define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R1_FB29_Pos      (29U)\n#define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R1_FB30_Pos      (30U)\n#define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R1_FB31_Pos      (31U)\n#define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R1 register  *******************/\n#define CAN_F8R1_FB0_Pos       (0U)\n#define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R1_FB1_Pos       (1U)\n#define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R1_FB2_Pos       (2U)\n#define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R1_FB3_Pos       (3U)\n#define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R1_FB4_Pos       (4U)\n#define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R1_FB5_Pos       (5U)\n#define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R1_FB6_Pos       (6U)\n#define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R1_FB7_Pos       (7U)\n#define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R1_FB8_Pos       (8U)\n#define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R1_FB9_Pos       (9U)\n#define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R1_FB10_Pos      (10U)\n#define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R1_FB11_Pos      (11U)\n#define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R1_FB12_Pos      (12U)\n#define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R1_FB13_Pos      (13U)\n#define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R1_FB14_Pos      (14U)\n#define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R1_FB15_Pos      (15U)\n#define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R1_FB16_Pos      (16U)\n#define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R1_FB17_Pos      (17U)\n#define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R1_FB18_Pos      (18U)\n#define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R1_FB19_Pos      (19U)\n#define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R1_FB20_Pos      (20U)\n#define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R1_FB21_Pos      (21U)\n#define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R1_FB22_Pos      (22U)\n#define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R1_FB23_Pos      (23U)\n#define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R1_FB24_Pos      (24U)\n#define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R1_FB25_Pos      (25U)\n#define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R1_FB26_Pos      (26U)\n#define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R1_FB27_Pos      (27U)\n#define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R1_FB28_Pos      (28U)\n#define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R1_FB29_Pos      (29U)\n#define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R1_FB30_Pos      (30U)\n#define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R1_FB31_Pos      (31U)\n#define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R1 register  *******************/\n#define CAN_F9R1_FB0_Pos       (0U)\n#define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R1_FB1_Pos       (1U)\n#define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R1_FB2_Pos       (2U)\n#define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R1_FB3_Pos       (3U)\n#define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R1_FB4_Pos       (4U)\n#define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R1_FB5_Pos       (5U)\n#define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R1_FB6_Pos       (6U)\n#define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R1_FB7_Pos       (7U)\n#define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R1_FB8_Pos       (8U)\n#define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R1_FB9_Pos       (9U)\n#define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R1_FB10_Pos      (10U)\n#define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R1_FB11_Pos      (11U)\n#define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R1_FB12_Pos      (12U)\n#define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R1_FB13_Pos      (13U)\n#define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R1_FB14_Pos      (14U)\n#define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R1_FB15_Pos      (15U)\n#define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R1_FB16_Pos      (16U)\n#define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R1_FB17_Pos      (17U)\n#define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R1_FB18_Pos      (18U)\n#define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R1_FB19_Pos      (19U)\n#define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R1_FB20_Pos      (20U)\n#define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R1_FB21_Pos      (21U)\n#define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R1_FB22_Pos      (22U)\n#define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R1_FB23_Pos      (23U)\n#define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R1_FB24_Pos      (24U)\n#define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R1_FB25_Pos      (25U)\n#define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R1_FB26_Pos      (26U)\n#define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R1_FB27_Pos      (27U)\n#define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R1_FB28_Pos      (28U)\n#define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R1_FB29_Pos      (29U)\n#define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R1_FB30_Pos      (30U)\n#define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R1_FB31_Pos      (31U)\n#define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R1 register  ******************/\n#define CAN_F10R1_FB0_Pos      (0U)\n#define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R1_FB1_Pos      (1U)\n#define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R1_FB2_Pos      (2U)\n#define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R1_FB3_Pos      (3U)\n#define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R1_FB4_Pos      (4U)\n#define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R1_FB5_Pos      (5U)\n#define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R1_FB6_Pos      (6U)\n#define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R1_FB7_Pos      (7U)\n#define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R1_FB8_Pos      (8U)\n#define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R1_FB9_Pos      (9U)\n#define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R1_FB10_Pos     (10U)\n#define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R1_FB11_Pos     (11U)\n#define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R1_FB12_Pos     (12U)\n#define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R1_FB13_Pos     (13U)\n#define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R1_FB14_Pos     (14U)\n#define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R1_FB15_Pos     (15U)\n#define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R1_FB16_Pos     (16U)\n#define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R1_FB17_Pos     (17U)\n#define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R1_FB18_Pos     (18U)\n#define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R1_FB19_Pos     (19U)\n#define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R1_FB20_Pos     (20U)\n#define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R1_FB21_Pos     (21U)\n#define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R1_FB22_Pos     (22U)\n#define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R1_FB23_Pos     (23U)\n#define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R1_FB24_Pos     (24U)\n#define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R1_FB25_Pos     (25U)\n#define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R1_FB26_Pos     (26U)\n#define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R1_FB27_Pos     (27U)\n#define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R1_FB28_Pos     (28U)\n#define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R1_FB29_Pos     (29U)\n#define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R1_FB30_Pos     (30U)\n#define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R1_FB31_Pos     (31U)\n#define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R1 register  ******************/\n#define CAN_F11R1_FB0_Pos      (0U)\n#define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R1_FB1_Pos      (1U)\n#define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R1_FB2_Pos      (2U)\n#define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R1_FB3_Pos      (3U)\n#define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R1_FB4_Pos      (4U)\n#define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R1_FB5_Pos      (5U)\n#define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R1_FB6_Pos      (6U)\n#define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R1_FB7_Pos      (7U)\n#define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R1_FB8_Pos      (8U)\n#define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R1_FB9_Pos      (9U)\n#define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R1_FB10_Pos     (10U)\n#define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R1_FB11_Pos     (11U)\n#define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R1_FB12_Pos     (12U)\n#define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R1_FB13_Pos     (13U)\n#define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R1_FB14_Pos     (14U)\n#define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R1_FB15_Pos     (15U)\n#define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R1_FB16_Pos     (16U)\n#define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R1_FB17_Pos     (17U)\n#define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R1_FB18_Pos     (18U)\n#define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R1_FB19_Pos     (19U)\n#define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R1_FB20_Pos     (20U)\n#define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R1_FB21_Pos     (21U)\n#define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R1_FB22_Pos     (22U)\n#define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R1_FB23_Pos     (23U)\n#define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R1_FB24_Pos     (24U)\n#define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R1_FB25_Pos     (25U)\n#define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R1_FB26_Pos     (26U)\n#define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R1_FB27_Pos     (27U)\n#define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R1_FB28_Pos     (28U)\n#define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R1_FB29_Pos     (29U)\n#define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R1_FB30_Pos     (30U)\n#define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R1_FB31_Pos     (31U)\n#define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R1 register  ******************/\n#define CAN_F12R1_FB0_Pos      (0U)\n#define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R1_FB1_Pos      (1U)\n#define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R1_FB2_Pos      (2U)\n#define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R1_FB3_Pos      (3U)\n#define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R1_FB4_Pos      (4U)\n#define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R1_FB5_Pos      (5U)\n#define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R1_FB6_Pos      (6U)\n#define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R1_FB7_Pos      (7U)\n#define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R1_FB8_Pos      (8U)\n#define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R1_FB9_Pos      (9U)\n#define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R1_FB10_Pos     (10U)\n#define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R1_FB11_Pos     (11U)\n#define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R1_FB12_Pos     (12U)\n#define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R1_FB13_Pos     (13U)\n#define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R1_FB14_Pos     (14U)\n#define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R1_FB15_Pos     (15U)\n#define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R1_FB16_Pos     (16U)\n#define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R1_FB17_Pos     (17U)\n#define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R1_FB18_Pos     (18U)\n#define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R1_FB19_Pos     (19U)\n#define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R1_FB20_Pos     (20U)\n#define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R1_FB21_Pos     (21U)\n#define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R1_FB22_Pos     (22U)\n#define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R1_FB23_Pos     (23U)\n#define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R1_FB24_Pos     (24U)\n#define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R1_FB25_Pos     (25U)\n#define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R1_FB26_Pos     (26U)\n#define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R1_FB27_Pos     (27U)\n#define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R1_FB28_Pos     (28U)\n#define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R1_FB29_Pos     (29U)\n#define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R1_FB30_Pos     (30U)\n#define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R1_FB31_Pos     (31U)\n#define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R1 register  ******************/\n#define CAN_F13R1_FB0_Pos      (0U)\n#define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R1_FB1_Pos      (1U)\n#define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R1_FB2_Pos      (2U)\n#define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R1_FB3_Pos      (3U)\n#define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R1_FB4_Pos      (4U)\n#define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R1_FB5_Pos      (5U)\n#define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R1_FB6_Pos      (6U)\n#define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R1_FB7_Pos      (7U)\n#define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R1_FB8_Pos      (8U)\n#define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R1_FB9_Pos      (9U)\n#define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R1_FB10_Pos     (10U)\n#define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R1_FB11_Pos     (11U)\n#define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R1_FB12_Pos     (12U)\n#define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R1_FB13_Pos     (13U)\n#define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R1_FB14_Pos     (14U)\n#define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R1_FB15_Pos     (15U)\n#define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R1_FB16_Pos     (16U)\n#define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R1_FB17_Pos     (17U)\n#define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R1_FB18_Pos     (18U)\n#define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R1_FB19_Pos     (19U)\n#define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R1_FB20_Pos     (20U)\n#define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R1_FB21_Pos     (21U)\n#define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R1_FB22_Pos     (22U)\n#define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R1_FB23_Pos     (23U)\n#define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R1_FB24_Pos     (24U)\n#define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R1_FB25_Pos     (25U)\n#define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R1_FB26_Pos     (26U)\n#define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R1_FB27_Pos     (27U)\n#define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R1_FB28_Pos     (28U)\n#define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R1_FB29_Pos     (29U)\n#define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R1_FB30_Pos     (30U)\n#define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R1_FB31_Pos     (31U)\n#define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F0R2 register  *******************/\n#define CAN_F0R2_FB0_Pos       (0U)\n#define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R2_FB1_Pos       (1U)\n#define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R2_FB2_Pos       (2U)\n#define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R2_FB3_Pos       (3U)\n#define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R2_FB4_Pos       (4U)\n#define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R2_FB5_Pos       (5U)\n#define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R2_FB6_Pos       (6U)\n#define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R2_FB7_Pos       (7U)\n#define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R2_FB8_Pos       (8U)\n#define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R2_FB9_Pos       (9U)\n#define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R2_FB10_Pos      (10U)\n#define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R2_FB11_Pos      (11U)\n#define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R2_FB12_Pos      (12U)\n#define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R2_FB13_Pos      (13U)\n#define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R2_FB14_Pos      (14U)\n#define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R2_FB15_Pos      (15U)\n#define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R2_FB16_Pos      (16U)\n#define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R2_FB17_Pos      (17U)\n#define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R2_FB18_Pos      (18U)\n#define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R2_FB19_Pos      (19U)\n#define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R2_FB20_Pos      (20U)\n#define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R2_FB21_Pos      (21U)\n#define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R2_FB22_Pos      (22U)\n#define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R2_FB23_Pos      (23U)\n#define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R2_FB24_Pos      (24U)\n#define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R2_FB25_Pos      (25U)\n#define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R2_FB26_Pos      (26U)\n#define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R2_FB27_Pos      (27U)\n#define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R2_FB28_Pos      (28U)\n#define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R2_FB29_Pos      (29U)\n#define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R2_FB30_Pos      (30U)\n#define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R2_FB31_Pos      (31U)\n#define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R2 register  *******************/\n#define CAN_F1R2_FB0_Pos       (0U)\n#define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R2_FB1_Pos       (1U)\n#define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R2_FB2_Pos       (2U)\n#define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R2_FB3_Pos       (3U)\n#define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R2_FB4_Pos       (4U)\n#define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R2_FB5_Pos       (5U)\n#define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R2_FB6_Pos       (6U)\n#define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R2_FB7_Pos       (7U)\n#define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R2_FB8_Pos       (8U)\n#define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R2_FB9_Pos       (9U)\n#define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R2_FB10_Pos      (10U)\n#define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R2_FB11_Pos      (11U)\n#define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R2_FB12_Pos      (12U)\n#define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R2_FB13_Pos      (13U)\n#define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R2_FB14_Pos      (14U)\n#define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R2_FB15_Pos      (15U)\n#define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R2_FB16_Pos      (16U)\n#define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R2_FB17_Pos      (17U)\n#define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R2_FB18_Pos      (18U)\n#define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R2_FB19_Pos      (19U)\n#define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R2_FB20_Pos      (20U)\n#define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R2_FB21_Pos      (21U)\n#define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R2_FB22_Pos      (22U)\n#define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R2_FB23_Pos      (23U)\n#define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R2_FB24_Pos      (24U)\n#define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R2_FB25_Pos      (25U)\n#define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R2_FB26_Pos      (26U)\n#define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R2_FB27_Pos      (27U)\n#define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R2_FB28_Pos      (28U)\n#define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R2_FB29_Pos      (29U)\n#define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R2_FB30_Pos      (30U)\n#define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R2_FB31_Pos      (31U)\n#define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R2 register  *******************/\n#define CAN_F2R2_FB0_Pos       (0U)\n#define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R2_FB1_Pos       (1U)\n#define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R2_FB2_Pos       (2U)\n#define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R2_FB3_Pos       (3U)\n#define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R2_FB4_Pos       (4U)\n#define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R2_FB5_Pos       (5U)\n#define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R2_FB6_Pos       (6U)\n#define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R2_FB7_Pos       (7U)\n#define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R2_FB8_Pos       (8U)\n#define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R2_FB9_Pos       (9U)\n#define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R2_FB10_Pos      (10U)\n#define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R2_FB11_Pos      (11U)\n#define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R2_FB12_Pos      (12U)\n#define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R2_FB13_Pos      (13U)\n#define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R2_FB14_Pos      (14U)\n#define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R2_FB15_Pos      (15U)\n#define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R2_FB16_Pos      (16U)\n#define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R2_FB17_Pos      (17U)\n#define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R2_FB18_Pos      (18U)\n#define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R2_FB19_Pos      (19U)\n#define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R2_FB20_Pos      (20U)\n#define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R2_FB21_Pos      (21U)\n#define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R2_FB22_Pos      (22U)\n#define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R2_FB23_Pos      (23U)\n#define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R2_FB24_Pos      (24U)\n#define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R2_FB25_Pos      (25U)\n#define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R2_FB26_Pos      (26U)\n#define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R2_FB27_Pos      (27U)\n#define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R2_FB28_Pos      (28U)\n#define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R2_FB29_Pos      (29U)\n#define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R2_FB30_Pos      (30U)\n#define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R2_FB31_Pos      (31U)\n#define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R2 register  *******************/\n#define CAN_F3R2_FB0_Pos       (0U)\n#define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R2_FB1_Pos       (1U)\n#define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R2_FB2_Pos       (2U)\n#define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R2_FB3_Pos       (3U)\n#define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R2_FB4_Pos       (4U)\n#define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R2_FB5_Pos       (5U)\n#define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R2_FB6_Pos       (6U)\n#define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R2_FB7_Pos       (7U)\n#define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R2_FB8_Pos       (8U)\n#define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R2_FB9_Pos       (9U)\n#define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R2_FB10_Pos      (10U)\n#define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R2_FB11_Pos      (11U)\n#define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R2_FB12_Pos      (12U)\n#define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R2_FB13_Pos      (13U)\n#define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R2_FB14_Pos      (14U)\n#define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R2_FB15_Pos      (15U)\n#define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R2_FB16_Pos      (16U)\n#define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R2_FB17_Pos      (17U)\n#define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R2_FB18_Pos      (18U)\n#define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R2_FB19_Pos      (19U)\n#define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R2_FB20_Pos      (20U)\n#define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R2_FB21_Pos      (21U)\n#define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R2_FB22_Pos      (22U)\n#define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R2_FB23_Pos      (23U)\n#define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R2_FB24_Pos      (24U)\n#define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R2_FB25_Pos      (25U)\n#define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R2_FB26_Pos      (26U)\n#define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R2_FB27_Pos      (27U)\n#define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R2_FB28_Pos      (28U)\n#define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R2_FB29_Pos      (29U)\n#define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R2_FB30_Pos      (30U)\n#define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R2_FB31_Pos      (31U)\n#define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R2 register  *******************/\n#define CAN_F4R2_FB0_Pos       (0U)\n#define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R2_FB1_Pos       (1U)\n#define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R2_FB2_Pos       (2U)\n#define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R2_FB3_Pos       (3U)\n#define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R2_FB4_Pos       (4U)\n#define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R2_FB5_Pos       (5U)\n#define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R2_FB6_Pos       (6U)\n#define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R2_FB7_Pos       (7U)\n#define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R2_FB8_Pos       (8U)\n#define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R2_FB9_Pos       (9U)\n#define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R2_FB10_Pos      (10U)\n#define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R2_FB11_Pos      (11U)\n#define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R2_FB12_Pos      (12U)\n#define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R2_FB13_Pos      (13U)\n#define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R2_FB14_Pos      (14U)\n#define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R2_FB15_Pos      (15U)\n#define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R2_FB16_Pos      (16U)\n#define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R2_FB17_Pos      (17U)\n#define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R2_FB18_Pos      (18U)\n#define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R2_FB19_Pos      (19U)\n#define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R2_FB20_Pos      (20U)\n#define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R2_FB21_Pos      (21U)\n#define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R2_FB22_Pos      (22U)\n#define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R2_FB23_Pos      (23U)\n#define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R2_FB24_Pos      (24U)\n#define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R2_FB25_Pos      (25U)\n#define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R2_FB26_Pos      (26U)\n#define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R2_FB27_Pos      (27U)\n#define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R2_FB28_Pos      (28U)\n#define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R2_FB29_Pos      (29U)\n#define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R2_FB30_Pos      (30U)\n#define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R2_FB31_Pos      (31U)\n#define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R2 register  *******************/\n#define CAN_F5R2_FB0_Pos       (0U)\n#define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R2_FB1_Pos       (1U)\n#define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R2_FB2_Pos       (2U)\n#define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R2_FB3_Pos       (3U)\n#define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R2_FB4_Pos       (4U)\n#define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R2_FB5_Pos       (5U)\n#define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R2_FB6_Pos       (6U)\n#define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R2_FB7_Pos       (7U)\n#define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R2_FB8_Pos       (8U)\n#define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R2_FB9_Pos       (9U)\n#define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R2_FB10_Pos      (10U)\n#define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R2_FB11_Pos      (11U)\n#define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R2_FB12_Pos      (12U)\n#define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R2_FB13_Pos      (13U)\n#define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R2_FB14_Pos      (14U)\n#define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R2_FB15_Pos      (15U)\n#define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R2_FB16_Pos      (16U)\n#define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R2_FB17_Pos      (17U)\n#define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R2_FB18_Pos      (18U)\n#define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R2_FB19_Pos      (19U)\n#define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R2_FB20_Pos      (20U)\n#define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R2_FB21_Pos      (21U)\n#define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R2_FB22_Pos      (22U)\n#define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R2_FB23_Pos      (23U)\n#define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R2_FB24_Pos      (24U)\n#define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R2_FB25_Pos      (25U)\n#define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R2_FB26_Pos      (26U)\n#define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R2_FB27_Pos      (27U)\n#define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R2_FB28_Pos      (28U)\n#define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R2_FB29_Pos      (29U)\n#define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R2_FB30_Pos      (30U)\n#define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R2_FB31_Pos      (31U)\n#define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R2 register  *******************/\n#define CAN_F6R2_FB0_Pos       (0U)\n#define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R2_FB1_Pos       (1U)\n#define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R2_FB2_Pos       (2U)\n#define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R2_FB3_Pos       (3U)\n#define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R2_FB4_Pos       (4U)\n#define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R2_FB5_Pos       (5U)\n#define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R2_FB6_Pos       (6U)\n#define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R2_FB7_Pos       (7U)\n#define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R2_FB8_Pos       (8U)\n#define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R2_FB9_Pos       (9U)\n#define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R2_FB10_Pos      (10U)\n#define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R2_FB11_Pos      (11U)\n#define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R2_FB12_Pos      (12U)\n#define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R2_FB13_Pos      (13U)\n#define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R2_FB14_Pos      (14U)\n#define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R2_FB15_Pos      (15U)\n#define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R2_FB16_Pos      (16U)\n#define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R2_FB17_Pos      (17U)\n#define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R2_FB18_Pos      (18U)\n#define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R2_FB19_Pos      (19U)\n#define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R2_FB20_Pos      (20U)\n#define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R2_FB21_Pos      (21U)\n#define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R2_FB22_Pos      (22U)\n#define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R2_FB23_Pos      (23U)\n#define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R2_FB24_Pos      (24U)\n#define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R2_FB25_Pos      (25U)\n#define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R2_FB26_Pos      (26U)\n#define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R2_FB27_Pos      (27U)\n#define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R2_FB28_Pos      (28U)\n#define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R2_FB29_Pos      (29U)\n#define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R2_FB30_Pos      (30U)\n#define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R2_FB31_Pos      (31U)\n#define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R2 register  *******************/\n#define CAN_F7R2_FB0_Pos       (0U)\n#define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R2_FB1_Pos       (1U)\n#define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R2_FB2_Pos       (2U)\n#define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R2_FB3_Pos       (3U)\n#define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R2_FB4_Pos       (4U)\n#define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R2_FB5_Pos       (5U)\n#define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R2_FB6_Pos       (6U)\n#define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R2_FB7_Pos       (7U)\n#define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R2_FB8_Pos       (8U)\n#define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R2_FB9_Pos       (9U)\n#define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R2_FB10_Pos      (10U)\n#define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R2_FB11_Pos      (11U)\n#define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R2_FB12_Pos      (12U)\n#define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R2_FB13_Pos      (13U)\n#define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R2_FB14_Pos      (14U)\n#define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R2_FB15_Pos      (15U)\n#define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R2_FB16_Pos      (16U)\n#define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R2_FB17_Pos      (17U)\n#define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R2_FB18_Pos      (18U)\n#define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R2_FB19_Pos      (19U)\n#define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R2_FB20_Pos      (20U)\n#define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R2_FB21_Pos      (21U)\n#define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R2_FB22_Pos      (22U)\n#define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R2_FB23_Pos      (23U)\n#define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R2_FB24_Pos      (24U)\n#define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R2_FB25_Pos      (25U)\n#define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R2_FB26_Pos      (26U)\n#define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R2_FB27_Pos      (27U)\n#define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R2_FB28_Pos      (28U)\n#define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R2_FB29_Pos      (29U)\n#define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R2_FB30_Pos      (30U)\n#define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R2_FB31_Pos      (31U)\n#define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R2 register  *******************/\n#define CAN_F8R2_FB0_Pos       (0U)\n#define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R2_FB1_Pos       (1U)\n#define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R2_FB2_Pos       (2U)\n#define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R2_FB3_Pos       (3U)\n#define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R2_FB4_Pos       (4U)\n#define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R2_FB5_Pos       (5U)\n#define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R2_FB6_Pos       (6U)\n#define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R2_FB7_Pos       (7U)\n#define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R2_FB8_Pos       (8U)\n#define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R2_FB9_Pos       (9U)\n#define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R2_FB10_Pos      (10U)\n#define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R2_FB11_Pos      (11U)\n#define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R2_FB12_Pos      (12U)\n#define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R2_FB13_Pos      (13U)\n#define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R2_FB14_Pos      (14U)\n#define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R2_FB15_Pos      (15U)\n#define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R2_FB16_Pos      (16U)\n#define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R2_FB17_Pos      (17U)\n#define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R2_FB18_Pos      (18U)\n#define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R2_FB19_Pos      (19U)\n#define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R2_FB20_Pos      (20U)\n#define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R2_FB21_Pos      (21U)\n#define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R2_FB22_Pos      (22U)\n#define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R2_FB23_Pos      (23U)\n#define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R2_FB24_Pos      (24U)\n#define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R2_FB25_Pos      (25U)\n#define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R2_FB26_Pos      (26U)\n#define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R2_FB27_Pos      (27U)\n#define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R2_FB28_Pos      (28U)\n#define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R2_FB29_Pos      (29U)\n#define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R2_FB30_Pos      (30U)\n#define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R2_FB31_Pos      (31U)\n#define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R2 register  *******************/\n#define CAN_F9R2_FB0_Pos       (0U)\n#define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R2_FB1_Pos       (1U)\n#define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R2_FB2_Pos       (2U)\n#define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R2_FB3_Pos       (3U)\n#define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R2_FB4_Pos       (4U)\n#define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R2_FB5_Pos       (5U)\n#define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R2_FB6_Pos       (6U)\n#define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R2_FB7_Pos       (7U)\n#define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R2_FB8_Pos       (8U)\n#define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R2_FB9_Pos       (9U)\n#define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R2_FB10_Pos      (10U)\n#define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R2_FB11_Pos      (11U)\n#define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R2_FB12_Pos      (12U)\n#define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R2_FB13_Pos      (13U)\n#define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R2_FB14_Pos      (14U)\n#define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R2_FB15_Pos      (15U)\n#define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R2_FB16_Pos      (16U)\n#define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R2_FB17_Pos      (17U)\n#define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R2_FB18_Pos      (18U)\n#define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R2_FB19_Pos      (19U)\n#define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R2_FB20_Pos      (20U)\n#define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R2_FB21_Pos      (21U)\n#define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R2_FB22_Pos      (22U)\n#define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R2_FB23_Pos      (23U)\n#define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R2_FB24_Pos      (24U)\n#define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R2_FB25_Pos      (25U)\n#define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R2_FB26_Pos      (26U)\n#define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R2_FB27_Pos      (27U)\n#define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R2_FB28_Pos      (28U)\n#define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R2_FB29_Pos      (29U)\n#define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R2_FB30_Pos      (30U)\n#define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R2_FB31_Pos      (31U)\n#define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R2 register  ******************/\n#define CAN_F10R2_FB0_Pos      (0U)\n#define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R2_FB1_Pos      (1U)\n#define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R2_FB2_Pos      (2U)\n#define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R2_FB3_Pos      (3U)\n#define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R2_FB4_Pos      (4U)\n#define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R2_FB5_Pos      (5U)\n#define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R2_FB6_Pos      (6U)\n#define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R2_FB7_Pos      (7U)\n#define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R2_FB8_Pos      (8U)\n#define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R2_FB9_Pos      (9U)\n#define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R2_FB10_Pos     (10U)\n#define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R2_FB11_Pos     (11U)\n#define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R2_FB12_Pos     (12U)\n#define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R2_FB13_Pos     (13U)\n#define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R2_FB14_Pos     (14U)\n#define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R2_FB15_Pos     (15U)\n#define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R2_FB16_Pos     (16U)\n#define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R2_FB17_Pos     (17U)\n#define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R2_FB18_Pos     (18U)\n#define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R2_FB19_Pos     (19U)\n#define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R2_FB20_Pos     (20U)\n#define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R2_FB21_Pos     (21U)\n#define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R2_FB22_Pos     (22U)\n#define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R2_FB23_Pos     (23U)\n#define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R2_FB24_Pos     (24U)\n#define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R2_FB25_Pos     (25U)\n#define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R2_FB26_Pos     (26U)\n#define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R2_FB27_Pos     (27U)\n#define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R2_FB28_Pos     (28U)\n#define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R2_FB29_Pos     (29U)\n#define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R2_FB30_Pos     (30U)\n#define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R2_FB31_Pos     (31U)\n#define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R2 register  ******************/\n#define CAN_F11R2_FB0_Pos      (0U)\n#define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R2_FB1_Pos      (1U)\n#define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R2_FB2_Pos      (2U)\n#define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R2_FB3_Pos      (3U)\n#define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R2_FB4_Pos      (4U)\n#define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R2_FB5_Pos      (5U)\n#define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R2_FB6_Pos      (6U)\n#define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R2_FB7_Pos      (7U)\n#define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R2_FB8_Pos      (8U)\n#define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R2_FB9_Pos      (9U)\n#define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R2_FB10_Pos     (10U)\n#define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R2_FB11_Pos     (11U)\n#define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R2_FB12_Pos     (12U)\n#define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R2_FB13_Pos     (13U)\n#define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R2_FB14_Pos     (14U)\n#define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R2_FB15_Pos     (15U)\n#define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R2_FB16_Pos     (16U)\n#define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R2_FB17_Pos     (17U)\n#define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R2_FB18_Pos     (18U)\n#define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R2_FB19_Pos     (19U)\n#define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R2_FB20_Pos     (20U)\n#define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R2_FB21_Pos     (21U)\n#define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R2_FB22_Pos     (22U)\n#define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R2_FB23_Pos     (23U)\n#define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R2_FB24_Pos     (24U)\n#define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R2_FB25_Pos     (25U)\n#define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R2_FB26_Pos     (26U)\n#define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R2_FB27_Pos     (27U)\n#define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R2_FB28_Pos     (28U)\n#define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R2_FB29_Pos     (29U)\n#define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R2_FB30_Pos     (30U)\n#define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R2_FB31_Pos     (31U)\n#define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R2 register  ******************/\n#define CAN_F12R2_FB0_Pos      (0U)\n#define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R2_FB1_Pos      (1U)\n#define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R2_FB2_Pos      (2U)\n#define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R2_FB3_Pos      (3U)\n#define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R2_FB4_Pos      (4U)\n#define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R2_FB5_Pos      (5U)\n#define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R2_FB6_Pos      (6U)\n#define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R2_FB7_Pos      (7U)\n#define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R2_FB8_Pos      (8U)\n#define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R2_FB9_Pos      (9U)\n#define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R2_FB10_Pos     (10U)\n#define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R2_FB11_Pos     (11U)\n#define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R2_FB12_Pos     (12U)\n#define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R2_FB13_Pos     (13U)\n#define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R2_FB14_Pos     (14U)\n#define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R2_FB15_Pos     (15U)\n#define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R2_FB16_Pos     (16U)\n#define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R2_FB17_Pos     (17U)\n#define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R2_FB18_Pos     (18U)\n#define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R2_FB19_Pos     (19U)\n#define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R2_FB20_Pos     (20U)\n#define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R2_FB21_Pos     (21U)\n#define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R2_FB22_Pos     (22U)\n#define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R2_FB23_Pos     (23U)\n#define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R2_FB24_Pos     (24U)\n#define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R2_FB25_Pos     (25U)\n#define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R2_FB26_Pos     (26U)\n#define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R2_FB27_Pos     (27U)\n#define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R2_FB28_Pos     (28U)\n#define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R2_FB29_Pos     (29U)\n#define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R2_FB30_Pos     (30U)\n#define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R2_FB31_Pos     (31U)\n#define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R2 register  ******************/\n#define CAN_F13R2_FB0_Pos      (0U)\n#define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R2_FB1_Pos      (1U)\n#define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R2_FB2_Pos      (2U)\n#define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R2_FB3_Pos      (3U)\n#define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R2_FB4_Pos      (4U)\n#define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R2_FB5_Pos      (5U)\n#define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R2_FB6_Pos      (6U)\n#define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R2_FB7_Pos      (7U)\n#define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R2_FB8_Pos      (8U)\n#define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R2_FB9_Pos      (9U)\n#define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R2_FB10_Pos     (10U)\n#define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R2_FB11_Pos     (11U)\n#define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R2_FB12_Pos     (12U)\n#define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R2_FB13_Pos     (13U)\n#define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R2_FB14_Pos     (14U)\n#define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R2_FB15_Pos     (15U)\n#define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R2_FB16_Pos     (16U)\n#define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R2_FB17_Pos     (17U)\n#define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R2_FB18_Pos     (18U)\n#define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R2_FB19_Pos     (19U)\n#define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R2_FB20_Pos     (20U)\n#define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R2_FB21_Pos     (21U)\n#define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R2_FB22_Pos     (22U)\n#define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R2_FB23_Pos     (23U)\n#define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R2_FB24_Pos     (24U)\n#define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R2_FB25_Pos     (25U)\n#define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R2_FB26_Pos     (26U)\n#define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R2_FB27_Pos     (27U)\n#define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R2_FB28_Pos     (28U)\n#define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R2_FB29_Pos     (29U)\n#define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R2_FB30_Pos     (30U)\n#define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R2_FB31_Pos     (31U)\n#define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          CRC calculation unit                              */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for CRC_DR register  *********************/\n#define CRC_DR_DR_Pos       (0U)\n#define CRC_DR_DR_Msk       (0xFFFFFFFFUL << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */\n#define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */\n\n\n/*******************  Bit definition for CRC_IDR register  ********************/\n#define CRC_IDR_IDR_Pos     (0U)\n#define CRC_IDR_IDR_Msk     (0xFFUL << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */\n#define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */\n\n\n/********************  Bit definition for CRC_CR register  ********************/\n#define CRC_CR_RESET_Pos    (0U)\n#define CRC_CR_RESET_Msk    (0x1UL << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */\n#define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Digital to Analog Converter                           */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define DAC_CHANNEL2_SUPPORT                                    /*!< DAC feature available only on specific devices: availability of DAC channel 2 */\n/********************  Bit definition for DAC_CR register  ********************/\n#define DAC_CR_EN1_Pos              (0U)\n#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */\n#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */\n#define DAC_CR_BOFF1_Pos            (1U)\n#define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */\n#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable */\n#define DAC_CR_TEN1_Pos             (2U)\n#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */\n#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */\n\n#define DAC_CR_TSEL1_Pos            (3U)\n#define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */\n#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\n#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */\n#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */\n#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */\n\n#define DAC_CR_WAVE1_Pos            (6U)\n#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */\n#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */\n#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */\n\n#define DAC_CR_MAMP1_Pos            (8U)\n#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */\n#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\n#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */\n#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */\n#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */\n#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */\n\n#define DAC_CR_DMAEN1_Pos           (12U)\n#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */\n#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */\n#define DAC_CR_DMAUDRIE1_Pos        (13U)\n#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */\n#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable*/\n#define DAC_CR_EN2_Pos              (16U)\n#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */\n#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */\n#define DAC_CR_BOFF2_Pos            (17U)\n#define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */\n#define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable */\n#define DAC_CR_TEN2_Pos             (18U)\n#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */\n#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */\n\n#define DAC_CR_TSEL2_Pos            (19U)\n#define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */\n#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\n#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */\n#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */\n#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */\n\n#define DAC_CR_WAVE2_Pos            (22U)\n#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */\n#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */\n#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */\n\n#define DAC_CR_MAMP2_Pos            (24U)\n#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */\n#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\n#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */\n#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */\n#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */\n#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */\n\n#define DAC_CR_DMAEN2_Pos           (28U)\n#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */\n#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */\n#define DAC_CR_DMAUDRIE2_Pos        (29U)\n#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */\n#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable*/\n\n/*****************  Bit definition for DAC_SWTRIGR register  ******************/\n#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)\n#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */\n#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */\n#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)\n#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */\n#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */\n\n/*****************  Bit definition for DAC_DHR12R1 register  ******************/\n#define DAC_DHR12R1_DACC1DHR_Pos    (0U)\n#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L1 register  ******************/\n#define DAC_DHR12L1_DACC1DHR_Pos    (4U)\n#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R1 register  ******************/\n#define DAC_DHR8R1_DACC1DHR_Pos     (0U)\n#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12R2 register  ******************/\n#define DAC_DHR12R2_DACC2DHR_Pos    (0U)\n#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L2 register  ******************/\n#define DAC_DHR12L2_DACC2DHR_Pos    (4U)\n#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R2 register  ******************/\n#define DAC_DHR8R2_DACC2DHR_Pos     (0U)\n#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12RD register  ******************/\n#define DAC_DHR12RD_DACC1DHR_Pos    (0U)\n#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\n#define DAC_DHR12RD_DACC2DHR_Pos    (16U)\n#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */\n#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12LD register  ******************/\n#define DAC_DHR12LD_DACC1DHR_Pos    (4U)\n#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\n#define DAC_DHR12LD_DACC2DHR_Pos    (20U)\n#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */\n#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8RD register  ******************/\n#define DAC_DHR8RD_DACC1DHR_Pos     (0U)\n#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\n#define DAC_DHR8RD_DACC2DHR_Pos     (8U)\n#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */\n#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\n\n/*******************  Bit definition for DAC_DOR1 register  *******************/\n#define DAC_DOR1_DACC1DOR_Pos       (0U)\n#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */\n#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */\n\n/*******************  Bit definition for DAC_DOR2 register  *******************/\n#define DAC_DOR2_DACC2DOR_Pos       (0U)\n#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */\n#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */\n\n/********************  Bit definition for DAC_SR register  ********************/\n#define DAC_SR_DMAUDR1_Pos          (13U)\n#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */\n#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */\n#define DAC_SR_DMAUDR2_Pos          (29U)\n#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */\n#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                             DMA Controller                                 */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DMA_SxCR register  *****************/\n#define DMA_SxCR_CHSEL_Pos       (25U)\n#define DMA_SxCR_CHSEL_Msk       (0x7UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */\n#define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk\n#define DMA_SxCR_CHSEL_0         0x02000000U\n#define DMA_SxCR_CHSEL_1         0x04000000U\n#define DMA_SxCR_CHSEL_2         0x08000000U\n#define DMA_SxCR_MBURST_Pos      (23U)\n#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */\n#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk\n#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */\n#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */\n#define DMA_SxCR_PBURST_Pos      (21U)\n#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */\n#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk\n#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */\n#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */\n#define DMA_SxCR_CT_Pos          (19U)\n#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */\n#define DMA_SxCR_CT              DMA_SxCR_CT_Msk\n#define DMA_SxCR_DBM_Pos         (18U)\n#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */\n#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk\n#define DMA_SxCR_PL_Pos          (16U)\n#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */\n#define DMA_SxCR_PL              DMA_SxCR_PL_Msk\n#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */\n#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */\n#define DMA_SxCR_PINCOS_Pos      (15U)\n#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */\n#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk\n#define DMA_SxCR_MSIZE_Pos       (13U)\n#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */\n#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk\n#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */\n#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */\n#define DMA_SxCR_PSIZE_Pos       (11U)\n#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */\n#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk\n#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */\n#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */\n#define DMA_SxCR_MINC_Pos        (10U)\n#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */\n#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk\n#define DMA_SxCR_PINC_Pos        (9U)\n#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */\n#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk\n#define DMA_SxCR_CIRC_Pos        (8U)\n#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */\n#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk\n#define DMA_SxCR_DIR_Pos         (6U)\n#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */\n#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk\n#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */\n#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */\n#define DMA_SxCR_PFCTRL_Pos      (5U)\n#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */\n#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk\n#define DMA_SxCR_TCIE_Pos        (4U)\n#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */\n#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk\n#define DMA_SxCR_HTIE_Pos        (3U)\n#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */\n#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk\n#define DMA_SxCR_TEIE_Pos        (2U)\n#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */\n#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk\n#define DMA_SxCR_DMEIE_Pos       (1U)\n#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */\n#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk\n#define DMA_SxCR_EN_Pos          (0U)\n#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */\n#define DMA_SxCR_EN              DMA_SxCR_EN_Msk\n\n/* Legacy defines */\n#define DMA_SxCR_ACK_Pos         (20U)\n#define DMA_SxCR_ACK_Msk         (0x1UL << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */\n#define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk\n\n/********************  Bits definition for DMA_SxCNDTR register  **************/\n#define DMA_SxNDT_Pos            (0U)\n#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */\n#define DMA_SxNDT                DMA_SxNDT_Msk\n#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */\n#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */\n#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */\n#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */\n#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */\n#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */\n#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */\n#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */\n#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */\n#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */\n#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */\n#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */\n#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */\n#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */\n#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */\n#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */\n\n/********************  Bits definition for DMA_SxFCR register  ****************/\n#define DMA_SxFCR_FEIE_Pos       (7U)\n#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */\n#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk\n#define DMA_SxFCR_FS_Pos         (3U)\n#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */\n#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk\n#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */\n#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */\n#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */\n#define DMA_SxFCR_DMDIS_Pos      (2U)\n#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */\n#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk\n#define DMA_SxFCR_FTH_Pos        (0U)\n#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */\n#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk\n#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */\n#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */\n\n/********************  Bits definition for DMA_LISR register  *****************/\n#define DMA_LISR_TCIF3_Pos       (27U)\n#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */\n#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk\n#define DMA_LISR_HTIF3_Pos       (26U)\n#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */\n#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk\n#define DMA_LISR_TEIF3_Pos       (25U)\n#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */\n#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk\n#define DMA_LISR_DMEIF3_Pos      (24U)\n#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */\n#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk\n#define DMA_LISR_FEIF3_Pos       (22U)\n#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */\n#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk\n#define DMA_LISR_TCIF2_Pos       (21U)\n#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */\n#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk\n#define DMA_LISR_HTIF2_Pos       (20U)\n#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */\n#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk\n#define DMA_LISR_TEIF2_Pos       (19U)\n#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */\n#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk\n#define DMA_LISR_DMEIF2_Pos      (18U)\n#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */\n#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk\n#define DMA_LISR_FEIF2_Pos       (16U)\n#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */\n#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk\n#define DMA_LISR_TCIF1_Pos       (11U)\n#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */\n#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk\n#define DMA_LISR_HTIF1_Pos       (10U)\n#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */\n#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk\n#define DMA_LISR_TEIF1_Pos       (9U)\n#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */\n#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk\n#define DMA_LISR_DMEIF1_Pos      (8U)\n#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */\n#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk\n#define DMA_LISR_FEIF1_Pos       (6U)\n#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */\n#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk\n#define DMA_LISR_TCIF0_Pos       (5U)\n#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */\n#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk\n#define DMA_LISR_HTIF0_Pos       (4U)\n#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */\n#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk\n#define DMA_LISR_TEIF0_Pos       (3U)\n#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */\n#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk\n#define DMA_LISR_DMEIF0_Pos      (2U)\n#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */\n#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk\n#define DMA_LISR_FEIF0_Pos       (0U)\n#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */\n#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk\n\n/********************  Bits definition for DMA_HISR register  *****************/\n#define DMA_HISR_TCIF7_Pos       (27U)\n#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */\n#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk\n#define DMA_HISR_HTIF7_Pos       (26U)\n#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */\n#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk\n#define DMA_HISR_TEIF7_Pos       (25U)\n#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */\n#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk\n#define DMA_HISR_DMEIF7_Pos      (24U)\n#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */\n#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk\n#define DMA_HISR_FEIF7_Pos       (22U)\n#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */\n#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk\n#define DMA_HISR_TCIF6_Pos       (21U)\n#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */\n#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk\n#define DMA_HISR_HTIF6_Pos       (20U)\n#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */\n#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk\n#define DMA_HISR_TEIF6_Pos       (19U)\n#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */\n#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk\n#define DMA_HISR_DMEIF6_Pos      (18U)\n#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */\n#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk\n#define DMA_HISR_FEIF6_Pos       (16U)\n#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */\n#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk\n#define DMA_HISR_TCIF5_Pos       (11U)\n#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */\n#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk\n#define DMA_HISR_HTIF5_Pos       (10U)\n#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */\n#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk\n#define DMA_HISR_TEIF5_Pos       (9U)\n#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */\n#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk\n#define DMA_HISR_DMEIF5_Pos      (8U)\n#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */\n#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk\n#define DMA_HISR_FEIF5_Pos       (6U)\n#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */\n#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk\n#define DMA_HISR_TCIF4_Pos       (5U)\n#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */\n#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk\n#define DMA_HISR_HTIF4_Pos       (4U)\n#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */\n#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk\n#define DMA_HISR_TEIF4_Pos       (3U)\n#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */\n#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk\n#define DMA_HISR_DMEIF4_Pos      (2U)\n#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */\n#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk\n#define DMA_HISR_FEIF4_Pos       (0U)\n#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */\n#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk\n\n/********************  Bits definition for DMA_LIFCR register  ****************/\n#define DMA_LIFCR_CTCIF3_Pos     (27U)\n#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */\n#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk\n#define DMA_LIFCR_CHTIF3_Pos     (26U)\n#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */\n#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk\n#define DMA_LIFCR_CTEIF3_Pos     (25U)\n#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */\n#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk\n#define DMA_LIFCR_CDMEIF3_Pos    (24U)\n#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */\n#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk\n#define DMA_LIFCR_CFEIF3_Pos     (22U)\n#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */\n#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk\n#define DMA_LIFCR_CTCIF2_Pos     (21U)\n#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */\n#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk\n#define DMA_LIFCR_CHTIF2_Pos     (20U)\n#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */\n#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk\n#define DMA_LIFCR_CTEIF2_Pos     (19U)\n#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */\n#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk\n#define DMA_LIFCR_CDMEIF2_Pos    (18U)\n#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */\n#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk\n#define DMA_LIFCR_CFEIF2_Pos     (16U)\n#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */\n#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk\n#define DMA_LIFCR_CTCIF1_Pos     (11U)\n#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */\n#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk\n#define DMA_LIFCR_CHTIF1_Pos     (10U)\n#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */\n#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk\n#define DMA_LIFCR_CTEIF1_Pos     (9U)\n#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */\n#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk\n#define DMA_LIFCR_CDMEIF1_Pos    (8U)\n#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */\n#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk\n#define DMA_LIFCR_CFEIF1_Pos     (6U)\n#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */\n#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk\n#define DMA_LIFCR_CTCIF0_Pos     (5U)\n#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */\n#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk\n#define DMA_LIFCR_CHTIF0_Pos     (4U)\n#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */\n#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk\n#define DMA_LIFCR_CTEIF0_Pos     (3U)\n#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */\n#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk\n#define DMA_LIFCR_CDMEIF0_Pos    (2U)\n#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */\n#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk\n#define DMA_LIFCR_CFEIF0_Pos     (0U)\n#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */\n#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk\n\n/********************  Bits definition for DMA_HIFCR  register  ****************/\n#define DMA_HIFCR_CTCIF7_Pos     (27U)\n#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */\n#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk\n#define DMA_HIFCR_CHTIF7_Pos     (26U)\n#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */\n#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk\n#define DMA_HIFCR_CTEIF7_Pos     (25U)\n#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */\n#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk\n#define DMA_HIFCR_CDMEIF7_Pos    (24U)\n#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */\n#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk\n#define DMA_HIFCR_CFEIF7_Pos     (22U)\n#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */\n#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk\n#define DMA_HIFCR_CTCIF6_Pos     (21U)\n#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */\n#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk\n#define DMA_HIFCR_CHTIF6_Pos     (20U)\n#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */\n#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk\n#define DMA_HIFCR_CTEIF6_Pos     (19U)\n#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */\n#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk\n#define DMA_HIFCR_CDMEIF6_Pos    (18U)\n#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */\n#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk\n#define DMA_HIFCR_CFEIF6_Pos     (16U)\n#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */\n#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk\n#define DMA_HIFCR_CTCIF5_Pos     (11U)\n#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */\n#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk\n#define DMA_HIFCR_CHTIF5_Pos     (10U)\n#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */\n#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk\n#define DMA_HIFCR_CTEIF5_Pos     (9U)\n#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */\n#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk\n#define DMA_HIFCR_CDMEIF5_Pos    (8U)\n#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */\n#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk\n#define DMA_HIFCR_CFEIF5_Pos     (6U)\n#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */\n#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk\n#define DMA_HIFCR_CTCIF4_Pos     (5U)\n#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */\n#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk\n#define DMA_HIFCR_CHTIF4_Pos     (4U)\n#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */\n#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk\n#define DMA_HIFCR_CTEIF4_Pos     (3U)\n#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */\n#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk\n#define DMA_HIFCR_CDMEIF4_Pos    (2U)\n#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */\n#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk\n#define DMA_HIFCR_CFEIF4_Pos     (0U)\n#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */\n#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk\n\n/******************  Bit definition for DMA_SxPAR register  ********************/\n#define DMA_SxPAR_PA_Pos         (0U)\n#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */\n#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */\n\n/******************  Bit definition for DMA_SxM0AR register  ********************/\n#define DMA_SxM0AR_M0A_Pos       (0U)\n#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */\n\n/******************  Bit definition for DMA_SxM1AR register  ********************/\n#define DMA_SxM1AR_M1A_Pos       (0U)\n#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                    External Interrupt/Event Controller                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for EXTI_IMR register  *******************/\n#define EXTI_IMR_MR0_Pos          (0U)\n#define EXTI_IMR_MR0_Msk          (0x1UL << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */\n#define EXTI_IMR_MR1_Pos          (1U)\n#define EXTI_IMR_MR1_Msk          (0x1UL << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */\n#define EXTI_IMR_MR2_Pos          (2U)\n#define EXTI_IMR_MR2_Msk          (0x1UL << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */\n#define EXTI_IMR_MR3_Pos          (3U)\n#define EXTI_IMR_MR3_Msk          (0x1UL << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */\n#define EXTI_IMR_MR4_Pos          (4U)\n#define EXTI_IMR_MR4_Msk          (0x1UL << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */\n#define EXTI_IMR_MR5_Pos          (5U)\n#define EXTI_IMR_MR5_Msk          (0x1UL << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */\n#define EXTI_IMR_MR6_Pos          (6U)\n#define EXTI_IMR_MR6_Msk          (0x1UL << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */\n#define EXTI_IMR_MR7_Pos          (7U)\n#define EXTI_IMR_MR7_Msk          (0x1UL << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */\n#define EXTI_IMR_MR8_Pos          (8U)\n#define EXTI_IMR_MR8_Msk          (0x1UL << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */\n#define EXTI_IMR_MR9_Pos          (9U)\n#define EXTI_IMR_MR9_Msk          (0x1UL << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */\n#define EXTI_IMR_MR10_Pos         (10U)\n#define EXTI_IMR_MR10_Msk         (0x1UL << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */\n#define EXTI_IMR_MR11_Pos         (11U)\n#define EXTI_IMR_MR11_Msk         (0x1UL << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */\n#define EXTI_IMR_MR12_Pos         (12U)\n#define EXTI_IMR_MR12_Msk         (0x1UL << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */\n#define EXTI_IMR_MR13_Pos         (13U)\n#define EXTI_IMR_MR13_Msk         (0x1UL << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */\n#define EXTI_IMR_MR14_Pos         (14U)\n#define EXTI_IMR_MR14_Msk         (0x1UL << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */\n#define EXTI_IMR_MR15_Pos         (15U)\n#define EXTI_IMR_MR15_Msk         (0x1UL << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */\n#define EXTI_IMR_MR16_Pos         (16U)\n#define EXTI_IMR_MR16_Msk         (0x1UL << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */\n#define EXTI_IMR_MR17_Pos         (17U)\n#define EXTI_IMR_MR17_Msk         (0x1UL << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */\n#define EXTI_IMR_MR18_Pos         (18U)\n#define EXTI_IMR_MR18_Msk         (0x1UL << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */\n#define EXTI_IMR_MR19_Pos         (19U)\n#define EXTI_IMR_MR19_Msk         (0x1UL << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */\n#define EXTI_IMR_MR20_Pos         (20U)\n#define EXTI_IMR_MR20_Msk         (0x1UL << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */\n#define EXTI_IMR_MR21_Pos         (21U)\n#define EXTI_IMR_MR21_Msk         (0x1UL << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */\n#define EXTI_IMR_MR22_Pos         (22U)\n#define EXTI_IMR_MR22_Msk         (0x1UL << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */\n\n/* Reference Defines */\n#define  EXTI_IMR_IM0                        EXTI_IMR_MR0\n#define  EXTI_IMR_IM1                        EXTI_IMR_MR1\n#define  EXTI_IMR_IM2                        EXTI_IMR_MR2\n#define  EXTI_IMR_IM3                        EXTI_IMR_MR3\n#define  EXTI_IMR_IM4                        EXTI_IMR_MR4\n#define  EXTI_IMR_IM5                        EXTI_IMR_MR5\n#define  EXTI_IMR_IM6                        EXTI_IMR_MR6\n#define  EXTI_IMR_IM7                        EXTI_IMR_MR7\n#define  EXTI_IMR_IM8                        EXTI_IMR_MR8\n#define  EXTI_IMR_IM9                        EXTI_IMR_MR9\n#define  EXTI_IMR_IM10                       EXTI_IMR_MR10\n#define  EXTI_IMR_IM11                       EXTI_IMR_MR11\n#define  EXTI_IMR_IM12                       EXTI_IMR_MR12\n#define  EXTI_IMR_IM13                       EXTI_IMR_MR13\n#define  EXTI_IMR_IM14                       EXTI_IMR_MR14\n#define  EXTI_IMR_IM15                       EXTI_IMR_MR15\n#define  EXTI_IMR_IM16                       EXTI_IMR_MR16\n#define  EXTI_IMR_IM17                       EXTI_IMR_MR17\n#define  EXTI_IMR_IM18                       EXTI_IMR_MR18\n#define  EXTI_IMR_IM19                       EXTI_IMR_MR19\n#define  EXTI_IMR_IM20                       EXTI_IMR_MR20\n#define  EXTI_IMR_IM21                       EXTI_IMR_MR21\n#define  EXTI_IMR_IM22                       EXTI_IMR_MR22\n#define EXTI_IMR_IM_Pos           (0U)\n#define EXTI_IMR_IM_Msk           (0x7FFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x007FFFFF */\n#define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */\n\n/*******************  Bit definition for EXTI_EMR register  *******************/\n#define EXTI_EMR_MR0_Pos          (0U)\n#define EXTI_EMR_MR0_Msk          (0x1UL << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */\n#define EXTI_EMR_MR1_Pos          (1U)\n#define EXTI_EMR_MR1_Msk          (0x1UL << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */\n#define EXTI_EMR_MR2_Pos          (2U)\n#define EXTI_EMR_MR2_Msk          (0x1UL << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */\n#define EXTI_EMR_MR3_Pos          (3U)\n#define EXTI_EMR_MR3_Msk          (0x1UL << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */\n#define EXTI_EMR_MR4_Pos          (4U)\n#define EXTI_EMR_MR4_Msk          (0x1UL << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */\n#define EXTI_EMR_MR5_Pos          (5U)\n#define EXTI_EMR_MR5_Msk          (0x1UL << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */\n#define EXTI_EMR_MR6_Pos          (6U)\n#define EXTI_EMR_MR6_Msk          (0x1UL << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */\n#define EXTI_EMR_MR7_Pos          (7U)\n#define EXTI_EMR_MR7_Msk          (0x1UL << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */\n#define EXTI_EMR_MR8_Pos          (8U)\n#define EXTI_EMR_MR8_Msk          (0x1UL << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */\n#define EXTI_EMR_MR9_Pos          (9U)\n#define EXTI_EMR_MR9_Msk          (0x1UL << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */\n#define EXTI_EMR_MR10_Pos         (10U)\n#define EXTI_EMR_MR10_Msk         (0x1UL << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */\n#define EXTI_EMR_MR11_Pos         (11U)\n#define EXTI_EMR_MR11_Msk         (0x1UL << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */\n#define EXTI_EMR_MR12_Pos         (12U)\n#define EXTI_EMR_MR12_Msk         (0x1UL << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */\n#define EXTI_EMR_MR13_Pos         (13U)\n#define EXTI_EMR_MR13_Msk         (0x1UL << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */\n#define EXTI_EMR_MR14_Pos         (14U)\n#define EXTI_EMR_MR14_Msk         (0x1UL << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */\n#define EXTI_EMR_MR15_Pos         (15U)\n#define EXTI_EMR_MR15_Msk         (0x1UL << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */\n#define EXTI_EMR_MR16_Pos         (16U)\n#define EXTI_EMR_MR16_Msk         (0x1UL << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */\n#define EXTI_EMR_MR17_Pos         (17U)\n#define EXTI_EMR_MR17_Msk         (0x1UL << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */\n#define EXTI_EMR_MR18_Pos         (18U)\n#define EXTI_EMR_MR18_Msk         (0x1UL << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */\n#define EXTI_EMR_MR19_Pos         (19U)\n#define EXTI_EMR_MR19_Msk         (0x1UL << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */\n#define EXTI_EMR_MR20_Pos         (20U)\n#define EXTI_EMR_MR20_Msk         (0x1UL << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */\n#define EXTI_EMR_MR21_Pos         (21U)\n#define EXTI_EMR_MR21_Msk         (0x1UL << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */\n#define EXTI_EMR_MR22_Pos         (22U)\n#define EXTI_EMR_MR22_Msk         (0x1UL << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */\n\n/* Reference Defines */\n#define  EXTI_EMR_EM0                        EXTI_EMR_MR0\n#define  EXTI_EMR_EM1                        EXTI_EMR_MR1\n#define  EXTI_EMR_EM2                        EXTI_EMR_MR2\n#define  EXTI_EMR_EM3                        EXTI_EMR_MR3\n#define  EXTI_EMR_EM4                        EXTI_EMR_MR4\n#define  EXTI_EMR_EM5                        EXTI_EMR_MR5\n#define  EXTI_EMR_EM6                        EXTI_EMR_MR6\n#define  EXTI_EMR_EM7                        EXTI_EMR_MR7\n#define  EXTI_EMR_EM8                        EXTI_EMR_MR8\n#define  EXTI_EMR_EM9                        EXTI_EMR_MR9\n#define  EXTI_EMR_EM10                       EXTI_EMR_MR10\n#define  EXTI_EMR_EM11                       EXTI_EMR_MR11\n#define  EXTI_EMR_EM12                       EXTI_EMR_MR12\n#define  EXTI_EMR_EM13                       EXTI_EMR_MR13\n#define  EXTI_EMR_EM14                       EXTI_EMR_MR14\n#define  EXTI_EMR_EM15                       EXTI_EMR_MR15\n#define  EXTI_EMR_EM16                       EXTI_EMR_MR16\n#define  EXTI_EMR_EM17                       EXTI_EMR_MR17\n#define  EXTI_EMR_EM18                       EXTI_EMR_MR18\n#define  EXTI_EMR_EM19                       EXTI_EMR_MR19\n#define  EXTI_EMR_EM20                       EXTI_EMR_MR20\n#define  EXTI_EMR_EM21                       EXTI_EMR_MR21\n#define  EXTI_EMR_EM22                       EXTI_EMR_MR22\n\n/******************  Bit definition for EXTI_RTSR register  *******************/\n#define EXTI_RTSR_TR0_Pos         (0U)\n#define EXTI_RTSR_TR0_Msk         (0x1UL << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */\n#define EXTI_RTSR_TR1_Pos         (1U)\n#define EXTI_RTSR_TR1_Msk         (0x1UL << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */\n#define EXTI_RTSR_TR2_Pos         (2U)\n#define EXTI_RTSR_TR2_Msk         (0x1UL << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */\n#define EXTI_RTSR_TR3_Pos         (3U)\n#define EXTI_RTSR_TR3_Msk         (0x1UL << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */\n#define EXTI_RTSR_TR4_Pos         (4U)\n#define EXTI_RTSR_TR4_Msk         (0x1UL << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */\n#define EXTI_RTSR_TR5_Pos         (5U)\n#define EXTI_RTSR_TR5_Msk         (0x1UL << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */\n#define EXTI_RTSR_TR6_Pos         (6U)\n#define EXTI_RTSR_TR6_Msk         (0x1UL << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */\n#define EXTI_RTSR_TR7_Pos         (7U)\n#define EXTI_RTSR_TR7_Msk         (0x1UL << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */\n#define EXTI_RTSR_TR8_Pos         (8U)\n#define EXTI_RTSR_TR8_Msk         (0x1UL << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */\n#define EXTI_RTSR_TR9_Pos         (9U)\n#define EXTI_RTSR_TR9_Msk         (0x1UL << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */\n#define EXTI_RTSR_TR10_Pos        (10U)\n#define EXTI_RTSR_TR10_Msk        (0x1UL << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */\n#define EXTI_RTSR_TR11_Pos        (11U)\n#define EXTI_RTSR_TR11_Msk        (0x1UL << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */\n#define EXTI_RTSR_TR12_Pos        (12U)\n#define EXTI_RTSR_TR12_Msk        (0x1UL << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */\n#define EXTI_RTSR_TR13_Pos        (13U)\n#define EXTI_RTSR_TR13_Msk        (0x1UL << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */\n#define EXTI_RTSR_TR14_Pos        (14U)\n#define EXTI_RTSR_TR14_Msk        (0x1UL << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */\n#define EXTI_RTSR_TR15_Pos        (15U)\n#define EXTI_RTSR_TR15_Msk        (0x1UL << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */\n#define EXTI_RTSR_TR16_Pos        (16U)\n#define EXTI_RTSR_TR16_Msk        (0x1UL << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */\n#define EXTI_RTSR_TR17_Pos        (17U)\n#define EXTI_RTSR_TR17_Msk        (0x1UL << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */\n#define EXTI_RTSR_TR18_Pos        (18U)\n#define EXTI_RTSR_TR18_Msk        (0x1UL << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */\n#define EXTI_RTSR_TR19_Pos        (19U)\n#define EXTI_RTSR_TR19_Msk        (0x1UL << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */\n#define EXTI_RTSR_TR20_Pos        (20U)\n#define EXTI_RTSR_TR20_Msk        (0x1UL << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */\n#define EXTI_RTSR_TR21_Pos        (21U)\n#define EXTI_RTSR_TR21_Msk        (0x1UL << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */\n#define EXTI_RTSR_TR22_Pos        (22U)\n#define EXTI_RTSR_TR22_Msk        (0x1UL << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_FTSR register  *******************/\n#define EXTI_FTSR_TR0_Pos         (0U)\n#define EXTI_FTSR_TR0_Msk         (0x1UL << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */\n#define EXTI_FTSR_TR1_Pos         (1U)\n#define EXTI_FTSR_TR1_Msk         (0x1UL << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */\n#define EXTI_FTSR_TR2_Pos         (2U)\n#define EXTI_FTSR_TR2_Msk         (0x1UL << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */\n#define EXTI_FTSR_TR3_Pos         (3U)\n#define EXTI_FTSR_TR3_Msk         (0x1UL << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */\n#define EXTI_FTSR_TR4_Pos         (4U)\n#define EXTI_FTSR_TR4_Msk         (0x1UL << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */\n#define EXTI_FTSR_TR5_Pos         (5U)\n#define EXTI_FTSR_TR5_Msk         (0x1UL << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */\n#define EXTI_FTSR_TR6_Pos         (6U)\n#define EXTI_FTSR_TR6_Msk         (0x1UL << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */\n#define EXTI_FTSR_TR7_Pos         (7U)\n#define EXTI_FTSR_TR7_Msk         (0x1UL << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */\n#define EXTI_FTSR_TR8_Pos         (8U)\n#define EXTI_FTSR_TR8_Msk         (0x1UL << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */\n#define EXTI_FTSR_TR9_Pos         (9U)\n#define EXTI_FTSR_TR9_Msk         (0x1UL << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */\n#define EXTI_FTSR_TR10_Pos        (10U)\n#define EXTI_FTSR_TR10_Msk        (0x1UL << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */\n#define EXTI_FTSR_TR11_Pos        (11U)\n#define EXTI_FTSR_TR11_Msk        (0x1UL << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */\n#define EXTI_FTSR_TR12_Pos        (12U)\n#define EXTI_FTSR_TR12_Msk        (0x1UL << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */\n#define EXTI_FTSR_TR13_Pos        (13U)\n#define EXTI_FTSR_TR13_Msk        (0x1UL << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */\n#define EXTI_FTSR_TR14_Pos        (14U)\n#define EXTI_FTSR_TR14_Msk        (0x1UL << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */\n#define EXTI_FTSR_TR15_Pos        (15U)\n#define EXTI_FTSR_TR15_Msk        (0x1UL << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */\n#define EXTI_FTSR_TR16_Pos        (16U)\n#define EXTI_FTSR_TR16_Msk        (0x1UL << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */\n#define EXTI_FTSR_TR17_Pos        (17U)\n#define EXTI_FTSR_TR17_Msk        (0x1UL << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */\n#define EXTI_FTSR_TR18_Pos        (18U)\n#define EXTI_FTSR_TR18_Msk        (0x1UL << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */\n#define EXTI_FTSR_TR19_Pos        (19U)\n#define EXTI_FTSR_TR19_Msk        (0x1UL << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */\n#define EXTI_FTSR_TR20_Pos        (20U)\n#define EXTI_FTSR_TR20_Msk        (0x1UL << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */\n#define EXTI_FTSR_TR21_Pos        (21U)\n#define EXTI_FTSR_TR21_Msk        (0x1UL << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */\n#define EXTI_FTSR_TR22_Pos        (22U)\n#define EXTI_FTSR_TR22_Msk        (0x1UL << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_SWIER register  ******************/\n#define EXTI_SWIER_SWIER0_Pos     (0U)\n#define EXTI_SWIER_SWIER0_Msk     (0x1UL << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */\n#define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */\n#define EXTI_SWIER_SWIER1_Pos     (1U)\n#define EXTI_SWIER_SWIER1_Msk     (0x1UL << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */\n#define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */\n#define EXTI_SWIER_SWIER2_Pos     (2U)\n#define EXTI_SWIER_SWIER2_Msk     (0x1UL << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */\n#define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */\n#define EXTI_SWIER_SWIER3_Pos     (3U)\n#define EXTI_SWIER_SWIER3_Msk     (0x1UL << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */\n#define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */\n#define EXTI_SWIER_SWIER4_Pos     (4U)\n#define EXTI_SWIER_SWIER4_Msk     (0x1UL << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */\n#define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */\n#define EXTI_SWIER_SWIER5_Pos     (5U)\n#define EXTI_SWIER_SWIER5_Msk     (0x1UL << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */\n#define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */\n#define EXTI_SWIER_SWIER6_Pos     (6U)\n#define EXTI_SWIER_SWIER6_Msk     (0x1UL << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */\n#define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */\n#define EXTI_SWIER_SWIER7_Pos     (7U)\n#define EXTI_SWIER_SWIER7_Msk     (0x1UL << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */\n#define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */\n#define EXTI_SWIER_SWIER8_Pos     (8U)\n#define EXTI_SWIER_SWIER8_Msk     (0x1UL << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */\n#define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */\n#define EXTI_SWIER_SWIER9_Pos     (9U)\n#define EXTI_SWIER_SWIER9_Msk     (0x1UL << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */\n#define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */\n#define EXTI_SWIER_SWIER10_Pos    (10U)\n#define EXTI_SWIER_SWIER10_Msk    (0x1UL << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */\n#define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */\n#define EXTI_SWIER_SWIER11_Pos    (11U)\n#define EXTI_SWIER_SWIER11_Msk    (0x1UL << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */\n#define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */\n#define EXTI_SWIER_SWIER12_Pos    (12U)\n#define EXTI_SWIER_SWIER12_Msk    (0x1UL << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */\n#define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */\n#define EXTI_SWIER_SWIER13_Pos    (13U)\n#define EXTI_SWIER_SWIER13_Msk    (0x1UL << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */\n#define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */\n#define EXTI_SWIER_SWIER14_Pos    (14U)\n#define EXTI_SWIER_SWIER14_Msk    (0x1UL << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */\n#define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */\n#define EXTI_SWIER_SWIER15_Pos    (15U)\n#define EXTI_SWIER_SWIER15_Msk    (0x1UL << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */\n#define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */\n#define EXTI_SWIER_SWIER16_Pos    (16U)\n#define EXTI_SWIER_SWIER16_Msk    (0x1UL << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */\n#define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */\n#define EXTI_SWIER_SWIER17_Pos    (17U)\n#define EXTI_SWIER_SWIER17_Msk    (0x1UL << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */\n#define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */\n#define EXTI_SWIER_SWIER18_Pos    (18U)\n#define EXTI_SWIER_SWIER18_Msk    (0x1UL << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */\n#define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */\n#define EXTI_SWIER_SWIER19_Pos    (19U)\n#define EXTI_SWIER_SWIER19_Msk    (0x1UL << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */\n#define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */\n#define EXTI_SWIER_SWIER20_Pos    (20U)\n#define EXTI_SWIER_SWIER20_Msk    (0x1UL << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */\n#define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */\n#define EXTI_SWIER_SWIER21_Pos    (21U)\n#define EXTI_SWIER_SWIER21_Msk    (0x1UL << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */\n#define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */\n#define EXTI_SWIER_SWIER22_Pos    (22U)\n#define EXTI_SWIER_SWIER22_Msk    (0x1UL << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */\n#define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */\n\n/*******************  Bit definition for EXTI_PR register  ********************/\n#define EXTI_PR_PR0_Pos           (0U)\n#define EXTI_PR_PR0_Msk           (0x1UL << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */\n#define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */\n#define EXTI_PR_PR1_Pos           (1U)\n#define EXTI_PR_PR1_Msk           (0x1UL << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */\n#define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */\n#define EXTI_PR_PR2_Pos           (2U)\n#define EXTI_PR_PR2_Msk           (0x1UL << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */\n#define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */\n#define EXTI_PR_PR3_Pos           (3U)\n#define EXTI_PR_PR3_Msk           (0x1UL << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */\n#define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */\n#define EXTI_PR_PR4_Pos           (4U)\n#define EXTI_PR_PR4_Msk           (0x1UL << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */\n#define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */\n#define EXTI_PR_PR5_Pos           (5U)\n#define EXTI_PR_PR5_Msk           (0x1UL << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */\n#define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */\n#define EXTI_PR_PR6_Pos           (6U)\n#define EXTI_PR_PR6_Msk           (0x1UL << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */\n#define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */\n#define EXTI_PR_PR7_Pos           (7U)\n#define EXTI_PR_PR7_Msk           (0x1UL << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */\n#define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */\n#define EXTI_PR_PR8_Pos           (8U)\n#define EXTI_PR_PR8_Msk           (0x1UL << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */\n#define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */\n#define EXTI_PR_PR9_Pos           (9U)\n#define EXTI_PR_PR9_Msk           (0x1UL << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */\n#define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */\n#define EXTI_PR_PR10_Pos          (10U)\n#define EXTI_PR_PR10_Msk          (0x1UL << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */\n#define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */\n#define EXTI_PR_PR11_Pos          (11U)\n#define EXTI_PR_PR11_Msk          (0x1UL << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */\n#define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */\n#define EXTI_PR_PR12_Pos          (12U)\n#define EXTI_PR_PR12_Msk          (0x1UL << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */\n#define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */\n#define EXTI_PR_PR13_Pos          (13U)\n#define EXTI_PR_PR13_Msk          (0x1UL << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */\n#define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */\n#define EXTI_PR_PR14_Pos          (14U)\n#define EXTI_PR_PR14_Msk          (0x1UL << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */\n#define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */\n#define EXTI_PR_PR15_Pos          (15U)\n#define EXTI_PR_PR15_Msk          (0x1UL << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */\n#define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */\n#define EXTI_PR_PR16_Pos          (16U)\n#define EXTI_PR_PR16_Msk          (0x1UL << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */\n#define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */\n#define EXTI_PR_PR17_Pos          (17U)\n#define EXTI_PR_PR17_Msk          (0x1UL << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */\n#define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */\n#define EXTI_PR_PR18_Pos          (18U)\n#define EXTI_PR_PR18_Msk          (0x1UL << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */\n#define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */\n#define EXTI_PR_PR19_Pos          (19U)\n#define EXTI_PR_PR19_Msk          (0x1UL << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */\n#define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */\n#define EXTI_PR_PR20_Pos          (20U)\n#define EXTI_PR_PR20_Msk          (0x1UL << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */\n#define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */\n#define EXTI_PR_PR21_Pos          (21U)\n#define EXTI_PR_PR21_Msk          (0x1UL << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */\n#define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */\n#define EXTI_PR_PR22_Pos          (22U)\n#define EXTI_PR_PR22_Msk          (0x1UL << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */\n#define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    FLASH                                   */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bits definition for FLASH_ACR register  *****************/\n#define FLASH_ACR_LATENCY_Pos          (0U)\n#define FLASH_ACR_LATENCY_Msk          (0xFUL << FLASH_ACR_LATENCY_Pos)         /*!< 0x0000000F */\n#define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk\n#define FLASH_ACR_LATENCY_0WS          0x00000000U\n#define FLASH_ACR_LATENCY_1WS          0x00000001U\n#define FLASH_ACR_LATENCY_2WS          0x00000002U\n#define FLASH_ACR_LATENCY_3WS          0x00000003U\n#define FLASH_ACR_LATENCY_4WS          0x00000004U\n#define FLASH_ACR_LATENCY_5WS          0x00000005U\n#define FLASH_ACR_LATENCY_6WS          0x00000006U\n#define FLASH_ACR_LATENCY_7WS          0x00000007U\n\n#define FLASH_ACR_PRFTEN_Pos           (8U)\n#define FLASH_ACR_PRFTEN_Msk           (0x1UL << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */\n#define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk\n#define FLASH_ACR_ICEN_Pos             (9U)\n#define FLASH_ACR_ICEN_Msk             (0x1UL << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */\n#define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk\n#define FLASH_ACR_DCEN_Pos             (10U)\n#define FLASH_ACR_DCEN_Msk             (0x1UL << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */\n#define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk\n#define FLASH_ACR_ICRST_Pos            (11U)\n#define FLASH_ACR_ICRST_Msk            (0x1UL << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */\n#define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk\n#define FLASH_ACR_DCRST_Pos            (12U)\n#define FLASH_ACR_DCRST_Msk            (0x1UL << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */\n#define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk\n#define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)\n#define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */\n#define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk\n#define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)\n#define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */\n#define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk\n\n/*******************  Bits definition for FLASH_SR register  ******************/\n#define FLASH_SR_EOP_Pos               (0U)\n#define FLASH_SR_EOP_Msk               (0x1UL << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */\n#define FLASH_SR_EOP                   FLASH_SR_EOP_Msk\n#define FLASH_SR_SOP_Pos               (1U)\n#define FLASH_SR_SOP_Msk               (0x1UL << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */\n#define FLASH_SR_SOP                   FLASH_SR_SOP_Msk\n#define FLASH_SR_WRPERR_Pos            (4U)\n#define FLASH_SR_WRPERR_Msk            (0x1UL << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */\n#define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk\n#define FLASH_SR_PGAERR_Pos            (5U)\n#define FLASH_SR_PGAERR_Msk            (0x1UL << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */\n#define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk\n#define FLASH_SR_PGPERR_Pos            (6U)\n#define FLASH_SR_PGPERR_Msk            (0x1UL << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */\n#define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk\n#define FLASH_SR_PGSERR_Pos            (7U)\n#define FLASH_SR_PGSERR_Msk            (0x1UL << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */\n#define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk\n#define FLASH_SR_BSY_Pos               (16U)\n#define FLASH_SR_BSY_Msk               (0x1UL << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */\n#define FLASH_SR_BSY                   FLASH_SR_BSY_Msk\n\n/*******************  Bits definition for FLASH_CR register  ******************/\n#define FLASH_CR_PG_Pos                (0U)\n#define FLASH_CR_PG_Msk                (0x1UL << FLASH_CR_PG_Pos)               /*!< 0x00000001 */\n#define FLASH_CR_PG                    FLASH_CR_PG_Msk\n#define FLASH_CR_SER_Pos               (1U)\n#define FLASH_CR_SER_Msk               (0x1UL << FLASH_CR_SER_Pos)              /*!< 0x00000002 */\n#define FLASH_CR_SER                   FLASH_CR_SER_Msk\n#define FLASH_CR_MER_Pos               (2U)\n#define FLASH_CR_MER_Msk               (0x1UL << FLASH_CR_MER_Pos)              /*!< 0x00000004 */\n#define FLASH_CR_MER                   FLASH_CR_MER_Msk\n#define FLASH_CR_SNB_Pos               (3U)\n#define FLASH_CR_SNB_Msk               (0x1FUL << FLASH_CR_SNB_Pos)             /*!< 0x000000F8 */\n#define FLASH_CR_SNB                   FLASH_CR_SNB_Msk\n#define FLASH_CR_SNB_0                 (0x01UL << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */\n#define FLASH_CR_SNB_1                 (0x02UL << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */\n#define FLASH_CR_SNB_2                 (0x04UL << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */\n#define FLASH_CR_SNB_3                 (0x08UL << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */\n#define FLASH_CR_SNB_4                 (0x10UL << FLASH_CR_SNB_Pos)             /*!< 0x00000080 */\n#define FLASH_CR_PSIZE_Pos             (8U)\n#define FLASH_CR_PSIZE_Msk             (0x3UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */\n#define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk\n#define FLASH_CR_PSIZE_0               (0x1UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */\n#define FLASH_CR_PSIZE_1               (0x2UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */\n#define FLASH_CR_STRT_Pos              (16U)\n#define FLASH_CR_STRT_Msk              (0x1UL << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */\n#define FLASH_CR_STRT                  FLASH_CR_STRT_Msk\n#define FLASH_CR_EOPIE_Pos             (24U)\n#define FLASH_CR_EOPIE_Msk             (0x1UL << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */\n#define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk\n#define FLASH_CR_LOCK_Pos              (31U)\n#define FLASH_CR_LOCK_Msk              (0x1UL << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */\n#define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk\n\n/*******************  Bits definition for FLASH_OPTCR register  ***************/\n#define FLASH_OPTCR_OPTLOCK_Pos        (0U)\n#define FLASH_OPTCR_OPTLOCK_Msk        (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */\n#define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk\n#define FLASH_OPTCR_OPTSTRT_Pos        (1U)\n#define FLASH_OPTCR_OPTSTRT_Msk        (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */\n#define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk\n\n#define FLASH_OPTCR_BOR_LEV_0          0x00000004U\n#define FLASH_OPTCR_BOR_LEV_1          0x00000008U\n#define FLASH_OPTCR_BOR_LEV_Pos        (2U)\n#define FLASH_OPTCR_BOR_LEV_Msk        (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */\n#define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk\n#define FLASH_OPTCR_WDG_SW_Pos         (5U)\n#define FLASH_OPTCR_WDG_SW_Msk         (0x1UL << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */\n#define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk\n#define FLASH_OPTCR_nRST_STOP_Pos      (6U)\n#define FLASH_OPTCR_nRST_STOP_Msk      (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */\n#define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk\n#define FLASH_OPTCR_nRST_STDBY_Pos     (7U)\n#define FLASH_OPTCR_nRST_STDBY_Msk     (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */\n#define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk\n#define FLASH_OPTCR_RDP_Pos            (8U)\n#define FLASH_OPTCR_RDP_Msk            (0xFFUL << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */\n#define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk\n#define FLASH_OPTCR_RDP_0              (0x01UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */\n#define FLASH_OPTCR_RDP_1              (0x02UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */\n#define FLASH_OPTCR_RDP_2              (0x04UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */\n#define FLASH_OPTCR_RDP_3              (0x08UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */\n#define FLASH_OPTCR_RDP_4              (0x10UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */\n#define FLASH_OPTCR_RDP_5              (0x20UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */\n#define FLASH_OPTCR_RDP_6              (0x40UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */\n#define FLASH_OPTCR_RDP_7              (0x80UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */\n#define FLASH_OPTCR_nWRP_Pos           (16U)\n#define FLASH_OPTCR_nWRP_Msk           (0xFFFUL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x0FFF0000 */\n#define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk\n#define FLASH_OPTCR_nWRP_0             0x00010000U\n#define FLASH_OPTCR_nWRP_1             0x00020000U\n#define FLASH_OPTCR_nWRP_2             0x00040000U\n#define FLASH_OPTCR_nWRP_3             0x00080000U\n#define FLASH_OPTCR_nWRP_4             0x00100000U\n#define FLASH_OPTCR_nWRP_5             0x00200000U\n#define FLASH_OPTCR_nWRP_6             0x00400000U\n#define FLASH_OPTCR_nWRP_7             0x00800000U\n#define FLASH_OPTCR_nWRP_8             0x01000000U\n#define FLASH_OPTCR_nWRP_9             0x02000000U\n#define FLASH_OPTCR_nWRP_10            0x04000000U\n#define FLASH_OPTCR_nWRP_11            0x08000000U\n\n/******************  Bits definition for FLASH_OPTCR1 register  ***************/\n#define FLASH_OPTCR1_nWRP_Pos          (16U)\n#define FLASH_OPTCR1_nWRP_Msk          (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */\n#define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk\n#define FLASH_OPTCR1_nWRP_0            (0x001UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */\n#define FLASH_OPTCR1_nWRP_1            (0x002UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */\n#define FLASH_OPTCR1_nWRP_2            (0x004UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */\n#define FLASH_OPTCR1_nWRP_3            (0x008UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */\n#define FLASH_OPTCR1_nWRP_4            (0x010UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */\n#define FLASH_OPTCR1_nWRP_5            (0x020UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */\n#define FLASH_OPTCR1_nWRP_6            (0x040UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */\n#define FLASH_OPTCR1_nWRP_7            (0x080UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */\n#define FLASH_OPTCR1_nWRP_8            (0x100UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */\n#define FLASH_OPTCR1_nWRP_9            (0x200UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */\n#define FLASH_OPTCR1_nWRP_10           (0x400UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */\n#define FLASH_OPTCR1_nWRP_11           (0x800UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                   Flexible Static Memory Controller                        */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for FSMC_BCR1 register  *******************/\n#define FSMC_BCR1_MBKEN_Pos          (0U)\n#define FSMC_BCR1_MBKEN_Msk          (0x1UL << FSMC_BCR1_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR1_MBKEN              FSMC_BCR1_MBKEN_Msk                       /*!<Memory bank enable bit                 */\n#define FSMC_BCR1_MUXEN_Pos          (1U)\n#define FSMC_BCR1_MUXEN_Msk          (0x1UL << FSMC_BCR1_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR1_MUXEN              FSMC_BCR1_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR1_MTYP_Pos           (2U)\n#define FSMC_BCR1_MTYP_Msk           (0x3UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR1_MTYP               FSMC_BCR1_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR1_MTYP_0             (0x1UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR1_MTYP_1             (0x2UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR1_MWID_Pos           (4U)\n#define FSMC_BCR1_MWID_Msk           (0x3UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR1_MWID               FSMC_BCR1_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR1_MWID_0             (0x1UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR1_MWID_1             (0x2UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR1_FACCEN_Pos         (6U)\n#define FSMC_BCR1_FACCEN_Msk         (0x1UL << FSMC_BCR1_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR1_FACCEN             FSMC_BCR1_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR1_BURSTEN_Pos        (8U)\n#define FSMC_BCR1_BURSTEN_Msk        (0x1UL << FSMC_BCR1_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR1_BURSTEN            FSMC_BCR1_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR1_WAITPOL_Pos        (9U)\n#define FSMC_BCR1_WAITPOL_Msk        (0x1UL << FSMC_BCR1_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR1_WAITPOL            FSMC_BCR1_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR1_WRAPMOD_Pos        (10U)\n#define FSMC_BCR1_WRAPMOD_Msk        (0x1UL << FSMC_BCR1_WRAPMOD_Pos)           /*!< 0x00000400 */\n#define FSMC_BCR1_WRAPMOD            FSMC_BCR1_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */\n#define FSMC_BCR1_WAITCFG_Pos        (11U)\n#define FSMC_BCR1_WAITCFG_Msk        (0x1UL << FSMC_BCR1_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR1_WAITCFG            FSMC_BCR1_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR1_WREN_Pos           (12U)\n#define FSMC_BCR1_WREN_Msk           (0x1UL << FSMC_BCR1_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR1_WREN               FSMC_BCR1_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR1_WAITEN_Pos         (13U)\n#define FSMC_BCR1_WAITEN_Msk         (0x1UL << FSMC_BCR1_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR1_WAITEN             FSMC_BCR1_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR1_EXTMOD_Pos         (14U)\n#define FSMC_BCR1_EXTMOD_Msk         (0x1UL << FSMC_BCR1_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR1_EXTMOD             FSMC_BCR1_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR1_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR1_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR1_ASYNCWAIT          FSMC_BCR1_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR1_CPSIZE_Pos         (16U)\n#define FSMC_BCR1_CPSIZE_Msk         (0x7UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR1_CPSIZE             FSMC_BCR1_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR1_CPSIZE_0           (0x1UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR1_CPSIZE_1           (0x2UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR1_CPSIZE_2           (0x4UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR1_CBURSTRW_Pos       (19U)\n#define FSMC_BCR1_CBURSTRW_Msk       (0x1UL << FSMC_BCR1_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR1_CBURSTRW           FSMC_BCR1_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BCR2 register  *******************/\n#define FSMC_BCR2_MBKEN_Pos          (0U)\n#define FSMC_BCR2_MBKEN_Msk          (0x1UL << FSMC_BCR2_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR2_MBKEN              FSMC_BCR2_MBKEN_Msk                       /*!<Memory bank enable bit                */\n#define FSMC_BCR2_MUXEN_Pos          (1U)\n#define FSMC_BCR2_MUXEN_Msk          (0x1UL << FSMC_BCR2_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR2_MUXEN              FSMC_BCR2_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR2_MTYP_Pos           (2U)\n#define FSMC_BCR2_MTYP_Msk           (0x3UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR2_MTYP               FSMC_BCR2_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR2_MTYP_0             (0x1UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR2_MTYP_1             (0x2UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR2_MWID_Pos           (4U)\n#define FSMC_BCR2_MWID_Msk           (0x3UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR2_MWID               FSMC_BCR2_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR2_MWID_0             (0x1UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR2_MWID_1             (0x2UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR2_FACCEN_Pos         (6U)\n#define FSMC_BCR2_FACCEN_Msk         (0x1UL << FSMC_BCR2_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR2_FACCEN             FSMC_BCR2_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR2_BURSTEN_Pos        (8U)\n#define FSMC_BCR2_BURSTEN_Msk        (0x1UL << FSMC_BCR2_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR2_BURSTEN            FSMC_BCR2_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR2_WAITPOL_Pos        (9U)\n#define FSMC_BCR2_WAITPOL_Msk        (0x1UL << FSMC_BCR2_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR2_WAITPOL            FSMC_BCR2_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR2_WRAPMOD_Pos        (10U)\n#define FSMC_BCR2_WRAPMOD_Msk        (0x1UL << FSMC_BCR2_WRAPMOD_Pos)           /*!< 0x00000400 */\n#define FSMC_BCR2_WRAPMOD            FSMC_BCR2_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */\n#define FSMC_BCR2_WAITCFG_Pos        (11U)\n#define FSMC_BCR2_WAITCFG_Msk        (0x1UL << FSMC_BCR2_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR2_WAITCFG            FSMC_BCR2_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR2_WREN_Pos           (12U)\n#define FSMC_BCR2_WREN_Msk           (0x1UL << FSMC_BCR2_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR2_WREN               FSMC_BCR2_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR2_WAITEN_Pos         (13U)\n#define FSMC_BCR2_WAITEN_Msk         (0x1UL << FSMC_BCR2_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR2_WAITEN             FSMC_BCR2_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR2_EXTMOD_Pos         (14U)\n#define FSMC_BCR2_EXTMOD_Msk         (0x1UL << FSMC_BCR2_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR2_EXTMOD             FSMC_BCR2_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR2_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR2_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR2_ASYNCWAIT          FSMC_BCR2_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR2_CPSIZE_Pos         (16U)\n#define FSMC_BCR2_CPSIZE_Msk         (0x7UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR2_CPSIZE             FSMC_BCR2_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR2_CPSIZE_0           (0x1UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR2_CPSIZE_1           (0x2UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR2_CPSIZE_2           (0x4UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR2_CBURSTRW_Pos       (19U)\n#define FSMC_BCR2_CBURSTRW_Msk       (0x1UL << FSMC_BCR2_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR2_CBURSTRW           FSMC_BCR2_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BCR3 register  *******************/\n#define FSMC_BCR3_MBKEN_Pos          (0U)\n#define FSMC_BCR3_MBKEN_Msk          (0x1UL << FSMC_BCR3_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR3_MBKEN              FSMC_BCR3_MBKEN_Msk                       /*!<Memory bank enable bit                 */\n#define FSMC_BCR3_MUXEN_Pos          (1U)\n#define FSMC_BCR3_MUXEN_Msk          (0x1UL << FSMC_BCR3_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR3_MUXEN              FSMC_BCR3_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR3_MTYP_Pos           (2U)\n#define FSMC_BCR3_MTYP_Msk           (0x3UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR3_MTYP               FSMC_BCR3_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR3_MTYP_0             (0x1UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR3_MTYP_1             (0x2UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR3_MWID_Pos           (4U)\n#define FSMC_BCR3_MWID_Msk           (0x3UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR3_MWID               FSMC_BCR3_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR3_MWID_0             (0x1UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR3_MWID_1             (0x2UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR3_FACCEN_Pos         (6U)\n#define FSMC_BCR3_FACCEN_Msk         (0x1UL << FSMC_BCR3_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR3_FACCEN             FSMC_BCR3_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR3_BURSTEN_Pos        (8U)\n#define FSMC_BCR3_BURSTEN_Msk        (0x1UL << FSMC_BCR3_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR3_BURSTEN            FSMC_BCR3_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR3_WAITPOL_Pos        (9U)\n#define FSMC_BCR3_WAITPOL_Msk        (0x1UL << FSMC_BCR3_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR3_WAITPOL            FSMC_BCR3_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR3_WRAPMOD_Pos        (10U)\n#define FSMC_BCR3_WRAPMOD_Msk        (0x1UL << FSMC_BCR3_WRAPMOD_Pos)           /*!< 0x00000400 */\n#define FSMC_BCR3_WRAPMOD            FSMC_BCR3_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */\n#define FSMC_BCR3_WAITCFG_Pos        (11U)\n#define FSMC_BCR3_WAITCFG_Msk        (0x1UL << FSMC_BCR3_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR3_WAITCFG            FSMC_BCR3_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR3_WREN_Pos           (12U)\n#define FSMC_BCR3_WREN_Msk           (0x1UL << FSMC_BCR3_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR3_WREN               FSMC_BCR3_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR3_WAITEN_Pos         (13U)\n#define FSMC_BCR3_WAITEN_Msk         (0x1UL << FSMC_BCR3_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR3_WAITEN             FSMC_BCR3_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR3_EXTMOD_Pos         (14U)\n#define FSMC_BCR3_EXTMOD_Msk         (0x1UL << FSMC_BCR3_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR3_EXTMOD             FSMC_BCR3_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR3_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR3_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR3_ASYNCWAIT          FSMC_BCR3_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR3_CPSIZE_Pos         (16U)\n#define FSMC_BCR3_CPSIZE_Msk         (0x7UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR3_CPSIZE             FSMC_BCR3_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR3_CPSIZE_0           (0x1UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR3_CPSIZE_1           (0x2UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR3_CPSIZE_2           (0x4UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR3_CBURSTRW_Pos       (19U)\n#define FSMC_BCR3_CBURSTRW_Msk       (0x1UL << FSMC_BCR3_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR3_CBURSTRW           FSMC_BCR3_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BCR4 register  *******************/\n#define FSMC_BCR4_MBKEN_Pos          (0U)\n#define FSMC_BCR4_MBKEN_Msk          (0x1UL << FSMC_BCR4_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR4_MBKEN              FSMC_BCR4_MBKEN_Msk                       /*!<Memory bank enable bit */\n#define FSMC_BCR4_MUXEN_Pos          (1U)\n#define FSMC_BCR4_MUXEN_Msk          (0x1UL << FSMC_BCR4_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR4_MUXEN              FSMC_BCR4_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR4_MTYP_Pos           (2U)\n#define FSMC_BCR4_MTYP_Msk           (0x3UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR4_MTYP               FSMC_BCR4_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR4_MTYP_0             (0x1UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR4_MTYP_1             (0x2UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR4_MWID_Pos           (4U)\n#define FSMC_BCR4_MWID_Msk           (0x3UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR4_MWID               FSMC_BCR4_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR4_MWID_0             (0x1UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR4_MWID_1             (0x2UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR4_FACCEN_Pos         (6U)\n#define FSMC_BCR4_FACCEN_Msk         (0x1UL << FSMC_BCR4_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR4_FACCEN             FSMC_BCR4_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR4_BURSTEN_Pos        (8U)\n#define FSMC_BCR4_BURSTEN_Msk        (0x1UL << FSMC_BCR4_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR4_BURSTEN            FSMC_BCR4_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR4_WAITPOL_Pos        (9U)\n#define FSMC_BCR4_WAITPOL_Msk        (0x1UL << FSMC_BCR4_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR4_WAITPOL            FSMC_BCR4_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR4_WRAPMOD_Pos        (10U)\n#define FSMC_BCR4_WRAPMOD_Msk        (0x1UL << FSMC_BCR4_WRAPMOD_Pos)           /*!< 0x00000400 */\n#define FSMC_BCR4_WRAPMOD            FSMC_BCR4_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */\n#define FSMC_BCR4_WAITCFG_Pos        (11U)\n#define FSMC_BCR4_WAITCFG_Msk        (0x1UL << FSMC_BCR4_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR4_WAITCFG            FSMC_BCR4_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR4_WREN_Pos           (12U)\n#define FSMC_BCR4_WREN_Msk           (0x1UL << FSMC_BCR4_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR4_WREN               FSMC_BCR4_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR4_WAITEN_Pos         (13U)\n#define FSMC_BCR4_WAITEN_Msk         (0x1UL << FSMC_BCR4_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR4_WAITEN             FSMC_BCR4_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR4_EXTMOD_Pos         (14U)\n#define FSMC_BCR4_EXTMOD_Msk         (0x1UL << FSMC_BCR4_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR4_EXTMOD             FSMC_BCR4_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR4_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR4_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR4_ASYNCWAIT          FSMC_BCR4_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR4_CPSIZE_Pos         (16U)\n#define FSMC_BCR4_CPSIZE_Msk         (0x7UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR4_CPSIZE             FSMC_BCR4_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR4_CPSIZE_0           (0x1UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR4_CPSIZE_1           (0x2UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR4_CPSIZE_2           (0x4UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR4_CBURSTRW_Pos       (19U)\n#define FSMC_BCR4_CBURSTRW_Msk       (0x1UL << FSMC_BCR4_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR4_CBURSTRW           FSMC_BCR4_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BTR1 register  ******************/\n#define FSMC_BTR1_ADDSET_Pos         (0U)\n#define FSMC_BTR1_ADDSET_Msk         (0xFUL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR1_ADDSET             FSMC_BTR1_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR1_ADDSET_0           (0x1UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR1_ADDSET_1           (0x2UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR1_ADDSET_2           (0x4UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR1_ADDSET_3           (0x8UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR1_ADDHLD_Pos         (4U)\n#define FSMC_BTR1_ADDHLD_Msk         (0xFUL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR1_ADDHLD             FSMC_BTR1_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR1_ADDHLD_0           (0x1UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR1_ADDHLD_1           (0x2UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR1_ADDHLD_2           (0x4UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR1_ADDHLD_3           (0x8UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR1_DATAST_Pos         (8U)\n#define FSMC_BTR1_DATAST_Msk         (0xFFUL << FSMC_BTR1_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR1_DATAST             FSMC_BTR1_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR1_DATAST_0           (0x01UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR1_DATAST_1           (0x02UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR1_DATAST_2           (0x04UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR1_DATAST_3           (0x08UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR1_DATAST_4           (0x10UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR1_DATAST_5           (0x20UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR1_DATAST_6           (0x40UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR1_DATAST_7           (0x80UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR1_BUSTURN_Pos        (16U)\n#define FSMC_BTR1_BUSTURN_Msk        (0xFUL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR1_BUSTURN            FSMC_BTR1_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR1_BUSTURN_0          (0x1UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR1_BUSTURN_1          (0x2UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR1_BUSTURN_2          (0x4UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR1_BUSTURN_3          (0x8UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR1_CLKDIV_Pos         (20U)\n#define FSMC_BTR1_CLKDIV_Msk         (0xFUL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR1_CLKDIV             FSMC_BTR1_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR1_CLKDIV_0           (0x1UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR1_CLKDIV_1           (0x2UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR1_CLKDIV_2           (0x4UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR1_CLKDIV_3           (0x8UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR1_DATLAT_Pos         (24U)\n#define FSMC_BTR1_DATLAT_Msk         (0xFUL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR1_DATLAT             FSMC_BTR1_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR1_DATLAT_0           (0x1UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR1_DATLAT_1           (0x2UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR1_DATLAT_2           (0x4UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR1_DATLAT_3           (0x8UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR1_ACCMOD_Pos         (28U)\n#define FSMC_BTR1_ACCMOD_Msk         (0x3UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR1_ACCMOD             FSMC_BTR1_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR1_ACCMOD_0           (0x1UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR1_ACCMOD_1           (0x2UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BTR2 register  *******************/\n#define FSMC_BTR2_ADDSET_Pos         (0U)\n#define FSMC_BTR2_ADDSET_Msk         (0xFUL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR2_ADDSET             FSMC_BTR2_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR2_ADDSET_0           (0x1UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR2_ADDSET_1           (0x2UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR2_ADDSET_2           (0x4UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR2_ADDSET_3           (0x8UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR2_ADDHLD_Pos         (4U)\n#define FSMC_BTR2_ADDHLD_Msk         (0xFUL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR2_ADDHLD             FSMC_BTR2_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR2_ADDHLD_0           (0x1UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR2_ADDHLD_1           (0x2UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR2_ADDHLD_2           (0x4UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR2_ADDHLD_3           (0x8UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR2_DATAST_Pos         (8U)\n#define FSMC_BTR2_DATAST_Msk         (0xFFUL << FSMC_BTR2_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR2_DATAST             FSMC_BTR2_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR2_DATAST_0           (0x01UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR2_DATAST_1           (0x02UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR2_DATAST_2           (0x04UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR2_DATAST_3           (0x08UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR2_DATAST_4           (0x10UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR2_DATAST_5           (0x20UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR2_DATAST_6           (0x40UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR2_DATAST_7           (0x80UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR2_BUSTURN_Pos        (16U)\n#define FSMC_BTR2_BUSTURN_Msk        (0xFUL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR2_BUSTURN            FSMC_BTR2_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR2_BUSTURN_0          (0x1UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR2_BUSTURN_1          (0x2UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR2_BUSTURN_2          (0x4UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR2_BUSTURN_3          (0x8UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR2_CLKDIV_Pos         (20U)\n#define FSMC_BTR2_CLKDIV_Msk         (0xFUL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR2_CLKDIV             FSMC_BTR2_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR2_CLKDIV_0           (0x1UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR2_CLKDIV_1           (0x2UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR2_CLKDIV_2           (0x4UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR2_CLKDIV_3           (0x8UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR2_DATLAT_Pos         (24U)\n#define FSMC_BTR2_DATLAT_Msk         (0xFUL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR2_DATLAT             FSMC_BTR2_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR2_DATLAT_0           (0x1UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR2_DATLAT_1           (0x2UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR2_DATLAT_2           (0x4UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR2_DATLAT_3           (0x8UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR2_ACCMOD_Pos         (28U)\n#define FSMC_BTR2_ACCMOD_Msk         (0x3UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR2_ACCMOD             FSMC_BTR2_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR2_ACCMOD_0           (0x1UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR2_ACCMOD_1           (0x2UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/*******************  Bit definition for FSMC_BTR3 register  *******************/\n#define FSMC_BTR3_ADDSET_Pos         (0U)\n#define FSMC_BTR3_ADDSET_Msk         (0xFUL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR3_ADDSET             FSMC_BTR3_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR3_ADDSET_0           (0x1UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR3_ADDSET_1           (0x2UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR3_ADDSET_2           (0x4UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR3_ADDSET_3           (0x8UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR3_ADDHLD_Pos         (4U)\n#define FSMC_BTR3_ADDHLD_Msk         (0xFUL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR3_ADDHLD             FSMC_BTR3_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR3_ADDHLD_0           (0x1UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR3_ADDHLD_1           (0x2UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR3_ADDHLD_2           (0x4UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR3_ADDHLD_3           (0x8UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR3_DATAST_Pos         (8U)\n#define FSMC_BTR3_DATAST_Msk         (0xFFUL << FSMC_BTR3_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR3_DATAST             FSMC_BTR3_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR3_DATAST_0           (0x01UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR3_DATAST_1           (0x02UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR3_DATAST_2           (0x04UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR3_DATAST_3           (0x08UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR3_DATAST_4           (0x10UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR3_DATAST_5           (0x20UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR3_DATAST_6           (0x40UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR3_DATAST_7           (0x80UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR3_BUSTURN_Pos        (16U)\n#define FSMC_BTR3_BUSTURN_Msk        (0xFUL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR3_BUSTURN            FSMC_BTR3_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR3_BUSTURN_0          (0x1UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR3_BUSTURN_1          (0x2UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR3_BUSTURN_2          (0x4UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR3_BUSTURN_3          (0x8UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR3_CLKDIV_Pos         (20U)\n#define FSMC_BTR3_CLKDIV_Msk         (0xFUL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR3_CLKDIV             FSMC_BTR3_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR3_CLKDIV_0           (0x1UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR3_CLKDIV_1           (0x2UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR3_CLKDIV_2           (0x4UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR3_CLKDIV_3           (0x8UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR3_DATLAT_Pos         (24U)\n#define FSMC_BTR3_DATLAT_Msk         (0xFUL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR3_DATLAT             FSMC_BTR3_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR3_DATLAT_0           (0x1UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR3_DATLAT_1           (0x2UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR3_DATLAT_2           (0x4UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR3_DATLAT_3           (0x8UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR3_ACCMOD_Pos         (28U)\n#define FSMC_BTR3_ACCMOD_Msk         (0x3UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR3_ACCMOD             FSMC_BTR3_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR3_ACCMOD_0           (0x1UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR3_ACCMOD_1           (0x2UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BTR4 register  *******************/\n#define FSMC_BTR4_ADDSET_Pos         (0U)\n#define FSMC_BTR4_ADDSET_Msk         (0xFUL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR4_ADDSET             FSMC_BTR4_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR4_ADDSET_0           (0x1UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR4_ADDSET_1           (0x2UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR4_ADDSET_2           (0x4UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR4_ADDSET_3           (0x8UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR4_ADDHLD_Pos         (4U)\n#define FSMC_BTR4_ADDHLD_Msk         (0xFUL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR4_ADDHLD             FSMC_BTR4_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR4_ADDHLD_0           (0x1UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR4_ADDHLD_1           (0x2UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR4_ADDHLD_2           (0x4UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR4_ADDHLD_3           (0x8UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR4_DATAST_Pos         (8U)\n#define FSMC_BTR4_DATAST_Msk         (0xFFUL << FSMC_BTR4_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR4_DATAST             FSMC_BTR4_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR4_DATAST_0           (0x01UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR4_DATAST_1           (0x02UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR4_DATAST_2           (0x04UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR4_DATAST_3           (0x08UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR4_DATAST_4           (0x10UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR4_DATAST_5           (0x20UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR4_DATAST_6           (0x40UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR4_DATAST_7           (0x80UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR4_BUSTURN_Pos        (16U)\n#define FSMC_BTR4_BUSTURN_Msk        (0xFUL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR4_BUSTURN            FSMC_BTR4_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR4_BUSTURN_0          (0x1UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR4_BUSTURN_1          (0x2UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR4_BUSTURN_2          (0x4UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR4_BUSTURN_3          (0x8UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR4_CLKDIV_Pos         (20U)\n#define FSMC_BTR4_CLKDIV_Msk         (0xFUL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR4_CLKDIV             FSMC_BTR4_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR4_CLKDIV_0           (0x1UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR4_CLKDIV_1           (0x2UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR4_CLKDIV_2           (0x4UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR4_CLKDIV_3           (0x8UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR4_DATLAT_Pos         (24U)\n#define FSMC_BTR4_DATLAT_Msk         (0xFUL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR4_DATLAT             FSMC_BTR4_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR4_DATLAT_0           (0x1UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR4_DATLAT_1           (0x2UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR4_DATLAT_2           (0x4UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR4_DATLAT_3           (0x8UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR4_ACCMOD_Pos         (28U)\n#define FSMC_BTR4_ACCMOD_Msk         (0x3UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR4_ACCMOD             FSMC_BTR4_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR4_ACCMOD_0           (0x1UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR4_ACCMOD_1           (0x2UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR1 register  ******************/\n#define FSMC_BWTR1_ADDSET_Pos        (0U)\n#define FSMC_BWTR1_ADDSET_Msk        (0xFUL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR1_ADDSET            FSMC_BWTR1_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR1_ADDSET_0          (0x1UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR1_ADDSET_1          (0x2UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR1_ADDSET_2          (0x4UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR1_ADDSET_3          (0x8UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR1_ADDHLD_Pos        (4U)\n#define FSMC_BWTR1_ADDHLD_Msk        (0xFUL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR1_ADDHLD            FSMC_BWTR1_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR1_ADDHLD_0          (0x1UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR1_ADDHLD_1          (0x2UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR1_ADDHLD_2          (0x4UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR1_ADDHLD_3          (0x8UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR1_DATAST_Pos        (8U)\n#define FSMC_BWTR1_DATAST_Msk        (0xFFUL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR1_DATAST            FSMC_BWTR1_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR1_DATAST_0          (0x01UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR1_DATAST_1          (0x02UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR1_DATAST_2          (0x04UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR1_DATAST_3          (0x08UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR1_DATAST_4          (0x10UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR1_DATAST_5          (0x20UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR1_DATAST_6          (0x40UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR1_DATAST_7          (0x80UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR1_BUSTURN_Pos       (16U)\n#define FSMC_BWTR1_BUSTURN_Msk       (0xFUL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR1_BUSTURN           FSMC_BWTR1_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR1_BUSTURN_0         (0x1UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR1_BUSTURN_1         (0x2UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR1_BUSTURN_2         (0x4UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR1_BUSTURN_3         (0x8UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR1_ACCMOD_Pos        (28U)\n#define FSMC_BWTR1_ACCMOD_Msk        (0x3UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR1_ACCMOD            FSMC_BWTR1_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR1_ACCMOD_0          (0x1UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR1_ACCMOD_1          (0x2UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR2 register  ******************/\n#define FSMC_BWTR2_ADDSET_Pos        (0U)\n#define FSMC_BWTR2_ADDSET_Msk        (0xFUL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR2_ADDSET            FSMC_BWTR2_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR2_ADDSET_0          (0x1UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR2_ADDSET_1          (0x2UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR2_ADDSET_2          (0x4UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR2_ADDSET_3          (0x8UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR2_ADDHLD_Pos        (4U)\n#define FSMC_BWTR2_ADDHLD_Msk        (0xFUL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR2_ADDHLD            FSMC_BWTR2_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR2_ADDHLD_0          (0x1UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR2_ADDHLD_1          (0x2UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR2_ADDHLD_2          (0x4UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR2_ADDHLD_3          (0x8UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR2_DATAST_Pos        (8U)\n#define FSMC_BWTR2_DATAST_Msk        (0xFFUL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR2_DATAST            FSMC_BWTR2_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR2_DATAST_0          (0x01UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR2_DATAST_1          (0x02UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR2_DATAST_2          (0x04UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR2_DATAST_3          (0x08UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR2_DATAST_4          (0x10UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR2_DATAST_5          (0x20UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR2_DATAST_6          (0x40UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR2_DATAST_7          (0x80UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR2_BUSTURN_Pos       (16U)\n#define FSMC_BWTR2_BUSTURN_Msk       (0xFUL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR2_BUSTURN           FSMC_BWTR2_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR2_BUSTURN_0         (0x1UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR2_BUSTURN_1         (0x2UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR2_BUSTURN_2         (0x4UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR2_BUSTURN_3         (0x8UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR2_ACCMOD_Pos        (28U)\n#define FSMC_BWTR2_ACCMOD_Msk        (0x3UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR2_ACCMOD            FSMC_BWTR2_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR2_ACCMOD_0          (0x1UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR2_ACCMOD_1          (0x2UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR3 register  ******************/\n#define FSMC_BWTR3_ADDSET_Pos        (0U)\n#define FSMC_BWTR3_ADDSET_Msk        (0xFUL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR3_ADDSET            FSMC_BWTR3_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR3_ADDSET_0          (0x1UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR3_ADDSET_1          (0x2UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR3_ADDSET_2          (0x4UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR3_ADDSET_3          (0x8UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR3_ADDHLD_Pos        (4U)\n#define FSMC_BWTR3_ADDHLD_Msk        (0xFUL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR3_ADDHLD            FSMC_BWTR3_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR3_ADDHLD_0          (0x1UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR3_ADDHLD_1          (0x2UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR3_ADDHLD_2          (0x4UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR3_ADDHLD_3          (0x8UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR3_DATAST_Pos        (8U)\n#define FSMC_BWTR3_DATAST_Msk        (0xFFUL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR3_DATAST            FSMC_BWTR3_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR3_DATAST_0          (0x01UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR3_DATAST_1          (0x02UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR3_DATAST_2          (0x04UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR3_DATAST_3          (0x08UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR3_DATAST_4          (0x10UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR3_DATAST_5          (0x20UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR3_DATAST_6          (0x40UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR3_DATAST_7          (0x80UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR3_BUSTURN_Pos       (16U)\n#define FSMC_BWTR3_BUSTURN_Msk       (0xFUL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR3_BUSTURN           FSMC_BWTR3_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR3_BUSTURN_0         (0x1UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR3_BUSTURN_1         (0x2UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR3_BUSTURN_2         (0x4UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR3_BUSTURN_3         (0x8UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR3_ACCMOD_Pos        (28U)\n#define FSMC_BWTR3_ACCMOD_Msk        (0x3UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR3_ACCMOD            FSMC_BWTR3_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR3_ACCMOD_0          (0x1UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR3_ACCMOD_1          (0x2UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR4 register  ******************/\n#define FSMC_BWTR4_ADDSET_Pos        (0U)\n#define FSMC_BWTR4_ADDSET_Msk        (0xFUL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR4_ADDSET            FSMC_BWTR4_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR4_ADDSET_0          (0x1UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR4_ADDSET_1          (0x2UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR4_ADDSET_2          (0x4UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR4_ADDSET_3          (0x8UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR4_ADDHLD_Pos        (4U)\n#define FSMC_BWTR4_ADDHLD_Msk        (0xFUL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR4_ADDHLD            FSMC_BWTR4_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR4_ADDHLD_0          (0x1UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR4_ADDHLD_1          (0x2UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR4_ADDHLD_2          (0x4UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR4_ADDHLD_3          (0x8UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR4_DATAST_Pos        (8U)\n#define FSMC_BWTR4_DATAST_Msk        (0xFFUL << FSMC_BWTR4_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR4_DATAST            FSMC_BWTR4_DATAST_Msk                     /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FSMC_BWTR4_DATAST_0          0x00000100U                               /*!<Bit 0 */\n#define FSMC_BWTR4_DATAST_1          0x00000200U                               /*!<Bit 1 */\n#define FSMC_BWTR4_DATAST_2          0x00000400U                               /*!<Bit 2 */\n#define FSMC_BWTR4_DATAST_3          0x00000800U                               /*!<Bit 3 */\n#define FSMC_BWTR4_DATAST_4          0x00001000U                               /*!<Bit 4 */\n#define FSMC_BWTR4_DATAST_5          0x00002000U                               /*!<Bit 5 */\n#define FSMC_BWTR4_DATAST_6          0x00004000U                               /*!<Bit 6 */\n#define FSMC_BWTR4_DATAST_7          0x00008000U                               /*!<Bit 7 */\n\n#define FSMC_BWTR4_BUSTURN_Pos       (16U)\n#define FSMC_BWTR4_BUSTURN_Msk       (0xFUL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR4_BUSTURN           FSMC_BWTR4_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR4_BUSTURN_0         (0x1UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR4_BUSTURN_1         (0x2UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR4_BUSTURN_2         (0x4UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR4_BUSTURN_3         (0x8UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR4_ACCMOD_Pos        (28U)\n#define FSMC_BWTR4_ACCMOD_Msk        (0x3UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR4_ACCMOD            FSMC_BWTR4_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR4_ACCMOD_0          (0x1UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR4_ACCMOD_1          (0x2UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_PCR2 register  *******************/\n#define FSMC_PCR2_PWAITEN_Pos        (1U)\n#define FSMC_PCR2_PWAITEN_Msk        (0x1UL << FSMC_PCR2_PWAITEN_Pos)           /*!< 0x00000002 */\n#define FSMC_PCR2_PWAITEN            FSMC_PCR2_PWAITEN_Msk                     /*!<Wait feature enable bit */\n#define FSMC_PCR2_PBKEN_Pos          (2U)\n#define FSMC_PCR2_PBKEN_Msk          (0x1UL << FSMC_PCR2_PBKEN_Pos)             /*!< 0x00000004 */\n#define FSMC_PCR2_PBKEN              FSMC_PCR2_PBKEN_Msk                       /*!<PC Card/NAND Flash memory bank enable bit */\n#define FSMC_PCR2_PTYP_Pos           (3U)\n#define FSMC_PCR2_PTYP_Msk           (0x1UL << FSMC_PCR2_PTYP_Pos)              /*!< 0x00000008 */\n#define FSMC_PCR2_PTYP               FSMC_PCR2_PTYP_Msk                        /*!<Memory type */\n\n#define FSMC_PCR2_PWID_Pos           (4U)\n#define FSMC_PCR2_PWID_Msk           (0x3UL << FSMC_PCR2_PWID_Pos)              /*!< 0x00000030 */\n#define FSMC_PCR2_PWID               FSMC_PCR2_PWID_Msk                        /*!<PWID[1:0] bits (NAND Flash databus width) */\n#define FSMC_PCR2_PWID_0             (0x1UL << FSMC_PCR2_PWID_Pos)              /*!< 0x00000010 */\n#define FSMC_PCR2_PWID_1             (0x2UL << FSMC_PCR2_PWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_PCR2_ECCEN_Pos          (6U)\n#define FSMC_PCR2_ECCEN_Msk          (0x1UL << FSMC_PCR2_ECCEN_Pos)             /*!< 0x00000040 */\n#define FSMC_PCR2_ECCEN              FSMC_PCR2_ECCEN_Msk                       /*!<ECC computation logic enable bit */\n\n#define FSMC_PCR2_TCLR_Pos           (9U)\n#define FSMC_PCR2_TCLR_Msk           (0xFUL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00001E00 */\n#define FSMC_PCR2_TCLR               FSMC_PCR2_TCLR_Msk                        /*!<TCLR[3:0] bits (CLE to RE delay) */\n#define FSMC_PCR2_TCLR_0             (0x1UL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00000200 */\n#define FSMC_PCR2_TCLR_1             (0x2UL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00000400 */\n#define FSMC_PCR2_TCLR_2             (0x4UL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00000800 */\n#define FSMC_PCR2_TCLR_3             (0x8UL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00001000 */\n\n#define FSMC_PCR2_TAR_Pos            (13U)\n#define FSMC_PCR2_TAR_Msk            (0xFUL << FSMC_PCR2_TAR_Pos)               /*!< 0x0001E000 */\n#define FSMC_PCR2_TAR                FSMC_PCR2_TAR_Msk                         /*!<TAR[3:0] bits (ALE to RE delay) */\n#define FSMC_PCR2_TAR_0              (0x1UL << FSMC_PCR2_TAR_Pos)               /*!< 0x00002000 */\n#define FSMC_PCR2_TAR_1              (0x2UL << FSMC_PCR2_TAR_Pos)               /*!< 0x00004000 */\n#define FSMC_PCR2_TAR_2              (0x4UL << FSMC_PCR2_TAR_Pos)               /*!< 0x00008000 */\n#define FSMC_PCR2_TAR_3              (0x8UL << FSMC_PCR2_TAR_Pos)               /*!< 0x00010000 */\n\n#define FSMC_PCR2_ECCPS_Pos          (17U)\n#define FSMC_PCR2_ECCPS_Msk          (0x7UL << FSMC_PCR2_ECCPS_Pos)             /*!< 0x000E0000 */\n#define FSMC_PCR2_ECCPS              FSMC_PCR2_ECCPS_Msk                       /*!<ECCPS[1:0] bits (ECC page size) */\n#define FSMC_PCR2_ECCPS_0            (0x1UL << FSMC_PCR2_ECCPS_Pos)             /*!< 0x00020000 */\n#define FSMC_PCR2_ECCPS_1            (0x2UL << FSMC_PCR2_ECCPS_Pos)             /*!< 0x00040000 */\n#define FSMC_PCR2_ECCPS_2            (0x4UL << FSMC_PCR2_ECCPS_Pos)             /*!< 0x00080000 */\n\n/******************  Bit definition for FSMC_PCR3 register  *******************/\n#define FSMC_PCR3_PWAITEN_Pos        (1U)\n#define FSMC_PCR3_PWAITEN_Msk        (0x1UL << FSMC_PCR3_PWAITEN_Pos)           /*!< 0x00000002 */\n#define FSMC_PCR3_PWAITEN            FSMC_PCR3_PWAITEN_Msk                     /*!<Wait feature enable bit */\n#define FSMC_PCR3_PBKEN_Pos          (2U)\n#define FSMC_PCR3_PBKEN_Msk          (0x1UL << FSMC_PCR3_PBKEN_Pos)             /*!< 0x00000004 */\n#define FSMC_PCR3_PBKEN              FSMC_PCR3_PBKEN_Msk                       /*!<PC Card/NAND Flash memory bank enable bit */\n#define FSMC_PCR3_PTYP_Pos           (3U)\n#define FSMC_PCR3_PTYP_Msk           (0x1UL << FSMC_PCR3_PTYP_Pos)              /*!< 0x00000008 */\n#define FSMC_PCR3_PTYP               FSMC_PCR3_PTYP_Msk                        /*!<Memory type */\n\n#define FSMC_PCR3_PWID_Pos           (4U)\n#define FSMC_PCR3_PWID_Msk           (0x3UL << FSMC_PCR3_PWID_Pos)              /*!< 0x00000030 */\n#define FSMC_PCR3_PWID               FSMC_PCR3_PWID_Msk                        /*!<PWID[1:0] bits (NAND Flash databus width) */\n#define FSMC_PCR3_PWID_0             (0x1UL << FSMC_PCR3_PWID_Pos)              /*!< 0x00000010 */\n#define FSMC_PCR3_PWID_1             (0x2UL << FSMC_PCR3_PWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_PCR3_ECCEN_Pos          (6U)\n#define FSMC_PCR3_ECCEN_Msk          (0x1UL << FSMC_PCR3_ECCEN_Pos)             /*!< 0x00000040 */\n#define FSMC_PCR3_ECCEN              FSMC_PCR3_ECCEN_Msk                       /*!<ECC computation logic enable bit */\n\n#define FSMC_PCR3_TCLR_Pos           (9U)\n#define FSMC_PCR3_TCLR_Msk           (0xFUL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00001E00 */\n#define FSMC_PCR3_TCLR               FSMC_PCR3_TCLR_Msk                        /*!<TCLR[3:0] bits (CLE to RE delay) */\n#define FSMC_PCR3_TCLR_0             (0x1UL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00000200 */\n#define FSMC_PCR3_TCLR_1             (0x2UL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00000400 */\n#define FSMC_PCR3_TCLR_2             (0x4UL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00000800 */\n#define FSMC_PCR3_TCLR_3             (0x8UL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00001000 */\n\n#define FSMC_PCR3_TAR_Pos            (13U)\n#define FSMC_PCR3_TAR_Msk            (0xFUL << FSMC_PCR3_TAR_Pos)               /*!< 0x0001E000 */\n#define FSMC_PCR3_TAR                FSMC_PCR3_TAR_Msk                         /*!<TAR[3:0] bits (ALE to RE delay) */\n#define FSMC_PCR3_TAR_0              (0x1UL << FSMC_PCR3_TAR_Pos)               /*!< 0x00002000 */\n#define FSMC_PCR3_TAR_1              (0x2UL << FSMC_PCR3_TAR_Pos)               /*!< 0x00004000 */\n#define FSMC_PCR3_TAR_2              (0x4UL << FSMC_PCR3_TAR_Pos)               /*!< 0x00008000 */\n#define FSMC_PCR3_TAR_3              (0x8UL << FSMC_PCR3_TAR_Pos)               /*!< 0x00010000 */\n\n#define FSMC_PCR3_ECCPS_Pos          (17U)\n#define FSMC_PCR3_ECCPS_Msk          (0x7UL << FSMC_PCR3_ECCPS_Pos)             /*!< 0x000E0000 */\n#define FSMC_PCR3_ECCPS              FSMC_PCR3_ECCPS_Msk                       /*!<ECCPS[2:0] bits (ECC page size) */\n#define FSMC_PCR3_ECCPS_0            (0x1UL << FSMC_PCR3_ECCPS_Pos)             /*!< 0x00020000 */\n#define FSMC_PCR3_ECCPS_1            (0x2UL << FSMC_PCR3_ECCPS_Pos)             /*!< 0x00040000 */\n#define FSMC_PCR3_ECCPS_2            (0x4UL << FSMC_PCR3_ECCPS_Pos)             /*!< 0x00080000 */\n\n/******************  Bit definition for FSMC_PCR4 register  *******************/\n#define FSMC_PCR4_PWAITEN_Pos        (1U)\n#define FSMC_PCR4_PWAITEN_Msk        (0x1UL << FSMC_PCR4_PWAITEN_Pos)           /*!< 0x00000002 */\n#define FSMC_PCR4_PWAITEN            FSMC_PCR4_PWAITEN_Msk                     /*!<Wait feature enable bit */\n#define FSMC_PCR4_PBKEN_Pos          (2U)\n#define FSMC_PCR4_PBKEN_Msk          (0x1UL << FSMC_PCR4_PBKEN_Pos)             /*!< 0x00000004 */\n#define FSMC_PCR4_PBKEN              FSMC_PCR4_PBKEN_Msk                       /*!<PC Card/NAND Flash memory bank enable bit */\n#define FSMC_PCR4_PTYP_Pos           (3U)\n#define FSMC_PCR4_PTYP_Msk           (0x1UL << FSMC_PCR4_PTYP_Pos)              /*!< 0x00000008 */\n#define FSMC_PCR4_PTYP               FSMC_PCR4_PTYP_Msk                        /*!<Memory type */\n\n#define FSMC_PCR4_PWID_Pos           (4U)\n#define FSMC_PCR4_PWID_Msk           (0x3UL << FSMC_PCR4_PWID_Pos)              /*!< 0x00000030 */\n#define FSMC_PCR4_PWID               FSMC_PCR4_PWID_Msk                        /*!<PWID[1:0] bits (NAND Flash databus width) */\n#define FSMC_PCR4_PWID_0             (0x1UL << FSMC_PCR4_PWID_Pos)              /*!< 0x00000010 */\n#define FSMC_PCR4_PWID_1             (0x2UL << FSMC_PCR4_PWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_PCR4_ECCEN_Pos          (6U)\n#define FSMC_PCR4_ECCEN_Msk          (0x1UL << FSMC_PCR4_ECCEN_Pos)             /*!< 0x00000040 */\n#define FSMC_PCR4_ECCEN              FSMC_PCR4_ECCEN_Msk                       /*!<ECC computation logic enable bit */\n\n#define FSMC_PCR4_TCLR_Pos           (9U)\n#define FSMC_PCR4_TCLR_Msk           (0xFUL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00001E00 */\n#define FSMC_PCR4_TCLR               FSMC_PCR4_TCLR_Msk                        /*!<TCLR[3:0] bits (CLE to RE delay) */\n#define FSMC_PCR4_TCLR_0             (0x1UL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00000200 */\n#define FSMC_PCR4_TCLR_1             (0x2UL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00000400 */\n#define FSMC_PCR4_TCLR_2             (0x4UL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00000800 */\n#define FSMC_PCR4_TCLR_3             (0x8UL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00001000 */\n\n#define FSMC_PCR4_TAR_Pos            (13U)\n#define FSMC_PCR4_TAR_Msk            (0xFUL << FSMC_PCR4_TAR_Pos)               /*!< 0x0001E000 */\n#define FSMC_PCR4_TAR                FSMC_PCR4_TAR_Msk                         /*!<TAR[3:0] bits (ALE to RE delay) */\n#define FSMC_PCR4_TAR_0              (0x1UL << FSMC_PCR4_TAR_Pos)               /*!< 0x00002000 */\n#define FSMC_PCR4_TAR_1              (0x2UL << FSMC_PCR4_TAR_Pos)               /*!< 0x00004000 */\n#define FSMC_PCR4_TAR_2              (0x4UL << FSMC_PCR4_TAR_Pos)               /*!< 0x00008000 */\n#define FSMC_PCR4_TAR_3              (0x8UL << FSMC_PCR4_TAR_Pos)               /*!< 0x00010000 */\n\n#define FSMC_PCR4_ECCPS_Pos          (17U)\n#define FSMC_PCR4_ECCPS_Msk          (0x7UL << FSMC_PCR4_ECCPS_Pos)             /*!< 0x000E0000 */\n#define FSMC_PCR4_ECCPS              FSMC_PCR4_ECCPS_Msk                       /*!<ECCPS[2:0] bits (ECC page size) */\n#define FSMC_PCR4_ECCPS_0            (0x1UL << FSMC_PCR4_ECCPS_Pos)             /*!< 0x00020000 */\n#define FSMC_PCR4_ECCPS_1            (0x2UL << FSMC_PCR4_ECCPS_Pos)             /*!< 0x00040000 */\n#define FSMC_PCR4_ECCPS_2            (0x4UL << FSMC_PCR4_ECCPS_Pos)             /*!< 0x00080000 */\n\n/*******************  Bit definition for FSMC_SR2 register  *******************/\n#define FSMC_SR2_IRS_Pos             (0U)\n#define FSMC_SR2_IRS_Msk             (0x1UL << FSMC_SR2_IRS_Pos)                /*!< 0x00000001 */\n#define FSMC_SR2_IRS                 FSMC_SR2_IRS_Msk                          /*!<Interrupt Rising Edge status                */\n#define FSMC_SR2_ILS_Pos             (1U)\n#define FSMC_SR2_ILS_Msk             (0x1UL << FSMC_SR2_ILS_Pos)                /*!< 0x00000002 */\n#define FSMC_SR2_ILS                 FSMC_SR2_ILS_Msk                          /*!<Interrupt Level status                      */\n#define FSMC_SR2_IFS_Pos             (2U)\n#define FSMC_SR2_IFS_Msk             (0x1UL << FSMC_SR2_IFS_Pos)                /*!< 0x00000004 */\n#define FSMC_SR2_IFS                 FSMC_SR2_IFS_Msk                          /*!<Interrupt Falling Edge status               */\n#define FSMC_SR2_IREN_Pos            (3U)\n#define FSMC_SR2_IREN_Msk            (0x1UL << FSMC_SR2_IREN_Pos)               /*!< 0x00000008 */\n#define FSMC_SR2_IREN                FSMC_SR2_IREN_Msk                         /*!<Interrupt Rising Edge detection Enable bit  */\n#define FSMC_SR2_ILEN_Pos            (4U)\n#define FSMC_SR2_ILEN_Msk            (0x1UL << FSMC_SR2_ILEN_Pos)               /*!< 0x00000010 */\n#define FSMC_SR2_ILEN                FSMC_SR2_ILEN_Msk                         /*!<Interrupt Level detection Enable bit        */\n#define FSMC_SR2_IFEN_Pos            (5U)\n#define FSMC_SR2_IFEN_Msk            (0x1UL << FSMC_SR2_IFEN_Pos)               /*!< 0x00000020 */\n#define FSMC_SR2_IFEN                FSMC_SR2_IFEN_Msk                         /*!<Interrupt Falling Edge detection Enable bit */\n#define FSMC_SR2_FEMPT_Pos           (6U)\n#define FSMC_SR2_FEMPT_Msk           (0x1UL << FSMC_SR2_FEMPT_Pos)              /*!< 0x00000040 */\n#define FSMC_SR2_FEMPT               FSMC_SR2_FEMPT_Msk                        /*!<FIFO empty */\n\n/*******************  Bit definition for FSMC_SR3 register  *******************/\n#define FSMC_SR3_IRS_Pos             (0U)\n#define FSMC_SR3_IRS_Msk             (0x1UL << FSMC_SR3_IRS_Pos)                /*!< 0x00000001 */\n#define FSMC_SR3_IRS                 FSMC_SR3_IRS_Msk                          /*!<Interrupt Rising Edge status                */\n#define FSMC_SR3_ILS_Pos             (1U)\n#define FSMC_SR3_ILS_Msk             (0x1UL << FSMC_SR3_ILS_Pos)                /*!< 0x00000002 */\n#define FSMC_SR3_ILS                 FSMC_SR3_ILS_Msk                          /*!<Interrupt Level status                      */\n#define FSMC_SR3_IFS_Pos             (2U)\n#define FSMC_SR3_IFS_Msk             (0x1UL << FSMC_SR3_IFS_Pos)                /*!< 0x00000004 */\n#define FSMC_SR3_IFS                 FSMC_SR3_IFS_Msk                          /*!<Interrupt Falling Edge status               */\n#define FSMC_SR3_IREN_Pos            (3U)\n#define FSMC_SR3_IREN_Msk            (0x1UL << FSMC_SR3_IREN_Pos)               /*!< 0x00000008 */\n#define FSMC_SR3_IREN                FSMC_SR3_IREN_Msk                         /*!<Interrupt Rising Edge detection Enable bit  */\n#define FSMC_SR3_ILEN_Pos            (4U)\n#define FSMC_SR3_ILEN_Msk            (0x1UL << FSMC_SR3_ILEN_Pos)               /*!< 0x00000010 */\n#define FSMC_SR3_ILEN                FSMC_SR3_ILEN_Msk                         /*!<Interrupt Level detection Enable bit        */\n#define FSMC_SR3_IFEN_Pos            (5U)\n#define FSMC_SR3_IFEN_Msk            (0x1UL << FSMC_SR3_IFEN_Pos)               /*!< 0x00000020 */\n#define FSMC_SR3_IFEN                FSMC_SR3_IFEN_Msk                         /*!<Interrupt Falling Edge detection Enable bit */\n#define FSMC_SR3_FEMPT_Pos           (6U)\n#define FSMC_SR3_FEMPT_Msk           (0x1UL << FSMC_SR3_FEMPT_Pos)              /*!< 0x00000040 */\n#define FSMC_SR3_FEMPT               FSMC_SR3_FEMPT_Msk                        /*!<FIFO empty */\n\n/*******************  Bit definition for FSMC_SR4 register  *******************/\n#define FSMC_SR4_IRS_Pos             (0U)\n#define FSMC_SR4_IRS_Msk             (0x1UL << FSMC_SR4_IRS_Pos)                /*!< 0x00000001 */\n#define FSMC_SR4_IRS                 FSMC_SR4_IRS_Msk                          /*!<Interrupt Rising Edge status                 */\n#define FSMC_SR4_ILS_Pos             (1U)\n#define FSMC_SR4_ILS_Msk             (0x1UL << FSMC_SR4_ILS_Pos)                /*!< 0x00000002 */\n#define FSMC_SR4_ILS                 FSMC_SR4_ILS_Msk                          /*!<Interrupt Level status                       */\n#define FSMC_SR4_IFS_Pos             (2U)\n#define FSMC_SR4_IFS_Msk             (0x1UL << FSMC_SR4_IFS_Pos)                /*!< 0x00000004 */\n#define FSMC_SR4_IFS                 FSMC_SR4_IFS_Msk                          /*!<Interrupt Falling Edge status                */\n#define FSMC_SR4_IREN_Pos            (3U)\n#define FSMC_SR4_IREN_Msk            (0x1UL << FSMC_SR4_IREN_Pos)               /*!< 0x00000008 */\n#define FSMC_SR4_IREN                FSMC_SR4_IREN_Msk                         /*!<Interrupt Rising Edge detection Enable bit   */\n#define FSMC_SR4_ILEN_Pos            (4U)\n#define FSMC_SR4_ILEN_Msk            (0x1UL << FSMC_SR4_ILEN_Pos)               /*!< 0x00000010 */\n#define FSMC_SR4_ILEN                FSMC_SR4_ILEN_Msk                         /*!<Interrupt Level detection Enable bit         */\n#define FSMC_SR4_IFEN_Pos            (5U)\n#define FSMC_SR4_IFEN_Msk            (0x1UL << FSMC_SR4_IFEN_Pos)               /*!< 0x00000020 */\n#define FSMC_SR4_IFEN                FSMC_SR4_IFEN_Msk                         /*!<Interrupt Falling Edge detection Enable bit  */\n#define FSMC_SR4_FEMPT_Pos           (6U)\n#define FSMC_SR4_FEMPT_Msk           (0x1UL << FSMC_SR4_FEMPT_Pos)              /*!< 0x00000040 */\n#define FSMC_SR4_FEMPT               FSMC_SR4_FEMPT_Msk                        /*!<FIFO empty */\n\n/******************  Bit definition for FSMC_PMEM2 register  ******************/\n#define FSMC_PMEM2_MEMSET2_Pos       (0U)\n#define FSMC_PMEM2_MEMSET2_Msk       (0xFFUL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x000000FF */\n#define FSMC_PMEM2_MEMSET2           FSMC_PMEM2_MEMSET2_Msk                    /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */\n#define FSMC_PMEM2_MEMSET2_0         (0x01UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000001 */\n#define FSMC_PMEM2_MEMSET2_1         (0x02UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000002 */\n#define FSMC_PMEM2_MEMSET2_2         (0x04UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000004 */\n#define FSMC_PMEM2_MEMSET2_3         (0x08UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000008 */\n#define FSMC_PMEM2_MEMSET2_4         (0x10UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000010 */\n#define FSMC_PMEM2_MEMSET2_5         (0x20UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000020 */\n#define FSMC_PMEM2_MEMSET2_6         (0x40UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000040 */\n#define FSMC_PMEM2_MEMSET2_7         (0x80UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000080 */\n\n#define FSMC_PMEM2_MEMWAIT2_Pos      (8U)\n#define FSMC_PMEM2_MEMWAIT2_Msk      (0xFFUL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x0000FF00 */\n#define FSMC_PMEM2_MEMWAIT2          FSMC_PMEM2_MEMWAIT2_Msk                   /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */\n#define FSMC_PMEM2_MEMWAIT2_0        (0x01UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000100 */\n#define FSMC_PMEM2_MEMWAIT2_1        (0x02UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000200 */\n#define FSMC_PMEM2_MEMWAIT2_2        (0x04UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000400 */\n#define FSMC_PMEM2_MEMWAIT2_3        (0x08UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000800 */\n#define FSMC_PMEM2_MEMWAIT2_4        (0x10UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00001000 */\n#define FSMC_PMEM2_MEMWAIT2_5        (0x20UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00002000 */\n#define FSMC_PMEM2_MEMWAIT2_6        (0x40UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00004000 */\n#define FSMC_PMEM2_MEMWAIT2_7        (0x80UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00008000 */\n\n#define FSMC_PMEM2_MEMHOLD2_Pos      (16U)\n#define FSMC_PMEM2_MEMHOLD2_Msk      (0xFFUL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00FF0000 */\n#define FSMC_PMEM2_MEMHOLD2          FSMC_PMEM2_MEMHOLD2_Msk                   /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */\n#define FSMC_PMEM2_MEMHOLD2_0        (0x01UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00010000 */\n#define FSMC_PMEM2_MEMHOLD2_1        (0x02UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00020000 */\n#define FSMC_PMEM2_MEMHOLD2_2        (0x04UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00040000 */\n#define FSMC_PMEM2_MEMHOLD2_3        (0x08UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00080000 */\n#define FSMC_PMEM2_MEMHOLD2_4        (0x10UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00100000 */\n#define FSMC_PMEM2_MEMHOLD2_5        (0x20UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00200000 */\n#define FSMC_PMEM2_MEMHOLD2_6        (0x40UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00400000 */\n#define FSMC_PMEM2_MEMHOLD2_7        (0x80UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00800000 */\n\n#define FSMC_PMEM2_MEMHIZ2_Pos       (24U)\n#define FSMC_PMEM2_MEMHIZ2_Msk       (0xFFUL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0xFF000000 */\n#define FSMC_PMEM2_MEMHIZ2           FSMC_PMEM2_MEMHIZ2_Msk                    /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */\n#define FSMC_PMEM2_MEMHIZ2_0         (0x01UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x01000000 */\n#define FSMC_PMEM2_MEMHIZ2_1         (0x02UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x02000000 */\n#define FSMC_PMEM2_MEMHIZ2_2         (0x04UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x04000000 */\n#define FSMC_PMEM2_MEMHIZ2_3         (0x08UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x08000000 */\n#define FSMC_PMEM2_MEMHIZ2_4         (0x10UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x10000000 */\n#define FSMC_PMEM2_MEMHIZ2_5         (0x20UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x20000000 */\n#define FSMC_PMEM2_MEMHIZ2_6         (0x40UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x40000000 */\n#define FSMC_PMEM2_MEMHIZ2_7         (0x80UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_PMEM3 register  ******************/\n#define FSMC_PMEM3_MEMSET3_Pos       (0U)\n#define FSMC_PMEM3_MEMSET3_Msk       (0xFFUL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x000000FF */\n#define FSMC_PMEM3_MEMSET3           FSMC_PMEM3_MEMSET3_Msk                    /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\n#define FSMC_PMEM3_MEMSET3_0         (0x01UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000001 */\n#define FSMC_PMEM3_MEMSET3_1         (0x02UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000002 */\n#define FSMC_PMEM3_MEMSET3_2         (0x04UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000004 */\n#define FSMC_PMEM3_MEMSET3_3         (0x08UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000008 */\n#define FSMC_PMEM3_MEMSET3_4         (0x10UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000010 */\n#define FSMC_PMEM3_MEMSET3_5         (0x20UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000020 */\n#define FSMC_PMEM3_MEMSET3_6         (0x40UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000040 */\n#define FSMC_PMEM3_MEMSET3_7         (0x80UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000080 */\n\n#define FSMC_PMEM3_MEMWAIT3_Pos      (8U)\n#define FSMC_PMEM3_MEMWAIT3_Msk      (0xFFUL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x0000FF00 */\n#define FSMC_PMEM3_MEMWAIT3          FSMC_PMEM3_MEMWAIT3_Msk                   /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\n#define FSMC_PMEM3_MEMWAIT3_0        (0x01UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000100 */\n#define FSMC_PMEM3_MEMWAIT3_1        (0x02UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000200 */\n#define FSMC_PMEM3_MEMWAIT3_2        (0x04UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000400 */\n#define FSMC_PMEM3_MEMWAIT3_3        (0x08UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000800 */\n#define FSMC_PMEM3_MEMWAIT3_4        (0x10UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00001000 */\n#define FSMC_PMEM3_MEMWAIT3_5        (0x20UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00002000 */\n#define FSMC_PMEM3_MEMWAIT3_6        (0x40UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00004000 */\n#define FSMC_PMEM3_MEMWAIT3_7        (0x80UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00008000 */\n\n#define FSMC_PMEM3_MEMHOLD3_Pos      (16U)\n#define FSMC_PMEM3_MEMHOLD3_Msk      (0xFFUL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00FF0000 */\n#define FSMC_PMEM3_MEMHOLD3          FSMC_PMEM3_MEMHOLD3_Msk                   /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\n#define FSMC_PMEM3_MEMHOLD3_0        (0x01UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00010000 */\n#define FSMC_PMEM3_MEMHOLD3_1        (0x02UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00020000 */\n#define FSMC_PMEM3_MEMHOLD3_2        (0x04UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00040000 */\n#define FSMC_PMEM3_MEMHOLD3_3        (0x08UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00080000 */\n#define FSMC_PMEM3_MEMHOLD3_4        (0x10UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00100000 */\n#define FSMC_PMEM3_MEMHOLD3_5        (0x20UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00200000 */\n#define FSMC_PMEM3_MEMHOLD3_6        (0x40UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00400000 */\n#define FSMC_PMEM3_MEMHOLD3_7        (0x80UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00800000 */\n\n#define FSMC_PMEM3_MEMHIZ3_Pos       (24U)\n#define FSMC_PMEM3_MEMHIZ3_Msk       (0xFFUL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0xFF000000 */\n#define FSMC_PMEM3_MEMHIZ3           FSMC_PMEM3_MEMHIZ3_Msk                    /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\n#define FSMC_PMEM3_MEMHIZ3_0         (0x01UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x01000000 */\n#define FSMC_PMEM3_MEMHIZ3_1         (0x02UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x02000000 */\n#define FSMC_PMEM3_MEMHIZ3_2         (0x04UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x04000000 */\n#define FSMC_PMEM3_MEMHIZ3_3         (0x08UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x08000000 */\n#define FSMC_PMEM3_MEMHIZ3_4         (0x10UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x10000000 */\n#define FSMC_PMEM3_MEMHIZ3_5         (0x20UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x20000000 */\n#define FSMC_PMEM3_MEMHIZ3_6         (0x40UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x40000000 */\n#define FSMC_PMEM3_MEMHIZ3_7         (0x80UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_PMEM4 register  ******************/\n#define FSMC_PMEM4_MEMSET4_Pos       (0U)\n#define FSMC_PMEM4_MEMSET4_Msk       (0xFFUL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x000000FF */\n#define FSMC_PMEM4_MEMSET4           FSMC_PMEM4_MEMSET4_Msk                    /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */\n#define FSMC_PMEM4_MEMSET4_0         (0x01UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000001 */\n#define FSMC_PMEM4_MEMSET4_1         (0x02UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000002 */\n#define FSMC_PMEM4_MEMSET4_2         (0x04UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000004 */\n#define FSMC_PMEM4_MEMSET4_3         (0x08UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000008 */\n#define FSMC_PMEM4_MEMSET4_4         (0x10UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000010 */\n#define FSMC_PMEM4_MEMSET4_5         (0x20UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000020 */\n#define FSMC_PMEM4_MEMSET4_6         (0x40UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000040 */\n#define FSMC_PMEM4_MEMSET4_7         (0x80UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000080 */\n\n#define FSMC_PMEM4_MEMWAIT4_Pos      (8U)\n#define FSMC_PMEM4_MEMWAIT4_Msk      (0xFFUL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x0000FF00 */\n#define FSMC_PMEM4_MEMWAIT4          FSMC_PMEM4_MEMWAIT4_Msk                   /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */\n#define FSMC_PMEM4_MEMWAIT4_0        (0x01UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000100 */\n#define FSMC_PMEM4_MEMWAIT4_1        (0x02UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000200 */\n#define FSMC_PMEM4_MEMWAIT4_2        (0x04UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000400 */\n#define FSMC_PMEM4_MEMWAIT4_3        (0x08UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000800 */\n#define FSMC_PMEM4_MEMWAIT4_4        (0x10UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00001000 */\n#define FSMC_PMEM4_MEMWAIT4_5        (0x20UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00002000 */\n#define FSMC_PMEM4_MEMWAIT4_6        (0x40UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00004000 */\n#define FSMC_PMEM4_MEMWAIT4_7        (0x80UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00008000 */\n\n#define FSMC_PMEM4_MEMHOLD4_Pos      (16U)\n#define FSMC_PMEM4_MEMHOLD4_Msk      (0xFFUL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00FF0000 */\n#define FSMC_PMEM4_MEMHOLD4          FSMC_PMEM4_MEMHOLD4_Msk                   /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */\n#define FSMC_PMEM4_MEMHOLD4_0        (0x01UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00010000 */\n#define FSMC_PMEM4_MEMHOLD4_1        (0x02UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00020000 */\n#define FSMC_PMEM4_MEMHOLD4_2        (0x04UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00040000 */\n#define FSMC_PMEM4_MEMHOLD4_3        (0x08UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00080000 */\n#define FSMC_PMEM4_MEMHOLD4_4        (0x10UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00100000 */\n#define FSMC_PMEM4_MEMHOLD4_5        (0x20UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00200000 */\n#define FSMC_PMEM4_MEMHOLD4_6        (0x40UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00400000 */\n#define FSMC_PMEM4_MEMHOLD4_7        (0x80UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00800000 */\n\n#define FSMC_PMEM4_MEMHIZ4_Pos       (24U)\n#define FSMC_PMEM4_MEMHIZ4_Msk       (0xFFUL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0xFF000000 */\n#define FSMC_PMEM4_MEMHIZ4           FSMC_PMEM4_MEMHIZ4_Msk                    /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */\n#define FSMC_PMEM4_MEMHIZ4_0         (0x01UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x01000000 */\n#define FSMC_PMEM4_MEMHIZ4_1         (0x02UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x02000000 */\n#define FSMC_PMEM4_MEMHIZ4_2         (0x04UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x04000000 */\n#define FSMC_PMEM4_MEMHIZ4_3         (0x08UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x08000000 */\n#define FSMC_PMEM4_MEMHIZ4_4         (0x10UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x10000000 */\n#define FSMC_PMEM4_MEMHIZ4_5         (0x20UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x20000000 */\n#define FSMC_PMEM4_MEMHIZ4_6         (0x40UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x40000000 */\n#define FSMC_PMEM4_MEMHIZ4_7         (0x80UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_PATT2 register  ******************/\n#define FSMC_PATT2_ATTSET2_Pos       (0U)\n#define FSMC_PATT2_ATTSET2_Msk       (0xFFUL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x000000FF */\n#define FSMC_PATT2_ATTSET2           FSMC_PATT2_ATTSET2_Msk                    /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */\n#define FSMC_PATT2_ATTSET2_0         (0x01UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000001 */\n#define FSMC_PATT2_ATTSET2_1         (0x02UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000002 */\n#define FSMC_PATT2_ATTSET2_2         (0x04UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000004 */\n#define FSMC_PATT2_ATTSET2_3         (0x08UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000008 */\n#define FSMC_PATT2_ATTSET2_4         (0x10UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000010 */\n#define FSMC_PATT2_ATTSET2_5         (0x20UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000020 */\n#define FSMC_PATT2_ATTSET2_6         (0x40UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000040 */\n#define FSMC_PATT2_ATTSET2_7         (0x80UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000080 */\n\n#define FSMC_PATT2_ATTWAIT2_Pos      (8U)\n#define FSMC_PATT2_ATTWAIT2_Msk      (0xFFUL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x0000FF00 */\n#define FSMC_PATT2_ATTWAIT2          FSMC_PATT2_ATTWAIT2_Msk                   /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */\n#define FSMC_PATT2_ATTWAIT2_0        (0x01UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000100 */\n#define FSMC_PATT2_ATTWAIT2_1        (0x02UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000200 */\n#define FSMC_PATT2_ATTWAIT2_2        (0x04UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000400 */\n#define FSMC_PATT2_ATTWAIT2_3        (0x08UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000800 */\n#define FSMC_PATT2_ATTWAIT2_4        (0x10UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00001000 */\n#define FSMC_PATT2_ATTWAIT2_5        (0x20UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00002000 */\n#define FSMC_PATT2_ATTWAIT2_6        (0x40UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00004000 */\n#define FSMC_PATT2_ATTWAIT2_7        (0x80UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00008000 */\n\n#define FSMC_PATT2_ATTHOLD2_Pos      (16U)\n#define FSMC_PATT2_ATTHOLD2_Msk      (0xFFUL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00FF0000 */\n#define FSMC_PATT2_ATTHOLD2          FSMC_PATT2_ATTHOLD2_Msk                   /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */\n#define FSMC_PATT2_ATTHOLD2_0        (0x01UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00010000 */\n#define FSMC_PATT2_ATTHOLD2_1        (0x02UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00020000 */\n#define FSMC_PATT2_ATTHOLD2_2        (0x04UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00040000 */\n#define FSMC_PATT2_ATTHOLD2_3        (0x08UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00080000 */\n#define FSMC_PATT2_ATTHOLD2_4        (0x10UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00100000 */\n#define FSMC_PATT2_ATTHOLD2_5        (0x20UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00200000 */\n#define FSMC_PATT2_ATTHOLD2_6        (0x40UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00400000 */\n#define FSMC_PATT2_ATTHOLD2_7        (0x80UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00800000 */\n\n#define FSMC_PATT2_ATTHIZ2_Pos       (24U)\n#define FSMC_PATT2_ATTHIZ2_Msk       (0xFFUL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0xFF000000 */\n#define FSMC_PATT2_ATTHIZ2           FSMC_PATT2_ATTHIZ2_Msk                    /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */\n#define FSMC_PATT2_ATTHIZ2_0         (0x01UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x01000000 */\n#define FSMC_PATT2_ATTHIZ2_1         (0x02UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x02000000 */\n#define FSMC_PATT2_ATTHIZ2_2         (0x04UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x04000000 */\n#define FSMC_PATT2_ATTHIZ2_3         (0x08UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x08000000 */\n#define FSMC_PATT2_ATTHIZ2_4         (0x10UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x10000000 */\n#define FSMC_PATT2_ATTHIZ2_5         (0x20UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x20000000 */\n#define FSMC_PATT2_ATTHIZ2_6         (0x40UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x40000000 */\n#define FSMC_PATT2_ATTHIZ2_7         (0x80UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_PATT3 register  ******************/\n#define FSMC_PATT3_ATTSET3_Pos       (0U)\n#define FSMC_PATT3_ATTSET3_Msk       (0xFFUL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x000000FF */\n#define FSMC_PATT3_ATTSET3           FSMC_PATT3_ATTSET3_Msk                    /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\n#define FSMC_PATT3_ATTSET3_0         (0x01UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000001 */\n#define FSMC_PATT3_ATTSET3_1         (0x02UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000002 */\n#define FSMC_PATT3_ATTSET3_2         (0x04UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000004 */\n#define FSMC_PATT3_ATTSET3_3         (0x08UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000008 */\n#define FSMC_PATT3_ATTSET3_4         (0x10UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000010 */\n#define FSMC_PATT3_ATTSET3_5         (0x20UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000020 */\n#define FSMC_PATT3_ATTSET3_6         (0x40UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000040 */\n#define FSMC_PATT3_ATTSET3_7         (0x80UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000080 */\n\n#define FSMC_PATT3_ATTWAIT3_Pos      (8U)\n#define FSMC_PATT3_ATTWAIT3_Msk      (0xFFUL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x0000FF00 */\n#define FSMC_PATT3_ATTWAIT3          FSMC_PATT3_ATTWAIT3_Msk                   /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\n#define FSMC_PATT3_ATTWAIT3_0        (0x01UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000100 */\n#define FSMC_PATT3_ATTWAIT3_1        (0x02UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000200 */\n#define FSMC_PATT3_ATTWAIT3_2        (0x04UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000400 */\n#define FSMC_PATT3_ATTWAIT3_3        (0x08UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000800 */\n#define FSMC_PATT3_ATTWAIT3_4        (0x10UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00001000 */\n#define FSMC_PATT3_ATTWAIT3_5        (0x20UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00002000 */\n#define FSMC_PATT3_ATTWAIT3_6        (0x40UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00004000 */\n#define FSMC_PATT3_ATTWAIT3_7        (0x80UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00008000 */\n\n#define FSMC_PATT3_ATTHOLD3_Pos      (16U)\n#define FSMC_PATT3_ATTHOLD3_Msk      (0xFFUL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00FF0000 */\n#define FSMC_PATT3_ATTHOLD3          FSMC_PATT3_ATTHOLD3_Msk                   /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\n#define FSMC_PATT3_ATTHOLD3_0        (0x01UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00010000 */\n#define FSMC_PATT3_ATTHOLD3_1        (0x02UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00020000 */\n#define FSMC_PATT3_ATTHOLD3_2        (0x04UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00040000 */\n#define FSMC_PATT3_ATTHOLD3_3        (0x08UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00080000 */\n#define FSMC_PATT3_ATTHOLD3_4        (0x10UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00100000 */\n#define FSMC_PATT3_ATTHOLD3_5        (0x20UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00200000 */\n#define FSMC_PATT3_ATTHOLD3_6        (0x40UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00400000 */\n#define FSMC_PATT3_ATTHOLD3_7        (0x80UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00800000 */\n\n#define FSMC_PATT3_ATTHIZ3_Pos       (24U)\n#define FSMC_PATT3_ATTHIZ3_Msk       (0xFFUL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0xFF000000 */\n#define FSMC_PATT3_ATTHIZ3           FSMC_PATT3_ATTHIZ3_Msk                    /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\n#define FSMC_PATT3_ATTHIZ3_0         (0x01UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x01000000 */\n#define FSMC_PATT3_ATTHIZ3_1         (0x02UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x02000000 */\n#define FSMC_PATT3_ATTHIZ3_2         (0x04UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x04000000 */\n#define FSMC_PATT3_ATTHIZ3_3         (0x08UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x08000000 */\n#define FSMC_PATT3_ATTHIZ3_4         (0x10UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x10000000 */\n#define FSMC_PATT3_ATTHIZ3_5         (0x20UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x20000000 */\n#define FSMC_PATT3_ATTHIZ3_6         (0x40UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x40000000 */\n#define FSMC_PATT3_ATTHIZ3_7         (0x80UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_PATT4 register  ******************/\n#define FSMC_PATT4_ATTSET4_Pos       (0U)\n#define FSMC_PATT4_ATTSET4_Msk       (0xFFUL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x000000FF */\n#define FSMC_PATT4_ATTSET4           FSMC_PATT4_ATTSET4_Msk                    /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */\n#define FSMC_PATT4_ATTSET4_0         (0x01UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000001 */\n#define FSMC_PATT4_ATTSET4_1         (0x02UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000002 */\n#define FSMC_PATT4_ATTSET4_2         (0x04UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000004 */\n#define FSMC_PATT4_ATTSET4_3         (0x08UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000008 */\n#define FSMC_PATT4_ATTSET4_4         (0x10UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000010 */\n#define FSMC_PATT4_ATTSET4_5         (0x20UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000020 */\n#define FSMC_PATT4_ATTSET4_6         (0x40UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000040 */\n#define FSMC_PATT4_ATTSET4_7         (0x80UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000080 */\n\n#define FSMC_PATT4_ATTWAIT4_Pos      (8U)\n#define FSMC_PATT4_ATTWAIT4_Msk      (0xFFUL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x0000FF00 */\n#define FSMC_PATT4_ATTWAIT4          FSMC_PATT4_ATTWAIT4_Msk                   /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */\n#define FSMC_PATT4_ATTWAIT4_0        (0x01UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000100 */\n#define FSMC_PATT4_ATTWAIT4_1        (0x02UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000200 */\n#define FSMC_PATT4_ATTWAIT4_2        (0x04UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000400 */\n#define FSMC_PATT4_ATTWAIT4_3        (0x08UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000800 */\n#define FSMC_PATT4_ATTWAIT4_4        (0x10UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00001000 */\n#define FSMC_PATT4_ATTWAIT4_5        (0x20UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00002000 */\n#define FSMC_PATT4_ATTWAIT4_6        (0x40UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00004000 */\n#define FSMC_PATT4_ATTWAIT4_7        (0x80UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00008000 */\n\n#define FSMC_PATT4_ATTHOLD4_Pos      (16U)\n#define FSMC_PATT4_ATTHOLD4_Msk      (0xFFUL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00FF0000 */\n#define FSMC_PATT4_ATTHOLD4          FSMC_PATT4_ATTHOLD4_Msk                   /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */\n#define FSMC_PATT4_ATTHOLD4_0        (0x01UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00010000 */\n#define FSMC_PATT4_ATTHOLD4_1        (0x02UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00020000 */\n#define FSMC_PATT4_ATTHOLD4_2        (0x04UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00040000 */\n#define FSMC_PATT4_ATTHOLD4_3        (0x08UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00080000 */\n#define FSMC_PATT4_ATTHOLD4_4        (0x10UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00100000 */\n#define FSMC_PATT4_ATTHOLD4_5        (0x20UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00200000 */\n#define FSMC_PATT4_ATTHOLD4_6        (0x40UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00400000 */\n#define FSMC_PATT4_ATTHOLD4_7        (0x80UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00800000 */\n\n#define FSMC_PATT4_ATTHIZ4_Pos       (24U)\n#define FSMC_PATT4_ATTHIZ4_Msk       (0xFFUL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0xFF000000 */\n#define FSMC_PATT4_ATTHIZ4           FSMC_PATT4_ATTHIZ4_Msk                    /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */\n#define FSMC_PATT4_ATTHIZ4_0         (0x01UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x01000000 */\n#define FSMC_PATT4_ATTHIZ4_1         (0x02UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x02000000 */\n#define FSMC_PATT4_ATTHIZ4_2         (0x04UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x04000000 */\n#define FSMC_PATT4_ATTHIZ4_3         (0x08UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x08000000 */\n#define FSMC_PATT4_ATTHIZ4_4         (0x10UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x10000000 */\n#define FSMC_PATT4_ATTHIZ4_5         (0x20UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x20000000 */\n#define FSMC_PATT4_ATTHIZ4_6         (0x40UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x40000000 */\n#define FSMC_PATT4_ATTHIZ4_7         (0x80UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_PIO4 register  *******************/\n#define FSMC_PIO4_IOSET4_Pos         (0U)\n#define FSMC_PIO4_IOSET4_Msk         (0xFFUL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x000000FF */\n#define FSMC_PIO4_IOSET4             FSMC_PIO4_IOSET4_Msk                      /*!<IOSET4[7:0] bits (I/O 4 setup time) */\n#define FSMC_PIO4_IOSET4_0           (0x01UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000001 */\n#define FSMC_PIO4_IOSET4_1           (0x02UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000002 */\n#define FSMC_PIO4_IOSET4_2           (0x04UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000004 */\n#define FSMC_PIO4_IOSET4_3           (0x08UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000008 */\n#define FSMC_PIO4_IOSET4_4           (0x10UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000010 */\n#define FSMC_PIO4_IOSET4_5           (0x20UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000020 */\n#define FSMC_PIO4_IOSET4_6           (0x40UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000040 */\n#define FSMC_PIO4_IOSET4_7           (0x80UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000080 */\n\n#define FSMC_PIO4_IOWAIT4_Pos        (8U)\n#define FSMC_PIO4_IOWAIT4_Msk        (0xFFUL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x0000FF00 */\n#define FSMC_PIO4_IOWAIT4            FSMC_PIO4_IOWAIT4_Msk                     /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */\n#define FSMC_PIO4_IOWAIT4_0          (0x01UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000100 */\n#define FSMC_PIO4_IOWAIT4_1          (0x02UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000200 */\n#define FSMC_PIO4_IOWAIT4_2          (0x04UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000400 */\n#define FSMC_PIO4_IOWAIT4_3          (0x08UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000800 */\n#define FSMC_PIO4_IOWAIT4_4          (0x10UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00001000 */\n#define FSMC_PIO4_IOWAIT4_5          (0x20UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00002000 */\n#define FSMC_PIO4_IOWAIT4_6          (0x40UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00004000 */\n#define FSMC_PIO4_IOWAIT4_7          (0x80UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00008000 */\n\n#define FSMC_PIO4_IOHOLD4_Pos        (16U)\n#define FSMC_PIO4_IOHOLD4_Msk        (0xFFUL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00FF0000 */\n#define FSMC_PIO4_IOHOLD4            FSMC_PIO4_IOHOLD4_Msk                     /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */\n#define FSMC_PIO4_IOHOLD4_0          (0x01UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00010000 */\n#define FSMC_PIO4_IOHOLD4_1          (0x02UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00020000 */\n#define FSMC_PIO4_IOHOLD4_2          (0x04UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00040000 */\n#define FSMC_PIO4_IOHOLD4_3          (0x08UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00080000 */\n#define FSMC_PIO4_IOHOLD4_4          (0x10UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00100000 */\n#define FSMC_PIO4_IOHOLD4_5          (0x20UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00200000 */\n#define FSMC_PIO4_IOHOLD4_6          (0x40UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00400000 */\n#define FSMC_PIO4_IOHOLD4_7          (0x80UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00800000 */\n\n#define FSMC_PIO4_IOHIZ4_Pos         (24U)\n#define FSMC_PIO4_IOHIZ4_Msk         (0xFFUL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0xFF000000 */\n#define FSMC_PIO4_IOHIZ4             FSMC_PIO4_IOHIZ4_Msk                      /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */\n#define FSMC_PIO4_IOHIZ4_0           (0x01UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x01000000 */\n#define FSMC_PIO4_IOHIZ4_1           (0x02UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x02000000 */\n#define FSMC_PIO4_IOHIZ4_2           (0x04UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x04000000 */\n#define FSMC_PIO4_IOHIZ4_3           (0x08UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x08000000 */\n#define FSMC_PIO4_IOHIZ4_4           (0x10UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x10000000 */\n#define FSMC_PIO4_IOHIZ4_5           (0x20UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x20000000 */\n#define FSMC_PIO4_IOHIZ4_6           (0x40UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x40000000 */\n#define FSMC_PIO4_IOHIZ4_7           (0x80UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_ECCR2 register  ******************/\n#define FSMC_ECCR2_ECC2_Pos          (0U)\n#define FSMC_ECCR2_ECC2_Msk          (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos)      /*!< 0xFFFFFFFF */\n#define FSMC_ECCR2_ECC2              FSMC_ECCR2_ECC2_Msk                       /*!<ECC result */\n\n/******************  Bit definition for FSMC_ECCR3 register  ******************/\n#define FSMC_ECCR3_ECC3_Pos          (0U)\n#define FSMC_ECCR3_ECC3_Msk          (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos)      /*!< 0xFFFFFFFF */\n#define FSMC_ECCR3_ECC3              FSMC_ECCR3_ECC3_Msk                       /*!<ECC result */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            General Purpose I/O                             */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bits definition for GPIO_MODER register  *****************/\n#define GPIO_MODER_MODER0_Pos            (0U)\n#define GPIO_MODER_MODER0_Msk            (0x3UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */\n#define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk\n#define GPIO_MODER_MODER0_0              (0x1UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */\n#define GPIO_MODER_MODER0_1              (0x2UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */\n#define GPIO_MODER_MODER1_Pos            (2U)\n#define GPIO_MODER_MODER1_Msk            (0x3UL << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */\n#define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk\n#define GPIO_MODER_MODER1_0              (0x1UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */\n#define GPIO_MODER_MODER1_1              (0x2UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */\n#define GPIO_MODER_MODER2_Pos            (4U)\n#define GPIO_MODER_MODER2_Msk            (0x3UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */\n#define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk\n#define GPIO_MODER_MODER2_0              (0x1UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */\n#define GPIO_MODER_MODER2_1              (0x2UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */\n#define GPIO_MODER_MODER3_Pos            (6U)\n#define GPIO_MODER_MODER3_Msk            (0x3UL << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */\n#define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk\n#define GPIO_MODER_MODER3_0              (0x1UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */\n#define GPIO_MODER_MODER3_1              (0x2UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */\n#define GPIO_MODER_MODER4_Pos            (8U)\n#define GPIO_MODER_MODER4_Msk            (0x3UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */\n#define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk\n#define GPIO_MODER_MODER4_0              (0x1UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */\n#define GPIO_MODER_MODER4_1              (0x2UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */\n#define GPIO_MODER_MODER5_Pos            (10U)\n#define GPIO_MODER_MODER5_Msk            (0x3UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */\n#define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk\n#define GPIO_MODER_MODER5_0              (0x1UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */\n#define GPIO_MODER_MODER5_1              (0x2UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */\n#define GPIO_MODER_MODER6_Pos            (12U)\n#define GPIO_MODER_MODER6_Msk            (0x3UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */\n#define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk\n#define GPIO_MODER_MODER6_0              (0x1UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */\n#define GPIO_MODER_MODER6_1              (0x2UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */\n#define GPIO_MODER_MODER7_Pos            (14U)\n#define GPIO_MODER_MODER7_Msk            (0x3UL << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */\n#define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk\n#define GPIO_MODER_MODER7_0              (0x1UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */\n#define GPIO_MODER_MODER7_1              (0x2UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */\n#define GPIO_MODER_MODER8_Pos            (16U)\n#define GPIO_MODER_MODER8_Msk            (0x3UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */\n#define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk\n#define GPIO_MODER_MODER8_0              (0x1UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */\n#define GPIO_MODER_MODER8_1              (0x2UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */\n#define GPIO_MODER_MODER9_Pos            (18U)\n#define GPIO_MODER_MODER9_Msk            (0x3UL << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */\n#define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk\n#define GPIO_MODER_MODER9_0              (0x1UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */\n#define GPIO_MODER_MODER9_1              (0x2UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */\n#define GPIO_MODER_MODER10_Pos           (20U)\n#define GPIO_MODER_MODER10_Msk           (0x3UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */\n#define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk\n#define GPIO_MODER_MODER10_0             (0x1UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */\n#define GPIO_MODER_MODER10_1             (0x2UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */\n#define GPIO_MODER_MODER11_Pos           (22U)\n#define GPIO_MODER_MODER11_Msk           (0x3UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */\n#define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk\n#define GPIO_MODER_MODER11_0             (0x1UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */\n#define GPIO_MODER_MODER11_1             (0x2UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */\n#define GPIO_MODER_MODER12_Pos           (24U)\n#define GPIO_MODER_MODER12_Msk           (0x3UL << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */\n#define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk\n#define GPIO_MODER_MODER12_0             (0x1UL << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */\n#define GPIO_MODER_MODER12_1             (0x2UL << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */\n#define GPIO_MODER_MODER13_Pos           (26U)\n#define GPIO_MODER_MODER13_Msk           (0x3UL << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */\n#define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk\n#define GPIO_MODER_MODER13_0             (0x1UL << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */\n#define GPIO_MODER_MODER13_1             (0x2UL << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */\n#define GPIO_MODER_MODER14_Pos           (28U)\n#define GPIO_MODER_MODER14_Msk           (0x3UL << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */\n#define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk\n#define GPIO_MODER_MODER14_0             (0x1UL << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */\n#define GPIO_MODER_MODER14_1             (0x2UL << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */\n#define GPIO_MODER_MODER15_Pos           (30U)\n#define GPIO_MODER_MODER15_Msk           (0x3UL << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */\n#define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk\n#define GPIO_MODER_MODER15_0             (0x1UL << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */\n#define GPIO_MODER_MODER15_1             (0x2UL << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_MODER_MODE0_Pos             GPIO_MODER_MODER0_Pos\n#define GPIO_MODER_MODE0_Msk             GPIO_MODER_MODER0_Msk\n#define GPIO_MODER_MODE0                 GPIO_MODER_MODER0\n#define GPIO_MODER_MODE0_0               GPIO_MODER_MODER0_0\n#define GPIO_MODER_MODE0_1               GPIO_MODER_MODER0_1\n#define GPIO_MODER_MODE1_Pos             GPIO_MODER_MODER1_Pos\n#define GPIO_MODER_MODE1_Msk             GPIO_MODER_MODER1_Msk\n#define GPIO_MODER_MODE1                 GPIO_MODER_MODER1\n#define GPIO_MODER_MODE1_0               GPIO_MODER_MODER1_0\n#define GPIO_MODER_MODE1_1               GPIO_MODER_MODER1_1\n#define GPIO_MODER_MODE2_Pos             GPIO_MODER_MODER2_PoS\n#define GPIO_MODER_MODE2_Msk             GPIO_MODER_MODER2_Msk\n#define GPIO_MODER_MODE2                 GPIO_MODER_MODER2\n#define GPIO_MODER_MODE2_0               GPIO_MODER_MODER2_0\n#define GPIO_MODER_MODE2_1               GPIO_MODER_MODER2_1\n#define GPIO_MODER_MODE3_Pos             GPIO_MODER_MODER3_Pos\n#define GPIO_MODER_MODE3_Msk             GPIO_MODER_MODER3_Msk\n#define GPIO_MODER_MODE3                 GPIO_MODER_MODER3\n#define GPIO_MODER_MODE3_0               GPIO_MODER_MODER3_0\n#define GPIO_MODER_MODE3_1               GPIO_MODER_MODER3_1\n#define GPIO_MODER_MODE4_Pos             GPIO_MODER_MODER4_Pos\n#define GPIO_MODER_MODE4_Msk             GPIO_MODER_MODER4_Msk\n#define GPIO_MODER_MODE4                 GPIO_MODER_MODER4\n#define GPIO_MODER_MODE4_0               GPIO_MODER_MODER4_0\n#define GPIO_MODER_MODE4_1               GPIO_MODER_MODER4_1\n#define GPIO_MODER_MODE5_Pos             GPIO_MODER_MODER5_Pos\n#define GPIO_MODER_MODE5_Msk             GPIO_MODER_MODER5_Msk\n#define GPIO_MODER_MODE5                 GPIO_MODER_MODER5\n#define GPIO_MODER_MODE5_0               GPIO_MODER_MODER5_0\n#define GPIO_MODER_MODE5_1               GPIO_MODER_MODER5_1\n#define GPIO_MODER_MODE6_Pos             GPIO_MODER_MODER6_Pos\n#define GPIO_MODER_MODE6_Msk             GPIO_MODER_MODER6_Msk\n#define GPIO_MODER_MODE6                 GPIO_MODER_MODER6\n#define GPIO_MODER_MODE6_0               GPIO_MODER_MODER6_0\n#define GPIO_MODER_MODE6_1               GPIO_MODER_MODER6_1\n#define GPIO_MODER_MODE7_Pos             GPIO_MODER_MODER7_Pos\n#define GPIO_MODER_MODE7_Msk             GPIO_MODER_MODER7_Msk\n#define GPIO_MODER_MODE7                 GPIO_MODER_MODER7\n#define GPIO_MODER_MODE7_0               GPIO_MODER_MODER7_0\n#define GPIO_MODER_MODE7_1               GPIO_MODER_MODER7_1\n#define GPIO_MODER_MODE8_Pos             GPIO_MODER_MODER8_Pos\n#define GPIO_MODER_MODE8_Msk             GPIO_MODER_MODER2_Msk\n#define GPIO_MODER_MODE8                 GPIO_MODER_MODER8\n#define GPIO_MODER_MODE8_0               GPIO_MODER_MODER8_0\n#define GPIO_MODER_MODE8_1               GPIO_MODER_MODER8_1\n#define GPIO_MODER_MODE9_Pos             GPIO_MODER_MODER9_Pos\n#define GPIO_MODER_MODE9_Msk             GPIO_MODER_MODER9_Msk\n#define GPIO_MODER_MODE9                 GPIO_MODER_MODER9\n#define GPIO_MODER_MODE9_0               GPIO_MODER_MODER9_0\n#define GPIO_MODER_MODE9_1               GPIO_MODER_MODER9_1\n#define GPIO_MODER_MODE10_Pos            GPIO_MODER_MODER10_Pos\n#define GPIO_MODER_MODE10_Msk            GPIO_MODER_MODER10_Msk\n#define GPIO_MODER_MODE10                GPIO_MODER_MODER10\n#define GPIO_MODER_MODE10_0              GPIO_MODER_MODER10_0\n#define GPIO_MODER_MODE10_1              GPIO_MODER_MODER10_1\n#define GPIO_MODER_MODE11_Pos            GPIO_MODER_MODER11_Pos\n#define GPIO_MODER_MODE11_Msk            GPIO_MODER_MODER11_Msk\n#define GPIO_MODER_MODE11                GPIO_MODER_MODER11\n#define GPIO_MODER_MODE11_0              GPIO_MODER_MODER11_0\n#define GPIO_MODER_MODE11_1              GPIO_MODER_MODER11_1\n#define GPIO_MODER_MODE12_Pos            GPIO_MODER_MODER12_Pos\n#define GPIO_MODER_MODE12_Msk            GPIO_MODER_MODER12_Msk\n#define GPIO_MODER_MODE12                GPIO_MODER_MODER12\n#define GPIO_MODER_MODE12_0              GPIO_MODER_MODER12_0\n#define GPIO_MODER_MODE12_1              GPIO_MODER_MODER12_1\n#define GPIO_MODER_MODE13_Pos            GPIO_MODER_MODER13_Pos\n#define GPIO_MODER_MODE13_Msk            GPIO_MODER_MODER13_Msk\n#define GPIO_MODER_MODE13                GPIO_MODER_MODER13\n#define GPIO_MODER_MODE13_0              GPIO_MODER_MODER13_0\n#define GPIO_MODER_MODE13_1              GPIO_MODER_MODER13_1\n#define GPIO_MODER_MODE14_Pos            GPIO_MODER_MODER14_Pos\n#define GPIO_MODER_MODE14_Msk            GPIO_MODER_MODER14_Msk\n#define GPIO_MODER_MODE14                GPIO_MODER_MODER14\n#define GPIO_MODER_MODE14_0              GPIO_MODER_MODER14_0\n#define GPIO_MODER_MODE14_1              GPIO_MODER_MODER14_1\n#define GPIO_MODER_MODE15_Pos            GPIO_MODER_MODER15_Pos\n#define GPIO_MODER_MODE15_Msk            GPIO_MODER_MODER15_Msk\n#define GPIO_MODER_MODE15                GPIO_MODER_MODER15\n#define GPIO_MODER_MODE15_0              GPIO_MODER_MODER15_0\n#define GPIO_MODER_MODE15_1              GPIO_MODER_MODER15_1\n\n/******************  Bits definition for GPIO_OTYPER register  ****************/\n#define GPIO_OTYPER_OT0_Pos              (0U)\n#define GPIO_OTYPER_OT0_Msk              (0x1UL << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */\n#define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk\n#define GPIO_OTYPER_OT1_Pos              (1U)\n#define GPIO_OTYPER_OT1_Msk              (0x1UL << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */\n#define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk\n#define GPIO_OTYPER_OT2_Pos              (2U)\n#define GPIO_OTYPER_OT2_Msk              (0x1UL << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */\n#define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk\n#define GPIO_OTYPER_OT3_Pos              (3U)\n#define GPIO_OTYPER_OT3_Msk              (0x1UL << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */\n#define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk\n#define GPIO_OTYPER_OT4_Pos              (4U)\n#define GPIO_OTYPER_OT4_Msk              (0x1UL << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */\n#define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk\n#define GPIO_OTYPER_OT5_Pos              (5U)\n#define GPIO_OTYPER_OT5_Msk              (0x1UL << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */\n#define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk\n#define GPIO_OTYPER_OT6_Pos              (6U)\n#define GPIO_OTYPER_OT6_Msk              (0x1UL << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */\n#define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk\n#define GPIO_OTYPER_OT7_Pos              (7U)\n#define GPIO_OTYPER_OT7_Msk              (0x1UL << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */\n#define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk\n#define GPIO_OTYPER_OT8_Pos              (8U)\n#define GPIO_OTYPER_OT8_Msk              (0x1UL << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */\n#define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk\n#define GPIO_OTYPER_OT9_Pos              (9U)\n#define GPIO_OTYPER_OT9_Msk              (0x1UL << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */\n#define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk\n#define GPIO_OTYPER_OT10_Pos             (10U)\n#define GPIO_OTYPER_OT10_Msk             (0x1UL << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */\n#define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk\n#define GPIO_OTYPER_OT11_Pos             (11U)\n#define GPIO_OTYPER_OT11_Msk             (0x1UL << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */\n#define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk\n#define GPIO_OTYPER_OT12_Pos             (12U)\n#define GPIO_OTYPER_OT12_Msk             (0x1UL << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */\n#define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk\n#define GPIO_OTYPER_OT13_Pos             (13U)\n#define GPIO_OTYPER_OT13_Msk             (0x1UL << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */\n#define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk\n#define GPIO_OTYPER_OT14_Pos             (14U)\n#define GPIO_OTYPER_OT14_Msk             (0x1UL << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */\n#define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk\n#define GPIO_OTYPER_OT15_Pos             (15U)\n#define GPIO_OTYPER_OT15_Msk             (0x1UL << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */\n#define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk\n\n/* Legacy defines */\n#define GPIO_OTYPER_OT_0                 GPIO_OTYPER_OT0\n#define GPIO_OTYPER_OT_1                 GPIO_OTYPER_OT1\n#define GPIO_OTYPER_OT_2                 GPIO_OTYPER_OT2\n#define GPIO_OTYPER_OT_3                 GPIO_OTYPER_OT3\n#define GPIO_OTYPER_OT_4                 GPIO_OTYPER_OT4\n#define GPIO_OTYPER_OT_5                 GPIO_OTYPER_OT5\n#define GPIO_OTYPER_OT_6                 GPIO_OTYPER_OT6\n#define GPIO_OTYPER_OT_7                 GPIO_OTYPER_OT7\n#define GPIO_OTYPER_OT_8                 GPIO_OTYPER_OT8\n#define GPIO_OTYPER_OT_9                 GPIO_OTYPER_OT9\n#define GPIO_OTYPER_OT_10                GPIO_OTYPER_OT10\n#define GPIO_OTYPER_OT_11                GPIO_OTYPER_OT11\n#define GPIO_OTYPER_OT_12                GPIO_OTYPER_OT12\n#define GPIO_OTYPER_OT_13                GPIO_OTYPER_OT13\n#define GPIO_OTYPER_OT_14                GPIO_OTYPER_OT14\n#define GPIO_OTYPER_OT_15                GPIO_OTYPER_OT15\n\n/******************  Bits definition for GPIO_OSPEEDR register  ***************/\n#define GPIO_OSPEEDR_OSPEED0_Pos         (0U)\n#define GPIO_OSPEEDR_OSPEED0_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000003 */\n#define GPIO_OSPEEDR_OSPEED0             GPIO_OSPEEDR_OSPEED0_Msk\n#define GPIO_OSPEEDR_OSPEED0_0           (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000001 */\n#define GPIO_OSPEEDR_OSPEED0_1           (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000002 */\n#define GPIO_OSPEEDR_OSPEED1_Pos         (2U)\n#define GPIO_OSPEEDR_OSPEED1_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x0000000C */\n#define GPIO_OSPEEDR_OSPEED1             GPIO_OSPEEDR_OSPEED1_Msk\n#define GPIO_OSPEEDR_OSPEED1_0           (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000004 */\n#define GPIO_OSPEEDR_OSPEED1_1           (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000008 */\n#define GPIO_OSPEEDR_OSPEED2_Pos         (4U)\n#define GPIO_OSPEEDR_OSPEED2_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000030 */\n#define GPIO_OSPEEDR_OSPEED2             GPIO_OSPEEDR_OSPEED2_Msk\n#define GPIO_OSPEEDR_OSPEED2_0           (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000010 */\n#define GPIO_OSPEEDR_OSPEED2_1           (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000020 */\n#define GPIO_OSPEEDR_OSPEED3_Pos         (6U)\n#define GPIO_OSPEEDR_OSPEED3_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x000000C0 */\n#define GPIO_OSPEEDR_OSPEED3             GPIO_OSPEEDR_OSPEED3_Msk\n#define GPIO_OSPEEDR_OSPEED3_0           (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000040 */\n#define GPIO_OSPEEDR_OSPEED3_1           (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000080 */\n#define GPIO_OSPEEDR_OSPEED4_Pos         (8U)\n#define GPIO_OSPEEDR_OSPEED4_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000300 */\n#define GPIO_OSPEEDR_OSPEED4             GPIO_OSPEEDR_OSPEED4_Msk\n#define GPIO_OSPEEDR_OSPEED4_0           (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000100 */\n#define GPIO_OSPEEDR_OSPEED4_1           (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000200 */\n#define GPIO_OSPEEDR_OSPEED5_Pos         (10U)\n#define GPIO_OSPEEDR_OSPEED5_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000C00 */\n#define GPIO_OSPEEDR_OSPEED5             GPIO_OSPEEDR_OSPEED5_Msk\n#define GPIO_OSPEEDR_OSPEED5_0           (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000400 */\n#define GPIO_OSPEEDR_OSPEED5_1           (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000800 */\n#define GPIO_OSPEEDR_OSPEED6_Pos         (12U)\n#define GPIO_OSPEEDR_OSPEED6_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00003000 */\n#define GPIO_OSPEEDR_OSPEED6             GPIO_OSPEEDR_OSPEED6_Msk\n#define GPIO_OSPEEDR_OSPEED6_0           (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00001000 */\n#define GPIO_OSPEEDR_OSPEED6_1           (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00002000 */\n#define GPIO_OSPEEDR_OSPEED7_Pos         (14U)\n#define GPIO_OSPEEDR_OSPEED7_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x0000C000 */\n#define GPIO_OSPEEDR_OSPEED7             GPIO_OSPEEDR_OSPEED7_Msk\n#define GPIO_OSPEEDR_OSPEED7_0           (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00004000 */\n#define GPIO_OSPEEDR_OSPEED7_1           (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00008000 */\n#define GPIO_OSPEEDR_OSPEED8_Pos         (16U)\n#define GPIO_OSPEEDR_OSPEED8_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00030000 */\n#define GPIO_OSPEEDR_OSPEED8             GPIO_OSPEEDR_OSPEED8_Msk\n#define GPIO_OSPEEDR_OSPEED8_0           (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00010000 */\n#define GPIO_OSPEEDR_OSPEED8_1           (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00020000 */\n#define GPIO_OSPEEDR_OSPEED9_Pos         (18U)\n#define GPIO_OSPEEDR_OSPEED9_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x000C0000 */\n#define GPIO_OSPEEDR_OSPEED9             GPIO_OSPEEDR_OSPEED9_Msk\n#define GPIO_OSPEEDR_OSPEED9_0           (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00040000 */\n#define GPIO_OSPEEDR_OSPEED9_1           (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00080000 */\n#define GPIO_OSPEEDR_OSPEED10_Pos        (20U)\n#define GPIO_OSPEEDR_OSPEED10_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00300000 */\n#define GPIO_OSPEEDR_OSPEED10            GPIO_OSPEEDR_OSPEED10_Msk\n#define GPIO_OSPEEDR_OSPEED10_0          (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00100000 */\n#define GPIO_OSPEEDR_OSPEED10_1          (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00200000 */\n#define GPIO_OSPEEDR_OSPEED11_Pos        (22U)\n#define GPIO_OSPEEDR_OSPEED11_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00C00000 */\n#define GPIO_OSPEEDR_OSPEED11            GPIO_OSPEEDR_OSPEED11_Msk\n#define GPIO_OSPEEDR_OSPEED11_0          (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00400000 */\n#define GPIO_OSPEEDR_OSPEED11_1          (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00800000 */\n#define GPIO_OSPEEDR_OSPEED12_Pos        (24U)\n#define GPIO_OSPEEDR_OSPEED12_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x03000000 */\n#define GPIO_OSPEEDR_OSPEED12            GPIO_OSPEEDR_OSPEED12_Msk\n#define GPIO_OSPEEDR_OSPEED12_0          (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x01000000 */\n#define GPIO_OSPEEDR_OSPEED12_1          (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x02000000 */\n#define GPIO_OSPEEDR_OSPEED13_Pos        (26U)\n#define GPIO_OSPEEDR_OSPEED13_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x0C000000 */\n#define GPIO_OSPEEDR_OSPEED13            GPIO_OSPEEDR_OSPEED13_Msk\n#define GPIO_OSPEEDR_OSPEED13_0          (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x04000000 */\n#define GPIO_OSPEEDR_OSPEED13_1          (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x08000000 */\n#define GPIO_OSPEEDR_OSPEED14_Pos        (28U)\n#define GPIO_OSPEEDR_OSPEED14_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x30000000 */\n#define GPIO_OSPEEDR_OSPEED14            GPIO_OSPEEDR_OSPEED14_Msk\n#define GPIO_OSPEEDR_OSPEED14_0          (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x10000000 */\n#define GPIO_OSPEEDR_OSPEED14_1          (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x20000000 */\n#define GPIO_OSPEEDR_OSPEED15_Pos        (30U)\n#define GPIO_OSPEEDR_OSPEED15_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0xC0000000 */\n#define GPIO_OSPEEDR_OSPEED15            GPIO_OSPEEDR_OSPEED15_Msk\n#define GPIO_OSPEEDR_OSPEED15_0          (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x40000000 */\n#define GPIO_OSPEEDR_OSPEED15_1          (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDR_OSPEED0\n#define GPIO_OSPEEDER_OSPEEDR0_0         GPIO_OSPEEDR_OSPEED0_0\n#define GPIO_OSPEEDER_OSPEEDR0_1         GPIO_OSPEEDR_OSPEED0_1\n#define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDR_OSPEED1\n#define GPIO_OSPEEDER_OSPEEDR1_0         GPIO_OSPEEDR_OSPEED1_0\n#define GPIO_OSPEEDER_OSPEEDR1_1         GPIO_OSPEEDR_OSPEED1_1\n#define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDR_OSPEED2\n#define GPIO_OSPEEDER_OSPEEDR2_0         GPIO_OSPEEDR_OSPEED2_0\n#define GPIO_OSPEEDER_OSPEEDR2_1         GPIO_OSPEEDR_OSPEED2_1\n#define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDR_OSPEED3\n#define GPIO_OSPEEDER_OSPEEDR3_0         GPIO_OSPEEDR_OSPEED3_0\n#define GPIO_OSPEEDER_OSPEEDR3_1         GPIO_OSPEEDR_OSPEED3_1\n#define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDR_OSPEED4\n#define GPIO_OSPEEDER_OSPEEDR4_0         GPIO_OSPEEDR_OSPEED4_0\n#define GPIO_OSPEEDER_OSPEEDR4_1         GPIO_OSPEEDR_OSPEED4_1\n#define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDR_OSPEED5\n#define GPIO_OSPEEDER_OSPEEDR5_0         GPIO_OSPEEDR_OSPEED5_0\n#define GPIO_OSPEEDER_OSPEEDR5_1         GPIO_OSPEEDR_OSPEED5_1\n#define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDR_OSPEED6\n#define GPIO_OSPEEDER_OSPEEDR6_0         GPIO_OSPEEDR_OSPEED6_0\n#define GPIO_OSPEEDER_OSPEEDR6_1         GPIO_OSPEEDR_OSPEED6_1\n#define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDR_OSPEED7\n#define GPIO_OSPEEDER_OSPEEDR7_0         GPIO_OSPEEDR_OSPEED7_0\n#define GPIO_OSPEEDER_OSPEEDR7_1         GPIO_OSPEEDR_OSPEED7_1\n#define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDR_OSPEED8\n#define GPIO_OSPEEDER_OSPEEDR8_0         GPIO_OSPEEDR_OSPEED8_0\n#define GPIO_OSPEEDER_OSPEEDR8_1         GPIO_OSPEEDR_OSPEED8_1\n#define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDR_OSPEED9\n#define GPIO_OSPEEDER_OSPEEDR9_0         GPIO_OSPEEDR_OSPEED9_0\n#define GPIO_OSPEEDER_OSPEEDR9_1         GPIO_OSPEEDR_OSPEED9_1\n#define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDR_OSPEED10\n#define GPIO_OSPEEDER_OSPEEDR10_0        GPIO_OSPEEDR_OSPEED10_0\n#define GPIO_OSPEEDER_OSPEEDR10_1        GPIO_OSPEEDR_OSPEED10_1\n#define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDR_OSPEED11\n#define GPIO_OSPEEDER_OSPEEDR11_0        GPIO_OSPEEDR_OSPEED11_0\n#define GPIO_OSPEEDER_OSPEEDR11_1        GPIO_OSPEEDR_OSPEED11_1\n#define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDR_OSPEED12\n#define GPIO_OSPEEDER_OSPEEDR12_0        GPIO_OSPEEDR_OSPEED12_0\n#define GPIO_OSPEEDER_OSPEEDR12_1        GPIO_OSPEEDR_OSPEED12_1\n#define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDR_OSPEED13\n#define GPIO_OSPEEDER_OSPEEDR13_0        GPIO_OSPEEDR_OSPEED13_0\n#define GPIO_OSPEEDER_OSPEEDR13_1        GPIO_OSPEEDR_OSPEED13_1\n#define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDR_OSPEED14\n#define GPIO_OSPEEDER_OSPEEDR14_0        GPIO_OSPEEDR_OSPEED14_0\n#define GPIO_OSPEEDER_OSPEEDR14_1        GPIO_OSPEEDR_OSPEED14_1\n#define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDR_OSPEED15\n#define GPIO_OSPEEDER_OSPEEDR15_0        GPIO_OSPEEDR_OSPEED15_0\n#define GPIO_OSPEEDER_OSPEEDR15_1        GPIO_OSPEEDR_OSPEED15_1\n\n/******************  Bits definition for GPIO_PUPDR register  *****************/\n#define GPIO_PUPDR_PUPD0_Pos             (0U)\n#define GPIO_PUPDR_PUPD0_Msk             (0x3UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000003 */\n#define GPIO_PUPDR_PUPD0                 GPIO_PUPDR_PUPD0_Msk\n#define GPIO_PUPDR_PUPD0_0               (0x1UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000001 */\n#define GPIO_PUPDR_PUPD0_1               (0x2UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000002 */\n#define GPIO_PUPDR_PUPD1_Pos             (2U)\n#define GPIO_PUPDR_PUPD1_Msk             (0x3UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x0000000C */\n#define GPIO_PUPDR_PUPD1                 GPIO_PUPDR_PUPD1_Msk\n#define GPIO_PUPDR_PUPD1_0               (0x1UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000004 */\n#define GPIO_PUPDR_PUPD1_1               (0x2UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000008 */\n#define GPIO_PUPDR_PUPD2_Pos             (4U)\n#define GPIO_PUPDR_PUPD2_Msk             (0x3UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000030 */\n#define GPIO_PUPDR_PUPD2                 GPIO_PUPDR_PUPD2_Msk\n#define GPIO_PUPDR_PUPD2_0               (0x1UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000010 */\n#define GPIO_PUPDR_PUPD2_1               (0x2UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000020 */\n#define GPIO_PUPDR_PUPD3_Pos             (6U)\n#define GPIO_PUPDR_PUPD3_Msk             (0x3UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x000000C0 */\n#define GPIO_PUPDR_PUPD3                 GPIO_PUPDR_PUPD3_Msk\n#define GPIO_PUPDR_PUPD3_0               (0x1UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000040 */\n#define GPIO_PUPDR_PUPD3_1               (0x2UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000080 */\n#define GPIO_PUPDR_PUPD4_Pos             (8U)\n#define GPIO_PUPDR_PUPD4_Msk             (0x3UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000300 */\n#define GPIO_PUPDR_PUPD4                 GPIO_PUPDR_PUPD4_Msk\n#define GPIO_PUPDR_PUPD4_0               (0x1UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000100 */\n#define GPIO_PUPDR_PUPD4_1               (0x2UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000200 */\n#define GPIO_PUPDR_PUPD5_Pos             (10U)\n#define GPIO_PUPDR_PUPD5_Msk             (0x3UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000C00 */\n#define GPIO_PUPDR_PUPD5                 GPIO_PUPDR_PUPD5_Msk\n#define GPIO_PUPDR_PUPD5_0               (0x1UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000400 */\n#define GPIO_PUPDR_PUPD5_1               (0x2UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000800 */\n#define GPIO_PUPDR_PUPD6_Pos             (12U)\n#define GPIO_PUPDR_PUPD6_Msk             (0x3UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00003000 */\n#define GPIO_PUPDR_PUPD6                 GPIO_PUPDR_PUPD6_Msk\n#define GPIO_PUPDR_PUPD6_0               (0x1UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00001000 */\n#define GPIO_PUPDR_PUPD6_1               (0x2UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00002000 */\n#define GPIO_PUPDR_PUPD7_Pos             (14U)\n#define GPIO_PUPDR_PUPD7_Msk             (0x3UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x0000C000 */\n#define GPIO_PUPDR_PUPD7                 GPIO_PUPDR_PUPD7_Msk\n#define GPIO_PUPDR_PUPD7_0               (0x1UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00004000 */\n#define GPIO_PUPDR_PUPD7_1               (0x2UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00008000 */\n#define GPIO_PUPDR_PUPD8_Pos             (16U)\n#define GPIO_PUPDR_PUPD8_Msk             (0x3UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00030000 */\n#define GPIO_PUPDR_PUPD8                 GPIO_PUPDR_PUPD8_Msk\n#define GPIO_PUPDR_PUPD8_0               (0x1UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00010000 */\n#define GPIO_PUPDR_PUPD8_1               (0x2UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00020000 */\n#define GPIO_PUPDR_PUPD9_Pos             (18U)\n#define GPIO_PUPDR_PUPD9_Msk             (0x3UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x000C0000 */\n#define GPIO_PUPDR_PUPD9                 GPIO_PUPDR_PUPD9_Msk\n#define GPIO_PUPDR_PUPD9_0               (0x1UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00040000 */\n#define GPIO_PUPDR_PUPD9_1               (0x2UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00080000 */\n#define GPIO_PUPDR_PUPD10_Pos            (20U)\n#define GPIO_PUPDR_PUPD10_Msk            (0x3UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00300000 */\n#define GPIO_PUPDR_PUPD10                GPIO_PUPDR_PUPD10_Msk\n#define GPIO_PUPDR_PUPD10_0              (0x1UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00100000 */\n#define GPIO_PUPDR_PUPD10_1              (0x2UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00200000 */\n#define GPIO_PUPDR_PUPD11_Pos            (22U)\n#define GPIO_PUPDR_PUPD11_Msk            (0x3UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00C00000 */\n#define GPIO_PUPDR_PUPD11                GPIO_PUPDR_PUPD11_Msk\n#define GPIO_PUPDR_PUPD11_0              (0x1UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00400000 */\n#define GPIO_PUPDR_PUPD11_1              (0x2UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00800000 */\n#define GPIO_PUPDR_PUPD12_Pos            (24U)\n#define GPIO_PUPDR_PUPD12_Msk            (0x3UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x03000000 */\n#define GPIO_PUPDR_PUPD12                GPIO_PUPDR_PUPD12_Msk\n#define GPIO_PUPDR_PUPD12_0              (0x1UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x01000000 */\n#define GPIO_PUPDR_PUPD12_1              (0x2UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x02000000 */\n#define GPIO_PUPDR_PUPD13_Pos            (26U)\n#define GPIO_PUPDR_PUPD13_Msk            (0x3UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x0C000000 */\n#define GPIO_PUPDR_PUPD13                GPIO_PUPDR_PUPD13_Msk\n#define GPIO_PUPDR_PUPD13_0              (0x1UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x04000000 */\n#define GPIO_PUPDR_PUPD13_1              (0x2UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x08000000 */\n#define GPIO_PUPDR_PUPD14_Pos            (28U)\n#define GPIO_PUPDR_PUPD14_Msk            (0x3UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x30000000 */\n#define GPIO_PUPDR_PUPD14                GPIO_PUPDR_PUPD14_Msk\n#define GPIO_PUPDR_PUPD14_0              (0x1UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x10000000 */\n#define GPIO_PUPDR_PUPD14_1              (0x2UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x20000000 */\n#define GPIO_PUPDR_PUPD15_Pos            (30U)\n#define GPIO_PUPDR_PUPD15_Msk            (0x3UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0xC0000000 */\n#define GPIO_PUPDR_PUPD15                GPIO_PUPDR_PUPD15_Msk\n#define GPIO_PUPDR_PUPD15_0              (0x1UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x40000000 */\n#define GPIO_PUPDR_PUPD15_1              (0x2UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPD0\n#define GPIO_PUPDR_PUPDR0_0              GPIO_PUPDR_PUPD0_0\n#define GPIO_PUPDR_PUPDR0_1              GPIO_PUPDR_PUPD0_1\n#define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPD1\n#define GPIO_PUPDR_PUPDR1_0              GPIO_PUPDR_PUPD1_0\n#define GPIO_PUPDR_PUPDR1_1              GPIO_PUPDR_PUPD1_1\n#define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPD2\n#define GPIO_PUPDR_PUPDR2_0              GPIO_PUPDR_PUPD2_0\n#define GPIO_PUPDR_PUPDR2_1              GPIO_PUPDR_PUPD2_1\n#define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPD3\n#define GPIO_PUPDR_PUPDR3_0              GPIO_PUPDR_PUPD3_0\n#define GPIO_PUPDR_PUPDR3_1              GPIO_PUPDR_PUPD3_1\n#define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPD4\n#define GPIO_PUPDR_PUPDR4_0              GPIO_PUPDR_PUPD4_0\n#define GPIO_PUPDR_PUPDR4_1              GPIO_PUPDR_PUPD4_1\n#define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPD5\n#define GPIO_PUPDR_PUPDR5_0              GPIO_PUPDR_PUPD5_0\n#define GPIO_PUPDR_PUPDR5_1              GPIO_PUPDR_PUPD5_1\n#define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPD6\n#define GPIO_PUPDR_PUPDR6_0              GPIO_PUPDR_PUPD6_0\n#define GPIO_PUPDR_PUPDR6_1              GPIO_PUPDR_PUPD6_1\n#define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPD7\n#define GPIO_PUPDR_PUPDR7_0              GPIO_PUPDR_PUPD7_0\n#define GPIO_PUPDR_PUPDR7_1              GPIO_PUPDR_PUPD7_1\n#define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPD8\n#define GPIO_PUPDR_PUPDR8_0              GPIO_PUPDR_PUPD8_0\n#define GPIO_PUPDR_PUPDR8_1              GPIO_PUPDR_PUPD8_1\n#define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPD9\n#define GPIO_PUPDR_PUPDR9_0              GPIO_PUPDR_PUPD9_0\n#define GPIO_PUPDR_PUPDR9_1              GPIO_PUPDR_PUPD9_1\n#define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPD10\n#define GPIO_PUPDR_PUPDR10_0             GPIO_PUPDR_PUPD10_0\n#define GPIO_PUPDR_PUPDR10_1             GPIO_PUPDR_PUPD10_1\n#define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPD11\n#define GPIO_PUPDR_PUPDR11_0             GPIO_PUPDR_PUPD11_0\n#define GPIO_PUPDR_PUPDR11_1             GPIO_PUPDR_PUPD11_1\n#define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPD12\n#define GPIO_PUPDR_PUPDR12_0             GPIO_PUPDR_PUPD12_0\n#define GPIO_PUPDR_PUPDR12_1             GPIO_PUPDR_PUPD12_1\n#define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPD13\n#define GPIO_PUPDR_PUPDR13_0             GPIO_PUPDR_PUPD13_0\n#define GPIO_PUPDR_PUPDR13_1             GPIO_PUPDR_PUPD13_1\n#define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPD14\n#define GPIO_PUPDR_PUPDR14_0             GPIO_PUPDR_PUPD14_0\n#define GPIO_PUPDR_PUPDR14_1             GPIO_PUPDR_PUPD14_1\n#define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPD15\n#define GPIO_PUPDR_PUPDR15_0             GPIO_PUPDR_PUPD15_0\n#define GPIO_PUPDR_PUPDR15_1             GPIO_PUPDR_PUPD15_1\n\n/******************  Bits definition for GPIO_IDR register  *******************/\n#define GPIO_IDR_ID0_Pos                 (0U)\n#define GPIO_IDR_ID0_Msk                 (0x1UL << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */\n#define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk\n#define GPIO_IDR_ID1_Pos                 (1U)\n#define GPIO_IDR_ID1_Msk                 (0x1UL << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */\n#define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk\n#define GPIO_IDR_ID2_Pos                 (2U)\n#define GPIO_IDR_ID2_Msk                 (0x1UL << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */\n#define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk\n#define GPIO_IDR_ID3_Pos                 (3U)\n#define GPIO_IDR_ID3_Msk                 (0x1UL << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */\n#define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk\n#define GPIO_IDR_ID4_Pos                 (4U)\n#define GPIO_IDR_ID4_Msk                 (0x1UL << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */\n#define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk\n#define GPIO_IDR_ID5_Pos                 (5U)\n#define GPIO_IDR_ID5_Msk                 (0x1UL << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */\n#define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk\n#define GPIO_IDR_ID6_Pos                 (6U)\n#define GPIO_IDR_ID6_Msk                 (0x1UL << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */\n#define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk\n#define GPIO_IDR_ID7_Pos                 (7U)\n#define GPIO_IDR_ID7_Msk                 (0x1UL << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */\n#define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk\n#define GPIO_IDR_ID8_Pos                 (8U)\n#define GPIO_IDR_ID8_Msk                 (0x1UL << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */\n#define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk\n#define GPIO_IDR_ID9_Pos                 (9U)\n#define GPIO_IDR_ID9_Msk                 (0x1UL << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */\n#define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk\n#define GPIO_IDR_ID10_Pos                (10U)\n#define GPIO_IDR_ID10_Msk                (0x1UL << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */\n#define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk\n#define GPIO_IDR_ID11_Pos                (11U)\n#define GPIO_IDR_ID11_Msk                (0x1UL << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */\n#define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk\n#define GPIO_IDR_ID12_Pos                (12U)\n#define GPIO_IDR_ID12_Msk                (0x1UL << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */\n#define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk\n#define GPIO_IDR_ID13_Pos                (13U)\n#define GPIO_IDR_ID13_Msk                (0x1UL << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */\n#define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk\n#define GPIO_IDR_ID14_Pos                (14U)\n#define GPIO_IDR_ID14_Msk                (0x1UL << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */\n#define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk\n#define GPIO_IDR_ID15_Pos                (15U)\n#define GPIO_IDR_ID15_Msk                (0x1UL << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */\n#define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk\n\n/* Legacy defines */\n#define GPIO_IDR_IDR_0                   GPIO_IDR_ID0\n#define GPIO_IDR_IDR_1                   GPIO_IDR_ID1\n#define GPIO_IDR_IDR_2                   GPIO_IDR_ID2\n#define GPIO_IDR_IDR_3                   GPIO_IDR_ID3\n#define GPIO_IDR_IDR_4                   GPIO_IDR_ID4\n#define GPIO_IDR_IDR_5                   GPIO_IDR_ID5\n#define GPIO_IDR_IDR_6                   GPIO_IDR_ID6\n#define GPIO_IDR_IDR_7                   GPIO_IDR_ID7\n#define GPIO_IDR_IDR_8                   GPIO_IDR_ID8\n#define GPIO_IDR_IDR_9                   GPIO_IDR_ID9\n#define GPIO_IDR_IDR_10                  GPIO_IDR_ID10\n#define GPIO_IDR_IDR_11                  GPIO_IDR_ID11\n#define GPIO_IDR_IDR_12                  GPIO_IDR_ID12\n#define GPIO_IDR_IDR_13                  GPIO_IDR_ID13\n#define GPIO_IDR_IDR_14                  GPIO_IDR_ID14\n#define GPIO_IDR_IDR_15                  GPIO_IDR_ID15\n\n/******************  Bits definition for GPIO_ODR register  *******************/\n#define GPIO_ODR_OD0_Pos                 (0U)\n#define GPIO_ODR_OD0_Msk                 (0x1UL << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */\n#define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk\n#define GPIO_ODR_OD1_Pos                 (1U)\n#define GPIO_ODR_OD1_Msk                 (0x1UL << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */\n#define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk\n#define GPIO_ODR_OD2_Pos                 (2U)\n#define GPIO_ODR_OD2_Msk                 (0x1UL << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */\n#define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk\n#define GPIO_ODR_OD3_Pos                 (3U)\n#define GPIO_ODR_OD3_Msk                 (0x1UL << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */\n#define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk\n#define GPIO_ODR_OD4_Pos                 (4U)\n#define GPIO_ODR_OD4_Msk                 (0x1UL << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */\n#define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk\n#define GPIO_ODR_OD5_Pos                 (5U)\n#define GPIO_ODR_OD5_Msk                 (0x1UL << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */\n#define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk\n#define GPIO_ODR_OD6_Pos                 (6U)\n#define GPIO_ODR_OD6_Msk                 (0x1UL << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */\n#define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk\n#define GPIO_ODR_OD7_Pos                 (7U)\n#define GPIO_ODR_OD7_Msk                 (0x1UL << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */\n#define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk\n#define GPIO_ODR_OD8_Pos                 (8U)\n#define GPIO_ODR_OD8_Msk                 (0x1UL << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */\n#define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk\n#define GPIO_ODR_OD9_Pos                 (9U)\n#define GPIO_ODR_OD9_Msk                 (0x1UL << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */\n#define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk\n#define GPIO_ODR_OD10_Pos                (10U)\n#define GPIO_ODR_OD10_Msk                (0x1UL << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */\n#define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk\n#define GPIO_ODR_OD11_Pos                (11U)\n#define GPIO_ODR_OD11_Msk                (0x1UL << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */\n#define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk\n#define GPIO_ODR_OD12_Pos                (12U)\n#define GPIO_ODR_OD12_Msk                (0x1UL << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */\n#define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk\n#define GPIO_ODR_OD13_Pos                (13U)\n#define GPIO_ODR_OD13_Msk                (0x1UL << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */\n#define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk\n#define GPIO_ODR_OD14_Pos                (14U)\n#define GPIO_ODR_OD14_Msk                (0x1UL << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */\n#define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk\n#define GPIO_ODR_OD15_Pos                (15U)\n#define GPIO_ODR_OD15_Msk                (0x1UL << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */\n#define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk\n/* Legacy defines */\n#define GPIO_ODR_ODR_0                   GPIO_ODR_OD0\n#define GPIO_ODR_ODR_1                   GPIO_ODR_OD1\n#define GPIO_ODR_ODR_2                   GPIO_ODR_OD2\n#define GPIO_ODR_ODR_3                   GPIO_ODR_OD3\n#define GPIO_ODR_ODR_4                   GPIO_ODR_OD4\n#define GPIO_ODR_ODR_5                   GPIO_ODR_OD5\n#define GPIO_ODR_ODR_6                   GPIO_ODR_OD6\n#define GPIO_ODR_ODR_7                   GPIO_ODR_OD7\n#define GPIO_ODR_ODR_8                   GPIO_ODR_OD8\n#define GPIO_ODR_ODR_9                   GPIO_ODR_OD9\n#define GPIO_ODR_ODR_10                  GPIO_ODR_OD10\n#define GPIO_ODR_ODR_11                  GPIO_ODR_OD11\n#define GPIO_ODR_ODR_12                  GPIO_ODR_OD12\n#define GPIO_ODR_ODR_13                  GPIO_ODR_OD13\n#define GPIO_ODR_ODR_14                  GPIO_ODR_OD14\n#define GPIO_ODR_ODR_15                  GPIO_ODR_OD15\n\n/******************  Bits definition for GPIO_BSRR register  ******************/\n#define GPIO_BSRR_BS0_Pos                (0U)\n#define GPIO_BSRR_BS0_Msk                (0x1UL << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */\n#define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk\n#define GPIO_BSRR_BS1_Pos                (1U)\n#define GPIO_BSRR_BS1_Msk                (0x1UL << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */\n#define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk\n#define GPIO_BSRR_BS2_Pos                (2U)\n#define GPIO_BSRR_BS2_Msk                (0x1UL << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */\n#define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk\n#define GPIO_BSRR_BS3_Pos                (3U)\n#define GPIO_BSRR_BS3_Msk                (0x1UL << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */\n#define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk\n#define GPIO_BSRR_BS4_Pos                (4U)\n#define GPIO_BSRR_BS4_Msk                (0x1UL << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */\n#define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk\n#define GPIO_BSRR_BS5_Pos                (5U)\n#define GPIO_BSRR_BS5_Msk                (0x1UL << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */\n#define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk\n#define GPIO_BSRR_BS6_Pos                (6U)\n#define GPIO_BSRR_BS6_Msk                (0x1UL << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */\n#define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk\n#define GPIO_BSRR_BS7_Pos                (7U)\n#define GPIO_BSRR_BS7_Msk                (0x1UL << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */\n#define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk\n#define GPIO_BSRR_BS8_Pos                (8U)\n#define GPIO_BSRR_BS8_Msk                (0x1UL << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */\n#define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk\n#define GPIO_BSRR_BS9_Pos                (9U)\n#define GPIO_BSRR_BS9_Msk                (0x1UL << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */\n#define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk\n#define GPIO_BSRR_BS10_Pos               (10U)\n#define GPIO_BSRR_BS10_Msk               (0x1UL << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */\n#define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk\n#define GPIO_BSRR_BS11_Pos               (11U)\n#define GPIO_BSRR_BS11_Msk               (0x1UL << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */\n#define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk\n#define GPIO_BSRR_BS12_Pos               (12U)\n#define GPIO_BSRR_BS12_Msk               (0x1UL << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */\n#define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk\n#define GPIO_BSRR_BS13_Pos               (13U)\n#define GPIO_BSRR_BS13_Msk               (0x1UL << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */\n#define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk\n#define GPIO_BSRR_BS14_Pos               (14U)\n#define GPIO_BSRR_BS14_Msk               (0x1UL << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */\n#define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk\n#define GPIO_BSRR_BS15_Pos               (15U)\n#define GPIO_BSRR_BS15_Msk               (0x1UL << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */\n#define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk\n#define GPIO_BSRR_BR0_Pos                (16U)\n#define GPIO_BSRR_BR0_Msk                (0x1UL << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */\n#define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk\n#define GPIO_BSRR_BR1_Pos                (17U)\n#define GPIO_BSRR_BR1_Msk                (0x1UL << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */\n#define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk\n#define GPIO_BSRR_BR2_Pos                (18U)\n#define GPIO_BSRR_BR2_Msk                (0x1UL << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */\n#define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk\n#define GPIO_BSRR_BR3_Pos                (19U)\n#define GPIO_BSRR_BR3_Msk                (0x1UL << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */\n#define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk\n#define GPIO_BSRR_BR4_Pos                (20U)\n#define GPIO_BSRR_BR4_Msk                (0x1UL << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */\n#define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk\n#define GPIO_BSRR_BR5_Pos                (21U)\n#define GPIO_BSRR_BR5_Msk                (0x1UL << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */\n#define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk\n#define GPIO_BSRR_BR6_Pos                (22U)\n#define GPIO_BSRR_BR6_Msk                (0x1UL << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */\n#define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk\n#define GPIO_BSRR_BR7_Pos                (23U)\n#define GPIO_BSRR_BR7_Msk                (0x1UL << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */\n#define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk\n#define GPIO_BSRR_BR8_Pos                (24U)\n#define GPIO_BSRR_BR8_Msk                (0x1UL << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */\n#define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk\n#define GPIO_BSRR_BR9_Pos                (25U)\n#define GPIO_BSRR_BR9_Msk                (0x1UL << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */\n#define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk\n#define GPIO_BSRR_BR10_Pos               (26U)\n#define GPIO_BSRR_BR10_Msk               (0x1UL << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */\n#define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk\n#define GPIO_BSRR_BR11_Pos               (27U)\n#define GPIO_BSRR_BR11_Msk               (0x1UL << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */\n#define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk\n#define GPIO_BSRR_BR12_Pos               (28U)\n#define GPIO_BSRR_BR12_Msk               (0x1UL << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */\n#define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk\n#define GPIO_BSRR_BR13_Pos               (29U)\n#define GPIO_BSRR_BR13_Msk               (0x1UL << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */\n#define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk\n#define GPIO_BSRR_BR14_Pos               (30U)\n#define GPIO_BSRR_BR14_Msk               (0x1UL << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */\n#define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk\n#define GPIO_BSRR_BR15_Pos               (31U)\n#define GPIO_BSRR_BR15_Msk               (0x1UL << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */\n#define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk\n\n/* Legacy defines */\n#define GPIO_BSRR_BS_0                   GPIO_BSRR_BS0\n#define GPIO_BSRR_BS_1                   GPIO_BSRR_BS1\n#define GPIO_BSRR_BS_2                   GPIO_BSRR_BS2\n#define GPIO_BSRR_BS_3                   GPIO_BSRR_BS3\n#define GPIO_BSRR_BS_4                   GPIO_BSRR_BS4\n#define GPIO_BSRR_BS_5                   GPIO_BSRR_BS5\n#define GPIO_BSRR_BS_6                   GPIO_BSRR_BS6\n#define GPIO_BSRR_BS_7                   GPIO_BSRR_BS7\n#define GPIO_BSRR_BS_8                   GPIO_BSRR_BS8\n#define GPIO_BSRR_BS_9                   GPIO_BSRR_BS9\n#define GPIO_BSRR_BS_10                  GPIO_BSRR_BS10\n#define GPIO_BSRR_BS_11                  GPIO_BSRR_BS11\n#define GPIO_BSRR_BS_12                  GPIO_BSRR_BS12\n#define GPIO_BSRR_BS_13                  GPIO_BSRR_BS13\n#define GPIO_BSRR_BS_14                  GPIO_BSRR_BS14\n#define GPIO_BSRR_BS_15                  GPIO_BSRR_BS15\n#define GPIO_BSRR_BR_0                   GPIO_BSRR_BR0\n#define GPIO_BSRR_BR_1                   GPIO_BSRR_BR1\n#define GPIO_BSRR_BR_2                   GPIO_BSRR_BR2\n#define GPIO_BSRR_BR_3                   GPIO_BSRR_BR3\n#define GPIO_BSRR_BR_4                   GPIO_BSRR_BR4\n#define GPIO_BSRR_BR_5                   GPIO_BSRR_BR5\n#define GPIO_BSRR_BR_6                   GPIO_BSRR_BR6\n#define GPIO_BSRR_BR_7                   GPIO_BSRR_BR7\n#define GPIO_BSRR_BR_8                   GPIO_BSRR_BR8\n#define GPIO_BSRR_BR_9                   GPIO_BSRR_BR9\n#define GPIO_BSRR_BR_10                  GPIO_BSRR_BR10\n#define GPIO_BSRR_BR_11                  GPIO_BSRR_BR11\n#define GPIO_BSRR_BR_12                  GPIO_BSRR_BR12\n#define GPIO_BSRR_BR_13                  GPIO_BSRR_BR13\n#define GPIO_BSRR_BR_14                  GPIO_BSRR_BR14\n#define GPIO_BSRR_BR_15                  GPIO_BSRR_BR15\n#define GPIO_BRR_BR0                     GPIO_BSRR_BR0\n#define GPIO_BRR_BR0_Pos                 GPIO_BSRR_BR0_Pos\n#define GPIO_BRR_BR0_Msk                 GPIO_BSRR_BR0_Msk\n#define GPIO_BRR_BR1                     GPIO_BSRR_BR1\n#define GPIO_BRR_BR1_Pos                 GPIO_BSRR_BR1_Pos\n#define GPIO_BRR_BR1_Msk                 GPIO_BSRR_BR1_Msk\n#define GPIO_BRR_BR2                     GPIO_BSRR_BR2\n#define GPIO_BRR_BR2_Pos                 GPIO_BSRR_BR2_Pos\n#define GPIO_BRR_BR2_Msk                 GPIO_BSRR_BR2_Msk\n#define GPIO_BRR_BR3                     GPIO_BSRR_BR3\n#define GPIO_BRR_BR3_Pos                 GPIO_BSRR_BR3_Pos\n#define GPIO_BRR_BR3_Msk                 GPIO_BSRR_BR3_Msk\n#define GPIO_BRR_BR4                     GPIO_BSRR_BR4\n#define GPIO_BRR_BR4_Pos                 GPIO_BSRR_BR4_Pos\n#define GPIO_BRR_BR4_Msk                 GPIO_BSRR_BR4_Msk\n#define GPIO_BRR_BR5                     GPIO_BSRR_BR5\n#define GPIO_BRR_BR5_Pos                 GPIO_BSRR_BR5_Pos\n#define GPIO_BRR_BR5_Msk                 GPIO_BSRR_BR5_Msk\n#define GPIO_BRR_BR6                     GPIO_BSRR_BR6\n#define GPIO_BRR_BR6_Pos                 GPIO_BSRR_BR6_Pos\n#define GPIO_BRR_BR6_Msk                 GPIO_BSRR_BR6_Msk\n#define GPIO_BRR_BR7                     GPIO_BSRR_BR7\n#define GPIO_BRR_BR7_Pos                 GPIO_BSRR_BR7_Pos\n#define GPIO_BRR_BR7_Msk                 GPIO_BSRR_BR7_Msk\n#define GPIO_BRR_BR8                     GPIO_BSRR_BR8\n#define GPIO_BRR_BR8_Pos                 GPIO_BSRR_BR8_Pos\n#define GPIO_BRR_BR8_Msk                 GPIO_BSRR_BR8_Msk\n#define GPIO_BRR_BR9                     GPIO_BSRR_BR9\n#define GPIO_BRR_BR9_Pos                 GPIO_BSRR_BR9_Pos\n#define GPIO_BRR_BR9_Msk                 GPIO_BSRR_BR9_Msk\n#define GPIO_BRR_BR10                    GPIO_BSRR_BR10\n#define GPIO_BRR_BR10_Pos                GPIO_BSRR_BR10_Pos\n#define GPIO_BRR_BR10_Msk                GPIO_BSRR_BR10_Msk\n#define GPIO_BRR_BR11                    GPIO_BSRR_BR11\n#define GPIO_BRR_BR11_Pos                GPIO_BSRR_BR11_Pos\n#define GPIO_BRR_BR11_Msk                GPIO_BSRR_BR11_Msk\n#define GPIO_BRR_BR12                    GPIO_BSRR_BR12\n#define GPIO_BRR_BR12_Pos                GPIO_BSRR_BR12_Pos\n#define GPIO_BRR_BR12_Msk                GPIO_BSRR_BR12_Msk\n#define GPIO_BRR_BR13                    GPIO_BSRR_BR13\n#define GPIO_BRR_BR13_Pos                GPIO_BSRR_BR13_Pos\n#define GPIO_BRR_BR13_Msk                GPIO_BSRR_BR13_Msk\n#define GPIO_BRR_BR14                    GPIO_BSRR_BR14\n#define GPIO_BRR_BR14_Pos                GPIO_BSRR_BR14_Pos\n#define GPIO_BRR_BR14_Msk                GPIO_BSRR_BR14_Msk\n#define GPIO_BRR_BR15                    GPIO_BSRR_BR15\n#define GPIO_BRR_BR15_Pos                GPIO_BSRR_BR15_Pos\n#define GPIO_BRR_BR15_Msk                GPIO_BSRR_BR15_Msk\n/****************** Bit definition for GPIO_LCKR register *********************/\n#define GPIO_LCKR_LCK0_Pos               (0U)\n#define GPIO_LCKR_LCK0_Msk               (0x1UL << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */\n#define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk\n#define GPIO_LCKR_LCK1_Pos               (1U)\n#define GPIO_LCKR_LCK1_Msk               (0x1UL << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */\n#define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk\n#define GPIO_LCKR_LCK2_Pos               (2U)\n#define GPIO_LCKR_LCK2_Msk               (0x1UL << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */\n#define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk\n#define GPIO_LCKR_LCK3_Pos               (3U)\n#define GPIO_LCKR_LCK3_Msk               (0x1UL << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */\n#define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk\n#define GPIO_LCKR_LCK4_Pos               (4U)\n#define GPIO_LCKR_LCK4_Msk               (0x1UL << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */\n#define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk\n#define GPIO_LCKR_LCK5_Pos               (5U)\n#define GPIO_LCKR_LCK5_Msk               (0x1UL << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */\n#define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk\n#define GPIO_LCKR_LCK6_Pos               (6U)\n#define GPIO_LCKR_LCK6_Msk               (0x1UL << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */\n#define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk\n#define GPIO_LCKR_LCK7_Pos               (7U)\n#define GPIO_LCKR_LCK7_Msk               (0x1UL << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */\n#define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk\n#define GPIO_LCKR_LCK8_Pos               (8U)\n#define GPIO_LCKR_LCK8_Msk               (0x1UL << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */\n#define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk\n#define GPIO_LCKR_LCK9_Pos               (9U)\n#define GPIO_LCKR_LCK9_Msk               (0x1UL << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */\n#define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk\n#define GPIO_LCKR_LCK10_Pos              (10U)\n#define GPIO_LCKR_LCK10_Msk              (0x1UL << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */\n#define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk\n#define GPIO_LCKR_LCK11_Pos              (11U)\n#define GPIO_LCKR_LCK11_Msk              (0x1UL << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */\n#define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk\n#define GPIO_LCKR_LCK12_Pos              (12U)\n#define GPIO_LCKR_LCK12_Msk              (0x1UL << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */\n#define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk\n#define GPIO_LCKR_LCK13_Pos              (13U)\n#define GPIO_LCKR_LCK13_Msk              (0x1UL << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */\n#define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk\n#define GPIO_LCKR_LCK14_Pos              (14U)\n#define GPIO_LCKR_LCK14_Msk              (0x1UL << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */\n#define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk\n#define GPIO_LCKR_LCK15_Pos              (15U)\n#define GPIO_LCKR_LCK15_Msk              (0x1UL << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */\n#define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk\n#define GPIO_LCKR_LCKK_Pos               (16U)\n#define GPIO_LCKR_LCKK_Msk               (0x1UL << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */\n#define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk\n/****************** Bit definition for GPIO_AFRL register *********************/\n#define GPIO_AFRL_AFSEL0_Pos             (0U)\n#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk\n#define GPIO_AFRL_AFSEL0_0               (0x1UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRL_AFSEL0_1               (0x2UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRL_AFSEL0_2               (0x4UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRL_AFSEL0_3               (0x8UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRL_AFSEL1_Pos             (4U)\n#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk\n#define GPIO_AFRL_AFSEL1_0               (0x1UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRL_AFSEL1_1               (0x2UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRL_AFSEL1_2               (0x4UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRL_AFSEL1_3               (0x8UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRL_AFSEL2_Pos             (8U)\n#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */\n#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk\n#define GPIO_AFRL_AFSEL2_0               (0x1UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */\n#define GPIO_AFRL_AFSEL2_1               (0x2UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */\n#define GPIO_AFRL_AFSEL2_2               (0x4UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */\n#define GPIO_AFRL_AFSEL2_3               (0x8UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */\n#define GPIO_AFRL_AFSEL3_Pos             (12U)\n#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */\n#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk\n#define GPIO_AFRL_AFSEL3_0               (0x1UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */\n#define GPIO_AFRL_AFSEL3_1               (0x2UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */\n#define GPIO_AFRL_AFSEL3_2               (0x4UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */\n#define GPIO_AFRL_AFSEL3_3               (0x8UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */\n#define GPIO_AFRL_AFSEL4_Pos             (16U)\n#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */\n#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk\n#define GPIO_AFRL_AFSEL4_0               (0x1UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */\n#define GPIO_AFRL_AFSEL4_1               (0x2UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */\n#define GPIO_AFRL_AFSEL4_2               (0x4UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */\n#define GPIO_AFRL_AFSEL4_3               (0x8UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */\n#define GPIO_AFRL_AFSEL5_Pos             (20U)\n#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */\n#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk\n#define GPIO_AFRL_AFSEL5_0               (0x1UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */\n#define GPIO_AFRL_AFSEL5_1               (0x2UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */\n#define GPIO_AFRL_AFSEL5_2               (0x4UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */\n#define GPIO_AFRL_AFSEL5_3               (0x8UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */\n#define GPIO_AFRL_AFSEL6_Pos             (24U)\n#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */\n#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk\n#define GPIO_AFRL_AFSEL6_0               (0x1UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */\n#define GPIO_AFRL_AFSEL6_1               (0x2UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */\n#define GPIO_AFRL_AFSEL6_2               (0x4UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */\n#define GPIO_AFRL_AFSEL6_3               (0x8UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */\n#define GPIO_AFRL_AFSEL7_Pos             (28U)\n#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */\n#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk\n#define GPIO_AFRL_AFSEL7_0               (0x1UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */\n#define GPIO_AFRL_AFSEL7_1               (0x2UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */\n#define GPIO_AFRL_AFSEL7_2               (0x4UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */\n#define GPIO_AFRL_AFSEL7_3               (0x8UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFSEL0\n#define GPIO_AFRL_AFRL0_0                GPIO_AFRL_AFSEL0_0\n#define GPIO_AFRL_AFRL0_1                GPIO_AFRL_AFSEL0_1\n#define GPIO_AFRL_AFRL0_2                GPIO_AFRL_AFSEL0_2\n#define GPIO_AFRL_AFRL0_3                GPIO_AFRL_AFSEL0_3\n#define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFSEL1\n#define GPIO_AFRL_AFRL1_0                GPIO_AFRL_AFSEL1_0\n#define GPIO_AFRL_AFRL1_1                GPIO_AFRL_AFSEL1_1\n#define GPIO_AFRL_AFRL1_2                GPIO_AFRL_AFSEL1_2\n#define GPIO_AFRL_AFRL1_3                GPIO_AFRL_AFSEL1_3\n#define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFSEL2\n#define GPIO_AFRL_AFRL2_0                GPIO_AFRL_AFSEL2_0\n#define GPIO_AFRL_AFRL2_1                GPIO_AFRL_AFSEL2_1\n#define GPIO_AFRL_AFRL2_2                GPIO_AFRL_AFSEL2_2\n#define GPIO_AFRL_AFRL2_3                GPIO_AFRL_AFSEL2_3\n#define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFSEL3\n#define GPIO_AFRL_AFRL3_0                GPIO_AFRL_AFSEL3_0\n#define GPIO_AFRL_AFRL3_1                GPIO_AFRL_AFSEL3_1\n#define GPIO_AFRL_AFRL3_2                GPIO_AFRL_AFSEL3_2\n#define GPIO_AFRL_AFRL3_3                GPIO_AFRL_AFSEL3_3\n#define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFSEL4\n#define GPIO_AFRL_AFRL4_0                GPIO_AFRL_AFSEL4_0\n#define GPIO_AFRL_AFRL4_1                GPIO_AFRL_AFSEL4_1\n#define GPIO_AFRL_AFRL4_2                GPIO_AFRL_AFSEL4_2\n#define GPIO_AFRL_AFRL4_3                GPIO_AFRL_AFSEL4_3\n#define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFSEL5\n#define GPIO_AFRL_AFRL5_0                GPIO_AFRL_AFSEL5_0\n#define GPIO_AFRL_AFRL5_1                GPIO_AFRL_AFSEL5_1\n#define GPIO_AFRL_AFRL5_2                GPIO_AFRL_AFSEL5_2\n#define GPIO_AFRL_AFRL5_3                GPIO_AFRL_AFSEL5_3\n#define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFSEL6\n#define GPIO_AFRL_AFRL6_0                GPIO_AFRL_AFSEL6_0\n#define GPIO_AFRL_AFRL6_1                GPIO_AFRL_AFSEL6_1\n#define GPIO_AFRL_AFRL6_2                GPIO_AFRL_AFSEL6_2\n#define GPIO_AFRL_AFRL6_3                GPIO_AFRL_AFSEL6_3\n#define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFSEL7\n#define GPIO_AFRL_AFRL7_0                GPIO_AFRL_AFSEL7_0\n#define GPIO_AFRL_AFRL7_1                GPIO_AFRL_AFSEL7_1\n#define GPIO_AFRL_AFRL7_2                GPIO_AFRL_AFSEL7_2\n#define GPIO_AFRL_AFRL7_3                GPIO_AFRL_AFSEL7_3\n\n/****************** Bit definition for GPIO_AFRH register *********************/\n#define GPIO_AFRH_AFSEL8_Pos             (0U)\n#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk\n#define GPIO_AFRH_AFSEL8_0               (0x1UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRH_AFSEL8_1               (0x2UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRH_AFSEL8_2               (0x4UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRH_AFSEL8_3               (0x8UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRH_AFSEL9_Pos             (4U)\n#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk\n#define GPIO_AFRH_AFSEL9_0               (0x1UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRH_AFSEL9_1               (0x2UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRH_AFSEL9_2               (0x4UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRH_AFSEL9_3               (0x8UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRH_AFSEL10_Pos            (8U)\n#define GPIO_AFRH_AFSEL10_Msk            (0xFUL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */\n#define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk\n#define GPIO_AFRH_AFSEL10_0              (0x1UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */\n#define GPIO_AFRH_AFSEL10_1              (0x2UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */\n#define GPIO_AFRH_AFSEL10_2              (0x4UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */\n#define GPIO_AFRH_AFSEL10_3              (0x8UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */\n#define GPIO_AFRH_AFSEL11_Pos            (12U)\n#define GPIO_AFRH_AFSEL11_Msk            (0xFUL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */\n#define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk\n#define GPIO_AFRH_AFSEL11_0              (0x1UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */\n#define GPIO_AFRH_AFSEL11_1              (0x2UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */\n#define GPIO_AFRH_AFSEL11_2              (0x4UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */\n#define GPIO_AFRH_AFSEL11_3              (0x8UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */\n#define GPIO_AFRH_AFSEL12_Pos            (16U)\n#define GPIO_AFRH_AFSEL12_Msk            (0xFUL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */\n#define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk\n#define GPIO_AFRH_AFSEL12_0              (0x1UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */\n#define GPIO_AFRH_AFSEL12_1              (0x2UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */\n#define GPIO_AFRH_AFSEL12_2              (0x4UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */\n#define GPIO_AFRH_AFSEL12_3              (0x8UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */\n#define GPIO_AFRH_AFSEL13_Pos            (20U)\n#define GPIO_AFRH_AFSEL13_Msk            (0xFUL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */\n#define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk\n#define GPIO_AFRH_AFSEL13_0              (0x1UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */\n#define GPIO_AFRH_AFSEL13_1              (0x2UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */\n#define GPIO_AFRH_AFSEL13_2              (0x4UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */\n#define GPIO_AFRH_AFSEL13_3              (0x8UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */\n#define GPIO_AFRH_AFSEL14_Pos            (24U)\n#define GPIO_AFRH_AFSEL14_Msk            (0xFUL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */\n#define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk\n#define GPIO_AFRH_AFSEL14_0              (0x1UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */\n#define GPIO_AFRH_AFSEL14_1              (0x2UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */\n#define GPIO_AFRH_AFSEL14_2              (0x4UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */\n#define GPIO_AFRH_AFSEL14_3              (0x8UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */\n#define GPIO_AFRH_AFSEL15_Pos            (28U)\n#define GPIO_AFRH_AFSEL15_Msk            (0xFUL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */\n#define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk\n#define GPIO_AFRH_AFSEL15_0              (0x1UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */\n#define GPIO_AFRH_AFSEL15_1              (0x2UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */\n#define GPIO_AFRH_AFSEL15_2              (0x4UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */\n#define GPIO_AFRH_AFSEL15_3              (0x8UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFSEL8\n#define GPIO_AFRH_AFRH0_0                GPIO_AFRH_AFSEL8_0\n#define GPIO_AFRH_AFRH0_1                GPIO_AFRH_AFSEL8_1\n#define GPIO_AFRH_AFRH0_2                GPIO_AFRH_AFSEL8_2\n#define GPIO_AFRH_AFRH0_3                GPIO_AFRH_AFSEL8_3\n#define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFSEL9\n#define GPIO_AFRH_AFRH1_0                GPIO_AFRH_AFSEL9_0\n#define GPIO_AFRH_AFRH1_1                GPIO_AFRH_AFSEL9_1\n#define GPIO_AFRH_AFRH1_2                GPIO_AFRH_AFSEL9_2\n#define GPIO_AFRH_AFRH1_3                GPIO_AFRH_AFSEL9_3\n#define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFSEL10\n#define GPIO_AFRH_AFRH2_0                GPIO_AFRH_AFSEL10_0\n#define GPIO_AFRH_AFRH2_1                GPIO_AFRH_AFSEL10_1\n#define GPIO_AFRH_AFRH2_2                GPIO_AFRH_AFSEL10_2\n#define GPIO_AFRH_AFRH2_3                GPIO_AFRH_AFSEL10_3\n#define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFSEL11\n#define GPIO_AFRH_AFRH3_0                GPIO_AFRH_AFSEL11_0\n#define GPIO_AFRH_AFRH3_1                GPIO_AFRH_AFSEL11_1\n#define GPIO_AFRH_AFRH3_2                GPIO_AFRH_AFSEL11_2\n#define GPIO_AFRH_AFRH3_3                GPIO_AFRH_AFSEL11_3\n#define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFSEL12\n#define GPIO_AFRH_AFRH4_0                GPIO_AFRH_AFSEL12_0\n#define GPIO_AFRH_AFRH4_1                GPIO_AFRH_AFSEL12_1\n#define GPIO_AFRH_AFRH4_2                GPIO_AFRH_AFSEL12_2\n#define GPIO_AFRH_AFRH4_3                GPIO_AFRH_AFSEL12_3\n#define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFSEL13\n#define GPIO_AFRH_AFRH5_0                GPIO_AFRH_AFSEL13_0\n#define GPIO_AFRH_AFRH5_1                GPIO_AFRH_AFSEL13_1\n#define GPIO_AFRH_AFRH5_2                GPIO_AFRH_AFSEL13_2\n#define GPIO_AFRH_AFRH5_3                GPIO_AFRH_AFSEL13_3\n#define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFSEL14\n#define GPIO_AFRH_AFRH6_0                GPIO_AFRH_AFSEL14_0\n#define GPIO_AFRH_AFRH6_1                GPIO_AFRH_AFSEL14_1\n#define GPIO_AFRH_AFRH6_2                GPIO_AFRH_AFSEL14_2\n#define GPIO_AFRH_AFRH6_3                GPIO_AFRH_AFSEL14_3\n#define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFSEL15\n#define GPIO_AFRH_AFRH7_0                GPIO_AFRH_AFSEL15_0\n#define GPIO_AFRH_AFRH7_1                GPIO_AFRH_AFSEL15_1\n#define GPIO_AFRH_AFRH7_2                GPIO_AFRH_AFSEL15_2\n#define GPIO_AFRH_AFRH7_3                GPIO_AFRH_AFSEL15_3\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Inter-integrated Circuit Interface                    */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for I2C_CR1 register  ********************/\n#define I2C_CR1_PE_Pos            (0U)\n#define I2C_CR1_PE_Msk            (0x1UL << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */\n#define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */\n#define I2C_CR1_SMBUS_Pos         (1U)\n#define I2C_CR1_SMBUS_Msk         (0x1UL << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */\n#define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */\n#define I2C_CR1_SMBTYPE_Pos       (3U)\n#define I2C_CR1_SMBTYPE_Msk       (0x1UL << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */\n#define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */\n#define I2C_CR1_ENARP_Pos         (4U)\n#define I2C_CR1_ENARP_Msk         (0x1UL << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */\n#define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */\n#define I2C_CR1_ENPEC_Pos         (5U)\n#define I2C_CR1_ENPEC_Msk         (0x1UL << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */\n#define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */\n#define I2C_CR1_ENGC_Pos          (6U)\n#define I2C_CR1_ENGC_Msk          (0x1UL << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */\n#define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */\n#define I2C_CR1_NOSTRETCH_Pos     (7U)\n#define I2C_CR1_NOSTRETCH_Msk     (0x1UL << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */\n#define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */\n#define I2C_CR1_START_Pos         (8U)\n#define I2C_CR1_START_Msk         (0x1UL << I2C_CR1_START_Pos)                  /*!< 0x00000100 */\n#define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */\n#define I2C_CR1_STOP_Pos          (9U)\n#define I2C_CR1_STOP_Msk          (0x1UL << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */\n#define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */\n#define I2C_CR1_ACK_Pos           (10U)\n#define I2C_CR1_ACK_Msk           (0x1UL << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */\n#define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */\n#define I2C_CR1_POS_Pos           (11U)\n#define I2C_CR1_POS_Msk           (0x1UL << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */\n#define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */\n#define I2C_CR1_PEC_Pos           (12U)\n#define I2C_CR1_PEC_Msk           (0x1UL << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */\n#define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */\n#define I2C_CR1_ALERT_Pos         (13U)\n#define I2C_CR1_ALERT_Msk         (0x1UL << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */\n#define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */\n#define I2C_CR1_SWRST_Pos         (15U)\n#define I2C_CR1_SWRST_Msk         (0x1UL << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */\n#define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */\n\n/*******************  Bit definition for I2C_CR2 register  ********************/\n#define I2C_CR2_FREQ_Pos          (0U)\n#define I2C_CR2_FREQ_Msk          (0x3FUL << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */\n#define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */\n#define I2C_CR2_FREQ_0            (0x01UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */\n#define I2C_CR2_FREQ_1            (0x02UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */\n#define I2C_CR2_FREQ_2            (0x04UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */\n#define I2C_CR2_FREQ_3            (0x08UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */\n#define I2C_CR2_FREQ_4            (0x10UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */\n#define I2C_CR2_FREQ_5            (0x20UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */\n\n#define I2C_CR2_ITERREN_Pos       (8U)\n#define I2C_CR2_ITERREN_Msk       (0x1UL << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */\n#define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */\n#define I2C_CR2_ITEVTEN_Pos       (9U)\n#define I2C_CR2_ITEVTEN_Msk       (0x1UL << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */\n#define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */\n#define I2C_CR2_ITBUFEN_Pos       (10U)\n#define I2C_CR2_ITBUFEN_Msk       (0x1UL << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */\n#define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */\n#define I2C_CR2_DMAEN_Pos         (11U)\n#define I2C_CR2_DMAEN_Msk         (0x1UL << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */\n#define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */\n#define I2C_CR2_LAST_Pos          (12U)\n#define I2C_CR2_LAST_Msk          (0x1UL << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */\n#define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */\n\n/*******************  Bit definition for I2C_OAR1 register  *******************/\n#define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */\n#define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */\n\n#define I2C_OAR1_ADD0_Pos         (0U)\n#define I2C_OAR1_ADD0_Msk         (0x1UL << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */\n#define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */\n#define I2C_OAR1_ADD1_Pos         (1U)\n#define I2C_OAR1_ADD1_Msk         (0x1UL << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */\n#define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */\n#define I2C_OAR1_ADD2_Pos         (2U)\n#define I2C_OAR1_ADD2_Msk         (0x1UL << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */\n#define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */\n#define I2C_OAR1_ADD3_Pos         (3U)\n#define I2C_OAR1_ADD3_Msk         (0x1UL << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */\n#define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */\n#define I2C_OAR1_ADD4_Pos         (4U)\n#define I2C_OAR1_ADD4_Msk         (0x1UL << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */\n#define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */\n#define I2C_OAR1_ADD5_Pos         (5U)\n#define I2C_OAR1_ADD5_Msk         (0x1UL << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */\n#define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */\n#define I2C_OAR1_ADD6_Pos         (6U)\n#define I2C_OAR1_ADD6_Msk         (0x1UL << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */\n#define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */\n#define I2C_OAR1_ADD7_Pos         (7U)\n#define I2C_OAR1_ADD7_Msk         (0x1UL << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */\n#define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */\n#define I2C_OAR1_ADD8_Pos         (8U)\n#define I2C_OAR1_ADD8_Msk         (0x1UL << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */\n#define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */\n#define I2C_OAR1_ADD9_Pos         (9U)\n#define I2C_OAR1_ADD9_Msk         (0x1UL << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */\n#define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */\n\n#define I2C_OAR1_ADDMODE_Pos      (15U)\n#define I2C_OAR1_ADDMODE_Msk      (0x1UL << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */\n#define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */\n\n/*******************  Bit definition for I2C_OAR2 register  *******************/\n#define I2C_OAR2_ENDUAL_Pos       (0U)\n#define I2C_OAR2_ENDUAL_Msk       (0x1UL << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */\n#define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */\n#define I2C_OAR2_ADD2_Pos         (1U)\n#define I2C_OAR2_ADD2_Msk         (0x7FUL << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */\n#define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */\n\n/********************  Bit definition for I2C_DR register  ********************/\n#define I2C_DR_DR_Pos             (0U)\n#define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */\n#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */\n\n/*******************  Bit definition for I2C_SR1 register  ********************/\n#define I2C_SR1_SB_Pos            (0U)\n#define I2C_SR1_SB_Msk            (0x1UL << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */\n#define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */\n#define I2C_SR1_ADDR_Pos          (1U)\n#define I2C_SR1_ADDR_Msk          (0x1UL << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */\n#define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */\n#define I2C_SR1_BTF_Pos           (2U)\n#define I2C_SR1_BTF_Msk           (0x1UL << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */\n#define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */\n#define I2C_SR1_ADD10_Pos         (3U)\n#define I2C_SR1_ADD10_Msk         (0x1UL << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */\n#define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */\n#define I2C_SR1_STOPF_Pos         (4U)\n#define I2C_SR1_STOPF_Msk         (0x1UL << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */\n#define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */\n#define I2C_SR1_RXNE_Pos          (6U)\n#define I2C_SR1_RXNE_Msk          (0x1UL << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */\n#define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */\n#define I2C_SR1_TXE_Pos           (7U)\n#define I2C_SR1_TXE_Msk           (0x1UL << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */\n#define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */\n#define I2C_SR1_BERR_Pos          (8U)\n#define I2C_SR1_BERR_Msk          (0x1UL << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */\n#define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */\n#define I2C_SR1_ARLO_Pos          (9U)\n#define I2C_SR1_ARLO_Msk          (0x1UL << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */\n#define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */\n#define I2C_SR1_AF_Pos            (10U)\n#define I2C_SR1_AF_Msk            (0x1UL << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */\n#define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */\n#define I2C_SR1_OVR_Pos           (11U)\n#define I2C_SR1_OVR_Msk           (0x1UL << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */\n#define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */\n#define I2C_SR1_PECERR_Pos        (12U)\n#define I2C_SR1_PECERR_Msk        (0x1UL << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */\n#define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */\n#define I2C_SR1_TIMEOUT_Pos       (14U)\n#define I2C_SR1_TIMEOUT_Msk       (0x1UL << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */\n#define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */\n#define I2C_SR1_SMBALERT_Pos      (15U)\n#define I2C_SR1_SMBALERT_Msk      (0x1UL << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */\n#define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */\n\n/*******************  Bit definition for I2C_SR2 register  ********************/\n#define I2C_SR2_MSL_Pos           (0U)\n#define I2C_SR2_MSL_Msk           (0x1UL << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */\n#define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */\n#define I2C_SR2_BUSY_Pos          (1U)\n#define I2C_SR2_BUSY_Msk          (0x1UL << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */\n#define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */\n#define I2C_SR2_TRA_Pos           (2U)\n#define I2C_SR2_TRA_Msk           (0x1UL << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */\n#define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */\n#define I2C_SR2_GENCALL_Pos       (4U)\n#define I2C_SR2_GENCALL_Msk       (0x1UL << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */\n#define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */\n#define I2C_SR2_SMBDEFAULT_Pos    (5U)\n#define I2C_SR2_SMBDEFAULT_Msk    (0x1UL << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */\n#define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */\n#define I2C_SR2_SMBHOST_Pos       (6U)\n#define I2C_SR2_SMBHOST_Msk       (0x1UL << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */\n#define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */\n#define I2C_SR2_DUALF_Pos         (7U)\n#define I2C_SR2_DUALF_Msk         (0x1UL << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */\n#define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */\n#define I2C_SR2_PEC_Pos           (8U)\n#define I2C_SR2_PEC_Msk           (0xFFUL << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */\n#define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */\n\n/*******************  Bit definition for I2C_CCR register  ********************/\n#define I2C_CCR_CCR_Pos           (0U)\n#define I2C_CCR_CCR_Msk           (0xFFFUL << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */\n#define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */\n#define I2C_CCR_DUTY_Pos          (14U)\n#define I2C_CCR_DUTY_Msk          (0x1UL << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */\n#define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */\n#define I2C_CCR_FS_Pos            (15U)\n#define I2C_CCR_FS_Msk            (0x1UL << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */\n#define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */\n\n/******************  Bit definition for I2C_TRISE register  *******************/\n#define I2C_TRISE_TRISE_Pos       (0U)\n#define I2C_TRISE_TRISE_Msk       (0x3FUL << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */\n#define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Independent WATCHDOG                             */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define IWDG_KR_KEY_Pos     (0U)\n#define IWDG_KR_KEY_Msk     (0xFFFFUL << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */\n#define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */\n\n/*******************  Bit definition for IWDG_PR register  ********************/\n#define IWDG_PR_PR_Pos      (0U)\n#define IWDG_PR_PR_Msk      (0x7UL << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */\n#define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */\n#define IWDG_PR_PR_0        (0x1UL << IWDG_PR_PR_Pos)                           /*!< 0x01 */\n#define IWDG_PR_PR_1        (0x2UL << IWDG_PR_PR_Pos)                           /*!< 0x02 */\n#define IWDG_PR_PR_2        (0x4UL << IWDG_PR_PR_Pos)                           /*!< 0x04 */\n\n/*******************  Bit definition for IWDG_RLR register  *******************/\n#define IWDG_RLR_RL_Pos     (0U)\n#define IWDG_RLR_RL_Msk     (0xFFFUL << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */\n#define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */\n\n/*******************  Bit definition for IWDG_SR register  ********************/\n#define IWDG_SR_PVU_Pos     (0U)\n#define IWDG_SR_PVU_Msk     (0x1UL << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */\n#define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */\n#define IWDG_SR_RVU_Pos     (1U)\n#define IWDG_SR_RVU_Msk     (0x1UL << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */\n#define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                             Power Control                                  */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for PWR_CR register  ********************/\n#define PWR_CR_LPDS_Pos        (0U)\n#define PWR_CR_LPDS_Msk        (0x1UL << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */\n#define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */\n#define PWR_CR_PDDS_Pos        (1U)\n#define PWR_CR_PDDS_Msk        (0x1UL << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */\n#define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */\n#define PWR_CR_CWUF_Pos        (2U)\n#define PWR_CR_CWUF_Msk        (0x1UL << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */\n#define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */\n#define PWR_CR_CSBF_Pos        (3U)\n#define PWR_CR_CSBF_Msk        (0x1UL << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */\n#define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */\n#define PWR_CR_PVDE_Pos        (4U)\n#define PWR_CR_PVDE_Msk        (0x1UL << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */\n#define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */\n\n#define PWR_CR_PLS_Pos         (5U)\n#define PWR_CR_PLS_Msk         (0x7UL << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */\n#define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */\n#define PWR_CR_PLS_0           (0x1UL << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */\n#define PWR_CR_PLS_1           (0x2UL << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */\n#define PWR_CR_PLS_2           (0x4UL << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */\n\n/*!< PVD level configuration */\n#define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */\n#define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */\n#define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */\n#define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */\n#define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */\n#define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */\n#define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */\n#define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */\n#define PWR_CR_DBP_Pos         (8U)\n#define PWR_CR_DBP_Msk         (0x1UL << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */\n#define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */\n#define PWR_CR_FPDS_Pos        (9U)\n#define PWR_CR_FPDS_Msk        (0x1UL << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */\n#define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */\n#define PWR_CR_VOS_Pos         (14U)\n#define PWR_CR_VOS_Msk         (0x1UL << PWR_CR_VOS_Pos)                        /*!< 0x00004000 */\n#define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS bit (Regulator voltage scaling output selection) */\n\n/* Legacy define */\n#define  PWR_CR_PMODE                        PWR_CR_VOS\n\n/*******************  Bit definition for PWR_CSR register  ********************/\n#define PWR_CSR_WUF_Pos        (0U)\n#define PWR_CSR_WUF_Msk        (0x1UL << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */\n#define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */\n#define PWR_CSR_SBF_Pos        (1U)\n#define PWR_CSR_SBF_Msk        (0x1UL << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */\n#define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */\n#define PWR_CSR_PVDO_Pos       (2U)\n#define PWR_CSR_PVDO_Msk       (0x1UL << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */\n#define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */\n#define PWR_CSR_BRR_Pos        (3U)\n#define PWR_CSR_BRR_Msk        (0x1UL << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */\n#define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */\n#define PWR_CSR_EWUP_Pos       (8U)\n#define PWR_CSR_EWUP_Msk       (0x1UL << PWR_CSR_EWUP_Pos)                      /*!< 0x00000100 */\n#define PWR_CSR_EWUP           PWR_CSR_EWUP_Msk                                /*!< Enable WKUP pin                                  */\n#define PWR_CSR_BRE_Pos        (9U)\n#define PWR_CSR_BRE_Msk        (0x1UL << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */\n#define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */\n#define PWR_CSR_VOSRDY_Pos     (14U)\n#define PWR_CSR_VOSRDY_Msk     (0x1UL << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */\n#define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */\n\n/* Legacy define */\n#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Reset and Clock Control                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for RCC_CR register  ********************/\n#define RCC_CR_HSION_Pos                   (0U)\n#define RCC_CR_HSION_Msk                   (0x1UL << RCC_CR_HSION_Pos)          /*!< 0x00000001 */\n#define RCC_CR_HSION                       RCC_CR_HSION_Msk\n#define RCC_CR_HSIRDY_Pos                  (1U)\n#define RCC_CR_HSIRDY_Msk                  (0x1UL << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */\n#define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk\n\n#define RCC_CR_HSITRIM_Pos                 (3U)\n#define RCC_CR_HSITRIM_Msk                 (0x1FUL << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */\n#define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk\n#define RCC_CR_HSITRIM_0                   (0x01UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */\n#define RCC_CR_HSITRIM_1                   (0x02UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */\n#define RCC_CR_HSITRIM_2                   (0x04UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */\n#define RCC_CR_HSITRIM_3                   (0x08UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */\n#define RCC_CR_HSITRIM_4                   (0x10UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */\n\n#define RCC_CR_HSICAL_Pos                  (8U)\n#define RCC_CR_HSICAL_Msk                  (0xFFUL << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */\n#define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk\n#define RCC_CR_HSICAL_0                    (0x01UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */\n#define RCC_CR_HSICAL_1                    (0x02UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */\n#define RCC_CR_HSICAL_2                    (0x04UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */\n#define RCC_CR_HSICAL_3                    (0x08UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */\n#define RCC_CR_HSICAL_4                    (0x10UL << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */\n#define RCC_CR_HSICAL_5                    (0x20UL << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */\n#define RCC_CR_HSICAL_6                    (0x40UL << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */\n#define RCC_CR_HSICAL_7                    (0x80UL << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */\n\n#define RCC_CR_HSEON_Pos                   (16U)\n#define RCC_CR_HSEON_Msk                   (0x1UL << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */\n#define RCC_CR_HSEON                       RCC_CR_HSEON_Msk\n#define RCC_CR_HSERDY_Pos                  (17U)\n#define RCC_CR_HSERDY_Msk                  (0x1UL << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */\n#define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk\n#define RCC_CR_HSEBYP_Pos                  (18U)\n#define RCC_CR_HSEBYP_Msk                  (0x1UL << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */\n#define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk\n#define RCC_CR_CSSON_Pos                   (19U)\n#define RCC_CR_CSSON_Msk                   (0x1UL << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */\n#define RCC_CR_CSSON                       RCC_CR_CSSON_Msk\n#define RCC_CR_PLLON_Pos                   (24U)\n#define RCC_CR_PLLON_Msk                   (0x1UL << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */\n#define RCC_CR_PLLON                       RCC_CR_PLLON_Msk\n#define RCC_CR_PLLRDY_Pos                  (25U)\n#define RCC_CR_PLLRDY_Msk                  (0x1UL << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */\n#define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_PLLI2S_SUPPORT                                                     /*!< Support PLLI2S oscillator */\n\n#define RCC_CR_PLLI2SON_Pos                (26U)\n#define RCC_CR_PLLI2SON_Msk                (0x1UL << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */\n#define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk\n#define RCC_CR_PLLI2SRDY_Pos               (27U)\n#define RCC_CR_PLLI2SRDY_Msk               (0x1UL << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */\n#define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk\n\n/********************  Bit definition for RCC_PLLCFGR register  ***************/\n#define RCC_PLLCFGR_PLLM_Pos               (0U)\n#define RCC_PLLCFGR_PLLM_Msk               (0x3FUL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */\n#define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk\n#define RCC_PLLCFGR_PLLM_0                 (0x01UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */\n#define RCC_PLLCFGR_PLLM_1                 (0x02UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */\n#define RCC_PLLCFGR_PLLM_2                 (0x04UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */\n#define RCC_PLLCFGR_PLLM_3                 (0x08UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */\n#define RCC_PLLCFGR_PLLM_4                 (0x10UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */\n#define RCC_PLLCFGR_PLLM_5                 (0x20UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */\n\n#define RCC_PLLCFGR_PLLN_Pos               (6U)\n#define RCC_PLLCFGR_PLLN_Msk               (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */\n#define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk\n#define RCC_PLLCFGR_PLLN_0                 (0x001UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */\n#define RCC_PLLCFGR_PLLN_1                 (0x002UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */\n#define RCC_PLLCFGR_PLLN_2                 (0x004UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */\n#define RCC_PLLCFGR_PLLN_3                 (0x008UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */\n#define RCC_PLLCFGR_PLLN_4                 (0x010UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */\n#define RCC_PLLCFGR_PLLN_5                 (0x020UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */\n#define RCC_PLLCFGR_PLLN_6                 (0x040UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */\n#define RCC_PLLCFGR_PLLN_7                 (0x080UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */\n#define RCC_PLLCFGR_PLLN_8                 (0x100UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */\n\n#define RCC_PLLCFGR_PLLP_Pos               (16U)\n#define RCC_PLLCFGR_PLLP_Msk               (0x3UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */\n#define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk\n#define RCC_PLLCFGR_PLLP_0                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */\n#define RCC_PLLCFGR_PLLP_1                 (0x2UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */\n\n#define RCC_PLLCFGR_PLLSRC_Pos             (22U)\n#define RCC_PLLCFGR_PLLSRC_Msk             (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk\n#define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)\n#define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk\n#define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U\n\n#define RCC_PLLCFGR_PLLQ_Pos               (24U)\n#define RCC_PLLCFGR_PLLQ_Msk               (0xFUL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */\n#define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk\n#define RCC_PLLCFGR_PLLQ_0                 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */\n#define RCC_PLLCFGR_PLLQ_1                 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */\n#define RCC_PLLCFGR_PLLQ_2                 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */\n#define RCC_PLLCFGR_PLLQ_3                 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */\n\n\n/********************  Bit definition for RCC_CFGR register  ******************/\n/*!< SW configuration */\n#define RCC_CFGR_SW_Pos                    (0U)\n#define RCC_CFGR_SW_Msk                    (0x3UL << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */\n#define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */\n#define RCC_CFGR_SW_0                      (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */\n#define RCC_CFGR_SW_1                      (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */\n\n#define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */\n#define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */\n#define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */\n\n/*!< SWS configuration */\n#define RCC_CFGR_SWS_Pos                   (2U)\n#define RCC_CFGR_SWS_Msk                   (0x3UL << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */\n#define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */\n#define RCC_CFGR_SWS_0                     (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */\n#define RCC_CFGR_SWS_1                     (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */\n\n#define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */\n#define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */\n#define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */\n\n/*!< HPRE configuration */\n#define RCC_CFGR_HPRE_Pos                  (4U)\n#define RCC_CFGR_HPRE_Msk                  (0xFUL << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */\n#define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */\n#define RCC_CFGR_HPRE_0                    (0x1UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */\n#define RCC_CFGR_HPRE_1                    (0x2UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */\n#define RCC_CFGR_HPRE_2                    (0x4UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */\n#define RCC_CFGR_HPRE_3                    (0x8UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */\n\n#define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */\n#define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */\n#define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */\n#define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */\n#define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */\n#define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */\n#define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */\n#define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */\n#define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */\n\n/*!< PPRE1 configuration */\n#define RCC_CFGR_PPRE1_Pos                 (10U)\n#define RCC_CFGR_PPRE1_Msk                 (0x7UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */\n#define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */\n#define RCC_CFGR_PPRE1_0                   (0x1UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */\n#define RCC_CFGR_PPRE1_1                   (0x2UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */\n#define RCC_CFGR_PPRE1_2                   (0x4UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */\n\n#define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */\n\n/*!< PPRE2 configuration */\n#define RCC_CFGR_PPRE2_Pos                 (13U)\n#define RCC_CFGR_PPRE2_Msk                 (0x7UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */\n#define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */\n#define RCC_CFGR_PPRE2_0                   (0x1UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */\n#define RCC_CFGR_PPRE2_1                   (0x2UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */\n#define RCC_CFGR_PPRE2_2                   (0x4UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */\n\n#define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */\n\n/*!< RTCPRE configuration */\n#define RCC_CFGR_RTCPRE_Pos                (16U)\n#define RCC_CFGR_RTCPRE_Msk                (0x1FUL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */\n#define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk\n#define RCC_CFGR_RTCPRE_0                  (0x01UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */\n#define RCC_CFGR_RTCPRE_1                  (0x02UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */\n#define RCC_CFGR_RTCPRE_2                  (0x04UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */\n#define RCC_CFGR_RTCPRE_3                  (0x08UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */\n#define RCC_CFGR_RTCPRE_4                  (0x10UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */\n\n/*!< MCO1 configuration */\n#define RCC_CFGR_MCO1_Pos                  (21U)\n#define RCC_CFGR_MCO1_Msk                  (0x3UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */\n#define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk\n#define RCC_CFGR_MCO1_0                    (0x1UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */\n#define RCC_CFGR_MCO1_1                    (0x2UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */\n\n#define RCC_CFGR_I2SSRC_Pos                (23U)\n#define RCC_CFGR_I2SSRC_Msk                (0x1UL << RCC_CFGR_I2SSRC_Pos)       /*!< 0x00800000 */\n#define RCC_CFGR_I2SSRC                    RCC_CFGR_I2SSRC_Msk\n\n#define RCC_CFGR_MCO1PRE_Pos               (24U)\n#define RCC_CFGR_MCO1PRE_Msk               (0x7UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */\n#define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk\n#define RCC_CFGR_MCO1PRE_0                 (0x1UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */\n#define RCC_CFGR_MCO1PRE_1                 (0x2UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */\n#define RCC_CFGR_MCO1PRE_2                 (0x4UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */\n\n#define RCC_CFGR_MCO2PRE_Pos               (27U)\n#define RCC_CFGR_MCO2PRE_Msk               (0x7UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */\n#define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk\n#define RCC_CFGR_MCO2PRE_0                 (0x1UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */\n#define RCC_CFGR_MCO2PRE_1                 (0x2UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */\n#define RCC_CFGR_MCO2PRE_2                 (0x4UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */\n\n#define RCC_CFGR_MCO2_Pos                  (30U)\n#define RCC_CFGR_MCO2_Msk                  (0x3UL << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */\n#define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk\n#define RCC_CFGR_MCO2_0                    (0x1UL << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */\n#define RCC_CFGR_MCO2_1                    (0x2UL << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */\n\n/********************  Bit definition for RCC_CIR register  *******************/\n#define RCC_CIR_LSIRDYF_Pos                (0U)\n#define RCC_CIR_LSIRDYF_Msk                (0x1UL << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */\n#define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk\n#define RCC_CIR_LSERDYF_Pos                (1U)\n#define RCC_CIR_LSERDYF_Msk                (0x1UL << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */\n#define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk\n#define RCC_CIR_HSIRDYF_Pos                (2U)\n#define RCC_CIR_HSIRDYF_Msk                (0x1UL << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */\n#define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk\n#define RCC_CIR_HSERDYF_Pos                (3U)\n#define RCC_CIR_HSERDYF_Msk                (0x1UL << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */\n#define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk\n#define RCC_CIR_PLLRDYF_Pos                (4U)\n#define RCC_CIR_PLLRDYF_Msk                (0x1UL << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */\n#define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk\n#define RCC_CIR_PLLI2SRDYF_Pos             (5U)\n#define RCC_CIR_PLLI2SRDYF_Msk             (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */\n#define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk\n\n#define RCC_CIR_CSSF_Pos                   (7U)\n#define RCC_CIR_CSSF_Msk                   (0x1UL << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */\n#define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk\n#define RCC_CIR_LSIRDYIE_Pos               (8U)\n#define RCC_CIR_LSIRDYIE_Msk               (0x1UL << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */\n#define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk\n#define RCC_CIR_LSERDYIE_Pos               (9U)\n#define RCC_CIR_LSERDYIE_Msk               (0x1UL << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */\n#define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk\n#define RCC_CIR_HSIRDYIE_Pos               (10U)\n#define RCC_CIR_HSIRDYIE_Msk               (0x1UL << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */\n#define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk\n#define RCC_CIR_HSERDYIE_Pos               (11U)\n#define RCC_CIR_HSERDYIE_Msk               (0x1UL << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */\n#define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk\n#define RCC_CIR_PLLRDYIE_Pos               (12U)\n#define RCC_CIR_PLLRDYIE_Msk               (0x1UL << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */\n#define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk\n#define RCC_CIR_PLLI2SRDYIE_Pos            (13U)\n#define RCC_CIR_PLLI2SRDYIE_Msk            (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */\n#define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk\n\n#define RCC_CIR_LSIRDYC_Pos                (16U)\n#define RCC_CIR_LSIRDYC_Msk                (0x1UL << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */\n#define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk\n#define RCC_CIR_LSERDYC_Pos                (17U)\n#define RCC_CIR_LSERDYC_Msk                (0x1UL << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */\n#define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk\n#define RCC_CIR_HSIRDYC_Pos                (18U)\n#define RCC_CIR_HSIRDYC_Msk                (0x1UL << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */\n#define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk\n#define RCC_CIR_HSERDYC_Pos                (19U)\n#define RCC_CIR_HSERDYC_Msk                (0x1UL << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */\n#define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk\n#define RCC_CIR_PLLRDYC_Pos                (20U)\n#define RCC_CIR_PLLRDYC_Msk                (0x1UL << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */\n#define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk\n#define RCC_CIR_PLLI2SRDYC_Pos             (21U)\n#define RCC_CIR_PLLI2SRDYC_Msk             (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */\n#define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk\n\n#define RCC_CIR_CSSC_Pos                   (23U)\n#define RCC_CIR_CSSC_Msk                   (0x1UL << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */\n#define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk\n\n/********************  Bit definition for RCC_AHB1RSTR register  **************/\n#define RCC_AHB1RSTR_GPIOARST_Pos          (0U)\n#define RCC_AHB1RSTR_GPIOARST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */\n#define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk\n#define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)\n#define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */\n#define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk\n#define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)\n#define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */\n#define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk\n#define RCC_AHB1RSTR_GPIODRST_Pos          (3U)\n#define RCC_AHB1RSTR_GPIODRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */\n#define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk\n#define RCC_AHB1RSTR_GPIOERST_Pos          (4U)\n#define RCC_AHB1RSTR_GPIOERST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */\n#define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk\n#define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)\n#define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */\n#define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk\n#define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)\n#define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */\n#define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk\n#define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)\n#define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk\n#define RCC_AHB1RSTR_GPIOIRST_Pos          (8U)\n#define RCC_AHB1RSTR_GPIOIRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */\n#define RCC_AHB1RSTR_GPIOIRST              RCC_AHB1RSTR_GPIOIRST_Msk\n#define RCC_AHB1RSTR_CRCRST_Pos            (12U)\n#define RCC_AHB1RSTR_CRCRST_Msk            (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */\n#define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk\n#define RCC_AHB1RSTR_DMA1RST_Pos           (21U)\n#define RCC_AHB1RSTR_DMA1RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */\n#define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk\n#define RCC_AHB1RSTR_DMA2RST_Pos           (22U)\n#define RCC_AHB1RSTR_DMA2RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */\n#define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk\n#define RCC_AHB1RSTR_OTGHRST_Pos           (29U)\n#define RCC_AHB1RSTR_OTGHRST_Msk           (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)  /*!< 0x20000000 */\n#define RCC_AHB1RSTR_OTGHRST               RCC_AHB1RSTR_OTGHRST_Msk\n\n/********************  Bit definition for RCC_AHB2RSTR register  **************/\n#define RCC_AHB2RSTR_RNGRST_Pos            (6U)\n#define RCC_AHB2RSTR_RNGRST_Msk            (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)   /*!< 0x00000040 */\n#define RCC_AHB2RSTR_RNGRST                RCC_AHB2RSTR_RNGRST_Msk\n#define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)\n#define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk\n/********************  Bit definition for RCC_AHB3RSTR register  **************/\n#define RCC_AHB3RSTR_FSMCRST_Pos           (0U)\n#define RCC_AHB3RSTR_FSMCRST_Msk           (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)  /*!< 0x00000001 */\n#define RCC_AHB3RSTR_FSMCRST               RCC_AHB3RSTR_FSMCRST_Msk\n\n\n/********************  Bit definition for RCC_APB1RSTR register  **************/\n#define RCC_APB1RSTR_TIM2RST_Pos           (0U)\n#define RCC_APB1RSTR_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk\n#define RCC_APB1RSTR_TIM3RST_Pos           (1U)\n#define RCC_APB1RSTR_TIM3RST_Msk           (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk\n#define RCC_APB1RSTR_TIM4RST_Pos           (2U)\n#define RCC_APB1RSTR_TIM4RST_Msk           (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */\n#define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk\n#define RCC_APB1RSTR_TIM5RST_Pos           (3U)\n#define RCC_APB1RSTR_TIM5RST_Msk           (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */\n#define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk\n#define RCC_APB1RSTR_TIM6RST_Pos           (4U)\n#define RCC_APB1RSTR_TIM6RST_Msk           (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */\n#define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk\n#define RCC_APB1RSTR_TIM7RST_Pos           (5U)\n#define RCC_APB1RSTR_TIM7RST_Msk           (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */\n#define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk\n#define RCC_APB1RSTR_TIM12RST_Pos          (6U)\n#define RCC_APB1RSTR_TIM12RST_Msk          (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */\n#define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk\n#define RCC_APB1RSTR_TIM13RST_Pos          (7U)\n#define RCC_APB1RSTR_TIM13RST_Msk          (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */\n#define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk\n#define RCC_APB1RSTR_TIM14RST_Pos          (8U)\n#define RCC_APB1RSTR_TIM14RST_Msk          (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */\n#define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk\n#define RCC_APB1RSTR_WWDGRST_Pos           (11U)\n#define RCC_APB1RSTR_WWDGRST_Msk           (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */\n#define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk\n#define RCC_APB1RSTR_SPI2RST_Pos           (14U)\n#define RCC_APB1RSTR_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */\n#define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk\n#define RCC_APB1RSTR_SPI3RST_Pos           (15U)\n#define RCC_APB1RSTR_SPI3RST_Msk           (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */\n#define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk\n#define RCC_APB1RSTR_USART2RST_Pos         (17U)\n#define RCC_APB1RSTR_USART2RST_Msk         (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */\n#define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk\n#define RCC_APB1RSTR_USART3RST_Pos         (18U)\n#define RCC_APB1RSTR_USART3RST_Msk         (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */\n#define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk\n#define RCC_APB1RSTR_UART4RST_Pos          (19U)\n#define RCC_APB1RSTR_UART4RST_Msk          (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */\n#define RCC_APB1RSTR_UART4RST              RCC_APB1RSTR_UART4RST_Msk\n#define RCC_APB1RSTR_UART5RST_Pos          (20U)\n#define RCC_APB1RSTR_UART5RST_Msk          (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */\n#define RCC_APB1RSTR_UART5RST              RCC_APB1RSTR_UART5RST_Msk\n#define RCC_APB1RSTR_I2C1RST_Pos           (21U)\n#define RCC_APB1RSTR_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */\n#define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk\n#define RCC_APB1RSTR_I2C2RST_Pos           (22U)\n#define RCC_APB1RSTR_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */\n#define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk\n#define RCC_APB1RSTR_I2C3RST_Pos           (23U)\n#define RCC_APB1RSTR_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */\n#define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk\n#define RCC_APB1RSTR_CAN1RST_Pos           (25U)\n#define RCC_APB1RSTR_CAN1RST_Msk           (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */\n#define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk\n#define RCC_APB1RSTR_CAN2RST_Pos           (26U)\n#define RCC_APB1RSTR_CAN2RST_Msk           (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */\n#define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk\n#define RCC_APB1RSTR_PWRRST_Pos            (28U)\n#define RCC_APB1RSTR_PWRRST_Msk            (0x1UL << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */\n#define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk\n#define RCC_APB1RSTR_DACRST_Pos            (29U)\n#define RCC_APB1RSTR_DACRST_Msk            (0x1UL << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */\n#define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk\n\n/********************  Bit definition for RCC_APB2RSTR register  **************/\n#define RCC_APB2RSTR_TIM1RST_Pos           (0U)\n#define RCC_APB2RSTR_TIM1RST_Msk           (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk\n#define RCC_APB2RSTR_TIM8RST_Pos           (1U)\n#define RCC_APB2RSTR_TIM8RST_Msk           (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk\n#define RCC_APB2RSTR_USART1RST_Pos         (4U)\n#define RCC_APB2RSTR_USART1RST_Msk         (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */\n#define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk\n#define RCC_APB2RSTR_USART6RST_Pos         (5U)\n#define RCC_APB2RSTR_USART6RST_Msk         (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */\n#define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk\n#define RCC_APB2RSTR_ADCRST_Pos            (8U)\n#define RCC_APB2RSTR_ADCRST_Msk            (0x1UL << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */\n#define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk\n#define RCC_APB2RSTR_SDIORST_Pos           (11U)\n#define RCC_APB2RSTR_SDIORST_Msk           (0x1UL << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */\n#define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk\n#define RCC_APB2RSTR_SPI1RST_Pos           (12U)\n#define RCC_APB2RSTR_SPI1RST_Msk           (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */\n#define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk\n#define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)\n#define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */\n#define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk\n#define RCC_APB2RSTR_TIM9RST_Pos           (16U)\n#define RCC_APB2RSTR_TIM9RST_Msk           (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */\n#define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk\n#define RCC_APB2RSTR_TIM10RST_Pos          (17U)\n#define RCC_APB2RSTR_TIM10RST_Msk          (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */\n#define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk\n#define RCC_APB2RSTR_TIM11RST_Pos          (18U)\n#define RCC_APB2RSTR_TIM11RST_Msk          (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */\n#define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk\n\n/* Old SPI1RST bit definition, maintained for legacy purpose */\n#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST\n\n/********************  Bit definition for RCC_AHB1ENR register  ***************/\n#define RCC_AHB1ENR_GPIOAEN_Pos            (0U)\n#define RCC_AHB1ENR_GPIOAEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */\n#define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk\n#define RCC_AHB1ENR_GPIOBEN_Pos            (1U)\n#define RCC_AHB1ENR_GPIOBEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */\n#define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk\n#define RCC_AHB1ENR_GPIOCEN_Pos            (2U)\n#define RCC_AHB1ENR_GPIOCEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */\n#define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk\n#define RCC_AHB1ENR_GPIODEN_Pos            (3U)\n#define RCC_AHB1ENR_GPIODEN_Msk            (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */\n#define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk\n#define RCC_AHB1ENR_GPIOEEN_Pos            (4U)\n#define RCC_AHB1ENR_GPIOEEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */\n#define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk\n#define RCC_AHB1ENR_GPIOFEN_Pos            (5U)\n#define RCC_AHB1ENR_GPIOFEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */\n#define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk\n#define RCC_AHB1ENR_GPIOGEN_Pos            (6U)\n#define RCC_AHB1ENR_GPIOGEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */\n#define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk\n#define RCC_AHB1ENR_GPIOHEN_Pos            (7U)\n#define RCC_AHB1ENR_GPIOHEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk\n#define RCC_AHB1ENR_GPIOIEN_Pos            (8U)\n#define RCC_AHB1ENR_GPIOIEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)   /*!< 0x00000100 */\n#define RCC_AHB1ENR_GPIOIEN                RCC_AHB1ENR_GPIOIEN_Msk\n#define RCC_AHB1ENR_CRCEN_Pos              (12U)\n#define RCC_AHB1ENR_CRCEN_Msk              (0x1UL << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */\n#define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk\n#define RCC_AHB1ENR_BKPSRAMEN_Pos          (18U)\n#define RCC_AHB1ENR_BKPSRAMEN_Msk          (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */\n#define RCC_AHB1ENR_BKPSRAMEN              RCC_AHB1ENR_BKPSRAMEN_Msk\n#define RCC_AHB1ENR_CCMDATARAMEN_Pos       (20U)\n#define RCC_AHB1ENR_CCMDATARAMEN_Msk       (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */\n#define RCC_AHB1ENR_CCMDATARAMEN           RCC_AHB1ENR_CCMDATARAMEN_Msk\n#define RCC_AHB1ENR_DMA1EN_Pos             (21U)\n#define RCC_AHB1ENR_DMA1EN_Msk             (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */\n#define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk\n#define RCC_AHB1ENR_DMA2EN_Pos             (22U)\n#define RCC_AHB1ENR_DMA2EN_Msk             (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */\n#define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk\n#define RCC_AHB1ENR_OTGHSEN_Pos            (29U)\n#define RCC_AHB1ENR_OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)   /*!< 0x20000000 */\n#define RCC_AHB1ENR_OTGHSEN                RCC_AHB1ENR_OTGHSEN_Msk\n#define RCC_AHB1ENR_OTGHSULPIEN_Pos        (30U)\n#define RCC_AHB1ENR_OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */\n#define RCC_AHB1ENR_OTGHSULPIEN            RCC_AHB1ENR_OTGHSULPIEN_Msk\n/********************  Bit definition for RCC_AHB2ENR register  ***************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_AHB2_SUPPORT                   /*!< AHB2 Bus is supported */\n\n#define RCC_AHB2ENR_RNGEN_Pos              (6U)\n#define RCC_AHB2ENR_RNGEN_Msk              (0x1UL << RCC_AHB2ENR_RNGEN_Pos)     /*!< 0x00000040 */\n#define RCC_AHB2ENR_RNGEN                  RCC_AHB2ENR_RNGEN_Msk\n#define RCC_AHB2ENR_OTGFSEN_Pos            (7U)\n#define RCC_AHB2ENR_OTGFSEN_Msk            (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk\n\n/********************  Bit definition for RCC_AHB3ENR register  ***************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_AHB3_SUPPORT                   /*!< AHB3 Bus is supported */\n\n#define RCC_AHB3ENR_FSMCEN_Pos             (0U)\n#define RCC_AHB3ENR_FSMCEN_Msk             (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)    /*!< 0x00000001 */\n#define RCC_AHB3ENR_FSMCEN                 RCC_AHB3ENR_FSMCEN_Msk\n\n/********************  Bit definition for RCC_APB1ENR register  ***************/\n#define RCC_APB1ENR_TIM2EN_Pos             (0U)\n#define RCC_APB1ENR_TIM2EN_Msk             (0x1UL << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk\n#define RCC_APB1ENR_TIM3EN_Pos             (1U)\n#define RCC_APB1ENR_TIM3EN_Msk             (0x1UL << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk\n#define RCC_APB1ENR_TIM4EN_Pos             (2U)\n#define RCC_APB1ENR_TIM4EN_Msk             (0x1UL << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */\n#define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk\n#define RCC_APB1ENR_TIM5EN_Pos             (3U)\n#define RCC_APB1ENR_TIM5EN_Msk             (0x1UL << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */\n#define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk\n#define RCC_APB1ENR_TIM6EN_Pos             (4U)\n#define RCC_APB1ENR_TIM6EN_Msk             (0x1UL << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */\n#define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk\n#define RCC_APB1ENR_TIM7EN_Pos             (5U)\n#define RCC_APB1ENR_TIM7EN_Msk             (0x1UL << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */\n#define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk\n#define RCC_APB1ENR_TIM12EN_Pos            (6U)\n#define RCC_APB1ENR_TIM12EN_Msk            (0x1UL << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */\n#define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk\n#define RCC_APB1ENR_TIM13EN_Pos            (7U)\n#define RCC_APB1ENR_TIM13EN_Msk            (0x1UL << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */\n#define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk\n#define RCC_APB1ENR_TIM14EN_Pos            (8U)\n#define RCC_APB1ENR_TIM14EN_Msk            (0x1UL << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */\n#define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk\n#define RCC_APB1ENR_WWDGEN_Pos             (11U)\n#define RCC_APB1ENR_WWDGEN_Msk             (0x1UL << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk\n#define RCC_APB1ENR_SPI2EN_Pos             (14U)\n#define RCC_APB1ENR_SPI2EN_Msk             (0x1UL << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */\n#define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk\n#define RCC_APB1ENR_SPI3EN_Pos             (15U)\n#define RCC_APB1ENR_SPI3EN_Msk             (0x1UL << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */\n#define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk\n#define RCC_APB1ENR_USART2EN_Pos           (17U)\n#define RCC_APB1ENR_USART2EN_Msk           (0x1UL << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */\n#define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk\n#define RCC_APB1ENR_USART3EN_Pos           (18U)\n#define RCC_APB1ENR_USART3EN_Msk           (0x1UL << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */\n#define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk\n#define RCC_APB1ENR_UART4EN_Pos            (19U)\n#define RCC_APB1ENR_UART4EN_Msk            (0x1UL << RCC_APB1ENR_UART4EN_Pos)   /*!< 0x00080000 */\n#define RCC_APB1ENR_UART4EN                RCC_APB1ENR_UART4EN_Msk\n#define RCC_APB1ENR_UART5EN_Pos            (20U)\n#define RCC_APB1ENR_UART5EN_Msk            (0x1UL << RCC_APB1ENR_UART5EN_Pos)   /*!< 0x00100000 */\n#define RCC_APB1ENR_UART5EN                RCC_APB1ENR_UART5EN_Msk\n#define RCC_APB1ENR_I2C1EN_Pos             (21U)\n#define RCC_APB1ENR_I2C1EN_Msk             (0x1UL << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */\n#define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk\n#define RCC_APB1ENR_I2C2EN_Pos             (22U)\n#define RCC_APB1ENR_I2C2EN_Msk             (0x1UL << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */\n#define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk\n#define RCC_APB1ENR_I2C3EN_Pos             (23U)\n#define RCC_APB1ENR_I2C3EN_Msk             (0x1UL << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */\n#define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk\n#define RCC_APB1ENR_CAN1EN_Pos             (25U)\n#define RCC_APB1ENR_CAN1EN_Msk             (0x1UL << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */\n#define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk\n#define RCC_APB1ENR_CAN2EN_Pos             (26U)\n#define RCC_APB1ENR_CAN2EN_Msk             (0x1UL << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */\n#define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk\n#define RCC_APB1ENR_PWREN_Pos              (28U)\n#define RCC_APB1ENR_PWREN_Msk              (0x1UL << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */\n#define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk\n#define RCC_APB1ENR_DACEN_Pos              (29U)\n#define RCC_APB1ENR_DACEN_Msk              (0x1UL << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */\n#define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk\n\n/********************  Bit definition for RCC_APB2ENR register  ***************/\n#define RCC_APB2ENR_TIM1EN_Pos             (0U)\n#define RCC_APB2ENR_TIM1EN_Msk             (0x1UL << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk\n#define RCC_APB2ENR_TIM8EN_Pos             (1U)\n#define RCC_APB2ENR_TIM8EN_Msk             (0x1UL << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk\n#define RCC_APB2ENR_USART1EN_Pos           (4U)\n#define RCC_APB2ENR_USART1EN_Msk           (0x1UL << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */\n#define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk\n#define RCC_APB2ENR_USART6EN_Pos           (5U)\n#define RCC_APB2ENR_USART6EN_Msk           (0x1UL << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */\n#define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk\n#define RCC_APB2ENR_ADC1EN_Pos             (8U)\n#define RCC_APB2ENR_ADC1EN_Msk             (0x1UL << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */\n#define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk\n#define RCC_APB2ENR_ADC2EN_Pos             (9U)\n#define RCC_APB2ENR_ADC2EN_Msk             (0x1UL << RCC_APB2ENR_ADC2EN_Pos)    /*!< 0x00000200 */\n#define RCC_APB2ENR_ADC2EN                 RCC_APB2ENR_ADC2EN_Msk\n#define RCC_APB2ENR_ADC3EN_Pos             (10U)\n#define RCC_APB2ENR_ADC3EN_Msk             (0x1UL << RCC_APB2ENR_ADC3EN_Pos)    /*!< 0x00000400 */\n#define RCC_APB2ENR_ADC3EN                 RCC_APB2ENR_ADC3EN_Msk\n#define RCC_APB2ENR_SDIOEN_Pos             (11U)\n#define RCC_APB2ENR_SDIOEN_Msk             (0x1UL << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk\n#define RCC_APB2ENR_SPI1EN_Pos             (12U)\n#define RCC_APB2ENR_SPI1EN_Msk             (0x1UL << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */\n#define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk\n#define RCC_APB2ENR_SYSCFGEN_Pos           (14U)\n#define RCC_APB2ENR_SYSCFGEN_Msk           (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */\n#define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk\n#define RCC_APB2ENR_TIM9EN_Pos             (16U)\n#define RCC_APB2ENR_TIM9EN_Msk             (0x1UL << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */\n#define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk\n#define RCC_APB2ENR_TIM10EN_Pos            (17U)\n#define RCC_APB2ENR_TIM10EN_Msk            (0x1UL << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */\n#define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk\n#define RCC_APB2ENR_TIM11EN_Pos            (18U)\n#define RCC_APB2ENR_TIM11EN_Msk            (0x1UL << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */\n#define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk\n\n/********************  Bit definition for RCC_AHB1LPENR register  *************/\n#define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)\n#define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk\n#define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)\n#define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk\n#define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)\n#define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */\n#define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk\n#define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)\n#define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */\n#define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk\n#define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)\n#define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */\n#define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk\n#define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)\n#define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */\n#define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk\n#define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)\n#define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk\n#define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)\n#define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk\n#define RCC_AHB1LPENR_GPIOILPEN_Pos        (8U)\n#define RCC_AHB1LPENR_GPIOILPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */\n#define RCC_AHB1LPENR_GPIOILPEN            RCC_AHB1LPENR_GPIOILPEN_Msk\n#define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)\n#define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */\n#define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk\n#define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)\n#define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */\n#define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk\n#define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)\n#define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */\n#define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk\n#define RCC_AHB1LPENR_SRAM2LPEN_Pos        (17U)\n#define RCC_AHB1LPENR_SRAM2LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */\n#define RCC_AHB1LPENR_SRAM2LPEN            RCC_AHB1LPENR_SRAM2LPEN_Msk\n#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos      (18U)\n#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk      (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */\n#define RCC_AHB1LPENR_BKPSRAMLPEN          RCC_AHB1LPENR_BKPSRAMLPEN_Msk\n#define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)\n#define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk\n#define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)\n#define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk\n\n#define RCC_AHB1LPENR_OTGHSLPEN_Pos        (29U)\n#define RCC_AHB1LPENR_OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */\n#define RCC_AHB1LPENR_OTGHSLPEN            RCC_AHB1LPENR_OTGHSLPEN_Msk\n#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos    (30U)\n#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */\n#define RCC_AHB1LPENR_OTGHSULPILPEN        RCC_AHB1LPENR_OTGHSULPILPEN_Msk\n\n/********************  Bit definition for RCC_AHB2LPENR register  *************/\n#define RCC_AHB2LPENR_RNGLPEN_Pos          (6U)\n#define RCC_AHB2LPENR_RNGLPEN_Msk          (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB2LPENR_RNGLPEN              RCC_AHB2LPENR_RNGLPEN_Msk\n#define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)\n#define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk\n\n/********************  Bit definition for RCC_AHB3LPENR register  *************/\n#define RCC_AHB3LPENR_FSMCLPEN_Pos         (0U)\n#define RCC_AHB3LPENR_FSMCLPEN_Msk         (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB3LPENR_FSMCLPEN             RCC_AHB3LPENR_FSMCLPEN_Msk\n\n/********************  Bit definition for RCC_APB1LPENR register  *************/\n#define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)\n#define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk\n#define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)\n#define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk\n#define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)\n#define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */\n#define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk\n#define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)\n#define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */\n#define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk\n#define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)\n#define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk\n#define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)\n#define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk\n#define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)\n#define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */\n#define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk\n#define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)\n#define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */\n#define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk\n#define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)\n#define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk\n#define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)\n#define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk\n#define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)\n#define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk\n#define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)\n#define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */\n#define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk\n#define RCC_APB1LPENR_USART2LPEN_Pos       (17U)\n#define RCC_APB1LPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk\n#define RCC_APB1LPENR_USART3LPEN_Pos       (18U)\n#define RCC_APB1LPENR_USART3LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk\n#define RCC_APB1LPENR_UART4LPEN_Pos        (19U)\n#define RCC_APB1LPENR_UART4LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */\n#define RCC_APB1LPENR_UART4LPEN            RCC_APB1LPENR_UART4LPEN_Msk\n#define RCC_APB1LPENR_UART5LPEN_Pos        (20U)\n#define RCC_APB1LPENR_UART5LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */\n#define RCC_APB1LPENR_UART5LPEN            RCC_APB1LPENR_UART5LPEN_Msk\n#define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)\n#define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk\n#define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)\n#define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk\n#define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)\n#define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */\n#define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk\n#define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)\n#define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */\n#define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk\n#define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)\n#define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */\n#define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk\n#define RCC_APB1LPENR_PWRLPEN_Pos          (28U)\n#define RCC_APB1LPENR_PWRLPEN_Msk          (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */\n#define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk\n#define RCC_APB1LPENR_DACLPEN_Pos          (29U)\n#define RCC_APB1LPENR_DACLPEN_Msk          (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */\n#define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk\n\n/********************  Bit definition for RCC_APB2LPENR register  *************/\n#define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)\n#define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk\n#define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)\n#define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk\n#define RCC_APB2LPENR_USART1LPEN_Pos       (4U)\n#define RCC_APB2LPENR_USART1LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk\n#define RCC_APB2LPENR_USART6LPEN_Pos       (5U)\n#define RCC_APB2LPENR_USART6LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk\n#define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)\n#define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk\n#define RCC_APB2LPENR_ADC2LPEN_Pos         (9U)\n#define RCC_APB2LPENR_ADC2LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */\n#define RCC_APB2LPENR_ADC2LPEN             RCC_APB2LPENR_ADC2LPEN_Msk\n#define RCC_APB2LPENR_ADC3LPEN_Pos         (10U)\n#define RCC_APB2LPENR_ADC3LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */\n#define RCC_APB2LPENR_ADC3LPEN             RCC_APB2LPENR_ADC3LPEN_Msk\n#define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)\n#define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk\n#define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)\n#define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */\n#define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk\n#define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)\n#define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk\n#define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)\n#define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */\n#define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk\n#define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)\n#define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk\n#define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)\n#define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk\n\n/********************  Bit definition for RCC_BDCR register  ******************/\n#define RCC_BDCR_LSEON_Pos                 (0U)\n#define RCC_BDCR_LSEON_Msk                 (0x1UL << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */\n#define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk\n#define RCC_BDCR_LSERDY_Pos                (1U)\n#define RCC_BDCR_LSERDY_Msk                (0x1UL << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */\n#define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk\n#define RCC_BDCR_LSEBYP_Pos                (2U)\n#define RCC_BDCR_LSEBYP_Msk                (0x1UL << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */\n#define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk\n\n#define RCC_BDCR_RTCSEL_Pos                (8U)\n#define RCC_BDCR_RTCSEL_Msk                (0x3UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */\n#define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk\n#define RCC_BDCR_RTCSEL_0                  (0x1UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */\n#define RCC_BDCR_RTCSEL_1                  (0x2UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */\n\n#define RCC_BDCR_RTCEN_Pos                 (15U)\n#define RCC_BDCR_RTCEN_Msk                 (0x1UL << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */\n#define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk\n#define RCC_BDCR_BDRST_Pos                 (16U)\n#define RCC_BDCR_BDRST_Msk                 (0x1UL << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */\n#define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk\n\n/********************  Bit definition for RCC_CSR register  *******************/\n#define RCC_CSR_LSION_Pos                  (0U)\n#define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */\n#define RCC_CSR_LSION                      RCC_CSR_LSION_Msk\n#define RCC_CSR_LSIRDY_Pos                 (1U)\n#define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */\n#define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk\n#define RCC_CSR_RMVF_Pos                   (24U)\n#define RCC_CSR_RMVF_Msk                   (0x1UL << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */\n#define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk\n#define RCC_CSR_BORRSTF_Pos                (25U)\n#define RCC_CSR_BORRSTF_Msk                (0x1UL << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */\n#define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk\n#define RCC_CSR_PINRSTF_Pos                (26U)\n#define RCC_CSR_PINRSTF_Msk                (0x1UL << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */\n#define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk\n#define RCC_CSR_PORRSTF_Pos                (27U)\n#define RCC_CSR_PORRSTF_Msk                (0x1UL << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */\n#define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk\n#define RCC_CSR_SFTRSTF_Pos                (28U)\n#define RCC_CSR_SFTRSTF_Msk                (0x1UL << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */\n#define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk\n#define RCC_CSR_IWDGRSTF_Pos               (29U)\n#define RCC_CSR_IWDGRSTF_Msk               (0x1UL << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */\n#define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk\n#define RCC_CSR_WWDGRSTF_Pos               (30U)\n#define RCC_CSR_WWDGRSTF_Msk               (0x1UL << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */\n#define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk\n#define RCC_CSR_LPWRRSTF_Pos               (31U)\n#define RCC_CSR_LPWRRSTF_Msk               (0x1UL << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */\n#define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk\n/* Legacy defines */\n#define RCC_CSR_PADRSTF                    RCC_CSR_PINRSTF\n#define RCC_CSR_WDGRSTF                    RCC_CSR_IWDGRSTF\n\n/********************  Bit definition for RCC_SSCGR register  *****************/\n#define RCC_SSCGR_MODPER_Pos               (0U)\n#define RCC_SSCGR_MODPER_Msk               (0x1FFFUL << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */\n#define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk\n#define RCC_SSCGR_INCSTEP_Pos              (13U)\n#define RCC_SSCGR_INCSTEP_Msk              (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */\n#define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk\n#define RCC_SSCGR_SPREADSEL_Pos            (30U)\n#define RCC_SSCGR_SPREADSEL_Msk            (0x1UL << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */\n#define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk\n#define RCC_SSCGR_SSCGEN_Pos               (31U)\n#define RCC_SSCGR_SSCGEN_Msk               (0x1UL << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */\n#define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk\n\n/********************  Bit definition for RCC_PLLI2SCFGR register  ************/\n#define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)\n#define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */\n#define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk\n#define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */\n#define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */\n#define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */\n#define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */\n#define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */\n#define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */\n#define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */\n\n#define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)\n#define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk\n#define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    RNG                                     */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RNG_CR register  *******************/\n#define RNG_CR_RNGEN_Pos    (2U)\n#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */\n#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk\n#define RNG_CR_IE_Pos       (3U)\n#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */\n#define RNG_CR_IE           RNG_CR_IE_Msk\n\n/********************  Bits definition for RNG_SR register  *******************/\n#define RNG_SR_DRDY_Pos     (0U)\n#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */\n#define RNG_SR_DRDY         RNG_SR_DRDY_Msk\n#define RNG_SR_CECS_Pos     (1U)\n#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */\n#define RNG_SR_CECS         RNG_SR_CECS_Msk\n#define RNG_SR_SECS_Pos     (2U)\n#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */\n#define RNG_SR_SECS         RNG_SR_SECS_Msk\n#define RNG_SR_CEIS_Pos     (5U)\n#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */\n#define RNG_SR_CEIS         RNG_SR_CEIS_Msk\n#define RNG_SR_SEIS_Pos     (6U)\n#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */\n#define RNG_SR_SEIS         RNG_SR_SEIS_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Real-Time Clock (RTC)                            */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions  (not present on all devices in the STM32F4 serie)\n */\n#define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */\n#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */\n/********************  Bits definition for RTC_TR register  *******************/\n#define RTC_TR_PM_Pos                 (22U)\n#define RTC_TR_PM_Msk                 (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */\n#define RTC_TR_PM                     RTC_TR_PM_Msk\n#define RTC_TR_HT_Pos                 (20U)\n#define RTC_TR_HT_Msk                 (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */\n#define RTC_TR_HT                     RTC_TR_HT_Msk\n#define RTC_TR_HT_0                   (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */\n#define RTC_TR_HT_1                   (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */\n#define RTC_TR_HU_Pos                 (16U)\n#define RTC_TR_HU_Msk                 (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */\n#define RTC_TR_HU                     RTC_TR_HU_Msk\n#define RTC_TR_HU_0                   (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */\n#define RTC_TR_HU_1                   (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */\n#define RTC_TR_HU_2                   (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */\n#define RTC_TR_HU_3                   (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */\n#define RTC_TR_MNT_Pos                (12U)\n#define RTC_TR_MNT_Msk                (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */\n#define RTC_TR_MNT                    RTC_TR_MNT_Msk\n#define RTC_TR_MNT_0                  (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */\n#define RTC_TR_MNT_1                  (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */\n#define RTC_TR_MNT_2                  (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */\n#define RTC_TR_MNU_Pos                (8U)\n#define RTC_TR_MNU_Msk                (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */\n#define RTC_TR_MNU                    RTC_TR_MNU_Msk\n#define RTC_TR_MNU_0                  (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */\n#define RTC_TR_MNU_1                  (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */\n#define RTC_TR_MNU_2                  (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */\n#define RTC_TR_MNU_3                  (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */\n#define RTC_TR_ST_Pos                 (4U)\n#define RTC_TR_ST_Msk                 (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */\n#define RTC_TR_ST                     RTC_TR_ST_Msk\n#define RTC_TR_ST_0                   (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */\n#define RTC_TR_ST_1                   (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */\n#define RTC_TR_ST_2                   (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */\n#define RTC_TR_SU_Pos                 (0U)\n#define RTC_TR_SU_Msk                 (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */\n#define RTC_TR_SU                     RTC_TR_SU_Msk\n#define RTC_TR_SU_0                   (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */\n#define RTC_TR_SU_1                   (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */\n#define RTC_TR_SU_2                   (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */\n#define RTC_TR_SU_3                   (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_DR register  *******************/\n#define RTC_DR_YT_Pos                 (20U)\n#define RTC_DR_YT_Msk                 (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */\n#define RTC_DR_YT                     RTC_DR_YT_Msk\n#define RTC_DR_YT_0                   (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */\n#define RTC_DR_YT_1                   (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */\n#define RTC_DR_YT_2                   (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */\n#define RTC_DR_YT_3                   (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */\n#define RTC_DR_YU_Pos                 (16U)\n#define RTC_DR_YU_Msk                 (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */\n#define RTC_DR_YU                     RTC_DR_YU_Msk\n#define RTC_DR_YU_0                   (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */\n#define RTC_DR_YU_1                   (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */\n#define RTC_DR_YU_2                   (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */\n#define RTC_DR_YU_3                   (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */\n#define RTC_DR_WDU_Pos                (13U)\n#define RTC_DR_WDU_Msk                (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */\n#define RTC_DR_WDU                    RTC_DR_WDU_Msk\n#define RTC_DR_WDU_0                  (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */\n#define RTC_DR_WDU_1                  (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */\n#define RTC_DR_WDU_2                  (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */\n#define RTC_DR_MT_Pos                 (12U)\n#define RTC_DR_MT_Msk                 (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */\n#define RTC_DR_MT                     RTC_DR_MT_Msk\n#define RTC_DR_MU_Pos                 (8U)\n#define RTC_DR_MU_Msk                 (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */\n#define RTC_DR_MU                     RTC_DR_MU_Msk\n#define RTC_DR_MU_0                   (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */\n#define RTC_DR_MU_1                   (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */\n#define RTC_DR_MU_2                   (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */\n#define RTC_DR_MU_3                   (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */\n#define RTC_DR_DT_Pos                 (4U)\n#define RTC_DR_DT_Msk                 (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */\n#define RTC_DR_DT                     RTC_DR_DT_Msk\n#define RTC_DR_DT_0                   (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */\n#define RTC_DR_DT_1                   (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */\n#define RTC_DR_DU_Pos                 (0U)\n#define RTC_DR_DU_Msk                 (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */\n#define RTC_DR_DU                     RTC_DR_DU_Msk\n#define RTC_DR_DU_0                   (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */\n#define RTC_DR_DU_1                   (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */\n#define RTC_DR_DU_2                   (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */\n#define RTC_DR_DU_3                   (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_CR register  *******************/\n#define RTC_CR_COE_Pos                (23U)\n#define RTC_CR_COE_Msk                (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */\n#define RTC_CR_COE                    RTC_CR_COE_Msk\n#define RTC_CR_OSEL_Pos               (21U)\n#define RTC_CR_OSEL_Msk               (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */\n#define RTC_CR_OSEL                   RTC_CR_OSEL_Msk\n#define RTC_CR_OSEL_0                 (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */\n#define RTC_CR_OSEL_1                 (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */\n#define RTC_CR_POL_Pos                (20U)\n#define RTC_CR_POL_Msk                (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */\n#define RTC_CR_POL                    RTC_CR_POL_Msk\n#define RTC_CR_COSEL_Pos              (19U)\n#define RTC_CR_COSEL_Msk              (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */\n#define RTC_CR_COSEL                  RTC_CR_COSEL_Msk\n#define RTC_CR_BKP_Pos                 (18U)\n#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */\n#define RTC_CR_BKP                     RTC_CR_BKP_Msk\n#define RTC_CR_SUB1H_Pos              (17U)\n#define RTC_CR_SUB1H_Msk              (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */\n#define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk\n#define RTC_CR_ADD1H_Pos              (16U)\n#define RTC_CR_ADD1H_Msk              (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */\n#define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk\n#define RTC_CR_TSIE_Pos               (15U)\n#define RTC_CR_TSIE_Msk               (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */\n#define RTC_CR_TSIE                   RTC_CR_TSIE_Msk\n#define RTC_CR_WUTIE_Pos              (14U)\n#define RTC_CR_WUTIE_Msk              (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */\n#define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk\n#define RTC_CR_ALRBIE_Pos             (13U)\n#define RTC_CR_ALRBIE_Msk             (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */\n#define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk\n#define RTC_CR_ALRAIE_Pos             (12U)\n#define RTC_CR_ALRAIE_Msk             (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */\n#define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk\n#define RTC_CR_TSE_Pos                (11U)\n#define RTC_CR_TSE_Msk                (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */\n#define RTC_CR_TSE                    RTC_CR_TSE_Msk\n#define RTC_CR_WUTE_Pos               (10U)\n#define RTC_CR_WUTE_Msk               (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */\n#define RTC_CR_WUTE                   RTC_CR_WUTE_Msk\n#define RTC_CR_ALRBE_Pos              (9U)\n#define RTC_CR_ALRBE_Msk              (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */\n#define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk\n#define RTC_CR_ALRAE_Pos              (8U)\n#define RTC_CR_ALRAE_Msk              (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */\n#define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk\n#define RTC_CR_DCE_Pos                (7U)\n#define RTC_CR_DCE_Msk                (0x1UL << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */\n#define RTC_CR_DCE                    RTC_CR_DCE_Msk\n#define RTC_CR_FMT_Pos                (6U)\n#define RTC_CR_FMT_Msk                (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */\n#define RTC_CR_FMT                    RTC_CR_FMT_Msk\n#define RTC_CR_BYPSHAD_Pos            (5U)\n#define RTC_CR_BYPSHAD_Msk            (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */\n#define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk\n#define RTC_CR_REFCKON_Pos            (4U)\n#define RTC_CR_REFCKON_Msk            (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */\n#define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk\n#define RTC_CR_TSEDGE_Pos             (3U)\n#define RTC_CR_TSEDGE_Msk             (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */\n#define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk\n#define RTC_CR_WUCKSEL_Pos            (0U)\n#define RTC_CR_WUCKSEL_Msk            (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */\n#define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk\n#define RTC_CR_WUCKSEL_0              (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */\n#define RTC_CR_WUCKSEL_1              (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */\n#define RTC_CR_WUCKSEL_2              (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */\n\n/* Legacy defines */\n#define RTC_CR_BCK                     RTC_CR_BKP\n\n/********************  Bits definition for RTC_ISR register  ******************/\n#define RTC_ISR_RECALPF_Pos           (16U)\n#define RTC_ISR_RECALPF_Msk           (0x1UL << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */\n#define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk\n#define RTC_ISR_TAMP1F_Pos            (13U)\n#define RTC_ISR_TAMP1F_Msk            (0x1UL << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */\n#define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk\n#define RTC_ISR_TAMP2F_Pos            (14U)\n#define RTC_ISR_TAMP2F_Msk            (0x1UL << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */\n#define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk\n#define RTC_ISR_TSOVF_Pos             (12U)\n#define RTC_ISR_TSOVF_Msk             (0x1UL << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */\n#define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk\n#define RTC_ISR_TSF_Pos               (11U)\n#define RTC_ISR_TSF_Msk               (0x1UL << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */\n#define RTC_ISR_TSF                   RTC_ISR_TSF_Msk\n#define RTC_ISR_WUTF_Pos              (10U)\n#define RTC_ISR_WUTF_Msk              (0x1UL << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */\n#define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk\n#define RTC_ISR_ALRBF_Pos             (9U)\n#define RTC_ISR_ALRBF_Msk             (0x1UL << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */\n#define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk\n#define RTC_ISR_ALRAF_Pos             (8U)\n#define RTC_ISR_ALRAF_Msk             (0x1UL << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */\n#define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk\n#define RTC_ISR_INIT_Pos              (7U)\n#define RTC_ISR_INIT_Msk              (0x1UL << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */\n#define RTC_ISR_INIT                  RTC_ISR_INIT_Msk\n#define RTC_ISR_INITF_Pos             (6U)\n#define RTC_ISR_INITF_Msk             (0x1UL << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */\n#define RTC_ISR_INITF                 RTC_ISR_INITF_Msk\n#define RTC_ISR_RSF_Pos               (5U)\n#define RTC_ISR_RSF_Msk               (0x1UL << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */\n#define RTC_ISR_RSF                   RTC_ISR_RSF_Msk\n#define RTC_ISR_INITS_Pos             (4U)\n#define RTC_ISR_INITS_Msk             (0x1UL << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */\n#define RTC_ISR_INITS                 RTC_ISR_INITS_Msk\n#define RTC_ISR_SHPF_Pos              (3U)\n#define RTC_ISR_SHPF_Msk              (0x1UL << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */\n#define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk\n#define RTC_ISR_WUTWF_Pos             (2U)\n#define RTC_ISR_WUTWF_Msk             (0x1UL << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */\n#define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk\n#define RTC_ISR_ALRBWF_Pos            (1U)\n#define RTC_ISR_ALRBWF_Msk            (0x1UL << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */\n#define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk\n#define RTC_ISR_ALRAWF_Pos            (0U)\n#define RTC_ISR_ALRAWF_Msk            (0x1UL << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */\n#define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk\n\n/********************  Bits definition for RTC_PRER register  *****************/\n#define RTC_PRER_PREDIV_A_Pos         (16U)\n#define RTC_PRER_PREDIV_A_Msk         (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */\n#define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk\n#define RTC_PRER_PREDIV_S_Pos         (0U)\n#define RTC_PRER_PREDIV_S_Msk         (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */\n#define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk\n\n/********************  Bits definition for RTC_WUTR register  *****************/\n#define RTC_WUTR_WUT_Pos              (0U)\n#define RTC_WUTR_WUT_Msk              (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */\n#define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk\n\n/********************  Bits definition for RTC_CALIBR register  ***************/\n#define RTC_CALIBR_DCS_Pos            (7U)\n#define RTC_CALIBR_DCS_Msk            (0x1UL << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */\n#define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk\n#define RTC_CALIBR_DC_Pos             (0U)\n#define RTC_CALIBR_DC_Msk             (0x1FUL << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */\n#define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk\n\n/********************  Bits definition for RTC_ALRMAR register  ***************/\n#define RTC_ALRMAR_MSK4_Pos           (31U)\n#define RTC_ALRMAR_MSK4_Msk           (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk\n#define RTC_ALRMAR_WDSEL_Pos          (30U)\n#define RTC_ALRMAR_WDSEL_Msk          (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk\n#define RTC_ALRMAR_DT_Pos             (28U)\n#define RTC_ALRMAR_DT_Msk             (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk\n#define RTC_ALRMAR_DT_0               (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMAR_DT_1               (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMAR_DU_Pos             (24U)\n#define RTC_ALRMAR_DU_Msk             (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk\n#define RTC_ALRMAR_DU_0               (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMAR_DU_1               (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMAR_DU_2               (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMAR_DU_3               (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMAR_MSK3_Pos           (23U)\n#define RTC_ALRMAR_MSK3_Msk           (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk\n#define RTC_ALRMAR_PM_Pos             (22U)\n#define RTC_ALRMAR_PM_Msk             (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk\n#define RTC_ALRMAR_HT_Pos             (20U)\n#define RTC_ALRMAR_HT_Msk             (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk\n#define RTC_ALRMAR_HT_0               (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMAR_HT_1               (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMAR_HU_Pos             (16U)\n#define RTC_ALRMAR_HU_Msk             (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk\n#define RTC_ALRMAR_HU_0               (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMAR_HU_1               (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMAR_HU_2               (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMAR_HU_3               (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMAR_MSK2_Pos           (15U)\n#define RTC_ALRMAR_MSK2_Msk           (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk\n#define RTC_ALRMAR_MNT_Pos            (12U)\n#define RTC_ALRMAR_MNT_Msk            (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk\n#define RTC_ALRMAR_MNT_0              (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMAR_MNT_1              (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMAR_MNT_2              (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMAR_MNU_Pos            (8U)\n#define RTC_ALRMAR_MNU_Msk            (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk\n#define RTC_ALRMAR_MNU_0              (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMAR_MNU_1              (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMAR_MNU_2              (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMAR_MNU_3              (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMAR_MSK1_Pos           (7U)\n#define RTC_ALRMAR_MSK1_Msk           (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk\n#define RTC_ALRMAR_ST_Pos             (4U)\n#define RTC_ALRMAR_ST_Msk             (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk\n#define RTC_ALRMAR_ST_0               (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMAR_ST_1               (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMAR_ST_2               (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMAR_SU_Pos             (0U)\n#define RTC_ALRMAR_SU_Msk             (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk\n#define RTC_ALRMAR_SU_0               (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMAR_SU_1               (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMAR_SU_2               (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMAR_SU_3               (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_ALRMBR register  ***************/\n#define RTC_ALRMBR_MSK4_Pos           (31U)\n#define RTC_ALRMBR_MSK4_Msk           (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk\n#define RTC_ALRMBR_WDSEL_Pos          (30U)\n#define RTC_ALRMBR_WDSEL_Msk          (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk\n#define RTC_ALRMBR_DT_Pos             (28U)\n#define RTC_ALRMBR_DT_Msk             (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk\n#define RTC_ALRMBR_DT_0               (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMBR_DT_1               (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMBR_DU_Pos             (24U)\n#define RTC_ALRMBR_DU_Msk             (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk\n#define RTC_ALRMBR_DU_0               (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMBR_DU_1               (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMBR_DU_2               (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMBR_DU_3               (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMBR_MSK3_Pos           (23U)\n#define RTC_ALRMBR_MSK3_Msk           (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk\n#define RTC_ALRMBR_PM_Pos             (22U)\n#define RTC_ALRMBR_PM_Msk             (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk\n#define RTC_ALRMBR_HT_Pos             (20U)\n#define RTC_ALRMBR_HT_Msk             (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk\n#define RTC_ALRMBR_HT_0               (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMBR_HT_1               (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMBR_HU_Pos             (16U)\n#define RTC_ALRMBR_HU_Msk             (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk\n#define RTC_ALRMBR_HU_0               (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMBR_HU_1               (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMBR_HU_2               (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMBR_HU_3               (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMBR_MSK2_Pos           (15U)\n#define RTC_ALRMBR_MSK2_Msk           (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk\n#define RTC_ALRMBR_MNT_Pos            (12U)\n#define RTC_ALRMBR_MNT_Msk            (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk\n#define RTC_ALRMBR_MNT_0              (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMBR_MNT_1              (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMBR_MNT_2              (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMBR_MNU_Pos            (8U)\n#define RTC_ALRMBR_MNU_Msk            (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk\n#define RTC_ALRMBR_MNU_0              (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMBR_MNU_1              (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMBR_MNU_2              (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMBR_MNU_3              (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMBR_MSK1_Pos           (7U)\n#define RTC_ALRMBR_MSK1_Msk           (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk\n#define RTC_ALRMBR_ST_Pos             (4U)\n#define RTC_ALRMBR_ST_Msk             (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk\n#define RTC_ALRMBR_ST_0               (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMBR_ST_1               (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMBR_ST_2               (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMBR_SU_Pos             (0U)\n#define RTC_ALRMBR_SU_Msk             (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk\n#define RTC_ALRMBR_SU_0               (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMBR_SU_1               (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMBR_SU_2               (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMBR_SU_3               (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_WPR register  ******************/\n#define RTC_WPR_KEY_Pos               (0U)\n#define RTC_WPR_KEY_Msk               (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */\n#define RTC_WPR_KEY                   RTC_WPR_KEY_Msk\n\n/********************  Bits definition for RTC_SSR register  ******************/\n#define RTC_SSR_SS_Pos                (0U)\n#define RTC_SSR_SS_Msk                (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */\n#define RTC_SSR_SS                    RTC_SSR_SS_Msk\n\n/********************  Bits definition for RTC_SHIFTR register  ***************/\n#define RTC_SHIFTR_SUBFS_Pos          (0U)\n#define RTC_SHIFTR_SUBFS_Msk          (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */\n#define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk\n#define RTC_SHIFTR_ADD1S_Pos          (31U)\n#define RTC_SHIFTR_ADD1S_Msk          (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */\n#define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk\n\n/********************  Bits definition for RTC_TSTR register  *****************/\n#define RTC_TSTR_PM_Pos               (22U)\n#define RTC_TSTR_PM_Msk               (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */\n#define RTC_TSTR_PM                   RTC_TSTR_PM_Msk\n#define RTC_TSTR_HT_Pos               (20U)\n#define RTC_TSTR_HT_Msk               (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */\n#define RTC_TSTR_HT                   RTC_TSTR_HT_Msk\n#define RTC_TSTR_HT_0                 (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */\n#define RTC_TSTR_HT_1                 (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */\n#define RTC_TSTR_HU_Pos               (16U)\n#define RTC_TSTR_HU_Msk               (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */\n#define RTC_TSTR_HU                   RTC_TSTR_HU_Msk\n#define RTC_TSTR_HU_0                 (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */\n#define RTC_TSTR_HU_1                 (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */\n#define RTC_TSTR_HU_2                 (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */\n#define RTC_TSTR_HU_3                 (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */\n#define RTC_TSTR_MNT_Pos              (12U)\n#define RTC_TSTR_MNT_Msk              (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */\n#define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk\n#define RTC_TSTR_MNT_0                (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */\n#define RTC_TSTR_MNT_1                (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */\n#define RTC_TSTR_MNT_2                (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */\n#define RTC_TSTR_MNU_Pos              (8U)\n#define RTC_TSTR_MNU_Msk              (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */\n#define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk\n#define RTC_TSTR_MNU_0                (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */\n#define RTC_TSTR_MNU_1                (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */\n#define RTC_TSTR_MNU_2                (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */\n#define RTC_TSTR_MNU_3                (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */\n#define RTC_TSTR_ST_Pos               (4U)\n#define RTC_TSTR_ST_Msk               (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */\n#define RTC_TSTR_ST                   RTC_TSTR_ST_Msk\n#define RTC_TSTR_ST_0                 (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */\n#define RTC_TSTR_ST_1                 (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */\n#define RTC_TSTR_ST_2                 (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */\n#define RTC_TSTR_SU_Pos               (0U)\n#define RTC_TSTR_SU_Msk               (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */\n#define RTC_TSTR_SU                   RTC_TSTR_SU_Msk\n#define RTC_TSTR_SU_0                 (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */\n#define RTC_TSTR_SU_1                 (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */\n#define RTC_TSTR_SU_2                 (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */\n#define RTC_TSTR_SU_3                 (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSDR register  *****************/\n#define RTC_TSDR_WDU_Pos              (13U)\n#define RTC_TSDR_WDU_Msk              (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */\n#define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk\n#define RTC_TSDR_WDU_0                (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */\n#define RTC_TSDR_WDU_1                (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */\n#define RTC_TSDR_WDU_2                (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */\n#define RTC_TSDR_MT_Pos               (12U)\n#define RTC_TSDR_MT_Msk               (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */\n#define RTC_TSDR_MT                   RTC_TSDR_MT_Msk\n#define RTC_TSDR_MU_Pos               (8U)\n#define RTC_TSDR_MU_Msk               (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */\n#define RTC_TSDR_MU                   RTC_TSDR_MU_Msk\n#define RTC_TSDR_MU_0                 (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */\n#define RTC_TSDR_MU_1                 (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */\n#define RTC_TSDR_MU_2                 (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */\n#define RTC_TSDR_MU_3                 (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */\n#define RTC_TSDR_DT_Pos               (4U)\n#define RTC_TSDR_DT_Msk               (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */\n#define RTC_TSDR_DT                   RTC_TSDR_DT_Msk\n#define RTC_TSDR_DT_0                 (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */\n#define RTC_TSDR_DT_1                 (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */\n#define RTC_TSDR_DU_Pos               (0U)\n#define RTC_TSDR_DU_Msk               (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */\n#define RTC_TSDR_DU                   RTC_TSDR_DU_Msk\n#define RTC_TSDR_DU_0                 (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */\n#define RTC_TSDR_DU_1                 (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */\n#define RTC_TSDR_DU_2                 (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */\n#define RTC_TSDR_DU_3                 (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSSSR register  ****************/\n#define RTC_TSSSR_SS_Pos              (0U)\n#define RTC_TSSSR_SS_Msk              (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */\n#define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk\n\n/********************  Bits definition for RTC_CAL register  *****************/\n#define RTC_CALR_CALP_Pos             (15U)\n#define RTC_CALR_CALP_Msk             (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */\n#define RTC_CALR_CALP                 RTC_CALR_CALP_Msk\n#define RTC_CALR_CALW8_Pos            (14U)\n#define RTC_CALR_CALW8_Msk            (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */\n#define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk\n#define RTC_CALR_CALW16_Pos           (13U)\n#define RTC_CALR_CALW16_Msk           (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */\n#define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk\n#define RTC_CALR_CALM_Pos             (0U)\n#define RTC_CALR_CALM_Msk             (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */\n#define RTC_CALR_CALM                 RTC_CALR_CALM_Msk\n#define RTC_CALR_CALM_0               (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */\n#define RTC_CALR_CALM_1               (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */\n#define RTC_CALR_CALM_2               (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */\n#define RTC_CALR_CALM_3               (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */\n#define RTC_CALR_CALM_4               (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */\n#define RTC_CALR_CALM_5               (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */\n#define RTC_CALR_CALM_6               (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */\n#define RTC_CALR_CALM_7               (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */\n#define RTC_CALR_CALM_8               (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */\n\n/********************  Bits definition for RTC_TAFCR register  ****************/\n#define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)\n#define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */\n#define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk\n#define RTC_TAFCR_TSINSEL_Pos         (17U)\n#define RTC_TAFCR_TSINSEL_Msk         (0x1UL << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */\n#define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk\n#define RTC_TAFCR_TAMP1INSEL_Pos      (16U)\n#define RTC_TAFCR_TAMP1INSEL_Msk      (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)        /*!< 0x00010000 */\n#define RTC_TAFCR_TAMP1INSEL          RTC_TAFCR_TAMP1INSEL_Msk\n#define RTC_TAFCR_TAMPPUDIS_Pos       (15U)\n#define RTC_TAFCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */\n#define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk\n#define RTC_TAFCR_TAMPPRCH_Pos        (13U)\n#define RTC_TAFCR_TAMPPRCH_Msk        (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */\n#define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk\n#define RTC_TAFCR_TAMPPRCH_0          (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */\n#define RTC_TAFCR_TAMPPRCH_1          (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */\n#define RTC_TAFCR_TAMPFLT_Pos         (11U)\n#define RTC_TAFCR_TAMPFLT_Msk         (0x3UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */\n#define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk\n#define RTC_TAFCR_TAMPFLT_0           (0x1UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */\n#define RTC_TAFCR_TAMPFLT_1           (0x2UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */\n#define RTC_TAFCR_TAMPFREQ_Pos        (8U)\n#define RTC_TAFCR_TAMPFREQ_Msk        (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */\n#define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk\n#define RTC_TAFCR_TAMPFREQ_0          (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */\n#define RTC_TAFCR_TAMPFREQ_1          (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */\n#define RTC_TAFCR_TAMPFREQ_2          (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */\n#define RTC_TAFCR_TAMPTS_Pos          (7U)\n#define RTC_TAFCR_TAMPTS_Msk          (0x1UL << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */\n#define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk\n#define RTC_TAFCR_TAMP2TRG_Pos        (4U)\n#define RTC_TAFCR_TAMP2TRG_Msk        (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */\n#define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk\n#define RTC_TAFCR_TAMP2E_Pos          (3U)\n#define RTC_TAFCR_TAMP2E_Msk          (0x1UL << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */\n#define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk\n#define RTC_TAFCR_TAMPIE_Pos          (2U)\n#define RTC_TAFCR_TAMPIE_Msk          (0x1UL << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */\n#define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk\n#define RTC_TAFCR_TAMP1TRG_Pos        (1U)\n#define RTC_TAFCR_TAMP1TRG_Msk        (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */\n#define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk\n#define RTC_TAFCR_TAMP1E_Pos          (0U)\n#define RTC_TAFCR_TAMP1E_Msk          (0x1UL << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */\n#define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk\n\n/* Legacy defines */\n#define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMP1INSEL\n\n/********************  Bits definition for RTC_ALRMASSR register  *************/\n#define RTC_ALRMASSR_MASKSS_Pos       (24U)\n#define RTC_ALRMASSR_MASKSS_Msk       (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk\n#define RTC_ALRMASSR_MASKSS_0         (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMASSR_MASKSS_1         (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMASSR_MASKSS_2         (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMASSR_MASKSS_3         (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMASSR_SS_Pos           (0U)\n#define RTC_ALRMASSR_SS_Msk           (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk\n\n/********************  Bits definition for RTC_ALRMBSSR register  *************/\n#define RTC_ALRMBSSR_MASKSS_Pos       (24U)\n#define RTC_ALRMBSSR_MASKSS_Msk       (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk\n#define RTC_ALRMBSSR_MASKSS_0         (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMBSSR_MASKSS_1         (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMBSSR_MASKSS_2         (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMBSSR_MASKSS_3         (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMBSSR_SS_Pos           (0U)\n#define RTC_ALRMBSSR_SS_Msk           (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk\n\n/********************  Bits definition for RTC_BKP0R register  ****************/\n#define RTC_BKP0R_Pos                 (0U)\n#define RTC_BKP0R_Msk                 (0xFFFFFFFFUL << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP0R                     RTC_BKP0R_Msk\n\n/********************  Bits definition for RTC_BKP1R register  ****************/\n#define RTC_BKP1R_Pos                 (0U)\n#define RTC_BKP1R_Msk                 (0xFFFFFFFFUL << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP1R                     RTC_BKP1R_Msk\n\n/********************  Bits definition for RTC_BKP2R register  ****************/\n#define RTC_BKP2R_Pos                 (0U)\n#define RTC_BKP2R_Msk                 (0xFFFFFFFFUL << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP2R                     RTC_BKP2R_Msk\n\n/********************  Bits definition for RTC_BKP3R register  ****************/\n#define RTC_BKP3R_Pos                 (0U)\n#define RTC_BKP3R_Msk                 (0xFFFFFFFFUL << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP3R                     RTC_BKP3R_Msk\n\n/********************  Bits definition for RTC_BKP4R register  ****************/\n#define RTC_BKP4R_Pos                 (0U)\n#define RTC_BKP4R_Msk                 (0xFFFFFFFFUL << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP4R                     RTC_BKP4R_Msk\n\n/********************  Bits definition for RTC_BKP5R register  ****************/\n#define RTC_BKP5R_Pos                 (0U)\n#define RTC_BKP5R_Msk                 (0xFFFFFFFFUL << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP5R                     RTC_BKP5R_Msk\n\n/********************  Bits definition for RTC_BKP6R register  ****************/\n#define RTC_BKP6R_Pos                 (0U)\n#define RTC_BKP6R_Msk                 (0xFFFFFFFFUL << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP6R                     RTC_BKP6R_Msk\n\n/********************  Bits definition for RTC_BKP7R register  ****************/\n#define RTC_BKP7R_Pos                 (0U)\n#define RTC_BKP7R_Msk                 (0xFFFFFFFFUL << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP7R                     RTC_BKP7R_Msk\n\n/********************  Bits definition for RTC_BKP8R register  ****************/\n#define RTC_BKP8R_Pos                 (0U)\n#define RTC_BKP8R_Msk                 (0xFFFFFFFFUL << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP8R                     RTC_BKP8R_Msk\n\n/********************  Bits definition for RTC_BKP9R register  ****************/\n#define RTC_BKP9R_Pos                 (0U)\n#define RTC_BKP9R_Msk                 (0xFFFFFFFFUL << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP9R                     RTC_BKP9R_Msk\n\n/********************  Bits definition for RTC_BKP10R register  ***************/\n#define RTC_BKP10R_Pos                (0U)\n#define RTC_BKP10R_Msk                (0xFFFFFFFFUL << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP10R                    RTC_BKP10R_Msk\n\n/********************  Bits definition for RTC_BKP11R register  ***************/\n#define RTC_BKP11R_Pos                (0U)\n#define RTC_BKP11R_Msk                (0xFFFFFFFFUL << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP11R                    RTC_BKP11R_Msk\n\n/********************  Bits definition for RTC_BKP12R register  ***************/\n#define RTC_BKP12R_Pos                (0U)\n#define RTC_BKP12R_Msk                (0xFFFFFFFFUL << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP12R                    RTC_BKP12R_Msk\n\n/********************  Bits definition for RTC_BKP13R register  ***************/\n#define RTC_BKP13R_Pos                (0U)\n#define RTC_BKP13R_Msk                (0xFFFFFFFFUL << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP13R                    RTC_BKP13R_Msk\n\n/********************  Bits definition for RTC_BKP14R register  ***************/\n#define RTC_BKP14R_Pos                (0U)\n#define RTC_BKP14R_Msk                (0xFFFFFFFFUL << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP14R                    RTC_BKP14R_Msk\n\n/********************  Bits definition for RTC_BKP15R register  ***************/\n#define RTC_BKP15R_Pos                (0U)\n#define RTC_BKP15R_Msk                (0xFFFFFFFFUL << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP15R                    RTC_BKP15R_Msk\n\n/********************  Bits definition for RTC_BKP16R register  ***************/\n#define RTC_BKP16R_Pos                (0U)\n#define RTC_BKP16R_Msk                (0xFFFFFFFFUL << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP16R                    RTC_BKP16R_Msk\n\n/********************  Bits definition for RTC_BKP17R register  ***************/\n#define RTC_BKP17R_Pos                (0U)\n#define RTC_BKP17R_Msk                (0xFFFFFFFFUL << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP17R                    RTC_BKP17R_Msk\n\n/********************  Bits definition for RTC_BKP18R register  ***************/\n#define RTC_BKP18R_Pos                (0U)\n#define RTC_BKP18R_Msk                (0xFFFFFFFFUL << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP18R                    RTC_BKP18R_Msk\n\n/********************  Bits definition for RTC_BKP19R register  ***************/\n#define RTC_BKP19R_Pos                (0U)\n#define RTC_BKP19R_Msk                (0xFFFFFFFFUL << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP19R                    RTC_BKP19R_Msk\n\n/******************** Number of backup registers ******************************/\n#define RTC_BKP_NUMBER                       0x000000014U\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                          SD host Interface                                 */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SDIO_POWER register  ******************/\n#define SDIO_POWER_PWRCTRL_Pos         (0U)\n#define SDIO_POWER_PWRCTRL_Msk         (0x3UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */\n#define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */\n#define SDIO_POWER_PWRCTRL_0           (0x1UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x01 */\n#define SDIO_POWER_PWRCTRL_1           (0x2UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x02 */\n\n/******************  Bit definition for SDIO_CLKCR register  ******************/\n#define SDIO_CLKCR_CLKDIV_Pos          (0U)\n#define SDIO_CLKCR_CLKDIV_Msk          (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */\n#define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor             */\n#define SDIO_CLKCR_CLKEN_Pos           (8U)\n#define SDIO_CLKCR_CLKEN_Msk           (0x1UL << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */\n#define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit                */\n#define SDIO_CLKCR_PWRSAV_Pos          (9U)\n#define SDIO_CLKCR_PWRSAV_Msk          (0x1UL << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */\n#define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit  */\n#define SDIO_CLKCR_BYPASS_Pos          (10U)\n#define SDIO_CLKCR_BYPASS_Msk          (0x1UL << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */\n#define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */\n\n#define SDIO_CLKCR_WIDBUS_Pos          (11U)\n#define SDIO_CLKCR_WIDBUS_Msk          (0x3UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */\n#define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\n#define SDIO_CLKCR_WIDBUS_0            (0x1UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x0800 */\n#define SDIO_CLKCR_WIDBUS_1            (0x2UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x1000 */\n\n#define SDIO_CLKCR_NEGEDGE_Pos         (13U)\n#define SDIO_CLKCR_NEGEDGE_Msk         (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */\n#define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */\n#define SDIO_CLKCR_HWFC_EN_Pos         (14U)\n#define SDIO_CLKCR_HWFC_EN_Msk         (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */\n#define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable          */\n\n/*******************  Bit definition for SDIO_ARG register  *******************/\n#define SDIO_ARG_CMDARG_Pos            (0U)\n#define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */\n#define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */\n\n/*******************  Bit definition for SDIO_CMD register  *******************/\n#define SDIO_CMD_CMDINDEX_Pos          (0U)\n#define SDIO_CMD_CMDINDEX_Msk          (0x3FUL << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */\n#define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index                               */\n\n#define SDIO_CMD_WAITRESP_Pos          (6U)\n#define SDIO_CMD_WAITRESP_Msk          (0x3UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */\n#define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */\n#define SDIO_CMD_WAITRESP_0            (0x1UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0040 */\n#define SDIO_CMD_WAITRESP_1            (0x2UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0080 */\n\n#define SDIO_CMD_WAITINT_Pos           (8U)\n#define SDIO_CMD_WAITINT_Msk           (0x1UL << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */\n#define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request                               */\n#define SDIO_CMD_WAITPEND_Pos          (9U)\n#define SDIO_CMD_WAITPEND_Msk          (0x1UL << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */\n#define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\n#define SDIO_CMD_CPSMEN_Pos            (10U)\n#define SDIO_CMD_CPSMEN_Msk            (0x1UL << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */\n#define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit                   */\n#define SDIO_CMD_SDIOSUSPEND_Pos       (11U)\n#define SDIO_CMD_SDIOSUSPEND_Msk       (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */\n#define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command                                         */\n#define SDIO_CMD_ENCMDCOMPL_Pos        (12U)\n#define SDIO_CMD_ENCMDCOMPL_Msk        (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)       /*!< 0x00001000 */\n#define SDIO_CMD_ENCMDCOMPL            SDIO_CMD_ENCMDCOMPL_Msk                 /*!<Enable CMD completion                                          */\n#define SDIO_CMD_NIEN_Pos              (13U)\n#define SDIO_CMD_NIEN_Msk              (0x1UL << SDIO_CMD_NIEN_Pos)             /*!< 0x00002000 */\n#define SDIO_CMD_NIEN                  SDIO_CMD_NIEN_Msk                       /*!<Not Interrupt Enable                                           */\n#define SDIO_CMD_CEATACMD_Pos          (14U)\n#define SDIO_CMD_CEATACMD_Msk          (0x1UL << SDIO_CMD_CEATACMD_Pos)         /*!< 0x00004000 */\n#define SDIO_CMD_CEATACMD              SDIO_CMD_CEATACMD_Msk                   /*!<CE-ATA command                                                 */\n\n/*****************  Bit definition for SDIO_RESPCMD register  *****************/\n#define SDIO_RESPCMD_RESPCMD_Pos       (0U)\n#define SDIO_RESPCMD_RESPCMD_Msk       (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */\n#define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */\n\n/******************  Bit definition for SDIO_RESP0 register  ******************/\n#define SDIO_RESP0_CARDSTATUS0_Pos     (0U)\n#define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP1 register  ******************/\n#define SDIO_RESP1_CARDSTATUS1_Pos     (0U)\n#define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP2 register  ******************/\n#define SDIO_RESP2_CARDSTATUS2_Pos     (0U)\n#define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP3 register  ******************/\n#define SDIO_RESP3_CARDSTATUS3_Pos     (0U)\n#define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP4 register  ******************/\n#define SDIO_RESP4_CARDSTATUS4_Pos     (0U)\n#define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_DTIMER register  *****************/\n#define SDIO_DTIMER_DATATIME_Pos       (0U)\n#define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */\n\n/******************  Bit definition for SDIO_DLEN register  *******************/\n#define SDIO_DLEN_DATALENGTH_Pos       (0U)\n#define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */\n\n/******************  Bit definition for SDIO_DCTRL register  ******************/\n#define SDIO_DCTRL_DTEN_Pos            (0U)\n#define SDIO_DCTRL_DTEN_Msk            (0x1UL << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */\n#define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit         */\n#define SDIO_DCTRL_DTDIR_Pos           (1U)\n#define SDIO_DCTRL_DTDIR_Msk           (0x1UL << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */\n#define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */\n#define SDIO_DCTRL_DTMODE_Pos          (2U)\n#define SDIO_DCTRL_DTMODE_Msk          (0x1UL << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */\n#define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection      */\n#define SDIO_DCTRL_DMAEN_Pos           (3U)\n#define SDIO_DCTRL_DMAEN_Msk           (0x1UL << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */\n#define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit                   */\n\n#define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)\n#define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */\n#define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */\n#define SDIO_DCTRL_DBLOCKSIZE_0        (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0010 */\n#define SDIO_DCTRL_DBLOCKSIZE_1        (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0020 */\n#define SDIO_DCTRL_DBLOCKSIZE_2        (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0040 */\n#define SDIO_DCTRL_DBLOCKSIZE_3        (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0080 */\n\n#define SDIO_DCTRL_RWSTART_Pos         (8U)\n#define SDIO_DCTRL_RWSTART_Msk         (0x1UL << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */\n#define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start         */\n#define SDIO_DCTRL_RWSTOP_Pos          (9U)\n#define SDIO_DCTRL_RWSTOP_Msk          (0x1UL << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */\n#define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop          */\n#define SDIO_DCTRL_RWMOD_Pos           (10U)\n#define SDIO_DCTRL_RWMOD_Msk           (0x1UL << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */\n#define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode          */\n#define SDIO_DCTRL_SDIOEN_Pos          (11U)\n#define SDIO_DCTRL_SDIOEN_Msk          (0x1UL << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */\n#define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */\n\n/******************  Bit definition for SDIO_DCOUNT register  *****************/\n#define SDIO_DCOUNT_DATACOUNT_Pos      (0U)\n#define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */\n\n/******************  Bit definition for SDIO_STA register  ********************/\n#define SDIO_STA_CCRCFAIL_Pos          (0U)\n#define SDIO_STA_CCRCFAIL_Msk          (0x1UL << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */\n#define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */\n#define SDIO_STA_DCRCFAIL_Pos          (1U)\n#define SDIO_STA_DCRCFAIL_Msk          (0x1UL << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */\n#define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */\n#define SDIO_STA_CTIMEOUT_Pos          (2U)\n#define SDIO_STA_CTIMEOUT_Msk          (0x1UL << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */\n#define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */\n#define SDIO_STA_DTIMEOUT_Pos          (3U)\n#define SDIO_STA_DTIMEOUT_Msk          (0x1UL << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */\n#define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */\n#define SDIO_STA_TXUNDERR_Pos          (4U)\n#define SDIO_STA_TXUNDERR_Msk          (0x1UL << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */\n#define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */\n#define SDIO_STA_RXOVERR_Pos           (5U)\n#define SDIO_STA_RXOVERR_Msk           (0x1UL << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */\n#define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */\n#define SDIO_STA_CMDREND_Pos           (6U)\n#define SDIO_STA_CMDREND_Msk           (0x1UL << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */\n#define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */\n#define SDIO_STA_CMDSENT_Pos           (7U)\n#define SDIO_STA_CMDSENT_Msk           (0x1UL << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */\n#define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */\n#define SDIO_STA_DATAEND_Pos           (8U)\n#define SDIO_STA_DATAEND_Msk           (0x1UL << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */\n#define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */\n#define SDIO_STA_STBITERR_Pos          (9U)\n#define SDIO_STA_STBITERR_Msk          (0x1UL << SDIO_STA_STBITERR_Pos)         /*!< 0x00000200 */\n#define SDIO_STA_STBITERR              SDIO_STA_STBITERR_Msk                   /*!<Start bit not detected on all data signals in wide bus mode */\n#define SDIO_STA_DBCKEND_Pos           (10U)\n#define SDIO_STA_DBCKEND_Msk           (0x1UL << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */\n#define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */\n#define SDIO_STA_CMDACT_Pos            (11U)\n#define SDIO_STA_CMDACT_Msk            (0x1UL << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */\n#define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */\n#define SDIO_STA_TXACT_Pos             (12U)\n#define SDIO_STA_TXACT_Msk             (0x1UL << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */\n#define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */\n#define SDIO_STA_RXACT_Pos             (13U)\n#define SDIO_STA_RXACT_Msk             (0x1UL << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */\n#define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */\n#define SDIO_STA_TXFIFOHE_Pos          (14U)\n#define SDIO_STA_TXFIFOHE_Msk          (0x1UL << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */\n#define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\n#define SDIO_STA_RXFIFOHF_Pos          (15U)\n#define SDIO_STA_RXFIFOHF_Msk          (0x1UL << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */\n#define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\n#define SDIO_STA_TXFIFOF_Pos           (16U)\n#define SDIO_STA_TXFIFOF_Msk           (0x1UL << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */\n#define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */\n#define SDIO_STA_RXFIFOF_Pos           (17U)\n#define SDIO_STA_RXFIFOF_Msk           (0x1UL << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */\n#define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */\n#define SDIO_STA_TXFIFOE_Pos           (18U)\n#define SDIO_STA_TXFIFOE_Msk           (0x1UL << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */\n#define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */\n#define SDIO_STA_RXFIFOE_Pos           (19U)\n#define SDIO_STA_RXFIFOE_Msk           (0x1UL << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */\n#define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */\n#define SDIO_STA_TXDAVL_Pos            (20U)\n#define SDIO_STA_TXDAVL_Msk            (0x1UL << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */\n#define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */\n#define SDIO_STA_RXDAVL_Pos            (21U)\n#define SDIO_STA_RXDAVL_Msk            (0x1UL << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */\n#define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */\n#define SDIO_STA_SDIOIT_Pos            (22U)\n#define SDIO_STA_SDIOIT_Msk            (0x1UL << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */\n#define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */\n#define SDIO_STA_CEATAEND_Pos          (23U)\n#define SDIO_STA_CEATAEND_Msk          (0x1UL << SDIO_STA_CEATAEND_Pos)         /*!< 0x00800000 */\n#define SDIO_STA_CEATAEND              SDIO_STA_CEATAEND_Msk                   /*!<CE-ATA command completion signal received for CMD61 */\n\n/*******************  Bit definition for SDIO_ICR register  *******************/\n#define SDIO_ICR_CCRCFAILC_Pos         (0U)\n#define SDIO_ICR_CCRCFAILC_Msk         (0x1UL << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */\n#define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */\n#define SDIO_ICR_DCRCFAILC_Pos         (1U)\n#define SDIO_ICR_DCRCFAILC_Msk         (0x1UL << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */\n#define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */\n#define SDIO_ICR_CTIMEOUTC_Pos         (2U)\n#define SDIO_ICR_CTIMEOUTC_Msk         (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */\n#define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */\n#define SDIO_ICR_DTIMEOUTC_Pos         (3U)\n#define SDIO_ICR_DTIMEOUTC_Msk         (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */\n#define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */\n#define SDIO_ICR_TXUNDERRC_Pos         (4U)\n#define SDIO_ICR_TXUNDERRC_Msk         (0x1UL << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */\n#define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */\n#define SDIO_ICR_RXOVERRC_Pos          (5U)\n#define SDIO_ICR_RXOVERRC_Msk          (0x1UL << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */\n#define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */\n#define SDIO_ICR_CMDRENDC_Pos          (6U)\n#define SDIO_ICR_CMDRENDC_Msk          (0x1UL << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */\n#define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */\n#define SDIO_ICR_CMDSENTC_Pos          (7U)\n#define SDIO_ICR_CMDSENTC_Msk          (0x1UL << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */\n#define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */\n#define SDIO_ICR_DATAENDC_Pos          (8U)\n#define SDIO_ICR_DATAENDC_Msk          (0x1UL << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */\n#define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */\n#define SDIO_ICR_STBITERRC_Pos         (9U)\n#define SDIO_ICR_STBITERRC_Msk         (0x1UL << SDIO_ICR_STBITERRC_Pos)        /*!< 0x00000200 */\n#define SDIO_ICR_STBITERRC             SDIO_ICR_STBITERRC_Msk                  /*!<STBITERR flag clear bit */\n#define SDIO_ICR_DBCKENDC_Pos          (10U)\n#define SDIO_ICR_DBCKENDC_Msk          (0x1UL << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */\n#define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */\n#define SDIO_ICR_SDIOITC_Pos           (22U)\n#define SDIO_ICR_SDIOITC_Msk           (0x1UL << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */\n#define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */\n#define SDIO_ICR_CEATAENDC_Pos         (23U)\n#define SDIO_ICR_CEATAENDC_Msk         (0x1UL << SDIO_ICR_CEATAENDC_Pos)        /*!< 0x00800000 */\n#define SDIO_ICR_CEATAENDC             SDIO_ICR_CEATAENDC_Msk                  /*!<CEATAEND flag clear bit */\n\n/******************  Bit definition for SDIO_MASK register  *******************/\n#define SDIO_MASK_CCRCFAILIE_Pos       (0U)\n#define SDIO_MASK_CCRCFAILIE_Msk       (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */\n#define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */\n#define SDIO_MASK_DCRCFAILIE_Pos       (1U)\n#define SDIO_MASK_DCRCFAILIE_Msk       (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */\n#define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */\n#define SDIO_MASK_CTIMEOUTIE_Pos       (2U)\n#define SDIO_MASK_CTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */\n#define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */\n#define SDIO_MASK_DTIMEOUTIE_Pos       (3U)\n#define SDIO_MASK_DTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */\n#define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */\n#define SDIO_MASK_TXUNDERRIE_Pos       (4U)\n#define SDIO_MASK_TXUNDERRIE_Msk       (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */\n#define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */\n#define SDIO_MASK_RXOVERRIE_Pos        (5U)\n#define SDIO_MASK_RXOVERRIE_Msk        (0x1UL << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */\n#define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */\n#define SDIO_MASK_CMDRENDIE_Pos        (6U)\n#define SDIO_MASK_CMDRENDIE_Msk        (0x1UL << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */\n#define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */\n#define SDIO_MASK_CMDSENTIE_Pos        (7U)\n#define SDIO_MASK_CMDSENTIE_Msk        (0x1UL << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */\n#define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */\n#define SDIO_MASK_DATAENDIE_Pos        (8U)\n#define SDIO_MASK_DATAENDIE_Msk        (0x1UL << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */\n#define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */\n#define SDIO_MASK_STBITERRIE_Pos       (9U)\n#define SDIO_MASK_STBITERRIE_Msk       (0x1UL << SDIO_MASK_STBITERRIE_Pos)      /*!< 0x00000200 */\n#define SDIO_MASK_STBITERRIE           SDIO_MASK_STBITERRIE_Msk                /*!<Start Bit Error Interrupt Enable           */\n#define SDIO_MASK_DBCKENDIE_Pos        (10U)\n#define SDIO_MASK_DBCKENDIE_Msk        (0x1UL << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */\n#define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */\n#define SDIO_MASK_CMDACTIE_Pos         (11U)\n#define SDIO_MASK_CMDACTIE_Msk         (0x1UL << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */\n#define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */\n#define SDIO_MASK_TXACTIE_Pos          (12U)\n#define SDIO_MASK_TXACTIE_Msk          (0x1UL << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */\n#define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */\n#define SDIO_MASK_RXACTIE_Pos          (13U)\n#define SDIO_MASK_RXACTIE_Msk          (0x1UL << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */\n#define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */\n#define SDIO_MASK_TXFIFOHEIE_Pos       (14U)\n#define SDIO_MASK_TXFIFOHEIE_Msk       (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */\n#define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */\n#define SDIO_MASK_RXFIFOHFIE_Pos       (15U)\n#define SDIO_MASK_RXFIFOHFIE_Msk       (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */\n#define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */\n#define SDIO_MASK_TXFIFOFIE_Pos        (16U)\n#define SDIO_MASK_TXFIFOFIE_Msk        (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */\n#define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */\n#define SDIO_MASK_RXFIFOFIE_Pos        (17U)\n#define SDIO_MASK_RXFIFOFIE_Msk        (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */\n#define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */\n#define SDIO_MASK_TXFIFOEIE_Pos        (18U)\n#define SDIO_MASK_TXFIFOEIE_Msk        (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */\n#define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_RXFIFOEIE_Pos        (19U)\n#define SDIO_MASK_RXFIFOEIE_Msk        (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */\n#define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_TXDAVLIE_Pos         (20U)\n#define SDIO_MASK_TXDAVLIE_Msk         (0x1UL << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */\n#define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */\n#define SDIO_MASK_RXDAVLIE_Pos         (21U)\n#define SDIO_MASK_RXDAVLIE_Msk         (0x1UL << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */\n#define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */\n#define SDIO_MASK_SDIOITIE_Pos         (22U)\n#define SDIO_MASK_SDIOITIE_Msk         (0x1UL << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */\n#define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */\n#define SDIO_MASK_CEATAENDIE_Pos       (23U)\n#define SDIO_MASK_CEATAENDIE_Msk       (0x1UL << SDIO_MASK_CEATAENDIE_Pos)      /*!< 0x00800000 */\n#define SDIO_MASK_CEATAENDIE           SDIO_MASK_CEATAENDIE_Msk                /*!<CE-ATA command completion signal received Interrupt Enable */\n\n/*****************  Bit definition for SDIO_FIFOCNT register  *****************/\n#define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)\n#define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */\n#define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */\n\n/******************  Bit definition for SDIO_FIFO register  *******************/\n#define SDIO_FIFO_FIFODATA_Pos         (0U)\n#define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Serial Peripheral Interface                         */\n/*                                                                            */\n/******************************************************************************/\n#define SPI_I2S_FULLDUPLEX_SUPPORT                                             /*!< I2S Full-Duplex support */\n\n/*******************  Bit definition for SPI_CR1 register  ********************/\n#define SPI_CR1_CPHA_Pos            (0U)\n#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */\n#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */\n#define SPI_CR1_CPOL_Pos            (1U)\n#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */\n#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */\n#define SPI_CR1_MSTR_Pos            (2U)\n#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */\n#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */\n\n#define SPI_CR1_BR_Pos              (3U)\n#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */\n#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */\n#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */\n#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */\n#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */\n\n#define SPI_CR1_SPE_Pos             (6U)\n#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */\n#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */\n#define SPI_CR1_LSBFIRST_Pos        (7U)\n#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */\n#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */\n#define SPI_CR1_SSI_Pos             (8U)\n#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */\n#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */\n#define SPI_CR1_SSM_Pos             (9U)\n#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */\n#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */\n#define SPI_CR1_RXONLY_Pos          (10U)\n#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */\n#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */\n#define SPI_CR1_DFF_Pos             (11U)\n#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */\n#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */\n#define SPI_CR1_CRCNEXT_Pos         (12U)\n#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */\n#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */\n#define SPI_CR1_CRCEN_Pos           (13U)\n#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */\n#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */\n#define SPI_CR1_BIDIOE_Pos          (14U)\n#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */\n#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */\n#define SPI_CR1_BIDIMODE_Pos        (15U)\n#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */\n#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */\n\n/*******************  Bit definition for SPI_CR2 register  ********************/\n#define SPI_CR2_RXDMAEN_Pos         (0U)\n#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */\n#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */\n#define SPI_CR2_TXDMAEN_Pos         (1U)\n#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */\n#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */\n#define SPI_CR2_SSOE_Pos            (2U)\n#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */\n#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */\n#define SPI_CR2_FRF_Pos             (4U)\n#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */\n#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */\n#define SPI_CR2_ERRIE_Pos           (5U)\n#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */\n#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */\n#define SPI_CR2_RXNEIE_Pos          (6U)\n#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */\n#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */\n#define SPI_CR2_TXEIE_Pos           (7U)\n#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */\n#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */\n\n/********************  Bit definition for SPI_SR register  ********************/\n#define SPI_SR_RXNE_Pos             (0U)\n#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */\n#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */\n#define SPI_SR_TXE_Pos              (1U)\n#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */\n#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */\n#define SPI_SR_CHSIDE_Pos           (2U)\n#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */\n#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */\n#define SPI_SR_UDR_Pos              (3U)\n#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */\n#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */\n#define SPI_SR_CRCERR_Pos           (4U)\n#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */\n#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */\n#define SPI_SR_MODF_Pos             (5U)\n#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */\n#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */\n#define SPI_SR_OVR_Pos              (6U)\n#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */\n#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */\n#define SPI_SR_BSY_Pos              (7U)\n#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */\n#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */\n#define SPI_SR_FRE_Pos              (8U)\n#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */\n#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */\n\n/********************  Bit definition for SPI_DR register  ********************/\n#define SPI_DR_DR_Pos               (0U)\n#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */\n#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */\n\n/*******************  Bit definition for SPI_CRCPR register  ******************/\n#define SPI_CRCPR_CRCPOLY_Pos       (0U)\n#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */\n#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */\n\n/******************  Bit definition for SPI_RXCRCR register  ******************/\n#define SPI_RXCRCR_RXCRC_Pos        (0U)\n#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */\n\n/******************  Bit definition for SPI_TXCRCR register  ******************/\n#define SPI_TXCRCR_TXCRC_Pos        (0U)\n#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */\n\n/******************  Bit definition for SPI_I2SCFGR register  *****************/\n#define SPI_I2SCFGR_CHLEN_Pos       (0U)\n#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */\n#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */\n\n#define SPI_I2SCFGR_DATLEN_Pos      (1U)\n#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */\n#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */\n#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */\n#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */\n\n#define SPI_I2SCFGR_CKPOL_Pos       (3U)\n#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */\n#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */\n\n#define SPI_I2SCFGR_I2SSTD_Pos      (4U)\n#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */\n#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */\n#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */\n#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */\n\n#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)\n#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */\n#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */\n\n#define SPI_I2SCFGR_I2SCFG_Pos      (8U)\n#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */\n#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */\n#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */\n#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */\n\n#define SPI_I2SCFGR_I2SE_Pos        (10U)\n#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */\n#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */\n#define SPI_I2SCFGR_I2SMOD_Pos      (11U)\n#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */\n#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */\n\n/******************  Bit definition for SPI_I2SPR register  *******************/\n#define SPI_I2SPR_I2SDIV_Pos        (0U)\n#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */\n#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */\n#define SPI_I2SPR_ODD_Pos           (8U)\n#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */\n#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */\n#define SPI_I2SPR_MCKOE_Pos         (9U)\n#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */\n#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                 SYSCFG                                     */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SYSCFG_MEMRMP register  ***************/\n#define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)\n#define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */\n#define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */\n#define SYSCFG_MEMRMP_MEM_MODE_0             (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */\n#define SYSCFG_MEMRMP_MEM_MODE_1             (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */\n/******************  Bit definition for SYSCFG_PMC register  ******************/\n#define SYSCFG_PMC_MII_RMII_SEL_Pos          (23U)\n#define SYSCFG_PMC_MII_RMII_SEL_Msk          (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */\n#define SYSCFG_PMC_MII_RMII_SEL              SYSCFG_PMC_MII_RMII_SEL_Msk       /*!<Ethernet PHY interface selection */\n/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */\n#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL\n\n/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\n#define SYSCFG_EXTICR1_EXTI0_Pos             (0U)\n#define SYSCFG_EXTICR1_EXTI0_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */\n#define SYSCFG_EXTICR1_EXTI1_Pos             (4U)\n#define SYSCFG_EXTICR1_EXTI1_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */\n#define SYSCFG_EXTICR1_EXTI2_Pos             (8U)\n#define SYSCFG_EXTICR1_EXTI2_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */\n#define SYSCFG_EXTICR1_EXTI3_Pos             (12U)\n#define SYSCFG_EXTICR1_EXTI3_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */\n/**\n  * @brief   EXTI0 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PD              0x0003U                           /*!<PD[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PE              0x0004U                           /*!<PE[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PF              0x0005U                           /*!<PF[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PG              0x0006U                           /*!<PG[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PI              0x0008U                           /*!<PI[0] pin */\n\n/**\n  * @brief   EXTI1 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PD              0x0030U                           /*!<PD[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PE              0x0040U                           /*!<PE[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PF              0x0050U                           /*!<PF[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PG              0x0060U                           /*!<PG[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PI              0x0080U                           /*!<PI[1] pin */\n\n/**\n  * @brief   EXTI2 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PD              0x0300U                           /*!<PD[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PE              0x0400U                           /*!<PE[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PF              0x0500U                           /*!<PF[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PG              0x0600U                           /*!<PG[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PI              0x0800U                           /*!<PI[2] pin */\n\n/**\n  * @brief   EXTI3 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PD              0x3000U                           /*!<PD[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PE              0x4000U                           /*!<PE[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PF              0x5000U                           /*!<PF[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PG              0x6000U                           /*!<PG[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PI              0x8000U                           /*!<PI[3] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\n#define SYSCFG_EXTICR2_EXTI4_Pos             (0U)\n#define SYSCFG_EXTICR2_EXTI4_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */\n#define SYSCFG_EXTICR2_EXTI5_Pos             (4U)\n#define SYSCFG_EXTICR2_EXTI5_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */\n#define SYSCFG_EXTICR2_EXTI6_Pos             (8U)\n#define SYSCFG_EXTICR2_EXTI6_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */\n#define SYSCFG_EXTICR2_EXTI7_Pos             (12U)\n#define SYSCFG_EXTICR2_EXTI7_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */\n\n/**\n  * @brief   EXTI4 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PD              0x0003U                           /*!<PD[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PE              0x0004U                           /*!<PE[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PF              0x0005U                           /*!<PF[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PG              0x0006U                           /*!<PG[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PI              0x0008U                           /*!<PI[4] pin */\n\n/**\n  * @brief   EXTI5 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PD              0x0030U                           /*!<PD[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PE              0x0040U                           /*!<PE[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PF              0x0050U                           /*!<PF[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PG              0x0060U                           /*!<PG[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PI              0x0080U                           /*!<PI[5] pin */\n\n/**\n  * @brief   EXTI6 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PD              0x0300U                           /*!<PD[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PE              0x0400U                           /*!<PE[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PF              0x0500U                           /*!<PF[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PG              0x0600U                           /*!<PG[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PI              0x0800U                           /*!<PI[6] pin */\n\n/**\n  * @brief   EXTI7 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PD              0x3000U                           /*!<PD[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PE              0x4000U                           /*!<PE[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PF              0x5000U                           /*!<PF[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PG              0x6000U                           /*!<PG[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PI              0x8000U                           /*!<PI[7] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\n#define SYSCFG_EXTICR3_EXTI8_Pos             (0U)\n#define SYSCFG_EXTICR3_EXTI8_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */\n#define SYSCFG_EXTICR3_EXTI9_Pos             (4U)\n#define SYSCFG_EXTICR3_EXTI9_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */\n#define SYSCFG_EXTICR3_EXTI10_Pos            (8U)\n#define SYSCFG_EXTICR3_EXTI10_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */\n#define SYSCFG_EXTICR3_EXTI11_Pos            (12U)\n#define SYSCFG_EXTICR3_EXTI11_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */\n\n/**\n  * @brief   EXTI8 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PD              0x0003U                           /*!<PD[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PE              0x0004U                           /*!<PE[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PF              0x0005U                           /*!<PF[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PG              0x0006U                           /*!<PG[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PI              0x0008U                           /*!<PI[8] pin */\n\n/**\n  * @brief   EXTI9 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PD              0x0030U                           /*!<PD[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PE              0x0040U                           /*!<PE[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PF              0x0050U                           /*!<PF[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PG              0x0060U                           /*!<PG[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PI              0x0080U                           /*!<PI[9] pin */\n\n/**\n  * @brief   EXTI10 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PD             0x0300U                           /*!<PD[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PE             0x0400U                           /*!<PE[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PF             0x0500U                           /*!<PF[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PG             0x0600U                           /*!<PG[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PI             0x0800U                           /*!<PI[10] pin */\n\n/**\n  * @brief   EXTI11 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PD             0x3000U                           /*!<PD[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PE             0x4000U                           /*!<PE[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PF             0x5000U                           /*!<PF[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PG             0x6000U                           /*!<PG[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PI             0x8000U                           /*!<PI[11] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\n#define SYSCFG_EXTICR4_EXTI12_Pos            (0U)\n#define SYSCFG_EXTICR4_EXTI12_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */\n#define SYSCFG_EXTICR4_EXTI13_Pos            (4U)\n#define SYSCFG_EXTICR4_EXTI13_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */\n#define SYSCFG_EXTICR4_EXTI14_Pos            (8U)\n#define SYSCFG_EXTICR4_EXTI14_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */\n#define SYSCFG_EXTICR4_EXTI15_Pos            (12U)\n#define SYSCFG_EXTICR4_EXTI15_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */\n\n/**\n  * @brief   EXTI12 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PD             0x0003U                           /*!<PD[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PE             0x0004U                           /*!<PE[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PF             0x0005U                           /*!<PF[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PG             0x0006U                           /*!<PG[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */\n\n/**\n  * @brief   EXTI13 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PD             0x0030U                           /*!<PD[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PE             0x0040U                           /*!<PE[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PF             0x0050U                           /*!<PF[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PG             0x0060U                           /*!<PG[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */\n\n/**\n  * @brief   EXTI14 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PD             0x0300U                           /*!<PD[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PE             0x0400U                           /*!<PE[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PF             0x0500U                           /*!<PF[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PG             0x0600U                           /*!<PG[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */\n\n/**\n  * @brief   EXTI15 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PD             0x3000U                           /*!<PD[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PE             0x4000U                           /*!<PE[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PF             0x5000U                           /*!<PF[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PG             0x6000U                           /*!<PG[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */\n\n/******************  Bit definition for SYSCFG_CMPCR register  ****************/\n#define SYSCFG_CMPCR_CMP_PD_Pos              (0U)\n#define SYSCFG_CMPCR_CMP_PD_Msk              (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */\n#define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */\n#define SYSCFG_CMPCR_READY_Pos               (8U)\n#define SYSCFG_CMPCR_READY_Msk               (0x1UL << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */\n#define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    TIM                                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for TIM_CR1 register  ********************/\n#define TIM_CR1_CEN_Pos           (0U)\n#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */\n#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */\n#define TIM_CR1_UDIS_Pos          (1U)\n#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */\n#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */\n#define TIM_CR1_URS_Pos           (2U)\n#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */\n#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */\n#define TIM_CR1_OPM_Pos           (3U)\n#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */\n#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */\n#define TIM_CR1_DIR_Pos           (4U)\n#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */\n#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */\n\n#define TIM_CR1_CMS_Pos           (5U)\n#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */\n#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */\n#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR1_ARPE_Pos          (7U)\n#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */\n#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */\n\n#define TIM_CR1_CKD_Pos           (8U)\n#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */\n#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */\n#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */\n#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */\n\n/*******************  Bit definition for TIM_CR2 register  ********************/\n#define TIM_CR2_CCPC_Pos          (0U)\n#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */\n#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */\n#define TIM_CR2_CCUS_Pos          (2U)\n#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */\n#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */\n#define TIM_CR2_CCDS_Pos          (3U)\n#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */\n#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */\n\n#define TIM_CR2_MMS_Pos           (4U)\n#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */\n#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */\n#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */\n#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR2_TI1S_Pos          (7U)\n#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */\n#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */\n#define TIM_CR2_OIS1_Pos          (8U)\n#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */\n#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */\n#define TIM_CR2_OIS1N_Pos         (9U)\n#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */\n#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */\n#define TIM_CR2_OIS2_Pos          (10U)\n#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */\n#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */\n#define TIM_CR2_OIS2N_Pos         (11U)\n#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */\n#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */\n#define TIM_CR2_OIS3_Pos          (12U)\n#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */\n#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */\n#define TIM_CR2_OIS3N_Pos         (13U)\n#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */\n#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */\n#define TIM_CR2_OIS4_Pos          (14U)\n#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */\n#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */\n\n/*******************  Bit definition for TIM_SMCR register  *******************/\n#define TIM_SMCR_SMS_Pos          (0U)\n#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */\n#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */\n#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */\n#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */\n#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */\n\n#define TIM_SMCR_TS_Pos           (4U)\n#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */\n#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */\n#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */\n#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */\n#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */\n\n#define TIM_SMCR_MSM_Pos          (7U)\n#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */\n#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */\n\n#define TIM_SMCR_ETF_Pos          (8U)\n#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */\n#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */\n#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */\n#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */\n#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */\n#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */\n\n#define TIM_SMCR_ETPS_Pos         (12U)\n#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */\n#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */\n#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */\n#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */\n\n#define TIM_SMCR_ECE_Pos          (14U)\n#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */\n#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */\n#define TIM_SMCR_ETP_Pos          (15U)\n#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */\n#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */\n\n/*******************  Bit definition for TIM_DIER register  *******************/\n#define TIM_DIER_UIE_Pos          (0U)\n#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */\n#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */\n#define TIM_DIER_CC1IE_Pos        (1U)\n#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */\n#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */\n#define TIM_DIER_CC2IE_Pos        (2U)\n#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */\n#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */\n#define TIM_DIER_CC3IE_Pos        (3U)\n#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */\n#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */\n#define TIM_DIER_CC4IE_Pos        (4U)\n#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */\n#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */\n#define TIM_DIER_COMIE_Pos        (5U)\n#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */\n#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */\n#define TIM_DIER_TIE_Pos          (6U)\n#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */\n#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */\n#define TIM_DIER_BIE_Pos          (7U)\n#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */\n#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */\n#define TIM_DIER_UDE_Pos          (8U)\n#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */\n#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */\n#define TIM_DIER_CC1DE_Pos        (9U)\n#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */\n#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */\n#define TIM_DIER_CC2DE_Pos        (10U)\n#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */\n#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */\n#define TIM_DIER_CC3DE_Pos        (11U)\n#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */\n#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */\n#define TIM_DIER_CC4DE_Pos        (12U)\n#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */\n#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */\n#define TIM_DIER_COMDE_Pos        (13U)\n#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */\n#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */\n#define TIM_DIER_TDE_Pos          (14U)\n#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */\n#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */\n\n/********************  Bit definition for TIM_SR register  ********************/\n#define TIM_SR_UIF_Pos            (0U)\n#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */\n#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */\n#define TIM_SR_CC1IF_Pos          (1U)\n#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */\n#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */\n#define TIM_SR_CC2IF_Pos          (2U)\n#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */\n#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */\n#define TIM_SR_CC3IF_Pos          (3U)\n#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */\n#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */\n#define TIM_SR_CC4IF_Pos          (4U)\n#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */\n#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */\n#define TIM_SR_COMIF_Pos          (5U)\n#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */\n#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */\n#define TIM_SR_TIF_Pos            (6U)\n#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */\n#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */\n#define TIM_SR_BIF_Pos            (7U)\n#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */\n#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */\n#define TIM_SR_CC1OF_Pos          (9U)\n#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */\n#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */\n#define TIM_SR_CC2OF_Pos          (10U)\n#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */\n#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */\n#define TIM_SR_CC3OF_Pos          (11U)\n#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */\n#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */\n#define TIM_SR_CC4OF_Pos          (12U)\n#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */\n#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */\n\n/*******************  Bit definition for TIM_EGR register  ********************/\n#define TIM_EGR_UG_Pos            (0U)\n#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */\n#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */\n#define TIM_EGR_CC1G_Pos          (1U)\n#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */\n#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */\n#define TIM_EGR_CC2G_Pos          (2U)\n#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */\n#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */\n#define TIM_EGR_CC3G_Pos          (3U)\n#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */\n#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */\n#define TIM_EGR_CC4G_Pos          (4U)\n#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */\n#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */\n#define TIM_EGR_COMG_Pos          (5U)\n#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */\n#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */\n#define TIM_EGR_TG_Pos            (6U)\n#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */\n#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */\n#define TIM_EGR_BG_Pos            (7U)\n#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */\n#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */\n\n/******************  Bit definition for TIM_CCMR1 register  *******************/\n#define TIM_CCMR1_CC1S_Pos        (0U)\n#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\n#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR1_OC1FE_Pos       (2U)\n#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */\n#define TIM_CCMR1_OC1PE_Pos       (3U)\n#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */\n\n#define TIM_CCMR1_OC1M_Pos        (4U)\n#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */\n#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR1_OC1CE_Pos       (7U)\n#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */\n\n#define TIM_CCMR1_CC2S_Pos        (8U)\n#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\n#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR1_OC2FE_Pos       (10U)\n#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */\n#define TIM_CCMR1_OC2PE_Pos       (11U)\n#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */\n\n#define TIM_CCMR1_OC2M_Pos        (12U)\n#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */\n#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR1_OC2CE_Pos       (15U)\n#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR1_IC1PSC_Pos      (2U)\n#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\n#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR1_IC1F_Pos        (4U)\n#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */\n#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR1_IC2PSC_Pos      (10U)\n#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */\n#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR1_IC2F_Pos        (12U)\n#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */\n#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */\n\n/******************  Bit definition for TIM_CCMR2 register  *******************/\n#define TIM_CCMR2_CC3S_Pos        (0U)\n#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */\n#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR2_OC3FE_Pos       (2U)\n#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */\n#define TIM_CCMR2_OC3PE_Pos       (3U)\n#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */\n\n#define TIM_CCMR2_OC3M_Pos        (4U)\n#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\n#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR2_OC3CE_Pos       (7U)\n#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */\n\n#define TIM_CCMR2_CC4S_Pos        (8U)\n#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\n#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR2_OC4FE_Pos       (10U)\n#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */\n#define TIM_CCMR2_OC4PE_Pos       (11U)\n#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */\n\n#define TIM_CCMR2_OC4M_Pos        (12U)\n#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\n#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR2_OC4CE_Pos       (15U)\n#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR2_IC3PSC_Pos      (2U)\n#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\n#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR2_IC3F_Pos        (4U)\n#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\n#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR2_IC4PSC_Pos      (10U)\n#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\n#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR2_IC4F_Pos        (12U)\n#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\n#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */\n\n/*******************  Bit definition for TIM_CCER register  *******************/\n#define TIM_CCER_CC1E_Pos         (0U)\n#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */\n#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */\n#define TIM_CCER_CC1P_Pos         (1U)\n#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */\n#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */\n#define TIM_CCER_CC1NE_Pos        (2U)\n#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */\n#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */\n#define TIM_CCER_CC1NP_Pos        (3U)\n#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */\n#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */\n#define TIM_CCER_CC2E_Pos         (4U)\n#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */\n#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */\n#define TIM_CCER_CC2P_Pos         (5U)\n#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */\n#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */\n#define TIM_CCER_CC2NE_Pos        (6U)\n#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */\n#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */\n#define TIM_CCER_CC2NP_Pos        (7U)\n#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */\n#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */\n#define TIM_CCER_CC3E_Pos         (8U)\n#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */\n#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */\n#define TIM_CCER_CC3P_Pos         (9U)\n#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */\n#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */\n#define TIM_CCER_CC3NE_Pos        (10U)\n#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */\n#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */\n#define TIM_CCER_CC3NP_Pos        (11U)\n#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */\n#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */\n#define TIM_CCER_CC4E_Pos         (12U)\n#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */\n#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */\n#define TIM_CCER_CC4P_Pos         (13U)\n#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */\n#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */\n#define TIM_CCER_CC4NP_Pos        (15U)\n#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */\n#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */\n\n/*******************  Bit definition for TIM_CNT register  ********************/\n#define TIM_CNT_CNT_Pos           (0U)\n#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0xFFFFFFFF */\n#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                                  /*!<Counter Value            */\n\n/*******************  Bit definition for TIM_PSC register  ********************/\n#define TIM_PSC_PSC_Pos           (0U)\n#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */\n#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */\n\n/*******************  Bit definition for TIM_ARR register  ********************/\n#define TIM_ARR_ARR_Pos           (0U)\n#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */\n#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */\n\n/*******************  Bit definition for TIM_RCR register  ********************/\n#define TIM_RCR_REP_Pos           (0U)\n#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */\n#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */\n\n/*******************  Bit definition for TIM_CCR1 register  *******************/\n#define TIM_CCR1_CCR1_Pos         (0U)\n#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */\n\n/*******************  Bit definition for TIM_CCR2 register  *******************/\n#define TIM_CCR2_CCR2_Pos         (0U)\n#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */\n\n/*******************  Bit definition for TIM_CCR3 register  *******************/\n#define TIM_CCR3_CCR3_Pos         (0U)\n#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */\n\n/*******************  Bit definition for TIM_CCR4 register  *******************/\n#define TIM_CCR4_CCR4_Pos         (0U)\n#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */\n\n/*******************  Bit definition for TIM_BDTR register  *******************/\n#define TIM_BDTR_DTG_Pos          (0U)\n#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */\n#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\n#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */\n#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */\n#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */\n#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */\n#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */\n#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */\n#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */\n#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */\n\n#define TIM_BDTR_LOCK_Pos         (8U)\n#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */\n#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */\n#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */\n#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */\n\n#define TIM_BDTR_OSSI_Pos         (10U)\n#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */\n#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */\n#define TIM_BDTR_OSSR_Pos         (11U)\n#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */\n#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */\n#define TIM_BDTR_BKE_Pos          (12U)\n#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */\n#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */\n#define TIM_BDTR_BKP_Pos          (13U)\n#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */\n#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */\n#define TIM_BDTR_AOE_Pos          (14U)\n#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */\n#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */\n#define TIM_BDTR_MOE_Pos          (15U)\n#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */\n#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */\n\n/*******************  Bit definition for TIM_DCR register  ********************/\n#define TIM_DCR_DBA_Pos           (0U)\n#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */\n#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */\n#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */\n#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */\n#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */\n#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */\n#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */\n\n#define TIM_DCR_DBL_Pos           (8U)\n#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */\n#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */\n#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */\n#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */\n#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */\n#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */\n#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */\n\n/*******************  Bit definition for TIM_DMAR register  *******************/\n#define TIM_DMAR_DMAB_Pos         (0U)\n#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */\n#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */\n\n/*******************  Bit definition for TIM_OR register  *********************/\n#define TIM_OR_TI1_RMP_Pos        (0U)\n#define TIM_OR_TI1_RMP_Msk        (0x3UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000003 */\n#define TIM_OR_TI1_RMP            TIM_OR_TI1_RMP_Msk                           /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */\n#define TIM_OR_TI1_RMP_0          (0x1UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000001 */\n#define TIM_OR_TI1_RMP_1          (0x2UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000002 */\n\n#define TIM_OR_TI4_RMP_Pos        (6U)\n#define TIM_OR_TI4_RMP_Msk        (0x3UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */\n#define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */\n#define TIM_OR_TI4_RMP_0          (0x1UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */\n#define TIM_OR_TI4_RMP_1          (0x2UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */\n#define TIM_OR_ITR1_RMP_Pos       (10U)\n#define TIM_OR_ITR1_RMP_Msk       (0x3UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */\n#define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\n#define TIM_OR_ITR1_RMP_0         (0x1UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */\n#define TIM_OR_ITR1_RMP_1         (0x2UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*         Universal Synchronous Asynchronous Receiver Transmitter            */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for USART_SR register  *******************/\n#define USART_SR_PE_Pos               (0U)\n#define USART_SR_PE_Msk               (0x1UL << USART_SR_PE_Pos)                /*!< 0x00000001 */\n#define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */\n#define USART_SR_FE_Pos               (1U)\n#define USART_SR_FE_Msk               (0x1UL << USART_SR_FE_Pos)                /*!< 0x00000002 */\n#define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */\n#define USART_SR_NE_Pos               (2U)\n#define USART_SR_NE_Msk               (0x1UL << USART_SR_NE_Pos)                /*!< 0x00000004 */\n#define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */\n#define USART_SR_ORE_Pos              (3U)\n#define USART_SR_ORE_Msk              (0x1UL << USART_SR_ORE_Pos)               /*!< 0x00000008 */\n#define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */\n#define USART_SR_IDLE_Pos             (4U)\n#define USART_SR_IDLE_Msk             (0x1UL << USART_SR_IDLE_Pos)              /*!< 0x00000010 */\n#define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */\n#define USART_SR_RXNE_Pos             (5U)\n#define USART_SR_RXNE_Msk             (0x1UL << USART_SR_RXNE_Pos)              /*!< 0x00000020 */\n#define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */\n#define USART_SR_TC_Pos               (6U)\n#define USART_SR_TC_Msk               (0x1UL << USART_SR_TC_Pos)                /*!< 0x00000040 */\n#define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */\n#define USART_SR_TXE_Pos              (7U)\n#define USART_SR_TXE_Msk              (0x1UL << USART_SR_TXE_Pos)               /*!< 0x00000080 */\n#define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */\n#define USART_SR_LBD_Pos              (8U)\n#define USART_SR_LBD_Msk              (0x1UL << USART_SR_LBD_Pos)               /*!< 0x00000100 */\n#define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */\n#define USART_SR_CTS_Pos              (9U)\n#define USART_SR_CTS_Msk              (0x1UL << USART_SR_CTS_Pos)               /*!< 0x00000200 */\n#define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */\n\n/*******************  Bit definition for USART_DR register  *******************/\n#define USART_DR_DR_Pos               (0U)\n#define USART_DR_DR_Msk               (0x1FFUL << USART_DR_DR_Pos)              /*!< 0x000001FF */\n#define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */\n\n/******************  Bit definition for USART_BRR register  *******************/\n#define USART_BRR_DIV_Fraction_Pos    (0U)\n#define USART_BRR_DIV_Fraction_Msk    (0xFUL << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */\n#define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */\n#define USART_BRR_DIV_Mantissa_Pos    (4U)\n#define USART_BRR_DIV_Mantissa_Msk    (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */\n#define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */\n\n/******************  Bit definition for USART_CR1 register  *******************/\n#define USART_CR1_SBK_Pos             (0U)\n#define USART_CR1_SBK_Msk             (0x1UL << USART_CR1_SBK_Pos)              /*!< 0x00000001 */\n#define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */\n#define USART_CR1_RWU_Pos             (1U)\n#define USART_CR1_RWU_Msk             (0x1UL << USART_CR1_RWU_Pos)              /*!< 0x00000002 */\n#define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */\n#define USART_CR1_RE_Pos              (2U)\n#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */\n#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */\n#define USART_CR1_TE_Pos              (3U)\n#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */\n#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */\n#define USART_CR1_IDLEIE_Pos          (4U)\n#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */\n#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */\n#define USART_CR1_RXNEIE_Pos          (5U)\n#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */\n#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */\n#define USART_CR1_TCIE_Pos            (6U)\n#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */\n#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */\n#define USART_CR1_TXEIE_Pos           (7U)\n#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */\n#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<TXE Interrupt Enable                   */\n#define USART_CR1_PEIE_Pos            (8U)\n#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */\n#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */\n#define USART_CR1_PS_Pos              (9U)\n#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */\n#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */\n#define USART_CR1_PCE_Pos             (10U)\n#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */\n#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */\n#define USART_CR1_WAKE_Pos            (11U)\n#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */\n#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */\n#define USART_CR1_M_Pos               (12U)\n#define USART_CR1_M_Msk               (0x1UL << USART_CR1_M_Pos)                /*!< 0x00001000 */\n#define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */\n#define USART_CR1_UE_Pos              (13U)\n#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00002000 */\n#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */\n#define USART_CR1_OVER8_Pos           (15U)\n#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */\n#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */\n\n/******************  Bit definition for USART_CR2 register  *******************/\n#define USART_CR2_ADD_Pos             (0U)\n#define USART_CR2_ADD_Msk             (0xFUL << USART_CR2_ADD_Pos)              /*!< 0x0000000F */\n#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */\n#define USART_CR2_LBDL_Pos            (5U)\n#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */\n#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */\n#define USART_CR2_LBDIE_Pos           (6U)\n#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */\n#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */\n#define USART_CR2_LBCL_Pos            (8U)\n#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */\n#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */\n#define USART_CR2_CPHA_Pos            (9U)\n#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */\n#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */\n#define USART_CR2_CPOL_Pos            (10U)\n#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */\n#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */\n#define USART_CR2_CLKEN_Pos           (11U)\n#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */\n#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */\n\n#define USART_CR2_STOP_Pos            (12U)\n#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */\n#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */\n#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x1000 */\n#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x2000 */\n\n#define USART_CR2_LINEN_Pos           (14U)\n#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */\n#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */\n\n/******************  Bit definition for USART_CR3 register  *******************/\n#define USART_CR3_EIE_Pos             (0U)\n#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */\n#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */\n#define USART_CR3_IREN_Pos            (1U)\n#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */\n#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */\n#define USART_CR3_IRLP_Pos            (2U)\n#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */\n#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */\n#define USART_CR3_HDSEL_Pos           (3U)\n#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */\n#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */\n#define USART_CR3_NACK_Pos            (4U)\n#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */\n#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */\n#define USART_CR3_SCEN_Pos            (5U)\n#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */\n#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */\n#define USART_CR3_DMAR_Pos            (6U)\n#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */\n#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */\n#define USART_CR3_DMAT_Pos            (7U)\n#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */\n#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */\n#define USART_CR3_RTSE_Pos            (8U)\n#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */\n#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */\n#define USART_CR3_CTSE_Pos            (9U)\n#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */\n#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */\n#define USART_CR3_CTSIE_Pos           (10U)\n#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */\n#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */\n#define USART_CR3_ONEBIT_Pos          (11U)\n#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */\n#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */\n\n/******************  Bit definition for USART_GTPR register  ******************/\n#define USART_GTPR_PSC_Pos            (0U)\n#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */\n#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */\n#define USART_GTPR_PSC_0              (0x01UL << USART_GTPR_PSC_Pos)            /*!< 0x0001 */\n#define USART_GTPR_PSC_1              (0x02UL << USART_GTPR_PSC_Pos)            /*!< 0x0002 */\n#define USART_GTPR_PSC_2              (0x04UL << USART_GTPR_PSC_Pos)            /*!< 0x0004 */\n#define USART_GTPR_PSC_3              (0x08UL << USART_GTPR_PSC_Pos)            /*!< 0x0008 */\n#define USART_GTPR_PSC_4              (0x10UL << USART_GTPR_PSC_Pos)            /*!< 0x0010 */\n#define USART_GTPR_PSC_5              (0x20UL << USART_GTPR_PSC_Pos)            /*!< 0x0020 */\n#define USART_GTPR_PSC_6              (0x40UL << USART_GTPR_PSC_Pos)            /*!< 0x0040 */\n#define USART_GTPR_PSC_7              (0x80UL << USART_GTPR_PSC_Pos)            /*!< 0x0080 */\n\n#define USART_GTPR_GT_Pos             (8U)\n#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */\n#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            Window WATCHDOG                                 */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for WWDG_CR register  ********************/\n#define WWDG_CR_T_Pos           (0U)\n#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */\n#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\n#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x01 */\n#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x02 */\n#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x04 */\n#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x08 */\n#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x10 */\n#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x20 */\n#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x40 */\n/* Legacy defines */\n#define  WWDG_CR_T0                          WWDG_CR_T_0\n#define  WWDG_CR_T1                          WWDG_CR_T_1\n#define  WWDG_CR_T2                          WWDG_CR_T_2\n#define  WWDG_CR_T3                          WWDG_CR_T_3\n#define  WWDG_CR_T4                          WWDG_CR_T_4\n#define  WWDG_CR_T5                          WWDG_CR_T_5\n#define  WWDG_CR_T6                          WWDG_CR_T_6\n\n#define WWDG_CR_WDGA_Pos        (7U)\n#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */\n#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */\n\n/*******************  Bit definition for WWDG_CFR register  *******************/\n#define WWDG_CFR_W_Pos          (0U)\n#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */\n#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */\n#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x0001 */\n#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x0002 */\n#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x0004 */\n#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x0008 */\n#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x0010 */\n#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x0020 */\n#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x0040 */\n/* Legacy defines */\n#define  WWDG_CFR_W0                         WWDG_CFR_W_0\n#define  WWDG_CFR_W1                         WWDG_CFR_W_1\n#define  WWDG_CFR_W2                         WWDG_CFR_W_2\n#define  WWDG_CFR_W3                         WWDG_CFR_W_3\n#define  WWDG_CFR_W4                         WWDG_CFR_W_4\n#define  WWDG_CFR_W5                         WWDG_CFR_W_5\n#define  WWDG_CFR_W6                         WWDG_CFR_W_6\n\n#define WWDG_CFR_WDGTB_Pos      (7U)\n#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */\n#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */\n#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */\n#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */\n/* Legacy defines */\n#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0\n#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1\n\n#define WWDG_CFR_EWI_Pos        (9U)\n#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */\n#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */\n\n/*******************  Bit definition for WWDG_SR register  ********************/\n#define WWDG_SR_EWIF_Pos        (0U)\n#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */\n#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                DBG                                         */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for DBGMCU_IDCODE register  *************/\n#define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)\n#define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\n#define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk\n#define DBGMCU_IDCODE_REV_ID_Pos                     (16U)\n#define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\n#define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk\n\n/********************  Bit definition for DBGMCU_CR register  *****************/\n#define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)\n#define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */\n#define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk\n#define DBGMCU_CR_DBG_STOP_Pos                       (1U)\n#define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk\n#define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)\n#define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */\n#define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk\n#define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)\n#define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */\n#define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk\n\n#define DBGMCU_CR_TRACE_MODE_Pos                     (6U)\n#define DBGMCU_CR_TRACE_MODE_Msk                     (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */\n#define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk\n#define DBGMCU_CR_TRACE_MODE_0                       (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */\n#define DBGMCU_CR_TRACE_MODE_1                       (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */\n\n/********************  Bit definition for DBGMCU_APB1_FZ register  ************/\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk\n/* Old IWDGSTOP bit definition, maintained for legacy purpose */\n#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP\n\n/********************  Bit definition for DBGMCU_APB2_FZ register  ************/\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                                       USB_OTG                              */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/\n#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)\n#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */\n#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)\n#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\n#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */\n#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)\n#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)\n#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */\n#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)\n#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)\n#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */\n#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */\n#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)\n#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */\n#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */\n#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)\n#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */\n#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)\n#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */\n#define USB_OTG_GOTGCTL_BSVLD_Pos                (19U)\n#define USB_OTG_GOTGCTL_BSVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGCTL_BSVLD                    USB_OTG_GOTGCTL_BSVLD_Msk     /*!< B-session valid */\n\n/********************  Bit definition forUSB_OTG_HCFG register  ********************/\n\n#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)\n#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\n#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */\n#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCFG_FSLSS_Pos                   (2U)\n#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */\n\n/********************  Bit definition for USB_OTG_DCFG register  ********************/\n\n#define USB_OTG_DCFG_DSPD_Pos                    (0U)\n#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\n#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */\n#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)\n#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */\n\n#define USB_OTG_DCFG_DAD_Pos                     (4U)\n#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\n#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */\n#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\n\n#define USB_OTG_DCFG_PFIVL_Pos                   (11U)\n#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\n#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */\n#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\n\n#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)\n#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */\n#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk        /*!< Transceiver delay */\n\n#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)\n#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */\n#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk        /*!< Erratic error interrupt mask */\n\n#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)\n#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\n#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */\n#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\n#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\n\n/********************  Bit definition for USB_OTG_PCGCR register  ********************/\n#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)\n#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */\n#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)\n#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */\n#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)\n#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */\n\n/********************  Bit definition for USB_OTG_GOTGINT register  ********************/\n#define USB_OTG_GOTGINT_SEDET_Pos                (2U)\n#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */\n#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)\n#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */\n#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)\n#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */\n#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)\n#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */\n#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)\n#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */\n#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)\n#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */\n\n/********************  Bit definition for USB_OTG_DCTL register  ********************/\n#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)\n#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */\n#define USB_OTG_DCTL_SDIS_Pos                    (1U)\n#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */\n#define USB_OTG_DCTL_GINSTS_Pos                  (2U)\n#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */\n#define USB_OTG_DCTL_GONSTS_Pos                  (3U)\n#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\n#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */\n\n#define USB_OTG_DCTL_TCTL_Pos                    (4U)\n#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\n#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */\n#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCTL_SGINAK_Pos                  (7U)\n#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */\n#define USB_OTG_DCTL_CGINAK_Pos                  (8U)\n#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */\n#define USB_OTG_DCTL_SGONAK_Pos                  (9U)\n#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */\n#define USB_OTG_DCTL_CGONAK_Pos                  (10U)\n#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\n#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */\n#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)\n#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */\n\n/********************  Bit definition for USB_OTG_HFIR register  ********************/\n#define USB_OTG_HFIR_FRIVL_Pos                   (0U)\n#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */\n\n/********************  Bit definition for USB_OTG_HFNUM register  ********************/\n#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)\n#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */\n#define USB_OTG_HFNUM_FTREM_Pos                  (16U)\n#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */\n\n/********************  Bit definition for USB_OTG_DSTS register  ********************/\n#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)\n#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */\n\n#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)\n#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\n#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */\n#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\n#define USB_OTG_DSTS_EERR_Pos                    (3U)\n#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\n#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */\n#define USB_OTG_DSTS_FNSOF_Pos                   (8U)\n#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\n#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */\n\n/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/\n#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)\n#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\n#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */\n#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)\n#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\n#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */\n#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */\n#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */\n#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */\n#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */\n#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */\n#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)\n#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */\n#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)\n#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */\n#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)\n#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\n#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */\n\n/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/\n\n#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)\n#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\n#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */\n#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\n#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\n#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\n#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)\n#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\n#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\n#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)\n#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\n#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */\n#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)\n#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\n#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */\n#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)\n#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\n#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */\n#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\n#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\n#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\n#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\n#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)\n#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */\n#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)\n#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\n#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */\n#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)\n#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\n#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */\n#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)\n#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\n#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */\n#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)\n#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\n#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */\n#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)\n#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\n#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */\n#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)\n#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\n#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */\n#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)\n#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\n#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */\n#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)\n#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\n#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */\n#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)\n#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\n#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */\n#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)\n#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */\n\n/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/\n#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)\n#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\n#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */\n#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)\n#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\n#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */\n#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)\n#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\n#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */\n#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)\n#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\n#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */\n#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)\n#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\n#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */\n\n\n#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)\n#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\n#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */\n#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\n#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\n#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)\n#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\n#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */\n#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)\n#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\n#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */\n\n/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/\n#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)\n#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)\n#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)\n#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)\n#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)\n#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/\n#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)\n#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */\n#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)\n#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */\n#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)\n#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */\n#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\n\n/********************  Bit definition for USB_OTG_HAINT register  ********************/\n#define USB_OTG_HAINT_HAINT_Pos                  (0U)\n#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */\n\n/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/\n#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask              */\n#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */\n#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)\n#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */\n#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */\n#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)\n#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */\n#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)\n#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */\n#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)\n#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */\n#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */\n#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)\n#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */\n#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)\n#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */\n#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)\n#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */\n#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)\n#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */\n#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)\n#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */\n/********************  Bit definition for USB_OTG_GINTSTS register  ********************/\n#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)\n#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\n#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */\n#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)\n#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */\n#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)\n#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */\n#define USB_OTG_GINTSTS_SOF_Pos                  (3U)\n#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */\n#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)\n#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */\n#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)\n#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */\n#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)\n#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */\n#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)\n#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */\n#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)\n#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */\n#define USB_OTG_GINTSTS_USBRST_Pos               (12U)\n#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */\n#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)\n#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */\n#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)\n#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */\n#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)\n#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */\n#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)\n#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */\n#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)\n#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */\n#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)\n#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */\n#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)\n#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */\n#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)\n#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */\n#define USB_OTG_GINTSTS_HCINT_Pos                (25U)\n#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */\n#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)\n#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */\n#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)\n#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */\n#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)\n#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */\n#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)\n#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */\n#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)\n#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */\n\n/********************  Bit definition for USB_OTG_GINTMSK register  ********************/\n#define USB_OTG_GINTMSK_MMISM_Pos                (1U)\n#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */\n#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)\n#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */\n#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)\n#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */\n#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)\n#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */\n#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)\n#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */\n#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)\n#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */\n#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)\n#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */\n#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)\n#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */\n#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)\n#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */\n#define USB_OTG_GINTMSK_USBRST_Pos               (12U)\n#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */\n#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)\n#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */\n#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)\n#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */\n#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)\n#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */\n#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)\n#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\n#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */\n#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)\n#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */\n#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)\n#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */\n#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)\n#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */\n#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)\n#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */\n#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)\n#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */\n#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)\n#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */\n#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)\n#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */\n#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)\n#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */\n#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)\n#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */\n#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)\n#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */\n#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)\n#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */\n\n/********************  Bit definition for USB_OTG_DAINT register  ********************/\n#define USB_OTG_DAINT_IEPINT_Pos                 (0U)\n#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */\n#define USB_OTG_DAINT_OEPINT_Pos                 (16U)\n#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */\n\n/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/\n#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)\n#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */\n\n/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/\n#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)\n#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\n#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */\n#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)\n#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\n#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)\n#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\n#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)\n#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/\n#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)\n#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */\n#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)\n#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/\n#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)\n#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/\n#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)\n#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */\n\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_NPTXFSA_Pos                      (0U)\n#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */\n#define USB_OTG_NPTXFD_Pos                       (16U)\n#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */\n#define USB_OTG_TX0FSA_Pos                       (0U)\n#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */\n#define USB_OTG_TX0FD_Pos                        (16U)\n#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */\n\n/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/\n#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)\n#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\n#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\n\n/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\n\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/\n#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)\n#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\n#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\n#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)\n#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\n#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */\n\n#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)\n#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\n#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */\n#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)\n#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\n#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */\n\n#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)\n#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */\n#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\n#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)\n#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\n#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */\n\n/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DEACHINT register  ********************/\n#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)\n#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */\n#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)\n#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */\n\n/********************  Bit definition for USB_OTG_GCCFG register  ********************/\n#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)\n#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\n#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */\n#define USB_OTG_GCCFG_I2CPADEN_Pos               (17U)\n#define USB_OTG_GCCFG_I2CPADEN_Msk               (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_GCCFG_I2CPADEN                   USB_OTG_GCCFG_I2CPADEN_Msk    /*!< Enable I2C bus connection for the external I2C PHY interface*/\n#define USB_OTG_GCCFG_VBUSASEN_Pos               (18U)\n#define USB_OTG_GCCFG_VBUSASEN_Msk               (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_GCCFG_VBUSASEN                   USB_OTG_GCCFG_VBUSASEN_Msk    /*!< Enable the VBUS sensing device */\n#define USB_OTG_GCCFG_VBUSBSEN_Pos               (19U)\n#define USB_OTG_GCCFG_VBUSBSEN_Msk               (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_GCCFG_VBUSBSEN                   USB_OTG_GCCFG_VBUSBSEN_Msk    /*!< Enable the VBUS sensing device */\n#define USB_OTG_GCCFG_SOFOUTEN_Pos               (20U)\n#define USB_OTG_GCCFG_SOFOUTEN_Msk               (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_GCCFG_SOFOUTEN                   USB_OTG_GCCFG_SOFOUTEN_Msk    /*!< SOF output enable */\n#define USB_OTG_GCCFG_NOVBUSSENS_Pos             (21U)\n#define USB_OTG_GCCFG_NOVBUSSENS_Msk             (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */\n#define USB_OTG_GCCFG_NOVBUSSENS                 USB_OTG_GCCFG_NOVBUSSENS_Msk  /*!< VBUS sensing disable option*/\n\n/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\n\n/********************  Bit definition for USB_OTG_CID register  ********************/\n#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)\n#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */\n\n/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */\n#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPRT register  ********************/\n#define USB_OTG_HPRT_PCSTS_Pos                   (0U)\n#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */\n#define USB_OTG_HPRT_PCDET_Pos                   (1U)\n#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\n#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */\n#define USB_OTG_HPRT_PENA_Pos                    (2U)\n#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\n#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */\n#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)\n#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\n#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */\n#define USB_OTG_HPRT_POCA_Pos                    (4U)\n#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\n#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */\n#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)\n#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\n#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */\n#define USB_OTG_HPRT_PRES_Pos                    (6U)\n#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\n#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */\n#define USB_OTG_HPRT_PSUSP_Pos                   (7U)\n#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\n#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */\n#define USB_OTG_HPRT_PRST_Pos                    (8U)\n#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\n#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */\n\n#define USB_OTG_HPRT_PLSTS_Pos                   (10U)\n#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\n#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */\n#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\n#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_HPRT_PPWR_Pos                    (12U)\n#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */\n\n#define USB_OTG_HPRT_PTCTL_Pos                   (13U)\n#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\n#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */\n#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\n#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\n#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\n#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\n\n#define USB_OTG_HPRT_PSPD_Pos                    (17U)\n#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\n#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */\n#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\n\n/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */\n#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */\n#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */\n#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)\n#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */\n#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)\n#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */\n\n/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/\n#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)\n#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */\n#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)\n#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */\n\n/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/\n#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */\n#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */\n#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)\n#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\n#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */\n#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */\n\n#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */\n#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DIEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */\n\n#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)\n#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\n#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */\n#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\n#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\n#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\n#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\n#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */\n#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */\n#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */\n#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */\n#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */\n\n/********************  Bit definition for USB_OTG_HCCHAR register  ********************/\n#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)\n#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */\n\n#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)\n#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\n#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */\n#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\n#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)\n#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */\n#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)\n#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */\n\n#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)\n#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */\n#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\n\n#define USB_OTG_HCCHAR_MC_Pos                    (20U)\n#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\n#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */\n#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\n#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\n\n#define USB_OTG_HCCHAR_DAD_Pos                   (22U)\n#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\n#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */\n#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\n#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\n#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\n#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\n#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\n#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\n#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\n#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)\n#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */\n#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)\n#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */\n#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)\n#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */\n\n/********************  Bit definition for USB_OTG_HCSPLT register  ********************/\n\n#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)\n#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\n#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */\n#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\n\n#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)\n#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\n#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */\n#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\n\n#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)\n#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\n#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */\n#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)\n#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\n#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */\n#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)\n#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */\n\n/********************  Bit definition for USB_OTG_HCINT register  ********************/\n#define USB_OTG_HCINT_XFRC_Pos                   (0U)\n#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */\n#define USB_OTG_HCINT_CHH_Pos                    (1U)\n#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */\n#define USB_OTG_HCINT_AHBERR_Pos                 (2U)\n#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */\n#define USB_OTG_HCINT_STALL_Pos                  (3U)\n#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */\n#define USB_OTG_HCINT_NAK_Pos                    (4U)\n#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */\n#define USB_OTG_HCINT_ACK_Pos                    (5U)\n#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */\n#define USB_OTG_HCINT_NYET_Pos                   (6U)\n#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */\n#define USB_OTG_HCINT_TXERR_Pos                  (7U)\n#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */\n#define USB_OTG_HCINT_BBERR_Pos                  (8U)\n#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */\n#define USB_OTG_HCINT_FRMOR_Pos                  (9U)\n#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */\n#define USB_OTG_HCINT_DTERR_Pos                  (10U)\n#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */\n\n/********************  Bit definition for USB_OTG_DIEPINT register  ********************/\n#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)\n#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */\n#define USB_OTG_DIEPINT_TOC_Pos                  (3U)\n#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */\n#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)\n#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */\n#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)\n#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */\n#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */\n#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)\n#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */\n#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)\n#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\n#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\n#define USB_OTG_DIEPINT_BNA_Pos                  (9U)\n#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */\n#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)\n#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\n#define USB_OTG_DIEPINT_BERR_Pos                 (12U)\n#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\n#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */\n#define USB_OTG_DIEPINT_NAK_Pos                  (13U)\n#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */\n\n/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/\n#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)\n#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */\n#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)\n#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */\n#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)\n#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */\n#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)\n#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */\n#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)\n#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */\n#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)\n#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */\n#define USB_OTG_HCINTMSK_NYET_Pos                (6U)\n#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */\n#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)\n#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */\n#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)\n#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */\n#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)\n#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */\n#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)\n#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */\n\n/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/\n\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)\n#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */\n/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/\n#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)\n#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */\n#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)\n#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */\n#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)\n#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */\n#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)\n#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\n#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */\n#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/\n#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)\n#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_HCDMA register  ********************/\n#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)\n#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/\n#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)\n#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */\n\n/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/\n#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)\n#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */\n#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)\n#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/\n\n#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */\n#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */\n#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\n#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */\n#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */\n#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)\n#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\n#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */\n#define USB_OTG_DOEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */\n#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */\n#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */\n#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */\n\n/********************  Bit definition for USB_OTG_DOEPINT register  ********************/\n#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)\n#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */\n#define USB_OTG_DOEPINT_STUP_Pos                 (3U)\n#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */\n#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)\n#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */\n#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)\n#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */\n#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */\n#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)\n#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */\n#define USB_OTG_DOEPINT_NAK_Pos                  (13U)\n#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */\n#define USB_OTG_DOEPINT_NYET_Pos                 (14U)\n#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */\n#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)\n#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */\n/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/\n\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n\n#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)\n#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */\n#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for PCGCCTL register  ********************/\n#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)\n#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */\n#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)\n#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */\n#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)\n#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */\n\n/* Legacy define */\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_CHNUM_Pos                        (0U)\n#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\n#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\n#define USB_OTG_BCNT_Pos                         (4U)\n#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\n\n#define USB_OTG_DPID_Pos                         (15U)\n#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)    /*!< 0x00018000 */\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\n#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\n#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\n\n#define USB_OTG_PKTSTS_Pos                       (17U)\n#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\n#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\n#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\n#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\n#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\n\n#define USB_OTG_EPNUM_Pos                        (0U)\n#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\n#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\n\n#define USB_OTG_FRMNUM_Pos                       (21U)\n#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\n#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\n#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\n#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\n#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_macros\n  * @{\n  */\n\n/******************************* ADC Instances ********************************/\n#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \\\n                                       ((INSTANCE) == ADC2) || \\\n                                       ((INSTANCE) == ADC3))\n\n#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\n\n#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)\n\n/******************************* CAN Instances ********************************/\n#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \\\n                                       ((INSTANCE) == CAN2))\n/******************************* CRC Instances ********************************/\n#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\n\n/******************************* DAC Instances ********************************/\n#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)\n\n\n/******************************** DMA Instances *******************************/\n#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \\\n                                              ((INSTANCE) == DMA1_Stream1) || \\\n                                              ((INSTANCE) == DMA1_Stream2) || \\\n                                              ((INSTANCE) == DMA1_Stream3) || \\\n                                              ((INSTANCE) == DMA1_Stream4) || \\\n                                              ((INSTANCE) == DMA1_Stream5) || \\\n                                              ((INSTANCE) == DMA1_Stream6) || \\\n                                              ((INSTANCE) == DMA1_Stream7) || \\\n                                              ((INSTANCE) == DMA2_Stream0) || \\\n                                              ((INSTANCE) == DMA2_Stream1) || \\\n                                              ((INSTANCE) == DMA2_Stream2) || \\\n                                              ((INSTANCE) == DMA2_Stream3) || \\\n                                              ((INSTANCE) == DMA2_Stream4) || \\\n                                              ((INSTANCE) == DMA2_Stream5) || \\\n                                              ((INSTANCE) == DMA2_Stream6) || \\\n                                              ((INSTANCE) == DMA2_Stream7))\n\n/******************************* GPIO Instances *******************************/\n#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\\n                                        ((INSTANCE) == GPIOB) || \\\n                                        ((INSTANCE) == GPIOC) || \\\n                                        ((INSTANCE) == GPIOD) || \\\n                                        ((INSTANCE) == GPIOE) || \\\n                                        ((INSTANCE) == GPIOF) || \\\n                                        ((INSTANCE) == GPIOG) || \\\n                                        ((INSTANCE) == GPIOH) || \\\n                                        ((INSTANCE) == GPIOI))\n\n/******************************** I2C Instances *******************************/\n#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\n                                       ((INSTANCE) == I2C2) || \\\n                                       ((INSTANCE) == I2C3))\n\n/******************************* SMBUS Instances ******************************/\n#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE\n\n/******************************** I2S Instances *******************************/\n\n#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \\\n                                       ((INSTANCE) == SPI3))\n\n/*************************** I2S Extended Instances ***************************/\n#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \\\n                                           ((INSTANCE) == I2S3ext))\n/* Legacy Defines */\n#define IS_I2S_ALL_INSTANCE_EXT    IS_I2S_EXT_ALL_INSTANCE\n\n/******************************* RNG Instances ********************************/\n#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)\n\n/****************************** RTC Instances *********************************/\n#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\n\n\n/******************************** SPI Instances *******************************/\n#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\\n                                       ((INSTANCE) == SPI2) || \\\n                                       ((INSTANCE) == SPI3))\n\n\n/****************** TIM Instances : All supported instances *******************/\n#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                    ((INSTANCE) == TIM2) || \\\n                                    ((INSTANCE) == TIM3) || \\\n                                    ((INSTANCE) == TIM4) || \\\n                                    ((INSTANCE) == TIM5) || \\\n                                    ((INSTANCE) == TIM6) || \\\n                                    ((INSTANCE) == TIM7) || \\\n                                    ((INSTANCE) == TIM8) || \\\n                                    ((INSTANCE) == TIM9) || \\\n                                    ((INSTANCE) == TIM10)|| \\\n                                    ((INSTANCE) == TIM11)|| \\\n                                    ((INSTANCE) == TIM12)|| \\\n                                    ((INSTANCE) == TIM13)|| \\\n                                    ((INSTANCE) == TIM14))\n\n/************* TIM Instances : at least 1 capture/compare channel *************/\n#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \\\n                                         ((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM3)  || \\\n                                         ((INSTANCE) == TIM4)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM8)  || \\\n                                         ((INSTANCE) == TIM9)  || \\\n                                         ((INSTANCE) == TIM10) || \\\n                                         ((INSTANCE) == TIM11) || \\\n                                         ((INSTANCE) == TIM12) || \\\n                                         ((INSTANCE) == TIM13) || \\\n                                         ((INSTANCE) == TIM14))\n\n/************ TIM Instances : at least 2 capture/compare channels *************/\n#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8) || \\\n                                       ((INSTANCE) == TIM9) || \\\n                                       ((INSTANCE) == TIM12))\n\n/************ TIM Instances : at least 3 capture/compare channels *************/\n#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/************ TIM Instances : at least 4 capture/compare channels *************/\n#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : Advanced-control timers *****************/\n#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                           ((INSTANCE) == TIM8))\n\n/******************* TIM Instances : Timer input XOR function *****************/\n#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : DMA requests generation (UDE) *************/\n#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM6) || \\\n                                       ((INSTANCE) == TIM7) || \\\n                                       ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (CCxDE) *****************/\n#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (COMDE) *****************/\n#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : DMA burst feature ***********************/\n#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                             ((INSTANCE) == TIM2) || \\\n                                             ((INSTANCE) == TIM3) || \\\n                                             ((INSTANCE) == TIM4) || \\\n                                             ((INSTANCE) == TIM5) || \\\n                                             ((INSTANCE) == TIM8))\n\n/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\n#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                          ((INSTANCE) == TIM2)  || \\\n                                          ((INSTANCE) == TIM3)  || \\\n                                          ((INSTANCE) == TIM4)  || \\\n                                          ((INSTANCE) == TIM5)  || \\\n                                          ((INSTANCE) == TIM6)  || \\\n                                          ((INSTANCE) == TIM7)  || \\\n                                          ((INSTANCE) == TIM8))\n\n/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\n#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8) || \\\n                                         ((INSTANCE) == TIM9) || \\\n                                         ((INSTANCE) == TIM12))\n/********************** TIM Instances : 32 bit Counter ************************/\n#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \\\n                                              ((INSTANCE) == TIM5))\n\n/***************** TIM Instances : external trigger input availabe ************/\n#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                        ((INSTANCE) == TIM2) || \\\n                                        ((INSTANCE) == TIM3) || \\\n                                        ((INSTANCE) == TIM4) || \\\n                                        ((INSTANCE) == TIM5) || \\\n                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : remapping capability **********************/\n#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM11))\n\n/******************* TIM Instances : output(s) available **********************/\n#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\\n    ((((INSTANCE) == TIM1) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM2) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM3) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM4) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM5) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM8) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM9) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM10) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM11) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM12) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM13) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM14) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1))))\n\n/************ TIM Instances : complementary output(s) available ***************/\n#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\\n   ((((INSTANCE) == TIM1) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3)))            \\\n    ||                                          \\\n    (((INSTANCE) == TIM8) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3))))\n\n/****************** TIM Instances : supporting counting mode selection ********/\n#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting clock division *****************/\n#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                                  ((INSTANCE) == TIM2) || \\\n                                                  ((INSTANCE) == TIM3) || \\\n                                                  ((INSTANCE) == TIM4) || \\\n                                                  ((INSTANCE) == TIM5) || \\\n                                                  ((INSTANCE) == TIM8) || \\\n                                                  ((INSTANCE) == TIM9) || \\\n                                                  ((INSTANCE) == TIM10)|| \\\n                                                  ((INSTANCE) == TIM11)|| \\\n                                                  ((INSTANCE) == TIM12)|| \\\n                                                  ((INSTANCE) == TIM13)|| \\\n                                                  ((INSTANCE) == TIM14))\n\n/****************** TIM Instances : supporting commutation event generation ***/\n#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \\\n                                                     ((INSTANCE) == TIM8))\n\n\n/****************** TIM Instances : supporting OCxREF clear *******************/\n#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM2) || \\\n                                                       ((INSTANCE) == TIM3) || \\\n                                                       ((INSTANCE) == TIM4) || \\\n                                                       ((INSTANCE) == TIM5) || \\\n                                                       ((INSTANCE) == TIM8))\n\n/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8))\n\n/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/\n#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/********** TIM Instances : supporting internal trigger inputs(ITRX) *********/\n#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/****************** TIM Instances : supporting repetition counter *************/\n#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting encoder interface **************/\n#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                      ((INSTANCE) == TIM2) || \\\n                                                      ((INSTANCE) == TIM3) || \\\n                                                      ((INSTANCE) == TIM4) || \\\n                                                      ((INSTANCE) == TIM5) || \\\n                                                      ((INSTANCE) == TIM8) || \\\n                                                      ((INSTANCE) == TIM9) || \\\n                                                      ((INSTANCE) == TIM12))\n/****************** TIM Instances : supporting Hall sensor interface **********/\n#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                          ((INSTANCE) == TIM2) || \\\n                                                          ((INSTANCE) == TIM3) || \\\n                                                          ((INSTANCE) == TIM4) || \\\n                                                          ((INSTANCE) == TIM5) || \\\n                                                          ((INSTANCE) == TIM8))\n/****************** TIM Instances : supporting the break function *************/\n#define IS_TIM_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM8))\n\n/******************** USART Instances : Synchronous mode **********************/\n#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                     ((INSTANCE) == USART2) || \\\n                                     ((INSTANCE) == USART3) || \\\n                                     ((INSTANCE) == USART6))\n\n/******************** UART Instances : Half-Duplex mode **********************/\n#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                               ((INSTANCE) == USART2) || \\\n                                               ((INSTANCE) == USART3) || \\\n                                               ((INSTANCE) == UART4)  || \\\n                                               ((INSTANCE) == UART5)  || \\\n                                               ((INSTANCE) == USART6))\n\n/* Legacy defines */\n#define IS_UART_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE\n\n/****************** UART Instances : Hardware Flow control ********************/\n#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                           ((INSTANCE) == USART2) || \\\n                                           ((INSTANCE) == USART3) || \\\n                                           ((INSTANCE) == USART6))\n/******************** UART Instances : LIN mode **********************/\n#define IS_UART_LIN_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE\n\n/********************* UART Instances : Smart card mode ***********************/\n#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                         ((INSTANCE) == USART2) || \\\n                                         ((INSTANCE) == USART3) || \\\n                                         ((INSTANCE) == USART6))\n\n/*********************** UART Instances : IRDA mode ***************************/\n#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2) || \\\n                                    ((INSTANCE) == USART3) || \\\n                                    ((INSTANCE) == UART4)  || \\\n                                    ((INSTANCE) == UART5)  || \\\n                                    ((INSTANCE) == USART6))\n\n\n/*********************** PCD Instances ****************************************/\n#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\\n                                       ((INSTANCE) == USB_OTG_HS))\n\n/*********************** HCD Instances ****************************************/\n#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\\n                                       ((INSTANCE) == USB_OTG_HS))\n\n/****************************** SDIO Instances ********************************/\n#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)\n\n/****************************** IWDG Instances ********************************/\n#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)\n\n/****************************** WWDG Instances ********************************/\n#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)\n\n/****************************** USB Exported Constants ************************/\n#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U\n#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */\n#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */\n#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */\n\n/*\n * @brief Specific devices reset values definitions\n */\n#define RCC_PLLCFGR_RST_VALUE              0x24003010U\n#define RCC_PLLI2SCFGR_RST_VALUE           0x20003000U\n\n#define RCC_MAX_FREQUENCY           168000000U         /*!< Max frequency of family in Hz*/\n#define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */\n#define RCC_MAX_FREQUENCY_SCALE2    144000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */\n#define RCC_PLLVCO_OUTPUT_MIN       100000000U       /*!< Frequency min for PLLVCO output, in Hz */\n#define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */\n\n#define RCC_PLLN_MIN_VALUE                 50U\n#define RCC_PLLN_MAX_VALUE                432U\n\n#define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */\n#define FLASH_SCALE1_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */\n#define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */\n#define FLASH_SCALE1_LATENCY4_FREQ   120000000U     /*!< HCLK frequency to set FLASH latency 4 in power scale 1  */\n#define FLASH_SCALE1_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */\n\n#define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */\n#define FLASH_SCALE2_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */\n#define FLASH_SCALE2_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */\n#define FLASH_SCALE2_LATENCY4_FREQ   12000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 2  */\n\n#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U\n#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */\n#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */\n#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */\n/******************************************************************************/\n/*  For a painless codes migration between the STM32F4xx device product       */\n/*  lines, the aliases defined below are put in place to overcome the         */\n/*  differences in the interrupt handlers and IRQn definitions.               */\n/*  No need to update developed interrupt code when moving across             */\n/*  product lines within the same STM32F4 Family                              */\n/******************************************************************************/\n/* Aliases for __IRQn */\n#define FMC_IRQn              FSMC_IRQn\n\n/* Aliases for __IRQHandler */\n#define FMC_IRQHandler        FSMC_IRQHandler\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32F405xx_H */\n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f407xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f407xx.h\n  * @author  MCD Application Team\n  * @version V2.6.1\n  * @date    14-February-2017\n  * @brief   CMSIS STM32F407xx Device Peripheral Access Layer Header File.\n  *\n  *          This file contains:\n  *           - Data structures and the address mapping for all peripherals\n  *           - peripherals registers declarations and bits definition\n  *           - Macros to access peripheral's registers hardware\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS_Device\n  * @{\n  */\n\n/** @addtogroup stm32f407xx\n  * @{\n  */\n\n#ifndef __STM32F407xx_H\n#define __STM32F407xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Configuration_section_for_CMSIS\n  * @{\n  */\n\n/**\n  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals\n  */\n#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */\n#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */\n#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */\n#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */\n#define __FPU_PRESENT             1U       /*!< FPU present                                   */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_interrupt_number_definition\n  * @{\n  */\n\n/**\n * @brief STM32F4XX Interrupt Number Definition, according to the selected device\n *        in @ref Library_configuration_section\n */\ntypedef enum\n{\n/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */\n  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */\n  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */\n  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */\n  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */\n  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */\n/******  STM32 specific Interrupt Numbers **********************************************************************/\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */\n  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */\n  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\n  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\n  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\n  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\n  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\n  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\n  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\n  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\n  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\n  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */\n  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */\n  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */\n  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */\n  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */\n  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */\n  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */\n  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */\n  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */\n  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */\n  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */\n  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\n  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */\n  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */\n  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\n  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\n  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */\n  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */\n  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */\n  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\n  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */\n  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */\n  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */\n  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\n  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */\n  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */\n  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */\n  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */\n  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */\n  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */\n  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */\n  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */\n  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */\n  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */\n  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */\n  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */\n  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */\n  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */\n  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */\n  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */\n  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */\n  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */\n  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */\n  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */\n  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\n  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\n  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */\n  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */\n  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */\n  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */\n  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */\n  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */\n  FPU_IRQn                    = 81      /*!< FPU global interrupt                                               */\n} IRQn_Type;\n\n/**\n  * @}\n  */\n\n#include \"core_cm4.h\"             /* Cortex-M4 processor and core peripherals */\n#include \"system_stm32f4xx.h\"\n#include <sys/stdint.h>\n\n/** @addtogroup Peripheral_registers_structures\n  * @{\n  */\n\n/**\n  * @brief Analog to Digital Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */\n  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */\n  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */\n  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */\n  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */\n  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\n  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\n  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\n  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\n  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */\n  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */\n  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */\n  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */\n  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */\n  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/\n  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */\n  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */\n  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */\n  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */\n  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */\n} ADC_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */\n  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */\n  __IO uint32_t CDR;    /*!< ADC common regular data register for dual\n                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */\n} ADC_Common_TypeDef;\n\n\n/**\n  * @brief Controller Area Network TxMailBox\n  */\n\ntypedef struct\n{\n  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */\n  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\n  __IO uint32_t TDLR; /*!< CAN mailbox data low register */\n  __IO uint32_t TDHR; /*!< CAN mailbox data high register */\n} CAN_TxMailBox_TypeDef;\n\n/**\n  * @brief Controller Area Network FIFOMailBox\n  */\n\ntypedef struct\n{\n  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */\n  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\n  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\n  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\n} CAN_FIFOMailBox_TypeDef;\n\n/**\n  * @brief Controller Area Network FilterRegister\n  */\n\ntypedef struct\n{\n  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\n  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\n} CAN_FilterRegister_TypeDef;\n\n/**\n  * @brief Controller Area Network\n  */\n\ntypedef struct\n{\n  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */\n  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */\n  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */\n  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */\n  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */\n  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */\n  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */\n  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */\n  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */\n  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */\n  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */\n  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */\n  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */\n  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */\n  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */\n  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */\n  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */\n  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */\n  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */\n  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */\n  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */\n  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */\n} CAN_TypeDef;\n\n/**\n  * @brief CRC calculation unit\n  */\n\ntypedef struct\n{\n  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */\n  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */\n  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */\n  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */\n  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */\n} CRC_TypeDef;\n\n/**\n  * @brief Digital to Analog Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */\n  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */\n  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\n  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */\n  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */\n  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\n  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */\n  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */\n  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */\n  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */\n  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */\n  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */\n  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */\n  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */\n} DAC_TypeDef;\n\n/**\n  * @brief Debug MCU\n  */\n\ntypedef struct\n{\n  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */\n  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */\n  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */\n  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */\n}DBGMCU_TypeDef;\n\n/**\n  * @brief DCMI\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */\n  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */\n  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */\n  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */\n  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */\n  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */\n  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */\n  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */\n  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */\n  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */\n  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */\n} DCMI_TypeDef;\n\n/**\n  * @brief DMA Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;     /*!< DMA stream x configuration register      */\n  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */\n  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */\n  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */\n  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */\n  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */\n} DMA_Stream_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */\n  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */\n  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */\n  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\n} DMA_TypeDef;\n\n/**\n  * @brief Ethernet MAC\n  */\n\ntypedef struct\n{\n  __IO uint32_t MACCR;\n  __IO uint32_t MACFFR;\n  __IO uint32_t MACHTHR;\n  __IO uint32_t MACHTLR;\n  __IO uint32_t MACMIIAR;\n  __IO uint32_t MACMIIDR;\n  __IO uint32_t MACFCR;\n  __IO uint32_t MACVLANTR;             /*    8 */\n  uint32_t      RESERVED0[2];\n  __IO uint32_t MACRWUFFR;             /*   11 */\n  __IO uint32_t MACPMTCSR;\n  uint32_t      RESERVED1;\n  __IO uint32_t MACDBGR;\n  __IO uint32_t MACSR;                 /*   15 */\n  __IO uint32_t MACIMR;\n  __IO uint32_t MACA0HR;\n  __IO uint32_t MACA0LR;\n  __IO uint32_t MACA1HR;\n  __IO uint32_t MACA1LR;\n  __IO uint32_t MACA2HR;\n  __IO uint32_t MACA2LR;\n  __IO uint32_t MACA3HR;\n  __IO uint32_t MACA3LR;               /*   24 */\n  uint32_t      RESERVED2[40];\n  __IO uint32_t MMCCR;                 /*   65 */\n  __IO uint32_t MMCRIR;\n  __IO uint32_t MMCTIR;\n  __IO uint32_t MMCRIMR;\n  __IO uint32_t MMCTIMR;               /*   69 */\n  uint32_t      RESERVED3[14];\n  __IO uint32_t MMCTGFSCCR;            /*   84 */\n  __IO uint32_t MMCTGFMSCCR;\n  uint32_t      RESERVED4[5];\n  __IO uint32_t MMCTGFCR;\n  uint32_t      RESERVED5[10];\n  __IO uint32_t MMCRFCECR;\n  __IO uint32_t MMCRFAECR;\n  uint32_t      RESERVED6[10];\n  __IO uint32_t MMCRGUFCR;\n  uint32_t      RESERVED7[334];\n  __IO uint32_t PTPTSCR;\n  __IO uint32_t PTPSSIR;\n  __IO uint32_t PTPTSHR;\n  __IO uint32_t PTPTSLR;\n  __IO uint32_t PTPTSHUR;\n  __IO uint32_t PTPTSLUR;\n  __IO uint32_t PTPTSAR;\n  __IO uint32_t PTPTTHR;\n  __IO uint32_t PTPTTLR;\n  __IO uint32_t RESERVED8;\n  __IO uint32_t PTPTSSR;\n  uint32_t      RESERVED9[565];\n  __IO uint32_t DMABMR;\n  __IO uint32_t DMATPDR;\n  __IO uint32_t DMARPDR;\n  __IO uint32_t DMARDLAR;\n  __IO uint32_t DMATDLAR;\n  __IO uint32_t DMASR;\n  __IO uint32_t DMAOMR;\n  __IO uint32_t DMAIER;\n  __IO uint32_t DMAMFBOCR;\n  __IO uint32_t DMARSWTR;\n  uint32_t      RESERVED10[8];\n  __IO uint32_t DMACHTDR;\n  __IO uint32_t DMACHRDR;\n  __IO uint32_t DMACHTBAR;\n  __IO uint32_t DMACHRBAR;\n} ETH_TypeDef;\n\n/**\n  * @brief External Interrupt/Event Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */\n  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */\n  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */\n  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\n  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */\n  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */\n} EXTI_TypeDef;\n\n/**\n  * @brief FLASH Registers\n  */\n\ntypedef struct\n{\n  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */\n  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */\n  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */\n  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */\n  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */\n  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */\n  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */\n} FLASH_TypeDef;\n\n\n\n/**\n  * @brief Flexible Static Memory Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\n} FSMC_Bank1_TypeDef;\n\n/**\n  * @brief Flexible Static Memory Controller Bank1E\n  */\n\ntypedef struct\n{\n  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\n} FSMC_Bank1E_TypeDef;\n\n/**\n  * @brief Flexible Static Memory Controller Bank2\n  */\n\ntypedef struct\n{\n  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */\n  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */\n  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */\n  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */\n  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */\n  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */\n  uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */\n  uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */\n  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */\n  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */\n  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */\n  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */\n  uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */\n  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */\n} FSMC_Bank2_3_TypeDef;\n\n/**\n  * @brief Flexible Static Memory Controller Bank4\n  */\n\ntypedef struct\n{\n  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */\n  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */\n  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */\n  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */\n  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */\n} FSMC_Bank4_TypeDef;\n\n/**\n  * @brief General Purpose I/O\n  */\n\ntypedef struct\n{\n  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */\n  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */\n  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */\n  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\n  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */\n  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */\n  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */\n  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */\n  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\n} GPIO_TypeDef;\n\n/**\n  * @brief System configuration controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */\n  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */\n  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\n  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */\n  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */\n} SYSCFG_TypeDef;\n\n/**\n  * @brief Inter-integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */\n  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */\n  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */\n  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */\n  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */\n  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */\n  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */\n  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */\n} I2C_TypeDef;\n\n/**\n  * @brief Independent WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */\n  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */\n  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */\n  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */\n} IWDG_TypeDef;\n\n\n/**\n  * @brief Power Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */\n  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */\n} PWR_TypeDef;\n\n/**\n  * @brief Reset and Clock Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */\n  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */\n  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */\n  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */\n  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */\n  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */\n  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */\n  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */\n  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */\n  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */\n  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */\n  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */\n  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */\n  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */\n  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */\n  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */\n  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */\n  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\n  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\n  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\n  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */\n  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\n  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\n  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */\n  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */\n  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */\n  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */\n  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */\n  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */\n} RCC_TypeDef;\n\n/**\n  * @brief Real-Time Clock\n  */\n\ntypedef struct\n{\n  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */\n  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */\n  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */\n  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */\n  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */\n  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */\n  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */\n  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */\n  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */\n  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */\n  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */\n  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */\n  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */\n  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */\n  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */\n  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */\n  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */\n  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */\n  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */\n  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */\n  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */\n  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */\n  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */\n  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */\n  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */\n  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */\n  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */\n  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */\n  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */\n  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */\n  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */\n  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */\n  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */\n  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */\n  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */\n  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */\n  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */\n  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */\n  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */\n  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */\n} RTC_TypeDef;\n\n/**\n  * @brief SD host Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t POWER;                 /*!< SDIO power control register,    Address offset: 0x00 */\n  __IO uint32_t CLKCR;                 /*!< SDI clock control register,     Address offset: 0x04 */\n  __IO uint32_t ARG;                   /*!< SDIO argument register,         Address offset: 0x08 */\n  __IO uint32_t CMD;                   /*!< SDIO command register,          Address offset: 0x0C */\n  __IO const uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */\n  __IO const uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */\n  __IO const uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */\n  __IO const uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */\n  __IO const uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */\n  __IO uint32_t DTIMER;                /*!< SDIO data timer register,       Address offset: 0x24 */\n  __IO uint32_t DLEN;                  /*!< SDIO data length register,      Address offset: 0x28 */\n  __IO uint32_t DCTRL;                 /*!< SDIO data control register,     Address offset: 0x2C */\n  __IO const uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */\n  __IO const uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */\n  __IO uint32_t ICR;                   /*!< SDIO interrupt clear register,  Address offset: 0x38 */\n  __IO uint32_t MASK;                  /*!< SDIO mask register,             Address offset: 0x3C */\n  uint32_t      RESERVED0[2];          /*!< Reserved, 0x40-0x44                                  */\n  __IO const uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */\n  uint32_t      RESERVED1[13];         /*!< Reserved, 0x4C-0x7C                                  */\n  __IO uint32_t FIFO;                  /*!< SDIO data FIFO register,        Address offset: 0x80 */\n} SDIO_TypeDef;\n\n/**\n  * @brief Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */\n  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */\n  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */\n  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\n  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */\n  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */\n  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */\n  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */\n} SPI_TypeDef;\n\n\n/**\n  * @brief TIM\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */\n  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */\n  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */\n  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */\n  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */\n  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\n  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\n  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */\n  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */\n  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */\n  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */\n  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */\n  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */\n  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */\n  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */\n  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */\n  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */\n  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */\n  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */\n  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */\n} TIM_TypeDef;\n\n/**\n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */\n  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */\n  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */\n  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */\n  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */\n  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */\n  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */\n} USART_TypeDef;\n\n/**\n  * @brief Window WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */\n  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */\n  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */\n} WWDG_TypeDef;\n\n/**\n  * @brief RNG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */\n  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */\n  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */\n} RNG_TypeDef;\n\n/**\n  * @brief USB_OTG_Core_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */\n  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */\n  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */\n  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */\n  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */\n  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */\n  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */\n  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */\n  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */\n  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */\n  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */\n  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */\n  uint32_t Reserved30[2];             /*!< Reserved                                     030h */\n  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */\n  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */\n  uint32_t  Reserved40[48];           /*!< Reserved                                0x40-0xFF */\n  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */\n  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                        */\n} USB_OTG_GlobalTypeDef;\n\n/**\n  * @brief USB_OTG_device_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */\n  __IO uint32_t DCTL;            /*!< dev Control Register         804h */\n  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */\n  uint32_t Reserved0C;           /*!< Reserved                     80Ch */\n  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */\n  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */\n  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */\n  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */\n  uint32_t  Reserved20;          /*!< Reserved                     820h */\n  uint32_t Reserved9;            /*!< Reserved                     824h */\n  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */\n  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */\n  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */\n  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */\n  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */\n  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */\n  uint32_t Reserved40;           /*!< dedicated EP mask            840h */\n  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */\n  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */\n  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */\n} USB_OTG_DeviceTypeDef;\n\n/**\n  * @brief USB_OTG_IN_Endpoint-Specific_Register\n  */\ntypedef struct\n{\n  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */\n  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */\n  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */\n  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\n  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\n} USB_OTG_INEndpointTypeDef;\n\n/**\n  * @brief USB_OTG_OUT_Endpoint-Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */\n  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */\n  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */\n  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\n} USB_OTG_OUTEndpointTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Mode_Register_Structures\n  */\ntypedef struct\n{\n  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */\n  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */\n  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */\n  uint32_t Reserved40C;           /*!< Reserved                             40Ch */\n  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */\n  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */\n  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */\n} USB_OTG_HostTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Channel_Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */\n  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */\n  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */\n  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */\n  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */\n  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */\n  uint32_t Reserved[2];           /*!< Reserved                                      */\n} USB_OTG_HostChannelTypeDef;\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_memory_map\n  * @{\n  */\n#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */\n#define CCMDATARAM_BASE       0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */\n#define SRAM1_BASE            0x20000000U /*!< SRAM1(112 KB) base address in the alias region                              */\n#define SRAM2_BASE            0x2001C000U /*!< SRAM2(16 KB) base address in the alias region                              */\n#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */\n#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */\n#define FSMC_R_BASE           0xA0000000U /*!< FSMC registers base address                                                */\n#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                          */\n#define SRAM2_BB_BASE         0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region                           */\n#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                             */\n#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                      */\n#define FLASH_END             0x080FFFFFU /*!< FLASH end address                                                          */\n#define FLASH_OTP_BASE        0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */\n#define FLASH_OTP_END         0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */\n#define CCMDATARAM_END        0x1000FFFFU /*!< CCM data RAM end address                                                   */\n\n/* Legacy defines */\n#define SRAM_BASE             SRAM1_BASE\n#define SRAM_BB_BASE          SRAM1_BB_BASE\n\n/*!< Peripheral memory map */\n#define APB1PERIPH_BASE       PERIPH_BASE\n#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)\n#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)\n#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)\n\n/*!< APB1 peripherals */\n#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)\n#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)\n#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)\n#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)\n#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)\n#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)\n#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)\n#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)\n#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)\n#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)\n#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)\n#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)\n#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)\n#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)\n#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)\n#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)\n#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)\n#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)\n#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)\n#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)\n#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)\n#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)\n#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)\n#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)\n#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)\n#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)\n#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)\n\n/*!< APB2 peripherals */\n#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)\n#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)\n#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)\n#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)\n#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)\n#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)\n#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)\n#define ADC123_COMMON_BASE    (APB2PERIPH_BASE + 0x2300U)\n/* Legacy define */\n#define ADC_BASE               ADC123_COMMON_BASE\n#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)\n#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)\n#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)\n#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)\n#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)\n#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)\n#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)\n\n/*!< AHB1 peripherals */\n#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)\n#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)\n#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)\n#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)\n#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)\n#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)\n#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)\n#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)\n#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)\n#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)\n#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)\n#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)\n#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)\n#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)\n#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)\n#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)\n#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)\n#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)\n#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)\n#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)\n#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)\n#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)\n#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)\n#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)\n#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)\n#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)\n#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)\n#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)\n#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)\n#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)\n#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)\n#define ETH_MAC_BASE          (ETH_BASE)\n#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)\n#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)\n#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)\n\n/*!< AHB2 peripherals */\n#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)\n#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)\n\n/*!< FSMC Bankx registers base address */\n#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000U)\n#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104U)\n#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060U)\n#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0U)\n\n\n/*!< Debug MCU registers base address */\n#define DBGMCU_BASE           0xE0042000U\n/*!< USB registers base address */\n#define USB_OTG_HS_PERIPH_BASE               0x40040000U\n#define USB_OTG_FS_PERIPH_BASE               0x50000000U\n\n#define USB_OTG_GLOBAL_BASE                  0x000U\n#define USB_OTG_DEVICE_BASE                  0x800U\n#define USB_OTG_IN_ENDPOINT_BASE             0x900U\n#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U\n#define USB_OTG_EP_REG_SIZE                  0x20U\n#define USB_OTG_HOST_BASE                    0x400U\n#define USB_OTG_HOST_PORT_BASE               0x440U\n#define USB_OTG_HOST_CHANNEL_BASE            0x500U\n#define USB_OTG_HOST_CHANNEL_SIZE            0x20U\n#define USB_OTG_PCGCCTL_BASE                 0xE00U\n#define USB_OTG_FIFO_BASE                    0x1000U\n#define USB_OTG_FIFO_SIZE                    0x1000U\n\n#define UID_BASE                     0x1FFF7A10U           /*!< Unique device ID register base address */\n#define FLASHSIZE_BASE               0x1FFF7A22U           /*!< FLASH Size register base address       */\n#define PACKAGE_BASE                 0x1FFF7BF0U           /*!< Package size register base address     */\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_declaration\n  * @{\n  */\n#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\n#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\n#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\n#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\n#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\n#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\n#define TIM12               ((TIM_TypeDef *) TIM12_BASE)\n#define TIM13               ((TIM_TypeDef *) TIM13_BASE)\n#define TIM14               ((TIM_TypeDef *) TIM14_BASE)\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\n#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\n#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\n#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)\n#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\n#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\n#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)\n#define USART2              ((USART_TypeDef *) USART2_BASE)\n#define USART3              ((USART_TypeDef *) USART3_BASE)\n#define UART4               ((USART_TypeDef *) UART4_BASE)\n#define UART5               ((USART_TypeDef *) UART5_BASE)\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\n#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\n#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\n#define CAN1                ((CAN_TypeDef *) CAN1_BASE)\n#define CAN2                ((CAN_TypeDef *) CAN2_BASE)\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\n#define DAC1                ((DAC_TypeDef *) DAC_BASE)\n#define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */\n#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\n#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\n#define USART1              ((USART_TypeDef *) USART1_BASE)\n#define USART6              ((USART_TypeDef *) USART6_BASE)\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\n#define ADC2                ((ADC_TypeDef *) ADC2_BASE)\n#define ADC3                ((ADC_TypeDef *) ADC3_BASE)\n#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)\n/* Legacy define */\n#define ADC                  ADC123_COMMON\n#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\n#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\n#define TIM9                ((TIM_TypeDef *) TIM9_BASE)\n#define TIM10               ((TIM_TypeDef *) TIM10_BASE)\n#define TIM11               ((TIM_TypeDef *) TIM11_BASE)\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\n#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\n#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\n#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)\n#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\n#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\n#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\n#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\n#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\n#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\n#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\n#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\n#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\n#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\n#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\n#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\n#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\n#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\n#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\n#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\n#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\n#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\n#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\n#define ETH                 ((ETH_TypeDef *) ETH_BASE)\n#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)\n#define RNG                 ((RNG_TypeDef *) RNG_BASE)\n#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)\n#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)\n#define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)\n#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)\n#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\n#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\n#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_constants\n  * @{\n  */\n\n  /** @addtogroup Peripheral_Registers_Bits_Definition\n  * @{\n  */\n\n/******************************************************************************/\n/*                         Peripheral Registers_Bits_Definition               */\n/******************************************************************************/\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Analog to Digital Converter                         */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define ADC_MULTIMODE_SUPPORT                                                  /*!<ADC Multimode feature available on specific devices */\n\n/********************  Bit definition for ADC_SR register  ********************/\n#define ADC_SR_AWD_Pos            (0U)\n#define ADC_SR_AWD_Msk            (0x1U << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */\n#define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */\n#define ADC_SR_EOC_Pos            (1U)\n#define ADC_SR_EOC_Msk            (0x1U << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */\n#define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */\n#define ADC_SR_JEOC_Pos           (2U)\n#define ADC_SR_JEOC_Msk           (0x1U << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */\n#define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */\n#define ADC_SR_JSTRT_Pos          (3U)\n#define ADC_SR_JSTRT_Msk          (0x1U << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */\n#define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */\n#define ADC_SR_STRT_Pos           (4U)\n#define ADC_SR_STRT_Msk           (0x1U << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */\n#define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */\n#define ADC_SR_OVR_Pos            (5U)\n#define ADC_SR_OVR_Msk            (0x1U << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */\n#define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */\n\n/*******************  Bit definition for ADC_CR1 register  ********************/\n#define ADC_CR1_AWDCH_Pos         (0U)\n#define ADC_CR1_AWDCH_Msk         (0x1FU << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */\n#define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\n#define ADC_CR1_AWDCH_0           (0x01U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */\n#define ADC_CR1_AWDCH_1           (0x02U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */\n#define ADC_CR1_AWDCH_2           (0x04U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */\n#define ADC_CR1_AWDCH_3           (0x08U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */\n#define ADC_CR1_AWDCH_4           (0x10U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */\n#define ADC_CR1_EOCIE_Pos         (5U)\n#define ADC_CR1_EOCIE_Msk         (0x1U << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */\n#define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */\n#define ADC_CR1_AWDIE_Pos         (6U)\n#define ADC_CR1_AWDIE_Msk         (0x1U << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */\n#define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */\n#define ADC_CR1_JEOCIE_Pos        (7U)\n#define ADC_CR1_JEOCIE_Msk        (0x1U << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */\n#define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */\n#define ADC_CR1_SCAN_Pos          (8U)\n#define ADC_CR1_SCAN_Msk          (0x1U << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */\n#define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */\n#define ADC_CR1_AWDSGL_Pos        (9U)\n#define ADC_CR1_AWDSGL_Msk        (0x1U << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */\n#define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */\n#define ADC_CR1_JAUTO_Pos         (10U)\n#define ADC_CR1_JAUTO_Msk         (0x1U << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */\n#define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */\n#define ADC_CR1_DISCEN_Pos        (11U)\n#define ADC_CR1_DISCEN_Msk        (0x1U << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */\n#define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */\n#define ADC_CR1_JDISCEN_Pos       (12U)\n#define ADC_CR1_JDISCEN_Msk       (0x1U << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */\n#define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */\n#define ADC_CR1_DISCNUM_Pos       (13U)\n#define ADC_CR1_DISCNUM_Msk       (0x7U << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */\n#define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\n#define ADC_CR1_DISCNUM_0         (0x1U << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */\n#define ADC_CR1_DISCNUM_1         (0x2U << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */\n#define ADC_CR1_DISCNUM_2         (0x4U << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */\n#define ADC_CR1_JAWDEN_Pos        (22U)\n#define ADC_CR1_JAWDEN_Msk        (0x1U << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */\n#define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */\n#define ADC_CR1_AWDEN_Pos         (23U)\n#define ADC_CR1_AWDEN_Msk         (0x1U << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */\n#define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */\n#define ADC_CR1_RES_Pos           (24U)\n#define ADC_CR1_RES_Msk           (0x3U << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */\n#define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */\n#define ADC_CR1_RES_0             (0x1U << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */\n#define ADC_CR1_RES_1             (0x2U << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */\n#define ADC_CR1_OVRIE_Pos         (26U)\n#define ADC_CR1_OVRIE_Msk         (0x1U << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */\n#define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */\n\n/*******************  Bit definition for ADC_CR2 register  ********************/\n#define ADC_CR2_ADON_Pos          (0U)\n#define ADC_CR2_ADON_Msk          (0x1U << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */\n#define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */\n#define ADC_CR2_CONT_Pos          (1U)\n#define ADC_CR2_CONT_Msk          (0x1U << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */\n#define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */\n#define ADC_CR2_DMA_Pos           (8U)\n#define ADC_CR2_DMA_Msk           (0x1U << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */\n#define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */\n#define ADC_CR2_DDS_Pos           (9U)\n#define ADC_CR2_DDS_Msk           (0x1U << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */\n#define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */\n#define ADC_CR2_EOCS_Pos          (10U)\n#define ADC_CR2_EOCS_Msk          (0x1U << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */\n#define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */\n#define ADC_CR2_ALIGN_Pos         (11U)\n#define ADC_CR2_ALIGN_Msk         (0x1U << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */\n#define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */\n#define ADC_CR2_JEXTSEL_Pos       (16U)\n#define ADC_CR2_JEXTSEL_Msk       (0xFU << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */\n#define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */\n#define ADC_CR2_JEXTSEL_0         (0x1U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */\n#define ADC_CR2_JEXTSEL_1         (0x2U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */\n#define ADC_CR2_JEXTSEL_2         (0x4U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */\n#define ADC_CR2_JEXTSEL_3         (0x8U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */\n#define ADC_CR2_JEXTEN_Pos        (20U)\n#define ADC_CR2_JEXTEN_Msk        (0x3U << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */\n#define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\n#define ADC_CR2_JEXTEN_0          (0x1U << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */\n#define ADC_CR2_JEXTEN_1          (0x2U << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */\n#define ADC_CR2_JSWSTART_Pos      (22U)\n#define ADC_CR2_JSWSTART_Msk      (0x1U << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */\n#define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */\n#define ADC_CR2_EXTSEL_Pos        (24U)\n#define ADC_CR2_EXTSEL_Msk        (0xFU << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */\n#define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\n#define ADC_CR2_EXTSEL_0          (0x1U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */\n#define ADC_CR2_EXTSEL_1          (0x2U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */\n#define ADC_CR2_EXTSEL_2          (0x4U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */\n#define ADC_CR2_EXTSEL_3          (0x8U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */\n#define ADC_CR2_EXTEN_Pos         (28U)\n#define ADC_CR2_EXTEN_Msk         (0x3U << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */\n#define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\n#define ADC_CR2_EXTEN_0           (0x1U << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */\n#define ADC_CR2_EXTEN_1           (0x2U << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */\n#define ADC_CR2_SWSTART_Pos       (30U)\n#define ADC_CR2_SWSTART_Msk       (0x1U << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */\n#define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */\n\n/******************  Bit definition for ADC_SMPR1 register  *******************/\n#define ADC_SMPR1_SMP10_Pos       (0U)\n#define ADC_SMPR1_SMP10_Msk       (0x7U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */\n#define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\n#define ADC_SMPR1_SMP10_0         (0x1U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */\n#define ADC_SMPR1_SMP10_1         (0x2U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */\n#define ADC_SMPR1_SMP10_2         (0x4U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */\n#define ADC_SMPR1_SMP11_Pos       (3U)\n#define ADC_SMPR1_SMP11_Msk       (0x7U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */\n#define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\n#define ADC_SMPR1_SMP11_0         (0x1U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */\n#define ADC_SMPR1_SMP11_1         (0x2U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */\n#define ADC_SMPR1_SMP11_2         (0x4U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */\n#define ADC_SMPR1_SMP12_Pos       (6U)\n#define ADC_SMPR1_SMP12_Msk       (0x7U << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */\n#define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\n#define ADC_SMPR1_SMP12_0         (0x1U << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */\n#define ADC_SMPR1_SMP12_1         (0x2U << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */\n#define ADC_SMPR1_SMP12_2         (0x4U << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */\n#define ADC_SMPR1_SMP13_Pos       (9U)\n#define ADC_SMPR1_SMP13_Msk       (0x7U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */\n#define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\n#define ADC_SMPR1_SMP13_0         (0x1U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */\n#define ADC_SMPR1_SMP13_1         (0x2U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */\n#define ADC_SMPR1_SMP13_2         (0x4U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */\n#define ADC_SMPR1_SMP14_Pos       (12U)\n#define ADC_SMPR1_SMP14_Msk       (0x7U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */\n#define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\n#define ADC_SMPR1_SMP14_0         (0x1U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */\n#define ADC_SMPR1_SMP14_1         (0x2U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */\n#define ADC_SMPR1_SMP14_2         (0x4U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */\n#define ADC_SMPR1_SMP15_Pos       (15U)\n#define ADC_SMPR1_SMP15_Msk       (0x7U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */\n#define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\n#define ADC_SMPR1_SMP15_0         (0x1U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */\n#define ADC_SMPR1_SMP15_1         (0x2U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */\n#define ADC_SMPR1_SMP15_2         (0x4U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */\n#define ADC_SMPR1_SMP16_Pos       (18U)\n#define ADC_SMPR1_SMP16_Msk       (0x7U << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */\n#define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\n#define ADC_SMPR1_SMP16_0         (0x1U << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */\n#define ADC_SMPR1_SMP16_1         (0x2U << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */\n#define ADC_SMPR1_SMP16_2         (0x4U << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */\n#define ADC_SMPR1_SMP17_Pos       (21U)\n#define ADC_SMPR1_SMP17_Msk       (0x7U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */\n#define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\n#define ADC_SMPR1_SMP17_0         (0x1U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */\n#define ADC_SMPR1_SMP17_1         (0x2U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */\n#define ADC_SMPR1_SMP17_2         (0x4U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */\n#define ADC_SMPR1_SMP18_Pos       (24U)\n#define ADC_SMPR1_SMP18_Msk       (0x7U << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */\n#define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\n#define ADC_SMPR1_SMP18_0         (0x1U << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */\n#define ADC_SMPR1_SMP18_1         (0x2U << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */\n#define ADC_SMPR1_SMP18_2         (0x4U << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */\n\n/******************  Bit definition for ADC_SMPR2 register  *******************/\n#define ADC_SMPR2_SMP0_Pos        (0U)\n#define ADC_SMPR2_SMP0_Msk        (0x7U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */\n#define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\n#define ADC_SMPR2_SMP0_0          (0x1U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */\n#define ADC_SMPR2_SMP0_1          (0x2U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */\n#define ADC_SMPR2_SMP0_2          (0x4U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */\n#define ADC_SMPR2_SMP1_Pos        (3U)\n#define ADC_SMPR2_SMP1_Msk        (0x7U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */\n#define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\n#define ADC_SMPR2_SMP1_0          (0x1U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */\n#define ADC_SMPR2_SMP1_1          (0x2U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */\n#define ADC_SMPR2_SMP1_2          (0x4U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */\n#define ADC_SMPR2_SMP2_Pos        (6U)\n#define ADC_SMPR2_SMP2_Msk        (0x7U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */\n#define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\n#define ADC_SMPR2_SMP2_0          (0x1U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */\n#define ADC_SMPR2_SMP2_1          (0x2U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */\n#define ADC_SMPR2_SMP2_2          (0x4U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */\n#define ADC_SMPR2_SMP3_Pos        (9U)\n#define ADC_SMPR2_SMP3_Msk        (0x7U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */\n#define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\n#define ADC_SMPR2_SMP3_0          (0x1U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */\n#define ADC_SMPR2_SMP3_1          (0x2U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */\n#define ADC_SMPR2_SMP3_2          (0x4U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */\n#define ADC_SMPR2_SMP4_Pos        (12U)\n#define ADC_SMPR2_SMP4_Msk        (0x7U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */\n#define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\n#define ADC_SMPR2_SMP4_0          (0x1U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */\n#define ADC_SMPR2_SMP4_1          (0x2U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */\n#define ADC_SMPR2_SMP4_2          (0x4U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */\n#define ADC_SMPR2_SMP5_Pos        (15U)\n#define ADC_SMPR2_SMP5_Msk        (0x7U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */\n#define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\n#define ADC_SMPR2_SMP5_0          (0x1U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */\n#define ADC_SMPR2_SMP5_1          (0x2U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */\n#define ADC_SMPR2_SMP5_2          (0x4U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */\n#define ADC_SMPR2_SMP6_Pos        (18U)\n#define ADC_SMPR2_SMP6_Msk        (0x7U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */\n#define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\n#define ADC_SMPR2_SMP6_0          (0x1U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */\n#define ADC_SMPR2_SMP6_1          (0x2U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */\n#define ADC_SMPR2_SMP6_2          (0x4U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */\n#define ADC_SMPR2_SMP7_Pos        (21U)\n#define ADC_SMPR2_SMP7_Msk        (0x7U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */\n#define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\n#define ADC_SMPR2_SMP7_0          (0x1U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */\n#define ADC_SMPR2_SMP7_1          (0x2U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */\n#define ADC_SMPR2_SMP7_2          (0x4U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */\n#define ADC_SMPR2_SMP8_Pos        (24U)\n#define ADC_SMPR2_SMP8_Msk        (0x7U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */\n#define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\n#define ADC_SMPR2_SMP8_0          (0x1U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */\n#define ADC_SMPR2_SMP8_1          (0x2U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */\n#define ADC_SMPR2_SMP8_2          (0x4U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */\n#define ADC_SMPR2_SMP9_Pos        (27U)\n#define ADC_SMPR2_SMP9_Msk        (0x7U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */\n#define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\n#define ADC_SMPR2_SMP9_0          (0x1U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */\n#define ADC_SMPR2_SMP9_1          (0x2U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */\n#define ADC_SMPR2_SMP9_2          (0x4U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */\n\n/******************  Bit definition for ADC_JOFR1 register  *******************/\n#define ADC_JOFR1_JOFFSET1_Pos    (0U)\n#define ADC_JOFR1_JOFFSET1_Msk    (0xFFFU << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */\n\n/******************  Bit definition for ADC_JOFR2 register  *******************/\n#define ADC_JOFR2_JOFFSET2_Pos    (0U)\n#define ADC_JOFR2_JOFFSET2_Msk    (0xFFFU << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */\n\n/******************  Bit definition for ADC_JOFR3 register  *******************/\n#define ADC_JOFR3_JOFFSET3_Pos    (0U)\n#define ADC_JOFR3_JOFFSET3_Msk    (0xFFFU << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */\n\n/******************  Bit definition for ADC_JOFR4 register  *******************/\n#define ADC_JOFR4_JOFFSET4_Pos    (0U)\n#define ADC_JOFR4_JOFFSET4_Msk    (0xFFFU << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */\n\n/*******************  Bit definition for ADC_HTR register  ********************/\n#define ADC_HTR_HT_Pos            (0U)\n#define ADC_HTR_HT_Msk            (0xFFFU << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */\n#define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */\n\n/*******************  Bit definition for ADC_LTR register  ********************/\n#define ADC_LTR_LT_Pos            (0U)\n#define ADC_LTR_LT_Msk            (0xFFFU << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */\n#define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */\n\n/*******************  Bit definition for ADC_SQR1 register  *******************/\n#define ADC_SQR1_SQ13_Pos         (0U)\n#define ADC_SQR1_SQ13_Msk         (0x1FU << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */\n#define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\n#define ADC_SQR1_SQ13_0           (0x01U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */\n#define ADC_SQR1_SQ13_1           (0x02U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */\n#define ADC_SQR1_SQ13_2           (0x04U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */\n#define ADC_SQR1_SQ13_3           (0x08U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */\n#define ADC_SQR1_SQ13_4           (0x10U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */\n#define ADC_SQR1_SQ14_Pos         (5U)\n#define ADC_SQR1_SQ14_Msk         (0x1FU << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */\n#define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\n#define ADC_SQR1_SQ14_0           (0x01U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */\n#define ADC_SQR1_SQ14_1           (0x02U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */\n#define ADC_SQR1_SQ14_2           (0x04U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */\n#define ADC_SQR1_SQ14_3           (0x08U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */\n#define ADC_SQR1_SQ14_4           (0x10U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */\n#define ADC_SQR1_SQ15_Pos         (10U)\n#define ADC_SQR1_SQ15_Msk         (0x1FU << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */\n#define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\n#define ADC_SQR1_SQ15_0           (0x01U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */\n#define ADC_SQR1_SQ15_1           (0x02U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */\n#define ADC_SQR1_SQ15_2           (0x04U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */\n#define ADC_SQR1_SQ15_3           (0x08U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */\n#define ADC_SQR1_SQ15_4           (0x10U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */\n#define ADC_SQR1_SQ16_Pos         (15U)\n#define ADC_SQR1_SQ16_Msk         (0x1FU << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\n#define ADC_SQR1_SQ16_0           (0x01U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR1_SQ16_1           (0x02U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR1_SQ16_2           (0x04U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR1_SQ16_3           (0x08U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR1_SQ16_4           (0x10U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR1_L_Pos            (20U)\n#define ADC_SQR1_L_Msk            (0xFU << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */\n#define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */\n#define ADC_SQR1_L_0              (0x1U << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */\n#define ADC_SQR1_L_1              (0x2U << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */\n#define ADC_SQR1_L_2              (0x4U << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */\n#define ADC_SQR1_L_3              (0x8U << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */\n\n/*******************  Bit definition for ADC_SQR2 register  *******************/\n#define ADC_SQR2_SQ7_Pos          (0U)\n#define ADC_SQR2_SQ7_Msk          (0x1FU << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\n#define ADC_SQR2_SQ7_0            (0x01U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR2_SQ7_1            (0x02U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR2_SQ7_2            (0x04U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR2_SQ7_3            (0x08U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR2_SQ7_4            (0x10U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR2_SQ8_Pos          (5U)\n#define ADC_SQR2_SQ8_Msk          (0x1FU << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\n#define ADC_SQR2_SQ8_0            (0x01U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR2_SQ8_1            (0x02U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR2_SQ8_2            (0x04U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR2_SQ8_3            (0x08U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR2_SQ8_4            (0x10U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR2_SQ9_Pos          (10U)\n#define ADC_SQR2_SQ9_Msk          (0x1FU << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\n#define ADC_SQR2_SQ9_0            (0x01U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR2_SQ9_1            (0x02U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR2_SQ9_2            (0x04U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR2_SQ9_3            (0x08U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR2_SQ9_4            (0x10U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR2_SQ10_Pos         (15U)\n#define ADC_SQR2_SQ10_Msk         (0x1FU << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\n#define ADC_SQR2_SQ10_0           (0x01U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR2_SQ10_1           (0x02U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR2_SQ10_2           (0x04U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR2_SQ10_3           (0x08U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR2_SQ10_4           (0x10U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR2_SQ11_Pos         (20U)\n#define ADC_SQR2_SQ11_Msk         (0x1FU << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */\n#define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\n#define ADC_SQR2_SQ11_0           (0x01U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */\n#define ADC_SQR2_SQ11_1           (0x02U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */\n#define ADC_SQR2_SQ11_2           (0x04U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */\n#define ADC_SQR2_SQ11_3           (0x08U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */\n#define ADC_SQR2_SQ11_4           (0x10U << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */\n#define ADC_SQR2_SQ12_Pos         (25U)\n#define ADC_SQR2_SQ12_Msk         (0x1FU << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */\n#define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\n#define ADC_SQR2_SQ12_0           (0x01U << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */\n#define ADC_SQR2_SQ12_1           (0x02U << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */\n#define ADC_SQR2_SQ12_2           (0x04U << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */\n#define ADC_SQR2_SQ12_3           (0x08U << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */\n#define ADC_SQR2_SQ12_4           (0x10U << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_SQR3 register  *******************/\n#define ADC_SQR3_SQ1_Pos          (0U)\n#define ADC_SQR3_SQ1_Msk          (0x1FU << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\n#define ADC_SQR3_SQ1_0            (0x01U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR3_SQ1_1            (0x02U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR3_SQ1_2            (0x04U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR3_SQ1_3            (0x08U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR3_SQ1_4            (0x10U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR3_SQ2_Pos          (5U)\n#define ADC_SQR3_SQ2_Msk          (0x1FU << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\n#define ADC_SQR3_SQ2_0            (0x01U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR3_SQ2_1            (0x02U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR3_SQ2_2            (0x04U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR3_SQ2_3            (0x08U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR3_SQ2_4            (0x10U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR3_SQ3_Pos          (10U)\n#define ADC_SQR3_SQ3_Msk          (0x1FU << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\n#define ADC_SQR3_SQ3_0            (0x01U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR3_SQ3_1            (0x02U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR3_SQ3_2            (0x04U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR3_SQ3_3            (0x08U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR3_SQ3_4            (0x10U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR3_SQ4_Pos          (15U)\n#define ADC_SQR3_SQ4_Msk          (0x1FU << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */\n#define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\n#define ADC_SQR3_SQ4_0            (0x01U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */\n#define ADC_SQR3_SQ4_1            (0x02U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */\n#define ADC_SQR3_SQ4_2            (0x04U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */\n#define ADC_SQR3_SQ4_3            (0x08U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */\n#define ADC_SQR3_SQ4_4            (0x10U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */\n#define ADC_SQR3_SQ5_Pos          (20U)\n#define ADC_SQR3_SQ5_Msk          (0x1FU << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */\n#define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\n#define ADC_SQR3_SQ5_0            (0x01U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */\n#define ADC_SQR3_SQ5_1            (0x02U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */\n#define ADC_SQR3_SQ5_2            (0x04U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */\n#define ADC_SQR3_SQ5_3            (0x08U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */\n#define ADC_SQR3_SQ5_4            (0x10U << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */\n#define ADC_SQR3_SQ6_Pos          (25U)\n#define ADC_SQR3_SQ6_Msk          (0x1FU << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */\n#define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\n#define ADC_SQR3_SQ6_0            (0x01U << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */\n#define ADC_SQR3_SQ6_1            (0x02U << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */\n#define ADC_SQR3_SQ6_2            (0x04U << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */\n#define ADC_SQR3_SQ6_3            (0x08U << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */\n#define ADC_SQR3_SQ6_4            (0x10U << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_JSQR register  *******************/\n#define ADC_JSQR_JSQ1_Pos         (0U)\n#define ADC_JSQR_JSQ1_Msk         (0x1FU << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */\n#define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */\n#define ADC_JSQR_JSQ1_0           (0x01U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */\n#define ADC_JSQR_JSQ1_1           (0x02U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */\n#define ADC_JSQR_JSQ1_2           (0x04U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */\n#define ADC_JSQR_JSQ1_3           (0x08U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */\n#define ADC_JSQR_JSQ1_4           (0x10U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */\n#define ADC_JSQR_JSQ2_Pos         (5U)\n#define ADC_JSQR_JSQ2_Msk         (0x1FU << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */\n#define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\n#define ADC_JSQR_JSQ2_0           (0x01U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */\n#define ADC_JSQR_JSQ2_1           (0x02U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */\n#define ADC_JSQR_JSQ2_2           (0x04U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */\n#define ADC_JSQR_JSQ2_3           (0x08U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */\n#define ADC_JSQR_JSQ2_4           (0x10U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */\n#define ADC_JSQR_JSQ3_Pos         (10U)\n#define ADC_JSQR_JSQ3_Msk         (0x1FU << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */\n#define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\n#define ADC_JSQR_JSQ3_0           (0x01U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */\n#define ADC_JSQR_JSQ3_1           (0x02U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */\n#define ADC_JSQR_JSQ3_2           (0x04U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */\n#define ADC_JSQR_JSQ3_3           (0x08U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */\n#define ADC_JSQR_JSQ3_4           (0x10U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */\n#define ADC_JSQR_JSQ4_Pos         (15U)\n#define ADC_JSQR_JSQ4_Msk         (0x1FU << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */\n#define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\n#define ADC_JSQR_JSQ4_0           (0x01U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */\n#define ADC_JSQR_JSQ4_1           (0x02U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */\n#define ADC_JSQR_JSQ4_2           (0x04U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */\n#define ADC_JSQR_JSQ4_3           (0x08U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */\n#define ADC_JSQR_JSQ4_4           (0x10U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */\n#define ADC_JSQR_JL_Pos           (20U)\n#define ADC_JSQR_JL_Msk           (0x3U << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */\n#define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */\n#define ADC_JSQR_JL_0             (0x1U << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */\n#define ADC_JSQR_JL_1             (0x2U << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */\n\n/*******************  Bit definition for ADC_JDR1 register  *******************/\n#define ADC_JDR1_JDATA_Pos        (0U)\n#define ADC_JDR1_JDATA_Msk        (0xFFFFU << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR2 register  *******************/\n#define ADC_JDR2_JDATA_Pos        (0U)\n#define ADC_JDR2_JDATA_Msk        (0xFFFFU << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR3 register  *******************/\n#define ADC_JDR3_JDATA_Pos        (0U)\n#define ADC_JDR3_JDATA_Msk        (0xFFFFU << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR4 register  *******************/\n#define ADC_JDR4_JDATA_Pos        (0U)\n#define ADC_JDR4_JDATA_Msk        (0xFFFFU << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */\n\n/********************  Bit definition for ADC_DR register  ********************/\n#define ADC_DR_DATA_Pos           (0U)\n#define ADC_DR_DATA_Msk           (0xFFFFU << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */\n#define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */\n#define ADC_DR_ADC2DATA_Pos       (16U)\n#define ADC_DR_ADC2DATA_Msk       (0xFFFFU << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */\n#define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */\n\n/*******************  Bit definition for ADC_CSR register  ********************/\n#define ADC_CSR_AWD1_Pos          (0U)\n#define ADC_CSR_AWD1_Msk          (0x1U << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */\n#define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */\n#define ADC_CSR_EOC1_Pos          (1U)\n#define ADC_CSR_EOC1_Msk          (0x1U << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */\n#define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */\n#define ADC_CSR_JEOC1_Pos         (2U)\n#define ADC_CSR_JEOC1_Msk         (0x1U << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */\n#define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */\n#define ADC_CSR_JSTRT1_Pos        (3U)\n#define ADC_CSR_JSTRT1_Msk        (0x1U << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */\n#define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */\n#define ADC_CSR_STRT1_Pos         (4U)\n#define ADC_CSR_STRT1_Msk         (0x1U << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */\n#define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */\n#define ADC_CSR_OVR1_Pos          (5U)\n#define ADC_CSR_OVR1_Msk          (0x1U << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */\n#define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */\n#define ADC_CSR_AWD2_Pos          (8U)\n#define ADC_CSR_AWD2_Msk          (0x1U << ADC_CSR_AWD2_Pos)                   /*!< 0x00000100 */\n#define ADC_CSR_AWD2              ADC_CSR_AWD2_Msk                             /*!<ADC2 Analog watchdog flag */\n#define ADC_CSR_EOC2_Pos          (9U)\n#define ADC_CSR_EOC2_Msk          (0x1U << ADC_CSR_EOC2_Pos)                   /*!< 0x00000200 */\n#define ADC_CSR_EOC2              ADC_CSR_EOC2_Msk                             /*!<ADC2 End of conversion */\n#define ADC_CSR_JEOC2_Pos         (10U)\n#define ADC_CSR_JEOC2_Msk         (0x1U << ADC_CSR_JEOC2_Pos)                  /*!< 0x00000400 */\n#define ADC_CSR_JEOC2             ADC_CSR_JEOC2_Msk                            /*!<ADC2 Injected channel end of conversion */\n#define ADC_CSR_JSTRT2_Pos        (11U)\n#define ADC_CSR_JSTRT2_Msk        (0x1U << ADC_CSR_JSTRT2_Pos)                 /*!< 0x00000800 */\n#define ADC_CSR_JSTRT2            ADC_CSR_JSTRT2_Msk                           /*!<ADC2 Injected channel Start flag */\n#define ADC_CSR_STRT2_Pos         (12U)\n#define ADC_CSR_STRT2_Msk         (0x1U << ADC_CSR_STRT2_Pos)                  /*!< 0x00001000 */\n#define ADC_CSR_STRT2             ADC_CSR_STRT2_Msk                            /*!<ADC2 Regular channel Start flag */\n#define ADC_CSR_OVR2_Pos          (13U)\n#define ADC_CSR_OVR2_Msk          (0x1U << ADC_CSR_OVR2_Pos)                   /*!< 0x00002000 */\n#define ADC_CSR_OVR2              ADC_CSR_OVR2_Msk                             /*!<ADC2 DMA overrun  flag */\n#define ADC_CSR_AWD3_Pos          (16U)\n#define ADC_CSR_AWD3_Msk          (0x1U << ADC_CSR_AWD3_Pos)                   /*!< 0x00010000 */\n#define ADC_CSR_AWD3              ADC_CSR_AWD3_Msk                             /*!<ADC3 Analog watchdog flag */\n#define ADC_CSR_EOC3_Pos          (17U)\n#define ADC_CSR_EOC3_Msk          (0x1U << ADC_CSR_EOC3_Pos)                   /*!< 0x00020000 */\n#define ADC_CSR_EOC3              ADC_CSR_EOC3_Msk                             /*!<ADC3 End of conversion */\n#define ADC_CSR_JEOC3_Pos         (18U)\n#define ADC_CSR_JEOC3_Msk         (0x1U << ADC_CSR_JEOC3_Pos)                  /*!< 0x00040000 */\n#define ADC_CSR_JEOC3             ADC_CSR_JEOC3_Msk                            /*!<ADC3 Injected channel end of conversion */\n#define ADC_CSR_JSTRT3_Pos        (19U)\n#define ADC_CSR_JSTRT3_Msk        (0x1U << ADC_CSR_JSTRT3_Pos)                 /*!< 0x00080000 */\n#define ADC_CSR_JSTRT3            ADC_CSR_JSTRT3_Msk                           /*!<ADC3 Injected channel Start flag */\n#define ADC_CSR_STRT3_Pos         (20U)\n#define ADC_CSR_STRT3_Msk         (0x1U << ADC_CSR_STRT3_Pos)                  /*!< 0x00100000 */\n#define ADC_CSR_STRT3             ADC_CSR_STRT3_Msk                            /*!<ADC3 Regular channel Start flag */\n#define ADC_CSR_OVR3_Pos          (21U)\n#define ADC_CSR_OVR3_Msk          (0x1U << ADC_CSR_OVR3_Pos)                   /*!< 0x00200000 */\n#define ADC_CSR_OVR3              ADC_CSR_OVR3_Msk                             /*!<ADC3 DMA overrun  flag */\n\n/* Legacy defines */\n#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1\n#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2\n#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3\n\n/*******************  Bit definition for ADC_CCR register  ********************/\n#define ADC_CCR_MULTI_Pos         (0U)\n#define ADC_CCR_MULTI_Msk         (0x1FU << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */\n#define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */\n#define ADC_CCR_MULTI_0           (0x01U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */\n#define ADC_CCR_MULTI_1           (0x02U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */\n#define ADC_CCR_MULTI_2           (0x04U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */\n#define ADC_CCR_MULTI_3           (0x08U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */\n#define ADC_CCR_MULTI_4           (0x10U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */\n#define ADC_CCR_DELAY_Pos         (8U)\n#define ADC_CCR_DELAY_Msk         (0xFU << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */\n#define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */\n#define ADC_CCR_DELAY_0           (0x1U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */\n#define ADC_CCR_DELAY_1           (0x2U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */\n#define ADC_CCR_DELAY_2           (0x4U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */\n#define ADC_CCR_DELAY_3           (0x8U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */\n#define ADC_CCR_DDS_Pos           (13U)\n#define ADC_CCR_DDS_Msk           (0x1U << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */\n#define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */\n#define ADC_CCR_DMA_Pos           (14U)\n#define ADC_CCR_DMA_Msk           (0x3U << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */\n#define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */\n#define ADC_CCR_DMA_0             (0x1U << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */\n#define ADC_CCR_DMA_1             (0x2U << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */\n#define ADC_CCR_ADCPRE_Pos        (16U)\n#define ADC_CCR_ADCPRE_Msk        (0x3U << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */\n#define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */\n#define ADC_CCR_ADCPRE_0          (0x1U << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */\n#define ADC_CCR_ADCPRE_1          (0x2U << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */\n#define ADC_CCR_VBATE_Pos         (22U)\n#define ADC_CCR_VBATE_Msk         (0x1U << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */\n#define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */\n#define ADC_CCR_TSVREFE_Pos       (23U)\n#define ADC_CCR_TSVREFE_Msk       (0x1U << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */\n#define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */\n\n/*******************  Bit definition for ADC_CDR register  ********************/\n#define ADC_CDR_DATA1_Pos         (0U)\n#define ADC_CDR_DATA1_Msk         (0xFFFFU << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */\n#define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */\n#define ADC_CDR_DATA2_Pos         (16U)\n#define ADC_CDR_DATA2_Msk         (0xFFFFU << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */\n#define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */\n\n/* Legacy defines */\n#define ADC_CDR_RDATA_MST         ADC_CDR_DATA1\n#define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Controller Area Network                            */\n/*                                                                            */\n/******************************************************************************/\n/*!<CAN control and status registers */\n/*******************  Bit definition for CAN_MCR register  ********************/\n#define CAN_MCR_INRQ_Pos       (0U)\n#define CAN_MCR_INRQ_Msk       (0x1U << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */\n#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */\n#define CAN_MCR_SLEEP_Pos      (1U)\n#define CAN_MCR_SLEEP_Msk      (0x1U << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */\n#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */\n#define CAN_MCR_TXFP_Pos       (2U)\n#define CAN_MCR_TXFP_Msk       (0x1U << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */\n#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */\n#define CAN_MCR_RFLM_Pos       (3U)\n#define CAN_MCR_RFLM_Msk       (0x1U << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */\n#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */\n#define CAN_MCR_NART_Pos       (4U)\n#define CAN_MCR_NART_Msk       (0x1U << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */\n#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */\n#define CAN_MCR_AWUM_Pos       (5U)\n#define CAN_MCR_AWUM_Msk       (0x1U << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */\n#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */\n#define CAN_MCR_ABOM_Pos       (6U)\n#define CAN_MCR_ABOM_Msk       (0x1U << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */\n#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */\n#define CAN_MCR_TTCM_Pos       (7U)\n#define CAN_MCR_TTCM_Msk       (0x1U << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */\n#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */\n#define CAN_MCR_RESET_Pos      (15U)\n#define CAN_MCR_RESET_Msk      (0x1U << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */\n#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */\n#define CAN_MCR_DBF_Pos        (16U)\n#define CAN_MCR_DBF_Msk        (0x1U << CAN_MCR_DBF_Pos)                       /*!< 0x00010000 */\n#define CAN_MCR_DBF            CAN_MCR_DBF_Msk                                 /*!<bxCAN Debug freeze */\n/*******************  Bit definition for CAN_MSR register  ********************/\n#define CAN_MSR_INAK_Pos       (0U)\n#define CAN_MSR_INAK_Msk       (0x1U << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */\n#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */\n#define CAN_MSR_SLAK_Pos       (1U)\n#define CAN_MSR_SLAK_Msk       (0x1U << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */\n#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */\n#define CAN_MSR_ERRI_Pos       (2U)\n#define CAN_MSR_ERRI_Msk       (0x1U << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */\n#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */\n#define CAN_MSR_WKUI_Pos       (3U)\n#define CAN_MSR_WKUI_Msk       (0x1U << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */\n#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */\n#define CAN_MSR_SLAKI_Pos      (4U)\n#define CAN_MSR_SLAKI_Msk      (0x1U << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */\n#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */\n#define CAN_MSR_TXM_Pos        (8U)\n#define CAN_MSR_TXM_Msk        (0x1U << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */\n#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */\n#define CAN_MSR_RXM_Pos        (9U)\n#define CAN_MSR_RXM_Msk        (0x1U << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */\n#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */\n#define CAN_MSR_SAMP_Pos       (10U)\n#define CAN_MSR_SAMP_Msk       (0x1U << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */\n#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */\n#define CAN_MSR_RX_Pos         (11U)\n#define CAN_MSR_RX_Msk         (0x1U << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */\n#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */\n\n/*******************  Bit definition for CAN_TSR register  ********************/\n#define CAN_TSR_RQCP0_Pos      (0U)\n#define CAN_TSR_RQCP0_Msk      (0x1U << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */\n#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */\n#define CAN_TSR_TXOK0_Pos      (1U)\n#define CAN_TSR_TXOK0_Msk      (0x1U << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */\n#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */\n#define CAN_TSR_ALST0_Pos      (2U)\n#define CAN_TSR_ALST0_Msk      (0x1U << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */\n#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */\n#define CAN_TSR_TERR0_Pos      (3U)\n#define CAN_TSR_TERR0_Msk      (0x1U << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */\n#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */\n#define CAN_TSR_ABRQ0_Pos      (7U)\n#define CAN_TSR_ABRQ0_Msk      (0x1U << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */\n#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */\n#define CAN_TSR_RQCP1_Pos      (8U)\n#define CAN_TSR_RQCP1_Msk      (0x1U << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */\n#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */\n#define CAN_TSR_TXOK1_Pos      (9U)\n#define CAN_TSR_TXOK1_Msk      (0x1U << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */\n#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */\n#define CAN_TSR_ALST1_Pos      (10U)\n#define CAN_TSR_ALST1_Msk      (0x1U << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */\n#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */\n#define CAN_TSR_TERR1_Pos      (11U)\n#define CAN_TSR_TERR1_Msk      (0x1U << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */\n#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */\n#define CAN_TSR_ABRQ1_Pos      (15U)\n#define CAN_TSR_ABRQ1_Msk      (0x1U << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */\n#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */\n#define CAN_TSR_RQCP2_Pos      (16U)\n#define CAN_TSR_RQCP2_Msk      (0x1U << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */\n#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */\n#define CAN_TSR_TXOK2_Pos      (17U)\n#define CAN_TSR_TXOK2_Msk      (0x1U << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */\n#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */\n#define CAN_TSR_ALST2_Pos      (18U)\n#define CAN_TSR_ALST2_Msk      (0x1U << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */\n#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */\n#define CAN_TSR_TERR2_Pos      (19U)\n#define CAN_TSR_TERR2_Msk      (0x1U << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */\n#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */\n#define CAN_TSR_ABRQ2_Pos      (23U)\n#define CAN_TSR_ABRQ2_Msk      (0x1U << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */\n#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */\n#define CAN_TSR_CODE_Pos       (24U)\n#define CAN_TSR_CODE_Msk       (0x3U << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */\n#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */\n\n#define CAN_TSR_TME_Pos        (26U)\n#define CAN_TSR_TME_Msk        (0x7U << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */\n#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */\n#define CAN_TSR_TME0_Pos       (26U)\n#define CAN_TSR_TME0_Msk       (0x1U << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */\n#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */\n#define CAN_TSR_TME1_Pos       (27U)\n#define CAN_TSR_TME1_Msk       (0x1U << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */\n#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */\n#define CAN_TSR_TME2_Pos       (28U)\n#define CAN_TSR_TME2_Msk       (0x1U << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */\n#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */\n\n#define CAN_TSR_LOW_Pos        (29U)\n#define CAN_TSR_LOW_Msk        (0x7U << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */\n#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */\n#define CAN_TSR_LOW0_Pos       (29U)\n#define CAN_TSR_LOW0_Msk       (0x1U << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */\n#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */\n#define CAN_TSR_LOW1_Pos       (30U)\n#define CAN_TSR_LOW1_Msk       (0x1U << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */\n#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */\n#define CAN_TSR_LOW2_Pos       (31U)\n#define CAN_TSR_LOW2_Msk       (0x1U << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */\n#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */\n\n/*******************  Bit definition for CAN_RF0R register  *******************/\n#define CAN_RF0R_FMP0_Pos      (0U)\n#define CAN_RF0R_FMP0_Msk      (0x3U << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */\n#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */\n#define CAN_RF0R_FULL0_Pos     (3U)\n#define CAN_RF0R_FULL0_Msk     (0x1U << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */\n#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */\n#define CAN_RF0R_FOVR0_Pos     (4U)\n#define CAN_RF0R_FOVR0_Msk     (0x1U << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */\n#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */\n#define CAN_RF0R_RFOM0_Pos     (5U)\n#define CAN_RF0R_RFOM0_Msk     (0x1U << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */\n#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */\n\n/*******************  Bit definition for CAN_RF1R register  *******************/\n#define CAN_RF1R_FMP1_Pos      (0U)\n#define CAN_RF1R_FMP1_Msk      (0x3U << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */\n#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */\n#define CAN_RF1R_FULL1_Pos     (3U)\n#define CAN_RF1R_FULL1_Msk     (0x1U << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */\n#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */\n#define CAN_RF1R_FOVR1_Pos     (4U)\n#define CAN_RF1R_FOVR1_Msk     (0x1U << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */\n#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */\n#define CAN_RF1R_RFOM1_Pos     (5U)\n#define CAN_RF1R_RFOM1_Msk     (0x1U << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */\n#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */\n\n/********************  Bit definition for CAN_IER register  *******************/\n#define CAN_IER_TMEIE_Pos      (0U)\n#define CAN_IER_TMEIE_Msk      (0x1U << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */\n#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */\n#define CAN_IER_FMPIE0_Pos     (1U)\n#define CAN_IER_FMPIE0_Msk     (0x1U << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */\n#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE0_Pos      (2U)\n#define CAN_IER_FFIE0_Msk      (0x1U << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */\n#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE0_Pos     (3U)\n#define CAN_IER_FOVIE0_Msk     (0x1U << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */\n#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_FMPIE1_Pos     (4U)\n#define CAN_IER_FMPIE1_Msk     (0x1U << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */\n#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE1_Pos      (5U)\n#define CAN_IER_FFIE1_Msk      (0x1U << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */\n#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE1_Pos     (6U)\n#define CAN_IER_FOVIE1_Msk     (0x1U << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */\n#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)\n#define CAN_IER_EWGIE_Msk      (0x1U << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */\n#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */\n#define CAN_IER_EPVIE_Pos      (9U)\n#define CAN_IER_EPVIE_Msk      (0x1U << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */\n#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */\n#define CAN_IER_BOFIE_Pos      (10U)\n#define CAN_IER_BOFIE_Msk      (0x1U << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */\n#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */\n#define CAN_IER_LECIE_Pos      (11U)\n#define CAN_IER_LECIE_Msk      (0x1U << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */\n#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */\n#define CAN_IER_ERRIE_Pos      (15U)\n#define CAN_IER_ERRIE_Msk      (0x1U << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */\n#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */\n#define CAN_IER_WKUIE_Pos      (16U)\n#define CAN_IER_WKUIE_Msk      (0x1U << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */\n#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */\n#define CAN_IER_SLKIE_Pos      (17U)\n#define CAN_IER_SLKIE_Msk      (0x1U << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */\n#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)\n\n/********************  Bit definition for CAN_ESR register  *******************/\n#define CAN_ESR_EWGF_Pos       (0U)\n#define CAN_ESR_EWGF_Msk       (0x1U << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */\n#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */\n#define CAN_ESR_EPVF_Pos       (1U)\n#define CAN_ESR_EPVF_Msk       (0x1U << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */\n#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */\n#define CAN_ESR_BOFF_Pos       (2U)\n#define CAN_ESR_BOFF_Msk       (0x1U << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */\n#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */\n\n#define CAN_ESR_LEC_Pos        (4U)\n#define CAN_ESR_LEC_Msk        (0x7U << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */\n#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */\n#define CAN_ESR_LEC_0          (0x1U << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */\n#define CAN_ESR_LEC_1          (0x2U << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */\n#define CAN_ESR_LEC_2          (0x4U << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */\n\n#define CAN_ESR_TEC_Pos        (16U)\n#define CAN_ESR_TEC_Msk        (0xFFU << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */\n#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */\n#define CAN_ESR_REC_Pos        (24U)\n#define CAN_ESR_REC_Msk        (0xFFU << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */\n#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */\n\n/*******************  Bit definition for CAN_BTR register  ********************/\n#define CAN_BTR_BRP_Pos        (0U)\n#define CAN_BTR_BRP_Msk        (0x3FFU << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */\n#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */\n#define CAN_BTR_TS1_Pos        (16U)\n#define CAN_BTR_TS1_Msk        (0xFU << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */\n#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */\n#define CAN_BTR_TS1_0          (0x1U << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */\n#define CAN_BTR_TS1_1          (0x2U << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */\n#define CAN_BTR_TS1_2          (0x4U << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */\n#define CAN_BTR_TS1_3          (0x8U << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */\n#define CAN_BTR_TS2_Pos        (20U)\n#define CAN_BTR_TS2_Msk        (0x7U << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */\n#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */\n#define CAN_BTR_TS2_0          (0x1U << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */\n#define CAN_BTR_TS2_1          (0x2U << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */\n#define CAN_BTR_TS2_2          (0x4U << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */\n#define CAN_BTR_SJW_Pos        (24U)\n#define CAN_BTR_SJW_Msk        (0x3U << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */\n#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */\n#define CAN_BTR_SJW_0          (0x1U << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */\n#define CAN_BTR_SJW_1          (0x2U << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */\n#define CAN_BTR_LBKM_Pos       (30U)\n#define CAN_BTR_LBKM_Msk       (0x1U << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */\n#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */\n#define CAN_BTR_SILM_Pos       (31U)\n#define CAN_BTR_SILM_Msk       (0x1U << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */\n#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */\n\n\n/*!<Mailbox registers */\n/******************  Bit definition for CAN_TI0R register  ********************/\n#define CAN_TI0R_TXRQ_Pos      (0U)\n#define CAN_TI0R_TXRQ_Msk      (0x1U << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI0R_RTR_Pos       (1U)\n#define CAN_TI0R_RTR_Msk       (0x1U << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI0R_IDE_Pos       (2U)\n#define CAN_TI0R_IDE_Msk       (0x1U << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI0R_EXID_Pos      (3U)\n#define CAN_TI0R_EXID_Msk      (0x3FFFFU << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI0R_STID_Pos      (21U)\n#define CAN_TI0R_STID_Msk      (0x7FFU << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/******************  Bit definition for CAN_TDT0R register  *******************/\n#define CAN_TDT0R_DLC_Pos      (0U)\n#define CAN_TDT0R_DLC_Msk      (0xFU << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT0R_TGT_Pos      (8U)\n#define CAN_TDT0R_TGT_Msk      (0x1U << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT0R_TIME_Pos     (16U)\n#define CAN_TDT0R_TIME_Msk     (0xFFFFU << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/******************  Bit definition for CAN_TDL0R register  *******************/\n#define CAN_TDL0R_DATA0_Pos    (0U)\n#define CAN_TDL0R_DATA0_Msk    (0xFFU << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL0R_DATA1_Pos    (8U)\n#define CAN_TDL0R_DATA1_Msk    (0xFFU << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL0R_DATA2_Pos    (16U)\n#define CAN_TDL0R_DATA2_Msk    (0xFFU << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL0R_DATA3_Pos    (24U)\n#define CAN_TDL0R_DATA3_Msk    (0xFFU << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/******************  Bit definition for CAN_TDH0R register  *******************/\n#define CAN_TDH0R_DATA4_Pos    (0U)\n#define CAN_TDH0R_DATA4_Msk    (0xFFU << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH0R_DATA5_Pos    (8U)\n#define CAN_TDH0R_DATA5_Msk    (0xFFU << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH0R_DATA6_Pos    (16U)\n#define CAN_TDH0R_DATA6_Msk    (0xFFU << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH0R_DATA7_Pos    (24U)\n#define CAN_TDH0R_DATA7_Msk    (0xFFU << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI1R register  *******************/\n#define CAN_TI1R_TXRQ_Pos      (0U)\n#define CAN_TI1R_TXRQ_Msk      (0x1U << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI1R_RTR_Pos       (1U)\n#define CAN_TI1R_RTR_Msk       (0x1U << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI1R_IDE_Pos       (2U)\n#define CAN_TI1R_IDE_Msk       (0x1U << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI1R_EXID_Pos      (3U)\n#define CAN_TI1R_EXID_Msk      (0x3FFFFU << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI1R_STID_Pos      (21U)\n#define CAN_TI1R_STID_Msk      (0x7FFU << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT1R register  ******************/\n#define CAN_TDT1R_DLC_Pos      (0U)\n#define CAN_TDT1R_DLC_Msk      (0xFU << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT1R_TGT_Pos      (8U)\n#define CAN_TDT1R_TGT_Msk      (0x1U << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT1R_TIME_Pos     (16U)\n#define CAN_TDT1R_TIME_Msk     (0xFFFFU << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL1R register  ******************/\n#define CAN_TDL1R_DATA0_Pos    (0U)\n#define CAN_TDL1R_DATA0_Msk    (0xFFU << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL1R_DATA1_Pos    (8U)\n#define CAN_TDL1R_DATA1_Msk    (0xFFU << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL1R_DATA2_Pos    (16U)\n#define CAN_TDL1R_DATA2_Msk    (0xFFU << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL1R_DATA3_Pos    (24U)\n#define CAN_TDL1R_DATA3_Msk    (0xFFU << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH1R register  ******************/\n#define CAN_TDH1R_DATA4_Pos    (0U)\n#define CAN_TDH1R_DATA4_Msk    (0xFFU << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH1R_DATA5_Pos    (8U)\n#define CAN_TDH1R_DATA5_Msk    (0xFFU << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH1R_DATA6_Pos    (16U)\n#define CAN_TDH1R_DATA6_Msk    (0xFFU << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH1R_DATA7_Pos    (24U)\n#define CAN_TDH1R_DATA7_Msk    (0xFFU << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI2R register  *******************/\n#define CAN_TI2R_TXRQ_Pos      (0U)\n#define CAN_TI2R_TXRQ_Msk      (0x1U << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI2R_RTR_Pos       (1U)\n#define CAN_TI2R_RTR_Msk       (0x1U << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI2R_IDE_Pos       (2U)\n#define CAN_TI2R_IDE_Msk       (0x1U << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI2R_EXID_Pos      (3U)\n#define CAN_TI2R_EXID_Msk      (0x3FFFFU << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_TI2R_STID_Pos      (21U)\n#define CAN_TI2R_STID_Msk      (0x7FFU << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT2R register  ******************/\n#define CAN_TDT2R_DLC_Pos      (0U)\n#define CAN_TDT2R_DLC_Msk      (0xFU << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT2R_TGT_Pos      (8U)\n#define CAN_TDT2R_TGT_Msk      (0x1U << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT2R_TIME_Pos     (16U)\n#define CAN_TDT2R_TIME_Msk     (0xFFFFU << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL2R register  ******************/\n#define CAN_TDL2R_DATA0_Pos    (0U)\n#define CAN_TDL2R_DATA0_Msk    (0xFFU << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL2R_DATA1_Pos    (8U)\n#define CAN_TDL2R_DATA1_Msk    (0xFFU << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL2R_DATA2_Pos    (16U)\n#define CAN_TDL2R_DATA2_Msk    (0xFFU << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL2R_DATA3_Pos    (24U)\n#define CAN_TDL2R_DATA3_Msk    (0xFFU << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH2R register  ******************/\n#define CAN_TDH2R_DATA4_Pos    (0U)\n#define CAN_TDH2R_DATA4_Msk    (0xFFU << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH2R_DATA5_Pos    (8U)\n#define CAN_TDH2R_DATA5_Msk    (0xFFU << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH2R_DATA6_Pos    (16U)\n#define CAN_TDH2R_DATA6_Msk    (0xFFU << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH2R_DATA7_Pos    (24U)\n#define CAN_TDH2R_DATA7_Msk    (0xFFU << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI0R register  *******************/\n#define CAN_RI0R_RTR_Pos       (1U)\n#define CAN_RI0R_RTR_Msk       (0x1U << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI0R_IDE_Pos       (2U)\n#define CAN_RI0R_IDE_Msk       (0x1U << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI0R_EXID_Pos      (3U)\n#define CAN_RI0R_EXID_Msk      (0x3FFFFU << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_RI0R_STID_Pos      (21U)\n#define CAN_RI0R_STID_Msk      (0x7FFU << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT0R register  ******************/\n#define CAN_RDT0R_DLC_Pos      (0U)\n#define CAN_RDT0R_DLC_Msk      (0xFU << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT0R_FMI_Pos      (8U)\n#define CAN_RDT0R_FMI_Msk      (0xFFU << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT0R_TIME_Pos     (16U)\n#define CAN_RDT0R_TIME_Msk     (0xFFFFU << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL0R register  ******************/\n#define CAN_RDL0R_DATA0_Pos    (0U)\n#define CAN_RDL0R_DATA0_Msk    (0xFFU << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL0R_DATA1_Pos    (8U)\n#define CAN_RDL0R_DATA1_Msk    (0xFFU << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL0R_DATA2_Pos    (16U)\n#define CAN_RDL0R_DATA2_Msk    (0xFFU << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL0R_DATA3_Pos    (24U)\n#define CAN_RDL0R_DATA3_Msk    (0xFFU << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH0R register  ******************/\n#define CAN_RDH0R_DATA4_Pos    (0U)\n#define CAN_RDH0R_DATA4_Msk    (0xFFU << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH0R_DATA5_Pos    (8U)\n#define CAN_RDH0R_DATA5_Msk    (0xFFU << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH0R_DATA6_Pos    (16U)\n#define CAN_RDH0R_DATA6_Msk    (0xFFU << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH0R_DATA7_Pos    (24U)\n#define CAN_RDH0R_DATA7_Msk    (0xFFU << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI1R register  *******************/\n#define CAN_RI1R_RTR_Pos       (1U)\n#define CAN_RI1R_RTR_Msk       (0x1U << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI1R_IDE_Pos       (2U)\n#define CAN_RI1R_IDE_Msk       (0x1U << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI1R_EXID_Pos      (3U)\n#define CAN_RI1R_EXID_Msk      (0x3FFFFU << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_RI1R_STID_Pos      (21U)\n#define CAN_RI1R_STID_Msk      (0x7FFU << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT1R register  ******************/\n#define CAN_RDT1R_DLC_Pos      (0U)\n#define CAN_RDT1R_DLC_Msk      (0xFU << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT1R_FMI_Pos      (8U)\n#define CAN_RDT1R_FMI_Msk      (0xFFU << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT1R_TIME_Pos     (16U)\n#define CAN_RDT1R_TIME_Msk     (0xFFFFU << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL1R register  ******************/\n#define CAN_RDL1R_DATA0_Pos    (0U)\n#define CAN_RDL1R_DATA0_Msk    (0xFFU << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL1R_DATA1_Pos    (8U)\n#define CAN_RDL1R_DATA1_Msk    (0xFFU << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL1R_DATA2_Pos    (16U)\n#define CAN_RDL1R_DATA2_Msk    (0xFFU << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL1R_DATA3_Pos    (24U)\n#define CAN_RDL1R_DATA3_Msk    (0xFFU << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH1R register  ******************/\n#define CAN_RDH1R_DATA4_Pos    (0U)\n#define CAN_RDH1R_DATA4_Msk    (0xFFU << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH1R_DATA5_Pos    (8U)\n#define CAN_RDH1R_DATA5_Msk    (0xFFU << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH1R_DATA6_Pos    (16U)\n#define CAN_RDH1R_DATA6_Msk    (0xFFU << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH1R_DATA7_Pos    (24U)\n#define CAN_RDH1R_DATA7_Msk    (0xFFU << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*!<CAN filter registers */\n/*******************  Bit definition for CAN_FMR register  ********************/\n#define CAN_FMR_FINIT_Pos      (0U)\n#define CAN_FMR_FINIT_Msk      (0x1U << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */\n#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */\n#define CAN_FMR_CAN2SB_Pos     (8U)\n#define CAN_FMR_CAN2SB_Msk     (0x3FU << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */\n#define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */\n\n/*******************  Bit definition for CAN_FM1R register  *******************/\n#define CAN_FM1R_FBM_Pos       (0U)\n#define CAN_FM1R_FBM_Msk       (0xFFFFFFFU << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */\n#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */\n#define CAN_FM1R_FBM0_Pos      (0U)\n#define CAN_FM1R_FBM0_Msk      (0x1U << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */\n#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */\n#define CAN_FM1R_FBM1_Pos      (1U)\n#define CAN_FM1R_FBM1_Msk      (0x1U << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */\n#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */\n#define CAN_FM1R_FBM2_Pos      (2U)\n#define CAN_FM1R_FBM2_Msk      (0x1U << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */\n#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */\n#define CAN_FM1R_FBM3_Pos      (3U)\n#define CAN_FM1R_FBM3_Msk      (0x1U << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */\n#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */\n#define CAN_FM1R_FBM4_Pos      (4U)\n#define CAN_FM1R_FBM4_Msk      (0x1U << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */\n#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */\n#define CAN_FM1R_FBM5_Pos      (5U)\n#define CAN_FM1R_FBM5_Msk      (0x1U << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */\n#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */\n#define CAN_FM1R_FBM6_Pos      (6U)\n#define CAN_FM1R_FBM6_Msk      (0x1U << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */\n#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */\n#define CAN_FM1R_FBM7_Pos      (7U)\n#define CAN_FM1R_FBM7_Msk      (0x1U << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */\n#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */\n#define CAN_FM1R_FBM8_Pos      (8U)\n#define CAN_FM1R_FBM8_Msk      (0x1U << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */\n#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */\n#define CAN_FM1R_FBM9_Pos      (9U)\n#define CAN_FM1R_FBM9_Msk      (0x1U << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */\n#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */\n#define CAN_FM1R_FBM10_Pos     (10U)\n#define CAN_FM1R_FBM10_Msk     (0x1U << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */\n#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */\n#define CAN_FM1R_FBM11_Pos     (11U)\n#define CAN_FM1R_FBM11_Msk     (0x1U << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */\n#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */\n#define CAN_FM1R_FBM12_Pos     (12U)\n#define CAN_FM1R_FBM12_Msk     (0x1U << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */\n#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */\n#define CAN_FM1R_FBM13_Pos     (13U)\n#define CAN_FM1R_FBM13_Msk     (0x1U << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */\n#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */\n#define CAN_FM1R_FBM14_Pos     (14U)\n#define CAN_FM1R_FBM14_Msk     (0x1U << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */\n#define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */\n#define CAN_FM1R_FBM15_Pos     (15U)\n#define CAN_FM1R_FBM15_Msk     (0x1U << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */\n#define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */\n#define CAN_FM1R_FBM16_Pos     (16U)\n#define CAN_FM1R_FBM16_Msk     (0x1U << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */\n#define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */\n#define CAN_FM1R_FBM17_Pos     (17U)\n#define CAN_FM1R_FBM17_Msk     (0x1U << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */\n#define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */\n#define CAN_FM1R_FBM18_Pos     (18U)\n#define CAN_FM1R_FBM18_Msk     (0x1U << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */\n#define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */\n#define CAN_FM1R_FBM19_Pos     (19U)\n#define CAN_FM1R_FBM19_Msk     (0x1U << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */\n#define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */\n#define CAN_FM1R_FBM20_Pos     (20U)\n#define CAN_FM1R_FBM20_Msk     (0x1U << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */\n#define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */\n#define CAN_FM1R_FBM21_Pos     (21U)\n#define CAN_FM1R_FBM21_Msk     (0x1U << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */\n#define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */\n#define CAN_FM1R_FBM22_Pos     (22U)\n#define CAN_FM1R_FBM22_Msk     (0x1U << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */\n#define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */\n#define CAN_FM1R_FBM23_Pos     (23U)\n#define CAN_FM1R_FBM23_Msk     (0x1U << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */\n#define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */\n#define CAN_FM1R_FBM24_Pos     (24U)\n#define CAN_FM1R_FBM24_Msk     (0x1U << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */\n#define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */\n#define CAN_FM1R_FBM25_Pos     (25U)\n#define CAN_FM1R_FBM25_Msk     (0x1U << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */\n#define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */\n#define CAN_FM1R_FBM26_Pos     (26U)\n#define CAN_FM1R_FBM26_Msk     (0x1U << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */\n#define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */\n#define CAN_FM1R_FBM27_Pos     (27U)\n#define CAN_FM1R_FBM27_Msk     (0x1U << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */\n#define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */\n\n/*******************  Bit definition for CAN_FS1R register  *******************/\n#define CAN_FS1R_FSC_Pos       (0U)\n#define CAN_FS1R_FSC_Msk       (0xFFFFFFFU << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */\n#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */\n#define CAN_FS1R_FSC0_Pos      (0U)\n#define CAN_FS1R_FSC0_Msk      (0x1U << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */\n#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */\n#define CAN_FS1R_FSC1_Pos      (1U)\n#define CAN_FS1R_FSC1_Msk      (0x1U << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */\n#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */\n#define CAN_FS1R_FSC2_Pos      (2U)\n#define CAN_FS1R_FSC2_Msk      (0x1U << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */\n#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */\n#define CAN_FS1R_FSC3_Pos      (3U)\n#define CAN_FS1R_FSC3_Msk      (0x1U << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */\n#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */\n#define CAN_FS1R_FSC4_Pos      (4U)\n#define CAN_FS1R_FSC4_Msk      (0x1U << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */\n#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */\n#define CAN_FS1R_FSC5_Pos      (5U)\n#define CAN_FS1R_FSC5_Msk      (0x1U << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */\n#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */\n#define CAN_FS1R_FSC6_Pos      (6U)\n#define CAN_FS1R_FSC6_Msk      (0x1U << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */\n#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */\n#define CAN_FS1R_FSC7_Pos      (7U)\n#define CAN_FS1R_FSC7_Msk      (0x1U << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */\n#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */\n#define CAN_FS1R_FSC8_Pos      (8U)\n#define CAN_FS1R_FSC8_Msk      (0x1U << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */\n#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */\n#define CAN_FS1R_FSC9_Pos      (9U)\n#define CAN_FS1R_FSC9_Msk      (0x1U << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */\n#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */\n#define CAN_FS1R_FSC10_Pos     (10U)\n#define CAN_FS1R_FSC10_Msk     (0x1U << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */\n#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */\n#define CAN_FS1R_FSC11_Pos     (11U)\n#define CAN_FS1R_FSC11_Msk     (0x1U << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */\n#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */\n#define CAN_FS1R_FSC12_Pos     (12U)\n#define CAN_FS1R_FSC12_Msk     (0x1U << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */\n#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */\n#define CAN_FS1R_FSC13_Pos     (13U)\n#define CAN_FS1R_FSC13_Msk     (0x1U << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */\n#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */\n#define CAN_FS1R_FSC14_Pos     (14U)\n#define CAN_FS1R_FSC14_Msk     (0x1U << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */\n#define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */\n#define CAN_FS1R_FSC15_Pos     (15U)\n#define CAN_FS1R_FSC15_Msk     (0x1U << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */\n#define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */\n#define CAN_FS1R_FSC16_Pos     (16U)\n#define CAN_FS1R_FSC16_Msk     (0x1U << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */\n#define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */\n#define CAN_FS1R_FSC17_Pos     (17U)\n#define CAN_FS1R_FSC17_Msk     (0x1U << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */\n#define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */\n#define CAN_FS1R_FSC18_Pos     (18U)\n#define CAN_FS1R_FSC18_Msk     (0x1U << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */\n#define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */\n#define CAN_FS1R_FSC19_Pos     (19U)\n#define CAN_FS1R_FSC19_Msk     (0x1U << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */\n#define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */\n#define CAN_FS1R_FSC20_Pos     (20U)\n#define CAN_FS1R_FSC20_Msk     (0x1U << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */\n#define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */\n#define CAN_FS1R_FSC21_Pos     (21U)\n#define CAN_FS1R_FSC21_Msk     (0x1U << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */\n#define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */\n#define CAN_FS1R_FSC22_Pos     (22U)\n#define CAN_FS1R_FSC22_Msk     (0x1U << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */\n#define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */\n#define CAN_FS1R_FSC23_Pos     (23U)\n#define CAN_FS1R_FSC23_Msk     (0x1U << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */\n#define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */\n#define CAN_FS1R_FSC24_Pos     (24U)\n#define CAN_FS1R_FSC24_Msk     (0x1U << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */\n#define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */\n#define CAN_FS1R_FSC25_Pos     (25U)\n#define CAN_FS1R_FSC25_Msk     (0x1U << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */\n#define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */\n#define CAN_FS1R_FSC26_Pos     (26U)\n#define CAN_FS1R_FSC26_Msk     (0x1U << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */\n#define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */\n#define CAN_FS1R_FSC27_Pos     (27U)\n#define CAN_FS1R_FSC27_Msk     (0x1U << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */\n#define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */\n\n/******************  Bit definition for CAN_FFA1R register  *******************/\n#define CAN_FFA1R_FFA_Pos      (0U)\n#define CAN_FFA1R_FFA_Msk      (0xFFFFFFFU << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */\n#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */\n#define CAN_FFA1R_FFA0_Pos     (0U)\n#define CAN_FFA1R_FFA0_Msk     (0x1U << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */\n#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */\n#define CAN_FFA1R_FFA1_Pos     (1U)\n#define CAN_FFA1R_FFA1_Msk     (0x1U << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */\n#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */\n#define CAN_FFA1R_FFA2_Pos     (2U)\n#define CAN_FFA1R_FFA2_Msk     (0x1U << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */\n#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */\n#define CAN_FFA1R_FFA3_Pos     (3U)\n#define CAN_FFA1R_FFA3_Msk     (0x1U << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */\n#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */\n#define CAN_FFA1R_FFA4_Pos     (4U)\n#define CAN_FFA1R_FFA4_Msk     (0x1U << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */\n#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */\n#define CAN_FFA1R_FFA5_Pos     (5U)\n#define CAN_FFA1R_FFA5_Msk     (0x1U << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */\n#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */\n#define CAN_FFA1R_FFA6_Pos     (6U)\n#define CAN_FFA1R_FFA6_Msk     (0x1U << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */\n#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */\n#define CAN_FFA1R_FFA7_Pos     (7U)\n#define CAN_FFA1R_FFA7_Msk     (0x1U << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */\n#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */\n#define CAN_FFA1R_FFA8_Pos     (8U)\n#define CAN_FFA1R_FFA8_Msk     (0x1U << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */\n#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */\n#define CAN_FFA1R_FFA9_Pos     (9U)\n#define CAN_FFA1R_FFA9_Msk     (0x1U << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */\n#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */\n#define CAN_FFA1R_FFA10_Pos    (10U)\n#define CAN_FFA1R_FFA10_Msk    (0x1U << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */\n#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */\n#define CAN_FFA1R_FFA11_Pos    (11U)\n#define CAN_FFA1R_FFA11_Msk    (0x1U << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */\n#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */\n#define CAN_FFA1R_FFA12_Pos    (12U)\n#define CAN_FFA1R_FFA12_Msk    (0x1U << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */\n#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */\n#define CAN_FFA1R_FFA13_Pos    (13U)\n#define CAN_FFA1R_FFA13_Msk    (0x1U << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */\n#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */\n#define CAN_FFA1R_FFA14_Pos    (14U)\n#define CAN_FFA1R_FFA14_Msk    (0x1U << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */\n#define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */\n#define CAN_FFA1R_FFA15_Pos    (15U)\n#define CAN_FFA1R_FFA15_Msk    (0x1U << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */\n#define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */\n#define CAN_FFA1R_FFA16_Pos    (16U)\n#define CAN_FFA1R_FFA16_Msk    (0x1U << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */\n#define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */\n#define CAN_FFA1R_FFA17_Pos    (17U)\n#define CAN_FFA1R_FFA17_Msk    (0x1U << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */\n#define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */\n#define CAN_FFA1R_FFA18_Pos    (18U)\n#define CAN_FFA1R_FFA18_Msk    (0x1U << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */\n#define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */\n#define CAN_FFA1R_FFA19_Pos    (19U)\n#define CAN_FFA1R_FFA19_Msk    (0x1U << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */\n#define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */\n#define CAN_FFA1R_FFA20_Pos    (20U)\n#define CAN_FFA1R_FFA20_Msk    (0x1U << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */\n#define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */\n#define CAN_FFA1R_FFA21_Pos    (21U)\n#define CAN_FFA1R_FFA21_Msk    (0x1U << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */\n#define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */\n#define CAN_FFA1R_FFA22_Pos    (22U)\n#define CAN_FFA1R_FFA22_Msk    (0x1U << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */\n#define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */\n#define CAN_FFA1R_FFA23_Pos    (23U)\n#define CAN_FFA1R_FFA23_Msk    (0x1U << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */\n#define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */\n#define CAN_FFA1R_FFA24_Pos    (24U)\n#define CAN_FFA1R_FFA24_Msk    (0x1U << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */\n#define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */\n#define CAN_FFA1R_FFA25_Pos    (25U)\n#define CAN_FFA1R_FFA25_Msk    (0x1U << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */\n#define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */\n#define CAN_FFA1R_FFA26_Pos    (26U)\n#define CAN_FFA1R_FFA26_Msk    (0x1U << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */\n#define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */\n#define CAN_FFA1R_FFA27_Pos    (27U)\n#define CAN_FFA1R_FFA27_Msk    (0x1U << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */\n#define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */\n\n/*******************  Bit definition for CAN_FA1R register  *******************/\n#define CAN_FA1R_FACT_Pos      (0U)\n#define CAN_FA1R_FACT_Msk      (0xFFFFFFFU << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */\n#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */\n#define CAN_FA1R_FACT0_Pos     (0U)\n#define CAN_FA1R_FACT0_Msk     (0x1U << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */\n#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */\n#define CAN_FA1R_FACT1_Pos     (1U)\n#define CAN_FA1R_FACT1_Msk     (0x1U << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */\n#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */\n#define CAN_FA1R_FACT2_Pos     (2U)\n#define CAN_FA1R_FACT2_Msk     (0x1U << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */\n#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */\n#define CAN_FA1R_FACT3_Pos     (3U)\n#define CAN_FA1R_FACT3_Msk     (0x1U << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */\n#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */\n#define CAN_FA1R_FACT4_Pos     (4U)\n#define CAN_FA1R_FACT4_Msk     (0x1U << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */\n#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */\n#define CAN_FA1R_FACT5_Pos     (5U)\n#define CAN_FA1R_FACT5_Msk     (0x1U << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */\n#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */\n#define CAN_FA1R_FACT6_Pos     (6U)\n#define CAN_FA1R_FACT6_Msk     (0x1U << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */\n#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */\n#define CAN_FA1R_FACT7_Pos     (7U)\n#define CAN_FA1R_FACT7_Msk     (0x1U << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */\n#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */\n#define CAN_FA1R_FACT8_Pos     (8U)\n#define CAN_FA1R_FACT8_Msk     (0x1U << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */\n#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */\n#define CAN_FA1R_FACT9_Pos     (9U)\n#define CAN_FA1R_FACT9_Msk     (0x1U << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */\n#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */\n#define CAN_FA1R_FACT10_Pos    (10U)\n#define CAN_FA1R_FACT10_Msk    (0x1U << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */\n#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */\n#define CAN_FA1R_FACT11_Pos    (11U)\n#define CAN_FA1R_FACT11_Msk    (0x1U << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */\n#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */\n#define CAN_FA1R_FACT12_Pos    (12U)\n#define CAN_FA1R_FACT12_Msk    (0x1U << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */\n#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */\n#define CAN_FA1R_FACT13_Pos    (13U)\n#define CAN_FA1R_FACT13_Msk    (0x1U << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */\n#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */\n#define CAN_FA1R_FACT14_Pos    (14U)\n#define CAN_FA1R_FACT14_Msk    (0x1U << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */\n#define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */\n#define CAN_FA1R_FACT15_Pos    (15U)\n#define CAN_FA1R_FACT15_Msk    (0x1U << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */\n#define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */\n#define CAN_FA1R_FACT16_Pos    (16U)\n#define CAN_FA1R_FACT16_Msk    (0x1U << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */\n#define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */\n#define CAN_FA1R_FACT17_Pos    (17U)\n#define CAN_FA1R_FACT17_Msk    (0x1U << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */\n#define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */\n#define CAN_FA1R_FACT18_Pos    (18U)\n#define CAN_FA1R_FACT18_Msk    (0x1U << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */\n#define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */\n#define CAN_FA1R_FACT19_Pos    (19U)\n#define CAN_FA1R_FACT19_Msk    (0x1U << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */\n#define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */\n#define CAN_FA1R_FACT20_Pos    (20U)\n#define CAN_FA1R_FACT20_Msk    (0x1U << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */\n#define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */\n#define CAN_FA1R_FACT21_Pos    (21U)\n#define CAN_FA1R_FACT21_Msk    (0x1U << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */\n#define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */\n#define CAN_FA1R_FACT22_Pos    (22U)\n#define CAN_FA1R_FACT22_Msk    (0x1U << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */\n#define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */\n#define CAN_FA1R_FACT23_Pos    (23U)\n#define CAN_FA1R_FACT23_Msk    (0x1U << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */\n#define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */\n#define CAN_FA1R_FACT24_Pos    (24U)\n#define CAN_FA1R_FACT24_Msk    (0x1U << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */\n#define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */\n#define CAN_FA1R_FACT25_Pos    (25U)\n#define CAN_FA1R_FACT25_Msk    (0x1U << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */\n#define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */\n#define CAN_FA1R_FACT26_Pos    (26U)\n#define CAN_FA1R_FACT26_Msk    (0x1U << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */\n#define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */\n#define CAN_FA1R_FACT27_Pos    (27U)\n#define CAN_FA1R_FACT27_Msk    (0x1U << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */\n#define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */\n\n\n/*******************  Bit definition for CAN_F0R1 register  *******************/\n#define CAN_F0R1_FB0_Pos       (0U)\n#define CAN_F0R1_FB0_Msk       (0x1U << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R1_FB1_Pos       (1U)\n#define CAN_F0R1_FB1_Msk       (0x1U << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R1_FB2_Pos       (2U)\n#define CAN_F0R1_FB2_Msk       (0x1U << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R1_FB3_Pos       (3U)\n#define CAN_F0R1_FB3_Msk       (0x1U << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R1_FB4_Pos       (4U)\n#define CAN_F0R1_FB4_Msk       (0x1U << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R1_FB5_Pos       (5U)\n#define CAN_F0R1_FB5_Msk       (0x1U << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R1_FB6_Pos       (6U)\n#define CAN_F0R1_FB6_Msk       (0x1U << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R1_FB7_Pos       (7U)\n#define CAN_F0R1_FB7_Msk       (0x1U << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R1_FB8_Pos       (8U)\n#define CAN_F0R1_FB8_Msk       (0x1U << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R1_FB9_Pos       (9U)\n#define CAN_F0R1_FB9_Msk       (0x1U << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R1_FB10_Pos      (10U)\n#define CAN_F0R1_FB10_Msk      (0x1U << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R1_FB11_Pos      (11U)\n#define CAN_F0R1_FB11_Msk      (0x1U << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R1_FB12_Pos      (12U)\n#define CAN_F0R1_FB12_Msk      (0x1U << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R1_FB13_Pos      (13U)\n#define CAN_F0R1_FB13_Msk      (0x1U << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R1_FB14_Pos      (14U)\n#define CAN_F0R1_FB14_Msk      (0x1U << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R1_FB15_Pos      (15U)\n#define CAN_F0R1_FB15_Msk      (0x1U << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R1_FB16_Pos      (16U)\n#define CAN_F0R1_FB16_Msk      (0x1U << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R1_FB17_Pos      (17U)\n#define CAN_F0R1_FB17_Msk      (0x1U << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R1_FB18_Pos      (18U)\n#define CAN_F0R1_FB18_Msk      (0x1U << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R1_FB19_Pos      (19U)\n#define CAN_F0R1_FB19_Msk      (0x1U << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R1_FB20_Pos      (20U)\n#define CAN_F0R1_FB20_Msk      (0x1U << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R1_FB21_Pos      (21U)\n#define CAN_F0R1_FB21_Msk      (0x1U << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R1_FB22_Pos      (22U)\n#define CAN_F0R1_FB22_Msk      (0x1U << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R1_FB23_Pos      (23U)\n#define CAN_F0R1_FB23_Msk      (0x1U << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R1_FB24_Pos      (24U)\n#define CAN_F0R1_FB24_Msk      (0x1U << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R1_FB25_Pos      (25U)\n#define CAN_F0R1_FB25_Msk      (0x1U << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R1_FB26_Pos      (26U)\n#define CAN_F0R1_FB26_Msk      (0x1U << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R1_FB27_Pos      (27U)\n#define CAN_F0R1_FB27_Msk      (0x1U << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R1_FB28_Pos      (28U)\n#define CAN_F0R1_FB28_Msk      (0x1U << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R1_FB29_Pos      (29U)\n#define CAN_F0R1_FB29_Msk      (0x1U << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R1_FB30_Pos      (30U)\n#define CAN_F0R1_FB30_Msk      (0x1U << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R1_FB31_Pos      (31U)\n#define CAN_F0R1_FB31_Msk      (0x1U << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R1 register  *******************/\n#define CAN_F1R1_FB0_Pos       (0U)\n#define CAN_F1R1_FB0_Msk       (0x1U << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R1_FB1_Pos       (1U)\n#define CAN_F1R1_FB1_Msk       (0x1U << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R1_FB2_Pos       (2U)\n#define CAN_F1R1_FB2_Msk       (0x1U << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R1_FB3_Pos       (3U)\n#define CAN_F1R1_FB3_Msk       (0x1U << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R1_FB4_Pos       (4U)\n#define CAN_F1R1_FB4_Msk       (0x1U << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R1_FB5_Pos       (5U)\n#define CAN_F1R1_FB5_Msk       (0x1U << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R1_FB6_Pos       (6U)\n#define CAN_F1R1_FB6_Msk       (0x1U << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R1_FB7_Pos       (7U)\n#define CAN_F1R1_FB7_Msk       (0x1U << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R1_FB8_Pos       (8U)\n#define CAN_F1R1_FB8_Msk       (0x1U << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R1_FB9_Pos       (9U)\n#define CAN_F1R1_FB9_Msk       (0x1U << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R1_FB10_Pos      (10U)\n#define CAN_F1R1_FB10_Msk      (0x1U << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R1_FB11_Pos      (11U)\n#define CAN_F1R1_FB11_Msk      (0x1U << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R1_FB12_Pos      (12U)\n#define CAN_F1R1_FB12_Msk      (0x1U << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R1_FB13_Pos      (13U)\n#define CAN_F1R1_FB13_Msk      (0x1U << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R1_FB14_Pos      (14U)\n#define CAN_F1R1_FB14_Msk      (0x1U << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R1_FB15_Pos      (15U)\n#define CAN_F1R1_FB15_Msk      (0x1U << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R1_FB16_Pos      (16U)\n#define CAN_F1R1_FB16_Msk      (0x1U << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R1_FB17_Pos      (17U)\n#define CAN_F1R1_FB17_Msk      (0x1U << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R1_FB18_Pos      (18U)\n#define CAN_F1R1_FB18_Msk      (0x1U << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R1_FB19_Pos      (19U)\n#define CAN_F1R1_FB19_Msk      (0x1U << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R1_FB20_Pos      (20U)\n#define CAN_F1R1_FB20_Msk      (0x1U << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R1_FB21_Pos      (21U)\n#define CAN_F1R1_FB21_Msk      (0x1U << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R1_FB22_Pos      (22U)\n#define CAN_F1R1_FB22_Msk      (0x1U << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R1_FB23_Pos      (23U)\n#define CAN_F1R1_FB23_Msk      (0x1U << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R1_FB24_Pos      (24U)\n#define CAN_F1R1_FB24_Msk      (0x1U << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R1_FB25_Pos      (25U)\n#define CAN_F1R1_FB25_Msk      (0x1U << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R1_FB26_Pos      (26U)\n#define CAN_F1R1_FB26_Msk      (0x1U << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R1_FB27_Pos      (27U)\n#define CAN_F1R1_FB27_Msk      (0x1U << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R1_FB28_Pos      (28U)\n#define CAN_F1R1_FB28_Msk      (0x1U << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R1_FB29_Pos      (29U)\n#define CAN_F1R1_FB29_Msk      (0x1U << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R1_FB30_Pos      (30U)\n#define CAN_F1R1_FB30_Msk      (0x1U << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R1_FB31_Pos      (31U)\n#define CAN_F1R1_FB31_Msk      (0x1U << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R1 register  *******************/\n#define CAN_F2R1_FB0_Pos       (0U)\n#define CAN_F2R1_FB0_Msk       (0x1U << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R1_FB1_Pos       (1U)\n#define CAN_F2R1_FB1_Msk       (0x1U << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R1_FB2_Pos       (2U)\n#define CAN_F2R1_FB2_Msk       (0x1U << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R1_FB3_Pos       (3U)\n#define CAN_F2R1_FB3_Msk       (0x1U << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R1_FB4_Pos       (4U)\n#define CAN_F2R1_FB4_Msk       (0x1U << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R1_FB5_Pos       (5U)\n#define CAN_F2R1_FB5_Msk       (0x1U << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R1_FB6_Pos       (6U)\n#define CAN_F2R1_FB6_Msk       (0x1U << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R1_FB7_Pos       (7U)\n#define CAN_F2R1_FB7_Msk       (0x1U << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R1_FB8_Pos       (8U)\n#define CAN_F2R1_FB8_Msk       (0x1U << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R1_FB9_Pos       (9U)\n#define CAN_F2R1_FB9_Msk       (0x1U << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R1_FB10_Pos      (10U)\n#define CAN_F2R1_FB10_Msk      (0x1U << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R1_FB11_Pos      (11U)\n#define CAN_F2R1_FB11_Msk      (0x1U << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R1_FB12_Pos      (12U)\n#define CAN_F2R1_FB12_Msk      (0x1U << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R1_FB13_Pos      (13U)\n#define CAN_F2R1_FB13_Msk      (0x1U << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R1_FB14_Pos      (14U)\n#define CAN_F2R1_FB14_Msk      (0x1U << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R1_FB15_Pos      (15U)\n#define CAN_F2R1_FB15_Msk      (0x1U << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R1_FB16_Pos      (16U)\n#define CAN_F2R1_FB16_Msk      (0x1U << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R1_FB17_Pos      (17U)\n#define CAN_F2R1_FB17_Msk      (0x1U << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R1_FB18_Pos      (18U)\n#define CAN_F2R1_FB18_Msk      (0x1U << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R1_FB19_Pos      (19U)\n#define CAN_F2R1_FB19_Msk      (0x1U << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R1_FB20_Pos      (20U)\n#define CAN_F2R1_FB20_Msk      (0x1U << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R1_FB21_Pos      (21U)\n#define CAN_F2R1_FB21_Msk      (0x1U << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R1_FB22_Pos      (22U)\n#define CAN_F2R1_FB22_Msk      (0x1U << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R1_FB23_Pos      (23U)\n#define CAN_F2R1_FB23_Msk      (0x1U << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R1_FB24_Pos      (24U)\n#define CAN_F2R1_FB24_Msk      (0x1U << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R1_FB25_Pos      (25U)\n#define CAN_F2R1_FB25_Msk      (0x1U << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R1_FB26_Pos      (26U)\n#define CAN_F2R1_FB26_Msk      (0x1U << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R1_FB27_Pos      (27U)\n#define CAN_F2R1_FB27_Msk      (0x1U << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R1_FB28_Pos      (28U)\n#define CAN_F2R1_FB28_Msk      (0x1U << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R1_FB29_Pos      (29U)\n#define CAN_F2R1_FB29_Msk      (0x1U << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R1_FB30_Pos      (30U)\n#define CAN_F2R1_FB30_Msk      (0x1U << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R1_FB31_Pos      (31U)\n#define CAN_F2R1_FB31_Msk      (0x1U << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R1 register  *******************/\n#define CAN_F3R1_FB0_Pos       (0U)\n#define CAN_F3R1_FB0_Msk       (0x1U << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R1_FB1_Pos       (1U)\n#define CAN_F3R1_FB1_Msk       (0x1U << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R1_FB2_Pos       (2U)\n#define CAN_F3R1_FB2_Msk       (0x1U << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R1_FB3_Pos       (3U)\n#define CAN_F3R1_FB3_Msk       (0x1U << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R1_FB4_Pos       (4U)\n#define CAN_F3R1_FB4_Msk       (0x1U << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R1_FB5_Pos       (5U)\n#define CAN_F3R1_FB5_Msk       (0x1U << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R1_FB6_Pos       (6U)\n#define CAN_F3R1_FB6_Msk       (0x1U << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R1_FB7_Pos       (7U)\n#define CAN_F3R1_FB7_Msk       (0x1U << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R1_FB8_Pos       (8U)\n#define CAN_F3R1_FB8_Msk       (0x1U << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R1_FB9_Pos       (9U)\n#define CAN_F3R1_FB9_Msk       (0x1U << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R1_FB10_Pos      (10U)\n#define CAN_F3R1_FB10_Msk      (0x1U << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R1_FB11_Pos      (11U)\n#define CAN_F3R1_FB11_Msk      (0x1U << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R1_FB12_Pos      (12U)\n#define CAN_F3R1_FB12_Msk      (0x1U << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R1_FB13_Pos      (13U)\n#define CAN_F3R1_FB13_Msk      (0x1U << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R1_FB14_Pos      (14U)\n#define CAN_F3R1_FB14_Msk      (0x1U << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R1_FB15_Pos      (15U)\n#define CAN_F3R1_FB15_Msk      (0x1U << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R1_FB16_Pos      (16U)\n#define CAN_F3R1_FB16_Msk      (0x1U << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R1_FB17_Pos      (17U)\n#define CAN_F3R1_FB17_Msk      (0x1U << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R1_FB18_Pos      (18U)\n#define CAN_F3R1_FB18_Msk      (0x1U << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R1_FB19_Pos      (19U)\n#define CAN_F3R1_FB19_Msk      (0x1U << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R1_FB20_Pos      (20U)\n#define CAN_F3R1_FB20_Msk      (0x1U << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R1_FB21_Pos      (21U)\n#define CAN_F3R1_FB21_Msk      (0x1U << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R1_FB22_Pos      (22U)\n#define CAN_F3R1_FB22_Msk      (0x1U << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R1_FB23_Pos      (23U)\n#define CAN_F3R1_FB23_Msk      (0x1U << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R1_FB24_Pos      (24U)\n#define CAN_F3R1_FB24_Msk      (0x1U << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R1_FB25_Pos      (25U)\n#define CAN_F3R1_FB25_Msk      (0x1U << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R1_FB26_Pos      (26U)\n#define CAN_F3R1_FB26_Msk      (0x1U << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R1_FB27_Pos      (27U)\n#define CAN_F3R1_FB27_Msk      (0x1U << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R1_FB28_Pos      (28U)\n#define CAN_F3R1_FB28_Msk      (0x1U << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R1_FB29_Pos      (29U)\n#define CAN_F3R1_FB29_Msk      (0x1U << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R1_FB30_Pos      (30U)\n#define CAN_F3R1_FB30_Msk      (0x1U << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R1_FB31_Pos      (31U)\n#define CAN_F3R1_FB31_Msk      (0x1U << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R1 register  *******************/\n#define CAN_F4R1_FB0_Pos       (0U)\n#define CAN_F4R1_FB0_Msk       (0x1U << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R1_FB1_Pos       (1U)\n#define CAN_F4R1_FB1_Msk       (0x1U << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R1_FB2_Pos       (2U)\n#define CAN_F4R1_FB2_Msk       (0x1U << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R1_FB3_Pos       (3U)\n#define CAN_F4R1_FB3_Msk       (0x1U << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R1_FB4_Pos       (4U)\n#define CAN_F4R1_FB4_Msk       (0x1U << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R1_FB5_Pos       (5U)\n#define CAN_F4R1_FB5_Msk       (0x1U << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R1_FB6_Pos       (6U)\n#define CAN_F4R1_FB6_Msk       (0x1U << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R1_FB7_Pos       (7U)\n#define CAN_F4R1_FB7_Msk       (0x1U << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R1_FB8_Pos       (8U)\n#define CAN_F4R1_FB8_Msk       (0x1U << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R1_FB9_Pos       (9U)\n#define CAN_F4R1_FB9_Msk       (0x1U << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R1_FB10_Pos      (10U)\n#define CAN_F4R1_FB10_Msk      (0x1U << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R1_FB11_Pos      (11U)\n#define CAN_F4R1_FB11_Msk      (0x1U << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R1_FB12_Pos      (12U)\n#define CAN_F4R1_FB12_Msk      (0x1U << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R1_FB13_Pos      (13U)\n#define CAN_F4R1_FB13_Msk      (0x1U << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R1_FB14_Pos      (14U)\n#define CAN_F4R1_FB14_Msk      (0x1U << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R1_FB15_Pos      (15U)\n#define CAN_F4R1_FB15_Msk      (0x1U << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R1_FB16_Pos      (16U)\n#define CAN_F4R1_FB16_Msk      (0x1U << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R1_FB17_Pos      (17U)\n#define CAN_F4R1_FB17_Msk      (0x1U << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R1_FB18_Pos      (18U)\n#define CAN_F4R1_FB18_Msk      (0x1U << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R1_FB19_Pos      (19U)\n#define CAN_F4R1_FB19_Msk      (0x1U << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R1_FB20_Pos      (20U)\n#define CAN_F4R1_FB20_Msk      (0x1U << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R1_FB21_Pos      (21U)\n#define CAN_F4R1_FB21_Msk      (0x1U << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R1_FB22_Pos      (22U)\n#define CAN_F4R1_FB22_Msk      (0x1U << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R1_FB23_Pos      (23U)\n#define CAN_F4R1_FB23_Msk      (0x1U << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R1_FB24_Pos      (24U)\n#define CAN_F4R1_FB24_Msk      (0x1U << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R1_FB25_Pos      (25U)\n#define CAN_F4R1_FB25_Msk      (0x1U << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R1_FB26_Pos      (26U)\n#define CAN_F4R1_FB26_Msk      (0x1U << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R1_FB27_Pos      (27U)\n#define CAN_F4R1_FB27_Msk      (0x1U << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R1_FB28_Pos      (28U)\n#define CAN_F4R1_FB28_Msk      (0x1U << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R1_FB29_Pos      (29U)\n#define CAN_F4R1_FB29_Msk      (0x1U << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R1_FB30_Pos      (30U)\n#define CAN_F4R1_FB30_Msk      (0x1U << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R1_FB31_Pos      (31U)\n#define CAN_F4R1_FB31_Msk      (0x1U << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R1 register  *******************/\n#define CAN_F5R1_FB0_Pos       (0U)\n#define CAN_F5R1_FB0_Msk       (0x1U << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R1_FB1_Pos       (1U)\n#define CAN_F5R1_FB1_Msk       (0x1U << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R1_FB2_Pos       (2U)\n#define CAN_F5R1_FB2_Msk       (0x1U << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R1_FB3_Pos       (3U)\n#define CAN_F5R1_FB3_Msk       (0x1U << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R1_FB4_Pos       (4U)\n#define CAN_F5R1_FB4_Msk       (0x1U << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R1_FB5_Pos       (5U)\n#define CAN_F5R1_FB5_Msk       (0x1U << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R1_FB6_Pos       (6U)\n#define CAN_F5R1_FB6_Msk       (0x1U << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R1_FB7_Pos       (7U)\n#define CAN_F5R1_FB7_Msk       (0x1U << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R1_FB8_Pos       (8U)\n#define CAN_F5R1_FB8_Msk       (0x1U << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R1_FB9_Pos       (9U)\n#define CAN_F5R1_FB9_Msk       (0x1U << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R1_FB10_Pos      (10U)\n#define CAN_F5R1_FB10_Msk      (0x1U << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R1_FB11_Pos      (11U)\n#define CAN_F5R1_FB11_Msk      (0x1U << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R1_FB12_Pos      (12U)\n#define CAN_F5R1_FB12_Msk      (0x1U << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R1_FB13_Pos      (13U)\n#define CAN_F5R1_FB13_Msk      (0x1U << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R1_FB14_Pos      (14U)\n#define CAN_F5R1_FB14_Msk      (0x1U << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R1_FB15_Pos      (15U)\n#define CAN_F5R1_FB15_Msk      (0x1U << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R1_FB16_Pos      (16U)\n#define CAN_F5R1_FB16_Msk      (0x1U << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R1_FB17_Pos      (17U)\n#define CAN_F5R1_FB17_Msk      (0x1U << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R1_FB18_Pos      (18U)\n#define CAN_F5R1_FB18_Msk      (0x1U << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R1_FB19_Pos      (19U)\n#define CAN_F5R1_FB19_Msk      (0x1U << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R1_FB20_Pos      (20U)\n#define CAN_F5R1_FB20_Msk      (0x1U << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R1_FB21_Pos      (21U)\n#define CAN_F5R1_FB21_Msk      (0x1U << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R1_FB22_Pos      (22U)\n#define CAN_F5R1_FB22_Msk      (0x1U << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R1_FB23_Pos      (23U)\n#define CAN_F5R1_FB23_Msk      (0x1U << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R1_FB24_Pos      (24U)\n#define CAN_F5R1_FB24_Msk      (0x1U << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R1_FB25_Pos      (25U)\n#define CAN_F5R1_FB25_Msk      (0x1U << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R1_FB26_Pos      (26U)\n#define CAN_F5R1_FB26_Msk      (0x1U << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R1_FB27_Pos      (27U)\n#define CAN_F5R1_FB27_Msk      (0x1U << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R1_FB28_Pos      (28U)\n#define CAN_F5R1_FB28_Msk      (0x1U << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R1_FB29_Pos      (29U)\n#define CAN_F5R1_FB29_Msk      (0x1U << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R1_FB30_Pos      (30U)\n#define CAN_F5R1_FB30_Msk      (0x1U << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R1_FB31_Pos      (31U)\n#define CAN_F5R1_FB31_Msk      (0x1U << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R1 register  *******************/\n#define CAN_F6R1_FB0_Pos       (0U)\n#define CAN_F6R1_FB0_Msk       (0x1U << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R1_FB1_Pos       (1U)\n#define CAN_F6R1_FB1_Msk       (0x1U << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R1_FB2_Pos       (2U)\n#define CAN_F6R1_FB2_Msk       (0x1U << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R1_FB3_Pos       (3U)\n#define CAN_F6R1_FB3_Msk       (0x1U << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R1_FB4_Pos       (4U)\n#define CAN_F6R1_FB4_Msk       (0x1U << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R1_FB5_Pos       (5U)\n#define CAN_F6R1_FB5_Msk       (0x1U << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R1_FB6_Pos       (6U)\n#define CAN_F6R1_FB6_Msk       (0x1U << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R1_FB7_Pos       (7U)\n#define CAN_F6R1_FB7_Msk       (0x1U << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R1_FB8_Pos       (8U)\n#define CAN_F6R1_FB8_Msk       (0x1U << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R1_FB9_Pos       (9U)\n#define CAN_F6R1_FB9_Msk       (0x1U << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R1_FB10_Pos      (10U)\n#define CAN_F6R1_FB10_Msk      (0x1U << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R1_FB11_Pos      (11U)\n#define CAN_F6R1_FB11_Msk      (0x1U << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R1_FB12_Pos      (12U)\n#define CAN_F6R1_FB12_Msk      (0x1U << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R1_FB13_Pos      (13U)\n#define CAN_F6R1_FB13_Msk      (0x1U << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R1_FB14_Pos      (14U)\n#define CAN_F6R1_FB14_Msk      (0x1U << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R1_FB15_Pos      (15U)\n#define CAN_F6R1_FB15_Msk      (0x1U << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R1_FB16_Pos      (16U)\n#define CAN_F6R1_FB16_Msk      (0x1U << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R1_FB17_Pos      (17U)\n#define CAN_F6R1_FB17_Msk      (0x1U << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R1_FB18_Pos      (18U)\n#define CAN_F6R1_FB18_Msk      (0x1U << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R1_FB19_Pos      (19U)\n#define CAN_F6R1_FB19_Msk      (0x1U << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R1_FB20_Pos      (20U)\n#define CAN_F6R1_FB20_Msk      (0x1U << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R1_FB21_Pos      (21U)\n#define CAN_F6R1_FB21_Msk      (0x1U << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R1_FB22_Pos      (22U)\n#define CAN_F6R1_FB22_Msk      (0x1U << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R1_FB23_Pos      (23U)\n#define CAN_F6R1_FB23_Msk      (0x1U << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R1_FB24_Pos      (24U)\n#define CAN_F6R1_FB24_Msk      (0x1U << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R1_FB25_Pos      (25U)\n#define CAN_F6R1_FB25_Msk      (0x1U << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R1_FB26_Pos      (26U)\n#define CAN_F6R1_FB26_Msk      (0x1U << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R1_FB27_Pos      (27U)\n#define CAN_F6R1_FB27_Msk      (0x1U << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R1_FB28_Pos      (28U)\n#define CAN_F6R1_FB28_Msk      (0x1U << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R1_FB29_Pos      (29U)\n#define CAN_F6R1_FB29_Msk      (0x1U << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R1_FB30_Pos      (30U)\n#define CAN_F6R1_FB30_Msk      (0x1U << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R1_FB31_Pos      (31U)\n#define CAN_F6R1_FB31_Msk      (0x1U << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R1 register  *******************/\n#define CAN_F7R1_FB0_Pos       (0U)\n#define CAN_F7R1_FB0_Msk       (0x1U << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R1_FB1_Pos       (1U)\n#define CAN_F7R1_FB1_Msk       (0x1U << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R1_FB2_Pos       (2U)\n#define CAN_F7R1_FB2_Msk       (0x1U << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R1_FB3_Pos       (3U)\n#define CAN_F7R1_FB3_Msk       (0x1U << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R1_FB4_Pos       (4U)\n#define CAN_F7R1_FB4_Msk       (0x1U << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R1_FB5_Pos       (5U)\n#define CAN_F7R1_FB5_Msk       (0x1U << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R1_FB6_Pos       (6U)\n#define CAN_F7R1_FB6_Msk       (0x1U << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R1_FB7_Pos       (7U)\n#define CAN_F7R1_FB7_Msk       (0x1U << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R1_FB8_Pos       (8U)\n#define CAN_F7R1_FB8_Msk       (0x1U << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R1_FB9_Pos       (9U)\n#define CAN_F7R1_FB9_Msk       (0x1U << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R1_FB10_Pos      (10U)\n#define CAN_F7R1_FB10_Msk      (0x1U << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R1_FB11_Pos      (11U)\n#define CAN_F7R1_FB11_Msk      (0x1U << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R1_FB12_Pos      (12U)\n#define CAN_F7R1_FB12_Msk      (0x1U << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R1_FB13_Pos      (13U)\n#define CAN_F7R1_FB13_Msk      (0x1U << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R1_FB14_Pos      (14U)\n#define CAN_F7R1_FB14_Msk      (0x1U << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R1_FB15_Pos      (15U)\n#define CAN_F7R1_FB15_Msk      (0x1U << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R1_FB16_Pos      (16U)\n#define CAN_F7R1_FB16_Msk      (0x1U << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R1_FB17_Pos      (17U)\n#define CAN_F7R1_FB17_Msk      (0x1U << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R1_FB18_Pos      (18U)\n#define CAN_F7R1_FB18_Msk      (0x1U << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R1_FB19_Pos      (19U)\n#define CAN_F7R1_FB19_Msk      (0x1U << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R1_FB20_Pos      (20U)\n#define CAN_F7R1_FB20_Msk      (0x1U << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R1_FB21_Pos      (21U)\n#define CAN_F7R1_FB21_Msk      (0x1U << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R1_FB22_Pos      (22U)\n#define CAN_F7R1_FB22_Msk      (0x1U << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R1_FB23_Pos      (23U)\n#define CAN_F7R1_FB23_Msk      (0x1U << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R1_FB24_Pos      (24U)\n#define CAN_F7R1_FB24_Msk      (0x1U << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R1_FB25_Pos      (25U)\n#define CAN_F7R1_FB25_Msk      (0x1U << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R1_FB26_Pos      (26U)\n#define CAN_F7R1_FB26_Msk      (0x1U << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R1_FB27_Pos      (27U)\n#define CAN_F7R1_FB27_Msk      (0x1U << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R1_FB28_Pos      (28U)\n#define CAN_F7R1_FB28_Msk      (0x1U << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R1_FB29_Pos      (29U)\n#define CAN_F7R1_FB29_Msk      (0x1U << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R1_FB30_Pos      (30U)\n#define CAN_F7R1_FB30_Msk      (0x1U << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R1_FB31_Pos      (31U)\n#define CAN_F7R1_FB31_Msk      (0x1U << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R1 register  *******************/\n#define CAN_F8R1_FB0_Pos       (0U)\n#define CAN_F8R1_FB0_Msk       (0x1U << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R1_FB1_Pos       (1U)\n#define CAN_F8R1_FB1_Msk       (0x1U << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R1_FB2_Pos       (2U)\n#define CAN_F8R1_FB2_Msk       (0x1U << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R1_FB3_Pos       (3U)\n#define CAN_F8R1_FB3_Msk       (0x1U << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R1_FB4_Pos       (4U)\n#define CAN_F8R1_FB4_Msk       (0x1U << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R1_FB5_Pos       (5U)\n#define CAN_F8R1_FB5_Msk       (0x1U << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R1_FB6_Pos       (6U)\n#define CAN_F8R1_FB6_Msk       (0x1U << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R1_FB7_Pos       (7U)\n#define CAN_F8R1_FB7_Msk       (0x1U << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R1_FB8_Pos       (8U)\n#define CAN_F8R1_FB8_Msk       (0x1U << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R1_FB9_Pos       (9U)\n#define CAN_F8R1_FB9_Msk       (0x1U << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R1_FB10_Pos      (10U)\n#define CAN_F8R1_FB10_Msk      (0x1U << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R1_FB11_Pos      (11U)\n#define CAN_F8R1_FB11_Msk      (0x1U << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R1_FB12_Pos      (12U)\n#define CAN_F8R1_FB12_Msk      (0x1U << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R1_FB13_Pos      (13U)\n#define CAN_F8R1_FB13_Msk      (0x1U << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R1_FB14_Pos      (14U)\n#define CAN_F8R1_FB14_Msk      (0x1U << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R1_FB15_Pos      (15U)\n#define CAN_F8R1_FB15_Msk      (0x1U << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R1_FB16_Pos      (16U)\n#define CAN_F8R1_FB16_Msk      (0x1U << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R1_FB17_Pos      (17U)\n#define CAN_F8R1_FB17_Msk      (0x1U << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R1_FB18_Pos      (18U)\n#define CAN_F8R1_FB18_Msk      (0x1U << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R1_FB19_Pos      (19U)\n#define CAN_F8R1_FB19_Msk      (0x1U << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R1_FB20_Pos      (20U)\n#define CAN_F8R1_FB20_Msk      (0x1U << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R1_FB21_Pos      (21U)\n#define CAN_F8R1_FB21_Msk      (0x1U << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R1_FB22_Pos      (22U)\n#define CAN_F8R1_FB22_Msk      (0x1U << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R1_FB23_Pos      (23U)\n#define CAN_F8R1_FB23_Msk      (0x1U << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R1_FB24_Pos      (24U)\n#define CAN_F8R1_FB24_Msk      (0x1U << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R1_FB25_Pos      (25U)\n#define CAN_F8R1_FB25_Msk      (0x1U << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R1_FB26_Pos      (26U)\n#define CAN_F8R1_FB26_Msk      (0x1U << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R1_FB27_Pos      (27U)\n#define CAN_F8R1_FB27_Msk      (0x1U << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R1_FB28_Pos      (28U)\n#define CAN_F8R1_FB28_Msk      (0x1U << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R1_FB29_Pos      (29U)\n#define CAN_F8R1_FB29_Msk      (0x1U << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R1_FB30_Pos      (30U)\n#define CAN_F8R1_FB30_Msk      (0x1U << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R1_FB31_Pos      (31U)\n#define CAN_F8R1_FB31_Msk      (0x1U << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R1 register  *******************/\n#define CAN_F9R1_FB0_Pos       (0U)\n#define CAN_F9R1_FB0_Msk       (0x1U << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R1_FB1_Pos       (1U)\n#define CAN_F9R1_FB1_Msk       (0x1U << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R1_FB2_Pos       (2U)\n#define CAN_F9R1_FB2_Msk       (0x1U << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R1_FB3_Pos       (3U)\n#define CAN_F9R1_FB3_Msk       (0x1U << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R1_FB4_Pos       (4U)\n#define CAN_F9R1_FB4_Msk       (0x1U << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R1_FB5_Pos       (5U)\n#define CAN_F9R1_FB5_Msk       (0x1U << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R1_FB6_Pos       (6U)\n#define CAN_F9R1_FB6_Msk       (0x1U << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R1_FB7_Pos       (7U)\n#define CAN_F9R1_FB7_Msk       (0x1U << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R1_FB8_Pos       (8U)\n#define CAN_F9R1_FB8_Msk       (0x1U << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R1_FB9_Pos       (9U)\n#define CAN_F9R1_FB9_Msk       (0x1U << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R1_FB10_Pos      (10U)\n#define CAN_F9R1_FB10_Msk      (0x1U << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R1_FB11_Pos      (11U)\n#define CAN_F9R1_FB11_Msk      (0x1U << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R1_FB12_Pos      (12U)\n#define CAN_F9R1_FB12_Msk      (0x1U << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R1_FB13_Pos      (13U)\n#define CAN_F9R1_FB13_Msk      (0x1U << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R1_FB14_Pos      (14U)\n#define CAN_F9R1_FB14_Msk      (0x1U << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R1_FB15_Pos      (15U)\n#define CAN_F9R1_FB15_Msk      (0x1U << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R1_FB16_Pos      (16U)\n#define CAN_F9R1_FB16_Msk      (0x1U << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R1_FB17_Pos      (17U)\n#define CAN_F9R1_FB17_Msk      (0x1U << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R1_FB18_Pos      (18U)\n#define CAN_F9R1_FB18_Msk      (0x1U << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R1_FB19_Pos      (19U)\n#define CAN_F9R1_FB19_Msk      (0x1U << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R1_FB20_Pos      (20U)\n#define CAN_F9R1_FB20_Msk      (0x1U << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R1_FB21_Pos      (21U)\n#define CAN_F9R1_FB21_Msk      (0x1U << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R1_FB22_Pos      (22U)\n#define CAN_F9R1_FB22_Msk      (0x1U << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R1_FB23_Pos      (23U)\n#define CAN_F9R1_FB23_Msk      (0x1U << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R1_FB24_Pos      (24U)\n#define CAN_F9R1_FB24_Msk      (0x1U << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R1_FB25_Pos      (25U)\n#define CAN_F9R1_FB25_Msk      (0x1U << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R1_FB26_Pos      (26U)\n#define CAN_F9R1_FB26_Msk      (0x1U << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R1_FB27_Pos      (27U)\n#define CAN_F9R1_FB27_Msk      (0x1U << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R1_FB28_Pos      (28U)\n#define CAN_F9R1_FB28_Msk      (0x1U << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R1_FB29_Pos      (29U)\n#define CAN_F9R1_FB29_Msk      (0x1U << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R1_FB30_Pos      (30U)\n#define CAN_F9R1_FB30_Msk      (0x1U << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R1_FB31_Pos      (31U)\n#define CAN_F9R1_FB31_Msk      (0x1U << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R1 register  ******************/\n#define CAN_F10R1_FB0_Pos      (0U)\n#define CAN_F10R1_FB0_Msk      (0x1U << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R1_FB1_Pos      (1U)\n#define CAN_F10R1_FB1_Msk      (0x1U << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R1_FB2_Pos      (2U)\n#define CAN_F10R1_FB2_Msk      (0x1U << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R1_FB3_Pos      (3U)\n#define CAN_F10R1_FB3_Msk      (0x1U << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R1_FB4_Pos      (4U)\n#define CAN_F10R1_FB4_Msk      (0x1U << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R1_FB5_Pos      (5U)\n#define CAN_F10R1_FB5_Msk      (0x1U << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R1_FB6_Pos      (6U)\n#define CAN_F10R1_FB6_Msk      (0x1U << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R1_FB7_Pos      (7U)\n#define CAN_F10R1_FB7_Msk      (0x1U << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R1_FB8_Pos      (8U)\n#define CAN_F10R1_FB8_Msk      (0x1U << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R1_FB9_Pos      (9U)\n#define CAN_F10R1_FB9_Msk      (0x1U << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R1_FB10_Pos     (10U)\n#define CAN_F10R1_FB10_Msk     (0x1U << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R1_FB11_Pos     (11U)\n#define CAN_F10R1_FB11_Msk     (0x1U << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R1_FB12_Pos     (12U)\n#define CAN_F10R1_FB12_Msk     (0x1U << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R1_FB13_Pos     (13U)\n#define CAN_F10R1_FB13_Msk     (0x1U << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R1_FB14_Pos     (14U)\n#define CAN_F10R1_FB14_Msk     (0x1U << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R1_FB15_Pos     (15U)\n#define CAN_F10R1_FB15_Msk     (0x1U << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R1_FB16_Pos     (16U)\n#define CAN_F10R1_FB16_Msk     (0x1U << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R1_FB17_Pos     (17U)\n#define CAN_F10R1_FB17_Msk     (0x1U << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R1_FB18_Pos     (18U)\n#define CAN_F10R1_FB18_Msk     (0x1U << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R1_FB19_Pos     (19U)\n#define CAN_F10R1_FB19_Msk     (0x1U << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R1_FB20_Pos     (20U)\n#define CAN_F10R1_FB20_Msk     (0x1U << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R1_FB21_Pos     (21U)\n#define CAN_F10R1_FB21_Msk     (0x1U << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R1_FB22_Pos     (22U)\n#define CAN_F10R1_FB22_Msk     (0x1U << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R1_FB23_Pos     (23U)\n#define CAN_F10R1_FB23_Msk     (0x1U << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R1_FB24_Pos     (24U)\n#define CAN_F10R1_FB24_Msk     (0x1U << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R1_FB25_Pos     (25U)\n#define CAN_F10R1_FB25_Msk     (0x1U << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R1_FB26_Pos     (26U)\n#define CAN_F10R1_FB26_Msk     (0x1U << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R1_FB27_Pos     (27U)\n#define CAN_F10R1_FB27_Msk     (0x1U << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R1_FB28_Pos     (28U)\n#define CAN_F10R1_FB28_Msk     (0x1U << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R1_FB29_Pos     (29U)\n#define CAN_F10R1_FB29_Msk     (0x1U << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R1_FB30_Pos     (30U)\n#define CAN_F10R1_FB30_Msk     (0x1U << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R1_FB31_Pos     (31U)\n#define CAN_F10R1_FB31_Msk     (0x1U << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R1 register  ******************/\n#define CAN_F11R1_FB0_Pos      (0U)\n#define CAN_F11R1_FB0_Msk      (0x1U << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R1_FB1_Pos      (1U)\n#define CAN_F11R1_FB1_Msk      (0x1U << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R1_FB2_Pos      (2U)\n#define CAN_F11R1_FB2_Msk      (0x1U << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R1_FB3_Pos      (3U)\n#define CAN_F11R1_FB3_Msk      (0x1U << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R1_FB4_Pos      (4U)\n#define CAN_F11R1_FB4_Msk      (0x1U << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R1_FB5_Pos      (5U)\n#define CAN_F11R1_FB5_Msk      (0x1U << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R1_FB6_Pos      (6U)\n#define CAN_F11R1_FB6_Msk      (0x1U << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R1_FB7_Pos      (7U)\n#define CAN_F11R1_FB7_Msk      (0x1U << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R1_FB8_Pos      (8U)\n#define CAN_F11R1_FB8_Msk      (0x1U << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R1_FB9_Pos      (9U)\n#define CAN_F11R1_FB9_Msk      (0x1U << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R1_FB10_Pos     (10U)\n#define CAN_F11R1_FB10_Msk     (0x1U << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R1_FB11_Pos     (11U)\n#define CAN_F11R1_FB11_Msk     (0x1U << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R1_FB12_Pos     (12U)\n#define CAN_F11R1_FB12_Msk     (0x1U << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R1_FB13_Pos     (13U)\n#define CAN_F11R1_FB13_Msk     (0x1U << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R1_FB14_Pos     (14U)\n#define CAN_F11R1_FB14_Msk     (0x1U << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R1_FB15_Pos     (15U)\n#define CAN_F11R1_FB15_Msk     (0x1U << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R1_FB16_Pos     (16U)\n#define CAN_F11R1_FB16_Msk     (0x1U << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R1_FB17_Pos     (17U)\n#define CAN_F11R1_FB17_Msk     (0x1U << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R1_FB18_Pos     (18U)\n#define CAN_F11R1_FB18_Msk     (0x1U << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R1_FB19_Pos     (19U)\n#define CAN_F11R1_FB19_Msk     (0x1U << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R1_FB20_Pos     (20U)\n#define CAN_F11R1_FB20_Msk     (0x1U << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R1_FB21_Pos     (21U)\n#define CAN_F11R1_FB21_Msk     (0x1U << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R1_FB22_Pos     (22U)\n#define CAN_F11R1_FB22_Msk     (0x1U << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R1_FB23_Pos     (23U)\n#define CAN_F11R1_FB23_Msk     (0x1U << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R1_FB24_Pos     (24U)\n#define CAN_F11R1_FB24_Msk     (0x1U << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R1_FB25_Pos     (25U)\n#define CAN_F11R1_FB25_Msk     (0x1U << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R1_FB26_Pos     (26U)\n#define CAN_F11R1_FB26_Msk     (0x1U << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R1_FB27_Pos     (27U)\n#define CAN_F11R1_FB27_Msk     (0x1U << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R1_FB28_Pos     (28U)\n#define CAN_F11R1_FB28_Msk     (0x1U << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R1_FB29_Pos     (29U)\n#define CAN_F11R1_FB29_Msk     (0x1U << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R1_FB30_Pos     (30U)\n#define CAN_F11R1_FB30_Msk     (0x1U << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R1_FB31_Pos     (31U)\n#define CAN_F11R1_FB31_Msk     (0x1U << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R1 register  ******************/\n#define CAN_F12R1_FB0_Pos      (0U)\n#define CAN_F12R1_FB0_Msk      (0x1U << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R1_FB1_Pos      (1U)\n#define CAN_F12R1_FB1_Msk      (0x1U << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R1_FB2_Pos      (2U)\n#define CAN_F12R1_FB2_Msk      (0x1U << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R1_FB3_Pos      (3U)\n#define CAN_F12R1_FB3_Msk      (0x1U << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R1_FB4_Pos      (4U)\n#define CAN_F12R1_FB4_Msk      (0x1U << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R1_FB5_Pos      (5U)\n#define CAN_F12R1_FB5_Msk      (0x1U << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R1_FB6_Pos      (6U)\n#define CAN_F12R1_FB6_Msk      (0x1U << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R1_FB7_Pos      (7U)\n#define CAN_F12R1_FB7_Msk      (0x1U << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R1_FB8_Pos      (8U)\n#define CAN_F12R1_FB8_Msk      (0x1U << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R1_FB9_Pos      (9U)\n#define CAN_F12R1_FB9_Msk      (0x1U << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R1_FB10_Pos     (10U)\n#define CAN_F12R1_FB10_Msk     (0x1U << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R1_FB11_Pos     (11U)\n#define CAN_F12R1_FB11_Msk     (0x1U << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R1_FB12_Pos     (12U)\n#define CAN_F12R1_FB12_Msk     (0x1U << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R1_FB13_Pos     (13U)\n#define CAN_F12R1_FB13_Msk     (0x1U << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R1_FB14_Pos     (14U)\n#define CAN_F12R1_FB14_Msk     (0x1U << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R1_FB15_Pos     (15U)\n#define CAN_F12R1_FB15_Msk     (0x1U << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R1_FB16_Pos     (16U)\n#define CAN_F12R1_FB16_Msk     (0x1U << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R1_FB17_Pos     (17U)\n#define CAN_F12R1_FB17_Msk     (0x1U << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R1_FB18_Pos     (18U)\n#define CAN_F12R1_FB18_Msk     (0x1U << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R1_FB19_Pos     (19U)\n#define CAN_F12R1_FB19_Msk     (0x1U << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R1_FB20_Pos     (20U)\n#define CAN_F12R1_FB20_Msk     (0x1U << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R1_FB21_Pos     (21U)\n#define CAN_F12R1_FB21_Msk     (0x1U << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R1_FB22_Pos     (22U)\n#define CAN_F12R1_FB22_Msk     (0x1U << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R1_FB23_Pos     (23U)\n#define CAN_F12R1_FB23_Msk     (0x1U << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R1_FB24_Pos     (24U)\n#define CAN_F12R1_FB24_Msk     (0x1U << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R1_FB25_Pos     (25U)\n#define CAN_F12R1_FB25_Msk     (0x1U << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R1_FB26_Pos     (26U)\n#define CAN_F12R1_FB26_Msk     (0x1U << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R1_FB27_Pos     (27U)\n#define CAN_F12R1_FB27_Msk     (0x1U << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R1_FB28_Pos     (28U)\n#define CAN_F12R1_FB28_Msk     (0x1U << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R1_FB29_Pos     (29U)\n#define CAN_F12R1_FB29_Msk     (0x1U << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R1_FB30_Pos     (30U)\n#define CAN_F12R1_FB30_Msk     (0x1U << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R1_FB31_Pos     (31U)\n#define CAN_F12R1_FB31_Msk     (0x1U << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R1 register  ******************/\n#define CAN_F13R1_FB0_Pos      (0U)\n#define CAN_F13R1_FB0_Msk      (0x1U << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R1_FB1_Pos      (1U)\n#define CAN_F13R1_FB1_Msk      (0x1U << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R1_FB2_Pos      (2U)\n#define CAN_F13R1_FB2_Msk      (0x1U << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R1_FB3_Pos      (3U)\n#define CAN_F13R1_FB3_Msk      (0x1U << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R1_FB4_Pos      (4U)\n#define CAN_F13R1_FB4_Msk      (0x1U << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R1_FB5_Pos      (5U)\n#define CAN_F13R1_FB5_Msk      (0x1U << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R1_FB6_Pos      (6U)\n#define CAN_F13R1_FB6_Msk      (0x1U << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R1_FB7_Pos      (7U)\n#define CAN_F13R1_FB7_Msk      (0x1U << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R1_FB8_Pos      (8U)\n#define CAN_F13R1_FB8_Msk      (0x1U << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R1_FB9_Pos      (9U)\n#define CAN_F13R1_FB9_Msk      (0x1U << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R1_FB10_Pos     (10U)\n#define CAN_F13R1_FB10_Msk     (0x1U << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R1_FB11_Pos     (11U)\n#define CAN_F13R1_FB11_Msk     (0x1U << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R1_FB12_Pos     (12U)\n#define CAN_F13R1_FB12_Msk     (0x1U << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R1_FB13_Pos     (13U)\n#define CAN_F13R1_FB13_Msk     (0x1U << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R1_FB14_Pos     (14U)\n#define CAN_F13R1_FB14_Msk     (0x1U << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R1_FB15_Pos     (15U)\n#define CAN_F13R1_FB15_Msk     (0x1U << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R1_FB16_Pos     (16U)\n#define CAN_F13R1_FB16_Msk     (0x1U << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R1_FB17_Pos     (17U)\n#define CAN_F13R1_FB17_Msk     (0x1U << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R1_FB18_Pos     (18U)\n#define CAN_F13R1_FB18_Msk     (0x1U << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R1_FB19_Pos     (19U)\n#define CAN_F13R1_FB19_Msk     (0x1U << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R1_FB20_Pos     (20U)\n#define CAN_F13R1_FB20_Msk     (0x1U << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R1_FB21_Pos     (21U)\n#define CAN_F13R1_FB21_Msk     (0x1U << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R1_FB22_Pos     (22U)\n#define CAN_F13R1_FB22_Msk     (0x1U << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R1_FB23_Pos     (23U)\n#define CAN_F13R1_FB23_Msk     (0x1U << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R1_FB24_Pos     (24U)\n#define CAN_F13R1_FB24_Msk     (0x1U << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R1_FB25_Pos     (25U)\n#define CAN_F13R1_FB25_Msk     (0x1U << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R1_FB26_Pos     (26U)\n#define CAN_F13R1_FB26_Msk     (0x1U << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R1_FB27_Pos     (27U)\n#define CAN_F13R1_FB27_Msk     (0x1U << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R1_FB28_Pos     (28U)\n#define CAN_F13R1_FB28_Msk     (0x1U << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R1_FB29_Pos     (29U)\n#define CAN_F13R1_FB29_Msk     (0x1U << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R1_FB30_Pos     (30U)\n#define CAN_F13R1_FB30_Msk     (0x1U << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R1_FB31_Pos     (31U)\n#define CAN_F13R1_FB31_Msk     (0x1U << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F0R2 register  *******************/\n#define CAN_F0R2_FB0_Pos       (0U)\n#define CAN_F0R2_FB0_Msk       (0x1U << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R2_FB1_Pos       (1U)\n#define CAN_F0R2_FB1_Msk       (0x1U << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R2_FB2_Pos       (2U)\n#define CAN_F0R2_FB2_Msk       (0x1U << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R2_FB3_Pos       (3U)\n#define CAN_F0R2_FB3_Msk       (0x1U << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R2_FB4_Pos       (4U)\n#define CAN_F0R2_FB4_Msk       (0x1U << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R2_FB5_Pos       (5U)\n#define CAN_F0R2_FB5_Msk       (0x1U << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R2_FB6_Pos       (6U)\n#define CAN_F0R2_FB6_Msk       (0x1U << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R2_FB7_Pos       (7U)\n#define CAN_F0R2_FB7_Msk       (0x1U << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R2_FB8_Pos       (8U)\n#define CAN_F0R2_FB8_Msk       (0x1U << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R2_FB9_Pos       (9U)\n#define CAN_F0R2_FB9_Msk       (0x1U << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R2_FB10_Pos      (10U)\n#define CAN_F0R2_FB10_Msk      (0x1U << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R2_FB11_Pos      (11U)\n#define CAN_F0R2_FB11_Msk      (0x1U << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R2_FB12_Pos      (12U)\n#define CAN_F0R2_FB12_Msk      (0x1U << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R2_FB13_Pos      (13U)\n#define CAN_F0R2_FB13_Msk      (0x1U << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R2_FB14_Pos      (14U)\n#define CAN_F0R2_FB14_Msk      (0x1U << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R2_FB15_Pos      (15U)\n#define CAN_F0R2_FB15_Msk      (0x1U << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R2_FB16_Pos      (16U)\n#define CAN_F0R2_FB16_Msk      (0x1U << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R2_FB17_Pos      (17U)\n#define CAN_F0R2_FB17_Msk      (0x1U << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R2_FB18_Pos      (18U)\n#define CAN_F0R2_FB18_Msk      (0x1U << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R2_FB19_Pos      (19U)\n#define CAN_F0R2_FB19_Msk      (0x1U << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R2_FB20_Pos      (20U)\n#define CAN_F0R2_FB20_Msk      (0x1U << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R2_FB21_Pos      (21U)\n#define CAN_F0R2_FB21_Msk      (0x1U << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R2_FB22_Pos      (22U)\n#define CAN_F0R2_FB22_Msk      (0x1U << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R2_FB23_Pos      (23U)\n#define CAN_F0R2_FB23_Msk      (0x1U << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R2_FB24_Pos      (24U)\n#define CAN_F0R2_FB24_Msk      (0x1U << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R2_FB25_Pos      (25U)\n#define CAN_F0R2_FB25_Msk      (0x1U << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R2_FB26_Pos      (26U)\n#define CAN_F0R2_FB26_Msk      (0x1U << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R2_FB27_Pos      (27U)\n#define CAN_F0R2_FB27_Msk      (0x1U << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R2_FB28_Pos      (28U)\n#define CAN_F0R2_FB28_Msk      (0x1U << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R2_FB29_Pos      (29U)\n#define CAN_F0R2_FB29_Msk      (0x1U << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R2_FB30_Pos      (30U)\n#define CAN_F0R2_FB30_Msk      (0x1U << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R2_FB31_Pos      (31U)\n#define CAN_F0R2_FB31_Msk      (0x1U << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R2 register  *******************/\n#define CAN_F1R2_FB0_Pos       (0U)\n#define CAN_F1R2_FB0_Msk       (0x1U << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R2_FB1_Pos       (1U)\n#define CAN_F1R2_FB1_Msk       (0x1U << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R2_FB2_Pos       (2U)\n#define CAN_F1R2_FB2_Msk       (0x1U << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R2_FB3_Pos       (3U)\n#define CAN_F1R2_FB3_Msk       (0x1U << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R2_FB4_Pos       (4U)\n#define CAN_F1R2_FB4_Msk       (0x1U << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R2_FB5_Pos       (5U)\n#define CAN_F1R2_FB5_Msk       (0x1U << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R2_FB6_Pos       (6U)\n#define CAN_F1R2_FB6_Msk       (0x1U << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R2_FB7_Pos       (7U)\n#define CAN_F1R2_FB7_Msk       (0x1U << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R2_FB8_Pos       (8U)\n#define CAN_F1R2_FB8_Msk       (0x1U << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R2_FB9_Pos       (9U)\n#define CAN_F1R2_FB9_Msk       (0x1U << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R2_FB10_Pos      (10U)\n#define CAN_F1R2_FB10_Msk      (0x1U << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R2_FB11_Pos      (11U)\n#define CAN_F1R2_FB11_Msk      (0x1U << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R2_FB12_Pos      (12U)\n#define CAN_F1R2_FB12_Msk      (0x1U << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R2_FB13_Pos      (13U)\n#define CAN_F1R2_FB13_Msk      (0x1U << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R2_FB14_Pos      (14U)\n#define CAN_F1R2_FB14_Msk      (0x1U << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R2_FB15_Pos      (15U)\n#define CAN_F1R2_FB15_Msk      (0x1U << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R2_FB16_Pos      (16U)\n#define CAN_F1R2_FB16_Msk      (0x1U << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R2_FB17_Pos      (17U)\n#define CAN_F1R2_FB17_Msk      (0x1U << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R2_FB18_Pos      (18U)\n#define CAN_F1R2_FB18_Msk      (0x1U << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R2_FB19_Pos      (19U)\n#define CAN_F1R2_FB19_Msk      (0x1U << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R2_FB20_Pos      (20U)\n#define CAN_F1R2_FB20_Msk      (0x1U << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R2_FB21_Pos      (21U)\n#define CAN_F1R2_FB21_Msk      (0x1U << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R2_FB22_Pos      (22U)\n#define CAN_F1R2_FB22_Msk      (0x1U << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R2_FB23_Pos      (23U)\n#define CAN_F1R2_FB23_Msk      (0x1U << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R2_FB24_Pos      (24U)\n#define CAN_F1R2_FB24_Msk      (0x1U << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R2_FB25_Pos      (25U)\n#define CAN_F1R2_FB25_Msk      (0x1U << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R2_FB26_Pos      (26U)\n#define CAN_F1R2_FB26_Msk      (0x1U << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R2_FB27_Pos      (27U)\n#define CAN_F1R2_FB27_Msk      (0x1U << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R2_FB28_Pos      (28U)\n#define CAN_F1R2_FB28_Msk      (0x1U << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R2_FB29_Pos      (29U)\n#define CAN_F1R2_FB29_Msk      (0x1U << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R2_FB30_Pos      (30U)\n#define CAN_F1R2_FB30_Msk      (0x1U << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R2_FB31_Pos      (31U)\n#define CAN_F1R2_FB31_Msk      (0x1U << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R2 register  *******************/\n#define CAN_F2R2_FB0_Pos       (0U)\n#define CAN_F2R2_FB0_Msk       (0x1U << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R2_FB1_Pos       (1U)\n#define CAN_F2R2_FB1_Msk       (0x1U << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R2_FB2_Pos       (2U)\n#define CAN_F2R2_FB2_Msk       (0x1U << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R2_FB3_Pos       (3U)\n#define CAN_F2R2_FB3_Msk       (0x1U << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R2_FB4_Pos       (4U)\n#define CAN_F2R2_FB4_Msk       (0x1U << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R2_FB5_Pos       (5U)\n#define CAN_F2R2_FB5_Msk       (0x1U << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R2_FB6_Pos       (6U)\n#define CAN_F2R2_FB6_Msk       (0x1U << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R2_FB7_Pos       (7U)\n#define CAN_F2R2_FB7_Msk       (0x1U << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R2_FB8_Pos       (8U)\n#define CAN_F2R2_FB8_Msk       (0x1U << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R2_FB9_Pos       (9U)\n#define CAN_F2R2_FB9_Msk       (0x1U << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R2_FB10_Pos      (10U)\n#define CAN_F2R2_FB10_Msk      (0x1U << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R2_FB11_Pos      (11U)\n#define CAN_F2R2_FB11_Msk      (0x1U << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R2_FB12_Pos      (12U)\n#define CAN_F2R2_FB12_Msk      (0x1U << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R2_FB13_Pos      (13U)\n#define CAN_F2R2_FB13_Msk      (0x1U << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R2_FB14_Pos      (14U)\n#define CAN_F2R2_FB14_Msk      (0x1U << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R2_FB15_Pos      (15U)\n#define CAN_F2R2_FB15_Msk      (0x1U << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R2_FB16_Pos      (16U)\n#define CAN_F2R2_FB16_Msk      (0x1U << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R2_FB17_Pos      (17U)\n#define CAN_F2R2_FB17_Msk      (0x1U << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R2_FB18_Pos      (18U)\n#define CAN_F2R2_FB18_Msk      (0x1U << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R2_FB19_Pos      (19U)\n#define CAN_F2R2_FB19_Msk      (0x1U << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R2_FB20_Pos      (20U)\n#define CAN_F2R2_FB20_Msk      (0x1U << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R2_FB21_Pos      (21U)\n#define CAN_F2R2_FB21_Msk      (0x1U << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R2_FB22_Pos      (22U)\n#define CAN_F2R2_FB22_Msk      (0x1U << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R2_FB23_Pos      (23U)\n#define CAN_F2R2_FB23_Msk      (0x1U << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R2_FB24_Pos      (24U)\n#define CAN_F2R2_FB24_Msk      (0x1U << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R2_FB25_Pos      (25U)\n#define CAN_F2R2_FB25_Msk      (0x1U << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R2_FB26_Pos      (26U)\n#define CAN_F2R2_FB26_Msk      (0x1U << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R2_FB27_Pos      (27U)\n#define CAN_F2R2_FB27_Msk      (0x1U << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R2_FB28_Pos      (28U)\n#define CAN_F2R2_FB28_Msk      (0x1U << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R2_FB29_Pos      (29U)\n#define CAN_F2R2_FB29_Msk      (0x1U << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R2_FB30_Pos      (30U)\n#define CAN_F2R2_FB30_Msk      (0x1U << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R2_FB31_Pos      (31U)\n#define CAN_F2R2_FB31_Msk      (0x1U << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R2 register  *******************/\n#define CAN_F3R2_FB0_Pos       (0U)\n#define CAN_F3R2_FB0_Msk       (0x1U << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R2_FB1_Pos       (1U)\n#define CAN_F3R2_FB1_Msk       (0x1U << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R2_FB2_Pos       (2U)\n#define CAN_F3R2_FB2_Msk       (0x1U << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R2_FB3_Pos       (3U)\n#define CAN_F3R2_FB3_Msk       (0x1U << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R2_FB4_Pos       (4U)\n#define CAN_F3R2_FB4_Msk       (0x1U << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R2_FB5_Pos       (5U)\n#define CAN_F3R2_FB5_Msk       (0x1U << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R2_FB6_Pos       (6U)\n#define CAN_F3R2_FB6_Msk       (0x1U << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R2_FB7_Pos       (7U)\n#define CAN_F3R2_FB7_Msk       (0x1U << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R2_FB8_Pos       (8U)\n#define CAN_F3R2_FB8_Msk       (0x1U << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R2_FB9_Pos       (9U)\n#define CAN_F3R2_FB9_Msk       (0x1U << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R2_FB10_Pos      (10U)\n#define CAN_F3R2_FB10_Msk      (0x1U << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R2_FB11_Pos      (11U)\n#define CAN_F3R2_FB11_Msk      (0x1U << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R2_FB12_Pos      (12U)\n#define CAN_F3R2_FB12_Msk      (0x1U << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R2_FB13_Pos      (13U)\n#define CAN_F3R2_FB13_Msk      (0x1U << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R2_FB14_Pos      (14U)\n#define CAN_F3R2_FB14_Msk      (0x1U << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R2_FB15_Pos      (15U)\n#define CAN_F3R2_FB15_Msk      (0x1U << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R2_FB16_Pos      (16U)\n#define CAN_F3R2_FB16_Msk      (0x1U << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R2_FB17_Pos      (17U)\n#define CAN_F3R2_FB17_Msk      (0x1U << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R2_FB18_Pos      (18U)\n#define CAN_F3R2_FB18_Msk      (0x1U << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R2_FB19_Pos      (19U)\n#define CAN_F3R2_FB19_Msk      (0x1U << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R2_FB20_Pos      (20U)\n#define CAN_F3R2_FB20_Msk      (0x1U << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R2_FB21_Pos      (21U)\n#define CAN_F3R2_FB21_Msk      (0x1U << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R2_FB22_Pos      (22U)\n#define CAN_F3R2_FB22_Msk      (0x1U << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R2_FB23_Pos      (23U)\n#define CAN_F3R2_FB23_Msk      (0x1U << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R2_FB24_Pos      (24U)\n#define CAN_F3R2_FB24_Msk      (0x1U << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R2_FB25_Pos      (25U)\n#define CAN_F3R2_FB25_Msk      (0x1U << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R2_FB26_Pos      (26U)\n#define CAN_F3R2_FB26_Msk      (0x1U << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R2_FB27_Pos      (27U)\n#define CAN_F3R2_FB27_Msk      (0x1U << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R2_FB28_Pos      (28U)\n#define CAN_F3R2_FB28_Msk      (0x1U << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R2_FB29_Pos      (29U)\n#define CAN_F3R2_FB29_Msk      (0x1U << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R2_FB30_Pos      (30U)\n#define CAN_F3R2_FB30_Msk      (0x1U << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R2_FB31_Pos      (31U)\n#define CAN_F3R2_FB31_Msk      (0x1U << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R2 register  *******************/\n#define CAN_F4R2_FB0_Pos       (0U)\n#define CAN_F4R2_FB0_Msk       (0x1U << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R2_FB1_Pos       (1U)\n#define CAN_F4R2_FB1_Msk       (0x1U << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R2_FB2_Pos       (2U)\n#define CAN_F4R2_FB2_Msk       (0x1U << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R2_FB3_Pos       (3U)\n#define CAN_F4R2_FB3_Msk       (0x1U << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R2_FB4_Pos       (4U)\n#define CAN_F4R2_FB4_Msk       (0x1U << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R2_FB5_Pos       (5U)\n#define CAN_F4R2_FB5_Msk       (0x1U << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R2_FB6_Pos       (6U)\n#define CAN_F4R2_FB6_Msk       (0x1U << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R2_FB7_Pos       (7U)\n#define CAN_F4R2_FB7_Msk       (0x1U << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R2_FB8_Pos       (8U)\n#define CAN_F4R2_FB8_Msk       (0x1U << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R2_FB9_Pos       (9U)\n#define CAN_F4R2_FB9_Msk       (0x1U << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R2_FB10_Pos      (10U)\n#define CAN_F4R2_FB10_Msk      (0x1U << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R2_FB11_Pos      (11U)\n#define CAN_F4R2_FB11_Msk      (0x1U << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R2_FB12_Pos      (12U)\n#define CAN_F4R2_FB12_Msk      (0x1U << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R2_FB13_Pos      (13U)\n#define CAN_F4R2_FB13_Msk      (0x1U << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R2_FB14_Pos      (14U)\n#define CAN_F4R2_FB14_Msk      (0x1U << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R2_FB15_Pos      (15U)\n#define CAN_F4R2_FB15_Msk      (0x1U << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R2_FB16_Pos      (16U)\n#define CAN_F4R2_FB16_Msk      (0x1U << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R2_FB17_Pos      (17U)\n#define CAN_F4R2_FB17_Msk      (0x1U << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R2_FB18_Pos      (18U)\n#define CAN_F4R2_FB18_Msk      (0x1U << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R2_FB19_Pos      (19U)\n#define CAN_F4R2_FB19_Msk      (0x1U << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R2_FB20_Pos      (20U)\n#define CAN_F4R2_FB20_Msk      (0x1U << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R2_FB21_Pos      (21U)\n#define CAN_F4R2_FB21_Msk      (0x1U << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R2_FB22_Pos      (22U)\n#define CAN_F4R2_FB22_Msk      (0x1U << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R2_FB23_Pos      (23U)\n#define CAN_F4R2_FB23_Msk      (0x1U << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R2_FB24_Pos      (24U)\n#define CAN_F4R2_FB24_Msk      (0x1U << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R2_FB25_Pos      (25U)\n#define CAN_F4R2_FB25_Msk      (0x1U << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R2_FB26_Pos      (26U)\n#define CAN_F4R2_FB26_Msk      (0x1U << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R2_FB27_Pos      (27U)\n#define CAN_F4R2_FB27_Msk      (0x1U << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R2_FB28_Pos      (28U)\n#define CAN_F4R2_FB28_Msk      (0x1U << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R2_FB29_Pos      (29U)\n#define CAN_F4R2_FB29_Msk      (0x1U << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R2_FB30_Pos      (30U)\n#define CAN_F4R2_FB30_Msk      (0x1U << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R2_FB31_Pos      (31U)\n#define CAN_F4R2_FB31_Msk      (0x1U << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R2 register  *******************/\n#define CAN_F5R2_FB0_Pos       (0U)\n#define CAN_F5R2_FB0_Msk       (0x1U << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R2_FB1_Pos       (1U)\n#define CAN_F5R2_FB1_Msk       (0x1U << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R2_FB2_Pos       (2U)\n#define CAN_F5R2_FB2_Msk       (0x1U << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R2_FB3_Pos       (3U)\n#define CAN_F5R2_FB3_Msk       (0x1U << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R2_FB4_Pos       (4U)\n#define CAN_F5R2_FB4_Msk       (0x1U << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R2_FB5_Pos       (5U)\n#define CAN_F5R2_FB5_Msk       (0x1U << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R2_FB6_Pos       (6U)\n#define CAN_F5R2_FB6_Msk       (0x1U << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R2_FB7_Pos       (7U)\n#define CAN_F5R2_FB7_Msk       (0x1U << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R2_FB8_Pos       (8U)\n#define CAN_F5R2_FB8_Msk       (0x1U << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R2_FB9_Pos       (9U)\n#define CAN_F5R2_FB9_Msk       (0x1U << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R2_FB10_Pos      (10U)\n#define CAN_F5R2_FB10_Msk      (0x1U << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R2_FB11_Pos      (11U)\n#define CAN_F5R2_FB11_Msk      (0x1U << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R2_FB12_Pos      (12U)\n#define CAN_F5R2_FB12_Msk      (0x1U << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R2_FB13_Pos      (13U)\n#define CAN_F5R2_FB13_Msk      (0x1U << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R2_FB14_Pos      (14U)\n#define CAN_F5R2_FB14_Msk      (0x1U << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R2_FB15_Pos      (15U)\n#define CAN_F5R2_FB15_Msk      (0x1U << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R2_FB16_Pos      (16U)\n#define CAN_F5R2_FB16_Msk      (0x1U << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R2_FB17_Pos      (17U)\n#define CAN_F5R2_FB17_Msk      (0x1U << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R2_FB18_Pos      (18U)\n#define CAN_F5R2_FB18_Msk      (0x1U << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R2_FB19_Pos      (19U)\n#define CAN_F5R2_FB19_Msk      (0x1U << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R2_FB20_Pos      (20U)\n#define CAN_F5R2_FB20_Msk      (0x1U << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R2_FB21_Pos      (21U)\n#define CAN_F5R2_FB21_Msk      (0x1U << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R2_FB22_Pos      (22U)\n#define CAN_F5R2_FB22_Msk      (0x1U << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R2_FB23_Pos      (23U)\n#define CAN_F5R2_FB23_Msk      (0x1U << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R2_FB24_Pos      (24U)\n#define CAN_F5R2_FB24_Msk      (0x1U << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R2_FB25_Pos      (25U)\n#define CAN_F5R2_FB25_Msk      (0x1U << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R2_FB26_Pos      (26U)\n#define CAN_F5R2_FB26_Msk      (0x1U << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R2_FB27_Pos      (27U)\n#define CAN_F5R2_FB27_Msk      (0x1U << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R2_FB28_Pos      (28U)\n#define CAN_F5R2_FB28_Msk      (0x1U << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R2_FB29_Pos      (29U)\n#define CAN_F5R2_FB29_Msk      (0x1U << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R2_FB30_Pos      (30U)\n#define CAN_F5R2_FB30_Msk      (0x1U << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R2_FB31_Pos      (31U)\n#define CAN_F5R2_FB31_Msk      (0x1U << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R2 register  *******************/\n#define CAN_F6R2_FB0_Pos       (0U)\n#define CAN_F6R2_FB0_Msk       (0x1U << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R2_FB1_Pos       (1U)\n#define CAN_F6R2_FB1_Msk       (0x1U << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R2_FB2_Pos       (2U)\n#define CAN_F6R2_FB2_Msk       (0x1U << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R2_FB3_Pos       (3U)\n#define CAN_F6R2_FB3_Msk       (0x1U << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R2_FB4_Pos       (4U)\n#define CAN_F6R2_FB4_Msk       (0x1U << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R2_FB5_Pos       (5U)\n#define CAN_F6R2_FB5_Msk       (0x1U << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R2_FB6_Pos       (6U)\n#define CAN_F6R2_FB6_Msk       (0x1U << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R2_FB7_Pos       (7U)\n#define CAN_F6R2_FB7_Msk       (0x1U << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R2_FB8_Pos       (8U)\n#define CAN_F6R2_FB8_Msk       (0x1U << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R2_FB9_Pos       (9U)\n#define CAN_F6R2_FB9_Msk       (0x1U << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R2_FB10_Pos      (10U)\n#define CAN_F6R2_FB10_Msk      (0x1U << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R2_FB11_Pos      (11U)\n#define CAN_F6R2_FB11_Msk      (0x1U << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R2_FB12_Pos      (12U)\n#define CAN_F6R2_FB12_Msk      (0x1U << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R2_FB13_Pos      (13U)\n#define CAN_F6R2_FB13_Msk      (0x1U << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R2_FB14_Pos      (14U)\n#define CAN_F6R2_FB14_Msk      (0x1U << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R2_FB15_Pos      (15U)\n#define CAN_F6R2_FB15_Msk      (0x1U << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R2_FB16_Pos      (16U)\n#define CAN_F6R2_FB16_Msk      (0x1U << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R2_FB17_Pos      (17U)\n#define CAN_F6R2_FB17_Msk      (0x1U << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R2_FB18_Pos      (18U)\n#define CAN_F6R2_FB18_Msk      (0x1U << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R2_FB19_Pos      (19U)\n#define CAN_F6R2_FB19_Msk      (0x1U << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R2_FB20_Pos      (20U)\n#define CAN_F6R2_FB20_Msk      (0x1U << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R2_FB21_Pos      (21U)\n#define CAN_F6R2_FB21_Msk      (0x1U << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R2_FB22_Pos      (22U)\n#define CAN_F6R2_FB22_Msk      (0x1U << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R2_FB23_Pos      (23U)\n#define CAN_F6R2_FB23_Msk      (0x1U << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R2_FB24_Pos      (24U)\n#define CAN_F6R2_FB24_Msk      (0x1U << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R2_FB25_Pos      (25U)\n#define CAN_F6R2_FB25_Msk      (0x1U << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R2_FB26_Pos      (26U)\n#define CAN_F6R2_FB26_Msk      (0x1U << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R2_FB27_Pos      (27U)\n#define CAN_F6R2_FB27_Msk      (0x1U << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R2_FB28_Pos      (28U)\n#define CAN_F6R2_FB28_Msk      (0x1U << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R2_FB29_Pos      (29U)\n#define CAN_F6R2_FB29_Msk      (0x1U << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R2_FB30_Pos      (30U)\n#define CAN_F6R2_FB30_Msk      (0x1U << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R2_FB31_Pos      (31U)\n#define CAN_F6R2_FB31_Msk      (0x1U << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R2 register  *******************/\n#define CAN_F7R2_FB0_Pos       (0U)\n#define CAN_F7R2_FB0_Msk       (0x1U << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R2_FB1_Pos       (1U)\n#define CAN_F7R2_FB1_Msk       (0x1U << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R2_FB2_Pos       (2U)\n#define CAN_F7R2_FB2_Msk       (0x1U << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R2_FB3_Pos       (3U)\n#define CAN_F7R2_FB3_Msk       (0x1U << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R2_FB4_Pos       (4U)\n#define CAN_F7R2_FB4_Msk       (0x1U << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R2_FB5_Pos       (5U)\n#define CAN_F7R2_FB5_Msk       (0x1U << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R2_FB6_Pos       (6U)\n#define CAN_F7R2_FB6_Msk       (0x1U << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R2_FB7_Pos       (7U)\n#define CAN_F7R2_FB7_Msk       (0x1U << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R2_FB8_Pos       (8U)\n#define CAN_F7R2_FB8_Msk       (0x1U << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R2_FB9_Pos       (9U)\n#define CAN_F7R2_FB9_Msk       (0x1U << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R2_FB10_Pos      (10U)\n#define CAN_F7R2_FB10_Msk      (0x1U << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R2_FB11_Pos      (11U)\n#define CAN_F7R2_FB11_Msk      (0x1U << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R2_FB12_Pos      (12U)\n#define CAN_F7R2_FB12_Msk      (0x1U << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R2_FB13_Pos      (13U)\n#define CAN_F7R2_FB13_Msk      (0x1U << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R2_FB14_Pos      (14U)\n#define CAN_F7R2_FB14_Msk      (0x1U << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R2_FB15_Pos      (15U)\n#define CAN_F7R2_FB15_Msk      (0x1U << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R2_FB16_Pos      (16U)\n#define CAN_F7R2_FB16_Msk      (0x1U << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R2_FB17_Pos      (17U)\n#define CAN_F7R2_FB17_Msk      (0x1U << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R2_FB18_Pos      (18U)\n#define CAN_F7R2_FB18_Msk      (0x1U << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R2_FB19_Pos      (19U)\n#define CAN_F7R2_FB19_Msk      (0x1U << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R2_FB20_Pos      (20U)\n#define CAN_F7R2_FB20_Msk      (0x1U << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R2_FB21_Pos      (21U)\n#define CAN_F7R2_FB21_Msk      (0x1U << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R2_FB22_Pos      (22U)\n#define CAN_F7R2_FB22_Msk      (0x1U << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R2_FB23_Pos      (23U)\n#define CAN_F7R2_FB23_Msk      (0x1U << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R2_FB24_Pos      (24U)\n#define CAN_F7R2_FB24_Msk      (0x1U << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R2_FB25_Pos      (25U)\n#define CAN_F7R2_FB25_Msk      (0x1U << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R2_FB26_Pos      (26U)\n#define CAN_F7R2_FB26_Msk      (0x1U << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R2_FB27_Pos      (27U)\n#define CAN_F7R2_FB27_Msk      (0x1U << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R2_FB28_Pos      (28U)\n#define CAN_F7R2_FB28_Msk      (0x1U << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R2_FB29_Pos      (29U)\n#define CAN_F7R2_FB29_Msk      (0x1U << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R2_FB30_Pos      (30U)\n#define CAN_F7R2_FB30_Msk      (0x1U << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R2_FB31_Pos      (31U)\n#define CAN_F7R2_FB31_Msk      (0x1U << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R2 register  *******************/\n#define CAN_F8R2_FB0_Pos       (0U)\n#define CAN_F8R2_FB0_Msk       (0x1U << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R2_FB1_Pos       (1U)\n#define CAN_F8R2_FB1_Msk       (0x1U << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R2_FB2_Pos       (2U)\n#define CAN_F8R2_FB2_Msk       (0x1U << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R2_FB3_Pos       (3U)\n#define CAN_F8R2_FB3_Msk       (0x1U << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R2_FB4_Pos       (4U)\n#define CAN_F8R2_FB4_Msk       (0x1U << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R2_FB5_Pos       (5U)\n#define CAN_F8R2_FB5_Msk       (0x1U << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R2_FB6_Pos       (6U)\n#define CAN_F8R2_FB6_Msk       (0x1U << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R2_FB7_Pos       (7U)\n#define CAN_F8R2_FB7_Msk       (0x1U << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R2_FB8_Pos       (8U)\n#define CAN_F8R2_FB8_Msk       (0x1U << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R2_FB9_Pos       (9U)\n#define CAN_F8R2_FB9_Msk       (0x1U << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R2_FB10_Pos      (10U)\n#define CAN_F8R2_FB10_Msk      (0x1U << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R2_FB11_Pos      (11U)\n#define CAN_F8R2_FB11_Msk      (0x1U << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R2_FB12_Pos      (12U)\n#define CAN_F8R2_FB12_Msk      (0x1U << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R2_FB13_Pos      (13U)\n#define CAN_F8R2_FB13_Msk      (0x1U << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R2_FB14_Pos      (14U)\n#define CAN_F8R2_FB14_Msk      (0x1U << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R2_FB15_Pos      (15U)\n#define CAN_F8R2_FB15_Msk      (0x1U << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R2_FB16_Pos      (16U)\n#define CAN_F8R2_FB16_Msk      (0x1U << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R2_FB17_Pos      (17U)\n#define CAN_F8R2_FB17_Msk      (0x1U << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R2_FB18_Pos      (18U)\n#define CAN_F8R2_FB18_Msk      (0x1U << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R2_FB19_Pos      (19U)\n#define CAN_F8R2_FB19_Msk      (0x1U << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R2_FB20_Pos      (20U)\n#define CAN_F8R2_FB20_Msk      (0x1U << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R2_FB21_Pos      (21U)\n#define CAN_F8R2_FB21_Msk      (0x1U << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R2_FB22_Pos      (22U)\n#define CAN_F8R2_FB22_Msk      (0x1U << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R2_FB23_Pos      (23U)\n#define CAN_F8R2_FB23_Msk      (0x1U << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R2_FB24_Pos      (24U)\n#define CAN_F8R2_FB24_Msk      (0x1U << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R2_FB25_Pos      (25U)\n#define CAN_F8R2_FB25_Msk      (0x1U << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R2_FB26_Pos      (26U)\n#define CAN_F8R2_FB26_Msk      (0x1U << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R2_FB27_Pos      (27U)\n#define CAN_F8R2_FB27_Msk      (0x1U << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R2_FB28_Pos      (28U)\n#define CAN_F8R2_FB28_Msk      (0x1U << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R2_FB29_Pos      (29U)\n#define CAN_F8R2_FB29_Msk      (0x1U << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R2_FB30_Pos      (30U)\n#define CAN_F8R2_FB30_Msk      (0x1U << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R2_FB31_Pos      (31U)\n#define CAN_F8R2_FB31_Msk      (0x1U << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R2 register  *******************/\n#define CAN_F9R2_FB0_Pos       (0U)\n#define CAN_F9R2_FB0_Msk       (0x1U << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R2_FB1_Pos       (1U)\n#define CAN_F9R2_FB1_Msk       (0x1U << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R2_FB2_Pos       (2U)\n#define CAN_F9R2_FB2_Msk       (0x1U << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R2_FB3_Pos       (3U)\n#define CAN_F9R2_FB3_Msk       (0x1U << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R2_FB4_Pos       (4U)\n#define CAN_F9R2_FB4_Msk       (0x1U << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R2_FB5_Pos       (5U)\n#define CAN_F9R2_FB5_Msk       (0x1U << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R2_FB6_Pos       (6U)\n#define CAN_F9R2_FB6_Msk       (0x1U << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R2_FB7_Pos       (7U)\n#define CAN_F9R2_FB7_Msk       (0x1U << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R2_FB8_Pos       (8U)\n#define CAN_F9R2_FB8_Msk       (0x1U << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R2_FB9_Pos       (9U)\n#define CAN_F9R2_FB9_Msk       (0x1U << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R2_FB10_Pos      (10U)\n#define CAN_F9R2_FB10_Msk      (0x1U << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R2_FB11_Pos      (11U)\n#define CAN_F9R2_FB11_Msk      (0x1U << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R2_FB12_Pos      (12U)\n#define CAN_F9R2_FB12_Msk      (0x1U << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R2_FB13_Pos      (13U)\n#define CAN_F9R2_FB13_Msk      (0x1U << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R2_FB14_Pos      (14U)\n#define CAN_F9R2_FB14_Msk      (0x1U << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R2_FB15_Pos      (15U)\n#define CAN_F9R2_FB15_Msk      (0x1U << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R2_FB16_Pos      (16U)\n#define CAN_F9R2_FB16_Msk      (0x1U << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R2_FB17_Pos      (17U)\n#define CAN_F9R2_FB17_Msk      (0x1U << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R2_FB18_Pos      (18U)\n#define CAN_F9R2_FB18_Msk      (0x1U << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R2_FB19_Pos      (19U)\n#define CAN_F9R2_FB19_Msk      (0x1U << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R2_FB20_Pos      (20U)\n#define CAN_F9R2_FB20_Msk      (0x1U << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R2_FB21_Pos      (21U)\n#define CAN_F9R2_FB21_Msk      (0x1U << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R2_FB22_Pos      (22U)\n#define CAN_F9R2_FB22_Msk      (0x1U << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R2_FB23_Pos      (23U)\n#define CAN_F9R2_FB23_Msk      (0x1U << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R2_FB24_Pos      (24U)\n#define CAN_F9R2_FB24_Msk      (0x1U << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R2_FB25_Pos      (25U)\n#define CAN_F9R2_FB25_Msk      (0x1U << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R2_FB26_Pos      (26U)\n#define CAN_F9R2_FB26_Msk      (0x1U << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R2_FB27_Pos      (27U)\n#define CAN_F9R2_FB27_Msk      (0x1U << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R2_FB28_Pos      (28U)\n#define CAN_F9R2_FB28_Msk      (0x1U << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R2_FB29_Pos      (29U)\n#define CAN_F9R2_FB29_Msk      (0x1U << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R2_FB30_Pos      (30U)\n#define CAN_F9R2_FB30_Msk      (0x1U << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R2_FB31_Pos      (31U)\n#define CAN_F9R2_FB31_Msk      (0x1U << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R2 register  ******************/\n#define CAN_F10R2_FB0_Pos      (0U)\n#define CAN_F10R2_FB0_Msk      (0x1U << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R2_FB1_Pos      (1U)\n#define CAN_F10R2_FB1_Msk      (0x1U << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R2_FB2_Pos      (2U)\n#define CAN_F10R2_FB2_Msk      (0x1U << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R2_FB3_Pos      (3U)\n#define CAN_F10R2_FB3_Msk      (0x1U << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R2_FB4_Pos      (4U)\n#define CAN_F10R2_FB4_Msk      (0x1U << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R2_FB5_Pos      (5U)\n#define CAN_F10R2_FB5_Msk      (0x1U << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R2_FB6_Pos      (6U)\n#define CAN_F10R2_FB6_Msk      (0x1U << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R2_FB7_Pos      (7U)\n#define CAN_F10R2_FB7_Msk      (0x1U << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R2_FB8_Pos      (8U)\n#define CAN_F10R2_FB8_Msk      (0x1U << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R2_FB9_Pos      (9U)\n#define CAN_F10R2_FB9_Msk      (0x1U << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R2_FB10_Pos     (10U)\n#define CAN_F10R2_FB10_Msk     (0x1U << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R2_FB11_Pos     (11U)\n#define CAN_F10R2_FB11_Msk     (0x1U << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R2_FB12_Pos     (12U)\n#define CAN_F10R2_FB12_Msk     (0x1U << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R2_FB13_Pos     (13U)\n#define CAN_F10R2_FB13_Msk     (0x1U << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R2_FB14_Pos     (14U)\n#define CAN_F10R2_FB14_Msk     (0x1U << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R2_FB15_Pos     (15U)\n#define CAN_F10R2_FB15_Msk     (0x1U << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R2_FB16_Pos     (16U)\n#define CAN_F10R2_FB16_Msk     (0x1U << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R2_FB17_Pos     (17U)\n#define CAN_F10R2_FB17_Msk     (0x1U << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R2_FB18_Pos     (18U)\n#define CAN_F10R2_FB18_Msk     (0x1U << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R2_FB19_Pos     (19U)\n#define CAN_F10R2_FB19_Msk     (0x1U << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R2_FB20_Pos     (20U)\n#define CAN_F10R2_FB20_Msk     (0x1U << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R2_FB21_Pos     (21U)\n#define CAN_F10R2_FB21_Msk     (0x1U << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R2_FB22_Pos     (22U)\n#define CAN_F10R2_FB22_Msk     (0x1U << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R2_FB23_Pos     (23U)\n#define CAN_F10R2_FB23_Msk     (0x1U << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R2_FB24_Pos     (24U)\n#define CAN_F10R2_FB24_Msk     (0x1U << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R2_FB25_Pos     (25U)\n#define CAN_F10R2_FB25_Msk     (0x1U << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R2_FB26_Pos     (26U)\n#define CAN_F10R2_FB26_Msk     (0x1U << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R2_FB27_Pos     (27U)\n#define CAN_F10R2_FB27_Msk     (0x1U << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R2_FB28_Pos     (28U)\n#define CAN_F10R2_FB28_Msk     (0x1U << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R2_FB29_Pos     (29U)\n#define CAN_F10R2_FB29_Msk     (0x1U << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R2_FB30_Pos     (30U)\n#define CAN_F10R2_FB30_Msk     (0x1U << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R2_FB31_Pos     (31U)\n#define CAN_F10R2_FB31_Msk     (0x1U << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R2 register  ******************/\n#define CAN_F11R2_FB0_Pos      (0U)\n#define CAN_F11R2_FB0_Msk      (0x1U << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R2_FB1_Pos      (1U)\n#define CAN_F11R2_FB1_Msk      (0x1U << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R2_FB2_Pos      (2U)\n#define CAN_F11R2_FB2_Msk      (0x1U << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R2_FB3_Pos      (3U)\n#define CAN_F11R2_FB3_Msk      (0x1U << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R2_FB4_Pos      (4U)\n#define CAN_F11R2_FB4_Msk      (0x1U << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R2_FB5_Pos      (5U)\n#define CAN_F11R2_FB5_Msk      (0x1U << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R2_FB6_Pos      (6U)\n#define CAN_F11R2_FB6_Msk      (0x1U << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R2_FB7_Pos      (7U)\n#define CAN_F11R2_FB7_Msk      (0x1U << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R2_FB8_Pos      (8U)\n#define CAN_F11R2_FB8_Msk      (0x1U << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R2_FB9_Pos      (9U)\n#define CAN_F11R2_FB9_Msk      (0x1U << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R2_FB10_Pos     (10U)\n#define CAN_F11R2_FB10_Msk     (0x1U << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R2_FB11_Pos     (11U)\n#define CAN_F11R2_FB11_Msk     (0x1U << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R2_FB12_Pos     (12U)\n#define CAN_F11R2_FB12_Msk     (0x1U << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R2_FB13_Pos     (13U)\n#define CAN_F11R2_FB13_Msk     (0x1U << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R2_FB14_Pos     (14U)\n#define CAN_F11R2_FB14_Msk     (0x1U << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R2_FB15_Pos     (15U)\n#define CAN_F11R2_FB15_Msk     (0x1U << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R2_FB16_Pos     (16U)\n#define CAN_F11R2_FB16_Msk     (0x1U << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R2_FB17_Pos     (17U)\n#define CAN_F11R2_FB17_Msk     (0x1U << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R2_FB18_Pos     (18U)\n#define CAN_F11R2_FB18_Msk     (0x1U << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R2_FB19_Pos     (19U)\n#define CAN_F11R2_FB19_Msk     (0x1U << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R2_FB20_Pos     (20U)\n#define CAN_F11R2_FB20_Msk     (0x1U << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R2_FB21_Pos     (21U)\n#define CAN_F11R2_FB21_Msk     (0x1U << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R2_FB22_Pos     (22U)\n#define CAN_F11R2_FB22_Msk     (0x1U << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R2_FB23_Pos     (23U)\n#define CAN_F11R2_FB23_Msk     (0x1U << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R2_FB24_Pos     (24U)\n#define CAN_F11R2_FB24_Msk     (0x1U << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R2_FB25_Pos     (25U)\n#define CAN_F11R2_FB25_Msk     (0x1U << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R2_FB26_Pos     (26U)\n#define CAN_F11R2_FB26_Msk     (0x1U << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R2_FB27_Pos     (27U)\n#define CAN_F11R2_FB27_Msk     (0x1U << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R2_FB28_Pos     (28U)\n#define CAN_F11R2_FB28_Msk     (0x1U << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R2_FB29_Pos     (29U)\n#define CAN_F11R2_FB29_Msk     (0x1U << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R2_FB30_Pos     (30U)\n#define CAN_F11R2_FB30_Msk     (0x1U << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R2_FB31_Pos     (31U)\n#define CAN_F11R2_FB31_Msk     (0x1U << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R2 register  ******************/\n#define CAN_F12R2_FB0_Pos      (0U)\n#define CAN_F12R2_FB0_Msk      (0x1U << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R2_FB1_Pos      (1U)\n#define CAN_F12R2_FB1_Msk      (0x1U << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R2_FB2_Pos      (2U)\n#define CAN_F12R2_FB2_Msk      (0x1U << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R2_FB3_Pos      (3U)\n#define CAN_F12R2_FB3_Msk      (0x1U << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R2_FB4_Pos      (4U)\n#define CAN_F12R2_FB4_Msk      (0x1U << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R2_FB5_Pos      (5U)\n#define CAN_F12R2_FB5_Msk      (0x1U << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R2_FB6_Pos      (6U)\n#define CAN_F12R2_FB6_Msk      (0x1U << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R2_FB7_Pos      (7U)\n#define CAN_F12R2_FB7_Msk      (0x1U << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R2_FB8_Pos      (8U)\n#define CAN_F12R2_FB8_Msk      (0x1U << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R2_FB9_Pos      (9U)\n#define CAN_F12R2_FB9_Msk      (0x1U << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R2_FB10_Pos     (10U)\n#define CAN_F12R2_FB10_Msk     (0x1U << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R2_FB11_Pos     (11U)\n#define CAN_F12R2_FB11_Msk     (0x1U << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R2_FB12_Pos     (12U)\n#define CAN_F12R2_FB12_Msk     (0x1U << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R2_FB13_Pos     (13U)\n#define CAN_F12R2_FB13_Msk     (0x1U << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R2_FB14_Pos     (14U)\n#define CAN_F12R2_FB14_Msk     (0x1U << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R2_FB15_Pos     (15U)\n#define CAN_F12R2_FB15_Msk     (0x1U << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R2_FB16_Pos     (16U)\n#define CAN_F12R2_FB16_Msk     (0x1U << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R2_FB17_Pos     (17U)\n#define CAN_F12R2_FB17_Msk     (0x1U << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R2_FB18_Pos     (18U)\n#define CAN_F12R2_FB18_Msk     (0x1U << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R2_FB19_Pos     (19U)\n#define CAN_F12R2_FB19_Msk     (0x1U << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R2_FB20_Pos     (20U)\n#define CAN_F12R2_FB20_Msk     (0x1U << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R2_FB21_Pos     (21U)\n#define CAN_F12R2_FB21_Msk     (0x1U << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R2_FB22_Pos     (22U)\n#define CAN_F12R2_FB22_Msk     (0x1U << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R2_FB23_Pos     (23U)\n#define CAN_F12R2_FB23_Msk     (0x1U << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R2_FB24_Pos     (24U)\n#define CAN_F12R2_FB24_Msk     (0x1U << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R2_FB25_Pos     (25U)\n#define CAN_F12R2_FB25_Msk     (0x1U << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R2_FB26_Pos     (26U)\n#define CAN_F12R2_FB26_Msk     (0x1U << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R2_FB27_Pos     (27U)\n#define CAN_F12R2_FB27_Msk     (0x1U << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R2_FB28_Pos     (28U)\n#define CAN_F12R2_FB28_Msk     (0x1U << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R2_FB29_Pos     (29U)\n#define CAN_F12R2_FB29_Msk     (0x1U << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R2_FB30_Pos     (30U)\n#define CAN_F12R2_FB30_Msk     (0x1U << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R2_FB31_Pos     (31U)\n#define CAN_F12R2_FB31_Msk     (0x1U << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R2 register  ******************/\n#define CAN_F13R2_FB0_Pos      (0U)\n#define CAN_F13R2_FB0_Msk      (0x1U << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R2_FB1_Pos      (1U)\n#define CAN_F13R2_FB1_Msk      (0x1U << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R2_FB2_Pos      (2U)\n#define CAN_F13R2_FB2_Msk      (0x1U << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R2_FB3_Pos      (3U)\n#define CAN_F13R2_FB3_Msk      (0x1U << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R2_FB4_Pos      (4U)\n#define CAN_F13R2_FB4_Msk      (0x1U << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R2_FB5_Pos      (5U)\n#define CAN_F13R2_FB5_Msk      (0x1U << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R2_FB6_Pos      (6U)\n#define CAN_F13R2_FB6_Msk      (0x1U << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R2_FB7_Pos      (7U)\n#define CAN_F13R2_FB7_Msk      (0x1U << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R2_FB8_Pos      (8U)\n#define CAN_F13R2_FB8_Msk      (0x1U << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R2_FB9_Pos      (9U)\n#define CAN_F13R2_FB9_Msk      (0x1U << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R2_FB10_Pos     (10U)\n#define CAN_F13R2_FB10_Msk     (0x1U << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R2_FB11_Pos     (11U)\n#define CAN_F13R2_FB11_Msk     (0x1U << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R2_FB12_Pos     (12U)\n#define CAN_F13R2_FB12_Msk     (0x1U << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R2_FB13_Pos     (13U)\n#define CAN_F13R2_FB13_Msk     (0x1U << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R2_FB14_Pos     (14U)\n#define CAN_F13R2_FB14_Msk     (0x1U << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R2_FB15_Pos     (15U)\n#define CAN_F13R2_FB15_Msk     (0x1U << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R2_FB16_Pos     (16U)\n#define CAN_F13R2_FB16_Msk     (0x1U << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R2_FB17_Pos     (17U)\n#define CAN_F13R2_FB17_Msk     (0x1U << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R2_FB18_Pos     (18U)\n#define CAN_F13R2_FB18_Msk     (0x1U << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R2_FB19_Pos     (19U)\n#define CAN_F13R2_FB19_Msk     (0x1U << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R2_FB20_Pos     (20U)\n#define CAN_F13R2_FB20_Msk     (0x1U << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R2_FB21_Pos     (21U)\n#define CAN_F13R2_FB21_Msk     (0x1U << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R2_FB22_Pos     (22U)\n#define CAN_F13R2_FB22_Msk     (0x1U << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R2_FB23_Pos     (23U)\n#define CAN_F13R2_FB23_Msk     (0x1U << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R2_FB24_Pos     (24U)\n#define CAN_F13R2_FB24_Msk     (0x1U << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R2_FB25_Pos     (25U)\n#define CAN_F13R2_FB25_Msk     (0x1U << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R2_FB26_Pos     (26U)\n#define CAN_F13R2_FB26_Msk     (0x1U << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R2_FB27_Pos     (27U)\n#define CAN_F13R2_FB27_Msk     (0x1U << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R2_FB28_Pos     (28U)\n#define CAN_F13R2_FB28_Msk     (0x1U << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R2_FB29_Pos     (29U)\n#define CAN_F13R2_FB29_Msk     (0x1U << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R2_FB30_Pos     (30U)\n#define CAN_F13R2_FB30_Msk     (0x1U << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R2_FB31_Pos     (31U)\n#define CAN_F13R2_FB31_Msk     (0x1U << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          CRC calculation unit                              */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for CRC_DR register  *********************/\n#define CRC_DR_DR_Pos       (0U)\n#define CRC_DR_DR_Msk       (0xFFFFFFFFU << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */\n#define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */\n\n\n/*******************  Bit definition for CRC_IDR register  ********************/\n#define CRC_IDR_IDR_Pos     (0U)\n#define CRC_IDR_IDR_Msk     (0xFFU << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */\n#define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */\n\n\n/********************  Bit definition for CRC_CR register  ********************/\n#define CRC_CR_RESET_Pos    (0U)\n#define CRC_CR_RESET_Msk    (0x1U << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */\n#define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Digital to Analog Converter                           */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define DAC_CHANNEL2_SUPPORT                                    /*!< DAC feature available only on specific devices: availability of DAC channel 2 */\n/********************  Bit definition for DAC_CR register  ********************/\n#define DAC_CR_EN1_Pos              (0U)\n#define DAC_CR_EN1_Msk              (0x1U << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */\n#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */\n#define DAC_CR_BOFF1_Pos            (1U)\n#define DAC_CR_BOFF1_Msk            (0x1U << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */\n#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable */\n#define DAC_CR_TEN1_Pos             (2U)\n#define DAC_CR_TEN1_Msk             (0x1U << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */\n#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */\n\n#define DAC_CR_TSEL1_Pos            (3U)\n#define DAC_CR_TSEL1_Msk            (0x7U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */\n#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\n#define DAC_CR_TSEL1_0              (0x1U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */\n#define DAC_CR_TSEL1_1              (0x2U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */\n#define DAC_CR_TSEL1_2              (0x4U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */\n\n#define DAC_CR_WAVE1_Pos            (6U)\n#define DAC_CR_WAVE1_Msk            (0x3U << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */\n#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE1_0              (0x1U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */\n#define DAC_CR_WAVE1_1              (0x2U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */\n\n#define DAC_CR_MAMP1_Pos            (8U)\n#define DAC_CR_MAMP1_Msk            (0xFU << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */\n#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\n#define DAC_CR_MAMP1_0              (0x1U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */\n#define DAC_CR_MAMP1_1              (0x2U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */\n#define DAC_CR_MAMP1_2              (0x4U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */\n#define DAC_CR_MAMP1_3              (0x8U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */\n\n#define DAC_CR_DMAEN1_Pos           (12U)\n#define DAC_CR_DMAEN1_Msk           (0x1U << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */\n#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */\n#define DAC_CR_DMAUDRIE1_Pos        (13U)\n#define DAC_CR_DMAUDRIE1_Msk        (0x1U << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */\n#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable*/\n#define DAC_CR_EN2_Pos              (16U)\n#define DAC_CR_EN2_Msk              (0x1U << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */\n#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */\n#define DAC_CR_BOFF2_Pos            (17U)\n#define DAC_CR_BOFF2_Msk            (0x1U << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */\n#define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable */\n#define DAC_CR_TEN2_Pos             (18U)\n#define DAC_CR_TEN2_Msk             (0x1U << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */\n#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */\n\n#define DAC_CR_TSEL2_Pos            (19U)\n#define DAC_CR_TSEL2_Msk            (0x7U << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */\n#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\n#define DAC_CR_TSEL2_0              (0x1U << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */\n#define DAC_CR_TSEL2_1              (0x2U << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */\n#define DAC_CR_TSEL2_2              (0x4U << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */\n\n#define DAC_CR_WAVE2_Pos            (22U)\n#define DAC_CR_WAVE2_Msk            (0x3U << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */\n#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE2_0              (0x1U << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */\n#define DAC_CR_WAVE2_1              (0x2U << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */\n\n#define DAC_CR_MAMP2_Pos            (24U)\n#define DAC_CR_MAMP2_Msk            (0xFU << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */\n#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\n#define DAC_CR_MAMP2_0              (0x1U << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */\n#define DAC_CR_MAMP2_1              (0x2U << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */\n#define DAC_CR_MAMP2_2              (0x4U << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */\n#define DAC_CR_MAMP2_3              (0x8U << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */\n\n#define DAC_CR_DMAEN2_Pos           (28U)\n#define DAC_CR_DMAEN2_Msk           (0x1U << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */\n#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */\n#define DAC_CR_DMAUDRIE2_Pos        (29U)\n#define DAC_CR_DMAUDRIE2_Msk        (0x1U << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */\n#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable*/\n\n/*****************  Bit definition for DAC_SWTRIGR register  ******************/\n#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)\n#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */\n#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */\n#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)\n#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1U << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */\n#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */\n\n/*****************  Bit definition for DAC_DHR12R1 register  ******************/\n#define DAC_DHR12R1_DACC1DHR_Pos    (0U)\n#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L1 register  ******************/\n#define DAC_DHR12L1_DACC1DHR_Pos    (4U)\n#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R1 register  ******************/\n#define DAC_DHR8R1_DACC1DHR_Pos     (0U)\n#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12R2 register  ******************/\n#define DAC_DHR12R2_DACC2DHR_Pos    (0U)\n#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L2 register  ******************/\n#define DAC_DHR12L2_DACC2DHR_Pos    (4U)\n#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R2 register  ******************/\n#define DAC_DHR8R2_DACC2DHR_Pos     (0U)\n#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFU << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12RD register  ******************/\n#define DAC_DHR12RD_DACC1DHR_Pos    (0U)\n#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\n#define DAC_DHR12RD_DACC2DHR_Pos    (16U)\n#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */\n#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12LD register  ******************/\n#define DAC_DHR12LD_DACC1DHR_Pos    (4U)\n#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\n#define DAC_DHR12LD_DACC2DHR_Pos    (20U)\n#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */\n#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8RD register  ******************/\n#define DAC_DHR8RD_DACC1DHR_Pos     (0U)\n#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFU << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\n#define DAC_DHR8RD_DACC2DHR_Pos     (8U)\n#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFU << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */\n#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\n\n/*******************  Bit definition for DAC_DOR1 register  *******************/\n#define DAC_DOR1_DACC1DOR_Pos       (0U)\n#define DAC_DOR1_DACC1DOR_Msk       (0xFFFU << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */\n#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */\n\n/*******************  Bit definition for DAC_DOR2 register  *******************/\n#define DAC_DOR2_DACC2DOR_Pos       (0U)\n#define DAC_DOR2_DACC2DOR_Msk       (0xFFFU << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */\n#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */\n\n/********************  Bit definition for DAC_SR register  ********************/\n#define DAC_SR_DMAUDR1_Pos          (13U)\n#define DAC_SR_DMAUDR1_Msk          (0x1U << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */\n#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */\n#define DAC_SR_DMAUDR2_Pos          (29U)\n#define DAC_SR_DMAUDR2_Msk          (0x1U << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */\n#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    DCMI                                    */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DCMI_CR register  ******************/\n#define DCMI_CR_CAPTURE_Pos        (0U)\n#define DCMI_CR_CAPTURE_Msk        (0x1U << DCMI_CR_CAPTURE_Pos)               /*!< 0x00000001 */\n#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk\n#define DCMI_CR_CM_Pos             (1U)\n#define DCMI_CR_CM_Msk             (0x1U << DCMI_CR_CM_Pos)                    /*!< 0x00000002 */\n#define DCMI_CR_CM                 DCMI_CR_CM_Msk\n#define DCMI_CR_CROP_Pos           (2U)\n#define DCMI_CR_CROP_Msk           (0x1U << DCMI_CR_CROP_Pos)                  /*!< 0x00000004 */\n#define DCMI_CR_CROP               DCMI_CR_CROP_Msk\n#define DCMI_CR_JPEG_Pos           (3U)\n#define DCMI_CR_JPEG_Msk           (0x1U << DCMI_CR_JPEG_Pos)                  /*!< 0x00000008 */\n#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk\n#define DCMI_CR_ESS_Pos            (4U)\n#define DCMI_CR_ESS_Msk            (0x1U << DCMI_CR_ESS_Pos)                   /*!< 0x00000010 */\n#define DCMI_CR_ESS                DCMI_CR_ESS_Msk\n#define DCMI_CR_PCKPOL_Pos         (5U)\n#define DCMI_CR_PCKPOL_Msk         (0x1U << DCMI_CR_PCKPOL_Pos)                /*!< 0x00000020 */\n#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk\n#define DCMI_CR_HSPOL_Pos          (6U)\n#define DCMI_CR_HSPOL_Msk          (0x1U << DCMI_CR_HSPOL_Pos)                 /*!< 0x00000040 */\n#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk\n#define DCMI_CR_VSPOL_Pos          (7U)\n#define DCMI_CR_VSPOL_Msk          (0x1U << DCMI_CR_VSPOL_Pos)                 /*!< 0x00000080 */\n#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk\n#define DCMI_CR_FCRC_0             0x00000100U\n#define DCMI_CR_FCRC_1             0x00000200U\n#define DCMI_CR_EDM_0              0x00000400U\n#define DCMI_CR_EDM_1              0x00000800U\n#define DCMI_CR_CRE_Pos            (12U)\n#define DCMI_CR_CRE_Msk            (0x1U << DCMI_CR_CRE_Pos)                   /*!< 0x00001000 */\n#define DCMI_CR_CRE                DCMI_CR_CRE_Msk\n#define DCMI_CR_ENABLE_Pos         (14U)\n#define DCMI_CR_ENABLE_Msk         (0x1U << DCMI_CR_ENABLE_Pos)                /*!< 0x00004000 */\n#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk\n\n/********************  Bits definition for DCMI_SR register  ******************/\n#define DCMI_SR_HSYNC_Pos          (0U)\n#define DCMI_SR_HSYNC_Msk          (0x1U << DCMI_SR_HSYNC_Pos)                 /*!< 0x00000001 */\n#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk\n#define DCMI_SR_VSYNC_Pos          (1U)\n#define DCMI_SR_VSYNC_Msk          (0x1U << DCMI_SR_VSYNC_Pos)                 /*!< 0x00000002 */\n#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk\n#define DCMI_SR_FNE_Pos            (2U)\n#define DCMI_SR_FNE_Msk            (0x1U << DCMI_SR_FNE_Pos)                   /*!< 0x00000004 */\n#define DCMI_SR_FNE                DCMI_SR_FNE_Msk\n\n/********************  Bits definition for DCMI_RIS register  *****************/\n#define DCMI_RIS_FRAME_RIS_Pos     (0U)\n#define DCMI_RIS_FRAME_RIS_Msk     (0x1U << DCMI_RIS_FRAME_RIS_Pos)            /*!< 0x00000001 */\n#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk\n#define DCMI_RIS_OVR_RIS_Pos       (1U)\n#define DCMI_RIS_OVR_RIS_Msk       (0x1U << DCMI_RIS_OVR_RIS_Pos)              /*!< 0x00000002 */\n#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk\n#define DCMI_RIS_ERR_RIS_Pos       (2U)\n#define DCMI_RIS_ERR_RIS_Msk       (0x1U << DCMI_RIS_ERR_RIS_Pos)              /*!< 0x00000004 */\n#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk\n#define DCMI_RIS_VSYNC_RIS_Pos     (3U)\n#define DCMI_RIS_VSYNC_RIS_Msk     (0x1U << DCMI_RIS_VSYNC_RIS_Pos)            /*!< 0x00000008 */\n#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk\n#define DCMI_RIS_LINE_RIS_Pos      (4U)\n#define DCMI_RIS_LINE_RIS_Msk      (0x1U << DCMI_RIS_LINE_RIS_Pos)             /*!< 0x00000010 */\n#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk\n/* Legacy defines */\n#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS\n#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS\n#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS\n#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS\n#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS\n#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS\n\n/********************  Bits definition for DCMI_IER register  *****************/\n#define DCMI_IER_FRAME_IE_Pos      (0U)\n#define DCMI_IER_FRAME_IE_Msk      (0x1U << DCMI_IER_FRAME_IE_Pos)             /*!< 0x00000001 */\n#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk\n#define DCMI_IER_OVR_IE_Pos        (1U)\n#define DCMI_IER_OVR_IE_Msk        (0x1U << DCMI_IER_OVR_IE_Pos)               /*!< 0x00000002 */\n#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk\n#define DCMI_IER_ERR_IE_Pos        (2U)\n#define DCMI_IER_ERR_IE_Msk        (0x1U << DCMI_IER_ERR_IE_Pos)               /*!< 0x00000004 */\n#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk\n#define DCMI_IER_VSYNC_IE_Pos      (3U)\n#define DCMI_IER_VSYNC_IE_Msk      (0x1U << DCMI_IER_VSYNC_IE_Pos)             /*!< 0x00000008 */\n#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk\n#define DCMI_IER_LINE_IE_Pos       (4U)\n#define DCMI_IER_LINE_IE_Msk       (0x1U << DCMI_IER_LINE_IE_Pos)              /*!< 0x00000010 */\n#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk\n/* Legacy defines */\n#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE\n\n/********************  Bits definition for DCMI_MIS register  *****************/\n#define DCMI_MIS_FRAME_MIS_Pos     (0U)\n#define DCMI_MIS_FRAME_MIS_Msk     (0x1U << DCMI_MIS_FRAME_MIS_Pos)            /*!< 0x00000001 */\n#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk\n#define DCMI_MIS_OVR_MIS_Pos       (1U)\n#define DCMI_MIS_OVR_MIS_Msk       (0x1U << DCMI_MIS_OVR_MIS_Pos)              /*!< 0x00000002 */\n#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk\n#define DCMI_MIS_ERR_MIS_Pos       (2U)\n#define DCMI_MIS_ERR_MIS_Msk       (0x1U << DCMI_MIS_ERR_MIS_Pos)              /*!< 0x00000004 */\n#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk\n#define DCMI_MIS_VSYNC_MIS_Pos     (3U)\n#define DCMI_MIS_VSYNC_MIS_Msk     (0x1U << DCMI_MIS_VSYNC_MIS_Pos)            /*!< 0x00000008 */\n#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk\n#define DCMI_MIS_LINE_MIS_Pos      (4U)\n#define DCMI_MIS_LINE_MIS_Msk      (0x1U << DCMI_MIS_LINE_MIS_Pos)             /*!< 0x00000010 */\n#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk\n\n/* Legacy defines */\n#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS\n#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS\n#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS\n#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS\n#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS\n\n/********************  Bits definition for DCMI_ICR register  *****************/\n#define DCMI_ICR_FRAME_ISC_Pos     (0U)\n#define DCMI_ICR_FRAME_ISC_Msk     (0x1U << DCMI_ICR_FRAME_ISC_Pos)            /*!< 0x00000001 */\n#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk\n#define DCMI_ICR_OVR_ISC_Pos       (1U)\n#define DCMI_ICR_OVR_ISC_Msk       (0x1U << DCMI_ICR_OVR_ISC_Pos)              /*!< 0x00000002 */\n#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk\n#define DCMI_ICR_ERR_ISC_Pos       (2U)\n#define DCMI_ICR_ERR_ISC_Msk       (0x1U << DCMI_ICR_ERR_ISC_Pos)              /*!< 0x00000004 */\n#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk\n#define DCMI_ICR_VSYNC_ISC_Pos     (3U)\n#define DCMI_ICR_VSYNC_ISC_Msk     (0x1U << DCMI_ICR_VSYNC_ISC_Pos)            /*!< 0x00000008 */\n#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk\n#define DCMI_ICR_LINE_ISC_Pos      (4U)\n#define DCMI_ICR_LINE_ISC_Msk      (0x1U << DCMI_ICR_LINE_ISC_Pos)             /*!< 0x00000010 */\n#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk\n\n/* Legacy defines */\n#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC\n\n/********************  Bits definition for DCMI_ESCR register  ******************/\n#define DCMI_ESCR_FSC_Pos          (0U)\n#define DCMI_ESCR_FSC_Msk          (0xFFU << DCMI_ESCR_FSC_Pos)                /*!< 0x000000FF */\n#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk\n#define DCMI_ESCR_LSC_Pos          (8U)\n#define DCMI_ESCR_LSC_Msk          (0xFFU << DCMI_ESCR_LSC_Pos)                /*!< 0x0000FF00 */\n#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk\n#define DCMI_ESCR_LEC_Pos          (16U)\n#define DCMI_ESCR_LEC_Msk          (0xFFU << DCMI_ESCR_LEC_Pos)                /*!< 0x00FF0000 */\n#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk\n#define DCMI_ESCR_FEC_Pos          (24U)\n#define DCMI_ESCR_FEC_Msk          (0xFFU << DCMI_ESCR_FEC_Pos)                /*!< 0xFF000000 */\n#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk\n\n/********************  Bits definition for DCMI_ESUR register  ******************/\n#define DCMI_ESUR_FSU_Pos          (0U)\n#define DCMI_ESUR_FSU_Msk          (0xFFU << DCMI_ESUR_FSU_Pos)                /*!< 0x000000FF */\n#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk\n#define DCMI_ESUR_LSU_Pos          (8U)\n#define DCMI_ESUR_LSU_Msk          (0xFFU << DCMI_ESUR_LSU_Pos)                /*!< 0x0000FF00 */\n#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk\n#define DCMI_ESUR_LEU_Pos          (16U)\n#define DCMI_ESUR_LEU_Msk          (0xFFU << DCMI_ESUR_LEU_Pos)                /*!< 0x00FF0000 */\n#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk\n#define DCMI_ESUR_FEU_Pos          (24U)\n#define DCMI_ESUR_FEU_Msk          (0xFFU << DCMI_ESUR_FEU_Pos)                /*!< 0xFF000000 */\n#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk\n\n/********************  Bits definition for DCMI_CWSTRT register  ******************/\n#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)\n#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos)        /*!< 0x00003FFF */\n#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk\n#define DCMI_CWSTRT_VST_Pos        (16U)\n#define DCMI_CWSTRT_VST_Msk        (0x1FFFU << DCMI_CWSTRT_VST_Pos)            /*!< 0x1FFF0000 */\n#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk\n\n/********************  Bits definition for DCMI_CWSIZE register  ******************/\n#define DCMI_CWSIZE_CAPCNT_Pos     (0U)\n#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos)         /*!< 0x00003FFF */\n#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk\n#define DCMI_CWSIZE_VLINE_Pos      (16U)\n#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFU << DCMI_CWSIZE_VLINE_Pos)          /*!< 0x3FFF0000 */\n#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk\n\n/********************  Bits definition for DCMI_DR register  *********************/\n#define DCMI_DR_BYTE0_Pos          (0U)\n#define DCMI_DR_BYTE0_Msk          (0xFFU << DCMI_DR_BYTE0_Pos)                /*!< 0x000000FF */\n#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk\n#define DCMI_DR_BYTE1_Pos          (8U)\n#define DCMI_DR_BYTE1_Msk          (0xFFU << DCMI_DR_BYTE1_Pos)                /*!< 0x0000FF00 */\n#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk\n#define DCMI_DR_BYTE2_Pos          (16U)\n#define DCMI_DR_BYTE2_Msk          (0xFFU << DCMI_DR_BYTE2_Pos)                /*!< 0x00FF0000 */\n#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk\n#define DCMI_DR_BYTE3_Pos          (24U)\n#define DCMI_DR_BYTE3_Msk          (0xFFU << DCMI_DR_BYTE3_Pos)                /*!< 0xFF000000 */\n#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                             DMA Controller                                 */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DMA_SxCR register  *****************/\n#define DMA_SxCR_CHSEL_Pos       (25U)\n#define DMA_SxCR_CHSEL_Msk       (0x7U << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */\n#define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk\n#define DMA_SxCR_CHSEL_0         0x02000000U\n#define DMA_SxCR_CHSEL_1         0x04000000U\n#define DMA_SxCR_CHSEL_2         0x08000000U\n#define DMA_SxCR_MBURST_Pos      (23U)\n#define DMA_SxCR_MBURST_Msk      (0x3U << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */\n#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk\n#define DMA_SxCR_MBURST_0        (0x1U << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */\n#define DMA_SxCR_MBURST_1        (0x2U << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */\n#define DMA_SxCR_PBURST_Pos      (21U)\n#define DMA_SxCR_PBURST_Msk      (0x3U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */\n#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk\n#define DMA_SxCR_PBURST_0        (0x1U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */\n#define DMA_SxCR_PBURST_1        (0x2U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */\n#define DMA_SxCR_CT_Pos          (19U)\n#define DMA_SxCR_CT_Msk          (0x1U << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */\n#define DMA_SxCR_CT              DMA_SxCR_CT_Msk\n#define DMA_SxCR_DBM_Pos         (18U)\n#define DMA_SxCR_DBM_Msk         (0x1U << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */\n#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk\n#define DMA_SxCR_PL_Pos          (16U)\n#define DMA_SxCR_PL_Msk          (0x3U << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */\n#define DMA_SxCR_PL              DMA_SxCR_PL_Msk\n#define DMA_SxCR_PL_0            (0x1U << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */\n#define DMA_SxCR_PL_1            (0x2U << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */\n#define DMA_SxCR_PINCOS_Pos      (15U)\n#define DMA_SxCR_PINCOS_Msk      (0x1U << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */\n#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk\n#define DMA_SxCR_MSIZE_Pos       (13U)\n#define DMA_SxCR_MSIZE_Msk       (0x3U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */\n#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk\n#define DMA_SxCR_MSIZE_0         (0x1U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */\n#define DMA_SxCR_MSIZE_1         (0x2U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */\n#define DMA_SxCR_PSIZE_Pos       (11U)\n#define DMA_SxCR_PSIZE_Msk       (0x3U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */\n#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk\n#define DMA_SxCR_PSIZE_0         (0x1U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */\n#define DMA_SxCR_PSIZE_1         (0x2U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */\n#define DMA_SxCR_MINC_Pos        (10U)\n#define DMA_SxCR_MINC_Msk        (0x1U << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */\n#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk\n#define DMA_SxCR_PINC_Pos        (9U)\n#define DMA_SxCR_PINC_Msk        (0x1U << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */\n#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk\n#define DMA_SxCR_CIRC_Pos        (8U)\n#define DMA_SxCR_CIRC_Msk        (0x1U << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */\n#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk\n#define DMA_SxCR_DIR_Pos         (6U)\n#define DMA_SxCR_DIR_Msk         (0x3U << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */\n#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk\n#define DMA_SxCR_DIR_0           (0x1U << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */\n#define DMA_SxCR_DIR_1           (0x2U << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */\n#define DMA_SxCR_PFCTRL_Pos      (5U)\n#define DMA_SxCR_PFCTRL_Msk      (0x1U << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */\n#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk\n#define DMA_SxCR_TCIE_Pos        (4U)\n#define DMA_SxCR_TCIE_Msk        (0x1U << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */\n#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk\n#define DMA_SxCR_HTIE_Pos        (3U)\n#define DMA_SxCR_HTIE_Msk        (0x1U << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */\n#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk\n#define DMA_SxCR_TEIE_Pos        (2U)\n#define DMA_SxCR_TEIE_Msk        (0x1U << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */\n#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk\n#define DMA_SxCR_DMEIE_Pos       (1U)\n#define DMA_SxCR_DMEIE_Msk       (0x1U << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */\n#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk\n#define DMA_SxCR_EN_Pos          (0U)\n#define DMA_SxCR_EN_Msk          (0x1U << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */\n#define DMA_SxCR_EN              DMA_SxCR_EN_Msk\n\n/* Legacy defines */\n#define DMA_SxCR_ACK_Pos         (20U)\n#define DMA_SxCR_ACK_Msk         (0x1U << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */\n#define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk\n\n/********************  Bits definition for DMA_SxCNDTR register  **************/\n#define DMA_SxNDT_Pos            (0U)\n#define DMA_SxNDT_Msk            (0xFFFFU << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */\n#define DMA_SxNDT                DMA_SxNDT_Msk\n#define DMA_SxNDT_0              (0x0001U << DMA_SxNDT_Pos)                    /*!< 0x00000001 */\n#define DMA_SxNDT_1              (0x0002U << DMA_SxNDT_Pos)                    /*!< 0x00000002 */\n#define DMA_SxNDT_2              (0x0004U << DMA_SxNDT_Pos)                    /*!< 0x00000004 */\n#define DMA_SxNDT_3              (0x0008U << DMA_SxNDT_Pos)                    /*!< 0x00000008 */\n#define DMA_SxNDT_4              (0x0010U << DMA_SxNDT_Pos)                    /*!< 0x00000010 */\n#define DMA_SxNDT_5              (0x0020U << DMA_SxNDT_Pos)                    /*!< 0x00000020 */\n#define DMA_SxNDT_6              (0x0040U << DMA_SxNDT_Pos)                    /*!< 0x00000040 */\n#define DMA_SxNDT_7              (0x0080U << DMA_SxNDT_Pos)                    /*!< 0x00000080 */\n#define DMA_SxNDT_8              (0x0100U << DMA_SxNDT_Pos)                    /*!< 0x00000100 */\n#define DMA_SxNDT_9              (0x0200U << DMA_SxNDT_Pos)                    /*!< 0x00000200 */\n#define DMA_SxNDT_10             (0x0400U << DMA_SxNDT_Pos)                    /*!< 0x00000400 */\n#define DMA_SxNDT_11             (0x0800U << DMA_SxNDT_Pos)                    /*!< 0x00000800 */\n#define DMA_SxNDT_12             (0x1000U << DMA_SxNDT_Pos)                    /*!< 0x00001000 */\n#define DMA_SxNDT_13             (0x2000U << DMA_SxNDT_Pos)                    /*!< 0x00002000 */\n#define DMA_SxNDT_14             (0x4000U << DMA_SxNDT_Pos)                    /*!< 0x00004000 */\n#define DMA_SxNDT_15             (0x8000U << DMA_SxNDT_Pos)                    /*!< 0x00008000 */\n\n/********************  Bits definition for DMA_SxFCR register  ****************/\n#define DMA_SxFCR_FEIE_Pos       (7U)\n#define DMA_SxFCR_FEIE_Msk       (0x1U << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */\n#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk\n#define DMA_SxFCR_FS_Pos         (3U)\n#define DMA_SxFCR_FS_Msk         (0x7U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */\n#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk\n#define DMA_SxFCR_FS_0           (0x1U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */\n#define DMA_SxFCR_FS_1           (0x2U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */\n#define DMA_SxFCR_FS_2           (0x4U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */\n#define DMA_SxFCR_DMDIS_Pos      (2U)\n#define DMA_SxFCR_DMDIS_Msk      (0x1U << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */\n#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk\n#define DMA_SxFCR_FTH_Pos        (0U)\n#define DMA_SxFCR_FTH_Msk        (0x3U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */\n#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk\n#define DMA_SxFCR_FTH_0          (0x1U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */\n#define DMA_SxFCR_FTH_1          (0x2U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */\n\n/********************  Bits definition for DMA_LISR register  *****************/\n#define DMA_LISR_TCIF3_Pos       (27U)\n#define DMA_LISR_TCIF3_Msk       (0x1U << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */\n#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk\n#define DMA_LISR_HTIF3_Pos       (26U)\n#define DMA_LISR_HTIF3_Msk       (0x1U << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */\n#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk\n#define DMA_LISR_TEIF3_Pos       (25U)\n#define DMA_LISR_TEIF3_Msk       (0x1U << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */\n#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk\n#define DMA_LISR_DMEIF3_Pos      (24U)\n#define DMA_LISR_DMEIF3_Msk      (0x1U << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */\n#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk\n#define DMA_LISR_FEIF3_Pos       (22U)\n#define DMA_LISR_FEIF3_Msk       (0x1U << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */\n#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk\n#define DMA_LISR_TCIF2_Pos       (21U)\n#define DMA_LISR_TCIF2_Msk       (0x1U << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */\n#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk\n#define DMA_LISR_HTIF2_Pos       (20U)\n#define DMA_LISR_HTIF2_Msk       (0x1U << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */\n#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk\n#define DMA_LISR_TEIF2_Pos       (19U)\n#define DMA_LISR_TEIF2_Msk       (0x1U << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */\n#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk\n#define DMA_LISR_DMEIF2_Pos      (18U)\n#define DMA_LISR_DMEIF2_Msk      (0x1U << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */\n#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk\n#define DMA_LISR_FEIF2_Pos       (16U)\n#define DMA_LISR_FEIF2_Msk       (0x1U << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */\n#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk\n#define DMA_LISR_TCIF1_Pos       (11U)\n#define DMA_LISR_TCIF1_Msk       (0x1U << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */\n#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk\n#define DMA_LISR_HTIF1_Pos       (10U)\n#define DMA_LISR_HTIF1_Msk       (0x1U << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */\n#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk\n#define DMA_LISR_TEIF1_Pos       (9U)\n#define DMA_LISR_TEIF1_Msk       (0x1U << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */\n#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk\n#define DMA_LISR_DMEIF1_Pos      (8U)\n#define DMA_LISR_DMEIF1_Msk      (0x1U << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */\n#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk\n#define DMA_LISR_FEIF1_Pos       (6U)\n#define DMA_LISR_FEIF1_Msk       (0x1U << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */\n#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk\n#define DMA_LISR_TCIF0_Pos       (5U)\n#define DMA_LISR_TCIF0_Msk       (0x1U << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */\n#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk\n#define DMA_LISR_HTIF0_Pos       (4U)\n#define DMA_LISR_HTIF0_Msk       (0x1U << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */\n#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk\n#define DMA_LISR_TEIF0_Pos       (3U)\n#define DMA_LISR_TEIF0_Msk       (0x1U << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */\n#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk\n#define DMA_LISR_DMEIF0_Pos      (2U)\n#define DMA_LISR_DMEIF0_Msk      (0x1U << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */\n#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk\n#define DMA_LISR_FEIF0_Pos       (0U)\n#define DMA_LISR_FEIF0_Msk       (0x1U << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */\n#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk\n\n/********************  Bits definition for DMA_HISR register  *****************/\n#define DMA_HISR_TCIF7_Pos       (27U)\n#define DMA_HISR_TCIF7_Msk       (0x1U << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */\n#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk\n#define DMA_HISR_HTIF7_Pos       (26U)\n#define DMA_HISR_HTIF7_Msk       (0x1U << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */\n#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk\n#define DMA_HISR_TEIF7_Pos       (25U)\n#define DMA_HISR_TEIF7_Msk       (0x1U << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */\n#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk\n#define DMA_HISR_DMEIF7_Pos      (24U)\n#define DMA_HISR_DMEIF7_Msk      (0x1U << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */\n#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk\n#define DMA_HISR_FEIF7_Pos       (22U)\n#define DMA_HISR_FEIF7_Msk       (0x1U << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */\n#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk\n#define DMA_HISR_TCIF6_Pos       (21U)\n#define DMA_HISR_TCIF6_Msk       (0x1U << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */\n#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk\n#define DMA_HISR_HTIF6_Pos       (20U)\n#define DMA_HISR_HTIF6_Msk       (0x1U << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */\n#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk\n#define DMA_HISR_TEIF6_Pos       (19U)\n#define DMA_HISR_TEIF6_Msk       (0x1U << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */\n#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk\n#define DMA_HISR_DMEIF6_Pos      (18U)\n#define DMA_HISR_DMEIF6_Msk      (0x1U << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */\n#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk\n#define DMA_HISR_FEIF6_Pos       (16U)\n#define DMA_HISR_FEIF6_Msk       (0x1U << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */\n#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk\n#define DMA_HISR_TCIF5_Pos       (11U)\n#define DMA_HISR_TCIF5_Msk       (0x1U << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */\n#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk\n#define DMA_HISR_HTIF5_Pos       (10U)\n#define DMA_HISR_HTIF5_Msk       (0x1U << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */\n#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk\n#define DMA_HISR_TEIF5_Pos       (9U)\n#define DMA_HISR_TEIF5_Msk       (0x1U << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */\n#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk\n#define DMA_HISR_DMEIF5_Pos      (8U)\n#define DMA_HISR_DMEIF5_Msk      (0x1U << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */\n#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk\n#define DMA_HISR_FEIF5_Pos       (6U)\n#define DMA_HISR_FEIF5_Msk       (0x1U << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */\n#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk\n#define DMA_HISR_TCIF4_Pos       (5U)\n#define DMA_HISR_TCIF4_Msk       (0x1U << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */\n#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk\n#define DMA_HISR_HTIF4_Pos       (4U)\n#define DMA_HISR_HTIF4_Msk       (0x1U << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */\n#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk\n#define DMA_HISR_TEIF4_Pos       (3U)\n#define DMA_HISR_TEIF4_Msk       (0x1U << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */\n#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk\n#define DMA_HISR_DMEIF4_Pos      (2U)\n#define DMA_HISR_DMEIF4_Msk      (0x1U << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */\n#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk\n#define DMA_HISR_FEIF4_Pos       (0U)\n#define DMA_HISR_FEIF4_Msk       (0x1U << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */\n#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk\n\n/********************  Bits definition for DMA_LIFCR register  ****************/\n#define DMA_LIFCR_CTCIF3_Pos     (27U)\n#define DMA_LIFCR_CTCIF3_Msk     (0x1U << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */\n#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk\n#define DMA_LIFCR_CHTIF3_Pos     (26U)\n#define DMA_LIFCR_CHTIF3_Msk     (0x1U << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */\n#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk\n#define DMA_LIFCR_CTEIF3_Pos     (25U)\n#define DMA_LIFCR_CTEIF3_Msk     (0x1U << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */\n#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk\n#define DMA_LIFCR_CDMEIF3_Pos    (24U)\n#define DMA_LIFCR_CDMEIF3_Msk    (0x1U << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */\n#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk\n#define DMA_LIFCR_CFEIF3_Pos     (22U)\n#define DMA_LIFCR_CFEIF3_Msk     (0x1U << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */\n#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk\n#define DMA_LIFCR_CTCIF2_Pos     (21U)\n#define DMA_LIFCR_CTCIF2_Msk     (0x1U << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */\n#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk\n#define DMA_LIFCR_CHTIF2_Pos     (20U)\n#define DMA_LIFCR_CHTIF2_Msk     (0x1U << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */\n#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk\n#define DMA_LIFCR_CTEIF2_Pos     (19U)\n#define DMA_LIFCR_CTEIF2_Msk     (0x1U << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */\n#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk\n#define DMA_LIFCR_CDMEIF2_Pos    (18U)\n#define DMA_LIFCR_CDMEIF2_Msk    (0x1U << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */\n#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk\n#define DMA_LIFCR_CFEIF2_Pos     (16U)\n#define DMA_LIFCR_CFEIF2_Msk     (0x1U << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */\n#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk\n#define DMA_LIFCR_CTCIF1_Pos     (11U)\n#define DMA_LIFCR_CTCIF1_Msk     (0x1U << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */\n#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk\n#define DMA_LIFCR_CHTIF1_Pos     (10U)\n#define DMA_LIFCR_CHTIF1_Msk     (0x1U << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */\n#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk\n#define DMA_LIFCR_CTEIF1_Pos     (9U)\n#define DMA_LIFCR_CTEIF1_Msk     (0x1U << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */\n#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk\n#define DMA_LIFCR_CDMEIF1_Pos    (8U)\n#define DMA_LIFCR_CDMEIF1_Msk    (0x1U << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */\n#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk\n#define DMA_LIFCR_CFEIF1_Pos     (6U)\n#define DMA_LIFCR_CFEIF1_Msk     (0x1U << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */\n#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk\n#define DMA_LIFCR_CTCIF0_Pos     (5U)\n#define DMA_LIFCR_CTCIF0_Msk     (0x1U << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */\n#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk\n#define DMA_LIFCR_CHTIF0_Pos     (4U)\n#define DMA_LIFCR_CHTIF0_Msk     (0x1U << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */\n#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk\n#define DMA_LIFCR_CTEIF0_Pos     (3U)\n#define DMA_LIFCR_CTEIF0_Msk     (0x1U << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */\n#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk\n#define DMA_LIFCR_CDMEIF0_Pos    (2U)\n#define DMA_LIFCR_CDMEIF0_Msk    (0x1U << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */\n#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk\n#define DMA_LIFCR_CFEIF0_Pos     (0U)\n#define DMA_LIFCR_CFEIF0_Msk     (0x1U << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */\n#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk\n\n/********************  Bits definition for DMA_HIFCR  register  ****************/\n#define DMA_HIFCR_CTCIF7_Pos     (27U)\n#define DMA_HIFCR_CTCIF7_Msk     (0x1U << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */\n#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk\n#define DMA_HIFCR_CHTIF7_Pos     (26U)\n#define DMA_HIFCR_CHTIF7_Msk     (0x1U << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */\n#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk\n#define DMA_HIFCR_CTEIF7_Pos     (25U)\n#define DMA_HIFCR_CTEIF7_Msk     (0x1U << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */\n#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk\n#define DMA_HIFCR_CDMEIF7_Pos    (24U)\n#define DMA_HIFCR_CDMEIF7_Msk    (0x1U << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */\n#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk\n#define DMA_HIFCR_CFEIF7_Pos     (22U)\n#define DMA_HIFCR_CFEIF7_Msk     (0x1U << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */\n#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk\n#define DMA_HIFCR_CTCIF6_Pos     (21U)\n#define DMA_HIFCR_CTCIF6_Msk     (0x1U << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */\n#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk\n#define DMA_HIFCR_CHTIF6_Pos     (20U)\n#define DMA_HIFCR_CHTIF6_Msk     (0x1U << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */\n#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk\n#define DMA_HIFCR_CTEIF6_Pos     (19U)\n#define DMA_HIFCR_CTEIF6_Msk     (0x1U << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */\n#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk\n#define DMA_HIFCR_CDMEIF6_Pos    (18U)\n#define DMA_HIFCR_CDMEIF6_Msk    (0x1U << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */\n#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk\n#define DMA_HIFCR_CFEIF6_Pos     (16U)\n#define DMA_HIFCR_CFEIF6_Msk     (0x1U << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */\n#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk\n#define DMA_HIFCR_CTCIF5_Pos     (11U)\n#define DMA_HIFCR_CTCIF5_Msk     (0x1U << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */\n#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk\n#define DMA_HIFCR_CHTIF5_Pos     (10U)\n#define DMA_HIFCR_CHTIF5_Msk     (0x1U << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */\n#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk\n#define DMA_HIFCR_CTEIF5_Pos     (9U)\n#define DMA_HIFCR_CTEIF5_Msk     (0x1U << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */\n#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk\n#define DMA_HIFCR_CDMEIF5_Pos    (8U)\n#define DMA_HIFCR_CDMEIF5_Msk    (0x1U << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */\n#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk\n#define DMA_HIFCR_CFEIF5_Pos     (6U)\n#define DMA_HIFCR_CFEIF5_Msk     (0x1U << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */\n#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk\n#define DMA_HIFCR_CTCIF4_Pos     (5U)\n#define DMA_HIFCR_CTCIF4_Msk     (0x1U << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */\n#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk\n#define DMA_HIFCR_CHTIF4_Pos     (4U)\n#define DMA_HIFCR_CHTIF4_Msk     (0x1U << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */\n#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk\n#define DMA_HIFCR_CTEIF4_Pos     (3U)\n#define DMA_HIFCR_CTEIF4_Msk     (0x1U << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */\n#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk\n#define DMA_HIFCR_CDMEIF4_Pos    (2U)\n#define DMA_HIFCR_CDMEIF4_Msk    (0x1U << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */\n#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk\n#define DMA_HIFCR_CFEIF4_Pos     (0U)\n#define DMA_HIFCR_CFEIF4_Msk     (0x1U << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */\n#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk\n\n/******************  Bit definition for DMA_SxPAR register  ********************/\n#define DMA_SxPAR_PA_Pos         (0U)\n#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFU << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */\n#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */\n\n/******************  Bit definition for DMA_SxM0AR register  ********************/\n#define DMA_SxM0AR_M0A_Pos       (0U)\n#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */\n\n/******************  Bit definition for DMA_SxM1AR register  ********************/\n#define DMA_SxM1AR_M1A_Pos       (0U)\n#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                    External Interrupt/Event Controller                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for EXTI_IMR register  *******************/\n#define EXTI_IMR_MR0_Pos          (0U)\n#define EXTI_IMR_MR0_Msk          (0x1U << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */\n#define EXTI_IMR_MR1_Pos          (1U)\n#define EXTI_IMR_MR1_Msk          (0x1U << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */\n#define EXTI_IMR_MR2_Pos          (2U)\n#define EXTI_IMR_MR2_Msk          (0x1U << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */\n#define EXTI_IMR_MR3_Pos          (3U)\n#define EXTI_IMR_MR3_Msk          (0x1U << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */\n#define EXTI_IMR_MR4_Pos          (4U)\n#define EXTI_IMR_MR4_Msk          (0x1U << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */\n#define EXTI_IMR_MR5_Pos          (5U)\n#define EXTI_IMR_MR5_Msk          (0x1U << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */\n#define EXTI_IMR_MR6_Pos          (6U)\n#define EXTI_IMR_MR6_Msk          (0x1U << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */\n#define EXTI_IMR_MR7_Pos          (7U)\n#define EXTI_IMR_MR7_Msk          (0x1U << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */\n#define EXTI_IMR_MR8_Pos          (8U)\n#define EXTI_IMR_MR8_Msk          (0x1U << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */\n#define EXTI_IMR_MR9_Pos          (9U)\n#define EXTI_IMR_MR9_Msk          (0x1U << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */\n#define EXTI_IMR_MR10_Pos         (10U)\n#define EXTI_IMR_MR10_Msk         (0x1U << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */\n#define EXTI_IMR_MR11_Pos         (11U)\n#define EXTI_IMR_MR11_Msk         (0x1U << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */\n#define EXTI_IMR_MR12_Pos         (12U)\n#define EXTI_IMR_MR12_Msk         (0x1U << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */\n#define EXTI_IMR_MR13_Pos         (13U)\n#define EXTI_IMR_MR13_Msk         (0x1U << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */\n#define EXTI_IMR_MR14_Pos         (14U)\n#define EXTI_IMR_MR14_Msk         (0x1U << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */\n#define EXTI_IMR_MR15_Pos         (15U)\n#define EXTI_IMR_MR15_Msk         (0x1U << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */\n#define EXTI_IMR_MR16_Pos         (16U)\n#define EXTI_IMR_MR16_Msk         (0x1U << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */\n#define EXTI_IMR_MR17_Pos         (17U)\n#define EXTI_IMR_MR17_Msk         (0x1U << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */\n#define EXTI_IMR_MR18_Pos         (18U)\n#define EXTI_IMR_MR18_Msk         (0x1U << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */\n#define EXTI_IMR_MR19_Pos         (19U)\n#define EXTI_IMR_MR19_Msk         (0x1U << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */\n#define EXTI_IMR_MR20_Pos         (20U)\n#define EXTI_IMR_MR20_Msk         (0x1U << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */\n#define EXTI_IMR_MR21_Pos         (21U)\n#define EXTI_IMR_MR21_Msk         (0x1U << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */\n#define EXTI_IMR_MR22_Pos         (22U)\n#define EXTI_IMR_MR22_Msk         (0x1U << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */\n\n/* Reference Defines */\n#define  EXTI_IMR_IM0                        EXTI_IMR_MR0\n#define  EXTI_IMR_IM1                        EXTI_IMR_MR1\n#define  EXTI_IMR_IM2                        EXTI_IMR_MR2\n#define  EXTI_IMR_IM3                        EXTI_IMR_MR3\n#define  EXTI_IMR_IM4                        EXTI_IMR_MR4\n#define  EXTI_IMR_IM5                        EXTI_IMR_MR5\n#define  EXTI_IMR_IM6                        EXTI_IMR_MR6\n#define  EXTI_IMR_IM7                        EXTI_IMR_MR7\n#define  EXTI_IMR_IM8                        EXTI_IMR_MR8\n#define  EXTI_IMR_IM9                        EXTI_IMR_MR9\n#define  EXTI_IMR_IM10                       EXTI_IMR_MR10\n#define  EXTI_IMR_IM11                       EXTI_IMR_MR11\n#define  EXTI_IMR_IM12                       EXTI_IMR_MR12\n#define  EXTI_IMR_IM13                       EXTI_IMR_MR13\n#define  EXTI_IMR_IM14                       EXTI_IMR_MR14\n#define  EXTI_IMR_IM15                       EXTI_IMR_MR15\n#define  EXTI_IMR_IM16                       EXTI_IMR_MR16\n#define  EXTI_IMR_IM17                       EXTI_IMR_MR17\n#define  EXTI_IMR_IM18                       EXTI_IMR_MR18\n#define  EXTI_IMR_IM19                       EXTI_IMR_MR19\n#define  EXTI_IMR_IM20                       EXTI_IMR_MR20\n#define  EXTI_IMR_IM21                       EXTI_IMR_MR21\n#define  EXTI_IMR_IM22                       EXTI_IMR_MR22\n#define EXTI_IMR_IM_Pos           (0U)\n#define EXTI_IMR_IM_Msk           (0x7FFFFFU << EXTI_IMR_IM_Pos)               /*!< 0x007FFFFF */\n#define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */\n\n/*******************  Bit definition for EXTI_EMR register  *******************/\n#define EXTI_EMR_MR0_Pos          (0U)\n#define EXTI_EMR_MR0_Msk          (0x1U << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */\n#define EXTI_EMR_MR1_Pos          (1U)\n#define EXTI_EMR_MR1_Msk          (0x1U << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */\n#define EXTI_EMR_MR2_Pos          (2U)\n#define EXTI_EMR_MR2_Msk          (0x1U << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */\n#define EXTI_EMR_MR3_Pos          (3U)\n#define EXTI_EMR_MR3_Msk          (0x1U << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */\n#define EXTI_EMR_MR4_Pos          (4U)\n#define EXTI_EMR_MR4_Msk          (0x1U << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */\n#define EXTI_EMR_MR5_Pos          (5U)\n#define EXTI_EMR_MR5_Msk          (0x1U << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */\n#define EXTI_EMR_MR6_Pos          (6U)\n#define EXTI_EMR_MR6_Msk          (0x1U << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */\n#define EXTI_EMR_MR7_Pos          (7U)\n#define EXTI_EMR_MR7_Msk          (0x1U << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */\n#define EXTI_EMR_MR8_Pos          (8U)\n#define EXTI_EMR_MR8_Msk          (0x1U << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */\n#define EXTI_EMR_MR9_Pos          (9U)\n#define EXTI_EMR_MR9_Msk          (0x1U << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */\n#define EXTI_EMR_MR10_Pos         (10U)\n#define EXTI_EMR_MR10_Msk         (0x1U << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */\n#define EXTI_EMR_MR11_Pos         (11U)\n#define EXTI_EMR_MR11_Msk         (0x1U << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */\n#define EXTI_EMR_MR12_Pos         (12U)\n#define EXTI_EMR_MR12_Msk         (0x1U << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */\n#define EXTI_EMR_MR13_Pos         (13U)\n#define EXTI_EMR_MR13_Msk         (0x1U << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */\n#define EXTI_EMR_MR14_Pos         (14U)\n#define EXTI_EMR_MR14_Msk         (0x1U << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */\n#define EXTI_EMR_MR15_Pos         (15U)\n#define EXTI_EMR_MR15_Msk         (0x1U << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */\n#define EXTI_EMR_MR16_Pos         (16U)\n#define EXTI_EMR_MR16_Msk         (0x1U << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */\n#define EXTI_EMR_MR17_Pos         (17U)\n#define EXTI_EMR_MR17_Msk         (0x1U << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */\n#define EXTI_EMR_MR18_Pos         (18U)\n#define EXTI_EMR_MR18_Msk         (0x1U << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */\n#define EXTI_EMR_MR19_Pos         (19U)\n#define EXTI_EMR_MR19_Msk         (0x1U << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */\n#define EXTI_EMR_MR20_Pos         (20U)\n#define EXTI_EMR_MR20_Msk         (0x1U << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */\n#define EXTI_EMR_MR21_Pos         (21U)\n#define EXTI_EMR_MR21_Msk         (0x1U << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */\n#define EXTI_EMR_MR22_Pos         (22U)\n#define EXTI_EMR_MR22_Msk         (0x1U << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */\n\n/* Reference Defines */\n#define  EXTI_EMR_EM0                        EXTI_EMR_MR0\n#define  EXTI_EMR_EM1                        EXTI_EMR_MR1\n#define  EXTI_EMR_EM2                        EXTI_EMR_MR2\n#define  EXTI_EMR_EM3                        EXTI_EMR_MR3\n#define  EXTI_EMR_EM4                        EXTI_EMR_MR4\n#define  EXTI_EMR_EM5                        EXTI_EMR_MR5\n#define  EXTI_EMR_EM6                        EXTI_EMR_MR6\n#define  EXTI_EMR_EM7                        EXTI_EMR_MR7\n#define  EXTI_EMR_EM8                        EXTI_EMR_MR8\n#define  EXTI_EMR_EM9                        EXTI_EMR_MR9\n#define  EXTI_EMR_EM10                       EXTI_EMR_MR10\n#define  EXTI_EMR_EM11                       EXTI_EMR_MR11\n#define  EXTI_EMR_EM12                       EXTI_EMR_MR12\n#define  EXTI_EMR_EM13                       EXTI_EMR_MR13\n#define  EXTI_EMR_EM14                       EXTI_EMR_MR14\n#define  EXTI_EMR_EM15                       EXTI_EMR_MR15\n#define  EXTI_EMR_EM16                       EXTI_EMR_MR16\n#define  EXTI_EMR_EM17                       EXTI_EMR_MR17\n#define  EXTI_EMR_EM18                       EXTI_EMR_MR18\n#define  EXTI_EMR_EM19                       EXTI_EMR_MR19\n#define  EXTI_EMR_EM20                       EXTI_EMR_MR20\n#define  EXTI_EMR_EM21                       EXTI_EMR_MR21\n#define  EXTI_EMR_EM22                       EXTI_EMR_MR22\n\n/******************  Bit definition for EXTI_RTSR register  *******************/\n#define EXTI_RTSR_TR0_Pos         (0U)\n#define EXTI_RTSR_TR0_Msk         (0x1U << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */\n#define EXTI_RTSR_TR1_Pos         (1U)\n#define EXTI_RTSR_TR1_Msk         (0x1U << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */\n#define EXTI_RTSR_TR2_Pos         (2U)\n#define EXTI_RTSR_TR2_Msk         (0x1U << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */\n#define EXTI_RTSR_TR3_Pos         (3U)\n#define EXTI_RTSR_TR3_Msk         (0x1U << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */\n#define EXTI_RTSR_TR4_Pos         (4U)\n#define EXTI_RTSR_TR4_Msk         (0x1U << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */\n#define EXTI_RTSR_TR5_Pos         (5U)\n#define EXTI_RTSR_TR5_Msk         (0x1U << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */\n#define EXTI_RTSR_TR6_Pos         (6U)\n#define EXTI_RTSR_TR6_Msk         (0x1U << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */\n#define EXTI_RTSR_TR7_Pos         (7U)\n#define EXTI_RTSR_TR7_Msk         (0x1U << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */\n#define EXTI_RTSR_TR8_Pos         (8U)\n#define EXTI_RTSR_TR8_Msk         (0x1U << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */\n#define EXTI_RTSR_TR9_Pos         (9U)\n#define EXTI_RTSR_TR9_Msk         (0x1U << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */\n#define EXTI_RTSR_TR10_Pos        (10U)\n#define EXTI_RTSR_TR10_Msk        (0x1U << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */\n#define EXTI_RTSR_TR11_Pos        (11U)\n#define EXTI_RTSR_TR11_Msk        (0x1U << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */\n#define EXTI_RTSR_TR12_Pos        (12U)\n#define EXTI_RTSR_TR12_Msk        (0x1U << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */\n#define EXTI_RTSR_TR13_Pos        (13U)\n#define EXTI_RTSR_TR13_Msk        (0x1U << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */\n#define EXTI_RTSR_TR14_Pos        (14U)\n#define EXTI_RTSR_TR14_Msk        (0x1U << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */\n#define EXTI_RTSR_TR15_Pos        (15U)\n#define EXTI_RTSR_TR15_Msk        (0x1U << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */\n#define EXTI_RTSR_TR16_Pos        (16U)\n#define EXTI_RTSR_TR16_Msk        (0x1U << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */\n#define EXTI_RTSR_TR17_Pos        (17U)\n#define EXTI_RTSR_TR17_Msk        (0x1U << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */\n#define EXTI_RTSR_TR18_Pos        (18U)\n#define EXTI_RTSR_TR18_Msk        (0x1U << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */\n#define EXTI_RTSR_TR19_Pos        (19U)\n#define EXTI_RTSR_TR19_Msk        (0x1U << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */\n#define EXTI_RTSR_TR20_Pos        (20U)\n#define EXTI_RTSR_TR20_Msk        (0x1U << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */\n#define EXTI_RTSR_TR21_Pos        (21U)\n#define EXTI_RTSR_TR21_Msk        (0x1U << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */\n#define EXTI_RTSR_TR22_Pos        (22U)\n#define EXTI_RTSR_TR22_Msk        (0x1U << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_FTSR register  *******************/\n#define EXTI_FTSR_TR0_Pos         (0U)\n#define EXTI_FTSR_TR0_Msk         (0x1U << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */\n#define EXTI_FTSR_TR1_Pos         (1U)\n#define EXTI_FTSR_TR1_Msk         (0x1U << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */\n#define EXTI_FTSR_TR2_Pos         (2U)\n#define EXTI_FTSR_TR2_Msk         (0x1U << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */\n#define EXTI_FTSR_TR3_Pos         (3U)\n#define EXTI_FTSR_TR3_Msk         (0x1U << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */\n#define EXTI_FTSR_TR4_Pos         (4U)\n#define EXTI_FTSR_TR4_Msk         (0x1U << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */\n#define EXTI_FTSR_TR5_Pos         (5U)\n#define EXTI_FTSR_TR5_Msk         (0x1U << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */\n#define EXTI_FTSR_TR6_Pos         (6U)\n#define EXTI_FTSR_TR6_Msk         (0x1U << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */\n#define EXTI_FTSR_TR7_Pos         (7U)\n#define EXTI_FTSR_TR7_Msk         (0x1U << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */\n#define EXTI_FTSR_TR8_Pos         (8U)\n#define EXTI_FTSR_TR8_Msk         (0x1U << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */\n#define EXTI_FTSR_TR9_Pos         (9U)\n#define EXTI_FTSR_TR9_Msk         (0x1U << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */\n#define EXTI_FTSR_TR10_Pos        (10U)\n#define EXTI_FTSR_TR10_Msk        (0x1U << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */\n#define EXTI_FTSR_TR11_Pos        (11U)\n#define EXTI_FTSR_TR11_Msk        (0x1U << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */\n#define EXTI_FTSR_TR12_Pos        (12U)\n#define EXTI_FTSR_TR12_Msk        (0x1U << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */\n#define EXTI_FTSR_TR13_Pos        (13U)\n#define EXTI_FTSR_TR13_Msk        (0x1U << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */\n#define EXTI_FTSR_TR14_Pos        (14U)\n#define EXTI_FTSR_TR14_Msk        (0x1U << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */\n#define EXTI_FTSR_TR15_Pos        (15U)\n#define EXTI_FTSR_TR15_Msk        (0x1U << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */\n#define EXTI_FTSR_TR16_Pos        (16U)\n#define EXTI_FTSR_TR16_Msk        (0x1U << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */\n#define EXTI_FTSR_TR17_Pos        (17U)\n#define EXTI_FTSR_TR17_Msk        (0x1U << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */\n#define EXTI_FTSR_TR18_Pos        (18U)\n#define EXTI_FTSR_TR18_Msk        (0x1U << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */\n#define EXTI_FTSR_TR19_Pos        (19U)\n#define EXTI_FTSR_TR19_Msk        (0x1U << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */\n#define EXTI_FTSR_TR20_Pos        (20U)\n#define EXTI_FTSR_TR20_Msk        (0x1U << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */\n#define EXTI_FTSR_TR21_Pos        (21U)\n#define EXTI_FTSR_TR21_Msk        (0x1U << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */\n#define EXTI_FTSR_TR22_Pos        (22U)\n#define EXTI_FTSR_TR22_Msk        (0x1U << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_SWIER register  ******************/\n#define EXTI_SWIER_SWIER0_Pos     (0U)\n#define EXTI_SWIER_SWIER0_Msk     (0x1U << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */\n#define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */\n#define EXTI_SWIER_SWIER1_Pos     (1U)\n#define EXTI_SWIER_SWIER1_Msk     (0x1U << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */\n#define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */\n#define EXTI_SWIER_SWIER2_Pos     (2U)\n#define EXTI_SWIER_SWIER2_Msk     (0x1U << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */\n#define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */\n#define EXTI_SWIER_SWIER3_Pos     (3U)\n#define EXTI_SWIER_SWIER3_Msk     (0x1U << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */\n#define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */\n#define EXTI_SWIER_SWIER4_Pos     (4U)\n#define EXTI_SWIER_SWIER4_Msk     (0x1U << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */\n#define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */\n#define EXTI_SWIER_SWIER5_Pos     (5U)\n#define EXTI_SWIER_SWIER5_Msk     (0x1U << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */\n#define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */\n#define EXTI_SWIER_SWIER6_Pos     (6U)\n#define EXTI_SWIER_SWIER6_Msk     (0x1U << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */\n#define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */\n#define EXTI_SWIER_SWIER7_Pos     (7U)\n#define EXTI_SWIER_SWIER7_Msk     (0x1U << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */\n#define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */\n#define EXTI_SWIER_SWIER8_Pos     (8U)\n#define EXTI_SWIER_SWIER8_Msk     (0x1U << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */\n#define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */\n#define EXTI_SWIER_SWIER9_Pos     (9U)\n#define EXTI_SWIER_SWIER9_Msk     (0x1U << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */\n#define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */\n#define EXTI_SWIER_SWIER10_Pos    (10U)\n#define EXTI_SWIER_SWIER10_Msk    (0x1U << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */\n#define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */\n#define EXTI_SWIER_SWIER11_Pos    (11U)\n#define EXTI_SWIER_SWIER11_Msk    (0x1U << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */\n#define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */\n#define EXTI_SWIER_SWIER12_Pos    (12U)\n#define EXTI_SWIER_SWIER12_Msk    (0x1U << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */\n#define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */\n#define EXTI_SWIER_SWIER13_Pos    (13U)\n#define EXTI_SWIER_SWIER13_Msk    (0x1U << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */\n#define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */\n#define EXTI_SWIER_SWIER14_Pos    (14U)\n#define EXTI_SWIER_SWIER14_Msk    (0x1U << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */\n#define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */\n#define EXTI_SWIER_SWIER15_Pos    (15U)\n#define EXTI_SWIER_SWIER15_Msk    (0x1U << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */\n#define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */\n#define EXTI_SWIER_SWIER16_Pos    (16U)\n#define EXTI_SWIER_SWIER16_Msk    (0x1U << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */\n#define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */\n#define EXTI_SWIER_SWIER17_Pos    (17U)\n#define EXTI_SWIER_SWIER17_Msk    (0x1U << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */\n#define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */\n#define EXTI_SWIER_SWIER18_Pos    (18U)\n#define EXTI_SWIER_SWIER18_Msk    (0x1U << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */\n#define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */\n#define EXTI_SWIER_SWIER19_Pos    (19U)\n#define EXTI_SWIER_SWIER19_Msk    (0x1U << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */\n#define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */\n#define EXTI_SWIER_SWIER20_Pos    (20U)\n#define EXTI_SWIER_SWIER20_Msk    (0x1U << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */\n#define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */\n#define EXTI_SWIER_SWIER21_Pos    (21U)\n#define EXTI_SWIER_SWIER21_Msk    (0x1U << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */\n#define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */\n#define EXTI_SWIER_SWIER22_Pos    (22U)\n#define EXTI_SWIER_SWIER22_Msk    (0x1U << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */\n#define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */\n\n/*******************  Bit definition for EXTI_PR register  ********************/\n#define EXTI_PR_PR0_Pos           (0U)\n#define EXTI_PR_PR0_Msk           (0x1U << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */\n#define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */\n#define EXTI_PR_PR1_Pos           (1U)\n#define EXTI_PR_PR1_Msk           (0x1U << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */\n#define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */\n#define EXTI_PR_PR2_Pos           (2U)\n#define EXTI_PR_PR2_Msk           (0x1U << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */\n#define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */\n#define EXTI_PR_PR3_Pos           (3U)\n#define EXTI_PR_PR3_Msk           (0x1U << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */\n#define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */\n#define EXTI_PR_PR4_Pos           (4U)\n#define EXTI_PR_PR4_Msk           (0x1U << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */\n#define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */\n#define EXTI_PR_PR5_Pos           (5U)\n#define EXTI_PR_PR5_Msk           (0x1U << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */\n#define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */\n#define EXTI_PR_PR6_Pos           (6U)\n#define EXTI_PR_PR6_Msk           (0x1U << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */\n#define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */\n#define EXTI_PR_PR7_Pos           (7U)\n#define EXTI_PR_PR7_Msk           (0x1U << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */\n#define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */\n#define EXTI_PR_PR8_Pos           (8U)\n#define EXTI_PR_PR8_Msk           (0x1U << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */\n#define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */\n#define EXTI_PR_PR9_Pos           (9U)\n#define EXTI_PR_PR9_Msk           (0x1U << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */\n#define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */\n#define EXTI_PR_PR10_Pos          (10U)\n#define EXTI_PR_PR10_Msk          (0x1U << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */\n#define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */\n#define EXTI_PR_PR11_Pos          (11U)\n#define EXTI_PR_PR11_Msk          (0x1U << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */\n#define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */\n#define EXTI_PR_PR12_Pos          (12U)\n#define EXTI_PR_PR12_Msk          (0x1U << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */\n#define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */\n#define EXTI_PR_PR13_Pos          (13U)\n#define EXTI_PR_PR13_Msk          (0x1U << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */\n#define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */\n#define EXTI_PR_PR14_Pos          (14U)\n#define EXTI_PR_PR14_Msk          (0x1U << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */\n#define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */\n#define EXTI_PR_PR15_Pos          (15U)\n#define EXTI_PR_PR15_Msk          (0x1U << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */\n#define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */\n#define EXTI_PR_PR16_Pos          (16U)\n#define EXTI_PR_PR16_Msk          (0x1U << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */\n#define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */\n#define EXTI_PR_PR17_Pos          (17U)\n#define EXTI_PR_PR17_Msk          (0x1U << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */\n#define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */\n#define EXTI_PR_PR18_Pos          (18U)\n#define EXTI_PR_PR18_Msk          (0x1U << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */\n#define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */\n#define EXTI_PR_PR19_Pos          (19U)\n#define EXTI_PR_PR19_Msk          (0x1U << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */\n#define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */\n#define EXTI_PR_PR20_Pos          (20U)\n#define EXTI_PR_PR20_Msk          (0x1U << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */\n#define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */\n#define EXTI_PR_PR21_Pos          (21U)\n#define EXTI_PR_PR21_Msk          (0x1U << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */\n#define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */\n#define EXTI_PR_PR22_Pos          (22U)\n#define EXTI_PR_PR22_Msk          (0x1U << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */\n#define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    FLASH                                   */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bits definition for FLASH_ACR register  *****************/\n#define FLASH_ACR_LATENCY_Pos          (0U)\n#define FLASH_ACR_LATENCY_Msk          (0xFU << FLASH_ACR_LATENCY_Pos)         /*!< 0x0000000F */\n#define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk\n#define FLASH_ACR_LATENCY_0WS          0x00000000U\n#define FLASH_ACR_LATENCY_1WS          0x00000001U\n#define FLASH_ACR_LATENCY_2WS          0x00000002U\n#define FLASH_ACR_LATENCY_3WS          0x00000003U\n#define FLASH_ACR_LATENCY_4WS          0x00000004U\n#define FLASH_ACR_LATENCY_5WS          0x00000005U\n#define FLASH_ACR_LATENCY_6WS          0x00000006U\n#define FLASH_ACR_LATENCY_7WS          0x00000007U\n\n#define FLASH_ACR_PRFTEN_Pos           (8U)\n#define FLASH_ACR_PRFTEN_Msk           (0x1U << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */\n#define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk\n#define FLASH_ACR_ICEN_Pos             (9U)\n#define FLASH_ACR_ICEN_Msk             (0x1U << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */\n#define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk\n#define FLASH_ACR_DCEN_Pos             (10U)\n#define FLASH_ACR_DCEN_Msk             (0x1U << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */\n#define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk\n#define FLASH_ACR_ICRST_Pos            (11U)\n#define FLASH_ACR_ICRST_Msk            (0x1U << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */\n#define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk\n#define FLASH_ACR_DCRST_Pos            (12U)\n#define FLASH_ACR_DCRST_Msk            (0x1U << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */\n#define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk\n#define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)\n#define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */\n#define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk\n#define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)\n#define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */\n#define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk\n\n/*******************  Bits definition for FLASH_SR register  ******************/\n#define FLASH_SR_EOP_Pos               (0U)\n#define FLASH_SR_EOP_Msk               (0x1U << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */\n#define FLASH_SR_EOP                   FLASH_SR_EOP_Msk\n#define FLASH_SR_SOP_Pos               (1U)\n#define FLASH_SR_SOP_Msk               (0x1U << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */\n#define FLASH_SR_SOP                   FLASH_SR_SOP_Msk\n#define FLASH_SR_WRPERR_Pos            (4U)\n#define FLASH_SR_WRPERR_Msk            (0x1U << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */\n#define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk\n#define FLASH_SR_PGAERR_Pos            (5U)\n#define FLASH_SR_PGAERR_Msk            (0x1U << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */\n#define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk\n#define FLASH_SR_PGPERR_Pos            (6U)\n#define FLASH_SR_PGPERR_Msk            (0x1U << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */\n#define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk\n#define FLASH_SR_PGSERR_Pos            (7U)\n#define FLASH_SR_PGSERR_Msk            (0x1U << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */\n#define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk\n#define FLASH_SR_BSY_Pos               (16U)\n#define FLASH_SR_BSY_Msk               (0x1U << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */\n#define FLASH_SR_BSY                   FLASH_SR_BSY_Msk\n\n/*******************  Bits definition for FLASH_CR register  ******************/\n#define FLASH_CR_PG_Pos                (0U)\n#define FLASH_CR_PG_Msk                (0x1U << FLASH_CR_PG_Pos)               /*!< 0x00000001 */\n#define FLASH_CR_PG                    FLASH_CR_PG_Msk\n#define FLASH_CR_SER_Pos               (1U)\n#define FLASH_CR_SER_Msk               (0x1U << FLASH_CR_SER_Pos)              /*!< 0x00000002 */\n#define FLASH_CR_SER                   FLASH_CR_SER_Msk\n#define FLASH_CR_MER_Pos               (2U)\n#define FLASH_CR_MER_Msk               (0x1U << FLASH_CR_MER_Pos)              /*!< 0x00000004 */\n#define FLASH_CR_MER                   FLASH_CR_MER_Msk\n#define FLASH_CR_SNB_Pos               (3U)\n#define FLASH_CR_SNB_Msk               (0x1FU << FLASH_CR_SNB_Pos)             /*!< 0x000000F8 */\n#define FLASH_CR_SNB                   FLASH_CR_SNB_Msk\n#define FLASH_CR_SNB_0                 (0x01U << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */\n#define FLASH_CR_SNB_1                 (0x02U << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */\n#define FLASH_CR_SNB_2                 (0x04U << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */\n#define FLASH_CR_SNB_3                 (0x08U << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */\n#define FLASH_CR_SNB_4                 (0x10U << FLASH_CR_SNB_Pos)             /*!< 0x00000080 */\n#define FLASH_CR_PSIZE_Pos             (8U)\n#define FLASH_CR_PSIZE_Msk             (0x3U << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */\n#define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk\n#define FLASH_CR_PSIZE_0               (0x1U << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */\n#define FLASH_CR_PSIZE_1               (0x2U << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */\n#define FLASH_CR_STRT_Pos              (16U)\n#define FLASH_CR_STRT_Msk              (0x1U << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */\n#define FLASH_CR_STRT                  FLASH_CR_STRT_Msk\n#define FLASH_CR_EOPIE_Pos             (24U)\n#define FLASH_CR_EOPIE_Msk             (0x1U << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */\n#define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk\n#define FLASH_CR_LOCK_Pos              (31U)\n#define FLASH_CR_LOCK_Msk              (0x1U << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */\n#define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk\n\n/*******************  Bits definition for FLASH_OPTCR register  ***************/\n#define FLASH_OPTCR_OPTLOCK_Pos        (0U)\n#define FLASH_OPTCR_OPTLOCK_Msk        (0x1U << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */\n#define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk\n#define FLASH_OPTCR_OPTSTRT_Pos        (1U)\n#define FLASH_OPTCR_OPTSTRT_Msk        (0x1U << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */\n#define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk\n\n#define FLASH_OPTCR_BOR_LEV_0          0x00000004U\n#define FLASH_OPTCR_BOR_LEV_1          0x00000008U\n#define FLASH_OPTCR_BOR_LEV_Pos        (2U)\n#define FLASH_OPTCR_BOR_LEV_Msk        (0x3U << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */\n#define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk\n#define FLASH_OPTCR_WDG_SW_Pos         (5U)\n#define FLASH_OPTCR_WDG_SW_Msk         (0x1U << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */\n#define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk\n#define FLASH_OPTCR_nRST_STOP_Pos      (6U)\n#define FLASH_OPTCR_nRST_STOP_Msk      (0x1U << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */\n#define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk\n#define FLASH_OPTCR_nRST_STDBY_Pos     (7U)\n#define FLASH_OPTCR_nRST_STDBY_Msk     (0x1U << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */\n#define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk\n#define FLASH_OPTCR_RDP_Pos            (8U)\n#define FLASH_OPTCR_RDP_Msk            (0xFFU << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */\n#define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk\n#define FLASH_OPTCR_RDP_0              (0x01U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */\n#define FLASH_OPTCR_RDP_1              (0x02U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */\n#define FLASH_OPTCR_RDP_2              (0x04U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */\n#define FLASH_OPTCR_RDP_3              (0x08U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */\n#define FLASH_OPTCR_RDP_4              (0x10U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */\n#define FLASH_OPTCR_RDP_5              (0x20U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */\n#define FLASH_OPTCR_RDP_6              (0x40U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */\n#define FLASH_OPTCR_RDP_7              (0x80U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */\n#define FLASH_OPTCR_nWRP_Pos           (16U)\n#define FLASH_OPTCR_nWRP_Msk           (0xFFFU << FLASH_OPTCR_nWRP_Pos)        /*!< 0x0FFF0000 */\n#define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk\n#define FLASH_OPTCR_nWRP_0             0x00010000U\n#define FLASH_OPTCR_nWRP_1             0x00020000U\n#define FLASH_OPTCR_nWRP_2             0x00040000U\n#define FLASH_OPTCR_nWRP_3             0x00080000U\n#define FLASH_OPTCR_nWRP_4             0x00100000U\n#define FLASH_OPTCR_nWRP_5             0x00200000U\n#define FLASH_OPTCR_nWRP_6             0x00400000U\n#define FLASH_OPTCR_nWRP_7             0x00800000U\n#define FLASH_OPTCR_nWRP_8             0x01000000U\n#define FLASH_OPTCR_nWRP_9             0x02000000U\n#define FLASH_OPTCR_nWRP_10            0x04000000U\n#define FLASH_OPTCR_nWRP_11            0x08000000U\n\n/******************  Bits definition for FLASH_OPTCR1 register  ***************/\n#define FLASH_OPTCR1_nWRP_Pos          (16U)\n#define FLASH_OPTCR1_nWRP_Msk          (0xFFFU << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */\n#define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk\n#define FLASH_OPTCR1_nWRP_0            (0x001U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */\n#define FLASH_OPTCR1_nWRP_1            (0x002U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */\n#define FLASH_OPTCR1_nWRP_2            (0x004U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */\n#define FLASH_OPTCR1_nWRP_3            (0x008U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */\n#define FLASH_OPTCR1_nWRP_4            (0x010U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */\n#define FLASH_OPTCR1_nWRP_5            (0x020U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */\n#define FLASH_OPTCR1_nWRP_6            (0x040U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */\n#define FLASH_OPTCR1_nWRP_7            (0x080U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */\n#define FLASH_OPTCR1_nWRP_8            (0x100U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */\n#define FLASH_OPTCR1_nWRP_9            (0x200U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */\n#define FLASH_OPTCR1_nWRP_10           (0x400U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */\n#define FLASH_OPTCR1_nWRP_11           (0x800U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                   Flexible Static Memory Controller                        */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for FSMC_BCR1 register  *******************/\n#define FSMC_BCR1_MBKEN_Pos          (0U)\n#define FSMC_BCR1_MBKEN_Msk          (0x1U << FSMC_BCR1_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR1_MBKEN              FSMC_BCR1_MBKEN_Msk                       /*!<Memory bank enable bit                 */\n#define FSMC_BCR1_MUXEN_Pos          (1U)\n#define FSMC_BCR1_MUXEN_Msk          (0x1U << FSMC_BCR1_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR1_MUXEN              FSMC_BCR1_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR1_MTYP_Pos           (2U)\n#define FSMC_BCR1_MTYP_Msk           (0x3U << FSMC_BCR1_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR1_MTYP               FSMC_BCR1_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR1_MTYP_0             (0x1U << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR1_MTYP_1             (0x2U << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR1_MWID_Pos           (4U)\n#define FSMC_BCR1_MWID_Msk           (0x3U << FSMC_BCR1_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR1_MWID               FSMC_BCR1_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR1_MWID_0             (0x1U << FSMC_BCR1_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR1_MWID_1             (0x2U << FSMC_BCR1_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR1_FACCEN_Pos         (6U)\n#define FSMC_BCR1_FACCEN_Msk         (0x1U << FSMC_BCR1_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR1_FACCEN             FSMC_BCR1_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR1_BURSTEN_Pos        (8U)\n#define FSMC_BCR1_BURSTEN_Msk        (0x1U << FSMC_BCR1_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR1_BURSTEN            FSMC_BCR1_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR1_WAITPOL_Pos        (9U)\n#define FSMC_BCR1_WAITPOL_Msk        (0x1U << FSMC_BCR1_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR1_WAITPOL            FSMC_BCR1_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR1_WRAPMOD_Pos        (10U)\n#define FSMC_BCR1_WRAPMOD_Msk        (0x1U << FSMC_BCR1_WRAPMOD_Pos)           /*!< 0x00000400 */\n#define FSMC_BCR1_WRAPMOD            FSMC_BCR1_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */\n#define FSMC_BCR1_WAITCFG_Pos        (11U)\n#define FSMC_BCR1_WAITCFG_Msk        (0x1U << FSMC_BCR1_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR1_WAITCFG            FSMC_BCR1_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR1_WREN_Pos           (12U)\n#define FSMC_BCR1_WREN_Msk           (0x1U << FSMC_BCR1_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR1_WREN               FSMC_BCR1_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR1_WAITEN_Pos         (13U)\n#define FSMC_BCR1_WAITEN_Msk         (0x1U << FSMC_BCR1_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR1_WAITEN             FSMC_BCR1_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR1_EXTMOD_Pos         (14U)\n#define FSMC_BCR1_EXTMOD_Msk         (0x1U << FSMC_BCR1_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR1_EXTMOD             FSMC_BCR1_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR1_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR1_ASYNCWAIT_Msk      (0x1U << FSMC_BCR1_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR1_ASYNCWAIT          FSMC_BCR1_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR1_CPSIZE_Pos         (16U)\n#define FSMC_BCR1_CPSIZE_Msk         (0x7U << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR1_CPSIZE             FSMC_BCR1_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR1_CPSIZE_0           (0x1U << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR1_CPSIZE_1           (0x2U << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR1_CPSIZE_2           (0x4U << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR1_CBURSTRW_Pos       (19U)\n#define FSMC_BCR1_CBURSTRW_Msk       (0x1U << FSMC_BCR1_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR1_CBURSTRW           FSMC_BCR1_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BCR2 register  *******************/\n#define FSMC_BCR2_MBKEN_Pos          (0U)\n#define FSMC_BCR2_MBKEN_Msk          (0x1U << FSMC_BCR2_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR2_MBKEN              FSMC_BCR2_MBKEN_Msk                       /*!<Memory bank enable bit                */\n#define FSMC_BCR2_MUXEN_Pos          (1U)\n#define FSMC_BCR2_MUXEN_Msk          (0x1U << FSMC_BCR2_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR2_MUXEN              FSMC_BCR2_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR2_MTYP_Pos           (2U)\n#define FSMC_BCR2_MTYP_Msk           (0x3U << FSMC_BCR2_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR2_MTYP               FSMC_BCR2_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR2_MTYP_0             (0x1U << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR2_MTYP_1             (0x2U << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR2_MWID_Pos           (4U)\n#define FSMC_BCR2_MWID_Msk           (0x3U << FSMC_BCR2_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR2_MWID               FSMC_BCR2_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR2_MWID_0             (0x1U << FSMC_BCR2_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR2_MWID_1             (0x2U << FSMC_BCR2_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR2_FACCEN_Pos         (6U)\n#define FSMC_BCR2_FACCEN_Msk         (0x1U << FSMC_BCR2_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR2_FACCEN             FSMC_BCR2_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR2_BURSTEN_Pos        (8U)\n#define FSMC_BCR2_BURSTEN_Msk        (0x1U << FSMC_BCR2_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR2_BURSTEN            FSMC_BCR2_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR2_WAITPOL_Pos        (9U)\n#define FSMC_BCR2_WAITPOL_Msk        (0x1U << FSMC_BCR2_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR2_WAITPOL            FSMC_BCR2_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR2_WRAPMOD_Pos        (10U)\n#define FSMC_BCR2_WRAPMOD_Msk        (0x1U << FSMC_BCR2_WRAPMOD_Pos)           /*!< 0x00000400 */\n#define FSMC_BCR2_WRAPMOD            FSMC_BCR2_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */\n#define FSMC_BCR2_WAITCFG_Pos        (11U)\n#define FSMC_BCR2_WAITCFG_Msk        (0x1U << FSMC_BCR2_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR2_WAITCFG            FSMC_BCR2_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR2_WREN_Pos           (12U)\n#define FSMC_BCR2_WREN_Msk           (0x1U << FSMC_BCR2_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR2_WREN               FSMC_BCR2_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR2_WAITEN_Pos         (13U)\n#define FSMC_BCR2_WAITEN_Msk         (0x1U << FSMC_BCR2_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR2_WAITEN             FSMC_BCR2_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR2_EXTMOD_Pos         (14U)\n#define FSMC_BCR2_EXTMOD_Msk         (0x1U << FSMC_BCR2_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR2_EXTMOD             FSMC_BCR2_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR2_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR2_ASYNCWAIT_Msk      (0x1U << FSMC_BCR2_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR2_ASYNCWAIT          FSMC_BCR2_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR2_CPSIZE_Pos         (16U)\n#define FSMC_BCR2_CPSIZE_Msk         (0x7U << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR2_CPSIZE             FSMC_BCR2_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR2_CPSIZE_0           (0x1U << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR2_CPSIZE_1           (0x2U << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR2_CPSIZE_2           (0x4U << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR2_CBURSTRW_Pos       (19U)\n#define FSMC_BCR2_CBURSTRW_Msk       (0x1U << FSMC_BCR2_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR2_CBURSTRW           FSMC_BCR2_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BCR3 register  *******************/\n#define FSMC_BCR3_MBKEN_Pos          (0U)\n#define FSMC_BCR3_MBKEN_Msk          (0x1U << FSMC_BCR3_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR3_MBKEN              FSMC_BCR3_MBKEN_Msk                       /*!<Memory bank enable bit                 */\n#define FSMC_BCR3_MUXEN_Pos          (1U)\n#define FSMC_BCR3_MUXEN_Msk          (0x1U << FSMC_BCR3_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR3_MUXEN              FSMC_BCR3_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR3_MTYP_Pos           (2U)\n#define FSMC_BCR3_MTYP_Msk           (0x3U << FSMC_BCR3_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR3_MTYP               FSMC_BCR3_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR3_MTYP_0             (0x1U << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR3_MTYP_1             (0x2U << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR3_MWID_Pos           (4U)\n#define FSMC_BCR3_MWID_Msk           (0x3U << FSMC_BCR3_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR3_MWID               FSMC_BCR3_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR3_MWID_0             (0x1U << FSMC_BCR3_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR3_MWID_1             (0x2U << FSMC_BCR3_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR3_FACCEN_Pos         (6U)\n#define FSMC_BCR3_FACCEN_Msk         (0x1U << FSMC_BCR3_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR3_FACCEN             FSMC_BCR3_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR3_BURSTEN_Pos        (8U)\n#define FSMC_BCR3_BURSTEN_Msk        (0x1U << FSMC_BCR3_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR3_BURSTEN            FSMC_BCR3_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR3_WAITPOL_Pos        (9U)\n#define FSMC_BCR3_WAITPOL_Msk        (0x1U << FSMC_BCR3_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR3_WAITPOL            FSMC_BCR3_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR3_WRAPMOD_Pos        (10U)\n#define FSMC_BCR3_WRAPMOD_Msk        (0x1U << FSMC_BCR3_WRAPMOD_Pos)           /*!< 0x00000400 */\n#define FSMC_BCR3_WRAPMOD            FSMC_BCR3_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */\n#define FSMC_BCR3_WAITCFG_Pos        (11U)\n#define FSMC_BCR3_WAITCFG_Msk        (0x1U << FSMC_BCR3_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR3_WAITCFG            FSMC_BCR3_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR3_WREN_Pos           (12U)\n#define FSMC_BCR3_WREN_Msk           (0x1U << FSMC_BCR3_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR3_WREN               FSMC_BCR3_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR3_WAITEN_Pos         (13U)\n#define FSMC_BCR3_WAITEN_Msk         (0x1U << FSMC_BCR3_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR3_WAITEN             FSMC_BCR3_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR3_EXTMOD_Pos         (14U)\n#define FSMC_BCR3_EXTMOD_Msk         (0x1U << FSMC_BCR3_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR3_EXTMOD             FSMC_BCR3_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR3_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR3_ASYNCWAIT_Msk      (0x1U << FSMC_BCR3_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR3_ASYNCWAIT          FSMC_BCR3_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR3_CPSIZE_Pos         (16U)\n#define FSMC_BCR3_CPSIZE_Msk         (0x7U << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR3_CPSIZE             FSMC_BCR3_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR3_CPSIZE_0           (0x1U << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR3_CPSIZE_1           (0x2U << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR3_CPSIZE_2           (0x4U << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR3_CBURSTRW_Pos       (19U)\n#define FSMC_BCR3_CBURSTRW_Msk       (0x1U << FSMC_BCR3_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR3_CBURSTRW           FSMC_BCR3_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BCR4 register  *******************/\n#define FSMC_BCR4_MBKEN_Pos          (0U)\n#define FSMC_BCR4_MBKEN_Msk          (0x1U << FSMC_BCR4_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR4_MBKEN              FSMC_BCR4_MBKEN_Msk                       /*!<Memory bank enable bit */\n#define FSMC_BCR4_MUXEN_Pos          (1U)\n#define FSMC_BCR4_MUXEN_Msk          (0x1U << FSMC_BCR4_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR4_MUXEN              FSMC_BCR4_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR4_MTYP_Pos           (2U)\n#define FSMC_BCR4_MTYP_Msk           (0x3U << FSMC_BCR4_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR4_MTYP               FSMC_BCR4_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR4_MTYP_0             (0x1U << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR4_MTYP_1             (0x2U << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR4_MWID_Pos           (4U)\n#define FSMC_BCR4_MWID_Msk           (0x3U << FSMC_BCR4_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR4_MWID               FSMC_BCR4_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR4_MWID_0             (0x1U << FSMC_BCR4_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR4_MWID_1             (0x2U << FSMC_BCR4_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR4_FACCEN_Pos         (6U)\n#define FSMC_BCR4_FACCEN_Msk         (0x1U << FSMC_BCR4_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR4_FACCEN             FSMC_BCR4_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR4_BURSTEN_Pos        (8U)\n#define FSMC_BCR4_BURSTEN_Msk        (0x1U << FSMC_BCR4_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR4_BURSTEN            FSMC_BCR4_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR4_WAITPOL_Pos        (9U)\n#define FSMC_BCR4_WAITPOL_Msk        (0x1U << FSMC_BCR4_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR4_WAITPOL            FSMC_BCR4_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR4_WRAPMOD_Pos        (10U)\n#define FSMC_BCR4_WRAPMOD_Msk        (0x1U << FSMC_BCR4_WRAPMOD_Pos)           /*!< 0x00000400 */\n#define FSMC_BCR4_WRAPMOD            FSMC_BCR4_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */\n#define FSMC_BCR4_WAITCFG_Pos        (11U)\n#define FSMC_BCR4_WAITCFG_Msk        (0x1U << FSMC_BCR4_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR4_WAITCFG            FSMC_BCR4_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR4_WREN_Pos           (12U)\n#define FSMC_BCR4_WREN_Msk           (0x1U << FSMC_BCR4_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR4_WREN               FSMC_BCR4_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR4_WAITEN_Pos         (13U)\n#define FSMC_BCR4_WAITEN_Msk         (0x1U << FSMC_BCR4_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR4_WAITEN             FSMC_BCR4_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR4_EXTMOD_Pos         (14U)\n#define FSMC_BCR4_EXTMOD_Msk         (0x1U << FSMC_BCR4_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR4_EXTMOD             FSMC_BCR4_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR4_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR4_ASYNCWAIT_Msk      (0x1U << FSMC_BCR4_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR4_ASYNCWAIT          FSMC_BCR4_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR4_CPSIZE_Pos         (16U)\n#define FSMC_BCR4_CPSIZE_Msk         (0x7U << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR4_CPSIZE             FSMC_BCR4_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR4_CPSIZE_0           (0x1U << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR4_CPSIZE_1           (0x2U << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR4_CPSIZE_2           (0x4U << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR4_CBURSTRW_Pos       (19U)\n#define FSMC_BCR4_CBURSTRW_Msk       (0x1U << FSMC_BCR4_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR4_CBURSTRW           FSMC_BCR4_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BTR1 register  ******************/\n#define FSMC_BTR1_ADDSET_Pos         (0U)\n#define FSMC_BTR1_ADDSET_Msk         (0xFU << FSMC_BTR1_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR1_ADDSET             FSMC_BTR1_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR1_ADDSET_0           (0x1U << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR1_ADDSET_1           (0x2U << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR1_ADDSET_2           (0x4U << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR1_ADDSET_3           (0x8U << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR1_ADDHLD_Pos         (4U)\n#define FSMC_BTR1_ADDHLD_Msk         (0xFU << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR1_ADDHLD             FSMC_BTR1_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR1_ADDHLD_0           (0x1U << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR1_ADDHLD_1           (0x2U << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR1_ADDHLD_2           (0x4U << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR1_ADDHLD_3           (0x8U << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR1_DATAST_Pos         (8U)\n#define FSMC_BTR1_DATAST_Msk         (0xFFU << FSMC_BTR1_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR1_DATAST             FSMC_BTR1_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR1_DATAST_0           (0x01U << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR1_DATAST_1           (0x02U << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR1_DATAST_2           (0x04U << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR1_DATAST_3           (0x08U << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR1_DATAST_4           (0x10U << FSMC_BTR1_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR1_DATAST_5           (0x20U << FSMC_BTR1_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR1_DATAST_6           (0x40U << FSMC_BTR1_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR1_DATAST_7           (0x80U << FSMC_BTR1_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR1_BUSTURN_Pos        (16U)\n#define FSMC_BTR1_BUSTURN_Msk        (0xFU << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR1_BUSTURN            FSMC_BTR1_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR1_BUSTURN_0          (0x1U << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR1_BUSTURN_1          (0x2U << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR1_BUSTURN_2          (0x4U << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR1_BUSTURN_3          (0x8U << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR1_CLKDIV_Pos         (20U)\n#define FSMC_BTR1_CLKDIV_Msk         (0xFU << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR1_CLKDIV             FSMC_BTR1_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR1_CLKDIV_0           (0x1U << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR1_CLKDIV_1           (0x2U << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR1_CLKDIV_2           (0x4U << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR1_CLKDIV_3           (0x8U << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR1_DATLAT_Pos         (24U)\n#define FSMC_BTR1_DATLAT_Msk         (0xFU << FSMC_BTR1_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR1_DATLAT             FSMC_BTR1_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR1_DATLAT_0           (0x1U << FSMC_BTR1_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR1_DATLAT_1           (0x2U << FSMC_BTR1_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR1_DATLAT_2           (0x4U << FSMC_BTR1_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR1_DATLAT_3           (0x8U << FSMC_BTR1_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR1_ACCMOD_Pos         (28U)\n#define FSMC_BTR1_ACCMOD_Msk         (0x3U << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR1_ACCMOD             FSMC_BTR1_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR1_ACCMOD_0           (0x1U << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR1_ACCMOD_1           (0x2U << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BTR2 register  *******************/\n#define FSMC_BTR2_ADDSET_Pos         (0U)\n#define FSMC_BTR2_ADDSET_Msk         (0xFU << FSMC_BTR2_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR2_ADDSET             FSMC_BTR2_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR2_ADDSET_0           (0x1U << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR2_ADDSET_1           (0x2U << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR2_ADDSET_2           (0x4U << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR2_ADDSET_3           (0x8U << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR2_ADDHLD_Pos         (4U)\n#define FSMC_BTR2_ADDHLD_Msk         (0xFU << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR2_ADDHLD             FSMC_BTR2_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR2_ADDHLD_0           (0x1U << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR2_ADDHLD_1           (0x2U << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR2_ADDHLD_2           (0x4U << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR2_ADDHLD_3           (0x8U << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR2_DATAST_Pos         (8U)\n#define FSMC_BTR2_DATAST_Msk         (0xFFU << FSMC_BTR2_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR2_DATAST             FSMC_BTR2_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR2_DATAST_0           (0x01U << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR2_DATAST_1           (0x02U << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR2_DATAST_2           (0x04U << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR2_DATAST_3           (0x08U << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR2_DATAST_4           (0x10U << FSMC_BTR2_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR2_DATAST_5           (0x20U << FSMC_BTR2_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR2_DATAST_6           (0x40U << FSMC_BTR2_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR2_DATAST_7           (0x80U << FSMC_BTR2_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR2_BUSTURN_Pos        (16U)\n#define FSMC_BTR2_BUSTURN_Msk        (0xFU << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR2_BUSTURN            FSMC_BTR2_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR2_BUSTURN_0          (0x1U << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR2_BUSTURN_1          (0x2U << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR2_BUSTURN_2          (0x4U << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR2_BUSTURN_3          (0x8U << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR2_CLKDIV_Pos         (20U)\n#define FSMC_BTR2_CLKDIV_Msk         (0xFU << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR2_CLKDIV             FSMC_BTR2_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR2_CLKDIV_0           (0x1U << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR2_CLKDIV_1           (0x2U << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR2_CLKDIV_2           (0x4U << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR2_CLKDIV_3           (0x8U << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR2_DATLAT_Pos         (24U)\n#define FSMC_BTR2_DATLAT_Msk         (0xFU << FSMC_BTR2_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR2_DATLAT             FSMC_BTR2_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR2_DATLAT_0           (0x1U << FSMC_BTR2_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR2_DATLAT_1           (0x2U << FSMC_BTR2_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR2_DATLAT_2           (0x4U << FSMC_BTR2_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR2_DATLAT_3           (0x8U << FSMC_BTR2_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR2_ACCMOD_Pos         (28U)\n#define FSMC_BTR2_ACCMOD_Msk         (0x3U << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR2_ACCMOD             FSMC_BTR2_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR2_ACCMOD_0           (0x1U << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR2_ACCMOD_1           (0x2U << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/*******************  Bit definition for FSMC_BTR3 register  *******************/\n#define FSMC_BTR3_ADDSET_Pos         (0U)\n#define FSMC_BTR3_ADDSET_Msk         (0xFU << FSMC_BTR3_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR3_ADDSET             FSMC_BTR3_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR3_ADDSET_0           (0x1U << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR3_ADDSET_1           (0x2U << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR3_ADDSET_2           (0x4U << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR3_ADDSET_3           (0x8U << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR3_ADDHLD_Pos         (4U)\n#define FSMC_BTR3_ADDHLD_Msk         (0xFU << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR3_ADDHLD             FSMC_BTR3_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR3_ADDHLD_0           (0x1U << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR3_ADDHLD_1           (0x2U << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR3_ADDHLD_2           (0x4U << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR3_ADDHLD_3           (0x8U << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR3_DATAST_Pos         (8U)\n#define FSMC_BTR3_DATAST_Msk         (0xFFU << FSMC_BTR3_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR3_DATAST             FSMC_BTR3_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR3_DATAST_0           (0x01U << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR3_DATAST_1           (0x02U << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR3_DATAST_2           (0x04U << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR3_DATAST_3           (0x08U << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR3_DATAST_4           (0x10U << FSMC_BTR3_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR3_DATAST_5           (0x20U << FSMC_BTR3_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR3_DATAST_6           (0x40U << FSMC_BTR3_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR3_DATAST_7           (0x80U << FSMC_BTR3_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR3_BUSTURN_Pos        (16U)\n#define FSMC_BTR3_BUSTURN_Msk        (0xFU << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR3_BUSTURN            FSMC_BTR3_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR3_BUSTURN_0          (0x1U << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR3_BUSTURN_1          (0x2U << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR3_BUSTURN_2          (0x4U << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR3_BUSTURN_3          (0x8U << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR3_CLKDIV_Pos         (20U)\n#define FSMC_BTR3_CLKDIV_Msk         (0xFU << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR3_CLKDIV             FSMC_BTR3_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR3_CLKDIV_0           (0x1U << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR3_CLKDIV_1           (0x2U << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR3_CLKDIV_2           (0x4U << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR3_CLKDIV_3           (0x8U << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR3_DATLAT_Pos         (24U)\n#define FSMC_BTR3_DATLAT_Msk         (0xFU << FSMC_BTR3_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR3_DATLAT             FSMC_BTR3_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR3_DATLAT_0           (0x1U << FSMC_BTR3_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR3_DATLAT_1           (0x2U << FSMC_BTR3_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR3_DATLAT_2           (0x4U << FSMC_BTR3_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR3_DATLAT_3           (0x8U << FSMC_BTR3_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR3_ACCMOD_Pos         (28U)\n#define FSMC_BTR3_ACCMOD_Msk         (0x3U << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR3_ACCMOD             FSMC_BTR3_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR3_ACCMOD_0           (0x1U << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR3_ACCMOD_1           (0x2U << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BTR4 register  *******************/\n#define FSMC_BTR4_ADDSET_Pos         (0U)\n#define FSMC_BTR4_ADDSET_Msk         (0xFU << FSMC_BTR4_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR4_ADDSET             FSMC_BTR4_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR4_ADDSET_0           (0x1U << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR4_ADDSET_1           (0x2U << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR4_ADDSET_2           (0x4U << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR4_ADDSET_3           (0x8U << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR4_ADDHLD_Pos         (4U)\n#define FSMC_BTR4_ADDHLD_Msk         (0xFU << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR4_ADDHLD             FSMC_BTR4_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR4_ADDHLD_0           (0x1U << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR4_ADDHLD_1           (0x2U << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR4_ADDHLD_2           (0x4U << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR4_ADDHLD_3           (0x8U << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR4_DATAST_Pos         (8U)\n#define FSMC_BTR4_DATAST_Msk         (0xFFU << FSMC_BTR4_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR4_DATAST             FSMC_BTR4_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR4_DATAST_0           (0x01U << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR4_DATAST_1           (0x02U << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR4_DATAST_2           (0x04U << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR4_DATAST_3           (0x08U << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR4_DATAST_4           (0x10U << FSMC_BTR4_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR4_DATAST_5           (0x20U << FSMC_BTR4_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR4_DATAST_6           (0x40U << FSMC_BTR4_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR4_DATAST_7           (0x80U << FSMC_BTR4_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR4_BUSTURN_Pos        (16U)\n#define FSMC_BTR4_BUSTURN_Msk        (0xFU << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR4_BUSTURN            FSMC_BTR4_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR4_BUSTURN_0          (0x1U << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR4_BUSTURN_1          (0x2U << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR4_BUSTURN_2          (0x4U << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR4_BUSTURN_3          (0x8U << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR4_CLKDIV_Pos         (20U)\n#define FSMC_BTR4_CLKDIV_Msk         (0xFU << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR4_CLKDIV             FSMC_BTR4_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR4_CLKDIV_0           (0x1U << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR4_CLKDIV_1           (0x2U << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR4_CLKDIV_2           (0x4U << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR4_CLKDIV_3           (0x8U << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR4_DATLAT_Pos         (24U)\n#define FSMC_BTR4_DATLAT_Msk         (0xFU << FSMC_BTR4_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR4_DATLAT             FSMC_BTR4_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR4_DATLAT_0           (0x1U << FSMC_BTR4_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR4_DATLAT_1           (0x2U << FSMC_BTR4_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR4_DATLAT_2           (0x4U << FSMC_BTR4_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR4_DATLAT_3           (0x8U << FSMC_BTR4_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR4_ACCMOD_Pos         (28U)\n#define FSMC_BTR4_ACCMOD_Msk         (0x3U << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR4_ACCMOD             FSMC_BTR4_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR4_ACCMOD_0           (0x1U << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR4_ACCMOD_1           (0x2U << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR1 register  ******************/\n#define FSMC_BWTR1_ADDSET_Pos        (0U)\n#define FSMC_BWTR1_ADDSET_Msk        (0xFU << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR1_ADDSET            FSMC_BWTR1_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR1_ADDSET_0          (0x1U << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR1_ADDSET_1          (0x2U << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR1_ADDSET_2          (0x4U << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR1_ADDSET_3          (0x8U << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR1_ADDHLD_Pos        (4U)\n#define FSMC_BWTR1_ADDHLD_Msk        (0xFU << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR1_ADDHLD            FSMC_BWTR1_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR1_ADDHLD_0          (0x1U << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR1_ADDHLD_1          (0x2U << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR1_ADDHLD_2          (0x4U << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR1_ADDHLD_3          (0x8U << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR1_DATAST_Pos        (8U)\n#define FSMC_BWTR1_DATAST_Msk        (0xFFU << FSMC_BWTR1_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR1_DATAST            FSMC_BWTR1_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR1_DATAST_0          (0x01U << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR1_DATAST_1          (0x02U << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR1_DATAST_2          (0x04U << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR1_DATAST_3          (0x08U << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR1_DATAST_4          (0x10U << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR1_DATAST_5          (0x20U << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR1_DATAST_6          (0x40U << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR1_DATAST_7          (0x80U << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR1_BUSTURN_Pos       (16U)\n#define FSMC_BWTR1_BUSTURN_Msk       (0xFU << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR1_BUSTURN           FSMC_BWTR1_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR1_BUSTURN_0         (0x1U << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR1_BUSTURN_1         (0x2U << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR1_BUSTURN_2         (0x4U << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR1_BUSTURN_3         (0x8U << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR1_ACCMOD_Pos        (28U)\n#define FSMC_BWTR1_ACCMOD_Msk        (0x3U << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR1_ACCMOD            FSMC_BWTR1_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR1_ACCMOD_0          (0x1U << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR1_ACCMOD_1          (0x2U << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR2 register  ******************/\n#define FSMC_BWTR2_ADDSET_Pos        (0U)\n#define FSMC_BWTR2_ADDSET_Msk        (0xFU << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR2_ADDSET            FSMC_BWTR2_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR2_ADDSET_0          (0x1U << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR2_ADDSET_1          (0x2U << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR2_ADDSET_2          (0x4U << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR2_ADDSET_3          (0x8U << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR2_ADDHLD_Pos        (4U)\n#define FSMC_BWTR2_ADDHLD_Msk        (0xFU << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR2_ADDHLD            FSMC_BWTR2_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR2_ADDHLD_0          (0x1U << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR2_ADDHLD_1          (0x2U << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR2_ADDHLD_2          (0x4U << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR2_ADDHLD_3          (0x8U << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR2_DATAST_Pos        (8U)\n#define FSMC_BWTR2_DATAST_Msk        (0xFFU << FSMC_BWTR2_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR2_DATAST            FSMC_BWTR2_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR2_DATAST_0          (0x01U << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR2_DATAST_1          (0x02U << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR2_DATAST_2          (0x04U << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR2_DATAST_3          (0x08U << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR2_DATAST_4          (0x10U << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR2_DATAST_5          (0x20U << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR2_DATAST_6          (0x40U << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR2_DATAST_7          (0x80U << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR2_BUSTURN_Pos       (16U)\n#define FSMC_BWTR2_BUSTURN_Msk       (0xFU << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR2_BUSTURN           FSMC_BWTR2_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR2_BUSTURN_0         (0x1U << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR2_BUSTURN_1         (0x2U << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR2_BUSTURN_2         (0x4U << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR2_BUSTURN_3         (0x8U << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR2_ACCMOD_Pos        (28U)\n#define FSMC_BWTR2_ACCMOD_Msk        (0x3U << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR2_ACCMOD            FSMC_BWTR2_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR2_ACCMOD_0          (0x1U << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR2_ACCMOD_1          (0x2U << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR3 register  ******************/\n#define FSMC_BWTR3_ADDSET_Pos        (0U)\n#define FSMC_BWTR3_ADDSET_Msk        (0xFU << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR3_ADDSET            FSMC_BWTR3_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR3_ADDSET_0          (0x1U << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR3_ADDSET_1          (0x2U << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR3_ADDSET_2          (0x4U << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR3_ADDSET_3          (0x8U << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR3_ADDHLD_Pos        (4U)\n#define FSMC_BWTR3_ADDHLD_Msk        (0xFU << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR3_ADDHLD            FSMC_BWTR3_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR3_ADDHLD_0          (0x1U << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR3_ADDHLD_1          (0x2U << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR3_ADDHLD_2          (0x4U << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR3_ADDHLD_3          (0x8U << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR3_DATAST_Pos        (8U)\n#define FSMC_BWTR3_DATAST_Msk        (0xFFU << FSMC_BWTR3_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR3_DATAST            FSMC_BWTR3_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR3_DATAST_0          (0x01U << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR3_DATAST_1          (0x02U << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR3_DATAST_2          (0x04U << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR3_DATAST_3          (0x08U << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR3_DATAST_4          (0x10U << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR3_DATAST_5          (0x20U << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR3_DATAST_6          (0x40U << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR3_DATAST_7          (0x80U << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR3_BUSTURN_Pos       (16U)\n#define FSMC_BWTR3_BUSTURN_Msk       (0xFU << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR3_BUSTURN           FSMC_BWTR3_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR3_BUSTURN_0         (0x1U << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR3_BUSTURN_1         (0x2U << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR3_BUSTURN_2         (0x4U << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR3_BUSTURN_3         (0x8U << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR3_ACCMOD_Pos        (28U)\n#define FSMC_BWTR3_ACCMOD_Msk        (0x3U << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR3_ACCMOD            FSMC_BWTR3_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR3_ACCMOD_0          (0x1U << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR3_ACCMOD_1          (0x2U << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR4 register  ******************/\n#define FSMC_BWTR4_ADDSET_Pos        (0U)\n#define FSMC_BWTR4_ADDSET_Msk        (0xFU << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR4_ADDSET            FSMC_BWTR4_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR4_ADDSET_0          (0x1U << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR4_ADDSET_1          (0x2U << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR4_ADDSET_2          (0x4U << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR4_ADDSET_3          (0x8U << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR4_ADDHLD_Pos        (4U)\n#define FSMC_BWTR4_ADDHLD_Msk        (0xFU << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR4_ADDHLD            FSMC_BWTR4_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR4_ADDHLD_0          (0x1U << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR4_ADDHLD_1          (0x2U << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR4_ADDHLD_2          (0x4U << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR4_ADDHLD_3          (0x8U << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR4_DATAST_Pos        (8U)\n#define FSMC_BWTR4_DATAST_Msk        (0xFFU << FSMC_BWTR4_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR4_DATAST            FSMC_BWTR4_DATAST_Msk                     /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FSMC_BWTR4_DATAST_0          0x00000100U                               /*!<Bit 0 */\n#define FSMC_BWTR4_DATAST_1          0x00000200U                               /*!<Bit 1 */\n#define FSMC_BWTR4_DATAST_2          0x00000400U                               /*!<Bit 2 */\n#define FSMC_BWTR4_DATAST_3          0x00000800U                               /*!<Bit 3 */\n#define FSMC_BWTR4_DATAST_4          0x00001000U                               /*!<Bit 4 */\n#define FSMC_BWTR4_DATAST_5          0x00002000U                               /*!<Bit 5 */\n#define FSMC_BWTR4_DATAST_6          0x00004000U                               /*!<Bit 6 */\n#define FSMC_BWTR4_DATAST_7          0x00008000U                               /*!<Bit 7 */\n\n#define FSMC_BWTR4_BUSTURN_Pos       (16U)\n#define FSMC_BWTR4_BUSTURN_Msk       (0xFU << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR4_BUSTURN           FSMC_BWTR4_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR4_BUSTURN_0         (0x1U << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR4_BUSTURN_1         (0x2U << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR4_BUSTURN_2         (0x4U << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR4_BUSTURN_3         (0x8U << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR4_ACCMOD_Pos        (28U)\n#define FSMC_BWTR4_ACCMOD_Msk        (0x3U << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR4_ACCMOD            FSMC_BWTR4_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR4_ACCMOD_0          (0x1U << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR4_ACCMOD_1          (0x2U << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_PCR2 register  *******************/\n#define FSMC_PCR2_PWAITEN_Pos        (1U)\n#define FSMC_PCR2_PWAITEN_Msk        (0x1U << FSMC_PCR2_PWAITEN_Pos)           /*!< 0x00000002 */\n#define FSMC_PCR2_PWAITEN            FSMC_PCR2_PWAITEN_Msk                     /*!<Wait feature enable bit */\n#define FSMC_PCR2_PBKEN_Pos          (2U)\n#define FSMC_PCR2_PBKEN_Msk          (0x1U << FSMC_PCR2_PBKEN_Pos)             /*!< 0x00000004 */\n#define FSMC_PCR2_PBKEN              FSMC_PCR2_PBKEN_Msk                       /*!<PC Card/NAND Flash memory bank enable bit */\n#define FSMC_PCR2_PTYP_Pos           (3U)\n#define FSMC_PCR2_PTYP_Msk           (0x1U << FSMC_PCR2_PTYP_Pos)              /*!< 0x00000008 */\n#define FSMC_PCR2_PTYP               FSMC_PCR2_PTYP_Msk                        /*!<Memory type */\n\n#define FSMC_PCR2_PWID_Pos           (4U)\n#define FSMC_PCR2_PWID_Msk           (0x3U << FSMC_PCR2_PWID_Pos)              /*!< 0x00000030 */\n#define FSMC_PCR2_PWID               FSMC_PCR2_PWID_Msk                        /*!<PWID[1:0] bits (NAND Flash databus width) */\n#define FSMC_PCR2_PWID_0             (0x1U << FSMC_PCR2_PWID_Pos)              /*!< 0x00000010 */\n#define FSMC_PCR2_PWID_1             (0x2U << FSMC_PCR2_PWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_PCR2_ECCEN_Pos          (6U)\n#define FSMC_PCR2_ECCEN_Msk          (0x1U << FSMC_PCR2_ECCEN_Pos)             /*!< 0x00000040 */\n#define FSMC_PCR2_ECCEN              FSMC_PCR2_ECCEN_Msk                       /*!<ECC computation logic enable bit */\n\n#define FSMC_PCR2_TCLR_Pos           (9U)\n#define FSMC_PCR2_TCLR_Msk           (0xFU << FSMC_PCR2_TCLR_Pos)              /*!< 0x00001E00 */\n#define FSMC_PCR2_TCLR               FSMC_PCR2_TCLR_Msk                        /*!<TCLR[3:0] bits (CLE to RE delay) */\n#define FSMC_PCR2_TCLR_0             (0x1U << FSMC_PCR2_TCLR_Pos)              /*!< 0x00000200 */\n#define FSMC_PCR2_TCLR_1             (0x2U << FSMC_PCR2_TCLR_Pos)              /*!< 0x00000400 */\n#define FSMC_PCR2_TCLR_2             (0x4U << FSMC_PCR2_TCLR_Pos)              /*!< 0x00000800 */\n#define FSMC_PCR2_TCLR_3             (0x8U << FSMC_PCR2_TCLR_Pos)              /*!< 0x00001000 */\n\n#define FSMC_PCR2_TAR_Pos            (13U)\n#define FSMC_PCR2_TAR_Msk            (0xFU << FSMC_PCR2_TAR_Pos)               /*!< 0x0001E000 */\n#define FSMC_PCR2_TAR                FSMC_PCR2_TAR_Msk                         /*!<TAR[3:0] bits (ALE to RE delay) */\n#define FSMC_PCR2_TAR_0              (0x1U << FSMC_PCR2_TAR_Pos)               /*!< 0x00002000 */\n#define FSMC_PCR2_TAR_1              (0x2U << FSMC_PCR2_TAR_Pos)               /*!< 0x00004000 */\n#define FSMC_PCR2_TAR_2              (0x4U << FSMC_PCR2_TAR_Pos)               /*!< 0x00008000 */\n#define FSMC_PCR2_TAR_3              (0x8U << FSMC_PCR2_TAR_Pos)               /*!< 0x00010000 */\n\n#define FSMC_PCR2_ECCPS_Pos          (17U)\n#define FSMC_PCR2_ECCPS_Msk          (0x7U << FSMC_PCR2_ECCPS_Pos)             /*!< 0x000E0000 */\n#define FSMC_PCR2_ECCPS              FSMC_PCR2_ECCPS_Msk                       /*!<ECCPS[1:0] bits (ECC page size) */\n#define FSMC_PCR2_ECCPS_0            (0x1U << FSMC_PCR2_ECCPS_Pos)             /*!< 0x00020000 */\n#define FSMC_PCR2_ECCPS_1            (0x2U << FSMC_PCR2_ECCPS_Pos)             /*!< 0x00040000 */\n#define FSMC_PCR2_ECCPS_2            (0x4U << FSMC_PCR2_ECCPS_Pos)             /*!< 0x00080000 */\n\n/******************  Bit definition for FSMC_PCR3 register  *******************/\n#define FSMC_PCR3_PWAITEN_Pos        (1U)\n#define FSMC_PCR3_PWAITEN_Msk        (0x1U << FSMC_PCR3_PWAITEN_Pos)           /*!< 0x00000002 */\n#define FSMC_PCR3_PWAITEN            FSMC_PCR3_PWAITEN_Msk                     /*!<Wait feature enable bit */\n#define FSMC_PCR3_PBKEN_Pos          (2U)\n#define FSMC_PCR3_PBKEN_Msk          (0x1U << FSMC_PCR3_PBKEN_Pos)             /*!< 0x00000004 */\n#define FSMC_PCR3_PBKEN              FSMC_PCR3_PBKEN_Msk                       /*!<PC Card/NAND Flash memory bank enable bit */\n#define FSMC_PCR3_PTYP_Pos           (3U)\n#define FSMC_PCR3_PTYP_Msk           (0x1U << FSMC_PCR3_PTYP_Pos)              /*!< 0x00000008 */\n#define FSMC_PCR3_PTYP               FSMC_PCR3_PTYP_Msk                        /*!<Memory type */\n\n#define FSMC_PCR3_PWID_Pos           (4U)\n#define FSMC_PCR3_PWID_Msk           (0x3U << FSMC_PCR3_PWID_Pos)              /*!< 0x00000030 */\n#define FSMC_PCR3_PWID               FSMC_PCR3_PWID_Msk                        /*!<PWID[1:0] bits (NAND Flash databus width) */\n#define FSMC_PCR3_PWID_0             (0x1U << FSMC_PCR3_PWID_Pos)              /*!< 0x00000010 */\n#define FSMC_PCR3_PWID_1             (0x2U << FSMC_PCR3_PWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_PCR3_ECCEN_Pos          (6U)\n#define FSMC_PCR3_ECCEN_Msk          (0x1U << FSMC_PCR3_ECCEN_Pos)             /*!< 0x00000040 */\n#define FSMC_PCR3_ECCEN              FSMC_PCR3_ECCEN_Msk                       /*!<ECC computation logic enable bit */\n\n#define FSMC_PCR3_TCLR_Pos           (9U)\n#define FSMC_PCR3_TCLR_Msk           (0xFU << FSMC_PCR3_TCLR_Pos)              /*!< 0x00001E00 */\n#define FSMC_PCR3_TCLR               FSMC_PCR3_TCLR_Msk                        /*!<TCLR[3:0] bits (CLE to RE delay) */\n#define FSMC_PCR3_TCLR_0             (0x1U << FSMC_PCR3_TCLR_Pos)              /*!< 0x00000200 */\n#define FSMC_PCR3_TCLR_1             (0x2U << FSMC_PCR3_TCLR_Pos)              /*!< 0x00000400 */\n#define FSMC_PCR3_TCLR_2             (0x4U << FSMC_PCR3_TCLR_Pos)              /*!< 0x00000800 */\n#define FSMC_PCR3_TCLR_3             (0x8U << FSMC_PCR3_TCLR_Pos)              /*!< 0x00001000 */\n\n#define FSMC_PCR3_TAR_Pos            (13U)\n#define FSMC_PCR3_TAR_Msk            (0xFU << FSMC_PCR3_TAR_Pos)               /*!< 0x0001E000 */\n#define FSMC_PCR3_TAR                FSMC_PCR3_TAR_Msk                         /*!<TAR[3:0] bits (ALE to RE delay) */\n#define FSMC_PCR3_TAR_0              (0x1U << FSMC_PCR3_TAR_Pos)               /*!< 0x00002000 */\n#define FSMC_PCR3_TAR_1              (0x2U << FSMC_PCR3_TAR_Pos)               /*!< 0x00004000 */\n#define FSMC_PCR3_TAR_2              (0x4U << FSMC_PCR3_TAR_Pos)               /*!< 0x00008000 */\n#define FSMC_PCR3_TAR_3              (0x8U << FSMC_PCR3_TAR_Pos)               /*!< 0x00010000 */\n\n#define FSMC_PCR3_ECCPS_Pos          (17U)\n#define FSMC_PCR3_ECCPS_Msk          (0x7U << FSMC_PCR3_ECCPS_Pos)             /*!< 0x000E0000 */\n#define FSMC_PCR3_ECCPS              FSMC_PCR3_ECCPS_Msk                       /*!<ECCPS[2:0] bits (ECC page size) */\n#define FSMC_PCR3_ECCPS_0            (0x1U << FSMC_PCR3_ECCPS_Pos)             /*!< 0x00020000 */\n#define FSMC_PCR3_ECCPS_1            (0x2U << FSMC_PCR3_ECCPS_Pos)             /*!< 0x00040000 */\n#define FSMC_PCR3_ECCPS_2            (0x4U << FSMC_PCR3_ECCPS_Pos)             /*!< 0x00080000 */\n\n/******************  Bit definition for FSMC_PCR4 register  *******************/\n#define FSMC_PCR4_PWAITEN_Pos        (1U)\n#define FSMC_PCR4_PWAITEN_Msk        (0x1U << FSMC_PCR4_PWAITEN_Pos)           /*!< 0x00000002 */\n#define FSMC_PCR4_PWAITEN            FSMC_PCR4_PWAITEN_Msk                     /*!<Wait feature enable bit */\n#define FSMC_PCR4_PBKEN_Pos          (2U)\n#define FSMC_PCR4_PBKEN_Msk          (0x1U << FSMC_PCR4_PBKEN_Pos)             /*!< 0x00000004 */\n#define FSMC_PCR4_PBKEN              FSMC_PCR4_PBKEN_Msk                       /*!<PC Card/NAND Flash memory bank enable bit */\n#define FSMC_PCR4_PTYP_Pos           (3U)\n#define FSMC_PCR4_PTYP_Msk           (0x1U << FSMC_PCR4_PTYP_Pos)              /*!< 0x00000008 */\n#define FSMC_PCR4_PTYP               FSMC_PCR4_PTYP_Msk                        /*!<Memory type */\n\n#define FSMC_PCR4_PWID_Pos           (4U)\n#define FSMC_PCR4_PWID_Msk           (0x3U << FSMC_PCR4_PWID_Pos)              /*!< 0x00000030 */\n#define FSMC_PCR4_PWID               FSMC_PCR4_PWID_Msk                        /*!<PWID[1:0] bits (NAND Flash databus width) */\n#define FSMC_PCR4_PWID_0             (0x1U << FSMC_PCR4_PWID_Pos)              /*!< 0x00000010 */\n#define FSMC_PCR4_PWID_1             (0x2U << FSMC_PCR4_PWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_PCR4_ECCEN_Pos          (6U)\n#define FSMC_PCR4_ECCEN_Msk          (0x1U << FSMC_PCR4_ECCEN_Pos)             /*!< 0x00000040 */\n#define FSMC_PCR4_ECCEN              FSMC_PCR4_ECCEN_Msk                       /*!<ECC computation logic enable bit */\n\n#define FSMC_PCR4_TCLR_Pos           (9U)\n#define FSMC_PCR4_TCLR_Msk           (0xFU << FSMC_PCR4_TCLR_Pos)              /*!< 0x00001E00 */\n#define FSMC_PCR4_TCLR               FSMC_PCR4_TCLR_Msk                        /*!<TCLR[3:0] bits (CLE to RE delay) */\n#define FSMC_PCR4_TCLR_0             (0x1U << FSMC_PCR4_TCLR_Pos)              /*!< 0x00000200 */\n#define FSMC_PCR4_TCLR_1             (0x2U << FSMC_PCR4_TCLR_Pos)              /*!< 0x00000400 */\n#define FSMC_PCR4_TCLR_2             (0x4U << FSMC_PCR4_TCLR_Pos)              /*!< 0x00000800 */\n#define FSMC_PCR4_TCLR_3             (0x8U << FSMC_PCR4_TCLR_Pos)              /*!< 0x00001000 */\n\n#define FSMC_PCR4_TAR_Pos            (13U)\n#define FSMC_PCR4_TAR_Msk            (0xFU << FSMC_PCR4_TAR_Pos)               /*!< 0x0001E000 */\n#define FSMC_PCR4_TAR                FSMC_PCR4_TAR_Msk                         /*!<TAR[3:0] bits (ALE to RE delay) */\n#define FSMC_PCR4_TAR_0              (0x1U << FSMC_PCR4_TAR_Pos)               /*!< 0x00002000 */\n#define FSMC_PCR4_TAR_1              (0x2U << FSMC_PCR4_TAR_Pos)               /*!< 0x00004000 */\n#define FSMC_PCR4_TAR_2              (0x4U << FSMC_PCR4_TAR_Pos)               /*!< 0x00008000 */\n#define FSMC_PCR4_TAR_3              (0x8U << FSMC_PCR4_TAR_Pos)               /*!< 0x00010000 */\n\n#define FSMC_PCR4_ECCPS_Pos          (17U)\n#define FSMC_PCR4_ECCPS_Msk          (0x7U << FSMC_PCR4_ECCPS_Pos)             /*!< 0x000E0000 */\n#define FSMC_PCR4_ECCPS              FSMC_PCR4_ECCPS_Msk                       /*!<ECCPS[2:0] bits (ECC page size) */\n#define FSMC_PCR4_ECCPS_0            (0x1U << FSMC_PCR4_ECCPS_Pos)             /*!< 0x00020000 */\n#define FSMC_PCR4_ECCPS_1            (0x2U << FSMC_PCR4_ECCPS_Pos)             /*!< 0x00040000 */\n#define FSMC_PCR4_ECCPS_2            (0x4U << FSMC_PCR4_ECCPS_Pos)             /*!< 0x00080000 */\n\n/*******************  Bit definition for FSMC_SR2 register  *******************/\n#define FSMC_SR2_IRS_Pos             (0U)\n#define FSMC_SR2_IRS_Msk             (0x1U << FSMC_SR2_IRS_Pos)                /*!< 0x00000001 */\n#define FSMC_SR2_IRS                 FSMC_SR2_IRS_Msk                          /*!<Interrupt Rising Edge status                */\n#define FSMC_SR2_ILS_Pos             (1U)\n#define FSMC_SR2_ILS_Msk             (0x1U << FSMC_SR2_ILS_Pos)                /*!< 0x00000002 */\n#define FSMC_SR2_ILS                 FSMC_SR2_ILS_Msk                          /*!<Interrupt Level status                      */\n#define FSMC_SR2_IFS_Pos             (2U)\n#define FSMC_SR2_IFS_Msk             (0x1U << FSMC_SR2_IFS_Pos)                /*!< 0x00000004 */\n#define FSMC_SR2_IFS                 FSMC_SR2_IFS_Msk                          /*!<Interrupt Falling Edge status               */\n#define FSMC_SR2_IREN_Pos            (3U)\n#define FSMC_SR2_IREN_Msk            (0x1U << FSMC_SR2_IREN_Pos)               /*!< 0x00000008 */\n#define FSMC_SR2_IREN                FSMC_SR2_IREN_Msk                         /*!<Interrupt Rising Edge detection Enable bit  */\n#define FSMC_SR2_ILEN_Pos            (4U)\n#define FSMC_SR2_ILEN_Msk            (0x1U << FSMC_SR2_ILEN_Pos)               /*!< 0x00000010 */\n#define FSMC_SR2_ILEN                FSMC_SR2_ILEN_Msk                         /*!<Interrupt Level detection Enable bit        */\n#define FSMC_SR2_IFEN_Pos            (5U)\n#define FSMC_SR2_IFEN_Msk            (0x1U << FSMC_SR2_IFEN_Pos)               /*!< 0x00000020 */\n#define FSMC_SR2_IFEN                FSMC_SR2_IFEN_Msk                         /*!<Interrupt Falling Edge detection Enable bit */\n#define FSMC_SR2_FEMPT_Pos           (6U)\n#define FSMC_SR2_FEMPT_Msk           (0x1U << FSMC_SR2_FEMPT_Pos)              /*!< 0x00000040 */\n#define FSMC_SR2_FEMPT               FSMC_SR2_FEMPT_Msk                        /*!<FIFO empty */\n\n/*******************  Bit definition for FSMC_SR3 register  *******************/\n#define FSMC_SR3_IRS_Pos             (0U)\n#define FSMC_SR3_IRS_Msk             (0x1U << FSMC_SR3_IRS_Pos)                /*!< 0x00000001 */\n#define FSMC_SR3_IRS                 FSMC_SR3_IRS_Msk                          /*!<Interrupt Rising Edge status                */\n#define FSMC_SR3_ILS_Pos             (1U)\n#define FSMC_SR3_ILS_Msk             (0x1U << FSMC_SR3_ILS_Pos)                /*!< 0x00000002 */\n#define FSMC_SR3_ILS                 FSMC_SR3_ILS_Msk                          /*!<Interrupt Level status                      */\n#define FSMC_SR3_IFS_Pos             (2U)\n#define FSMC_SR3_IFS_Msk             (0x1U << FSMC_SR3_IFS_Pos)                /*!< 0x00000004 */\n#define FSMC_SR3_IFS                 FSMC_SR3_IFS_Msk                          /*!<Interrupt Falling Edge status               */\n#define FSMC_SR3_IREN_Pos            (3U)\n#define FSMC_SR3_IREN_Msk            (0x1U << FSMC_SR3_IREN_Pos)               /*!< 0x00000008 */\n#define FSMC_SR3_IREN                FSMC_SR3_IREN_Msk                         /*!<Interrupt Rising Edge detection Enable bit  */\n#define FSMC_SR3_ILEN_Pos            (4U)\n#define FSMC_SR3_ILEN_Msk            (0x1U << FSMC_SR3_ILEN_Pos)               /*!< 0x00000010 */\n#define FSMC_SR3_ILEN                FSMC_SR3_ILEN_Msk                         /*!<Interrupt Level detection Enable bit        */\n#define FSMC_SR3_IFEN_Pos            (5U)\n#define FSMC_SR3_IFEN_Msk            (0x1U << FSMC_SR3_IFEN_Pos)               /*!< 0x00000020 */\n#define FSMC_SR3_IFEN                FSMC_SR3_IFEN_Msk                         /*!<Interrupt Falling Edge detection Enable bit */\n#define FSMC_SR3_FEMPT_Pos           (6U)\n#define FSMC_SR3_FEMPT_Msk           (0x1U << FSMC_SR3_FEMPT_Pos)              /*!< 0x00000040 */\n#define FSMC_SR3_FEMPT               FSMC_SR3_FEMPT_Msk                        /*!<FIFO empty */\n\n/*******************  Bit definition for FSMC_SR4 register  *******************/\n#define FSMC_SR4_IRS_Pos             (0U)\n#define FSMC_SR4_IRS_Msk             (0x1U << FSMC_SR4_IRS_Pos)                /*!< 0x00000001 */\n#define FSMC_SR4_IRS                 FSMC_SR4_IRS_Msk                          /*!<Interrupt Rising Edge status                 */\n#define FSMC_SR4_ILS_Pos             (1U)\n#define FSMC_SR4_ILS_Msk             (0x1U << FSMC_SR4_ILS_Pos)                /*!< 0x00000002 */\n#define FSMC_SR4_ILS                 FSMC_SR4_ILS_Msk                          /*!<Interrupt Level status                       */\n#define FSMC_SR4_IFS_Pos             (2U)\n#define FSMC_SR4_IFS_Msk             (0x1U << FSMC_SR4_IFS_Pos)                /*!< 0x00000004 */\n#define FSMC_SR4_IFS                 FSMC_SR4_IFS_Msk                          /*!<Interrupt Falling Edge status                */\n#define FSMC_SR4_IREN_Pos            (3U)\n#define FSMC_SR4_IREN_Msk            (0x1U << FSMC_SR4_IREN_Pos)               /*!< 0x00000008 */\n#define FSMC_SR4_IREN                FSMC_SR4_IREN_Msk                         /*!<Interrupt Rising Edge detection Enable bit   */\n#define FSMC_SR4_ILEN_Pos            (4U)\n#define FSMC_SR4_ILEN_Msk            (0x1U << FSMC_SR4_ILEN_Pos)               /*!< 0x00000010 */\n#define FSMC_SR4_ILEN                FSMC_SR4_ILEN_Msk                         /*!<Interrupt Level detection Enable bit         */\n#define FSMC_SR4_IFEN_Pos            (5U)\n#define FSMC_SR4_IFEN_Msk            (0x1U << FSMC_SR4_IFEN_Pos)               /*!< 0x00000020 */\n#define FSMC_SR4_IFEN                FSMC_SR4_IFEN_Msk                         /*!<Interrupt Falling Edge detection Enable bit  */\n#define FSMC_SR4_FEMPT_Pos           (6U)\n#define FSMC_SR4_FEMPT_Msk           (0x1U << FSMC_SR4_FEMPT_Pos)              /*!< 0x00000040 */\n#define FSMC_SR4_FEMPT               FSMC_SR4_FEMPT_Msk                        /*!<FIFO empty */\n\n/******************  Bit definition for FSMC_PMEM2 register  ******************/\n#define FSMC_PMEM2_MEMSET2_Pos       (0U)\n#define FSMC_PMEM2_MEMSET2_Msk       (0xFFU << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x000000FF */\n#define FSMC_PMEM2_MEMSET2           FSMC_PMEM2_MEMSET2_Msk                    /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */\n#define FSMC_PMEM2_MEMSET2_0         (0x01U << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000001 */\n#define FSMC_PMEM2_MEMSET2_1         (0x02U << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000002 */\n#define FSMC_PMEM2_MEMSET2_2         (0x04U << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000004 */\n#define FSMC_PMEM2_MEMSET2_3         (0x08U << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000008 */\n#define FSMC_PMEM2_MEMSET2_4         (0x10U << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000010 */\n#define FSMC_PMEM2_MEMSET2_5         (0x20U << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000020 */\n#define FSMC_PMEM2_MEMSET2_6         (0x40U << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000040 */\n#define FSMC_PMEM2_MEMSET2_7         (0x80U << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000080 */\n\n#define FSMC_PMEM2_MEMWAIT2_Pos      (8U)\n#define FSMC_PMEM2_MEMWAIT2_Msk      (0xFFU << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x0000FF00 */\n#define FSMC_PMEM2_MEMWAIT2          FSMC_PMEM2_MEMWAIT2_Msk                   /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */\n#define FSMC_PMEM2_MEMWAIT2_0        (0x01U << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000100 */\n#define FSMC_PMEM2_MEMWAIT2_1        (0x02U << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000200 */\n#define FSMC_PMEM2_MEMWAIT2_2        (0x04U << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000400 */\n#define FSMC_PMEM2_MEMWAIT2_3        (0x08U << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000800 */\n#define FSMC_PMEM2_MEMWAIT2_4        (0x10U << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00001000 */\n#define FSMC_PMEM2_MEMWAIT2_5        (0x20U << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00002000 */\n#define FSMC_PMEM2_MEMWAIT2_6        (0x40U << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00004000 */\n#define FSMC_PMEM2_MEMWAIT2_7        (0x80U << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00008000 */\n\n#define FSMC_PMEM2_MEMHOLD2_Pos      (16U)\n#define FSMC_PMEM2_MEMHOLD2_Msk      (0xFFU << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00FF0000 */\n#define FSMC_PMEM2_MEMHOLD2          FSMC_PMEM2_MEMHOLD2_Msk                   /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */\n#define FSMC_PMEM2_MEMHOLD2_0        (0x01U << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00010000 */\n#define FSMC_PMEM2_MEMHOLD2_1        (0x02U << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00020000 */\n#define FSMC_PMEM2_MEMHOLD2_2        (0x04U << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00040000 */\n#define FSMC_PMEM2_MEMHOLD2_3        (0x08U << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00080000 */\n#define FSMC_PMEM2_MEMHOLD2_4        (0x10U << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00100000 */\n#define FSMC_PMEM2_MEMHOLD2_5        (0x20U << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00200000 */\n#define FSMC_PMEM2_MEMHOLD2_6        (0x40U << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00400000 */\n#define FSMC_PMEM2_MEMHOLD2_7        (0x80U << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00800000 */\n\n#define FSMC_PMEM2_MEMHIZ2_Pos       (24U)\n#define FSMC_PMEM2_MEMHIZ2_Msk       (0xFFU << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0xFF000000 */\n#define FSMC_PMEM2_MEMHIZ2           FSMC_PMEM2_MEMHIZ2_Msk                    /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */\n#define FSMC_PMEM2_MEMHIZ2_0         (0x01U << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x01000000 */\n#define FSMC_PMEM2_MEMHIZ2_1         (0x02U << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x02000000 */\n#define FSMC_PMEM2_MEMHIZ2_2         (0x04U << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x04000000 */\n#define FSMC_PMEM2_MEMHIZ2_3         (0x08U << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x08000000 */\n#define FSMC_PMEM2_MEMHIZ2_4         (0x10U << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x10000000 */\n#define FSMC_PMEM2_MEMHIZ2_5         (0x20U << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x20000000 */\n#define FSMC_PMEM2_MEMHIZ2_6         (0x40U << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x40000000 */\n#define FSMC_PMEM2_MEMHIZ2_7         (0x80U << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_PMEM3 register  ******************/\n#define FSMC_PMEM3_MEMSET3_Pos       (0U)\n#define FSMC_PMEM3_MEMSET3_Msk       (0xFFU << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x000000FF */\n#define FSMC_PMEM3_MEMSET3           FSMC_PMEM3_MEMSET3_Msk                    /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\n#define FSMC_PMEM3_MEMSET3_0         (0x01U << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000001 */\n#define FSMC_PMEM3_MEMSET3_1         (0x02U << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000002 */\n#define FSMC_PMEM3_MEMSET3_2         (0x04U << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000004 */\n#define FSMC_PMEM3_MEMSET3_3         (0x08U << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000008 */\n#define FSMC_PMEM3_MEMSET3_4         (0x10U << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000010 */\n#define FSMC_PMEM3_MEMSET3_5         (0x20U << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000020 */\n#define FSMC_PMEM3_MEMSET3_6         (0x40U << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000040 */\n#define FSMC_PMEM3_MEMSET3_7         (0x80U << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000080 */\n\n#define FSMC_PMEM3_MEMWAIT3_Pos      (8U)\n#define FSMC_PMEM3_MEMWAIT3_Msk      (0xFFU << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x0000FF00 */\n#define FSMC_PMEM3_MEMWAIT3          FSMC_PMEM3_MEMWAIT3_Msk                   /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\n#define FSMC_PMEM3_MEMWAIT3_0        (0x01U << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000100 */\n#define FSMC_PMEM3_MEMWAIT3_1        (0x02U << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000200 */\n#define FSMC_PMEM3_MEMWAIT3_2        (0x04U << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000400 */\n#define FSMC_PMEM3_MEMWAIT3_3        (0x08U << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000800 */\n#define FSMC_PMEM3_MEMWAIT3_4        (0x10U << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00001000 */\n#define FSMC_PMEM3_MEMWAIT3_5        (0x20U << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00002000 */\n#define FSMC_PMEM3_MEMWAIT3_6        (0x40U << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00004000 */\n#define FSMC_PMEM3_MEMWAIT3_7        (0x80U << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00008000 */\n\n#define FSMC_PMEM3_MEMHOLD3_Pos      (16U)\n#define FSMC_PMEM3_MEMHOLD3_Msk      (0xFFU << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00FF0000 */\n#define FSMC_PMEM3_MEMHOLD3          FSMC_PMEM3_MEMHOLD3_Msk                   /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\n#define FSMC_PMEM3_MEMHOLD3_0        (0x01U << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00010000 */\n#define FSMC_PMEM3_MEMHOLD3_1        (0x02U << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00020000 */\n#define FSMC_PMEM3_MEMHOLD3_2        (0x04U << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00040000 */\n#define FSMC_PMEM3_MEMHOLD3_3        (0x08U << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00080000 */\n#define FSMC_PMEM3_MEMHOLD3_4        (0x10U << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00100000 */\n#define FSMC_PMEM3_MEMHOLD3_5        (0x20U << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00200000 */\n#define FSMC_PMEM3_MEMHOLD3_6        (0x40U << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00400000 */\n#define FSMC_PMEM3_MEMHOLD3_7        (0x80U << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00800000 */\n\n#define FSMC_PMEM3_MEMHIZ3_Pos       (24U)\n#define FSMC_PMEM3_MEMHIZ3_Msk       (0xFFU << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0xFF000000 */\n#define FSMC_PMEM3_MEMHIZ3           FSMC_PMEM3_MEMHIZ3_Msk                    /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\n#define FSMC_PMEM3_MEMHIZ3_0         (0x01U << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x01000000 */\n#define FSMC_PMEM3_MEMHIZ3_1         (0x02U << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x02000000 */\n#define FSMC_PMEM3_MEMHIZ3_2         (0x04U << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x04000000 */\n#define FSMC_PMEM3_MEMHIZ3_3         (0x08U << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x08000000 */\n#define FSMC_PMEM3_MEMHIZ3_4         (0x10U << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x10000000 */\n#define FSMC_PMEM3_MEMHIZ3_5         (0x20U << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x20000000 */\n#define FSMC_PMEM3_MEMHIZ3_6         (0x40U << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x40000000 */\n#define FSMC_PMEM3_MEMHIZ3_7         (0x80U << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_PMEM4 register  ******************/\n#define FSMC_PMEM4_MEMSET4_Pos       (0U)\n#define FSMC_PMEM4_MEMSET4_Msk       (0xFFU << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x000000FF */\n#define FSMC_PMEM4_MEMSET4           FSMC_PMEM4_MEMSET4_Msk                    /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */\n#define FSMC_PMEM4_MEMSET4_0         (0x01U << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000001 */\n#define FSMC_PMEM4_MEMSET4_1         (0x02U << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000002 */\n#define FSMC_PMEM4_MEMSET4_2         (0x04U << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000004 */\n#define FSMC_PMEM4_MEMSET4_3         (0x08U << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000008 */\n#define FSMC_PMEM4_MEMSET4_4         (0x10U << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000010 */\n#define FSMC_PMEM4_MEMSET4_5         (0x20U << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000020 */\n#define FSMC_PMEM4_MEMSET4_6         (0x40U << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000040 */\n#define FSMC_PMEM4_MEMSET4_7         (0x80U << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000080 */\n\n#define FSMC_PMEM4_MEMWAIT4_Pos      (8U)\n#define FSMC_PMEM4_MEMWAIT4_Msk      (0xFFU << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x0000FF00 */\n#define FSMC_PMEM4_MEMWAIT4          FSMC_PMEM4_MEMWAIT4_Msk                   /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */\n#define FSMC_PMEM4_MEMWAIT4_0        (0x01U << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000100 */\n#define FSMC_PMEM4_MEMWAIT4_1        (0x02U << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000200 */\n#define FSMC_PMEM4_MEMWAIT4_2        (0x04U << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000400 */\n#define FSMC_PMEM4_MEMWAIT4_3        (0x08U << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000800 */\n#define FSMC_PMEM4_MEMWAIT4_4        (0x10U << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00001000 */\n#define FSMC_PMEM4_MEMWAIT4_5        (0x20U << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00002000 */\n#define FSMC_PMEM4_MEMWAIT4_6        (0x40U << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00004000 */\n#define FSMC_PMEM4_MEMWAIT4_7        (0x80U << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00008000 */\n\n#define FSMC_PMEM4_MEMHOLD4_Pos      (16U)\n#define FSMC_PMEM4_MEMHOLD4_Msk      (0xFFU << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00FF0000 */\n#define FSMC_PMEM4_MEMHOLD4          FSMC_PMEM4_MEMHOLD4_Msk                   /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */\n#define FSMC_PMEM4_MEMHOLD4_0        (0x01U << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00010000 */\n#define FSMC_PMEM4_MEMHOLD4_1        (0x02U << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00020000 */\n#define FSMC_PMEM4_MEMHOLD4_2        (0x04U << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00040000 */\n#define FSMC_PMEM4_MEMHOLD4_3        (0x08U << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00080000 */\n#define FSMC_PMEM4_MEMHOLD4_4        (0x10U << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00100000 */\n#define FSMC_PMEM4_MEMHOLD4_5        (0x20U << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00200000 */\n#define FSMC_PMEM4_MEMHOLD4_6        (0x40U << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00400000 */\n#define FSMC_PMEM4_MEMHOLD4_7        (0x80U << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00800000 */\n\n#define FSMC_PMEM4_MEMHIZ4_Pos       (24U)\n#define FSMC_PMEM4_MEMHIZ4_Msk       (0xFFU << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0xFF000000 */\n#define FSMC_PMEM4_MEMHIZ4           FSMC_PMEM4_MEMHIZ4_Msk                    /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */\n#define FSMC_PMEM4_MEMHIZ4_0         (0x01U << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x01000000 */\n#define FSMC_PMEM4_MEMHIZ4_1         (0x02U << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x02000000 */\n#define FSMC_PMEM4_MEMHIZ4_2         (0x04U << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x04000000 */\n#define FSMC_PMEM4_MEMHIZ4_3         (0x08U << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x08000000 */\n#define FSMC_PMEM4_MEMHIZ4_4         (0x10U << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x10000000 */\n#define FSMC_PMEM4_MEMHIZ4_5         (0x20U << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x20000000 */\n#define FSMC_PMEM4_MEMHIZ4_6         (0x40U << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x40000000 */\n#define FSMC_PMEM4_MEMHIZ4_7         (0x80U << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_PATT2 register  ******************/\n#define FSMC_PATT2_ATTSET2_Pos       (0U)\n#define FSMC_PATT2_ATTSET2_Msk       (0xFFU << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x000000FF */\n#define FSMC_PATT2_ATTSET2           FSMC_PATT2_ATTSET2_Msk                    /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */\n#define FSMC_PATT2_ATTSET2_0         (0x01U << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000001 */\n#define FSMC_PATT2_ATTSET2_1         (0x02U << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000002 */\n#define FSMC_PATT2_ATTSET2_2         (0x04U << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000004 */\n#define FSMC_PATT2_ATTSET2_3         (0x08U << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000008 */\n#define FSMC_PATT2_ATTSET2_4         (0x10U << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000010 */\n#define FSMC_PATT2_ATTSET2_5         (0x20U << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000020 */\n#define FSMC_PATT2_ATTSET2_6         (0x40U << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000040 */\n#define FSMC_PATT2_ATTSET2_7         (0x80U << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000080 */\n\n#define FSMC_PATT2_ATTWAIT2_Pos      (8U)\n#define FSMC_PATT2_ATTWAIT2_Msk      (0xFFU << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x0000FF00 */\n#define FSMC_PATT2_ATTWAIT2          FSMC_PATT2_ATTWAIT2_Msk                   /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */\n#define FSMC_PATT2_ATTWAIT2_0        (0x01U << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000100 */\n#define FSMC_PATT2_ATTWAIT2_1        (0x02U << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000200 */\n#define FSMC_PATT2_ATTWAIT2_2        (0x04U << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000400 */\n#define FSMC_PATT2_ATTWAIT2_3        (0x08U << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000800 */\n#define FSMC_PATT2_ATTWAIT2_4        (0x10U << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00001000 */\n#define FSMC_PATT2_ATTWAIT2_5        (0x20U << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00002000 */\n#define FSMC_PATT2_ATTWAIT2_6        (0x40U << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00004000 */\n#define FSMC_PATT2_ATTWAIT2_7        (0x80U << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00008000 */\n\n#define FSMC_PATT2_ATTHOLD2_Pos      (16U)\n#define FSMC_PATT2_ATTHOLD2_Msk      (0xFFU << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00FF0000 */\n#define FSMC_PATT2_ATTHOLD2          FSMC_PATT2_ATTHOLD2_Msk                   /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */\n#define FSMC_PATT2_ATTHOLD2_0        (0x01U << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00010000 */\n#define FSMC_PATT2_ATTHOLD2_1        (0x02U << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00020000 */\n#define FSMC_PATT2_ATTHOLD2_2        (0x04U << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00040000 */\n#define FSMC_PATT2_ATTHOLD2_3        (0x08U << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00080000 */\n#define FSMC_PATT2_ATTHOLD2_4        (0x10U << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00100000 */\n#define FSMC_PATT2_ATTHOLD2_5        (0x20U << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00200000 */\n#define FSMC_PATT2_ATTHOLD2_6        (0x40U << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00400000 */\n#define FSMC_PATT2_ATTHOLD2_7        (0x80U << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00800000 */\n\n#define FSMC_PATT2_ATTHIZ2_Pos       (24U)\n#define FSMC_PATT2_ATTHIZ2_Msk       (0xFFU << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0xFF000000 */\n#define FSMC_PATT2_ATTHIZ2           FSMC_PATT2_ATTHIZ2_Msk                    /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */\n#define FSMC_PATT2_ATTHIZ2_0         (0x01U << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x01000000 */\n#define FSMC_PATT2_ATTHIZ2_1         (0x02U << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x02000000 */\n#define FSMC_PATT2_ATTHIZ2_2         (0x04U << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x04000000 */\n#define FSMC_PATT2_ATTHIZ2_3         (0x08U << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x08000000 */\n#define FSMC_PATT2_ATTHIZ2_4         (0x10U << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x10000000 */\n#define FSMC_PATT2_ATTHIZ2_5         (0x20U << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x20000000 */\n#define FSMC_PATT2_ATTHIZ2_6         (0x40U << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x40000000 */\n#define FSMC_PATT2_ATTHIZ2_7         (0x80U << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_PATT3 register  ******************/\n#define FSMC_PATT3_ATTSET3_Pos       (0U)\n#define FSMC_PATT3_ATTSET3_Msk       (0xFFU << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x000000FF */\n#define FSMC_PATT3_ATTSET3           FSMC_PATT3_ATTSET3_Msk                    /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\n#define FSMC_PATT3_ATTSET3_0         (0x01U << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000001 */\n#define FSMC_PATT3_ATTSET3_1         (0x02U << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000002 */\n#define FSMC_PATT3_ATTSET3_2         (0x04U << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000004 */\n#define FSMC_PATT3_ATTSET3_3         (0x08U << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000008 */\n#define FSMC_PATT3_ATTSET3_4         (0x10U << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000010 */\n#define FSMC_PATT3_ATTSET3_5         (0x20U << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000020 */\n#define FSMC_PATT3_ATTSET3_6         (0x40U << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000040 */\n#define FSMC_PATT3_ATTSET3_7         (0x80U << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000080 */\n\n#define FSMC_PATT3_ATTWAIT3_Pos      (8U)\n#define FSMC_PATT3_ATTWAIT3_Msk      (0xFFU << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x0000FF00 */\n#define FSMC_PATT3_ATTWAIT3          FSMC_PATT3_ATTWAIT3_Msk                   /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\n#define FSMC_PATT3_ATTWAIT3_0        (0x01U << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000100 */\n#define FSMC_PATT3_ATTWAIT3_1        (0x02U << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000200 */\n#define FSMC_PATT3_ATTWAIT3_2        (0x04U << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000400 */\n#define FSMC_PATT3_ATTWAIT3_3        (0x08U << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000800 */\n#define FSMC_PATT3_ATTWAIT3_4        (0x10U << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00001000 */\n#define FSMC_PATT3_ATTWAIT3_5        (0x20U << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00002000 */\n#define FSMC_PATT3_ATTWAIT3_6        (0x40U << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00004000 */\n#define FSMC_PATT3_ATTWAIT3_7        (0x80U << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00008000 */\n\n#define FSMC_PATT3_ATTHOLD3_Pos      (16U)\n#define FSMC_PATT3_ATTHOLD3_Msk      (0xFFU << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00FF0000 */\n#define FSMC_PATT3_ATTHOLD3          FSMC_PATT3_ATTHOLD3_Msk                   /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\n#define FSMC_PATT3_ATTHOLD3_0        (0x01U << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00010000 */\n#define FSMC_PATT3_ATTHOLD3_1        (0x02U << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00020000 */\n#define FSMC_PATT3_ATTHOLD3_2        (0x04U << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00040000 */\n#define FSMC_PATT3_ATTHOLD3_3        (0x08U << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00080000 */\n#define FSMC_PATT3_ATTHOLD3_4        (0x10U << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00100000 */\n#define FSMC_PATT3_ATTHOLD3_5        (0x20U << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00200000 */\n#define FSMC_PATT3_ATTHOLD3_6        (0x40U << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00400000 */\n#define FSMC_PATT3_ATTHOLD3_7        (0x80U << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00800000 */\n\n#define FSMC_PATT3_ATTHIZ3_Pos       (24U)\n#define FSMC_PATT3_ATTHIZ3_Msk       (0xFFU << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0xFF000000 */\n#define FSMC_PATT3_ATTHIZ3           FSMC_PATT3_ATTHIZ3_Msk                    /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\n#define FSMC_PATT3_ATTHIZ3_0         (0x01U << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x01000000 */\n#define FSMC_PATT3_ATTHIZ3_1         (0x02U << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x02000000 */\n#define FSMC_PATT3_ATTHIZ3_2         (0x04U << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x04000000 */\n#define FSMC_PATT3_ATTHIZ3_3         (0x08U << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x08000000 */\n#define FSMC_PATT3_ATTHIZ3_4         (0x10U << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x10000000 */\n#define FSMC_PATT3_ATTHIZ3_5         (0x20U << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x20000000 */\n#define FSMC_PATT3_ATTHIZ3_6         (0x40U << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x40000000 */\n#define FSMC_PATT3_ATTHIZ3_7         (0x80U << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_PATT4 register  ******************/\n#define FSMC_PATT4_ATTSET4_Pos       (0U)\n#define FSMC_PATT4_ATTSET4_Msk       (0xFFU << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x000000FF */\n#define FSMC_PATT4_ATTSET4           FSMC_PATT4_ATTSET4_Msk                    /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */\n#define FSMC_PATT4_ATTSET4_0         (0x01U << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000001 */\n#define FSMC_PATT4_ATTSET4_1         (0x02U << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000002 */\n#define FSMC_PATT4_ATTSET4_2         (0x04U << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000004 */\n#define FSMC_PATT4_ATTSET4_3         (0x08U << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000008 */\n#define FSMC_PATT4_ATTSET4_4         (0x10U << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000010 */\n#define FSMC_PATT4_ATTSET4_5         (0x20U << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000020 */\n#define FSMC_PATT4_ATTSET4_6         (0x40U << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000040 */\n#define FSMC_PATT4_ATTSET4_7         (0x80U << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000080 */\n\n#define FSMC_PATT4_ATTWAIT4_Pos      (8U)\n#define FSMC_PATT4_ATTWAIT4_Msk      (0xFFU << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x0000FF00 */\n#define FSMC_PATT4_ATTWAIT4          FSMC_PATT4_ATTWAIT4_Msk                   /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */\n#define FSMC_PATT4_ATTWAIT4_0        (0x01U << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000100 */\n#define FSMC_PATT4_ATTWAIT4_1        (0x02U << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000200 */\n#define FSMC_PATT4_ATTWAIT4_2        (0x04U << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000400 */\n#define FSMC_PATT4_ATTWAIT4_3        (0x08U << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000800 */\n#define FSMC_PATT4_ATTWAIT4_4        (0x10U << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00001000 */\n#define FSMC_PATT4_ATTWAIT4_5        (0x20U << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00002000 */\n#define FSMC_PATT4_ATTWAIT4_6        (0x40U << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00004000 */\n#define FSMC_PATT4_ATTWAIT4_7        (0x80U << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00008000 */\n\n#define FSMC_PATT4_ATTHOLD4_Pos      (16U)\n#define FSMC_PATT4_ATTHOLD4_Msk      (0xFFU << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00FF0000 */\n#define FSMC_PATT4_ATTHOLD4          FSMC_PATT4_ATTHOLD4_Msk                   /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */\n#define FSMC_PATT4_ATTHOLD4_0        (0x01U << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00010000 */\n#define FSMC_PATT4_ATTHOLD4_1        (0x02U << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00020000 */\n#define FSMC_PATT4_ATTHOLD4_2        (0x04U << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00040000 */\n#define FSMC_PATT4_ATTHOLD4_3        (0x08U << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00080000 */\n#define FSMC_PATT4_ATTHOLD4_4        (0x10U << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00100000 */\n#define FSMC_PATT4_ATTHOLD4_5        (0x20U << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00200000 */\n#define FSMC_PATT4_ATTHOLD4_6        (0x40U << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00400000 */\n#define FSMC_PATT4_ATTHOLD4_7        (0x80U << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00800000 */\n\n#define FSMC_PATT4_ATTHIZ4_Pos       (24U)\n#define FSMC_PATT4_ATTHIZ4_Msk       (0xFFU << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0xFF000000 */\n#define FSMC_PATT4_ATTHIZ4           FSMC_PATT4_ATTHIZ4_Msk                    /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */\n#define FSMC_PATT4_ATTHIZ4_0         (0x01U << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x01000000 */\n#define FSMC_PATT4_ATTHIZ4_1         (0x02U << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x02000000 */\n#define FSMC_PATT4_ATTHIZ4_2         (0x04U << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x04000000 */\n#define FSMC_PATT4_ATTHIZ4_3         (0x08U << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x08000000 */\n#define FSMC_PATT4_ATTHIZ4_4         (0x10U << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x10000000 */\n#define FSMC_PATT4_ATTHIZ4_5         (0x20U << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x20000000 */\n#define FSMC_PATT4_ATTHIZ4_6         (0x40U << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x40000000 */\n#define FSMC_PATT4_ATTHIZ4_7         (0x80U << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_PIO4 register  *******************/\n#define FSMC_PIO4_IOSET4_Pos         (0U)\n#define FSMC_PIO4_IOSET4_Msk         (0xFFU << FSMC_PIO4_IOSET4_Pos)           /*!< 0x000000FF */\n#define FSMC_PIO4_IOSET4             FSMC_PIO4_IOSET4_Msk                      /*!<IOSET4[7:0] bits (I/O 4 setup time) */\n#define FSMC_PIO4_IOSET4_0           (0x01U << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000001 */\n#define FSMC_PIO4_IOSET4_1           (0x02U << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000002 */\n#define FSMC_PIO4_IOSET4_2           (0x04U << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000004 */\n#define FSMC_PIO4_IOSET4_3           (0x08U << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000008 */\n#define FSMC_PIO4_IOSET4_4           (0x10U << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000010 */\n#define FSMC_PIO4_IOSET4_5           (0x20U << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000020 */\n#define FSMC_PIO4_IOSET4_6           (0x40U << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000040 */\n#define FSMC_PIO4_IOSET4_7           (0x80U << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000080 */\n\n#define FSMC_PIO4_IOWAIT4_Pos        (8U)\n#define FSMC_PIO4_IOWAIT4_Msk        (0xFFU << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x0000FF00 */\n#define FSMC_PIO4_IOWAIT4            FSMC_PIO4_IOWAIT4_Msk                     /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */\n#define FSMC_PIO4_IOWAIT4_0          (0x01U << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000100 */\n#define FSMC_PIO4_IOWAIT4_1          (0x02U << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000200 */\n#define FSMC_PIO4_IOWAIT4_2          (0x04U << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000400 */\n#define FSMC_PIO4_IOWAIT4_3          (0x08U << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000800 */\n#define FSMC_PIO4_IOWAIT4_4          (0x10U << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00001000 */\n#define FSMC_PIO4_IOWAIT4_5          (0x20U << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00002000 */\n#define FSMC_PIO4_IOWAIT4_6          (0x40U << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00004000 */\n#define FSMC_PIO4_IOWAIT4_7          (0x80U << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00008000 */\n\n#define FSMC_PIO4_IOHOLD4_Pos        (16U)\n#define FSMC_PIO4_IOHOLD4_Msk        (0xFFU << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00FF0000 */\n#define FSMC_PIO4_IOHOLD4            FSMC_PIO4_IOHOLD4_Msk                     /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */\n#define FSMC_PIO4_IOHOLD4_0          (0x01U << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00010000 */\n#define FSMC_PIO4_IOHOLD4_1          (0x02U << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00020000 */\n#define FSMC_PIO4_IOHOLD4_2          (0x04U << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00040000 */\n#define FSMC_PIO4_IOHOLD4_3          (0x08U << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00080000 */\n#define FSMC_PIO4_IOHOLD4_4          (0x10U << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00100000 */\n#define FSMC_PIO4_IOHOLD4_5          (0x20U << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00200000 */\n#define FSMC_PIO4_IOHOLD4_6          (0x40U << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00400000 */\n#define FSMC_PIO4_IOHOLD4_7          (0x80U << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00800000 */\n\n#define FSMC_PIO4_IOHIZ4_Pos         (24U)\n#define FSMC_PIO4_IOHIZ4_Msk         (0xFFU << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0xFF000000 */\n#define FSMC_PIO4_IOHIZ4             FSMC_PIO4_IOHIZ4_Msk                      /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */\n#define FSMC_PIO4_IOHIZ4_0           (0x01U << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x01000000 */\n#define FSMC_PIO4_IOHIZ4_1           (0x02U << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x02000000 */\n#define FSMC_PIO4_IOHIZ4_2           (0x04U << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x04000000 */\n#define FSMC_PIO4_IOHIZ4_3           (0x08U << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x08000000 */\n#define FSMC_PIO4_IOHIZ4_4           (0x10U << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x10000000 */\n#define FSMC_PIO4_IOHIZ4_5           (0x20U << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x20000000 */\n#define FSMC_PIO4_IOHIZ4_6           (0x40U << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x40000000 */\n#define FSMC_PIO4_IOHIZ4_7           (0x80U << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_ECCR2 register  ******************/\n#define FSMC_ECCR2_ECC2_Pos          (0U)\n#define FSMC_ECCR2_ECC2_Msk          (0xFFFFFFFFU << FSMC_ECCR2_ECC2_Pos)      /*!< 0xFFFFFFFF */\n#define FSMC_ECCR2_ECC2              FSMC_ECCR2_ECC2_Msk                       /*!<ECC result */\n\n/******************  Bit definition for FSMC_ECCR3 register  ******************/\n#define FSMC_ECCR3_ECC3_Pos          (0U)\n#define FSMC_ECCR3_ECC3_Msk          (0xFFFFFFFFU << FSMC_ECCR3_ECC3_Pos)      /*!< 0xFFFFFFFF */\n#define FSMC_ECCR3_ECC3              FSMC_ECCR3_ECC3_Msk                       /*!<ECC result */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            General Purpose I/O                             */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bits definition for GPIO_MODER register  *****************/\n#define GPIO_MODER_MODE0_Pos             (0U)\n#define GPIO_MODER_MODE0_Msk             (0x3U << GPIO_MODER_MODE0_Pos)        /*!< 0x00000003 */\n#define GPIO_MODER_MODE0                 GPIO_MODER_MODE0_Msk\n#define GPIO_MODER_MODE0_0               (0x1U << GPIO_MODER_MODE0_Pos)        /*!< 0x00000001 */\n#define GPIO_MODER_MODE0_1               (0x2U << GPIO_MODER_MODE0_Pos)        /*!< 0x00000002 */\n#define GPIO_MODER_MODE1_Pos             (2U)\n#define GPIO_MODER_MODE1_Msk             (0x3U << GPIO_MODER_MODE1_Pos)        /*!< 0x0000000C */\n#define GPIO_MODER_MODE1                 GPIO_MODER_MODE1_Msk\n#define GPIO_MODER_MODE1_0               (0x1U << GPIO_MODER_MODE1_Pos)        /*!< 0x00000004 */\n#define GPIO_MODER_MODE1_1               (0x2U << GPIO_MODER_MODE1_Pos)        /*!< 0x00000008 */\n#define GPIO_MODER_MODE2_Pos             (4U)\n#define GPIO_MODER_MODE2_Msk             (0x3U << GPIO_MODER_MODE2_Pos)        /*!< 0x00000030 */\n#define GPIO_MODER_MODE2                 GPIO_MODER_MODE2_Msk\n#define GPIO_MODER_MODE2_0               (0x1U << GPIO_MODER_MODE2_Pos)        /*!< 0x00000010 */\n#define GPIO_MODER_MODE2_1               (0x2U << GPIO_MODER_MODE2_Pos)        /*!< 0x00000020 */\n#define GPIO_MODER_MODE3_Pos             (6U)\n#define GPIO_MODER_MODE3_Msk             (0x3U << GPIO_MODER_MODE3_Pos)        /*!< 0x000000C0 */\n#define GPIO_MODER_MODE3                 GPIO_MODER_MODE3_Msk\n#define GPIO_MODER_MODE3_0               (0x1U << GPIO_MODER_MODE3_Pos)        /*!< 0x00000040 */\n#define GPIO_MODER_MODE3_1               (0x2U << GPIO_MODER_MODE3_Pos)        /*!< 0x00000080 */\n#define GPIO_MODER_MODE4_Pos             (8U)\n#define GPIO_MODER_MODE4_Msk             (0x3U << GPIO_MODER_MODE4_Pos)        /*!< 0x00000300 */\n#define GPIO_MODER_MODE4                 GPIO_MODER_MODE4_Msk\n#define GPIO_MODER_MODE4_0               (0x1U << GPIO_MODER_MODE4_Pos)        /*!< 0x00000100 */\n#define GPIO_MODER_MODE4_1               (0x2U << GPIO_MODER_MODE4_Pos)        /*!< 0x00000200 */\n#define GPIO_MODER_MODE5_Pos             (10U)\n#define GPIO_MODER_MODE5_Msk             (0x3U << GPIO_MODER_MODE5_Pos)        /*!< 0x00000C00 */\n#define GPIO_MODER_MODE5                 GPIO_MODER_MODE5_Msk\n#define GPIO_MODER_MODE5_0               (0x1U << GPIO_MODER_MODE5_Pos)        /*!< 0x00000400 */\n#define GPIO_MODER_MODE5_1               (0x2U << GPIO_MODER_MODE5_Pos)        /*!< 0x00000800 */\n#define GPIO_MODER_MODE6_Pos             (12U)\n#define GPIO_MODER_MODE6_Msk             (0x3U << GPIO_MODER_MODE6_Pos)        /*!< 0x00003000 */\n#define GPIO_MODER_MODE6                 GPIO_MODER_MODE6_Msk\n#define GPIO_MODER_MODE6_0               (0x1U << GPIO_MODER_MODE6_Pos)        /*!< 0x00001000 */\n#define GPIO_MODER_MODE6_1               (0x2U << GPIO_MODER_MODE6_Pos)        /*!< 0x00002000 */\n#define GPIO_MODER_MODE7_Pos             (14U)\n#define GPIO_MODER_MODE7_Msk             (0x3U << GPIO_MODER_MODE7_Pos)        /*!< 0x0000C000 */\n#define GPIO_MODER_MODE7                 GPIO_MODER_MODE7_Msk\n#define GPIO_MODER_MODE7_0               (0x1U << GPIO_MODER_MODE7_Pos)        /*!< 0x00004000 */\n#define GPIO_MODER_MODE7_1               (0x2U << GPIO_MODER_MODE7_Pos)        /*!< 0x00008000 */\n#define GPIO_MODER_MODE8_Pos             (16U)\n#define GPIO_MODER_MODE8_Msk             (0x3U << GPIO_MODER_MODE8_Pos)        /*!< 0x00030000 */\n#define GPIO_MODER_MODE8                 GPIO_MODER_MODE8_Msk\n#define GPIO_MODER_MODE8_0               (0x1U << GPIO_MODER_MODE8_Pos)        /*!< 0x00010000 */\n#define GPIO_MODER_MODE8_1               (0x2U << GPIO_MODER_MODE8_Pos)        /*!< 0x00020000 */\n#define GPIO_MODER_MODE9_Pos             (18U)\n#define GPIO_MODER_MODE9_Msk             (0x3U << GPIO_MODER_MODE9_Pos)        /*!< 0x000C0000 */\n#define GPIO_MODER_MODE9                 GPIO_MODER_MODE9_Msk\n#define GPIO_MODER_MODE9_0               (0x1U << GPIO_MODER_MODE9_Pos)        /*!< 0x00040000 */\n#define GPIO_MODER_MODE9_1               (0x2U << GPIO_MODER_MODE9_Pos)        /*!< 0x00080000 */\n#define GPIO_MODER_MODE10_Pos            (20U)\n#define GPIO_MODER_MODE10_Msk            (0x3U << GPIO_MODER_MODE10_Pos)       /*!< 0x00300000 */\n#define GPIO_MODER_MODE10                GPIO_MODER_MODE10_Msk\n#define GPIO_MODER_MODE10_0              (0x1U << GPIO_MODER_MODE10_Pos)       /*!< 0x00100000 */\n#define GPIO_MODER_MODE10_1              (0x2U << GPIO_MODER_MODE10_Pos)       /*!< 0x00200000 */\n#define GPIO_MODER_MODE11_Pos            (22U)\n#define GPIO_MODER_MODE11_Msk            (0x3U << GPIO_MODER_MODE11_Pos)       /*!< 0x00C00000 */\n#define GPIO_MODER_MODE11                GPIO_MODER_MODE11_Msk\n#define GPIO_MODER_MODE11_0              (0x1U << GPIO_MODER_MODE11_Pos)       /*!< 0x00400000 */\n#define GPIO_MODER_MODE11_1              (0x2U << GPIO_MODER_MODE11_Pos)       /*!< 0x00800000 */\n#define GPIO_MODER_MODE12_Pos            (24U)\n#define GPIO_MODER_MODE12_Msk            (0x3U << GPIO_MODER_MODE12_Pos)       /*!< 0x03000000 */\n#define GPIO_MODER_MODE12                GPIO_MODER_MODE12_Msk\n#define GPIO_MODER_MODE12_0              (0x1U << GPIO_MODER_MODE12_Pos)       /*!< 0x01000000 */\n#define GPIO_MODER_MODE12_1              (0x2U << GPIO_MODER_MODE12_Pos)       /*!< 0x02000000 */\n#define GPIO_MODER_MODE13_Pos            (26U)\n#define GPIO_MODER_MODE13_Msk            (0x3U << GPIO_MODER_MODE13_Pos)       /*!< 0x0C000000 */\n#define GPIO_MODER_MODE13                GPIO_MODER_MODE13_Msk\n#define GPIO_MODER_MODE13_0              (0x1U << GPIO_MODER_MODE13_Pos)       /*!< 0x04000000 */\n#define GPIO_MODER_MODE13_1              (0x2U << GPIO_MODER_MODE13_Pos)       /*!< 0x08000000 */\n#define GPIO_MODER_MODE14_Pos            (28U)\n#define GPIO_MODER_MODE14_Msk            (0x3U << GPIO_MODER_MODE14_Pos)       /*!< 0x30000000 */\n#define GPIO_MODER_MODE14                GPIO_MODER_MODE14_Msk\n#define GPIO_MODER_MODE14_0              (0x1U << GPIO_MODER_MODE14_Pos)       /*!< 0x10000000 */\n#define GPIO_MODER_MODE14_1              (0x2U << GPIO_MODER_MODE14_Pos)       /*!< 0x20000000 */\n#define GPIO_MODER_MODE15_Pos            (30U)\n#define GPIO_MODER_MODE15_Msk            (0x3U << GPIO_MODER_MODE15_Pos)       /*!< 0xC0000000 */\n#define GPIO_MODER_MODE15                GPIO_MODER_MODE15_Msk\n#define GPIO_MODER_MODE15_0              (0x1U << GPIO_MODER_MODE15_Pos)       /*!< 0x40000000 */\n#define GPIO_MODER_MODE15_1              (0x2U << GPIO_MODER_MODE15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_MODER_MODER0_Pos            (0U)\n#define GPIO_MODER_MODER0_Msk            (0x3U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */\n#define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk\n#define GPIO_MODER_MODER0_0              (0x1U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */\n#define GPIO_MODER_MODER0_1              (0x2U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */\n#define GPIO_MODER_MODER1_Pos            (2U)\n#define GPIO_MODER_MODER1_Msk            (0x3U << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */\n#define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk\n#define GPIO_MODER_MODER1_0              (0x1U << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */\n#define GPIO_MODER_MODER1_1              (0x2U << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */\n#define GPIO_MODER_MODER2_Pos            (4U)\n#define GPIO_MODER_MODER2_Msk            (0x3U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */\n#define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk\n#define GPIO_MODER_MODER2_0              (0x1U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */\n#define GPIO_MODER_MODER2_1              (0x2U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */\n#define GPIO_MODER_MODER3_Pos            (6U)\n#define GPIO_MODER_MODER3_Msk            (0x3U << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */\n#define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk\n#define GPIO_MODER_MODER3_0              (0x1U << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */\n#define GPIO_MODER_MODER3_1              (0x2U << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */\n#define GPIO_MODER_MODER4_Pos            (8U)\n#define GPIO_MODER_MODER4_Msk            (0x3U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */\n#define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk\n#define GPIO_MODER_MODER4_0              (0x1U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */\n#define GPIO_MODER_MODER4_1              (0x2U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */\n#define GPIO_MODER_MODER5_Pos            (10U)\n#define GPIO_MODER_MODER5_Msk            (0x3U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */\n#define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk\n#define GPIO_MODER_MODER5_0              (0x1U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */\n#define GPIO_MODER_MODER5_1              (0x2U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */\n#define GPIO_MODER_MODER6_Pos            (12U)\n#define GPIO_MODER_MODER6_Msk            (0x3U << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */\n#define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk\n#define GPIO_MODER_MODER6_0              (0x1U << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */\n#define GPIO_MODER_MODER6_1              (0x2U << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */\n#define GPIO_MODER_MODER7_Pos            (14U)\n#define GPIO_MODER_MODER7_Msk            (0x3U << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */\n#define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk\n#define GPIO_MODER_MODER7_0              (0x1U << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */\n#define GPIO_MODER_MODER7_1              (0x2U << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */\n#define GPIO_MODER_MODER8_Pos            (16U)\n#define GPIO_MODER_MODER8_Msk            (0x3U << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */\n#define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk\n#define GPIO_MODER_MODER8_0              (0x1U << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */\n#define GPIO_MODER_MODER8_1              (0x2U << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */\n#define GPIO_MODER_MODER9_Pos            (18U)\n#define GPIO_MODER_MODER9_Msk            (0x3U << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */\n#define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk\n#define GPIO_MODER_MODER9_0              (0x1U << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */\n#define GPIO_MODER_MODER9_1              (0x2U << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */\n#define GPIO_MODER_MODER10_Pos           (20U)\n#define GPIO_MODER_MODER10_Msk           (0x3U << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */\n#define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk\n#define GPIO_MODER_MODER10_0             (0x1U << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */\n#define GPIO_MODER_MODER10_1             (0x2U << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */\n#define GPIO_MODER_MODER11_Pos           (22U)\n#define GPIO_MODER_MODER11_Msk           (0x3U << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */\n#define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk\n#define GPIO_MODER_MODER11_0             (0x1U << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */\n#define GPIO_MODER_MODER11_1             (0x2U << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */\n#define GPIO_MODER_MODER12_Pos           (24U)\n#define GPIO_MODER_MODER12_Msk           (0x3U << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */\n#define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk\n#define GPIO_MODER_MODER12_0             (0x1U << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */\n#define GPIO_MODER_MODER12_1             (0x2U << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */\n#define GPIO_MODER_MODER13_Pos           (26U)\n#define GPIO_MODER_MODER13_Msk           (0x3U << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */\n#define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk\n#define GPIO_MODER_MODER13_0             (0x1U << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */\n#define GPIO_MODER_MODER13_1             (0x2U << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */\n#define GPIO_MODER_MODER14_Pos           (28U)\n#define GPIO_MODER_MODER14_Msk           (0x3U << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */\n#define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk\n#define GPIO_MODER_MODER14_0             (0x1U << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */\n#define GPIO_MODER_MODER14_1             (0x2U << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */\n#define GPIO_MODER_MODER15_Pos           (30U)\n#define GPIO_MODER_MODER15_Msk           (0x3U << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */\n#define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk\n#define GPIO_MODER_MODER15_0             (0x1U << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */\n#define GPIO_MODER_MODER15_1             (0x2U << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */\n\n/******************  Bits definition for GPIO_OTYPER register  ****************/\n#define GPIO_OTYPER_OT0_Pos              (0U)\n#define GPIO_OTYPER_OT0_Msk              (0x1U << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */\n#define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk\n#define GPIO_OTYPER_OT1_Pos              (1U)\n#define GPIO_OTYPER_OT1_Msk              (0x1U << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */\n#define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk\n#define GPIO_OTYPER_OT2_Pos              (2U)\n#define GPIO_OTYPER_OT2_Msk              (0x1U << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */\n#define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk\n#define GPIO_OTYPER_OT3_Pos              (3U)\n#define GPIO_OTYPER_OT3_Msk              (0x1U << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */\n#define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk\n#define GPIO_OTYPER_OT4_Pos              (4U)\n#define GPIO_OTYPER_OT4_Msk              (0x1U << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */\n#define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk\n#define GPIO_OTYPER_OT5_Pos              (5U)\n#define GPIO_OTYPER_OT5_Msk              (0x1U << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */\n#define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk\n#define GPIO_OTYPER_OT6_Pos              (6U)\n#define GPIO_OTYPER_OT6_Msk              (0x1U << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */\n#define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk\n#define GPIO_OTYPER_OT7_Pos              (7U)\n#define GPIO_OTYPER_OT7_Msk              (0x1U << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */\n#define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk\n#define GPIO_OTYPER_OT8_Pos              (8U)\n#define GPIO_OTYPER_OT8_Msk              (0x1U << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */\n#define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk\n#define GPIO_OTYPER_OT9_Pos              (9U)\n#define GPIO_OTYPER_OT9_Msk              (0x1U << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */\n#define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk\n#define GPIO_OTYPER_OT10_Pos             (10U)\n#define GPIO_OTYPER_OT10_Msk             (0x1U << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */\n#define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk\n#define GPIO_OTYPER_OT11_Pos             (11U)\n#define GPIO_OTYPER_OT11_Msk             (0x1U << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */\n#define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk\n#define GPIO_OTYPER_OT12_Pos             (12U)\n#define GPIO_OTYPER_OT12_Msk             (0x1U << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */\n#define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk\n#define GPIO_OTYPER_OT13_Pos             (13U)\n#define GPIO_OTYPER_OT13_Msk             (0x1U << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */\n#define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk\n#define GPIO_OTYPER_OT14_Pos             (14U)\n#define GPIO_OTYPER_OT14_Msk             (0x1U << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */\n#define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk\n#define GPIO_OTYPER_OT15_Pos             (15U)\n#define GPIO_OTYPER_OT15_Msk             (0x1U << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */\n#define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk\n\n/* Legacy defines */\n#define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0\n#define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1\n#define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2\n#define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3\n#define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4\n#define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5\n#define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6\n#define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7\n#define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8\n#define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9\n#define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10\n#define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11\n#define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12\n#define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13\n#define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14\n#define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15\n\n/******************  Bits definition for GPIO_OSPEEDR register  ***************/\n#define GPIO_OSPEEDR_OSPEED0_Pos         (0U)\n#define GPIO_OSPEEDR_OSPEED0_Msk         (0x3U << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000003 */\n#define GPIO_OSPEEDR_OSPEED0             GPIO_OSPEEDR_OSPEED0_Msk\n#define GPIO_OSPEEDR_OSPEED0_0           (0x1U << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000001 */\n#define GPIO_OSPEEDR_OSPEED0_1           (0x2U << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000002 */\n#define GPIO_OSPEEDR_OSPEED1_Pos         (2U)\n#define GPIO_OSPEEDR_OSPEED1_Msk         (0x3U << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x0000000C */\n#define GPIO_OSPEEDR_OSPEED1             GPIO_OSPEEDR_OSPEED1_Msk\n#define GPIO_OSPEEDR_OSPEED1_0           (0x1U << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000004 */\n#define GPIO_OSPEEDR_OSPEED1_1           (0x2U << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000008 */\n#define GPIO_OSPEEDR_OSPEED2_Pos         (4U)\n#define GPIO_OSPEEDR_OSPEED2_Msk         (0x3U << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000030 */\n#define GPIO_OSPEEDR_OSPEED2             GPIO_OSPEEDR_OSPEED2_Msk\n#define GPIO_OSPEEDR_OSPEED2_0           (0x1U << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000010 */\n#define GPIO_OSPEEDR_OSPEED2_1           (0x2U << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000020 */\n#define GPIO_OSPEEDR_OSPEED3_Pos         (6U)\n#define GPIO_OSPEEDR_OSPEED3_Msk         (0x3U << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x000000C0 */\n#define GPIO_OSPEEDR_OSPEED3             GPIO_OSPEEDR_OSPEED3_Msk\n#define GPIO_OSPEEDR_OSPEED3_0           (0x1U << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000040 */\n#define GPIO_OSPEEDR_OSPEED3_1           (0x2U << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000080 */\n#define GPIO_OSPEEDR_OSPEED4_Pos         (8U)\n#define GPIO_OSPEEDR_OSPEED4_Msk         (0x3U << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000300 */\n#define GPIO_OSPEEDR_OSPEED4             GPIO_OSPEEDR_OSPEED4_Msk\n#define GPIO_OSPEEDR_OSPEED4_0           (0x1U << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000100 */\n#define GPIO_OSPEEDR_OSPEED4_1           (0x2U << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000200 */\n#define GPIO_OSPEEDR_OSPEED5_Pos         (10U)\n#define GPIO_OSPEEDR_OSPEED5_Msk         (0x3U << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000C00 */\n#define GPIO_OSPEEDR_OSPEED5             GPIO_OSPEEDR_OSPEED5_Msk\n#define GPIO_OSPEEDR_OSPEED5_0           (0x1U << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000400 */\n#define GPIO_OSPEEDR_OSPEED5_1           (0x2U << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000800 */\n#define GPIO_OSPEEDR_OSPEED6_Pos         (12U)\n#define GPIO_OSPEEDR_OSPEED6_Msk         (0x3U << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00003000 */\n#define GPIO_OSPEEDR_OSPEED6             GPIO_OSPEEDR_OSPEED6_Msk\n#define GPIO_OSPEEDR_OSPEED6_0           (0x1U << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00001000 */\n#define GPIO_OSPEEDR_OSPEED6_1           (0x2U << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00002000 */\n#define GPIO_OSPEEDR_OSPEED7_Pos         (14U)\n#define GPIO_OSPEEDR_OSPEED7_Msk         (0x3U << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x0000C000 */\n#define GPIO_OSPEEDR_OSPEED7             GPIO_OSPEEDR_OSPEED7_Msk\n#define GPIO_OSPEEDR_OSPEED7_0           (0x1U << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00004000 */\n#define GPIO_OSPEEDR_OSPEED7_1           (0x2U << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00008000 */\n#define GPIO_OSPEEDR_OSPEED8_Pos         (16U)\n#define GPIO_OSPEEDR_OSPEED8_Msk         (0x3U << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00030000 */\n#define GPIO_OSPEEDR_OSPEED8             GPIO_OSPEEDR_OSPEED8_Msk\n#define GPIO_OSPEEDR_OSPEED8_0           (0x1U << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00010000 */\n#define GPIO_OSPEEDR_OSPEED8_1           (0x2U << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00020000 */\n#define GPIO_OSPEEDR_OSPEED9_Pos         (18U)\n#define GPIO_OSPEEDR_OSPEED9_Msk         (0x3U << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x000C0000 */\n#define GPIO_OSPEEDR_OSPEED9             GPIO_OSPEEDR_OSPEED9_Msk\n#define GPIO_OSPEEDR_OSPEED9_0           (0x1U << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00040000 */\n#define GPIO_OSPEEDR_OSPEED9_1           (0x2U << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00080000 */\n#define GPIO_OSPEEDR_OSPEED10_Pos        (20U)\n#define GPIO_OSPEEDR_OSPEED10_Msk        (0x3U << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00300000 */\n#define GPIO_OSPEEDR_OSPEED10            GPIO_OSPEEDR_OSPEED10_Msk\n#define GPIO_OSPEEDR_OSPEED10_0          (0x1U << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00100000 */\n#define GPIO_OSPEEDR_OSPEED10_1          (0x2U << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00200000 */\n#define GPIO_OSPEEDR_OSPEED11_Pos        (22U)\n#define GPIO_OSPEEDR_OSPEED11_Msk        (0x3U << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00C00000 */\n#define GPIO_OSPEEDR_OSPEED11            GPIO_OSPEEDR_OSPEED11_Msk\n#define GPIO_OSPEEDR_OSPEED11_0          (0x1U << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00400000 */\n#define GPIO_OSPEEDR_OSPEED11_1          (0x2U << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00800000 */\n#define GPIO_OSPEEDR_OSPEED12_Pos        (24U)\n#define GPIO_OSPEEDR_OSPEED12_Msk        (0x3U << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x03000000 */\n#define GPIO_OSPEEDR_OSPEED12            GPIO_OSPEEDR_OSPEED12_Msk\n#define GPIO_OSPEEDR_OSPEED12_0          (0x1U << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x01000000 */\n#define GPIO_OSPEEDR_OSPEED12_1          (0x2U << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x02000000 */\n#define GPIO_OSPEEDR_OSPEED13_Pos        (26U)\n#define GPIO_OSPEEDR_OSPEED13_Msk        (0x3U << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x0C000000 */\n#define GPIO_OSPEEDR_OSPEED13            GPIO_OSPEEDR_OSPEED13_Msk\n#define GPIO_OSPEEDR_OSPEED13_0          (0x1U << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x04000000 */\n#define GPIO_OSPEEDR_OSPEED13_1          (0x2U << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x08000000 */\n#define GPIO_OSPEEDR_OSPEED14_Pos        (28U)\n#define GPIO_OSPEEDR_OSPEED14_Msk        (0x3U << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x30000000 */\n#define GPIO_OSPEEDR_OSPEED14            GPIO_OSPEEDR_OSPEED14_Msk\n#define GPIO_OSPEEDR_OSPEED14_0          (0x1U << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x10000000 */\n#define GPIO_OSPEEDR_OSPEED14_1          (0x2U << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x20000000 */\n#define GPIO_OSPEEDR_OSPEED15_Pos        (30U)\n#define GPIO_OSPEEDR_OSPEED15_Msk        (0x3U << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0xC0000000 */\n#define GPIO_OSPEEDR_OSPEED15            GPIO_OSPEEDR_OSPEED15_Msk\n#define GPIO_OSPEEDR_OSPEED15_0          (0x1U << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x40000000 */\n#define GPIO_OSPEEDR_OSPEED15_1          (0x2U << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0\n#define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0\n#define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1\n#define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1\n#define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0\n#define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1\n#define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2\n#define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0\n#define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1\n#define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3\n#define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0\n#define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1\n#define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4\n#define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0\n#define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1\n#define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5\n#define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0\n#define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1\n#define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6\n#define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0\n#define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1\n#define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7\n#define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0\n#define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1\n#define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8\n#define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0\n#define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1\n#define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9\n#define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0\n#define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1\n#define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10\n#define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0\n#define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1\n#define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11\n#define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0\n#define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1\n#define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12\n#define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0\n#define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1\n#define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13\n#define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0\n#define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1\n#define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14\n#define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0\n#define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1\n#define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15\n#define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0\n#define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1\n\n/******************  Bits definition for GPIO_PUPDR register  *****************/\n#define GPIO_PUPDR_PUPD0_Pos             (0U)\n#define GPIO_PUPDR_PUPD0_Msk             (0x3U << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000003 */\n#define GPIO_PUPDR_PUPD0                 GPIO_PUPDR_PUPD0_Msk\n#define GPIO_PUPDR_PUPD0_0               (0x1U << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000001 */\n#define GPIO_PUPDR_PUPD0_1               (0x2U << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000002 */\n#define GPIO_PUPDR_PUPD1_Pos             (2U)\n#define GPIO_PUPDR_PUPD1_Msk             (0x3U << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x0000000C */\n#define GPIO_PUPDR_PUPD1                 GPIO_PUPDR_PUPD1_Msk\n#define GPIO_PUPDR_PUPD1_0               (0x1U << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000004 */\n#define GPIO_PUPDR_PUPD1_1               (0x2U << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000008 */\n#define GPIO_PUPDR_PUPD2_Pos             (4U)\n#define GPIO_PUPDR_PUPD2_Msk             (0x3U << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000030 */\n#define GPIO_PUPDR_PUPD2                 GPIO_PUPDR_PUPD2_Msk\n#define GPIO_PUPDR_PUPD2_0               (0x1U << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000010 */\n#define GPIO_PUPDR_PUPD2_1               (0x2U << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000020 */\n#define GPIO_PUPDR_PUPD3_Pos             (6U)\n#define GPIO_PUPDR_PUPD3_Msk             (0x3U << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x000000C0 */\n#define GPIO_PUPDR_PUPD3                 GPIO_PUPDR_PUPD3_Msk\n#define GPIO_PUPDR_PUPD3_0               (0x1U << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000040 */\n#define GPIO_PUPDR_PUPD3_1               (0x2U << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000080 */\n#define GPIO_PUPDR_PUPD4_Pos             (8U)\n#define GPIO_PUPDR_PUPD4_Msk             (0x3U << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000300 */\n#define GPIO_PUPDR_PUPD4                 GPIO_PUPDR_PUPD4_Msk\n#define GPIO_PUPDR_PUPD4_0               (0x1U << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000100 */\n#define GPIO_PUPDR_PUPD4_1               (0x2U << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000200 */\n#define GPIO_PUPDR_PUPD5_Pos             (10U)\n#define GPIO_PUPDR_PUPD5_Msk             (0x3U << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000C00 */\n#define GPIO_PUPDR_PUPD5                 GPIO_PUPDR_PUPD5_Msk\n#define GPIO_PUPDR_PUPD5_0               (0x1U << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000400 */\n#define GPIO_PUPDR_PUPD5_1               (0x2U << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000800 */\n#define GPIO_PUPDR_PUPD6_Pos             (12U)\n#define GPIO_PUPDR_PUPD6_Msk             (0x3U << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00003000 */\n#define GPIO_PUPDR_PUPD6                 GPIO_PUPDR_PUPD6_Msk\n#define GPIO_PUPDR_PUPD6_0               (0x1U << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00001000 */\n#define GPIO_PUPDR_PUPD6_1               (0x2U << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00002000 */\n#define GPIO_PUPDR_PUPD7_Pos             (14U)\n#define GPIO_PUPDR_PUPD7_Msk             (0x3U << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x0000C000 */\n#define GPIO_PUPDR_PUPD7                 GPIO_PUPDR_PUPD7_Msk\n#define GPIO_PUPDR_PUPD7_0               (0x1U << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00004000 */\n#define GPIO_PUPDR_PUPD7_1               (0x2U << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00008000 */\n#define GPIO_PUPDR_PUPD8_Pos             (16U)\n#define GPIO_PUPDR_PUPD8_Msk             (0x3U << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00030000 */\n#define GPIO_PUPDR_PUPD8                 GPIO_PUPDR_PUPD8_Msk\n#define GPIO_PUPDR_PUPD8_0               (0x1U << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00010000 */\n#define GPIO_PUPDR_PUPD8_1               (0x2U << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00020000 */\n#define GPIO_PUPDR_PUPD9_Pos             (18U)\n#define GPIO_PUPDR_PUPD9_Msk             (0x3U << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x000C0000 */\n#define GPIO_PUPDR_PUPD9                 GPIO_PUPDR_PUPD9_Msk\n#define GPIO_PUPDR_PUPD9_0               (0x1U << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00040000 */\n#define GPIO_PUPDR_PUPD9_1               (0x2U << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00080000 */\n#define GPIO_PUPDR_PUPD10_Pos            (20U)\n#define GPIO_PUPDR_PUPD10_Msk            (0x3U << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00300000 */\n#define GPIO_PUPDR_PUPD10                GPIO_PUPDR_PUPD10_Msk\n#define GPIO_PUPDR_PUPD10_0              (0x1U << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00100000 */\n#define GPIO_PUPDR_PUPD10_1              (0x2U << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00200000 */\n#define GPIO_PUPDR_PUPD11_Pos            (22U)\n#define GPIO_PUPDR_PUPD11_Msk            (0x3U << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00C00000 */\n#define GPIO_PUPDR_PUPD11                GPIO_PUPDR_PUPD11_Msk\n#define GPIO_PUPDR_PUPD11_0              (0x1U << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00400000 */\n#define GPIO_PUPDR_PUPD11_1              (0x2U << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00800000 */\n#define GPIO_PUPDR_PUPD12_Pos            (24U)\n#define GPIO_PUPDR_PUPD12_Msk            (0x3U << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x03000000 */\n#define GPIO_PUPDR_PUPD12                GPIO_PUPDR_PUPD12_Msk\n#define GPIO_PUPDR_PUPD12_0              (0x1U << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x01000000 */\n#define GPIO_PUPDR_PUPD12_1              (0x2U << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x02000000 */\n#define GPIO_PUPDR_PUPD13_Pos            (26U)\n#define GPIO_PUPDR_PUPD13_Msk            (0x3U << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x0C000000 */\n#define GPIO_PUPDR_PUPD13                GPIO_PUPDR_PUPD13_Msk\n#define GPIO_PUPDR_PUPD13_0              (0x1U << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x04000000 */\n#define GPIO_PUPDR_PUPD13_1              (0x2U << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x08000000 */\n#define GPIO_PUPDR_PUPD14_Pos            (28U)\n#define GPIO_PUPDR_PUPD14_Msk            (0x3U << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x30000000 */\n#define GPIO_PUPDR_PUPD14                GPIO_PUPDR_PUPD14_Msk\n#define GPIO_PUPDR_PUPD14_0              (0x1U << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x10000000 */\n#define GPIO_PUPDR_PUPD14_1              (0x2U << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x20000000 */\n#define GPIO_PUPDR_PUPD15_Pos            (30U)\n#define GPIO_PUPDR_PUPD15_Msk            (0x3U << GPIO_PUPDR_PUPD15_Pos)       /*!< 0xC0000000 */\n#define GPIO_PUPDR_PUPD15                GPIO_PUPDR_PUPD15_Msk\n#define GPIO_PUPDR_PUPD15_0              (0x1U << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x40000000 */\n#define GPIO_PUPDR_PUPD15_1              (0x2U << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0\n#define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0\n#define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1\n#define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1\n#define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0\n#define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1\n#define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2\n#define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0\n#define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1\n#define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3\n#define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0\n#define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1\n#define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4\n#define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0\n#define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1\n#define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5\n#define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0\n#define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1\n#define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6\n#define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0\n#define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1\n#define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7\n#define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0\n#define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1\n#define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8\n#define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0\n#define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1\n#define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9\n#define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0\n#define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1\n#define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10\n#define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0\n#define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1\n#define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11\n#define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0\n#define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1\n#define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12\n#define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0\n#define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1\n#define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13\n#define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0\n#define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1\n#define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14\n#define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0\n#define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1\n#define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15\n#define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0\n#define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1\n\n/******************  Bits definition for GPIO_IDR register  *******************/\n#define GPIO_IDR_ID0_Pos                 (0U)\n#define GPIO_IDR_ID0_Msk                 (0x1U << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */\n#define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk\n#define GPIO_IDR_ID1_Pos                 (1U)\n#define GPIO_IDR_ID1_Msk                 (0x1U << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */\n#define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk\n#define GPIO_IDR_ID2_Pos                 (2U)\n#define GPIO_IDR_ID2_Msk                 (0x1U << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */\n#define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk\n#define GPIO_IDR_ID3_Pos                 (3U)\n#define GPIO_IDR_ID3_Msk                 (0x1U << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */\n#define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk\n#define GPIO_IDR_ID4_Pos                 (4U)\n#define GPIO_IDR_ID4_Msk                 (0x1U << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */\n#define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk\n#define GPIO_IDR_ID5_Pos                 (5U)\n#define GPIO_IDR_ID5_Msk                 (0x1U << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */\n#define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk\n#define GPIO_IDR_ID6_Pos                 (6U)\n#define GPIO_IDR_ID6_Msk                 (0x1U << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */\n#define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk\n#define GPIO_IDR_ID7_Pos                 (7U)\n#define GPIO_IDR_ID7_Msk                 (0x1U << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */\n#define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk\n#define GPIO_IDR_ID8_Pos                 (8U)\n#define GPIO_IDR_ID8_Msk                 (0x1U << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */\n#define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk\n#define GPIO_IDR_ID9_Pos                 (9U)\n#define GPIO_IDR_ID9_Msk                 (0x1U << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */\n#define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk\n#define GPIO_IDR_ID10_Pos                (10U)\n#define GPIO_IDR_ID10_Msk                (0x1U << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */\n#define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk\n#define GPIO_IDR_ID11_Pos                (11U)\n#define GPIO_IDR_ID11_Msk                (0x1U << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */\n#define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk\n#define GPIO_IDR_ID12_Pos                (12U)\n#define GPIO_IDR_ID12_Msk                (0x1U << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */\n#define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk\n#define GPIO_IDR_ID13_Pos                (13U)\n#define GPIO_IDR_ID13_Msk                (0x1U << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */\n#define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk\n#define GPIO_IDR_ID14_Pos                (14U)\n#define GPIO_IDR_ID14_Msk                (0x1U << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */\n#define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk\n#define GPIO_IDR_ID15_Pos                (15U)\n#define GPIO_IDR_ID15_Msk                (0x1U << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */\n#define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk\n\n/* Legacy defines */\n#define GPIO_IDR_IDR_0                      GPIO_IDR_ID0\n#define GPIO_IDR_IDR_1                      GPIO_IDR_ID1\n#define GPIO_IDR_IDR_2                      GPIO_IDR_ID2\n#define GPIO_IDR_IDR_3                      GPIO_IDR_ID3\n#define GPIO_IDR_IDR_4                      GPIO_IDR_ID4\n#define GPIO_IDR_IDR_5                      GPIO_IDR_ID5\n#define GPIO_IDR_IDR_6                      GPIO_IDR_ID6\n#define GPIO_IDR_IDR_7                      GPIO_IDR_ID7\n#define GPIO_IDR_IDR_8                      GPIO_IDR_ID8\n#define GPIO_IDR_IDR_9                      GPIO_IDR_ID9\n#define GPIO_IDR_IDR_10                     GPIO_IDR_ID10\n#define GPIO_IDR_IDR_11                     GPIO_IDR_ID11\n#define GPIO_IDR_IDR_12                     GPIO_IDR_ID12\n#define GPIO_IDR_IDR_13                     GPIO_IDR_ID13\n#define GPIO_IDR_IDR_14                     GPIO_IDR_ID14\n#define GPIO_IDR_IDR_15                     GPIO_IDR_ID15\n\n/******************  Bits definition for GPIO_ODR register  *******************/\n#define GPIO_ODR_OD0_Pos                 (0U)\n#define GPIO_ODR_OD0_Msk                 (0x1U << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */\n#define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk\n#define GPIO_ODR_OD1_Pos                 (1U)\n#define GPIO_ODR_OD1_Msk                 (0x1U << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */\n#define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk\n#define GPIO_ODR_OD2_Pos                 (2U)\n#define GPIO_ODR_OD2_Msk                 (0x1U << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */\n#define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk\n#define GPIO_ODR_OD3_Pos                 (3U)\n#define GPIO_ODR_OD3_Msk                 (0x1U << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */\n#define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk\n#define GPIO_ODR_OD4_Pos                 (4U)\n#define GPIO_ODR_OD4_Msk                 (0x1U << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */\n#define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk\n#define GPIO_ODR_OD5_Pos                 (5U)\n#define GPIO_ODR_OD5_Msk                 (0x1U << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */\n#define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk\n#define GPIO_ODR_OD6_Pos                 (6U)\n#define GPIO_ODR_OD6_Msk                 (0x1U << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */\n#define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk\n#define GPIO_ODR_OD7_Pos                 (7U)\n#define GPIO_ODR_OD7_Msk                 (0x1U << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */\n#define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk\n#define GPIO_ODR_OD8_Pos                 (8U)\n#define GPIO_ODR_OD8_Msk                 (0x1U << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */\n#define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk\n#define GPIO_ODR_OD9_Pos                 (9U)\n#define GPIO_ODR_OD9_Msk                 (0x1U << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */\n#define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk\n#define GPIO_ODR_OD10_Pos                (10U)\n#define GPIO_ODR_OD10_Msk                (0x1U << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */\n#define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk\n#define GPIO_ODR_OD11_Pos                (11U)\n#define GPIO_ODR_OD11_Msk                (0x1U << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */\n#define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk\n#define GPIO_ODR_OD12_Pos                (12U)\n#define GPIO_ODR_OD12_Msk                (0x1U << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */\n#define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk\n#define GPIO_ODR_OD13_Pos                (13U)\n#define GPIO_ODR_OD13_Msk                (0x1U << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */\n#define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk\n#define GPIO_ODR_OD14_Pos                (14U)\n#define GPIO_ODR_OD14_Msk                (0x1U << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */\n#define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk\n#define GPIO_ODR_OD15_Pos                (15U)\n#define GPIO_ODR_OD15_Msk                (0x1U << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */\n#define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk\n/* Legacy defines */\n#define GPIO_ODR_ODR_0                       GPIO_ODR_OD0\n#define GPIO_ODR_ODR_1                       GPIO_ODR_OD1\n#define GPIO_ODR_ODR_2                       GPIO_ODR_OD2\n#define GPIO_ODR_ODR_3                       GPIO_ODR_OD3\n#define GPIO_ODR_ODR_4                       GPIO_ODR_OD4\n#define GPIO_ODR_ODR_5                       GPIO_ODR_OD5\n#define GPIO_ODR_ODR_6                       GPIO_ODR_OD6\n#define GPIO_ODR_ODR_7                       GPIO_ODR_OD7\n#define GPIO_ODR_ODR_8                       GPIO_ODR_OD8\n#define GPIO_ODR_ODR_9                       GPIO_ODR_OD9\n#define GPIO_ODR_ODR_10                      GPIO_ODR_OD10\n#define GPIO_ODR_ODR_11                      GPIO_ODR_OD11\n#define GPIO_ODR_ODR_12                      GPIO_ODR_OD12\n#define GPIO_ODR_ODR_13                      GPIO_ODR_OD13\n#define GPIO_ODR_ODR_14                      GPIO_ODR_OD14\n#define GPIO_ODR_ODR_15                      GPIO_ODR_OD15\n\n/******************  Bits definition for GPIO_BSRR register  ******************/\n#define GPIO_BSRR_BS0_Pos                (0U)\n#define GPIO_BSRR_BS0_Msk                (0x1U << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */\n#define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk\n#define GPIO_BSRR_BS1_Pos                (1U)\n#define GPIO_BSRR_BS1_Msk                (0x1U << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */\n#define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk\n#define GPIO_BSRR_BS2_Pos                (2U)\n#define GPIO_BSRR_BS2_Msk                (0x1U << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */\n#define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk\n#define GPIO_BSRR_BS3_Pos                (3U)\n#define GPIO_BSRR_BS3_Msk                (0x1U << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */\n#define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk\n#define GPIO_BSRR_BS4_Pos                (4U)\n#define GPIO_BSRR_BS4_Msk                (0x1U << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */\n#define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk\n#define GPIO_BSRR_BS5_Pos                (5U)\n#define GPIO_BSRR_BS5_Msk                (0x1U << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */\n#define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk\n#define GPIO_BSRR_BS6_Pos                (6U)\n#define GPIO_BSRR_BS6_Msk                (0x1U << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */\n#define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk\n#define GPIO_BSRR_BS7_Pos                (7U)\n#define GPIO_BSRR_BS7_Msk                (0x1U << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */\n#define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk\n#define GPIO_BSRR_BS8_Pos                (8U)\n#define GPIO_BSRR_BS8_Msk                (0x1U << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */\n#define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk\n#define GPIO_BSRR_BS9_Pos                (9U)\n#define GPIO_BSRR_BS9_Msk                (0x1U << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */\n#define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk\n#define GPIO_BSRR_BS10_Pos               (10U)\n#define GPIO_BSRR_BS10_Msk               (0x1U << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */\n#define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk\n#define GPIO_BSRR_BS11_Pos               (11U)\n#define GPIO_BSRR_BS11_Msk               (0x1U << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */\n#define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk\n#define GPIO_BSRR_BS12_Pos               (12U)\n#define GPIO_BSRR_BS12_Msk               (0x1U << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */\n#define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk\n#define GPIO_BSRR_BS13_Pos               (13U)\n#define GPIO_BSRR_BS13_Msk               (0x1U << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */\n#define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk\n#define GPIO_BSRR_BS14_Pos               (14U)\n#define GPIO_BSRR_BS14_Msk               (0x1U << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */\n#define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk\n#define GPIO_BSRR_BS15_Pos               (15U)\n#define GPIO_BSRR_BS15_Msk               (0x1U << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */\n#define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk\n#define GPIO_BSRR_BR0_Pos                (16U)\n#define GPIO_BSRR_BR0_Msk                (0x1U << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */\n#define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk\n#define GPIO_BSRR_BR1_Pos                (17U)\n#define GPIO_BSRR_BR1_Msk                (0x1U << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */\n#define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk\n#define GPIO_BSRR_BR2_Pos                (18U)\n#define GPIO_BSRR_BR2_Msk                (0x1U << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */\n#define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk\n#define GPIO_BSRR_BR3_Pos                (19U)\n#define GPIO_BSRR_BR3_Msk                (0x1U << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */\n#define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk\n#define GPIO_BSRR_BR4_Pos                (20U)\n#define GPIO_BSRR_BR4_Msk                (0x1U << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */\n#define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk\n#define GPIO_BSRR_BR5_Pos                (21U)\n#define GPIO_BSRR_BR5_Msk                (0x1U << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */\n#define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk\n#define GPIO_BSRR_BR6_Pos                (22U)\n#define GPIO_BSRR_BR6_Msk                (0x1U << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */\n#define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk\n#define GPIO_BSRR_BR7_Pos                (23U)\n#define GPIO_BSRR_BR7_Msk                (0x1U << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */\n#define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk\n#define GPIO_BSRR_BR8_Pos                (24U)\n#define GPIO_BSRR_BR8_Msk                (0x1U << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */\n#define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk\n#define GPIO_BSRR_BR9_Pos                (25U)\n#define GPIO_BSRR_BR9_Msk                (0x1U << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */\n#define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk\n#define GPIO_BSRR_BR10_Pos               (26U)\n#define GPIO_BSRR_BR10_Msk               (0x1U << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */\n#define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk\n#define GPIO_BSRR_BR11_Pos               (27U)\n#define GPIO_BSRR_BR11_Msk               (0x1U << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */\n#define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk\n#define GPIO_BSRR_BR12_Pos               (28U)\n#define GPIO_BSRR_BR12_Msk               (0x1U << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */\n#define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk\n#define GPIO_BSRR_BR13_Pos               (29U)\n#define GPIO_BSRR_BR13_Msk               (0x1U << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */\n#define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk\n#define GPIO_BSRR_BR14_Pos               (30U)\n#define GPIO_BSRR_BR14_Msk               (0x1U << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */\n#define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk\n#define GPIO_BSRR_BR15_Pos               (31U)\n#define GPIO_BSRR_BR15_Msk               (0x1U << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */\n#define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk\n\n/* Legacy defines */\n#define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0\n#define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1\n#define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2\n#define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3\n#define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4\n#define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5\n#define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6\n#define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7\n#define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8\n#define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9\n#define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10\n#define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11\n#define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12\n#define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13\n#define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14\n#define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15\n#define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0\n#define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1\n#define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2\n#define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3\n#define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4\n#define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5\n#define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6\n#define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7\n#define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8\n#define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9\n#define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10\n#define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11\n#define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12\n#define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13\n#define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14\n#define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15\n/****************** Bit definition for GPIO_LCKR register *********************/\n#define GPIO_LCKR_LCK0_Pos               (0U)\n#define GPIO_LCKR_LCK0_Msk               (0x1U << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */\n#define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk\n#define GPIO_LCKR_LCK1_Pos               (1U)\n#define GPIO_LCKR_LCK1_Msk               (0x1U << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */\n#define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk\n#define GPIO_LCKR_LCK2_Pos               (2U)\n#define GPIO_LCKR_LCK2_Msk               (0x1U << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */\n#define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk\n#define GPIO_LCKR_LCK3_Pos               (3U)\n#define GPIO_LCKR_LCK3_Msk               (0x1U << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */\n#define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk\n#define GPIO_LCKR_LCK4_Pos               (4U)\n#define GPIO_LCKR_LCK4_Msk               (0x1U << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */\n#define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk\n#define GPIO_LCKR_LCK5_Pos               (5U)\n#define GPIO_LCKR_LCK5_Msk               (0x1U << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */\n#define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk\n#define GPIO_LCKR_LCK6_Pos               (6U)\n#define GPIO_LCKR_LCK6_Msk               (0x1U << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */\n#define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk\n#define GPIO_LCKR_LCK7_Pos               (7U)\n#define GPIO_LCKR_LCK7_Msk               (0x1U << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */\n#define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk\n#define GPIO_LCKR_LCK8_Pos               (8U)\n#define GPIO_LCKR_LCK8_Msk               (0x1U << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */\n#define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk\n#define GPIO_LCKR_LCK9_Pos               (9U)\n#define GPIO_LCKR_LCK9_Msk               (0x1U << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */\n#define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk\n#define GPIO_LCKR_LCK10_Pos              (10U)\n#define GPIO_LCKR_LCK10_Msk              (0x1U << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */\n#define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk\n#define GPIO_LCKR_LCK11_Pos              (11U)\n#define GPIO_LCKR_LCK11_Msk              (0x1U << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */\n#define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk\n#define GPIO_LCKR_LCK12_Pos              (12U)\n#define GPIO_LCKR_LCK12_Msk              (0x1U << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */\n#define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk\n#define GPIO_LCKR_LCK13_Pos              (13U)\n#define GPIO_LCKR_LCK13_Msk              (0x1U << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */\n#define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk\n#define GPIO_LCKR_LCK14_Pos              (14U)\n#define GPIO_LCKR_LCK14_Msk              (0x1U << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */\n#define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk\n#define GPIO_LCKR_LCK15_Pos              (15U)\n#define GPIO_LCKR_LCK15_Msk              (0x1U << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */\n#define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk\n#define GPIO_LCKR_LCKK_Pos               (16U)\n#define GPIO_LCKR_LCKK_Msk               (0x1U << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */\n#define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk\n/****************** Bit definition for GPIO_AFRL register *********************/\n#define GPIO_AFRL_AFSEL0_Pos             (0U)\n#define GPIO_AFRL_AFSEL0_Msk             (0xFU << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk\n#define GPIO_AFRL_AFSEL0_0               (0x1U << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRL_AFSEL0_1               (0x2U << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRL_AFSEL0_2               (0x4U << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRL_AFSEL0_3               (0x8U << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRL_AFSEL1_Pos             (4U)\n#define GPIO_AFRL_AFSEL1_Msk             (0xFU << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk\n#define GPIO_AFRL_AFSEL1_0               (0x1U << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRL_AFSEL1_1               (0x2U << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRL_AFSEL1_2               (0x4U << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRL_AFSEL1_3               (0x8U << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRL_AFSEL2_Pos             (8U)\n#define GPIO_AFRL_AFSEL2_Msk             (0xFU << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */\n#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk\n#define GPIO_AFRL_AFSEL2_0               (0x1U << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */\n#define GPIO_AFRL_AFSEL2_1               (0x2U << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */\n#define GPIO_AFRL_AFSEL2_2               (0x4U << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */\n#define GPIO_AFRL_AFSEL2_3               (0x8U << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */\n#define GPIO_AFRL_AFSEL3_Pos             (12U)\n#define GPIO_AFRL_AFSEL3_Msk             (0xFU << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */\n#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk\n#define GPIO_AFRL_AFSEL3_0               (0x1U << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */\n#define GPIO_AFRL_AFSEL3_1               (0x2U << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */\n#define GPIO_AFRL_AFSEL3_2               (0x4U << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */\n#define GPIO_AFRL_AFSEL3_3               (0x8U << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */\n#define GPIO_AFRL_AFSEL4_Pos             (16U)\n#define GPIO_AFRL_AFSEL4_Msk             (0xFU << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */\n#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk\n#define GPIO_AFRL_AFSEL4_0               (0x1U << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */\n#define GPIO_AFRL_AFSEL4_1               (0x2U << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */\n#define GPIO_AFRL_AFSEL4_2               (0x4U << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */\n#define GPIO_AFRL_AFSEL4_3               (0x8U << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */\n#define GPIO_AFRL_AFSEL5_Pos             (20U)\n#define GPIO_AFRL_AFSEL5_Msk             (0xFU << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */\n#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk\n#define GPIO_AFRL_AFSEL5_0               (0x1U << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */\n#define GPIO_AFRL_AFSEL5_1               (0x2U << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */\n#define GPIO_AFRL_AFSEL5_2               (0x4U << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */\n#define GPIO_AFRL_AFSEL5_3               (0x8U << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */\n#define GPIO_AFRL_AFSEL6_Pos             (24U)\n#define GPIO_AFRL_AFSEL6_Msk             (0xFU << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */\n#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk\n#define GPIO_AFRL_AFSEL6_0               (0x1U << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */\n#define GPIO_AFRL_AFSEL6_1               (0x2U << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */\n#define GPIO_AFRL_AFSEL6_2               (0x4U << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */\n#define GPIO_AFRL_AFSEL6_3               (0x8U << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */\n#define GPIO_AFRL_AFSEL7_Pos             (28U)\n#define GPIO_AFRL_AFSEL7_Msk             (0xFU << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */\n#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk\n#define GPIO_AFRL_AFSEL7_0               (0x1U << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */\n#define GPIO_AFRL_AFSEL7_1               (0x2U << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */\n#define GPIO_AFRL_AFSEL7_2               (0x4U << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */\n#define GPIO_AFRL_AFSEL7_3               (0x8U << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0\n#define GPIO_AFRL_AFRL0_0                    GPIO_AFRL_AFSEL0_0\n#define GPIO_AFRL_AFRL0_1                    GPIO_AFRL_AFSEL0_1\n#define GPIO_AFRL_AFRL0_2                    GPIO_AFRL_AFSEL0_2\n#define GPIO_AFRL_AFRL0_3                    GPIO_AFRL_AFSEL0_3\n#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1\n#define GPIO_AFRL_AFRL1_0                    GPIO_AFRL_AFSEL1_0\n#define GPIO_AFRL_AFRL1_1                    GPIO_AFRL_AFSEL1_1\n#define GPIO_AFRL_AFRL1_2                    GPIO_AFRL_AFSEL1_2\n#define GPIO_AFRL_AFRL1_3                    GPIO_AFRL_AFSEL1_3\n#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2\n#define GPIO_AFRL_AFRL2_0                    GPIO_AFRL_AFSEL2_0\n#define GPIO_AFRL_AFRL2_1                    GPIO_AFRL_AFSEL2_1\n#define GPIO_AFRL_AFRL2_2                    GPIO_AFRL_AFSEL2_2\n#define GPIO_AFRL_AFRL2_3                    GPIO_AFRL_AFSEL2_3\n#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3\n#define GPIO_AFRL_AFRL3_0                    GPIO_AFRL_AFSEL3_0\n#define GPIO_AFRL_AFRL3_1                    GPIO_AFRL_AFSEL3_1\n#define GPIO_AFRL_AFRL3_2                    GPIO_AFRL_AFSEL3_2\n#define GPIO_AFRL_AFRL3_3                    GPIO_AFRL_AFSEL3_3\n#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4\n#define GPIO_AFRL_AFRL4_0                    GPIO_AFRL_AFSEL4_0\n#define GPIO_AFRL_AFRL4_1                    GPIO_AFRL_AFSEL4_1\n#define GPIO_AFRL_AFRL4_2                    GPIO_AFRL_AFSEL4_2\n#define GPIO_AFRL_AFRL4_3                    GPIO_AFRL_AFSEL4_3\n#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5\n#define GPIO_AFRL_AFRL5_0                    GPIO_AFRL_AFSEL5_0\n#define GPIO_AFRL_AFRL5_1                    GPIO_AFRL_AFSEL5_1\n#define GPIO_AFRL_AFRL5_2                    GPIO_AFRL_AFSEL5_2\n#define GPIO_AFRL_AFRL5_3                    GPIO_AFRL_AFSEL5_3\n#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6\n#define GPIO_AFRL_AFRL6_0                    GPIO_AFRL_AFSEL6_0\n#define GPIO_AFRL_AFRL6_1                    GPIO_AFRL_AFSEL6_1\n#define GPIO_AFRL_AFRL6_2                    GPIO_AFRL_AFSEL6_2\n#define GPIO_AFRL_AFRL6_3                    GPIO_AFRL_AFSEL6_3\n#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7\n#define GPIO_AFRL_AFRL7_0                    GPIO_AFRL_AFSEL7_0\n#define GPIO_AFRL_AFRL7_1                    GPIO_AFRL_AFSEL7_1\n#define GPIO_AFRL_AFRL7_2                    GPIO_AFRL_AFSEL7_2\n#define GPIO_AFRL_AFRL7_3                    GPIO_AFRL_AFSEL7_3\n\n/****************** Bit definition for GPIO_AFRH register *********************/\n#define GPIO_AFRH_AFSEL8_Pos             (0U)\n#define GPIO_AFRH_AFSEL8_Msk             (0xFU << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk\n#define GPIO_AFRH_AFSEL8_0               (0x1U << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRH_AFSEL8_1               (0x2U << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRH_AFSEL8_2               (0x4U << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRH_AFSEL8_3               (0x8U << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRH_AFSEL9_Pos             (4U)\n#define GPIO_AFRH_AFSEL9_Msk             (0xFU << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk\n#define GPIO_AFRH_AFSEL9_0               (0x1U << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRH_AFSEL9_1               (0x2U << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRH_AFSEL9_2               (0x4U << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRH_AFSEL9_3               (0x8U << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRH_AFSEL10_Pos            (8U)\n#define GPIO_AFRH_AFSEL10_Msk            (0xFU << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */\n#define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk\n#define GPIO_AFRH_AFSEL10_0              (0x1U << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */\n#define GPIO_AFRH_AFSEL10_1              (0x2U << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */\n#define GPIO_AFRH_AFSEL10_2              (0x4U << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */\n#define GPIO_AFRH_AFSEL10_3              (0x8U << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */\n#define GPIO_AFRH_AFSEL11_Pos            (12U)\n#define GPIO_AFRH_AFSEL11_Msk            (0xFU << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */\n#define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk\n#define GPIO_AFRH_AFSEL11_0              (0x1U << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */\n#define GPIO_AFRH_AFSEL11_1              (0x2U << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */\n#define GPIO_AFRH_AFSEL11_2              (0x4U << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */\n#define GPIO_AFRH_AFSEL11_3              (0x8U << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */\n#define GPIO_AFRH_AFSEL12_Pos            (16U)\n#define GPIO_AFRH_AFSEL12_Msk            (0xFU << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */\n#define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk\n#define GPIO_AFRH_AFSEL12_0              (0x1U << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */\n#define GPIO_AFRH_AFSEL12_1              (0x2U << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */\n#define GPIO_AFRH_AFSEL12_2              (0x4U << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */\n#define GPIO_AFRH_AFSEL12_3              (0x8U << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */\n#define GPIO_AFRH_AFSEL13_Pos            (20U)\n#define GPIO_AFRH_AFSEL13_Msk            (0xFU << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */\n#define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk\n#define GPIO_AFRH_AFSEL13_0              (0x1U << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */\n#define GPIO_AFRH_AFSEL13_1              (0x2U << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */\n#define GPIO_AFRH_AFSEL13_2              (0x4U << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */\n#define GPIO_AFRH_AFSEL13_3              (0x8U << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */\n#define GPIO_AFRH_AFSEL14_Pos            (24U)\n#define GPIO_AFRH_AFSEL14_Msk            (0xFU << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */\n#define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk\n#define GPIO_AFRH_AFSEL14_0              (0x1U << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */\n#define GPIO_AFRH_AFSEL14_1              (0x2U << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */\n#define GPIO_AFRH_AFSEL14_2              (0x4U << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */\n#define GPIO_AFRH_AFSEL14_3              (0x8U << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */\n#define GPIO_AFRH_AFSEL15_Pos            (28U)\n#define GPIO_AFRH_AFSEL15_Msk            (0xFU << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */\n#define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk\n#define GPIO_AFRH_AFSEL15_0              (0x1U << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */\n#define GPIO_AFRH_AFSEL15_1              (0x2U << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */\n#define GPIO_AFRH_AFSEL15_2              (0x4U << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */\n#define GPIO_AFRH_AFSEL15_3              (0x8U << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8\n#define GPIO_AFRH_AFRH0_0                    GPIO_AFRH_AFSEL8_0\n#define GPIO_AFRH_AFRH0_1                    GPIO_AFRH_AFSEL8_1\n#define GPIO_AFRH_AFRH0_2                    GPIO_AFRH_AFSEL8_2\n#define GPIO_AFRH_AFRH0_3                    GPIO_AFRH_AFSEL8_3\n#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9\n#define GPIO_AFRH_AFRH1_0                    GPIO_AFRH_AFSEL9_0\n#define GPIO_AFRH_AFRH1_1                    GPIO_AFRH_AFSEL9_1\n#define GPIO_AFRH_AFRH1_2                    GPIO_AFRH_AFSEL9_2\n#define GPIO_AFRH_AFRH1_3                    GPIO_AFRH_AFSEL9_3\n#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10\n#define GPIO_AFRH_AFRH2_0                    GPIO_AFRH_AFSEL10_0\n#define GPIO_AFRH_AFRH2_1                    GPIO_AFRH_AFSEL10_1\n#define GPIO_AFRH_AFRH2_2                    GPIO_AFRH_AFSEL10_2\n#define GPIO_AFRH_AFRH2_3                    GPIO_AFRH_AFSEL10_3\n#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11\n#define GPIO_AFRH_AFRH3_0                    GPIO_AFRH_AFSEL11_0\n#define GPIO_AFRH_AFRH3_1                    GPIO_AFRH_AFSEL11_1\n#define GPIO_AFRH_AFRH3_2                    GPIO_AFRH_AFSEL11_2\n#define GPIO_AFRH_AFRH3_3                    GPIO_AFRH_AFSEL11_3\n#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12\n#define GPIO_AFRH_AFRH4_0                    GPIO_AFRH_AFSEL12_0\n#define GPIO_AFRH_AFRH4_1                    GPIO_AFRH_AFSEL12_1\n#define GPIO_AFRH_AFRH4_2                    GPIO_AFRH_AFSEL12_2\n#define GPIO_AFRH_AFRH4_3                    GPIO_AFRH_AFSEL12_3\n#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13\n#define GPIO_AFRH_AFRH5_0                    GPIO_AFRH_AFSEL13_0\n#define GPIO_AFRH_AFRH5_1                    GPIO_AFRH_AFSEL13_1\n#define GPIO_AFRH_AFRH5_2                    GPIO_AFRH_AFSEL13_2\n#define GPIO_AFRH_AFRH5_3                    GPIO_AFRH_AFSEL13_3\n#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14\n#define GPIO_AFRH_AFRH6_0                    GPIO_AFRH_AFSEL14_0\n#define GPIO_AFRH_AFRH6_1                    GPIO_AFRH_AFSEL14_1\n#define GPIO_AFRH_AFRH6_2                    GPIO_AFRH_AFSEL14_2\n#define GPIO_AFRH_AFRH6_3                    GPIO_AFRH_AFSEL14_3\n#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15\n#define GPIO_AFRH_AFRH7_0                    GPIO_AFRH_AFSEL15_0\n#define GPIO_AFRH_AFRH7_1                    GPIO_AFRH_AFSEL15_1\n#define GPIO_AFRH_AFRH7_2                    GPIO_AFRH_AFSEL15_2\n#define GPIO_AFRH_AFRH7_3                    GPIO_AFRH_AFSEL15_3\n\n/******************  Bits definition for GPIO_BRR register  ******************/\n#define GPIO_BRR_BR0_Pos                 (0U)\n#define GPIO_BRR_BR0_Msk                 (0x1U << GPIO_BRR_BR0_Pos)            /*!< 0x00000001 */\n#define GPIO_BRR_BR0                     GPIO_BRR_BR0_Msk\n#define GPIO_BRR_BR1_Pos                 (1U)\n#define GPIO_BRR_BR1_Msk                 (0x1U << GPIO_BRR_BR1_Pos)            /*!< 0x00000002 */\n#define GPIO_BRR_BR1                     GPIO_BRR_BR1_Msk\n#define GPIO_BRR_BR2_Pos                 (2U)\n#define GPIO_BRR_BR2_Msk                 (0x1U << GPIO_BRR_BR2_Pos)            /*!< 0x00000004 */\n#define GPIO_BRR_BR2                     GPIO_BRR_BR2_Msk\n#define GPIO_BRR_BR3_Pos                 (3U)\n#define GPIO_BRR_BR3_Msk                 (0x1U << GPIO_BRR_BR3_Pos)            /*!< 0x00000008 */\n#define GPIO_BRR_BR3                     GPIO_BRR_BR3_Msk\n#define GPIO_BRR_BR4_Pos                 (4U)\n#define GPIO_BRR_BR4_Msk                 (0x1U << GPIO_BRR_BR4_Pos)            /*!< 0x00000010 */\n#define GPIO_BRR_BR4                     GPIO_BRR_BR4_Msk\n#define GPIO_BRR_BR5_Pos                 (5U)\n#define GPIO_BRR_BR5_Msk                 (0x1U << GPIO_BRR_BR5_Pos)            /*!< 0x00000020 */\n#define GPIO_BRR_BR5                     GPIO_BRR_BR5_Msk\n#define GPIO_BRR_BR6_Pos                 (6U)\n#define GPIO_BRR_BR6_Msk                 (0x1U << GPIO_BRR_BR6_Pos)            /*!< 0x00000040 */\n#define GPIO_BRR_BR6                     GPIO_BRR_BR6_Msk\n#define GPIO_BRR_BR7_Pos                 (7U)\n#define GPIO_BRR_BR7_Msk                 (0x1U << GPIO_BRR_BR7_Pos)            /*!< 0x00000080 */\n#define GPIO_BRR_BR7                     GPIO_BRR_BR7_Msk\n#define GPIO_BRR_BR8_Pos                 (8U)\n#define GPIO_BRR_BR8_Msk                 (0x1U << GPIO_BRR_BR8_Pos)            /*!< 0x00000100 */\n#define GPIO_BRR_BR8                     GPIO_BRR_BR8_Msk\n#define GPIO_BRR_BR9_Pos                 (9U)\n#define GPIO_BRR_BR9_Msk                 (0x1U << GPIO_BRR_BR9_Pos)            /*!< 0x00000200 */\n#define GPIO_BRR_BR9                     GPIO_BRR_BR9_Msk\n#define GPIO_BRR_BR10_Pos                (10U)\n#define GPIO_BRR_BR10_Msk                (0x1U << GPIO_BRR_BR10_Pos)           /*!< 0x00000400 */\n#define GPIO_BRR_BR10                    GPIO_BRR_BR10_Msk\n#define GPIO_BRR_BR11_Pos                (11U)\n#define GPIO_BRR_BR11_Msk                (0x1U << GPIO_BRR_BR11_Pos)           /*!< 0x00000800 */\n#define GPIO_BRR_BR11                    GPIO_BRR_BR11_Msk\n#define GPIO_BRR_BR12_Pos                (12U)\n#define GPIO_BRR_BR12_Msk                (0x1U << GPIO_BRR_BR12_Pos)           /*!< 0x00001000 */\n#define GPIO_BRR_BR12                    GPIO_BRR_BR12_Msk\n#define GPIO_BRR_BR13_Pos                (13U)\n#define GPIO_BRR_BR13_Msk                (0x1U << GPIO_BRR_BR13_Pos)           /*!< 0x00002000 */\n#define GPIO_BRR_BR13                    GPIO_BRR_BR13_Msk\n#define GPIO_BRR_BR14_Pos                (14U)\n#define GPIO_BRR_BR14_Msk                (0x1U << GPIO_BRR_BR14_Pos)           /*!< 0x00004000 */\n#define GPIO_BRR_BR14                    GPIO_BRR_BR14_Msk\n#define GPIO_BRR_BR15_Pos                (15U)\n#define GPIO_BRR_BR15_Msk                (0x1U << GPIO_BRR_BR15_Pos)           /*!< 0x00008000 */\n#define GPIO_BRR_BR15                    GPIO_BRR_BR15_Msk\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Inter-integrated Circuit Interface                    */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for I2C_CR1 register  ********************/\n#define I2C_CR1_PE_Pos            (0U)\n#define I2C_CR1_PE_Msk            (0x1U << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */\n#define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */\n#define I2C_CR1_SMBUS_Pos         (1U)\n#define I2C_CR1_SMBUS_Msk         (0x1U << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */\n#define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */\n#define I2C_CR1_SMBTYPE_Pos       (3U)\n#define I2C_CR1_SMBTYPE_Msk       (0x1U << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */\n#define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */\n#define I2C_CR1_ENARP_Pos         (4U)\n#define I2C_CR1_ENARP_Msk         (0x1U << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */\n#define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */\n#define I2C_CR1_ENPEC_Pos         (5U)\n#define I2C_CR1_ENPEC_Msk         (0x1U << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */\n#define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */\n#define I2C_CR1_ENGC_Pos          (6U)\n#define I2C_CR1_ENGC_Msk          (0x1U << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */\n#define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */\n#define I2C_CR1_NOSTRETCH_Pos     (7U)\n#define I2C_CR1_NOSTRETCH_Msk     (0x1U << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */\n#define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */\n#define I2C_CR1_START_Pos         (8U)\n#define I2C_CR1_START_Msk         (0x1U << I2C_CR1_START_Pos)                  /*!< 0x00000100 */\n#define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */\n#define I2C_CR1_STOP_Pos          (9U)\n#define I2C_CR1_STOP_Msk          (0x1U << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */\n#define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */\n#define I2C_CR1_ACK_Pos           (10U)\n#define I2C_CR1_ACK_Msk           (0x1U << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */\n#define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */\n#define I2C_CR1_POS_Pos           (11U)\n#define I2C_CR1_POS_Msk           (0x1U << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */\n#define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */\n#define I2C_CR1_PEC_Pos           (12U)\n#define I2C_CR1_PEC_Msk           (0x1U << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */\n#define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */\n#define I2C_CR1_ALERT_Pos         (13U)\n#define I2C_CR1_ALERT_Msk         (0x1U << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */\n#define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */\n#define I2C_CR1_SWRST_Pos         (15U)\n#define I2C_CR1_SWRST_Msk         (0x1U << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */\n#define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */\n\n/*******************  Bit definition for I2C_CR2 register  ********************/\n#define I2C_CR2_FREQ_Pos          (0U)\n#define I2C_CR2_FREQ_Msk          (0x3FU << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */\n#define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */\n#define I2C_CR2_FREQ_0            (0x01U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */\n#define I2C_CR2_FREQ_1            (0x02U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */\n#define I2C_CR2_FREQ_2            (0x04U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */\n#define I2C_CR2_FREQ_3            (0x08U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */\n#define I2C_CR2_FREQ_4            (0x10U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */\n#define I2C_CR2_FREQ_5            (0x20U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */\n\n#define I2C_CR2_ITERREN_Pos       (8U)\n#define I2C_CR2_ITERREN_Msk       (0x1U << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */\n#define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */\n#define I2C_CR2_ITEVTEN_Pos       (9U)\n#define I2C_CR2_ITEVTEN_Msk       (0x1U << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */\n#define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */\n#define I2C_CR2_ITBUFEN_Pos       (10U)\n#define I2C_CR2_ITBUFEN_Msk       (0x1U << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */\n#define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */\n#define I2C_CR2_DMAEN_Pos         (11U)\n#define I2C_CR2_DMAEN_Msk         (0x1U << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */\n#define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */\n#define I2C_CR2_LAST_Pos          (12U)\n#define I2C_CR2_LAST_Msk          (0x1U << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */\n#define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */\n\n/*******************  Bit definition for I2C_OAR1 register  *******************/\n#define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */\n#define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */\n\n#define I2C_OAR1_ADD0_Pos         (0U)\n#define I2C_OAR1_ADD0_Msk         (0x1U << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */\n#define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */\n#define I2C_OAR1_ADD1_Pos         (1U)\n#define I2C_OAR1_ADD1_Msk         (0x1U << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */\n#define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */\n#define I2C_OAR1_ADD2_Pos         (2U)\n#define I2C_OAR1_ADD2_Msk         (0x1U << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */\n#define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */\n#define I2C_OAR1_ADD3_Pos         (3U)\n#define I2C_OAR1_ADD3_Msk         (0x1U << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */\n#define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */\n#define I2C_OAR1_ADD4_Pos         (4U)\n#define I2C_OAR1_ADD4_Msk         (0x1U << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */\n#define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */\n#define I2C_OAR1_ADD5_Pos         (5U)\n#define I2C_OAR1_ADD5_Msk         (0x1U << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */\n#define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */\n#define I2C_OAR1_ADD6_Pos         (6U)\n#define I2C_OAR1_ADD6_Msk         (0x1U << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */\n#define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */\n#define I2C_OAR1_ADD7_Pos         (7U)\n#define I2C_OAR1_ADD7_Msk         (0x1U << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */\n#define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */\n#define I2C_OAR1_ADD8_Pos         (8U)\n#define I2C_OAR1_ADD8_Msk         (0x1U << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */\n#define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */\n#define I2C_OAR1_ADD9_Pos         (9U)\n#define I2C_OAR1_ADD9_Msk         (0x1U << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */\n#define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */\n\n#define I2C_OAR1_ADDMODE_Pos      (15U)\n#define I2C_OAR1_ADDMODE_Msk      (0x1U << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */\n#define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */\n\n/*******************  Bit definition for I2C_OAR2 register  *******************/\n#define I2C_OAR2_ENDUAL_Pos       (0U)\n#define I2C_OAR2_ENDUAL_Msk       (0x1U << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */\n#define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */\n#define I2C_OAR2_ADD2_Pos         (1U)\n#define I2C_OAR2_ADD2_Msk         (0x7FU << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */\n#define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */\n\n/********************  Bit definition for I2C_DR register  ********************/\n#define I2C_DR_DR_Pos             (0U)\n#define I2C_DR_DR_Msk             (0xFFU << I2C_DR_DR_Pos)                     /*!< 0x000000FF */\n#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */\n\n/*******************  Bit definition for I2C_SR1 register  ********************/\n#define I2C_SR1_SB_Pos            (0U)\n#define I2C_SR1_SB_Msk            (0x1U << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */\n#define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */\n#define I2C_SR1_ADDR_Pos          (1U)\n#define I2C_SR1_ADDR_Msk          (0x1U << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */\n#define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */\n#define I2C_SR1_BTF_Pos           (2U)\n#define I2C_SR1_BTF_Msk           (0x1U << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */\n#define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */\n#define I2C_SR1_ADD10_Pos         (3U)\n#define I2C_SR1_ADD10_Msk         (0x1U << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */\n#define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */\n#define I2C_SR1_STOPF_Pos         (4U)\n#define I2C_SR1_STOPF_Msk         (0x1U << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */\n#define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */\n#define I2C_SR1_RXNE_Pos          (6U)\n#define I2C_SR1_RXNE_Msk          (0x1U << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */\n#define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */\n#define I2C_SR1_TXE_Pos           (7U)\n#define I2C_SR1_TXE_Msk           (0x1U << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */\n#define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */\n#define I2C_SR1_BERR_Pos          (8U)\n#define I2C_SR1_BERR_Msk          (0x1U << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */\n#define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */\n#define I2C_SR1_ARLO_Pos          (9U)\n#define I2C_SR1_ARLO_Msk          (0x1U << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */\n#define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */\n#define I2C_SR1_AF_Pos            (10U)\n#define I2C_SR1_AF_Msk            (0x1U << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */\n#define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */\n#define I2C_SR1_OVR_Pos           (11U)\n#define I2C_SR1_OVR_Msk           (0x1U << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */\n#define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */\n#define I2C_SR1_PECERR_Pos        (12U)\n#define I2C_SR1_PECERR_Msk        (0x1U << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */\n#define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */\n#define I2C_SR1_TIMEOUT_Pos       (14U)\n#define I2C_SR1_TIMEOUT_Msk       (0x1U << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */\n#define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */\n#define I2C_SR1_SMBALERT_Pos      (15U)\n#define I2C_SR1_SMBALERT_Msk      (0x1U << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */\n#define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */\n\n/*******************  Bit definition for I2C_SR2 register  ********************/\n#define I2C_SR2_MSL_Pos           (0U)\n#define I2C_SR2_MSL_Msk           (0x1U << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */\n#define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */\n#define I2C_SR2_BUSY_Pos          (1U)\n#define I2C_SR2_BUSY_Msk          (0x1U << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */\n#define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */\n#define I2C_SR2_TRA_Pos           (2U)\n#define I2C_SR2_TRA_Msk           (0x1U << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */\n#define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */\n#define I2C_SR2_GENCALL_Pos       (4U)\n#define I2C_SR2_GENCALL_Msk       (0x1U << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */\n#define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */\n#define I2C_SR2_SMBDEFAULT_Pos    (5U)\n#define I2C_SR2_SMBDEFAULT_Msk    (0x1U << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */\n#define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */\n#define I2C_SR2_SMBHOST_Pos       (6U)\n#define I2C_SR2_SMBHOST_Msk       (0x1U << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */\n#define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */\n#define I2C_SR2_DUALF_Pos         (7U)\n#define I2C_SR2_DUALF_Msk         (0x1U << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */\n#define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */\n#define I2C_SR2_PEC_Pos           (8U)\n#define I2C_SR2_PEC_Msk           (0xFFU << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */\n#define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */\n\n/*******************  Bit definition for I2C_CCR register  ********************/\n#define I2C_CCR_CCR_Pos           (0U)\n#define I2C_CCR_CCR_Msk           (0xFFFU << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */\n#define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */\n#define I2C_CCR_DUTY_Pos          (14U)\n#define I2C_CCR_DUTY_Msk          (0x1U << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */\n#define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */\n#define I2C_CCR_FS_Pos            (15U)\n#define I2C_CCR_FS_Msk            (0x1U << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */\n#define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */\n\n/******************  Bit definition for I2C_TRISE register  *******************/\n#define I2C_TRISE_TRISE_Pos       (0U)\n#define I2C_TRISE_TRISE_Msk       (0x3FU << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */\n#define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Independent WATCHDOG                             */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define IWDG_KR_KEY_Pos     (0U)\n#define IWDG_KR_KEY_Msk     (0xFFFFU << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */\n#define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */\n\n/*******************  Bit definition for IWDG_PR register  ********************/\n#define IWDG_PR_PR_Pos      (0U)\n#define IWDG_PR_PR_Msk      (0x7U << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */\n#define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */\n#define IWDG_PR_PR_0        (0x1U << IWDG_PR_PR_Pos)                           /*!< 0x01 */\n#define IWDG_PR_PR_1        (0x2U << IWDG_PR_PR_Pos)                           /*!< 0x02 */\n#define IWDG_PR_PR_2        (0x4U << IWDG_PR_PR_Pos)                           /*!< 0x04 */\n\n/*******************  Bit definition for IWDG_RLR register  *******************/\n#define IWDG_RLR_RL_Pos     (0U)\n#define IWDG_RLR_RL_Msk     (0xFFFU << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */\n#define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */\n\n/*******************  Bit definition for IWDG_SR register  ********************/\n#define IWDG_SR_PVU_Pos     (0U)\n#define IWDG_SR_PVU_Msk     (0x1U << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */\n#define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */\n#define IWDG_SR_RVU_Pos     (1U)\n#define IWDG_SR_RVU_Msk     (0x1U << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */\n#define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                             Power Control                                  */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for PWR_CR register  ********************/\n#define PWR_CR_LPDS_Pos        (0U)\n#define PWR_CR_LPDS_Msk        (0x1U << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */\n#define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */\n#define PWR_CR_PDDS_Pos        (1U)\n#define PWR_CR_PDDS_Msk        (0x1U << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */\n#define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */\n#define PWR_CR_CWUF_Pos        (2U)\n#define PWR_CR_CWUF_Msk        (0x1U << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */\n#define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */\n#define PWR_CR_CSBF_Pos        (3U)\n#define PWR_CR_CSBF_Msk        (0x1U << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */\n#define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */\n#define PWR_CR_PVDE_Pos        (4U)\n#define PWR_CR_PVDE_Msk        (0x1U << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */\n#define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */\n\n#define PWR_CR_PLS_Pos         (5U)\n#define PWR_CR_PLS_Msk         (0x7U << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */\n#define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */\n#define PWR_CR_PLS_0           (0x1U << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */\n#define PWR_CR_PLS_1           (0x2U << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */\n#define PWR_CR_PLS_2           (0x4U << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */\n\n/*!< PVD level configuration */\n#define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */\n#define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */\n#define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */\n#define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */\n#define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */\n#define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */\n#define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */\n#define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */\n#define PWR_CR_DBP_Pos         (8U)\n#define PWR_CR_DBP_Msk         (0x1U << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */\n#define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */\n#define PWR_CR_FPDS_Pos        (9U)\n#define PWR_CR_FPDS_Msk        (0x1U << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */\n#define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */\n#define PWR_CR_VOS_Pos         (14U)\n#define PWR_CR_VOS_Msk         (0x1U << PWR_CR_VOS_Pos)                        /*!< 0x00004000 */\n#define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS bit (Regulator voltage scaling output selection) */\n\n/* Legacy define */\n#define  PWR_CR_PMODE                        PWR_CR_VOS\n\n/*******************  Bit definition for PWR_CSR register  ********************/\n#define PWR_CSR_WUF_Pos        (0U)\n#define PWR_CSR_WUF_Msk        (0x1U << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */\n#define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */\n#define PWR_CSR_SBF_Pos        (1U)\n#define PWR_CSR_SBF_Msk        (0x1U << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */\n#define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */\n#define PWR_CSR_PVDO_Pos       (2U)\n#define PWR_CSR_PVDO_Msk       (0x1U << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */\n#define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */\n#define PWR_CSR_BRR_Pos        (3U)\n#define PWR_CSR_BRR_Msk        (0x1U << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */\n#define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */\n#define PWR_CSR_EWUP_Pos       (8U)\n#define PWR_CSR_EWUP_Msk       (0x1U << PWR_CSR_EWUP_Pos)                      /*!< 0x00000100 */\n#define PWR_CSR_EWUP           PWR_CSR_EWUP_Msk                                /*!< Enable WKUP pin                                  */\n#define PWR_CSR_BRE_Pos        (9U)\n#define PWR_CSR_BRE_Msk        (0x1U << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */\n#define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */\n#define PWR_CSR_VOSRDY_Pos     (14U)\n#define PWR_CSR_VOSRDY_Msk     (0x1U << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */\n#define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */\n\n/* Legacy define */\n#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Reset and Clock Control                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for RCC_CR register  ********************/\n#define RCC_CR_HSION_Pos                   (0U)\n#define RCC_CR_HSION_Msk                   (0x1U << RCC_CR_HSION_Pos)          /*!< 0x00000001 */\n#define RCC_CR_HSION                       RCC_CR_HSION_Msk\n#define RCC_CR_HSIRDY_Pos                  (1U)\n#define RCC_CR_HSIRDY_Msk                  (0x1U << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */\n#define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk\n\n#define RCC_CR_HSITRIM_Pos                 (3U)\n#define RCC_CR_HSITRIM_Msk                 (0x1FU << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */\n#define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk\n#define RCC_CR_HSITRIM_0                   (0x01U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */\n#define RCC_CR_HSITRIM_1                   (0x02U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */\n#define RCC_CR_HSITRIM_2                   (0x04U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */\n#define RCC_CR_HSITRIM_3                   (0x08U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */\n#define RCC_CR_HSITRIM_4                   (0x10U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */\n\n#define RCC_CR_HSICAL_Pos                  (8U)\n#define RCC_CR_HSICAL_Msk                  (0xFFU << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */\n#define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk\n#define RCC_CR_HSICAL_0                    (0x01U << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */\n#define RCC_CR_HSICAL_1                    (0x02U << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */\n#define RCC_CR_HSICAL_2                    (0x04U << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */\n#define RCC_CR_HSICAL_3                    (0x08U << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */\n#define RCC_CR_HSICAL_4                    (0x10U << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */\n#define RCC_CR_HSICAL_5                    (0x20U << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */\n#define RCC_CR_HSICAL_6                    (0x40U << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */\n#define RCC_CR_HSICAL_7                    (0x80U << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */\n\n#define RCC_CR_HSEON_Pos                   (16U)\n#define RCC_CR_HSEON_Msk                   (0x1U << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */\n#define RCC_CR_HSEON                       RCC_CR_HSEON_Msk\n#define RCC_CR_HSERDY_Pos                  (17U)\n#define RCC_CR_HSERDY_Msk                  (0x1U << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */\n#define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk\n#define RCC_CR_HSEBYP_Pos                  (18U)\n#define RCC_CR_HSEBYP_Msk                  (0x1U << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */\n#define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk\n#define RCC_CR_CSSON_Pos                   (19U)\n#define RCC_CR_CSSON_Msk                   (0x1U << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */\n#define RCC_CR_CSSON                       RCC_CR_CSSON_Msk\n#define RCC_CR_PLLON_Pos                   (24U)\n#define RCC_CR_PLLON_Msk                   (0x1U << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */\n#define RCC_CR_PLLON                       RCC_CR_PLLON_Msk\n#define RCC_CR_PLLRDY_Pos                  (25U)\n#define RCC_CR_PLLRDY_Msk                  (0x1U << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */\n#define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_PLLI2S_SUPPORT                                                     /*!< Support PLLI2S oscillator */\n\n#define RCC_CR_PLLI2SON_Pos                (26U)\n#define RCC_CR_PLLI2SON_Msk                (0x1U << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */\n#define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk\n#define RCC_CR_PLLI2SRDY_Pos               (27U)\n#define RCC_CR_PLLI2SRDY_Msk               (0x1U << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */\n#define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk\n\n/********************  Bit definition for RCC_PLLCFGR register  ***************/\n#define RCC_PLLCFGR_PLLM_Pos               (0U)\n#define RCC_PLLCFGR_PLLM_Msk               (0x3FU << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */\n#define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk\n#define RCC_PLLCFGR_PLLM_0                 (0x01U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */\n#define RCC_PLLCFGR_PLLM_1                 (0x02U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */\n#define RCC_PLLCFGR_PLLM_2                 (0x04U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */\n#define RCC_PLLCFGR_PLLM_3                 (0x08U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */\n#define RCC_PLLCFGR_PLLM_4                 (0x10U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */\n#define RCC_PLLCFGR_PLLM_5                 (0x20U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */\n\n#define RCC_PLLCFGR_PLLN_Pos               (6U)\n#define RCC_PLLCFGR_PLLN_Msk               (0x1FFU << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */\n#define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk\n#define RCC_PLLCFGR_PLLN_0                 (0x001U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */\n#define RCC_PLLCFGR_PLLN_1                 (0x002U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */\n#define RCC_PLLCFGR_PLLN_2                 (0x004U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */\n#define RCC_PLLCFGR_PLLN_3                 (0x008U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */\n#define RCC_PLLCFGR_PLLN_4                 (0x010U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */\n#define RCC_PLLCFGR_PLLN_5                 (0x020U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */\n#define RCC_PLLCFGR_PLLN_6                 (0x040U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */\n#define RCC_PLLCFGR_PLLN_7                 (0x080U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */\n#define RCC_PLLCFGR_PLLN_8                 (0x100U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */\n\n#define RCC_PLLCFGR_PLLP_Pos               (16U)\n#define RCC_PLLCFGR_PLLP_Msk               (0x3U << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */\n#define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk\n#define RCC_PLLCFGR_PLLP_0                 (0x1U << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */\n#define RCC_PLLCFGR_PLLP_1                 (0x2U << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */\n\n#define RCC_PLLCFGR_PLLSRC_Pos             (22U)\n#define RCC_PLLCFGR_PLLSRC_Msk             (0x1U << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk\n#define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)\n#define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk\n#define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U\n\n#define RCC_PLLCFGR_PLLQ_Pos               (24U)\n#define RCC_PLLCFGR_PLLQ_Msk               (0xFU << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */\n#define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk\n#define RCC_PLLCFGR_PLLQ_0                 (0x1U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */\n#define RCC_PLLCFGR_PLLQ_1                 (0x2U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */\n#define RCC_PLLCFGR_PLLQ_2                 (0x4U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */\n#define RCC_PLLCFGR_PLLQ_3                 (0x8U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */\n\n\n/********************  Bit definition for RCC_CFGR register  ******************/\n/*!< SW configuration */\n#define RCC_CFGR_SW_Pos                    (0U)\n#define RCC_CFGR_SW_Msk                    (0x3U << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */\n#define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */\n#define RCC_CFGR_SW_0                      (0x1U << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */\n#define RCC_CFGR_SW_1                      (0x2U << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */\n\n#define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */\n#define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */\n#define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */\n\n/*!< SWS configuration */\n#define RCC_CFGR_SWS_Pos                   (2U)\n#define RCC_CFGR_SWS_Msk                   (0x3U << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */\n#define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */\n#define RCC_CFGR_SWS_0                     (0x1U << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */\n#define RCC_CFGR_SWS_1                     (0x2U << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */\n\n#define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */\n#define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */\n#define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */\n\n/*!< HPRE configuration */\n#define RCC_CFGR_HPRE_Pos                  (4U)\n#define RCC_CFGR_HPRE_Msk                  (0xFU << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */\n#define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */\n#define RCC_CFGR_HPRE_0                    (0x1U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */\n#define RCC_CFGR_HPRE_1                    (0x2U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */\n#define RCC_CFGR_HPRE_2                    (0x4U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */\n#define RCC_CFGR_HPRE_3                    (0x8U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */\n\n#define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */\n#define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */\n#define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */\n#define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */\n#define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */\n#define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */\n#define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */\n#define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */\n#define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */\n\n/*!< PPRE1 configuration */\n#define RCC_CFGR_PPRE1_Pos                 (10U)\n#define RCC_CFGR_PPRE1_Msk                 (0x7U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */\n#define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */\n#define RCC_CFGR_PPRE1_0                   (0x1U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */\n#define RCC_CFGR_PPRE1_1                   (0x2U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */\n#define RCC_CFGR_PPRE1_2                   (0x4U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */\n\n#define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */\n\n/*!< PPRE2 configuration */\n#define RCC_CFGR_PPRE2_Pos                 (13U)\n#define RCC_CFGR_PPRE2_Msk                 (0x7U << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */\n#define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */\n#define RCC_CFGR_PPRE2_0                   (0x1U << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */\n#define RCC_CFGR_PPRE2_1                   (0x2U << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */\n#define RCC_CFGR_PPRE2_2                   (0x4U << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */\n\n#define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */\n\n/*!< RTCPRE configuration */\n#define RCC_CFGR_RTCPRE_Pos                (16U)\n#define RCC_CFGR_RTCPRE_Msk                (0x1FU << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */\n#define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk\n#define RCC_CFGR_RTCPRE_0                  (0x01U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */\n#define RCC_CFGR_RTCPRE_1                  (0x02U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */\n#define RCC_CFGR_RTCPRE_2                  (0x04U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */\n#define RCC_CFGR_RTCPRE_3                  (0x08U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */\n#define RCC_CFGR_RTCPRE_4                  (0x10U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */\n\n/*!< MCO1 configuration */\n#define RCC_CFGR_MCO1_Pos                  (21U)\n#define RCC_CFGR_MCO1_Msk                  (0x3U << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */\n#define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk\n#define RCC_CFGR_MCO1_0                    (0x1U << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */\n#define RCC_CFGR_MCO1_1                    (0x2U << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */\n\n#define RCC_CFGR_I2SSRC_Pos                (23U)\n#define RCC_CFGR_I2SSRC_Msk                (0x1U << RCC_CFGR_I2SSRC_Pos)       /*!< 0x00800000 */\n#define RCC_CFGR_I2SSRC                    RCC_CFGR_I2SSRC_Msk\n\n#define RCC_CFGR_MCO1PRE_Pos               (24U)\n#define RCC_CFGR_MCO1PRE_Msk               (0x7U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */\n#define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk\n#define RCC_CFGR_MCO1PRE_0                 (0x1U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */\n#define RCC_CFGR_MCO1PRE_1                 (0x2U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */\n#define RCC_CFGR_MCO1PRE_2                 (0x4U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */\n\n#define RCC_CFGR_MCO2PRE_Pos               (27U)\n#define RCC_CFGR_MCO2PRE_Msk               (0x7U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */\n#define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk\n#define RCC_CFGR_MCO2PRE_0                 (0x1U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */\n#define RCC_CFGR_MCO2PRE_1                 (0x2U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */\n#define RCC_CFGR_MCO2PRE_2                 (0x4U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */\n\n#define RCC_CFGR_MCO2_Pos                  (30U)\n#define RCC_CFGR_MCO2_Msk                  (0x3U << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */\n#define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk\n#define RCC_CFGR_MCO2_0                    (0x1U << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */\n#define RCC_CFGR_MCO2_1                    (0x2U << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */\n\n/********************  Bit definition for RCC_CIR register  *******************/\n#define RCC_CIR_LSIRDYF_Pos                (0U)\n#define RCC_CIR_LSIRDYF_Msk                (0x1U << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */\n#define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk\n#define RCC_CIR_LSERDYF_Pos                (1U)\n#define RCC_CIR_LSERDYF_Msk                (0x1U << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */\n#define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk\n#define RCC_CIR_HSIRDYF_Pos                (2U)\n#define RCC_CIR_HSIRDYF_Msk                (0x1U << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */\n#define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk\n#define RCC_CIR_HSERDYF_Pos                (3U)\n#define RCC_CIR_HSERDYF_Msk                (0x1U << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */\n#define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk\n#define RCC_CIR_PLLRDYF_Pos                (4U)\n#define RCC_CIR_PLLRDYF_Msk                (0x1U << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */\n#define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk\n#define RCC_CIR_PLLI2SRDYF_Pos             (5U)\n#define RCC_CIR_PLLI2SRDYF_Msk             (0x1U << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */\n#define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk\n\n#define RCC_CIR_CSSF_Pos                   (7U)\n#define RCC_CIR_CSSF_Msk                   (0x1U << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */\n#define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk\n#define RCC_CIR_LSIRDYIE_Pos               (8U)\n#define RCC_CIR_LSIRDYIE_Msk               (0x1U << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */\n#define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk\n#define RCC_CIR_LSERDYIE_Pos               (9U)\n#define RCC_CIR_LSERDYIE_Msk               (0x1U << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */\n#define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk\n#define RCC_CIR_HSIRDYIE_Pos               (10U)\n#define RCC_CIR_HSIRDYIE_Msk               (0x1U << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */\n#define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk\n#define RCC_CIR_HSERDYIE_Pos               (11U)\n#define RCC_CIR_HSERDYIE_Msk               (0x1U << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */\n#define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk\n#define RCC_CIR_PLLRDYIE_Pos               (12U)\n#define RCC_CIR_PLLRDYIE_Msk               (0x1U << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */\n#define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk\n#define RCC_CIR_PLLI2SRDYIE_Pos            (13U)\n#define RCC_CIR_PLLI2SRDYIE_Msk            (0x1U << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */\n#define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk\n\n#define RCC_CIR_LSIRDYC_Pos                (16U)\n#define RCC_CIR_LSIRDYC_Msk                (0x1U << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */\n#define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk\n#define RCC_CIR_LSERDYC_Pos                (17U)\n#define RCC_CIR_LSERDYC_Msk                (0x1U << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */\n#define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk\n#define RCC_CIR_HSIRDYC_Pos                (18U)\n#define RCC_CIR_HSIRDYC_Msk                (0x1U << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */\n#define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk\n#define RCC_CIR_HSERDYC_Pos                (19U)\n#define RCC_CIR_HSERDYC_Msk                (0x1U << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */\n#define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk\n#define RCC_CIR_PLLRDYC_Pos                (20U)\n#define RCC_CIR_PLLRDYC_Msk                (0x1U << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */\n#define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk\n#define RCC_CIR_PLLI2SRDYC_Pos             (21U)\n#define RCC_CIR_PLLI2SRDYC_Msk             (0x1U << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */\n#define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk\n\n#define RCC_CIR_CSSC_Pos                   (23U)\n#define RCC_CIR_CSSC_Msk                   (0x1U << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */\n#define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk\n\n/********************  Bit definition for RCC_AHB1RSTR register  **************/\n#define RCC_AHB1RSTR_GPIOARST_Pos          (0U)\n#define RCC_AHB1RSTR_GPIOARST_Msk          (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */\n#define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk\n#define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)\n#define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */\n#define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk\n#define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)\n#define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */\n#define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk\n#define RCC_AHB1RSTR_GPIODRST_Pos          (3U)\n#define RCC_AHB1RSTR_GPIODRST_Msk          (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */\n#define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk\n#define RCC_AHB1RSTR_GPIOERST_Pos          (4U)\n#define RCC_AHB1RSTR_GPIOERST_Msk          (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */\n#define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk\n#define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)\n#define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */\n#define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk\n#define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)\n#define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */\n#define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk\n#define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)\n#define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk\n#define RCC_AHB1RSTR_GPIOIRST_Pos          (8U)\n#define RCC_AHB1RSTR_GPIOIRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */\n#define RCC_AHB1RSTR_GPIOIRST              RCC_AHB1RSTR_GPIOIRST_Msk\n#define RCC_AHB1RSTR_CRCRST_Pos            (12U)\n#define RCC_AHB1RSTR_CRCRST_Msk            (0x1U << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */\n#define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk\n#define RCC_AHB1RSTR_DMA1RST_Pos           (21U)\n#define RCC_AHB1RSTR_DMA1RST_Msk           (0x1U << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */\n#define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk\n#define RCC_AHB1RSTR_DMA2RST_Pos           (22U)\n#define RCC_AHB1RSTR_DMA2RST_Msk           (0x1U << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */\n#define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk\n#define RCC_AHB1RSTR_ETHMACRST_Pos         (25U)\n#define RCC_AHB1RSTR_ETHMACRST_Msk         (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */\n#define RCC_AHB1RSTR_ETHMACRST             RCC_AHB1RSTR_ETHMACRST_Msk\n#define RCC_AHB1RSTR_OTGHRST_Pos           (29U)\n#define RCC_AHB1RSTR_OTGHRST_Msk           (0x1U << RCC_AHB1RSTR_OTGHRST_Pos)  /*!< 0x20000000 */\n#define RCC_AHB1RSTR_OTGHRST               RCC_AHB1RSTR_OTGHRST_Msk\n\n/********************  Bit definition for RCC_AHB2RSTR register  **************/\n#define RCC_AHB2RSTR_DCMIRST_Pos           (0U)\n#define RCC_AHB2RSTR_DCMIRST_Msk           (0x1U << RCC_AHB2RSTR_DCMIRST_Pos)  /*!< 0x00000001 */\n#define RCC_AHB2RSTR_DCMIRST               RCC_AHB2RSTR_DCMIRST_Msk\n#define RCC_AHB2RSTR_RNGRST_Pos            (6U)\n#define RCC_AHB2RSTR_RNGRST_Msk            (0x1U << RCC_AHB2RSTR_RNGRST_Pos)   /*!< 0x00000040 */\n#define RCC_AHB2RSTR_RNGRST                RCC_AHB2RSTR_RNGRST_Msk\n#define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)\n#define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk\n/********************  Bit definition for RCC_AHB3RSTR register  **************/\n#define RCC_AHB3RSTR_FSMCRST_Pos           (0U)\n#define RCC_AHB3RSTR_FSMCRST_Msk           (0x1U << RCC_AHB3RSTR_FSMCRST_Pos)  /*!< 0x00000001 */\n#define RCC_AHB3RSTR_FSMCRST               RCC_AHB3RSTR_FSMCRST_Msk\n\n\n/********************  Bit definition for RCC_APB1RSTR register  **************/\n#define RCC_APB1RSTR_TIM2RST_Pos           (0U)\n#define RCC_APB1RSTR_TIM2RST_Msk           (0x1U << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk\n#define RCC_APB1RSTR_TIM3RST_Pos           (1U)\n#define RCC_APB1RSTR_TIM3RST_Msk           (0x1U << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk\n#define RCC_APB1RSTR_TIM4RST_Pos           (2U)\n#define RCC_APB1RSTR_TIM4RST_Msk           (0x1U << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */\n#define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk\n#define RCC_APB1RSTR_TIM5RST_Pos           (3U)\n#define RCC_APB1RSTR_TIM5RST_Msk           (0x1U << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */\n#define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk\n#define RCC_APB1RSTR_TIM6RST_Pos           (4U)\n#define RCC_APB1RSTR_TIM6RST_Msk           (0x1U << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */\n#define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk\n#define RCC_APB1RSTR_TIM7RST_Pos           (5U)\n#define RCC_APB1RSTR_TIM7RST_Msk           (0x1U << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */\n#define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk\n#define RCC_APB1RSTR_TIM12RST_Pos          (6U)\n#define RCC_APB1RSTR_TIM12RST_Msk          (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */\n#define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk\n#define RCC_APB1RSTR_TIM13RST_Pos          (7U)\n#define RCC_APB1RSTR_TIM13RST_Msk          (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */\n#define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk\n#define RCC_APB1RSTR_TIM14RST_Pos          (8U)\n#define RCC_APB1RSTR_TIM14RST_Msk          (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */\n#define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk\n#define RCC_APB1RSTR_WWDGRST_Pos           (11U)\n#define RCC_APB1RSTR_WWDGRST_Msk           (0x1U << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */\n#define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk\n#define RCC_APB1RSTR_SPI2RST_Pos           (14U)\n#define RCC_APB1RSTR_SPI2RST_Msk           (0x1U << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */\n#define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk\n#define RCC_APB1RSTR_SPI3RST_Pos           (15U)\n#define RCC_APB1RSTR_SPI3RST_Msk           (0x1U << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */\n#define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk\n#define RCC_APB1RSTR_USART2RST_Pos         (17U)\n#define RCC_APB1RSTR_USART2RST_Msk         (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */\n#define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk\n#define RCC_APB1RSTR_USART3RST_Pos         (18U)\n#define RCC_APB1RSTR_USART3RST_Msk         (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */\n#define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk\n#define RCC_APB1RSTR_UART4RST_Pos          (19U)\n#define RCC_APB1RSTR_UART4RST_Msk          (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */\n#define RCC_APB1RSTR_UART4RST              RCC_APB1RSTR_UART4RST_Msk\n#define RCC_APB1RSTR_UART5RST_Pos          (20U)\n#define RCC_APB1RSTR_UART5RST_Msk          (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */\n#define RCC_APB1RSTR_UART5RST              RCC_APB1RSTR_UART5RST_Msk\n#define RCC_APB1RSTR_I2C1RST_Pos           (21U)\n#define RCC_APB1RSTR_I2C1RST_Msk           (0x1U << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */\n#define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk\n#define RCC_APB1RSTR_I2C2RST_Pos           (22U)\n#define RCC_APB1RSTR_I2C2RST_Msk           (0x1U << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */\n#define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk\n#define RCC_APB1RSTR_I2C3RST_Pos           (23U)\n#define RCC_APB1RSTR_I2C3RST_Msk           (0x1U << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */\n#define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk\n#define RCC_APB1RSTR_CAN1RST_Pos           (25U)\n#define RCC_APB1RSTR_CAN1RST_Msk           (0x1U << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */\n#define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk\n#define RCC_APB1RSTR_CAN2RST_Pos           (26U)\n#define RCC_APB1RSTR_CAN2RST_Msk           (0x1U << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */\n#define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk\n#define RCC_APB1RSTR_PWRRST_Pos            (28U)\n#define RCC_APB1RSTR_PWRRST_Msk            (0x1U << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */\n#define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk\n#define RCC_APB1RSTR_DACRST_Pos            (29U)\n#define RCC_APB1RSTR_DACRST_Msk            (0x1U << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */\n#define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk\n\n/********************  Bit definition for RCC_APB2RSTR register  **************/\n#define RCC_APB2RSTR_TIM1RST_Pos           (0U)\n#define RCC_APB2RSTR_TIM1RST_Msk           (0x1U << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk\n#define RCC_APB2RSTR_TIM8RST_Pos           (1U)\n#define RCC_APB2RSTR_TIM8RST_Msk           (0x1U << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk\n#define RCC_APB2RSTR_USART1RST_Pos         (4U)\n#define RCC_APB2RSTR_USART1RST_Msk         (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */\n#define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk\n#define RCC_APB2RSTR_USART6RST_Pos         (5U)\n#define RCC_APB2RSTR_USART6RST_Msk         (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */\n#define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk\n#define RCC_APB2RSTR_ADCRST_Pos            (8U)\n#define RCC_APB2RSTR_ADCRST_Msk            (0x1U << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */\n#define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk\n#define RCC_APB2RSTR_SDIORST_Pos           (11U)\n#define RCC_APB2RSTR_SDIORST_Msk           (0x1U << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */\n#define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk\n#define RCC_APB2RSTR_SPI1RST_Pos           (12U)\n#define RCC_APB2RSTR_SPI1RST_Msk           (0x1U << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */\n#define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk\n#define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)\n#define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */\n#define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk\n#define RCC_APB2RSTR_TIM9RST_Pos           (16U)\n#define RCC_APB2RSTR_TIM9RST_Msk           (0x1U << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */\n#define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk\n#define RCC_APB2RSTR_TIM10RST_Pos          (17U)\n#define RCC_APB2RSTR_TIM10RST_Msk          (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */\n#define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk\n#define RCC_APB2RSTR_TIM11RST_Pos          (18U)\n#define RCC_APB2RSTR_TIM11RST_Msk          (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */\n#define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk\n\n/* Old SPI1RST bit definition, maintained for legacy purpose */\n#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST\n\n/********************  Bit definition for RCC_AHB1ENR register  ***************/\n#define RCC_AHB1ENR_GPIOAEN_Pos            (0U)\n#define RCC_AHB1ENR_GPIOAEN_Msk            (0x1U << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */\n#define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk\n#define RCC_AHB1ENR_GPIOBEN_Pos            (1U)\n#define RCC_AHB1ENR_GPIOBEN_Msk            (0x1U << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */\n#define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk\n#define RCC_AHB1ENR_GPIOCEN_Pos            (2U)\n#define RCC_AHB1ENR_GPIOCEN_Msk            (0x1U << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */\n#define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk\n#define RCC_AHB1ENR_GPIODEN_Pos            (3U)\n#define RCC_AHB1ENR_GPIODEN_Msk            (0x1U << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */\n#define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk\n#define RCC_AHB1ENR_GPIOEEN_Pos            (4U)\n#define RCC_AHB1ENR_GPIOEEN_Msk            (0x1U << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */\n#define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk\n#define RCC_AHB1ENR_GPIOFEN_Pos            (5U)\n#define RCC_AHB1ENR_GPIOFEN_Msk            (0x1U << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */\n#define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk\n#define RCC_AHB1ENR_GPIOGEN_Pos            (6U)\n#define RCC_AHB1ENR_GPIOGEN_Msk            (0x1U << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */\n#define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk\n#define RCC_AHB1ENR_GPIOHEN_Pos            (7U)\n#define RCC_AHB1ENR_GPIOHEN_Msk            (0x1U << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk\n#define RCC_AHB1ENR_GPIOIEN_Pos            (8U)\n#define RCC_AHB1ENR_GPIOIEN_Msk            (0x1U << RCC_AHB1ENR_GPIOIEN_Pos)   /*!< 0x00000100 */\n#define RCC_AHB1ENR_GPIOIEN                RCC_AHB1ENR_GPIOIEN_Msk\n#define RCC_AHB1ENR_CRCEN_Pos              (12U)\n#define RCC_AHB1ENR_CRCEN_Msk              (0x1U << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */\n#define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk\n#define RCC_AHB1ENR_BKPSRAMEN_Pos          (18U)\n#define RCC_AHB1ENR_BKPSRAMEN_Msk          (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */\n#define RCC_AHB1ENR_BKPSRAMEN              RCC_AHB1ENR_BKPSRAMEN_Msk\n#define RCC_AHB1ENR_CCMDATARAMEN_Pos       (20U)\n#define RCC_AHB1ENR_CCMDATARAMEN_Msk       (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */\n#define RCC_AHB1ENR_CCMDATARAMEN           RCC_AHB1ENR_CCMDATARAMEN_Msk\n#define RCC_AHB1ENR_DMA1EN_Pos             (21U)\n#define RCC_AHB1ENR_DMA1EN_Msk             (0x1U << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */\n#define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk\n#define RCC_AHB1ENR_DMA2EN_Pos             (22U)\n#define RCC_AHB1ENR_DMA2EN_Msk             (0x1U << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */\n#define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk\n#define RCC_AHB1ENR_ETHMACEN_Pos           (25U)\n#define RCC_AHB1ENR_ETHMACEN_Msk           (0x1U << RCC_AHB1ENR_ETHMACEN_Pos)  /*!< 0x02000000 */\n#define RCC_AHB1ENR_ETHMACEN               RCC_AHB1ENR_ETHMACEN_Msk\n#define RCC_AHB1ENR_ETHMACTXEN_Pos         (26U)\n#define RCC_AHB1ENR_ETHMACTXEN_Msk         (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */\n#define RCC_AHB1ENR_ETHMACTXEN             RCC_AHB1ENR_ETHMACTXEN_Msk\n#define RCC_AHB1ENR_ETHMACRXEN_Pos         (27U)\n#define RCC_AHB1ENR_ETHMACRXEN_Msk         (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */\n#define RCC_AHB1ENR_ETHMACRXEN             RCC_AHB1ENR_ETHMACRXEN_Msk\n#define RCC_AHB1ENR_ETHMACPTPEN_Pos        (28U)\n#define RCC_AHB1ENR_ETHMACPTPEN_Msk        (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */\n#define RCC_AHB1ENR_ETHMACPTPEN            RCC_AHB1ENR_ETHMACPTPEN_Msk\n#define RCC_AHB1ENR_OTGHSEN_Pos            (29U)\n#define RCC_AHB1ENR_OTGHSEN_Msk            (0x1U << RCC_AHB1ENR_OTGHSEN_Pos)   /*!< 0x20000000 */\n#define RCC_AHB1ENR_OTGHSEN                RCC_AHB1ENR_OTGHSEN_Msk\n#define RCC_AHB1ENR_OTGHSULPIEN_Pos        (30U)\n#define RCC_AHB1ENR_OTGHSULPIEN_Msk        (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */\n#define RCC_AHB1ENR_OTGHSULPIEN            RCC_AHB1ENR_OTGHSULPIEN_Msk\n/********************  Bit definition for RCC_AHB2ENR register  ***************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_AHB2_SUPPORT                   /*!< AHB2 Bus is supported */\n\n#define RCC_AHB2ENR_DCMIEN_Pos             (0U)\n#define RCC_AHB2ENR_DCMIEN_Msk             (0x1U << RCC_AHB2ENR_DCMIEN_Pos)    /*!< 0x00000001 */\n#define RCC_AHB2ENR_DCMIEN                 RCC_AHB2ENR_DCMIEN_Msk\n#define RCC_AHB2ENR_RNGEN_Pos              (6U)\n#define RCC_AHB2ENR_RNGEN_Msk              (0x1U << RCC_AHB2ENR_RNGEN_Pos)     /*!< 0x00000040 */\n#define RCC_AHB2ENR_RNGEN                  RCC_AHB2ENR_RNGEN_Msk\n#define RCC_AHB2ENR_OTGFSEN_Pos            (7U)\n#define RCC_AHB2ENR_OTGFSEN_Msk            (0x1U << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk\n\n/********************  Bit definition for RCC_AHB3ENR register  ***************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_AHB3_SUPPORT                   /*!< AHB3 Bus is supported */\n\n#define RCC_AHB3ENR_FSMCEN_Pos             (0U)\n#define RCC_AHB3ENR_FSMCEN_Msk             (0x1U << RCC_AHB3ENR_FSMCEN_Pos)    /*!< 0x00000001 */\n#define RCC_AHB3ENR_FSMCEN                 RCC_AHB3ENR_FSMCEN_Msk\n\n/********************  Bit definition for RCC_APB1ENR register  ***************/\n#define RCC_APB1ENR_TIM2EN_Pos             (0U)\n#define RCC_APB1ENR_TIM2EN_Msk             (0x1U << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk\n#define RCC_APB1ENR_TIM3EN_Pos             (1U)\n#define RCC_APB1ENR_TIM3EN_Msk             (0x1U << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk\n#define RCC_APB1ENR_TIM4EN_Pos             (2U)\n#define RCC_APB1ENR_TIM4EN_Msk             (0x1U << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */\n#define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk\n#define RCC_APB1ENR_TIM5EN_Pos             (3U)\n#define RCC_APB1ENR_TIM5EN_Msk             (0x1U << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */\n#define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk\n#define RCC_APB1ENR_TIM6EN_Pos             (4U)\n#define RCC_APB1ENR_TIM6EN_Msk             (0x1U << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */\n#define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk\n#define RCC_APB1ENR_TIM7EN_Pos             (5U)\n#define RCC_APB1ENR_TIM7EN_Msk             (0x1U << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */\n#define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk\n#define RCC_APB1ENR_TIM12EN_Pos            (6U)\n#define RCC_APB1ENR_TIM12EN_Msk            (0x1U << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */\n#define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk\n#define RCC_APB1ENR_TIM13EN_Pos            (7U)\n#define RCC_APB1ENR_TIM13EN_Msk            (0x1U << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */\n#define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk\n#define RCC_APB1ENR_TIM14EN_Pos            (8U)\n#define RCC_APB1ENR_TIM14EN_Msk            (0x1U << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */\n#define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk\n#define RCC_APB1ENR_WWDGEN_Pos             (11U)\n#define RCC_APB1ENR_WWDGEN_Msk             (0x1U << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk\n#define RCC_APB1ENR_SPI2EN_Pos             (14U)\n#define RCC_APB1ENR_SPI2EN_Msk             (0x1U << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */\n#define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk\n#define RCC_APB1ENR_SPI3EN_Pos             (15U)\n#define RCC_APB1ENR_SPI3EN_Msk             (0x1U << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */\n#define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk\n#define RCC_APB1ENR_USART2EN_Pos           (17U)\n#define RCC_APB1ENR_USART2EN_Msk           (0x1U << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */\n#define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk\n#define RCC_APB1ENR_USART3EN_Pos           (18U)\n#define RCC_APB1ENR_USART3EN_Msk           (0x1U << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */\n#define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk\n#define RCC_APB1ENR_UART4EN_Pos            (19U)\n#define RCC_APB1ENR_UART4EN_Msk            (0x1U << RCC_APB1ENR_UART4EN_Pos)   /*!< 0x00080000 */\n#define RCC_APB1ENR_UART4EN                RCC_APB1ENR_UART4EN_Msk\n#define RCC_APB1ENR_UART5EN_Pos            (20U)\n#define RCC_APB1ENR_UART5EN_Msk            (0x1U << RCC_APB1ENR_UART5EN_Pos)   /*!< 0x00100000 */\n#define RCC_APB1ENR_UART5EN                RCC_APB1ENR_UART5EN_Msk\n#define RCC_APB1ENR_I2C1EN_Pos             (21U)\n#define RCC_APB1ENR_I2C1EN_Msk             (0x1U << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */\n#define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk\n#define RCC_APB1ENR_I2C2EN_Pos             (22U)\n#define RCC_APB1ENR_I2C2EN_Msk             (0x1U << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */\n#define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk\n#define RCC_APB1ENR_I2C3EN_Pos             (23U)\n#define RCC_APB1ENR_I2C3EN_Msk             (0x1U << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */\n#define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk\n#define RCC_APB1ENR_CAN1EN_Pos             (25U)\n#define RCC_APB1ENR_CAN1EN_Msk             (0x1U << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */\n#define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk\n#define RCC_APB1ENR_CAN2EN_Pos             (26U)\n#define RCC_APB1ENR_CAN2EN_Msk             (0x1U << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */\n#define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk\n#define RCC_APB1ENR_PWREN_Pos              (28U)\n#define RCC_APB1ENR_PWREN_Msk              (0x1U << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */\n#define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk\n#define RCC_APB1ENR_DACEN_Pos              (29U)\n#define RCC_APB1ENR_DACEN_Msk              (0x1U << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */\n#define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk\n\n/********************  Bit definition for RCC_APB2ENR register  ***************/\n#define RCC_APB2ENR_TIM1EN_Pos             (0U)\n#define RCC_APB2ENR_TIM1EN_Msk             (0x1U << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk\n#define RCC_APB2ENR_TIM8EN_Pos             (1U)\n#define RCC_APB2ENR_TIM8EN_Msk             (0x1U << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk\n#define RCC_APB2ENR_USART1EN_Pos           (4U)\n#define RCC_APB2ENR_USART1EN_Msk           (0x1U << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */\n#define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk\n#define RCC_APB2ENR_USART6EN_Pos           (5U)\n#define RCC_APB2ENR_USART6EN_Msk           (0x1U << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */\n#define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk\n#define RCC_APB2ENR_ADC1EN_Pos             (8U)\n#define RCC_APB2ENR_ADC1EN_Msk             (0x1U << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */\n#define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk\n#define RCC_APB2ENR_ADC2EN_Pos             (9U)\n#define RCC_APB2ENR_ADC2EN_Msk             (0x1U << RCC_APB2ENR_ADC2EN_Pos)    /*!< 0x00000200 */\n#define RCC_APB2ENR_ADC2EN                 RCC_APB2ENR_ADC2EN_Msk\n#define RCC_APB2ENR_ADC3EN_Pos             (10U)\n#define RCC_APB2ENR_ADC3EN_Msk             (0x1U << RCC_APB2ENR_ADC3EN_Pos)    /*!< 0x00000400 */\n#define RCC_APB2ENR_ADC3EN                 RCC_APB2ENR_ADC3EN_Msk\n#define RCC_APB2ENR_SDIOEN_Pos             (11U)\n#define RCC_APB2ENR_SDIOEN_Msk             (0x1U << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk\n#define RCC_APB2ENR_SPI1EN_Pos             (12U)\n#define RCC_APB2ENR_SPI1EN_Msk             (0x1U << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */\n#define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk\n#define RCC_APB2ENR_SYSCFGEN_Pos           (14U)\n#define RCC_APB2ENR_SYSCFGEN_Msk           (0x1U << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */\n#define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk\n#define RCC_APB2ENR_TIM9EN_Pos             (16U)\n#define RCC_APB2ENR_TIM9EN_Msk             (0x1U << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */\n#define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk\n#define RCC_APB2ENR_TIM10EN_Pos            (17U)\n#define RCC_APB2ENR_TIM10EN_Msk            (0x1U << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */\n#define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk\n#define RCC_APB2ENR_TIM11EN_Pos            (18U)\n#define RCC_APB2ENR_TIM11EN_Msk            (0x1U << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */\n#define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk\n\n/********************  Bit definition for RCC_AHB1LPENR register  *************/\n#define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)\n#define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk\n#define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)\n#define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk\n#define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)\n#define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */\n#define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk\n#define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)\n#define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */\n#define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk\n#define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)\n#define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */\n#define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk\n#define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)\n#define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */\n#define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk\n#define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)\n#define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk\n#define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)\n#define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk\n#define RCC_AHB1LPENR_GPIOILPEN_Pos        (8U)\n#define RCC_AHB1LPENR_GPIOILPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */\n#define RCC_AHB1LPENR_GPIOILPEN            RCC_AHB1LPENR_GPIOILPEN_Msk\n#define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)\n#define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */\n#define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk\n#define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)\n#define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */\n#define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk\n#define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)\n#define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */\n#define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk\n#define RCC_AHB1LPENR_SRAM2LPEN_Pos        (17U)\n#define RCC_AHB1LPENR_SRAM2LPEN_Msk        (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */\n#define RCC_AHB1LPENR_SRAM2LPEN            RCC_AHB1LPENR_SRAM2LPEN_Msk\n#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos      (18U)\n#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk      (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */\n#define RCC_AHB1LPENR_BKPSRAMLPEN          RCC_AHB1LPENR_BKPSRAMLPEN_Msk\n#define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)\n#define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk\n#define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)\n#define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk\n\n#define RCC_AHB1LPENR_ETHMACLPEN_Pos       (25U)\n#define RCC_AHB1LPENR_ETHMACLPEN_Msk       (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */\n#define RCC_AHB1LPENR_ETHMACLPEN           RCC_AHB1LPENR_ETHMACLPEN_Msk\n#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos     (26U)\n#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk     (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */\n#define RCC_AHB1LPENR_ETHMACTXLPEN         RCC_AHB1LPENR_ETHMACTXLPEN_Msk\n#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos     (27U)\n#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk     (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */\n#define RCC_AHB1LPENR_ETHMACRXLPEN         RCC_AHB1LPENR_ETHMACRXLPEN_Msk\n#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos    (28U)\n#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk    (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */\n#define RCC_AHB1LPENR_ETHMACPTPLPEN        RCC_AHB1LPENR_ETHMACPTPLPEN_Msk\n#define RCC_AHB1LPENR_OTGHSLPEN_Pos        (29U)\n#define RCC_AHB1LPENR_OTGHSLPEN_Msk        (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */\n#define RCC_AHB1LPENR_OTGHSLPEN            RCC_AHB1LPENR_OTGHSLPEN_Msk\n#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos    (30U)\n#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk    (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */\n#define RCC_AHB1LPENR_OTGHSULPILPEN        RCC_AHB1LPENR_OTGHSULPILPEN_Msk\n\n/********************  Bit definition for RCC_AHB2LPENR register  *************/\n#define RCC_AHB2LPENR_DCMILPEN_Pos         (0U)\n#define RCC_AHB2LPENR_DCMILPEN_Msk         (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB2LPENR_DCMILPEN             RCC_AHB2LPENR_DCMILPEN_Msk\n#define RCC_AHB2LPENR_RNGLPEN_Pos          (6U)\n#define RCC_AHB2LPENR_RNGLPEN_Msk          (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB2LPENR_RNGLPEN              RCC_AHB2LPENR_RNGLPEN_Msk\n#define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)\n#define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk\n\n/********************  Bit definition for RCC_AHB3LPENR register  *************/\n#define RCC_AHB3LPENR_FSMCLPEN_Pos         (0U)\n#define RCC_AHB3LPENR_FSMCLPEN_Msk         (0x1U << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB3LPENR_FSMCLPEN             RCC_AHB3LPENR_FSMCLPEN_Msk\n\n/********************  Bit definition for RCC_APB1LPENR register  *************/\n#define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)\n#define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk\n#define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)\n#define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk\n#define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)\n#define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */\n#define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk\n#define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)\n#define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */\n#define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk\n#define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)\n#define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk\n#define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)\n#define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk\n#define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)\n#define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */\n#define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk\n#define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)\n#define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */\n#define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk\n#define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)\n#define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk\n#define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)\n#define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk\n#define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)\n#define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk\n#define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)\n#define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */\n#define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk\n#define RCC_APB1LPENR_USART2LPEN_Pos       (17U)\n#define RCC_APB1LPENR_USART2LPEN_Msk       (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk\n#define RCC_APB1LPENR_USART3LPEN_Pos       (18U)\n#define RCC_APB1LPENR_USART3LPEN_Msk       (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk\n#define RCC_APB1LPENR_UART4LPEN_Pos        (19U)\n#define RCC_APB1LPENR_UART4LPEN_Msk        (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */\n#define RCC_APB1LPENR_UART4LPEN            RCC_APB1LPENR_UART4LPEN_Msk\n#define RCC_APB1LPENR_UART5LPEN_Pos        (20U)\n#define RCC_APB1LPENR_UART5LPEN_Msk        (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */\n#define RCC_APB1LPENR_UART5LPEN            RCC_APB1LPENR_UART5LPEN_Msk\n#define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)\n#define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk\n#define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)\n#define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk\n#define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)\n#define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */\n#define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk\n#define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)\n#define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */\n#define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk\n#define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)\n#define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */\n#define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk\n#define RCC_APB1LPENR_PWRLPEN_Pos          (28U)\n#define RCC_APB1LPENR_PWRLPEN_Msk          (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */\n#define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk\n#define RCC_APB1LPENR_DACLPEN_Pos          (29U)\n#define RCC_APB1LPENR_DACLPEN_Msk          (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */\n#define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk\n\n/********************  Bit definition for RCC_APB2LPENR register  *************/\n#define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)\n#define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk\n#define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)\n#define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk\n#define RCC_APB2LPENR_USART1LPEN_Pos       (4U)\n#define RCC_APB2LPENR_USART1LPEN_Msk       (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk\n#define RCC_APB2LPENR_USART6LPEN_Pos       (5U)\n#define RCC_APB2LPENR_USART6LPEN_Msk       (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk\n#define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)\n#define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk\n#define RCC_APB2LPENR_ADC2LPEN_Pos         (9U)\n#define RCC_APB2LPENR_ADC2LPEN_Msk         (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */\n#define RCC_APB2LPENR_ADC2LPEN             RCC_APB2LPENR_ADC2LPEN_Msk\n#define RCC_APB2LPENR_ADC3LPEN_Pos         (10U)\n#define RCC_APB2LPENR_ADC3LPEN_Msk         (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */\n#define RCC_APB2LPENR_ADC3LPEN             RCC_APB2LPENR_ADC3LPEN_Msk\n#define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)\n#define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk\n#define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)\n#define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */\n#define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk\n#define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)\n#define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk\n#define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)\n#define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */\n#define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk\n#define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)\n#define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk\n#define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)\n#define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk\n\n/********************  Bit definition for RCC_BDCR register  ******************/\n#define RCC_BDCR_LSEON_Pos                 (0U)\n#define RCC_BDCR_LSEON_Msk                 (0x1U << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */\n#define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk\n#define RCC_BDCR_LSERDY_Pos                (1U)\n#define RCC_BDCR_LSERDY_Msk                (0x1U << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */\n#define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk\n#define RCC_BDCR_LSEBYP_Pos                (2U)\n#define RCC_BDCR_LSEBYP_Msk                (0x1U << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */\n#define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk\n\n#define RCC_BDCR_RTCSEL_Pos                (8U)\n#define RCC_BDCR_RTCSEL_Msk                (0x3U << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */\n#define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk\n#define RCC_BDCR_RTCSEL_0                  (0x1U << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */\n#define RCC_BDCR_RTCSEL_1                  (0x2U << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */\n\n#define RCC_BDCR_RTCEN_Pos                 (15U)\n#define RCC_BDCR_RTCEN_Msk                 (0x1U << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */\n#define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk\n#define RCC_BDCR_BDRST_Pos                 (16U)\n#define RCC_BDCR_BDRST_Msk                 (0x1U << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */\n#define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk\n\n/********************  Bit definition for RCC_CSR register  *******************/\n#define RCC_CSR_LSION_Pos                  (0U)\n#define RCC_CSR_LSION_Msk                  (0x1U << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */\n#define RCC_CSR_LSION                      RCC_CSR_LSION_Msk\n#define RCC_CSR_LSIRDY_Pos                 (1U)\n#define RCC_CSR_LSIRDY_Msk                 (0x1U << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */\n#define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk\n#define RCC_CSR_RMVF_Pos                   (24U)\n#define RCC_CSR_RMVF_Msk                   (0x1U << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */\n#define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk\n#define RCC_CSR_BORRSTF_Pos                (25U)\n#define RCC_CSR_BORRSTF_Msk                (0x1U << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */\n#define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk\n#define RCC_CSR_PINRSTF_Pos                (26U)\n#define RCC_CSR_PINRSTF_Msk                (0x1U << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */\n#define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk\n#define RCC_CSR_PORRSTF_Pos                (27U)\n#define RCC_CSR_PORRSTF_Msk                (0x1U << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */\n#define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk\n#define RCC_CSR_SFTRSTF_Pos                (28U)\n#define RCC_CSR_SFTRSTF_Msk                (0x1U << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */\n#define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk\n#define RCC_CSR_IWDGRSTF_Pos               (29U)\n#define RCC_CSR_IWDGRSTF_Msk               (0x1U << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */\n#define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk\n#define RCC_CSR_WWDGRSTF_Pos               (30U)\n#define RCC_CSR_WWDGRSTF_Msk               (0x1U << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */\n#define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk\n#define RCC_CSR_LPWRRSTF_Pos               (31U)\n#define RCC_CSR_LPWRRSTF_Msk               (0x1U << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */\n#define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk\n/* Legacy defines */\n#define RCC_CSR_PADRSTF                    RCC_CSR_PINRSTF\n#define RCC_CSR_WDGRSTF                    RCC_CSR_IWDGRSTF\n\n/********************  Bit definition for RCC_SSCGR register  *****************/\n#define RCC_SSCGR_MODPER_Pos               (0U)\n#define RCC_SSCGR_MODPER_Msk               (0x1FFFU << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */\n#define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk\n#define RCC_SSCGR_INCSTEP_Pos              (13U)\n#define RCC_SSCGR_INCSTEP_Msk              (0x7FFFU << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */\n#define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk\n#define RCC_SSCGR_SPREADSEL_Pos            (30U)\n#define RCC_SSCGR_SPREADSEL_Msk            (0x1U << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */\n#define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk\n#define RCC_SSCGR_SSCGEN_Pos               (31U)\n#define RCC_SSCGR_SSCGEN_Msk               (0x1U << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */\n#define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk\n\n/********************  Bit definition for RCC_PLLI2SCFGR register  ************/\n#define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)\n#define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */\n#define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk\n#define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */\n#define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */\n#define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */\n#define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */\n#define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */\n#define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */\n#define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */\n\n#define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)\n#define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk\n#define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    RNG                                     */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RNG_CR register  *******************/\n#define RNG_CR_RNGEN_Pos    (2U)\n#define RNG_CR_RNGEN_Msk    (0x1U << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */\n#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk\n#define RNG_CR_IE_Pos       (3U)\n#define RNG_CR_IE_Msk       (0x1U << RNG_CR_IE_Pos)                            /*!< 0x00000008 */\n#define RNG_CR_IE           RNG_CR_IE_Msk\n\n/********************  Bits definition for RNG_SR register  *******************/\n#define RNG_SR_DRDY_Pos     (0U)\n#define RNG_SR_DRDY_Msk     (0x1U << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */\n#define RNG_SR_DRDY         RNG_SR_DRDY_Msk\n#define RNG_SR_CECS_Pos     (1U)\n#define RNG_SR_CECS_Msk     (0x1U << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */\n#define RNG_SR_CECS         RNG_SR_CECS_Msk\n#define RNG_SR_SECS_Pos     (2U)\n#define RNG_SR_SECS_Msk     (0x1U << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */\n#define RNG_SR_SECS         RNG_SR_SECS_Msk\n#define RNG_SR_CEIS_Pos     (5U)\n#define RNG_SR_CEIS_Msk     (0x1U << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */\n#define RNG_SR_CEIS         RNG_SR_CEIS_Msk\n#define RNG_SR_SEIS_Pos     (6U)\n#define RNG_SR_SEIS_Msk     (0x1U << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */\n#define RNG_SR_SEIS         RNG_SR_SEIS_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Real-Time Clock (RTC)                            */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions  (not present on all devices in the STM32F4 serie)\n */\n#define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */\n#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */\n/********************  Bits definition for RTC_TR register  *******************/\n#define RTC_TR_PM_Pos                 (22U)\n#define RTC_TR_PM_Msk                 (0x1U << RTC_TR_PM_Pos)                  /*!< 0x00400000 */\n#define RTC_TR_PM                     RTC_TR_PM_Msk\n#define RTC_TR_HT_Pos                 (20U)\n#define RTC_TR_HT_Msk                 (0x3U << RTC_TR_HT_Pos)                  /*!< 0x00300000 */\n#define RTC_TR_HT                     RTC_TR_HT_Msk\n#define RTC_TR_HT_0                   (0x1U << RTC_TR_HT_Pos)                  /*!< 0x00100000 */\n#define RTC_TR_HT_1                   (0x2U << RTC_TR_HT_Pos)                  /*!< 0x00200000 */\n#define RTC_TR_HU_Pos                 (16U)\n#define RTC_TR_HU_Msk                 (0xFU << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */\n#define RTC_TR_HU                     RTC_TR_HU_Msk\n#define RTC_TR_HU_0                   (0x1U << RTC_TR_HU_Pos)                  /*!< 0x00010000 */\n#define RTC_TR_HU_1                   (0x2U << RTC_TR_HU_Pos)                  /*!< 0x00020000 */\n#define RTC_TR_HU_2                   (0x4U << RTC_TR_HU_Pos)                  /*!< 0x00040000 */\n#define RTC_TR_HU_3                   (0x8U << RTC_TR_HU_Pos)                  /*!< 0x00080000 */\n#define RTC_TR_MNT_Pos                (12U)\n#define RTC_TR_MNT_Msk                (0x7U << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */\n#define RTC_TR_MNT                    RTC_TR_MNT_Msk\n#define RTC_TR_MNT_0                  (0x1U << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */\n#define RTC_TR_MNT_1                  (0x2U << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */\n#define RTC_TR_MNT_2                  (0x4U << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */\n#define RTC_TR_MNU_Pos                (8U)\n#define RTC_TR_MNU_Msk                (0xFU << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */\n#define RTC_TR_MNU                    RTC_TR_MNU_Msk\n#define RTC_TR_MNU_0                  (0x1U << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */\n#define RTC_TR_MNU_1                  (0x2U << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */\n#define RTC_TR_MNU_2                  (0x4U << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */\n#define RTC_TR_MNU_3                  (0x8U << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */\n#define RTC_TR_ST_Pos                 (4U)\n#define RTC_TR_ST_Msk                 (0x7U << RTC_TR_ST_Pos)                  /*!< 0x00000070 */\n#define RTC_TR_ST                     RTC_TR_ST_Msk\n#define RTC_TR_ST_0                   (0x1U << RTC_TR_ST_Pos)                  /*!< 0x00000010 */\n#define RTC_TR_ST_1                   (0x2U << RTC_TR_ST_Pos)                  /*!< 0x00000020 */\n#define RTC_TR_ST_2                   (0x4U << RTC_TR_ST_Pos)                  /*!< 0x00000040 */\n#define RTC_TR_SU_Pos                 (0U)\n#define RTC_TR_SU_Msk                 (0xFU << RTC_TR_SU_Pos)                  /*!< 0x0000000F */\n#define RTC_TR_SU                     RTC_TR_SU_Msk\n#define RTC_TR_SU_0                   (0x1U << RTC_TR_SU_Pos)                  /*!< 0x00000001 */\n#define RTC_TR_SU_1                   (0x2U << RTC_TR_SU_Pos)                  /*!< 0x00000002 */\n#define RTC_TR_SU_2                   (0x4U << RTC_TR_SU_Pos)                  /*!< 0x00000004 */\n#define RTC_TR_SU_3                   (0x8U << RTC_TR_SU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_DR register  *******************/\n#define RTC_DR_YT_Pos                 (20U)\n#define RTC_DR_YT_Msk                 (0xFU << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */\n#define RTC_DR_YT                     RTC_DR_YT_Msk\n#define RTC_DR_YT_0                   (0x1U << RTC_DR_YT_Pos)                  /*!< 0x00100000 */\n#define RTC_DR_YT_1                   (0x2U << RTC_DR_YT_Pos)                  /*!< 0x00200000 */\n#define RTC_DR_YT_2                   (0x4U << RTC_DR_YT_Pos)                  /*!< 0x00400000 */\n#define RTC_DR_YT_3                   (0x8U << RTC_DR_YT_Pos)                  /*!< 0x00800000 */\n#define RTC_DR_YU_Pos                 (16U)\n#define RTC_DR_YU_Msk                 (0xFU << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */\n#define RTC_DR_YU                     RTC_DR_YU_Msk\n#define RTC_DR_YU_0                   (0x1U << RTC_DR_YU_Pos)                  /*!< 0x00010000 */\n#define RTC_DR_YU_1                   (0x2U << RTC_DR_YU_Pos)                  /*!< 0x00020000 */\n#define RTC_DR_YU_2                   (0x4U << RTC_DR_YU_Pos)                  /*!< 0x00040000 */\n#define RTC_DR_YU_3                   (0x8U << RTC_DR_YU_Pos)                  /*!< 0x00080000 */\n#define RTC_DR_WDU_Pos                (13U)\n#define RTC_DR_WDU_Msk                (0x7U << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */\n#define RTC_DR_WDU                    RTC_DR_WDU_Msk\n#define RTC_DR_WDU_0                  (0x1U << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */\n#define RTC_DR_WDU_1                  (0x2U << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */\n#define RTC_DR_WDU_2                  (0x4U << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */\n#define RTC_DR_MT_Pos                 (12U)\n#define RTC_DR_MT_Msk                 (0x1U << RTC_DR_MT_Pos)                  /*!< 0x00001000 */\n#define RTC_DR_MT                     RTC_DR_MT_Msk\n#define RTC_DR_MU_Pos                 (8U)\n#define RTC_DR_MU_Msk                 (0xFU << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */\n#define RTC_DR_MU                     RTC_DR_MU_Msk\n#define RTC_DR_MU_0                   (0x1U << RTC_DR_MU_Pos)                  /*!< 0x00000100 */\n#define RTC_DR_MU_1                   (0x2U << RTC_DR_MU_Pos)                  /*!< 0x00000200 */\n#define RTC_DR_MU_2                   (0x4U << RTC_DR_MU_Pos)                  /*!< 0x00000400 */\n#define RTC_DR_MU_3                   (0x8U << RTC_DR_MU_Pos)                  /*!< 0x00000800 */\n#define RTC_DR_DT_Pos                 (4U)\n#define RTC_DR_DT_Msk                 (0x3U << RTC_DR_DT_Pos)                  /*!< 0x00000030 */\n#define RTC_DR_DT                     RTC_DR_DT_Msk\n#define RTC_DR_DT_0                   (0x1U << RTC_DR_DT_Pos)                  /*!< 0x00000010 */\n#define RTC_DR_DT_1                   (0x2U << RTC_DR_DT_Pos)                  /*!< 0x00000020 */\n#define RTC_DR_DU_Pos                 (0U)\n#define RTC_DR_DU_Msk                 (0xFU << RTC_DR_DU_Pos)                  /*!< 0x0000000F */\n#define RTC_DR_DU                     RTC_DR_DU_Msk\n#define RTC_DR_DU_0                   (0x1U << RTC_DR_DU_Pos)                  /*!< 0x00000001 */\n#define RTC_DR_DU_1                   (0x2U << RTC_DR_DU_Pos)                  /*!< 0x00000002 */\n#define RTC_DR_DU_2                   (0x4U << RTC_DR_DU_Pos)                  /*!< 0x00000004 */\n#define RTC_DR_DU_3                   (0x8U << RTC_DR_DU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_CR register  *******************/\n#define RTC_CR_COE_Pos                (23U)\n#define RTC_CR_COE_Msk                (0x1U << RTC_CR_COE_Pos)                 /*!< 0x00800000 */\n#define RTC_CR_COE                    RTC_CR_COE_Msk\n#define RTC_CR_OSEL_Pos               (21U)\n#define RTC_CR_OSEL_Msk               (0x3U << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */\n#define RTC_CR_OSEL                   RTC_CR_OSEL_Msk\n#define RTC_CR_OSEL_0                 (0x1U << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */\n#define RTC_CR_OSEL_1                 (0x2U << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */\n#define RTC_CR_POL_Pos                (20U)\n#define RTC_CR_POL_Msk                (0x1U << RTC_CR_POL_Pos)                 /*!< 0x00100000 */\n#define RTC_CR_POL                    RTC_CR_POL_Msk\n#define RTC_CR_COSEL_Pos              (19U)\n#define RTC_CR_COSEL_Msk              (0x1U << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */\n#define RTC_CR_COSEL                  RTC_CR_COSEL_Msk\n#define RTC_CR_BKP_Pos                 (18U)\n#define RTC_CR_BKP_Msk                 (0x1U << RTC_CR_BKP_Pos)                /*!< 0x00040000 */\n#define RTC_CR_BKP                     RTC_CR_BKP_Msk\n#define RTC_CR_SUB1H_Pos              (17U)\n#define RTC_CR_SUB1H_Msk              (0x1U << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */\n#define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk\n#define RTC_CR_ADD1H_Pos              (16U)\n#define RTC_CR_ADD1H_Msk              (0x1U << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */\n#define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk\n#define RTC_CR_TSIE_Pos               (15U)\n#define RTC_CR_TSIE_Msk               (0x1U << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */\n#define RTC_CR_TSIE                   RTC_CR_TSIE_Msk\n#define RTC_CR_WUTIE_Pos              (14U)\n#define RTC_CR_WUTIE_Msk              (0x1U << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */\n#define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk\n#define RTC_CR_ALRBIE_Pos             (13U)\n#define RTC_CR_ALRBIE_Msk             (0x1U << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */\n#define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk\n#define RTC_CR_ALRAIE_Pos             (12U)\n#define RTC_CR_ALRAIE_Msk             (0x1U << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */\n#define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk\n#define RTC_CR_TSE_Pos                (11U)\n#define RTC_CR_TSE_Msk                (0x1U << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */\n#define RTC_CR_TSE                    RTC_CR_TSE_Msk\n#define RTC_CR_WUTE_Pos               (10U)\n#define RTC_CR_WUTE_Msk               (0x1U << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */\n#define RTC_CR_WUTE                   RTC_CR_WUTE_Msk\n#define RTC_CR_ALRBE_Pos              (9U)\n#define RTC_CR_ALRBE_Msk              (0x1U << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */\n#define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk\n#define RTC_CR_ALRAE_Pos              (8U)\n#define RTC_CR_ALRAE_Msk              (0x1U << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */\n#define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk\n#define RTC_CR_DCE_Pos                (7U)\n#define RTC_CR_DCE_Msk                (0x1U << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */\n#define RTC_CR_DCE                    RTC_CR_DCE_Msk\n#define RTC_CR_FMT_Pos                (6U)\n#define RTC_CR_FMT_Msk                (0x1U << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */\n#define RTC_CR_FMT                    RTC_CR_FMT_Msk\n#define RTC_CR_BYPSHAD_Pos            (5U)\n#define RTC_CR_BYPSHAD_Msk            (0x1U << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */\n#define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk\n#define RTC_CR_REFCKON_Pos            (4U)\n#define RTC_CR_REFCKON_Msk            (0x1U << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */\n#define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk\n#define RTC_CR_TSEDGE_Pos             (3U)\n#define RTC_CR_TSEDGE_Msk             (0x1U << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */\n#define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk\n#define RTC_CR_WUCKSEL_Pos            (0U)\n#define RTC_CR_WUCKSEL_Msk            (0x7U << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */\n#define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk\n#define RTC_CR_WUCKSEL_0              (0x1U << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */\n#define RTC_CR_WUCKSEL_1              (0x2U << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */\n#define RTC_CR_WUCKSEL_2              (0x4U << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */\n\n/* Legacy defines */\n#define RTC_CR_BCK                     RTC_CR_BKP\n\n/********************  Bits definition for RTC_ISR register  ******************/\n#define RTC_ISR_RECALPF_Pos           (16U)\n#define RTC_ISR_RECALPF_Msk           (0x1U << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */\n#define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk\n#define RTC_ISR_TAMP1F_Pos            (13U)\n#define RTC_ISR_TAMP1F_Msk            (0x1U << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */\n#define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk\n#define RTC_ISR_TAMP2F_Pos            (14U)\n#define RTC_ISR_TAMP2F_Msk            (0x1U << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */\n#define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk\n#define RTC_ISR_TSOVF_Pos             (12U)\n#define RTC_ISR_TSOVF_Msk             (0x1U << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */\n#define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk\n#define RTC_ISR_TSF_Pos               (11U)\n#define RTC_ISR_TSF_Msk               (0x1U << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */\n#define RTC_ISR_TSF                   RTC_ISR_TSF_Msk\n#define RTC_ISR_WUTF_Pos              (10U)\n#define RTC_ISR_WUTF_Msk              (0x1U << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */\n#define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk\n#define RTC_ISR_ALRBF_Pos             (9U)\n#define RTC_ISR_ALRBF_Msk             (0x1U << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */\n#define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk\n#define RTC_ISR_ALRAF_Pos             (8U)\n#define RTC_ISR_ALRAF_Msk             (0x1U << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */\n#define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk\n#define RTC_ISR_INIT_Pos              (7U)\n#define RTC_ISR_INIT_Msk              (0x1U << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */\n#define RTC_ISR_INIT                  RTC_ISR_INIT_Msk\n#define RTC_ISR_INITF_Pos             (6U)\n#define RTC_ISR_INITF_Msk             (0x1U << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */\n#define RTC_ISR_INITF                 RTC_ISR_INITF_Msk\n#define RTC_ISR_RSF_Pos               (5U)\n#define RTC_ISR_RSF_Msk               (0x1U << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */\n#define RTC_ISR_RSF                   RTC_ISR_RSF_Msk\n#define RTC_ISR_INITS_Pos             (4U)\n#define RTC_ISR_INITS_Msk             (0x1U << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */\n#define RTC_ISR_INITS                 RTC_ISR_INITS_Msk\n#define RTC_ISR_SHPF_Pos              (3U)\n#define RTC_ISR_SHPF_Msk              (0x1U << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */\n#define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk\n#define RTC_ISR_WUTWF_Pos             (2U)\n#define RTC_ISR_WUTWF_Msk             (0x1U << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */\n#define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk\n#define RTC_ISR_ALRBWF_Pos            (1U)\n#define RTC_ISR_ALRBWF_Msk            (0x1U << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */\n#define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk\n#define RTC_ISR_ALRAWF_Pos            (0U)\n#define RTC_ISR_ALRAWF_Msk            (0x1U << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */\n#define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk\n\n/********************  Bits definition for RTC_PRER register  *****************/\n#define RTC_PRER_PREDIV_A_Pos         (16U)\n#define RTC_PRER_PREDIV_A_Msk         (0x7FU << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */\n#define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk\n#define RTC_PRER_PREDIV_S_Pos         (0U)\n#define RTC_PRER_PREDIV_S_Msk         (0x7FFFU << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */\n#define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk\n\n/********************  Bits definition for RTC_WUTR register  *****************/\n#define RTC_WUTR_WUT_Pos              (0U)\n#define RTC_WUTR_WUT_Msk              (0xFFFFU << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */\n#define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk\n\n/********************  Bits definition for RTC_CALIBR register  ***************/\n#define RTC_CALIBR_DCS_Pos            (7U)\n#define RTC_CALIBR_DCS_Msk            (0x1U << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */\n#define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk\n#define RTC_CALIBR_DC_Pos             (0U)\n#define RTC_CALIBR_DC_Msk             (0x1FU << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */\n#define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk\n\n/********************  Bits definition for RTC_ALRMAR register  ***************/\n#define RTC_ALRMAR_MSK4_Pos           (31U)\n#define RTC_ALRMAR_MSK4_Msk           (0x1U << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk\n#define RTC_ALRMAR_WDSEL_Pos          (30U)\n#define RTC_ALRMAR_WDSEL_Msk          (0x1U << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk\n#define RTC_ALRMAR_DT_Pos             (28U)\n#define RTC_ALRMAR_DT_Msk             (0x3U << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk\n#define RTC_ALRMAR_DT_0               (0x1U << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMAR_DT_1               (0x2U << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMAR_DU_Pos             (24U)\n#define RTC_ALRMAR_DU_Msk             (0xFU << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk\n#define RTC_ALRMAR_DU_0               (0x1U << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMAR_DU_1               (0x2U << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMAR_DU_2               (0x4U << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMAR_DU_3               (0x8U << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMAR_MSK3_Pos           (23U)\n#define RTC_ALRMAR_MSK3_Msk           (0x1U << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk\n#define RTC_ALRMAR_PM_Pos             (22U)\n#define RTC_ALRMAR_PM_Msk             (0x1U << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk\n#define RTC_ALRMAR_HT_Pos             (20U)\n#define RTC_ALRMAR_HT_Msk             (0x3U << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk\n#define RTC_ALRMAR_HT_0               (0x1U << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMAR_HT_1               (0x2U << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMAR_HU_Pos             (16U)\n#define RTC_ALRMAR_HU_Msk             (0xFU << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk\n#define RTC_ALRMAR_HU_0               (0x1U << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMAR_HU_1               (0x2U << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMAR_HU_2               (0x4U << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMAR_HU_3               (0x8U << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMAR_MSK2_Pos           (15U)\n#define RTC_ALRMAR_MSK2_Msk           (0x1U << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk\n#define RTC_ALRMAR_MNT_Pos            (12U)\n#define RTC_ALRMAR_MNT_Msk            (0x7U << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk\n#define RTC_ALRMAR_MNT_0              (0x1U << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMAR_MNT_1              (0x2U << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMAR_MNT_2              (0x4U << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMAR_MNU_Pos            (8U)\n#define RTC_ALRMAR_MNU_Msk            (0xFU << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk\n#define RTC_ALRMAR_MNU_0              (0x1U << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMAR_MNU_1              (0x2U << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMAR_MNU_2              (0x4U << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMAR_MNU_3              (0x8U << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMAR_MSK1_Pos           (7U)\n#define RTC_ALRMAR_MSK1_Msk           (0x1U << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk\n#define RTC_ALRMAR_ST_Pos             (4U)\n#define RTC_ALRMAR_ST_Msk             (0x7U << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk\n#define RTC_ALRMAR_ST_0               (0x1U << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMAR_ST_1               (0x2U << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMAR_ST_2               (0x4U << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMAR_SU_Pos             (0U)\n#define RTC_ALRMAR_SU_Msk             (0xFU << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk\n#define RTC_ALRMAR_SU_0               (0x1U << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMAR_SU_1               (0x2U << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMAR_SU_2               (0x4U << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMAR_SU_3               (0x8U << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_ALRMBR register  ***************/\n#define RTC_ALRMBR_MSK4_Pos           (31U)\n#define RTC_ALRMBR_MSK4_Msk           (0x1U << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk\n#define RTC_ALRMBR_WDSEL_Pos          (30U)\n#define RTC_ALRMBR_WDSEL_Msk          (0x1U << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk\n#define RTC_ALRMBR_DT_Pos             (28U)\n#define RTC_ALRMBR_DT_Msk             (0x3U << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk\n#define RTC_ALRMBR_DT_0               (0x1U << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMBR_DT_1               (0x2U << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMBR_DU_Pos             (24U)\n#define RTC_ALRMBR_DU_Msk             (0xFU << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk\n#define RTC_ALRMBR_DU_0               (0x1U << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMBR_DU_1               (0x2U << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMBR_DU_2               (0x4U << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMBR_DU_3               (0x8U << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMBR_MSK3_Pos           (23U)\n#define RTC_ALRMBR_MSK3_Msk           (0x1U << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk\n#define RTC_ALRMBR_PM_Pos             (22U)\n#define RTC_ALRMBR_PM_Msk             (0x1U << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk\n#define RTC_ALRMBR_HT_Pos             (20U)\n#define RTC_ALRMBR_HT_Msk             (0x3U << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk\n#define RTC_ALRMBR_HT_0               (0x1U << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMBR_HT_1               (0x2U << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMBR_HU_Pos             (16U)\n#define RTC_ALRMBR_HU_Msk             (0xFU << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk\n#define RTC_ALRMBR_HU_0               (0x1U << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMBR_HU_1               (0x2U << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMBR_HU_2               (0x4U << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMBR_HU_3               (0x8U << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMBR_MSK2_Pos           (15U)\n#define RTC_ALRMBR_MSK2_Msk           (0x1U << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk\n#define RTC_ALRMBR_MNT_Pos            (12U)\n#define RTC_ALRMBR_MNT_Msk            (0x7U << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk\n#define RTC_ALRMBR_MNT_0              (0x1U << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMBR_MNT_1              (0x2U << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMBR_MNT_2              (0x4U << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMBR_MNU_Pos            (8U)\n#define RTC_ALRMBR_MNU_Msk            (0xFU << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk\n#define RTC_ALRMBR_MNU_0              (0x1U << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMBR_MNU_1              (0x2U << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMBR_MNU_2              (0x4U << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMBR_MNU_3              (0x8U << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMBR_MSK1_Pos           (7U)\n#define RTC_ALRMBR_MSK1_Msk           (0x1U << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk\n#define RTC_ALRMBR_ST_Pos             (4U)\n#define RTC_ALRMBR_ST_Msk             (0x7U << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk\n#define RTC_ALRMBR_ST_0               (0x1U << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMBR_ST_1               (0x2U << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMBR_ST_2               (0x4U << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMBR_SU_Pos             (0U)\n#define RTC_ALRMBR_SU_Msk             (0xFU << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk\n#define RTC_ALRMBR_SU_0               (0x1U << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMBR_SU_1               (0x2U << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMBR_SU_2               (0x4U << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMBR_SU_3               (0x8U << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_WPR register  ******************/\n#define RTC_WPR_KEY_Pos               (0U)\n#define RTC_WPR_KEY_Msk               (0xFFU << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */\n#define RTC_WPR_KEY                   RTC_WPR_KEY_Msk\n\n/********************  Bits definition for RTC_SSR register  ******************/\n#define RTC_SSR_SS_Pos                (0U)\n#define RTC_SSR_SS_Msk                (0xFFFFU << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */\n#define RTC_SSR_SS                    RTC_SSR_SS_Msk\n\n/********************  Bits definition for RTC_SHIFTR register  ***************/\n#define RTC_SHIFTR_SUBFS_Pos          (0U)\n#define RTC_SHIFTR_SUBFS_Msk          (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */\n#define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk\n#define RTC_SHIFTR_ADD1S_Pos          (31U)\n#define RTC_SHIFTR_ADD1S_Msk          (0x1U << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */\n#define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk\n\n/********************  Bits definition for RTC_TSTR register  *****************/\n#define RTC_TSTR_PM_Pos               (22U)\n#define RTC_TSTR_PM_Msk               (0x1U << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */\n#define RTC_TSTR_PM                   RTC_TSTR_PM_Msk\n#define RTC_TSTR_HT_Pos               (20U)\n#define RTC_TSTR_HT_Msk               (0x3U << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */\n#define RTC_TSTR_HT                   RTC_TSTR_HT_Msk\n#define RTC_TSTR_HT_0                 (0x1U << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */\n#define RTC_TSTR_HT_1                 (0x2U << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */\n#define RTC_TSTR_HU_Pos               (16U)\n#define RTC_TSTR_HU_Msk               (0xFU << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */\n#define RTC_TSTR_HU                   RTC_TSTR_HU_Msk\n#define RTC_TSTR_HU_0                 (0x1U << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */\n#define RTC_TSTR_HU_1                 (0x2U << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */\n#define RTC_TSTR_HU_2                 (0x4U << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */\n#define RTC_TSTR_HU_3                 (0x8U << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */\n#define RTC_TSTR_MNT_Pos              (12U)\n#define RTC_TSTR_MNT_Msk              (0x7U << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */\n#define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk\n#define RTC_TSTR_MNT_0                (0x1U << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */\n#define RTC_TSTR_MNT_1                (0x2U << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */\n#define RTC_TSTR_MNT_2                (0x4U << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */\n#define RTC_TSTR_MNU_Pos              (8U)\n#define RTC_TSTR_MNU_Msk              (0xFU << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */\n#define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk\n#define RTC_TSTR_MNU_0                (0x1U << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */\n#define RTC_TSTR_MNU_1                (0x2U << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */\n#define RTC_TSTR_MNU_2                (0x4U << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */\n#define RTC_TSTR_MNU_3                (0x8U << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */\n#define RTC_TSTR_ST_Pos               (4U)\n#define RTC_TSTR_ST_Msk               (0x7U << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */\n#define RTC_TSTR_ST                   RTC_TSTR_ST_Msk\n#define RTC_TSTR_ST_0                 (0x1U << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */\n#define RTC_TSTR_ST_1                 (0x2U << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */\n#define RTC_TSTR_ST_2                 (0x4U << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */\n#define RTC_TSTR_SU_Pos               (0U)\n#define RTC_TSTR_SU_Msk               (0xFU << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */\n#define RTC_TSTR_SU                   RTC_TSTR_SU_Msk\n#define RTC_TSTR_SU_0                 (0x1U << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */\n#define RTC_TSTR_SU_1                 (0x2U << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */\n#define RTC_TSTR_SU_2                 (0x4U << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */\n#define RTC_TSTR_SU_3                 (0x8U << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSDR register  *****************/\n#define RTC_TSDR_WDU_Pos              (13U)\n#define RTC_TSDR_WDU_Msk              (0x7U << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */\n#define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk\n#define RTC_TSDR_WDU_0                (0x1U << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */\n#define RTC_TSDR_WDU_1                (0x2U << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */\n#define RTC_TSDR_WDU_2                (0x4U << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */\n#define RTC_TSDR_MT_Pos               (12U)\n#define RTC_TSDR_MT_Msk               (0x1U << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */\n#define RTC_TSDR_MT                   RTC_TSDR_MT_Msk\n#define RTC_TSDR_MU_Pos               (8U)\n#define RTC_TSDR_MU_Msk               (0xFU << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */\n#define RTC_TSDR_MU                   RTC_TSDR_MU_Msk\n#define RTC_TSDR_MU_0                 (0x1U << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */\n#define RTC_TSDR_MU_1                 (0x2U << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */\n#define RTC_TSDR_MU_2                 (0x4U << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */\n#define RTC_TSDR_MU_3                 (0x8U << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */\n#define RTC_TSDR_DT_Pos               (4U)\n#define RTC_TSDR_DT_Msk               (0x3U << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */\n#define RTC_TSDR_DT                   RTC_TSDR_DT_Msk\n#define RTC_TSDR_DT_0                 (0x1U << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */\n#define RTC_TSDR_DT_1                 (0x2U << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */\n#define RTC_TSDR_DU_Pos               (0U)\n#define RTC_TSDR_DU_Msk               (0xFU << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */\n#define RTC_TSDR_DU                   RTC_TSDR_DU_Msk\n#define RTC_TSDR_DU_0                 (0x1U << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */\n#define RTC_TSDR_DU_1                 (0x2U << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */\n#define RTC_TSDR_DU_2                 (0x4U << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */\n#define RTC_TSDR_DU_3                 (0x8U << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSSSR register  ****************/\n#define RTC_TSSSR_SS_Pos              (0U)\n#define RTC_TSSSR_SS_Msk              (0xFFFFU << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */\n#define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk\n\n/********************  Bits definition for RTC_CAL register  *****************/\n#define RTC_CALR_CALP_Pos             (15U)\n#define RTC_CALR_CALP_Msk             (0x1U << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */\n#define RTC_CALR_CALP                 RTC_CALR_CALP_Msk\n#define RTC_CALR_CALW8_Pos            (14U)\n#define RTC_CALR_CALW8_Msk            (0x1U << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */\n#define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk\n#define RTC_CALR_CALW16_Pos           (13U)\n#define RTC_CALR_CALW16_Msk           (0x1U << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */\n#define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk\n#define RTC_CALR_CALM_Pos             (0U)\n#define RTC_CALR_CALM_Msk             (0x1FFU << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */\n#define RTC_CALR_CALM                 RTC_CALR_CALM_Msk\n#define RTC_CALR_CALM_0               (0x001U << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */\n#define RTC_CALR_CALM_1               (0x002U << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */\n#define RTC_CALR_CALM_2               (0x004U << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */\n#define RTC_CALR_CALM_3               (0x008U << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */\n#define RTC_CALR_CALM_4               (0x010U << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */\n#define RTC_CALR_CALM_5               (0x020U << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */\n#define RTC_CALR_CALM_6               (0x040U << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */\n#define RTC_CALR_CALM_7               (0x080U << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */\n#define RTC_CALR_CALM_8               (0x100U << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */\n\n/********************  Bits definition for RTC_TAFCR register  ****************/\n#define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)\n#define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */\n#define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk\n#define RTC_TAFCR_TSINSEL_Pos         (17U)\n#define RTC_TAFCR_TSINSEL_Msk         (0x1U << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */\n#define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk\n#define RTC_TAFCR_TAMP1INSEL_Pos      (16U)\n#define RTC_TAFCR_TAMP1INSEL_Msk      (0x1U << RTC_TAFCR_TAMP1INSEL_Pos)        /*!< 0x00010000 */\n#define RTC_TAFCR_TAMP1INSEL          RTC_TAFCR_TAMP1INSEL_Msk\n#define RTC_TAFCR_TAMPPUDIS_Pos       (15U)\n#define RTC_TAFCR_TAMPPUDIS_Msk       (0x1U << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */\n#define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk\n#define RTC_TAFCR_TAMPPRCH_Pos        (13U)\n#define RTC_TAFCR_TAMPPRCH_Msk        (0x3U << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */\n#define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk\n#define RTC_TAFCR_TAMPPRCH_0          (0x1U << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */\n#define RTC_TAFCR_TAMPPRCH_1          (0x2U << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */\n#define RTC_TAFCR_TAMPFLT_Pos         (11U)\n#define RTC_TAFCR_TAMPFLT_Msk         (0x3U << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */\n#define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk\n#define RTC_TAFCR_TAMPFLT_0           (0x1U << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */\n#define RTC_TAFCR_TAMPFLT_1           (0x2U << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */\n#define RTC_TAFCR_TAMPFREQ_Pos        (8U)\n#define RTC_TAFCR_TAMPFREQ_Msk        (0x7U << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */\n#define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk\n#define RTC_TAFCR_TAMPFREQ_0          (0x1U << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */\n#define RTC_TAFCR_TAMPFREQ_1          (0x2U << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */\n#define RTC_TAFCR_TAMPFREQ_2          (0x4U << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */\n#define RTC_TAFCR_TAMPTS_Pos          (7U)\n#define RTC_TAFCR_TAMPTS_Msk          (0x1U << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */\n#define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk\n#define RTC_TAFCR_TAMP2TRG_Pos        (4U)\n#define RTC_TAFCR_TAMP2TRG_Msk        (0x1U << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */\n#define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk\n#define RTC_TAFCR_TAMP2E_Pos          (3U)\n#define RTC_TAFCR_TAMP2E_Msk          (0x1U << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */\n#define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk\n#define RTC_TAFCR_TAMPIE_Pos          (2U)\n#define RTC_TAFCR_TAMPIE_Msk          (0x1U << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */\n#define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk\n#define RTC_TAFCR_TAMP1TRG_Pos        (1U)\n#define RTC_TAFCR_TAMP1TRG_Msk        (0x1U << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */\n#define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk\n#define RTC_TAFCR_TAMP1E_Pos          (0U)\n#define RTC_TAFCR_TAMP1E_Msk          (0x1U << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */\n#define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk\n\n/* Legacy defines */\n#define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMP1INSEL\n\n/********************  Bits definition for RTC_ALRMASSR register  *************/\n#define RTC_ALRMASSR_MASKSS_Pos       (24U)\n#define RTC_ALRMASSR_MASKSS_Msk       (0xFU << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk\n#define RTC_ALRMASSR_MASKSS_0         (0x1U << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMASSR_MASKSS_1         (0x2U << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMASSR_MASKSS_2         (0x4U << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMASSR_MASKSS_3         (0x8U << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMASSR_SS_Pos           (0U)\n#define RTC_ALRMASSR_SS_Msk           (0x7FFFU << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk\n\n/********************  Bits definition for RTC_ALRMBSSR register  *************/\n#define RTC_ALRMBSSR_MASKSS_Pos       (24U)\n#define RTC_ALRMBSSR_MASKSS_Msk       (0xFU << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk\n#define RTC_ALRMBSSR_MASKSS_0         (0x1U << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMBSSR_MASKSS_1         (0x2U << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMBSSR_MASKSS_2         (0x4U << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMBSSR_MASKSS_3         (0x8U << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMBSSR_SS_Pos           (0U)\n#define RTC_ALRMBSSR_SS_Msk           (0x7FFFU << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk\n\n/********************  Bits definition for RTC_BKP0R register  ****************/\n#define RTC_BKP0R_Pos                 (0U)\n#define RTC_BKP0R_Msk                 (0xFFFFFFFFU << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP0R                     RTC_BKP0R_Msk\n\n/********************  Bits definition for RTC_BKP1R register  ****************/\n#define RTC_BKP1R_Pos                 (0U)\n#define RTC_BKP1R_Msk                 (0xFFFFFFFFU << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP1R                     RTC_BKP1R_Msk\n\n/********************  Bits definition for RTC_BKP2R register  ****************/\n#define RTC_BKP2R_Pos                 (0U)\n#define RTC_BKP2R_Msk                 (0xFFFFFFFFU << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP2R                     RTC_BKP2R_Msk\n\n/********************  Bits definition for RTC_BKP3R register  ****************/\n#define RTC_BKP3R_Pos                 (0U)\n#define RTC_BKP3R_Msk                 (0xFFFFFFFFU << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP3R                     RTC_BKP3R_Msk\n\n/********************  Bits definition for RTC_BKP4R register  ****************/\n#define RTC_BKP4R_Pos                 (0U)\n#define RTC_BKP4R_Msk                 (0xFFFFFFFFU << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP4R                     RTC_BKP4R_Msk\n\n/********************  Bits definition for RTC_BKP5R register  ****************/\n#define RTC_BKP5R_Pos                 (0U)\n#define RTC_BKP5R_Msk                 (0xFFFFFFFFU << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP5R                     RTC_BKP5R_Msk\n\n/********************  Bits definition for RTC_BKP6R register  ****************/\n#define RTC_BKP6R_Pos                 (0U)\n#define RTC_BKP6R_Msk                 (0xFFFFFFFFU << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP6R                     RTC_BKP6R_Msk\n\n/********************  Bits definition for RTC_BKP7R register  ****************/\n#define RTC_BKP7R_Pos                 (0U)\n#define RTC_BKP7R_Msk                 (0xFFFFFFFFU << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP7R                     RTC_BKP7R_Msk\n\n/********************  Bits definition for RTC_BKP8R register  ****************/\n#define RTC_BKP8R_Pos                 (0U)\n#define RTC_BKP8R_Msk                 (0xFFFFFFFFU << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP8R                     RTC_BKP8R_Msk\n\n/********************  Bits definition for RTC_BKP9R register  ****************/\n#define RTC_BKP9R_Pos                 (0U)\n#define RTC_BKP9R_Msk                 (0xFFFFFFFFU << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP9R                     RTC_BKP9R_Msk\n\n/********************  Bits definition for RTC_BKP10R register  ***************/\n#define RTC_BKP10R_Pos                (0U)\n#define RTC_BKP10R_Msk                (0xFFFFFFFFU << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP10R                    RTC_BKP10R_Msk\n\n/********************  Bits definition for RTC_BKP11R register  ***************/\n#define RTC_BKP11R_Pos                (0U)\n#define RTC_BKP11R_Msk                (0xFFFFFFFFU << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP11R                    RTC_BKP11R_Msk\n\n/********************  Bits definition for RTC_BKP12R register  ***************/\n#define RTC_BKP12R_Pos                (0U)\n#define RTC_BKP12R_Msk                (0xFFFFFFFFU << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP12R                    RTC_BKP12R_Msk\n\n/********************  Bits definition for RTC_BKP13R register  ***************/\n#define RTC_BKP13R_Pos                (0U)\n#define RTC_BKP13R_Msk                (0xFFFFFFFFU << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP13R                    RTC_BKP13R_Msk\n\n/********************  Bits definition for RTC_BKP14R register  ***************/\n#define RTC_BKP14R_Pos                (0U)\n#define RTC_BKP14R_Msk                (0xFFFFFFFFU << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP14R                    RTC_BKP14R_Msk\n\n/********************  Bits definition for RTC_BKP15R register  ***************/\n#define RTC_BKP15R_Pos                (0U)\n#define RTC_BKP15R_Msk                (0xFFFFFFFFU << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP15R                    RTC_BKP15R_Msk\n\n/********************  Bits definition for RTC_BKP16R register  ***************/\n#define RTC_BKP16R_Pos                (0U)\n#define RTC_BKP16R_Msk                (0xFFFFFFFFU << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP16R                    RTC_BKP16R_Msk\n\n/********************  Bits definition for RTC_BKP17R register  ***************/\n#define RTC_BKP17R_Pos                (0U)\n#define RTC_BKP17R_Msk                (0xFFFFFFFFU << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP17R                    RTC_BKP17R_Msk\n\n/********************  Bits definition for RTC_BKP18R register  ***************/\n#define RTC_BKP18R_Pos                (0U)\n#define RTC_BKP18R_Msk                (0xFFFFFFFFU << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP18R                    RTC_BKP18R_Msk\n\n/********************  Bits definition for RTC_BKP19R register  ***************/\n#define RTC_BKP19R_Pos                (0U)\n#define RTC_BKP19R_Msk                (0xFFFFFFFFU << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP19R                    RTC_BKP19R_Msk\n\n/******************** Number of backup registers ******************************/\n#define RTC_BKP_NUMBER                       0x000000014U\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                          SD host Interface                                 */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SDIO_POWER register  ******************/\n#define SDIO_POWER_PWRCTRL_Pos         (0U)\n#define SDIO_POWER_PWRCTRL_Msk         (0x3U << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */\n#define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */\n#define SDIO_POWER_PWRCTRL_0           (0x1U << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x01 */\n#define SDIO_POWER_PWRCTRL_1           (0x2U << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x02 */\n\n/******************  Bit definition for SDIO_CLKCR register  ******************/\n#define SDIO_CLKCR_CLKDIV_Pos          (0U)\n#define SDIO_CLKCR_CLKDIV_Msk          (0xFFU << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */\n#define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor             */\n#define SDIO_CLKCR_CLKEN_Pos           (8U)\n#define SDIO_CLKCR_CLKEN_Msk           (0x1U << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */\n#define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit                */\n#define SDIO_CLKCR_PWRSAV_Pos          (9U)\n#define SDIO_CLKCR_PWRSAV_Msk          (0x1U << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */\n#define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit  */\n#define SDIO_CLKCR_BYPASS_Pos          (10U)\n#define SDIO_CLKCR_BYPASS_Msk          (0x1U << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */\n#define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */\n\n#define SDIO_CLKCR_WIDBUS_Pos          (11U)\n#define SDIO_CLKCR_WIDBUS_Msk          (0x3U << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */\n#define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\n#define SDIO_CLKCR_WIDBUS_0            (0x1U << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x0800 */\n#define SDIO_CLKCR_WIDBUS_1            (0x2U << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x1000 */\n\n#define SDIO_CLKCR_NEGEDGE_Pos         (13U)\n#define SDIO_CLKCR_NEGEDGE_Msk         (0x1U << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */\n#define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */\n#define SDIO_CLKCR_HWFC_EN_Pos         (14U)\n#define SDIO_CLKCR_HWFC_EN_Msk         (0x1U << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */\n#define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable          */\n\n/*******************  Bit definition for SDIO_ARG register  *******************/\n#define SDIO_ARG_CMDARG_Pos            (0U)\n#define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */\n#define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */\n\n/*******************  Bit definition for SDIO_CMD register  *******************/\n#define SDIO_CMD_CMDINDEX_Pos          (0U)\n#define SDIO_CMD_CMDINDEX_Msk          (0x3FU << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */\n#define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index                               */\n\n#define SDIO_CMD_WAITRESP_Pos          (6U)\n#define SDIO_CMD_WAITRESP_Msk          (0x3U << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */\n#define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */\n#define SDIO_CMD_WAITRESP_0            (0x1U << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0040 */\n#define SDIO_CMD_WAITRESP_1            (0x2U << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0080 */\n\n#define SDIO_CMD_WAITINT_Pos           (8U)\n#define SDIO_CMD_WAITINT_Msk           (0x1U << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */\n#define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request                               */\n#define SDIO_CMD_WAITPEND_Pos          (9U)\n#define SDIO_CMD_WAITPEND_Msk          (0x1U << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */\n#define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\n#define SDIO_CMD_CPSMEN_Pos            (10U)\n#define SDIO_CMD_CPSMEN_Msk            (0x1U << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */\n#define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit                   */\n#define SDIO_CMD_SDIOSUSPEND_Pos       (11U)\n#define SDIO_CMD_SDIOSUSPEND_Msk       (0x1U << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */\n#define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command                                         */\n#define SDIO_CMD_ENCMDCOMPL_Pos        (12U)\n#define SDIO_CMD_ENCMDCOMPL_Msk        (0x1U << SDIO_CMD_ENCMDCOMPL_Pos)       /*!< 0x00001000 */\n#define SDIO_CMD_ENCMDCOMPL            SDIO_CMD_ENCMDCOMPL_Msk                 /*!<Enable CMD completion                                          */\n#define SDIO_CMD_NIEN_Pos              (13U)\n#define SDIO_CMD_NIEN_Msk              (0x1U << SDIO_CMD_NIEN_Pos)             /*!< 0x00002000 */\n#define SDIO_CMD_NIEN                  SDIO_CMD_NIEN_Msk                       /*!<Not Interrupt Enable                                           */\n#define SDIO_CMD_CEATACMD_Pos          (14U)\n#define SDIO_CMD_CEATACMD_Msk          (0x1U << SDIO_CMD_CEATACMD_Pos)         /*!< 0x00004000 */\n#define SDIO_CMD_CEATACMD              SDIO_CMD_CEATACMD_Msk                   /*!<CE-ATA command                                                 */\n\n/*****************  Bit definition for SDIO_RESPCMD register  *****************/\n#define SDIO_RESPCMD_RESPCMD_Pos       (0U)\n#define SDIO_RESPCMD_RESPCMD_Msk       (0x3FU << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */\n#define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */\n\n/******************  Bit definition for SDIO_RESP0 register  ******************/\n#define SDIO_RESP0_CARDSTATUS0_Pos     (0U)\n#define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP1 register  ******************/\n#define SDIO_RESP1_CARDSTATUS1_Pos     (0U)\n#define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP2 register  ******************/\n#define SDIO_RESP2_CARDSTATUS2_Pos     (0U)\n#define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP3 register  ******************/\n#define SDIO_RESP3_CARDSTATUS3_Pos     (0U)\n#define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP4 register  ******************/\n#define SDIO_RESP4_CARDSTATUS4_Pos     (0U)\n#define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_DTIMER register  *****************/\n#define SDIO_DTIMER_DATATIME_Pos       (0U)\n#define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */\n\n/******************  Bit definition for SDIO_DLEN register  *******************/\n#define SDIO_DLEN_DATALENGTH_Pos       (0U)\n#define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */\n\n/******************  Bit definition for SDIO_DCTRL register  ******************/\n#define SDIO_DCTRL_DTEN_Pos            (0U)\n#define SDIO_DCTRL_DTEN_Msk            (0x1U << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */\n#define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit         */\n#define SDIO_DCTRL_DTDIR_Pos           (1U)\n#define SDIO_DCTRL_DTDIR_Msk           (0x1U << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */\n#define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */\n#define SDIO_DCTRL_DTMODE_Pos          (2U)\n#define SDIO_DCTRL_DTMODE_Msk          (0x1U << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */\n#define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection      */\n#define SDIO_DCTRL_DMAEN_Pos           (3U)\n#define SDIO_DCTRL_DMAEN_Msk           (0x1U << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */\n#define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit                   */\n\n#define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)\n#define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */\n#define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */\n#define SDIO_DCTRL_DBLOCKSIZE_0        (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0010 */\n#define SDIO_DCTRL_DBLOCKSIZE_1        (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0020 */\n#define SDIO_DCTRL_DBLOCKSIZE_2        (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0040 */\n#define SDIO_DCTRL_DBLOCKSIZE_3        (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0080 */\n\n#define SDIO_DCTRL_RWSTART_Pos         (8U)\n#define SDIO_DCTRL_RWSTART_Msk         (0x1U << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */\n#define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start         */\n#define SDIO_DCTRL_RWSTOP_Pos          (9U)\n#define SDIO_DCTRL_RWSTOP_Msk          (0x1U << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */\n#define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop          */\n#define SDIO_DCTRL_RWMOD_Pos           (10U)\n#define SDIO_DCTRL_RWMOD_Msk           (0x1U << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */\n#define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode          */\n#define SDIO_DCTRL_SDIOEN_Pos          (11U)\n#define SDIO_DCTRL_SDIOEN_Msk          (0x1U << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */\n#define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */\n\n/******************  Bit definition for SDIO_DCOUNT register  *****************/\n#define SDIO_DCOUNT_DATACOUNT_Pos      (0U)\n#define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */\n\n/******************  Bit definition for SDIO_STA register  ********************/\n#define SDIO_STA_CCRCFAIL_Pos          (0U)\n#define SDIO_STA_CCRCFAIL_Msk          (0x1U << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */\n#define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */\n#define SDIO_STA_DCRCFAIL_Pos          (1U)\n#define SDIO_STA_DCRCFAIL_Msk          (0x1U << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */\n#define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */\n#define SDIO_STA_CTIMEOUT_Pos          (2U)\n#define SDIO_STA_CTIMEOUT_Msk          (0x1U << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */\n#define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */\n#define SDIO_STA_DTIMEOUT_Pos          (3U)\n#define SDIO_STA_DTIMEOUT_Msk          (0x1U << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */\n#define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */\n#define SDIO_STA_TXUNDERR_Pos          (4U)\n#define SDIO_STA_TXUNDERR_Msk          (0x1U << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */\n#define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */\n#define SDIO_STA_RXOVERR_Pos           (5U)\n#define SDIO_STA_RXOVERR_Msk           (0x1U << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */\n#define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */\n#define SDIO_STA_CMDREND_Pos           (6U)\n#define SDIO_STA_CMDREND_Msk           (0x1U << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */\n#define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */\n#define SDIO_STA_CMDSENT_Pos           (7U)\n#define SDIO_STA_CMDSENT_Msk           (0x1U << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */\n#define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */\n#define SDIO_STA_DATAEND_Pos           (8U)\n#define SDIO_STA_DATAEND_Msk           (0x1U << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */\n#define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */\n#define SDIO_STA_STBITERR_Pos          (9U)\n#define SDIO_STA_STBITERR_Msk          (0x1U << SDIO_STA_STBITERR_Pos)         /*!< 0x00000200 */\n#define SDIO_STA_STBITERR              SDIO_STA_STBITERR_Msk                   /*!<Start bit not detected on all data signals in wide bus mode */\n#define SDIO_STA_DBCKEND_Pos           (10U)\n#define SDIO_STA_DBCKEND_Msk           (0x1U << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */\n#define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */\n#define SDIO_STA_CMDACT_Pos            (11U)\n#define SDIO_STA_CMDACT_Msk            (0x1U << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */\n#define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */\n#define SDIO_STA_TXACT_Pos             (12U)\n#define SDIO_STA_TXACT_Msk             (0x1U << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */\n#define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */\n#define SDIO_STA_RXACT_Pos             (13U)\n#define SDIO_STA_RXACT_Msk             (0x1U << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */\n#define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */\n#define SDIO_STA_TXFIFOHE_Pos          (14U)\n#define SDIO_STA_TXFIFOHE_Msk          (0x1U << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */\n#define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\n#define SDIO_STA_RXFIFOHF_Pos          (15U)\n#define SDIO_STA_RXFIFOHF_Msk          (0x1U << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */\n#define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\n#define SDIO_STA_TXFIFOF_Pos           (16U)\n#define SDIO_STA_TXFIFOF_Msk           (0x1U << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */\n#define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */\n#define SDIO_STA_RXFIFOF_Pos           (17U)\n#define SDIO_STA_RXFIFOF_Msk           (0x1U << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */\n#define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */\n#define SDIO_STA_TXFIFOE_Pos           (18U)\n#define SDIO_STA_TXFIFOE_Msk           (0x1U << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */\n#define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */\n#define SDIO_STA_RXFIFOE_Pos           (19U)\n#define SDIO_STA_RXFIFOE_Msk           (0x1U << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */\n#define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */\n#define SDIO_STA_TXDAVL_Pos            (20U)\n#define SDIO_STA_TXDAVL_Msk            (0x1U << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */\n#define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */\n#define SDIO_STA_RXDAVL_Pos            (21U)\n#define SDIO_STA_RXDAVL_Msk            (0x1U << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */\n#define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */\n#define SDIO_STA_SDIOIT_Pos            (22U)\n#define SDIO_STA_SDIOIT_Msk            (0x1U << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */\n#define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */\n#define SDIO_STA_CEATAEND_Pos          (23U)\n#define SDIO_STA_CEATAEND_Msk          (0x1U << SDIO_STA_CEATAEND_Pos)         /*!< 0x00800000 */\n#define SDIO_STA_CEATAEND              SDIO_STA_CEATAEND_Msk                   /*!<CE-ATA command completion signal received for CMD61 */\n\n/*******************  Bit definition for SDIO_ICR register  *******************/\n#define SDIO_ICR_CCRCFAILC_Pos         (0U)\n#define SDIO_ICR_CCRCFAILC_Msk         (0x1U << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */\n#define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */\n#define SDIO_ICR_DCRCFAILC_Pos         (1U)\n#define SDIO_ICR_DCRCFAILC_Msk         (0x1U << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */\n#define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */\n#define SDIO_ICR_CTIMEOUTC_Pos         (2U)\n#define SDIO_ICR_CTIMEOUTC_Msk         (0x1U << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */\n#define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */\n#define SDIO_ICR_DTIMEOUTC_Pos         (3U)\n#define SDIO_ICR_DTIMEOUTC_Msk         (0x1U << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */\n#define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */\n#define SDIO_ICR_TXUNDERRC_Pos         (4U)\n#define SDIO_ICR_TXUNDERRC_Msk         (0x1U << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */\n#define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */\n#define SDIO_ICR_RXOVERRC_Pos          (5U)\n#define SDIO_ICR_RXOVERRC_Msk          (0x1U << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */\n#define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */\n#define SDIO_ICR_CMDRENDC_Pos          (6U)\n#define SDIO_ICR_CMDRENDC_Msk          (0x1U << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */\n#define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */\n#define SDIO_ICR_CMDSENTC_Pos          (7U)\n#define SDIO_ICR_CMDSENTC_Msk          (0x1U << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */\n#define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */\n#define SDIO_ICR_DATAENDC_Pos          (8U)\n#define SDIO_ICR_DATAENDC_Msk          (0x1U << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */\n#define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */\n#define SDIO_ICR_STBITERRC_Pos         (9U)\n#define SDIO_ICR_STBITERRC_Msk         (0x1U << SDIO_ICR_STBITERRC_Pos)        /*!< 0x00000200 */\n#define SDIO_ICR_STBITERRC             SDIO_ICR_STBITERRC_Msk                  /*!<STBITERR flag clear bit */\n#define SDIO_ICR_DBCKENDC_Pos          (10U)\n#define SDIO_ICR_DBCKENDC_Msk          (0x1U << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */\n#define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */\n#define SDIO_ICR_SDIOITC_Pos           (22U)\n#define SDIO_ICR_SDIOITC_Msk           (0x1U << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */\n#define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */\n#define SDIO_ICR_CEATAENDC_Pos         (23U)\n#define SDIO_ICR_CEATAENDC_Msk         (0x1U << SDIO_ICR_CEATAENDC_Pos)        /*!< 0x00800000 */\n#define SDIO_ICR_CEATAENDC             SDIO_ICR_CEATAENDC_Msk                  /*!<CEATAEND flag clear bit */\n\n/******************  Bit definition for SDIO_MASK register  *******************/\n#define SDIO_MASK_CCRCFAILIE_Pos       (0U)\n#define SDIO_MASK_CCRCFAILIE_Msk       (0x1U << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */\n#define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */\n#define SDIO_MASK_DCRCFAILIE_Pos       (1U)\n#define SDIO_MASK_DCRCFAILIE_Msk       (0x1U << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */\n#define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */\n#define SDIO_MASK_CTIMEOUTIE_Pos       (2U)\n#define SDIO_MASK_CTIMEOUTIE_Msk       (0x1U << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */\n#define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */\n#define SDIO_MASK_DTIMEOUTIE_Pos       (3U)\n#define SDIO_MASK_DTIMEOUTIE_Msk       (0x1U << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */\n#define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */\n#define SDIO_MASK_TXUNDERRIE_Pos       (4U)\n#define SDIO_MASK_TXUNDERRIE_Msk       (0x1U << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */\n#define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */\n#define SDIO_MASK_RXOVERRIE_Pos        (5U)\n#define SDIO_MASK_RXOVERRIE_Msk        (0x1U << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */\n#define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */\n#define SDIO_MASK_CMDRENDIE_Pos        (6U)\n#define SDIO_MASK_CMDRENDIE_Msk        (0x1U << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */\n#define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */\n#define SDIO_MASK_CMDSENTIE_Pos        (7U)\n#define SDIO_MASK_CMDSENTIE_Msk        (0x1U << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */\n#define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */\n#define SDIO_MASK_DATAENDIE_Pos        (8U)\n#define SDIO_MASK_DATAENDIE_Msk        (0x1U << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */\n#define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */\n#define SDIO_MASK_STBITERRIE_Pos       (9U)\n#define SDIO_MASK_STBITERRIE_Msk       (0x1U << SDIO_MASK_STBITERRIE_Pos)      /*!< 0x00000200 */\n#define SDIO_MASK_STBITERRIE           SDIO_MASK_STBITERRIE_Msk                /*!<Start Bit Error Interrupt Enable           */\n#define SDIO_MASK_DBCKENDIE_Pos        (10U)\n#define SDIO_MASK_DBCKENDIE_Msk        (0x1U << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */\n#define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */\n#define SDIO_MASK_CMDACTIE_Pos         (11U)\n#define SDIO_MASK_CMDACTIE_Msk         (0x1U << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */\n#define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */\n#define SDIO_MASK_TXACTIE_Pos          (12U)\n#define SDIO_MASK_TXACTIE_Msk          (0x1U << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */\n#define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */\n#define SDIO_MASK_RXACTIE_Pos          (13U)\n#define SDIO_MASK_RXACTIE_Msk          (0x1U << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */\n#define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */\n#define SDIO_MASK_TXFIFOHEIE_Pos       (14U)\n#define SDIO_MASK_TXFIFOHEIE_Msk       (0x1U << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */\n#define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */\n#define SDIO_MASK_RXFIFOHFIE_Pos       (15U)\n#define SDIO_MASK_RXFIFOHFIE_Msk       (0x1U << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */\n#define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */\n#define SDIO_MASK_TXFIFOFIE_Pos        (16U)\n#define SDIO_MASK_TXFIFOFIE_Msk        (0x1U << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */\n#define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */\n#define SDIO_MASK_RXFIFOFIE_Pos        (17U)\n#define SDIO_MASK_RXFIFOFIE_Msk        (0x1U << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */\n#define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */\n#define SDIO_MASK_TXFIFOEIE_Pos        (18U)\n#define SDIO_MASK_TXFIFOEIE_Msk        (0x1U << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */\n#define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_RXFIFOEIE_Pos        (19U)\n#define SDIO_MASK_RXFIFOEIE_Msk        (0x1U << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */\n#define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_TXDAVLIE_Pos         (20U)\n#define SDIO_MASK_TXDAVLIE_Msk         (0x1U << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */\n#define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */\n#define SDIO_MASK_RXDAVLIE_Pos         (21U)\n#define SDIO_MASK_RXDAVLIE_Msk         (0x1U << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */\n#define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */\n#define SDIO_MASK_SDIOITIE_Pos         (22U)\n#define SDIO_MASK_SDIOITIE_Msk         (0x1U << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */\n#define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */\n#define SDIO_MASK_CEATAENDIE_Pos       (23U)\n#define SDIO_MASK_CEATAENDIE_Msk       (0x1U << SDIO_MASK_CEATAENDIE_Pos)      /*!< 0x00800000 */\n#define SDIO_MASK_CEATAENDIE           SDIO_MASK_CEATAENDIE_Msk                /*!<CE-ATA command completion signal received Interrupt Enable */\n\n/*****************  Bit definition for SDIO_FIFOCNT register  *****************/\n#define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)\n#define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */\n#define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */\n\n/******************  Bit definition for SDIO_FIFO register  *******************/\n#define SDIO_FIFO_FIFODATA_Pos         (0U)\n#define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Serial Peripheral Interface                         */\n/*                                                                            */\n/******************************************************************************/\n#define SPI_I2S_FULLDUPLEX_SUPPORT                                             /*!< I2S Full-Duplex support */\n\n/*******************  Bit definition for SPI_CR1 register  ********************/\n#define SPI_CR1_CPHA_Pos            (0U)\n#define SPI_CR1_CPHA_Msk            (0x1U << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */\n#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */\n#define SPI_CR1_CPOL_Pos            (1U)\n#define SPI_CR1_CPOL_Msk            (0x1U << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */\n#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */\n#define SPI_CR1_MSTR_Pos            (2U)\n#define SPI_CR1_MSTR_Msk            (0x1U << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */\n#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */\n\n#define SPI_CR1_BR_Pos              (3U)\n#define SPI_CR1_BR_Msk              (0x7U << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */\n#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */\n#define SPI_CR1_BR_0                (0x1U << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */\n#define SPI_CR1_BR_1                (0x2U << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */\n#define SPI_CR1_BR_2                (0x4U << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */\n\n#define SPI_CR1_SPE_Pos             (6U)\n#define SPI_CR1_SPE_Msk             (0x1U << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */\n#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */\n#define SPI_CR1_LSBFIRST_Pos        (7U)\n#define SPI_CR1_LSBFIRST_Msk        (0x1U << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */\n#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */\n#define SPI_CR1_SSI_Pos             (8U)\n#define SPI_CR1_SSI_Msk             (0x1U << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */\n#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */\n#define SPI_CR1_SSM_Pos             (9U)\n#define SPI_CR1_SSM_Msk             (0x1U << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */\n#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */\n#define SPI_CR1_RXONLY_Pos          (10U)\n#define SPI_CR1_RXONLY_Msk          (0x1U << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */\n#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */\n#define SPI_CR1_DFF_Pos             (11U)\n#define SPI_CR1_DFF_Msk             (0x1U << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */\n#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */\n#define SPI_CR1_CRCNEXT_Pos         (12U)\n#define SPI_CR1_CRCNEXT_Msk         (0x1U << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */\n#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */\n#define SPI_CR1_CRCEN_Pos           (13U)\n#define SPI_CR1_CRCEN_Msk           (0x1U << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */\n#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */\n#define SPI_CR1_BIDIOE_Pos          (14U)\n#define SPI_CR1_BIDIOE_Msk          (0x1U << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */\n#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */\n#define SPI_CR1_BIDIMODE_Pos        (15U)\n#define SPI_CR1_BIDIMODE_Msk        (0x1U << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */\n#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */\n\n/*******************  Bit definition for SPI_CR2 register  ********************/\n#define SPI_CR2_RXDMAEN_Pos         (0U)\n#define SPI_CR2_RXDMAEN_Msk         (0x1U << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */\n#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */\n#define SPI_CR2_TXDMAEN_Pos         (1U)\n#define SPI_CR2_TXDMAEN_Msk         (0x1U << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */\n#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */\n#define SPI_CR2_SSOE_Pos            (2U)\n#define SPI_CR2_SSOE_Msk            (0x1U << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */\n#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */\n#define SPI_CR2_FRF_Pos             (4U)\n#define SPI_CR2_FRF_Msk             (0x1U << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */\n#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */\n#define SPI_CR2_ERRIE_Pos           (5U)\n#define SPI_CR2_ERRIE_Msk           (0x1U << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */\n#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */\n#define SPI_CR2_RXNEIE_Pos          (6U)\n#define SPI_CR2_RXNEIE_Msk          (0x1U << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */\n#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */\n#define SPI_CR2_TXEIE_Pos           (7U)\n#define SPI_CR2_TXEIE_Msk           (0x1U << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */\n#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */\n\n/********************  Bit definition for SPI_SR register  ********************/\n#define SPI_SR_RXNE_Pos             (0U)\n#define SPI_SR_RXNE_Msk             (0x1U << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */\n#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */\n#define SPI_SR_TXE_Pos              (1U)\n#define SPI_SR_TXE_Msk              (0x1U << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */\n#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */\n#define SPI_SR_CHSIDE_Pos           (2U)\n#define SPI_SR_CHSIDE_Msk           (0x1U << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */\n#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */\n#define SPI_SR_UDR_Pos              (3U)\n#define SPI_SR_UDR_Msk              (0x1U << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */\n#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */\n#define SPI_SR_CRCERR_Pos           (4U)\n#define SPI_SR_CRCERR_Msk           (0x1U << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */\n#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */\n#define SPI_SR_MODF_Pos             (5U)\n#define SPI_SR_MODF_Msk             (0x1U << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */\n#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */\n#define SPI_SR_OVR_Pos              (6U)\n#define SPI_SR_OVR_Msk              (0x1U << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */\n#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */\n#define SPI_SR_BSY_Pos              (7U)\n#define SPI_SR_BSY_Msk              (0x1U << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */\n#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */\n#define SPI_SR_FRE_Pos              (8U)\n#define SPI_SR_FRE_Msk              (0x1U << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */\n#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */\n\n/********************  Bit definition for SPI_DR register  ********************/\n#define SPI_DR_DR_Pos               (0U)\n#define SPI_DR_DR_Msk               (0xFFFFU << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */\n#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */\n\n/*******************  Bit definition for SPI_CRCPR register  ******************/\n#define SPI_CRCPR_CRCPOLY_Pos       (0U)\n#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */\n#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */\n\n/******************  Bit definition for SPI_RXCRCR register  ******************/\n#define SPI_RXCRCR_RXCRC_Pos        (0U)\n#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */\n\n/******************  Bit definition for SPI_TXCRCR register  ******************/\n#define SPI_TXCRCR_TXCRC_Pos        (0U)\n#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */\n\n/******************  Bit definition for SPI_I2SCFGR register  *****************/\n#define SPI_I2SCFGR_CHLEN_Pos       (0U)\n#define SPI_I2SCFGR_CHLEN_Msk       (0x1U << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */\n#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */\n\n#define SPI_I2SCFGR_DATLEN_Pos      (1U)\n#define SPI_I2SCFGR_DATLEN_Msk      (0x3U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */\n#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */\n#define SPI_I2SCFGR_DATLEN_0        (0x1U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */\n#define SPI_I2SCFGR_DATLEN_1        (0x2U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */\n\n#define SPI_I2SCFGR_CKPOL_Pos       (3U)\n#define SPI_I2SCFGR_CKPOL_Msk       (0x1U << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */\n#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */\n\n#define SPI_I2SCFGR_I2SSTD_Pos      (4U)\n#define SPI_I2SCFGR_I2SSTD_Msk      (0x3U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */\n#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */\n#define SPI_I2SCFGR_I2SSTD_0        (0x1U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */\n#define SPI_I2SCFGR_I2SSTD_1        (0x2U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */\n\n#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)\n#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1U << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */\n#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */\n\n#define SPI_I2SCFGR_I2SCFG_Pos      (8U)\n#define SPI_I2SCFGR_I2SCFG_Msk      (0x3U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */\n#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */\n#define SPI_I2SCFGR_I2SCFG_0        (0x1U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */\n#define SPI_I2SCFGR_I2SCFG_1        (0x2U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */\n\n#define SPI_I2SCFGR_I2SE_Pos        (10U)\n#define SPI_I2SCFGR_I2SE_Msk        (0x1U << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */\n#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */\n#define SPI_I2SCFGR_I2SMOD_Pos      (11U)\n#define SPI_I2SCFGR_I2SMOD_Msk      (0x1U << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */\n#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */\n\n/******************  Bit definition for SPI_I2SPR register  *******************/\n#define SPI_I2SPR_I2SDIV_Pos        (0U)\n#define SPI_I2SPR_I2SDIV_Msk        (0xFFU << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */\n#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */\n#define SPI_I2SPR_ODD_Pos           (8U)\n#define SPI_I2SPR_ODD_Msk           (0x1U << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */\n#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */\n#define SPI_I2SPR_MCKOE_Pos         (9U)\n#define SPI_I2SPR_MCKOE_Msk         (0x1U << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */\n#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                 SYSCFG                                     */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SYSCFG_MEMRMP register  ***************/\n#define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)\n#define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */\n#define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */\n#define SYSCFG_MEMRMP_MEM_MODE_0             (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */\n#define SYSCFG_MEMRMP_MEM_MODE_1             (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */\n/******************  Bit definition for SYSCFG_PMC register  ******************/\n#define SYSCFG_PMC_MII_RMII_SEL_Pos          (23U)\n#define SYSCFG_PMC_MII_RMII_SEL_Msk          (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */\n#define SYSCFG_PMC_MII_RMII_SEL              SYSCFG_PMC_MII_RMII_SEL_Msk       /*!<Ethernet PHY interface selection */\n/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */\n#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL\n\n/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\n#define SYSCFG_EXTICR1_EXTI0_Pos             (0U)\n#define SYSCFG_EXTICR1_EXTI0_Msk             (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */\n#define SYSCFG_EXTICR1_EXTI1_Pos             (4U)\n#define SYSCFG_EXTICR1_EXTI1_Msk             (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */\n#define SYSCFG_EXTICR1_EXTI2_Pos             (8U)\n#define SYSCFG_EXTICR1_EXTI2_Msk             (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */\n#define SYSCFG_EXTICR1_EXTI3_Pos             (12U)\n#define SYSCFG_EXTICR1_EXTI3_Msk             (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */\n/**\n  * @brief   EXTI0 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PD              0x0003U                           /*!<PD[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PE              0x0004U                           /*!<PE[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PF              0x0005U                           /*!<PF[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PG              0x0006U                           /*!<PG[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PI              0x0008U                           /*!<PI[0] pin */\n\n/**\n  * @brief   EXTI1 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PD              0x0030U                           /*!<PD[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PE              0x0040U                           /*!<PE[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PF              0x0050U                           /*!<PF[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PG              0x0060U                           /*!<PG[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PI              0x0080U                           /*!<PI[1] pin */\n\n/**\n  * @brief   EXTI2 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PD              0x0300U                           /*!<PD[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PE              0x0400U                           /*!<PE[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PF              0x0500U                           /*!<PF[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PG              0x0600U                           /*!<PG[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PI              0x0800U                           /*!<PI[2] pin */\n\n/**\n  * @brief   EXTI3 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PD              0x3000U                           /*!<PD[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PE              0x4000U                           /*!<PE[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PF              0x5000U                           /*!<PF[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PG              0x6000U                           /*!<PG[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PI              0x8000U                           /*!<PI[3] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\n#define SYSCFG_EXTICR2_EXTI4_Pos             (0U)\n#define SYSCFG_EXTICR2_EXTI4_Msk             (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */\n#define SYSCFG_EXTICR2_EXTI5_Pos             (4U)\n#define SYSCFG_EXTICR2_EXTI5_Msk             (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */\n#define SYSCFG_EXTICR2_EXTI6_Pos             (8U)\n#define SYSCFG_EXTICR2_EXTI6_Msk             (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */\n#define SYSCFG_EXTICR2_EXTI7_Pos             (12U)\n#define SYSCFG_EXTICR2_EXTI7_Msk             (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */\n\n/**\n  * @brief   EXTI4 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PD              0x0003U                           /*!<PD[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PE              0x0004U                           /*!<PE[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PF              0x0005U                           /*!<PF[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PG              0x0006U                           /*!<PG[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PI              0x0008U                           /*!<PI[4] pin */\n\n/**\n  * @brief   EXTI5 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PD              0x0030U                           /*!<PD[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PE              0x0040U                           /*!<PE[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PF              0x0050U                           /*!<PF[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PG              0x0060U                           /*!<PG[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PI              0x0080U                           /*!<PI[5] pin */\n\n/**\n  * @brief   EXTI6 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PD              0x0300U                           /*!<PD[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PE              0x0400U                           /*!<PE[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PF              0x0500U                           /*!<PF[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PG              0x0600U                           /*!<PG[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PI              0x0800U                           /*!<PI[6] pin */\n\n/**\n  * @brief   EXTI7 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PD              0x3000U                           /*!<PD[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PE              0x4000U                           /*!<PE[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PF              0x5000U                           /*!<PF[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PG              0x6000U                           /*!<PG[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PI              0x8000U                           /*!<PI[7] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\n#define SYSCFG_EXTICR3_EXTI8_Pos             (0U)\n#define SYSCFG_EXTICR3_EXTI8_Msk             (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */\n#define SYSCFG_EXTICR3_EXTI9_Pos             (4U)\n#define SYSCFG_EXTICR3_EXTI9_Msk             (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */\n#define SYSCFG_EXTICR3_EXTI10_Pos            (8U)\n#define SYSCFG_EXTICR3_EXTI10_Msk            (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */\n#define SYSCFG_EXTICR3_EXTI11_Pos            (12U)\n#define SYSCFG_EXTICR3_EXTI11_Msk            (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */\n\n/**\n  * @brief   EXTI8 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PD              0x0003U                           /*!<PD[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PE              0x0004U                           /*!<PE[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PF              0x0005U                           /*!<PF[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PG              0x0006U                           /*!<PG[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PI              0x0008U                           /*!<PI[8] pin */\n\n/**\n  * @brief   EXTI9 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PD              0x0030U                           /*!<PD[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PE              0x0040U                           /*!<PE[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PF              0x0050U                           /*!<PF[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PG              0x0060U                           /*!<PG[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PI              0x0080U                           /*!<PI[9] pin */\n\n/**\n  * @brief   EXTI10 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PD             0x0300U                           /*!<PD[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PE             0x0400U                           /*!<PE[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PF             0x0500U                           /*!<PF[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PG             0x0600U                           /*!<PG[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PI             0x0800U                           /*!<PI[10] pin */\n\n/**\n  * @brief   EXTI11 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PD             0x3000U                           /*!<PD[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PE             0x4000U                           /*!<PE[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PF             0x5000U                           /*!<PF[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PG             0x6000U                           /*!<PG[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PI             0x8000U                           /*!<PI[11] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\n#define SYSCFG_EXTICR4_EXTI12_Pos            (0U)\n#define SYSCFG_EXTICR4_EXTI12_Msk            (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */\n#define SYSCFG_EXTICR4_EXTI13_Pos            (4U)\n#define SYSCFG_EXTICR4_EXTI13_Msk            (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */\n#define SYSCFG_EXTICR4_EXTI14_Pos            (8U)\n#define SYSCFG_EXTICR4_EXTI14_Msk            (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */\n#define SYSCFG_EXTICR4_EXTI15_Pos            (12U)\n#define SYSCFG_EXTICR4_EXTI15_Msk            (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */\n\n/**\n  * @brief   EXTI12 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PD             0x0003U                           /*!<PD[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PE             0x0004U                           /*!<PE[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PF             0x0005U                           /*!<PF[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PG             0x0006U                           /*!<PG[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */\n\n/**\n  * @brief   EXTI13 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PD             0x0030U                           /*!<PD[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PE             0x0040U                           /*!<PE[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PF             0x0050U                           /*!<PF[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PG             0x0060U                           /*!<PG[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */\n\n/**\n  * @brief   EXTI14 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PD             0x0300U                           /*!<PD[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PE             0x0400U                           /*!<PE[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PF             0x0500U                           /*!<PF[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PG             0x0600U                           /*!<PG[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */\n\n/**\n  * @brief   EXTI15 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PD             0x3000U                           /*!<PD[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PE             0x4000U                           /*!<PE[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PF             0x5000U                           /*!<PF[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PG             0x6000U                           /*!<PG[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */\n\n/******************  Bit definition for SYSCFG_CMPCR register  ****************/\n#define SYSCFG_CMPCR_CMP_PD_Pos              (0U)\n#define SYSCFG_CMPCR_CMP_PD_Msk              (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */\n#define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */\n#define SYSCFG_CMPCR_READY_Pos               (8U)\n#define SYSCFG_CMPCR_READY_Msk               (0x1U << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */\n#define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    TIM                                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for TIM_CR1 register  ********************/\n#define TIM_CR1_CEN_Pos           (0U)\n#define TIM_CR1_CEN_Msk           (0x1U << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */\n#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */\n#define TIM_CR1_UDIS_Pos          (1U)\n#define TIM_CR1_UDIS_Msk          (0x1U << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */\n#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */\n#define TIM_CR1_URS_Pos           (2U)\n#define TIM_CR1_URS_Msk           (0x1U << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */\n#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */\n#define TIM_CR1_OPM_Pos           (3U)\n#define TIM_CR1_OPM_Msk           (0x1U << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */\n#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */\n#define TIM_CR1_DIR_Pos           (4U)\n#define TIM_CR1_DIR_Msk           (0x1U << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */\n#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */\n\n#define TIM_CR1_CMS_Pos           (5U)\n#define TIM_CR1_CMS_Msk           (0x3U << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */\n#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */\n#define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR1_ARPE_Pos          (7U)\n#define TIM_CR1_ARPE_Msk          (0x1U << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */\n#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */\n\n#define TIM_CR1_CKD_Pos           (8U)\n#define TIM_CR1_CKD_Msk           (0x3U << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */\n#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */\n#define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */\n#define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */\n\n/*******************  Bit definition for TIM_CR2 register  ********************/\n#define TIM_CR2_CCPC_Pos          (0U)\n#define TIM_CR2_CCPC_Msk          (0x1U << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */\n#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */\n#define TIM_CR2_CCUS_Pos          (2U)\n#define TIM_CR2_CCUS_Msk          (0x1U << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */\n#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */\n#define TIM_CR2_CCDS_Pos          (3U)\n#define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */\n#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */\n\n#define TIM_CR2_MMS_Pos           (4U)\n#define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */\n#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */\n#define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */\n#define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR2_TI1S_Pos          (7U)\n#define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */\n#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */\n#define TIM_CR2_OIS1_Pos          (8U)\n#define TIM_CR2_OIS1_Msk          (0x1U << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */\n#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */\n#define TIM_CR2_OIS1N_Pos         (9U)\n#define TIM_CR2_OIS1N_Msk         (0x1U << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */\n#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */\n#define TIM_CR2_OIS2_Pos          (10U)\n#define TIM_CR2_OIS2_Msk          (0x1U << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */\n#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */\n#define TIM_CR2_OIS2N_Pos         (11U)\n#define TIM_CR2_OIS2N_Msk         (0x1U << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */\n#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */\n#define TIM_CR2_OIS3_Pos          (12U)\n#define TIM_CR2_OIS3_Msk          (0x1U << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */\n#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */\n#define TIM_CR2_OIS3N_Pos         (13U)\n#define TIM_CR2_OIS3N_Msk         (0x1U << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */\n#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */\n#define TIM_CR2_OIS4_Pos          (14U)\n#define TIM_CR2_OIS4_Msk          (0x1U << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */\n#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */\n\n/*******************  Bit definition for TIM_SMCR register  *******************/\n#define TIM_SMCR_SMS_Pos          (0U)\n#define TIM_SMCR_SMS_Msk          (0x7U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */\n#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */\n#define TIM_SMCR_SMS_0            (0x1U << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */\n#define TIM_SMCR_SMS_1            (0x2U << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */\n#define TIM_SMCR_SMS_2            (0x4U << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */\n\n#define TIM_SMCR_TS_Pos           (4U)\n#define TIM_SMCR_TS_Msk           (0x7U << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */\n#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */\n#define TIM_SMCR_TS_0             (0x1U << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */\n#define TIM_SMCR_TS_1             (0x2U << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */\n#define TIM_SMCR_TS_2             (0x4U << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */\n\n#define TIM_SMCR_MSM_Pos          (7U)\n#define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */\n#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */\n\n#define TIM_SMCR_ETF_Pos          (8U)\n#define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */\n#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */\n#define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */\n#define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */\n#define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */\n#define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */\n\n#define TIM_SMCR_ETPS_Pos         (12U)\n#define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */\n#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */\n#define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */\n#define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */\n\n#define TIM_SMCR_ECE_Pos          (14U)\n#define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */\n#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */\n#define TIM_SMCR_ETP_Pos          (15U)\n#define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */\n#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */\n\n/*******************  Bit definition for TIM_DIER register  *******************/\n#define TIM_DIER_UIE_Pos          (0U)\n#define TIM_DIER_UIE_Msk          (0x1U << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */\n#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */\n#define TIM_DIER_CC1IE_Pos        (1U)\n#define TIM_DIER_CC1IE_Msk        (0x1U << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */\n#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */\n#define TIM_DIER_CC2IE_Pos        (2U)\n#define TIM_DIER_CC2IE_Msk        (0x1U << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */\n#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */\n#define TIM_DIER_CC3IE_Pos        (3U)\n#define TIM_DIER_CC3IE_Msk        (0x1U << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */\n#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */\n#define TIM_DIER_CC4IE_Pos        (4U)\n#define TIM_DIER_CC4IE_Msk        (0x1U << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */\n#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */\n#define TIM_DIER_COMIE_Pos        (5U)\n#define TIM_DIER_COMIE_Msk        (0x1U << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */\n#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */\n#define TIM_DIER_TIE_Pos          (6U)\n#define TIM_DIER_TIE_Msk          (0x1U << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */\n#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */\n#define TIM_DIER_BIE_Pos          (7U)\n#define TIM_DIER_BIE_Msk          (0x1U << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */\n#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */\n#define TIM_DIER_UDE_Pos          (8U)\n#define TIM_DIER_UDE_Msk          (0x1U << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */\n#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */\n#define TIM_DIER_CC1DE_Pos        (9U)\n#define TIM_DIER_CC1DE_Msk        (0x1U << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */\n#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */\n#define TIM_DIER_CC2DE_Pos        (10U)\n#define TIM_DIER_CC2DE_Msk        (0x1U << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */\n#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */\n#define TIM_DIER_CC3DE_Pos        (11U)\n#define TIM_DIER_CC3DE_Msk        (0x1U << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */\n#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */\n#define TIM_DIER_CC4DE_Pos        (12U)\n#define TIM_DIER_CC4DE_Msk        (0x1U << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */\n#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */\n#define TIM_DIER_COMDE_Pos        (13U)\n#define TIM_DIER_COMDE_Msk        (0x1U << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */\n#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */\n#define TIM_DIER_TDE_Pos          (14U)\n#define TIM_DIER_TDE_Msk          (0x1U << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */\n#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */\n\n/********************  Bit definition for TIM_SR register  ********************/\n#define TIM_SR_UIF_Pos            (0U)\n#define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */\n#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */\n#define TIM_SR_CC1IF_Pos          (1U)\n#define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */\n#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */\n#define TIM_SR_CC2IF_Pos          (2U)\n#define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */\n#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */\n#define TIM_SR_CC3IF_Pos          (3U)\n#define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */\n#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */\n#define TIM_SR_CC4IF_Pos          (4U)\n#define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */\n#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */\n#define TIM_SR_COMIF_Pos          (5U)\n#define TIM_SR_COMIF_Msk          (0x1U << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */\n#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */\n#define TIM_SR_TIF_Pos            (6U)\n#define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */\n#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */\n#define TIM_SR_BIF_Pos            (7U)\n#define TIM_SR_BIF_Msk            (0x1U << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */\n#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */\n#define TIM_SR_CC1OF_Pos          (9U)\n#define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */\n#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */\n#define TIM_SR_CC2OF_Pos          (10U)\n#define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */\n#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */\n#define TIM_SR_CC3OF_Pos          (11U)\n#define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */\n#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */\n#define TIM_SR_CC4OF_Pos          (12U)\n#define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */\n#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */\n\n/*******************  Bit definition for TIM_EGR register  ********************/\n#define TIM_EGR_UG_Pos            (0U)\n#define TIM_EGR_UG_Msk            (0x1U << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */\n#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */\n#define TIM_EGR_CC1G_Pos          (1U)\n#define TIM_EGR_CC1G_Msk          (0x1U << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */\n#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */\n#define TIM_EGR_CC2G_Pos          (2U)\n#define TIM_EGR_CC2G_Msk          (0x1U << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */\n#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */\n#define TIM_EGR_CC3G_Pos          (3U)\n#define TIM_EGR_CC3G_Msk          (0x1U << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */\n#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */\n#define TIM_EGR_CC4G_Pos          (4U)\n#define TIM_EGR_CC4G_Msk          (0x1U << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */\n#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */\n#define TIM_EGR_COMG_Pos          (5U)\n#define TIM_EGR_COMG_Msk          (0x1U << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */\n#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */\n#define TIM_EGR_TG_Pos            (6U)\n#define TIM_EGR_TG_Msk            (0x1U << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */\n#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */\n#define TIM_EGR_BG_Pos            (7U)\n#define TIM_EGR_BG_Msk            (0x1U << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */\n#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */\n\n/******************  Bit definition for TIM_CCMR1 register  *******************/\n#define TIM_CCMR1_CC1S_Pos        (0U)\n#define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\n#define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR1_OC1FE_Pos       (2U)\n#define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */\n#define TIM_CCMR1_OC1PE_Pos       (3U)\n#define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */\n\n#define TIM_CCMR1_OC1M_Pos        (4U)\n#define TIM_CCMR1_OC1M_Msk        (0x7U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */\n#define TIM_CCMR1_OC1M_0          (0x1U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_OC1M_1          (0x2U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_OC1M_2          (0x4U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR1_OC1CE_Pos       (7U)\n#define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */\n\n#define TIM_CCMR1_CC2S_Pos        (8U)\n#define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\n#define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR1_OC2FE_Pos       (10U)\n#define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */\n#define TIM_CCMR1_OC2PE_Pos       (11U)\n#define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */\n\n#define TIM_CCMR1_OC2M_Pos        (12U)\n#define TIM_CCMR1_OC2M_Msk        (0x7U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */\n#define TIM_CCMR1_OC2M_0          (0x1U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_OC2M_1          (0x2U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_OC2M_2          (0x4U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR1_OC2CE_Pos       (15U)\n#define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR1_IC1PSC_Pos      (2U)\n#define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\n#define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR1_IC1F_Pos        (4U)\n#define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */\n#define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR1_IC2PSC_Pos      (10U)\n#define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */\n#define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR1_IC2F_Pos        (12U)\n#define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */\n#define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */\n\n/******************  Bit definition for TIM_CCMR2 register  *******************/\n#define TIM_CCMR2_CC3S_Pos        (0U)\n#define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */\n#define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR2_OC3FE_Pos       (2U)\n#define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */\n#define TIM_CCMR2_OC3PE_Pos       (3U)\n#define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */\n\n#define TIM_CCMR2_OC3M_Pos        (4U)\n#define TIM_CCMR2_OC3M_Msk        (0x7U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\n#define TIM_CCMR2_OC3M_0          (0x1U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_OC3M_1          (0x2U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_OC3M_2          (0x4U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR2_OC3CE_Pos       (7U)\n#define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */\n\n#define TIM_CCMR2_CC4S_Pos        (8U)\n#define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\n#define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR2_OC4FE_Pos       (10U)\n#define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */\n#define TIM_CCMR2_OC4PE_Pos       (11U)\n#define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */\n\n#define TIM_CCMR2_OC4M_Pos        (12U)\n#define TIM_CCMR2_OC4M_Msk        (0x7U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\n#define TIM_CCMR2_OC4M_0          (0x1U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_OC4M_1          (0x2U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_OC4M_2          (0x4U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR2_OC4CE_Pos       (15U)\n#define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR2_IC3PSC_Pos      (2U)\n#define TIM_CCMR2_IC3PSC_Msk      (0x3U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\n#define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR2_IC3F_Pos        (4U)\n#define TIM_CCMR2_IC3F_Msk        (0xFU << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\n#define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR2_IC4PSC_Pos      (10U)\n#define TIM_CCMR2_IC4PSC_Msk      (0x3U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\n#define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR2_IC4F_Pos        (12U)\n#define TIM_CCMR2_IC4F_Msk        (0xFU << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\n#define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */\n\n/*******************  Bit definition for TIM_CCER register  *******************/\n#define TIM_CCER_CC1E_Pos         (0U)\n#define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */\n#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */\n#define TIM_CCER_CC1P_Pos         (1U)\n#define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */\n#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */\n#define TIM_CCER_CC1NE_Pos        (2U)\n#define TIM_CCER_CC1NE_Msk        (0x1U << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */\n#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */\n#define TIM_CCER_CC1NP_Pos        (3U)\n#define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */\n#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */\n#define TIM_CCER_CC2E_Pos         (4U)\n#define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */\n#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */\n#define TIM_CCER_CC2P_Pos         (5U)\n#define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */\n#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */\n#define TIM_CCER_CC2NE_Pos        (6U)\n#define TIM_CCER_CC2NE_Msk        (0x1U << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */\n#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */\n#define TIM_CCER_CC2NP_Pos        (7U)\n#define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */\n#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */\n#define TIM_CCER_CC3E_Pos         (8U)\n#define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */\n#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */\n#define TIM_CCER_CC3P_Pos         (9U)\n#define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */\n#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */\n#define TIM_CCER_CC3NE_Pos        (10U)\n#define TIM_CCER_CC3NE_Msk        (0x1U << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */\n#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */\n#define TIM_CCER_CC3NP_Pos        (11U)\n#define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */\n#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */\n#define TIM_CCER_CC4E_Pos         (12U)\n#define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */\n#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */\n#define TIM_CCER_CC4P_Pos         (13U)\n#define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */\n#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */\n#define TIM_CCER_CC4NP_Pos        (15U)\n#define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */\n#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */\n\n/*******************  Bit definition for TIM_CNT register  ********************/\n#define TIM_CNT_CNT_Pos           (0U)\n#define TIM_CNT_CNT_Msk           (0xFFFFFFFFU << TIM_CNT_CNT_Pos)                 /*!< 0xFFFFFFFF */\n#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                                  /*!<Counter Value            */\n\n/*******************  Bit definition for TIM_PSC register  ********************/\n#define TIM_PSC_PSC_Pos           (0U)\n#define TIM_PSC_PSC_Msk           (0xFFFFU << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */\n#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */\n\n/*******************  Bit definition for TIM_ARR register  ********************/\n#define TIM_ARR_ARR_Pos           (0U)\n#define TIM_ARR_ARR_Msk           (0xFFFFFFFFU << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */\n#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */\n\n/*******************  Bit definition for TIM_RCR register  ********************/\n#define TIM_RCR_REP_Pos           (0U)\n#define TIM_RCR_REP_Msk           (0xFFU << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */\n#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */\n\n/*******************  Bit definition for TIM_CCR1 register  *******************/\n#define TIM_CCR1_CCR1_Pos         (0U)\n#define TIM_CCR1_CCR1_Msk         (0xFFFFU << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */\n\n/*******************  Bit definition for TIM_CCR2 register  *******************/\n#define TIM_CCR2_CCR2_Pos         (0U)\n#define TIM_CCR2_CCR2_Msk         (0xFFFFU << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */\n\n/*******************  Bit definition for TIM_CCR3 register  *******************/\n#define TIM_CCR3_CCR3_Pos         (0U)\n#define TIM_CCR3_CCR3_Msk         (0xFFFFU << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */\n\n/*******************  Bit definition for TIM_CCR4 register  *******************/\n#define TIM_CCR4_CCR4_Pos         (0U)\n#define TIM_CCR4_CCR4_Msk         (0xFFFFU << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */\n\n/*******************  Bit definition for TIM_BDTR register  *******************/\n#define TIM_BDTR_DTG_Pos          (0U)\n#define TIM_BDTR_DTG_Msk          (0xFFU << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */\n#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\n#define TIM_BDTR_DTG_0            (0x01U << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */\n#define TIM_BDTR_DTG_1            (0x02U << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */\n#define TIM_BDTR_DTG_2            (0x04U << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */\n#define TIM_BDTR_DTG_3            (0x08U << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */\n#define TIM_BDTR_DTG_4            (0x10U << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */\n#define TIM_BDTR_DTG_5            (0x20U << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */\n#define TIM_BDTR_DTG_6            (0x40U << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */\n#define TIM_BDTR_DTG_7            (0x80U << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */\n\n#define TIM_BDTR_LOCK_Pos         (8U)\n#define TIM_BDTR_LOCK_Msk         (0x3U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */\n#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */\n#define TIM_BDTR_LOCK_0           (0x1U << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */\n#define TIM_BDTR_LOCK_1           (0x2U << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */\n\n#define TIM_BDTR_OSSI_Pos         (10U)\n#define TIM_BDTR_OSSI_Msk         (0x1U << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */\n#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */\n#define TIM_BDTR_OSSR_Pos         (11U)\n#define TIM_BDTR_OSSR_Msk         (0x1U << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */\n#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */\n#define TIM_BDTR_BKE_Pos          (12U)\n#define TIM_BDTR_BKE_Msk          (0x1U << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */\n#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */\n#define TIM_BDTR_BKP_Pos          (13U)\n#define TIM_BDTR_BKP_Msk          (0x1U << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */\n#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */\n#define TIM_BDTR_AOE_Pos          (14U)\n#define TIM_BDTR_AOE_Msk          (0x1U << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */\n#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */\n#define TIM_BDTR_MOE_Pos          (15U)\n#define TIM_BDTR_MOE_Msk          (0x1U << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */\n#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */\n\n/*******************  Bit definition for TIM_DCR register  ********************/\n#define TIM_DCR_DBA_Pos           (0U)\n#define TIM_DCR_DBA_Msk           (0x1FU << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */\n#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */\n#define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */\n#define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */\n#define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */\n#define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */\n#define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */\n\n#define TIM_DCR_DBL_Pos           (8U)\n#define TIM_DCR_DBL_Msk           (0x1FU << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */\n#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */\n#define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */\n#define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */\n#define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */\n#define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */\n#define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */\n\n/*******************  Bit definition for TIM_DMAR register  *******************/\n#define TIM_DMAR_DMAB_Pos         (0U)\n#define TIM_DMAR_DMAB_Msk         (0xFFFFU << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */\n#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */\n\n/*******************  Bit definition for TIM_OR register  *********************/\n#define TIM_OR_TI1_RMP_Pos        (0U)\n#define TIM_OR_TI1_RMP_Msk        (0x3U << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000003 */\n#define TIM_OR_TI1_RMP            TIM_OR_TI1_RMP_Msk                           /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */\n#define TIM_OR_TI1_RMP_0          (0x1U << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000001 */\n#define TIM_OR_TI1_RMP_1          (0x2U << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000002 */\n\n#define TIM_OR_TI4_RMP_Pos        (6U)\n#define TIM_OR_TI4_RMP_Msk        (0x3U << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */\n#define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */\n#define TIM_OR_TI4_RMP_0          (0x1U << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */\n#define TIM_OR_TI4_RMP_1          (0x2U << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */\n#define TIM_OR_ITR1_RMP_Pos       (10U)\n#define TIM_OR_ITR1_RMP_Msk       (0x3U << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */\n#define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\n#define TIM_OR_ITR1_RMP_0         (0x1U << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */\n#define TIM_OR_ITR1_RMP_1         (0x2U << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*         Universal Synchronous Asynchronous Receiver Transmitter            */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for USART_SR register  *******************/\n#define USART_SR_PE_Pos               (0U)\n#define USART_SR_PE_Msk               (0x1U << USART_SR_PE_Pos)                /*!< 0x00000001 */\n#define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */\n#define USART_SR_FE_Pos               (1U)\n#define USART_SR_FE_Msk               (0x1U << USART_SR_FE_Pos)                /*!< 0x00000002 */\n#define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */\n#define USART_SR_NE_Pos               (2U)\n#define USART_SR_NE_Msk               (0x1U << USART_SR_NE_Pos)                /*!< 0x00000004 */\n#define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */\n#define USART_SR_ORE_Pos              (3U)\n#define USART_SR_ORE_Msk              (0x1U << USART_SR_ORE_Pos)               /*!< 0x00000008 */\n#define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */\n#define USART_SR_IDLE_Pos             (4U)\n#define USART_SR_IDLE_Msk             (0x1U << USART_SR_IDLE_Pos)              /*!< 0x00000010 */\n#define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */\n#define USART_SR_RXNE_Pos             (5U)\n#define USART_SR_RXNE_Msk             (0x1U << USART_SR_RXNE_Pos)              /*!< 0x00000020 */\n#define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */\n#define USART_SR_TC_Pos               (6U)\n#define USART_SR_TC_Msk               (0x1U << USART_SR_TC_Pos)                /*!< 0x00000040 */\n#define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */\n#define USART_SR_TXE_Pos              (7U)\n#define USART_SR_TXE_Msk              (0x1U << USART_SR_TXE_Pos)               /*!< 0x00000080 */\n#define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */\n#define USART_SR_LBD_Pos              (8U)\n#define USART_SR_LBD_Msk              (0x1U << USART_SR_LBD_Pos)               /*!< 0x00000100 */\n#define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */\n#define USART_SR_CTS_Pos              (9U)\n#define USART_SR_CTS_Msk              (0x1U << USART_SR_CTS_Pos)               /*!< 0x00000200 */\n#define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */\n\n/*******************  Bit definition for USART_DR register  *******************/\n#define USART_DR_DR_Pos               (0U)\n#define USART_DR_DR_Msk               (0x1FFU << USART_DR_DR_Pos)              /*!< 0x000001FF */\n#define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */\n\n/******************  Bit definition for USART_BRR register  *******************/\n#define USART_BRR_DIV_Fraction_Pos    (0U)\n#define USART_BRR_DIV_Fraction_Msk    (0xFU << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */\n#define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */\n#define USART_BRR_DIV_Mantissa_Pos    (4U)\n#define USART_BRR_DIV_Mantissa_Msk    (0xFFFU << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */\n#define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */\n\n/******************  Bit definition for USART_CR1 register  *******************/\n#define USART_CR1_SBK_Pos             (0U)\n#define USART_CR1_SBK_Msk             (0x1U << USART_CR1_SBK_Pos)              /*!< 0x00000001 */\n#define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */\n#define USART_CR1_RWU_Pos             (1U)\n#define USART_CR1_RWU_Msk             (0x1U << USART_CR1_RWU_Pos)              /*!< 0x00000002 */\n#define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */\n#define USART_CR1_RE_Pos              (2U)\n#define USART_CR1_RE_Msk              (0x1U << USART_CR1_RE_Pos)               /*!< 0x00000004 */\n#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */\n#define USART_CR1_TE_Pos              (3U)\n#define USART_CR1_TE_Msk              (0x1U << USART_CR1_TE_Pos)               /*!< 0x00000008 */\n#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */\n#define USART_CR1_IDLEIE_Pos          (4U)\n#define USART_CR1_IDLEIE_Msk          (0x1U << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */\n#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */\n#define USART_CR1_RXNEIE_Pos          (5U)\n#define USART_CR1_RXNEIE_Msk          (0x1U << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */\n#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */\n#define USART_CR1_TCIE_Pos            (6U)\n#define USART_CR1_TCIE_Msk            (0x1U << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */\n#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */\n#define USART_CR1_TXEIE_Pos           (7U)\n#define USART_CR1_TXEIE_Msk           (0x1U << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */\n#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<PE Interrupt Enable                    */\n#define USART_CR1_PEIE_Pos            (8U)\n#define USART_CR1_PEIE_Msk            (0x1U << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */\n#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */\n#define USART_CR1_PS_Pos              (9U)\n#define USART_CR1_PS_Msk              (0x1U << USART_CR1_PS_Pos)               /*!< 0x00000200 */\n#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */\n#define USART_CR1_PCE_Pos             (10U)\n#define USART_CR1_PCE_Msk             (0x1U << USART_CR1_PCE_Pos)              /*!< 0x00000400 */\n#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */\n#define USART_CR1_WAKE_Pos            (11U)\n#define USART_CR1_WAKE_Msk            (0x1U << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */\n#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */\n#define USART_CR1_M_Pos               (12U)\n#define USART_CR1_M_Msk               (0x1U << USART_CR1_M_Pos)                /*!< 0x00001000 */\n#define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */\n#define USART_CR1_UE_Pos              (13U)\n#define USART_CR1_UE_Msk              (0x1U << USART_CR1_UE_Pos)               /*!< 0x00002000 */\n#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */\n#define USART_CR1_OVER8_Pos           (15U)\n#define USART_CR1_OVER8_Msk           (0x1U << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */\n#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */\n\n/******************  Bit definition for USART_CR2 register  *******************/\n#define USART_CR2_ADD_Pos             (0U)\n#define USART_CR2_ADD_Msk             (0xFU << USART_CR2_ADD_Pos)              /*!< 0x0000000F */\n#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */\n#define USART_CR2_LBDL_Pos            (5U)\n#define USART_CR2_LBDL_Msk            (0x1U << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */\n#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */\n#define USART_CR2_LBDIE_Pos           (6U)\n#define USART_CR2_LBDIE_Msk           (0x1U << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */\n#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */\n#define USART_CR2_LBCL_Pos            (8U)\n#define USART_CR2_LBCL_Msk            (0x1U << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */\n#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */\n#define USART_CR2_CPHA_Pos            (9U)\n#define USART_CR2_CPHA_Msk            (0x1U << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */\n#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */\n#define USART_CR2_CPOL_Pos            (10U)\n#define USART_CR2_CPOL_Msk            (0x1U << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */\n#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */\n#define USART_CR2_CLKEN_Pos           (11U)\n#define USART_CR2_CLKEN_Msk           (0x1U << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */\n#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */\n\n#define USART_CR2_STOP_Pos            (12U)\n#define USART_CR2_STOP_Msk            (0x3U << USART_CR2_STOP_Pos)             /*!< 0x00003000 */\n#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */\n#define USART_CR2_STOP_0              (0x1U << USART_CR2_STOP_Pos)             /*!< 0x1000 */\n#define USART_CR2_STOP_1              (0x2U << USART_CR2_STOP_Pos)             /*!< 0x2000 */\n\n#define USART_CR2_LINEN_Pos           (14U)\n#define USART_CR2_LINEN_Msk           (0x1U << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */\n#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */\n\n/******************  Bit definition for USART_CR3 register  *******************/\n#define USART_CR3_EIE_Pos             (0U)\n#define USART_CR3_EIE_Msk             (0x1U << USART_CR3_EIE_Pos)              /*!< 0x00000001 */\n#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */\n#define USART_CR3_IREN_Pos            (1U)\n#define USART_CR3_IREN_Msk            (0x1U << USART_CR3_IREN_Pos)             /*!< 0x00000002 */\n#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */\n#define USART_CR3_IRLP_Pos            (2U)\n#define USART_CR3_IRLP_Msk            (0x1U << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */\n#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */\n#define USART_CR3_HDSEL_Pos           (3U)\n#define USART_CR3_HDSEL_Msk           (0x1U << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */\n#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */\n#define USART_CR3_NACK_Pos            (4U)\n#define USART_CR3_NACK_Msk            (0x1U << USART_CR3_NACK_Pos)             /*!< 0x00000010 */\n#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */\n#define USART_CR3_SCEN_Pos            (5U)\n#define USART_CR3_SCEN_Msk            (0x1U << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */\n#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */\n#define USART_CR3_DMAR_Pos            (6U)\n#define USART_CR3_DMAR_Msk            (0x1U << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */\n#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */\n#define USART_CR3_DMAT_Pos            (7U)\n#define USART_CR3_DMAT_Msk            (0x1U << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */\n#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */\n#define USART_CR3_RTSE_Pos            (8U)\n#define USART_CR3_RTSE_Msk            (0x1U << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */\n#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */\n#define USART_CR3_CTSE_Pos            (9U)\n#define USART_CR3_CTSE_Msk            (0x1U << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */\n#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */\n#define USART_CR3_CTSIE_Pos           (10U)\n#define USART_CR3_CTSIE_Msk           (0x1U << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */\n#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */\n#define USART_CR3_ONEBIT_Pos          (11U)\n#define USART_CR3_ONEBIT_Msk          (0x1U << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */\n#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */\n\n/******************  Bit definition for USART_GTPR register  ******************/\n#define USART_GTPR_PSC_Pos            (0U)\n#define USART_GTPR_PSC_Msk            (0xFFU << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */\n#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */\n#define USART_GTPR_PSC_0              (0x01U << USART_GTPR_PSC_Pos)            /*!< 0x0001 */\n#define USART_GTPR_PSC_1              (0x02U << USART_GTPR_PSC_Pos)            /*!< 0x0002 */\n#define USART_GTPR_PSC_2              (0x04U << USART_GTPR_PSC_Pos)            /*!< 0x0004 */\n#define USART_GTPR_PSC_3              (0x08U << USART_GTPR_PSC_Pos)            /*!< 0x0008 */\n#define USART_GTPR_PSC_4              (0x10U << USART_GTPR_PSC_Pos)            /*!< 0x0010 */\n#define USART_GTPR_PSC_5              (0x20U << USART_GTPR_PSC_Pos)            /*!< 0x0020 */\n#define USART_GTPR_PSC_6              (0x40U << USART_GTPR_PSC_Pos)            /*!< 0x0040 */\n#define USART_GTPR_PSC_7              (0x80U << USART_GTPR_PSC_Pos)            /*!< 0x0080 */\n\n#define USART_GTPR_GT_Pos             (8U)\n#define USART_GTPR_GT_Msk             (0xFFU << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */\n#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            Window WATCHDOG                                 */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for WWDG_CR register  ********************/\n#define WWDG_CR_T_Pos           (0U)\n#define WWDG_CR_T_Msk           (0x7FU << WWDG_CR_T_Pos)                       /*!< 0x0000007F */\n#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\n#define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x01 */\n#define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x02 */\n#define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x04 */\n#define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x08 */\n#define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x10 */\n#define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x20 */\n#define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x40 */\n/* Legacy defines */\n#define  WWDG_CR_T0                          WWDG_CR_T_0\n#define  WWDG_CR_T1                          WWDG_CR_T_1\n#define  WWDG_CR_T2                          WWDG_CR_T_2\n#define  WWDG_CR_T3                          WWDG_CR_T_3\n#define  WWDG_CR_T4                          WWDG_CR_T_4\n#define  WWDG_CR_T5                          WWDG_CR_T_5\n#define  WWDG_CR_T6                          WWDG_CR_T_6\n\n#define WWDG_CR_WDGA_Pos        (7U)\n#define WWDG_CR_WDGA_Msk        (0x1U << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */\n#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */\n\n/*******************  Bit definition for WWDG_CFR register  *******************/\n#define WWDG_CFR_W_Pos          (0U)\n#define WWDG_CFR_W_Msk          (0x7FU << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */\n#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */\n#define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x0001 */\n#define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x0002 */\n#define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x0004 */\n#define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x0008 */\n#define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x0010 */\n#define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x0020 */\n#define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x0040 */\n/* Legacy defines */\n#define  WWDG_CFR_W0                         WWDG_CFR_W_0\n#define  WWDG_CFR_W1                         WWDG_CFR_W_1\n#define  WWDG_CFR_W2                         WWDG_CFR_W_2\n#define  WWDG_CFR_W3                         WWDG_CFR_W_3\n#define  WWDG_CFR_W4                         WWDG_CFR_W_4\n#define  WWDG_CFR_W5                         WWDG_CFR_W_5\n#define  WWDG_CFR_W6                         WWDG_CFR_W_6\n\n#define WWDG_CFR_WDGTB_Pos      (7U)\n#define WWDG_CFR_WDGTB_Msk      (0x3U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */\n#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */\n#define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */\n#define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */\n/* Legacy defines */\n#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0\n#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1\n\n#define WWDG_CFR_EWI_Pos        (9U)\n#define WWDG_CFR_EWI_Msk        (0x1U << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */\n#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */\n\n/*******************  Bit definition for WWDG_SR register  ********************/\n#define WWDG_SR_EWIF_Pos        (0U)\n#define WWDG_SR_EWIF_Msk        (0x1U << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */\n#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                DBG                                         */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for DBGMCU_IDCODE register  *************/\n#define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)\n#define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\n#define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk\n#define DBGMCU_IDCODE_REV_ID_Pos                     (16U)\n#define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\n#define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk\n\n/********************  Bit definition for DBGMCU_CR register  *****************/\n#define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)\n#define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */\n#define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk\n#define DBGMCU_CR_DBG_STOP_Pos                       (1U)\n#define DBGMCU_CR_DBG_STOP_Msk                       (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk\n#define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)\n#define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */\n#define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk\n#define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)\n#define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */\n#define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk\n\n#define DBGMCU_CR_TRACE_MODE_Pos                     (6U)\n#define DBGMCU_CR_TRACE_MODE_Msk                     (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */\n#define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk\n#define DBGMCU_CR_TRACE_MODE_0                       (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */\n#define DBGMCU_CR_TRACE_MODE_1                       (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */\n\n/********************  Bit definition for DBGMCU_APB1_FZ register  ************/\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk\n/* Old IWDGSTOP bit definition, maintained for legacy purpose */\n#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP\n\n/********************  Bit definition for DBGMCU_APB2_FZ register  ************/\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                Ethernet MAC Registers bits definitions                     */\n/*                                                                            */\n/******************************************************************************/\n/* Bit definition for Ethernet MAC Control Register register */\n#define ETH_MACCR_WD_Pos                              (23U)\n#define ETH_MACCR_WD_Msk                              (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */\n#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */\n#define ETH_MACCR_JD_Pos                              (22U)\n#define ETH_MACCR_JD_Msk                              (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */\n#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */\n#define ETH_MACCR_IFG_Pos                             (17U)\n#define ETH_MACCR_IFG_Msk                             (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */\n#define ETH_MACCR_IFG                                 ETH_MACCR_IFG_Msk        /* Inter-frame gap */\n#define ETH_MACCR_IFG_96Bit                           0x00000000U              /* Minimum IFG between frames during transmission is 96Bit */\n#define ETH_MACCR_IFG_88Bit                           0x00020000U              /* Minimum IFG between frames during transmission is 88Bit */\n#define ETH_MACCR_IFG_80Bit                           0x00040000U              /* Minimum IFG between frames during transmission is 80Bit */\n#define ETH_MACCR_IFG_72Bit                           0x00060000U              /* Minimum IFG between frames during transmission is 72Bit */\n#define ETH_MACCR_IFG_64Bit                           0x00080000U              /* Minimum IFG between frames during transmission is 64Bit */\n#define ETH_MACCR_IFG_56Bit                           0x000A0000U              /* Minimum IFG between frames during transmission is 56Bit */\n#define ETH_MACCR_IFG_48Bit                           0x000C0000U              /* Minimum IFG between frames during transmission is 48Bit */\n#define ETH_MACCR_IFG_40Bit                           0x000E0000U              /* Minimum IFG between frames during transmission is 40Bit */\n#define ETH_MACCR_CSD_Pos                             (16U)\n#define ETH_MACCR_CSD_Msk                             (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */\n#define ETH_MACCR_CSD                                 ETH_MACCR_CSD_Msk        /* Carrier sense disable (during transmission) */\n#define ETH_MACCR_FES_Pos                             (14U)\n#define ETH_MACCR_FES_Msk                             (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */\n#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */\n#define ETH_MACCR_ROD_Pos                             (13U)\n#define ETH_MACCR_ROD_Msk                             (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */\n#define ETH_MACCR_ROD                                 ETH_MACCR_ROD_Msk        /* Receive own disable */\n#define ETH_MACCR_LM_Pos                              (12U)\n#define ETH_MACCR_LM_Msk                              (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */\n#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */\n#define ETH_MACCR_DM_Pos                              (11U)\n#define ETH_MACCR_DM_Msk                              (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */\n#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */\n#define ETH_MACCR_IPCO_Pos                            (10U)\n#define ETH_MACCR_IPCO_Msk                            (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */\n#define ETH_MACCR_IPCO                                ETH_MACCR_IPCO_Msk       /* IP Checksum offload */\n#define ETH_MACCR_RD_Pos                              (9U)\n#define ETH_MACCR_RD_Msk                              (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */\n#define ETH_MACCR_RD                                  ETH_MACCR_RD_Msk         /* Retry disable */\n#define ETH_MACCR_APCS_Pos                            (7U)\n#define ETH_MACCR_APCS_Msk                            (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */\n#define ETH_MACCR_APCS                                ETH_MACCR_APCS_Msk       /* Automatic Pad/CRC stripping */\n#define ETH_MACCR_BL_Pos                              (5U)\n#define ETH_MACCR_BL_Msk                              (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */\n#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit: random integer number (r) of slot time delays before rescheduling\n                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */\n#define ETH_MACCR_BL_10                               0x00000000U              /* k = min (n, 10) */\n#define ETH_MACCR_BL_8                                0x00000020U              /* k = min (n, 8) */\n#define ETH_MACCR_BL_4                                0x00000040U              /* k = min (n, 4) */\n#define ETH_MACCR_BL_1                                0x00000060U              /* k = min (n, 1) */\n#define ETH_MACCR_DC_Pos                              (4U)\n#define ETH_MACCR_DC_Msk                              (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */\n#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */\n#define ETH_MACCR_TE_Pos                              (3U)\n#define ETH_MACCR_TE_Msk                              (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */\n#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */\n#define ETH_MACCR_RE_Pos                              (2U)\n#define ETH_MACCR_RE_Msk                              (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */\n#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */\n\n/* Bit definition for Ethernet MAC Frame Filter Register */\n#define ETH_MACFFR_RA_Pos                             (31U)\n#define ETH_MACFFR_RA_Msk                             (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */\n#define ETH_MACFFR_RA                                 ETH_MACFFR_RA_Msk        /* Receive all */\n#define ETH_MACFFR_HPF_Pos                            (10U)\n#define ETH_MACFFR_HPF_Msk                            (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */\n#define ETH_MACFFR_HPF                                ETH_MACFFR_HPF_Msk       /* Hash or perfect filter */\n#define ETH_MACFFR_SAF_Pos                            (9U)\n#define ETH_MACFFR_SAF_Msk                            (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */\n#define ETH_MACFFR_SAF                                ETH_MACFFR_SAF_Msk       /* Source address filter enable */\n#define ETH_MACFFR_SAIF_Pos                           (8U)\n#define ETH_MACFFR_SAIF_Msk                           (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */\n#define ETH_MACFFR_SAIF                               ETH_MACFFR_SAIF_Msk      /* SA inverse filtering */\n#define ETH_MACFFR_PCF_Pos                            (6U)\n#define ETH_MACFFR_PCF_Msk                            (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */\n#define ETH_MACFFR_PCF                                ETH_MACFFR_PCF_Msk       /* Pass control frames: 3 cases */\n#define ETH_MACFFR_PCF_BlockAll_Pos                   (6U)\n#define ETH_MACFFR_PCF_BlockAll_Msk                   (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */\n#define ETH_MACFFR_PCF_BlockAll                       ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */\n#define ETH_MACFFR_PCF_ForwardAll_Pos                 (7U)\n#define ETH_MACFFR_PCF_ForwardAll_Msk                 (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */\n#define ETH_MACFFR_PCF_ForwardAll                     ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */\n#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos    (6U)\n#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk    (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */\n#define ETH_MACFFR_PCF_ForwardPassedAddrFilter        ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */\n#define ETH_MACFFR_BFD_Pos                            (5U)\n#define ETH_MACFFR_BFD_Msk                            (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */\n#define ETH_MACFFR_BFD                                ETH_MACFFR_BFD_Msk       /* Broadcast frame disable */\n#define ETH_MACFFR_PAM_Pos                            (4U)\n#define ETH_MACFFR_PAM_Msk                            (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */\n#define ETH_MACFFR_PAM                                ETH_MACFFR_PAM_Msk       /* Pass all mutlicast */\n#define ETH_MACFFR_DAIF_Pos                           (3U)\n#define ETH_MACFFR_DAIF_Msk                           (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */\n#define ETH_MACFFR_DAIF                               ETH_MACFFR_DAIF_Msk      /* DA Inverse filtering */\n#define ETH_MACFFR_HM_Pos                             (2U)\n#define ETH_MACFFR_HM_Msk                             (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */\n#define ETH_MACFFR_HM                                 ETH_MACFFR_HM_Msk        /* Hash multicast */\n#define ETH_MACFFR_HU_Pos                             (1U)\n#define ETH_MACFFR_HU_Msk                             (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */\n#define ETH_MACFFR_HU                                 ETH_MACFFR_HU_Msk        /* Hash unicast */\n#define ETH_MACFFR_PM_Pos                             (0U)\n#define ETH_MACFFR_PM_Msk                             (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */\n#define ETH_MACFFR_PM                                 ETH_MACFFR_PM_Msk        /* Promiscuous mode */\n\n/* Bit definition for Ethernet MAC Hash Table High Register */\n#define ETH_MACHTHR_HTH_Pos                           (0U)\n#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */\n\n/* Bit definition for Ethernet MAC Hash Table Low Register */\n#define ETH_MACHTLR_HTL_Pos                           (0U)\n#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */\n\n/* Bit definition for Ethernet MAC MII Address Register */\n#define ETH_MACMIIAR_PA_Pos                           (11U)\n#define ETH_MACMIIAR_PA_Msk                           (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */\n#define ETH_MACMIIAR_PA                               ETH_MACMIIAR_PA_Msk      /* Physical layer address */\n#define ETH_MACMIIAR_MR_Pos                           (6U)\n#define ETH_MACMIIAR_MR_Msk                           (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */\n#define ETH_MACMIIAR_MR                               ETH_MACMIIAR_MR_Msk      /* MII register in the selected PHY */\n#define ETH_MACMIIAR_CR_Pos                           (2U)\n#define ETH_MACMIIAR_CR_Msk                           (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */\n#define ETH_MACMIIAR_CR                               ETH_MACMIIAR_CR_Msk      /* CR clock range: 6 cases */\n#define ETH_MACMIIAR_CR_Div42                         0x00000000U              /* HCLK:60-100 MHz; MDC clock= HCLK/42   */\n#define ETH_MACMIIAR_CR_Div62_Pos                     (2U)\n#define ETH_MACMIIAR_CR_Div62_Msk                     (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */\n#define ETH_MACMIIAR_CR_Div62                         ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62  */\n#define ETH_MACMIIAR_CR_Div16_Pos                     (3U)\n#define ETH_MACMIIAR_CR_Div16_Msk                     (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */\n#define ETH_MACMIIAR_CR_Div16                         ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16    */\n#define ETH_MACMIIAR_CR_Div26_Pos                     (2U)\n#define ETH_MACMIIAR_CR_Div26_Msk                     (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */\n#define ETH_MACMIIAR_CR_Div26                         ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26    */\n#define ETH_MACMIIAR_CR_Div102_Pos                    (4U)\n#define ETH_MACMIIAR_CR_Div102_Msk                    (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */\n#define ETH_MACMIIAR_CR_Div102                        ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */\n#define ETH_MACMIIAR_MW_Pos                           (1U)\n#define ETH_MACMIIAR_MW_Msk                           (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */\n#define ETH_MACMIIAR_MW                               ETH_MACMIIAR_MW_Msk      /* MII write */\n#define ETH_MACMIIAR_MB_Pos                           (0U)\n#define ETH_MACMIIAR_MB_Msk                           (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */\n#define ETH_MACMIIAR_MB                               ETH_MACMIIAR_MB_Msk      /* MII busy  */\n\n/* Bit definition for Ethernet MAC MII Data Register */\n#define ETH_MACMIIDR_MD_Pos                           (0U)\n#define ETH_MACMIIDR_MD_Msk                           (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */\n#define ETH_MACMIIDR_MD                               ETH_MACMIIDR_MD_Msk      /* MII data: read/write data from/to PHY */\n\n/* Bit definition for Ethernet MAC Flow Control Register */\n#define ETH_MACFCR_PT_Pos                             (16U)\n#define ETH_MACFCR_PT_Msk                             (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */\n#define ETH_MACFCR_PT                                 ETH_MACFCR_PT_Msk        /* Pause time */\n#define ETH_MACFCR_ZQPD_Pos                           (7U)\n#define ETH_MACFCR_ZQPD_Msk                           (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */\n#define ETH_MACFCR_ZQPD                               ETH_MACFCR_ZQPD_Msk      /* Zero-quanta pause disable */\n#define ETH_MACFCR_PLT_Pos                            (4U)\n#define ETH_MACFCR_PLT_Msk                            (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */\n#define ETH_MACFCR_PLT                                ETH_MACFCR_PLT_Msk       /* Pause low threshold: 4 cases */\n#define ETH_MACFCR_PLT_Minus4                         0x00000000U              /* Pause time minus 4 slot times   */\n#define ETH_MACFCR_PLT_Minus28_Pos                    (4U)\n#define ETH_MACFCR_PLT_Minus28_Msk                    (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */\n#define ETH_MACFCR_PLT_Minus28                        ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times  */\n#define ETH_MACFCR_PLT_Minus144_Pos                   (5U)\n#define ETH_MACFCR_PLT_Minus144_Msk                   (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */\n#define ETH_MACFCR_PLT_Minus144                       ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */\n#define ETH_MACFCR_PLT_Minus256_Pos                   (4U)\n#define ETH_MACFCR_PLT_Minus256_Msk                   (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */\n#define ETH_MACFCR_PLT_Minus256                       ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */\n#define ETH_MACFCR_UPFD_Pos                           (3U)\n#define ETH_MACFCR_UPFD_Msk                           (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */\n#define ETH_MACFCR_UPFD                               ETH_MACFCR_UPFD_Msk      /* Unicast pause frame detect */\n#define ETH_MACFCR_RFCE_Pos                           (2U)\n#define ETH_MACFCR_RFCE_Msk                           (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */\n#define ETH_MACFCR_RFCE                               ETH_MACFCR_RFCE_Msk      /* Receive flow control enable */\n#define ETH_MACFCR_TFCE_Pos                           (1U)\n#define ETH_MACFCR_TFCE_Msk                           (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */\n#define ETH_MACFCR_TFCE                               ETH_MACFCR_TFCE_Msk      /* Transmit flow control enable */\n#define ETH_MACFCR_FCBBPA_Pos                         (0U)\n#define ETH_MACFCR_FCBBPA_Msk                         (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */\n#define ETH_MACFCR_FCBBPA                             ETH_MACFCR_FCBBPA_Msk    /* Flow control busy/backpressure activate */\n\n/* Bit definition for Ethernet MAC VLAN Tag Register */\n#define ETH_MACVLANTR_VLANTC_Pos                      (16U)\n#define ETH_MACVLANTR_VLANTC_Msk                      (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */\n#define ETH_MACVLANTR_VLANTC                          ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */\n#define ETH_MACVLANTR_VLANTI_Pos                      (0U)\n#define ETH_MACVLANTR_VLANTI_Msk                      (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */\n#define ETH_MACVLANTR_VLANTI                          ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */\n\n/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */\n#define ETH_MACRWUFFR_D_Pos                           (0U)\n#define ETH_MACRWUFFR_D_Msk                           (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACRWUFFR_D                               ETH_MACRWUFFR_D_Msk      /* Wake-up frame filter register data */\n/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.\n   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */\n/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask\n   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask\n   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask\n   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask\n   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -\n                              RSVD - Filter1 Command - RSVD - Filter0 Command\n   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset\n   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16\n   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */\n\n/* Bit definition for Ethernet MAC PMT Control and Status Register */\n#define ETH_MACPMTCSR_WFFRPR_Pos                      (31U)\n#define ETH_MACPMTCSR_WFFRPR_Msk                      (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */\n#define ETH_MACPMTCSR_WFFRPR                          ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */\n#define ETH_MACPMTCSR_GU_Pos                          (9U)\n#define ETH_MACPMTCSR_GU_Msk                          (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */\n#define ETH_MACPMTCSR_GU                              ETH_MACPMTCSR_GU_Msk     /* Global Unicast                              */\n#define ETH_MACPMTCSR_WFR_Pos                         (6U)\n#define ETH_MACPMTCSR_WFR_Msk                         (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */\n#define ETH_MACPMTCSR_WFR                             ETH_MACPMTCSR_WFR_Msk    /* Wake-Up Frame Received                      */\n#define ETH_MACPMTCSR_MPR_Pos                         (5U)\n#define ETH_MACPMTCSR_MPR_Msk                         (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */\n#define ETH_MACPMTCSR_MPR                             ETH_MACPMTCSR_MPR_Msk    /* Magic Packet Received                       */\n#define ETH_MACPMTCSR_WFE_Pos                         (2U)\n#define ETH_MACPMTCSR_WFE_Msk                         (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */\n#define ETH_MACPMTCSR_WFE                             ETH_MACPMTCSR_WFE_Msk    /* Wake-Up Frame Enable                        */\n#define ETH_MACPMTCSR_MPE_Pos                         (1U)\n#define ETH_MACPMTCSR_MPE_Msk                         (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */\n#define ETH_MACPMTCSR_MPE                             ETH_MACPMTCSR_MPE_Msk    /* Magic Packet Enable                         */\n#define ETH_MACPMTCSR_PD_Pos                          (0U)\n#define ETH_MACPMTCSR_PD_Msk                          (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */\n#define ETH_MACPMTCSR_PD                              ETH_MACPMTCSR_PD_Msk     /* Power Down                                  */\n\n/* Bit definition for Ethernet MAC debug Register */\n#define ETH_MACDBGR_TFF_Pos                           (25U)\n#define ETH_MACDBGR_TFF_Msk                           (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */\n#define ETH_MACDBGR_TFF                               ETH_MACDBGR_TFF_Msk      /* Tx FIFO full                                                            */\n#define ETH_MACDBGR_TFNE_Pos                          (24U)\n#define ETH_MACDBGR_TFNE_Msk                          (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */\n#define ETH_MACDBGR_TFNE                              ETH_MACDBGR_TFNE_Msk     /* Tx FIFO not empty                                                       */\n#define ETH_MACDBGR_TFWA_Pos                          (22U)\n#define ETH_MACDBGR_TFWA_Msk                          (0x1U << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */\n#define ETH_MACDBGR_TFWA                              ETH_MACDBGR_TFWA_Msk     /* Tx FIFO write active                                                    */\n#define ETH_MACDBGR_TFRS_Pos                          (20U)\n#define ETH_MACDBGR_TFRS_Msk                          (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */\n#define ETH_MACDBGR_TFRS                              ETH_MACDBGR_TFRS_Msk     /* Tx FIFO read status mask                                                */\n#define ETH_MACDBGR_TFRS_WRITING_Pos                  (20U)\n#define ETH_MACDBGR_TFRS_WRITING_Msk                  (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */\n#define ETH_MACDBGR_TFRS_WRITING                      ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO                    */\n#define ETH_MACDBGR_TFRS_WAITING_Pos                  (21U)\n#define ETH_MACDBGR_TFRS_WAITING_Msk                  (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */\n#define ETH_MACDBGR_TFRS_WAITING                      ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter                               */\n#define ETH_MACDBGR_TFRS_READ_Pos                     (20U)\n#define ETH_MACDBGR_TFRS_READ_Msk                     (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */\n#define ETH_MACDBGR_TFRS_READ                         ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter)                   */\n#define ETH_MACDBGR_TFRS_IDLE                         0x00000000U              /* Idle state                                                              */\n#define ETH_MACDBGR_MTP_Pos                           (19U)\n#define ETH_MACDBGR_MTP_Msk                           (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */\n#define ETH_MACDBGR_MTP                               ETH_MACDBGR_MTP_Msk      /* MAC transmitter in pause                                                */\n#define ETH_MACDBGR_MTFCS_Pos                         (17U)\n#define ETH_MACDBGR_MTFCS_Msk                         (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */\n#define ETH_MACDBGR_MTFCS                             ETH_MACDBGR_MTFCS_Msk    /* MAC transmit frame controller status mask                               */\n#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos            (17U)\n#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk            (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */\n#define ETH_MACDBGR_MTFCS_TRANSFERRING                ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission                               */\n#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos           (18U)\n#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk           (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */\n#define ETH_MACDBGR_MTFCS_GENERATINGPCF               ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */\n#define ETH_MACDBGR_MTFCS_WAITING_Pos                 (17U)\n#define ETH_MACDBGR_MTFCS_WAITING_Msk                 (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */\n#define ETH_MACDBGR_MTFCS_WAITING                     ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over   */\n#define ETH_MACDBGR_MTFCS_IDLE                        0x00000000U              /* Idle                                                                    */\n#define ETH_MACDBGR_MMTEA_Pos                         (16U)\n#define ETH_MACDBGR_MMTEA_Msk                         (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */\n#define ETH_MACDBGR_MMTEA                             ETH_MACDBGR_MMTEA_Msk    /* MAC MII transmit engine active                                          */\n#define ETH_MACDBGR_RFFL_Pos                          (8U)\n#define ETH_MACDBGR_RFFL_Msk                          (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */\n#define ETH_MACDBGR_RFFL                              ETH_MACDBGR_RFFL_Msk     /* Rx FIFO fill level mask                                                 */\n#define ETH_MACDBGR_RFFL_FULL_Pos                     (8U)\n#define ETH_MACDBGR_RFFL_FULL_Msk                     (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */\n#define ETH_MACDBGR_RFFL_FULL                         ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full                                                             */\n#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos                 (9U)\n#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk                 (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */\n#define ETH_MACDBGR_RFFL_ABOVEFCT                     ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold                 */\n#define ETH_MACDBGR_RFFL_BELOWFCT_Pos                 (8U)\n#define ETH_MACDBGR_RFFL_BELOWFCT_Msk                 (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */\n#define ETH_MACDBGR_RFFL_BELOWFCT                     ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold              */\n#define ETH_MACDBGR_RFFL_EMPTY                        0x00000000U              /* RxFIFO empty                                                            */\n#define ETH_MACDBGR_RFRCS_Pos                         (5U)\n#define ETH_MACDBGR_RFRCS_Msk                         (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */\n#define ETH_MACDBGR_RFRCS                             ETH_MACDBGR_RFRCS_Msk    /* Rx FIFO read controller status mask                                     */\n#define ETH_MACDBGR_RFRCS_FLUSHING_Pos                (5U)\n#define ETH_MACDBGR_RFRCS_FLUSHING_Msk                (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */\n#define ETH_MACDBGR_RFRCS_FLUSHING                    ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status                                      */\n#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos           (6U)\n#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk           (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */\n#define ETH_MACDBGR_RFRCS_STATUSREADING               ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp)                                    */\n#define ETH_MACDBGR_RFRCS_DATAREADING_Pos             (5U)\n#define ETH_MACDBGR_RFRCS_DATAREADING_Msk             (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */\n#define ETH_MACDBGR_RFRCS_DATAREADING                 ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data                                                      */\n#define ETH_MACDBGR_RFRCS_IDLE                        0x00000000U              /* IDLE state                                                              */\n#define ETH_MACDBGR_RFWRA_Pos                         (4U)\n#define ETH_MACDBGR_RFWRA_Msk                         (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */\n#define ETH_MACDBGR_RFWRA                             ETH_MACDBGR_RFWRA_Msk    /* Rx FIFO write controller active                                         */\n#define ETH_MACDBGR_MSFRWCS_Pos                       (1U)\n#define ETH_MACDBGR_MSFRWCS_Msk                       (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */\n#define ETH_MACDBGR_MSFRWCS                           ETH_MACDBGR_MSFRWCS_Msk  /* MAC small FIFO read / write controllers status  mask                    */\n#define ETH_MACDBGR_MSFRWCS_1                         (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */\n#define ETH_MACDBGR_MSFRWCS_0                         (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */\n#define ETH_MACDBGR_MMRPEA_Pos                        (0U)\n#define ETH_MACDBGR_MMRPEA_Msk                        (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */\n#define ETH_MACDBGR_MMRPEA                            ETH_MACDBGR_MMRPEA_Msk   /* MAC MII receive protocol engine active                                  */\n\n/* Bit definition for Ethernet MAC Status Register */\n#define ETH_MACSR_TSTS_Pos                            (9U)\n#define ETH_MACSR_TSTS_Msk                            (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */\n#define ETH_MACSR_TSTS                                ETH_MACSR_TSTS_Msk       /* Time stamp trigger status */\n#define ETH_MACSR_MMCTS_Pos                           (6U)\n#define ETH_MACSR_MMCTS_Msk                           (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */\n#define ETH_MACSR_MMCTS                               ETH_MACSR_MMCTS_Msk      /* MMC transmit status       */\n#define ETH_MACSR_MMMCRS_Pos                          (5U)\n#define ETH_MACSR_MMMCRS_Msk                          (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */\n#define ETH_MACSR_MMMCRS                              ETH_MACSR_MMMCRS_Msk     /* MMC receive status        */\n#define ETH_MACSR_MMCS_Pos                            (4U)\n#define ETH_MACSR_MMCS_Msk                            (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */\n#define ETH_MACSR_MMCS                                ETH_MACSR_MMCS_Msk       /* MMC status                */\n#define ETH_MACSR_PMTS_Pos                            (3U)\n#define ETH_MACSR_PMTS_Msk                            (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */\n#define ETH_MACSR_PMTS                                ETH_MACSR_PMTS_Msk       /* PMT status                */\n\n/* Bit definition for Ethernet MAC Interrupt Mask Register */\n#define ETH_MACIMR_TSTIM_Pos                          (9U)\n#define ETH_MACIMR_TSTIM_Msk                          (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */\n#define ETH_MACIMR_TSTIM                              ETH_MACIMR_TSTIM_Msk     /* Time stamp trigger interrupt mask */\n#define ETH_MACIMR_PMTIM_Pos                          (3U)\n#define ETH_MACIMR_PMTIM_Msk                          (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */\n#define ETH_MACIMR_PMTIM                              ETH_MACIMR_PMTIM_Msk     /* PMT interrupt mask                */\n\n/* Bit definition for Ethernet MAC Address0 High Register */\n#define ETH_MACA0HR_MACA0H_Pos                        (0U)\n#define ETH_MACA0HR_MACA0H_Msk                        (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */\n#define ETH_MACA0HR_MACA0H                            ETH_MACA0HR_MACA0H_Msk   /* MAC address0 high */\n\n/* Bit definition for Ethernet MAC Address0 Low Register */\n#define ETH_MACA0LR_MACA0L_Pos                        (0U)\n#define ETH_MACA0LR_MACA0L_Msk                        (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACA0LR_MACA0L                            ETH_MACA0LR_MACA0L_Msk   /* MAC address0 low */\n\n/* Bit definition for Ethernet MAC Address1 High Register */\n#define ETH_MACA1HR_AE_Pos                            (31U)\n#define ETH_MACA1HR_AE_Msk                            (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */\n#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk       /* Address enable */\n#define ETH_MACA1HR_SA_Pos                            (30U)\n#define ETH_MACA1HR_SA_Msk                            (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */\n#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk       /* Source address */\n#define ETH_MACA1HR_MBC_Pos                           (24U)\n#define ETH_MACA1HR_MBC_Msk                           (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */\n#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk      /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\n#define ETH_MACA1HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */\n#define ETH_MACA1HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */\n#define ETH_MACA1HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */\n#define ETH_MACA1HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */\n#define ETH_MACA1HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */\n#define ETH_MACA1HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [7:0]   */\n#define ETH_MACA1HR_MACA1H_Pos                        (0U)\n#define ETH_MACA1HR_MACA1H_Msk                        (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */\n#define ETH_MACA1HR_MACA1H                            ETH_MACA1HR_MACA1H_Msk   /* MAC address1 high */\n\n/* Bit definition for Ethernet MAC Address1 Low Register */\n#define ETH_MACA1LR_MACA1L_Pos                        (0U)\n#define ETH_MACA1LR_MACA1L_Msk                        (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACA1LR_MACA1L                            ETH_MACA1LR_MACA1L_Msk   /* MAC address1 low */\n\n/* Bit definition for Ethernet MAC Address2 High Register */\n#define ETH_MACA2HR_AE_Pos                            (31U)\n#define ETH_MACA2HR_AE_Msk                            (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */\n#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk       /* Address enable */\n#define ETH_MACA2HR_SA_Pos                            (30U)\n#define ETH_MACA2HR_SA_Msk                            (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */\n#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk       /* Source address */\n#define ETH_MACA2HR_MBC_Pos                           (24U)\n#define ETH_MACA2HR_MBC_Msk                           (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */\n#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk      /* Mask byte control */\n#define ETH_MACA2HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */\n#define ETH_MACA2HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */\n#define ETH_MACA2HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */\n#define ETH_MACA2HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */\n#define ETH_MACA2HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */\n#define ETH_MACA2HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70]    */\n#define ETH_MACA2HR_MACA2H_Pos                        (0U)\n#define ETH_MACA2HR_MACA2H_Msk                        (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */\n#define ETH_MACA2HR_MACA2H                            ETH_MACA2HR_MACA2H_Msk   /* MAC address1 high */\n\n/* Bit definition for Ethernet MAC Address2 Low Register */\n#define ETH_MACA2LR_MACA2L_Pos                        (0U)\n#define ETH_MACA2LR_MACA2L_Msk                        (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACA2LR_MACA2L                            ETH_MACA2LR_MACA2L_Msk   /* MAC address2 low */\n\n/* Bit definition for Ethernet MAC Address3 High Register */\n#define ETH_MACA3HR_AE_Pos                            (31U)\n#define ETH_MACA3HR_AE_Msk                            (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */\n#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk       /* Address enable */\n#define ETH_MACA3HR_SA_Pos                            (30U)\n#define ETH_MACA3HR_SA_Msk                            (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */\n#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk       /* Source address */\n#define ETH_MACA3HR_MBC_Pos                           (24U)\n#define ETH_MACA3HR_MBC_Msk                           (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */\n#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk      /* Mask byte control */\n#define ETH_MACA3HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */\n#define ETH_MACA3HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */\n#define ETH_MACA3HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */\n#define ETH_MACA3HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */\n#define ETH_MACA3HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */\n#define ETH_MACA3HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70]    */\n#define ETH_MACA3HR_MACA3H_Pos                        (0U)\n#define ETH_MACA3HR_MACA3H_Msk                        (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */\n#define ETH_MACA3HR_MACA3H                            ETH_MACA3HR_MACA3H_Msk   /* MAC address3 high */\n\n/* Bit definition for Ethernet MAC Address3 Low Register */\n#define ETH_MACA3LR_MACA3L_Pos                        (0U)\n#define ETH_MACA3LR_MACA3L_Msk                        (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACA3LR_MACA3L                            ETH_MACA3LR_MACA3L_Msk   /* MAC address3 low */\n\n/******************************************************************************/\n/*                Ethernet MMC Registers bits definition                      */\n/******************************************************************************/\n\n/* Bit definition for Ethernet MMC Contol Register */\n#define ETH_MMCCR_MCFHP_Pos                           (5U)\n#define ETH_MMCCR_MCFHP_Msk                           (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */\n#define ETH_MMCCR_MCFHP                               ETH_MMCCR_MCFHP_Msk      /* MMC counter Full-Half preset */\n#define ETH_MMCCR_MCP_Pos                             (4U)\n#define ETH_MMCCR_MCP_Msk                             (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */\n#define ETH_MMCCR_MCP                                 ETH_MMCCR_MCP_Msk        /* MMC counter preset           */\n#define ETH_MMCCR_MCF_Pos                             (3U)\n#define ETH_MMCCR_MCF_Msk                             (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */\n#define ETH_MMCCR_MCF                                 ETH_MMCCR_MCF_Msk        /* MMC Counter Freeze           */\n#define ETH_MMCCR_ROR_Pos                             (2U)\n#define ETH_MMCCR_ROR_Msk                             (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */\n#define ETH_MMCCR_ROR                                 ETH_MMCCR_ROR_Msk        /* Reset on Read                */\n#define ETH_MMCCR_CSR_Pos                             (1U)\n#define ETH_MMCCR_CSR_Msk                             (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */\n#define ETH_MMCCR_CSR                                 ETH_MMCCR_CSR_Msk        /* Counter Stop Rollover        */\n#define ETH_MMCCR_CR_Pos                              (0U)\n#define ETH_MMCCR_CR_Msk                              (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */\n#define ETH_MMCCR_CR                                  ETH_MMCCR_CR_Msk         /* Counters Reset               */\n\n/* Bit definition for Ethernet MMC Receive Interrupt Register */\n#define ETH_MMCRIR_RGUFS_Pos                          (17U)\n#define ETH_MMCRIR_RGUFS_Msk                          (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */\n#define ETH_MMCRIR_RGUFS                              ETH_MMCRIR_RGUFS_Msk     /* Set when Rx good unicast frames counter reaches half the maximum value */\n#define ETH_MMCRIR_RFAES_Pos                          (6U)\n#define ETH_MMCRIR_RFAES_Msk                          (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */\n#define ETH_MMCRIR_RFAES                              ETH_MMCRIR_RFAES_Msk     /* Set when Rx alignment error counter reaches half the maximum value */\n#define ETH_MMCRIR_RFCES_Pos                          (5U)\n#define ETH_MMCRIR_RFCES_Msk                          (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */\n#define ETH_MMCRIR_RFCES                              ETH_MMCRIR_RFCES_Msk     /* Set when Rx crc error counter reaches half the maximum value */\n\n/* Bit definition for Ethernet MMC Transmit Interrupt Register */\n#define ETH_MMCTIR_TGFS_Pos                           (21U)\n#define ETH_MMCTIR_TGFS_Msk                           (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */\n#define ETH_MMCTIR_TGFS                               ETH_MMCTIR_TGFS_Msk      /* Set when Tx good frame count counter reaches half the maximum value */\n#define ETH_MMCTIR_TGFMSCS_Pos                        (15U)\n#define ETH_MMCTIR_TGFMSCS_Msk                        (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */\n#define ETH_MMCTIR_TGFMSCS                            ETH_MMCTIR_TGFMSCS_Msk   /* Set when Tx good multi col counter reaches half the maximum value */\n#define ETH_MMCTIR_TGFSCS_Pos                         (14U)\n#define ETH_MMCTIR_TGFSCS_Msk                         (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */\n#define ETH_MMCTIR_TGFSCS                             ETH_MMCTIR_TGFSCS_Msk    /* Set when Tx good single col counter reaches half the maximum value */\n\n/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */\n#define ETH_MMCRIMR_RGUFM_Pos                         (17U)\n#define ETH_MMCRIMR_RGUFM_Msk                         (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */\n#define ETH_MMCRIMR_RGUFM                             ETH_MMCRIMR_RGUFM_Msk    /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */\n#define ETH_MMCRIMR_RFAEM_Pos                         (6U)\n#define ETH_MMCRIMR_RFAEM_Msk                         (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */\n#define ETH_MMCRIMR_RFAEM                             ETH_MMCRIMR_RFAEM_Msk    /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */\n#define ETH_MMCRIMR_RFCEM_Pos                         (5U)\n#define ETH_MMCRIMR_RFCEM_Msk                         (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */\n#define ETH_MMCRIMR_RFCEM                             ETH_MMCRIMR_RFCEM_Msk    /* Mask the interrupt when Rx crc error counter reaches half the maximum value */\n\n/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */\n#define ETH_MMCTIMR_TGFM_Pos                          (21U)\n#define ETH_MMCTIMR_TGFM_Msk                          (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */\n#define ETH_MMCTIMR_TGFM                              ETH_MMCTIMR_TGFM_Msk     /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */\n#define ETH_MMCTIMR_TGFMSCM_Pos                       (15U)\n#define ETH_MMCTIMR_TGFMSCM_Msk                       (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */\n#define ETH_MMCTIMR_TGFMSCM                           ETH_MMCTIMR_TGFMSCM_Msk  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */\n#define ETH_MMCTIMR_TGFSCM_Pos                        (14U)\n#define ETH_MMCTIMR_TGFSCM_Msk                        (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */\n#define ETH_MMCTIMR_TGFSCM                            ETH_MMCTIMR_TGFSCM_Msk   /* Mask the interrupt when Tx good single col counter reaches half the maximum value */\n\n/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */\n#define ETH_MMCTGFSCCR_TGFSCC_Pos                     (0U)\n#define ETH_MMCTGFSCCR_TGFSCC_Msk                     (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCTGFSCCR_TGFSCC                         ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */\n\n/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */\n#define ETH_MMCTGFMSCCR_TGFMSCC_Pos                   (0U)\n#define ETH_MMCTGFMSCCR_TGFMSCC_Msk                   (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCTGFMSCCR_TGFMSCC                       ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */\n\n/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */\n#define ETH_MMCTGFCR_TGFC_Pos                         (0U)\n#define ETH_MMCTGFCR_TGFC_Msk                         (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCTGFCR_TGFC                             ETH_MMCTGFCR_TGFC_Msk    /* Number of good frames transmitted. */\n\n/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */\n#define ETH_MMCRFCECR_RFCEC_Pos                       (0U)\n#define ETH_MMCRFCECR_RFCEC_Msk                       (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCRFCECR_RFCEC                           ETH_MMCRFCECR_RFCEC_Msk  /* Number of frames received with CRC error. */\n\n/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */\n#define ETH_MMCRFAECR_RFAEC_Pos                       (0U)\n#define ETH_MMCRFAECR_RFAEC_Msk                       (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCRFAECR_RFAEC                           ETH_MMCRFAECR_RFAEC_Msk  /* Number of frames received with alignment (dribble) error */\n\n/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */\n#define ETH_MMCRGUFCR_RGUFC_Pos                       (0U)\n#define ETH_MMCRGUFCR_RGUFC_Msk                       (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCRGUFCR_RGUFC                           ETH_MMCRGUFCR_RGUFC_Msk  /* Number of good unicast frames received. */\n\n/******************************************************************************/\n/*               Ethernet PTP Registers bits definition                       */\n/******************************************************************************/\n\n/* Bit definition for Ethernet PTP Time Stamp Contol Register */\n#define ETH_PTPTSCR_TSCNT_Pos                         (16U)\n#define ETH_PTPTSCR_TSCNT_Msk                         (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */\n#define ETH_PTPTSCR_TSCNT                             ETH_PTPTSCR_TSCNT_Msk    /* Time stamp clock node type */\n#define ETH_PTPTSSR_TSSMRME_Pos                       (15U)\n#define ETH_PTPTSSR_TSSMRME_Msk                       (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */\n#define ETH_PTPTSSR_TSSMRME                           ETH_PTPTSSR_TSSMRME_Msk  /* Time stamp snapshot for message relevant to master enable */\n#define ETH_PTPTSSR_TSSEME_Pos                        (14U)\n#define ETH_PTPTSSR_TSSEME_Msk                        (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */\n#define ETH_PTPTSSR_TSSEME                            ETH_PTPTSSR_TSSEME_Msk   /* Time stamp snapshot for event message enable */\n#define ETH_PTPTSSR_TSSIPV4FE_Pos                     (13U)\n#define ETH_PTPTSSR_TSSIPV4FE_Msk                     (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */\n#define ETH_PTPTSSR_TSSIPV4FE                         ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */\n#define ETH_PTPTSSR_TSSIPV6FE_Pos                     (12U)\n#define ETH_PTPTSSR_TSSIPV6FE_Msk                     (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */\n#define ETH_PTPTSSR_TSSIPV6FE                         ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */\n#define ETH_PTPTSSR_TSSPTPOEFE_Pos                    (11U)\n#define ETH_PTPTSSR_TSSPTPOEFE_Msk                    (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */\n#define ETH_PTPTSSR_TSSPTPOEFE                        ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */\n#define ETH_PTPTSSR_TSPTPPSV2E_Pos                    (10U)\n#define ETH_PTPTSSR_TSPTPPSV2E_Msk                    (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */\n#define ETH_PTPTSSR_TSPTPPSV2E                        ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */\n#define ETH_PTPTSSR_TSSSR_Pos                         (9U)\n#define ETH_PTPTSSR_TSSSR_Msk                         (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */\n#define ETH_PTPTSSR_TSSSR                             ETH_PTPTSSR_TSSSR_Msk    /* Time stamp Sub-seconds rollover */\n#define ETH_PTPTSSR_TSSARFE_Pos                       (8U)\n#define ETH_PTPTSSR_TSSARFE_Msk                       (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */\n#define ETH_PTPTSSR_TSSARFE                           ETH_PTPTSSR_TSSARFE_Msk  /* Time stamp snapshot for all received frames enable */\n\n#define ETH_PTPTSCR_TSARU_Pos                         (5U)\n#define ETH_PTPTSCR_TSARU_Msk                         (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */\n#define ETH_PTPTSCR_TSARU                             ETH_PTPTSCR_TSARU_Msk    /* Addend register update */\n#define ETH_PTPTSCR_TSITE_Pos                         (4U)\n#define ETH_PTPTSCR_TSITE_Msk                         (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */\n#define ETH_PTPTSCR_TSITE                             ETH_PTPTSCR_TSITE_Msk    /* Time stamp interrupt trigger enable */\n#define ETH_PTPTSCR_TSSTU_Pos                         (3U)\n#define ETH_PTPTSCR_TSSTU_Msk                         (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */\n#define ETH_PTPTSCR_TSSTU                             ETH_PTPTSCR_TSSTU_Msk    /* Time stamp update */\n#define ETH_PTPTSCR_TSSTI_Pos                         (2U)\n#define ETH_PTPTSCR_TSSTI_Msk                         (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */\n#define ETH_PTPTSCR_TSSTI                             ETH_PTPTSCR_TSSTI_Msk    /* Time stamp initialize */\n#define ETH_PTPTSCR_TSFCU_Pos                         (1U)\n#define ETH_PTPTSCR_TSFCU_Msk                         (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */\n#define ETH_PTPTSCR_TSFCU                             ETH_PTPTSCR_TSFCU_Msk    /* Time stamp fine or coarse update */\n#define ETH_PTPTSCR_TSE_Pos                           (0U)\n#define ETH_PTPTSCR_TSE_Msk                           (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */\n#define ETH_PTPTSCR_TSE                               ETH_PTPTSCR_TSE_Msk      /* Time stamp enable */\n\n/* Bit definition for Ethernet PTP Sub-Second Increment Register */\n#define ETH_PTPSSIR_STSSI_Pos                         (0U)\n#define ETH_PTPSSIR_STSSI_Msk                         (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */\n#define ETH_PTPSSIR_STSSI                             ETH_PTPSSIR_STSSI_Msk    /* System time Sub-second increment value */\n\n/* Bit definition for Ethernet PTP Time Stamp High Register */\n#define ETH_PTPTSHR_STS_Pos                           (0U)\n#define ETH_PTPTSHR_STS_Msk                           (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */\n#define ETH_PTPTSHR_STS                               ETH_PTPTSHR_STS_Msk      /* System Time second */\n\n/* Bit definition for Ethernet PTP Time Stamp Low Register */\n#define ETH_PTPTSLR_STPNS_Pos                         (31U)\n#define ETH_PTPTSLR_STPNS_Msk                         (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */\n#define ETH_PTPTSLR_STPNS                             ETH_PTPTSLR_STPNS_Msk    /* System Time Positive or negative time */\n#define ETH_PTPTSLR_STSS_Pos                          (0U)\n#define ETH_PTPTSLR_STSS_Msk                          (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */\n#define ETH_PTPTSLR_STSS                              ETH_PTPTSLR_STSS_Msk     /* System Time sub-seconds */\n\n/* Bit definition for Ethernet PTP Time Stamp High Update Register */\n#define ETH_PTPTSHUR_TSUS_Pos                         (0U)\n#define ETH_PTPTSHUR_TSUS_Msk                         (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */\n#define ETH_PTPTSHUR_TSUS                             ETH_PTPTSHUR_TSUS_Msk    /* Time stamp update seconds */\n\n/* Bit definition for Ethernet PTP Time Stamp Low Update Register */\n#define ETH_PTPTSLUR_TSUPNS_Pos                       (31U)\n#define ETH_PTPTSLUR_TSUPNS_Msk                       (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */\n#define ETH_PTPTSLUR_TSUPNS                           ETH_PTPTSLUR_TSUPNS_Msk  /* Time stamp update Positive or negative time */\n#define ETH_PTPTSLUR_TSUSS_Pos                        (0U)\n#define ETH_PTPTSLUR_TSUSS_Msk                        (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */\n#define ETH_PTPTSLUR_TSUSS                            ETH_PTPTSLUR_TSUSS_Msk   /* Time stamp update sub-seconds */\n\n/* Bit definition for Ethernet PTP Time Stamp Addend Register */\n#define ETH_PTPTSAR_TSA_Pos                           (0U)\n#define ETH_PTPTSAR_TSA_Msk                           (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */\n#define ETH_PTPTSAR_TSA                               ETH_PTPTSAR_TSA_Msk      /* Time stamp addend */\n\n/* Bit definition for Ethernet PTP Target Time High Register */\n#define ETH_PTPTTHR_TTSH_Pos                          (0U)\n#define ETH_PTPTTHR_TTSH_Msk                          (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */\n#define ETH_PTPTTHR_TTSH                              ETH_PTPTTHR_TTSH_Msk     /* Target time stamp high */\n\n/* Bit definition for Ethernet PTP Target Time Low Register */\n#define ETH_PTPTTLR_TTSL_Pos                          (0U)\n#define ETH_PTPTTLR_TTSL_Msk                          (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */\n#define ETH_PTPTTLR_TTSL                              ETH_PTPTTLR_TTSL_Msk     /* Target time stamp low */\n\n/* Bit definition for Ethernet PTP Time Stamp Status Register */\n#define ETH_PTPTSSR_TSTTR_Pos                         (5U)\n#define ETH_PTPTSSR_TSTTR_Msk                         (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */\n#define ETH_PTPTSSR_TSTTR                             ETH_PTPTSSR_TSTTR_Msk    /* Time stamp target time reached */\n#define ETH_PTPTSSR_TSSO_Pos                          (4U)\n#define ETH_PTPTSSR_TSSO_Msk                          (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */\n#define ETH_PTPTSSR_TSSO                              ETH_PTPTSSR_TSSO_Msk     /* Time stamp seconds overflow */\n\n/******************************************************************************/\n/*                 Ethernet DMA Registers bits definition                     */\n/******************************************************************************/\n\n/* Bit definition for Ethernet DMA Bus Mode Register */\n#define ETH_DMABMR_AAB_Pos                            (25U)\n#define ETH_DMABMR_AAB_Msk                            (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */\n#define ETH_DMABMR_AAB                                ETH_DMABMR_AAB_Msk       /* Address-Aligned beats */\n#define ETH_DMABMR_FPM_Pos                            (24U)\n#define ETH_DMABMR_FPM_Msk                            (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */\n#define ETH_DMABMR_FPM                                ETH_DMABMR_FPM_Msk       /* 4xPBL mode */\n#define ETH_DMABMR_USP_Pos                            (23U)\n#define ETH_DMABMR_USP_Msk                            (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */\n#define ETH_DMABMR_USP                                ETH_DMABMR_USP_Msk       /* Use separate PBL */\n#define ETH_DMABMR_RDP_Pos                            (17U)\n#define ETH_DMABMR_RDP_Msk                            (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */\n#define ETH_DMABMR_RDP                                ETH_DMABMR_RDP_Msk       /* RxDMA PBL */\n#define ETH_DMABMR_RDP_1Beat                          0x00020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 1 */\n#define ETH_DMABMR_RDP_2Beat                          0x00040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 2 */\n#define ETH_DMABMR_RDP_4Beat                          0x00080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\n#define ETH_DMABMR_RDP_8Beat                          0x00100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\n#define ETH_DMABMR_RDP_16Beat                         0x00200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\n#define ETH_DMABMR_RDP_32Beat                         0x00400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\n#define ETH_DMABMR_RDP_4xPBL_4Beat                    0x01020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\n#define ETH_DMABMR_RDP_4xPBL_8Beat                    0x01040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\n#define ETH_DMABMR_RDP_4xPBL_16Beat                   0x01080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\n#define ETH_DMABMR_RDP_4xPBL_32Beat                   0x01100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\n#define ETH_DMABMR_RDP_4xPBL_64Beat                   0x01200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 64 */\n#define ETH_DMABMR_RDP_4xPBL_128Beat                  0x01400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 128 */\n#define ETH_DMABMR_FB_Pos                             (16U)\n#define ETH_DMABMR_FB_Msk                             (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */\n#define ETH_DMABMR_FB                                 ETH_DMABMR_FB_Msk        /* Fixed Burst */\n#define ETH_DMABMR_RTPR_Pos                           (14U)\n#define ETH_DMABMR_RTPR_Msk                           (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */\n#define ETH_DMABMR_RTPR                               ETH_DMABMR_RTPR_Msk      /* Rx Tx priority ratio */\n#define ETH_DMABMR_RTPR_1_1                           0x00000000U              /* Rx Tx priority ratio */\n#define ETH_DMABMR_RTPR_2_1                           0x00004000U              /* Rx Tx priority ratio */\n#define ETH_DMABMR_RTPR_3_1                           0x00008000U              /* Rx Tx priority ratio */\n#define ETH_DMABMR_RTPR_4_1                           0x0000C000U              /* Rx Tx priority ratio */\n#define ETH_DMABMR_PBL_Pos                            (8U)\n#define ETH_DMABMR_PBL_Msk                            (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */\n#define ETH_DMABMR_PBL                                ETH_DMABMR_PBL_Msk       /* Programmable burst length */\n#define ETH_DMABMR_PBL_1Beat                          0x00000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\n#define ETH_DMABMR_PBL_2Beat                          0x00000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\n#define ETH_DMABMR_PBL_4Beat                          0x00000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\n#define ETH_DMABMR_PBL_8Beat                          0x00000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\n#define ETH_DMABMR_PBL_16Beat                         0x00001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\n#define ETH_DMABMR_PBL_32Beat                         0x00002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\n#define ETH_DMABMR_PBL_4xPBL_4Beat                    0x01000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\n#define ETH_DMABMR_PBL_4xPBL_8Beat                    0x01000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\n#define ETH_DMABMR_PBL_4xPBL_16Beat                   0x01000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\n#define ETH_DMABMR_PBL_4xPBL_32Beat                   0x01000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\n#define ETH_DMABMR_PBL_4xPBL_64Beat                   0x01001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\n#define ETH_DMABMR_PBL_4xPBL_128Beat                  0x01002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\n#define ETH_DMABMR_EDE_Pos                            (7U)\n#define ETH_DMABMR_EDE_Msk                            (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */\n#define ETH_DMABMR_EDE                                ETH_DMABMR_EDE_Msk       /* Enhanced Descriptor Enable */\n#define ETH_DMABMR_DSL_Pos                            (2U)\n#define ETH_DMABMR_DSL_Msk                            (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */\n#define ETH_DMABMR_DSL                                ETH_DMABMR_DSL_Msk       /* Descriptor Skip Length */\n#define ETH_DMABMR_DA_Pos                             (1U)\n#define ETH_DMABMR_DA_Msk                             (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */\n#define ETH_DMABMR_DA                                 ETH_DMABMR_DA_Msk        /* DMA arbitration scheme */\n#define ETH_DMABMR_SR_Pos                             (0U)\n#define ETH_DMABMR_SR_Msk                             (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */\n#define ETH_DMABMR_SR                                 ETH_DMABMR_SR_Msk        /* Software reset */\n\n/* Bit definition for Ethernet DMA Transmit Poll Demand Register */\n#define ETH_DMATPDR_TPD_Pos                           (0U)\n#define ETH_DMATPDR_TPD_Msk                           (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMATPDR_TPD                               ETH_DMATPDR_TPD_Msk      /* Transmit poll demand */\n\n/* Bit definition for Ethernet DMA Receive Poll Demand Register */\n#define ETH_DMARPDR_RPD_Pos                           (0U)\n#define ETH_DMARPDR_RPD_Msk                           (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMARPDR_RPD                               ETH_DMARPDR_RPD_Msk      /* Receive poll demand  */\n\n/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */\n#define ETH_DMARDLAR_SRL_Pos                          (0U)\n#define ETH_DMARDLAR_SRL_Msk                          (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMARDLAR_SRL                              ETH_DMARDLAR_SRL_Msk     /* Start of receive list */\n\n/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */\n#define ETH_DMATDLAR_STL_Pos                          (0U)\n#define ETH_DMATDLAR_STL_Msk                          (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMATDLAR_STL                              ETH_DMATDLAR_STL_Msk     /* Start of transmit list */\n\n/* Bit definition for Ethernet DMA Status Register */\n#define ETH_DMASR_TSTS_Pos                            (29U)\n#define ETH_DMASR_TSTS_Msk                            (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */\n#define ETH_DMASR_TSTS                                ETH_DMASR_TSTS_Msk       /* Time-stamp trigger status */\n#define ETH_DMASR_PMTS_Pos                            (28U)\n#define ETH_DMASR_PMTS_Msk                            (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */\n#define ETH_DMASR_PMTS                                ETH_DMASR_PMTS_Msk       /* PMT status */\n#define ETH_DMASR_MMCS_Pos                            (27U)\n#define ETH_DMASR_MMCS_Msk                            (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */\n#define ETH_DMASR_MMCS                                ETH_DMASR_MMCS_Msk       /* MMC status */\n#define ETH_DMASR_EBS_Pos                             (23U)\n#define ETH_DMASR_EBS_Msk                             (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */\n#define ETH_DMASR_EBS                                 ETH_DMASR_EBS_Msk        /* Error bits status */\n  /* combination with EBS[2:0] for GetFlagStatus function */\n#define ETH_DMASR_EBS_DescAccess_Pos                  (25U)\n#define ETH_DMASR_EBS_DescAccess_Msk                  (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */\n#define ETH_DMASR_EBS_DescAccess                      ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */\n#define ETH_DMASR_EBS_ReadTransf_Pos                  (24U)\n#define ETH_DMASR_EBS_ReadTransf_Msk                  (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */\n#define ETH_DMASR_EBS_ReadTransf                      ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */\n#define ETH_DMASR_EBS_DataTransfTx_Pos                (23U)\n#define ETH_DMASR_EBS_DataTransfTx_Msk                (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */\n#define ETH_DMASR_EBS_DataTransfTx                    ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */\n#define ETH_DMASR_TPS_Pos                             (20U)\n#define ETH_DMASR_TPS_Msk                             (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */\n#define ETH_DMASR_TPS                                 ETH_DMASR_TPS_Msk        /* Transmit process state */\n#define ETH_DMASR_TPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Tx Command issued  */\n#define ETH_DMASR_TPS_Fetching_Pos                    (20U)\n#define ETH_DMASR_TPS_Fetching_Msk                    (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */\n#define ETH_DMASR_TPS_Fetching                        ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */\n#define ETH_DMASR_TPS_Waiting_Pos                     (21U)\n#define ETH_DMASR_TPS_Waiting_Msk                     (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */\n#define ETH_DMASR_TPS_Waiting                         ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */\n#define ETH_DMASR_TPS_Reading_Pos                     (20U)\n#define ETH_DMASR_TPS_Reading_Msk                     (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */\n#define ETH_DMASR_TPS_Reading                         ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */\n#define ETH_DMASR_TPS_Suspended_Pos                   (21U)\n#define ETH_DMASR_TPS_Suspended_Msk                   (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */\n#define ETH_DMASR_TPS_Suspended                       ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */\n#define ETH_DMASR_TPS_Closing_Pos                     (20U)\n#define ETH_DMASR_TPS_Closing_Msk                     (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */\n#define ETH_DMASR_TPS_Closing                         ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */\n#define ETH_DMASR_RPS_Pos                             (17U)\n#define ETH_DMASR_RPS_Msk                             (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */\n#define ETH_DMASR_RPS                                 ETH_DMASR_RPS_Msk        /* Receive process state */\n#define ETH_DMASR_RPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Rx Command issued */\n#define ETH_DMASR_RPS_Fetching_Pos                    (17U)\n#define ETH_DMASR_RPS_Fetching_Msk                    (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */\n#define ETH_DMASR_RPS_Fetching                        ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */\n#define ETH_DMASR_RPS_Waiting_Pos                     (17U)\n#define ETH_DMASR_RPS_Waiting_Msk                     (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */\n#define ETH_DMASR_RPS_Waiting                         ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */\n#define ETH_DMASR_RPS_Suspended_Pos                   (19U)\n#define ETH_DMASR_RPS_Suspended_Msk                   (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */\n#define ETH_DMASR_RPS_Suspended                       ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */\n#define ETH_DMASR_RPS_Closing_Pos                     (17U)\n#define ETH_DMASR_RPS_Closing_Msk                     (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */\n#define ETH_DMASR_RPS_Closing                         ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */\n#define ETH_DMASR_RPS_Queuing_Pos                     (17U)\n#define ETH_DMASR_RPS_Queuing_Msk                     (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */\n#define ETH_DMASR_RPS_Queuing                         ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */\n#define ETH_DMASR_NIS_Pos                             (16U)\n#define ETH_DMASR_NIS_Msk                             (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */\n#define ETH_DMASR_NIS                                 ETH_DMASR_NIS_Msk        /* Normal interrupt summary */\n#define ETH_DMASR_AIS_Pos                             (15U)\n#define ETH_DMASR_AIS_Msk                             (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */\n#define ETH_DMASR_AIS                                 ETH_DMASR_AIS_Msk        /* Abnormal interrupt summary */\n#define ETH_DMASR_ERS_Pos                             (14U)\n#define ETH_DMASR_ERS_Msk                             (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */\n#define ETH_DMASR_ERS                                 ETH_DMASR_ERS_Msk        /* Early receive status */\n#define ETH_DMASR_FBES_Pos                            (13U)\n#define ETH_DMASR_FBES_Msk                            (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */\n#define ETH_DMASR_FBES                                ETH_DMASR_FBES_Msk       /* Fatal bus error status */\n#define ETH_DMASR_ETS_Pos                             (10U)\n#define ETH_DMASR_ETS_Msk                             (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */\n#define ETH_DMASR_ETS                                 ETH_DMASR_ETS_Msk        /* Early transmit status */\n#define ETH_DMASR_RWTS_Pos                            (9U)\n#define ETH_DMASR_RWTS_Msk                            (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */\n#define ETH_DMASR_RWTS                                ETH_DMASR_RWTS_Msk       /* Receive watchdog timeout status */\n#define ETH_DMASR_RPSS_Pos                            (8U)\n#define ETH_DMASR_RPSS_Msk                            (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */\n#define ETH_DMASR_RPSS                                ETH_DMASR_RPSS_Msk       /* Receive process stopped status */\n#define ETH_DMASR_RBUS_Pos                            (7U)\n#define ETH_DMASR_RBUS_Msk                            (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */\n#define ETH_DMASR_RBUS                                ETH_DMASR_RBUS_Msk       /* Receive buffer unavailable status */\n#define ETH_DMASR_RS_Pos                              (6U)\n#define ETH_DMASR_RS_Msk                              (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */\n#define ETH_DMASR_RS                                  ETH_DMASR_RS_Msk         /* Receive status */\n#define ETH_DMASR_TUS_Pos                             (5U)\n#define ETH_DMASR_TUS_Msk                             (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */\n#define ETH_DMASR_TUS                                 ETH_DMASR_TUS_Msk        /* Transmit underflow status */\n#define ETH_DMASR_ROS_Pos                             (4U)\n#define ETH_DMASR_ROS_Msk                             (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */\n#define ETH_DMASR_ROS                                 ETH_DMASR_ROS_Msk        /* Receive overflow status */\n#define ETH_DMASR_TJTS_Pos                            (3U)\n#define ETH_DMASR_TJTS_Msk                            (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */\n#define ETH_DMASR_TJTS                                ETH_DMASR_TJTS_Msk       /* Transmit jabber timeout status */\n#define ETH_DMASR_TBUS_Pos                            (2U)\n#define ETH_DMASR_TBUS_Msk                            (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */\n#define ETH_DMASR_TBUS                                ETH_DMASR_TBUS_Msk       /* Transmit buffer unavailable status */\n#define ETH_DMASR_TPSS_Pos                            (1U)\n#define ETH_DMASR_TPSS_Msk                            (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */\n#define ETH_DMASR_TPSS                                ETH_DMASR_TPSS_Msk       /* Transmit process stopped status */\n#define ETH_DMASR_TS_Pos                              (0U)\n#define ETH_DMASR_TS_Msk                              (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */\n#define ETH_DMASR_TS                                  ETH_DMASR_TS_Msk         /* Transmit status */\n\n/* Bit definition for Ethernet DMA Operation Mode Register */\n#define ETH_DMAOMR_DTCEFD_Pos                         (26U)\n#define ETH_DMAOMR_DTCEFD_Msk                         (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */\n#define ETH_DMAOMR_DTCEFD                             ETH_DMAOMR_DTCEFD_Msk    /* Disable Dropping of TCP/IP checksum error frames */\n#define ETH_DMAOMR_RSF_Pos                            (25U)\n#define ETH_DMAOMR_RSF_Msk                            (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */\n#define ETH_DMAOMR_RSF                                ETH_DMAOMR_RSF_Msk       /* Receive store and forward */\n#define ETH_DMAOMR_DFRF_Pos                           (24U)\n#define ETH_DMAOMR_DFRF_Msk                           (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */\n#define ETH_DMAOMR_DFRF                               ETH_DMAOMR_DFRF_Msk      /* Disable flushing of received frames */\n#define ETH_DMAOMR_TSF_Pos                            (21U)\n#define ETH_DMAOMR_TSF_Msk                            (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */\n#define ETH_DMAOMR_TSF                                ETH_DMAOMR_TSF_Msk       /* Transmit store and forward */\n#define ETH_DMAOMR_FTF_Pos                            (20U)\n#define ETH_DMAOMR_FTF_Msk                            (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */\n#define ETH_DMAOMR_FTF                                ETH_DMAOMR_FTF_Msk       /* Flush transmit FIFO */\n#define ETH_DMAOMR_TTC_Pos                            (14U)\n#define ETH_DMAOMR_TTC_Msk                            (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */\n#define ETH_DMAOMR_TTC                                ETH_DMAOMR_TTC_Msk       /* Transmit threshold control */\n#define ETH_DMAOMR_TTC_64Bytes                        0x00000000U              /* threshold level of the MTL Transmit FIFO is 64 Bytes */\n#define ETH_DMAOMR_TTC_128Bytes                       0x00004000U              /* threshold level of the MTL Transmit FIFO is 128 Bytes */\n#define ETH_DMAOMR_TTC_192Bytes                       0x00008000U              /* threshold level of the MTL Transmit FIFO is 192 Bytes */\n#define ETH_DMAOMR_TTC_256Bytes                       0x0000C000U              /* threshold level of the MTL Transmit FIFO is 256 Bytes */\n#define ETH_DMAOMR_TTC_40Bytes                        0x00010000U              /* threshold level of the MTL Transmit FIFO is 40 Bytes */\n#define ETH_DMAOMR_TTC_32Bytes                        0x00014000U              /* threshold level of the MTL Transmit FIFO is 32 Bytes */\n#define ETH_DMAOMR_TTC_24Bytes                        0x00018000U              /* threshold level of the MTL Transmit FIFO is 24 Bytes */\n#define ETH_DMAOMR_TTC_16Bytes                        0x0001C000U              /* threshold level of the MTL Transmit FIFO is 16 Bytes */\n#define ETH_DMAOMR_ST_Pos                             (13U)\n#define ETH_DMAOMR_ST_Msk                             (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */\n#define ETH_DMAOMR_ST                                 ETH_DMAOMR_ST_Msk        /* Start/stop transmission command */\n#define ETH_DMAOMR_FEF_Pos                            (7U)\n#define ETH_DMAOMR_FEF_Msk                            (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */\n#define ETH_DMAOMR_FEF                                ETH_DMAOMR_FEF_Msk       /* Forward error frames */\n#define ETH_DMAOMR_FUGF_Pos                           (6U)\n#define ETH_DMAOMR_FUGF_Msk                           (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */\n#define ETH_DMAOMR_FUGF                               ETH_DMAOMR_FUGF_Msk      /* Forward undersized good frames */\n#define ETH_DMAOMR_RTC_Pos                            (3U)\n#define ETH_DMAOMR_RTC_Msk                            (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */\n#define ETH_DMAOMR_RTC                                ETH_DMAOMR_RTC_Msk       /* receive threshold control */\n#define ETH_DMAOMR_RTC_64Bytes                        0x00000000U              /* threshold level of the MTL Receive FIFO is 64 Bytes */\n#define ETH_DMAOMR_RTC_32Bytes                        0x00000008U              /* threshold level of the MTL Receive FIFO is 32 Bytes */\n#define ETH_DMAOMR_RTC_96Bytes                        0x00000010U              /* threshold level of the MTL Receive FIFO is 96 Bytes */\n#define ETH_DMAOMR_RTC_128Bytes                       0x00000018U              /* threshold level of the MTL Receive FIFO is 128 Bytes */\n#define ETH_DMAOMR_OSF_Pos                            (2U)\n#define ETH_DMAOMR_OSF_Msk                            (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */\n#define ETH_DMAOMR_OSF                                ETH_DMAOMR_OSF_Msk       /* operate on second frame */\n#define ETH_DMAOMR_SR_Pos                             (1U)\n#define ETH_DMAOMR_SR_Msk                             (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */\n#define ETH_DMAOMR_SR                                 ETH_DMAOMR_SR_Msk        /* Start/stop receive */\n\n/* Bit definition for Ethernet DMA Interrupt Enable Register */\n#define ETH_DMAIER_NISE_Pos                           (16U)\n#define ETH_DMAIER_NISE_Msk                           (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */\n#define ETH_DMAIER_NISE                               ETH_DMAIER_NISE_Msk      /* Normal interrupt summary enable */\n#define ETH_DMAIER_AISE_Pos                           (15U)\n#define ETH_DMAIER_AISE_Msk                           (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */\n#define ETH_DMAIER_AISE                               ETH_DMAIER_AISE_Msk      /* Abnormal interrupt summary enable */\n#define ETH_DMAIER_ERIE_Pos                           (14U)\n#define ETH_DMAIER_ERIE_Msk                           (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */\n#define ETH_DMAIER_ERIE                               ETH_DMAIER_ERIE_Msk      /* Early receive interrupt enable */\n#define ETH_DMAIER_FBEIE_Pos                          (13U)\n#define ETH_DMAIER_FBEIE_Msk                          (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */\n#define ETH_DMAIER_FBEIE                              ETH_DMAIER_FBEIE_Msk     /* Fatal bus error interrupt enable */\n#define ETH_DMAIER_ETIE_Pos                           (10U)\n#define ETH_DMAIER_ETIE_Msk                           (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */\n#define ETH_DMAIER_ETIE                               ETH_DMAIER_ETIE_Msk      /* Early transmit interrupt enable */\n#define ETH_DMAIER_RWTIE_Pos                          (9U)\n#define ETH_DMAIER_RWTIE_Msk                          (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */\n#define ETH_DMAIER_RWTIE                              ETH_DMAIER_RWTIE_Msk     /* Receive watchdog timeout interrupt enable */\n#define ETH_DMAIER_RPSIE_Pos                          (8U)\n#define ETH_DMAIER_RPSIE_Msk                          (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */\n#define ETH_DMAIER_RPSIE                              ETH_DMAIER_RPSIE_Msk     /* Receive process stopped interrupt enable */\n#define ETH_DMAIER_RBUIE_Pos                          (7U)\n#define ETH_DMAIER_RBUIE_Msk                          (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */\n#define ETH_DMAIER_RBUIE                              ETH_DMAIER_RBUIE_Msk     /* Receive buffer unavailable interrupt enable */\n#define ETH_DMAIER_RIE_Pos                            (6U)\n#define ETH_DMAIER_RIE_Msk                            (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */\n#define ETH_DMAIER_RIE                                ETH_DMAIER_RIE_Msk       /* Receive interrupt enable */\n#define ETH_DMAIER_TUIE_Pos                           (5U)\n#define ETH_DMAIER_TUIE_Msk                           (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */\n#define ETH_DMAIER_TUIE                               ETH_DMAIER_TUIE_Msk      /* Transmit Underflow interrupt enable */\n#define ETH_DMAIER_ROIE_Pos                           (4U)\n#define ETH_DMAIER_ROIE_Msk                           (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */\n#define ETH_DMAIER_ROIE                               ETH_DMAIER_ROIE_Msk      /* Receive Overflow interrupt enable */\n#define ETH_DMAIER_TJTIE_Pos                          (3U)\n#define ETH_DMAIER_TJTIE_Msk                          (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */\n#define ETH_DMAIER_TJTIE                              ETH_DMAIER_TJTIE_Msk     /* Transmit jabber timeout interrupt enable */\n#define ETH_DMAIER_TBUIE_Pos                          (2U)\n#define ETH_DMAIER_TBUIE_Msk                          (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */\n#define ETH_DMAIER_TBUIE                              ETH_DMAIER_TBUIE_Msk     /* Transmit buffer unavailable interrupt enable */\n#define ETH_DMAIER_TPSIE_Pos                          (1U)\n#define ETH_DMAIER_TPSIE_Msk                          (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */\n#define ETH_DMAIER_TPSIE                              ETH_DMAIER_TPSIE_Msk     /* Transmit process stopped interrupt enable */\n#define ETH_DMAIER_TIE_Pos                            (0U)\n#define ETH_DMAIER_TIE_Msk                            (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */\n#define ETH_DMAIER_TIE                                ETH_DMAIER_TIE_Msk       /* Transmit interrupt enable */\n\n/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */\n#define ETH_DMAMFBOCR_OFOC_Pos                        (28U)\n#define ETH_DMAMFBOCR_OFOC_Msk                        (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */\n#define ETH_DMAMFBOCR_OFOC                            ETH_DMAMFBOCR_OFOC_Msk   /* Overflow bit for FIFO overflow counter */\n#define ETH_DMAMFBOCR_MFA_Pos                         (17U)\n#define ETH_DMAMFBOCR_MFA_Msk                         (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */\n#define ETH_DMAMFBOCR_MFA                             ETH_DMAMFBOCR_MFA_Msk    /* Number of frames missed by the application */\n#define ETH_DMAMFBOCR_OMFC_Pos                        (16U)\n#define ETH_DMAMFBOCR_OMFC_Msk                        (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */\n#define ETH_DMAMFBOCR_OMFC                            ETH_DMAMFBOCR_OMFC_Msk   /* Overflow bit for missed frame counter */\n#define ETH_DMAMFBOCR_MFC_Pos                         (0U)\n#define ETH_DMAMFBOCR_MFC_Msk                         (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */\n#define ETH_DMAMFBOCR_MFC                             ETH_DMAMFBOCR_MFC_Msk    /* Number of frames missed by the controller */\n\n/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */\n#define ETH_DMACHTDR_HTDAP_Pos                        (0U)\n#define ETH_DMACHTDR_HTDAP_Msk                        (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMACHTDR_HTDAP                            ETH_DMACHTDR_HTDAP_Msk   /* Host transmit descriptor address pointer */\n\n/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */\n#define ETH_DMACHRDR_HRDAP_Pos                        (0U)\n#define ETH_DMACHRDR_HRDAP_Msk                        (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMACHRDR_HRDAP                            ETH_DMACHRDR_HRDAP_Msk   /* Host receive descriptor address pointer */\n\n/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */\n#define ETH_DMACHTBAR_HTBAP_Pos                       (0U)\n#define ETH_DMACHTBAR_HTBAP_Msk                       (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMACHTBAR_HTBAP                           ETH_DMACHTBAR_HTBAP_Msk  /* Host transmit buffer address pointer */\n\n/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */\n#define ETH_DMACHRBAR_HRBAP_Pos                       (0U)\n#define ETH_DMACHRBAR_HRBAP_Msk                       (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMACHRBAR_HRBAP                           ETH_DMACHRBAR_HRBAP_Msk  /* Host receive buffer address pointer */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                       USB_OTG                              */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/\n#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)\n#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */\n#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)\n#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\n#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */\n#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)\n#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)\n#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */\n#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)\n#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)\n#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */\n#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */\n#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)\n#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */\n#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */\n#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)\n#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */\n#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)\n#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */\n#define USB_OTG_GOTGCTL_BSVLD_Pos                (19U)\n#define USB_OTG_GOTGCTL_BSVLD_Msk                (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGCTL_BSVLD                    USB_OTG_GOTGCTL_BSVLD_Msk     /*!< B-session valid */\n\n/********************  Bit definition forUSB_OTG_HCFG register  ********************/\n\n#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)\n#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\n#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */\n#define USB_OTG_HCFG_FSLSPCS_0                   (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCFG_FSLSPCS_1                   (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCFG_FSLSS_Pos                   (2U)\n#define USB_OTG_HCFG_FSLSS_Msk                   (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */\n\n/********************  Bit definition for USB_OTG_DCFG register  ********************/\n\n#define USB_OTG_DCFG_DSPD_Pos                    (0U)\n#define USB_OTG_DCFG_DSPD_Msk                    (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\n#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */\n#define USB_OTG_DCFG_DSPD_0                      (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCFG_DSPD_1                      (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)\n#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */\n\n#define USB_OTG_DCFG_DAD_Pos                     (4U)\n#define USB_OTG_DCFG_DAD_Msk                     (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\n#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */\n#define USB_OTG_DCFG_DAD_0                       (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCFG_DAD_1                       (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCFG_DAD_2                       (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCFG_DAD_3                       (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCFG_DAD_4                       (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCFG_DAD_5                       (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCFG_DAD_6                       (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\n\n#define USB_OTG_DCFG_PFIVL_Pos                   (11U)\n#define USB_OTG_DCFG_PFIVL_Msk                   (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\n#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */\n#define USB_OTG_DCFG_PFIVL_0                     (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCFG_PFIVL_1                     (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\n\n#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)\n#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\n#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */\n#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\n#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\n\n/********************  Bit definition for USB_OTG_PCGCR register  ********************/\n#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)\n#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */\n#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)\n#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */\n#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)\n#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */\n\n/********************  Bit definition for USB_OTG_GOTGINT register  ********************/\n#define USB_OTG_GOTGINT_SEDET_Pos                (2U)\n#define USB_OTG_GOTGINT_SEDET_Msk                (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */\n#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)\n#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */\n#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)\n#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */\n#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)\n#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */\n#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)\n#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */\n#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)\n#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */\n\n/********************  Bit definition for USB_OTG_DCTL register  ********************/\n#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)\n#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */\n#define USB_OTG_DCTL_SDIS_Pos                    (1U)\n#define USB_OTG_DCTL_SDIS_Msk                    (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */\n#define USB_OTG_DCTL_GINSTS_Pos                  (2U)\n#define USB_OTG_DCTL_GINSTS_Msk                  (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */\n#define USB_OTG_DCTL_GONSTS_Pos                  (3U)\n#define USB_OTG_DCTL_GONSTS_Msk                  (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\n#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */\n\n#define USB_OTG_DCTL_TCTL_Pos                    (4U)\n#define USB_OTG_DCTL_TCTL_Msk                    (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\n#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */\n#define USB_OTG_DCTL_TCTL_0                      (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCTL_TCTL_1                      (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCTL_TCTL_2                      (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCTL_SGINAK_Pos                  (7U)\n#define USB_OTG_DCTL_SGINAK_Msk                  (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */\n#define USB_OTG_DCTL_CGINAK_Pos                  (8U)\n#define USB_OTG_DCTL_CGINAK_Msk                  (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */\n#define USB_OTG_DCTL_SGONAK_Pos                  (9U)\n#define USB_OTG_DCTL_SGONAK_Msk                  (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */\n#define USB_OTG_DCTL_CGONAK_Pos                  (10U)\n#define USB_OTG_DCTL_CGONAK_Msk                  (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\n#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */\n#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)\n#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */\n\n/********************  Bit definition for USB_OTG_HFIR register  ********************/\n#define USB_OTG_HFIR_FRIVL_Pos                   (0U)\n#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */\n\n/********************  Bit definition for USB_OTG_HFNUM register  ********************/\n#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)\n#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */\n#define USB_OTG_HFNUM_FTREM_Pos                  (16U)\n#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */\n\n/********************  Bit definition for USB_OTG_DSTS register  ********************/\n#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)\n#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */\n\n#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)\n#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\n#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */\n#define USB_OTG_DSTS_ENUMSPD_0                   (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DSTS_ENUMSPD_1                   (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\n#define USB_OTG_DSTS_EERR_Pos                    (3U)\n#define USB_OTG_DSTS_EERR_Msk                    (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\n#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */\n#define USB_OTG_DSTS_FNSOF_Pos                   (8U)\n#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\n#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */\n\n/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/\n#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)\n#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\n#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */\n#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)\n#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\n#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */\n#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */\n#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */\n#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */\n#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */\n#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */\n#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)\n#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */\n#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)\n#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */\n#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)\n#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\n#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */\n\n/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/\n\n#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)\n#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\n#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */\n#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\n#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\n#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\n#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)\n#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\n#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\n#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)\n#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\n#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */\n#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)\n#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\n#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */\n#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)\n#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\n#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */\n#define USB_OTG_GUSBCFG_TRDT_0                   (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\n#define USB_OTG_GUSBCFG_TRDT_1                   (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\n#define USB_OTG_GUSBCFG_TRDT_2                   (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\n#define USB_OTG_GUSBCFG_TRDT_3                   (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\n#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)\n#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */\n#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)\n#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\n#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */\n#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)\n#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\n#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */\n#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)\n#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\n#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */\n#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)\n#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\n#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */\n#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)\n#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\n#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */\n#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)\n#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\n#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */\n#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)\n#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\n#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */\n#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)\n#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\n#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */\n#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)\n#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\n#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */\n#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)\n#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */\n\n/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/\n#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)\n#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\n#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */\n#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)\n#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\n#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */\n#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)\n#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\n#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */\n#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)\n#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\n#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */\n#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)\n#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\n#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */\n\n\n#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)\n#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\n#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */\n#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\n#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\n#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)\n#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\n#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */\n#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)\n#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\n#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */\n\n/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/\n#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)\n#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)\n#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)\n#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)\n#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)\n#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/\n#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)\n#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */\n#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)\n#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */\n#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)\n#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */\n#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\n\n/********************  Bit definition for USB_OTG_HAINT register  ********************/\n#define USB_OTG_HAINT_HAINT_Pos                  (0U)\n#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */\n\n/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/\n#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */\n#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */\n#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)\n#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */\n#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)\n#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */\n#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask */\n#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)\n#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */\n#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)\n#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */\n\n/********************  Bit definition for USB_OTG_GINTSTS register  ********************/\n#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)\n#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\n#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */\n#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)\n#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */\n#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)\n#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */\n#define USB_OTG_GINTSTS_SOF_Pos                  (3U)\n#define USB_OTG_GINTSTS_SOF_Msk                  (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */\n#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)\n#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */\n#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)\n#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */\n#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)\n#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */\n#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)\n#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */\n#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)\n#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */\n#define USB_OTG_GINTSTS_USBRST_Pos               (12U)\n#define USB_OTG_GINTSTS_USBRST_Msk               (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */\n#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)\n#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */\n#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)\n#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */\n#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)\n#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */\n#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)\n#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */\n#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)\n#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */\n#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)\n#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */\n#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)\n#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */\n#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)\n#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */\n#define USB_OTG_GINTSTS_HCINT_Pos                (25U)\n#define USB_OTG_GINTSTS_HCINT_Msk                (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */\n#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)\n#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */\n#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)\n#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */\n#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)\n#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */\n#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)\n#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */\n#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)\n#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */\n\n/********************  Bit definition for USB_OTG_GINTMSK register  ********************/\n#define USB_OTG_GINTMSK_MMISM_Pos                (1U)\n#define USB_OTG_GINTMSK_MMISM_Msk                (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */\n#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)\n#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */\n#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)\n#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */\n#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)\n#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */\n#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)\n#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */\n#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)\n#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */\n#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)\n#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */\n#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)\n#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */\n#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)\n#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */\n#define USB_OTG_GINTMSK_USBRST_Pos               (12U)\n#define USB_OTG_GINTMSK_USBRST_Msk               (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */\n#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)\n#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */\n#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)\n#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */\n#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)\n#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */\n#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)\n#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\n#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */\n#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)\n#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */\n#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)\n#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */\n#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)\n#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */\n#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)\n#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */\n#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)\n#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */\n#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)\n#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */\n#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)\n#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */\n#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)\n#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */\n#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)\n#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */\n#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)\n#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */\n#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)\n#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */\n\n/********************  Bit definition for USB_OTG_DAINT register  ********************/\n#define USB_OTG_DAINT_IEPINT_Pos                 (0U)\n#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */\n#define USB_OTG_DAINT_OEPINT_Pos                 (16U)\n#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */\n\n/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/\n#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)\n#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */\n\n/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/\n#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)\n#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\n#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */\n#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)\n#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\n#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)\n#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\n#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)\n#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/\n#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)\n#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */\n#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)\n#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for OTG register  ********************/\n\n#define USB_OTG_CHNUM_Pos                        (0U)\n#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\n#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\n#define USB_OTG_BCNT_Pos                         (4U)\n#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\n\n#define USB_OTG_DPID_Pos                         (15U)\n#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\n#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\n#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\n\n#define USB_OTG_PKTSTS_Pos                       (17U)\n#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\n#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\n#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\n#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\n#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\n\n#define USB_OTG_EPNUM_Pos                        (0U)\n#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\n#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\n\n#define USB_OTG_FRMNUM_Pos                       (21U)\n#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\n#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\n#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\n#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\n#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\n\n/********************  Bit definition for OTG register  ********************/\n\n#define USB_OTG_CHNUM_Pos                        (0U)\n#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\n#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\n#define USB_OTG_BCNT_Pos                         (4U)\n#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\n\n#define USB_OTG_DPID_Pos                         (15U)\n#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\n#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\n#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\n\n#define USB_OTG_PKTSTS_Pos                       (17U)\n#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\n#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\n#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\n#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\n#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\n\n#define USB_OTG_EPNUM_Pos                        (0U)\n#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\n#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\n\n#define USB_OTG_FRMNUM_Pos                       (21U)\n#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\n#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\n#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\n#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\n#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\n\n/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/\n#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)\n#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/\n#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)\n#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */\n\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_NPTXFSA_Pos                      (0U)\n#define USB_OTG_NPTXFSA_Msk                      (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */\n#define USB_OTG_NPTXFD_Pos                       (16U)\n#define USB_OTG_NPTXFD_Msk                       (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */\n#define USB_OTG_TX0FSA_Pos                       (0U)\n#define USB_OTG_TX0FSA_Msk                       (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */\n#define USB_OTG_TX0FD_Pos                        (16U)\n#define USB_OTG_TX0FD_Msk                        (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */\n\n/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/\n#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)\n#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\n#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\n\n/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\n\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/\n#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)\n#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\n#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\n#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)\n#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\n#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */\n\n#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)\n#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\n#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */\n#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)\n#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\n#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */\n\n#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)\n#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */\n#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\n#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)\n#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\n#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */\n\n/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DEACHINT register  ********************/\n#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)\n#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */\n#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)\n#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */\n\n/********************  Bit definition for USB_OTG_GCCFG register  ********************/\n#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)\n#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\n#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */\n#define USB_OTG_GCCFG_I2CPADEN_Pos               (17U)\n#define USB_OTG_GCCFG_I2CPADEN_Msk               (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_GCCFG_I2CPADEN                   USB_OTG_GCCFG_I2CPADEN_Msk    /*!< Enable I2C bus connection for the external I2C PHY interface*/\n#define USB_OTG_GCCFG_VBUSASEN_Pos               (18U)\n#define USB_OTG_GCCFG_VBUSASEN_Msk               (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_GCCFG_VBUSASEN                   USB_OTG_GCCFG_VBUSASEN_Msk    /*!< Enable the VBUS sensing device */\n#define USB_OTG_GCCFG_VBUSBSEN_Pos               (19U)\n#define USB_OTG_GCCFG_VBUSBSEN_Msk               (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_GCCFG_VBUSBSEN                   USB_OTG_GCCFG_VBUSBSEN_Msk    /*!< Enable the VBUS sensing device */\n#define USB_OTG_GCCFG_SOFOUTEN_Pos               (20U)\n#define USB_OTG_GCCFG_SOFOUTEN_Msk               (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_GCCFG_SOFOUTEN                   USB_OTG_GCCFG_SOFOUTEN_Msk    /*!< SOF output enable */\n#define USB_OTG_GCCFG_NOVBUSSENS_Pos             (21U)\n#define USB_OTG_GCCFG_NOVBUSSENS_Msk             (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */\n#define USB_OTG_GCCFG_NOVBUSSENS                 USB_OTG_GCCFG_NOVBUSSENS_Msk  /*!< VBUS sensing disable option*/\n\n/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\n\n/********************  Bit definition for USB_OTG_CID register  ********************/\n#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)\n#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */\n\n/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */\n#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPRT register  ********************/\n#define USB_OTG_HPRT_PCSTS_Pos                   (0U)\n#define USB_OTG_HPRT_PCSTS_Msk                   (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */\n#define USB_OTG_HPRT_PCDET_Pos                   (1U)\n#define USB_OTG_HPRT_PCDET_Msk                   (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\n#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */\n#define USB_OTG_HPRT_PENA_Pos                    (2U)\n#define USB_OTG_HPRT_PENA_Msk                    (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\n#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */\n#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)\n#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\n#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */\n#define USB_OTG_HPRT_POCA_Pos                    (4U)\n#define USB_OTG_HPRT_POCA_Msk                    (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\n#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */\n#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)\n#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\n#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */\n#define USB_OTG_HPRT_PRES_Pos                    (6U)\n#define USB_OTG_HPRT_PRES_Msk                    (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\n#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */\n#define USB_OTG_HPRT_PSUSP_Pos                   (7U)\n#define USB_OTG_HPRT_PSUSP_Msk                   (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\n#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */\n#define USB_OTG_HPRT_PRST_Pos                    (8U)\n#define USB_OTG_HPRT_PRST_Msk                    (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\n#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */\n\n#define USB_OTG_HPRT_PLSTS_Pos                   (10U)\n#define USB_OTG_HPRT_PLSTS_Msk                   (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\n#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */\n#define USB_OTG_HPRT_PLSTS_0                     (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\n#define USB_OTG_HPRT_PLSTS_1                     (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_HPRT_PPWR_Pos                    (12U)\n#define USB_OTG_HPRT_PPWR_Msk                    (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */\n\n#define USB_OTG_HPRT_PTCTL_Pos                   (13U)\n#define USB_OTG_HPRT_PTCTL_Msk                   (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\n#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */\n#define USB_OTG_HPRT_PTCTL_0                     (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\n#define USB_OTG_HPRT_PTCTL_1                     (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\n#define USB_OTG_HPRT_PTCTL_2                     (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\n#define USB_OTG_HPRT_PTCTL_3                     (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\n\n#define USB_OTG_HPRT_PSPD_Pos                    (17U)\n#define USB_OTG_HPRT_PSPD_Msk                    (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\n#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */\n#define USB_OTG_HPRT_PSPD_0                      (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPRT_PSPD_1                      (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\n\n/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */\n#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */\n#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */\n#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)\n#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */\n#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)\n#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */\n\n/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/\n#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)\n#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */\n#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)\n#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */\n\n/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/\n#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */\n#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */\n#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)\n#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\n#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */\n#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */\n\n#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */\n#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DIEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DIEPCTL_STALL_Msk                (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */\n\n#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)\n#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\n#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */\n#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\n#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\n#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\n#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\n#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */\n#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */\n#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */\n#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */\n#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */\n\n/********************  Bit definition for USB_OTG_HCCHAR register  ********************/\n#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)\n#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */\n\n#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)\n#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\n#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */\n#define USB_OTG_HCCHAR_EPNUM_0                   (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCCHAR_EPNUM_1                   (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCCHAR_EPNUM_2                   (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\n#define USB_OTG_HCCHAR_EPNUM_3                   (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)\n#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */\n#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)\n#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */\n\n#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)\n#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */\n#define USB_OTG_HCCHAR_EPTYP_0                   (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_HCCHAR_EPTYP_1                   (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\n\n#define USB_OTG_HCCHAR_MC_Pos                    (20U)\n#define USB_OTG_HCCHAR_MC_Msk                    (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\n#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */\n#define USB_OTG_HCCHAR_MC_0                      (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\n#define USB_OTG_HCCHAR_MC_1                      (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\n\n#define USB_OTG_HCCHAR_DAD_Pos                   (22U)\n#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\n#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */\n#define USB_OTG_HCCHAR_DAD_0                     (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\n#define USB_OTG_HCCHAR_DAD_1                     (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\n#define USB_OTG_HCCHAR_DAD_2                     (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\n#define USB_OTG_HCCHAR_DAD_3                     (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\n#define USB_OTG_HCCHAR_DAD_4                     (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\n#define USB_OTG_HCCHAR_DAD_5                     (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\n#define USB_OTG_HCCHAR_DAD_6                     (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\n#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)\n#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */\n#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)\n#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */\n#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)\n#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */\n\n/********************  Bit definition for USB_OTG_HCSPLT register  ********************/\n\n#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)\n#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\n#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */\n#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\n\n#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)\n#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\n#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */\n#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\n\n#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)\n#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\n#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */\n#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)\n#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\n#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */\n#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)\n#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */\n\n/********************  Bit definition for USB_OTG_HCINT register  ********************/\n#define USB_OTG_HCINT_XFRC_Pos                   (0U)\n#define USB_OTG_HCINT_XFRC_Msk                   (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */\n#define USB_OTG_HCINT_CHH_Pos                    (1U)\n#define USB_OTG_HCINT_CHH_Msk                    (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */\n#define USB_OTG_HCINT_AHBERR_Pos                 (2U)\n#define USB_OTG_HCINT_AHBERR_Msk                 (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */\n#define USB_OTG_HCINT_STALL_Pos                  (3U)\n#define USB_OTG_HCINT_STALL_Msk                  (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */\n#define USB_OTG_HCINT_NAK_Pos                    (4U)\n#define USB_OTG_HCINT_NAK_Msk                    (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */\n#define USB_OTG_HCINT_ACK_Pos                    (5U)\n#define USB_OTG_HCINT_ACK_Msk                    (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */\n#define USB_OTG_HCINT_NYET_Pos                   (6U)\n#define USB_OTG_HCINT_NYET_Msk                   (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */\n#define USB_OTG_HCINT_TXERR_Pos                  (7U)\n#define USB_OTG_HCINT_TXERR_Msk                  (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */\n#define USB_OTG_HCINT_BBERR_Pos                  (8U)\n#define USB_OTG_HCINT_BBERR_Msk                  (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */\n#define USB_OTG_HCINT_FRMOR_Pos                  (9U)\n#define USB_OTG_HCINT_FRMOR_Msk                  (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */\n#define USB_OTG_HCINT_DTERR_Pos                  (10U)\n#define USB_OTG_HCINT_DTERR_Msk                  (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */\n\n/********************  Bit definition for USB_OTG_DIEPINT register  ********************/\n#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DIEPINT_TOC_Pos                  (3U)\n#define USB_OTG_DIEPINT_TOC_Msk                  (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */\n#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)\n#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */\n#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)\n#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */\n#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)\n#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\n#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\n#define USB_OTG_DIEPINT_BNA_Pos                  (9U)\n#define USB_OTG_DIEPINT_BNA_Msk                  (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */\n#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)\n#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\n#define USB_OTG_DIEPINT_BERR_Pos                 (12U)\n#define USB_OTG_DIEPINT_BERR_Msk                 (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\n#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */\n#define USB_OTG_DIEPINT_NAK_Pos                  (13U)\n#define USB_OTG_DIEPINT_NAK_Msk                  (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */\n\n/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/\n#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)\n#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */\n#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)\n#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */\n#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)\n#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */\n#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)\n#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */\n#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)\n#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */\n#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)\n#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */\n#define USB_OTG_HCINTMSK_NYET_Pos                (6U)\n#define USB_OTG_HCINTMSK_NYET_Msk                (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */\n#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)\n#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */\n#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)\n#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */\n#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)\n#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */\n#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)\n#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */\n\n/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/\n\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)\n#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */\n/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/\n#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)\n#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */\n#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)\n#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */\n#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)\n#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */\n#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)\n#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\n#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */\n#define USB_OTG_HCTSIZ_DPID_0                    (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCTSIZ_DPID_1                    (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/\n#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)\n#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_HCDMA register  ********************/\n#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)\n#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/\n#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)\n#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */\n\n/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/\n#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)\n#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */\n#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)\n#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/\n\n#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */\n#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */\n#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\n#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */\n#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */\n#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)\n#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\n#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */\n#define USB_OTG_DOEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DOEPCTL_STALL_Msk                (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */\n#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */\n#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */\n#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */\n\n/********************  Bit definition for USB_OTG_DOEPINT register  ********************/\n#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DOEPINT_STUP_Pos                 (3U)\n#define USB_OTG_DOEPINT_STUP_Msk                 (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */\n#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)\n#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */\n#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */\n#define USB_OTG_DOEPINT_NYET_Pos                 (14U)\n#define USB_OTG_DOEPINT_NYET_Msk                 (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */\n\n/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/\n\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n\n#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)\n#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */\n#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for PCGCCTL register  ********************/\n#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)\n#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */\n#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)\n#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */\n#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)\n#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_macros\n  * @{\n  */\n\n/******************************* ADC Instances ********************************/\n#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \\\n                                       ((INSTANCE) == ADC2) || \\\n                                       ((INSTANCE) == ADC3))\n\n#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\n\n#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)\n\n/******************************* CAN Instances ********************************/\n#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \\\n                                       ((INSTANCE) == CAN2))\n/******************************* CRC Instances ********************************/\n#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\n\n/******************************* DAC Instances ********************************/\n#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)\n\n/******************************* DCMI Instances *******************************/\n#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)\n\n/******************************** DMA Instances *******************************/\n#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \\\n                                              ((INSTANCE) == DMA1_Stream1) || \\\n                                              ((INSTANCE) == DMA1_Stream2) || \\\n                                              ((INSTANCE) == DMA1_Stream3) || \\\n                                              ((INSTANCE) == DMA1_Stream4) || \\\n                                              ((INSTANCE) == DMA1_Stream5) || \\\n                                              ((INSTANCE) == DMA1_Stream6) || \\\n                                              ((INSTANCE) == DMA1_Stream7) || \\\n                                              ((INSTANCE) == DMA2_Stream0) || \\\n                                              ((INSTANCE) == DMA2_Stream1) || \\\n                                              ((INSTANCE) == DMA2_Stream2) || \\\n                                              ((INSTANCE) == DMA2_Stream3) || \\\n                                              ((INSTANCE) == DMA2_Stream4) || \\\n                                              ((INSTANCE) == DMA2_Stream5) || \\\n                                              ((INSTANCE) == DMA2_Stream6) || \\\n                                              ((INSTANCE) == DMA2_Stream7))\n\n/******************************* GPIO Instances *******************************/\n#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\\n                                        ((INSTANCE) == GPIOB) || \\\n                                        ((INSTANCE) == GPIOC) || \\\n                                        ((INSTANCE) == GPIOD) || \\\n                                        ((INSTANCE) == GPIOE) || \\\n                                        ((INSTANCE) == GPIOF) || \\\n                                        ((INSTANCE) == GPIOG) || \\\n                                        ((INSTANCE) == GPIOH) || \\\n                                        ((INSTANCE) == GPIOI))\n\n/******************************** I2C Instances *******************************/\n#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\n                                       ((INSTANCE) == I2C2) || \\\n                                       ((INSTANCE) == I2C3))\n\n/******************************* SMBUS Instances ******************************/\n#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE\n\n/******************************** I2S Instances *******************************/\n\n#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \\\n                                       ((INSTANCE) == SPI3))\n\n/*************************** I2S Extended Instances ***************************/\n#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \\\n                                           ((INSTANCE) == I2S3ext))\n/* Legacy Defines */\n#define IS_I2S_ALL_INSTANCE_EXT    IS_I2S_EXT_ALL_INSTANCE\n\n/******************************* RNG Instances ********************************/\n#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)\n\n/****************************** RTC Instances *********************************/\n#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\n\n\n/******************************** SPI Instances *******************************/\n#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\\n                                       ((INSTANCE) == SPI2) || \\\n                                       ((INSTANCE) == SPI3))\n\n\n/****************** TIM Instances : All supported instances *******************/\n#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                    ((INSTANCE) == TIM2) || \\\n                                    ((INSTANCE) == TIM3) || \\\n                                    ((INSTANCE) == TIM4) || \\\n                                    ((INSTANCE) == TIM5) || \\\n                                    ((INSTANCE) == TIM6) || \\\n                                    ((INSTANCE) == TIM7) || \\\n                                    ((INSTANCE) == TIM8) || \\\n                                    ((INSTANCE) == TIM9) || \\\n                                    ((INSTANCE) == TIM10)|| \\\n                                    ((INSTANCE) == TIM11)|| \\\n                                    ((INSTANCE) == TIM12)|| \\\n                                    ((INSTANCE) == TIM13)|| \\\n                                    ((INSTANCE) == TIM14))\n\n/************* TIM Instances : at least 1 capture/compare channel *************/\n#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \\\n                                         ((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM3)  || \\\n                                         ((INSTANCE) == TIM4)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM8)  || \\\n                                         ((INSTANCE) == TIM9)  || \\\n                                         ((INSTANCE) == TIM10) || \\\n                                         ((INSTANCE) == TIM11) || \\\n                                         ((INSTANCE) == TIM12) || \\\n                                         ((INSTANCE) == TIM13) || \\\n                                         ((INSTANCE) == TIM14))\n\n/************ TIM Instances : at least 2 capture/compare channels *************/\n#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8) || \\\n                                       ((INSTANCE) == TIM9) || \\\n                                       ((INSTANCE) == TIM12))\n\n/************ TIM Instances : at least 3 capture/compare channels *************/\n#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/************ TIM Instances : at least 4 capture/compare channels *************/\n#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : Advanced-control timers *****************/\n#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                           ((INSTANCE) == TIM8))\n\n/******************* TIM Instances : Timer input XOR function *****************/\n#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : DMA requests generation (UDE) *************/\n#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM6) || \\\n                                       ((INSTANCE) == TIM7) || \\\n                                       ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (CCxDE) *****************/\n#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (COMDE) *****************/\n#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : DMA burst feature ***********************/\n#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                             ((INSTANCE) == TIM2) || \\\n                                             ((INSTANCE) == TIM3) || \\\n                                             ((INSTANCE) == TIM4) || \\\n                                             ((INSTANCE) == TIM5) || \\\n                                             ((INSTANCE) == TIM8))\n\n/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\n#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                          ((INSTANCE) == TIM2)  || \\\n                                          ((INSTANCE) == TIM3)  || \\\n                                          ((INSTANCE) == TIM4)  || \\\n                                          ((INSTANCE) == TIM5)  || \\\n                                          ((INSTANCE) == TIM6)  || \\\n                                          ((INSTANCE) == TIM7)  || \\\n                                          ((INSTANCE) == TIM8))\n\n/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\n#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8) || \\\n                                         ((INSTANCE) == TIM9) || \\\n                                         ((INSTANCE) == TIM12))\n\n/********************** TIM Instances : 32 bit Counter ************************/\n#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \\\n                                              ((INSTANCE) == TIM5))\n\n/***************** TIM Instances : external trigger input availabe ************/\n#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                        ((INSTANCE) == TIM2) || \\\n                                        ((INSTANCE) == TIM3) || \\\n                                        ((INSTANCE) == TIM4) || \\\n                                        ((INSTANCE) == TIM5) || \\\n                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : remapping capability **********************/\n#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM11))\n\n/******************* TIM Instances : output(s) available **********************/\n#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\\n    ((((INSTANCE) == TIM1) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM2) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM3) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM4) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM5) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM8) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM9) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM10) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM11) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM12) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM13) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM14) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1))))\n\n/************ TIM Instances : complementary output(s) available ***************/\n#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\\n   ((((INSTANCE) == TIM1) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3)))            \\\n    ||                                          \\\n    (((INSTANCE) == TIM8) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3))))\n\n/****************** TIM Instances : supporting counting mode selection ********/\n#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting clock division *****************/\n#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                                  ((INSTANCE) == TIM2) || \\\n                                                  ((INSTANCE) == TIM3) || \\\n                                                  ((INSTANCE) == TIM4) || \\\n                                                  ((INSTANCE) == TIM5) || \\\n                                                  ((INSTANCE) == TIM8) || \\\n                                                  ((INSTANCE) == TIM9) || \\\n                                                  ((INSTANCE) == TIM10)|| \\\n                                                  ((INSTANCE) == TIM11)|| \\\n                                                  ((INSTANCE) == TIM12)|| \\\n                                                  ((INSTANCE) == TIM13)|| \\\n                                                  ((INSTANCE) == TIM14))\n\n/****************** TIM Instances : supporting commutation event generation ***/\n#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \\\n                                                     ((INSTANCE) == TIM8))\n\n\n/****************** TIM Instances : supporting OCxREF clear *******************/\n#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM2) || \\\n                                                       ((INSTANCE) == TIM3) || \\\n                                                       ((INSTANCE) == TIM4) || \\\n                                                       ((INSTANCE) == TIM5) || \\\n                                                       ((INSTANCE) == TIM8))\n\n/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting repetition counter *************/\n#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting encoder interface **************/\n#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                      ((INSTANCE) == TIM2) || \\\n                                                      ((INSTANCE) == TIM3) || \\\n                                                      ((INSTANCE) == TIM4) || \\\n                                                      ((INSTANCE) == TIM5) || \\\n                                                      ((INSTANCE) == TIM8) || \\\n                                                      ((INSTANCE) == TIM9) || \\\n                                                      ((INSTANCE) == TIM12))\n/****************** TIM Instances : supporting Hall sensor interface **********/\n#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                          ((INSTANCE) == TIM2) || \\\n                                                          ((INSTANCE) == TIM3) || \\\n                                                          ((INSTANCE) == TIM4) || \\\n                                                          ((INSTANCE) == TIM5) || \\\n                                                          ((INSTANCE) == TIM8))\n/****************** TIM Instances : supporting the break function *************/\n#define IS_TIM_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM8))\n\n/******************** USART Instances : Synchronous mode **********************/\n#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                     ((INSTANCE) == USART2) || \\\n                                     ((INSTANCE) == USART3) || \\\n                                     ((INSTANCE) == USART6))\n\n/******************** UART Instances : Half-Duplex mode **********************/\n#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                               ((INSTANCE) == USART2) || \\\n                                               ((INSTANCE) == USART3) || \\\n                                               ((INSTANCE) == UART4)  || \\\n                                               ((INSTANCE) == UART5)  || \\\n                                               ((INSTANCE) == USART6))\n\n/* Legacy defines */\n#define IS_UART_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE\n\n/****************** UART Instances : Hardware Flow control ********************/\n#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                           ((INSTANCE) == USART2) || \\\n                                           ((INSTANCE) == USART3) || \\\n                                           ((INSTANCE) == USART6))\n/******************** UART Instances : LIN mode **********************/\n#define IS_UART_LIN_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE\n\n/********************* UART Instances : Smart card mode ***********************/\n#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                         ((INSTANCE) == USART2) || \\\n                                         ((INSTANCE) == USART3) || \\\n                                         ((INSTANCE) == USART6))\n\n/*********************** UART Instances : IRDA mode ***************************/\n#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2) || \\\n                                    ((INSTANCE) == USART3) || \\\n                                    ((INSTANCE) == UART4)  || \\\n                                    ((INSTANCE) == UART5)  || \\\n                                    ((INSTANCE) == USART6))\n\n\n/*********************** PCD Instances ****************************************/\n#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\\n                                       ((INSTANCE) == USB_OTG_HS))\n\n/*********************** HCD Instances ****************************************/\n#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\\n                                       ((INSTANCE) == USB_OTG_HS))\n\n/****************************** SDIO Instances ********************************/\n#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)\n\n/****************************** IWDG Instances ********************************/\n#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)\n\n/****************************** WWDG Instances ********************************/\n#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)\n\n/****************************** USB Exported Constants ************************/\n#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U\n#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */\n#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */\n#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */\n\n/*\n * @brief Specific devices reset values definitions\n */\n#define RCC_PLLCFGR_RST_VALUE              0x24003010U\n#define RCC_PLLI2SCFGR_RST_VALUE           0x20003000U\n\n#define RCC_MAX_FREQUENCY           168000000U         /*!< Max frequency of family in Hz*/\n#define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */\n#define RCC_MAX_FREQUENCY_SCALE2    144000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */\n#define RCC_PLLVCO_OUTPUT_MIN       100000000U       /*!< Frequency min for PLLVCO output, in Hz */\n#define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */\n\n#define RCC_PLLN_MIN_VALUE                 50U\n#define RCC_PLLN_MAX_VALUE                432U\n\n#define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */\n#define FLASH_SCALE1_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */\n#define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */\n#define FLASH_SCALE1_LATENCY4_FREQ   120000000U     /*!< HCLK frequency to set FLASH latency 4 in power scale 1  */\n#define FLASH_SCALE1_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */\n\n#define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */\n#define FLASH_SCALE2_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */\n#define FLASH_SCALE2_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */\n#define FLASH_SCALE2_LATENCY4_FREQ   12000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 2  */\n\n#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U\n#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */\n#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */\n#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */\n/******************************************************************************/\n/*  For a painless codes migration between the STM32F4xx device product       */\n/*  lines, the aliases defined below are put in place to overcome the         */\n/*  differences in the interrupt handlers and IRQn definitions.               */\n/*  No need to update developed interrupt code when moving across             */\n/*  product lines within the same STM32F4 Family                              */\n/******************************************************************************/\n/* Aliases for __IRQn */\n#define FMC_IRQn              FSMC_IRQn\n\n/* Aliases for __IRQHandler */\n#define FMC_IRQHandler        FSMC_IRQHandler\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32F407xx_H */\n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f411xe.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f411xe.h\n  * @author  MCD Application Team\n  * @version V2.6.4\n  * @date    06-December-2019\n  * @brief   CMSIS STM32F411xE Device Peripheral Access Layer Header File.\n  *\n  *          This file contains:\n  *           - Data structures and the address mapping for all peripherals\n  *           - peripherals registers declarations and bits definition\n  *           - Macros to access peripheral's registers hardware\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS_Device\n  * @{\n  */\n\n/** @addtogroup stm32f411xe\n  * @{\n  */\n\n#ifndef __STM32F411xE_H\n#define __STM32F411xE_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Configuration_section_for_CMSIS\n  * @{\n  */\n\n/**\n  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals\n  */\n#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */\n#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */\n#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */\n#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */\n#define __FPU_PRESENT             1U       /*!< FPU present                                   */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_interrupt_number_definition\n  * @{\n  */\n\n/**\n * @brief STM32F4XX Interrupt Number Definition, according to the selected device\n *        in @ref Library_configuration_section\n */\ntypedef enum\n{\n/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */\n  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */\n  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */\n  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */\n  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */\n  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */\n/******  STM32 specific Interrupt Numbers **********************************************************************/\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */\n  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */\n  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\n  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\n  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\n  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\n  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\n  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\n  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\n  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\n  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\n  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */\n  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */\n  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */\n  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */\n  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */\n  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */\n  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */\n  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\n  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */\n  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */\n  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\n  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\n  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */\n  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */\n  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\n  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */\n  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */\n  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */\n  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */\n  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */\n  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */\n  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */\n  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */\n  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */\n  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */\n  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\n  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\n  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */\n  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */\n  SPI5_IRQn                   = 85      /*!< SPI5 global Interrupt                                              */\n} IRQn_Type;\n\n/**\n  * @}\n  */\n\n#include \"core_cm4.h\"             /* Cortex-M4 processor and core peripherals */\n#include \"system_stm32f4xx.h\"\n#include <sys/stdint.h>\n\n/** @addtogroup Peripheral_registers_structures\n  * @{\n  */\n\n/**\n  * @brief Analog to Digital Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */\n  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */\n  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */\n  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */\n  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */\n  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\n  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\n  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\n  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\n  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */\n  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */\n  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */\n  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */\n  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */\n  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/\n  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */\n  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */\n  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */\n  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */\n  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */\n} ADC_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */\n  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */\n  __IO uint32_t CDR;    /*!< ADC common regular data register for dual\n                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */\n} ADC_Common_TypeDef;\n\n/**\n  * @brief CRC calculation unit\n  */\n\ntypedef struct\n{\n  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */\n  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */\n  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */\n  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */\n  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */\n} CRC_TypeDef;\n\n/**\n  * @brief Debug MCU\n  */\n\ntypedef struct\n{\n  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */\n  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */\n  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */\n  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */\n}DBGMCU_TypeDef;\n\n\n/**\n  * @brief DMA Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;     /*!< DMA stream x configuration register      */\n  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */\n  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */\n  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */\n  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */\n  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */\n} DMA_Stream_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */\n  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */\n  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */\n  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\n} DMA_TypeDef;\n\n/**\n  * @brief External Interrupt/Event Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */\n  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */\n  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */\n  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\n  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */\n  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */\n} EXTI_TypeDef;\n\n/**\n  * @brief FLASH Registers\n  */\n\ntypedef struct\n{\n  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */\n  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */\n  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */\n  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */\n  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */\n  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */\n  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */\n} FLASH_TypeDef;\n\n/**\n  * @brief General Purpose I/O\n  */\n\ntypedef struct\n{\n  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */\n  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */\n  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */\n  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\n  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */\n  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */\n  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */\n  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */\n  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\n} GPIO_TypeDef;\n\n/**\n  * @brief System configuration controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */\n  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */\n  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\n  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */\n  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */\n} SYSCFG_TypeDef;\n\n/**\n  * @brief Inter-integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */\n  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */\n  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */\n  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */\n  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */\n  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */\n  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */\n  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */\n  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */\n} I2C_TypeDef;\n\n/**\n  * @brief Independent WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */\n  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */\n  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */\n  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */\n} IWDG_TypeDef;\n\n\n/**\n  * @brief Power Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */\n  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */\n} PWR_TypeDef;\n\n/**\n  * @brief Reset and Clock Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */\n  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */\n  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */\n  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */\n  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */\n  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */\n  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */\n  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */\n  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */\n  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */\n  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */\n  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */\n  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */\n  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */\n  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */\n  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */\n  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */\n  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\n  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\n  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\n  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */\n  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\n  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\n  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */\n  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */\n  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */\n  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */\n  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */\n  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */\n  uint32_t      RESERVED7[1];  /*!< Reserved, 0x88                                                                    */\n  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */\n} RCC_TypeDef;\n\n/**\n  * @brief Real-Time Clock\n  */\n\ntypedef struct\n{\n  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */\n  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */\n  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */\n  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */\n  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */\n  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */\n  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */\n  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */\n  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */\n  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */\n  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */\n  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */\n  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */\n  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */\n  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */\n  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */\n  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */\n  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */\n  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */\n  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */\n  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */\n  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */\n  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */\n  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */\n  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */\n  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */\n  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */\n  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */\n  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */\n  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */\n  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */\n  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */\n  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */\n  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */\n  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */\n  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */\n  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */\n  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */\n  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */\n  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */\n} RTC_TypeDef;\n\n/**\n  * @brief SD host Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t POWER;                 /*!< SDIO power control register,    Address offset: 0x00 */\n  __IO uint32_t CLKCR;                 /*!< SDI clock control register,     Address offset: 0x04 */\n  __IO uint32_t ARG;                   /*!< SDIO argument register,         Address offset: 0x08 */\n  __IO uint32_t CMD;                   /*!< SDIO command register,          Address offset: 0x0C */\n  __IO const uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */\n  __IO const uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */\n  __IO const uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */\n  __IO const uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */\n  __IO const uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */\n  __IO uint32_t DTIMER;                /*!< SDIO data timer register,       Address offset: 0x24 */\n  __IO uint32_t DLEN;                  /*!< SDIO data length register,      Address offset: 0x28 */\n  __IO uint32_t DCTRL;                 /*!< SDIO data control register,     Address offset: 0x2C */\n  __IO const uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */\n  __IO const uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */\n  __IO uint32_t ICR;                   /*!< SDIO interrupt clear register,  Address offset: 0x38 */\n  __IO uint32_t MASK;                  /*!< SDIO mask register,             Address offset: 0x3C */\n  uint32_t      RESERVED0[2];          /*!< Reserved, 0x40-0x44                                  */\n  __IO const uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */\n  uint32_t      RESERVED1[13];         /*!< Reserved, 0x4C-0x7C                                  */\n  __IO uint32_t FIFO;                  /*!< SDIO data FIFO register,        Address offset: 0x80 */\n} SDIO_TypeDef;\n\n/**\n  * @brief Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */\n  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */\n  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */\n  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\n  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */\n  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */\n  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */\n  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */\n} SPI_TypeDef;\n\n\n/**\n  * @brief TIM\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */\n  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */\n  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */\n  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */\n  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */\n  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\n  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\n  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */\n  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */\n  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */\n  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */\n  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */\n  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */\n  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */\n  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */\n  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */\n  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */\n  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */\n  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */\n  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */\n} TIM_TypeDef;\n\n/**\n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */\n  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */\n  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */\n  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */\n  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */\n  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */\n  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */\n} USART_TypeDef;\n\n/**\n  * @brief Window WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */\n  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */\n  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */\n} WWDG_TypeDef;\n/**\n  * @brief USB_OTG_Core_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */\n  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */\n  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */\n  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */\n  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */\n  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */\n  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */\n  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */\n  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */\n  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */\n  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */\n  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */\n  uint32_t Reserved30[2];             /*!< Reserved                                     030h */\n  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */\n  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */\n  uint32_t  Reserved40[48];           /*!< Reserved                                0x40-0xFF */\n  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */\n  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                        */\n} USB_OTG_GlobalTypeDef;\n\n/**\n  * @brief USB_OTG_device_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */\n  __IO uint32_t DCTL;            /*!< dev Control Register         804h */\n  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */\n  uint32_t Reserved0C;           /*!< Reserved                     80Ch */\n  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */\n  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */\n  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */\n  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */\n  uint32_t  Reserved20;          /*!< Reserved                     820h */\n  uint32_t Reserved9;            /*!< Reserved                     824h */\n  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */\n  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */\n  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */\n  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */\n  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */\n  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */\n  uint32_t Reserved40;           /*!< dedicated EP mask            840h */\n  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */\n  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */\n  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */\n} USB_OTG_DeviceTypeDef;\n\n/**\n  * @brief USB_OTG_IN_Endpoint-Specific_Register\n  */\ntypedef struct\n{\n  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */\n  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */\n  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */\n  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\n  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\n} USB_OTG_INEndpointTypeDef;\n\n/**\n  * @brief USB_OTG_OUT_Endpoint-Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */\n  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */\n  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */\n  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\n} USB_OTG_OUTEndpointTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Mode_Register_Structures\n  */\ntypedef struct\n{\n  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */\n  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */\n  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */\n  uint32_t Reserved40C;           /*!< Reserved                             40Ch */\n  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */\n  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */\n  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */\n} USB_OTG_HostTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Channel_Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */\n  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */\n  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */\n  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */\n  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */\n  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */\n  uint32_t Reserved[2];           /*!< Reserved                                      */\n} USB_OTG_HostChannelTypeDef;\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_memory_map\n  * @{\n  */\n#define FLASH_BASE            0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region                         */\n#define SRAM1_BASE            0x20000000UL /*!< SRAM1(128 KB) base address in the alias region                             */\n#define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */\n#define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(128 KB) base address in the bit-band region                          */\n#define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */\n#define BKPSRAM_BB_BASE       0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region                      */\n#define FLASH_END             0x0807FFFFUL /*!< FLASH end address                                                          */\n#define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */\n#define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */\n\n/* Legacy defines */\n#define SRAM_BASE             SRAM1_BASE\n#define SRAM_BB_BASE          SRAM1_BB_BASE\n\n/*!< Peripheral memory map */\n#define APB1PERIPH_BASE       PERIPH_BASE\n#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)\n#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)\n#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)\n\n/*!< APB1 peripherals */\n#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)\n#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)\n#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)\n#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)\n#define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)\n#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)\n#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)\n#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400UL)\n#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)\n#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)\n#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000UL)\n#define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)\n#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)\n#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)\n#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)\n#define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)\n\n/*!< APB2 peripherals */\n#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)\n#define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)\n#define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)\n#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)\n#define ADC1_COMMON_BASE      (APB2PERIPH_BASE + 0x2300UL)\n/* Legacy define */\n#define ADC_BASE               ADC1_COMMON_BASE\n#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)\n#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)\n#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400UL)\n#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)\n#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)\n#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)\n#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)\n#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)\n#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000UL)\n\n/*!< AHB1 peripherals */\n#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)\n#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)\n#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)\n#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)\n#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)\n#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)\n#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)\n#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)\n#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)\n#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)\n#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)\n#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)\n#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)\n#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)\n#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)\n#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)\n#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)\n#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)\n#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)\n#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)\n#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)\n#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)\n#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)\n#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)\n#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)\n#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)\n#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)\n\n\n/*!< Debug MCU registers base address */\n#define DBGMCU_BASE           0xE0042000UL\n/*!< USB registers base address */\n#define USB_OTG_FS_PERIPH_BASE               0x50000000UL\n\n#define USB_OTG_GLOBAL_BASE                  0x000UL\n#define USB_OTG_DEVICE_BASE                  0x800UL\n#define USB_OTG_IN_ENDPOINT_BASE             0x900UL\n#define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL\n#define USB_OTG_EP_REG_SIZE                  0x20UL\n#define USB_OTG_HOST_BASE                    0x400UL\n#define USB_OTG_HOST_PORT_BASE               0x440UL\n#define USB_OTG_HOST_CHANNEL_BASE            0x500UL\n#define USB_OTG_HOST_CHANNEL_SIZE            0x20UL\n#define USB_OTG_PCGCCTL_BASE                 0xE00UL\n#define USB_OTG_FIFO_BASE                    0x1000UL\n#define USB_OTG_FIFO_SIZE                    0x1000UL\n\n#define UID_BASE                     0x1FFF7A10UL           /*!< Unique device ID register base address */\n#define FLASHSIZE_BASE               0x1FFF7A22UL           /*!< FLASH Size register base address       */\n#define PACKAGE_BASE                 0x1FFF7BF0UL           /*!< Package size register base address     */\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_declaration\n  * @{\n  */\n#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\n#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\n#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\n#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\n#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\n#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\n#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)\n#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\n#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\n#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)\n#define USART2              ((USART_TypeDef *) USART2_BASE)\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\n#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\n#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\n#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\n#define USART1              ((USART_TypeDef *) USART1_BASE)\n#define USART6              ((USART_TypeDef *) USART6_BASE)\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\n#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)\n/* Legacy define */\n#define ADC                  ADC1_COMMON\n#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\n#define SPI4                ((SPI_TypeDef *) SPI4_BASE)\n#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\n#define TIM9                ((TIM_TypeDef *) TIM9_BASE)\n#define TIM10               ((TIM_TypeDef *) TIM10_BASE)\n#define TIM11               ((TIM_TypeDef *) TIM11_BASE)\n#define SPI5                ((SPI_TypeDef *) SPI5_BASE)\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\n#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\n#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\n#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\n#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\n#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\n#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\n#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\n#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\n#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\n#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\n#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\n#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\n#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\n#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\n#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\n#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\n#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\n#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\n#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\n#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\n#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_constants\n  * @{\n  */\n\n  /** @addtogroup Peripheral_Registers_Bits_Definition\n  * @{\n  */\n\n/******************************************************************************/\n/*                         Peripheral Registers_Bits_Definition               */\n/******************************************************************************/\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Analog to Digital Converter                         */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for ADC_SR register  ********************/\n#define ADC_SR_AWD_Pos            (0U)\n#define ADC_SR_AWD_Msk            (0x1UL << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */\n#define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */\n#define ADC_SR_EOC_Pos            (1U)\n#define ADC_SR_EOC_Msk            (0x1UL << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */\n#define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */\n#define ADC_SR_JEOC_Pos           (2U)\n#define ADC_SR_JEOC_Msk           (0x1UL << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */\n#define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */\n#define ADC_SR_JSTRT_Pos          (3U)\n#define ADC_SR_JSTRT_Msk          (0x1UL << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */\n#define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */\n#define ADC_SR_STRT_Pos           (4U)\n#define ADC_SR_STRT_Msk           (0x1UL << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */\n#define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */\n#define ADC_SR_OVR_Pos            (5U)\n#define ADC_SR_OVR_Msk            (0x1UL << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */\n#define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */\n\n/*******************  Bit definition for ADC_CR1 register  ********************/\n#define ADC_CR1_AWDCH_Pos         (0U)\n#define ADC_CR1_AWDCH_Msk         (0x1FUL << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */\n#define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\n#define ADC_CR1_AWDCH_0           (0x01UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */\n#define ADC_CR1_AWDCH_1           (0x02UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */\n#define ADC_CR1_AWDCH_2           (0x04UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */\n#define ADC_CR1_AWDCH_3           (0x08UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */\n#define ADC_CR1_AWDCH_4           (0x10UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */\n#define ADC_CR1_EOCIE_Pos         (5U)\n#define ADC_CR1_EOCIE_Msk         (0x1UL << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */\n#define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */\n#define ADC_CR1_AWDIE_Pos         (6U)\n#define ADC_CR1_AWDIE_Msk         (0x1UL << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */\n#define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */\n#define ADC_CR1_JEOCIE_Pos        (7U)\n#define ADC_CR1_JEOCIE_Msk        (0x1UL << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */\n#define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */\n#define ADC_CR1_SCAN_Pos          (8U)\n#define ADC_CR1_SCAN_Msk          (0x1UL << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */\n#define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */\n#define ADC_CR1_AWDSGL_Pos        (9U)\n#define ADC_CR1_AWDSGL_Msk        (0x1UL << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */\n#define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */\n#define ADC_CR1_JAUTO_Pos         (10U)\n#define ADC_CR1_JAUTO_Msk         (0x1UL << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */\n#define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */\n#define ADC_CR1_DISCEN_Pos        (11U)\n#define ADC_CR1_DISCEN_Msk        (0x1UL << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */\n#define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */\n#define ADC_CR1_JDISCEN_Pos       (12U)\n#define ADC_CR1_JDISCEN_Msk       (0x1UL << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */\n#define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */\n#define ADC_CR1_DISCNUM_Pos       (13U)\n#define ADC_CR1_DISCNUM_Msk       (0x7UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */\n#define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\n#define ADC_CR1_DISCNUM_0         (0x1UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */\n#define ADC_CR1_DISCNUM_1         (0x2UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */\n#define ADC_CR1_DISCNUM_2         (0x4UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */\n#define ADC_CR1_JAWDEN_Pos        (22U)\n#define ADC_CR1_JAWDEN_Msk        (0x1UL << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */\n#define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */\n#define ADC_CR1_AWDEN_Pos         (23U)\n#define ADC_CR1_AWDEN_Msk         (0x1UL << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */\n#define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */\n#define ADC_CR1_RES_Pos           (24U)\n#define ADC_CR1_RES_Msk           (0x3UL << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */\n#define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */\n#define ADC_CR1_RES_0             (0x1UL << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */\n#define ADC_CR1_RES_1             (0x2UL << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */\n#define ADC_CR1_OVRIE_Pos         (26U)\n#define ADC_CR1_OVRIE_Msk         (0x1UL << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */\n#define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */\n\n/*******************  Bit definition for ADC_CR2 register  ********************/\n#define ADC_CR2_ADON_Pos          (0U)\n#define ADC_CR2_ADON_Msk          (0x1UL << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */\n#define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */\n#define ADC_CR2_CONT_Pos          (1U)\n#define ADC_CR2_CONT_Msk          (0x1UL << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */\n#define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */\n#define ADC_CR2_DMA_Pos           (8U)\n#define ADC_CR2_DMA_Msk           (0x1UL << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */\n#define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */\n#define ADC_CR2_DDS_Pos           (9U)\n#define ADC_CR2_DDS_Msk           (0x1UL << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */\n#define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */\n#define ADC_CR2_EOCS_Pos          (10U)\n#define ADC_CR2_EOCS_Msk          (0x1UL << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */\n#define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */\n#define ADC_CR2_ALIGN_Pos         (11U)\n#define ADC_CR2_ALIGN_Msk         (0x1UL << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */\n#define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */\n#define ADC_CR2_JEXTSEL_Pos       (16U)\n#define ADC_CR2_JEXTSEL_Msk       (0xFUL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */\n#define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */\n#define ADC_CR2_JEXTSEL_0         (0x1UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */\n#define ADC_CR2_JEXTSEL_1         (0x2UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */\n#define ADC_CR2_JEXTSEL_2         (0x4UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */\n#define ADC_CR2_JEXTSEL_3         (0x8UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */\n#define ADC_CR2_JEXTEN_Pos        (20U)\n#define ADC_CR2_JEXTEN_Msk        (0x3UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */\n#define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\n#define ADC_CR2_JEXTEN_0          (0x1UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */\n#define ADC_CR2_JEXTEN_1          (0x2UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */\n#define ADC_CR2_JSWSTART_Pos      (22U)\n#define ADC_CR2_JSWSTART_Msk      (0x1UL << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */\n#define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */\n#define ADC_CR2_EXTSEL_Pos        (24U)\n#define ADC_CR2_EXTSEL_Msk        (0xFUL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */\n#define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\n#define ADC_CR2_EXTSEL_0          (0x1UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */\n#define ADC_CR2_EXTSEL_1          (0x2UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */\n#define ADC_CR2_EXTSEL_2          (0x4UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */\n#define ADC_CR2_EXTSEL_3          (0x8UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */\n#define ADC_CR2_EXTEN_Pos         (28U)\n#define ADC_CR2_EXTEN_Msk         (0x3UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */\n#define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\n#define ADC_CR2_EXTEN_0           (0x1UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */\n#define ADC_CR2_EXTEN_1           (0x2UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */\n#define ADC_CR2_SWSTART_Pos       (30U)\n#define ADC_CR2_SWSTART_Msk       (0x1UL << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */\n#define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */\n\n/******************  Bit definition for ADC_SMPR1 register  *******************/\n#define ADC_SMPR1_SMP10_Pos       (0U)\n#define ADC_SMPR1_SMP10_Msk       (0x7UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */\n#define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\n#define ADC_SMPR1_SMP10_0         (0x1UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */\n#define ADC_SMPR1_SMP10_1         (0x2UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */\n#define ADC_SMPR1_SMP10_2         (0x4UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */\n#define ADC_SMPR1_SMP11_Pos       (3U)\n#define ADC_SMPR1_SMP11_Msk       (0x7UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */\n#define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\n#define ADC_SMPR1_SMP11_0         (0x1UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */\n#define ADC_SMPR1_SMP11_1         (0x2UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */\n#define ADC_SMPR1_SMP11_2         (0x4UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */\n#define ADC_SMPR1_SMP12_Pos       (6U)\n#define ADC_SMPR1_SMP12_Msk       (0x7UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */\n#define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\n#define ADC_SMPR1_SMP12_0         (0x1UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */\n#define ADC_SMPR1_SMP12_1         (0x2UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */\n#define ADC_SMPR1_SMP12_2         (0x4UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */\n#define ADC_SMPR1_SMP13_Pos       (9U)\n#define ADC_SMPR1_SMP13_Msk       (0x7UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */\n#define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\n#define ADC_SMPR1_SMP13_0         (0x1UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */\n#define ADC_SMPR1_SMP13_1         (0x2UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */\n#define ADC_SMPR1_SMP13_2         (0x4UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */\n#define ADC_SMPR1_SMP14_Pos       (12U)\n#define ADC_SMPR1_SMP14_Msk       (0x7UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */\n#define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\n#define ADC_SMPR1_SMP14_0         (0x1UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */\n#define ADC_SMPR1_SMP14_1         (0x2UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */\n#define ADC_SMPR1_SMP14_2         (0x4UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */\n#define ADC_SMPR1_SMP15_Pos       (15U)\n#define ADC_SMPR1_SMP15_Msk       (0x7UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */\n#define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\n#define ADC_SMPR1_SMP15_0         (0x1UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */\n#define ADC_SMPR1_SMP15_1         (0x2UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */\n#define ADC_SMPR1_SMP15_2         (0x4UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */\n#define ADC_SMPR1_SMP16_Pos       (18U)\n#define ADC_SMPR1_SMP16_Msk       (0x7UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */\n#define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\n#define ADC_SMPR1_SMP16_0         (0x1UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */\n#define ADC_SMPR1_SMP16_1         (0x2UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */\n#define ADC_SMPR1_SMP16_2         (0x4UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */\n#define ADC_SMPR1_SMP17_Pos       (21U)\n#define ADC_SMPR1_SMP17_Msk       (0x7UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */\n#define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\n#define ADC_SMPR1_SMP17_0         (0x1UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */\n#define ADC_SMPR1_SMP17_1         (0x2UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */\n#define ADC_SMPR1_SMP17_2         (0x4UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */\n#define ADC_SMPR1_SMP18_Pos       (24U)\n#define ADC_SMPR1_SMP18_Msk       (0x7UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */\n#define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\n#define ADC_SMPR1_SMP18_0         (0x1UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */\n#define ADC_SMPR1_SMP18_1         (0x2UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */\n#define ADC_SMPR1_SMP18_2         (0x4UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */\n\n/******************  Bit definition for ADC_SMPR2 register  *******************/\n#define ADC_SMPR2_SMP0_Pos        (0U)\n#define ADC_SMPR2_SMP0_Msk        (0x7UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */\n#define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\n#define ADC_SMPR2_SMP0_0          (0x1UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */\n#define ADC_SMPR2_SMP0_1          (0x2UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */\n#define ADC_SMPR2_SMP0_2          (0x4UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */\n#define ADC_SMPR2_SMP1_Pos        (3U)\n#define ADC_SMPR2_SMP1_Msk        (0x7UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */\n#define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\n#define ADC_SMPR2_SMP1_0          (0x1UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */\n#define ADC_SMPR2_SMP1_1          (0x2UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */\n#define ADC_SMPR2_SMP1_2          (0x4UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */\n#define ADC_SMPR2_SMP2_Pos        (6U)\n#define ADC_SMPR2_SMP2_Msk        (0x7UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */\n#define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\n#define ADC_SMPR2_SMP2_0          (0x1UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */\n#define ADC_SMPR2_SMP2_1          (0x2UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */\n#define ADC_SMPR2_SMP2_2          (0x4UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */\n#define ADC_SMPR2_SMP3_Pos        (9U)\n#define ADC_SMPR2_SMP3_Msk        (0x7UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */\n#define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\n#define ADC_SMPR2_SMP3_0          (0x1UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */\n#define ADC_SMPR2_SMP3_1          (0x2UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */\n#define ADC_SMPR2_SMP3_2          (0x4UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */\n#define ADC_SMPR2_SMP4_Pos        (12U)\n#define ADC_SMPR2_SMP4_Msk        (0x7UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */\n#define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\n#define ADC_SMPR2_SMP4_0          (0x1UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */\n#define ADC_SMPR2_SMP4_1          (0x2UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */\n#define ADC_SMPR2_SMP4_2          (0x4UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */\n#define ADC_SMPR2_SMP5_Pos        (15U)\n#define ADC_SMPR2_SMP5_Msk        (0x7UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */\n#define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\n#define ADC_SMPR2_SMP5_0          (0x1UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */\n#define ADC_SMPR2_SMP5_1          (0x2UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */\n#define ADC_SMPR2_SMP5_2          (0x4UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */\n#define ADC_SMPR2_SMP6_Pos        (18U)\n#define ADC_SMPR2_SMP6_Msk        (0x7UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */\n#define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\n#define ADC_SMPR2_SMP6_0          (0x1UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */\n#define ADC_SMPR2_SMP6_1          (0x2UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */\n#define ADC_SMPR2_SMP6_2          (0x4UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */\n#define ADC_SMPR2_SMP7_Pos        (21U)\n#define ADC_SMPR2_SMP7_Msk        (0x7UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */\n#define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\n#define ADC_SMPR2_SMP7_0          (0x1UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */\n#define ADC_SMPR2_SMP7_1          (0x2UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */\n#define ADC_SMPR2_SMP7_2          (0x4UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */\n#define ADC_SMPR2_SMP8_Pos        (24U)\n#define ADC_SMPR2_SMP8_Msk        (0x7UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */\n#define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\n#define ADC_SMPR2_SMP8_0          (0x1UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */\n#define ADC_SMPR2_SMP8_1          (0x2UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */\n#define ADC_SMPR2_SMP8_2          (0x4UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */\n#define ADC_SMPR2_SMP9_Pos        (27U)\n#define ADC_SMPR2_SMP9_Msk        (0x7UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */\n#define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\n#define ADC_SMPR2_SMP9_0          (0x1UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */\n#define ADC_SMPR2_SMP9_1          (0x2UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */\n#define ADC_SMPR2_SMP9_2          (0x4UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */\n\n/******************  Bit definition for ADC_JOFR1 register  *******************/\n#define ADC_JOFR1_JOFFSET1_Pos    (0U)\n#define ADC_JOFR1_JOFFSET1_Msk    (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */\n\n/******************  Bit definition for ADC_JOFR2 register  *******************/\n#define ADC_JOFR2_JOFFSET2_Pos    (0U)\n#define ADC_JOFR2_JOFFSET2_Msk    (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */\n\n/******************  Bit definition for ADC_JOFR3 register  *******************/\n#define ADC_JOFR3_JOFFSET3_Pos    (0U)\n#define ADC_JOFR3_JOFFSET3_Msk    (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */\n\n/******************  Bit definition for ADC_JOFR4 register  *******************/\n#define ADC_JOFR4_JOFFSET4_Pos    (0U)\n#define ADC_JOFR4_JOFFSET4_Msk    (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */\n\n/*******************  Bit definition for ADC_HTR register  ********************/\n#define ADC_HTR_HT_Pos            (0U)\n#define ADC_HTR_HT_Msk            (0xFFFUL << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */\n#define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */\n\n/*******************  Bit definition for ADC_LTR register  ********************/\n#define ADC_LTR_LT_Pos            (0U)\n#define ADC_LTR_LT_Msk            (0xFFFUL << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */\n#define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */\n\n/*******************  Bit definition for ADC_SQR1 register  *******************/\n#define ADC_SQR1_SQ13_Pos         (0U)\n#define ADC_SQR1_SQ13_Msk         (0x1FUL << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */\n#define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\n#define ADC_SQR1_SQ13_0           (0x01UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */\n#define ADC_SQR1_SQ13_1           (0x02UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */\n#define ADC_SQR1_SQ13_2           (0x04UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */\n#define ADC_SQR1_SQ13_3           (0x08UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */\n#define ADC_SQR1_SQ13_4           (0x10UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */\n#define ADC_SQR1_SQ14_Pos         (5U)\n#define ADC_SQR1_SQ14_Msk         (0x1FUL << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */\n#define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\n#define ADC_SQR1_SQ14_0           (0x01UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */\n#define ADC_SQR1_SQ14_1           (0x02UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */\n#define ADC_SQR1_SQ14_2           (0x04UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */\n#define ADC_SQR1_SQ14_3           (0x08UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */\n#define ADC_SQR1_SQ14_4           (0x10UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */\n#define ADC_SQR1_SQ15_Pos         (10U)\n#define ADC_SQR1_SQ15_Msk         (0x1FUL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */\n#define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\n#define ADC_SQR1_SQ15_0           (0x01UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */\n#define ADC_SQR1_SQ15_1           (0x02UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */\n#define ADC_SQR1_SQ15_2           (0x04UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */\n#define ADC_SQR1_SQ15_3           (0x08UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */\n#define ADC_SQR1_SQ15_4           (0x10UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */\n#define ADC_SQR1_SQ16_Pos         (15U)\n#define ADC_SQR1_SQ16_Msk         (0x1FUL << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\n#define ADC_SQR1_SQ16_0           (0x01UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR1_SQ16_1           (0x02UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR1_SQ16_2           (0x04UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR1_SQ16_3           (0x08UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR1_SQ16_4           (0x10UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR1_L_Pos            (20U)\n#define ADC_SQR1_L_Msk            (0xFUL << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */\n#define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */\n#define ADC_SQR1_L_0              (0x1UL << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */\n#define ADC_SQR1_L_1              (0x2UL << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */\n#define ADC_SQR1_L_2              (0x4UL << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */\n#define ADC_SQR1_L_3              (0x8UL << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */\n\n/*******************  Bit definition for ADC_SQR2 register  *******************/\n#define ADC_SQR2_SQ7_Pos          (0U)\n#define ADC_SQR2_SQ7_Msk          (0x1FUL << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\n#define ADC_SQR2_SQ7_0            (0x01UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR2_SQ7_1            (0x02UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR2_SQ7_2            (0x04UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR2_SQ7_3            (0x08UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR2_SQ7_4            (0x10UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR2_SQ8_Pos          (5U)\n#define ADC_SQR2_SQ8_Msk          (0x1FUL << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\n#define ADC_SQR2_SQ8_0            (0x01UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR2_SQ8_1            (0x02UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR2_SQ8_2            (0x04UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR2_SQ8_3            (0x08UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR2_SQ8_4            (0x10UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR2_SQ9_Pos          (10U)\n#define ADC_SQR2_SQ9_Msk          (0x1FUL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\n#define ADC_SQR2_SQ9_0            (0x01UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR2_SQ9_1            (0x02UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR2_SQ9_2            (0x04UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR2_SQ9_3            (0x08UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR2_SQ9_4            (0x10UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR2_SQ10_Pos         (15U)\n#define ADC_SQR2_SQ10_Msk         (0x1FUL << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\n#define ADC_SQR2_SQ10_0           (0x01UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR2_SQ10_1           (0x02UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR2_SQ10_2           (0x04UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR2_SQ10_3           (0x08UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR2_SQ10_4           (0x10UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR2_SQ11_Pos         (20U)\n#define ADC_SQR2_SQ11_Msk         (0x1FUL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */\n#define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\n#define ADC_SQR2_SQ11_0           (0x01UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */\n#define ADC_SQR2_SQ11_1           (0x02UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */\n#define ADC_SQR2_SQ11_2           (0x04UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */\n#define ADC_SQR2_SQ11_3           (0x08UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */\n#define ADC_SQR2_SQ11_4           (0x10UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */\n#define ADC_SQR2_SQ12_Pos         (25U)\n#define ADC_SQR2_SQ12_Msk         (0x1FUL << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */\n#define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\n#define ADC_SQR2_SQ12_0           (0x01UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */\n#define ADC_SQR2_SQ12_1           (0x02UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */\n#define ADC_SQR2_SQ12_2           (0x04UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */\n#define ADC_SQR2_SQ12_3           (0x08UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */\n#define ADC_SQR2_SQ12_4           (0x10UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_SQR3 register  *******************/\n#define ADC_SQR3_SQ1_Pos          (0U)\n#define ADC_SQR3_SQ1_Msk          (0x1FUL << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\n#define ADC_SQR3_SQ1_0            (0x01UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR3_SQ1_1            (0x02UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR3_SQ1_2            (0x04UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR3_SQ1_3            (0x08UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR3_SQ1_4            (0x10UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR3_SQ2_Pos          (5U)\n#define ADC_SQR3_SQ2_Msk          (0x1FUL << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\n#define ADC_SQR3_SQ2_0            (0x01UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR3_SQ2_1            (0x02UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR3_SQ2_2            (0x04UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR3_SQ2_3            (0x08UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR3_SQ2_4            (0x10UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR3_SQ3_Pos          (10U)\n#define ADC_SQR3_SQ3_Msk          (0x1FUL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\n#define ADC_SQR3_SQ3_0            (0x01UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR3_SQ3_1            (0x02UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR3_SQ3_2            (0x04UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR3_SQ3_3            (0x08UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR3_SQ3_4            (0x10UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR3_SQ4_Pos          (15U)\n#define ADC_SQR3_SQ4_Msk          (0x1FUL << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */\n#define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\n#define ADC_SQR3_SQ4_0            (0x01UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */\n#define ADC_SQR3_SQ4_1            (0x02UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */\n#define ADC_SQR3_SQ4_2            (0x04UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */\n#define ADC_SQR3_SQ4_3            (0x08UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */\n#define ADC_SQR3_SQ4_4            (0x10UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */\n#define ADC_SQR3_SQ5_Pos          (20U)\n#define ADC_SQR3_SQ5_Msk          (0x1FUL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */\n#define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\n#define ADC_SQR3_SQ5_0            (0x01UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */\n#define ADC_SQR3_SQ5_1            (0x02UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */\n#define ADC_SQR3_SQ5_2            (0x04UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */\n#define ADC_SQR3_SQ5_3            (0x08UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */\n#define ADC_SQR3_SQ5_4            (0x10UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */\n#define ADC_SQR3_SQ6_Pos          (25U)\n#define ADC_SQR3_SQ6_Msk          (0x1FUL << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */\n#define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\n#define ADC_SQR3_SQ6_0            (0x01UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */\n#define ADC_SQR3_SQ6_1            (0x02UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */\n#define ADC_SQR3_SQ6_2            (0x04UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */\n#define ADC_SQR3_SQ6_3            (0x08UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */\n#define ADC_SQR3_SQ6_4            (0x10UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_JSQR register  *******************/\n#define ADC_JSQR_JSQ1_Pos         (0U)\n#define ADC_JSQR_JSQ1_Msk         (0x1FUL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */\n#define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */\n#define ADC_JSQR_JSQ1_0           (0x01UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */\n#define ADC_JSQR_JSQ1_1           (0x02UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */\n#define ADC_JSQR_JSQ1_2           (0x04UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */\n#define ADC_JSQR_JSQ1_3           (0x08UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */\n#define ADC_JSQR_JSQ1_4           (0x10UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */\n#define ADC_JSQR_JSQ2_Pos         (5U)\n#define ADC_JSQR_JSQ2_Msk         (0x1FUL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */\n#define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\n#define ADC_JSQR_JSQ2_0           (0x01UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */\n#define ADC_JSQR_JSQ2_1           (0x02UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */\n#define ADC_JSQR_JSQ2_2           (0x04UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */\n#define ADC_JSQR_JSQ2_3           (0x08UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */\n#define ADC_JSQR_JSQ2_4           (0x10UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */\n#define ADC_JSQR_JSQ3_Pos         (10U)\n#define ADC_JSQR_JSQ3_Msk         (0x1FUL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */\n#define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\n#define ADC_JSQR_JSQ3_0           (0x01UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */\n#define ADC_JSQR_JSQ3_1           (0x02UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */\n#define ADC_JSQR_JSQ3_2           (0x04UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */\n#define ADC_JSQR_JSQ3_3           (0x08UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */\n#define ADC_JSQR_JSQ3_4           (0x10UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */\n#define ADC_JSQR_JSQ4_Pos         (15U)\n#define ADC_JSQR_JSQ4_Msk         (0x1FUL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */\n#define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\n#define ADC_JSQR_JSQ4_0           (0x01UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */\n#define ADC_JSQR_JSQ4_1           (0x02UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */\n#define ADC_JSQR_JSQ4_2           (0x04UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */\n#define ADC_JSQR_JSQ4_3           (0x08UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */\n#define ADC_JSQR_JSQ4_4           (0x10UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */\n#define ADC_JSQR_JL_Pos           (20U)\n#define ADC_JSQR_JL_Msk           (0x3UL << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */\n#define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */\n#define ADC_JSQR_JL_0             (0x1UL << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */\n#define ADC_JSQR_JL_1             (0x2UL << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */\n\n/*******************  Bit definition for ADC_JDR1 register  *******************/\n#define ADC_JDR1_JDATA_Pos        (0U)\n#define ADC_JDR1_JDATA_Msk        (0xFFFFUL << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR2 register  *******************/\n#define ADC_JDR2_JDATA_Pos        (0U)\n#define ADC_JDR2_JDATA_Msk        (0xFFFFUL << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR3 register  *******************/\n#define ADC_JDR3_JDATA_Pos        (0U)\n#define ADC_JDR3_JDATA_Msk        (0xFFFFUL << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR4 register  *******************/\n#define ADC_JDR4_JDATA_Pos        (0U)\n#define ADC_JDR4_JDATA_Msk        (0xFFFFUL << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */\n\n/********************  Bit definition for ADC_DR register  ********************/\n#define ADC_DR_DATA_Pos           (0U)\n#define ADC_DR_DATA_Msk           (0xFFFFUL << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */\n#define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */\n#define ADC_DR_ADC2DATA_Pos       (16U)\n#define ADC_DR_ADC2DATA_Msk       (0xFFFFUL << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */\n#define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */\n\n/*******************  Bit definition for ADC_CSR register  ********************/\n#define ADC_CSR_AWD1_Pos          (0U)\n#define ADC_CSR_AWD1_Msk          (0x1UL << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */\n#define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */\n#define ADC_CSR_EOC1_Pos          (1U)\n#define ADC_CSR_EOC1_Msk          (0x1UL << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */\n#define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */\n#define ADC_CSR_JEOC1_Pos         (2U)\n#define ADC_CSR_JEOC1_Msk         (0x1UL << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */\n#define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */\n#define ADC_CSR_JSTRT1_Pos        (3U)\n#define ADC_CSR_JSTRT1_Msk        (0x1UL << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */\n#define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */\n#define ADC_CSR_STRT1_Pos         (4U)\n#define ADC_CSR_STRT1_Msk         (0x1UL << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */\n#define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */\n#define ADC_CSR_OVR1_Pos          (5U)\n#define ADC_CSR_OVR1_Msk          (0x1UL << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */\n#define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */\n\n/* Legacy defines */\n#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1\n\n/*******************  Bit definition for ADC_CCR register  ********************/\n#define ADC_CCR_MULTI_Pos         (0U)\n#define ADC_CCR_MULTI_Msk         (0x1FUL << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */\n#define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */\n#define ADC_CCR_MULTI_0           (0x01UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */\n#define ADC_CCR_MULTI_1           (0x02UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */\n#define ADC_CCR_MULTI_2           (0x04UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */\n#define ADC_CCR_MULTI_3           (0x08UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */\n#define ADC_CCR_MULTI_4           (0x10UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */\n#define ADC_CCR_DELAY_Pos         (8U)\n#define ADC_CCR_DELAY_Msk         (0xFUL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */\n#define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */\n#define ADC_CCR_DELAY_0           (0x1UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */\n#define ADC_CCR_DELAY_1           (0x2UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */\n#define ADC_CCR_DELAY_2           (0x4UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */\n#define ADC_CCR_DELAY_3           (0x8UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */\n#define ADC_CCR_DDS_Pos           (13U)\n#define ADC_CCR_DDS_Msk           (0x1UL << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */\n#define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */\n#define ADC_CCR_DMA_Pos           (14U)\n#define ADC_CCR_DMA_Msk           (0x3UL << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */\n#define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */\n#define ADC_CCR_DMA_0             (0x1UL << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */\n#define ADC_CCR_DMA_1             (0x2UL << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */\n#define ADC_CCR_ADCPRE_Pos        (16U)\n#define ADC_CCR_ADCPRE_Msk        (0x3UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */\n#define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */\n#define ADC_CCR_ADCPRE_0          (0x1UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */\n#define ADC_CCR_ADCPRE_1          (0x2UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */\n#define ADC_CCR_VBATE_Pos         (22U)\n#define ADC_CCR_VBATE_Msk         (0x1UL << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */\n#define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */\n#define ADC_CCR_TSVREFE_Pos       (23U)\n#define ADC_CCR_TSVREFE_Msk       (0x1UL << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */\n#define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */\n\n/*******************  Bit definition for ADC_CDR register  ********************/\n#define ADC_CDR_DATA1_Pos         (0U)\n#define ADC_CDR_DATA1_Msk         (0xFFFFUL << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */\n#define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */\n#define ADC_CDR_DATA2_Pos         (16U)\n#define ADC_CDR_DATA2_Msk         (0xFFFFUL << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */\n#define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */\n\n/* Legacy defines */\n#define ADC_CDR_RDATA_MST         ADC_CDR_DATA1\n#define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2\n\n/******************************************************************************/\n/*                                                                            */\n/*                          CRC calculation unit                              */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for CRC_DR register  *********************/\n#define CRC_DR_DR_Pos       (0U)\n#define CRC_DR_DR_Msk       (0xFFFFFFFFUL << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */\n#define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */\n\n\n/*******************  Bit definition for CRC_IDR register  ********************/\n#define CRC_IDR_IDR_Pos     (0U)\n#define CRC_IDR_IDR_Msk     (0xFFUL << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */\n#define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */\n\n\n/********************  Bit definition for CRC_CR register  ********************/\n#define CRC_CR_RESET_Pos    (0U)\n#define CRC_CR_RESET_Msk    (0x1UL << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */\n#define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                             DMA Controller                                 */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DMA_SxCR register  *****************/\n#define DMA_SxCR_CHSEL_Pos       (25U)\n#define DMA_SxCR_CHSEL_Msk       (0x7UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */\n#define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk\n#define DMA_SxCR_CHSEL_0         0x02000000U\n#define DMA_SxCR_CHSEL_1         0x04000000U\n#define DMA_SxCR_CHSEL_2         0x08000000U\n#define DMA_SxCR_MBURST_Pos      (23U)\n#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */\n#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk\n#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */\n#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */\n#define DMA_SxCR_PBURST_Pos      (21U)\n#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */\n#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk\n#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */\n#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */\n#define DMA_SxCR_CT_Pos          (19U)\n#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */\n#define DMA_SxCR_CT              DMA_SxCR_CT_Msk\n#define DMA_SxCR_DBM_Pos         (18U)\n#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */\n#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk\n#define DMA_SxCR_PL_Pos          (16U)\n#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */\n#define DMA_SxCR_PL              DMA_SxCR_PL_Msk\n#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */\n#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */\n#define DMA_SxCR_PINCOS_Pos      (15U)\n#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */\n#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk\n#define DMA_SxCR_MSIZE_Pos       (13U)\n#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */\n#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk\n#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */\n#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */\n#define DMA_SxCR_PSIZE_Pos       (11U)\n#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */\n#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk\n#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */\n#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */\n#define DMA_SxCR_MINC_Pos        (10U)\n#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */\n#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk\n#define DMA_SxCR_PINC_Pos        (9U)\n#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */\n#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk\n#define DMA_SxCR_CIRC_Pos        (8U)\n#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */\n#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk\n#define DMA_SxCR_DIR_Pos         (6U)\n#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */\n#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk\n#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */\n#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */\n#define DMA_SxCR_PFCTRL_Pos      (5U)\n#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */\n#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk\n#define DMA_SxCR_TCIE_Pos        (4U)\n#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */\n#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk\n#define DMA_SxCR_HTIE_Pos        (3U)\n#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */\n#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk\n#define DMA_SxCR_TEIE_Pos        (2U)\n#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */\n#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk\n#define DMA_SxCR_DMEIE_Pos       (1U)\n#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */\n#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk\n#define DMA_SxCR_EN_Pos          (0U)\n#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */\n#define DMA_SxCR_EN              DMA_SxCR_EN_Msk\n\n/* Legacy defines */\n#define DMA_SxCR_ACK_Pos         (20U)\n#define DMA_SxCR_ACK_Msk         (0x1UL << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */\n#define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk\n\n/********************  Bits definition for DMA_SxCNDTR register  **************/\n#define DMA_SxNDT_Pos            (0U)\n#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */\n#define DMA_SxNDT                DMA_SxNDT_Msk\n#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */\n#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */\n#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */\n#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */\n#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */\n#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */\n#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */\n#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */\n#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */\n#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */\n#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */\n#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */\n#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */\n#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */\n#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */\n#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */\n\n/********************  Bits definition for DMA_SxFCR register  ****************/\n#define DMA_SxFCR_FEIE_Pos       (7U)\n#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */\n#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk\n#define DMA_SxFCR_FS_Pos         (3U)\n#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */\n#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk\n#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */\n#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */\n#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */\n#define DMA_SxFCR_DMDIS_Pos      (2U)\n#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */\n#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk\n#define DMA_SxFCR_FTH_Pos        (0U)\n#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */\n#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk\n#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */\n#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */\n\n/********************  Bits definition for DMA_LISR register  *****************/\n#define DMA_LISR_TCIF3_Pos       (27U)\n#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */\n#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk\n#define DMA_LISR_HTIF3_Pos       (26U)\n#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */\n#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk\n#define DMA_LISR_TEIF3_Pos       (25U)\n#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */\n#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk\n#define DMA_LISR_DMEIF3_Pos      (24U)\n#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */\n#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk\n#define DMA_LISR_FEIF3_Pos       (22U)\n#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */\n#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk\n#define DMA_LISR_TCIF2_Pos       (21U)\n#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */\n#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk\n#define DMA_LISR_HTIF2_Pos       (20U)\n#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */\n#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk\n#define DMA_LISR_TEIF2_Pos       (19U)\n#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */\n#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk\n#define DMA_LISR_DMEIF2_Pos      (18U)\n#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */\n#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk\n#define DMA_LISR_FEIF2_Pos       (16U)\n#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */\n#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk\n#define DMA_LISR_TCIF1_Pos       (11U)\n#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */\n#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk\n#define DMA_LISR_HTIF1_Pos       (10U)\n#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */\n#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk\n#define DMA_LISR_TEIF1_Pos       (9U)\n#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */\n#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk\n#define DMA_LISR_DMEIF1_Pos      (8U)\n#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */\n#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk\n#define DMA_LISR_FEIF1_Pos       (6U)\n#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */\n#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk\n#define DMA_LISR_TCIF0_Pos       (5U)\n#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */\n#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk\n#define DMA_LISR_HTIF0_Pos       (4U)\n#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */\n#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk\n#define DMA_LISR_TEIF0_Pos       (3U)\n#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */\n#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk\n#define DMA_LISR_DMEIF0_Pos      (2U)\n#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */\n#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk\n#define DMA_LISR_FEIF0_Pos       (0U)\n#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */\n#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk\n\n/********************  Bits definition for DMA_HISR register  *****************/\n#define DMA_HISR_TCIF7_Pos       (27U)\n#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */\n#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk\n#define DMA_HISR_HTIF7_Pos       (26U)\n#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */\n#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk\n#define DMA_HISR_TEIF7_Pos       (25U)\n#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */\n#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk\n#define DMA_HISR_DMEIF7_Pos      (24U)\n#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */\n#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk\n#define DMA_HISR_FEIF7_Pos       (22U)\n#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */\n#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk\n#define DMA_HISR_TCIF6_Pos       (21U)\n#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */\n#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk\n#define DMA_HISR_HTIF6_Pos       (20U)\n#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */\n#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk\n#define DMA_HISR_TEIF6_Pos       (19U)\n#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */\n#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk\n#define DMA_HISR_DMEIF6_Pos      (18U)\n#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */\n#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk\n#define DMA_HISR_FEIF6_Pos       (16U)\n#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */\n#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk\n#define DMA_HISR_TCIF5_Pos       (11U)\n#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */\n#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk\n#define DMA_HISR_HTIF5_Pos       (10U)\n#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */\n#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk\n#define DMA_HISR_TEIF5_Pos       (9U)\n#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */\n#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk\n#define DMA_HISR_DMEIF5_Pos      (8U)\n#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */\n#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk\n#define DMA_HISR_FEIF5_Pos       (6U)\n#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */\n#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk\n#define DMA_HISR_TCIF4_Pos       (5U)\n#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */\n#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk\n#define DMA_HISR_HTIF4_Pos       (4U)\n#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */\n#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk\n#define DMA_HISR_TEIF4_Pos       (3U)\n#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */\n#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk\n#define DMA_HISR_DMEIF4_Pos      (2U)\n#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */\n#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk\n#define DMA_HISR_FEIF4_Pos       (0U)\n#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */\n#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk\n\n/********************  Bits definition for DMA_LIFCR register  ****************/\n#define DMA_LIFCR_CTCIF3_Pos     (27U)\n#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */\n#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk\n#define DMA_LIFCR_CHTIF3_Pos     (26U)\n#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */\n#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk\n#define DMA_LIFCR_CTEIF3_Pos     (25U)\n#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */\n#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk\n#define DMA_LIFCR_CDMEIF3_Pos    (24U)\n#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */\n#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk\n#define DMA_LIFCR_CFEIF3_Pos     (22U)\n#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */\n#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk\n#define DMA_LIFCR_CTCIF2_Pos     (21U)\n#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */\n#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk\n#define DMA_LIFCR_CHTIF2_Pos     (20U)\n#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */\n#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk\n#define DMA_LIFCR_CTEIF2_Pos     (19U)\n#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */\n#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk\n#define DMA_LIFCR_CDMEIF2_Pos    (18U)\n#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */\n#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk\n#define DMA_LIFCR_CFEIF2_Pos     (16U)\n#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */\n#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk\n#define DMA_LIFCR_CTCIF1_Pos     (11U)\n#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */\n#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk\n#define DMA_LIFCR_CHTIF1_Pos     (10U)\n#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */\n#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk\n#define DMA_LIFCR_CTEIF1_Pos     (9U)\n#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */\n#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk\n#define DMA_LIFCR_CDMEIF1_Pos    (8U)\n#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */\n#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk\n#define DMA_LIFCR_CFEIF1_Pos     (6U)\n#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */\n#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk\n#define DMA_LIFCR_CTCIF0_Pos     (5U)\n#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */\n#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk\n#define DMA_LIFCR_CHTIF0_Pos     (4U)\n#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */\n#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk\n#define DMA_LIFCR_CTEIF0_Pos     (3U)\n#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */\n#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk\n#define DMA_LIFCR_CDMEIF0_Pos    (2U)\n#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */\n#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk\n#define DMA_LIFCR_CFEIF0_Pos     (0U)\n#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */\n#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk\n\n/********************  Bits definition for DMA_HIFCR  register  ****************/\n#define DMA_HIFCR_CTCIF7_Pos     (27U)\n#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */\n#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk\n#define DMA_HIFCR_CHTIF7_Pos     (26U)\n#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */\n#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk\n#define DMA_HIFCR_CTEIF7_Pos     (25U)\n#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */\n#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk\n#define DMA_HIFCR_CDMEIF7_Pos    (24U)\n#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */\n#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk\n#define DMA_HIFCR_CFEIF7_Pos     (22U)\n#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */\n#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk\n#define DMA_HIFCR_CTCIF6_Pos     (21U)\n#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */\n#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk\n#define DMA_HIFCR_CHTIF6_Pos     (20U)\n#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */\n#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk\n#define DMA_HIFCR_CTEIF6_Pos     (19U)\n#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */\n#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk\n#define DMA_HIFCR_CDMEIF6_Pos    (18U)\n#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */\n#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk\n#define DMA_HIFCR_CFEIF6_Pos     (16U)\n#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */\n#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk\n#define DMA_HIFCR_CTCIF5_Pos     (11U)\n#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */\n#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk\n#define DMA_HIFCR_CHTIF5_Pos     (10U)\n#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */\n#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk\n#define DMA_HIFCR_CTEIF5_Pos     (9U)\n#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */\n#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk\n#define DMA_HIFCR_CDMEIF5_Pos    (8U)\n#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */\n#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk\n#define DMA_HIFCR_CFEIF5_Pos     (6U)\n#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */\n#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk\n#define DMA_HIFCR_CTCIF4_Pos     (5U)\n#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */\n#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk\n#define DMA_HIFCR_CHTIF4_Pos     (4U)\n#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */\n#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk\n#define DMA_HIFCR_CTEIF4_Pos     (3U)\n#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */\n#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk\n#define DMA_HIFCR_CDMEIF4_Pos    (2U)\n#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */\n#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk\n#define DMA_HIFCR_CFEIF4_Pos     (0U)\n#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */\n#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk\n\n/******************  Bit definition for DMA_SxPAR register  ********************/\n#define DMA_SxPAR_PA_Pos         (0U)\n#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */\n#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */\n\n/******************  Bit definition for DMA_SxM0AR register  ********************/\n#define DMA_SxM0AR_M0A_Pos       (0U)\n#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */\n\n/******************  Bit definition for DMA_SxM1AR register  ********************/\n#define DMA_SxM1AR_M1A_Pos       (0U)\n#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                    External Interrupt/Event Controller                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for EXTI_IMR register  *******************/\n#define EXTI_IMR_MR0_Pos          (0U)\n#define EXTI_IMR_MR0_Msk          (0x1UL << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */\n#define EXTI_IMR_MR1_Pos          (1U)\n#define EXTI_IMR_MR1_Msk          (0x1UL << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */\n#define EXTI_IMR_MR2_Pos          (2U)\n#define EXTI_IMR_MR2_Msk          (0x1UL << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */\n#define EXTI_IMR_MR3_Pos          (3U)\n#define EXTI_IMR_MR3_Msk          (0x1UL << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */\n#define EXTI_IMR_MR4_Pos          (4U)\n#define EXTI_IMR_MR4_Msk          (0x1UL << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */\n#define EXTI_IMR_MR5_Pos          (5U)\n#define EXTI_IMR_MR5_Msk          (0x1UL << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */\n#define EXTI_IMR_MR6_Pos          (6U)\n#define EXTI_IMR_MR6_Msk          (0x1UL << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */\n#define EXTI_IMR_MR7_Pos          (7U)\n#define EXTI_IMR_MR7_Msk          (0x1UL << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */\n#define EXTI_IMR_MR8_Pos          (8U)\n#define EXTI_IMR_MR8_Msk          (0x1UL << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */\n#define EXTI_IMR_MR9_Pos          (9U)\n#define EXTI_IMR_MR9_Msk          (0x1UL << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */\n#define EXTI_IMR_MR10_Pos         (10U)\n#define EXTI_IMR_MR10_Msk         (0x1UL << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */\n#define EXTI_IMR_MR11_Pos         (11U)\n#define EXTI_IMR_MR11_Msk         (0x1UL << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */\n#define EXTI_IMR_MR12_Pos         (12U)\n#define EXTI_IMR_MR12_Msk         (0x1UL << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */\n#define EXTI_IMR_MR13_Pos         (13U)\n#define EXTI_IMR_MR13_Msk         (0x1UL << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */\n#define EXTI_IMR_MR14_Pos         (14U)\n#define EXTI_IMR_MR14_Msk         (0x1UL << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */\n#define EXTI_IMR_MR15_Pos         (15U)\n#define EXTI_IMR_MR15_Msk         (0x1UL << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */\n#define EXTI_IMR_MR16_Pos         (16U)\n#define EXTI_IMR_MR16_Msk         (0x1UL << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */\n#define EXTI_IMR_MR17_Pos         (17U)\n#define EXTI_IMR_MR17_Msk         (0x1UL << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */\n#define EXTI_IMR_MR18_Pos         (18U)\n#define EXTI_IMR_MR18_Msk         (0x1UL << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */\n#define EXTI_IMR_MR19_Pos         (19U)\n#define EXTI_IMR_MR19_Msk         (0x1UL << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */\n#define EXTI_IMR_MR20_Pos         (20U)\n#define EXTI_IMR_MR20_Msk         (0x1UL << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */\n#define EXTI_IMR_MR21_Pos         (21U)\n#define EXTI_IMR_MR21_Msk         (0x1UL << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */\n#define EXTI_IMR_MR22_Pos         (22U)\n#define EXTI_IMR_MR22_Msk         (0x1UL << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */\n\n/* Reference Defines */\n#define  EXTI_IMR_IM0                        EXTI_IMR_MR0\n#define  EXTI_IMR_IM1                        EXTI_IMR_MR1\n#define  EXTI_IMR_IM2                        EXTI_IMR_MR2\n#define  EXTI_IMR_IM3                        EXTI_IMR_MR3\n#define  EXTI_IMR_IM4                        EXTI_IMR_MR4\n#define  EXTI_IMR_IM5                        EXTI_IMR_MR5\n#define  EXTI_IMR_IM6                        EXTI_IMR_MR6\n#define  EXTI_IMR_IM7                        EXTI_IMR_MR7\n#define  EXTI_IMR_IM8                        EXTI_IMR_MR8\n#define  EXTI_IMR_IM9                        EXTI_IMR_MR9\n#define  EXTI_IMR_IM10                       EXTI_IMR_MR10\n#define  EXTI_IMR_IM11                       EXTI_IMR_MR11\n#define  EXTI_IMR_IM12                       EXTI_IMR_MR12\n#define  EXTI_IMR_IM13                       EXTI_IMR_MR13\n#define  EXTI_IMR_IM14                       EXTI_IMR_MR14\n#define  EXTI_IMR_IM15                       EXTI_IMR_MR15\n#define  EXTI_IMR_IM16                       EXTI_IMR_MR16\n#define  EXTI_IMR_IM17                       EXTI_IMR_MR17\n#define  EXTI_IMR_IM18                       EXTI_IMR_MR18\n#define  EXTI_IMR_IM19                       EXTI_IMR_MR19\n#define  EXTI_IMR_IM20                       EXTI_IMR_MR20\n#define  EXTI_IMR_IM21                       EXTI_IMR_MR21\n#define  EXTI_IMR_IM22                       EXTI_IMR_MR22\n#define EXTI_IMR_IM_Pos           (0U)\n#define EXTI_IMR_IM_Msk           (0x7FFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x007FFFFF */\n#define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */\n\n/*******************  Bit definition for EXTI_EMR register  *******************/\n#define EXTI_EMR_MR0_Pos          (0U)\n#define EXTI_EMR_MR0_Msk          (0x1UL << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */\n#define EXTI_EMR_MR1_Pos          (1U)\n#define EXTI_EMR_MR1_Msk          (0x1UL << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */\n#define EXTI_EMR_MR2_Pos          (2U)\n#define EXTI_EMR_MR2_Msk          (0x1UL << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */\n#define EXTI_EMR_MR3_Pos          (3U)\n#define EXTI_EMR_MR3_Msk          (0x1UL << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */\n#define EXTI_EMR_MR4_Pos          (4U)\n#define EXTI_EMR_MR4_Msk          (0x1UL << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */\n#define EXTI_EMR_MR5_Pos          (5U)\n#define EXTI_EMR_MR5_Msk          (0x1UL << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */\n#define EXTI_EMR_MR6_Pos          (6U)\n#define EXTI_EMR_MR6_Msk          (0x1UL << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */\n#define EXTI_EMR_MR7_Pos          (7U)\n#define EXTI_EMR_MR7_Msk          (0x1UL << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */\n#define EXTI_EMR_MR8_Pos          (8U)\n#define EXTI_EMR_MR8_Msk          (0x1UL << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */\n#define EXTI_EMR_MR9_Pos          (9U)\n#define EXTI_EMR_MR9_Msk          (0x1UL << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */\n#define EXTI_EMR_MR10_Pos         (10U)\n#define EXTI_EMR_MR10_Msk         (0x1UL << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */\n#define EXTI_EMR_MR11_Pos         (11U)\n#define EXTI_EMR_MR11_Msk         (0x1UL << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */\n#define EXTI_EMR_MR12_Pos         (12U)\n#define EXTI_EMR_MR12_Msk         (0x1UL << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */\n#define EXTI_EMR_MR13_Pos         (13U)\n#define EXTI_EMR_MR13_Msk         (0x1UL << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */\n#define EXTI_EMR_MR14_Pos         (14U)\n#define EXTI_EMR_MR14_Msk         (0x1UL << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */\n#define EXTI_EMR_MR15_Pos         (15U)\n#define EXTI_EMR_MR15_Msk         (0x1UL << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */\n#define EXTI_EMR_MR16_Pos         (16U)\n#define EXTI_EMR_MR16_Msk         (0x1UL << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */\n#define EXTI_EMR_MR17_Pos         (17U)\n#define EXTI_EMR_MR17_Msk         (0x1UL << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */\n#define EXTI_EMR_MR18_Pos         (18U)\n#define EXTI_EMR_MR18_Msk         (0x1UL << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */\n#define EXTI_EMR_MR19_Pos         (19U)\n#define EXTI_EMR_MR19_Msk         (0x1UL << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */\n#define EXTI_EMR_MR20_Pos         (20U)\n#define EXTI_EMR_MR20_Msk         (0x1UL << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */\n#define EXTI_EMR_MR21_Pos         (21U)\n#define EXTI_EMR_MR21_Msk         (0x1UL << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */\n#define EXTI_EMR_MR22_Pos         (22U)\n#define EXTI_EMR_MR22_Msk         (0x1UL << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */\n\n/* Reference Defines */\n#define  EXTI_EMR_EM0                        EXTI_EMR_MR0\n#define  EXTI_EMR_EM1                        EXTI_EMR_MR1\n#define  EXTI_EMR_EM2                        EXTI_EMR_MR2\n#define  EXTI_EMR_EM3                        EXTI_EMR_MR3\n#define  EXTI_EMR_EM4                        EXTI_EMR_MR4\n#define  EXTI_EMR_EM5                        EXTI_EMR_MR5\n#define  EXTI_EMR_EM6                        EXTI_EMR_MR6\n#define  EXTI_EMR_EM7                        EXTI_EMR_MR7\n#define  EXTI_EMR_EM8                        EXTI_EMR_MR8\n#define  EXTI_EMR_EM9                        EXTI_EMR_MR9\n#define  EXTI_EMR_EM10                       EXTI_EMR_MR10\n#define  EXTI_EMR_EM11                       EXTI_EMR_MR11\n#define  EXTI_EMR_EM12                       EXTI_EMR_MR12\n#define  EXTI_EMR_EM13                       EXTI_EMR_MR13\n#define  EXTI_EMR_EM14                       EXTI_EMR_MR14\n#define  EXTI_EMR_EM15                       EXTI_EMR_MR15\n#define  EXTI_EMR_EM16                       EXTI_EMR_MR16\n#define  EXTI_EMR_EM17                       EXTI_EMR_MR17\n#define  EXTI_EMR_EM18                       EXTI_EMR_MR18\n#define  EXTI_EMR_EM19                       EXTI_EMR_MR19\n#define  EXTI_EMR_EM20                       EXTI_EMR_MR20\n#define  EXTI_EMR_EM21                       EXTI_EMR_MR21\n#define  EXTI_EMR_EM22                       EXTI_EMR_MR22\n\n/******************  Bit definition for EXTI_RTSR register  *******************/\n#define EXTI_RTSR_TR0_Pos         (0U)\n#define EXTI_RTSR_TR0_Msk         (0x1UL << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */\n#define EXTI_RTSR_TR1_Pos         (1U)\n#define EXTI_RTSR_TR1_Msk         (0x1UL << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */\n#define EXTI_RTSR_TR2_Pos         (2U)\n#define EXTI_RTSR_TR2_Msk         (0x1UL << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */\n#define EXTI_RTSR_TR3_Pos         (3U)\n#define EXTI_RTSR_TR3_Msk         (0x1UL << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */\n#define EXTI_RTSR_TR4_Pos         (4U)\n#define EXTI_RTSR_TR4_Msk         (0x1UL << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */\n#define EXTI_RTSR_TR5_Pos         (5U)\n#define EXTI_RTSR_TR5_Msk         (0x1UL << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */\n#define EXTI_RTSR_TR6_Pos         (6U)\n#define EXTI_RTSR_TR6_Msk         (0x1UL << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */\n#define EXTI_RTSR_TR7_Pos         (7U)\n#define EXTI_RTSR_TR7_Msk         (0x1UL << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */\n#define EXTI_RTSR_TR8_Pos         (8U)\n#define EXTI_RTSR_TR8_Msk         (0x1UL << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */\n#define EXTI_RTSR_TR9_Pos         (9U)\n#define EXTI_RTSR_TR9_Msk         (0x1UL << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */\n#define EXTI_RTSR_TR10_Pos        (10U)\n#define EXTI_RTSR_TR10_Msk        (0x1UL << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */\n#define EXTI_RTSR_TR11_Pos        (11U)\n#define EXTI_RTSR_TR11_Msk        (0x1UL << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */\n#define EXTI_RTSR_TR12_Pos        (12U)\n#define EXTI_RTSR_TR12_Msk        (0x1UL << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */\n#define EXTI_RTSR_TR13_Pos        (13U)\n#define EXTI_RTSR_TR13_Msk        (0x1UL << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */\n#define EXTI_RTSR_TR14_Pos        (14U)\n#define EXTI_RTSR_TR14_Msk        (0x1UL << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */\n#define EXTI_RTSR_TR15_Pos        (15U)\n#define EXTI_RTSR_TR15_Msk        (0x1UL << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */\n#define EXTI_RTSR_TR16_Pos        (16U)\n#define EXTI_RTSR_TR16_Msk        (0x1UL << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */\n#define EXTI_RTSR_TR17_Pos        (17U)\n#define EXTI_RTSR_TR17_Msk        (0x1UL << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */\n#define EXTI_RTSR_TR18_Pos        (18U)\n#define EXTI_RTSR_TR18_Msk        (0x1UL << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */\n#define EXTI_RTSR_TR19_Pos        (19U)\n#define EXTI_RTSR_TR19_Msk        (0x1UL << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */\n#define EXTI_RTSR_TR20_Pos        (20U)\n#define EXTI_RTSR_TR20_Msk        (0x1UL << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */\n#define EXTI_RTSR_TR21_Pos        (21U)\n#define EXTI_RTSR_TR21_Msk        (0x1UL << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */\n#define EXTI_RTSR_TR22_Pos        (22U)\n#define EXTI_RTSR_TR22_Msk        (0x1UL << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_FTSR register  *******************/\n#define EXTI_FTSR_TR0_Pos         (0U)\n#define EXTI_FTSR_TR0_Msk         (0x1UL << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */\n#define EXTI_FTSR_TR1_Pos         (1U)\n#define EXTI_FTSR_TR1_Msk         (0x1UL << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */\n#define EXTI_FTSR_TR2_Pos         (2U)\n#define EXTI_FTSR_TR2_Msk         (0x1UL << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */\n#define EXTI_FTSR_TR3_Pos         (3U)\n#define EXTI_FTSR_TR3_Msk         (0x1UL << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */\n#define EXTI_FTSR_TR4_Pos         (4U)\n#define EXTI_FTSR_TR4_Msk         (0x1UL << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */\n#define EXTI_FTSR_TR5_Pos         (5U)\n#define EXTI_FTSR_TR5_Msk         (0x1UL << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */\n#define EXTI_FTSR_TR6_Pos         (6U)\n#define EXTI_FTSR_TR6_Msk         (0x1UL << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */\n#define EXTI_FTSR_TR7_Pos         (7U)\n#define EXTI_FTSR_TR7_Msk         (0x1UL << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */\n#define EXTI_FTSR_TR8_Pos         (8U)\n#define EXTI_FTSR_TR8_Msk         (0x1UL << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */\n#define EXTI_FTSR_TR9_Pos         (9U)\n#define EXTI_FTSR_TR9_Msk         (0x1UL << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */\n#define EXTI_FTSR_TR10_Pos        (10U)\n#define EXTI_FTSR_TR10_Msk        (0x1UL << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */\n#define EXTI_FTSR_TR11_Pos        (11U)\n#define EXTI_FTSR_TR11_Msk        (0x1UL << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */\n#define EXTI_FTSR_TR12_Pos        (12U)\n#define EXTI_FTSR_TR12_Msk        (0x1UL << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */\n#define EXTI_FTSR_TR13_Pos        (13U)\n#define EXTI_FTSR_TR13_Msk        (0x1UL << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */\n#define EXTI_FTSR_TR14_Pos        (14U)\n#define EXTI_FTSR_TR14_Msk        (0x1UL << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */\n#define EXTI_FTSR_TR15_Pos        (15U)\n#define EXTI_FTSR_TR15_Msk        (0x1UL << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */\n#define EXTI_FTSR_TR16_Pos        (16U)\n#define EXTI_FTSR_TR16_Msk        (0x1UL << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */\n#define EXTI_FTSR_TR17_Pos        (17U)\n#define EXTI_FTSR_TR17_Msk        (0x1UL << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */\n#define EXTI_FTSR_TR18_Pos        (18U)\n#define EXTI_FTSR_TR18_Msk        (0x1UL << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */\n#define EXTI_FTSR_TR19_Pos        (19U)\n#define EXTI_FTSR_TR19_Msk        (0x1UL << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */\n#define EXTI_FTSR_TR20_Pos        (20U)\n#define EXTI_FTSR_TR20_Msk        (0x1UL << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */\n#define EXTI_FTSR_TR21_Pos        (21U)\n#define EXTI_FTSR_TR21_Msk        (0x1UL << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */\n#define EXTI_FTSR_TR22_Pos        (22U)\n#define EXTI_FTSR_TR22_Msk        (0x1UL << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_SWIER register  ******************/\n#define EXTI_SWIER_SWIER0_Pos     (0U)\n#define EXTI_SWIER_SWIER0_Msk     (0x1UL << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */\n#define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */\n#define EXTI_SWIER_SWIER1_Pos     (1U)\n#define EXTI_SWIER_SWIER1_Msk     (0x1UL << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */\n#define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */\n#define EXTI_SWIER_SWIER2_Pos     (2U)\n#define EXTI_SWIER_SWIER2_Msk     (0x1UL << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */\n#define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */\n#define EXTI_SWIER_SWIER3_Pos     (3U)\n#define EXTI_SWIER_SWIER3_Msk     (0x1UL << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */\n#define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */\n#define EXTI_SWIER_SWIER4_Pos     (4U)\n#define EXTI_SWIER_SWIER4_Msk     (0x1UL << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */\n#define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */\n#define EXTI_SWIER_SWIER5_Pos     (5U)\n#define EXTI_SWIER_SWIER5_Msk     (0x1UL << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */\n#define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */\n#define EXTI_SWIER_SWIER6_Pos     (6U)\n#define EXTI_SWIER_SWIER6_Msk     (0x1UL << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */\n#define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */\n#define EXTI_SWIER_SWIER7_Pos     (7U)\n#define EXTI_SWIER_SWIER7_Msk     (0x1UL << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */\n#define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */\n#define EXTI_SWIER_SWIER8_Pos     (8U)\n#define EXTI_SWIER_SWIER8_Msk     (0x1UL << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */\n#define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */\n#define EXTI_SWIER_SWIER9_Pos     (9U)\n#define EXTI_SWIER_SWIER9_Msk     (0x1UL << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */\n#define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */\n#define EXTI_SWIER_SWIER10_Pos    (10U)\n#define EXTI_SWIER_SWIER10_Msk    (0x1UL << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */\n#define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */\n#define EXTI_SWIER_SWIER11_Pos    (11U)\n#define EXTI_SWIER_SWIER11_Msk    (0x1UL << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */\n#define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */\n#define EXTI_SWIER_SWIER12_Pos    (12U)\n#define EXTI_SWIER_SWIER12_Msk    (0x1UL << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */\n#define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */\n#define EXTI_SWIER_SWIER13_Pos    (13U)\n#define EXTI_SWIER_SWIER13_Msk    (0x1UL << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */\n#define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */\n#define EXTI_SWIER_SWIER14_Pos    (14U)\n#define EXTI_SWIER_SWIER14_Msk    (0x1UL << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */\n#define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */\n#define EXTI_SWIER_SWIER15_Pos    (15U)\n#define EXTI_SWIER_SWIER15_Msk    (0x1UL << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */\n#define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */\n#define EXTI_SWIER_SWIER16_Pos    (16U)\n#define EXTI_SWIER_SWIER16_Msk    (0x1UL << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */\n#define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */\n#define EXTI_SWIER_SWIER17_Pos    (17U)\n#define EXTI_SWIER_SWIER17_Msk    (0x1UL << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */\n#define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */\n#define EXTI_SWIER_SWIER18_Pos    (18U)\n#define EXTI_SWIER_SWIER18_Msk    (0x1UL << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */\n#define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */\n#define EXTI_SWIER_SWIER19_Pos    (19U)\n#define EXTI_SWIER_SWIER19_Msk    (0x1UL << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */\n#define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */\n#define EXTI_SWIER_SWIER20_Pos    (20U)\n#define EXTI_SWIER_SWIER20_Msk    (0x1UL << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */\n#define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */\n#define EXTI_SWIER_SWIER21_Pos    (21U)\n#define EXTI_SWIER_SWIER21_Msk    (0x1UL << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */\n#define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */\n#define EXTI_SWIER_SWIER22_Pos    (22U)\n#define EXTI_SWIER_SWIER22_Msk    (0x1UL << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */\n#define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */\n\n/*******************  Bit definition for EXTI_PR register  ********************/\n#define EXTI_PR_PR0_Pos           (0U)\n#define EXTI_PR_PR0_Msk           (0x1UL << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */\n#define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */\n#define EXTI_PR_PR1_Pos           (1U)\n#define EXTI_PR_PR1_Msk           (0x1UL << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */\n#define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */\n#define EXTI_PR_PR2_Pos           (2U)\n#define EXTI_PR_PR2_Msk           (0x1UL << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */\n#define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */\n#define EXTI_PR_PR3_Pos           (3U)\n#define EXTI_PR_PR3_Msk           (0x1UL << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */\n#define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */\n#define EXTI_PR_PR4_Pos           (4U)\n#define EXTI_PR_PR4_Msk           (0x1UL << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */\n#define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */\n#define EXTI_PR_PR5_Pos           (5U)\n#define EXTI_PR_PR5_Msk           (0x1UL << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */\n#define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */\n#define EXTI_PR_PR6_Pos           (6U)\n#define EXTI_PR_PR6_Msk           (0x1UL << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */\n#define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */\n#define EXTI_PR_PR7_Pos           (7U)\n#define EXTI_PR_PR7_Msk           (0x1UL << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */\n#define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */\n#define EXTI_PR_PR8_Pos           (8U)\n#define EXTI_PR_PR8_Msk           (0x1UL << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */\n#define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */\n#define EXTI_PR_PR9_Pos           (9U)\n#define EXTI_PR_PR9_Msk           (0x1UL << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */\n#define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */\n#define EXTI_PR_PR10_Pos          (10U)\n#define EXTI_PR_PR10_Msk          (0x1UL << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */\n#define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */\n#define EXTI_PR_PR11_Pos          (11U)\n#define EXTI_PR_PR11_Msk          (0x1UL << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */\n#define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */\n#define EXTI_PR_PR12_Pos          (12U)\n#define EXTI_PR_PR12_Msk          (0x1UL << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */\n#define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */\n#define EXTI_PR_PR13_Pos          (13U)\n#define EXTI_PR_PR13_Msk          (0x1UL << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */\n#define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */\n#define EXTI_PR_PR14_Pos          (14U)\n#define EXTI_PR_PR14_Msk          (0x1UL << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */\n#define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */\n#define EXTI_PR_PR15_Pos          (15U)\n#define EXTI_PR_PR15_Msk          (0x1UL << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */\n#define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */\n#define EXTI_PR_PR16_Pos          (16U)\n#define EXTI_PR_PR16_Msk          (0x1UL << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */\n#define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */\n#define EXTI_PR_PR17_Pos          (17U)\n#define EXTI_PR_PR17_Msk          (0x1UL << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */\n#define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */\n#define EXTI_PR_PR18_Pos          (18U)\n#define EXTI_PR_PR18_Msk          (0x1UL << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */\n#define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */\n#define EXTI_PR_PR19_Pos          (19U)\n#define EXTI_PR_PR19_Msk          (0x1UL << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */\n#define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */\n#define EXTI_PR_PR20_Pos          (20U)\n#define EXTI_PR_PR20_Msk          (0x1UL << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */\n#define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */\n#define EXTI_PR_PR21_Pos          (21U)\n#define EXTI_PR_PR21_Msk          (0x1UL << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */\n#define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */\n#define EXTI_PR_PR22_Pos          (22U)\n#define EXTI_PR_PR22_Msk          (0x1UL << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */\n#define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    FLASH                                   */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bits definition for FLASH_ACR register  *****************/\n#define FLASH_ACR_LATENCY_Pos          (0U)\n#define FLASH_ACR_LATENCY_Msk          (0xFUL << FLASH_ACR_LATENCY_Pos)         /*!< 0x0000000F */\n#define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk\n#define FLASH_ACR_LATENCY_0WS          0x00000000U\n#define FLASH_ACR_LATENCY_1WS          0x00000001U\n#define FLASH_ACR_LATENCY_2WS          0x00000002U\n#define FLASH_ACR_LATENCY_3WS          0x00000003U\n#define FLASH_ACR_LATENCY_4WS          0x00000004U\n#define FLASH_ACR_LATENCY_5WS          0x00000005U\n#define FLASH_ACR_LATENCY_6WS          0x00000006U\n#define FLASH_ACR_LATENCY_7WS          0x00000007U\n\n#define FLASH_ACR_PRFTEN_Pos           (8U)\n#define FLASH_ACR_PRFTEN_Msk           (0x1UL << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */\n#define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk\n#define FLASH_ACR_ICEN_Pos             (9U)\n#define FLASH_ACR_ICEN_Msk             (0x1UL << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */\n#define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk\n#define FLASH_ACR_DCEN_Pos             (10U)\n#define FLASH_ACR_DCEN_Msk             (0x1UL << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */\n#define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk\n#define FLASH_ACR_ICRST_Pos            (11U)\n#define FLASH_ACR_ICRST_Msk            (0x1UL << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */\n#define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk\n#define FLASH_ACR_DCRST_Pos            (12U)\n#define FLASH_ACR_DCRST_Msk            (0x1UL << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */\n#define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk\n#define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)\n#define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */\n#define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk\n#define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)\n#define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */\n#define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk\n\n/*******************  Bits definition for FLASH_SR register  ******************/\n#define FLASH_SR_EOP_Pos               (0U)\n#define FLASH_SR_EOP_Msk               (0x1UL << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */\n#define FLASH_SR_EOP                   FLASH_SR_EOP_Msk\n#define FLASH_SR_SOP_Pos               (1U)\n#define FLASH_SR_SOP_Msk               (0x1UL << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */\n#define FLASH_SR_SOP                   FLASH_SR_SOP_Msk\n#define FLASH_SR_WRPERR_Pos            (4U)\n#define FLASH_SR_WRPERR_Msk            (0x1UL << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */\n#define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk\n#define FLASH_SR_PGAERR_Pos            (5U)\n#define FLASH_SR_PGAERR_Msk            (0x1UL << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */\n#define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk\n#define FLASH_SR_PGPERR_Pos            (6U)\n#define FLASH_SR_PGPERR_Msk            (0x1UL << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */\n#define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk\n#define FLASH_SR_PGSERR_Pos            (7U)\n#define FLASH_SR_PGSERR_Msk            (0x1UL << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */\n#define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk\n#define FLASH_SR_RDERR_Pos            (8U)\n#define FLASH_SR_RDERR_Msk            (0x1UL << FLASH_SR_RDERR_Pos)             /*!< 0x00000100 */\n#define FLASH_SR_RDERR                FLASH_SR_RDERR_Msk\n#define FLASH_SR_BSY_Pos               (16U)\n#define FLASH_SR_BSY_Msk               (0x1UL << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */\n#define FLASH_SR_BSY                   FLASH_SR_BSY_Msk\n\n/*******************  Bits definition for FLASH_CR register  ******************/\n#define FLASH_CR_PG_Pos                (0U)\n#define FLASH_CR_PG_Msk                (0x1UL << FLASH_CR_PG_Pos)               /*!< 0x00000001 */\n#define FLASH_CR_PG                    FLASH_CR_PG_Msk\n#define FLASH_CR_SER_Pos               (1U)\n#define FLASH_CR_SER_Msk               (0x1UL << FLASH_CR_SER_Pos)              /*!< 0x00000002 */\n#define FLASH_CR_SER                   FLASH_CR_SER_Msk\n#define FLASH_CR_MER_Pos               (2U)\n#define FLASH_CR_MER_Msk               (0x1UL << FLASH_CR_MER_Pos)              /*!< 0x00000004 */\n#define FLASH_CR_MER                   FLASH_CR_MER_Msk\n#define FLASH_CR_SNB_Pos               (3U)\n#define FLASH_CR_SNB_Msk               (0x1FUL << FLASH_CR_SNB_Pos)             /*!< 0x000000F8 */\n#define FLASH_CR_SNB                   FLASH_CR_SNB_Msk\n#define FLASH_CR_SNB_0                 (0x01UL << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */\n#define FLASH_CR_SNB_1                 (0x02UL << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */\n#define FLASH_CR_SNB_2                 (0x04UL << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */\n#define FLASH_CR_SNB_3                 (0x08UL << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */\n#define FLASH_CR_SNB_4                 (0x10UL << FLASH_CR_SNB_Pos)             /*!< 0x00000080 */\n#define FLASH_CR_PSIZE_Pos             (8U)\n#define FLASH_CR_PSIZE_Msk             (0x3UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */\n#define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk\n#define FLASH_CR_PSIZE_0               (0x1UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */\n#define FLASH_CR_PSIZE_1               (0x2UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */\n#define FLASH_CR_STRT_Pos              (16U)\n#define FLASH_CR_STRT_Msk              (0x1UL << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */\n#define FLASH_CR_STRT                  FLASH_CR_STRT_Msk\n#define FLASH_CR_EOPIE_Pos             (24U)\n#define FLASH_CR_EOPIE_Msk             (0x1UL << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */\n#define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk\n#define FLASH_CR_LOCK_Pos              (31U)\n#define FLASH_CR_LOCK_Msk              (0x1UL << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */\n#define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk\n\n/*******************  Bits definition for FLASH_OPTCR register  ***************/\n#define FLASH_OPTCR_OPTLOCK_Pos        (0U)\n#define FLASH_OPTCR_OPTLOCK_Msk        (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */\n#define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk\n#define FLASH_OPTCR_OPTSTRT_Pos        (1U)\n#define FLASH_OPTCR_OPTSTRT_Msk        (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */\n#define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk\n\n#define FLASH_OPTCR_BOR_LEV_0          0x00000004U\n#define FLASH_OPTCR_BOR_LEV_1          0x00000008U\n#define FLASH_OPTCR_BOR_LEV_Pos        (2U)\n#define FLASH_OPTCR_BOR_LEV_Msk        (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */\n#define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk\n#define FLASH_OPTCR_WDG_SW_Pos         (5U)\n#define FLASH_OPTCR_WDG_SW_Msk         (0x1UL << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */\n#define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk\n#define FLASH_OPTCR_nRST_STOP_Pos      (6U)\n#define FLASH_OPTCR_nRST_STOP_Msk      (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */\n#define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk\n#define FLASH_OPTCR_nRST_STDBY_Pos     (7U)\n#define FLASH_OPTCR_nRST_STDBY_Msk     (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */\n#define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk\n#define FLASH_OPTCR_RDP_Pos            (8U)\n#define FLASH_OPTCR_RDP_Msk            (0xFFUL << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */\n#define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk\n#define FLASH_OPTCR_RDP_0              (0x01UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */\n#define FLASH_OPTCR_RDP_1              (0x02UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */\n#define FLASH_OPTCR_RDP_2              (0x04UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */\n#define FLASH_OPTCR_RDP_3              (0x08UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */\n#define FLASH_OPTCR_RDP_4              (0x10UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */\n#define FLASH_OPTCR_RDP_5              (0x20UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */\n#define FLASH_OPTCR_RDP_6              (0x40UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */\n#define FLASH_OPTCR_RDP_7              (0x80UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */\n#define FLASH_OPTCR_nWRP_Pos           (16U)\n#define FLASH_OPTCR_nWRP_Msk           (0xFFFUL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x0FFF0000 */\n#define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk\n#define FLASH_OPTCR_nWRP_0             0x00010000U\n#define FLASH_OPTCR_nWRP_1             0x00020000U\n#define FLASH_OPTCR_nWRP_2             0x00040000U\n#define FLASH_OPTCR_nWRP_3             0x00080000U\n#define FLASH_OPTCR_nWRP_4             0x00100000U\n#define FLASH_OPTCR_nWRP_5             0x00200000U\n#define FLASH_OPTCR_nWRP_6             0x00400000U\n#define FLASH_OPTCR_nWRP_7             0x00800000U\n#define FLASH_OPTCR_nWRP_8             0x01000000U\n#define FLASH_OPTCR_nWRP_9             0x02000000U\n#define FLASH_OPTCR_nWRP_10            0x04000000U\n#define FLASH_OPTCR_nWRP_11            0x08000000U\n\n/******************  Bits definition for FLASH_OPTCR1 register  ***************/\n#define FLASH_OPTCR1_nWRP_Pos          (16U)\n#define FLASH_OPTCR1_nWRP_Msk          (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */\n#define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk\n#define FLASH_OPTCR1_nWRP_0            (0x001UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */\n#define FLASH_OPTCR1_nWRP_1            (0x002UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */\n#define FLASH_OPTCR1_nWRP_2            (0x004UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */\n#define FLASH_OPTCR1_nWRP_3            (0x008UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */\n#define FLASH_OPTCR1_nWRP_4            (0x010UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */\n#define FLASH_OPTCR1_nWRP_5            (0x020UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */\n#define FLASH_OPTCR1_nWRP_6            (0x040UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */\n#define FLASH_OPTCR1_nWRP_7            (0x080UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */\n#define FLASH_OPTCR1_nWRP_8            (0x100UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */\n#define FLASH_OPTCR1_nWRP_9            (0x200UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */\n#define FLASH_OPTCR1_nWRP_10           (0x400UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */\n#define FLASH_OPTCR1_nWRP_11           (0x800UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            General Purpose I/O                             */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bits definition for GPIO_MODER register  *****************/\n#define GPIO_MODER_MODER0_Pos            (0U)\n#define GPIO_MODER_MODER0_Msk            (0x3UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */\n#define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk\n#define GPIO_MODER_MODER0_0              (0x1UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */\n#define GPIO_MODER_MODER0_1              (0x2UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */\n#define GPIO_MODER_MODER1_Pos            (2U)\n#define GPIO_MODER_MODER1_Msk            (0x3UL << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */\n#define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk\n#define GPIO_MODER_MODER1_0              (0x1UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */\n#define GPIO_MODER_MODER1_1              (0x2UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */\n#define GPIO_MODER_MODER2_Pos            (4U)\n#define GPIO_MODER_MODER2_Msk            (0x3UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */\n#define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk\n#define GPIO_MODER_MODER2_0              (0x1UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */\n#define GPIO_MODER_MODER2_1              (0x2UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */\n#define GPIO_MODER_MODER3_Pos            (6U)\n#define GPIO_MODER_MODER3_Msk            (0x3UL << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */\n#define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk\n#define GPIO_MODER_MODER3_0              (0x1UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */\n#define GPIO_MODER_MODER3_1              (0x2UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */\n#define GPIO_MODER_MODER4_Pos            (8U)\n#define GPIO_MODER_MODER4_Msk            (0x3UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */\n#define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk\n#define GPIO_MODER_MODER4_0              (0x1UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */\n#define GPIO_MODER_MODER4_1              (0x2UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */\n#define GPIO_MODER_MODER5_Pos            (10U)\n#define GPIO_MODER_MODER5_Msk            (0x3UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */\n#define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk\n#define GPIO_MODER_MODER5_0              (0x1UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */\n#define GPIO_MODER_MODER5_1              (0x2UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */\n#define GPIO_MODER_MODER6_Pos            (12U)\n#define GPIO_MODER_MODER6_Msk            (0x3UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */\n#define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk\n#define GPIO_MODER_MODER6_0              (0x1UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */\n#define GPIO_MODER_MODER6_1              (0x2UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */\n#define GPIO_MODER_MODER7_Pos            (14U)\n#define GPIO_MODER_MODER7_Msk            (0x3UL << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */\n#define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk\n#define GPIO_MODER_MODER7_0              (0x1UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */\n#define GPIO_MODER_MODER7_1              (0x2UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */\n#define GPIO_MODER_MODER8_Pos            (16U)\n#define GPIO_MODER_MODER8_Msk            (0x3UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */\n#define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk\n#define GPIO_MODER_MODER8_0              (0x1UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */\n#define GPIO_MODER_MODER8_1              (0x2UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */\n#define GPIO_MODER_MODER9_Pos            (18U)\n#define GPIO_MODER_MODER9_Msk            (0x3UL << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */\n#define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk\n#define GPIO_MODER_MODER9_0              (0x1UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */\n#define GPIO_MODER_MODER9_1              (0x2UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */\n#define GPIO_MODER_MODER10_Pos           (20U)\n#define GPIO_MODER_MODER10_Msk           (0x3UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */\n#define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk\n#define GPIO_MODER_MODER10_0             (0x1UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */\n#define GPIO_MODER_MODER10_1             (0x2UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */\n#define GPIO_MODER_MODER11_Pos           (22U)\n#define GPIO_MODER_MODER11_Msk           (0x3UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */\n#define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk\n#define GPIO_MODER_MODER11_0             (0x1UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */\n#define GPIO_MODER_MODER11_1             (0x2UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */\n#define GPIO_MODER_MODER12_Pos           (24U)\n#define GPIO_MODER_MODER12_Msk           (0x3UL << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */\n#define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk\n#define GPIO_MODER_MODER12_0             (0x1UL << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */\n#define GPIO_MODER_MODER12_1             (0x2UL << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */\n#define GPIO_MODER_MODER13_Pos           (26U)\n#define GPIO_MODER_MODER13_Msk           (0x3UL << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */\n#define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk\n#define GPIO_MODER_MODER13_0             (0x1UL << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */\n#define GPIO_MODER_MODER13_1             (0x2UL << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */\n#define GPIO_MODER_MODER14_Pos           (28U)\n#define GPIO_MODER_MODER14_Msk           (0x3UL << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */\n#define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk\n#define GPIO_MODER_MODER14_0             (0x1UL << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */\n#define GPIO_MODER_MODER14_1             (0x2UL << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */\n#define GPIO_MODER_MODER15_Pos           (30U)\n#define GPIO_MODER_MODER15_Msk           (0x3UL << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */\n#define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk\n#define GPIO_MODER_MODER15_0             (0x1UL << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */\n#define GPIO_MODER_MODER15_1             (0x2UL << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_MODER_MODE0_Pos             GPIO_MODER_MODER0_Pos\n#define GPIO_MODER_MODE0_Msk             GPIO_MODER_MODER0_Msk\n#define GPIO_MODER_MODE0                 GPIO_MODER_MODER0\n#define GPIO_MODER_MODE0_0               GPIO_MODER_MODER0_0\n#define GPIO_MODER_MODE0_1               GPIO_MODER_MODER0_1\n#define GPIO_MODER_MODE1_Pos             GPIO_MODER_MODER1_Pos\n#define GPIO_MODER_MODE1_Msk             GPIO_MODER_MODER1_Msk\n#define GPIO_MODER_MODE1                 GPIO_MODER_MODER1\n#define GPIO_MODER_MODE1_0               GPIO_MODER_MODER1_0\n#define GPIO_MODER_MODE1_1               GPIO_MODER_MODER1_1\n#define GPIO_MODER_MODE2_Pos             GPIO_MODER_MODER2_Pos\n#define GPIO_MODER_MODE2_Msk             GPIO_MODER_MODER2_Msk\n#define GPIO_MODER_MODE2                 GPIO_MODER_MODER2\n#define GPIO_MODER_MODE2_0               GPIO_MODER_MODER2_0\n#define GPIO_MODER_MODE2_1               GPIO_MODER_MODER2_1\n#define GPIO_MODER_MODE3_Pos             GPIO_MODER_MODER3_Pos\n#define GPIO_MODER_MODE3_Msk             GPIO_MODER_MODER3_Msk\n#define GPIO_MODER_MODE3                 GPIO_MODER_MODER3\n#define GPIO_MODER_MODE3_0               GPIO_MODER_MODER3_0\n#define GPIO_MODER_MODE3_1               GPIO_MODER_MODER3_1\n#define GPIO_MODER_MODE4_Pos             GPIO_MODER_MODER4_Pos\n#define GPIO_MODER_MODE4_Msk             GPIO_MODER_MODER4_Msk\n#define GPIO_MODER_MODE4                 GPIO_MODER_MODER4\n#define GPIO_MODER_MODE4_0               GPIO_MODER_MODER4_0\n#define GPIO_MODER_MODE4_1               GPIO_MODER_MODER4_1\n#define GPIO_MODER_MODE5_Pos             GPIO_MODER_MODER5_Pos\n#define GPIO_MODER_MODE5_Msk             GPIO_MODER_MODER5_Msk\n#define GPIO_MODER_MODE5                 GPIO_MODER_MODER5\n#define GPIO_MODER_MODE5_0               GPIO_MODER_MODER5_0\n#define GPIO_MODER_MODE5_1               GPIO_MODER_MODER5_1\n#define GPIO_MODER_MODE6_Pos             GPIO_MODER_MODER6_Pos\n#define GPIO_MODER_MODE6_Msk             GPIO_MODER_MODER6_Msk\n#define GPIO_MODER_MODE6                 GPIO_MODER_MODER6\n#define GPIO_MODER_MODE6_0               GPIO_MODER_MODER6_0\n#define GPIO_MODER_MODE6_1               GPIO_MODER_MODER6_1\n#define GPIO_MODER_MODE7_Pos             GPIO_MODER_MODER7_Pos\n#define GPIO_MODER_MODE7_Msk             GPIO_MODER_MODER7_Msk\n#define GPIO_MODER_MODE7                 GPIO_MODER_MODER7\n#define GPIO_MODER_MODE7_0               GPIO_MODER_MODER7_0\n#define GPIO_MODER_MODE7_1               GPIO_MODER_MODER7_1\n#define GPIO_MODER_MODE8_Pos             GPIO_MODER_MODER8_Pos\n#define GPIO_MODER_MODE8_Msk             GPIO_MODER_MODER2_Msk\n#define GPIO_MODER_MODE8                 GPIO_MODER_MODER8\n#define GPIO_MODER_MODE8_0               GPIO_MODER_MODER8_0\n#define GPIO_MODER_MODE8_1               GPIO_MODER_MODER8_1\n#define GPIO_MODER_MODE9_Pos             GPIO_MODER_MODER9_Pos\n#define GPIO_MODER_MODE9_Msk             GPIO_MODER_MODER9_Msk\n#define GPIO_MODER_MODE9                 GPIO_MODER_MODER9\n#define GPIO_MODER_MODE9_0               GPIO_MODER_MODER9_0\n#define GPIO_MODER_MODE9_1               GPIO_MODER_MODER9_1\n#define GPIO_MODER_MODE10_Pos            GPIO_MODER_MODER10_Pos\n#define GPIO_MODER_MODE10_Msk            GPIO_MODER_MODER10_Msk\n#define GPIO_MODER_MODE10                GPIO_MODER_MODER10\n#define GPIO_MODER_MODE10_0              GPIO_MODER_MODER10_0\n#define GPIO_MODER_MODE10_1              GPIO_MODER_MODER10_1\n#define GPIO_MODER_MODE11_Pos            GPIO_MODER_MODER11_Pos\n#define GPIO_MODER_MODE11_Msk            GPIO_MODER_MODER11_Msk\n#define GPIO_MODER_MODE11                GPIO_MODER_MODER11\n#define GPIO_MODER_MODE11_0              GPIO_MODER_MODER11_0\n#define GPIO_MODER_MODE11_1              GPIO_MODER_MODER11_1\n#define GPIO_MODER_MODE12_Pos            GPIO_MODER_MODER12_Pos\n#define GPIO_MODER_MODE12_Msk            GPIO_MODER_MODER12_Msk\n#define GPIO_MODER_MODE12                GPIO_MODER_MODER12\n#define GPIO_MODER_MODE12_0              GPIO_MODER_MODER12_0\n#define GPIO_MODER_MODE12_1              GPIO_MODER_MODER12_1\n#define GPIO_MODER_MODE13_Pos            GPIO_MODER_MODER13_Pos\n#define GPIO_MODER_MODE13_Msk            GPIO_MODER_MODER13_Msk\n#define GPIO_MODER_MODE13                GPIO_MODER_MODER13\n#define GPIO_MODER_MODE13_0              GPIO_MODER_MODER13_0\n#define GPIO_MODER_MODE13_1              GPIO_MODER_MODER13_1\n#define GPIO_MODER_MODE14_Pos            GPIO_MODER_MODER14_Pos\n#define GPIO_MODER_MODE14_Msk            GPIO_MODER_MODER14_Msk\n#define GPIO_MODER_MODE14                GPIO_MODER_MODER14\n#define GPIO_MODER_MODE14_0              GPIO_MODER_MODER14_0\n#define GPIO_MODER_MODE14_1              GPIO_MODER_MODER14_1\n#define GPIO_MODER_MODE15_Pos            GPIO_MODER_MODER15_Pos\n#define GPIO_MODER_MODE15_Msk            GPIO_MODER_MODER15_Msk\n#define GPIO_MODER_MODE15                GPIO_MODER_MODER15\n#define GPIO_MODER_MODE15_0              GPIO_MODER_MODER15_0\n#define GPIO_MODER_MODE15_1              GPIO_MODER_MODER15_1\n\n/******************  Bits definition for GPIO_OTYPER register  ****************/\n#define GPIO_OTYPER_OT0_Pos              (0U)\n#define GPIO_OTYPER_OT0_Msk              (0x1UL << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */\n#define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk\n#define GPIO_OTYPER_OT1_Pos              (1U)\n#define GPIO_OTYPER_OT1_Msk              (0x1UL << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */\n#define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk\n#define GPIO_OTYPER_OT2_Pos              (2U)\n#define GPIO_OTYPER_OT2_Msk              (0x1UL << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */\n#define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk\n#define GPIO_OTYPER_OT3_Pos              (3U)\n#define GPIO_OTYPER_OT3_Msk              (0x1UL << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */\n#define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk\n#define GPIO_OTYPER_OT4_Pos              (4U)\n#define GPIO_OTYPER_OT4_Msk              (0x1UL << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */\n#define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk\n#define GPIO_OTYPER_OT5_Pos              (5U)\n#define GPIO_OTYPER_OT5_Msk              (0x1UL << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */\n#define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk\n#define GPIO_OTYPER_OT6_Pos              (6U)\n#define GPIO_OTYPER_OT6_Msk              (0x1UL << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */\n#define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk\n#define GPIO_OTYPER_OT7_Pos              (7U)\n#define GPIO_OTYPER_OT7_Msk              (0x1UL << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */\n#define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk\n#define GPIO_OTYPER_OT8_Pos              (8U)\n#define GPIO_OTYPER_OT8_Msk              (0x1UL << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */\n#define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk\n#define GPIO_OTYPER_OT9_Pos              (9U)\n#define GPIO_OTYPER_OT9_Msk              (0x1UL << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */\n#define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk\n#define GPIO_OTYPER_OT10_Pos             (10U)\n#define GPIO_OTYPER_OT10_Msk             (0x1UL << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */\n#define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk\n#define GPIO_OTYPER_OT11_Pos             (11U)\n#define GPIO_OTYPER_OT11_Msk             (0x1UL << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */\n#define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk\n#define GPIO_OTYPER_OT12_Pos             (12U)\n#define GPIO_OTYPER_OT12_Msk             (0x1UL << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */\n#define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk\n#define GPIO_OTYPER_OT13_Pos             (13U)\n#define GPIO_OTYPER_OT13_Msk             (0x1UL << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */\n#define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk\n#define GPIO_OTYPER_OT14_Pos             (14U)\n#define GPIO_OTYPER_OT14_Msk             (0x1UL << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */\n#define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk\n#define GPIO_OTYPER_OT15_Pos             (15U)\n#define GPIO_OTYPER_OT15_Msk             (0x1UL << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */\n#define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk\n\n/* Legacy defines */\n#define GPIO_OTYPER_OT_0                 GPIO_OTYPER_OT0\n#define GPIO_OTYPER_OT_1                 GPIO_OTYPER_OT1\n#define GPIO_OTYPER_OT_2                 GPIO_OTYPER_OT2\n#define GPIO_OTYPER_OT_3                 GPIO_OTYPER_OT3\n#define GPIO_OTYPER_OT_4                 GPIO_OTYPER_OT4\n#define GPIO_OTYPER_OT_5                 GPIO_OTYPER_OT5\n#define GPIO_OTYPER_OT_6                 GPIO_OTYPER_OT6\n#define GPIO_OTYPER_OT_7                 GPIO_OTYPER_OT7\n#define GPIO_OTYPER_OT_8                 GPIO_OTYPER_OT8\n#define GPIO_OTYPER_OT_9                 GPIO_OTYPER_OT9\n#define GPIO_OTYPER_OT_10                GPIO_OTYPER_OT10\n#define GPIO_OTYPER_OT_11                GPIO_OTYPER_OT11\n#define GPIO_OTYPER_OT_12                GPIO_OTYPER_OT12\n#define GPIO_OTYPER_OT_13                GPIO_OTYPER_OT13\n#define GPIO_OTYPER_OT_14                GPIO_OTYPER_OT14\n#define GPIO_OTYPER_OT_15                GPIO_OTYPER_OT15\n\n/******************  Bits definition for GPIO_OSPEEDR register  ***************/\n#define GPIO_OSPEEDR_OSPEED0_Pos         (0U)\n#define GPIO_OSPEEDR_OSPEED0_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000003 */\n#define GPIO_OSPEEDR_OSPEED0             GPIO_OSPEEDR_OSPEED0_Msk\n#define GPIO_OSPEEDR_OSPEED0_0           (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000001 */\n#define GPIO_OSPEEDR_OSPEED0_1           (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000002 */\n#define GPIO_OSPEEDR_OSPEED1_Pos         (2U)\n#define GPIO_OSPEEDR_OSPEED1_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x0000000C */\n#define GPIO_OSPEEDR_OSPEED1             GPIO_OSPEEDR_OSPEED1_Msk\n#define GPIO_OSPEEDR_OSPEED1_0           (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000004 */\n#define GPIO_OSPEEDR_OSPEED1_1           (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000008 */\n#define GPIO_OSPEEDR_OSPEED2_Pos         (4U)\n#define GPIO_OSPEEDR_OSPEED2_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000030 */\n#define GPIO_OSPEEDR_OSPEED2             GPIO_OSPEEDR_OSPEED2_Msk\n#define GPIO_OSPEEDR_OSPEED2_0           (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000010 */\n#define GPIO_OSPEEDR_OSPEED2_1           (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000020 */\n#define GPIO_OSPEEDR_OSPEED3_Pos         (6U)\n#define GPIO_OSPEEDR_OSPEED3_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x000000C0 */\n#define GPIO_OSPEEDR_OSPEED3             GPIO_OSPEEDR_OSPEED3_Msk\n#define GPIO_OSPEEDR_OSPEED3_0           (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000040 */\n#define GPIO_OSPEEDR_OSPEED3_1           (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000080 */\n#define GPIO_OSPEEDR_OSPEED4_Pos         (8U)\n#define GPIO_OSPEEDR_OSPEED4_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000300 */\n#define GPIO_OSPEEDR_OSPEED4             GPIO_OSPEEDR_OSPEED4_Msk\n#define GPIO_OSPEEDR_OSPEED4_0           (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000100 */\n#define GPIO_OSPEEDR_OSPEED4_1           (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000200 */\n#define GPIO_OSPEEDR_OSPEED5_Pos         (10U)\n#define GPIO_OSPEEDR_OSPEED5_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000C00 */\n#define GPIO_OSPEEDR_OSPEED5             GPIO_OSPEEDR_OSPEED5_Msk\n#define GPIO_OSPEEDR_OSPEED5_0           (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000400 */\n#define GPIO_OSPEEDR_OSPEED5_1           (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000800 */\n#define GPIO_OSPEEDR_OSPEED6_Pos         (12U)\n#define GPIO_OSPEEDR_OSPEED6_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00003000 */\n#define GPIO_OSPEEDR_OSPEED6             GPIO_OSPEEDR_OSPEED6_Msk\n#define GPIO_OSPEEDR_OSPEED6_0           (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00001000 */\n#define GPIO_OSPEEDR_OSPEED6_1           (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00002000 */\n#define GPIO_OSPEEDR_OSPEED7_Pos         (14U)\n#define GPIO_OSPEEDR_OSPEED7_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x0000C000 */\n#define GPIO_OSPEEDR_OSPEED7             GPIO_OSPEEDR_OSPEED7_Msk\n#define GPIO_OSPEEDR_OSPEED7_0           (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00004000 */\n#define GPIO_OSPEEDR_OSPEED7_1           (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00008000 */\n#define GPIO_OSPEEDR_OSPEED8_Pos         (16U)\n#define GPIO_OSPEEDR_OSPEED8_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00030000 */\n#define GPIO_OSPEEDR_OSPEED8             GPIO_OSPEEDR_OSPEED8_Msk\n#define GPIO_OSPEEDR_OSPEED8_0           (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00010000 */\n#define GPIO_OSPEEDR_OSPEED8_1           (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00020000 */\n#define GPIO_OSPEEDR_OSPEED9_Pos         (18U)\n#define GPIO_OSPEEDR_OSPEED9_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x000C0000 */\n#define GPIO_OSPEEDR_OSPEED9             GPIO_OSPEEDR_OSPEED9_Msk\n#define GPIO_OSPEEDR_OSPEED9_0           (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00040000 */\n#define GPIO_OSPEEDR_OSPEED9_1           (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00080000 */\n#define GPIO_OSPEEDR_OSPEED10_Pos        (20U)\n#define GPIO_OSPEEDR_OSPEED10_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00300000 */\n#define GPIO_OSPEEDR_OSPEED10            GPIO_OSPEEDR_OSPEED10_Msk\n#define GPIO_OSPEEDR_OSPEED10_0          (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00100000 */\n#define GPIO_OSPEEDR_OSPEED10_1          (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00200000 */\n#define GPIO_OSPEEDR_OSPEED11_Pos        (22U)\n#define GPIO_OSPEEDR_OSPEED11_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00C00000 */\n#define GPIO_OSPEEDR_OSPEED11            GPIO_OSPEEDR_OSPEED11_Msk\n#define GPIO_OSPEEDR_OSPEED11_0          (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00400000 */\n#define GPIO_OSPEEDR_OSPEED11_1          (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00800000 */\n#define GPIO_OSPEEDR_OSPEED12_Pos        (24U)\n#define GPIO_OSPEEDR_OSPEED12_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x03000000 */\n#define GPIO_OSPEEDR_OSPEED12            GPIO_OSPEEDR_OSPEED12_Msk\n#define GPIO_OSPEEDR_OSPEED12_0          (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x01000000 */\n#define GPIO_OSPEEDR_OSPEED12_1          (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x02000000 */\n#define GPIO_OSPEEDR_OSPEED13_Pos        (26U)\n#define GPIO_OSPEEDR_OSPEED13_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x0C000000 */\n#define GPIO_OSPEEDR_OSPEED13            GPIO_OSPEEDR_OSPEED13_Msk\n#define GPIO_OSPEEDR_OSPEED13_0          (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x04000000 */\n#define GPIO_OSPEEDR_OSPEED13_1          (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x08000000 */\n#define GPIO_OSPEEDR_OSPEED14_Pos        (28U)\n#define GPIO_OSPEEDR_OSPEED14_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x30000000 */\n#define GPIO_OSPEEDR_OSPEED14            GPIO_OSPEEDR_OSPEED14_Msk\n#define GPIO_OSPEEDR_OSPEED14_0          (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x10000000 */\n#define GPIO_OSPEEDR_OSPEED14_1          (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x20000000 */\n#define GPIO_OSPEEDR_OSPEED15_Pos        (30U)\n#define GPIO_OSPEEDR_OSPEED15_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0xC0000000 */\n#define GPIO_OSPEEDR_OSPEED15            GPIO_OSPEEDR_OSPEED15_Msk\n#define GPIO_OSPEEDR_OSPEED15_0          (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x40000000 */\n#define GPIO_OSPEEDR_OSPEED15_1          (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDR_OSPEED0\n#define GPIO_OSPEEDER_OSPEEDR0_0         GPIO_OSPEEDR_OSPEED0_0\n#define GPIO_OSPEEDER_OSPEEDR0_1         GPIO_OSPEEDR_OSPEED0_1\n#define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDR_OSPEED1\n#define GPIO_OSPEEDER_OSPEEDR1_0         GPIO_OSPEEDR_OSPEED1_0\n#define GPIO_OSPEEDER_OSPEEDR1_1         GPIO_OSPEEDR_OSPEED1_1\n#define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDR_OSPEED2\n#define GPIO_OSPEEDER_OSPEEDR2_0         GPIO_OSPEEDR_OSPEED2_0\n#define GPIO_OSPEEDER_OSPEEDR2_1         GPIO_OSPEEDR_OSPEED2_1\n#define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDR_OSPEED3\n#define GPIO_OSPEEDER_OSPEEDR3_0         GPIO_OSPEEDR_OSPEED3_0\n#define GPIO_OSPEEDER_OSPEEDR3_1         GPIO_OSPEEDR_OSPEED3_1\n#define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDR_OSPEED4\n#define GPIO_OSPEEDER_OSPEEDR4_0         GPIO_OSPEEDR_OSPEED4_0\n#define GPIO_OSPEEDER_OSPEEDR4_1         GPIO_OSPEEDR_OSPEED4_1\n#define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDR_OSPEED5\n#define GPIO_OSPEEDER_OSPEEDR5_0         GPIO_OSPEEDR_OSPEED5_0\n#define GPIO_OSPEEDER_OSPEEDR5_1         GPIO_OSPEEDR_OSPEED5_1\n#define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDR_OSPEED6\n#define GPIO_OSPEEDER_OSPEEDR6_0         GPIO_OSPEEDR_OSPEED6_0\n#define GPIO_OSPEEDER_OSPEEDR6_1         GPIO_OSPEEDR_OSPEED6_1\n#define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDR_OSPEED7\n#define GPIO_OSPEEDER_OSPEEDR7_0         GPIO_OSPEEDR_OSPEED7_0\n#define GPIO_OSPEEDER_OSPEEDR7_1         GPIO_OSPEEDR_OSPEED7_1\n#define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDR_OSPEED8\n#define GPIO_OSPEEDER_OSPEEDR8_0         GPIO_OSPEEDR_OSPEED8_0\n#define GPIO_OSPEEDER_OSPEEDR8_1         GPIO_OSPEEDR_OSPEED8_1\n#define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDR_OSPEED9\n#define GPIO_OSPEEDER_OSPEEDR9_0         GPIO_OSPEEDR_OSPEED9_0\n#define GPIO_OSPEEDER_OSPEEDR9_1         GPIO_OSPEEDR_OSPEED9_1\n#define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDR_OSPEED10\n#define GPIO_OSPEEDER_OSPEEDR10_0        GPIO_OSPEEDR_OSPEED10_0\n#define GPIO_OSPEEDER_OSPEEDR10_1        GPIO_OSPEEDR_OSPEED10_1\n#define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDR_OSPEED11\n#define GPIO_OSPEEDER_OSPEEDR11_0        GPIO_OSPEEDR_OSPEED11_0\n#define GPIO_OSPEEDER_OSPEEDR11_1        GPIO_OSPEEDR_OSPEED11_1\n#define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDR_OSPEED12\n#define GPIO_OSPEEDER_OSPEEDR12_0        GPIO_OSPEEDR_OSPEED12_0\n#define GPIO_OSPEEDER_OSPEEDR12_1        GPIO_OSPEEDR_OSPEED12_1\n#define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDR_OSPEED13\n#define GPIO_OSPEEDER_OSPEEDR13_0        GPIO_OSPEEDR_OSPEED13_0\n#define GPIO_OSPEEDER_OSPEEDR13_1        GPIO_OSPEEDR_OSPEED13_1\n#define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDR_OSPEED14\n#define GPIO_OSPEEDER_OSPEEDR14_0        GPIO_OSPEEDR_OSPEED14_0\n#define GPIO_OSPEEDER_OSPEEDR14_1        GPIO_OSPEEDR_OSPEED14_1\n#define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDR_OSPEED15\n#define GPIO_OSPEEDER_OSPEEDR15_0        GPIO_OSPEEDR_OSPEED15_0\n#define GPIO_OSPEEDER_OSPEEDR15_1        GPIO_OSPEEDR_OSPEED15_1\n\n/******************  Bits definition for GPIO_PUPDR register  *****************/\n#define GPIO_PUPDR_PUPD0_Pos             (0U)\n#define GPIO_PUPDR_PUPD0_Msk             (0x3UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000003 */\n#define GPIO_PUPDR_PUPD0                 GPIO_PUPDR_PUPD0_Msk\n#define GPIO_PUPDR_PUPD0_0               (0x1UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000001 */\n#define GPIO_PUPDR_PUPD0_1               (0x2UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000002 */\n#define GPIO_PUPDR_PUPD1_Pos             (2U)\n#define GPIO_PUPDR_PUPD1_Msk             (0x3UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x0000000C */\n#define GPIO_PUPDR_PUPD1                 GPIO_PUPDR_PUPD1_Msk\n#define GPIO_PUPDR_PUPD1_0               (0x1UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000004 */\n#define GPIO_PUPDR_PUPD1_1               (0x2UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000008 */\n#define GPIO_PUPDR_PUPD2_Pos             (4U)\n#define GPIO_PUPDR_PUPD2_Msk             (0x3UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000030 */\n#define GPIO_PUPDR_PUPD2                 GPIO_PUPDR_PUPD2_Msk\n#define GPIO_PUPDR_PUPD2_0               (0x1UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000010 */\n#define GPIO_PUPDR_PUPD2_1               (0x2UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000020 */\n#define GPIO_PUPDR_PUPD3_Pos             (6U)\n#define GPIO_PUPDR_PUPD3_Msk             (0x3UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x000000C0 */\n#define GPIO_PUPDR_PUPD3                 GPIO_PUPDR_PUPD3_Msk\n#define GPIO_PUPDR_PUPD3_0               (0x1UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000040 */\n#define GPIO_PUPDR_PUPD3_1               (0x2UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000080 */\n#define GPIO_PUPDR_PUPD4_Pos             (8U)\n#define GPIO_PUPDR_PUPD4_Msk             (0x3UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000300 */\n#define GPIO_PUPDR_PUPD4                 GPIO_PUPDR_PUPD4_Msk\n#define GPIO_PUPDR_PUPD4_0               (0x1UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000100 */\n#define GPIO_PUPDR_PUPD4_1               (0x2UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000200 */\n#define GPIO_PUPDR_PUPD5_Pos             (10U)\n#define GPIO_PUPDR_PUPD5_Msk             (0x3UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000C00 */\n#define GPIO_PUPDR_PUPD5                 GPIO_PUPDR_PUPD5_Msk\n#define GPIO_PUPDR_PUPD5_0               (0x1UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000400 */\n#define GPIO_PUPDR_PUPD5_1               (0x2UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000800 */\n#define GPIO_PUPDR_PUPD6_Pos             (12U)\n#define GPIO_PUPDR_PUPD6_Msk             (0x3UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00003000 */\n#define GPIO_PUPDR_PUPD6                 GPIO_PUPDR_PUPD6_Msk\n#define GPIO_PUPDR_PUPD6_0               (0x1UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00001000 */\n#define GPIO_PUPDR_PUPD6_1               (0x2UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00002000 */\n#define GPIO_PUPDR_PUPD7_Pos             (14U)\n#define GPIO_PUPDR_PUPD7_Msk             (0x3UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x0000C000 */\n#define GPIO_PUPDR_PUPD7                 GPIO_PUPDR_PUPD7_Msk\n#define GPIO_PUPDR_PUPD7_0               (0x1UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00004000 */\n#define GPIO_PUPDR_PUPD7_1               (0x2UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00008000 */\n#define GPIO_PUPDR_PUPD8_Pos             (16U)\n#define GPIO_PUPDR_PUPD8_Msk             (0x3UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00030000 */\n#define GPIO_PUPDR_PUPD8                 GPIO_PUPDR_PUPD8_Msk\n#define GPIO_PUPDR_PUPD8_0               (0x1UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00010000 */\n#define GPIO_PUPDR_PUPD8_1               (0x2UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00020000 */\n#define GPIO_PUPDR_PUPD9_Pos             (18U)\n#define GPIO_PUPDR_PUPD9_Msk             (0x3UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x000C0000 */\n#define GPIO_PUPDR_PUPD9                 GPIO_PUPDR_PUPD9_Msk\n#define GPIO_PUPDR_PUPD9_0               (0x1UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00040000 */\n#define GPIO_PUPDR_PUPD9_1               (0x2UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00080000 */\n#define GPIO_PUPDR_PUPD10_Pos            (20U)\n#define GPIO_PUPDR_PUPD10_Msk            (0x3UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00300000 */\n#define GPIO_PUPDR_PUPD10                GPIO_PUPDR_PUPD10_Msk\n#define GPIO_PUPDR_PUPD10_0              (0x1UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00100000 */\n#define GPIO_PUPDR_PUPD10_1              (0x2UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00200000 */\n#define GPIO_PUPDR_PUPD11_Pos            (22U)\n#define GPIO_PUPDR_PUPD11_Msk            (0x3UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00C00000 */\n#define GPIO_PUPDR_PUPD11                GPIO_PUPDR_PUPD11_Msk\n#define GPIO_PUPDR_PUPD11_0              (0x1UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00400000 */\n#define GPIO_PUPDR_PUPD11_1              (0x2UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00800000 */\n#define GPIO_PUPDR_PUPD12_Pos            (24U)\n#define GPIO_PUPDR_PUPD12_Msk            (0x3UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x03000000 */\n#define GPIO_PUPDR_PUPD12                GPIO_PUPDR_PUPD12_Msk\n#define GPIO_PUPDR_PUPD12_0              (0x1UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x01000000 */\n#define GPIO_PUPDR_PUPD12_1              (0x2UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x02000000 */\n#define GPIO_PUPDR_PUPD13_Pos            (26U)\n#define GPIO_PUPDR_PUPD13_Msk            (0x3UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x0C000000 */\n#define GPIO_PUPDR_PUPD13                GPIO_PUPDR_PUPD13_Msk\n#define GPIO_PUPDR_PUPD13_0              (0x1UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x04000000 */\n#define GPIO_PUPDR_PUPD13_1              (0x2UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x08000000 */\n#define GPIO_PUPDR_PUPD14_Pos            (28U)\n#define GPIO_PUPDR_PUPD14_Msk            (0x3UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x30000000 */\n#define GPIO_PUPDR_PUPD14                GPIO_PUPDR_PUPD14_Msk\n#define GPIO_PUPDR_PUPD14_0              (0x1UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x10000000 */\n#define GPIO_PUPDR_PUPD14_1              (0x2UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x20000000 */\n#define GPIO_PUPDR_PUPD15_Pos            (30U)\n#define GPIO_PUPDR_PUPD15_Msk            (0x3UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0xC0000000 */\n#define GPIO_PUPDR_PUPD15                GPIO_PUPDR_PUPD15_Msk\n#define GPIO_PUPDR_PUPD15_0              (0x1UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x40000000 */\n#define GPIO_PUPDR_PUPD15_1              (0x2UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPD0\n#define GPIO_PUPDR_PUPDR0_0              GPIO_PUPDR_PUPD0_0\n#define GPIO_PUPDR_PUPDR0_1              GPIO_PUPDR_PUPD0_1\n#define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPD1\n#define GPIO_PUPDR_PUPDR1_0              GPIO_PUPDR_PUPD1_0\n#define GPIO_PUPDR_PUPDR1_1              GPIO_PUPDR_PUPD1_1\n#define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPD2\n#define GPIO_PUPDR_PUPDR2_0              GPIO_PUPDR_PUPD2_0\n#define GPIO_PUPDR_PUPDR2_1              GPIO_PUPDR_PUPD2_1\n#define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPD3\n#define GPIO_PUPDR_PUPDR3_0              GPIO_PUPDR_PUPD3_0\n#define GPIO_PUPDR_PUPDR3_1              GPIO_PUPDR_PUPD3_1\n#define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPD4\n#define GPIO_PUPDR_PUPDR4_0              GPIO_PUPDR_PUPD4_0\n#define GPIO_PUPDR_PUPDR4_1              GPIO_PUPDR_PUPD4_1\n#define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPD5\n#define GPIO_PUPDR_PUPDR5_0              GPIO_PUPDR_PUPD5_0\n#define GPIO_PUPDR_PUPDR5_1              GPIO_PUPDR_PUPD5_1\n#define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPD6\n#define GPIO_PUPDR_PUPDR6_0              GPIO_PUPDR_PUPD6_0\n#define GPIO_PUPDR_PUPDR6_1              GPIO_PUPDR_PUPD6_1\n#define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPD7\n#define GPIO_PUPDR_PUPDR7_0              GPIO_PUPDR_PUPD7_0\n#define GPIO_PUPDR_PUPDR7_1              GPIO_PUPDR_PUPD7_1\n#define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPD8\n#define GPIO_PUPDR_PUPDR8_0              GPIO_PUPDR_PUPD8_0\n#define GPIO_PUPDR_PUPDR8_1              GPIO_PUPDR_PUPD8_1\n#define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPD9\n#define GPIO_PUPDR_PUPDR9_0              GPIO_PUPDR_PUPD9_0\n#define GPIO_PUPDR_PUPDR9_1              GPIO_PUPDR_PUPD9_1\n#define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPD10\n#define GPIO_PUPDR_PUPDR10_0             GPIO_PUPDR_PUPD10_0\n#define GPIO_PUPDR_PUPDR10_1             GPIO_PUPDR_PUPD10_1\n#define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPD11\n#define GPIO_PUPDR_PUPDR11_0             GPIO_PUPDR_PUPD11_0\n#define GPIO_PUPDR_PUPDR11_1             GPIO_PUPDR_PUPD11_1\n#define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPD12\n#define GPIO_PUPDR_PUPDR12_0             GPIO_PUPDR_PUPD12_0\n#define GPIO_PUPDR_PUPDR12_1             GPIO_PUPDR_PUPD12_1\n#define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPD13\n#define GPIO_PUPDR_PUPDR13_0             GPIO_PUPDR_PUPD13_0\n#define GPIO_PUPDR_PUPDR13_1             GPIO_PUPDR_PUPD13_1\n#define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPD14\n#define GPIO_PUPDR_PUPDR14_0             GPIO_PUPDR_PUPD14_0\n#define GPIO_PUPDR_PUPDR14_1             GPIO_PUPDR_PUPD14_1\n#define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPD15\n#define GPIO_PUPDR_PUPDR15_0             GPIO_PUPDR_PUPD15_0\n#define GPIO_PUPDR_PUPDR15_1             GPIO_PUPDR_PUPD15_1\n\n/******************  Bits definition for GPIO_IDR register  *******************/\n#define GPIO_IDR_ID0_Pos                 (0U)\n#define GPIO_IDR_ID0_Msk                 (0x1UL << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */\n#define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk\n#define GPIO_IDR_ID1_Pos                 (1U)\n#define GPIO_IDR_ID1_Msk                 (0x1UL << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */\n#define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk\n#define GPIO_IDR_ID2_Pos                 (2U)\n#define GPIO_IDR_ID2_Msk                 (0x1UL << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */\n#define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk\n#define GPIO_IDR_ID3_Pos                 (3U)\n#define GPIO_IDR_ID3_Msk                 (0x1UL << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */\n#define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk\n#define GPIO_IDR_ID4_Pos                 (4U)\n#define GPIO_IDR_ID4_Msk                 (0x1UL << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */\n#define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk\n#define GPIO_IDR_ID5_Pos                 (5U)\n#define GPIO_IDR_ID5_Msk                 (0x1UL << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */\n#define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk\n#define GPIO_IDR_ID6_Pos                 (6U)\n#define GPIO_IDR_ID6_Msk                 (0x1UL << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */\n#define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk\n#define GPIO_IDR_ID7_Pos                 (7U)\n#define GPIO_IDR_ID7_Msk                 (0x1UL << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */\n#define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk\n#define GPIO_IDR_ID8_Pos                 (8U)\n#define GPIO_IDR_ID8_Msk                 (0x1UL << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */\n#define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk\n#define GPIO_IDR_ID9_Pos                 (9U)\n#define GPIO_IDR_ID9_Msk                 (0x1UL << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */\n#define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk\n#define GPIO_IDR_ID10_Pos                (10U)\n#define GPIO_IDR_ID10_Msk                (0x1UL << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */\n#define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk\n#define GPIO_IDR_ID11_Pos                (11U)\n#define GPIO_IDR_ID11_Msk                (0x1UL << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */\n#define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk\n#define GPIO_IDR_ID12_Pos                (12U)\n#define GPIO_IDR_ID12_Msk                (0x1UL << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */\n#define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk\n#define GPIO_IDR_ID13_Pos                (13U)\n#define GPIO_IDR_ID13_Msk                (0x1UL << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */\n#define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk\n#define GPIO_IDR_ID14_Pos                (14U)\n#define GPIO_IDR_ID14_Msk                (0x1UL << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */\n#define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk\n#define GPIO_IDR_ID15_Pos                (15U)\n#define GPIO_IDR_ID15_Msk                (0x1UL << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */\n#define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk\n\n/* Legacy defines */\n#define GPIO_IDR_IDR_0                   GPIO_IDR_ID0\n#define GPIO_IDR_IDR_1                   GPIO_IDR_ID1\n#define GPIO_IDR_IDR_2                   GPIO_IDR_ID2\n#define GPIO_IDR_IDR_3                   GPIO_IDR_ID3\n#define GPIO_IDR_IDR_4                   GPIO_IDR_ID4\n#define GPIO_IDR_IDR_5                   GPIO_IDR_ID5\n#define GPIO_IDR_IDR_6                   GPIO_IDR_ID6\n#define GPIO_IDR_IDR_7                   GPIO_IDR_ID7\n#define GPIO_IDR_IDR_8                   GPIO_IDR_ID8\n#define GPIO_IDR_IDR_9                   GPIO_IDR_ID9\n#define GPIO_IDR_IDR_10                  GPIO_IDR_ID10\n#define GPIO_IDR_IDR_11                  GPIO_IDR_ID11\n#define GPIO_IDR_IDR_12                  GPIO_IDR_ID12\n#define GPIO_IDR_IDR_13                  GPIO_IDR_ID13\n#define GPIO_IDR_IDR_14                  GPIO_IDR_ID14\n#define GPIO_IDR_IDR_15                  GPIO_IDR_ID15\n\n/******************  Bits definition for GPIO_ODR register  *******************/\n#define GPIO_ODR_OD0_Pos                 (0U)\n#define GPIO_ODR_OD0_Msk                 (0x1UL << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */\n#define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk\n#define GPIO_ODR_OD1_Pos                 (1U)\n#define GPIO_ODR_OD1_Msk                 (0x1UL << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */\n#define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk\n#define GPIO_ODR_OD2_Pos                 (2U)\n#define GPIO_ODR_OD2_Msk                 (0x1UL << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */\n#define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk\n#define GPIO_ODR_OD3_Pos                 (3U)\n#define GPIO_ODR_OD3_Msk                 (0x1UL << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */\n#define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk\n#define GPIO_ODR_OD4_Pos                 (4U)\n#define GPIO_ODR_OD4_Msk                 (0x1UL << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */\n#define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk\n#define GPIO_ODR_OD5_Pos                 (5U)\n#define GPIO_ODR_OD5_Msk                 (0x1UL << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */\n#define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk\n#define GPIO_ODR_OD6_Pos                 (6U)\n#define GPIO_ODR_OD6_Msk                 (0x1UL << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */\n#define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk\n#define GPIO_ODR_OD7_Pos                 (7U)\n#define GPIO_ODR_OD7_Msk                 (0x1UL << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */\n#define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk\n#define GPIO_ODR_OD8_Pos                 (8U)\n#define GPIO_ODR_OD8_Msk                 (0x1UL << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */\n#define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk\n#define GPIO_ODR_OD9_Pos                 (9U)\n#define GPIO_ODR_OD9_Msk                 (0x1UL << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */\n#define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk\n#define GPIO_ODR_OD10_Pos                (10U)\n#define GPIO_ODR_OD10_Msk                (0x1UL << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */\n#define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk\n#define GPIO_ODR_OD11_Pos                (11U)\n#define GPIO_ODR_OD11_Msk                (0x1UL << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */\n#define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk\n#define GPIO_ODR_OD12_Pos                (12U)\n#define GPIO_ODR_OD12_Msk                (0x1UL << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */\n#define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk\n#define GPIO_ODR_OD13_Pos                (13U)\n#define GPIO_ODR_OD13_Msk                (0x1UL << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */\n#define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk\n#define GPIO_ODR_OD14_Pos                (14U)\n#define GPIO_ODR_OD14_Msk                (0x1UL << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */\n#define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk\n#define GPIO_ODR_OD15_Pos                (15U)\n#define GPIO_ODR_OD15_Msk                (0x1UL << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */\n#define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk\n/* Legacy defines */\n#define GPIO_ODR_ODR_0                   GPIO_ODR_OD0\n#define GPIO_ODR_ODR_1                   GPIO_ODR_OD1\n#define GPIO_ODR_ODR_2                   GPIO_ODR_OD2\n#define GPIO_ODR_ODR_3                   GPIO_ODR_OD3\n#define GPIO_ODR_ODR_4                   GPIO_ODR_OD4\n#define GPIO_ODR_ODR_5                   GPIO_ODR_OD5\n#define GPIO_ODR_ODR_6                   GPIO_ODR_OD6\n#define GPIO_ODR_ODR_7                   GPIO_ODR_OD7\n#define GPIO_ODR_ODR_8                   GPIO_ODR_OD8\n#define GPIO_ODR_ODR_9                   GPIO_ODR_OD9\n#define GPIO_ODR_ODR_10                  GPIO_ODR_OD10\n#define GPIO_ODR_ODR_11                  GPIO_ODR_OD11\n#define GPIO_ODR_ODR_12                  GPIO_ODR_OD12\n#define GPIO_ODR_ODR_13                  GPIO_ODR_OD13\n#define GPIO_ODR_ODR_14                  GPIO_ODR_OD14\n#define GPIO_ODR_ODR_15                  GPIO_ODR_OD15\n\n/******************  Bits definition for GPIO_BSRR register  ******************/\n#define GPIO_BSRR_BS0_Pos                (0U)\n#define GPIO_BSRR_BS0_Msk                (0x1UL << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */\n#define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk\n#define GPIO_BSRR_BS1_Pos                (1U)\n#define GPIO_BSRR_BS1_Msk                (0x1UL << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */\n#define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk\n#define GPIO_BSRR_BS2_Pos                (2U)\n#define GPIO_BSRR_BS2_Msk                (0x1UL << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */\n#define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk\n#define GPIO_BSRR_BS3_Pos                (3U)\n#define GPIO_BSRR_BS3_Msk                (0x1UL << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */\n#define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk\n#define GPIO_BSRR_BS4_Pos                (4U)\n#define GPIO_BSRR_BS4_Msk                (0x1UL << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */\n#define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk\n#define GPIO_BSRR_BS5_Pos                (5U)\n#define GPIO_BSRR_BS5_Msk                (0x1UL << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */\n#define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk\n#define GPIO_BSRR_BS6_Pos                (6U)\n#define GPIO_BSRR_BS6_Msk                (0x1UL << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */\n#define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk\n#define GPIO_BSRR_BS7_Pos                (7U)\n#define GPIO_BSRR_BS7_Msk                (0x1UL << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */\n#define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk\n#define GPIO_BSRR_BS8_Pos                (8U)\n#define GPIO_BSRR_BS8_Msk                (0x1UL << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */\n#define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk\n#define GPIO_BSRR_BS9_Pos                (9U)\n#define GPIO_BSRR_BS9_Msk                (0x1UL << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */\n#define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk\n#define GPIO_BSRR_BS10_Pos               (10U)\n#define GPIO_BSRR_BS10_Msk               (0x1UL << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */\n#define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk\n#define GPIO_BSRR_BS11_Pos               (11U)\n#define GPIO_BSRR_BS11_Msk               (0x1UL << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */\n#define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk\n#define GPIO_BSRR_BS12_Pos               (12U)\n#define GPIO_BSRR_BS12_Msk               (0x1UL << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */\n#define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk\n#define GPIO_BSRR_BS13_Pos               (13U)\n#define GPIO_BSRR_BS13_Msk               (0x1UL << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */\n#define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk\n#define GPIO_BSRR_BS14_Pos               (14U)\n#define GPIO_BSRR_BS14_Msk               (0x1UL << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */\n#define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk\n#define GPIO_BSRR_BS15_Pos               (15U)\n#define GPIO_BSRR_BS15_Msk               (0x1UL << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */\n#define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk\n#define GPIO_BSRR_BR0_Pos                (16U)\n#define GPIO_BSRR_BR0_Msk                (0x1UL << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */\n#define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk\n#define GPIO_BSRR_BR1_Pos                (17U)\n#define GPIO_BSRR_BR1_Msk                (0x1UL << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */\n#define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk\n#define GPIO_BSRR_BR2_Pos                (18U)\n#define GPIO_BSRR_BR2_Msk                (0x1UL << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */\n#define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk\n#define GPIO_BSRR_BR3_Pos                (19U)\n#define GPIO_BSRR_BR3_Msk                (0x1UL << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */\n#define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk\n#define GPIO_BSRR_BR4_Pos                (20U)\n#define GPIO_BSRR_BR4_Msk                (0x1UL << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */\n#define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk\n#define GPIO_BSRR_BR5_Pos                (21U)\n#define GPIO_BSRR_BR5_Msk                (0x1UL << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */\n#define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk\n#define GPIO_BSRR_BR6_Pos                (22U)\n#define GPIO_BSRR_BR6_Msk                (0x1UL << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */\n#define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk\n#define GPIO_BSRR_BR7_Pos                (23U)\n#define GPIO_BSRR_BR7_Msk                (0x1UL << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */\n#define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk\n#define GPIO_BSRR_BR8_Pos                (24U)\n#define GPIO_BSRR_BR8_Msk                (0x1UL << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */\n#define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk\n#define GPIO_BSRR_BR9_Pos                (25U)\n#define GPIO_BSRR_BR9_Msk                (0x1UL << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */\n#define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk\n#define GPIO_BSRR_BR10_Pos               (26U)\n#define GPIO_BSRR_BR10_Msk               (0x1UL << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */\n#define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk\n#define GPIO_BSRR_BR11_Pos               (27U)\n#define GPIO_BSRR_BR11_Msk               (0x1UL << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */\n#define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk\n#define GPIO_BSRR_BR12_Pos               (28U)\n#define GPIO_BSRR_BR12_Msk               (0x1UL << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */\n#define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk\n#define GPIO_BSRR_BR13_Pos               (29U)\n#define GPIO_BSRR_BR13_Msk               (0x1UL << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */\n#define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk\n#define GPIO_BSRR_BR14_Pos               (30U)\n#define GPIO_BSRR_BR14_Msk               (0x1UL << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */\n#define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk\n#define GPIO_BSRR_BR15_Pos               (31U)\n#define GPIO_BSRR_BR15_Msk               (0x1UL << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */\n#define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk\n\n/* Legacy defines */\n#define GPIO_BSRR_BS_0                   GPIO_BSRR_BS0\n#define GPIO_BSRR_BS_1                   GPIO_BSRR_BS1\n#define GPIO_BSRR_BS_2                   GPIO_BSRR_BS2\n#define GPIO_BSRR_BS_3                   GPIO_BSRR_BS3\n#define GPIO_BSRR_BS_4                   GPIO_BSRR_BS4\n#define GPIO_BSRR_BS_5                   GPIO_BSRR_BS5\n#define GPIO_BSRR_BS_6                   GPIO_BSRR_BS6\n#define GPIO_BSRR_BS_7                   GPIO_BSRR_BS7\n#define GPIO_BSRR_BS_8                   GPIO_BSRR_BS8\n#define GPIO_BSRR_BS_9                   GPIO_BSRR_BS9\n#define GPIO_BSRR_BS_10                  GPIO_BSRR_BS10\n#define GPIO_BSRR_BS_11                  GPIO_BSRR_BS11\n#define GPIO_BSRR_BS_12                  GPIO_BSRR_BS12\n#define GPIO_BSRR_BS_13                  GPIO_BSRR_BS13\n#define GPIO_BSRR_BS_14                  GPIO_BSRR_BS14\n#define GPIO_BSRR_BS_15                  GPIO_BSRR_BS15\n#define GPIO_BSRR_BR_0                   GPIO_BSRR_BR0\n#define GPIO_BSRR_BR_1                   GPIO_BSRR_BR1\n#define GPIO_BSRR_BR_2                   GPIO_BSRR_BR2\n#define GPIO_BSRR_BR_3                   GPIO_BSRR_BR3\n#define GPIO_BSRR_BR_4                   GPIO_BSRR_BR4\n#define GPIO_BSRR_BR_5                   GPIO_BSRR_BR5\n#define GPIO_BSRR_BR_6                   GPIO_BSRR_BR6\n#define GPIO_BSRR_BR_7                   GPIO_BSRR_BR7\n#define GPIO_BSRR_BR_8                   GPIO_BSRR_BR8\n#define GPIO_BSRR_BR_9                   GPIO_BSRR_BR9\n#define GPIO_BSRR_BR_10                  GPIO_BSRR_BR10\n#define GPIO_BSRR_BR_11                  GPIO_BSRR_BR11\n#define GPIO_BSRR_BR_12                  GPIO_BSRR_BR12\n#define GPIO_BSRR_BR_13                  GPIO_BSRR_BR13\n#define GPIO_BSRR_BR_14                  GPIO_BSRR_BR14\n#define GPIO_BSRR_BR_15                  GPIO_BSRR_BR15\n#define GPIO_BRR_BR0                     GPIO_BSRR_BR0\n#define GPIO_BRR_BR0_Pos                 GPIO_BSRR_BR0_Pos\n#define GPIO_BRR_BR0_Msk                 GPIO_BSRR_BR0_Msk\n#define GPIO_BRR_BR1                     GPIO_BSRR_BR1\n#define GPIO_BRR_BR1_Pos                 GPIO_BSRR_BR1_Pos\n#define GPIO_BRR_BR1_Msk                 GPIO_BSRR_BR1_Msk\n#define GPIO_BRR_BR2                     GPIO_BSRR_BR2\n#define GPIO_BRR_BR2_Pos                 GPIO_BSRR_BR2_Pos\n#define GPIO_BRR_BR2_Msk                 GPIO_BSRR_BR2_Msk\n#define GPIO_BRR_BR3                     GPIO_BSRR_BR3\n#define GPIO_BRR_BR3_Pos                 GPIO_BSRR_BR3_Pos\n#define GPIO_BRR_BR3_Msk                 GPIO_BSRR_BR3_Msk\n#define GPIO_BRR_BR4                     GPIO_BSRR_BR4\n#define GPIO_BRR_BR4_Pos                 GPIO_BSRR_BR4_Pos\n#define GPIO_BRR_BR4_Msk                 GPIO_BSRR_BR4_Msk\n#define GPIO_BRR_BR5                     GPIO_BSRR_BR5\n#define GPIO_BRR_BR5_Pos                 GPIO_BSRR_BR5_Pos\n#define GPIO_BRR_BR5_Msk                 GPIO_BSRR_BR5_Msk\n#define GPIO_BRR_BR6                     GPIO_BSRR_BR6\n#define GPIO_BRR_BR6_Pos                 GPIO_BSRR_BR6_Pos\n#define GPIO_BRR_BR6_Msk                 GPIO_BSRR_BR6_Msk\n#define GPIO_BRR_BR7                     GPIO_BSRR_BR7\n#define GPIO_BRR_BR7_Pos                 GPIO_BSRR_BR7_Pos\n#define GPIO_BRR_BR7_Msk                 GPIO_BSRR_BR7_Msk\n#define GPIO_BRR_BR8                     GPIO_BSRR_BR8\n#define GPIO_BRR_BR8_Pos                 GPIO_BSRR_BR8_Pos\n#define GPIO_BRR_BR8_Msk                 GPIO_BSRR_BR8_Msk\n#define GPIO_BRR_BR9                     GPIO_BSRR_BR9\n#define GPIO_BRR_BR9_Pos                 GPIO_BSRR_BR9_Pos\n#define GPIO_BRR_BR9_Msk                 GPIO_BSRR_BR9_Msk\n#define GPIO_BRR_BR10                    GPIO_BSRR_BR10\n#define GPIO_BRR_BR10_Pos                GPIO_BSRR_BR10_Pos\n#define GPIO_BRR_BR10_Msk                GPIO_BSRR_BR10_Msk\n#define GPIO_BRR_BR11                    GPIO_BSRR_BR11\n#define GPIO_BRR_BR11_Pos                GPIO_BSRR_BR11_Pos\n#define GPIO_BRR_BR11_Msk                GPIO_BSRR_BR11_Msk\n#define GPIO_BRR_BR12                    GPIO_BSRR_BR12\n#define GPIO_BRR_BR12_Pos                GPIO_BSRR_BR12_Pos\n#define GPIO_BRR_BR12_Msk                GPIO_BSRR_BR12_Msk\n#define GPIO_BRR_BR13                    GPIO_BSRR_BR13\n#define GPIO_BRR_BR13_Pos                GPIO_BSRR_BR13_Pos\n#define GPIO_BRR_BR13_Msk                GPIO_BSRR_BR13_Msk\n#define GPIO_BRR_BR14                    GPIO_BSRR_BR14\n#define GPIO_BRR_BR14_Pos                GPIO_BSRR_BR14_Pos\n#define GPIO_BRR_BR14_Msk                GPIO_BSRR_BR14_Msk\n#define GPIO_BRR_BR15                    GPIO_BSRR_BR15\n#define GPIO_BRR_BR15_Pos                GPIO_BSRR_BR15_Pos\n#define GPIO_BRR_BR15_Msk                GPIO_BSRR_BR15_Msk\n/****************** Bit definition for GPIO_LCKR register *********************/\n#define GPIO_LCKR_LCK0_Pos               (0U)\n#define GPIO_LCKR_LCK0_Msk               (0x1UL << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */\n#define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk\n#define GPIO_LCKR_LCK1_Pos               (1U)\n#define GPIO_LCKR_LCK1_Msk               (0x1UL << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */\n#define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk\n#define GPIO_LCKR_LCK2_Pos               (2U)\n#define GPIO_LCKR_LCK2_Msk               (0x1UL << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */\n#define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk\n#define GPIO_LCKR_LCK3_Pos               (3U)\n#define GPIO_LCKR_LCK3_Msk               (0x1UL << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */\n#define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk\n#define GPIO_LCKR_LCK4_Pos               (4U)\n#define GPIO_LCKR_LCK4_Msk               (0x1UL << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */\n#define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk\n#define GPIO_LCKR_LCK5_Pos               (5U)\n#define GPIO_LCKR_LCK5_Msk               (0x1UL << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */\n#define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk\n#define GPIO_LCKR_LCK6_Pos               (6U)\n#define GPIO_LCKR_LCK6_Msk               (0x1UL << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */\n#define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk\n#define GPIO_LCKR_LCK7_Pos               (7U)\n#define GPIO_LCKR_LCK7_Msk               (0x1UL << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */\n#define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk\n#define GPIO_LCKR_LCK8_Pos               (8U)\n#define GPIO_LCKR_LCK8_Msk               (0x1UL << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */\n#define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk\n#define GPIO_LCKR_LCK9_Pos               (9U)\n#define GPIO_LCKR_LCK9_Msk               (0x1UL << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */\n#define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk\n#define GPIO_LCKR_LCK10_Pos              (10U)\n#define GPIO_LCKR_LCK10_Msk              (0x1UL << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */\n#define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk\n#define GPIO_LCKR_LCK11_Pos              (11U)\n#define GPIO_LCKR_LCK11_Msk              (0x1UL << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */\n#define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk\n#define GPIO_LCKR_LCK12_Pos              (12U)\n#define GPIO_LCKR_LCK12_Msk              (0x1UL << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */\n#define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk\n#define GPIO_LCKR_LCK13_Pos              (13U)\n#define GPIO_LCKR_LCK13_Msk              (0x1UL << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */\n#define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk\n#define GPIO_LCKR_LCK14_Pos              (14U)\n#define GPIO_LCKR_LCK14_Msk              (0x1UL << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */\n#define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk\n#define GPIO_LCKR_LCK15_Pos              (15U)\n#define GPIO_LCKR_LCK15_Msk              (0x1UL << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */\n#define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk\n#define GPIO_LCKR_LCKK_Pos               (16U)\n#define GPIO_LCKR_LCKK_Msk               (0x1UL << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */\n#define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk\n/****************** Bit definition for GPIO_AFRL register *********************/\n#define GPIO_AFRL_AFSEL0_Pos             (0U)\n#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk\n#define GPIO_AFRL_AFSEL0_0               (0x1UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRL_AFSEL0_1               (0x2UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRL_AFSEL0_2               (0x4UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRL_AFSEL0_3               (0x8UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRL_AFSEL1_Pos             (4U)\n#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk\n#define GPIO_AFRL_AFSEL1_0               (0x1UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRL_AFSEL1_1               (0x2UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRL_AFSEL1_2               (0x4UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRL_AFSEL1_3               (0x8UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRL_AFSEL2_Pos             (8U)\n#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */\n#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk\n#define GPIO_AFRL_AFSEL2_0               (0x1UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */\n#define GPIO_AFRL_AFSEL2_1               (0x2UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */\n#define GPIO_AFRL_AFSEL2_2               (0x4UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */\n#define GPIO_AFRL_AFSEL2_3               (0x8UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */\n#define GPIO_AFRL_AFSEL3_Pos             (12U)\n#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */\n#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk\n#define GPIO_AFRL_AFSEL3_0               (0x1UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */\n#define GPIO_AFRL_AFSEL3_1               (0x2UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */\n#define GPIO_AFRL_AFSEL3_2               (0x4UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */\n#define GPIO_AFRL_AFSEL3_3               (0x8UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */\n#define GPIO_AFRL_AFSEL4_Pos             (16U)\n#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */\n#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk\n#define GPIO_AFRL_AFSEL4_0               (0x1UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */\n#define GPIO_AFRL_AFSEL4_1               (0x2UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */\n#define GPIO_AFRL_AFSEL4_2               (0x4UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */\n#define GPIO_AFRL_AFSEL4_3               (0x8UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */\n#define GPIO_AFRL_AFSEL5_Pos             (20U)\n#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */\n#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk\n#define GPIO_AFRL_AFSEL5_0               (0x1UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */\n#define GPIO_AFRL_AFSEL5_1               (0x2UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */\n#define GPIO_AFRL_AFSEL5_2               (0x4UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */\n#define GPIO_AFRL_AFSEL5_3               (0x8UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */\n#define GPIO_AFRL_AFSEL6_Pos             (24U)\n#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */\n#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk\n#define GPIO_AFRL_AFSEL6_0               (0x1UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */\n#define GPIO_AFRL_AFSEL6_1               (0x2UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */\n#define GPIO_AFRL_AFSEL6_2               (0x4UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */\n#define GPIO_AFRL_AFSEL6_3               (0x8UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */\n#define GPIO_AFRL_AFSEL7_Pos             (28U)\n#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */\n#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk\n#define GPIO_AFRL_AFSEL7_0               (0x1UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */\n#define GPIO_AFRL_AFSEL7_1               (0x2UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */\n#define GPIO_AFRL_AFSEL7_2               (0x4UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */\n#define GPIO_AFRL_AFSEL7_3               (0x8UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFSEL0\n#define GPIO_AFRL_AFRL0_0                GPIO_AFRL_AFSEL0_0\n#define GPIO_AFRL_AFRL0_1                GPIO_AFRL_AFSEL0_1\n#define GPIO_AFRL_AFRL0_2                GPIO_AFRL_AFSEL0_2\n#define GPIO_AFRL_AFRL0_3                GPIO_AFRL_AFSEL0_3\n#define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFSEL1\n#define GPIO_AFRL_AFRL1_0                GPIO_AFRL_AFSEL1_0\n#define GPIO_AFRL_AFRL1_1                GPIO_AFRL_AFSEL1_1\n#define GPIO_AFRL_AFRL1_2                GPIO_AFRL_AFSEL1_2\n#define GPIO_AFRL_AFRL1_3                GPIO_AFRL_AFSEL1_3\n#define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFSEL2\n#define GPIO_AFRL_AFRL2_0                GPIO_AFRL_AFSEL2_0\n#define GPIO_AFRL_AFRL2_1                GPIO_AFRL_AFSEL2_1\n#define GPIO_AFRL_AFRL2_2                GPIO_AFRL_AFSEL2_2\n#define GPIO_AFRL_AFRL2_3                GPIO_AFRL_AFSEL2_3\n#define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFSEL3\n#define GPIO_AFRL_AFRL3_0                GPIO_AFRL_AFSEL3_0\n#define GPIO_AFRL_AFRL3_1                GPIO_AFRL_AFSEL3_1\n#define GPIO_AFRL_AFRL3_2                GPIO_AFRL_AFSEL3_2\n#define GPIO_AFRL_AFRL3_3                GPIO_AFRL_AFSEL3_3\n#define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFSEL4\n#define GPIO_AFRL_AFRL4_0                GPIO_AFRL_AFSEL4_0\n#define GPIO_AFRL_AFRL4_1                GPIO_AFRL_AFSEL4_1\n#define GPIO_AFRL_AFRL4_2                GPIO_AFRL_AFSEL4_2\n#define GPIO_AFRL_AFRL4_3                GPIO_AFRL_AFSEL4_3\n#define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFSEL5\n#define GPIO_AFRL_AFRL5_0                GPIO_AFRL_AFSEL5_0\n#define GPIO_AFRL_AFRL5_1                GPIO_AFRL_AFSEL5_1\n#define GPIO_AFRL_AFRL5_2                GPIO_AFRL_AFSEL5_2\n#define GPIO_AFRL_AFRL5_3                GPIO_AFRL_AFSEL5_3\n#define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFSEL6\n#define GPIO_AFRL_AFRL6_0                GPIO_AFRL_AFSEL6_0\n#define GPIO_AFRL_AFRL6_1                GPIO_AFRL_AFSEL6_1\n#define GPIO_AFRL_AFRL6_2                GPIO_AFRL_AFSEL6_2\n#define GPIO_AFRL_AFRL6_3                GPIO_AFRL_AFSEL6_3\n#define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFSEL7\n#define GPIO_AFRL_AFRL7_0                GPIO_AFRL_AFSEL7_0\n#define GPIO_AFRL_AFRL7_1                GPIO_AFRL_AFSEL7_1\n#define GPIO_AFRL_AFRL7_2                GPIO_AFRL_AFSEL7_2\n#define GPIO_AFRL_AFRL7_3                GPIO_AFRL_AFSEL7_3\n\n/****************** Bit definition for GPIO_AFRH register *********************/\n#define GPIO_AFRH_AFSEL8_Pos             (0U)\n#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk\n#define GPIO_AFRH_AFSEL8_0               (0x1UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRH_AFSEL8_1               (0x2UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRH_AFSEL8_2               (0x4UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRH_AFSEL8_3               (0x8UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRH_AFSEL9_Pos             (4U)\n#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk\n#define GPIO_AFRH_AFSEL9_0               (0x1UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRH_AFSEL9_1               (0x2UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRH_AFSEL9_2               (0x4UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRH_AFSEL9_3               (0x8UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRH_AFSEL10_Pos            (8U)\n#define GPIO_AFRH_AFSEL10_Msk            (0xFUL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */\n#define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk\n#define GPIO_AFRH_AFSEL10_0              (0x1UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */\n#define GPIO_AFRH_AFSEL10_1              (0x2UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */\n#define GPIO_AFRH_AFSEL10_2              (0x4UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */\n#define GPIO_AFRH_AFSEL10_3              (0x8UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */\n#define GPIO_AFRH_AFSEL11_Pos            (12U)\n#define GPIO_AFRH_AFSEL11_Msk            (0xFUL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */\n#define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk\n#define GPIO_AFRH_AFSEL11_0              (0x1UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */\n#define GPIO_AFRH_AFSEL11_1              (0x2UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */\n#define GPIO_AFRH_AFSEL11_2              (0x4UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */\n#define GPIO_AFRH_AFSEL11_3              (0x8UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */\n#define GPIO_AFRH_AFSEL12_Pos            (16U)\n#define GPIO_AFRH_AFSEL12_Msk            (0xFUL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */\n#define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk\n#define GPIO_AFRH_AFSEL12_0              (0x1UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */\n#define GPIO_AFRH_AFSEL12_1              (0x2UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */\n#define GPIO_AFRH_AFSEL12_2              (0x4UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */\n#define GPIO_AFRH_AFSEL12_3              (0x8UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */\n#define GPIO_AFRH_AFSEL13_Pos            (20U)\n#define GPIO_AFRH_AFSEL13_Msk            (0xFUL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */\n#define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk\n#define GPIO_AFRH_AFSEL13_0              (0x1UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */\n#define GPIO_AFRH_AFSEL13_1              (0x2UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */\n#define GPIO_AFRH_AFSEL13_2              (0x4UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */\n#define GPIO_AFRH_AFSEL13_3              (0x8UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */\n#define GPIO_AFRH_AFSEL14_Pos            (24U)\n#define GPIO_AFRH_AFSEL14_Msk            (0xFUL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */\n#define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk\n#define GPIO_AFRH_AFSEL14_0              (0x1UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */\n#define GPIO_AFRH_AFSEL14_1              (0x2UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */\n#define GPIO_AFRH_AFSEL14_2              (0x4UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */\n#define GPIO_AFRH_AFSEL14_3              (0x8UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */\n#define GPIO_AFRH_AFSEL15_Pos            (28U)\n#define GPIO_AFRH_AFSEL15_Msk            (0xFUL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */\n#define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk\n#define GPIO_AFRH_AFSEL15_0              (0x1UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */\n#define GPIO_AFRH_AFSEL15_1              (0x2UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */\n#define GPIO_AFRH_AFSEL15_2              (0x4UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */\n#define GPIO_AFRH_AFSEL15_3              (0x8UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFSEL8\n#define GPIO_AFRH_AFRH0_0                GPIO_AFRH_AFSEL8_0\n#define GPIO_AFRH_AFRH0_1                GPIO_AFRH_AFSEL8_1\n#define GPIO_AFRH_AFRH0_2                GPIO_AFRH_AFSEL8_2\n#define GPIO_AFRH_AFRH0_3                GPIO_AFRH_AFSEL8_3\n#define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFSEL9\n#define GPIO_AFRH_AFRH1_0                GPIO_AFRH_AFSEL9_0\n#define GPIO_AFRH_AFRH1_1                GPIO_AFRH_AFSEL9_1\n#define GPIO_AFRH_AFRH1_2                GPIO_AFRH_AFSEL9_2\n#define GPIO_AFRH_AFRH1_3                GPIO_AFRH_AFSEL9_3\n#define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFSEL10\n#define GPIO_AFRH_AFRH2_0                GPIO_AFRH_AFSEL10_0\n#define GPIO_AFRH_AFRH2_1                GPIO_AFRH_AFSEL10_1\n#define GPIO_AFRH_AFRH2_2                GPIO_AFRH_AFSEL10_2\n#define GPIO_AFRH_AFRH2_3                GPIO_AFRH_AFSEL10_3\n#define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFSEL11\n#define GPIO_AFRH_AFRH3_0                GPIO_AFRH_AFSEL11_0\n#define GPIO_AFRH_AFRH3_1                GPIO_AFRH_AFSEL11_1\n#define GPIO_AFRH_AFRH3_2                GPIO_AFRH_AFSEL11_2\n#define GPIO_AFRH_AFRH3_3                GPIO_AFRH_AFSEL11_3\n#define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFSEL12\n#define GPIO_AFRH_AFRH4_0                GPIO_AFRH_AFSEL12_0\n#define GPIO_AFRH_AFRH4_1                GPIO_AFRH_AFSEL12_1\n#define GPIO_AFRH_AFRH4_2                GPIO_AFRH_AFSEL12_2\n#define GPIO_AFRH_AFRH4_3                GPIO_AFRH_AFSEL12_3\n#define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFSEL13\n#define GPIO_AFRH_AFRH5_0                GPIO_AFRH_AFSEL13_0\n#define GPIO_AFRH_AFRH5_1                GPIO_AFRH_AFSEL13_1\n#define GPIO_AFRH_AFRH5_2                GPIO_AFRH_AFSEL13_2\n#define GPIO_AFRH_AFRH5_3                GPIO_AFRH_AFSEL13_3\n#define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFSEL14\n#define GPIO_AFRH_AFRH6_0                GPIO_AFRH_AFSEL14_0\n#define GPIO_AFRH_AFRH6_1                GPIO_AFRH_AFSEL14_1\n#define GPIO_AFRH_AFRH6_2                GPIO_AFRH_AFSEL14_2\n#define GPIO_AFRH_AFRH6_3                GPIO_AFRH_AFSEL14_3\n#define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFSEL15\n#define GPIO_AFRH_AFRH7_0                GPIO_AFRH_AFSEL15_0\n#define GPIO_AFRH_AFRH7_1                GPIO_AFRH_AFSEL15_1\n#define GPIO_AFRH_AFRH7_2                GPIO_AFRH_AFSEL15_2\n#define GPIO_AFRH_AFRH7_3                GPIO_AFRH_AFSEL15_3\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Inter-integrated Circuit Interface                    */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for I2C_CR1 register  ********************/\n#define I2C_CR1_PE_Pos            (0U)\n#define I2C_CR1_PE_Msk            (0x1UL << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */\n#define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */\n#define I2C_CR1_SMBUS_Pos         (1U)\n#define I2C_CR1_SMBUS_Msk         (0x1UL << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */\n#define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */\n#define I2C_CR1_SMBTYPE_Pos       (3U)\n#define I2C_CR1_SMBTYPE_Msk       (0x1UL << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */\n#define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */\n#define I2C_CR1_ENARP_Pos         (4U)\n#define I2C_CR1_ENARP_Msk         (0x1UL << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */\n#define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */\n#define I2C_CR1_ENPEC_Pos         (5U)\n#define I2C_CR1_ENPEC_Msk         (0x1UL << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */\n#define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */\n#define I2C_CR1_ENGC_Pos          (6U)\n#define I2C_CR1_ENGC_Msk          (0x1UL << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */\n#define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */\n#define I2C_CR1_NOSTRETCH_Pos     (7U)\n#define I2C_CR1_NOSTRETCH_Msk     (0x1UL << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */\n#define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */\n#define I2C_CR1_START_Pos         (8U)\n#define I2C_CR1_START_Msk         (0x1UL << I2C_CR1_START_Pos)                  /*!< 0x00000100 */\n#define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */\n#define I2C_CR1_STOP_Pos          (9U)\n#define I2C_CR1_STOP_Msk          (0x1UL << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */\n#define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */\n#define I2C_CR1_ACK_Pos           (10U)\n#define I2C_CR1_ACK_Msk           (0x1UL << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */\n#define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */\n#define I2C_CR1_POS_Pos           (11U)\n#define I2C_CR1_POS_Msk           (0x1UL << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */\n#define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */\n#define I2C_CR1_PEC_Pos           (12U)\n#define I2C_CR1_PEC_Msk           (0x1UL << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */\n#define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */\n#define I2C_CR1_ALERT_Pos         (13U)\n#define I2C_CR1_ALERT_Msk         (0x1UL << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */\n#define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */\n#define I2C_CR1_SWRST_Pos         (15U)\n#define I2C_CR1_SWRST_Msk         (0x1UL << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */\n#define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */\n\n/*******************  Bit definition for I2C_CR2 register  ********************/\n#define I2C_CR2_FREQ_Pos          (0U)\n#define I2C_CR2_FREQ_Msk          (0x3FUL << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */\n#define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */\n#define I2C_CR2_FREQ_0            (0x01UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */\n#define I2C_CR2_FREQ_1            (0x02UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */\n#define I2C_CR2_FREQ_2            (0x04UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */\n#define I2C_CR2_FREQ_3            (0x08UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */\n#define I2C_CR2_FREQ_4            (0x10UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */\n#define I2C_CR2_FREQ_5            (0x20UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */\n\n#define I2C_CR2_ITERREN_Pos       (8U)\n#define I2C_CR2_ITERREN_Msk       (0x1UL << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */\n#define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */\n#define I2C_CR2_ITEVTEN_Pos       (9U)\n#define I2C_CR2_ITEVTEN_Msk       (0x1UL << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */\n#define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */\n#define I2C_CR2_ITBUFEN_Pos       (10U)\n#define I2C_CR2_ITBUFEN_Msk       (0x1UL << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */\n#define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */\n#define I2C_CR2_DMAEN_Pos         (11U)\n#define I2C_CR2_DMAEN_Msk         (0x1UL << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */\n#define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */\n#define I2C_CR2_LAST_Pos          (12U)\n#define I2C_CR2_LAST_Msk          (0x1UL << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */\n#define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */\n\n/*******************  Bit definition for I2C_OAR1 register  *******************/\n#define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */\n#define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */\n\n#define I2C_OAR1_ADD0_Pos         (0U)\n#define I2C_OAR1_ADD0_Msk         (0x1UL << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */\n#define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */\n#define I2C_OAR1_ADD1_Pos         (1U)\n#define I2C_OAR1_ADD1_Msk         (0x1UL << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */\n#define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */\n#define I2C_OAR1_ADD2_Pos         (2U)\n#define I2C_OAR1_ADD2_Msk         (0x1UL << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */\n#define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */\n#define I2C_OAR1_ADD3_Pos         (3U)\n#define I2C_OAR1_ADD3_Msk         (0x1UL << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */\n#define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */\n#define I2C_OAR1_ADD4_Pos         (4U)\n#define I2C_OAR1_ADD4_Msk         (0x1UL << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */\n#define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */\n#define I2C_OAR1_ADD5_Pos         (5U)\n#define I2C_OAR1_ADD5_Msk         (0x1UL << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */\n#define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */\n#define I2C_OAR1_ADD6_Pos         (6U)\n#define I2C_OAR1_ADD6_Msk         (0x1UL << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */\n#define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */\n#define I2C_OAR1_ADD7_Pos         (7U)\n#define I2C_OAR1_ADD7_Msk         (0x1UL << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */\n#define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */\n#define I2C_OAR1_ADD8_Pos         (8U)\n#define I2C_OAR1_ADD8_Msk         (0x1UL << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */\n#define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */\n#define I2C_OAR1_ADD9_Pos         (9U)\n#define I2C_OAR1_ADD9_Msk         (0x1UL << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */\n#define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */\n\n#define I2C_OAR1_ADDMODE_Pos      (15U)\n#define I2C_OAR1_ADDMODE_Msk      (0x1UL << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */\n#define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */\n\n/*******************  Bit definition for I2C_OAR2 register  *******************/\n#define I2C_OAR2_ENDUAL_Pos       (0U)\n#define I2C_OAR2_ENDUAL_Msk       (0x1UL << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */\n#define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */\n#define I2C_OAR2_ADD2_Pos         (1U)\n#define I2C_OAR2_ADD2_Msk         (0x7FUL << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */\n#define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */\n\n/********************  Bit definition for I2C_DR register  ********************/\n#define I2C_DR_DR_Pos             (0U)\n#define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */\n#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */\n\n/*******************  Bit definition for I2C_SR1 register  ********************/\n#define I2C_SR1_SB_Pos            (0U)\n#define I2C_SR1_SB_Msk            (0x1UL << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */\n#define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */\n#define I2C_SR1_ADDR_Pos          (1U)\n#define I2C_SR1_ADDR_Msk          (0x1UL << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */\n#define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */\n#define I2C_SR1_BTF_Pos           (2U)\n#define I2C_SR1_BTF_Msk           (0x1UL << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */\n#define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */\n#define I2C_SR1_ADD10_Pos         (3U)\n#define I2C_SR1_ADD10_Msk         (0x1UL << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */\n#define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */\n#define I2C_SR1_STOPF_Pos         (4U)\n#define I2C_SR1_STOPF_Msk         (0x1UL << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */\n#define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */\n#define I2C_SR1_RXNE_Pos          (6U)\n#define I2C_SR1_RXNE_Msk          (0x1UL << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */\n#define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */\n#define I2C_SR1_TXE_Pos           (7U)\n#define I2C_SR1_TXE_Msk           (0x1UL << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */\n#define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */\n#define I2C_SR1_BERR_Pos          (8U)\n#define I2C_SR1_BERR_Msk          (0x1UL << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */\n#define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */\n#define I2C_SR1_ARLO_Pos          (9U)\n#define I2C_SR1_ARLO_Msk          (0x1UL << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */\n#define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */\n#define I2C_SR1_AF_Pos            (10U)\n#define I2C_SR1_AF_Msk            (0x1UL << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */\n#define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */\n#define I2C_SR1_OVR_Pos           (11U)\n#define I2C_SR1_OVR_Msk           (0x1UL << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */\n#define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */\n#define I2C_SR1_PECERR_Pos        (12U)\n#define I2C_SR1_PECERR_Msk        (0x1UL << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */\n#define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */\n#define I2C_SR1_TIMEOUT_Pos       (14U)\n#define I2C_SR1_TIMEOUT_Msk       (0x1UL << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */\n#define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */\n#define I2C_SR1_SMBALERT_Pos      (15U)\n#define I2C_SR1_SMBALERT_Msk      (0x1UL << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */\n#define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */\n\n/*******************  Bit definition for I2C_SR2 register  ********************/\n#define I2C_SR2_MSL_Pos           (0U)\n#define I2C_SR2_MSL_Msk           (0x1UL << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */\n#define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */\n#define I2C_SR2_BUSY_Pos          (1U)\n#define I2C_SR2_BUSY_Msk          (0x1UL << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */\n#define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */\n#define I2C_SR2_TRA_Pos           (2U)\n#define I2C_SR2_TRA_Msk           (0x1UL << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */\n#define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */\n#define I2C_SR2_GENCALL_Pos       (4U)\n#define I2C_SR2_GENCALL_Msk       (0x1UL << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */\n#define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */\n#define I2C_SR2_SMBDEFAULT_Pos    (5U)\n#define I2C_SR2_SMBDEFAULT_Msk    (0x1UL << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */\n#define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */\n#define I2C_SR2_SMBHOST_Pos       (6U)\n#define I2C_SR2_SMBHOST_Msk       (0x1UL << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */\n#define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */\n#define I2C_SR2_DUALF_Pos         (7U)\n#define I2C_SR2_DUALF_Msk         (0x1UL << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */\n#define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */\n#define I2C_SR2_PEC_Pos           (8U)\n#define I2C_SR2_PEC_Msk           (0xFFUL << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */\n#define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */\n\n/*******************  Bit definition for I2C_CCR register  ********************/\n#define I2C_CCR_CCR_Pos           (0U)\n#define I2C_CCR_CCR_Msk           (0xFFFUL << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */\n#define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */\n#define I2C_CCR_DUTY_Pos          (14U)\n#define I2C_CCR_DUTY_Msk          (0x1UL << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */\n#define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */\n#define I2C_CCR_FS_Pos            (15U)\n#define I2C_CCR_FS_Msk            (0x1UL << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */\n#define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */\n\n/******************  Bit definition for I2C_TRISE register  *******************/\n#define I2C_TRISE_TRISE_Pos       (0U)\n#define I2C_TRISE_TRISE_Msk       (0x3FUL << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */\n#define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */\n\n/******************  Bit definition for I2C_FLTR register  *******************/\n#define I2C_FLTR_DNF_Pos          (0U)\n#define I2C_FLTR_DNF_Msk          (0xFUL << I2C_FLTR_DNF_Pos)                   /*!< 0x0000000F */\n#define I2C_FLTR_DNF              I2C_FLTR_DNF_Msk                             /*!<Digital Noise Filter */\n#define I2C_FLTR_ANOFF_Pos        (4U)\n#define I2C_FLTR_ANOFF_Msk        (0x1UL << I2C_FLTR_ANOFF_Pos)                 /*!< 0x00000010 */\n#define I2C_FLTR_ANOFF            I2C_FLTR_ANOFF_Msk                           /*!<Analog Noise Filter OFF */\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Independent WATCHDOG                             */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define IWDG_KR_KEY_Pos     (0U)\n#define IWDG_KR_KEY_Msk     (0xFFFFUL << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */\n#define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */\n\n/*******************  Bit definition for IWDG_PR register  ********************/\n#define IWDG_PR_PR_Pos      (0U)\n#define IWDG_PR_PR_Msk      (0x7UL << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */\n#define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */\n#define IWDG_PR_PR_0        (0x1UL << IWDG_PR_PR_Pos)                           /*!< 0x01 */\n#define IWDG_PR_PR_1        (0x2UL << IWDG_PR_PR_Pos)                           /*!< 0x02 */\n#define IWDG_PR_PR_2        (0x4UL << IWDG_PR_PR_Pos)                           /*!< 0x04 */\n\n/*******************  Bit definition for IWDG_RLR register  *******************/\n#define IWDG_RLR_RL_Pos     (0U)\n#define IWDG_RLR_RL_Msk     (0xFFFUL << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */\n#define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */\n\n/*******************  Bit definition for IWDG_SR register  ********************/\n#define IWDG_SR_PVU_Pos     (0U)\n#define IWDG_SR_PVU_Msk     (0x1UL << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */\n#define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */\n#define IWDG_SR_RVU_Pos     (1U)\n#define IWDG_SR_RVU_Msk     (0x1UL << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */\n#define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                             Power Control                                  */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for PWR_CR register  ********************/\n#define PWR_CR_LPDS_Pos        (0U)\n#define PWR_CR_LPDS_Msk        (0x1UL << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */\n#define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */\n#define PWR_CR_PDDS_Pos        (1U)\n#define PWR_CR_PDDS_Msk        (0x1UL << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */\n#define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */\n#define PWR_CR_CWUF_Pos        (2U)\n#define PWR_CR_CWUF_Msk        (0x1UL << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */\n#define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */\n#define PWR_CR_CSBF_Pos        (3U)\n#define PWR_CR_CSBF_Msk        (0x1UL << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */\n#define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */\n#define PWR_CR_PVDE_Pos        (4U)\n#define PWR_CR_PVDE_Msk        (0x1UL << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */\n#define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */\n\n#define PWR_CR_PLS_Pos         (5U)\n#define PWR_CR_PLS_Msk         (0x7UL << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */\n#define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */\n#define PWR_CR_PLS_0           (0x1UL << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */\n#define PWR_CR_PLS_1           (0x2UL << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */\n#define PWR_CR_PLS_2           (0x4UL << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */\n\n/*!< PVD level configuration */\n#define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */\n#define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */\n#define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */\n#define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */\n#define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */\n#define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */\n#define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */\n#define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */\n#define PWR_CR_DBP_Pos         (8U)\n#define PWR_CR_DBP_Msk         (0x1UL << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */\n#define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */\n#define PWR_CR_FPDS_Pos        (9U)\n#define PWR_CR_FPDS_Msk        (0x1UL << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */\n#define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */\n#define PWR_CR_LPLVDS_Pos      (10U)\n#define PWR_CR_LPLVDS_Msk      (0x1UL << PWR_CR_LPLVDS_Pos)                     /*!< 0x00000400 */\n#define PWR_CR_LPLVDS          PWR_CR_LPLVDS_Msk                               /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */\n#define PWR_CR_MRLVDS_Pos      (11U)\n#define PWR_CR_MRLVDS_Msk      (0x1UL << PWR_CR_MRLVDS_Pos)                     /*!< 0x00000800 */\n#define PWR_CR_MRLVDS          PWR_CR_MRLVDS_Msk                               /*!< Main Regulator Low Voltage in Deep Sleep mode              */\n#define PWR_CR_ADCDC1_Pos      (13U)\n#define PWR_CR_ADCDC1_Msk      (0x1UL << PWR_CR_ADCDC1_Pos)                     /*!< 0x00002000 */\n#define PWR_CR_ADCDC1          PWR_CR_ADCDC1_Msk                               /*!< Refer to AN4073 on how to use this bit                     */\n#define PWR_CR_VOS_Pos         (14U)\n#define PWR_CR_VOS_Msk         (0x3UL << PWR_CR_VOS_Pos)                        /*!< 0x0000C000 */\n#define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\n#define PWR_CR_VOS_0           0x00004000U                                     /*!< Bit 0 */\n#define PWR_CR_VOS_1           0x00008000U                                     /*!< Bit 1 */\n#define PWR_CR_FMSSR_Pos       (20U)\n#define PWR_CR_FMSSR_Msk       (0x1UL << PWR_CR_FMSSR_Pos)                      /*!< 0x00100000 */\n#define PWR_CR_FMSSR           PWR_CR_FMSSR_Msk                                /*!< Flash Memory Sleep System Run        */\n#define PWR_CR_FISSR_Pos       (21U)\n#define PWR_CR_FISSR_Msk       (0x1UL << PWR_CR_FISSR_Pos)                      /*!< 0x00200000 */\n#define PWR_CR_FISSR           PWR_CR_FISSR_Msk                                /*!< Flash Interface Stop while System Run */\n\n/* Legacy define */\n#define  PWR_CR_PMODE                        PWR_CR_VOS\n\n/*******************  Bit definition for PWR_CSR register  ********************/\n#define PWR_CSR_WUF_Pos        (0U)\n#define PWR_CSR_WUF_Msk        (0x1UL << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */\n#define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */\n#define PWR_CSR_SBF_Pos        (1U)\n#define PWR_CSR_SBF_Msk        (0x1UL << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */\n#define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */\n#define PWR_CSR_PVDO_Pos       (2U)\n#define PWR_CSR_PVDO_Msk       (0x1UL << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */\n#define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */\n#define PWR_CSR_BRR_Pos        (3U)\n#define PWR_CSR_BRR_Msk        (0x1UL << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */\n#define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */\n#define PWR_CSR_EWUP_Pos       (8U)\n#define PWR_CSR_EWUP_Msk       (0x1UL << PWR_CSR_EWUP_Pos)                      /*!< 0x00000100 */\n#define PWR_CSR_EWUP           PWR_CSR_EWUP_Msk                                /*!< Enable WKUP pin                                  */\n#define PWR_CSR_BRE_Pos        (9U)\n#define PWR_CSR_BRE_Msk        (0x1UL << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */\n#define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */\n#define PWR_CSR_VOSRDY_Pos     (14U)\n#define PWR_CSR_VOSRDY_Msk     (0x1UL << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */\n#define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */\n\n/* Legacy define */\n#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Reset and Clock Control                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for RCC_CR register  ********************/\n#define RCC_CR_HSION_Pos                   (0U)\n#define RCC_CR_HSION_Msk                   (0x1UL << RCC_CR_HSION_Pos)          /*!< 0x00000001 */\n#define RCC_CR_HSION                       RCC_CR_HSION_Msk\n#define RCC_CR_HSIRDY_Pos                  (1U)\n#define RCC_CR_HSIRDY_Msk                  (0x1UL << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */\n#define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk\n\n#define RCC_CR_HSITRIM_Pos                 (3U)\n#define RCC_CR_HSITRIM_Msk                 (0x1FUL << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */\n#define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk\n#define RCC_CR_HSITRIM_0                   (0x01UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */\n#define RCC_CR_HSITRIM_1                   (0x02UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */\n#define RCC_CR_HSITRIM_2                   (0x04UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */\n#define RCC_CR_HSITRIM_3                   (0x08UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */\n#define RCC_CR_HSITRIM_4                   (0x10UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */\n\n#define RCC_CR_HSICAL_Pos                  (8U)\n#define RCC_CR_HSICAL_Msk                  (0xFFUL << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */\n#define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk\n#define RCC_CR_HSICAL_0                    (0x01UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */\n#define RCC_CR_HSICAL_1                    (0x02UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */\n#define RCC_CR_HSICAL_2                    (0x04UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */\n#define RCC_CR_HSICAL_3                    (0x08UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */\n#define RCC_CR_HSICAL_4                    (0x10UL << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */\n#define RCC_CR_HSICAL_5                    (0x20UL << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */\n#define RCC_CR_HSICAL_6                    (0x40UL << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */\n#define RCC_CR_HSICAL_7                    (0x80UL << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */\n\n#define RCC_CR_HSEON_Pos                   (16U)\n#define RCC_CR_HSEON_Msk                   (0x1UL << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */\n#define RCC_CR_HSEON                       RCC_CR_HSEON_Msk\n#define RCC_CR_HSERDY_Pos                  (17U)\n#define RCC_CR_HSERDY_Msk                  (0x1UL << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */\n#define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk\n#define RCC_CR_HSEBYP_Pos                  (18U)\n#define RCC_CR_HSEBYP_Msk                  (0x1UL << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */\n#define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk\n#define RCC_CR_CSSON_Pos                   (19U)\n#define RCC_CR_CSSON_Msk                   (0x1UL << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */\n#define RCC_CR_CSSON                       RCC_CR_CSSON_Msk\n#define RCC_CR_PLLON_Pos                   (24U)\n#define RCC_CR_PLLON_Msk                   (0x1UL << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */\n#define RCC_CR_PLLON                       RCC_CR_PLLON_Msk\n#define RCC_CR_PLLRDY_Pos                  (25U)\n#define RCC_CR_PLLRDY_Msk                  (0x1UL << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */\n#define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_PLLI2S_SUPPORT                                                     /*!< Support PLLI2S oscillator */\n\n#define RCC_CR_PLLI2SON_Pos                (26U)\n#define RCC_CR_PLLI2SON_Msk                (0x1UL << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */\n#define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk\n#define RCC_CR_PLLI2SRDY_Pos               (27U)\n#define RCC_CR_PLLI2SRDY_Msk               (0x1UL << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */\n#define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk\n\n/********************  Bit definition for RCC_PLLCFGR register  ***************/\n#define RCC_PLLCFGR_PLLM_Pos               (0U)\n#define RCC_PLLCFGR_PLLM_Msk               (0x3FUL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */\n#define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk\n#define RCC_PLLCFGR_PLLM_0                 (0x01UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */\n#define RCC_PLLCFGR_PLLM_1                 (0x02UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */\n#define RCC_PLLCFGR_PLLM_2                 (0x04UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */\n#define RCC_PLLCFGR_PLLM_3                 (0x08UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */\n#define RCC_PLLCFGR_PLLM_4                 (0x10UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */\n#define RCC_PLLCFGR_PLLM_5                 (0x20UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */\n\n#define RCC_PLLCFGR_PLLN_Pos               (6U)\n#define RCC_PLLCFGR_PLLN_Msk               (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */\n#define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk\n#define RCC_PLLCFGR_PLLN_0                 (0x001UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */\n#define RCC_PLLCFGR_PLLN_1                 (0x002UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */\n#define RCC_PLLCFGR_PLLN_2                 (0x004UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */\n#define RCC_PLLCFGR_PLLN_3                 (0x008UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */\n#define RCC_PLLCFGR_PLLN_4                 (0x010UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */\n#define RCC_PLLCFGR_PLLN_5                 (0x020UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */\n#define RCC_PLLCFGR_PLLN_6                 (0x040UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */\n#define RCC_PLLCFGR_PLLN_7                 (0x080UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */\n#define RCC_PLLCFGR_PLLN_8                 (0x100UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */\n\n#define RCC_PLLCFGR_PLLP_Pos               (16U)\n#define RCC_PLLCFGR_PLLP_Msk               (0x3UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */\n#define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk\n#define RCC_PLLCFGR_PLLP_0                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */\n#define RCC_PLLCFGR_PLLP_1                 (0x2UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */\n\n#define RCC_PLLCFGR_PLLSRC_Pos             (22U)\n#define RCC_PLLCFGR_PLLSRC_Msk             (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk\n#define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)\n#define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk\n#define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U\n\n#define RCC_PLLCFGR_PLLQ_Pos               (24U)\n#define RCC_PLLCFGR_PLLQ_Msk               (0xFUL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */\n#define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk\n#define RCC_PLLCFGR_PLLQ_0                 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */\n#define RCC_PLLCFGR_PLLQ_1                 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */\n#define RCC_PLLCFGR_PLLQ_2                 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */\n#define RCC_PLLCFGR_PLLQ_3                 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */\n\n\n/********************  Bit definition for RCC_CFGR register  ******************/\n/*!< SW configuration */\n#define RCC_CFGR_SW_Pos                    (0U)\n#define RCC_CFGR_SW_Msk                    (0x3UL << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */\n#define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */\n#define RCC_CFGR_SW_0                      (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */\n#define RCC_CFGR_SW_1                      (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */\n\n#define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */\n#define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */\n#define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */\n\n/*!< SWS configuration */\n#define RCC_CFGR_SWS_Pos                   (2U)\n#define RCC_CFGR_SWS_Msk                   (0x3UL << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */\n#define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */\n#define RCC_CFGR_SWS_0                     (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */\n#define RCC_CFGR_SWS_1                     (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */\n\n#define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */\n#define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */\n#define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */\n\n/*!< HPRE configuration */\n#define RCC_CFGR_HPRE_Pos                  (4U)\n#define RCC_CFGR_HPRE_Msk                  (0xFUL << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */\n#define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */\n#define RCC_CFGR_HPRE_0                    (0x1UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */\n#define RCC_CFGR_HPRE_1                    (0x2UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */\n#define RCC_CFGR_HPRE_2                    (0x4UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */\n#define RCC_CFGR_HPRE_3                    (0x8UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */\n\n#define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */\n#define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */\n#define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */\n#define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */\n#define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */\n#define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */\n#define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */\n#define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */\n#define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */\n\n/*!< PPRE1 configuration */\n#define RCC_CFGR_PPRE1_Pos                 (10U)\n#define RCC_CFGR_PPRE1_Msk                 (0x7UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */\n#define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */\n#define RCC_CFGR_PPRE1_0                   (0x1UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */\n#define RCC_CFGR_PPRE1_1                   (0x2UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */\n#define RCC_CFGR_PPRE1_2                   (0x4UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */\n\n#define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */\n\n/*!< PPRE2 configuration */\n#define RCC_CFGR_PPRE2_Pos                 (13U)\n#define RCC_CFGR_PPRE2_Msk                 (0x7UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */\n#define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */\n#define RCC_CFGR_PPRE2_0                   (0x1UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */\n#define RCC_CFGR_PPRE2_1                   (0x2UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */\n#define RCC_CFGR_PPRE2_2                   (0x4UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */\n\n#define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */\n\n/*!< RTCPRE configuration */\n#define RCC_CFGR_RTCPRE_Pos                (16U)\n#define RCC_CFGR_RTCPRE_Msk                (0x1FUL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */\n#define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk\n#define RCC_CFGR_RTCPRE_0                  (0x01UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */\n#define RCC_CFGR_RTCPRE_1                  (0x02UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */\n#define RCC_CFGR_RTCPRE_2                  (0x04UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */\n#define RCC_CFGR_RTCPRE_3                  (0x08UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */\n#define RCC_CFGR_RTCPRE_4                  (0x10UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */\n\n/*!< MCO1 configuration */\n#define RCC_CFGR_MCO1_Pos                  (21U)\n#define RCC_CFGR_MCO1_Msk                  (0x3UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */\n#define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk\n#define RCC_CFGR_MCO1_0                    (0x1UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */\n#define RCC_CFGR_MCO1_1                    (0x2UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */\n\n#define RCC_CFGR_I2SSRC_Pos                (23U)\n#define RCC_CFGR_I2SSRC_Msk                (0x1UL << RCC_CFGR_I2SSRC_Pos)       /*!< 0x00800000 */\n#define RCC_CFGR_I2SSRC                    RCC_CFGR_I2SSRC_Msk\n\n#define RCC_CFGR_MCO1PRE_Pos               (24U)\n#define RCC_CFGR_MCO1PRE_Msk               (0x7UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */\n#define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk\n#define RCC_CFGR_MCO1PRE_0                 (0x1UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */\n#define RCC_CFGR_MCO1PRE_1                 (0x2UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */\n#define RCC_CFGR_MCO1PRE_2                 (0x4UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */\n\n#define RCC_CFGR_MCO2PRE_Pos               (27U)\n#define RCC_CFGR_MCO2PRE_Msk               (0x7UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */\n#define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk\n#define RCC_CFGR_MCO2PRE_0                 (0x1UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */\n#define RCC_CFGR_MCO2PRE_1                 (0x2UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */\n#define RCC_CFGR_MCO2PRE_2                 (0x4UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */\n\n#define RCC_CFGR_MCO2_Pos                  (30U)\n#define RCC_CFGR_MCO2_Msk                  (0x3UL << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */\n#define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk\n#define RCC_CFGR_MCO2_0                    (0x1UL << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */\n#define RCC_CFGR_MCO2_1                    (0x2UL << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */\n\n/********************  Bit definition for RCC_CIR register  *******************/\n#define RCC_CIR_LSIRDYF_Pos                (0U)\n#define RCC_CIR_LSIRDYF_Msk                (0x1UL << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */\n#define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk\n#define RCC_CIR_LSERDYF_Pos                (1U)\n#define RCC_CIR_LSERDYF_Msk                (0x1UL << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */\n#define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk\n#define RCC_CIR_HSIRDYF_Pos                (2U)\n#define RCC_CIR_HSIRDYF_Msk                (0x1UL << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */\n#define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk\n#define RCC_CIR_HSERDYF_Pos                (3U)\n#define RCC_CIR_HSERDYF_Msk                (0x1UL << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */\n#define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk\n#define RCC_CIR_PLLRDYF_Pos                (4U)\n#define RCC_CIR_PLLRDYF_Msk                (0x1UL << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */\n#define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk\n#define RCC_CIR_PLLI2SRDYF_Pos             (5U)\n#define RCC_CIR_PLLI2SRDYF_Msk             (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */\n#define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk\n\n#define RCC_CIR_CSSF_Pos                   (7U)\n#define RCC_CIR_CSSF_Msk                   (0x1UL << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */\n#define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk\n#define RCC_CIR_LSIRDYIE_Pos               (8U)\n#define RCC_CIR_LSIRDYIE_Msk               (0x1UL << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */\n#define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk\n#define RCC_CIR_LSERDYIE_Pos               (9U)\n#define RCC_CIR_LSERDYIE_Msk               (0x1UL << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */\n#define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk\n#define RCC_CIR_HSIRDYIE_Pos               (10U)\n#define RCC_CIR_HSIRDYIE_Msk               (0x1UL << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */\n#define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk\n#define RCC_CIR_HSERDYIE_Pos               (11U)\n#define RCC_CIR_HSERDYIE_Msk               (0x1UL << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */\n#define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk\n#define RCC_CIR_PLLRDYIE_Pos               (12U)\n#define RCC_CIR_PLLRDYIE_Msk               (0x1UL << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */\n#define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk\n#define RCC_CIR_PLLI2SRDYIE_Pos            (13U)\n#define RCC_CIR_PLLI2SRDYIE_Msk            (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */\n#define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk\n\n#define RCC_CIR_LSIRDYC_Pos                (16U)\n#define RCC_CIR_LSIRDYC_Msk                (0x1UL << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */\n#define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk\n#define RCC_CIR_LSERDYC_Pos                (17U)\n#define RCC_CIR_LSERDYC_Msk                (0x1UL << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */\n#define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk\n#define RCC_CIR_HSIRDYC_Pos                (18U)\n#define RCC_CIR_HSIRDYC_Msk                (0x1UL << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */\n#define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk\n#define RCC_CIR_HSERDYC_Pos                (19U)\n#define RCC_CIR_HSERDYC_Msk                (0x1UL << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */\n#define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk\n#define RCC_CIR_PLLRDYC_Pos                (20U)\n#define RCC_CIR_PLLRDYC_Msk                (0x1UL << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */\n#define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk\n#define RCC_CIR_PLLI2SRDYC_Pos             (21U)\n#define RCC_CIR_PLLI2SRDYC_Msk             (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */\n#define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk\n\n#define RCC_CIR_CSSC_Pos                   (23U)\n#define RCC_CIR_CSSC_Msk                   (0x1UL << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */\n#define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk\n\n/********************  Bit definition for RCC_AHB1RSTR register  **************/\n#define RCC_AHB1RSTR_GPIOARST_Pos          (0U)\n#define RCC_AHB1RSTR_GPIOARST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */\n#define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk\n#define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)\n#define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */\n#define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk\n#define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)\n#define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */\n#define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk\n#define RCC_AHB1RSTR_GPIODRST_Pos          (3U)\n#define RCC_AHB1RSTR_GPIODRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */\n#define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk\n#define RCC_AHB1RSTR_GPIOERST_Pos          (4U)\n#define RCC_AHB1RSTR_GPIOERST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */\n#define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk\n#define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)\n#define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk\n#define RCC_AHB1RSTR_CRCRST_Pos            (12U)\n#define RCC_AHB1RSTR_CRCRST_Msk            (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */\n#define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk\n#define RCC_AHB1RSTR_DMA1RST_Pos           (21U)\n#define RCC_AHB1RSTR_DMA1RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */\n#define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk\n#define RCC_AHB1RSTR_DMA2RST_Pos           (22U)\n#define RCC_AHB1RSTR_DMA2RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */\n#define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk\n\n/********************  Bit definition for RCC_AHB2RSTR register  **************/\n#define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)\n#define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk\n/********************  Bit definition for RCC_AHB3RSTR register  **************/\n\n\n/********************  Bit definition for RCC_APB1RSTR register  **************/\n#define RCC_APB1RSTR_TIM2RST_Pos           (0U)\n#define RCC_APB1RSTR_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk\n#define RCC_APB1RSTR_TIM3RST_Pos           (1U)\n#define RCC_APB1RSTR_TIM3RST_Msk           (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk\n#define RCC_APB1RSTR_TIM4RST_Pos           (2U)\n#define RCC_APB1RSTR_TIM4RST_Msk           (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */\n#define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk\n#define RCC_APB1RSTR_TIM5RST_Pos           (3U)\n#define RCC_APB1RSTR_TIM5RST_Msk           (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */\n#define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk\n#define RCC_APB1RSTR_WWDGRST_Pos           (11U)\n#define RCC_APB1RSTR_WWDGRST_Msk           (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */\n#define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk\n#define RCC_APB1RSTR_SPI2RST_Pos           (14U)\n#define RCC_APB1RSTR_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */\n#define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk\n#define RCC_APB1RSTR_SPI3RST_Pos           (15U)\n#define RCC_APB1RSTR_SPI3RST_Msk           (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */\n#define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk\n#define RCC_APB1RSTR_USART2RST_Pos         (17U)\n#define RCC_APB1RSTR_USART2RST_Msk         (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */\n#define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk\n#define RCC_APB1RSTR_I2C1RST_Pos           (21U)\n#define RCC_APB1RSTR_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */\n#define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk\n#define RCC_APB1RSTR_I2C2RST_Pos           (22U)\n#define RCC_APB1RSTR_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */\n#define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk\n#define RCC_APB1RSTR_I2C3RST_Pos           (23U)\n#define RCC_APB1RSTR_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */\n#define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk\n#define RCC_APB1RSTR_PWRRST_Pos            (28U)\n#define RCC_APB1RSTR_PWRRST_Msk            (0x1UL << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */\n#define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk\n\n/********************  Bit definition for RCC_APB2RSTR register  **************/\n#define RCC_APB2RSTR_TIM1RST_Pos           (0U)\n#define RCC_APB2RSTR_TIM1RST_Msk           (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk\n#define RCC_APB2RSTR_USART1RST_Pos         (4U)\n#define RCC_APB2RSTR_USART1RST_Msk         (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */\n#define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk\n#define RCC_APB2RSTR_USART6RST_Pos         (5U)\n#define RCC_APB2RSTR_USART6RST_Msk         (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */\n#define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk\n#define RCC_APB2RSTR_ADCRST_Pos            (8U)\n#define RCC_APB2RSTR_ADCRST_Msk            (0x1UL << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */\n#define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk\n#define RCC_APB2RSTR_SDIORST_Pos           (11U)\n#define RCC_APB2RSTR_SDIORST_Msk           (0x1UL << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */\n#define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk\n#define RCC_APB2RSTR_SPI1RST_Pos           (12U)\n#define RCC_APB2RSTR_SPI1RST_Msk           (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */\n#define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk\n#define RCC_APB2RSTR_SPI4RST_Pos           (13U)\n#define RCC_APB2RSTR_SPI4RST_Msk           (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)  /*!< 0x00002000 */\n#define RCC_APB2RSTR_SPI4RST               RCC_APB2RSTR_SPI4RST_Msk\n#define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)\n#define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */\n#define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk\n#define RCC_APB2RSTR_TIM9RST_Pos           (16U)\n#define RCC_APB2RSTR_TIM9RST_Msk           (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */\n#define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk\n#define RCC_APB2RSTR_TIM10RST_Pos          (17U)\n#define RCC_APB2RSTR_TIM10RST_Msk          (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */\n#define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk\n#define RCC_APB2RSTR_TIM11RST_Pos          (18U)\n#define RCC_APB2RSTR_TIM11RST_Msk          (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */\n#define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk\n#define RCC_APB2RSTR_SPI5RST_Pos           (20U)\n#define RCC_APB2RSTR_SPI5RST_Msk           (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)  /*!< 0x00100000 */\n#define RCC_APB2RSTR_SPI5RST               RCC_APB2RSTR_SPI5RST_Msk\n\n/* Old SPI1RST bit definition, maintained for legacy purpose */\n#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST\n\n/********************  Bit definition for RCC_AHB1ENR register  ***************/\n#define RCC_AHB1ENR_GPIOAEN_Pos            (0U)\n#define RCC_AHB1ENR_GPIOAEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */\n#define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk\n#define RCC_AHB1ENR_GPIOBEN_Pos            (1U)\n#define RCC_AHB1ENR_GPIOBEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */\n#define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk\n#define RCC_AHB1ENR_GPIOCEN_Pos            (2U)\n#define RCC_AHB1ENR_GPIOCEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */\n#define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk\n#define RCC_AHB1ENR_GPIODEN_Pos            (3U)\n#define RCC_AHB1ENR_GPIODEN_Msk            (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */\n#define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk\n#define RCC_AHB1ENR_GPIOEEN_Pos            (4U)\n#define RCC_AHB1ENR_GPIOEEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */\n#define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk\n#define RCC_AHB1ENR_GPIOHEN_Pos            (7U)\n#define RCC_AHB1ENR_GPIOHEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk\n#define RCC_AHB1ENR_CRCEN_Pos              (12U)\n#define RCC_AHB1ENR_CRCEN_Msk              (0x1UL << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */\n#define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk\n#define RCC_AHB1ENR_DMA1EN_Pos             (21U)\n#define RCC_AHB1ENR_DMA1EN_Msk             (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */\n#define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk\n#define RCC_AHB1ENR_DMA2EN_Pos             (22U)\n#define RCC_AHB1ENR_DMA2EN_Msk             (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */\n#define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk\n/********************  Bit definition for RCC_AHB2ENR register  ***************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_AHB2_SUPPORT                   /*!< AHB2 Bus is supported */\n\n#define RCC_AHB2ENR_OTGFSEN_Pos            (7U)\n#define RCC_AHB2ENR_OTGFSEN_Msk            (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk\n\n/********************  Bit definition for RCC_APB1ENR register  ***************/\n#define RCC_APB1ENR_TIM2EN_Pos             (0U)\n#define RCC_APB1ENR_TIM2EN_Msk             (0x1UL << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk\n#define RCC_APB1ENR_TIM3EN_Pos             (1U)\n#define RCC_APB1ENR_TIM3EN_Msk             (0x1UL << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk\n#define RCC_APB1ENR_TIM4EN_Pos             (2U)\n#define RCC_APB1ENR_TIM4EN_Msk             (0x1UL << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */\n#define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk\n#define RCC_APB1ENR_TIM5EN_Pos             (3U)\n#define RCC_APB1ENR_TIM5EN_Msk             (0x1UL << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */\n#define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk\n#define RCC_APB1ENR_WWDGEN_Pos             (11U)\n#define RCC_APB1ENR_WWDGEN_Msk             (0x1UL << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk\n#define RCC_APB1ENR_SPI2EN_Pos             (14U)\n#define RCC_APB1ENR_SPI2EN_Msk             (0x1UL << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */\n#define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk\n#define RCC_APB1ENR_SPI3EN_Pos             (15U)\n#define RCC_APB1ENR_SPI3EN_Msk             (0x1UL << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */\n#define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk\n#define RCC_APB1ENR_USART2EN_Pos           (17U)\n#define RCC_APB1ENR_USART2EN_Msk           (0x1UL << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */\n#define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk\n#define RCC_APB1ENR_I2C1EN_Pos             (21U)\n#define RCC_APB1ENR_I2C1EN_Msk             (0x1UL << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */\n#define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk\n#define RCC_APB1ENR_I2C2EN_Pos             (22U)\n#define RCC_APB1ENR_I2C2EN_Msk             (0x1UL << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */\n#define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk\n#define RCC_APB1ENR_I2C3EN_Pos             (23U)\n#define RCC_APB1ENR_I2C3EN_Msk             (0x1UL << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */\n#define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk\n#define RCC_APB1ENR_PWREN_Pos              (28U)\n#define RCC_APB1ENR_PWREN_Msk              (0x1UL << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */\n#define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk\n\n/********************  Bit definition for RCC_APB2ENR register  ***************/\n#define RCC_APB2ENR_TIM1EN_Pos             (0U)\n#define RCC_APB2ENR_TIM1EN_Msk             (0x1UL << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk\n#define RCC_APB2ENR_USART1EN_Pos           (4U)\n#define RCC_APB2ENR_USART1EN_Msk           (0x1UL << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */\n#define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk\n#define RCC_APB2ENR_USART6EN_Pos           (5U)\n#define RCC_APB2ENR_USART6EN_Msk           (0x1UL << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */\n#define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk\n#define RCC_APB2ENR_ADC1EN_Pos             (8U)\n#define RCC_APB2ENR_ADC1EN_Msk             (0x1UL << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */\n#define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk\n#define RCC_APB2ENR_SDIOEN_Pos             (11U)\n#define RCC_APB2ENR_SDIOEN_Msk             (0x1UL << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk\n#define RCC_APB2ENR_SPI1EN_Pos             (12U)\n#define RCC_APB2ENR_SPI1EN_Msk             (0x1UL << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */\n#define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk\n#define RCC_APB2ENR_SPI4EN_Pos             (13U)\n#define RCC_APB2ENR_SPI4EN_Msk             (0x1UL << RCC_APB2ENR_SPI4EN_Pos)    /*!< 0x00002000 */\n#define RCC_APB2ENR_SPI4EN                 RCC_APB2ENR_SPI4EN_Msk\n#define RCC_APB2ENR_SYSCFGEN_Pos           (14U)\n#define RCC_APB2ENR_SYSCFGEN_Msk           (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */\n#define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk\n#define RCC_APB2ENR_TIM9EN_Pos             (16U)\n#define RCC_APB2ENR_TIM9EN_Msk             (0x1UL << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */\n#define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk\n#define RCC_APB2ENR_TIM10EN_Pos            (17U)\n#define RCC_APB2ENR_TIM10EN_Msk            (0x1UL << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */\n#define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk\n#define RCC_APB2ENR_TIM11EN_Pos            (18U)\n#define RCC_APB2ENR_TIM11EN_Msk            (0x1UL << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */\n#define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk\n#define RCC_APB2ENR_SPI5EN_Pos             (20U)\n#define RCC_APB2ENR_SPI5EN_Msk             (0x1UL << RCC_APB2ENR_SPI5EN_Pos)    /*!< 0x00100000 */\n#define RCC_APB2ENR_SPI5EN                 RCC_APB2ENR_SPI5EN_Msk\n\n/********************  Bit definition for RCC_AHB1LPENR register  *************/\n#define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)\n#define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk\n#define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)\n#define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk\n#define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)\n#define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */\n#define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk\n#define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)\n#define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */\n#define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk\n#define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)\n#define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */\n#define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk\n#define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)\n#define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk\n#define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)\n#define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */\n#define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk\n#define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)\n#define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */\n#define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk\n#define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)\n#define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */\n#define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk\n#define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)\n#define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk\n#define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)\n#define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk\n\n\n/********************  Bit definition for RCC_AHB2LPENR register  *************/\n#define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)\n#define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk\n\n/********************  Bit definition for RCC_AHB3LPENR register  *************/\n\n/********************  Bit definition for RCC_APB1LPENR register  *************/\n#define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)\n#define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk\n#define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)\n#define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk\n#define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)\n#define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */\n#define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk\n#define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)\n#define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */\n#define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk\n#define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)\n#define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk\n#define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)\n#define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk\n#define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)\n#define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */\n#define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk\n#define RCC_APB1LPENR_USART2LPEN_Pos       (17U)\n#define RCC_APB1LPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk\n#define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)\n#define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk\n#define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)\n#define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk\n#define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)\n#define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */\n#define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk\n#define RCC_APB1LPENR_PWRLPEN_Pos          (28U)\n#define RCC_APB1LPENR_PWRLPEN_Msk          (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */\n#define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk\n\n/********************  Bit definition for RCC_APB2LPENR register  *************/\n#define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)\n#define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk\n#define RCC_APB2LPENR_USART1LPEN_Pos       (4U)\n#define RCC_APB2LPENR_USART1LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk\n#define RCC_APB2LPENR_USART6LPEN_Pos       (5U)\n#define RCC_APB2LPENR_USART6LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk\n#define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)\n#define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk\n#define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)\n#define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk\n#define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)\n#define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */\n#define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk\n#define RCC_APB2LPENR_SPI4LPEN_Pos         (13U)\n#define RCC_APB2LPENR_SPI4LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */\n#define RCC_APB2LPENR_SPI4LPEN             RCC_APB2LPENR_SPI4LPEN_Msk\n#define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)\n#define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk\n#define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)\n#define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */\n#define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk\n#define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)\n#define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk\n#define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)\n#define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk\n#define RCC_APB2LPENR_SPI5LPEN_Pos         (20U)\n#define RCC_APB2LPENR_SPI5LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */\n#define RCC_APB2LPENR_SPI5LPEN             RCC_APB2LPENR_SPI5LPEN_Msk\n\n/********************  Bit definition for RCC_BDCR register  ******************/\n#define RCC_BDCR_LSEON_Pos                 (0U)\n#define RCC_BDCR_LSEON_Msk                 (0x1UL << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */\n#define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk\n#define RCC_BDCR_LSERDY_Pos                (1U)\n#define RCC_BDCR_LSERDY_Msk                (0x1UL << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */\n#define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk\n#define RCC_BDCR_LSEBYP_Pos                (2U)\n#define RCC_BDCR_LSEBYP_Msk                (0x1UL << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */\n#define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk\n#define RCC_BDCR_LSEMOD_Pos                (3U)\n#define RCC_BDCR_LSEMOD_Msk                (0x1UL << RCC_BDCR_LSEMOD_Pos)       /*!< 0x00000008 */\n#define RCC_BDCR_LSEMOD                    RCC_BDCR_LSEMOD_Msk\n\n#define RCC_BDCR_RTCSEL_Pos                (8U)\n#define RCC_BDCR_RTCSEL_Msk                (0x3UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */\n#define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk\n#define RCC_BDCR_RTCSEL_0                  (0x1UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */\n#define RCC_BDCR_RTCSEL_1                  (0x2UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */\n\n#define RCC_BDCR_RTCEN_Pos                 (15U)\n#define RCC_BDCR_RTCEN_Msk                 (0x1UL << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */\n#define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk\n#define RCC_BDCR_BDRST_Pos                 (16U)\n#define RCC_BDCR_BDRST_Msk                 (0x1UL << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */\n#define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk\n\n/********************  Bit definition for RCC_CSR register  *******************/\n#define RCC_CSR_LSION_Pos                  (0U)\n#define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */\n#define RCC_CSR_LSION                      RCC_CSR_LSION_Msk\n#define RCC_CSR_LSIRDY_Pos                 (1U)\n#define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */\n#define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk\n#define RCC_CSR_RMVF_Pos                   (24U)\n#define RCC_CSR_RMVF_Msk                   (0x1UL << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */\n#define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk\n#define RCC_CSR_BORRSTF_Pos                (25U)\n#define RCC_CSR_BORRSTF_Msk                (0x1UL << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */\n#define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk\n#define RCC_CSR_PINRSTF_Pos                (26U)\n#define RCC_CSR_PINRSTF_Msk                (0x1UL << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */\n#define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk\n#define RCC_CSR_PORRSTF_Pos                (27U)\n#define RCC_CSR_PORRSTF_Msk                (0x1UL << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */\n#define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk\n#define RCC_CSR_SFTRSTF_Pos                (28U)\n#define RCC_CSR_SFTRSTF_Msk                (0x1UL << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */\n#define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk\n#define RCC_CSR_IWDGRSTF_Pos               (29U)\n#define RCC_CSR_IWDGRSTF_Msk               (0x1UL << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */\n#define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk\n#define RCC_CSR_WWDGRSTF_Pos               (30U)\n#define RCC_CSR_WWDGRSTF_Msk               (0x1UL << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */\n#define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk\n#define RCC_CSR_LPWRRSTF_Pos               (31U)\n#define RCC_CSR_LPWRRSTF_Msk               (0x1UL << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */\n#define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk\n/* Legacy defines */\n#define RCC_CSR_PADRSTF                    RCC_CSR_PINRSTF\n#define RCC_CSR_WDGRSTF                    RCC_CSR_IWDGRSTF\n\n/********************  Bit definition for RCC_SSCGR register  *****************/\n#define RCC_SSCGR_MODPER_Pos               (0U)\n#define RCC_SSCGR_MODPER_Msk               (0x1FFFUL << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */\n#define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk\n#define RCC_SSCGR_INCSTEP_Pos              (13U)\n#define RCC_SSCGR_INCSTEP_Msk              (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */\n#define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk\n#define RCC_SSCGR_SPREADSEL_Pos            (30U)\n#define RCC_SSCGR_SPREADSEL_Msk            (0x1UL << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */\n#define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk\n#define RCC_SSCGR_SSCGEN_Pos               (31U)\n#define RCC_SSCGR_SSCGEN_Msk               (0x1UL << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */\n#define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk\n\n/********************  Bit definition for RCC_PLLI2SCFGR register  ************/\n#define RCC_PLLI2SCFGR_PLLI2SM_Pos         (0U)\n#define RCC_PLLI2SCFGR_PLLI2SM_Msk         (0x3FUL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */\n#define RCC_PLLI2SCFGR_PLLI2SM             RCC_PLLI2SCFGR_PLLI2SM_Msk\n#define RCC_PLLI2SCFGR_PLLI2SM_0           (0x01UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */\n#define RCC_PLLI2SCFGR_PLLI2SM_1           (0x02UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */\n#define RCC_PLLI2SCFGR_PLLI2SM_2           (0x04UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */\n#define RCC_PLLI2SCFGR_PLLI2SM_3           (0x08UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */\n#define RCC_PLLI2SCFGR_PLLI2SM_4           (0x10UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */\n#define RCC_PLLI2SCFGR_PLLI2SM_5           (0x20UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */\n\n#define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)\n#define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */\n#define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk\n#define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */\n#define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */\n#define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */\n#define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */\n#define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */\n#define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */\n#define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */\n\n#define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)\n#define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk\n#define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for RCC_DCKCFGR register  ***************/\n\n#define RCC_DCKCFGR_TIMPRE_Pos             (24U)\n#define RCC_DCKCFGR_TIMPRE_Msk             (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)    /*!< 0x01000000 */\n#define RCC_DCKCFGR_TIMPRE                 RCC_DCKCFGR_TIMPRE_Msk\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Real-Time Clock (RTC)                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RTC_TR register  *******************/\n#define RTC_TR_PM_Pos                 (22U)\n#define RTC_TR_PM_Msk                 (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */\n#define RTC_TR_PM                     RTC_TR_PM_Msk\n#define RTC_TR_HT_Pos                 (20U)\n#define RTC_TR_HT_Msk                 (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */\n#define RTC_TR_HT                     RTC_TR_HT_Msk\n#define RTC_TR_HT_0                   (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */\n#define RTC_TR_HT_1                   (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */\n#define RTC_TR_HU_Pos                 (16U)\n#define RTC_TR_HU_Msk                 (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */\n#define RTC_TR_HU                     RTC_TR_HU_Msk\n#define RTC_TR_HU_0                   (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */\n#define RTC_TR_HU_1                   (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */\n#define RTC_TR_HU_2                   (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */\n#define RTC_TR_HU_3                   (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */\n#define RTC_TR_MNT_Pos                (12U)\n#define RTC_TR_MNT_Msk                (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */\n#define RTC_TR_MNT                    RTC_TR_MNT_Msk\n#define RTC_TR_MNT_0                  (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */\n#define RTC_TR_MNT_1                  (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */\n#define RTC_TR_MNT_2                  (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */\n#define RTC_TR_MNU_Pos                (8U)\n#define RTC_TR_MNU_Msk                (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */\n#define RTC_TR_MNU                    RTC_TR_MNU_Msk\n#define RTC_TR_MNU_0                  (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */\n#define RTC_TR_MNU_1                  (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */\n#define RTC_TR_MNU_2                  (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */\n#define RTC_TR_MNU_3                  (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */\n#define RTC_TR_ST_Pos                 (4U)\n#define RTC_TR_ST_Msk                 (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */\n#define RTC_TR_ST                     RTC_TR_ST_Msk\n#define RTC_TR_ST_0                   (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */\n#define RTC_TR_ST_1                   (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */\n#define RTC_TR_ST_2                   (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */\n#define RTC_TR_SU_Pos                 (0U)\n#define RTC_TR_SU_Msk                 (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */\n#define RTC_TR_SU                     RTC_TR_SU_Msk\n#define RTC_TR_SU_0                   (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */\n#define RTC_TR_SU_1                   (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */\n#define RTC_TR_SU_2                   (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */\n#define RTC_TR_SU_3                   (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_DR register  *******************/\n#define RTC_DR_YT_Pos                 (20U)\n#define RTC_DR_YT_Msk                 (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */\n#define RTC_DR_YT                     RTC_DR_YT_Msk\n#define RTC_DR_YT_0                   (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */\n#define RTC_DR_YT_1                   (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */\n#define RTC_DR_YT_2                   (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */\n#define RTC_DR_YT_3                   (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */\n#define RTC_DR_YU_Pos                 (16U)\n#define RTC_DR_YU_Msk                 (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */\n#define RTC_DR_YU                     RTC_DR_YU_Msk\n#define RTC_DR_YU_0                   (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */\n#define RTC_DR_YU_1                   (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */\n#define RTC_DR_YU_2                   (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */\n#define RTC_DR_YU_3                   (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */\n#define RTC_DR_WDU_Pos                (13U)\n#define RTC_DR_WDU_Msk                (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */\n#define RTC_DR_WDU                    RTC_DR_WDU_Msk\n#define RTC_DR_WDU_0                  (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */\n#define RTC_DR_WDU_1                  (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */\n#define RTC_DR_WDU_2                  (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */\n#define RTC_DR_MT_Pos                 (12U)\n#define RTC_DR_MT_Msk                 (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */\n#define RTC_DR_MT                     RTC_DR_MT_Msk\n#define RTC_DR_MU_Pos                 (8U)\n#define RTC_DR_MU_Msk                 (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */\n#define RTC_DR_MU                     RTC_DR_MU_Msk\n#define RTC_DR_MU_0                   (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */\n#define RTC_DR_MU_1                   (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */\n#define RTC_DR_MU_2                   (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */\n#define RTC_DR_MU_3                   (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */\n#define RTC_DR_DT_Pos                 (4U)\n#define RTC_DR_DT_Msk                 (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */\n#define RTC_DR_DT                     RTC_DR_DT_Msk\n#define RTC_DR_DT_0                   (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */\n#define RTC_DR_DT_1                   (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */\n#define RTC_DR_DU_Pos                 (0U)\n#define RTC_DR_DU_Msk                 (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */\n#define RTC_DR_DU                     RTC_DR_DU_Msk\n#define RTC_DR_DU_0                   (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */\n#define RTC_DR_DU_1                   (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */\n#define RTC_DR_DU_2                   (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */\n#define RTC_DR_DU_3                   (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_CR register  *******************/\n#define RTC_CR_COE_Pos                (23U)\n#define RTC_CR_COE_Msk                (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */\n#define RTC_CR_COE                    RTC_CR_COE_Msk\n#define RTC_CR_OSEL_Pos               (21U)\n#define RTC_CR_OSEL_Msk               (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */\n#define RTC_CR_OSEL                   RTC_CR_OSEL_Msk\n#define RTC_CR_OSEL_0                 (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */\n#define RTC_CR_OSEL_1                 (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */\n#define RTC_CR_POL_Pos                (20U)\n#define RTC_CR_POL_Msk                (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */\n#define RTC_CR_POL                    RTC_CR_POL_Msk\n#define RTC_CR_COSEL_Pos              (19U)\n#define RTC_CR_COSEL_Msk              (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */\n#define RTC_CR_COSEL                  RTC_CR_COSEL_Msk\n#define RTC_CR_BKP_Pos                 (18U)\n#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */\n#define RTC_CR_BKP                     RTC_CR_BKP_Msk\n#define RTC_CR_SUB1H_Pos              (17U)\n#define RTC_CR_SUB1H_Msk              (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */\n#define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk\n#define RTC_CR_ADD1H_Pos              (16U)\n#define RTC_CR_ADD1H_Msk              (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */\n#define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk\n#define RTC_CR_TSIE_Pos               (15U)\n#define RTC_CR_TSIE_Msk               (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */\n#define RTC_CR_TSIE                   RTC_CR_TSIE_Msk\n#define RTC_CR_WUTIE_Pos              (14U)\n#define RTC_CR_WUTIE_Msk              (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */\n#define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk\n#define RTC_CR_ALRBIE_Pos             (13U)\n#define RTC_CR_ALRBIE_Msk             (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */\n#define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk\n#define RTC_CR_ALRAIE_Pos             (12U)\n#define RTC_CR_ALRAIE_Msk             (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */\n#define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk\n#define RTC_CR_TSE_Pos                (11U)\n#define RTC_CR_TSE_Msk                (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */\n#define RTC_CR_TSE                    RTC_CR_TSE_Msk\n#define RTC_CR_WUTE_Pos               (10U)\n#define RTC_CR_WUTE_Msk               (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */\n#define RTC_CR_WUTE                   RTC_CR_WUTE_Msk\n#define RTC_CR_ALRBE_Pos              (9U)\n#define RTC_CR_ALRBE_Msk              (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */\n#define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk\n#define RTC_CR_ALRAE_Pos              (8U)\n#define RTC_CR_ALRAE_Msk              (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */\n#define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk\n#define RTC_CR_DCE_Pos                (7U)\n#define RTC_CR_DCE_Msk                (0x1UL << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */\n#define RTC_CR_DCE                    RTC_CR_DCE_Msk\n#define RTC_CR_FMT_Pos                (6U)\n#define RTC_CR_FMT_Msk                (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */\n#define RTC_CR_FMT                    RTC_CR_FMT_Msk\n#define RTC_CR_BYPSHAD_Pos            (5U)\n#define RTC_CR_BYPSHAD_Msk            (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */\n#define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk\n#define RTC_CR_REFCKON_Pos            (4U)\n#define RTC_CR_REFCKON_Msk            (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */\n#define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk\n#define RTC_CR_TSEDGE_Pos             (3U)\n#define RTC_CR_TSEDGE_Msk             (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */\n#define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk\n#define RTC_CR_WUCKSEL_Pos            (0U)\n#define RTC_CR_WUCKSEL_Msk            (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */\n#define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk\n#define RTC_CR_WUCKSEL_0              (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */\n#define RTC_CR_WUCKSEL_1              (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */\n#define RTC_CR_WUCKSEL_2              (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */\n\n/* Legacy defines */\n#define RTC_CR_BCK                     RTC_CR_BKP\n\n/********************  Bits definition for RTC_ISR register  ******************/\n#define RTC_ISR_RECALPF_Pos           (16U)\n#define RTC_ISR_RECALPF_Msk           (0x1UL << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */\n#define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk\n#define RTC_ISR_TAMP1F_Pos            (13U)\n#define RTC_ISR_TAMP1F_Msk            (0x1UL << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */\n#define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk\n#define RTC_ISR_TAMP2F_Pos            (14U)\n#define RTC_ISR_TAMP2F_Msk            (0x1UL << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */\n#define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk\n#define RTC_ISR_TSOVF_Pos             (12U)\n#define RTC_ISR_TSOVF_Msk             (0x1UL << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */\n#define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk\n#define RTC_ISR_TSF_Pos               (11U)\n#define RTC_ISR_TSF_Msk               (0x1UL << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */\n#define RTC_ISR_TSF                   RTC_ISR_TSF_Msk\n#define RTC_ISR_WUTF_Pos              (10U)\n#define RTC_ISR_WUTF_Msk              (0x1UL << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */\n#define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk\n#define RTC_ISR_ALRBF_Pos             (9U)\n#define RTC_ISR_ALRBF_Msk             (0x1UL << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */\n#define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk\n#define RTC_ISR_ALRAF_Pos             (8U)\n#define RTC_ISR_ALRAF_Msk             (0x1UL << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */\n#define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk\n#define RTC_ISR_INIT_Pos              (7U)\n#define RTC_ISR_INIT_Msk              (0x1UL << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */\n#define RTC_ISR_INIT                  RTC_ISR_INIT_Msk\n#define RTC_ISR_INITF_Pos             (6U)\n#define RTC_ISR_INITF_Msk             (0x1UL << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */\n#define RTC_ISR_INITF                 RTC_ISR_INITF_Msk\n#define RTC_ISR_RSF_Pos               (5U)\n#define RTC_ISR_RSF_Msk               (0x1UL << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */\n#define RTC_ISR_RSF                   RTC_ISR_RSF_Msk\n#define RTC_ISR_INITS_Pos             (4U)\n#define RTC_ISR_INITS_Msk             (0x1UL << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */\n#define RTC_ISR_INITS                 RTC_ISR_INITS_Msk\n#define RTC_ISR_SHPF_Pos              (3U)\n#define RTC_ISR_SHPF_Msk              (0x1UL << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */\n#define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk\n#define RTC_ISR_WUTWF_Pos             (2U)\n#define RTC_ISR_WUTWF_Msk             (0x1UL << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */\n#define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk\n#define RTC_ISR_ALRBWF_Pos            (1U)\n#define RTC_ISR_ALRBWF_Msk            (0x1UL << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */\n#define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk\n#define RTC_ISR_ALRAWF_Pos            (0U)\n#define RTC_ISR_ALRAWF_Msk            (0x1UL << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */\n#define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk\n\n/********************  Bits definition for RTC_PRER register  *****************/\n#define RTC_PRER_PREDIV_A_Pos         (16U)\n#define RTC_PRER_PREDIV_A_Msk         (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */\n#define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk\n#define RTC_PRER_PREDIV_S_Pos         (0U)\n#define RTC_PRER_PREDIV_S_Msk         (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */\n#define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk\n\n/********************  Bits definition for RTC_WUTR register  *****************/\n#define RTC_WUTR_WUT_Pos              (0U)\n#define RTC_WUTR_WUT_Msk              (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */\n#define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk\n\n/********************  Bits definition for RTC_CALIBR register  ***************/\n#define RTC_CALIBR_DCS_Pos            (7U)\n#define RTC_CALIBR_DCS_Msk            (0x1UL << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */\n#define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk\n#define RTC_CALIBR_DC_Pos             (0U)\n#define RTC_CALIBR_DC_Msk             (0x1FUL << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */\n#define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk\n\n/********************  Bits definition for RTC_ALRMAR register  ***************/\n#define RTC_ALRMAR_MSK4_Pos           (31U)\n#define RTC_ALRMAR_MSK4_Msk           (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk\n#define RTC_ALRMAR_WDSEL_Pos          (30U)\n#define RTC_ALRMAR_WDSEL_Msk          (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk\n#define RTC_ALRMAR_DT_Pos             (28U)\n#define RTC_ALRMAR_DT_Msk             (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk\n#define RTC_ALRMAR_DT_0               (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMAR_DT_1               (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMAR_DU_Pos             (24U)\n#define RTC_ALRMAR_DU_Msk             (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk\n#define RTC_ALRMAR_DU_0               (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMAR_DU_1               (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMAR_DU_2               (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMAR_DU_3               (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMAR_MSK3_Pos           (23U)\n#define RTC_ALRMAR_MSK3_Msk           (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk\n#define RTC_ALRMAR_PM_Pos             (22U)\n#define RTC_ALRMAR_PM_Msk             (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk\n#define RTC_ALRMAR_HT_Pos             (20U)\n#define RTC_ALRMAR_HT_Msk             (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk\n#define RTC_ALRMAR_HT_0               (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMAR_HT_1               (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMAR_HU_Pos             (16U)\n#define RTC_ALRMAR_HU_Msk             (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk\n#define RTC_ALRMAR_HU_0               (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMAR_HU_1               (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMAR_HU_2               (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMAR_HU_3               (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMAR_MSK2_Pos           (15U)\n#define RTC_ALRMAR_MSK2_Msk           (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk\n#define RTC_ALRMAR_MNT_Pos            (12U)\n#define RTC_ALRMAR_MNT_Msk            (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk\n#define RTC_ALRMAR_MNT_0              (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMAR_MNT_1              (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMAR_MNT_2              (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMAR_MNU_Pos            (8U)\n#define RTC_ALRMAR_MNU_Msk            (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk\n#define RTC_ALRMAR_MNU_0              (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMAR_MNU_1              (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMAR_MNU_2              (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMAR_MNU_3              (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMAR_MSK1_Pos           (7U)\n#define RTC_ALRMAR_MSK1_Msk           (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk\n#define RTC_ALRMAR_ST_Pos             (4U)\n#define RTC_ALRMAR_ST_Msk             (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk\n#define RTC_ALRMAR_ST_0               (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMAR_ST_1               (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMAR_ST_2               (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMAR_SU_Pos             (0U)\n#define RTC_ALRMAR_SU_Msk             (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk\n#define RTC_ALRMAR_SU_0               (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMAR_SU_1               (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMAR_SU_2               (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMAR_SU_3               (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_ALRMBR register  ***************/\n#define RTC_ALRMBR_MSK4_Pos           (31U)\n#define RTC_ALRMBR_MSK4_Msk           (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk\n#define RTC_ALRMBR_WDSEL_Pos          (30U)\n#define RTC_ALRMBR_WDSEL_Msk          (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk\n#define RTC_ALRMBR_DT_Pos             (28U)\n#define RTC_ALRMBR_DT_Msk             (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk\n#define RTC_ALRMBR_DT_0               (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMBR_DT_1               (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMBR_DU_Pos             (24U)\n#define RTC_ALRMBR_DU_Msk             (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk\n#define RTC_ALRMBR_DU_0               (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMBR_DU_1               (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMBR_DU_2               (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMBR_DU_3               (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMBR_MSK3_Pos           (23U)\n#define RTC_ALRMBR_MSK3_Msk           (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk\n#define RTC_ALRMBR_PM_Pos             (22U)\n#define RTC_ALRMBR_PM_Msk             (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk\n#define RTC_ALRMBR_HT_Pos             (20U)\n#define RTC_ALRMBR_HT_Msk             (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk\n#define RTC_ALRMBR_HT_0               (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMBR_HT_1               (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMBR_HU_Pos             (16U)\n#define RTC_ALRMBR_HU_Msk             (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk\n#define RTC_ALRMBR_HU_0               (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMBR_HU_1               (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMBR_HU_2               (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMBR_HU_3               (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMBR_MSK2_Pos           (15U)\n#define RTC_ALRMBR_MSK2_Msk           (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk\n#define RTC_ALRMBR_MNT_Pos            (12U)\n#define RTC_ALRMBR_MNT_Msk            (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk\n#define RTC_ALRMBR_MNT_0              (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMBR_MNT_1              (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMBR_MNT_2              (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMBR_MNU_Pos            (8U)\n#define RTC_ALRMBR_MNU_Msk            (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk\n#define RTC_ALRMBR_MNU_0              (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMBR_MNU_1              (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMBR_MNU_2              (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMBR_MNU_3              (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMBR_MSK1_Pos           (7U)\n#define RTC_ALRMBR_MSK1_Msk           (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk\n#define RTC_ALRMBR_ST_Pos             (4U)\n#define RTC_ALRMBR_ST_Msk             (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk\n#define RTC_ALRMBR_ST_0               (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMBR_ST_1               (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMBR_ST_2               (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMBR_SU_Pos             (0U)\n#define RTC_ALRMBR_SU_Msk             (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk\n#define RTC_ALRMBR_SU_0               (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMBR_SU_1               (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMBR_SU_2               (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMBR_SU_3               (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_WPR register  ******************/\n#define RTC_WPR_KEY_Pos               (0U)\n#define RTC_WPR_KEY_Msk               (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */\n#define RTC_WPR_KEY                   RTC_WPR_KEY_Msk\n\n/********************  Bits definition for RTC_SSR register  ******************/\n#define RTC_SSR_SS_Pos                (0U)\n#define RTC_SSR_SS_Msk                (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */\n#define RTC_SSR_SS                    RTC_SSR_SS_Msk\n\n/********************  Bits definition for RTC_SHIFTR register  ***************/\n#define RTC_SHIFTR_SUBFS_Pos          (0U)\n#define RTC_SHIFTR_SUBFS_Msk          (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */\n#define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk\n#define RTC_SHIFTR_ADD1S_Pos          (31U)\n#define RTC_SHIFTR_ADD1S_Msk          (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */\n#define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk\n\n/********************  Bits definition for RTC_TSTR register  *****************/\n#define RTC_TSTR_PM_Pos               (22U)\n#define RTC_TSTR_PM_Msk               (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */\n#define RTC_TSTR_PM                   RTC_TSTR_PM_Msk\n#define RTC_TSTR_HT_Pos               (20U)\n#define RTC_TSTR_HT_Msk               (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */\n#define RTC_TSTR_HT                   RTC_TSTR_HT_Msk\n#define RTC_TSTR_HT_0                 (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */\n#define RTC_TSTR_HT_1                 (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */\n#define RTC_TSTR_HU_Pos               (16U)\n#define RTC_TSTR_HU_Msk               (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */\n#define RTC_TSTR_HU                   RTC_TSTR_HU_Msk\n#define RTC_TSTR_HU_0                 (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */\n#define RTC_TSTR_HU_1                 (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */\n#define RTC_TSTR_HU_2                 (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */\n#define RTC_TSTR_HU_3                 (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */\n#define RTC_TSTR_MNT_Pos              (12U)\n#define RTC_TSTR_MNT_Msk              (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */\n#define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk\n#define RTC_TSTR_MNT_0                (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */\n#define RTC_TSTR_MNT_1                (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */\n#define RTC_TSTR_MNT_2                (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */\n#define RTC_TSTR_MNU_Pos              (8U)\n#define RTC_TSTR_MNU_Msk              (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */\n#define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk\n#define RTC_TSTR_MNU_0                (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */\n#define RTC_TSTR_MNU_1                (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */\n#define RTC_TSTR_MNU_2                (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */\n#define RTC_TSTR_MNU_3                (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */\n#define RTC_TSTR_ST_Pos               (4U)\n#define RTC_TSTR_ST_Msk               (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */\n#define RTC_TSTR_ST                   RTC_TSTR_ST_Msk\n#define RTC_TSTR_ST_0                 (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */\n#define RTC_TSTR_ST_1                 (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */\n#define RTC_TSTR_ST_2                 (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */\n#define RTC_TSTR_SU_Pos               (0U)\n#define RTC_TSTR_SU_Msk               (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */\n#define RTC_TSTR_SU                   RTC_TSTR_SU_Msk\n#define RTC_TSTR_SU_0                 (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */\n#define RTC_TSTR_SU_1                 (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */\n#define RTC_TSTR_SU_2                 (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */\n#define RTC_TSTR_SU_3                 (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSDR register  *****************/\n#define RTC_TSDR_WDU_Pos              (13U)\n#define RTC_TSDR_WDU_Msk              (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */\n#define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk\n#define RTC_TSDR_WDU_0                (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */\n#define RTC_TSDR_WDU_1                (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */\n#define RTC_TSDR_WDU_2                (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */\n#define RTC_TSDR_MT_Pos               (12U)\n#define RTC_TSDR_MT_Msk               (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */\n#define RTC_TSDR_MT                   RTC_TSDR_MT_Msk\n#define RTC_TSDR_MU_Pos               (8U)\n#define RTC_TSDR_MU_Msk               (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */\n#define RTC_TSDR_MU                   RTC_TSDR_MU_Msk\n#define RTC_TSDR_MU_0                 (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */\n#define RTC_TSDR_MU_1                 (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */\n#define RTC_TSDR_MU_2                 (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */\n#define RTC_TSDR_MU_3                 (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */\n#define RTC_TSDR_DT_Pos               (4U)\n#define RTC_TSDR_DT_Msk               (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */\n#define RTC_TSDR_DT                   RTC_TSDR_DT_Msk\n#define RTC_TSDR_DT_0                 (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */\n#define RTC_TSDR_DT_1                 (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */\n#define RTC_TSDR_DU_Pos               (0U)\n#define RTC_TSDR_DU_Msk               (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */\n#define RTC_TSDR_DU                   RTC_TSDR_DU_Msk\n#define RTC_TSDR_DU_0                 (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */\n#define RTC_TSDR_DU_1                 (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */\n#define RTC_TSDR_DU_2                 (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */\n#define RTC_TSDR_DU_3                 (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSSSR register  ****************/\n#define RTC_TSSSR_SS_Pos              (0U)\n#define RTC_TSSSR_SS_Msk              (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */\n#define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk\n\n/********************  Bits definition for RTC_CAL register  *****************/\n#define RTC_CALR_CALP_Pos             (15U)\n#define RTC_CALR_CALP_Msk             (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */\n#define RTC_CALR_CALP                 RTC_CALR_CALP_Msk\n#define RTC_CALR_CALW8_Pos            (14U)\n#define RTC_CALR_CALW8_Msk            (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */\n#define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk\n#define RTC_CALR_CALW16_Pos           (13U)\n#define RTC_CALR_CALW16_Msk           (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */\n#define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk\n#define RTC_CALR_CALM_Pos             (0U)\n#define RTC_CALR_CALM_Msk             (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */\n#define RTC_CALR_CALM                 RTC_CALR_CALM_Msk\n#define RTC_CALR_CALM_0               (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */\n#define RTC_CALR_CALM_1               (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */\n#define RTC_CALR_CALM_2               (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */\n#define RTC_CALR_CALM_3               (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */\n#define RTC_CALR_CALM_4               (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */\n#define RTC_CALR_CALM_5               (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */\n#define RTC_CALR_CALM_6               (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */\n#define RTC_CALR_CALM_7               (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */\n#define RTC_CALR_CALM_8               (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */\n\n/********************  Bits definition for RTC_TAFCR register  ****************/\n#define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)\n#define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */\n#define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk\n#define RTC_TAFCR_TSINSEL_Pos         (17U)\n#define RTC_TAFCR_TSINSEL_Msk         (0x1UL << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */\n#define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk\n#define RTC_TAFCR_TAMP1INSEL_Pos      (16U)\n#define RTC_TAFCR_TAMP1INSEL_Msk      (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)        /*!< 0x00010000 */\n#define RTC_TAFCR_TAMP1INSEL          RTC_TAFCR_TAMP1INSEL_Msk\n#define RTC_TAFCR_TAMPPUDIS_Pos       (15U)\n#define RTC_TAFCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */\n#define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk\n#define RTC_TAFCR_TAMPPRCH_Pos        (13U)\n#define RTC_TAFCR_TAMPPRCH_Msk        (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */\n#define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk\n#define RTC_TAFCR_TAMPPRCH_0          (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */\n#define RTC_TAFCR_TAMPPRCH_1          (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */\n#define RTC_TAFCR_TAMPFLT_Pos         (11U)\n#define RTC_TAFCR_TAMPFLT_Msk         (0x3UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */\n#define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk\n#define RTC_TAFCR_TAMPFLT_0           (0x1UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */\n#define RTC_TAFCR_TAMPFLT_1           (0x2UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */\n#define RTC_TAFCR_TAMPFREQ_Pos        (8U)\n#define RTC_TAFCR_TAMPFREQ_Msk        (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */\n#define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk\n#define RTC_TAFCR_TAMPFREQ_0          (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */\n#define RTC_TAFCR_TAMPFREQ_1          (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */\n#define RTC_TAFCR_TAMPFREQ_2          (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */\n#define RTC_TAFCR_TAMPTS_Pos          (7U)\n#define RTC_TAFCR_TAMPTS_Msk          (0x1UL << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */\n#define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk\n#define RTC_TAFCR_TAMP2TRG_Pos        (4U)\n#define RTC_TAFCR_TAMP2TRG_Msk        (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */\n#define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk\n#define RTC_TAFCR_TAMP2E_Pos          (3U)\n#define RTC_TAFCR_TAMP2E_Msk          (0x1UL << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */\n#define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk\n#define RTC_TAFCR_TAMPIE_Pos          (2U)\n#define RTC_TAFCR_TAMPIE_Msk          (0x1UL << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */\n#define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk\n#define RTC_TAFCR_TAMP1TRG_Pos        (1U)\n#define RTC_TAFCR_TAMP1TRG_Msk        (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */\n#define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk\n#define RTC_TAFCR_TAMP1E_Pos          (0U)\n#define RTC_TAFCR_TAMP1E_Msk          (0x1UL << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */\n#define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk\n\n/* Legacy defines */\n#define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMP1INSEL\n\n/********************  Bits definition for RTC_ALRMASSR register  *************/\n#define RTC_ALRMASSR_MASKSS_Pos       (24U)\n#define RTC_ALRMASSR_MASKSS_Msk       (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk\n#define RTC_ALRMASSR_MASKSS_0         (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMASSR_MASKSS_1         (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMASSR_MASKSS_2         (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMASSR_MASKSS_3         (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMASSR_SS_Pos           (0U)\n#define RTC_ALRMASSR_SS_Msk           (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk\n\n/********************  Bits definition for RTC_ALRMBSSR register  *************/\n#define RTC_ALRMBSSR_MASKSS_Pos       (24U)\n#define RTC_ALRMBSSR_MASKSS_Msk       (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk\n#define RTC_ALRMBSSR_MASKSS_0         (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMBSSR_MASKSS_1         (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMBSSR_MASKSS_2         (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMBSSR_MASKSS_3         (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMBSSR_SS_Pos           (0U)\n#define RTC_ALRMBSSR_SS_Msk           (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk\n\n/********************  Bits definition for RTC_BKP0R register  ****************/\n#define RTC_BKP0R_Pos                 (0U)\n#define RTC_BKP0R_Msk                 (0xFFFFFFFFUL << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP0R                     RTC_BKP0R_Msk\n\n/********************  Bits definition for RTC_BKP1R register  ****************/\n#define RTC_BKP1R_Pos                 (0U)\n#define RTC_BKP1R_Msk                 (0xFFFFFFFFUL << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP1R                     RTC_BKP1R_Msk\n\n/********************  Bits definition for RTC_BKP2R register  ****************/\n#define RTC_BKP2R_Pos                 (0U)\n#define RTC_BKP2R_Msk                 (0xFFFFFFFFUL << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP2R                     RTC_BKP2R_Msk\n\n/********************  Bits definition for RTC_BKP3R register  ****************/\n#define RTC_BKP3R_Pos                 (0U)\n#define RTC_BKP3R_Msk                 (0xFFFFFFFFUL << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP3R                     RTC_BKP3R_Msk\n\n/********************  Bits definition for RTC_BKP4R register  ****************/\n#define RTC_BKP4R_Pos                 (0U)\n#define RTC_BKP4R_Msk                 (0xFFFFFFFFUL << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP4R                     RTC_BKP4R_Msk\n\n/********************  Bits definition for RTC_BKP5R register  ****************/\n#define RTC_BKP5R_Pos                 (0U)\n#define RTC_BKP5R_Msk                 (0xFFFFFFFFUL << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP5R                     RTC_BKP5R_Msk\n\n/********************  Bits definition for RTC_BKP6R register  ****************/\n#define RTC_BKP6R_Pos                 (0U)\n#define RTC_BKP6R_Msk                 (0xFFFFFFFFUL << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP6R                     RTC_BKP6R_Msk\n\n/********************  Bits definition for RTC_BKP7R register  ****************/\n#define RTC_BKP7R_Pos                 (0U)\n#define RTC_BKP7R_Msk                 (0xFFFFFFFFUL << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP7R                     RTC_BKP7R_Msk\n\n/********************  Bits definition for RTC_BKP8R register  ****************/\n#define RTC_BKP8R_Pos                 (0U)\n#define RTC_BKP8R_Msk                 (0xFFFFFFFFUL << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP8R                     RTC_BKP8R_Msk\n\n/********************  Bits definition for RTC_BKP9R register  ****************/\n#define RTC_BKP9R_Pos                 (0U)\n#define RTC_BKP9R_Msk                 (0xFFFFFFFFUL << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP9R                     RTC_BKP9R_Msk\n\n/********************  Bits definition for RTC_BKP10R register  ***************/\n#define RTC_BKP10R_Pos                (0U)\n#define RTC_BKP10R_Msk                (0xFFFFFFFFUL << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP10R                    RTC_BKP10R_Msk\n\n/********************  Bits definition for RTC_BKP11R register  ***************/\n#define RTC_BKP11R_Pos                (0U)\n#define RTC_BKP11R_Msk                (0xFFFFFFFFUL << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP11R                    RTC_BKP11R_Msk\n\n/********************  Bits definition for RTC_BKP12R register  ***************/\n#define RTC_BKP12R_Pos                (0U)\n#define RTC_BKP12R_Msk                (0xFFFFFFFFUL << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP12R                    RTC_BKP12R_Msk\n\n/********************  Bits definition for RTC_BKP13R register  ***************/\n#define RTC_BKP13R_Pos                (0U)\n#define RTC_BKP13R_Msk                (0xFFFFFFFFUL << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP13R                    RTC_BKP13R_Msk\n\n/********************  Bits definition for RTC_BKP14R register  ***************/\n#define RTC_BKP14R_Pos                (0U)\n#define RTC_BKP14R_Msk                (0xFFFFFFFFUL << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP14R                    RTC_BKP14R_Msk\n\n/********************  Bits definition for RTC_BKP15R register  ***************/\n#define RTC_BKP15R_Pos                (0U)\n#define RTC_BKP15R_Msk                (0xFFFFFFFFUL << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP15R                    RTC_BKP15R_Msk\n\n/********************  Bits definition for RTC_BKP16R register  ***************/\n#define RTC_BKP16R_Pos                (0U)\n#define RTC_BKP16R_Msk                (0xFFFFFFFFUL << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP16R                    RTC_BKP16R_Msk\n\n/********************  Bits definition for RTC_BKP17R register  ***************/\n#define RTC_BKP17R_Pos                (0U)\n#define RTC_BKP17R_Msk                (0xFFFFFFFFUL << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP17R                    RTC_BKP17R_Msk\n\n/********************  Bits definition for RTC_BKP18R register  ***************/\n#define RTC_BKP18R_Pos                (0U)\n#define RTC_BKP18R_Msk                (0xFFFFFFFFUL << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP18R                    RTC_BKP18R_Msk\n\n/********************  Bits definition for RTC_BKP19R register  ***************/\n#define RTC_BKP19R_Pos                (0U)\n#define RTC_BKP19R_Msk                (0xFFFFFFFFUL << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP19R                    RTC_BKP19R_Msk\n\n/******************** Number of backup registers ******************************/\n#define RTC_BKP_NUMBER                       0x000000014U\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                          SD host Interface                                 */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SDIO_POWER register  ******************/\n#define SDIO_POWER_PWRCTRL_Pos         (0U)\n#define SDIO_POWER_PWRCTRL_Msk         (0x3UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */\n#define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */\n#define SDIO_POWER_PWRCTRL_0           (0x1UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x01 */\n#define SDIO_POWER_PWRCTRL_1           (0x2UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x02 */\n\n/******************  Bit definition for SDIO_CLKCR register  ******************/\n#define SDIO_CLKCR_CLKDIV_Pos          (0U)\n#define SDIO_CLKCR_CLKDIV_Msk          (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */\n#define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor             */\n#define SDIO_CLKCR_CLKEN_Pos           (8U)\n#define SDIO_CLKCR_CLKEN_Msk           (0x1UL << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */\n#define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit                */\n#define SDIO_CLKCR_PWRSAV_Pos          (9U)\n#define SDIO_CLKCR_PWRSAV_Msk          (0x1UL << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */\n#define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit  */\n#define SDIO_CLKCR_BYPASS_Pos          (10U)\n#define SDIO_CLKCR_BYPASS_Msk          (0x1UL << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */\n#define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */\n\n#define SDIO_CLKCR_WIDBUS_Pos          (11U)\n#define SDIO_CLKCR_WIDBUS_Msk          (0x3UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */\n#define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\n#define SDIO_CLKCR_WIDBUS_0            (0x1UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x0800 */\n#define SDIO_CLKCR_WIDBUS_1            (0x2UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x1000 */\n\n#define SDIO_CLKCR_NEGEDGE_Pos         (13U)\n#define SDIO_CLKCR_NEGEDGE_Msk         (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */\n#define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */\n#define SDIO_CLKCR_HWFC_EN_Pos         (14U)\n#define SDIO_CLKCR_HWFC_EN_Msk         (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */\n#define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable          */\n\n/*******************  Bit definition for SDIO_ARG register  *******************/\n#define SDIO_ARG_CMDARG_Pos            (0U)\n#define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */\n#define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */\n\n/*******************  Bit definition for SDIO_CMD register  *******************/\n#define SDIO_CMD_CMDINDEX_Pos          (0U)\n#define SDIO_CMD_CMDINDEX_Msk          (0x3FUL << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */\n#define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index                               */\n\n#define SDIO_CMD_WAITRESP_Pos          (6U)\n#define SDIO_CMD_WAITRESP_Msk          (0x3UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */\n#define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */\n#define SDIO_CMD_WAITRESP_0            (0x1UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0040 */\n#define SDIO_CMD_WAITRESP_1            (0x2UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0080 */\n\n#define SDIO_CMD_WAITINT_Pos           (8U)\n#define SDIO_CMD_WAITINT_Msk           (0x1UL << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */\n#define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request                               */\n#define SDIO_CMD_WAITPEND_Pos          (9U)\n#define SDIO_CMD_WAITPEND_Msk          (0x1UL << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */\n#define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\n#define SDIO_CMD_CPSMEN_Pos            (10U)\n#define SDIO_CMD_CPSMEN_Msk            (0x1UL << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */\n#define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit                   */\n#define SDIO_CMD_SDIOSUSPEND_Pos       (11U)\n#define SDIO_CMD_SDIOSUSPEND_Msk       (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */\n#define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command                                         */\n#define SDIO_CMD_ENCMDCOMPL_Pos        (12U)\n#define SDIO_CMD_ENCMDCOMPL_Msk        (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)       /*!< 0x00001000 */\n#define SDIO_CMD_ENCMDCOMPL            SDIO_CMD_ENCMDCOMPL_Msk                 /*!<Enable CMD completion                                          */\n#define SDIO_CMD_NIEN_Pos              (13U)\n#define SDIO_CMD_NIEN_Msk              (0x1UL << SDIO_CMD_NIEN_Pos)             /*!< 0x00002000 */\n#define SDIO_CMD_NIEN                  SDIO_CMD_NIEN_Msk                       /*!<Not Interrupt Enable                                           */\n#define SDIO_CMD_CEATACMD_Pos          (14U)\n#define SDIO_CMD_CEATACMD_Msk          (0x1UL << SDIO_CMD_CEATACMD_Pos)         /*!< 0x00004000 */\n#define SDIO_CMD_CEATACMD              SDIO_CMD_CEATACMD_Msk                   /*!<CE-ATA command                                                 */\n\n/*****************  Bit definition for SDIO_RESPCMD register  *****************/\n#define SDIO_RESPCMD_RESPCMD_Pos       (0U)\n#define SDIO_RESPCMD_RESPCMD_Msk       (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */\n#define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */\n\n/******************  Bit definition for SDIO_RESP0 register  ******************/\n#define SDIO_RESP0_CARDSTATUS0_Pos     (0U)\n#define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP1 register  ******************/\n#define SDIO_RESP1_CARDSTATUS1_Pos     (0U)\n#define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP2 register  ******************/\n#define SDIO_RESP2_CARDSTATUS2_Pos     (0U)\n#define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP3 register  ******************/\n#define SDIO_RESP3_CARDSTATUS3_Pos     (0U)\n#define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP4 register  ******************/\n#define SDIO_RESP4_CARDSTATUS4_Pos     (0U)\n#define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_DTIMER register  *****************/\n#define SDIO_DTIMER_DATATIME_Pos       (0U)\n#define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */\n\n/******************  Bit definition for SDIO_DLEN register  *******************/\n#define SDIO_DLEN_DATALENGTH_Pos       (0U)\n#define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */\n\n/******************  Bit definition for SDIO_DCTRL register  ******************/\n#define SDIO_DCTRL_DTEN_Pos            (0U)\n#define SDIO_DCTRL_DTEN_Msk            (0x1UL << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */\n#define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit         */\n#define SDIO_DCTRL_DTDIR_Pos           (1U)\n#define SDIO_DCTRL_DTDIR_Msk           (0x1UL << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */\n#define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */\n#define SDIO_DCTRL_DTMODE_Pos          (2U)\n#define SDIO_DCTRL_DTMODE_Msk          (0x1UL << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */\n#define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection      */\n#define SDIO_DCTRL_DMAEN_Pos           (3U)\n#define SDIO_DCTRL_DMAEN_Msk           (0x1UL << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */\n#define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit                   */\n\n#define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)\n#define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */\n#define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */\n#define SDIO_DCTRL_DBLOCKSIZE_0        (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0010 */\n#define SDIO_DCTRL_DBLOCKSIZE_1        (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0020 */\n#define SDIO_DCTRL_DBLOCKSIZE_2        (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0040 */\n#define SDIO_DCTRL_DBLOCKSIZE_3        (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0080 */\n\n#define SDIO_DCTRL_RWSTART_Pos         (8U)\n#define SDIO_DCTRL_RWSTART_Msk         (0x1UL << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */\n#define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start         */\n#define SDIO_DCTRL_RWSTOP_Pos          (9U)\n#define SDIO_DCTRL_RWSTOP_Msk          (0x1UL << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */\n#define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop          */\n#define SDIO_DCTRL_RWMOD_Pos           (10U)\n#define SDIO_DCTRL_RWMOD_Msk           (0x1UL << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */\n#define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode          */\n#define SDIO_DCTRL_SDIOEN_Pos          (11U)\n#define SDIO_DCTRL_SDIOEN_Msk          (0x1UL << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */\n#define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */\n\n/******************  Bit definition for SDIO_DCOUNT register  *****************/\n#define SDIO_DCOUNT_DATACOUNT_Pos      (0U)\n#define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */\n\n/******************  Bit definition for SDIO_STA register  ********************/\n#define SDIO_STA_CCRCFAIL_Pos          (0U)\n#define SDIO_STA_CCRCFAIL_Msk          (0x1UL << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */\n#define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */\n#define SDIO_STA_DCRCFAIL_Pos          (1U)\n#define SDIO_STA_DCRCFAIL_Msk          (0x1UL << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */\n#define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */\n#define SDIO_STA_CTIMEOUT_Pos          (2U)\n#define SDIO_STA_CTIMEOUT_Msk          (0x1UL << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */\n#define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */\n#define SDIO_STA_DTIMEOUT_Pos          (3U)\n#define SDIO_STA_DTIMEOUT_Msk          (0x1UL << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */\n#define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */\n#define SDIO_STA_TXUNDERR_Pos          (4U)\n#define SDIO_STA_TXUNDERR_Msk          (0x1UL << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */\n#define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */\n#define SDIO_STA_RXOVERR_Pos           (5U)\n#define SDIO_STA_RXOVERR_Msk           (0x1UL << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */\n#define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */\n#define SDIO_STA_CMDREND_Pos           (6U)\n#define SDIO_STA_CMDREND_Msk           (0x1UL << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */\n#define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */\n#define SDIO_STA_CMDSENT_Pos           (7U)\n#define SDIO_STA_CMDSENT_Msk           (0x1UL << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */\n#define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */\n#define SDIO_STA_DATAEND_Pos           (8U)\n#define SDIO_STA_DATAEND_Msk           (0x1UL << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */\n#define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */\n#define SDIO_STA_STBITERR_Pos          (9U)\n#define SDIO_STA_STBITERR_Msk          (0x1UL << SDIO_STA_STBITERR_Pos)         /*!< 0x00000200 */\n#define SDIO_STA_STBITERR              SDIO_STA_STBITERR_Msk                   /*!<Start bit not detected on all data signals in wide bus mode */\n#define SDIO_STA_DBCKEND_Pos           (10U)\n#define SDIO_STA_DBCKEND_Msk           (0x1UL << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */\n#define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */\n#define SDIO_STA_CMDACT_Pos            (11U)\n#define SDIO_STA_CMDACT_Msk            (0x1UL << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */\n#define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */\n#define SDIO_STA_TXACT_Pos             (12U)\n#define SDIO_STA_TXACT_Msk             (0x1UL << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */\n#define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */\n#define SDIO_STA_RXACT_Pos             (13U)\n#define SDIO_STA_RXACT_Msk             (0x1UL << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */\n#define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */\n#define SDIO_STA_TXFIFOHE_Pos          (14U)\n#define SDIO_STA_TXFIFOHE_Msk          (0x1UL << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */\n#define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\n#define SDIO_STA_RXFIFOHF_Pos          (15U)\n#define SDIO_STA_RXFIFOHF_Msk          (0x1UL << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */\n#define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\n#define SDIO_STA_TXFIFOF_Pos           (16U)\n#define SDIO_STA_TXFIFOF_Msk           (0x1UL << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */\n#define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */\n#define SDIO_STA_RXFIFOF_Pos           (17U)\n#define SDIO_STA_RXFIFOF_Msk           (0x1UL << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */\n#define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */\n#define SDIO_STA_TXFIFOE_Pos           (18U)\n#define SDIO_STA_TXFIFOE_Msk           (0x1UL << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */\n#define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */\n#define SDIO_STA_RXFIFOE_Pos           (19U)\n#define SDIO_STA_RXFIFOE_Msk           (0x1UL << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */\n#define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */\n#define SDIO_STA_TXDAVL_Pos            (20U)\n#define SDIO_STA_TXDAVL_Msk            (0x1UL << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */\n#define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */\n#define SDIO_STA_RXDAVL_Pos            (21U)\n#define SDIO_STA_RXDAVL_Msk            (0x1UL << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */\n#define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */\n#define SDIO_STA_SDIOIT_Pos            (22U)\n#define SDIO_STA_SDIOIT_Msk            (0x1UL << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */\n#define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */\n#define SDIO_STA_CEATAEND_Pos          (23U)\n#define SDIO_STA_CEATAEND_Msk          (0x1UL << SDIO_STA_CEATAEND_Pos)         /*!< 0x00800000 */\n#define SDIO_STA_CEATAEND              SDIO_STA_CEATAEND_Msk                   /*!<CE-ATA command completion signal received for CMD61 */\n\n/*******************  Bit definition for SDIO_ICR register  *******************/\n#define SDIO_ICR_CCRCFAILC_Pos         (0U)\n#define SDIO_ICR_CCRCFAILC_Msk         (0x1UL << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */\n#define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */\n#define SDIO_ICR_DCRCFAILC_Pos         (1U)\n#define SDIO_ICR_DCRCFAILC_Msk         (0x1UL << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */\n#define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */\n#define SDIO_ICR_CTIMEOUTC_Pos         (2U)\n#define SDIO_ICR_CTIMEOUTC_Msk         (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */\n#define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */\n#define SDIO_ICR_DTIMEOUTC_Pos         (3U)\n#define SDIO_ICR_DTIMEOUTC_Msk         (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */\n#define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */\n#define SDIO_ICR_TXUNDERRC_Pos         (4U)\n#define SDIO_ICR_TXUNDERRC_Msk         (0x1UL << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */\n#define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */\n#define SDIO_ICR_RXOVERRC_Pos          (5U)\n#define SDIO_ICR_RXOVERRC_Msk          (0x1UL << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */\n#define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */\n#define SDIO_ICR_CMDRENDC_Pos          (6U)\n#define SDIO_ICR_CMDRENDC_Msk          (0x1UL << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */\n#define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */\n#define SDIO_ICR_CMDSENTC_Pos          (7U)\n#define SDIO_ICR_CMDSENTC_Msk          (0x1UL << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */\n#define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */\n#define SDIO_ICR_DATAENDC_Pos          (8U)\n#define SDIO_ICR_DATAENDC_Msk          (0x1UL << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */\n#define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */\n#define SDIO_ICR_STBITERRC_Pos         (9U)\n#define SDIO_ICR_STBITERRC_Msk         (0x1UL << SDIO_ICR_STBITERRC_Pos)        /*!< 0x00000200 */\n#define SDIO_ICR_STBITERRC             SDIO_ICR_STBITERRC_Msk                  /*!<STBITERR flag clear bit */\n#define SDIO_ICR_DBCKENDC_Pos          (10U)\n#define SDIO_ICR_DBCKENDC_Msk          (0x1UL << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */\n#define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */\n#define SDIO_ICR_SDIOITC_Pos           (22U)\n#define SDIO_ICR_SDIOITC_Msk           (0x1UL << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */\n#define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */\n#define SDIO_ICR_CEATAENDC_Pos         (23U)\n#define SDIO_ICR_CEATAENDC_Msk         (0x1UL << SDIO_ICR_CEATAENDC_Pos)        /*!< 0x00800000 */\n#define SDIO_ICR_CEATAENDC             SDIO_ICR_CEATAENDC_Msk                  /*!<CEATAEND flag clear bit */\n\n/******************  Bit definition for SDIO_MASK register  *******************/\n#define SDIO_MASK_CCRCFAILIE_Pos       (0U)\n#define SDIO_MASK_CCRCFAILIE_Msk       (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */\n#define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */\n#define SDIO_MASK_DCRCFAILIE_Pos       (1U)\n#define SDIO_MASK_DCRCFAILIE_Msk       (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */\n#define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */\n#define SDIO_MASK_CTIMEOUTIE_Pos       (2U)\n#define SDIO_MASK_CTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */\n#define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */\n#define SDIO_MASK_DTIMEOUTIE_Pos       (3U)\n#define SDIO_MASK_DTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */\n#define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */\n#define SDIO_MASK_TXUNDERRIE_Pos       (4U)\n#define SDIO_MASK_TXUNDERRIE_Msk       (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */\n#define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */\n#define SDIO_MASK_RXOVERRIE_Pos        (5U)\n#define SDIO_MASK_RXOVERRIE_Msk        (0x1UL << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */\n#define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */\n#define SDIO_MASK_CMDRENDIE_Pos        (6U)\n#define SDIO_MASK_CMDRENDIE_Msk        (0x1UL << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */\n#define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */\n#define SDIO_MASK_CMDSENTIE_Pos        (7U)\n#define SDIO_MASK_CMDSENTIE_Msk        (0x1UL << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */\n#define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */\n#define SDIO_MASK_DATAENDIE_Pos        (8U)\n#define SDIO_MASK_DATAENDIE_Msk        (0x1UL << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */\n#define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */\n#define SDIO_MASK_STBITERRIE_Pos       (9U)\n#define SDIO_MASK_STBITERRIE_Msk       (0x1UL << SDIO_MASK_STBITERRIE_Pos)      /*!< 0x00000200 */\n#define SDIO_MASK_STBITERRIE           SDIO_MASK_STBITERRIE_Msk                /*!<Start Bit Error Interrupt Enable           */\n#define SDIO_MASK_DBCKENDIE_Pos        (10U)\n#define SDIO_MASK_DBCKENDIE_Msk        (0x1UL << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */\n#define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */\n#define SDIO_MASK_CMDACTIE_Pos         (11U)\n#define SDIO_MASK_CMDACTIE_Msk         (0x1UL << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */\n#define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */\n#define SDIO_MASK_TXACTIE_Pos          (12U)\n#define SDIO_MASK_TXACTIE_Msk          (0x1UL << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */\n#define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */\n#define SDIO_MASK_RXACTIE_Pos          (13U)\n#define SDIO_MASK_RXACTIE_Msk          (0x1UL << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */\n#define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */\n#define SDIO_MASK_TXFIFOHEIE_Pos       (14U)\n#define SDIO_MASK_TXFIFOHEIE_Msk       (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */\n#define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */\n#define SDIO_MASK_RXFIFOHFIE_Pos       (15U)\n#define SDIO_MASK_RXFIFOHFIE_Msk       (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */\n#define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */\n#define SDIO_MASK_TXFIFOFIE_Pos        (16U)\n#define SDIO_MASK_TXFIFOFIE_Msk        (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */\n#define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */\n#define SDIO_MASK_RXFIFOFIE_Pos        (17U)\n#define SDIO_MASK_RXFIFOFIE_Msk        (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */\n#define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */\n#define SDIO_MASK_TXFIFOEIE_Pos        (18U)\n#define SDIO_MASK_TXFIFOEIE_Msk        (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */\n#define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_RXFIFOEIE_Pos        (19U)\n#define SDIO_MASK_RXFIFOEIE_Msk        (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */\n#define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_TXDAVLIE_Pos         (20U)\n#define SDIO_MASK_TXDAVLIE_Msk         (0x1UL << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */\n#define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */\n#define SDIO_MASK_RXDAVLIE_Pos         (21U)\n#define SDIO_MASK_RXDAVLIE_Msk         (0x1UL << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */\n#define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */\n#define SDIO_MASK_SDIOITIE_Pos         (22U)\n#define SDIO_MASK_SDIOITIE_Msk         (0x1UL << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */\n#define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */\n#define SDIO_MASK_CEATAENDIE_Pos       (23U)\n#define SDIO_MASK_CEATAENDIE_Msk       (0x1UL << SDIO_MASK_CEATAENDIE_Pos)      /*!< 0x00800000 */\n#define SDIO_MASK_CEATAENDIE           SDIO_MASK_CEATAENDIE_Msk                /*!<CE-ATA command completion signal received Interrupt Enable */\n\n/*****************  Bit definition for SDIO_FIFOCNT register  *****************/\n#define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)\n#define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */\n#define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */\n\n/******************  Bit definition for SDIO_FIFO register  *******************/\n#define SDIO_FIFO_FIFODATA_Pos         (0U)\n#define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Serial Peripheral Interface                         */\n/*                                                                            */\n/******************************************************************************/\n#define SPI_I2S_FULLDUPLEX_SUPPORT                                             /*!< I2S Full-Duplex support */\n\n/*******************  Bit definition for SPI_CR1 register  ********************/\n#define SPI_CR1_CPHA_Pos            (0U)\n#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */\n#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */\n#define SPI_CR1_CPOL_Pos            (1U)\n#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */\n#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */\n#define SPI_CR1_MSTR_Pos            (2U)\n#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */\n#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */\n\n#define SPI_CR1_BR_Pos              (3U)\n#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */\n#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */\n#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */\n#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */\n#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */\n\n#define SPI_CR1_SPE_Pos             (6U)\n#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */\n#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */\n#define SPI_CR1_LSBFIRST_Pos        (7U)\n#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */\n#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */\n#define SPI_CR1_SSI_Pos             (8U)\n#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */\n#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */\n#define SPI_CR1_SSM_Pos             (9U)\n#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */\n#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */\n#define SPI_CR1_RXONLY_Pos          (10U)\n#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */\n#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */\n#define SPI_CR1_DFF_Pos             (11U)\n#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */\n#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */\n#define SPI_CR1_CRCNEXT_Pos         (12U)\n#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */\n#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */\n#define SPI_CR1_CRCEN_Pos           (13U)\n#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */\n#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */\n#define SPI_CR1_BIDIOE_Pos          (14U)\n#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */\n#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */\n#define SPI_CR1_BIDIMODE_Pos        (15U)\n#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */\n#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */\n\n/*******************  Bit definition for SPI_CR2 register  ********************/\n#define SPI_CR2_RXDMAEN_Pos         (0U)\n#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */\n#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */\n#define SPI_CR2_TXDMAEN_Pos         (1U)\n#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */\n#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */\n#define SPI_CR2_SSOE_Pos            (2U)\n#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */\n#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */\n#define SPI_CR2_FRF_Pos             (4U)\n#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */\n#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */\n#define SPI_CR2_ERRIE_Pos           (5U)\n#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */\n#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */\n#define SPI_CR2_RXNEIE_Pos          (6U)\n#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */\n#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */\n#define SPI_CR2_TXEIE_Pos           (7U)\n#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */\n#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */\n\n/********************  Bit definition for SPI_SR register  ********************/\n#define SPI_SR_RXNE_Pos             (0U)\n#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */\n#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */\n#define SPI_SR_TXE_Pos              (1U)\n#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */\n#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */\n#define SPI_SR_CHSIDE_Pos           (2U)\n#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */\n#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */\n#define SPI_SR_UDR_Pos              (3U)\n#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */\n#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */\n#define SPI_SR_CRCERR_Pos           (4U)\n#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */\n#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */\n#define SPI_SR_MODF_Pos             (5U)\n#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */\n#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */\n#define SPI_SR_OVR_Pos              (6U)\n#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */\n#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */\n#define SPI_SR_BSY_Pos              (7U)\n#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */\n#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */\n#define SPI_SR_FRE_Pos              (8U)\n#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */\n#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */\n\n/********************  Bit definition for SPI_DR register  ********************/\n#define SPI_DR_DR_Pos               (0U)\n#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */\n#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */\n\n/*******************  Bit definition for SPI_CRCPR register  ******************/\n#define SPI_CRCPR_CRCPOLY_Pos       (0U)\n#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */\n#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */\n\n/******************  Bit definition for SPI_RXCRCR register  ******************/\n#define SPI_RXCRCR_RXCRC_Pos        (0U)\n#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */\n\n/******************  Bit definition for SPI_TXCRCR register  ******************/\n#define SPI_TXCRCR_TXCRC_Pos        (0U)\n#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */\n\n/******************  Bit definition for SPI_I2SCFGR register  *****************/\n#define SPI_I2SCFGR_CHLEN_Pos       (0U)\n#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */\n#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */\n\n#define SPI_I2SCFGR_DATLEN_Pos      (1U)\n#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */\n#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */\n#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */\n#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */\n\n#define SPI_I2SCFGR_CKPOL_Pos       (3U)\n#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */\n#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */\n\n#define SPI_I2SCFGR_I2SSTD_Pos      (4U)\n#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */\n#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */\n#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */\n#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */\n\n#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)\n#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */\n#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */\n\n#define SPI_I2SCFGR_I2SCFG_Pos      (8U)\n#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */\n#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */\n#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */\n#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */\n\n#define SPI_I2SCFGR_I2SE_Pos        (10U)\n#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */\n#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */\n#define SPI_I2SCFGR_I2SMOD_Pos      (11U)\n#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */\n#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */\n\n/******************  Bit definition for SPI_I2SPR register  *******************/\n#define SPI_I2SPR_I2SDIV_Pos        (0U)\n#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */\n#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */\n#define SPI_I2SPR_ODD_Pos           (8U)\n#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */\n#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */\n#define SPI_I2SPR_MCKOE_Pos         (9U)\n#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */\n#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                 SYSCFG                                     */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SYSCFG_MEMRMP register  ***************/\n#define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)\n#define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */\n#define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */\n#define SYSCFG_MEMRMP_MEM_MODE_0             (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */\n#define SYSCFG_MEMRMP_MEM_MODE_1             (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */\n/******************  Bit definition for SYSCFG_PMC register  ******************/\n#define SYSCFG_PMC_ADC1DC2_Pos               (16U)\n#define SYSCFG_PMC_ADC1DC2_Msk               (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)  /*!< 0x00010000 */\n#define SYSCFG_PMC_ADC1DC2                   SYSCFG_PMC_ADC1DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */\n\n/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\n#define SYSCFG_EXTICR1_EXTI0_Pos             (0U)\n#define SYSCFG_EXTICR1_EXTI0_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */\n#define SYSCFG_EXTICR1_EXTI1_Pos             (4U)\n#define SYSCFG_EXTICR1_EXTI1_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */\n#define SYSCFG_EXTICR1_EXTI2_Pos             (8U)\n#define SYSCFG_EXTICR1_EXTI2_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */\n#define SYSCFG_EXTICR1_EXTI3_Pos             (12U)\n#define SYSCFG_EXTICR1_EXTI3_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */\n/**\n  * @brief   EXTI0 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PD              0x0003U                           /*!<PD[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PE              0x0004U                           /*!<PE[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */\n\n/**\n  * @brief   EXTI1 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PD              0x0030U                           /*!<PD[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PE              0x0040U                           /*!<PE[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */\n\n/**\n  * @brief   EXTI2 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PD              0x0300U                           /*!<PD[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PE              0x0400U                           /*!<PE[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */\n\n/**\n  * @brief   EXTI3 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PD              0x3000U                           /*!<PD[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PE              0x4000U                           /*!<PE[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\n#define SYSCFG_EXTICR2_EXTI4_Pos             (0U)\n#define SYSCFG_EXTICR2_EXTI4_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */\n#define SYSCFG_EXTICR2_EXTI5_Pos             (4U)\n#define SYSCFG_EXTICR2_EXTI5_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */\n#define SYSCFG_EXTICR2_EXTI6_Pos             (8U)\n#define SYSCFG_EXTICR2_EXTI6_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */\n#define SYSCFG_EXTICR2_EXTI7_Pos             (12U)\n#define SYSCFG_EXTICR2_EXTI7_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */\n\n/**\n  * @brief   EXTI4 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PD              0x0003U                           /*!<PD[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PE              0x0004U                           /*!<PE[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */\n\n/**\n  * @brief   EXTI5 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PD              0x0030U                           /*!<PD[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PE              0x0040U                           /*!<PE[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */\n\n/**\n  * @brief   EXTI6 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PD              0x0300U                           /*!<PD[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PE              0x0400U                           /*!<PE[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */\n\n/**\n  * @brief   EXTI7 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PD              0x3000U                           /*!<PD[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PE              0x4000U                           /*!<PE[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\n#define SYSCFG_EXTICR3_EXTI8_Pos             (0U)\n#define SYSCFG_EXTICR3_EXTI8_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */\n#define SYSCFG_EXTICR3_EXTI9_Pos             (4U)\n#define SYSCFG_EXTICR3_EXTI9_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */\n#define SYSCFG_EXTICR3_EXTI10_Pos            (8U)\n#define SYSCFG_EXTICR3_EXTI10_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */\n#define SYSCFG_EXTICR3_EXTI11_Pos            (12U)\n#define SYSCFG_EXTICR3_EXTI11_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */\n\n/**\n  * @brief   EXTI8 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PD              0x0003U                           /*!<PD[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PE              0x0004U                           /*!<PE[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */\n\n/**\n  * @brief   EXTI9 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PD              0x0030U                           /*!<PD[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PE              0x0040U                           /*!<PE[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */\n\n/**\n  * @brief   EXTI10 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PD             0x0300U                           /*!<PD[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PE             0x0400U                           /*!<PE[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */\n\n/**\n  * @brief   EXTI11 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PD             0x3000U                           /*!<PD[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PE             0x4000U                           /*!<PE[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\n#define SYSCFG_EXTICR4_EXTI12_Pos            (0U)\n#define SYSCFG_EXTICR4_EXTI12_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */\n#define SYSCFG_EXTICR4_EXTI13_Pos            (4U)\n#define SYSCFG_EXTICR4_EXTI13_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */\n#define SYSCFG_EXTICR4_EXTI14_Pos            (8U)\n#define SYSCFG_EXTICR4_EXTI14_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */\n#define SYSCFG_EXTICR4_EXTI15_Pos            (12U)\n#define SYSCFG_EXTICR4_EXTI15_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */\n\n/**\n  * @brief   EXTI12 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PD             0x0003U                           /*!<PD[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PE             0x0004U                           /*!<PE[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */\n\n/**\n  * @brief   EXTI13 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PD             0x0030U                           /*!<PD[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PE             0x0040U                           /*!<PE[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */\n\n/**\n  * @brief   EXTI14 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PD             0x0300U                           /*!<PD[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PE             0x0400U                           /*!<PE[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */\n\n/**\n  * @brief   EXTI15 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PD             0x3000U                           /*!<PD[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PE             0x4000U                           /*!<PE[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */\n\n/******************  Bit definition for SYSCFG_CMPCR register  ****************/\n#define SYSCFG_CMPCR_CMP_PD_Pos              (0U)\n#define SYSCFG_CMPCR_CMP_PD_Msk              (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */\n#define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */\n#define SYSCFG_CMPCR_READY_Pos               (8U)\n#define SYSCFG_CMPCR_READY_Msk               (0x1UL << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */\n#define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    TIM                                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for TIM_CR1 register  ********************/\n#define TIM_CR1_CEN_Pos           (0U)\n#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */\n#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */\n#define TIM_CR1_UDIS_Pos          (1U)\n#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */\n#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */\n#define TIM_CR1_URS_Pos           (2U)\n#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */\n#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */\n#define TIM_CR1_OPM_Pos           (3U)\n#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */\n#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */\n#define TIM_CR1_DIR_Pos           (4U)\n#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */\n#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */\n\n#define TIM_CR1_CMS_Pos           (5U)\n#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */\n#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */\n#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR1_ARPE_Pos          (7U)\n#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */\n#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */\n\n#define TIM_CR1_CKD_Pos           (8U)\n#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */\n#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */\n#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */\n#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */\n\n/*******************  Bit definition for TIM_CR2 register  ********************/\n#define TIM_CR2_CCPC_Pos          (0U)\n#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */\n#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */\n#define TIM_CR2_CCUS_Pos          (2U)\n#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */\n#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */\n#define TIM_CR2_CCDS_Pos          (3U)\n#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */\n#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */\n\n#define TIM_CR2_MMS_Pos           (4U)\n#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */\n#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */\n#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */\n#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR2_TI1S_Pos          (7U)\n#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */\n#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */\n#define TIM_CR2_OIS1_Pos          (8U)\n#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */\n#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */\n#define TIM_CR2_OIS1N_Pos         (9U)\n#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */\n#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */\n#define TIM_CR2_OIS2_Pos          (10U)\n#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */\n#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */\n#define TIM_CR2_OIS2N_Pos         (11U)\n#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */\n#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */\n#define TIM_CR2_OIS3_Pos          (12U)\n#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */\n#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */\n#define TIM_CR2_OIS3N_Pos         (13U)\n#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */\n#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */\n#define TIM_CR2_OIS4_Pos          (14U)\n#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */\n#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */\n\n/*******************  Bit definition for TIM_SMCR register  *******************/\n#define TIM_SMCR_SMS_Pos          (0U)\n#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */\n#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */\n#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */\n#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */\n#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */\n\n#define TIM_SMCR_TS_Pos           (4U)\n#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */\n#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */\n#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */\n#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */\n#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */\n\n#define TIM_SMCR_MSM_Pos          (7U)\n#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */\n#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */\n\n#define TIM_SMCR_ETF_Pos          (8U)\n#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */\n#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */\n#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */\n#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */\n#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */\n#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */\n\n#define TIM_SMCR_ETPS_Pos         (12U)\n#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */\n#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */\n#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */\n#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */\n\n#define TIM_SMCR_ECE_Pos          (14U)\n#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */\n#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */\n#define TIM_SMCR_ETP_Pos          (15U)\n#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */\n#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */\n\n/*******************  Bit definition for TIM_DIER register  *******************/\n#define TIM_DIER_UIE_Pos          (0U)\n#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */\n#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */\n#define TIM_DIER_CC1IE_Pos        (1U)\n#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */\n#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */\n#define TIM_DIER_CC2IE_Pos        (2U)\n#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */\n#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */\n#define TIM_DIER_CC3IE_Pos        (3U)\n#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */\n#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */\n#define TIM_DIER_CC4IE_Pos        (4U)\n#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */\n#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */\n#define TIM_DIER_COMIE_Pos        (5U)\n#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */\n#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */\n#define TIM_DIER_TIE_Pos          (6U)\n#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */\n#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */\n#define TIM_DIER_BIE_Pos          (7U)\n#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */\n#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */\n#define TIM_DIER_UDE_Pos          (8U)\n#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */\n#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */\n#define TIM_DIER_CC1DE_Pos        (9U)\n#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */\n#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */\n#define TIM_DIER_CC2DE_Pos        (10U)\n#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */\n#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */\n#define TIM_DIER_CC3DE_Pos        (11U)\n#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */\n#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */\n#define TIM_DIER_CC4DE_Pos        (12U)\n#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */\n#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */\n#define TIM_DIER_COMDE_Pos        (13U)\n#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */\n#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */\n#define TIM_DIER_TDE_Pos          (14U)\n#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */\n#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */\n\n/********************  Bit definition for TIM_SR register  ********************/\n#define TIM_SR_UIF_Pos            (0U)\n#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */\n#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */\n#define TIM_SR_CC1IF_Pos          (1U)\n#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */\n#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */\n#define TIM_SR_CC2IF_Pos          (2U)\n#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */\n#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */\n#define TIM_SR_CC3IF_Pos          (3U)\n#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */\n#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */\n#define TIM_SR_CC4IF_Pos          (4U)\n#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */\n#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */\n#define TIM_SR_COMIF_Pos          (5U)\n#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */\n#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */\n#define TIM_SR_TIF_Pos            (6U)\n#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */\n#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */\n#define TIM_SR_BIF_Pos            (7U)\n#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */\n#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */\n#define TIM_SR_CC1OF_Pos          (9U)\n#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */\n#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */\n#define TIM_SR_CC2OF_Pos          (10U)\n#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */\n#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */\n#define TIM_SR_CC3OF_Pos          (11U)\n#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */\n#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */\n#define TIM_SR_CC4OF_Pos          (12U)\n#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */\n#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */\n\n/*******************  Bit definition for TIM_EGR register  ********************/\n#define TIM_EGR_UG_Pos            (0U)\n#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */\n#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */\n#define TIM_EGR_CC1G_Pos          (1U)\n#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */\n#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */\n#define TIM_EGR_CC2G_Pos          (2U)\n#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */\n#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */\n#define TIM_EGR_CC3G_Pos          (3U)\n#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */\n#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */\n#define TIM_EGR_CC4G_Pos          (4U)\n#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */\n#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */\n#define TIM_EGR_COMG_Pos          (5U)\n#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */\n#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */\n#define TIM_EGR_TG_Pos            (6U)\n#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */\n#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */\n#define TIM_EGR_BG_Pos            (7U)\n#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */\n#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */\n\n/******************  Bit definition for TIM_CCMR1 register  *******************/\n#define TIM_CCMR1_CC1S_Pos        (0U)\n#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\n#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR1_OC1FE_Pos       (2U)\n#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */\n#define TIM_CCMR1_OC1PE_Pos       (3U)\n#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */\n\n#define TIM_CCMR1_OC1M_Pos        (4U)\n#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */\n#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR1_OC1CE_Pos       (7U)\n#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */\n\n#define TIM_CCMR1_CC2S_Pos        (8U)\n#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\n#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR1_OC2FE_Pos       (10U)\n#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */\n#define TIM_CCMR1_OC2PE_Pos       (11U)\n#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */\n\n#define TIM_CCMR1_OC2M_Pos        (12U)\n#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */\n#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR1_OC2CE_Pos       (15U)\n#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR1_IC1PSC_Pos      (2U)\n#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\n#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR1_IC1F_Pos        (4U)\n#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */\n#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR1_IC2PSC_Pos      (10U)\n#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */\n#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR1_IC2F_Pos        (12U)\n#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */\n#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */\n\n/******************  Bit definition for TIM_CCMR2 register  *******************/\n#define TIM_CCMR2_CC3S_Pos        (0U)\n#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */\n#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR2_OC3FE_Pos       (2U)\n#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */\n#define TIM_CCMR2_OC3PE_Pos       (3U)\n#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */\n\n#define TIM_CCMR2_OC3M_Pos        (4U)\n#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\n#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR2_OC3CE_Pos       (7U)\n#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */\n\n#define TIM_CCMR2_CC4S_Pos        (8U)\n#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\n#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR2_OC4FE_Pos       (10U)\n#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */\n#define TIM_CCMR2_OC4PE_Pos       (11U)\n#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */\n\n#define TIM_CCMR2_OC4M_Pos        (12U)\n#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\n#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR2_OC4CE_Pos       (15U)\n#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR2_IC3PSC_Pos      (2U)\n#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\n#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR2_IC3F_Pos        (4U)\n#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\n#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR2_IC4PSC_Pos      (10U)\n#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\n#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR2_IC4F_Pos        (12U)\n#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\n#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */\n\n/*******************  Bit definition for TIM_CCER register  *******************/\n#define TIM_CCER_CC1E_Pos         (0U)\n#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */\n#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */\n#define TIM_CCER_CC1P_Pos         (1U)\n#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */\n#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */\n#define TIM_CCER_CC1NE_Pos        (2U)\n#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */\n#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */\n#define TIM_CCER_CC1NP_Pos        (3U)\n#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */\n#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */\n#define TIM_CCER_CC2E_Pos         (4U)\n#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */\n#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */\n#define TIM_CCER_CC2P_Pos         (5U)\n#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */\n#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */\n#define TIM_CCER_CC2NE_Pos        (6U)\n#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */\n#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */\n#define TIM_CCER_CC2NP_Pos        (7U)\n#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */\n#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */\n#define TIM_CCER_CC3E_Pos         (8U)\n#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */\n#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */\n#define TIM_CCER_CC3P_Pos         (9U)\n#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */\n#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */\n#define TIM_CCER_CC3NE_Pos        (10U)\n#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */\n#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */\n#define TIM_CCER_CC3NP_Pos        (11U)\n#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */\n#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */\n#define TIM_CCER_CC4E_Pos         (12U)\n#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */\n#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */\n#define TIM_CCER_CC4P_Pos         (13U)\n#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */\n#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */\n#define TIM_CCER_CC4NP_Pos        (15U)\n#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */\n#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */\n\n/*******************  Bit definition for TIM_CNT register  ********************/\n#define TIM_CNT_CNT_Pos           (0U)\n#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0xFFFFFFFF */\n#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                                  /*!<Counter Value            */\n\n/*******************  Bit definition for TIM_PSC register  ********************/\n#define TIM_PSC_PSC_Pos           (0U)\n#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */\n#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */\n\n/*******************  Bit definition for TIM_ARR register  ********************/\n#define TIM_ARR_ARR_Pos           (0U)\n#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */\n#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */\n\n/*******************  Bit definition for TIM_RCR register  ********************/\n#define TIM_RCR_REP_Pos           (0U)\n#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */\n#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */\n\n/*******************  Bit definition for TIM_CCR1 register  *******************/\n#define TIM_CCR1_CCR1_Pos         (0U)\n#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */\n\n/*******************  Bit definition for TIM_CCR2 register  *******************/\n#define TIM_CCR2_CCR2_Pos         (0U)\n#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */\n\n/*******************  Bit definition for TIM_CCR3 register  *******************/\n#define TIM_CCR3_CCR3_Pos         (0U)\n#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */\n\n/*******************  Bit definition for TIM_CCR4 register  *******************/\n#define TIM_CCR4_CCR4_Pos         (0U)\n#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */\n\n/*******************  Bit definition for TIM_BDTR register  *******************/\n#define TIM_BDTR_DTG_Pos          (0U)\n#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */\n#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\n#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */\n#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */\n#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */\n#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */\n#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */\n#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */\n#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */\n#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */\n\n#define TIM_BDTR_LOCK_Pos         (8U)\n#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */\n#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */\n#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */\n#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */\n\n#define TIM_BDTR_OSSI_Pos         (10U)\n#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */\n#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */\n#define TIM_BDTR_OSSR_Pos         (11U)\n#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */\n#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */\n#define TIM_BDTR_BKE_Pos          (12U)\n#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */\n#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */\n#define TIM_BDTR_BKP_Pos          (13U)\n#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */\n#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */\n#define TIM_BDTR_AOE_Pos          (14U)\n#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */\n#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */\n#define TIM_BDTR_MOE_Pos          (15U)\n#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */\n#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */\n\n/*******************  Bit definition for TIM_DCR register  ********************/\n#define TIM_DCR_DBA_Pos           (0U)\n#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */\n#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */\n#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */\n#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */\n#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */\n#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */\n#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */\n\n#define TIM_DCR_DBL_Pos           (8U)\n#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */\n#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */\n#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */\n#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */\n#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */\n#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */\n#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */\n\n/*******************  Bit definition for TIM_DMAR register  *******************/\n#define TIM_DMAR_DMAB_Pos         (0U)\n#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */\n#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */\n\n/*******************  Bit definition for TIM_OR register  *********************/\n#define TIM_OR_TI1_RMP_Pos        (0U)\n#define TIM_OR_TI1_RMP_Msk        (0x3UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000003 */\n#define TIM_OR_TI1_RMP            TIM_OR_TI1_RMP_Msk                           /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */\n#define TIM_OR_TI1_RMP_0          (0x1UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000001 */\n#define TIM_OR_TI1_RMP_1          (0x2UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000002 */\n\n#define TIM_OR_TI4_RMP_Pos        (6U)\n#define TIM_OR_TI4_RMP_Msk        (0x3UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */\n#define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */\n#define TIM_OR_TI4_RMP_0          (0x1UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */\n#define TIM_OR_TI4_RMP_1          (0x2UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */\n#define TIM_OR_ITR1_RMP_Pos       (10U)\n#define TIM_OR_ITR1_RMP_Msk       (0x3UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */\n#define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\n#define TIM_OR_ITR1_RMP_0         (0x1UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */\n#define TIM_OR_ITR1_RMP_1         (0x2UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*         Universal Synchronous Asynchronous Receiver Transmitter            */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for USART_SR register  *******************/\n#define USART_SR_PE_Pos               (0U)\n#define USART_SR_PE_Msk               (0x1UL << USART_SR_PE_Pos)                /*!< 0x00000001 */\n#define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */\n#define USART_SR_FE_Pos               (1U)\n#define USART_SR_FE_Msk               (0x1UL << USART_SR_FE_Pos)                /*!< 0x00000002 */\n#define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */\n#define USART_SR_NE_Pos               (2U)\n#define USART_SR_NE_Msk               (0x1UL << USART_SR_NE_Pos)                /*!< 0x00000004 */\n#define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */\n#define USART_SR_ORE_Pos              (3U)\n#define USART_SR_ORE_Msk              (0x1UL << USART_SR_ORE_Pos)               /*!< 0x00000008 */\n#define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */\n#define USART_SR_IDLE_Pos             (4U)\n#define USART_SR_IDLE_Msk             (0x1UL << USART_SR_IDLE_Pos)              /*!< 0x00000010 */\n#define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */\n#define USART_SR_RXNE_Pos             (5U)\n#define USART_SR_RXNE_Msk             (0x1UL << USART_SR_RXNE_Pos)              /*!< 0x00000020 */\n#define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */\n#define USART_SR_TC_Pos               (6U)\n#define USART_SR_TC_Msk               (0x1UL << USART_SR_TC_Pos)                /*!< 0x00000040 */\n#define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */\n#define USART_SR_TXE_Pos              (7U)\n#define USART_SR_TXE_Msk              (0x1UL << USART_SR_TXE_Pos)               /*!< 0x00000080 */\n#define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */\n#define USART_SR_LBD_Pos              (8U)\n#define USART_SR_LBD_Msk              (0x1UL << USART_SR_LBD_Pos)               /*!< 0x00000100 */\n#define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */\n#define USART_SR_CTS_Pos              (9U)\n#define USART_SR_CTS_Msk              (0x1UL << USART_SR_CTS_Pos)               /*!< 0x00000200 */\n#define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */\n\n/*******************  Bit definition for USART_DR register  *******************/\n#define USART_DR_DR_Pos               (0U)\n#define USART_DR_DR_Msk               (0x1FFUL << USART_DR_DR_Pos)              /*!< 0x000001FF */\n#define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */\n\n/******************  Bit definition for USART_BRR register  *******************/\n#define USART_BRR_DIV_Fraction_Pos    (0U)\n#define USART_BRR_DIV_Fraction_Msk    (0xFUL << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */\n#define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */\n#define USART_BRR_DIV_Mantissa_Pos    (4U)\n#define USART_BRR_DIV_Mantissa_Msk    (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */\n#define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */\n\n/******************  Bit definition for USART_CR1 register  *******************/\n#define USART_CR1_SBK_Pos             (0U)\n#define USART_CR1_SBK_Msk             (0x1UL << USART_CR1_SBK_Pos)              /*!< 0x00000001 */\n#define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */\n#define USART_CR1_RWU_Pos             (1U)\n#define USART_CR1_RWU_Msk             (0x1UL << USART_CR1_RWU_Pos)              /*!< 0x00000002 */\n#define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */\n#define USART_CR1_RE_Pos              (2U)\n#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */\n#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */\n#define USART_CR1_TE_Pos              (3U)\n#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */\n#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */\n#define USART_CR1_IDLEIE_Pos          (4U)\n#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */\n#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */\n#define USART_CR1_RXNEIE_Pos          (5U)\n#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */\n#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */\n#define USART_CR1_TCIE_Pos            (6U)\n#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */\n#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */\n#define USART_CR1_TXEIE_Pos           (7U)\n#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */\n#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<TXE Interrupt Enable                   */\n#define USART_CR1_PEIE_Pos            (8U)\n#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */\n#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */\n#define USART_CR1_PS_Pos              (9U)\n#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */\n#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */\n#define USART_CR1_PCE_Pos             (10U)\n#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */\n#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */\n#define USART_CR1_WAKE_Pos            (11U)\n#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */\n#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */\n#define USART_CR1_M_Pos               (12U)\n#define USART_CR1_M_Msk               (0x1UL << USART_CR1_M_Pos)                /*!< 0x00001000 */\n#define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */\n#define USART_CR1_UE_Pos              (13U)\n#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00002000 */\n#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */\n#define USART_CR1_OVER8_Pos           (15U)\n#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */\n#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */\n\n/******************  Bit definition for USART_CR2 register  *******************/\n#define USART_CR2_ADD_Pos             (0U)\n#define USART_CR2_ADD_Msk             (0xFUL << USART_CR2_ADD_Pos)              /*!< 0x0000000F */\n#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */\n#define USART_CR2_LBDL_Pos            (5U)\n#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */\n#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */\n#define USART_CR2_LBDIE_Pos           (6U)\n#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */\n#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */\n#define USART_CR2_LBCL_Pos            (8U)\n#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */\n#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */\n#define USART_CR2_CPHA_Pos            (9U)\n#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */\n#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */\n#define USART_CR2_CPOL_Pos            (10U)\n#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */\n#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */\n#define USART_CR2_CLKEN_Pos           (11U)\n#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */\n#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */\n\n#define USART_CR2_STOP_Pos            (12U)\n#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */\n#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */\n#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x1000 */\n#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x2000 */\n\n#define USART_CR2_LINEN_Pos           (14U)\n#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */\n#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */\n\n/******************  Bit definition for USART_CR3 register  *******************/\n#define USART_CR3_EIE_Pos             (0U)\n#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */\n#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */\n#define USART_CR3_IREN_Pos            (1U)\n#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */\n#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */\n#define USART_CR3_IRLP_Pos            (2U)\n#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */\n#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */\n#define USART_CR3_HDSEL_Pos           (3U)\n#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */\n#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */\n#define USART_CR3_NACK_Pos            (4U)\n#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */\n#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */\n#define USART_CR3_SCEN_Pos            (5U)\n#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */\n#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */\n#define USART_CR3_DMAR_Pos            (6U)\n#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */\n#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */\n#define USART_CR3_DMAT_Pos            (7U)\n#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */\n#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */\n#define USART_CR3_RTSE_Pos            (8U)\n#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */\n#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */\n#define USART_CR3_CTSE_Pos            (9U)\n#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */\n#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */\n#define USART_CR3_CTSIE_Pos           (10U)\n#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */\n#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */\n#define USART_CR3_ONEBIT_Pos          (11U)\n#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */\n#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */\n\n/******************  Bit definition for USART_GTPR register  ******************/\n#define USART_GTPR_PSC_Pos            (0U)\n#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */\n#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */\n#define USART_GTPR_PSC_0              (0x01UL << USART_GTPR_PSC_Pos)            /*!< 0x0001 */\n#define USART_GTPR_PSC_1              (0x02UL << USART_GTPR_PSC_Pos)            /*!< 0x0002 */\n#define USART_GTPR_PSC_2              (0x04UL << USART_GTPR_PSC_Pos)            /*!< 0x0004 */\n#define USART_GTPR_PSC_3              (0x08UL << USART_GTPR_PSC_Pos)            /*!< 0x0008 */\n#define USART_GTPR_PSC_4              (0x10UL << USART_GTPR_PSC_Pos)            /*!< 0x0010 */\n#define USART_GTPR_PSC_5              (0x20UL << USART_GTPR_PSC_Pos)            /*!< 0x0020 */\n#define USART_GTPR_PSC_6              (0x40UL << USART_GTPR_PSC_Pos)            /*!< 0x0040 */\n#define USART_GTPR_PSC_7              (0x80UL << USART_GTPR_PSC_Pos)            /*!< 0x0080 */\n\n#define USART_GTPR_GT_Pos             (8U)\n#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */\n#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            Window WATCHDOG                                 */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for WWDG_CR register  ********************/\n#define WWDG_CR_T_Pos           (0U)\n#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */\n#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\n#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x01 */\n#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x02 */\n#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x04 */\n#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x08 */\n#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x10 */\n#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x20 */\n#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x40 */\n/* Legacy defines */\n#define  WWDG_CR_T0                          WWDG_CR_T_0\n#define  WWDG_CR_T1                          WWDG_CR_T_1\n#define  WWDG_CR_T2                          WWDG_CR_T_2\n#define  WWDG_CR_T3                          WWDG_CR_T_3\n#define  WWDG_CR_T4                          WWDG_CR_T_4\n#define  WWDG_CR_T5                          WWDG_CR_T_5\n#define  WWDG_CR_T6                          WWDG_CR_T_6\n\n#define WWDG_CR_WDGA_Pos        (7U)\n#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */\n#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */\n\n/*******************  Bit definition for WWDG_CFR register  *******************/\n#define WWDG_CFR_W_Pos          (0U)\n#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */\n#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */\n#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x0001 */\n#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x0002 */\n#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x0004 */\n#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x0008 */\n#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x0010 */\n#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x0020 */\n#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x0040 */\n/* Legacy defines */\n#define  WWDG_CFR_W0                         WWDG_CFR_W_0\n#define  WWDG_CFR_W1                         WWDG_CFR_W_1\n#define  WWDG_CFR_W2                         WWDG_CFR_W_2\n#define  WWDG_CFR_W3                         WWDG_CFR_W_3\n#define  WWDG_CFR_W4                         WWDG_CFR_W_4\n#define  WWDG_CFR_W5                         WWDG_CFR_W_5\n#define  WWDG_CFR_W6                         WWDG_CFR_W_6\n\n#define WWDG_CFR_WDGTB_Pos      (7U)\n#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */\n#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */\n#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */\n#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */\n/* Legacy defines */\n#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0\n#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1\n\n#define WWDG_CFR_EWI_Pos        (9U)\n#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */\n#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */\n\n/*******************  Bit definition for WWDG_SR register  ********************/\n#define WWDG_SR_EWIF_Pos        (0U)\n#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */\n#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                DBG                                         */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for DBGMCU_IDCODE register  *************/\n#define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)\n#define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\n#define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk\n#define DBGMCU_IDCODE_REV_ID_Pos                     (16U)\n#define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\n#define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk\n\n/********************  Bit definition for DBGMCU_CR register  *****************/\n#define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)\n#define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */\n#define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk\n#define DBGMCU_CR_DBG_STOP_Pos                       (1U)\n#define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk\n#define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)\n#define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */\n#define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk\n#define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)\n#define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */\n#define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk\n\n#define DBGMCU_CR_TRACE_MODE_Pos                     (6U)\n#define DBGMCU_CR_TRACE_MODE_Msk                     (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */\n#define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk\n#define DBGMCU_CR_TRACE_MODE_0                       (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */\n#define DBGMCU_CR_TRACE_MODE_1                       (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */\n\n/********************  Bit definition for DBGMCU_APB1_FZ register  ************/\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk\n/* Old IWDGSTOP bit definition, maintained for legacy purpose */\n#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP\n\n/********************  Bit definition for DBGMCU_APB2_FZ register  ************/\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                                       USB_OTG                              */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/\n#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)\n#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */\n#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)\n#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\n#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */\n#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)\n#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)\n#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */\n#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)\n#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)\n#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */\n#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */\n#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)\n#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */\n#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */\n#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)\n#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */\n#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)\n#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */\n#define USB_OTG_GOTGCTL_BSVLD_Pos                (19U)\n#define USB_OTG_GOTGCTL_BSVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGCTL_BSVLD                    USB_OTG_GOTGCTL_BSVLD_Msk     /*!< B-session valid */\n\n/********************  Bit definition forUSB_OTG_HCFG register  ********************/\n\n#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)\n#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\n#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */\n#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCFG_FSLSS_Pos                   (2U)\n#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */\n\n/********************  Bit definition for USB_OTG_DCFG register  ********************/\n\n#define USB_OTG_DCFG_DSPD_Pos                    (0U)\n#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\n#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */\n#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)\n#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */\n\n#define USB_OTG_DCFG_DAD_Pos                     (4U)\n#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\n#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */\n#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\n\n#define USB_OTG_DCFG_PFIVL_Pos                   (11U)\n#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\n#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */\n#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\n\n#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)\n#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */\n#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk        /*!< Transceiver delay */\n\n#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)\n#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */\n#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk        /*!< Erratic error interrupt mask */\n\n#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)\n#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\n#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */\n#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\n#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\n\n/********************  Bit definition for USB_OTG_PCGCR register  ********************/\n#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)\n#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */\n#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)\n#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */\n#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)\n#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */\n\n/********************  Bit definition for USB_OTG_GOTGINT register  ********************/\n#define USB_OTG_GOTGINT_SEDET_Pos                (2U)\n#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */\n#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)\n#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */\n#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)\n#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */\n#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)\n#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */\n#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)\n#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */\n#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)\n#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */\n\n/********************  Bit definition for USB_OTG_DCTL register  ********************/\n#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)\n#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */\n#define USB_OTG_DCTL_SDIS_Pos                    (1U)\n#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */\n#define USB_OTG_DCTL_GINSTS_Pos                  (2U)\n#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */\n#define USB_OTG_DCTL_GONSTS_Pos                  (3U)\n#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\n#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */\n\n#define USB_OTG_DCTL_TCTL_Pos                    (4U)\n#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\n#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */\n#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCTL_SGINAK_Pos                  (7U)\n#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */\n#define USB_OTG_DCTL_CGINAK_Pos                  (8U)\n#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */\n#define USB_OTG_DCTL_SGONAK_Pos                  (9U)\n#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */\n#define USB_OTG_DCTL_CGONAK_Pos                  (10U)\n#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\n#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */\n#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)\n#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */\n\n/********************  Bit definition for USB_OTG_HFIR register  ********************/\n#define USB_OTG_HFIR_FRIVL_Pos                   (0U)\n#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */\n\n/********************  Bit definition for USB_OTG_HFNUM register  ********************/\n#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)\n#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */\n#define USB_OTG_HFNUM_FTREM_Pos                  (16U)\n#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */\n\n/********************  Bit definition for USB_OTG_DSTS register  ********************/\n#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)\n#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */\n\n#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)\n#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\n#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */\n#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\n#define USB_OTG_DSTS_EERR_Pos                    (3U)\n#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\n#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */\n#define USB_OTG_DSTS_FNSOF_Pos                   (8U)\n#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\n#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */\n\n/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/\n#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)\n#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\n#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */\n#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)\n#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\n#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */\n#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */\n#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */\n#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */\n#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */\n#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */\n#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)\n#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */\n#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)\n#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */\n#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)\n#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\n#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */\n\n/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/\n\n#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)\n#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\n#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */\n#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\n#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\n#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\n#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)\n#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\n#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\n#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)\n#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\n#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */\n#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)\n#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\n#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */\n#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)\n#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\n#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */\n#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\n#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\n#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\n#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\n#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)\n#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */\n#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)\n#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\n#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */\n#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)\n#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\n#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */\n#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)\n#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\n#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */\n#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)\n#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\n#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */\n#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)\n#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\n#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */\n#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)\n#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\n#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */\n#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)\n#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\n#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */\n#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)\n#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\n#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */\n#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)\n#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\n#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */\n#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)\n#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */\n\n/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/\n#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)\n#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\n#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */\n#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)\n#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\n#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */\n#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)\n#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\n#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */\n#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)\n#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\n#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */\n#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)\n#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\n#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */\n\n\n#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)\n#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\n#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */\n#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\n#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\n#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)\n#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\n#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */\n#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)\n#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\n#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */\n\n/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/\n#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)\n#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)\n#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)\n#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)\n#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)\n#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/\n#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)\n#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */\n#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)\n#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */\n#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)\n#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */\n#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\n\n/********************  Bit definition for USB_OTG_HAINT register  ********************/\n#define USB_OTG_HAINT_HAINT_Pos                  (0U)\n#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */\n\n/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/\n#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask              */\n#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */\n#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)\n#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */\n#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */\n#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)\n#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */\n#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)\n#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */\n#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)\n#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */\n#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */\n#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)\n#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */\n#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)\n#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */\n#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)\n#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */\n#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)\n#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */\n#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)\n#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */\n/********************  Bit definition for USB_OTG_GINTSTS register  ********************/\n#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)\n#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\n#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */\n#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)\n#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */\n#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)\n#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */\n#define USB_OTG_GINTSTS_SOF_Pos                  (3U)\n#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */\n#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)\n#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */\n#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)\n#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */\n#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)\n#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */\n#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)\n#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */\n#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)\n#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */\n#define USB_OTG_GINTSTS_USBRST_Pos               (12U)\n#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */\n#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)\n#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */\n#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)\n#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */\n#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)\n#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */\n#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)\n#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */\n#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)\n#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */\n#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)\n#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */\n#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)\n#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */\n#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)\n#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */\n#define USB_OTG_GINTSTS_HCINT_Pos                (25U)\n#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */\n#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)\n#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */\n#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)\n#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */\n#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)\n#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */\n#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)\n#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */\n#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)\n#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */\n\n/********************  Bit definition for USB_OTG_GINTMSK register  ********************/\n#define USB_OTG_GINTMSK_MMISM_Pos                (1U)\n#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */\n#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)\n#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */\n#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)\n#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */\n#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)\n#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */\n#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)\n#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */\n#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)\n#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */\n#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)\n#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */\n#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)\n#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */\n#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)\n#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */\n#define USB_OTG_GINTMSK_USBRST_Pos               (12U)\n#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */\n#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)\n#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */\n#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)\n#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */\n#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)\n#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */\n#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)\n#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\n#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */\n#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)\n#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */\n#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)\n#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */\n#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)\n#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */\n#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)\n#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */\n#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)\n#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */\n#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)\n#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */\n#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)\n#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */\n#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)\n#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */\n#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)\n#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */\n#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)\n#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */\n#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)\n#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */\n\n/********************  Bit definition for USB_OTG_DAINT register  ********************/\n#define USB_OTG_DAINT_IEPINT_Pos                 (0U)\n#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */\n#define USB_OTG_DAINT_OEPINT_Pos                 (16U)\n#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */\n\n/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/\n#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)\n#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */\n\n/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/\n#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)\n#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\n#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */\n#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)\n#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\n#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)\n#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\n#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)\n#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/\n#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)\n#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */\n#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)\n#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/\n#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)\n#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/\n#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)\n#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */\n\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_NPTXFSA_Pos                      (0U)\n#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */\n#define USB_OTG_NPTXFD_Pos                       (16U)\n#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */\n#define USB_OTG_TX0FSA_Pos                       (0U)\n#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */\n#define USB_OTG_TX0FD_Pos                        (16U)\n#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */\n\n/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/\n#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)\n#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\n#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\n\n/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\n\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/\n#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)\n#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\n#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\n#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)\n#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\n#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */\n\n#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)\n#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\n#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */\n#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)\n#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\n#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */\n\n#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)\n#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */\n#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\n#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)\n#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\n#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */\n\n/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DEACHINT register  ********************/\n#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)\n#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */\n#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)\n#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */\n\n/********************  Bit definition for USB_OTG_GCCFG register  ********************/\n#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)\n#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\n#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */\n#define USB_OTG_GCCFG_I2CPADEN_Pos               (17U)\n#define USB_OTG_GCCFG_I2CPADEN_Msk               (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_GCCFG_I2CPADEN                   USB_OTG_GCCFG_I2CPADEN_Msk    /*!< Enable I2C bus connection for the external I2C PHY interface*/\n#define USB_OTG_GCCFG_VBUSASEN_Pos               (18U)\n#define USB_OTG_GCCFG_VBUSASEN_Msk               (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_GCCFG_VBUSASEN                   USB_OTG_GCCFG_VBUSASEN_Msk    /*!< Enable the VBUS sensing device */\n#define USB_OTG_GCCFG_VBUSBSEN_Pos               (19U)\n#define USB_OTG_GCCFG_VBUSBSEN_Msk               (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_GCCFG_VBUSBSEN                   USB_OTG_GCCFG_VBUSBSEN_Msk    /*!< Enable the VBUS sensing device */\n#define USB_OTG_GCCFG_SOFOUTEN_Pos               (20U)\n#define USB_OTG_GCCFG_SOFOUTEN_Msk               (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_GCCFG_SOFOUTEN                   USB_OTG_GCCFG_SOFOUTEN_Msk    /*!< SOF output enable */\n#define USB_OTG_GCCFG_NOVBUSSENS_Pos             (21U)\n#define USB_OTG_GCCFG_NOVBUSSENS_Msk             (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */\n#define USB_OTG_GCCFG_NOVBUSSENS                 USB_OTG_GCCFG_NOVBUSSENS_Msk  /*!< VBUS sensing disable option*/\n\n/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\n\n/********************  Bit definition for USB_OTG_CID register  ********************/\n#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)\n#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */\n\n/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */\n#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPRT register  ********************/\n#define USB_OTG_HPRT_PCSTS_Pos                   (0U)\n#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */\n#define USB_OTG_HPRT_PCDET_Pos                   (1U)\n#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\n#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */\n#define USB_OTG_HPRT_PENA_Pos                    (2U)\n#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\n#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */\n#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)\n#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\n#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */\n#define USB_OTG_HPRT_POCA_Pos                    (4U)\n#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\n#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */\n#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)\n#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\n#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */\n#define USB_OTG_HPRT_PRES_Pos                    (6U)\n#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\n#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */\n#define USB_OTG_HPRT_PSUSP_Pos                   (7U)\n#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\n#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */\n#define USB_OTG_HPRT_PRST_Pos                    (8U)\n#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\n#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */\n\n#define USB_OTG_HPRT_PLSTS_Pos                   (10U)\n#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\n#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */\n#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\n#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_HPRT_PPWR_Pos                    (12U)\n#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */\n\n#define USB_OTG_HPRT_PTCTL_Pos                   (13U)\n#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\n#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */\n#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\n#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\n#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\n#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\n\n#define USB_OTG_HPRT_PSPD_Pos                    (17U)\n#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\n#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */\n#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\n\n/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */\n#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */\n#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */\n#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)\n#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */\n#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)\n#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */\n\n/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/\n#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)\n#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */\n#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)\n#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */\n\n/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/\n#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */\n#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */\n#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)\n#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\n#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */\n#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */\n\n#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */\n#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DIEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */\n\n#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)\n#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\n#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */\n#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\n#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\n#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\n#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\n#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */\n#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */\n#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */\n#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */\n#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */\n\n/********************  Bit definition for USB_OTG_HCCHAR register  ********************/\n#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)\n#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */\n\n#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)\n#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\n#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */\n#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\n#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)\n#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */\n#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)\n#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */\n\n#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)\n#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */\n#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\n\n#define USB_OTG_HCCHAR_MC_Pos                    (20U)\n#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\n#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */\n#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\n#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\n\n#define USB_OTG_HCCHAR_DAD_Pos                   (22U)\n#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\n#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */\n#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\n#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\n#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\n#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\n#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\n#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\n#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\n#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)\n#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */\n#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)\n#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */\n#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)\n#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */\n\n/********************  Bit definition for USB_OTG_HCSPLT register  ********************/\n\n#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)\n#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\n#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */\n#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\n\n#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)\n#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\n#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */\n#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\n\n#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)\n#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\n#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */\n#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)\n#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\n#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */\n#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)\n#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */\n\n/********************  Bit definition for USB_OTG_HCINT register  ********************/\n#define USB_OTG_HCINT_XFRC_Pos                   (0U)\n#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */\n#define USB_OTG_HCINT_CHH_Pos                    (1U)\n#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */\n#define USB_OTG_HCINT_AHBERR_Pos                 (2U)\n#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */\n#define USB_OTG_HCINT_STALL_Pos                  (3U)\n#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */\n#define USB_OTG_HCINT_NAK_Pos                    (4U)\n#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */\n#define USB_OTG_HCINT_ACK_Pos                    (5U)\n#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */\n#define USB_OTG_HCINT_NYET_Pos                   (6U)\n#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */\n#define USB_OTG_HCINT_TXERR_Pos                  (7U)\n#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */\n#define USB_OTG_HCINT_BBERR_Pos                  (8U)\n#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */\n#define USB_OTG_HCINT_FRMOR_Pos                  (9U)\n#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */\n#define USB_OTG_HCINT_DTERR_Pos                  (10U)\n#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */\n\n/********************  Bit definition for USB_OTG_DIEPINT register  ********************/\n#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)\n#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */\n#define USB_OTG_DIEPINT_TOC_Pos                  (3U)\n#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */\n#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)\n#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */\n#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)\n#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */\n#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */\n#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)\n#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */\n#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)\n#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\n#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\n#define USB_OTG_DIEPINT_BNA_Pos                  (9U)\n#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */\n#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)\n#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\n#define USB_OTG_DIEPINT_BERR_Pos                 (12U)\n#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\n#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */\n#define USB_OTG_DIEPINT_NAK_Pos                  (13U)\n#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */\n\n/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/\n#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)\n#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */\n#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)\n#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */\n#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)\n#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */\n#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)\n#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */\n#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)\n#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */\n#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)\n#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */\n#define USB_OTG_HCINTMSK_NYET_Pos                (6U)\n#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */\n#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)\n#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */\n#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)\n#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */\n#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)\n#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */\n#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)\n#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */\n\n/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/\n\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)\n#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */\n/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/\n#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)\n#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */\n#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)\n#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */\n#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)\n#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */\n#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)\n#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\n#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */\n#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/\n#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)\n#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_HCDMA register  ********************/\n#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)\n#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/\n#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)\n#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */\n\n/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/\n#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)\n#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */\n#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)\n#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/\n\n#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */\n#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */\n#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\n#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */\n#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */\n#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)\n#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\n#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */\n#define USB_OTG_DOEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */\n#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */\n#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */\n#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */\n\n/********************  Bit definition for USB_OTG_DOEPINT register  ********************/\n#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)\n#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */\n#define USB_OTG_DOEPINT_STUP_Pos                 (3U)\n#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */\n#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)\n#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */\n#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)\n#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */\n#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */\n#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)\n#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */\n#define USB_OTG_DOEPINT_NAK_Pos                  (13U)\n#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */\n#define USB_OTG_DOEPINT_NYET_Pos                 (14U)\n#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */\n#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)\n#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */\n/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/\n\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n\n#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)\n#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */\n#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for PCGCCTL register  ********************/\n#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)\n#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */\n#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)\n#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */\n#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)\n#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */\n\n/* Legacy define */\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_CHNUM_Pos                        (0U)\n#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\n#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\n#define USB_OTG_BCNT_Pos                         (4U)\n#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\n\n#define USB_OTG_DPID_Pos                         (15U)\n#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)    /*!< 0x00018000 */\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\n#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\n#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\n\n#define USB_OTG_PKTSTS_Pos                       (17U)\n#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\n#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\n#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\n#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\n#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\n\n#define USB_OTG_EPNUM_Pos                        (0U)\n#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\n#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\n\n#define USB_OTG_FRMNUM_Pos                       (21U)\n#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\n#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\n#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\n#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\n#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_macros\n  * @{\n  */\n\n/******************************* ADC Instances ********************************/\n#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\n\n#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)\n/******************************* CRC Instances ********************************/\n#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\n\n\n/******************************** DMA Instances *******************************/\n#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \\\n                                              ((INSTANCE) == DMA1_Stream1) || \\\n                                              ((INSTANCE) == DMA1_Stream2) || \\\n                                              ((INSTANCE) == DMA1_Stream3) || \\\n                                              ((INSTANCE) == DMA1_Stream4) || \\\n                                              ((INSTANCE) == DMA1_Stream5) || \\\n                                              ((INSTANCE) == DMA1_Stream6) || \\\n                                              ((INSTANCE) == DMA1_Stream7) || \\\n                                              ((INSTANCE) == DMA2_Stream0) || \\\n                                              ((INSTANCE) == DMA2_Stream1) || \\\n                                              ((INSTANCE) == DMA2_Stream2) || \\\n                                              ((INSTANCE) == DMA2_Stream3) || \\\n                                              ((INSTANCE) == DMA2_Stream4) || \\\n                                              ((INSTANCE) == DMA2_Stream5) || \\\n                                              ((INSTANCE) == DMA2_Stream6) || \\\n                                              ((INSTANCE) == DMA2_Stream7))\n\n/******************************* GPIO Instances *******************************/\n#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\\n                                        ((INSTANCE) == GPIOB) || \\\n                                        ((INSTANCE) == GPIOC) || \\\n                                        ((INSTANCE) == GPIOD) || \\\n                                        ((INSTANCE) == GPIOE) || \\\n                                        ((INSTANCE) == GPIOH))\n\n/******************************** I2C Instances *******************************/\n#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\n                                       ((INSTANCE) == I2C2) || \\\n                                       ((INSTANCE) == I2C3))\n\n/******************************* SMBUS Instances ******************************/\n#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE\n\n/******************************** I2S Instances *******************************/\n\n#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI1) || \\\n                                        ((INSTANCE) == SPI2) || \\\n                                        ((INSTANCE) == SPI3) || \\\n                                        ((INSTANCE) == SPI4) || \\\n                                        ((INSTANCE) == SPI5))\n\n/*************************** I2S Extended Instances ***************************/\n#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \\\n                                           ((INSTANCE) == I2S3ext))\n/* Legacy Defines */\n#define IS_I2S_ALL_INSTANCE_EXT    IS_I2S_EXT_ALL_INSTANCE\n\n\n/****************************** RTC Instances *********************************/\n#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\n\n\n/******************************** SPI Instances *******************************/\n\n#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\\n                                       ((INSTANCE) == SPI2) || \\\n                                       ((INSTANCE) == SPI3) || \\\n                                       ((INSTANCE) == SPI4) || \\\n                                       ((INSTANCE) == SPI5))\n\n\n/****************** TIM Instances : All supported instances *******************/\n#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\\n                                   ((INSTANCE) == TIM2)   || \\\n                                   ((INSTANCE) == TIM3)   || \\\n                                   ((INSTANCE) == TIM4)   || \\\n                                   ((INSTANCE) == TIM5)   || \\\n                                   ((INSTANCE) == TIM9)   || \\\n                                   ((INSTANCE) == TIM10)  || \\\n                                   ((INSTANCE) == TIM11))\n\n/************* TIM Instances : at least 1 capture/compare channel *************/\n#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \\\n                                         ((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM3)  || \\\n                                         ((INSTANCE) == TIM4)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM9)  || \\\n                                         ((INSTANCE) == TIM10) || \\\n                                         ((INSTANCE) == TIM11))\n\n/************ TIM Instances : at least 2 capture/compare channels *************/\n#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM9))\n\n/************ TIM Instances : at least 3 capture/compare channels *************/\n#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5))\n\n/************ TIM Instances : at least 4 capture/compare channels *************/\n#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5))\n\n/******************** TIM Instances : Advanced-control timers *****************/\n#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)\n\n/******************* TIM Instances : Timer input XOR function *****************/\n#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5))\n\n/****************** TIM Instances : DMA requests generation (UDE) *************/\n#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5))\n\n/************ TIM Instances : DMA requests generation (CCxDE) *****************/\n#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5))\n\n/************ TIM Instances : DMA requests generation (COMDE) *****************/\n#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5))\n\n/******************** TIM Instances : DMA burst feature ***********************/\n#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                             ((INSTANCE) == TIM2) || \\\n                                             ((INSTANCE) == TIM3) || \\\n                                             ((INSTANCE) == TIM4) || \\\n                                             ((INSTANCE) == TIM5))\n\n/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\n#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5))\n\n/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\n#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM9))\n/********************** TIM Instances : 32 bit Counter ************************/\n#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \\\n                                              ((INSTANCE) == TIM5))\n\n/***************** TIM Instances : external trigger input availabe ************/\n#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                        ((INSTANCE) == TIM2) || \\\n                                        ((INSTANCE) == TIM3) || \\\n                                        ((INSTANCE) == TIM4) || \\\n                                        ((INSTANCE) == TIM5))\n\n/****************** TIM Instances : remapping capability **********************/\n#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM11))\n\n/******************* TIM Instances : output(s) available **********************/\n#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\\n    ((((INSTANCE) == TIM1) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM2) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM3) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM4) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM5) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM9) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM10) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM11) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1))))\n\n/************ TIM Instances : complementary output(s) available ***************/\n#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\\n   ((((INSTANCE) == TIM1) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3))))\n\n/****************** TIM Instances : supporting counting mode selection ********/\n#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5))\n\n/****************** TIM Instances : supporting clock division *****************/\n#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\\n                                                  ((INSTANCE) == TIM2)   || \\\n                                                  ((INSTANCE) == TIM3)   || \\\n                                                  ((INSTANCE) == TIM4)   || \\\n                                                  ((INSTANCE) == TIM5)   || \\\n                                                  ((INSTANCE) == TIM9)   || \\\n                                                  ((INSTANCE) == TIM10)  || \\\n                                                  ((INSTANCE) == TIM11))\n\n/****************** TIM Instances : supporting commutation event generation ***/\n\n#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)\n\n/****************** TIM Instances : supporting OCxREF clear *******************/\n#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM2) || \\\n                                                       ((INSTANCE) == TIM3) || \\\n                                                       ((INSTANCE) == TIM4) || \\\n                                                       ((INSTANCE) == TIM5))\n\n/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM9))\n\n/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5))\n\n/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/\n#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM9))\n\n/********** TIM Instances : supporting internal trigger inputs(ITRX) *********/\n#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM9))\n\n/****************** TIM Instances : supporting repetition counter *************/\n#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1))\n\n/****************** TIM Instances : supporting encoder interface **************/\n#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                      ((INSTANCE) == TIM2) || \\\n                                                      ((INSTANCE) == TIM3) || \\\n                                                      ((INSTANCE) == TIM4) || \\\n                                                      ((INSTANCE) == TIM5) || \\\n                                                      ((INSTANCE) == TIM9))\n/****************** TIM Instances : supporting Hall sensor interface **********/\n#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                          ((INSTANCE) == TIM2) || \\\n                                                          ((INSTANCE) == TIM3) || \\\n                                                          ((INSTANCE) == TIM4) || \\\n                                                          ((INSTANCE) == TIM5))\n/****************** TIM Instances : supporting the break function *************/\n#define IS_TIM_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1))\n\n/******************** USART Instances : Synchronous mode **********************/\n#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                     ((INSTANCE) == USART2) || \\\n                                     ((INSTANCE) == USART6))\n\n/******************** UART Instances : Half-Duplex mode **********************/\n#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                               ((INSTANCE) == USART2) || \\\n                                               ((INSTANCE) == USART6))\n\n/* Legacy defines */\n#define IS_UART_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE\n\n/****************** UART Instances : Hardware Flow control ********************/\n#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                           ((INSTANCE) == USART2) || \\\n                                           ((INSTANCE) == USART6))\n/******************** UART Instances : LIN mode **********************/\n#define IS_UART_LIN_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE\n\n/********************* UART Instances : Smart card mode ***********************/\n#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                         ((INSTANCE) == USART2) || \\\n                                         ((INSTANCE) == USART6))\n\n/*********************** UART Instances : IRDA mode ***************************/\n#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2) || \\\n                                    ((INSTANCE) == USART6))\n\n/*********************** PCD Instances ****************************************/\n#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))\n\n/*********************** HCD Instances ****************************************/\n#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))\n\n/****************************** SDIO Instances ********************************/\n#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)\n\n/****************************** IWDG Instances ********************************/\n#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)\n\n/****************************** WWDG Instances ********************************/\n#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)\n\n/****************************** USB Exported Constants ************************/\n#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U\n#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */\n#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */\n#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */\n\n/*\n * @brief Specific devices reset values definitions\n */\n#define RCC_PLLCFGR_RST_VALUE              0x24003010U\n#define RCC_PLLI2SCFGR_RST_VALUE           0x20003010U\n\n#define RCC_MAX_FREQUENCY           100000000U         /*!< Max frequency of family in Hz*/\n#define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */\n#define RCC_MAX_FREQUENCY_SCALE2     84000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */\n#define RCC_MAX_FREQUENCY_SCALE3     64000000U         /*!< Maximum frequency for system clock at power scale3, in Hz */\n#define RCC_PLLVCO_OUTPUT_MIN       100000000U       /*!< Frequency min for PLLVCO output, in Hz */\n#define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */\n\n#define RCC_PLLN_MIN_VALUE                 50U\n#define RCC_PLLN_MAX_VALUE                432U\n\n#define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */\n#define FLASH_SCALE1_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */\n#define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */\n\n#define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */\n#define FLASH_SCALE2_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */\n\n#define FLASH_SCALE3_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */\n#define FLASH_SCALE3_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */\n\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32F411xE_H */\n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f412rx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f412rx.h\n  * @author  MCD Application Team\n  * @version V2.6.4\n  * @date    06-December-2019\n  * @brief   CMSIS STM32F412Rx Device Peripheral Access Layer Header File.\n  *\n  *          This file contains:\n  *           - Data structures and the address mapping for all peripherals\n  *           - peripherals registers declarations and bits definition\n  *           - Macros to access peripheral's registers hardware\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS_Device\n  * @{\n  */\n\n/** @addtogroup stm32f412rx\n  * @{\n  */\n\n#ifndef __STM32F412Rx_H\n#define __STM32F412Rx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Configuration_section_for_CMSIS\n  * @{\n  */\n\n/**\n  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals\n  */\n#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */\n#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */\n#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */\n#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */\n#define __FPU_PRESENT             1U       /*!< FPU present                                   */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_interrupt_number_definition\n  * @{\n  */\n\n/**\n * @brief STM32F4XX Interrupt Number Definition, according to the selected device\n *        in @ref Library_configuration_section\n */\ntypedef enum\n{\n/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */\n  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */\n  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */\n  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */\n  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */\n  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */\n/******  STM32 specific Interrupt Numbers **********************************************************************/\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */\n  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */\n  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\n  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\n  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\n  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\n  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\n  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\n  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\n  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\n  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\n  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */\n  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */\n  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */\n  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */\n  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */\n  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */\n  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */\n  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */\n  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */\n  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */\n  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */\n  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\n  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */\n  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */\n  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\n  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\n  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */\n  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */\n  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */\n  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\n  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */\n  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */\n  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\n  TIM6_IRQn                   = 54,     /*!< TIM6 global interrupt                                             */\n  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */\n  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */\n  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */\n  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */\n  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */\n  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */\n  DFSDM1_FLT0_IRQn            = 61,     /*!< DFSDM1 Filter 0 global Interrupt                                  */\n  DFSDM1_FLT1_IRQn            = 62,     /*!< DFSDM1 Filter 1 global Interrupt                                  */\n  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */\n  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */\n  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */\n  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */\n  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */\n  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */\n  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */\n  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */\n  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */\n  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\n  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\n  RNG_IRQn                    = 80,     /*!< RNG global Interrupt                                              */\n  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */\n  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */\n  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */\n  QUADSPI_IRQn                = 92,     /*!< QuadSPI global Interrupt                                          */\n  FMPI2C1_EV_IRQn             = 95,     /*!< FMPI2C1 Event Interrupt                                           */\n  FMPI2C1_ER_IRQn             = 96      /*!< FMPI2C1 Error Interrupt                                           */\n} IRQn_Type;\n\n/**\n  * @}\n  */\n\n#include \"core_cm4.h\"             /* Cortex-M4 processor and core peripherals */\n#include \"system_stm32f4xx.h\"\n#include <sys/stdint.h>\n\n/** @addtogroup Peripheral_registers_structures\n  * @{\n  */\n\n/**\n  * @brief Analog to Digital Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */\n  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */\n  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */\n  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */\n  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */\n  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\n  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\n  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\n  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\n  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */\n  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */\n  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */\n  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */\n  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */\n  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/\n  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */\n  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */\n  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */\n  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */\n  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */\n} ADC_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */\n  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */\n  __IO uint32_t CDR;    /*!< ADC common regular data register for dual\n                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */\n} ADC_Common_TypeDef;\n\n\n/**\n  * @brief Controller Area Network TxMailBox\n  */\n\ntypedef struct\n{\n  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */\n  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\n  __IO uint32_t TDLR; /*!< CAN mailbox data low register */\n  __IO uint32_t TDHR; /*!< CAN mailbox data high register */\n} CAN_TxMailBox_TypeDef;\n\n/**\n  * @brief Controller Area Network FIFOMailBox\n  */\n\ntypedef struct\n{\n  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */\n  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\n  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\n  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\n} CAN_FIFOMailBox_TypeDef;\n\n/**\n  * @brief Controller Area Network FilterRegister\n  */\n\ntypedef struct\n{\n  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\n  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\n} CAN_FilterRegister_TypeDef;\n\n/**\n  * @brief Controller Area Network\n  */\n\ntypedef struct\n{\n  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */\n  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */\n  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */\n  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */\n  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */\n  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */\n  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */\n  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */\n  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */\n  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */\n  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */\n  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */\n  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */\n  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */\n  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */\n  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */\n  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */\n  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */\n  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */\n  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */\n  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */\n  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */\n} CAN_TypeDef;\n\n/**\n  * @brief CRC calculation unit\n  */\n\ntypedef struct\n{\n  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */\n  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */\n  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */\n  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */\n  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */\n} CRC_TypeDef;\n\n/**\n  * @brief DFSDM module registers\n  */\ntypedef struct\n{\n  __IO uint32_t FLTCR1;      /*!< DFSDM control register1,                          Address offset: 0x100 */\n  __IO uint32_t FLTCR2;      /*!< DFSDM control register2,                          Address offset: 0x104 */\n  __IO uint32_t FLTISR;      /*!< DFSDM interrupt and status register,              Address offset: 0x108 */\n  __IO uint32_t FLTICR;      /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */\n  __IO uint32_t FLTJCHGR;    /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */\n  __IO uint32_t FLTFCR;      /*!< DFSDM filter control register,                    Address offset: 0x114 */\n  __IO uint32_t FLTJDATAR;   /*!< DFSDM data register for injected group,           Address offset: 0x118 */\n  __IO uint32_t FLTRDATAR;   /*!< DFSDM data register for regular group,            Address offset: 0x11C */\n  __IO uint32_t FLTAWHTR;    /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */\n  __IO uint32_t FLTAWLTR;    /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */\n  __IO uint32_t FLTAWSR;     /*!< DFSDM analog watchdog status register             Address offset: 0x128 */\n  __IO uint32_t FLTAWCFR;    /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */\n  __IO uint32_t FLTEXMAX;    /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */\n  __IO uint32_t FLTEXMIN;    /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */\n  __IO uint32_t FLTCNVTIMR;  /*!< DFSDM conversion timer,                           Address offset: 0x138 */\n} DFSDM_Filter_TypeDef;\n\n/**\n  * @brief DFSDM channel configuration registers\n  */\ntypedef struct\n{\n  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */\n  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */\n  __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and\n                                  short circuit detector register,                  Address offset: 0x08 */\n  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */\n  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */\n} DFSDM_Channel_TypeDef;\n\n/**\n  * @brief Debug MCU\n  */\n\ntypedef struct\n{\n  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */\n  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */\n  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */\n  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */\n}DBGMCU_TypeDef;\n\n\n/**\n  * @brief DMA Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;     /*!< DMA stream x configuration register      */\n  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */\n  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */\n  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */\n  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */\n  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */\n} DMA_Stream_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */\n  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */\n  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */\n  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\n} DMA_TypeDef;\n\n/**\n  * @brief External Interrupt/Event Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */\n  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */\n  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */\n  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\n  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */\n  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */\n} EXTI_TypeDef;\n\n/**\n  * @brief FLASH Registers\n  */\n\ntypedef struct\n{\n  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */\n  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */\n  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */\n  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */\n  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */\n  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */\n  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */\n} FLASH_TypeDef;\n\n\n\n/**\n  * @brief Flexible Static Memory Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\n} FSMC_Bank1_TypeDef;\n\n/**\n  * @brief Flexible Static Memory Controller Bank1E\n  */\n\ntypedef struct\n{\n  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\n} FSMC_Bank1E_TypeDef;\n/**\n  * @brief General Purpose I/O\n  */\n\ntypedef struct\n{\n  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */\n  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */\n  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */\n  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\n  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */\n  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */\n  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */\n  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */\n  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\n} GPIO_TypeDef;\n\n/**\n  * @brief System configuration controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */\n  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */\n  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\n  uint32_t      RESERVED;     /*!< Reserved, 0x18                                                               */\n  __IO uint32_t CFGR2;        /*!< SYSCFG Configuration register2,                    Address offset: 0x1C      */\n  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */\n  __IO uint32_t CFGR;         /*!< SYSCFG Configuration register,                     Address offset: 0x24      */\n} SYSCFG_TypeDef;\n\n/**\n  * @brief Inter-integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */\n  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */\n  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */\n  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */\n  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */\n  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */\n  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */\n  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */\n  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */\n} I2C_TypeDef;\n\n/**\n  * @brief Inter-integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< FMPI2C Control register 1,            Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< FMPI2C Control register 2,            Address offset: 0x04 */\n  __IO uint32_t OAR1;        /*!< FMPI2C Own address 1 register,        Address offset: 0x08 */\n  __IO uint32_t OAR2;        /*!< FMPI2C Own address 2 register,        Address offset: 0x0C */\n  __IO uint32_t TIMINGR;     /*!< FMPI2C Timing register,               Address offset: 0x10 */\n  __IO uint32_t TIMEOUTR;    /*!< FMPI2C Timeout register,              Address offset: 0x14 */\n  __IO uint32_t ISR;         /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */\n  __IO uint32_t ICR;         /*!< FMPI2C Interrupt clear register,      Address offset: 0x1C */\n  __IO uint32_t PECR;        /*!< FMPI2C PEC register,                  Address offset: 0x20 */\n  __IO uint32_t RXDR;        /*!< FMPI2C Receive data register,         Address offset: 0x24 */\n  __IO uint32_t TXDR;        /*!< FMPI2C Transmit data register,        Address offset: 0x28 */\n} FMPI2C_TypeDef;\n\n/**\n  * @brief Independent WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */\n  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */\n  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */\n  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */\n} IWDG_TypeDef;\n\n\n/**\n  * @brief Power Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */\n  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */\n} PWR_TypeDef;\n\n/**\n  * @brief Reset and Clock Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */\n  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */\n  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */\n  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */\n  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */\n  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */\n  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */\n  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */\n  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */\n  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */\n  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */\n  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */\n  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */\n  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */\n  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */\n  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */\n  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */\n  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\n  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\n  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\n  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */\n  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\n  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\n  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */\n  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */\n  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */\n  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */\n  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */\n  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */\n  uint32_t      RESERVED7;     /*!< Reserved, 0x88                                                                    */\n  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */\n  __IO uint32_t CKGATENR;      /*!< RCC Clocks Gated ENable Register,                           Address offset: 0x90  */\n  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x94 */\n} RCC_TypeDef;\n\n/**\n  * @brief Real-Time Clock\n  */\n\ntypedef struct\n{\n  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */\n  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */\n  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */\n  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */\n  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */\n  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */\n  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */\n  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */\n  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */\n  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */\n  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */\n  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */\n  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */\n  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */\n  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */\n  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */\n  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */\n  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */\n  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */\n  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */\n  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */\n  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */\n  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */\n  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */\n  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */\n  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */\n  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */\n  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */\n  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */\n  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */\n  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */\n  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */\n  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */\n  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */\n  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */\n  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */\n  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */\n  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */\n  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */\n  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */\n} RTC_TypeDef;\n\n/**\n  * @brief SD host Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t POWER;                 /*!< SDIO power control register,    Address offset: 0x00 */\n  __IO uint32_t CLKCR;                 /*!< SDI clock control register,     Address offset: 0x04 */\n  __IO uint32_t ARG;                   /*!< SDIO argument register,         Address offset: 0x08 */\n  __IO uint32_t CMD;                   /*!< SDIO command register,          Address offset: 0x0C */\n  __IO const uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */\n  __IO const uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */\n  __IO const uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */\n  __IO const uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */\n  __IO const uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */\n  __IO uint32_t DTIMER;                /*!< SDIO data timer register,       Address offset: 0x24 */\n  __IO uint32_t DLEN;                  /*!< SDIO data length register,      Address offset: 0x28 */\n  __IO uint32_t DCTRL;                 /*!< SDIO data control register,     Address offset: 0x2C */\n  __IO const uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */\n  __IO const uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */\n  __IO uint32_t ICR;                   /*!< SDIO interrupt clear register,  Address offset: 0x38 */\n  __IO uint32_t MASK;                  /*!< SDIO mask register,             Address offset: 0x3C */\n  uint32_t      RESERVED0[2];          /*!< Reserved, 0x40-0x44                                  */\n  __IO const uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */\n  uint32_t      RESERVED1[13];         /*!< Reserved, 0x4C-0x7C                                  */\n  __IO uint32_t FIFO;                  /*!< SDIO data FIFO register,        Address offset: 0x80 */\n} SDIO_TypeDef;\n\n/**\n  * @brief Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */\n  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */\n  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */\n  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\n  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */\n  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */\n  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */\n  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */\n} SPI_TypeDef;\n\n/**\n  * @brief QUAD Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */\n  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */\n  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */\n  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */\n  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */\n  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */\n  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */\n  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */\n  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */\n  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */\n  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */\n  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */\n  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */\n} QUADSPI_TypeDef;\n\n/**\n  * @brief TIM\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */\n  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */\n  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */\n  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */\n  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */\n  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\n  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\n  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */\n  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */\n  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */\n  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */\n  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */\n  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */\n  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */\n  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */\n  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */\n  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */\n  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */\n  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */\n  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */\n} TIM_TypeDef;\n\n/**\n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */\n  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */\n  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */\n  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */\n  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */\n  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */\n  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */\n} USART_TypeDef;\n\n/**\n  * @brief Window WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */\n  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */\n  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */\n} WWDG_TypeDef;\n\n/**\n  * @brief RNG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */\n  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */\n  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */\n} RNG_TypeDef;\n\n/**\n  * @brief USB_OTG_Core_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */\n  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */\n  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */\n  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */\n  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */\n  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */\n  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */\n  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */\n  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */\n  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */\n  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */\n  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */\n  uint32_t Reserved30[2];             /*!< Reserved                                     030h */\n  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */\n  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */\n  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */\n  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */\n  uint32_t  Reserved6;                /*!< Reserved                                     050h */\n  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */\n  uint32_t  Reserved;                 /*!< Reserved                                     058h */\n  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */\n  uint32_t  Reserved43[40];           /*!< Reserved                                058h-0FFh */\n  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */\n  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                        */\n} USB_OTG_GlobalTypeDef;\n\n/**\n  * @brief USB_OTG_device_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */\n  __IO uint32_t DCTL;            /*!< dev Control Register         804h */\n  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */\n  uint32_t Reserved0C;           /*!< Reserved                     80Ch */\n  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */\n  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */\n  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */\n  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */\n  uint32_t  Reserved20;          /*!< Reserved                     820h */\n  uint32_t Reserved9;            /*!< Reserved                     824h */\n  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */\n  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */\n  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */\n  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */\n  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */\n  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */\n  uint32_t Reserved40;           /*!< dedicated EP mask            840h */\n  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */\n  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */\n  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */\n} USB_OTG_DeviceTypeDef;\n\n/**\n  * @brief USB_OTG_IN_Endpoint-Specific_Register\n  */\ntypedef struct\n{\n  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */\n  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */\n  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */\n  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\n  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\n} USB_OTG_INEndpointTypeDef;\n\n/**\n  * @brief USB_OTG_OUT_Endpoint-Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */\n  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */\n  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */\n  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\n} USB_OTG_OUTEndpointTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Mode_Register_Structures\n  */\ntypedef struct\n{\n  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */\n  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */\n  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */\n  uint32_t Reserved40C;           /*!< Reserved                             40Ch */\n  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */\n  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */\n  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */\n} USB_OTG_HostTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Channel_Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */\n  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */\n  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */\n  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */\n  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */\n  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */\n  uint32_t Reserved[2];           /*!< Reserved                                      */\n} USB_OTG_HostChannelTypeDef;\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_memory_map\n  * @{\n  */\n#define FLASH_BASE            0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region                         */\n#define SRAM1_BASE            0x20000000UL /*!< SRAM1(256 KB) base address in the alias region                             */\n#define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */\n#define FSMC_R_BASE           0xA0000000UL /*!< FSMC registers base address                                                */\n#define QSPI_R_BASE           0xA0001000UL /*!< QuadSPI registers base address                                             */\n#define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(256 KB) base address in the bit-band region                          */\n#define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */\n#define FLASH_END             0x080FFFFFUL /*!< FLASH end address                                                          */\n#define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */\n#define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */\n\n/* Legacy defines */\n#define SRAM_BASE             SRAM1_BASE\n#define SRAM_BB_BASE          SRAM1_BB_BASE\n\n/*!< Peripheral memory map */\n#define APB1PERIPH_BASE       PERIPH_BASE\n#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)\n#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)\n#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)\n\n/*!< APB1 peripherals */\n#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)\n#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)\n#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)\n#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)\n#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)\n#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)\n#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)\n#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)\n#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)\n#define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)\n#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)\n#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)\n#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400UL)\n#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)\n#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)\n#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000UL)\n#define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)\n#define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)\n#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)\n#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)\n#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)\n#define FMPI2C1_BASE          (APB1PERIPH_BASE + 0x6000UL)\n#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)\n#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)\n#define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)\n\n/*!< APB2 peripherals */\n#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)\n#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)\n#define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)\n#define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)\n#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)\n#define ADC1_COMMON_BASE      (APB2PERIPH_BASE + 0x2300UL)\n/* Legacy define */\n#define ADC_BASE               ADC1_COMMON_BASE\n#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)\n#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)\n#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400UL)\n#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)\n#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)\n#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)\n#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)\n#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)\n#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000UL)\n#define DFSDM1_BASE           (APB2PERIPH_BASE + 0x6000UL)\n#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)\n#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)\n#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)\n#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)\n#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)\n#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)\n\n/*!< AHB1 peripherals */\n#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)\n#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)\n#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)\n#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)\n#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)\n#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)\n#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)\n#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)\n#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)\n#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)\n#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)\n#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)\n#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)\n#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)\n#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)\n#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)\n#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)\n#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)\n#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)\n#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)\n#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)\n#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)\n#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)\n#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)\n#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)\n#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)\n\n/*!< AHB2 peripherals */\n#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800UL)\n\n\n/*!< FSMC Bankx registers base address */\n#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000UL)\n#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104UL)\n\n/*!< Debug MCU registers base address */\n#define DBGMCU_BASE           0xE0042000UL\n/*!< USB registers base address */\n#define USB_OTG_FS_PERIPH_BASE               0x50000000UL\n\n#define USB_OTG_GLOBAL_BASE                  0x000UL\n#define USB_OTG_DEVICE_BASE                  0x800UL\n#define USB_OTG_IN_ENDPOINT_BASE             0x900UL\n#define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL\n#define USB_OTG_EP_REG_SIZE                  0x20UL\n#define USB_OTG_HOST_BASE                    0x400UL\n#define USB_OTG_HOST_PORT_BASE               0x440UL\n#define USB_OTG_HOST_CHANNEL_BASE            0x500UL\n#define USB_OTG_HOST_CHANNEL_SIZE            0x20UL\n#define USB_OTG_PCGCCTL_BASE                 0xE00UL\n#define USB_OTG_FIFO_BASE                    0x1000UL\n#define USB_OTG_FIFO_SIZE                    0x1000UL\n\n#define UID_BASE                     0x1FFF7A10UL           /*!< Unique device ID register base address */\n#define FLASHSIZE_BASE               0x1FFF7A22UL           /*!< FLASH Size register base address       */\n#define PACKAGE_BASE                 0x1FFF7BF0UL           /*!< Package size register base address     */\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_declaration\n  * @{\n  */\n#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\n#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\n#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\n#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\n#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\n#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\n#define TIM12               ((TIM_TypeDef *) TIM12_BASE)\n#define TIM13               ((TIM_TypeDef *) TIM13_BASE)\n#define TIM14               ((TIM_TypeDef *) TIM14_BASE)\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\n#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\n#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\n#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)\n#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\n#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\n#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)\n#define USART2              ((USART_TypeDef *) USART2_BASE)\n#define USART3              ((USART_TypeDef *) USART3_BASE)\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\n#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\n#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\n#define FMPI2C1             ((FMPI2C_TypeDef *) FMPI2C1_BASE)\n#define CAN1                ((CAN_TypeDef *) CAN1_BASE)\n#define CAN2                ((CAN_TypeDef *) CAN2_BASE)\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\n#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\n#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\n#define USART1              ((USART_TypeDef *) USART1_BASE)\n#define USART6              ((USART_TypeDef *) USART6_BASE)\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\n#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)\n/* Legacy define */\n#define ADC                  ADC1_COMMON\n#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\n#define SPI4                ((SPI_TypeDef *) SPI4_BASE)\n#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\n#define TIM9                ((TIM_TypeDef *) TIM9_BASE)\n#define TIM10               ((TIM_TypeDef *) TIM10_BASE)\n#define TIM11               ((TIM_TypeDef *) TIM11_BASE)\n#define SPI5                ((SPI_TypeDef *) SPI5_BASE)\n#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)\n#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)\n#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)\n#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)\n#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)\n#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\n#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\n#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\n#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\n#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\n#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\n#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\n#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\n#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\n#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\n#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\n#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\n#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\n#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\n#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\n#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\n#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\n#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\n#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\n#define RNG                 ((RNG_TypeDef *) RNG_BASE)\n#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)\n#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)\n#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)\n#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\n#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_constants\n  * @{\n  */\n\n  /** @addtogroup Peripheral_Registers_Bits_Definition\n  * @{\n  */\n\n/******************************************************************************/\n/*                         Peripheral Registers_Bits_Definition               */\n/******************************************************************************/\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Analog to Digital Converter                         */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for ADC_SR register  ********************/\n#define ADC_SR_AWD_Pos            (0U)\n#define ADC_SR_AWD_Msk            (0x1UL << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */\n#define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */\n#define ADC_SR_EOC_Pos            (1U)\n#define ADC_SR_EOC_Msk            (0x1UL << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */\n#define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */\n#define ADC_SR_JEOC_Pos           (2U)\n#define ADC_SR_JEOC_Msk           (0x1UL << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */\n#define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */\n#define ADC_SR_JSTRT_Pos          (3U)\n#define ADC_SR_JSTRT_Msk          (0x1UL << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */\n#define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */\n#define ADC_SR_STRT_Pos           (4U)\n#define ADC_SR_STRT_Msk           (0x1UL << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */\n#define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */\n#define ADC_SR_OVR_Pos            (5U)\n#define ADC_SR_OVR_Msk            (0x1UL << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */\n#define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */\n\n/*******************  Bit definition for ADC_CR1 register  ********************/\n#define ADC_CR1_AWDCH_Pos         (0U)\n#define ADC_CR1_AWDCH_Msk         (0x1FUL << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */\n#define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\n#define ADC_CR1_AWDCH_0           (0x01UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */\n#define ADC_CR1_AWDCH_1           (0x02UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */\n#define ADC_CR1_AWDCH_2           (0x04UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */\n#define ADC_CR1_AWDCH_3           (0x08UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */\n#define ADC_CR1_AWDCH_4           (0x10UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */\n#define ADC_CR1_EOCIE_Pos         (5U)\n#define ADC_CR1_EOCIE_Msk         (0x1UL << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */\n#define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */\n#define ADC_CR1_AWDIE_Pos         (6U)\n#define ADC_CR1_AWDIE_Msk         (0x1UL << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */\n#define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */\n#define ADC_CR1_JEOCIE_Pos        (7U)\n#define ADC_CR1_JEOCIE_Msk        (0x1UL << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */\n#define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */\n#define ADC_CR1_SCAN_Pos          (8U)\n#define ADC_CR1_SCAN_Msk          (0x1UL << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */\n#define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */\n#define ADC_CR1_AWDSGL_Pos        (9U)\n#define ADC_CR1_AWDSGL_Msk        (0x1UL << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */\n#define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */\n#define ADC_CR1_JAUTO_Pos         (10U)\n#define ADC_CR1_JAUTO_Msk         (0x1UL << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */\n#define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */\n#define ADC_CR1_DISCEN_Pos        (11U)\n#define ADC_CR1_DISCEN_Msk        (0x1UL << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */\n#define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */\n#define ADC_CR1_JDISCEN_Pos       (12U)\n#define ADC_CR1_JDISCEN_Msk       (0x1UL << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */\n#define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */\n#define ADC_CR1_DISCNUM_Pos       (13U)\n#define ADC_CR1_DISCNUM_Msk       (0x7UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */\n#define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\n#define ADC_CR1_DISCNUM_0         (0x1UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */\n#define ADC_CR1_DISCNUM_1         (0x2UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */\n#define ADC_CR1_DISCNUM_2         (0x4UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */\n#define ADC_CR1_JAWDEN_Pos        (22U)\n#define ADC_CR1_JAWDEN_Msk        (0x1UL << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */\n#define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */\n#define ADC_CR1_AWDEN_Pos         (23U)\n#define ADC_CR1_AWDEN_Msk         (0x1UL << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */\n#define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */\n#define ADC_CR1_RES_Pos           (24U)\n#define ADC_CR1_RES_Msk           (0x3UL << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */\n#define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */\n#define ADC_CR1_RES_0             (0x1UL << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */\n#define ADC_CR1_RES_1             (0x2UL << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */\n#define ADC_CR1_OVRIE_Pos         (26U)\n#define ADC_CR1_OVRIE_Msk         (0x1UL << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */\n#define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */\n\n/*******************  Bit definition for ADC_CR2 register  ********************/\n#define ADC_CR2_ADON_Pos          (0U)\n#define ADC_CR2_ADON_Msk          (0x1UL << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */\n#define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */\n#define ADC_CR2_CONT_Pos          (1U)\n#define ADC_CR2_CONT_Msk          (0x1UL << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */\n#define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */\n#define ADC_CR2_DMA_Pos           (8U)\n#define ADC_CR2_DMA_Msk           (0x1UL << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */\n#define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */\n#define ADC_CR2_DDS_Pos           (9U)\n#define ADC_CR2_DDS_Msk           (0x1UL << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */\n#define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */\n#define ADC_CR2_EOCS_Pos          (10U)\n#define ADC_CR2_EOCS_Msk          (0x1UL << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */\n#define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */\n#define ADC_CR2_ALIGN_Pos         (11U)\n#define ADC_CR2_ALIGN_Msk         (0x1UL << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */\n#define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */\n#define ADC_CR2_JEXTSEL_Pos       (16U)\n#define ADC_CR2_JEXTSEL_Msk       (0xFUL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */\n#define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */\n#define ADC_CR2_JEXTSEL_0         (0x1UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */\n#define ADC_CR2_JEXTSEL_1         (0x2UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */\n#define ADC_CR2_JEXTSEL_2         (0x4UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */\n#define ADC_CR2_JEXTSEL_3         (0x8UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */\n#define ADC_CR2_JEXTEN_Pos        (20U)\n#define ADC_CR2_JEXTEN_Msk        (0x3UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */\n#define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\n#define ADC_CR2_JEXTEN_0          (0x1UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */\n#define ADC_CR2_JEXTEN_1          (0x2UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */\n#define ADC_CR2_JSWSTART_Pos      (22U)\n#define ADC_CR2_JSWSTART_Msk      (0x1UL << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */\n#define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */\n#define ADC_CR2_EXTSEL_Pos        (24U)\n#define ADC_CR2_EXTSEL_Msk        (0xFUL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */\n#define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\n#define ADC_CR2_EXTSEL_0          (0x1UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */\n#define ADC_CR2_EXTSEL_1          (0x2UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */\n#define ADC_CR2_EXTSEL_2          (0x4UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */\n#define ADC_CR2_EXTSEL_3          (0x8UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */\n#define ADC_CR2_EXTEN_Pos         (28U)\n#define ADC_CR2_EXTEN_Msk         (0x3UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */\n#define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\n#define ADC_CR2_EXTEN_0           (0x1UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */\n#define ADC_CR2_EXTEN_1           (0x2UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */\n#define ADC_CR2_SWSTART_Pos       (30U)\n#define ADC_CR2_SWSTART_Msk       (0x1UL << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */\n#define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */\n\n/******************  Bit definition for ADC_SMPR1 register  *******************/\n#define ADC_SMPR1_SMP10_Pos       (0U)\n#define ADC_SMPR1_SMP10_Msk       (0x7UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */\n#define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\n#define ADC_SMPR1_SMP10_0         (0x1UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */\n#define ADC_SMPR1_SMP10_1         (0x2UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */\n#define ADC_SMPR1_SMP10_2         (0x4UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */\n#define ADC_SMPR1_SMP11_Pos       (3U)\n#define ADC_SMPR1_SMP11_Msk       (0x7UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */\n#define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\n#define ADC_SMPR1_SMP11_0         (0x1UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */\n#define ADC_SMPR1_SMP11_1         (0x2UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */\n#define ADC_SMPR1_SMP11_2         (0x4UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */\n#define ADC_SMPR1_SMP12_Pos       (6U)\n#define ADC_SMPR1_SMP12_Msk       (0x7UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */\n#define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\n#define ADC_SMPR1_SMP12_0         (0x1UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */\n#define ADC_SMPR1_SMP12_1         (0x2UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */\n#define ADC_SMPR1_SMP12_2         (0x4UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */\n#define ADC_SMPR1_SMP13_Pos       (9U)\n#define ADC_SMPR1_SMP13_Msk       (0x7UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */\n#define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\n#define ADC_SMPR1_SMP13_0         (0x1UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */\n#define ADC_SMPR1_SMP13_1         (0x2UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */\n#define ADC_SMPR1_SMP13_2         (0x4UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */\n#define ADC_SMPR1_SMP14_Pos       (12U)\n#define ADC_SMPR1_SMP14_Msk       (0x7UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */\n#define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\n#define ADC_SMPR1_SMP14_0         (0x1UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */\n#define ADC_SMPR1_SMP14_1         (0x2UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */\n#define ADC_SMPR1_SMP14_2         (0x4UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */\n#define ADC_SMPR1_SMP15_Pos       (15U)\n#define ADC_SMPR1_SMP15_Msk       (0x7UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */\n#define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\n#define ADC_SMPR1_SMP15_0         (0x1UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */\n#define ADC_SMPR1_SMP15_1         (0x2UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */\n#define ADC_SMPR1_SMP15_2         (0x4UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */\n#define ADC_SMPR1_SMP16_Pos       (18U)\n#define ADC_SMPR1_SMP16_Msk       (0x7UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */\n#define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\n#define ADC_SMPR1_SMP16_0         (0x1UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */\n#define ADC_SMPR1_SMP16_1         (0x2UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */\n#define ADC_SMPR1_SMP16_2         (0x4UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */\n#define ADC_SMPR1_SMP17_Pos       (21U)\n#define ADC_SMPR1_SMP17_Msk       (0x7UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */\n#define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\n#define ADC_SMPR1_SMP17_0         (0x1UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */\n#define ADC_SMPR1_SMP17_1         (0x2UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */\n#define ADC_SMPR1_SMP17_2         (0x4UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */\n#define ADC_SMPR1_SMP18_Pos       (24U)\n#define ADC_SMPR1_SMP18_Msk       (0x7UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */\n#define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\n#define ADC_SMPR1_SMP18_0         (0x1UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */\n#define ADC_SMPR1_SMP18_1         (0x2UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */\n#define ADC_SMPR1_SMP18_2         (0x4UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */\n\n/******************  Bit definition for ADC_SMPR2 register  *******************/\n#define ADC_SMPR2_SMP0_Pos        (0U)\n#define ADC_SMPR2_SMP0_Msk        (0x7UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */\n#define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\n#define ADC_SMPR2_SMP0_0          (0x1UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */\n#define ADC_SMPR2_SMP0_1          (0x2UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */\n#define ADC_SMPR2_SMP0_2          (0x4UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */\n#define ADC_SMPR2_SMP1_Pos        (3U)\n#define ADC_SMPR2_SMP1_Msk        (0x7UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */\n#define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\n#define ADC_SMPR2_SMP1_0          (0x1UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */\n#define ADC_SMPR2_SMP1_1          (0x2UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */\n#define ADC_SMPR2_SMP1_2          (0x4UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */\n#define ADC_SMPR2_SMP2_Pos        (6U)\n#define ADC_SMPR2_SMP2_Msk        (0x7UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */\n#define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\n#define ADC_SMPR2_SMP2_0          (0x1UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */\n#define ADC_SMPR2_SMP2_1          (0x2UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */\n#define ADC_SMPR2_SMP2_2          (0x4UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */\n#define ADC_SMPR2_SMP3_Pos        (9U)\n#define ADC_SMPR2_SMP3_Msk        (0x7UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */\n#define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\n#define ADC_SMPR2_SMP3_0          (0x1UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */\n#define ADC_SMPR2_SMP3_1          (0x2UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */\n#define ADC_SMPR2_SMP3_2          (0x4UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */\n#define ADC_SMPR2_SMP4_Pos        (12U)\n#define ADC_SMPR2_SMP4_Msk        (0x7UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */\n#define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\n#define ADC_SMPR2_SMP4_0          (0x1UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */\n#define ADC_SMPR2_SMP4_1          (0x2UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */\n#define ADC_SMPR2_SMP4_2          (0x4UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */\n#define ADC_SMPR2_SMP5_Pos        (15U)\n#define ADC_SMPR2_SMP5_Msk        (0x7UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */\n#define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\n#define ADC_SMPR2_SMP5_0          (0x1UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */\n#define ADC_SMPR2_SMP5_1          (0x2UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */\n#define ADC_SMPR2_SMP5_2          (0x4UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */\n#define ADC_SMPR2_SMP6_Pos        (18U)\n#define ADC_SMPR2_SMP6_Msk        (0x7UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */\n#define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\n#define ADC_SMPR2_SMP6_0          (0x1UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */\n#define ADC_SMPR2_SMP6_1          (0x2UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */\n#define ADC_SMPR2_SMP6_2          (0x4UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */\n#define ADC_SMPR2_SMP7_Pos        (21U)\n#define ADC_SMPR2_SMP7_Msk        (0x7UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */\n#define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\n#define ADC_SMPR2_SMP7_0          (0x1UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */\n#define ADC_SMPR2_SMP7_1          (0x2UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */\n#define ADC_SMPR2_SMP7_2          (0x4UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */\n#define ADC_SMPR2_SMP8_Pos        (24U)\n#define ADC_SMPR2_SMP8_Msk        (0x7UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */\n#define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\n#define ADC_SMPR2_SMP8_0          (0x1UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */\n#define ADC_SMPR2_SMP8_1          (0x2UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */\n#define ADC_SMPR2_SMP8_2          (0x4UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */\n#define ADC_SMPR2_SMP9_Pos        (27U)\n#define ADC_SMPR2_SMP9_Msk        (0x7UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */\n#define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\n#define ADC_SMPR2_SMP9_0          (0x1UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */\n#define ADC_SMPR2_SMP9_1          (0x2UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */\n#define ADC_SMPR2_SMP9_2          (0x4UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */\n\n/******************  Bit definition for ADC_JOFR1 register  *******************/\n#define ADC_JOFR1_JOFFSET1_Pos    (0U)\n#define ADC_JOFR1_JOFFSET1_Msk    (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */\n\n/******************  Bit definition for ADC_JOFR2 register  *******************/\n#define ADC_JOFR2_JOFFSET2_Pos    (0U)\n#define ADC_JOFR2_JOFFSET2_Msk    (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */\n\n/******************  Bit definition for ADC_JOFR3 register  *******************/\n#define ADC_JOFR3_JOFFSET3_Pos    (0U)\n#define ADC_JOFR3_JOFFSET3_Msk    (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */\n\n/******************  Bit definition for ADC_JOFR4 register  *******************/\n#define ADC_JOFR4_JOFFSET4_Pos    (0U)\n#define ADC_JOFR4_JOFFSET4_Msk    (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */\n\n/*******************  Bit definition for ADC_HTR register  ********************/\n#define ADC_HTR_HT_Pos            (0U)\n#define ADC_HTR_HT_Msk            (0xFFFUL << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */\n#define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */\n\n/*******************  Bit definition for ADC_LTR register  ********************/\n#define ADC_LTR_LT_Pos            (0U)\n#define ADC_LTR_LT_Msk            (0xFFFUL << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */\n#define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */\n\n/*******************  Bit definition for ADC_SQR1 register  *******************/\n#define ADC_SQR1_SQ13_Pos         (0U)\n#define ADC_SQR1_SQ13_Msk         (0x1FUL << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */\n#define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\n#define ADC_SQR1_SQ13_0           (0x01UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */\n#define ADC_SQR1_SQ13_1           (0x02UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */\n#define ADC_SQR1_SQ13_2           (0x04UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */\n#define ADC_SQR1_SQ13_3           (0x08UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */\n#define ADC_SQR1_SQ13_4           (0x10UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */\n#define ADC_SQR1_SQ14_Pos         (5U)\n#define ADC_SQR1_SQ14_Msk         (0x1FUL << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */\n#define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\n#define ADC_SQR1_SQ14_0           (0x01UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */\n#define ADC_SQR1_SQ14_1           (0x02UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */\n#define ADC_SQR1_SQ14_2           (0x04UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */\n#define ADC_SQR1_SQ14_3           (0x08UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */\n#define ADC_SQR1_SQ14_4           (0x10UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */\n#define ADC_SQR1_SQ15_Pos         (10U)\n#define ADC_SQR1_SQ15_Msk         (0x1FUL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */\n#define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\n#define ADC_SQR1_SQ15_0           (0x01UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */\n#define ADC_SQR1_SQ15_1           (0x02UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */\n#define ADC_SQR1_SQ15_2           (0x04UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */\n#define ADC_SQR1_SQ15_3           (0x08UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */\n#define ADC_SQR1_SQ15_4           (0x10UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */\n#define ADC_SQR1_SQ16_Pos         (15U)\n#define ADC_SQR1_SQ16_Msk         (0x1FUL << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\n#define ADC_SQR1_SQ16_0           (0x01UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR1_SQ16_1           (0x02UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR1_SQ16_2           (0x04UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR1_SQ16_3           (0x08UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR1_SQ16_4           (0x10UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR1_L_Pos            (20U)\n#define ADC_SQR1_L_Msk            (0xFUL << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */\n#define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */\n#define ADC_SQR1_L_0              (0x1UL << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */\n#define ADC_SQR1_L_1              (0x2UL << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */\n#define ADC_SQR1_L_2              (0x4UL << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */\n#define ADC_SQR1_L_3              (0x8UL << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */\n\n/*******************  Bit definition for ADC_SQR2 register  *******************/\n#define ADC_SQR2_SQ7_Pos          (0U)\n#define ADC_SQR2_SQ7_Msk          (0x1FUL << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\n#define ADC_SQR2_SQ7_0            (0x01UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR2_SQ7_1            (0x02UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR2_SQ7_2            (0x04UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR2_SQ7_3            (0x08UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR2_SQ7_4            (0x10UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR2_SQ8_Pos          (5U)\n#define ADC_SQR2_SQ8_Msk          (0x1FUL << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\n#define ADC_SQR2_SQ8_0            (0x01UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR2_SQ8_1            (0x02UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR2_SQ8_2            (0x04UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR2_SQ8_3            (0x08UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR2_SQ8_4            (0x10UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR2_SQ9_Pos          (10U)\n#define ADC_SQR2_SQ9_Msk          (0x1FUL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\n#define ADC_SQR2_SQ9_0            (0x01UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR2_SQ9_1            (0x02UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR2_SQ9_2            (0x04UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR2_SQ9_3            (0x08UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR2_SQ9_4            (0x10UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR2_SQ10_Pos         (15U)\n#define ADC_SQR2_SQ10_Msk         (0x1FUL << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\n#define ADC_SQR2_SQ10_0           (0x01UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR2_SQ10_1           (0x02UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR2_SQ10_2           (0x04UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR2_SQ10_3           (0x08UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR2_SQ10_4           (0x10UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR2_SQ11_Pos         (20U)\n#define ADC_SQR2_SQ11_Msk         (0x1FUL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */\n#define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\n#define ADC_SQR2_SQ11_0           (0x01UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */\n#define ADC_SQR2_SQ11_1           (0x02UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */\n#define ADC_SQR2_SQ11_2           (0x04UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */\n#define ADC_SQR2_SQ11_3           (0x08UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */\n#define ADC_SQR2_SQ11_4           (0x10UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */\n#define ADC_SQR2_SQ12_Pos         (25U)\n#define ADC_SQR2_SQ12_Msk         (0x1FUL << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */\n#define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\n#define ADC_SQR2_SQ12_0           (0x01UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */\n#define ADC_SQR2_SQ12_1           (0x02UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */\n#define ADC_SQR2_SQ12_2           (0x04UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */\n#define ADC_SQR2_SQ12_3           (0x08UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */\n#define ADC_SQR2_SQ12_4           (0x10UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_SQR3 register  *******************/\n#define ADC_SQR3_SQ1_Pos          (0U)\n#define ADC_SQR3_SQ1_Msk          (0x1FUL << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\n#define ADC_SQR3_SQ1_0            (0x01UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR3_SQ1_1            (0x02UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR3_SQ1_2            (0x04UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR3_SQ1_3            (0x08UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR3_SQ1_4            (0x10UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR3_SQ2_Pos          (5U)\n#define ADC_SQR3_SQ2_Msk          (0x1FUL << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\n#define ADC_SQR3_SQ2_0            (0x01UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR3_SQ2_1            (0x02UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR3_SQ2_2            (0x04UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR3_SQ2_3            (0x08UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR3_SQ2_4            (0x10UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR3_SQ3_Pos          (10U)\n#define ADC_SQR3_SQ3_Msk          (0x1FUL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\n#define ADC_SQR3_SQ3_0            (0x01UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR3_SQ3_1            (0x02UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR3_SQ3_2            (0x04UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR3_SQ3_3            (0x08UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR3_SQ3_4            (0x10UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR3_SQ4_Pos          (15U)\n#define ADC_SQR3_SQ4_Msk          (0x1FUL << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */\n#define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\n#define ADC_SQR3_SQ4_0            (0x01UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */\n#define ADC_SQR3_SQ4_1            (0x02UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */\n#define ADC_SQR3_SQ4_2            (0x04UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */\n#define ADC_SQR3_SQ4_3            (0x08UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */\n#define ADC_SQR3_SQ4_4            (0x10UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */\n#define ADC_SQR3_SQ5_Pos          (20U)\n#define ADC_SQR3_SQ5_Msk          (0x1FUL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */\n#define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\n#define ADC_SQR3_SQ5_0            (0x01UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */\n#define ADC_SQR3_SQ5_1            (0x02UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */\n#define ADC_SQR3_SQ5_2            (0x04UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */\n#define ADC_SQR3_SQ5_3            (0x08UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */\n#define ADC_SQR3_SQ5_4            (0x10UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */\n#define ADC_SQR3_SQ6_Pos          (25U)\n#define ADC_SQR3_SQ6_Msk          (0x1FUL << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */\n#define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\n#define ADC_SQR3_SQ6_0            (0x01UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */\n#define ADC_SQR3_SQ6_1            (0x02UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */\n#define ADC_SQR3_SQ6_2            (0x04UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */\n#define ADC_SQR3_SQ6_3            (0x08UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */\n#define ADC_SQR3_SQ6_4            (0x10UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_JSQR register  *******************/\n#define ADC_JSQR_JSQ1_Pos         (0U)\n#define ADC_JSQR_JSQ1_Msk         (0x1FUL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */\n#define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */\n#define ADC_JSQR_JSQ1_0           (0x01UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */\n#define ADC_JSQR_JSQ1_1           (0x02UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */\n#define ADC_JSQR_JSQ1_2           (0x04UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */\n#define ADC_JSQR_JSQ1_3           (0x08UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */\n#define ADC_JSQR_JSQ1_4           (0x10UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */\n#define ADC_JSQR_JSQ2_Pos         (5U)\n#define ADC_JSQR_JSQ2_Msk         (0x1FUL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */\n#define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\n#define ADC_JSQR_JSQ2_0           (0x01UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */\n#define ADC_JSQR_JSQ2_1           (0x02UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */\n#define ADC_JSQR_JSQ2_2           (0x04UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */\n#define ADC_JSQR_JSQ2_3           (0x08UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */\n#define ADC_JSQR_JSQ2_4           (0x10UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */\n#define ADC_JSQR_JSQ3_Pos         (10U)\n#define ADC_JSQR_JSQ3_Msk         (0x1FUL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */\n#define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\n#define ADC_JSQR_JSQ3_0           (0x01UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */\n#define ADC_JSQR_JSQ3_1           (0x02UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */\n#define ADC_JSQR_JSQ3_2           (0x04UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */\n#define ADC_JSQR_JSQ3_3           (0x08UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */\n#define ADC_JSQR_JSQ3_4           (0x10UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */\n#define ADC_JSQR_JSQ4_Pos         (15U)\n#define ADC_JSQR_JSQ4_Msk         (0x1FUL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */\n#define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\n#define ADC_JSQR_JSQ4_0           (0x01UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */\n#define ADC_JSQR_JSQ4_1           (0x02UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */\n#define ADC_JSQR_JSQ4_2           (0x04UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */\n#define ADC_JSQR_JSQ4_3           (0x08UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */\n#define ADC_JSQR_JSQ4_4           (0x10UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */\n#define ADC_JSQR_JL_Pos           (20U)\n#define ADC_JSQR_JL_Msk           (0x3UL << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */\n#define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */\n#define ADC_JSQR_JL_0             (0x1UL << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */\n#define ADC_JSQR_JL_1             (0x2UL << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */\n\n/*******************  Bit definition for ADC_JDR1 register  *******************/\n#define ADC_JDR1_JDATA_Pos        (0U)\n#define ADC_JDR1_JDATA_Msk        (0xFFFFUL << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR2 register  *******************/\n#define ADC_JDR2_JDATA_Pos        (0U)\n#define ADC_JDR2_JDATA_Msk        (0xFFFFUL << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR3 register  *******************/\n#define ADC_JDR3_JDATA_Pos        (0U)\n#define ADC_JDR3_JDATA_Msk        (0xFFFFUL << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR4 register  *******************/\n#define ADC_JDR4_JDATA_Pos        (0U)\n#define ADC_JDR4_JDATA_Msk        (0xFFFFUL << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */\n\n/********************  Bit definition for ADC_DR register  ********************/\n#define ADC_DR_DATA_Pos           (0U)\n#define ADC_DR_DATA_Msk           (0xFFFFUL << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */\n#define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */\n#define ADC_DR_ADC2DATA_Pos       (16U)\n#define ADC_DR_ADC2DATA_Msk       (0xFFFFUL << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */\n#define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */\n\n/*******************  Bit definition for ADC_CSR register  ********************/\n#define ADC_CSR_AWD1_Pos          (0U)\n#define ADC_CSR_AWD1_Msk          (0x1UL << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */\n#define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */\n#define ADC_CSR_EOC1_Pos          (1U)\n#define ADC_CSR_EOC1_Msk          (0x1UL << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */\n#define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */\n#define ADC_CSR_JEOC1_Pos         (2U)\n#define ADC_CSR_JEOC1_Msk         (0x1UL << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */\n#define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */\n#define ADC_CSR_JSTRT1_Pos        (3U)\n#define ADC_CSR_JSTRT1_Msk        (0x1UL << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */\n#define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */\n#define ADC_CSR_STRT1_Pos         (4U)\n#define ADC_CSR_STRT1_Msk         (0x1UL << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */\n#define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */\n#define ADC_CSR_OVR1_Pos          (5U)\n#define ADC_CSR_OVR1_Msk          (0x1UL << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */\n#define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */\n\n/* Legacy defines */\n#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1\n\n/*******************  Bit definition for ADC_CCR register  ********************/\n#define ADC_CCR_MULTI_Pos         (0U)\n#define ADC_CCR_MULTI_Msk         (0x1FUL << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */\n#define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */\n#define ADC_CCR_MULTI_0           (0x01UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */\n#define ADC_CCR_MULTI_1           (0x02UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */\n#define ADC_CCR_MULTI_2           (0x04UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */\n#define ADC_CCR_MULTI_3           (0x08UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */\n#define ADC_CCR_MULTI_4           (0x10UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */\n#define ADC_CCR_DELAY_Pos         (8U)\n#define ADC_CCR_DELAY_Msk         (0xFUL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */\n#define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */\n#define ADC_CCR_DELAY_0           (0x1UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */\n#define ADC_CCR_DELAY_1           (0x2UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */\n#define ADC_CCR_DELAY_2           (0x4UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */\n#define ADC_CCR_DELAY_3           (0x8UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */\n#define ADC_CCR_DDS_Pos           (13U)\n#define ADC_CCR_DDS_Msk           (0x1UL << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */\n#define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */\n#define ADC_CCR_DMA_Pos           (14U)\n#define ADC_CCR_DMA_Msk           (0x3UL << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */\n#define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */\n#define ADC_CCR_DMA_0             (0x1UL << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */\n#define ADC_CCR_DMA_1             (0x2UL << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */\n#define ADC_CCR_ADCPRE_Pos        (16U)\n#define ADC_CCR_ADCPRE_Msk        (0x3UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */\n#define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */\n#define ADC_CCR_ADCPRE_0          (0x1UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */\n#define ADC_CCR_ADCPRE_1          (0x2UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */\n#define ADC_CCR_VBATE_Pos         (22U)\n#define ADC_CCR_VBATE_Msk         (0x1UL << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */\n#define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */\n#define ADC_CCR_TSVREFE_Pos       (23U)\n#define ADC_CCR_TSVREFE_Msk       (0x1UL << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */\n#define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */\n\n/*******************  Bit definition for ADC_CDR register  ********************/\n#define ADC_CDR_DATA1_Pos         (0U)\n#define ADC_CDR_DATA1_Msk         (0xFFFFUL << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */\n#define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */\n#define ADC_CDR_DATA2_Pos         (16U)\n#define ADC_CDR_DATA2_Msk         (0xFFFFUL << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */\n#define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */\n\n/* Legacy defines */\n#define ADC_CDR_RDATA_MST         ADC_CDR_DATA1\n#define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Controller Area Network                            */\n/*                                                                            */\n/******************************************************************************/\n/*!<CAN control and status registers */\n/*******************  Bit definition for CAN_MCR register  ********************/\n#define CAN_MCR_INRQ_Pos       (0U)\n#define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */\n#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */\n#define CAN_MCR_SLEEP_Pos      (1U)\n#define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */\n#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */\n#define CAN_MCR_TXFP_Pos       (2U)\n#define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */\n#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */\n#define CAN_MCR_RFLM_Pos       (3U)\n#define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */\n#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */\n#define CAN_MCR_NART_Pos       (4U)\n#define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */\n#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */\n#define CAN_MCR_AWUM_Pos       (5U)\n#define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */\n#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */\n#define CAN_MCR_ABOM_Pos       (6U)\n#define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */\n#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */\n#define CAN_MCR_TTCM_Pos       (7U)\n#define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */\n#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */\n#define CAN_MCR_RESET_Pos      (15U)\n#define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */\n#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */\n#define CAN_MCR_DBF_Pos        (16U)\n#define CAN_MCR_DBF_Msk        (0x1UL << CAN_MCR_DBF_Pos)                       /*!< 0x00010000 */\n#define CAN_MCR_DBF            CAN_MCR_DBF_Msk                                 /*!<bxCAN Debug freeze */\n/*******************  Bit definition for CAN_MSR register  ********************/\n#define CAN_MSR_INAK_Pos       (0U)\n#define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */\n#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */\n#define CAN_MSR_SLAK_Pos       (1U)\n#define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */\n#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */\n#define CAN_MSR_ERRI_Pos       (2U)\n#define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */\n#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */\n#define CAN_MSR_WKUI_Pos       (3U)\n#define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */\n#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */\n#define CAN_MSR_SLAKI_Pos      (4U)\n#define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */\n#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */\n#define CAN_MSR_TXM_Pos        (8U)\n#define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */\n#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */\n#define CAN_MSR_RXM_Pos        (9U)\n#define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */\n#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */\n#define CAN_MSR_SAMP_Pos       (10U)\n#define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */\n#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */\n#define CAN_MSR_RX_Pos         (11U)\n#define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */\n#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */\n\n/*******************  Bit definition for CAN_TSR register  ********************/\n#define CAN_TSR_RQCP0_Pos      (0U)\n#define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */\n#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */\n#define CAN_TSR_TXOK0_Pos      (1U)\n#define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */\n#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */\n#define CAN_TSR_ALST0_Pos      (2U)\n#define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */\n#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */\n#define CAN_TSR_TERR0_Pos      (3U)\n#define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */\n#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */\n#define CAN_TSR_ABRQ0_Pos      (7U)\n#define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */\n#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */\n#define CAN_TSR_RQCP1_Pos      (8U)\n#define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */\n#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */\n#define CAN_TSR_TXOK1_Pos      (9U)\n#define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */\n#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */\n#define CAN_TSR_ALST1_Pos      (10U)\n#define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */\n#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */\n#define CAN_TSR_TERR1_Pos      (11U)\n#define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */\n#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */\n#define CAN_TSR_ABRQ1_Pos      (15U)\n#define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */\n#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */\n#define CAN_TSR_RQCP2_Pos      (16U)\n#define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */\n#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */\n#define CAN_TSR_TXOK2_Pos      (17U)\n#define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */\n#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */\n#define CAN_TSR_ALST2_Pos      (18U)\n#define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */\n#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */\n#define CAN_TSR_TERR2_Pos      (19U)\n#define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */\n#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */\n#define CAN_TSR_ABRQ2_Pos      (23U)\n#define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */\n#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */\n#define CAN_TSR_CODE_Pos       (24U)\n#define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */\n#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */\n\n#define CAN_TSR_TME_Pos        (26U)\n#define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */\n#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */\n#define CAN_TSR_TME0_Pos       (26U)\n#define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */\n#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */\n#define CAN_TSR_TME1_Pos       (27U)\n#define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */\n#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */\n#define CAN_TSR_TME2_Pos       (28U)\n#define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */\n#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */\n\n#define CAN_TSR_LOW_Pos        (29U)\n#define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */\n#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */\n#define CAN_TSR_LOW0_Pos       (29U)\n#define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */\n#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */\n#define CAN_TSR_LOW1_Pos       (30U)\n#define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */\n#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */\n#define CAN_TSR_LOW2_Pos       (31U)\n#define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */\n#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */\n\n/*******************  Bit definition for CAN_RF0R register  *******************/\n#define CAN_RF0R_FMP0_Pos      (0U)\n#define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */\n#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */\n#define CAN_RF0R_FULL0_Pos     (3U)\n#define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */\n#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */\n#define CAN_RF0R_FOVR0_Pos     (4U)\n#define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */\n#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */\n#define CAN_RF0R_RFOM0_Pos     (5U)\n#define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */\n#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */\n\n/*******************  Bit definition for CAN_RF1R register  *******************/\n#define CAN_RF1R_FMP1_Pos      (0U)\n#define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */\n#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */\n#define CAN_RF1R_FULL1_Pos     (3U)\n#define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */\n#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */\n#define CAN_RF1R_FOVR1_Pos     (4U)\n#define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */\n#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */\n#define CAN_RF1R_RFOM1_Pos     (5U)\n#define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */\n#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */\n\n/********************  Bit definition for CAN_IER register  *******************/\n#define CAN_IER_TMEIE_Pos      (0U)\n#define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */\n#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */\n#define CAN_IER_FMPIE0_Pos     (1U)\n#define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */\n#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE0_Pos      (2U)\n#define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */\n#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE0_Pos     (3U)\n#define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */\n#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_FMPIE1_Pos     (4U)\n#define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */\n#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE1_Pos      (5U)\n#define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */\n#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE1_Pos     (6U)\n#define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */\n#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)\n#define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */\n#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */\n#define CAN_IER_EPVIE_Pos      (9U)\n#define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */\n#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */\n#define CAN_IER_BOFIE_Pos      (10U)\n#define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */\n#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */\n#define CAN_IER_LECIE_Pos      (11U)\n#define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */\n#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */\n#define CAN_IER_ERRIE_Pos      (15U)\n#define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */\n#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */\n#define CAN_IER_WKUIE_Pos      (16U)\n#define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */\n#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */\n#define CAN_IER_SLKIE_Pos      (17U)\n#define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */\n#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)\n\n/********************  Bit definition for CAN_ESR register  *******************/\n#define CAN_ESR_EWGF_Pos       (0U)\n#define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */\n#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */\n#define CAN_ESR_EPVF_Pos       (1U)\n#define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */\n#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */\n#define CAN_ESR_BOFF_Pos       (2U)\n#define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */\n#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */\n\n#define CAN_ESR_LEC_Pos        (4U)\n#define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */\n#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */\n#define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */\n#define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */\n#define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */\n\n#define CAN_ESR_TEC_Pos        (16U)\n#define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */\n#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */\n#define CAN_ESR_REC_Pos        (24U)\n#define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */\n#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */\n\n/*******************  Bit definition for CAN_BTR register  ********************/\n#define CAN_BTR_BRP_Pos        (0U)\n#define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */\n#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */\n#define CAN_BTR_TS1_Pos        (16U)\n#define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */\n#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */\n#define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */\n#define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */\n#define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */\n#define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */\n#define CAN_BTR_TS2_Pos        (20U)\n#define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */\n#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */\n#define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */\n#define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */\n#define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */\n#define CAN_BTR_SJW_Pos        (24U)\n#define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */\n#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */\n#define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */\n#define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */\n#define CAN_BTR_LBKM_Pos       (30U)\n#define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */\n#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */\n#define CAN_BTR_SILM_Pos       (31U)\n#define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */\n#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */\n\n\n/*!<Mailbox registers */\n/******************  Bit definition for CAN_TI0R register  ********************/\n#define CAN_TI0R_TXRQ_Pos      (0U)\n#define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI0R_RTR_Pos       (1U)\n#define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI0R_IDE_Pos       (2U)\n#define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI0R_EXID_Pos      (3U)\n#define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI0R_STID_Pos      (21U)\n#define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/******************  Bit definition for CAN_TDT0R register  *******************/\n#define CAN_TDT0R_DLC_Pos      (0U)\n#define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT0R_TGT_Pos      (8U)\n#define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT0R_TIME_Pos     (16U)\n#define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/******************  Bit definition for CAN_TDL0R register  *******************/\n#define CAN_TDL0R_DATA0_Pos    (0U)\n#define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL0R_DATA1_Pos    (8U)\n#define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL0R_DATA2_Pos    (16U)\n#define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL0R_DATA3_Pos    (24U)\n#define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/******************  Bit definition for CAN_TDH0R register  *******************/\n#define CAN_TDH0R_DATA4_Pos    (0U)\n#define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH0R_DATA5_Pos    (8U)\n#define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH0R_DATA6_Pos    (16U)\n#define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH0R_DATA7_Pos    (24U)\n#define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI1R register  *******************/\n#define CAN_TI1R_TXRQ_Pos      (0U)\n#define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI1R_RTR_Pos       (1U)\n#define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI1R_IDE_Pos       (2U)\n#define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI1R_EXID_Pos      (3U)\n#define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI1R_STID_Pos      (21U)\n#define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT1R register  ******************/\n#define CAN_TDT1R_DLC_Pos      (0U)\n#define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT1R_TGT_Pos      (8U)\n#define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT1R_TIME_Pos     (16U)\n#define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL1R register  ******************/\n#define CAN_TDL1R_DATA0_Pos    (0U)\n#define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL1R_DATA1_Pos    (8U)\n#define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL1R_DATA2_Pos    (16U)\n#define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL1R_DATA3_Pos    (24U)\n#define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH1R register  ******************/\n#define CAN_TDH1R_DATA4_Pos    (0U)\n#define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH1R_DATA5_Pos    (8U)\n#define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH1R_DATA6_Pos    (16U)\n#define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH1R_DATA7_Pos    (24U)\n#define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI2R register  *******************/\n#define CAN_TI2R_TXRQ_Pos      (0U)\n#define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI2R_RTR_Pos       (1U)\n#define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI2R_IDE_Pos       (2U)\n#define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI2R_EXID_Pos      (3U)\n#define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_TI2R_STID_Pos      (21U)\n#define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT2R register  ******************/\n#define CAN_TDT2R_DLC_Pos      (0U)\n#define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT2R_TGT_Pos      (8U)\n#define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT2R_TIME_Pos     (16U)\n#define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL2R register  ******************/\n#define CAN_TDL2R_DATA0_Pos    (0U)\n#define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL2R_DATA1_Pos    (8U)\n#define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL2R_DATA2_Pos    (16U)\n#define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL2R_DATA3_Pos    (24U)\n#define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH2R register  ******************/\n#define CAN_TDH2R_DATA4_Pos    (0U)\n#define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH2R_DATA5_Pos    (8U)\n#define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH2R_DATA6_Pos    (16U)\n#define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH2R_DATA7_Pos    (24U)\n#define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI0R register  *******************/\n#define CAN_RI0R_RTR_Pos       (1U)\n#define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI0R_IDE_Pos       (2U)\n#define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI0R_EXID_Pos      (3U)\n#define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_RI0R_STID_Pos      (21U)\n#define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT0R register  ******************/\n#define CAN_RDT0R_DLC_Pos      (0U)\n#define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT0R_FMI_Pos      (8U)\n#define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT0R_TIME_Pos     (16U)\n#define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL0R register  ******************/\n#define CAN_RDL0R_DATA0_Pos    (0U)\n#define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL0R_DATA1_Pos    (8U)\n#define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL0R_DATA2_Pos    (16U)\n#define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL0R_DATA3_Pos    (24U)\n#define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH0R register  ******************/\n#define CAN_RDH0R_DATA4_Pos    (0U)\n#define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH0R_DATA5_Pos    (8U)\n#define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH0R_DATA6_Pos    (16U)\n#define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH0R_DATA7_Pos    (24U)\n#define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI1R register  *******************/\n#define CAN_RI1R_RTR_Pos       (1U)\n#define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI1R_IDE_Pos       (2U)\n#define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI1R_EXID_Pos      (3U)\n#define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_RI1R_STID_Pos      (21U)\n#define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT1R register  ******************/\n#define CAN_RDT1R_DLC_Pos      (0U)\n#define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT1R_FMI_Pos      (8U)\n#define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT1R_TIME_Pos     (16U)\n#define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL1R register  ******************/\n#define CAN_RDL1R_DATA0_Pos    (0U)\n#define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL1R_DATA1_Pos    (8U)\n#define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL1R_DATA2_Pos    (16U)\n#define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL1R_DATA3_Pos    (24U)\n#define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH1R register  ******************/\n#define CAN_RDH1R_DATA4_Pos    (0U)\n#define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH1R_DATA5_Pos    (8U)\n#define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH1R_DATA6_Pos    (16U)\n#define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH1R_DATA7_Pos    (24U)\n#define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*!<CAN filter registers */\n/*******************  Bit definition for CAN_FMR register  ********************/\n#define CAN_FMR_FINIT_Pos      (0U)\n#define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */\n#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */\n#define CAN_FMR_CAN2SB_Pos     (8U)\n#define CAN_FMR_CAN2SB_Msk     (0x3FUL << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */\n#define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */\n\n/*******************  Bit definition for CAN_FM1R register  *******************/\n#define CAN_FM1R_FBM_Pos       (0U)\n#define CAN_FM1R_FBM_Msk       (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */\n#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */\n#define CAN_FM1R_FBM0_Pos      (0U)\n#define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */\n#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */\n#define CAN_FM1R_FBM1_Pos      (1U)\n#define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */\n#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */\n#define CAN_FM1R_FBM2_Pos      (2U)\n#define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */\n#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */\n#define CAN_FM1R_FBM3_Pos      (3U)\n#define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */\n#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */\n#define CAN_FM1R_FBM4_Pos      (4U)\n#define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */\n#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */\n#define CAN_FM1R_FBM5_Pos      (5U)\n#define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */\n#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */\n#define CAN_FM1R_FBM6_Pos      (6U)\n#define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */\n#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */\n#define CAN_FM1R_FBM7_Pos      (7U)\n#define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */\n#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */\n#define CAN_FM1R_FBM8_Pos      (8U)\n#define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */\n#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */\n#define CAN_FM1R_FBM9_Pos      (9U)\n#define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */\n#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */\n#define CAN_FM1R_FBM10_Pos     (10U)\n#define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */\n#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */\n#define CAN_FM1R_FBM11_Pos     (11U)\n#define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */\n#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */\n#define CAN_FM1R_FBM12_Pos     (12U)\n#define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */\n#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */\n#define CAN_FM1R_FBM13_Pos     (13U)\n#define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */\n#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */\n#define CAN_FM1R_FBM14_Pos     (14U)\n#define CAN_FM1R_FBM14_Msk     (0x1UL << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */\n#define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */\n#define CAN_FM1R_FBM15_Pos     (15U)\n#define CAN_FM1R_FBM15_Msk     (0x1UL << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */\n#define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */\n#define CAN_FM1R_FBM16_Pos     (16U)\n#define CAN_FM1R_FBM16_Msk     (0x1UL << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */\n#define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */\n#define CAN_FM1R_FBM17_Pos     (17U)\n#define CAN_FM1R_FBM17_Msk     (0x1UL << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */\n#define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */\n#define CAN_FM1R_FBM18_Pos     (18U)\n#define CAN_FM1R_FBM18_Msk     (0x1UL << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */\n#define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */\n#define CAN_FM1R_FBM19_Pos     (19U)\n#define CAN_FM1R_FBM19_Msk     (0x1UL << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */\n#define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */\n#define CAN_FM1R_FBM20_Pos     (20U)\n#define CAN_FM1R_FBM20_Msk     (0x1UL << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */\n#define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */\n#define CAN_FM1R_FBM21_Pos     (21U)\n#define CAN_FM1R_FBM21_Msk     (0x1UL << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */\n#define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */\n#define CAN_FM1R_FBM22_Pos     (22U)\n#define CAN_FM1R_FBM22_Msk     (0x1UL << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */\n#define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */\n#define CAN_FM1R_FBM23_Pos     (23U)\n#define CAN_FM1R_FBM23_Msk     (0x1UL << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */\n#define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */\n#define CAN_FM1R_FBM24_Pos     (24U)\n#define CAN_FM1R_FBM24_Msk     (0x1UL << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */\n#define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */\n#define CAN_FM1R_FBM25_Pos     (25U)\n#define CAN_FM1R_FBM25_Msk     (0x1UL << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */\n#define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */\n#define CAN_FM1R_FBM26_Pos     (26U)\n#define CAN_FM1R_FBM26_Msk     (0x1UL << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */\n#define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */\n#define CAN_FM1R_FBM27_Pos     (27U)\n#define CAN_FM1R_FBM27_Msk     (0x1UL << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */\n#define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */\n\n/*******************  Bit definition for CAN_FS1R register  *******************/\n#define CAN_FS1R_FSC_Pos       (0U)\n#define CAN_FS1R_FSC_Msk       (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */\n#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */\n#define CAN_FS1R_FSC0_Pos      (0U)\n#define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */\n#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */\n#define CAN_FS1R_FSC1_Pos      (1U)\n#define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */\n#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */\n#define CAN_FS1R_FSC2_Pos      (2U)\n#define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */\n#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */\n#define CAN_FS1R_FSC3_Pos      (3U)\n#define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */\n#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */\n#define CAN_FS1R_FSC4_Pos      (4U)\n#define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */\n#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */\n#define CAN_FS1R_FSC5_Pos      (5U)\n#define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */\n#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */\n#define CAN_FS1R_FSC6_Pos      (6U)\n#define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */\n#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */\n#define CAN_FS1R_FSC7_Pos      (7U)\n#define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */\n#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */\n#define CAN_FS1R_FSC8_Pos      (8U)\n#define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */\n#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */\n#define CAN_FS1R_FSC9_Pos      (9U)\n#define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */\n#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */\n#define CAN_FS1R_FSC10_Pos     (10U)\n#define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */\n#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */\n#define CAN_FS1R_FSC11_Pos     (11U)\n#define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */\n#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */\n#define CAN_FS1R_FSC12_Pos     (12U)\n#define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */\n#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */\n#define CAN_FS1R_FSC13_Pos     (13U)\n#define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */\n#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */\n#define CAN_FS1R_FSC14_Pos     (14U)\n#define CAN_FS1R_FSC14_Msk     (0x1UL << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */\n#define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */\n#define CAN_FS1R_FSC15_Pos     (15U)\n#define CAN_FS1R_FSC15_Msk     (0x1UL << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */\n#define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */\n#define CAN_FS1R_FSC16_Pos     (16U)\n#define CAN_FS1R_FSC16_Msk     (0x1UL << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */\n#define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */\n#define CAN_FS1R_FSC17_Pos     (17U)\n#define CAN_FS1R_FSC17_Msk     (0x1UL << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */\n#define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */\n#define CAN_FS1R_FSC18_Pos     (18U)\n#define CAN_FS1R_FSC18_Msk     (0x1UL << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */\n#define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */\n#define CAN_FS1R_FSC19_Pos     (19U)\n#define CAN_FS1R_FSC19_Msk     (0x1UL << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */\n#define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */\n#define CAN_FS1R_FSC20_Pos     (20U)\n#define CAN_FS1R_FSC20_Msk     (0x1UL << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */\n#define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */\n#define CAN_FS1R_FSC21_Pos     (21U)\n#define CAN_FS1R_FSC21_Msk     (0x1UL << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */\n#define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */\n#define CAN_FS1R_FSC22_Pos     (22U)\n#define CAN_FS1R_FSC22_Msk     (0x1UL << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */\n#define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */\n#define CAN_FS1R_FSC23_Pos     (23U)\n#define CAN_FS1R_FSC23_Msk     (0x1UL << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */\n#define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */\n#define CAN_FS1R_FSC24_Pos     (24U)\n#define CAN_FS1R_FSC24_Msk     (0x1UL << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */\n#define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */\n#define CAN_FS1R_FSC25_Pos     (25U)\n#define CAN_FS1R_FSC25_Msk     (0x1UL << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */\n#define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */\n#define CAN_FS1R_FSC26_Pos     (26U)\n#define CAN_FS1R_FSC26_Msk     (0x1UL << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */\n#define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */\n#define CAN_FS1R_FSC27_Pos     (27U)\n#define CAN_FS1R_FSC27_Msk     (0x1UL << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */\n#define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */\n\n/******************  Bit definition for CAN_FFA1R register  *******************/\n#define CAN_FFA1R_FFA_Pos      (0U)\n#define CAN_FFA1R_FFA_Msk      (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */\n#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */\n#define CAN_FFA1R_FFA0_Pos     (0U)\n#define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */\n#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */\n#define CAN_FFA1R_FFA1_Pos     (1U)\n#define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */\n#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */\n#define CAN_FFA1R_FFA2_Pos     (2U)\n#define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */\n#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */\n#define CAN_FFA1R_FFA3_Pos     (3U)\n#define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */\n#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */\n#define CAN_FFA1R_FFA4_Pos     (4U)\n#define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */\n#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */\n#define CAN_FFA1R_FFA5_Pos     (5U)\n#define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */\n#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */\n#define CAN_FFA1R_FFA6_Pos     (6U)\n#define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */\n#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */\n#define CAN_FFA1R_FFA7_Pos     (7U)\n#define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */\n#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */\n#define CAN_FFA1R_FFA8_Pos     (8U)\n#define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */\n#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */\n#define CAN_FFA1R_FFA9_Pos     (9U)\n#define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */\n#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */\n#define CAN_FFA1R_FFA10_Pos    (10U)\n#define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */\n#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */\n#define CAN_FFA1R_FFA11_Pos    (11U)\n#define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */\n#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */\n#define CAN_FFA1R_FFA12_Pos    (12U)\n#define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */\n#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */\n#define CAN_FFA1R_FFA13_Pos    (13U)\n#define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */\n#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */\n#define CAN_FFA1R_FFA14_Pos    (14U)\n#define CAN_FFA1R_FFA14_Msk    (0x1UL << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */\n#define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */\n#define CAN_FFA1R_FFA15_Pos    (15U)\n#define CAN_FFA1R_FFA15_Msk    (0x1UL << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */\n#define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */\n#define CAN_FFA1R_FFA16_Pos    (16U)\n#define CAN_FFA1R_FFA16_Msk    (0x1UL << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */\n#define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */\n#define CAN_FFA1R_FFA17_Pos    (17U)\n#define CAN_FFA1R_FFA17_Msk    (0x1UL << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */\n#define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */\n#define CAN_FFA1R_FFA18_Pos    (18U)\n#define CAN_FFA1R_FFA18_Msk    (0x1UL << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */\n#define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */\n#define CAN_FFA1R_FFA19_Pos    (19U)\n#define CAN_FFA1R_FFA19_Msk    (0x1UL << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */\n#define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */\n#define CAN_FFA1R_FFA20_Pos    (20U)\n#define CAN_FFA1R_FFA20_Msk    (0x1UL << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */\n#define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */\n#define CAN_FFA1R_FFA21_Pos    (21U)\n#define CAN_FFA1R_FFA21_Msk    (0x1UL << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */\n#define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */\n#define CAN_FFA1R_FFA22_Pos    (22U)\n#define CAN_FFA1R_FFA22_Msk    (0x1UL << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */\n#define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */\n#define CAN_FFA1R_FFA23_Pos    (23U)\n#define CAN_FFA1R_FFA23_Msk    (0x1UL << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */\n#define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */\n#define CAN_FFA1R_FFA24_Pos    (24U)\n#define CAN_FFA1R_FFA24_Msk    (0x1UL << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */\n#define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */\n#define CAN_FFA1R_FFA25_Pos    (25U)\n#define CAN_FFA1R_FFA25_Msk    (0x1UL << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */\n#define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */\n#define CAN_FFA1R_FFA26_Pos    (26U)\n#define CAN_FFA1R_FFA26_Msk    (0x1UL << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */\n#define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */\n#define CAN_FFA1R_FFA27_Pos    (27U)\n#define CAN_FFA1R_FFA27_Msk    (0x1UL << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */\n#define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */\n\n/*******************  Bit definition for CAN_FA1R register  *******************/\n#define CAN_FA1R_FACT_Pos      (0U)\n#define CAN_FA1R_FACT_Msk      (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */\n#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */\n#define CAN_FA1R_FACT0_Pos     (0U)\n#define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */\n#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */\n#define CAN_FA1R_FACT1_Pos     (1U)\n#define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */\n#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */\n#define CAN_FA1R_FACT2_Pos     (2U)\n#define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */\n#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */\n#define CAN_FA1R_FACT3_Pos     (3U)\n#define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */\n#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */\n#define CAN_FA1R_FACT4_Pos     (4U)\n#define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */\n#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */\n#define CAN_FA1R_FACT5_Pos     (5U)\n#define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */\n#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */\n#define CAN_FA1R_FACT6_Pos     (6U)\n#define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */\n#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */\n#define CAN_FA1R_FACT7_Pos     (7U)\n#define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */\n#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */\n#define CAN_FA1R_FACT8_Pos     (8U)\n#define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */\n#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */\n#define CAN_FA1R_FACT9_Pos     (9U)\n#define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */\n#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */\n#define CAN_FA1R_FACT10_Pos    (10U)\n#define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */\n#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */\n#define CAN_FA1R_FACT11_Pos    (11U)\n#define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */\n#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */\n#define CAN_FA1R_FACT12_Pos    (12U)\n#define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */\n#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */\n#define CAN_FA1R_FACT13_Pos    (13U)\n#define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */\n#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */\n#define CAN_FA1R_FACT14_Pos    (14U)\n#define CAN_FA1R_FACT14_Msk    (0x1UL << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */\n#define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */\n#define CAN_FA1R_FACT15_Pos    (15U)\n#define CAN_FA1R_FACT15_Msk    (0x1UL << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */\n#define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */\n#define CAN_FA1R_FACT16_Pos    (16U)\n#define CAN_FA1R_FACT16_Msk    (0x1UL << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */\n#define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */\n#define CAN_FA1R_FACT17_Pos    (17U)\n#define CAN_FA1R_FACT17_Msk    (0x1UL << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */\n#define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */\n#define CAN_FA1R_FACT18_Pos    (18U)\n#define CAN_FA1R_FACT18_Msk    (0x1UL << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */\n#define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */\n#define CAN_FA1R_FACT19_Pos    (19U)\n#define CAN_FA1R_FACT19_Msk    (0x1UL << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */\n#define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */\n#define CAN_FA1R_FACT20_Pos    (20U)\n#define CAN_FA1R_FACT20_Msk    (0x1UL << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */\n#define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */\n#define CAN_FA1R_FACT21_Pos    (21U)\n#define CAN_FA1R_FACT21_Msk    (0x1UL << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */\n#define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */\n#define CAN_FA1R_FACT22_Pos    (22U)\n#define CAN_FA1R_FACT22_Msk    (0x1UL << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */\n#define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */\n#define CAN_FA1R_FACT23_Pos    (23U)\n#define CAN_FA1R_FACT23_Msk    (0x1UL << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */\n#define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */\n#define CAN_FA1R_FACT24_Pos    (24U)\n#define CAN_FA1R_FACT24_Msk    (0x1UL << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */\n#define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */\n#define CAN_FA1R_FACT25_Pos    (25U)\n#define CAN_FA1R_FACT25_Msk    (0x1UL << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */\n#define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */\n#define CAN_FA1R_FACT26_Pos    (26U)\n#define CAN_FA1R_FACT26_Msk    (0x1UL << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */\n#define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */\n#define CAN_FA1R_FACT27_Pos    (27U)\n#define CAN_FA1R_FACT27_Msk    (0x1UL << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */\n#define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */\n\n\n/*******************  Bit definition for CAN_F0R1 register  *******************/\n#define CAN_F0R1_FB0_Pos       (0U)\n#define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R1_FB1_Pos       (1U)\n#define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R1_FB2_Pos       (2U)\n#define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R1_FB3_Pos       (3U)\n#define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R1_FB4_Pos       (4U)\n#define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R1_FB5_Pos       (5U)\n#define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R1_FB6_Pos       (6U)\n#define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R1_FB7_Pos       (7U)\n#define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R1_FB8_Pos       (8U)\n#define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R1_FB9_Pos       (9U)\n#define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R1_FB10_Pos      (10U)\n#define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R1_FB11_Pos      (11U)\n#define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R1_FB12_Pos      (12U)\n#define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R1_FB13_Pos      (13U)\n#define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R1_FB14_Pos      (14U)\n#define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R1_FB15_Pos      (15U)\n#define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R1_FB16_Pos      (16U)\n#define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R1_FB17_Pos      (17U)\n#define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R1_FB18_Pos      (18U)\n#define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R1_FB19_Pos      (19U)\n#define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R1_FB20_Pos      (20U)\n#define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R1_FB21_Pos      (21U)\n#define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R1_FB22_Pos      (22U)\n#define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R1_FB23_Pos      (23U)\n#define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R1_FB24_Pos      (24U)\n#define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R1_FB25_Pos      (25U)\n#define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R1_FB26_Pos      (26U)\n#define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R1_FB27_Pos      (27U)\n#define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R1_FB28_Pos      (28U)\n#define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R1_FB29_Pos      (29U)\n#define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R1_FB30_Pos      (30U)\n#define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R1_FB31_Pos      (31U)\n#define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R1 register  *******************/\n#define CAN_F1R1_FB0_Pos       (0U)\n#define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R1_FB1_Pos       (1U)\n#define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R1_FB2_Pos       (2U)\n#define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R1_FB3_Pos       (3U)\n#define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R1_FB4_Pos       (4U)\n#define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R1_FB5_Pos       (5U)\n#define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R1_FB6_Pos       (6U)\n#define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R1_FB7_Pos       (7U)\n#define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R1_FB8_Pos       (8U)\n#define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R1_FB9_Pos       (9U)\n#define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R1_FB10_Pos      (10U)\n#define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R1_FB11_Pos      (11U)\n#define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R1_FB12_Pos      (12U)\n#define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R1_FB13_Pos      (13U)\n#define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R1_FB14_Pos      (14U)\n#define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R1_FB15_Pos      (15U)\n#define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R1_FB16_Pos      (16U)\n#define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R1_FB17_Pos      (17U)\n#define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R1_FB18_Pos      (18U)\n#define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R1_FB19_Pos      (19U)\n#define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R1_FB20_Pos      (20U)\n#define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R1_FB21_Pos      (21U)\n#define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R1_FB22_Pos      (22U)\n#define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R1_FB23_Pos      (23U)\n#define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R1_FB24_Pos      (24U)\n#define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R1_FB25_Pos      (25U)\n#define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R1_FB26_Pos      (26U)\n#define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R1_FB27_Pos      (27U)\n#define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R1_FB28_Pos      (28U)\n#define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R1_FB29_Pos      (29U)\n#define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R1_FB30_Pos      (30U)\n#define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R1_FB31_Pos      (31U)\n#define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R1 register  *******************/\n#define CAN_F2R1_FB0_Pos       (0U)\n#define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R1_FB1_Pos       (1U)\n#define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R1_FB2_Pos       (2U)\n#define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R1_FB3_Pos       (3U)\n#define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R1_FB4_Pos       (4U)\n#define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R1_FB5_Pos       (5U)\n#define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R1_FB6_Pos       (6U)\n#define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R1_FB7_Pos       (7U)\n#define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R1_FB8_Pos       (8U)\n#define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R1_FB9_Pos       (9U)\n#define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R1_FB10_Pos      (10U)\n#define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R1_FB11_Pos      (11U)\n#define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R1_FB12_Pos      (12U)\n#define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R1_FB13_Pos      (13U)\n#define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R1_FB14_Pos      (14U)\n#define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R1_FB15_Pos      (15U)\n#define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R1_FB16_Pos      (16U)\n#define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R1_FB17_Pos      (17U)\n#define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R1_FB18_Pos      (18U)\n#define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R1_FB19_Pos      (19U)\n#define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R1_FB20_Pos      (20U)\n#define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R1_FB21_Pos      (21U)\n#define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R1_FB22_Pos      (22U)\n#define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R1_FB23_Pos      (23U)\n#define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R1_FB24_Pos      (24U)\n#define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R1_FB25_Pos      (25U)\n#define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R1_FB26_Pos      (26U)\n#define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R1_FB27_Pos      (27U)\n#define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R1_FB28_Pos      (28U)\n#define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R1_FB29_Pos      (29U)\n#define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R1_FB30_Pos      (30U)\n#define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R1_FB31_Pos      (31U)\n#define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R1 register  *******************/\n#define CAN_F3R1_FB0_Pos       (0U)\n#define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R1_FB1_Pos       (1U)\n#define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R1_FB2_Pos       (2U)\n#define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R1_FB3_Pos       (3U)\n#define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R1_FB4_Pos       (4U)\n#define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R1_FB5_Pos       (5U)\n#define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R1_FB6_Pos       (6U)\n#define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R1_FB7_Pos       (7U)\n#define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R1_FB8_Pos       (8U)\n#define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R1_FB9_Pos       (9U)\n#define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R1_FB10_Pos      (10U)\n#define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R1_FB11_Pos      (11U)\n#define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R1_FB12_Pos      (12U)\n#define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R1_FB13_Pos      (13U)\n#define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R1_FB14_Pos      (14U)\n#define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R1_FB15_Pos      (15U)\n#define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R1_FB16_Pos      (16U)\n#define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R1_FB17_Pos      (17U)\n#define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R1_FB18_Pos      (18U)\n#define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R1_FB19_Pos      (19U)\n#define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R1_FB20_Pos      (20U)\n#define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R1_FB21_Pos      (21U)\n#define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R1_FB22_Pos      (22U)\n#define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R1_FB23_Pos      (23U)\n#define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R1_FB24_Pos      (24U)\n#define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R1_FB25_Pos      (25U)\n#define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R1_FB26_Pos      (26U)\n#define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R1_FB27_Pos      (27U)\n#define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R1_FB28_Pos      (28U)\n#define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R1_FB29_Pos      (29U)\n#define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R1_FB30_Pos      (30U)\n#define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R1_FB31_Pos      (31U)\n#define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R1 register  *******************/\n#define CAN_F4R1_FB0_Pos       (0U)\n#define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R1_FB1_Pos       (1U)\n#define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R1_FB2_Pos       (2U)\n#define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R1_FB3_Pos       (3U)\n#define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R1_FB4_Pos       (4U)\n#define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R1_FB5_Pos       (5U)\n#define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R1_FB6_Pos       (6U)\n#define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R1_FB7_Pos       (7U)\n#define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R1_FB8_Pos       (8U)\n#define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R1_FB9_Pos       (9U)\n#define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R1_FB10_Pos      (10U)\n#define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R1_FB11_Pos      (11U)\n#define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R1_FB12_Pos      (12U)\n#define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R1_FB13_Pos      (13U)\n#define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R1_FB14_Pos      (14U)\n#define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R1_FB15_Pos      (15U)\n#define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R1_FB16_Pos      (16U)\n#define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R1_FB17_Pos      (17U)\n#define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R1_FB18_Pos      (18U)\n#define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R1_FB19_Pos      (19U)\n#define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R1_FB20_Pos      (20U)\n#define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R1_FB21_Pos      (21U)\n#define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R1_FB22_Pos      (22U)\n#define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R1_FB23_Pos      (23U)\n#define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R1_FB24_Pos      (24U)\n#define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R1_FB25_Pos      (25U)\n#define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R1_FB26_Pos      (26U)\n#define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R1_FB27_Pos      (27U)\n#define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R1_FB28_Pos      (28U)\n#define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R1_FB29_Pos      (29U)\n#define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R1_FB30_Pos      (30U)\n#define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R1_FB31_Pos      (31U)\n#define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R1 register  *******************/\n#define CAN_F5R1_FB0_Pos       (0U)\n#define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R1_FB1_Pos       (1U)\n#define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R1_FB2_Pos       (2U)\n#define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R1_FB3_Pos       (3U)\n#define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R1_FB4_Pos       (4U)\n#define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R1_FB5_Pos       (5U)\n#define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R1_FB6_Pos       (6U)\n#define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R1_FB7_Pos       (7U)\n#define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R1_FB8_Pos       (8U)\n#define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R1_FB9_Pos       (9U)\n#define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R1_FB10_Pos      (10U)\n#define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R1_FB11_Pos      (11U)\n#define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R1_FB12_Pos      (12U)\n#define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R1_FB13_Pos      (13U)\n#define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R1_FB14_Pos      (14U)\n#define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R1_FB15_Pos      (15U)\n#define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R1_FB16_Pos      (16U)\n#define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R1_FB17_Pos      (17U)\n#define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R1_FB18_Pos      (18U)\n#define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R1_FB19_Pos      (19U)\n#define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R1_FB20_Pos      (20U)\n#define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R1_FB21_Pos      (21U)\n#define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R1_FB22_Pos      (22U)\n#define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R1_FB23_Pos      (23U)\n#define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R1_FB24_Pos      (24U)\n#define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R1_FB25_Pos      (25U)\n#define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R1_FB26_Pos      (26U)\n#define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R1_FB27_Pos      (27U)\n#define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R1_FB28_Pos      (28U)\n#define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R1_FB29_Pos      (29U)\n#define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R1_FB30_Pos      (30U)\n#define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R1_FB31_Pos      (31U)\n#define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R1 register  *******************/\n#define CAN_F6R1_FB0_Pos       (0U)\n#define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R1_FB1_Pos       (1U)\n#define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R1_FB2_Pos       (2U)\n#define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R1_FB3_Pos       (3U)\n#define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R1_FB4_Pos       (4U)\n#define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R1_FB5_Pos       (5U)\n#define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R1_FB6_Pos       (6U)\n#define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R1_FB7_Pos       (7U)\n#define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R1_FB8_Pos       (8U)\n#define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R1_FB9_Pos       (9U)\n#define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R1_FB10_Pos      (10U)\n#define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R1_FB11_Pos      (11U)\n#define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R1_FB12_Pos      (12U)\n#define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R1_FB13_Pos      (13U)\n#define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R1_FB14_Pos      (14U)\n#define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R1_FB15_Pos      (15U)\n#define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R1_FB16_Pos      (16U)\n#define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R1_FB17_Pos      (17U)\n#define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R1_FB18_Pos      (18U)\n#define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R1_FB19_Pos      (19U)\n#define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R1_FB20_Pos      (20U)\n#define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R1_FB21_Pos      (21U)\n#define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R1_FB22_Pos      (22U)\n#define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R1_FB23_Pos      (23U)\n#define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R1_FB24_Pos      (24U)\n#define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R1_FB25_Pos      (25U)\n#define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R1_FB26_Pos      (26U)\n#define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R1_FB27_Pos      (27U)\n#define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R1_FB28_Pos      (28U)\n#define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R1_FB29_Pos      (29U)\n#define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R1_FB30_Pos      (30U)\n#define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R1_FB31_Pos      (31U)\n#define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R1 register  *******************/\n#define CAN_F7R1_FB0_Pos       (0U)\n#define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R1_FB1_Pos       (1U)\n#define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R1_FB2_Pos       (2U)\n#define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R1_FB3_Pos       (3U)\n#define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R1_FB4_Pos       (4U)\n#define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R1_FB5_Pos       (5U)\n#define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R1_FB6_Pos       (6U)\n#define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R1_FB7_Pos       (7U)\n#define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R1_FB8_Pos       (8U)\n#define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R1_FB9_Pos       (9U)\n#define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R1_FB10_Pos      (10U)\n#define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R1_FB11_Pos      (11U)\n#define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R1_FB12_Pos      (12U)\n#define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R1_FB13_Pos      (13U)\n#define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R1_FB14_Pos      (14U)\n#define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R1_FB15_Pos      (15U)\n#define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R1_FB16_Pos      (16U)\n#define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R1_FB17_Pos      (17U)\n#define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R1_FB18_Pos      (18U)\n#define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R1_FB19_Pos      (19U)\n#define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R1_FB20_Pos      (20U)\n#define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R1_FB21_Pos      (21U)\n#define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R1_FB22_Pos      (22U)\n#define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R1_FB23_Pos      (23U)\n#define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R1_FB24_Pos      (24U)\n#define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R1_FB25_Pos      (25U)\n#define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R1_FB26_Pos      (26U)\n#define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R1_FB27_Pos      (27U)\n#define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R1_FB28_Pos      (28U)\n#define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R1_FB29_Pos      (29U)\n#define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R1_FB30_Pos      (30U)\n#define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R1_FB31_Pos      (31U)\n#define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R1 register  *******************/\n#define CAN_F8R1_FB0_Pos       (0U)\n#define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R1_FB1_Pos       (1U)\n#define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R1_FB2_Pos       (2U)\n#define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R1_FB3_Pos       (3U)\n#define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R1_FB4_Pos       (4U)\n#define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R1_FB5_Pos       (5U)\n#define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R1_FB6_Pos       (6U)\n#define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R1_FB7_Pos       (7U)\n#define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R1_FB8_Pos       (8U)\n#define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R1_FB9_Pos       (9U)\n#define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R1_FB10_Pos      (10U)\n#define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R1_FB11_Pos      (11U)\n#define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R1_FB12_Pos      (12U)\n#define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R1_FB13_Pos      (13U)\n#define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R1_FB14_Pos      (14U)\n#define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R1_FB15_Pos      (15U)\n#define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R1_FB16_Pos      (16U)\n#define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R1_FB17_Pos      (17U)\n#define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R1_FB18_Pos      (18U)\n#define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R1_FB19_Pos      (19U)\n#define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R1_FB20_Pos      (20U)\n#define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R1_FB21_Pos      (21U)\n#define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R1_FB22_Pos      (22U)\n#define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R1_FB23_Pos      (23U)\n#define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R1_FB24_Pos      (24U)\n#define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R1_FB25_Pos      (25U)\n#define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R1_FB26_Pos      (26U)\n#define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R1_FB27_Pos      (27U)\n#define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R1_FB28_Pos      (28U)\n#define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R1_FB29_Pos      (29U)\n#define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R1_FB30_Pos      (30U)\n#define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R1_FB31_Pos      (31U)\n#define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R1 register  *******************/\n#define CAN_F9R1_FB0_Pos       (0U)\n#define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R1_FB1_Pos       (1U)\n#define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R1_FB2_Pos       (2U)\n#define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R1_FB3_Pos       (3U)\n#define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R1_FB4_Pos       (4U)\n#define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R1_FB5_Pos       (5U)\n#define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R1_FB6_Pos       (6U)\n#define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R1_FB7_Pos       (7U)\n#define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R1_FB8_Pos       (8U)\n#define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R1_FB9_Pos       (9U)\n#define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R1_FB10_Pos      (10U)\n#define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R1_FB11_Pos      (11U)\n#define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R1_FB12_Pos      (12U)\n#define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R1_FB13_Pos      (13U)\n#define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R1_FB14_Pos      (14U)\n#define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R1_FB15_Pos      (15U)\n#define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R1_FB16_Pos      (16U)\n#define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R1_FB17_Pos      (17U)\n#define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R1_FB18_Pos      (18U)\n#define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R1_FB19_Pos      (19U)\n#define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R1_FB20_Pos      (20U)\n#define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R1_FB21_Pos      (21U)\n#define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R1_FB22_Pos      (22U)\n#define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R1_FB23_Pos      (23U)\n#define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R1_FB24_Pos      (24U)\n#define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R1_FB25_Pos      (25U)\n#define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R1_FB26_Pos      (26U)\n#define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R1_FB27_Pos      (27U)\n#define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R1_FB28_Pos      (28U)\n#define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R1_FB29_Pos      (29U)\n#define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R1_FB30_Pos      (30U)\n#define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R1_FB31_Pos      (31U)\n#define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R1 register  ******************/\n#define CAN_F10R1_FB0_Pos      (0U)\n#define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R1_FB1_Pos      (1U)\n#define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R1_FB2_Pos      (2U)\n#define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R1_FB3_Pos      (3U)\n#define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R1_FB4_Pos      (4U)\n#define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R1_FB5_Pos      (5U)\n#define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R1_FB6_Pos      (6U)\n#define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R1_FB7_Pos      (7U)\n#define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R1_FB8_Pos      (8U)\n#define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R1_FB9_Pos      (9U)\n#define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R1_FB10_Pos     (10U)\n#define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R1_FB11_Pos     (11U)\n#define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R1_FB12_Pos     (12U)\n#define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R1_FB13_Pos     (13U)\n#define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R1_FB14_Pos     (14U)\n#define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R1_FB15_Pos     (15U)\n#define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R1_FB16_Pos     (16U)\n#define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R1_FB17_Pos     (17U)\n#define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R1_FB18_Pos     (18U)\n#define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R1_FB19_Pos     (19U)\n#define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R1_FB20_Pos     (20U)\n#define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R1_FB21_Pos     (21U)\n#define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R1_FB22_Pos     (22U)\n#define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R1_FB23_Pos     (23U)\n#define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R1_FB24_Pos     (24U)\n#define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R1_FB25_Pos     (25U)\n#define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R1_FB26_Pos     (26U)\n#define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R1_FB27_Pos     (27U)\n#define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R1_FB28_Pos     (28U)\n#define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R1_FB29_Pos     (29U)\n#define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R1_FB30_Pos     (30U)\n#define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R1_FB31_Pos     (31U)\n#define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R1 register  ******************/\n#define CAN_F11R1_FB0_Pos      (0U)\n#define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R1_FB1_Pos      (1U)\n#define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R1_FB2_Pos      (2U)\n#define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R1_FB3_Pos      (3U)\n#define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R1_FB4_Pos      (4U)\n#define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R1_FB5_Pos      (5U)\n#define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R1_FB6_Pos      (6U)\n#define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R1_FB7_Pos      (7U)\n#define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R1_FB8_Pos      (8U)\n#define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R1_FB9_Pos      (9U)\n#define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R1_FB10_Pos     (10U)\n#define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R1_FB11_Pos     (11U)\n#define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R1_FB12_Pos     (12U)\n#define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R1_FB13_Pos     (13U)\n#define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R1_FB14_Pos     (14U)\n#define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R1_FB15_Pos     (15U)\n#define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R1_FB16_Pos     (16U)\n#define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R1_FB17_Pos     (17U)\n#define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R1_FB18_Pos     (18U)\n#define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R1_FB19_Pos     (19U)\n#define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R1_FB20_Pos     (20U)\n#define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R1_FB21_Pos     (21U)\n#define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R1_FB22_Pos     (22U)\n#define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R1_FB23_Pos     (23U)\n#define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R1_FB24_Pos     (24U)\n#define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R1_FB25_Pos     (25U)\n#define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R1_FB26_Pos     (26U)\n#define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R1_FB27_Pos     (27U)\n#define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R1_FB28_Pos     (28U)\n#define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R1_FB29_Pos     (29U)\n#define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R1_FB30_Pos     (30U)\n#define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R1_FB31_Pos     (31U)\n#define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R1 register  ******************/\n#define CAN_F12R1_FB0_Pos      (0U)\n#define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R1_FB1_Pos      (1U)\n#define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R1_FB2_Pos      (2U)\n#define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R1_FB3_Pos      (3U)\n#define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R1_FB4_Pos      (4U)\n#define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R1_FB5_Pos      (5U)\n#define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R1_FB6_Pos      (6U)\n#define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R1_FB7_Pos      (7U)\n#define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R1_FB8_Pos      (8U)\n#define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R1_FB9_Pos      (9U)\n#define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R1_FB10_Pos     (10U)\n#define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R1_FB11_Pos     (11U)\n#define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R1_FB12_Pos     (12U)\n#define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R1_FB13_Pos     (13U)\n#define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R1_FB14_Pos     (14U)\n#define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R1_FB15_Pos     (15U)\n#define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R1_FB16_Pos     (16U)\n#define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R1_FB17_Pos     (17U)\n#define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R1_FB18_Pos     (18U)\n#define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R1_FB19_Pos     (19U)\n#define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R1_FB20_Pos     (20U)\n#define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R1_FB21_Pos     (21U)\n#define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R1_FB22_Pos     (22U)\n#define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R1_FB23_Pos     (23U)\n#define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R1_FB24_Pos     (24U)\n#define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R1_FB25_Pos     (25U)\n#define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R1_FB26_Pos     (26U)\n#define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R1_FB27_Pos     (27U)\n#define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R1_FB28_Pos     (28U)\n#define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R1_FB29_Pos     (29U)\n#define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R1_FB30_Pos     (30U)\n#define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R1_FB31_Pos     (31U)\n#define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R1 register  ******************/\n#define CAN_F13R1_FB0_Pos      (0U)\n#define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R1_FB1_Pos      (1U)\n#define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R1_FB2_Pos      (2U)\n#define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R1_FB3_Pos      (3U)\n#define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R1_FB4_Pos      (4U)\n#define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R1_FB5_Pos      (5U)\n#define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R1_FB6_Pos      (6U)\n#define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R1_FB7_Pos      (7U)\n#define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R1_FB8_Pos      (8U)\n#define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R1_FB9_Pos      (9U)\n#define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R1_FB10_Pos     (10U)\n#define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R1_FB11_Pos     (11U)\n#define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R1_FB12_Pos     (12U)\n#define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R1_FB13_Pos     (13U)\n#define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R1_FB14_Pos     (14U)\n#define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R1_FB15_Pos     (15U)\n#define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R1_FB16_Pos     (16U)\n#define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R1_FB17_Pos     (17U)\n#define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R1_FB18_Pos     (18U)\n#define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R1_FB19_Pos     (19U)\n#define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R1_FB20_Pos     (20U)\n#define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R1_FB21_Pos     (21U)\n#define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R1_FB22_Pos     (22U)\n#define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R1_FB23_Pos     (23U)\n#define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R1_FB24_Pos     (24U)\n#define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R1_FB25_Pos     (25U)\n#define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R1_FB26_Pos     (26U)\n#define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R1_FB27_Pos     (27U)\n#define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R1_FB28_Pos     (28U)\n#define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R1_FB29_Pos     (29U)\n#define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R1_FB30_Pos     (30U)\n#define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R1_FB31_Pos     (31U)\n#define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F0R2 register  *******************/\n#define CAN_F0R2_FB0_Pos       (0U)\n#define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R2_FB1_Pos       (1U)\n#define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R2_FB2_Pos       (2U)\n#define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R2_FB3_Pos       (3U)\n#define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R2_FB4_Pos       (4U)\n#define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R2_FB5_Pos       (5U)\n#define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R2_FB6_Pos       (6U)\n#define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R2_FB7_Pos       (7U)\n#define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R2_FB8_Pos       (8U)\n#define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R2_FB9_Pos       (9U)\n#define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R2_FB10_Pos      (10U)\n#define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R2_FB11_Pos      (11U)\n#define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R2_FB12_Pos      (12U)\n#define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R2_FB13_Pos      (13U)\n#define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R2_FB14_Pos      (14U)\n#define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R2_FB15_Pos      (15U)\n#define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R2_FB16_Pos      (16U)\n#define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R2_FB17_Pos      (17U)\n#define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R2_FB18_Pos      (18U)\n#define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R2_FB19_Pos      (19U)\n#define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R2_FB20_Pos      (20U)\n#define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R2_FB21_Pos      (21U)\n#define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R2_FB22_Pos      (22U)\n#define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R2_FB23_Pos      (23U)\n#define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R2_FB24_Pos      (24U)\n#define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R2_FB25_Pos      (25U)\n#define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R2_FB26_Pos      (26U)\n#define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R2_FB27_Pos      (27U)\n#define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R2_FB28_Pos      (28U)\n#define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R2_FB29_Pos      (29U)\n#define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R2_FB30_Pos      (30U)\n#define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R2_FB31_Pos      (31U)\n#define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R2 register  *******************/\n#define CAN_F1R2_FB0_Pos       (0U)\n#define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R2_FB1_Pos       (1U)\n#define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R2_FB2_Pos       (2U)\n#define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R2_FB3_Pos       (3U)\n#define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R2_FB4_Pos       (4U)\n#define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R2_FB5_Pos       (5U)\n#define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R2_FB6_Pos       (6U)\n#define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R2_FB7_Pos       (7U)\n#define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R2_FB8_Pos       (8U)\n#define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R2_FB9_Pos       (9U)\n#define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R2_FB10_Pos      (10U)\n#define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R2_FB11_Pos      (11U)\n#define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R2_FB12_Pos      (12U)\n#define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R2_FB13_Pos      (13U)\n#define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R2_FB14_Pos      (14U)\n#define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R2_FB15_Pos      (15U)\n#define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R2_FB16_Pos      (16U)\n#define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R2_FB17_Pos      (17U)\n#define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R2_FB18_Pos      (18U)\n#define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R2_FB19_Pos      (19U)\n#define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R2_FB20_Pos      (20U)\n#define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R2_FB21_Pos      (21U)\n#define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R2_FB22_Pos      (22U)\n#define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R2_FB23_Pos      (23U)\n#define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R2_FB24_Pos      (24U)\n#define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R2_FB25_Pos      (25U)\n#define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R2_FB26_Pos      (26U)\n#define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R2_FB27_Pos      (27U)\n#define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R2_FB28_Pos      (28U)\n#define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R2_FB29_Pos      (29U)\n#define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R2_FB30_Pos      (30U)\n#define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R2_FB31_Pos      (31U)\n#define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R2 register  *******************/\n#define CAN_F2R2_FB0_Pos       (0U)\n#define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R2_FB1_Pos       (1U)\n#define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R2_FB2_Pos       (2U)\n#define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R2_FB3_Pos       (3U)\n#define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R2_FB4_Pos       (4U)\n#define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R2_FB5_Pos       (5U)\n#define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R2_FB6_Pos       (6U)\n#define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R2_FB7_Pos       (7U)\n#define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R2_FB8_Pos       (8U)\n#define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R2_FB9_Pos       (9U)\n#define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R2_FB10_Pos      (10U)\n#define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R2_FB11_Pos      (11U)\n#define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R2_FB12_Pos      (12U)\n#define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R2_FB13_Pos      (13U)\n#define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R2_FB14_Pos      (14U)\n#define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R2_FB15_Pos      (15U)\n#define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R2_FB16_Pos      (16U)\n#define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R2_FB17_Pos      (17U)\n#define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R2_FB18_Pos      (18U)\n#define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R2_FB19_Pos      (19U)\n#define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R2_FB20_Pos      (20U)\n#define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R2_FB21_Pos      (21U)\n#define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R2_FB22_Pos      (22U)\n#define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R2_FB23_Pos      (23U)\n#define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R2_FB24_Pos      (24U)\n#define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R2_FB25_Pos      (25U)\n#define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R2_FB26_Pos      (26U)\n#define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R2_FB27_Pos      (27U)\n#define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R2_FB28_Pos      (28U)\n#define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R2_FB29_Pos      (29U)\n#define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R2_FB30_Pos      (30U)\n#define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R2_FB31_Pos      (31U)\n#define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R2 register  *******************/\n#define CAN_F3R2_FB0_Pos       (0U)\n#define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R2_FB1_Pos       (1U)\n#define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R2_FB2_Pos       (2U)\n#define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R2_FB3_Pos       (3U)\n#define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R2_FB4_Pos       (4U)\n#define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R2_FB5_Pos       (5U)\n#define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R2_FB6_Pos       (6U)\n#define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R2_FB7_Pos       (7U)\n#define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R2_FB8_Pos       (8U)\n#define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R2_FB9_Pos       (9U)\n#define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R2_FB10_Pos      (10U)\n#define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R2_FB11_Pos      (11U)\n#define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R2_FB12_Pos      (12U)\n#define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R2_FB13_Pos      (13U)\n#define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R2_FB14_Pos      (14U)\n#define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R2_FB15_Pos      (15U)\n#define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R2_FB16_Pos      (16U)\n#define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R2_FB17_Pos      (17U)\n#define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R2_FB18_Pos      (18U)\n#define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R2_FB19_Pos      (19U)\n#define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R2_FB20_Pos      (20U)\n#define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R2_FB21_Pos      (21U)\n#define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R2_FB22_Pos      (22U)\n#define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R2_FB23_Pos      (23U)\n#define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R2_FB24_Pos      (24U)\n#define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R2_FB25_Pos      (25U)\n#define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R2_FB26_Pos      (26U)\n#define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R2_FB27_Pos      (27U)\n#define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R2_FB28_Pos      (28U)\n#define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R2_FB29_Pos      (29U)\n#define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R2_FB30_Pos      (30U)\n#define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R2_FB31_Pos      (31U)\n#define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R2 register  *******************/\n#define CAN_F4R2_FB0_Pos       (0U)\n#define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R2_FB1_Pos       (1U)\n#define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R2_FB2_Pos       (2U)\n#define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R2_FB3_Pos       (3U)\n#define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R2_FB4_Pos       (4U)\n#define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R2_FB5_Pos       (5U)\n#define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R2_FB6_Pos       (6U)\n#define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R2_FB7_Pos       (7U)\n#define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R2_FB8_Pos       (8U)\n#define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R2_FB9_Pos       (9U)\n#define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R2_FB10_Pos      (10U)\n#define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R2_FB11_Pos      (11U)\n#define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R2_FB12_Pos      (12U)\n#define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R2_FB13_Pos      (13U)\n#define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R2_FB14_Pos      (14U)\n#define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R2_FB15_Pos      (15U)\n#define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R2_FB16_Pos      (16U)\n#define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R2_FB17_Pos      (17U)\n#define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R2_FB18_Pos      (18U)\n#define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R2_FB19_Pos      (19U)\n#define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R2_FB20_Pos      (20U)\n#define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R2_FB21_Pos      (21U)\n#define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R2_FB22_Pos      (22U)\n#define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R2_FB23_Pos      (23U)\n#define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R2_FB24_Pos      (24U)\n#define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R2_FB25_Pos      (25U)\n#define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R2_FB26_Pos      (26U)\n#define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R2_FB27_Pos      (27U)\n#define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R2_FB28_Pos      (28U)\n#define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R2_FB29_Pos      (29U)\n#define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R2_FB30_Pos      (30U)\n#define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R2_FB31_Pos      (31U)\n#define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R2 register  *******************/\n#define CAN_F5R2_FB0_Pos       (0U)\n#define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R2_FB1_Pos       (1U)\n#define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R2_FB2_Pos       (2U)\n#define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R2_FB3_Pos       (3U)\n#define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R2_FB4_Pos       (4U)\n#define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R2_FB5_Pos       (5U)\n#define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R2_FB6_Pos       (6U)\n#define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R2_FB7_Pos       (7U)\n#define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R2_FB8_Pos       (8U)\n#define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R2_FB9_Pos       (9U)\n#define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R2_FB10_Pos      (10U)\n#define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R2_FB11_Pos      (11U)\n#define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R2_FB12_Pos      (12U)\n#define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R2_FB13_Pos      (13U)\n#define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R2_FB14_Pos      (14U)\n#define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R2_FB15_Pos      (15U)\n#define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R2_FB16_Pos      (16U)\n#define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R2_FB17_Pos      (17U)\n#define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R2_FB18_Pos      (18U)\n#define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R2_FB19_Pos      (19U)\n#define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R2_FB20_Pos      (20U)\n#define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R2_FB21_Pos      (21U)\n#define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R2_FB22_Pos      (22U)\n#define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R2_FB23_Pos      (23U)\n#define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R2_FB24_Pos      (24U)\n#define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R2_FB25_Pos      (25U)\n#define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R2_FB26_Pos      (26U)\n#define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R2_FB27_Pos      (27U)\n#define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R2_FB28_Pos      (28U)\n#define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R2_FB29_Pos      (29U)\n#define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R2_FB30_Pos      (30U)\n#define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R2_FB31_Pos      (31U)\n#define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R2 register  *******************/\n#define CAN_F6R2_FB0_Pos       (0U)\n#define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R2_FB1_Pos       (1U)\n#define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R2_FB2_Pos       (2U)\n#define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R2_FB3_Pos       (3U)\n#define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R2_FB4_Pos       (4U)\n#define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R2_FB5_Pos       (5U)\n#define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R2_FB6_Pos       (6U)\n#define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R2_FB7_Pos       (7U)\n#define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R2_FB8_Pos       (8U)\n#define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R2_FB9_Pos       (9U)\n#define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R2_FB10_Pos      (10U)\n#define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R2_FB11_Pos      (11U)\n#define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R2_FB12_Pos      (12U)\n#define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R2_FB13_Pos      (13U)\n#define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R2_FB14_Pos      (14U)\n#define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R2_FB15_Pos      (15U)\n#define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R2_FB16_Pos      (16U)\n#define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R2_FB17_Pos      (17U)\n#define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R2_FB18_Pos      (18U)\n#define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R2_FB19_Pos      (19U)\n#define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R2_FB20_Pos      (20U)\n#define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R2_FB21_Pos      (21U)\n#define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R2_FB22_Pos      (22U)\n#define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R2_FB23_Pos      (23U)\n#define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R2_FB24_Pos      (24U)\n#define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R2_FB25_Pos      (25U)\n#define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R2_FB26_Pos      (26U)\n#define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R2_FB27_Pos      (27U)\n#define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R2_FB28_Pos      (28U)\n#define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R2_FB29_Pos      (29U)\n#define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R2_FB30_Pos      (30U)\n#define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R2_FB31_Pos      (31U)\n#define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R2 register  *******************/\n#define CAN_F7R2_FB0_Pos       (0U)\n#define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R2_FB1_Pos       (1U)\n#define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R2_FB2_Pos       (2U)\n#define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R2_FB3_Pos       (3U)\n#define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R2_FB4_Pos       (4U)\n#define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R2_FB5_Pos       (5U)\n#define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R2_FB6_Pos       (6U)\n#define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R2_FB7_Pos       (7U)\n#define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R2_FB8_Pos       (8U)\n#define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R2_FB9_Pos       (9U)\n#define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R2_FB10_Pos      (10U)\n#define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R2_FB11_Pos      (11U)\n#define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R2_FB12_Pos      (12U)\n#define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R2_FB13_Pos      (13U)\n#define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R2_FB14_Pos      (14U)\n#define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R2_FB15_Pos      (15U)\n#define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R2_FB16_Pos      (16U)\n#define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R2_FB17_Pos      (17U)\n#define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R2_FB18_Pos      (18U)\n#define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R2_FB19_Pos      (19U)\n#define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R2_FB20_Pos      (20U)\n#define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R2_FB21_Pos      (21U)\n#define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R2_FB22_Pos      (22U)\n#define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R2_FB23_Pos      (23U)\n#define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R2_FB24_Pos      (24U)\n#define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R2_FB25_Pos      (25U)\n#define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R2_FB26_Pos      (26U)\n#define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R2_FB27_Pos      (27U)\n#define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R2_FB28_Pos      (28U)\n#define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R2_FB29_Pos      (29U)\n#define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R2_FB30_Pos      (30U)\n#define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R2_FB31_Pos      (31U)\n#define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R2 register  *******************/\n#define CAN_F8R2_FB0_Pos       (0U)\n#define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R2_FB1_Pos       (1U)\n#define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R2_FB2_Pos       (2U)\n#define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R2_FB3_Pos       (3U)\n#define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R2_FB4_Pos       (4U)\n#define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R2_FB5_Pos       (5U)\n#define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R2_FB6_Pos       (6U)\n#define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R2_FB7_Pos       (7U)\n#define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R2_FB8_Pos       (8U)\n#define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R2_FB9_Pos       (9U)\n#define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R2_FB10_Pos      (10U)\n#define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R2_FB11_Pos      (11U)\n#define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R2_FB12_Pos      (12U)\n#define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R2_FB13_Pos      (13U)\n#define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R2_FB14_Pos      (14U)\n#define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R2_FB15_Pos      (15U)\n#define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R2_FB16_Pos      (16U)\n#define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R2_FB17_Pos      (17U)\n#define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R2_FB18_Pos      (18U)\n#define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R2_FB19_Pos      (19U)\n#define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R2_FB20_Pos      (20U)\n#define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R2_FB21_Pos      (21U)\n#define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R2_FB22_Pos      (22U)\n#define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R2_FB23_Pos      (23U)\n#define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R2_FB24_Pos      (24U)\n#define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R2_FB25_Pos      (25U)\n#define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R2_FB26_Pos      (26U)\n#define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R2_FB27_Pos      (27U)\n#define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R2_FB28_Pos      (28U)\n#define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R2_FB29_Pos      (29U)\n#define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R2_FB30_Pos      (30U)\n#define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R2_FB31_Pos      (31U)\n#define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R2 register  *******************/\n#define CAN_F9R2_FB0_Pos       (0U)\n#define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R2_FB1_Pos       (1U)\n#define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R2_FB2_Pos       (2U)\n#define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R2_FB3_Pos       (3U)\n#define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R2_FB4_Pos       (4U)\n#define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R2_FB5_Pos       (5U)\n#define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R2_FB6_Pos       (6U)\n#define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R2_FB7_Pos       (7U)\n#define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R2_FB8_Pos       (8U)\n#define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R2_FB9_Pos       (9U)\n#define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R2_FB10_Pos      (10U)\n#define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R2_FB11_Pos      (11U)\n#define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R2_FB12_Pos      (12U)\n#define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R2_FB13_Pos      (13U)\n#define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R2_FB14_Pos      (14U)\n#define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R2_FB15_Pos      (15U)\n#define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R2_FB16_Pos      (16U)\n#define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R2_FB17_Pos      (17U)\n#define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R2_FB18_Pos      (18U)\n#define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R2_FB19_Pos      (19U)\n#define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R2_FB20_Pos      (20U)\n#define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R2_FB21_Pos      (21U)\n#define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R2_FB22_Pos      (22U)\n#define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R2_FB23_Pos      (23U)\n#define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R2_FB24_Pos      (24U)\n#define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R2_FB25_Pos      (25U)\n#define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R2_FB26_Pos      (26U)\n#define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R2_FB27_Pos      (27U)\n#define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R2_FB28_Pos      (28U)\n#define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R2_FB29_Pos      (29U)\n#define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R2_FB30_Pos      (30U)\n#define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R2_FB31_Pos      (31U)\n#define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R2 register  ******************/\n#define CAN_F10R2_FB0_Pos      (0U)\n#define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R2_FB1_Pos      (1U)\n#define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R2_FB2_Pos      (2U)\n#define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R2_FB3_Pos      (3U)\n#define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R2_FB4_Pos      (4U)\n#define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R2_FB5_Pos      (5U)\n#define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R2_FB6_Pos      (6U)\n#define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R2_FB7_Pos      (7U)\n#define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R2_FB8_Pos      (8U)\n#define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R2_FB9_Pos      (9U)\n#define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R2_FB10_Pos     (10U)\n#define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R2_FB11_Pos     (11U)\n#define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R2_FB12_Pos     (12U)\n#define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R2_FB13_Pos     (13U)\n#define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R2_FB14_Pos     (14U)\n#define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R2_FB15_Pos     (15U)\n#define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R2_FB16_Pos     (16U)\n#define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R2_FB17_Pos     (17U)\n#define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R2_FB18_Pos     (18U)\n#define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R2_FB19_Pos     (19U)\n#define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R2_FB20_Pos     (20U)\n#define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R2_FB21_Pos     (21U)\n#define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R2_FB22_Pos     (22U)\n#define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R2_FB23_Pos     (23U)\n#define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R2_FB24_Pos     (24U)\n#define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R2_FB25_Pos     (25U)\n#define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R2_FB26_Pos     (26U)\n#define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R2_FB27_Pos     (27U)\n#define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R2_FB28_Pos     (28U)\n#define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R2_FB29_Pos     (29U)\n#define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R2_FB30_Pos     (30U)\n#define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R2_FB31_Pos     (31U)\n#define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R2 register  ******************/\n#define CAN_F11R2_FB0_Pos      (0U)\n#define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R2_FB1_Pos      (1U)\n#define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R2_FB2_Pos      (2U)\n#define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R2_FB3_Pos      (3U)\n#define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R2_FB4_Pos      (4U)\n#define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R2_FB5_Pos      (5U)\n#define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R2_FB6_Pos      (6U)\n#define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R2_FB7_Pos      (7U)\n#define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R2_FB8_Pos      (8U)\n#define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R2_FB9_Pos      (9U)\n#define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R2_FB10_Pos     (10U)\n#define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R2_FB11_Pos     (11U)\n#define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R2_FB12_Pos     (12U)\n#define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R2_FB13_Pos     (13U)\n#define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R2_FB14_Pos     (14U)\n#define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R2_FB15_Pos     (15U)\n#define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R2_FB16_Pos     (16U)\n#define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R2_FB17_Pos     (17U)\n#define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R2_FB18_Pos     (18U)\n#define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R2_FB19_Pos     (19U)\n#define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R2_FB20_Pos     (20U)\n#define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R2_FB21_Pos     (21U)\n#define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R2_FB22_Pos     (22U)\n#define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R2_FB23_Pos     (23U)\n#define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R2_FB24_Pos     (24U)\n#define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R2_FB25_Pos     (25U)\n#define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R2_FB26_Pos     (26U)\n#define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R2_FB27_Pos     (27U)\n#define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R2_FB28_Pos     (28U)\n#define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R2_FB29_Pos     (29U)\n#define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R2_FB30_Pos     (30U)\n#define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R2_FB31_Pos     (31U)\n#define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R2 register  ******************/\n#define CAN_F12R2_FB0_Pos      (0U)\n#define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R2_FB1_Pos      (1U)\n#define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R2_FB2_Pos      (2U)\n#define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R2_FB3_Pos      (3U)\n#define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R2_FB4_Pos      (4U)\n#define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R2_FB5_Pos      (5U)\n#define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R2_FB6_Pos      (6U)\n#define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R2_FB7_Pos      (7U)\n#define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R2_FB8_Pos      (8U)\n#define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R2_FB9_Pos      (9U)\n#define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R2_FB10_Pos     (10U)\n#define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R2_FB11_Pos     (11U)\n#define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R2_FB12_Pos     (12U)\n#define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R2_FB13_Pos     (13U)\n#define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R2_FB14_Pos     (14U)\n#define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R2_FB15_Pos     (15U)\n#define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R2_FB16_Pos     (16U)\n#define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R2_FB17_Pos     (17U)\n#define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R2_FB18_Pos     (18U)\n#define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R2_FB19_Pos     (19U)\n#define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R2_FB20_Pos     (20U)\n#define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R2_FB21_Pos     (21U)\n#define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R2_FB22_Pos     (22U)\n#define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R2_FB23_Pos     (23U)\n#define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R2_FB24_Pos     (24U)\n#define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R2_FB25_Pos     (25U)\n#define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R2_FB26_Pos     (26U)\n#define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R2_FB27_Pos     (27U)\n#define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R2_FB28_Pos     (28U)\n#define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R2_FB29_Pos     (29U)\n#define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R2_FB30_Pos     (30U)\n#define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R2_FB31_Pos     (31U)\n#define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R2 register  ******************/\n#define CAN_F13R2_FB0_Pos      (0U)\n#define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R2_FB1_Pos      (1U)\n#define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R2_FB2_Pos      (2U)\n#define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R2_FB3_Pos      (3U)\n#define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R2_FB4_Pos      (4U)\n#define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R2_FB5_Pos      (5U)\n#define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R2_FB6_Pos      (6U)\n#define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R2_FB7_Pos      (7U)\n#define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R2_FB8_Pos      (8U)\n#define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R2_FB9_Pos      (9U)\n#define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R2_FB10_Pos     (10U)\n#define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R2_FB11_Pos     (11U)\n#define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R2_FB12_Pos     (12U)\n#define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R2_FB13_Pos     (13U)\n#define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R2_FB14_Pos     (14U)\n#define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R2_FB15_Pos     (15U)\n#define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R2_FB16_Pos     (16U)\n#define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R2_FB17_Pos     (17U)\n#define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R2_FB18_Pos     (18U)\n#define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R2_FB19_Pos     (19U)\n#define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R2_FB20_Pos     (20U)\n#define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R2_FB21_Pos     (21U)\n#define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R2_FB22_Pos     (22U)\n#define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R2_FB23_Pos     (23U)\n#define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R2_FB24_Pos     (24U)\n#define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R2_FB25_Pos     (25U)\n#define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R2_FB26_Pos     (26U)\n#define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R2_FB27_Pos     (27U)\n#define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R2_FB28_Pos     (28U)\n#define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R2_FB29_Pos     (29U)\n#define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R2_FB30_Pos     (30U)\n#define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R2_FB31_Pos     (31U)\n#define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          CRC calculation unit                              */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for CRC_DR register  *********************/\n#define CRC_DR_DR_Pos       (0U)\n#define CRC_DR_DR_Msk       (0xFFFFFFFFUL << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */\n#define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */\n\n\n/*******************  Bit definition for CRC_IDR register  ********************/\n#define CRC_IDR_IDR_Pos     (0U)\n#define CRC_IDR_IDR_Msk     (0xFFUL << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */\n#define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */\n\n\n/********************  Bit definition for CRC_CR register  ********************/\n#define CRC_CR_RESET_Pos    (0U)\n#define CRC_CR_RESET_Msk    (0x1UL << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */\n#define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */\n\n/******************************************************************************/\n/*                                                                            */\n/*                 Digital Filter for Sigma Delta Modulators                  */\n/*                                                                            */\n/******************************************************************************/\n\n/****************   DFSDM channel configuration registers  ********************/\n\n/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/\n#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)\n#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)    /*!< 0x80000000 */\n#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */\n#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)\n#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)   /*!< 0x40000000 */\n#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */\n#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)\n#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos)  /*!< 0x00FF0000 */\n#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */\n#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)\n#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x0000C000 */\n#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */\n#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */\n#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */\n#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)\n#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00003000 */\n#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */\n#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */\n#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */\n#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)\n#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)    /*!< 0x00000100 */\n#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */\n#define DFSDM_CHCFGR1_CHEN_Pos          (7U)\n#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)       /*!< 0x00000080 */\n#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */\n#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)\n#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)     /*!< 0x00000040 */\n#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */\n#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)\n#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)      /*!< 0x00000020 */\n#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */\n#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)\n#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x0000000C */\n#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */\n#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */\n#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */\n#define DFSDM_CHCFGR1_SITP_Pos          (0U)\n#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000003 */\n#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */\n#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */\n#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */\n\n/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/\n#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)\n#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */\n#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)\n#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)     /*!< 0x000000F8 */\n#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */\n\n/****************  Bit definition for DFSDM_CHAWSCDR register *****************/\n#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)\n#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00C00000 */\n#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */\n#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */\n#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */\n#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)\n#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)   /*!< 0x001F0000 */\n#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */\n#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)\n#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)     /*!< 0x0000F000 */\n#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */\n#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)\n#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)     /*!< 0x000000FF */\n#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */\n\n/****************  Bit definition for DFSDM_CHWDATR register *******************/\n#define DFSDM_CHWDATR_WDATA_Pos         (0U)\n#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)   /*!< 0x0000FFFF */\n#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */\n\n/****************  Bit definition for DFSDM_CHDATINR register *****************/\n#define DFSDM_CHDATINR_INDAT0_Pos       (0U)\n#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */\n#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */\n#define DFSDM_CHDATINR_INDAT1_Pos       (16U)\n#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */\n#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */\n\n/************************   DFSDM module registers  ****************************/\n\n/*****************  Bit definition for DFSDM_FLTCR1 register *******************/\n#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)\n#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)      /*!< 0x40000000 */\n#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */\n#define DFSDM_FLTCR1_FAST_Pos           (29U)\n#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)        /*!< 0x20000000 */\n#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */\n#define DFSDM_FLTCR1_RCH_Pos            (24U)\n#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)         /*!< 0x07000000 */\n#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */\n#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)\n#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)      /*!< 0x00200000 */\n#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */\n#define DFSDM_FLTCR1_RSYNC_Pos          (19U)\n#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)       /*!< 0x00080000 */\n#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */\n#define DFSDM_FLTCR1_RCONT_Pos          (18U)\n#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)       /*!< 0x00040000 */\n#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */\n#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)\n#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)    /*!< 0x00020000 */\n#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */\n#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)\n#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00006000 */\n#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */\n#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */\n#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */\n#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)\n#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x7UL << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000700 */\n#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */\n#define DFSDM_FLTCR1_JEXTSEL_2          (0x4UL << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000400 */\n#define DFSDM_FLTCR1_JEXTSEL_1          (0x2UL << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000200 */\n#define DFSDM_FLTCR1_JEXTSEL_0          (0x1UL << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000100 */\n#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)\n#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)      /*!< 0x00000020 */\n#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */\n#define DFSDM_FLTCR1_JSCAN_Pos          (4U)\n#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)       /*!< 0x00000010 */\n#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */\n#define DFSDM_FLTCR1_JSYNC_Pos          (3U)\n#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)       /*!< 0x00000008 */\n#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */\n#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)\n#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)    /*!< 0x00000002 */\n#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */\n#define DFSDM_FLTCR1_DFEN_Pos           (0U)\n#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)        /*!< 0x00000001 */\n#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */\n\n/*****************  Bit definition for DFSDM_FLTCR2 register *******************/\n#define DFSDM_FLTCR2_AWDCH_Pos          (16U)\n#define DFSDM_FLTCR2_AWDCH_Msk          (0xFUL << DFSDM_FLTCR2_AWDCH_Pos)       /*!< 0x000F0000 */\n#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */\n#define DFSDM_FLTCR2_EXCH_Pos           (8U)\n#define DFSDM_FLTCR2_EXCH_Msk           (0xFUL << DFSDM_FLTCR2_EXCH_Pos)        /*!< 0x00000F00 */\n#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */\n#define DFSDM_FLTCR2_CKABIE_Pos         (6U)\n#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)      /*!< 0x00000040 */\n#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */\n#define DFSDM_FLTCR2_SCDIE_Pos          (5U)\n#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)       /*!< 0x00000020 */\n#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */\n#define DFSDM_FLTCR2_AWDIE_Pos          (4U)\n#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)       /*!< 0x00000010 */\n#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */\n#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)\n#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)      /*!< 0x00000008 */\n#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */\n#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)\n#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)      /*!< 0x00000004 */\n#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */\n#define DFSDM_FLTCR2_REOCIE_Pos         (1U)\n#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)      /*!< 0x00000002 */\n#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */\n#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)\n#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)      /*!< 0x00000001 */\n#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */\n\n/*****************  Bit definition for DFSDM_FLTISR register *******************/\n#define DFSDM_FLTISR_SCDF_Pos           (24U)\n#define DFSDM_FLTISR_SCDF_Msk           (0xFUL << DFSDM_FLTISR_SCDF_Pos)        /*!< 0x0F000000 */\n#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */\n#define DFSDM_FLTISR_CKABF_Pos          (16U)\n#define DFSDM_FLTISR_CKABF_Msk          (0xFUL << DFSDM_FLTISR_CKABF_Pos)       /*!< 0x000F0000 */\n#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */\n#define DFSDM_FLTISR_RCIP_Pos           (14U)\n#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)        /*!< 0x00004000 */\n#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */\n#define DFSDM_FLTISR_JCIP_Pos           (13U)\n#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)        /*!< 0x00002000 */\n#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */\n#define DFSDM_FLTISR_AWDF_Pos           (4U)\n#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)        /*!< 0x00000010 */\n#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */\n#define DFSDM_FLTISR_ROVRF_Pos          (3U)\n#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)       /*!< 0x00000008 */\n#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */\n#define DFSDM_FLTISR_JOVRF_Pos          (2U)\n#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)       /*!< 0x00000004 */\n#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */\n#define DFSDM_FLTISR_REOCF_Pos          (1U)\n#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)       /*!< 0x00000002 */\n#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */\n#define DFSDM_FLTISR_JEOCF_Pos          (0U)\n#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)       /*!< 0x00000001 */\n#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */\n\n/*****************  Bit definition for DFSDM_FLTICR register *******************/\n#define DFSDM_FLTICR_CLRSCDF_Pos       (24U)\n#define DFSDM_FLTICR_CLRSCDF_Msk       (0xFUL << DFSDM_FLTICR_CLRSCDF_Pos)      /*!< 0x0F000000 */\n#define DFSDM_FLTICR_CLRSCDF           DFSDM_FLTICR_CLRSCDF_Msk                /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */\n#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)\n#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFUL << DFSDM_FLTICR_CLRCKABF_Pos)    /*!< 0x000F0000 */\n#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */\n#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)\n#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)    /*!< 0x00000008 */\n#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */\n#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)\n#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)    /*!< 0x00000004 */\n#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */\n\n/****************  Bit definition for DFSDM_FLTJCHGR register ******************/\n#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)\n#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFUL << DFSDM_FLTJCHGR_JCHG_Pos)      /*!< 0x0000000F */\n#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */\n/*****************  Bit definition for DFSDM_FLTFCR register *******************/\n#define DFSDM_FLTFCR_FORD_Pos           (29U)\n#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0xE0000000 */\n#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */\n#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */\n#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */\n#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */\n#define DFSDM_FLTFCR_FOSR_Pos           (16U)\n#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)      /*!< 0x03FF0000 */\n#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */\n#define DFSDM_FLTFCR_IOSR_Pos           (0U)\n#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)       /*!< 0x000000FF */\n#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */\n\n/***************  Bit definition for DFSDM_FLTJDATAR register *****************/\n#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)\n#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */\n#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)\n#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos)  /*!< 0x00000007 */\n#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */\n\n/***************  Bit definition for DFSDM_FLTRDATAR register *****************/\n#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)\n#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */\n#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)\n#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)    /*!< 0x00000010 */\n#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */\n#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)\n#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos)  /*!< 0x00000007 */\n#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */\n\n/***************  Bit definition for DFSDM_FLTAWHTR register ******************/\n#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)\n#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */\n#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)\n#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)     /*!< 0x0000000F */\n#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */\n\n/***************  Bit definition for DFSDM_FLTAWLTR register ******************/\n#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)\n#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWLT[23:0] Analog watchdog low threshold */\n#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)\n#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)     /*!< 0x0000000F */\n#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */\n\n/***************  Bit definition for DFSDM_FLTAWSR register *******************/\n#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)\n#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFUL << DFSDM_FLTAWSR_AWHTF_Pos)      /*!< 0x00000F00 */\n#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */\n#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)\n#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFUL << DFSDM_FLTAWSR_AWLTF_Pos)      /*!< 0x0000000F */\n#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */\n\n/***************  Bit definition for DFSDM_FLTAWCFR register ******************/\n#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)\n#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos)  /*!< 0x00000F00 */\n#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */\n#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)\n#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos)  /*!< 0x0000000F */\n#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */\n\n/***************  Bit definition for DFSDM_FLTEXMAX register ******************/\n#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)\n#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */\n#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)\n#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)   /*!< 0x00000007 */\n#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */\n\n/***************  Bit definition for DFSDM_FLTEXMIN register ******************/\n#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)\n#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */\n#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)\n#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)   /*!< 0x00000007 */\n#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */\n\n/***************  Bit definition for DFSDM_FLTCNVTIMR register ****************/\n#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)\n#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */\n#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */\n\n/* Legacy Defines */\n#define DFSDM_FLTICR_CLRSCSDF_Pos        DFSDM_FLTICR_CLRSCDF_Pos\n#define DFSDM_FLTICR_CLRSCSDF_Msk        DFSDM_FLTICR_CLRSCDF_Msk\n#define DFSDM_FLTICR_CLRSCSDF            DFSDM_FLTICR_CLRSCDF\n\n/******************************************************************************/\n/*                                                                            */\n/*                             DMA Controller                                 */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DMA_SxCR register  *****************/\n#define DMA_SxCR_CHSEL_Pos       (25U)\n#define DMA_SxCR_CHSEL_Msk       (0x7UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */\n#define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk\n#define DMA_SxCR_CHSEL_0         0x02000000U\n#define DMA_SxCR_CHSEL_1         0x04000000U\n#define DMA_SxCR_CHSEL_2         0x08000000U\n#define DMA_SxCR_MBURST_Pos      (23U)\n#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */\n#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk\n#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */\n#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */\n#define DMA_SxCR_PBURST_Pos      (21U)\n#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */\n#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk\n#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */\n#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */\n#define DMA_SxCR_CT_Pos          (19U)\n#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */\n#define DMA_SxCR_CT              DMA_SxCR_CT_Msk\n#define DMA_SxCR_DBM_Pos         (18U)\n#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */\n#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk\n#define DMA_SxCR_PL_Pos          (16U)\n#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */\n#define DMA_SxCR_PL              DMA_SxCR_PL_Msk\n#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */\n#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */\n#define DMA_SxCR_PINCOS_Pos      (15U)\n#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */\n#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk\n#define DMA_SxCR_MSIZE_Pos       (13U)\n#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */\n#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk\n#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */\n#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */\n#define DMA_SxCR_PSIZE_Pos       (11U)\n#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */\n#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk\n#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */\n#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */\n#define DMA_SxCR_MINC_Pos        (10U)\n#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */\n#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk\n#define DMA_SxCR_PINC_Pos        (9U)\n#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */\n#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk\n#define DMA_SxCR_CIRC_Pos        (8U)\n#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */\n#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk\n#define DMA_SxCR_DIR_Pos         (6U)\n#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */\n#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk\n#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */\n#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */\n#define DMA_SxCR_PFCTRL_Pos      (5U)\n#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */\n#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk\n#define DMA_SxCR_TCIE_Pos        (4U)\n#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */\n#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk\n#define DMA_SxCR_HTIE_Pos        (3U)\n#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */\n#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk\n#define DMA_SxCR_TEIE_Pos        (2U)\n#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */\n#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk\n#define DMA_SxCR_DMEIE_Pos       (1U)\n#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */\n#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk\n#define DMA_SxCR_EN_Pos          (0U)\n#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */\n#define DMA_SxCR_EN              DMA_SxCR_EN_Msk\n\n/* Legacy defines */\n#define DMA_SxCR_ACK_Pos         (20U)\n#define DMA_SxCR_ACK_Msk         (0x1UL << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */\n#define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk\n\n/********************  Bits definition for DMA_SxCNDTR register  **************/\n#define DMA_SxNDT_Pos            (0U)\n#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */\n#define DMA_SxNDT                DMA_SxNDT_Msk\n#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */\n#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */\n#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */\n#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */\n#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */\n#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */\n#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */\n#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */\n#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */\n#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */\n#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */\n#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */\n#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */\n#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */\n#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */\n#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */\n\n/********************  Bits definition for DMA_SxFCR register  ****************/\n#define DMA_SxFCR_FEIE_Pos       (7U)\n#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */\n#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk\n#define DMA_SxFCR_FS_Pos         (3U)\n#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */\n#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk\n#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */\n#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */\n#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */\n#define DMA_SxFCR_DMDIS_Pos      (2U)\n#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */\n#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk\n#define DMA_SxFCR_FTH_Pos        (0U)\n#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */\n#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk\n#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */\n#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */\n\n/********************  Bits definition for DMA_LISR register  *****************/\n#define DMA_LISR_TCIF3_Pos       (27U)\n#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */\n#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk\n#define DMA_LISR_HTIF3_Pos       (26U)\n#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */\n#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk\n#define DMA_LISR_TEIF3_Pos       (25U)\n#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */\n#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk\n#define DMA_LISR_DMEIF3_Pos      (24U)\n#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */\n#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk\n#define DMA_LISR_FEIF3_Pos       (22U)\n#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */\n#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk\n#define DMA_LISR_TCIF2_Pos       (21U)\n#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */\n#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk\n#define DMA_LISR_HTIF2_Pos       (20U)\n#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */\n#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk\n#define DMA_LISR_TEIF2_Pos       (19U)\n#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */\n#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk\n#define DMA_LISR_DMEIF2_Pos      (18U)\n#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */\n#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk\n#define DMA_LISR_FEIF2_Pos       (16U)\n#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */\n#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk\n#define DMA_LISR_TCIF1_Pos       (11U)\n#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */\n#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk\n#define DMA_LISR_HTIF1_Pos       (10U)\n#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */\n#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk\n#define DMA_LISR_TEIF1_Pos       (9U)\n#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */\n#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk\n#define DMA_LISR_DMEIF1_Pos      (8U)\n#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */\n#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk\n#define DMA_LISR_FEIF1_Pos       (6U)\n#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */\n#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk\n#define DMA_LISR_TCIF0_Pos       (5U)\n#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */\n#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk\n#define DMA_LISR_HTIF0_Pos       (4U)\n#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */\n#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk\n#define DMA_LISR_TEIF0_Pos       (3U)\n#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */\n#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk\n#define DMA_LISR_DMEIF0_Pos      (2U)\n#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */\n#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk\n#define DMA_LISR_FEIF0_Pos       (0U)\n#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */\n#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk\n\n/********************  Bits definition for DMA_HISR register  *****************/\n#define DMA_HISR_TCIF7_Pos       (27U)\n#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */\n#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk\n#define DMA_HISR_HTIF7_Pos       (26U)\n#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */\n#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk\n#define DMA_HISR_TEIF7_Pos       (25U)\n#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */\n#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk\n#define DMA_HISR_DMEIF7_Pos      (24U)\n#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */\n#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk\n#define DMA_HISR_FEIF7_Pos       (22U)\n#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */\n#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk\n#define DMA_HISR_TCIF6_Pos       (21U)\n#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */\n#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk\n#define DMA_HISR_HTIF6_Pos       (20U)\n#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */\n#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk\n#define DMA_HISR_TEIF6_Pos       (19U)\n#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */\n#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk\n#define DMA_HISR_DMEIF6_Pos      (18U)\n#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */\n#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk\n#define DMA_HISR_FEIF6_Pos       (16U)\n#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */\n#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk\n#define DMA_HISR_TCIF5_Pos       (11U)\n#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */\n#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk\n#define DMA_HISR_HTIF5_Pos       (10U)\n#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */\n#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk\n#define DMA_HISR_TEIF5_Pos       (9U)\n#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */\n#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk\n#define DMA_HISR_DMEIF5_Pos      (8U)\n#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */\n#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk\n#define DMA_HISR_FEIF5_Pos       (6U)\n#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */\n#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk\n#define DMA_HISR_TCIF4_Pos       (5U)\n#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */\n#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk\n#define DMA_HISR_HTIF4_Pos       (4U)\n#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */\n#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk\n#define DMA_HISR_TEIF4_Pos       (3U)\n#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */\n#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk\n#define DMA_HISR_DMEIF4_Pos      (2U)\n#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */\n#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk\n#define DMA_HISR_FEIF4_Pos       (0U)\n#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */\n#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk\n\n/********************  Bits definition for DMA_LIFCR register  ****************/\n#define DMA_LIFCR_CTCIF3_Pos     (27U)\n#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */\n#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk\n#define DMA_LIFCR_CHTIF3_Pos     (26U)\n#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */\n#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk\n#define DMA_LIFCR_CTEIF3_Pos     (25U)\n#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */\n#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk\n#define DMA_LIFCR_CDMEIF3_Pos    (24U)\n#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */\n#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk\n#define DMA_LIFCR_CFEIF3_Pos     (22U)\n#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */\n#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk\n#define DMA_LIFCR_CTCIF2_Pos     (21U)\n#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */\n#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk\n#define DMA_LIFCR_CHTIF2_Pos     (20U)\n#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */\n#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk\n#define DMA_LIFCR_CTEIF2_Pos     (19U)\n#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */\n#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk\n#define DMA_LIFCR_CDMEIF2_Pos    (18U)\n#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */\n#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk\n#define DMA_LIFCR_CFEIF2_Pos     (16U)\n#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */\n#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk\n#define DMA_LIFCR_CTCIF1_Pos     (11U)\n#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */\n#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk\n#define DMA_LIFCR_CHTIF1_Pos     (10U)\n#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */\n#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk\n#define DMA_LIFCR_CTEIF1_Pos     (9U)\n#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */\n#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk\n#define DMA_LIFCR_CDMEIF1_Pos    (8U)\n#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */\n#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk\n#define DMA_LIFCR_CFEIF1_Pos     (6U)\n#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */\n#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk\n#define DMA_LIFCR_CTCIF0_Pos     (5U)\n#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */\n#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk\n#define DMA_LIFCR_CHTIF0_Pos     (4U)\n#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */\n#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk\n#define DMA_LIFCR_CTEIF0_Pos     (3U)\n#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */\n#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk\n#define DMA_LIFCR_CDMEIF0_Pos    (2U)\n#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */\n#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk\n#define DMA_LIFCR_CFEIF0_Pos     (0U)\n#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */\n#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk\n\n/********************  Bits definition for DMA_HIFCR  register  ****************/\n#define DMA_HIFCR_CTCIF7_Pos     (27U)\n#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */\n#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk\n#define DMA_HIFCR_CHTIF7_Pos     (26U)\n#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */\n#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk\n#define DMA_HIFCR_CTEIF7_Pos     (25U)\n#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */\n#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk\n#define DMA_HIFCR_CDMEIF7_Pos    (24U)\n#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */\n#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk\n#define DMA_HIFCR_CFEIF7_Pos     (22U)\n#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */\n#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk\n#define DMA_HIFCR_CTCIF6_Pos     (21U)\n#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */\n#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk\n#define DMA_HIFCR_CHTIF6_Pos     (20U)\n#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */\n#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk\n#define DMA_HIFCR_CTEIF6_Pos     (19U)\n#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */\n#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk\n#define DMA_HIFCR_CDMEIF6_Pos    (18U)\n#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */\n#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk\n#define DMA_HIFCR_CFEIF6_Pos     (16U)\n#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */\n#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk\n#define DMA_HIFCR_CTCIF5_Pos     (11U)\n#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */\n#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk\n#define DMA_HIFCR_CHTIF5_Pos     (10U)\n#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */\n#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk\n#define DMA_HIFCR_CTEIF5_Pos     (9U)\n#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */\n#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk\n#define DMA_HIFCR_CDMEIF5_Pos    (8U)\n#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */\n#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk\n#define DMA_HIFCR_CFEIF5_Pos     (6U)\n#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */\n#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk\n#define DMA_HIFCR_CTCIF4_Pos     (5U)\n#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */\n#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk\n#define DMA_HIFCR_CHTIF4_Pos     (4U)\n#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */\n#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk\n#define DMA_HIFCR_CTEIF4_Pos     (3U)\n#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */\n#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk\n#define DMA_HIFCR_CDMEIF4_Pos    (2U)\n#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */\n#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk\n#define DMA_HIFCR_CFEIF4_Pos     (0U)\n#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */\n#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk\n\n/******************  Bit definition for DMA_SxPAR register  ********************/\n#define DMA_SxPAR_PA_Pos         (0U)\n#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */\n#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */\n\n/******************  Bit definition for DMA_SxM0AR register  ********************/\n#define DMA_SxM0AR_M0A_Pos       (0U)\n#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */\n\n/******************  Bit definition for DMA_SxM1AR register  ********************/\n#define DMA_SxM1AR_M1A_Pos       (0U)\n#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                    External Interrupt/Event Controller                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for EXTI_IMR register  *******************/\n#define EXTI_IMR_MR0_Pos          (0U)\n#define EXTI_IMR_MR0_Msk          (0x1UL << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */\n#define EXTI_IMR_MR1_Pos          (1U)\n#define EXTI_IMR_MR1_Msk          (0x1UL << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */\n#define EXTI_IMR_MR2_Pos          (2U)\n#define EXTI_IMR_MR2_Msk          (0x1UL << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */\n#define EXTI_IMR_MR3_Pos          (3U)\n#define EXTI_IMR_MR3_Msk          (0x1UL << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */\n#define EXTI_IMR_MR4_Pos          (4U)\n#define EXTI_IMR_MR4_Msk          (0x1UL << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */\n#define EXTI_IMR_MR5_Pos          (5U)\n#define EXTI_IMR_MR5_Msk          (0x1UL << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */\n#define EXTI_IMR_MR6_Pos          (6U)\n#define EXTI_IMR_MR6_Msk          (0x1UL << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */\n#define EXTI_IMR_MR7_Pos          (7U)\n#define EXTI_IMR_MR7_Msk          (0x1UL << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */\n#define EXTI_IMR_MR8_Pos          (8U)\n#define EXTI_IMR_MR8_Msk          (0x1UL << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */\n#define EXTI_IMR_MR9_Pos          (9U)\n#define EXTI_IMR_MR9_Msk          (0x1UL << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */\n#define EXTI_IMR_MR10_Pos         (10U)\n#define EXTI_IMR_MR10_Msk         (0x1UL << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */\n#define EXTI_IMR_MR11_Pos         (11U)\n#define EXTI_IMR_MR11_Msk         (0x1UL << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */\n#define EXTI_IMR_MR12_Pos         (12U)\n#define EXTI_IMR_MR12_Msk         (0x1UL << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */\n#define EXTI_IMR_MR13_Pos         (13U)\n#define EXTI_IMR_MR13_Msk         (0x1UL << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */\n#define EXTI_IMR_MR14_Pos         (14U)\n#define EXTI_IMR_MR14_Msk         (0x1UL << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */\n#define EXTI_IMR_MR15_Pos         (15U)\n#define EXTI_IMR_MR15_Msk         (0x1UL << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */\n#define EXTI_IMR_MR16_Pos         (16U)\n#define EXTI_IMR_MR16_Msk         (0x1UL << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */\n#define EXTI_IMR_MR17_Pos         (17U)\n#define EXTI_IMR_MR17_Msk         (0x1UL << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */\n#define EXTI_IMR_MR18_Pos         (18U)\n#define EXTI_IMR_MR18_Msk         (0x1UL << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */\n#define EXTI_IMR_MR19_Pos         (19U)\n#define EXTI_IMR_MR19_Msk         (0x1UL << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */\n#define EXTI_IMR_MR20_Pos         (20U)\n#define EXTI_IMR_MR20_Msk         (0x1UL << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */\n#define EXTI_IMR_MR21_Pos         (21U)\n#define EXTI_IMR_MR21_Msk         (0x1UL << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */\n#define EXTI_IMR_MR22_Pos         (22U)\n#define EXTI_IMR_MR22_Msk         (0x1UL << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */\n\n/* Reference Defines */\n#define  EXTI_IMR_IM0                        EXTI_IMR_MR0\n#define  EXTI_IMR_IM1                        EXTI_IMR_MR1\n#define  EXTI_IMR_IM2                        EXTI_IMR_MR2\n#define  EXTI_IMR_IM3                        EXTI_IMR_MR3\n#define  EXTI_IMR_IM4                        EXTI_IMR_MR4\n#define  EXTI_IMR_IM5                        EXTI_IMR_MR5\n#define  EXTI_IMR_IM6                        EXTI_IMR_MR6\n#define  EXTI_IMR_IM7                        EXTI_IMR_MR7\n#define  EXTI_IMR_IM8                        EXTI_IMR_MR8\n#define  EXTI_IMR_IM9                        EXTI_IMR_MR9\n#define  EXTI_IMR_IM10                       EXTI_IMR_MR10\n#define  EXTI_IMR_IM11                       EXTI_IMR_MR11\n#define  EXTI_IMR_IM12                       EXTI_IMR_MR12\n#define  EXTI_IMR_IM13                       EXTI_IMR_MR13\n#define  EXTI_IMR_IM14                       EXTI_IMR_MR14\n#define  EXTI_IMR_IM15                       EXTI_IMR_MR15\n#define  EXTI_IMR_IM16                       EXTI_IMR_MR16\n#define  EXTI_IMR_IM17                       EXTI_IMR_MR17\n#define  EXTI_IMR_IM18                       EXTI_IMR_MR18\n#define  EXTI_IMR_IM19                       EXTI_IMR_MR19\n#define  EXTI_IMR_IM20                       EXTI_IMR_MR20\n#define  EXTI_IMR_IM21                       EXTI_IMR_MR21\n#define  EXTI_IMR_IM22                       EXTI_IMR_MR22\n#define EXTI_IMR_IM_Pos           (0U)\n#define EXTI_IMR_IM_Msk           (0x7FFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x007FFFFF */\n#define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */\n\n/*******************  Bit definition for EXTI_EMR register  *******************/\n#define EXTI_EMR_MR0_Pos          (0U)\n#define EXTI_EMR_MR0_Msk          (0x1UL << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */\n#define EXTI_EMR_MR1_Pos          (1U)\n#define EXTI_EMR_MR1_Msk          (0x1UL << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */\n#define EXTI_EMR_MR2_Pos          (2U)\n#define EXTI_EMR_MR2_Msk          (0x1UL << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */\n#define EXTI_EMR_MR3_Pos          (3U)\n#define EXTI_EMR_MR3_Msk          (0x1UL << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */\n#define EXTI_EMR_MR4_Pos          (4U)\n#define EXTI_EMR_MR4_Msk          (0x1UL << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */\n#define EXTI_EMR_MR5_Pos          (5U)\n#define EXTI_EMR_MR5_Msk          (0x1UL << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */\n#define EXTI_EMR_MR6_Pos          (6U)\n#define EXTI_EMR_MR6_Msk          (0x1UL << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */\n#define EXTI_EMR_MR7_Pos          (7U)\n#define EXTI_EMR_MR7_Msk          (0x1UL << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */\n#define EXTI_EMR_MR8_Pos          (8U)\n#define EXTI_EMR_MR8_Msk          (0x1UL << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */\n#define EXTI_EMR_MR9_Pos          (9U)\n#define EXTI_EMR_MR9_Msk          (0x1UL << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */\n#define EXTI_EMR_MR10_Pos         (10U)\n#define EXTI_EMR_MR10_Msk         (0x1UL << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */\n#define EXTI_EMR_MR11_Pos         (11U)\n#define EXTI_EMR_MR11_Msk         (0x1UL << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */\n#define EXTI_EMR_MR12_Pos         (12U)\n#define EXTI_EMR_MR12_Msk         (0x1UL << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */\n#define EXTI_EMR_MR13_Pos         (13U)\n#define EXTI_EMR_MR13_Msk         (0x1UL << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */\n#define EXTI_EMR_MR14_Pos         (14U)\n#define EXTI_EMR_MR14_Msk         (0x1UL << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */\n#define EXTI_EMR_MR15_Pos         (15U)\n#define EXTI_EMR_MR15_Msk         (0x1UL << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */\n#define EXTI_EMR_MR16_Pos         (16U)\n#define EXTI_EMR_MR16_Msk         (0x1UL << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */\n#define EXTI_EMR_MR17_Pos         (17U)\n#define EXTI_EMR_MR17_Msk         (0x1UL << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */\n#define EXTI_EMR_MR18_Pos         (18U)\n#define EXTI_EMR_MR18_Msk         (0x1UL << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */\n#define EXTI_EMR_MR19_Pos         (19U)\n#define EXTI_EMR_MR19_Msk         (0x1UL << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */\n#define EXTI_EMR_MR20_Pos         (20U)\n#define EXTI_EMR_MR20_Msk         (0x1UL << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */\n#define EXTI_EMR_MR21_Pos         (21U)\n#define EXTI_EMR_MR21_Msk         (0x1UL << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */\n#define EXTI_EMR_MR22_Pos         (22U)\n#define EXTI_EMR_MR22_Msk         (0x1UL << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */\n\n/* Reference Defines */\n#define  EXTI_EMR_EM0                        EXTI_EMR_MR0\n#define  EXTI_EMR_EM1                        EXTI_EMR_MR1\n#define  EXTI_EMR_EM2                        EXTI_EMR_MR2\n#define  EXTI_EMR_EM3                        EXTI_EMR_MR3\n#define  EXTI_EMR_EM4                        EXTI_EMR_MR4\n#define  EXTI_EMR_EM5                        EXTI_EMR_MR5\n#define  EXTI_EMR_EM6                        EXTI_EMR_MR6\n#define  EXTI_EMR_EM7                        EXTI_EMR_MR7\n#define  EXTI_EMR_EM8                        EXTI_EMR_MR8\n#define  EXTI_EMR_EM9                        EXTI_EMR_MR9\n#define  EXTI_EMR_EM10                       EXTI_EMR_MR10\n#define  EXTI_EMR_EM11                       EXTI_EMR_MR11\n#define  EXTI_EMR_EM12                       EXTI_EMR_MR12\n#define  EXTI_EMR_EM13                       EXTI_EMR_MR13\n#define  EXTI_EMR_EM14                       EXTI_EMR_MR14\n#define  EXTI_EMR_EM15                       EXTI_EMR_MR15\n#define  EXTI_EMR_EM16                       EXTI_EMR_MR16\n#define  EXTI_EMR_EM17                       EXTI_EMR_MR17\n#define  EXTI_EMR_EM18                       EXTI_EMR_MR18\n#define  EXTI_EMR_EM19                       EXTI_EMR_MR19\n#define  EXTI_EMR_EM20                       EXTI_EMR_MR20\n#define  EXTI_EMR_EM21                       EXTI_EMR_MR21\n#define  EXTI_EMR_EM22                       EXTI_EMR_MR22\n\n/******************  Bit definition for EXTI_RTSR register  *******************/\n#define EXTI_RTSR_TR0_Pos         (0U)\n#define EXTI_RTSR_TR0_Msk         (0x1UL << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */\n#define EXTI_RTSR_TR1_Pos         (1U)\n#define EXTI_RTSR_TR1_Msk         (0x1UL << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */\n#define EXTI_RTSR_TR2_Pos         (2U)\n#define EXTI_RTSR_TR2_Msk         (0x1UL << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */\n#define EXTI_RTSR_TR3_Pos         (3U)\n#define EXTI_RTSR_TR3_Msk         (0x1UL << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */\n#define EXTI_RTSR_TR4_Pos         (4U)\n#define EXTI_RTSR_TR4_Msk         (0x1UL << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */\n#define EXTI_RTSR_TR5_Pos         (5U)\n#define EXTI_RTSR_TR5_Msk         (0x1UL << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */\n#define EXTI_RTSR_TR6_Pos         (6U)\n#define EXTI_RTSR_TR6_Msk         (0x1UL << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */\n#define EXTI_RTSR_TR7_Pos         (7U)\n#define EXTI_RTSR_TR7_Msk         (0x1UL << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */\n#define EXTI_RTSR_TR8_Pos         (8U)\n#define EXTI_RTSR_TR8_Msk         (0x1UL << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */\n#define EXTI_RTSR_TR9_Pos         (9U)\n#define EXTI_RTSR_TR9_Msk         (0x1UL << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */\n#define EXTI_RTSR_TR10_Pos        (10U)\n#define EXTI_RTSR_TR10_Msk        (0x1UL << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */\n#define EXTI_RTSR_TR11_Pos        (11U)\n#define EXTI_RTSR_TR11_Msk        (0x1UL << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */\n#define EXTI_RTSR_TR12_Pos        (12U)\n#define EXTI_RTSR_TR12_Msk        (0x1UL << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */\n#define EXTI_RTSR_TR13_Pos        (13U)\n#define EXTI_RTSR_TR13_Msk        (0x1UL << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */\n#define EXTI_RTSR_TR14_Pos        (14U)\n#define EXTI_RTSR_TR14_Msk        (0x1UL << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */\n#define EXTI_RTSR_TR15_Pos        (15U)\n#define EXTI_RTSR_TR15_Msk        (0x1UL << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */\n#define EXTI_RTSR_TR16_Pos        (16U)\n#define EXTI_RTSR_TR16_Msk        (0x1UL << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */\n#define EXTI_RTSR_TR17_Pos        (17U)\n#define EXTI_RTSR_TR17_Msk        (0x1UL << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */\n#define EXTI_RTSR_TR18_Pos        (18U)\n#define EXTI_RTSR_TR18_Msk        (0x1UL << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */\n#define EXTI_RTSR_TR19_Pos        (19U)\n#define EXTI_RTSR_TR19_Msk        (0x1UL << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */\n#define EXTI_RTSR_TR20_Pos        (20U)\n#define EXTI_RTSR_TR20_Msk        (0x1UL << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */\n#define EXTI_RTSR_TR21_Pos        (21U)\n#define EXTI_RTSR_TR21_Msk        (0x1UL << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */\n#define EXTI_RTSR_TR22_Pos        (22U)\n#define EXTI_RTSR_TR22_Msk        (0x1UL << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_FTSR register  *******************/\n#define EXTI_FTSR_TR0_Pos         (0U)\n#define EXTI_FTSR_TR0_Msk         (0x1UL << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */\n#define EXTI_FTSR_TR1_Pos         (1U)\n#define EXTI_FTSR_TR1_Msk         (0x1UL << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */\n#define EXTI_FTSR_TR2_Pos         (2U)\n#define EXTI_FTSR_TR2_Msk         (0x1UL << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */\n#define EXTI_FTSR_TR3_Pos         (3U)\n#define EXTI_FTSR_TR3_Msk         (0x1UL << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */\n#define EXTI_FTSR_TR4_Pos         (4U)\n#define EXTI_FTSR_TR4_Msk         (0x1UL << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */\n#define EXTI_FTSR_TR5_Pos         (5U)\n#define EXTI_FTSR_TR5_Msk         (0x1UL << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */\n#define EXTI_FTSR_TR6_Pos         (6U)\n#define EXTI_FTSR_TR6_Msk         (0x1UL << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */\n#define EXTI_FTSR_TR7_Pos         (7U)\n#define EXTI_FTSR_TR7_Msk         (0x1UL << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */\n#define EXTI_FTSR_TR8_Pos         (8U)\n#define EXTI_FTSR_TR8_Msk         (0x1UL << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */\n#define EXTI_FTSR_TR9_Pos         (9U)\n#define EXTI_FTSR_TR9_Msk         (0x1UL << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */\n#define EXTI_FTSR_TR10_Pos        (10U)\n#define EXTI_FTSR_TR10_Msk        (0x1UL << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */\n#define EXTI_FTSR_TR11_Pos        (11U)\n#define EXTI_FTSR_TR11_Msk        (0x1UL << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */\n#define EXTI_FTSR_TR12_Pos        (12U)\n#define EXTI_FTSR_TR12_Msk        (0x1UL << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */\n#define EXTI_FTSR_TR13_Pos        (13U)\n#define EXTI_FTSR_TR13_Msk        (0x1UL << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */\n#define EXTI_FTSR_TR14_Pos        (14U)\n#define EXTI_FTSR_TR14_Msk        (0x1UL << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */\n#define EXTI_FTSR_TR15_Pos        (15U)\n#define EXTI_FTSR_TR15_Msk        (0x1UL << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */\n#define EXTI_FTSR_TR16_Pos        (16U)\n#define EXTI_FTSR_TR16_Msk        (0x1UL << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */\n#define EXTI_FTSR_TR17_Pos        (17U)\n#define EXTI_FTSR_TR17_Msk        (0x1UL << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */\n#define EXTI_FTSR_TR18_Pos        (18U)\n#define EXTI_FTSR_TR18_Msk        (0x1UL << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */\n#define EXTI_FTSR_TR19_Pos        (19U)\n#define EXTI_FTSR_TR19_Msk        (0x1UL << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */\n#define EXTI_FTSR_TR20_Pos        (20U)\n#define EXTI_FTSR_TR20_Msk        (0x1UL << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */\n#define EXTI_FTSR_TR21_Pos        (21U)\n#define EXTI_FTSR_TR21_Msk        (0x1UL << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */\n#define EXTI_FTSR_TR22_Pos        (22U)\n#define EXTI_FTSR_TR22_Msk        (0x1UL << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_SWIER register  ******************/\n#define EXTI_SWIER_SWIER0_Pos     (0U)\n#define EXTI_SWIER_SWIER0_Msk     (0x1UL << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */\n#define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */\n#define EXTI_SWIER_SWIER1_Pos     (1U)\n#define EXTI_SWIER_SWIER1_Msk     (0x1UL << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */\n#define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */\n#define EXTI_SWIER_SWIER2_Pos     (2U)\n#define EXTI_SWIER_SWIER2_Msk     (0x1UL << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */\n#define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */\n#define EXTI_SWIER_SWIER3_Pos     (3U)\n#define EXTI_SWIER_SWIER3_Msk     (0x1UL << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */\n#define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */\n#define EXTI_SWIER_SWIER4_Pos     (4U)\n#define EXTI_SWIER_SWIER4_Msk     (0x1UL << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */\n#define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */\n#define EXTI_SWIER_SWIER5_Pos     (5U)\n#define EXTI_SWIER_SWIER5_Msk     (0x1UL << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */\n#define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */\n#define EXTI_SWIER_SWIER6_Pos     (6U)\n#define EXTI_SWIER_SWIER6_Msk     (0x1UL << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */\n#define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */\n#define EXTI_SWIER_SWIER7_Pos     (7U)\n#define EXTI_SWIER_SWIER7_Msk     (0x1UL << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */\n#define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */\n#define EXTI_SWIER_SWIER8_Pos     (8U)\n#define EXTI_SWIER_SWIER8_Msk     (0x1UL << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */\n#define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */\n#define EXTI_SWIER_SWIER9_Pos     (9U)\n#define EXTI_SWIER_SWIER9_Msk     (0x1UL << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */\n#define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */\n#define EXTI_SWIER_SWIER10_Pos    (10U)\n#define EXTI_SWIER_SWIER10_Msk    (0x1UL << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */\n#define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */\n#define EXTI_SWIER_SWIER11_Pos    (11U)\n#define EXTI_SWIER_SWIER11_Msk    (0x1UL << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */\n#define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */\n#define EXTI_SWIER_SWIER12_Pos    (12U)\n#define EXTI_SWIER_SWIER12_Msk    (0x1UL << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */\n#define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */\n#define EXTI_SWIER_SWIER13_Pos    (13U)\n#define EXTI_SWIER_SWIER13_Msk    (0x1UL << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */\n#define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */\n#define EXTI_SWIER_SWIER14_Pos    (14U)\n#define EXTI_SWIER_SWIER14_Msk    (0x1UL << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */\n#define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */\n#define EXTI_SWIER_SWIER15_Pos    (15U)\n#define EXTI_SWIER_SWIER15_Msk    (0x1UL << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */\n#define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */\n#define EXTI_SWIER_SWIER16_Pos    (16U)\n#define EXTI_SWIER_SWIER16_Msk    (0x1UL << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */\n#define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */\n#define EXTI_SWIER_SWIER17_Pos    (17U)\n#define EXTI_SWIER_SWIER17_Msk    (0x1UL << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */\n#define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */\n#define EXTI_SWIER_SWIER18_Pos    (18U)\n#define EXTI_SWIER_SWIER18_Msk    (0x1UL << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */\n#define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */\n#define EXTI_SWIER_SWIER19_Pos    (19U)\n#define EXTI_SWIER_SWIER19_Msk    (0x1UL << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */\n#define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */\n#define EXTI_SWIER_SWIER20_Pos    (20U)\n#define EXTI_SWIER_SWIER20_Msk    (0x1UL << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */\n#define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */\n#define EXTI_SWIER_SWIER21_Pos    (21U)\n#define EXTI_SWIER_SWIER21_Msk    (0x1UL << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */\n#define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */\n#define EXTI_SWIER_SWIER22_Pos    (22U)\n#define EXTI_SWIER_SWIER22_Msk    (0x1UL << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */\n#define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */\n\n/*******************  Bit definition for EXTI_PR register  ********************/\n#define EXTI_PR_PR0_Pos           (0U)\n#define EXTI_PR_PR0_Msk           (0x1UL << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */\n#define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */\n#define EXTI_PR_PR1_Pos           (1U)\n#define EXTI_PR_PR1_Msk           (0x1UL << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */\n#define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */\n#define EXTI_PR_PR2_Pos           (2U)\n#define EXTI_PR_PR2_Msk           (0x1UL << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */\n#define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */\n#define EXTI_PR_PR3_Pos           (3U)\n#define EXTI_PR_PR3_Msk           (0x1UL << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */\n#define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */\n#define EXTI_PR_PR4_Pos           (4U)\n#define EXTI_PR_PR4_Msk           (0x1UL << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */\n#define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */\n#define EXTI_PR_PR5_Pos           (5U)\n#define EXTI_PR_PR5_Msk           (0x1UL << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */\n#define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */\n#define EXTI_PR_PR6_Pos           (6U)\n#define EXTI_PR_PR6_Msk           (0x1UL << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */\n#define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */\n#define EXTI_PR_PR7_Pos           (7U)\n#define EXTI_PR_PR7_Msk           (0x1UL << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */\n#define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */\n#define EXTI_PR_PR8_Pos           (8U)\n#define EXTI_PR_PR8_Msk           (0x1UL << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */\n#define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */\n#define EXTI_PR_PR9_Pos           (9U)\n#define EXTI_PR_PR9_Msk           (0x1UL << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */\n#define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */\n#define EXTI_PR_PR10_Pos          (10U)\n#define EXTI_PR_PR10_Msk          (0x1UL << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */\n#define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */\n#define EXTI_PR_PR11_Pos          (11U)\n#define EXTI_PR_PR11_Msk          (0x1UL << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */\n#define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */\n#define EXTI_PR_PR12_Pos          (12U)\n#define EXTI_PR_PR12_Msk          (0x1UL << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */\n#define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */\n#define EXTI_PR_PR13_Pos          (13U)\n#define EXTI_PR_PR13_Msk          (0x1UL << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */\n#define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */\n#define EXTI_PR_PR14_Pos          (14U)\n#define EXTI_PR_PR14_Msk          (0x1UL << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */\n#define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */\n#define EXTI_PR_PR15_Pos          (15U)\n#define EXTI_PR_PR15_Msk          (0x1UL << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */\n#define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */\n#define EXTI_PR_PR16_Pos          (16U)\n#define EXTI_PR_PR16_Msk          (0x1UL << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */\n#define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */\n#define EXTI_PR_PR17_Pos          (17U)\n#define EXTI_PR_PR17_Msk          (0x1UL << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */\n#define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */\n#define EXTI_PR_PR18_Pos          (18U)\n#define EXTI_PR_PR18_Msk          (0x1UL << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */\n#define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */\n#define EXTI_PR_PR19_Pos          (19U)\n#define EXTI_PR_PR19_Msk          (0x1UL << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */\n#define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */\n#define EXTI_PR_PR20_Pos          (20U)\n#define EXTI_PR_PR20_Msk          (0x1UL << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */\n#define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */\n#define EXTI_PR_PR21_Pos          (21U)\n#define EXTI_PR_PR21_Msk          (0x1UL << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */\n#define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */\n#define EXTI_PR_PR22_Pos          (22U)\n#define EXTI_PR_PR22_Msk          (0x1UL << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */\n#define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    FLASH                                   */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bits definition for FLASH_ACR register  *****************/\n#define FLASH_ACR_LATENCY_Pos          (0U)\n#define FLASH_ACR_LATENCY_Msk          (0xFUL << FLASH_ACR_LATENCY_Pos)         /*!< 0x0000000F */\n#define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk\n#define FLASH_ACR_LATENCY_0WS          0x00000000U\n#define FLASH_ACR_LATENCY_1WS          0x00000001U\n#define FLASH_ACR_LATENCY_2WS          0x00000002U\n#define FLASH_ACR_LATENCY_3WS          0x00000003U\n#define FLASH_ACR_LATENCY_4WS          0x00000004U\n#define FLASH_ACR_LATENCY_5WS          0x00000005U\n#define FLASH_ACR_LATENCY_6WS          0x00000006U\n#define FLASH_ACR_LATENCY_7WS          0x00000007U\n\n#define FLASH_ACR_PRFTEN_Pos           (8U)\n#define FLASH_ACR_PRFTEN_Msk           (0x1UL << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */\n#define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk\n#define FLASH_ACR_ICEN_Pos             (9U)\n#define FLASH_ACR_ICEN_Msk             (0x1UL << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */\n#define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk\n#define FLASH_ACR_DCEN_Pos             (10U)\n#define FLASH_ACR_DCEN_Msk             (0x1UL << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */\n#define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk\n#define FLASH_ACR_ICRST_Pos            (11U)\n#define FLASH_ACR_ICRST_Msk            (0x1UL << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */\n#define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk\n#define FLASH_ACR_DCRST_Pos            (12U)\n#define FLASH_ACR_DCRST_Msk            (0x1UL << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */\n#define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk\n#define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)\n#define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */\n#define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk\n#define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)\n#define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */\n#define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk\n\n/*******************  Bits definition for FLASH_SR register  ******************/\n#define FLASH_SR_EOP_Pos               (0U)\n#define FLASH_SR_EOP_Msk               (0x1UL << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */\n#define FLASH_SR_EOP                   FLASH_SR_EOP_Msk\n#define FLASH_SR_SOP_Pos               (1U)\n#define FLASH_SR_SOP_Msk               (0x1UL << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */\n#define FLASH_SR_SOP                   FLASH_SR_SOP_Msk\n#define FLASH_SR_WRPERR_Pos            (4U)\n#define FLASH_SR_WRPERR_Msk            (0x1UL << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */\n#define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk\n#define FLASH_SR_PGAERR_Pos            (5U)\n#define FLASH_SR_PGAERR_Msk            (0x1UL << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */\n#define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk\n#define FLASH_SR_PGPERR_Pos            (6U)\n#define FLASH_SR_PGPERR_Msk            (0x1UL << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */\n#define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk\n#define FLASH_SR_PGSERR_Pos            (7U)\n#define FLASH_SR_PGSERR_Msk            (0x1UL << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */\n#define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk\n#define FLASH_SR_RDERR_Pos            (8U)\n#define FLASH_SR_RDERR_Msk            (0x1UL << FLASH_SR_RDERR_Pos)             /*!< 0x00000100 */\n#define FLASH_SR_RDERR                FLASH_SR_RDERR_Msk\n#define FLASH_SR_BSY_Pos               (16U)\n#define FLASH_SR_BSY_Msk               (0x1UL << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */\n#define FLASH_SR_BSY                   FLASH_SR_BSY_Msk\n\n/*******************  Bits definition for FLASH_CR register  ******************/\n#define FLASH_CR_PG_Pos                (0U)\n#define FLASH_CR_PG_Msk                (0x1UL << FLASH_CR_PG_Pos)               /*!< 0x00000001 */\n#define FLASH_CR_PG                    FLASH_CR_PG_Msk\n#define FLASH_CR_SER_Pos               (1U)\n#define FLASH_CR_SER_Msk               (0x1UL << FLASH_CR_SER_Pos)              /*!< 0x00000002 */\n#define FLASH_CR_SER                   FLASH_CR_SER_Msk\n#define FLASH_CR_MER_Pos               (2U)\n#define FLASH_CR_MER_Msk               (0x1UL << FLASH_CR_MER_Pos)              /*!< 0x00000004 */\n#define FLASH_CR_MER                   FLASH_CR_MER_Msk\n#define FLASH_CR_SNB_Pos               (3U)\n#define FLASH_CR_SNB_Msk               (0x1FUL << FLASH_CR_SNB_Pos)             /*!< 0x000000F8 */\n#define FLASH_CR_SNB                   FLASH_CR_SNB_Msk\n#define FLASH_CR_SNB_0                 (0x01UL << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */\n#define FLASH_CR_SNB_1                 (0x02UL << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */\n#define FLASH_CR_SNB_2                 (0x04UL << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */\n#define FLASH_CR_SNB_3                 (0x08UL << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */\n#define FLASH_CR_SNB_4                 (0x10UL << FLASH_CR_SNB_Pos)             /*!< 0x00000080 */\n#define FLASH_CR_PSIZE_Pos             (8U)\n#define FLASH_CR_PSIZE_Msk             (0x3UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */\n#define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk\n#define FLASH_CR_PSIZE_0               (0x1UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */\n#define FLASH_CR_PSIZE_1               (0x2UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */\n#define FLASH_CR_STRT_Pos              (16U)\n#define FLASH_CR_STRT_Msk              (0x1UL << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */\n#define FLASH_CR_STRT                  FLASH_CR_STRT_Msk\n#define FLASH_CR_EOPIE_Pos             (24U)\n#define FLASH_CR_EOPIE_Msk             (0x1UL << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */\n#define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk\n#define FLASH_CR_LOCK_Pos              (31U)\n#define FLASH_CR_LOCK_Msk              (0x1UL << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */\n#define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk\n\n/*******************  Bits definition for FLASH_OPTCR register  ***************/\n#define FLASH_OPTCR_OPTLOCK_Pos        (0U)\n#define FLASH_OPTCR_OPTLOCK_Msk        (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */\n#define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk\n#define FLASH_OPTCR_OPTSTRT_Pos        (1U)\n#define FLASH_OPTCR_OPTSTRT_Msk        (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */\n#define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk\n\n#define FLASH_OPTCR_BOR_LEV_0          0x00000004U\n#define FLASH_OPTCR_BOR_LEV_1          0x00000008U\n#define FLASH_OPTCR_BOR_LEV_Pos        (2U)\n#define FLASH_OPTCR_BOR_LEV_Msk        (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */\n#define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk\n#define FLASH_OPTCR_WDG_SW_Pos         (5U)\n#define FLASH_OPTCR_WDG_SW_Msk         (0x1UL << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */\n#define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk\n#define FLASH_OPTCR_nRST_STOP_Pos      (6U)\n#define FLASH_OPTCR_nRST_STOP_Msk      (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */\n#define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk\n#define FLASH_OPTCR_nRST_STDBY_Pos     (7U)\n#define FLASH_OPTCR_nRST_STDBY_Msk     (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */\n#define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk\n#define FLASH_OPTCR_RDP_Pos            (8U)\n#define FLASH_OPTCR_RDP_Msk            (0xFFUL << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */\n#define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk\n#define FLASH_OPTCR_RDP_0              (0x01UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */\n#define FLASH_OPTCR_RDP_1              (0x02UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */\n#define FLASH_OPTCR_RDP_2              (0x04UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */\n#define FLASH_OPTCR_RDP_3              (0x08UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */\n#define FLASH_OPTCR_RDP_4              (0x10UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */\n#define FLASH_OPTCR_RDP_5              (0x20UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */\n#define FLASH_OPTCR_RDP_6              (0x40UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */\n#define FLASH_OPTCR_RDP_7              (0x80UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */\n#define FLASH_OPTCR_nWRP_Pos           (16U)\n#define FLASH_OPTCR_nWRP_Msk           (0xFFFUL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x0FFF0000 */\n#define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk\n#define FLASH_OPTCR_nWRP_0             0x00010000U\n#define FLASH_OPTCR_nWRP_1             0x00020000U\n#define FLASH_OPTCR_nWRP_2             0x00040000U\n#define FLASH_OPTCR_nWRP_3             0x00080000U\n#define FLASH_OPTCR_nWRP_4             0x00100000U\n#define FLASH_OPTCR_nWRP_5             0x00200000U\n#define FLASH_OPTCR_nWRP_6             0x00400000U\n#define FLASH_OPTCR_nWRP_7             0x00800000U\n#define FLASH_OPTCR_nWRP_8             0x01000000U\n#define FLASH_OPTCR_nWRP_9             0x02000000U\n#define FLASH_OPTCR_nWRP_10            0x04000000U\n#define FLASH_OPTCR_nWRP_11            0x08000000U\n\n/******************  Bits definition for FLASH_OPTCR1 register  ***************/\n#define FLASH_OPTCR1_nWRP_Pos          (16U)\n#define FLASH_OPTCR1_nWRP_Msk          (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */\n#define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk\n#define FLASH_OPTCR1_nWRP_0            (0x001UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */\n#define FLASH_OPTCR1_nWRP_1            (0x002UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */\n#define FLASH_OPTCR1_nWRP_2            (0x004UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */\n#define FLASH_OPTCR1_nWRP_3            (0x008UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */\n#define FLASH_OPTCR1_nWRP_4            (0x010UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */\n#define FLASH_OPTCR1_nWRP_5            (0x020UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */\n#define FLASH_OPTCR1_nWRP_6            (0x040UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */\n#define FLASH_OPTCR1_nWRP_7            (0x080UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */\n#define FLASH_OPTCR1_nWRP_8            (0x100UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */\n#define FLASH_OPTCR1_nWRP_9            (0x200UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */\n#define FLASH_OPTCR1_nWRP_10           (0x400UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */\n#define FLASH_OPTCR1_nWRP_11           (0x800UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                   Flexible Static Memory Controller                        */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for FSMC_BCR1 register  *******************/\n#define FSMC_BCR1_MBKEN_Pos          (0U)\n#define FSMC_BCR1_MBKEN_Msk          (0x1UL << FSMC_BCR1_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR1_MBKEN              FSMC_BCR1_MBKEN_Msk                       /*!<Memory bank enable bit                 */\n#define FSMC_BCR1_MUXEN_Pos          (1U)\n#define FSMC_BCR1_MUXEN_Msk          (0x1UL << FSMC_BCR1_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR1_MUXEN              FSMC_BCR1_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR1_MTYP_Pos           (2U)\n#define FSMC_BCR1_MTYP_Msk           (0x3UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR1_MTYP               FSMC_BCR1_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR1_MTYP_0             (0x1UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR1_MTYP_1             (0x2UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR1_MWID_Pos           (4U)\n#define FSMC_BCR1_MWID_Msk           (0x3UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR1_MWID               FSMC_BCR1_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR1_MWID_0             (0x1UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR1_MWID_1             (0x2UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR1_FACCEN_Pos         (6U)\n#define FSMC_BCR1_FACCEN_Msk         (0x1UL << FSMC_BCR1_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR1_FACCEN             FSMC_BCR1_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR1_BURSTEN_Pos        (8U)\n#define FSMC_BCR1_BURSTEN_Msk        (0x1UL << FSMC_BCR1_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR1_BURSTEN            FSMC_BCR1_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR1_WAITPOL_Pos        (9U)\n#define FSMC_BCR1_WAITPOL_Msk        (0x1UL << FSMC_BCR1_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR1_WAITPOL            FSMC_BCR1_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR1_WAITCFG_Pos        (11U)\n#define FSMC_BCR1_WAITCFG_Msk        (0x1UL << FSMC_BCR1_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR1_WAITCFG            FSMC_BCR1_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR1_WREN_Pos           (12U)\n#define FSMC_BCR1_WREN_Msk           (0x1UL << FSMC_BCR1_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR1_WREN               FSMC_BCR1_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR1_WAITEN_Pos         (13U)\n#define FSMC_BCR1_WAITEN_Msk         (0x1UL << FSMC_BCR1_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR1_WAITEN             FSMC_BCR1_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR1_EXTMOD_Pos         (14U)\n#define FSMC_BCR1_EXTMOD_Msk         (0x1UL << FSMC_BCR1_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR1_EXTMOD             FSMC_BCR1_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR1_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR1_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR1_ASYNCWAIT          FSMC_BCR1_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR1_CPSIZE_Pos         (16U)\n#define FSMC_BCR1_CPSIZE_Msk         (0x7UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR1_CPSIZE             FSMC_BCR1_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR1_CPSIZE_0           (0x1UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR1_CPSIZE_1           (0x2UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR1_CPSIZE_2           (0x4UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR1_CBURSTRW_Pos       (19U)\n#define FSMC_BCR1_CBURSTRW_Msk       (0x1UL << FSMC_BCR1_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR1_CBURSTRW           FSMC_BCR1_CBURSTRW_Msk                    /*!<Write burst enable                     */\n#define FSMC_BCR1_CCLKEN_Pos         (20U)\n#define FSMC_BCR1_CCLKEN_Msk         (0x1UL << FSMC_BCR1_CCLKEN_Pos)            /*!< 0x00100000 */\n#define FSMC_BCR1_CCLKEN             FSMC_BCR1_CCLKEN_Msk                      /*!<Continous clock enable     */\n#define FSMC_BCR1_WFDIS_Pos          (21U)\n#define FSMC_BCR1_WFDIS_Msk          (0x1UL << FSMC_BCR1_WFDIS_Pos)             /*!< 0x00200000 */\n#define FSMC_BCR1_WFDIS              FSMC_BCR1_WFDIS_Msk                       /*!<Write FIFO Disable         */\n\n/******************  Bit definition for FSMC_BCR2 register  *******************/\n#define FSMC_BCR2_MBKEN_Pos          (0U)\n#define FSMC_BCR2_MBKEN_Msk          (0x1UL << FSMC_BCR2_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR2_MBKEN              FSMC_BCR2_MBKEN_Msk                       /*!<Memory bank enable bit                */\n#define FSMC_BCR2_MUXEN_Pos          (1U)\n#define FSMC_BCR2_MUXEN_Msk          (0x1UL << FSMC_BCR2_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR2_MUXEN              FSMC_BCR2_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR2_MTYP_Pos           (2U)\n#define FSMC_BCR2_MTYP_Msk           (0x3UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR2_MTYP               FSMC_BCR2_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR2_MTYP_0             (0x1UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR2_MTYP_1             (0x2UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR2_MWID_Pos           (4U)\n#define FSMC_BCR2_MWID_Msk           (0x3UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR2_MWID               FSMC_BCR2_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR2_MWID_0             (0x1UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR2_MWID_1             (0x2UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR2_FACCEN_Pos         (6U)\n#define FSMC_BCR2_FACCEN_Msk         (0x1UL << FSMC_BCR2_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR2_FACCEN             FSMC_BCR2_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR2_BURSTEN_Pos        (8U)\n#define FSMC_BCR2_BURSTEN_Msk        (0x1UL << FSMC_BCR2_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR2_BURSTEN            FSMC_BCR2_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR2_WAITPOL_Pos        (9U)\n#define FSMC_BCR2_WAITPOL_Msk        (0x1UL << FSMC_BCR2_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR2_WAITPOL            FSMC_BCR2_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR2_WAITCFG_Pos        (11U)\n#define FSMC_BCR2_WAITCFG_Msk        (0x1UL << FSMC_BCR2_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR2_WAITCFG            FSMC_BCR2_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR2_WREN_Pos           (12U)\n#define FSMC_BCR2_WREN_Msk           (0x1UL << FSMC_BCR2_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR2_WREN               FSMC_BCR2_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR2_WAITEN_Pos         (13U)\n#define FSMC_BCR2_WAITEN_Msk         (0x1UL << FSMC_BCR2_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR2_WAITEN             FSMC_BCR2_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR2_EXTMOD_Pos         (14U)\n#define FSMC_BCR2_EXTMOD_Msk         (0x1UL << FSMC_BCR2_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR2_EXTMOD             FSMC_BCR2_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR2_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR2_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR2_ASYNCWAIT          FSMC_BCR2_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR2_CPSIZE_Pos         (16U)\n#define FSMC_BCR2_CPSIZE_Msk         (0x7UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR2_CPSIZE             FSMC_BCR2_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR2_CPSIZE_0           (0x1UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR2_CPSIZE_1           (0x2UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR2_CPSIZE_2           (0x4UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR2_CBURSTRW_Pos       (19U)\n#define FSMC_BCR2_CBURSTRW_Msk       (0x1UL << FSMC_BCR2_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR2_CBURSTRW           FSMC_BCR2_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BCR3 register  *******************/\n#define FSMC_BCR3_MBKEN_Pos          (0U)\n#define FSMC_BCR3_MBKEN_Msk          (0x1UL << FSMC_BCR3_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR3_MBKEN              FSMC_BCR3_MBKEN_Msk                       /*!<Memory bank enable bit                 */\n#define FSMC_BCR3_MUXEN_Pos          (1U)\n#define FSMC_BCR3_MUXEN_Msk          (0x1UL << FSMC_BCR3_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR3_MUXEN              FSMC_BCR3_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR3_MTYP_Pos           (2U)\n#define FSMC_BCR3_MTYP_Msk           (0x3UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR3_MTYP               FSMC_BCR3_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR3_MTYP_0             (0x1UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR3_MTYP_1             (0x2UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR3_MWID_Pos           (4U)\n#define FSMC_BCR3_MWID_Msk           (0x3UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR3_MWID               FSMC_BCR3_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR3_MWID_0             (0x1UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR3_MWID_1             (0x2UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR3_FACCEN_Pos         (6U)\n#define FSMC_BCR3_FACCEN_Msk         (0x1UL << FSMC_BCR3_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR3_FACCEN             FSMC_BCR3_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR3_BURSTEN_Pos        (8U)\n#define FSMC_BCR3_BURSTEN_Msk        (0x1UL << FSMC_BCR3_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR3_BURSTEN            FSMC_BCR3_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR3_WAITPOL_Pos        (9U)\n#define FSMC_BCR3_WAITPOL_Msk        (0x1UL << FSMC_BCR3_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR3_WAITPOL            FSMC_BCR3_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR3_WAITCFG_Pos        (11U)\n#define FSMC_BCR3_WAITCFG_Msk        (0x1UL << FSMC_BCR3_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR3_WAITCFG            FSMC_BCR3_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR3_WREN_Pos           (12U)\n#define FSMC_BCR3_WREN_Msk           (0x1UL << FSMC_BCR3_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR3_WREN               FSMC_BCR3_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR3_WAITEN_Pos         (13U)\n#define FSMC_BCR3_WAITEN_Msk         (0x1UL << FSMC_BCR3_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR3_WAITEN             FSMC_BCR3_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR3_EXTMOD_Pos         (14U)\n#define FSMC_BCR3_EXTMOD_Msk         (0x1UL << FSMC_BCR3_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR3_EXTMOD             FSMC_BCR3_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR3_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR3_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR3_ASYNCWAIT          FSMC_BCR3_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR3_CPSIZE_Pos         (16U)\n#define FSMC_BCR3_CPSIZE_Msk         (0x7UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR3_CPSIZE             FSMC_BCR3_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR3_CPSIZE_0           (0x1UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR3_CPSIZE_1           (0x2UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR3_CPSIZE_2           (0x4UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR3_CBURSTRW_Pos       (19U)\n#define FSMC_BCR3_CBURSTRW_Msk       (0x1UL << FSMC_BCR3_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR3_CBURSTRW           FSMC_BCR3_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BCR4 register  *******************/\n#define FSMC_BCR4_MBKEN_Pos          (0U)\n#define FSMC_BCR4_MBKEN_Msk          (0x1UL << FSMC_BCR4_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR4_MBKEN              FSMC_BCR4_MBKEN_Msk                       /*!<Memory bank enable bit */\n#define FSMC_BCR4_MUXEN_Pos          (1U)\n#define FSMC_BCR4_MUXEN_Msk          (0x1UL << FSMC_BCR4_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR4_MUXEN              FSMC_BCR4_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR4_MTYP_Pos           (2U)\n#define FSMC_BCR4_MTYP_Msk           (0x3UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR4_MTYP               FSMC_BCR4_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR4_MTYP_0             (0x1UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR4_MTYP_1             (0x2UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR4_MWID_Pos           (4U)\n#define FSMC_BCR4_MWID_Msk           (0x3UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR4_MWID               FSMC_BCR4_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR4_MWID_0             (0x1UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR4_MWID_1             (0x2UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR4_FACCEN_Pos         (6U)\n#define FSMC_BCR4_FACCEN_Msk         (0x1UL << FSMC_BCR4_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR4_FACCEN             FSMC_BCR4_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR4_BURSTEN_Pos        (8U)\n#define FSMC_BCR4_BURSTEN_Msk        (0x1UL << FSMC_BCR4_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR4_BURSTEN            FSMC_BCR4_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR4_WAITPOL_Pos        (9U)\n#define FSMC_BCR4_WAITPOL_Msk        (0x1UL << FSMC_BCR4_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR4_WAITPOL            FSMC_BCR4_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR4_WAITCFG_Pos        (11U)\n#define FSMC_BCR4_WAITCFG_Msk        (0x1UL << FSMC_BCR4_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR4_WAITCFG            FSMC_BCR4_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR4_WREN_Pos           (12U)\n#define FSMC_BCR4_WREN_Msk           (0x1UL << FSMC_BCR4_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR4_WREN               FSMC_BCR4_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR4_WAITEN_Pos         (13U)\n#define FSMC_BCR4_WAITEN_Msk         (0x1UL << FSMC_BCR4_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR4_WAITEN             FSMC_BCR4_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR4_EXTMOD_Pos         (14U)\n#define FSMC_BCR4_EXTMOD_Msk         (0x1UL << FSMC_BCR4_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR4_EXTMOD             FSMC_BCR4_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR4_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR4_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR4_ASYNCWAIT          FSMC_BCR4_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR4_CPSIZE_Pos         (16U)\n#define FSMC_BCR4_CPSIZE_Msk         (0x7UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR4_CPSIZE             FSMC_BCR4_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR4_CPSIZE_0           (0x1UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR4_CPSIZE_1           (0x2UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR4_CPSIZE_2           (0x4UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR4_CBURSTRW_Pos       (19U)\n#define FSMC_BCR4_CBURSTRW_Msk       (0x1UL << FSMC_BCR4_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR4_CBURSTRW           FSMC_BCR4_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BTR1 register  ******************/\n#define FSMC_BTR1_ADDSET_Pos         (0U)\n#define FSMC_BTR1_ADDSET_Msk         (0xFUL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR1_ADDSET             FSMC_BTR1_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR1_ADDSET_0           (0x1UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR1_ADDSET_1           (0x2UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR1_ADDSET_2           (0x4UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR1_ADDSET_3           (0x8UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR1_ADDHLD_Pos         (4U)\n#define FSMC_BTR1_ADDHLD_Msk         (0xFUL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR1_ADDHLD             FSMC_BTR1_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR1_ADDHLD_0           (0x1UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR1_ADDHLD_1           (0x2UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR1_ADDHLD_2           (0x4UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR1_ADDHLD_3           (0x8UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR1_DATAST_Pos         (8U)\n#define FSMC_BTR1_DATAST_Msk         (0xFFUL << FSMC_BTR1_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR1_DATAST             FSMC_BTR1_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR1_DATAST_0           (0x01UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR1_DATAST_1           (0x02UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR1_DATAST_2           (0x04UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR1_DATAST_3           (0x08UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR1_DATAST_4           (0x10UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR1_DATAST_5           (0x20UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR1_DATAST_6           (0x40UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR1_DATAST_7           (0x80UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR1_BUSTURN_Pos        (16U)\n#define FSMC_BTR1_BUSTURN_Msk        (0xFUL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR1_BUSTURN            FSMC_BTR1_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR1_BUSTURN_0          (0x1UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR1_BUSTURN_1          (0x2UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR1_BUSTURN_2          (0x4UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR1_BUSTURN_3          (0x8UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR1_CLKDIV_Pos         (20U)\n#define FSMC_BTR1_CLKDIV_Msk         (0xFUL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR1_CLKDIV             FSMC_BTR1_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR1_CLKDIV_0           (0x1UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR1_CLKDIV_1           (0x2UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR1_CLKDIV_2           (0x4UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR1_CLKDIV_3           (0x8UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR1_DATLAT_Pos         (24U)\n#define FSMC_BTR1_DATLAT_Msk         (0xFUL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR1_DATLAT             FSMC_BTR1_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR1_DATLAT_0           (0x1UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR1_DATLAT_1           (0x2UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR1_DATLAT_2           (0x4UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR1_DATLAT_3           (0x8UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR1_ACCMOD_Pos         (28U)\n#define FSMC_BTR1_ACCMOD_Msk         (0x3UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR1_ACCMOD             FSMC_BTR1_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR1_ACCMOD_0           (0x1UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR1_ACCMOD_1           (0x2UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BTR2 register  *******************/\n#define FSMC_BTR2_ADDSET_Pos         (0U)\n#define FSMC_BTR2_ADDSET_Msk         (0xFUL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR2_ADDSET             FSMC_BTR2_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR2_ADDSET_0           (0x1UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR2_ADDSET_1           (0x2UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR2_ADDSET_2           (0x4UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR2_ADDSET_3           (0x8UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR2_ADDHLD_Pos         (4U)\n#define FSMC_BTR2_ADDHLD_Msk         (0xFUL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR2_ADDHLD             FSMC_BTR2_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR2_ADDHLD_0           (0x1UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR2_ADDHLD_1           (0x2UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR2_ADDHLD_2           (0x4UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR2_ADDHLD_3           (0x8UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR2_DATAST_Pos         (8U)\n#define FSMC_BTR2_DATAST_Msk         (0xFFUL << FSMC_BTR2_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR2_DATAST             FSMC_BTR2_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR2_DATAST_0           (0x01UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR2_DATAST_1           (0x02UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR2_DATAST_2           (0x04UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR2_DATAST_3           (0x08UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR2_DATAST_4           (0x10UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR2_DATAST_5           (0x20UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR2_DATAST_6           (0x40UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR2_DATAST_7           (0x80UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR2_BUSTURN_Pos        (16U)\n#define FSMC_BTR2_BUSTURN_Msk        (0xFUL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR2_BUSTURN            FSMC_BTR2_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR2_BUSTURN_0          (0x1UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR2_BUSTURN_1          (0x2UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR2_BUSTURN_2          (0x4UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR2_BUSTURN_3          (0x8UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR2_CLKDIV_Pos         (20U)\n#define FSMC_BTR2_CLKDIV_Msk         (0xFUL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR2_CLKDIV             FSMC_BTR2_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR2_CLKDIV_0           (0x1UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR2_CLKDIV_1           (0x2UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR2_CLKDIV_2           (0x4UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR2_CLKDIV_3           (0x8UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR2_DATLAT_Pos         (24U)\n#define FSMC_BTR2_DATLAT_Msk         (0xFUL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR2_DATLAT             FSMC_BTR2_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR2_DATLAT_0           (0x1UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR2_DATLAT_1           (0x2UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR2_DATLAT_2           (0x4UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR2_DATLAT_3           (0x8UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR2_ACCMOD_Pos         (28U)\n#define FSMC_BTR2_ACCMOD_Msk         (0x3UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR2_ACCMOD             FSMC_BTR2_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR2_ACCMOD_0           (0x1UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR2_ACCMOD_1           (0x2UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/*******************  Bit definition for FSMC_BTR3 register  *******************/\n#define FSMC_BTR3_ADDSET_Pos         (0U)\n#define FSMC_BTR3_ADDSET_Msk         (0xFUL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR3_ADDSET             FSMC_BTR3_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR3_ADDSET_0           (0x1UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR3_ADDSET_1           (0x2UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR3_ADDSET_2           (0x4UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR3_ADDSET_3           (0x8UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR3_ADDHLD_Pos         (4U)\n#define FSMC_BTR3_ADDHLD_Msk         (0xFUL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR3_ADDHLD             FSMC_BTR3_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR3_ADDHLD_0           (0x1UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR3_ADDHLD_1           (0x2UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR3_ADDHLD_2           (0x4UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR3_ADDHLD_3           (0x8UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR3_DATAST_Pos         (8U)\n#define FSMC_BTR3_DATAST_Msk         (0xFFUL << FSMC_BTR3_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR3_DATAST             FSMC_BTR3_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR3_DATAST_0           (0x01UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR3_DATAST_1           (0x02UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR3_DATAST_2           (0x04UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR3_DATAST_3           (0x08UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR3_DATAST_4           (0x10UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR3_DATAST_5           (0x20UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR3_DATAST_6           (0x40UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR3_DATAST_7           (0x80UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR3_BUSTURN_Pos        (16U)\n#define FSMC_BTR3_BUSTURN_Msk        (0xFUL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR3_BUSTURN            FSMC_BTR3_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR3_BUSTURN_0          (0x1UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR3_BUSTURN_1          (0x2UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR3_BUSTURN_2          (0x4UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR3_BUSTURN_3          (0x8UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR3_CLKDIV_Pos         (20U)\n#define FSMC_BTR3_CLKDIV_Msk         (0xFUL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR3_CLKDIV             FSMC_BTR3_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR3_CLKDIV_0           (0x1UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR3_CLKDIV_1           (0x2UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR3_CLKDIV_2           (0x4UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR3_CLKDIV_3           (0x8UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR3_DATLAT_Pos         (24U)\n#define FSMC_BTR3_DATLAT_Msk         (0xFUL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR3_DATLAT             FSMC_BTR3_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR3_DATLAT_0           (0x1UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR3_DATLAT_1           (0x2UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR3_DATLAT_2           (0x4UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR3_DATLAT_3           (0x8UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR3_ACCMOD_Pos         (28U)\n#define FSMC_BTR3_ACCMOD_Msk         (0x3UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR3_ACCMOD             FSMC_BTR3_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR3_ACCMOD_0           (0x1UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR3_ACCMOD_1           (0x2UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BTR4 register  *******************/\n#define FSMC_BTR4_ADDSET_Pos         (0U)\n#define FSMC_BTR4_ADDSET_Msk         (0xFUL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR4_ADDSET             FSMC_BTR4_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR4_ADDSET_0           (0x1UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR4_ADDSET_1           (0x2UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR4_ADDSET_2           (0x4UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR4_ADDSET_3           (0x8UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR4_ADDHLD_Pos         (4U)\n#define FSMC_BTR4_ADDHLD_Msk         (0xFUL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR4_ADDHLD             FSMC_BTR4_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR4_ADDHLD_0           (0x1UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR4_ADDHLD_1           (0x2UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR4_ADDHLD_2           (0x4UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR4_ADDHLD_3           (0x8UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR4_DATAST_Pos         (8U)\n#define FSMC_BTR4_DATAST_Msk         (0xFFUL << FSMC_BTR4_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR4_DATAST             FSMC_BTR4_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR4_DATAST_0           (0x01UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR4_DATAST_1           (0x02UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR4_DATAST_2           (0x04UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR4_DATAST_3           (0x08UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR4_DATAST_4           (0x10UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR4_DATAST_5           (0x20UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR4_DATAST_6           (0x40UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR4_DATAST_7           (0x80UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR4_BUSTURN_Pos        (16U)\n#define FSMC_BTR4_BUSTURN_Msk        (0xFUL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR4_BUSTURN            FSMC_BTR4_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR4_BUSTURN_0          (0x1UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR4_BUSTURN_1          (0x2UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR4_BUSTURN_2          (0x4UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR4_BUSTURN_3          (0x8UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR4_CLKDIV_Pos         (20U)\n#define FSMC_BTR4_CLKDIV_Msk         (0xFUL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR4_CLKDIV             FSMC_BTR4_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR4_CLKDIV_0           (0x1UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR4_CLKDIV_1           (0x2UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR4_CLKDIV_2           (0x4UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR4_CLKDIV_3           (0x8UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR4_DATLAT_Pos         (24U)\n#define FSMC_BTR4_DATLAT_Msk         (0xFUL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR4_DATLAT             FSMC_BTR4_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR4_DATLAT_0           (0x1UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR4_DATLAT_1           (0x2UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR4_DATLAT_2           (0x4UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR4_DATLAT_3           (0x8UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR4_ACCMOD_Pos         (28U)\n#define FSMC_BTR4_ACCMOD_Msk         (0x3UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR4_ACCMOD             FSMC_BTR4_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR4_ACCMOD_0           (0x1UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR4_ACCMOD_1           (0x2UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR1 register  ******************/\n#define FSMC_BWTR1_ADDSET_Pos        (0U)\n#define FSMC_BWTR1_ADDSET_Msk        (0xFUL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR1_ADDSET            FSMC_BWTR1_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR1_ADDSET_0          (0x1UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR1_ADDSET_1          (0x2UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR1_ADDSET_2          (0x4UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR1_ADDSET_3          (0x8UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR1_ADDHLD_Pos        (4U)\n#define FSMC_BWTR1_ADDHLD_Msk        (0xFUL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR1_ADDHLD            FSMC_BWTR1_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR1_ADDHLD_0          (0x1UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR1_ADDHLD_1          (0x2UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR1_ADDHLD_2          (0x4UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR1_ADDHLD_3          (0x8UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR1_DATAST_Pos        (8U)\n#define FSMC_BWTR1_DATAST_Msk        (0xFFUL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR1_DATAST            FSMC_BWTR1_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR1_DATAST_0          (0x01UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR1_DATAST_1          (0x02UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR1_DATAST_2          (0x04UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR1_DATAST_3          (0x08UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR1_DATAST_4          (0x10UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR1_DATAST_5          (0x20UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR1_DATAST_6          (0x40UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR1_DATAST_7          (0x80UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR1_BUSTURN_Pos       (16U)\n#define FSMC_BWTR1_BUSTURN_Msk       (0xFUL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR1_BUSTURN           FSMC_BWTR1_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR1_BUSTURN_0         (0x1UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR1_BUSTURN_1         (0x2UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR1_BUSTURN_2         (0x4UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR1_BUSTURN_3         (0x8UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR1_ACCMOD_Pos        (28U)\n#define FSMC_BWTR1_ACCMOD_Msk        (0x3UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR1_ACCMOD            FSMC_BWTR1_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR1_ACCMOD_0          (0x1UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR1_ACCMOD_1          (0x2UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR2 register  ******************/\n#define FSMC_BWTR2_ADDSET_Pos        (0U)\n#define FSMC_BWTR2_ADDSET_Msk        (0xFUL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR2_ADDSET            FSMC_BWTR2_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR2_ADDSET_0          (0x1UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR2_ADDSET_1          (0x2UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR2_ADDSET_2          (0x4UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR2_ADDSET_3          (0x8UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR2_ADDHLD_Pos        (4U)\n#define FSMC_BWTR2_ADDHLD_Msk        (0xFUL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR2_ADDHLD            FSMC_BWTR2_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR2_ADDHLD_0          (0x1UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR2_ADDHLD_1          (0x2UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR2_ADDHLD_2          (0x4UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR2_ADDHLD_3          (0x8UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR2_DATAST_Pos        (8U)\n#define FSMC_BWTR2_DATAST_Msk        (0xFFUL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR2_DATAST            FSMC_BWTR2_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR2_DATAST_0          (0x01UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR2_DATAST_1          (0x02UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR2_DATAST_2          (0x04UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR2_DATAST_3          (0x08UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR2_DATAST_4          (0x10UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR2_DATAST_5          (0x20UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR2_DATAST_6          (0x40UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR2_DATAST_7          (0x80UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR2_BUSTURN_Pos       (16U)\n#define FSMC_BWTR2_BUSTURN_Msk       (0xFUL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR2_BUSTURN           FSMC_BWTR2_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR2_BUSTURN_0         (0x1UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR2_BUSTURN_1         (0x2UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR2_BUSTURN_2         (0x4UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR2_BUSTURN_3         (0x8UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR2_ACCMOD_Pos        (28U)\n#define FSMC_BWTR2_ACCMOD_Msk        (0x3UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR2_ACCMOD            FSMC_BWTR2_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR2_ACCMOD_0          (0x1UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR2_ACCMOD_1          (0x2UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR3 register  ******************/\n#define FSMC_BWTR3_ADDSET_Pos        (0U)\n#define FSMC_BWTR3_ADDSET_Msk        (0xFUL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR3_ADDSET            FSMC_BWTR3_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR3_ADDSET_0          (0x1UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR3_ADDSET_1          (0x2UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR3_ADDSET_2          (0x4UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR3_ADDSET_3          (0x8UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR3_ADDHLD_Pos        (4U)\n#define FSMC_BWTR3_ADDHLD_Msk        (0xFUL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR3_ADDHLD            FSMC_BWTR3_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR3_ADDHLD_0          (0x1UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR3_ADDHLD_1          (0x2UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR3_ADDHLD_2          (0x4UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR3_ADDHLD_3          (0x8UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR3_DATAST_Pos        (8U)\n#define FSMC_BWTR3_DATAST_Msk        (0xFFUL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR3_DATAST            FSMC_BWTR3_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR3_DATAST_0          (0x01UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR3_DATAST_1          (0x02UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR3_DATAST_2          (0x04UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR3_DATAST_3          (0x08UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR3_DATAST_4          (0x10UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR3_DATAST_5          (0x20UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR3_DATAST_6          (0x40UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR3_DATAST_7          (0x80UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR3_BUSTURN_Pos       (16U)\n#define FSMC_BWTR3_BUSTURN_Msk       (0xFUL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR3_BUSTURN           FSMC_BWTR3_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR3_BUSTURN_0         (0x1UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR3_BUSTURN_1         (0x2UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR3_BUSTURN_2         (0x4UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR3_BUSTURN_3         (0x8UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR3_ACCMOD_Pos        (28U)\n#define FSMC_BWTR3_ACCMOD_Msk        (0x3UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR3_ACCMOD            FSMC_BWTR3_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR3_ACCMOD_0          (0x1UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR3_ACCMOD_1          (0x2UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR4 register  ******************/\n#define FSMC_BWTR4_ADDSET_Pos        (0U)\n#define FSMC_BWTR4_ADDSET_Msk        (0xFUL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR4_ADDSET            FSMC_BWTR4_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR4_ADDSET_0          (0x1UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR4_ADDSET_1          (0x2UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR4_ADDSET_2          (0x4UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR4_ADDSET_3          (0x8UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR4_ADDHLD_Pos        (4U)\n#define FSMC_BWTR4_ADDHLD_Msk        (0xFUL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR4_ADDHLD            FSMC_BWTR4_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR4_ADDHLD_0          (0x1UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR4_ADDHLD_1          (0x2UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR4_ADDHLD_2          (0x4UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR4_ADDHLD_3          (0x8UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR4_DATAST_Pos        (8U)\n#define FSMC_BWTR4_DATAST_Msk        (0xFFUL << FSMC_BWTR4_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR4_DATAST            FSMC_BWTR4_DATAST_Msk                     /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FSMC_BWTR4_DATAST_0          0x00000100U                               /*!<Bit 0 */\n#define FSMC_BWTR4_DATAST_1          0x00000200U                               /*!<Bit 1 */\n#define FSMC_BWTR4_DATAST_2          0x00000400U                               /*!<Bit 2 */\n#define FSMC_BWTR4_DATAST_3          0x00000800U                               /*!<Bit 3 */\n#define FSMC_BWTR4_DATAST_4          0x00001000U                               /*!<Bit 4 */\n#define FSMC_BWTR4_DATAST_5          0x00002000U                               /*!<Bit 5 */\n#define FSMC_BWTR4_DATAST_6          0x00004000U                               /*!<Bit 6 */\n#define FSMC_BWTR4_DATAST_7          0x00008000U                               /*!<Bit 7 */\n\n#define FSMC_BWTR4_BUSTURN_Pos       (16U)\n#define FSMC_BWTR4_BUSTURN_Msk       (0xFUL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR4_BUSTURN           FSMC_BWTR4_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR4_BUSTURN_0         (0x1UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR4_BUSTURN_1         (0x2UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR4_BUSTURN_2         (0x4UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR4_BUSTURN_3         (0x8UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR4_ACCMOD_Pos        (28U)\n#define FSMC_BWTR4_ACCMOD_Msk        (0x3UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR4_ACCMOD            FSMC_BWTR4_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR4_ACCMOD_0          (0x1UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR4_ACCMOD_1          (0x2UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            General Purpose I/O                             */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bits definition for GPIO_MODER register  *****************/\n#define GPIO_MODER_MODER0_Pos            (0U)\n#define GPIO_MODER_MODER0_Msk            (0x3UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */\n#define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk\n#define GPIO_MODER_MODER0_0              (0x1UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */\n#define GPIO_MODER_MODER0_1              (0x2UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */\n#define GPIO_MODER_MODER1_Pos            (2U)\n#define GPIO_MODER_MODER1_Msk            (0x3UL << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */\n#define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk\n#define GPIO_MODER_MODER1_0              (0x1UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */\n#define GPIO_MODER_MODER1_1              (0x2UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */\n#define GPIO_MODER_MODER2_Pos            (4U)\n#define GPIO_MODER_MODER2_Msk            (0x3UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */\n#define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk\n#define GPIO_MODER_MODER2_0              (0x1UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */\n#define GPIO_MODER_MODER2_1              (0x2UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */\n#define GPIO_MODER_MODER3_Pos            (6U)\n#define GPIO_MODER_MODER3_Msk            (0x3UL << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */\n#define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk\n#define GPIO_MODER_MODER3_0              (0x1UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */\n#define GPIO_MODER_MODER3_1              (0x2UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */\n#define GPIO_MODER_MODER4_Pos            (8U)\n#define GPIO_MODER_MODER4_Msk            (0x3UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */\n#define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk\n#define GPIO_MODER_MODER4_0              (0x1UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */\n#define GPIO_MODER_MODER4_1              (0x2UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */\n#define GPIO_MODER_MODER5_Pos            (10U)\n#define GPIO_MODER_MODER5_Msk            (0x3UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */\n#define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk\n#define GPIO_MODER_MODER5_0              (0x1UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */\n#define GPIO_MODER_MODER5_1              (0x2UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */\n#define GPIO_MODER_MODER6_Pos            (12U)\n#define GPIO_MODER_MODER6_Msk            (0x3UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */\n#define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk\n#define GPIO_MODER_MODER6_0              (0x1UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */\n#define GPIO_MODER_MODER6_1              (0x2UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */\n#define GPIO_MODER_MODER7_Pos            (14U)\n#define GPIO_MODER_MODER7_Msk            (0x3UL << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */\n#define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk\n#define GPIO_MODER_MODER7_0              (0x1UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */\n#define GPIO_MODER_MODER7_1              (0x2UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */\n#define GPIO_MODER_MODER8_Pos            (16U)\n#define GPIO_MODER_MODER8_Msk            (0x3UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */\n#define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk\n#define GPIO_MODER_MODER8_0              (0x1UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */\n#define GPIO_MODER_MODER8_1              (0x2UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */\n#define GPIO_MODER_MODER9_Pos            (18U)\n#define GPIO_MODER_MODER9_Msk            (0x3UL << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */\n#define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk\n#define GPIO_MODER_MODER9_0              (0x1UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */\n#define GPIO_MODER_MODER9_1              (0x2UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */\n#define GPIO_MODER_MODER10_Pos           (20U)\n#define GPIO_MODER_MODER10_Msk           (0x3UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */\n#define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk\n#define GPIO_MODER_MODER10_0             (0x1UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */\n#define GPIO_MODER_MODER10_1             (0x2UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */\n#define GPIO_MODER_MODER11_Pos           (22U)\n#define GPIO_MODER_MODER11_Msk           (0x3UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */\n#define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk\n#define GPIO_MODER_MODER11_0             (0x1UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */\n#define GPIO_MODER_MODER11_1             (0x2UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */\n#define GPIO_MODER_MODER12_Pos           (24U)\n#define GPIO_MODER_MODER12_Msk           (0x3UL << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */\n#define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk\n#define GPIO_MODER_MODER12_0             (0x1UL << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */\n#define GPIO_MODER_MODER12_1             (0x2UL << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */\n#define GPIO_MODER_MODER13_Pos           (26U)\n#define GPIO_MODER_MODER13_Msk           (0x3UL << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */\n#define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk\n#define GPIO_MODER_MODER13_0             (0x1UL << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */\n#define GPIO_MODER_MODER13_1             (0x2UL << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */\n#define GPIO_MODER_MODER14_Pos           (28U)\n#define GPIO_MODER_MODER14_Msk           (0x3UL << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */\n#define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk\n#define GPIO_MODER_MODER14_0             (0x1UL << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */\n#define GPIO_MODER_MODER14_1             (0x2UL << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */\n#define GPIO_MODER_MODER15_Pos           (30U)\n#define GPIO_MODER_MODER15_Msk           (0x3UL << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */\n#define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk\n#define GPIO_MODER_MODER15_0             (0x1UL << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */\n#define GPIO_MODER_MODER15_1             (0x2UL << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_MODER_MODE0_Pos             GPIO_MODER_MODER0_Pos\n#define GPIO_MODER_MODE0_Msk             GPIO_MODER_MODER0_Msk\n#define GPIO_MODER_MODE0                 GPIO_MODER_MODER0\n#define GPIO_MODER_MODE0_0               GPIO_MODER_MODER0_0\n#define GPIO_MODER_MODE0_1               GPIO_MODER_MODER0_1\n#define GPIO_MODER_MODE1_Pos             GPIO_MODER_MODER1_Pos\n#define GPIO_MODER_MODE1_Msk             GPIO_MODER_MODER1_Msk\n#define GPIO_MODER_MODE1                 GPIO_MODER_MODER1\n#define GPIO_MODER_MODE1_0               GPIO_MODER_MODER1_0\n#define GPIO_MODER_MODE1_1               GPIO_MODER_MODER1_1\n#define GPIO_MODER_MODE2_Pos             GPIO_MODER_MODER2_PoS\n#define GPIO_MODER_MODE2_Msk             GPIO_MODER_MODER2_Msk\n#define GPIO_MODER_MODE2                 GPIO_MODER_MODER2\n#define GPIO_MODER_MODE2_0               GPIO_MODER_MODER2_0\n#define GPIO_MODER_MODE2_1               GPIO_MODER_MODER2_1\n#define GPIO_MODER_MODE3_Pos             GPIO_MODER_MODER3_Pos\n#define GPIO_MODER_MODE3_Msk             GPIO_MODER_MODER3_Msk\n#define GPIO_MODER_MODE3                 GPIO_MODER_MODER3\n#define GPIO_MODER_MODE3_0               GPIO_MODER_MODER3_0\n#define GPIO_MODER_MODE3_1               GPIO_MODER_MODER3_1\n#define GPIO_MODER_MODE4_Pos             GPIO_MODER_MODER4_Pos\n#define GPIO_MODER_MODE4_Msk             GPIO_MODER_MODER4_Msk\n#define GPIO_MODER_MODE4                 GPIO_MODER_MODER4\n#define GPIO_MODER_MODE4_0               GPIO_MODER_MODER4_0\n#define GPIO_MODER_MODE4_1               GPIO_MODER_MODER4_1\n#define GPIO_MODER_MODE5_Pos             GPIO_MODER_MODER5_Pos\n#define GPIO_MODER_MODE5_Msk             GPIO_MODER_MODER5_Msk\n#define GPIO_MODER_MODE5                 GPIO_MODER_MODER5\n#define GPIO_MODER_MODE5_0               GPIO_MODER_MODER5_0\n#define GPIO_MODER_MODE5_1               GPIO_MODER_MODER5_1\n#define GPIO_MODER_MODE6_Pos             GPIO_MODER_MODER6_Pos\n#define GPIO_MODER_MODE6_Msk             GPIO_MODER_MODER6_Msk\n#define GPIO_MODER_MODE6                 GPIO_MODER_MODER6\n#define GPIO_MODER_MODE6_0               GPIO_MODER_MODER6_0\n#define GPIO_MODER_MODE6_1               GPIO_MODER_MODER6_1\n#define GPIO_MODER_MODE7_Pos             GPIO_MODER_MODER7_Pos\n#define GPIO_MODER_MODE7_Msk             GPIO_MODER_MODER7_Msk\n#define GPIO_MODER_MODE7                 GPIO_MODER_MODER7\n#define GPIO_MODER_MODE7_0               GPIO_MODER_MODER7_0\n#define GPIO_MODER_MODE7_1               GPIO_MODER_MODER7_1\n#define GPIO_MODER_MODE8_Pos             GPIO_MODER_MODER8_Pos\n#define GPIO_MODER_MODE8_Msk             GPIO_MODER_MODER2_Msk\n#define GPIO_MODER_MODE8                 GPIO_MODER_MODER8\n#define GPIO_MODER_MODE8_0               GPIO_MODER_MODER8_0\n#define GPIO_MODER_MODE8_1               GPIO_MODER_MODER8_1\n#define GPIO_MODER_MODE9_Pos             GPIO_MODER_MODER9_Pos\n#define GPIO_MODER_MODE9_Msk             GPIO_MODER_MODER9_Msk\n#define GPIO_MODER_MODE9                 GPIO_MODER_MODER9\n#define GPIO_MODER_MODE9_0               GPIO_MODER_MODER9_0\n#define GPIO_MODER_MODE9_1               GPIO_MODER_MODER9_1\n#define GPIO_MODER_MODE10_Pos            GPIO_MODER_MODER10_Pos\n#define GPIO_MODER_MODE10_Msk            GPIO_MODER_MODER10_Msk\n#define GPIO_MODER_MODE10                GPIO_MODER_MODER10\n#define GPIO_MODER_MODE10_0              GPIO_MODER_MODER10_0\n#define GPIO_MODER_MODE10_1              GPIO_MODER_MODER10_1\n#define GPIO_MODER_MODE11_Pos            GPIO_MODER_MODER11_Pos\n#define GPIO_MODER_MODE11_Msk            GPIO_MODER_MODER11_Msk\n#define GPIO_MODER_MODE11                GPIO_MODER_MODER11\n#define GPIO_MODER_MODE11_0              GPIO_MODER_MODER11_0\n#define GPIO_MODER_MODE11_1              GPIO_MODER_MODER11_1\n#define GPIO_MODER_MODE12_Pos            GPIO_MODER_MODER12_Pos\n#define GPIO_MODER_MODE12_Msk            GPIO_MODER_MODER12_Msk\n#define GPIO_MODER_MODE12                GPIO_MODER_MODER12\n#define GPIO_MODER_MODE12_0              GPIO_MODER_MODER12_0\n#define GPIO_MODER_MODE12_1              GPIO_MODER_MODER12_1\n#define GPIO_MODER_MODE13_Pos            GPIO_MODER_MODER13_Pos\n#define GPIO_MODER_MODE13_Msk            GPIO_MODER_MODER13_Msk\n#define GPIO_MODER_MODE13                GPIO_MODER_MODER13\n#define GPIO_MODER_MODE13_0              GPIO_MODER_MODER13_0\n#define GPIO_MODER_MODE13_1              GPIO_MODER_MODER13_1\n#define GPIO_MODER_MODE14_Pos            GPIO_MODER_MODER14_Pos\n#define GPIO_MODER_MODE14_Msk            GPIO_MODER_MODER14_Msk\n#define GPIO_MODER_MODE14                GPIO_MODER_MODER14\n#define GPIO_MODER_MODE14_0              GPIO_MODER_MODER14_0\n#define GPIO_MODER_MODE14_1              GPIO_MODER_MODER14_1\n#define GPIO_MODER_MODE15_Pos            GPIO_MODER_MODER15_Pos\n#define GPIO_MODER_MODE15_Msk            GPIO_MODER_MODER15_Msk\n#define GPIO_MODER_MODE15                GPIO_MODER_MODER15\n#define GPIO_MODER_MODE15_0              GPIO_MODER_MODER15_0\n#define GPIO_MODER_MODE15_1              GPIO_MODER_MODER15_1\n\n/******************  Bits definition for GPIO_OTYPER register  ****************/\n#define GPIO_OTYPER_OT0_Pos              (0U)\n#define GPIO_OTYPER_OT0_Msk              (0x1UL << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */\n#define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk\n#define GPIO_OTYPER_OT1_Pos              (1U)\n#define GPIO_OTYPER_OT1_Msk              (0x1UL << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */\n#define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk\n#define GPIO_OTYPER_OT2_Pos              (2U)\n#define GPIO_OTYPER_OT2_Msk              (0x1UL << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */\n#define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk\n#define GPIO_OTYPER_OT3_Pos              (3U)\n#define GPIO_OTYPER_OT3_Msk              (0x1UL << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */\n#define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk\n#define GPIO_OTYPER_OT4_Pos              (4U)\n#define GPIO_OTYPER_OT4_Msk              (0x1UL << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */\n#define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk\n#define GPIO_OTYPER_OT5_Pos              (5U)\n#define GPIO_OTYPER_OT5_Msk              (0x1UL << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */\n#define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk\n#define GPIO_OTYPER_OT6_Pos              (6U)\n#define GPIO_OTYPER_OT6_Msk              (0x1UL << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */\n#define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk\n#define GPIO_OTYPER_OT7_Pos              (7U)\n#define GPIO_OTYPER_OT7_Msk              (0x1UL << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */\n#define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk\n#define GPIO_OTYPER_OT8_Pos              (8U)\n#define GPIO_OTYPER_OT8_Msk              (0x1UL << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */\n#define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk\n#define GPIO_OTYPER_OT9_Pos              (9U)\n#define GPIO_OTYPER_OT9_Msk              (0x1UL << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */\n#define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk\n#define GPIO_OTYPER_OT10_Pos             (10U)\n#define GPIO_OTYPER_OT10_Msk             (0x1UL << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */\n#define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk\n#define GPIO_OTYPER_OT11_Pos             (11U)\n#define GPIO_OTYPER_OT11_Msk             (0x1UL << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */\n#define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk\n#define GPIO_OTYPER_OT12_Pos             (12U)\n#define GPIO_OTYPER_OT12_Msk             (0x1UL << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */\n#define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk\n#define GPIO_OTYPER_OT13_Pos             (13U)\n#define GPIO_OTYPER_OT13_Msk             (0x1UL << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */\n#define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk\n#define GPIO_OTYPER_OT14_Pos             (14U)\n#define GPIO_OTYPER_OT14_Msk             (0x1UL << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */\n#define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk\n#define GPIO_OTYPER_OT15_Pos             (15U)\n#define GPIO_OTYPER_OT15_Msk             (0x1UL << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */\n#define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk\n\n/* Legacy defines */\n#define GPIO_OTYPER_OT_0                 GPIO_OTYPER_OT0\n#define GPIO_OTYPER_OT_1                 GPIO_OTYPER_OT1\n#define GPIO_OTYPER_OT_2                 GPIO_OTYPER_OT2\n#define GPIO_OTYPER_OT_3                 GPIO_OTYPER_OT3\n#define GPIO_OTYPER_OT_4                 GPIO_OTYPER_OT4\n#define GPIO_OTYPER_OT_5                 GPIO_OTYPER_OT5\n#define GPIO_OTYPER_OT_6                 GPIO_OTYPER_OT6\n#define GPIO_OTYPER_OT_7                 GPIO_OTYPER_OT7\n#define GPIO_OTYPER_OT_8                 GPIO_OTYPER_OT8\n#define GPIO_OTYPER_OT_9                 GPIO_OTYPER_OT9\n#define GPIO_OTYPER_OT_10                GPIO_OTYPER_OT10\n#define GPIO_OTYPER_OT_11                GPIO_OTYPER_OT11\n#define GPIO_OTYPER_OT_12                GPIO_OTYPER_OT12\n#define GPIO_OTYPER_OT_13                GPIO_OTYPER_OT13\n#define GPIO_OTYPER_OT_14                GPIO_OTYPER_OT14\n#define GPIO_OTYPER_OT_15                GPIO_OTYPER_OT15\n\n/******************  Bits definition for GPIO_OSPEEDR register  ***************/\n#define GPIO_OSPEEDR_OSPEED0_Pos         (0U)\n#define GPIO_OSPEEDR_OSPEED0_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000003 */\n#define GPIO_OSPEEDR_OSPEED0             GPIO_OSPEEDR_OSPEED0_Msk\n#define GPIO_OSPEEDR_OSPEED0_0           (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000001 */\n#define GPIO_OSPEEDR_OSPEED0_1           (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000002 */\n#define GPIO_OSPEEDR_OSPEED1_Pos         (2U)\n#define GPIO_OSPEEDR_OSPEED1_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x0000000C */\n#define GPIO_OSPEEDR_OSPEED1             GPIO_OSPEEDR_OSPEED1_Msk\n#define GPIO_OSPEEDR_OSPEED1_0           (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000004 */\n#define GPIO_OSPEEDR_OSPEED1_1           (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000008 */\n#define GPIO_OSPEEDR_OSPEED2_Pos         (4U)\n#define GPIO_OSPEEDR_OSPEED2_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000030 */\n#define GPIO_OSPEEDR_OSPEED2             GPIO_OSPEEDR_OSPEED2_Msk\n#define GPIO_OSPEEDR_OSPEED2_0           (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000010 */\n#define GPIO_OSPEEDR_OSPEED2_1           (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000020 */\n#define GPIO_OSPEEDR_OSPEED3_Pos         (6U)\n#define GPIO_OSPEEDR_OSPEED3_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x000000C0 */\n#define GPIO_OSPEEDR_OSPEED3             GPIO_OSPEEDR_OSPEED3_Msk\n#define GPIO_OSPEEDR_OSPEED3_0           (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000040 */\n#define GPIO_OSPEEDR_OSPEED3_1           (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000080 */\n#define GPIO_OSPEEDR_OSPEED4_Pos         (8U)\n#define GPIO_OSPEEDR_OSPEED4_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000300 */\n#define GPIO_OSPEEDR_OSPEED4             GPIO_OSPEEDR_OSPEED4_Msk\n#define GPIO_OSPEEDR_OSPEED4_0           (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000100 */\n#define GPIO_OSPEEDR_OSPEED4_1           (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000200 */\n#define GPIO_OSPEEDR_OSPEED5_Pos         (10U)\n#define GPIO_OSPEEDR_OSPEED5_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000C00 */\n#define GPIO_OSPEEDR_OSPEED5             GPIO_OSPEEDR_OSPEED5_Msk\n#define GPIO_OSPEEDR_OSPEED5_0           (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000400 */\n#define GPIO_OSPEEDR_OSPEED5_1           (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000800 */\n#define GPIO_OSPEEDR_OSPEED6_Pos         (12U)\n#define GPIO_OSPEEDR_OSPEED6_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00003000 */\n#define GPIO_OSPEEDR_OSPEED6             GPIO_OSPEEDR_OSPEED6_Msk\n#define GPIO_OSPEEDR_OSPEED6_0           (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00001000 */\n#define GPIO_OSPEEDR_OSPEED6_1           (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00002000 */\n#define GPIO_OSPEEDR_OSPEED7_Pos         (14U)\n#define GPIO_OSPEEDR_OSPEED7_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x0000C000 */\n#define GPIO_OSPEEDR_OSPEED7             GPIO_OSPEEDR_OSPEED7_Msk\n#define GPIO_OSPEEDR_OSPEED7_0           (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00004000 */\n#define GPIO_OSPEEDR_OSPEED7_1           (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00008000 */\n#define GPIO_OSPEEDR_OSPEED8_Pos         (16U)\n#define GPIO_OSPEEDR_OSPEED8_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00030000 */\n#define GPIO_OSPEEDR_OSPEED8             GPIO_OSPEEDR_OSPEED8_Msk\n#define GPIO_OSPEEDR_OSPEED8_0           (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00010000 */\n#define GPIO_OSPEEDR_OSPEED8_1           (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00020000 */\n#define GPIO_OSPEEDR_OSPEED9_Pos         (18U)\n#define GPIO_OSPEEDR_OSPEED9_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x000C0000 */\n#define GPIO_OSPEEDR_OSPEED9             GPIO_OSPEEDR_OSPEED9_Msk\n#define GPIO_OSPEEDR_OSPEED9_0           (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00040000 */\n#define GPIO_OSPEEDR_OSPEED9_1           (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00080000 */\n#define GPIO_OSPEEDR_OSPEED10_Pos        (20U)\n#define GPIO_OSPEEDR_OSPEED10_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00300000 */\n#define GPIO_OSPEEDR_OSPEED10            GPIO_OSPEEDR_OSPEED10_Msk\n#define GPIO_OSPEEDR_OSPEED10_0          (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00100000 */\n#define GPIO_OSPEEDR_OSPEED10_1          (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00200000 */\n#define GPIO_OSPEEDR_OSPEED11_Pos        (22U)\n#define GPIO_OSPEEDR_OSPEED11_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00C00000 */\n#define GPIO_OSPEEDR_OSPEED11            GPIO_OSPEEDR_OSPEED11_Msk\n#define GPIO_OSPEEDR_OSPEED11_0          (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00400000 */\n#define GPIO_OSPEEDR_OSPEED11_1          (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00800000 */\n#define GPIO_OSPEEDR_OSPEED12_Pos        (24U)\n#define GPIO_OSPEEDR_OSPEED12_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x03000000 */\n#define GPIO_OSPEEDR_OSPEED12            GPIO_OSPEEDR_OSPEED12_Msk\n#define GPIO_OSPEEDR_OSPEED12_0          (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x01000000 */\n#define GPIO_OSPEEDR_OSPEED12_1          (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x02000000 */\n#define GPIO_OSPEEDR_OSPEED13_Pos        (26U)\n#define GPIO_OSPEEDR_OSPEED13_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x0C000000 */\n#define GPIO_OSPEEDR_OSPEED13            GPIO_OSPEEDR_OSPEED13_Msk\n#define GPIO_OSPEEDR_OSPEED13_0          (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x04000000 */\n#define GPIO_OSPEEDR_OSPEED13_1          (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x08000000 */\n#define GPIO_OSPEEDR_OSPEED14_Pos        (28U)\n#define GPIO_OSPEEDR_OSPEED14_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x30000000 */\n#define GPIO_OSPEEDR_OSPEED14            GPIO_OSPEEDR_OSPEED14_Msk\n#define GPIO_OSPEEDR_OSPEED14_0          (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x10000000 */\n#define GPIO_OSPEEDR_OSPEED14_1          (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x20000000 */\n#define GPIO_OSPEEDR_OSPEED15_Pos        (30U)\n#define GPIO_OSPEEDR_OSPEED15_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0xC0000000 */\n#define GPIO_OSPEEDR_OSPEED15            GPIO_OSPEEDR_OSPEED15_Msk\n#define GPIO_OSPEEDR_OSPEED15_0          (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x40000000 */\n#define GPIO_OSPEEDR_OSPEED15_1          (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDR_OSPEED0\n#define GPIO_OSPEEDER_OSPEEDR0_0         GPIO_OSPEEDR_OSPEED0_0\n#define GPIO_OSPEEDER_OSPEEDR0_1         GPIO_OSPEEDR_OSPEED0_1\n#define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDR_OSPEED1\n#define GPIO_OSPEEDER_OSPEEDR1_0         GPIO_OSPEEDR_OSPEED1_0\n#define GPIO_OSPEEDER_OSPEEDR1_1         GPIO_OSPEEDR_OSPEED1_1\n#define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDR_OSPEED2\n#define GPIO_OSPEEDER_OSPEEDR2_0         GPIO_OSPEEDR_OSPEED2_0\n#define GPIO_OSPEEDER_OSPEEDR2_1         GPIO_OSPEEDR_OSPEED2_1\n#define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDR_OSPEED3\n#define GPIO_OSPEEDER_OSPEEDR3_0         GPIO_OSPEEDR_OSPEED3_0\n#define GPIO_OSPEEDER_OSPEEDR3_1         GPIO_OSPEEDR_OSPEED3_1\n#define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDR_OSPEED4\n#define GPIO_OSPEEDER_OSPEEDR4_0         GPIO_OSPEEDR_OSPEED4_0\n#define GPIO_OSPEEDER_OSPEEDR4_1         GPIO_OSPEEDR_OSPEED4_1\n#define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDR_OSPEED5\n#define GPIO_OSPEEDER_OSPEEDR5_0         GPIO_OSPEEDR_OSPEED5_0\n#define GPIO_OSPEEDER_OSPEEDR5_1         GPIO_OSPEEDR_OSPEED5_1\n#define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDR_OSPEED6\n#define GPIO_OSPEEDER_OSPEEDR6_0         GPIO_OSPEEDR_OSPEED6_0\n#define GPIO_OSPEEDER_OSPEEDR6_1         GPIO_OSPEEDR_OSPEED6_1\n#define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDR_OSPEED7\n#define GPIO_OSPEEDER_OSPEEDR7_0         GPIO_OSPEEDR_OSPEED7_0\n#define GPIO_OSPEEDER_OSPEEDR7_1         GPIO_OSPEEDR_OSPEED7_1\n#define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDR_OSPEED8\n#define GPIO_OSPEEDER_OSPEEDR8_0         GPIO_OSPEEDR_OSPEED8_0\n#define GPIO_OSPEEDER_OSPEEDR8_1         GPIO_OSPEEDR_OSPEED8_1\n#define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDR_OSPEED9\n#define GPIO_OSPEEDER_OSPEEDR9_0         GPIO_OSPEEDR_OSPEED9_0\n#define GPIO_OSPEEDER_OSPEEDR9_1         GPIO_OSPEEDR_OSPEED9_1\n#define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDR_OSPEED10\n#define GPIO_OSPEEDER_OSPEEDR10_0        GPIO_OSPEEDR_OSPEED10_0\n#define GPIO_OSPEEDER_OSPEEDR10_1        GPIO_OSPEEDR_OSPEED10_1\n#define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDR_OSPEED11\n#define GPIO_OSPEEDER_OSPEEDR11_0        GPIO_OSPEEDR_OSPEED11_0\n#define GPIO_OSPEEDER_OSPEEDR11_1        GPIO_OSPEEDR_OSPEED11_1\n#define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDR_OSPEED12\n#define GPIO_OSPEEDER_OSPEEDR12_0        GPIO_OSPEEDR_OSPEED12_0\n#define GPIO_OSPEEDER_OSPEEDR12_1        GPIO_OSPEEDR_OSPEED12_1\n#define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDR_OSPEED13\n#define GPIO_OSPEEDER_OSPEEDR13_0        GPIO_OSPEEDR_OSPEED13_0\n#define GPIO_OSPEEDER_OSPEEDR13_1        GPIO_OSPEEDR_OSPEED13_1\n#define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDR_OSPEED14\n#define GPIO_OSPEEDER_OSPEEDR14_0        GPIO_OSPEEDR_OSPEED14_0\n#define GPIO_OSPEEDER_OSPEEDR14_1        GPIO_OSPEEDR_OSPEED14_1\n#define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDR_OSPEED15\n#define GPIO_OSPEEDER_OSPEEDR15_0        GPIO_OSPEEDR_OSPEED15_0\n#define GPIO_OSPEEDER_OSPEEDR15_1        GPIO_OSPEEDR_OSPEED15_1\n\n/******************  Bits definition for GPIO_PUPDR register  *****************/\n#define GPIO_PUPDR_PUPD0_Pos             (0U)\n#define GPIO_PUPDR_PUPD0_Msk             (0x3UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000003 */\n#define GPIO_PUPDR_PUPD0                 GPIO_PUPDR_PUPD0_Msk\n#define GPIO_PUPDR_PUPD0_0               (0x1UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000001 */\n#define GPIO_PUPDR_PUPD0_1               (0x2UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000002 */\n#define GPIO_PUPDR_PUPD1_Pos             (2U)\n#define GPIO_PUPDR_PUPD1_Msk             (0x3UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x0000000C */\n#define GPIO_PUPDR_PUPD1                 GPIO_PUPDR_PUPD1_Msk\n#define GPIO_PUPDR_PUPD1_0               (0x1UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000004 */\n#define GPIO_PUPDR_PUPD1_1               (0x2UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000008 */\n#define GPIO_PUPDR_PUPD2_Pos             (4U)\n#define GPIO_PUPDR_PUPD2_Msk             (0x3UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000030 */\n#define GPIO_PUPDR_PUPD2                 GPIO_PUPDR_PUPD2_Msk\n#define GPIO_PUPDR_PUPD2_0               (0x1UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000010 */\n#define GPIO_PUPDR_PUPD2_1               (0x2UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000020 */\n#define GPIO_PUPDR_PUPD3_Pos             (6U)\n#define GPIO_PUPDR_PUPD3_Msk             (0x3UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x000000C0 */\n#define GPIO_PUPDR_PUPD3                 GPIO_PUPDR_PUPD3_Msk\n#define GPIO_PUPDR_PUPD3_0               (0x1UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000040 */\n#define GPIO_PUPDR_PUPD3_1               (0x2UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000080 */\n#define GPIO_PUPDR_PUPD4_Pos             (8U)\n#define GPIO_PUPDR_PUPD4_Msk             (0x3UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000300 */\n#define GPIO_PUPDR_PUPD4                 GPIO_PUPDR_PUPD4_Msk\n#define GPIO_PUPDR_PUPD4_0               (0x1UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000100 */\n#define GPIO_PUPDR_PUPD4_1               (0x2UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000200 */\n#define GPIO_PUPDR_PUPD5_Pos             (10U)\n#define GPIO_PUPDR_PUPD5_Msk             (0x3UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000C00 */\n#define GPIO_PUPDR_PUPD5                 GPIO_PUPDR_PUPD5_Msk\n#define GPIO_PUPDR_PUPD5_0               (0x1UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000400 */\n#define GPIO_PUPDR_PUPD5_1               (0x2UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000800 */\n#define GPIO_PUPDR_PUPD6_Pos             (12U)\n#define GPIO_PUPDR_PUPD6_Msk             (0x3UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00003000 */\n#define GPIO_PUPDR_PUPD6                 GPIO_PUPDR_PUPD6_Msk\n#define GPIO_PUPDR_PUPD6_0               (0x1UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00001000 */\n#define GPIO_PUPDR_PUPD6_1               (0x2UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00002000 */\n#define GPIO_PUPDR_PUPD7_Pos             (14U)\n#define GPIO_PUPDR_PUPD7_Msk             (0x3UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x0000C000 */\n#define GPIO_PUPDR_PUPD7                 GPIO_PUPDR_PUPD7_Msk\n#define GPIO_PUPDR_PUPD7_0               (0x1UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00004000 */\n#define GPIO_PUPDR_PUPD7_1               (0x2UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00008000 */\n#define GPIO_PUPDR_PUPD8_Pos             (16U)\n#define GPIO_PUPDR_PUPD8_Msk             (0x3UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00030000 */\n#define GPIO_PUPDR_PUPD8                 GPIO_PUPDR_PUPD8_Msk\n#define GPIO_PUPDR_PUPD8_0               (0x1UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00010000 */\n#define GPIO_PUPDR_PUPD8_1               (0x2UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00020000 */\n#define GPIO_PUPDR_PUPD9_Pos             (18U)\n#define GPIO_PUPDR_PUPD9_Msk             (0x3UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x000C0000 */\n#define GPIO_PUPDR_PUPD9                 GPIO_PUPDR_PUPD9_Msk\n#define GPIO_PUPDR_PUPD9_0               (0x1UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00040000 */\n#define GPIO_PUPDR_PUPD9_1               (0x2UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00080000 */\n#define GPIO_PUPDR_PUPD10_Pos            (20U)\n#define GPIO_PUPDR_PUPD10_Msk            (0x3UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00300000 */\n#define GPIO_PUPDR_PUPD10                GPIO_PUPDR_PUPD10_Msk\n#define GPIO_PUPDR_PUPD10_0              (0x1UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00100000 */\n#define GPIO_PUPDR_PUPD10_1              (0x2UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00200000 */\n#define GPIO_PUPDR_PUPD11_Pos            (22U)\n#define GPIO_PUPDR_PUPD11_Msk            (0x3UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00C00000 */\n#define GPIO_PUPDR_PUPD11                GPIO_PUPDR_PUPD11_Msk\n#define GPIO_PUPDR_PUPD11_0              (0x1UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00400000 */\n#define GPIO_PUPDR_PUPD11_1              (0x2UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00800000 */\n#define GPIO_PUPDR_PUPD12_Pos            (24U)\n#define GPIO_PUPDR_PUPD12_Msk            (0x3UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x03000000 */\n#define GPIO_PUPDR_PUPD12                GPIO_PUPDR_PUPD12_Msk\n#define GPIO_PUPDR_PUPD12_0              (0x1UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x01000000 */\n#define GPIO_PUPDR_PUPD12_1              (0x2UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x02000000 */\n#define GPIO_PUPDR_PUPD13_Pos            (26U)\n#define GPIO_PUPDR_PUPD13_Msk            (0x3UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x0C000000 */\n#define GPIO_PUPDR_PUPD13                GPIO_PUPDR_PUPD13_Msk\n#define GPIO_PUPDR_PUPD13_0              (0x1UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x04000000 */\n#define GPIO_PUPDR_PUPD13_1              (0x2UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x08000000 */\n#define GPIO_PUPDR_PUPD14_Pos            (28U)\n#define GPIO_PUPDR_PUPD14_Msk            (0x3UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x30000000 */\n#define GPIO_PUPDR_PUPD14                GPIO_PUPDR_PUPD14_Msk\n#define GPIO_PUPDR_PUPD14_0              (0x1UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x10000000 */\n#define GPIO_PUPDR_PUPD14_1              (0x2UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x20000000 */\n#define GPIO_PUPDR_PUPD15_Pos            (30U)\n#define GPIO_PUPDR_PUPD15_Msk            (0x3UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0xC0000000 */\n#define GPIO_PUPDR_PUPD15                GPIO_PUPDR_PUPD15_Msk\n#define GPIO_PUPDR_PUPD15_0              (0x1UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x40000000 */\n#define GPIO_PUPDR_PUPD15_1              (0x2UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPD0\n#define GPIO_PUPDR_PUPDR0_0              GPIO_PUPDR_PUPD0_0\n#define GPIO_PUPDR_PUPDR0_1              GPIO_PUPDR_PUPD0_1\n#define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPD1\n#define GPIO_PUPDR_PUPDR1_0              GPIO_PUPDR_PUPD1_0\n#define GPIO_PUPDR_PUPDR1_1              GPIO_PUPDR_PUPD1_1\n#define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPD2\n#define GPIO_PUPDR_PUPDR2_0              GPIO_PUPDR_PUPD2_0\n#define GPIO_PUPDR_PUPDR2_1              GPIO_PUPDR_PUPD2_1\n#define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPD3\n#define GPIO_PUPDR_PUPDR3_0              GPIO_PUPDR_PUPD3_0\n#define GPIO_PUPDR_PUPDR3_1              GPIO_PUPDR_PUPD3_1\n#define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPD4\n#define GPIO_PUPDR_PUPDR4_0              GPIO_PUPDR_PUPD4_0\n#define GPIO_PUPDR_PUPDR4_1              GPIO_PUPDR_PUPD4_1\n#define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPD5\n#define GPIO_PUPDR_PUPDR5_0              GPIO_PUPDR_PUPD5_0\n#define GPIO_PUPDR_PUPDR5_1              GPIO_PUPDR_PUPD5_1\n#define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPD6\n#define GPIO_PUPDR_PUPDR6_0              GPIO_PUPDR_PUPD6_0\n#define GPIO_PUPDR_PUPDR6_1              GPIO_PUPDR_PUPD6_1\n#define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPD7\n#define GPIO_PUPDR_PUPDR7_0              GPIO_PUPDR_PUPD7_0\n#define GPIO_PUPDR_PUPDR7_1              GPIO_PUPDR_PUPD7_1\n#define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPD8\n#define GPIO_PUPDR_PUPDR8_0              GPIO_PUPDR_PUPD8_0\n#define GPIO_PUPDR_PUPDR8_1              GPIO_PUPDR_PUPD8_1\n#define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPD9\n#define GPIO_PUPDR_PUPDR9_0              GPIO_PUPDR_PUPD9_0\n#define GPIO_PUPDR_PUPDR9_1              GPIO_PUPDR_PUPD9_1\n#define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPD10\n#define GPIO_PUPDR_PUPDR10_0             GPIO_PUPDR_PUPD10_0\n#define GPIO_PUPDR_PUPDR10_1             GPIO_PUPDR_PUPD10_1\n#define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPD11\n#define GPIO_PUPDR_PUPDR11_0             GPIO_PUPDR_PUPD11_0\n#define GPIO_PUPDR_PUPDR11_1             GPIO_PUPDR_PUPD11_1\n#define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPD12\n#define GPIO_PUPDR_PUPDR12_0             GPIO_PUPDR_PUPD12_0\n#define GPIO_PUPDR_PUPDR12_1             GPIO_PUPDR_PUPD12_1\n#define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPD13\n#define GPIO_PUPDR_PUPDR13_0             GPIO_PUPDR_PUPD13_0\n#define GPIO_PUPDR_PUPDR13_1             GPIO_PUPDR_PUPD13_1\n#define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPD14\n#define GPIO_PUPDR_PUPDR14_0             GPIO_PUPDR_PUPD14_0\n#define GPIO_PUPDR_PUPDR14_1             GPIO_PUPDR_PUPD14_1\n#define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPD15\n#define GPIO_PUPDR_PUPDR15_0             GPIO_PUPDR_PUPD15_0\n#define GPIO_PUPDR_PUPDR15_1             GPIO_PUPDR_PUPD15_1\n\n/******************  Bits definition for GPIO_IDR register  *******************/\n#define GPIO_IDR_ID0_Pos                 (0U)\n#define GPIO_IDR_ID0_Msk                 (0x1UL << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */\n#define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk\n#define GPIO_IDR_ID1_Pos                 (1U)\n#define GPIO_IDR_ID1_Msk                 (0x1UL << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */\n#define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk\n#define GPIO_IDR_ID2_Pos                 (2U)\n#define GPIO_IDR_ID2_Msk                 (0x1UL << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */\n#define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk\n#define GPIO_IDR_ID3_Pos                 (3U)\n#define GPIO_IDR_ID3_Msk                 (0x1UL << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */\n#define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk\n#define GPIO_IDR_ID4_Pos                 (4U)\n#define GPIO_IDR_ID4_Msk                 (0x1UL << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */\n#define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk\n#define GPIO_IDR_ID5_Pos                 (5U)\n#define GPIO_IDR_ID5_Msk                 (0x1UL << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */\n#define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk\n#define GPIO_IDR_ID6_Pos                 (6U)\n#define GPIO_IDR_ID6_Msk                 (0x1UL << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */\n#define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk\n#define GPIO_IDR_ID7_Pos                 (7U)\n#define GPIO_IDR_ID7_Msk                 (0x1UL << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */\n#define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk\n#define GPIO_IDR_ID8_Pos                 (8U)\n#define GPIO_IDR_ID8_Msk                 (0x1UL << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */\n#define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk\n#define GPIO_IDR_ID9_Pos                 (9U)\n#define GPIO_IDR_ID9_Msk                 (0x1UL << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */\n#define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk\n#define GPIO_IDR_ID10_Pos                (10U)\n#define GPIO_IDR_ID10_Msk                (0x1UL << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */\n#define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk\n#define GPIO_IDR_ID11_Pos                (11U)\n#define GPIO_IDR_ID11_Msk                (0x1UL << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */\n#define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk\n#define GPIO_IDR_ID12_Pos                (12U)\n#define GPIO_IDR_ID12_Msk                (0x1UL << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */\n#define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk\n#define GPIO_IDR_ID13_Pos                (13U)\n#define GPIO_IDR_ID13_Msk                (0x1UL << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */\n#define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk\n#define GPIO_IDR_ID14_Pos                (14U)\n#define GPIO_IDR_ID14_Msk                (0x1UL << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */\n#define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk\n#define GPIO_IDR_ID15_Pos                (15U)\n#define GPIO_IDR_ID15_Msk                (0x1UL << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */\n#define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk\n\n/* Legacy defines */\n#define GPIO_IDR_IDR_0                   GPIO_IDR_ID0\n#define GPIO_IDR_IDR_1                   GPIO_IDR_ID1\n#define GPIO_IDR_IDR_2                   GPIO_IDR_ID2\n#define GPIO_IDR_IDR_3                   GPIO_IDR_ID3\n#define GPIO_IDR_IDR_4                   GPIO_IDR_ID4\n#define GPIO_IDR_IDR_5                   GPIO_IDR_ID5\n#define GPIO_IDR_IDR_6                   GPIO_IDR_ID6\n#define GPIO_IDR_IDR_7                   GPIO_IDR_ID7\n#define GPIO_IDR_IDR_8                   GPIO_IDR_ID8\n#define GPIO_IDR_IDR_9                   GPIO_IDR_ID9\n#define GPIO_IDR_IDR_10                  GPIO_IDR_ID10\n#define GPIO_IDR_IDR_11                  GPIO_IDR_ID11\n#define GPIO_IDR_IDR_12                  GPIO_IDR_ID12\n#define GPIO_IDR_IDR_13                  GPIO_IDR_ID13\n#define GPIO_IDR_IDR_14                  GPIO_IDR_ID14\n#define GPIO_IDR_IDR_15                  GPIO_IDR_ID15\n\n/******************  Bits definition for GPIO_ODR register  *******************/\n#define GPIO_ODR_OD0_Pos                 (0U)\n#define GPIO_ODR_OD0_Msk                 (0x1UL << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */\n#define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk\n#define GPIO_ODR_OD1_Pos                 (1U)\n#define GPIO_ODR_OD1_Msk                 (0x1UL << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */\n#define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk\n#define GPIO_ODR_OD2_Pos                 (2U)\n#define GPIO_ODR_OD2_Msk                 (0x1UL << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */\n#define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk\n#define GPIO_ODR_OD3_Pos                 (3U)\n#define GPIO_ODR_OD3_Msk                 (0x1UL << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */\n#define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk\n#define GPIO_ODR_OD4_Pos                 (4U)\n#define GPIO_ODR_OD4_Msk                 (0x1UL << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */\n#define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk\n#define GPIO_ODR_OD5_Pos                 (5U)\n#define GPIO_ODR_OD5_Msk                 (0x1UL << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */\n#define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk\n#define GPIO_ODR_OD6_Pos                 (6U)\n#define GPIO_ODR_OD6_Msk                 (0x1UL << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */\n#define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk\n#define GPIO_ODR_OD7_Pos                 (7U)\n#define GPIO_ODR_OD7_Msk                 (0x1UL << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */\n#define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk\n#define GPIO_ODR_OD8_Pos                 (8U)\n#define GPIO_ODR_OD8_Msk                 (0x1UL << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */\n#define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk\n#define GPIO_ODR_OD9_Pos                 (9U)\n#define GPIO_ODR_OD9_Msk                 (0x1UL << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */\n#define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk\n#define GPIO_ODR_OD10_Pos                (10U)\n#define GPIO_ODR_OD10_Msk                (0x1UL << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */\n#define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk\n#define GPIO_ODR_OD11_Pos                (11U)\n#define GPIO_ODR_OD11_Msk                (0x1UL << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */\n#define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk\n#define GPIO_ODR_OD12_Pos                (12U)\n#define GPIO_ODR_OD12_Msk                (0x1UL << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */\n#define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk\n#define GPIO_ODR_OD13_Pos                (13U)\n#define GPIO_ODR_OD13_Msk                (0x1UL << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */\n#define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk\n#define GPIO_ODR_OD14_Pos                (14U)\n#define GPIO_ODR_OD14_Msk                (0x1UL << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */\n#define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk\n#define GPIO_ODR_OD15_Pos                (15U)\n#define GPIO_ODR_OD15_Msk                (0x1UL << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */\n#define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk\n/* Legacy defines */\n#define GPIO_ODR_ODR_0                   GPIO_ODR_OD0\n#define GPIO_ODR_ODR_1                   GPIO_ODR_OD1\n#define GPIO_ODR_ODR_2                   GPIO_ODR_OD2\n#define GPIO_ODR_ODR_3                   GPIO_ODR_OD3\n#define GPIO_ODR_ODR_4                   GPIO_ODR_OD4\n#define GPIO_ODR_ODR_5                   GPIO_ODR_OD5\n#define GPIO_ODR_ODR_6                   GPIO_ODR_OD6\n#define GPIO_ODR_ODR_7                   GPIO_ODR_OD7\n#define GPIO_ODR_ODR_8                   GPIO_ODR_OD8\n#define GPIO_ODR_ODR_9                   GPIO_ODR_OD9\n#define GPIO_ODR_ODR_10                  GPIO_ODR_OD10\n#define GPIO_ODR_ODR_11                  GPIO_ODR_OD11\n#define GPIO_ODR_ODR_12                  GPIO_ODR_OD12\n#define GPIO_ODR_ODR_13                  GPIO_ODR_OD13\n#define GPIO_ODR_ODR_14                  GPIO_ODR_OD14\n#define GPIO_ODR_ODR_15                  GPIO_ODR_OD15\n\n/******************  Bits definition for GPIO_BSRR register  ******************/\n#define GPIO_BSRR_BS0_Pos                (0U)\n#define GPIO_BSRR_BS0_Msk                (0x1UL << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */\n#define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk\n#define GPIO_BSRR_BS1_Pos                (1U)\n#define GPIO_BSRR_BS1_Msk                (0x1UL << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */\n#define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk\n#define GPIO_BSRR_BS2_Pos                (2U)\n#define GPIO_BSRR_BS2_Msk                (0x1UL << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */\n#define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk\n#define GPIO_BSRR_BS3_Pos                (3U)\n#define GPIO_BSRR_BS3_Msk                (0x1UL << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */\n#define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk\n#define GPIO_BSRR_BS4_Pos                (4U)\n#define GPIO_BSRR_BS4_Msk                (0x1UL << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */\n#define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk\n#define GPIO_BSRR_BS5_Pos                (5U)\n#define GPIO_BSRR_BS5_Msk                (0x1UL << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */\n#define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk\n#define GPIO_BSRR_BS6_Pos                (6U)\n#define GPIO_BSRR_BS6_Msk                (0x1UL << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */\n#define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk\n#define GPIO_BSRR_BS7_Pos                (7U)\n#define GPIO_BSRR_BS7_Msk                (0x1UL << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */\n#define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk\n#define GPIO_BSRR_BS8_Pos                (8U)\n#define GPIO_BSRR_BS8_Msk                (0x1UL << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */\n#define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk\n#define GPIO_BSRR_BS9_Pos                (9U)\n#define GPIO_BSRR_BS9_Msk                (0x1UL << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */\n#define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk\n#define GPIO_BSRR_BS10_Pos               (10U)\n#define GPIO_BSRR_BS10_Msk               (0x1UL << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */\n#define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk\n#define GPIO_BSRR_BS11_Pos               (11U)\n#define GPIO_BSRR_BS11_Msk               (0x1UL << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */\n#define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk\n#define GPIO_BSRR_BS12_Pos               (12U)\n#define GPIO_BSRR_BS12_Msk               (0x1UL << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */\n#define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk\n#define GPIO_BSRR_BS13_Pos               (13U)\n#define GPIO_BSRR_BS13_Msk               (0x1UL << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */\n#define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk\n#define GPIO_BSRR_BS14_Pos               (14U)\n#define GPIO_BSRR_BS14_Msk               (0x1UL << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */\n#define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk\n#define GPIO_BSRR_BS15_Pos               (15U)\n#define GPIO_BSRR_BS15_Msk               (0x1UL << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */\n#define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk\n#define GPIO_BSRR_BR0_Pos                (16U)\n#define GPIO_BSRR_BR0_Msk                (0x1UL << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */\n#define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk\n#define GPIO_BSRR_BR1_Pos                (17U)\n#define GPIO_BSRR_BR1_Msk                (0x1UL << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */\n#define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk\n#define GPIO_BSRR_BR2_Pos                (18U)\n#define GPIO_BSRR_BR2_Msk                (0x1UL << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */\n#define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk\n#define GPIO_BSRR_BR3_Pos                (19U)\n#define GPIO_BSRR_BR3_Msk                (0x1UL << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */\n#define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk\n#define GPIO_BSRR_BR4_Pos                (20U)\n#define GPIO_BSRR_BR4_Msk                (0x1UL << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */\n#define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk\n#define GPIO_BSRR_BR5_Pos                (21U)\n#define GPIO_BSRR_BR5_Msk                (0x1UL << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */\n#define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk\n#define GPIO_BSRR_BR6_Pos                (22U)\n#define GPIO_BSRR_BR6_Msk                (0x1UL << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */\n#define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk\n#define GPIO_BSRR_BR7_Pos                (23U)\n#define GPIO_BSRR_BR7_Msk                (0x1UL << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */\n#define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk\n#define GPIO_BSRR_BR8_Pos                (24U)\n#define GPIO_BSRR_BR8_Msk                (0x1UL << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */\n#define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk\n#define GPIO_BSRR_BR9_Pos                (25U)\n#define GPIO_BSRR_BR9_Msk                (0x1UL << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */\n#define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk\n#define GPIO_BSRR_BR10_Pos               (26U)\n#define GPIO_BSRR_BR10_Msk               (0x1UL << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */\n#define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk\n#define GPIO_BSRR_BR11_Pos               (27U)\n#define GPIO_BSRR_BR11_Msk               (0x1UL << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */\n#define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk\n#define GPIO_BSRR_BR12_Pos               (28U)\n#define GPIO_BSRR_BR12_Msk               (0x1UL << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */\n#define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk\n#define GPIO_BSRR_BR13_Pos               (29U)\n#define GPIO_BSRR_BR13_Msk               (0x1UL << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */\n#define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk\n#define GPIO_BSRR_BR14_Pos               (30U)\n#define GPIO_BSRR_BR14_Msk               (0x1UL << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */\n#define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk\n#define GPIO_BSRR_BR15_Pos               (31U)\n#define GPIO_BSRR_BR15_Msk               (0x1UL << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */\n#define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk\n\n/* Legacy defines */\n#define GPIO_BSRR_BS_0                   GPIO_BSRR_BS0\n#define GPIO_BSRR_BS_1                   GPIO_BSRR_BS1\n#define GPIO_BSRR_BS_2                   GPIO_BSRR_BS2\n#define GPIO_BSRR_BS_3                   GPIO_BSRR_BS3\n#define GPIO_BSRR_BS_4                   GPIO_BSRR_BS4\n#define GPIO_BSRR_BS_5                   GPIO_BSRR_BS5\n#define GPIO_BSRR_BS_6                   GPIO_BSRR_BS6\n#define GPIO_BSRR_BS_7                   GPIO_BSRR_BS7\n#define GPIO_BSRR_BS_8                   GPIO_BSRR_BS8\n#define GPIO_BSRR_BS_9                   GPIO_BSRR_BS9\n#define GPIO_BSRR_BS_10                  GPIO_BSRR_BS10\n#define GPIO_BSRR_BS_11                  GPIO_BSRR_BS11\n#define GPIO_BSRR_BS_12                  GPIO_BSRR_BS12\n#define GPIO_BSRR_BS_13                  GPIO_BSRR_BS13\n#define GPIO_BSRR_BS_14                  GPIO_BSRR_BS14\n#define GPIO_BSRR_BS_15                  GPIO_BSRR_BS15\n#define GPIO_BSRR_BR_0                   GPIO_BSRR_BR0\n#define GPIO_BSRR_BR_1                   GPIO_BSRR_BR1\n#define GPIO_BSRR_BR_2                   GPIO_BSRR_BR2\n#define GPIO_BSRR_BR_3                   GPIO_BSRR_BR3\n#define GPIO_BSRR_BR_4                   GPIO_BSRR_BR4\n#define GPIO_BSRR_BR_5                   GPIO_BSRR_BR5\n#define GPIO_BSRR_BR_6                   GPIO_BSRR_BR6\n#define GPIO_BSRR_BR_7                   GPIO_BSRR_BR7\n#define GPIO_BSRR_BR_8                   GPIO_BSRR_BR8\n#define GPIO_BSRR_BR_9                   GPIO_BSRR_BR9\n#define GPIO_BSRR_BR_10                  GPIO_BSRR_BR10\n#define GPIO_BSRR_BR_11                  GPIO_BSRR_BR11\n#define GPIO_BSRR_BR_12                  GPIO_BSRR_BR12\n#define GPIO_BSRR_BR_13                  GPIO_BSRR_BR13\n#define GPIO_BSRR_BR_14                  GPIO_BSRR_BR14\n#define GPIO_BSRR_BR_15                  GPIO_BSRR_BR15\n#define GPIO_BRR_BR0                     GPIO_BSRR_BR0\n#define GPIO_BRR_BR0_Pos                 GPIO_BSRR_BR0_Pos\n#define GPIO_BRR_BR0_Msk                 GPIO_BSRR_BR0_Msk\n#define GPIO_BRR_BR1                     GPIO_BSRR_BR1\n#define GPIO_BRR_BR1_Pos                 GPIO_BSRR_BR1_Pos\n#define GPIO_BRR_BR1_Msk                 GPIO_BSRR_BR1_Msk\n#define GPIO_BRR_BR2                     GPIO_BSRR_BR2\n#define GPIO_BRR_BR2_Pos                 GPIO_BSRR_BR2_Pos\n#define GPIO_BRR_BR2_Msk                 GPIO_BSRR_BR2_Msk\n#define GPIO_BRR_BR3                     GPIO_BSRR_BR3\n#define GPIO_BRR_BR3_Pos                 GPIO_BSRR_BR3_Pos\n#define GPIO_BRR_BR3_Msk                 GPIO_BSRR_BR3_Msk\n#define GPIO_BRR_BR4                     GPIO_BSRR_BR4\n#define GPIO_BRR_BR4_Pos                 GPIO_BSRR_BR4_Pos\n#define GPIO_BRR_BR4_Msk                 GPIO_BSRR_BR4_Msk\n#define GPIO_BRR_BR5                     GPIO_BSRR_BR5\n#define GPIO_BRR_BR5_Pos                 GPIO_BSRR_BR5_Pos\n#define GPIO_BRR_BR5_Msk                 GPIO_BSRR_BR5_Msk\n#define GPIO_BRR_BR6                     GPIO_BSRR_BR6\n#define GPIO_BRR_BR6_Pos                 GPIO_BSRR_BR6_Pos\n#define GPIO_BRR_BR6_Msk                 GPIO_BSRR_BR6_Msk\n#define GPIO_BRR_BR7                     GPIO_BSRR_BR7\n#define GPIO_BRR_BR7_Pos                 GPIO_BSRR_BR7_Pos\n#define GPIO_BRR_BR7_Msk                 GPIO_BSRR_BR7_Msk\n#define GPIO_BRR_BR8                     GPIO_BSRR_BR8\n#define GPIO_BRR_BR8_Pos                 GPIO_BSRR_BR8_Pos\n#define GPIO_BRR_BR8_Msk                 GPIO_BSRR_BR8_Msk\n#define GPIO_BRR_BR9                     GPIO_BSRR_BR9\n#define GPIO_BRR_BR9_Pos                 GPIO_BSRR_BR9_Pos\n#define GPIO_BRR_BR9_Msk                 GPIO_BSRR_BR9_Msk\n#define GPIO_BRR_BR10                    GPIO_BSRR_BR10\n#define GPIO_BRR_BR10_Pos                GPIO_BSRR_BR10_Pos\n#define GPIO_BRR_BR10_Msk                GPIO_BSRR_BR10_Msk\n#define GPIO_BRR_BR11                    GPIO_BSRR_BR11\n#define GPIO_BRR_BR11_Pos                GPIO_BSRR_BR11_Pos\n#define GPIO_BRR_BR11_Msk                GPIO_BSRR_BR11_Msk\n#define GPIO_BRR_BR12                    GPIO_BSRR_BR12\n#define GPIO_BRR_BR12_Pos                GPIO_BSRR_BR12_Pos\n#define GPIO_BRR_BR12_Msk                GPIO_BSRR_BR12_Msk\n#define GPIO_BRR_BR13                    GPIO_BSRR_BR13\n#define GPIO_BRR_BR13_Pos                GPIO_BSRR_BR13_Pos\n#define GPIO_BRR_BR13_Msk                GPIO_BSRR_BR13_Msk\n#define GPIO_BRR_BR14                    GPIO_BSRR_BR14\n#define GPIO_BRR_BR14_Pos                GPIO_BSRR_BR14_Pos\n#define GPIO_BRR_BR14_Msk                GPIO_BSRR_BR14_Msk\n#define GPIO_BRR_BR15                    GPIO_BSRR_BR15\n#define GPIO_BRR_BR15_Pos                GPIO_BSRR_BR15_Pos\n#define GPIO_BRR_BR15_Msk                GPIO_BSRR_BR15_Msk\n/****************** Bit definition for GPIO_LCKR register *********************/\n#define GPIO_LCKR_LCK0_Pos               (0U)\n#define GPIO_LCKR_LCK0_Msk               (0x1UL << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */\n#define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk\n#define GPIO_LCKR_LCK1_Pos               (1U)\n#define GPIO_LCKR_LCK1_Msk               (0x1UL << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */\n#define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk\n#define GPIO_LCKR_LCK2_Pos               (2U)\n#define GPIO_LCKR_LCK2_Msk               (0x1UL << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */\n#define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk\n#define GPIO_LCKR_LCK3_Pos               (3U)\n#define GPIO_LCKR_LCK3_Msk               (0x1UL << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */\n#define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk\n#define GPIO_LCKR_LCK4_Pos               (4U)\n#define GPIO_LCKR_LCK4_Msk               (0x1UL << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */\n#define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk\n#define GPIO_LCKR_LCK5_Pos               (5U)\n#define GPIO_LCKR_LCK5_Msk               (0x1UL << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */\n#define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk\n#define GPIO_LCKR_LCK6_Pos               (6U)\n#define GPIO_LCKR_LCK6_Msk               (0x1UL << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */\n#define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk\n#define GPIO_LCKR_LCK7_Pos               (7U)\n#define GPIO_LCKR_LCK7_Msk               (0x1UL << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */\n#define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk\n#define GPIO_LCKR_LCK8_Pos               (8U)\n#define GPIO_LCKR_LCK8_Msk               (0x1UL << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */\n#define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk\n#define GPIO_LCKR_LCK9_Pos               (9U)\n#define GPIO_LCKR_LCK9_Msk               (0x1UL << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */\n#define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk\n#define GPIO_LCKR_LCK10_Pos              (10U)\n#define GPIO_LCKR_LCK10_Msk              (0x1UL << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */\n#define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk\n#define GPIO_LCKR_LCK11_Pos              (11U)\n#define GPIO_LCKR_LCK11_Msk              (0x1UL << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */\n#define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk\n#define GPIO_LCKR_LCK12_Pos              (12U)\n#define GPIO_LCKR_LCK12_Msk              (0x1UL << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */\n#define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk\n#define GPIO_LCKR_LCK13_Pos              (13U)\n#define GPIO_LCKR_LCK13_Msk              (0x1UL << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */\n#define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk\n#define GPIO_LCKR_LCK14_Pos              (14U)\n#define GPIO_LCKR_LCK14_Msk              (0x1UL << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */\n#define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk\n#define GPIO_LCKR_LCK15_Pos              (15U)\n#define GPIO_LCKR_LCK15_Msk              (0x1UL << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */\n#define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk\n#define GPIO_LCKR_LCKK_Pos               (16U)\n#define GPIO_LCKR_LCKK_Msk               (0x1UL << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */\n#define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk\n/****************** Bit definition for GPIO_AFRL register *********************/\n#define GPIO_AFRL_AFSEL0_Pos             (0U)\n#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk\n#define GPIO_AFRL_AFSEL0_0               (0x1UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRL_AFSEL0_1               (0x2UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRL_AFSEL0_2               (0x4UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRL_AFSEL0_3               (0x8UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRL_AFSEL1_Pos             (4U)\n#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk\n#define GPIO_AFRL_AFSEL1_0               (0x1UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRL_AFSEL1_1               (0x2UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRL_AFSEL1_2               (0x4UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRL_AFSEL1_3               (0x8UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRL_AFSEL2_Pos             (8U)\n#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */\n#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk\n#define GPIO_AFRL_AFSEL2_0               (0x1UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */\n#define GPIO_AFRL_AFSEL2_1               (0x2UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */\n#define GPIO_AFRL_AFSEL2_2               (0x4UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */\n#define GPIO_AFRL_AFSEL2_3               (0x8UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */\n#define GPIO_AFRL_AFSEL3_Pos             (12U)\n#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */\n#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk\n#define GPIO_AFRL_AFSEL3_0               (0x1UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */\n#define GPIO_AFRL_AFSEL3_1               (0x2UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */\n#define GPIO_AFRL_AFSEL3_2               (0x4UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */\n#define GPIO_AFRL_AFSEL3_3               (0x8UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */\n#define GPIO_AFRL_AFSEL4_Pos             (16U)\n#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */\n#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk\n#define GPIO_AFRL_AFSEL4_0               (0x1UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */\n#define GPIO_AFRL_AFSEL4_1               (0x2UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */\n#define GPIO_AFRL_AFSEL4_2               (0x4UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */\n#define GPIO_AFRL_AFSEL4_3               (0x8UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */\n#define GPIO_AFRL_AFSEL5_Pos             (20U)\n#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */\n#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk\n#define GPIO_AFRL_AFSEL5_0               (0x1UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */\n#define GPIO_AFRL_AFSEL5_1               (0x2UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */\n#define GPIO_AFRL_AFSEL5_2               (0x4UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */\n#define GPIO_AFRL_AFSEL5_3               (0x8UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */\n#define GPIO_AFRL_AFSEL6_Pos             (24U)\n#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */\n#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk\n#define GPIO_AFRL_AFSEL6_0               (0x1UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */\n#define GPIO_AFRL_AFSEL6_1               (0x2UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */\n#define GPIO_AFRL_AFSEL6_2               (0x4UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */\n#define GPIO_AFRL_AFSEL6_3               (0x8UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */\n#define GPIO_AFRL_AFSEL7_Pos             (28U)\n#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */\n#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk\n#define GPIO_AFRL_AFSEL7_0               (0x1UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */\n#define GPIO_AFRL_AFSEL7_1               (0x2UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */\n#define GPIO_AFRL_AFSEL7_2               (0x4UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */\n#define GPIO_AFRL_AFSEL7_3               (0x8UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFSEL0\n#define GPIO_AFRL_AFRL0_0                GPIO_AFRL_AFSEL0_0\n#define GPIO_AFRL_AFRL0_1                GPIO_AFRL_AFSEL0_1\n#define GPIO_AFRL_AFRL0_2                GPIO_AFRL_AFSEL0_2\n#define GPIO_AFRL_AFRL0_3                GPIO_AFRL_AFSEL0_3\n#define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFSEL1\n#define GPIO_AFRL_AFRL1_0                GPIO_AFRL_AFSEL1_0\n#define GPIO_AFRL_AFRL1_1                GPIO_AFRL_AFSEL1_1\n#define GPIO_AFRL_AFRL1_2                GPIO_AFRL_AFSEL1_2\n#define GPIO_AFRL_AFRL1_3                GPIO_AFRL_AFSEL1_3\n#define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFSEL2\n#define GPIO_AFRL_AFRL2_0                GPIO_AFRL_AFSEL2_0\n#define GPIO_AFRL_AFRL2_1                GPIO_AFRL_AFSEL2_1\n#define GPIO_AFRL_AFRL2_2                GPIO_AFRL_AFSEL2_2\n#define GPIO_AFRL_AFRL2_3                GPIO_AFRL_AFSEL2_3\n#define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFSEL3\n#define GPIO_AFRL_AFRL3_0                GPIO_AFRL_AFSEL3_0\n#define GPIO_AFRL_AFRL3_1                GPIO_AFRL_AFSEL3_1\n#define GPIO_AFRL_AFRL3_2                GPIO_AFRL_AFSEL3_2\n#define GPIO_AFRL_AFRL3_3                GPIO_AFRL_AFSEL3_3\n#define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFSEL4\n#define GPIO_AFRL_AFRL4_0                GPIO_AFRL_AFSEL4_0\n#define GPIO_AFRL_AFRL4_1                GPIO_AFRL_AFSEL4_1\n#define GPIO_AFRL_AFRL4_2                GPIO_AFRL_AFSEL4_2\n#define GPIO_AFRL_AFRL4_3                GPIO_AFRL_AFSEL4_3\n#define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFSEL5\n#define GPIO_AFRL_AFRL5_0                GPIO_AFRL_AFSEL5_0\n#define GPIO_AFRL_AFRL5_1                GPIO_AFRL_AFSEL5_1\n#define GPIO_AFRL_AFRL5_2                GPIO_AFRL_AFSEL5_2\n#define GPIO_AFRL_AFRL5_3                GPIO_AFRL_AFSEL5_3\n#define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFSEL6\n#define GPIO_AFRL_AFRL6_0                GPIO_AFRL_AFSEL6_0\n#define GPIO_AFRL_AFRL6_1                GPIO_AFRL_AFSEL6_1\n#define GPIO_AFRL_AFRL6_2                GPIO_AFRL_AFSEL6_2\n#define GPIO_AFRL_AFRL6_3                GPIO_AFRL_AFSEL6_3\n#define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFSEL7\n#define GPIO_AFRL_AFRL7_0                GPIO_AFRL_AFSEL7_0\n#define GPIO_AFRL_AFRL7_1                GPIO_AFRL_AFSEL7_1\n#define GPIO_AFRL_AFRL7_2                GPIO_AFRL_AFSEL7_2\n#define GPIO_AFRL_AFRL7_3                GPIO_AFRL_AFSEL7_3\n\n/****************** Bit definition for GPIO_AFRH register *********************/\n#define GPIO_AFRH_AFSEL8_Pos             (0U)\n#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk\n#define GPIO_AFRH_AFSEL8_0               (0x1UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRH_AFSEL8_1               (0x2UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRH_AFSEL8_2               (0x4UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRH_AFSEL8_3               (0x8UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRH_AFSEL9_Pos             (4U)\n#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk\n#define GPIO_AFRH_AFSEL9_0               (0x1UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRH_AFSEL9_1               (0x2UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRH_AFSEL9_2               (0x4UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRH_AFSEL9_3               (0x8UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRH_AFSEL10_Pos            (8U)\n#define GPIO_AFRH_AFSEL10_Msk            (0xFUL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */\n#define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk\n#define GPIO_AFRH_AFSEL10_0              (0x1UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */\n#define GPIO_AFRH_AFSEL10_1              (0x2UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */\n#define GPIO_AFRH_AFSEL10_2              (0x4UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */\n#define GPIO_AFRH_AFSEL10_3              (0x8UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */\n#define GPIO_AFRH_AFSEL11_Pos            (12U)\n#define GPIO_AFRH_AFSEL11_Msk            (0xFUL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */\n#define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk\n#define GPIO_AFRH_AFSEL11_0              (0x1UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */\n#define GPIO_AFRH_AFSEL11_1              (0x2UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */\n#define GPIO_AFRH_AFSEL11_2              (0x4UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */\n#define GPIO_AFRH_AFSEL11_3              (0x8UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */\n#define GPIO_AFRH_AFSEL12_Pos            (16U)\n#define GPIO_AFRH_AFSEL12_Msk            (0xFUL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */\n#define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk\n#define GPIO_AFRH_AFSEL12_0              (0x1UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */\n#define GPIO_AFRH_AFSEL12_1              (0x2UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */\n#define GPIO_AFRH_AFSEL12_2              (0x4UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */\n#define GPIO_AFRH_AFSEL12_3              (0x8UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */\n#define GPIO_AFRH_AFSEL13_Pos            (20U)\n#define GPIO_AFRH_AFSEL13_Msk            (0xFUL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */\n#define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk\n#define GPIO_AFRH_AFSEL13_0              (0x1UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */\n#define GPIO_AFRH_AFSEL13_1              (0x2UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */\n#define GPIO_AFRH_AFSEL13_2              (0x4UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */\n#define GPIO_AFRH_AFSEL13_3              (0x8UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */\n#define GPIO_AFRH_AFSEL14_Pos            (24U)\n#define GPIO_AFRH_AFSEL14_Msk            (0xFUL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */\n#define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk\n#define GPIO_AFRH_AFSEL14_0              (0x1UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */\n#define GPIO_AFRH_AFSEL14_1              (0x2UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */\n#define GPIO_AFRH_AFSEL14_2              (0x4UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */\n#define GPIO_AFRH_AFSEL14_3              (0x8UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */\n#define GPIO_AFRH_AFSEL15_Pos            (28U)\n#define GPIO_AFRH_AFSEL15_Msk            (0xFUL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */\n#define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk\n#define GPIO_AFRH_AFSEL15_0              (0x1UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */\n#define GPIO_AFRH_AFSEL15_1              (0x2UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */\n#define GPIO_AFRH_AFSEL15_2              (0x4UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */\n#define GPIO_AFRH_AFSEL15_3              (0x8UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFSEL8\n#define GPIO_AFRH_AFRH0_0                GPIO_AFRH_AFSEL8_0\n#define GPIO_AFRH_AFRH0_1                GPIO_AFRH_AFSEL8_1\n#define GPIO_AFRH_AFRH0_2                GPIO_AFRH_AFSEL8_2\n#define GPIO_AFRH_AFRH0_3                GPIO_AFRH_AFSEL8_3\n#define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFSEL9\n#define GPIO_AFRH_AFRH1_0                GPIO_AFRH_AFSEL9_0\n#define GPIO_AFRH_AFRH1_1                GPIO_AFRH_AFSEL9_1\n#define GPIO_AFRH_AFRH1_2                GPIO_AFRH_AFSEL9_2\n#define GPIO_AFRH_AFRH1_3                GPIO_AFRH_AFSEL9_3\n#define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFSEL10\n#define GPIO_AFRH_AFRH2_0                GPIO_AFRH_AFSEL10_0\n#define GPIO_AFRH_AFRH2_1                GPIO_AFRH_AFSEL10_1\n#define GPIO_AFRH_AFRH2_2                GPIO_AFRH_AFSEL10_2\n#define GPIO_AFRH_AFRH2_3                GPIO_AFRH_AFSEL10_3\n#define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFSEL11\n#define GPIO_AFRH_AFRH3_0                GPIO_AFRH_AFSEL11_0\n#define GPIO_AFRH_AFRH3_1                GPIO_AFRH_AFSEL11_1\n#define GPIO_AFRH_AFRH3_2                GPIO_AFRH_AFSEL11_2\n#define GPIO_AFRH_AFRH3_3                GPIO_AFRH_AFSEL11_3\n#define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFSEL12\n#define GPIO_AFRH_AFRH4_0                GPIO_AFRH_AFSEL12_0\n#define GPIO_AFRH_AFRH4_1                GPIO_AFRH_AFSEL12_1\n#define GPIO_AFRH_AFRH4_2                GPIO_AFRH_AFSEL12_2\n#define GPIO_AFRH_AFRH4_3                GPIO_AFRH_AFSEL12_3\n#define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFSEL13\n#define GPIO_AFRH_AFRH5_0                GPIO_AFRH_AFSEL13_0\n#define GPIO_AFRH_AFRH5_1                GPIO_AFRH_AFSEL13_1\n#define GPIO_AFRH_AFRH5_2                GPIO_AFRH_AFSEL13_2\n#define GPIO_AFRH_AFRH5_3                GPIO_AFRH_AFSEL13_3\n#define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFSEL14\n#define GPIO_AFRH_AFRH6_0                GPIO_AFRH_AFSEL14_0\n#define GPIO_AFRH_AFRH6_1                GPIO_AFRH_AFSEL14_1\n#define GPIO_AFRH_AFRH6_2                GPIO_AFRH_AFSEL14_2\n#define GPIO_AFRH_AFRH6_3                GPIO_AFRH_AFSEL14_3\n#define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFSEL15\n#define GPIO_AFRH_AFRH7_0                GPIO_AFRH_AFSEL15_0\n#define GPIO_AFRH_AFRH7_1                GPIO_AFRH_AFSEL15_1\n#define GPIO_AFRH_AFRH7_2                GPIO_AFRH_AFSEL15_2\n#define GPIO_AFRH_AFRH7_3                GPIO_AFRH_AFSEL15_3\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Inter-integrated Circuit Interface                    */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for I2C_CR1 register  ********************/\n#define I2C_CR1_PE_Pos            (0U)\n#define I2C_CR1_PE_Msk            (0x1UL << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */\n#define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */\n#define I2C_CR1_SMBUS_Pos         (1U)\n#define I2C_CR1_SMBUS_Msk         (0x1UL << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */\n#define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */\n#define I2C_CR1_SMBTYPE_Pos       (3U)\n#define I2C_CR1_SMBTYPE_Msk       (0x1UL << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */\n#define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */\n#define I2C_CR1_ENARP_Pos         (4U)\n#define I2C_CR1_ENARP_Msk         (0x1UL << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */\n#define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */\n#define I2C_CR1_ENPEC_Pos         (5U)\n#define I2C_CR1_ENPEC_Msk         (0x1UL << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */\n#define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */\n#define I2C_CR1_ENGC_Pos          (6U)\n#define I2C_CR1_ENGC_Msk          (0x1UL << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */\n#define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */\n#define I2C_CR1_NOSTRETCH_Pos     (7U)\n#define I2C_CR1_NOSTRETCH_Msk     (0x1UL << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */\n#define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */\n#define I2C_CR1_START_Pos         (8U)\n#define I2C_CR1_START_Msk         (0x1UL << I2C_CR1_START_Pos)                  /*!< 0x00000100 */\n#define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */\n#define I2C_CR1_STOP_Pos          (9U)\n#define I2C_CR1_STOP_Msk          (0x1UL << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */\n#define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */\n#define I2C_CR1_ACK_Pos           (10U)\n#define I2C_CR1_ACK_Msk           (0x1UL << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */\n#define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */\n#define I2C_CR1_POS_Pos           (11U)\n#define I2C_CR1_POS_Msk           (0x1UL << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */\n#define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */\n#define I2C_CR1_PEC_Pos           (12U)\n#define I2C_CR1_PEC_Msk           (0x1UL << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */\n#define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */\n#define I2C_CR1_ALERT_Pos         (13U)\n#define I2C_CR1_ALERT_Msk         (0x1UL << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */\n#define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */\n#define I2C_CR1_SWRST_Pos         (15U)\n#define I2C_CR1_SWRST_Msk         (0x1UL << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */\n#define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */\n\n/*******************  Bit definition for I2C_CR2 register  ********************/\n#define I2C_CR2_FREQ_Pos          (0U)\n#define I2C_CR2_FREQ_Msk          (0x3FUL << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */\n#define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */\n#define I2C_CR2_FREQ_0            (0x01UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */\n#define I2C_CR2_FREQ_1            (0x02UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */\n#define I2C_CR2_FREQ_2            (0x04UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */\n#define I2C_CR2_FREQ_3            (0x08UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */\n#define I2C_CR2_FREQ_4            (0x10UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */\n#define I2C_CR2_FREQ_5            (0x20UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */\n\n#define I2C_CR2_ITERREN_Pos       (8U)\n#define I2C_CR2_ITERREN_Msk       (0x1UL << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */\n#define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */\n#define I2C_CR2_ITEVTEN_Pos       (9U)\n#define I2C_CR2_ITEVTEN_Msk       (0x1UL << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */\n#define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */\n#define I2C_CR2_ITBUFEN_Pos       (10U)\n#define I2C_CR2_ITBUFEN_Msk       (0x1UL << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */\n#define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */\n#define I2C_CR2_DMAEN_Pos         (11U)\n#define I2C_CR2_DMAEN_Msk         (0x1UL << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */\n#define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */\n#define I2C_CR2_LAST_Pos          (12U)\n#define I2C_CR2_LAST_Msk          (0x1UL << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */\n#define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */\n\n/*******************  Bit definition for I2C_OAR1 register  *******************/\n#define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */\n#define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */\n\n#define I2C_OAR1_ADD0_Pos         (0U)\n#define I2C_OAR1_ADD0_Msk         (0x1UL << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */\n#define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */\n#define I2C_OAR1_ADD1_Pos         (1U)\n#define I2C_OAR1_ADD1_Msk         (0x1UL << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */\n#define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */\n#define I2C_OAR1_ADD2_Pos         (2U)\n#define I2C_OAR1_ADD2_Msk         (0x1UL << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */\n#define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */\n#define I2C_OAR1_ADD3_Pos         (3U)\n#define I2C_OAR1_ADD3_Msk         (0x1UL << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */\n#define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */\n#define I2C_OAR1_ADD4_Pos         (4U)\n#define I2C_OAR1_ADD4_Msk         (0x1UL << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */\n#define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */\n#define I2C_OAR1_ADD5_Pos         (5U)\n#define I2C_OAR1_ADD5_Msk         (0x1UL << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */\n#define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */\n#define I2C_OAR1_ADD6_Pos         (6U)\n#define I2C_OAR1_ADD6_Msk         (0x1UL << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */\n#define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */\n#define I2C_OAR1_ADD7_Pos         (7U)\n#define I2C_OAR1_ADD7_Msk         (0x1UL << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */\n#define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */\n#define I2C_OAR1_ADD8_Pos         (8U)\n#define I2C_OAR1_ADD8_Msk         (0x1UL << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */\n#define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */\n#define I2C_OAR1_ADD9_Pos         (9U)\n#define I2C_OAR1_ADD9_Msk         (0x1UL << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */\n#define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */\n\n#define I2C_OAR1_ADDMODE_Pos      (15U)\n#define I2C_OAR1_ADDMODE_Msk      (0x1UL << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */\n#define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */\n\n/*******************  Bit definition for I2C_OAR2 register  *******************/\n#define I2C_OAR2_ENDUAL_Pos       (0U)\n#define I2C_OAR2_ENDUAL_Msk       (0x1UL << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */\n#define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */\n#define I2C_OAR2_ADD2_Pos         (1U)\n#define I2C_OAR2_ADD2_Msk         (0x7FUL << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */\n#define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */\n\n/********************  Bit definition for I2C_DR register  ********************/\n#define I2C_DR_DR_Pos             (0U)\n#define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */\n#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */\n\n/*******************  Bit definition for I2C_SR1 register  ********************/\n#define I2C_SR1_SB_Pos            (0U)\n#define I2C_SR1_SB_Msk            (0x1UL << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */\n#define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */\n#define I2C_SR1_ADDR_Pos          (1U)\n#define I2C_SR1_ADDR_Msk          (0x1UL << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */\n#define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */\n#define I2C_SR1_BTF_Pos           (2U)\n#define I2C_SR1_BTF_Msk           (0x1UL << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */\n#define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */\n#define I2C_SR1_ADD10_Pos         (3U)\n#define I2C_SR1_ADD10_Msk         (0x1UL << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */\n#define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */\n#define I2C_SR1_STOPF_Pos         (4U)\n#define I2C_SR1_STOPF_Msk         (0x1UL << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */\n#define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */\n#define I2C_SR1_RXNE_Pos          (6U)\n#define I2C_SR1_RXNE_Msk          (0x1UL << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */\n#define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */\n#define I2C_SR1_TXE_Pos           (7U)\n#define I2C_SR1_TXE_Msk           (0x1UL << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */\n#define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */\n#define I2C_SR1_BERR_Pos          (8U)\n#define I2C_SR1_BERR_Msk          (0x1UL << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */\n#define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */\n#define I2C_SR1_ARLO_Pos          (9U)\n#define I2C_SR1_ARLO_Msk          (0x1UL << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */\n#define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */\n#define I2C_SR1_AF_Pos            (10U)\n#define I2C_SR1_AF_Msk            (0x1UL << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */\n#define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */\n#define I2C_SR1_OVR_Pos           (11U)\n#define I2C_SR1_OVR_Msk           (0x1UL << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */\n#define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */\n#define I2C_SR1_PECERR_Pos        (12U)\n#define I2C_SR1_PECERR_Msk        (0x1UL << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */\n#define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */\n#define I2C_SR1_TIMEOUT_Pos       (14U)\n#define I2C_SR1_TIMEOUT_Msk       (0x1UL << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */\n#define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */\n#define I2C_SR1_SMBALERT_Pos      (15U)\n#define I2C_SR1_SMBALERT_Msk      (0x1UL << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */\n#define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */\n\n/*******************  Bit definition for I2C_SR2 register  ********************/\n#define I2C_SR2_MSL_Pos           (0U)\n#define I2C_SR2_MSL_Msk           (0x1UL << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */\n#define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */\n#define I2C_SR2_BUSY_Pos          (1U)\n#define I2C_SR2_BUSY_Msk          (0x1UL << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */\n#define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */\n#define I2C_SR2_TRA_Pos           (2U)\n#define I2C_SR2_TRA_Msk           (0x1UL << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */\n#define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */\n#define I2C_SR2_GENCALL_Pos       (4U)\n#define I2C_SR2_GENCALL_Msk       (0x1UL << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */\n#define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */\n#define I2C_SR2_SMBDEFAULT_Pos    (5U)\n#define I2C_SR2_SMBDEFAULT_Msk    (0x1UL << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */\n#define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */\n#define I2C_SR2_SMBHOST_Pos       (6U)\n#define I2C_SR2_SMBHOST_Msk       (0x1UL << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */\n#define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */\n#define I2C_SR2_DUALF_Pos         (7U)\n#define I2C_SR2_DUALF_Msk         (0x1UL << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */\n#define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */\n#define I2C_SR2_PEC_Pos           (8U)\n#define I2C_SR2_PEC_Msk           (0xFFUL << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */\n#define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */\n\n/*******************  Bit definition for I2C_CCR register  ********************/\n#define I2C_CCR_CCR_Pos           (0U)\n#define I2C_CCR_CCR_Msk           (0xFFFUL << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */\n#define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */\n#define I2C_CCR_DUTY_Pos          (14U)\n#define I2C_CCR_DUTY_Msk          (0x1UL << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */\n#define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */\n#define I2C_CCR_FS_Pos            (15U)\n#define I2C_CCR_FS_Msk            (0x1UL << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */\n#define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */\n\n/******************  Bit definition for I2C_TRISE register  *******************/\n#define I2C_TRISE_TRISE_Pos       (0U)\n#define I2C_TRISE_TRISE_Msk       (0x3FUL << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */\n#define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */\n\n/******************  Bit definition for I2C_FLTR register  *******************/\n#define I2C_FLTR_DNF_Pos          (0U)\n#define I2C_FLTR_DNF_Msk          (0xFUL << I2C_FLTR_DNF_Pos)                   /*!< 0x0000000F */\n#define I2C_FLTR_DNF              I2C_FLTR_DNF_Msk                             /*!<Digital Noise Filter */\n#define I2C_FLTR_ANOFF_Pos        (4U)\n#define I2C_FLTR_ANOFF_Msk        (0x1UL << I2C_FLTR_ANOFF_Pos)                 /*!< 0x00000010 */\n#define I2C_FLTR_ANOFF            I2C_FLTR_ANOFF_Msk                           /*!<Analog Noise Filter OFF */\n\n/******************************************************************************/\n/*                                                                            */\n/*        Fast Mode Plus Inter-integrated Circuit Interface (I2C)             */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for I2C_CR1 register  *******************/\n#define FMPI2C_CR1_PE_Pos               (0U)\n#define FMPI2C_CR1_PE_Msk               (0x1UL << FMPI2C_CR1_PE_Pos)            /*!< 0x00000001 */\n#define FMPI2C_CR1_PE                   FMPI2C_CR1_PE_Msk                      /*!< Peripheral enable                   */\n#define FMPI2C_CR1_TXIE_Pos             (1U)\n#define FMPI2C_CR1_TXIE_Msk             (0x1UL << FMPI2C_CR1_TXIE_Pos)          /*!< 0x00000002 */\n#define FMPI2C_CR1_TXIE                 FMPI2C_CR1_TXIE_Msk                    /*!< TX interrupt enable                 */\n#define FMPI2C_CR1_RXIE_Pos             (2U)\n#define FMPI2C_CR1_RXIE_Msk             (0x1UL << FMPI2C_CR1_RXIE_Pos)          /*!< 0x00000004 */\n#define FMPI2C_CR1_RXIE                 FMPI2C_CR1_RXIE_Msk                    /*!< RX interrupt enable                 */\n#define FMPI2C_CR1_ADDRIE_Pos           (3U)\n#define FMPI2C_CR1_ADDRIE_Msk           (0x1UL << FMPI2C_CR1_ADDRIE_Pos)        /*!< 0x00000008 */\n#define FMPI2C_CR1_ADDRIE               FMPI2C_CR1_ADDRIE_Msk                  /*!< Address match interrupt enable      */\n#define FMPI2C_CR1_NACKIE_Pos           (4U)\n#define FMPI2C_CR1_NACKIE_Msk           (0x1UL << FMPI2C_CR1_NACKIE_Pos)        /*!< 0x00000010 */\n#define FMPI2C_CR1_NACKIE               FMPI2C_CR1_NACKIE_Msk                  /*!< NACK received interrupt enable      */\n#define FMPI2C_CR1_STOPIE_Pos           (5U)\n#define FMPI2C_CR1_STOPIE_Msk           (0x1UL << FMPI2C_CR1_STOPIE_Pos)        /*!< 0x00000020 */\n#define FMPI2C_CR1_STOPIE               FMPI2C_CR1_STOPIE_Msk                  /*!< STOP detection interrupt enable     */\n#define FMPI2C_CR1_TCIE_Pos             (6U)\n#define FMPI2C_CR1_TCIE_Msk             (0x1UL << FMPI2C_CR1_TCIE_Pos)          /*!< 0x00000040 */\n#define FMPI2C_CR1_TCIE                 FMPI2C_CR1_TCIE_Msk                    /*!< Transfer complete interrupt enable  */\n#define FMPI2C_CR1_ERRIE_Pos            (7U)\n#define FMPI2C_CR1_ERRIE_Msk            (0x1UL << FMPI2C_CR1_ERRIE_Pos)         /*!< 0x00000080 */\n#define FMPI2C_CR1_ERRIE                FMPI2C_CR1_ERRIE_Msk                   /*!< Errors interrupt enable             */\n#define FMPI2C_CR1_DNF_Pos              (8U)\n#define FMPI2C_CR1_DNF_Msk              (0xFUL << FMPI2C_CR1_DNF_Pos)           /*!< 0x00000F00 */\n#define FMPI2C_CR1_DNF                  FMPI2C_CR1_DNF_Msk                     /*!< Digital noise filter                */\n#define FMPI2C_CR1_ANFOFF_Pos           (12U)\n#define FMPI2C_CR1_ANFOFF_Msk           (0x1UL << FMPI2C_CR1_ANFOFF_Pos)        /*!< 0x00001000 */\n#define FMPI2C_CR1_ANFOFF               FMPI2C_CR1_ANFOFF_Msk                  /*!< Analog noise filter OFF             */\n#define FMPI2C_CR1_TXDMAEN_Pos          (14U)\n#define FMPI2C_CR1_TXDMAEN_Msk          (0x1UL << FMPI2C_CR1_TXDMAEN_Pos)       /*!< 0x00004000 */\n#define FMPI2C_CR1_TXDMAEN              FMPI2C_CR1_TXDMAEN_Msk                 /*!< DMA transmission requests enable    */\n#define FMPI2C_CR1_RXDMAEN_Pos          (15U)\n#define FMPI2C_CR1_RXDMAEN_Msk          (0x1UL << FMPI2C_CR1_RXDMAEN_Pos)       /*!< 0x00008000 */\n#define FMPI2C_CR1_RXDMAEN              FMPI2C_CR1_RXDMAEN_Msk                 /*!< DMA reception requests enable       */\n#define FMPI2C_CR1_SBC_Pos              (16U)\n#define FMPI2C_CR1_SBC_Msk              (0x1UL << FMPI2C_CR1_SBC_Pos)           /*!< 0x00010000 */\n#define FMPI2C_CR1_SBC                  FMPI2C_CR1_SBC_Msk                     /*!< Slave byte control                  */\n#define FMPI2C_CR1_NOSTRETCH_Pos        (17U)\n#define FMPI2C_CR1_NOSTRETCH_Msk        (0x1UL << FMPI2C_CR1_NOSTRETCH_Pos)     /*!< 0x00020000 */\n#define FMPI2C_CR1_NOSTRETCH            FMPI2C_CR1_NOSTRETCH_Msk               /*!< Clock stretching disable            */\n#define FMPI2C_CR1_GCEN_Pos             (19U)\n#define FMPI2C_CR1_GCEN_Msk             (0x1UL << FMPI2C_CR1_GCEN_Pos)          /*!< 0x00080000 */\n#define FMPI2C_CR1_GCEN                 FMPI2C_CR1_GCEN_Msk                    /*!< General call enable                 */\n#define FMPI2C_CR1_SMBHEN_Pos           (20U)\n#define FMPI2C_CR1_SMBHEN_Msk           (0x1UL << FMPI2C_CR1_SMBHEN_Pos)        /*!< 0x00100000 */\n#define FMPI2C_CR1_SMBHEN               FMPI2C_CR1_SMBHEN_Msk                  /*!< SMBus host address enable           */\n#define FMPI2C_CR1_SMBDEN_Pos           (21U)\n#define FMPI2C_CR1_SMBDEN_Msk           (0x1UL << FMPI2C_CR1_SMBDEN_Pos)        /*!< 0x00200000 */\n#define FMPI2C_CR1_SMBDEN               FMPI2C_CR1_SMBDEN_Msk                  /*!< SMBus device default address enable */\n#define FMPI2C_CR1_ALERTEN_Pos          (22U)\n#define FMPI2C_CR1_ALERTEN_Msk          (0x1UL << FMPI2C_CR1_ALERTEN_Pos)       /*!< 0x00400000 */\n#define FMPI2C_CR1_ALERTEN              FMPI2C_CR1_ALERTEN_Msk                 /*!< SMBus alert enable                  */\n#define FMPI2C_CR1_PECEN_Pos            (23U)\n#define FMPI2C_CR1_PECEN_Msk            (0x1UL << FMPI2C_CR1_PECEN_Pos)         /*!< 0x00800000 */\n#define FMPI2C_CR1_PECEN                FMPI2C_CR1_PECEN_Msk                   /*!< PEC enable                          */\n\n/* Legacy Defines */\n#define FMPI2C_CR1_DFN_Pos              FMPI2C_CR1_DNF_Pos\n#define FMPI2C_CR1_DFN_Msk              FMPI2C_CR1_DNF_Msk\n#define FMPI2C_CR1_DFN                  FMPI2C_CR1_DNF\n/******************  Bit definition for I2C_CR2 register  ********************/\n#define FMPI2C_CR2_SADD_Pos             (0U)\n#define FMPI2C_CR2_SADD_Msk             (0x3FFUL << FMPI2C_CR2_SADD_Pos)        /*!< 0x000003FF */\n#define FMPI2C_CR2_SADD                 FMPI2C_CR2_SADD_Msk                    /*!< Slave address (master mode)                             */\n#define FMPI2C_CR2_RD_WRN_Pos           (10U)\n#define FMPI2C_CR2_RD_WRN_Msk           (0x1UL << FMPI2C_CR2_RD_WRN_Pos)        /*!< 0x00000400 */\n#define FMPI2C_CR2_RD_WRN               FMPI2C_CR2_RD_WRN_Msk                  /*!< Transfer direction (master mode)                        */\n#define FMPI2C_CR2_ADD10_Pos            (11U)\n#define FMPI2C_CR2_ADD10_Msk            (0x1UL << FMPI2C_CR2_ADD10_Pos)         /*!< 0x00000800 */\n#define FMPI2C_CR2_ADD10                FMPI2C_CR2_ADD10_Msk                   /*!< 10-bit addressing mode (master mode)                    */\n#define FMPI2C_CR2_HEAD10R_Pos          (12U)\n#define FMPI2C_CR2_HEAD10R_Msk          (0x1UL << FMPI2C_CR2_HEAD10R_Pos)       /*!< 0x00001000 */\n#define FMPI2C_CR2_HEAD10R              FMPI2C_CR2_HEAD10R_Msk                 /*!< 10-bit address header only read direction (master mode) */\n#define FMPI2C_CR2_START_Pos            (13U)\n#define FMPI2C_CR2_START_Msk            (0x1UL << FMPI2C_CR2_START_Pos)         /*!< 0x00002000 */\n#define FMPI2C_CR2_START                FMPI2C_CR2_START_Msk                   /*!< START generation                                        */\n#define FMPI2C_CR2_STOP_Pos             (14U)\n#define FMPI2C_CR2_STOP_Msk             (0x1UL << FMPI2C_CR2_STOP_Pos)          /*!< 0x00004000 */\n#define FMPI2C_CR2_STOP                 FMPI2C_CR2_STOP_Msk                    /*!< STOP generation (master mode)                           */\n#define FMPI2C_CR2_NACK_Pos             (15U)\n#define FMPI2C_CR2_NACK_Msk             (0x1UL << FMPI2C_CR2_NACK_Pos)          /*!< 0x00008000 */\n#define FMPI2C_CR2_NACK                 FMPI2C_CR2_NACK_Msk                    /*!< NACK generation (slave mode)                            */\n#define FMPI2C_CR2_NBYTES_Pos           (16U)\n#define FMPI2C_CR2_NBYTES_Msk           (0xFFUL << FMPI2C_CR2_NBYTES_Pos)       /*!< 0x00FF0000 */\n#define FMPI2C_CR2_NBYTES               FMPI2C_CR2_NBYTES_Msk                  /*!< Number of bytes                                         */\n#define FMPI2C_CR2_RELOAD_Pos           (24U)\n#define FMPI2C_CR2_RELOAD_Msk           (0x1UL << FMPI2C_CR2_RELOAD_Pos)        /*!< 0x01000000 */\n#define FMPI2C_CR2_RELOAD               FMPI2C_CR2_RELOAD_Msk                  /*!< NBYTES reload mode                                      */\n#define FMPI2C_CR2_AUTOEND_Pos          (25U)\n#define FMPI2C_CR2_AUTOEND_Msk          (0x1UL << FMPI2C_CR2_AUTOEND_Pos)       /*!< 0x02000000 */\n#define FMPI2C_CR2_AUTOEND              FMPI2C_CR2_AUTOEND_Msk                 /*!< Automatic end mode (master mode)                        */\n#define FMPI2C_CR2_PECBYTE_Pos          (26U)\n#define FMPI2C_CR2_PECBYTE_Msk          (0x1UL << FMPI2C_CR2_PECBYTE_Pos)       /*!< 0x04000000 */\n#define FMPI2C_CR2_PECBYTE              FMPI2C_CR2_PECBYTE_Msk                 /*!< Packet error checking byte                              */\n\n/*******************  Bit definition for I2C_OAR1 register  ******************/\n#define FMPI2C_OAR1_OA1_Pos             (0U)\n#define FMPI2C_OAR1_OA1_Msk             (0x3FFUL << FMPI2C_OAR1_OA1_Pos)        /*!< 0x000003FF */\n#define FMPI2C_OAR1_OA1                 FMPI2C_OAR1_OA1_Msk                    /*!< Interface own address 1   */\n#define FMPI2C_OAR1_OA1MODE_Pos         (10U)\n#define FMPI2C_OAR1_OA1MODE_Msk         (0x1UL << FMPI2C_OAR1_OA1MODE_Pos)      /*!< 0x00000400 */\n#define FMPI2C_OAR1_OA1MODE             FMPI2C_OAR1_OA1MODE_Msk                /*!< Own address 1 10-bit mode */\n#define FMPI2C_OAR1_OA1EN_Pos           (15U)\n#define FMPI2C_OAR1_OA1EN_Msk           (0x1UL << FMPI2C_OAR1_OA1EN_Pos)        /*!< 0x00008000 */\n#define FMPI2C_OAR1_OA1EN               FMPI2C_OAR1_OA1EN_Msk                  /*!< Own address 1 enable      */\n\n/*******************  Bit definition for I2C_OAR2 register  ******************/\n#define FMPI2C_OAR2_OA2_Pos             (1U)\n#define FMPI2C_OAR2_OA2_Msk             (0x7FUL << FMPI2C_OAR2_OA2_Pos)         /*!< 0x000000FE */\n#define FMPI2C_OAR2_OA2                 FMPI2C_OAR2_OA2_Msk                    /*!< Interface own address 2 */\n#define FMPI2C_OAR2_OA2MSK_Pos          (8U)\n#define FMPI2C_OAR2_OA2MSK_Msk          (0x7UL << FMPI2C_OAR2_OA2MSK_Pos)       /*!< 0x00000700 */\n#define FMPI2C_OAR2_OA2MSK              FMPI2C_OAR2_OA2MSK_Msk                 /*!< Own address 2 masks     */\n#define FMPI2C_OAR2_OA2EN_Pos           (15U)\n#define FMPI2C_OAR2_OA2EN_Msk           (0x1UL << FMPI2C_OAR2_OA2EN_Pos)        /*!< 0x00008000 */\n#define FMPI2C_OAR2_OA2EN               FMPI2C_OAR2_OA2EN_Msk                  /*!< Own address 2 enable    */\n\n/*******************  Bit definition for I2C_TIMINGR register *******************/\n#define FMPI2C_TIMINGR_SCLL_Pos         (0U)\n#define FMPI2C_TIMINGR_SCLL_Msk         (0xFFUL << FMPI2C_TIMINGR_SCLL_Pos)     /*!< 0x000000FF */\n#define FMPI2C_TIMINGR_SCLL             FMPI2C_TIMINGR_SCLL_Msk                /*!< SCL low period (master mode)  */\n#define FMPI2C_TIMINGR_SCLH_Pos         (8U)\n#define FMPI2C_TIMINGR_SCLH_Msk         (0xFFUL << FMPI2C_TIMINGR_SCLH_Pos)     /*!< 0x0000FF00 */\n#define FMPI2C_TIMINGR_SCLH             FMPI2C_TIMINGR_SCLH_Msk                /*!< SCL high period (master mode) */\n#define FMPI2C_TIMINGR_SDADEL_Pos       (16U)\n#define FMPI2C_TIMINGR_SDADEL_Msk       (0xFUL << FMPI2C_TIMINGR_SDADEL_Pos)    /*!< 0x000F0000 */\n#define FMPI2C_TIMINGR_SDADEL           FMPI2C_TIMINGR_SDADEL_Msk              /*!< Data hold time                */\n#define FMPI2C_TIMINGR_SCLDEL_Pos       (20U)\n#define FMPI2C_TIMINGR_SCLDEL_Msk       (0xFUL << FMPI2C_TIMINGR_SCLDEL_Pos)    /*!< 0x00F00000 */\n#define FMPI2C_TIMINGR_SCLDEL           FMPI2C_TIMINGR_SCLDEL_Msk              /*!< Data setup time               */\n#define FMPI2C_TIMINGR_PRESC_Pos        (28U)\n#define FMPI2C_TIMINGR_PRESC_Msk        (0xFUL << FMPI2C_TIMINGR_PRESC_Pos)     /*!< 0xF0000000 */\n#define FMPI2C_TIMINGR_PRESC            FMPI2C_TIMINGR_PRESC_Msk               /*!< Timings prescaler             */\n\n/******************* Bit definition for I2C_TIMEOUTR register *******************/\n#define FMPI2C_TIMEOUTR_TIMEOUTA_Pos    (0U)\n#define FMPI2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */\n#define FMPI2C_TIMEOUTR_TIMEOUTA        FMPI2C_TIMEOUTR_TIMEOUTA_Msk           /*!< Bus timeout A                 */\n#define FMPI2C_TIMEOUTR_TIDLE_Pos       (12U)\n#define FMPI2C_TIMEOUTR_TIDLE_Msk       (0x1UL << FMPI2C_TIMEOUTR_TIDLE_Pos)    /*!< 0x00001000 */\n#define FMPI2C_TIMEOUTR_TIDLE           FMPI2C_TIMEOUTR_TIDLE_Msk              /*!< Idle clock timeout detection  */\n#define FMPI2C_TIMEOUTR_TIMOUTEN_Pos    (15U)\n#define FMPI2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */\n#define FMPI2C_TIMEOUTR_TIMOUTEN        FMPI2C_TIMEOUTR_TIMOUTEN_Msk           /*!< Clock timeout enable          */\n#define FMPI2C_TIMEOUTR_TIMEOUTB_Pos    (16U)\n#define FMPI2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */\n#define FMPI2C_TIMEOUTR_TIMEOUTB        FMPI2C_TIMEOUTR_TIMEOUTB_Msk           /*!< Bus timeout B                 */\n#define FMPI2C_TIMEOUTR_TEXTEN_Pos      (31U)\n#define FMPI2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << FMPI2C_TIMEOUTR_TEXTEN_Pos)   /*!< 0x80000000 */\n#define FMPI2C_TIMEOUTR_TEXTEN          FMPI2C_TIMEOUTR_TEXTEN_Msk             /*!< Extended clock timeout enable */\n\n/******************  Bit definition for I2C_ISR register  *********************/\n#define FMPI2C_ISR_TXE_Pos              (0U)\n#define FMPI2C_ISR_TXE_Msk              (0x1UL << FMPI2C_ISR_TXE_Pos)           /*!< 0x00000001 */\n#define FMPI2C_ISR_TXE                  FMPI2C_ISR_TXE_Msk                     /*!< Transmit data register empty     */\n#define FMPI2C_ISR_TXIS_Pos             (1U)\n#define FMPI2C_ISR_TXIS_Msk             (0x1UL << FMPI2C_ISR_TXIS_Pos)          /*!< 0x00000002 */\n#define FMPI2C_ISR_TXIS                 FMPI2C_ISR_TXIS_Msk                    /*!< Transmit interrupt status        */\n#define FMPI2C_ISR_RXNE_Pos             (2U)\n#define FMPI2C_ISR_RXNE_Msk             (0x1UL << FMPI2C_ISR_RXNE_Pos)          /*!< 0x00000004 */\n#define FMPI2C_ISR_RXNE                 FMPI2C_ISR_RXNE_Msk                    /*!< Receive data register not empty  */\n#define FMPI2C_ISR_ADDR_Pos             (3U)\n#define FMPI2C_ISR_ADDR_Msk             (0x1UL << FMPI2C_ISR_ADDR_Pos)          /*!< 0x00000008 */\n#define FMPI2C_ISR_ADDR                 FMPI2C_ISR_ADDR_Msk                    /*!< Address matched (slave mode)     */\n#define FMPI2C_ISR_NACKF_Pos            (4U)\n#define FMPI2C_ISR_NACKF_Msk            (0x1UL << FMPI2C_ISR_NACKF_Pos)         /*!< 0x00000010 */\n#define FMPI2C_ISR_NACKF                FMPI2C_ISR_NACKF_Msk                   /*!< NACK received flag               */\n#define FMPI2C_ISR_STOPF_Pos            (5U)\n#define FMPI2C_ISR_STOPF_Msk            (0x1UL << FMPI2C_ISR_STOPF_Pos)         /*!< 0x00000020 */\n#define FMPI2C_ISR_STOPF                FMPI2C_ISR_STOPF_Msk                   /*!< STOP detection flag              */\n#define FMPI2C_ISR_TC_Pos               (6U)\n#define FMPI2C_ISR_TC_Msk               (0x1UL << FMPI2C_ISR_TC_Pos)            /*!< 0x00000040 */\n#define FMPI2C_ISR_TC                   FMPI2C_ISR_TC_Msk                      /*!< Transfer complete (master mode)  */\n#define FMPI2C_ISR_TCR_Pos              (7U)\n#define FMPI2C_ISR_TCR_Msk              (0x1UL << FMPI2C_ISR_TCR_Pos)           /*!< 0x00000080 */\n#define FMPI2C_ISR_TCR                  FMPI2C_ISR_TCR_Msk                     /*!< Transfer complete reload         */\n#define FMPI2C_ISR_BERR_Pos             (8U)\n#define FMPI2C_ISR_BERR_Msk             (0x1UL << FMPI2C_ISR_BERR_Pos)          /*!< 0x00000100 */\n#define FMPI2C_ISR_BERR                 FMPI2C_ISR_BERR_Msk                    /*!< Bus error                        */\n#define FMPI2C_ISR_ARLO_Pos             (9U)\n#define FMPI2C_ISR_ARLO_Msk             (0x1UL << FMPI2C_ISR_ARLO_Pos)          /*!< 0x00000200 */\n#define FMPI2C_ISR_ARLO                 FMPI2C_ISR_ARLO_Msk                    /*!< Arbitration lost                 */\n#define FMPI2C_ISR_OVR_Pos              (10U)\n#define FMPI2C_ISR_OVR_Msk              (0x1UL << FMPI2C_ISR_OVR_Pos)           /*!< 0x00000400 */\n#define FMPI2C_ISR_OVR                  FMPI2C_ISR_OVR_Msk                     /*!< Overrun/Underrun                 */\n#define FMPI2C_ISR_PECERR_Pos           (11U)\n#define FMPI2C_ISR_PECERR_Msk           (0x1UL << FMPI2C_ISR_PECERR_Pos)        /*!< 0x00000800 */\n#define FMPI2C_ISR_PECERR               FMPI2C_ISR_PECERR_Msk                  /*!< PEC error in reception           */\n#define FMPI2C_ISR_TIMEOUT_Pos          (12U)\n#define FMPI2C_ISR_TIMEOUT_Msk          (0x1UL << FMPI2C_ISR_TIMEOUT_Pos)       /*!< 0x00001000 */\n#define FMPI2C_ISR_TIMEOUT              FMPI2C_ISR_TIMEOUT_Msk                 /*!< Timeout or Tlow detection flag   */\n#define FMPI2C_ISR_ALERT_Pos            (13U)\n#define FMPI2C_ISR_ALERT_Msk            (0x1UL << FMPI2C_ISR_ALERT_Pos)         /*!< 0x00002000 */\n#define FMPI2C_ISR_ALERT                FMPI2C_ISR_ALERT_Msk                   /*!< SMBus alert                      */\n#define FMPI2C_ISR_BUSY_Pos             (15U)\n#define FMPI2C_ISR_BUSY_Msk             (0x1UL << FMPI2C_ISR_BUSY_Pos)          /*!< 0x00008000 */\n#define FMPI2C_ISR_BUSY                 FMPI2C_ISR_BUSY_Msk                    /*!< Bus busy                         */\n#define FMPI2C_ISR_DIR_Pos              (16U)\n#define FMPI2C_ISR_DIR_Msk              (0x1UL << FMPI2C_ISR_DIR_Pos)           /*!< 0x00010000 */\n#define FMPI2C_ISR_DIR                  FMPI2C_ISR_DIR_Msk                     /*!< Transfer direction (slave mode)  */\n#define FMPI2C_ISR_ADDCODE_Pos          (17U)\n#define FMPI2C_ISR_ADDCODE_Msk          (0x7FUL << FMPI2C_ISR_ADDCODE_Pos)      /*!< 0x00FE0000 */\n#define FMPI2C_ISR_ADDCODE              FMPI2C_ISR_ADDCODE_Msk                 /*!< Address match code (slave mode)  */\n\n/******************  Bit definition for I2C_ICR register  *********************/\n#define FMPI2C_ICR_ADDRCF_Pos           (3U)\n#define FMPI2C_ICR_ADDRCF_Msk           (0x1UL << FMPI2C_ICR_ADDRCF_Pos)        /*!< 0x00000008 */\n#define FMPI2C_ICR_ADDRCF               FMPI2C_ICR_ADDRCF_Msk                  /*!< Address matched clear flag  */\n#define FMPI2C_ICR_NACKCF_Pos           (4U)\n#define FMPI2C_ICR_NACKCF_Msk           (0x1UL << FMPI2C_ICR_NACKCF_Pos)        /*!< 0x00000010 */\n#define FMPI2C_ICR_NACKCF               FMPI2C_ICR_NACKCF_Msk                  /*!< NACK clear flag             */\n#define FMPI2C_ICR_STOPCF_Pos           (5U)\n#define FMPI2C_ICR_STOPCF_Msk           (0x1UL << FMPI2C_ICR_STOPCF_Pos)        /*!< 0x00000020 */\n#define FMPI2C_ICR_STOPCF               FMPI2C_ICR_STOPCF_Msk                  /*!< STOP detection clear flag   */\n#define FMPI2C_ICR_BERRCF_Pos           (8U)\n#define FMPI2C_ICR_BERRCF_Msk           (0x1UL << FMPI2C_ICR_BERRCF_Pos)        /*!< 0x00000100 */\n#define FMPI2C_ICR_BERRCF               FMPI2C_ICR_BERRCF_Msk                  /*!< Bus error clear flag        */\n#define FMPI2C_ICR_ARLOCF_Pos           (9U)\n#define FMPI2C_ICR_ARLOCF_Msk           (0x1UL << FMPI2C_ICR_ARLOCF_Pos)        /*!< 0x00000200 */\n#define FMPI2C_ICR_ARLOCF               FMPI2C_ICR_ARLOCF_Msk                  /*!< Arbitration lost clear flag */\n#define FMPI2C_ICR_OVRCF_Pos            (10U)\n#define FMPI2C_ICR_OVRCF_Msk            (0x1UL << FMPI2C_ICR_OVRCF_Pos)         /*!< 0x00000400 */\n#define FMPI2C_ICR_OVRCF                FMPI2C_ICR_OVRCF_Msk                   /*!< Overrun/Underrun clear flag */\n#define FMPI2C_ICR_PECCF_Pos            (11U)\n#define FMPI2C_ICR_PECCF_Msk            (0x1UL << FMPI2C_ICR_PECCF_Pos)         /*!< 0x00000800 */\n#define FMPI2C_ICR_PECCF                FMPI2C_ICR_PECCF_Msk                   /*!< PAC error clear flag        */\n#define FMPI2C_ICR_TIMOUTCF_Pos         (12U)\n#define FMPI2C_ICR_TIMOUTCF_Msk         (0x1UL << FMPI2C_ICR_TIMOUTCF_Pos)      /*!< 0x00001000 */\n#define FMPI2C_ICR_TIMOUTCF             FMPI2C_ICR_TIMOUTCF_Msk                /*!< Timeout clear flag          */\n#define FMPI2C_ICR_ALERTCF_Pos          (13U)\n#define FMPI2C_ICR_ALERTCF_Msk          (0x1UL << FMPI2C_ICR_ALERTCF_Pos)       /*!< 0x00002000 */\n#define FMPI2C_ICR_ALERTCF              FMPI2C_ICR_ALERTCF_Msk                 /*!< Alert clear flag            */\n\n/******************  Bit definition for I2C_PECR register  *********************/\n#define FMPI2C_PECR_PEC_Pos             (0U)\n#define FMPI2C_PECR_PEC_Msk             (0xFFUL << FMPI2C_PECR_PEC_Pos)         /*!< 0x000000FF */\n#define FMPI2C_PECR_PEC                 FMPI2C_PECR_PEC_Msk                    /*!< PEC register */\n\n/******************  Bit definition for I2C_RXDR register  *********************/\n#define FMPI2C_RXDR_RXDATA_Pos          (0U)\n#define FMPI2C_RXDR_RXDATA_Msk          (0xFFUL << FMPI2C_RXDR_RXDATA_Pos)      /*!< 0x000000FF */\n#define FMPI2C_RXDR_RXDATA              FMPI2C_RXDR_RXDATA_Msk                 /*!< 8-bit receive data */\n\n/******************  Bit definition for I2C_TXDR register  *********************/\n#define FMPI2C_TXDR_TXDATA_Pos          (0U)\n#define FMPI2C_TXDR_TXDATA_Msk          (0xFFUL << FMPI2C_TXDR_TXDATA_Pos)      /*!< 0x000000FF */\n#define FMPI2C_TXDR_TXDATA              FMPI2C_TXDR_TXDATA_Msk                 /*!< 8-bit transmit data */\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Independent WATCHDOG                             */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define IWDG_KR_KEY_Pos     (0U)\n#define IWDG_KR_KEY_Msk     (0xFFFFUL << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */\n#define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */\n\n/*******************  Bit definition for IWDG_PR register  ********************/\n#define IWDG_PR_PR_Pos      (0U)\n#define IWDG_PR_PR_Msk      (0x7UL << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */\n#define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */\n#define IWDG_PR_PR_0        (0x1UL << IWDG_PR_PR_Pos)                           /*!< 0x01 */\n#define IWDG_PR_PR_1        (0x2UL << IWDG_PR_PR_Pos)                           /*!< 0x02 */\n#define IWDG_PR_PR_2        (0x4UL << IWDG_PR_PR_Pos)                           /*!< 0x04 */\n\n/*******************  Bit definition for IWDG_RLR register  *******************/\n#define IWDG_RLR_RL_Pos     (0U)\n#define IWDG_RLR_RL_Msk     (0xFFFUL << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */\n#define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */\n\n/*******************  Bit definition for IWDG_SR register  ********************/\n#define IWDG_SR_PVU_Pos     (0U)\n#define IWDG_SR_PVU_Msk     (0x1UL << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */\n#define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */\n#define IWDG_SR_RVU_Pos     (1U)\n#define IWDG_SR_RVU_Msk     (0x1UL << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */\n#define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                             Power Control                                  */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for PWR_CR register  ********************/\n#define PWR_CR_LPDS_Pos        (0U)\n#define PWR_CR_LPDS_Msk        (0x1UL << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */\n#define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */\n#define PWR_CR_PDDS_Pos        (1U)\n#define PWR_CR_PDDS_Msk        (0x1UL << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */\n#define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */\n#define PWR_CR_CWUF_Pos        (2U)\n#define PWR_CR_CWUF_Msk        (0x1UL << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */\n#define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */\n#define PWR_CR_CSBF_Pos        (3U)\n#define PWR_CR_CSBF_Msk        (0x1UL << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */\n#define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */\n#define PWR_CR_PVDE_Pos        (4U)\n#define PWR_CR_PVDE_Msk        (0x1UL << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */\n#define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */\n\n#define PWR_CR_PLS_Pos         (5U)\n#define PWR_CR_PLS_Msk         (0x7UL << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */\n#define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */\n#define PWR_CR_PLS_0           (0x1UL << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */\n#define PWR_CR_PLS_1           (0x2UL << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */\n#define PWR_CR_PLS_2           (0x4UL << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */\n\n/*!< PVD level configuration */\n#define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */\n#define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */\n#define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */\n#define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */\n#define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */\n#define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */\n#define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */\n#define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */\n#define PWR_CR_DBP_Pos         (8U)\n#define PWR_CR_DBP_Msk         (0x1UL << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */\n#define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */\n#define PWR_CR_FPDS_Pos        (9U)\n#define PWR_CR_FPDS_Msk        (0x1UL << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */\n#define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */\n#define PWR_CR_LPLVDS_Pos      (10U)\n#define PWR_CR_LPLVDS_Msk      (0x1UL << PWR_CR_LPLVDS_Pos)                     /*!< 0x00000400 */\n#define PWR_CR_LPLVDS          PWR_CR_LPLVDS_Msk                               /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */\n#define PWR_CR_MRLVDS_Pos      (11U)\n#define PWR_CR_MRLVDS_Msk      (0x1UL << PWR_CR_MRLVDS_Pos)                     /*!< 0x00000800 */\n#define PWR_CR_MRLVDS          PWR_CR_MRLVDS_Msk                               /*!< Main Regulator Low Voltage in Deep Sleep mode              */\n#define PWR_CR_ADCDC1_Pos      (13U)\n#define PWR_CR_ADCDC1_Msk      (0x1UL << PWR_CR_ADCDC1_Pos)                     /*!< 0x00002000 */\n#define PWR_CR_ADCDC1          PWR_CR_ADCDC1_Msk                               /*!< Refer to AN4073 on how to use this bit                     */\n#define PWR_CR_VOS_Pos         (14U)\n#define PWR_CR_VOS_Msk         (0x3UL << PWR_CR_VOS_Pos)                        /*!< 0x0000C000 */\n#define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\n#define PWR_CR_VOS_0           0x00004000U                                     /*!< Bit 0 */\n#define PWR_CR_VOS_1           0x00008000U                                     /*!< Bit 1 */\n#define PWR_CR_FMSSR_Pos       (20U)\n#define PWR_CR_FMSSR_Msk       (0x1UL << PWR_CR_FMSSR_Pos)                      /*!< 0x00100000 */\n#define PWR_CR_FMSSR           PWR_CR_FMSSR_Msk                                /*!< Flash Memory Sleep System Run        */\n#define PWR_CR_FISSR_Pos       (21U)\n#define PWR_CR_FISSR_Msk       (0x1UL << PWR_CR_FISSR_Pos)                      /*!< 0x00200000 */\n#define PWR_CR_FISSR           PWR_CR_FISSR_Msk                                /*!< Flash Interface Stop while System Run */\n\n\n/*******************  Bit definition for PWR_CSR register  ********************/\n#define PWR_CSR_WUF_Pos        (0U)\n#define PWR_CSR_WUF_Msk        (0x1UL << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */\n#define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */\n#define PWR_CSR_SBF_Pos        (1U)\n#define PWR_CSR_SBF_Msk        (0x1UL << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */\n#define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */\n#define PWR_CSR_PVDO_Pos       (2U)\n#define PWR_CSR_PVDO_Msk       (0x1UL << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */\n#define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */\n#define PWR_CSR_BRR_Pos        (3U)\n#define PWR_CSR_BRR_Msk        (0x1UL << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */\n#define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */\n#define PWR_CSR_EWUP3_Pos      (6U)\n#define PWR_CSR_EWUP3_Msk      (0x1UL << PWR_CSR_EWUP1_Pos)                     /*!< 0x00000040 */\n#define PWR_CSR_EWUP3          PWR_CSR_EWUP3_Msk                               /*!< Enable WKUP pin 3                                */\n#define PWR_CSR_EWUP2_Pos      (7U)\n#define PWR_CSR_EWUP2_Msk      (0x1UL << PWR_CSR_EWUP2_Pos)                     /*!< 0x00000080 */\n#define PWR_CSR_EWUP2          PWR_CSR_EWUP2_Msk                               /*!< Enable WKUP pin 2                                */\n#define PWR_CSR_EWUP1_Pos      (8U)\n#define PWR_CSR_EWUP1_Msk      (0x1UL << PWR_CSR_EWUP1_Pos)                     /*!< 0x00000100 */\n#define PWR_CSR_EWUP1          PWR_CSR_EWUP1_Msk                               /*!< Enable WKUP pin 1                                */\n#define PWR_CSR_BRE_Pos        (9U)\n#define PWR_CSR_BRE_Msk        (0x1UL << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */\n#define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */\n#define PWR_CSR_VOSRDY_Pos     (14U)\n#define PWR_CSR_VOSRDY_Msk     (0x1UL << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */\n#define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    QUADSPI                                 */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define  QSPI1_V2_1L                                                           /*!< QSPI Virtual Version             */\n\n/*****************  Bit definition for QUADSPI_CR register  *******************/\n#define QUADSPI_CR_EN_Pos                (0U)\n#define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)           /*!< 0x00000001 */\n#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable                             */\n#define QUADSPI_CR_ABORT_Pos             (1U)\n#define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)        /*!< 0x00000002 */\n#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request                      */\n#define QUADSPI_CR_DMAEN_Pos             (2U)\n#define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)        /*!< 0x00000004 */\n#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable                         */\n#define QUADSPI_CR_TCEN_Pos              (3U)\n#define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)         /*!< 0x00000008 */\n#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable             */\n#define QUADSPI_CR_SSHIFT_Pos            (4U)\n#define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)       /*!< 0x00000010 */\n#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift                */\n#define QUADSPI_CR_DFM_Pos               (6U)\n#define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)          /*!< 0x00000040 */\n#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode                    */\n#define QUADSPI_CR_FSEL_Pos              (7U)\n#define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)         /*!< 0x00000080 */\n#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select                       */\n#define QUADSPI_CR_FTHRES_Pos            (8U)\n#define QUADSPI_CR_FTHRES_Msk            (0x1FUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */\n#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level             */\n#define QUADSPI_CR_FTHRES_0              (0x01UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */\n#define QUADSPI_CR_FTHRES_1              (0x02UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */\n#define QUADSPI_CR_FTHRES_2              (0x04UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */\n#define QUADSPI_CR_FTHRES_3              (0x08UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */\n#define QUADSPI_CR_FTHRES_4              (0x10UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001000 */\n#define QUADSPI_CR_TEIE_Pos              (16U)\n#define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)         /*!< 0x00010000 */\n#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable    */\n#define QUADSPI_CR_TCIE_Pos              (17U)\n#define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)         /*!< 0x00020000 */\n#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */\n#define QUADSPI_CR_FTIE_Pos              (18U)\n#define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)         /*!< 0x00040000 */\n#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable    */\n#define QUADSPI_CR_SMIE_Pos              (19U)\n#define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)         /*!< 0x00080000 */\n#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable      */\n#define QUADSPI_CR_TOIE_Pos              (20U)\n#define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)         /*!< 0x00100000 */\n#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable           */\n#define QUADSPI_CR_APMS_Pos              (22U)\n#define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)         /*!< 0x00400000 */\n#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1                              */\n#define QUADSPI_CR_PMM_Pos               (23U)\n#define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)          /*!< 0x00800000 */\n#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode                 */\n#define QUADSPI_CR_PRESCALER_Pos         (24U)\n#define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0xFF000000 */\n#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler     */\n#define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x01000000 */\n#define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x02000000 */\n#define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x04000000 */\n#define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x08000000 */\n#define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x10000000 */\n#define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x20000000 */\n#define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x40000000 */\n#define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x80000000 */\n\n/*****************  Bit definition for QUADSPI_DCR register  ******************/\n#define QUADSPI_DCR_CKMODE_Pos           (0U)\n#define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)      /*!< 0x00000001 */\n#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3                 */\n#define QUADSPI_DCR_CSHT_Pos             (8U)\n#define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000700 */\n#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */\n#define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000100 */\n#define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000200 */\n#define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000400 */\n#define QUADSPI_DCR_FSIZE_Pos            (16U)\n#define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x001F0000 */\n#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size          */\n#define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00010000 */\n#define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00020000 */\n#define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00040000 */\n#define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00080000 */\n#define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00100000 */\n\n/******************  Bit definition for QUADSPI_SR register  *******************/\n#define QUADSPI_SR_TEF_Pos               (0U)\n#define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)          /*!< 0x00000001 */\n#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag    */\n#define QUADSPI_SR_TCF_Pos               (1U)\n#define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)          /*!< 0x00000002 */\n#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */\n#define QUADSPI_SR_FTF_Pos               (2U)\n#define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)          /*!< 0x00000004 */\n#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag    */\n#define QUADSPI_SR_SMF_Pos               (3U)\n#define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)          /*!< 0x00000008 */\n#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag      */\n#define QUADSPI_SR_TOF_Pos               (4U)\n#define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)          /*!< 0x00000010 */\n#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag           */\n#define QUADSPI_SR_BUSY_Pos              (5U)\n#define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)         /*!< 0x00000020 */\n#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy                   */\n#define QUADSPI_SR_FLEVEL_Pos            (8U)\n#define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00003F00 */\n#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag    */\n#define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000100 */\n#define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000200 */\n#define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000400 */\n#define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000800 */\n#define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00001000 */\n#define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00002000 */\n\n/******************  Bit definition for QUADSPI_FCR register  ******************/\n#define QUADSPI_FCR_CTEF_Pos             (0U)\n#define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)        /*!< 0x00000001 */\n#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag    */\n#define QUADSPI_FCR_CTCF_Pos             (1U)\n#define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)        /*!< 0x00000002 */\n#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */\n#define QUADSPI_FCR_CSMF_Pos             (3U)\n#define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)        /*!< 0x00000008 */\n#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag      */\n#define QUADSPI_FCR_CTOF_Pos             (4U)\n#define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)        /*!< 0x00000010 */\n#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag           */\n\n/******************  Bit definition for QUADSPI_DLR register  ******************/\n#define QUADSPI_DLR_DL_Pos               (0U)\n#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)   /*!< 0xFFFFFFFF */\n#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */\n\n/******************  Bit definition for QUADSPI_CCR register  ******************/\n#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)\n#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */\n#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk           /*!< INSTRUCTION[7:0]: Instruction         */\n#define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */\n#define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */\n#define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */\n#define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */\n#define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */\n#define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */\n#define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */\n#define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */\n#define QUADSPI_CCR_IMODE_Pos            (8U)\n#define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000300 */\n#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                 /*!< IMODE[1:0]: Instruction Mode          */\n#define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000100 */\n#define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000200 */\n#define QUADSPI_CCR_ADMODE_Pos           (10U)\n#define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000C00 */\n#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                /*!< ADMODE[1:0]: Address Mode             */\n#define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000400 */\n#define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000800 */\n#define QUADSPI_CCR_ADSIZE_Pos           (12U)\n#define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00003000 */\n#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                /*!< ADSIZE[1:0]: Address Size             */\n#define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00001000 */\n#define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00002000 */\n#define QUADSPI_CCR_ABMODE_Pos           (14U)\n#define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x0000C000 */\n#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                /*!< ABMODE[1:0]: Alternate Bytes Mode     */\n#define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00004000 */\n#define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00008000 */\n#define QUADSPI_CCR_ABSIZE_Pos           (16U)\n#define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00030000 */\n#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                /*!< ABSIZE[1:0]: Instruction Mode         */\n#define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00010000 */\n#define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00020000 */\n#define QUADSPI_CCR_DCYC_Pos             (18U)\n#define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x007C0000 */\n#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                  /*!< DCYC[4:0]: Dummy Cycles               */\n#define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00040000 */\n#define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00080000 */\n#define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00100000 */\n#define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00200000 */\n#define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00400000 */\n#define QUADSPI_CCR_DMODE_Pos            (24U)\n#define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x03000000 */\n#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                 /*!< DMODE[1:0]: Data Mode                 */\n#define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x01000000 */\n#define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x02000000 */\n#define QUADSPI_CCR_FMODE_Pos            (26U)\n#define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x0C000000 */\n#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                 /*!< FMODE[1:0]: Functional Mode           */\n#define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x04000000 */\n#define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x08000000 */\n#define QUADSPI_CCR_SIOO_Pos             (28U)\n#define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)        /*!< 0x10000000 */\n#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                  /*!< SIOO: Send Instruction Only Once Mode */\n#define QUADSPI_CCR_DHHC_Pos             (30U)\n#define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)        /*!< 0x40000000 */\n#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                  /*!< DHHC: Delay Half Hclk Cycle           */\n#define QUADSPI_CCR_DDRM_Pos             (31U)\n#define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)        /*!< 0x80000000 */\n#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                  /*!< DDRM: Double Data Rate Mode           */\n/******************  Bit definition for QUADSPI_AR register  *******************/\n#define QUADSPI_AR_ADDRESS_Pos           (0U)\n#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address                */\n\n/******************  Bit definition for QUADSPI_ABR register  ******************/\n#define QUADSPI_ABR_ALTERNATE_Pos        (0U)\n#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes      */\n\n/******************  Bit definition for QUADSPI_DR register  *******************/\n#define QUADSPI_DR_DATA_Pos              (0U)\n#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)  /*!< 0xFFFFFFFF */\n#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data                      */\n\n/******************  Bit definition for QUADSPI_PSMKR register  ****************/\n#define QUADSPI_PSMKR_MASK_Pos           (0U)\n#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask               */\n\n/******************  Bit definition for QUADSPI_PSMAR register  ****************/\n#define QUADSPI_PSMAR_MATCH_Pos          (0U)\n#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match             */\n\n/******************  Bit definition for QUADSPI_PIR register  *****************/\n#define QUADSPI_PIR_INTERVAL_Pos         (0U)\n#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */\n#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval      */\n\n/******************  Bit definition for QUADSPI_LPTR register  *****************/\n#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)\n#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */\n#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period         */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Reset and Clock Control                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for RCC_CR register  ********************/\n#define RCC_CR_HSION_Pos                   (0U)\n#define RCC_CR_HSION_Msk                   (0x1UL << RCC_CR_HSION_Pos)          /*!< 0x00000001 */\n#define RCC_CR_HSION                       RCC_CR_HSION_Msk\n#define RCC_CR_HSIRDY_Pos                  (1U)\n#define RCC_CR_HSIRDY_Msk                  (0x1UL << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */\n#define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk\n\n#define RCC_CR_HSITRIM_Pos                 (3U)\n#define RCC_CR_HSITRIM_Msk                 (0x1FUL << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */\n#define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk\n#define RCC_CR_HSITRIM_0                   (0x01UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */\n#define RCC_CR_HSITRIM_1                   (0x02UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */\n#define RCC_CR_HSITRIM_2                   (0x04UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */\n#define RCC_CR_HSITRIM_3                   (0x08UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */\n#define RCC_CR_HSITRIM_4                   (0x10UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */\n\n#define RCC_CR_HSICAL_Pos                  (8U)\n#define RCC_CR_HSICAL_Msk                  (0xFFUL << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */\n#define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk\n#define RCC_CR_HSICAL_0                    (0x01UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */\n#define RCC_CR_HSICAL_1                    (0x02UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */\n#define RCC_CR_HSICAL_2                    (0x04UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */\n#define RCC_CR_HSICAL_3                    (0x08UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */\n#define RCC_CR_HSICAL_4                    (0x10UL << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */\n#define RCC_CR_HSICAL_5                    (0x20UL << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */\n#define RCC_CR_HSICAL_6                    (0x40UL << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */\n#define RCC_CR_HSICAL_7                    (0x80UL << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */\n\n#define RCC_CR_HSEON_Pos                   (16U)\n#define RCC_CR_HSEON_Msk                   (0x1UL << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */\n#define RCC_CR_HSEON                       RCC_CR_HSEON_Msk\n#define RCC_CR_HSERDY_Pos                  (17U)\n#define RCC_CR_HSERDY_Msk                  (0x1UL << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */\n#define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk\n#define RCC_CR_HSEBYP_Pos                  (18U)\n#define RCC_CR_HSEBYP_Msk                  (0x1UL << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */\n#define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk\n#define RCC_CR_CSSON_Pos                   (19U)\n#define RCC_CR_CSSON_Msk                   (0x1UL << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */\n#define RCC_CR_CSSON                       RCC_CR_CSSON_Msk\n#define RCC_CR_PLLON_Pos                   (24U)\n#define RCC_CR_PLLON_Msk                   (0x1UL << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */\n#define RCC_CR_PLLON                       RCC_CR_PLLON_Msk\n#define RCC_CR_PLLRDY_Pos                  (25U)\n#define RCC_CR_PLLRDY_Msk                  (0x1UL << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */\n#define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_PLLI2S_SUPPORT                                                     /*!< Support PLLI2S oscillator */\n\n#define RCC_CR_PLLI2SON_Pos                (26U)\n#define RCC_CR_PLLI2SON_Msk                (0x1UL << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */\n#define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk\n#define RCC_CR_PLLI2SRDY_Pos               (27U)\n#define RCC_CR_PLLI2SRDY_Msk               (0x1UL << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */\n#define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk\n\n/********************  Bit definition for RCC_PLLCFGR register  ***************/\n#define RCC_PLLCFGR_PLLM_Pos               (0U)\n#define RCC_PLLCFGR_PLLM_Msk               (0x3FUL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */\n#define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk\n#define RCC_PLLCFGR_PLLM_0                 (0x01UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */\n#define RCC_PLLCFGR_PLLM_1                 (0x02UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */\n#define RCC_PLLCFGR_PLLM_2                 (0x04UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */\n#define RCC_PLLCFGR_PLLM_3                 (0x08UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */\n#define RCC_PLLCFGR_PLLM_4                 (0x10UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */\n#define RCC_PLLCFGR_PLLM_5                 (0x20UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */\n\n#define RCC_PLLCFGR_PLLN_Pos               (6U)\n#define RCC_PLLCFGR_PLLN_Msk               (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */\n#define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk\n#define RCC_PLLCFGR_PLLN_0                 (0x001UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */\n#define RCC_PLLCFGR_PLLN_1                 (0x002UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */\n#define RCC_PLLCFGR_PLLN_2                 (0x004UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */\n#define RCC_PLLCFGR_PLLN_3                 (0x008UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */\n#define RCC_PLLCFGR_PLLN_4                 (0x010UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */\n#define RCC_PLLCFGR_PLLN_5                 (0x020UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */\n#define RCC_PLLCFGR_PLLN_6                 (0x040UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */\n#define RCC_PLLCFGR_PLLN_7                 (0x080UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */\n#define RCC_PLLCFGR_PLLN_8                 (0x100UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */\n\n#define RCC_PLLCFGR_PLLP_Pos               (16U)\n#define RCC_PLLCFGR_PLLP_Msk               (0x3UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */\n#define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk\n#define RCC_PLLCFGR_PLLP_0                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */\n#define RCC_PLLCFGR_PLLP_1                 (0x2UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */\n\n#define RCC_PLLCFGR_PLLSRC_Pos             (22U)\n#define RCC_PLLCFGR_PLLSRC_Msk             (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk\n#define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)\n#define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk\n#define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U\n\n#define RCC_PLLCFGR_PLLQ_Pos               (24U)\n#define RCC_PLLCFGR_PLLQ_Msk               (0xFUL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */\n#define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk\n#define RCC_PLLCFGR_PLLQ_0                 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */\n#define RCC_PLLCFGR_PLLQ_1                 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */\n#define RCC_PLLCFGR_PLLQ_2                 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */\n#define RCC_PLLCFGR_PLLQ_3                 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_PLLR_I2S_CLKSOURCE_SUPPORT     /*!< Support PLLR clock as I2S clock source */\n\n#define RCC_PLLCFGR_PLLR_Pos               (28U)\n#define RCC_PLLCFGR_PLLR_Msk               (0x7UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x70000000 */\n#define RCC_PLLCFGR_PLLR                   RCC_PLLCFGR_PLLR_Msk\n#define RCC_PLLCFGR_PLLR_0                 (0x1UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x10000000 */\n#define RCC_PLLCFGR_PLLR_1                 (0x2UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x20000000 */\n#define RCC_PLLCFGR_PLLR_2                 (0x4UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x40000000 */\n\n/********************  Bit definition for RCC_CFGR register  ******************/\n/*!< SW configuration */\n#define RCC_CFGR_SW_Pos                    (0U)\n#define RCC_CFGR_SW_Msk                    (0x3UL << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */\n#define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */\n#define RCC_CFGR_SW_0                      (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */\n#define RCC_CFGR_SW_1                      (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */\n\n#define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */\n#define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */\n#define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */\n\n/*!< SWS configuration */\n#define RCC_CFGR_SWS_Pos                   (2U)\n#define RCC_CFGR_SWS_Msk                   (0x3UL << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */\n#define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */\n#define RCC_CFGR_SWS_0                     (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */\n#define RCC_CFGR_SWS_1                     (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */\n\n#define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */\n#define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */\n#define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */\n\n/*!< HPRE configuration */\n#define RCC_CFGR_HPRE_Pos                  (4U)\n#define RCC_CFGR_HPRE_Msk                  (0xFUL << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */\n#define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */\n#define RCC_CFGR_HPRE_0                    (0x1UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */\n#define RCC_CFGR_HPRE_1                    (0x2UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */\n#define RCC_CFGR_HPRE_2                    (0x4UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */\n#define RCC_CFGR_HPRE_3                    (0x8UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */\n\n#define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */\n#define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */\n#define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */\n#define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */\n#define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */\n#define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */\n#define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */\n#define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */\n#define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */\n\n/*!< PPRE1 configuration */\n#define RCC_CFGR_PPRE1_Pos                 (10U)\n#define RCC_CFGR_PPRE1_Msk                 (0x7UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */\n#define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */\n#define RCC_CFGR_PPRE1_0                   (0x1UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */\n#define RCC_CFGR_PPRE1_1                   (0x2UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */\n#define RCC_CFGR_PPRE1_2                   (0x4UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */\n\n#define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */\n\n/*!< PPRE2 configuration */\n#define RCC_CFGR_PPRE2_Pos                 (13U)\n#define RCC_CFGR_PPRE2_Msk                 (0x7UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */\n#define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */\n#define RCC_CFGR_PPRE2_0                   (0x1UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */\n#define RCC_CFGR_PPRE2_1                   (0x2UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */\n#define RCC_CFGR_PPRE2_2                   (0x4UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */\n\n#define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */\n\n/*!< RTCPRE configuration */\n#define RCC_CFGR_RTCPRE_Pos                (16U)\n#define RCC_CFGR_RTCPRE_Msk                (0x1FUL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */\n#define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk\n#define RCC_CFGR_RTCPRE_0                  (0x01UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */\n#define RCC_CFGR_RTCPRE_1                  (0x02UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */\n#define RCC_CFGR_RTCPRE_2                  (0x04UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */\n#define RCC_CFGR_RTCPRE_3                  (0x08UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */\n#define RCC_CFGR_RTCPRE_4                  (0x10UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */\n\n/*!< MCO1 configuration */\n#define RCC_CFGR_MCO1_Pos                  (21U)\n#define RCC_CFGR_MCO1_Msk                  (0x3UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */\n#define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk\n#define RCC_CFGR_MCO1_0                    (0x1UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */\n#define RCC_CFGR_MCO1_1                    (0x2UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */\n\n\n#define RCC_CFGR_MCO1PRE_Pos               (24U)\n#define RCC_CFGR_MCO1PRE_Msk               (0x7UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */\n#define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk\n#define RCC_CFGR_MCO1PRE_0                 (0x1UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */\n#define RCC_CFGR_MCO1PRE_1                 (0x2UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */\n#define RCC_CFGR_MCO1PRE_2                 (0x4UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */\n\n#define RCC_CFGR_MCO2PRE_Pos               (27U)\n#define RCC_CFGR_MCO2PRE_Msk               (0x7UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */\n#define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk\n#define RCC_CFGR_MCO2PRE_0                 (0x1UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */\n#define RCC_CFGR_MCO2PRE_1                 (0x2UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */\n#define RCC_CFGR_MCO2PRE_2                 (0x4UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */\n\n#define RCC_CFGR_MCO2_Pos                  (30U)\n#define RCC_CFGR_MCO2_Msk                  (0x3UL << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */\n#define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk\n#define RCC_CFGR_MCO2_0                    (0x1UL << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */\n#define RCC_CFGR_MCO2_1                    (0x2UL << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */\n\n/********************  Bit definition for RCC_CIR register  *******************/\n#define RCC_CIR_LSIRDYF_Pos                (0U)\n#define RCC_CIR_LSIRDYF_Msk                (0x1UL << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */\n#define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk\n#define RCC_CIR_LSERDYF_Pos                (1U)\n#define RCC_CIR_LSERDYF_Msk                (0x1UL << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */\n#define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk\n#define RCC_CIR_HSIRDYF_Pos                (2U)\n#define RCC_CIR_HSIRDYF_Msk                (0x1UL << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */\n#define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk\n#define RCC_CIR_HSERDYF_Pos                (3U)\n#define RCC_CIR_HSERDYF_Msk                (0x1UL << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */\n#define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk\n#define RCC_CIR_PLLRDYF_Pos                (4U)\n#define RCC_CIR_PLLRDYF_Msk                (0x1UL << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */\n#define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk\n#define RCC_CIR_PLLI2SRDYF_Pos             (5U)\n#define RCC_CIR_PLLI2SRDYF_Msk             (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */\n#define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk\n\n#define RCC_CIR_CSSF_Pos                   (7U)\n#define RCC_CIR_CSSF_Msk                   (0x1UL << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */\n#define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk\n#define RCC_CIR_LSIRDYIE_Pos               (8U)\n#define RCC_CIR_LSIRDYIE_Msk               (0x1UL << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */\n#define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk\n#define RCC_CIR_LSERDYIE_Pos               (9U)\n#define RCC_CIR_LSERDYIE_Msk               (0x1UL << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */\n#define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk\n#define RCC_CIR_HSIRDYIE_Pos               (10U)\n#define RCC_CIR_HSIRDYIE_Msk               (0x1UL << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */\n#define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk\n#define RCC_CIR_HSERDYIE_Pos               (11U)\n#define RCC_CIR_HSERDYIE_Msk               (0x1UL << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */\n#define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk\n#define RCC_CIR_PLLRDYIE_Pos               (12U)\n#define RCC_CIR_PLLRDYIE_Msk               (0x1UL << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */\n#define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk\n#define RCC_CIR_PLLI2SRDYIE_Pos            (13U)\n#define RCC_CIR_PLLI2SRDYIE_Msk            (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */\n#define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk\n\n#define RCC_CIR_LSIRDYC_Pos                (16U)\n#define RCC_CIR_LSIRDYC_Msk                (0x1UL << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */\n#define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk\n#define RCC_CIR_LSERDYC_Pos                (17U)\n#define RCC_CIR_LSERDYC_Msk                (0x1UL << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */\n#define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk\n#define RCC_CIR_HSIRDYC_Pos                (18U)\n#define RCC_CIR_HSIRDYC_Msk                (0x1UL << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */\n#define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk\n#define RCC_CIR_HSERDYC_Pos                (19U)\n#define RCC_CIR_HSERDYC_Msk                (0x1UL << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */\n#define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk\n#define RCC_CIR_PLLRDYC_Pos                (20U)\n#define RCC_CIR_PLLRDYC_Msk                (0x1UL << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */\n#define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk\n#define RCC_CIR_PLLI2SRDYC_Pos             (21U)\n#define RCC_CIR_PLLI2SRDYC_Msk             (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */\n#define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk\n\n#define RCC_CIR_CSSC_Pos                   (23U)\n#define RCC_CIR_CSSC_Msk                   (0x1UL << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */\n#define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk\n\n/********************  Bit definition for RCC_AHB1RSTR register  **************/\n#define RCC_AHB1RSTR_GPIOARST_Pos          (0U)\n#define RCC_AHB1RSTR_GPIOARST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */\n#define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk\n#define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)\n#define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */\n#define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk\n#define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)\n#define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */\n#define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk\n#define RCC_AHB1RSTR_GPIODRST_Pos          (3U)\n#define RCC_AHB1RSTR_GPIODRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */\n#define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk\n#define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)\n#define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk\n#define RCC_AHB1RSTR_CRCRST_Pos            (12U)\n#define RCC_AHB1RSTR_CRCRST_Msk            (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */\n#define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk\n#define RCC_AHB1RSTR_DMA1RST_Pos           (21U)\n#define RCC_AHB1RSTR_DMA1RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */\n#define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk\n#define RCC_AHB1RSTR_DMA2RST_Pos           (22U)\n#define RCC_AHB1RSTR_DMA2RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */\n#define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk\n\n/********************  Bit definition for RCC_AHB2RSTR register  **************/\n#define RCC_AHB2RSTR_RNGRST_Pos            (6U)\n#define RCC_AHB2RSTR_RNGRST_Msk            (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)   /*!< 0x00000040 */\n#define RCC_AHB2RSTR_RNGRST                RCC_AHB2RSTR_RNGRST_Msk\n#define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)\n#define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk\n/********************  Bit definition for RCC_AHB3RSTR register  **************/\n#define RCC_AHB3RSTR_FSMCRST_Pos           (0U)\n#define RCC_AHB3RSTR_FSMCRST_Msk           (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)  /*!< 0x00000001 */\n#define RCC_AHB3RSTR_FSMCRST               RCC_AHB3RSTR_FSMCRST_Msk\n#define RCC_AHB3RSTR_QSPIRST_Pos           (1U)\n#define RCC_AHB3RSTR_QSPIRST_Msk           (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)  /*!< 0x00000002 */\n#define RCC_AHB3RSTR_QSPIRST               RCC_AHB3RSTR_QSPIRST_Msk\n\n\n/********************  Bit definition for RCC_APB1RSTR register  **************/\n#define RCC_APB1RSTR_TIM2RST_Pos           (0U)\n#define RCC_APB1RSTR_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk\n#define RCC_APB1RSTR_TIM3RST_Pos           (1U)\n#define RCC_APB1RSTR_TIM3RST_Msk           (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk\n#define RCC_APB1RSTR_TIM4RST_Pos           (2U)\n#define RCC_APB1RSTR_TIM4RST_Msk           (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */\n#define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk\n#define RCC_APB1RSTR_TIM5RST_Pos           (3U)\n#define RCC_APB1RSTR_TIM5RST_Msk           (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */\n#define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk\n#define RCC_APB1RSTR_TIM6RST_Pos           (4U)\n#define RCC_APB1RSTR_TIM6RST_Msk           (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */\n#define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk\n#define RCC_APB1RSTR_TIM7RST_Pos           (5U)\n#define RCC_APB1RSTR_TIM7RST_Msk           (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */\n#define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk\n#define RCC_APB1RSTR_TIM12RST_Pos          (6U)\n#define RCC_APB1RSTR_TIM12RST_Msk          (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */\n#define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk\n#define RCC_APB1RSTR_TIM13RST_Pos          (7U)\n#define RCC_APB1RSTR_TIM13RST_Msk          (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */\n#define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk\n#define RCC_APB1RSTR_TIM14RST_Pos          (8U)\n#define RCC_APB1RSTR_TIM14RST_Msk          (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */\n#define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk\n#define RCC_APB1RSTR_WWDGRST_Pos           (11U)\n#define RCC_APB1RSTR_WWDGRST_Msk           (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */\n#define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk\n#define RCC_APB1RSTR_SPI2RST_Pos           (14U)\n#define RCC_APB1RSTR_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */\n#define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk\n#define RCC_APB1RSTR_SPI3RST_Pos           (15U)\n#define RCC_APB1RSTR_SPI3RST_Msk           (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */\n#define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk\n#define RCC_APB1RSTR_USART2RST_Pos         (17U)\n#define RCC_APB1RSTR_USART2RST_Msk         (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */\n#define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk\n#define RCC_APB1RSTR_USART3RST_Pos         (18U)\n#define RCC_APB1RSTR_USART3RST_Msk         (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */\n#define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk\n#define RCC_APB1RSTR_I2C1RST_Pos           (21U)\n#define RCC_APB1RSTR_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */\n#define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk\n#define RCC_APB1RSTR_I2C2RST_Pos           (22U)\n#define RCC_APB1RSTR_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */\n#define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk\n#define RCC_APB1RSTR_I2C3RST_Pos           (23U)\n#define RCC_APB1RSTR_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */\n#define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk\n#define RCC_APB1RSTR_FMPI2C1RST_Pos        (24U)\n#define RCC_APB1RSTR_FMPI2C1RST_Msk        (0x1UL << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */\n#define RCC_APB1RSTR_FMPI2C1RST            RCC_APB1RSTR_FMPI2C1RST_Msk\n#define RCC_APB1RSTR_CAN1RST_Pos           (25U)\n#define RCC_APB1RSTR_CAN1RST_Msk           (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */\n#define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk\n#define RCC_APB1RSTR_CAN2RST_Pos           (26U)\n#define RCC_APB1RSTR_CAN2RST_Msk           (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */\n#define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk\n#define RCC_APB1RSTR_PWRRST_Pos            (28U)\n#define RCC_APB1RSTR_PWRRST_Msk            (0x1UL << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */\n#define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk\n\n/********************  Bit definition for RCC_APB2RSTR register  **************/\n#define RCC_APB2RSTR_TIM1RST_Pos           (0U)\n#define RCC_APB2RSTR_TIM1RST_Msk           (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk\n#define RCC_APB2RSTR_TIM8RST_Pos           (1U)\n#define RCC_APB2RSTR_TIM8RST_Msk           (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk\n#define RCC_APB2RSTR_USART1RST_Pos         (4U)\n#define RCC_APB2RSTR_USART1RST_Msk         (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */\n#define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk\n#define RCC_APB2RSTR_USART6RST_Pos         (5U)\n#define RCC_APB2RSTR_USART6RST_Msk         (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */\n#define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk\n#define RCC_APB2RSTR_ADCRST_Pos            (8U)\n#define RCC_APB2RSTR_ADCRST_Msk            (0x1UL << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */\n#define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk\n#define RCC_APB2RSTR_SDIORST_Pos           (11U)\n#define RCC_APB2RSTR_SDIORST_Msk           (0x1UL << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */\n#define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk\n#define RCC_APB2RSTR_SPI1RST_Pos           (12U)\n#define RCC_APB2RSTR_SPI1RST_Msk           (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */\n#define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk\n#define RCC_APB2RSTR_SPI4RST_Pos           (13U)\n#define RCC_APB2RSTR_SPI4RST_Msk           (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)  /*!< 0x00002000 */\n#define RCC_APB2RSTR_SPI4RST               RCC_APB2RSTR_SPI4RST_Msk\n#define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)\n#define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */\n#define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk\n#define RCC_APB2RSTR_TIM9RST_Pos           (16U)\n#define RCC_APB2RSTR_TIM9RST_Msk           (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */\n#define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk\n#define RCC_APB2RSTR_TIM10RST_Pos          (17U)\n#define RCC_APB2RSTR_TIM10RST_Msk          (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */\n#define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk\n#define RCC_APB2RSTR_TIM11RST_Pos          (18U)\n#define RCC_APB2RSTR_TIM11RST_Msk          (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */\n#define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk\n#define RCC_APB2RSTR_SPI5RST_Pos           (20U)\n#define RCC_APB2RSTR_SPI5RST_Msk           (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)  /*!< 0x00100000 */\n#define RCC_APB2RSTR_SPI5RST               RCC_APB2RSTR_SPI5RST_Msk\n#define RCC_APB2RSTR_DFSDM1RST_Pos         (24U)\n#define RCC_APB2RSTR_DFSDM1RST_Msk         (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */\n#define RCC_APB2RSTR_DFSDM1RST             RCC_APB2RSTR_DFSDM1RST_Msk\n\n/********************  Bit definition for RCC_AHB1ENR register  ***************/\n#define RCC_AHB1ENR_GPIOAEN_Pos            (0U)\n#define RCC_AHB1ENR_GPIOAEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */\n#define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk\n#define RCC_AHB1ENR_GPIOBEN_Pos            (1U)\n#define RCC_AHB1ENR_GPIOBEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */\n#define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk\n#define RCC_AHB1ENR_GPIOCEN_Pos            (2U)\n#define RCC_AHB1ENR_GPIOCEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */\n#define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk\n#define RCC_AHB1ENR_GPIODEN_Pos            (3U)\n#define RCC_AHB1ENR_GPIODEN_Msk            (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */\n#define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk\n#define RCC_AHB1ENR_GPIOHEN_Pos            (7U)\n#define RCC_AHB1ENR_GPIOHEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk\n#define RCC_AHB1ENR_CRCEN_Pos              (12U)\n#define RCC_AHB1ENR_CRCEN_Msk              (0x1UL << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */\n#define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk\n#define RCC_AHB1ENR_DMA1EN_Pos             (21U)\n#define RCC_AHB1ENR_DMA1EN_Msk             (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */\n#define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk\n#define RCC_AHB1ENR_DMA2EN_Pos             (22U)\n#define RCC_AHB1ENR_DMA2EN_Msk             (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */\n#define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk\n/********************  Bit definition for RCC_AHB2ENR register  ***************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_AHB2_SUPPORT                   /*!< AHB2 Bus is supported */\n\n#define RCC_AHB2ENR_RNGEN_Pos              (6U)\n#define RCC_AHB2ENR_RNGEN_Msk              (0x1UL << RCC_AHB2ENR_RNGEN_Pos)     /*!< 0x00000040 */\n#define RCC_AHB2ENR_RNGEN                  RCC_AHB2ENR_RNGEN_Msk\n#define RCC_AHB2ENR_OTGFSEN_Pos            (7U)\n#define RCC_AHB2ENR_OTGFSEN_Msk            (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk\n\n/********************  Bit definition for RCC_AHB3ENR register  ***************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_AHB3_SUPPORT                   /*!< AHB3 Bus is supported */\n\n#define RCC_AHB3ENR_FSMCEN_Pos             (0U)\n#define RCC_AHB3ENR_FSMCEN_Msk             (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)    /*!< 0x00000001 */\n#define RCC_AHB3ENR_FSMCEN                 RCC_AHB3ENR_FSMCEN_Msk\n#define RCC_AHB3ENR_QSPIEN_Pos             (1U)\n#define RCC_AHB3ENR_QSPIEN_Msk             (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)    /*!< 0x00000002 */\n#define RCC_AHB3ENR_QSPIEN                 RCC_AHB3ENR_QSPIEN_Msk\n\n/********************  Bit definition for RCC_APB1ENR register  ***************/\n#define RCC_APB1ENR_TIM2EN_Pos             (0U)\n#define RCC_APB1ENR_TIM2EN_Msk             (0x1UL << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk\n#define RCC_APB1ENR_TIM3EN_Pos             (1U)\n#define RCC_APB1ENR_TIM3EN_Msk             (0x1UL << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk\n#define RCC_APB1ENR_TIM4EN_Pos             (2U)\n#define RCC_APB1ENR_TIM4EN_Msk             (0x1UL << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */\n#define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk\n#define RCC_APB1ENR_TIM5EN_Pos             (3U)\n#define RCC_APB1ENR_TIM5EN_Msk             (0x1UL << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */\n#define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk\n#define RCC_APB1ENR_TIM6EN_Pos             (4U)\n#define RCC_APB1ENR_TIM6EN_Msk             (0x1UL << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */\n#define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk\n#define RCC_APB1ENR_TIM7EN_Pos             (5U)\n#define RCC_APB1ENR_TIM7EN_Msk             (0x1UL << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */\n#define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk\n#define RCC_APB1ENR_TIM12EN_Pos            (6U)\n#define RCC_APB1ENR_TIM12EN_Msk            (0x1UL << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */\n#define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk\n#define RCC_APB1ENR_TIM13EN_Pos            (7U)\n#define RCC_APB1ENR_TIM13EN_Msk            (0x1UL << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */\n#define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk\n#define RCC_APB1ENR_TIM14EN_Pos            (8U)\n#define RCC_APB1ENR_TIM14EN_Msk            (0x1UL << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */\n#define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk\n#define RCC_APB1ENR_RTCAPBEN_Pos           (10U)\n#define RCC_APB1ENR_RTCAPBEN_Msk           (0x1UL << RCC_APB1ENR_RTCAPBEN_Pos)  /*!< 0x00000400 */\n#define RCC_APB1ENR_RTCAPBEN               RCC_APB1ENR_RTCAPBEN_Msk\n#define RCC_APB1ENR_WWDGEN_Pos             (11U)\n#define RCC_APB1ENR_WWDGEN_Msk             (0x1UL << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk\n#define RCC_APB1ENR_SPI2EN_Pos             (14U)\n#define RCC_APB1ENR_SPI2EN_Msk             (0x1UL << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */\n#define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk\n#define RCC_APB1ENR_SPI3EN_Pos             (15U)\n#define RCC_APB1ENR_SPI3EN_Msk             (0x1UL << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */\n#define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk\n#define RCC_APB1ENR_USART2EN_Pos           (17U)\n#define RCC_APB1ENR_USART2EN_Msk           (0x1UL << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */\n#define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk\n#define RCC_APB1ENR_USART3EN_Pos           (18U)\n#define RCC_APB1ENR_USART3EN_Msk           (0x1UL << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */\n#define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk\n#define RCC_APB1ENR_I2C1EN_Pos             (21U)\n#define RCC_APB1ENR_I2C1EN_Msk             (0x1UL << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */\n#define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk\n#define RCC_APB1ENR_I2C2EN_Pos             (22U)\n#define RCC_APB1ENR_I2C2EN_Msk             (0x1UL << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */\n#define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk\n#define RCC_APB1ENR_I2C3EN_Pos             (23U)\n#define RCC_APB1ENR_I2C3EN_Msk             (0x1UL << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */\n#define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk\n#define RCC_APB1ENR_FMPI2C1EN_Pos          (24U)\n#define RCC_APB1ENR_FMPI2C1EN_Msk          (0x1UL << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */\n#define RCC_APB1ENR_FMPI2C1EN              RCC_APB1ENR_FMPI2C1EN_Msk\n#define RCC_APB1ENR_CAN1EN_Pos             (25U)\n#define RCC_APB1ENR_CAN1EN_Msk             (0x1UL << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */\n#define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk\n#define RCC_APB1ENR_CAN2EN_Pos             (26U)\n#define RCC_APB1ENR_CAN2EN_Msk             (0x1UL << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */\n#define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk\n#define RCC_APB1ENR_PWREN_Pos              (28U)\n#define RCC_APB1ENR_PWREN_Msk              (0x1UL << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */\n#define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk\n\n/********************  Bit definition for RCC_APB2ENR register  ***************/\n#define RCC_APB2ENR_TIM1EN_Pos             (0U)\n#define RCC_APB2ENR_TIM1EN_Msk             (0x1UL << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk\n#define RCC_APB2ENR_TIM8EN_Pos             (1U)\n#define RCC_APB2ENR_TIM8EN_Msk             (0x1UL << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk\n#define RCC_APB2ENR_USART1EN_Pos           (4U)\n#define RCC_APB2ENR_USART1EN_Msk           (0x1UL << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */\n#define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk\n#define RCC_APB2ENR_USART6EN_Pos           (5U)\n#define RCC_APB2ENR_USART6EN_Msk           (0x1UL << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */\n#define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk\n#define RCC_APB2ENR_ADC1EN_Pos             (8U)\n#define RCC_APB2ENR_ADC1EN_Msk             (0x1UL << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */\n#define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk\n#define RCC_APB2ENR_SDIOEN_Pos             (11U)\n#define RCC_APB2ENR_SDIOEN_Msk             (0x1UL << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk\n#define RCC_APB2ENR_SPI1EN_Pos             (12U)\n#define RCC_APB2ENR_SPI1EN_Msk             (0x1UL << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */\n#define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk\n#define RCC_APB2ENR_SPI4EN_Pos             (13U)\n#define RCC_APB2ENR_SPI4EN_Msk             (0x1UL << RCC_APB2ENR_SPI4EN_Pos)    /*!< 0x00002000 */\n#define RCC_APB2ENR_SPI4EN                 RCC_APB2ENR_SPI4EN_Msk\n#define RCC_APB2ENR_SYSCFGEN_Pos           (14U)\n#define RCC_APB2ENR_SYSCFGEN_Msk           (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */\n#define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk\n#define RCC_APB2ENR_EXTITEN_Pos            (15U)\n#define RCC_APB2ENR_EXTITEN_Msk            (0x1UL << RCC_APB2ENR_EXTITEN_Pos)   /*!< 0x00008000 */\n#define RCC_APB2ENR_EXTITEN                RCC_APB2ENR_EXTITEN_Msk\n#define RCC_APB2ENR_TIM9EN_Pos             (16U)\n#define RCC_APB2ENR_TIM9EN_Msk             (0x1UL << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */\n#define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk\n#define RCC_APB2ENR_TIM10EN_Pos            (17U)\n#define RCC_APB2ENR_TIM10EN_Msk            (0x1UL << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */\n#define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk\n#define RCC_APB2ENR_TIM11EN_Pos            (18U)\n#define RCC_APB2ENR_TIM11EN_Msk            (0x1UL << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */\n#define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk\n#define RCC_APB2ENR_SPI5EN_Pos             (20U)\n#define RCC_APB2ENR_SPI5EN_Msk             (0x1UL << RCC_APB2ENR_SPI5EN_Pos)    /*!< 0x00100000 */\n#define RCC_APB2ENR_SPI5EN                 RCC_APB2ENR_SPI5EN_Msk\n#define RCC_APB2ENR_DFSDM1EN_Pos           (24U)\n#define RCC_APB2ENR_DFSDM1EN_Msk           (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos)  /*!< 0x01000000 */\n#define RCC_APB2ENR_DFSDM1EN               RCC_APB2ENR_DFSDM1EN_Msk\n\n/********************  Bit definition for RCC_AHB1LPENR register  *************/\n#define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)\n#define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk\n#define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)\n#define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk\n#define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)\n#define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */\n#define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk\n#define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)\n#define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */\n#define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk\n#define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)\n#define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk\n#define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)\n#define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */\n#define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk\n#define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)\n#define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */\n#define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk\n#define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)\n#define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */\n#define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk\n#define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)\n#define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk\n#define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)\n#define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk\n\n\n/********************  Bit definition for RCC_AHB2LPENR register  *************/\n#define RCC_AHB2LPENR_RNGLPEN_Pos          (6U)\n#define RCC_AHB2LPENR_RNGLPEN_Msk          (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB2LPENR_RNGLPEN              RCC_AHB2LPENR_RNGLPEN_Msk\n#define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)\n#define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk\n\n/********************  Bit definition for RCC_AHB3LPENR register  *************/\n#define RCC_AHB3LPENR_FSMCLPEN_Pos         (0U)\n#define RCC_AHB3LPENR_FSMCLPEN_Msk         (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB3LPENR_FSMCLPEN             RCC_AHB3LPENR_FSMCLPEN_Msk\n#define RCC_AHB3LPENR_QSPILPEN_Pos         (1U)\n#define RCC_AHB3LPENR_QSPILPEN_Msk         (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB3LPENR_QSPILPEN             RCC_AHB3LPENR_QSPILPEN_Msk\n\n/********************  Bit definition for RCC_APB1LPENR register  *************/\n#define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)\n#define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk\n#define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)\n#define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk\n#define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)\n#define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */\n#define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk\n#define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)\n#define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */\n#define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk\n#define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)\n#define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk\n#define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)\n#define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk\n#define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)\n#define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */\n#define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk\n#define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)\n#define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */\n#define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk\n#define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)\n#define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk\n#define RCC_APB1LPENR_RTCAPBLPEN_Pos       (10U)\n#define RCC_APB1LPENR_RTCAPBLPEN_Msk       (0x1UL << RCC_APB1LPENR_RTCAPBLPEN_Pos) /*!< 0x00000400 */\n#define RCC_APB1LPENR_RTCAPBLPEN           RCC_APB1LPENR_RTCAPBLPEN_Msk\n#define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)\n#define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk\n#define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)\n#define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk\n#define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)\n#define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */\n#define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk\n#define RCC_APB1LPENR_USART2LPEN_Pos       (17U)\n#define RCC_APB1LPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk\n#define RCC_APB1LPENR_USART3LPEN_Pos       (18U)\n#define RCC_APB1LPENR_USART3LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk\n#define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)\n#define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk\n#define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)\n#define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk\n#define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)\n#define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */\n#define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk\n#define RCC_APB1LPENR_FMPI2C1LPEN_Pos      (24U)\n#define RCC_APB1LPENR_FMPI2C1LPEN_Msk      (0x1UL << RCC_APB1LPENR_FMPI2C1LPEN_Pos) /*!< 0x01000000 */\n#define RCC_APB1LPENR_FMPI2C1LPEN          RCC_APB1LPENR_FMPI2C1LPEN_Msk\n#define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)\n#define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */\n#define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk\n#define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)\n#define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */\n#define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk\n#define RCC_APB1LPENR_PWRLPEN_Pos          (28U)\n#define RCC_APB1LPENR_PWRLPEN_Msk          (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */\n#define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk\n\n/********************  Bit definition for RCC_APB2LPENR register  *************/\n#define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)\n#define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk\n#define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)\n#define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk\n#define RCC_APB2LPENR_USART1LPEN_Pos       (4U)\n#define RCC_APB2LPENR_USART1LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk\n#define RCC_APB2LPENR_USART6LPEN_Pos       (5U)\n#define RCC_APB2LPENR_USART6LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk\n#define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)\n#define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk\n#define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)\n#define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk\n#define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)\n#define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */\n#define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk\n#define RCC_APB2LPENR_SPI4LPEN_Pos         (13U)\n#define RCC_APB2LPENR_SPI4LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */\n#define RCC_APB2LPENR_SPI4LPEN             RCC_APB2LPENR_SPI4LPEN_Msk\n#define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)\n#define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk\n#define RCC_APB2LPENR_EXTITLPEN_Pos        (15U)\n#define RCC_APB2LPENR_EXTITLPEN_Msk        (0x1UL << RCC_APB2LPENR_EXTITLPEN_Pos) /*!< 0x00008000 */\n#define RCC_APB2LPENR_EXTITLPEN            RCC_APB2LPENR_EXTITLPEN_Msk\n#define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)\n#define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */\n#define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk\n#define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)\n#define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk\n#define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)\n#define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk\n#define RCC_APB2LPENR_SPI5LPEN_Pos         (20U)\n#define RCC_APB2LPENR_SPI5LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */\n#define RCC_APB2LPENR_SPI5LPEN             RCC_APB2LPENR_SPI5LPEN_Msk\n#define RCC_APB2LPENR_DFSDM1LPEN_Pos       (24U)\n#define RCC_APB2LPENR_DFSDM1LPEN_Msk       (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x01000000 */\n#define RCC_APB2LPENR_DFSDM1LPEN           RCC_APB2LPENR_DFSDM1LPEN_Msk\n\n/********************  Bit definition for RCC_BDCR register  ******************/\n#define RCC_BDCR_LSEON_Pos                 (0U)\n#define RCC_BDCR_LSEON_Msk                 (0x1UL << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */\n#define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk\n#define RCC_BDCR_LSERDY_Pos                (1U)\n#define RCC_BDCR_LSERDY_Msk                (0x1UL << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */\n#define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk\n#define RCC_BDCR_LSEBYP_Pos                (2U)\n#define RCC_BDCR_LSEBYP_Msk                (0x1UL << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */\n#define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk\n#define RCC_BDCR_LSEMOD_Pos                (3U)\n#define RCC_BDCR_LSEMOD_Msk                (0x1UL << RCC_BDCR_LSEMOD_Pos)       /*!< 0x00000008 */\n#define RCC_BDCR_LSEMOD                    RCC_BDCR_LSEMOD_Msk\n\n#define RCC_BDCR_RTCSEL_Pos                (8U)\n#define RCC_BDCR_RTCSEL_Msk                (0x3UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */\n#define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk\n#define RCC_BDCR_RTCSEL_0                  (0x1UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */\n#define RCC_BDCR_RTCSEL_1                  (0x2UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */\n\n#define RCC_BDCR_RTCEN_Pos                 (15U)\n#define RCC_BDCR_RTCEN_Msk                 (0x1UL << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */\n#define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk\n#define RCC_BDCR_BDRST_Pos                 (16U)\n#define RCC_BDCR_BDRST_Msk                 (0x1UL << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */\n#define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk\n\n/********************  Bit definition for RCC_CSR register  *******************/\n#define RCC_CSR_LSION_Pos                  (0U)\n#define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */\n#define RCC_CSR_LSION                      RCC_CSR_LSION_Msk\n#define RCC_CSR_LSIRDY_Pos                 (1U)\n#define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */\n#define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk\n#define RCC_CSR_RMVF_Pos                   (24U)\n#define RCC_CSR_RMVF_Msk                   (0x1UL << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */\n#define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk\n#define RCC_CSR_BORRSTF_Pos                (25U)\n#define RCC_CSR_BORRSTF_Msk                (0x1UL << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */\n#define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk\n#define RCC_CSR_PINRSTF_Pos                (26U)\n#define RCC_CSR_PINRSTF_Msk                (0x1UL << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */\n#define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk\n#define RCC_CSR_PORRSTF_Pos                (27U)\n#define RCC_CSR_PORRSTF_Msk                (0x1UL << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */\n#define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk\n#define RCC_CSR_SFTRSTF_Pos                (28U)\n#define RCC_CSR_SFTRSTF_Msk                (0x1UL << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */\n#define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk\n#define RCC_CSR_IWDGRSTF_Pos               (29U)\n#define RCC_CSR_IWDGRSTF_Msk               (0x1UL << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */\n#define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk\n#define RCC_CSR_WWDGRSTF_Pos               (30U)\n#define RCC_CSR_WWDGRSTF_Msk               (0x1UL << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */\n#define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk\n#define RCC_CSR_LPWRRSTF_Pos               (31U)\n#define RCC_CSR_LPWRRSTF_Msk               (0x1UL << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */\n#define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk\n/* Legacy defines */\n#define RCC_CSR_PADRSTF                    RCC_CSR_PINRSTF\n#define RCC_CSR_WDGRSTF                    RCC_CSR_IWDGRSTF\n\n/********************  Bit definition for RCC_SSCGR register  *****************/\n#define RCC_SSCGR_MODPER_Pos               (0U)\n#define RCC_SSCGR_MODPER_Msk               (0x1FFFUL << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */\n#define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk\n#define RCC_SSCGR_INCSTEP_Pos              (13U)\n#define RCC_SSCGR_INCSTEP_Msk              (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */\n#define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk\n#define RCC_SSCGR_SPREADSEL_Pos            (30U)\n#define RCC_SSCGR_SPREADSEL_Msk            (0x1UL << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */\n#define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk\n#define RCC_SSCGR_SSCGEN_Pos               (31U)\n#define RCC_SSCGR_SSCGEN_Msk               (0x1UL << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */\n#define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk\n\n/********************  Bit definition for RCC_PLLI2SCFGR register  ************/\n#define RCC_PLLI2SCFGR_PLLI2SM_Pos         (0U)\n#define RCC_PLLI2SCFGR_PLLI2SM_Msk         (0x3FUL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */\n#define RCC_PLLI2SCFGR_PLLI2SM             RCC_PLLI2SCFGR_PLLI2SM_Msk\n#define RCC_PLLI2SCFGR_PLLI2SM_0           (0x01UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */\n#define RCC_PLLI2SCFGR_PLLI2SM_1           (0x02UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */\n#define RCC_PLLI2SCFGR_PLLI2SM_2           (0x04UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */\n#define RCC_PLLI2SCFGR_PLLI2SM_3           (0x08UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */\n#define RCC_PLLI2SCFGR_PLLI2SM_4           (0x10UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */\n#define RCC_PLLI2SCFGR_PLLI2SM_5           (0x20UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */\n\n#define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)\n#define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */\n#define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk\n#define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */\n#define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */\n#define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */\n#define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */\n#define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */\n#define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */\n#define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */\n\n#define RCC_PLLI2SCFGR_PLLI2SSRC_Pos       (22U)\n#define RCC_PLLI2SCFGR_PLLI2SSRC_Msk       (0x1UL << RCC_PLLI2SCFGR_PLLI2SSRC_Pos) /*!< 0x00400000 */\n#define RCC_PLLI2SCFGR_PLLI2SSRC           RCC_PLLI2SCFGR_PLLI2SSRC_Msk\n#define RCC_PLLI2SCFGR_PLLI2SQ_Pos         (24U)\n#define RCC_PLLI2SCFGR_PLLI2SQ_Msk         (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ             RCC_PLLI2SCFGR_PLLI2SQ_Msk\n#define RCC_PLLI2SCFGR_PLLI2SQ_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_3           (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)\n#define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk\n#define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for RCC_DCKCFGR register  ***************/\n\n#define RCC_DCKCFGR_CKDFSDM1ASEL_Pos       (15U)\n#define RCC_DCKCFGR_CKDFSDM1ASEL_Msk       (0x1UL << RCC_DCKCFGR_CKDFSDM1ASEL_Pos) /*!< 0x00008000 */\n#define RCC_DCKCFGR_CKDFSDM1ASEL           RCC_DCKCFGR_CKDFSDM1ASEL_Msk\n#define RCC_DCKCFGR_TIMPRE_Pos             (24U)\n#define RCC_DCKCFGR_TIMPRE_Msk             (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)    /*!< 0x01000000 */\n#define RCC_DCKCFGR_TIMPRE                 RCC_DCKCFGR_TIMPRE_Msk\n#define RCC_DCKCFGR_I2S1SRC_Pos            (25U)\n#define RCC_DCKCFGR_I2S1SRC_Msk            (0x3UL << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x06000000 */\n#define RCC_DCKCFGR_I2S1SRC                RCC_DCKCFGR_I2S1SRC_Msk\n#define RCC_DCKCFGR_I2S1SRC_0              (0x1UL << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x02000000 */\n#define RCC_DCKCFGR_I2S1SRC_1              (0x2UL << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x04000000 */\n\n#define RCC_DCKCFGR_I2S2SRC_Pos            (27U)\n#define RCC_DCKCFGR_I2S2SRC_Msk            (0x3UL << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x18000000 */\n#define RCC_DCKCFGR_I2S2SRC                RCC_DCKCFGR_I2S2SRC_Msk\n#define RCC_DCKCFGR_I2S2SRC_0              (0x1UL << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x08000000 */\n#define RCC_DCKCFGR_I2S2SRC_1              (0x2UL << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x10000000 */\n#define RCC_DCKCFGR_CKDFSDM1SEL_Pos        (31U)\n#define RCC_DCKCFGR_CKDFSDM1SEL_Msk        (0x1UL << RCC_DCKCFGR_CKDFSDM1SEL_Pos) /*!< 0x80000000 */\n#define RCC_DCKCFGR_CKDFSDM1SEL            RCC_DCKCFGR_CKDFSDM1SEL_Msk\n\n/********************  Bit definition for RCC_CKGATENR register  ***************/\n#define RCC_CKGATENR_AHB2APB1_CKEN_Pos     (0U)\n#define RCC_CKGATENR_AHB2APB1_CKEN_Msk     (0x1UL << RCC_CKGATENR_AHB2APB1_CKEN_Pos) /*!< 0x00000001 */\n#define RCC_CKGATENR_AHB2APB1_CKEN         RCC_CKGATENR_AHB2APB1_CKEN_Msk\n#define RCC_CKGATENR_AHB2APB2_CKEN_Pos     (1U)\n#define RCC_CKGATENR_AHB2APB2_CKEN_Msk     (0x1UL << RCC_CKGATENR_AHB2APB2_CKEN_Pos) /*!< 0x00000002 */\n#define RCC_CKGATENR_AHB2APB2_CKEN         RCC_CKGATENR_AHB2APB2_CKEN_Msk\n#define RCC_CKGATENR_CM4DBG_CKEN_Pos       (2U)\n#define RCC_CKGATENR_CM4DBG_CKEN_Msk       (0x1UL << RCC_CKGATENR_CM4DBG_CKEN_Pos) /*!< 0x00000004 */\n#define RCC_CKGATENR_CM4DBG_CKEN           RCC_CKGATENR_CM4DBG_CKEN_Msk\n#define RCC_CKGATENR_SPARE_CKEN_Pos        (3U)\n#define RCC_CKGATENR_SPARE_CKEN_Msk        (0x1UL << RCC_CKGATENR_SPARE_CKEN_Pos) /*!< 0x00000008 */\n#define RCC_CKGATENR_SPARE_CKEN            RCC_CKGATENR_SPARE_CKEN_Msk\n#define RCC_CKGATENR_SRAM_CKEN_Pos         (4U)\n#define RCC_CKGATENR_SRAM_CKEN_Msk         (0x1UL << RCC_CKGATENR_SRAM_CKEN_Pos) /*!< 0x00000010 */\n#define RCC_CKGATENR_SRAM_CKEN             RCC_CKGATENR_SRAM_CKEN_Msk\n#define RCC_CKGATENR_FLITF_CKEN_Pos        (5U)\n#define RCC_CKGATENR_FLITF_CKEN_Msk        (0x1UL << RCC_CKGATENR_FLITF_CKEN_Pos) /*!< 0x00000020 */\n#define RCC_CKGATENR_FLITF_CKEN            RCC_CKGATENR_FLITF_CKEN_Msk\n#define RCC_CKGATENR_RCC_CKEN_Pos          (6U)\n#define RCC_CKGATENR_RCC_CKEN_Msk          (0x1UL << RCC_CKGATENR_RCC_CKEN_Pos) /*!< 0x00000040 */\n#define RCC_CKGATENR_RCC_CKEN              RCC_CKGATENR_RCC_CKEN_Msk\n#define RCC_CKGATENR_RCC_EVTCTL_Pos        (7U)\n#define RCC_CKGATENR_RCC_EVTCTL_Msk        (0x1UL << RCC_CKGATENR_RCC_EVTCTL_Pos) /*!< 0x00000080 */\n#define RCC_CKGATENR_RCC_EVTCTL            RCC_CKGATENR_RCC_EVTCTL_Msk\n\n/********************  Bit definition for RCC_DCKCFGR2 register  ***************/\n#define RCC_DCKCFGR2_FMPI2C1SEL_Pos        (22U)\n#define RCC_DCKCFGR2_FMPI2C1SEL_Msk        (0x3UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */\n#define RCC_DCKCFGR2_FMPI2C1SEL            RCC_DCKCFGR2_FMPI2C1SEL_Msk\n#define RCC_DCKCFGR2_FMPI2C1SEL_0          (0x1UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */\n#define RCC_DCKCFGR2_FMPI2C1SEL_1          (0x2UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */\n#define RCC_DCKCFGR2_CK48MSEL_Pos          (27U)\n#define RCC_DCKCFGR2_CK48MSEL_Msk          (0x1UL << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */\n#define RCC_DCKCFGR2_CK48MSEL              RCC_DCKCFGR2_CK48MSEL_Msk\n#define RCC_DCKCFGR2_SDIOSEL_Pos           (28U)\n#define RCC_DCKCFGR2_SDIOSEL_Msk           (0x1UL << RCC_DCKCFGR2_SDIOSEL_Pos)  /*!< 0x10000000 */\n#define RCC_DCKCFGR2_SDIOSEL               RCC_DCKCFGR2_SDIOSEL_Msk\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    RNG                                     */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RNG_CR register  *******************/\n#define RNG_CR_RNGEN_Pos    (2U)\n#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */\n#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk\n#define RNG_CR_IE_Pos       (3U)\n#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */\n#define RNG_CR_IE           RNG_CR_IE_Msk\n\n/********************  Bits definition for RNG_SR register  *******************/\n#define RNG_SR_DRDY_Pos     (0U)\n#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */\n#define RNG_SR_DRDY         RNG_SR_DRDY_Msk\n#define RNG_SR_CECS_Pos     (1U)\n#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */\n#define RNG_SR_CECS         RNG_SR_CECS_Msk\n#define RNG_SR_SECS_Pos     (2U)\n#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */\n#define RNG_SR_SECS         RNG_SR_SECS_Msk\n#define RNG_SR_CEIS_Pos     (5U)\n#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */\n#define RNG_SR_CEIS         RNG_SR_CEIS_Msk\n#define RNG_SR_SEIS_Pos     (6U)\n#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */\n#define RNG_SR_SEIS         RNG_SR_SEIS_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Real-Time Clock (RTC)                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RTC_TR register  *******************/\n#define RTC_TR_PM_Pos                 (22U)\n#define RTC_TR_PM_Msk                 (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */\n#define RTC_TR_PM                     RTC_TR_PM_Msk\n#define RTC_TR_HT_Pos                 (20U)\n#define RTC_TR_HT_Msk                 (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */\n#define RTC_TR_HT                     RTC_TR_HT_Msk\n#define RTC_TR_HT_0                   (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */\n#define RTC_TR_HT_1                   (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */\n#define RTC_TR_HU_Pos                 (16U)\n#define RTC_TR_HU_Msk                 (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */\n#define RTC_TR_HU                     RTC_TR_HU_Msk\n#define RTC_TR_HU_0                   (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */\n#define RTC_TR_HU_1                   (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */\n#define RTC_TR_HU_2                   (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */\n#define RTC_TR_HU_3                   (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */\n#define RTC_TR_MNT_Pos                (12U)\n#define RTC_TR_MNT_Msk                (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */\n#define RTC_TR_MNT                    RTC_TR_MNT_Msk\n#define RTC_TR_MNT_0                  (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */\n#define RTC_TR_MNT_1                  (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */\n#define RTC_TR_MNT_2                  (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */\n#define RTC_TR_MNU_Pos                (8U)\n#define RTC_TR_MNU_Msk                (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */\n#define RTC_TR_MNU                    RTC_TR_MNU_Msk\n#define RTC_TR_MNU_0                  (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */\n#define RTC_TR_MNU_1                  (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */\n#define RTC_TR_MNU_2                  (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */\n#define RTC_TR_MNU_3                  (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */\n#define RTC_TR_ST_Pos                 (4U)\n#define RTC_TR_ST_Msk                 (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */\n#define RTC_TR_ST                     RTC_TR_ST_Msk\n#define RTC_TR_ST_0                   (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */\n#define RTC_TR_ST_1                   (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */\n#define RTC_TR_ST_2                   (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */\n#define RTC_TR_SU_Pos                 (0U)\n#define RTC_TR_SU_Msk                 (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */\n#define RTC_TR_SU                     RTC_TR_SU_Msk\n#define RTC_TR_SU_0                   (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */\n#define RTC_TR_SU_1                   (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */\n#define RTC_TR_SU_2                   (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */\n#define RTC_TR_SU_3                   (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_DR register  *******************/\n#define RTC_DR_YT_Pos                 (20U)\n#define RTC_DR_YT_Msk                 (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */\n#define RTC_DR_YT                     RTC_DR_YT_Msk\n#define RTC_DR_YT_0                   (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */\n#define RTC_DR_YT_1                   (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */\n#define RTC_DR_YT_2                   (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */\n#define RTC_DR_YT_3                   (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */\n#define RTC_DR_YU_Pos                 (16U)\n#define RTC_DR_YU_Msk                 (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */\n#define RTC_DR_YU                     RTC_DR_YU_Msk\n#define RTC_DR_YU_0                   (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */\n#define RTC_DR_YU_1                   (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */\n#define RTC_DR_YU_2                   (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */\n#define RTC_DR_YU_3                   (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */\n#define RTC_DR_WDU_Pos                (13U)\n#define RTC_DR_WDU_Msk                (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */\n#define RTC_DR_WDU                    RTC_DR_WDU_Msk\n#define RTC_DR_WDU_0                  (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */\n#define RTC_DR_WDU_1                  (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */\n#define RTC_DR_WDU_2                  (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */\n#define RTC_DR_MT_Pos                 (12U)\n#define RTC_DR_MT_Msk                 (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */\n#define RTC_DR_MT                     RTC_DR_MT_Msk\n#define RTC_DR_MU_Pos                 (8U)\n#define RTC_DR_MU_Msk                 (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */\n#define RTC_DR_MU                     RTC_DR_MU_Msk\n#define RTC_DR_MU_0                   (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */\n#define RTC_DR_MU_1                   (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */\n#define RTC_DR_MU_2                   (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */\n#define RTC_DR_MU_3                   (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */\n#define RTC_DR_DT_Pos                 (4U)\n#define RTC_DR_DT_Msk                 (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */\n#define RTC_DR_DT                     RTC_DR_DT_Msk\n#define RTC_DR_DT_0                   (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */\n#define RTC_DR_DT_1                   (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */\n#define RTC_DR_DU_Pos                 (0U)\n#define RTC_DR_DU_Msk                 (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */\n#define RTC_DR_DU                     RTC_DR_DU_Msk\n#define RTC_DR_DU_0                   (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */\n#define RTC_DR_DU_1                   (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */\n#define RTC_DR_DU_2                   (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */\n#define RTC_DR_DU_3                   (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_CR register  *******************/\n#define RTC_CR_COE_Pos                (23U)\n#define RTC_CR_COE_Msk                (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */\n#define RTC_CR_COE                    RTC_CR_COE_Msk\n#define RTC_CR_OSEL_Pos               (21U)\n#define RTC_CR_OSEL_Msk               (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */\n#define RTC_CR_OSEL                   RTC_CR_OSEL_Msk\n#define RTC_CR_OSEL_0                 (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */\n#define RTC_CR_OSEL_1                 (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */\n#define RTC_CR_POL_Pos                (20U)\n#define RTC_CR_POL_Msk                (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */\n#define RTC_CR_POL                    RTC_CR_POL_Msk\n#define RTC_CR_COSEL_Pos              (19U)\n#define RTC_CR_COSEL_Msk              (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */\n#define RTC_CR_COSEL                  RTC_CR_COSEL_Msk\n#define RTC_CR_BKP_Pos                 (18U)\n#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */\n#define RTC_CR_BKP                     RTC_CR_BKP_Msk\n#define RTC_CR_SUB1H_Pos              (17U)\n#define RTC_CR_SUB1H_Msk              (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */\n#define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk\n#define RTC_CR_ADD1H_Pos              (16U)\n#define RTC_CR_ADD1H_Msk              (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */\n#define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk\n#define RTC_CR_TSIE_Pos               (15U)\n#define RTC_CR_TSIE_Msk               (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */\n#define RTC_CR_TSIE                   RTC_CR_TSIE_Msk\n#define RTC_CR_WUTIE_Pos              (14U)\n#define RTC_CR_WUTIE_Msk              (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */\n#define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk\n#define RTC_CR_ALRBIE_Pos             (13U)\n#define RTC_CR_ALRBIE_Msk             (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */\n#define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk\n#define RTC_CR_ALRAIE_Pos             (12U)\n#define RTC_CR_ALRAIE_Msk             (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */\n#define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk\n#define RTC_CR_TSE_Pos                (11U)\n#define RTC_CR_TSE_Msk                (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */\n#define RTC_CR_TSE                    RTC_CR_TSE_Msk\n#define RTC_CR_WUTE_Pos               (10U)\n#define RTC_CR_WUTE_Msk               (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */\n#define RTC_CR_WUTE                   RTC_CR_WUTE_Msk\n#define RTC_CR_ALRBE_Pos              (9U)\n#define RTC_CR_ALRBE_Msk              (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */\n#define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk\n#define RTC_CR_ALRAE_Pos              (8U)\n#define RTC_CR_ALRAE_Msk              (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */\n#define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk\n#define RTC_CR_DCE_Pos                (7U)\n#define RTC_CR_DCE_Msk                (0x1UL << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */\n#define RTC_CR_DCE                    RTC_CR_DCE_Msk\n#define RTC_CR_FMT_Pos                (6U)\n#define RTC_CR_FMT_Msk                (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */\n#define RTC_CR_FMT                    RTC_CR_FMT_Msk\n#define RTC_CR_BYPSHAD_Pos            (5U)\n#define RTC_CR_BYPSHAD_Msk            (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */\n#define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk\n#define RTC_CR_REFCKON_Pos            (4U)\n#define RTC_CR_REFCKON_Msk            (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */\n#define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk\n#define RTC_CR_TSEDGE_Pos             (3U)\n#define RTC_CR_TSEDGE_Msk             (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */\n#define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk\n#define RTC_CR_WUCKSEL_Pos            (0U)\n#define RTC_CR_WUCKSEL_Msk            (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */\n#define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk\n#define RTC_CR_WUCKSEL_0              (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */\n#define RTC_CR_WUCKSEL_1              (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */\n#define RTC_CR_WUCKSEL_2              (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */\n\n/* Legacy defines */\n#define RTC_CR_BCK                     RTC_CR_BKP\n\n/********************  Bits definition for RTC_ISR register  ******************/\n#define RTC_ISR_RECALPF_Pos           (16U)\n#define RTC_ISR_RECALPF_Msk           (0x1UL << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */\n#define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk\n#define RTC_ISR_TAMP1F_Pos            (13U)\n#define RTC_ISR_TAMP1F_Msk            (0x1UL << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */\n#define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk\n#define RTC_ISR_TAMP2F_Pos            (14U)\n#define RTC_ISR_TAMP2F_Msk            (0x1UL << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */\n#define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk\n#define RTC_ISR_TSOVF_Pos             (12U)\n#define RTC_ISR_TSOVF_Msk             (0x1UL << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */\n#define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk\n#define RTC_ISR_TSF_Pos               (11U)\n#define RTC_ISR_TSF_Msk               (0x1UL << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */\n#define RTC_ISR_TSF                   RTC_ISR_TSF_Msk\n#define RTC_ISR_WUTF_Pos              (10U)\n#define RTC_ISR_WUTF_Msk              (0x1UL << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */\n#define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk\n#define RTC_ISR_ALRBF_Pos             (9U)\n#define RTC_ISR_ALRBF_Msk             (0x1UL << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */\n#define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk\n#define RTC_ISR_ALRAF_Pos             (8U)\n#define RTC_ISR_ALRAF_Msk             (0x1UL << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */\n#define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk\n#define RTC_ISR_INIT_Pos              (7U)\n#define RTC_ISR_INIT_Msk              (0x1UL << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */\n#define RTC_ISR_INIT                  RTC_ISR_INIT_Msk\n#define RTC_ISR_INITF_Pos             (6U)\n#define RTC_ISR_INITF_Msk             (0x1UL << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */\n#define RTC_ISR_INITF                 RTC_ISR_INITF_Msk\n#define RTC_ISR_RSF_Pos               (5U)\n#define RTC_ISR_RSF_Msk               (0x1UL << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */\n#define RTC_ISR_RSF                   RTC_ISR_RSF_Msk\n#define RTC_ISR_INITS_Pos             (4U)\n#define RTC_ISR_INITS_Msk             (0x1UL << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */\n#define RTC_ISR_INITS                 RTC_ISR_INITS_Msk\n#define RTC_ISR_SHPF_Pos              (3U)\n#define RTC_ISR_SHPF_Msk              (0x1UL << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */\n#define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk\n#define RTC_ISR_WUTWF_Pos             (2U)\n#define RTC_ISR_WUTWF_Msk             (0x1UL << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */\n#define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk\n#define RTC_ISR_ALRBWF_Pos            (1U)\n#define RTC_ISR_ALRBWF_Msk            (0x1UL << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */\n#define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk\n#define RTC_ISR_ALRAWF_Pos            (0U)\n#define RTC_ISR_ALRAWF_Msk            (0x1UL << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */\n#define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk\n\n/********************  Bits definition for RTC_PRER register  *****************/\n#define RTC_PRER_PREDIV_A_Pos         (16U)\n#define RTC_PRER_PREDIV_A_Msk         (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */\n#define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk\n#define RTC_PRER_PREDIV_S_Pos         (0U)\n#define RTC_PRER_PREDIV_S_Msk         (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */\n#define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk\n\n/********************  Bits definition for RTC_WUTR register  *****************/\n#define RTC_WUTR_WUT_Pos              (0U)\n#define RTC_WUTR_WUT_Msk              (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */\n#define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk\n\n/********************  Bits definition for RTC_CALIBR register  ***************/\n#define RTC_CALIBR_DCS_Pos            (7U)\n#define RTC_CALIBR_DCS_Msk            (0x1UL << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */\n#define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk\n#define RTC_CALIBR_DC_Pos             (0U)\n#define RTC_CALIBR_DC_Msk             (0x1FUL << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */\n#define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk\n\n/********************  Bits definition for RTC_ALRMAR register  ***************/\n#define RTC_ALRMAR_MSK4_Pos           (31U)\n#define RTC_ALRMAR_MSK4_Msk           (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk\n#define RTC_ALRMAR_WDSEL_Pos          (30U)\n#define RTC_ALRMAR_WDSEL_Msk          (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk\n#define RTC_ALRMAR_DT_Pos             (28U)\n#define RTC_ALRMAR_DT_Msk             (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk\n#define RTC_ALRMAR_DT_0               (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMAR_DT_1               (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMAR_DU_Pos             (24U)\n#define RTC_ALRMAR_DU_Msk             (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk\n#define RTC_ALRMAR_DU_0               (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMAR_DU_1               (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMAR_DU_2               (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMAR_DU_3               (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMAR_MSK3_Pos           (23U)\n#define RTC_ALRMAR_MSK3_Msk           (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk\n#define RTC_ALRMAR_PM_Pos             (22U)\n#define RTC_ALRMAR_PM_Msk             (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk\n#define RTC_ALRMAR_HT_Pos             (20U)\n#define RTC_ALRMAR_HT_Msk             (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk\n#define RTC_ALRMAR_HT_0               (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMAR_HT_1               (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMAR_HU_Pos             (16U)\n#define RTC_ALRMAR_HU_Msk             (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk\n#define RTC_ALRMAR_HU_0               (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMAR_HU_1               (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMAR_HU_2               (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMAR_HU_3               (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMAR_MSK2_Pos           (15U)\n#define RTC_ALRMAR_MSK2_Msk           (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk\n#define RTC_ALRMAR_MNT_Pos            (12U)\n#define RTC_ALRMAR_MNT_Msk            (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk\n#define RTC_ALRMAR_MNT_0              (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMAR_MNT_1              (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMAR_MNT_2              (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMAR_MNU_Pos            (8U)\n#define RTC_ALRMAR_MNU_Msk            (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk\n#define RTC_ALRMAR_MNU_0              (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMAR_MNU_1              (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMAR_MNU_2              (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMAR_MNU_3              (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMAR_MSK1_Pos           (7U)\n#define RTC_ALRMAR_MSK1_Msk           (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk\n#define RTC_ALRMAR_ST_Pos             (4U)\n#define RTC_ALRMAR_ST_Msk             (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk\n#define RTC_ALRMAR_ST_0               (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMAR_ST_1               (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMAR_ST_2               (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMAR_SU_Pos             (0U)\n#define RTC_ALRMAR_SU_Msk             (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk\n#define RTC_ALRMAR_SU_0               (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMAR_SU_1               (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMAR_SU_2               (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMAR_SU_3               (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_ALRMBR register  ***************/\n#define RTC_ALRMBR_MSK4_Pos           (31U)\n#define RTC_ALRMBR_MSK4_Msk           (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk\n#define RTC_ALRMBR_WDSEL_Pos          (30U)\n#define RTC_ALRMBR_WDSEL_Msk          (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk\n#define RTC_ALRMBR_DT_Pos             (28U)\n#define RTC_ALRMBR_DT_Msk             (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk\n#define RTC_ALRMBR_DT_0               (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMBR_DT_1               (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMBR_DU_Pos             (24U)\n#define RTC_ALRMBR_DU_Msk             (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk\n#define RTC_ALRMBR_DU_0               (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMBR_DU_1               (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMBR_DU_2               (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMBR_DU_3               (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMBR_MSK3_Pos           (23U)\n#define RTC_ALRMBR_MSK3_Msk           (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk\n#define RTC_ALRMBR_PM_Pos             (22U)\n#define RTC_ALRMBR_PM_Msk             (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk\n#define RTC_ALRMBR_HT_Pos             (20U)\n#define RTC_ALRMBR_HT_Msk             (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk\n#define RTC_ALRMBR_HT_0               (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMBR_HT_1               (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMBR_HU_Pos             (16U)\n#define RTC_ALRMBR_HU_Msk             (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk\n#define RTC_ALRMBR_HU_0               (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMBR_HU_1               (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMBR_HU_2               (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMBR_HU_3               (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMBR_MSK2_Pos           (15U)\n#define RTC_ALRMBR_MSK2_Msk           (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk\n#define RTC_ALRMBR_MNT_Pos            (12U)\n#define RTC_ALRMBR_MNT_Msk            (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk\n#define RTC_ALRMBR_MNT_0              (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMBR_MNT_1              (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMBR_MNT_2              (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMBR_MNU_Pos            (8U)\n#define RTC_ALRMBR_MNU_Msk            (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk\n#define RTC_ALRMBR_MNU_0              (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMBR_MNU_1              (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMBR_MNU_2              (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMBR_MNU_3              (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMBR_MSK1_Pos           (7U)\n#define RTC_ALRMBR_MSK1_Msk           (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk\n#define RTC_ALRMBR_ST_Pos             (4U)\n#define RTC_ALRMBR_ST_Msk             (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk\n#define RTC_ALRMBR_ST_0               (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMBR_ST_1               (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMBR_ST_2               (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMBR_SU_Pos             (0U)\n#define RTC_ALRMBR_SU_Msk             (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk\n#define RTC_ALRMBR_SU_0               (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMBR_SU_1               (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMBR_SU_2               (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMBR_SU_3               (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_WPR register  ******************/\n#define RTC_WPR_KEY_Pos               (0U)\n#define RTC_WPR_KEY_Msk               (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */\n#define RTC_WPR_KEY                   RTC_WPR_KEY_Msk\n\n/********************  Bits definition for RTC_SSR register  ******************/\n#define RTC_SSR_SS_Pos                (0U)\n#define RTC_SSR_SS_Msk                (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */\n#define RTC_SSR_SS                    RTC_SSR_SS_Msk\n\n/********************  Bits definition for RTC_SHIFTR register  ***************/\n#define RTC_SHIFTR_SUBFS_Pos          (0U)\n#define RTC_SHIFTR_SUBFS_Msk          (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */\n#define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk\n#define RTC_SHIFTR_ADD1S_Pos          (31U)\n#define RTC_SHIFTR_ADD1S_Msk          (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */\n#define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk\n\n/********************  Bits definition for RTC_TSTR register  *****************/\n#define RTC_TSTR_PM_Pos               (22U)\n#define RTC_TSTR_PM_Msk               (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */\n#define RTC_TSTR_PM                   RTC_TSTR_PM_Msk\n#define RTC_TSTR_HT_Pos               (20U)\n#define RTC_TSTR_HT_Msk               (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */\n#define RTC_TSTR_HT                   RTC_TSTR_HT_Msk\n#define RTC_TSTR_HT_0                 (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */\n#define RTC_TSTR_HT_1                 (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */\n#define RTC_TSTR_HU_Pos               (16U)\n#define RTC_TSTR_HU_Msk               (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */\n#define RTC_TSTR_HU                   RTC_TSTR_HU_Msk\n#define RTC_TSTR_HU_0                 (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */\n#define RTC_TSTR_HU_1                 (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */\n#define RTC_TSTR_HU_2                 (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */\n#define RTC_TSTR_HU_3                 (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */\n#define RTC_TSTR_MNT_Pos              (12U)\n#define RTC_TSTR_MNT_Msk              (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */\n#define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk\n#define RTC_TSTR_MNT_0                (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */\n#define RTC_TSTR_MNT_1                (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */\n#define RTC_TSTR_MNT_2                (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */\n#define RTC_TSTR_MNU_Pos              (8U)\n#define RTC_TSTR_MNU_Msk              (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */\n#define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk\n#define RTC_TSTR_MNU_0                (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */\n#define RTC_TSTR_MNU_1                (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */\n#define RTC_TSTR_MNU_2                (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */\n#define RTC_TSTR_MNU_3                (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */\n#define RTC_TSTR_ST_Pos               (4U)\n#define RTC_TSTR_ST_Msk               (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */\n#define RTC_TSTR_ST                   RTC_TSTR_ST_Msk\n#define RTC_TSTR_ST_0                 (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */\n#define RTC_TSTR_ST_1                 (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */\n#define RTC_TSTR_ST_2                 (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */\n#define RTC_TSTR_SU_Pos               (0U)\n#define RTC_TSTR_SU_Msk               (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */\n#define RTC_TSTR_SU                   RTC_TSTR_SU_Msk\n#define RTC_TSTR_SU_0                 (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */\n#define RTC_TSTR_SU_1                 (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */\n#define RTC_TSTR_SU_2                 (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */\n#define RTC_TSTR_SU_3                 (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSDR register  *****************/\n#define RTC_TSDR_WDU_Pos              (13U)\n#define RTC_TSDR_WDU_Msk              (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */\n#define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk\n#define RTC_TSDR_WDU_0                (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */\n#define RTC_TSDR_WDU_1                (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */\n#define RTC_TSDR_WDU_2                (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */\n#define RTC_TSDR_MT_Pos               (12U)\n#define RTC_TSDR_MT_Msk               (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */\n#define RTC_TSDR_MT                   RTC_TSDR_MT_Msk\n#define RTC_TSDR_MU_Pos               (8U)\n#define RTC_TSDR_MU_Msk               (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */\n#define RTC_TSDR_MU                   RTC_TSDR_MU_Msk\n#define RTC_TSDR_MU_0                 (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */\n#define RTC_TSDR_MU_1                 (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */\n#define RTC_TSDR_MU_2                 (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */\n#define RTC_TSDR_MU_3                 (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */\n#define RTC_TSDR_DT_Pos               (4U)\n#define RTC_TSDR_DT_Msk               (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */\n#define RTC_TSDR_DT                   RTC_TSDR_DT_Msk\n#define RTC_TSDR_DT_0                 (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */\n#define RTC_TSDR_DT_1                 (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */\n#define RTC_TSDR_DU_Pos               (0U)\n#define RTC_TSDR_DU_Msk               (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */\n#define RTC_TSDR_DU                   RTC_TSDR_DU_Msk\n#define RTC_TSDR_DU_0                 (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */\n#define RTC_TSDR_DU_1                 (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */\n#define RTC_TSDR_DU_2                 (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */\n#define RTC_TSDR_DU_3                 (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSSSR register  ****************/\n#define RTC_TSSSR_SS_Pos              (0U)\n#define RTC_TSSSR_SS_Msk              (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */\n#define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk\n\n/********************  Bits definition for RTC_CAL register  *****************/\n#define RTC_CALR_CALP_Pos             (15U)\n#define RTC_CALR_CALP_Msk             (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */\n#define RTC_CALR_CALP                 RTC_CALR_CALP_Msk\n#define RTC_CALR_CALW8_Pos            (14U)\n#define RTC_CALR_CALW8_Msk            (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */\n#define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk\n#define RTC_CALR_CALW16_Pos           (13U)\n#define RTC_CALR_CALW16_Msk           (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */\n#define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk\n#define RTC_CALR_CALM_Pos             (0U)\n#define RTC_CALR_CALM_Msk             (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */\n#define RTC_CALR_CALM                 RTC_CALR_CALM_Msk\n#define RTC_CALR_CALM_0               (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */\n#define RTC_CALR_CALM_1               (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */\n#define RTC_CALR_CALM_2               (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */\n#define RTC_CALR_CALM_3               (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */\n#define RTC_CALR_CALM_4               (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */\n#define RTC_CALR_CALM_5               (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */\n#define RTC_CALR_CALM_6               (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */\n#define RTC_CALR_CALM_7               (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */\n#define RTC_CALR_CALM_8               (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */\n\n/********************  Bits definition for RTC_TAFCR register  ****************/\n#define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)\n#define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */\n#define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk\n#define RTC_TAFCR_TSINSEL_Pos         (17U)\n#define RTC_TAFCR_TSINSEL_Msk         (0x1UL << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */\n#define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk\n#define RTC_TAFCR_TAMP1INSEL_Pos      (16U)\n#define RTC_TAFCR_TAMP1INSEL_Msk      (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)        /*!< 0x00010000 */\n#define RTC_TAFCR_TAMP1INSEL          RTC_TAFCR_TAMP1INSEL_Msk\n#define RTC_TAFCR_TAMPPUDIS_Pos       (15U)\n#define RTC_TAFCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */\n#define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk\n#define RTC_TAFCR_TAMPPRCH_Pos        (13U)\n#define RTC_TAFCR_TAMPPRCH_Msk        (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */\n#define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk\n#define RTC_TAFCR_TAMPPRCH_0          (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */\n#define RTC_TAFCR_TAMPPRCH_1          (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */\n#define RTC_TAFCR_TAMPFLT_Pos         (11U)\n#define RTC_TAFCR_TAMPFLT_Msk         (0x3UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */\n#define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk\n#define RTC_TAFCR_TAMPFLT_0           (0x1UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */\n#define RTC_TAFCR_TAMPFLT_1           (0x2UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */\n#define RTC_TAFCR_TAMPFREQ_Pos        (8U)\n#define RTC_TAFCR_TAMPFREQ_Msk        (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */\n#define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk\n#define RTC_TAFCR_TAMPFREQ_0          (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */\n#define RTC_TAFCR_TAMPFREQ_1          (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */\n#define RTC_TAFCR_TAMPFREQ_2          (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */\n#define RTC_TAFCR_TAMPTS_Pos          (7U)\n#define RTC_TAFCR_TAMPTS_Msk          (0x1UL << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */\n#define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk\n#define RTC_TAFCR_TAMP2TRG_Pos        (4U)\n#define RTC_TAFCR_TAMP2TRG_Msk        (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */\n#define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk\n#define RTC_TAFCR_TAMP2E_Pos          (3U)\n#define RTC_TAFCR_TAMP2E_Msk          (0x1UL << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */\n#define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk\n#define RTC_TAFCR_TAMPIE_Pos          (2U)\n#define RTC_TAFCR_TAMPIE_Msk          (0x1UL << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */\n#define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk\n#define RTC_TAFCR_TAMP1TRG_Pos        (1U)\n#define RTC_TAFCR_TAMP1TRG_Msk        (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */\n#define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk\n#define RTC_TAFCR_TAMP1E_Pos          (0U)\n#define RTC_TAFCR_TAMP1E_Msk          (0x1UL << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */\n#define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk\n\n/* Legacy defines */\n#define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMP1INSEL\n\n/********************  Bits definition for RTC_ALRMASSR register  *************/\n#define RTC_ALRMASSR_MASKSS_Pos       (24U)\n#define RTC_ALRMASSR_MASKSS_Msk       (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk\n#define RTC_ALRMASSR_MASKSS_0         (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMASSR_MASKSS_1         (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMASSR_MASKSS_2         (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMASSR_MASKSS_3         (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMASSR_SS_Pos           (0U)\n#define RTC_ALRMASSR_SS_Msk           (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk\n\n/********************  Bits definition for RTC_ALRMBSSR register  *************/\n#define RTC_ALRMBSSR_MASKSS_Pos       (24U)\n#define RTC_ALRMBSSR_MASKSS_Msk       (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk\n#define RTC_ALRMBSSR_MASKSS_0         (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMBSSR_MASKSS_1         (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMBSSR_MASKSS_2         (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMBSSR_MASKSS_3         (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMBSSR_SS_Pos           (0U)\n#define RTC_ALRMBSSR_SS_Msk           (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk\n\n/********************  Bits definition for RTC_BKP0R register  ****************/\n#define RTC_BKP0R_Pos                 (0U)\n#define RTC_BKP0R_Msk                 (0xFFFFFFFFUL << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP0R                     RTC_BKP0R_Msk\n\n/********************  Bits definition for RTC_BKP1R register  ****************/\n#define RTC_BKP1R_Pos                 (0U)\n#define RTC_BKP1R_Msk                 (0xFFFFFFFFUL << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP1R                     RTC_BKP1R_Msk\n\n/********************  Bits definition for RTC_BKP2R register  ****************/\n#define RTC_BKP2R_Pos                 (0U)\n#define RTC_BKP2R_Msk                 (0xFFFFFFFFUL << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP2R                     RTC_BKP2R_Msk\n\n/********************  Bits definition for RTC_BKP3R register  ****************/\n#define RTC_BKP3R_Pos                 (0U)\n#define RTC_BKP3R_Msk                 (0xFFFFFFFFUL << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP3R                     RTC_BKP3R_Msk\n\n/********************  Bits definition for RTC_BKP4R register  ****************/\n#define RTC_BKP4R_Pos                 (0U)\n#define RTC_BKP4R_Msk                 (0xFFFFFFFFUL << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP4R                     RTC_BKP4R_Msk\n\n/********************  Bits definition for RTC_BKP5R register  ****************/\n#define RTC_BKP5R_Pos                 (0U)\n#define RTC_BKP5R_Msk                 (0xFFFFFFFFUL << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP5R                     RTC_BKP5R_Msk\n\n/********************  Bits definition for RTC_BKP6R register  ****************/\n#define RTC_BKP6R_Pos                 (0U)\n#define RTC_BKP6R_Msk                 (0xFFFFFFFFUL << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP6R                     RTC_BKP6R_Msk\n\n/********************  Bits definition for RTC_BKP7R register  ****************/\n#define RTC_BKP7R_Pos                 (0U)\n#define RTC_BKP7R_Msk                 (0xFFFFFFFFUL << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP7R                     RTC_BKP7R_Msk\n\n/********************  Bits definition for RTC_BKP8R register  ****************/\n#define RTC_BKP8R_Pos                 (0U)\n#define RTC_BKP8R_Msk                 (0xFFFFFFFFUL << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP8R                     RTC_BKP8R_Msk\n\n/********************  Bits definition for RTC_BKP9R register  ****************/\n#define RTC_BKP9R_Pos                 (0U)\n#define RTC_BKP9R_Msk                 (0xFFFFFFFFUL << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP9R                     RTC_BKP9R_Msk\n\n/********************  Bits definition for RTC_BKP10R register  ***************/\n#define RTC_BKP10R_Pos                (0U)\n#define RTC_BKP10R_Msk                (0xFFFFFFFFUL << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP10R                    RTC_BKP10R_Msk\n\n/********************  Bits definition for RTC_BKP11R register  ***************/\n#define RTC_BKP11R_Pos                (0U)\n#define RTC_BKP11R_Msk                (0xFFFFFFFFUL << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP11R                    RTC_BKP11R_Msk\n\n/********************  Bits definition for RTC_BKP12R register  ***************/\n#define RTC_BKP12R_Pos                (0U)\n#define RTC_BKP12R_Msk                (0xFFFFFFFFUL << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP12R                    RTC_BKP12R_Msk\n\n/********************  Bits definition for RTC_BKP13R register  ***************/\n#define RTC_BKP13R_Pos                (0U)\n#define RTC_BKP13R_Msk                (0xFFFFFFFFUL << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP13R                    RTC_BKP13R_Msk\n\n/********************  Bits definition for RTC_BKP14R register  ***************/\n#define RTC_BKP14R_Pos                (0U)\n#define RTC_BKP14R_Msk                (0xFFFFFFFFUL << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP14R                    RTC_BKP14R_Msk\n\n/********************  Bits definition for RTC_BKP15R register  ***************/\n#define RTC_BKP15R_Pos                (0U)\n#define RTC_BKP15R_Msk                (0xFFFFFFFFUL << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP15R                    RTC_BKP15R_Msk\n\n/********************  Bits definition for RTC_BKP16R register  ***************/\n#define RTC_BKP16R_Pos                (0U)\n#define RTC_BKP16R_Msk                (0xFFFFFFFFUL << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP16R                    RTC_BKP16R_Msk\n\n/********************  Bits definition for RTC_BKP17R register  ***************/\n#define RTC_BKP17R_Pos                (0U)\n#define RTC_BKP17R_Msk                (0xFFFFFFFFUL << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP17R                    RTC_BKP17R_Msk\n\n/********************  Bits definition for RTC_BKP18R register  ***************/\n#define RTC_BKP18R_Pos                (0U)\n#define RTC_BKP18R_Msk                (0xFFFFFFFFUL << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP18R                    RTC_BKP18R_Msk\n\n/********************  Bits definition for RTC_BKP19R register  ***************/\n#define RTC_BKP19R_Pos                (0U)\n#define RTC_BKP19R_Msk                (0xFFFFFFFFUL << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP19R                    RTC_BKP19R_Msk\n\n/******************** Number of backup registers ******************************/\n#define RTC_BKP_NUMBER                       0x000000014U\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                          SD host Interface                                 */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SDIO_POWER register  ******************/\n#define SDIO_POWER_PWRCTRL_Pos         (0U)\n#define SDIO_POWER_PWRCTRL_Msk         (0x3UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */\n#define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */\n#define SDIO_POWER_PWRCTRL_0           (0x1UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x01 */\n#define SDIO_POWER_PWRCTRL_1           (0x2UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x02 */\n\n/******************  Bit definition for SDIO_CLKCR register  ******************/\n#define SDIO_CLKCR_CLKDIV_Pos          (0U)\n#define SDIO_CLKCR_CLKDIV_Msk          (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */\n#define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor             */\n#define SDIO_CLKCR_CLKEN_Pos           (8U)\n#define SDIO_CLKCR_CLKEN_Msk           (0x1UL << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */\n#define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit                */\n#define SDIO_CLKCR_PWRSAV_Pos          (9U)\n#define SDIO_CLKCR_PWRSAV_Msk          (0x1UL << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */\n#define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit  */\n#define SDIO_CLKCR_BYPASS_Pos          (10U)\n#define SDIO_CLKCR_BYPASS_Msk          (0x1UL << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */\n#define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */\n\n#define SDIO_CLKCR_WIDBUS_Pos          (11U)\n#define SDIO_CLKCR_WIDBUS_Msk          (0x3UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */\n#define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\n#define SDIO_CLKCR_WIDBUS_0            (0x1UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x0800 */\n#define SDIO_CLKCR_WIDBUS_1            (0x2UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x1000 */\n\n#define SDIO_CLKCR_NEGEDGE_Pos         (13U)\n#define SDIO_CLKCR_NEGEDGE_Msk         (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */\n#define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */\n#define SDIO_CLKCR_HWFC_EN_Pos         (14U)\n#define SDIO_CLKCR_HWFC_EN_Msk         (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */\n#define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable          */\n\n/*******************  Bit definition for SDIO_ARG register  *******************/\n#define SDIO_ARG_CMDARG_Pos            (0U)\n#define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */\n#define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */\n\n/*******************  Bit definition for SDIO_CMD register  *******************/\n#define SDIO_CMD_CMDINDEX_Pos          (0U)\n#define SDIO_CMD_CMDINDEX_Msk          (0x3FUL << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */\n#define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index                               */\n\n#define SDIO_CMD_WAITRESP_Pos          (6U)\n#define SDIO_CMD_WAITRESP_Msk          (0x3UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */\n#define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */\n#define SDIO_CMD_WAITRESP_0            (0x1UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0040 */\n#define SDIO_CMD_WAITRESP_1            (0x2UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0080 */\n\n#define SDIO_CMD_WAITINT_Pos           (8U)\n#define SDIO_CMD_WAITINT_Msk           (0x1UL << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */\n#define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request                               */\n#define SDIO_CMD_WAITPEND_Pos          (9U)\n#define SDIO_CMD_WAITPEND_Msk          (0x1UL << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */\n#define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\n#define SDIO_CMD_CPSMEN_Pos            (10U)\n#define SDIO_CMD_CPSMEN_Msk            (0x1UL << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */\n#define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit                   */\n#define SDIO_CMD_SDIOSUSPEND_Pos       (11U)\n#define SDIO_CMD_SDIOSUSPEND_Msk       (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */\n#define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command                                         */\n\n/*****************  Bit definition for SDIO_RESPCMD register  *****************/\n#define SDIO_RESPCMD_RESPCMD_Pos       (0U)\n#define SDIO_RESPCMD_RESPCMD_Msk       (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */\n#define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */\n\n/******************  Bit definition for SDIO_RESP0 register  ******************/\n#define SDIO_RESP0_CARDSTATUS0_Pos     (0U)\n#define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP1 register  ******************/\n#define SDIO_RESP1_CARDSTATUS1_Pos     (0U)\n#define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP2 register  ******************/\n#define SDIO_RESP2_CARDSTATUS2_Pos     (0U)\n#define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP3 register  ******************/\n#define SDIO_RESP3_CARDSTATUS3_Pos     (0U)\n#define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP4 register  ******************/\n#define SDIO_RESP4_CARDSTATUS4_Pos     (0U)\n#define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_DTIMER register  *****************/\n#define SDIO_DTIMER_DATATIME_Pos       (0U)\n#define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */\n\n/******************  Bit definition for SDIO_DLEN register  *******************/\n#define SDIO_DLEN_DATALENGTH_Pos       (0U)\n#define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */\n\n/******************  Bit definition for SDIO_DCTRL register  ******************/\n#define SDIO_DCTRL_DTEN_Pos            (0U)\n#define SDIO_DCTRL_DTEN_Msk            (0x1UL << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */\n#define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit         */\n#define SDIO_DCTRL_DTDIR_Pos           (1U)\n#define SDIO_DCTRL_DTDIR_Msk           (0x1UL << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */\n#define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */\n#define SDIO_DCTRL_DTMODE_Pos          (2U)\n#define SDIO_DCTRL_DTMODE_Msk          (0x1UL << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */\n#define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection      */\n#define SDIO_DCTRL_DMAEN_Pos           (3U)\n#define SDIO_DCTRL_DMAEN_Msk           (0x1UL << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */\n#define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit                   */\n\n#define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)\n#define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */\n#define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */\n#define SDIO_DCTRL_DBLOCKSIZE_0        (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0010 */\n#define SDIO_DCTRL_DBLOCKSIZE_1        (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0020 */\n#define SDIO_DCTRL_DBLOCKSIZE_2        (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0040 */\n#define SDIO_DCTRL_DBLOCKSIZE_3        (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0080 */\n\n#define SDIO_DCTRL_RWSTART_Pos         (8U)\n#define SDIO_DCTRL_RWSTART_Msk         (0x1UL << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */\n#define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start         */\n#define SDIO_DCTRL_RWSTOP_Pos          (9U)\n#define SDIO_DCTRL_RWSTOP_Msk          (0x1UL << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */\n#define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop          */\n#define SDIO_DCTRL_RWMOD_Pos           (10U)\n#define SDIO_DCTRL_RWMOD_Msk           (0x1UL << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */\n#define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode          */\n#define SDIO_DCTRL_SDIOEN_Pos          (11U)\n#define SDIO_DCTRL_SDIOEN_Msk          (0x1UL << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */\n#define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */\n\n/******************  Bit definition for SDIO_DCOUNT register  *****************/\n#define SDIO_DCOUNT_DATACOUNT_Pos      (0U)\n#define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */\n\n/******************  Bit definition for SDIO_STA register  ********************/\n#define SDIO_STA_CCRCFAIL_Pos          (0U)\n#define SDIO_STA_CCRCFAIL_Msk          (0x1UL << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */\n#define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */\n#define SDIO_STA_DCRCFAIL_Pos          (1U)\n#define SDIO_STA_DCRCFAIL_Msk          (0x1UL << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */\n#define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */\n#define SDIO_STA_CTIMEOUT_Pos          (2U)\n#define SDIO_STA_CTIMEOUT_Msk          (0x1UL << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */\n#define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */\n#define SDIO_STA_DTIMEOUT_Pos          (3U)\n#define SDIO_STA_DTIMEOUT_Msk          (0x1UL << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */\n#define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */\n#define SDIO_STA_TXUNDERR_Pos          (4U)\n#define SDIO_STA_TXUNDERR_Msk          (0x1UL << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */\n#define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */\n#define SDIO_STA_RXOVERR_Pos           (5U)\n#define SDIO_STA_RXOVERR_Msk           (0x1UL << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */\n#define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */\n#define SDIO_STA_CMDREND_Pos           (6U)\n#define SDIO_STA_CMDREND_Msk           (0x1UL << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */\n#define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */\n#define SDIO_STA_CMDSENT_Pos           (7U)\n#define SDIO_STA_CMDSENT_Msk           (0x1UL << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */\n#define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */\n#define SDIO_STA_DATAEND_Pos           (8U)\n#define SDIO_STA_DATAEND_Msk           (0x1UL << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */\n#define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */\n#define SDIO_STA_DBCKEND_Pos           (10U)\n#define SDIO_STA_DBCKEND_Msk           (0x1UL << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */\n#define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */\n#define SDIO_STA_CMDACT_Pos            (11U)\n#define SDIO_STA_CMDACT_Msk            (0x1UL << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */\n#define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */\n#define SDIO_STA_TXACT_Pos             (12U)\n#define SDIO_STA_TXACT_Msk             (0x1UL << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */\n#define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */\n#define SDIO_STA_RXACT_Pos             (13U)\n#define SDIO_STA_RXACT_Msk             (0x1UL << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */\n#define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */\n#define SDIO_STA_TXFIFOHE_Pos          (14U)\n#define SDIO_STA_TXFIFOHE_Msk          (0x1UL << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */\n#define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\n#define SDIO_STA_RXFIFOHF_Pos          (15U)\n#define SDIO_STA_RXFIFOHF_Msk          (0x1UL << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */\n#define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\n#define SDIO_STA_TXFIFOF_Pos           (16U)\n#define SDIO_STA_TXFIFOF_Msk           (0x1UL << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */\n#define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */\n#define SDIO_STA_RXFIFOF_Pos           (17U)\n#define SDIO_STA_RXFIFOF_Msk           (0x1UL << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */\n#define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */\n#define SDIO_STA_TXFIFOE_Pos           (18U)\n#define SDIO_STA_TXFIFOE_Msk           (0x1UL << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */\n#define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */\n#define SDIO_STA_RXFIFOE_Pos           (19U)\n#define SDIO_STA_RXFIFOE_Msk           (0x1UL << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */\n#define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */\n#define SDIO_STA_TXDAVL_Pos            (20U)\n#define SDIO_STA_TXDAVL_Msk            (0x1UL << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */\n#define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */\n#define SDIO_STA_RXDAVL_Pos            (21U)\n#define SDIO_STA_RXDAVL_Msk            (0x1UL << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */\n#define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */\n#define SDIO_STA_SDIOIT_Pos            (22U)\n#define SDIO_STA_SDIOIT_Msk            (0x1UL << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */\n#define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */\n\n/*******************  Bit definition for SDIO_ICR register  *******************/\n#define SDIO_ICR_CCRCFAILC_Pos         (0U)\n#define SDIO_ICR_CCRCFAILC_Msk         (0x1UL << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */\n#define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */\n#define SDIO_ICR_DCRCFAILC_Pos         (1U)\n#define SDIO_ICR_DCRCFAILC_Msk         (0x1UL << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */\n#define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */\n#define SDIO_ICR_CTIMEOUTC_Pos         (2U)\n#define SDIO_ICR_CTIMEOUTC_Msk         (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */\n#define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */\n#define SDIO_ICR_DTIMEOUTC_Pos         (3U)\n#define SDIO_ICR_DTIMEOUTC_Msk         (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */\n#define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */\n#define SDIO_ICR_TXUNDERRC_Pos         (4U)\n#define SDIO_ICR_TXUNDERRC_Msk         (0x1UL << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */\n#define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */\n#define SDIO_ICR_RXOVERRC_Pos          (5U)\n#define SDIO_ICR_RXOVERRC_Msk          (0x1UL << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */\n#define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */\n#define SDIO_ICR_CMDRENDC_Pos          (6U)\n#define SDIO_ICR_CMDRENDC_Msk          (0x1UL << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */\n#define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */\n#define SDIO_ICR_CMDSENTC_Pos          (7U)\n#define SDIO_ICR_CMDSENTC_Msk          (0x1UL << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */\n#define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */\n#define SDIO_ICR_DATAENDC_Pos          (8U)\n#define SDIO_ICR_DATAENDC_Msk          (0x1UL << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */\n#define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */\n#define SDIO_ICR_DBCKENDC_Pos          (10U)\n#define SDIO_ICR_DBCKENDC_Msk          (0x1UL << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */\n#define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */\n#define SDIO_ICR_SDIOITC_Pos           (22U)\n#define SDIO_ICR_SDIOITC_Msk           (0x1UL << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */\n#define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */\n\n/******************  Bit definition for SDIO_MASK register  *******************/\n#define SDIO_MASK_CCRCFAILIE_Pos       (0U)\n#define SDIO_MASK_CCRCFAILIE_Msk       (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */\n#define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */\n#define SDIO_MASK_DCRCFAILIE_Pos       (1U)\n#define SDIO_MASK_DCRCFAILIE_Msk       (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */\n#define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */\n#define SDIO_MASK_CTIMEOUTIE_Pos       (2U)\n#define SDIO_MASK_CTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */\n#define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */\n#define SDIO_MASK_DTIMEOUTIE_Pos       (3U)\n#define SDIO_MASK_DTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */\n#define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */\n#define SDIO_MASK_TXUNDERRIE_Pos       (4U)\n#define SDIO_MASK_TXUNDERRIE_Msk       (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */\n#define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */\n#define SDIO_MASK_RXOVERRIE_Pos        (5U)\n#define SDIO_MASK_RXOVERRIE_Msk        (0x1UL << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */\n#define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */\n#define SDIO_MASK_CMDRENDIE_Pos        (6U)\n#define SDIO_MASK_CMDRENDIE_Msk        (0x1UL << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */\n#define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */\n#define SDIO_MASK_CMDSENTIE_Pos        (7U)\n#define SDIO_MASK_CMDSENTIE_Msk        (0x1UL << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */\n#define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */\n#define SDIO_MASK_DATAENDIE_Pos        (8U)\n#define SDIO_MASK_DATAENDIE_Msk        (0x1UL << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */\n#define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */\n#define SDIO_MASK_DBCKENDIE_Pos        (10U)\n#define SDIO_MASK_DBCKENDIE_Msk        (0x1UL << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */\n#define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */\n#define SDIO_MASK_CMDACTIE_Pos         (11U)\n#define SDIO_MASK_CMDACTIE_Msk         (0x1UL << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */\n#define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */\n#define SDIO_MASK_TXACTIE_Pos          (12U)\n#define SDIO_MASK_TXACTIE_Msk          (0x1UL << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */\n#define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */\n#define SDIO_MASK_RXACTIE_Pos          (13U)\n#define SDIO_MASK_RXACTIE_Msk          (0x1UL << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */\n#define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */\n#define SDIO_MASK_TXFIFOHEIE_Pos       (14U)\n#define SDIO_MASK_TXFIFOHEIE_Msk       (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */\n#define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */\n#define SDIO_MASK_RXFIFOHFIE_Pos       (15U)\n#define SDIO_MASK_RXFIFOHFIE_Msk       (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */\n#define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */\n#define SDIO_MASK_TXFIFOFIE_Pos        (16U)\n#define SDIO_MASK_TXFIFOFIE_Msk        (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */\n#define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */\n#define SDIO_MASK_RXFIFOFIE_Pos        (17U)\n#define SDIO_MASK_RXFIFOFIE_Msk        (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */\n#define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */\n#define SDIO_MASK_TXFIFOEIE_Pos        (18U)\n#define SDIO_MASK_TXFIFOEIE_Msk        (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */\n#define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_RXFIFOEIE_Pos        (19U)\n#define SDIO_MASK_RXFIFOEIE_Msk        (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */\n#define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_TXDAVLIE_Pos         (20U)\n#define SDIO_MASK_TXDAVLIE_Msk         (0x1UL << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */\n#define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */\n#define SDIO_MASK_RXDAVLIE_Pos         (21U)\n#define SDIO_MASK_RXDAVLIE_Msk         (0x1UL << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */\n#define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */\n#define SDIO_MASK_SDIOITIE_Pos         (22U)\n#define SDIO_MASK_SDIOITIE_Msk         (0x1UL << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */\n#define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */\n\n/*****************  Bit definition for SDIO_FIFOCNT register  *****************/\n#define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)\n#define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */\n#define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */\n\n/******************  Bit definition for SDIO_FIFO register  *******************/\n#define SDIO_FIFO_FIFODATA_Pos         (0U)\n#define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Serial Peripheral Interface                         */\n/*                                                                            */\n/******************************************************************************/\n#define SPI_I2S_FULLDUPLEX_SUPPORT                                             /*!< I2S Full-Duplex support */\n#define I2S_APB1_APB2_FEATURE                                                  /*!< I2S IP's are splited between RCC APB1 and APB2 interfaces */\n\n/*******************  Bit definition for SPI_CR1 register  ********************/\n#define SPI_CR1_CPHA_Pos            (0U)\n#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */\n#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */\n#define SPI_CR1_CPOL_Pos            (1U)\n#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */\n#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */\n#define SPI_CR1_MSTR_Pos            (2U)\n#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */\n#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */\n\n#define SPI_CR1_BR_Pos              (3U)\n#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */\n#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */\n#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */\n#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */\n#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */\n\n#define SPI_CR1_SPE_Pos             (6U)\n#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */\n#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */\n#define SPI_CR1_LSBFIRST_Pos        (7U)\n#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */\n#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */\n#define SPI_CR1_SSI_Pos             (8U)\n#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */\n#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */\n#define SPI_CR1_SSM_Pos             (9U)\n#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */\n#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */\n#define SPI_CR1_RXONLY_Pos          (10U)\n#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */\n#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */\n#define SPI_CR1_DFF_Pos             (11U)\n#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */\n#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */\n#define SPI_CR1_CRCNEXT_Pos         (12U)\n#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */\n#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */\n#define SPI_CR1_CRCEN_Pos           (13U)\n#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */\n#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */\n#define SPI_CR1_BIDIOE_Pos          (14U)\n#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */\n#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */\n#define SPI_CR1_BIDIMODE_Pos        (15U)\n#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */\n#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */\n\n/*******************  Bit definition for SPI_CR2 register  ********************/\n#define SPI_CR2_RXDMAEN_Pos         (0U)\n#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */\n#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */\n#define SPI_CR2_TXDMAEN_Pos         (1U)\n#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */\n#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */\n#define SPI_CR2_SSOE_Pos            (2U)\n#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */\n#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */\n#define SPI_CR2_FRF_Pos             (4U)\n#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */\n#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */\n#define SPI_CR2_ERRIE_Pos           (5U)\n#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */\n#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */\n#define SPI_CR2_RXNEIE_Pos          (6U)\n#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */\n#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */\n#define SPI_CR2_TXEIE_Pos           (7U)\n#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */\n#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */\n\n/********************  Bit definition for SPI_SR register  ********************/\n#define SPI_SR_RXNE_Pos             (0U)\n#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */\n#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */\n#define SPI_SR_TXE_Pos              (1U)\n#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */\n#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */\n#define SPI_SR_CHSIDE_Pos           (2U)\n#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */\n#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */\n#define SPI_SR_UDR_Pos              (3U)\n#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */\n#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */\n#define SPI_SR_CRCERR_Pos           (4U)\n#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */\n#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */\n#define SPI_SR_MODF_Pos             (5U)\n#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */\n#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */\n#define SPI_SR_OVR_Pos              (6U)\n#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */\n#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */\n#define SPI_SR_BSY_Pos              (7U)\n#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */\n#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */\n#define SPI_SR_FRE_Pos              (8U)\n#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */\n#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */\n\n/********************  Bit definition for SPI_DR register  ********************/\n#define SPI_DR_DR_Pos               (0U)\n#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */\n#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */\n\n/*******************  Bit definition for SPI_CRCPR register  ******************/\n#define SPI_CRCPR_CRCPOLY_Pos       (0U)\n#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */\n#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */\n\n/******************  Bit definition for SPI_RXCRCR register  ******************/\n#define SPI_RXCRCR_RXCRC_Pos        (0U)\n#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */\n\n/******************  Bit definition for SPI_TXCRCR register  ******************/\n#define SPI_TXCRCR_TXCRC_Pos        (0U)\n#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */\n\n/******************  Bit definition for SPI_I2SCFGR register  *****************/\n#define SPI_I2SCFGR_CHLEN_Pos       (0U)\n#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */\n#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */\n\n#define SPI_I2SCFGR_DATLEN_Pos      (1U)\n#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */\n#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */\n#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */\n#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */\n\n#define SPI_I2SCFGR_CKPOL_Pos       (3U)\n#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */\n#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */\n\n#define SPI_I2SCFGR_I2SSTD_Pos      (4U)\n#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */\n#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */\n#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */\n#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */\n\n#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)\n#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */\n#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */\n\n#define SPI_I2SCFGR_I2SCFG_Pos      (8U)\n#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */\n#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */\n#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */\n#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */\n\n#define SPI_I2SCFGR_I2SE_Pos        (10U)\n#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */\n#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */\n#define SPI_I2SCFGR_I2SMOD_Pos      (11U)\n#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */\n#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */\n#define SPI_I2SCFGR_ASTRTEN_Pos     (12U)\n#define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)          /*!< 0x00001000 */\n#define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */\n\n/******************  Bit definition for SPI_I2SPR register  *******************/\n#define SPI_I2SPR_I2SDIV_Pos        (0U)\n#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */\n#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */\n#define SPI_I2SPR_ODD_Pos           (8U)\n#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */\n#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */\n#define SPI_I2SPR_MCKOE_Pos         (9U)\n#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */\n#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                 SYSCFG                                     */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SYSCFG_MEMRMP register  ***************/\n#define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)\n#define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */\n#define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */\n#define SYSCFG_MEMRMP_MEM_MODE_0             (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */\n#define SYSCFG_MEMRMP_MEM_MODE_1             (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */\n/******************  Bit definition for SYSCFG_PMC register  ******************/\n#define SYSCFG_PMC_ADC1DC2_Pos               (16U)\n#define SYSCFG_PMC_ADC1DC2_Msk               (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)  /*!< 0x00010000 */\n#define SYSCFG_PMC_ADC1DC2                   SYSCFG_PMC_ADC1DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */\n\n/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\n#define SYSCFG_EXTICR1_EXTI0_Pos             (0U)\n#define SYSCFG_EXTICR1_EXTI0_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */\n#define SYSCFG_EXTICR1_EXTI1_Pos             (4U)\n#define SYSCFG_EXTICR1_EXTI1_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */\n#define SYSCFG_EXTICR1_EXTI2_Pos             (8U)\n#define SYSCFG_EXTICR1_EXTI2_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */\n#define SYSCFG_EXTICR1_EXTI3_Pos             (12U)\n#define SYSCFG_EXTICR1_EXTI3_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */\n/**\n  * @brief   EXTI0 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PD              0x0003U                           /*!<PD[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PE              0x0004U                           /*!<PE[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PF              0x0005U                           /*!<PF[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PG              0x0006U                           /*!<PG[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */\n\n/**\n  * @brief   EXTI1 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PD              0x0030U                           /*!<PD[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PE              0x0040U                           /*!<PE[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PF              0x0050U                           /*!<PF[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PG              0x0060U                           /*!<PG[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */\n\n/**\n  * @brief   EXTI2 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PD              0x0300U                           /*!<PD[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PE              0x0400U                           /*!<PE[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PF              0x0500U                           /*!<PF[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PG              0x0600U                           /*!<PG[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */\n\n/**\n  * @brief   EXTI3 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PD              0x3000U                           /*!<PD[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PE              0x4000U                           /*!<PE[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PF              0x5000U                           /*!<PF[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PG              0x6000U                           /*!<PG[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\n#define SYSCFG_EXTICR2_EXTI4_Pos             (0U)\n#define SYSCFG_EXTICR2_EXTI4_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */\n#define SYSCFG_EXTICR2_EXTI5_Pos             (4U)\n#define SYSCFG_EXTICR2_EXTI5_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */\n#define SYSCFG_EXTICR2_EXTI6_Pos             (8U)\n#define SYSCFG_EXTICR2_EXTI6_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */\n#define SYSCFG_EXTICR2_EXTI7_Pos             (12U)\n#define SYSCFG_EXTICR2_EXTI7_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */\n\n/**\n  * @brief   EXTI4 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PD              0x0003U                           /*!<PD[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PE              0x0004U                           /*!<PE[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PF              0x0005U                           /*!<PF[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PG              0x0006U                           /*!<PG[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */\n\n/**\n  * @brief   EXTI5 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PD              0x0030U                           /*!<PD[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PE              0x0040U                           /*!<PE[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PF              0x0050U                           /*!<PF[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PG              0x0060U                           /*!<PG[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */\n\n/**\n  * @brief   EXTI6 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PD              0x0300U                           /*!<PD[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PE              0x0400U                           /*!<PE[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PF              0x0500U                           /*!<PF[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PG              0x0600U                           /*!<PG[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */\n\n/**\n  * @brief   EXTI7 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PD              0x3000U                           /*!<PD[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PE              0x4000U                           /*!<PE[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PF              0x5000U                           /*!<PF[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PG              0x6000U                           /*!<PG[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\n#define SYSCFG_EXTICR3_EXTI8_Pos             (0U)\n#define SYSCFG_EXTICR3_EXTI8_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */\n#define SYSCFG_EXTICR3_EXTI9_Pos             (4U)\n#define SYSCFG_EXTICR3_EXTI9_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */\n#define SYSCFG_EXTICR3_EXTI10_Pos            (8U)\n#define SYSCFG_EXTICR3_EXTI10_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */\n#define SYSCFG_EXTICR3_EXTI11_Pos            (12U)\n#define SYSCFG_EXTICR3_EXTI11_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */\n\n/**\n  * @brief   EXTI8 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PD              0x0003U                           /*!<PD[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PE              0x0004U                           /*!<PE[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PF              0x0005U                           /*!<PF[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PG              0x0006U                           /*!<PG[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */\n\n/**\n  * @brief   EXTI9 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PD              0x0030U                           /*!<PD[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PE              0x0040U                           /*!<PE[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PF              0x0050U                           /*!<PF[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PG              0x0060U                           /*!<PG[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */\n\n/**\n  * @brief   EXTI10 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PD             0x0300U                           /*!<PD[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PE             0x0400U                           /*!<PE[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PF             0x0500U                           /*!<PF[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PG             0x0600U                           /*!<PG[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */\n\n/**\n  * @brief   EXTI11 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PD             0x3000U                           /*!<PD[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PE             0x4000U                           /*!<PE[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PF             0x5000U                           /*!<PF[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PG             0x6000U                           /*!<PG[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\n#define SYSCFG_EXTICR4_EXTI12_Pos            (0U)\n#define SYSCFG_EXTICR4_EXTI12_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */\n#define SYSCFG_EXTICR4_EXTI13_Pos            (4U)\n#define SYSCFG_EXTICR4_EXTI13_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */\n#define SYSCFG_EXTICR4_EXTI14_Pos            (8U)\n#define SYSCFG_EXTICR4_EXTI14_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */\n#define SYSCFG_EXTICR4_EXTI15_Pos            (12U)\n#define SYSCFG_EXTICR4_EXTI15_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */\n\n/**\n  * @brief   EXTI12 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PD             0x0003U                           /*!<PD[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PE             0x0004U                           /*!<PE[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PF             0x0005U                           /*!<PF[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PG             0x0006U                           /*!<PG[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */\n\n/**\n  * @brief   EXTI13 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PD             0x0030U                           /*!<PD[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PE             0x0040U                           /*!<PE[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PF             0x0050U                           /*!<PF[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PG             0x0060U                           /*!<PG[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */\n\n/**\n  * @brief   EXTI14 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PD             0x0300U                           /*!<PD[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PE             0x0400U                           /*!<PE[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PF             0x0500U                           /*!<PF[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PG             0x0600U                           /*!<PG[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */\n\n/**\n  * @brief   EXTI15 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PD             0x3000U                           /*!<PD[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PE             0x4000U                           /*!<PE[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PF             0x5000U                           /*!<PF[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PG             0x6000U                           /*!<PG[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */\n\n/******************  Bit definition for SYSCFG_CMPCR register  ****************/\n#define SYSCFG_CMPCR_CMP_PD_Pos              (0U)\n#define SYSCFG_CMPCR_CMP_PD_Msk              (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */\n#define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */\n#define SYSCFG_CMPCR_READY_Pos               (8U)\n#define SYSCFG_CMPCR_READY_Msk               (0x1UL << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */\n#define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */\n/******************  Bit definition for SYSCFG_CFGR register  ****************/\n#define SYSCFG_CFGR_FMPI2C1_SCL_Pos          (0U)\n#define SYSCFG_CFGR_FMPI2C1_SCL_Msk          (0x1UL << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */\n#define SYSCFG_CFGR_FMPI2C1_SCL              SYSCFG_CFGR_FMPI2C1_SCL_Msk       /*!<FM+ drive capability for FMPI2C1_SCL pin */\n#define SYSCFG_CFGR_FMPI2C1_SDA_Pos          (1U)\n#define SYSCFG_CFGR_FMPI2C1_SDA_Msk          (0x1UL << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */\n#define SYSCFG_CFGR_FMPI2C1_SDA              SYSCFG_CFGR_FMPI2C1_SDA_Msk       /*!<FM+ drive capability for FMPI2C1_SDA pin */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    TIM                                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for TIM_CR1 register  ********************/\n#define TIM_CR1_CEN_Pos           (0U)\n#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */\n#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */\n#define TIM_CR1_UDIS_Pos          (1U)\n#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */\n#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */\n#define TIM_CR1_URS_Pos           (2U)\n#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */\n#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */\n#define TIM_CR1_OPM_Pos           (3U)\n#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */\n#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */\n#define TIM_CR1_DIR_Pos           (4U)\n#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */\n#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */\n\n#define TIM_CR1_CMS_Pos           (5U)\n#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */\n#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */\n#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR1_ARPE_Pos          (7U)\n#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */\n#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */\n\n#define TIM_CR1_CKD_Pos           (8U)\n#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */\n#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */\n#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */\n#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */\n\n/*******************  Bit definition for TIM_CR2 register  ********************/\n#define TIM_CR2_CCPC_Pos          (0U)\n#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */\n#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */\n#define TIM_CR2_CCUS_Pos          (2U)\n#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */\n#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */\n#define TIM_CR2_CCDS_Pos          (3U)\n#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */\n#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */\n\n#define TIM_CR2_MMS_Pos           (4U)\n#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */\n#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */\n#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */\n#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR2_TI1S_Pos          (7U)\n#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */\n#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */\n#define TIM_CR2_OIS1_Pos          (8U)\n#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */\n#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */\n#define TIM_CR2_OIS1N_Pos         (9U)\n#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */\n#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */\n#define TIM_CR2_OIS2_Pos          (10U)\n#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */\n#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */\n#define TIM_CR2_OIS2N_Pos         (11U)\n#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */\n#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */\n#define TIM_CR2_OIS3_Pos          (12U)\n#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */\n#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */\n#define TIM_CR2_OIS3N_Pos         (13U)\n#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */\n#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */\n#define TIM_CR2_OIS4_Pos          (14U)\n#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */\n#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */\n\n/*******************  Bit definition for TIM_SMCR register  *******************/\n#define TIM_SMCR_SMS_Pos          (0U)\n#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */\n#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */\n#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */\n#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */\n#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */\n\n#define TIM_SMCR_TS_Pos           (4U)\n#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */\n#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */\n#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */\n#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */\n#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */\n\n#define TIM_SMCR_MSM_Pos          (7U)\n#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */\n#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */\n\n#define TIM_SMCR_ETF_Pos          (8U)\n#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */\n#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */\n#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */\n#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */\n#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */\n#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */\n\n#define TIM_SMCR_ETPS_Pos         (12U)\n#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */\n#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */\n#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */\n#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */\n\n#define TIM_SMCR_ECE_Pos          (14U)\n#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */\n#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */\n#define TIM_SMCR_ETP_Pos          (15U)\n#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */\n#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */\n\n/*******************  Bit definition for TIM_DIER register  *******************/\n#define TIM_DIER_UIE_Pos          (0U)\n#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */\n#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */\n#define TIM_DIER_CC1IE_Pos        (1U)\n#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */\n#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */\n#define TIM_DIER_CC2IE_Pos        (2U)\n#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */\n#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */\n#define TIM_DIER_CC3IE_Pos        (3U)\n#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */\n#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */\n#define TIM_DIER_CC4IE_Pos        (4U)\n#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */\n#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */\n#define TIM_DIER_COMIE_Pos        (5U)\n#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */\n#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */\n#define TIM_DIER_TIE_Pos          (6U)\n#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */\n#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */\n#define TIM_DIER_BIE_Pos          (7U)\n#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */\n#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */\n#define TIM_DIER_UDE_Pos          (8U)\n#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */\n#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */\n#define TIM_DIER_CC1DE_Pos        (9U)\n#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */\n#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */\n#define TIM_DIER_CC2DE_Pos        (10U)\n#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */\n#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */\n#define TIM_DIER_CC3DE_Pos        (11U)\n#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */\n#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */\n#define TIM_DIER_CC4DE_Pos        (12U)\n#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */\n#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */\n#define TIM_DIER_COMDE_Pos        (13U)\n#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */\n#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */\n#define TIM_DIER_TDE_Pos          (14U)\n#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */\n#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */\n\n/********************  Bit definition for TIM_SR register  ********************/\n#define TIM_SR_UIF_Pos            (0U)\n#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */\n#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */\n#define TIM_SR_CC1IF_Pos          (1U)\n#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */\n#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */\n#define TIM_SR_CC2IF_Pos          (2U)\n#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */\n#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */\n#define TIM_SR_CC3IF_Pos          (3U)\n#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */\n#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */\n#define TIM_SR_CC4IF_Pos          (4U)\n#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */\n#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */\n#define TIM_SR_COMIF_Pos          (5U)\n#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */\n#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */\n#define TIM_SR_TIF_Pos            (6U)\n#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */\n#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */\n#define TIM_SR_BIF_Pos            (7U)\n#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */\n#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */\n#define TIM_SR_CC1OF_Pos          (9U)\n#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */\n#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */\n#define TIM_SR_CC2OF_Pos          (10U)\n#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */\n#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */\n#define TIM_SR_CC3OF_Pos          (11U)\n#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */\n#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */\n#define TIM_SR_CC4OF_Pos          (12U)\n#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */\n#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */\n\n/*******************  Bit definition for TIM_EGR register  ********************/\n#define TIM_EGR_UG_Pos            (0U)\n#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */\n#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */\n#define TIM_EGR_CC1G_Pos          (1U)\n#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */\n#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */\n#define TIM_EGR_CC2G_Pos          (2U)\n#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */\n#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */\n#define TIM_EGR_CC3G_Pos          (3U)\n#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */\n#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */\n#define TIM_EGR_CC4G_Pos          (4U)\n#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */\n#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */\n#define TIM_EGR_COMG_Pos          (5U)\n#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */\n#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */\n#define TIM_EGR_TG_Pos            (6U)\n#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */\n#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */\n#define TIM_EGR_BG_Pos            (7U)\n#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */\n#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */\n\n/******************  Bit definition for TIM_CCMR1 register  *******************/\n#define TIM_CCMR1_CC1S_Pos        (0U)\n#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\n#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR1_OC1FE_Pos       (2U)\n#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */\n#define TIM_CCMR1_OC1PE_Pos       (3U)\n#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */\n\n#define TIM_CCMR1_OC1M_Pos        (4U)\n#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */\n#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR1_OC1CE_Pos       (7U)\n#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */\n\n#define TIM_CCMR1_CC2S_Pos        (8U)\n#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\n#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR1_OC2FE_Pos       (10U)\n#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */\n#define TIM_CCMR1_OC2PE_Pos       (11U)\n#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */\n\n#define TIM_CCMR1_OC2M_Pos        (12U)\n#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */\n#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR1_OC2CE_Pos       (15U)\n#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR1_IC1PSC_Pos      (2U)\n#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\n#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR1_IC1F_Pos        (4U)\n#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */\n#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR1_IC2PSC_Pos      (10U)\n#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */\n#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR1_IC2F_Pos        (12U)\n#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */\n#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */\n\n/******************  Bit definition for TIM_CCMR2 register  *******************/\n#define TIM_CCMR2_CC3S_Pos        (0U)\n#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */\n#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR2_OC3FE_Pos       (2U)\n#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */\n#define TIM_CCMR2_OC3PE_Pos       (3U)\n#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */\n\n#define TIM_CCMR2_OC3M_Pos        (4U)\n#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\n#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR2_OC3CE_Pos       (7U)\n#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */\n\n#define TIM_CCMR2_CC4S_Pos        (8U)\n#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\n#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR2_OC4FE_Pos       (10U)\n#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */\n#define TIM_CCMR2_OC4PE_Pos       (11U)\n#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */\n\n#define TIM_CCMR2_OC4M_Pos        (12U)\n#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\n#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR2_OC4CE_Pos       (15U)\n#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR2_IC3PSC_Pos      (2U)\n#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\n#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR2_IC3F_Pos        (4U)\n#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\n#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR2_IC4PSC_Pos      (10U)\n#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\n#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR2_IC4F_Pos        (12U)\n#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\n#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */\n\n/*******************  Bit definition for TIM_CCER register  *******************/\n#define TIM_CCER_CC1E_Pos         (0U)\n#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */\n#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */\n#define TIM_CCER_CC1P_Pos         (1U)\n#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */\n#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */\n#define TIM_CCER_CC1NE_Pos        (2U)\n#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */\n#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */\n#define TIM_CCER_CC1NP_Pos        (3U)\n#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */\n#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */\n#define TIM_CCER_CC2E_Pos         (4U)\n#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */\n#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */\n#define TIM_CCER_CC2P_Pos         (5U)\n#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */\n#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */\n#define TIM_CCER_CC2NE_Pos        (6U)\n#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */\n#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */\n#define TIM_CCER_CC2NP_Pos        (7U)\n#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */\n#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */\n#define TIM_CCER_CC3E_Pos         (8U)\n#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */\n#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */\n#define TIM_CCER_CC3P_Pos         (9U)\n#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */\n#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */\n#define TIM_CCER_CC3NE_Pos        (10U)\n#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */\n#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */\n#define TIM_CCER_CC3NP_Pos        (11U)\n#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */\n#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */\n#define TIM_CCER_CC4E_Pos         (12U)\n#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */\n#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */\n#define TIM_CCER_CC4P_Pos         (13U)\n#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */\n#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */\n#define TIM_CCER_CC4NP_Pos        (15U)\n#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */\n#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */\n\n/*******************  Bit definition for TIM_CNT register  ********************/\n#define TIM_CNT_CNT_Pos           (0U)\n#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0xFFFFFFFF */\n#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                                  /*!<Counter Value            */\n\n/*******************  Bit definition for TIM_PSC register  ********************/\n#define TIM_PSC_PSC_Pos           (0U)\n#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */\n#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */\n\n/*******************  Bit definition for TIM_ARR register  ********************/\n#define TIM_ARR_ARR_Pos           (0U)\n#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */\n#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */\n\n/*******************  Bit definition for TIM_RCR register  ********************/\n#define TIM_RCR_REP_Pos           (0U)\n#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */\n#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */\n\n/*******************  Bit definition for TIM_CCR1 register  *******************/\n#define TIM_CCR1_CCR1_Pos         (0U)\n#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */\n\n/*******************  Bit definition for TIM_CCR2 register  *******************/\n#define TIM_CCR2_CCR2_Pos         (0U)\n#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */\n\n/*******************  Bit definition for TIM_CCR3 register  *******************/\n#define TIM_CCR3_CCR3_Pos         (0U)\n#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */\n\n/*******************  Bit definition for TIM_CCR4 register  *******************/\n#define TIM_CCR4_CCR4_Pos         (0U)\n#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */\n\n/*******************  Bit definition for TIM_BDTR register  *******************/\n#define TIM_BDTR_DTG_Pos          (0U)\n#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */\n#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\n#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */\n#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */\n#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */\n#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */\n#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */\n#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */\n#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */\n#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */\n\n#define TIM_BDTR_LOCK_Pos         (8U)\n#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */\n#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */\n#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */\n#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */\n\n#define TIM_BDTR_OSSI_Pos         (10U)\n#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */\n#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */\n#define TIM_BDTR_OSSR_Pos         (11U)\n#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */\n#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */\n#define TIM_BDTR_BKE_Pos          (12U)\n#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */\n#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */\n#define TIM_BDTR_BKP_Pos          (13U)\n#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */\n#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */\n#define TIM_BDTR_AOE_Pos          (14U)\n#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */\n#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */\n#define TIM_BDTR_MOE_Pos          (15U)\n#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */\n#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */\n\n/*******************  Bit definition for TIM_DCR register  ********************/\n#define TIM_DCR_DBA_Pos           (0U)\n#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */\n#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */\n#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */\n#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */\n#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */\n#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */\n#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */\n\n#define TIM_DCR_DBL_Pos           (8U)\n#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */\n#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */\n#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */\n#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */\n#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */\n#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */\n#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */\n\n/*******************  Bit definition for TIM_DMAR register  *******************/\n#define TIM_DMAR_DMAB_Pos         (0U)\n#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */\n#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */\n\n/*******************  Bit definition for TIM_OR register  *********************/\n#define TIM_OR_TI1_RMP_Pos        (0U)\n#define TIM_OR_TI1_RMP_Msk        (0x3UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000003 */\n#define TIM_OR_TI1_RMP            TIM_OR_TI1_RMP_Msk                           /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */\n#define TIM_OR_TI1_RMP_0          (0x1UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000001 */\n#define TIM_OR_TI1_RMP_1          (0x2UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000002 */\n\n#define TIM_OR_TI4_RMP_Pos        (6U)\n#define TIM_OR_TI4_RMP_Msk        (0x3UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */\n#define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */\n#define TIM_OR_TI4_RMP_0          (0x1UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */\n#define TIM_OR_TI4_RMP_1          (0x2UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */\n#define TIM_OR_ITR1_RMP_Pos       (10U)\n#define TIM_OR_ITR1_RMP_Msk       (0x3UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */\n#define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\n#define TIM_OR_ITR1_RMP_0         (0x1UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */\n#define TIM_OR_ITR1_RMP_1         (0x2UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*         Universal Synchronous Asynchronous Receiver Transmitter            */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for USART_SR register  *******************/\n#define USART_SR_PE_Pos               (0U)\n#define USART_SR_PE_Msk               (0x1UL << USART_SR_PE_Pos)                /*!< 0x00000001 */\n#define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */\n#define USART_SR_FE_Pos               (1U)\n#define USART_SR_FE_Msk               (0x1UL << USART_SR_FE_Pos)                /*!< 0x00000002 */\n#define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */\n#define USART_SR_NE_Pos               (2U)\n#define USART_SR_NE_Msk               (0x1UL << USART_SR_NE_Pos)                /*!< 0x00000004 */\n#define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */\n#define USART_SR_ORE_Pos              (3U)\n#define USART_SR_ORE_Msk              (0x1UL << USART_SR_ORE_Pos)               /*!< 0x00000008 */\n#define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */\n#define USART_SR_IDLE_Pos             (4U)\n#define USART_SR_IDLE_Msk             (0x1UL << USART_SR_IDLE_Pos)              /*!< 0x00000010 */\n#define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */\n#define USART_SR_RXNE_Pos             (5U)\n#define USART_SR_RXNE_Msk             (0x1UL << USART_SR_RXNE_Pos)              /*!< 0x00000020 */\n#define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */\n#define USART_SR_TC_Pos               (6U)\n#define USART_SR_TC_Msk               (0x1UL << USART_SR_TC_Pos)                /*!< 0x00000040 */\n#define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */\n#define USART_SR_TXE_Pos              (7U)\n#define USART_SR_TXE_Msk              (0x1UL << USART_SR_TXE_Pos)               /*!< 0x00000080 */\n#define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */\n#define USART_SR_LBD_Pos              (8U)\n#define USART_SR_LBD_Msk              (0x1UL << USART_SR_LBD_Pos)               /*!< 0x00000100 */\n#define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */\n#define USART_SR_CTS_Pos              (9U)\n#define USART_SR_CTS_Msk              (0x1UL << USART_SR_CTS_Pos)               /*!< 0x00000200 */\n#define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */\n\n/*******************  Bit definition for USART_DR register  *******************/\n#define USART_DR_DR_Pos               (0U)\n#define USART_DR_DR_Msk               (0x1FFUL << USART_DR_DR_Pos)              /*!< 0x000001FF */\n#define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */\n\n/******************  Bit definition for USART_BRR register  *******************/\n#define USART_BRR_DIV_Fraction_Pos    (0U)\n#define USART_BRR_DIV_Fraction_Msk    (0xFUL << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */\n#define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */\n#define USART_BRR_DIV_Mantissa_Pos    (4U)\n#define USART_BRR_DIV_Mantissa_Msk    (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */\n#define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */\n\n/******************  Bit definition for USART_CR1 register  *******************/\n#define USART_CR1_SBK_Pos             (0U)\n#define USART_CR1_SBK_Msk             (0x1UL << USART_CR1_SBK_Pos)              /*!< 0x00000001 */\n#define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */\n#define USART_CR1_RWU_Pos             (1U)\n#define USART_CR1_RWU_Msk             (0x1UL << USART_CR1_RWU_Pos)              /*!< 0x00000002 */\n#define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */\n#define USART_CR1_RE_Pos              (2U)\n#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */\n#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */\n#define USART_CR1_TE_Pos              (3U)\n#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */\n#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */\n#define USART_CR1_IDLEIE_Pos          (4U)\n#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */\n#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */\n#define USART_CR1_RXNEIE_Pos          (5U)\n#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */\n#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */\n#define USART_CR1_TCIE_Pos            (6U)\n#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */\n#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */\n#define USART_CR1_TXEIE_Pos           (7U)\n#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */\n#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<TXE Interrupt Enable                   */\n#define USART_CR1_PEIE_Pos            (8U)\n#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */\n#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */\n#define USART_CR1_PS_Pos              (9U)\n#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */\n#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */\n#define USART_CR1_PCE_Pos             (10U)\n#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */\n#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */\n#define USART_CR1_WAKE_Pos            (11U)\n#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */\n#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */\n#define USART_CR1_M_Pos               (12U)\n#define USART_CR1_M_Msk               (0x1UL << USART_CR1_M_Pos)                /*!< 0x00001000 */\n#define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */\n#define USART_CR1_UE_Pos              (13U)\n#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00002000 */\n#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */\n#define USART_CR1_OVER8_Pos           (15U)\n#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */\n#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */\n\n/******************  Bit definition for USART_CR2 register  *******************/\n#define USART_CR2_ADD_Pos             (0U)\n#define USART_CR2_ADD_Msk             (0xFUL << USART_CR2_ADD_Pos)              /*!< 0x0000000F */\n#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */\n#define USART_CR2_LBDL_Pos            (5U)\n#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */\n#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */\n#define USART_CR2_LBDIE_Pos           (6U)\n#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */\n#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */\n#define USART_CR2_LBCL_Pos            (8U)\n#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */\n#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */\n#define USART_CR2_CPHA_Pos            (9U)\n#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */\n#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */\n#define USART_CR2_CPOL_Pos            (10U)\n#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */\n#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */\n#define USART_CR2_CLKEN_Pos           (11U)\n#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */\n#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */\n\n#define USART_CR2_STOP_Pos            (12U)\n#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */\n#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */\n#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x1000 */\n#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x2000 */\n\n#define USART_CR2_LINEN_Pos           (14U)\n#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */\n#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */\n\n/******************  Bit definition for USART_CR3 register  *******************/\n#define USART_CR3_EIE_Pos             (0U)\n#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */\n#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */\n#define USART_CR3_IREN_Pos            (1U)\n#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */\n#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */\n#define USART_CR3_IRLP_Pos            (2U)\n#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */\n#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */\n#define USART_CR3_HDSEL_Pos           (3U)\n#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */\n#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */\n#define USART_CR3_NACK_Pos            (4U)\n#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */\n#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */\n#define USART_CR3_SCEN_Pos            (5U)\n#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */\n#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */\n#define USART_CR3_DMAR_Pos            (6U)\n#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */\n#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */\n#define USART_CR3_DMAT_Pos            (7U)\n#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */\n#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */\n#define USART_CR3_RTSE_Pos            (8U)\n#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */\n#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */\n#define USART_CR3_CTSE_Pos            (9U)\n#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */\n#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */\n#define USART_CR3_CTSIE_Pos           (10U)\n#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */\n#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */\n#define USART_CR3_ONEBIT_Pos          (11U)\n#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */\n#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */\n\n/******************  Bit definition for USART_GTPR register  ******************/\n#define USART_GTPR_PSC_Pos            (0U)\n#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */\n#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */\n#define USART_GTPR_PSC_0              (0x01UL << USART_GTPR_PSC_Pos)            /*!< 0x0001 */\n#define USART_GTPR_PSC_1              (0x02UL << USART_GTPR_PSC_Pos)            /*!< 0x0002 */\n#define USART_GTPR_PSC_2              (0x04UL << USART_GTPR_PSC_Pos)            /*!< 0x0004 */\n#define USART_GTPR_PSC_3              (0x08UL << USART_GTPR_PSC_Pos)            /*!< 0x0008 */\n#define USART_GTPR_PSC_4              (0x10UL << USART_GTPR_PSC_Pos)            /*!< 0x0010 */\n#define USART_GTPR_PSC_5              (0x20UL << USART_GTPR_PSC_Pos)            /*!< 0x0020 */\n#define USART_GTPR_PSC_6              (0x40UL << USART_GTPR_PSC_Pos)            /*!< 0x0040 */\n#define USART_GTPR_PSC_7              (0x80UL << USART_GTPR_PSC_Pos)            /*!< 0x0080 */\n\n#define USART_GTPR_GT_Pos             (8U)\n#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */\n#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            Window WATCHDOG                                 */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for WWDG_CR register  ********************/\n#define WWDG_CR_T_Pos           (0U)\n#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */\n#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\n#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x01 */\n#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x02 */\n#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x04 */\n#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x08 */\n#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x10 */\n#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x20 */\n#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x40 */\n/* Legacy defines */\n#define  WWDG_CR_T0                          WWDG_CR_T_0\n#define  WWDG_CR_T1                          WWDG_CR_T_1\n#define  WWDG_CR_T2                          WWDG_CR_T_2\n#define  WWDG_CR_T3                          WWDG_CR_T_3\n#define  WWDG_CR_T4                          WWDG_CR_T_4\n#define  WWDG_CR_T5                          WWDG_CR_T_5\n#define  WWDG_CR_T6                          WWDG_CR_T_6\n\n#define WWDG_CR_WDGA_Pos        (7U)\n#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */\n#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */\n\n/*******************  Bit definition for WWDG_CFR register  *******************/\n#define WWDG_CFR_W_Pos          (0U)\n#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */\n#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */\n#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x0001 */\n#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x0002 */\n#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x0004 */\n#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x0008 */\n#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x0010 */\n#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x0020 */\n#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x0040 */\n/* Legacy defines */\n#define  WWDG_CFR_W0                         WWDG_CFR_W_0\n#define  WWDG_CFR_W1                         WWDG_CFR_W_1\n#define  WWDG_CFR_W2                         WWDG_CFR_W_2\n#define  WWDG_CFR_W3                         WWDG_CFR_W_3\n#define  WWDG_CFR_W4                         WWDG_CFR_W_4\n#define  WWDG_CFR_W5                         WWDG_CFR_W_5\n#define  WWDG_CFR_W6                         WWDG_CFR_W_6\n\n#define WWDG_CFR_WDGTB_Pos      (7U)\n#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */\n#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */\n#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */\n#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */\n/* Legacy defines */\n#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0\n#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1\n\n#define WWDG_CFR_EWI_Pos        (9U)\n#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */\n#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */\n\n/*******************  Bit definition for WWDG_SR register  ********************/\n#define WWDG_SR_EWIF_Pos        (0U)\n#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */\n#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                DBG                                         */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for DBGMCU_IDCODE register  *************/\n#define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)\n#define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\n#define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk\n#define DBGMCU_IDCODE_REV_ID_Pos                     (16U)\n#define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\n#define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk\n\n/********************  Bit definition for DBGMCU_CR register  *****************/\n#define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)\n#define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */\n#define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk\n#define DBGMCU_CR_DBG_STOP_Pos                       (1U)\n#define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk\n#define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)\n#define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */\n#define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk\n#define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)\n#define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */\n#define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk\n\n#define DBGMCU_CR_TRACE_MODE_Pos                     (6U)\n#define DBGMCU_CR_TRACE_MODE_Msk                     (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */\n#define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk\n#define DBGMCU_CR_TRACE_MODE_0                       (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */\n#define DBGMCU_CR_TRACE_MODE_1                       (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */\n\n/********************  Bit definition for DBGMCU_APB1_FZ register  ************/\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos    (24U)\n#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */\n#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk\n\n/********************  Bit definition for DBGMCU_APB2_FZ register  ************/\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                                       USB_OTG                              */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/\n#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)\n#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */\n#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)\n#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\n#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */\n#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)\n#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */\n#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)\n#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */\n#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */\n#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)\n#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */\n#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)\n#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */\n#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */\n#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)\n#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */\n#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)\n#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */\n#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)\n#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)\n#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */\n#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)\n#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)\n#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */\n#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */\n#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)\n#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */\n#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */\n#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)\n#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */\n#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */\n#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)\n#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */\n#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)\n#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */\n#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)\n#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */\n#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)\n#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */\n#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */\n\n/********************  Bit definition forUSB_OTG_HCFG register  ********************/\n\n#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)\n#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\n#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */\n#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCFG_FSLSS_Pos                   (2U)\n#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */\n\n/********************  Bit definition for USB_OTG_DCFG register  ********************/\n\n#define USB_OTG_DCFG_DSPD_Pos                    (0U)\n#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\n#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */\n#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)\n#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */\n\n#define USB_OTG_DCFG_DAD_Pos                     (4U)\n#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\n#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */\n#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\n\n#define USB_OTG_DCFG_PFIVL_Pos                   (11U)\n#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\n#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */\n#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\n\n#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)\n#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */\n#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk        /*!< Transceiver delay */\n\n#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)\n#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */\n#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk        /*!< Erratic error interrupt mask */\n\n#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)\n#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\n#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */\n#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\n#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\n\n/********************  Bit definition for USB_OTG_PCGCR register  ********************/\n#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)\n#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */\n#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)\n#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */\n#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)\n#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */\n\n/********************  Bit definition for USB_OTG_GOTGINT register  ********************/\n#define USB_OTG_GOTGINT_SEDET_Pos                (2U)\n#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */\n#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)\n#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */\n#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)\n#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */\n#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)\n#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */\n#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)\n#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */\n#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)\n#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */\n#define USB_OTG_GOTGINT_IDCHNG_Pos               (20U)\n#define USB_OTG_GOTGINT_IDCHNG_Msk               (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */\n#define USB_OTG_GOTGINT_IDCHNG                   USB_OTG_GOTGINT_IDCHNG_Msk    /*!< Change in ID pin input value           */\n\n/********************  Bit definition for USB_OTG_DCTL register  ********************/\n#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)\n#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */\n#define USB_OTG_DCTL_SDIS_Pos                    (1U)\n#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */\n#define USB_OTG_DCTL_GINSTS_Pos                  (2U)\n#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */\n#define USB_OTG_DCTL_GONSTS_Pos                  (3U)\n#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\n#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */\n\n#define USB_OTG_DCTL_TCTL_Pos                    (4U)\n#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\n#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */\n#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCTL_SGINAK_Pos                  (7U)\n#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */\n#define USB_OTG_DCTL_CGINAK_Pos                  (8U)\n#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */\n#define USB_OTG_DCTL_SGONAK_Pos                  (9U)\n#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */\n#define USB_OTG_DCTL_CGONAK_Pos                  (10U)\n#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\n#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */\n#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)\n#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */\n\n/********************  Bit definition for USB_OTG_HFIR register  ********************/\n#define USB_OTG_HFIR_FRIVL_Pos                   (0U)\n#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */\n\n/********************  Bit definition for USB_OTG_HFNUM register  ********************/\n#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)\n#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */\n#define USB_OTG_HFNUM_FTREM_Pos                  (16U)\n#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */\n\n/********************  Bit definition for USB_OTG_DSTS register  ********************/\n#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)\n#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */\n\n#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)\n#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\n#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */\n#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\n#define USB_OTG_DSTS_EERR_Pos                    (3U)\n#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\n#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */\n#define USB_OTG_DSTS_FNSOF_Pos                   (8U)\n#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\n#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */\n\n/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/\n#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)\n#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\n#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */\n#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)\n#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\n#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */\n#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */\n#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */\n#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */\n#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */\n#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */\n#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)\n#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */\n#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)\n#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */\n#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)\n#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\n#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */\n\n/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/\n\n#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)\n#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\n#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */\n#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\n#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\n#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\n#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)\n#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\n#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\n#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)\n#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\n#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */\n#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)\n#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\n#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */\n#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)\n#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\n#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */\n#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\n#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\n#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\n#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\n#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)\n#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */\n#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)\n#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\n#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */\n#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)\n#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\n#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */\n#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)\n#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\n#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */\n#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)\n#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\n#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */\n#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)\n#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\n#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */\n#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)\n#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\n#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */\n#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)\n#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\n#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */\n#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)\n#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\n#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */\n#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)\n#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\n#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */\n#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)\n#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */\n\n/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/\n#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)\n#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\n#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */\n#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)\n#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\n#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */\n#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)\n#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\n#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */\n#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)\n#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\n#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */\n#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)\n#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\n#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */\n\n\n#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)\n#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\n#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */\n#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\n#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\n#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)\n#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\n#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */\n#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)\n#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\n#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */\n\n/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/\n#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)\n#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)\n#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)\n#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)\n#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)\n#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/\n#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)\n#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */\n#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)\n#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */\n#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)\n#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */\n#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\n\n/********************  Bit definition for USB_OTG_HAINT register  ********************/\n#define USB_OTG_HAINT_HAINT_Pos                  (0U)\n#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */\n\n/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/\n#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask              */\n#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */\n#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)\n#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */\n#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */\n#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)\n#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */\n#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)\n#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */\n#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)\n#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */\n#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */\n#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)\n#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */\n#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)\n#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */\n#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)\n#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */\n#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)\n#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */\n#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)\n#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */\n/********************  Bit definition for USB_OTG_GINTSTS register  ********************/\n#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)\n#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\n#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */\n#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)\n#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */\n#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)\n#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */\n#define USB_OTG_GINTSTS_SOF_Pos                  (3U)\n#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */\n#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)\n#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */\n#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)\n#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */\n#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)\n#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */\n#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)\n#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */\n#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)\n#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */\n#define USB_OTG_GINTSTS_USBRST_Pos               (12U)\n#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */\n#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)\n#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */\n#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)\n#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */\n#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)\n#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */\n#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)\n#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */\n#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)\n#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */\n#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)\n#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */\n#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)\n#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */\n#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)\n#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */\n#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */\n#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)\n#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */\n#define USB_OTG_GINTSTS_HCINT_Pos                (25U)\n#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */\n#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)\n#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */\n#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)\n#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */\n#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */\n#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)\n#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */\n#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)\n#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */\n#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)\n#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */\n#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)\n#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */\n\n/********************  Bit definition for USB_OTG_GINTMSK register  ********************/\n#define USB_OTG_GINTMSK_MMISM_Pos                (1U)\n#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */\n#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)\n#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */\n#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)\n#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */\n#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)\n#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */\n#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)\n#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */\n#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)\n#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */\n#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)\n#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */\n#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)\n#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */\n#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)\n#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */\n#define USB_OTG_GINTMSK_USBRST_Pos               (12U)\n#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */\n#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)\n#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */\n#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)\n#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */\n#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)\n#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */\n#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)\n#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\n#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */\n#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)\n#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */\n#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)\n#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */\n#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)\n#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */\n#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)\n#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */\n#define USB_OTG_GINTMSK_RSTDETM_Pos              (23U)\n#define USB_OTG_GINTMSK_RSTDETM_Msk              (0x1UL << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */\n#define USB_OTG_GINTMSK_RSTDETM                  USB_OTG_GINTMSK_RSTDETM_Msk   /*!< Reset detected interrupt mask */\n#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)\n#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */\n#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)\n#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */\n#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)\n#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */\n#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)\n#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */\n#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */\n#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)\n#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */\n#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)\n#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */\n#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)\n#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */\n#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)\n#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */\n\n/********************  Bit definition for USB_OTG_DAINT register  ********************/\n#define USB_OTG_DAINT_IEPINT_Pos                 (0U)\n#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */\n#define USB_OTG_DAINT_OEPINT_Pos                 (16U)\n#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */\n\n/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/\n#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)\n#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */\n\n/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/\n#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)\n#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\n#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */\n#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)\n#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\n#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)\n#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\n#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)\n#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/\n#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)\n#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */\n#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)\n#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/\n#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)\n#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/\n#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)\n#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */\n\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_NPTXFSA_Pos                      (0U)\n#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */\n#define USB_OTG_NPTXFD_Pos                       (16U)\n#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */\n#define USB_OTG_TX0FSA_Pos                       (0U)\n#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */\n#define USB_OTG_TX0FD_Pos                        (16U)\n#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */\n\n/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/\n#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)\n#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\n#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\n\n/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\n\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/\n#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)\n#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\n#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\n#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)\n#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\n#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */\n\n#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)\n#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\n#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */\n#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)\n#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\n#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */\n\n#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)\n#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */\n#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\n#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)\n#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\n#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */\n\n/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DEACHINT register  ********************/\n#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)\n#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */\n#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)\n#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */\n\n/********************  Bit definition for USB_OTG_GCCFG register  ********************/\n#define USB_OTG_GCCFG_DCDET_Pos                  (0U)\n#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */\n#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */\n#define USB_OTG_GCCFG_PDET_Pos                   (1U)\n#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */\n#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */\n#define USB_OTG_GCCFG_SDET_Pos                   (2U)\n#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */\n#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */\n#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)\n#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */\n#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */\n#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)\n#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\n#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */\n#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)\n#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */\n#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)\n#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/\n#define USB_OTG_GCCFG_PDEN_Pos                   (19U)\n#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/\n#define USB_OTG_GCCFG_SDEN_Pos                   (20U)\n#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */\n#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)\n#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< USB VBUS Detection Enable */\n\n/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\n\n/********************  Bit definition for USB_OTG_CID register  ********************/\n#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)\n#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */\n\n/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/\n#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)\n#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */\n#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */\n#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)\n#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */\n#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */\n#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)\n#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */\n#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */\n#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)\n#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */\n#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */\n#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)\n#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */\n#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)\n#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */\n#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */\n#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)\n#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */\n#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */\n#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)\n#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */\n#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */\n#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)\n#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */\n#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)\n#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */\n#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */\n#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)\n#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */\n#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)\n#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */\n#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */\n#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)\n#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */\n#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */\n#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)\n#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */\n#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */\n\n/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */\n#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPRT register  ********************/\n#define USB_OTG_HPRT_PCSTS_Pos                   (0U)\n#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */\n#define USB_OTG_HPRT_PCDET_Pos                   (1U)\n#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\n#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */\n#define USB_OTG_HPRT_PENA_Pos                    (2U)\n#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\n#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */\n#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)\n#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\n#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */\n#define USB_OTG_HPRT_POCA_Pos                    (4U)\n#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\n#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */\n#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)\n#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\n#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */\n#define USB_OTG_HPRT_PRES_Pos                    (6U)\n#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\n#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */\n#define USB_OTG_HPRT_PSUSP_Pos                   (7U)\n#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\n#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */\n#define USB_OTG_HPRT_PRST_Pos                    (8U)\n#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\n#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */\n\n#define USB_OTG_HPRT_PLSTS_Pos                   (10U)\n#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\n#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */\n#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\n#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_HPRT_PPWR_Pos                    (12U)\n#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */\n\n#define USB_OTG_HPRT_PTCTL_Pos                   (13U)\n#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\n#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */\n#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\n#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\n#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\n#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\n\n#define USB_OTG_HPRT_PSPD_Pos                    (17U)\n#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\n#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */\n#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\n\n/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */\n#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */\n#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */\n#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)\n#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */\n#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)\n#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */\n\n/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/\n#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)\n#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */\n#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)\n#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */\n\n/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/\n#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */\n#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */\n#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)\n#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\n#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */\n#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */\n\n#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */\n#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DIEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */\n\n#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)\n#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\n#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */\n#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\n#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\n#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\n#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\n#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */\n#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */\n#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */\n#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */\n#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */\n\n/********************  Bit definition for USB_OTG_HCCHAR register  ********************/\n#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)\n#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */\n\n#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)\n#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\n#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */\n#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\n#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)\n#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */\n#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)\n#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */\n\n#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)\n#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */\n#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\n\n#define USB_OTG_HCCHAR_MC_Pos                    (20U)\n#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\n#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */\n#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\n#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\n\n#define USB_OTG_HCCHAR_DAD_Pos                   (22U)\n#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\n#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */\n#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\n#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\n#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\n#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\n#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\n#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\n#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\n#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)\n#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */\n#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)\n#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */\n#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)\n#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */\n\n/********************  Bit definition for USB_OTG_HCSPLT register  ********************/\n\n#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)\n#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\n#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */\n#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\n\n#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)\n#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\n#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */\n#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\n\n#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)\n#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\n#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */\n#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)\n#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\n#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */\n#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)\n#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */\n\n/********************  Bit definition for USB_OTG_HCINT register  ********************/\n#define USB_OTG_HCINT_XFRC_Pos                   (0U)\n#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */\n#define USB_OTG_HCINT_CHH_Pos                    (1U)\n#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */\n#define USB_OTG_HCINT_AHBERR_Pos                 (2U)\n#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */\n#define USB_OTG_HCINT_STALL_Pos                  (3U)\n#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */\n#define USB_OTG_HCINT_NAK_Pos                    (4U)\n#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */\n#define USB_OTG_HCINT_ACK_Pos                    (5U)\n#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */\n#define USB_OTG_HCINT_NYET_Pos                   (6U)\n#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */\n#define USB_OTG_HCINT_TXERR_Pos                  (7U)\n#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */\n#define USB_OTG_HCINT_BBERR_Pos                  (8U)\n#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */\n#define USB_OTG_HCINT_FRMOR_Pos                  (9U)\n#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */\n#define USB_OTG_HCINT_DTERR_Pos                  (10U)\n#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */\n\n/********************  Bit definition for USB_OTG_DIEPINT register  ********************/\n#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)\n#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */\n#define USB_OTG_DIEPINT_TOC_Pos                  (3U)\n#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */\n#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)\n#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */\n#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)\n#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */\n#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */\n#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)\n#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */\n#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)\n#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\n#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\n#define USB_OTG_DIEPINT_BNA_Pos                  (9U)\n#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */\n#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)\n#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\n#define USB_OTG_DIEPINT_BERR_Pos                 (12U)\n#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\n#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */\n#define USB_OTG_DIEPINT_NAK_Pos                  (13U)\n#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */\n\n/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/\n#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)\n#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */\n#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)\n#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */\n#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)\n#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */\n#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)\n#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */\n#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)\n#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */\n#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)\n#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */\n#define USB_OTG_HCINTMSK_NYET_Pos                (6U)\n#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */\n#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)\n#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */\n#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)\n#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */\n#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)\n#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */\n#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)\n#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */\n\n/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/\n\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)\n#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */\n/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/\n#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)\n#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */\n#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)\n#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */\n#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)\n#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */\n#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)\n#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\n#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */\n#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/\n#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)\n#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_HCDMA register  ********************/\n#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)\n#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/\n#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)\n#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */\n\n/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/\n#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)\n#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */\n#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)\n#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/\n\n#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */\n#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */\n#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\n#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */\n#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */\n#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)\n#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\n#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */\n#define USB_OTG_DOEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */\n#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */\n#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */\n#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */\n\n/********************  Bit definition for USB_OTG_DOEPINT register  ********************/\n#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)\n#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */\n#define USB_OTG_DOEPINT_STUP_Pos                 (3U)\n#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */\n#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)\n#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */\n#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)\n#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */\n#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */\n#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)\n#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */\n#define USB_OTG_DOEPINT_NAK_Pos                  (13U)\n#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */\n#define USB_OTG_DOEPINT_NYET_Pos                 (14U)\n#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */\n#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)\n#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */\n/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/\n\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n\n#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)\n#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */\n#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for PCGCCTL register  ********************/\n#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)\n#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */\n#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)\n#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */\n#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)\n#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */\n\n/* Legacy define */\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_CHNUM_Pos                        (0U)\n#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\n#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\n#define USB_OTG_BCNT_Pos                         (4U)\n#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\n\n#define USB_OTG_DPID_Pos                         (15U)\n#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)    /*!< 0x00018000 */\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\n#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\n#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\n\n#define USB_OTG_PKTSTS_Pos                       (17U)\n#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\n#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\n#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\n#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\n#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\n\n#define USB_OTG_EPNUM_Pos                        (0U)\n#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\n#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\n\n#define USB_OTG_FRMNUM_Pos                       (21U)\n#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\n#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\n#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\n#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\n#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_macros\n  * @{\n  */\n\n/******************************* ADC Instances ********************************/\n#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\n\n#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)\n\n/******************************* CAN Instances ********************************/\n#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \\\n                                       ((INSTANCE) == CAN2))\n\n/****************************** DFSDM Instances *******************************/\n#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \\\n                                                ((INSTANCE) == DFSDM1_Filter1))\n\n#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel1) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel2) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel3))\n/******************************* CRC Instances ********************************/\n#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\n\n\n/******************************** DMA Instances *******************************/\n#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \\\n                                              ((INSTANCE) == DMA1_Stream1) || \\\n                                              ((INSTANCE) == DMA1_Stream2) || \\\n                                              ((INSTANCE) == DMA1_Stream3) || \\\n                                              ((INSTANCE) == DMA1_Stream4) || \\\n                                              ((INSTANCE) == DMA1_Stream5) || \\\n                                              ((INSTANCE) == DMA1_Stream6) || \\\n                                              ((INSTANCE) == DMA1_Stream7) || \\\n                                              ((INSTANCE) == DMA2_Stream0) || \\\n                                              ((INSTANCE) == DMA2_Stream1) || \\\n                                              ((INSTANCE) == DMA2_Stream2) || \\\n                                              ((INSTANCE) == DMA2_Stream3) || \\\n                                              ((INSTANCE) == DMA2_Stream4) || \\\n                                              ((INSTANCE) == DMA2_Stream5) || \\\n                                              ((INSTANCE) == DMA2_Stream6) || \\\n                                              ((INSTANCE) == DMA2_Stream7))\n\n/******************************* GPIO Instances *******************************/\n#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\\n                                        ((INSTANCE) == GPIOB) || \\\n                                        ((INSTANCE) == GPIOC) || \\\n                                        ((INSTANCE) == GPIOD) || \\\n                                        ((INSTANCE) == GPIOH))\n\n/******************************** I2C Instances *******************************/\n#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\n                                       ((INSTANCE) == I2C2) || \\\n                                       ((INSTANCE) == I2C3))\n\n/******************************* SMBUS Instances ******************************/\n#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE\n\n/******************************** I2S Instances *******************************/\n#define IS_I2S_APB1_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \\\n                                         ((INSTANCE) == SPI3))\n\n#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI1) || \\\n                                        ((INSTANCE) == SPI2) || \\\n                                        ((INSTANCE) == SPI3) || \\\n                                        ((INSTANCE) == SPI4) || \\\n                                        ((INSTANCE) == SPI5))\n\n/*************************** I2S Extended Instances ***************************/\n#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \\\n                                           ((INSTANCE) == I2S3ext))\n/* Legacy Defines */\n#define IS_I2S_ALL_INSTANCE_EXT    IS_I2S_EXT_ALL_INSTANCE\n\n/******************************* RNG Instances ********************************/\n#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)\n\n/****************************** RTC Instances *********************************/\n#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\n\n\n/******************************** SPI Instances *******************************/\n\n#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\\n                                       ((INSTANCE) == SPI2) || \\\n                                       ((INSTANCE) == SPI3) || \\\n                                       ((INSTANCE) == SPI4) || \\\n                                       ((INSTANCE) == SPI5))\n\n\n/****************** TIM Instances : All supported instances *******************/\n#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                    ((INSTANCE) == TIM2) || \\\n                                    ((INSTANCE) == TIM3) || \\\n                                    ((INSTANCE) == TIM4) || \\\n                                    ((INSTANCE) == TIM5) || \\\n                                    ((INSTANCE) == TIM6) || \\\n                                    ((INSTANCE) == TIM7) || \\\n                                    ((INSTANCE) == TIM8) || \\\n                                    ((INSTANCE) == TIM9) || \\\n                                    ((INSTANCE) == TIM10)|| \\\n                                    ((INSTANCE) == TIM11)|| \\\n                                    ((INSTANCE) == TIM12)|| \\\n                                    ((INSTANCE) == TIM13)|| \\\n                                    ((INSTANCE) == TIM14))\n\n/************* TIM Instances : at least 1 capture/compare channel *************/\n#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \\\n                                         ((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM3)  || \\\n                                         ((INSTANCE) == TIM4)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM8)  || \\\n                                         ((INSTANCE) == TIM9)  || \\\n                                         ((INSTANCE) == TIM10) || \\\n                                         ((INSTANCE) == TIM11) || \\\n                                         ((INSTANCE) == TIM12) || \\\n                                         ((INSTANCE) == TIM13) || \\\n                                         ((INSTANCE) == TIM14))\n\n/************ TIM Instances : at least 2 capture/compare channels *************/\n#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8) || \\\n                                       ((INSTANCE) == TIM9) || \\\n                                       ((INSTANCE) == TIM12))\n\n/************ TIM Instances : at least 3 capture/compare channels *************/\n#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/************ TIM Instances : at least 4 capture/compare channels *************/\n#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : Advanced-control timers *****************/\n#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                           ((INSTANCE) == TIM8))\n\n/******************* TIM Instances : Timer input XOR function *****************/\n#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : DMA requests generation (UDE) *************/\n#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM6) || \\\n                                       ((INSTANCE) == TIM7) || \\\n                                       ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (CCxDE) *****************/\n#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (COMDE) *****************/\n#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : DMA burst feature ***********************/\n#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                             ((INSTANCE) == TIM2) || \\\n                                             ((INSTANCE) == TIM3) || \\\n                                             ((INSTANCE) == TIM4) || \\\n                                             ((INSTANCE) == TIM5) || \\\n                                             ((INSTANCE) == TIM8))\n\n/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\n#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                          ((INSTANCE) == TIM2)  || \\\n                                          ((INSTANCE) == TIM3)  || \\\n                                          ((INSTANCE) == TIM4)  || \\\n                                          ((INSTANCE) == TIM5)  || \\\n                                          ((INSTANCE) == TIM6)  || \\\n                                          ((INSTANCE) == TIM8))\n\n/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\n#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8) || \\\n                                         ((INSTANCE) == TIM9) || \\\n                                         ((INSTANCE) == TIM12))\n/********************** TIM Instances : 32 bit Counter ************************/\n#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \\\n                                              ((INSTANCE) == TIM5))\n\n/***************** TIM Instances : external trigger input availabe ************/\n#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                        ((INSTANCE) == TIM2) || \\\n                                        ((INSTANCE) == TIM3) || \\\n                                        ((INSTANCE) == TIM4) || \\\n                                        ((INSTANCE) == TIM5) || \\\n                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : remapping capability **********************/\n#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM11))\n\n/******************* TIM Instances : output(s) available **********************/\n#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\\n    ((((INSTANCE) == TIM1) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM2) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM3) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM4) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM5) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM8) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM9) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM10) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM11) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM12) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM13) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM14) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1))))\n\n/************ TIM Instances : complementary output(s) available ***************/\n#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\\n   ((((INSTANCE) == TIM1) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3)))            \\\n    ||                                          \\\n    (((INSTANCE) == TIM8) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3))))\n\n/****************** TIM Instances : supporting counting mode selection ********/\n#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting clock division *****************/\n#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                                  ((INSTANCE) == TIM2) || \\\n                                                  ((INSTANCE) == TIM3) || \\\n                                                  ((INSTANCE) == TIM4) || \\\n                                                  ((INSTANCE) == TIM5) || \\\n                                                  ((INSTANCE) == TIM8) || \\\n                                                  ((INSTANCE) == TIM9) || \\\n                                                  ((INSTANCE) == TIM10)|| \\\n                                                  ((INSTANCE) == TIM11)|| \\\n                                                  ((INSTANCE) == TIM12)|| \\\n                                                  ((INSTANCE) == TIM13)|| \\\n                                                  ((INSTANCE) == TIM14))\n\n/****************** TIM Instances : supporting commutation event generation ***/\n#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \\\n                                                     ((INSTANCE) == TIM8))\n\n\n/****************** TIM Instances : supporting OCxREF clear *******************/\n#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM2) || \\\n                                                       ((INSTANCE) == TIM3) || \\\n                                                       ((INSTANCE) == TIM4) || \\\n                                                       ((INSTANCE) == TIM5) || \\\n                                                       ((INSTANCE) == TIM8))\n\n/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8))\n\n/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/\n#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/********** TIM Instances : supporting internal trigger inputs(ITRX) *********/\n#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/****************** TIM Instances : supporting repetition counter *************/\n#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting encoder interface **************/\n#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                      ((INSTANCE) == TIM2) || \\\n                                                      ((INSTANCE) == TIM3) || \\\n                                                      ((INSTANCE) == TIM4) || \\\n                                                      ((INSTANCE) == TIM5) || \\\n                                                      ((INSTANCE) == TIM8) || \\\n                                                      ((INSTANCE) == TIM9) || \\\n                                                      ((INSTANCE) == TIM12))\n/****************** TIM Instances : supporting Hall sensor interface **********/\n#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                          ((INSTANCE) == TIM2) || \\\n                                                          ((INSTANCE) == TIM3) || \\\n                                                          ((INSTANCE) == TIM4) || \\\n                                                          ((INSTANCE) == TIM5) || \\\n                                                          ((INSTANCE) == TIM8))\n/****************** TIM Instances : supporting the break function *************/\n#define IS_TIM_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM8))\n\n/******************** USART Instances : Synchronous mode **********************/\n#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                     ((INSTANCE) == USART2) || \\\n                                     ((INSTANCE) == USART3) || \\\n                                     ((INSTANCE) == USART6))\n\n/******************** UART Instances : Half-Duplex mode **********************/\n#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                               ((INSTANCE) == USART2) || \\\n                                               ((INSTANCE) == USART3) || \\\n                                               ((INSTANCE) == USART6))\n\n/* Legacy defines */\n#define IS_UART_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE\n\n/****************** UART Instances : Hardware Flow control ********************/\n#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                           ((INSTANCE) == USART2) || \\\n                                           ((INSTANCE) == USART3))\n/******************** UART Instances : LIN mode **********************/\n#define IS_UART_LIN_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE\n\n/********************* UART Instances : Smart card mode ***********************/\n#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                         ((INSTANCE) == USART2) || \\\n                                         ((INSTANCE) == USART3) || \\\n                                         ((INSTANCE) == USART6))\n\n/*********************** UART Instances : IRDA mode ***************************/\n#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2) || \\\n                                    ((INSTANCE) == USART3) || \\\n                                    ((INSTANCE) == USART6))\n\n/*********************** PCD Instances ****************************************/\n#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))\n\n/*********************** HCD Instances ****************************************/\n#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))\n\n/****************************** SDIO Instances ********************************/\n#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)\n\n/****************************** IWDG Instances ********************************/\n#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)\n\n/****************************** WWDG Instances ********************************/\n#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)\n\n\n/***************************** FMPI2C Instances *******************************/\n#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)\n#define IS_FMPSMBUS_ALL_INSTANCE         IS_FMPI2C_ALL_INSTANCE\n\n/****************************** QSPI Instances ********************************/\n#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)\n/****************************** USB Exported Constants ************************/\n#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                12U\n#define USB_OTG_FS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */\n#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */\n#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */\n\n/*\n * @brief Specific devices reset values definitions\n */\n#define RCC_PLLCFGR_RST_VALUE              0x24003010U\n#define RCC_PLLI2SCFGR_RST_VALUE           0x24003010U\n\n#define RCC_MAX_FREQUENCY           100000000U         /*!< Max frequency of family in Hz*/\n#define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */\n#define RCC_MAX_FREQUENCY_SCALE2     84000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */\n#define RCC_MAX_FREQUENCY_SCALE3     64000000U         /*!< Maximum frequency for system clock at power scale3, in Hz */\n#define RCC_PLLVCO_OUTPUT_MIN       100000000U       /*!< Frequency min for PLLVCO output, in Hz */\n#define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */\n\n#define RCC_PLLN_MIN_VALUE                 50U\n#define RCC_PLLN_MAX_VALUE                432U\n\n#define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */\n#define FLASH_SCALE1_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */\n#define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */\n\n#define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */\n#define FLASH_SCALE2_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */\n\n#define FLASH_SCALE3_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */\n#define FLASH_SCALE3_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */\n\n/******************************************************************************/\n/*  For a painless codes migration between the STM32F4xx device product       */\n/*  lines, the aliases defined below are put in place to overcome the         */\n/*  differences in the interrupt handlers and IRQn definitions.               */\n/*  No need to update developed interrupt code when moving across             */\n/*  product lines within the same STM32F4 Family                              */\n/******************************************************************************/\n/* Aliases for __IRQn */\n#define FMC_IRQn              FSMC_IRQn\n\n/* Aliases for __IRQHandler */\n#define FMC_IRQHandler        FSMC_IRQHandler\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32F412Rx_H */\n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f412zx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f412zx.h\n  * @author  MCD Application Team\n  * @version V2.6.4\n  * @date    06-December-2019\n  * @brief   CMSIS STM32F412Zx Device Peripheral Access Layer Header File.\n  *\n  *          This file contains:\n  *           - Data structures and the address mapping for all peripherals\n  *           - peripherals registers declarations and bits definition\n  *           - Macros to access peripheral's registers hardware\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS_Device\n  * @{\n  */\n\n/** @addtogroup stm32f412zx\n  * @{\n  */\n\n#ifndef __STM32F412Zx_H\n#define __STM32F412Zx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Configuration_section_for_CMSIS\n  * @{\n  */\n\n/**\n  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals\n  */\n#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */\n#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */\n#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */\n#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */\n#define __FPU_PRESENT             1U       /*!< FPU present                                   */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_interrupt_number_definition\n  * @{\n  */\n\n/**\n * @brief STM32F4XX Interrupt Number Definition, according to the selected device\n *        in @ref Library_configuration_section\n */\ntypedef enum\n{\n/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */\n  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */\n  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */\n  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */\n  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */\n  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */\n/******  STM32 specific Interrupt Numbers **********************************************************************/\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */\n  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */\n  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\n  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\n  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\n  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\n  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\n  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\n  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\n  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\n  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\n  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */\n  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */\n  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */\n  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */\n  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */\n  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */\n  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */\n  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */\n  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */\n  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */\n  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */\n  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\n  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */\n  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */\n  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\n  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\n  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */\n  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */\n  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */\n  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\n  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */\n  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */\n  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\n  TIM6_IRQn                   = 54,     /*!< TIM6 global interrupt                                             */\n  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */\n  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */\n  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */\n  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */\n  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */\n  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */\n  DFSDM1_FLT0_IRQn            = 61,     /*!< DFSDM1 Filter 0 global Interrupt                                  */\n  DFSDM1_FLT1_IRQn            = 62,     /*!< DFSDM1 Filter 1 global Interrupt                                  */\n  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */\n  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */\n  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */\n  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */\n  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */\n  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */\n  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */\n  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */\n  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */\n  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\n  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\n  RNG_IRQn                    = 80,     /*!< RNG global Interrupt                                              */\n  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */\n  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */\n  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */\n  QUADSPI_IRQn                = 92,     /*!< QuadSPI global Interrupt                                          */\n  FMPI2C1_EV_IRQn             = 95,     /*!< FMPI2C1 Event Interrupt                                           */\n  FMPI2C1_ER_IRQn             = 96      /*!< FMPI2C1 Error Interrupt                                           */\n} IRQn_Type;\n\n/**\n  * @}\n  */\n\n#include \"core_cm4.h\"             /* Cortex-M4 processor and core peripherals */\n#include \"system_stm32f4xx.h\"\n#include <sys/stdint.h>\n\n/** @addtogroup Peripheral_registers_structures\n  * @{\n  */\n\n/**\n  * @brief Analog to Digital Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */\n  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */\n  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */\n  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */\n  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */\n  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\n  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\n  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\n  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\n  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */\n  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */\n  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */\n  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */\n  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */\n  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/\n  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */\n  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */\n  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */\n  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */\n  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */\n} ADC_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */\n  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */\n  __IO uint32_t CDR;    /*!< ADC common regular data register for dual\n                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */\n} ADC_Common_TypeDef;\n\n\n/**\n  * @brief Controller Area Network TxMailBox\n  */\n\ntypedef struct\n{\n  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */\n  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\n  __IO uint32_t TDLR; /*!< CAN mailbox data low register */\n  __IO uint32_t TDHR; /*!< CAN mailbox data high register */\n} CAN_TxMailBox_TypeDef;\n\n/**\n  * @brief Controller Area Network FIFOMailBox\n  */\n\ntypedef struct\n{\n  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */\n  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\n  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\n  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\n} CAN_FIFOMailBox_TypeDef;\n\n/**\n  * @brief Controller Area Network FilterRegister\n  */\n\ntypedef struct\n{\n  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\n  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\n} CAN_FilterRegister_TypeDef;\n\n/**\n  * @brief Controller Area Network\n  */\n\ntypedef struct\n{\n  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */\n  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */\n  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */\n  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */\n  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */\n  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */\n  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */\n  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */\n  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */\n  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */\n  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */\n  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */\n  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */\n  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */\n  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */\n  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */\n  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */\n  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */\n  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */\n  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */\n  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */\n  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */\n} CAN_TypeDef;\n\n/**\n  * @brief CRC calculation unit\n  */\n\ntypedef struct\n{\n  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */\n  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */\n  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */\n  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */\n  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */\n} CRC_TypeDef;\n\n/**\n  * @brief DFSDM module registers\n  */\ntypedef struct\n{\n  __IO uint32_t FLTCR1;      /*!< DFSDM control register1,                          Address offset: 0x100 */\n  __IO uint32_t FLTCR2;      /*!< DFSDM control register2,                          Address offset: 0x104 */\n  __IO uint32_t FLTISR;      /*!< DFSDM interrupt and status register,              Address offset: 0x108 */\n  __IO uint32_t FLTICR;      /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */\n  __IO uint32_t FLTJCHGR;    /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */\n  __IO uint32_t FLTFCR;      /*!< DFSDM filter control register,                    Address offset: 0x114 */\n  __IO uint32_t FLTJDATAR;   /*!< DFSDM data register for injected group,           Address offset: 0x118 */\n  __IO uint32_t FLTRDATAR;   /*!< DFSDM data register for regular group,            Address offset: 0x11C */\n  __IO uint32_t FLTAWHTR;    /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */\n  __IO uint32_t FLTAWLTR;    /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */\n  __IO uint32_t FLTAWSR;     /*!< DFSDM analog watchdog status register             Address offset: 0x128 */\n  __IO uint32_t FLTAWCFR;    /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */\n  __IO uint32_t FLTEXMAX;    /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */\n  __IO uint32_t FLTEXMIN;    /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */\n  __IO uint32_t FLTCNVTIMR;  /*!< DFSDM conversion timer,                           Address offset: 0x138 */\n} DFSDM_Filter_TypeDef;\n\n/**\n  * @brief DFSDM channel configuration registers\n  */\ntypedef struct\n{\n  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */\n  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */\n  __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and\n                                  short circuit detector register,                  Address offset: 0x08 */\n  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */\n  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */\n} DFSDM_Channel_TypeDef;\n\n/**\n  * @brief Debug MCU\n  */\n\ntypedef struct\n{\n  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */\n  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */\n  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */\n  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */\n}DBGMCU_TypeDef;\n\n\n/**\n  * @brief DMA Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;     /*!< DMA stream x configuration register      */\n  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */\n  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */\n  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */\n  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */\n  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */\n} DMA_Stream_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */\n  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */\n  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */\n  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\n} DMA_TypeDef;\n\n/**\n  * @brief External Interrupt/Event Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */\n  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */\n  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */\n  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\n  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */\n  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */\n} EXTI_TypeDef;\n\n/**\n  * @brief FLASH Registers\n  */\n\ntypedef struct\n{\n  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */\n  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */\n  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */\n  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */\n  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */\n  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */\n  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */\n} FLASH_TypeDef;\n\n\n\n/**\n  * @brief Flexible Static Memory Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\n} FSMC_Bank1_TypeDef;\n\n/**\n  * @brief Flexible Static Memory Controller Bank1E\n  */\n\ntypedef struct\n{\n  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\n} FSMC_Bank1E_TypeDef;\n/**\n  * @brief General Purpose I/O\n  */\n\ntypedef struct\n{\n  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */\n  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */\n  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */\n  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\n  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */\n  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */\n  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */\n  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */\n  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\n} GPIO_TypeDef;\n\n/**\n  * @brief System configuration controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */\n  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */\n  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\n  uint32_t      RESERVED;     /*!< Reserved, 0x18                                                               */\n  __IO uint32_t CFGR2;        /*!< SYSCFG Configuration register2,                    Address offset: 0x1C      */\n  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */\n  __IO uint32_t CFGR;         /*!< SYSCFG Configuration register,                     Address offset: 0x24      */\n} SYSCFG_TypeDef;\n\n/**\n  * @brief Inter-integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */\n  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */\n  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */\n  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */\n  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */\n  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */\n  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */\n  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */\n  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */\n} I2C_TypeDef;\n\n/**\n  * @brief Inter-integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< FMPI2C Control register 1,            Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< FMPI2C Control register 2,            Address offset: 0x04 */\n  __IO uint32_t OAR1;        /*!< FMPI2C Own address 1 register,        Address offset: 0x08 */\n  __IO uint32_t OAR2;        /*!< FMPI2C Own address 2 register,        Address offset: 0x0C */\n  __IO uint32_t TIMINGR;     /*!< FMPI2C Timing register,               Address offset: 0x10 */\n  __IO uint32_t TIMEOUTR;    /*!< FMPI2C Timeout register,              Address offset: 0x14 */\n  __IO uint32_t ISR;         /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */\n  __IO uint32_t ICR;         /*!< FMPI2C Interrupt clear register,      Address offset: 0x1C */\n  __IO uint32_t PECR;        /*!< FMPI2C PEC register,                  Address offset: 0x20 */\n  __IO uint32_t RXDR;        /*!< FMPI2C Receive data register,         Address offset: 0x24 */\n  __IO uint32_t TXDR;        /*!< FMPI2C Transmit data register,        Address offset: 0x28 */\n} FMPI2C_TypeDef;\n\n/**\n  * @brief Independent WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */\n  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */\n  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */\n  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */\n} IWDG_TypeDef;\n\n\n/**\n  * @brief Power Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */\n  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */\n} PWR_TypeDef;\n\n/**\n  * @brief Reset and Clock Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */\n  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */\n  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */\n  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */\n  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */\n  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */\n  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */\n  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */\n  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */\n  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */\n  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */\n  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */\n  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */\n  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */\n  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */\n  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */\n  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */\n  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\n  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\n  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\n  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */\n  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\n  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\n  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */\n  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */\n  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */\n  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */\n  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */\n  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */\n  uint32_t      RESERVED7;     /*!< Reserved, 0x88                                                                    */\n  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */\n  __IO uint32_t CKGATENR;      /*!< RCC Clocks Gated ENable Register,                           Address offset: 0x90  */\n  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x94 */\n} RCC_TypeDef;\n\n/**\n  * @brief Real-Time Clock\n  */\n\ntypedef struct\n{\n  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */\n  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */\n  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */\n  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */\n  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */\n  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */\n  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */\n  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */\n  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */\n  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */\n  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */\n  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */\n  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */\n  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */\n  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */\n  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */\n  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */\n  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */\n  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */\n  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */\n  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */\n  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */\n  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */\n  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */\n  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */\n  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */\n  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */\n  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */\n  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */\n  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */\n  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */\n  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */\n  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */\n  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */\n  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */\n  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */\n  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */\n  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */\n  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */\n  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */\n} RTC_TypeDef;\n\n/**\n  * @brief SD host Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t POWER;                 /*!< SDIO power control register,    Address offset: 0x00 */\n  __IO uint32_t CLKCR;                 /*!< SDI clock control register,     Address offset: 0x04 */\n  __IO uint32_t ARG;                   /*!< SDIO argument register,         Address offset: 0x08 */\n  __IO uint32_t CMD;                   /*!< SDIO command register,          Address offset: 0x0C */\n  __IO const uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */\n  __IO const uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */\n  __IO const uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */\n  __IO const uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */\n  __IO const uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */\n  __IO uint32_t DTIMER;                /*!< SDIO data timer register,       Address offset: 0x24 */\n  __IO uint32_t DLEN;                  /*!< SDIO data length register,      Address offset: 0x28 */\n  __IO uint32_t DCTRL;                 /*!< SDIO data control register,     Address offset: 0x2C */\n  __IO const uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */\n  __IO const uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */\n  __IO uint32_t ICR;                   /*!< SDIO interrupt clear register,  Address offset: 0x38 */\n  __IO uint32_t MASK;                  /*!< SDIO mask register,             Address offset: 0x3C */\n  uint32_t      RESERVED0[2];          /*!< Reserved, 0x40-0x44                                  */\n  __IO const uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */\n  uint32_t      RESERVED1[13];         /*!< Reserved, 0x4C-0x7C                                  */\n  __IO uint32_t FIFO;                  /*!< SDIO data FIFO register,        Address offset: 0x80 */\n} SDIO_TypeDef;\n\n/**\n  * @brief Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */\n  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */\n  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */\n  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\n  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */\n  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */\n  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */\n  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */\n} SPI_TypeDef;\n\n/**\n  * @brief QUAD Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */\n  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */\n  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */\n  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */\n  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */\n  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */\n  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */\n  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */\n  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */\n  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */\n  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */\n  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */\n  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */\n} QUADSPI_TypeDef;\n\n/**\n  * @brief TIM\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */\n  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */\n  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */\n  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */\n  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */\n  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\n  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\n  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */\n  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */\n  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */\n  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */\n  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */\n  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */\n  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */\n  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */\n  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */\n  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */\n  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */\n  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */\n  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */\n} TIM_TypeDef;\n\n/**\n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */\n  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */\n  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */\n  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */\n  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */\n  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */\n  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */\n} USART_TypeDef;\n\n/**\n  * @brief Window WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */\n  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */\n  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */\n} WWDG_TypeDef;\n\n/**\n  * @brief RNG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */\n  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */\n  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */\n} RNG_TypeDef;\n\n/**\n  * @brief USB_OTG_Core_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */\n  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */\n  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */\n  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */\n  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */\n  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */\n  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */\n  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */\n  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */\n  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */\n  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */\n  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */\n  uint32_t Reserved30[2];             /*!< Reserved                                     030h */\n  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */\n  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */\n  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */\n  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */\n  uint32_t  Reserved6;                /*!< Reserved                                     050h */\n  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */\n  uint32_t  Reserved;                 /*!< Reserved                                     058h */\n  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */\n  uint32_t  Reserved43[40];           /*!< Reserved                                058h-0FFh */\n  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */\n  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                        */\n} USB_OTG_GlobalTypeDef;\n\n/**\n  * @brief USB_OTG_device_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */\n  __IO uint32_t DCTL;            /*!< dev Control Register         804h */\n  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */\n  uint32_t Reserved0C;           /*!< Reserved                     80Ch */\n  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */\n  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */\n  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */\n  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */\n  uint32_t  Reserved20;          /*!< Reserved                     820h */\n  uint32_t Reserved9;            /*!< Reserved                     824h */\n  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */\n  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */\n  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */\n  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */\n  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */\n  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */\n  uint32_t Reserved40;           /*!< dedicated EP mask            840h */\n  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */\n  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */\n  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */\n} USB_OTG_DeviceTypeDef;\n\n/**\n  * @brief USB_OTG_IN_Endpoint-Specific_Register\n  */\ntypedef struct\n{\n  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */\n  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */\n  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */\n  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\n  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\n} USB_OTG_INEndpointTypeDef;\n\n/**\n  * @brief USB_OTG_OUT_Endpoint-Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */\n  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */\n  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */\n  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\n} USB_OTG_OUTEndpointTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Mode_Register_Structures\n  */\ntypedef struct\n{\n  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */\n  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */\n  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */\n  uint32_t Reserved40C;           /*!< Reserved                             40Ch */\n  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */\n  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */\n  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */\n} USB_OTG_HostTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Channel_Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */\n  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */\n  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */\n  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */\n  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */\n  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */\n  uint32_t Reserved[2];           /*!< Reserved                                      */\n} USB_OTG_HostChannelTypeDef;\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_memory_map\n  * @{\n  */\n#define FLASH_BASE            0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region                         */\n#define SRAM1_BASE            0x20000000UL /*!< SRAM1(256 KB) base address in the alias region                             */\n#define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */\n#define FSMC_R_BASE           0xA0000000UL /*!< FSMC registers base address                                                */\n#define QSPI_R_BASE           0xA0001000UL /*!< QuadSPI registers base address                                             */\n#define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(256 KB) base address in the bit-band region                          */\n#define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */\n#define FLASH_END             0x080FFFFFUL /*!< FLASH end address                                                          */\n#define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */\n#define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */\n\n/* Legacy defines */\n#define SRAM_BASE             SRAM1_BASE\n#define SRAM_BB_BASE          SRAM1_BB_BASE\n\n/*!< Peripheral memory map */\n#define APB1PERIPH_BASE       PERIPH_BASE\n#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)\n#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)\n#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)\n\n/*!< APB1 peripherals */\n#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)\n#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)\n#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)\n#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)\n#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)\n#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)\n#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)\n#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)\n#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)\n#define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)\n#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)\n#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)\n#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400UL)\n#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)\n#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)\n#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000UL)\n#define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)\n#define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)\n#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)\n#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)\n#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)\n#define FMPI2C1_BASE          (APB1PERIPH_BASE + 0x6000UL)\n#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)\n#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)\n#define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)\n\n/*!< APB2 peripherals */\n#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)\n#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)\n#define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)\n#define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)\n#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)\n#define ADC1_COMMON_BASE      (APB2PERIPH_BASE + 0x2300UL)\n/* Legacy define */\n#define ADC_BASE               ADC1_COMMON_BASE\n#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)\n#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)\n#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400UL)\n#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)\n#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)\n#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)\n#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)\n#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)\n#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000UL)\n#define DFSDM1_BASE           (APB2PERIPH_BASE + 0x6000UL)\n#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)\n#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)\n#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)\n#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)\n#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)\n#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)\n\n/*!< AHB1 peripherals */\n#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)\n#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)\n#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)\n#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)\n#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)\n#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)\n#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)\n#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)\n#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)\n#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)\n#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)\n#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)\n#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)\n#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)\n#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)\n#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)\n#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)\n#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)\n#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)\n#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)\n#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)\n#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)\n#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)\n#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)\n#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)\n#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)\n#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)\n#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)\n#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)\n\n/*!< AHB2 peripherals */\n#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800UL)\n\n\n/*!< FSMC Bankx registers base address */\n#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000UL)\n#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104UL)\n\n/*!< Debug MCU registers base address */\n#define DBGMCU_BASE           0xE0042000UL\n/*!< USB registers base address */\n#define USB_OTG_FS_PERIPH_BASE               0x50000000UL\n\n#define USB_OTG_GLOBAL_BASE                  0x000UL\n#define USB_OTG_DEVICE_BASE                  0x800UL\n#define USB_OTG_IN_ENDPOINT_BASE             0x900UL\n#define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL\n#define USB_OTG_EP_REG_SIZE                  0x20UL\n#define USB_OTG_HOST_BASE                    0x400UL\n#define USB_OTG_HOST_PORT_BASE               0x440UL\n#define USB_OTG_HOST_CHANNEL_BASE            0x500UL\n#define USB_OTG_HOST_CHANNEL_SIZE            0x20UL\n#define USB_OTG_PCGCCTL_BASE                 0xE00UL\n#define USB_OTG_FIFO_BASE                    0x1000UL\n#define USB_OTG_FIFO_SIZE                    0x1000UL\n\n#define UID_BASE                     0x1FFF7A10UL           /*!< Unique device ID register base address */\n#define FLASHSIZE_BASE               0x1FFF7A22UL           /*!< FLASH Size register base address       */\n#define PACKAGE_BASE                 0x1FFF7BF0UL           /*!< Package size register base address     */\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_declaration\n  * @{\n  */\n#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\n#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\n#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\n#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\n#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\n#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\n#define TIM12               ((TIM_TypeDef *) TIM12_BASE)\n#define TIM13               ((TIM_TypeDef *) TIM13_BASE)\n#define TIM14               ((TIM_TypeDef *) TIM14_BASE)\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\n#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\n#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\n#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)\n#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\n#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\n#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)\n#define USART2              ((USART_TypeDef *) USART2_BASE)\n#define USART3              ((USART_TypeDef *) USART3_BASE)\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\n#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\n#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\n#define FMPI2C1             ((FMPI2C_TypeDef *) FMPI2C1_BASE)\n#define CAN1                ((CAN_TypeDef *) CAN1_BASE)\n#define CAN2                ((CAN_TypeDef *) CAN2_BASE)\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\n#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\n#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\n#define USART1              ((USART_TypeDef *) USART1_BASE)\n#define USART6              ((USART_TypeDef *) USART6_BASE)\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\n#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)\n/* Legacy define */\n#define ADC                  ADC1_COMMON\n#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\n#define SPI4                ((SPI_TypeDef *) SPI4_BASE)\n#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\n#define TIM9                ((TIM_TypeDef *) TIM9_BASE)\n#define TIM10               ((TIM_TypeDef *) TIM10_BASE)\n#define TIM11               ((TIM_TypeDef *) TIM11_BASE)\n#define SPI5                ((SPI_TypeDef *) SPI5_BASE)\n#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)\n#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)\n#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)\n#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)\n#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)\n#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\n#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\n#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\n#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)\n#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\n#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\n#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\n#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\n#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\n#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\n#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\n#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\n#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\n#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\n#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\n#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\n#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\n#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\n#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\n#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\n#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\n#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\n#define RNG                 ((RNG_TypeDef *) RNG_BASE)\n#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)\n#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)\n#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)\n#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\n#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_constants\n  * @{\n  */\n\n  /** @addtogroup Peripheral_Registers_Bits_Definition\n  * @{\n  */\n\n/******************************************************************************/\n/*                         Peripheral Registers_Bits_Definition               */\n/******************************************************************************/\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Analog to Digital Converter                         */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for ADC_SR register  ********************/\n#define ADC_SR_AWD_Pos            (0U)\n#define ADC_SR_AWD_Msk            (0x1UL << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */\n#define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */\n#define ADC_SR_EOC_Pos            (1U)\n#define ADC_SR_EOC_Msk            (0x1UL << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */\n#define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */\n#define ADC_SR_JEOC_Pos           (2U)\n#define ADC_SR_JEOC_Msk           (0x1UL << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */\n#define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */\n#define ADC_SR_JSTRT_Pos          (3U)\n#define ADC_SR_JSTRT_Msk          (0x1UL << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */\n#define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */\n#define ADC_SR_STRT_Pos           (4U)\n#define ADC_SR_STRT_Msk           (0x1UL << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */\n#define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */\n#define ADC_SR_OVR_Pos            (5U)\n#define ADC_SR_OVR_Msk            (0x1UL << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */\n#define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */\n\n/*******************  Bit definition for ADC_CR1 register  ********************/\n#define ADC_CR1_AWDCH_Pos         (0U)\n#define ADC_CR1_AWDCH_Msk         (0x1FUL << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */\n#define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\n#define ADC_CR1_AWDCH_0           (0x01UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */\n#define ADC_CR1_AWDCH_1           (0x02UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */\n#define ADC_CR1_AWDCH_2           (0x04UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */\n#define ADC_CR1_AWDCH_3           (0x08UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */\n#define ADC_CR1_AWDCH_4           (0x10UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */\n#define ADC_CR1_EOCIE_Pos         (5U)\n#define ADC_CR1_EOCIE_Msk         (0x1UL << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */\n#define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */\n#define ADC_CR1_AWDIE_Pos         (6U)\n#define ADC_CR1_AWDIE_Msk         (0x1UL << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */\n#define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */\n#define ADC_CR1_JEOCIE_Pos        (7U)\n#define ADC_CR1_JEOCIE_Msk        (0x1UL << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */\n#define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */\n#define ADC_CR1_SCAN_Pos          (8U)\n#define ADC_CR1_SCAN_Msk          (0x1UL << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */\n#define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */\n#define ADC_CR1_AWDSGL_Pos        (9U)\n#define ADC_CR1_AWDSGL_Msk        (0x1UL << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */\n#define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */\n#define ADC_CR1_JAUTO_Pos         (10U)\n#define ADC_CR1_JAUTO_Msk         (0x1UL << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */\n#define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */\n#define ADC_CR1_DISCEN_Pos        (11U)\n#define ADC_CR1_DISCEN_Msk        (0x1UL << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */\n#define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */\n#define ADC_CR1_JDISCEN_Pos       (12U)\n#define ADC_CR1_JDISCEN_Msk       (0x1UL << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */\n#define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */\n#define ADC_CR1_DISCNUM_Pos       (13U)\n#define ADC_CR1_DISCNUM_Msk       (0x7UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */\n#define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\n#define ADC_CR1_DISCNUM_0         (0x1UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */\n#define ADC_CR1_DISCNUM_1         (0x2UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */\n#define ADC_CR1_DISCNUM_2         (0x4UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */\n#define ADC_CR1_JAWDEN_Pos        (22U)\n#define ADC_CR1_JAWDEN_Msk        (0x1UL << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */\n#define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */\n#define ADC_CR1_AWDEN_Pos         (23U)\n#define ADC_CR1_AWDEN_Msk         (0x1UL << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */\n#define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */\n#define ADC_CR1_RES_Pos           (24U)\n#define ADC_CR1_RES_Msk           (0x3UL << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */\n#define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */\n#define ADC_CR1_RES_0             (0x1UL << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */\n#define ADC_CR1_RES_1             (0x2UL << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */\n#define ADC_CR1_OVRIE_Pos         (26U)\n#define ADC_CR1_OVRIE_Msk         (0x1UL << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */\n#define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */\n\n/*******************  Bit definition for ADC_CR2 register  ********************/\n#define ADC_CR2_ADON_Pos          (0U)\n#define ADC_CR2_ADON_Msk          (0x1UL << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */\n#define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */\n#define ADC_CR2_CONT_Pos          (1U)\n#define ADC_CR2_CONT_Msk          (0x1UL << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */\n#define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */\n#define ADC_CR2_DMA_Pos           (8U)\n#define ADC_CR2_DMA_Msk           (0x1UL << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */\n#define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */\n#define ADC_CR2_DDS_Pos           (9U)\n#define ADC_CR2_DDS_Msk           (0x1UL << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */\n#define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */\n#define ADC_CR2_EOCS_Pos          (10U)\n#define ADC_CR2_EOCS_Msk          (0x1UL << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */\n#define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */\n#define ADC_CR2_ALIGN_Pos         (11U)\n#define ADC_CR2_ALIGN_Msk         (0x1UL << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */\n#define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */\n#define ADC_CR2_JEXTSEL_Pos       (16U)\n#define ADC_CR2_JEXTSEL_Msk       (0xFUL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */\n#define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */\n#define ADC_CR2_JEXTSEL_0         (0x1UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */\n#define ADC_CR2_JEXTSEL_1         (0x2UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */\n#define ADC_CR2_JEXTSEL_2         (0x4UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */\n#define ADC_CR2_JEXTSEL_3         (0x8UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */\n#define ADC_CR2_JEXTEN_Pos        (20U)\n#define ADC_CR2_JEXTEN_Msk        (0x3UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */\n#define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\n#define ADC_CR2_JEXTEN_0          (0x1UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */\n#define ADC_CR2_JEXTEN_1          (0x2UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */\n#define ADC_CR2_JSWSTART_Pos      (22U)\n#define ADC_CR2_JSWSTART_Msk      (0x1UL << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */\n#define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */\n#define ADC_CR2_EXTSEL_Pos        (24U)\n#define ADC_CR2_EXTSEL_Msk        (0xFUL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */\n#define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\n#define ADC_CR2_EXTSEL_0          (0x1UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */\n#define ADC_CR2_EXTSEL_1          (0x2UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */\n#define ADC_CR2_EXTSEL_2          (0x4UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */\n#define ADC_CR2_EXTSEL_3          (0x8UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */\n#define ADC_CR2_EXTEN_Pos         (28U)\n#define ADC_CR2_EXTEN_Msk         (0x3UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */\n#define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\n#define ADC_CR2_EXTEN_0           (0x1UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */\n#define ADC_CR2_EXTEN_1           (0x2UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */\n#define ADC_CR2_SWSTART_Pos       (30U)\n#define ADC_CR2_SWSTART_Msk       (0x1UL << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */\n#define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */\n\n/******************  Bit definition for ADC_SMPR1 register  *******************/\n#define ADC_SMPR1_SMP10_Pos       (0U)\n#define ADC_SMPR1_SMP10_Msk       (0x7UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */\n#define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\n#define ADC_SMPR1_SMP10_0         (0x1UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */\n#define ADC_SMPR1_SMP10_1         (0x2UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */\n#define ADC_SMPR1_SMP10_2         (0x4UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */\n#define ADC_SMPR1_SMP11_Pos       (3U)\n#define ADC_SMPR1_SMP11_Msk       (0x7UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */\n#define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\n#define ADC_SMPR1_SMP11_0         (0x1UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */\n#define ADC_SMPR1_SMP11_1         (0x2UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */\n#define ADC_SMPR1_SMP11_2         (0x4UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */\n#define ADC_SMPR1_SMP12_Pos       (6U)\n#define ADC_SMPR1_SMP12_Msk       (0x7UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */\n#define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\n#define ADC_SMPR1_SMP12_0         (0x1UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */\n#define ADC_SMPR1_SMP12_1         (0x2UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */\n#define ADC_SMPR1_SMP12_2         (0x4UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */\n#define ADC_SMPR1_SMP13_Pos       (9U)\n#define ADC_SMPR1_SMP13_Msk       (0x7UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */\n#define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\n#define ADC_SMPR1_SMP13_0         (0x1UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */\n#define ADC_SMPR1_SMP13_1         (0x2UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */\n#define ADC_SMPR1_SMP13_2         (0x4UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */\n#define ADC_SMPR1_SMP14_Pos       (12U)\n#define ADC_SMPR1_SMP14_Msk       (0x7UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */\n#define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\n#define ADC_SMPR1_SMP14_0         (0x1UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */\n#define ADC_SMPR1_SMP14_1         (0x2UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */\n#define ADC_SMPR1_SMP14_2         (0x4UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */\n#define ADC_SMPR1_SMP15_Pos       (15U)\n#define ADC_SMPR1_SMP15_Msk       (0x7UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */\n#define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\n#define ADC_SMPR1_SMP15_0         (0x1UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */\n#define ADC_SMPR1_SMP15_1         (0x2UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */\n#define ADC_SMPR1_SMP15_2         (0x4UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */\n#define ADC_SMPR1_SMP16_Pos       (18U)\n#define ADC_SMPR1_SMP16_Msk       (0x7UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */\n#define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\n#define ADC_SMPR1_SMP16_0         (0x1UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */\n#define ADC_SMPR1_SMP16_1         (0x2UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */\n#define ADC_SMPR1_SMP16_2         (0x4UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */\n#define ADC_SMPR1_SMP17_Pos       (21U)\n#define ADC_SMPR1_SMP17_Msk       (0x7UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */\n#define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\n#define ADC_SMPR1_SMP17_0         (0x1UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */\n#define ADC_SMPR1_SMP17_1         (0x2UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */\n#define ADC_SMPR1_SMP17_2         (0x4UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */\n#define ADC_SMPR1_SMP18_Pos       (24U)\n#define ADC_SMPR1_SMP18_Msk       (0x7UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */\n#define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\n#define ADC_SMPR1_SMP18_0         (0x1UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */\n#define ADC_SMPR1_SMP18_1         (0x2UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */\n#define ADC_SMPR1_SMP18_2         (0x4UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */\n\n/******************  Bit definition for ADC_SMPR2 register  *******************/\n#define ADC_SMPR2_SMP0_Pos        (0U)\n#define ADC_SMPR2_SMP0_Msk        (0x7UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */\n#define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\n#define ADC_SMPR2_SMP0_0          (0x1UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */\n#define ADC_SMPR2_SMP0_1          (0x2UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */\n#define ADC_SMPR2_SMP0_2          (0x4UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */\n#define ADC_SMPR2_SMP1_Pos        (3U)\n#define ADC_SMPR2_SMP1_Msk        (0x7UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */\n#define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\n#define ADC_SMPR2_SMP1_0          (0x1UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */\n#define ADC_SMPR2_SMP1_1          (0x2UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */\n#define ADC_SMPR2_SMP1_2          (0x4UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */\n#define ADC_SMPR2_SMP2_Pos        (6U)\n#define ADC_SMPR2_SMP2_Msk        (0x7UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */\n#define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\n#define ADC_SMPR2_SMP2_0          (0x1UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */\n#define ADC_SMPR2_SMP2_1          (0x2UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */\n#define ADC_SMPR2_SMP2_2          (0x4UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */\n#define ADC_SMPR2_SMP3_Pos        (9U)\n#define ADC_SMPR2_SMP3_Msk        (0x7UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */\n#define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\n#define ADC_SMPR2_SMP3_0          (0x1UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */\n#define ADC_SMPR2_SMP3_1          (0x2UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */\n#define ADC_SMPR2_SMP3_2          (0x4UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */\n#define ADC_SMPR2_SMP4_Pos        (12U)\n#define ADC_SMPR2_SMP4_Msk        (0x7UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */\n#define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\n#define ADC_SMPR2_SMP4_0          (0x1UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */\n#define ADC_SMPR2_SMP4_1          (0x2UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */\n#define ADC_SMPR2_SMP4_2          (0x4UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */\n#define ADC_SMPR2_SMP5_Pos        (15U)\n#define ADC_SMPR2_SMP5_Msk        (0x7UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */\n#define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\n#define ADC_SMPR2_SMP5_0          (0x1UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */\n#define ADC_SMPR2_SMP5_1          (0x2UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */\n#define ADC_SMPR2_SMP5_2          (0x4UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */\n#define ADC_SMPR2_SMP6_Pos        (18U)\n#define ADC_SMPR2_SMP6_Msk        (0x7UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */\n#define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\n#define ADC_SMPR2_SMP6_0          (0x1UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */\n#define ADC_SMPR2_SMP6_1          (0x2UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */\n#define ADC_SMPR2_SMP6_2          (0x4UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */\n#define ADC_SMPR2_SMP7_Pos        (21U)\n#define ADC_SMPR2_SMP7_Msk        (0x7UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */\n#define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\n#define ADC_SMPR2_SMP7_0          (0x1UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */\n#define ADC_SMPR2_SMP7_1          (0x2UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */\n#define ADC_SMPR2_SMP7_2          (0x4UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */\n#define ADC_SMPR2_SMP8_Pos        (24U)\n#define ADC_SMPR2_SMP8_Msk        (0x7UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */\n#define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\n#define ADC_SMPR2_SMP8_0          (0x1UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */\n#define ADC_SMPR2_SMP8_1          (0x2UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */\n#define ADC_SMPR2_SMP8_2          (0x4UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */\n#define ADC_SMPR2_SMP9_Pos        (27U)\n#define ADC_SMPR2_SMP9_Msk        (0x7UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */\n#define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\n#define ADC_SMPR2_SMP9_0          (0x1UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */\n#define ADC_SMPR2_SMP9_1          (0x2UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */\n#define ADC_SMPR2_SMP9_2          (0x4UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */\n\n/******************  Bit definition for ADC_JOFR1 register  *******************/\n#define ADC_JOFR1_JOFFSET1_Pos    (0U)\n#define ADC_JOFR1_JOFFSET1_Msk    (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */\n\n/******************  Bit definition for ADC_JOFR2 register  *******************/\n#define ADC_JOFR2_JOFFSET2_Pos    (0U)\n#define ADC_JOFR2_JOFFSET2_Msk    (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */\n\n/******************  Bit definition for ADC_JOFR3 register  *******************/\n#define ADC_JOFR3_JOFFSET3_Pos    (0U)\n#define ADC_JOFR3_JOFFSET3_Msk    (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */\n\n/******************  Bit definition for ADC_JOFR4 register  *******************/\n#define ADC_JOFR4_JOFFSET4_Pos    (0U)\n#define ADC_JOFR4_JOFFSET4_Msk    (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */\n\n/*******************  Bit definition for ADC_HTR register  ********************/\n#define ADC_HTR_HT_Pos            (0U)\n#define ADC_HTR_HT_Msk            (0xFFFUL << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */\n#define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */\n\n/*******************  Bit definition for ADC_LTR register  ********************/\n#define ADC_LTR_LT_Pos            (0U)\n#define ADC_LTR_LT_Msk            (0xFFFUL << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */\n#define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */\n\n/*******************  Bit definition for ADC_SQR1 register  *******************/\n#define ADC_SQR1_SQ13_Pos         (0U)\n#define ADC_SQR1_SQ13_Msk         (0x1FUL << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */\n#define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\n#define ADC_SQR1_SQ13_0           (0x01UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */\n#define ADC_SQR1_SQ13_1           (0x02UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */\n#define ADC_SQR1_SQ13_2           (0x04UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */\n#define ADC_SQR1_SQ13_3           (0x08UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */\n#define ADC_SQR1_SQ13_4           (0x10UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */\n#define ADC_SQR1_SQ14_Pos         (5U)\n#define ADC_SQR1_SQ14_Msk         (0x1FUL << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */\n#define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\n#define ADC_SQR1_SQ14_0           (0x01UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */\n#define ADC_SQR1_SQ14_1           (0x02UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */\n#define ADC_SQR1_SQ14_2           (0x04UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */\n#define ADC_SQR1_SQ14_3           (0x08UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */\n#define ADC_SQR1_SQ14_4           (0x10UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */\n#define ADC_SQR1_SQ15_Pos         (10U)\n#define ADC_SQR1_SQ15_Msk         (0x1FUL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */\n#define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\n#define ADC_SQR1_SQ15_0           (0x01UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */\n#define ADC_SQR1_SQ15_1           (0x02UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */\n#define ADC_SQR1_SQ15_2           (0x04UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */\n#define ADC_SQR1_SQ15_3           (0x08UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */\n#define ADC_SQR1_SQ15_4           (0x10UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */\n#define ADC_SQR1_SQ16_Pos         (15U)\n#define ADC_SQR1_SQ16_Msk         (0x1FUL << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\n#define ADC_SQR1_SQ16_0           (0x01UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR1_SQ16_1           (0x02UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR1_SQ16_2           (0x04UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR1_SQ16_3           (0x08UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR1_SQ16_4           (0x10UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR1_L_Pos            (20U)\n#define ADC_SQR1_L_Msk            (0xFUL << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */\n#define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */\n#define ADC_SQR1_L_0              (0x1UL << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */\n#define ADC_SQR1_L_1              (0x2UL << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */\n#define ADC_SQR1_L_2              (0x4UL << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */\n#define ADC_SQR1_L_3              (0x8UL << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */\n\n/*******************  Bit definition for ADC_SQR2 register  *******************/\n#define ADC_SQR2_SQ7_Pos          (0U)\n#define ADC_SQR2_SQ7_Msk          (0x1FUL << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\n#define ADC_SQR2_SQ7_0            (0x01UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR2_SQ7_1            (0x02UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR2_SQ7_2            (0x04UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR2_SQ7_3            (0x08UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR2_SQ7_4            (0x10UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR2_SQ8_Pos          (5U)\n#define ADC_SQR2_SQ8_Msk          (0x1FUL << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\n#define ADC_SQR2_SQ8_0            (0x01UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR2_SQ8_1            (0x02UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR2_SQ8_2            (0x04UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR2_SQ8_3            (0x08UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR2_SQ8_4            (0x10UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR2_SQ9_Pos          (10U)\n#define ADC_SQR2_SQ9_Msk          (0x1FUL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\n#define ADC_SQR2_SQ9_0            (0x01UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR2_SQ9_1            (0x02UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR2_SQ9_2            (0x04UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR2_SQ9_3            (0x08UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR2_SQ9_4            (0x10UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR2_SQ10_Pos         (15U)\n#define ADC_SQR2_SQ10_Msk         (0x1FUL << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\n#define ADC_SQR2_SQ10_0           (0x01UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR2_SQ10_1           (0x02UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR2_SQ10_2           (0x04UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR2_SQ10_3           (0x08UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR2_SQ10_4           (0x10UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR2_SQ11_Pos         (20U)\n#define ADC_SQR2_SQ11_Msk         (0x1FUL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */\n#define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\n#define ADC_SQR2_SQ11_0           (0x01UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */\n#define ADC_SQR2_SQ11_1           (0x02UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */\n#define ADC_SQR2_SQ11_2           (0x04UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */\n#define ADC_SQR2_SQ11_3           (0x08UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */\n#define ADC_SQR2_SQ11_4           (0x10UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */\n#define ADC_SQR2_SQ12_Pos         (25U)\n#define ADC_SQR2_SQ12_Msk         (0x1FUL << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */\n#define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\n#define ADC_SQR2_SQ12_0           (0x01UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */\n#define ADC_SQR2_SQ12_1           (0x02UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */\n#define ADC_SQR2_SQ12_2           (0x04UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */\n#define ADC_SQR2_SQ12_3           (0x08UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */\n#define ADC_SQR2_SQ12_4           (0x10UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_SQR3 register  *******************/\n#define ADC_SQR3_SQ1_Pos          (0U)\n#define ADC_SQR3_SQ1_Msk          (0x1FUL << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\n#define ADC_SQR3_SQ1_0            (0x01UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR3_SQ1_1            (0x02UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR3_SQ1_2            (0x04UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR3_SQ1_3            (0x08UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR3_SQ1_4            (0x10UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR3_SQ2_Pos          (5U)\n#define ADC_SQR3_SQ2_Msk          (0x1FUL << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\n#define ADC_SQR3_SQ2_0            (0x01UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR3_SQ2_1            (0x02UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR3_SQ2_2            (0x04UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR3_SQ2_3            (0x08UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR3_SQ2_4            (0x10UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR3_SQ3_Pos          (10U)\n#define ADC_SQR3_SQ3_Msk          (0x1FUL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\n#define ADC_SQR3_SQ3_0            (0x01UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR3_SQ3_1            (0x02UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR3_SQ3_2            (0x04UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR3_SQ3_3            (0x08UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR3_SQ3_4            (0x10UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR3_SQ4_Pos          (15U)\n#define ADC_SQR3_SQ4_Msk          (0x1FUL << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */\n#define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\n#define ADC_SQR3_SQ4_0            (0x01UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */\n#define ADC_SQR3_SQ4_1            (0x02UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */\n#define ADC_SQR3_SQ4_2            (0x04UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */\n#define ADC_SQR3_SQ4_3            (0x08UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */\n#define ADC_SQR3_SQ4_4            (0x10UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */\n#define ADC_SQR3_SQ5_Pos          (20U)\n#define ADC_SQR3_SQ5_Msk          (0x1FUL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */\n#define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\n#define ADC_SQR3_SQ5_0            (0x01UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */\n#define ADC_SQR3_SQ5_1            (0x02UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */\n#define ADC_SQR3_SQ5_2            (0x04UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */\n#define ADC_SQR3_SQ5_3            (0x08UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */\n#define ADC_SQR3_SQ5_4            (0x10UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */\n#define ADC_SQR3_SQ6_Pos          (25U)\n#define ADC_SQR3_SQ6_Msk          (0x1FUL << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */\n#define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\n#define ADC_SQR3_SQ6_0            (0x01UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */\n#define ADC_SQR3_SQ6_1            (0x02UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */\n#define ADC_SQR3_SQ6_2            (0x04UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */\n#define ADC_SQR3_SQ6_3            (0x08UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */\n#define ADC_SQR3_SQ6_4            (0x10UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_JSQR register  *******************/\n#define ADC_JSQR_JSQ1_Pos         (0U)\n#define ADC_JSQR_JSQ1_Msk         (0x1FUL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */\n#define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */\n#define ADC_JSQR_JSQ1_0           (0x01UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */\n#define ADC_JSQR_JSQ1_1           (0x02UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */\n#define ADC_JSQR_JSQ1_2           (0x04UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */\n#define ADC_JSQR_JSQ1_3           (0x08UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */\n#define ADC_JSQR_JSQ1_4           (0x10UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */\n#define ADC_JSQR_JSQ2_Pos         (5U)\n#define ADC_JSQR_JSQ2_Msk         (0x1FUL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */\n#define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\n#define ADC_JSQR_JSQ2_0           (0x01UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */\n#define ADC_JSQR_JSQ2_1           (0x02UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */\n#define ADC_JSQR_JSQ2_2           (0x04UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */\n#define ADC_JSQR_JSQ2_3           (0x08UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */\n#define ADC_JSQR_JSQ2_4           (0x10UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */\n#define ADC_JSQR_JSQ3_Pos         (10U)\n#define ADC_JSQR_JSQ3_Msk         (0x1FUL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */\n#define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\n#define ADC_JSQR_JSQ3_0           (0x01UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */\n#define ADC_JSQR_JSQ3_1           (0x02UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */\n#define ADC_JSQR_JSQ3_2           (0x04UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */\n#define ADC_JSQR_JSQ3_3           (0x08UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */\n#define ADC_JSQR_JSQ3_4           (0x10UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */\n#define ADC_JSQR_JSQ4_Pos         (15U)\n#define ADC_JSQR_JSQ4_Msk         (0x1FUL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */\n#define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\n#define ADC_JSQR_JSQ4_0           (0x01UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */\n#define ADC_JSQR_JSQ4_1           (0x02UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */\n#define ADC_JSQR_JSQ4_2           (0x04UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */\n#define ADC_JSQR_JSQ4_3           (0x08UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */\n#define ADC_JSQR_JSQ4_4           (0x10UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */\n#define ADC_JSQR_JL_Pos           (20U)\n#define ADC_JSQR_JL_Msk           (0x3UL << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */\n#define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */\n#define ADC_JSQR_JL_0             (0x1UL << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */\n#define ADC_JSQR_JL_1             (0x2UL << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */\n\n/*******************  Bit definition for ADC_JDR1 register  *******************/\n#define ADC_JDR1_JDATA_Pos        (0U)\n#define ADC_JDR1_JDATA_Msk        (0xFFFFUL << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR2 register  *******************/\n#define ADC_JDR2_JDATA_Pos        (0U)\n#define ADC_JDR2_JDATA_Msk        (0xFFFFUL << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR3 register  *******************/\n#define ADC_JDR3_JDATA_Pos        (0U)\n#define ADC_JDR3_JDATA_Msk        (0xFFFFUL << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR4 register  *******************/\n#define ADC_JDR4_JDATA_Pos        (0U)\n#define ADC_JDR4_JDATA_Msk        (0xFFFFUL << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */\n\n/********************  Bit definition for ADC_DR register  ********************/\n#define ADC_DR_DATA_Pos           (0U)\n#define ADC_DR_DATA_Msk           (0xFFFFUL << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */\n#define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */\n#define ADC_DR_ADC2DATA_Pos       (16U)\n#define ADC_DR_ADC2DATA_Msk       (0xFFFFUL << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */\n#define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */\n\n/*******************  Bit definition for ADC_CSR register  ********************/\n#define ADC_CSR_AWD1_Pos          (0U)\n#define ADC_CSR_AWD1_Msk          (0x1UL << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */\n#define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */\n#define ADC_CSR_EOC1_Pos          (1U)\n#define ADC_CSR_EOC1_Msk          (0x1UL << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */\n#define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */\n#define ADC_CSR_JEOC1_Pos         (2U)\n#define ADC_CSR_JEOC1_Msk         (0x1UL << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */\n#define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */\n#define ADC_CSR_JSTRT1_Pos        (3U)\n#define ADC_CSR_JSTRT1_Msk        (0x1UL << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */\n#define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */\n#define ADC_CSR_STRT1_Pos         (4U)\n#define ADC_CSR_STRT1_Msk         (0x1UL << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */\n#define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */\n#define ADC_CSR_OVR1_Pos          (5U)\n#define ADC_CSR_OVR1_Msk          (0x1UL << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */\n#define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */\n\n/* Legacy defines */\n#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1\n\n/*******************  Bit definition for ADC_CCR register  ********************/\n#define ADC_CCR_MULTI_Pos         (0U)\n#define ADC_CCR_MULTI_Msk         (0x1FUL << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */\n#define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */\n#define ADC_CCR_MULTI_0           (0x01UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */\n#define ADC_CCR_MULTI_1           (0x02UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */\n#define ADC_CCR_MULTI_2           (0x04UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */\n#define ADC_CCR_MULTI_3           (0x08UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */\n#define ADC_CCR_MULTI_4           (0x10UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */\n#define ADC_CCR_DELAY_Pos         (8U)\n#define ADC_CCR_DELAY_Msk         (0xFUL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */\n#define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */\n#define ADC_CCR_DELAY_0           (0x1UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */\n#define ADC_CCR_DELAY_1           (0x2UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */\n#define ADC_CCR_DELAY_2           (0x4UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */\n#define ADC_CCR_DELAY_3           (0x8UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */\n#define ADC_CCR_DDS_Pos           (13U)\n#define ADC_CCR_DDS_Msk           (0x1UL << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */\n#define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */\n#define ADC_CCR_DMA_Pos           (14U)\n#define ADC_CCR_DMA_Msk           (0x3UL << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */\n#define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */\n#define ADC_CCR_DMA_0             (0x1UL << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */\n#define ADC_CCR_DMA_1             (0x2UL << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */\n#define ADC_CCR_ADCPRE_Pos        (16U)\n#define ADC_CCR_ADCPRE_Msk        (0x3UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */\n#define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */\n#define ADC_CCR_ADCPRE_0          (0x1UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */\n#define ADC_CCR_ADCPRE_1          (0x2UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */\n#define ADC_CCR_VBATE_Pos         (22U)\n#define ADC_CCR_VBATE_Msk         (0x1UL << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */\n#define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */\n#define ADC_CCR_TSVREFE_Pos       (23U)\n#define ADC_CCR_TSVREFE_Msk       (0x1UL << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */\n#define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */\n\n/*******************  Bit definition for ADC_CDR register  ********************/\n#define ADC_CDR_DATA1_Pos         (0U)\n#define ADC_CDR_DATA1_Msk         (0xFFFFUL << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */\n#define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */\n#define ADC_CDR_DATA2_Pos         (16U)\n#define ADC_CDR_DATA2_Msk         (0xFFFFUL << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */\n#define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */\n\n/* Legacy defines */\n#define ADC_CDR_RDATA_MST         ADC_CDR_DATA1\n#define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Controller Area Network                            */\n/*                                                                            */\n/******************************************************************************/\n/*!<CAN control and status registers */\n/*******************  Bit definition for CAN_MCR register  ********************/\n#define CAN_MCR_INRQ_Pos       (0U)\n#define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */\n#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */\n#define CAN_MCR_SLEEP_Pos      (1U)\n#define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */\n#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */\n#define CAN_MCR_TXFP_Pos       (2U)\n#define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */\n#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */\n#define CAN_MCR_RFLM_Pos       (3U)\n#define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */\n#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */\n#define CAN_MCR_NART_Pos       (4U)\n#define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */\n#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */\n#define CAN_MCR_AWUM_Pos       (5U)\n#define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */\n#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */\n#define CAN_MCR_ABOM_Pos       (6U)\n#define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */\n#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */\n#define CAN_MCR_TTCM_Pos       (7U)\n#define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */\n#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */\n#define CAN_MCR_RESET_Pos      (15U)\n#define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */\n#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */\n#define CAN_MCR_DBF_Pos        (16U)\n#define CAN_MCR_DBF_Msk        (0x1UL << CAN_MCR_DBF_Pos)                       /*!< 0x00010000 */\n#define CAN_MCR_DBF            CAN_MCR_DBF_Msk                                 /*!<bxCAN Debug freeze */\n/*******************  Bit definition for CAN_MSR register  ********************/\n#define CAN_MSR_INAK_Pos       (0U)\n#define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */\n#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */\n#define CAN_MSR_SLAK_Pos       (1U)\n#define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */\n#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */\n#define CAN_MSR_ERRI_Pos       (2U)\n#define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */\n#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */\n#define CAN_MSR_WKUI_Pos       (3U)\n#define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */\n#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */\n#define CAN_MSR_SLAKI_Pos      (4U)\n#define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */\n#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */\n#define CAN_MSR_TXM_Pos        (8U)\n#define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */\n#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */\n#define CAN_MSR_RXM_Pos        (9U)\n#define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */\n#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */\n#define CAN_MSR_SAMP_Pos       (10U)\n#define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */\n#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */\n#define CAN_MSR_RX_Pos         (11U)\n#define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */\n#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */\n\n/*******************  Bit definition for CAN_TSR register  ********************/\n#define CAN_TSR_RQCP0_Pos      (0U)\n#define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */\n#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */\n#define CAN_TSR_TXOK0_Pos      (1U)\n#define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */\n#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */\n#define CAN_TSR_ALST0_Pos      (2U)\n#define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */\n#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */\n#define CAN_TSR_TERR0_Pos      (3U)\n#define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */\n#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */\n#define CAN_TSR_ABRQ0_Pos      (7U)\n#define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */\n#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */\n#define CAN_TSR_RQCP1_Pos      (8U)\n#define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */\n#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */\n#define CAN_TSR_TXOK1_Pos      (9U)\n#define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */\n#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */\n#define CAN_TSR_ALST1_Pos      (10U)\n#define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */\n#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */\n#define CAN_TSR_TERR1_Pos      (11U)\n#define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */\n#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */\n#define CAN_TSR_ABRQ1_Pos      (15U)\n#define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */\n#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */\n#define CAN_TSR_RQCP2_Pos      (16U)\n#define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */\n#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */\n#define CAN_TSR_TXOK2_Pos      (17U)\n#define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */\n#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */\n#define CAN_TSR_ALST2_Pos      (18U)\n#define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */\n#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */\n#define CAN_TSR_TERR2_Pos      (19U)\n#define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */\n#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */\n#define CAN_TSR_ABRQ2_Pos      (23U)\n#define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */\n#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */\n#define CAN_TSR_CODE_Pos       (24U)\n#define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */\n#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */\n\n#define CAN_TSR_TME_Pos        (26U)\n#define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */\n#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */\n#define CAN_TSR_TME0_Pos       (26U)\n#define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */\n#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */\n#define CAN_TSR_TME1_Pos       (27U)\n#define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */\n#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */\n#define CAN_TSR_TME2_Pos       (28U)\n#define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */\n#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */\n\n#define CAN_TSR_LOW_Pos        (29U)\n#define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */\n#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */\n#define CAN_TSR_LOW0_Pos       (29U)\n#define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */\n#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */\n#define CAN_TSR_LOW1_Pos       (30U)\n#define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */\n#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */\n#define CAN_TSR_LOW2_Pos       (31U)\n#define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */\n#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */\n\n/*******************  Bit definition for CAN_RF0R register  *******************/\n#define CAN_RF0R_FMP0_Pos      (0U)\n#define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */\n#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */\n#define CAN_RF0R_FULL0_Pos     (3U)\n#define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */\n#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */\n#define CAN_RF0R_FOVR0_Pos     (4U)\n#define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */\n#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */\n#define CAN_RF0R_RFOM0_Pos     (5U)\n#define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */\n#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */\n\n/*******************  Bit definition for CAN_RF1R register  *******************/\n#define CAN_RF1R_FMP1_Pos      (0U)\n#define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */\n#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */\n#define CAN_RF1R_FULL1_Pos     (3U)\n#define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */\n#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */\n#define CAN_RF1R_FOVR1_Pos     (4U)\n#define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */\n#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */\n#define CAN_RF1R_RFOM1_Pos     (5U)\n#define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */\n#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */\n\n/********************  Bit definition for CAN_IER register  *******************/\n#define CAN_IER_TMEIE_Pos      (0U)\n#define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */\n#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */\n#define CAN_IER_FMPIE0_Pos     (1U)\n#define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */\n#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE0_Pos      (2U)\n#define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */\n#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE0_Pos     (3U)\n#define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */\n#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_FMPIE1_Pos     (4U)\n#define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */\n#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE1_Pos      (5U)\n#define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */\n#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE1_Pos     (6U)\n#define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */\n#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)\n#define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */\n#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */\n#define CAN_IER_EPVIE_Pos      (9U)\n#define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */\n#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */\n#define CAN_IER_BOFIE_Pos      (10U)\n#define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */\n#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */\n#define CAN_IER_LECIE_Pos      (11U)\n#define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */\n#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */\n#define CAN_IER_ERRIE_Pos      (15U)\n#define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */\n#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */\n#define CAN_IER_WKUIE_Pos      (16U)\n#define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */\n#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */\n#define CAN_IER_SLKIE_Pos      (17U)\n#define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */\n#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)\n\n/********************  Bit definition for CAN_ESR register  *******************/\n#define CAN_ESR_EWGF_Pos       (0U)\n#define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */\n#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */\n#define CAN_ESR_EPVF_Pos       (1U)\n#define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */\n#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */\n#define CAN_ESR_BOFF_Pos       (2U)\n#define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */\n#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */\n\n#define CAN_ESR_LEC_Pos        (4U)\n#define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */\n#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */\n#define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */\n#define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */\n#define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */\n\n#define CAN_ESR_TEC_Pos        (16U)\n#define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */\n#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */\n#define CAN_ESR_REC_Pos        (24U)\n#define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */\n#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */\n\n/*******************  Bit definition for CAN_BTR register  ********************/\n#define CAN_BTR_BRP_Pos        (0U)\n#define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */\n#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */\n#define CAN_BTR_TS1_Pos        (16U)\n#define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */\n#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */\n#define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */\n#define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */\n#define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */\n#define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */\n#define CAN_BTR_TS2_Pos        (20U)\n#define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */\n#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */\n#define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */\n#define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */\n#define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */\n#define CAN_BTR_SJW_Pos        (24U)\n#define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */\n#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */\n#define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */\n#define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */\n#define CAN_BTR_LBKM_Pos       (30U)\n#define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */\n#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */\n#define CAN_BTR_SILM_Pos       (31U)\n#define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */\n#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */\n\n\n/*!<Mailbox registers */\n/******************  Bit definition for CAN_TI0R register  ********************/\n#define CAN_TI0R_TXRQ_Pos      (0U)\n#define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI0R_RTR_Pos       (1U)\n#define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI0R_IDE_Pos       (2U)\n#define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI0R_EXID_Pos      (3U)\n#define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI0R_STID_Pos      (21U)\n#define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/******************  Bit definition for CAN_TDT0R register  *******************/\n#define CAN_TDT0R_DLC_Pos      (0U)\n#define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT0R_TGT_Pos      (8U)\n#define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT0R_TIME_Pos     (16U)\n#define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/******************  Bit definition for CAN_TDL0R register  *******************/\n#define CAN_TDL0R_DATA0_Pos    (0U)\n#define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL0R_DATA1_Pos    (8U)\n#define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL0R_DATA2_Pos    (16U)\n#define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL0R_DATA3_Pos    (24U)\n#define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/******************  Bit definition for CAN_TDH0R register  *******************/\n#define CAN_TDH0R_DATA4_Pos    (0U)\n#define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH0R_DATA5_Pos    (8U)\n#define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH0R_DATA6_Pos    (16U)\n#define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH0R_DATA7_Pos    (24U)\n#define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI1R register  *******************/\n#define CAN_TI1R_TXRQ_Pos      (0U)\n#define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI1R_RTR_Pos       (1U)\n#define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI1R_IDE_Pos       (2U)\n#define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI1R_EXID_Pos      (3U)\n#define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI1R_STID_Pos      (21U)\n#define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT1R register  ******************/\n#define CAN_TDT1R_DLC_Pos      (0U)\n#define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT1R_TGT_Pos      (8U)\n#define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT1R_TIME_Pos     (16U)\n#define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL1R register  ******************/\n#define CAN_TDL1R_DATA0_Pos    (0U)\n#define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL1R_DATA1_Pos    (8U)\n#define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL1R_DATA2_Pos    (16U)\n#define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL1R_DATA3_Pos    (24U)\n#define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH1R register  ******************/\n#define CAN_TDH1R_DATA4_Pos    (0U)\n#define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH1R_DATA5_Pos    (8U)\n#define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH1R_DATA6_Pos    (16U)\n#define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH1R_DATA7_Pos    (24U)\n#define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI2R register  *******************/\n#define CAN_TI2R_TXRQ_Pos      (0U)\n#define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI2R_RTR_Pos       (1U)\n#define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI2R_IDE_Pos       (2U)\n#define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI2R_EXID_Pos      (3U)\n#define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_TI2R_STID_Pos      (21U)\n#define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT2R register  ******************/\n#define CAN_TDT2R_DLC_Pos      (0U)\n#define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT2R_TGT_Pos      (8U)\n#define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT2R_TIME_Pos     (16U)\n#define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL2R register  ******************/\n#define CAN_TDL2R_DATA0_Pos    (0U)\n#define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL2R_DATA1_Pos    (8U)\n#define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL2R_DATA2_Pos    (16U)\n#define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL2R_DATA3_Pos    (24U)\n#define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH2R register  ******************/\n#define CAN_TDH2R_DATA4_Pos    (0U)\n#define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH2R_DATA5_Pos    (8U)\n#define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH2R_DATA6_Pos    (16U)\n#define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH2R_DATA7_Pos    (24U)\n#define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI0R register  *******************/\n#define CAN_RI0R_RTR_Pos       (1U)\n#define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI0R_IDE_Pos       (2U)\n#define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI0R_EXID_Pos      (3U)\n#define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_RI0R_STID_Pos      (21U)\n#define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT0R register  ******************/\n#define CAN_RDT0R_DLC_Pos      (0U)\n#define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT0R_FMI_Pos      (8U)\n#define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT0R_TIME_Pos     (16U)\n#define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL0R register  ******************/\n#define CAN_RDL0R_DATA0_Pos    (0U)\n#define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL0R_DATA1_Pos    (8U)\n#define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL0R_DATA2_Pos    (16U)\n#define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL0R_DATA3_Pos    (24U)\n#define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH0R register  ******************/\n#define CAN_RDH0R_DATA4_Pos    (0U)\n#define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH0R_DATA5_Pos    (8U)\n#define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH0R_DATA6_Pos    (16U)\n#define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH0R_DATA7_Pos    (24U)\n#define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI1R register  *******************/\n#define CAN_RI1R_RTR_Pos       (1U)\n#define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI1R_IDE_Pos       (2U)\n#define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI1R_EXID_Pos      (3U)\n#define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_RI1R_STID_Pos      (21U)\n#define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT1R register  ******************/\n#define CAN_RDT1R_DLC_Pos      (0U)\n#define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT1R_FMI_Pos      (8U)\n#define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT1R_TIME_Pos     (16U)\n#define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL1R register  ******************/\n#define CAN_RDL1R_DATA0_Pos    (0U)\n#define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL1R_DATA1_Pos    (8U)\n#define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL1R_DATA2_Pos    (16U)\n#define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL1R_DATA3_Pos    (24U)\n#define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH1R register  ******************/\n#define CAN_RDH1R_DATA4_Pos    (0U)\n#define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH1R_DATA5_Pos    (8U)\n#define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH1R_DATA6_Pos    (16U)\n#define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH1R_DATA7_Pos    (24U)\n#define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*!<CAN filter registers */\n/*******************  Bit definition for CAN_FMR register  ********************/\n#define CAN_FMR_FINIT_Pos      (0U)\n#define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */\n#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */\n#define CAN_FMR_CAN2SB_Pos     (8U)\n#define CAN_FMR_CAN2SB_Msk     (0x3FUL << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */\n#define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */\n\n/*******************  Bit definition for CAN_FM1R register  *******************/\n#define CAN_FM1R_FBM_Pos       (0U)\n#define CAN_FM1R_FBM_Msk       (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */\n#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */\n#define CAN_FM1R_FBM0_Pos      (0U)\n#define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */\n#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */\n#define CAN_FM1R_FBM1_Pos      (1U)\n#define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */\n#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */\n#define CAN_FM1R_FBM2_Pos      (2U)\n#define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */\n#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */\n#define CAN_FM1R_FBM3_Pos      (3U)\n#define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */\n#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */\n#define CAN_FM1R_FBM4_Pos      (4U)\n#define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */\n#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */\n#define CAN_FM1R_FBM5_Pos      (5U)\n#define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */\n#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */\n#define CAN_FM1R_FBM6_Pos      (6U)\n#define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */\n#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */\n#define CAN_FM1R_FBM7_Pos      (7U)\n#define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */\n#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */\n#define CAN_FM1R_FBM8_Pos      (8U)\n#define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */\n#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */\n#define CAN_FM1R_FBM9_Pos      (9U)\n#define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */\n#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */\n#define CAN_FM1R_FBM10_Pos     (10U)\n#define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */\n#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */\n#define CAN_FM1R_FBM11_Pos     (11U)\n#define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */\n#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */\n#define CAN_FM1R_FBM12_Pos     (12U)\n#define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */\n#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */\n#define CAN_FM1R_FBM13_Pos     (13U)\n#define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */\n#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */\n#define CAN_FM1R_FBM14_Pos     (14U)\n#define CAN_FM1R_FBM14_Msk     (0x1UL << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */\n#define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */\n#define CAN_FM1R_FBM15_Pos     (15U)\n#define CAN_FM1R_FBM15_Msk     (0x1UL << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */\n#define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */\n#define CAN_FM1R_FBM16_Pos     (16U)\n#define CAN_FM1R_FBM16_Msk     (0x1UL << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */\n#define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */\n#define CAN_FM1R_FBM17_Pos     (17U)\n#define CAN_FM1R_FBM17_Msk     (0x1UL << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */\n#define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */\n#define CAN_FM1R_FBM18_Pos     (18U)\n#define CAN_FM1R_FBM18_Msk     (0x1UL << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */\n#define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */\n#define CAN_FM1R_FBM19_Pos     (19U)\n#define CAN_FM1R_FBM19_Msk     (0x1UL << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */\n#define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */\n#define CAN_FM1R_FBM20_Pos     (20U)\n#define CAN_FM1R_FBM20_Msk     (0x1UL << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */\n#define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */\n#define CAN_FM1R_FBM21_Pos     (21U)\n#define CAN_FM1R_FBM21_Msk     (0x1UL << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */\n#define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */\n#define CAN_FM1R_FBM22_Pos     (22U)\n#define CAN_FM1R_FBM22_Msk     (0x1UL << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */\n#define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */\n#define CAN_FM1R_FBM23_Pos     (23U)\n#define CAN_FM1R_FBM23_Msk     (0x1UL << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */\n#define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */\n#define CAN_FM1R_FBM24_Pos     (24U)\n#define CAN_FM1R_FBM24_Msk     (0x1UL << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */\n#define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */\n#define CAN_FM1R_FBM25_Pos     (25U)\n#define CAN_FM1R_FBM25_Msk     (0x1UL << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */\n#define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */\n#define CAN_FM1R_FBM26_Pos     (26U)\n#define CAN_FM1R_FBM26_Msk     (0x1UL << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */\n#define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */\n#define CAN_FM1R_FBM27_Pos     (27U)\n#define CAN_FM1R_FBM27_Msk     (0x1UL << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */\n#define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */\n\n/*******************  Bit definition for CAN_FS1R register  *******************/\n#define CAN_FS1R_FSC_Pos       (0U)\n#define CAN_FS1R_FSC_Msk       (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */\n#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */\n#define CAN_FS1R_FSC0_Pos      (0U)\n#define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */\n#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */\n#define CAN_FS1R_FSC1_Pos      (1U)\n#define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */\n#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */\n#define CAN_FS1R_FSC2_Pos      (2U)\n#define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */\n#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */\n#define CAN_FS1R_FSC3_Pos      (3U)\n#define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */\n#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */\n#define CAN_FS1R_FSC4_Pos      (4U)\n#define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */\n#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */\n#define CAN_FS1R_FSC5_Pos      (5U)\n#define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */\n#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */\n#define CAN_FS1R_FSC6_Pos      (6U)\n#define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */\n#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */\n#define CAN_FS1R_FSC7_Pos      (7U)\n#define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */\n#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */\n#define CAN_FS1R_FSC8_Pos      (8U)\n#define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */\n#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */\n#define CAN_FS1R_FSC9_Pos      (9U)\n#define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */\n#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */\n#define CAN_FS1R_FSC10_Pos     (10U)\n#define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */\n#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */\n#define CAN_FS1R_FSC11_Pos     (11U)\n#define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */\n#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */\n#define CAN_FS1R_FSC12_Pos     (12U)\n#define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */\n#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */\n#define CAN_FS1R_FSC13_Pos     (13U)\n#define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */\n#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */\n#define CAN_FS1R_FSC14_Pos     (14U)\n#define CAN_FS1R_FSC14_Msk     (0x1UL << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */\n#define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */\n#define CAN_FS1R_FSC15_Pos     (15U)\n#define CAN_FS1R_FSC15_Msk     (0x1UL << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */\n#define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */\n#define CAN_FS1R_FSC16_Pos     (16U)\n#define CAN_FS1R_FSC16_Msk     (0x1UL << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */\n#define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */\n#define CAN_FS1R_FSC17_Pos     (17U)\n#define CAN_FS1R_FSC17_Msk     (0x1UL << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */\n#define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */\n#define CAN_FS1R_FSC18_Pos     (18U)\n#define CAN_FS1R_FSC18_Msk     (0x1UL << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */\n#define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */\n#define CAN_FS1R_FSC19_Pos     (19U)\n#define CAN_FS1R_FSC19_Msk     (0x1UL << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */\n#define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */\n#define CAN_FS1R_FSC20_Pos     (20U)\n#define CAN_FS1R_FSC20_Msk     (0x1UL << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */\n#define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */\n#define CAN_FS1R_FSC21_Pos     (21U)\n#define CAN_FS1R_FSC21_Msk     (0x1UL << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */\n#define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */\n#define CAN_FS1R_FSC22_Pos     (22U)\n#define CAN_FS1R_FSC22_Msk     (0x1UL << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */\n#define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */\n#define CAN_FS1R_FSC23_Pos     (23U)\n#define CAN_FS1R_FSC23_Msk     (0x1UL << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */\n#define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */\n#define CAN_FS1R_FSC24_Pos     (24U)\n#define CAN_FS1R_FSC24_Msk     (0x1UL << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */\n#define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */\n#define CAN_FS1R_FSC25_Pos     (25U)\n#define CAN_FS1R_FSC25_Msk     (0x1UL << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */\n#define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */\n#define CAN_FS1R_FSC26_Pos     (26U)\n#define CAN_FS1R_FSC26_Msk     (0x1UL << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */\n#define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */\n#define CAN_FS1R_FSC27_Pos     (27U)\n#define CAN_FS1R_FSC27_Msk     (0x1UL << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */\n#define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */\n\n/******************  Bit definition for CAN_FFA1R register  *******************/\n#define CAN_FFA1R_FFA_Pos      (0U)\n#define CAN_FFA1R_FFA_Msk      (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */\n#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */\n#define CAN_FFA1R_FFA0_Pos     (0U)\n#define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */\n#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */\n#define CAN_FFA1R_FFA1_Pos     (1U)\n#define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */\n#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */\n#define CAN_FFA1R_FFA2_Pos     (2U)\n#define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */\n#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */\n#define CAN_FFA1R_FFA3_Pos     (3U)\n#define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */\n#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */\n#define CAN_FFA1R_FFA4_Pos     (4U)\n#define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */\n#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */\n#define CAN_FFA1R_FFA5_Pos     (5U)\n#define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */\n#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */\n#define CAN_FFA1R_FFA6_Pos     (6U)\n#define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */\n#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */\n#define CAN_FFA1R_FFA7_Pos     (7U)\n#define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */\n#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */\n#define CAN_FFA1R_FFA8_Pos     (8U)\n#define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */\n#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */\n#define CAN_FFA1R_FFA9_Pos     (9U)\n#define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */\n#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */\n#define CAN_FFA1R_FFA10_Pos    (10U)\n#define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */\n#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */\n#define CAN_FFA1R_FFA11_Pos    (11U)\n#define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */\n#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */\n#define CAN_FFA1R_FFA12_Pos    (12U)\n#define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */\n#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */\n#define CAN_FFA1R_FFA13_Pos    (13U)\n#define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */\n#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */\n#define CAN_FFA1R_FFA14_Pos    (14U)\n#define CAN_FFA1R_FFA14_Msk    (0x1UL << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */\n#define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */\n#define CAN_FFA1R_FFA15_Pos    (15U)\n#define CAN_FFA1R_FFA15_Msk    (0x1UL << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */\n#define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */\n#define CAN_FFA1R_FFA16_Pos    (16U)\n#define CAN_FFA1R_FFA16_Msk    (0x1UL << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */\n#define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */\n#define CAN_FFA1R_FFA17_Pos    (17U)\n#define CAN_FFA1R_FFA17_Msk    (0x1UL << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */\n#define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */\n#define CAN_FFA1R_FFA18_Pos    (18U)\n#define CAN_FFA1R_FFA18_Msk    (0x1UL << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */\n#define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */\n#define CAN_FFA1R_FFA19_Pos    (19U)\n#define CAN_FFA1R_FFA19_Msk    (0x1UL << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */\n#define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */\n#define CAN_FFA1R_FFA20_Pos    (20U)\n#define CAN_FFA1R_FFA20_Msk    (0x1UL << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */\n#define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */\n#define CAN_FFA1R_FFA21_Pos    (21U)\n#define CAN_FFA1R_FFA21_Msk    (0x1UL << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */\n#define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */\n#define CAN_FFA1R_FFA22_Pos    (22U)\n#define CAN_FFA1R_FFA22_Msk    (0x1UL << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */\n#define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */\n#define CAN_FFA1R_FFA23_Pos    (23U)\n#define CAN_FFA1R_FFA23_Msk    (0x1UL << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */\n#define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */\n#define CAN_FFA1R_FFA24_Pos    (24U)\n#define CAN_FFA1R_FFA24_Msk    (0x1UL << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */\n#define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */\n#define CAN_FFA1R_FFA25_Pos    (25U)\n#define CAN_FFA1R_FFA25_Msk    (0x1UL << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */\n#define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */\n#define CAN_FFA1R_FFA26_Pos    (26U)\n#define CAN_FFA1R_FFA26_Msk    (0x1UL << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */\n#define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */\n#define CAN_FFA1R_FFA27_Pos    (27U)\n#define CAN_FFA1R_FFA27_Msk    (0x1UL << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */\n#define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */\n\n/*******************  Bit definition for CAN_FA1R register  *******************/\n#define CAN_FA1R_FACT_Pos      (0U)\n#define CAN_FA1R_FACT_Msk      (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */\n#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */\n#define CAN_FA1R_FACT0_Pos     (0U)\n#define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */\n#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */\n#define CAN_FA1R_FACT1_Pos     (1U)\n#define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */\n#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */\n#define CAN_FA1R_FACT2_Pos     (2U)\n#define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */\n#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */\n#define CAN_FA1R_FACT3_Pos     (3U)\n#define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */\n#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */\n#define CAN_FA1R_FACT4_Pos     (4U)\n#define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */\n#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */\n#define CAN_FA1R_FACT5_Pos     (5U)\n#define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */\n#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */\n#define CAN_FA1R_FACT6_Pos     (6U)\n#define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */\n#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */\n#define CAN_FA1R_FACT7_Pos     (7U)\n#define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */\n#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */\n#define CAN_FA1R_FACT8_Pos     (8U)\n#define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */\n#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */\n#define CAN_FA1R_FACT9_Pos     (9U)\n#define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */\n#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */\n#define CAN_FA1R_FACT10_Pos    (10U)\n#define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */\n#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */\n#define CAN_FA1R_FACT11_Pos    (11U)\n#define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */\n#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */\n#define CAN_FA1R_FACT12_Pos    (12U)\n#define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */\n#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */\n#define CAN_FA1R_FACT13_Pos    (13U)\n#define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */\n#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */\n#define CAN_FA1R_FACT14_Pos    (14U)\n#define CAN_FA1R_FACT14_Msk    (0x1UL << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */\n#define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */\n#define CAN_FA1R_FACT15_Pos    (15U)\n#define CAN_FA1R_FACT15_Msk    (0x1UL << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */\n#define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */\n#define CAN_FA1R_FACT16_Pos    (16U)\n#define CAN_FA1R_FACT16_Msk    (0x1UL << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */\n#define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */\n#define CAN_FA1R_FACT17_Pos    (17U)\n#define CAN_FA1R_FACT17_Msk    (0x1UL << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */\n#define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */\n#define CAN_FA1R_FACT18_Pos    (18U)\n#define CAN_FA1R_FACT18_Msk    (0x1UL << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */\n#define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */\n#define CAN_FA1R_FACT19_Pos    (19U)\n#define CAN_FA1R_FACT19_Msk    (0x1UL << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */\n#define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */\n#define CAN_FA1R_FACT20_Pos    (20U)\n#define CAN_FA1R_FACT20_Msk    (0x1UL << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */\n#define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */\n#define CAN_FA1R_FACT21_Pos    (21U)\n#define CAN_FA1R_FACT21_Msk    (0x1UL << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */\n#define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */\n#define CAN_FA1R_FACT22_Pos    (22U)\n#define CAN_FA1R_FACT22_Msk    (0x1UL << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */\n#define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */\n#define CAN_FA1R_FACT23_Pos    (23U)\n#define CAN_FA1R_FACT23_Msk    (0x1UL << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */\n#define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */\n#define CAN_FA1R_FACT24_Pos    (24U)\n#define CAN_FA1R_FACT24_Msk    (0x1UL << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */\n#define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */\n#define CAN_FA1R_FACT25_Pos    (25U)\n#define CAN_FA1R_FACT25_Msk    (0x1UL << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */\n#define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */\n#define CAN_FA1R_FACT26_Pos    (26U)\n#define CAN_FA1R_FACT26_Msk    (0x1UL << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */\n#define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */\n#define CAN_FA1R_FACT27_Pos    (27U)\n#define CAN_FA1R_FACT27_Msk    (0x1UL << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */\n#define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */\n\n\n/*******************  Bit definition for CAN_F0R1 register  *******************/\n#define CAN_F0R1_FB0_Pos       (0U)\n#define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R1_FB1_Pos       (1U)\n#define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R1_FB2_Pos       (2U)\n#define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R1_FB3_Pos       (3U)\n#define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R1_FB4_Pos       (4U)\n#define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R1_FB5_Pos       (5U)\n#define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R1_FB6_Pos       (6U)\n#define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R1_FB7_Pos       (7U)\n#define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R1_FB8_Pos       (8U)\n#define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R1_FB9_Pos       (9U)\n#define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R1_FB10_Pos      (10U)\n#define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R1_FB11_Pos      (11U)\n#define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R1_FB12_Pos      (12U)\n#define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R1_FB13_Pos      (13U)\n#define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R1_FB14_Pos      (14U)\n#define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R1_FB15_Pos      (15U)\n#define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R1_FB16_Pos      (16U)\n#define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R1_FB17_Pos      (17U)\n#define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R1_FB18_Pos      (18U)\n#define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R1_FB19_Pos      (19U)\n#define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R1_FB20_Pos      (20U)\n#define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R1_FB21_Pos      (21U)\n#define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R1_FB22_Pos      (22U)\n#define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R1_FB23_Pos      (23U)\n#define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R1_FB24_Pos      (24U)\n#define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R1_FB25_Pos      (25U)\n#define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R1_FB26_Pos      (26U)\n#define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R1_FB27_Pos      (27U)\n#define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R1_FB28_Pos      (28U)\n#define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R1_FB29_Pos      (29U)\n#define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R1_FB30_Pos      (30U)\n#define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R1_FB31_Pos      (31U)\n#define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R1 register  *******************/\n#define CAN_F1R1_FB0_Pos       (0U)\n#define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R1_FB1_Pos       (1U)\n#define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R1_FB2_Pos       (2U)\n#define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R1_FB3_Pos       (3U)\n#define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R1_FB4_Pos       (4U)\n#define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R1_FB5_Pos       (5U)\n#define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R1_FB6_Pos       (6U)\n#define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R1_FB7_Pos       (7U)\n#define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R1_FB8_Pos       (8U)\n#define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R1_FB9_Pos       (9U)\n#define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R1_FB10_Pos      (10U)\n#define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R1_FB11_Pos      (11U)\n#define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R1_FB12_Pos      (12U)\n#define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R1_FB13_Pos      (13U)\n#define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R1_FB14_Pos      (14U)\n#define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R1_FB15_Pos      (15U)\n#define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R1_FB16_Pos      (16U)\n#define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R1_FB17_Pos      (17U)\n#define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R1_FB18_Pos      (18U)\n#define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R1_FB19_Pos      (19U)\n#define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R1_FB20_Pos      (20U)\n#define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R1_FB21_Pos      (21U)\n#define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R1_FB22_Pos      (22U)\n#define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R1_FB23_Pos      (23U)\n#define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R1_FB24_Pos      (24U)\n#define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R1_FB25_Pos      (25U)\n#define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R1_FB26_Pos      (26U)\n#define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R1_FB27_Pos      (27U)\n#define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R1_FB28_Pos      (28U)\n#define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R1_FB29_Pos      (29U)\n#define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R1_FB30_Pos      (30U)\n#define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R1_FB31_Pos      (31U)\n#define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R1 register  *******************/\n#define CAN_F2R1_FB0_Pos       (0U)\n#define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R1_FB1_Pos       (1U)\n#define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R1_FB2_Pos       (2U)\n#define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R1_FB3_Pos       (3U)\n#define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R1_FB4_Pos       (4U)\n#define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R1_FB5_Pos       (5U)\n#define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R1_FB6_Pos       (6U)\n#define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R1_FB7_Pos       (7U)\n#define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R1_FB8_Pos       (8U)\n#define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R1_FB9_Pos       (9U)\n#define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R1_FB10_Pos      (10U)\n#define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R1_FB11_Pos      (11U)\n#define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R1_FB12_Pos      (12U)\n#define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R1_FB13_Pos      (13U)\n#define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R1_FB14_Pos      (14U)\n#define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R1_FB15_Pos      (15U)\n#define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R1_FB16_Pos      (16U)\n#define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R1_FB17_Pos      (17U)\n#define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R1_FB18_Pos      (18U)\n#define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R1_FB19_Pos      (19U)\n#define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R1_FB20_Pos      (20U)\n#define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R1_FB21_Pos      (21U)\n#define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R1_FB22_Pos      (22U)\n#define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R1_FB23_Pos      (23U)\n#define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R1_FB24_Pos      (24U)\n#define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R1_FB25_Pos      (25U)\n#define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R1_FB26_Pos      (26U)\n#define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R1_FB27_Pos      (27U)\n#define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R1_FB28_Pos      (28U)\n#define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R1_FB29_Pos      (29U)\n#define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R1_FB30_Pos      (30U)\n#define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R1_FB31_Pos      (31U)\n#define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R1 register  *******************/\n#define CAN_F3R1_FB0_Pos       (0U)\n#define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R1_FB1_Pos       (1U)\n#define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R1_FB2_Pos       (2U)\n#define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R1_FB3_Pos       (3U)\n#define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R1_FB4_Pos       (4U)\n#define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R1_FB5_Pos       (5U)\n#define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R1_FB6_Pos       (6U)\n#define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R1_FB7_Pos       (7U)\n#define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R1_FB8_Pos       (8U)\n#define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R1_FB9_Pos       (9U)\n#define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R1_FB10_Pos      (10U)\n#define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R1_FB11_Pos      (11U)\n#define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R1_FB12_Pos      (12U)\n#define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R1_FB13_Pos      (13U)\n#define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R1_FB14_Pos      (14U)\n#define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R1_FB15_Pos      (15U)\n#define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R1_FB16_Pos      (16U)\n#define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R1_FB17_Pos      (17U)\n#define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R1_FB18_Pos      (18U)\n#define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R1_FB19_Pos      (19U)\n#define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R1_FB20_Pos      (20U)\n#define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R1_FB21_Pos      (21U)\n#define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R1_FB22_Pos      (22U)\n#define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R1_FB23_Pos      (23U)\n#define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R1_FB24_Pos      (24U)\n#define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R1_FB25_Pos      (25U)\n#define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R1_FB26_Pos      (26U)\n#define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R1_FB27_Pos      (27U)\n#define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R1_FB28_Pos      (28U)\n#define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R1_FB29_Pos      (29U)\n#define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R1_FB30_Pos      (30U)\n#define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R1_FB31_Pos      (31U)\n#define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R1 register  *******************/\n#define CAN_F4R1_FB0_Pos       (0U)\n#define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R1_FB1_Pos       (1U)\n#define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R1_FB2_Pos       (2U)\n#define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R1_FB3_Pos       (3U)\n#define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R1_FB4_Pos       (4U)\n#define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R1_FB5_Pos       (5U)\n#define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R1_FB6_Pos       (6U)\n#define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R1_FB7_Pos       (7U)\n#define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R1_FB8_Pos       (8U)\n#define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R1_FB9_Pos       (9U)\n#define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R1_FB10_Pos      (10U)\n#define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R1_FB11_Pos      (11U)\n#define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R1_FB12_Pos      (12U)\n#define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R1_FB13_Pos      (13U)\n#define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R1_FB14_Pos      (14U)\n#define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R1_FB15_Pos      (15U)\n#define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R1_FB16_Pos      (16U)\n#define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R1_FB17_Pos      (17U)\n#define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R1_FB18_Pos      (18U)\n#define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R1_FB19_Pos      (19U)\n#define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R1_FB20_Pos      (20U)\n#define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R1_FB21_Pos      (21U)\n#define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R1_FB22_Pos      (22U)\n#define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R1_FB23_Pos      (23U)\n#define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R1_FB24_Pos      (24U)\n#define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R1_FB25_Pos      (25U)\n#define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R1_FB26_Pos      (26U)\n#define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R1_FB27_Pos      (27U)\n#define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R1_FB28_Pos      (28U)\n#define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R1_FB29_Pos      (29U)\n#define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R1_FB30_Pos      (30U)\n#define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R1_FB31_Pos      (31U)\n#define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R1 register  *******************/\n#define CAN_F5R1_FB0_Pos       (0U)\n#define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R1_FB1_Pos       (1U)\n#define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R1_FB2_Pos       (2U)\n#define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R1_FB3_Pos       (3U)\n#define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R1_FB4_Pos       (4U)\n#define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R1_FB5_Pos       (5U)\n#define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R1_FB6_Pos       (6U)\n#define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R1_FB7_Pos       (7U)\n#define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R1_FB8_Pos       (8U)\n#define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R1_FB9_Pos       (9U)\n#define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R1_FB10_Pos      (10U)\n#define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R1_FB11_Pos      (11U)\n#define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R1_FB12_Pos      (12U)\n#define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R1_FB13_Pos      (13U)\n#define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R1_FB14_Pos      (14U)\n#define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R1_FB15_Pos      (15U)\n#define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R1_FB16_Pos      (16U)\n#define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R1_FB17_Pos      (17U)\n#define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R1_FB18_Pos      (18U)\n#define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R1_FB19_Pos      (19U)\n#define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R1_FB20_Pos      (20U)\n#define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R1_FB21_Pos      (21U)\n#define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R1_FB22_Pos      (22U)\n#define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R1_FB23_Pos      (23U)\n#define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R1_FB24_Pos      (24U)\n#define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R1_FB25_Pos      (25U)\n#define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R1_FB26_Pos      (26U)\n#define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R1_FB27_Pos      (27U)\n#define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R1_FB28_Pos      (28U)\n#define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R1_FB29_Pos      (29U)\n#define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R1_FB30_Pos      (30U)\n#define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R1_FB31_Pos      (31U)\n#define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R1 register  *******************/\n#define CAN_F6R1_FB0_Pos       (0U)\n#define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R1_FB1_Pos       (1U)\n#define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R1_FB2_Pos       (2U)\n#define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R1_FB3_Pos       (3U)\n#define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R1_FB4_Pos       (4U)\n#define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R1_FB5_Pos       (5U)\n#define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R1_FB6_Pos       (6U)\n#define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R1_FB7_Pos       (7U)\n#define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R1_FB8_Pos       (8U)\n#define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R1_FB9_Pos       (9U)\n#define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R1_FB10_Pos      (10U)\n#define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R1_FB11_Pos      (11U)\n#define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R1_FB12_Pos      (12U)\n#define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R1_FB13_Pos      (13U)\n#define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R1_FB14_Pos      (14U)\n#define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R1_FB15_Pos      (15U)\n#define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R1_FB16_Pos      (16U)\n#define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R1_FB17_Pos      (17U)\n#define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R1_FB18_Pos      (18U)\n#define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R1_FB19_Pos      (19U)\n#define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R1_FB20_Pos      (20U)\n#define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R1_FB21_Pos      (21U)\n#define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R1_FB22_Pos      (22U)\n#define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R1_FB23_Pos      (23U)\n#define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R1_FB24_Pos      (24U)\n#define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R1_FB25_Pos      (25U)\n#define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R1_FB26_Pos      (26U)\n#define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R1_FB27_Pos      (27U)\n#define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R1_FB28_Pos      (28U)\n#define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R1_FB29_Pos      (29U)\n#define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R1_FB30_Pos      (30U)\n#define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R1_FB31_Pos      (31U)\n#define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R1 register  *******************/\n#define CAN_F7R1_FB0_Pos       (0U)\n#define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R1_FB1_Pos       (1U)\n#define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R1_FB2_Pos       (2U)\n#define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R1_FB3_Pos       (3U)\n#define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R1_FB4_Pos       (4U)\n#define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R1_FB5_Pos       (5U)\n#define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R1_FB6_Pos       (6U)\n#define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R1_FB7_Pos       (7U)\n#define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R1_FB8_Pos       (8U)\n#define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R1_FB9_Pos       (9U)\n#define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R1_FB10_Pos      (10U)\n#define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R1_FB11_Pos      (11U)\n#define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R1_FB12_Pos      (12U)\n#define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R1_FB13_Pos      (13U)\n#define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R1_FB14_Pos      (14U)\n#define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R1_FB15_Pos      (15U)\n#define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R1_FB16_Pos      (16U)\n#define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R1_FB17_Pos      (17U)\n#define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R1_FB18_Pos      (18U)\n#define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R1_FB19_Pos      (19U)\n#define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R1_FB20_Pos      (20U)\n#define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R1_FB21_Pos      (21U)\n#define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R1_FB22_Pos      (22U)\n#define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R1_FB23_Pos      (23U)\n#define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R1_FB24_Pos      (24U)\n#define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R1_FB25_Pos      (25U)\n#define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R1_FB26_Pos      (26U)\n#define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R1_FB27_Pos      (27U)\n#define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R1_FB28_Pos      (28U)\n#define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R1_FB29_Pos      (29U)\n#define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R1_FB30_Pos      (30U)\n#define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R1_FB31_Pos      (31U)\n#define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R1 register  *******************/\n#define CAN_F8R1_FB0_Pos       (0U)\n#define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R1_FB1_Pos       (1U)\n#define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R1_FB2_Pos       (2U)\n#define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R1_FB3_Pos       (3U)\n#define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R1_FB4_Pos       (4U)\n#define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R1_FB5_Pos       (5U)\n#define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R1_FB6_Pos       (6U)\n#define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R1_FB7_Pos       (7U)\n#define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R1_FB8_Pos       (8U)\n#define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R1_FB9_Pos       (9U)\n#define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R1_FB10_Pos      (10U)\n#define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R1_FB11_Pos      (11U)\n#define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R1_FB12_Pos      (12U)\n#define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R1_FB13_Pos      (13U)\n#define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R1_FB14_Pos      (14U)\n#define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R1_FB15_Pos      (15U)\n#define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R1_FB16_Pos      (16U)\n#define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R1_FB17_Pos      (17U)\n#define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R1_FB18_Pos      (18U)\n#define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R1_FB19_Pos      (19U)\n#define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R1_FB20_Pos      (20U)\n#define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R1_FB21_Pos      (21U)\n#define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R1_FB22_Pos      (22U)\n#define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R1_FB23_Pos      (23U)\n#define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R1_FB24_Pos      (24U)\n#define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R1_FB25_Pos      (25U)\n#define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R1_FB26_Pos      (26U)\n#define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R1_FB27_Pos      (27U)\n#define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R1_FB28_Pos      (28U)\n#define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R1_FB29_Pos      (29U)\n#define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R1_FB30_Pos      (30U)\n#define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R1_FB31_Pos      (31U)\n#define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R1 register  *******************/\n#define CAN_F9R1_FB0_Pos       (0U)\n#define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R1_FB1_Pos       (1U)\n#define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R1_FB2_Pos       (2U)\n#define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R1_FB3_Pos       (3U)\n#define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R1_FB4_Pos       (4U)\n#define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R1_FB5_Pos       (5U)\n#define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R1_FB6_Pos       (6U)\n#define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R1_FB7_Pos       (7U)\n#define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R1_FB8_Pos       (8U)\n#define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R1_FB9_Pos       (9U)\n#define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R1_FB10_Pos      (10U)\n#define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R1_FB11_Pos      (11U)\n#define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R1_FB12_Pos      (12U)\n#define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R1_FB13_Pos      (13U)\n#define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R1_FB14_Pos      (14U)\n#define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R1_FB15_Pos      (15U)\n#define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R1_FB16_Pos      (16U)\n#define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R1_FB17_Pos      (17U)\n#define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R1_FB18_Pos      (18U)\n#define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R1_FB19_Pos      (19U)\n#define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R1_FB20_Pos      (20U)\n#define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R1_FB21_Pos      (21U)\n#define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R1_FB22_Pos      (22U)\n#define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R1_FB23_Pos      (23U)\n#define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R1_FB24_Pos      (24U)\n#define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R1_FB25_Pos      (25U)\n#define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R1_FB26_Pos      (26U)\n#define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R1_FB27_Pos      (27U)\n#define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R1_FB28_Pos      (28U)\n#define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R1_FB29_Pos      (29U)\n#define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R1_FB30_Pos      (30U)\n#define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R1_FB31_Pos      (31U)\n#define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R1 register  ******************/\n#define CAN_F10R1_FB0_Pos      (0U)\n#define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R1_FB1_Pos      (1U)\n#define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R1_FB2_Pos      (2U)\n#define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R1_FB3_Pos      (3U)\n#define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R1_FB4_Pos      (4U)\n#define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R1_FB5_Pos      (5U)\n#define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R1_FB6_Pos      (6U)\n#define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R1_FB7_Pos      (7U)\n#define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R1_FB8_Pos      (8U)\n#define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R1_FB9_Pos      (9U)\n#define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R1_FB10_Pos     (10U)\n#define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R1_FB11_Pos     (11U)\n#define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R1_FB12_Pos     (12U)\n#define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R1_FB13_Pos     (13U)\n#define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R1_FB14_Pos     (14U)\n#define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R1_FB15_Pos     (15U)\n#define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R1_FB16_Pos     (16U)\n#define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R1_FB17_Pos     (17U)\n#define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R1_FB18_Pos     (18U)\n#define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R1_FB19_Pos     (19U)\n#define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R1_FB20_Pos     (20U)\n#define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R1_FB21_Pos     (21U)\n#define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R1_FB22_Pos     (22U)\n#define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R1_FB23_Pos     (23U)\n#define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R1_FB24_Pos     (24U)\n#define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R1_FB25_Pos     (25U)\n#define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R1_FB26_Pos     (26U)\n#define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R1_FB27_Pos     (27U)\n#define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R1_FB28_Pos     (28U)\n#define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R1_FB29_Pos     (29U)\n#define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R1_FB30_Pos     (30U)\n#define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R1_FB31_Pos     (31U)\n#define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R1 register  ******************/\n#define CAN_F11R1_FB0_Pos      (0U)\n#define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R1_FB1_Pos      (1U)\n#define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R1_FB2_Pos      (2U)\n#define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R1_FB3_Pos      (3U)\n#define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R1_FB4_Pos      (4U)\n#define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R1_FB5_Pos      (5U)\n#define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R1_FB6_Pos      (6U)\n#define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R1_FB7_Pos      (7U)\n#define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R1_FB8_Pos      (8U)\n#define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R1_FB9_Pos      (9U)\n#define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R1_FB10_Pos     (10U)\n#define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R1_FB11_Pos     (11U)\n#define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R1_FB12_Pos     (12U)\n#define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R1_FB13_Pos     (13U)\n#define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R1_FB14_Pos     (14U)\n#define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R1_FB15_Pos     (15U)\n#define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R1_FB16_Pos     (16U)\n#define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R1_FB17_Pos     (17U)\n#define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R1_FB18_Pos     (18U)\n#define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R1_FB19_Pos     (19U)\n#define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R1_FB20_Pos     (20U)\n#define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R1_FB21_Pos     (21U)\n#define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R1_FB22_Pos     (22U)\n#define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R1_FB23_Pos     (23U)\n#define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R1_FB24_Pos     (24U)\n#define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R1_FB25_Pos     (25U)\n#define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R1_FB26_Pos     (26U)\n#define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R1_FB27_Pos     (27U)\n#define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R1_FB28_Pos     (28U)\n#define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R1_FB29_Pos     (29U)\n#define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R1_FB30_Pos     (30U)\n#define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R1_FB31_Pos     (31U)\n#define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R1 register  ******************/\n#define CAN_F12R1_FB0_Pos      (0U)\n#define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R1_FB1_Pos      (1U)\n#define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R1_FB2_Pos      (2U)\n#define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R1_FB3_Pos      (3U)\n#define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R1_FB4_Pos      (4U)\n#define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R1_FB5_Pos      (5U)\n#define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R1_FB6_Pos      (6U)\n#define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R1_FB7_Pos      (7U)\n#define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R1_FB8_Pos      (8U)\n#define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R1_FB9_Pos      (9U)\n#define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R1_FB10_Pos     (10U)\n#define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R1_FB11_Pos     (11U)\n#define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R1_FB12_Pos     (12U)\n#define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R1_FB13_Pos     (13U)\n#define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R1_FB14_Pos     (14U)\n#define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R1_FB15_Pos     (15U)\n#define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R1_FB16_Pos     (16U)\n#define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R1_FB17_Pos     (17U)\n#define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R1_FB18_Pos     (18U)\n#define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R1_FB19_Pos     (19U)\n#define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R1_FB20_Pos     (20U)\n#define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R1_FB21_Pos     (21U)\n#define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R1_FB22_Pos     (22U)\n#define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R1_FB23_Pos     (23U)\n#define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R1_FB24_Pos     (24U)\n#define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R1_FB25_Pos     (25U)\n#define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R1_FB26_Pos     (26U)\n#define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R1_FB27_Pos     (27U)\n#define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R1_FB28_Pos     (28U)\n#define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R1_FB29_Pos     (29U)\n#define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R1_FB30_Pos     (30U)\n#define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R1_FB31_Pos     (31U)\n#define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R1 register  ******************/\n#define CAN_F13R1_FB0_Pos      (0U)\n#define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R1_FB1_Pos      (1U)\n#define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R1_FB2_Pos      (2U)\n#define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R1_FB3_Pos      (3U)\n#define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R1_FB4_Pos      (4U)\n#define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R1_FB5_Pos      (5U)\n#define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R1_FB6_Pos      (6U)\n#define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R1_FB7_Pos      (7U)\n#define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R1_FB8_Pos      (8U)\n#define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R1_FB9_Pos      (9U)\n#define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R1_FB10_Pos     (10U)\n#define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R1_FB11_Pos     (11U)\n#define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R1_FB12_Pos     (12U)\n#define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R1_FB13_Pos     (13U)\n#define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R1_FB14_Pos     (14U)\n#define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R1_FB15_Pos     (15U)\n#define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R1_FB16_Pos     (16U)\n#define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R1_FB17_Pos     (17U)\n#define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R1_FB18_Pos     (18U)\n#define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R1_FB19_Pos     (19U)\n#define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R1_FB20_Pos     (20U)\n#define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R1_FB21_Pos     (21U)\n#define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R1_FB22_Pos     (22U)\n#define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R1_FB23_Pos     (23U)\n#define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R1_FB24_Pos     (24U)\n#define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R1_FB25_Pos     (25U)\n#define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R1_FB26_Pos     (26U)\n#define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R1_FB27_Pos     (27U)\n#define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R1_FB28_Pos     (28U)\n#define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R1_FB29_Pos     (29U)\n#define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R1_FB30_Pos     (30U)\n#define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R1_FB31_Pos     (31U)\n#define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F0R2 register  *******************/\n#define CAN_F0R2_FB0_Pos       (0U)\n#define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R2_FB1_Pos       (1U)\n#define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R2_FB2_Pos       (2U)\n#define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R2_FB3_Pos       (3U)\n#define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R2_FB4_Pos       (4U)\n#define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R2_FB5_Pos       (5U)\n#define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R2_FB6_Pos       (6U)\n#define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R2_FB7_Pos       (7U)\n#define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R2_FB8_Pos       (8U)\n#define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R2_FB9_Pos       (9U)\n#define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R2_FB10_Pos      (10U)\n#define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R2_FB11_Pos      (11U)\n#define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R2_FB12_Pos      (12U)\n#define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R2_FB13_Pos      (13U)\n#define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R2_FB14_Pos      (14U)\n#define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R2_FB15_Pos      (15U)\n#define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R2_FB16_Pos      (16U)\n#define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R2_FB17_Pos      (17U)\n#define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R2_FB18_Pos      (18U)\n#define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R2_FB19_Pos      (19U)\n#define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R2_FB20_Pos      (20U)\n#define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R2_FB21_Pos      (21U)\n#define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R2_FB22_Pos      (22U)\n#define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R2_FB23_Pos      (23U)\n#define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R2_FB24_Pos      (24U)\n#define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R2_FB25_Pos      (25U)\n#define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R2_FB26_Pos      (26U)\n#define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R2_FB27_Pos      (27U)\n#define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R2_FB28_Pos      (28U)\n#define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R2_FB29_Pos      (29U)\n#define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R2_FB30_Pos      (30U)\n#define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R2_FB31_Pos      (31U)\n#define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R2 register  *******************/\n#define CAN_F1R2_FB0_Pos       (0U)\n#define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R2_FB1_Pos       (1U)\n#define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R2_FB2_Pos       (2U)\n#define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R2_FB3_Pos       (3U)\n#define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R2_FB4_Pos       (4U)\n#define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R2_FB5_Pos       (5U)\n#define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R2_FB6_Pos       (6U)\n#define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R2_FB7_Pos       (7U)\n#define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R2_FB8_Pos       (8U)\n#define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R2_FB9_Pos       (9U)\n#define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R2_FB10_Pos      (10U)\n#define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R2_FB11_Pos      (11U)\n#define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R2_FB12_Pos      (12U)\n#define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R2_FB13_Pos      (13U)\n#define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R2_FB14_Pos      (14U)\n#define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R2_FB15_Pos      (15U)\n#define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R2_FB16_Pos      (16U)\n#define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R2_FB17_Pos      (17U)\n#define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R2_FB18_Pos      (18U)\n#define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R2_FB19_Pos      (19U)\n#define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R2_FB20_Pos      (20U)\n#define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R2_FB21_Pos      (21U)\n#define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R2_FB22_Pos      (22U)\n#define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R2_FB23_Pos      (23U)\n#define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R2_FB24_Pos      (24U)\n#define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R2_FB25_Pos      (25U)\n#define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R2_FB26_Pos      (26U)\n#define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R2_FB27_Pos      (27U)\n#define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R2_FB28_Pos      (28U)\n#define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R2_FB29_Pos      (29U)\n#define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R2_FB30_Pos      (30U)\n#define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R2_FB31_Pos      (31U)\n#define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R2 register  *******************/\n#define CAN_F2R2_FB0_Pos       (0U)\n#define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R2_FB1_Pos       (1U)\n#define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R2_FB2_Pos       (2U)\n#define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R2_FB3_Pos       (3U)\n#define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R2_FB4_Pos       (4U)\n#define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R2_FB5_Pos       (5U)\n#define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R2_FB6_Pos       (6U)\n#define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R2_FB7_Pos       (7U)\n#define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R2_FB8_Pos       (8U)\n#define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R2_FB9_Pos       (9U)\n#define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R2_FB10_Pos      (10U)\n#define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R2_FB11_Pos      (11U)\n#define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R2_FB12_Pos      (12U)\n#define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R2_FB13_Pos      (13U)\n#define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R2_FB14_Pos      (14U)\n#define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R2_FB15_Pos      (15U)\n#define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R2_FB16_Pos      (16U)\n#define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R2_FB17_Pos      (17U)\n#define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R2_FB18_Pos      (18U)\n#define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R2_FB19_Pos      (19U)\n#define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R2_FB20_Pos      (20U)\n#define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R2_FB21_Pos      (21U)\n#define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R2_FB22_Pos      (22U)\n#define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R2_FB23_Pos      (23U)\n#define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R2_FB24_Pos      (24U)\n#define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R2_FB25_Pos      (25U)\n#define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R2_FB26_Pos      (26U)\n#define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R2_FB27_Pos      (27U)\n#define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R2_FB28_Pos      (28U)\n#define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R2_FB29_Pos      (29U)\n#define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R2_FB30_Pos      (30U)\n#define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R2_FB31_Pos      (31U)\n#define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R2 register  *******************/\n#define CAN_F3R2_FB0_Pos       (0U)\n#define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R2_FB1_Pos       (1U)\n#define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R2_FB2_Pos       (2U)\n#define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R2_FB3_Pos       (3U)\n#define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R2_FB4_Pos       (4U)\n#define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R2_FB5_Pos       (5U)\n#define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R2_FB6_Pos       (6U)\n#define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R2_FB7_Pos       (7U)\n#define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R2_FB8_Pos       (8U)\n#define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R2_FB9_Pos       (9U)\n#define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R2_FB10_Pos      (10U)\n#define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R2_FB11_Pos      (11U)\n#define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R2_FB12_Pos      (12U)\n#define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R2_FB13_Pos      (13U)\n#define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R2_FB14_Pos      (14U)\n#define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R2_FB15_Pos      (15U)\n#define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R2_FB16_Pos      (16U)\n#define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R2_FB17_Pos      (17U)\n#define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R2_FB18_Pos      (18U)\n#define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R2_FB19_Pos      (19U)\n#define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R2_FB20_Pos      (20U)\n#define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R2_FB21_Pos      (21U)\n#define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R2_FB22_Pos      (22U)\n#define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R2_FB23_Pos      (23U)\n#define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R2_FB24_Pos      (24U)\n#define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R2_FB25_Pos      (25U)\n#define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R2_FB26_Pos      (26U)\n#define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R2_FB27_Pos      (27U)\n#define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R2_FB28_Pos      (28U)\n#define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R2_FB29_Pos      (29U)\n#define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R2_FB30_Pos      (30U)\n#define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R2_FB31_Pos      (31U)\n#define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R2 register  *******************/\n#define CAN_F4R2_FB0_Pos       (0U)\n#define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R2_FB1_Pos       (1U)\n#define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R2_FB2_Pos       (2U)\n#define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R2_FB3_Pos       (3U)\n#define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R2_FB4_Pos       (4U)\n#define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R2_FB5_Pos       (5U)\n#define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R2_FB6_Pos       (6U)\n#define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R2_FB7_Pos       (7U)\n#define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R2_FB8_Pos       (8U)\n#define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R2_FB9_Pos       (9U)\n#define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R2_FB10_Pos      (10U)\n#define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R2_FB11_Pos      (11U)\n#define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R2_FB12_Pos      (12U)\n#define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R2_FB13_Pos      (13U)\n#define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R2_FB14_Pos      (14U)\n#define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R2_FB15_Pos      (15U)\n#define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R2_FB16_Pos      (16U)\n#define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R2_FB17_Pos      (17U)\n#define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R2_FB18_Pos      (18U)\n#define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R2_FB19_Pos      (19U)\n#define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R2_FB20_Pos      (20U)\n#define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R2_FB21_Pos      (21U)\n#define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R2_FB22_Pos      (22U)\n#define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R2_FB23_Pos      (23U)\n#define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R2_FB24_Pos      (24U)\n#define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R2_FB25_Pos      (25U)\n#define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R2_FB26_Pos      (26U)\n#define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R2_FB27_Pos      (27U)\n#define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R2_FB28_Pos      (28U)\n#define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R2_FB29_Pos      (29U)\n#define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R2_FB30_Pos      (30U)\n#define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R2_FB31_Pos      (31U)\n#define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R2 register  *******************/\n#define CAN_F5R2_FB0_Pos       (0U)\n#define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R2_FB1_Pos       (1U)\n#define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R2_FB2_Pos       (2U)\n#define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R2_FB3_Pos       (3U)\n#define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R2_FB4_Pos       (4U)\n#define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R2_FB5_Pos       (5U)\n#define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R2_FB6_Pos       (6U)\n#define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R2_FB7_Pos       (7U)\n#define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R2_FB8_Pos       (8U)\n#define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R2_FB9_Pos       (9U)\n#define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R2_FB10_Pos      (10U)\n#define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R2_FB11_Pos      (11U)\n#define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R2_FB12_Pos      (12U)\n#define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R2_FB13_Pos      (13U)\n#define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R2_FB14_Pos      (14U)\n#define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R2_FB15_Pos      (15U)\n#define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R2_FB16_Pos      (16U)\n#define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R2_FB17_Pos      (17U)\n#define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R2_FB18_Pos      (18U)\n#define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R2_FB19_Pos      (19U)\n#define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R2_FB20_Pos      (20U)\n#define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R2_FB21_Pos      (21U)\n#define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R2_FB22_Pos      (22U)\n#define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R2_FB23_Pos      (23U)\n#define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R2_FB24_Pos      (24U)\n#define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R2_FB25_Pos      (25U)\n#define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R2_FB26_Pos      (26U)\n#define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R2_FB27_Pos      (27U)\n#define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R2_FB28_Pos      (28U)\n#define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R2_FB29_Pos      (29U)\n#define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R2_FB30_Pos      (30U)\n#define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R2_FB31_Pos      (31U)\n#define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R2 register  *******************/\n#define CAN_F6R2_FB0_Pos       (0U)\n#define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R2_FB1_Pos       (1U)\n#define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R2_FB2_Pos       (2U)\n#define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R2_FB3_Pos       (3U)\n#define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R2_FB4_Pos       (4U)\n#define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R2_FB5_Pos       (5U)\n#define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R2_FB6_Pos       (6U)\n#define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R2_FB7_Pos       (7U)\n#define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R2_FB8_Pos       (8U)\n#define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R2_FB9_Pos       (9U)\n#define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R2_FB10_Pos      (10U)\n#define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R2_FB11_Pos      (11U)\n#define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R2_FB12_Pos      (12U)\n#define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R2_FB13_Pos      (13U)\n#define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R2_FB14_Pos      (14U)\n#define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R2_FB15_Pos      (15U)\n#define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R2_FB16_Pos      (16U)\n#define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R2_FB17_Pos      (17U)\n#define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R2_FB18_Pos      (18U)\n#define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R2_FB19_Pos      (19U)\n#define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R2_FB20_Pos      (20U)\n#define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R2_FB21_Pos      (21U)\n#define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R2_FB22_Pos      (22U)\n#define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R2_FB23_Pos      (23U)\n#define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R2_FB24_Pos      (24U)\n#define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R2_FB25_Pos      (25U)\n#define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R2_FB26_Pos      (26U)\n#define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R2_FB27_Pos      (27U)\n#define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R2_FB28_Pos      (28U)\n#define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R2_FB29_Pos      (29U)\n#define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R2_FB30_Pos      (30U)\n#define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R2_FB31_Pos      (31U)\n#define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R2 register  *******************/\n#define CAN_F7R2_FB0_Pos       (0U)\n#define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R2_FB1_Pos       (1U)\n#define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R2_FB2_Pos       (2U)\n#define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R2_FB3_Pos       (3U)\n#define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R2_FB4_Pos       (4U)\n#define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R2_FB5_Pos       (5U)\n#define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R2_FB6_Pos       (6U)\n#define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R2_FB7_Pos       (7U)\n#define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R2_FB8_Pos       (8U)\n#define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R2_FB9_Pos       (9U)\n#define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R2_FB10_Pos      (10U)\n#define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R2_FB11_Pos      (11U)\n#define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R2_FB12_Pos      (12U)\n#define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R2_FB13_Pos      (13U)\n#define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R2_FB14_Pos      (14U)\n#define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R2_FB15_Pos      (15U)\n#define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R2_FB16_Pos      (16U)\n#define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R2_FB17_Pos      (17U)\n#define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R2_FB18_Pos      (18U)\n#define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R2_FB19_Pos      (19U)\n#define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R2_FB20_Pos      (20U)\n#define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R2_FB21_Pos      (21U)\n#define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R2_FB22_Pos      (22U)\n#define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R2_FB23_Pos      (23U)\n#define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R2_FB24_Pos      (24U)\n#define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R2_FB25_Pos      (25U)\n#define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R2_FB26_Pos      (26U)\n#define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R2_FB27_Pos      (27U)\n#define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R2_FB28_Pos      (28U)\n#define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R2_FB29_Pos      (29U)\n#define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R2_FB30_Pos      (30U)\n#define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R2_FB31_Pos      (31U)\n#define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R2 register  *******************/\n#define CAN_F8R2_FB0_Pos       (0U)\n#define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R2_FB1_Pos       (1U)\n#define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R2_FB2_Pos       (2U)\n#define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R2_FB3_Pos       (3U)\n#define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R2_FB4_Pos       (4U)\n#define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R2_FB5_Pos       (5U)\n#define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R2_FB6_Pos       (6U)\n#define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R2_FB7_Pos       (7U)\n#define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R2_FB8_Pos       (8U)\n#define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R2_FB9_Pos       (9U)\n#define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R2_FB10_Pos      (10U)\n#define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R2_FB11_Pos      (11U)\n#define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R2_FB12_Pos      (12U)\n#define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R2_FB13_Pos      (13U)\n#define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R2_FB14_Pos      (14U)\n#define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R2_FB15_Pos      (15U)\n#define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R2_FB16_Pos      (16U)\n#define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R2_FB17_Pos      (17U)\n#define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R2_FB18_Pos      (18U)\n#define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R2_FB19_Pos      (19U)\n#define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R2_FB20_Pos      (20U)\n#define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R2_FB21_Pos      (21U)\n#define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R2_FB22_Pos      (22U)\n#define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R2_FB23_Pos      (23U)\n#define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R2_FB24_Pos      (24U)\n#define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R2_FB25_Pos      (25U)\n#define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R2_FB26_Pos      (26U)\n#define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R2_FB27_Pos      (27U)\n#define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R2_FB28_Pos      (28U)\n#define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R2_FB29_Pos      (29U)\n#define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R2_FB30_Pos      (30U)\n#define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R2_FB31_Pos      (31U)\n#define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R2 register  *******************/\n#define CAN_F9R2_FB0_Pos       (0U)\n#define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R2_FB1_Pos       (1U)\n#define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R2_FB2_Pos       (2U)\n#define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R2_FB3_Pos       (3U)\n#define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R2_FB4_Pos       (4U)\n#define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R2_FB5_Pos       (5U)\n#define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R2_FB6_Pos       (6U)\n#define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R2_FB7_Pos       (7U)\n#define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R2_FB8_Pos       (8U)\n#define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R2_FB9_Pos       (9U)\n#define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R2_FB10_Pos      (10U)\n#define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R2_FB11_Pos      (11U)\n#define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R2_FB12_Pos      (12U)\n#define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R2_FB13_Pos      (13U)\n#define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R2_FB14_Pos      (14U)\n#define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R2_FB15_Pos      (15U)\n#define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R2_FB16_Pos      (16U)\n#define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R2_FB17_Pos      (17U)\n#define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R2_FB18_Pos      (18U)\n#define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R2_FB19_Pos      (19U)\n#define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R2_FB20_Pos      (20U)\n#define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R2_FB21_Pos      (21U)\n#define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R2_FB22_Pos      (22U)\n#define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R2_FB23_Pos      (23U)\n#define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R2_FB24_Pos      (24U)\n#define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R2_FB25_Pos      (25U)\n#define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R2_FB26_Pos      (26U)\n#define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R2_FB27_Pos      (27U)\n#define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R2_FB28_Pos      (28U)\n#define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R2_FB29_Pos      (29U)\n#define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R2_FB30_Pos      (30U)\n#define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R2_FB31_Pos      (31U)\n#define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R2 register  ******************/\n#define CAN_F10R2_FB0_Pos      (0U)\n#define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R2_FB1_Pos      (1U)\n#define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R2_FB2_Pos      (2U)\n#define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R2_FB3_Pos      (3U)\n#define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R2_FB4_Pos      (4U)\n#define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R2_FB5_Pos      (5U)\n#define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R2_FB6_Pos      (6U)\n#define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R2_FB7_Pos      (7U)\n#define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R2_FB8_Pos      (8U)\n#define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R2_FB9_Pos      (9U)\n#define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R2_FB10_Pos     (10U)\n#define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R2_FB11_Pos     (11U)\n#define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R2_FB12_Pos     (12U)\n#define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R2_FB13_Pos     (13U)\n#define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R2_FB14_Pos     (14U)\n#define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R2_FB15_Pos     (15U)\n#define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R2_FB16_Pos     (16U)\n#define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R2_FB17_Pos     (17U)\n#define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R2_FB18_Pos     (18U)\n#define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R2_FB19_Pos     (19U)\n#define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R2_FB20_Pos     (20U)\n#define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R2_FB21_Pos     (21U)\n#define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R2_FB22_Pos     (22U)\n#define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R2_FB23_Pos     (23U)\n#define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R2_FB24_Pos     (24U)\n#define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R2_FB25_Pos     (25U)\n#define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R2_FB26_Pos     (26U)\n#define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R2_FB27_Pos     (27U)\n#define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R2_FB28_Pos     (28U)\n#define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R2_FB29_Pos     (29U)\n#define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R2_FB30_Pos     (30U)\n#define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R2_FB31_Pos     (31U)\n#define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R2 register  ******************/\n#define CAN_F11R2_FB0_Pos      (0U)\n#define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R2_FB1_Pos      (1U)\n#define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R2_FB2_Pos      (2U)\n#define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R2_FB3_Pos      (3U)\n#define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R2_FB4_Pos      (4U)\n#define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R2_FB5_Pos      (5U)\n#define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R2_FB6_Pos      (6U)\n#define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R2_FB7_Pos      (7U)\n#define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R2_FB8_Pos      (8U)\n#define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R2_FB9_Pos      (9U)\n#define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R2_FB10_Pos     (10U)\n#define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R2_FB11_Pos     (11U)\n#define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R2_FB12_Pos     (12U)\n#define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R2_FB13_Pos     (13U)\n#define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R2_FB14_Pos     (14U)\n#define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R2_FB15_Pos     (15U)\n#define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R2_FB16_Pos     (16U)\n#define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R2_FB17_Pos     (17U)\n#define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R2_FB18_Pos     (18U)\n#define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R2_FB19_Pos     (19U)\n#define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R2_FB20_Pos     (20U)\n#define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R2_FB21_Pos     (21U)\n#define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R2_FB22_Pos     (22U)\n#define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R2_FB23_Pos     (23U)\n#define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R2_FB24_Pos     (24U)\n#define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R2_FB25_Pos     (25U)\n#define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R2_FB26_Pos     (26U)\n#define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R2_FB27_Pos     (27U)\n#define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R2_FB28_Pos     (28U)\n#define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R2_FB29_Pos     (29U)\n#define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R2_FB30_Pos     (30U)\n#define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R2_FB31_Pos     (31U)\n#define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R2 register  ******************/\n#define CAN_F12R2_FB0_Pos      (0U)\n#define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R2_FB1_Pos      (1U)\n#define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R2_FB2_Pos      (2U)\n#define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R2_FB3_Pos      (3U)\n#define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R2_FB4_Pos      (4U)\n#define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R2_FB5_Pos      (5U)\n#define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R2_FB6_Pos      (6U)\n#define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R2_FB7_Pos      (7U)\n#define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R2_FB8_Pos      (8U)\n#define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R2_FB9_Pos      (9U)\n#define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R2_FB10_Pos     (10U)\n#define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R2_FB11_Pos     (11U)\n#define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R2_FB12_Pos     (12U)\n#define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R2_FB13_Pos     (13U)\n#define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R2_FB14_Pos     (14U)\n#define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R2_FB15_Pos     (15U)\n#define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R2_FB16_Pos     (16U)\n#define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R2_FB17_Pos     (17U)\n#define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R2_FB18_Pos     (18U)\n#define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R2_FB19_Pos     (19U)\n#define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R2_FB20_Pos     (20U)\n#define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R2_FB21_Pos     (21U)\n#define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R2_FB22_Pos     (22U)\n#define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R2_FB23_Pos     (23U)\n#define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R2_FB24_Pos     (24U)\n#define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R2_FB25_Pos     (25U)\n#define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R2_FB26_Pos     (26U)\n#define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R2_FB27_Pos     (27U)\n#define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R2_FB28_Pos     (28U)\n#define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R2_FB29_Pos     (29U)\n#define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R2_FB30_Pos     (30U)\n#define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R2_FB31_Pos     (31U)\n#define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R2 register  ******************/\n#define CAN_F13R2_FB0_Pos      (0U)\n#define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R2_FB1_Pos      (1U)\n#define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R2_FB2_Pos      (2U)\n#define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R2_FB3_Pos      (3U)\n#define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R2_FB4_Pos      (4U)\n#define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R2_FB5_Pos      (5U)\n#define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R2_FB6_Pos      (6U)\n#define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R2_FB7_Pos      (7U)\n#define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R2_FB8_Pos      (8U)\n#define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R2_FB9_Pos      (9U)\n#define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R2_FB10_Pos     (10U)\n#define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R2_FB11_Pos     (11U)\n#define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R2_FB12_Pos     (12U)\n#define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R2_FB13_Pos     (13U)\n#define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R2_FB14_Pos     (14U)\n#define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R2_FB15_Pos     (15U)\n#define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R2_FB16_Pos     (16U)\n#define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R2_FB17_Pos     (17U)\n#define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R2_FB18_Pos     (18U)\n#define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R2_FB19_Pos     (19U)\n#define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R2_FB20_Pos     (20U)\n#define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R2_FB21_Pos     (21U)\n#define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R2_FB22_Pos     (22U)\n#define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R2_FB23_Pos     (23U)\n#define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R2_FB24_Pos     (24U)\n#define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R2_FB25_Pos     (25U)\n#define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R2_FB26_Pos     (26U)\n#define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R2_FB27_Pos     (27U)\n#define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R2_FB28_Pos     (28U)\n#define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R2_FB29_Pos     (29U)\n#define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R2_FB30_Pos     (30U)\n#define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R2_FB31_Pos     (31U)\n#define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          CRC calculation unit                              */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for CRC_DR register  *********************/\n#define CRC_DR_DR_Pos       (0U)\n#define CRC_DR_DR_Msk       (0xFFFFFFFFUL << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */\n#define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */\n\n\n/*******************  Bit definition for CRC_IDR register  ********************/\n#define CRC_IDR_IDR_Pos     (0U)\n#define CRC_IDR_IDR_Msk     (0xFFUL << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */\n#define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */\n\n\n/********************  Bit definition for CRC_CR register  ********************/\n#define CRC_CR_RESET_Pos    (0U)\n#define CRC_CR_RESET_Msk    (0x1UL << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */\n#define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */\n\n/******************************************************************************/\n/*                                                                            */\n/*                 Digital Filter for Sigma Delta Modulators                  */\n/*                                                                            */\n/******************************************************************************/\n\n/****************   DFSDM channel configuration registers  ********************/\n\n/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/\n#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)\n#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)    /*!< 0x80000000 */\n#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */\n#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)\n#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)   /*!< 0x40000000 */\n#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */\n#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)\n#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos)  /*!< 0x00FF0000 */\n#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */\n#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)\n#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x0000C000 */\n#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */\n#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */\n#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */\n#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)\n#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00003000 */\n#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */\n#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */\n#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */\n#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)\n#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)    /*!< 0x00000100 */\n#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */\n#define DFSDM_CHCFGR1_CHEN_Pos          (7U)\n#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)       /*!< 0x00000080 */\n#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */\n#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)\n#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)     /*!< 0x00000040 */\n#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */\n#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)\n#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)      /*!< 0x00000020 */\n#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */\n#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)\n#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x0000000C */\n#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */\n#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */\n#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */\n#define DFSDM_CHCFGR1_SITP_Pos          (0U)\n#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000003 */\n#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */\n#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */\n#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */\n\n/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/\n#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)\n#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */\n#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)\n#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)     /*!< 0x000000F8 */\n#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */\n\n/****************  Bit definition for DFSDM_CHAWSCDR register *****************/\n#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)\n#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00C00000 */\n#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */\n#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */\n#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */\n#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)\n#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)   /*!< 0x001F0000 */\n#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */\n#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)\n#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)     /*!< 0x0000F000 */\n#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */\n#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)\n#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)     /*!< 0x000000FF */\n#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */\n\n/****************  Bit definition for DFSDM_CHWDATR register *******************/\n#define DFSDM_CHWDATR_WDATA_Pos         (0U)\n#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)   /*!< 0x0000FFFF */\n#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */\n\n/****************  Bit definition for DFSDM_CHDATINR register *****************/\n#define DFSDM_CHDATINR_INDAT0_Pos       (0U)\n#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */\n#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */\n#define DFSDM_CHDATINR_INDAT1_Pos       (16U)\n#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */\n#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */\n\n/************************   DFSDM module registers  ****************************/\n\n/*****************  Bit definition for DFSDM_FLTCR1 register *******************/\n#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)\n#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)      /*!< 0x40000000 */\n#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */\n#define DFSDM_FLTCR1_FAST_Pos           (29U)\n#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)        /*!< 0x20000000 */\n#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */\n#define DFSDM_FLTCR1_RCH_Pos            (24U)\n#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)         /*!< 0x07000000 */\n#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */\n#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)\n#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)      /*!< 0x00200000 */\n#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */\n#define DFSDM_FLTCR1_RSYNC_Pos          (19U)\n#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)       /*!< 0x00080000 */\n#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */\n#define DFSDM_FLTCR1_RCONT_Pos          (18U)\n#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)       /*!< 0x00040000 */\n#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */\n#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)\n#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)    /*!< 0x00020000 */\n#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */\n#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)\n#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00006000 */\n#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */\n#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */\n#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */\n#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)\n#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x7UL << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000700 */\n#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */\n#define DFSDM_FLTCR1_JEXTSEL_2          (0x4UL << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000400 */\n#define DFSDM_FLTCR1_JEXTSEL_1          (0x2UL << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000200 */\n#define DFSDM_FLTCR1_JEXTSEL_0          (0x1UL << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000100 */\n#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)\n#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)      /*!< 0x00000020 */\n#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */\n#define DFSDM_FLTCR1_JSCAN_Pos          (4U)\n#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)       /*!< 0x00000010 */\n#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */\n#define DFSDM_FLTCR1_JSYNC_Pos          (3U)\n#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)       /*!< 0x00000008 */\n#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */\n#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)\n#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)    /*!< 0x00000002 */\n#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */\n#define DFSDM_FLTCR1_DFEN_Pos           (0U)\n#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)        /*!< 0x00000001 */\n#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */\n\n/*****************  Bit definition for DFSDM_FLTCR2 register *******************/\n#define DFSDM_FLTCR2_AWDCH_Pos          (16U)\n#define DFSDM_FLTCR2_AWDCH_Msk          (0xFUL << DFSDM_FLTCR2_AWDCH_Pos)       /*!< 0x000F0000 */\n#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */\n#define DFSDM_FLTCR2_EXCH_Pos           (8U)\n#define DFSDM_FLTCR2_EXCH_Msk           (0xFUL << DFSDM_FLTCR2_EXCH_Pos)        /*!< 0x00000F00 */\n#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */\n#define DFSDM_FLTCR2_CKABIE_Pos         (6U)\n#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)      /*!< 0x00000040 */\n#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */\n#define DFSDM_FLTCR2_SCDIE_Pos          (5U)\n#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)       /*!< 0x00000020 */\n#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */\n#define DFSDM_FLTCR2_AWDIE_Pos          (4U)\n#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)       /*!< 0x00000010 */\n#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */\n#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)\n#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)      /*!< 0x00000008 */\n#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */\n#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)\n#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)      /*!< 0x00000004 */\n#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */\n#define DFSDM_FLTCR2_REOCIE_Pos         (1U)\n#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)      /*!< 0x00000002 */\n#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */\n#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)\n#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)      /*!< 0x00000001 */\n#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */\n\n/*****************  Bit definition for DFSDM_FLTISR register *******************/\n#define DFSDM_FLTISR_SCDF_Pos           (24U)\n#define DFSDM_FLTISR_SCDF_Msk           (0xFUL << DFSDM_FLTISR_SCDF_Pos)        /*!< 0x0F000000 */\n#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */\n#define DFSDM_FLTISR_CKABF_Pos          (16U)\n#define DFSDM_FLTISR_CKABF_Msk          (0xFUL << DFSDM_FLTISR_CKABF_Pos)       /*!< 0x000F0000 */\n#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */\n#define DFSDM_FLTISR_RCIP_Pos           (14U)\n#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)        /*!< 0x00004000 */\n#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */\n#define DFSDM_FLTISR_JCIP_Pos           (13U)\n#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)        /*!< 0x00002000 */\n#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */\n#define DFSDM_FLTISR_AWDF_Pos           (4U)\n#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)        /*!< 0x00000010 */\n#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */\n#define DFSDM_FLTISR_ROVRF_Pos          (3U)\n#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)       /*!< 0x00000008 */\n#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */\n#define DFSDM_FLTISR_JOVRF_Pos          (2U)\n#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)       /*!< 0x00000004 */\n#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */\n#define DFSDM_FLTISR_REOCF_Pos          (1U)\n#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)       /*!< 0x00000002 */\n#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */\n#define DFSDM_FLTISR_JEOCF_Pos          (0U)\n#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)       /*!< 0x00000001 */\n#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */\n\n/*****************  Bit definition for DFSDM_FLTICR register *******************/\n#define DFSDM_FLTICR_CLRSCDF_Pos       (24U)\n#define DFSDM_FLTICR_CLRSCDF_Msk       (0xFUL << DFSDM_FLTICR_CLRSCDF_Pos)      /*!< 0x0F000000 */\n#define DFSDM_FLTICR_CLRSCDF           DFSDM_FLTICR_CLRSCDF_Msk                /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */\n#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)\n#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFUL << DFSDM_FLTICR_CLRCKABF_Pos)    /*!< 0x000F0000 */\n#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */\n#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)\n#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)    /*!< 0x00000008 */\n#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */\n#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)\n#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)    /*!< 0x00000004 */\n#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */\n\n/****************  Bit definition for DFSDM_FLTJCHGR register ******************/\n#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)\n#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFUL << DFSDM_FLTJCHGR_JCHG_Pos)      /*!< 0x0000000F */\n#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */\n/*****************  Bit definition for DFSDM_FLTFCR register *******************/\n#define DFSDM_FLTFCR_FORD_Pos           (29U)\n#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0xE0000000 */\n#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */\n#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */\n#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */\n#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */\n#define DFSDM_FLTFCR_FOSR_Pos           (16U)\n#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)      /*!< 0x03FF0000 */\n#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */\n#define DFSDM_FLTFCR_IOSR_Pos           (0U)\n#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)       /*!< 0x000000FF */\n#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */\n\n/***************  Bit definition for DFSDM_FLTJDATAR register *****************/\n#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)\n#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */\n#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)\n#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos)  /*!< 0x00000007 */\n#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */\n\n/***************  Bit definition for DFSDM_FLTRDATAR register *****************/\n#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)\n#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */\n#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)\n#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)    /*!< 0x00000010 */\n#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */\n#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)\n#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos)  /*!< 0x00000007 */\n#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */\n\n/***************  Bit definition for DFSDM_FLTAWHTR register ******************/\n#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)\n#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */\n#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)\n#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)     /*!< 0x0000000F */\n#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */\n\n/***************  Bit definition for DFSDM_FLTAWLTR register ******************/\n#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)\n#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWLT[23:0] Analog watchdog low threshold */\n#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)\n#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)     /*!< 0x0000000F */\n#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */\n\n/***************  Bit definition for DFSDM_FLTAWSR register *******************/\n#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)\n#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFUL << DFSDM_FLTAWSR_AWHTF_Pos)      /*!< 0x00000F00 */\n#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */\n#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)\n#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFUL << DFSDM_FLTAWSR_AWLTF_Pos)      /*!< 0x0000000F */\n#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */\n\n/***************  Bit definition for DFSDM_FLTAWCFR register ******************/\n#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)\n#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos)  /*!< 0x00000F00 */\n#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */\n#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)\n#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos)  /*!< 0x0000000F */\n#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */\n\n/***************  Bit definition for DFSDM_FLTEXMAX register ******************/\n#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)\n#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */\n#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)\n#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)   /*!< 0x00000007 */\n#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */\n\n/***************  Bit definition for DFSDM_FLTEXMIN register ******************/\n#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)\n#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */\n#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)\n#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)   /*!< 0x00000007 */\n#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */\n\n/***************  Bit definition for DFSDM_FLTCNVTIMR register ****************/\n#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)\n#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */\n#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */\n\n/* Legacy Defines */\n#define DFSDM_FLTICR_CLRSCSDF_Pos        DFSDM_FLTICR_CLRSCDF_Pos\n#define DFSDM_FLTICR_CLRSCSDF_Msk        DFSDM_FLTICR_CLRSCDF_Msk\n#define DFSDM_FLTICR_CLRSCSDF            DFSDM_FLTICR_CLRSCDF\n\n/******************************************************************************/\n/*                                                                            */\n/*                             DMA Controller                                 */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DMA_SxCR register  *****************/\n#define DMA_SxCR_CHSEL_Pos       (25U)\n#define DMA_SxCR_CHSEL_Msk       (0x7UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */\n#define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk\n#define DMA_SxCR_CHSEL_0         0x02000000U\n#define DMA_SxCR_CHSEL_1         0x04000000U\n#define DMA_SxCR_CHSEL_2         0x08000000U\n#define DMA_SxCR_MBURST_Pos      (23U)\n#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */\n#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk\n#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */\n#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */\n#define DMA_SxCR_PBURST_Pos      (21U)\n#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */\n#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk\n#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */\n#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */\n#define DMA_SxCR_CT_Pos          (19U)\n#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */\n#define DMA_SxCR_CT              DMA_SxCR_CT_Msk\n#define DMA_SxCR_DBM_Pos         (18U)\n#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */\n#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk\n#define DMA_SxCR_PL_Pos          (16U)\n#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */\n#define DMA_SxCR_PL              DMA_SxCR_PL_Msk\n#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */\n#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */\n#define DMA_SxCR_PINCOS_Pos      (15U)\n#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */\n#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk\n#define DMA_SxCR_MSIZE_Pos       (13U)\n#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */\n#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk\n#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */\n#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */\n#define DMA_SxCR_PSIZE_Pos       (11U)\n#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */\n#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk\n#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */\n#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */\n#define DMA_SxCR_MINC_Pos        (10U)\n#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */\n#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk\n#define DMA_SxCR_PINC_Pos        (9U)\n#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */\n#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk\n#define DMA_SxCR_CIRC_Pos        (8U)\n#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */\n#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk\n#define DMA_SxCR_DIR_Pos         (6U)\n#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */\n#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk\n#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */\n#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */\n#define DMA_SxCR_PFCTRL_Pos      (5U)\n#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */\n#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk\n#define DMA_SxCR_TCIE_Pos        (4U)\n#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */\n#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk\n#define DMA_SxCR_HTIE_Pos        (3U)\n#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */\n#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk\n#define DMA_SxCR_TEIE_Pos        (2U)\n#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */\n#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk\n#define DMA_SxCR_DMEIE_Pos       (1U)\n#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */\n#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk\n#define DMA_SxCR_EN_Pos          (0U)\n#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */\n#define DMA_SxCR_EN              DMA_SxCR_EN_Msk\n\n/* Legacy defines */\n#define DMA_SxCR_ACK_Pos         (20U)\n#define DMA_SxCR_ACK_Msk         (0x1UL << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */\n#define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk\n\n/********************  Bits definition for DMA_SxCNDTR register  **************/\n#define DMA_SxNDT_Pos            (0U)\n#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */\n#define DMA_SxNDT                DMA_SxNDT_Msk\n#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */\n#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */\n#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */\n#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */\n#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */\n#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */\n#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */\n#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */\n#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */\n#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */\n#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */\n#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */\n#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */\n#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */\n#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */\n#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */\n\n/********************  Bits definition for DMA_SxFCR register  ****************/\n#define DMA_SxFCR_FEIE_Pos       (7U)\n#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */\n#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk\n#define DMA_SxFCR_FS_Pos         (3U)\n#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */\n#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk\n#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */\n#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */\n#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */\n#define DMA_SxFCR_DMDIS_Pos      (2U)\n#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */\n#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk\n#define DMA_SxFCR_FTH_Pos        (0U)\n#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */\n#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk\n#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */\n#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */\n\n/********************  Bits definition for DMA_LISR register  *****************/\n#define DMA_LISR_TCIF3_Pos       (27U)\n#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */\n#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk\n#define DMA_LISR_HTIF3_Pos       (26U)\n#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */\n#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk\n#define DMA_LISR_TEIF3_Pos       (25U)\n#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */\n#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk\n#define DMA_LISR_DMEIF3_Pos      (24U)\n#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */\n#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk\n#define DMA_LISR_FEIF3_Pos       (22U)\n#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */\n#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk\n#define DMA_LISR_TCIF2_Pos       (21U)\n#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */\n#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk\n#define DMA_LISR_HTIF2_Pos       (20U)\n#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */\n#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk\n#define DMA_LISR_TEIF2_Pos       (19U)\n#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */\n#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk\n#define DMA_LISR_DMEIF2_Pos      (18U)\n#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */\n#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk\n#define DMA_LISR_FEIF2_Pos       (16U)\n#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */\n#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk\n#define DMA_LISR_TCIF1_Pos       (11U)\n#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */\n#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk\n#define DMA_LISR_HTIF1_Pos       (10U)\n#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */\n#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk\n#define DMA_LISR_TEIF1_Pos       (9U)\n#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */\n#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk\n#define DMA_LISR_DMEIF1_Pos      (8U)\n#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */\n#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk\n#define DMA_LISR_FEIF1_Pos       (6U)\n#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */\n#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk\n#define DMA_LISR_TCIF0_Pos       (5U)\n#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */\n#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk\n#define DMA_LISR_HTIF0_Pos       (4U)\n#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */\n#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk\n#define DMA_LISR_TEIF0_Pos       (3U)\n#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */\n#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk\n#define DMA_LISR_DMEIF0_Pos      (2U)\n#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */\n#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk\n#define DMA_LISR_FEIF0_Pos       (0U)\n#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */\n#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk\n\n/********************  Bits definition for DMA_HISR register  *****************/\n#define DMA_HISR_TCIF7_Pos       (27U)\n#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */\n#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk\n#define DMA_HISR_HTIF7_Pos       (26U)\n#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */\n#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk\n#define DMA_HISR_TEIF7_Pos       (25U)\n#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */\n#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk\n#define DMA_HISR_DMEIF7_Pos      (24U)\n#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */\n#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk\n#define DMA_HISR_FEIF7_Pos       (22U)\n#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */\n#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk\n#define DMA_HISR_TCIF6_Pos       (21U)\n#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */\n#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk\n#define DMA_HISR_HTIF6_Pos       (20U)\n#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */\n#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk\n#define DMA_HISR_TEIF6_Pos       (19U)\n#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */\n#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk\n#define DMA_HISR_DMEIF6_Pos      (18U)\n#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */\n#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk\n#define DMA_HISR_FEIF6_Pos       (16U)\n#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */\n#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk\n#define DMA_HISR_TCIF5_Pos       (11U)\n#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */\n#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk\n#define DMA_HISR_HTIF5_Pos       (10U)\n#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */\n#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk\n#define DMA_HISR_TEIF5_Pos       (9U)\n#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */\n#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk\n#define DMA_HISR_DMEIF5_Pos      (8U)\n#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */\n#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk\n#define DMA_HISR_FEIF5_Pos       (6U)\n#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */\n#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk\n#define DMA_HISR_TCIF4_Pos       (5U)\n#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */\n#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk\n#define DMA_HISR_HTIF4_Pos       (4U)\n#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */\n#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk\n#define DMA_HISR_TEIF4_Pos       (3U)\n#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */\n#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk\n#define DMA_HISR_DMEIF4_Pos      (2U)\n#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */\n#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk\n#define DMA_HISR_FEIF4_Pos       (0U)\n#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */\n#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk\n\n/********************  Bits definition for DMA_LIFCR register  ****************/\n#define DMA_LIFCR_CTCIF3_Pos     (27U)\n#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */\n#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk\n#define DMA_LIFCR_CHTIF3_Pos     (26U)\n#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */\n#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk\n#define DMA_LIFCR_CTEIF3_Pos     (25U)\n#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */\n#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk\n#define DMA_LIFCR_CDMEIF3_Pos    (24U)\n#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */\n#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk\n#define DMA_LIFCR_CFEIF3_Pos     (22U)\n#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */\n#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk\n#define DMA_LIFCR_CTCIF2_Pos     (21U)\n#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */\n#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk\n#define DMA_LIFCR_CHTIF2_Pos     (20U)\n#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */\n#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk\n#define DMA_LIFCR_CTEIF2_Pos     (19U)\n#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */\n#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk\n#define DMA_LIFCR_CDMEIF2_Pos    (18U)\n#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */\n#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk\n#define DMA_LIFCR_CFEIF2_Pos     (16U)\n#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */\n#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk\n#define DMA_LIFCR_CTCIF1_Pos     (11U)\n#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */\n#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk\n#define DMA_LIFCR_CHTIF1_Pos     (10U)\n#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */\n#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk\n#define DMA_LIFCR_CTEIF1_Pos     (9U)\n#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */\n#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk\n#define DMA_LIFCR_CDMEIF1_Pos    (8U)\n#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */\n#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk\n#define DMA_LIFCR_CFEIF1_Pos     (6U)\n#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */\n#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk\n#define DMA_LIFCR_CTCIF0_Pos     (5U)\n#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */\n#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk\n#define DMA_LIFCR_CHTIF0_Pos     (4U)\n#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */\n#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk\n#define DMA_LIFCR_CTEIF0_Pos     (3U)\n#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */\n#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk\n#define DMA_LIFCR_CDMEIF0_Pos    (2U)\n#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */\n#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk\n#define DMA_LIFCR_CFEIF0_Pos     (0U)\n#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */\n#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk\n\n/********************  Bits definition for DMA_HIFCR  register  ****************/\n#define DMA_HIFCR_CTCIF7_Pos     (27U)\n#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */\n#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk\n#define DMA_HIFCR_CHTIF7_Pos     (26U)\n#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */\n#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk\n#define DMA_HIFCR_CTEIF7_Pos     (25U)\n#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */\n#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk\n#define DMA_HIFCR_CDMEIF7_Pos    (24U)\n#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */\n#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk\n#define DMA_HIFCR_CFEIF7_Pos     (22U)\n#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */\n#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk\n#define DMA_HIFCR_CTCIF6_Pos     (21U)\n#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */\n#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk\n#define DMA_HIFCR_CHTIF6_Pos     (20U)\n#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */\n#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk\n#define DMA_HIFCR_CTEIF6_Pos     (19U)\n#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */\n#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk\n#define DMA_HIFCR_CDMEIF6_Pos    (18U)\n#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */\n#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk\n#define DMA_HIFCR_CFEIF6_Pos     (16U)\n#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */\n#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk\n#define DMA_HIFCR_CTCIF5_Pos     (11U)\n#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */\n#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk\n#define DMA_HIFCR_CHTIF5_Pos     (10U)\n#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */\n#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk\n#define DMA_HIFCR_CTEIF5_Pos     (9U)\n#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */\n#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk\n#define DMA_HIFCR_CDMEIF5_Pos    (8U)\n#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */\n#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk\n#define DMA_HIFCR_CFEIF5_Pos     (6U)\n#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */\n#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk\n#define DMA_HIFCR_CTCIF4_Pos     (5U)\n#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */\n#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk\n#define DMA_HIFCR_CHTIF4_Pos     (4U)\n#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */\n#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk\n#define DMA_HIFCR_CTEIF4_Pos     (3U)\n#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */\n#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk\n#define DMA_HIFCR_CDMEIF4_Pos    (2U)\n#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */\n#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk\n#define DMA_HIFCR_CFEIF4_Pos     (0U)\n#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */\n#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk\n\n/******************  Bit definition for DMA_SxPAR register  ********************/\n#define DMA_SxPAR_PA_Pos         (0U)\n#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */\n#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */\n\n/******************  Bit definition for DMA_SxM0AR register  ********************/\n#define DMA_SxM0AR_M0A_Pos       (0U)\n#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */\n\n/******************  Bit definition for DMA_SxM1AR register  ********************/\n#define DMA_SxM1AR_M1A_Pos       (0U)\n#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                    External Interrupt/Event Controller                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for EXTI_IMR register  *******************/\n#define EXTI_IMR_MR0_Pos          (0U)\n#define EXTI_IMR_MR0_Msk          (0x1UL << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */\n#define EXTI_IMR_MR1_Pos          (1U)\n#define EXTI_IMR_MR1_Msk          (0x1UL << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */\n#define EXTI_IMR_MR2_Pos          (2U)\n#define EXTI_IMR_MR2_Msk          (0x1UL << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */\n#define EXTI_IMR_MR3_Pos          (3U)\n#define EXTI_IMR_MR3_Msk          (0x1UL << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */\n#define EXTI_IMR_MR4_Pos          (4U)\n#define EXTI_IMR_MR4_Msk          (0x1UL << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */\n#define EXTI_IMR_MR5_Pos          (5U)\n#define EXTI_IMR_MR5_Msk          (0x1UL << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */\n#define EXTI_IMR_MR6_Pos          (6U)\n#define EXTI_IMR_MR6_Msk          (0x1UL << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */\n#define EXTI_IMR_MR7_Pos          (7U)\n#define EXTI_IMR_MR7_Msk          (0x1UL << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */\n#define EXTI_IMR_MR8_Pos          (8U)\n#define EXTI_IMR_MR8_Msk          (0x1UL << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */\n#define EXTI_IMR_MR9_Pos          (9U)\n#define EXTI_IMR_MR9_Msk          (0x1UL << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */\n#define EXTI_IMR_MR10_Pos         (10U)\n#define EXTI_IMR_MR10_Msk         (0x1UL << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */\n#define EXTI_IMR_MR11_Pos         (11U)\n#define EXTI_IMR_MR11_Msk         (0x1UL << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */\n#define EXTI_IMR_MR12_Pos         (12U)\n#define EXTI_IMR_MR12_Msk         (0x1UL << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */\n#define EXTI_IMR_MR13_Pos         (13U)\n#define EXTI_IMR_MR13_Msk         (0x1UL << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */\n#define EXTI_IMR_MR14_Pos         (14U)\n#define EXTI_IMR_MR14_Msk         (0x1UL << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */\n#define EXTI_IMR_MR15_Pos         (15U)\n#define EXTI_IMR_MR15_Msk         (0x1UL << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */\n#define EXTI_IMR_MR16_Pos         (16U)\n#define EXTI_IMR_MR16_Msk         (0x1UL << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */\n#define EXTI_IMR_MR17_Pos         (17U)\n#define EXTI_IMR_MR17_Msk         (0x1UL << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */\n#define EXTI_IMR_MR18_Pos         (18U)\n#define EXTI_IMR_MR18_Msk         (0x1UL << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */\n#define EXTI_IMR_MR19_Pos         (19U)\n#define EXTI_IMR_MR19_Msk         (0x1UL << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */\n#define EXTI_IMR_MR20_Pos         (20U)\n#define EXTI_IMR_MR20_Msk         (0x1UL << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */\n#define EXTI_IMR_MR21_Pos         (21U)\n#define EXTI_IMR_MR21_Msk         (0x1UL << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */\n#define EXTI_IMR_MR22_Pos         (22U)\n#define EXTI_IMR_MR22_Msk         (0x1UL << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */\n\n/* Reference Defines */\n#define  EXTI_IMR_IM0                        EXTI_IMR_MR0\n#define  EXTI_IMR_IM1                        EXTI_IMR_MR1\n#define  EXTI_IMR_IM2                        EXTI_IMR_MR2\n#define  EXTI_IMR_IM3                        EXTI_IMR_MR3\n#define  EXTI_IMR_IM4                        EXTI_IMR_MR4\n#define  EXTI_IMR_IM5                        EXTI_IMR_MR5\n#define  EXTI_IMR_IM6                        EXTI_IMR_MR6\n#define  EXTI_IMR_IM7                        EXTI_IMR_MR7\n#define  EXTI_IMR_IM8                        EXTI_IMR_MR8\n#define  EXTI_IMR_IM9                        EXTI_IMR_MR9\n#define  EXTI_IMR_IM10                       EXTI_IMR_MR10\n#define  EXTI_IMR_IM11                       EXTI_IMR_MR11\n#define  EXTI_IMR_IM12                       EXTI_IMR_MR12\n#define  EXTI_IMR_IM13                       EXTI_IMR_MR13\n#define  EXTI_IMR_IM14                       EXTI_IMR_MR14\n#define  EXTI_IMR_IM15                       EXTI_IMR_MR15\n#define  EXTI_IMR_IM16                       EXTI_IMR_MR16\n#define  EXTI_IMR_IM17                       EXTI_IMR_MR17\n#define  EXTI_IMR_IM18                       EXTI_IMR_MR18\n#define  EXTI_IMR_IM19                       EXTI_IMR_MR19\n#define  EXTI_IMR_IM20                       EXTI_IMR_MR20\n#define  EXTI_IMR_IM21                       EXTI_IMR_MR21\n#define  EXTI_IMR_IM22                       EXTI_IMR_MR22\n#define EXTI_IMR_IM_Pos           (0U)\n#define EXTI_IMR_IM_Msk           (0x7FFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x007FFFFF */\n#define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */\n\n/*******************  Bit definition for EXTI_EMR register  *******************/\n#define EXTI_EMR_MR0_Pos          (0U)\n#define EXTI_EMR_MR0_Msk          (0x1UL << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */\n#define EXTI_EMR_MR1_Pos          (1U)\n#define EXTI_EMR_MR1_Msk          (0x1UL << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */\n#define EXTI_EMR_MR2_Pos          (2U)\n#define EXTI_EMR_MR2_Msk          (0x1UL << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */\n#define EXTI_EMR_MR3_Pos          (3U)\n#define EXTI_EMR_MR3_Msk          (0x1UL << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */\n#define EXTI_EMR_MR4_Pos          (4U)\n#define EXTI_EMR_MR4_Msk          (0x1UL << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */\n#define EXTI_EMR_MR5_Pos          (5U)\n#define EXTI_EMR_MR5_Msk          (0x1UL << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */\n#define EXTI_EMR_MR6_Pos          (6U)\n#define EXTI_EMR_MR6_Msk          (0x1UL << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */\n#define EXTI_EMR_MR7_Pos          (7U)\n#define EXTI_EMR_MR7_Msk          (0x1UL << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */\n#define EXTI_EMR_MR8_Pos          (8U)\n#define EXTI_EMR_MR8_Msk          (0x1UL << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */\n#define EXTI_EMR_MR9_Pos          (9U)\n#define EXTI_EMR_MR9_Msk          (0x1UL << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */\n#define EXTI_EMR_MR10_Pos         (10U)\n#define EXTI_EMR_MR10_Msk         (0x1UL << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */\n#define EXTI_EMR_MR11_Pos         (11U)\n#define EXTI_EMR_MR11_Msk         (0x1UL << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */\n#define EXTI_EMR_MR12_Pos         (12U)\n#define EXTI_EMR_MR12_Msk         (0x1UL << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */\n#define EXTI_EMR_MR13_Pos         (13U)\n#define EXTI_EMR_MR13_Msk         (0x1UL << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */\n#define EXTI_EMR_MR14_Pos         (14U)\n#define EXTI_EMR_MR14_Msk         (0x1UL << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */\n#define EXTI_EMR_MR15_Pos         (15U)\n#define EXTI_EMR_MR15_Msk         (0x1UL << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */\n#define EXTI_EMR_MR16_Pos         (16U)\n#define EXTI_EMR_MR16_Msk         (0x1UL << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */\n#define EXTI_EMR_MR17_Pos         (17U)\n#define EXTI_EMR_MR17_Msk         (0x1UL << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */\n#define EXTI_EMR_MR18_Pos         (18U)\n#define EXTI_EMR_MR18_Msk         (0x1UL << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */\n#define EXTI_EMR_MR19_Pos         (19U)\n#define EXTI_EMR_MR19_Msk         (0x1UL << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */\n#define EXTI_EMR_MR20_Pos         (20U)\n#define EXTI_EMR_MR20_Msk         (0x1UL << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */\n#define EXTI_EMR_MR21_Pos         (21U)\n#define EXTI_EMR_MR21_Msk         (0x1UL << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */\n#define EXTI_EMR_MR22_Pos         (22U)\n#define EXTI_EMR_MR22_Msk         (0x1UL << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */\n\n/* Reference Defines */\n#define  EXTI_EMR_EM0                        EXTI_EMR_MR0\n#define  EXTI_EMR_EM1                        EXTI_EMR_MR1\n#define  EXTI_EMR_EM2                        EXTI_EMR_MR2\n#define  EXTI_EMR_EM3                        EXTI_EMR_MR3\n#define  EXTI_EMR_EM4                        EXTI_EMR_MR4\n#define  EXTI_EMR_EM5                        EXTI_EMR_MR5\n#define  EXTI_EMR_EM6                        EXTI_EMR_MR6\n#define  EXTI_EMR_EM7                        EXTI_EMR_MR7\n#define  EXTI_EMR_EM8                        EXTI_EMR_MR8\n#define  EXTI_EMR_EM9                        EXTI_EMR_MR9\n#define  EXTI_EMR_EM10                       EXTI_EMR_MR10\n#define  EXTI_EMR_EM11                       EXTI_EMR_MR11\n#define  EXTI_EMR_EM12                       EXTI_EMR_MR12\n#define  EXTI_EMR_EM13                       EXTI_EMR_MR13\n#define  EXTI_EMR_EM14                       EXTI_EMR_MR14\n#define  EXTI_EMR_EM15                       EXTI_EMR_MR15\n#define  EXTI_EMR_EM16                       EXTI_EMR_MR16\n#define  EXTI_EMR_EM17                       EXTI_EMR_MR17\n#define  EXTI_EMR_EM18                       EXTI_EMR_MR18\n#define  EXTI_EMR_EM19                       EXTI_EMR_MR19\n#define  EXTI_EMR_EM20                       EXTI_EMR_MR20\n#define  EXTI_EMR_EM21                       EXTI_EMR_MR21\n#define  EXTI_EMR_EM22                       EXTI_EMR_MR22\n\n/******************  Bit definition for EXTI_RTSR register  *******************/\n#define EXTI_RTSR_TR0_Pos         (0U)\n#define EXTI_RTSR_TR0_Msk         (0x1UL << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */\n#define EXTI_RTSR_TR1_Pos         (1U)\n#define EXTI_RTSR_TR1_Msk         (0x1UL << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */\n#define EXTI_RTSR_TR2_Pos         (2U)\n#define EXTI_RTSR_TR2_Msk         (0x1UL << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */\n#define EXTI_RTSR_TR3_Pos         (3U)\n#define EXTI_RTSR_TR3_Msk         (0x1UL << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */\n#define EXTI_RTSR_TR4_Pos         (4U)\n#define EXTI_RTSR_TR4_Msk         (0x1UL << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */\n#define EXTI_RTSR_TR5_Pos         (5U)\n#define EXTI_RTSR_TR5_Msk         (0x1UL << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */\n#define EXTI_RTSR_TR6_Pos         (6U)\n#define EXTI_RTSR_TR6_Msk         (0x1UL << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */\n#define EXTI_RTSR_TR7_Pos         (7U)\n#define EXTI_RTSR_TR7_Msk         (0x1UL << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */\n#define EXTI_RTSR_TR8_Pos         (8U)\n#define EXTI_RTSR_TR8_Msk         (0x1UL << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */\n#define EXTI_RTSR_TR9_Pos         (9U)\n#define EXTI_RTSR_TR9_Msk         (0x1UL << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */\n#define EXTI_RTSR_TR10_Pos        (10U)\n#define EXTI_RTSR_TR10_Msk        (0x1UL << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */\n#define EXTI_RTSR_TR11_Pos        (11U)\n#define EXTI_RTSR_TR11_Msk        (0x1UL << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */\n#define EXTI_RTSR_TR12_Pos        (12U)\n#define EXTI_RTSR_TR12_Msk        (0x1UL << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */\n#define EXTI_RTSR_TR13_Pos        (13U)\n#define EXTI_RTSR_TR13_Msk        (0x1UL << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */\n#define EXTI_RTSR_TR14_Pos        (14U)\n#define EXTI_RTSR_TR14_Msk        (0x1UL << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */\n#define EXTI_RTSR_TR15_Pos        (15U)\n#define EXTI_RTSR_TR15_Msk        (0x1UL << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */\n#define EXTI_RTSR_TR16_Pos        (16U)\n#define EXTI_RTSR_TR16_Msk        (0x1UL << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */\n#define EXTI_RTSR_TR17_Pos        (17U)\n#define EXTI_RTSR_TR17_Msk        (0x1UL << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */\n#define EXTI_RTSR_TR18_Pos        (18U)\n#define EXTI_RTSR_TR18_Msk        (0x1UL << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */\n#define EXTI_RTSR_TR19_Pos        (19U)\n#define EXTI_RTSR_TR19_Msk        (0x1UL << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */\n#define EXTI_RTSR_TR20_Pos        (20U)\n#define EXTI_RTSR_TR20_Msk        (0x1UL << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */\n#define EXTI_RTSR_TR21_Pos        (21U)\n#define EXTI_RTSR_TR21_Msk        (0x1UL << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */\n#define EXTI_RTSR_TR22_Pos        (22U)\n#define EXTI_RTSR_TR22_Msk        (0x1UL << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_FTSR register  *******************/\n#define EXTI_FTSR_TR0_Pos         (0U)\n#define EXTI_FTSR_TR0_Msk         (0x1UL << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */\n#define EXTI_FTSR_TR1_Pos         (1U)\n#define EXTI_FTSR_TR1_Msk         (0x1UL << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */\n#define EXTI_FTSR_TR2_Pos         (2U)\n#define EXTI_FTSR_TR2_Msk         (0x1UL << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */\n#define EXTI_FTSR_TR3_Pos         (3U)\n#define EXTI_FTSR_TR3_Msk         (0x1UL << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */\n#define EXTI_FTSR_TR4_Pos         (4U)\n#define EXTI_FTSR_TR4_Msk         (0x1UL << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */\n#define EXTI_FTSR_TR5_Pos         (5U)\n#define EXTI_FTSR_TR5_Msk         (0x1UL << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */\n#define EXTI_FTSR_TR6_Pos         (6U)\n#define EXTI_FTSR_TR6_Msk         (0x1UL << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */\n#define EXTI_FTSR_TR7_Pos         (7U)\n#define EXTI_FTSR_TR7_Msk         (0x1UL << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */\n#define EXTI_FTSR_TR8_Pos         (8U)\n#define EXTI_FTSR_TR8_Msk         (0x1UL << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */\n#define EXTI_FTSR_TR9_Pos         (9U)\n#define EXTI_FTSR_TR9_Msk         (0x1UL << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */\n#define EXTI_FTSR_TR10_Pos        (10U)\n#define EXTI_FTSR_TR10_Msk        (0x1UL << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */\n#define EXTI_FTSR_TR11_Pos        (11U)\n#define EXTI_FTSR_TR11_Msk        (0x1UL << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */\n#define EXTI_FTSR_TR12_Pos        (12U)\n#define EXTI_FTSR_TR12_Msk        (0x1UL << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */\n#define EXTI_FTSR_TR13_Pos        (13U)\n#define EXTI_FTSR_TR13_Msk        (0x1UL << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */\n#define EXTI_FTSR_TR14_Pos        (14U)\n#define EXTI_FTSR_TR14_Msk        (0x1UL << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */\n#define EXTI_FTSR_TR15_Pos        (15U)\n#define EXTI_FTSR_TR15_Msk        (0x1UL << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */\n#define EXTI_FTSR_TR16_Pos        (16U)\n#define EXTI_FTSR_TR16_Msk        (0x1UL << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */\n#define EXTI_FTSR_TR17_Pos        (17U)\n#define EXTI_FTSR_TR17_Msk        (0x1UL << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */\n#define EXTI_FTSR_TR18_Pos        (18U)\n#define EXTI_FTSR_TR18_Msk        (0x1UL << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */\n#define EXTI_FTSR_TR19_Pos        (19U)\n#define EXTI_FTSR_TR19_Msk        (0x1UL << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */\n#define EXTI_FTSR_TR20_Pos        (20U)\n#define EXTI_FTSR_TR20_Msk        (0x1UL << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */\n#define EXTI_FTSR_TR21_Pos        (21U)\n#define EXTI_FTSR_TR21_Msk        (0x1UL << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */\n#define EXTI_FTSR_TR22_Pos        (22U)\n#define EXTI_FTSR_TR22_Msk        (0x1UL << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_SWIER register  ******************/\n#define EXTI_SWIER_SWIER0_Pos     (0U)\n#define EXTI_SWIER_SWIER0_Msk     (0x1UL << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */\n#define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */\n#define EXTI_SWIER_SWIER1_Pos     (1U)\n#define EXTI_SWIER_SWIER1_Msk     (0x1UL << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */\n#define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */\n#define EXTI_SWIER_SWIER2_Pos     (2U)\n#define EXTI_SWIER_SWIER2_Msk     (0x1UL << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */\n#define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */\n#define EXTI_SWIER_SWIER3_Pos     (3U)\n#define EXTI_SWIER_SWIER3_Msk     (0x1UL << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */\n#define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */\n#define EXTI_SWIER_SWIER4_Pos     (4U)\n#define EXTI_SWIER_SWIER4_Msk     (0x1UL << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */\n#define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */\n#define EXTI_SWIER_SWIER5_Pos     (5U)\n#define EXTI_SWIER_SWIER5_Msk     (0x1UL << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */\n#define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */\n#define EXTI_SWIER_SWIER6_Pos     (6U)\n#define EXTI_SWIER_SWIER6_Msk     (0x1UL << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */\n#define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */\n#define EXTI_SWIER_SWIER7_Pos     (7U)\n#define EXTI_SWIER_SWIER7_Msk     (0x1UL << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */\n#define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */\n#define EXTI_SWIER_SWIER8_Pos     (8U)\n#define EXTI_SWIER_SWIER8_Msk     (0x1UL << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */\n#define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */\n#define EXTI_SWIER_SWIER9_Pos     (9U)\n#define EXTI_SWIER_SWIER9_Msk     (0x1UL << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */\n#define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */\n#define EXTI_SWIER_SWIER10_Pos    (10U)\n#define EXTI_SWIER_SWIER10_Msk    (0x1UL << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */\n#define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */\n#define EXTI_SWIER_SWIER11_Pos    (11U)\n#define EXTI_SWIER_SWIER11_Msk    (0x1UL << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */\n#define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */\n#define EXTI_SWIER_SWIER12_Pos    (12U)\n#define EXTI_SWIER_SWIER12_Msk    (0x1UL << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */\n#define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */\n#define EXTI_SWIER_SWIER13_Pos    (13U)\n#define EXTI_SWIER_SWIER13_Msk    (0x1UL << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */\n#define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */\n#define EXTI_SWIER_SWIER14_Pos    (14U)\n#define EXTI_SWIER_SWIER14_Msk    (0x1UL << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */\n#define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */\n#define EXTI_SWIER_SWIER15_Pos    (15U)\n#define EXTI_SWIER_SWIER15_Msk    (0x1UL << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */\n#define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */\n#define EXTI_SWIER_SWIER16_Pos    (16U)\n#define EXTI_SWIER_SWIER16_Msk    (0x1UL << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */\n#define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */\n#define EXTI_SWIER_SWIER17_Pos    (17U)\n#define EXTI_SWIER_SWIER17_Msk    (0x1UL << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */\n#define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */\n#define EXTI_SWIER_SWIER18_Pos    (18U)\n#define EXTI_SWIER_SWIER18_Msk    (0x1UL << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */\n#define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */\n#define EXTI_SWIER_SWIER19_Pos    (19U)\n#define EXTI_SWIER_SWIER19_Msk    (0x1UL << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */\n#define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */\n#define EXTI_SWIER_SWIER20_Pos    (20U)\n#define EXTI_SWIER_SWIER20_Msk    (0x1UL << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */\n#define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */\n#define EXTI_SWIER_SWIER21_Pos    (21U)\n#define EXTI_SWIER_SWIER21_Msk    (0x1UL << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */\n#define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */\n#define EXTI_SWIER_SWIER22_Pos    (22U)\n#define EXTI_SWIER_SWIER22_Msk    (0x1UL << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */\n#define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */\n\n/*******************  Bit definition for EXTI_PR register  ********************/\n#define EXTI_PR_PR0_Pos           (0U)\n#define EXTI_PR_PR0_Msk           (0x1UL << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */\n#define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */\n#define EXTI_PR_PR1_Pos           (1U)\n#define EXTI_PR_PR1_Msk           (0x1UL << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */\n#define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */\n#define EXTI_PR_PR2_Pos           (2U)\n#define EXTI_PR_PR2_Msk           (0x1UL << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */\n#define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */\n#define EXTI_PR_PR3_Pos           (3U)\n#define EXTI_PR_PR3_Msk           (0x1UL << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */\n#define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */\n#define EXTI_PR_PR4_Pos           (4U)\n#define EXTI_PR_PR4_Msk           (0x1UL << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */\n#define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */\n#define EXTI_PR_PR5_Pos           (5U)\n#define EXTI_PR_PR5_Msk           (0x1UL << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */\n#define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */\n#define EXTI_PR_PR6_Pos           (6U)\n#define EXTI_PR_PR6_Msk           (0x1UL << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */\n#define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */\n#define EXTI_PR_PR7_Pos           (7U)\n#define EXTI_PR_PR7_Msk           (0x1UL << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */\n#define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */\n#define EXTI_PR_PR8_Pos           (8U)\n#define EXTI_PR_PR8_Msk           (0x1UL << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */\n#define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */\n#define EXTI_PR_PR9_Pos           (9U)\n#define EXTI_PR_PR9_Msk           (0x1UL << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */\n#define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */\n#define EXTI_PR_PR10_Pos          (10U)\n#define EXTI_PR_PR10_Msk          (0x1UL << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */\n#define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */\n#define EXTI_PR_PR11_Pos          (11U)\n#define EXTI_PR_PR11_Msk          (0x1UL << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */\n#define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */\n#define EXTI_PR_PR12_Pos          (12U)\n#define EXTI_PR_PR12_Msk          (0x1UL << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */\n#define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */\n#define EXTI_PR_PR13_Pos          (13U)\n#define EXTI_PR_PR13_Msk          (0x1UL << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */\n#define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */\n#define EXTI_PR_PR14_Pos          (14U)\n#define EXTI_PR_PR14_Msk          (0x1UL << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */\n#define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */\n#define EXTI_PR_PR15_Pos          (15U)\n#define EXTI_PR_PR15_Msk          (0x1UL << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */\n#define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */\n#define EXTI_PR_PR16_Pos          (16U)\n#define EXTI_PR_PR16_Msk          (0x1UL << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */\n#define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */\n#define EXTI_PR_PR17_Pos          (17U)\n#define EXTI_PR_PR17_Msk          (0x1UL << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */\n#define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */\n#define EXTI_PR_PR18_Pos          (18U)\n#define EXTI_PR_PR18_Msk          (0x1UL << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */\n#define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */\n#define EXTI_PR_PR19_Pos          (19U)\n#define EXTI_PR_PR19_Msk          (0x1UL << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */\n#define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */\n#define EXTI_PR_PR20_Pos          (20U)\n#define EXTI_PR_PR20_Msk          (0x1UL << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */\n#define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */\n#define EXTI_PR_PR21_Pos          (21U)\n#define EXTI_PR_PR21_Msk          (0x1UL << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */\n#define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */\n#define EXTI_PR_PR22_Pos          (22U)\n#define EXTI_PR_PR22_Msk          (0x1UL << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */\n#define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    FLASH                                   */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bits definition for FLASH_ACR register  *****************/\n#define FLASH_ACR_LATENCY_Pos          (0U)\n#define FLASH_ACR_LATENCY_Msk          (0xFUL << FLASH_ACR_LATENCY_Pos)         /*!< 0x0000000F */\n#define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk\n#define FLASH_ACR_LATENCY_0WS          0x00000000U\n#define FLASH_ACR_LATENCY_1WS          0x00000001U\n#define FLASH_ACR_LATENCY_2WS          0x00000002U\n#define FLASH_ACR_LATENCY_3WS          0x00000003U\n#define FLASH_ACR_LATENCY_4WS          0x00000004U\n#define FLASH_ACR_LATENCY_5WS          0x00000005U\n#define FLASH_ACR_LATENCY_6WS          0x00000006U\n#define FLASH_ACR_LATENCY_7WS          0x00000007U\n\n#define FLASH_ACR_PRFTEN_Pos           (8U)\n#define FLASH_ACR_PRFTEN_Msk           (0x1UL << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */\n#define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk\n#define FLASH_ACR_ICEN_Pos             (9U)\n#define FLASH_ACR_ICEN_Msk             (0x1UL << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */\n#define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk\n#define FLASH_ACR_DCEN_Pos             (10U)\n#define FLASH_ACR_DCEN_Msk             (0x1UL << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */\n#define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk\n#define FLASH_ACR_ICRST_Pos            (11U)\n#define FLASH_ACR_ICRST_Msk            (0x1UL << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */\n#define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk\n#define FLASH_ACR_DCRST_Pos            (12U)\n#define FLASH_ACR_DCRST_Msk            (0x1UL << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */\n#define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk\n#define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)\n#define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */\n#define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk\n#define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)\n#define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */\n#define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk\n\n/*******************  Bits definition for FLASH_SR register  ******************/\n#define FLASH_SR_EOP_Pos               (0U)\n#define FLASH_SR_EOP_Msk               (0x1UL << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */\n#define FLASH_SR_EOP                   FLASH_SR_EOP_Msk\n#define FLASH_SR_SOP_Pos               (1U)\n#define FLASH_SR_SOP_Msk               (0x1UL << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */\n#define FLASH_SR_SOP                   FLASH_SR_SOP_Msk\n#define FLASH_SR_WRPERR_Pos            (4U)\n#define FLASH_SR_WRPERR_Msk            (0x1UL << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */\n#define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk\n#define FLASH_SR_PGAERR_Pos            (5U)\n#define FLASH_SR_PGAERR_Msk            (0x1UL << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */\n#define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk\n#define FLASH_SR_PGPERR_Pos            (6U)\n#define FLASH_SR_PGPERR_Msk            (0x1UL << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */\n#define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk\n#define FLASH_SR_PGSERR_Pos            (7U)\n#define FLASH_SR_PGSERR_Msk            (0x1UL << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */\n#define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk\n#define FLASH_SR_RDERR_Pos            (8U)\n#define FLASH_SR_RDERR_Msk            (0x1UL << FLASH_SR_RDERR_Pos)             /*!< 0x00000100 */\n#define FLASH_SR_RDERR                FLASH_SR_RDERR_Msk\n#define FLASH_SR_BSY_Pos               (16U)\n#define FLASH_SR_BSY_Msk               (0x1UL << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */\n#define FLASH_SR_BSY                   FLASH_SR_BSY_Msk\n\n/*******************  Bits definition for FLASH_CR register  ******************/\n#define FLASH_CR_PG_Pos                (0U)\n#define FLASH_CR_PG_Msk                (0x1UL << FLASH_CR_PG_Pos)               /*!< 0x00000001 */\n#define FLASH_CR_PG                    FLASH_CR_PG_Msk\n#define FLASH_CR_SER_Pos               (1U)\n#define FLASH_CR_SER_Msk               (0x1UL << FLASH_CR_SER_Pos)              /*!< 0x00000002 */\n#define FLASH_CR_SER                   FLASH_CR_SER_Msk\n#define FLASH_CR_MER_Pos               (2U)\n#define FLASH_CR_MER_Msk               (0x1UL << FLASH_CR_MER_Pos)              /*!< 0x00000004 */\n#define FLASH_CR_MER                   FLASH_CR_MER_Msk\n#define FLASH_CR_SNB_Pos               (3U)\n#define FLASH_CR_SNB_Msk               (0x1FUL << FLASH_CR_SNB_Pos)             /*!< 0x000000F8 */\n#define FLASH_CR_SNB                   FLASH_CR_SNB_Msk\n#define FLASH_CR_SNB_0                 (0x01UL << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */\n#define FLASH_CR_SNB_1                 (0x02UL << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */\n#define FLASH_CR_SNB_2                 (0x04UL << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */\n#define FLASH_CR_SNB_3                 (0x08UL << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */\n#define FLASH_CR_SNB_4                 (0x10UL << FLASH_CR_SNB_Pos)             /*!< 0x00000080 */\n#define FLASH_CR_PSIZE_Pos             (8U)\n#define FLASH_CR_PSIZE_Msk             (0x3UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */\n#define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk\n#define FLASH_CR_PSIZE_0               (0x1UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */\n#define FLASH_CR_PSIZE_1               (0x2UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */\n#define FLASH_CR_STRT_Pos              (16U)\n#define FLASH_CR_STRT_Msk              (0x1UL << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */\n#define FLASH_CR_STRT                  FLASH_CR_STRT_Msk\n#define FLASH_CR_EOPIE_Pos             (24U)\n#define FLASH_CR_EOPIE_Msk             (0x1UL << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */\n#define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk\n#define FLASH_CR_LOCK_Pos              (31U)\n#define FLASH_CR_LOCK_Msk              (0x1UL << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */\n#define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk\n\n/*******************  Bits definition for FLASH_OPTCR register  ***************/\n#define FLASH_OPTCR_OPTLOCK_Pos        (0U)\n#define FLASH_OPTCR_OPTLOCK_Msk        (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */\n#define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk\n#define FLASH_OPTCR_OPTSTRT_Pos        (1U)\n#define FLASH_OPTCR_OPTSTRT_Msk        (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */\n#define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk\n\n#define FLASH_OPTCR_BOR_LEV_0          0x00000004U\n#define FLASH_OPTCR_BOR_LEV_1          0x00000008U\n#define FLASH_OPTCR_BOR_LEV_Pos        (2U)\n#define FLASH_OPTCR_BOR_LEV_Msk        (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */\n#define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk\n#define FLASH_OPTCR_WDG_SW_Pos         (5U)\n#define FLASH_OPTCR_WDG_SW_Msk         (0x1UL << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */\n#define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk\n#define FLASH_OPTCR_nRST_STOP_Pos      (6U)\n#define FLASH_OPTCR_nRST_STOP_Msk      (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */\n#define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk\n#define FLASH_OPTCR_nRST_STDBY_Pos     (7U)\n#define FLASH_OPTCR_nRST_STDBY_Msk     (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */\n#define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk\n#define FLASH_OPTCR_RDP_Pos            (8U)\n#define FLASH_OPTCR_RDP_Msk            (0xFFUL << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */\n#define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk\n#define FLASH_OPTCR_RDP_0              (0x01UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */\n#define FLASH_OPTCR_RDP_1              (0x02UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */\n#define FLASH_OPTCR_RDP_2              (0x04UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */\n#define FLASH_OPTCR_RDP_3              (0x08UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */\n#define FLASH_OPTCR_RDP_4              (0x10UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */\n#define FLASH_OPTCR_RDP_5              (0x20UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */\n#define FLASH_OPTCR_RDP_6              (0x40UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */\n#define FLASH_OPTCR_RDP_7              (0x80UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */\n#define FLASH_OPTCR_nWRP_Pos           (16U)\n#define FLASH_OPTCR_nWRP_Msk           (0xFFFUL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x0FFF0000 */\n#define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk\n#define FLASH_OPTCR_nWRP_0             0x00010000U\n#define FLASH_OPTCR_nWRP_1             0x00020000U\n#define FLASH_OPTCR_nWRP_2             0x00040000U\n#define FLASH_OPTCR_nWRP_3             0x00080000U\n#define FLASH_OPTCR_nWRP_4             0x00100000U\n#define FLASH_OPTCR_nWRP_5             0x00200000U\n#define FLASH_OPTCR_nWRP_6             0x00400000U\n#define FLASH_OPTCR_nWRP_7             0x00800000U\n#define FLASH_OPTCR_nWRP_8             0x01000000U\n#define FLASH_OPTCR_nWRP_9             0x02000000U\n#define FLASH_OPTCR_nWRP_10            0x04000000U\n#define FLASH_OPTCR_nWRP_11            0x08000000U\n\n/******************  Bits definition for FLASH_OPTCR1 register  ***************/\n#define FLASH_OPTCR1_nWRP_Pos          (16U)\n#define FLASH_OPTCR1_nWRP_Msk          (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */\n#define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk\n#define FLASH_OPTCR1_nWRP_0            (0x001UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */\n#define FLASH_OPTCR1_nWRP_1            (0x002UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */\n#define FLASH_OPTCR1_nWRP_2            (0x004UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */\n#define FLASH_OPTCR1_nWRP_3            (0x008UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */\n#define FLASH_OPTCR1_nWRP_4            (0x010UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */\n#define FLASH_OPTCR1_nWRP_5            (0x020UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */\n#define FLASH_OPTCR1_nWRP_6            (0x040UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */\n#define FLASH_OPTCR1_nWRP_7            (0x080UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */\n#define FLASH_OPTCR1_nWRP_8            (0x100UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */\n#define FLASH_OPTCR1_nWRP_9            (0x200UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */\n#define FLASH_OPTCR1_nWRP_10           (0x400UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */\n#define FLASH_OPTCR1_nWRP_11           (0x800UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                   Flexible Static Memory Controller                        */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for FSMC_BCR1 register  *******************/\n#define FSMC_BCR1_MBKEN_Pos          (0U)\n#define FSMC_BCR1_MBKEN_Msk          (0x1UL << FSMC_BCR1_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR1_MBKEN              FSMC_BCR1_MBKEN_Msk                       /*!<Memory bank enable bit                 */\n#define FSMC_BCR1_MUXEN_Pos          (1U)\n#define FSMC_BCR1_MUXEN_Msk          (0x1UL << FSMC_BCR1_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR1_MUXEN              FSMC_BCR1_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR1_MTYP_Pos           (2U)\n#define FSMC_BCR1_MTYP_Msk           (0x3UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR1_MTYP               FSMC_BCR1_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR1_MTYP_0             (0x1UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR1_MTYP_1             (0x2UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR1_MWID_Pos           (4U)\n#define FSMC_BCR1_MWID_Msk           (0x3UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR1_MWID               FSMC_BCR1_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR1_MWID_0             (0x1UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR1_MWID_1             (0x2UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR1_FACCEN_Pos         (6U)\n#define FSMC_BCR1_FACCEN_Msk         (0x1UL << FSMC_BCR1_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR1_FACCEN             FSMC_BCR1_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR1_BURSTEN_Pos        (8U)\n#define FSMC_BCR1_BURSTEN_Msk        (0x1UL << FSMC_BCR1_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR1_BURSTEN            FSMC_BCR1_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR1_WAITPOL_Pos        (9U)\n#define FSMC_BCR1_WAITPOL_Msk        (0x1UL << FSMC_BCR1_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR1_WAITPOL            FSMC_BCR1_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR1_WAITCFG_Pos        (11U)\n#define FSMC_BCR1_WAITCFG_Msk        (0x1UL << FSMC_BCR1_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR1_WAITCFG            FSMC_BCR1_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR1_WREN_Pos           (12U)\n#define FSMC_BCR1_WREN_Msk           (0x1UL << FSMC_BCR1_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR1_WREN               FSMC_BCR1_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR1_WAITEN_Pos         (13U)\n#define FSMC_BCR1_WAITEN_Msk         (0x1UL << FSMC_BCR1_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR1_WAITEN             FSMC_BCR1_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR1_EXTMOD_Pos         (14U)\n#define FSMC_BCR1_EXTMOD_Msk         (0x1UL << FSMC_BCR1_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR1_EXTMOD             FSMC_BCR1_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR1_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR1_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR1_ASYNCWAIT          FSMC_BCR1_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR1_CPSIZE_Pos         (16U)\n#define FSMC_BCR1_CPSIZE_Msk         (0x7UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR1_CPSIZE             FSMC_BCR1_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR1_CPSIZE_0           (0x1UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR1_CPSIZE_1           (0x2UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR1_CPSIZE_2           (0x4UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR1_CBURSTRW_Pos       (19U)\n#define FSMC_BCR1_CBURSTRW_Msk       (0x1UL << FSMC_BCR1_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR1_CBURSTRW           FSMC_BCR1_CBURSTRW_Msk                    /*!<Write burst enable                     */\n#define FSMC_BCR1_CCLKEN_Pos         (20U)\n#define FSMC_BCR1_CCLKEN_Msk         (0x1UL << FSMC_BCR1_CCLKEN_Pos)            /*!< 0x00100000 */\n#define FSMC_BCR1_CCLKEN             FSMC_BCR1_CCLKEN_Msk                      /*!<Continous clock enable     */\n#define FSMC_BCR1_WFDIS_Pos          (21U)\n#define FSMC_BCR1_WFDIS_Msk          (0x1UL << FSMC_BCR1_WFDIS_Pos)             /*!< 0x00200000 */\n#define FSMC_BCR1_WFDIS              FSMC_BCR1_WFDIS_Msk                       /*!<Write FIFO Disable         */\n\n/******************  Bit definition for FSMC_BCR2 register  *******************/\n#define FSMC_BCR2_MBKEN_Pos          (0U)\n#define FSMC_BCR2_MBKEN_Msk          (0x1UL << FSMC_BCR2_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR2_MBKEN              FSMC_BCR2_MBKEN_Msk                       /*!<Memory bank enable bit                */\n#define FSMC_BCR2_MUXEN_Pos          (1U)\n#define FSMC_BCR2_MUXEN_Msk          (0x1UL << FSMC_BCR2_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR2_MUXEN              FSMC_BCR2_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR2_MTYP_Pos           (2U)\n#define FSMC_BCR2_MTYP_Msk           (0x3UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR2_MTYP               FSMC_BCR2_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR2_MTYP_0             (0x1UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR2_MTYP_1             (0x2UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR2_MWID_Pos           (4U)\n#define FSMC_BCR2_MWID_Msk           (0x3UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR2_MWID               FSMC_BCR2_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR2_MWID_0             (0x1UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR2_MWID_1             (0x2UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR2_FACCEN_Pos         (6U)\n#define FSMC_BCR2_FACCEN_Msk         (0x1UL << FSMC_BCR2_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR2_FACCEN             FSMC_BCR2_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR2_BURSTEN_Pos        (8U)\n#define FSMC_BCR2_BURSTEN_Msk        (0x1UL << FSMC_BCR2_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR2_BURSTEN            FSMC_BCR2_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR2_WAITPOL_Pos        (9U)\n#define FSMC_BCR2_WAITPOL_Msk        (0x1UL << FSMC_BCR2_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR2_WAITPOL            FSMC_BCR2_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR2_WAITCFG_Pos        (11U)\n#define FSMC_BCR2_WAITCFG_Msk        (0x1UL << FSMC_BCR2_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR2_WAITCFG            FSMC_BCR2_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR2_WREN_Pos           (12U)\n#define FSMC_BCR2_WREN_Msk           (0x1UL << FSMC_BCR2_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR2_WREN               FSMC_BCR2_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR2_WAITEN_Pos         (13U)\n#define FSMC_BCR2_WAITEN_Msk         (0x1UL << FSMC_BCR2_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR2_WAITEN             FSMC_BCR2_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR2_EXTMOD_Pos         (14U)\n#define FSMC_BCR2_EXTMOD_Msk         (0x1UL << FSMC_BCR2_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR2_EXTMOD             FSMC_BCR2_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR2_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR2_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR2_ASYNCWAIT          FSMC_BCR2_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR2_CPSIZE_Pos         (16U)\n#define FSMC_BCR2_CPSIZE_Msk         (0x7UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR2_CPSIZE             FSMC_BCR2_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR2_CPSIZE_0           (0x1UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR2_CPSIZE_1           (0x2UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR2_CPSIZE_2           (0x4UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR2_CBURSTRW_Pos       (19U)\n#define FSMC_BCR2_CBURSTRW_Msk       (0x1UL << FSMC_BCR2_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR2_CBURSTRW           FSMC_BCR2_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BCR3 register  *******************/\n#define FSMC_BCR3_MBKEN_Pos          (0U)\n#define FSMC_BCR3_MBKEN_Msk          (0x1UL << FSMC_BCR3_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR3_MBKEN              FSMC_BCR3_MBKEN_Msk                       /*!<Memory bank enable bit                 */\n#define FSMC_BCR3_MUXEN_Pos          (1U)\n#define FSMC_BCR3_MUXEN_Msk          (0x1UL << FSMC_BCR3_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR3_MUXEN              FSMC_BCR3_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR3_MTYP_Pos           (2U)\n#define FSMC_BCR3_MTYP_Msk           (0x3UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR3_MTYP               FSMC_BCR3_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR3_MTYP_0             (0x1UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR3_MTYP_1             (0x2UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR3_MWID_Pos           (4U)\n#define FSMC_BCR3_MWID_Msk           (0x3UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR3_MWID               FSMC_BCR3_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR3_MWID_0             (0x1UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR3_MWID_1             (0x2UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR3_FACCEN_Pos         (6U)\n#define FSMC_BCR3_FACCEN_Msk         (0x1UL << FSMC_BCR3_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR3_FACCEN             FSMC_BCR3_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR3_BURSTEN_Pos        (8U)\n#define FSMC_BCR3_BURSTEN_Msk        (0x1UL << FSMC_BCR3_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR3_BURSTEN            FSMC_BCR3_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR3_WAITPOL_Pos        (9U)\n#define FSMC_BCR3_WAITPOL_Msk        (0x1UL << FSMC_BCR3_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR3_WAITPOL            FSMC_BCR3_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR3_WAITCFG_Pos        (11U)\n#define FSMC_BCR3_WAITCFG_Msk        (0x1UL << FSMC_BCR3_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR3_WAITCFG            FSMC_BCR3_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR3_WREN_Pos           (12U)\n#define FSMC_BCR3_WREN_Msk           (0x1UL << FSMC_BCR3_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR3_WREN               FSMC_BCR3_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR3_WAITEN_Pos         (13U)\n#define FSMC_BCR3_WAITEN_Msk         (0x1UL << FSMC_BCR3_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR3_WAITEN             FSMC_BCR3_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR3_EXTMOD_Pos         (14U)\n#define FSMC_BCR3_EXTMOD_Msk         (0x1UL << FSMC_BCR3_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR3_EXTMOD             FSMC_BCR3_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR3_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR3_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR3_ASYNCWAIT          FSMC_BCR3_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR3_CPSIZE_Pos         (16U)\n#define FSMC_BCR3_CPSIZE_Msk         (0x7UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR3_CPSIZE             FSMC_BCR3_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR3_CPSIZE_0           (0x1UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR3_CPSIZE_1           (0x2UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR3_CPSIZE_2           (0x4UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR3_CBURSTRW_Pos       (19U)\n#define FSMC_BCR3_CBURSTRW_Msk       (0x1UL << FSMC_BCR3_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR3_CBURSTRW           FSMC_BCR3_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BCR4 register  *******************/\n#define FSMC_BCR4_MBKEN_Pos          (0U)\n#define FSMC_BCR4_MBKEN_Msk          (0x1UL << FSMC_BCR4_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR4_MBKEN              FSMC_BCR4_MBKEN_Msk                       /*!<Memory bank enable bit */\n#define FSMC_BCR4_MUXEN_Pos          (1U)\n#define FSMC_BCR4_MUXEN_Msk          (0x1UL << FSMC_BCR4_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR4_MUXEN              FSMC_BCR4_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR4_MTYP_Pos           (2U)\n#define FSMC_BCR4_MTYP_Msk           (0x3UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR4_MTYP               FSMC_BCR4_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR4_MTYP_0             (0x1UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR4_MTYP_1             (0x2UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR4_MWID_Pos           (4U)\n#define FSMC_BCR4_MWID_Msk           (0x3UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR4_MWID               FSMC_BCR4_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR4_MWID_0             (0x1UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR4_MWID_1             (0x2UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR4_FACCEN_Pos         (6U)\n#define FSMC_BCR4_FACCEN_Msk         (0x1UL << FSMC_BCR4_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR4_FACCEN             FSMC_BCR4_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR4_BURSTEN_Pos        (8U)\n#define FSMC_BCR4_BURSTEN_Msk        (0x1UL << FSMC_BCR4_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR4_BURSTEN            FSMC_BCR4_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR4_WAITPOL_Pos        (9U)\n#define FSMC_BCR4_WAITPOL_Msk        (0x1UL << FSMC_BCR4_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR4_WAITPOL            FSMC_BCR4_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR4_WAITCFG_Pos        (11U)\n#define FSMC_BCR4_WAITCFG_Msk        (0x1UL << FSMC_BCR4_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR4_WAITCFG            FSMC_BCR4_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR4_WREN_Pos           (12U)\n#define FSMC_BCR4_WREN_Msk           (0x1UL << FSMC_BCR4_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR4_WREN               FSMC_BCR4_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR4_WAITEN_Pos         (13U)\n#define FSMC_BCR4_WAITEN_Msk         (0x1UL << FSMC_BCR4_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR4_WAITEN             FSMC_BCR4_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR4_EXTMOD_Pos         (14U)\n#define FSMC_BCR4_EXTMOD_Msk         (0x1UL << FSMC_BCR4_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR4_EXTMOD             FSMC_BCR4_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR4_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR4_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR4_ASYNCWAIT          FSMC_BCR4_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR4_CPSIZE_Pos         (16U)\n#define FSMC_BCR4_CPSIZE_Msk         (0x7UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR4_CPSIZE             FSMC_BCR4_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR4_CPSIZE_0           (0x1UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR4_CPSIZE_1           (0x2UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR4_CPSIZE_2           (0x4UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR4_CBURSTRW_Pos       (19U)\n#define FSMC_BCR4_CBURSTRW_Msk       (0x1UL << FSMC_BCR4_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR4_CBURSTRW           FSMC_BCR4_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BTR1 register  ******************/\n#define FSMC_BTR1_ADDSET_Pos         (0U)\n#define FSMC_BTR1_ADDSET_Msk         (0xFUL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR1_ADDSET             FSMC_BTR1_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR1_ADDSET_0           (0x1UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR1_ADDSET_1           (0x2UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR1_ADDSET_2           (0x4UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR1_ADDSET_3           (0x8UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR1_ADDHLD_Pos         (4U)\n#define FSMC_BTR1_ADDHLD_Msk         (0xFUL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR1_ADDHLD             FSMC_BTR1_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR1_ADDHLD_0           (0x1UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR1_ADDHLD_1           (0x2UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR1_ADDHLD_2           (0x4UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR1_ADDHLD_3           (0x8UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR1_DATAST_Pos         (8U)\n#define FSMC_BTR1_DATAST_Msk         (0xFFUL << FSMC_BTR1_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR1_DATAST             FSMC_BTR1_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR1_DATAST_0           (0x01UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR1_DATAST_1           (0x02UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR1_DATAST_2           (0x04UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR1_DATAST_3           (0x08UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR1_DATAST_4           (0x10UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR1_DATAST_5           (0x20UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR1_DATAST_6           (0x40UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR1_DATAST_7           (0x80UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR1_BUSTURN_Pos        (16U)\n#define FSMC_BTR1_BUSTURN_Msk        (0xFUL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR1_BUSTURN            FSMC_BTR1_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR1_BUSTURN_0          (0x1UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR1_BUSTURN_1          (0x2UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR1_BUSTURN_2          (0x4UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR1_BUSTURN_3          (0x8UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR1_CLKDIV_Pos         (20U)\n#define FSMC_BTR1_CLKDIV_Msk         (0xFUL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR1_CLKDIV             FSMC_BTR1_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR1_CLKDIV_0           (0x1UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR1_CLKDIV_1           (0x2UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR1_CLKDIV_2           (0x4UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR1_CLKDIV_3           (0x8UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR1_DATLAT_Pos         (24U)\n#define FSMC_BTR1_DATLAT_Msk         (0xFUL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR1_DATLAT             FSMC_BTR1_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR1_DATLAT_0           (0x1UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR1_DATLAT_1           (0x2UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR1_DATLAT_2           (0x4UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR1_DATLAT_3           (0x8UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR1_ACCMOD_Pos         (28U)\n#define FSMC_BTR1_ACCMOD_Msk         (0x3UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR1_ACCMOD             FSMC_BTR1_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR1_ACCMOD_0           (0x1UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR1_ACCMOD_1           (0x2UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BTR2 register  *******************/\n#define FSMC_BTR2_ADDSET_Pos         (0U)\n#define FSMC_BTR2_ADDSET_Msk         (0xFUL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR2_ADDSET             FSMC_BTR2_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR2_ADDSET_0           (0x1UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR2_ADDSET_1           (0x2UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR2_ADDSET_2           (0x4UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR2_ADDSET_3           (0x8UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR2_ADDHLD_Pos         (4U)\n#define FSMC_BTR2_ADDHLD_Msk         (0xFUL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR2_ADDHLD             FSMC_BTR2_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR2_ADDHLD_0           (0x1UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR2_ADDHLD_1           (0x2UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR2_ADDHLD_2           (0x4UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR2_ADDHLD_3           (0x8UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR2_DATAST_Pos         (8U)\n#define FSMC_BTR2_DATAST_Msk         (0xFFUL << FSMC_BTR2_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR2_DATAST             FSMC_BTR2_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR2_DATAST_0           (0x01UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR2_DATAST_1           (0x02UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR2_DATAST_2           (0x04UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR2_DATAST_3           (0x08UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR2_DATAST_4           (0x10UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR2_DATAST_5           (0x20UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR2_DATAST_6           (0x40UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR2_DATAST_7           (0x80UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR2_BUSTURN_Pos        (16U)\n#define FSMC_BTR2_BUSTURN_Msk        (0xFUL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR2_BUSTURN            FSMC_BTR2_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR2_BUSTURN_0          (0x1UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR2_BUSTURN_1          (0x2UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR2_BUSTURN_2          (0x4UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR2_BUSTURN_3          (0x8UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR2_CLKDIV_Pos         (20U)\n#define FSMC_BTR2_CLKDIV_Msk         (0xFUL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR2_CLKDIV             FSMC_BTR2_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR2_CLKDIV_0           (0x1UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR2_CLKDIV_1           (0x2UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR2_CLKDIV_2           (0x4UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR2_CLKDIV_3           (0x8UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR2_DATLAT_Pos         (24U)\n#define FSMC_BTR2_DATLAT_Msk         (0xFUL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR2_DATLAT             FSMC_BTR2_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR2_DATLAT_0           (0x1UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR2_DATLAT_1           (0x2UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR2_DATLAT_2           (0x4UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR2_DATLAT_3           (0x8UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR2_ACCMOD_Pos         (28U)\n#define FSMC_BTR2_ACCMOD_Msk         (0x3UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR2_ACCMOD             FSMC_BTR2_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR2_ACCMOD_0           (0x1UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR2_ACCMOD_1           (0x2UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/*******************  Bit definition for FSMC_BTR3 register  *******************/\n#define FSMC_BTR3_ADDSET_Pos         (0U)\n#define FSMC_BTR3_ADDSET_Msk         (0xFUL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR3_ADDSET             FSMC_BTR3_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR3_ADDSET_0           (0x1UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR3_ADDSET_1           (0x2UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR3_ADDSET_2           (0x4UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR3_ADDSET_3           (0x8UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR3_ADDHLD_Pos         (4U)\n#define FSMC_BTR3_ADDHLD_Msk         (0xFUL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR3_ADDHLD             FSMC_BTR3_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR3_ADDHLD_0           (0x1UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR3_ADDHLD_1           (0x2UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR3_ADDHLD_2           (0x4UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR3_ADDHLD_3           (0x8UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR3_DATAST_Pos         (8U)\n#define FSMC_BTR3_DATAST_Msk         (0xFFUL << FSMC_BTR3_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR3_DATAST             FSMC_BTR3_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR3_DATAST_0           (0x01UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR3_DATAST_1           (0x02UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR3_DATAST_2           (0x04UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR3_DATAST_3           (0x08UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR3_DATAST_4           (0x10UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR3_DATAST_5           (0x20UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR3_DATAST_6           (0x40UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR3_DATAST_7           (0x80UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR3_BUSTURN_Pos        (16U)\n#define FSMC_BTR3_BUSTURN_Msk        (0xFUL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR3_BUSTURN            FSMC_BTR3_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR3_BUSTURN_0          (0x1UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR3_BUSTURN_1          (0x2UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR3_BUSTURN_2          (0x4UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR3_BUSTURN_3          (0x8UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR3_CLKDIV_Pos         (20U)\n#define FSMC_BTR3_CLKDIV_Msk         (0xFUL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR3_CLKDIV             FSMC_BTR3_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR3_CLKDIV_0           (0x1UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR3_CLKDIV_1           (0x2UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR3_CLKDIV_2           (0x4UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR3_CLKDIV_3           (0x8UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR3_DATLAT_Pos         (24U)\n#define FSMC_BTR3_DATLAT_Msk         (0xFUL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR3_DATLAT             FSMC_BTR3_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR3_DATLAT_0           (0x1UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR3_DATLAT_1           (0x2UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR3_DATLAT_2           (0x4UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR3_DATLAT_3           (0x8UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR3_ACCMOD_Pos         (28U)\n#define FSMC_BTR3_ACCMOD_Msk         (0x3UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR3_ACCMOD             FSMC_BTR3_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR3_ACCMOD_0           (0x1UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR3_ACCMOD_1           (0x2UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BTR4 register  *******************/\n#define FSMC_BTR4_ADDSET_Pos         (0U)\n#define FSMC_BTR4_ADDSET_Msk         (0xFUL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR4_ADDSET             FSMC_BTR4_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR4_ADDSET_0           (0x1UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR4_ADDSET_1           (0x2UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR4_ADDSET_2           (0x4UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR4_ADDSET_3           (0x8UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR4_ADDHLD_Pos         (4U)\n#define FSMC_BTR4_ADDHLD_Msk         (0xFUL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR4_ADDHLD             FSMC_BTR4_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR4_ADDHLD_0           (0x1UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR4_ADDHLD_1           (0x2UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR4_ADDHLD_2           (0x4UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR4_ADDHLD_3           (0x8UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR4_DATAST_Pos         (8U)\n#define FSMC_BTR4_DATAST_Msk         (0xFFUL << FSMC_BTR4_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR4_DATAST             FSMC_BTR4_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR4_DATAST_0           (0x01UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR4_DATAST_1           (0x02UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR4_DATAST_2           (0x04UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR4_DATAST_3           (0x08UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR4_DATAST_4           (0x10UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR4_DATAST_5           (0x20UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR4_DATAST_6           (0x40UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR4_DATAST_7           (0x80UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR4_BUSTURN_Pos        (16U)\n#define FSMC_BTR4_BUSTURN_Msk        (0xFUL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR4_BUSTURN            FSMC_BTR4_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR4_BUSTURN_0          (0x1UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR4_BUSTURN_1          (0x2UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR4_BUSTURN_2          (0x4UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR4_BUSTURN_3          (0x8UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR4_CLKDIV_Pos         (20U)\n#define FSMC_BTR4_CLKDIV_Msk         (0xFUL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR4_CLKDIV             FSMC_BTR4_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR4_CLKDIV_0           (0x1UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR4_CLKDIV_1           (0x2UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR4_CLKDIV_2           (0x4UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR4_CLKDIV_3           (0x8UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR4_DATLAT_Pos         (24U)\n#define FSMC_BTR4_DATLAT_Msk         (0xFUL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR4_DATLAT             FSMC_BTR4_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR4_DATLAT_0           (0x1UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR4_DATLAT_1           (0x2UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR4_DATLAT_2           (0x4UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR4_DATLAT_3           (0x8UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR4_ACCMOD_Pos         (28U)\n#define FSMC_BTR4_ACCMOD_Msk         (0x3UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR4_ACCMOD             FSMC_BTR4_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR4_ACCMOD_0           (0x1UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR4_ACCMOD_1           (0x2UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR1 register  ******************/\n#define FSMC_BWTR1_ADDSET_Pos        (0U)\n#define FSMC_BWTR1_ADDSET_Msk        (0xFUL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR1_ADDSET            FSMC_BWTR1_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR1_ADDSET_0          (0x1UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR1_ADDSET_1          (0x2UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR1_ADDSET_2          (0x4UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR1_ADDSET_3          (0x8UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR1_ADDHLD_Pos        (4U)\n#define FSMC_BWTR1_ADDHLD_Msk        (0xFUL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR1_ADDHLD            FSMC_BWTR1_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR1_ADDHLD_0          (0x1UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR1_ADDHLD_1          (0x2UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR1_ADDHLD_2          (0x4UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR1_ADDHLD_3          (0x8UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR1_DATAST_Pos        (8U)\n#define FSMC_BWTR1_DATAST_Msk        (0xFFUL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR1_DATAST            FSMC_BWTR1_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR1_DATAST_0          (0x01UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR1_DATAST_1          (0x02UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR1_DATAST_2          (0x04UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR1_DATAST_3          (0x08UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR1_DATAST_4          (0x10UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR1_DATAST_5          (0x20UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR1_DATAST_6          (0x40UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR1_DATAST_7          (0x80UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR1_BUSTURN_Pos       (16U)\n#define FSMC_BWTR1_BUSTURN_Msk       (0xFUL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR1_BUSTURN           FSMC_BWTR1_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR1_BUSTURN_0         (0x1UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR1_BUSTURN_1         (0x2UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR1_BUSTURN_2         (0x4UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR1_BUSTURN_3         (0x8UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR1_ACCMOD_Pos        (28U)\n#define FSMC_BWTR1_ACCMOD_Msk        (0x3UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR1_ACCMOD            FSMC_BWTR1_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR1_ACCMOD_0          (0x1UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR1_ACCMOD_1          (0x2UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR2 register  ******************/\n#define FSMC_BWTR2_ADDSET_Pos        (0U)\n#define FSMC_BWTR2_ADDSET_Msk        (0xFUL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR2_ADDSET            FSMC_BWTR2_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR2_ADDSET_0          (0x1UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR2_ADDSET_1          (0x2UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR2_ADDSET_2          (0x4UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR2_ADDSET_3          (0x8UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR2_ADDHLD_Pos        (4U)\n#define FSMC_BWTR2_ADDHLD_Msk        (0xFUL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR2_ADDHLD            FSMC_BWTR2_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR2_ADDHLD_0          (0x1UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR2_ADDHLD_1          (0x2UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR2_ADDHLD_2          (0x4UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR2_ADDHLD_3          (0x8UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR2_DATAST_Pos        (8U)\n#define FSMC_BWTR2_DATAST_Msk        (0xFFUL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR2_DATAST            FSMC_BWTR2_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR2_DATAST_0          (0x01UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR2_DATAST_1          (0x02UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR2_DATAST_2          (0x04UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR2_DATAST_3          (0x08UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR2_DATAST_4          (0x10UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR2_DATAST_5          (0x20UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR2_DATAST_6          (0x40UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR2_DATAST_7          (0x80UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR2_BUSTURN_Pos       (16U)\n#define FSMC_BWTR2_BUSTURN_Msk       (0xFUL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR2_BUSTURN           FSMC_BWTR2_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR2_BUSTURN_0         (0x1UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR2_BUSTURN_1         (0x2UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR2_BUSTURN_2         (0x4UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR2_BUSTURN_3         (0x8UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR2_ACCMOD_Pos        (28U)\n#define FSMC_BWTR2_ACCMOD_Msk        (0x3UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR2_ACCMOD            FSMC_BWTR2_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR2_ACCMOD_0          (0x1UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR2_ACCMOD_1          (0x2UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR3 register  ******************/\n#define FSMC_BWTR3_ADDSET_Pos        (0U)\n#define FSMC_BWTR3_ADDSET_Msk        (0xFUL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR3_ADDSET            FSMC_BWTR3_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR3_ADDSET_0          (0x1UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR3_ADDSET_1          (0x2UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR3_ADDSET_2          (0x4UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR3_ADDSET_3          (0x8UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR3_ADDHLD_Pos        (4U)\n#define FSMC_BWTR3_ADDHLD_Msk        (0xFUL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR3_ADDHLD            FSMC_BWTR3_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR3_ADDHLD_0          (0x1UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR3_ADDHLD_1          (0x2UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR3_ADDHLD_2          (0x4UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR3_ADDHLD_3          (0x8UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR3_DATAST_Pos        (8U)\n#define FSMC_BWTR3_DATAST_Msk        (0xFFUL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR3_DATAST            FSMC_BWTR3_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR3_DATAST_0          (0x01UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR3_DATAST_1          (0x02UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR3_DATAST_2          (0x04UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR3_DATAST_3          (0x08UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR3_DATAST_4          (0x10UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR3_DATAST_5          (0x20UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR3_DATAST_6          (0x40UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR3_DATAST_7          (0x80UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR3_BUSTURN_Pos       (16U)\n#define FSMC_BWTR3_BUSTURN_Msk       (0xFUL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR3_BUSTURN           FSMC_BWTR3_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR3_BUSTURN_0         (0x1UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR3_BUSTURN_1         (0x2UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR3_BUSTURN_2         (0x4UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR3_BUSTURN_3         (0x8UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR3_ACCMOD_Pos        (28U)\n#define FSMC_BWTR3_ACCMOD_Msk        (0x3UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR3_ACCMOD            FSMC_BWTR3_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR3_ACCMOD_0          (0x1UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR3_ACCMOD_1          (0x2UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR4 register  ******************/\n#define FSMC_BWTR4_ADDSET_Pos        (0U)\n#define FSMC_BWTR4_ADDSET_Msk        (0xFUL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR4_ADDSET            FSMC_BWTR4_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR4_ADDSET_0          (0x1UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR4_ADDSET_1          (0x2UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR4_ADDSET_2          (0x4UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR4_ADDSET_3          (0x8UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR4_ADDHLD_Pos        (4U)\n#define FSMC_BWTR4_ADDHLD_Msk        (0xFUL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR4_ADDHLD            FSMC_BWTR4_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR4_ADDHLD_0          (0x1UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR4_ADDHLD_1          (0x2UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR4_ADDHLD_2          (0x4UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR4_ADDHLD_3          (0x8UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR4_DATAST_Pos        (8U)\n#define FSMC_BWTR4_DATAST_Msk        (0xFFUL << FSMC_BWTR4_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR4_DATAST            FSMC_BWTR4_DATAST_Msk                     /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FSMC_BWTR4_DATAST_0          0x00000100U                               /*!<Bit 0 */\n#define FSMC_BWTR4_DATAST_1          0x00000200U                               /*!<Bit 1 */\n#define FSMC_BWTR4_DATAST_2          0x00000400U                               /*!<Bit 2 */\n#define FSMC_BWTR4_DATAST_3          0x00000800U                               /*!<Bit 3 */\n#define FSMC_BWTR4_DATAST_4          0x00001000U                               /*!<Bit 4 */\n#define FSMC_BWTR4_DATAST_5          0x00002000U                               /*!<Bit 5 */\n#define FSMC_BWTR4_DATAST_6          0x00004000U                               /*!<Bit 6 */\n#define FSMC_BWTR4_DATAST_7          0x00008000U                               /*!<Bit 7 */\n\n#define FSMC_BWTR4_BUSTURN_Pos       (16U)\n#define FSMC_BWTR4_BUSTURN_Msk       (0xFUL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR4_BUSTURN           FSMC_BWTR4_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR4_BUSTURN_0         (0x1UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR4_BUSTURN_1         (0x2UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR4_BUSTURN_2         (0x4UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR4_BUSTURN_3         (0x8UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR4_ACCMOD_Pos        (28U)\n#define FSMC_BWTR4_ACCMOD_Msk        (0x3UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR4_ACCMOD            FSMC_BWTR4_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR4_ACCMOD_0          (0x1UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR4_ACCMOD_1          (0x2UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            General Purpose I/O                             */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bits definition for GPIO_MODER register  *****************/\n#define GPIO_MODER_MODER0_Pos            (0U)\n#define GPIO_MODER_MODER0_Msk            (0x3UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */\n#define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk\n#define GPIO_MODER_MODER0_0              (0x1UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */\n#define GPIO_MODER_MODER0_1              (0x2UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */\n#define GPIO_MODER_MODER1_Pos            (2U)\n#define GPIO_MODER_MODER1_Msk            (0x3UL << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */\n#define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk\n#define GPIO_MODER_MODER1_0              (0x1UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */\n#define GPIO_MODER_MODER1_1              (0x2UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */\n#define GPIO_MODER_MODER2_Pos            (4U)\n#define GPIO_MODER_MODER2_Msk            (0x3UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */\n#define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk\n#define GPIO_MODER_MODER2_0              (0x1UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */\n#define GPIO_MODER_MODER2_1              (0x2UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */\n#define GPIO_MODER_MODER3_Pos            (6U)\n#define GPIO_MODER_MODER3_Msk            (0x3UL << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */\n#define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk\n#define GPIO_MODER_MODER3_0              (0x1UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */\n#define GPIO_MODER_MODER3_1              (0x2UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */\n#define GPIO_MODER_MODER4_Pos            (8U)\n#define GPIO_MODER_MODER4_Msk            (0x3UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */\n#define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk\n#define GPIO_MODER_MODER4_0              (0x1UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */\n#define GPIO_MODER_MODER4_1              (0x2UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */\n#define GPIO_MODER_MODER5_Pos            (10U)\n#define GPIO_MODER_MODER5_Msk            (0x3UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */\n#define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk\n#define GPIO_MODER_MODER5_0              (0x1UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */\n#define GPIO_MODER_MODER5_1              (0x2UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */\n#define GPIO_MODER_MODER6_Pos            (12U)\n#define GPIO_MODER_MODER6_Msk            (0x3UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */\n#define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk\n#define GPIO_MODER_MODER6_0              (0x1UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */\n#define GPIO_MODER_MODER6_1              (0x2UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */\n#define GPIO_MODER_MODER7_Pos            (14U)\n#define GPIO_MODER_MODER7_Msk            (0x3UL << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */\n#define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk\n#define GPIO_MODER_MODER7_0              (0x1UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */\n#define GPIO_MODER_MODER7_1              (0x2UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */\n#define GPIO_MODER_MODER8_Pos            (16U)\n#define GPIO_MODER_MODER8_Msk            (0x3UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */\n#define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk\n#define GPIO_MODER_MODER8_0              (0x1UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */\n#define GPIO_MODER_MODER8_1              (0x2UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */\n#define GPIO_MODER_MODER9_Pos            (18U)\n#define GPIO_MODER_MODER9_Msk            (0x3UL << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */\n#define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk\n#define GPIO_MODER_MODER9_0              (0x1UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */\n#define GPIO_MODER_MODER9_1              (0x2UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */\n#define GPIO_MODER_MODER10_Pos           (20U)\n#define GPIO_MODER_MODER10_Msk           (0x3UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */\n#define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk\n#define GPIO_MODER_MODER10_0             (0x1UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */\n#define GPIO_MODER_MODER10_1             (0x2UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */\n#define GPIO_MODER_MODER11_Pos           (22U)\n#define GPIO_MODER_MODER11_Msk           (0x3UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */\n#define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk\n#define GPIO_MODER_MODER11_0             (0x1UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */\n#define GPIO_MODER_MODER11_1             (0x2UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */\n#define GPIO_MODER_MODER12_Pos           (24U)\n#define GPIO_MODER_MODER12_Msk           (0x3UL << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */\n#define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk\n#define GPIO_MODER_MODER12_0             (0x1UL << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */\n#define GPIO_MODER_MODER12_1             (0x2UL << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */\n#define GPIO_MODER_MODER13_Pos           (26U)\n#define GPIO_MODER_MODER13_Msk           (0x3UL << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */\n#define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk\n#define GPIO_MODER_MODER13_0             (0x1UL << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */\n#define GPIO_MODER_MODER13_1             (0x2UL << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */\n#define GPIO_MODER_MODER14_Pos           (28U)\n#define GPIO_MODER_MODER14_Msk           (0x3UL << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */\n#define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk\n#define GPIO_MODER_MODER14_0             (0x1UL << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */\n#define GPIO_MODER_MODER14_1             (0x2UL << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */\n#define GPIO_MODER_MODER15_Pos           (30U)\n#define GPIO_MODER_MODER15_Msk           (0x3UL << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */\n#define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk\n#define GPIO_MODER_MODER15_0             (0x1UL << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */\n#define GPIO_MODER_MODER15_1             (0x2UL << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_MODER_MODE0_Pos             GPIO_MODER_MODER0_Pos\n#define GPIO_MODER_MODE0_Msk             GPIO_MODER_MODER0_Msk\n#define GPIO_MODER_MODE0                 GPIO_MODER_MODER0\n#define GPIO_MODER_MODE0_0               GPIO_MODER_MODER0_0\n#define GPIO_MODER_MODE0_1               GPIO_MODER_MODER0_1\n#define GPIO_MODER_MODE1_Pos             GPIO_MODER_MODER1_Pos\n#define GPIO_MODER_MODE1_Msk             GPIO_MODER_MODER1_Msk\n#define GPIO_MODER_MODE1                 GPIO_MODER_MODER1\n#define GPIO_MODER_MODE1_0               GPIO_MODER_MODER1_0\n#define GPIO_MODER_MODE1_1               GPIO_MODER_MODER1_1\n#define GPIO_MODER_MODE2_Pos             GPIO_MODER_MODER2_PoS\n#define GPIO_MODER_MODE2_Msk             GPIO_MODER_MODER2_Msk\n#define GPIO_MODER_MODE2                 GPIO_MODER_MODER2\n#define GPIO_MODER_MODE2_0               GPIO_MODER_MODER2_0\n#define GPIO_MODER_MODE2_1               GPIO_MODER_MODER2_1\n#define GPIO_MODER_MODE3_Pos             GPIO_MODER_MODER3_Pos\n#define GPIO_MODER_MODE3_Msk             GPIO_MODER_MODER3_Msk\n#define GPIO_MODER_MODE3                 GPIO_MODER_MODER3\n#define GPIO_MODER_MODE3_0               GPIO_MODER_MODER3_0\n#define GPIO_MODER_MODE3_1               GPIO_MODER_MODER3_1\n#define GPIO_MODER_MODE4_Pos             GPIO_MODER_MODER4_Pos\n#define GPIO_MODER_MODE4_Msk             GPIO_MODER_MODER4_Msk\n#define GPIO_MODER_MODE4                 GPIO_MODER_MODER4\n#define GPIO_MODER_MODE4_0               GPIO_MODER_MODER4_0\n#define GPIO_MODER_MODE4_1               GPIO_MODER_MODER4_1\n#define GPIO_MODER_MODE5_Pos             GPIO_MODER_MODER5_Pos\n#define GPIO_MODER_MODE5_Msk             GPIO_MODER_MODER5_Msk\n#define GPIO_MODER_MODE5                 GPIO_MODER_MODER5\n#define GPIO_MODER_MODE5_0               GPIO_MODER_MODER5_0\n#define GPIO_MODER_MODE5_1               GPIO_MODER_MODER5_1\n#define GPIO_MODER_MODE6_Pos             GPIO_MODER_MODER6_Pos\n#define GPIO_MODER_MODE6_Msk             GPIO_MODER_MODER6_Msk\n#define GPIO_MODER_MODE6                 GPIO_MODER_MODER6\n#define GPIO_MODER_MODE6_0               GPIO_MODER_MODER6_0\n#define GPIO_MODER_MODE6_1               GPIO_MODER_MODER6_1\n#define GPIO_MODER_MODE7_Pos             GPIO_MODER_MODER7_Pos\n#define GPIO_MODER_MODE7_Msk             GPIO_MODER_MODER7_Msk\n#define GPIO_MODER_MODE7                 GPIO_MODER_MODER7\n#define GPIO_MODER_MODE7_0               GPIO_MODER_MODER7_0\n#define GPIO_MODER_MODE7_1               GPIO_MODER_MODER7_1\n#define GPIO_MODER_MODE8_Pos             GPIO_MODER_MODER8_Pos\n#define GPIO_MODER_MODE8_Msk             GPIO_MODER_MODER2_Msk\n#define GPIO_MODER_MODE8                 GPIO_MODER_MODER8\n#define GPIO_MODER_MODE8_0               GPIO_MODER_MODER8_0\n#define GPIO_MODER_MODE8_1               GPIO_MODER_MODER8_1\n#define GPIO_MODER_MODE9_Pos             GPIO_MODER_MODER9_Pos\n#define GPIO_MODER_MODE9_Msk             GPIO_MODER_MODER9_Msk\n#define GPIO_MODER_MODE9                 GPIO_MODER_MODER9\n#define GPIO_MODER_MODE9_0               GPIO_MODER_MODER9_0\n#define GPIO_MODER_MODE9_1               GPIO_MODER_MODER9_1\n#define GPIO_MODER_MODE10_Pos            GPIO_MODER_MODER10_Pos\n#define GPIO_MODER_MODE10_Msk            GPIO_MODER_MODER10_Msk\n#define GPIO_MODER_MODE10                GPIO_MODER_MODER10\n#define GPIO_MODER_MODE10_0              GPIO_MODER_MODER10_0\n#define GPIO_MODER_MODE10_1              GPIO_MODER_MODER10_1\n#define GPIO_MODER_MODE11_Pos            GPIO_MODER_MODER11_Pos\n#define GPIO_MODER_MODE11_Msk            GPIO_MODER_MODER11_Msk\n#define GPIO_MODER_MODE11                GPIO_MODER_MODER11\n#define GPIO_MODER_MODE11_0              GPIO_MODER_MODER11_0\n#define GPIO_MODER_MODE11_1              GPIO_MODER_MODER11_1\n#define GPIO_MODER_MODE12_Pos            GPIO_MODER_MODER12_Pos\n#define GPIO_MODER_MODE12_Msk            GPIO_MODER_MODER12_Msk\n#define GPIO_MODER_MODE12                GPIO_MODER_MODER12\n#define GPIO_MODER_MODE12_0              GPIO_MODER_MODER12_0\n#define GPIO_MODER_MODE12_1              GPIO_MODER_MODER12_1\n#define GPIO_MODER_MODE13_Pos            GPIO_MODER_MODER13_Pos\n#define GPIO_MODER_MODE13_Msk            GPIO_MODER_MODER13_Msk\n#define GPIO_MODER_MODE13                GPIO_MODER_MODER13\n#define GPIO_MODER_MODE13_0              GPIO_MODER_MODER13_0\n#define GPIO_MODER_MODE13_1              GPIO_MODER_MODER13_1\n#define GPIO_MODER_MODE14_Pos            GPIO_MODER_MODER14_Pos\n#define GPIO_MODER_MODE14_Msk            GPIO_MODER_MODER14_Msk\n#define GPIO_MODER_MODE14                GPIO_MODER_MODER14\n#define GPIO_MODER_MODE14_0              GPIO_MODER_MODER14_0\n#define GPIO_MODER_MODE14_1              GPIO_MODER_MODER14_1\n#define GPIO_MODER_MODE15_Pos            GPIO_MODER_MODER15_Pos\n#define GPIO_MODER_MODE15_Msk            GPIO_MODER_MODER15_Msk\n#define GPIO_MODER_MODE15                GPIO_MODER_MODER15\n#define GPIO_MODER_MODE15_0              GPIO_MODER_MODER15_0\n#define GPIO_MODER_MODE15_1              GPIO_MODER_MODER15_1\n\n/******************  Bits definition for GPIO_OTYPER register  ****************/\n#define GPIO_OTYPER_OT0_Pos              (0U)\n#define GPIO_OTYPER_OT0_Msk              (0x1UL << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */\n#define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk\n#define GPIO_OTYPER_OT1_Pos              (1U)\n#define GPIO_OTYPER_OT1_Msk              (0x1UL << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */\n#define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk\n#define GPIO_OTYPER_OT2_Pos              (2U)\n#define GPIO_OTYPER_OT2_Msk              (0x1UL << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */\n#define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk\n#define GPIO_OTYPER_OT3_Pos              (3U)\n#define GPIO_OTYPER_OT3_Msk              (0x1UL << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */\n#define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk\n#define GPIO_OTYPER_OT4_Pos              (4U)\n#define GPIO_OTYPER_OT4_Msk              (0x1UL << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */\n#define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk\n#define GPIO_OTYPER_OT5_Pos              (5U)\n#define GPIO_OTYPER_OT5_Msk              (0x1UL << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */\n#define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk\n#define GPIO_OTYPER_OT6_Pos              (6U)\n#define GPIO_OTYPER_OT6_Msk              (0x1UL << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */\n#define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk\n#define GPIO_OTYPER_OT7_Pos              (7U)\n#define GPIO_OTYPER_OT7_Msk              (0x1UL << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */\n#define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk\n#define GPIO_OTYPER_OT8_Pos              (8U)\n#define GPIO_OTYPER_OT8_Msk              (0x1UL << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */\n#define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk\n#define GPIO_OTYPER_OT9_Pos              (9U)\n#define GPIO_OTYPER_OT9_Msk              (0x1UL << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */\n#define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk\n#define GPIO_OTYPER_OT10_Pos             (10U)\n#define GPIO_OTYPER_OT10_Msk             (0x1UL << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */\n#define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk\n#define GPIO_OTYPER_OT11_Pos             (11U)\n#define GPIO_OTYPER_OT11_Msk             (0x1UL << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */\n#define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk\n#define GPIO_OTYPER_OT12_Pos             (12U)\n#define GPIO_OTYPER_OT12_Msk             (0x1UL << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */\n#define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk\n#define GPIO_OTYPER_OT13_Pos             (13U)\n#define GPIO_OTYPER_OT13_Msk             (0x1UL << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */\n#define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk\n#define GPIO_OTYPER_OT14_Pos             (14U)\n#define GPIO_OTYPER_OT14_Msk             (0x1UL << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */\n#define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk\n#define GPIO_OTYPER_OT15_Pos             (15U)\n#define GPIO_OTYPER_OT15_Msk             (0x1UL << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */\n#define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk\n\n/* Legacy defines */\n#define GPIO_OTYPER_OT_0                 GPIO_OTYPER_OT0\n#define GPIO_OTYPER_OT_1                 GPIO_OTYPER_OT1\n#define GPIO_OTYPER_OT_2                 GPIO_OTYPER_OT2\n#define GPIO_OTYPER_OT_3                 GPIO_OTYPER_OT3\n#define GPIO_OTYPER_OT_4                 GPIO_OTYPER_OT4\n#define GPIO_OTYPER_OT_5                 GPIO_OTYPER_OT5\n#define GPIO_OTYPER_OT_6                 GPIO_OTYPER_OT6\n#define GPIO_OTYPER_OT_7                 GPIO_OTYPER_OT7\n#define GPIO_OTYPER_OT_8                 GPIO_OTYPER_OT8\n#define GPIO_OTYPER_OT_9                 GPIO_OTYPER_OT9\n#define GPIO_OTYPER_OT_10                GPIO_OTYPER_OT10\n#define GPIO_OTYPER_OT_11                GPIO_OTYPER_OT11\n#define GPIO_OTYPER_OT_12                GPIO_OTYPER_OT12\n#define GPIO_OTYPER_OT_13                GPIO_OTYPER_OT13\n#define GPIO_OTYPER_OT_14                GPIO_OTYPER_OT14\n#define GPIO_OTYPER_OT_15                GPIO_OTYPER_OT15\n\n/******************  Bits definition for GPIO_OSPEEDR register  ***************/\n#define GPIO_OSPEEDR_OSPEED0_Pos         (0U)\n#define GPIO_OSPEEDR_OSPEED0_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000003 */\n#define GPIO_OSPEEDR_OSPEED0             GPIO_OSPEEDR_OSPEED0_Msk\n#define GPIO_OSPEEDR_OSPEED0_0           (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000001 */\n#define GPIO_OSPEEDR_OSPEED0_1           (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000002 */\n#define GPIO_OSPEEDR_OSPEED1_Pos         (2U)\n#define GPIO_OSPEEDR_OSPEED1_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x0000000C */\n#define GPIO_OSPEEDR_OSPEED1             GPIO_OSPEEDR_OSPEED1_Msk\n#define GPIO_OSPEEDR_OSPEED1_0           (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000004 */\n#define GPIO_OSPEEDR_OSPEED1_1           (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000008 */\n#define GPIO_OSPEEDR_OSPEED2_Pos         (4U)\n#define GPIO_OSPEEDR_OSPEED2_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000030 */\n#define GPIO_OSPEEDR_OSPEED2             GPIO_OSPEEDR_OSPEED2_Msk\n#define GPIO_OSPEEDR_OSPEED2_0           (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000010 */\n#define GPIO_OSPEEDR_OSPEED2_1           (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000020 */\n#define GPIO_OSPEEDR_OSPEED3_Pos         (6U)\n#define GPIO_OSPEEDR_OSPEED3_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x000000C0 */\n#define GPIO_OSPEEDR_OSPEED3             GPIO_OSPEEDR_OSPEED3_Msk\n#define GPIO_OSPEEDR_OSPEED3_0           (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000040 */\n#define GPIO_OSPEEDR_OSPEED3_1           (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000080 */\n#define GPIO_OSPEEDR_OSPEED4_Pos         (8U)\n#define GPIO_OSPEEDR_OSPEED4_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000300 */\n#define GPIO_OSPEEDR_OSPEED4             GPIO_OSPEEDR_OSPEED4_Msk\n#define GPIO_OSPEEDR_OSPEED4_0           (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000100 */\n#define GPIO_OSPEEDR_OSPEED4_1           (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000200 */\n#define GPIO_OSPEEDR_OSPEED5_Pos         (10U)\n#define GPIO_OSPEEDR_OSPEED5_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000C00 */\n#define GPIO_OSPEEDR_OSPEED5             GPIO_OSPEEDR_OSPEED5_Msk\n#define GPIO_OSPEEDR_OSPEED5_0           (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000400 */\n#define GPIO_OSPEEDR_OSPEED5_1           (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000800 */\n#define GPIO_OSPEEDR_OSPEED6_Pos         (12U)\n#define GPIO_OSPEEDR_OSPEED6_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00003000 */\n#define GPIO_OSPEEDR_OSPEED6             GPIO_OSPEEDR_OSPEED6_Msk\n#define GPIO_OSPEEDR_OSPEED6_0           (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00001000 */\n#define GPIO_OSPEEDR_OSPEED6_1           (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00002000 */\n#define GPIO_OSPEEDR_OSPEED7_Pos         (14U)\n#define GPIO_OSPEEDR_OSPEED7_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x0000C000 */\n#define GPIO_OSPEEDR_OSPEED7             GPIO_OSPEEDR_OSPEED7_Msk\n#define GPIO_OSPEEDR_OSPEED7_0           (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00004000 */\n#define GPIO_OSPEEDR_OSPEED7_1           (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00008000 */\n#define GPIO_OSPEEDR_OSPEED8_Pos         (16U)\n#define GPIO_OSPEEDR_OSPEED8_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00030000 */\n#define GPIO_OSPEEDR_OSPEED8             GPIO_OSPEEDR_OSPEED8_Msk\n#define GPIO_OSPEEDR_OSPEED8_0           (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00010000 */\n#define GPIO_OSPEEDR_OSPEED8_1           (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00020000 */\n#define GPIO_OSPEEDR_OSPEED9_Pos         (18U)\n#define GPIO_OSPEEDR_OSPEED9_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x000C0000 */\n#define GPIO_OSPEEDR_OSPEED9             GPIO_OSPEEDR_OSPEED9_Msk\n#define GPIO_OSPEEDR_OSPEED9_0           (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00040000 */\n#define GPIO_OSPEEDR_OSPEED9_1           (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00080000 */\n#define GPIO_OSPEEDR_OSPEED10_Pos        (20U)\n#define GPIO_OSPEEDR_OSPEED10_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00300000 */\n#define GPIO_OSPEEDR_OSPEED10            GPIO_OSPEEDR_OSPEED10_Msk\n#define GPIO_OSPEEDR_OSPEED10_0          (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00100000 */\n#define GPIO_OSPEEDR_OSPEED10_1          (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00200000 */\n#define GPIO_OSPEEDR_OSPEED11_Pos        (22U)\n#define GPIO_OSPEEDR_OSPEED11_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00C00000 */\n#define GPIO_OSPEEDR_OSPEED11            GPIO_OSPEEDR_OSPEED11_Msk\n#define GPIO_OSPEEDR_OSPEED11_0          (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00400000 */\n#define GPIO_OSPEEDR_OSPEED11_1          (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00800000 */\n#define GPIO_OSPEEDR_OSPEED12_Pos        (24U)\n#define GPIO_OSPEEDR_OSPEED12_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x03000000 */\n#define GPIO_OSPEEDR_OSPEED12            GPIO_OSPEEDR_OSPEED12_Msk\n#define GPIO_OSPEEDR_OSPEED12_0          (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x01000000 */\n#define GPIO_OSPEEDR_OSPEED12_1          (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x02000000 */\n#define GPIO_OSPEEDR_OSPEED13_Pos        (26U)\n#define GPIO_OSPEEDR_OSPEED13_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x0C000000 */\n#define GPIO_OSPEEDR_OSPEED13            GPIO_OSPEEDR_OSPEED13_Msk\n#define GPIO_OSPEEDR_OSPEED13_0          (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x04000000 */\n#define GPIO_OSPEEDR_OSPEED13_1          (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x08000000 */\n#define GPIO_OSPEEDR_OSPEED14_Pos        (28U)\n#define GPIO_OSPEEDR_OSPEED14_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x30000000 */\n#define GPIO_OSPEEDR_OSPEED14            GPIO_OSPEEDR_OSPEED14_Msk\n#define GPIO_OSPEEDR_OSPEED14_0          (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x10000000 */\n#define GPIO_OSPEEDR_OSPEED14_1          (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x20000000 */\n#define GPIO_OSPEEDR_OSPEED15_Pos        (30U)\n#define GPIO_OSPEEDR_OSPEED15_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0xC0000000 */\n#define GPIO_OSPEEDR_OSPEED15            GPIO_OSPEEDR_OSPEED15_Msk\n#define GPIO_OSPEEDR_OSPEED15_0          (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x40000000 */\n#define GPIO_OSPEEDR_OSPEED15_1          (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDR_OSPEED0\n#define GPIO_OSPEEDER_OSPEEDR0_0         GPIO_OSPEEDR_OSPEED0_0\n#define GPIO_OSPEEDER_OSPEEDR0_1         GPIO_OSPEEDR_OSPEED0_1\n#define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDR_OSPEED1\n#define GPIO_OSPEEDER_OSPEEDR1_0         GPIO_OSPEEDR_OSPEED1_0\n#define GPIO_OSPEEDER_OSPEEDR1_1         GPIO_OSPEEDR_OSPEED1_1\n#define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDR_OSPEED2\n#define GPIO_OSPEEDER_OSPEEDR2_0         GPIO_OSPEEDR_OSPEED2_0\n#define GPIO_OSPEEDER_OSPEEDR2_1         GPIO_OSPEEDR_OSPEED2_1\n#define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDR_OSPEED3\n#define GPIO_OSPEEDER_OSPEEDR3_0         GPIO_OSPEEDR_OSPEED3_0\n#define GPIO_OSPEEDER_OSPEEDR3_1         GPIO_OSPEEDR_OSPEED3_1\n#define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDR_OSPEED4\n#define GPIO_OSPEEDER_OSPEEDR4_0         GPIO_OSPEEDR_OSPEED4_0\n#define GPIO_OSPEEDER_OSPEEDR4_1         GPIO_OSPEEDR_OSPEED4_1\n#define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDR_OSPEED5\n#define GPIO_OSPEEDER_OSPEEDR5_0         GPIO_OSPEEDR_OSPEED5_0\n#define GPIO_OSPEEDER_OSPEEDR5_1         GPIO_OSPEEDR_OSPEED5_1\n#define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDR_OSPEED6\n#define GPIO_OSPEEDER_OSPEEDR6_0         GPIO_OSPEEDR_OSPEED6_0\n#define GPIO_OSPEEDER_OSPEEDR6_1         GPIO_OSPEEDR_OSPEED6_1\n#define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDR_OSPEED7\n#define GPIO_OSPEEDER_OSPEEDR7_0         GPIO_OSPEEDR_OSPEED7_0\n#define GPIO_OSPEEDER_OSPEEDR7_1         GPIO_OSPEEDR_OSPEED7_1\n#define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDR_OSPEED8\n#define GPIO_OSPEEDER_OSPEEDR8_0         GPIO_OSPEEDR_OSPEED8_0\n#define GPIO_OSPEEDER_OSPEEDR8_1         GPIO_OSPEEDR_OSPEED8_1\n#define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDR_OSPEED9\n#define GPIO_OSPEEDER_OSPEEDR9_0         GPIO_OSPEEDR_OSPEED9_0\n#define GPIO_OSPEEDER_OSPEEDR9_1         GPIO_OSPEEDR_OSPEED9_1\n#define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDR_OSPEED10\n#define GPIO_OSPEEDER_OSPEEDR10_0        GPIO_OSPEEDR_OSPEED10_0\n#define GPIO_OSPEEDER_OSPEEDR10_1        GPIO_OSPEEDR_OSPEED10_1\n#define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDR_OSPEED11\n#define GPIO_OSPEEDER_OSPEEDR11_0        GPIO_OSPEEDR_OSPEED11_0\n#define GPIO_OSPEEDER_OSPEEDR11_1        GPIO_OSPEEDR_OSPEED11_1\n#define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDR_OSPEED12\n#define GPIO_OSPEEDER_OSPEEDR12_0        GPIO_OSPEEDR_OSPEED12_0\n#define GPIO_OSPEEDER_OSPEEDR12_1        GPIO_OSPEEDR_OSPEED12_1\n#define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDR_OSPEED13\n#define GPIO_OSPEEDER_OSPEEDR13_0        GPIO_OSPEEDR_OSPEED13_0\n#define GPIO_OSPEEDER_OSPEEDR13_1        GPIO_OSPEEDR_OSPEED13_1\n#define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDR_OSPEED14\n#define GPIO_OSPEEDER_OSPEEDR14_0        GPIO_OSPEEDR_OSPEED14_0\n#define GPIO_OSPEEDER_OSPEEDR14_1        GPIO_OSPEEDR_OSPEED14_1\n#define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDR_OSPEED15\n#define GPIO_OSPEEDER_OSPEEDR15_0        GPIO_OSPEEDR_OSPEED15_0\n#define GPIO_OSPEEDER_OSPEEDR15_1        GPIO_OSPEEDR_OSPEED15_1\n\n/******************  Bits definition for GPIO_PUPDR register  *****************/\n#define GPIO_PUPDR_PUPD0_Pos             (0U)\n#define GPIO_PUPDR_PUPD0_Msk             (0x3UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000003 */\n#define GPIO_PUPDR_PUPD0                 GPIO_PUPDR_PUPD0_Msk\n#define GPIO_PUPDR_PUPD0_0               (0x1UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000001 */\n#define GPIO_PUPDR_PUPD0_1               (0x2UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000002 */\n#define GPIO_PUPDR_PUPD1_Pos             (2U)\n#define GPIO_PUPDR_PUPD1_Msk             (0x3UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x0000000C */\n#define GPIO_PUPDR_PUPD1                 GPIO_PUPDR_PUPD1_Msk\n#define GPIO_PUPDR_PUPD1_0               (0x1UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000004 */\n#define GPIO_PUPDR_PUPD1_1               (0x2UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000008 */\n#define GPIO_PUPDR_PUPD2_Pos             (4U)\n#define GPIO_PUPDR_PUPD2_Msk             (0x3UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000030 */\n#define GPIO_PUPDR_PUPD2                 GPIO_PUPDR_PUPD2_Msk\n#define GPIO_PUPDR_PUPD2_0               (0x1UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000010 */\n#define GPIO_PUPDR_PUPD2_1               (0x2UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000020 */\n#define GPIO_PUPDR_PUPD3_Pos             (6U)\n#define GPIO_PUPDR_PUPD3_Msk             (0x3UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x000000C0 */\n#define GPIO_PUPDR_PUPD3                 GPIO_PUPDR_PUPD3_Msk\n#define GPIO_PUPDR_PUPD3_0               (0x1UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000040 */\n#define GPIO_PUPDR_PUPD3_1               (0x2UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000080 */\n#define GPIO_PUPDR_PUPD4_Pos             (8U)\n#define GPIO_PUPDR_PUPD4_Msk             (0x3UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000300 */\n#define GPIO_PUPDR_PUPD4                 GPIO_PUPDR_PUPD4_Msk\n#define GPIO_PUPDR_PUPD4_0               (0x1UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000100 */\n#define GPIO_PUPDR_PUPD4_1               (0x2UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000200 */\n#define GPIO_PUPDR_PUPD5_Pos             (10U)\n#define GPIO_PUPDR_PUPD5_Msk             (0x3UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000C00 */\n#define GPIO_PUPDR_PUPD5                 GPIO_PUPDR_PUPD5_Msk\n#define GPIO_PUPDR_PUPD5_0               (0x1UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000400 */\n#define GPIO_PUPDR_PUPD5_1               (0x2UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000800 */\n#define GPIO_PUPDR_PUPD6_Pos             (12U)\n#define GPIO_PUPDR_PUPD6_Msk             (0x3UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00003000 */\n#define GPIO_PUPDR_PUPD6                 GPIO_PUPDR_PUPD6_Msk\n#define GPIO_PUPDR_PUPD6_0               (0x1UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00001000 */\n#define GPIO_PUPDR_PUPD6_1               (0x2UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00002000 */\n#define GPIO_PUPDR_PUPD7_Pos             (14U)\n#define GPIO_PUPDR_PUPD7_Msk             (0x3UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x0000C000 */\n#define GPIO_PUPDR_PUPD7                 GPIO_PUPDR_PUPD7_Msk\n#define GPIO_PUPDR_PUPD7_0               (0x1UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00004000 */\n#define GPIO_PUPDR_PUPD7_1               (0x2UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00008000 */\n#define GPIO_PUPDR_PUPD8_Pos             (16U)\n#define GPIO_PUPDR_PUPD8_Msk             (0x3UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00030000 */\n#define GPIO_PUPDR_PUPD8                 GPIO_PUPDR_PUPD8_Msk\n#define GPIO_PUPDR_PUPD8_0               (0x1UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00010000 */\n#define GPIO_PUPDR_PUPD8_1               (0x2UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00020000 */\n#define GPIO_PUPDR_PUPD9_Pos             (18U)\n#define GPIO_PUPDR_PUPD9_Msk             (0x3UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x000C0000 */\n#define GPIO_PUPDR_PUPD9                 GPIO_PUPDR_PUPD9_Msk\n#define GPIO_PUPDR_PUPD9_0               (0x1UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00040000 */\n#define GPIO_PUPDR_PUPD9_1               (0x2UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00080000 */\n#define GPIO_PUPDR_PUPD10_Pos            (20U)\n#define GPIO_PUPDR_PUPD10_Msk            (0x3UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00300000 */\n#define GPIO_PUPDR_PUPD10                GPIO_PUPDR_PUPD10_Msk\n#define GPIO_PUPDR_PUPD10_0              (0x1UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00100000 */\n#define GPIO_PUPDR_PUPD10_1              (0x2UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00200000 */\n#define GPIO_PUPDR_PUPD11_Pos            (22U)\n#define GPIO_PUPDR_PUPD11_Msk            (0x3UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00C00000 */\n#define GPIO_PUPDR_PUPD11                GPIO_PUPDR_PUPD11_Msk\n#define GPIO_PUPDR_PUPD11_0              (0x1UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00400000 */\n#define GPIO_PUPDR_PUPD11_1              (0x2UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00800000 */\n#define GPIO_PUPDR_PUPD12_Pos            (24U)\n#define GPIO_PUPDR_PUPD12_Msk            (0x3UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x03000000 */\n#define GPIO_PUPDR_PUPD12                GPIO_PUPDR_PUPD12_Msk\n#define GPIO_PUPDR_PUPD12_0              (0x1UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x01000000 */\n#define GPIO_PUPDR_PUPD12_1              (0x2UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x02000000 */\n#define GPIO_PUPDR_PUPD13_Pos            (26U)\n#define GPIO_PUPDR_PUPD13_Msk            (0x3UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x0C000000 */\n#define GPIO_PUPDR_PUPD13                GPIO_PUPDR_PUPD13_Msk\n#define GPIO_PUPDR_PUPD13_0              (0x1UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x04000000 */\n#define GPIO_PUPDR_PUPD13_1              (0x2UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x08000000 */\n#define GPIO_PUPDR_PUPD14_Pos            (28U)\n#define GPIO_PUPDR_PUPD14_Msk            (0x3UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x30000000 */\n#define GPIO_PUPDR_PUPD14                GPIO_PUPDR_PUPD14_Msk\n#define GPIO_PUPDR_PUPD14_0              (0x1UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x10000000 */\n#define GPIO_PUPDR_PUPD14_1              (0x2UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x20000000 */\n#define GPIO_PUPDR_PUPD15_Pos            (30U)\n#define GPIO_PUPDR_PUPD15_Msk            (0x3UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0xC0000000 */\n#define GPIO_PUPDR_PUPD15                GPIO_PUPDR_PUPD15_Msk\n#define GPIO_PUPDR_PUPD15_0              (0x1UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x40000000 */\n#define GPIO_PUPDR_PUPD15_1              (0x2UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPD0\n#define GPIO_PUPDR_PUPDR0_0              GPIO_PUPDR_PUPD0_0\n#define GPIO_PUPDR_PUPDR0_1              GPIO_PUPDR_PUPD0_1\n#define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPD1\n#define GPIO_PUPDR_PUPDR1_0              GPIO_PUPDR_PUPD1_0\n#define GPIO_PUPDR_PUPDR1_1              GPIO_PUPDR_PUPD1_1\n#define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPD2\n#define GPIO_PUPDR_PUPDR2_0              GPIO_PUPDR_PUPD2_0\n#define GPIO_PUPDR_PUPDR2_1              GPIO_PUPDR_PUPD2_1\n#define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPD3\n#define GPIO_PUPDR_PUPDR3_0              GPIO_PUPDR_PUPD3_0\n#define GPIO_PUPDR_PUPDR3_1              GPIO_PUPDR_PUPD3_1\n#define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPD4\n#define GPIO_PUPDR_PUPDR4_0              GPIO_PUPDR_PUPD4_0\n#define GPIO_PUPDR_PUPDR4_1              GPIO_PUPDR_PUPD4_1\n#define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPD5\n#define GPIO_PUPDR_PUPDR5_0              GPIO_PUPDR_PUPD5_0\n#define GPIO_PUPDR_PUPDR5_1              GPIO_PUPDR_PUPD5_1\n#define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPD6\n#define GPIO_PUPDR_PUPDR6_0              GPIO_PUPDR_PUPD6_0\n#define GPIO_PUPDR_PUPDR6_1              GPIO_PUPDR_PUPD6_1\n#define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPD7\n#define GPIO_PUPDR_PUPDR7_0              GPIO_PUPDR_PUPD7_0\n#define GPIO_PUPDR_PUPDR7_1              GPIO_PUPDR_PUPD7_1\n#define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPD8\n#define GPIO_PUPDR_PUPDR8_0              GPIO_PUPDR_PUPD8_0\n#define GPIO_PUPDR_PUPDR8_1              GPIO_PUPDR_PUPD8_1\n#define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPD9\n#define GPIO_PUPDR_PUPDR9_0              GPIO_PUPDR_PUPD9_0\n#define GPIO_PUPDR_PUPDR9_1              GPIO_PUPDR_PUPD9_1\n#define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPD10\n#define GPIO_PUPDR_PUPDR10_0             GPIO_PUPDR_PUPD10_0\n#define GPIO_PUPDR_PUPDR10_1             GPIO_PUPDR_PUPD10_1\n#define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPD11\n#define GPIO_PUPDR_PUPDR11_0             GPIO_PUPDR_PUPD11_0\n#define GPIO_PUPDR_PUPDR11_1             GPIO_PUPDR_PUPD11_1\n#define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPD12\n#define GPIO_PUPDR_PUPDR12_0             GPIO_PUPDR_PUPD12_0\n#define GPIO_PUPDR_PUPDR12_1             GPIO_PUPDR_PUPD12_1\n#define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPD13\n#define GPIO_PUPDR_PUPDR13_0             GPIO_PUPDR_PUPD13_0\n#define GPIO_PUPDR_PUPDR13_1             GPIO_PUPDR_PUPD13_1\n#define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPD14\n#define GPIO_PUPDR_PUPDR14_0             GPIO_PUPDR_PUPD14_0\n#define GPIO_PUPDR_PUPDR14_1             GPIO_PUPDR_PUPD14_1\n#define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPD15\n#define GPIO_PUPDR_PUPDR15_0             GPIO_PUPDR_PUPD15_0\n#define GPIO_PUPDR_PUPDR15_1             GPIO_PUPDR_PUPD15_1\n\n/******************  Bits definition for GPIO_IDR register  *******************/\n#define GPIO_IDR_ID0_Pos                 (0U)\n#define GPIO_IDR_ID0_Msk                 (0x1UL << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */\n#define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk\n#define GPIO_IDR_ID1_Pos                 (1U)\n#define GPIO_IDR_ID1_Msk                 (0x1UL << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */\n#define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk\n#define GPIO_IDR_ID2_Pos                 (2U)\n#define GPIO_IDR_ID2_Msk                 (0x1UL << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */\n#define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk\n#define GPIO_IDR_ID3_Pos                 (3U)\n#define GPIO_IDR_ID3_Msk                 (0x1UL << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */\n#define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk\n#define GPIO_IDR_ID4_Pos                 (4U)\n#define GPIO_IDR_ID4_Msk                 (0x1UL << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */\n#define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk\n#define GPIO_IDR_ID5_Pos                 (5U)\n#define GPIO_IDR_ID5_Msk                 (0x1UL << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */\n#define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk\n#define GPIO_IDR_ID6_Pos                 (6U)\n#define GPIO_IDR_ID6_Msk                 (0x1UL << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */\n#define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk\n#define GPIO_IDR_ID7_Pos                 (7U)\n#define GPIO_IDR_ID7_Msk                 (0x1UL << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */\n#define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk\n#define GPIO_IDR_ID8_Pos                 (8U)\n#define GPIO_IDR_ID8_Msk                 (0x1UL << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */\n#define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk\n#define GPIO_IDR_ID9_Pos                 (9U)\n#define GPIO_IDR_ID9_Msk                 (0x1UL << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */\n#define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk\n#define GPIO_IDR_ID10_Pos                (10U)\n#define GPIO_IDR_ID10_Msk                (0x1UL << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */\n#define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk\n#define GPIO_IDR_ID11_Pos                (11U)\n#define GPIO_IDR_ID11_Msk                (0x1UL << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */\n#define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk\n#define GPIO_IDR_ID12_Pos                (12U)\n#define GPIO_IDR_ID12_Msk                (0x1UL << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */\n#define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk\n#define GPIO_IDR_ID13_Pos                (13U)\n#define GPIO_IDR_ID13_Msk                (0x1UL << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */\n#define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk\n#define GPIO_IDR_ID14_Pos                (14U)\n#define GPIO_IDR_ID14_Msk                (0x1UL << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */\n#define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk\n#define GPIO_IDR_ID15_Pos                (15U)\n#define GPIO_IDR_ID15_Msk                (0x1UL << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */\n#define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk\n\n/* Legacy defines */\n#define GPIO_IDR_IDR_0                   GPIO_IDR_ID0\n#define GPIO_IDR_IDR_1                   GPIO_IDR_ID1\n#define GPIO_IDR_IDR_2                   GPIO_IDR_ID2\n#define GPIO_IDR_IDR_3                   GPIO_IDR_ID3\n#define GPIO_IDR_IDR_4                   GPIO_IDR_ID4\n#define GPIO_IDR_IDR_5                   GPIO_IDR_ID5\n#define GPIO_IDR_IDR_6                   GPIO_IDR_ID6\n#define GPIO_IDR_IDR_7                   GPIO_IDR_ID7\n#define GPIO_IDR_IDR_8                   GPIO_IDR_ID8\n#define GPIO_IDR_IDR_9                   GPIO_IDR_ID9\n#define GPIO_IDR_IDR_10                  GPIO_IDR_ID10\n#define GPIO_IDR_IDR_11                  GPIO_IDR_ID11\n#define GPIO_IDR_IDR_12                  GPIO_IDR_ID12\n#define GPIO_IDR_IDR_13                  GPIO_IDR_ID13\n#define GPIO_IDR_IDR_14                  GPIO_IDR_ID14\n#define GPIO_IDR_IDR_15                  GPIO_IDR_ID15\n\n/******************  Bits definition for GPIO_ODR register  *******************/\n#define GPIO_ODR_OD0_Pos                 (0U)\n#define GPIO_ODR_OD0_Msk                 (0x1UL << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */\n#define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk\n#define GPIO_ODR_OD1_Pos                 (1U)\n#define GPIO_ODR_OD1_Msk                 (0x1UL << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */\n#define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk\n#define GPIO_ODR_OD2_Pos                 (2U)\n#define GPIO_ODR_OD2_Msk                 (0x1UL << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */\n#define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk\n#define GPIO_ODR_OD3_Pos                 (3U)\n#define GPIO_ODR_OD3_Msk                 (0x1UL << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */\n#define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk\n#define GPIO_ODR_OD4_Pos                 (4U)\n#define GPIO_ODR_OD4_Msk                 (0x1UL << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */\n#define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk\n#define GPIO_ODR_OD5_Pos                 (5U)\n#define GPIO_ODR_OD5_Msk                 (0x1UL << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */\n#define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk\n#define GPIO_ODR_OD6_Pos                 (6U)\n#define GPIO_ODR_OD6_Msk                 (0x1UL << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */\n#define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk\n#define GPIO_ODR_OD7_Pos                 (7U)\n#define GPIO_ODR_OD7_Msk                 (0x1UL << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */\n#define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk\n#define GPIO_ODR_OD8_Pos                 (8U)\n#define GPIO_ODR_OD8_Msk                 (0x1UL << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */\n#define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk\n#define GPIO_ODR_OD9_Pos                 (9U)\n#define GPIO_ODR_OD9_Msk                 (0x1UL << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */\n#define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk\n#define GPIO_ODR_OD10_Pos                (10U)\n#define GPIO_ODR_OD10_Msk                (0x1UL << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */\n#define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk\n#define GPIO_ODR_OD11_Pos                (11U)\n#define GPIO_ODR_OD11_Msk                (0x1UL << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */\n#define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk\n#define GPIO_ODR_OD12_Pos                (12U)\n#define GPIO_ODR_OD12_Msk                (0x1UL << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */\n#define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk\n#define GPIO_ODR_OD13_Pos                (13U)\n#define GPIO_ODR_OD13_Msk                (0x1UL << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */\n#define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk\n#define GPIO_ODR_OD14_Pos                (14U)\n#define GPIO_ODR_OD14_Msk                (0x1UL << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */\n#define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk\n#define GPIO_ODR_OD15_Pos                (15U)\n#define GPIO_ODR_OD15_Msk                (0x1UL << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */\n#define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk\n/* Legacy defines */\n#define GPIO_ODR_ODR_0                   GPIO_ODR_OD0\n#define GPIO_ODR_ODR_1                   GPIO_ODR_OD1\n#define GPIO_ODR_ODR_2                   GPIO_ODR_OD2\n#define GPIO_ODR_ODR_3                   GPIO_ODR_OD3\n#define GPIO_ODR_ODR_4                   GPIO_ODR_OD4\n#define GPIO_ODR_ODR_5                   GPIO_ODR_OD5\n#define GPIO_ODR_ODR_6                   GPIO_ODR_OD6\n#define GPIO_ODR_ODR_7                   GPIO_ODR_OD7\n#define GPIO_ODR_ODR_8                   GPIO_ODR_OD8\n#define GPIO_ODR_ODR_9                   GPIO_ODR_OD9\n#define GPIO_ODR_ODR_10                  GPIO_ODR_OD10\n#define GPIO_ODR_ODR_11                  GPIO_ODR_OD11\n#define GPIO_ODR_ODR_12                  GPIO_ODR_OD12\n#define GPIO_ODR_ODR_13                  GPIO_ODR_OD13\n#define GPIO_ODR_ODR_14                  GPIO_ODR_OD14\n#define GPIO_ODR_ODR_15                  GPIO_ODR_OD15\n\n/******************  Bits definition for GPIO_BSRR register  ******************/\n#define GPIO_BSRR_BS0_Pos                (0U)\n#define GPIO_BSRR_BS0_Msk                (0x1UL << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */\n#define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk\n#define GPIO_BSRR_BS1_Pos                (1U)\n#define GPIO_BSRR_BS1_Msk                (0x1UL << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */\n#define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk\n#define GPIO_BSRR_BS2_Pos                (2U)\n#define GPIO_BSRR_BS2_Msk                (0x1UL << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */\n#define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk\n#define GPIO_BSRR_BS3_Pos                (3U)\n#define GPIO_BSRR_BS3_Msk                (0x1UL << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */\n#define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk\n#define GPIO_BSRR_BS4_Pos                (4U)\n#define GPIO_BSRR_BS4_Msk                (0x1UL << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */\n#define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk\n#define GPIO_BSRR_BS5_Pos                (5U)\n#define GPIO_BSRR_BS5_Msk                (0x1UL << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */\n#define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk\n#define GPIO_BSRR_BS6_Pos                (6U)\n#define GPIO_BSRR_BS6_Msk                (0x1UL << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */\n#define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk\n#define GPIO_BSRR_BS7_Pos                (7U)\n#define GPIO_BSRR_BS7_Msk                (0x1UL << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */\n#define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk\n#define GPIO_BSRR_BS8_Pos                (8U)\n#define GPIO_BSRR_BS8_Msk                (0x1UL << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */\n#define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk\n#define GPIO_BSRR_BS9_Pos                (9U)\n#define GPIO_BSRR_BS9_Msk                (0x1UL << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */\n#define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk\n#define GPIO_BSRR_BS10_Pos               (10U)\n#define GPIO_BSRR_BS10_Msk               (0x1UL << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */\n#define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk\n#define GPIO_BSRR_BS11_Pos               (11U)\n#define GPIO_BSRR_BS11_Msk               (0x1UL << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */\n#define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk\n#define GPIO_BSRR_BS12_Pos               (12U)\n#define GPIO_BSRR_BS12_Msk               (0x1UL << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */\n#define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk\n#define GPIO_BSRR_BS13_Pos               (13U)\n#define GPIO_BSRR_BS13_Msk               (0x1UL << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */\n#define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk\n#define GPIO_BSRR_BS14_Pos               (14U)\n#define GPIO_BSRR_BS14_Msk               (0x1UL << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */\n#define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk\n#define GPIO_BSRR_BS15_Pos               (15U)\n#define GPIO_BSRR_BS15_Msk               (0x1UL << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */\n#define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk\n#define GPIO_BSRR_BR0_Pos                (16U)\n#define GPIO_BSRR_BR0_Msk                (0x1UL << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */\n#define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk\n#define GPIO_BSRR_BR1_Pos                (17U)\n#define GPIO_BSRR_BR1_Msk                (0x1UL << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */\n#define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk\n#define GPIO_BSRR_BR2_Pos                (18U)\n#define GPIO_BSRR_BR2_Msk                (0x1UL << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */\n#define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk\n#define GPIO_BSRR_BR3_Pos                (19U)\n#define GPIO_BSRR_BR3_Msk                (0x1UL << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */\n#define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk\n#define GPIO_BSRR_BR4_Pos                (20U)\n#define GPIO_BSRR_BR4_Msk                (0x1UL << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */\n#define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk\n#define GPIO_BSRR_BR5_Pos                (21U)\n#define GPIO_BSRR_BR5_Msk                (0x1UL << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */\n#define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk\n#define GPIO_BSRR_BR6_Pos                (22U)\n#define GPIO_BSRR_BR6_Msk                (0x1UL << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */\n#define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk\n#define GPIO_BSRR_BR7_Pos                (23U)\n#define GPIO_BSRR_BR7_Msk                (0x1UL << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */\n#define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk\n#define GPIO_BSRR_BR8_Pos                (24U)\n#define GPIO_BSRR_BR8_Msk                (0x1UL << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */\n#define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk\n#define GPIO_BSRR_BR9_Pos                (25U)\n#define GPIO_BSRR_BR9_Msk                (0x1UL << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */\n#define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk\n#define GPIO_BSRR_BR10_Pos               (26U)\n#define GPIO_BSRR_BR10_Msk               (0x1UL << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */\n#define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk\n#define GPIO_BSRR_BR11_Pos               (27U)\n#define GPIO_BSRR_BR11_Msk               (0x1UL << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */\n#define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk\n#define GPIO_BSRR_BR12_Pos               (28U)\n#define GPIO_BSRR_BR12_Msk               (0x1UL << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */\n#define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk\n#define GPIO_BSRR_BR13_Pos               (29U)\n#define GPIO_BSRR_BR13_Msk               (0x1UL << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */\n#define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk\n#define GPIO_BSRR_BR14_Pos               (30U)\n#define GPIO_BSRR_BR14_Msk               (0x1UL << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */\n#define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk\n#define GPIO_BSRR_BR15_Pos               (31U)\n#define GPIO_BSRR_BR15_Msk               (0x1UL << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */\n#define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk\n\n/* Legacy defines */\n#define GPIO_BSRR_BS_0                   GPIO_BSRR_BS0\n#define GPIO_BSRR_BS_1                   GPIO_BSRR_BS1\n#define GPIO_BSRR_BS_2                   GPIO_BSRR_BS2\n#define GPIO_BSRR_BS_3                   GPIO_BSRR_BS3\n#define GPIO_BSRR_BS_4                   GPIO_BSRR_BS4\n#define GPIO_BSRR_BS_5                   GPIO_BSRR_BS5\n#define GPIO_BSRR_BS_6                   GPIO_BSRR_BS6\n#define GPIO_BSRR_BS_7                   GPIO_BSRR_BS7\n#define GPIO_BSRR_BS_8                   GPIO_BSRR_BS8\n#define GPIO_BSRR_BS_9                   GPIO_BSRR_BS9\n#define GPIO_BSRR_BS_10                  GPIO_BSRR_BS10\n#define GPIO_BSRR_BS_11                  GPIO_BSRR_BS11\n#define GPIO_BSRR_BS_12                  GPIO_BSRR_BS12\n#define GPIO_BSRR_BS_13                  GPIO_BSRR_BS13\n#define GPIO_BSRR_BS_14                  GPIO_BSRR_BS14\n#define GPIO_BSRR_BS_15                  GPIO_BSRR_BS15\n#define GPIO_BSRR_BR_0                   GPIO_BSRR_BR0\n#define GPIO_BSRR_BR_1                   GPIO_BSRR_BR1\n#define GPIO_BSRR_BR_2                   GPIO_BSRR_BR2\n#define GPIO_BSRR_BR_3                   GPIO_BSRR_BR3\n#define GPIO_BSRR_BR_4                   GPIO_BSRR_BR4\n#define GPIO_BSRR_BR_5                   GPIO_BSRR_BR5\n#define GPIO_BSRR_BR_6                   GPIO_BSRR_BR6\n#define GPIO_BSRR_BR_7                   GPIO_BSRR_BR7\n#define GPIO_BSRR_BR_8                   GPIO_BSRR_BR8\n#define GPIO_BSRR_BR_9                   GPIO_BSRR_BR9\n#define GPIO_BSRR_BR_10                  GPIO_BSRR_BR10\n#define GPIO_BSRR_BR_11                  GPIO_BSRR_BR11\n#define GPIO_BSRR_BR_12                  GPIO_BSRR_BR12\n#define GPIO_BSRR_BR_13                  GPIO_BSRR_BR13\n#define GPIO_BSRR_BR_14                  GPIO_BSRR_BR14\n#define GPIO_BSRR_BR_15                  GPIO_BSRR_BR15\n#define GPIO_BRR_BR0                     GPIO_BSRR_BR0\n#define GPIO_BRR_BR0_Pos                 GPIO_BSRR_BR0_Pos\n#define GPIO_BRR_BR0_Msk                 GPIO_BSRR_BR0_Msk\n#define GPIO_BRR_BR1                     GPIO_BSRR_BR1\n#define GPIO_BRR_BR1_Pos                 GPIO_BSRR_BR1_Pos\n#define GPIO_BRR_BR1_Msk                 GPIO_BSRR_BR1_Msk\n#define GPIO_BRR_BR2                     GPIO_BSRR_BR2\n#define GPIO_BRR_BR2_Pos                 GPIO_BSRR_BR2_Pos\n#define GPIO_BRR_BR2_Msk                 GPIO_BSRR_BR2_Msk\n#define GPIO_BRR_BR3                     GPIO_BSRR_BR3\n#define GPIO_BRR_BR3_Pos                 GPIO_BSRR_BR3_Pos\n#define GPIO_BRR_BR3_Msk                 GPIO_BSRR_BR3_Msk\n#define GPIO_BRR_BR4                     GPIO_BSRR_BR4\n#define GPIO_BRR_BR4_Pos                 GPIO_BSRR_BR4_Pos\n#define GPIO_BRR_BR4_Msk                 GPIO_BSRR_BR4_Msk\n#define GPIO_BRR_BR5                     GPIO_BSRR_BR5\n#define GPIO_BRR_BR5_Pos                 GPIO_BSRR_BR5_Pos\n#define GPIO_BRR_BR5_Msk                 GPIO_BSRR_BR5_Msk\n#define GPIO_BRR_BR6                     GPIO_BSRR_BR6\n#define GPIO_BRR_BR6_Pos                 GPIO_BSRR_BR6_Pos\n#define GPIO_BRR_BR6_Msk                 GPIO_BSRR_BR6_Msk\n#define GPIO_BRR_BR7                     GPIO_BSRR_BR7\n#define GPIO_BRR_BR7_Pos                 GPIO_BSRR_BR7_Pos\n#define GPIO_BRR_BR7_Msk                 GPIO_BSRR_BR7_Msk\n#define GPIO_BRR_BR8                     GPIO_BSRR_BR8\n#define GPIO_BRR_BR8_Pos                 GPIO_BSRR_BR8_Pos\n#define GPIO_BRR_BR8_Msk                 GPIO_BSRR_BR8_Msk\n#define GPIO_BRR_BR9                     GPIO_BSRR_BR9\n#define GPIO_BRR_BR9_Pos                 GPIO_BSRR_BR9_Pos\n#define GPIO_BRR_BR9_Msk                 GPIO_BSRR_BR9_Msk\n#define GPIO_BRR_BR10                    GPIO_BSRR_BR10\n#define GPIO_BRR_BR10_Pos                GPIO_BSRR_BR10_Pos\n#define GPIO_BRR_BR10_Msk                GPIO_BSRR_BR10_Msk\n#define GPIO_BRR_BR11                    GPIO_BSRR_BR11\n#define GPIO_BRR_BR11_Pos                GPIO_BSRR_BR11_Pos\n#define GPIO_BRR_BR11_Msk                GPIO_BSRR_BR11_Msk\n#define GPIO_BRR_BR12                    GPIO_BSRR_BR12\n#define GPIO_BRR_BR12_Pos                GPIO_BSRR_BR12_Pos\n#define GPIO_BRR_BR12_Msk                GPIO_BSRR_BR12_Msk\n#define GPIO_BRR_BR13                    GPIO_BSRR_BR13\n#define GPIO_BRR_BR13_Pos                GPIO_BSRR_BR13_Pos\n#define GPIO_BRR_BR13_Msk                GPIO_BSRR_BR13_Msk\n#define GPIO_BRR_BR14                    GPIO_BSRR_BR14\n#define GPIO_BRR_BR14_Pos                GPIO_BSRR_BR14_Pos\n#define GPIO_BRR_BR14_Msk                GPIO_BSRR_BR14_Msk\n#define GPIO_BRR_BR15                    GPIO_BSRR_BR15\n#define GPIO_BRR_BR15_Pos                GPIO_BSRR_BR15_Pos\n#define GPIO_BRR_BR15_Msk                GPIO_BSRR_BR15_Msk\n/****************** Bit definition for GPIO_LCKR register *********************/\n#define GPIO_LCKR_LCK0_Pos               (0U)\n#define GPIO_LCKR_LCK0_Msk               (0x1UL << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */\n#define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk\n#define GPIO_LCKR_LCK1_Pos               (1U)\n#define GPIO_LCKR_LCK1_Msk               (0x1UL << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */\n#define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk\n#define GPIO_LCKR_LCK2_Pos               (2U)\n#define GPIO_LCKR_LCK2_Msk               (0x1UL << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */\n#define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk\n#define GPIO_LCKR_LCK3_Pos               (3U)\n#define GPIO_LCKR_LCK3_Msk               (0x1UL << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */\n#define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk\n#define GPIO_LCKR_LCK4_Pos               (4U)\n#define GPIO_LCKR_LCK4_Msk               (0x1UL << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */\n#define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk\n#define GPIO_LCKR_LCK5_Pos               (5U)\n#define GPIO_LCKR_LCK5_Msk               (0x1UL << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */\n#define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk\n#define GPIO_LCKR_LCK6_Pos               (6U)\n#define GPIO_LCKR_LCK6_Msk               (0x1UL << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */\n#define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk\n#define GPIO_LCKR_LCK7_Pos               (7U)\n#define GPIO_LCKR_LCK7_Msk               (0x1UL << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */\n#define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk\n#define GPIO_LCKR_LCK8_Pos               (8U)\n#define GPIO_LCKR_LCK8_Msk               (0x1UL << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */\n#define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk\n#define GPIO_LCKR_LCK9_Pos               (9U)\n#define GPIO_LCKR_LCK9_Msk               (0x1UL << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */\n#define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk\n#define GPIO_LCKR_LCK10_Pos              (10U)\n#define GPIO_LCKR_LCK10_Msk              (0x1UL << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */\n#define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk\n#define GPIO_LCKR_LCK11_Pos              (11U)\n#define GPIO_LCKR_LCK11_Msk              (0x1UL << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */\n#define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk\n#define GPIO_LCKR_LCK12_Pos              (12U)\n#define GPIO_LCKR_LCK12_Msk              (0x1UL << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */\n#define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk\n#define GPIO_LCKR_LCK13_Pos              (13U)\n#define GPIO_LCKR_LCK13_Msk              (0x1UL << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */\n#define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk\n#define GPIO_LCKR_LCK14_Pos              (14U)\n#define GPIO_LCKR_LCK14_Msk              (0x1UL << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */\n#define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk\n#define GPIO_LCKR_LCK15_Pos              (15U)\n#define GPIO_LCKR_LCK15_Msk              (0x1UL << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */\n#define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk\n#define GPIO_LCKR_LCKK_Pos               (16U)\n#define GPIO_LCKR_LCKK_Msk               (0x1UL << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */\n#define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk\n/****************** Bit definition for GPIO_AFRL register *********************/\n#define GPIO_AFRL_AFSEL0_Pos             (0U)\n#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk\n#define GPIO_AFRL_AFSEL0_0               (0x1UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRL_AFSEL0_1               (0x2UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRL_AFSEL0_2               (0x4UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRL_AFSEL0_3               (0x8UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRL_AFSEL1_Pos             (4U)\n#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk\n#define GPIO_AFRL_AFSEL1_0               (0x1UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRL_AFSEL1_1               (0x2UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRL_AFSEL1_2               (0x4UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRL_AFSEL1_3               (0x8UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRL_AFSEL2_Pos             (8U)\n#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */\n#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk\n#define GPIO_AFRL_AFSEL2_0               (0x1UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */\n#define GPIO_AFRL_AFSEL2_1               (0x2UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */\n#define GPIO_AFRL_AFSEL2_2               (0x4UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */\n#define GPIO_AFRL_AFSEL2_3               (0x8UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */\n#define GPIO_AFRL_AFSEL3_Pos             (12U)\n#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */\n#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk\n#define GPIO_AFRL_AFSEL3_0               (0x1UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */\n#define GPIO_AFRL_AFSEL3_1               (0x2UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */\n#define GPIO_AFRL_AFSEL3_2               (0x4UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */\n#define GPIO_AFRL_AFSEL3_3               (0x8UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */\n#define GPIO_AFRL_AFSEL4_Pos             (16U)\n#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */\n#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk\n#define GPIO_AFRL_AFSEL4_0               (0x1UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */\n#define GPIO_AFRL_AFSEL4_1               (0x2UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */\n#define GPIO_AFRL_AFSEL4_2               (0x4UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */\n#define GPIO_AFRL_AFSEL4_3               (0x8UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */\n#define GPIO_AFRL_AFSEL5_Pos             (20U)\n#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */\n#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk\n#define GPIO_AFRL_AFSEL5_0               (0x1UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */\n#define GPIO_AFRL_AFSEL5_1               (0x2UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */\n#define GPIO_AFRL_AFSEL5_2               (0x4UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */\n#define GPIO_AFRL_AFSEL5_3               (0x8UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */\n#define GPIO_AFRL_AFSEL6_Pos             (24U)\n#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */\n#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk\n#define GPIO_AFRL_AFSEL6_0               (0x1UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */\n#define GPIO_AFRL_AFSEL6_1               (0x2UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */\n#define GPIO_AFRL_AFSEL6_2               (0x4UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */\n#define GPIO_AFRL_AFSEL6_3               (0x8UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */\n#define GPIO_AFRL_AFSEL7_Pos             (28U)\n#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */\n#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk\n#define GPIO_AFRL_AFSEL7_0               (0x1UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */\n#define GPIO_AFRL_AFSEL7_1               (0x2UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */\n#define GPIO_AFRL_AFSEL7_2               (0x4UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */\n#define GPIO_AFRL_AFSEL7_3               (0x8UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFSEL0\n#define GPIO_AFRL_AFRL0_0                GPIO_AFRL_AFSEL0_0\n#define GPIO_AFRL_AFRL0_1                GPIO_AFRL_AFSEL0_1\n#define GPIO_AFRL_AFRL0_2                GPIO_AFRL_AFSEL0_2\n#define GPIO_AFRL_AFRL0_3                GPIO_AFRL_AFSEL0_3\n#define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFSEL1\n#define GPIO_AFRL_AFRL1_0                GPIO_AFRL_AFSEL1_0\n#define GPIO_AFRL_AFRL1_1                GPIO_AFRL_AFSEL1_1\n#define GPIO_AFRL_AFRL1_2                GPIO_AFRL_AFSEL1_2\n#define GPIO_AFRL_AFRL1_3                GPIO_AFRL_AFSEL1_3\n#define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFSEL2\n#define GPIO_AFRL_AFRL2_0                GPIO_AFRL_AFSEL2_0\n#define GPIO_AFRL_AFRL2_1                GPIO_AFRL_AFSEL2_1\n#define GPIO_AFRL_AFRL2_2                GPIO_AFRL_AFSEL2_2\n#define GPIO_AFRL_AFRL2_3                GPIO_AFRL_AFSEL2_3\n#define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFSEL3\n#define GPIO_AFRL_AFRL3_0                GPIO_AFRL_AFSEL3_0\n#define GPIO_AFRL_AFRL3_1                GPIO_AFRL_AFSEL3_1\n#define GPIO_AFRL_AFRL3_2                GPIO_AFRL_AFSEL3_2\n#define GPIO_AFRL_AFRL3_3                GPIO_AFRL_AFSEL3_3\n#define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFSEL4\n#define GPIO_AFRL_AFRL4_0                GPIO_AFRL_AFSEL4_0\n#define GPIO_AFRL_AFRL4_1                GPIO_AFRL_AFSEL4_1\n#define GPIO_AFRL_AFRL4_2                GPIO_AFRL_AFSEL4_2\n#define GPIO_AFRL_AFRL4_3                GPIO_AFRL_AFSEL4_3\n#define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFSEL5\n#define GPIO_AFRL_AFRL5_0                GPIO_AFRL_AFSEL5_0\n#define GPIO_AFRL_AFRL5_1                GPIO_AFRL_AFSEL5_1\n#define GPIO_AFRL_AFRL5_2                GPIO_AFRL_AFSEL5_2\n#define GPIO_AFRL_AFRL5_3                GPIO_AFRL_AFSEL5_3\n#define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFSEL6\n#define GPIO_AFRL_AFRL6_0                GPIO_AFRL_AFSEL6_0\n#define GPIO_AFRL_AFRL6_1                GPIO_AFRL_AFSEL6_1\n#define GPIO_AFRL_AFRL6_2                GPIO_AFRL_AFSEL6_2\n#define GPIO_AFRL_AFRL6_3                GPIO_AFRL_AFSEL6_3\n#define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFSEL7\n#define GPIO_AFRL_AFRL7_0                GPIO_AFRL_AFSEL7_0\n#define GPIO_AFRL_AFRL7_1                GPIO_AFRL_AFSEL7_1\n#define GPIO_AFRL_AFRL7_2                GPIO_AFRL_AFSEL7_2\n#define GPIO_AFRL_AFRL7_3                GPIO_AFRL_AFSEL7_3\n\n/****************** Bit definition for GPIO_AFRH register *********************/\n#define GPIO_AFRH_AFSEL8_Pos             (0U)\n#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk\n#define GPIO_AFRH_AFSEL8_0               (0x1UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRH_AFSEL8_1               (0x2UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRH_AFSEL8_2               (0x4UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRH_AFSEL8_3               (0x8UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRH_AFSEL9_Pos             (4U)\n#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk\n#define GPIO_AFRH_AFSEL9_0               (0x1UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRH_AFSEL9_1               (0x2UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRH_AFSEL9_2               (0x4UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRH_AFSEL9_3               (0x8UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRH_AFSEL10_Pos            (8U)\n#define GPIO_AFRH_AFSEL10_Msk            (0xFUL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */\n#define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk\n#define GPIO_AFRH_AFSEL10_0              (0x1UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */\n#define GPIO_AFRH_AFSEL10_1              (0x2UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */\n#define GPIO_AFRH_AFSEL10_2              (0x4UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */\n#define GPIO_AFRH_AFSEL10_3              (0x8UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */\n#define GPIO_AFRH_AFSEL11_Pos            (12U)\n#define GPIO_AFRH_AFSEL11_Msk            (0xFUL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */\n#define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk\n#define GPIO_AFRH_AFSEL11_0              (0x1UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */\n#define GPIO_AFRH_AFSEL11_1              (0x2UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */\n#define GPIO_AFRH_AFSEL11_2              (0x4UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */\n#define GPIO_AFRH_AFSEL11_3              (0x8UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */\n#define GPIO_AFRH_AFSEL12_Pos            (16U)\n#define GPIO_AFRH_AFSEL12_Msk            (0xFUL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */\n#define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk\n#define GPIO_AFRH_AFSEL12_0              (0x1UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */\n#define GPIO_AFRH_AFSEL12_1              (0x2UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */\n#define GPIO_AFRH_AFSEL12_2              (0x4UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */\n#define GPIO_AFRH_AFSEL12_3              (0x8UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */\n#define GPIO_AFRH_AFSEL13_Pos            (20U)\n#define GPIO_AFRH_AFSEL13_Msk            (0xFUL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */\n#define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk\n#define GPIO_AFRH_AFSEL13_0              (0x1UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */\n#define GPIO_AFRH_AFSEL13_1              (0x2UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */\n#define GPIO_AFRH_AFSEL13_2              (0x4UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */\n#define GPIO_AFRH_AFSEL13_3              (0x8UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */\n#define GPIO_AFRH_AFSEL14_Pos            (24U)\n#define GPIO_AFRH_AFSEL14_Msk            (0xFUL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */\n#define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk\n#define GPIO_AFRH_AFSEL14_0              (0x1UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */\n#define GPIO_AFRH_AFSEL14_1              (0x2UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */\n#define GPIO_AFRH_AFSEL14_2              (0x4UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */\n#define GPIO_AFRH_AFSEL14_3              (0x8UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */\n#define GPIO_AFRH_AFSEL15_Pos            (28U)\n#define GPIO_AFRH_AFSEL15_Msk            (0xFUL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */\n#define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk\n#define GPIO_AFRH_AFSEL15_0              (0x1UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */\n#define GPIO_AFRH_AFSEL15_1              (0x2UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */\n#define GPIO_AFRH_AFSEL15_2              (0x4UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */\n#define GPIO_AFRH_AFSEL15_3              (0x8UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFSEL8\n#define GPIO_AFRH_AFRH0_0                GPIO_AFRH_AFSEL8_0\n#define GPIO_AFRH_AFRH0_1                GPIO_AFRH_AFSEL8_1\n#define GPIO_AFRH_AFRH0_2                GPIO_AFRH_AFSEL8_2\n#define GPIO_AFRH_AFRH0_3                GPIO_AFRH_AFSEL8_3\n#define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFSEL9\n#define GPIO_AFRH_AFRH1_0                GPIO_AFRH_AFSEL9_0\n#define GPIO_AFRH_AFRH1_1                GPIO_AFRH_AFSEL9_1\n#define GPIO_AFRH_AFRH1_2                GPIO_AFRH_AFSEL9_2\n#define GPIO_AFRH_AFRH1_3                GPIO_AFRH_AFSEL9_3\n#define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFSEL10\n#define GPIO_AFRH_AFRH2_0                GPIO_AFRH_AFSEL10_0\n#define GPIO_AFRH_AFRH2_1                GPIO_AFRH_AFSEL10_1\n#define GPIO_AFRH_AFRH2_2                GPIO_AFRH_AFSEL10_2\n#define GPIO_AFRH_AFRH2_3                GPIO_AFRH_AFSEL10_3\n#define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFSEL11\n#define GPIO_AFRH_AFRH3_0                GPIO_AFRH_AFSEL11_0\n#define GPIO_AFRH_AFRH3_1                GPIO_AFRH_AFSEL11_1\n#define GPIO_AFRH_AFRH3_2                GPIO_AFRH_AFSEL11_2\n#define GPIO_AFRH_AFRH3_3                GPIO_AFRH_AFSEL11_3\n#define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFSEL12\n#define GPIO_AFRH_AFRH4_0                GPIO_AFRH_AFSEL12_0\n#define GPIO_AFRH_AFRH4_1                GPIO_AFRH_AFSEL12_1\n#define GPIO_AFRH_AFRH4_2                GPIO_AFRH_AFSEL12_2\n#define GPIO_AFRH_AFRH4_3                GPIO_AFRH_AFSEL12_3\n#define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFSEL13\n#define GPIO_AFRH_AFRH5_0                GPIO_AFRH_AFSEL13_0\n#define GPIO_AFRH_AFRH5_1                GPIO_AFRH_AFSEL13_1\n#define GPIO_AFRH_AFRH5_2                GPIO_AFRH_AFSEL13_2\n#define GPIO_AFRH_AFRH5_3                GPIO_AFRH_AFSEL13_3\n#define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFSEL14\n#define GPIO_AFRH_AFRH6_0                GPIO_AFRH_AFSEL14_0\n#define GPIO_AFRH_AFRH6_1                GPIO_AFRH_AFSEL14_1\n#define GPIO_AFRH_AFRH6_2                GPIO_AFRH_AFSEL14_2\n#define GPIO_AFRH_AFRH6_3                GPIO_AFRH_AFSEL14_3\n#define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFSEL15\n#define GPIO_AFRH_AFRH7_0                GPIO_AFRH_AFSEL15_0\n#define GPIO_AFRH_AFRH7_1                GPIO_AFRH_AFSEL15_1\n#define GPIO_AFRH_AFRH7_2                GPIO_AFRH_AFSEL15_2\n#define GPIO_AFRH_AFRH7_3                GPIO_AFRH_AFSEL15_3\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Inter-integrated Circuit Interface                    */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for I2C_CR1 register  ********************/\n#define I2C_CR1_PE_Pos            (0U)\n#define I2C_CR1_PE_Msk            (0x1UL << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */\n#define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */\n#define I2C_CR1_SMBUS_Pos         (1U)\n#define I2C_CR1_SMBUS_Msk         (0x1UL << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */\n#define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */\n#define I2C_CR1_SMBTYPE_Pos       (3U)\n#define I2C_CR1_SMBTYPE_Msk       (0x1UL << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */\n#define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */\n#define I2C_CR1_ENARP_Pos         (4U)\n#define I2C_CR1_ENARP_Msk         (0x1UL << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */\n#define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */\n#define I2C_CR1_ENPEC_Pos         (5U)\n#define I2C_CR1_ENPEC_Msk         (0x1UL << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */\n#define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */\n#define I2C_CR1_ENGC_Pos          (6U)\n#define I2C_CR1_ENGC_Msk          (0x1UL << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */\n#define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */\n#define I2C_CR1_NOSTRETCH_Pos     (7U)\n#define I2C_CR1_NOSTRETCH_Msk     (0x1UL << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */\n#define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */\n#define I2C_CR1_START_Pos         (8U)\n#define I2C_CR1_START_Msk         (0x1UL << I2C_CR1_START_Pos)                  /*!< 0x00000100 */\n#define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */\n#define I2C_CR1_STOP_Pos          (9U)\n#define I2C_CR1_STOP_Msk          (0x1UL << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */\n#define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */\n#define I2C_CR1_ACK_Pos           (10U)\n#define I2C_CR1_ACK_Msk           (0x1UL << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */\n#define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */\n#define I2C_CR1_POS_Pos           (11U)\n#define I2C_CR1_POS_Msk           (0x1UL << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */\n#define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */\n#define I2C_CR1_PEC_Pos           (12U)\n#define I2C_CR1_PEC_Msk           (0x1UL << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */\n#define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */\n#define I2C_CR1_ALERT_Pos         (13U)\n#define I2C_CR1_ALERT_Msk         (0x1UL << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */\n#define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */\n#define I2C_CR1_SWRST_Pos         (15U)\n#define I2C_CR1_SWRST_Msk         (0x1UL << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */\n#define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */\n\n/*******************  Bit definition for I2C_CR2 register  ********************/\n#define I2C_CR2_FREQ_Pos          (0U)\n#define I2C_CR2_FREQ_Msk          (0x3FUL << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */\n#define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */\n#define I2C_CR2_FREQ_0            (0x01UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */\n#define I2C_CR2_FREQ_1            (0x02UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */\n#define I2C_CR2_FREQ_2            (0x04UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */\n#define I2C_CR2_FREQ_3            (0x08UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */\n#define I2C_CR2_FREQ_4            (0x10UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */\n#define I2C_CR2_FREQ_5            (0x20UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */\n\n#define I2C_CR2_ITERREN_Pos       (8U)\n#define I2C_CR2_ITERREN_Msk       (0x1UL << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */\n#define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */\n#define I2C_CR2_ITEVTEN_Pos       (9U)\n#define I2C_CR2_ITEVTEN_Msk       (0x1UL << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */\n#define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */\n#define I2C_CR2_ITBUFEN_Pos       (10U)\n#define I2C_CR2_ITBUFEN_Msk       (0x1UL << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */\n#define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */\n#define I2C_CR2_DMAEN_Pos         (11U)\n#define I2C_CR2_DMAEN_Msk         (0x1UL << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */\n#define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */\n#define I2C_CR2_LAST_Pos          (12U)\n#define I2C_CR2_LAST_Msk          (0x1UL << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */\n#define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */\n\n/*******************  Bit definition for I2C_OAR1 register  *******************/\n#define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */\n#define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */\n\n#define I2C_OAR1_ADD0_Pos         (0U)\n#define I2C_OAR1_ADD0_Msk         (0x1UL << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */\n#define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */\n#define I2C_OAR1_ADD1_Pos         (1U)\n#define I2C_OAR1_ADD1_Msk         (0x1UL << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */\n#define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */\n#define I2C_OAR1_ADD2_Pos         (2U)\n#define I2C_OAR1_ADD2_Msk         (0x1UL << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */\n#define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */\n#define I2C_OAR1_ADD3_Pos         (3U)\n#define I2C_OAR1_ADD3_Msk         (0x1UL << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */\n#define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */\n#define I2C_OAR1_ADD4_Pos         (4U)\n#define I2C_OAR1_ADD4_Msk         (0x1UL << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */\n#define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */\n#define I2C_OAR1_ADD5_Pos         (5U)\n#define I2C_OAR1_ADD5_Msk         (0x1UL << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */\n#define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */\n#define I2C_OAR1_ADD6_Pos         (6U)\n#define I2C_OAR1_ADD6_Msk         (0x1UL << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */\n#define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */\n#define I2C_OAR1_ADD7_Pos         (7U)\n#define I2C_OAR1_ADD7_Msk         (0x1UL << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */\n#define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */\n#define I2C_OAR1_ADD8_Pos         (8U)\n#define I2C_OAR1_ADD8_Msk         (0x1UL << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */\n#define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */\n#define I2C_OAR1_ADD9_Pos         (9U)\n#define I2C_OAR1_ADD9_Msk         (0x1UL << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */\n#define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */\n\n#define I2C_OAR1_ADDMODE_Pos      (15U)\n#define I2C_OAR1_ADDMODE_Msk      (0x1UL << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */\n#define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */\n\n/*******************  Bit definition for I2C_OAR2 register  *******************/\n#define I2C_OAR2_ENDUAL_Pos       (0U)\n#define I2C_OAR2_ENDUAL_Msk       (0x1UL << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */\n#define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */\n#define I2C_OAR2_ADD2_Pos         (1U)\n#define I2C_OAR2_ADD2_Msk         (0x7FUL << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */\n#define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */\n\n/********************  Bit definition for I2C_DR register  ********************/\n#define I2C_DR_DR_Pos             (0U)\n#define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */\n#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */\n\n/*******************  Bit definition for I2C_SR1 register  ********************/\n#define I2C_SR1_SB_Pos            (0U)\n#define I2C_SR1_SB_Msk            (0x1UL << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */\n#define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */\n#define I2C_SR1_ADDR_Pos          (1U)\n#define I2C_SR1_ADDR_Msk          (0x1UL << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */\n#define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */\n#define I2C_SR1_BTF_Pos           (2U)\n#define I2C_SR1_BTF_Msk           (0x1UL << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */\n#define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */\n#define I2C_SR1_ADD10_Pos         (3U)\n#define I2C_SR1_ADD10_Msk         (0x1UL << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */\n#define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */\n#define I2C_SR1_STOPF_Pos         (4U)\n#define I2C_SR1_STOPF_Msk         (0x1UL << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */\n#define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */\n#define I2C_SR1_RXNE_Pos          (6U)\n#define I2C_SR1_RXNE_Msk          (0x1UL << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */\n#define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */\n#define I2C_SR1_TXE_Pos           (7U)\n#define I2C_SR1_TXE_Msk           (0x1UL << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */\n#define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */\n#define I2C_SR1_BERR_Pos          (8U)\n#define I2C_SR1_BERR_Msk          (0x1UL << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */\n#define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */\n#define I2C_SR1_ARLO_Pos          (9U)\n#define I2C_SR1_ARLO_Msk          (0x1UL << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */\n#define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */\n#define I2C_SR1_AF_Pos            (10U)\n#define I2C_SR1_AF_Msk            (0x1UL << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */\n#define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */\n#define I2C_SR1_OVR_Pos           (11U)\n#define I2C_SR1_OVR_Msk           (0x1UL << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */\n#define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */\n#define I2C_SR1_PECERR_Pos        (12U)\n#define I2C_SR1_PECERR_Msk        (0x1UL << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */\n#define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */\n#define I2C_SR1_TIMEOUT_Pos       (14U)\n#define I2C_SR1_TIMEOUT_Msk       (0x1UL << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */\n#define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */\n#define I2C_SR1_SMBALERT_Pos      (15U)\n#define I2C_SR1_SMBALERT_Msk      (0x1UL << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */\n#define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */\n\n/*******************  Bit definition for I2C_SR2 register  ********************/\n#define I2C_SR2_MSL_Pos           (0U)\n#define I2C_SR2_MSL_Msk           (0x1UL << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */\n#define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */\n#define I2C_SR2_BUSY_Pos          (1U)\n#define I2C_SR2_BUSY_Msk          (0x1UL << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */\n#define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */\n#define I2C_SR2_TRA_Pos           (2U)\n#define I2C_SR2_TRA_Msk           (0x1UL << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */\n#define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */\n#define I2C_SR2_GENCALL_Pos       (4U)\n#define I2C_SR2_GENCALL_Msk       (0x1UL << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */\n#define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */\n#define I2C_SR2_SMBDEFAULT_Pos    (5U)\n#define I2C_SR2_SMBDEFAULT_Msk    (0x1UL << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */\n#define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */\n#define I2C_SR2_SMBHOST_Pos       (6U)\n#define I2C_SR2_SMBHOST_Msk       (0x1UL << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */\n#define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */\n#define I2C_SR2_DUALF_Pos         (7U)\n#define I2C_SR2_DUALF_Msk         (0x1UL << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */\n#define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */\n#define I2C_SR2_PEC_Pos           (8U)\n#define I2C_SR2_PEC_Msk           (0xFFUL << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */\n#define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */\n\n/*******************  Bit definition for I2C_CCR register  ********************/\n#define I2C_CCR_CCR_Pos           (0U)\n#define I2C_CCR_CCR_Msk           (0xFFFUL << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */\n#define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */\n#define I2C_CCR_DUTY_Pos          (14U)\n#define I2C_CCR_DUTY_Msk          (0x1UL << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */\n#define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */\n#define I2C_CCR_FS_Pos            (15U)\n#define I2C_CCR_FS_Msk            (0x1UL << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */\n#define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */\n\n/******************  Bit definition for I2C_TRISE register  *******************/\n#define I2C_TRISE_TRISE_Pos       (0U)\n#define I2C_TRISE_TRISE_Msk       (0x3FUL << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */\n#define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */\n\n/******************  Bit definition for I2C_FLTR register  *******************/\n#define I2C_FLTR_DNF_Pos          (0U)\n#define I2C_FLTR_DNF_Msk          (0xFUL << I2C_FLTR_DNF_Pos)                   /*!< 0x0000000F */\n#define I2C_FLTR_DNF              I2C_FLTR_DNF_Msk                             /*!<Digital Noise Filter */\n#define I2C_FLTR_ANOFF_Pos        (4U)\n#define I2C_FLTR_ANOFF_Msk        (0x1UL << I2C_FLTR_ANOFF_Pos)                 /*!< 0x00000010 */\n#define I2C_FLTR_ANOFF            I2C_FLTR_ANOFF_Msk                           /*!<Analog Noise Filter OFF */\n\n/******************************************************************************/\n/*                                                                            */\n/*        Fast Mode Plus Inter-integrated Circuit Interface (I2C)             */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for I2C_CR1 register  *******************/\n#define FMPI2C_CR1_PE_Pos               (0U)\n#define FMPI2C_CR1_PE_Msk               (0x1UL << FMPI2C_CR1_PE_Pos)            /*!< 0x00000001 */\n#define FMPI2C_CR1_PE                   FMPI2C_CR1_PE_Msk                      /*!< Peripheral enable                   */\n#define FMPI2C_CR1_TXIE_Pos             (1U)\n#define FMPI2C_CR1_TXIE_Msk             (0x1UL << FMPI2C_CR1_TXIE_Pos)          /*!< 0x00000002 */\n#define FMPI2C_CR1_TXIE                 FMPI2C_CR1_TXIE_Msk                    /*!< TX interrupt enable                 */\n#define FMPI2C_CR1_RXIE_Pos             (2U)\n#define FMPI2C_CR1_RXIE_Msk             (0x1UL << FMPI2C_CR1_RXIE_Pos)          /*!< 0x00000004 */\n#define FMPI2C_CR1_RXIE                 FMPI2C_CR1_RXIE_Msk                    /*!< RX interrupt enable                 */\n#define FMPI2C_CR1_ADDRIE_Pos           (3U)\n#define FMPI2C_CR1_ADDRIE_Msk           (0x1UL << FMPI2C_CR1_ADDRIE_Pos)        /*!< 0x00000008 */\n#define FMPI2C_CR1_ADDRIE               FMPI2C_CR1_ADDRIE_Msk                  /*!< Address match interrupt enable      */\n#define FMPI2C_CR1_NACKIE_Pos           (4U)\n#define FMPI2C_CR1_NACKIE_Msk           (0x1UL << FMPI2C_CR1_NACKIE_Pos)        /*!< 0x00000010 */\n#define FMPI2C_CR1_NACKIE               FMPI2C_CR1_NACKIE_Msk                  /*!< NACK received interrupt enable      */\n#define FMPI2C_CR1_STOPIE_Pos           (5U)\n#define FMPI2C_CR1_STOPIE_Msk           (0x1UL << FMPI2C_CR1_STOPIE_Pos)        /*!< 0x00000020 */\n#define FMPI2C_CR1_STOPIE               FMPI2C_CR1_STOPIE_Msk                  /*!< STOP detection interrupt enable     */\n#define FMPI2C_CR1_TCIE_Pos             (6U)\n#define FMPI2C_CR1_TCIE_Msk             (0x1UL << FMPI2C_CR1_TCIE_Pos)          /*!< 0x00000040 */\n#define FMPI2C_CR1_TCIE                 FMPI2C_CR1_TCIE_Msk                    /*!< Transfer complete interrupt enable  */\n#define FMPI2C_CR1_ERRIE_Pos            (7U)\n#define FMPI2C_CR1_ERRIE_Msk            (0x1UL << FMPI2C_CR1_ERRIE_Pos)         /*!< 0x00000080 */\n#define FMPI2C_CR1_ERRIE                FMPI2C_CR1_ERRIE_Msk                   /*!< Errors interrupt enable             */\n#define FMPI2C_CR1_DNF_Pos              (8U)\n#define FMPI2C_CR1_DNF_Msk              (0xFUL << FMPI2C_CR1_DNF_Pos)           /*!< 0x00000F00 */\n#define FMPI2C_CR1_DNF                  FMPI2C_CR1_DNF_Msk                     /*!< Digital noise filter                */\n#define FMPI2C_CR1_ANFOFF_Pos           (12U)\n#define FMPI2C_CR1_ANFOFF_Msk           (0x1UL << FMPI2C_CR1_ANFOFF_Pos)        /*!< 0x00001000 */\n#define FMPI2C_CR1_ANFOFF               FMPI2C_CR1_ANFOFF_Msk                  /*!< Analog noise filter OFF             */\n#define FMPI2C_CR1_TXDMAEN_Pos          (14U)\n#define FMPI2C_CR1_TXDMAEN_Msk          (0x1UL << FMPI2C_CR1_TXDMAEN_Pos)       /*!< 0x00004000 */\n#define FMPI2C_CR1_TXDMAEN              FMPI2C_CR1_TXDMAEN_Msk                 /*!< DMA transmission requests enable    */\n#define FMPI2C_CR1_RXDMAEN_Pos          (15U)\n#define FMPI2C_CR1_RXDMAEN_Msk          (0x1UL << FMPI2C_CR1_RXDMAEN_Pos)       /*!< 0x00008000 */\n#define FMPI2C_CR1_RXDMAEN              FMPI2C_CR1_RXDMAEN_Msk                 /*!< DMA reception requests enable       */\n#define FMPI2C_CR1_SBC_Pos              (16U)\n#define FMPI2C_CR1_SBC_Msk              (0x1UL << FMPI2C_CR1_SBC_Pos)           /*!< 0x00010000 */\n#define FMPI2C_CR1_SBC                  FMPI2C_CR1_SBC_Msk                     /*!< Slave byte control                  */\n#define FMPI2C_CR1_NOSTRETCH_Pos        (17U)\n#define FMPI2C_CR1_NOSTRETCH_Msk        (0x1UL << FMPI2C_CR1_NOSTRETCH_Pos)     /*!< 0x00020000 */\n#define FMPI2C_CR1_NOSTRETCH            FMPI2C_CR1_NOSTRETCH_Msk               /*!< Clock stretching disable            */\n#define FMPI2C_CR1_GCEN_Pos             (19U)\n#define FMPI2C_CR1_GCEN_Msk             (0x1UL << FMPI2C_CR1_GCEN_Pos)          /*!< 0x00080000 */\n#define FMPI2C_CR1_GCEN                 FMPI2C_CR1_GCEN_Msk                    /*!< General call enable                 */\n#define FMPI2C_CR1_SMBHEN_Pos           (20U)\n#define FMPI2C_CR1_SMBHEN_Msk           (0x1UL << FMPI2C_CR1_SMBHEN_Pos)        /*!< 0x00100000 */\n#define FMPI2C_CR1_SMBHEN               FMPI2C_CR1_SMBHEN_Msk                  /*!< SMBus host address enable           */\n#define FMPI2C_CR1_SMBDEN_Pos           (21U)\n#define FMPI2C_CR1_SMBDEN_Msk           (0x1UL << FMPI2C_CR1_SMBDEN_Pos)        /*!< 0x00200000 */\n#define FMPI2C_CR1_SMBDEN               FMPI2C_CR1_SMBDEN_Msk                  /*!< SMBus device default address enable */\n#define FMPI2C_CR1_ALERTEN_Pos          (22U)\n#define FMPI2C_CR1_ALERTEN_Msk          (0x1UL << FMPI2C_CR1_ALERTEN_Pos)       /*!< 0x00400000 */\n#define FMPI2C_CR1_ALERTEN              FMPI2C_CR1_ALERTEN_Msk                 /*!< SMBus alert enable                  */\n#define FMPI2C_CR1_PECEN_Pos            (23U)\n#define FMPI2C_CR1_PECEN_Msk            (0x1UL << FMPI2C_CR1_PECEN_Pos)         /*!< 0x00800000 */\n#define FMPI2C_CR1_PECEN                FMPI2C_CR1_PECEN_Msk                   /*!< PEC enable                          */\n\n/* Legacy Defines */\n#define FMPI2C_CR1_DFN_Pos              FMPI2C_CR1_DNF_Pos\n#define FMPI2C_CR1_DFN_Msk              FMPI2C_CR1_DNF_Msk\n#define FMPI2C_CR1_DFN                  FMPI2C_CR1_DNF\n/******************  Bit definition for I2C_CR2 register  ********************/\n#define FMPI2C_CR2_SADD_Pos             (0U)\n#define FMPI2C_CR2_SADD_Msk             (0x3FFUL << FMPI2C_CR2_SADD_Pos)        /*!< 0x000003FF */\n#define FMPI2C_CR2_SADD                 FMPI2C_CR2_SADD_Msk                    /*!< Slave address (master mode)                             */\n#define FMPI2C_CR2_RD_WRN_Pos           (10U)\n#define FMPI2C_CR2_RD_WRN_Msk           (0x1UL << FMPI2C_CR2_RD_WRN_Pos)        /*!< 0x00000400 */\n#define FMPI2C_CR2_RD_WRN               FMPI2C_CR2_RD_WRN_Msk                  /*!< Transfer direction (master mode)                        */\n#define FMPI2C_CR2_ADD10_Pos            (11U)\n#define FMPI2C_CR2_ADD10_Msk            (0x1UL << FMPI2C_CR2_ADD10_Pos)         /*!< 0x00000800 */\n#define FMPI2C_CR2_ADD10                FMPI2C_CR2_ADD10_Msk                   /*!< 10-bit addressing mode (master mode)                    */\n#define FMPI2C_CR2_HEAD10R_Pos          (12U)\n#define FMPI2C_CR2_HEAD10R_Msk          (0x1UL << FMPI2C_CR2_HEAD10R_Pos)       /*!< 0x00001000 */\n#define FMPI2C_CR2_HEAD10R              FMPI2C_CR2_HEAD10R_Msk                 /*!< 10-bit address header only read direction (master mode) */\n#define FMPI2C_CR2_START_Pos            (13U)\n#define FMPI2C_CR2_START_Msk            (0x1UL << FMPI2C_CR2_START_Pos)         /*!< 0x00002000 */\n#define FMPI2C_CR2_START                FMPI2C_CR2_START_Msk                   /*!< START generation                                        */\n#define FMPI2C_CR2_STOP_Pos             (14U)\n#define FMPI2C_CR2_STOP_Msk             (0x1UL << FMPI2C_CR2_STOP_Pos)          /*!< 0x00004000 */\n#define FMPI2C_CR2_STOP                 FMPI2C_CR2_STOP_Msk                    /*!< STOP generation (master mode)                           */\n#define FMPI2C_CR2_NACK_Pos             (15U)\n#define FMPI2C_CR2_NACK_Msk             (0x1UL << FMPI2C_CR2_NACK_Pos)          /*!< 0x00008000 */\n#define FMPI2C_CR2_NACK                 FMPI2C_CR2_NACK_Msk                    /*!< NACK generation (slave mode)                            */\n#define FMPI2C_CR2_NBYTES_Pos           (16U)\n#define FMPI2C_CR2_NBYTES_Msk           (0xFFUL << FMPI2C_CR2_NBYTES_Pos)       /*!< 0x00FF0000 */\n#define FMPI2C_CR2_NBYTES               FMPI2C_CR2_NBYTES_Msk                  /*!< Number of bytes                                         */\n#define FMPI2C_CR2_RELOAD_Pos           (24U)\n#define FMPI2C_CR2_RELOAD_Msk           (0x1UL << FMPI2C_CR2_RELOAD_Pos)        /*!< 0x01000000 */\n#define FMPI2C_CR2_RELOAD               FMPI2C_CR2_RELOAD_Msk                  /*!< NBYTES reload mode                                      */\n#define FMPI2C_CR2_AUTOEND_Pos          (25U)\n#define FMPI2C_CR2_AUTOEND_Msk          (0x1UL << FMPI2C_CR2_AUTOEND_Pos)       /*!< 0x02000000 */\n#define FMPI2C_CR2_AUTOEND              FMPI2C_CR2_AUTOEND_Msk                 /*!< Automatic end mode (master mode)                        */\n#define FMPI2C_CR2_PECBYTE_Pos          (26U)\n#define FMPI2C_CR2_PECBYTE_Msk          (0x1UL << FMPI2C_CR2_PECBYTE_Pos)       /*!< 0x04000000 */\n#define FMPI2C_CR2_PECBYTE              FMPI2C_CR2_PECBYTE_Msk                 /*!< Packet error checking byte                              */\n\n/*******************  Bit definition for I2C_OAR1 register  ******************/\n#define FMPI2C_OAR1_OA1_Pos             (0U)\n#define FMPI2C_OAR1_OA1_Msk             (0x3FFUL << FMPI2C_OAR1_OA1_Pos)        /*!< 0x000003FF */\n#define FMPI2C_OAR1_OA1                 FMPI2C_OAR1_OA1_Msk                    /*!< Interface own address 1   */\n#define FMPI2C_OAR1_OA1MODE_Pos         (10U)\n#define FMPI2C_OAR1_OA1MODE_Msk         (0x1UL << FMPI2C_OAR1_OA1MODE_Pos)      /*!< 0x00000400 */\n#define FMPI2C_OAR1_OA1MODE             FMPI2C_OAR1_OA1MODE_Msk                /*!< Own address 1 10-bit mode */\n#define FMPI2C_OAR1_OA1EN_Pos           (15U)\n#define FMPI2C_OAR1_OA1EN_Msk           (0x1UL << FMPI2C_OAR1_OA1EN_Pos)        /*!< 0x00008000 */\n#define FMPI2C_OAR1_OA1EN               FMPI2C_OAR1_OA1EN_Msk                  /*!< Own address 1 enable      */\n\n/*******************  Bit definition for I2C_OAR2 register  ******************/\n#define FMPI2C_OAR2_OA2_Pos             (1U)\n#define FMPI2C_OAR2_OA2_Msk             (0x7FUL << FMPI2C_OAR2_OA2_Pos)         /*!< 0x000000FE */\n#define FMPI2C_OAR2_OA2                 FMPI2C_OAR2_OA2_Msk                    /*!< Interface own address 2 */\n#define FMPI2C_OAR2_OA2MSK_Pos          (8U)\n#define FMPI2C_OAR2_OA2MSK_Msk          (0x7UL << FMPI2C_OAR2_OA2MSK_Pos)       /*!< 0x00000700 */\n#define FMPI2C_OAR2_OA2MSK              FMPI2C_OAR2_OA2MSK_Msk                 /*!< Own address 2 masks     */\n#define FMPI2C_OAR2_OA2EN_Pos           (15U)\n#define FMPI2C_OAR2_OA2EN_Msk           (0x1UL << FMPI2C_OAR2_OA2EN_Pos)        /*!< 0x00008000 */\n#define FMPI2C_OAR2_OA2EN               FMPI2C_OAR2_OA2EN_Msk                  /*!< Own address 2 enable    */\n\n/*******************  Bit definition for I2C_TIMINGR register *******************/\n#define FMPI2C_TIMINGR_SCLL_Pos         (0U)\n#define FMPI2C_TIMINGR_SCLL_Msk         (0xFFUL << FMPI2C_TIMINGR_SCLL_Pos)     /*!< 0x000000FF */\n#define FMPI2C_TIMINGR_SCLL             FMPI2C_TIMINGR_SCLL_Msk                /*!< SCL low period (master mode)  */\n#define FMPI2C_TIMINGR_SCLH_Pos         (8U)\n#define FMPI2C_TIMINGR_SCLH_Msk         (0xFFUL << FMPI2C_TIMINGR_SCLH_Pos)     /*!< 0x0000FF00 */\n#define FMPI2C_TIMINGR_SCLH             FMPI2C_TIMINGR_SCLH_Msk                /*!< SCL high period (master mode) */\n#define FMPI2C_TIMINGR_SDADEL_Pos       (16U)\n#define FMPI2C_TIMINGR_SDADEL_Msk       (0xFUL << FMPI2C_TIMINGR_SDADEL_Pos)    /*!< 0x000F0000 */\n#define FMPI2C_TIMINGR_SDADEL           FMPI2C_TIMINGR_SDADEL_Msk              /*!< Data hold time                */\n#define FMPI2C_TIMINGR_SCLDEL_Pos       (20U)\n#define FMPI2C_TIMINGR_SCLDEL_Msk       (0xFUL << FMPI2C_TIMINGR_SCLDEL_Pos)    /*!< 0x00F00000 */\n#define FMPI2C_TIMINGR_SCLDEL           FMPI2C_TIMINGR_SCLDEL_Msk              /*!< Data setup time               */\n#define FMPI2C_TIMINGR_PRESC_Pos        (28U)\n#define FMPI2C_TIMINGR_PRESC_Msk        (0xFUL << FMPI2C_TIMINGR_PRESC_Pos)     /*!< 0xF0000000 */\n#define FMPI2C_TIMINGR_PRESC            FMPI2C_TIMINGR_PRESC_Msk               /*!< Timings prescaler             */\n\n/******************* Bit definition for I2C_TIMEOUTR register *******************/\n#define FMPI2C_TIMEOUTR_TIMEOUTA_Pos    (0U)\n#define FMPI2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */\n#define FMPI2C_TIMEOUTR_TIMEOUTA        FMPI2C_TIMEOUTR_TIMEOUTA_Msk           /*!< Bus timeout A                 */\n#define FMPI2C_TIMEOUTR_TIDLE_Pos       (12U)\n#define FMPI2C_TIMEOUTR_TIDLE_Msk       (0x1UL << FMPI2C_TIMEOUTR_TIDLE_Pos)    /*!< 0x00001000 */\n#define FMPI2C_TIMEOUTR_TIDLE           FMPI2C_TIMEOUTR_TIDLE_Msk              /*!< Idle clock timeout detection  */\n#define FMPI2C_TIMEOUTR_TIMOUTEN_Pos    (15U)\n#define FMPI2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */\n#define FMPI2C_TIMEOUTR_TIMOUTEN        FMPI2C_TIMEOUTR_TIMOUTEN_Msk           /*!< Clock timeout enable          */\n#define FMPI2C_TIMEOUTR_TIMEOUTB_Pos    (16U)\n#define FMPI2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */\n#define FMPI2C_TIMEOUTR_TIMEOUTB        FMPI2C_TIMEOUTR_TIMEOUTB_Msk           /*!< Bus timeout B                 */\n#define FMPI2C_TIMEOUTR_TEXTEN_Pos      (31U)\n#define FMPI2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << FMPI2C_TIMEOUTR_TEXTEN_Pos)   /*!< 0x80000000 */\n#define FMPI2C_TIMEOUTR_TEXTEN          FMPI2C_TIMEOUTR_TEXTEN_Msk             /*!< Extended clock timeout enable */\n\n/******************  Bit definition for I2C_ISR register  *********************/\n#define FMPI2C_ISR_TXE_Pos              (0U)\n#define FMPI2C_ISR_TXE_Msk              (0x1UL << FMPI2C_ISR_TXE_Pos)           /*!< 0x00000001 */\n#define FMPI2C_ISR_TXE                  FMPI2C_ISR_TXE_Msk                     /*!< Transmit data register empty     */\n#define FMPI2C_ISR_TXIS_Pos             (1U)\n#define FMPI2C_ISR_TXIS_Msk             (0x1UL << FMPI2C_ISR_TXIS_Pos)          /*!< 0x00000002 */\n#define FMPI2C_ISR_TXIS                 FMPI2C_ISR_TXIS_Msk                    /*!< Transmit interrupt status        */\n#define FMPI2C_ISR_RXNE_Pos             (2U)\n#define FMPI2C_ISR_RXNE_Msk             (0x1UL << FMPI2C_ISR_RXNE_Pos)          /*!< 0x00000004 */\n#define FMPI2C_ISR_RXNE                 FMPI2C_ISR_RXNE_Msk                    /*!< Receive data register not empty  */\n#define FMPI2C_ISR_ADDR_Pos             (3U)\n#define FMPI2C_ISR_ADDR_Msk             (0x1UL << FMPI2C_ISR_ADDR_Pos)          /*!< 0x00000008 */\n#define FMPI2C_ISR_ADDR                 FMPI2C_ISR_ADDR_Msk                    /*!< Address matched (slave mode)     */\n#define FMPI2C_ISR_NACKF_Pos            (4U)\n#define FMPI2C_ISR_NACKF_Msk            (0x1UL << FMPI2C_ISR_NACKF_Pos)         /*!< 0x00000010 */\n#define FMPI2C_ISR_NACKF                FMPI2C_ISR_NACKF_Msk                   /*!< NACK received flag               */\n#define FMPI2C_ISR_STOPF_Pos            (5U)\n#define FMPI2C_ISR_STOPF_Msk            (0x1UL << FMPI2C_ISR_STOPF_Pos)         /*!< 0x00000020 */\n#define FMPI2C_ISR_STOPF                FMPI2C_ISR_STOPF_Msk                   /*!< STOP detection flag              */\n#define FMPI2C_ISR_TC_Pos               (6U)\n#define FMPI2C_ISR_TC_Msk               (0x1UL << FMPI2C_ISR_TC_Pos)            /*!< 0x00000040 */\n#define FMPI2C_ISR_TC                   FMPI2C_ISR_TC_Msk                      /*!< Transfer complete (master mode)  */\n#define FMPI2C_ISR_TCR_Pos              (7U)\n#define FMPI2C_ISR_TCR_Msk              (0x1UL << FMPI2C_ISR_TCR_Pos)           /*!< 0x00000080 */\n#define FMPI2C_ISR_TCR                  FMPI2C_ISR_TCR_Msk                     /*!< Transfer complete reload         */\n#define FMPI2C_ISR_BERR_Pos             (8U)\n#define FMPI2C_ISR_BERR_Msk             (0x1UL << FMPI2C_ISR_BERR_Pos)          /*!< 0x00000100 */\n#define FMPI2C_ISR_BERR                 FMPI2C_ISR_BERR_Msk                    /*!< Bus error                        */\n#define FMPI2C_ISR_ARLO_Pos             (9U)\n#define FMPI2C_ISR_ARLO_Msk             (0x1UL << FMPI2C_ISR_ARLO_Pos)          /*!< 0x00000200 */\n#define FMPI2C_ISR_ARLO                 FMPI2C_ISR_ARLO_Msk                    /*!< Arbitration lost                 */\n#define FMPI2C_ISR_OVR_Pos              (10U)\n#define FMPI2C_ISR_OVR_Msk              (0x1UL << FMPI2C_ISR_OVR_Pos)           /*!< 0x00000400 */\n#define FMPI2C_ISR_OVR                  FMPI2C_ISR_OVR_Msk                     /*!< Overrun/Underrun                 */\n#define FMPI2C_ISR_PECERR_Pos           (11U)\n#define FMPI2C_ISR_PECERR_Msk           (0x1UL << FMPI2C_ISR_PECERR_Pos)        /*!< 0x00000800 */\n#define FMPI2C_ISR_PECERR               FMPI2C_ISR_PECERR_Msk                  /*!< PEC error in reception           */\n#define FMPI2C_ISR_TIMEOUT_Pos          (12U)\n#define FMPI2C_ISR_TIMEOUT_Msk          (0x1UL << FMPI2C_ISR_TIMEOUT_Pos)       /*!< 0x00001000 */\n#define FMPI2C_ISR_TIMEOUT              FMPI2C_ISR_TIMEOUT_Msk                 /*!< Timeout or Tlow detection flag   */\n#define FMPI2C_ISR_ALERT_Pos            (13U)\n#define FMPI2C_ISR_ALERT_Msk            (0x1UL << FMPI2C_ISR_ALERT_Pos)         /*!< 0x00002000 */\n#define FMPI2C_ISR_ALERT                FMPI2C_ISR_ALERT_Msk                   /*!< SMBus alert                      */\n#define FMPI2C_ISR_BUSY_Pos             (15U)\n#define FMPI2C_ISR_BUSY_Msk             (0x1UL << FMPI2C_ISR_BUSY_Pos)          /*!< 0x00008000 */\n#define FMPI2C_ISR_BUSY                 FMPI2C_ISR_BUSY_Msk                    /*!< Bus busy                         */\n#define FMPI2C_ISR_DIR_Pos              (16U)\n#define FMPI2C_ISR_DIR_Msk              (0x1UL << FMPI2C_ISR_DIR_Pos)           /*!< 0x00010000 */\n#define FMPI2C_ISR_DIR                  FMPI2C_ISR_DIR_Msk                     /*!< Transfer direction (slave mode)  */\n#define FMPI2C_ISR_ADDCODE_Pos          (17U)\n#define FMPI2C_ISR_ADDCODE_Msk          (0x7FUL << FMPI2C_ISR_ADDCODE_Pos)      /*!< 0x00FE0000 */\n#define FMPI2C_ISR_ADDCODE              FMPI2C_ISR_ADDCODE_Msk                 /*!< Address match code (slave mode)  */\n\n/******************  Bit definition for I2C_ICR register  *********************/\n#define FMPI2C_ICR_ADDRCF_Pos           (3U)\n#define FMPI2C_ICR_ADDRCF_Msk           (0x1UL << FMPI2C_ICR_ADDRCF_Pos)        /*!< 0x00000008 */\n#define FMPI2C_ICR_ADDRCF               FMPI2C_ICR_ADDRCF_Msk                  /*!< Address matched clear flag  */\n#define FMPI2C_ICR_NACKCF_Pos           (4U)\n#define FMPI2C_ICR_NACKCF_Msk           (0x1UL << FMPI2C_ICR_NACKCF_Pos)        /*!< 0x00000010 */\n#define FMPI2C_ICR_NACKCF               FMPI2C_ICR_NACKCF_Msk                  /*!< NACK clear flag             */\n#define FMPI2C_ICR_STOPCF_Pos           (5U)\n#define FMPI2C_ICR_STOPCF_Msk           (0x1UL << FMPI2C_ICR_STOPCF_Pos)        /*!< 0x00000020 */\n#define FMPI2C_ICR_STOPCF               FMPI2C_ICR_STOPCF_Msk                  /*!< STOP detection clear flag   */\n#define FMPI2C_ICR_BERRCF_Pos           (8U)\n#define FMPI2C_ICR_BERRCF_Msk           (0x1UL << FMPI2C_ICR_BERRCF_Pos)        /*!< 0x00000100 */\n#define FMPI2C_ICR_BERRCF               FMPI2C_ICR_BERRCF_Msk                  /*!< Bus error clear flag        */\n#define FMPI2C_ICR_ARLOCF_Pos           (9U)\n#define FMPI2C_ICR_ARLOCF_Msk           (0x1UL << FMPI2C_ICR_ARLOCF_Pos)        /*!< 0x00000200 */\n#define FMPI2C_ICR_ARLOCF               FMPI2C_ICR_ARLOCF_Msk                  /*!< Arbitration lost clear flag */\n#define FMPI2C_ICR_OVRCF_Pos            (10U)\n#define FMPI2C_ICR_OVRCF_Msk            (0x1UL << FMPI2C_ICR_OVRCF_Pos)         /*!< 0x00000400 */\n#define FMPI2C_ICR_OVRCF                FMPI2C_ICR_OVRCF_Msk                   /*!< Overrun/Underrun clear flag */\n#define FMPI2C_ICR_PECCF_Pos            (11U)\n#define FMPI2C_ICR_PECCF_Msk            (0x1UL << FMPI2C_ICR_PECCF_Pos)         /*!< 0x00000800 */\n#define FMPI2C_ICR_PECCF                FMPI2C_ICR_PECCF_Msk                   /*!< PAC error clear flag        */\n#define FMPI2C_ICR_TIMOUTCF_Pos         (12U)\n#define FMPI2C_ICR_TIMOUTCF_Msk         (0x1UL << FMPI2C_ICR_TIMOUTCF_Pos)      /*!< 0x00001000 */\n#define FMPI2C_ICR_TIMOUTCF             FMPI2C_ICR_TIMOUTCF_Msk                /*!< Timeout clear flag          */\n#define FMPI2C_ICR_ALERTCF_Pos          (13U)\n#define FMPI2C_ICR_ALERTCF_Msk          (0x1UL << FMPI2C_ICR_ALERTCF_Pos)       /*!< 0x00002000 */\n#define FMPI2C_ICR_ALERTCF              FMPI2C_ICR_ALERTCF_Msk                 /*!< Alert clear flag            */\n\n/******************  Bit definition for I2C_PECR register  *********************/\n#define FMPI2C_PECR_PEC_Pos             (0U)\n#define FMPI2C_PECR_PEC_Msk             (0xFFUL << FMPI2C_PECR_PEC_Pos)         /*!< 0x000000FF */\n#define FMPI2C_PECR_PEC                 FMPI2C_PECR_PEC_Msk                    /*!< PEC register */\n\n/******************  Bit definition for I2C_RXDR register  *********************/\n#define FMPI2C_RXDR_RXDATA_Pos          (0U)\n#define FMPI2C_RXDR_RXDATA_Msk          (0xFFUL << FMPI2C_RXDR_RXDATA_Pos)      /*!< 0x000000FF */\n#define FMPI2C_RXDR_RXDATA              FMPI2C_RXDR_RXDATA_Msk                 /*!< 8-bit receive data */\n\n/******************  Bit definition for I2C_TXDR register  *********************/\n#define FMPI2C_TXDR_TXDATA_Pos          (0U)\n#define FMPI2C_TXDR_TXDATA_Msk          (0xFFUL << FMPI2C_TXDR_TXDATA_Pos)      /*!< 0x000000FF */\n#define FMPI2C_TXDR_TXDATA              FMPI2C_TXDR_TXDATA_Msk                 /*!< 8-bit transmit data */\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Independent WATCHDOG                             */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define IWDG_KR_KEY_Pos     (0U)\n#define IWDG_KR_KEY_Msk     (0xFFFFUL << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */\n#define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */\n\n/*******************  Bit definition for IWDG_PR register  ********************/\n#define IWDG_PR_PR_Pos      (0U)\n#define IWDG_PR_PR_Msk      (0x7UL << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */\n#define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */\n#define IWDG_PR_PR_0        (0x1UL << IWDG_PR_PR_Pos)                           /*!< 0x01 */\n#define IWDG_PR_PR_1        (0x2UL << IWDG_PR_PR_Pos)                           /*!< 0x02 */\n#define IWDG_PR_PR_2        (0x4UL << IWDG_PR_PR_Pos)                           /*!< 0x04 */\n\n/*******************  Bit definition for IWDG_RLR register  *******************/\n#define IWDG_RLR_RL_Pos     (0U)\n#define IWDG_RLR_RL_Msk     (0xFFFUL << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */\n#define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */\n\n/*******************  Bit definition for IWDG_SR register  ********************/\n#define IWDG_SR_PVU_Pos     (0U)\n#define IWDG_SR_PVU_Msk     (0x1UL << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */\n#define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */\n#define IWDG_SR_RVU_Pos     (1U)\n#define IWDG_SR_RVU_Msk     (0x1UL << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */\n#define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                             Power Control                                  */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for PWR_CR register  ********************/\n#define PWR_CR_LPDS_Pos        (0U)\n#define PWR_CR_LPDS_Msk        (0x1UL << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */\n#define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */\n#define PWR_CR_PDDS_Pos        (1U)\n#define PWR_CR_PDDS_Msk        (0x1UL << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */\n#define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */\n#define PWR_CR_CWUF_Pos        (2U)\n#define PWR_CR_CWUF_Msk        (0x1UL << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */\n#define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */\n#define PWR_CR_CSBF_Pos        (3U)\n#define PWR_CR_CSBF_Msk        (0x1UL << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */\n#define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */\n#define PWR_CR_PVDE_Pos        (4U)\n#define PWR_CR_PVDE_Msk        (0x1UL << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */\n#define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */\n\n#define PWR_CR_PLS_Pos         (5U)\n#define PWR_CR_PLS_Msk         (0x7UL << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */\n#define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */\n#define PWR_CR_PLS_0           (0x1UL << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */\n#define PWR_CR_PLS_1           (0x2UL << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */\n#define PWR_CR_PLS_2           (0x4UL << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */\n\n/*!< PVD level configuration */\n#define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */\n#define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */\n#define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */\n#define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */\n#define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */\n#define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */\n#define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */\n#define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */\n#define PWR_CR_DBP_Pos         (8U)\n#define PWR_CR_DBP_Msk         (0x1UL << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */\n#define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */\n#define PWR_CR_FPDS_Pos        (9U)\n#define PWR_CR_FPDS_Msk        (0x1UL << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */\n#define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */\n#define PWR_CR_LPLVDS_Pos      (10U)\n#define PWR_CR_LPLVDS_Msk      (0x1UL << PWR_CR_LPLVDS_Pos)                     /*!< 0x00000400 */\n#define PWR_CR_LPLVDS          PWR_CR_LPLVDS_Msk                               /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */\n#define PWR_CR_MRLVDS_Pos      (11U)\n#define PWR_CR_MRLVDS_Msk      (0x1UL << PWR_CR_MRLVDS_Pos)                     /*!< 0x00000800 */\n#define PWR_CR_MRLVDS          PWR_CR_MRLVDS_Msk                               /*!< Main Regulator Low Voltage in Deep Sleep mode              */\n#define PWR_CR_ADCDC1_Pos      (13U)\n#define PWR_CR_ADCDC1_Msk      (0x1UL << PWR_CR_ADCDC1_Pos)                     /*!< 0x00002000 */\n#define PWR_CR_ADCDC1          PWR_CR_ADCDC1_Msk                               /*!< Refer to AN4073 on how to use this bit                     */\n#define PWR_CR_VOS_Pos         (14U)\n#define PWR_CR_VOS_Msk         (0x3UL << PWR_CR_VOS_Pos)                        /*!< 0x0000C000 */\n#define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\n#define PWR_CR_VOS_0           0x00004000U                                     /*!< Bit 0 */\n#define PWR_CR_VOS_1           0x00008000U                                     /*!< Bit 1 */\n#define PWR_CR_FMSSR_Pos       (20U)\n#define PWR_CR_FMSSR_Msk       (0x1UL << PWR_CR_FMSSR_Pos)                      /*!< 0x00100000 */\n#define PWR_CR_FMSSR           PWR_CR_FMSSR_Msk                                /*!< Flash Memory Sleep System Run        */\n#define PWR_CR_FISSR_Pos       (21U)\n#define PWR_CR_FISSR_Msk       (0x1UL << PWR_CR_FISSR_Pos)                      /*!< 0x00200000 */\n#define PWR_CR_FISSR           PWR_CR_FISSR_Msk                                /*!< Flash Interface Stop while System Run */\n\n\n/*******************  Bit definition for PWR_CSR register  ********************/\n#define PWR_CSR_WUF_Pos        (0U)\n#define PWR_CSR_WUF_Msk        (0x1UL << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */\n#define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */\n#define PWR_CSR_SBF_Pos        (1U)\n#define PWR_CSR_SBF_Msk        (0x1UL << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */\n#define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */\n#define PWR_CSR_PVDO_Pos       (2U)\n#define PWR_CSR_PVDO_Msk       (0x1UL << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */\n#define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */\n#define PWR_CSR_BRR_Pos        (3U)\n#define PWR_CSR_BRR_Msk        (0x1UL << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */\n#define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */\n#define PWR_CSR_EWUP3_Pos      (6U)\n#define PWR_CSR_EWUP3_Msk      (0x1UL << PWR_CSR_EWUP1_Pos)                     /*!< 0x00000040 */\n#define PWR_CSR_EWUP3          PWR_CSR_EWUP3_Msk                               /*!< Enable WKUP pin 3                                */\n#define PWR_CSR_EWUP2_Pos      (7U)\n#define PWR_CSR_EWUP2_Msk      (0x1UL << PWR_CSR_EWUP2_Pos)                     /*!< 0x00000080 */\n#define PWR_CSR_EWUP2          PWR_CSR_EWUP2_Msk                               /*!< Enable WKUP pin 2                                */\n#define PWR_CSR_EWUP1_Pos      (8U)\n#define PWR_CSR_EWUP1_Msk      (0x1UL << PWR_CSR_EWUP1_Pos)                     /*!< 0x00000100 */\n#define PWR_CSR_EWUP1          PWR_CSR_EWUP1_Msk                               /*!< Enable WKUP pin 1                                */\n#define PWR_CSR_BRE_Pos        (9U)\n#define PWR_CSR_BRE_Msk        (0x1UL << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */\n#define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */\n#define PWR_CSR_VOSRDY_Pos     (14U)\n#define PWR_CSR_VOSRDY_Msk     (0x1UL << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */\n#define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    QUADSPI                                 */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define  QSPI1_V2_1L                                                           /*!< QSPI Virtual Version             */\n\n/*****************  Bit definition for QUADSPI_CR register  *******************/\n#define QUADSPI_CR_EN_Pos                (0U)\n#define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)           /*!< 0x00000001 */\n#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable                             */\n#define QUADSPI_CR_ABORT_Pos             (1U)\n#define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)        /*!< 0x00000002 */\n#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request                      */\n#define QUADSPI_CR_DMAEN_Pos             (2U)\n#define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)        /*!< 0x00000004 */\n#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable                         */\n#define QUADSPI_CR_TCEN_Pos              (3U)\n#define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)         /*!< 0x00000008 */\n#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable             */\n#define QUADSPI_CR_SSHIFT_Pos            (4U)\n#define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)       /*!< 0x00000010 */\n#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift                */\n#define QUADSPI_CR_DFM_Pos               (6U)\n#define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)          /*!< 0x00000040 */\n#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode                    */\n#define QUADSPI_CR_FSEL_Pos              (7U)\n#define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)         /*!< 0x00000080 */\n#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select                       */\n#define QUADSPI_CR_FTHRES_Pos            (8U)\n#define QUADSPI_CR_FTHRES_Msk            (0x1FUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */\n#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level             */\n#define QUADSPI_CR_FTHRES_0              (0x01UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */\n#define QUADSPI_CR_FTHRES_1              (0x02UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */\n#define QUADSPI_CR_FTHRES_2              (0x04UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */\n#define QUADSPI_CR_FTHRES_3              (0x08UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */\n#define QUADSPI_CR_FTHRES_4              (0x10UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001000 */\n#define QUADSPI_CR_TEIE_Pos              (16U)\n#define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)         /*!< 0x00010000 */\n#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable    */\n#define QUADSPI_CR_TCIE_Pos              (17U)\n#define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)         /*!< 0x00020000 */\n#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */\n#define QUADSPI_CR_FTIE_Pos              (18U)\n#define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)         /*!< 0x00040000 */\n#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable    */\n#define QUADSPI_CR_SMIE_Pos              (19U)\n#define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)         /*!< 0x00080000 */\n#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable      */\n#define QUADSPI_CR_TOIE_Pos              (20U)\n#define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)         /*!< 0x00100000 */\n#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable           */\n#define QUADSPI_CR_APMS_Pos              (22U)\n#define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)         /*!< 0x00400000 */\n#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1                              */\n#define QUADSPI_CR_PMM_Pos               (23U)\n#define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)          /*!< 0x00800000 */\n#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode                 */\n#define QUADSPI_CR_PRESCALER_Pos         (24U)\n#define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0xFF000000 */\n#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler     */\n#define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x01000000 */\n#define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x02000000 */\n#define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x04000000 */\n#define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x08000000 */\n#define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x10000000 */\n#define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x20000000 */\n#define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x40000000 */\n#define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x80000000 */\n\n/*****************  Bit definition for QUADSPI_DCR register  ******************/\n#define QUADSPI_DCR_CKMODE_Pos           (0U)\n#define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)      /*!< 0x00000001 */\n#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3                 */\n#define QUADSPI_DCR_CSHT_Pos             (8U)\n#define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000700 */\n#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */\n#define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000100 */\n#define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000200 */\n#define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000400 */\n#define QUADSPI_DCR_FSIZE_Pos            (16U)\n#define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x001F0000 */\n#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size          */\n#define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00010000 */\n#define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00020000 */\n#define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00040000 */\n#define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00080000 */\n#define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00100000 */\n\n/******************  Bit definition for QUADSPI_SR register  *******************/\n#define QUADSPI_SR_TEF_Pos               (0U)\n#define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)          /*!< 0x00000001 */\n#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag    */\n#define QUADSPI_SR_TCF_Pos               (1U)\n#define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)          /*!< 0x00000002 */\n#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */\n#define QUADSPI_SR_FTF_Pos               (2U)\n#define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)          /*!< 0x00000004 */\n#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag    */\n#define QUADSPI_SR_SMF_Pos               (3U)\n#define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)          /*!< 0x00000008 */\n#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag      */\n#define QUADSPI_SR_TOF_Pos               (4U)\n#define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)          /*!< 0x00000010 */\n#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag           */\n#define QUADSPI_SR_BUSY_Pos              (5U)\n#define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)         /*!< 0x00000020 */\n#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy                   */\n#define QUADSPI_SR_FLEVEL_Pos            (8U)\n#define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00003F00 */\n#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag    */\n#define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000100 */\n#define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000200 */\n#define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000400 */\n#define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000800 */\n#define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00001000 */\n#define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00002000 */\n\n/******************  Bit definition for QUADSPI_FCR register  ******************/\n#define QUADSPI_FCR_CTEF_Pos             (0U)\n#define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)        /*!< 0x00000001 */\n#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag    */\n#define QUADSPI_FCR_CTCF_Pos             (1U)\n#define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)        /*!< 0x00000002 */\n#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */\n#define QUADSPI_FCR_CSMF_Pos             (3U)\n#define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)        /*!< 0x00000008 */\n#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag      */\n#define QUADSPI_FCR_CTOF_Pos             (4U)\n#define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)        /*!< 0x00000010 */\n#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag           */\n\n/******************  Bit definition for QUADSPI_DLR register  ******************/\n#define QUADSPI_DLR_DL_Pos               (0U)\n#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)   /*!< 0xFFFFFFFF */\n#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */\n\n/******************  Bit definition for QUADSPI_CCR register  ******************/\n#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)\n#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */\n#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk           /*!< INSTRUCTION[7:0]: Instruction         */\n#define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */\n#define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */\n#define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */\n#define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */\n#define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */\n#define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */\n#define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */\n#define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */\n#define QUADSPI_CCR_IMODE_Pos            (8U)\n#define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000300 */\n#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                 /*!< IMODE[1:0]: Instruction Mode          */\n#define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000100 */\n#define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000200 */\n#define QUADSPI_CCR_ADMODE_Pos           (10U)\n#define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000C00 */\n#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                /*!< ADMODE[1:0]: Address Mode             */\n#define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000400 */\n#define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000800 */\n#define QUADSPI_CCR_ADSIZE_Pos           (12U)\n#define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00003000 */\n#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                /*!< ADSIZE[1:0]: Address Size             */\n#define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00001000 */\n#define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00002000 */\n#define QUADSPI_CCR_ABMODE_Pos           (14U)\n#define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x0000C000 */\n#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                /*!< ABMODE[1:0]: Alternate Bytes Mode     */\n#define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00004000 */\n#define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00008000 */\n#define QUADSPI_CCR_ABSIZE_Pos           (16U)\n#define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00030000 */\n#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                /*!< ABSIZE[1:0]: Instruction Mode         */\n#define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00010000 */\n#define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00020000 */\n#define QUADSPI_CCR_DCYC_Pos             (18U)\n#define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x007C0000 */\n#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                  /*!< DCYC[4:0]: Dummy Cycles               */\n#define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00040000 */\n#define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00080000 */\n#define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00100000 */\n#define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00200000 */\n#define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00400000 */\n#define QUADSPI_CCR_DMODE_Pos            (24U)\n#define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x03000000 */\n#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                 /*!< DMODE[1:0]: Data Mode                 */\n#define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x01000000 */\n#define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x02000000 */\n#define QUADSPI_CCR_FMODE_Pos            (26U)\n#define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x0C000000 */\n#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                 /*!< FMODE[1:0]: Functional Mode           */\n#define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x04000000 */\n#define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x08000000 */\n#define QUADSPI_CCR_SIOO_Pos             (28U)\n#define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)        /*!< 0x10000000 */\n#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                  /*!< SIOO: Send Instruction Only Once Mode */\n#define QUADSPI_CCR_DHHC_Pos             (30U)\n#define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)        /*!< 0x40000000 */\n#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                  /*!< DHHC: Delay Half Hclk Cycle           */\n#define QUADSPI_CCR_DDRM_Pos             (31U)\n#define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)        /*!< 0x80000000 */\n#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                  /*!< DDRM: Double Data Rate Mode           */\n/******************  Bit definition for QUADSPI_AR register  *******************/\n#define QUADSPI_AR_ADDRESS_Pos           (0U)\n#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address                */\n\n/******************  Bit definition for QUADSPI_ABR register  ******************/\n#define QUADSPI_ABR_ALTERNATE_Pos        (0U)\n#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes      */\n\n/******************  Bit definition for QUADSPI_DR register  *******************/\n#define QUADSPI_DR_DATA_Pos              (0U)\n#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)  /*!< 0xFFFFFFFF */\n#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data                      */\n\n/******************  Bit definition for QUADSPI_PSMKR register  ****************/\n#define QUADSPI_PSMKR_MASK_Pos           (0U)\n#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask               */\n\n/******************  Bit definition for QUADSPI_PSMAR register  ****************/\n#define QUADSPI_PSMAR_MATCH_Pos          (0U)\n#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match             */\n\n/******************  Bit definition for QUADSPI_PIR register  *****************/\n#define QUADSPI_PIR_INTERVAL_Pos         (0U)\n#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */\n#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval      */\n\n/******************  Bit definition for QUADSPI_LPTR register  *****************/\n#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)\n#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */\n#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period         */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Reset and Clock Control                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for RCC_CR register  ********************/\n#define RCC_CR_HSION_Pos                   (0U)\n#define RCC_CR_HSION_Msk                   (0x1UL << RCC_CR_HSION_Pos)          /*!< 0x00000001 */\n#define RCC_CR_HSION                       RCC_CR_HSION_Msk\n#define RCC_CR_HSIRDY_Pos                  (1U)\n#define RCC_CR_HSIRDY_Msk                  (0x1UL << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */\n#define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk\n\n#define RCC_CR_HSITRIM_Pos                 (3U)\n#define RCC_CR_HSITRIM_Msk                 (0x1FUL << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */\n#define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk\n#define RCC_CR_HSITRIM_0                   (0x01UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */\n#define RCC_CR_HSITRIM_1                   (0x02UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */\n#define RCC_CR_HSITRIM_2                   (0x04UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */\n#define RCC_CR_HSITRIM_3                   (0x08UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */\n#define RCC_CR_HSITRIM_4                   (0x10UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */\n\n#define RCC_CR_HSICAL_Pos                  (8U)\n#define RCC_CR_HSICAL_Msk                  (0xFFUL << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */\n#define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk\n#define RCC_CR_HSICAL_0                    (0x01UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */\n#define RCC_CR_HSICAL_1                    (0x02UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */\n#define RCC_CR_HSICAL_2                    (0x04UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */\n#define RCC_CR_HSICAL_3                    (0x08UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */\n#define RCC_CR_HSICAL_4                    (0x10UL << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */\n#define RCC_CR_HSICAL_5                    (0x20UL << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */\n#define RCC_CR_HSICAL_6                    (0x40UL << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */\n#define RCC_CR_HSICAL_7                    (0x80UL << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */\n\n#define RCC_CR_HSEON_Pos                   (16U)\n#define RCC_CR_HSEON_Msk                   (0x1UL << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */\n#define RCC_CR_HSEON                       RCC_CR_HSEON_Msk\n#define RCC_CR_HSERDY_Pos                  (17U)\n#define RCC_CR_HSERDY_Msk                  (0x1UL << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */\n#define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk\n#define RCC_CR_HSEBYP_Pos                  (18U)\n#define RCC_CR_HSEBYP_Msk                  (0x1UL << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */\n#define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk\n#define RCC_CR_CSSON_Pos                   (19U)\n#define RCC_CR_CSSON_Msk                   (0x1UL << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */\n#define RCC_CR_CSSON                       RCC_CR_CSSON_Msk\n#define RCC_CR_PLLON_Pos                   (24U)\n#define RCC_CR_PLLON_Msk                   (0x1UL << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */\n#define RCC_CR_PLLON                       RCC_CR_PLLON_Msk\n#define RCC_CR_PLLRDY_Pos                  (25U)\n#define RCC_CR_PLLRDY_Msk                  (0x1UL << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */\n#define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_PLLI2S_SUPPORT                                                     /*!< Support PLLI2S oscillator */\n\n#define RCC_CR_PLLI2SON_Pos                (26U)\n#define RCC_CR_PLLI2SON_Msk                (0x1UL << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */\n#define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk\n#define RCC_CR_PLLI2SRDY_Pos               (27U)\n#define RCC_CR_PLLI2SRDY_Msk               (0x1UL << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */\n#define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk\n\n/********************  Bit definition for RCC_PLLCFGR register  ***************/\n#define RCC_PLLCFGR_PLLM_Pos               (0U)\n#define RCC_PLLCFGR_PLLM_Msk               (0x3FUL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */\n#define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk\n#define RCC_PLLCFGR_PLLM_0                 (0x01UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */\n#define RCC_PLLCFGR_PLLM_1                 (0x02UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */\n#define RCC_PLLCFGR_PLLM_2                 (0x04UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */\n#define RCC_PLLCFGR_PLLM_3                 (0x08UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */\n#define RCC_PLLCFGR_PLLM_4                 (0x10UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */\n#define RCC_PLLCFGR_PLLM_5                 (0x20UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */\n\n#define RCC_PLLCFGR_PLLN_Pos               (6U)\n#define RCC_PLLCFGR_PLLN_Msk               (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */\n#define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk\n#define RCC_PLLCFGR_PLLN_0                 (0x001UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */\n#define RCC_PLLCFGR_PLLN_1                 (0x002UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */\n#define RCC_PLLCFGR_PLLN_2                 (0x004UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */\n#define RCC_PLLCFGR_PLLN_3                 (0x008UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */\n#define RCC_PLLCFGR_PLLN_4                 (0x010UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */\n#define RCC_PLLCFGR_PLLN_5                 (0x020UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */\n#define RCC_PLLCFGR_PLLN_6                 (0x040UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */\n#define RCC_PLLCFGR_PLLN_7                 (0x080UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */\n#define RCC_PLLCFGR_PLLN_8                 (0x100UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */\n\n#define RCC_PLLCFGR_PLLP_Pos               (16U)\n#define RCC_PLLCFGR_PLLP_Msk               (0x3UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */\n#define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk\n#define RCC_PLLCFGR_PLLP_0                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */\n#define RCC_PLLCFGR_PLLP_1                 (0x2UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */\n\n#define RCC_PLLCFGR_PLLSRC_Pos             (22U)\n#define RCC_PLLCFGR_PLLSRC_Msk             (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk\n#define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)\n#define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk\n#define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U\n\n#define RCC_PLLCFGR_PLLQ_Pos               (24U)\n#define RCC_PLLCFGR_PLLQ_Msk               (0xFUL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */\n#define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk\n#define RCC_PLLCFGR_PLLQ_0                 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */\n#define RCC_PLLCFGR_PLLQ_1                 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */\n#define RCC_PLLCFGR_PLLQ_2                 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */\n#define RCC_PLLCFGR_PLLQ_3                 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_PLLR_I2S_CLKSOURCE_SUPPORT     /*!< Support PLLR clock as I2S clock source */\n\n#define RCC_PLLCFGR_PLLR_Pos               (28U)\n#define RCC_PLLCFGR_PLLR_Msk               (0x7UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x70000000 */\n#define RCC_PLLCFGR_PLLR                   RCC_PLLCFGR_PLLR_Msk\n#define RCC_PLLCFGR_PLLR_0                 (0x1UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x10000000 */\n#define RCC_PLLCFGR_PLLR_1                 (0x2UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x20000000 */\n#define RCC_PLLCFGR_PLLR_2                 (0x4UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x40000000 */\n\n/********************  Bit definition for RCC_CFGR register  ******************/\n/*!< SW configuration */\n#define RCC_CFGR_SW_Pos                    (0U)\n#define RCC_CFGR_SW_Msk                    (0x3UL << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */\n#define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */\n#define RCC_CFGR_SW_0                      (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */\n#define RCC_CFGR_SW_1                      (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */\n\n#define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */\n#define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */\n#define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */\n\n/*!< SWS configuration */\n#define RCC_CFGR_SWS_Pos                   (2U)\n#define RCC_CFGR_SWS_Msk                   (0x3UL << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */\n#define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */\n#define RCC_CFGR_SWS_0                     (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */\n#define RCC_CFGR_SWS_1                     (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */\n\n#define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */\n#define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */\n#define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */\n\n/*!< HPRE configuration */\n#define RCC_CFGR_HPRE_Pos                  (4U)\n#define RCC_CFGR_HPRE_Msk                  (0xFUL << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */\n#define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */\n#define RCC_CFGR_HPRE_0                    (0x1UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */\n#define RCC_CFGR_HPRE_1                    (0x2UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */\n#define RCC_CFGR_HPRE_2                    (0x4UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */\n#define RCC_CFGR_HPRE_3                    (0x8UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */\n\n#define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */\n#define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */\n#define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */\n#define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */\n#define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */\n#define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */\n#define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */\n#define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */\n#define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */\n\n/*!< PPRE1 configuration */\n#define RCC_CFGR_PPRE1_Pos                 (10U)\n#define RCC_CFGR_PPRE1_Msk                 (0x7UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */\n#define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */\n#define RCC_CFGR_PPRE1_0                   (0x1UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */\n#define RCC_CFGR_PPRE1_1                   (0x2UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */\n#define RCC_CFGR_PPRE1_2                   (0x4UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */\n\n#define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */\n\n/*!< PPRE2 configuration */\n#define RCC_CFGR_PPRE2_Pos                 (13U)\n#define RCC_CFGR_PPRE2_Msk                 (0x7UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */\n#define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */\n#define RCC_CFGR_PPRE2_0                   (0x1UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */\n#define RCC_CFGR_PPRE2_1                   (0x2UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */\n#define RCC_CFGR_PPRE2_2                   (0x4UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */\n\n#define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */\n\n/*!< RTCPRE configuration */\n#define RCC_CFGR_RTCPRE_Pos                (16U)\n#define RCC_CFGR_RTCPRE_Msk                (0x1FUL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */\n#define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk\n#define RCC_CFGR_RTCPRE_0                  (0x01UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */\n#define RCC_CFGR_RTCPRE_1                  (0x02UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */\n#define RCC_CFGR_RTCPRE_2                  (0x04UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */\n#define RCC_CFGR_RTCPRE_3                  (0x08UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */\n#define RCC_CFGR_RTCPRE_4                  (0x10UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */\n\n/*!< MCO1 configuration */\n#define RCC_CFGR_MCO1_Pos                  (21U)\n#define RCC_CFGR_MCO1_Msk                  (0x3UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */\n#define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk\n#define RCC_CFGR_MCO1_0                    (0x1UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */\n#define RCC_CFGR_MCO1_1                    (0x2UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */\n\n\n#define RCC_CFGR_MCO1PRE_Pos               (24U)\n#define RCC_CFGR_MCO1PRE_Msk               (0x7UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */\n#define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk\n#define RCC_CFGR_MCO1PRE_0                 (0x1UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */\n#define RCC_CFGR_MCO1PRE_1                 (0x2UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */\n#define RCC_CFGR_MCO1PRE_2                 (0x4UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */\n\n#define RCC_CFGR_MCO2PRE_Pos               (27U)\n#define RCC_CFGR_MCO2PRE_Msk               (0x7UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */\n#define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk\n#define RCC_CFGR_MCO2PRE_0                 (0x1UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */\n#define RCC_CFGR_MCO2PRE_1                 (0x2UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */\n#define RCC_CFGR_MCO2PRE_2                 (0x4UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */\n\n#define RCC_CFGR_MCO2_Pos                  (30U)\n#define RCC_CFGR_MCO2_Msk                  (0x3UL << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */\n#define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk\n#define RCC_CFGR_MCO2_0                    (0x1UL << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */\n#define RCC_CFGR_MCO2_1                    (0x2UL << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */\n\n/********************  Bit definition for RCC_CIR register  *******************/\n#define RCC_CIR_LSIRDYF_Pos                (0U)\n#define RCC_CIR_LSIRDYF_Msk                (0x1UL << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */\n#define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk\n#define RCC_CIR_LSERDYF_Pos                (1U)\n#define RCC_CIR_LSERDYF_Msk                (0x1UL << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */\n#define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk\n#define RCC_CIR_HSIRDYF_Pos                (2U)\n#define RCC_CIR_HSIRDYF_Msk                (0x1UL << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */\n#define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk\n#define RCC_CIR_HSERDYF_Pos                (3U)\n#define RCC_CIR_HSERDYF_Msk                (0x1UL << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */\n#define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk\n#define RCC_CIR_PLLRDYF_Pos                (4U)\n#define RCC_CIR_PLLRDYF_Msk                (0x1UL << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */\n#define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk\n#define RCC_CIR_PLLI2SRDYF_Pos             (5U)\n#define RCC_CIR_PLLI2SRDYF_Msk             (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */\n#define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk\n\n#define RCC_CIR_CSSF_Pos                   (7U)\n#define RCC_CIR_CSSF_Msk                   (0x1UL << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */\n#define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk\n#define RCC_CIR_LSIRDYIE_Pos               (8U)\n#define RCC_CIR_LSIRDYIE_Msk               (0x1UL << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */\n#define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk\n#define RCC_CIR_LSERDYIE_Pos               (9U)\n#define RCC_CIR_LSERDYIE_Msk               (0x1UL << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */\n#define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk\n#define RCC_CIR_HSIRDYIE_Pos               (10U)\n#define RCC_CIR_HSIRDYIE_Msk               (0x1UL << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */\n#define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk\n#define RCC_CIR_HSERDYIE_Pos               (11U)\n#define RCC_CIR_HSERDYIE_Msk               (0x1UL << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */\n#define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk\n#define RCC_CIR_PLLRDYIE_Pos               (12U)\n#define RCC_CIR_PLLRDYIE_Msk               (0x1UL << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */\n#define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk\n#define RCC_CIR_PLLI2SRDYIE_Pos            (13U)\n#define RCC_CIR_PLLI2SRDYIE_Msk            (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */\n#define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk\n\n#define RCC_CIR_LSIRDYC_Pos                (16U)\n#define RCC_CIR_LSIRDYC_Msk                (0x1UL << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */\n#define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk\n#define RCC_CIR_LSERDYC_Pos                (17U)\n#define RCC_CIR_LSERDYC_Msk                (0x1UL << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */\n#define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk\n#define RCC_CIR_HSIRDYC_Pos                (18U)\n#define RCC_CIR_HSIRDYC_Msk                (0x1UL << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */\n#define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk\n#define RCC_CIR_HSERDYC_Pos                (19U)\n#define RCC_CIR_HSERDYC_Msk                (0x1UL << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */\n#define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk\n#define RCC_CIR_PLLRDYC_Pos                (20U)\n#define RCC_CIR_PLLRDYC_Msk                (0x1UL << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */\n#define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk\n#define RCC_CIR_PLLI2SRDYC_Pos             (21U)\n#define RCC_CIR_PLLI2SRDYC_Msk             (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */\n#define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk\n\n#define RCC_CIR_CSSC_Pos                   (23U)\n#define RCC_CIR_CSSC_Msk                   (0x1UL << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */\n#define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk\n\n/********************  Bit definition for RCC_AHB1RSTR register  **************/\n#define RCC_AHB1RSTR_GPIOARST_Pos          (0U)\n#define RCC_AHB1RSTR_GPIOARST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */\n#define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk\n#define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)\n#define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */\n#define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk\n#define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)\n#define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */\n#define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk\n#define RCC_AHB1RSTR_GPIODRST_Pos          (3U)\n#define RCC_AHB1RSTR_GPIODRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */\n#define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk\n#define RCC_AHB1RSTR_GPIOERST_Pos          (4U)\n#define RCC_AHB1RSTR_GPIOERST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */\n#define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk\n#define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)\n#define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */\n#define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk\n#define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)\n#define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */\n#define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk\n#define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)\n#define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk\n#define RCC_AHB1RSTR_CRCRST_Pos            (12U)\n#define RCC_AHB1RSTR_CRCRST_Msk            (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */\n#define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk\n#define RCC_AHB1RSTR_DMA1RST_Pos           (21U)\n#define RCC_AHB1RSTR_DMA1RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */\n#define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk\n#define RCC_AHB1RSTR_DMA2RST_Pos           (22U)\n#define RCC_AHB1RSTR_DMA2RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */\n#define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk\n\n/********************  Bit definition for RCC_AHB2RSTR register  **************/\n#define RCC_AHB2RSTR_RNGRST_Pos            (6U)\n#define RCC_AHB2RSTR_RNGRST_Msk            (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)   /*!< 0x00000040 */\n#define RCC_AHB2RSTR_RNGRST                RCC_AHB2RSTR_RNGRST_Msk\n#define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)\n#define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk\n/********************  Bit definition for RCC_AHB3RSTR register  **************/\n#define RCC_AHB3RSTR_FSMCRST_Pos           (0U)\n#define RCC_AHB3RSTR_FSMCRST_Msk           (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)  /*!< 0x00000001 */\n#define RCC_AHB3RSTR_FSMCRST               RCC_AHB3RSTR_FSMCRST_Msk\n#define RCC_AHB3RSTR_QSPIRST_Pos           (1U)\n#define RCC_AHB3RSTR_QSPIRST_Msk           (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)  /*!< 0x00000002 */\n#define RCC_AHB3RSTR_QSPIRST               RCC_AHB3RSTR_QSPIRST_Msk\n\n\n/********************  Bit definition for RCC_APB1RSTR register  **************/\n#define RCC_APB1RSTR_TIM2RST_Pos           (0U)\n#define RCC_APB1RSTR_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk\n#define RCC_APB1RSTR_TIM3RST_Pos           (1U)\n#define RCC_APB1RSTR_TIM3RST_Msk           (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk\n#define RCC_APB1RSTR_TIM4RST_Pos           (2U)\n#define RCC_APB1RSTR_TIM4RST_Msk           (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */\n#define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk\n#define RCC_APB1RSTR_TIM5RST_Pos           (3U)\n#define RCC_APB1RSTR_TIM5RST_Msk           (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */\n#define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk\n#define RCC_APB1RSTR_TIM6RST_Pos           (4U)\n#define RCC_APB1RSTR_TIM6RST_Msk           (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */\n#define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk\n#define RCC_APB1RSTR_TIM7RST_Pos           (5U)\n#define RCC_APB1RSTR_TIM7RST_Msk           (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */\n#define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk\n#define RCC_APB1RSTR_TIM12RST_Pos          (6U)\n#define RCC_APB1RSTR_TIM12RST_Msk          (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */\n#define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk\n#define RCC_APB1RSTR_TIM13RST_Pos          (7U)\n#define RCC_APB1RSTR_TIM13RST_Msk          (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */\n#define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk\n#define RCC_APB1RSTR_TIM14RST_Pos          (8U)\n#define RCC_APB1RSTR_TIM14RST_Msk          (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */\n#define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk\n#define RCC_APB1RSTR_WWDGRST_Pos           (11U)\n#define RCC_APB1RSTR_WWDGRST_Msk           (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */\n#define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk\n#define RCC_APB1RSTR_SPI2RST_Pos           (14U)\n#define RCC_APB1RSTR_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */\n#define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk\n#define RCC_APB1RSTR_SPI3RST_Pos           (15U)\n#define RCC_APB1RSTR_SPI3RST_Msk           (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */\n#define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk\n#define RCC_APB1RSTR_USART2RST_Pos         (17U)\n#define RCC_APB1RSTR_USART2RST_Msk         (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */\n#define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk\n#define RCC_APB1RSTR_USART3RST_Pos         (18U)\n#define RCC_APB1RSTR_USART3RST_Msk         (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */\n#define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk\n#define RCC_APB1RSTR_I2C1RST_Pos           (21U)\n#define RCC_APB1RSTR_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */\n#define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk\n#define RCC_APB1RSTR_I2C2RST_Pos           (22U)\n#define RCC_APB1RSTR_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */\n#define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk\n#define RCC_APB1RSTR_I2C3RST_Pos           (23U)\n#define RCC_APB1RSTR_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */\n#define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk\n#define RCC_APB1RSTR_FMPI2C1RST_Pos        (24U)\n#define RCC_APB1RSTR_FMPI2C1RST_Msk        (0x1UL << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */\n#define RCC_APB1RSTR_FMPI2C1RST            RCC_APB1RSTR_FMPI2C1RST_Msk\n#define RCC_APB1RSTR_CAN1RST_Pos           (25U)\n#define RCC_APB1RSTR_CAN1RST_Msk           (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */\n#define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk\n#define RCC_APB1RSTR_CAN2RST_Pos           (26U)\n#define RCC_APB1RSTR_CAN2RST_Msk           (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */\n#define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk\n#define RCC_APB1RSTR_PWRRST_Pos            (28U)\n#define RCC_APB1RSTR_PWRRST_Msk            (0x1UL << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */\n#define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk\n\n/********************  Bit definition for RCC_APB2RSTR register  **************/\n#define RCC_APB2RSTR_TIM1RST_Pos           (0U)\n#define RCC_APB2RSTR_TIM1RST_Msk           (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk\n#define RCC_APB2RSTR_TIM8RST_Pos           (1U)\n#define RCC_APB2RSTR_TIM8RST_Msk           (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk\n#define RCC_APB2RSTR_USART1RST_Pos         (4U)\n#define RCC_APB2RSTR_USART1RST_Msk         (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */\n#define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk\n#define RCC_APB2RSTR_USART6RST_Pos         (5U)\n#define RCC_APB2RSTR_USART6RST_Msk         (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */\n#define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk\n#define RCC_APB2RSTR_ADCRST_Pos            (8U)\n#define RCC_APB2RSTR_ADCRST_Msk            (0x1UL << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */\n#define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk\n#define RCC_APB2RSTR_SDIORST_Pos           (11U)\n#define RCC_APB2RSTR_SDIORST_Msk           (0x1UL << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */\n#define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk\n#define RCC_APB2RSTR_SPI1RST_Pos           (12U)\n#define RCC_APB2RSTR_SPI1RST_Msk           (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */\n#define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk\n#define RCC_APB2RSTR_SPI4RST_Pos           (13U)\n#define RCC_APB2RSTR_SPI4RST_Msk           (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)  /*!< 0x00002000 */\n#define RCC_APB2RSTR_SPI4RST               RCC_APB2RSTR_SPI4RST_Msk\n#define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)\n#define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */\n#define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk\n#define RCC_APB2RSTR_TIM9RST_Pos           (16U)\n#define RCC_APB2RSTR_TIM9RST_Msk           (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */\n#define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk\n#define RCC_APB2RSTR_TIM10RST_Pos          (17U)\n#define RCC_APB2RSTR_TIM10RST_Msk          (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */\n#define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk\n#define RCC_APB2RSTR_TIM11RST_Pos          (18U)\n#define RCC_APB2RSTR_TIM11RST_Msk          (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */\n#define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk\n#define RCC_APB2RSTR_SPI5RST_Pos           (20U)\n#define RCC_APB2RSTR_SPI5RST_Msk           (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)  /*!< 0x00100000 */\n#define RCC_APB2RSTR_SPI5RST               RCC_APB2RSTR_SPI5RST_Msk\n#define RCC_APB2RSTR_DFSDM1RST_Pos         (24U)\n#define RCC_APB2RSTR_DFSDM1RST_Msk         (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */\n#define RCC_APB2RSTR_DFSDM1RST             RCC_APB2RSTR_DFSDM1RST_Msk\n\n/********************  Bit definition for RCC_AHB1ENR register  ***************/\n#define RCC_AHB1ENR_GPIOAEN_Pos            (0U)\n#define RCC_AHB1ENR_GPIOAEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */\n#define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk\n#define RCC_AHB1ENR_GPIOBEN_Pos            (1U)\n#define RCC_AHB1ENR_GPIOBEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */\n#define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk\n#define RCC_AHB1ENR_GPIOCEN_Pos            (2U)\n#define RCC_AHB1ENR_GPIOCEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */\n#define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk\n#define RCC_AHB1ENR_GPIODEN_Pos            (3U)\n#define RCC_AHB1ENR_GPIODEN_Msk            (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */\n#define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk\n#define RCC_AHB1ENR_GPIOEEN_Pos            (4U)\n#define RCC_AHB1ENR_GPIOEEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */\n#define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk\n#define RCC_AHB1ENR_GPIOFEN_Pos            (5U)\n#define RCC_AHB1ENR_GPIOFEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */\n#define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk\n#define RCC_AHB1ENR_GPIOGEN_Pos            (6U)\n#define RCC_AHB1ENR_GPIOGEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */\n#define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk\n#define RCC_AHB1ENR_GPIOHEN_Pos            (7U)\n#define RCC_AHB1ENR_GPIOHEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk\n#define RCC_AHB1ENR_CRCEN_Pos              (12U)\n#define RCC_AHB1ENR_CRCEN_Msk              (0x1UL << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */\n#define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk\n#define RCC_AHB1ENR_DMA1EN_Pos             (21U)\n#define RCC_AHB1ENR_DMA1EN_Msk             (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */\n#define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk\n#define RCC_AHB1ENR_DMA2EN_Pos             (22U)\n#define RCC_AHB1ENR_DMA2EN_Msk             (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */\n#define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk\n/********************  Bit definition for RCC_AHB2ENR register  ***************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_AHB2_SUPPORT                   /*!< AHB2 Bus is supported */\n\n#define RCC_AHB2ENR_RNGEN_Pos              (6U)\n#define RCC_AHB2ENR_RNGEN_Msk              (0x1UL << RCC_AHB2ENR_RNGEN_Pos)     /*!< 0x00000040 */\n#define RCC_AHB2ENR_RNGEN                  RCC_AHB2ENR_RNGEN_Msk\n#define RCC_AHB2ENR_OTGFSEN_Pos            (7U)\n#define RCC_AHB2ENR_OTGFSEN_Msk            (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk\n\n/********************  Bit definition for RCC_AHB3ENR register  ***************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_AHB3_SUPPORT                   /*!< AHB3 Bus is supported */\n\n#define RCC_AHB3ENR_FSMCEN_Pos             (0U)\n#define RCC_AHB3ENR_FSMCEN_Msk             (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)    /*!< 0x00000001 */\n#define RCC_AHB3ENR_FSMCEN                 RCC_AHB3ENR_FSMCEN_Msk\n#define RCC_AHB3ENR_QSPIEN_Pos             (1U)\n#define RCC_AHB3ENR_QSPIEN_Msk             (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)    /*!< 0x00000002 */\n#define RCC_AHB3ENR_QSPIEN                 RCC_AHB3ENR_QSPIEN_Msk\n\n/********************  Bit definition for RCC_APB1ENR register  ***************/\n#define RCC_APB1ENR_TIM2EN_Pos             (0U)\n#define RCC_APB1ENR_TIM2EN_Msk             (0x1UL << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk\n#define RCC_APB1ENR_TIM3EN_Pos             (1U)\n#define RCC_APB1ENR_TIM3EN_Msk             (0x1UL << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk\n#define RCC_APB1ENR_TIM4EN_Pos             (2U)\n#define RCC_APB1ENR_TIM4EN_Msk             (0x1UL << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */\n#define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk\n#define RCC_APB1ENR_TIM5EN_Pos             (3U)\n#define RCC_APB1ENR_TIM5EN_Msk             (0x1UL << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */\n#define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk\n#define RCC_APB1ENR_TIM6EN_Pos             (4U)\n#define RCC_APB1ENR_TIM6EN_Msk             (0x1UL << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */\n#define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk\n#define RCC_APB1ENR_TIM7EN_Pos             (5U)\n#define RCC_APB1ENR_TIM7EN_Msk             (0x1UL << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */\n#define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk\n#define RCC_APB1ENR_TIM12EN_Pos            (6U)\n#define RCC_APB1ENR_TIM12EN_Msk            (0x1UL << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */\n#define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk\n#define RCC_APB1ENR_TIM13EN_Pos            (7U)\n#define RCC_APB1ENR_TIM13EN_Msk            (0x1UL << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */\n#define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk\n#define RCC_APB1ENR_TIM14EN_Pos            (8U)\n#define RCC_APB1ENR_TIM14EN_Msk            (0x1UL << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */\n#define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk\n#define RCC_APB1ENR_RTCAPBEN_Pos           (10U)\n#define RCC_APB1ENR_RTCAPBEN_Msk           (0x1UL << RCC_APB1ENR_RTCAPBEN_Pos)  /*!< 0x00000400 */\n#define RCC_APB1ENR_RTCAPBEN               RCC_APB1ENR_RTCAPBEN_Msk\n#define RCC_APB1ENR_WWDGEN_Pos             (11U)\n#define RCC_APB1ENR_WWDGEN_Msk             (0x1UL << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk\n#define RCC_APB1ENR_SPI2EN_Pos             (14U)\n#define RCC_APB1ENR_SPI2EN_Msk             (0x1UL << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */\n#define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk\n#define RCC_APB1ENR_SPI3EN_Pos             (15U)\n#define RCC_APB1ENR_SPI3EN_Msk             (0x1UL << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */\n#define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk\n#define RCC_APB1ENR_USART2EN_Pos           (17U)\n#define RCC_APB1ENR_USART2EN_Msk           (0x1UL << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */\n#define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk\n#define RCC_APB1ENR_USART3EN_Pos           (18U)\n#define RCC_APB1ENR_USART3EN_Msk           (0x1UL << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */\n#define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk\n#define RCC_APB1ENR_I2C1EN_Pos             (21U)\n#define RCC_APB1ENR_I2C1EN_Msk             (0x1UL << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */\n#define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk\n#define RCC_APB1ENR_I2C2EN_Pos             (22U)\n#define RCC_APB1ENR_I2C2EN_Msk             (0x1UL << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */\n#define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk\n#define RCC_APB1ENR_I2C3EN_Pos             (23U)\n#define RCC_APB1ENR_I2C3EN_Msk             (0x1UL << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */\n#define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk\n#define RCC_APB1ENR_FMPI2C1EN_Pos          (24U)\n#define RCC_APB1ENR_FMPI2C1EN_Msk          (0x1UL << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */\n#define RCC_APB1ENR_FMPI2C1EN              RCC_APB1ENR_FMPI2C1EN_Msk\n#define RCC_APB1ENR_CAN1EN_Pos             (25U)\n#define RCC_APB1ENR_CAN1EN_Msk             (0x1UL << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */\n#define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk\n#define RCC_APB1ENR_CAN2EN_Pos             (26U)\n#define RCC_APB1ENR_CAN2EN_Msk             (0x1UL << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */\n#define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk\n#define RCC_APB1ENR_PWREN_Pos              (28U)\n#define RCC_APB1ENR_PWREN_Msk              (0x1UL << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */\n#define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk\n\n/********************  Bit definition for RCC_APB2ENR register  ***************/\n#define RCC_APB2ENR_TIM1EN_Pos             (0U)\n#define RCC_APB2ENR_TIM1EN_Msk             (0x1UL << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk\n#define RCC_APB2ENR_TIM8EN_Pos             (1U)\n#define RCC_APB2ENR_TIM8EN_Msk             (0x1UL << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk\n#define RCC_APB2ENR_USART1EN_Pos           (4U)\n#define RCC_APB2ENR_USART1EN_Msk           (0x1UL << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */\n#define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk\n#define RCC_APB2ENR_USART6EN_Pos           (5U)\n#define RCC_APB2ENR_USART6EN_Msk           (0x1UL << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */\n#define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk\n#define RCC_APB2ENR_ADC1EN_Pos             (8U)\n#define RCC_APB2ENR_ADC1EN_Msk             (0x1UL << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */\n#define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk\n#define RCC_APB2ENR_SDIOEN_Pos             (11U)\n#define RCC_APB2ENR_SDIOEN_Msk             (0x1UL << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk\n#define RCC_APB2ENR_SPI1EN_Pos             (12U)\n#define RCC_APB2ENR_SPI1EN_Msk             (0x1UL << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */\n#define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk\n#define RCC_APB2ENR_SPI4EN_Pos             (13U)\n#define RCC_APB2ENR_SPI4EN_Msk             (0x1UL << RCC_APB2ENR_SPI4EN_Pos)    /*!< 0x00002000 */\n#define RCC_APB2ENR_SPI4EN                 RCC_APB2ENR_SPI4EN_Msk\n#define RCC_APB2ENR_SYSCFGEN_Pos           (14U)\n#define RCC_APB2ENR_SYSCFGEN_Msk           (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */\n#define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk\n#define RCC_APB2ENR_EXTITEN_Pos            (15U)\n#define RCC_APB2ENR_EXTITEN_Msk            (0x1UL << RCC_APB2ENR_EXTITEN_Pos)   /*!< 0x00008000 */\n#define RCC_APB2ENR_EXTITEN                RCC_APB2ENR_EXTITEN_Msk\n#define RCC_APB2ENR_TIM9EN_Pos             (16U)\n#define RCC_APB2ENR_TIM9EN_Msk             (0x1UL << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */\n#define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk\n#define RCC_APB2ENR_TIM10EN_Pos            (17U)\n#define RCC_APB2ENR_TIM10EN_Msk            (0x1UL << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */\n#define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk\n#define RCC_APB2ENR_TIM11EN_Pos            (18U)\n#define RCC_APB2ENR_TIM11EN_Msk            (0x1UL << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */\n#define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk\n#define RCC_APB2ENR_SPI5EN_Pos             (20U)\n#define RCC_APB2ENR_SPI5EN_Msk             (0x1UL << RCC_APB2ENR_SPI5EN_Pos)    /*!< 0x00100000 */\n#define RCC_APB2ENR_SPI5EN                 RCC_APB2ENR_SPI5EN_Msk\n#define RCC_APB2ENR_DFSDM1EN_Pos           (24U)\n#define RCC_APB2ENR_DFSDM1EN_Msk           (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos)  /*!< 0x01000000 */\n#define RCC_APB2ENR_DFSDM1EN               RCC_APB2ENR_DFSDM1EN_Msk\n\n/********************  Bit definition for RCC_AHB1LPENR register  *************/\n#define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)\n#define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk\n#define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)\n#define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk\n#define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)\n#define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */\n#define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk\n#define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)\n#define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */\n#define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk\n#define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)\n#define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */\n#define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk\n#define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)\n#define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */\n#define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk\n#define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)\n#define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk\n#define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)\n#define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk\n#define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)\n#define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */\n#define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk\n#define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)\n#define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */\n#define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk\n#define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)\n#define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */\n#define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk\n#define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)\n#define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk\n#define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)\n#define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk\n\n\n/********************  Bit definition for RCC_AHB2LPENR register  *************/\n#define RCC_AHB2LPENR_RNGLPEN_Pos          (6U)\n#define RCC_AHB2LPENR_RNGLPEN_Msk          (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB2LPENR_RNGLPEN              RCC_AHB2LPENR_RNGLPEN_Msk\n#define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)\n#define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk\n\n/********************  Bit definition for RCC_AHB3LPENR register  *************/\n#define RCC_AHB3LPENR_FSMCLPEN_Pos         (0U)\n#define RCC_AHB3LPENR_FSMCLPEN_Msk         (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB3LPENR_FSMCLPEN             RCC_AHB3LPENR_FSMCLPEN_Msk\n#define RCC_AHB3LPENR_QSPILPEN_Pos         (1U)\n#define RCC_AHB3LPENR_QSPILPEN_Msk         (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB3LPENR_QSPILPEN             RCC_AHB3LPENR_QSPILPEN_Msk\n\n/********************  Bit definition for RCC_APB1LPENR register  *************/\n#define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)\n#define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk\n#define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)\n#define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk\n#define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)\n#define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */\n#define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk\n#define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)\n#define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */\n#define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk\n#define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)\n#define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk\n#define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)\n#define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk\n#define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)\n#define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */\n#define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk\n#define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)\n#define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */\n#define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk\n#define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)\n#define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk\n#define RCC_APB1LPENR_RTCAPBLPEN_Pos       (10U)\n#define RCC_APB1LPENR_RTCAPBLPEN_Msk       (0x1UL << RCC_APB1LPENR_RTCAPBLPEN_Pos) /*!< 0x00000400 */\n#define RCC_APB1LPENR_RTCAPBLPEN           RCC_APB1LPENR_RTCAPBLPEN_Msk\n#define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)\n#define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk\n#define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)\n#define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk\n#define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)\n#define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */\n#define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk\n#define RCC_APB1LPENR_USART2LPEN_Pos       (17U)\n#define RCC_APB1LPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk\n#define RCC_APB1LPENR_USART3LPEN_Pos       (18U)\n#define RCC_APB1LPENR_USART3LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk\n#define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)\n#define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk\n#define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)\n#define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk\n#define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)\n#define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */\n#define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk\n#define RCC_APB1LPENR_FMPI2C1LPEN_Pos      (24U)\n#define RCC_APB1LPENR_FMPI2C1LPEN_Msk      (0x1UL << RCC_APB1LPENR_FMPI2C1LPEN_Pos) /*!< 0x01000000 */\n#define RCC_APB1LPENR_FMPI2C1LPEN          RCC_APB1LPENR_FMPI2C1LPEN_Msk\n#define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)\n#define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */\n#define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk\n#define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)\n#define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */\n#define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk\n#define RCC_APB1LPENR_PWRLPEN_Pos          (28U)\n#define RCC_APB1LPENR_PWRLPEN_Msk          (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */\n#define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk\n\n/********************  Bit definition for RCC_APB2LPENR register  *************/\n#define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)\n#define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk\n#define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)\n#define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk\n#define RCC_APB2LPENR_USART1LPEN_Pos       (4U)\n#define RCC_APB2LPENR_USART1LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk\n#define RCC_APB2LPENR_USART6LPEN_Pos       (5U)\n#define RCC_APB2LPENR_USART6LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk\n#define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)\n#define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk\n#define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)\n#define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk\n#define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)\n#define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */\n#define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk\n#define RCC_APB2LPENR_SPI4LPEN_Pos         (13U)\n#define RCC_APB2LPENR_SPI4LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */\n#define RCC_APB2LPENR_SPI4LPEN             RCC_APB2LPENR_SPI4LPEN_Msk\n#define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)\n#define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk\n#define RCC_APB2LPENR_EXTITLPEN_Pos        (15U)\n#define RCC_APB2LPENR_EXTITLPEN_Msk        (0x1UL << RCC_APB2LPENR_EXTITLPEN_Pos) /*!< 0x00008000 */\n#define RCC_APB2LPENR_EXTITLPEN            RCC_APB2LPENR_EXTITLPEN_Msk\n#define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)\n#define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */\n#define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk\n#define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)\n#define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk\n#define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)\n#define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk\n#define RCC_APB2LPENR_SPI5LPEN_Pos         (20U)\n#define RCC_APB2LPENR_SPI5LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */\n#define RCC_APB2LPENR_SPI5LPEN             RCC_APB2LPENR_SPI5LPEN_Msk\n#define RCC_APB2LPENR_DFSDM1LPEN_Pos       (24U)\n#define RCC_APB2LPENR_DFSDM1LPEN_Msk       (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x01000000 */\n#define RCC_APB2LPENR_DFSDM1LPEN           RCC_APB2LPENR_DFSDM1LPEN_Msk\n\n/********************  Bit definition for RCC_BDCR register  ******************/\n#define RCC_BDCR_LSEON_Pos                 (0U)\n#define RCC_BDCR_LSEON_Msk                 (0x1UL << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */\n#define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk\n#define RCC_BDCR_LSERDY_Pos                (1U)\n#define RCC_BDCR_LSERDY_Msk                (0x1UL << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */\n#define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk\n#define RCC_BDCR_LSEBYP_Pos                (2U)\n#define RCC_BDCR_LSEBYP_Msk                (0x1UL << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */\n#define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk\n#define RCC_BDCR_LSEMOD_Pos                (3U)\n#define RCC_BDCR_LSEMOD_Msk                (0x1UL << RCC_BDCR_LSEMOD_Pos)       /*!< 0x00000008 */\n#define RCC_BDCR_LSEMOD                    RCC_BDCR_LSEMOD_Msk\n\n#define RCC_BDCR_RTCSEL_Pos                (8U)\n#define RCC_BDCR_RTCSEL_Msk                (0x3UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */\n#define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk\n#define RCC_BDCR_RTCSEL_0                  (0x1UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */\n#define RCC_BDCR_RTCSEL_1                  (0x2UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */\n\n#define RCC_BDCR_RTCEN_Pos                 (15U)\n#define RCC_BDCR_RTCEN_Msk                 (0x1UL << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */\n#define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk\n#define RCC_BDCR_BDRST_Pos                 (16U)\n#define RCC_BDCR_BDRST_Msk                 (0x1UL << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */\n#define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk\n\n/********************  Bit definition for RCC_CSR register  *******************/\n#define RCC_CSR_LSION_Pos                  (0U)\n#define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */\n#define RCC_CSR_LSION                      RCC_CSR_LSION_Msk\n#define RCC_CSR_LSIRDY_Pos                 (1U)\n#define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */\n#define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk\n#define RCC_CSR_RMVF_Pos                   (24U)\n#define RCC_CSR_RMVF_Msk                   (0x1UL << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */\n#define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk\n#define RCC_CSR_BORRSTF_Pos                (25U)\n#define RCC_CSR_BORRSTF_Msk                (0x1UL << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */\n#define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk\n#define RCC_CSR_PINRSTF_Pos                (26U)\n#define RCC_CSR_PINRSTF_Msk                (0x1UL << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */\n#define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk\n#define RCC_CSR_PORRSTF_Pos                (27U)\n#define RCC_CSR_PORRSTF_Msk                (0x1UL << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */\n#define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk\n#define RCC_CSR_SFTRSTF_Pos                (28U)\n#define RCC_CSR_SFTRSTF_Msk                (0x1UL << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */\n#define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk\n#define RCC_CSR_IWDGRSTF_Pos               (29U)\n#define RCC_CSR_IWDGRSTF_Msk               (0x1UL << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */\n#define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk\n#define RCC_CSR_WWDGRSTF_Pos               (30U)\n#define RCC_CSR_WWDGRSTF_Msk               (0x1UL << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */\n#define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk\n#define RCC_CSR_LPWRRSTF_Pos               (31U)\n#define RCC_CSR_LPWRRSTF_Msk               (0x1UL << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */\n#define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk\n/* Legacy defines */\n#define RCC_CSR_PADRSTF                    RCC_CSR_PINRSTF\n#define RCC_CSR_WDGRSTF                    RCC_CSR_IWDGRSTF\n\n/********************  Bit definition for RCC_SSCGR register  *****************/\n#define RCC_SSCGR_MODPER_Pos               (0U)\n#define RCC_SSCGR_MODPER_Msk               (0x1FFFUL << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */\n#define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk\n#define RCC_SSCGR_INCSTEP_Pos              (13U)\n#define RCC_SSCGR_INCSTEP_Msk              (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */\n#define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk\n#define RCC_SSCGR_SPREADSEL_Pos            (30U)\n#define RCC_SSCGR_SPREADSEL_Msk            (0x1UL << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */\n#define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk\n#define RCC_SSCGR_SSCGEN_Pos               (31U)\n#define RCC_SSCGR_SSCGEN_Msk               (0x1UL << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */\n#define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk\n\n/********************  Bit definition for RCC_PLLI2SCFGR register  ************/\n#define RCC_PLLI2SCFGR_PLLI2SM_Pos         (0U)\n#define RCC_PLLI2SCFGR_PLLI2SM_Msk         (0x3FUL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */\n#define RCC_PLLI2SCFGR_PLLI2SM             RCC_PLLI2SCFGR_PLLI2SM_Msk\n#define RCC_PLLI2SCFGR_PLLI2SM_0           (0x01UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */\n#define RCC_PLLI2SCFGR_PLLI2SM_1           (0x02UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */\n#define RCC_PLLI2SCFGR_PLLI2SM_2           (0x04UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */\n#define RCC_PLLI2SCFGR_PLLI2SM_3           (0x08UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */\n#define RCC_PLLI2SCFGR_PLLI2SM_4           (0x10UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */\n#define RCC_PLLI2SCFGR_PLLI2SM_5           (0x20UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */\n\n#define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)\n#define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */\n#define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk\n#define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */\n#define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */\n#define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */\n#define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */\n#define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */\n#define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */\n#define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */\n\n#define RCC_PLLI2SCFGR_PLLI2SSRC_Pos       (22U)\n#define RCC_PLLI2SCFGR_PLLI2SSRC_Msk       (0x1UL << RCC_PLLI2SCFGR_PLLI2SSRC_Pos) /*!< 0x00400000 */\n#define RCC_PLLI2SCFGR_PLLI2SSRC           RCC_PLLI2SCFGR_PLLI2SSRC_Msk\n#define RCC_PLLI2SCFGR_PLLI2SQ_Pos         (24U)\n#define RCC_PLLI2SCFGR_PLLI2SQ_Msk         (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ             RCC_PLLI2SCFGR_PLLI2SQ_Msk\n#define RCC_PLLI2SCFGR_PLLI2SQ_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_3           (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)\n#define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk\n#define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for RCC_DCKCFGR register  ***************/\n\n#define RCC_DCKCFGR_CKDFSDM1ASEL_Pos       (15U)\n#define RCC_DCKCFGR_CKDFSDM1ASEL_Msk       (0x1UL << RCC_DCKCFGR_CKDFSDM1ASEL_Pos) /*!< 0x00008000 */\n#define RCC_DCKCFGR_CKDFSDM1ASEL           RCC_DCKCFGR_CKDFSDM1ASEL_Msk\n#define RCC_DCKCFGR_TIMPRE_Pos             (24U)\n#define RCC_DCKCFGR_TIMPRE_Msk             (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)    /*!< 0x01000000 */\n#define RCC_DCKCFGR_TIMPRE                 RCC_DCKCFGR_TIMPRE_Msk\n#define RCC_DCKCFGR_I2S1SRC_Pos            (25U)\n#define RCC_DCKCFGR_I2S1SRC_Msk            (0x3UL << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x06000000 */\n#define RCC_DCKCFGR_I2S1SRC                RCC_DCKCFGR_I2S1SRC_Msk\n#define RCC_DCKCFGR_I2S1SRC_0              (0x1UL << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x02000000 */\n#define RCC_DCKCFGR_I2S1SRC_1              (0x2UL << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x04000000 */\n\n#define RCC_DCKCFGR_I2S2SRC_Pos            (27U)\n#define RCC_DCKCFGR_I2S2SRC_Msk            (0x3UL << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x18000000 */\n#define RCC_DCKCFGR_I2S2SRC                RCC_DCKCFGR_I2S2SRC_Msk\n#define RCC_DCKCFGR_I2S2SRC_0              (0x1UL << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x08000000 */\n#define RCC_DCKCFGR_I2S2SRC_1              (0x2UL << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x10000000 */\n#define RCC_DCKCFGR_CKDFSDM1SEL_Pos        (31U)\n#define RCC_DCKCFGR_CKDFSDM1SEL_Msk        (0x1UL << RCC_DCKCFGR_CKDFSDM1SEL_Pos) /*!< 0x80000000 */\n#define RCC_DCKCFGR_CKDFSDM1SEL            RCC_DCKCFGR_CKDFSDM1SEL_Msk\n\n/********************  Bit definition for RCC_CKGATENR register  ***************/\n#define RCC_CKGATENR_AHB2APB1_CKEN_Pos     (0U)\n#define RCC_CKGATENR_AHB2APB1_CKEN_Msk     (0x1UL << RCC_CKGATENR_AHB2APB1_CKEN_Pos) /*!< 0x00000001 */\n#define RCC_CKGATENR_AHB2APB1_CKEN         RCC_CKGATENR_AHB2APB1_CKEN_Msk\n#define RCC_CKGATENR_AHB2APB2_CKEN_Pos     (1U)\n#define RCC_CKGATENR_AHB2APB2_CKEN_Msk     (0x1UL << RCC_CKGATENR_AHB2APB2_CKEN_Pos) /*!< 0x00000002 */\n#define RCC_CKGATENR_AHB2APB2_CKEN         RCC_CKGATENR_AHB2APB2_CKEN_Msk\n#define RCC_CKGATENR_CM4DBG_CKEN_Pos       (2U)\n#define RCC_CKGATENR_CM4DBG_CKEN_Msk       (0x1UL << RCC_CKGATENR_CM4DBG_CKEN_Pos) /*!< 0x00000004 */\n#define RCC_CKGATENR_CM4DBG_CKEN           RCC_CKGATENR_CM4DBG_CKEN_Msk\n#define RCC_CKGATENR_SPARE_CKEN_Pos        (3U)\n#define RCC_CKGATENR_SPARE_CKEN_Msk        (0x1UL << RCC_CKGATENR_SPARE_CKEN_Pos) /*!< 0x00000008 */\n#define RCC_CKGATENR_SPARE_CKEN            RCC_CKGATENR_SPARE_CKEN_Msk\n#define RCC_CKGATENR_SRAM_CKEN_Pos         (4U)\n#define RCC_CKGATENR_SRAM_CKEN_Msk         (0x1UL << RCC_CKGATENR_SRAM_CKEN_Pos) /*!< 0x00000010 */\n#define RCC_CKGATENR_SRAM_CKEN             RCC_CKGATENR_SRAM_CKEN_Msk\n#define RCC_CKGATENR_FLITF_CKEN_Pos        (5U)\n#define RCC_CKGATENR_FLITF_CKEN_Msk        (0x1UL << RCC_CKGATENR_FLITF_CKEN_Pos) /*!< 0x00000020 */\n#define RCC_CKGATENR_FLITF_CKEN            RCC_CKGATENR_FLITF_CKEN_Msk\n#define RCC_CKGATENR_RCC_CKEN_Pos          (6U)\n#define RCC_CKGATENR_RCC_CKEN_Msk          (0x1UL << RCC_CKGATENR_RCC_CKEN_Pos) /*!< 0x00000040 */\n#define RCC_CKGATENR_RCC_CKEN              RCC_CKGATENR_RCC_CKEN_Msk\n#define RCC_CKGATENR_RCC_EVTCTL_Pos        (7U)\n#define RCC_CKGATENR_RCC_EVTCTL_Msk        (0x1UL << RCC_CKGATENR_RCC_EVTCTL_Pos) /*!< 0x00000080 */\n#define RCC_CKGATENR_RCC_EVTCTL            RCC_CKGATENR_RCC_EVTCTL_Msk\n\n/********************  Bit definition for RCC_DCKCFGR2 register  ***************/\n#define RCC_DCKCFGR2_FMPI2C1SEL_Pos        (22U)\n#define RCC_DCKCFGR2_FMPI2C1SEL_Msk        (0x3UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */\n#define RCC_DCKCFGR2_FMPI2C1SEL            RCC_DCKCFGR2_FMPI2C1SEL_Msk\n#define RCC_DCKCFGR2_FMPI2C1SEL_0          (0x1UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */\n#define RCC_DCKCFGR2_FMPI2C1SEL_1          (0x2UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */\n#define RCC_DCKCFGR2_CK48MSEL_Pos          (27U)\n#define RCC_DCKCFGR2_CK48MSEL_Msk          (0x1UL << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */\n#define RCC_DCKCFGR2_CK48MSEL              RCC_DCKCFGR2_CK48MSEL_Msk\n#define RCC_DCKCFGR2_SDIOSEL_Pos           (28U)\n#define RCC_DCKCFGR2_SDIOSEL_Msk           (0x1UL << RCC_DCKCFGR2_SDIOSEL_Pos)  /*!< 0x10000000 */\n#define RCC_DCKCFGR2_SDIOSEL               RCC_DCKCFGR2_SDIOSEL_Msk\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    RNG                                     */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RNG_CR register  *******************/\n#define RNG_CR_RNGEN_Pos    (2U)\n#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */\n#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk\n#define RNG_CR_IE_Pos       (3U)\n#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */\n#define RNG_CR_IE           RNG_CR_IE_Msk\n\n/********************  Bits definition for RNG_SR register  *******************/\n#define RNG_SR_DRDY_Pos     (0U)\n#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */\n#define RNG_SR_DRDY         RNG_SR_DRDY_Msk\n#define RNG_SR_CECS_Pos     (1U)\n#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */\n#define RNG_SR_CECS         RNG_SR_CECS_Msk\n#define RNG_SR_SECS_Pos     (2U)\n#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */\n#define RNG_SR_SECS         RNG_SR_SECS_Msk\n#define RNG_SR_CEIS_Pos     (5U)\n#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */\n#define RNG_SR_CEIS         RNG_SR_CEIS_Msk\n#define RNG_SR_SEIS_Pos     (6U)\n#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */\n#define RNG_SR_SEIS         RNG_SR_SEIS_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Real-Time Clock (RTC)                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RTC_TR register  *******************/\n#define RTC_TR_PM_Pos                 (22U)\n#define RTC_TR_PM_Msk                 (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */\n#define RTC_TR_PM                     RTC_TR_PM_Msk\n#define RTC_TR_HT_Pos                 (20U)\n#define RTC_TR_HT_Msk                 (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */\n#define RTC_TR_HT                     RTC_TR_HT_Msk\n#define RTC_TR_HT_0                   (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */\n#define RTC_TR_HT_1                   (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */\n#define RTC_TR_HU_Pos                 (16U)\n#define RTC_TR_HU_Msk                 (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */\n#define RTC_TR_HU                     RTC_TR_HU_Msk\n#define RTC_TR_HU_0                   (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */\n#define RTC_TR_HU_1                   (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */\n#define RTC_TR_HU_2                   (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */\n#define RTC_TR_HU_3                   (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */\n#define RTC_TR_MNT_Pos                (12U)\n#define RTC_TR_MNT_Msk                (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */\n#define RTC_TR_MNT                    RTC_TR_MNT_Msk\n#define RTC_TR_MNT_0                  (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */\n#define RTC_TR_MNT_1                  (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */\n#define RTC_TR_MNT_2                  (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */\n#define RTC_TR_MNU_Pos                (8U)\n#define RTC_TR_MNU_Msk                (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */\n#define RTC_TR_MNU                    RTC_TR_MNU_Msk\n#define RTC_TR_MNU_0                  (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */\n#define RTC_TR_MNU_1                  (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */\n#define RTC_TR_MNU_2                  (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */\n#define RTC_TR_MNU_3                  (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */\n#define RTC_TR_ST_Pos                 (4U)\n#define RTC_TR_ST_Msk                 (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */\n#define RTC_TR_ST                     RTC_TR_ST_Msk\n#define RTC_TR_ST_0                   (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */\n#define RTC_TR_ST_1                   (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */\n#define RTC_TR_ST_2                   (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */\n#define RTC_TR_SU_Pos                 (0U)\n#define RTC_TR_SU_Msk                 (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */\n#define RTC_TR_SU                     RTC_TR_SU_Msk\n#define RTC_TR_SU_0                   (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */\n#define RTC_TR_SU_1                   (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */\n#define RTC_TR_SU_2                   (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */\n#define RTC_TR_SU_3                   (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_DR register  *******************/\n#define RTC_DR_YT_Pos                 (20U)\n#define RTC_DR_YT_Msk                 (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */\n#define RTC_DR_YT                     RTC_DR_YT_Msk\n#define RTC_DR_YT_0                   (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */\n#define RTC_DR_YT_1                   (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */\n#define RTC_DR_YT_2                   (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */\n#define RTC_DR_YT_3                   (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */\n#define RTC_DR_YU_Pos                 (16U)\n#define RTC_DR_YU_Msk                 (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */\n#define RTC_DR_YU                     RTC_DR_YU_Msk\n#define RTC_DR_YU_0                   (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */\n#define RTC_DR_YU_1                   (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */\n#define RTC_DR_YU_2                   (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */\n#define RTC_DR_YU_3                   (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */\n#define RTC_DR_WDU_Pos                (13U)\n#define RTC_DR_WDU_Msk                (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */\n#define RTC_DR_WDU                    RTC_DR_WDU_Msk\n#define RTC_DR_WDU_0                  (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */\n#define RTC_DR_WDU_1                  (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */\n#define RTC_DR_WDU_2                  (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */\n#define RTC_DR_MT_Pos                 (12U)\n#define RTC_DR_MT_Msk                 (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */\n#define RTC_DR_MT                     RTC_DR_MT_Msk\n#define RTC_DR_MU_Pos                 (8U)\n#define RTC_DR_MU_Msk                 (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */\n#define RTC_DR_MU                     RTC_DR_MU_Msk\n#define RTC_DR_MU_0                   (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */\n#define RTC_DR_MU_1                   (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */\n#define RTC_DR_MU_2                   (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */\n#define RTC_DR_MU_3                   (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */\n#define RTC_DR_DT_Pos                 (4U)\n#define RTC_DR_DT_Msk                 (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */\n#define RTC_DR_DT                     RTC_DR_DT_Msk\n#define RTC_DR_DT_0                   (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */\n#define RTC_DR_DT_1                   (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */\n#define RTC_DR_DU_Pos                 (0U)\n#define RTC_DR_DU_Msk                 (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */\n#define RTC_DR_DU                     RTC_DR_DU_Msk\n#define RTC_DR_DU_0                   (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */\n#define RTC_DR_DU_1                   (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */\n#define RTC_DR_DU_2                   (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */\n#define RTC_DR_DU_3                   (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_CR register  *******************/\n#define RTC_CR_COE_Pos                (23U)\n#define RTC_CR_COE_Msk                (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */\n#define RTC_CR_COE                    RTC_CR_COE_Msk\n#define RTC_CR_OSEL_Pos               (21U)\n#define RTC_CR_OSEL_Msk               (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */\n#define RTC_CR_OSEL                   RTC_CR_OSEL_Msk\n#define RTC_CR_OSEL_0                 (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */\n#define RTC_CR_OSEL_1                 (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */\n#define RTC_CR_POL_Pos                (20U)\n#define RTC_CR_POL_Msk                (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */\n#define RTC_CR_POL                    RTC_CR_POL_Msk\n#define RTC_CR_COSEL_Pos              (19U)\n#define RTC_CR_COSEL_Msk              (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */\n#define RTC_CR_COSEL                  RTC_CR_COSEL_Msk\n#define RTC_CR_BKP_Pos                 (18U)\n#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */\n#define RTC_CR_BKP                     RTC_CR_BKP_Msk\n#define RTC_CR_SUB1H_Pos              (17U)\n#define RTC_CR_SUB1H_Msk              (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */\n#define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk\n#define RTC_CR_ADD1H_Pos              (16U)\n#define RTC_CR_ADD1H_Msk              (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */\n#define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk\n#define RTC_CR_TSIE_Pos               (15U)\n#define RTC_CR_TSIE_Msk               (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */\n#define RTC_CR_TSIE                   RTC_CR_TSIE_Msk\n#define RTC_CR_WUTIE_Pos              (14U)\n#define RTC_CR_WUTIE_Msk              (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */\n#define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk\n#define RTC_CR_ALRBIE_Pos             (13U)\n#define RTC_CR_ALRBIE_Msk             (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */\n#define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk\n#define RTC_CR_ALRAIE_Pos             (12U)\n#define RTC_CR_ALRAIE_Msk             (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */\n#define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk\n#define RTC_CR_TSE_Pos                (11U)\n#define RTC_CR_TSE_Msk                (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */\n#define RTC_CR_TSE                    RTC_CR_TSE_Msk\n#define RTC_CR_WUTE_Pos               (10U)\n#define RTC_CR_WUTE_Msk               (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */\n#define RTC_CR_WUTE                   RTC_CR_WUTE_Msk\n#define RTC_CR_ALRBE_Pos              (9U)\n#define RTC_CR_ALRBE_Msk              (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */\n#define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk\n#define RTC_CR_ALRAE_Pos              (8U)\n#define RTC_CR_ALRAE_Msk              (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */\n#define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk\n#define RTC_CR_DCE_Pos                (7U)\n#define RTC_CR_DCE_Msk                (0x1UL << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */\n#define RTC_CR_DCE                    RTC_CR_DCE_Msk\n#define RTC_CR_FMT_Pos                (6U)\n#define RTC_CR_FMT_Msk                (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */\n#define RTC_CR_FMT                    RTC_CR_FMT_Msk\n#define RTC_CR_BYPSHAD_Pos            (5U)\n#define RTC_CR_BYPSHAD_Msk            (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */\n#define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk\n#define RTC_CR_REFCKON_Pos            (4U)\n#define RTC_CR_REFCKON_Msk            (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */\n#define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk\n#define RTC_CR_TSEDGE_Pos             (3U)\n#define RTC_CR_TSEDGE_Msk             (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */\n#define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk\n#define RTC_CR_WUCKSEL_Pos            (0U)\n#define RTC_CR_WUCKSEL_Msk            (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */\n#define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk\n#define RTC_CR_WUCKSEL_0              (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */\n#define RTC_CR_WUCKSEL_1              (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */\n#define RTC_CR_WUCKSEL_2              (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */\n\n/* Legacy defines */\n#define RTC_CR_BCK                     RTC_CR_BKP\n\n/********************  Bits definition for RTC_ISR register  ******************/\n#define RTC_ISR_RECALPF_Pos           (16U)\n#define RTC_ISR_RECALPF_Msk           (0x1UL << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */\n#define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk\n#define RTC_ISR_TAMP1F_Pos            (13U)\n#define RTC_ISR_TAMP1F_Msk            (0x1UL << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */\n#define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk\n#define RTC_ISR_TAMP2F_Pos            (14U)\n#define RTC_ISR_TAMP2F_Msk            (0x1UL << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */\n#define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk\n#define RTC_ISR_TSOVF_Pos             (12U)\n#define RTC_ISR_TSOVF_Msk             (0x1UL << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */\n#define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk\n#define RTC_ISR_TSF_Pos               (11U)\n#define RTC_ISR_TSF_Msk               (0x1UL << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */\n#define RTC_ISR_TSF                   RTC_ISR_TSF_Msk\n#define RTC_ISR_WUTF_Pos              (10U)\n#define RTC_ISR_WUTF_Msk              (0x1UL << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */\n#define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk\n#define RTC_ISR_ALRBF_Pos             (9U)\n#define RTC_ISR_ALRBF_Msk             (0x1UL << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */\n#define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk\n#define RTC_ISR_ALRAF_Pos             (8U)\n#define RTC_ISR_ALRAF_Msk             (0x1UL << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */\n#define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk\n#define RTC_ISR_INIT_Pos              (7U)\n#define RTC_ISR_INIT_Msk              (0x1UL << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */\n#define RTC_ISR_INIT                  RTC_ISR_INIT_Msk\n#define RTC_ISR_INITF_Pos             (6U)\n#define RTC_ISR_INITF_Msk             (0x1UL << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */\n#define RTC_ISR_INITF                 RTC_ISR_INITF_Msk\n#define RTC_ISR_RSF_Pos               (5U)\n#define RTC_ISR_RSF_Msk               (0x1UL << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */\n#define RTC_ISR_RSF                   RTC_ISR_RSF_Msk\n#define RTC_ISR_INITS_Pos             (4U)\n#define RTC_ISR_INITS_Msk             (0x1UL << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */\n#define RTC_ISR_INITS                 RTC_ISR_INITS_Msk\n#define RTC_ISR_SHPF_Pos              (3U)\n#define RTC_ISR_SHPF_Msk              (0x1UL << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */\n#define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk\n#define RTC_ISR_WUTWF_Pos             (2U)\n#define RTC_ISR_WUTWF_Msk             (0x1UL << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */\n#define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk\n#define RTC_ISR_ALRBWF_Pos            (1U)\n#define RTC_ISR_ALRBWF_Msk            (0x1UL << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */\n#define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk\n#define RTC_ISR_ALRAWF_Pos            (0U)\n#define RTC_ISR_ALRAWF_Msk            (0x1UL << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */\n#define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk\n\n/********************  Bits definition for RTC_PRER register  *****************/\n#define RTC_PRER_PREDIV_A_Pos         (16U)\n#define RTC_PRER_PREDIV_A_Msk         (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */\n#define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk\n#define RTC_PRER_PREDIV_S_Pos         (0U)\n#define RTC_PRER_PREDIV_S_Msk         (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */\n#define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk\n\n/********************  Bits definition for RTC_WUTR register  *****************/\n#define RTC_WUTR_WUT_Pos              (0U)\n#define RTC_WUTR_WUT_Msk              (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */\n#define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk\n\n/********************  Bits definition for RTC_CALIBR register  ***************/\n#define RTC_CALIBR_DCS_Pos            (7U)\n#define RTC_CALIBR_DCS_Msk            (0x1UL << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */\n#define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk\n#define RTC_CALIBR_DC_Pos             (0U)\n#define RTC_CALIBR_DC_Msk             (0x1FUL << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */\n#define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk\n\n/********************  Bits definition for RTC_ALRMAR register  ***************/\n#define RTC_ALRMAR_MSK4_Pos           (31U)\n#define RTC_ALRMAR_MSK4_Msk           (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk\n#define RTC_ALRMAR_WDSEL_Pos          (30U)\n#define RTC_ALRMAR_WDSEL_Msk          (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk\n#define RTC_ALRMAR_DT_Pos             (28U)\n#define RTC_ALRMAR_DT_Msk             (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk\n#define RTC_ALRMAR_DT_0               (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMAR_DT_1               (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMAR_DU_Pos             (24U)\n#define RTC_ALRMAR_DU_Msk             (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk\n#define RTC_ALRMAR_DU_0               (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMAR_DU_1               (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMAR_DU_2               (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMAR_DU_3               (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMAR_MSK3_Pos           (23U)\n#define RTC_ALRMAR_MSK3_Msk           (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk\n#define RTC_ALRMAR_PM_Pos             (22U)\n#define RTC_ALRMAR_PM_Msk             (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk\n#define RTC_ALRMAR_HT_Pos             (20U)\n#define RTC_ALRMAR_HT_Msk             (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk\n#define RTC_ALRMAR_HT_0               (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMAR_HT_1               (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMAR_HU_Pos             (16U)\n#define RTC_ALRMAR_HU_Msk             (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk\n#define RTC_ALRMAR_HU_0               (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMAR_HU_1               (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMAR_HU_2               (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMAR_HU_3               (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMAR_MSK2_Pos           (15U)\n#define RTC_ALRMAR_MSK2_Msk           (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk\n#define RTC_ALRMAR_MNT_Pos            (12U)\n#define RTC_ALRMAR_MNT_Msk            (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk\n#define RTC_ALRMAR_MNT_0              (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMAR_MNT_1              (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMAR_MNT_2              (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMAR_MNU_Pos            (8U)\n#define RTC_ALRMAR_MNU_Msk            (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk\n#define RTC_ALRMAR_MNU_0              (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMAR_MNU_1              (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMAR_MNU_2              (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMAR_MNU_3              (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMAR_MSK1_Pos           (7U)\n#define RTC_ALRMAR_MSK1_Msk           (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk\n#define RTC_ALRMAR_ST_Pos             (4U)\n#define RTC_ALRMAR_ST_Msk             (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk\n#define RTC_ALRMAR_ST_0               (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMAR_ST_1               (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMAR_ST_2               (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMAR_SU_Pos             (0U)\n#define RTC_ALRMAR_SU_Msk             (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk\n#define RTC_ALRMAR_SU_0               (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMAR_SU_1               (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMAR_SU_2               (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMAR_SU_3               (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_ALRMBR register  ***************/\n#define RTC_ALRMBR_MSK4_Pos           (31U)\n#define RTC_ALRMBR_MSK4_Msk           (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk\n#define RTC_ALRMBR_WDSEL_Pos          (30U)\n#define RTC_ALRMBR_WDSEL_Msk          (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk\n#define RTC_ALRMBR_DT_Pos             (28U)\n#define RTC_ALRMBR_DT_Msk             (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk\n#define RTC_ALRMBR_DT_0               (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMBR_DT_1               (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMBR_DU_Pos             (24U)\n#define RTC_ALRMBR_DU_Msk             (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk\n#define RTC_ALRMBR_DU_0               (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMBR_DU_1               (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMBR_DU_2               (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMBR_DU_3               (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMBR_MSK3_Pos           (23U)\n#define RTC_ALRMBR_MSK3_Msk           (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk\n#define RTC_ALRMBR_PM_Pos             (22U)\n#define RTC_ALRMBR_PM_Msk             (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk\n#define RTC_ALRMBR_HT_Pos             (20U)\n#define RTC_ALRMBR_HT_Msk             (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk\n#define RTC_ALRMBR_HT_0               (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMBR_HT_1               (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMBR_HU_Pos             (16U)\n#define RTC_ALRMBR_HU_Msk             (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk\n#define RTC_ALRMBR_HU_0               (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMBR_HU_1               (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMBR_HU_2               (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMBR_HU_3               (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMBR_MSK2_Pos           (15U)\n#define RTC_ALRMBR_MSK2_Msk           (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk\n#define RTC_ALRMBR_MNT_Pos            (12U)\n#define RTC_ALRMBR_MNT_Msk            (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk\n#define RTC_ALRMBR_MNT_0              (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMBR_MNT_1              (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMBR_MNT_2              (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMBR_MNU_Pos            (8U)\n#define RTC_ALRMBR_MNU_Msk            (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk\n#define RTC_ALRMBR_MNU_0              (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMBR_MNU_1              (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMBR_MNU_2              (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMBR_MNU_3              (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMBR_MSK1_Pos           (7U)\n#define RTC_ALRMBR_MSK1_Msk           (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk\n#define RTC_ALRMBR_ST_Pos             (4U)\n#define RTC_ALRMBR_ST_Msk             (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk\n#define RTC_ALRMBR_ST_0               (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMBR_ST_1               (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMBR_ST_2               (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMBR_SU_Pos             (0U)\n#define RTC_ALRMBR_SU_Msk             (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk\n#define RTC_ALRMBR_SU_0               (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMBR_SU_1               (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMBR_SU_2               (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMBR_SU_3               (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_WPR register  ******************/\n#define RTC_WPR_KEY_Pos               (0U)\n#define RTC_WPR_KEY_Msk               (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */\n#define RTC_WPR_KEY                   RTC_WPR_KEY_Msk\n\n/********************  Bits definition for RTC_SSR register  ******************/\n#define RTC_SSR_SS_Pos                (0U)\n#define RTC_SSR_SS_Msk                (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */\n#define RTC_SSR_SS                    RTC_SSR_SS_Msk\n\n/********************  Bits definition for RTC_SHIFTR register  ***************/\n#define RTC_SHIFTR_SUBFS_Pos          (0U)\n#define RTC_SHIFTR_SUBFS_Msk          (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */\n#define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk\n#define RTC_SHIFTR_ADD1S_Pos          (31U)\n#define RTC_SHIFTR_ADD1S_Msk          (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */\n#define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk\n\n/********************  Bits definition for RTC_TSTR register  *****************/\n#define RTC_TSTR_PM_Pos               (22U)\n#define RTC_TSTR_PM_Msk               (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */\n#define RTC_TSTR_PM                   RTC_TSTR_PM_Msk\n#define RTC_TSTR_HT_Pos               (20U)\n#define RTC_TSTR_HT_Msk               (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */\n#define RTC_TSTR_HT                   RTC_TSTR_HT_Msk\n#define RTC_TSTR_HT_0                 (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */\n#define RTC_TSTR_HT_1                 (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */\n#define RTC_TSTR_HU_Pos               (16U)\n#define RTC_TSTR_HU_Msk               (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */\n#define RTC_TSTR_HU                   RTC_TSTR_HU_Msk\n#define RTC_TSTR_HU_0                 (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */\n#define RTC_TSTR_HU_1                 (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */\n#define RTC_TSTR_HU_2                 (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */\n#define RTC_TSTR_HU_3                 (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */\n#define RTC_TSTR_MNT_Pos              (12U)\n#define RTC_TSTR_MNT_Msk              (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */\n#define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk\n#define RTC_TSTR_MNT_0                (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */\n#define RTC_TSTR_MNT_1                (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */\n#define RTC_TSTR_MNT_2                (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */\n#define RTC_TSTR_MNU_Pos              (8U)\n#define RTC_TSTR_MNU_Msk              (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */\n#define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk\n#define RTC_TSTR_MNU_0                (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */\n#define RTC_TSTR_MNU_1                (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */\n#define RTC_TSTR_MNU_2                (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */\n#define RTC_TSTR_MNU_3                (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */\n#define RTC_TSTR_ST_Pos               (4U)\n#define RTC_TSTR_ST_Msk               (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */\n#define RTC_TSTR_ST                   RTC_TSTR_ST_Msk\n#define RTC_TSTR_ST_0                 (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */\n#define RTC_TSTR_ST_1                 (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */\n#define RTC_TSTR_ST_2                 (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */\n#define RTC_TSTR_SU_Pos               (0U)\n#define RTC_TSTR_SU_Msk               (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */\n#define RTC_TSTR_SU                   RTC_TSTR_SU_Msk\n#define RTC_TSTR_SU_0                 (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */\n#define RTC_TSTR_SU_1                 (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */\n#define RTC_TSTR_SU_2                 (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */\n#define RTC_TSTR_SU_3                 (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSDR register  *****************/\n#define RTC_TSDR_WDU_Pos              (13U)\n#define RTC_TSDR_WDU_Msk              (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */\n#define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk\n#define RTC_TSDR_WDU_0                (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */\n#define RTC_TSDR_WDU_1                (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */\n#define RTC_TSDR_WDU_2                (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */\n#define RTC_TSDR_MT_Pos               (12U)\n#define RTC_TSDR_MT_Msk               (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */\n#define RTC_TSDR_MT                   RTC_TSDR_MT_Msk\n#define RTC_TSDR_MU_Pos               (8U)\n#define RTC_TSDR_MU_Msk               (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */\n#define RTC_TSDR_MU                   RTC_TSDR_MU_Msk\n#define RTC_TSDR_MU_0                 (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */\n#define RTC_TSDR_MU_1                 (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */\n#define RTC_TSDR_MU_2                 (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */\n#define RTC_TSDR_MU_3                 (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */\n#define RTC_TSDR_DT_Pos               (4U)\n#define RTC_TSDR_DT_Msk               (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */\n#define RTC_TSDR_DT                   RTC_TSDR_DT_Msk\n#define RTC_TSDR_DT_0                 (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */\n#define RTC_TSDR_DT_1                 (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */\n#define RTC_TSDR_DU_Pos               (0U)\n#define RTC_TSDR_DU_Msk               (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */\n#define RTC_TSDR_DU                   RTC_TSDR_DU_Msk\n#define RTC_TSDR_DU_0                 (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */\n#define RTC_TSDR_DU_1                 (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */\n#define RTC_TSDR_DU_2                 (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */\n#define RTC_TSDR_DU_3                 (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSSSR register  ****************/\n#define RTC_TSSSR_SS_Pos              (0U)\n#define RTC_TSSSR_SS_Msk              (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */\n#define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk\n\n/********************  Bits definition for RTC_CAL register  *****************/\n#define RTC_CALR_CALP_Pos             (15U)\n#define RTC_CALR_CALP_Msk             (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */\n#define RTC_CALR_CALP                 RTC_CALR_CALP_Msk\n#define RTC_CALR_CALW8_Pos            (14U)\n#define RTC_CALR_CALW8_Msk            (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */\n#define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk\n#define RTC_CALR_CALW16_Pos           (13U)\n#define RTC_CALR_CALW16_Msk           (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */\n#define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk\n#define RTC_CALR_CALM_Pos             (0U)\n#define RTC_CALR_CALM_Msk             (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */\n#define RTC_CALR_CALM                 RTC_CALR_CALM_Msk\n#define RTC_CALR_CALM_0               (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */\n#define RTC_CALR_CALM_1               (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */\n#define RTC_CALR_CALM_2               (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */\n#define RTC_CALR_CALM_3               (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */\n#define RTC_CALR_CALM_4               (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */\n#define RTC_CALR_CALM_5               (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */\n#define RTC_CALR_CALM_6               (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */\n#define RTC_CALR_CALM_7               (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */\n#define RTC_CALR_CALM_8               (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */\n\n/********************  Bits definition for RTC_TAFCR register  ****************/\n#define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)\n#define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */\n#define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk\n#define RTC_TAFCR_TSINSEL_Pos         (17U)\n#define RTC_TAFCR_TSINSEL_Msk         (0x1UL << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */\n#define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk\n#define RTC_TAFCR_TAMP1INSEL_Pos      (16U)\n#define RTC_TAFCR_TAMP1INSEL_Msk      (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)        /*!< 0x00010000 */\n#define RTC_TAFCR_TAMP1INSEL          RTC_TAFCR_TAMP1INSEL_Msk\n#define RTC_TAFCR_TAMPPUDIS_Pos       (15U)\n#define RTC_TAFCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */\n#define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk\n#define RTC_TAFCR_TAMPPRCH_Pos        (13U)\n#define RTC_TAFCR_TAMPPRCH_Msk        (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */\n#define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk\n#define RTC_TAFCR_TAMPPRCH_0          (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */\n#define RTC_TAFCR_TAMPPRCH_1          (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */\n#define RTC_TAFCR_TAMPFLT_Pos         (11U)\n#define RTC_TAFCR_TAMPFLT_Msk         (0x3UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */\n#define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk\n#define RTC_TAFCR_TAMPFLT_0           (0x1UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */\n#define RTC_TAFCR_TAMPFLT_1           (0x2UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */\n#define RTC_TAFCR_TAMPFREQ_Pos        (8U)\n#define RTC_TAFCR_TAMPFREQ_Msk        (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */\n#define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk\n#define RTC_TAFCR_TAMPFREQ_0          (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */\n#define RTC_TAFCR_TAMPFREQ_1          (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */\n#define RTC_TAFCR_TAMPFREQ_2          (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */\n#define RTC_TAFCR_TAMPTS_Pos          (7U)\n#define RTC_TAFCR_TAMPTS_Msk          (0x1UL << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */\n#define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk\n#define RTC_TAFCR_TAMP2TRG_Pos        (4U)\n#define RTC_TAFCR_TAMP2TRG_Msk        (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */\n#define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk\n#define RTC_TAFCR_TAMP2E_Pos          (3U)\n#define RTC_TAFCR_TAMP2E_Msk          (0x1UL << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */\n#define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk\n#define RTC_TAFCR_TAMPIE_Pos          (2U)\n#define RTC_TAFCR_TAMPIE_Msk          (0x1UL << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */\n#define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk\n#define RTC_TAFCR_TAMP1TRG_Pos        (1U)\n#define RTC_TAFCR_TAMP1TRG_Msk        (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */\n#define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk\n#define RTC_TAFCR_TAMP1E_Pos          (0U)\n#define RTC_TAFCR_TAMP1E_Msk          (0x1UL << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */\n#define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk\n\n/* Legacy defines */\n#define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMP1INSEL\n\n/********************  Bits definition for RTC_ALRMASSR register  *************/\n#define RTC_ALRMASSR_MASKSS_Pos       (24U)\n#define RTC_ALRMASSR_MASKSS_Msk       (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk\n#define RTC_ALRMASSR_MASKSS_0         (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMASSR_MASKSS_1         (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMASSR_MASKSS_2         (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMASSR_MASKSS_3         (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMASSR_SS_Pos           (0U)\n#define RTC_ALRMASSR_SS_Msk           (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk\n\n/********************  Bits definition for RTC_ALRMBSSR register  *************/\n#define RTC_ALRMBSSR_MASKSS_Pos       (24U)\n#define RTC_ALRMBSSR_MASKSS_Msk       (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk\n#define RTC_ALRMBSSR_MASKSS_0         (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMBSSR_MASKSS_1         (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMBSSR_MASKSS_2         (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMBSSR_MASKSS_3         (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMBSSR_SS_Pos           (0U)\n#define RTC_ALRMBSSR_SS_Msk           (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk\n\n/********************  Bits definition for RTC_BKP0R register  ****************/\n#define RTC_BKP0R_Pos                 (0U)\n#define RTC_BKP0R_Msk                 (0xFFFFFFFFUL << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP0R                     RTC_BKP0R_Msk\n\n/********************  Bits definition for RTC_BKP1R register  ****************/\n#define RTC_BKP1R_Pos                 (0U)\n#define RTC_BKP1R_Msk                 (0xFFFFFFFFUL << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP1R                     RTC_BKP1R_Msk\n\n/********************  Bits definition for RTC_BKP2R register  ****************/\n#define RTC_BKP2R_Pos                 (0U)\n#define RTC_BKP2R_Msk                 (0xFFFFFFFFUL << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP2R                     RTC_BKP2R_Msk\n\n/********************  Bits definition for RTC_BKP3R register  ****************/\n#define RTC_BKP3R_Pos                 (0U)\n#define RTC_BKP3R_Msk                 (0xFFFFFFFFUL << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP3R                     RTC_BKP3R_Msk\n\n/********************  Bits definition for RTC_BKP4R register  ****************/\n#define RTC_BKP4R_Pos                 (0U)\n#define RTC_BKP4R_Msk                 (0xFFFFFFFFUL << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP4R                     RTC_BKP4R_Msk\n\n/********************  Bits definition for RTC_BKP5R register  ****************/\n#define RTC_BKP5R_Pos                 (0U)\n#define RTC_BKP5R_Msk                 (0xFFFFFFFFUL << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP5R                     RTC_BKP5R_Msk\n\n/********************  Bits definition for RTC_BKP6R register  ****************/\n#define RTC_BKP6R_Pos                 (0U)\n#define RTC_BKP6R_Msk                 (0xFFFFFFFFUL << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP6R                     RTC_BKP6R_Msk\n\n/********************  Bits definition for RTC_BKP7R register  ****************/\n#define RTC_BKP7R_Pos                 (0U)\n#define RTC_BKP7R_Msk                 (0xFFFFFFFFUL << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP7R                     RTC_BKP7R_Msk\n\n/********************  Bits definition for RTC_BKP8R register  ****************/\n#define RTC_BKP8R_Pos                 (0U)\n#define RTC_BKP8R_Msk                 (0xFFFFFFFFUL << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP8R                     RTC_BKP8R_Msk\n\n/********************  Bits definition for RTC_BKP9R register  ****************/\n#define RTC_BKP9R_Pos                 (0U)\n#define RTC_BKP9R_Msk                 (0xFFFFFFFFUL << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP9R                     RTC_BKP9R_Msk\n\n/********************  Bits definition for RTC_BKP10R register  ***************/\n#define RTC_BKP10R_Pos                (0U)\n#define RTC_BKP10R_Msk                (0xFFFFFFFFUL << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP10R                    RTC_BKP10R_Msk\n\n/********************  Bits definition for RTC_BKP11R register  ***************/\n#define RTC_BKP11R_Pos                (0U)\n#define RTC_BKP11R_Msk                (0xFFFFFFFFUL << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP11R                    RTC_BKP11R_Msk\n\n/********************  Bits definition for RTC_BKP12R register  ***************/\n#define RTC_BKP12R_Pos                (0U)\n#define RTC_BKP12R_Msk                (0xFFFFFFFFUL << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP12R                    RTC_BKP12R_Msk\n\n/********************  Bits definition for RTC_BKP13R register  ***************/\n#define RTC_BKP13R_Pos                (0U)\n#define RTC_BKP13R_Msk                (0xFFFFFFFFUL << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP13R                    RTC_BKP13R_Msk\n\n/********************  Bits definition for RTC_BKP14R register  ***************/\n#define RTC_BKP14R_Pos                (0U)\n#define RTC_BKP14R_Msk                (0xFFFFFFFFUL << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP14R                    RTC_BKP14R_Msk\n\n/********************  Bits definition for RTC_BKP15R register  ***************/\n#define RTC_BKP15R_Pos                (0U)\n#define RTC_BKP15R_Msk                (0xFFFFFFFFUL << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP15R                    RTC_BKP15R_Msk\n\n/********************  Bits definition for RTC_BKP16R register  ***************/\n#define RTC_BKP16R_Pos                (0U)\n#define RTC_BKP16R_Msk                (0xFFFFFFFFUL << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP16R                    RTC_BKP16R_Msk\n\n/********************  Bits definition for RTC_BKP17R register  ***************/\n#define RTC_BKP17R_Pos                (0U)\n#define RTC_BKP17R_Msk                (0xFFFFFFFFUL << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP17R                    RTC_BKP17R_Msk\n\n/********************  Bits definition for RTC_BKP18R register  ***************/\n#define RTC_BKP18R_Pos                (0U)\n#define RTC_BKP18R_Msk                (0xFFFFFFFFUL << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP18R                    RTC_BKP18R_Msk\n\n/********************  Bits definition for RTC_BKP19R register  ***************/\n#define RTC_BKP19R_Pos                (0U)\n#define RTC_BKP19R_Msk                (0xFFFFFFFFUL << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP19R                    RTC_BKP19R_Msk\n\n/******************** Number of backup registers ******************************/\n#define RTC_BKP_NUMBER                       0x000000014U\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                          SD host Interface                                 */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SDIO_POWER register  ******************/\n#define SDIO_POWER_PWRCTRL_Pos         (0U)\n#define SDIO_POWER_PWRCTRL_Msk         (0x3UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */\n#define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */\n#define SDIO_POWER_PWRCTRL_0           (0x1UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x01 */\n#define SDIO_POWER_PWRCTRL_1           (0x2UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x02 */\n\n/******************  Bit definition for SDIO_CLKCR register  ******************/\n#define SDIO_CLKCR_CLKDIV_Pos          (0U)\n#define SDIO_CLKCR_CLKDIV_Msk          (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */\n#define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor             */\n#define SDIO_CLKCR_CLKEN_Pos           (8U)\n#define SDIO_CLKCR_CLKEN_Msk           (0x1UL << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */\n#define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit                */\n#define SDIO_CLKCR_PWRSAV_Pos          (9U)\n#define SDIO_CLKCR_PWRSAV_Msk          (0x1UL << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */\n#define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit  */\n#define SDIO_CLKCR_BYPASS_Pos          (10U)\n#define SDIO_CLKCR_BYPASS_Msk          (0x1UL << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */\n#define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */\n\n#define SDIO_CLKCR_WIDBUS_Pos          (11U)\n#define SDIO_CLKCR_WIDBUS_Msk          (0x3UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */\n#define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\n#define SDIO_CLKCR_WIDBUS_0            (0x1UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x0800 */\n#define SDIO_CLKCR_WIDBUS_1            (0x2UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x1000 */\n\n#define SDIO_CLKCR_NEGEDGE_Pos         (13U)\n#define SDIO_CLKCR_NEGEDGE_Msk         (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */\n#define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */\n#define SDIO_CLKCR_HWFC_EN_Pos         (14U)\n#define SDIO_CLKCR_HWFC_EN_Msk         (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */\n#define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable          */\n\n/*******************  Bit definition for SDIO_ARG register  *******************/\n#define SDIO_ARG_CMDARG_Pos            (0U)\n#define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */\n#define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */\n\n/*******************  Bit definition for SDIO_CMD register  *******************/\n#define SDIO_CMD_CMDINDEX_Pos          (0U)\n#define SDIO_CMD_CMDINDEX_Msk          (0x3FUL << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */\n#define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index                               */\n\n#define SDIO_CMD_WAITRESP_Pos          (6U)\n#define SDIO_CMD_WAITRESP_Msk          (0x3UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */\n#define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */\n#define SDIO_CMD_WAITRESP_0            (0x1UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0040 */\n#define SDIO_CMD_WAITRESP_1            (0x2UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0080 */\n\n#define SDIO_CMD_WAITINT_Pos           (8U)\n#define SDIO_CMD_WAITINT_Msk           (0x1UL << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */\n#define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request                               */\n#define SDIO_CMD_WAITPEND_Pos          (9U)\n#define SDIO_CMD_WAITPEND_Msk          (0x1UL << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */\n#define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\n#define SDIO_CMD_CPSMEN_Pos            (10U)\n#define SDIO_CMD_CPSMEN_Msk            (0x1UL << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */\n#define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit                   */\n#define SDIO_CMD_SDIOSUSPEND_Pos       (11U)\n#define SDIO_CMD_SDIOSUSPEND_Msk       (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */\n#define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command                                         */\n\n/*****************  Bit definition for SDIO_RESPCMD register  *****************/\n#define SDIO_RESPCMD_RESPCMD_Pos       (0U)\n#define SDIO_RESPCMD_RESPCMD_Msk       (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */\n#define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */\n\n/******************  Bit definition for SDIO_RESP0 register  ******************/\n#define SDIO_RESP0_CARDSTATUS0_Pos     (0U)\n#define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP1 register  ******************/\n#define SDIO_RESP1_CARDSTATUS1_Pos     (0U)\n#define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP2 register  ******************/\n#define SDIO_RESP2_CARDSTATUS2_Pos     (0U)\n#define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP3 register  ******************/\n#define SDIO_RESP3_CARDSTATUS3_Pos     (0U)\n#define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP4 register  ******************/\n#define SDIO_RESP4_CARDSTATUS4_Pos     (0U)\n#define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_DTIMER register  *****************/\n#define SDIO_DTIMER_DATATIME_Pos       (0U)\n#define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */\n\n/******************  Bit definition for SDIO_DLEN register  *******************/\n#define SDIO_DLEN_DATALENGTH_Pos       (0U)\n#define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */\n\n/******************  Bit definition for SDIO_DCTRL register  ******************/\n#define SDIO_DCTRL_DTEN_Pos            (0U)\n#define SDIO_DCTRL_DTEN_Msk            (0x1UL << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */\n#define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit         */\n#define SDIO_DCTRL_DTDIR_Pos           (1U)\n#define SDIO_DCTRL_DTDIR_Msk           (0x1UL << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */\n#define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */\n#define SDIO_DCTRL_DTMODE_Pos          (2U)\n#define SDIO_DCTRL_DTMODE_Msk          (0x1UL << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */\n#define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection      */\n#define SDIO_DCTRL_DMAEN_Pos           (3U)\n#define SDIO_DCTRL_DMAEN_Msk           (0x1UL << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */\n#define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit                   */\n\n#define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)\n#define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */\n#define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */\n#define SDIO_DCTRL_DBLOCKSIZE_0        (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0010 */\n#define SDIO_DCTRL_DBLOCKSIZE_1        (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0020 */\n#define SDIO_DCTRL_DBLOCKSIZE_2        (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0040 */\n#define SDIO_DCTRL_DBLOCKSIZE_3        (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0080 */\n\n#define SDIO_DCTRL_RWSTART_Pos         (8U)\n#define SDIO_DCTRL_RWSTART_Msk         (0x1UL << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */\n#define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start         */\n#define SDIO_DCTRL_RWSTOP_Pos          (9U)\n#define SDIO_DCTRL_RWSTOP_Msk          (0x1UL << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */\n#define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop          */\n#define SDIO_DCTRL_RWMOD_Pos           (10U)\n#define SDIO_DCTRL_RWMOD_Msk           (0x1UL << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */\n#define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode          */\n#define SDIO_DCTRL_SDIOEN_Pos          (11U)\n#define SDIO_DCTRL_SDIOEN_Msk          (0x1UL << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */\n#define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */\n\n/******************  Bit definition for SDIO_DCOUNT register  *****************/\n#define SDIO_DCOUNT_DATACOUNT_Pos      (0U)\n#define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */\n\n/******************  Bit definition for SDIO_STA register  ********************/\n#define SDIO_STA_CCRCFAIL_Pos          (0U)\n#define SDIO_STA_CCRCFAIL_Msk          (0x1UL << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */\n#define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */\n#define SDIO_STA_DCRCFAIL_Pos          (1U)\n#define SDIO_STA_DCRCFAIL_Msk          (0x1UL << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */\n#define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */\n#define SDIO_STA_CTIMEOUT_Pos          (2U)\n#define SDIO_STA_CTIMEOUT_Msk          (0x1UL << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */\n#define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */\n#define SDIO_STA_DTIMEOUT_Pos          (3U)\n#define SDIO_STA_DTIMEOUT_Msk          (0x1UL << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */\n#define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */\n#define SDIO_STA_TXUNDERR_Pos          (4U)\n#define SDIO_STA_TXUNDERR_Msk          (0x1UL << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */\n#define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */\n#define SDIO_STA_RXOVERR_Pos           (5U)\n#define SDIO_STA_RXOVERR_Msk           (0x1UL << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */\n#define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */\n#define SDIO_STA_CMDREND_Pos           (6U)\n#define SDIO_STA_CMDREND_Msk           (0x1UL << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */\n#define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */\n#define SDIO_STA_CMDSENT_Pos           (7U)\n#define SDIO_STA_CMDSENT_Msk           (0x1UL << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */\n#define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */\n#define SDIO_STA_DATAEND_Pos           (8U)\n#define SDIO_STA_DATAEND_Msk           (0x1UL << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */\n#define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */\n#define SDIO_STA_DBCKEND_Pos           (10U)\n#define SDIO_STA_DBCKEND_Msk           (0x1UL << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */\n#define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */\n#define SDIO_STA_CMDACT_Pos            (11U)\n#define SDIO_STA_CMDACT_Msk            (0x1UL << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */\n#define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */\n#define SDIO_STA_TXACT_Pos             (12U)\n#define SDIO_STA_TXACT_Msk             (0x1UL << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */\n#define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */\n#define SDIO_STA_RXACT_Pos             (13U)\n#define SDIO_STA_RXACT_Msk             (0x1UL << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */\n#define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */\n#define SDIO_STA_TXFIFOHE_Pos          (14U)\n#define SDIO_STA_TXFIFOHE_Msk          (0x1UL << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */\n#define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\n#define SDIO_STA_RXFIFOHF_Pos          (15U)\n#define SDIO_STA_RXFIFOHF_Msk          (0x1UL << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */\n#define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\n#define SDIO_STA_TXFIFOF_Pos           (16U)\n#define SDIO_STA_TXFIFOF_Msk           (0x1UL << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */\n#define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */\n#define SDIO_STA_RXFIFOF_Pos           (17U)\n#define SDIO_STA_RXFIFOF_Msk           (0x1UL << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */\n#define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */\n#define SDIO_STA_TXFIFOE_Pos           (18U)\n#define SDIO_STA_TXFIFOE_Msk           (0x1UL << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */\n#define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */\n#define SDIO_STA_RXFIFOE_Pos           (19U)\n#define SDIO_STA_RXFIFOE_Msk           (0x1UL << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */\n#define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */\n#define SDIO_STA_TXDAVL_Pos            (20U)\n#define SDIO_STA_TXDAVL_Msk            (0x1UL << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */\n#define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */\n#define SDIO_STA_RXDAVL_Pos            (21U)\n#define SDIO_STA_RXDAVL_Msk            (0x1UL << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */\n#define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */\n#define SDIO_STA_SDIOIT_Pos            (22U)\n#define SDIO_STA_SDIOIT_Msk            (0x1UL << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */\n#define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */\n\n/*******************  Bit definition for SDIO_ICR register  *******************/\n#define SDIO_ICR_CCRCFAILC_Pos         (0U)\n#define SDIO_ICR_CCRCFAILC_Msk         (0x1UL << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */\n#define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */\n#define SDIO_ICR_DCRCFAILC_Pos         (1U)\n#define SDIO_ICR_DCRCFAILC_Msk         (0x1UL << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */\n#define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */\n#define SDIO_ICR_CTIMEOUTC_Pos         (2U)\n#define SDIO_ICR_CTIMEOUTC_Msk         (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */\n#define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */\n#define SDIO_ICR_DTIMEOUTC_Pos         (3U)\n#define SDIO_ICR_DTIMEOUTC_Msk         (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */\n#define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */\n#define SDIO_ICR_TXUNDERRC_Pos         (4U)\n#define SDIO_ICR_TXUNDERRC_Msk         (0x1UL << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */\n#define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */\n#define SDIO_ICR_RXOVERRC_Pos          (5U)\n#define SDIO_ICR_RXOVERRC_Msk          (0x1UL << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */\n#define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */\n#define SDIO_ICR_CMDRENDC_Pos          (6U)\n#define SDIO_ICR_CMDRENDC_Msk          (0x1UL << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */\n#define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */\n#define SDIO_ICR_CMDSENTC_Pos          (7U)\n#define SDIO_ICR_CMDSENTC_Msk          (0x1UL << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */\n#define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */\n#define SDIO_ICR_DATAENDC_Pos          (8U)\n#define SDIO_ICR_DATAENDC_Msk          (0x1UL << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */\n#define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */\n#define SDIO_ICR_DBCKENDC_Pos          (10U)\n#define SDIO_ICR_DBCKENDC_Msk          (0x1UL << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */\n#define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */\n#define SDIO_ICR_SDIOITC_Pos           (22U)\n#define SDIO_ICR_SDIOITC_Msk           (0x1UL << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */\n#define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */\n\n/******************  Bit definition for SDIO_MASK register  *******************/\n#define SDIO_MASK_CCRCFAILIE_Pos       (0U)\n#define SDIO_MASK_CCRCFAILIE_Msk       (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */\n#define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */\n#define SDIO_MASK_DCRCFAILIE_Pos       (1U)\n#define SDIO_MASK_DCRCFAILIE_Msk       (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */\n#define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */\n#define SDIO_MASK_CTIMEOUTIE_Pos       (2U)\n#define SDIO_MASK_CTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */\n#define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */\n#define SDIO_MASK_DTIMEOUTIE_Pos       (3U)\n#define SDIO_MASK_DTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */\n#define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */\n#define SDIO_MASK_TXUNDERRIE_Pos       (4U)\n#define SDIO_MASK_TXUNDERRIE_Msk       (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */\n#define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */\n#define SDIO_MASK_RXOVERRIE_Pos        (5U)\n#define SDIO_MASK_RXOVERRIE_Msk        (0x1UL << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */\n#define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */\n#define SDIO_MASK_CMDRENDIE_Pos        (6U)\n#define SDIO_MASK_CMDRENDIE_Msk        (0x1UL << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */\n#define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */\n#define SDIO_MASK_CMDSENTIE_Pos        (7U)\n#define SDIO_MASK_CMDSENTIE_Msk        (0x1UL << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */\n#define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */\n#define SDIO_MASK_DATAENDIE_Pos        (8U)\n#define SDIO_MASK_DATAENDIE_Msk        (0x1UL << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */\n#define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */\n#define SDIO_MASK_DBCKENDIE_Pos        (10U)\n#define SDIO_MASK_DBCKENDIE_Msk        (0x1UL << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */\n#define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */\n#define SDIO_MASK_CMDACTIE_Pos         (11U)\n#define SDIO_MASK_CMDACTIE_Msk         (0x1UL << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */\n#define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */\n#define SDIO_MASK_TXACTIE_Pos          (12U)\n#define SDIO_MASK_TXACTIE_Msk          (0x1UL << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */\n#define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */\n#define SDIO_MASK_RXACTIE_Pos          (13U)\n#define SDIO_MASK_RXACTIE_Msk          (0x1UL << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */\n#define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */\n#define SDIO_MASK_TXFIFOHEIE_Pos       (14U)\n#define SDIO_MASK_TXFIFOHEIE_Msk       (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */\n#define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */\n#define SDIO_MASK_RXFIFOHFIE_Pos       (15U)\n#define SDIO_MASK_RXFIFOHFIE_Msk       (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */\n#define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */\n#define SDIO_MASK_TXFIFOFIE_Pos        (16U)\n#define SDIO_MASK_TXFIFOFIE_Msk        (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */\n#define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */\n#define SDIO_MASK_RXFIFOFIE_Pos        (17U)\n#define SDIO_MASK_RXFIFOFIE_Msk        (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */\n#define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */\n#define SDIO_MASK_TXFIFOEIE_Pos        (18U)\n#define SDIO_MASK_TXFIFOEIE_Msk        (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */\n#define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_RXFIFOEIE_Pos        (19U)\n#define SDIO_MASK_RXFIFOEIE_Msk        (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */\n#define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_TXDAVLIE_Pos         (20U)\n#define SDIO_MASK_TXDAVLIE_Msk         (0x1UL << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */\n#define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */\n#define SDIO_MASK_RXDAVLIE_Pos         (21U)\n#define SDIO_MASK_RXDAVLIE_Msk         (0x1UL << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */\n#define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */\n#define SDIO_MASK_SDIOITIE_Pos         (22U)\n#define SDIO_MASK_SDIOITIE_Msk         (0x1UL << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */\n#define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */\n\n/*****************  Bit definition for SDIO_FIFOCNT register  *****************/\n#define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)\n#define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */\n#define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */\n\n/******************  Bit definition for SDIO_FIFO register  *******************/\n#define SDIO_FIFO_FIFODATA_Pos         (0U)\n#define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Serial Peripheral Interface                         */\n/*                                                                            */\n/******************************************************************************/\n#define SPI_I2S_FULLDUPLEX_SUPPORT                                             /*!< I2S Full-Duplex support */\n#define I2S_APB1_APB2_FEATURE                                                  /*!< I2S IP's are splited between RCC APB1 and APB2 interfaces */\n\n/*******************  Bit definition for SPI_CR1 register  ********************/\n#define SPI_CR1_CPHA_Pos            (0U)\n#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */\n#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */\n#define SPI_CR1_CPOL_Pos            (1U)\n#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */\n#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */\n#define SPI_CR1_MSTR_Pos            (2U)\n#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */\n#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */\n\n#define SPI_CR1_BR_Pos              (3U)\n#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */\n#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */\n#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */\n#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */\n#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */\n\n#define SPI_CR1_SPE_Pos             (6U)\n#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */\n#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */\n#define SPI_CR1_LSBFIRST_Pos        (7U)\n#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */\n#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */\n#define SPI_CR1_SSI_Pos             (8U)\n#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */\n#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */\n#define SPI_CR1_SSM_Pos             (9U)\n#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */\n#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */\n#define SPI_CR1_RXONLY_Pos          (10U)\n#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */\n#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */\n#define SPI_CR1_DFF_Pos             (11U)\n#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */\n#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */\n#define SPI_CR1_CRCNEXT_Pos         (12U)\n#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */\n#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */\n#define SPI_CR1_CRCEN_Pos           (13U)\n#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */\n#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */\n#define SPI_CR1_BIDIOE_Pos          (14U)\n#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */\n#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */\n#define SPI_CR1_BIDIMODE_Pos        (15U)\n#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */\n#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */\n\n/*******************  Bit definition for SPI_CR2 register  ********************/\n#define SPI_CR2_RXDMAEN_Pos         (0U)\n#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */\n#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */\n#define SPI_CR2_TXDMAEN_Pos         (1U)\n#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */\n#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */\n#define SPI_CR2_SSOE_Pos            (2U)\n#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */\n#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */\n#define SPI_CR2_FRF_Pos             (4U)\n#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */\n#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */\n#define SPI_CR2_ERRIE_Pos           (5U)\n#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */\n#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */\n#define SPI_CR2_RXNEIE_Pos          (6U)\n#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */\n#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */\n#define SPI_CR2_TXEIE_Pos           (7U)\n#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */\n#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */\n\n/********************  Bit definition for SPI_SR register  ********************/\n#define SPI_SR_RXNE_Pos             (0U)\n#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */\n#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */\n#define SPI_SR_TXE_Pos              (1U)\n#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */\n#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */\n#define SPI_SR_CHSIDE_Pos           (2U)\n#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */\n#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */\n#define SPI_SR_UDR_Pos              (3U)\n#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */\n#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */\n#define SPI_SR_CRCERR_Pos           (4U)\n#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */\n#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */\n#define SPI_SR_MODF_Pos             (5U)\n#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */\n#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */\n#define SPI_SR_OVR_Pos              (6U)\n#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */\n#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */\n#define SPI_SR_BSY_Pos              (7U)\n#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */\n#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */\n#define SPI_SR_FRE_Pos              (8U)\n#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */\n#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */\n\n/********************  Bit definition for SPI_DR register  ********************/\n#define SPI_DR_DR_Pos               (0U)\n#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */\n#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */\n\n/*******************  Bit definition for SPI_CRCPR register  ******************/\n#define SPI_CRCPR_CRCPOLY_Pos       (0U)\n#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */\n#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */\n\n/******************  Bit definition for SPI_RXCRCR register  ******************/\n#define SPI_RXCRCR_RXCRC_Pos        (0U)\n#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */\n\n/******************  Bit definition for SPI_TXCRCR register  ******************/\n#define SPI_TXCRCR_TXCRC_Pos        (0U)\n#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */\n\n/******************  Bit definition for SPI_I2SCFGR register  *****************/\n#define SPI_I2SCFGR_CHLEN_Pos       (0U)\n#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */\n#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */\n\n#define SPI_I2SCFGR_DATLEN_Pos      (1U)\n#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */\n#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */\n#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */\n#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */\n\n#define SPI_I2SCFGR_CKPOL_Pos       (3U)\n#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */\n#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */\n\n#define SPI_I2SCFGR_I2SSTD_Pos      (4U)\n#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */\n#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */\n#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */\n#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */\n\n#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)\n#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */\n#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */\n\n#define SPI_I2SCFGR_I2SCFG_Pos      (8U)\n#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */\n#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */\n#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */\n#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */\n\n#define SPI_I2SCFGR_I2SE_Pos        (10U)\n#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */\n#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */\n#define SPI_I2SCFGR_I2SMOD_Pos      (11U)\n#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */\n#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */\n#define SPI_I2SCFGR_ASTRTEN_Pos     (12U)\n#define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)          /*!< 0x00001000 */\n#define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */\n\n/******************  Bit definition for SPI_I2SPR register  *******************/\n#define SPI_I2SPR_I2SDIV_Pos        (0U)\n#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */\n#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */\n#define SPI_I2SPR_ODD_Pos           (8U)\n#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */\n#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */\n#define SPI_I2SPR_MCKOE_Pos         (9U)\n#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */\n#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                 SYSCFG                                     */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SYSCFG_MEMRMP register  ***************/\n#define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)\n#define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */\n#define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */\n#define SYSCFG_MEMRMP_MEM_MODE_0             (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */\n#define SYSCFG_MEMRMP_MEM_MODE_1             (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */\n/******************  Bit definition for SYSCFG_PMC register  ******************/\n#define SYSCFG_PMC_ADC1DC2_Pos               (16U)\n#define SYSCFG_PMC_ADC1DC2_Msk               (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)  /*!< 0x00010000 */\n#define SYSCFG_PMC_ADC1DC2                   SYSCFG_PMC_ADC1DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */\n\n/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\n#define SYSCFG_EXTICR1_EXTI0_Pos             (0U)\n#define SYSCFG_EXTICR1_EXTI0_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */\n#define SYSCFG_EXTICR1_EXTI1_Pos             (4U)\n#define SYSCFG_EXTICR1_EXTI1_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */\n#define SYSCFG_EXTICR1_EXTI2_Pos             (8U)\n#define SYSCFG_EXTICR1_EXTI2_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */\n#define SYSCFG_EXTICR1_EXTI3_Pos             (12U)\n#define SYSCFG_EXTICR1_EXTI3_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */\n/**\n  * @brief   EXTI0 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PD              0x0003U                           /*!<PD[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PE              0x0004U                           /*!<PE[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PF              0x0005U                           /*!<PF[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PG              0x0006U                           /*!<PG[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */\n\n/**\n  * @brief   EXTI1 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PD              0x0030U                           /*!<PD[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PE              0x0040U                           /*!<PE[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PF              0x0050U                           /*!<PF[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PG              0x0060U                           /*!<PG[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */\n\n/**\n  * @brief   EXTI2 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PD              0x0300U                           /*!<PD[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PE              0x0400U                           /*!<PE[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PF              0x0500U                           /*!<PF[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PG              0x0600U                           /*!<PG[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */\n\n/**\n  * @brief   EXTI3 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PD              0x3000U                           /*!<PD[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PE              0x4000U                           /*!<PE[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PF              0x5000U                           /*!<PF[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PG              0x6000U                           /*!<PG[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\n#define SYSCFG_EXTICR2_EXTI4_Pos             (0U)\n#define SYSCFG_EXTICR2_EXTI4_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */\n#define SYSCFG_EXTICR2_EXTI5_Pos             (4U)\n#define SYSCFG_EXTICR2_EXTI5_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */\n#define SYSCFG_EXTICR2_EXTI6_Pos             (8U)\n#define SYSCFG_EXTICR2_EXTI6_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */\n#define SYSCFG_EXTICR2_EXTI7_Pos             (12U)\n#define SYSCFG_EXTICR2_EXTI7_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */\n\n/**\n  * @brief   EXTI4 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PD              0x0003U                           /*!<PD[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PE              0x0004U                           /*!<PE[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PF              0x0005U                           /*!<PF[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PG              0x0006U                           /*!<PG[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */\n\n/**\n  * @brief   EXTI5 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PD              0x0030U                           /*!<PD[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PE              0x0040U                           /*!<PE[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PF              0x0050U                           /*!<PF[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PG              0x0060U                           /*!<PG[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */\n\n/**\n  * @brief   EXTI6 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PD              0x0300U                           /*!<PD[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PE              0x0400U                           /*!<PE[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PF              0x0500U                           /*!<PF[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PG              0x0600U                           /*!<PG[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */\n\n/**\n  * @brief   EXTI7 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PD              0x3000U                           /*!<PD[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PE              0x4000U                           /*!<PE[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PF              0x5000U                           /*!<PF[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PG              0x6000U                           /*!<PG[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\n#define SYSCFG_EXTICR3_EXTI8_Pos             (0U)\n#define SYSCFG_EXTICR3_EXTI8_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */\n#define SYSCFG_EXTICR3_EXTI9_Pos             (4U)\n#define SYSCFG_EXTICR3_EXTI9_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */\n#define SYSCFG_EXTICR3_EXTI10_Pos            (8U)\n#define SYSCFG_EXTICR3_EXTI10_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */\n#define SYSCFG_EXTICR3_EXTI11_Pos            (12U)\n#define SYSCFG_EXTICR3_EXTI11_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */\n\n/**\n  * @brief   EXTI8 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PD              0x0003U                           /*!<PD[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PE              0x0004U                           /*!<PE[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PF              0x0005U                           /*!<PF[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PG              0x0006U                           /*!<PG[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */\n\n/**\n  * @brief   EXTI9 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PD              0x0030U                           /*!<PD[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PE              0x0040U                           /*!<PE[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PF              0x0050U                           /*!<PF[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PG              0x0060U                           /*!<PG[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */\n\n/**\n  * @brief   EXTI10 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PD             0x0300U                           /*!<PD[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PE             0x0400U                           /*!<PE[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PF             0x0500U                           /*!<PF[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PG             0x0600U                           /*!<PG[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */\n\n/**\n  * @brief   EXTI11 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PD             0x3000U                           /*!<PD[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PE             0x4000U                           /*!<PE[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PF             0x5000U                           /*!<PF[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PG             0x6000U                           /*!<PG[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\n#define SYSCFG_EXTICR4_EXTI12_Pos            (0U)\n#define SYSCFG_EXTICR4_EXTI12_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */\n#define SYSCFG_EXTICR4_EXTI13_Pos            (4U)\n#define SYSCFG_EXTICR4_EXTI13_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */\n#define SYSCFG_EXTICR4_EXTI14_Pos            (8U)\n#define SYSCFG_EXTICR4_EXTI14_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */\n#define SYSCFG_EXTICR4_EXTI15_Pos            (12U)\n#define SYSCFG_EXTICR4_EXTI15_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */\n\n/**\n  * @brief   EXTI12 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PD             0x0003U                           /*!<PD[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PE             0x0004U                           /*!<PE[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PF             0x0005U                           /*!<PF[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PG             0x0006U                           /*!<PG[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */\n\n/**\n  * @brief   EXTI13 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PD             0x0030U                           /*!<PD[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PE             0x0040U                           /*!<PE[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PF             0x0050U                           /*!<PF[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PG             0x0060U                           /*!<PG[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */\n\n/**\n  * @brief   EXTI14 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PD             0x0300U                           /*!<PD[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PE             0x0400U                           /*!<PE[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PF             0x0500U                           /*!<PF[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PG             0x0600U                           /*!<PG[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */\n\n/**\n  * @brief   EXTI15 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PD             0x3000U                           /*!<PD[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PE             0x4000U                           /*!<PE[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PF             0x5000U                           /*!<PF[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PG             0x6000U                           /*!<PG[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */\n\n/******************  Bit definition for SYSCFG_CMPCR register  ****************/\n#define SYSCFG_CMPCR_CMP_PD_Pos              (0U)\n#define SYSCFG_CMPCR_CMP_PD_Msk              (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */\n#define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */\n#define SYSCFG_CMPCR_READY_Pos               (8U)\n#define SYSCFG_CMPCR_READY_Msk               (0x1UL << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */\n#define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */\n/******************  Bit definition for SYSCFG_CFGR register  ****************/\n#define SYSCFG_CFGR_FMPI2C1_SCL_Pos          (0U)\n#define SYSCFG_CFGR_FMPI2C1_SCL_Msk          (0x1UL << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */\n#define SYSCFG_CFGR_FMPI2C1_SCL              SYSCFG_CFGR_FMPI2C1_SCL_Msk       /*!<FM+ drive capability for FMPI2C1_SCL pin */\n#define SYSCFG_CFGR_FMPI2C1_SDA_Pos          (1U)\n#define SYSCFG_CFGR_FMPI2C1_SDA_Msk          (0x1UL << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */\n#define SYSCFG_CFGR_FMPI2C1_SDA              SYSCFG_CFGR_FMPI2C1_SDA_Msk       /*!<FM+ drive capability for FMPI2C1_SDA pin */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    TIM                                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for TIM_CR1 register  ********************/\n#define TIM_CR1_CEN_Pos           (0U)\n#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */\n#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */\n#define TIM_CR1_UDIS_Pos          (1U)\n#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */\n#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */\n#define TIM_CR1_URS_Pos           (2U)\n#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */\n#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */\n#define TIM_CR1_OPM_Pos           (3U)\n#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */\n#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */\n#define TIM_CR1_DIR_Pos           (4U)\n#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */\n#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */\n\n#define TIM_CR1_CMS_Pos           (5U)\n#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */\n#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */\n#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR1_ARPE_Pos          (7U)\n#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */\n#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */\n\n#define TIM_CR1_CKD_Pos           (8U)\n#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */\n#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */\n#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */\n#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */\n\n/*******************  Bit definition for TIM_CR2 register  ********************/\n#define TIM_CR2_CCPC_Pos          (0U)\n#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */\n#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */\n#define TIM_CR2_CCUS_Pos          (2U)\n#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */\n#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */\n#define TIM_CR2_CCDS_Pos          (3U)\n#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */\n#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */\n\n#define TIM_CR2_MMS_Pos           (4U)\n#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */\n#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */\n#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */\n#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR2_TI1S_Pos          (7U)\n#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */\n#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */\n#define TIM_CR2_OIS1_Pos          (8U)\n#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */\n#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */\n#define TIM_CR2_OIS1N_Pos         (9U)\n#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */\n#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */\n#define TIM_CR2_OIS2_Pos          (10U)\n#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */\n#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */\n#define TIM_CR2_OIS2N_Pos         (11U)\n#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */\n#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */\n#define TIM_CR2_OIS3_Pos          (12U)\n#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */\n#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */\n#define TIM_CR2_OIS3N_Pos         (13U)\n#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */\n#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */\n#define TIM_CR2_OIS4_Pos          (14U)\n#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */\n#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */\n\n/*******************  Bit definition for TIM_SMCR register  *******************/\n#define TIM_SMCR_SMS_Pos          (0U)\n#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */\n#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */\n#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */\n#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */\n#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */\n\n#define TIM_SMCR_TS_Pos           (4U)\n#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */\n#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */\n#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */\n#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */\n#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */\n\n#define TIM_SMCR_MSM_Pos          (7U)\n#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */\n#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */\n\n#define TIM_SMCR_ETF_Pos          (8U)\n#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */\n#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */\n#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */\n#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */\n#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */\n#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */\n\n#define TIM_SMCR_ETPS_Pos         (12U)\n#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */\n#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */\n#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */\n#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */\n\n#define TIM_SMCR_ECE_Pos          (14U)\n#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */\n#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */\n#define TIM_SMCR_ETP_Pos          (15U)\n#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */\n#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */\n\n/*******************  Bit definition for TIM_DIER register  *******************/\n#define TIM_DIER_UIE_Pos          (0U)\n#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */\n#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */\n#define TIM_DIER_CC1IE_Pos        (1U)\n#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */\n#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */\n#define TIM_DIER_CC2IE_Pos        (2U)\n#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */\n#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */\n#define TIM_DIER_CC3IE_Pos        (3U)\n#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */\n#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */\n#define TIM_DIER_CC4IE_Pos        (4U)\n#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */\n#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */\n#define TIM_DIER_COMIE_Pos        (5U)\n#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */\n#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */\n#define TIM_DIER_TIE_Pos          (6U)\n#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */\n#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */\n#define TIM_DIER_BIE_Pos          (7U)\n#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */\n#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */\n#define TIM_DIER_UDE_Pos          (8U)\n#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */\n#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */\n#define TIM_DIER_CC1DE_Pos        (9U)\n#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */\n#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */\n#define TIM_DIER_CC2DE_Pos        (10U)\n#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */\n#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */\n#define TIM_DIER_CC3DE_Pos        (11U)\n#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */\n#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */\n#define TIM_DIER_CC4DE_Pos        (12U)\n#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */\n#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */\n#define TIM_DIER_COMDE_Pos        (13U)\n#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */\n#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */\n#define TIM_DIER_TDE_Pos          (14U)\n#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */\n#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */\n\n/********************  Bit definition for TIM_SR register  ********************/\n#define TIM_SR_UIF_Pos            (0U)\n#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */\n#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */\n#define TIM_SR_CC1IF_Pos          (1U)\n#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */\n#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */\n#define TIM_SR_CC2IF_Pos          (2U)\n#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */\n#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */\n#define TIM_SR_CC3IF_Pos          (3U)\n#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */\n#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */\n#define TIM_SR_CC4IF_Pos          (4U)\n#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */\n#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */\n#define TIM_SR_COMIF_Pos          (5U)\n#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */\n#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */\n#define TIM_SR_TIF_Pos            (6U)\n#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */\n#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */\n#define TIM_SR_BIF_Pos            (7U)\n#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */\n#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */\n#define TIM_SR_CC1OF_Pos          (9U)\n#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */\n#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */\n#define TIM_SR_CC2OF_Pos          (10U)\n#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */\n#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */\n#define TIM_SR_CC3OF_Pos          (11U)\n#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */\n#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */\n#define TIM_SR_CC4OF_Pos          (12U)\n#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */\n#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */\n\n/*******************  Bit definition for TIM_EGR register  ********************/\n#define TIM_EGR_UG_Pos            (0U)\n#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */\n#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */\n#define TIM_EGR_CC1G_Pos          (1U)\n#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */\n#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */\n#define TIM_EGR_CC2G_Pos          (2U)\n#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */\n#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */\n#define TIM_EGR_CC3G_Pos          (3U)\n#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */\n#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */\n#define TIM_EGR_CC4G_Pos          (4U)\n#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */\n#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */\n#define TIM_EGR_COMG_Pos          (5U)\n#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */\n#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */\n#define TIM_EGR_TG_Pos            (6U)\n#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */\n#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */\n#define TIM_EGR_BG_Pos            (7U)\n#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */\n#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */\n\n/******************  Bit definition for TIM_CCMR1 register  *******************/\n#define TIM_CCMR1_CC1S_Pos        (0U)\n#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\n#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR1_OC1FE_Pos       (2U)\n#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */\n#define TIM_CCMR1_OC1PE_Pos       (3U)\n#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */\n\n#define TIM_CCMR1_OC1M_Pos        (4U)\n#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */\n#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR1_OC1CE_Pos       (7U)\n#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */\n\n#define TIM_CCMR1_CC2S_Pos        (8U)\n#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\n#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR1_OC2FE_Pos       (10U)\n#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */\n#define TIM_CCMR1_OC2PE_Pos       (11U)\n#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */\n\n#define TIM_CCMR1_OC2M_Pos        (12U)\n#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */\n#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR1_OC2CE_Pos       (15U)\n#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR1_IC1PSC_Pos      (2U)\n#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\n#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR1_IC1F_Pos        (4U)\n#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */\n#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR1_IC2PSC_Pos      (10U)\n#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */\n#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR1_IC2F_Pos        (12U)\n#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */\n#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */\n\n/******************  Bit definition for TIM_CCMR2 register  *******************/\n#define TIM_CCMR2_CC3S_Pos        (0U)\n#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */\n#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR2_OC3FE_Pos       (2U)\n#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */\n#define TIM_CCMR2_OC3PE_Pos       (3U)\n#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */\n\n#define TIM_CCMR2_OC3M_Pos        (4U)\n#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\n#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR2_OC3CE_Pos       (7U)\n#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */\n\n#define TIM_CCMR2_CC4S_Pos        (8U)\n#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\n#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR2_OC4FE_Pos       (10U)\n#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */\n#define TIM_CCMR2_OC4PE_Pos       (11U)\n#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */\n\n#define TIM_CCMR2_OC4M_Pos        (12U)\n#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\n#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR2_OC4CE_Pos       (15U)\n#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR2_IC3PSC_Pos      (2U)\n#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\n#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR2_IC3F_Pos        (4U)\n#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\n#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR2_IC4PSC_Pos      (10U)\n#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\n#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR2_IC4F_Pos        (12U)\n#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\n#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */\n\n/*******************  Bit definition for TIM_CCER register  *******************/\n#define TIM_CCER_CC1E_Pos         (0U)\n#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */\n#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */\n#define TIM_CCER_CC1P_Pos         (1U)\n#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */\n#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */\n#define TIM_CCER_CC1NE_Pos        (2U)\n#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */\n#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */\n#define TIM_CCER_CC1NP_Pos        (3U)\n#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */\n#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */\n#define TIM_CCER_CC2E_Pos         (4U)\n#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */\n#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */\n#define TIM_CCER_CC2P_Pos         (5U)\n#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */\n#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */\n#define TIM_CCER_CC2NE_Pos        (6U)\n#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */\n#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */\n#define TIM_CCER_CC2NP_Pos        (7U)\n#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */\n#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */\n#define TIM_CCER_CC3E_Pos         (8U)\n#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */\n#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */\n#define TIM_CCER_CC3P_Pos         (9U)\n#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */\n#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */\n#define TIM_CCER_CC3NE_Pos        (10U)\n#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */\n#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */\n#define TIM_CCER_CC3NP_Pos        (11U)\n#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */\n#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */\n#define TIM_CCER_CC4E_Pos         (12U)\n#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */\n#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */\n#define TIM_CCER_CC4P_Pos         (13U)\n#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */\n#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */\n#define TIM_CCER_CC4NP_Pos        (15U)\n#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */\n#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */\n\n/*******************  Bit definition for TIM_CNT register  ********************/\n#define TIM_CNT_CNT_Pos           (0U)\n#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0xFFFFFFFF */\n#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                                  /*!<Counter Value            */\n\n/*******************  Bit definition for TIM_PSC register  ********************/\n#define TIM_PSC_PSC_Pos           (0U)\n#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */\n#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */\n\n/*******************  Bit definition for TIM_ARR register  ********************/\n#define TIM_ARR_ARR_Pos           (0U)\n#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */\n#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */\n\n/*******************  Bit definition for TIM_RCR register  ********************/\n#define TIM_RCR_REP_Pos           (0U)\n#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */\n#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */\n\n/*******************  Bit definition for TIM_CCR1 register  *******************/\n#define TIM_CCR1_CCR1_Pos         (0U)\n#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */\n\n/*******************  Bit definition for TIM_CCR2 register  *******************/\n#define TIM_CCR2_CCR2_Pos         (0U)\n#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */\n\n/*******************  Bit definition for TIM_CCR3 register  *******************/\n#define TIM_CCR3_CCR3_Pos         (0U)\n#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */\n\n/*******************  Bit definition for TIM_CCR4 register  *******************/\n#define TIM_CCR4_CCR4_Pos         (0U)\n#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */\n\n/*******************  Bit definition for TIM_BDTR register  *******************/\n#define TIM_BDTR_DTG_Pos          (0U)\n#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */\n#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\n#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */\n#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */\n#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */\n#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */\n#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */\n#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */\n#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */\n#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */\n\n#define TIM_BDTR_LOCK_Pos         (8U)\n#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */\n#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */\n#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */\n#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */\n\n#define TIM_BDTR_OSSI_Pos         (10U)\n#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */\n#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */\n#define TIM_BDTR_OSSR_Pos         (11U)\n#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */\n#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */\n#define TIM_BDTR_BKE_Pos          (12U)\n#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */\n#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */\n#define TIM_BDTR_BKP_Pos          (13U)\n#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */\n#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */\n#define TIM_BDTR_AOE_Pos          (14U)\n#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */\n#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */\n#define TIM_BDTR_MOE_Pos          (15U)\n#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */\n#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */\n\n/*******************  Bit definition for TIM_DCR register  ********************/\n#define TIM_DCR_DBA_Pos           (0U)\n#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */\n#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */\n#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */\n#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */\n#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */\n#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */\n#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */\n\n#define TIM_DCR_DBL_Pos           (8U)\n#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */\n#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */\n#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */\n#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */\n#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */\n#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */\n#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */\n\n/*******************  Bit definition for TIM_DMAR register  *******************/\n#define TIM_DMAR_DMAB_Pos         (0U)\n#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */\n#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */\n\n/*******************  Bit definition for TIM_OR register  *********************/\n#define TIM_OR_TI1_RMP_Pos        (0U)\n#define TIM_OR_TI1_RMP_Msk        (0x3UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000003 */\n#define TIM_OR_TI1_RMP            TIM_OR_TI1_RMP_Msk                           /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */\n#define TIM_OR_TI1_RMP_0          (0x1UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000001 */\n#define TIM_OR_TI1_RMP_1          (0x2UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000002 */\n\n#define TIM_OR_TI4_RMP_Pos        (6U)\n#define TIM_OR_TI4_RMP_Msk        (0x3UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */\n#define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */\n#define TIM_OR_TI4_RMP_0          (0x1UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */\n#define TIM_OR_TI4_RMP_1          (0x2UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */\n#define TIM_OR_ITR1_RMP_Pos       (10U)\n#define TIM_OR_ITR1_RMP_Msk       (0x3UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */\n#define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\n#define TIM_OR_ITR1_RMP_0         (0x1UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */\n#define TIM_OR_ITR1_RMP_1         (0x2UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*         Universal Synchronous Asynchronous Receiver Transmitter            */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for USART_SR register  *******************/\n#define USART_SR_PE_Pos               (0U)\n#define USART_SR_PE_Msk               (0x1UL << USART_SR_PE_Pos)                /*!< 0x00000001 */\n#define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */\n#define USART_SR_FE_Pos               (1U)\n#define USART_SR_FE_Msk               (0x1UL << USART_SR_FE_Pos)                /*!< 0x00000002 */\n#define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */\n#define USART_SR_NE_Pos               (2U)\n#define USART_SR_NE_Msk               (0x1UL << USART_SR_NE_Pos)                /*!< 0x00000004 */\n#define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */\n#define USART_SR_ORE_Pos              (3U)\n#define USART_SR_ORE_Msk              (0x1UL << USART_SR_ORE_Pos)               /*!< 0x00000008 */\n#define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */\n#define USART_SR_IDLE_Pos             (4U)\n#define USART_SR_IDLE_Msk             (0x1UL << USART_SR_IDLE_Pos)              /*!< 0x00000010 */\n#define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */\n#define USART_SR_RXNE_Pos             (5U)\n#define USART_SR_RXNE_Msk             (0x1UL << USART_SR_RXNE_Pos)              /*!< 0x00000020 */\n#define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */\n#define USART_SR_TC_Pos               (6U)\n#define USART_SR_TC_Msk               (0x1UL << USART_SR_TC_Pos)                /*!< 0x00000040 */\n#define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */\n#define USART_SR_TXE_Pos              (7U)\n#define USART_SR_TXE_Msk              (0x1UL << USART_SR_TXE_Pos)               /*!< 0x00000080 */\n#define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */\n#define USART_SR_LBD_Pos              (8U)\n#define USART_SR_LBD_Msk              (0x1UL << USART_SR_LBD_Pos)               /*!< 0x00000100 */\n#define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */\n#define USART_SR_CTS_Pos              (9U)\n#define USART_SR_CTS_Msk              (0x1UL << USART_SR_CTS_Pos)               /*!< 0x00000200 */\n#define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */\n\n/*******************  Bit definition for USART_DR register  *******************/\n#define USART_DR_DR_Pos               (0U)\n#define USART_DR_DR_Msk               (0x1FFUL << USART_DR_DR_Pos)              /*!< 0x000001FF */\n#define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */\n\n/******************  Bit definition for USART_BRR register  *******************/\n#define USART_BRR_DIV_Fraction_Pos    (0U)\n#define USART_BRR_DIV_Fraction_Msk    (0xFUL << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */\n#define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */\n#define USART_BRR_DIV_Mantissa_Pos    (4U)\n#define USART_BRR_DIV_Mantissa_Msk    (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */\n#define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */\n\n/******************  Bit definition for USART_CR1 register  *******************/\n#define USART_CR1_SBK_Pos             (0U)\n#define USART_CR1_SBK_Msk             (0x1UL << USART_CR1_SBK_Pos)              /*!< 0x00000001 */\n#define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */\n#define USART_CR1_RWU_Pos             (1U)\n#define USART_CR1_RWU_Msk             (0x1UL << USART_CR1_RWU_Pos)              /*!< 0x00000002 */\n#define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */\n#define USART_CR1_RE_Pos              (2U)\n#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */\n#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */\n#define USART_CR1_TE_Pos              (3U)\n#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */\n#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */\n#define USART_CR1_IDLEIE_Pos          (4U)\n#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */\n#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */\n#define USART_CR1_RXNEIE_Pos          (5U)\n#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */\n#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */\n#define USART_CR1_TCIE_Pos            (6U)\n#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */\n#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */\n#define USART_CR1_TXEIE_Pos           (7U)\n#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */\n#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<TXE Interrupt Enable                   */\n#define USART_CR1_PEIE_Pos            (8U)\n#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */\n#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */\n#define USART_CR1_PS_Pos              (9U)\n#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */\n#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */\n#define USART_CR1_PCE_Pos             (10U)\n#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */\n#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */\n#define USART_CR1_WAKE_Pos            (11U)\n#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */\n#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */\n#define USART_CR1_M_Pos               (12U)\n#define USART_CR1_M_Msk               (0x1UL << USART_CR1_M_Pos)                /*!< 0x00001000 */\n#define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */\n#define USART_CR1_UE_Pos              (13U)\n#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00002000 */\n#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */\n#define USART_CR1_OVER8_Pos           (15U)\n#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */\n#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */\n\n/******************  Bit definition for USART_CR2 register  *******************/\n#define USART_CR2_ADD_Pos             (0U)\n#define USART_CR2_ADD_Msk             (0xFUL << USART_CR2_ADD_Pos)              /*!< 0x0000000F */\n#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */\n#define USART_CR2_LBDL_Pos            (5U)\n#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */\n#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */\n#define USART_CR2_LBDIE_Pos           (6U)\n#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */\n#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */\n#define USART_CR2_LBCL_Pos            (8U)\n#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */\n#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */\n#define USART_CR2_CPHA_Pos            (9U)\n#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */\n#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */\n#define USART_CR2_CPOL_Pos            (10U)\n#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */\n#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */\n#define USART_CR2_CLKEN_Pos           (11U)\n#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */\n#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */\n\n#define USART_CR2_STOP_Pos            (12U)\n#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */\n#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */\n#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x1000 */\n#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x2000 */\n\n#define USART_CR2_LINEN_Pos           (14U)\n#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */\n#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */\n\n/******************  Bit definition for USART_CR3 register  *******************/\n#define USART_CR3_EIE_Pos             (0U)\n#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */\n#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */\n#define USART_CR3_IREN_Pos            (1U)\n#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */\n#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */\n#define USART_CR3_IRLP_Pos            (2U)\n#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */\n#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */\n#define USART_CR3_HDSEL_Pos           (3U)\n#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */\n#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */\n#define USART_CR3_NACK_Pos            (4U)\n#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */\n#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */\n#define USART_CR3_SCEN_Pos            (5U)\n#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */\n#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */\n#define USART_CR3_DMAR_Pos            (6U)\n#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */\n#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */\n#define USART_CR3_DMAT_Pos            (7U)\n#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */\n#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */\n#define USART_CR3_RTSE_Pos            (8U)\n#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */\n#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */\n#define USART_CR3_CTSE_Pos            (9U)\n#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */\n#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */\n#define USART_CR3_CTSIE_Pos           (10U)\n#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */\n#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */\n#define USART_CR3_ONEBIT_Pos          (11U)\n#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */\n#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */\n\n/******************  Bit definition for USART_GTPR register  ******************/\n#define USART_GTPR_PSC_Pos            (0U)\n#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */\n#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */\n#define USART_GTPR_PSC_0              (0x01UL << USART_GTPR_PSC_Pos)            /*!< 0x0001 */\n#define USART_GTPR_PSC_1              (0x02UL << USART_GTPR_PSC_Pos)            /*!< 0x0002 */\n#define USART_GTPR_PSC_2              (0x04UL << USART_GTPR_PSC_Pos)            /*!< 0x0004 */\n#define USART_GTPR_PSC_3              (0x08UL << USART_GTPR_PSC_Pos)            /*!< 0x0008 */\n#define USART_GTPR_PSC_4              (0x10UL << USART_GTPR_PSC_Pos)            /*!< 0x0010 */\n#define USART_GTPR_PSC_5              (0x20UL << USART_GTPR_PSC_Pos)            /*!< 0x0020 */\n#define USART_GTPR_PSC_6              (0x40UL << USART_GTPR_PSC_Pos)            /*!< 0x0040 */\n#define USART_GTPR_PSC_7              (0x80UL << USART_GTPR_PSC_Pos)            /*!< 0x0080 */\n\n#define USART_GTPR_GT_Pos             (8U)\n#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */\n#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            Window WATCHDOG                                 */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for WWDG_CR register  ********************/\n#define WWDG_CR_T_Pos           (0U)\n#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */\n#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\n#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x01 */\n#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x02 */\n#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x04 */\n#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x08 */\n#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x10 */\n#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x20 */\n#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x40 */\n/* Legacy defines */\n#define  WWDG_CR_T0                          WWDG_CR_T_0\n#define  WWDG_CR_T1                          WWDG_CR_T_1\n#define  WWDG_CR_T2                          WWDG_CR_T_2\n#define  WWDG_CR_T3                          WWDG_CR_T_3\n#define  WWDG_CR_T4                          WWDG_CR_T_4\n#define  WWDG_CR_T5                          WWDG_CR_T_5\n#define  WWDG_CR_T6                          WWDG_CR_T_6\n\n#define WWDG_CR_WDGA_Pos        (7U)\n#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */\n#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */\n\n/*******************  Bit definition for WWDG_CFR register  *******************/\n#define WWDG_CFR_W_Pos          (0U)\n#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */\n#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */\n#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x0001 */\n#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x0002 */\n#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x0004 */\n#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x0008 */\n#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x0010 */\n#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x0020 */\n#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x0040 */\n/* Legacy defines */\n#define  WWDG_CFR_W0                         WWDG_CFR_W_0\n#define  WWDG_CFR_W1                         WWDG_CFR_W_1\n#define  WWDG_CFR_W2                         WWDG_CFR_W_2\n#define  WWDG_CFR_W3                         WWDG_CFR_W_3\n#define  WWDG_CFR_W4                         WWDG_CFR_W_4\n#define  WWDG_CFR_W5                         WWDG_CFR_W_5\n#define  WWDG_CFR_W6                         WWDG_CFR_W_6\n\n#define WWDG_CFR_WDGTB_Pos      (7U)\n#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */\n#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */\n#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */\n#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */\n/* Legacy defines */\n#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0\n#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1\n\n#define WWDG_CFR_EWI_Pos        (9U)\n#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */\n#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */\n\n/*******************  Bit definition for WWDG_SR register  ********************/\n#define WWDG_SR_EWIF_Pos        (0U)\n#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */\n#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                DBG                                         */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for DBGMCU_IDCODE register  *************/\n#define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)\n#define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\n#define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk\n#define DBGMCU_IDCODE_REV_ID_Pos                     (16U)\n#define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\n#define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk\n\n/********************  Bit definition for DBGMCU_CR register  *****************/\n#define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)\n#define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */\n#define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk\n#define DBGMCU_CR_DBG_STOP_Pos                       (1U)\n#define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk\n#define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)\n#define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */\n#define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk\n#define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)\n#define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */\n#define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk\n\n#define DBGMCU_CR_TRACE_MODE_Pos                     (6U)\n#define DBGMCU_CR_TRACE_MODE_Msk                     (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */\n#define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk\n#define DBGMCU_CR_TRACE_MODE_0                       (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */\n#define DBGMCU_CR_TRACE_MODE_1                       (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */\n\n/********************  Bit definition for DBGMCU_APB1_FZ register  ************/\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos    (24U)\n#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */\n#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk\n\n/********************  Bit definition for DBGMCU_APB2_FZ register  ************/\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                                       USB_OTG                              */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/\n#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)\n#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */\n#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)\n#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\n#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */\n#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)\n#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */\n#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)\n#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */\n#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */\n#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)\n#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */\n#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)\n#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */\n#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */\n#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)\n#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */\n#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)\n#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */\n#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)\n#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)\n#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */\n#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)\n#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)\n#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */\n#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */\n#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)\n#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */\n#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */\n#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)\n#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */\n#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */\n#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)\n#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */\n#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)\n#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */\n#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)\n#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */\n#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)\n#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */\n#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */\n\n/********************  Bit definition forUSB_OTG_HCFG register  ********************/\n\n#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)\n#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\n#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */\n#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCFG_FSLSS_Pos                   (2U)\n#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */\n\n/********************  Bit definition for USB_OTG_DCFG register  ********************/\n\n#define USB_OTG_DCFG_DSPD_Pos                    (0U)\n#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\n#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */\n#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)\n#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */\n\n#define USB_OTG_DCFG_DAD_Pos                     (4U)\n#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\n#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */\n#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\n\n#define USB_OTG_DCFG_PFIVL_Pos                   (11U)\n#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\n#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */\n#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\n\n#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)\n#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */\n#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk        /*!< Transceiver delay */\n\n#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)\n#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */\n#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk        /*!< Erratic error interrupt mask */\n\n#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)\n#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\n#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */\n#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\n#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\n\n/********************  Bit definition for USB_OTG_PCGCR register  ********************/\n#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)\n#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */\n#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)\n#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */\n#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)\n#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */\n\n/********************  Bit definition for USB_OTG_GOTGINT register  ********************/\n#define USB_OTG_GOTGINT_SEDET_Pos                (2U)\n#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */\n#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)\n#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */\n#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)\n#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */\n#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)\n#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */\n#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)\n#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */\n#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)\n#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */\n#define USB_OTG_GOTGINT_IDCHNG_Pos               (20U)\n#define USB_OTG_GOTGINT_IDCHNG_Msk               (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */\n#define USB_OTG_GOTGINT_IDCHNG                   USB_OTG_GOTGINT_IDCHNG_Msk    /*!< Change in ID pin input value           */\n\n/********************  Bit definition for USB_OTG_DCTL register  ********************/\n#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)\n#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */\n#define USB_OTG_DCTL_SDIS_Pos                    (1U)\n#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */\n#define USB_OTG_DCTL_GINSTS_Pos                  (2U)\n#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */\n#define USB_OTG_DCTL_GONSTS_Pos                  (3U)\n#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\n#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */\n\n#define USB_OTG_DCTL_TCTL_Pos                    (4U)\n#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\n#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */\n#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCTL_SGINAK_Pos                  (7U)\n#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */\n#define USB_OTG_DCTL_CGINAK_Pos                  (8U)\n#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */\n#define USB_OTG_DCTL_SGONAK_Pos                  (9U)\n#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */\n#define USB_OTG_DCTL_CGONAK_Pos                  (10U)\n#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\n#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */\n#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)\n#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */\n\n/********************  Bit definition for USB_OTG_HFIR register  ********************/\n#define USB_OTG_HFIR_FRIVL_Pos                   (0U)\n#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */\n\n/********************  Bit definition for USB_OTG_HFNUM register  ********************/\n#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)\n#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */\n#define USB_OTG_HFNUM_FTREM_Pos                  (16U)\n#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */\n\n/********************  Bit definition for USB_OTG_DSTS register  ********************/\n#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)\n#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */\n\n#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)\n#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\n#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */\n#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\n#define USB_OTG_DSTS_EERR_Pos                    (3U)\n#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\n#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */\n#define USB_OTG_DSTS_FNSOF_Pos                   (8U)\n#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\n#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */\n\n/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/\n#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)\n#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\n#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */\n#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)\n#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\n#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */\n#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */\n#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */\n#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */\n#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */\n#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */\n#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)\n#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */\n#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)\n#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */\n#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)\n#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\n#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */\n\n/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/\n\n#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)\n#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\n#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */\n#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\n#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\n#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\n#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)\n#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\n#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\n#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)\n#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\n#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */\n#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)\n#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\n#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */\n#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)\n#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\n#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */\n#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\n#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\n#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\n#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\n#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)\n#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */\n#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)\n#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\n#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */\n#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)\n#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\n#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */\n#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)\n#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\n#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */\n#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)\n#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\n#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */\n#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)\n#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\n#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */\n#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)\n#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\n#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */\n#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)\n#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\n#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */\n#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)\n#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\n#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */\n#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)\n#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\n#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */\n#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)\n#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */\n\n/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/\n#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)\n#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\n#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */\n#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)\n#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\n#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */\n#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)\n#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\n#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */\n#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)\n#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\n#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */\n#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)\n#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\n#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */\n\n\n#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)\n#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\n#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */\n#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\n#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\n#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)\n#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\n#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */\n#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)\n#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\n#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */\n\n/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/\n#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)\n#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)\n#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)\n#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)\n#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)\n#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/\n#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)\n#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */\n#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)\n#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */\n#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)\n#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */\n#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\n\n/********************  Bit definition for USB_OTG_HAINT register  ********************/\n#define USB_OTG_HAINT_HAINT_Pos                  (0U)\n#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */\n\n/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/\n#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask              */\n#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */\n#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)\n#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */\n#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */\n#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)\n#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */\n#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)\n#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */\n#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)\n#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */\n#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */\n#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)\n#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */\n#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)\n#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */\n#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)\n#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */\n#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)\n#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */\n#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)\n#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */\n/********************  Bit definition for USB_OTG_GINTSTS register  ********************/\n#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)\n#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\n#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */\n#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)\n#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */\n#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)\n#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */\n#define USB_OTG_GINTSTS_SOF_Pos                  (3U)\n#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */\n#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)\n#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */\n#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)\n#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */\n#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)\n#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */\n#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)\n#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */\n#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)\n#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */\n#define USB_OTG_GINTSTS_USBRST_Pos               (12U)\n#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */\n#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)\n#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */\n#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)\n#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */\n#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)\n#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */\n#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)\n#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */\n#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)\n#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */\n#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)\n#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */\n#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)\n#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */\n#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)\n#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */\n#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */\n#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)\n#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */\n#define USB_OTG_GINTSTS_HCINT_Pos                (25U)\n#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */\n#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)\n#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */\n#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)\n#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */\n#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */\n#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)\n#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */\n#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)\n#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */\n#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)\n#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */\n#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)\n#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */\n\n/********************  Bit definition for USB_OTG_GINTMSK register  ********************/\n#define USB_OTG_GINTMSK_MMISM_Pos                (1U)\n#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */\n#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)\n#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */\n#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)\n#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */\n#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)\n#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */\n#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)\n#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */\n#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)\n#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */\n#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)\n#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */\n#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)\n#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */\n#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)\n#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */\n#define USB_OTG_GINTMSK_USBRST_Pos               (12U)\n#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */\n#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)\n#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */\n#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)\n#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */\n#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)\n#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */\n#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)\n#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\n#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */\n#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)\n#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */\n#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)\n#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */\n#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)\n#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */\n#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)\n#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */\n#define USB_OTG_GINTMSK_RSTDETM_Pos              (23U)\n#define USB_OTG_GINTMSK_RSTDETM_Msk              (0x1UL << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */\n#define USB_OTG_GINTMSK_RSTDETM                  USB_OTG_GINTMSK_RSTDETM_Msk   /*!< Reset detected interrupt mask */\n#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)\n#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */\n#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)\n#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */\n#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)\n#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */\n#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)\n#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */\n#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */\n#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)\n#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */\n#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)\n#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */\n#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)\n#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */\n#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)\n#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */\n\n/********************  Bit definition for USB_OTG_DAINT register  ********************/\n#define USB_OTG_DAINT_IEPINT_Pos                 (0U)\n#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */\n#define USB_OTG_DAINT_OEPINT_Pos                 (16U)\n#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */\n\n/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/\n#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)\n#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */\n\n/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/\n#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)\n#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\n#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */\n#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)\n#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\n#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)\n#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\n#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)\n#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/\n#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)\n#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */\n#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)\n#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/\n#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)\n#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/\n#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)\n#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */\n\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_NPTXFSA_Pos                      (0U)\n#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */\n#define USB_OTG_NPTXFD_Pos                       (16U)\n#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */\n#define USB_OTG_TX0FSA_Pos                       (0U)\n#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */\n#define USB_OTG_TX0FD_Pos                        (16U)\n#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */\n\n/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/\n#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)\n#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\n#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\n\n/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\n\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/\n#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)\n#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\n#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\n#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)\n#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\n#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */\n\n#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)\n#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\n#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */\n#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)\n#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\n#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */\n\n#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)\n#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */\n#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\n#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)\n#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\n#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */\n\n/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DEACHINT register  ********************/\n#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)\n#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */\n#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)\n#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */\n\n/********************  Bit definition for USB_OTG_GCCFG register  ********************/\n#define USB_OTG_GCCFG_DCDET_Pos                  (0U)\n#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */\n#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */\n#define USB_OTG_GCCFG_PDET_Pos                   (1U)\n#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */\n#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */\n#define USB_OTG_GCCFG_SDET_Pos                   (2U)\n#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */\n#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */\n#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)\n#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */\n#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */\n#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)\n#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\n#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */\n#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)\n#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */\n#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)\n#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/\n#define USB_OTG_GCCFG_PDEN_Pos                   (19U)\n#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/\n#define USB_OTG_GCCFG_SDEN_Pos                   (20U)\n#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */\n#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)\n#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< USB VBUS Detection Enable */\n\n/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\n\n/********************  Bit definition for USB_OTG_CID register  ********************/\n#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)\n#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */\n\n/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/\n#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)\n#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */\n#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */\n#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)\n#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */\n#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */\n#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)\n#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */\n#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */\n#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)\n#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */\n#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */\n#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)\n#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */\n#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)\n#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */\n#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */\n#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)\n#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */\n#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */\n#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)\n#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */\n#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */\n#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)\n#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */\n#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)\n#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */\n#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */\n#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)\n#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */\n#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)\n#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */\n#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */\n#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)\n#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */\n#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */\n#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)\n#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */\n#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */\n\n/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */\n#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPRT register  ********************/\n#define USB_OTG_HPRT_PCSTS_Pos                   (0U)\n#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */\n#define USB_OTG_HPRT_PCDET_Pos                   (1U)\n#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\n#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */\n#define USB_OTG_HPRT_PENA_Pos                    (2U)\n#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\n#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */\n#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)\n#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\n#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */\n#define USB_OTG_HPRT_POCA_Pos                    (4U)\n#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\n#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */\n#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)\n#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\n#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */\n#define USB_OTG_HPRT_PRES_Pos                    (6U)\n#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\n#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */\n#define USB_OTG_HPRT_PSUSP_Pos                   (7U)\n#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\n#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */\n#define USB_OTG_HPRT_PRST_Pos                    (8U)\n#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\n#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */\n\n#define USB_OTG_HPRT_PLSTS_Pos                   (10U)\n#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\n#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */\n#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\n#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_HPRT_PPWR_Pos                    (12U)\n#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */\n\n#define USB_OTG_HPRT_PTCTL_Pos                   (13U)\n#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\n#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */\n#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\n#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\n#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\n#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\n\n#define USB_OTG_HPRT_PSPD_Pos                    (17U)\n#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\n#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */\n#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\n\n/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */\n#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */\n#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */\n#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)\n#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */\n#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)\n#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */\n\n/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/\n#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)\n#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */\n#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)\n#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */\n\n/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/\n#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */\n#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */\n#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)\n#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\n#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */\n#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */\n\n#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */\n#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DIEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */\n\n#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)\n#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\n#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */\n#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\n#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\n#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\n#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\n#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */\n#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */\n#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */\n#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */\n#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */\n\n/********************  Bit definition for USB_OTG_HCCHAR register  ********************/\n#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)\n#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */\n\n#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)\n#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\n#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */\n#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\n#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)\n#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */\n#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)\n#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */\n\n#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)\n#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */\n#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\n\n#define USB_OTG_HCCHAR_MC_Pos                    (20U)\n#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\n#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */\n#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\n#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\n\n#define USB_OTG_HCCHAR_DAD_Pos                   (22U)\n#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\n#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */\n#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\n#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\n#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\n#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\n#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\n#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\n#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\n#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)\n#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */\n#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)\n#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */\n#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)\n#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */\n\n/********************  Bit definition for USB_OTG_HCSPLT register  ********************/\n\n#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)\n#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\n#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */\n#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\n\n#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)\n#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\n#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */\n#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\n\n#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)\n#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\n#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */\n#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)\n#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\n#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */\n#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)\n#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */\n\n/********************  Bit definition for USB_OTG_HCINT register  ********************/\n#define USB_OTG_HCINT_XFRC_Pos                   (0U)\n#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */\n#define USB_OTG_HCINT_CHH_Pos                    (1U)\n#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */\n#define USB_OTG_HCINT_AHBERR_Pos                 (2U)\n#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */\n#define USB_OTG_HCINT_STALL_Pos                  (3U)\n#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */\n#define USB_OTG_HCINT_NAK_Pos                    (4U)\n#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */\n#define USB_OTG_HCINT_ACK_Pos                    (5U)\n#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */\n#define USB_OTG_HCINT_NYET_Pos                   (6U)\n#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */\n#define USB_OTG_HCINT_TXERR_Pos                  (7U)\n#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */\n#define USB_OTG_HCINT_BBERR_Pos                  (8U)\n#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */\n#define USB_OTG_HCINT_FRMOR_Pos                  (9U)\n#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */\n#define USB_OTG_HCINT_DTERR_Pos                  (10U)\n#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */\n\n/********************  Bit definition for USB_OTG_DIEPINT register  ********************/\n#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)\n#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */\n#define USB_OTG_DIEPINT_TOC_Pos                  (3U)\n#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */\n#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)\n#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */\n#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)\n#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */\n#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */\n#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)\n#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */\n#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)\n#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\n#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\n#define USB_OTG_DIEPINT_BNA_Pos                  (9U)\n#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */\n#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)\n#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\n#define USB_OTG_DIEPINT_BERR_Pos                 (12U)\n#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\n#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */\n#define USB_OTG_DIEPINT_NAK_Pos                  (13U)\n#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */\n\n/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/\n#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)\n#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */\n#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)\n#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */\n#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)\n#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */\n#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)\n#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */\n#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)\n#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */\n#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)\n#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */\n#define USB_OTG_HCINTMSK_NYET_Pos                (6U)\n#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */\n#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)\n#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */\n#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)\n#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */\n#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)\n#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */\n#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)\n#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */\n\n/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/\n\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)\n#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */\n/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/\n#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)\n#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */\n#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)\n#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */\n#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)\n#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */\n#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)\n#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\n#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */\n#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/\n#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)\n#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_HCDMA register  ********************/\n#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)\n#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/\n#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)\n#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */\n\n/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/\n#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)\n#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */\n#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)\n#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/\n\n#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */\n#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */\n#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\n#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */\n#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */\n#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)\n#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\n#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */\n#define USB_OTG_DOEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */\n#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */\n#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */\n#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */\n\n/********************  Bit definition for USB_OTG_DOEPINT register  ********************/\n#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)\n#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */\n#define USB_OTG_DOEPINT_STUP_Pos                 (3U)\n#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */\n#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)\n#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */\n#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)\n#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */\n#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */\n#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)\n#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */\n#define USB_OTG_DOEPINT_NAK_Pos                  (13U)\n#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */\n#define USB_OTG_DOEPINT_NYET_Pos                 (14U)\n#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */\n#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)\n#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */\n/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/\n\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n\n#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)\n#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */\n#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for PCGCCTL register  ********************/\n#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)\n#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */\n#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)\n#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */\n#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)\n#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */\n\n/* Legacy define */\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_CHNUM_Pos                        (0U)\n#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\n#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\n#define USB_OTG_BCNT_Pos                         (4U)\n#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\n\n#define USB_OTG_DPID_Pos                         (15U)\n#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)    /*!< 0x00018000 */\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\n#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\n#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\n\n#define USB_OTG_PKTSTS_Pos                       (17U)\n#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\n#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\n#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\n#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\n#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\n\n#define USB_OTG_EPNUM_Pos                        (0U)\n#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\n#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\n\n#define USB_OTG_FRMNUM_Pos                       (21U)\n#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\n#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\n#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\n#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\n#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_macros\n  * @{\n  */\n\n/******************************* ADC Instances ********************************/\n#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\n\n#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)\n\n/******************************* CAN Instances ********************************/\n#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \\\n                                       ((INSTANCE) == CAN2))\n\n/****************************** DFSDM Instances *******************************/\n#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \\\n                                                ((INSTANCE) == DFSDM1_Filter1))\n\n#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel1) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel2) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel3))\n/******************************* CRC Instances ********************************/\n#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\n\n\n/******************************** DMA Instances *******************************/\n#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \\\n                                              ((INSTANCE) == DMA1_Stream1) || \\\n                                              ((INSTANCE) == DMA1_Stream2) || \\\n                                              ((INSTANCE) == DMA1_Stream3) || \\\n                                              ((INSTANCE) == DMA1_Stream4) || \\\n                                              ((INSTANCE) == DMA1_Stream5) || \\\n                                              ((INSTANCE) == DMA1_Stream6) || \\\n                                              ((INSTANCE) == DMA1_Stream7) || \\\n                                              ((INSTANCE) == DMA2_Stream0) || \\\n                                              ((INSTANCE) == DMA2_Stream1) || \\\n                                              ((INSTANCE) == DMA2_Stream2) || \\\n                                              ((INSTANCE) == DMA2_Stream3) || \\\n                                              ((INSTANCE) == DMA2_Stream4) || \\\n                                              ((INSTANCE) == DMA2_Stream5) || \\\n                                              ((INSTANCE) == DMA2_Stream6) || \\\n                                              ((INSTANCE) == DMA2_Stream7))\n\n/******************************* GPIO Instances *******************************/\n#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\\n                                        ((INSTANCE) == GPIOB) || \\\n                                        ((INSTANCE) == GPIOC) || \\\n                                        ((INSTANCE) == GPIOD) || \\\n                                        ((INSTANCE) == GPIOE) || \\\n                                        ((INSTANCE) == GPIOF) || \\\n                                        ((INSTANCE) == GPIOG) || \\\n                                        ((INSTANCE) == GPIOH))\n\n/******************************** I2C Instances *******************************/\n#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\n                                       ((INSTANCE) == I2C2) || \\\n                                       ((INSTANCE) == I2C3))\n\n/******************************* SMBUS Instances ******************************/\n#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE\n\n/******************************** I2S Instances *******************************/\n#define IS_I2S_APB1_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \\\n                                         ((INSTANCE) == SPI3))\n\n#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI1) || \\\n                                        ((INSTANCE) == SPI2) || \\\n                                        ((INSTANCE) == SPI3) || \\\n                                        ((INSTANCE) == SPI4) || \\\n                                        ((INSTANCE) == SPI5))\n\n/*************************** I2S Extended Instances ***************************/\n#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \\\n                                           ((INSTANCE) == I2S3ext))\n/* Legacy Defines */\n#define IS_I2S_ALL_INSTANCE_EXT    IS_I2S_EXT_ALL_INSTANCE\n\n/******************************* RNG Instances ********************************/\n#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)\n\n/****************************** RTC Instances *********************************/\n#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\n\n\n/******************************** SPI Instances *******************************/\n\n#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\\n                                       ((INSTANCE) == SPI2) || \\\n                                       ((INSTANCE) == SPI3) || \\\n                                       ((INSTANCE) == SPI4) || \\\n                                       ((INSTANCE) == SPI5))\n\n\n/****************** TIM Instances : All supported instances *******************/\n#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                    ((INSTANCE) == TIM2) || \\\n                                    ((INSTANCE) == TIM3) || \\\n                                    ((INSTANCE) == TIM4) || \\\n                                    ((INSTANCE) == TIM5) || \\\n                                    ((INSTANCE) == TIM6) || \\\n                                    ((INSTANCE) == TIM7) || \\\n                                    ((INSTANCE) == TIM8) || \\\n                                    ((INSTANCE) == TIM9) || \\\n                                    ((INSTANCE) == TIM10)|| \\\n                                    ((INSTANCE) == TIM11)|| \\\n                                    ((INSTANCE) == TIM12)|| \\\n                                    ((INSTANCE) == TIM13)|| \\\n                                    ((INSTANCE) == TIM14))\n\n/************* TIM Instances : at least 1 capture/compare channel *************/\n#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \\\n                                         ((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM3)  || \\\n                                         ((INSTANCE) == TIM4)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM8)  || \\\n                                         ((INSTANCE) == TIM9)  || \\\n                                         ((INSTANCE) == TIM10) || \\\n                                         ((INSTANCE) == TIM11) || \\\n                                         ((INSTANCE) == TIM12) || \\\n                                         ((INSTANCE) == TIM13) || \\\n                                         ((INSTANCE) == TIM14))\n\n/************ TIM Instances : at least 2 capture/compare channels *************/\n#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8) || \\\n                                       ((INSTANCE) == TIM9) || \\\n                                       ((INSTANCE) == TIM12))\n\n/************ TIM Instances : at least 3 capture/compare channels *************/\n#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/************ TIM Instances : at least 4 capture/compare channels *************/\n#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : Advanced-control timers *****************/\n#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                           ((INSTANCE) == TIM8))\n\n/******************* TIM Instances : Timer input XOR function *****************/\n#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : DMA requests generation (UDE) *************/\n#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM6) || \\\n                                       ((INSTANCE) == TIM7) || \\\n                                       ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (CCxDE) *****************/\n#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (COMDE) *****************/\n#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : DMA burst feature ***********************/\n#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                             ((INSTANCE) == TIM2) || \\\n                                             ((INSTANCE) == TIM3) || \\\n                                             ((INSTANCE) == TIM4) || \\\n                                             ((INSTANCE) == TIM5) || \\\n                                             ((INSTANCE) == TIM8))\n\n/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\n#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                          ((INSTANCE) == TIM2)  || \\\n                                          ((INSTANCE) == TIM3)  || \\\n                                          ((INSTANCE) == TIM4)  || \\\n                                          ((INSTANCE) == TIM5)  || \\\n                                          ((INSTANCE) == TIM6)  || \\\n                                          ((INSTANCE) == TIM8))\n\n/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\n#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8) || \\\n                                         ((INSTANCE) == TIM9) || \\\n                                         ((INSTANCE) == TIM12))\n/********************** TIM Instances : 32 bit Counter ************************/\n#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \\\n                                              ((INSTANCE) == TIM5))\n\n/***************** TIM Instances : external trigger input availabe ************/\n#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                        ((INSTANCE) == TIM2) || \\\n                                        ((INSTANCE) == TIM3) || \\\n                                        ((INSTANCE) == TIM4) || \\\n                                        ((INSTANCE) == TIM5) || \\\n                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : remapping capability **********************/\n#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM11))\n\n/******************* TIM Instances : output(s) available **********************/\n#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\\n    ((((INSTANCE) == TIM1) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM2) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM3) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM4) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM5) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM8) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM9) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM10) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM11) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM12) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM13) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM14) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1))))\n\n/************ TIM Instances : complementary output(s) available ***************/\n#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\\n   ((((INSTANCE) == TIM1) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3)))            \\\n    ||                                          \\\n    (((INSTANCE) == TIM8) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3))))\n\n/****************** TIM Instances : supporting counting mode selection ********/\n#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting clock division *****************/\n#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                                  ((INSTANCE) == TIM2) || \\\n                                                  ((INSTANCE) == TIM3) || \\\n                                                  ((INSTANCE) == TIM4) || \\\n                                                  ((INSTANCE) == TIM5) || \\\n                                                  ((INSTANCE) == TIM8) || \\\n                                                  ((INSTANCE) == TIM9) || \\\n                                                  ((INSTANCE) == TIM10)|| \\\n                                                  ((INSTANCE) == TIM11)|| \\\n                                                  ((INSTANCE) == TIM12)|| \\\n                                                  ((INSTANCE) == TIM13)|| \\\n                                                  ((INSTANCE) == TIM14))\n\n/****************** TIM Instances : supporting commutation event generation ***/\n#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \\\n                                                     ((INSTANCE) == TIM8))\n\n\n/****************** TIM Instances : supporting OCxREF clear *******************/\n#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM2) || \\\n                                                       ((INSTANCE) == TIM3) || \\\n                                                       ((INSTANCE) == TIM4) || \\\n                                                       ((INSTANCE) == TIM5) || \\\n                                                       ((INSTANCE) == TIM8))\n\n/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8))\n\n/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/\n#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/********** TIM Instances : supporting internal trigger inputs(ITRX) *********/\n#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/****************** TIM Instances : supporting repetition counter *************/\n#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting encoder interface **************/\n#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                      ((INSTANCE) == TIM2) || \\\n                                                      ((INSTANCE) == TIM3) || \\\n                                                      ((INSTANCE) == TIM4) || \\\n                                                      ((INSTANCE) == TIM5) || \\\n                                                      ((INSTANCE) == TIM8) || \\\n                                                      ((INSTANCE) == TIM9) || \\\n                                                      ((INSTANCE) == TIM12))\n/****************** TIM Instances : supporting Hall sensor interface **********/\n#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                          ((INSTANCE) == TIM2) || \\\n                                                          ((INSTANCE) == TIM3) || \\\n                                                          ((INSTANCE) == TIM4) || \\\n                                                          ((INSTANCE) == TIM5) || \\\n                                                          ((INSTANCE) == TIM8))\n/****************** TIM Instances : supporting the break function *************/\n#define IS_TIM_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM8))\n\n/******************** USART Instances : Synchronous mode **********************/\n#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                     ((INSTANCE) == USART2) || \\\n                                     ((INSTANCE) == USART3) || \\\n                                     ((INSTANCE) == USART6))\n\n/******************** UART Instances : Half-Duplex mode **********************/\n#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                               ((INSTANCE) == USART2) || \\\n                                               ((INSTANCE) == USART3) || \\\n                                               ((INSTANCE) == USART6))\n\n/* Legacy defines */\n#define IS_UART_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE\n\n/****************** UART Instances : Hardware Flow control ********************/\n#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                           ((INSTANCE) == USART2) || \\\n                                           ((INSTANCE) == USART3) || \\\n                                           ((INSTANCE) == USART6))\n/******************** UART Instances : LIN mode **********************/\n#define IS_UART_LIN_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE\n\n/********************* UART Instances : Smart card mode ***********************/\n#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                         ((INSTANCE) == USART2) || \\\n                                         ((INSTANCE) == USART3) || \\\n                                         ((INSTANCE) == USART6))\n\n/*********************** UART Instances : IRDA mode ***************************/\n#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2) || \\\n                                    ((INSTANCE) == USART3) || \\\n                                    ((INSTANCE) == USART6))\n\n/*********************** PCD Instances ****************************************/\n#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))\n\n/*********************** HCD Instances ****************************************/\n#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))\n\n/****************************** SDIO Instances ********************************/\n#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)\n\n/****************************** IWDG Instances ********************************/\n#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)\n\n/****************************** WWDG Instances ********************************/\n#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)\n\n\n/***************************** FMPI2C Instances *******************************/\n#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)\n#define IS_FMPSMBUS_ALL_INSTANCE         IS_FMPI2C_ALL_INSTANCE\n\n/****************************** QSPI Instances ********************************/\n#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)\n/****************************** USB Exported Constants ************************/\n#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                12U\n#define USB_OTG_FS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */\n#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */\n#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */\n\n/*\n * @brief Specific devices reset values definitions\n */\n#define RCC_PLLCFGR_RST_VALUE              0x24003010U\n#define RCC_PLLI2SCFGR_RST_VALUE           0x24003010U\n\n#define RCC_MAX_FREQUENCY           100000000U         /*!< Max frequency of family in Hz*/\n#define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */\n#define RCC_MAX_FREQUENCY_SCALE2     84000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */\n#define RCC_MAX_FREQUENCY_SCALE3     64000000U         /*!< Maximum frequency for system clock at power scale3, in Hz */\n#define RCC_PLLVCO_OUTPUT_MIN       100000000U       /*!< Frequency min for PLLVCO output, in Hz */\n#define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */\n\n#define RCC_PLLN_MIN_VALUE                 50U\n#define RCC_PLLN_MAX_VALUE                432U\n\n#define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */\n#define FLASH_SCALE1_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */\n#define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */\n\n#define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */\n#define FLASH_SCALE2_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */\n\n#define FLASH_SCALE3_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */\n#define FLASH_SCALE3_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */\n\n/******************************************************************************/\n/*  For a painless codes migration between the STM32F4xx device product       */\n/*  lines, the aliases defined below are put in place to overcome the         */\n/*  differences in the interrupt handlers and IRQn definitions.               */\n/*  No need to update developed interrupt code when moving across             */\n/*  product lines within the same STM32F4 Family                              */\n/******************************************************************************/\n/* Aliases for __IRQn */\n#define FMC_IRQn              FSMC_IRQn\n\n/* Aliases for __IRQHandler */\n#define FMC_IRQHandler        FSMC_IRQHandler\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32F412Zx_H */\n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f413xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f413xx.h\n  * @author  MCD Application Team\n  * @brief   CMSIS STM32F413xx Device Peripheral Access Layer Header File.\n  *\n  *          This file contains:\n  *           - Data structures and the address mapping for all peripherals\n  *           - peripherals registers declarations and bits definition\n  *           - Macros to access peripheral's registers hardware\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS_Device\n  * @{\n  */\n\n/** @addtogroup stm32f413xx\n  * @{\n  */\n\n#ifndef __STM32F413xx_H\n#define __STM32F413xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Configuration_section_for_CMSIS\n  * @{\n  */\n\n/**\n  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals\n  */\n#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */\n#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */\n#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */\n#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */\n#define __FPU_PRESENT             1U       /*!< FPU present                                   */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_interrupt_number_definition\n  * @{\n  */\n\n/**\n * @brief STM32F4XX Interrupt Number Definition, according to the selected device\n *        in @ref Library_configuration_section\n */\ntypedef enum\n{\n/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */\n  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */\n  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */\n  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */\n  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */\n  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */\n/******  STM32 specific Interrupt Numbers **********************************************************************/\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */\n  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */\n  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\n  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\n  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\n  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\n  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\n  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\n  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\n  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\n  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\n  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */\n  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */\n  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */\n  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */\n  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */\n  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */\n  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */\n  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */\n  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */\n  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */\n  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */\n  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\n  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */\n  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */\n  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\n  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\n  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */\n  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */\n  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */\n  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\n  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */\n  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */\n  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\n  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */\n  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */\n  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */\n  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */\n  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */\n  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */\n  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */\n  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */\n  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */\n  DFSDM1_FLT0_IRQn            = 61,     /*!< DFSDM1 Filter 0 global Interrupt                                  */\n  DFSDM1_FLT1_IRQn            = 62,     /*!< DFSDM1 Filter 1 global Interrupt                                  */\n  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */\n  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */\n  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */\n  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */\n  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */\n  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */\n  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */\n  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */\n  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */\n  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\n  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\n  CAN3_TX_IRQn                = 74,     /*!< CAN3 TX Interrupt                                                 */\n  CAN3_RX0_IRQn               = 75,     /*!< CAN3 RX0 Interrupt                                                */\n  CAN3_RX1_IRQn               = 76,     /*!< CAN3 RX1 Interrupt                                                */\n  CAN3_SCE_IRQn               = 77,     /*!< CAN3 SCE Interrupt                                                */\n  RNG_IRQn                    = 80,     /*!< RNG global Interrupt                                              */\n  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */\n  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */\n  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */\n  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */\n  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */\n  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */\n  UART9_IRQn                  = 88,     /*!< UART9 global Interrupt                                            */\n  UART10_IRQn                 = 89,     /*!< UART10 global Interrupt                                           */\n  QUADSPI_IRQn                = 92,     /*!< QuadSPI global Interrupt                                          */\n  FMPI2C1_EV_IRQn             = 95,     /*!< FMPI2C1 Event Interrupt                                           */\n  FMPI2C1_ER_IRQn             = 96,     /*!< FMPI2C1 Error Interrupt                                           */\n  LPTIM1_IRQn                 = 97,     /*!< LP TIM1 interrupt                                                 */\n  DFSDM2_FLT0_IRQn            = 98,     /*!< DFSDM2 Filter 0 global Interrupt                                  */\n  DFSDM2_FLT1_IRQn            = 99,     /*!< DFSDM2 Filter 1 global Interrupt                                  */\n  DFSDM2_FLT2_IRQn            = 100,    /*!< DFSDM2 Filter 2 global Interrupt                                  */\n  DFSDM2_FLT3_IRQn            = 101     /*!< DFSDM2 Filter 3 global Interrupt                                  */\n} IRQn_Type;\n\n/**\n  * @}\n  */\n\n#include \"core_cm4.h\"             /* Cortex-M4 processor and core peripherals */\n#include \"system_stm32f4xx.h\"\n#include <sys/stdint.h>\n\n/** @addtogroup Peripheral_registers_structures\n  * @{\n  */\n\n/**\n  * @brief Analog to Digital Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */\n  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */\n  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */\n  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */\n  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */\n  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\n  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\n  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\n  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\n  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */\n  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */\n  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */\n  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */\n  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */\n  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/\n  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */\n  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */\n  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */\n  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */\n  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */\n} ADC_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */\n  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */\n  __IO uint32_t CDR;    /*!< ADC common regular data register for dual\n                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */\n} ADC_Common_TypeDef;\n\n\n/**\n  * @brief Controller Area Network TxMailBox\n  */\n\ntypedef struct\n{\n  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */\n  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\n  __IO uint32_t TDLR; /*!< CAN mailbox data low register */\n  __IO uint32_t TDHR; /*!< CAN mailbox data high register */\n} CAN_TxMailBox_TypeDef;\n\n/**\n  * @brief Controller Area Network FIFOMailBox\n  */\n\ntypedef struct\n{\n  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */\n  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\n  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\n  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\n} CAN_FIFOMailBox_TypeDef;\n\n/**\n  * @brief Controller Area Network FilterRegister\n  */\n\ntypedef struct\n{\n  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\n  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\n} CAN_FilterRegister_TypeDef;\n\n/**\n  * @brief Controller Area Network\n  */\n\ntypedef struct\n{\n  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */\n  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */\n  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */\n  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */\n  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */\n  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */\n  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */\n  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */\n  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */\n  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */\n  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */\n  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */\n  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */\n  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */\n  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */\n  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */\n  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */\n  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */\n  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */\n  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */\n  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */\n  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */\n} CAN_TypeDef;\n\n/**\n  * @brief CRC calculation unit\n  */\n\ntypedef struct\n{\n  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */\n  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */\n  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */\n  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */\n  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */\n} CRC_TypeDef;\n\n/**\n  * @brief DFSDM module registers\n  */\ntypedef struct\n{\n  __IO uint32_t FLTCR1;      /*!< DFSDM control register1,                          Address offset: 0x100 */\n  __IO uint32_t FLTCR2;      /*!< DFSDM control register2,                          Address offset: 0x104 */\n  __IO uint32_t FLTISR;      /*!< DFSDM interrupt and status register,              Address offset: 0x108 */\n  __IO uint32_t FLTICR;      /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */\n  __IO uint32_t FLTJCHGR;    /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */\n  __IO uint32_t FLTFCR;      /*!< DFSDM filter control register,                    Address offset: 0x114 */\n  __IO uint32_t FLTJDATAR;   /*!< DFSDM data register for injected group,           Address offset: 0x118 */\n  __IO uint32_t FLTRDATAR;   /*!< DFSDM data register for regular group,            Address offset: 0x11C */\n  __IO uint32_t FLTAWHTR;    /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */\n  __IO uint32_t FLTAWLTR;    /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */\n  __IO uint32_t FLTAWSR;     /*!< DFSDM analog watchdog status register             Address offset: 0x128 */\n  __IO uint32_t FLTAWCFR;    /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */\n  __IO uint32_t FLTEXMAX;    /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */\n  __IO uint32_t FLTEXMIN;    /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */\n  __IO uint32_t FLTCNVTIMR;  /*!< DFSDM conversion timer,                           Address offset: 0x138 */\n} DFSDM_Filter_TypeDef;\n\n/**\n  * @brief DFSDM channel configuration registers\n  */\ntypedef struct\n{\n  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */\n  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */\n  __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and\n                                  short circuit detector register,                  Address offset: 0x08 */\n  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */\n  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */\n} DFSDM_Channel_TypeDef;\n\n/**\n  * @brief Digital to Analog Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */\n  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */\n  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\n  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */\n  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */\n  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\n  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */\n  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */\n  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */\n  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */\n  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */\n  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */\n  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */\n  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */\n} DAC_TypeDef;\n\n/**\n  * @brief Debug MCU\n  */\n\ntypedef struct\n{\n  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */\n  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */\n  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */\n  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */\n}DBGMCU_TypeDef;\n\n\n/**\n  * @brief DMA Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;     /*!< DMA stream x configuration register      */\n  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */\n  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */\n  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */\n  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */\n  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */\n} DMA_Stream_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */\n  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */\n  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */\n  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\n} DMA_TypeDef;\n\n/**\n  * @brief External Interrupt/Event Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */\n  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */\n  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */\n  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\n  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */\n  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */\n} EXTI_TypeDef;\n\n/**\n  * @brief FLASH Registers\n  */\n\ntypedef struct\n{\n  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */\n  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */\n  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */\n  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */\n  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */\n  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */\n  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */\n} FLASH_TypeDef;\n\n\n\n/**\n  * @brief Flexible Static Memory Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\n} FSMC_Bank1_TypeDef;\n\n/**\n  * @brief Flexible Static Memory Controller Bank1E\n  */\n\ntypedef struct\n{\n  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\n} FSMC_Bank1E_TypeDef;\n/**\n  * @brief General Purpose I/O\n  */\n\ntypedef struct\n{\n  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */\n  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */\n  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */\n  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\n  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */\n  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */\n  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */\n  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */\n  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\n} GPIO_TypeDef;\n\n/**\n  * @brief System configuration controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */\n  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */\n  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\n  uint32_t      RESERVED;     /*!< Reserved, 0x18                                                               */\n  __IO uint32_t CFGR2;        /*!< SYSCFG Configuration register2,                    Address offset: 0x1C      */\n  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */\n  uint32_t      RESERVED1[2]; /*!< Reserved, 0x24-0x28                                                          */\n  __IO uint32_t CFGR;         /*!< SYSCFG Configuration register,                     Address offset: 0x2C      */\n  __IO uint32_t MCHDLYCR;     /*!< SYSCFG multi-channel delay register,               Address offset: 0x30      */\n} SYSCFG_TypeDef;\n\n/**\n  * @brief Inter-integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */\n  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */\n  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */\n  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */\n  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */\n  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */\n  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */\n  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */\n  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */\n} I2C_TypeDef;\n\n/**\n  * @brief Inter-integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< FMPI2C Control register 1,            Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< FMPI2C Control register 2,            Address offset: 0x04 */\n  __IO uint32_t OAR1;        /*!< FMPI2C Own address 1 register,        Address offset: 0x08 */\n  __IO uint32_t OAR2;        /*!< FMPI2C Own address 2 register,        Address offset: 0x0C */\n  __IO uint32_t TIMINGR;     /*!< FMPI2C Timing register,               Address offset: 0x10 */\n  __IO uint32_t TIMEOUTR;    /*!< FMPI2C Timeout register,              Address offset: 0x14 */\n  __IO uint32_t ISR;         /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */\n  __IO uint32_t ICR;         /*!< FMPI2C Interrupt clear register,      Address offset: 0x1C */\n  __IO uint32_t PECR;        /*!< FMPI2C PEC register,                  Address offset: 0x20 */\n  __IO uint32_t RXDR;        /*!< FMPI2C Receive data register,         Address offset: 0x24 */\n  __IO uint32_t TXDR;        /*!< FMPI2C Transmit data register,        Address offset: 0x28 */\n} FMPI2C_TypeDef;\n\n/**\n  * @brief Independent WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */\n  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */\n  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */\n  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */\n} IWDG_TypeDef;\n\n\n/**\n  * @brief Power Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */\n  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */\n} PWR_TypeDef;\n\n/**\n  * @brief Reset and Clock Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */\n  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */\n  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */\n  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */\n  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */\n  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */\n  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */\n  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */\n  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */\n  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */\n  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */\n  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */\n  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */\n  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */\n  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */\n  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */\n  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */\n  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\n  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\n  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\n  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */\n  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\n  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\n  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */\n  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */\n  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */\n  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */\n  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */\n  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */\n  uint32_t      RESERVED7;     /*!< Reserved, 0x84                                                                    */\n  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */\n  __IO uint32_t CKGATENR;      /*!< RCC Clocks Gated ENable Register,                            Address offset: 0x90 */\n  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x94 */\n} RCC_TypeDef;\n\n/**\n  * @brief Real-Time Clock\n  */\n\ntypedef struct\n{\n  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */\n  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */\n  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */\n  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */\n  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */\n  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */\n  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */\n  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */\n  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */\n  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */\n  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */\n  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */\n  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */\n  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */\n  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */\n  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */\n  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */\n  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */\n  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */\n  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */\n  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */\n  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */\n  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */\n  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */\n  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */\n  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */\n  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */\n  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */\n  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */\n  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */\n  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */\n  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */\n  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */\n  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */\n  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */\n  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */\n  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */\n  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */\n  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */\n  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */\n} RTC_TypeDef;\n\n/**\n  * @brief Serial Audio Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */\n} SAI_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */\n  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */\n  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */\n  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */\n  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */\n  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */\n  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */\n  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */\n} SAI_Block_TypeDef;\n\n/**\n  * @brief SD host Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t POWER;                 /*!< SDIO power control register,    Address offset: 0x00 */\n  __IO uint32_t CLKCR;                 /*!< SDI clock control register,     Address offset: 0x04 */\n  __IO uint32_t ARG;                   /*!< SDIO argument register,         Address offset: 0x08 */\n  __IO uint32_t CMD;                   /*!< SDIO command register,          Address offset: 0x0C */\n  __IO const uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */\n  __IO const uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */\n  __IO const uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */\n  __IO const uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */\n  __IO const uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */\n  __IO uint32_t DTIMER;                /*!< SDIO data timer register,       Address offset: 0x24 */\n  __IO uint32_t DLEN;                  /*!< SDIO data length register,      Address offset: 0x28 */\n  __IO uint32_t DCTRL;                 /*!< SDIO data control register,     Address offset: 0x2C */\n  __IO const uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */\n  __IO const uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */\n  __IO uint32_t ICR;                   /*!< SDIO interrupt clear register,  Address offset: 0x38 */\n  __IO uint32_t MASK;                  /*!< SDIO mask register,             Address offset: 0x3C */\n  uint32_t      RESERVED0[2];          /*!< Reserved, 0x40-0x44                                  */\n  __IO const uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */\n  uint32_t      RESERVED1[13];         /*!< Reserved, 0x4C-0x7C                                  */\n  __IO uint32_t FIFO;                  /*!< SDIO data FIFO register,        Address offset: 0x80 */\n} SDIO_TypeDef;\n\n/**\n  * @brief Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */\n  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */\n  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */\n  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\n  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */\n  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */\n  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */\n  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */\n} SPI_TypeDef;\n\n/**\n  * @brief QUAD Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */\n  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */\n  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */\n  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */\n  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */\n  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */\n  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */\n  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */\n  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */\n  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */\n  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */\n  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */\n  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */\n} QUADSPI_TypeDef;\n\n/**\n  * @brief TIM\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */\n  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */\n  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */\n  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */\n  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */\n  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\n  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\n  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */\n  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */\n  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */\n  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */\n  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */\n  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */\n  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */\n  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */\n  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */\n  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */\n  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */\n  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */\n  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */\n} TIM_TypeDef;\n\n/**\n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */\n  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */\n  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */\n  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */\n  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */\n  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */\n  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */\n} USART_TypeDef;\n\n/**\n  * @brief Window WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */\n  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */\n  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */\n} WWDG_TypeDef;\n\n/**\n  * @brief RNG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */\n  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */\n  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */\n} RNG_TypeDef;\n\n/**\n  * @brief USB_OTG_Core_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */\n  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */\n  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */\n  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */\n  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */\n  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */\n  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */\n  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */\n  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */\n  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */\n  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */\n  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */\n  uint32_t Reserved30[2];             /*!< Reserved                                     030h */\n  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */\n  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */\n  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */\n  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */\n  uint32_t  Reserved6;                /*!< Reserved                                     050h */\n  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */\n  uint32_t  Reserved;                 /*!< Reserved                                     058h */\n  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */\n  uint32_t  Reserved43[40];           /*!< Reserved                                058h-0FFh */\n  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */\n  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                        */\n} USB_OTG_GlobalTypeDef;\n\n/**\n  * @brief USB_OTG_device_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */\n  __IO uint32_t DCTL;            /*!< dev Control Register         804h */\n  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */\n  uint32_t Reserved0C;           /*!< Reserved                     80Ch */\n  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */\n  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */\n  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */\n  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */\n  uint32_t  Reserved20;          /*!< Reserved                     820h */\n  uint32_t Reserved9;            /*!< Reserved                     824h */\n  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */\n  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */\n  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */\n  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */\n  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */\n  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */\n  uint32_t Reserved40;           /*!< dedicated EP mask            840h */\n  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */\n  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */\n  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */\n} USB_OTG_DeviceTypeDef;\n\n/**\n  * @brief USB_OTG_IN_Endpoint-Specific_Register\n  */\ntypedef struct\n{\n  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */\n  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */\n  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */\n  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\n  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\n} USB_OTG_INEndpointTypeDef;\n\n/**\n  * @brief USB_OTG_OUT_Endpoint-Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */\n  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */\n  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */\n  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\n} USB_OTG_OUTEndpointTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Mode_Register_Structures\n  */\ntypedef struct\n{\n  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */\n  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */\n  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */\n  uint32_t Reserved40C;           /*!< Reserved                             40Ch */\n  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */\n  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */\n  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */\n} USB_OTG_HostTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Channel_Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */\n  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */\n  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */\n  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */\n  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */\n  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */\n  uint32_t Reserved[2];           /*!< Reserved                                      */\n} USB_OTG_HostChannelTypeDef;\n\n/**\n  * @brief LPTIMER\n  */\ntypedef struct\n{\n  __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */\n  __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */\n  __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */\n  __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */\n  __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */\n  __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */\n  __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */\n  __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */\n  __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */\n} LPTIM_TypeDef;\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_memory_map\n  * @{\n  */\n#define FLASH_BASE            0x08000000UL /*!< FLASH (up to 1.5 MB) base address in the alias region                      */\n#define SRAM1_BASE            0x20000000UL /*!< SRAM1(256 KB) base address in the alias region                             */\n#define SRAM2_BASE            0x20040000UL /*!< SRAM2(64 KB) base address in the alias region                              */\n#define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */\n#define FSMC_R_BASE           0xA0000000UL /*!< FSMC registers base address                                                */\n#define QSPI_R_BASE           0xA0001000UL /*!< QuadSPI registers base address                                             */\n#define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(256 KB) base address in the bit-band region                          */\n#define SRAM2_BB_BASE         0x22800000UL /*!< SRAM2(64 KB) base address in the bit-band region                           */\n#define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */\n#define FLASH_END             0x0817FFFFUL /*!< FLASH end address                                                          */\n#define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */\n#define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */\n\n/* Legacy defines */\n#define SRAM_BASE             SRAM1_BASE\n#define SRAM_BB_BASE          SRAM1_BB_BASE\n\n/*!< Peripheral memory map */\n#define APB1PERIPH_BASE       PERIPH_BASE\n#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)\n#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)\n#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)\n\n/*!< APB1 peripherals */\n#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)\n#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)\n#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)\n#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)\n#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)\n#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)\n#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)\n#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)\n#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)\n#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x2400UL)\n#define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)\n#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)\n#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)\n#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400UL)\n#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)\n#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)\n#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000UL)\n#define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)\n#define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)\n#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)\n#define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)\n#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)\n#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)\n#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)\n#define FMPI2C1_BASE          (APB1PERIPH_BASE + 0x6000UL)\n#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)\n#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)\n#define CAN3_BASE             (APB1PERIPH_BASE + 0x6C00UL)\n#define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)\n#define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)\n#define UART7_BASE            (APB1PERIPH_BASE + 0x7800UL)\n#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00UL)\n\n/*!< APB2 peripherals */\n#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)\n#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)\n#define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)\n#define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)\n#define UART9_BASE            (APB2PERIPH_BASE + 0x1800UL)\n#define UART10_BASE           (APB2PERIPH_BASE + 0x1C00UL)\n#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)\n#define ADC1_COMMON_BASE      (APB2PERIPH_BASE + 0x2300UL)\n/* Legacy define */\n#define ADC_BASE               ADC1_COMMON_BASE\n#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)\n#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)\n#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400UL)\n#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)\n#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)\n#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)\n#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)\n#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)\n#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000UL)\n#define DFSDM1_BASE           (APB2PERIPH_BASE + 0x6000UL)\n#define DFSDM2_BASE           (APB2PERIPH_BASE + 0x6400UL)\n#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)\n#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)\n#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)\n#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)\n#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)\n#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)\n#define DFSDM2_Channel0_BASE  (DFSDM2_BASE + 0x00UL)\n#define DFSDM2_Channel1_BASE  (DFSDM2_BASE + 0x20UL)\n#define DFSDM2_Channel2_BASE  (DFSDM2_BASE + 0x40UL)\n#define DFSDM2_Channel3_BASE  (DFSDM2_BASE + 0x60UL)\n#define DFSDM2_Channel4_BASE  (DFSDM2_BASE + 0x80UL)\n#define DFSDM2_Channel5_BASE  (DFSDM2_BASE + 0xA0UL)\n#define DFSDM2_Channel6_BASE  (DFSDM2_BASE + 0xC0UL)\n#define DFSDM2_Channel7_BASE  (DFSDM2_BASE + 0xE0UL)\n#define DFSDM2_Filter0_BASE   (DFSDM2_BASE + 0x100UL)\n#define DFSDM2_Filter1_BASE   (DFSDM2_BASE + 0x180UL)\n#define DFSDM2_Filter2_BASE   (DFSDM2_BASE + 0x200UL)\n#define DFSDM2_Filter3_BASE   (DFSDM2_BASE + 0x280UL)\n#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800UL)\n#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)\n#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)\n\n/*!< AHB1 peripherals */\n#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)\n#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)\n#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)\n#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)\n#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)\n#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)\n#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)\n#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)\n#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)\n#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)\n#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)\n#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)\n#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)\n#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)\n#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)\n#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)\n#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)\n#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)\n#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)\n#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)\n#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)\n#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)\n#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)\n#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)\n#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)\n#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)\n#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)\n#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)\n#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)\n\n/*!< AHB2 peripherals */\n#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800UL)\n\n\n/*!< FSMC Bankx registers base address */\n#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000UL)\n#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104UL)\n\n/*!< Debug MCU registers base address */\n#define DBGMCU_BASE           0xE0042000UL\n/*!< USB registers base address */\n#define USB_OTG_FS_PERIPH_BASE               0x50000000UL\n\n#define USB_OTG_GLOBAL_BASE                  0x000UL\n#define USB_OTG_DEVICE_BASE                  0x800UL\n#define USB_OTG_IN_ENDPOINT_BASE             0x900UL\n#define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL\n#define USB_OTG_EP_REG_SIZE                  0x20UL\n#define USB_OTG_HOST_BASE                    0x400UL\n#define USB_OTG_HOST_PORT_BASE               0x440UL\n#define USB_OTG_HOST_CHANNEL_BASE            0x500UL\n#define USB_OTG_HOST_CHANNEL_SIZE            0x20UL\n#define USB_OTG_PCGCCTL_BASE                 0xE00UL\n#define USB_OTG_FIFO_BASE                    0x1000UL\n#define USB_OTG_FIFO_SIZE                    0x1000UL\n\n#define UID_BASE                     0x1FFF7A10UL           /*!< Unique device ID register base address */\n#define FLASHSIZE_BASE               0x1FFF7A22UL           /*!< FLASH Size register base address       */\n#define PACKAGE_BASE                 0x1FFF7BF0UL           /*!< Package size register base address     */\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_declaration\n  * @{\n  */\n#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\n#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\n#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\n#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\n#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\n#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\n#define TIM12               ((TIM_TypeDef *) TIM12_BASE)\n#define TIM13               ((TIM_TypeDef *) TIM13_BASE)\n#define TIM14               ((TIM_TypeDef *) TIM14_BASE)\n#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\n#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\n#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\n#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)\n#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\n#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\n#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)\n#define USART2              ((USART_TypeDef *) USART2_BASE)\n#define USART3              ((USART_TypeDef *) USART3_BASE)\n#define UART4               ((USART_TypeDef *) UART4_BASE)\n#define UART5               ((USART_TypeDef *) UART5_BASE)\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\n#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\n#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\n#define FMPI2C1             ((FMPI2C_TypeDef *) FMPI2C1_BASE)\n#define CAN1                ((CAN_TypeDef *) CAN1_BASE)\n#define CAN2                ((CAN_TypeDef *) CAN2_BASE)\n#define CAN3                ((CAN_TypeDef *) CAN3_BASE)\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\n#define DAC1                ((DAC_TypeDef *) DAC_BASE)\n#define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */\n#define UART7               ((USART_TypeDef *) UART7_BASE)\n#define UART8               ((USART_TypeDef *) UART8_BASE)\n#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\n#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\n#define USART1              ((USART_TypeDef *) USART1_BASE)\n#define USART6              ((USART_TypeDef *) USART6_BASE)\n#define UART9               ((USART_TypeDef *) UART9_BASE)\n#define UART10              ((USART_TypeDef *) UART10_BASE)\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\n#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)\n/* Legacy define */\n#define ADC                  ADC1_COMMON\n#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\n#define SPI4                ((SPI_TypeDef *) SPI4_BASE)\n#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\n#define TIM9                ((TIM_TypeDef *) TIM9_BASE)\n#define TIM10               ((TIM_TypeDef *) TIM10_BASE)\n#define TIM11               ((TIM_TypeDef *) TIM11_BASE)\n#define SPI5                ((SPI_TypeDef *) SPI5_BASE)\n#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)\n#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)\n#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)\n#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)\n#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)\n#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)\n#define DFSDM2_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)\n#define DFSDM2_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)\n#define DFSDM2_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel2_BASE)\n#define DFSDM2_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel3_BASE)\n#define DFSDM2_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel4_BASE)\n#define DFSDM2_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel5_BASE)\n#define DFSDM2_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel6_BASE)\n#define DFSDM2_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel7_BASE)\n#define DFSDM2_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM2_Filter0_BASE)\n#define DFSDM2_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM2_Filter1_BASE)\n#define DFSDM2_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM2_Filter2_BASE)\n#define DFSDM2_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM2_Filter3_BASE)\n#define SAI1                ((SAI_TypeDef *) SAI1_BASE)\n#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\n#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\n#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\n#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\n#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)\n#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\n#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\n#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\n#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\n#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\n#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\n#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\n#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\n#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\n#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\n#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\n#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\n#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\n#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\n#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\n#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\n#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\n#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\n#define RNG                 ((RNG_TypeDef *) RNG_BASE)\n#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)\n#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)\n#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)\n#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\n#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_constants\n  * @{\n  */\n\n  /** @addtogroup Peripheral_Registers_Bits_Definition\n  * @{\n  */\n\n/******************************************************************************/\n/*                         Peripheral Registers_Bits_Definition               */\n/******************************************************************************/\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Analog to Digital Converter                         */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for ADC_SR register  ********************/\n#define ADC_SR_AWD_Pos            (0U)\n#define ADC_SR_AWD_Msk            (0x1UL << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */\n#define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */\n#define ADC_SR_EOC_Pos            (1U)\n#define ADC_SR_EOC_Msk            (0x1UL << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */\n#define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */\n#define ADC_SR_JEOC_Pos           (2U)\n#define ADC_SR_JEOC_Msk           (0x1UL << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */\n#define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */\n#define ADC_SR_JSTRT_Pos          (3U)\n#define ADC_SR_JSTRT_Msk          (0x1UL << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */\n#define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */\n#define ADC_SR_STRT_Pos           (4U)\n#define ADC_SR_STRT_Msk           (0x1UL << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */\n#define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */\n#define ADC_SR_OVR_Pos            (5U)\n#define ADC_SR_OVR_Msk            (0x1UL << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */\n#define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */\n\n/*******************  Bit definition for ADC_CR1 register  ********************/\n#define ADC_CR1_AWDCH_Pos         (0U)\n#define ADC_CR1_AWDCH_Msk         (0x1FUL << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */\n#define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\n#define ADC_CR1_AWDCH_0           (0x01UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */\n#define ADC_CR1_AWDCH_1           (0x02UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */\n#define ADC_CR1_AWDCH_2           (0x04UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */\n#define ADC_CR1_AWDCH_3           (0x08UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */\n#define ADC_CR1_AWDCH_4           (0x10UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */\n#define ADC_CR1_EOCIE_Pos         (5U)\n#define ADC_CR1_EOCIE_Msk         (0x1UL << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */\n#define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */\n#define ADC_CR1_AWDIE_Pos         (6U)\n#define ADC_CR1_AWDIE_Msk         (0x1UL << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */\n#define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */\n#define ADC_CR1_JEOCIE_Pos        (7U)\n#define ADC_CR1_JEOCIE_Msk        (0x1UL << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */\n#define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */\n#define ADC_CR1_SCAN_Pos          (8U)\n#define ADC_CR1_SCAN_Msk          (0x1UL << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */\n#define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */\n#define ADC_CR1_AWDSGL_Pos        (9U)\n#define ADC_CR1_AWDSGL_Msk        (0x1UL << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */\n#define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */\n#define ADC_CR1_JAUTO_Pos         (10U)\n#define ADC_CR1_JAUTO_Msk         (0x1UL << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */\n#define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */\n#define ADC_CR1_DISCEN_Pos        (11U)\n#define ADC_CR1_DISCEN_Msk        (0x1UL << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */\n#define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */\n#define ADC_CR1_JDISCEN_Pos       (12U)\n#define ADC_CR1_JDISCEN_Msk       (0x1UL << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */\n#define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */\n#define ADC_CR1_DISCNUM_Pos       (13U)\n#define ADC_CR1_DISCNUM_Msk       (0x7UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */\n#define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\n#define ADC_CR1_DISCNUM_0         (0x1UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */\n#define ADC_CR1_DISCNUM_1         (0x2UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */\n#define ADC_CR1_DISCNUM_2         (0x4UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */\n#define ADC_CR1_JAWDEN_Pos        (22U)\n#define ADC_CR1_JAWDEN_Msk        (0x1UL << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */\n#define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */\n#define ADC_CR1_AWDEN_Pos         (23U)\n#define ADC_CR1_AWDEN_Msk         (0x1UL << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */\n#define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */\n#define ADC_CR1_RES_Pos           (24U)\n#define ADC_CR1_RES_Msk           (0x3UL << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */\n#define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */\n#define ADC_CR1_RES_0             (0x1UL << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */\n#define ADC_CR1_RES_1             (0x2UL << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */\n#define ADC_CR1_OVRIE_Pos         (26U)\n#define ADC_CR1_OVRIE_Msk         (0x1UL << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */\n#define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */\n\n/*******************  Bit definition for ADC_CR2 register  ********************/\n#define ADC_CR2_ADON_Pos          (0U)\n#define ADC_CR2_ADON_Msk          (0x1UL << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */\n#define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */\n#define ADC_CR2_CONT_Pos          (1U)\n#define ADC_CR2_CONT_Msk          (0x1UL << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */\n#define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */\n#define ADC_CR2_DMA_Pos           (8U)\n#define ADC_CR2_DMA_Msk           (0x1UL << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */\n#define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */\n#define ADC_CR2_DDS_Pos           (9U)\n#define ADC_CR2_DDS_Msk           (0x1UL << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */\n#define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */\n#define ADC_CR2_EOCS_Pos          (10U)\n#define ADC_CR2_EOCS_Msk          (0x1UL << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */\n#define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */\n#define ADC_CR2_ALIGN_Pos         (11U)\n#define ADC_CR2_ALIGN_Msk         (0x1UL << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */\n#define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */\n#define ADC_CR2_JEXTSEL_Pos       (16U)\n#define ADC_CR2_JEXTSEL_Msk       (0xFUL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */\n#define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */\n#define ADC_CR2_JEXTSEL_0         (0x1UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */\n#define ADC_CR2_JEXTSEL_1         (0x2UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */\n#define ADC_CR2_JEXTSEL_2         (0x4UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */\n#define ADC_CR2_JEXTSEL_3         (0x8UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */\n#define ADC_CR2_JEXTEN_Pos        (20U)\n#define ADC_CR2_JEXTEN_Msk        (0x3UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */\n#define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\n#define ADC_CR2_JEXTEN_0          (0x1UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */\n#define ADC_CR2_JEXTEN_1          (0x2UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */\n#define ADC_CR2_JSWSTART_Pos      (22U)\n#define ADC_CR2_JSWSTART_Msk      (0x1UL << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */\n#define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */\n#define ADC_CR2_EXTSEL_Pos        (24U)\n#define ADC_CR2_EXTSEL_Msk        (0xFUL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */\n#define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\n#define ADC_CR2_EXTSEL_0          (0x1UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */\n#define ADC_CR2_EXTSEL_1          (0x2UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */\n#define ADC_CR2_EXTSEL_2          (0x4UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */\n#define ADC_CR2_EXTSEL_3          (0x8UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */\n#define ADC_CR2_EXTEN_Pos         (28U)\n#define ADC_CR2_EXTEN_Msk         (0x3UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */\n#define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\n#define ADC_CR2_EXTEN_0           (0x1UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */\n#define ADC_CR2_EXTEN_1           (0x2UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */\n#define ADC_CR2_SWSTART_Pos       (30U)\n#define ADC_CR2_SWSTART_Msk       (0x1UL << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */\n#define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */\n\n/******************  Bit definition for ADC_SMPR1 register  *******************/\n#define ADC_SMPR1_SMP10_Pos       (0U)\n#define ADC_SMPR1_SMP10_Msk       (0x7UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */\n#define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\n#define ADC_SMPR1_SMP10_0         (0x1UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */\n#define ADC_SMPR1_SMP10_1         (0x2UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */\n#define ADC_SMPR1_SMP10_2         (0x4UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */\n#define ADC_SMPR1_SMP11_Pos       (3U)\n#define ADC_SMPR1_SMP11_Msk       (0x7UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */\n#define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\n#define ADC_SMPR1_SMP11_0         (0x1UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */\n#define ADC_SMPR1_SMP11_1         (0x2UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */\n#define ADC_SMPR1_SMP11_2         (0x4UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */\n#define ADC_SMPR1_SMP12_Pos       (6U)\n#define ADC_SMPR1_SMP12_Msk       (0x7UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */\n#define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\n#define ADC_SMPR1_SMP12_0         (0x1UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */\n#define ADC_SMPR1_SMP12_1         (0x2UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */\n#define ADC_SMPR1_SMP12_2         (0x4UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */\n#define ADC_SMPR1_SMP13_Pos       (9U)\n#define ADC_SMPR1_SMP13_Msk       (0x7UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */\n#define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\n#define ADC_SMPR1_SMP13_0         (0x1UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */\n#define ADC_SMPR1_SMP13_1         (0x2UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */\n#define ADC_SMPR1_SMP13_2         (0x4UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */\n#define ADC_SMPR1_SMP14_Pos       (12U)\n#define ADC_SMPR1_SMP14_Msk       (0x7UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */\n#define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\n#define ADC_SMPR1_SMP14_0         (0x1UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */\n#define ADC_SMPR1_SMP14_1         (0x2UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */\n#define ADC_SMPR1_SMP14_2         (0x4UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */\n#define ADC_SMPR1_SMP15_Pos       (15U)\n#define ADC_SMPR1_SMP15_Msk       (0x7UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */\n#define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\n#define ADC_SMPR1_SMP15_0         (0x1UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */\n#define ADC_SMPR1_SMP15_1         (0x2UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */\n#define ADC_SMPR1_SMP15_2         (0x4UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */\n#define ADC_SMPR1_SMP16_Pos       (18U)\n#define ADC_SMPR1_SMP16_Msk       (0x7UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */\n#define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\n#define ADC_SMPR1_SMP16_0         (0x1UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */\n#define ADC_SMPR1_SMP16_1         (0x2UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */\n#define ADC_SMPR1_SMP16_2         (0x4UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */\n#define ADC_SMPR1_SMP17_Pos       (21U)\n#define ADC_SMPR1_SMP17_Msk       (0x7UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */\n#define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\n#define ADC_SMPR1_SMP17_0         (0x1UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */\n#define ADC_SMPR1_SMP17_1         (0x2UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */\n#define ADC_SMPR1_SMP17_2         (0x4UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */\n#define ADC_SMPR1_SMP18_Pos       (24U)\n#define ADC_SMPR1_SMP18_Msk       (0x7UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */\n#define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\n#define ADC_SMPR1_SMP18_0         (0x1UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */\n#define ADC_SMPR1_SMP18_1         (0x2UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */\n#define ADC_SMPR1_SMP18_2         (0x4UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */\n\n/******************  Bit definition for ADC_SMPR2 register  *******************/\n#define ADC_SMPR2_SMP0_Pos        (0U)\n#define ADC_SMPR2_SMP0_Msk        (0x7UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */\n#define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\n#define ADC_SMPR2_SMP0_0          (0x1UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */\n#define ADC_SMPR2_SMP0_1          (0x2UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */\n#define ADC_SMPR2_SMP0_2          (0x4UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */\n#define ADC_SMPR2_SMP1_Pos        (3U)\n#define ADC_SMPR2_SMP1_Msk        (0x7UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */\n#define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\n#define ADC_SMPR2_SMP1_0          (0x1UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */\n#define ADC_SMPR2_SMP1_1          (0x2UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */\n#define ADC_SMPR2_SMP1_2          (0x4UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */\n#define ADC_SMPR2_SMP2_Pos        (6U)\n#define ADC_SMPR2_SMP2_Msk        (0x7UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */\n#define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\n#define ADC_SMPR2_SMP2_0          (0x1UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */\n#define ADC_SMPR2_SMP2_1          (0x2UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */\n#define ADC_SMPR2_SMP2_2          (0x4UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */\n#define ADC_SMPR2_SMP3_Pos        (9U)\n#define ADC_SMPR2_SMP3_Msk        (0x7UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */\n#define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\n#define ADC_SMPR2_SMP3_0          (0x1UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */\n#define ADC_SMPR2_SMP3_1          (0x2UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */\n#define ADC_SMPR2_SMP3_2          (0x4UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */\n#define ADC_SMPR2_SMP4_Pos        (12U)\n#define ADC_SMPR2_SMP4_Msk        (0x7UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */\n#define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\n#define ADC_SMPR2_SMP4_0          (0x1UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */\n#define ADC_SMPR2_SMP4_1          (0x2UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */\n#define ADC_SMPR2_SMP4_2          (0x4UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */\n#define ADC_SMPR2_SMP5_Pos        (15U)\n#define ADC_SMPR2_SMP5_Msk        (0x7UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */\n#define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\n#define ADC_SMPR2_SMP5_0          (0x1UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */\n#define ADC_SMPR2_SMP5_1          (0x2UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */\n#define ADC_SMPR2_SMP5_2          (0x4UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */\n#define ADC_SMPR2_SMP6_Pos        (18U)\n#define ADC_SMPR2_SMP6_Msk        (0x7UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */\n#define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\n#define ADC_SMPR2_SMP6_0          (0x1UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */\n#define ADC_SMPR2_SMP6_1          (0x2UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */\n#define ADC_SMPR2_SMP6_2          (0x4UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */\n#define ADC_SMPR2_SMP7_Pos        (21U)\n#define ADC_SMPR2_SMP7_Msk        (0x7UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */\n#define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\n#define ADC_SMPR2_SMP7_0          (0x1UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */\n#define ADC_SMPR2_SMP7_1          (0x2UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */\n#define ADC_SMPR2_SMP7_2          (0x4UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */\n#define ADC_SMPR2_SMP8_Pos        (24U)\n#define ADC_SMPR2_SMP8_Msk        (0x7UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */\n#define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\n#define ADC_SMPR2_SMP8_0          (0x1UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */\n#define ADC_SMPR2_SMP8_1          (0x2UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */\n#define ADC_SMPR2_SMP8_2          (0x4UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */\n#define ADC_SMPR2_SMP9_Pos        (27U)\n#define ADC_SMPR2_SMP9_Msk        (0x7UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */\n#define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\n#define ADC_SMPR2_SMP9_0          (0x1UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */\n#define ADC_SMPR2_SMP9_1          (0x2UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */\n#define ADC_SMPR2_SMP9_2          (0x4UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */\n\n/******************  Bit definition for ADC_JOFR1 register  *******************/\n#define ADC_JOFR1_JOFFSET1_Pos    (0U)\n#define ADC_JOFR1_JOFFSET1_Msk    (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */\n\n/******************  Bit definition for ADC_JOFR2 register  *******************/\n#define ADC_JOFR2_JOFFSET2_Pos    (0U)\n#define ADC_JOFR2_JOFFSET2_Msk    (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */\n\n/******************  Bit definition for ADC_JOFR3 register  *******************/\n#define ADC_JOFR3_JOFFSET3_Pos    (0U)\n#define ADC_JOFR3_JOFFSET3_Msk    (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */\n\n/******************  Bit definition for ADC_JOFR4 register  *******************/\n#define ADC_JOFR4_JOFFSET4_Pos    (0U)\n#define ADC_JOFR4_JOFFSET4_Msk    (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */\n\n/*******************  Bit definition for ADC_HTR register  ********************/\n#define ADC_HTR_HT_Pos            (0U)\n#define ADC_HTR_HT_Msk            (0xFFFUL << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */\n#define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */\n\n/*******************  Bit definition for ADC_LTR register  ********************/\n#define ADC_LTR_LT_Pos            (0U)\n#define ADC_LTR_LT_Msk            (0xFFFUL << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */\n#define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */\n\n/*******************  Bit definition for ADC_SQR1 register  *******************/\n#define ADC_SQR1_SQ13_Pos         (0U)\n#define ADC_SQR1_SQ13_Msk         (0x1FUL << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */\n#define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\n#define ADC_SQR1_SQ13_0           (0x01UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */\n#define ADC_SQR1_SQ13_1           (0x02UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */\n#define ADC_SQR1_SQ13_2           (0x04UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */\n#define ADC_SQR1_SQ13_3           (0x08UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */\n#define ADC_SQR1_SQ13_4           (0x10UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */\n#define ADC_SQR1_SQ14_Pos         (5U)\n#define ADC_SQR1_SQ14_Msk         (0x1FUL << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */\n#define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\n#define ADC_SQR1_SQ14_0           (0x01UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */\n#define ADC_SQR1_SQ14_1           (0x02UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */\n#define ADC_SQR1_SQ14_2           (0x04UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */\n#define ADC_SQR1_SQ14_3           (0x08UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */\n#define ADC_SQR1_SQ14_4           (0x10UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */\n#define ADC_SQR1_SQ15_Pos         (10U)\n#define ADC_SQR1_SQ15_Msk         (0x1FUL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */\n#define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\n#define ADC_SQR1_SQ15_0           (0x01UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */\n#define ADC_SQR1_SQ15_1           (0x02UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */\n#define ADC_SQR1_SQ15_2           (0x04UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */\n#define ADC_SQR1_SQ15_3           (0x08UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */\n#define ADC_SQR1_SQ15_4           (0x10UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */\n#define ADC_SQR1_SQ16_Pos         (15U)\n#define ADC_SQR1_SQ16_Msk         (0x1FUL << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\n#define ADC_SQR1_SQ16_0           (0x01UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR1_SQ16_1           (0x02UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR1_SQ16_2           (0x04UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR1_SQ16_3           (0x08UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR1_SQ16_4           (0x10UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR1_L_Pos            (20U)\n#define ADC_SQR1_L_Msk            (0xFUL << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */\n#define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */\n#define ADC_SQR1_L_0              (0x1UL << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */\n#define ADC_SQR1_L_1              (0x2UL << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */\n#define ADC_SQR1_L_2              (0x4UL << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */\n#define ADC_SQR1_L_3              (0x8UL << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */\n\n/*******************  Bit definition for ADC_SQR2 register  *******************/\n#define ADC_SQR2_SQ7_Pos          (0U)\n#define ADC_SQR2_SQ7_Msk          (0x1FUL << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\n#define ADC_SQR2_SQ7_0            (0x01UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR2_SQ7_1            (0x02UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR2_SQ7_2            (0x04UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR2_SQ7_3            (0x08UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR2_SQ7_4            (0x10UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR2_SQ8_Pos          (5U)\n#define ADC_SQR2_SQ8_Msk          (0x1FUL << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\n#define ADC_SQR2_SQ8_0            (0x01UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR2_SQ8_1            (0x02UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR2_SQ8_2            (0x04UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR2_SQ8_3            (0x08UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR2_SQ8_4            (0x10UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR2_SQ9_Pos          (10U)\n#define ADC_SQR2_SQ9_Msk          (0x1FUL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\n#define ADC_SQR2_SQ9_0            (0x01UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR2_SQ9_1            (0x02UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR2_SQ9_2            (0x04UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR2_SQ9_3            (0x08UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR2_SQ9_4            (0x10UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR2_SQ10_Pos         (15U)\n#define ADC_SQR2_SQ10_Msk         (0x1FUL << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\n#define ADC_SQR2_SQ10_0           (0x01UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR2_SQ10_1           (0x02UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR2_SQ10_2           (0x04UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR2_SQ10_3           (0x08UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR2_SQ10_4           (0x10UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR2_SQ11_Pos         (20U)\n#define ADC_SQR2_SQ11_Msk         (0x1FUL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */\n#define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\n#define ADC_SQR2_SQ11_0           (0x01UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */\n#define ADC_SQR2_SQ11_1           (0x02UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */\n#define ADC_SQR2_SQ11_2           (0x04UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */\n#define ADC_SQR2_SQ11_3           (0x08UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */\n#define ADC_SQR2_SQ11_4           (0x10UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */\n#define ADC_SQR2_SQ12_Pos         (25U)\n#define ADC_SQR2_SQ12_Msk         (0x1FUL << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */\n#define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\n#define ADC_SQR2_SQ12_0           (0x01UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */\n#define ADC_SQR2_SQ12_1           (0x02UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */\n#define ADC_SQR2_SQ12_2           (0x04UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */\n#define ADC_SQR2_SQ12_3           (0x08UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */\n#define ADC_SQR2_SQ12_4           (0x10UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_SQR3 register  *******************/\n#define ADC_SQR3_SQ1_Pos          (0U)\n#define ADC_SQR3_SQ1_Msk          (0x1FUL << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\n#define ADC_SQR3_SQ1_0            (0x01UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR3_SQ1_1            (0x02UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR3_SQ1_2            (0x04UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR3_SQ1_3            (0x08UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR3_SQ1_4            (0x10UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR3_SQ2_Pos          (5U)\n#define ADC_SQR3_SQ2_Msk          (0x1FUL << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\n#define ADC_SQR3_SQ2_0            (0x01UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR3_SQ2_1            (0x02UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR3_SQ2_2            (0x04UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR3_SQ2_3            (0x08UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR3_SQ2_4            (0x10UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR3_SQ3_Pos          (10U)\n#define ADC_SQR3_SQ3_Msk          (0x1FUL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\n#define ADC_SQR3_SQ3_0            (0x01UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR3_SQ3_1            (0x02UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR3_SQ3_2            (0x04UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR3_SQ3_3            (0x08UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR3_SQ3_4            (0x10UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR3_SQ4_Pos          (15U)\n#define ADC_SQR3_SQ4_Msk          (0x1FUL << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */\n#define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\n#define ADC_SQR3_SQ4_0            (0x01UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */\n#define ADC_SQR3_SQ4_1            (0x02UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */\n#define ADC_SQR3_SQ4_2            (0x04UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */\n#define ADC_SQR3_SQ4_3            (0x08UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */\n#define ADC_SQR3_SQ4_4            (0x10UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */\n#define ADC_SQR3_SQ5_Pos          (20U)\n#define ADC_SQR3_SQ5_Msk          (0x1FUL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */\n#define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\n#define ADC_SQR3_SQ5_0            (0x01UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */\n#define ADC_SQR3_SQ5_1            (0x02UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */\n#define ADC_SQR3_SQ5_2            (0x04UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */\n#define ADC_SQR3_SQ5_3            (0x08UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */\n#define ADC_SQR3_SQ5_4            (0x10UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */\n#define ADC_SQR3_SQ6_Pos          (25U)\n#define ADC_SQR3_SQ6_Msk          (0x1FUL << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */\n#define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\n#define ADC_SQR3_SQ6_0            (0x01UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */\n#define ADC_SQR3_SQ6_1            (0x02UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */\n#define ADC_SQR3_SQ6_2            (0x04UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */\n#define ADC_SQR3_SQ6_3            (0x08UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */\n#define ADC_SQR3_SQ6_4            (0x10UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_JSQR register  *******************/\n#define ADC_JSQR_JSQ1_Pos         (0U)\n#define ADC_JSQR_JSQ1_Msk         (0x1FUL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */\n#define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */\n#define ADC_JSQR_JSQ1_0           (0x01UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */\n#define ADC_JSQR_JSQ1_1           (0x02UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */\n#define ADC_JSQR_JSQ1_2           (0x04UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */\n#define ADC_JSQR_JSQ1_3           (0x08UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */\n#define ADC_JSQR_JSQ1_4           (0x10UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */\n#define ADC_JSQR_JSQ2_Pos         (5U)\n#define ADC_JSQR_JSQ2_Msk         (0x1FUL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */\n#define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\n#define ADC_JSQR_JSQ2_0           (0x01UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */\n#define ADC_JSQR_JSQ2_1           (0x02UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */\n#define ADC_JSQR_JSQ2_2           (0x04UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */\n#define ADC_JSQR_JSQ2_3           (0x08UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */\n#define ADC_JSQR_JSQ2_4           (0x10UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */\n#define ADC_JSQR_JSQ3_Pos         (10U)\n#define ADC_JSQR_JSQ3_Msk         (0x1FUL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */\n#define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\n#define ADC_JSQR_JSQ3_0           (0x01UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */\n#define ADC_JSQR_JSQ3_1           (0x02UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */\n#define ADC_JSQR_JSQ3_2           (0x04UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */\n#define ADC_JSQR_JSQ3_3           (0x08UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */\n#define ADC_JSQR_JSQ3_4           (0x10UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */\n#define ADC_JSQR_JSQ4_Pos         (15U)\n#define ADC_JSQR_JSQ4_Msk         (0x1FUL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */\n#define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\n#define ADC_JSQR_JSQ4_0           (0x01UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */\n#define ADC_JSQR_JSQ4_1           (0x02UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */\n#define ADC_JSQR_JSQ4_2           (0x04UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */\n#define ADC_JSQR_JSQ4_3           (0x08UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */\n#define ADC_JSQR_JSQ4_4           (0x10UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */\n#define ADC_JSQR_JL_Pos           (20U)\n#define ADC_JSQR_JL_Msk           (0x3UL << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */\n#define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */\n#define ADC_JSQR_JL_0             (0x1UL << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */\n#define ADC_JSQR_JL_1             (0x2UL << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */\n\n/*******************  Bit definition for ADC_JDR1 register  *******************/\n#define ADC_JDR1_JDATA_Pos        (0U)\n#define ADC_JDR1_JDATA_Msk        (0xFFFFUL << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR2 register  *******************/\n#define ADC_JDR2_JDATA_Pos        (0U)\n#define ADC_JDR2_JDATA_Msk        (0xFFFFUL << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR3 register  *******************/\n#define ADC_JDR3_JDATA_Pos        (0U)\n#define ADC_JDR3_JDATA_Msk        (0xFFFFUL << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR4 register  *******************/\n#define ADC_JDR4_JDATA_Pos        (0U)\n#define ADC_JDR4_JDATA_Msk        (0xFFFFUL << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */\n\n/********************  Bit definition for ADC_DR register  ********************/\n#define ADC_DR_DATA_Pos           (0U)\n#define ADC_DR_DATA_Msk           (0xFFFFUL << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */\n#define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */\n#define ADC_DR_ADC2DATA_Pos       (16U)\n#define ADC_DR_ADC2DATA_Msk       (0xFFFFUL << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */\n#define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */\n\n/*******************  Bit definition for ADC_CSR register  ********************/\n#define ADC_CSR_AWD1_Pos          (0U)\n#define ADC_CSR_AWD1_Msk          (0x1UL << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */\n#define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */\n#define ADC_CSR_EOC1_Pos          (1U)\n#define ADC_CSR_EOC1_Msk          (0x1UL << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */\n#define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */\n#define ADC_CSR_JEOC1_Pos         (2U)\n#define ADC_CSR_JEOC1_Msk         (0x1UL << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */\n#define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */\n#define ADC_CSR_JSTRT1_Pos        (3U)\n#define ADC_CSR_JSTRT1_Msk        (0x1UL << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */\n#define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */\n#define ADC_CSR_STRT1_Pos         (4U)\n#define ADC_CSR_STRT1_Msk         (0x1UL << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */\n#define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */\n#define ADC_CSR_OVR1_Pos          (5U)\n#define ADC_CSR_OVR1_Msk          (0x1UL << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */\n#define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */\n\n/* Legacy defines */\n#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1\n\n/*******************  Bit definition for ADC_CCR register  ********************/\n#define ADC_CCR_MULTI_Pos         (0U)\n#define ADC_CCR_MULTI_Msk         (0x1FUL << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */\n#define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */\n#define ADC_CCR_MULTI_0           (0x01UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */\n#define ADC_CCR_MULTI_1           (0x02UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */\n#define ADC_CCR_MULTI_2           (0x04UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */\n#define ADC_CCR_MULTI_3           (0x08UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */\n#define ADC_CCR_MULTI_4           (0x10UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */\n#define ADC_CCR_DELAY_Pos         (8U)\n#define ADC_CCR_DELAY_Msk         (0xFUL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */\n#define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */\n#define ADC_CCR_DELAY_0           (0x1UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */\n#define ADC_CCR_DELAY_1           (0x2UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */\n#define ADC_CCR_DELAY_2           (0x4UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */\n#define ADC_CCR_DELAY_3           (0x8UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */\n#define ADC_CCR_DDS_Pos           (13U)\n#define ADC_CCR_DDS_Msk           (0x1UL << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */\n#define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */\n#define ADC_CCR_DMA_Pos           (14U)\n#define ADC_CCR_DMA_Msk           (0x3UL << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */\n#define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */\n#define ADC_CCR_DMA_0             (0x1UL << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */\n#define ADC_CCR_DMA_1             (0x2UL << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */\n#define ADC_CCR_ADCPRE_Pos        (16U)\n#define ADC_CCR_ADCPRE_Msk        (0x3UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */\n#define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */\n#define ADC_CCR_ADCPRE_0          (0x1UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */\n#define ADC_CCR_ADCPRE_1          (0x2UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */\n#define ADC_CCR_VBATE_Pos         (22U)\n#define ADC_CCR_VBATE_Msk         (0x1UL << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */\n#define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */\n#define ADC_CCR_TSVREFE_Pos       (23U)\n#define ADC_CCR_TSVREFE_Msk       (0x1UL << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */\n#define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */\n\n/*******************  Bit definition for ADC_CDR register  ********************/\n#define ADC_CDR_DATA1_Pos         (0U)\n#define ADC_CDR_DATA1_Msk         (0xFFFFUL << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */\n#define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */\n#define ADC_CDR_DATA2_Pos         (16U)\n#define ADC_CDR_DATA2_Msk         (0xFFFFUL << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */\n#define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */\n\n/* Legacy defines */\n#define ADC_CDR_RDATA_MST         ADC_CDR_DATA1\n#define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Controller Area Network                            */\n/*                                                                            */\n/******************************************************************************/\n/*!<CAN control and status registers */\n/*******************  Bit definition for CAN_MCR register  ********************/\n#define CAN_MCR_INRQ_Pos       (0U)\n#define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */\n#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */\n#define CAN_MCR_SLEEP_Pos      (1U)\n#define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */\n#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */\n#define CAN_MCR_TXFP_Pos       (2U)\n#define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */\n#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */\n#define CAN_MCR_RFLM_Pos       (3U)\n#define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */\n#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */\n#define CAN_MCR_NART_Pos       (4U)\n#define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */\n#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */\n#define CAN_MCR_AWUM_Pos       (5U)\n#define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */\n#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */\n#define CAN_MCR_ABOM_Pos       (6U)\n#define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */\n#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */\n#define CAN_MCR_TTCM_Pos       (7U)\n#define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */\n#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */\n#define CAN_MCR_RESET_Pos      (15U)\n#define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */\n#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */\n#define CAN_MCR_DBF_Pos        (16U)\n#define CAN_MCR_DBF_Msk        (0x1UL << CAN_MCR_DBF_Pos)                       /*!< 0x00010000 */\n#define CAN_MCR_DBF            CAN_MCR_DBF_Msk                                 /*!<bxCAN Debug freeze */\n/*******************  Bit definition for CAN_MSR register  ********************/\n#define CAN_MSR_INAK_Pos       (0U)\n#define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */\n#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */\n#define CAN_MSR_SLAK_Pos       (1U)\n#define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */\n#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */\n#define CAN_MSR_ERRI_Pos       (2U)\n#define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */\n#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */\n#define CAN_MSR_WKUI_Pos       (3U)\n#define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */\n#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */\n#define CAN_MSR_SLAKI_Pos      (4U)\n#define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */\n#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */\n#define CAN_MSR_TXM_Pos        (8U)\n#define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */\n#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */\n#define CAN_MSR_RXM_Pos        (9U)\n#define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */\n#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */\n#define CAN_MSR_SAMP_Pos       (10U)\n#define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */\n#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */\n#define CAN_MSR_RX_Pos         (11U)\n#define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */\n#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */\n\n/*******************  Bit definition for CAN_TSR register  ********************/\n#define CAN_TSR_RQCP0_Pos      (0U)\n#define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */\n#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */\n#define CAN_TSR_TXOK0_Pos      (1U)\n#define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */\n#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */\n#define CAN_TSR_ALST0_Pos      (2U)\n#define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */\n#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */\n#define CAN_TSR_TERR0_Pos      (3U)\n#define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */\n#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */\n#define CAN_TSR_ABRQ0_Pos      (7U)\n#define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */\n#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */\n#define CAN_TSR_RQCP1_Pos      (8U)\n#define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */\n#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */\n#define CAN_TSR_TXOK1_Pos      (9U)\n#define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */\n#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */\n#define CAN_TSR_ALST1_Pos      (10U)\n#define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */\n#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */\n#define CAN_TSR_TERR1_Pos      (11U)\n#define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */\n#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */\n#define CAN_TSR_ABRQ1_Pos      (15U)\n#define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */\n#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */\n#define CAN_TSR_RQCP2_Pos      (16U)\n#define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */\n#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */\n#define CAN_TSR_TXOK2_Pos      (17U)\n#define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */\n#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */\n#define CAN_TSR_ALST2_Pos      (18U)\n#define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */\n#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */\n#define CAN_TSR_TERR2_Pos      (19U)\n#define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */\n#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */\n#define CAN_TSR_ABRQ2_Pos      (23U)\n#define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */\n#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */\n#define CAN_TSR_CODE_Pos       (24U)\n#define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */\n#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */\n\n#define CAN_TSR_TME_Pos        (26U)\n#define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */\n#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */\n#define CAN_TSR_TME0_Pos       (26U)\n#define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */\n#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */\n#define CAN_TSR_TME1_Pos       (27U)\n#define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */\n#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */\n#define CAN_TSR_TME2_Pos       (28U)\n#define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */\n#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */\n\n#define CAN_TSR_LOW_Pos        (29U)\n#define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */\n#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */\n#define CAN_TSR_LOW0_Pos       (29U)\n#define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */\n#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */\n#define CAN_TSR_LOW1_Pos       (30U)\n#define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */\n#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */\n#define CAN_TSR_LOW2_Pos       (31U)\n#define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */\n#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */\n\n/*******************  Bit definition for CAN_RF0R register  *******************/\n#define CAN_RF0R_FMP0_Pos      (0U)\n#define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */\n#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */\n#define CAN_RF0R_FULL0_Pos     (3U)\n#define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */\n#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */\n#define CAN_RF0R_FOVR0_Pos     (4U)\n#define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */\n#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */\n#define CAN_RF0R_RFOM0_Pos     (5U)\n#define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */\n#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */\n\n/*******************  Bit definition for CAN_RF1R register  *******************/\n#define CAN_RF1R_FMP1_Pos      (0U)\n#define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */\n#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */\n#define CAN_RF1R_FULL1_Pos     (3U)\n#define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */\n#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */\n#define CAN_RF1R_FOVR1_Pos     (4U)\n#define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */\n#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */\n#define CAN_RF1R_RFOM1_Pos     (5U)\n#define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */\n#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */\n\n/********************  Bit definition for CAN_IER register  *******************/\n#define CAN_IER_TMEIE_Pos      (0U)\n#define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */\n#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */\n#define CAN_IER_FMPIE0_Pos     (1U)\n#define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */\n#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE0_Pos      (2U)\n#define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */\n#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE0_Pos     (3U)\n#define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */\n#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_FMPIE1_Pos     (4U)\n#define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */\n#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE1_Pos      (5U)\n#define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */\n#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE1_Pos     (6U)\n#define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */\n#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)\n#define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */\n#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */\n#define CAN_IER_EPVIE_Pos      (9U)\n#define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */\n#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */\n#define CAN_IER_BOFIE_Pos      (10U)\n#define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */\n#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */\n#define CAN_IER_LECIE_Pos      (11U)\n#define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */\n#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */\n#define CAN_IER_ERRIE_Pos      (15U)\n#define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */\n#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */\n#define CAN_IER_WKUIE_Pos      (16U)\n#define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */\n#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */\n#define CAN_IER_SLKIE_Pos      (17U)\n#define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */\n#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)\n\n/********************  Bit definition for CAN_ESR register  *******************/\n#define CAN_ESR_EWGF_Pos       (0U)\n#define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */\n#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */\n#define CAN_ESR_EPVF_Pos       (1U)\n#define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */\n#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */\n#define CAN_ESR_BOFF_Pos       (2U)\n#define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */\n#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */\n\n#define CAN_ESR_LEC_Pos        (4U)\n#define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */\n#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */\n#define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */\n#define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */\n#define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */\n\n#define CAN_ESR_TEC_Pos        (16U)\n#define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */\n#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */\n#define CAN_ESR_REC_Pos        (24U)\n#define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */\n#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */\n\n/*******************  Bit definition for CAN_BTR register  ********************/\n#define CAN_BTR_BRP_Pos        (0U)\n#define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */\n#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */\n#define CAN_BTR_TS1_Pos        (16U)\n#define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */\n#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */\n#define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */\n#define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */\n#define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */\n#define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */\n#define CAN_BTR_TS2_Pos        (20U)\n#define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */\n#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */\n#define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */\n#define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */\n#define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */\n#define CAN_BTR_SJW_Pos        (24U)\n#define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */\n#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */\n#define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */\n#define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */\n#define CAN_BTR_LBKM_Pos       (30U)\n#define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */\n#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */\n#define CAN_BTR_SILM_Pos       (31U)\n#define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */\n#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */\n\n\n/*!<Mailbox registers */\n/******************  Bit definition for CAN_TI0R register  ********************/\n#define CAN_TI0R_TXRQ_Pos      (0U)\n#define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI0R_RTR_Pos       (1U)\n#define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI0R_IDE_Pos       (2U)\n#define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI0R_EXID_Pos      (3U)\n#define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI0R_STID_Pos      (21U)\n#define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/******************  Bit definition for CAN_TDT0R register  *******************/\n#define CAN_TDT0R_DLC_Pos      (0U)\n#define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT0R_TGT_Pos      (8U)\n#define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT0R_TIME_Pos     (16U)\n#define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/******************  Bit definition for CAN_TDL0R register  *******************/\n#define CAN_TDL0R_DATA0_Pos    (0U)\n#define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL0R_DATA1_Pos    (8U)\n#define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL0R_DATA2_Pos    (16U)\n#define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL0R_DATA3_Pos    (24U)\n#define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/******************  Bit definition for CAN_TDH0R register  *******************/\n#define CAN_TDH0R_DATA4_Pos    (0U)\n#define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH0R_DATA5_Pos    (8U)\n#define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH0R_DATA6_Pos    (16U)\n#define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH0R_DATA7_Pos    (24U)\n#define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI1R register  *******************/\n#define CAN_TI1R_TXRQ_Pos      (0U)\n#define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI1R_RTR_Pos       (1U)\n#define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI1R_IDE_Pos       (2U)\n#define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI1R_EXID_Pos      (3U)\n#define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI1R_STID_Pos      (21U)\n#define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT1R register  ******************/\n#define CAN_TDT1R_DLC_Pos      (0U)\n#define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT1R_TGT_Pos      (8U)\n#define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT1R_TIME_Pos     (16U)\n#define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL1R register  ******************/\n#define CAN_TDL1R_DATA0_Pos    (0U)\n#define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL1R_DATA1_Pos    (8U)\n#define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL1R_DATA2_Pos    (16U)\n#define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL1R_DATA3_Pos    (24U)\n#define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH1R register  ******************/\n#define CAN_TDH1R_DATA4_Pos    (0U)\n#define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH1R_DATA5_Pos    (8U)\n#define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH1R_DATA6_Pos    (16U)\n#define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH1R_DATA7_Pos    (24U)\n#define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI2R register  *******************/\n#define CAN_TI2R_TXRQ_Pos      (0U)\n#define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI2R_RTR_Pos       (1U)\n#define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI2R_IDE_Pos       (2U)\n#define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI2R_EXID_Pos      (3U)\n#define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_TI2R_STID_Pos      (21U)\n#define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT2R register  ******************/\n#define CAN_TDT2R_DLC_Pos      (0U)\n#define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT2R_TGT_Pos      (8U)\n#define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT2R_TIME_Pos     (16U)\n#define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL2R register  ******************/\n#define CAN_TDL2R_DATA0_Pos    (0U)\n#define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL2R_DATA1_Pos    (8U)\n#define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL2R_DATA2_Pos    (16U)\n#define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL2R_DATA3_Pos    (24U)\n#define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH2R register  ******************/\n#define CAN_TDH2R_DATA4_Pos    (0U)\n#define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH2R_DATA5_Pos    (8U)\n#define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH2R_DATA6_Pos    (16U)\n#define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH2R_DATA7_Pos    (24U)\n#define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI0R register  *******************/\n#define CAN_RI0R_RTR_Pos       (1U)\n#define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI0R_IDE_Pos       (2U)\n#define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI0R_EXID_Pos      (3U)\n#define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_RI0R_STID_Pos      (21U)\n#define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT0R register  ******************/\n#define CAN_RDT0R_DLC_Pos      (0U)\n#define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT0R_FMI_Pos      (8U)\n#define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT0R_TIME_Pos     (16U)\n#define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL0R register  ******************/\n#define CAN_RDL0R_DATA0_Pos    (0U)\n#define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL0R_DATA1_Pos    (8U)\n#define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL0R_DATA2_Pos    (16U)\n#define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL0R_DATA3_Pos    (24U)\n#define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH0R register  ******************/\n#define CAN_RDH0R_DATA4_Pos    (0U)\n#define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH0R_DATA5_Pos    (8U)\n#define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH0R_DATA6_Pos    (16U)\n#define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH0R_DATA7_Pos    (24U)\n#define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI1R register  *******************/\n#define CAN_RI1R_RTR_Pos       (1U)\n#define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI1R_IDE_Pos       (2U)\n#define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI1R_EXID_Pos      (3U)\n#define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_RI1R_STID_Pos      (21U)\n#define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT1R register  ******************/\n#define CAN_RDT1R_DLC_Pos      (0U)\n#define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT1R_FMI_Pos      (8U)\n#define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT1R_TIME_Pos     (16U)\n#define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL1R register  ******************/\n#define CAN_RDL1R_DATA0_Pos    (0U)\n#define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL1R_DATA1_Pos    (8U)\n#define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL1R_DATA2_Pos    (16U)\n#define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL1R_DATA3_Pos    (24U)\n#define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH1R register  ******************/\n#define CAN_RDH1R_DATA4_Pos    (0U)\n#define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH1R_DATA5_Pos    (8U)\n#define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH1R_DATA6_Pos    (16U)\n#define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH1R_DATA7_Pos    (24U)\n#define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*!<CAN filter registers */\n/*******************  Bit definition for CAN_FMR register  ********************/\n#define CAN_FMR_FINIT_Pos      (0U)\n#define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */\n#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */\n#define CAN_FMR_CAN2SB_Pos     (8U)\n#define CAN_FMR_CAN2SB_Msk     (0x3FUL << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */\n#define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */\n\n/*******************  Bit definition for CAN_FM1R register  *******************/\n#define CAN_FM1R_FBM_Pos       (0U)\n#define CAN_FM1R_FBM_Msk       (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */\n#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */\n#define CAN_FM1R_FBM0_Pos      (0U)\n#define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */\n#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */\n#define CAN_FM1R_FBM1_Pos      (1U)\n#define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */\n#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */\n#define CAN_FM1R_FBM2_Pos      (2U)\n#define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */\n#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */\n#define CAN_FM1R_FBM3_Pos      (3U)\n#define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */\n#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */\n#define CAN_FM1R_FBM4_Pos      (4U)\n#define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */\n#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */\n#define CAN_FM1R_FBM5_Pos      (5U)\n#define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */\n#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */\n#define CAN_FM1R_FBM6_Pos      (6U)\n#define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */\n#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */\n#define CAN_FM1R_FBM7_Pos      (7U)\n#define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */\n#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */\n#define CAN_FM1R_FBM8_Pos      (8U)\n#define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */\n#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */\n#define CAN_FM1R_FBM9_Pos      (9U)\n#define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */\n#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */\n#define CAN_FM1R_FBM10_Pos     (10U)\n#define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */\n#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */\n#define CAN_FM1R_FBM11_Pos     (11U)\n#define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */\n#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */\n#define CAN_FM1R_FBM12_Pos     (12U)\n#define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */\n#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */\n#define CAN_FM1R_FBM13_Pos     (13U)\n#define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */\n#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */\n#define CAN_FM1R_FBM14_Pos     (14U)\n#define CAN_FM1R_FBM14_Msk     (0x1UL << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */\n#define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */\n#define CAN_FM1R_FBM15_Pos     (15U)\n#define CAN_FM1R_FBM15_Msk     (0x1UL << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */\n#define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */\n#define CAN_FM1R_FBM16_Pos     (16U)\n#define CAN_FM1R_FBM16_Msk     (0x1UL << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */\n#define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */\n#define CAN_FM1R_FBM17_Pos     (17U)\n#define CAN_FM1R_FBM17_Msk     (0x1UL << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */\n#define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */\n#define CAN_FM1R_FBM18_Pos     (18U)\n#define CAN_FM1R_FBM18_Msk     (0x1UL << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */\n#define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */\n#define CAN_FM1R_FBM19_Pos     (19U)\n#define CAN_FM1R_FBM19_Msk     (0x1UL << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */\n#define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */\n#define CAN_FM1R_FBM20_Pos     (20U)\n#define CAN_FM1R_FBM20_Msk     (0x1UL << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */\n#define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */\n#define CAN_FM1R_FBM21_Pos     (21U)\n#define CAN_FM1R_FBM21_Msk     (0x1UL << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */\n#define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */\n#define CAN_FM1R_FBM22_Pos     (22U)\n#define CAN_FM1R_FBM22_Msk     (0x1UL << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */\n#define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */\n#define CAN_FM1R_FBM23_Pos     (23U)\n#define CAN_FM1R_FBM23_Msk     (0x1UL << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */\n#define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */\n#define CAN_FM1R_FBM24_Pos     (24U)\n#define CAN_FM1R_FBM24_Msk     (0x1UL << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */\n#define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */\n#define CAN_FM1R_FBM25_Pos     (25U)\n#define CAN_FM1R_FBM25_Msk     (0x1UL << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */\n#define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */\n#define CAN_FM1R_FBM26_Pos     (26U)\n#define CAN_FM1R_FBM26_Msk     (0x1UL << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */\n#define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */\n#define CAN_FM1R_FBM27_Pos     (27U)\n#define CAN_FM1R_FBM27_Msk     (0x1UL << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */\n#define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */\n\n/*******************  Bit definition for CAN_FS1R register  *******************/\n#define CAN_FS1R_FSC_Pos       (0U)\n#define CAN_FS1R_FSC_Msk       (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */\n#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */\n#define CAN_FS1R_FSC0_Pos      (0U)\n#define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */\n#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */\n#define CAN_FS1R_FSC1_Pos      (1U)\n#define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */\n#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */\n#define CAN_FS1R_FSC2_Pos      (2U)\n#define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */\n#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */\n#define CAN_FS1R_FSC3_Pos      (3U)\n#define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */\n#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */\n#define CAN_FS1R_FSC4_Pos      (4U)\n#define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */\n#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */\n#define CAN_FS1R_FSC5_Pos      (5U)\n#define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */\n#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */\n#define CAN_FS1R_FSC6_Pos      (6U)\n#define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */\n#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */\n#define CAN_FS1R_FSC7_Pos      (7U)\n#define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */\n#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */\n#define CAN_FS1R_FSC8_Pos      (8U)\n#define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */\n#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */\n#define CAN_FS1R_FSC9_Pos      (9U)\n#define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */\n#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */\n#define CAN_FS1R_FSC10_Pos     (10U)\n#define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */\n#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */\n#define CAN_FS1R_FSC11_Pos     (11U)\n#define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */\n#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */\n#define CAN_FS1R_FSC12_Pos     (12U)\n#define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */\n#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */\n#define CAN_FS1R_FSC13_Pos     (13U)\n#define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */\n#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */\n#define CAN_FS1R_FSC14_Pos     (14U)\n#define CAN_FS1R_FSC14_Msk     (0x1UL << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */\n#define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */\n#define CAN_FS1R_FSC15_Pos     (15U)\n#define CAN_FS1R_FSC15_Msk     (0x1UL << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */\n#define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */\n#define CAN_FS1R_FSC16_Pos     (16U)\n#define CAN_FS1R_FSC16_Msk     (0x1UL << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */\n#define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */\n#define CAN_FS1R_FSC17_Pos     (17U)\n#define CAN_FS1R_FSC17_Msk     (0x1UL << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */\n#define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */\n#define CAN_FS1R_FSC18_Pos     (18U)\n#define CAN_FS1R_FSC18_Msk     (0x1UL << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */\n#define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */\n#define CAN_FS1R_FSC19_Pos     (19U)\n#define CAN_FS1R_FSC19_Msk     (0x1UL << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */\n#define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */\n#define CAN_FS1R_FSC20_Pos     (20U)\n#define CAN_FS1R_FSC20_Msk     (0x1UL << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */\n#define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */\n#define CAN_FS1R_FSC21_Pos     (21U)\n#define CAN_FS1R_FSC21_Msk     (0x1UL << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */\n#define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */\n#define CAN_FS1R_FSC22_Pos     (22U)\n#define CAN_FS1R_FSC22_Msk     (0x1UL << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */\n#define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */\n#define CAN_FS1R_FSC23_Pos     (23U)\n#define CAN_FS1R_FSC23_Msk     (0x1UL << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */\n#define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */\n#define CAN_FS1R_FSC24_Pos     (24U)\n#define CAN_FS1R_FSC24_Msk     (0x1UL << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */\n#define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */\n#define CAN_FS1R_FSC25_Pos     (25U)\n#define CAN_FS1R_FSC25_Msk     (0x1UL << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */\n#define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */\n#define CAN_FS1R_FSC26_Pos     (26U)\n#define CAN_FS1R_FSC26_Msk     (0x1UL << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */\n#define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */\n#define CAN_FS1R_FSC27_Pos     (27U)\n#define CAN_FS1R_FSC27_Msk     (0x1UL << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */\n#define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */\n\n/******************  Bit definition for CAN_FFA1R register  *******************/\n#define CAN_FFA1R_FFA_Pos      (0U)\n#define CAN_FFA1R_FFA_Msk      (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */\n#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */\n#define CAN_FFA1R_FFA0_Pos     (0U)\n#define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */\n#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */\n#define CAN_FFA1R_FFA1_Pos     (1U)\n#define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */\n#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */\n#define CAN_FFA1R_FFA2_Pos     (2U)\n#define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */\n#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */\n#define CAN_FFA1R_FFA3_Pos     (3U)\n#define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */\n#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */\n#define CAN_FFA1R_FFA4_Pos     (4U)\n#define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */\n#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */\n#define CAN_FFA1R_FFA5_Pos     (5U)\n#define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */\n#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */\n#define CAN_FFA1R_FFA6_Pos     (6U)\n#define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */\n#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */\n#define CAN_FFA1R_FFA7_Pos     (7U)\n#define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */\n#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */\n#define CAN_FFA1R_FFA8_Pos     (8U)\n#define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */\n#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */\n#define CAN_FFA1R_FFA9_Pos     (9U)\n#define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */\n#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */\n#define CAN_FFA1R_FFA10_Pos    (10U)\n#define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */\n#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */\n#define CAN_FFA1R_FFA11_Pos    (11U)\n#define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */\n#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */\n#define CAN_FFA1R_FFA12_Pos    (12U)\n#define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */\n#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */\n#define CAN_FFA1R_FFA13_Pos    (13U)\n#define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */\n#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */\n#define CAN_FFA1R_FFA14_Pos    (14U)\n#define CAN_FFA1R_FFA14_Msk    (0x1UL << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */\n#define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */\n#define CAN_FFA1R_FFA15_Pos    (15U)\n#define CAN_FFA1R_FFA15_Msk    (0x1UL << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */\n#define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */\n#define CAN_FFA1R_FFA16_Pos    (16U)\n#define CAN_FFA1R_FFA16_Msk    (0x1UL << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */\n#define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */\n#define CAN_FFA1R_FFA17_Pos    (17U)\n#define CAN_FFA1R_FFA17_Msk    (0x1UL << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */\n#define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */\n#define CAN_FFA1R_FFA18_Pos    (18U)\n#define CAN_FFA1R_FFA18_Msk    (0x1UL << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */\n#define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */\n#define CAN_FFA1R_FFA19_Pos    (19U)\n#define CAN_FFA1R_FFA19_Msk    (0x1UL << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */\n#define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */\n#define CAN_FFA1R_FFA20_Pos    (20U)\n#define CAN_FFA1R_FFA20_Msk    (0x1UL << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */\n#define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */\n#define CAN_FFA1R_FFA21_Pos    (21U)\n#define CAN_FFA1R_FFA21_Msk    (0x1UL << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */\n#define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */\n#define CAN_FFA1R_FFA22_Pos    (22U)\n#define CAN_FFA1R_FFA22_Msk    (0x1UL << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */\n#define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */\n#define CAN_FFA1R_FFA23_Pos    (23U)\n#define CAN_FFA1R_FFA23_Msk    (0x1UL << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */\n#define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */\n#define CAN_FFA1R_FFA24_Pos    (24U)\n#define CAN_FFA1R_FFA24_Msk    (0x1UL << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */\n#define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */\n#define CAN_FFA1R_FFA25_Pos    (25U)\n#define CAN_FFA1R_FFA25_Msk    (0x1UL << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */\n#define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */\n#define CAN_FFA1R_FFA26_Pos    (26U)\n#define CAN_FFA1R_FFA26_Msk    (0x1UL << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */\n#define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */\n#define CAN_FFA1R_FFA27_Pos    (27U)\n#define CAN_FFA1R_FFA27_Msk    (0x1UL << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */\n#define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */\n\n/*******************  Bit definition for CAN_FA1R register  *******************/\n#define CAN_FA1R_FACT_Pos      (0U)\n#define CAN_FA1R_FACT_Msk      (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */\n#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */\n#define CAN_FA1R_FACT0_Pos     (0U)\n#define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */\n#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */\n#define CAN_FA1R_FACT1_Pos     (1U)\n#define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */\n#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */\n#define CAN_FA1R_FACT2_Pos     (2U)\n#define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */\n#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */\n#define CAN_FA1R_FACT3_Pos     (3U)\n#define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */\n#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */\n#define CAN_FA1R_FACT4_Pos     (4U)\n#define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */\n#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */\n#define CAN_FA1R_FACT5_Pos     (5U)\n#define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */\n#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */\n#define CAN_FA1R_FACT6_Pos     (6U)\n#define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */\n#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */\n#define CAN_FA1R_FACT7_Pos     (7U)\n#define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */\n#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */\n#define CAN_FA1R_FACT8_Pos     (8U)\n#define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */\n#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */\n#define CAN_FA1R_FACT9_Pos     (9U)\n#define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */\n#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */\n#define CAN_FA1R_FACT10_Pos    (10U)\n#define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */\n#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */\n#define CAN_FA1R_FACT11_Pos    (11U)\n#define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */\n#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */\n#define CAN_FA1R_FACT12_Pos    (12U)\n#define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */\n#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */\n#define CAN_FA1R_FACT13_Pos    (13U)\n#define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */\n#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */\n#define CAN_FA1R_FACT14_Pos    (14U)\n#define CAN_FA1R_FACT14_Msk    (0x1UL << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */\n#define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */\n#define CAN_FA1R_FACT15_Pos    (15U)\n#define CAN_FA1R_FACT15_Msk    (0x1UL << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */\n#define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */\n#define CAN_FA1R_FACT16_Pos    (16U)\n#define CAN_FA1R_FACT16_Msk    (0x1UL << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */\n#define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */\n#define CAN_FA1R_FACT17_Pos    (17U)\n#define CAN_FA1R_FACT17_Msk    (0x1UL << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */\n#define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */\n#define CAN_FA1R_FACT18_Pos    (18U)\n#define CAN_FA1R_FACT18_Msk    (0x1UL << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */\n#define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */\n#define CAN_FA1R_FACT19_Pos    (19U)\n#define CAN_FA1R_FACT19_Msk    (0x1UL << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */\n#define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */\n#define CAN_FA1R_FACT20_Pos    (20U)\n#define CAN_FA1R_FACT20_Msk    (0x1UL << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */\n#define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */\n#define CAN_FA1R_FACT21_Pos    (21U)\n#define CAN_FA1R_FACT21_Msk    (0x1UL << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */\n#define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */\n#define CAN_FA1R_FACT22_Pos    (22U)\n#define CAN_FA1R_FACT22_Msk    (0x1UL << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */\n#define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */\n#define CAN_FA1R_FACT23_Pos    (23U)\n#define CAN_FA1R_FACT23_Msk    (0x1UL << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */\n#define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */\n#define CAN_FA1R_FACT24_Pos    (24U)\n#define CAN_FA1R_FACT24_Msk    (0x1UL << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */\n#define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */\n#define CAN_FA1R_FACT25_Pos    (25U)\n#define CAN_FA1R_FACT25_Msk    (0x1UL << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */\n#define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */\n#define CAN_FA1R_FACT26_Pos    (26U)\n#define CAN_FA1R_FACT26_Msk    (0x1UL << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */\n#define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */\n#define CAN_FA1R_FACT27_Pos    (27U)\n#define CAN_FA1R_FACT27_Msk    (0x1UL << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */\n#define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */\n\n\n/*******************  Bit definition for CAN_F0R1 register  *******************/\n#define CAN_F0R1_FB0_Pos       (0U)\n#define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R1_FB1_Pos       (1U)\n#define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R1_FB2_Pos       (2U)\n#define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R1_FB3_Pos       (3U)\n#define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R1_FB4_Pos       (4U)\n#define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R1_FB5_Pos       (5U)\n#define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R1_FB6_Pos       (6U)\n#define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R1_FB7_Pos       (7U)\n#define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R1_FB8_Pos       (8U)\n#define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R1_FB9_Pos       (9U)\n#define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R1_FB10_Pos      (10U)\n#define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R1_FB11_Pos      (11U)\n#define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R1_FB12_Pos      (12U)\n#define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R1_FB13_Pos      (13U)\n#define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R1_FB14_Pos      (14U)\n#define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R1_FB15_Pos      (15U)\n#define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R1_FB16_Pos      (16U)\n#define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R1_FB17_Pos      (17U)\n#define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R1_FB18_Pos      (18U)\n#define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R1_FB19_Pos      (19U)\n#define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R1_FB20_Pos      (20U)\n#define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R1_FB21_Pos      (21U)\n#define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R1_FB22_Pos      (22U)\n#define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R1_FB23_Pos      (23U)\n#define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R1_FB24_Pos      (24U)\n#define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R1_FB25_Pos      (25U)\n#define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R1_FB26_Pos      (26U)\n#define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R1_FB27_Pos      (27U)\n#define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R1_FB28_Pos      (28U)\n#define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R1_FB29_Pos      (29U)\n#define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R1_FB30_Pos      (30U)\n#define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R1_FB31_Pos      (31U)\n#define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R1 register  *******************/\n#define CAN_F1R1_FB0_Pos       (0U)\n#define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R1_FB1_Pos       (1U)\n#define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R1_FB2_Pos       (2U)\n#define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R1_FB3_Pos       (3U)\n#define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R1_FB4_Pos       (4U)\n#define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R1_FB5_Pos       (5U)\n#define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R1_FB6_Pos       (6U)\n#define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R1_FB7_Pos       (7U)\n#define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R1_FB8_Pos       (8U)\n#define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R1_FB9_Pos       (9U)\n#define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R1_FB10_Pos      (10U)\n#define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R1_FB11_Pos      (11U)\n#define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R1_FB12_Pos      (12U)\n#define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R1_FB13_Pos      (13U)\n#define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R1_FB14_Pos      (14U)\n#define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R1_FB15_Pos      (15U)\n#define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R1_FB16_Pos      (16U)\n#define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R1_FB17_Pos      (17U)\n#define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R1_FB18_Pos      (18U)\n#define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R1_FB19_Pos      (19U)\n#define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R1_FB20_Pos      (20U)\n#define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R1_FB21_Pos      (21U)\n#define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R1_FB22_Pos      (22U)\n#define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R1_FB23_Pos      (23U)\n#define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R1_FB24_Pos      (24U)\n#define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R1_FB25_Pos      (25U)\n#define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R1_FB26_Pos      (26U)\n#define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R1_FB27_Pos      (27U)\n#define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R1_FB28_Pos      (28U)\n#define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R1_FB29_Pos      (29U)\n#define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R1_FB30_Pos      (30U)\n#define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R1_FB31_Pos      (31U)\n#define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R1 register  *******************/\n#define CAN_F2R1_FB0_Pos       (0U)\n#define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R1_FB1_Pos       (1U)\n#define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R1_FB2_Pos       (2U)\n#define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R1_FB3_Pos       (3U)\n#define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R1_FB4_Pos       (4U)\n#define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R1_FB5_Pos       (5U)\n#define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R1_FB6_Pos       (6U)\n#define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R1_FB7_Pos       (7U)\n#define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R1_FB8_Pos       (8U)\n#define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R1_FB9_Pos       (9U)\n#define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R1_FB10_Pos      (10U)\n#define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R1_FB11_Pos      (11U)\n#define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R1_FB12_Pos      (12U)\n#define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R1_FB13_Pos      (13U)\n#define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R1_FB14_Pos      (14U)\n#define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R1_FB15_Pos      (15U)\n#define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R1_FB16_Pos      (16U)\n#define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R1_FB17_Pos      (17U)\n#define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R1_FB18_Pos      (18U)\n#define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R1_FB19_Pos      (19U)\n#define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R1_FB20_Pos      (20U)\n#define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R1_FB21_Pos      (21U)\n#define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R1_FB22_Pos      (22U)\n#define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R1_FB23_Pos      (23U)\n#define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R1_FB24_Pos      (24U)\n#define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R1_FB25_Pos      (25U)\n#define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R1_FB26_Pos      (26U)\n#define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R1_FB27_Pos      (27U)\n#define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R1_FB28_Pos      (28U)\n#define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R1_FB29_Pos      (29U)\n#define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R1_FB30_Pos      (30U)\n#define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R1_FB31_Pos      (31U)\n#define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R1 register  *******************/\n#define CAN_F3R1_FB0_Pos       (0U)\n#define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R1_FB1_Pos       (1U)\n#define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R1_FB2_Pos       (2U)\n#define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R1_FB3_Pos       (3U)\n#define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R1_FB4_Pos       (4U)\n#define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R1_FB5_Pos       (5U)\n#define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R1_FB6_Pos       (6U)\n#define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R1_FB7_Pos       (7U)\n#define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R1_FB8_Pos       (8U)\n#define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R1_FB9_Pos       (9U)\n#define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R1_FB10_Pos      (10U)\n#define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R1_FB11_Pos      (11U)\n#define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R1_FB12_Pos      (12U)\n#define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R1_FB13_Pos      (13U)\n#define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R1_FB14_Pos      (14U)\n#define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R1_FB15_Pos      (15U)\n#define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R1_FB16_Pos      (16U)\n#define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R1_FB17_Pos      (17U)\n#define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R1_FB18_Pos      (18U)\n#define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R1_FB19_Pos      (19U)\n#define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R1_FB20_Pos      (20U)\n#define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R1_FB21_Pos      (21U)\n#define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R1_FB22_Pos      (22U)\n#define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R1_FB23_Pos      (23U)\n#define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R1_FB24_Pos      (24U)\n#define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R1_FB25_Pos      (25U)\n#define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R1_FB26_Pos      (26U)\n#define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R1_FB27_Pos      (27U)\n#define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R1_FB28_Pos      (28U)\n#define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R1_FB29_Pos      (29U)\n#define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R1_FB30_Pos      (30U)\n#define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R1_FB31_Pos      (31U)\n#define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R1 register  *******************/\n#define CAN_F4R1_FB0_Pos       (0U)\n#define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R1_FB1_Pos       (1U)\n#define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R1_FB2_Pos       (2U)\n#define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R1_FB3_Pos       (3U)\n#define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R1_FB4_Pos       (4U)\n#define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R1_FB5_Pos       (5U)\n#define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R1_FB6_Pos       (6U)\n#define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R1_FB7_Pos       (7U)\n#define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R1_FB8_Pos       (8U)\n#define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R1_FB9_Pos       (9U)\n#define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R1_FB10_Pos      (10U)\n#define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R1_FB11_Pos      (11U)\n#define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R1_FB12_Pos      (12U)\n#define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R1_FB13_Pos      (13U)\n#define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R1_FB14_Pos      (14U)\n#define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R1_FB15_Pos      (15U)\n#define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R1_FB16_Pos      (16U)\n#define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R1_FB17_Pos      (17U)\n#define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R1_FB18_Pos      (18U)\n#define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R1_FB19_Pos      (19U)\n#define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R1_FB20_Pos      (20U)\n#define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R1_FB21_Pos      (21U)\n#define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R1_FB22_Pos      (22U)\n#define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R1_FB23_Pos      (23U)\n#define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R1_FB24_Pos      (24U)\n#define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R1_FB25_Pos      (25U)\n#define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R1_FB26_Pos      (26U)\n#define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R1_FB27_Pos      (27U)\n#define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R1_FB28_Pos      (28U)\n#define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R1_FB29_Pos      (29U)\n#define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R1_FB30_Pos      (30U)\n#define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R1_FB31_Pos      (31U)\n#define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R1 register  *******************/\n#define CAN_F5R1_FB0_Pos       (0U)\n#define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R1_FB1_Pos       (1U)\n#define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R1_FB2_Pos       (2U)\n#define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R1_FB3_Pos       (3U)\n#define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R1_FB4_Pos       (4U)\n#define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R1_FB5_Pos       (5U)\n#define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R1_FB6_Pos       (6U)\n#define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R1_FB7_Pos       (7U)\n#define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R1_FB8_Pos       (8U)\n#define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R1_FB9_Pos       (9U)\n#define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R1_FB10_Pos      (10U)\n#define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R1_FB11_Pos      (11U)\n#define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R1_FB12_Pos      (12U)\n#define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R1_FB13_Pos      (13U)\n#define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R1_FB14_Pos      (14U)\n#define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R1_FB15_Pos      (15U)\n#define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R1_FB16_Pos      (16U)\n#define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R1_FB17_Pos      (17U)\n#define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R1_FB18_Pos      (18U)\n#define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R1_FB19_Pos      (19U)\n#define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R1_FB20_Pos      (20U)\n#define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R1_FB21_Pos      (21U)\n#define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R1_FB22_Pos      (22U)\n#define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R1_FB23_Pos      (23U)\n#define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R1_FB24_Pos      (24U)\n#define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R1_FB25_Pos      (25U)\n#define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R1_FB26_Pos      (26U)\n#define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R1_FB27_Pos      (27U)\n#define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R1_FB28_Pos      (28U)\n#define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R1_FB29_Pos      (29U)\n#define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R1_FB30_Pos      (30U)\n#define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R1_FB31_Pos      (31U)\n#define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R1 register  *******************/\n#define CAN_F6R1_FB0_Pos       (0U)\n#define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R1_FB1_Pos       (1U)\n#define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R1_FB2_Pos       (2U)\n#define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R1_FB3_Pos       (3U)\n#define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R1_FB4_Pos       (4U)\n#define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R1_FB5_Pos       (5U)\n#define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R1_FB6_Pos       (6U)\n#define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R1_FB7_Pos       (7U)\n#define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R1_FB8_Pos       (8U)\n#define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R1_FB9_Pos       (9U)\n#define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R1_FB10_Pos      (10U)\n#define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R1_FB11_Pos      (11U)\n#define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R1_FB12_Pos      (12U)\n#define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R1_FB13_Pos      (13U)\n#define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R1_FB14_Pos      (14U)\n#define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R1_FB15_Pos      (15U)\n#define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R1_FB16_Pos      (16U)\n#define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R1_FB17_Pos      (17U)\n#define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R1_FB18_Pos      (18U)\n#define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R1_FB19_Pos      (19U)\n#define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R1_FB20_Pos      (20U)\n#define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R1_FB21_Pos      (21U)\n#define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R1_FB22_Pos      (22U)\n#define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R1_FB23_Pos      (23U)\n#define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R1_FB24_Pos      (24U)\n#define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R1_FB25_Pos      (25U)\n#define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R1_FB26_Pos      (26U)\n#define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R1_FB27_Pos      (27U)\n#define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R1_FB28_Pos      (28U)\n#define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R1_FB29_Pos      (29U)\n#define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R1_FB30_Pos      (30U)\n#define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R1_FB31_Pos      (31U)\n#define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R1 register  *******************/\n#define CAN_F7R1_FB0_Pos       (0U)\n#define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R1_FB1_Pos       (1U)\n#define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R1_FB2_Pos       (2U)\n#define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R1_FB3_Pos       (3U)\n#define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R1_FB4_Pos       (4U)\n#define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R1_FB5_Pos       (5U)\n#define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R1_FB6_Pos       (6U)\n#define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R1_FB7_Pos       (7U)\n#define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R1_FB8_Pos       (8U)\n#define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R1_FB9_Pos       (9U)\n#define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R1_FB10_Pos      (10U)\n#define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R1_FB11_Pos      (11U)\n#define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R1_FB12_Pos      (12U)\n#define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R1_FB13_Pos      (13U)\n#define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R1_FB14_Pos      (14U)\n#define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R1_FB15_Pos      (15U)\n#define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R1_FB16_Pos      (16U)\n#define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R1_FB17_Pos      (17U)\n#define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R1_FB18_Pos      (18U)\n#define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R1_FB19_Pos      (19U)\n#define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R1_FB20_Pos      (20U)\n#define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R1_FB21_Pos      (21U)\n#define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R1_FB22_Pos      (22U)\n#define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R1_FB23_Pos      (23U)\n#define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R1_FB24_Pos      (24U)\n#define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R1_FB25_Pos      (25U)\n#define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R1_FB26_Pos      (26U)\n#define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R1_FB27_Pos      (27U)\n#define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R1_FB28_Pos      (28U)\n#define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R1_FB29_Pos      (29U)\n#define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R1_FB30_Pos      (30U)\n#define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R1_FB31_Pos      (31U)\n#define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R1 register  *******************/\n#define CAN_F8R1_FB0_Pos       (0U)\n#define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R1_FB1_Pos       (1U)\n#define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R1_FB2_Pos       (2U)\n#define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R1_FB3_Pos       (3U)\n#define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R1_FB4_Pos       (4U)\n#define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R1_FB5_Pos       (5U)\n#define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R1_FB6_Pos       (6U)\n#define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R1_FB7_Pos       (7U)\n#define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R1_FB8_Pos       (8U)\n#define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R1_FB9_Pos       (9U)\n#define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R1_FB10_Pos      (10U)\n#define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R1_FB11_Pos      (11U)\n#define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R1_FB12_Pos      (12U)\n#define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R1_FB13_Pos      (13U)\n#define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R1_FB14_Pos      (14U)\n#define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R1_FB15_Pos      (15U)\n#define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R1_FB16_Pos      (16U)\n#define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R1_FB17_Pos      (17U)\n#define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R1_FB18_Pos      (18U)\n#define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R1_FB19_Pos      (19U)\n#define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R1_FB20_Pos      (20U)\n#define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R1_FB21_Pos      (21U)\n#define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R1_FB22_Pos      (22U)\n#define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R1_FB23_Pos      (23U)\n#define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R1_FB24_Pos      (24U)\n#define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R1_FB25_Pos      (25U)\n#define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R1_FB26_Pos      (26U)\n#define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R1_FB27_Pos      (27U)\n#define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R1_FB28_Pos      (28U)\n#define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R1_FB29_Pos      (29U)\n#define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R1_FB30_Pos      (30U)\n#define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R1_FB31_Pos      (31U)\n#define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R1 register  *******************/\n#define CAN_F9R1_FB0_Pos       (0U)\n#define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R1_FB1_Pos       (1U)\n#define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R1_FB2_Pos       (2U)\n#define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R1_FB3_Pos       (3U)\n#define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R1_FB4_Pos       (4U)\n#define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R1_FB5_Pos       (5U)\n#define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R1_FB6_Pos       (6U)\n#define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R1_FB7_Pos       (7U)\n#define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R1_FB8_Pos       (8U)\n#define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R1_FB9_Pos       (9U)\n#define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R1_FB10_Pos      (10U)\n#define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R1_FB11_Pos      (11U)\n#define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R1_FB12_Pos      (12U)\n#define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R1_FB13_Pos      (13U)\n#define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R1_FB14_Pos      (14U)\n#define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R1_FB15_Pos      (15U)\n#define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R1_FB16_Pos      (16U)\n#define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R1_FB17_Pos      (17U)\n#define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R1_FB18_Pos      (18U)\n#define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R1_FB19_Pos      (19U)\n#define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R1_FB20_Pos      (20U)\n#define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R1_FB21_Pos      (21U)\n#define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R1_FB22_Pos      (22U)\n#define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R1_FB23_Pos      (23U)\n#define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R1_FB24_Pos      (24U)\n#define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R1_FB25_Pos      (25U)\n#define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R1_FB26_Pos      (26U)\n#define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R1_FB27_Pos      (27U)\n#define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R1_FB28_Pos      (28U)\n#define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R1_FB29_Pos      (29U)\n#define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R1_FB30_Pos      (30U)\n#define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R1_FB31_Pos      (31U)\n#define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R1 register  ******************/\n#define CAN_F10R1_FB0_Pos      (0U)\n#define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R1_FB1_Pos      (1U)\n#define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R1_FB2_Pos      (2U)\n#define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R1_FB3_Pos      (3U)\n#define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R1_FB4_Pos      (4U)\n#define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R1_FB5_Pos      (5U)\n#define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R1_FB6_Pos      (6U)\n#define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R1_FB7_Pos      (7U)\n#define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R1_FB8_Pos      (8U)\n#define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R1_FB9_Pos      (9U)\n#define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R1_FB10_Pos     (10U)\n#define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R1_FB11_Pos     (11U)\n#define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R1_FB12_Pos     (12U)\n#define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R1_FB13_Pos     (13U)\n#define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R1_FB14_Pos     (14U)\n#define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R1_FB15_Pos     (15U)\n#define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R1_FB16_Pos     (16U)\n#define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R1_FB17_Pos     (17U)\n#define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R1_FB18_Pos     (18U)\n#define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R1_FB19_Pos     (19U)\n#define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R1_FB20_Pos     (20U)\n#define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R1_FB21_Pos     (21U)\n#define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R1_FB22_Pos     (22U)\n#define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R1_FB23_Pos     (23U)\n#define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R1_FB24_Pos     (24U)\n#define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R1_FB25_Pos     (25U)\n#define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R1_FB26_Pos     (26U)\n#define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R1_FB27_Pos     (27U)\n#define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R1_FB28_Pos     (28U)\n#define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R1_FB29_Pos     (29U)\n#define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R1_FB30_Pos     (30U)\n#define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R1_FB31_Pos     (31U)\n#define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R1 register  ******************/\n#define CAN_F11R1_FB0_Pos      (0U)\n#define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R1_FB1_Pos      (1U)\n#define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R1_FB2_Pos      (2U)\n#define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R1_FB3_Pos      (3U)\n#define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R1_FB4_Pos      (4U)\n#define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R1_FB5_Pos      (5U)\n#define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R1_FB6_Pos      (6U)\n#define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R1_FB7_Pos      (7U)\n#define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R1_FB8_Pos      (8U)\n#define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R1_FB9_Pos      (9U)\n#define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R1_FB10_Pos     (10U)\n#define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R1_FB11_Pos     (11U)\n#define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R1_FB12_Pos     (12U)\n#define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R1_FB13_Pos     (13U)\n#define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R1_FB14_Pos     (14U)\n#define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R1_FB15_Pos     (15U)\n#define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R1_FB16_Pos     (16U)\n#define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R1_FB17_Pos     (17U)\n#define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R1_FB18_Pos     (18U)\n#define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R1_FB19_Pos     (19U)\n#define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R1_FB20_Pos     (20U)\n#define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R1_FB21_Pos     (21U)\n#define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R1_FB22_Pos     (22U)\n#define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R1_FB23_Pos     (23U)\n#define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R1_FB24_Pos     (24U)\n#define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R1_FB25_Pos     (25U)\n#define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R1_FB26_Pos     (26U)\n#define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R1_FB27_Pos     (27U)\n#define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R1_FB28_Pos     (28U)\n#define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R1_FB29_Pos     (29U)\n#define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R1_FB30_Pos     (30U)\n#define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R1_FB31_Pos     (31U)\n#define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R1 register  ******************/\n#define CAN_F12R1_FB0_Pos      (0U)\n#define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R1_FB1_Pos      (1U)\n#define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R1_FB2_Pos      (2U)\n#define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R1_FB3_Pos      (3U)\n#define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R1_FB4_Pos      (4U)\n#define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R1_FB5_Pos      (5U)\n#define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R1_FB6_Pos      (6U)\n#define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R1_FB7_Pos      (7U)\n#define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R1_FB8_Pos      (8U)\n#define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R1_FB9_Pos      (9U)\n#define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R1_FB10_Pos     (10U)\n#define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R1_FB11_Pos     (11U)\n#define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R1_FB12_Pos     (12U)\n#define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R1_FB13_Pos     (13U)\n#define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R1_FB14_Pos     (14U)\n#define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R1_FB15_Pos     (15U)\n#define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R1_FB16_Pos     (16U)\n#define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R1_FB17_Pos     (17U)\n#define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R1_FB18_Pos     (18U)\n#define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R1_FB19_Pos     (19U)\n#define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R1_FB20_Pos     (20U)\n#define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R1_FB21_Pos     (21U)\n#define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R1_FB22_Pos     (22U)\n#define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R1_FB23_Pos     (23U)\n#define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R1_FB24_Pos     (24U)\n#define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R1_FB25_Pos     (25U)\n#define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R1_FB26_Pos     (26U)\n#define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R1_FB27_Pos     (27U)\n#define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R1_FB28_Pos     (28U)\n#define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R1_FB29_Pos     (29U)\n#define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R1_FB30_Pos     (30U)\n#define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R1_FB31_Pos     (31U)\n#define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R1 register  ******************/\n#define CAN_F13R1_FB0_Pos      (0U)\n#define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R1_FB1_Pos      (1U)\n#define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R1_FB2_Pos      (2U)\n#define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R1_FB3_Pos      (3U)\n#define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R1_FB4_Pos      (4U)\n#define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R1_FB5_Pos      (5U)\n#define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R1_FB6_Pos      (6U)\n#define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R1_FB7_Pos      (7U)\n#define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R1_FB8_Pos      (8U)\n#define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R1_FB9_Pos      (9U)\n#define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R1_FB10_Pos     (10U)\n#define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R1_FB11_Pos     (11U)\n#define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R1_FB12_Pos     (12U)\n#define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R1_FB13_Pos     (13U)\n#define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R1_FB14_Pos     (14U)\n#define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R1_FB15_Pos     (15U)\n#define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R1_FB16_Pos     (16U)\n#define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R1_FB17_Pos     (17U)\n#define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R1_FB18_Pos     (18U)\n#define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R1_FB19_Pos     (19U)\n#define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R1_FB20_Pos     (20U)\n#define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R1_FB21_Pos     (21U)\n#define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R1_FB22_Pos     (22U)\n#define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R1_FB23_Pos     (23U)\n#define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R1_FB24_Pos     (24U)\n#define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R1_FB25_Pos     (25U)\n#define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R1_FB26_Pos     (26U)\n#define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R1_FB27_Pos     (27U)\n#define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R1_FB28_Pos     (28U)\n#define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R1_FB29_Pos     (29U)\n#define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R1_FB30_Pos     (30U)\n#define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R1_FB31_Pos     (31U)\n#define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F0R2 register  *******************/\n#define CAN_F0R2_FB0_Pos       (0U)\n#define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R2_FB1_Pos       (1U)\n#define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R2_FB2_Pos       (2U)\n#define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R2_FB3_Pos       (3U)\n#define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R2_FB4_Pos       (4U)\n#define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R2_FB5_Pos       (5U)\n#define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R2_FB6_Pos       (6U)\n#define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R2_FB7_Pos       (7U)\n#define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R2_FB8_Pos       (8U)\n#define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R2_FB9_Pos       (9U)\n#define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R2_FB10_Pos      (10U)\n#define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R2_FB11_Pos      (11U)\n#define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R2_FB12_Pos      (12U)\n#define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R2_FB13_Pos      (13U)\n#define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R2_FB14_Pos      (14U)\n#define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R2_FB15_Pos      (15U)\n#define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R2_FB16_Pos      (16U)\n#define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R2_FB17_Pos      (17U)\n#define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R2_FB18_Pos      (18U)\n#define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R2_FB19_Pos      (19U)\n#define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R2_FB20_Pos      (20U)\n#define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R2_FB21_Pos      (21U)\n#define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R2_FB22_Pos      (22U)\n#define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R2_FB23_Pos      (23U)\n#define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R2_FB24_Pos      (24U)\n#define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R2_FB25_Pos      (25U)\n#define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R2_FB26_Pos      (26U)\n#define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R2_FB27_Pos      (27U)\n#define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R2_FB28_Pos      (28U)\n#define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R2_FB29_Pos      (29U)\n#define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R2_FB30_Pos      (30U)\n#define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R2_FB31_Pos      (31U)\n#define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R2 register  *******************/\n#define CAN_F1R2_FB0_Pos       (0U)\n#define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R2_FB1_Pos       (1U)\n#define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R2_FB2_Pos       (2U)\n#define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R2_FB3_Pos       (3U)\n#define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R2_FB4_Pos       (4U)\n#define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R2_FB5_Pos       (5U)\n#define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R2_FB6_Pos       (6U)\n#define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R2_FB7_Pos       (7U)\n#define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R2_FB8_Pos       (8U)\n#define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R2_FB9_Pos       (9U)\n#define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R2_FB10_Pos      (10U)\n#define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R2_FB11_Pos      (11U)\n#define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R2_FB12_Pos      (12U)\n#define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R2_FB13_Pos      (13U)\n#define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R2_FB14_Pos      (14U)\n#define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R2_FB15_Pos      (15U)\n#define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R2_FB16_Pos      (16U)\n#define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R2_FB17_Pos      (17U)\n#define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R2_FB18_Pos      (18U)\n#define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R2_FB19_Pos      (19U)\n#define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R2_FB20_Pos      (20U)\n#define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R2_FB21_Pos      (21U)\n#define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R2_FB22_Pos      (22U)\n#define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R2_FB23_Pos      (23U)\n#define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R2_FB24_Pos      (24U)\n#define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R2_FB25_Pos      (25U)\n#define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R2_FB26_Pos      (26U)\n#define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R2_FB27_Pos      (27U)\n#define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R2_FB28_Pos      (28U)\n#define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R2_FB29_Pos      (29U)\n#define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R2_FB30_Pos      (30U)\n#define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R2_FB31_Pos      (31U)\n#define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R2 register  *******************/\n#define CAN_F2R2_FB0_Pos       (0U)\n#define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R2_FB1_Pos       (1U)\n#define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R2_FB2_Pos       (2U)\n#define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R2_FB3_Pos       (3U)\n#define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R2_FB4_Pos       (4U)\n#define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R2_FB5_Pos       (5U)\n#define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R2_FB6_Pos       (6U)\n#define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R2_FB7_Pos       (7U)\n#define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R2_FB8_Pos       (8U)\n#define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R2_FB9_Pos       (9U)\n#define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R2_FB10_Pos      (10U)\n#define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R2_FB11_Pos      (11U)\n#define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R2_FB12_Pos      (12U)\n#define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R2_FB13_Pos      (13U)\n#define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R2_FB14_Pos      (14U)\n#define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R2_FB15_Pos      (15U)\n#define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R2_FB16_Pos      (16U)\n#define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R2_FB17_Pos      (17U)\n#define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R2_FB18_Pos      (18U)\n#define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R2_FB19_Pos      (19U)\n#define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R2_FB20_Pos      (20U)\n#define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R2_FB21_Pos      (21U)\n#define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R2_FB22_Pos      (22U)\n#define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R2_FB23_Pos      (23U)\n#define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R2_FB24_Pos      (24U)\n#define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R2_FB25_Pos      (25U)\n#define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R2_FB26_Pos      (26U)\n#define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R2_FB27_Pos      (27U)\n#define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R2_FB28_Pos      (28U)\n#define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R2_FB29_Pos      (29U)\n#define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R2_FB30_Pos      (30U)\n#define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R2_FB31_Pos      (31U)\n#define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R2 register  *******************/\n#define CAN_F3R2_FB0_Pos       (0U)\n#define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R2_FB1_Pos       (1U)\n#define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R2_FB2_Pos       (2U)\n#define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R2_FB3_Pos       (3U)\n#define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R2_FB4_Pos       (4U)\n#define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R2_FB5_Pos       (5U)\n#define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R2_FB6_Pos       (6U)\n#define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R2_FB7_Pos       (7U)\n#define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R2_FB8_Pos       (8U)\n#define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R2_FB9_Pos       (9U)\n#define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R2_FB10_Pos      (10U)\n#define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R2_FB11_Pos      (11U)\n#define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R2_FB12_Pos      (12U)\n#define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R2_FB13_Pos      (13U)\n#define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R2_FB14_Pos      (14U)\n#define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R2_FB15_Pos      (15U)\n#define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R2_FB16_Pos      (16U)\n#define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R2_FB17_Pos      (17U)\n#define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R2_FB18_Pos      (18U)\n#define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R2_FB19_Pos      (19U)\n#define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R2_FB20_Pos      (20U)\n#define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R2_FB21_Pos      (21U)\n#define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R2_FB22_Pos      (22U)\n#define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R2_FB23_Pos      (23U)\n#define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R2_FB24_Pos      (24U)\n#define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R2_FB25_Pos      (25U)\n#define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R2_FB26_Pos      (26U)\n#define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R2_FB27_Pos      (27U)\n#define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R2_FB28_Pos      (28U)\n#define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R2_FB29_Pos      (29U)\n#define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R2_FB30_Pos      (30U)\n#define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R2_FB31_Pos      (31U)\n#define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R2 register  *******************/\n#define CAN_F4R2_FB0_Pos       (0U)\n#define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R2_FB1_Pos       (1U)\n#define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R2_FB2_Pos       (2U)\n#define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R2_FB3_Pos       (3U)\n#define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R2_FB4_Pos       (4U)\n#define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R2_FB5_Pos       (5U)\n#define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R2_FB6_Pos       (6U)\n#define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R2_FB7_Pos       (7U)\n#define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R2_FB8_Pos       (8U)\n#define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R2_FB9_Pos       (9U)\n#define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R2_FB10_Pos      (10U)\n#define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R2_FB11_Pos      (11U)\n#define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R2_FB12_Pos      (12U)\n#define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R2_FB13_Pos      (13U)\n#define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R2_FB14_Pos      (14U)\n#define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R2_FB15_Pos      (15U)\n#define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R2_FB16_Pos      (16U)\n#define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R2_FB17_Pos      (17U)\n#define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R2_FB18_Pos      (18U)\n#define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R2_FB19_Pos      (19U)\n#define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R2_FB20_Pos      (20U)\n#define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R2_FB21_Pos      (21U)\n#define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R2_FB22_Pos      (22U)\n#define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R2_FB23_Pos      (23U)\n#define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R2_FB24_Pos      (24U)\n#define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R2_FB25_Pos      (25U)\n#define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R2_FB26_Pos      (26U)\n#define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R2_FB27_Pos      (27U)\n#define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R2_FB28_Pos      (28U)\n#define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R2_FB29_Pos      (29U)\n#define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R2_FB30_Pos      (30U)\n#define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R2_FB31_Pos      (31U)\n#define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R2 register  *******************/\n#define CAN_F5R2_FB0_Pos       (0U)\n#define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R2_FB1_Pos       (1U)\n#define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R2_FB2_Pos       (2U)\n#define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R2_FB3_Pos       (3U)\n#define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R2_FB4_Pos       (4U)\n#define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R2_FB5_Pos       (5U)\n#define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R2_FB6_Pos       (6U)\n#define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R2_FB7_Pos       (7U)\n#define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R2_FB8_Pos       (8U)\n#define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R2_FB9_Pos       (9U)\n#define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R2_FB10_Pos      (10U)\n#define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R2_FB11_Pos      (11U)\n#define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R2_FB12_Pos      (12U)\n#define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R2_FB13_Pos      (13U)\n#define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R2_FB14_Pos      (14U)\n#define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R2_FB15_Pos      (15U)\n#define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R2_FB16_Pos      (16U)\n#define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R2_FB17_Pos      (17U)\n#define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R2_FB18_Pos      (18U)\n#define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R2_FB19_Pos      (19U)\n#define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R2_FB20_Pos      (20U)\n#define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R2_FB21_Pos      (21U)\n#define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R2_FB22_Pos      (22U)\n#define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R2_FB23_Pos      (23U)\n#define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R2_FB24_Pos      (24U)\n#define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R2_FB25_Pos      (25U)\n#define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R2_FB26_Pos      (26U)\n#define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R2_FB27_Pos      (27U)\n#define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R2_FB28_Pos      (28U)\n#define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R2_FB29_Pos      (29U)\n#define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R2_FB30_Pos      (30U)\n#define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R2_FB31_Pos      (31U)\n#define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R2 register  *******************/\n#define CAN_F6R2_FB0_Pos       (0U)\n#define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R2_FB1_Pos       (1U)\n#define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R2_FB2_Pos       (2U)\n#define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R2_FB3_Pos       (3U)\n#define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R2_FB4_Pos       (4U)\n#define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R2_FB5_Pos       (5U)\n#define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R2_FB6_Pos       (6U)\n#define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R2_FB7_Pos       (7U)\n#define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R2_FB8_Pos       (8U)\n#define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R2_FB9_Pos       (9U)\n#define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R2_FB10_Pos      (10U)\n#define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R2_FB11_Pos      (11U)\n#define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R2_FB12_Pos      (12U)\n#define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R2_FB13_Pos      (13U)\n#define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R2_FB14_Pos      (14U)\n#define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R2_FB15_Pos      (15U)\n#define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R2_FB16_Pos      (16U)\n#define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R2_FB17_Pos      (17U)\n#define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R2_FB18_Pos      (18U)\n#define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R2_FB19_Pos      (19U)\n#define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R2_FB20_Pos      (20U)\n#define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R2_FB21_Pos      (21U)\n#define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R2_FB22_Pos      (22U)\n#define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R2_FB23_Pos      (23U)\n#define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R2_FB24_Pos      (24U)\n#define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R2_FB25_Pos      (25U)\n#define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R2_FB26_Pos      (26U)\n#define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R2_FB27_Pos      (27U)\n#define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R2_FB28_Pos      (28U)\n#define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R2_FB29_Pos      (29U)\n#define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R2_FB30_Pos      (30U)\n#define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R2_FB31_Pos      (31U)\n#define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R2 register  *******************/\n#define CAN_F7R2_FB0_Pos       (0U)\n#define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R2_FB1_Pos       (1U)\n#define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R2_FB2_Pos       (2U)\n#define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R2_FB3_Pos       (3U)\n#define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R2_FB4_Pos       (4U)\n#define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R2_FB5_Pos       (5U)\n#define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R2_FB6_Pos       (6U)\n#define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R2_FB7_Pos       (7U)\n#define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R2_FB8_Pos       (8U)\n#define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R2_FB9_Pos       (9U)\n#define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R2_FB10_Pos      (10U)\n#define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R2_FB11_Pos      (11U)\n#define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R2_FB12_Pos      (12U)\n#define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R2_FB13_Pos      (13U)\n#define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R2_FB14_Pos      (14U)\n#define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R2_FB15_Pos      (15U)\n#define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R2_FB16_Pos      (16U)\n#define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R2_FB17_Pos      (17U)\n#define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R2_FB18_Pos      (18U)\n#define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R2_FB19_Pos      (19U)\n#define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R2_FB20_Pos      (20U)\n#define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R2_FB21_Pos      (21U)\n#define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R2_FB22_Pos      (22U)\n#define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R2_FB23_Pos      (23U)\n#define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R2_FB24_Pos      (24U)\n#define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R2_FB25_Pos      (25U)\n#define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R2_FB26_Pos      (26U)\n#define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R2_FB27_Pos      (27U)\n#define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R2_FB28_Pos      (28U)\n#define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R2_FB29_Pos      (29U)\n#define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R2_FB30_Pos      (30U)\n#define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R2_FB31_Pos      (31U)\n#define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R2 register  *******************/\n#define CAN_F8R2_FB0_Pos       (0U)\n#define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R2_FB1_Pos       (1U)\n#define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R2_FB2_Pos       (2U)\n#define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R2_FB3_Pos       (3U)\n#define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R2_FB4_Pos       (4U)\n#define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R2_FB5_Pos       (5U)\n#define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R2_FB6_Pos       (6U)\n#define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R2_FB7_Pos       (7U)\n#define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R2_FB8_Pos       (8U)\n#define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R2_FB9_Pos       (9U)\n#define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R2_FB10_Pos      (10U)\n#define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R2_FB11_Pos      (11U)\n#define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R2_FB12_Pos      (12U)\n#define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R2_FB13_Pos      (13U)\n#define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R2_FB14_Pos      (14U)\n#define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R2_FB15_Pos      (15U)\n#define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R2_FB16_Pos      (16U)\n#define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R2_FB17_Pos      (17U)\n#define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R2_FB18_Pos      (18U)\n#define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R2_FB19_Pos      (19U)\n#define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R2_FB20_Pos      (20U)\n#define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R2_FB21_Pos      (21U)\n#define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R2_FB22_Pos      (22U)\n#define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R2_FB23_Pos      (23U)\n#define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R2_FB24_Pos      (24U)\n#define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R2_FB25_Pos      (25U)\n#define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R2_FB26_Pos      (26U)\n#define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R2_FB27_Pos      (27U)\n#define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R2_FB28_Pos      (28U)\n#define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R2_FB29_Pos      (29U)\n#define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R2_FB30_Pos      (30U)\n#define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R2_FB31_Pos      (31U)\n#define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R2 register  *******************/\n#define CAN_F9R2_FB0_Pos       (0U)\n#define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R2_FB1_Pos       (1U)\n#define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R2_FB2_Pos       (2U)\n#define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R2_FB3_Pos       (3U)\n#define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R2_FB4_Pos       (4U)\n#define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R2_FB5_Pos       (5U)\n#define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R2_FB6_Pos       (6U)\n#define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R2_FB7_Pos       (7U)\n#define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R2_FB8_Pos       (8U)\n#define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R2_FB9_Pos       (9U)\n#define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R2_FB10_Pos      (10U)\n#define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R2_FB11_Pos      (11U)\n#define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R2_FB12_Pos      (12U)\n#define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R2_FB13_Pos      (13U)\n#define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R2_FB14_Pos      (14U)\n#define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R2_FB15_Pos      (15U)\n#define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R2_FB16_Pos      (16U)\n#define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R2_FB17_Pos      (17U)\n#define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R2_FB18_Pos      (18U)\n#define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R2_FB19_Pos      (19U)\n#define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R2_FB20_Pos      (20U)\n#define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R2_FB21_Pos      (21U)\n#define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R2_FB22_Pos      (22U)\n#define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R2_FB23_Pos      (23U)\n#define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R2_FB24_Pos      (24U)\n#define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R2_FB25_Pos      (25U)\n#define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R2_FB26_Pos      (26U)\n#define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R2_FB27_Pos      (27U)\n#define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R2_FB28_Pos      (28U)\n#define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R2_FB29_Pos      (29U)\n#define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R2_FB30_Pos      (30U)\n#define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R2_FB31_Pos      (31U)\n#define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R2 register  ******************/\n#define CAN_F10R2_FB0_Pos      (0U)\n#define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R2_FB1_Pos      (1U)\n#define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R2_FB2_Pos      (2U)\n#define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R2_FB3_Pos      (3U)\n#define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R2_FB4_Pos      (4U)\n#define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R2_FB5_Pos      (5U)\n#define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R2_FB6_Pos      (6U)\n#define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R2_FB7_Pos      (7U)\n#define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R2_FB8_Pos      (8U)\n#define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R2_FB9_Pos      (9U)\n#define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R2_FB10_Pos     (10U)\n#define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R2_FB11_Pos     (11U)\n#define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R2_FB12_Pos     (12U)\n#define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R2_FB13_Pos     (13U)\n#define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R2_FB14_Pos     (14U)\n#define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R2_FB15_Pos     (15U)\n#define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R2_FB16_Pos     (16U)\n#define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R2_FB17_Pos     (17U)\n#define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R2_FB18_Pos     (18U)\n#define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R2_FB19_Pos     (19U)\n#define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R2_FB20_Pos     (20U)\n#define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R2_FB21_Pos     (21U)\n#define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R2_FB22_Pos     (22U)\n#define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R2_FB23_Pos     (23U)\n#define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R2_FB24_Pos     (24U)\n#define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R2_FB25_Pos     (25U)\n#define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R2_FB26_Pos     (26U)\n#define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R2_FB27_Pos     (27U)\n#define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R2_FB28_Pos     (28U)\n#define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R2_FB29_Pos     (29U)\n#define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R2_FB30_Pos     (30U)\n#define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R2_FB31_Pos     (31U)\n#define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R2 register  ******************/\n#define CAN_F11R2_FB0_Pos      (0U)\n#define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R2_FB1_Pos      (1U)\n#define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R2_FB2_Pos      (2U)\n#define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R2_FB3_Pos      (3U)\n#define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R2_FB4_Pos      (4U)\n#define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R2_FB5_Pos      (5U)\n#define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R2_FB6_Pos      (6U)\n#define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R2_FB7_Pos      (7U)\n#define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R2_FB8_Pos      (8U)\n#define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R2_FB9_Pos      (9U)\n#define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R2_FB10_Pos     (10U)\n#define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R2_FB11_Pos     (11U)\n#define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R2_FB12_Pos     (12U)\n#define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R2_FB13_Pos     (13U)\n#define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R2_FB14_Pos     (14U)\n#define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R2_FB15_Pos     (15U)\n#define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R2_FB16_Pos     (16U)\n#define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R2_FB17_Pos     (17U)\n#define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R2_FB18_Pos     (18U)\n#define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R2_FB19_Pos     (19U)\n#define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R2_FB20_Pos     (20U)\n#define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R2_FB21_Pos     (21U)\n#define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R2_FB22_Pos     (22U)\n#define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R2_FB23_Pos     (23U)\n#define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R2_FB24_Pos     (24U)\n#define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R2_FB25_Pos     (25U)\n#define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R2_FB26_Pos     (26U)\n#define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R2_FB27_Pos     (27U)\n#define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R2_FB28_Pos     (28U)\n#define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R2_FB29_Pos     (29U)\n#define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R2_FB30_Pos     (30U)\n#define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R2_FB31_Pos     (31U)\n#define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R2 register  ******************/\n#define CAN_F12R2_FB0_Pos      (0U)\n#define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R2_FB1_Pos      (1U)\n#define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R2_FB2_Pos      (2U)\n#define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R2_FB3_Pos      (3U)\n#define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R2_FB4_Pos      (4U)\n#define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R2_FB5_Pos      (5U)\n#define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R2_FB6_Pos      (6U)\n#define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R2_FB7_Pos      (7U)\n#define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R2_FB8_Pos      (8U)\n#define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R2_FB9_Pos      (9U)\n#define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R2_FB10_Pos     (10U)\n#define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R2_FB11_Pos     (11U)\n#define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R2_FB12_Pos     (12U)\n#define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R2_FB13_Pos     (13U)\n#define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R2_FB14_Pos     (14U)\n#define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R2_FB15_Pos     (15U)\n#define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R2_FB16_Pos     (16U)\n#define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R2_FB17_Pos     (17U)\n#define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R2_FB18_Pos     (18U)\n#define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R2_FB19_Pos     (19U)\n#define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R2_FB20_Pos     (20U)\n#define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R2_FB21_Pos     (21U)\n#define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R2_FB22_Pos     (22U)\n#define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R2_FB23_Pos     (23U)\n#define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R2_FB24_Pos     (24U)\n#define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R2_FB25_Pos     (25U)\n#define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R2_FB26_Pos     (26U)\n#define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R2_FB27_Pos     (27U)\n#define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R2_FB28_Pos     (28U)\n#define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R2_FB29_Pos     (29U)\n#define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R2_FB30_Pos     (30U)\n#define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R2_FB31_Pos     (31U)\n#define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R2 register  ******************/\n#define CAN_F13R2_FB0_Pos      (0U)\n#define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R2_FB1_Pos      (1U)\n#define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R2_FB2_Pos      (2U)\n#define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R2_FB3_Pos      (3U)\n#define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R2_FB4_Pos      (4U)\n#define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R2_FB5_Pos      (5U)\n#define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R2_FB6_Pos      (6U)\n#define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R2_FB7_Pos      (7U)\n#define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R2_FB8_Pos      (8U)\n#define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R2_FB9_Pos      (9U)\n#define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R2_FB10_Pos     (10U)\n#define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R2_FB11_Pos     (11U)\n#define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R2_FB12_Pos     (12U)\n#define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R2_FB13_Pos     (13U)\n#define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R2_FB14_Pos     (14U)\n#define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R2_FB15_Pos     (15U)\n#define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R2_FB16_Pos     (16U)\n#define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R2_FB17_Pos     (17U)\n#define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R2_FB18_Pos     (18U)\n#define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R2_FB19_Pos     (19U)\n#define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R2_FB20_Pos     (20U)\n#define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R2_FB21_Pos     (21U)\n#define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R2_FB22_Pos     (22U)\n#define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R2_FB23_Pos     (23U)\n#define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R2_FB24_Pos     (24U)\n#define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R2_FB25_Pos     (25U)\n#define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R2_FB26_Pos     (26U)\n#define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R2_FB27_Pos     (27U)\n#define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R2_FB28_Pos     (28U)\n#define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R2_FB29_Pos     (29U)\n#define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R2_FB30_Pos     (30U)\n#define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R2_FB31_Pos     (31U)\n#define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          CRC calculation unit                              */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for CRC_DR register  *********************/\n#define CRC_DR_DR_Pos       (0U)\n#define CRC_DR_DR_Msk       (0xFFFFFFFFUL << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */\n#define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */\n\n\n/*******************  Bit definition for CRC_IDR register  ********************/\n#define CRC_IDR_IDR_Pos     (0U)\n#define CRC_IDR_IDR_Msk     (0xFFUL << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */\n#define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */\n\n\n/********************  Bit definition for CRC_CR register  ********************/\n#define CRC_CR_RESET_Pos    (0U)\n#define CRC_CR_RESET_Msk    (0x1UL << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */\n#define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Digital to Analog Converter                           */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define DAC_CHANNEL2_SUPPORT                                    /*!< DAC feature available only on specific devices: availability of DAC channel 2 */\n/********************  Bit definition for DAC_CR register  ********************/\n#define DAC_CR_EN1_Pos              (0U)\n#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */\n#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */\n#define DAC_CR_BOFF1_Pos            (1U)\n#define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */\n#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable */\n#define DAC_CR_TEN1_Pos             (2U)\n#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */\n#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */\n\n#define DAC_CR_TSEL1_Pos            (3U)\n#define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */\n#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\n#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */\n#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */\n#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */\n\n#define DAC_CR_WAVE1_Pos            (6U)\n#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */\n#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */\n#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */\n\n#define DAC_CR_MAMP1_Pos            (8U)\n#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */\n#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\n#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */\n#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */\n#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */\n#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */\n\n#define DAC_CR_DMAEN1_Pos           (12U)\n#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */\n#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */\n#define DAC_CR_DMAUDRIE1_Pos        (13U)\n#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */\n#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable*/\n#define DAC_CR_EN2_Pos              (16U)\n#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */\n#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */\n#define DAC_CR_BOFF2_Pos            (17U)\n#define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */\n#define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable */\n#define DAC_CR_TEN2_Pos             (18U)\n#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */\n#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */\n\n#define DAC_CR_TSEL2_Pos            (19U)\n#define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */\n#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\n#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */\n#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */\n#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */\n\n#define DAC_CR_WAVE2_Pos            (22U)\n#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */\n#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */\n#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */\n\n#define DAC_CR_MAMP2_Pos            (24U)\n#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */\n#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\n#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */\n#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */\n#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */\n#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */\n\n#define DAC_CR_DMAEN2_Pos           (28U)\n#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */\n#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */\n#define DAC_CR_DMAUDRIE2_Pos        (29U)\n#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */\n#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable*/\n\n/*****************  Bit definition for DAC_SWTRIGR register  ******************/\n#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)\n#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */\n#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */\n#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)\n#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */\n#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */\n\n/*****************  Bit definition for DAC_DHR12R1 register  ******************/\n#define DAC_DHR12R1_DACC1DHR_Pos    (0U)\n#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L1 register  ******************/\n#define DAC_DHR12L1_DACC1DHR_Pos    (4U)\n#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R1 register  ******************/\n#define DAC_DHR8R1_DACC1DHR_Pos     (0U)\n#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12R2 register  ******************/\n#define DAC_DHR12R2_DACC2DHR_Pos    (0U)\n#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L2 register  ******************/\n#define DAC_DHR12L2_DACC2DHR_Pos    (4U)\n#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R2 register  ******************/\n#define DAC_DHR8R2_DACC2DHR_Pos     (0U)\n#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12RD register  ******************/\n#define DAC_DHR12RD_DACC1DHR_Pos    (0U)\n#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\n#define DAC_DHR12RD_DACC2DHR_Pos    (16U)\n#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */\n#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12LD register  ******************/\n#define DAC_DHR12LD_DACC1DHR_Pos    (4U)\n#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\n#define DAC_DHR12LD_DACC2DHR_Pos    (20U)\n#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */\n#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8RD register  ******************/\n#define DAC_DHR8RD_DACC1DHR_Pos     (0U)\n#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\n#define DAC_DHR8RD_DACC2DHR_Pos     (8U)\n#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */\n#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\n\n/*******************  Bit definition for DAC_DOR1 register  *******************/\n#define DAC_DOR1_DACC1DOR_Pos       (0U)\n#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */\n#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */\n\n/*******************  Bit definition for DAC_DOR2 register  *******************/\n#define DAC_DOR2_DACC2DOR_Pos       (0U)\n#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */\n#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */\n\n/********************  Bit definition for DAC_SR register  ********************/\n#define DAC_SR_DMAUDR1_Pos          (13U)\n#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */\n#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */\n#define DAC_SR_DMAUDR2_Pos          (29U)\n#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */\n#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */\n\n/******************************************************************************/\n/*                                                                            */\n/*                 Digital Filter for Sigma Delta Modulators                  */\n/*                                                                            */\n/******************************************************************************/\n\n/****************   DFSDM channel configuration registers  ********************/\n\n/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/\n#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)\n#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)    /*!< 0x80000000 */\n#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */\n#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)\n#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)   /*!< 0x40000000 */\n#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */\n#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)\n#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos)  /*!< 0x00FF0000 */\n#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */\n#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)\n#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x0000C000 */\n#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */\n#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */\n#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */\n#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)\n#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00003000 */\n#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */\n#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */\n#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */\n#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)\n#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)    /*!< 0x00000100 */\n#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */\n#define DFSDM_CHCFGR1_CHEN_Pos          (7U)\n#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)       /*!< 0x00000080 */\n#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */\n#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)\n#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)     /*!< 0x00000040 */\n#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */\n#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)\n#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)      /*!< 0x00000020 */\n#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */\n#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)\n#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x0000000C */\n#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */\n#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */\n#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */\n#define DFSDM_CHCFGR1_SITP_Pos          (0U)\n#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000003 */\n#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */\n#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */\n#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */\n\n/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/\n#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)\n#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */\n#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)\n#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)     /*!< 0x000000F8 */\n#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */\n\n/****************  Bit definition for DFSDM_CHAWSCDR register *****************/\n#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)\n#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00C00000 */\n#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */\n#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */\n#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */\n#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)\n#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)   /*!< 0x001F0000 */\n#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */\n#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)\n#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)     /*!< 0x0000F000 */\n#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */\n#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)\n#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)     /*!< 0x000000FF */\n#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */\n\n/****************  Bit definition for DFSDM_CHWDATR register *******************/\n#define DFSDM_CHWDATR_WDATA_Pos         (0U)\n#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)   /*!< 0x0000FFFF */\n#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */\n\n/****************  Bit definition for DFSDM_CHDATINR register *****************/\n#define DFSDM_CHDATINR_INDAT0_Pos       (0U)\n#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */\n#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */\n#define DFSDM_CHDATINR_INDAT1_Pos       (16U)\n#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */\n#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */\n\n/************************   DFSDM module registers  ****************************/\n\n/*****************  Bit definition for DFSDM_FLTCR1 register *******************/\n#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)\n#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)      /*!< 0x40000000 */\n#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */\n#define DFSDM_FLTCR1_FAST_Pos           (29U)\n#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)        /*!< 0x20000000 */\n#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */\n#define DFSDM_FLTCR1_RCH_Pos            (24U)\n#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)         /*!< 0x07000000 */\n#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */\n#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)\n#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)      /*!< 0x00200000 */\n#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */\n#define DFSDM_FLTCR1_RSYNC_Pos          (19U)\n#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)       /*!< 0x00080000 */\n#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */\n#define DFSDM_FLTCR1_RCONT_Pos          (18U)\n#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)       /*!< 0x00040000 */\n#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */\n#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)\n#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)    /*!< 0x00020000 */\n#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */\n#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)\n#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00006000 */\n#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */\n#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */\n#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */\n#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)\n#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x7UL << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000700 */\n#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */\n#define DFSDM_FLTCR1_JEXTSEL_2          (0x4UL << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000400 */\n#define DFSDM_FLTCR1_JEXTSEL_1          (0x2UL << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000200 */\n#define DFSDM_FLTCR1_JEXTSEL_0          (0x1UL << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000100 */\n#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)\n#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)      /*!< 0x00000020 */\n#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */\n#define DFSDM_FLTCR1_JSCAN_Pos          (4U)\n#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)       /*!< 0x00000010 */\n#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */\n#define DFSDM_FLTCR1_JSYNC_Pos          (3U)\n#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)       /*!< 0x00000008 */\n#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */\n#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)\n#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)    /*!< 0x00000002 */\n#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */\n#define DFSDM_FLTCR1_DFEN_Pos           (0U)\n#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)        /*!< 0x00000001 */\n#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */\n\n/*****************  Bit definition for DFSDM_FLTCR2 register *******************/\n#define DFSDM_FLTCR2_AWDCH_Pos          (16U)\n#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)      /*!< 0x00FF0000 */\n#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */\n#define DFSDM_FLTCR2_EXCH_Pos           (8U)\n#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)       /*!< 0x0000FF00 */\n#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */\n#define DFSDM_FLTCR2_CKABIE_Pos         (6U)\n#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)      /*!< 0x00000040 */\n#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */\n#define DFSDM_FLTCR2_SCDIE_Pos          (5U)\n#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)       /*!< 0x00000020 */\n#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */\n#define DFSDM_FLTCR2_AWDIE_Pos          (4U)\n#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)       /*!< 0x00000010 */\n#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */\n#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)\n#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)      /*!< 0x00000008 */\n#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */\n#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)\n#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)      /*!< 0x00000004 */\n#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */\n#define DFSDM_FLTCR2_REOCIE_Pos         (1U)\n#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)      /*!< 0x00000002 */\n#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */\n#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)\n#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)      /*!< 0x00000001 */\n#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */\n\n/*****************  Bit definition for DFSDM_FLTISR register *******************/\n#define DFSDM_FLTISR_SCDF_Pos           (24U)\n#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)       /*!< 0xFF000000 */\n#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */\n#define DFSDM_FLTISR_CKABF_Pos          (16U)\n#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)      /*!< 0x00FF0000 */\n#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */\n#define DFSDM_FLTISR_RCIP_Pos           (14U)\n#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)        /*!< 0x00004000 */\n#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */\n#define DFSDM_FLTISR_JCIP_Pos           (13U)\n#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)        /*!< 0x00002000 */\n#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */\n#define DFSDM_FLTISR_AWDF_Pos           (4U)\n#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)        /*!< 0x00000010 */\n#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */\n#define DFSDM_FLTISR_ROVRF_Pos          (3U)\n#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)       /*!< 0x00000008 */\n#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */\n#define DFSDM_FLTISR_JOVRF_Pos          (2U)\n#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)       /*!< 0x00000004 */\n#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */\n#define DFSDM_FLTISR_REOCF_Pos          (1U)\n#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)       /*!< 0x00000002 */\n#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */\n#define DFSDM_FLTISR_JEOCF_Pos          (0U)\n#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)       /*!< 0x00000001 */\n#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */\n\n/*****************  Bit definition for DFSDM_FLTICR register *******************/\n#define DFSDM_FLTICR_CLRSCDF_Pos       (24U)\n#define DFSDM_FLTICR_CLRSCDF_Msk       (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)     /*!< 0xFF000000 */\n#define DFSDM_FLTICR_CLRSCDF           DFSDM_FLTICR_CLRSCDF_Msk                /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */\n#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)\n#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)   /*!< 0x00FF0000 */\n#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */\n#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)\n#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)    /*!< 0x00000008 */\n#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */\n#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)\n#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)    /*!< 0x00000004 */\n#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */\n\n/****************  Bit definition for DFSDM_FLTJCHGR register ******************/\n#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)\n#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)     /*!< 0x000000FF */\n#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */\n\n/*****************  Bit definition for DFSDM_FLTFCR register *******************/\n#define DFSDM_FLTFCR_FORD_Pos           (29U)\n#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0xE0000000 */\n#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */\n#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */\n#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */\n#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */\n#define DFSDM_FLTFCR_FOSR_Pos           (16U)\n#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)      /*!< 0x03FF0000 */\n#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */\n#define DFSDM_FLTFCR_IOSR_Pos           (0U)\n#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)       /*!< 0x000000FF */\n#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */\n\n/***************  Bit definition for DFSDM_FLTJDATAR register *****************/\n#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)\n#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */\n#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)\n#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos)  /*!< 0x00000007 */\n#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */\n\n/***************  Bit definition for DFSDM_FLTRDATAR register *****************/\n#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)\n#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */\n#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)\n#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)    /*!< 0x00000010 */\n#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */\n#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)\n#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos)  /*!< 0x00000007 */\n#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */\n\n/***************  Bit definition for DFSDM_FLTAWHTR register ******************/\n#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)\n#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */\n#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)\n#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)     /*!< 0x0000000F */\n#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */\n\n/***************  Bit definition for DFSDM_FLTAWLTR register ******************/\n#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)\n#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWLT[23:0] Analog watchdog low threshold */\n#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)\n#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)     /*!< 0x0000000F */\n#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */\n\n/***************  Bit definition for DFSDM_FLTAWSR register *******************/\n#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)\n#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)     /*!< 0x0000FF00 */\n#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */\n#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)\n#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)     /*!< 0x000000FF */\n#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */\n\n\n/***************  Bit definition for DFSDM_FLTAWCFR register ******************/\n#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)\n#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */\n#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */\n#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)\n#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */\n#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */\n\n/***************  Bit definition for DFSDM_FLTEXMAX register ******************/\n#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)\n#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */\n#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)\n#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)   /*!< 0x00000007 */\n#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */\n\n/***************  Bit definition for DFSDM_FLTEXMIN register ******************/\n#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)\n#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */\n#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)\n#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)   /*!< 0x00000007 */\n#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */\n\n/***************  Bit definition for DFSDM_FLTCNVTIMR register ****************/\n#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)\n#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */\n#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */\n\n/* Legacy Defines */\n#define DFSDM_FLTICR_CLRSCSDF_Pos        DFSDM_FLTICR_CLRSCDF_Pos\n#define DFSDM_FLTICR_CLRSCSDF_Msk        DFSDM_FLTICR_CLRSCDF_Msk\n#define DFSDM_FLTICR_CLRSCSDF            DFSDM_FLTICR_CLRSCDF\n\n/******************************************************************************/\n/*                                                                            */\n/*                             DMA Controller                                 */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DMA_SxCR register  *****************/\n#define DMA_SxCR_CHSEL_Pos       (25U)\n#define DMA_SxCR_CHSEL_Msk       (0xFUL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x1E000000 */\n#define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk\n#define DMA_SxCR_CHSEL_0         0x02000000U\n#define DMA_SxCR_CHSEL_1         0x04000000U\n#define DMA_SxCR_CHSEL_2         0x08000000U\n#define DMA_SxCR_CHSEL_3         0x10000000U\n#define DMA_SxCR_MBURST_Pos      (23U)\n#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */\n#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk\n#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */\n#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */\n#define DMA_SxCR_PBURST_Pos      (21U)\n#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */\n#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk\n#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */\n#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */\n#define DMA_SxCR_CT_Pos          (19U)\n#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */\n#define DMA_SxCR_CT              DMA_SxCR_CT_Msk\n#define DMA_SxCR_DBM_Pos         (18U)\n#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */\n#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk\n#define DMA_SxCR_PL_Pos          (16U)\n#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */\n#define DMA_SxCR_PL              DMA_SxCR_PL_Msk\n#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */\n#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */\n#define DMA_SxCR_PINCOS_Pos      (15U)\n#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */\n#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk\n#define DMA_SxCR_MSIZE_Pos       (13U)\n#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */\n#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk\n#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */\n#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */\n#define DMA_SxCR_PSIZE_Pos       (11U)\n#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */\n#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk\n#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */\n#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */\n#define DMA_SxCR_MINC_Pos        (10U)\n#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */\n#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk\n#define DMA_SxCR_PINC_Pos        (9U)\n#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */\n#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk\n#define DMA_SxCR_CIRC_Pos        (8U)\n#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */\n#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk\n#define DMA_SxCR_DIR_Pos         (6U)\n#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */\n#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk\n#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */\n#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */\n#define DMA_SxCR_PFCTRL_Pos      (5U)\n#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */\n#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk\n#define DMA_SxCR_TCIE_Pos        (4U)\n#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */\n#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk\n#define DMA_SxCR_HTIE_Pos        (3U)\n#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */\n#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk\n#define DMA_SxCR_TEIE_Pos        (2U)\n#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */\n#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk\n#define DMA_SxCR_DMEIE_Pos       (1U)\n#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */\n#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk\n#define DMA_SxCR_EN_Pos          (0U)\n#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */\n#define DMA_SxCR_EN              DMA_SxCR_EN_Msk\n\n/* Legacy defines */\n#define DMA_SxCR_ACK_Pos         (20U)\n#define DMA_SxCR_ACK_Msk         (0x1UL << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */\n#define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk\n\n/********************  Bits definition for DMA_SxCNDTR register  **************/\n#define DMA_SxNDT_Pos            (0U)\n#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */\n#define DMA_SxNDT                DMA_SxNDT_Msk\n#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */\n#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */\n#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */\n#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */\n#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */\n#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */\n#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */\n#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */\n#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */\n#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */\n#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */\n#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */\n#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */\n#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */\n#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */\n#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */\n\n/********************  Bits definition for DMA_SxFCR register  ****************/\n#define DMA_SxFCR_FEIE_Pos       (7U)\n#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */\n#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk\n#define DMA_SxFCR_FS_Pos         (3U)\n#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */\n#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk\n#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */\n#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */\n#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */\n#define DMA_SxFCR_DMDIS_Pos      (2U)\n#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */\n#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk\n#define DMA_SxFCR_FTH_Pos        (0U)\n#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */\n#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk\n#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */\n#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */\n\n/********************  Bits definition for DMA_LISR register  *****************/\n#define DMA_LISR_TCIF3_Pos       (27U)\n#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */\n#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk\n#define DMA_LISR_HTIF3_Pos       (26U)\n#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */\n#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk\n#define DMA_LISR_TEIF3_Pos       (25U)\n#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */\n#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk\n#define DMA_LISR_DMEIF3_Pos      (24U)\n#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */\n#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk\n#define DMA_LISR_FEIF3_Pos       (22U)\n#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */\n#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk\n#define DMA_LISR_TCIF2_Pos       (21U)\n#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */\n#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk\n#define DMA_LISR_HTIF2_Pos       (20U)\n#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */\n#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk\n#define DMA_LISR_TEIF2_Pos       (19U)\n#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */\n#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk\n#define DMA_LISR_DMEIF2_Pos      (18U)\n#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */\n#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk\n#define DMA_LISR_FEIF2_Pos       (16U)\n#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */\n#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk\n#define DMA_LISR_TCIF1_Pos       (11U)\n#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */\n#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk\n#define DMA_LISR_HTIF1_Pos       (10U)\n#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */\n#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk\n#define DMA_LISR_TEIF1_Pos       (9U)\n#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */\n#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk\n#define DMA_LISR_DMEIF1_Pos      (8U)\n#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */\n#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk\n#define DMA_LISR_FEIF1_Pos       (6U)\n#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */\n#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk\n#define DMA_LISR_TCIF0_Pos       (5U)\n#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */\n#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk\n#define DMA_LISR_HTIF0_Pos       (4U)\n#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */\n#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk\n#define DMA_LISR_TEIF0_Pos       (3U)\n#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */\n#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk\n#define DMA_LISR_DMEIF0_Pos      (2U)\n#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */\n#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk\n#define DMA_LISR_FEIF0_Pos       (0U)\n#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */\n#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk\n\n/********************  Bits definition for DMA_HISR register  *****************/\n#define DMA_HISR_TCIF7_Pos       (27U)\n#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */\n#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk\n#define DMA_HISR_HTIF7_Pos       (26U)\n#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */\n#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk\n#define DMA_HISR_TEIF7_Pos       (25U)\n#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */\n#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk\n#define DMA_HISR_DMEIF7_Pos      (24U)\n#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */\n#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk\n#define DMA_HISR_FEIF7_Pos       (22U)\n#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */\n#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk\n#define DMA_HISR_TCIF6_Pos       (21U)\n#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */\n#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk\n#define DMA_HISR_HTIF6_Pos       (20U)\n#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */\n#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk\n#define DMA_HISR_TEIF6_Pos       (19U)\n#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */\n#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk\n#define DMA_HISR_DMEIF6_Pos      (18U)\n#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */\n#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk\n#define DMA_HISR_FEIF6_Pos       (16U)\n#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */\n#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk\n#define DMA_HISR_TCIF5_Pos       (11U)\n#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */\n#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk\n#define DMA_HISR_HTIF5_Pos       (10U)\n#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */\n#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk\n#define DMA_HISR_TEIF5_Pos       (9U)\n#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */\n#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk\n#define DMA_HISR_DMEIF5_Pos      (8U)\n#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */\n#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk\n#define DMA_HISR_FEIF5_Pos       (6U)\n#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */\n#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk\n#define DMA_HISR_TCIF4_Pos       (5U)\n#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */\n#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk\n#define DMA_HISR_HTIF4_Pos       (4U)\n#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */\n#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk\n#define DMA_HISR_TEIF4_Pos       (3U)\n#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */\n#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk\n#define DMA_HISR_DMEIF4_Pos      (2U)\n#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */\n#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk\n#define DMA_HISR_FEIF4_Pos       (0U)\n#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */\n#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk\n\n/********************  Bits definition for DMA_LIFCR register  ****************/\n#define DMA_LIFCR_CTCIF3_Pos     (27U)\n#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */\n#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk\n#define DMA_LIFCR_CHTIF3_Pos     (26U)\n#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */\n#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk\n#define DMA_LIFCR_CTEIF3_Pos     (25U)\n#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */\n#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk\n#define DMA_LIFCR_CDMEIF3_Pos    (24U)\n#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */\n#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk\n#define DMA_LIFCR_CFEIF3_Pos     (22U)\n#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */\n#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk\n#define DMA_LIFCR_CTCIF2_Pos     (21U)\n#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */\n#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk\n#define DMA_LIFCR_CHTIF2_Pos     (20U)\n#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */\n#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk\n#define DMA_LIFCR_CTEIF2_Pos     (19U)\n#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */\n#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk\n#define DMA_LIFCR_CDMEIF2_Pos    (18U)\n#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */\n#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk\n#define DMA_LIFCR_CFEIF2_Pos     (16U)\n#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */\n#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk\n#define DMA_LIFCR_CTCIF1_Pos     (11U)\n#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */\n#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk\n#define DMA_LIFCR_CHTIF1_Pos     (10U)\n#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */\n#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk\n#define DMA_LIFCR_CTEIF1_Pos     (9U)\n#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */\n#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk\n#define DMA_LIFCR_CDMEIF1_Pos    (8U)\n#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */\n#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk\n#define DMA_LIFCR_CFEIF1_Pos     (6U)\n#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */\n#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk\n#define DMA_LIFCR_CTCIF0_Pos     (5U)\n#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */\n#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk\n#define DMA_LIFCR_CHTIF0_Pos     (4U)\n#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */\n#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk\n#define DMA_LIFCR_CTEIF0_Pos     (3U)\n#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */\n#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk\n#define DMA_LIFCR_CDMEIF0_Pos    (2U)\n#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */\n#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk\n#define DMA_LIFCR_CFEIF0_Pos     (0U)\n#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */\n#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk\n\n/********************  Bits definition for DMA_HIFCR  register  ****************/\n#define DMA_HIFCR_CTCIF7_Pos     (27U)\n#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */\n#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk\n#define DMA_HIFCR_CHTIF7_Pos     (26U)\n#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */\n#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk\n#define DMA_HIFCR_CTEIF7_Pos     (25U)\n#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */\n#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk\n#define DMA_HIFCR_CDMEIF7_Pos    (24U)\n#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */\n#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk\n#define DMA_HIFCR_CFEIF7_Pos     (22U)\n#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */\n#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk\n#define DMA_HIFCR_CTCIF6_Pos     (21U)\n#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */\n#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk\n#define DMA_HIFCR_CHTIF6_Pos     (20U)\n#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */\n#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk\n#define DMA_HIFCR_CTEIF6_Pos     (19U)\n#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */\n#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk\n#define DMA_HIFCR_CDMEIF6_Pos    (18U)\n#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */\n#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk\n#define DMA_HIFCR_CFEIF6_Pos     (16U)\n#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */\n#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk\n#define DMA_HIFCR_CTCIF5_Pos     (11U)\n#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */\n#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk\n#define DMA_HIFCR_CHTIF5_Pos     (10U)\n#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */\n#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk\n#define DMA_HIFCR_CTEIF5_Pos     (9U)\n#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */\n#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk\n#define DMA_HIFCR_CDMEIF5_Pos    (8U)\n#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */\n#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk\n#define DMA_HIFCR_CFEIF5_Pos     (6U)\n#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */\n#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk\n#define DMA_HIFCR_CTCIF4_Pos     (5U)\n#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */\n#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk\n#define DMA_HIFCR_CHTIF4_Pos     (4U)\n#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */\n#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk\n#define DMA_HIFCR_CTEIF4_Pos     (3U)\n#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */\n#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk\n#define DMA_HIFCR_CDMEIF4_Pos    (2U)\n#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */\n#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk\n#define DMA_HIFCR_CFEIF4_Pos     (0U)\n#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */\n#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk\n\n/******************  Bit definition for DMA_SxPAR register  ********************/\n#define DMA_SxPAR_PA_Pos         (0U)\n#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */\n#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */\n\n/******************  Bit definition for DMA_SxM0AR register  ********************/\n#define DMA_SxM0AR_M0A_Pos       (0U)\n#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */\n\n/******************  Bit definition for DMA_SxM1AR register  ********************/\n#define DMA_SxM1AR_M1A_Pos       (0U)\n#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                    External Interrupt/Event Controller                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for EXTI_IMR register  *******************/\n#define EXTI_IMR_MR0_Pos          (0U)\n#define EXTI_IMR_MR0_Msk          (0x1UL << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */\n#define EXTI_IMR_MR1_Pos          (1U)\n#define EXTI_IMR_MR1_Msk          (0x1UL << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */\n#define EXTI_IMR_MR2_Pos          (2U)\n#define EXTI_IMR_MR2_Msk          (0x1UL << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */\n#define EXTI_IMR_MR3_Pos          (3U)\n#define EXTI_IMR_MR3_Msk          (0x1UL << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */\n#define EXTI_IMR_MR4_Pos          (4U)\n#define EXTI_IMR_MR4_Msk          (0x1UL << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */\n#define EXTI_IMR_MR5_Pos          (5U)\n#define EXTI_IMR_MR5_Msk          (0x1UL << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */\n#define EXTI_IMR_MR6_Pos          (6U)\n#define EXTI_IMR_MR6_Msk          (0x1UL << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */\n#define EXTI_IMR_MR7_Pos          (7U)\n#define EXTI_IMR_MR7_Msk          (0x1UL << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */\n#define EXTI_IMR_MR8_Pos          (8U)\n#define EXTI_IMR_MR8_Msk          (0x1UL << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */\n#define EXTI_IMR_MR9_Pos          (9U)\n#define EXTI_IMR_MR9_Msk          (0x1UL << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */\n#define EXTI_IMR_MR10_Pos         (10U)\n#define EXTI_IMR_MR10_Msk         (0x1UL << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */\n#define EXTI_IMR_MR11_Pos         (11U)\n#define EXTI_IMR_MR11_Msk         (0x1UL << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */\n#define EXTI_IMR_MR12_Pos         (12U)\n#define EXTI_IMR_MR12_Msk         (0x1UL << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */\n#define EXTI_IMR_MR13_Pos         (13U)\n#define EXTI_IMR_MR13_Msk         (0x1UL << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */\n#define EXTI_IMR_MR14_Pos         (14U)\n#define EXTI_IMR_MR14_Msk         (0x1UL << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */\n#define EXTI_IMR_MR15_Pos         (15U)\n#define EXTI_IMR_MR15_Msk         (0x1UL << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */\n#define EXTI_IMR_MR16_Pos         (16U)\n#define EXTI_IMR_MR16_Msk         (0x1UL << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */\n#define EXTI_IMR_MR17_Pos         (17U)\n#define EXTI_IMR_MR17_Msk         (0x1UL << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */\n#define EXTI_IMR_MR18_Pos         (18U)\n#define EXTI_IMR_MR18_Msk         (0x1UL << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */\n#define EXTI_IMR_MR19_Pos         (19U)\n#define EXTI_IMR_MR19_Msk         (0x1UL << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */\n#define EXTI_IMR_MR20_Pos         (20U)\n#define EXTI_IMR_MR20_Msk         (0x1UL << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */\n#define EXTI_IMR_MR21_Pos         (21U)\n#define EXTI_IMR_MR21_Msk         (0x1UL << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */\n#define EXTI_IMR_MR22_Pos         (22U)\n#define EXTI_IMR_MR22_Msk         (0x1UL << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */\n#define EXTI_IMR_MR23_Pos         (23U)\n#define EXTI_IMR_MR23_Msk         (0x1UL << EXTI_IMR_MR23_Pos)                  /*!< 0x00800000 */\n#define EXTI_IMR_MR23             EXTI_IMR_MR23_Msk                            /*!< Interrupt Mask on line 23 */\n\n/* Reference Defines */\n#define  EXTI_IMR_IM0                        EXTI_IMR_MR0\n#define  EXTI_IMR_IM1                        EXTI_IMR_MR1\n#define  EXTI_IMR_IM2                        EXTI_IMR_MR2\n#define  EXTI_IMR_IM3                        EXTI_IMR_MR3\n#define  EXTI_IMR_IM4                        EXTI_IMR_MR4\n#define  EXTI_IMR_IM5                        EXTI_IMR_MR5\n#define  EXTI_IMR_IM6                        EXTI_IMR_MR6\n#define  EXTI_IMR_IM7                        EXTI_IMR_MR7\n#define  EXTI_IMR_IM8                        EXTI_IMR_MR8\n#define  EXTI_IMR_IM9                        EXTI_IMR_MR9\n#define  EXTI_IMR_IM10                       EXTI_IMR_MR10\n#define  EXTI_IMR_IM11                       EXTI_IMR_MR11\n#define  EXTI_IMR_IM12                       EXTI_IMR_MR12\n#define  EXTI_IMR_IM13                       EXTI_IMR_MR13\n#define  EXTI_IMR_IM14                       EXTI_IMR_MR14\n#define  EXTI_IMR_IM15                       EXTI_IMR_MR15\n#define  EXTI_IMR_IM16                       EXTI_IMR_MR16\n#define  EXTI_IMR_IM17                       EXTI_IMR_MR17\n#define  EXTI_IMR_IM18                       EXTI_IMR_MR18\n#define  EXTI_IMR_IM19                       EXTI_IMR_MR19\n#define  EXTI_IMR_IM20                       EXTI_IMR_MR20\n#define  EXTI_IMR_IM21                       EXTI_IMR_MR21\n#define  EXTI_IMR_IM22                       EXTI_IMR_MR22\n#define  EXTI_IMR_IM23                       EXTI_IMR_MR23\n#define EXTI_IMR_IM_Pos           (0U)\n#define EXTI_IMR_IM_Msk           (0xFFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x00FFFFFF */\n#define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */\n\n/*******************  Bit definition for EXTI_EMR register  *******************/\n#define EXTI_EMR_MR0_Pos          (0U)\n#define EXTI_EMR_MR0_Msk          (0x1UL << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */\n#define EXTI_EMR_MR1_Pos          (1U)\n#define EXTI_EMR_MR1_Msk          (0x1UL << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */\n#define EXTI_EMR_MR2_Pos          (2U)\n#define EXTI_EMR_MR2_Msk          (0x1UL << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */\n#define EXTI_EMR_MR3_Pos          (3U)\n#define EXTI_EMR_MR3_Msk          (0x1UL << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */\n#define EXTI_EMR_MR4_Pos          (4U)\n#define EXTI_EMR_MR4_Msk          (0x1UL << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */\n#define EXTI_EMR_MR5_Pos          (5U)\n#define EXTI_EMR_MR5_Msk          (0x1UL << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */\n#define EXTI_EMR_MR6_Pos          (6U)\n#define EXTI_EMR_MR6_Msk          (0x1UL << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */\n#define EXTI_EMR_MR7_Pos          (7U)\n#define EXTI_EMR_MR7_Msk          (0x1UL << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */\n#define EXTI_EMR_MR8_Pos          (8U)\n#define EXTI_EMR_MR8_Msk          (0x1UL << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */\n#define EXTI_EMR_MR9_Pos          (9U)\n#define EXTI_EMR_MR9_Msk          (0x1UL << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */\n#define EXTI_EMR_MR10_Pos         (10U)\n#define EXTI_EMR_MR10_Msk         (0x1UL << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */\n#define EXTI_EMR_MR11_Pos         (11U)\n#define EXTI_EMR_MR11_Msk         (0x1UL << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */\n#define EXTI_EMR_MR12_Pos         (12U)\n#define EXTI_EMR_MR12_Msk         (0x1UL << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */\n#define EXTI_EMR_MR13_Pos         (13U)\n#define EXTI_EMR_MR13_Msk         (0x1UL << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */\n#define EXTI_EMR_MR14_Pos         (14U)\n#define EXTI_EMR_MR14_Msk         (0x1UL << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */\n#define EXTI_EMR_MR15_Pos         (15U)\n#define EXTI_EMR_MR15_Msk         (0x1UL << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */\n#define EXTI_EMR_MR16_Pos         (16U)\n#define EXTI_EMR_MR16_Msk         (0x1UL << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */\n#define EXTI_EMR_MR17_Pos         (17U)\n#define EXTI_EMR_MR17_Msk         (0x1UL << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */\n#define EXTI_EMR_MR18_Pos         (18U)\n#define EXTI_EMR_MR18_Msk         (0x1UL << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */\n#define EXTI_EMR_MR19_Pos         (19U)\n#define EXTI_EMR_MR19_Msk         (0x1UL << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */\n#define EXTI_EMR_MR20_Pos         (20U)\n#define EXTI_EMR_MR20_Msk         (0x1UL << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */\n#define EXTI_EMR_MR21_Pos         (21U)\n#define EXTI_EMR_MR21_Msk         (0x1UL << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */\n#define EXTI_EMR_MR22_Pos         (22U)\n#define EXTI_EMR_MR22_Msk         (0x1UL << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */\n#define EXTI_EMR_MR23_Pos         (23U)\n#define EXTI_EMR_MR23_Msk         (0x1UL << EXTI_EMR_MR23_Pos)                  /*!< 0x00800000 */\n#define EXTI_EMR_MR23             EXTI_EMR_MR23_Msk                            /*!< Event Mask on line 23 */\n\n/* Reference Defines */\n#define  EXTI_EMR_EM0                        EXTI_EMR_MR0\n#define  EXTI_EMR_EM1                        EXTI_EMR_MR1\n#define  EXTI_EMR_EM2                        EXTI_EMR_MR2\n#define  EXTI_EMR_EM3                        EXTI_EMR_MR3\n#define  EXTI_EMR_EM4                        EXTI_EMR_MR4\n#define  EXTI_EMR_EM5                        EXTI_EMR_MR5\n#define  EXTI_EMR_EM6                        EXTI_EMR_MR6\n#define  EXTI_EMR_EM7                        EXTI_EMR_MR7\n#define  EXTI_EMR_EM8                        EXTI_EMR_MR8\n#define  EXTI_EMR_EM9                        EXTI_EMR_MR9\n#define  EXTI_EMR_EM10                       EXTI_EMR_MR10\n#define  EXTI_EMR_EM11                       EXTI_EMR_MR11\n#define  EXTI_EMR_EM12                       EXTI_EMR_MR12\n#define  EXTI_EMR_EM13                       EXTI_EMR_MR13\n#define  EXTI_EMR_EM14                       EXTI_EMR_MR14\n#define  EXTI_EMR_EM15                       EXTI_EMR_MR15\n#define  EXTI_EMR_EM16                       EXTI_EMR_MR16\n#define  EXTI_EMR_EM17                       EXTI_EMR_MR17\n#define  EXTI_EMR_EM18                       EXTI_EMR_MR18\n#define  EXTI_EMR_EM19                       EXTI_EMR_MR19\n#define  EXTI_EMR_EM20                       EXTI_EMR_MR20\n#define  EXTI_EMR_EM21                       EXTI_EMR_MR21\n#define  EXTI_EMR_EM22                       EXTI_EMR_MR22\n#define  EXTI_EMR_EM23                       EXTI_EMR_MR23\n\n/******************  Bit definition for EXTI_RTSR register  *******************/\n#define EXTI_RTSR_TR0_Pos         (0U)\n#define EXTI_RTSR_TR0_Msk         (0x1UL << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */\n#define EXTI_RTSR_TR1_Pos         (1U)\n#define EXTI_RTSR_TR1_Msk         (0x1UL << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */\n#define EXTI_RTSR_TR2_Pos         (2U)\n#define EXTI_RTSR_TR2_Msk         (0x1UL << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */\n#define EXTI_RTSR_TR3_Pos         (3U)\n#define EXTI_RTSR_TR3_Msk         (0x1UL << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */\n#define EXTI_RTSR_TR4_Pos         (4U)\n#define EXTI_RTSR_TR4_Msk         (0x1UL << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */\n#define EXTI_RTSR_TR5_Pos         (5U)\n#define EXTI_RTSR_TR5_Msk         (0x1UL << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */\n#define EXTI_RTSR_TR6_Pos         (6U)\n#define EXTI_RTSR_TR6_Msk         (0x1UL << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */\n#define EXTI_RTSR_TR7_Pos         (7U)\n#define EXTI_RTSR_TR7_Msk         (0x1UL << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */\n#define EXTI_RTSR_TR8_Pos         (8U)\n#define EXTI_RTSR_TR8_Msk         (0x1UL << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */\n#define EXTI_RTSR_TR9_Pos         (9U)\n#define EXTI_RTSR_TR9_Msk         (0x1UL << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */\n#define EXTI_RTSR_TR10_Pos        (10U)\n#define EXTI_RTSR_TR10_Msk        (0x1UL << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */\n#define EXTI_RTSR_TR11_Pos        (11U)\n#define EXTI_RTSR_TR11_Msk        (0x1UL << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */\n#define EXTI_RTSR_TR12_Pos        (12U)\n#define EXTI_RTSR_TR12_Msk        (0x1UL << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */\n#define EXTI_RTSR_TR13_Pos        (13U)\n#define EXTI_RTSR_TR13_Msk        (0x1UL << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */\n#define EXTI_RTSR_TR14_Pos        (14U)\n#define EXTI_RTSR_TR14_Msk        (0x1UL << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */\n#define EXTI_RTSR_TR15_Pos        (15U)\n#define EXTI_RTSR_TR15_Msk        (0x1UL << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */\n#define EXTI_RTSR_TR16_Pos        (16U)\n#define EXTI_RTSR_TR16_Msk        (0x1UL << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */\n#define EXTI_RTSR_TR17_Pos        (17U)\n#define EXTI_RTSR_TR17_Msk        (0x1UL << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */\n#define EXTI_RTSR_TR18_Pos        (18U)\n#define EXTI_RTSR_TR18_Msk        (0x1UL << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */\n#define EXTI_RTSR_TR19_Pos        (19U)\n#define EXTI_RTSR_TR19_Msk        (0x1UL << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */\n#define EXTI_RTSR_TR20_Pos        (20U)\n#define EXTI_RTSR_TR20_Msk        (0x1UL << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */\n#define EXTI_RTSR_TR21_Pos        (21U)\n#define EXTI_RTSR_TR21_Msk        (0x1UL << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */\n#define EXTI_RTSR_TR22_Pos        (22U)\n#define EXTI_RTSR_TR22_Msk        (0x1UL << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */\n#define EXTI_RTSR_TR23_Pos        (23U)\n#define EXTI_RTSR_TR23_Msk        (0x1UL << EXTI_RTSR_TR23_Pos)                 /*!< 0x00800000 */\n#define EXTI_RTSR_TR23            EXTI_RTSR_TR23_Msk                           /*!< Rising trigger event configuration bit of line 23 */\n\n/******************  Bit definition for EXTI_FTSR register  *******************/\n#define EXTI_FTSR_TR0_Pos         (0U)\n#define EXTI_FTSR_TR0_Msk         (0x1UL << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */\n#define EXTI_FTSR_TR1_Pos         (1U)\n#define EXTI_FTSR_TR1_Msk         (0x1UL << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */\n#define EXTI_FTSR_TR2_Pos         (2U)\n#define EXTI_FTSR_TR2_Msk         (0x1UL << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */\n#define EXTI_FTSR_TR3_Pos         (3U)\n#define EXTI_FTSR_TR3_Msk         (0x1UL << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */\n#define EXTI_FTSR_TR4_Pos         (4U)\n#define EXTI_FTSR_TR4_Msk         (0x1UL << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */\n#define EXTI_FTSR_TR5_Pos         (5U)\n#define EXTI_FTSR_TR5_Msk         (0x1UL << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */\n#define EXTI_FTSR_TR6_Pos         (6U)\n#define EXTI_FTSR_TR6_Msk         (0x1UL << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */\n#define EXTI_FTSR_TR7_Pos         (7U)\n#define EXTI_FTSR_TR7_Msk         (0x1UL << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */\n#define EXTI_FTSR_TR8_Pos         (8U)\n#define EXTI_FTSR_TR8_Msk         (0x1UL << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */\n#define EXTI_FTSR_TR9_Pos         (9U)\n#define EXTI_FTSR_TR9_Msk         (0x1UL << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */\n#define EXTI_FTSR_TR10_Pos        (10U)\n#define EXTI_FTSR_TR10_Msk        (0x1UL << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */\n#define EXTI_FTSR_TR11_Pos        (11U)\n#define EXTI_FTSR_TR11_Msk        (0x1UL << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */\n#define EXTI_FTSR_TR12_Pos        (12U)\n#define EXTI_FTSR_TR12_Msk        (0x1UL << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */\n#define EXTI_FTSR_TR13_Pos        (13U)\n#define EXTI_FTSR_TR13_Msk        (0x1UL << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */\n#define EXTI_FTSR_TR14_Pos        (14U)\n#define EXTI_FTSR_TR14_Msk        (0x1UL << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */\n#define EXTI_FTSR_TR15_Pos        (15U)\n#define EXTI_FTSR_TR15_Msk        (0x1UL << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */\n#define EXTI_FTSR_TR16_Pos        (16U)\n#define EXTI_FTSR_TR16_Msk        (0x1UL << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */\n#define EXTI_FTSR_TR17_Pos        (17U)\n#define EXTI_FTSR_TR17_Msk        (0x1UL << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */\n#define EXTI_FTSR_TR18_Pos        (18U)\n#define EXTI_FTSR_TR18_Msk        (0x1UL << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */\n#define EXTI_FTSR_TR19_Pos        (19U)\n#define EXTI_FTSR_TR19_Msk        (0x1UL << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */\n#define EXTI_FTSR_TR20_Pos        (20U)\n#define EXTI_FTSR_TR20_Msk        (0x1UL << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */\n#define EXTI_FTSR_TR21_Pos        (21U)\n#define EXTI_FTSR_TR21_Msk        (0x1UL << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */\n#define EXTI_FTSR_TR22_Pos        (22U)\n#define EXTI_FTSR_TR22_Msk        (0x1UL << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */\n#define EXTI_FTSR_TR23_Pos        (23U)\n#define EXTI_FTSR_TR23_Msk        (0x1UL << EXTI_FTSR_TR23_Pos)                 /*!< 0x00800000 */\n#define EXTI_FTSR_TR23            EXTI_FTSR_TR23_Msk                           /*!< Falling trigger event configuration bit of line 23 */\n\n/******************  Bit definition for EXTI_SWIER register  ******************/\n#define EXTI_SWIER_SWIER0_Pos     (0U)\n#define EXTI_SWIER_SWIER0_Msk     (0x1UL << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */\n#define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */\n#define EXTI_SWIER_SWIER1_Pos     (1U)\n#define EXTI_SWIER_SWIER1_Msk     (0x1UL << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */\n#define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */\n#define EXTI_SWIER_SWIER2_Pos     (2U)\n#define EXTI_SWIER_SWIER2_Msk     (0x1UL << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */\n#define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */\n#define EXTI_SWIER_SWIER3_Pos     (3U)\n#define EXTI_SWIER_SWIER3_Msk     (0x1UL << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */\n#define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */\n#define EXTI_SWIER_SWIER4_Pos     (4U)\n#define EXTI_SWIER_SWIER4_Msk     (0x1UL << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */\n#define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */\n#define EXTI_SWIER_SWIER5_Pos     (5U)\n#define EXTI_SWIER_SWIER5_Msk     (0x1UL << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */\n#define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */\n#define EXTI_SWIER_SWIER6_Pos     (6U)\n#define EXTI_SWIER_SWIER6_Msk     (0x1UL << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */\n#define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */\n#define EXTI_SWIER_SWIER7_Pos     (7U)\n#define EXTI_SWIER_SWIER7_Msk     (0x1UL << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */\n#define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */\n#define EXTI_SWIER_SWIER8_Pos     (8U)\n#define EXTI_SWIER_SWIER8_Msk     (0x1UL << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */\n#define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */\n#define EXTI_SWIER_SWIER9_Pos     (9U)\n#define EXTI_SWIER_SWIER9_Msk     (0x1UL << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */\n#define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */\n#define EXTI_SWIER_SWIER10_Pos    (10U)\n#define EXTI_SWIER_SWIER10_Msk    (0x1UL << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */\n#define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */\n#define EXTI_SWIER_SWIER11_Pos    (11U)\n#define EXTI_SWIER_SWIER11_Msk    (0x1UL << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */\n#define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */\n#define EXTI_SWIER_SWIER12_Pos    (12U)\n#define EXTI_SWIER_SWIER12_Msk    (0x1UL << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */\n#define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */\n#define EXTI_SWIER_SWIER13_Pos    (13U)\n#define EXTI_SWIER_SWIER13_Msk    (0x1UL << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */\n#define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */\n#define EXTI_SWIER_SWIER14_Pos    (14U)\n#define EXTI_SWIER_SWIER14_Msk    (0x1UL << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */\n#define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */\n#define EXTI_SWIER_SWIER15_Pos    (15U)\n#define EXTI_SWIER_SWIER15_Msk    (0x1UL << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */\n#define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */\n#define EXTI_SWIER_SWIER16_Pos    (16U)\n#define EXTI_SWIER_SWIER16_Msk    (0x1UL << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */\n#define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */\n#define EXTI_SWIER_SWIER17_Pos    (17U)\n#define EXTI_SWIER_SWIER17_Msk    (0x1UL << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */\n#define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */\n#define EXTI_SWIER_SWIER18_Pos    (18U)\n#define EXTI_SWIER_SWIER18_Msk    (0x1UL << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */\n#define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */\n#define EXTI_SWIER_SWIER19_Pos    (19U)\n#define EXTI_SWIER_SWIER19_Msk    (0x1UL << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */\n#define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */\n#define EXTI_SWIER_SWIER20_Pos    (20U)\n#define EXTI_SWIER_SWIER20_Msk    (0x1UL << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */\n#define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */\n#define EXTI_SWIER_SWIER21_Pos    (21U)\n#define EXTI_SWIER_SWIER21_Msk    (0x1UL << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */\n#define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */\n#define EXTI_SWIER_SWIER22_Pos    (22U)\n#define EXTI_SWIER_SWIER22_Msk    (0x1UL << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */\n#define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */\n#define EXTI_SWIER_SWIER23_Pos    (23U)\n#define EXTI_SWIER_SWIER23_Msk    (0x1UL << EXTI_SWIER_SWIER23_Pos)             /*!< 0x00800000 */\n#define EXTI_SWIER_SWIER23        EXTI_SWIER_SWIER23_Msk                       /*!< Software Interrupt on line 23 */\n\n/*******************  Bit definition for EXTI_PR register  ********************/\n#define EXTI_PR_PR0_Pos           (0U)\n#define EXTI_PR_PR0_Msk           (0x1UL << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */\n#define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */\n#define EXTI_PR_PR1_Pos           (1U)\n#define EXTI_PR_PR1_Msk           (0x1UL << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */\n#define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */\n#define EXTI_PR_PR2_Pos           (2U)\n#define EXTI_PR_PR2_Msk           (0x1UL << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */\n#define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */\n#define EXTI_PR_PR3_Pos           (3U)\n#define EXTI_PR_PR3_Msk           (0x1UL << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */\n#define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */\n#define EXTI_PR_PR4_Pos           (4U)\n#define EXTI_PR_PR4_Msk           (0x1UL << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */\n#define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */\n#define EXTI_PR_PR5_Pos           (5U)\n#define EXTI_PR_PR5_Msk           (0x1UL << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */\n#define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */\n#define EXTI_PR_PR6_Pos           (6U)\n#define EXTI_PR_PR6_Msk           (0x1UL << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */\n#define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */\n#define EXTI_PR_PR7_Pos           (7U)\n#define EXTI_PR_PR7_Msk           (0x1UL << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */\n#define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */\n#define EXTI_PR_PR8_Pos           (8U)\n#define EXTI_PR_PR8_Msk           (0x1UL << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */\n#define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */\n#define EXTI_PR_PR9_Pos           (9U)\n#define EXTI_PR_PR9_Msk           (0x1UL << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */\n#define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */\n#define EXTI_PR_PR10_Pos          (10U)\n#define EXTI_PR_PR10_Msk          (0x1UL << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */\n#define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */\n#define EXTI_PR_PR11_Pos          (11U)\n#define EXTI_PR_PR11_Msk          (0x1UL << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */\n#define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */\n#define EXTI_PR_PR12_Pos          (12U)\n#define EXTI_PR_PR12_Msk          (0x1UL << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */\n#define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */\n#define EXTI_PR_PR13_Pos          (13U)\n#define EXTI_PR_PR13_Msk          (0x1UL << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */\n#define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */\n#define EXTI_PR_PR14_Pos          (14U)\n#define EXTI_PR_PR14_Msk          (0x1UL << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */\n#define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */\n#define EXTI_PR_PR15_Pos          (15U)\n#define EXTI_PR_PR15_Msk          (0x1UL << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */\n#define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */\n#define EXTI_PR_PR16_Pos          (16U)\n#define EXTI_PR_PR16_Msk          (0x1UL << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */\n#define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */\n#define EXTI_PR_PR17_Pos          (17U)\n#define EXTI_PR_PR17_Msk          (0x1UL << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */\n#define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */\n#define EXTI_PR_PR18_Pos          (18U)\n#define EXTI_PR_PR18_Msk          (0x1UL << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */\n#define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */\n#define EXTI_PR_PR19_Pos          (19U)\n#define EXTI_PR_PR19_Msk          (0x1UL << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */\n#define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */\n#define EXTI_PR_PR20_Pos          (20U)\n#define EXTI_PR_PR20_Msk          (0x1UL << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */\n#define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */\n#define EXTI_PR_PR21_Pos          (21U)\n#define EXTI_PR_PR21_Msk          (0x1UL << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */\n#define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */\n#define EXTI_PR_PR22_Pos          (22U)\n#define EXTI_PR_PR22_Msk          (0x1UL << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */\n#define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */\n#define EXTI_PR_PR23_Pos          (23U)\n#define EXTI_PR_PR23_Msk          (0x1UL << EXTI_PR_PR23_Pos)                   /*!< 0x00800000 */\n#define EXTI_PR_PR23              EXTI_PR_PR23_Msk                             /*!< Pending bit for line 23 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    FLASH                                   */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bits definition for FLASH_ACR register  *****************/\n#define FLASH_ACR_LATENCY_Pos          (0U)\n#define FLASH_ACR_LATENCY_Msk          (0xFUL << FLASH_ACR_LATENCY_Pos)         /*!< 0x0000000F */\n#define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk\n#define FLASH_ACR_LATENCY_0WS          0x00000000U\n#define FLASH_ACR_LATENCY_1WS          0x00000001U\n#define FLASH_ACR_LATENCY_2WS          0x00000002U\n#define FLASH_ACR_LATENCY_3WS          0x00000003U\n#define FLASH_ACR_LATENCY_4WS          0x00000004U\n#define FLASH_ACR_LATENCY_5WS          0x00000005U\n#define FLASH_ACR_LATENCY_6WS          0x00000006U\n#define FLASH_ACR_LATENCY_7WS          0x00000007U\n\n#define FLASH_ACR_PRFTEN_Pos           (8U)\n#define FLASH_ACR_PRFTEN_Msk           (0x1UL << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */\n#define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk\n#define FLASH_ACR_ICEN_Pos             (9U)\n#define FLASH_ACR_ICEN_Msk             (0x1UL << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */\n#define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk\n#define FLASH_ACR_DCEN_Pos             (10U)\n#define FLASH_ACR_DCEN_Msk             (0x1UL << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */\n#define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk\n#define FLASH_ACR_ICRST_Pos            (11U)\n#define FLASH_ACR_ICRST_Msk            (0x1UL << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */\n#define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk\n#define FLASH_ACR_DCRST_Pos            (12U)\n#define FLASH_ACR_DCRST_Msk            (0x1UL << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */\n#define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk\n#define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)\n#define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */\n#define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk\n#define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)\n#define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */\n#define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk\n\n/*******************  Bits definition for FLASH_SR register  ******************/\n#define FLASH_SR_EOP_Pos               (0U)\n#define FLASH_SR_EOP_Msk               (0x1UL << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */\n#define FLASH_SR_EOP                   FLASH_SR_EOP_Msk\n#define FLASH_SR_SOP_Pos               (1U)\n#define FLASH_SR_SOP_Msk               (0x1UL << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */\n#define FLASH_SR_SOP                   FLASH_SR_SOP_Msk\n#define FLASH_SR_WRPERR_Pos            (4U)\n#define FLASH_SR_WRPERR_Msk            (0x1UL << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */\n#define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk\n#define FLASH_SR_PGAERR_Pos            (5U)\n#define FLASH_SR_PGAERR_Msk            (0x1UL << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */\n#define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk\n#define FLASH_SR_PGPERR_Pos            (6U)\n#define FLASH_SR_PGPERR_Msk            (0x1UL << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */\n#define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk\n#define FLASH_SR_PGSERR_Pos            (7U)\n#define FLASH_SR_PGSERR_Msk            (0x1UL << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */\n#define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk\n#define FLASH_SR_RDERR_Pos            (8U)\n#define FLASH_SR_RDERR_Msk            (0x1UL << FLASH_SR_RDERR_Pos)             /*!< 0x00000100 */\n#define FLASH_SR_RDERR                FLASH_SR_RDERR_Msk\n#define FLASH_SR_BSY_Pos               (16U)\n#define FLASH_SR_BSY_Msk               (0x1UL << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */\n#define FLASH_SR_BSY                   FLASH_SR_BSY_Msk\n\n/*******************  Bits definition for FLASH_CR register  ******************/\n#define FLASH_CR_PG_Pos                (0U)\n#define FLASH_CR_PG_Msk                (0x1UL << FLASH_CR_PG_Pos)               /*!< 0x00000001 */\n#define FLASH_CR_PG                    FLASH_CR_PG_Msk\n#define FLASH_CR_SER_Pos               (1U)\n#define FLASH_CR_SER_Msk               (0x1UL << FLASH_CR_SER_Pos)              /*!< 0x00000002 */\n#define FLASH_CR_SER                   FLASH_CR_SER_Msk\n#define FLASH_CR_MER_Pos               (2U)\n#define FLASH_CR_MER_Msk               (0x1UL << FLASH_CR_MER_Pos)              /*!< 0x00000004 */\n#define FLASH_CR_MER                   FLASH_CR_MER_Msk\n#define FLASH_CR_SNB_Pos               (3U)\n#define FLASH_CR_SNB_Msk               (0x0FUL << FLASH_CR_SNB_Pos)             /*!< 0x00000078 */\n#define FLASH_CR_SNB                   FLASH_CR_SNB_Msk\n#define FLASH_CR_SNB_0                 (0x01UL << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */\n#define FLASH_CR_SNB_1                 (0x02UL << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */\n#define FLASH_CR_SNB_2                 (0x04UL << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */\n#define FLASH_CR_SNB_3                 (0x08UL << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */\n#define FLASH_CR_PSIZE_Pos             (8U)\n#define FLASH_CR_PSIZE_Msk             (0x3UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */\n#define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk\n#define FLASH_CR_PSIZE_0               (0x1UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */\n#define FLASH_CR_PSIZE_1               (0x2UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */\n#define FLASH_CR_STRT_Pos              (16U)\n#define FLASH_CR_STRT_Msk              (0x1UL << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */\n#define FLASH_CR_STRT                  FLASH_CR_STRT_Msk\n#define FLASH_CR_EOPIE_Pos             (24U)\n#define FLASH_CR_EOPIE_Msk             (0x1UL << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */\n#define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk\n#define FLASH_CR_LOCK_Pos              (31U)\n#define FLASH_CR_LOCK_Msk              (0x1UL << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */\n#define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk\n\n/*******************  Bits definition for FLASH_OPTCR register  ***************/\n#define FLASH_OPTCR_OPTLOCK_Pos        (0U)\n#define FLASH_OPTCR_OPTLOCK_Msk        (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */\n#define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk\n#define FLASH_OPTCR_OPTSTRT_Pos        (1U)\n#define FLASH_OPTCR_OPTSTRT_Msk        (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */\n#define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk\n\n#define FLASH_OPTCR_BOR_LEV_0          0x00000004U\n#define FLASH_OPTCR_BOR_LEV_1          0x00000008U\n#define FLASH_OPTCR_BOR_LEV_Pos        (2U)\n#define FLASH_OPTCR_BOR_LEV_Msk        (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */\n#define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk\n#define FLASH_OPTCR_WDG_SW_Pos         (5U)\n#define FLASH_OPTCR_WDG_SW_Msk         (0x1UL << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */\n#define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk\n#define FLASH_OPTCR_nRST_STOP_Pos      (6U)\n#define FLASH_OPTCR_nRST_STOP_Msk      (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */\n#define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk\n#define FLASH_OPTCR_nRST_STDBY_Pos     (7U)\n#define FLASH_OPTCR_nRST_STDBY_Msk     (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */\n#define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk\n#define FLASH_OPTCR_RDP_Pos            (8U)\n#define FLASH_OPTCR_RDP_Msk            (0xFFUL << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */\n#define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk\n#define FLASH_OPTCR_RDP_0              (0x01UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */\n#define FLASH_OPTCR_RDP_1              (0x02UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */\n#define FLASH_OPTCR_RDP_2              (0x04UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */\n#define FLASH_OPTCR_RDP_3              (0x08UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */\n#define FLASH_OPTCR_RDP_4              (0x10UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */\n#define FLASH_OPTCR_RDP_5              (0x20UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */\n#define FLASH_OPTCR_RDP_6              (0x40UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */\n#define FLASH_OPTCR_RDP_7              (0x80UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */\n#define FLASH_OPTCR_nWRP_Pos           (16U)\n#define FLASH_OPTCR_nWRP_Msk           (0x7FFFUL << FLASH_OPTCR_nWRP_Pos)       /*!< 0x7FFF0000 */\n#define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk\n#define FLASH_OPTCR_nWRP_0             0x00010000U\n#define FLASH_OPTCR_nWRP_1             0x00020000U\n#define FLASH_OPTCR_nWRP_2             0x00040000U\n#define FLASH_OPTCR_nWRP_3             0x00080000U\n#define FLASH_OPTCR_nWRP_4             0x00100000U\n#define FLASH_OPTCR_nWRP_5             0x00200000U\n#define FLASH_OPTCR_nWRP_6             0x00400000U\n#define FLASH_OPTCR_nWRP_7             0x00800000U\n#define FLASH_OPTCR_nWRP_8             0x01000000U\n#define FLASH_OPTCR_nWRP_9             0x02000000U\n#define FLASH_OPTCR_nWRP_10            0x04000000U\n#define FLASH_OPTCR_nWRP_11            0x08000000U\n#define FLASH_OPTCR_nWRP_12            0x10000000U\n#define FLASH_OPTCR_nWRP_13            0x20000000U\n#define FLASH_OPTCR_nWRP_14            0x40000000U\n#define FLASH_OPTCR_nWRP_15            0x40000000U\n\n/******************  Bits definition for FLASH_OPTCR1 register  ***************/\n#define FLASH_OPTCR1_nWRP_Pos          (16U)\n#define FLASH_OPTCR1_nWRP_Msk          (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */\n#define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk\n#define FLASH_OPTCR1_nWRP_0            (0x001UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */\n#define FLASH_OPTCR1_nWRP_1            (0x002UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */\n#define FLASH_OPTCR1_nWRP_2            (0x004UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */\n#define FLASH_OPTCR1_nWRP_3            (0x008UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */\n#define FLASH_OPTCR1_nWRP_4            (0x010UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */\n#define FLASH_OPTCR1_nWRP_5            (0x020UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */\n#define FLASH_OPTCR1_nWRP_6            (0x040UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */\n#define FLASH_OPTCR1_nWRP_7            (0x080UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */\n#define FLASH_OPTCR1_nWRP_8            (0x100UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */\n#define FLASH_OPTCR1_nWRP_9            (0x200UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */\n#define FLASH_OPTCR1_nWRP_10           (0x400UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */\n#define FLASH_OPTCR1_nWRP_11           (0x800UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                   Flexible Static Memory Controller                        */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for FSMC_BCR1 register  *******************/\n#define FSMC_BCR1_MBKEN_Pos          (0U)\n#define FSMC_BCR1_MBKEN_Msk          (0x1UL << FSMC_BCR1_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR1_MBKEN              FSMC_BCR1_MBKEN_Msk                       /*!<Memory bank enable bit                 */\n#define FSMC_BCR1_MUXEN_Pos          (1U)\n#define FSMC_BCR1_MUXEN_Msk          (0x1UL << FSMC_BCR1_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR1_MUXEN              FSMC_BCR1_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR1_MTYP_Pos           (2U)\n#define FSMC_BCR1_MTYP_Msk           (0x3UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR1_MTYP               FSMC_BCR1_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR1_MTYP_0             (0x1UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR1_MTYP_1             (0x2UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR1_MWID_Pos           (4U)\n#define FSMC_BCR1_MWID_Msk           (0x3UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR1_MWID               FSMC_BCR1_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR1_MWID_0             (0x1UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR1_MWID_1             (0x2UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR1_FACCEN_Pos         (6U)\n#define FSMC_BCR1_FACCEN_Msk         (0x1UL << FSMC_BCR1_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR1_FACCEN             FSMC_BCR1_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR1_BURSTEN_Pos        (8U)\n#define FSMC_BCR1_BURSTEN_Msk        (0x1UL << FSMC_BCR1_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR1_BURSTEN            FSMC_BCR1_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR1_WAITPOL_Pos        (9U)\n#define FSMC_BCR1_WAITPOL_Msk        (0x1UL << FSMC_BCR1_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR1_WAITPOL            FSMC_BCR1_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR1_WAITCFG_Pos        (11U)\n#define FSMC_BCR1_WAITCFG_Msk        (0x1UL << FSMC_BCR1_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR1_WAITCFG            FSMC_BCR1_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR1_WREN_Pos           (12U)\n#define FSMC_BCR1_WREN_Msk           (0x1UL << FSMC_BCR1_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR1_WREN               FSMC_BCR1_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR1_WAITEN_Pos         (13U)\n#define FSMC_BCR1_WAITEN_Msk         (0x1UL << FSMC_BCR1_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR1_WAITEN             FSMC_BCR1_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR1_EXTMOD_Pos         (14U)\n#define FSMC_BCR1_EXTMOD_Msk         (0x1UL << FSMC_BCR1_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR1_EXTMOD             FSMC_BCR1_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR1_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR1_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR1_ASYNCWAIT          FSMC_BCR1_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR1_CPSIZE_Pos         (16U)\n#define FSMC_BCR1_CPSIZE_Msk         (0x7UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR1_CPSIZE             FSMC_BCR1_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR1_CPSIZE_0           (0x1UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR1_CPSIZE_1           (0x2UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR1_CPSIZE_2           (0x4UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR1_CBURSTRW_Pos       (19U)\n#define FSMC_BCR1_CBURSTRW_Msk       (0x1UL << FSMC_BCR1_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR1_CBURSTRW           FSMC_BCR1_CBURSTRW_Msk                    /*!<Write burst enable                     */\n#define FSMC_BCR1_CCLKEN_Pos         (20U)\n#define FSMC_BCR1_CCLKEN_Msk         (0x1UL << FSMC_BCR1_CCLKEN_Pos)            /*!< 0x00100000 */\n#define FSMC_BCR1_CCLKEN             FSMC_BCR1_CCLKEN_Msk                      /*!<Continous clock enable     */\n#define FSMC_BCR1_WFDIS_Pos          (21U)\n#define FSMC_BCR1_WFDIS_Msk          (0x1UL << FSMC_BCR1_WFDIS_Pos)             /*!< 0x00200000 */\n#define FSMC_BCR1_WFDIS              FSMC_BCR1_WFDIS_Msk                       /*!<Write FIFO Disable         */\n\n/******************  Bit definition for FSMC_BCR2 register  *******************/\n#define FSMC_BCR2_MBKEN_Pos          (0U)\n#define FSMC_BCR2_MBKEN_Msk          (0x1UL << FSMC_BCR2_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR2_MBKEN              FSMC_BCR2_MBKEN_Msk                       /*!<Memory bank enable bit                */\n#define FSMC_BCR2_MUXEN_Pos          (1U)\n#define FSMC_BCR2_MUXEN_Msk          (0x1UL << FSMC_BCR2_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR2_MUXEN              FSMC_BCR2_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR2_MTYP_Pos           (2U)\n#define FSMC_BCR2_MTYP_Msk           (0x3UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR2_MTYP               FSMC_BCR2_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR2_MTYP_0             (0x1UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR2_MTYP_1             (0x2UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR2_MWID_Pos           (4U)\n#define FSMC_BCR2_MWID_Msk           (0x3UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR2_MWID               FSMC_BCR2_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR2_MWID_0             (0x1UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR2_MWID_1             (0x2UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR2_FACCEN_Pos         (6U)\n#define FSMC_BCR2_FACCEN_Msk         (0x1UL << FSMC_BCR2_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR2_FACCEN             FSMC_BCR2_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR2_BURSTEN_Pos        (8U)\n#define FSMC_BCR2_BURSTEN_Msk        (0x1UL << FSMC_BCR2_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR2_BURSTEN            FSMC_BCR2_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR2_WAITPOL_Pos        (9U)\n#define FSMC_BCR2_WAITPOL_Msk        (0x1UL << FSMC_BCR2_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR2_WAITPOL            FSMC_BCR2_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR2_WAITCFG_Pos        (11U)\n#define FSMC_BCR2_WAITCFG_Msk        (0x1UL << FSMC_BCR2_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR2_WAITCFG            FSMC_BCR2_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR2_WREN_Pos           (12U)\n#define FSMC_BCR2_WREN_Msk           (0x1UL << FSMC_BCR2_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR2_WREN               FSMC_BCR2_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR2_WAITEN_Pos         (13U)\n#define FSMC_BCR2_WAITEN_Msk         (0x1UL << FSMC_BCR2_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR2_WAITEN             FSMC_BCR2_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR2_EXTMOD_Pos         (14U)\n#define FSMC_BCR2_EXTMOD_Msk         (0x1UL << FSMC_BCR2_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR2_EXTMOD             FSMC_BCR2_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR2_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR2_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR2_ASYNCWAIT          FSMC_BCR2_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR2_CPSIZE_Pos         (16U)\n#define FSMC_BCR2_CPSIZE_Msk         (0x7UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR2_CPSIZE             FSMC_BCR2_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR2_CPSIZE_0           (0x1UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR2_CPSIZE_1           (0x2UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR2_CPSIZE_2           (0x4UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR2_CBURSTRW_Pos       (19U)\n#define FSMC_BCR2_CBURSTRW_Msk       (0x1UL << FSMC_BCR2_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR2_CBURSTRW           FSMC_BCR2_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BCR3 register  *******************/\n#define FSMC_BCR3_MBKEN_Pos          (0U)\n#define FSMC_BCR3_MBKEN_Msk          (0x1UL << FSMC_BCR3_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR3_MBKEN              FSMC_BCR3_MBKEN_Msk                       /*!<Memory bank enable bit                 */\n#define FSMC_BCR3_MUXEN_Pos          (1U)\n#define FSMC_BCR3_MUXEN_Msk          (0x1UL << FSMC_BCR3_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR3_MUXEN              FSMC_BCR3_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR3_MTYP_Pos           (2U)\n#define FSMC_BCR3_MTYP_Msk           (0x3UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR3_MTYP               FSMC_BCR3_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR3_MTYP_0             (0x1UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR3_MTYP_1             (0x2UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR3_MWID_Pos           (4U)\n#define FSMC_BCR3_MWID_Msk           (0x3UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR3_MWID               FSMC_BCR3_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR3_MWID_0             (0x1UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR3_MWID_1             (0x2UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR3_FACCEN_Pos         (6U)\n#define FSMC_BCR3_FACCEN_Msk         (0x1UL << FSMC_BCR3_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR3_FACCEN             FSMC_BCR3_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR3_BURSTEN_Pos        (8U)\n#define FSMC_BCR3_BURSTEN_Msk        (0x1UL << FSMC_BCR3_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR3_BURSTEN            FSMC_BCR3_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR3_WAITPOL_Pos        (9U)\n#define FSMC_BCR3_WAITPOL_Msk        (0x1UL << FSMC_BCR3_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR3_WAITPOL            FSMC_BCR3_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR3_WAITCFG_Pos        (11U)\n#define FSMC_BCR3_WAITCFG_Msk        (0x1UL << FSMC_BCR3_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR3_WAITCFG            FSMC_BCR3_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR3_WREN_Pos           (12U)\n#define FSMC_BCR3_WREN_Msk           (0x1UL << FSMC_BCR3_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR3_WREN               FSMC_BCR3_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR3_WAITEN_Pos         (13U)\n#define FSMC_BCR3_WAITEN_Msk         (0x1UL << FSMC_BCR3_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR3_WAITEN             FSMC_BCR3_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR3_EXTMOD_Pos         (14U)\n#define FSMC_BCR3_EXTMOD_Msk         (0x1UL << FSMC_BCR3_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR3_EXTMOD             FSMC_BCR3_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR3_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR3_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR3_ASYNCWAIT          FSMC_BCR3_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR3_CPSIZE_Pos         (16U)\n#define FSMC_BCR3_CPSIZE_Msk         (0x7UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR3_CPSIZE             FSMC_BCR3_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR3_CPSIZE_0           (0x1UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR3_CPSIZE_1           (0x2UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR3_CPSIZE_2           (0x4UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR3_CBURSTRW_Pos       (19U)\n#define FSMC_BCR3_CBURSTRW_Msk       (0x1UL << FSMC_BCR3_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR3_CBURSTRW           FSMC_BCR3_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BCR4 register  *******************/\n#define FSMC_BCR4_MBKEN_Pos          (0U)\n#define FSMC_BCR4_MBKEN_Msk          (0x1UL << FSMC_BCR4_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR4_MBKEN              FSMC_BCR4_MBKEN_Msk                       /*!<Memory bank enable bit */\n#define FSMC_BCR4_MUXEN_Pos          (1U)\n#define FSMC_BCR4_MUXEN_Msk          (0x1UL << FSMC_BCR4_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR4_MUXEN              FSMC_BCR4_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR4_MTYP_Pos           (2U)\n#define FSMC_BCR4_MTYP_Msk           (0x3UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR4_MTYP               FSMC_BCR4_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR4_MTYP_0             (0x1UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR4_MTYP_1             (0x2UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR4_MWID_Pos           (4U)\n#define FSMC_BCR4_MWID_Msk           (0x3UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR4_MWID               FSMC_BCR4_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR4_MWID_0             (0x1UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR4_MWID_1             (0x2UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR4_FACCEN_Pos         (6U)\n#define FSMC_BCR4_FACCEN_Msk         (0x1UL << FSMC_BCR4_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR4_FACCEN             FSMC_BCR4_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR4_BURSTEN_Pos        (8U)\n#define FSMC_BCR4_BURSTEN_Msk        (0x1UL << FSMC_BCR4_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR4_BURSTEN            FSMC_BCR4_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR4_WAITPOL_Pos        (9U)\n#define FSMC_BCR4_WAITPOL_Msk        (0x1UL << FSMC_BCR4_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR4_WAITPOL            FSMC_BCR4_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR4_WAITCFG_Pos        (11U)\n#define FSMC_BCR4_WAITCFG_Msk        (0x1UL << FSMC_BCR4_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR4_WAITCFG            FSMC_BCR4_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR4_WREN_Pos           (12U)\n#define FSMC_BCR4_WREN_Msk           (0x1UL << FSMC_BCR4_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR4_WREN               FSMC_BCR4_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR4_WAITEN_Pos         (13U)\n#define FSMC_BCR4_WAITEN_Msk         (0x1UL << FSMC_BCR4_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR4_WAITEN             FSMC_BCR4_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR4_EXTMOD_Pos         (14U)\n#define FSMC_BCR4_EXTMOD_Msk         (0x1UL << FSMC_BCR4_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR4_EXTMOD             FSMC_BCR4_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR4_ASYNCWAIT_Pos      (15U)\n#define FSMC_BCR4_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR4_ASYNCWAIT          FSMC_BCR4_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR4_CPSIZE_Pos         (16U)\n#define FSMC_BCR4_CPSIZE_Msk         (0x7UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR4_CPSIZE             FSMC_BCR4_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR4_CPSIZE_0           (0x1UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR4_CPSIZE_1           (0x2UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR4_CPSIZE_2           (0x4UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR4_CBURSTRW_Pos       (19U)\n#define FSMC_BCR4_CBURSTRW_Msk       (0x1UL << FSMC_BCR4_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR4_CBURSTRW           FSMC_BCR4_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BTR1 register  ******************/\n#define FSMC_BTR1_ADDSET_Pos         (0U)\n#define FSMC_BTR1_ADDSET_Msk         (0xFUL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR1_ADDSET             FSMC_BTR1_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR1_ADDSET_0           (0x1UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR1_ADDSET_1           (0x2UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR1_ADDSET_2           (0x4UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR1_ADDSET_3           (0x8UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR1_ADDHLD_Pos         (4U)\n#define FSMC_BTR1_ADDHLD_Msk         (0xFUL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR1_ADDHLD             FSMC_BTR1_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR1_ADDHLD_0           (0x1UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR1_ADDHLD_1           (0x2UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR1_ADDHLD_2           (0x4UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR1_ADDHLD_3           (0x8UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR1_DATAST_Pos         (8U)\n#define FSMC_BTR1_DATAST_Msk         (0xFFUL << FSMC_BTR1_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR1_DATAST             FSMC_BTR1_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR1_DATAST_0           (0x01UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR1_DATAST_1           (0x02UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR1_DATAST_2           (0x04UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR1_DATAST_3           (0x08UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR1_DATAST_4           (0x10UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR1_DATAST_5           (0x20UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR1_DATAST_6           (0x40UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR1_DATAST_7           (0x80UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR1_BUSTURN_Pos        (16U)\n#define FSMC_BTR1_BUSTURN_Msk        (0xFUL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR1_BUSTURN            FSMC_BTR1_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR1_BUSTURN_0          (0x1UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR1_BUSTURN_1          (0x2UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR1_BUSTURN_2          (0x4UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR1_BUSTURN_3          (0x8UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR1_CLKDIV_Pos         (20U)\n#define FSMC_BTR1_CLKDIV_Msk         (0xFUL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR1_CLKDIV             FSMC_BTR1_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR1_CLKDIV_0           (0x1UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR1_CLKDIV_1           (0x2UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR1_CLKDIV_2           (0x4UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR1_CLKDIV_3           (0x8UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR1_DATLAT_Pos         (24U)\n#define FSMC_BTR1_DATLAT_Msk         (0xFUL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR1_DATLAT             FSMC_BTR1_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR1_DATLAT_0           (0x1UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR1_DATLAT_1           (0x2UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR1_DATLAT_2           (0x4UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR1_DATLAT_3           (0x8UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR1_ACCMOD_Pos         (28U)\n#define FSMC_BTR1_ACCMOD_Msk         (0x3UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR1_ACCMOD             FSMC_BTR1_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR1_ACCMOD_0           (0x1UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR1_ACCMOD_1           (0x2UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BTR2 register  *******************/\n#define FSMC_BTR2_ADDSET_Pos         (0U)\n#define FSMC_BTR2_ADDSET_Msk         (0xFUL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR2_ADDSET             FSMC_BTR2_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR2_ADDSET_0           (0x1UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR2_ADDSET_1           (0x2UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR2_ADDSET_2           (0x4UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR2_ADDSET_3           (0x8UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR2_ADDHLD_Pos         (4U)\n#define FSMC_BTR2_ADDHLD_Msk         (0xFUL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR2_ADDHLD             FSMC_BTR2_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR2_ADDHLD_0           (0x1UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR2_ADDHLD_1           (0x2UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR2_ADDHLD_2           (0x4UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR2_ADDHLD_3           (0x8UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR2_DATAST_Pos         (8U)\n#define FSMC_BTR2_DATAST_Msk         (0xFFUL << FSMC_BTR2_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR2_DATAST             FSMC_BTR2_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR2_DATAST_0           (0x01UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR2_DATAST_1           (0x02UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR2_DATAST_2           (0x04UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR2_DATAST_3           (0x08UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR2_DATAST_4           (0x10UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR2_DATAST_5           (0x20UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR2_DATAST_6           (0x40UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR2_DATAST_7           (0x80UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR2_BUSTURN_Pos        (16U)\n#define FSMC_BTR2_BUSTURN_Msk        (0xFUL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR2_BUSTURN            FSMC_BTR2_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR2_BUSTURN_0          (0x1UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR2_BUSTURN_1          (0x2UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR2_BUSTURN_2          (0x4UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR2_BUSTURN_3          (0x8UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR2_CLKDIV_Pos         (20U)\n#define FSMC_BTR2_CLKDIV_Msk         (0xFUL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR2_CLKDIV             FSMC_BTR2_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR2_CLKDIV_0           (0x1UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR2_CLKDIV_1           (0x2UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR2_CLKDIV_2           (0x4UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR2_CLKDIV_3           (0x8UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR2_DATLAT_Pos         (24U)\n#define FSMC_BTR2_DATLAT_Msk         (0xFUL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR2_DATLAT             FSMC_BTR2_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR2_DATLAT_0           (0x1UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR2_DATLAT_1           (0x2UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR2_DATLAT_2           (0x4UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR2_DATLAT_3           (0x8UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR2_ACCMOD_Pos         (28U)\n#define FSMC_BTR2_ACCMOD_Msk         (0x3UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR2_ACCMOD             FSMC_BTR2_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR2_ACCMOD_0           (0x1UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR2_ACCMOD_1           (0x2UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/*******************  Bit definition for FSMC_BTR3 register  *******************/\n#define FSMC_BTR3_ADDSET_Pos         (0U)\n#define FSMC_BTR3_ADDSET_Msk         (0xFUL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR3_ADDSET             FSMC_BTR3_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR3_ADDSET_0           (0x1UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR3_ADDSET_1           (0x2UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR3_ADDSET_2           (0x4UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR3_ADDSET_3           (0x8UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR3_ADDHLD_Pos         (4U)\n#define FSMC_BTR3_ADDHLD_Msk         (0xFUL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR3_ADDHLD             FSMC_BTR3_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR3_ADDHLD_0           (0x1UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR3_ADDHLD_1           (0x2UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR3_ADDHLD_2           (0x4UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR3_ADDHLD_3           (0x8UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR3_DATAST_Pos         (8U)\n#define FSMC_BTR3_DATAST_Msk         (0xFFUL << FSMC_BTR3_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR3_DATAST             FSMC_BTR3_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR3_DATAST_0           (0x01UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR3_DATAST_1           (0x02UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR3_DATAST_2           (0x04UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR3_DATAST_3           (0x08UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR3_DATAST_4           (0x10UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR3_DATAST_5           (0x20UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR3_DATAST_6           (0x40UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR3_DATAST_7           (0x80UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR3_BUSTURN_Pos        (16U)\n#define FSMC_BTR3_BUSTURN_Msk        (0xFUL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR3_BUSTURN            FSMC_BTR3_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR3_BUSTURN_0          (0x1UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR3_BUSTURN_1          (0x2UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR3_BUSTURN_2          (0x4UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR3_BUSTURN_3          (0x8UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR3_CLKDIV_Pos         (20U)\n#define FSMC_BTR3_CLKDIV_Msk         (0xFUL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR3_CLKDIV             FSMC_BTR3_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR3_CLKDIV_0           (0x1UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR3_CLKDIV_1           (0x2UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR3_CLKDIV_2           (0x4UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR3_CLKDIV_3           (0x8UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR3_DATLAT_Pos         (24U)\n#define FSMC_BTR3_DATLAT_Msk         (0xFUL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR3_DATLAT             FSMC_BTR3_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR3_DATLAT_0           (0x1UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR3_DATLAT_1           (0x2UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR3_DATLAT_2           (0x4UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR3_DATLAT_3           (0x8UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR3_ACCMOD_Pos         (28U)\n#define FSMC_BTR3_ACCMOD_Msk         (0x3UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR3_ACCMOD             FSMC_BTR3_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR3_ACCMOD_0           (0x1UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR3_ACCMOD_1           (0x2UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BTR4 register  *******************/\n#define FSMC_BTR4_ADDSET_Pos         (0U)\n#define FSMC_BTR4_ADDSET_Msk         (0xFUL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR4_ADDSET             FSMC_BTR4_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR4_ADDSET_0           (0x1UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR4_ADDSET_1           (0x2UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR4_ADDSET_2           (0x4UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR4_ADDSET_3           (0x8UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR4_ADDHLD_Pos         (4U)\n#define FSMC_BTR4_ADDHLD_Msk         (0xFUL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR4_ADDHLD             FSMC_BTR4_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR4_ADDHLD_0           (0x1UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR4_ADDHLD_1           (0x2UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR4_ADDHLD_2           (0x4UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR4_ADDHLD_3           (0x8UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR4_DATAST_Pos         (8U)\n#define FSMC_BTR4_DATAST_Msk         (0xFFUL << FSMC_BTR4_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR4_DATAST             FSMC_BTR4_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR4_DATAST_0           (0x01UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR4_DATAST_1           (0x02UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR4_DATAST_2           (0x04UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR4_DATAST_3           (0x08UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR4_DATAST_4           (0x10UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR4_DATAST_5           (0x20UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR4_DATAST_6           (0x40UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR4_DATAST_7           (0x80UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR4_BUSTURN_Pos        (16U)\n#define FSMC_BTR4_BUSTURN_Msk        (0xFUL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR4_BUSTURN            FSMC_BTR4_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR4_BUSTURN_0          (0x1UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR4_BUSTURN_1          (0x2UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR4_BUSTURN_2          (0x4UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR4_BUSTURN_3          (0x8UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR4_CLKDIV_Pos         (20U)\n#define FSMC_BTR4_CLKDIV_Msk         (0xFUL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR4_CLKDIV             FSMC_BTR4_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR4_CLKDIV_0           (0x1UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR4_CLKDIV_1           (0x2UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR4_CLKDIV_2           (0x4UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR4_CLKDIV_3           (0x8UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR4_DATLAT_Pos         (24U)\n#define FSMC_BTR4_DATLAT_Msk         (0xFUL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR4_DATLAT             FSMC_BTR4_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR4_DATLAT_0           (0x1UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR4_DATLAT_1           (0x2UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR4_DATLAT_2           (0x4UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR4_DATLAT_3           (0x8UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR4_ACCMOD_Pos         (28U)\n#define FSMC_BTR4_ACCMOD_Msk         (0x3UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR4_ACCMOD             FSMC_BTR4_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR4_ACCMOD_0           (0x1UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR4_ACCMOD_1           (0x2UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR1 register  ******************/\n#define FSMC_BWTR1_ADDSET_Pos        (0U)\n#define FSMC_BWTR1_ADDSET_Msk        (0xFUL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR1_ADDSET            FSMC_BWTR1_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR1_ADDSET_0          (0x1UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR1_ADDSET_1          (0x2UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR1_ADDSET_2          (0x4UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR1_ADDSET_3          (0x8UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR1_ADDHLD_Pos        (4U)\n#define FSMC_BWTR1_ADDHLD_Msk        (0xFUL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR1_ADDHLD            FSMC_BWTR1_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR1_ADDHLD_0          (0x1UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR1_ADDHLD_1          (0x2UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR1_ADDHLD_2          (0x4UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR1_ADDHLD_3          (0x8UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR1_DATAST_Pos        (8U)\n#define FSMC_BWTR1_DATAST_Msk        (0xFFUL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR1_DATAST            FSMC_BWTR1_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR1_DATAST_0          (0x01UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR1_DATAST_1          (0x02UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR1_DATAST_2          (0x04UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR1_DATAST_3          (0x08UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR1_DATAST_4          (0x10UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR1_DATAST_5          (0x20UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR1_DATAST_6          (0x40UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR1_DATAST_7          (0x80UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR1_BUSTURN_Pos       (16U)\n#define FSMC_BWTR1_BUSTURN_Msk       (0xFUL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR1_BUSTURN           FSMC_BWTR1_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR1_BUSTURN_0         (0x1UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR1_BUSTURN_1         (0x2UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR1_BUSTURN_2         (0x4UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR1_BUSTURN_3         (0x8UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR1_ACCMOD_Pos        (28U)\n#define FSMC_BWTR1_ACCMOD_Msk        (0x3UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR1_ACCMOD            FSMC_BWTR1_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR1_ACCMOD_0          (0x1UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR1_ACCMOD_1          (0x2UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR2 register  ******************/\n#define FSMC_BWTR2_ADDSET_Pos        (0U)\n#define FSMC_BWTR2_ADDSET_Msk        (0xFUL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR2_ADDSET            FSMC_BWTR2_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR2_ADDSET_0          (0x1UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR2_ADDSET_1          (0x2UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR2_ADDSET_2          (0x4UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR2_ADDSET_3          (0x8UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR2_ADDHLD_Pos        (4U)\n#define FSMC_BWTR2_ADDHLD_Msk        (0xFUL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR2_ADDHLD            FSMC_BWTR2_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR2_ADDHLD_0          (0x1UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR2_ADDHLD_1          (0x2UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR2_ADDHLD_2          (0x4UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR2_ADDHLD_3          (0x8UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR2_DATAST_Pos        (8U)\n#define FSMC_BWTR2_DATAST_Msk        (0xFFUL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR2_DATAST            FSMC_BWTR2_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR2_DATAST_0          (0x01UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR2_DATAST_1          (0x02UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR2_DATAST_2          (0x04UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR2_DATAST_3          (0x08UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR2_DATAST_4          (0x10UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR2_DATAST_5          (0x20UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR2_DATAST_6          (0x40UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR2_DATAST_7          (0x80UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR2_BUSTURN_Pos       (16U)\n#define FSMC_BWTR2_BUSTURN_Msk       (0xFUL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR2_BUSTURN           FSMC_BWTR2_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR2_BUSTURN_0         (0x1UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR2_BUSTURN_1         (0x2UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR2_BUSTURN_2         (0x4UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR2_BUSTURN_3         (0x8UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR2_ACCMOD_Pos        (28U)\n#define FSMC_BWTR2_ACCMOD_Msk        (0x3UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR2_ACCMOD            FSMC_BWTR2_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR2_ACCMOD_0          (0x1UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR2_ACCMOD_1          (0x2UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR3 register  ******************/\n#define FSMC_BWTR3_ADDSET_Pos        (0U)\n#define FSMC_BWTR3_ADDSET_Msk        (0xFUL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR3_ADDSET            FSMC_BWTR3_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR3_ADDSET_0          (0x1UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR3_ADDSET_1          (0x2UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR3_ADDSET_2          (0x4UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR3_ADDSET_3          (0x8UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR3_ADDHLD_Pos        (4U)\n#define FSMC_BWTR3_ADDHLD_Msk        (0xFUL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR3_ADDHLD            FSMC_BWTR3_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR3_ADDHLD_0          (0x1UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR3_ADDHLD_1          (0x2UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR3_ADDHLD_2          (0x4UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR3_ADDHLD_3          (0x8UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR3_DATAST_Pos        (8U)\n#define FSMC_BWTR3_DATAST_Msk        (0xFFUL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR3_DATAST            FSMC_BWTR3_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR3_DATAST_0          (0x01UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR3_DATAST_1          (0x02UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR3_DATAST_2          (0x04UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR3_DATAST_3          (0x08UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR3_DATAST_4          (0x10UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR3_DATAST_5          (0x20UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR3_DATAST_6          (0x40UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR3_DATAST_7          (0x80UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR3_BUSTURN_Pos       (16U)\n#define FSMC_BWTR3_BUSTURN_Msk       (0xFUL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR3_BUSTURN           FSMC_BWTR3_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR3_BUSTURN_0         (0x1UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR3_BUSTURN_1         (0x2UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR3_BUSTURN_2         (0x4UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR3_BUSTURN_3         (0x8UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR3_ACCMOD_Pos        (28U)\n#define FSMC_BWTR3_ACCMOD_Msk        (0x3UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR3_ACCMOD            FSMC_BWTR3_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR3_ACCMOD_0          (0x1UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR3_ACCMOD_1          (0x2UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR4 register  ******************/\n#define FSMC_BWTR4_ADDSET_Pos        (0U)\n#define FSMC_BWTR4_ADDSET_Msk        (0xFUL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR4_ADDSET            FSMC_BWTR4_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR4_ADDSET_0          (0x1UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR4_ADDSET_1          (0x2UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR4_ADDSET_2          (0x4UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR4_ADDSET_3          (0x8UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR4_ADDHLD_Pos        (4U)\n#define FSMC_BWTR4_ADDHLD_Msk        (0xFUL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR4_ADDHLD            FSMC_BWTR4_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR4_ADDHLD_0          (0x1UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR4_ADDHLD_1          (0x2UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR4_ADDHLD_2          (0x4UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR4_ADDHLD_3          (0x8UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR4_DATAST_Pos        (8U)\n#define FSMC_BWTR4_DATAST_Msk        (0xFFUL << FSMC_BWTR4_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR4_DATAST            FSMC_BWTR4_DATAST_Msk                     /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FSMC_BWTR4_DATAST_0          0x00000100U                               /*!<Bit 0 */\n#define FSMC_BWTR4_DATAST_1          0x00000200U                               /*!<Bit 1 */\n#define FSMC_BWTR4_DATAST_2          0x00000400U                               /*!<Bit 2 */\n#define FSMC_BWTR4_DATAST_3          0x00000800U                               /*!<Bit 3 */\n#define FSMC_BWTR4_DATAST_4          0x00001000U                               /*!<Bit 4 */\n#define FSMC_BWTR4_DATAST_5          0x00002000U                               /*!<Bit 5 */\n#define FSMC_BWTR4_DATAST_6          0x00004000U                               /*!<Bit 6 */\n#define FSMC_BWTR4_DATAST_7          0x00008000U                               /*!<Bit 7 */\n\n#define FSMC_BWTR4_BUSTURN_Pos       (16U)\n#define FSMC_BWTR4_BUSTURN_Msk       (0xFUL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR4_BUSTURN           FSMC_BWTR4_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR4_BUSTURN_0         (0x1UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR4_BUSTURN_1         (0x2UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR4_BUSTURN_2         (0x4UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR4_BUSTURN_3         (0x8UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR4_ACCMOD_Pos        (28U)\n#define FSMC_BWTR4_ACCMOD_Msk        (0x3UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR4_ACCMOD            FSMC_BWTR4_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR4_ACCMOD_0          (0x1UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR4_ACCMOD_1          (0x2UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            General Purpose I/O                             */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bits definition for GPIO_MODER register  *****************/\n#define GPIO_MODER_MODER0_Pos            (0U)\n#define GPIO_MODER_MODER0_Msk            (0x3UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */\n#define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk\n#define GPIO_MODER_MODER0_0              (0x1UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */\n#define GPIO_MODER_MODER0_1              (0x2UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */\n#define GPIO_MODER_MODER1_Pos            (2U)\n#define GPIO_MODER_MODER1_Msk            (0x3UL << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */\n#define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk\n#define GPIO_MODER_MODER1_0              (0x1UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */\n#define GPIO_MODER_MODER1_1              (0x2UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */\n#define GPIO_MODER_MODER2_Pos            (4U)\n#define GPIO_MODER_MODER2_Msk            (0x3UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */\n#define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk\n#define GPIO_MODER_MODER2_0              (0x1UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */\n#define GPIO_MODER_MODER2_1              (0x2UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */\n#define GPIO_MODER_MODER3_Pos            (6U)\n#define GPIO_MODER_MODER3_Msk            (0x3UL << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */\n#define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk\n#define GPIO_MODER_MODER3_0              (0x1UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */\n#define GPIO_MODER_MODER3_1              (0x2UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */\n#define GPIO_MODER_MODER4_Pos            (8U)\n#define GPIO_MODER_MODER4_Msk            (0x3UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */\n#define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk\n#define GPIO_MODER_MODER4_0              (0x1UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */\n#define GPIO_MODER_MODER4_1              (0x2UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */\n#define GPIO_MODER_MODER5_Pos            (10U)\n#define GPIO_MODER_MODER5_Msk            (0x3UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */\n#define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk\n#define GPIO_MODER_MODER5_0              (0x1UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */\n#define GPIO_MODER_MODER5_1              (0x2UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */\n#define GPIO_MODER_MODER6_Pos            (12U)\n#define GPIO_MODER_MODER6_Msk            (0x3UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */\n#define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk\n#define GPIO_MODER_MODER6_0              (0x1UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */\n#define GPIO_MODER_MODER6_1              (0x2UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */\n#define GPIO_MODER_MODER7_Pos            (14U)\n#define GPIO_MODER_MODER7_Msk            (0x3UL << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */\n#define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk\n#define GPIO_MODER_MODER7_0              (0x1UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */\n#define GPIO_MODER_MODER7_1              (0x2UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */\n#define GPIO_MODER_MODER8_Pos            (16U)\n#define GPIO_MODER_MODER8_Msk            (0x3UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */\n#define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk\n#define GPIO_MODER_MODER8_0              (0x1UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */\n#define GPIO_MODER_MODER8_1              (0x2UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */\n#define GPIO_MODER_MODER9_Pos            (18U)\n#define GPIO_MODER_MODER9_Msk            (0x3UL << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */\n#define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk\n#define GPIO_MODER_MODER9_0              (0x1UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */\n#define GPIO_MODER_MODER9_1              (0x2UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */\n#define GPIO_MODER_MODER10_Pos           (20U)\n#define GPIO_MODER_MODER10_Msk           (0x3UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */\n#define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk\n#define GPIO_MODER_MODER10_0             (0x1UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */\n#define GPIO_MODER_MODER10_1             (0x2UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */\n#define GPIO_MODER_MODER11_Pos           (22U)\n#define GPIO_MODER_MODER11_Msk           (0x3UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */\n#define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk\n#define GPIO_MODER_MODER11_0             (0x1UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */\n#define GPIO_MODER_MODER11_1             (0x2UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */\n#define GPIO_MODER_MODER12_Pos           (24U)\n#define GPIO_MODER_MODER12_Msk           (0x3UL << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */\n#define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk\n#define GPIO_MODER_MODER12_0             (0x1UL << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */\n#define GPIO_MODER_MODER12_1             (0x2UL << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */\n#define GPIO_MODER_MODER13_Pos           (26U)\n#define GPIO_MODER_MODER13_Msk           (0x3UL << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */\n#define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk\n#define GPIO_MODER_MODER13_0             (0x1UL << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */\n#define GPIO_MODER_MODER13_1             (0x2UL << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */\n#define GPIO_MODER_MODER14_Pos           (28U)\n#define GPIO_MODER_MODER14_Msk           (0x3UL << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */\n#define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk\n#define GPIO_MODER_MODER14_0             (0x1UL << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */\n#define GPIO_MODER_MODER14_1             (0x2UL << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */\n#define GPIO_MODER_MODER15_Pos           (30U)\n#define GPIO_MODER_MODER15_Msk           (0x3UL << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */\n#define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk\n#define GPIO_MODER_MODER15_0             (0x1UL << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */\n#define GPIO_MODER_MODER15_1             (0x2UL << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */\n\n\n/******************  Bits definition for GPIO_OTYPER register  ****************/\n#define GPIO_OTYPER_OT0_Pos              (0U)\n#define GPIO_OTYPER_OT0_Msk              (0x1UL << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */\n#define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk\n#define GPIO_OTYPER_OT1_Pos              (1U)\n#define GPIO_OTYPER_OT1_Msk              (0x1UL << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */\n#define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk\n#define GPIO_OTYPER_OT2_Pos              (2U)\n#define GPIO_OTYPER_OT2_Msk              (0x1UL << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */\n#define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk\n#define GPIO_OTYPER_OT3_Pos              (3U)\n#define GPIO_OTYPER_OT3_Msk              (0x1UL << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */\n#define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk\n#define GPIO_OTYPER_OT4_Pos              (4U)\n#define GPIO_OTYPER_OT4_Msk              (0x1UL << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */\n#define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk\n#define GPIO_OTYPER_OT5_Pos              (5U)\n#define GPIO_OTYPER_OT5_Msk              (0x1UL << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */\n#define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk\n#define GPIO_OTYPER_OT6_Pos              (6U)\n#define GPIO_OTYPER_OT6_Msk              (0x1UL << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */\n#define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk\n#define GPIO_OTYPER_OT7_Pos              (7U)\n#define GPIO_OTYPER_OT7_Msk              (0x1UL << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */\n#define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk\n#define GPIO_OTYPER_OT8_Pos              (8U)\n#define GPIO_OTYPER_OT8_Msk              (0x1UL << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */\n#define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk\n#define GPIO_OTYPER_OT9_Pos              (9U)\n#define GPIO_OTYPER_OT9_Msk              (0x1UL << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */\n#define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk\n#define GPIO_OTYPER_OT10_Pos             (10U)\n#define GPIO_OTYPER_OT10_Msk             (0x1UL << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */\n#define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk\n#define GPIO_OTYPER_OT11_Pos             (11U)\n#define GPIO_OTYPER_OT11_Msk             (0x1UL << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */\n#define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk\n#define GPIO_OTYPER_OT12_Pos             (12U)\n#define GPIO_OTYPER_OT12_Msk             (0x1UL << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */\n#define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk\n#define GPIO_OTYPER_OT13_Pos             (13U)\n#define GPIO_OTYPER_OT13_Msk             (0x1UL << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */\n#define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk\n#define GPIO_OTYPER_OT14_Pos             (14U)\n#define GPIO_OTYPER_OT14_Msk             (0x1UL << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */\n#define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk\n#define GPIO_OTYPER_OT15_Pos             (15U)\n#define GPIO_OTYPER_OT15_Msk             (0x1UL << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */\n#define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk\n\n/* Legacy defines */\n#define GPIO_OTYPER_OT_0                 GPIO_OTYPER_OT0\n#define GPIO_OTYPER_OT_1                 GPIO_OTYPER_OT1\n#define GPIO_OTYPER_OT_2                 GPIO_OTYPER_OT2\n#define GPIO_OTYPER_OT_3                 GPIO_OTYPER_OT3\n#define GPIO_OTYPER_OT_4                 GPIO_OTYPER_OT4\n#define GPIO_OTYPER_OT_5                 GPIO_OTYPER_OT5\n#define GPIO_OTYPER_OT_6                 GPIO_OTYPER_OT6\n#define GPIO_OTYPER_OT_7                 GPIO_OTYPER_OT7\n#define GPIO_OTYPER_OT_8                 GPIO_OTYPER_OT8\n#define GPIO_OTYPER_OT_9                 GPIO_OTYPER_OT9\n#define GPIO_OTYPER_OT_10                GPIO_OTYPER_OT10\n#define GPIO_OTYPER_OT_11                GPIO_OTYPER_OT11\n#define GPIO_OTYPER_OT_12                GPIO_OTYPER_OT12\n#define GPIO_OTYPER_OT_13                GPIO_OTYPER_OT13\n#define GPIO_OTYPER_OT_14                GPIO_OTYPER_OT14\n#define GPIO_OTYPER_OT_15                GPIO_OTYPER_OT15\n\n/******************  Bits definition for GPIO_OSPEEDR register  ***************/\n#define GPIO_OSPEEDR_OSPEED0_Pos         (0U)\n#define GPIO_OSPEEDR_OSPEED0_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000003 */\n#define GPIO_OSPEEDR_OSPEED0             GPIO_OSPEEDR_OSPEED0_Msk\n#define GPIO_OSPEEDR_OSPEED0_0           (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000001 */\n#define GPIO_OSPEEDR_OSPEED0_1           (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000002 */\n#define GPIO_OSPEEDR_OSPEED1_Pos         (2U)\n#define GPIO_OSPEEDR_OSPEED1_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x0000000C */\n#define GPIO_OSPEEDR_OSPEED1             GPIO_OSPEEDR_OSPEED1_Msk\n#define GPIO_OSPEEDR_OSPEED1_0           (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000004 */\n#define GPIO_OSPEEDR_OSPEED1_1           (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000008 */\n#define GPIO_OSPEEDR_OSPEED2_Pos         (4U)\n#define GPIO_OSPEEDR_OSPEED2_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000030 */\n#define GPIO_OSPEEDR_OSPEED2             GPIO_OSPEEDR_OSPEED2_Msk\n#define GPIO_OSPEEDR_OSPEED2_0           (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000010 */\n#define GPIO_OSPEEDR_OSPEED2_1           (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000020 */\n#define GPIO_OSPEEDR_OSPEED3_Pos         (6U)\n#define GPIO_OSPEEDR_OSPEED3_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x000000C0 */\n#define GPIO_OSPEEDR_OSPEED3             GPIO_OSPEEDR_OSPEED3_Msk\n#define GPIO_OSPEEDR_OSPEED3_0           (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000040 */\n#define GPIO_OSPEEDR_OSPEED3_1           (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000080 */\n#define GPIO_OSPEEDR_OSPEED4_Pos         (8U)\n#define GPIO_OSPEEDR_OSPEED4_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000300 */\n#define GPIO_OSPEEDR_OSPEED4             GPIO_OSPEEDR_OSPEED4_Msk\n#define GPIO_OSPEEDR_OSPEED4_0           (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000100 */\n#define GPIO_OSPEEDR_OSPEED4_1           (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000200 */\n#define GPIO_OSPEEDR_OSPEED5_Pos         (10U)\n#define GPIO_OSPEEDR_OSPEED5_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000C00 */\n#define GPIO_OSPEEDR_OSPEED5             GPIO_OSPEEDR_OSPEED5_Msk\n#define GPIO_OSPEEDR_OSPEED5_0           (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000400 */\n#define GPIO_OSPEEDR_OSPEED5_1           (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000800 */\n#define GPIO_OSPEEDR_OSPEED6_Pos         (12U)\n#define GPIO_OSPEEDR_OSPEED6_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00003000 */\n#define GPIO_OSPEEDR_OSPEED6             GPIO_OSPEEDR_OSPEED6_Msk\n#define GPIO_OSPEEDR_OSPEED6_0           (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00001000 */\n#define GPIO_OSPEEDR_OSPEED6_1           (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00002000 */\n#define GPIO_OSPEEDR_OSPEED7_Pos         (14U)\n#define GPIO_OSPEEDR_OSPEED7_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x0000C000 */\n#define GPIO_OSPEEDR_OSPEED7             GPIO_OSPEEDR_OSPEED7_Msk\n#define GPIO_OSPEEDR_OSPEED7_0           (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00004000 */\n#define GPIO_OSPEEDR_OSPEED7_1           (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00008000 */\n#define GPIO_OSPEEDR_OSPEED8_Pos         (16U)\n#define GPIO_OSPEEDR_OSPEED8_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00030000 */\n#define GPIO_OSPEEDR_OSPEED8             GPIO_OSPEEDR_OSPEED8_Msk\n#define GPIO_OSPEEDR_OSPEED8_0           (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00010000 */\n#define GPIO_OSPEEDR_OSPEED8_1           (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00020000 */\n#define GPIO_OSPEEDR_OSPEED9_Pos         (18U)\n#define GPIO_OSPEEDR_OSPEED9_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x000C0000 */\n#define GPIO_OSPEEDR_OSPEED9             GPIO_OSPEEDR_OSPEED9_Msk\n#define GPIO_OSPEEDR_OSPEED9_0           (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00040000 */\n#define GPIO_OSPEEDR_OSPEED9_1           (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00080000 */\n#define GPIO_OSPEEDR_OSPEED10_Pos        (20U)\n#define GPIO_OSPEEDR_OSPEED10_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00300000 */\n#define GPIO_OSPEEDR_OSPEED10            GPIO_OSPEEDR_OSPEED10_Msk\n#define GPIO_OSPEEDR_OSPEED10_0          (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00100000 */\n#define GPIO_OSPEEDR_OSPEED10_1          (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00200000 */\n#define GPIO_OSPEEDR_OSPEED11_Pos        (22U)\n#define GPIO_OSPEEDR_OSPEED11_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00C00000 */\n#define GPIO_OSPEEDR_OSPEED11            GPIO_OSPEEDR_OSPEED11_Msk\n#define GPIO_OSPEEDR_OSPEED11_0          (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00400000 */\n#define GPIO_OSPEEDR_OSPEED11_1          (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00800000 */\n#define GPIO_OSPEEDR_OSPEED12_Pos        (24U)\n#define GPIO_OSPEEDR_OSPEED12_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x03000000 */\n#define GPIO_OSPEEDR_OSPEED12            GPIO_OSPEEDR_OSPEED12_Msk\n#define GPIO_OSPEEDR_OSPEED12_0          (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x01000000 */\n#define GPIO_OSPEEDR_OSPEED12_1          (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x02000000 */\n#define GPIO_OSPEEDR_OSPEED13_Pos        (26U)\n#define GPIO_OSPEEDR_OSPEED13_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x0C000000 */\n#define GPIO_OSPEEDR_OSPEED13            GPIO_OSPEEDR_OSPEED13_Msk\n#define GPIO_OSPEEDR_OSPEED13_0          (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x04000000 */\n#define GPIO_OSPEEDR_OSPEED13_1          (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x08000000 */\n#define GPIO_OSPEEDR_OSPEED14_Pos        (28U)\n#define GPIO_OSPEEDR_OSPEED14_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x30000000 */\n#define GPIO_OSPEEDR_OSPEED14            GPIO_OSPEEDR_OSPEED14_Msk\n#define GPIO_OSPEEDR_OSPEED14_0          (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x10000000 */\n#define GPIO_OSPEEDR_OSPEED14_1          (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x20000000 */\n#define GPIO_OSPEEDR_OSPEED15_Pos        (30U)\n#define GPIO_OSPEEDR_OSPEED15_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0xC0000000 */\n#define GPIO_OSPEEDR_OSPEED15            GPIO_OSPEEDR_OSPEED15_Msk\n#define GPIO_OSPEEDR_OSPEED15_0          (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x40000000 */\n#define GPIO_OSPEEDR_OSPEED15_1          (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDR_OSPEED0\n#define GPIO_OSPEEDER_OSPEEDR0_0         GPIO_OSPEEDR_OSPEED0_0\n#define GPIO_OSPEEDER_OSPEEDR0_1         GPIO_OSPEEDR_OSPEED0_1\n#define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDR_OSPEED1\n#define GPIO_OSPEEDER_OSPEEDR1_0         GPIO_OSPEEDR_OSPEED1_0\n#define GPIO_OSPEEDER_OSPEEDR1_1         GPIO_OSPEEDR_OSPEED1_1\n#define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDR_OSPEED2\n#define GPIO_OSPEEDER_OSPEEDR2_0         GPIO_OSPEEDR_OSPEED2_0\n#define GPIO_OSPEEDER_OSPEEDR2_1         GPIO_OSPEEDR_OSPEED2_1\n#define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDR_OSPEED3\n#define GPIO_OSPEEDER_OSPEEDR3_0         GPIO_OSPEEDR_OSPEED3_0\n#define GPIO_OSPEEDER_OSPEEDR3_1         GPIO_OSPEEDR_OSPEED3_1\n#define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDR_OSPEED4\n#define GPIO_OSPEEDER_OSPEEDR4_0         GPIO_OSPEEDR_OSPEED4_0\n#define GPIO_OSPEEDER_OSPEEDR4_1         GPIO_OSPEEDR_OSPEED4_1\n#define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDR_OSPEED5\n#define GPIO_OSPEEDER_OSPEEDR5_0         GPIO_OSPEEDR_OSPEED5_0\n#define GPIO_OSPEEDER_OSPEEDR5_1         GPIO_OSPEEDR_OSPEED5_1\n#define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDR_OSPEED6\n#define GPIO_OSPEEDER_OSPEEDR6_0         GPIO_OSPEEDR_OSPEED6_0\n#define GPIO_OSPEEDER_OSPEEDR6_1         GPIO_OSPEEDR_OSPEED6_1\n#define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDR_OSPEED7\n#define GPIO_OSPEEDER_OSPEEDR7_0         GPIO_OSPEEDR_OSPEED7_0\n#define GPIO_OSPEEDER_OSPEEDR7_1         GPIO_OSPEEDR_OSPEED7_1\n#define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDR_OSPEED8\n#define GPIO_OSPEEDER_OSPEEDR8_0         GPIO_OSPEEDR_OSPEED8_0\n#define GPIO_OSPEEDER_OSPEEDR8_1         GPIO_OSPEEDR_OSPEED8_1\n#define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDR_OSPEED9\n#define GPIO_OSPEEDER_OSPEEDR9_0         GPIO_OSPEEDR_OSPEED9_0\n#define GPIO_OSPEEDER_OSPEEDR9_1         GPIO_OSPEEDR_OSPEED9_1\n#define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDR_OSPEED10\n#define GPIO_OSPEEDER_OSPEEDR10_0        GPIO_OSPEEDR_OSPEED10_0\n#define GPIO_OSPEEDER_OSPEEDR10_1        GPIO_OSPEEDR_OSPEED10_1\n#define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDR_OSPEED11\n#define GPIO_OSPEEDER_OSPEEDR11_0        GPIO_OSPEEDR_OSPEED11_0\n#define GPIO_OSPEEDER_OSPEEDR11_1        GPIO_OSPEEDR_OSPEED11_1\n#define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDR_OSPEED12\n#define GPIO_OSPEEDER_OSPEEDR12_0        GPIO_OSPEEDR_OSPEED12_0\n#define GPIO_OSPEEDER_OSPEEDR12_1        GPIO_OSPEEDR_OSPEED12_1\n#define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDR_OSPEED13\n#define GPIO_OSPEEDER_OSPEEDR13_0        GPIO_OSPEEDR_OSPEED13_0\n#define GPIO_OSPEEDER_OSPEEDR13_1        GPIO_OSPEEDR_OSPEED13_1\n#define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDR_OSPEED14\n#define GPIO_OSPEEDER_OSPEEDR14_0        GPIO_OSPEEDR_OSPEED14_0\n#define GPIO_OSPEEDER_OSPEEDR14_1        GPIO_OSPEEDR_OSPEED14_1\n#define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDR_OSPEED15\n#define GPIO_OSPEEDER_OSPEEDR15_0        GPIO_OSPEEDR_OSPEED15_0\n#define GPIO_OSPEEDER_OSPEEDR15_1        GPIO_OSPEEDR_OSPEED15_1\n\n/******************  Bits definition for GPIO_PUPDR register  *****************/\n#define GPIO_PUPDR_PUPD0_Pos             (0U)\n#define GPIO_PUPDR_PUPD0_Msk             (0x3UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000003 */\n#define GPIO_PUPDR_PUPD0                 GPIO_PUPDR_PUPD0_Msk\n#define GPIO_PUPDR_PUPD0_0               (0x1UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000001 */\n#define GPIO_PUPDR_PUPD0_1               (0x2UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000002 */\n#define GPIO_PUPDR_PUPD1_Pos             (2U)\n#define GPIO_PUPDR_PUPD1_Msk             (0x3UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x0000000C */\n#define GPIO_PUPDR_PUPD1                 GPIO_PUPDR_PUPD1_Msk\n#define GPIO_PUPDR_PUPD1_0               (0x1UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000004 */\n#define GPIO_PUPDR_PUPD1_1               (0x2UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000008 */\n#define GPIO_PUPDR_PUPD2_Pos             (4U)\n#define GPIO_PUPDR_PUPD2_Msk             (0x3UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000030 */\n#define GPIO_PUPDR_PUPD2                 GPIO_PUPDR_PUPD2_Msk\n#define GPIO_PUPDR_PUPD2_0               (0x1UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000010 */\n#define GPIO_PUPDR_PUPD2_1               (0x2UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000020 */\n#define GPIO_PUPDR_PUPD3_Pos             (6U)\n#define GPIO_PUPDR_PUPD3_Msk             (0x3UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x000000C0 */\n#define GPIO_PUPDR_PUPD3                 GPIO_PUPDR_PUPD3_Msk\n#define GPIO_PUPDR_PUPD3_0               (0x1UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000040 */\n#define GPIO_PUPDR_PUPD3_1               (0x2UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000080 */\n#define GPIO_PUPDR_PUPD4_Pos             (8U)\n#define GPIO_PUPDR_PUPD4_Msk             (0x3UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000300 */\n#define GPIO_PUPDR_PUPD4                 GPIO_PUPDR_PUPD4_Msk\n#define GPIO_PUPDR_PUPD4_0               (0x1UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000100 */\n#define GPIO_PUPDR_PUPD4_1               (0x2UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000200 */\n#define GPIO_PUPDR_PUPD5_Pos             (10U)\n#define GPIO_PUPDR_PUPD5_Msk             (0x3UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000C00 */\n#define GPIO_PUPDR_PUPD5                 GPIO_PUPDR_PUPD5_Msk\n#define GPIO_PUPDR_PUPD5_0               (0x1UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000400 */\n#define GPIO_PUPDR_PUPD5_1               (0x2UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000800 */\n#define GPIO_PUPDR_PUPD6_Pos             (12U)\n#define GPIO_PUPDR_PUPD6_Msk             (0x3UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00003000 */\n#define GPIO_PUPDR_PUPD6                 GPIO_PUPDR_PUPD6_Msk\n#define GPIO_PUPDR_PUPD6_0               (0x1UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00001000 */\n#define GPIO_PUPDR_PUPD6_1               (0x2UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00002000 */\n#define GPIO_PUPDR_PUPD7_Pos             (14U)\n#define GPIO_PUPDR_PUPD7_Msk             (0x3UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x0000C000 */\n#define GPIO_PUPDR_PUPD7                 GPIO_PUPDR_PUPD7_Msk\n#define GPIO_PUPDR_PUPD7_0               (0x1UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00004000 */\n#define GPIO_PUPDR_PUPD7_1               (0x2UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00008000 */\n#define GPIO_PUPDR_PUPD8_Pos             (16U)\n#define GPIO_PUPDR_PUPD8_Msk             (0x3UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00030000 */\n#define GPIO_PUPDR_PUPD8                 GPIO_PUPDR_PUPD8_Msk\n#define GPIO_PUPDR_PUPD8_0               (0x1UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00010000 */\n#define GPIO_PUPDR_PUPD8_1               (0x2UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00020000 */\n#define GPIO_PUPDR_PUPD9_Pos             (18U)\n#define GPIO_PUPDR_PUPD9_Msk             (0x3UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x000C0000 */\n#define GPIO_PUPDR_PUPD9                 GPIO_PUPDR_PUPD9_Msk\n#define GPIO_PUPDR_PUPD9_0               (0x1UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00040000 */\n#define GPIO_PUPDR_PUPD9_1               (0x2UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00080000 */\n#define GPIO_PUPDR_PUPD10_Pos            (20U)\n#define GPIO_PUPDR_PUPD10_Msk            (0x3UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00300000 */\n#define GPIO_PUPDR_PUPD10                GPIO_PUPDR_PUPD10_Msk\n#define GPIO_PUPDR_PUPD10_0              (0x1UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00100000 */\n#define GPIO_PUPDR_PUPD10_1              (0x2UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00200000 */\n#define GPIO_PUPDR_PUPD11_Pos            (22U)\n#define GPIO_PUPDR_PUPD11_Msk            (0x3UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00C00000 */\n#define GPIO_PUPDR_PUPD11                GPIO_PUPDR_PUPD11_Msk\n#define GPIO_PUPDR_PUPD11_0              (0x1UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00400000 */\n#define GPIO_PUPDR_PUPD11_1              (0x2UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00800000 */\n#define GPIO_PUPDR_PUPD12_Pos            (24U)\n#define GPIO_PUPDR_PUPD12_Msk            (0x3UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x03000000 */\n#define GPIO_PUPDR_PUPD12                GPIO_PUPDR_PUPD12_Msk\n#define GPIO_PUPDR_PUPD12_0              (0x1UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x01000000 */\n#define GPIO_PUPDR_PUPD12_1              (0x2UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x02000000 */\n#define GPIO_PUPDR_PUPD13_Pos            (26U)\n#define GPIO_PUPDR_PUPD13_Msk            (0x3UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x0C000000 */\n#define GPIO_PUPDR_PUPD13                GPIO_PUPDR_PUPD13_Msk\n#define GPIO_PUPDR_PUPD13_0              (0x1UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x04000000 */\n#define GPIO_PUPDR_PUPD13_1              (0x2UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x08000000 */\n#define GPIO_PUPDR_PUPD14_Pos            (28U)\n#define GPIO_PUPDR_PUPD14_Msk            (0x3UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x30000000 */\n#define GPIO_PUPDR_PUPD14                GPIO_PUPDR_PUPD14_Msk\n#define GPIO_PUPDR_PUPD14_0              (0x1UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x10000000 */\n#define GPIO_PUPDR_PUPD14_1              (0x2UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x20000000 */\n#define GPIO_PUPDR_PUPD15_Pos            (30U)\n#define GPIO_PUPDR_PUPD15_Msk            (0x3UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0xC0000000 */\n#define GPIO_PUPDR_PUPD15                GPIO_PUPDR_PUPD15_Msk\n#define GPIO_PUPDR_PUPD15_0              (0x1UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x40000000 */\n#define GPIO_PUPDR_PUPD15_1              (0x2UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPD0\n#define GPIO_PUPDR_PUPDR0_0              GPIO_PUPDR_PUPD0_0\n#define GPIO_PUPDR_PUPDR0_1              GPIO_PUPDR_PUPD0_1\n#define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPD1\n#define GPIO_PUPDR_PUPDR1_0              GPIO_PUPDR_PUPD1_0\n#define GPIO_PUPDR_PUPDR1_1              GPIO_PUPDR_PUPD1_1\n#define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPD2\n#define GPIO_PUPDR_PUPDR2_0              GPIO_PUPDR_PUPD2_0\n#define GPIO_PUPDR_PUPDR2_1              GPIO_PUPDR_PUPD2_1\n#define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPD3\n#define GPIO_PUPDR_PUPDR3_0              GPIO_PUPDR_PUPD3_0\n#define GPIO_PUPDR_PUPDR3_1              GPIO_PUPDR_PUPD3_1\n#define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPD4\n#define GPIO_PUPDR_PUPDR4_0              GPIO_PUPDR_PUPD4_0\n#define GPIO_PUPDR_PUPDR4_1              GPIO_PUPDR_PUPD4_1\n#define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPD5\n#define GPIO_PUPDR_PUPDR5_0              GPIO_PUPDR_PUPD5_0\n#define GPIO_PUPDR_PUPDR5_1              GPIO_PUPDR_PUPD5_1\n#define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPD6\n#define GPIO_PUPDR_PUPDR6_0              GPIO_PUPDR_PUPD6_0\n#define GPIO_PUPDR_PUPDR6_1              GPIO_PUPDR_PUPD6_1\n#define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPD7\n#define GPIO_PUPDR_PUPDR7_0              GPIO_PUPDR_PUPD7_0\n#define GPIO_PUPDR_PUPDR7_1              GPIO_PUPDR_PUPD7_1\n#define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPD8\n#define GPIO_PUPDR_PUPDR8_0              GPIO_PUPDR_PUPD8_0\n#define GPIO_PUPDR_PUPDR8_1              GPIO_PUPDR_PUPD8_1\n#define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPD9\n#define GPIO_PUPDR_PUPDR9_0              GPIO_PUPDR_PUPD9_0\n#define GPIO_PUPDR_PUPDR9_1              GPIO_PUPDR_PUPD9_1\n#define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPD10\n#define GPIO_PUPDR_PUPDR10_0             GPIO_PUPDR_PUPD10_0\n#define GPIO_PUPDR_PUPDR10_1             GPIO_PUPDR_PUPD10_1\n#define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPD11\n#define GPIO_PUPDR_PUPDR11_0             GPIO_PUPDR_PUPD11_0\n#define GPIO_PUPDR_PUPDR11_1             GPIO_PUPDR_PUPD11_1\n#define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPD12\n#define GPIO_PUPDR_PUPDR12_0             GPIO_PUPDR_PUPD12_0\n#define GPIO_PUPDR_PUPDR12_1             GPIO_PUPDR_PUPD12_1\n#define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPD13\n#define GPIO_PUPDR_PUPDR13_0             GPIO_PUPDR_PUPD13_0\n#define GPIO_PUPDR_PUPDR13_1             GPIO_PUPDR_PUPD13_1\n#define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPD14\n#define GPIO_PUPDR_PUPDR14_0             GPIO_PUPDR_PUPD14_0\n#define GPIO_PUPDR_PUPDR14_1             GPIO_PUPDR_PUPD14_1\n#define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPD15\n#define GPIO_PUPDR_PUPDR15_0             GPIO_PUPDR_PUPD15_0\n#define GPIO_PUPDR_PUPDR15_1             GPIO_PUPDR_PUPD15_1\n\n/******************  Bits definition for GPIO_IDR register  *******************/\n#define GPIO_IDR_ID0_Pos                 (0U)\n#define GPIO_IDR_ID0_Msk                 (0x1UL << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */\n#define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk\n#define GPIO_IDR_ID1_Pos                 (1U)\n#define GPIO_IDR_ID1_Msk                 (0x1UL << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */\n#define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk\n#define GPIO_IDR_ID2_Pos                 (2U)\n#define GPIO_IDR_ID2_Msk                 (0x1UL << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */\n#define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk\n#define GPIO_IDR_ID3_Pos                 (3U)\n#define GPIO_IDR_ID3_Msk                 (0x1UL << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */\n#define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk\n#define GPIO_IDR_ID4_Pos                 (4U)\n#define GPIO_IDR_ID4_Msk                 (0x1UL << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */\n#define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk\n#define GPIO_IDR_ID5_Pos                 (5U)\n#define GPIO_IDR_ID5_Msk                 (0x1UL << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */\n#define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk\n#define GPIO_IDR_ID6_Pos                 (6U)\n#define GPIO_IDR_ID6_Msk                 (0x1UL << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */\n#define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk\n#define GPIO_IDR_ID7_Pos                 (7U)\n#define GPIO_IDR_ID7_Msk                 (0x1UL << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */\n#define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk\n#define GPIO_IDR_ID8_Pos                 (8U)\n#define GPIO_IDR_ID8_Msk                 (0x1UL << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */\n#define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk\n#define GPIO_IDR_ID9_Pos                 (9U)\n#define GPIO_IDR_ID9_Msk                 (0x1UL << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */\n#define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk\n#define GPIO_IDR_ID10_Pos                (10U)\n#define GPIO_IDR_ID10_Msk                (0x1UL << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */\n#define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk\n#define GPIO_IDR_ID11_Pos                (11U)\n#define GPIO_IDR_ID11_Msk                (0x1UL << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */\n#define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk\n#define GPIO_IDR_ID12_Pos                (12U)\n#define GPIO_IDR_ID12_Msk                (0x1UL << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */\n#define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk\n#define GPIO_IDR_ID13_Pos                (13U)\n#define GPIO_IDR_ID13_Msk                (0x1UL << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */\n#define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk\n#define GPIO_IDR_ID14_Pos                (14U)\n#define GPIO_IDR_ID14_Msk                (0x1UL << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */\n#define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk\n#define GPIO_IDR_ID15_Pos                (15U)\n#define GPIO_IDR_ID15_Msk                (0x1UL << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */\n#define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk\n\n/* Legacy defines */\n#define GPIO_IDR_IDR_0                   GPIO_IDR_ID0\n#define GPIO_IDR_IDR_1                   GPIO_IDR_ID1\n#define GPIO_IDR_IDR_2                   GPIO_IDR_ID2\n#define GPIO_IDR_IDR_3                   GPIO_IDR_ID3\n#define GPIO_IDR_IDR_4                   GPIO_IDR_ID4\n#define GPIO_IDR_IDR_5                   GPIO_IDR_ID5\n#define GPIO_IDR_IDR_6                   GPIO_IDR_ID6\n#define GPIO_IDR_IDR_7                   GPIO_IDR_ID7\n#define GPIO_IDR_IDR_8                   GPIO_IDR_ID8\n#define GPIO_IDR_IDR_9                   GPIO_IDR_ID9\n#define GPIO_IDR_IDR_10                  GPIO_IDR_ID10\n#define GPIO_IDR_IDR_11                  GPIO_IDR_ID11\n#define GPIO_IDR_IDR_12                  GPIO_IDR_ID12\n#define GPIO_IDR_IDR_13                  GPIO_IDR_ID13\n#define GPIO_IDR_IDR_14                  GPIO_IDR_ID14\n#define GPIO_IDR_IDR_15                  GPIO_IDR_ID15\n\n/******************  Bits definition for GPIO_ODR register  *******************/\n#define GPIO_ODR_OD0_Pos                 (0U)\n#define GPIO_ODR_OD0_Msk                 (0x1UL << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */\n#define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk\n#define GPIO_ODR_OD1_Pos                 (1U)\n#define GPIO_ODR_OD1_Msk                 (0x1UL << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */\n#define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk\n#define GPIO_ODR_OD2_Pos                 (2U)\n#define GPIO_ODR_OD2_Msk                 (0x1UL << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */\n#define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk\n#define GPIO_ODR_OD3_Pos                 (3U)\n#define GPIO_ODR_OD3_Msk                 (0x1UL << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */\n#define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk\n#define GPIO_ODR_OD4_Pos                 (4U)\n#define GPIO_ODR_OD4_Msk                 (0x1UL << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */\n#define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk\n#define GPIO_ODR_OD5_Pos                 (5U)\n#define GPIO_ODR_OD5_Msk                 (0x1UL << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */\n#define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk\n#define GPIO_ODR_OD6_Pos                 (6U)\n#define GPIO_ODR_OD6_Msk                 (0x1UL << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */\n#define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk\n#define GPIO_ODR_OD7_Pos                 (7U)\n#define GPIO_ODR_OD7_Msk                 (0x1UL << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */\n#define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk\n#define GPIO_ODR_OD8_Pos                 (8U)\n#define GPIO_ODR_OD8_Msk                 (0x1UL << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */\n#define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk\n#define GPIO_ODR_OD9_Pos                 (9U)\n#define GPIO_ODR_OD9_Msk                 (0x1UL << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */\n#define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk\n#define GPIO_ODR_OD10_Pos                (10U)\n#define GPIO_ODR_OD10_Msk                (0x1UL << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */\n#define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk\n#define GPIO_ODR_OD11_Pos                (11U)\n#define GPIO_ODR_OD11_Msk                (0x1UL << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */\n#define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk\n#define GPIO_ODR_OD12_Pos                (12U)\n#define GPIO_ODR_OD12_Msk                (0x1UL << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */\n#define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk\n#define GPIO_ODR_OD13_Pos                (13U)\n#define GPIO_ODR_OD13_Msk                (0x1UL << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */\n#define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk\n#define GPIO_ODR_OD14_Pos                (14U)\n#define GPIO_ODR_OD14_Msk                (0x1UL << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */\n#define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk\n#define GPIO_ODR_OD15_Pos                (15U)\n#define GPIO_ODR_OD15_Msk                (0x1UL << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */\n#define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk\n/* Legacy defines */\n#define GPIO_ODR_ODR_0                   GPIO_ODR_OD0\n#define GPIO_ODR_ODR_1                   GPIO_ODR_OD1\n#define GPIO_ODR_ODR_2                   GPIO_ODR_OD2\n#define GPIO_ODR_ODR_3                   GPIO_ODR_OD3\n#define GPIO_ODR_ODR_4                   GPIO_ODR_OD4\n#define GPIO_ODR_ODR_5                   GPIO_ODR_OD5\n#define GPIO_ODR_ODR_6                   GPIO_ODR_OD6\n#define GPIO_ODR_ODR_7                   GPIO_ODR_OD7\n#define GPIO_ODR_ODR_8                   GPIO_ODR_OD8\n#define GPIO_ODR_ODR_9                   GPIO_ODR_OD9\n#define GPIO_ODR_ODR_10                  GPIO_ODR_OD10\n#define GPIO_ODR_ODR_11                  GPIO_ODR_OD11\n#define GPIO_ODR_ODR_12                  GPIO_ODR_OD12\n#define GPIO_ODR_ODR_13                  GPIO_ODR_OD13\n#define GPIO_ODR_ODR_14                  GPIO_ODR_OD14\n#define GPIO_ODR_ODR_15                  GPIO_ODR_OD15\n\n/******************  Bits definition for GPIO_BSRR register  ******************/\n#define GPIO_BSRR_BS0_Pos                (0U)\n#define GPIO_BSRR_BS0_Msk                (0x1UL << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */\n#define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk\n#define GPIO_BSRR_BS1_Pos                (1U)\n#define GPIO_BSRR_BS1_Msk                (0x1UL << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */\n#define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk\n#define GPIO_BSRR_BS2_Pos                (2U)\n#define GPIO_BSRR_BS2_Msk                (0x1UL << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */\n#define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk\n#define GPIO_BSRR_BS3_Pos                (3U)\n#define GPIO_BSRR_BS3_Msk                (0x1UL << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */\n#define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk\n#define GPIO_BSRR_BS4_Pos                (4U)\n#define GPIO_BSRR_BS4_Msk                (0x1UL << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */\n#define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk\n#define GPIO_BSRR_BS5_Pos                (5U)\n#define GPIO_BSRR_BS5_Msk                (0x1UL << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */\n#define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk\n#define GPIO_BSRR_BS6_Pos                (6U)\n#define GPIO_BSRR_BS6_Msk                (0x1UL << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */\n#define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk\n#define GPIO_BSRR_BS7_Pos                (7U)\n#define GPIO_BSRR_BS7_Msk                (0x1UL << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */\n#define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk\n#define GPIO_BSRR_BS8_Pos                (8U)\n#define GPIO_BSRR_BS8_Msk                (0x1UL << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */\n#define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk\n#define GPIO_BSRR_BS9_Pos                (9U)\n#define GPIO_BSRR_BS9_Msk                (0x1UL << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */\n#define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk\n#define GPIO_BSRR_BS10_Pos               (10U)\n#define GPIO_BSRR_BS10_Msk               (0x1UL << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */\n#define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk\n#define GPIO_BSRR_BS11_Pos               (11U)\n#define GPIO_BSRR_BS11_Msk               (0x1UL << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */\n#define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk\n#define GPIO_BSRR_BS12_Pos               (12U)\n#define GPIO_BSRR_BS12_Msk               (0x1UL << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */\n#define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk\n#define GPIO_BSRR_BS13_Pos               (13U)\n#define GPIO_BSRR_BS13_Msk               (0x1UL << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */\n#define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk\n#define GPIO_BSRR_BS14_Pos               (14U)\n#define GPIO_BSRR_BS14_Msk               (0x1UL << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */\n#define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk\n#define GPIO_BSRR_BS15_Pos               (15U)\n#define GPIO_BSRR_BS15_Msk               (0x1UL << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */\n#define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk\n#define GPIO_BSRR_BR0_Pos                (16U)\n#define GPIO_BSRR_BR0_Msk                (0x1UL << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */\n#define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk\n#define GPIO_BSRR_BR1_Pos                (17U)\n#define GPIO_BSRR_BR1_Msk                (0x1UL << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */\n#define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk\n#define GPIO_BSRR_BR2_Pos                (18U)\n#define GPIO_BSRR_BR2_Msk                (0x1UL << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */\n#define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk\n#define GPIO_BSRR_BR3_Pos                (19U)\n#define GPIO_BSRR_BR3_Msk                (0x1UL << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */\n#define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk\n#define GPIO_BSRR_BR4_Pos                (20U)\n#define GPIO_BSRR_BR4_Msk                (0x1UL << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */\n#define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk\n#define GPIO_BSRR_BR5_Pos                (21U)\n#define GPIO_BSRR_BR5_Msk                (0x1UL << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */\n#define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk\n#define GPIO_BSRR_BR6_Pos                (22U)\n#define GPIO_BSRR_BR6_Msk                (0x1UL << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */\n#define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk\n#define GPIO_BSRR_BR7_Pos                (23U)\n#define GPIO_BSRR_BR7_Msk                (0x1UL << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */\n#define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk\n#define GPIO_BSRR_BR8_Pos                (24U)\n#define GPIO_BSRR_BR8_Msk                (0x1UL << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */\n#define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk\n#define GPIO_BSRR_BR9_Pos                (25U)\n#define GPIO_BSRR_BR9_Msk                (0x1UL << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */\n#define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk\n#define GPIO_BSRR_BR10_Pos               (26U)\n#define GPIO_BSRR_BR10_Msk               (0x1UL << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */\n#define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk\n#define GPIO_BSRR_BR11_Pos               (27U)\n#define GPIO_BSRR_BR11_Msk               (0x1UL << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */\n#define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk\n#define GPIO_BSRR_BR12_Pos               (28U)\n#define GPIO_BSRR_BR12_Msk               (0x1UL << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */\n#define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk\n#define GPIO_BSRR_BR13_Pos               (29U)\n#define GPIO_BSRR_BR13_Msk               (0x1UL << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */\n#define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk\n#define GPIO_BSRR_BR14_Pos               (30U)\n#define GPIO_BSRR_BR14_Msk               (0x1UL << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */\n#define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk\n#define GPIO_BSRR_BR15_Pos               (31U)\n#define GPIO_BSRR_BR15_Msk               (0x1UL << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */\n#define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk\n\n/* Legacy defines */\n#define GPIO_BSRR_BS_0                   GPIO_BSRR_BS0\n#define GPIO_BSRR_BS_1                   GPIO_BSRR_BS1\n#define GPIO_BSRR_BS_2                   GPIO_BSRR_BS2\n#define GPIO_BSRR_BS_3                   GPIO_BSRR_BS3\n#define GPIO_BSRR_BS_4                   GPIO_BSRR_BS4\n#define GPIO_BSRR_BS_5                   GPIO_BSRR_BS5\n#define GPIO_BSRR_BS_6                   GPIO_BSRR_BS6\n#define GPIO_BSRR_BS_7                   GPIO_BSRR_BS7\n#define GPIO_BSRR_BS_8                   GPIO_BSRR_BS8\n#define GPIO_BSRR_BS_9                   GPIO_BSRR_BS9\n#define GPIO_BSRR_BS_10                  GPIO_BSRR_BS10\n#define GPIO_BSRR_BS_11                  GPIO_BSRR_BS11\n#define GPIO_BSRR_BS_12                  GPIO_BSRR_BS12\n#define GPIO_BSRR_BS_13                  GPIO_BSRR_BS13\n#define GPIO_BSRR_BS_14                  GPIO_BSRR_BS14\n#define GPIO_BSRR_BS_15                  GPIO_BSRR_BS15\n#define GPIO_BSRR_BR_0                   GPIO_BSRR_BR0\n#define GPIO_BSRR_BR_1                   GPIO_BSRR_BR1\n#define GPIO_BSRR_BR_2                   GPIO_BSRR_BR2\n#define GPIO_BSRR_BR_3                   GPIO_BSRR_BR3\n#define GPIO_BSRR_BR_4                   GPIO_BSRR_BR4\n#define GPIO_BSRR_BR_5                   GPIO_BSRR_BR5\n#define GPIO_BSRR_BR_6                   GPIO_BSRR_BR6\n#define GPIO_BSRR_BR_7                   GPIO_BSRR_BR7\n#define GPIO_BSRR_BR_8                   GPIO_BSRR_BR8\n#define GPIO_BSRR_BR_9                   GPIO_BSRR_BR9\n#define GPIO_BSRR_BR_10                  GPIO_BSRR_BR10\n#define GPIO_BSRR_BR_11                  GPIO_BSRR_BR11\n#define GPIO_BSRR_BR_12                  GPIO_BSRR_BR12\n#define GPIO_BSRR_BR_13                  GPIO_BSRR_BR13\n#define GPIO_BSRR_BR_14                  GPIO_BSRR_BR14\n#define GPIO_BSRR_BR_15                  GPIO_BSRR_BR15\n#define GPIO_BRR_BR0                     GPIO_BSRR_BR0\n#define GPIO_BRR_BR0_Pos                 GPIO_BSRR_BR0_Pos\n#define GPIO_BRR_BR0_Msk                 GPIO_BSRR_BR0_Msk\n#define GPIO_BRR_BR1                     GPIO_BSRR_BR1\n#define GPIO_BRR_BR1_Pos                 GPIO_BSRR_BR1_Pos\n#define GPIO_BRR_BR1_Msk                 GPIO_BSRR_BR1_Msk\n#define GPIO_BRR_BR2                     GPIO_BSRR_BR2\n#define GPIO_BRR_BR2_Pos                 GPIO_BSRR_BR2_Pos\n#define GPIO_BRR_BR2_Msk                 GPIO_BSRR_BR2_Msk\n#define GPIO_BRR_BR3                     GPIO_BSRR_BR3\n#define GPIO_BRR_BR3_Pos                 GPIO_BSRR_BR3_Pos\n#define GPIO_BRR_BR3_Msk                 GPIO_BSRR_BR3_Msk\n#define GPIO_BRR_BR4                     GPIO_BSRR_BR4\n#define GPIO_BRR_BR4_Pos                 GPIO_BSRR_BR4_Pos\n#define GPIO_BRR_BR4_Msk                 GPIO_BSRR_BR4_Msk\n#define GPIO_BRR_BR5                     GPIO_BSRR_BR5\n#define GPIO_BRR_BR5_Pos                 GPIO_BSRR_BR5_Pos\n#define GPIO_BRR_BR5_Msk                 GPIO_BSRR_BR5_Msk\n#define GPIO_BRR_BR6                     GPIO_BSRR_BR6\n#define GPIO_BRR_BR6_Pos                 GPIO_BSRR_BR6_Pos\n#define GPIO_BRR_BR6_Msk                 GPIO_BSRR_BR6_Msk\n#define GPIO_BRR_BR7                     GPIO_BSRR_BR7\n#define GPIO_BRR_BR7_Pos                 GPIO_BSRR_BR7_Pos\n#define GPIO_BRR_BR7_Msk                 GPIO_BSRR_BR7_Msk\n#define GPIO_BRR_BR8                     GPIO_BSRR_BR8\n#define GPIO_BRR_BR8_Pos                 GPIO_BSRR_BR8_Pos\n#define GPIO_BRR_BR8_Msk                 GPIO_BSRR_BR8_Msk\n#define GPIO_BRR_BR9                     GPIO_BSRR_BR9\n#define GPIO_BRR_BR9_Pos                 GPIO_BSRR_BR9_Pos\n#define GPIO_BRR_BR9_Msk                 GPIO_BSRR_BR9_Msk\n#define GPIO_BRR_BR10                    GPIO_BSRR_BR10\n#define GPIO_BRR_BR10_Pos                GPIO_BSRR_BR10_Pos\n#define GPIO_BRR_BR10_Msk                GPIO_BSRR_BR10_Msk\n#define GPIO_BRR_BR11                    GPIO_BSRR_BR11\n#define GPIO_BRR_BR11_Pos                GPIO_BSRR_BR11_Pos\n#define GPIO_BRR_BR11_Msk                GPIO_BSRR_BR11_Msk\n#define GPIO_BRR_BR12                    GPIO_BSRR_BR12\n#define GPIO_BRR_BR12_Pos                GPIO_BSRR_BR12_Pos\n#define GPIO_BRR_BR12_Msk                GPIO_BSRR_BR12_Msk\n#define GPIO_BRR_BR13                    GPIO_BSRR_BR13\n#define GPIO_BRR_BR13_Pos                GPIO_BSRR_BR13_Pos\n#define GPIO_BRR_BR13_Msk                GPIO_BSRR_BR13_Msk\n#define GPIO_BRR_BR14                    GPIO_BSRR_BR14\n#define GPIO_BRR_BR14_Pos                GPIO_BSRR_BR14_Pos\n#define GPIO_BRR_BR14_Msk                GPIO_BSRR_BR14_Msk\n#define GPIO_BRR_BR15                    GPIO_BSRR_BR15\n#define GPIO_BRR_BR15_Pos                GPIO_BSRR_BR15_Pos\n#define GPIO_BRR_BR15_Msk                GPIO_BSRR_BR15_Msk\n/****************** Bit definition for GPIO_LCKR register *********************/\n#define GPIO_LCKR_LCK0_Pos               (0U)\n#define GPIO_LCKR_LCK0_Msk               (0x1UL << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */\n#define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk\n#define GPIO_LCKR_LCK1_Pos               (1U)\n#define GPIO_LCKR_LCK1_Msk               (0x1UL << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */\n#define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk\n#define GPIO_LCKR_LCK2_Pos               (2U)\n#define GPIO_LCKR_LCK2_Msk               (0x1UL << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */\n#define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk\n#define GPIO_LCKR_LCK3_Pos               (3U)\n#define GPIO_LCKR_LCK3_Msk               (0x1UL << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */\n#define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk\n#define GPIO_LCKR_LCK4_Pos               (4U)\n#define GPIO_LCKR_LCK4_Msk               (0x1UL << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */\n#define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk\n#define GPIO_LCKR_LCK5_Pos               (5U)\n#define GPIO_LCKR_LCK5_Msk               (0x1UL << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */\n#define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk\n#define GPIO_LCKR_LCK6_Pos               (6U)\n#define GPIO_LCKR_LCK6_Msk               (0x1UL << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */\n#define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk\n#define GPIO_LCKR_LCK7_Pos               (7U)\n#define GPIO_LCKR_LCK7_Msk               (0x1UL << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */\n#define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk\n#define GPIO_LCKR_LCK8_Pos               (8U)\n#define GPIO_LCKR_LCK8_Msk               (0x1UL << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */\n#define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk\n#define GPIO_LCKR_LCK9_Pos               (9U)\n#define GPIO_LCKR_LCK9_Msk               (0x1UL << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */\n#define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk\n#define GPIO_LCKR_LCK10_Pos              (10U)\n#define GPIO_LCKR_LCK10_Msk              (0x1UL << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */\n#define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk\n#define GPIO_LCKR_LCK11_Pos              (11U)\n#define GPIO_LCKR_LCK11_Msk              (0x1UL << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */\n#define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk\n#define GPIO_LCKR_LCK12_Pos              (12U)\n#define GPIO_LCKR_LCK12_Msk              (0x1UL << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */\n#define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk\n#define GPIO_LCKR_LCK13_Pos              (13U)\n#define GPIO_LCKR_LCK13_Msk              (0x1UL << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */\n#define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk\n#define GPIO_LCKR_LCK14_Pos              (14U)\n#define GPIO_LCKR_LCK14_Msk              (0x1UL << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */\n#define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk\n#define GPIO_LCKR_LCK15_Pos              (15U)\n#define GPIO_LCKR_LCK15_Msk              (0x1UL << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */\n#define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk\n#define GPIO_LCKR_LCKK_Pos               (16U)\n#define GPIO_LCKR_LCKK_Msk               (0x1UL << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */\n#define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk\n/****************** Bit definition for GPIO_AFRL register *********************/\n#define GPIO_AFRL_AFSEL0_Pos             (0U)\n#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk\n#define GPIO_AFRL_AFSEL0_0               (0x1UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRL_AFSEL0_1               (0x2UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRL_AFSEL0_2               (0x4UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRL_AFSEL0_3               (0x8UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRL_AFSEL1_Pos             (4U)\n#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk\n#define GPIO_AFRL_AFSEL1_0               (0x1UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRL_AFSEL1_1               (0x2UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRL_AFSEL1_2               (0x4UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRL_AFSEL1_3               (0x8UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRL_AFSEL2_Pos             (8U)\n#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */\n#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk\n#define GPIO_AFRL_AFSEL2_0               (0x1UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */\n#define GPIO_AFRL_AFSEL2_1               (0x2UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */\n#define GPIO_AFRL_AFSEL2_2               (0x4UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */\n#define GPIO_AFRL_AFSEL2_3               (0x8UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */\n#define GPIO_AFRL_AFSEL3_Pos             (12U)\n#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */\n#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk\n#define GPIO_AFRL_AFSEL3_0               (0x1UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */\n#define GPIO_AFRL_AFSEL3_1               (0x2UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */\n#define GPIO_AFRL_AFSEL3_2               (0x4UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */\n#define GPIO_AFRL_AFSEL3_3               (0x8UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */\n#define GPIO_AFRL_AFSEL4_Pos             (16U)\n#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */\n#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk\n#define GPIO_AFRL_AFSEL4_0               (0x1UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */\n#define GPIO_AFRL_AFSEL4_1               (0x2UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */\n#define GPIO_AFRL_AFSEL4_2               (0x4UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */\n#define GPIO_AFRL_AFSEL4_3               (0x8UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */\n#define GPIO_AFRL_AFSEL5_Pos             (20U)\n#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */\n#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk\n#define GPIO_AFRL_AFSEL5_0               (0x1UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */\n#define GPIO_AFRL_AFSEL5_1               (0x2UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */\n#define GPIO_AFRL_AFSEL5_2               (0x4UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */\n#define GPIO_AFRL_AFSEL5_3               (0x8UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */\n#define GPIO_AFRL_AFSEL6_Pos             (24U)\n#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */\n#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk\n#define GPIO_AFRL_AFSEL6_0               (0x1UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */\n#define GPIO_AFRL_AFSEL6_1               (0x2UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */\n#define GPIO_AFRL_AFSEL6_2               (0x4UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */\n#define GPIO_AFRL_AFSEL6_3               (0x8UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */\n#define GPIO_AFRL_AFSEL7_Pos             (28U)\n#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */\n#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk\n#define GPIO_AFRL_AFSEL7_0               (0x1UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */\n#define GPIO_AFRL_AFSEL7_1               (0x2UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */\n#define GPIO_AFRL_AFSEL7_2               (0x4UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */\n#define GPIO_AFRL_AFSEL7_3               (0x8UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFSEL0\n#define GPIO_AFRL_AFRL0_0                GPIO_AFRL_AFSEL0_0\n#define GPIO_AFRL_AFRL0_1                GPIO_AFRL_AFSEL0_1\n#define GPIO_AFRL_AFRL0_2                GPIO_AFRL_AFSEL0_2\n#define GPIO_AFRL_AFRL0_3                GPIO_AFRL_AFSEL0_3\n#define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFSEL1\n#define GPIO_AFRL_AFRL1_0                GPIO_AFRL_AFSEL1_0\n#define GPIO_AFRL_AFRL1_1                GPIO_AFRL_AFSEL1_1\n#define GPIO_AFRL_AFRL1_2                GPIO_AFRL_AFSEL1_2\n#define GPIO_AFRL_AFRL1_3                GPIO_AFRL_AFSEL1_3\n#define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFSEL2\n#define GPIO_AFRL_AFRL2_0                GPIO_AFRL_AFSEL2_0\n#define GPIO_AFRL_AFRL2_1                GPIO_AFRL_AFSEL2_1\n#define GPIO_AFRL_AFRL2_2                GPIO_AFRL_AFSEL2_2\n#define GPIO_AFRL_AFRL2_3                GPIO_AFRL_AFSEL2_3\n#define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFSEL3\n#define GPIO_AFRL_AFRL3_0                GPIO_AFRL_AFSEL3_0\n#define GPIO_AFRL_AFRL3_1                GPIO_AFRL_AFSEL3_1\n#define GPIO_AFRL_AFRL3_2                GPIO_AFRL_AFSEL3_2\n#define GPIO_AFRL_AFRL3_3                GPIO_AFRL_AFSEL3_3\n#define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFSEL4\n#define GPIO_AFRL_AFRL4_0                GPIO_AFRL_AFSEL4_0\n#define GPIO_AFRL_AFRL4_1                GPIO_AFRL_AFSEL4_1\n#define GPIO_AFRL_AFRL4_2                GPIO_AFRL_AFSEL4_2\n#define GPIO_AFRL_AFRL4_3                GPIO_AFRL_AFSEL4_3\n#define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFSEL5\n#define GPIO_AFRL_AFRL5_0                GPIO_AFRL_AFSEL5_0\n#define GPIO_AFRL_AFRL5_1                GPIO_AFRL_AFSEL5_1\n#define GPIO_AFRL_AFRL5_2                GPIO_AFRL_AFSEL5_2\n#define GPIO_AFRL_AFRL5_3                GPIO_AFRL_AFSEL5_3\n#define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFSEL6\n#define GPIO_AFRL_AFRL6_0                GPIO_AFRL_AFSEL6_0\n#define GPIO_AFRL_AFRL6_1                GPIO_AFRL_AFSEL6_1\n#define GPIO_AFRL_AFRL6_2                GPIO_AFRL_AFSEL6_2\n#define GPIO_AFRL_AFRL6_3                GPIO_AFRL_AFSEL6_3\n#define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFSEL7\n#define GPIO_AFRL_AFRL7_0                GPIO_AFRL_AFSEL7_0\n#define GPIO_AFRL_AFRL7_1                GPIO_AFRL_AFSEL7_1\n#define GPIO_AFRL_AFRL7_2                GPIO_AFRL_AFSEL7_2\n#define GPIO_AFRL_AFRL7_3                GPIO_AFRL_AFSEL7_3\n\n/****************** Bit definition for GPIO_AFRH register *********************/\n#define GPIO_AFRH_AFSEL8_Pos             (0U)\n#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk\n#define GPIO_AFRH_AFSEL8_0               (0x1UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRH_AFSEL8_1               (0x2UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRH_AFSEL8_2               (0x4UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRH_AFSEL8_3               (0x8UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRH_AFSEL9_Pos             (4U)\n#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk\n#define GPIO_AFRH_AFSEL9_0               (0x1UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRH_AFSEL9_1               (0x2UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRH_AFSEL9_2               (0x4UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRH_AFSEL9_3               (0x8UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRH_AFSEL10_Pos            (8U)\n#define GPIO_AFRH_AFSEL10_Msk            (0xFUL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */\n#define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk\n#define GPIO_AFRH_AFSEL10_0              (0x1UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */\n#define GPIO_AFRH_AFSEL10_1              (0x2UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */\n#define GPIO_AFRH_AFSEL10_2              (0x4UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */\n#define GPIO_AFRH_AFSEL10_3              (0x8UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */\n#define GPIO_AFRH_AFSEL11_Pos            (12U)\n#define GPIO_AFRH_AFSEL11_Msk            (0xFUL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */\n#define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk\n#define GPIO_AFRH_AFSEL11_0              (0x1UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */\n#define GPIO_AFRH_AFSEL11_1              (0x2UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */\n#define GPIO_AFRH_AFSEL11_2              (0x4UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */\n#define GPIO_AFRH_AFSEL11_3              (0x8UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */\n#define GPIO_AFRH_AFSEL12_Pos            (16U)\n#define GPIO_AFRH_AFSEL12_Msk            (0xFUL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */\n#define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk\n#define GPIO_AFRH_AFSEL12_0              (0x1UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */\n#define GPIO_AFRH_AFSEL12_1              (0x2UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */\n#define GPIO_AFRH_AFSEL12_2              (0x4UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */\n#define GPIO_AFRH_AFSEL12_3              (0x8UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */\n#define GPIO_AFRH_AFSEL13_Pos            (20U)\n#define GPIO_AFRH_AFSEL13_Msk            (0xFUL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */\n#define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk\n#define GPIO_AFRH_AFSEL13_0              (0x1UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */\n#define GPIO_AFRH_AFSEL13_1              (0x2UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */\n#define GPIO_AFRH_AFSEL13_2              (0x4UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */\n#define GPIO_AFRH_AFSEL13_3              (0x8UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */\n#define GPIO_AFRH_AFSEL14_Pos            (24U)\n#define GPIO_AFRH_AFSEL14_Msk            (0xFUL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */\n#define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk\n#define GPIO_AFRH_AFSEL14_0              (0x1UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */\n#define GPIO_AFRH_AFSEL14_1              (0x2UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */\n#define GPIO_AFRH_AFSEL14_2              (0x4UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */\n#define GPIO_AFRH_AFSEL14_3              (0x8UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */\n#define GPIO_AFRH_AFSEL15_Pos            (28U)\n#define GPIO_AFRH_AFSEL15_Msk            (0xFUL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */\n#define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk\n#define GPIO_AFRH_AFSEL15_0              (0x1UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */\n#define GPIO_AFRH_AFSEL15_1              (0x2UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */\n#define GPIO_AFRH_AFSEL15_2              (0x4UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */\n#define GPIO_AFRH_AFSEL15_3              (0x8UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFSEL8\n#define GPIO_AFRH_AFRH0_0                GPIO_AFRH_AFSEL8_0\n#define GPIO_AFRH_AFRH0_1                GPIO_AFRH_AFSEL8_1\n#define GPIO_AFRH_AFRH0_2                GPIO_AFRH_AFSEL8_2\n#define GPIO_AFRH_AFRH0_3                GPIO_AFRH_AFSEL8_3\n#define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFSEL9\n#define GPIO_AFRH_AFRH1_0                GPIO_AFRH_AFSEL9_0\n#define GPIO_AFRH_AFRH1_1                GPIO_AFRH_AFSEL9_1\n#define GPIO_AFRH_AFRH1_2                GPIO_AFRH_AFSEL9_2\n#define GPIO_AFRH_AFRH1_3                GPIO_AFRH_AFSEL9_3\n#define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFSEL10\n#define GPIO_AFRH_AFRH2_0                GPIO_AFRH_AFSEL10_0\n#define GPIO_AFRH_AFRH2_1                GPIO_AFRH_AFSEL10_1\n#define GPIO_AFRH_AFRH2_2                GPIO_AFRH_AFSEL10_2\n#define GPIO_AFRH_AFRH2_3                GPIO_AFRH_AFSEL10_3\n#define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFSEL11\n#define GPIO_AFRH_AFRH3_0                GPIO_AFRH_AFSEL11_0\n#define GPIO_AFRH_AFRH3_1                GPIO_AFRH_AFSEL11_1\n#define GPIO_AFRH_AFRH3_2                GPIO_AFRH_AFSEL11_2\n#define GPIO_AFRH_AFRH3_3                GPIO_AFRH_AFSEL11_3\n#define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFSEL12\n#define GPIO_AFRH_AFRH4_0                GPIO_AFRH_AFSEL12_0\n#define GPIO_AFRH_AFRH4_1                GPIO_AFRH_AFSEL12_1\n#define GPIO_AFRH_AFRH4_2                GPIO_AFRH_AFSEL12_2\n#define GPIO_AFRH_AFRH4_3                GPIO_AFRH_AFSEL12_3\n#define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFSEL13\n#define GPIO_AFRH_AFRH5_0                GPIO_AFRH_AFSEL13_0\n#define GPIO_AFRH_AFRH5_1                GPIO_AFRH_AFSEL13_1\n#define GPIO_AFRH_AFRH5_2                GPIO_AFRH_AFSEL13_2\n#define GPIO_AFRH_AFRH5_3                GPIO_AFRH_AFSEL13_3\n#define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFSEL14\n#define GPIO_AFRH_AFRH6_0                GPIO_AFRH_AFSEL14_0\n#define GPIO_AFRH_AFRH6_1                GPIO_AFRH_AFSEL14_1\n#define GPIO_AFRH_AFRH6_2                GPIO_AFRH_AFSEL14_2\n#define GPIO_AFRH_AFRH6_3                GPIO_AFRH_AFSEL14_3\n#define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFSEL15\n#define GPIO_AFRH_AFRH7_0                GPIO_AFRH_AFSEL15_0\n#define GPIO_AFRH_AFRH7_1                GPIO_AFRH_AFSEL15_1\n#define GPIO_AFRH_AFRH7_2                GPIO_AFRH_AFSEL15_2\n#define GPIO_AFRH_AFRH7_3                GPIO_AFRH_AFSEL15_3\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Inter-integrated Circuit Interface                    */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for I2C_CR1 register  ********************/\n#define I2C_CR1_PE_Pos            (0U)\n#define I2C_CR1_PE_Msk            (0x1UL << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */\n#define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */\n#define I2C_CR1_SMBUS_Pos         (1U)\n#define I2C_CR1_SMBUS_Msk         (0x1UL << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */\n#define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */\n#define I2C_CR1_SMBTYPE_Pos       (3U)\n#define I2C_CR1_SMBTYPE_Msk       (0x1UL << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */\n#define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */\n#define I2C_CR1_ENARP_Pos         (4U)\n#define I2C_CR1_ENARP_Msk         (0x1UL << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */\n#define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */\n#define I2C_CR1_ENPEC_Pos         (5U)\n#define I2C_CR1_ENPEC_Msk         (0x1UL << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */\n#define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */\n#define I2C_CR1_ENGC_Pos          (6U)\n#define I2C_CR1_ENGC_Msk          (0x1UL << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */\n#define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */\n#define I2C_CR1_NOSTRETCH_Pos     (7U)\n#define I2C_CR1_NOSTRETCH_Msk     (0x1UL << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */\n#define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */\n#define I2C_CR1_START_Pos         (8U)\n#define I2C_CR1_START_Msk         (0x1UL << I2C_CR1_START_Pos)                  /*!< 0x00000100 */\n#define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */\n#define I2C_CR1_STOP_Pos          (9U)\n#define I2C_CR1_STOP_Msk          (0x1UL << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */\n#define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */\n#define I2C_CR1_ACK_Pos           (10U)\n#define I2C_CR1_ACK_Msk           (0x1UL << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */\n#define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */\n#define I2C_CR1_POS_Pos           (11U)\n#define I2C_CR1_POS_Msk           (0x1UL << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */\n#define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */\n#define I2C_CR1_PEC_Pos           (12U)\n#define I2C_CR1_PEC_Msk           (0x1UL << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */\n#define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */\n#define I2C_CR1_ALERT_Pos         (13U)\n#define I2C_CR1_ALERT_Msk         (0x1UL << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */\n#define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */\n#define I2C_CR1_SWRST_Pos         (15U)\n#define I2C_CR1_SWRST_Msk         (0x1UL << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */\n#define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */\n\n/*******************  Bit definition for I2C_CR2 register  ********************/\n#define I2C_CR2_FREQ_Pos          (0U)\n#define I2C_CR2_FREQ_Msk          (0x3FUL << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */\n#define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */\n#define I2C_CR2_FREQ_0            (0x01UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */\n#define I2C_CR2_FREQ_1            (0x02UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */\n#define I2C_CR2_FREQ_2            (0x04UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */\n#define I2C_CR2_FREQ_3            (0x08UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */\n#define I2C_CR2_FREQ_4            (0x10UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */\n#define I2C_CR2_FREQ_5            (0x20UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */\n\n#define I2C_CR2_ITERREN_Pos       (8U)\n#define I2C_CR2_ITERREN_Msk       (0x1UL << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */\n#define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */\n#define I2C_CR2_ITEVTEN_Pos       (9U)\n#define I2C_CR2_ITEVTEN_Msk       (0x1UL << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */\n#define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */\n#define I2C_CR2_ITBUFEN_Pos       (10U)\n#define I2C_CR2_ITBUFEN_Msk       (0x1UL << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */\n#define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */\n#define I2C_CR2_DMAEN_Pos         (11U)\n#define I2C_CR2_DMAEN_Msk         (0x1UL << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */\n#define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */\n#define I2C_CR2_LAST_Pos          (12U)\n#define I2C_CR2_LAST_Msk          (0x1UL << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */\n#define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */\n\n/*******************  Bit definition for I2C_OAR1 register  *******************/\n#define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */\n#define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */\n\n#define I2C_OAR1_ADD0_Pos         (0U)\n#define I2C_OAR1_ADD0_Msk         (0x1UL << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */\n#define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */\n#define I2C_OAR1_ADD1_Pos         (1U)\n#define I2C_OAR1_ADD1_Msk         (0x1UL << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */\n#define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */\n#define I2C_OAR1_ADD2_Pos         (2U)\n#define I2C_OAR1_ADD2_Msk         (0x1UL << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */\n#define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */\n#define I2C_OAR1_ADD3_Pos         (3U)\n#define I2C_OAR1_ADD3_Msk         (0x1UL << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */\n#define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */\n#define I2C_OAR1_ADD4_Pos         (4U)\n#define I2C_OAR1_ADD4_Msk         (0x1UL << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */\n#define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */\n#define I2C_OAR1_ADD5_Pos         (5U)\n#define I2C_OAR1_ADD5_Msk         (0x1UL << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */\n#define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */\n#define I2C_OAR1_ADD6_Pos         (6U)\n#define I2C_OAR1_ADD6_Msk         (0x1UL << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */\n#define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */\n#define I2C_OAR1_ADD7_Pos         (7U)\n#define I2C_OAR1_ADD7_Msk         (0x1UL << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */\n#define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */\n#define I2C_OAR1_ADD8_Pos         (8U)\n#define I2C_OAR1_ADD8_Msk         (0x1UL << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */\n#define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */\n#define I2C_OAR1_ADD9_Pos         (9U)\n#define I2C_OAR1_ADD9_Msk         (0x1UL << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */\n#define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */\n\n#define I2C_OAR1_ADDMODE_Pos      (15U)\n#define I2C_OAR1_ADDMODE_Msk      (0x1UL << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */\n#define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */\n\n/*******************  Bit definition for I2C_OAR2 register  *******************/\n#define I2C_OAR2_ENDUAL_Pos       (0U)\n#define I2C_OAR2_ENDUAL_Msk       (0x1UL << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */\n#define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */\n#define I2C_OAR2_ADD2_Pos         (1U)\n#define I2C_OAR2_ADD2_Msk         (0x7FUL << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */\n#define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */\n\n/********************  Bit definition for I2C_DR register  ********************/\n#define I2C_DR_DR_Pos             (0U)\n#define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */\n#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */\n\n/*******************  Bit definition for I2C_SR1 register  ********************/\n#define I2C_SR1_SB_Pos            (0U)\n#define I2C_SR1_SB_Msk            (0x1UL << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */\n#define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */\n#define I2C_SR1_ADDR_Pos          (1U)\n#define I2C_SR1_ADDR_Msk          (0x1UL << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */\n#define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */\n#define I2C_SR1_BTF_Pos           (2U)\n#define I2C_SR1_BTF_Msk           (0x1UL << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */\n#define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */\n#define I2C_SR1_ADD10_Pos         (3U)\n#define I2C_SR1_ADD10_Msk         (0x1UL << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */\n#define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */\n#define I2C_SR1_STOPF_Pos         (4U)\n#define I2C_SR1_STOPF_Msk         (0x1UL << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */\n#define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */\n#define I2C_SR1_RXNE_Pos          (6U)\n#define I2C_SR1_RXNE_Msk          (0x1UL << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */\n#define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */\n#define I2C_SR1_TXE_Pos           (7U)\n#define I2C_SR1_TXE_Msk           (0x1UL << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */\n#define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */\n#define I2C_SR1_BERR_Pos          (8U)\n#define I2C_SR1_BERR_Msk          (0x1UL << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */\n#define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */\n#define I2C_SR1_ARLO_Pos          (9U)\n#define I2C_SR1_ARLO_Msk          (0x1UL << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */\n#define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */\n#define I2C_SR1_AF_Pos            (10U)\n#define I2C_SR1_AF_Msk            (0x1UL << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */\n#define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */\n#define I2C_SR1_OVR_Pos           (11U)\n#define I2C_SR1_OVR_Msk           (0x1UL << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */\n#define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */\n#define I2C_SR1_PECERR_Pos        (12U)\n#define I2C_SR1_PECERR_Msk        (0x1UL << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */\n#define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */\n#define I2C_SR1_TIMEOUT_Pos       (14U)\n#define I2C_SR1_TIMEOUT_Msk       (0x1UL << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */\n#define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */\n#define I2C_SR1_SMBALERT_Pos      (15U)\n#define I2C_SR1_SMBALERT_Msk      (0x1UL << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */\n#define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */\n\n/*******************  Bit definition for I2C_SR2 register  ********************/\n#define I2C_SR2_MSL_Pos           (0U)\n#define I2C_SR2_MSL_Msk           (0x1UL << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */\n#define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */\n#define I2C_SR2_BUSY_Pos          (1U)\n#define I2C_SR2_BUSY_Msk          (0x1UL << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */\n#define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */\n#define I2C_SR2_TRA_Pos           (2U)\n#define I2C_SR2_TRA_Msk           (0x1UL << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */\n#define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */\n#define I2C_SR2_GENCALL_Pos       (4U)\n#define I2C_SR2_GENCALL_Msk       (0x1UL << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */\n#define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */\n#define I2C_SR2_SMBDEFAULT_Pos    (5U)\n#define I2C_SR2_SMBDEFAULT_Msk    (0x1UL << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */\n#define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */\n#define I2C_SR2_SMBHOST_Pos       (6U)\n#define I2C_SR2_SMBHOST_Msk       (0x1UL << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */\n#define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */\n#define I2C_SR2_DUALF_Pos         (7U)\n#define I2C_SR2_DUALF_Msk         (0x1UL << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */\n#define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */\n#define I2C_SR2_PEC_Pos           (8U)\n#define I2C_SR2_PEC_Msk           (0xFFUL << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */\n#define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */\n\n/*******************  Bit definition for I2C_CCR register  ********************/\n#define I2C_CCR_CCR_Pos           (0U)\n#define I2C_CCR_CCR_Msk           (0xFFFUL << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */\n#define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */\n#define I2C_CCR_DUTY_Pos          (14U)\n#define I2C_CCR_DUTY_Msk          (0x1UL << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */\n#define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */\n#define I2C_CCR_FS_Pos            (15U)\n#define I2C_CCR_FS_Msk            (0x1UL << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */\n#define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */\n\n/******************  Bit definition for I2C_TRISE register  *******************/\n#define I2C_TRISE_TRISE_Pos       (0U)\n#define I2C_TRISE_TRISE_Msk       (0x3FUL << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */\n#define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */\n\n/******************  Bit definition for I2C_FLTR register  *******************/\n#define I2C_FLTR_DNF_Pos          (0U)\n#define I2C_FLTR_DNF_Msk          (0xFUL << I2C_FLTR_DNF_Pos)                   /*!< 0x0000000F */\n#define I2C_FLTR_DNF              I2C_FLTR_DNF_Msk                             /*!<Digital Noise Filter */\n#define I2C_FLTR_ANOFF_Pos        (4U)\n#define I2C_FLTR_ANOFF_Msk        (0x1UL << I2C_FLTR_ANOFF_Pos)                 /*!< 0x00000010 */\n#define I2C_FLTR_ANOFF            I2C_FLTR_ANOFF_Msk                           /*!<Analog Noise Filter OFF */\n\n/******************************************************************************/\n/*                                                                            */\n/*        Fast Mode Plus Inter-integrated Circuit Interface (I2C)             */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for I2C_CR1 register  *******************/\n#define FMPI2C_CR1_PE_Pos               (0U)\n#define FMPI2C_CR1_PE_Msk               (0x1UL << FMPI2C_CR1_PE_Pos)            /*!< 0x00000001 */\n#define FMPI2C_CR1_PE                   FMPI2C_CR1_PE_Msk                      /*!< Peripheral enable                   */\n#define FMPI2C_CR1_TXIE_Pos             (1U)\n#define FMPI2C_CR1_TXIE_Msk             (0x1UL << FMPI2C_CR1_TXIE_Pos)          /*!< 0x00000002 */\n#define FMPI2C_CR1_TXIE                 FMPI2C_CR1_TXIE_Msk                    /*!< TX interrupt enable                 */\n#define FMPI2C_CR1_RXIE_Pos             (2U)\n#define FMPI2C_CR1_RXIE_Msk             (0x1UL << FMPI2C_CR1_RXIE_Pos)          /*!< 0x00000004 */\n#define FMPI2C_CR1_RXIE                 FMPI2C_CR1_RXIE_Msk                    /*!< RX interrupt enable                 */\n#define FMPI2C_CR1_ADDRIE_Pos           (3U)\n#define FMPI2C_CR1_ADDRIE_Msk           (0x1UL << FMPI2C_CR1_ADDRIE_Pos)        /*!< 0x00000008 */\n#define FMPI2C_CR1_ADDRIE               FMPI2C_CR1_ADDRIE_Msk                  /*!< Address match interrupt enable      */\n#define FMPI2C_CR1_NACKIE_Pos           (4U)\n#define FMPI2C_CR1_NACKIE_Msk           (0x1UL << FMPI2C_CR1_NACKIE_Pos)        /*!< 0x00000010 */\n#define FMPI2C_CR1_NACKIE               FMPI2C_CR1_NACKIE_Msk                  /*!< NACK received interrupt enable      */\n#define FMPI2C_CR1_STOPIE_Pos           (5U)\n#define FMPI2C_CR1_STOPIE_Msk           (0x1UL << FMPI2C_CR1_STOPIE_Pos)        /*!< 0x00000020 */\n#define FMPI2C_CR1_STOPIE               FMPI2C_CR1_STOPIE_Msk                  /*!< STOP detection interrupt enable     */\n#define FMPI2C_CR1_TCIE_Pos             (6U)\n#define FMPI2C_CR1_TCIE_Msk             (0x1UL << FMPI2C_CR1_TCIE_Pos)          /*!< 0x00000040 */\n#define FMPI2C_CR1_TCIE                 FMPI2C_CR1_TCIE_Msk                    /*!< Transfer complete interrupt enable  */\n#define FMPI2C_CR1_ERRIE_Pos            (7U)\n#define FMPI2C_CR1_ERRIE_Msk            (0x1UL << FMPI2C_CR1_ERRIE_Pos)         /*!< 0x00000080 */\n#define FMPI2C_CR1_ERRIE                FMPI2C_CR1_ERRIE_Msk                   /*!< Errors interrupt enable             */\n#define FMPI2C_CR1_DNF_Pos              (8U)\n#define FMPI2C_CR1_DNF_Msk              (0xFUL << FMPI2C_CR1_DNF_Pos)           /*!< 0x00000F00 */\n#define FMPI2C_CR1_DNF                  FMPI2C_CR1_DNF_Msk                     /*!< Digital noise filter                */\n#define FMPI2C_CR1_ANFOFF_Pos           (12U)\n#define FMPI2C_CR1_ANFOFF_Msk           (0x1UL << FMPI2C_CR1_ANFOFF_Pos)        /*!< 0x00001000 */\n#define FMPI2C_CR1_ANFOFF               FMPI2C_CR1_ANFOFF_Msk                  /*!< Analog noise filter OFF             */\n#define FMPI2C_CR1_TXDMAEN_Pos          (14U)\n#define FMPI2C_CR1_TXDMAEN_Msk          (0x1UL << FMPI2C_CR1_TXDMAEN_Pos)       /*!< 0x00004000 */\n#define FMPI2C_CR1_TXDMAEN              FMPI2C_CR1_TXDMAEN_Msk                 /*!< DMA transmission requests enable    */\n#define FMPI2C_CR1_RXDMAEN_Pos          (15U)\n#define FMPI2C_CR1_RXDMAEN_Msk          (0x1UL << FMPI2C_CR1_RXDMAEN_Pos)       /*!< 0x00008000 */\n#define FMPI2C_CR1_RXDMAEN              FMPI2C_CR1_RXDMAEN_Msk                 /*!< DMA reception requests enable       */\n#define FMPI2C_CR1_SBC_Pos              (16U)\n#define FMPI2C_CR1_SBC_Msk              (0x1UL << FMPI2C_CR1_SBC_Pos)           /*!< 0x00010000 */\n#define FMPI2C_CR1_SBC                  FMPI2C_CR1_SBC_Msk                     /*!< Slave byte control                  */\n#define FMPI2C_CR1_NOSTRETCH_Pos        (17U)\n#define FMPI2C_CR1_NOSTRETCH_Msk        (0x1UL << FMPI2C_CR1_NOSTRETCH_Pos)     /*!< 0x00020000 */\n#define FMPI2C_CR1_NOSTRETCH            FMPI2C_CR1_NOSTRETCH_Msk               /*!< Clock stretching disable            */\n#define FMPI2C_CR1_GCEN_Pos             (19U)\n#define FMPI2C_CR1_GCEN_Msk             (0x1UL << FMPI2C_CR1_GCEN_Pos)          /*!< 0x00080000 */\n#define FMPI2C_CR1_GCEN                 FMPI2C_CR1_GCEN_Msk                    /*!< General call enable                 */\n#define FMPI2C_CR1_SMBHEN_Pos           (20U)\n#define FMPI2C_CR1_SMBHEN_Msk           (0x1UL << FMPI2C_CR1_SMBHEN_Pos)        /*!< 0x00100000 */\n#define FMPI2C_CR1_SMBHEN               FMPI2C_CR1_SMBHEN_Msk                  /*!< SMBus host address enable           */\n#define FMPI2C_CR1_SMBDEN_Pos           (21U)\n#define FMPI2C_CR1_SMBDEN_Msk           (0x1UL << FMPI2C_CR1_SMBDEN_Pos)        /*!< 0x00200000 */\n#define FMPI2C_CR1_SMBDEN               FMPI2C_CR1_SMBDEN_Msk                  /*!< SMBus device default address enable */\n#define FMPI2C_CR1_ALERTEN_Pos          (22U)\n#define FMPI2C_CR1_ALERTEN_Msk          (0x1UL << FMPI2C_CR1_ALERTEN_Pos)       /*!< 0x00400000 */\n#define FMPI2C_CR1_ALERTEN              FMPI2C_CR1_ALERTEN_Msk                 /*!< SMBus alert enable                  */\n#define FMPI2C_CR1_PECEN_Pos            (23U)\n#define FMPI2C_CR1_PECEN_Msk            (0x1UL << FMPI2C_CR1_PECEN_Pos)         /*!< 0x00800000 */\n#define FMPI2C_CR1_PECEN                FMPI2C_CR1_PECEN_Msk                   /*!< PEC enable                          */\n\n/* Legacy Defines */\n#define FMPI2C_CR1_DFN_Pos              FMPI2C_CR1_DNF_Pos\n#define FMPI2C_CR1_DFN_Msk              FMPI2C_CR1_DNF_Msk\n#define FMPI2C_CR1_DFN                  FMPI2C_CR1_DNF\n/******************  Bit definition for I2C_CR2 register  ********************/\n#define FMPI2C_CR2_SADD_Pos             (0U)\n#define FMPI2C_CR2_SADD_Msk             (0x3FFUL << FMPI2C_CR2_SADD_Pos)        /*!< 0x000003FF */\n#define FMPI2C_CR2_SADD                 FMPI2C_CR2_SADD_Msk                    /*!< Slave address (master mode)                             */\n#define FMPI2C_CR2_RD_WRN_Pos           (10U)\n#define FMPI2C_CR2_RD_WRN_Msk           (0x1UL << FMPI2C_CR2_RD_WRN_Pos)        /*!< 0x00000400 */\n#define FMPI2C_CR2_RD_WRN               FMPI2C_CR2_RD_WRN_Msk                  /*!< Transfer direction (master mode)                        */\n#define FMPI2C_CR2_ADD10_Pos            (11U)\n#define FMPI2C_CR2_ADD10_Msk            (0x1UL << FMPI2C_CR2_ADD10_Pos)         /*!< 0x00000800 */\n#define FMPI2C_CR2_ADD10                FMPI2C_CR2_ADD10_Msk                   /*!< 10-bit addressing mode (master mode)                    */\n#define FMPI2C_CR2_HEAD10R_Pos          (12U)\n#define FMPI2C_CR2_HEAD10R_Msk          (0x1UL << FMPI2C_CR2_HEAD10R_Pos)       /*!< 0x00001000 */\n#define FMPI2C_CR2_HEAD10R              FMPI2C_CR2_HEAD10R_Msk                 /*!< 10-bit address header only read direction (master mode) */\n#define FMPI2C_CR2_START_Pos            (13U)\n#define FMPI2C_CR2_START_Msk            (0x1UL << FMPI2C_CR2_START_Pos)         /*!< 0x00002000 */\n#define FMPI2C_CR2_START                FMPI2C_CR2_START_Msk                   /*!< START generation                                        */\n#define FMPI2C_CR2_STOP_Pos             (14U)\n#define FMPI2C_CR2_STOP_Msk             (0x1UL << FMPI2C_CR2_STOP_Pos)          /*!< 0x00004000 */\n#define FMPI2C_CR2_STOP                 FMPI2C_CR2_STOP_Msk                    /*!< STOP generation (master mode)                           */\n#define FMPI2C_CR2_NACK_Pos             (15U)\n#define FMPI2C_CR2_NACK_Msk             (0x1UL << FMPI2C_CR2_NACK_Pos)          /*!< 0x00008000 */\n#define FMPI2C_CR2_NACK                 FMPI2C_CR2_NACK_Msk                    /*!< NACK generation (slave mode)                            */\n#define FMPI2C_CR2_NBYTES_Pos           (16U)\n#define FMPI2C_CR2_NBYTES_Msk           (0xFFUL << FMPI2C_CR2_NBYTES_Pos)       /*!< 0x00FF0000 */\n#define FMPI2C_CR2_NBYTES               FMPI2C_CR2_NBYTES_Msk                  /*!< Number of bytes                                         */\n#define FMPI2C_CR2_RELOAD_Pos           (24U)\n#define FMPI2C_CR2_RELOAD_Msk           (0x1UL << FMPI2C_CR2_RELOAD_Pos)        /*!< 0x01000000 */\n#define FMPI2C_CR2_RELOAD               FMPI2C_CR2_RELOAD_Msk                  /*!< NBYTES reload mode                                      */\n#define FMPI2C_CR2_AUTOEND_Pos          (25U)\n#define FMPI2C_CR2_AUTOEND_Msk          (0x1UL << FMPI2C_CR2_AUTOEND_Pos)       /*!< 0x02000000 */\n#define FMPI2C_CR2_AUTOEND              FMPI2C_CR2_AUTOEND_Msk                 /*!< Automatic end mode (master mode)                        */\n#define FMPI2C_CR2_PECBYTE_Pos          (26U)\n#define FMPI2C_CR2_PECBYTE_Msk          (0x1UL << FMPI2C_CR2_PECBYTE_Pos)       /*!< 0x04000000 */\n#define FMPI2C_CR2_PECBYTE              FMPI2C_CR2_PECBYTE_Msk                 /*!< Packet error checking byte                              */\n\n/*******************  Bit definition for I2C_OAR1 register  ******************/\n#define FMPI2C_OAR1_OA1_Pos             (0U)\n#define FMPI2C_OAR1_OA1_Msk             (0x3FFUL << FMPI2C_OAR1_OA1_Pos)        /*!< 0x000003FF */\n#define FMPI2C_OAR1_OA1                 FMPI2C_OAR1_OA1_Msk                    /*!< Interface own address 1   */\n#define FMPI2C_OAR1_OA1MODE_Pos         (10U)\n#define FMPI2C_OAR1_OA1MODE_Msk         (0x1UL << FMPI2C_OAR1_OA1MODE_Pos)      /*!< 0x00000400 */\n#define FMPI2C_OAR1_OA1MODE             FMPI2C_OAR1_OA1MODE_Msk                /*!< Own address 1 10-bit mode */\n#define FMPI2C_OAR1_OA1EN_Pos           (15U)\n#define FMPI2C_OAR1_OA1EN_Msk           (0x1UL << FMPI2C_OAR1_OA1EN_Pos)        /*!< 0x00008000 */\n#define FMPI2C_OAR1_OA1EN               FMPI2C_OAR1_OA1EN_Msk                  /*!< Own address 1 enable      */\n\n/*******************  Bit definition for I2C_OAR2 register  ******************/\n#define FMPI2C_OAR2_OA2_Pos             (1U)\n#define FMPI2C_OAR2_OA2_Msk             (0x7FUL << FMPI2C_OAR2_OA2_Pos)         /*!< 0x000000FE */\n#define FMPI2C_OAR2_OA2                 FMPI2C_OAR2_OA2_Msk                    /*!< Interface own address 2 */\n#define FMPI2C_OAR2_OA2MSK_Pos          (8U)\n#define FMPI2C_OAR2_OA2MSK_Msk          (0x7UL << FMPI2C_OAR2_OA2MSK_Pos)       /*!< 0x00000700 */\n#define FMPI2C_OAR2_OA2MSK              FMPI2C_OAR2_OA2MSK_Msk                 /*!< Own address 2 masks     */\n#define FMPI2C_OAR2_OA2EN_Pos           (15U)\n#define FMPI2C_OAR2_OA2EN_Msk           (0x1UL << FMPI2C_OAR2_OA2EN_Pos)        /*!< 0x00008000 */\n#define FMPI2C_OAR2_OA2EN               FMPI2C_OAR2_OA2EN_Msk                  /*!< Own address 2 enable    */\n\n/*******************  Bit definition for I2C_TIMINGR register *******************/\n#define FMPI2C_TIMINGR_SCLL_Pos         (0U)\n#define FMPI2C_TIMINGR_SCLL_Msk         (0xFFUL << FMPI2C_TIMINGR_SCLL_Pos)     /*!< 0x000000FF */\n#define FMPI2C_TIMINGR_SCLL             FMPI2C_TIMINGR_SCLL_Msk                /*!< SCL low period (master mode)  */\n#define FMPI2C_TIMINGR_SCLH_Pos         (8U)\n#define FMPI2C_TIMINGR_SCLH_Msk         (0xFFUL << FMPI2C_TIMINGR_SCLH_Pos)     /*!< 0x0000FF00 */\n#define FMPI2C_TIMINGR_SCLH             FMPI2C_TIMINGR_SCLH_Msk                /*!< SCL high period (master mode) */\n#define FMPI2C_TIMINGR_SDADEL_Pos       (16U)\n#define FMPI2C_TIMINGR_SDADEL_Msk       (0xFUL << FMPI2C_TIMINGR_SDADEL_Pos)    /*!< 0x000F0000 */\n#define FMPI2C_TIMINGR_SDADEL           FMPI2C_TIMINGR_SDADEL_Msk              /*!< Data hold time                */\n#define FMPI2C_TIMINGR_SCLDEL_Pos       (20U)\n#define FMPI2C_TIMINGR_SCLDEL_Msk       (0xFUL << FMPI2C_TIMINGR_SCLDEL_Pos)    /*!< 0x00F00000 */\n#define FMPI2C_TIMINGR_SCLDEL           FMPI2C_TIMINGR_SCLDEL_Msk              /*!< Data setup time               */\n#define FMPI2C_TIMINGR_PRESC_Pos        (28U)\n#define FMPI2C_TIMINGR_PRESC_Msk        (0xFUL << FMPI2C_TIMINGR_PRESC_Pos)     /*!< 0xF0000000 */\n#define FMPI2C_TIMINGR_PRESC            FMPI2C_TIMINGR_PRESC_Msk               /*!< Timings prescaler             */\n\n/******************* Bit definition for I2C_TIMEOUTR register *******************/\n#define FMPI2C_TIMEOUTR_TIMEOUTA_Pos    (0U)\n#define FMPI2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */\n#define FMPI2C_TIMEOUTR_TIMEOUTA        FMPI2C_TIMEOUTR_TIMEOUTA_Msk           /*!< Bus timeout A                 */\n#define FMPI2C_TIMEOUTR_TIDLE_Pos       (12U)\n#define FMPI2C_TIMEOUTR_TIDLE_Msk       (0x1UL << FMPI2C_TIMEOUTR_TIDLE_Pos)    /*!< 0x00001000 */\n#define FMPI2C_TIMEOUTR_TIDLE           FMPI2C_TIMEOUTR_TIDLE_Msk              /*!< Idle clock timeout detection  */\n#define FMPI2C_TIMEOUTR_TIMOUTEN_Pos    (15U)\n#define FMPI2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */\n#define FMPI2C_TIMEOUTR_TIMOUTEN        FMPI2C_TIMEOUTR_TIMOUTEN_Msk           /*!< Clock timeout enable          */\n#define FMPI2C_TIMEOUTR_TIMEOUTB_Pos    (16U)\n#define FMPI2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */\n#define FMPI2C_TIMEOUTR_TIMEOUTB        FMPI2C_TIMEOUTR_TIMEOUTB_Msk           /*!< Bus timeout B                 */\n#define FMPI2C_TIMEOUTR_TEXTEN_Pos      (31U)\n#define FMPI2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << FMPI2C_TIMEOUTR_TEXTEN_Pos)   /*!< 0x80000000 */\n#define FMPI2C_TIMEOUTR_TEXTEN          FMPI2C_TIMEOUTR_TEXTEN_Msk             /*!< Extended clock timeout enable */\n\n/******************  Bit definition for I2C_ISR register  *********************/\n#define FMPI2C_ISR_TXE_Pos              (0U)\n#define FMPI2C_ISR_TXE_Msk              (0x1UL << FMPI2C_ISR_TXE_Pos)           /*!< 0x00000001 */\n#define FMPI2C_ISR_TXE                  FMPI2C_ISR_TXE_Msk                     /*!< Transmit data register empty     */\n#define FMPI2C_ISR_TXIS_Pos             (1U)\n#define FMPI2C_ISR_TXIS_Msk             (0x1UL << FMPI2C_ISR_TXIS_Pos)          /*!< 0x00000002 */\n#define FMPI2C_ISR_TXIS                 FMPI2C_ISR_TXIS_Msk                    /*!< Transmit interrupt status        */\n#define FMPI2C_ISR_RXNE_Pos             (2U)\n#define FMPI2C_ISR_RXNE_Msk             (0x1UL << FMPI2C_ISR_RXNE_Pos)          /*!< 0x00000004 */\n#define FMPI2C_ISR_RXNE                 FMPI2C_ISR_RXNE_Msk                    /*!< Receive data register not empty  */\n#define FMPI2C_ISR_ADDR_Pos             (3U)\n#define FMPI2C_ISR_ADDR_Msk             (0x1UL << FMPI2C_ISR_ADDR_Pos)          /*!< 0x00000008 */\n#define FMPI2C_ISR_ADDR                 FMPI2C_ISR_ADDR_Msk                    /*!< Address matched (slave mode)     */\n#define FMPI2C_ISR_NACKF_Pos            (4U)\n#define FMPI2C_ISR_NACKF_Msk            (0x1UL << FMPI2C_ISR_NACKF_Pos)         /*!< 0x00000010 */\n#define FMPI2C_ISR_NACKF                FMPI2C_ISR_NACKF_Msk                   /*!< NACK received flag               */\n#define FMPI2C_ISR_STOPF_Pos            (5U)\n#define FMPI2C_ISR_STOPF_Msk            (0x1UL << FMPI2C_ISR_STOPF_Pos)         /*!< 0x00000020 */\n#define FMPI2C_ISR_STOPF                FMPI2C_ISR_STOPF_Msk                   /*!< STOP detection flag              */\n#define FMPI2C_ISR_TC_Pos               (6U)\n#define FMPI2C_ISR_TC_Msk               (0x1UL << FMPI2C_ISR_TC_Pos)            /*!< 0x00000040 */\n#define FMPI2C_ISR_TC                   FMPI2C_ISR_TC_Msk                      /*!< Transfer complete (master mode)  */\n#define FMPI2C_ISR_TCR_Pos              (7U)\n#define FMPI2C_ISR_TCR_Msk              (0x1UL << FMPI2C_ISR_TCR_Pos)           /*!< 0x00000080 */\n#define FMPI2C_ISR_TCR                  FMPI2C_ISR_TCR_Msk                     /*!< Transfer complete reload         */\n#define FMPI2C_ISR_BERR_Pos             (8U)\n#define FMPI2C_ISR_BERR_Msk             (0x1UL << FMPI2C_ISR_BERR_Pos)          /*!< 0x00000100 */\n#define FMPI2C_ISR_BERR                 FMPI2C_ISR_BERR_Msk                    /*!< Bus error                        */\n#define FMPI2C_ISR_ARLO_Pos             (9U)\n#define FMPI2C_ISR_ARLO_Msk             (0x1UL << FMPI2C_ISR_ARLO_Pos)          /*!< 0x00000200 */\n#define FMPI2C_ISR_ARLO                 FMPI2C_ISR_ARLO_Msk                    /*!< Arbitration lost                 */\n#define FMPI2C_ISR_OVR_Pos              (10U)\n#define FMPI2C_ISR_OVR_Msk              (0x1UL << FMPI2C_ISR_OVR_Pos)           /*!< 0x00000400 */\n#define FMPI2C_ISR_OVR                  FMPI2C_ISR_OVR_Msk                     /*!< Overrun/Underrun                 */\n#define FMPI2C_ISR_PECERR_Pos           (11U)\n#define FMPI2C_ISR_PECERR_Msk           (0x1UL << FMPI2C_ISR_PECERR_Pos)        /*!< 0x00000800 */\n#define FMPI2C_ISR_PECERR               FMPI2C_ISR_PECERR_Msk                  /*!< PEC error in reception           */\n#define FMPI2C_ISR_TIMEOUT_Pos          (12U)\n#define FMPI2C_ISR_TIMEOUT_Msk          (0x1UL << FMPI2C_ISR_TIMEOUT_Pos)       /*!< 0x00001000 */\n#define FMPI2C_ISR_TIMEOUT              FMPI2C_ISR_TIMEOUT_Msk                 /*!< Timeout or Tlow detection flag   */\n#define FMPI2C_ISR_ALERT_Pos            (13U)\n#define FMPI2C_ISR_ALERT_Msk            (0x1UL << FMPI2C_ISR_ALERT_Pos)         /*!< 0x00002000 */\n#define FMPI2C_ISR_ALERT                FMPI2C_ISR_ALERT_Msk                   /*!< SMBus alert                      */\n#define FMPI2C_ISR_BUSY_Pos             (15U)\n#define FMPI2C_ISR_BUSY_Msk             (0x1UL << FMPI2C_ISR_BUSY_Pos)          /*!< 0x00008000 */\n#define FMPI2C_ISR_BUSY                 FMPI2C_ISR_BUSY_Msk                    /*!< Bus busy                         */\n#define FMPI2C_ISR_DIR_Pos              (16U)\n#define FMPI2C_ISR_DIR_Msk              (0x1UL << FMPI2C_ISR_DIR_Pos)           /*!< 0x00010000 */\n#define FMPI2C_ISR_DIR                  FMPI2C_ISR_DIR_Msk                     /*!< Transfer direction (slave mode)  */\n#define FMPI2C_ISR_ADDCODE_Pos          (17U)\n#define FMPI2C_ISR_ADDCODE_Msk          (0x7FUL << FMPI2C_ISR_ADDCODE_Pos)      /*!< 0x00FE0000 */\n#define FMPI2C_ISR_ADDCODE              FMPI2C_ISR_ADDCODE_Msk                 /*!< Address match code (slave mode)  */\n\n/******************  Bit definition for I2C_ICR register  *********************/\n#define FMPI2C_ICR_ADDRCF_Pos           (3U)\n#define FMPI2C_ICR_ADDRCF_Msk           (0x1UL << FMPI2C_ICR_ADDRCF_Pos)        /*!< 0x00000008 */\n#define FMPI2C_ICR_ADDRCF               FMPI2C_ICR_ADDRCF_Msk                  /*!< Address matched clear flag  */\n#define FMPI2C_ICR_NACKCF_Pos           (4U)\n#define FMPI2C_ICR_NACKCF_Msk           (0x1UL << FMPI2C_ICR_NACKCF_Pos)        /*!< 0x00000010 */\n#define FMPI2C_ICR_NACKCF               FMPI2C_ICR_NACKCF_Msk                  /*!< NACK clear flag             */\n#define FMPI2C_ICR_STOPCF_Pos           (5U)\n#define FMPI2C_ICR_STOPCF_Msk           (0x1UL << FMPI2C_ICR_STOPCF_Pos)        /*!< 0x00000020 */\n#define FMPI2C_ICR_STOPCF               FMPI2C_ICR_STOPCF_Msk                  /*!< STOP detection clear flag   */\n#define FMPI2C_ICR_BERRCF_Pos           (8U)\n#define FMPI2C_ICR_BERRCF_Msk           (0x1UL << FMPI2C_ICR_BERRCF_Pos)        /*!< 0x00000100 */\n#define FMPI2C_ICR_BERRCF               FMPI2C_ICR_BERRCF_Msk                  /*!< Bus error clear flag        */\n#define FMPI2C_ICR_ARLOCF_Pos           (9U)\n#define FMPI2C_ICR_ARLOCF_Msk           (0x1UL << FMPI2C_ICR_ARLOCF_Pos)        /*!< 0x00000200 */\n#define FMPI2C_ICR_ARLOCF               FMPI2C_ICR_ARLOCF_Msk                  /*!< Arbitration lost clear flag */\n#define FMPI2C_ICR_OVRCF_Pos            (10U)\n#define FMPI2C_ICR_OVRCF_Msk            (0x1UL << FMPI2C_ICR_OVRCF_Pos)         /*!< 0x00000400 */\n#define FMPI2C_ICR_OVRCF                FMPI2C_ICR_OVRCF_Msk                   /*!< Overrun/Underrun clear flag */\n#define FMPI2C_ICR_PECCF_Pos            (11U)\n#define FMPI2C_ICR_PECCF_Msk            (0x1UL << FMPI2C_ICR_PECCF_Pos)         /*!< 0x00000800 */\n#define FMPI2C_ICR_PECCF                FMPI2C_ICR_PECCF_Msk                   /*!< PAC error clear flag        */\n#define FMPI2C_ICR_TIMOUTCF_Pos         (12U)\n#define FMPI2C_ICR_TIMOUTCF_Msk         (0x1UL << FMPI2C_ICR_TIMOUTCF_Pos)      /*!< 0x00001000 */\n#define FMPI2C_ICR_TIMOUTCF             FMPI2C_ICR_TIMOUTCF_Msk                /*!< Timeout clear flag          */\n#define FMPI2C_ICR_ALERTCF_Pos          (13U)\n#define FMPI2C_ICR_ALERTCF_Msk          (0x1UL << FMPI2C_ICR_ALERTCF_Pos)       /*!< 0x00002000 */\n#define FMPI2C_ICR_ALERTCF              FMPI2C_ICR_ALERTCF_Msk                 /*!< Alert clear flag            */\n\n/******************  Bit definition for I2C_PECR register  *********************/\n#define FMPI2C_PECR_PEC_Pos             (0U)\n#define FMPI2C_PECR_PEC_Msk             (0xFFUL << FMPI2C_PECR_PEC_Pos)         /*!< 0x000000FF */\n#define FMPI2C_PECR_PEC                 FMPI2C_PECR_PEC_Msk                    /*!< PEC register */\n\n/******************  Bit definition for I2C_RXDR register  *********************/\n#define FMPI2C_RXDR_RXDATA_Pos          (0U)\n#define FMPI2C_RXDR_RXDATA_Msk          (0xFFUL << FMPI2C_RXDR_RXDATA_Pos)      /*!< 0x000000FF */\n#define FMPI2C_RXDR_RXDATA              FMPI2C_RXDR_RXDATA_Msk                 /*!< 8-bit receive data */\n\n/******************  Bit definition for I2C_TXDR register  *********************/\n#define FMPI2C_TXDR_TXDATA_Pos          (0U)\n#define FMPI2C_TXDR_TXDATA_Msk          (0xFFUL << FMPI2C_TXDR_TXDATA_Pos)      /*!< 0x000000FF */\n#define FMPI2C_TXDR_TXDATA              FMPI2C_TXDR_TXDATA_Msk                 /*!< 8-bit transmit data */\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Independent WATCHDOG                             */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define IWDG_KR_KEY_Pos     (0U)\n#define IWDG_KR_KEY_Msk     (0xFFFFUL << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */\n#define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */\n\n/*******************  Bit definition for IWDG_PR register  ********************/\n#define IWDG_PR_PR_Pos      (0U)\n#define IWDG_PR_PR_Msk      (0x7UL << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */\n#define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */\n#define IWDG_PR_PR_0        (0x1UL << IWDG_PR_PR_Pos)                           /*!< 0x01 */\n#define IWDG_PR_PR_1        (0x2UL << IWDG_PR_PR_Pos)                           /*!< 0x02 */\n#define IWDG_PR_PR_2        (0x4UL << IWDG_PR_PR_Pos)                           /*!< 0x04 */\n\n/*******************  Bit definition for IWDG_RLR register  *******************/\n#define IWDG_RLR_RL_Pos     (0U)\n#define IWDG_RLR_RL_Msk     (0xFFFUL << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */\n#define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */\n\n/*******************  Bit definition for IWDG_SR register  ********************/\n#define IWDG_SR_PVU_Pos     (0U)\n#define IWDG_SR_PVU_Msk     (0x1UL << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */\n#define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */\n#define IWDG_SR_RVU_Pos     (1U)\n#define IWDG_SR_RVU_Msk     (0x1UL << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */\n#define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                             Power Control                                  */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for PWR_CR register  ********************/\n#define PWR_CR_LPDS_Pos        (0U)\n#define PWR_CR_LPDS_Msk        (0x1UL << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */\n#define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */\n#define PWR_CR_PDDS_Pos        (1U)\n#define PWR_CR_PDDS_Msk        (0x1UL << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */\n#define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */\n#define PWR_CR_CWUF_Pos        (2U)\n#define PWR_CR_CWUF_Msk        (0x1UL << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */\n#define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */\n#define PWR_CR_CSBF_Pos        (3U)\n#define PWR_CR_CSBF_Msk        (0x1UL << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */\n#define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */\n#define PWR_CR_PVDE_Pos        (4U)\n#define PWR_CR_PVDE_Msk        (0x1UL << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */\n#define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */\n\n#define PWR_CR_PLS_Pos         (5U)\n#define PWR_CR_PLS_Msk         (0x7UL << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */\n#define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */\n#define PWR_CR_PLS_0           (0x1UL << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */\n#define PWR_CR_PLS_1           (0x2UL << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */\n#define PWR_CR_PLS_2           (0x4UL << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */\n\n/*!< PVD level configuration */\n#define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */\n#define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */\n#define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */\n#define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */\n#define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */\n#define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */\n#define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */\n#define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */\n#define PWR_CR_DBP_Pos         (8U)\n#define PWR_CR_DBP_Msk         (0x1UL << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */\n#define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */\n#define PWR_CR_FPDS_Pos        (9U)\n#define PWR_CR_FPDS_Msk        (0x1UL << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */\n#define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */\n#define PWR_CR_LPLVDS_Pos      (10U)\n#define PWR_CR_LPLVDS_Msk      (0x1UL << PWR_CR_LPLVDS_Pos)                     /*!< 0x00000400 */\n#define PWR_CR_LPLVDS          PWR_CR_LPLVDS_Msk                               /*!< Low Power Regulator Low Voltage in Deep Sleep mode         */\n#define PWR_CR_MRLVDS_Pos      (11U)\n#define PWR_CR_MRLVDS_Msk      (0x1UL << PWR_CR_MRLVDS_Pos)                     /*!< 0x00000800 */\n#define PWR_CR_MRLVDS          PWR_CR_MRLVDS_Msk                               /*!< Main Regulator Low Voltage in Deep Sleep mode              */\n#define PWR_CR_ADCDC1_Pos      (13U)\n#define PWR_CR_ADCDC1_Msk      (0x1UL << PWR_CR_ADCDC1_Pos)                     /*!< 0x00002000 */\n#define PWR_CR_ADCDC1          PWR_CR_ADCDC1_Msk                               /*!< Refer to AN4073 on how to use this bit                     */\n#define PWR_CR_VOS_Pos         (14U)\n#define PWR_CR_VOS_Msk         (0x3UL << PWR_CR_VOS_Pos)                        /*!< 0x0000C000 */\n#define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\n#define PWR_CR_VOS_0           0x00004000U                                     /*!< Bit 0 */\n#define PWR_CR_VOS_1           0x00008000U                                     /*!< Bit 1 */\n#define PWR_CR_FMSSR_Pos       (20U)\n#define PWR_CR_FMSSR_Msk       (0x1UL << PWR_CR_FMSSR_Pos)                      /*!< 0x00100000 */\n#define PWR_CR_FMSSR           PWR_CR_FMSSR_Msk                                /*!< Flash Memory Sleep System Run        */\n#define PWR_CR_FISSR_Pos       (21U)\n#define PWR_CR_FISSR_Msk       (0x1UL << PWR_CR_FISSR_Pos)                      /*!< 0x00200000 */\n#define PWR_CR_FISSR           PWR_CR_FISSR_Msk                                /*!< Flash Interface Stop while System Run */\n\n\n/*******************  Bit definition for PWR_CSR register  ********************/\n#define PWR_CSR_WUF_Pos        (0U)\n#define PWR_CSR_WUF_Msk        (0x1UL << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */\n#define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */\n#define PWR_CSR_SBF_Pos        (1U)\n#define PWR_CSR_SBF_Msk        (0x1UL << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */\n#define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */\n#define PWR_CSR_PVDO_Pos       (2U)\n#define PWR_CSR_PVDO_Msk       (0x1UL << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */\n#define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */\n#define PWR_CSR_BRR_Pos        (3U)\n#define PWR_CSR_BRR_Msk        (0x1UL << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */\n#define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */\n#define PWR_CSR_EWUP3_Pos      (6U)\n#define PWR_CSR_EWUP3_Msk      (0x1UL << PWR_CSR_EWUP1_Pos)                     /*!< 0x00000040 */\n#define PWR_CSR_EWUP3          PWR_CSR_EWUP3_Msk                               /*!< Enable WKUP pin 3                                */\n#define PWR_CSR_EWUP2_Pos      (7U)\n#define PWR_CSR_EWUP2_Msk      (0x1UL << PWR_CSR_EWUP2_Pos)                     /*!< 0x00000080 */\n#define PWR_CSR_EWUP2          PWR_CSR_EWUP2_Msk                               /*!< Enable WKUP pin 2                                */\n#define PWR_CSR_EWUP1_Pos      (8U)\n#define PWR_CSR_EWUP1_Msk      (0x1UL << PWR_CSR_EWUP1_Pos)                     /*!< 0x00000100 */\n#define PWR_CSR_EWUP1          PWR_CSR_EWUP1_Msk                               /*!< Enable WKUP pin 1                                */\n#define PWR_CSR_BRE_Pos        (9U)\n#define PWR_CSR_BRE_Msk        (0x1UL << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */\n#define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */\n#define PWR_CSR_VOSRDY_Pos     (14U)\n#define PWR_CSR_VOSRDY_Msk     (0x1UL << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */\n#define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    QUADSPI                                 */\n/*                                                                            */\n/******************************************************************************/\n/*****************  Bit definition for QUADSPI_CR register  *******************/\n#define QUADSPI_CR_EN_Pos                (0U)\n#define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)           /*!< 0x00000001 */\n#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable                             */\n#define QUADSPI_CR_ABORT_Pos             (1U)\n#define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)        /*!< 0x00000002 */\n#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request                      */\n#define QUADSPI_CR_DMAEN_Pos             (2U)\n#define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)        /*!< 0x00000004 */\n#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable                         */\n#define QUADSPI_CR_TCEN_Pos              (3U)\n#define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)         /*!< 0x00000008 */\n#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable             */\n#define QUADSPI_CR_SSHIFT_Pos            (4U)\n#define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)       /*!< 0x00000010 */\n#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift                */\n#define QUADSPI_CR_DFM_Pos               (6U)\n#define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)          /*!< 0x00000040 */\n#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode                    */\n#define QUADSPI_CR_FSEL_Pos              (7U)\n#define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)         /*!< 0x00000080 */\n#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select                       */\n#define QUADSPI_CR_FTHRES_Pos            (8U)\n#define QUADSPI_CR_FTHRES_Msk            (0x1FUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */\n#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level             */\n#define QUADSPI_CR_FTHRES_0              (0x01UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */\n#define QUADSPI_CR_FTHRES_1              (0x02UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */\n#define QUADSPI_CR_FTHRES_2              (0x04UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */\n#define QUADSPI_CR_FTHRES_3              (0x08UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */\n#define QUADSPI_CR_FTHRES_4              (0x10UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001000 */\n#define QUADSPI_CR_TEIE_Pos              (16U)\n#define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)         /*!< 0x00010000 */\n#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable    */\n#define QUADSPI_CR_TCIE_Pos              (17U)\n#define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)         /*!< 0x00020000 */\n#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */\n#define QUADSPI_CR_FTIE_Pos              (18U)\n#define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)         /*!< 0x00040000 */\n#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable    */\n#define QUADSPI_CR_SMIE_Pos              (19U)\n#define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)         /*!< 0x00080000 */\n#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable      */\n#define QUADSPI_CR_TOIE_Pos              (20U)\n#define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)         /*!< 0x00100000 */\n#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable           */\n#define QUADSPI_CR_APMS_Pos              (22U)\n#define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)         /*!< 0x00400000 */\n#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1                              */\n#define QUADSPI_CR_PMM_Pos               (23U)\n#define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)          /*!< 0x00800000 */\n#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode                 */\n#define QUADSPI_CR_PRESCALER_Pos         (24U)\n#define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0xFF000000 */\n#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler     */\n#define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x01000000 */\n#define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x02000000 */\n#define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x04000000 */\n#define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x08000000 */\n#define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x10000000 */\n#define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x20000000 */\n#define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x40000000 */\n#define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x80000000 */\n\n/*****************  Bit definition for QUADSPI_DCR register  ******************/\n#define QUADSPI_DCR_CKMODE_Pos           (0U)\n#define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)      /*!< 0x00000001 */\n#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3                 */\n#define QUADSPI_DCR_CSHT_Pos             (8U)\n#define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000700 */\n#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */\n#define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000100 */\n#define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000200 */\n#define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000400 */\n#define QUADSPI_DCR_FSIZE_Pos            (16U)\n#define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x001F0000 */\n#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size          */\n#define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00010000 */\n#define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00020000 */\n#define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00040000 */\n#define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00080000 */\n#define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00100000 */\n\n/******************  Bit definition for QUADSPI_SR register  *******************/\n#define QUADSPI_SR_TEF_Pos               (0U)\n#define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)          /*!< 0x00000001 */\n#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag    */\n#define QUADSPI_SR_TCF_Pos               (1U)\n#define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)          /*!< 0x00000002 */\n#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */\n#define QUADSPI_SR_FTF_Pos               (2U)\n#define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)          /*!< 0x00000004 */\n#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag    */\n#define QUADSPI_SR_SMF_Pos               (3U)\n#define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)          /*!< 0x00000008 */\n#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag      */\n#define QUADSPI_SR_TOF_Pos               (4U)\n#define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)          /*!< 0x00000010 */\n#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag           */\n#define QUADSPI_SR_BUSY_Pos              (5U)\n#define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)         /*!< 0x00000020 */\n#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy                   */\n#define QUADSPI_SR_FLEVEL_Pos            (8U)\n#define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00003F00 */\n#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag    */\n#define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000100 */\n#define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000200 */\n#define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000400 */\n#define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000800 */\n#define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00001000 */\n#define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00002000 */\n\n/******************  Bit definition for QUADSPI_FCR register  ******************/\n#define QUADSPI_FCR_CTEF_Pos             (0U)\n#define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)        /*!< 0x00000001 */\n#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag    */\n#define QUADSPI_FCR_CTCF_Pos             (1U)\n#define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)        /*!< 0x00000002 */\n#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */\n#define QUADSPI_FCR_CSMF_Pos             (3U)\n#define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)        /*!< 0x00000008 */\n#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag      */\n#define QUADSPI_FCR_CTOF_Pos             (4U)\n#define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)        /*!< 0x00000010 */\n#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag           */\n\n/******************  Bit definition for QUADSPI_DLR register  ******************/\n#define QUADSPI_DLR_DL_Pos               (0U)\n#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)   /*!< 0xFFFFFFFF */\n#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */\n\n/******************  Bit definition for QUADSPI_CCR register  ******************/\n#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)\n#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */\n#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk           /*!< INSTRUCTION[7:0]: Instruction         */\n#define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */\n#define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */\n#define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */\n#define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */\n#define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */\n#define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */\n#define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */\n#define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */\n#define QUADSPI_CCR_IMODE_Pos            (8U)\n#define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000300 */\n#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                 /*!< IMODE[1:0]: Instruction Mode          */\n#define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000100 */\n#define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000200 */\n#define QUADSPI_CCR_ADMODE_Pos           (10U)\n#define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000C00 */\n#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                /*!< ADMODE[1:0]: Address Mode             */\n#define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000400 */\n#define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000800 */\n#define QUADSPI_CCR_ADSIZE_Pos           (12U)\n#define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00003000 */\n#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                /*!< ADSIZE[1:0]: Address Size             */\n#define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00001000 */\n#define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00002000 */\n#define QUADSPI_CCR_ABMODE_Pos           (14U)\n#define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x0000C000 */\n#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                /*!< ABMODE[1:0]: Alternate Bytes Mode     */\n#define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00004000 */\n#define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00008000 */\n#define QUADSPI_CCR_ABSIZE_Pos           (16U)\n#define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00030000 */\n#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                /*!< ABSIZE[1:0]: Instruction Mode         */\n#define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00010000 */\n#define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00020000 */\n#define QUADSPI_CCR_DCYC_Pos             (18U)\n#define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x007C0000 */\n#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                  /*!< DCYC[4:0]: Dummy Cycles               */\n#define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00040000 */\n#define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00080000 */\n#define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00100000 */\n#define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00200000 */\n#define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00400000 */\n#define QUADSPI_CCR_DMODE_Pos            (24U)\n#define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x03000000 */\n#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                 /*!< DMODE[1:0]: Data Mode                 */\n#define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x01000000 */\n#define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x02000000 */\n#define QUADSPI_CCR_FMODE_Pos            (26U)\n#define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x0C000000 */\n#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                 /*!< FMODE[1:0]: Functional Mode           */\n#define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x04000000 */\n#define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x08000000 */\n#define QUADSPI_CCR_SIOO_Pos             (28U)\n#define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)        /*!< 0x10000000 */\n#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                  /*!< SIOO: Send Instruction Only Once Mode */\n#define QUADSPI_CCR_DHHC_Pos             (30U)\n#define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)        /*!< 0x40000000 */\n#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                  /*!< DHHC: Delay Half Hclk Cycle           */\n#define QUADSPI_CCR_DDRM_Pos             (31U)\n#define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)        /*!< 0x80000000 */\n#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                  /*!< DDRM: Double Data Rate Mode           */\n/******************  Bit definition for QUADSPI_AR register  *******************/\n#define QUADSPI_AR_ADDRESS_Pos           (0U)\n#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address                */\n\n/******************  Bit definition for QUADSPI_ABR register  ******************/\n#define QUADSPI_ABR_ALTERNATE_Pos        (0U)\n#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes      */\n\n/******************  Bit definition for QUADSPI_DR register  *******************/\n#define QUADSPI_DR_DATA_Pos              (0U)\n#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)  /*!< 0xFFFFFFFF */\n#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data                      */\n\n/******************  Bit definition for QUADSPI_PSMKR register  ****************/\n#define QUADSPI_PSMKR_MASK_Pos           (0U)\n#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask               */\n\n/******************  Bit definition for QUADSPI_PSMAR register  ****************/\n#define QUADSPI_PSMAR_MATCH_Pos          (0U)\n#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match             */\n\n/******************  Bit definition for QUADSPI_PIR register  *****************/\n#define QUADSPI_PIR_INTERVAL_Pos         (0U)\n#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */\n#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval      */\n\n/******************  Bit definition for QUADSPI_LPTR register  *****************/\n#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)\n#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */\n#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period         */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Reset and Clock Control                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for RCC_CR register  ********************/\n#define RCC_CR_HSION_Pos                   (0U)\n#define RCC_CR_HSION_Msk                   (0x1UL << RCC_CR_HSION_Pos)          /*!< 0x00000001 */\n#define RCC_CR_HSION                       RCC_CR_HSION_Msk\n#define RCC_CR_HSIRDY_Pos                  (1U)\n#define RCC_CR_HSIRDY_Msk                  (0x1UL << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */\n#define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk\n\n#define RCC_CR_HSITRIM_Pos                 (3U)\n#define RCC_CR_HSITRIM_Msk                 (0x1FUL << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */\n#define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk\n#define RCC_CR_HSITRIM_0                   (0x01UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */\n#define RCC_CR_HSITRIM_1                   (0x02UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */\n#define RCC_CR_HSITRIM_2                   (0x04UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */\n#define RCC_CR_HSITRIM_3                   (0x08UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */\n#define RCC_CR_HSITRIM_4                   (0x10UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */\n\n#define RCC_CR_HSICAL_Pos                  (8U)\n#define RCC_CR_HSICAL_Msk                  (0xFFUL << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */\n#define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk\n#define RCC_CR_HSICAL_0                    (0x01UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */\n#define RCC_CR_HSICAL_1                    (0x02UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */\n#define RCC_CR_HSICAL_2                    (0x04UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */\n#define RCC_CR_HSICAL_3                    (0x08UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */\n#define RCC_CR_HSICAL_4                    (0x10UL << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */\n#define RCC_CR_HSICAL_5                    (0x20UL << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */\n#define RCC_CR_HSICAL_6                    (0x40UL << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */\n#define RCC_CR_HSICAL_7                    (0x80UL << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */\n\n#define RCC_CR_HSEON_Pos                   (16U)\n#define RCC_CR_HSEON_Msk                   (0x1UL << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */\n#define RCC_CR_HSEON                       RCC_CR_HSEON_Msk\n#define RCC_CR_HSERDY_Pos                  (17U)\n#define RCC_CR_HSERDY_Msk                  (0x1UL << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */\n#define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk\n#define RCC_CR_HSEBYP_Pos                  (18U)\n#define RCC_CR_HSEBYP_Msk                  (0x1UL << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */\n#define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk\n#define RCC_CR_CSSON_Pos                   (19U)\n#define RCC_CR_CSSON_Msk                   (0x1UL << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */\n#define RCC_CR_CSSON                       RCC_CR_CSSON_Msk\n#define RCC_CR_PLLON_Pos                   (24U)\n#define RCC_CR_PLLON_Msk                   (0x1UL << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */\n#define RCC_CR_PLLON                       RCC_CR_PLLON_Msk\n#define RCC_CR_PLLRDY_Pos                  (25U)\n#define RCC_CR_PLLRDY_Msk                  (0x1UL << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */\n#define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_PLLI2S_SUPPORT                                                     /*!< Support PLLI2S oscillator */\n\n#define RCC_CR_PLLI2SON_Pos                (26U)\n#define RCC_CR_PLLI2SON_Msk                (0x1UL << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */\n#define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk\n#define RCC_CR_PLLI2SRDY_Pos               (27U)\n#define RCC_CR_PLLI2SRDY_Msk               (0x1UL << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */\n#define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk\n\n/********************  Bit definition for RCC_PLLCFGR register  ***************/\n#define RCC_PLLCFGR_PLLM_Pos               (0U)\n#define RCC_PLLCFGR_PLLM_Msk               (0x3FUL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */\n#define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk\n#define RCC_PLLCFGR_PLLM_0                 (0x01UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */\n#define RCC_PLLCFGR_PLLM_1                 (0x02UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */\n#define RCC_PLLCFGR_PLLM_2                 (0x04UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */\n#define RCC_PLLCFGR_PLLM_3                 (0x08UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */\n#define RCC_PLLCFGR_PLLM_4                 (0x10UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */\n#define RCC_PLLCFGR_PLLM_5                 (0x20UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */\n\n#define RCC_PLLCFGR_PLLN_Pos               (6U)\n#define RCC_PLLCFGR_PLLN_Msk               (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */\n#define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk\n#define RCC_PLLCFGR_PLLN_0                 (0x001UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */\n#define RCC_PLLCFGR_PLLN_1                 (0x002UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */\n#define RCC_PLLCFGR_PLLN_2                 (0x004UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */\n#define RCC_PLLCFGR_PLLN_3                 (0x008UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */\n#define RCC_PLLCFGR_PLLN_4                 (0x010UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */\n#define RCC_PLLCFGR_PLLN_5                 (0x020UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */\n#define RCC_PLLCFGR_PLLN_6                 (0x040UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */\n#define RCC_PLLCFGR_PLLN_7                 (0x080UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */\n#define RCC_PLLCFGR_PLLN_8                 (0x100UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */\n\n#define RCC_PLLCFGR_PLLP_Pos               (16U)\n#define RCC_PLLCFGR_PLLP_Msk               (0x3UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */\n#define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk\n#define RCC_PLLCFGR_PLLP_0                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */\n#define RCC_PLLCFGR_PLLP_1                 (0x2UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */\n\n#define RCC_PLLCFGR_PLLSRC_Pos             (22U)\n#define RCC_PLLCFGR_PLLSRC_Msk             (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk\n#define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)\n#define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk\n#define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U\n\n#define RCC_PLLCFGR_PLLQ_Pos               (24U)\n#define RCC_PLLCFGR_PLLQ_Msk               (0xFUL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */\n#define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk\n#define RCC_PLLCFGR_PLLQ_0                 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */\n#define RCC_PLLCFGR_PLLQ_1                 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */\n#define RCC_PLLCFGR_PLLQ_2                 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */\n#define RCC_PLLCFGR_PLLQ_3                 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_PLLR_I2S_CLKSOURCE_SUPPORT     /*!< Support PLLR clock as I2S clock source */\n\n#define RCC_PLLCFGR_PLLR_Pos               (28U)\n#define RCC_PLLCFGR_PLLR_Msk               (0x7UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x70000000 */\n#define RCC_PLLCFGR_PLLR                   RCC_PLLCFGR_PLLR_Msk\n#define RCC_PLLCFGR_PLLR_0                 (0x1UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x10000000 */\n#define RCC_PLLCFGR_PLLR_1                 (0x2UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x20000000 */\n#define RCC_PLLCFGR_PLLR_2                 (0x4UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x40000000 */\n\n/********************  Bit definition for RCC_CFGR register  ******************/\n/*!< SW configuration */\n#define RCC_CFGR_SW_Pos                    (0U)\n#define RCC_CFGR_SW_Msk                    (0x3UL << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */\n#define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */\n#define RCC_CFGR_SW_0                      (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */\n#define RCC_CFGR_SW_1                      (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */\n\n#define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */\n#define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */\n#define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */\n\n/*!< SWS configuration */\n#define RCC_CFGR_SWS_Pos                   (2U)\n#define RCC_CFGR_SWS_Msk                   (0x3UL << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */\n#define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */\n#define RCC_CFGR_SWS_0                     (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */\n#define RCC_CFGR_SWS_1                     (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */\n\n#define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */\n#define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */\n#define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */\n\n/*!< HPRE configuration */\n#define RCC_CFGR_HPRE_Pos                  (4U)\n#define RCC_CFGR_HPRE_Msk                  (0xFUL << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */\n#define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */\n#define RCC_CFGR_HPRE_0                    (0x1UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */\n#define RCC_CFGR_HPRE_1                    (0x2UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */\n#define RCC_CFGR_HPRE_2                    (0x4UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */\n#define RCC_CFGR_HPRE_3                    (0x8UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */\n\n#define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */\n#define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */\n#define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */\n#define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */\n#define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */\n#define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */\n#define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */\n#define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */\n#define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */\n\n/*!< PPRE1 configuration */\n#define RCC_CFGR_PPRE1_Pos                 (10U)\n#define RCC_CFGR_PPRE1_Msk                 (0x7UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */\n#define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */\n#define RCC_CFGR_PPRE1_0                   (0x1UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */\n#define RCC_CFGR_PPRE1_1                   (0x2UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */\n#define RCC_CFGR_PPRE1_2                   (0x4UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */\n\n#define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */\n\n/*!< PPRE2 configuration */\n#define RCC_CFGR_PPRE2_Pos                 (13U)\n#define RCC_CFGR_PPRE2_Msk                 (0x7UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */\n#define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */\n#define RCC_CFGR_PPRE2_0                   (0x1UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */\n#define RCC_CFGR_PPRE2_1                   (0x2UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */\n#define RCC_CFGR_PPRE2_2                   (0x4UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */\n\n#define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */\n\n/*!< RTCPRE configuration */\n#define RCC_CFGR_RTCPRE_Pos                (16U)\n#define RCC_CFGR_RTCPRE_Msk                (0x1FUL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */\n#define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk\n#define RCC_CFGR_RTCPRE_0                  (0x01UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */\n#define RCC_CFGR_RTCPRE_1                  (0x02UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */\n#define RCC_CFGR_RTCPRE_2                  (0x04UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */\n#define RCC_CFGR_RTCPRE_3                  (0x08UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */\n#define RCC_CFGR_RTCPRE_4                  (0x10UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */\n\n/*!< MCO1 configuration */\n#define RCC_CFGR_MCO1_Pos                  (21U)\n#define RCC_CFGR_MCO1_Msk                  (0x3UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */\n#define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk\n#define RCC_CFGR_MCO1_0                    (0x1UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */\n#define RCC_CFGR_MCO1_1                    (0x2UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */\n\n\n#define RCC_CFGR_MCO1PRE_Pos               (24U)\n#define RCC_CFGR_MCO1PRE_Msk               (0x7UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */\n#define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk\n#define RCC_CFGR_MCO1PRE_0                 (0x1UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */\n#define RCC_CFGR_MCO1PRE_1                 (0x2UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */\n#define RCC_CFGR_MCO1PRE_2                 (0x4UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */\n\n#define RCC_CFGR_MCO2PRE_Pos               (27U)\n#define RCC_CFGR_MCO2PRE_Msk               (0x7UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */\n#define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk\n#define RCC_CFGR_MCO2PRE_0                 (0x1UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */\n#define RCC_CFGR_MCO2PRE_1                 (0x2UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */\n#define RCC_CFGR_MCO2PRE_2                 (0x4UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */\n\n#define RCC_CFGR_MCO2_Pos                  (30U)\n#define RCC_CFGR_MCO2_Msk                  (0x3UL << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */\n#define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk\n#define RCC_CFGR_MCO2_0                    (0x1UL << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */\n#define RCC_CFGR_MCO2_1                    (0x2UL << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */\n\n/********************  Bit definition for RCC_CIR register  *******************/\n#define RCC_CIR_LSIRDYF_Pos                (0U)\n#define RCC_CIR_LSIRDYF_Msk                (0x1UL << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */\n#define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk\n#define RCC_CIR_LSERDYF_Pos                (1U)\n#define RCC_CIR_LSERDYF_Msk                (0x1UL << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */\n#define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk\n#define RCC_CIR_HSIRDYF_Pos                (2U)\n#define RCC_CIR_HSIRDYF_Msk                (0x1UL << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */\n#define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk\n#define RCC_CIR_HSERDYF_Pos                (3U)\n#define RCC_CIR_HSERDYF_Msk                (0x1UL << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */\n#define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk\n#define RCC_CIR_PLLRDYF_Pos                (4U)\n#define RCC_CIR_PLLRDYF_Msk                (0x1UL << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */\n#define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk\n#define RCC_CIR_PLLI2SRDYF_Pos             (5U)\n#define RCC_CIR_PLLI2SRDYF_Msk             (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */\n#define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk\n\n#define RCC_CIR_CSSF_Pos                   (7U)\n#define RCC_CIR_CSSF_Msk                   (0x1UL << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */\n#define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk\n#define RCC_CIR_LSIRDYIE_Pos               (8U)\n#define RCC_CIR_LSIRDYIE_Msk               (0x1UL << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */\n#define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk\n#define RCC_CIR_LSERDYIE_Pos               (9U)\n#define RCC_CIR_LSERDYIE_Msk               (0x1UL << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */\n#define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk\n#define RCC_CIR_HSIRDYIE_Pos               (10U)\n#define RCC_CIR_HSIRDYIE_Msk               (0x1UL << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */\n#define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk\n#define RCC_CIR_HSERDYIE_Pos               (11U)\n#define RCC_CIR_HSERDYIE_Msk               (0x1UL << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */\n#define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk\n#define RCC_CIR_PLLRDYIE_Pos               (12U)\n#define RCC_CIR_PLLRDYIE_Msk               (0x1UL << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */\n#define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk\n#define RCC_CIR_PLLI2SRDYIE_Pos            (13U)\n#define RCC_CIR_PLLI2SRDYIE_Msk            (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */\n#define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk\n\n#define RCC_CIR_LSIRDYC_Pos                (16U)\n#define RCC_CIR_LSIRDYC_Msk                (0x1UL << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */\n#define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk\n#define RCC_CIR_LSERDYC_Pos                (17U)\n#define RCC_CIR_LSERDYC_Msk                (0x1UL << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */\n#define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk\n#define RCC_CIR_HSIRDYC_Pos                (18U)\n#define RCC_CIR_HSIRDYC_Msk                (0x1UL << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */\n#define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk\n#define RCC_CIR_HSERDYC_Pos                (19U)\n#define RCC_CIR_HSERDYC_Msk                (0x1UL << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */\n#define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk\n#define RCC_CIR_PLLRDYC_Pos                (20U)\n#define RCC_CIR_PLLRDYC_Msk                (0x1UL << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */\n#define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk\n#define RCC_CIR_PLLI2SRDYC_Pos             (21U)\n#define RCC_CIR_PLLI2SRDYC_Msk             (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */\n#define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk\n\n#define RCC_CIR_CSSC_Pos                   (23U)\n#define RCC_CIR_CSSC_Msk                   (0x1UL << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */\n#define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk\n\n/********************  Bit definition for RCC_AHB1RSTR register  **************/\n#define RCC_AHB1RSTR_GPIOARST_Pos          (0U)\n#define RCC_AHB1RSTR_GPIOARST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */\n#define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk\n#define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)\n#define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */\n#define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk\n#define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)\n#define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */\n#define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk\n#define RCC_AHB1RSTR_GPIODRST_Pos          (3U)\n#define RCC_AHB1RSTR_GPIODRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */\n#define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk\n#define RCC_AHB1RSTR_GPIOERST_Pos          (4U)\n#define RCC_AHB1RSTR_GPIOERST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */\n#define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk\n#define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)\n#define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */\n#define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk\n#define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)\n#define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */\n#define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk\n#define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)\n#define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk\n#define RCC_AHB1RSTR_CRCRST_Pos            (12U)\n#define RCC_AHB1RSTR_CRCRST_Msk            (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */\n#define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk\n#define RCC_AHB1RSTR_DMA1RST_Pos           (21U)\n#define RCC_AHB1RSTR_DMA1RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */\n#define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk\n#define RCC_AHB1RSTR_DMA2RST_Pos           (22U)\n#define RCC_AHB1RSTR_DMA2RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */\n#define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk\n\n/********************  Bit definition for RCC_AHB2RSTR register  **************/\n#define RCC_AHB2RSTR_RNGRST_Pos            (6U)\n#define RCC_AHB2RSTR_RNGRST_Msk            (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)   /*!< 0x00000040 */\n#define RCC_AHB2RSTR_RNGRST                RCC_AHB2RSTR_RNGRST_Msk\n#define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)\n#define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk\n/********************  Bit definition for RCC_AHB3RSTR register  **************/\n#define RCC_AHB3RSTR_FSMCRST_Pos           (0U)\n#define RCC_AHB3RSTR_FSMCRST_Msk           (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)  /*!< 0x00000001 */\n#define RCC_AHB3RSTR_FSMCRST               RCC_AHB3RSTR_FSMCRST_Msk\n#define RCC_AHB3RSTR_QSPIRST_Pos           (1U)\n#define RCC_AHB3RSTR_QSPIRST_Msk           (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)  /*!< 0x00000002 */\n#define RCC_AHB3RSTR_QSPIRST               RCC_AHB3RSTR_QSPIRST_Msk\n\n\n/********************  Bit definition for RCC_APB1RSTR register  **************/\n#define RCC_APB1RSTR_TIM2RST_Pos           (0U)\n#define RCC_APB1RSTR_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk\n#define RCC_APB1RSTR_TIM3RST_Pos           (1U)\n#define RCC_APB1RSTR_TIM3RST_Msk           (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk\n#define RCC_APB1RSTR_TIM4RST_Pos           (2U)\n#define RCC_APB1RSTR_TIM4RST_Msk           (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */\n#define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk\n#define RCC_APB1RSTR_TIM5RST_Pos           (3U)\n#define RCC_APB1RSTR_TIM5RST_Msk           (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */\n#define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk\n#define RCC_APB1RSTR_TIM6RST_Pos           (4U)\n#define RCC_APB1RSTR_TIM6RST_Msk           (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */\n#define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk\n#define RCC_APB1RSTR_TIM7RST_Pos           (5U)\n#define RCC_APB1RSTR_TIM7RST_Msk           (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */\n#define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk\n#define RCC_APB1RSTR_TIM12RST_Pos          (6U)\n#define RCC_APB1RSTR_TIM12RST_Msk          (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */\n#define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk\n#define RCC_APB1RSTR_TIM13RST_Pos          (7U)\n#define RCC_APB1RSTR_TIM13RST_Msk          (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */\n#define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk\n#define RCC_APB1RSTR_TIM14RST_Pos          (8U)\n#define RCC_APB1RSTR_TIM14RST_Msk          (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */\n#define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk\n#define RCC_APB1RSTR_LPTIM1RST_Pos         (9U)\n#define RCC_APB1RSTR_LPTIM1RST_Msk         (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */\n#define RCC_APB1RSTR_LPTIM1RST             RCC_APB1RSTR_LPTIM1RST_Msk\n#define RCC_APB1RSTR_WWDGRST_Pos           (11U)\n#define RCC_APB1RSTR_WWDGRST_Msk           (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */\n#define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk\n#define RCC_APB1RSTR_SPI2RST_Pos           (14U)\n#define RCC_APB1RSTR_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */\n#define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk\n#define RCC_APB1RSTR_SPI3RST_Pos           (15U)\n#define RCC_APB1RSTR_SPI3RST_Msk           (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */\n#define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk\n#define RCC_APB1RSTR_USART2RST_Pos         (17U)\n#define RCC_APB1RSTR_USART2RST_Msk         (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */\n#define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk\n#define RCC_APB1RSTR_USART3RST_Pos         (18U)\n#define RCC_APB1RSTR_USART3RST_Msk         (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */\n#define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk\n#define RCC_APB1RSTR_UART4RST_Pos          (19U)\n#define RCC_APB1RSTR_UART4RST_Msk          (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */\n#define RCC_APB1RSTR_UART4RST              RCC_APB1RSTR_UART4RST_Msk\n#define RCC_APB1RSTR_UART5RST_Pos          (20U)\n#define RCC_APB1RSTR_UART5RST_Msk          (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */\n#define RCC_APB1RSTR_UART5RST              RCC_APB1RSTR_UART5RST_Msk\n#define RCC_APB1RSTR_I2C1RST_Pos           (21U)\n#define RCC_APB1RSTR_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */\n#define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk\n#define RCC_APB1RSTR_I2C2RST_Pos           (22U)\n#define RCC_APB1RSTR_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */\n#define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk\n#define RCC_APB1RSTR_I2C3RST_Pos           (23U)\n#define RCC_APB1RSTR_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */\n#define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk\n#define RCC_APB1RSTR_FMPI2C1RST_Pos        (24U)\n#define RCC_APB1RSTR_FMPI2C1RST_Msk        (0x1UL << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */\n#define RCC_APB1RSTR_FMPI2C1RST            RCC_APB1RSTR_FMPI2C1RST_Msk\n#define RCC_APB1RSTR_CAN1RST_Pos           (25U)\n#define RCC_APB1RSTR_CAN1RST_Msk           (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */\n#define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk\n#define RCC_APB1RSTR_CAN2RST_Pos           (26U)\n#define RCC_APB1RSTR_CAN2RST_Msk           (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */\n#define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk\n#define RCC_APB1RSTR_CAN3RST_Pos           (27U)\n#define RCC_APB1RSTR_CAN3RST_Msk           (0x1UL << RCC_APB1RSTR_CAN3RST_Pos)  /*!< 0x08000000 */\n#define RCC_APB1RSTR_CAN3RST               RCC_APB1RSTR_CAN3RST_Msk\n#define RCC_APB1RSTR_PWRRST_Pos            (28U)\n#define RCC_APB1RSTR_PWRRST_Msk            (0x1UL << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */\n#define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk\n#define RCC_APB1RSTR_DACRST_Pos            (29U)\n#define RCC_APB1RSTR_DACRST_Msk            (0x1UL << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */\n#define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk\n#define RCC_APB1RSTR_UART7RST_Pos          (30U)\n#define RCC_APB1RSTR_UART7RST_Msk          (0x1UL << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */\n#define RCC_APB1RSTR_UART7RST              RCC_APB1RSTR_UART7RST_Msk\n#define RCC_APB1RSTR_UART8RST_Pos          (31U)\n#define RCC_APB1RSTR_UART8RST_Msk          (0x1UL << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */\n#define RCC_APB1RSTR_UART8RST              RCC_APB1RSTR_UART8RST_Msk\n\n/********************  Bit definition for RCC_APB2RSTR register  **************/\n#define RCC_APB2RSTR_TIM1RST_Pos           (0U)\n#define RCC_APB2RSTR_TIM1RST_Msk           (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk\n#define RCC_APB2RSTR_TIM8RST_Pos           (1U)\n#define RCC_APB2RSTR_TIM8RST_Msk           (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk\n#define RCC_APB2RSTR_USART1RST_Pos         (4U)\n#define RCC_APB2RSTR_USART1RST_Msk         (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */\n#define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk\n#define RCC_APB2RSTR_USART6RST_Pos         (5U)\n#define RCC_APB2RSTR_USART6RST_Msk         (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */\n#define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk\n#define RCC_APB2RSTR_UART9RST_Pos          (6U)\n#define RCC_APB2RSTR_UART9RST_Msk          (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */\n#define RCC_APB2RSTR_UART9RST              RCC_APB2RSTR_UART9RST_Msk\n#define RCC_APB2RSTR_UART10RST_Pos         (7U)\n#define RCC_APB2RSTR_UART10RST_Msk         (0x1UL << RCC_APB2RSTR_UART10RST_Pos) /*!< 0x00000080 */\n#define RCC_APB2RSTR_UART10RST             RCC_APB2RSTR_UART10RST_Msk\n#define RCC_APB2RSTR_ADCRST_Pos            (8U)\n#define RCC_APB2RSTR_ADCRST_Msk            (0x1UL << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */\n#define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk\n#define RCC_APB2RSTR_SDIORST_Pos           (11U)\n#define RCC_APB2RSTR_SDIORST_Msk           (0x1UL << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */\n#define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk\n#define RCC_APB2RSTR_SPI1RST_Pos           (12U)\n#define RCC_APB2RSTR_SPI1RST_Msk           (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */\n#define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk\n#define RCC_APB2RSTR_SPI4RST_Pos           (13U)\n#define RCC_APB2RSTR_SPI4RST_Msk           (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)  /*!< 0x00002000 */\n#define RCC_APB2RSTR_SPI4RST               RCC_APB2RSTR_SPI4RST_Msk\n#define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)\n#define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */\n#define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk\n#define RCC_APB2RSTR_TIM9RST_Pos           (16U)\n#define RCC_APB2RSTR_TIM9RST_Msk           (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */\n#define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk\n#define RCC_APB2RSTR_TIM10RST_Pos          (17U)\n#define RCC_APB2RSTR_TIM10RST_Msk          (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */\n#define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk\n#define RCC_APB2RSTR_TIM11RST_Pos          (18U)\n#define RCC_APB2RSTR_TIM11RST_Msk          (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */\n#define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk\n#define RCC_APB2RSTR_SPI5RST_Pos           (20U)\n#define RCC_APB2RSTR_SPI5RST_Msk           (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)  /*!< 0x00100000 */\n#define RCC_APB2RSTR_SPI5RST               RCC_APB2RSTR_SPI5RST_Msk\n#define RCC_APB2RSTR_SAI1RST_Pos           (22U)\n#define RCC_APB2RSTR_SAI1RST_Msk           (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)  /*!< 0x00400000 */\n#define RCC_APB2RSTR_SAI1RST               RCC_APB2RSTR_SAI1RST_Msk\n#define RCC_APB2RSTR_DFSDM1RST_Pos         (24U)\n#define RCC_APB2RSTR_DFSDM1RST_Msk         (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */\n#define RCC_APB2RSTR_DFSDM1RST             RCC_APB2RSTR_DFSDM1RST_Msk\n#define RCC_APB2RSTR_DFSDM2RST_Pos         (25U)\n#define RCC_APB2RSTR_DFSDM2RST_Msk         (0x1UL << RCC_APB2RSTR_DFSDM2RST_Pos) /*!< 0x02000000 */\n#define RCC_APB2RSTR_DFSDM2RST             RCC_APB2RSTR_DFSDM2RST_Msk\n\n/********************  Bit definition for RCC_AHB1ENR register  ***************/\n#define RCC_AHB1ENR_GPIOAEN_Pos            (0U)\n#define RCC_AHB1ENR_GPIOAEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */\n#define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk\n#define RCC_AHB1ENR_GPIOBEN_Pos            (1U)\n#define RCC_AHB1ENR_GPIOBEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */\n#define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk\n#define RCC_AHB1ENR_GPIOCEN_Pos            (2U)\n#define RCC_AHB1ENR_GPIOCEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */\n#define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk\n#define RCC_AHB1ENR_GPIODEN_Pos            (3U)\n#define RCC_AHB1ENR_GPIODEN_Msk            (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */\n#define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk\n#define RCC_AHB1ENR_GPIOEEN_Pos            (4U)\n#define RCC_AHB1ENR_GPIOEEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */\n#define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk\n#define RCC_AHB1ENR_GPIOFEN_Pos            (5U)\n#define RCC_AHB1ENR_GPIOFEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */\n#define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk\n#define RCC_AHB1ENR_GPIOGEN_Pos            (6U)\n#define RCC_AHB1ENR_GPIOGEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */\n#define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk\n#define RCC_AHB1ENR_GPIOHEN_Pos            (7U)\n#define RCC_AHB1ENR_GPIOHEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk\n#define RCC_AHB1ENR_CRCEN_Pos              (12U)\n#define RCC_AHB1ENR_CRCEN_Msk              (0x1UL << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */\n#define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk\n#define RCC_AHB1ENR_DMA1EN_Pos             (21U)\n#define RCC_AHB1ENR_DMA1EN_Msk             (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */\n#define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk\n#define RCC_AHB1ENR_DMA2EN_Pos             (22U)\n#define RCC_AHB1ENR_DMA2EN_Msk             (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */\n#define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk\n/********************  Bit definition for RCC_AHB2ENR register  ***************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_AHB2_SUPPORT                   /*!< AHB2 Bus is supported */\n\n#define RCC_AHB2ENR_RNGEN_Pos              (6U)\n#define RCC_AHB2ENR_RNGEN_Msk              (0x1UL << RCC_AHB2ENR_RNGEN_Pos)     /*!< 0x00000040 */\n#define RCC_AHB2ENR_RNGEN                  RCC_AHB2ENR_RNGEN_Msk\n#define RCC_AHB2ENR_OTGFSEN_Pos            (7U)\n#define RCC_AHB2ENR_OTGFSEN_Msk            (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk\n\n/********************  Bit definition for RCC_AHB3ENR register  ***************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_AHB3_SUPPORT                   /*!< AHB3 Bus is supported */\n\n#define RCC_AHB3ENR_FSMCEN_Pos             (0U)\n#define RCC_AHB3ENR_FSMCEN_Msk             (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)    /*!< 0x00000001 */\n#define RCC_AHB3ENR_FSMCEN                 RCC_AHB3ENR_FSMCEN_Msk\n#define RCC_AHB3ENR_QSPIEN_Pos             (1U)\n#define RCC_AHB3ENR_QSPIEN_Msk             (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)    /*!< 0x00000002 */\n#define RCC_AHB3ENR_QSPIEN                 RCC_AHB3ENR_QSPIEN_Msk\n\n/********************  Bit definition for RCC_APB1ENR register  ***************/\n#define RCC_APB1ENR_TIM2EN_Pos             (0U)\n#define RCC_APB1ENR_TIM2EN_Msk             (0x1UL << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk\n#define RCC_APB1ENR_TIM3EN_Pos             (1U)\n#define RCC_APB1ENR_TIM3EN_Msk             (0x1UL << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk\n#define RCC_APB1ENR_TIM4EN_Pos             (2U)\n#define RCC_APB1ENR_TIM4EN_Msk             (0x1UL << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */\n#define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk\n#define RCC_APB1ENR_TIM5EN_Pos             (3U)\n#define RCC_APB1ENR_TIM5EN_Msk             (0x1UL << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */\n#define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk\n#define RCC_APB1ENR_TIM6EN_Pos             (4U)\n#define RCC_APB1ENR_TIM6EN_Msk             (0x1UL << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */\n#define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk\n#define RCC_APB1ENR_TIM7EN_Pos             (5U)\n#define RCC_APB1ENR_TIM7EN_Msk             (0x1UL << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */\n#define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk\n#define RCC_APB1ENR_TIM12EN_Pos            (6U)\n#define RCC_APB1ENR_TIM12EN_Msk            (0x1UL << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */\n#define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk\n#define RCC_APB1ENR_TIM13EN_Pos            (7U)\n#define RCC_APB1ENR_TIM13EN_Msk            (0x1UL << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */\n#define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk\n#define RCC_APB1ENR_TIM14EN_Pos            (8U)\n#define RCC_APB1ENR_TIM14EN_Msk            (0x1UL << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */\n#define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk\n#define RCC_APB1ENR_LPTIM1EN_Pos           (9U)\n#define RCC_APB1ENR_LPTIM1EN_Msk           (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)  /*!< 0x00000200 */\n#define RCC_APB1ENR_LPTIM1EN               RCC_APB1ENR_LPTIM1EN_Msk\n#define RCC_APB1ENR_RTCAPBEN_Pos           (10U)\n#define RCC_APB1ENR_RTCAPBEN_Msk           (0x1UL << RCC_APB1ENR_RTCAPBEN_Pos)  /*!< 0x00000400 */\n#define RCC_APB1ENR_RTCAPBEN               RCC_APB1ENR_RTCAPBEN_Msk\n#define RCC_APB1ENR_WWDGEN_Pos             (11U)\n#define RCC_APB1ENR_WWDGEN_Msk             (0x1UL << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk\n#define RCC_APB1ENR_SPI2EN_Pos             (14U)\n#define RCC_APB1ENR_SPI2EN_Msk             (0x1UL << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */\n#define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk\n#define RCC_APB1ENR_SPI3EN_Pos             (15U)\n#define RCC_APB1ENR_SPI3EN_Msk             (0x1UL << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */\n#define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk\n#define RCC_APB1ENR_USART2EN_Pos           (17U)\n#define RCC_APB1ENR_USART2EN_Msk           (0x1UL << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */\n#define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk\n#define RCC_APB1ENR_USART3EN_Pos           (18U)\n#define RCC_APB1ENR_USART3EN_Msk           (0x1UL << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */\n#define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk\n#define RCC_APB1ENR_UART4EN_Pos            (19U)\n#define RCC_APB1ENR_UART4EN_Msk            (0x1UL << RCC_APB1ENR_UART4EN_Pos)   /*!< 0x00080000 */\n#define RCC_APB1ENR_UART4EN                RCC_APB1ENR_UART4EN_Msk\n#define RCC_APB1ENR_UART5EN_Pos            (20U)\n#define RCC_APB1ENR_UART5EN_Msk            (0x1UL << RCC_APB1ENR_UART5EN_Pos)   /*!< 0x00100000 */\n#define RCC_APB1ENR_UART5EN                RCC_APB1ENR_UART5EN_Msk\n#define RCC_APB1ENR_I2C1EN_Pos             (21U)\n#define RCC_APB1ENR_I2C1EN_Msk             (0x1UL << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */\n#define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk\n#define RCC_APB1ENR_I2C2EN_Pos             (22U)\n#define RCC_APB1ENR_I2C2EN_Msk             (0x1UL << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */\n#define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk\n#define RCC_APB1ENR_I2C3EN_Pos             (23U)\n#define RCC_APB1ENR_I2C3EN_Msk             (0x1UL << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */\n#define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk\n#define RCC_APB1ENR_FMPI2C1EN_Pos          (24U)\n#define RCC_APB1ENR_FMPI2C1EN_Msk          (0x1UL << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */\n#define RCC_APB1ENR_FMPI2C1EN              RCC_APB1ENR_FMPI2C1EN_Msk\n#define RCC_APB1ENR_CAN1EN_Pos             (25U)\n#define RCC_APB1ENR_CAN1EN_Msk             (0x1UL << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */\n#define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk\n#define RCC_APB1ENR_CAN2EN_Pos             (26U)\n#define RCC_APB1ENR_CAN2EN_Msk             (0x1UL << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */\n#define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk\n#define RCC_APB1ENR_CAN3EN_Pos             (27U)\n#define RCC_APB1ENR_CAN3EN_Msk             (0x1UL << RCC_APB1ENR_CAN3EN_Pos)    /*!< 0x08000000 */\n#define RCC_APB1ENR_CAN3EN                 RCC_APB1ENR_CAN3EN_Msk\n#define RCC_APB1ENR_PWREN_Pos              (28U)\n#define RCC_APB1ENR_PWREN_Msk              (0x1UL << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */\n#define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk\n#define RCC_APB1ENR_DACEN_Pos              (29U)\n#define RCC_APB1ENR_DACEN_Msk              (0x1UL << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */\n#define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk\n#define RCC_APB1ENR_UART7EN_Pos            (30U)\n#define RCC_APB1ENR_UART7EN_Msk            (0x1UL << RCC_APB1ENR_UART7EN_Pos)   /*!< 0x40000000 */\n#define RCC_APB1ENR_UART7EN                RCC_APB1ENR_UART7EN_Msk\n#define RCC_APB1ENR_UART8EN_Pos            (31U)\n#define RCC_APB1ENR_UART8EN_Msk            (0x1UL << RCC_APB1ENR_UART8EN_Pos)   /*!< 0x80000000 */\n#define RCC_APB1ENR_UART8EN                RCC_APB1ENR_UART8EN_Msk\n\n/********************  Bit definition for RCC_APB2ENR register  ***************/\n#define RCC_APB2ENR_TIM1EN_Pos             (0U)\n#define RCC_APB2ENR_TIM1EN_Msk             (0x1UL << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk\n#define RCC_APB2ENR_TIM8EN_Pos             (1U)\n#define RCC_APB2ENR_TIM8EN_Msk             (0x1UL << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk\n#define RCC_APB2ENR_USART1EN_Pos           (4U)\n#define RCC_APB2ENR_USART1EN_Msk           (0x1UL << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */\n#define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk\n#define RCC_APB2ENR_USART6EN_Pos           (5U)\n#define RCC_APB2ENR_USART6EN_Msk           (0x1UL << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */\n#define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk\n#define RCC_APB2ENR_UART9EN_Pos            (6U)\n#define RCC_APB2ENR_UART9EN_Msk            (0x1UL << RCC_APB2ENR_UART9EN_Pos)   /*!< 0x00000040 */\n#define RCC_APB2ENR_UART9EN                RCC_APB2ENR_UART9EN_Msk\n#define RCC_APB2ENR_UART10EN_Pos           (7U)\n#define RCC_APB2ENR_UART10EN_Msk           (0x1UL << RCC_APB2ENR_UART10EN_Pos)  /*!< 0x00000080 */\n#define RCC_APB2ENR_UART10EN               RCC_APB2ENR_UART10EN_Msk\n#define RCC_APB2ENR_ADC1EN_Pos             (8U)\n#define RCC_APB2ENR_ADC1EN_Msk             (0x1UL << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */\n#define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk\n#define RCC_APB2ENR_SDIOEN_Pos             (11U)\n#define RCC_APB2ENR_SDIOEN_Msk             (0x1UL << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk\n#define RCC_APB2ENR_SPI1EN_Pos             (12U)\n#define RCC_APB2ENR_SPI1EN_Msk             (0x1UL << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */\n#define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk\n#define RCC_APB2ENR_SPI4EN_Pos             (13U)\n#define RCC_APB2ENR_SPI4EN_Msk             (0x1UL << RCC_APB2ENR_SPI4EN_Pos)    /*!< 0x00002000 */\n#define RCC_APB2ENR_SPI4EN                 RCC_APB2ENR_SPI4EN_Msk\n#define RCC_APB2ENR_SYSCFGEN_Pos           (14U)\n#define RCC_APB2ENR_SYSCFGEN_Msk           (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */\n#define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk\n#define RCC_APB2ENR_EXTITEN_Pos            (15U)\n#define RCC_APB2ENR_EXTITEN_Msk            (0x1UL << RCC_APB2ENR_EXTITEN_Pos)   /*!< 0x00008000 */\n#define RCC_APB2ENR_EXTITEN                RCC_APB2ENR_EXTITEN_Msk\n#define RCC_APB2ENR_TIM9EN_Pos             (16U)\n#define RCC_APB2ENR_TIM9EN_Msk             (0x1UL << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */\n#define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk\n#define RCC_APB2ENR_TIM10EN_Pos            (17U)\n#define RCC_APB2ENR_TIM10EN_Msk            (0x1UL << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */\n#define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk\n#define RCC_APB2ENR_TIM11EN_Pos            (18U)\n#define RCC_APB2ENR_TIM11EN_Msk            (0x1UL << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */\n#define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk\n#define RCC_APB2ENR_SPI5EN_Pos             (20U)\n#define RCC_APB2ENR_SPI5EN_Msk             (0x1UL << RCC_APB2ENR_SPI5EN_Pos)    /*!< 0x00100000 */\n#define RCC_APB2ENR_SPI5EN                 RCC_APB2ENR_SPI5EN_Msk\n#define RCC_APB2ENR_SAI1EN_Pos             (22U)\n#define RCC_APB2ENR_SAI1EN_Msk             (0x1UL << RCC_APB2ENR_SAI1EN_Pos)    /*!< 0x00400000 */\n#define RCC_APB2ENR_SAI1EN                 RCC_APB2ENR_SAI1EN_Msk\n#define RCC_APB2ENR_DFSDM1EN_Pos           (24U)\n#define RCC_APB2ENR_DFSDM1EN_Msk           (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos)  /*!< 0x01000000 */\n#define RCC_APB2ENR_DFSDM1EN               RCC_APB2ENR_DFSDM1EN_Msk\n#define RCC_APB2ENR_DFSDM2EN_Pos           (25U)\n#define RCC_APB2ENR_DFSDM2EN_Msk           (0x1UL << RCC_APB2ENR_DFSDM2EN_Pos)  /*!< 0x02000000 */\n#define RCC_APB2ENR_DFSDM2EN               RCC_APB2ENR_DFSDM2EN_Msk\n\n/********************  Bit definition for RCC_AHB1LPENR register  *************/\n#define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)\n#define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk\n#define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)\n#define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk\n#define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)\n#define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */\n#define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk\n#define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)\n#define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */\n#define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk\n#define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)\n#define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */\n#define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk\n#define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)\n#define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */\n#define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk\n#define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)\n#define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk\n#define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)\n#define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk\n#define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)\n#define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */\n#define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk\n#define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)\n#define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */\n#define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk\n#define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)\n#define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */\n#define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk\n#define RCC_AHB1LPENR_SRAM2LPEN_Pos        (17U)\n#define RCC_AHB1LPENR_SRAM2LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */\n#define RCC_AHB1LPENR_SRAM2LPEN            RCC_AHB1LPENR_SRAM2LPEN_Msk\n#define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)\n#define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk\n#define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)\n#define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk\n\n\n/********************  Bit definition for RCC_AHB2LPENR register  *************/\n#define RCC_AHB2LPENR_RNGLPEN_Pos          (6U)\n#define RCC_AHB2LPENR_RNGLPEN_Msk          (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB2LPENR_RNGLPEN              RCC_AHB2LPENR_RNGLPEN_Msk\n#define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)\n#define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk\n\n/********************  Bit definition for RCC_AHB3LPENR register  *************/\n#define RCC_AHB3LPENR_FSMCLPEN_Pos         (0U)\n#define RCC_AHB3LPENR_FSMCLPEN_Msk         (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB3LPENR_FSMCLPEN             RCC_AHB3LPENR_FSMCLPEN_Msk\n#define RCC_AHB3LPENR_QSPILPEN_Pos         (1U)\n#define RCC_AHB3LPENR_QSPILPEN_Msk         (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB3LPENR_QSPILPEN             RCC_AHB3LPENR_QSPILPEN_Msk\n\n/********************  Bit definition for RCC_APB1LPENR register  *************/\n#define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)\n#define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk\n#define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)\n#define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk\n#define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)\n#define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */\n#define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk\n#define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)\n#define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */\n#define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk\n#define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)\n#define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk\n#define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)\n#define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk\n#define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)\n#define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */\n#define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk\n#define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)\n#define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */\n#define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk\n#define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)\n#define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk\n#define RCC_APB1LPENR_LPTIM1LPEN_Pos       (9U)\n#define RCC_APB1LPENR_LPTIM1LPEN_Msk       (0x1UL << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */\n#define RCC_APB1LPENR_LPTIM1LPEN           RCC_APB1LPENR_LPTIM1LPEN_Msk\n#define RCC_APB1LPENR_RTCAPBLPEN_Pos       (10U)\n#define RCC_APB1LPENR_RTCAPBLPEN_Msk       (0x1UL << RCC_APB1LPENR_RTCAPBLPEN_Pos) /*!< 0x00000400 */\n#define RCC_APB1LPENR_RTCAPBLPEN           RCC_APB1LPENR_RTCAPBLPEN_Msk\n#define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)\n#define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk\n#define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)\n#define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk\n#define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)\n#define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */\n#define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk\n#define RCC_APB1LPENR_USART2LPEN_Pos       (17U)\n#define RCC_APB1LPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk\n#define RCC_APB1LPENR_USART3LPEN_Pos       (18U)\n#define RCC_APB1LPENR_USART3LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk\n#define RCC_APB1LPENR_UART4LPEN_Pos        (19U)\n#define RCC_APB1LPENR_UART4LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */\n#define RCC_APB1LPENR_UART4LPEN            RCC_APB1LPENR_UART4LPEN_Msk\n#define RCC_APB1LPENR_UART5LPEN_Pos        (20U)\n#define RCC_APB1LPENR_UART5LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */\n#define RCC_APB1LPENR_UART5LPEN            RCC_APB1LPENR_UART5LPEN_Msk\n#define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)\n#define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk\n#define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)\n#define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk\n#define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)\n#define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */\n#define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk\n#define RCC_APB1LPENR_FMPI2C1LPEN_Pos      (24U)\n#define RCC_APB1LPENR_FMPI2C1LPEN_Msk      (0x1UL << RCC_APB1LPENR_FMPI2C1LPEN_Pos) /*!< 0x01000000 */\n#define RCC_APB1LPENR_FMPI2C1LPEN          RCC_APB1LPENR_FMPI2C1LPEN_Msk\n#define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)\n#define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */\n#define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk\n#define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)\n#define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */\n#define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk\n#define RCC_APB1LPENR_CAN3LPEN_Pos         (27U)\n#define RCC_APB1LPENR_CAN3LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN3LPEN_Pos) /*!< 0x08000000 */\n#define RCC_APB1LPENR_CAN3LPEN             RCC_APB1LPENR_CAN3LPEN_Msk\n#define RCC_APB1LPENR_PWRLPEN_Pos          (28U)\n#define RCC_APB1LPENR_PWRLPEN_Msk          (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */\n#define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk\n#define RCC_APB1LPENR_DACLPEN_Pos          (29U)\n#define RCC_APB1LPENR_DACLPEN_Msk          (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */\n#define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk\n#define RCC_APB1LPENR_UART7LPEN_Pos        (30U)\n#define RCC_APB1LPENR_UART7LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */\n#define RCC_APB1LPENR_UART7LPEN            RCC_APB1LPENR_UART7LPEN_Msk\n#define RCC_APB1LPENR_UART8LPEN_Pos        (31U)\n#define RCC_APB1LPENR_UART8LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */\n#define RCC_APB1LPENR_UART8LPEN            RCC_APB1LPENR_UART8LPEN_Msk\n\n/********************  Bit definition for RCC_APB2LPENR register  *************/\n#define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)\n#define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk\n#define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)\n#define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk\n#define RCC_APB2LPENR_USART1LPEN_Pos       (4U)\n#define RCC_APB2LPENR_USART1LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk\n#define RCC_APB2LPENR_USART6LPEN_Pos       (5U)\n#define RCC_APB2LPENR_USART6LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk\n#define RCC_APB2LPENR_UART9LPEN_Pos        (6U)\n#define RCC_APB2LPENR_UART9LPEN_Msk        (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos) /*!< 0x00000040 */\n#define RCC_APB2LPENR_UART9LPEN            RCC_APB2LPENR_UART9LPEN_Msk\n#define RCC_APB2LPENR_UART10LPEN_Pos       (7U)\n#define RCC_APB2LPENR_UART10LPEN_Msk       (0x1UL << RCC_APB2LPENR_UART10LPEN_Pos) /*!< 0x00000080 */\n#define RCC_APB2LPENR_UART10LPEN           RCC_APB2LPENR_UART10LPEN_Msk\n#define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)\n#define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk\n#define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)\n#define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk\n#define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)\n#define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */\n#define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk\n#define RCC_APB2LPENR_SPI4LPEN_Pos         (13U)\n#define RCC_APB2LPENR_SPI4LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */\n#define RCC_APB2LPENR_SPI4LPEN             RCC_APB2LPENR_SPI4LPEN_Msk\n#define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)\n#define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk\n#define RCC_APB2LPENR_EXTITLPEN_Pos        (15U)\n#define RCC_APB2LPENR_EXTITLPEN_Msk        (0x1UL << RCC_APB2LPENR_EXTITLPEN_Pos) /*!< 0x00008000 */\n#define RCC_APB2LPENR_EXTITLPEN            RCC_APB2LPENR_EXTITLPEN_Msk\n#define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)\n#define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */\n#define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk\n#define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)\n#define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk\n#define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)\n#define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk\n#define RCC_APB2LPENR_SPI5LPEN_Pos         (20U)\n#define RCC_APB2LPENR_SPI5LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */\n#define RCC_APB2LPENR_SPI5LPEN             RCC_APB2LPENR_SPI5LPEN_Msk\n#define RCC_APB2LPENR_SAI1LPEN_Pos         (22U)\n#define RCC_APB2LPENR_SAI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */\n#define RCC_APB2LPENR_SAI1LPEN             RCC_APB2LPENR_SAI1LPEN_Msk\n#define RCC_APB2LPENR_DFSDM1LPEN_Pos       (24U)\n#define RCC_APB2LPENR_DFSDM1LPEN_Msk       (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x01000000 */\n#define RCC_APB2LPENR_DFSDM1LPEN           RCC_APB2LPENR_DFSDM1LPEN_Msk\n#define RCC_APB2LPENR_DFSDM2LPEN_Pos       (25U)\n#define RCC_APB2LPENR_DFSDM2LPEN_Msk       (0x1UL << RCC_APB2LPENR_DFSDM2LPEN_Pos) /*!< 0x02000000 */\n#define RCC_APB2LPENR_DFSDM2LPEN           RCC_APB2LPENR_DFSDM2LPEN_Msk\n\n/********************  Bit definition for RCC_BDCR register  ******************/\n#define RCC_BDCR_LSEON_Pos                 (0U)\n#define RCC_BDCR_LSEON_Msk                 (0x1UL << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */\n#define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk\n#define RCC_BDCR_LSERDY_Pos                (1U)\n#define RCC_BDCR_LSERDY_Msk                (0x1UL << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */\n#define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk\n#define RCC_BDCR_LSEBYP_Pos                (2U)\n#define RCC_BDCR_LSEBYP_Msk                (0x1UL << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */\n#define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk\n#define RCC_BDCR_LSEMOD_Pos                (3U)\n#define RCC_BDCR_LSEMOD_Msk                (0x1UL << RCC_BDCR_LSEMOD_Pos)       /*!< 0x00000008 */\n#define RCC_BDCR_LSEMOD                    RCC_BDCR_LSEMOD_Msk\n\n#define RCC_BDCR_RTCSEL_Pos                (8U)\n#define RCC_BDCR_RTCSEL_Msk                (0x3UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */\n#define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk\n#define RCC_BDCR_RTCSEL_0                  (0x1UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */\n#define RCC_BDCR_RTCSEL_1                  (0x2UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */\n\n#define RCC_BDCR_RTCEN_Pos                 (15U)\n#define RCC_BDCR_RTCEN_Msk                 (0x1UL << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */\n#define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk\n#define RCC_BDCR_BDRST_Pos                 (16U)\n#define RCC_BDCR_BDRST_Msk                 (0x1UL << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */\n#define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk\n\n/********************  Bit definition for RCC_CSR register  *******************/\n#define RCC_CSR_LSION_Pos                  (0U)\n#define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */\n#define RCC_CSR_LSION                      RCC_CSR_LSION_Msk\n#define RCC_CSR_LSIRDY_Pos                 (1U)\n#define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */\n#define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk\n#define RCC_CSR_RMVF_Pos                   (24U)\n#define RCC_CSR_RMVF_Msk                   (0x1UL << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */\n#define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk\n#define RCC_CSR_BORRSTF_Pos                (25U)\n#define RCC_CSR_BORRSTF_Msk                (0x1UL << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */\n#define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk\n#define RCC_CSR_PINRSTF_Pos                (26U)\n#define RCC_CSR_PINRSTF_Msk                (0x1UL << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */\n#define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk\n#define RCC_CSR_PORRSTF_Pos                (27U)\n#define RCC_CSR_PORRSTF_Msk                (0x1UL << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */\n#define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk\n#define RCC_CSR_SFTRSTF_Pos                (28U)\n#define RCC_CSR_SFTRSTF_Msk                (0x1UL << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */\n#define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk\n#define RCC_CSR_IWDGRSTF_Pos               (29U)\n#define RCC_CSR_IWDGRSTF_Msk               (0x1UL << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */\n#define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk\n#define RCC_CSR_WWDGRSTF_Pos               (30U)\n#define RCC_CSR_WWDGRSTF_Msk               (0x1UL << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */\n#define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk\n#define RCC_CSR_LPWRRSTF_Pos               (31U)\n#define RCC_CSR_LPWRRSTF_Msk               (0x1UL << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */\n#define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk\n/* Legacy defines */\n#define RCC_CSR_PADRSTF                    RCC_CSR_PINRSTF\n#define RCC_CSR_WDGRSTF                    RCC_CSR_IWDGRSTF\n\n/********************  Bit definition for RCC_SSCGR register  *****************/\n#define RCC_SSCGR_MODPER_Pos               (0U)\n#define RCC_SSCGR_MODPER_Msk               (0x1FFFUL << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */\n#define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk\n#define RCC_SSCGR_INCSTEP_Pos              (13U)\n#define RCC_SSCGR_INCSTEP_Msk              (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */\n#define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk\n#define RCC_SSCGR_SPREADSEL_Pos            (30U)\n#define RCC_SSCGR_SPREADSEL_Msk            (0x1UL << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */\n#define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk\n#define RCC_SSCGR_SSCGEN_Pos               (31U)\n#define RCC_SSCGR_SSCGEN_Msk               (0x1UL << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */\n#define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk\n\n/********************  Bit definition for RCC_PLLI2SCFGR register  ************/\n#define RCC_PLLI2SCFGR_PLLI2SM_Pos         (0U)\n#define RCC_PLLI2SCFGR_PLLI2SM_Msk         (0x3FUL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */\n#define RCC_PLLI2SCFGR_PLLI2SM             RCC_PLLI2SCFGR_PLLI2SM_Msk\n#define RCC_PLLI2SCFGR_PLLI2SM_0           (0x01UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */\n#define RCC_PLLI2SCFGR_PLLI2SM_1           (0x02UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */\n#define RCC_PLLI2SCFGR_PLLI2SM_2           (0x04UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */\n#define RCC_PLLI2SCFGR_PLLI2SM_3           (0x08UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */\n#define RCC_PLLI2SCFGR_PLLI2SM_4           (0x10UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */\n#define RCC_PLLI2SCFGR_PLLI2SM_5           (0x20UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */\n\n#define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)\n#define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */\n#define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk\n#define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */\n#define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */\n#define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */\n#define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */\n#define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */\n#define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */\n#define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */\n\n#define RCC_PLLI2SCFGR_PLLI2SSRC_Pos       (22U)\n#define RCC_PLLI2SCFGR_PLLI2SSRC_Msk       (0x1UL << RCC_PLLI2SCFGR_PLLI2SSRC_Pos) /*!< 0x00400000 */\n#define RCC_PLLI2SCFGR_PLLI2SSRC           RCC_PLLI2SCFGR_PLLI2SSRC_Msk\n#define RCC_PLLI2SCFGR_PLLI2SQ_Pos         (24U)\n#define RCC_PLLI2SCFGR_PLLI2SQ_Msk         (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ             RCC_PLLI2SCFGR_PLLI2SQ_Msk\n#define RCC_PLLI2SCFGR_PLLI2SQ_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_3           (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)\n#define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk\n#define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */\n\n\n\n/********************  Bit definition for RCC_DCKCFGR register  ***************/\n#define RCC_DCKCFGR_PLLI2SDIVR_Pos         (0U)\n#define RCC_DCKCFGR_PLLI2SDIVR_Msk         (0x1FUL << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x0000001F */\n#define RCC_DCKCFGR_PLLI2SDIVR             RCC_DCKCFGR_PLLI2SDIVR_Msk\n#define RCC_DCKCFGR_PLLI2SDIVR_0           (0x01UL << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000001 */\n#define RCC_DCKCFGR_PLLI2SDIVR_1           (0x02UL << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000002 */\n#define RCC_DCKCFGR_PLLI2SDIVR_2           (0x04UL << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000004 */\n#define RCC_DCKCFGR_PLLI2SDIVR_3           (0x08UL << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000008 */\n#define RCC_DCKCFGR_PLLI2SDIVR_4           (0x10UL << RCC_DCKCFGR_PLLI2SDIVR_Pos) /*!< 0x00000010 */\n\n#define RCC_DCKCFGR_PLLDIVR_Pos            (8U)\n#define RCC_DCKCFGR_PLLDIVR_Msk            (0x1FUL << RCC_DCKCFGR_PLLDIVR_Pos)  /*!< 0x00001F00 */\n#define RCC_DCKCFGR_PLLDIVR                RCC_DCKCFGR_PLLDIVR_Msk\n#define RCC_DCKCFGR_PLLDIVR_0              (0x01UL << RCC_DCKCFGR_PLLDIVR_Pos)  /*!< 0x00000100 */\n#define RCC_DCKCFGR_PLLDIVR_1              (0x02UL << RCC_DCKCFGR_PLLDIVR_Pos)  /*!< 0x00000200 */\n#define RCC_DCKCFGR_PLLDIVR_2              (0x04UL << RCC_DCKCFGR_PLLDIVR_Pos)  /*!< 0x00000400 */\n#define RCC_DCKCFGR_PLLDIVR_3              (0x08UL << RCC_DCKCFGR_PLLDIVR_Pos)  /*!< 0x00000800 */\n#define RCC_DCKCFGR_PLLDIVR_4              (0x10UL << RCC_DCKCFGR_PLLDIVR_Pos)  /*!< 0x00001000 */\n\n#define RCC_DCKCFGR_CKDFSDM2ASEL_Pos       (14U)\n#define RCC_DCKCFGR_CKDFSDM2ASEL_Msk       (0x1UL << RCC_DCKCFGR_CKDFSDM2ASEL_Pos) /*!< 0x00004000 */\n#define RCC_DCKCFGR_CKDFSDM2ASEL           RCC_DCKCFGR_CKDFSDM2ASEL_Msk\n#define RCC_DCKCFGR_CKDFSDM1ASEL_Pos       (15U)\n#define RCC_DCKCFGR_CKDFSDM1ASEL_Msk       (0x1UL << RCC_DCKCFGR_CKDFSDM1ASEL_Pos) /*!< 0x00008000 */\n#define RCC_DCKCFGR_CKDFSDM1ASEL           RCC_DCKCFGR_CKDFSDM1ASEL_Msk\n\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define  RCC_SAI1A_PLLSOURCE_SUPPORT      /*!< SAI1 block A PLL Main source clock support */\n#define  RCC_SAI1B_PLLSOURCE_SUPPORT      /*!< SAI1 block B PLL Main source clock support */\n\n#define RCC_DCKCFGR_SAI1ASRC_Pos           (20U)\n#define RCC_DCKCFGR_SAI1ASRC_Msk           (0x3UL << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00300000 */\n#define RCC_DCKCFGR_SAI1ASRC               RCC_DCKCFGR_SAI1ASRC_Msk\n#define RCC_DCKCFGR_SAI1ASRC_0             (0x1UL << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00100000 */\n#define RCC_DCKCFGR_SAI1ASRC_1             (0x2UL << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00200000 */\n#define RCC_DCKCFGR_SAI1BSRC_Pos           (22U)\n#define RCC_DCKCFGR_SAI1BSRC_Msk           (0x3UL << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00C00000 */\n#define RCC_DCKCFGR_SAI1BSRC               RCC_DCKCFGR_SAI1BSRC_Msk\n#define RCC_DCKCFGR_SAI1BSRC_0             (0x1UL << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00400000 */\n#define RCC_DCKCFGR_SAI1BSRC_1             (0x2UL << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00800000 */\n#define RCC_DCKCFGR_TIMPRE_Pos             (24U)\n#define RCC_DCKCFGR_TIMPRE_Msk             (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)    /*!< 0x01000000 */\n#define RCC_DCKCFGR_TIMPRE                 RCC_DCKCFGR_TIMPRE_Msk\n#define RCC_DCKCFGR_I2S1SRC_Pos            (25U)\n#define RCC_DCKCFGR_I2S1SRC_Msk            (0x3UL << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x06000000 */\n#define RCC_DCKCFGR_I2S1SRC                RCC_DCKCFGR_I2S1SRC_Msk\n#define RCC_DCKCFGR_I2S1SRC_0              (0x1UL << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x02000000 */\n#define RCC_DCKCFGR_I2S1SRC_1              (0x2UL << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x04000000 */\n\n#define RCC_DCKCFGR_I2S2SRC_Pos            (27U)\n#define RCC_DCKCFGR_I2S2SRC_Msk            (0x3UL << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x18000000 */\n#define RCC_DCKCFGR_I2S2SRC                RCC_DCKCFGR_I2S2SRC_Msk\n#define RCC_DCKCFGR_I2S2SRC_0              (0x1UL << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x08000000 */\n#define RCC_DCKCFGR_I2S2SRC_1              (0x2UL << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x10000000 */\n#define RCC_DCKCFGR_CKDFSDM1SEL_Pos        (31U)\n#define RCC_DCKCFGR_CKDFSDM1SEL_Msk        (0x1UL << RCC_DCKCFGR_CKDFSDM1SEL_Pos) /*!< 0x80000000 */\n#define RCC_DCKCFGR_CKDFSDM1SEL            RCC_DCKCFGR_CKDFSDM1SEL_Msk\n\n/********************  Bit definition for RCC_CKGATENR register  ***************/\n#define RCC_CKGATENR_AHB2APB1_CKEN_Pos     (0U)\n#define RCC_CKGATENR_AHB2APB1_CKEN_Msk     (0x1UL << RCC_CKGATENR_AHB2APB1_CKEN_Pos) /*!< 0x00000001 */\n#define RCC_CKGATENR_AHB2APB1_CKEN         RCC_CKGATENR_AHB2APB1_CKEN_Msk\n#define RCC_CKGATENR_AHB2APB2_CKEN_Pos     (1U)\n#define RCC_CKGATENR_AHB2APB2_CKEN_Msk     (0x1UL << RCC_CKGATENR_AHB2APB2_CKEN_Pos) /*!< 0x00000002 */\n#define RCC_CKGATENR_AHB2APB2_CKEN         RCC_CKGATENR_AHB2APB2_CKEN_Msk\n#define RCC_CKGATENR_CM4DBG_CKEN_Pos       (2U)\n#define RCC_CKGATENR_CM4DBG_CKEN_Msk       (0x1UL << RCC_CKGATENR_CM4DBG_CKEN_Pos) /*!< 0x00000004 */\n#define RCC_CKGATENR_CM4DBG_CKEN           RCC_CKGATENR_CM4DBG_CKEN_Msk\n#define RCC_CKGATENR_SPARE_CKEN_Pos        (3U)\n#define RCC_CKGATENR_SPARE_CKEN_Msk        (0x1UL << RCC_CKGATENR_SPARE_CKEN_Pos) /*!< 0x00000008 */\n#define RCC_CKGATENR_SPARE_CKEN            RCC_CKGATENR_SPARE_CKEN_Msk\n#define RCC_CKGATENR_SRAM_CKEN_Pos         (4U)\n#define RCC_CKGATENR_SRAM_CKEN_Msk         (0x1UL << RCC_CKGATENR_SRAM_CKEN_Pos) /*!< 0x00000010 */\n#define RCC_CKGATENR_SRAM_CKEN             RCC_CKGATENR_SRAM_CKEN_Msk\n#define RCC_CKGATENR_FLITF_CKEN_Pos        (5U)\n#define RCC_CKGATENR_FLITF_CKEN_Msk        (0x1UL << RCC_CKGATENR_FLITF_CKEN_Pos) /*!< 0x00000020 */\n#define RCC_CKGATENR_FLITF_CKEN            RCC_CKGATENR_FLITF_CKEN_Msk\n#define RCC_CKGATENR_RCC_CKEN_Pos          (6U)\n#define RCC_CKGATENR_RCC_CKEN_Msk          (0x1UL << RCC_CKGATENR_RCC_CKEN_Pos) /*!< 0x00000040 */\n#define RCC_CKGATENR_RCC_CKEN              RCC_CKGATENR_RCC_CKEN_Msk\n#define RCC_CKGATENR_RCC_EVTCTL_Pos        (7U)\n#define RCC_CKGATENR_RCC_EVTCTL_Msk        (0x1UL << RCC_CKGATENR_RCC_EVTCTL_Pos) /*!< 0x00000080 */\n#define RCC_CKGATENR_RCC_EVTCTL            RCC_CKGATENR_RCC_EVTCTL_Msk\n\n/********************  Bit definition for RCC_DCKCFGR2 register  ***************/\n#define RCC_DCKCFGR2_FMPI2C1SEL_Pos        (22U)\n#define RCC_DCKCFGR2_FMPI2C1SEL_Msk        (0x3UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */\n#define RCC_DCKCFGR2_FMPI2C1SEL            RCC_DCKCFGR2_FMPI2C1SEL_Msk\n#define RCC_DCKCFGR2_FMPI2C1SEL_0          (0x1UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */\n#define RCC_DCKCFGR2_FMPI2C1SEL_1          (0x2UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */\n#define RCC_DCKCFGR2_CK48MSEL_Pos          (27U)\n#define RCC_DCKCFGR2_CK48MSEL_Msk          (0x1UL << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */\n#define RCC_DCKCFGR2_CK48MSEL              RCC_DCKCFGR2_CK48MSEL_Msk\n#define RCC_DCKCFGR2_SDIOSEL_Pos           (28U)\n#define RCC_DCKCFGR2_SDIOSEL_Msk           (0x1UL << RCC_DCKCFGR2_SDIOSEL_Pos)  /*!< 0x10000000 */\n#define RCC_DCKCFGR2_SDIOSEL               RCC_DCKCFGR2_SDIOSEL_Msk\n#define RCC_DCKCFGR2_LPTIM1SEL_Pos         (30U)\n#define RCC_DCKCFGR2_LPTIM1SEL_Msk         (0x3UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0xC0000000 */\n#define RCC_DCKCFGR2_LPTIM1SEL             RCC_DCKCFGR2_LPTIM1SEL_Msk\n#define RCC_DCKCFGR2_LPTIM1SEL_0           (0x1UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x40000000 */\n#define RCC_DCKCFGR2_LPTIM1SEL_1           (0x2UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x80000000 */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    RNG                                     */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RNG_CR register  *******************/\n#define RNG_CR_RNGEN_Pos    (2U)\n#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */\n#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk\n#define RNG_CR_IE_Pos       (3U)\n#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */\n#define RNG_CR_IE           RNG_CR_IE_Msk\n\n/********************  Bits definition for RNG_SR register  *******************/\n#define RNG_SR_DRDY_Pos     (0U)\n#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */\n#define RNG_SR_DRDY         RNG_SR_DRDY_Msk\n#define RNG_SR_CECS_Pos     (1U)\n#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */\n#define RNG_SR_CECS         RNG_SR_CECS_Msk\n#define RNG_SR_SECS_Pos     (2U)\n#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */\n#define RNG_SR_SECS         RNG_SR_SECS_Msk\n#define RNG_SR_CEIS_Pos     (5U)\n#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */\n#define RNG_SR_CEIS         RNG_SR_CEIS_Msk\n#define RNG_SR_SEIS_Pos     (6U)\n#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */\n#define RNG_SR_SEIS         RNG_SR_SEIS_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Real-Time Clock (RTC)                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RTC_TR register  *******************/\n#define RTC_TR_PM_Pos                 (22U)\n#define RTC_TR_PM_Msk                 (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */\n#define RTC_TR_PM                     RTC_TR_PM_Msk\n#define RTC_TR_HT_Pos                 (20U)\n#define RTC_TR_HT_Msk                 (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */\n#define RTC_TR_HT                     RTC_TR_HT_Msk\n#define RTC_TR_HT_0                   (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */\n#define RTC_TR_HT_1                   (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */\n#define RTC_TR_HU_Pos                 (16U)\n#define RTC_TR_HU_Msk                 (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */\n#define RTC_TR_HU                     RTC_TR_HU_Msk\n#define RTC_TR_HU_0                   (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */\n#define RTC_TR_HU_1                   (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */\n#define RTC_TR_HU_2                   (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */\n#define RTC_TR_HU_3                   (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */\n#define RTC_TR_MNT_Pos                (12U)\n#define RTC_TR_MNT_Msk                (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */\n#define RTC_TR_MNT                    RTC_TR_MNT_Msk\n#define RTC_TR_MNT_0                  (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */\n#define RTC_TR_MNT_1                  (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */\n#define RTC_TR_MNT_2                  (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */\n#define RTC_TR_MNU_Pos                (8U)\n#define RTC_TR_MNU_Msk                (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */\n#define RTC_TR_MNU                    RTC_TR_MNU_Msk\n#define RTC_TR_MNU_0                  (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */\n#define RTC_TR_MNU_1                  (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */\n#define RTC_TR_MNU_2                  (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */\n#define RTC_TR_MNU_3                  (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */\n#define RTC_TR_ST_Pos                 (4U)\n#define RTC_TR_ST_Msk                 (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */\n#define RTC_TR_ST                     RTC_TR_ST_Msk\n#define RTC_TR_ST_0                   (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */\n#define RTC_TR_ST_1                   (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */\n#define RTC_TR_ST_2                   (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */\n#define RTC_TR_SU_Pos                 (0U)\n#define RTC_TR_SU_Msk                 (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */\n#define RTC_TR_SU                     RTC_TR_SU_Msk\n#define RTC_TR_SU_0                   (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */\n#define RTC_TR_SU_1                   (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */\n#define RTC_TR_SU_2                   (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */\n#define RTC_TR_SU_3                   (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_DR register  *******************/\n#define RTC_DR_YT_Pos                 (20U)\n#define RTC_DR_YT_Msk                 (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */\n#define RTC_DR_YT                     RTC_DR_YT_Msk\n#define RTC_DR_YT_0                   (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */\n#define RTC_DR_YT_1                   (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */\n#define RTC_DR_YT_2                   (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */\n#define RTC_DR_YT_3                   (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */\n#define RTC_DR_YU_Pos                 (16U)\n#define RTC_DR_YU_Msk                 (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */\n#define RTC_DR_YU                     RTC_DR_YU_Msk\n#define RTC_DR_YU_0                   (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */\n#define RTC_DR_YU_1                   (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */\n#define RTC_DR_YU_2                   (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */\n#define RTC_DR_YU_3                   (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */\n#define RTC_DR_WDU_Pos                (13U)\n#define RTC_DR_WDU_Msk                (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */\n#define RTC_DR_WDU                    RTC_DR_WDU_Msk\n#define RTC_DR_WDU_0                  (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */\n#define RTC_DR_WDU_1                  (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */\n#define RTC_DR_WDU_2                  (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */\n#define RTC_DR_MT_Pos                 (12U)\n#define RTC_DR_MT_Msk                 (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */\n#define RTC_DR_MT                     RTC_DR_MT_Msk\n#define RTC_DR_MU_Pos                 (8U)\n#define RTC_DR_MU_Msk                 (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */\n#define RTC_DR_MU                     RTC_DR_MU_Msk\n#define RTC_DR_MU_0                   (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */\n#define RTC_DR_MU_1                   (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */\n#define RTC_DR_MU_2                   (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */\n#define RTC_DR_MU_3                   (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */\n#define RTC_DR_DT_Pos                 (4U)\n#define RTC_DR_DT_Msk                 (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */\n#define RTC_DR_DT                     RTC_DR_DT_Msk\n#define RTC_DR_DT_0                   (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */\n#define RTC_DR_DT_1                   (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */\n#define RTC_DR_DU_Pos                 (0U)\n#define RTC_DR_DU_Msk                 (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */\n#define RTC_DR_DU                     RTC_DR_DU_Msk\n#define RTC_DR_DU_0                   (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */\n#define RTC_DR_DU_1                   (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */\n#define RTC_DR_DU_2                   (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */\n#define RTC_DR_DU_3                   (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_CR register  *******************/\n#define RTC_CR_COE_Pos                (23U)\n#define RTC_CR_COE_Msk                (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */\n#define RTC_CR_COE                    RTC_CR_COE_Msk\n#define RTC_CR_OSEL_Pos               (21U)\n#define RTC_CR_OSEL_Msk               (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */\n#define RTC_CR_OSEL                   RTC_CR_OSEL_Msk\n#define RTC_CR_OSEL_0                 (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */\n#define RTC_CR_OSEL_1                 (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */\n#define RTC_CR_POL_Pos                (20U)\n#define RTC_CR_POL_Msk                (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */\n#define RTC_CR_POL                    RTC_CR_POL_Msk\n#define RTC_CR_COSEL_Pos              (19U)\n#define RTC_CR_COSEL_Msk              (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */\n#define RTC_CR_COSEL                  RTC_CR_COSEL_Msk\n#define RTC_CR_BKP_Pos                 (18U)\n#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */\n#define RTC_CR_BKP                     RTC_CR_BKP_Msk\n#define RTC_CR_SUB1H_Pos              (17U)\n#define RTC_CR_SUB1H_Msk              (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */\n#define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk\n#define RTC_CR_ADD1H_Pos              (16U)\n#define RTC_CR_ADD1H_Msk              (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */\n#define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk\n#define RTC_CR_TSIE_Pos               (15U)\n#define RTC_CR_TSIE_Msk               (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */\n#define RTC_CR_TSIE                   RTC_CR_TSIE_Msk\n#define RTC_CR_WUTIE_Pos              (14U)\n#define RTC_CR_WUTIE_Msk              (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */\n#define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk\n#define RTC_CR_ALRBIE_Pos             (13U)\n#define RTC_CR_ALRBIE_Msk             (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */\n#define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk\n#define RTC_CR_ALRAIE_Pos             (12U)\n#define RTC_CR_ALRAIE_Msk             (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */\n#define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk\n#define RTC_CR_TSE_Pos                (11U)\n#define RTC_CR_TSE_Msk                (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */\n#define RTC_CR_TSE                    RTC_CR_TSE_Msk\n#define RTC_CR_WUTE_Pos               (10U)\n#define RTC_CR_WUTE_Msk               (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */\n#define RTC_CR_WUTE                   RTC_CR_WUTE_Msk\n#define RTC_CR_ALRBE_Pos              (9U)\n#define RTC_CR_ALRBE_Msk              (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */\n#define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk\n#define RTC_CR_ALRAE_Pos              (8U)\n#define RTC_CR_ALRAE_Msk              (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */\n#define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk\n#define RTC_CR_DCE_Pos                (7U)\n#define RTC_CR_DCE_Msk                (0x1UL << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */\n#define RTC_CR_DCE                    RTC_CR_DCE_Msk\n#define RTC_CR_FMT_Pos                (6U)\n#define RTC_CR_FMT_Msk                (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */\n#define RTC_CR_FMT                    RTC_CR_FMT_Msk\n#define RTC_CR_BYPSHAD_Pos            (5U)\n#define RTC_CR_BYPSHAD_Msk            (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */\n#define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk\n#define RTC_CR_REFCKON_Pos            (4U)\n#define RTC_CR_REFCKON_Msk            (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */\n#define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk\n#define RTC_CR_TSEDGE_Pos             (3U)\n#define RTC_CR_TSEDGE_Msk             (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */\n#define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk\n#define RTC_CR_WUCKSEL_Pos            (0U)\n#define RTC_CR_WUCKSEL_Msk            (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */\n#define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk\n#define RTC_CR_WUCKSEL_0              (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */\n#define RTC_CR_WUCKSEL_1              (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */\n#define RTC_CR_WUCKSEL_2              (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */\n\n/* Legacy defines */\n#define RTC_CR_BCK                     RTC_CR_BKP\n\n/********************  Bits definition for RTC_ISR register  ******************/\n#define RTC_ISR_RECALPF_Pos           (16U)\n#define RTC_ISR_RECALPF_Msk           (0x1UL << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */\n#define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk\n#define RTC_ISR_TAMP1F_Pos            (13U)\n#define RTC_ISR_TAMP1F_Msk            (0x1UL << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */\n#define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk\n#define RTC_ISR_TAMP2F_Pos            (14U)\n#define RTC_ISR_TAMP2F_Msk            (0x1UL << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */\n#define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk\n#define RTC_ISR_TSOVF_Pos             (12U)\n#define RTC_ISR_TSOVF_Msk             (0x1UL << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */\n#define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk\n#define RTC_ISR_TSF_Pos               (11U)\n#define RTC_ISR_TSF_Msk               (0x1UL << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */\n#define RTC_ISR_TSF                   RTC_ISR_TSF_Msk\n#define RTC_ISR_WUTF_Pos              (10U)\n#define RTC_ISR_WUTF_Msk              (0x1UL << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */\n#define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk\n#define RTC_ISR_ALRBF_Pos             (9U)\n#define RTC_ISR_ALRBF_Msk             (0x1UL << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */\n#define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk\n#define RTC_ISR_ALRAF_Pos             (8U)\n#define RTC_ISR_ALRAF_Msk             (0x1UL << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */\n#define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk\n#define RTC_ISR_INIT_Pos              (7U)\n#define RTC_ISR_INIT_Msk              (0x1UL << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */\n#define RTC_ISR_INIT                  RTC_ISR_INIT_Msk\n#define RTC_ISR_INITF_Pos             (6U)\n#define RTC_ISR_INITF_Msk             (0x1UL << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */\n#define RTC_ISR_INITF                 RTC_ISR_INITF_Msk\n#define RTC_ISR_RSF_Pos               (5U)\n#define RTC_ISR_RSF_Msk               (0x1UL << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */\n#define RTC_ISR_RSF                   RTC_ISR_RSF_Msk\n#define RTC_ISR_INITS_Pos             (4U)\n#define RTC_ISR_INITS_Msk             (0x1UL << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */\n#define RTC_ISR_INITS                 RTC_ISR_INITS_Msk\n#define RTC_ISR_SHPF_Pos              (3U)\n#define RTC_ISR_SHPF_Msk              (0x1UL << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */\n#define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk\n#define RTC_ISR_WUTWF_Pos             (2U)\n#define RTC_ISR_WUTWF_Msk             (0x1UL << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */\n#define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk\n#define RTC_ISR_ALRBWF_Pos            (1U)\n#define RTC_ISR_ALRBWF_Msk            (0x1UL << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */\n#define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk\n#define RTC_ISR_ALRAWF_Pos            (0U)\n#define RTC_ISR_ALRAWF_Msk            (0x1UL << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */\n#define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk\n\n/********************  Bits definition for RTC_PRER register  *****************/\n#define RTC_PRER_PREDIV_A_Pos         (16U)\n#define RTC_PRER_PREDIV_A_Msk         (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */\n#define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk\n#define RTC_PRER_PREDIV_S_Pos         (0U)\n#define RTC_PRER_PREDIV_S_Msk         (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */\n#define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk\n\n/********************  Bits definition for RTC_WUTR register  *****************/\n#define RTC_WUTR_WUT_Pos              (0U)\n#define RTC_WUTR_WUT_Msk              (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */\n#define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk\n\n/********************  Bits definition for RTC_CALIBR register  ***************/\n#define RTC_CALIBR_DCS_Pos            (7U)\n#define RTC_CALIBR_DCS_Msk            (0x1UL << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */\n#define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk\n#define RTC_CALIBR_DC_Pos             (0U)\n#define RTC_CALIBR_DC_Msk             (0x1FUL << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */\n#define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk\n\n/********************  Bits definition for RTC_ALRMAR register  ***************/\n#define RTC_ALRMAR_MSK4_Pos           (31U)\n#define RTC_ALRMAR_MSK4_Msk           (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk\n#define RTC_ALRMAR_WDSEL_Pos          (30U)\n#define RTC_ALRMAR_WDSEL_Msk          (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk\n#define RTC_ALRMAR_DT_Pos             (28U)\n#define RTC_ALRMAR_DT_Msk             (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk\n#define RTC_ALRMAR_DT_0               (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMAR_DT_1               (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMAR_DU_Pos             (24U)\n#define RTC_ALRMAR_DU_Msk             (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk\n#define RTC_ALRMAR_DU_0               (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMAR_DU_1               (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMAR_DU_2               (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMAR_DU_3               (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMAR_MSK3_Pos           (23U)\n#define RTC_ALRMAR_MSK3_Msk           (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk\n#define RTC_ALRMAR_PM_Pos             (22U)\n#define RTC_ALRMAR_PM_Msk             (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk\n#define RTC_ALRMAR_HT_Pos             (20U)\n#define RTC_ALRMAR_HT_Msk             (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk\n#define RTC_ALRMAR_HT_0               (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMAR_HT_1               (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMAR_HU_Pos             (16U)\n#define RTC_ALRMAR_HU_Msk             (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk\n#define RTC_ALRMAR_HU_0               (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMAR_HU_1               (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMAR_HU_2               (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMAR_HU_3               (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMAR_MSK2_Pos           (15U)\n#define RTC_ALRMAR_MSK2_Msk           (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk\n#define RTC_ALRMAR_MNT_Pos            (12U)\n#define RTC_ALRMAR_MNT_Msk            (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk\n#define RTC_ALRMAR_MNT_0              (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMAR_MNT_1              (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMAR_MNT_2              (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMAR_MNU_Pos            (8U)\n#define RTC_ALRMAR_MNU_Msk            (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk\n#define RTC_ALRMAR_MNU_0              (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMAR_MNU_1              (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMAR_MNU_2              (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMAR_MNU_3              (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMAR_MSK1_Pos           (7U)\n#define RTC_ALRMAR_MSK1_Msk           (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk\n#define RTC_ALRMAR_ST_Pos             (4U)\n#define RTC_ALRMAR_ST_Msk             (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk\n#define RTC_ALRMAR_ST_0               (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMAR_ST_1               (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMAR_ST_2               (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMAR_SU_Pos             (0U)\n#define RTC_ALRMAR_SU_Msk             (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk\n#define RTC_ALRMAR_SU_0               (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMAR_SU_1               (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMAR_SU_2               (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMAR_SU_3               (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_ALRMBR register  ***************/\n#define RTC_ALRMBR_MSK4_Pos           (31U)\n#define RTC_ALRMBR_MSK4_Msk           (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk\n#define RTC_ALRMBR_WDSEL_Pos          (30U)\n#define RTC_ALRMBR_WDSEL_Msk          (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk\n#define RTC_ALRMBR_DT_Pos             (28U)\n#define RTC_ALRMBR_DT_Msk             (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk\n#define RTC_ALRMBR_DT_0               (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMBR_DT_1               (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMBR_DU_Pos             (24U)\n#define RTC_ALRMBR_DU_Msk             (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk\n#define RTC_ALRMBR_DU_0               (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMBR_DU_1               (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMBR_DU_2               (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMBR_DU_3               (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMBR_MSK3_Pos           (23U)\n#define RTC_ALRMBR_MSK3_Msk           (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk\n#define RTC_ALRMBR_PM_Pos             (22U)\n#define RTC_ALRMBR_PM_Msk             (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk\n#define RTC_ALRMBR_HT_Pos             (20U)\n#define RTC_ALRMBR_HT_Msk             (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk\n#define RTC_ALRMBR_HT_0               (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMBR_HT_1               (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMBR_HU_Pos             (16U)\n#define RTC_ALRMBR_HU_Msk             (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk\n#define RTC_ALRMBR_HU_0               (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMBR_HU_1               (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMBR_HU_2               (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMBR_HU_3               (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMBR_MSK2_Pos           (15U)\n#define RTC_ALRMBR_MSK2_Msk           (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk\n#define RTC_ALRMBR_MNT_Pos            (12U)\n#define RTC_ALRMBR_MNT_Msk            (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk\n#define RTC_ALRMBR_MNT_0              (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMBR_MNT_1              (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMBR_MNT_2              (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMBR_MNU_Pos            (8U)\n#define RTC_ALRMBR_MNU_Msk            (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk\n#define RTC_ALRMBR_MNU_0              (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMBR_MNU_1              (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMBR_MNU_2              (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMBR_MNU_3              (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMBR_MSK1_Pos           (7U)\n#define RTC_ALRMBR_MSK1_Msk           (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk\n#define RTC_ALRMBR_ST_Pos             (4U)\n#define RTC_ALRMBR_ST_Msk             (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk\n#define RTC_ALRMBR_ST_0               (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMBR_ST_1               (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMBR_ST_2               (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMBR_SU_Pos             (0U)\n#define RTC_ALRMBR_SU_Msk             (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk\n#define RTC_ALRMBR_SU_0               (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMBR_SU_1               (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMBR_SU_2               (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMBR_SU_3               (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_WPR register  ******************/\n#define RTC_WPR_KEY_Pos               (0U)\n#define RTC_WPR_KEY_Msk               (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */\n#define RTC_WPR_KEY                   RTC_WPR_KEY_Msk\n\n/********************  Bits definition for RTC_SSR register  ******************/\n#define RTC_SSR_SS_Pos                (0U)\n#define RTC_SSR_SS_Msk                (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */\n#define RTC_SSR_SS                    RTC_SSR_SS_Msk\n\n/********************  Bits definition for RTC_SHIFTR register  ***************/\n#define RTC_SHIFTR_SUBFS_Pos          (0U)\n#define RTC_SHIFTR_SUBFS_Msk          (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */\n#define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk\n#define RTC_SHIFTR_ADD1S_Pos          (31U)\n#define RTC_SHIFTR_ADD1S_Msk          (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */\n#define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk\n\n/********************  Bits definition for RTC_TSTR register  *****************/\n#define RTC_TSTR_PM_Pos               (22U)\n#define RTC_TSTR_PM_Msk               (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */\n#define RTC_TSTR_PM                   RTC_TSTR_PM_Msk\n#define RTC_TSTR_HT_Pos               (20U)\n#define RTC_TSTR_HT_Msk               (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */\n#define RTC_TSTR_HT                   RTC_TSTR_HT_Msk\n#define RTC_TSTR_HT_0                 (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */\n#define RTC_TSTR_HT_1                 (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */\n#define RTC_TSTR_HU_Pos               (16U)\n#define RTC_TSTR_HU_Msk               (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */\n#define RTC_TSTR_HU                   RTC_TSTR_HU_Msk\n#define RTC_TSTR_HU_0                 (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */\n#define RTC_TSTR_HU_1                 (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */\n#define RTC_TSTR_HU_2                 (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */\n#define RTC_TSTR_HU_3                 (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */\n#define RTC_TSTR_MNT_Pos              (12U)\n#define RTC_TSTR_MNT_Msk              (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */\n#define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk\n#define RTC_TSTR_MNT_0                (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */\n#define RTC_TSTR_MNT_1                (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */\n#define RTC_TSTR_MNT_2                (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */\n#define RTC_TSTR_MNU_Pos              (8U)\n#define RTC_TSTR_MNU_Msk              (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */\n#define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk\n#define RTC_TSTR_MNU_0                (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */\n#define RTC_TSTR_MNU_1                (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */\n#define RTC_TSTR_MNU_2                (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */\n#define RTC_TSTR_MNU_3                (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */\n#define RTC_TSTR_ST_Pos               (4U)\n#define RTC_TSTR_ST_Msk               (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */\n#define RTC_TSTR_ST                   RTC_TSTR_ST_Msk\n#define RTC_TSTR_ST_0                 (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */\n#define RTC_TSTR_ST_1                 (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */\n#define RTC_TSTR_ST_2                 (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */\n#define RTC_TSTR_SU_Pos               (0U)\n#define RTC_TSTR_SU_Msk               (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */\n#define RTC_TSTR_SU                   RTC_TSTR_SU_Msk\n#define RTC_TSTR_SU_0                 (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */\n#define RTC_TSTR_SU_1                 (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */\n#define RTC_TSTR_SU_2                 (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */\n#define RTC_TSTR_SU_3                 (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSDR register  *****************/\n#define RTC_TSDR_WDU_Pos              (13U)\n#define RTC_TSDR_WDU_Msk              (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */\n#define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk\n#define RTC_TSDR_WDU_0                (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */\n#define RTC_TSDR_WDU_1                (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */\n#define RTC_TSDR_WDU_2                (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */\n#define RTC_TSDR_MT_Pos               (12U)\n#define RTC_TSDR_MT_Msk               (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */\n#define RTC_TSDR_MT                   RTC_TSDR_MT_Msk\n#define RTC_TSDR_MU_Pos               (8U)\n#define RTC_TSDR_MU_Msk               (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */\n#define RTC_TSDR_MU                   RTC_TSDR_MU_Msk\n#define RTC_TSDR_MU_0                 (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */\n#define RTC_TSDR_MU_1                 (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */\n#define RTC_TSDR_MU_2                 (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */\n#define RTC_TSDR_MU_3                 (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */\n#define RTC_TSDR_DT_Pos               (4U)\n#define RTC_TSDR_DT_Msk               (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */\n#define RTC_TSDR_DT                   RTC_TSDR_DT_Msk\n#define RTC_TSDR_DT_0                 (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */\n#define RTC_TSDR_DT_1                 (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */\n#define RTC_TSDR_DU_Pos               (0U)\n#define RTC_TSDR_DU_Msk               (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */\n#define RTC_TSDR_DU                   RTC_TSDR_DU_Msk\n#define RTC_TSDR_DU_0                 (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */\n#define RTC_TSDR_DU_1                 (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */\n#define RTC_TSDR_DU_2                 (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */\n#define RTC_TSDR_DU_3                 (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSSSR register  ****************/\n#define RTC_TSSSR_SS_Pos              (0U)\n#define RTC_TSSSR_SS_Msk              (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */\n#define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk\n\n/********************  Bits definition for RTC_CAL register  *****************/\n#define RTC_CALR_CALP_Pos             (15U)\n#define RTC_CALR_CALP_Msk             (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */\n#define RTC_CALR_CALP                 RTC_CALR_CALP_Msk\n#define RTC_CALR_CALW8_Pos            (14U)\n#define RTC_CALR_CALW8_Msk            (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */\n#define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk\n#define RTC_CALR_CALW16_Pos           (13U)\n#define RTC_CALR_CALW16_Msk           (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */\n#define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk\n#define RTC_CALR_CALM_Pos             (0U)\n#define RTC_CALR_CALM_Msk             (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */\n#define RTC_CALR_CALM                 RTC_CALR_CALM_Msk\n#define RTC_CALR_CALM_0               (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */\n#define RTC_CALR_CALM_1               (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */\n#define RTC_CALR_CALM_2               (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */\n#define RTC_CALR_CALM_3               (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */\n#define RTC_CALR_CALM_4               (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */\n#define RTC_CALR_CALM_5               (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */\n#define RTC_CALR_CALM_6               (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */\n#define RTC_CALR_CALM_7               (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */\n#define RTC_CALR_CALM_8               (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */\n\n/********************  Bits definition for RTC_TAFCR register  ****************/\n#define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)\n#define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */\n#define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk\n#define RTC_TAFCR_TSINSEL_Pos         (17U)\n#define RTC_TAFCR_TSINSEL_Msk         (0x1UL << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */\n#define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk\n#define RTC_TAFCR_TAMP1INSEL_Pos      (16U)\n#define RTC_TAFCR_TAMP1INSEL_Msk      (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)        /*!< 0x00010000 */\n#define RTC_TAFCR_TAMP1INSEL          RTC_TAFCR_TAMP1INSEL_Msk\n#define RTC_TAFCR_TAMPPUDIS_Pos       (15U)\n#define RTC_TAFCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */\n#define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk\n#define RTC_TAFCR_TAMPPRCH_Pos        (13U)\n#define RTC_TAFCR_TAMPPRCH_Msk        (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */\n#define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk\n#define RTC_TAFCR_TAMPPRCH_0          (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */\n#define RTC_TAFCR_TAMPPRCH_1          (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */\n#define RTC_TAFCR_TAMPFLT_Pos         (11U)\n#define RTC_TAFCR_TAMPFLT_Msk         (0x3UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */\n#define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk\n#define RTC_TAFCR_TAMPFLT_0           (0x1UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */\n#define RTC_TAFCR_TAMPFLT_1           (0x2UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */\n#define RTC_TAFCR_TAMPFREQ_Pos        (8U)\n#define RTC_TAFCR_TAMPFREQ_Msk        (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */\n#define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk\n#define RTC_TAFCR_TAMPFREQ_0          (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */\n#define RTC_TAFCR_TAMPFREQ_1          (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */\n#define RTC_TAFCR_TAMPFREQ_2          (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */\n#define RTC_TAFCR_TAMPTS_Pos          (7U)\n#define RTC_TAFCR_TAMPTS_Msk          (0x1UL << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */\n#define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk\n#define RTC_TAFCR_TAMP2TRG_Pos        (4U)\n#define RTC_TAFCR_TAMP2TRG_Msk        (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */\n#define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk\n#define RTC_TAFCR_TAMP2E_Pos          (3U)\n#define RTC_TAFCR_TAMP2E_Msk          (0x1UL << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */\n#define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk\n#define RTC_TAFCR_TAMPIE_Pos          (2U)\n#define RTC_TAFCR_TAMPIE_Msk          (0x1UL << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */\n#define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk\n#define RTC_TAFCR_TAMP1TRG_Pos        (1U)\n#define RTC_TAFCR_TAMP1TRG_Msk        (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */\n#define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk\n#define RTC_TAFCR_TAMP1E_Pos          (0U)\n#define RTC_TAFCR_TAMP1E_Msk          (0x1UL << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */\n#define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk\n\n/* Legacy defines */\n#define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMP1INSEL\n\n/********************  Bits definition for RTC_ALRMASSR register  *************/\n#define RTC_ALRMASSR_MASKSS_Pos       (24U)\n#define RTC_ALRMASSR_MASKSS_Msk       (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk\n#define RTC_ALRMASSR_MASKSS_0         (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMASSR_MASKSS_1         (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMASSR_MASKSS_2         (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMASSR_MASKSS_3         (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMASSR_SS_Pos           (0U)\n#define RTC_ALRMASSR_SS_Msk           (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk\n\n/********************  Bits definition for RTC_ALRMBSSR register  *************/\n#define RTC_ALRMBSSR_MASKSS_Pos       (24U)\n#define RTC_ALRMBSSR_MASKSS_Msk       (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk\n#define RTC_ALRMBSSR_MASKSS_0         (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMBSSR_MASKSS_1         (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMBSSR_MASKSS_2         (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMBSSR_MASKSS_3         (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMBSSR_SS_Pos           (0U)\n#define RTC_ALRMBSSR_SS_Msk           (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk\n\n/********************  Bits definition for RTC_BKP0R register  ****************/\n#define RTC_BKP0R_Pos                 (0U)\n#define RTC_BKP0R_Msk                 (0xFFFFFFFFUL << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP0R                     RTC_BKP0R_Msk\n\n/********************  Bits definition for RTC_BKP1R register  ****************/\n#define RTC_BKP1R_Pos                 (0U)\n#define RTC_BKP1R_Msk                 (0xFFFFFFFFUL << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP1R                     RTC_BKP1R_Msk\n\n/********************  Bits definition for RTC_BKP2R register  ****************/\n#define RTC_BKP2R_Pos                 (0U)\n#define RTC_BKP2R_Msk                 (0xFFFFFFFFUL << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP2R                     RTC_BKP2R_Msk\n\n/********************  Bits definition for RTC_BKP3R register  ****************/\n#define RTC_BKP3R_Pos                 (0U)\n#define RTC_BKP3R_Msk                 (0xFFFFFFFFUL << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP3R                     RTC_BKP3R_Msk\n\n/********************  Bits definition for RTC_BKP4R register  ****************/\n#define RTC_BKP4R_Pos                 (0U)\n#define RTC_BKP4R_Msk                 (0xFFFFFFFFUL << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP4R                     RTC_BKP4R_Msk\n\n/********************  Bits definition for RTC_BKP5R register  ****************/\n#define RTC_BKP5R_Pos                 (0U)\n#define RTC_BKP5R_Msk                 (0xFFFFFFFFUL << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP5R                     RTC_BKP5R_Msk\n\n/********************  Bits definition for RTC_BKP6R register  ****************/\n#define RTC_BKP6R_Pos                 (0U)\n#define RTC_BKP6R_Msk                 (0xFFFFFFFFUL << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP6R                     RTC_BKP6R_Msk\n\n/********************  Bits definition for RTC_BKP7R register  ****************/\n#define RTC_BKP7R_Pos                 (0U)\n#define RTC_BKP7R_Msk                 (0xFFFFFFFFUL << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP7R                     RTC_BKP7R_Msk\n\n/********************  Bits definition for RTC_BKP8R register  ****************/\n#define RTC_BKP8R_Pos                 (0U)\n#define RTC_BKP8R_Msk                 (0xFFFFFFFFUL << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP8R                     RTC_BKP8R_Msk\n\n/********************  Bits definition for RTC_BKP9R register  ****************/\n#define RTC_BKP9R_Pos                 (0U)\n#define RTC_BKP9R_Msk                 (0xFFFFFFFFUL << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP9R                     RTC_BKP9R_Msk\n\n/********************  Bits definition for RTC_BKP10R register  ***************/\n#define RTC_BKP10R_Pos                (0U)\n#define RTC_BKP10R_Msk                (0xFFFFFFFFUL << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP10R                    RTC_BKP10R_Msk\n\n/********************  Bits definition for RTC_BKP11R register  ***************/\n#define RTC_BKP11R_Pos                (0U)\n#define RTC_BKP11R_Msk                (0xFFFFFFFFUL << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP11R                    RTC_BKP11R_Msk\n\n/********************  Bits definition for RTC_BKP12R register  ***************/\n#define RTC_BKP12R_Pos                (0U)\n#define RTC_BKP12R_Msk                (0xFFFFFFFFUL << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP12R                    RTC_BKP12R_Msk\n\n/********************  Bits definition for RTC_BKP13R register  ***************/\n#define RTC_BKP13R_Pos                (0U)\n#define RTC_BKP13R_Msk                (0xFFFFFFFFUL << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP13R                    RTC_BKP13R_Msk\n\n/********************  Bits definition for RTC_BKP14R register  ***************/\n#define RTC_BKP14R_Pos                (0U)\n#define RTC_BKP14R_Msk                (0xFFFFFFFFUL << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP14R                    RTC_BKP14R_Msk\n\n/********************  Bits definition for RTC_BKP15R register  ***************/\n#define RTC_BKP15R_Pos                (0U)\n#define RTC_BKP15R_Msk                (0xFFFFFFFFUL << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP15R                    RTC_BKP15R_Msk\n\n/********************  Bits definition for RTC_BKP16R register  ***************/\n#define RTC_BKP16R_Pos                (0U)\n#define RTC_BKP16R_Msk                (0xFFFFFFFFUL << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP16R                    RTC_BKP16R_Msk\n\n/********************  Bits definition for RTC_BKP17R register  ***************/\n#define RTC_BKP17R_Pos                (0U)\n#define RTC_BKP17R_Msk                (0xFFFFFFFFUL << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP17R                    RTC_BKP17R_Msk\n\n/********************  Bits definition for RTC_BKP18R register  ***************/\n#define RTC_BKP18R_Pos                (0U)\n#define RTC_BKP18R_Msk                (0xFFFFFFFFUL << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP18R                    RTC_BKP18R_Msk\n\n/********************  Bits definition for RTC_BKP19R register  ***************/\n#define RTC_BKP19R_Pos                (0U)\n#define RTC_BKP19R_Msk                (0xFFFFFFFFUL << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP19R                    RTC_BKP19R_Msk\n\n/******************** Number of backup registers ******************************/\n#define RTC_BKP_NUMBER                       0x000000014U\n\n/******************************************************************************/\n/*                                                                            */\n/*                          Serial Audio Interface                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for SAI_GCR register  *******************/\n#define SAI_GCR_SYNCIN_Pos         (0U)\n#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */\n#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */\n#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */\n#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */\n\n#define SAI_GCR_SYNCOUT_Pos        (4U)\n#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */\n#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\n#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */\n#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */\n\n/*******************  Bit definition for SAI_xCR1 register  *******************/\n#define SAI_xCR1_MODE_Pos          (0U)\n#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */\n#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */\n#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */\n#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */\n\n#define SAI_xCR1_PRTCFG_Pos        (2U)\n#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */\n#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */\n#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */\n#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */\n\n#define SAI_xCR1_DS_Pos            (5U)\n#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */\n#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */\n#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */\n#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */\n#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */\n\n#define SAI_xCR1_LSBFIRST_Pos      (8U)\n#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */\n#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */\n#define SAI_xCR1_CKSTR_Pos         (9U)\n#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */\n#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */\n\n#define SAI_xCR1_SYNCEN_Pos        (10U)\n#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */\n#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */\n#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */\n#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */\n\n#define SAI_xCR1_MONO_Pos          (12U)\n#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */\n#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */\n#define SAI_xCR1_OUTDRIV_Pos       (13U)\n#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */\n#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */\n#define SAI_xCR1_SAIEN_Pos         (16U)\n#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */\n#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */\n#define SAI_xCR1_DMAEN_Pos         (17U)\n#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */\n#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */\n#define SAI_xCR1_NODIV_Pos         (19U)\n#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */\n#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */\n\n#define SAI_xCR1_MCKDIV_Pos        (20U)\n#define SAI_xCR1_MCKDIV_Msk        (0xFUL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */\n#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */\n#define SAI_xCR1_MCKDIV_0          (0x1UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00100000 */\n#define SAI_xCR1_MCKDIV_1          (0x2UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00200000 */\n#define SAI_xCR1_MCKDIV_2          (0x4UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00400000 */\n#define SAI_xCR1_MCKDIV_3          (0x8UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00800000 */\n\n/*******************  Bit definition for SAI_xCR2 register  *******************/\n#define SAI_xCR2_FTH_Pos           (0U)\n#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */\n#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */\n#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */\n#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */\n#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */\n\n#define SAI_xCR2_FFLUSH_Pos        (3U)\n#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */\n#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */\n#define SAI_xCR2_TRIS_Pos          (4U)\n#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */\n#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */\n#define SAI_xCR2_MUTE_Pos          (5U)\n#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */\n#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */\n#define SAI_xCR2_MUTEVAL_Pos       (6U)\n#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */\n#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */\n\n#define SAI_xCR2_MUTECNT_Pos       (7U)\n#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */\n#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */\n#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */\n#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */\n#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */\n#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */\n#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */\n#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */\n\n#define SAI_xCR2_CPL_Pos           (13U)\n#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */\n#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */\n\n#define SAI_xCR2_COMP_Pos          (14U)\n#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */\n#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */\n#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */\n#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */\n\n/******************  Bit definition for SAI_xFRCR register  *******************/\n#define SAI_xFRCR_FRL_Pos          (0U)\n#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */\n#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */\n#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */\n#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */\n#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */\n#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */\n#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */\n#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */\n#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */\n#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */\n\n#define SAI_xFRCR_FSALL_Pos        (8U)\n#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */\n#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */\n#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */\n#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */\n#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */\n#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */\n#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */\n#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */\n#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */\n\n#define SAI_xFRCR_FSDEF_Pos        (16U)\n#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */\n#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */\n#define SAI_xFRCR_FSPOL_Pos        (17U)\n#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */\n#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */\n#define SAI_xFRCR_FSOFF_Pos        (18U)\n#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */\n#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */\n/* Legacy defines */\n#define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL\n\n/******************  Bit definition for SAI_xSLOTR register  *******************/\n#define SAI_xSLOTR_FBOFF_Pos       (0U)\n#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */\n#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */\n#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */\n#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */\n#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */\n#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */\n#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */\n\n#define SAI_xSLOTR_SLOTSZ_Pos      (6U)\n#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */\n#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */\n#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */\n#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */\n\n#define SAI_xSLOTR_NBSLOT_Pos      (8U)\n#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */\n#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */\n#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */\n#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */\n#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */\n#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */\n\n#define SAI_xSLOTR_SLOTEN_Pos      (16U)\n#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */\n#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */\n\n/*******************  Bit definition for SAI_xIMR register  *******************/\n#define SAI_xIMR_OVRUDRIE_Pos      (0U)\n#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */\n#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */\n#define SAI_xIMR_MUTEDETIE_Pos     (1U)\n#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */\n#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */\n#define SAI_xIMR_WCKCFGIE_Pos      (2U)\n#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */\n#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */\n#define SAI_xIMR_FREQIE_Pos        (3U)\n#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */\n#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */\n#define SAI_xIMR_CNRDYIE_Pos       (4U)\n#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */\n#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */\n#define SAI_xIMR_AFSDETIE_Pos      (5U)\n#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */\n#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */\n#define SAI_xIMR_LFSDETIE_Pos      (6U)\n#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */\n#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */\n\n/********************  Bit definition for SAI_xSR register  *******************/\n#define SAI_xSR_OVRUDR_Pos         (0U)\n#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */\n#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */\n#define SAI_xSR_MUTEDET_Pos        (1U)\n#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */\n#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */\n#define SAI_xSR_WCKCFG_Pos         (2U)\n#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */\n#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */\n#define SAI_xSR_FREQ_Pos           (3U)\n#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */\n#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */\n#define SAI_xSR_CNRDY_Pos          (4U)\n#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */\n#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */\n#define SAI_xSR_AFSDET_Pos         (5U)\n#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */\n#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */\n#define SAI_xSR_LFSDET_Pos         (6U)\n#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */\n#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */\n\n#define SAI_xSR_FLVL_Pos           (16U)\n#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */\n#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */\n#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */\n#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */\n#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */\n\n/******************  Bit definition for SAI_xCLRFR register  ******************/\n#define SAI_xCLRFR_COVRUDR_Pos     (0U)\n#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */\n#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */\n#define SAI_xCLRFR_CMUTEDET_Pos    (1U)\n#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */\n#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */\n#define SAI_xCLRFR_CWCKCFG_Pos     (2U)\n#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */\n#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */\n#define SAI_xCLRFR_CFREQ_Pos       (3U)\n#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */\n#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */\n#define SAI_xCLRFR_CCNRDY_Pos      (4U)\n#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */\n#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */\n#define SAI_xCLRFR_CAFSDET_Pos     (5U)\n#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */\n#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */\n#define SAI_xCLRFR_CLFSDET_Pos     (6U)\n#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */\n#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */\n\n/******************  Bit definition for SAI_xDR register  ******************/\n#define SAI_xDR_DATA_Pos           (0U)\n#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */\n#define SAI_xDR_DATA               SAI_xDR_DATA_Msk\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                          SD host Interface                                 */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SDIO_POWER register  ******************/\n#define SDIO_POWER_PWRCTRL_Pos         (0U)\n#define SDIO_POWER_PWRCTRL_Msk         (0x3UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */\n#define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */\n#define SDIO_POWER_PWRCTRL_0           (0x1UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x01 */\n#define SDIO_POWER_PWRCTRL_1           (0x2UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x02 */\n\n/******************  Bit definition for SDIO_CLKCR register  ******************/\n#define SDIO_CLKCR_CLKDIV_Pos          (0U)\n#define SDIO_CLKCR_CLKDIV_Msk          (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */\n#define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor             */\n#define SDIO_CLKCR_CLKEN_Pos           (8U)\n#define SDIO_CLKCR_CLKEN_Msk           (0x1UL << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */\n#define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit                */\n#define SDIO_CLKCR_PWRSAV_Pos          (9U)\n#define SDIO_CLKCR_PWRSAV_Msk          (0x1UL << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */\n#define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit  */\n#define SDIO_CLKCR_BYPASS_Pos          (10U)\n#define SDIO_CLKCR_BYPASS_Msk          (0x1UL << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */\n#define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */\n\n#define SDIO_CLKCR_WIDBUS_Pos          (11U)\n#define SDIO_CLKCR_WIDBUS_Msk          (0x3UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */\n#define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\n#define SDIO_CLKCR_WIDBUS_0            (0x1UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x0800 */\n#define SDIO_CLKCR_WIDBUS_1            (0x2UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x1000 */\n\n#define SDIO_CLKCR_NEGEDGE_Pos         (13U)\n#define SDIO_CLKCR_NEGEDGE_Msk         (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */\n#define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */\n#define SDIO_CLKCR_HWFC_EN_Pos         (14U)\n#define SDIO_CLKCR_HWFC_EN_Msk         (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */\n#define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable          */\n\n/*******************  Bit definition for SDIO_ARG register  *******************/\n#define SDIO_ARG_CMDARG_Pos            (0U)\n#define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */\n#define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */\n\n/*******************  Bit definition for SDIO_CMD register  *******************/\n#define SDIO_CMD_CMDINDEX_Pos          (0U)\n#define SDIO_CMD_CMDINDEX_Msk          (0x3FUL << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */\n#define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index                               */\n\n#define SDIO_CMD_WAITRESP_Pos          (6U)\n#define SDIO_CMD_WAITRESP_Msk          (0x3UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */\n#define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */\n#define SDIO_CMD_WAITRESP_0            (0x1UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0040 */\n#define SDIO_CMD_WAITRESP_1            (0x2UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0080 */\n\n#define SDIO_CMD_WAITINT_Pos           (8U)\n#define SDIO_CMD_WAITINT_Msk           (0x1UL << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */\n#define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request                               */\n#define SDIO_CMD_WAITPEND_Pos          (9U)\n#define SDIO_CMD_WAITPEND_Msk          (0x1UL << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */\n#define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\n#define SDIO_CMD_CPSMEN_Pos            (10U)\n#define SDIO_CMD_CPSMEN_Msk            (0x1UL << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */\n#define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit                   */\n#define SDIO_CMD_SDIOSUSPEND_Pos       (11U)\n#define SDIO_CMD_SDIOSUSPEND_Msk       (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */\n#define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command                                         */\n\n/*****************  Bit definition for SDIO_RESPCMD register  *****************/\n#define SDIO_RESPCMD_RESPCMD_Pos       (0U)\n#define SDIO_RESPCMD_RESPCMD_Msk       (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */\n#define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */\n\n/******************  Bit definition for SDIO_RESP0 register  ******************/\n#define SDIO_RESP0_CARDSTATUS0_Pos     (0U)\n#define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP1 register  ******************/\n#define SDIO_RESP1_CARDSTATUS1_Pos     (0U)\n#define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP2 register  ******************/\n#define SDIO_RESP2_CARDSTATUS2_Pos     (0U)\n#define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP3 register  ******************/\n#define SDIO_RESP3_CARDSTATUS3_Pos     (0U)\n#define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP4 register  ******************/\n#define SDIO_RESP4_CARDSTATUS4_Pos     (0U)\n#define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_DTIMER register  *****************/\n#define SDIO_DTIMER_DATATIME_Pos       (0U)\n#define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */\n\n/******************  Bit definition for SDIO_DLEN register  *******************/\n#define SDIO_DLEN_DATALENGTH_Pos       (0U)\n#define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */\n\n/******************  Bit definition for SDIO_DCTRL register  ******************/\n#define SDIO_DCTRL_DTEN_Pos            (0U)\n#define SDIO_DCTRL_DTEN_Msk            (0x1UL << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */\n#define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit         */\n#define SDIO_DCTRL_DTDIR_Pos           (1U)\n#define SDIO_DCTRL_DTDIR_Msk           (0x1UL << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */\n#define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */\n#define SDIO_DCTRL_DTMODE_Pos          (2U)\n#define SDIO_DCTRL_DTMODE_Msk          (0x1UL << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */\n#define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection      */\n#define SDIO_DCTRL_DMAEN_Pos           (3U)\n#define SDIO_DCTRL_DMAEN_Msk           (0x1UL << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */\n#define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit                   */\n\n#define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)\n#define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */\n#define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */\n#define SDIO_DCTRL_DBLOCKSIZE_0        (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0010 */\n#define SDIO_DCTRL_DBLOCKSIZE_1        (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0020 */\n#define SDIO_DCTRL_DBLOCKSIZE_2        (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0040 */\n#define SDIO_DCTRL_DBLOCKSIZE_3        (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0080 */\n\n#define SDIO_DCTRL_RWSTART_Pos         (8U)\n#define SDIO_DCTRL_RWSTART_Msk         (0x1UL << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */\n#define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start         */\n#define SDIO_DCTRL_RWSTOP_Pos          (9U)\n#define SDIO_DCTRL_RWSTOP_Msk          (0x1UL << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */\n#define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop          */\n#define SDIO_DCTRL_RWMOD_Pos           (10U)\n#define SDIO_DCTRL_RWMOD_Msk           (0x1UL << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */\n#define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode          */\n#define SDIO_DCTRL_SDIOEN_Pos          (11U)\n#define SDIO_DCTRL_SDIOEN_Msk          (0x1UL << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */\n#define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */\n\n/******************  Bit definition for SDIO_DCOUNT register  *****************/\n#define SDIO_DCOUNT_DATACOUNT_Pos      (0U)\n#define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */\n\n/******************  Bit definition for SDIO_STA register  ********************/\n#define SDIO_STA_CCRCFAIL_Pos          (0U)\n#define SDIO_STA_CCRCFAIL_Msk          (0x1UL << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */\n#define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */\n#define SDIO_STA_DCRCFAIL_Pos          (1U)\n#define SDIO_STA_DCRCFAIL_Msk          (0x1UL << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */\n#define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */\n#define SDIO_STA_CTIMEOUT_Pos          (2U)\n#define SDIO_STA_CTIMEOUT_Msk          (0x1UL << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */\n#define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */\n#define SDIO_STA_DTIMEOUT_Pos          (3U)\n#define SDIO_STA_DTIMEOUT_Msk          (0x1UL << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */\n#define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */\n#define SDIO_STA_TXUNDERR_Pos          (4U)\n#define SDIO_STA_TXUNDERR_Msk          (0x1UL << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */\n#define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */\n#define SDIO_STA_RXOVERR_Pos           (5U)\n#define SDIO_STA_RXOVERR_Msk           (0x1UL << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */\n#define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */\n#define SDIO_STA_CMDREND_Pos           (6U)\n#define SDIO_STA_CMDREND_Msk           (0x1UL << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */\n#define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */\n#define SDIO_STA_CMDSENT_Pos           (7U)\n#define SDIO_STA_CMDSENT_Msk           (0x1UL << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */\n#define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */\n#define SDIO_STA_DATAEND_Pos           (8U)\n#define SDIO_STA_DATAEND_Msk           (0x1UL << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */\n#define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */\n#define SDIO_STA_DBCKEND_Pos           (10U)\n#define SDIO_STA_DBCKEND_Msk           (0x1UL << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */\n#define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */\n#define SDIO_STA_CMDACT_Pos            (11U)\n#define SDIO_STA_CMDACT_Msk            (0x1UL << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */\n#define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */\n#define SDIO_STA_TXACT_Pos             (12U)\n#define SDIO_STA_TXACT_Msk             (0x1UL << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */\n#define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */\n#define SDIO_STA_RXACT_Pos             (13U)\n#define SDIO_STA_RXACT_Msk             (0x1UL << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */\n#define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */\n#define SDIO_STA_TXFIFOHE_Pos          (14U)\n#define SDIO_STA_TXFIFOHE_Msk          (0x1UL << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */\n#define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\n#define SDIO_STA_RXFIFOHF_Pos          (15U)\n#define SDIO_STA_RXFIFOHF_Msk          (0x1UL << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */\n#define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\n#define SDIO_STA_TXFIFOF_Pos           (16U)\n#define SDIO_STA_TXFIFOF_Msk           (0x1UL << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */\n#define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */\n#define SDIO_STA_RXFIFOF_Pos           (17U)\n#define SDIO_STA_RXFIFOF_Msk           (0x1UL << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */\n#define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */\n#define SDIO_STA_TXFIFOE_Pos           (18U)\n#define SDIO_STA_TXFIFOE_Msk           (0x1UL << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */\n#define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */\n#define SDIO_STA_RXFIFOE_Pos           (19U)\n#define SDIO_STA_RXFIFOE_Msk           (0x1UL << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */\n#define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */\n#define SDIO_STA_TXDAVL_Pos            (20U)\n#define SDIO_STA_TXDAVL_Msk            (0x1UL << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */\n#define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */\n#define SDIO_STA_RXDAVL_Pos            (21U)\n#define SDIO_STA_RXDAVL_Msk            (0x1UL << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */\n#define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */\n#define SDIO_STA_SDIOIT_Pos            (22U)\n#define SDIO_STA_SDIOIT_Msk            (0x1UL << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */\n#define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */\n\n/*******************  Bit definition for SDIO_ICR register  *******************/\n#define SDIO_ICR_CCRCFAILC_Pos         (0U)\n#define SDIO_ICR_CCRCFAILC_Msk         (0x1UL << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */\n#define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */\n#define SDIO_ICR_DCRCFAILC_Pos         (1U)\n#define SDIO_ICR_DCRCFAILC_Msk         (0x1UL << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */\n#define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */\n#define SDIO_ICR_CTIMEOUTC_Pos         (2U)\n#define SDIO_ICR_CTIMEOUTC_Msk         (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */\n#define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */\n#define SDIO_ICR_DTIMEOUTC_Pos         (3U)\n#define SDIO_ICR_DTIMEOUTC_Msk         (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */\n#define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */\n#define SDIO_ICR_TXUNDERRC_Pos         (4U)\n#define SDIO_ICR_TXUNDERRC_Msk         (0x1UL << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */\n#define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */\n#define SDIO_ICR_RXOVERRC_Pos          (5U)\n#define SDIO_ICR_RXOVERRC_Msk          (0x1UL << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */\n#define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */\n#define SDIO_ICR_CMDRENDC_Pos          (6U)\n#define SDIO_ICR_CMDRENDC_Msk          (0x1UL << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */\n#define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */\n#define SDIO_ICR_CMDSENTC_Pos          (7U)\n#define SDIO_ICR_CMDSENTC_Msk          (0x1UL << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */\n#define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */\n#define SDIO_ICR_DATAENDC_Pos          (8U)\n#define SDIO_ICR_DATAENDC_Msk          (0x1UL << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */\n#define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */\n#define SDIO_ICR_DBCKENDC_Pos          (10U)\n#define SDIO_ICR_DBCKENDC_Msk          (0x1UL << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */\n#define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */\n#define SDIO_ICR_SDIOITC_Pos           (22U)\n#define SDIO_ICR_SDIOITC_Msk           (0x1UL << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */\n#define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */\n\n/******************  Bit definition for SDIO_MASK register  *******************/\n#define SDIO_MASK_CCRCFAILIE_Pos       (0U)\n#define SDIO_MASK_CCRCFAILIE_Msk       (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */\n#define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */\n#define SDIO_MASK_DCRCFAILIE_Pos       (1U)\n#define SDIO_MASK_DCRCFAILIE_Msk       (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */\n#define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */\n#define SDIO_MASK_CTIMEOUTIE_Pos       (2U)\n#define SDIO_MASK_CTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */\n#define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */\n#define SDIO_MASK_DTIMEOUTIE_Pos       (3U)\n#define SDIO_MASK_DTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */\n#define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */\n#define SDIO_MASK_TXUNDERRIE_Pos       (4U)\n#define SDIO_MASK_TXUNDERRIE_Msk       (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */\n#define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */\n#define SDIO_MASK_RXOVERRIE_Pos        (5U)\n#define SDIO_MASK_RXOVERRIE_Msk        (0x1UL << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */\n#define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */\n#define SDIO_MASK_CMDRENDIE_Pos        (6U)\n#define SDIO_MASK_CMDRENDIE_Msk        (0x1UL << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */\n#define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */\n#define SDIO_MASK_CMDSENTIE_Pos        (7U)\n#define SDIO_MASK_CMDSENTIE_Msk        (0x1UL << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */\n#define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */\n#define SDIO_MASK_DATAENDIE_Pos        (8U)\n#define SDIO_MASK_DATAENDIE_Msk        (0x1UL << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */\n#define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */\n#define SDIO_MASK_DBCKENDIE_Pos        (10U)\n#define SDIO_MASK_DBCKENDIE_Msk        (0x1UL << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */\n#define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */\n#define SDIO_MASK_CMDACTIE_Pos         (11U)\n#define SDIO_MASK_CMDACTIE_Msk         (0x1UL << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */\n#define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */\n#define SDIO_MASK_TXACTIE_Pos          (12U)\n#define SDIO_MASK_TXACTIE_Msk          (0x1UL << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */\n#define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */\n#define SDIO_MASK_RXACTIE_Pos          (13U)\n#define SDIO_MASK_RXACTIE_Msk          (0x1UL << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */\n#define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */\n#define SDIO_MASK_TXFIFOHEIE_Pos       (14U)\n#define SDIO_MASK_TXFIFOHEIE_Msk       (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */\n#define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */\n#define SDIO_MASK_RXFIFOHFIE_Pos       (15U)\n#define SDIO_MASK_RXFIFOHFIE_Msk       (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */\n#define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */\n#define SDIO_MASK_TXFIFOFIE_Pos        (16U)\n#define SDIO_MASK_TXFIFOFIE_Msk        (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */\n#define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */\n#define SDIO_MASK_RXFIFOFIE_Pos        (17U)\n#define SDIO_MASK_RXFIFOFIE_Msk        (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */\n#define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */\n#define SDIO_MASK_TXFIFOEIE_Pos        (18U)\n#define SDIO_MASK_TXFIFOEIE_Msk        (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */\n#define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_RXFIFOEIE_Pos        (19U)\n#define SDIO_MASK_RXFIFOEIE_Msk        (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */\n#define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_TXDAVLIE_Pos         (20U)\n#define SDIO_MASK_TXDAVLIE_Msk         (0x1UL << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */\n#define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */\n#define SDIO_MASK_RXDAVLIE_Pos         (21U)\n#define SDIO_MASK_RXDAVLIE_Msk         (0x1UL << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */\n#define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */\n#define SDIO_MASK_SDIOITIE_Pos         (22U)\n#define SDIO_MASK_SDIOITIE_Msk         (0x1UL << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */\n#define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */\n\n/*****************  Bit definition for SDIO_FIFOCNT register  *****************/\n#define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)\n#define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */\n#define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */\n\n/******************  Bit definition for SDIO_FIFO register  *******************/\n#define SDIO_FIFO_FIFODATA_Pos         (0U)\n#define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Serial Peripheral Interface                         */\n/*                                                                            */\n/******************************************************************************/\n#define SPI_I2S_FULLDUPLEX_SUPPORT                                             /*!< I2S Full-Duplex support */\n#define I2S_APB1_APB2_FEATURE                                                  /*!< I2S IP's are splited between RCC APB1 and APB2 interfaces */\n\n/*******************  Bit definition for SPI_CR1 register  ********************/\n#define SPI_CR1_CPHA_Pos            (0U)\n#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */\n#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */\n#define SPI_CR1_CPOL_Pos            (1U)\n#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */\n#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */\n#define SPI_CR1_MSTR_Pos            (2U)\n#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */\n#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */\n\n#define SPI_CR1_BR_Pos              (3U)\n#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */\n#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */\n#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */\n#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */\n#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */\n\n#define SPI_CR1_SPE_Pos             (6U)\n#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */\n#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */\n#define SPI_CR1_LSBFIRST_Pos        (7U)\n#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */\n#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */\n#define SPI_CR1_SSI_Pos             (8U)\n#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */\n#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */\n#define SPI_CR1_SSM_Pos             (9U)\n#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */\n#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */\n#define SPI_CR1_RXONLY_Pos          (10U)\n#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */\n#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */\n#define SPI_CR1_DFF_Pos             (11U)\n#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */\n#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */\n#define SPI_CR1_CRCNEXT_Pos         (12U)\n#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */\n#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */\n#define SPI_CR1_CRCEN_Pos           (13U)\n#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */\n#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */\n#define SPI_CR1_BIDIOE_Pos          (14U)\n#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */\n#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */\n#define SPI_CR1_BIDIMODE_Pos        (15U)\n#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */\n#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */\n\n/*******************  Bit definition for SPI_CR2 register  ********************/\n#define SPI_CR2_RXDMAEN_Pos         (0U)\n#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */\n#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */\n#define SPI_CR2_TXDMAEN_Pos         (1U)\n#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */\n#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */\n#define SPI_CR2_SSOE_Pos            (2U)\n#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */\n#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */\n#define SPI_CR2_FRF_Pos             (4U)\n#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */\n#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */\n#define SPI_CR2_ERRIE_Pos           (5U)\n#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */\n#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */\n#define SPI_CR2_RXNEIE_Pos          (6U)\n#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */\n#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */\n#define SPI_CR2_TXEIE_Pos           (7U)\n#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */\n#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */\n\n/********************  Bit definition for SPI_SR register  ********************/\n#define SPI_SR_RXNE_Pos             (0U)\n#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */\n#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */\n#define SPI_SR_TXE_Pos              (1U)\n#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */\n#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */\n#define SPI_SR_CHSIDE_Pos           (2U)\n#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */\n#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */\n#define SPI_SR_UDR_Pos              (3U)\n#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */\n#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */\n#define SPI_SR_CRCERR_Pos           (4U)\n#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */\n#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */\n#define SPI_SR_MODF_Pos             (5U)\n#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */\n#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */\n#define SPI_SR_OVR_Pos              (6U)\n#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */\n#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */\n#define SPI_SR_BSY_Pos              (7U)\n#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */\n#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */\n#define SPI_SR_FRE_Pos              (8U)\n#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */\n#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */\n\n/********************  Bit definition for SPI_DR register  ********************/\n#define SPI_DR_DR_Pos               (0U)\n#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */\n#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */\n\n/*******************  Bit definition for SPI_CRCPR register  ******************/\n#define SPI_CRCPR_CRCPOLY_Pos       (0U)\n#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */\n#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */\n\n/******************  Bit definition for SPI_RXCRCR register  ******************/\n#define SPI_RXCRCR_RXCRC_Pos        (0U)\n#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */\n\n/******************  Bit definition for SPI_TXCRCR register  ******************/\n#define SPI_TXCRCR_TXCRC_Pos        (0U)\n#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */\n\n/******************  Bit definition for SPI_I2SCFGR register  *****************/\n#define SPI_I2SCFGR_CHLEN_Pos       (0U)\n#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */\n#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */\n\n#define SPI_I2SCFGR_DATLEN_Pos      (1U)\n#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */\n#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */\n#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */\n#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */\n\n#define SPI_I2SCFGR_CKPOL_Pos       (3U)\n#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */\n#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */\n\n#define SPI_I2SCFGR_I2SSTD_Pos      (4U)\n#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */\n#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */\n#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */\n#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */\n\n#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)\n#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */\n#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */\n\n#define SPI_I2SCFGR_I2SCFG_Pos      (8U)\n#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */\n#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */\n#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */\n#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */\n\n#define SPI_I2SCFGR_I2SE_Pos        (10U)\n#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */\n#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */\n#define SPI_I2SCFGR_I2SMOD_Pos      (11U)\n#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */\n#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */\n#define SPI_I2SCFGR_ASTRTEN_Pos     (12U)\n#define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)          /*!< 0x00001000 */\n#define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */\n\n/******************  Bit definition for SPI_I2SPR register  *******************/\n#define SPI_I2SPR_I2SDIV_Pos        (0U)\n#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */\n#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */\n#define SPI_I2SPR_ODD_Pos           (8U)\n#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */\n#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */\n#define SPI_I2SPR_MCKOE_Pos         (9U)\n#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */\n#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                 SYSCFG                                     */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SYSCFG_MEMRMP register  ***************/\n#define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)\n#define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */\n#define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */\n#define SYSCFG_MEMRMP_MEM_MODE_0             (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */\n#define SYSCFG_MEMRMP_MEM_MODE_1             (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */\n/******************  Bit definition for SYSCFG_PMC register  ******************/\n#define SYSCFG_PMC_ADC1DC2_Pos               (16U)\n#define SYSCFG_PMC_ADC1DC2_Msk               (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)  /*!< 0x00010000 */\n#define SYSCFG_PMC_ADC1DC2                   SYSCFG_PMC_ADC1DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */\n\n/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\n#define SYSCFG_EXTICR1_EXTI0_Pos             (0U)\n#define SYSCFG_EXTICR1_EXTI0_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */\n#define SYSCFG_EXTICR1_EXTI1_Pos             (4U)\n#define SYSCFG_EXTICR1_EXTI1_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */\n#define SYSCFG_EXTICR1_EXTI2_Pos             (8U)\n#define SYSCFG_EXTICR1_EXTI2_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */\n#define SYSCFG_EXTICR1_EXTI3_Pos             (12U)\n#define SYSCFG_EXTICR1_EXTI3_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */\n/**\n  * @brief   EXTI0 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PD              0x0003U                           /*!<PD[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PE              0x0004U                           /*!<PE[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PF              0x0005U                           /*!<PF[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PG              0x0006U                           /*!<PG[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */\n\n/**\n  * @brief   EXTI1 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PD              0x0030U                           /*!<PD[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PE              0x0040U                           /*!<PE[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PF              0x0050U                           /*!<PF[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PG              0x0060U                           /*!<PG[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */\n\n/**\n  * @brief   EXTI2 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PD              0x0300U                           /*!<PD[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PE              0x0400U                           /*!<PE[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PF              0x0500U                           /*!<PF[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PG              0x0600U                           /*!<PG[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */\n\n/**\n  * @brief   EXTI3 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PD              0x3000U                           /*!<PD[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PE              0x4000U                           /*!<PE[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PF              0x5000U                           /*!<PF[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PG              0x6000U                           /*!<PG[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\n#define SYSCFG_EXTICR2_EXTI4_Pos             (0U)\n#define SYSCFG_EXTICR2_EXTI4_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */\n#define SYSCFG_EXTICR2_EXTI5_Pos             (4U)\n#define SYSCFG_EXTICR2_EXTI5_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */\n#define SYSCFG_EXTICR2_EXTI6_Pos             (8U)\n#define SYSCFG_EXTICR2_EXTI6_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */\n#define SYSCFG_EXTICR2_EXTI7_Pos             (12U)\n#define SYSCFG_EXTICR2_EXTI7_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */\n\n/**\n  * @brief   EXTI4 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PD              0x0003U                           /*!<PD[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PE              0x0004U                           /*!<PE[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PF              0x0005U                           /*!<PF[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PG              0x0006U                           /*!<PG[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */\n\n/**\n  * @brief   EXTI5 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PD              0x0030U                           /*!<PD[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PE              0x0040U                           /*!<PE[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PF              0x0050U                           /*!<PF[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PG              0x0060U                           /*!<PG[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */\n\n/**\n  * @brief   EXTI6 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PD              0x0300U                           /*!<PD[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PE              0x0400U                           /*!<PE[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PF              0x0500U                           /*!<PF[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PG              0x0600U                           /*!<PG[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */\n\n/**\n  * @brief   EXTI7 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PD              0x3000U                           /*!<PD[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PE              0x4000U                           /*!<PE[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PF              0x5000U                           /*!<PF[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PG              0x6000U                           /*!<PG[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\n#define SYSCFG_EXTICR3_EXTI8_Pos             (0U)\n#define SYSCFG_EXTICR3_EXTI8_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */\n#define SYSCFG_EXTICR3_EXTI9_Pos             (4U)\n#define SYSCFG_EXTICR3_EXTI9_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */\n#define SYSCFG_EXTICR3_EXTI10_Pos            (8U)\n#define SYSCFG_EXTICR3_EXTI10_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */\n#define SYSCFG_EXTICR3_EXTI11_Pos            (12U)\n#define SYSCFG_EXTICR3_EXTI11_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */\n\n/**\n  * @brief   EXTI8 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PD              0x0003U                           /*!<PD[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PE              0x0004U                           /*!<PE[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PF              0x0005U                           /*!<PF[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PG              0x0006U                           /*!<PG[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */\n\n/**\n  * @brief   EXTI9 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PD              0x0030U                           /*!<PD[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PE              0x0040U                           /*!<PE[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PF              0x0050U                           /*!<PF[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PG              0x0060U                           /*!<PG[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */\n\n/**\n  * @brief   EXTI10 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PD             0x0300U                           /*!<PD[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PE             0x0400U                           /*!<PE[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PF             0x0500U                           /*!<PF[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PG             0x0600U                           /*!<PG[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */\n\n/**\n  * @brief   EXTI11 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PD             0x3000U                           /*!<PD[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PE             0x4000U                           /*!<PE[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PF             0x5000U                           /*!<PF[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PG             0x6000U                           /*!<PG[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\n#define SYSCFG_EXTICR4_EXTI12_Pos            (0U)\n#define SYSCFG_EXTICR4_EXTI12_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */\n#define SYSCFG_EXTICR4_EXTI13_Pos            (4U)\n#define SYSCFG_EXTICR4_EXTI13_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */\n#define SYSCFG_EXTICR4_EXTI14_Pos            (8U)\n#define SYSCFG_EXTICR4_EXTI14_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */\n#define SYSCFG_EXTICR4_EXTI15_Pos            (12U)\n#define SYSCFG_EXTICR4_EXTI15_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */\n\n/**\n  * @brief   EXTI12 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PD             0x0003U                           /*!<PD[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PE             0x0004U                           /*!<PE[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PF             0x0005U                           /*!<PF[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PG             0x0006U                           /*!<PG[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */\n\n/**\n  * @brief   EXTI13 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PD             0x0030U                           /*!<PD[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PE             0x0040U                           /*!<PE[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PF             0x0050U                           /*!<PF[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PG             0x0060U                           /*!<PG[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */\n\n/**\n  * @brief   EXTI14 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PD             0x0300U                           /*!<PD[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PE             0x0400U                           /*!<PE[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PF             0x0500U                           /*!<PF[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PG             0x0600U                           /*!<PG[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */\n\n/**\n  * @brief   EXTI15 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PD             0x3000U                           /*!<PD[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PE             0x4000U                           /*!<PE[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PF             0x5000U                           /*!<PF[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PG             0x6000U                           /*!<PG[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */\n\n/******************  Bit definition for SYSCFG_CMPCR register  ****************/\n#define SYSCFG_CMPCR_CMP_PD_Pos              (0U)\n#define SYSCFG_CMPCR_CMP_PD_Msk              (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */\n#define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */\n#define SYSCFG_CMPCR_READY_Pos               (8U)\n#define SYSCFG_CMPCR_READY_Msk               (0x1UL << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */\n#define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */\n/******************  Bit definition for SYSCFG_CFGR register  *****************/\n#define SYSCFG_CFGR_FMPI2C1_SCL_Pos          (0U)\n#define SYSCFG_CFGR_FMPI2C1_SCL_Msk          (0x1UL << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */\n#define SYSCFG_CFGR_FMPI2C1_SCL              SYSCFG_CFGR_FMPI2C1_SCL_Msk       /*!<FM+ drive capability for FMPI2C1_SCL pin */\n#define SYSCFG_CFGR_FMPI2C1_SDA_Pos          (1U)\n#define SYSCFG_CFGR_FMPI2C1_SDA_Msk          (0x1UL << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */\n#define SYSCFG_CFGR_FMPI2C1_SDA              SYSCFG_CFGR_FMPI2C1_SDA_Msk       /*!<FM+ drive capability for FMPI2C1_SDA pin */\n\n/******************  Bit definition for SYSCFG_CFGR2 register  *****************/\n#define SYSCFG_CFGR2_LOCKUP_LOCK_Pos         (0U)\n#define SYSCFG_CFGR2_LOCKUP_LOCK_Msk         (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */\n#define SYSCFG_CFGR2_LOCKUP_LOCK             SYSCFG_CFGR2_LOCKUP_LOCK_Msk      /*!<Core Lockup lock */\n#define SYSCFG_CFGR2_PVD_LOCK_Pos            (2U)\n#define SYSCFG_CFGR2_PVD_LOCK_Msk            (0x1UL << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */\n#define SYSCFG_CFGR2_PVD_LOCK                SYSCFG_CFGR2_PVD_LOCK_Msk         /*!<PVD Lock         */\n/******************  Bit definition for SYSCFG_MCHDLYCR register  *****************/\n#define SYSCFG_MCHDLYCR_BSCKSEL_Pos          (0U)\n#define SYSCFG_MCHDLYCR_BSCKSEL_Msk          (0x1UL << SYSCFG_MCHDLYCR_BSCKSEL_Pos) /*!< 0x00000001 */\n#define SYSCFG_MCHDLYCR_BSCKSEL              SYSCFG_MCHDLYCR_BSCKSEL_Msk       /*!<Bitstream clock source selection                     */\n#define SYSCFG_MCHDLYCR_MCHDLY1EN_Pos        (1U)\n#define SYSCFG_MCHDLYCR_MCHDLY1EN_Msk        (0x1UL << SYSCFG_MCHDLYCR_MCHDLY1EN_Pos) /*!< 0x00000002 */\n#define SYSCFG_MCHDLYCR_MCHDLY1EN            SYSCFG_MCHDLYCR_MCHDLY1EN_Msk     /*!<MCHDLY clock enable for DFSDM1                       */\n#define SYSCFG_MCHDLYCR_DFSDM1D0SEL_Pos      (2U)\n#define SYSCFG_MCHDLYCR_DFSDM1D0SEL_Msk      (0x1UL << SYSCFG_MCHDLYCR_DFSDM1D0SEL_Pos) /*!< 0x00000004 */\n#define SYSCFG_MCHDLYCR_DFSDM1D0SEL          SYSCFG_MCHDLYCR_DFSDM1D0SEL_Msk   /*!<Source selection for DatIn0 for DFSDM1               */\n#define SYSCFG_MCHDLYCR_DFSDM1D2SEL_Pos      (3U)\n#define SYSCFG_MCHDLYCR_DFSDM1D2SEL_Msk      (0x1UL << SYSCFG_MCHDLYCR_DFSDM1D2SEL_Pos) /*!< 0x00000008 */\n#define SYSCFG_MCHDLYCR_DFSDM1D2SEL          SYSCFG_MCHDLYCR_DFSDM1D2SEL_Msk   /*!<Source selection for DatIn2 for DFSDM1               */\n#define SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Pos    (4U)\n#define SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Msk    (0x1UL << SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Pos) /*!< 0x00000010 */\n#define SYSCFG_MCHDLYCR_DFSDM1CK02SEL        SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM4 OC2 */\n#define SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Pos    (5U)\n#define SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Msk    (0x1UL << SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Pos) /*!< 0x00000020 */\n#define SYSCFG_MCHDLYCR_DFSDM1CK13SEL        SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM4 OC1 */\n#define SYSCFG_MCHDLYCR_DFSDM1CFG_Pos        (6U)\n#define SYSCFG_MCHDLYCR_DFSDM1CFG_Msk        (0x1UL << SYSCFG_MCHDLYCR_DFSDM1CFG_Pos) /*!< 0x00000040 */\n#define SYSCFG_MCHDLYCR_DFSDM1CFG            SYSCFG_MCHDLYCR_DFSDM1CFG_Msk     /*!<Source selection for DFSDM1                          */\n#define SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Pos     (7U)\n#define SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Msk     (0x1UL << SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Pos) /*!< 0x00000080 */\n#define SYSCFG_MCHDLYCR_DFSDM1CKOSEL         SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Msk  /*!<Source selection for 1_CKOUT                         */\n#define SYSCFG_MCHDLYCR_MCHDLY2EN_Pos        (8U)\n#define SYSCFG_MCHDLYCR_MCHDLY2EN_Msk        (0x1UL << SYSCFG_MCHDLYCR_MCHDLY2EN_Pos) /*!< 0x00000100 */\n#define SYSCFG_MCHDLYCR_MCHDLY2EN            SYSCFG_MCHDLYCR_MCHDLY2EN_Msk     /*!<MCHDLY clock enable for DFSDM2                       */\n#define SYSCFG_MCHDLYCR_DFSDM2D0SEL_Pos      (9U)\n#define SYSCFG_MCHDLYCR_DFSDM2D0SEL_Msk      (0x1UL << SYSCFG_MCHDLYCR_DFSDM2D0SEL_Pos) /*!< 0x00000200 */\n#define SYSCFG_MCHDLYCR_DFSDM2D0SEL          SYSCFG_MCHDLYCR_DFSDM2D0SEL_Msk   /*!<Source selection for DatIn0 for DFSDM2               */\n#define SYSCFG_MCHDLYCR_DFSDM2D2SEL_Pos      (10U)\n#define SYSCFG_MCHDLYCR_DFSDM2D2SEL_Msk      (0x1UL << SYSCFG_MCHDLYCR_DFSDM2D2SEL_Pos) /*!< 0x00000400 */\n#define SYSCFG_MCHDLYCR_DFSDM2D2SEL          SYSCFG_MCHDLYCR_DFSDM2D2SEL_Msk   /*!<Source selection for DatIn2 for DFSDM2               */\n#define SYSCFG_MCHDLYCR_DFSDM2D4SEL_Pos      (11U)\n#define SYSCFG_MCHDLYCR_DFSDM2D4SEL_Msk      (0x1UL << SYSCFG_MCHDLYCR_DFSDM2D4SEL_Pos) /*!< 0x00000800 */\n#define SYSCFG_MCHDLYCR_DFSDM2D4SEL          SYSCFG_MCHDLYCR_DFSDM2D4SEL_Msk   /*!<Source selection for DatIn4 for DFSDM2               */\n#define SYSCFG_MCHDLYCR_DFSDM2D6SEL_Pos      (12U)\n#define SYSCFG_MCHDLYCR_DFSDM2D6SEL_Msk      (0x1UL << SYSCFG_MCHDLYCR_DFSDM2D6SEL_Pos) /*!< 0x00001000 */\n#define SYSCFG_MCHDLYCR_DFSDM2D6SEL          SYSCFG_MCHDLYCR_DFSDM2D6SEL_Msk   /*!<Source selection for DatIn6 for DFSDM2               */\n#define SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Pos    (13U)\n#define SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Msk    (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Pos) /*!< 0x00002000 */\n#define SYSCFG_MCHDLYCR_DFSDM2CK04SEL        SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC4 */\n#define SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Pos    (14U)\n#define SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Msk    (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Pos) /*!< 0x00004000 */\n#define SYSCFG_MCHDLYCR_DFSDM2CK15SEL        SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC3 */\n#define SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Pos    (15U)\n#define SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Msk    (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Pos) /*!< 0x00008000 */\n#define SYSCFG_MCHDLYCR_DFSDM2CK26SEL        SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Msk /*!Distribution of the bitstreamclock gated by TIM3 OC2  */\n#define SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Pos    (16U)\n#define SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Msk    (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Pos) /*!< 0x00010000 */\n#define SYSCFG_MCHDLYCR_DFSDM2CK37SEL        SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Msk /*!<Distribution of the bitstreamclock gated by TIM3 OC1 */\n#define SYSCFG_MCHDLYCR_DFSDM2CFG_Pos        (17U)\n#define SYSCFG_MCHDLYCR_DFSDM2CFG_Msk        (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CFG_Pos) /*!< 0x00020000 */\n#define SYSCFG_MCHDLYCR_DFSDM2CFG            SYSCFG_MCHDLYCR_DFSDM2CFG_Msk     /*!<Source selection for DFSDM2                          */\n#define SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Pos     (18U)\n#define SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Msk     (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Pos) /*!< 0x00040000 */\n#define SYSCFG_MCHDLYCR_DFSDM2CKOSEL         SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Msk  /*!<Source selection for 2_CKOUT                         */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    TIM                                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for TIM_CR1 register  ********************/\n#define TIM_CR1_CEN_Pos           (0U)\n#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */\n#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */\n#define TIM_CR1_UDIS_Pos          (1U)\n#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */\n#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */\n#define TIM_CR1_URS_Pos           (2U)\n#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */\n#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */\n#define TIM_CR1_OPM_Pos           (3U)\n#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */\n#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */\n#define TIM_CR1_DIR_Pos           (4U)\n#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */\n#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */\n\n#define TIM_CR1_CMS_Pos           (5U)\n#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */\n#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */\n#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR1_ARPE_Pos          (7U)\n#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */\n#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */\n\n#define TIM_CR1_CKD_Pos           (8U)\n#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */\n#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */\n#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */\n#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */\n\n/*******************  Bit definition for TIM_CR2 register  ********************/\n#define TIM_CR2_CCPC_Pos          (0U)\n#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */\n#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */\n#define TIM_CR2_CCUS_Pos          (2U)\n#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */\n#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */\n#define TIM_CR2_CCDS_Pos          (3U)\n#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */\n#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */\n\n#define TIM_CR2_MMS_Pos           (4U)\n#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */\n#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */\n#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */\n#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR2_TI1S_Pos          (7U)\n#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */\n#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */\n#define TIM_CR2_OIS1_Pos          (8U)\n#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */\n#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */\n#define TIM_CR2_OIS1N_Pos         (9U)\n#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */\n#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */\n#define TIM_CR2_OIS2_Pos          (10U)\n#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */\n#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */\n#define TIM_CR2_OIS2N_Pos         (11U)\n#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */\n#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */\n#define TIM_CR2_OIS3_Pos          (12U)\n#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */\n#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */\n#define TIM_CR2_OIS3N_Pos         (13U)\n#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */\n#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */\n#define TIM_CR2_OIS4_Pos          (14U)\n#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */\n#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */\n\n/*******************  Bit definition for TIM_SMCR register  *******************/\n#define TIM_SMCR_SMS_Pos          (0U)\n#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */\n#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */\n#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */\n#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */\n#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */\n\n#define TIM_SMCR_TS_Pos           (4U)\n#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */\n#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */\n#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */\n#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */\n#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */\n\n#define TIM_SMCR_MSM_Pos          (7U)\n#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */\n#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */\n\n#define TIM_SMCR_ETF_Pos          (8U)\n#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */\n#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */\n#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */\n#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */\n#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */\n#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */\n\n#define TIM_SMCR_ETPS_Pos         (12U)\n#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */\n#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */\n#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */\n#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */\n\n#define TIM_SMCR_ECE_Pos          (14U)\n#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */\n#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */\n#define TIM_SMCR_ETP_Pos          (15U)\n#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */\n#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */\n\n/*******************  Bit definition for TIM_DIER register  *******************/\n#define TIM_DIER_UIE_Pos          (0U)\n#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */\n#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */\n#define TIM_DIER_CC1IE_Pos        (1U)\n#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */\n#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */\n#define TIM_DIER_CC2IE_Pos        (2U)\n#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */\n#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */\n#define TIM_DIER_CC3IE_Pos        (3U)\n#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */\n#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */\n#define TIM_DIER_CC4IE_Pos        (4U)\n#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */\n#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */\n#define TIM_DIER_COMIE_Pos        (5U)\n#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */\n#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */\n#define TIM_DIER_TIE_Pos          (6U)\n#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */\n#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */\n#define TIM_DIER_BIE_Pos          (7U)\n#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */\n#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */\n#define TIM_DIER_UDE_Pos          (8U)\n#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */\n#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */\n#define TIM_DIER_CC1DE_Pos        (9U)\n#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */\n#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */\n#define TIM_DIER_CC2DE_Pos        (10U)\n#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */\n#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */\n#define TIM_DIER_CC3DE_Pos        (11U)\n#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */\n#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */\n#define TIM_DIER_CC4DE_Pos        (12U)\n#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */\n#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */\n#define TIM_DIER_COMDE_Pos        (13U)\n#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */\n#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */\n#define TIM_DIER_TDE_Pos          (14U)\n#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */\n#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */\n\n/********************  Bit definition for TIM_SR register  ********************/\n#define TIM_SR_UIF_Pos            (0U)\n#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */\n#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */\n#define TIM_SR_CC1IF_Pos          (1U)\n#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */\n#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */\n#define TIM_SR_CC2IF_Pos          (2U)\n#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */\n#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */\n#define TIM_SR_CC3IF_Pos          (3U)\n#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */\n#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */\n#define TIM_SR_CC4IF_Pos          (4U)\n#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */\n#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */\n#define TIM_SR_COMIF_Pos          (5U)\n#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */\n#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */\n#define TIM_SR_TIF_Pos            (6U)\n#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */\n#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */\n#define TIM_SR_BIF_Pos            (7U)\n#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */\n#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */\n#define TIM_SR_CC1OF_Pos          (9U)\n#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */\n#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */\n#define TIM_SR_CC2OF_Pos          (10U)\n#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */\n#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */\n#define TIM_SR_CC3OF_Pos          (11U)\n#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */\n#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */\n#define TIM_SR_CC4OF_Pos          (12U)\n#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */\n#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */\n\n/*******************  Bit definition for TIM_EGR register  ********************/\n#define TIM_EGR_UG_Pos            (0U)\n#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */\n#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */\n#define TIM_EGR_CC1G_Pos          (1U)\n#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */\n#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */\n#define TIM_EGR_CC2G_Pos          (2U)\n#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */\n#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */\n#define TIM_EGR_CC3G_Pos          (3U)\n#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */\n#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */\n#define TIM_EGR_CC4G_Pos          (4U)\n#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */\n#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */\n#define TIM_EGR_COMG_Pos          (5U)\n#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */\n#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */\n#define TIM_EGR_TG_Pos            (6U)\n#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */\n#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */\n#define TIM_EGR_BG_Pos            (7U)\n#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */\n#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */\n\n/******************  Bit definition for TIM_CCMR1 register  *******************/\n#define TIM_CCMR1_CC1S_Pos        (0U)\n#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\n#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR1_OC1FE_Pos       (2U)\n#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */\n#define TIM_CCMR1_OC1PE_Pos       (3U)\n#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */\n\n#define TIM_CCMR1_OC1M_Pos        (4U)\n#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */\n#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR1_OC1CE_Pos       (7U)\n#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */\n\n#define TIM_CCMR1_CC2S_Pos        (8U)\n#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\n#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR1_OC2FE_Pos       (10U)\n#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */\n#define TIM_CCMR1_OC2PE_Pos       (11U)\n#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */\n\n#define TIM_CCMR1_OC2M_Pos        (12U)\n#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */\n#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR1_OC2CE_Pos       (15U)\n#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR1_IC1PSC_Pos      (2U)\n#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\n#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR1_IC1F_Pos        (4U)\n#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */\n#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR1_IC2PSC_Pos      (10U)\n#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */\n#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR1_IC2F_Pos        (12U)\n#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */\n#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */\n\n/******************  Bit definition for TIM_CCMR2 register  *******************/\n#define TIM_CCMR2_CC3S_Pos        (0U)\n#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */\n#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR2_OC3FE_Pos       (2U)\n#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */\n#define TIM_CCMR2_OC3PE_Pos       (3U)\n#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */\n\n#define TIM_CCMR2_OC3M_Pos        (4U)\n#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\n#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR2_OC3CE_Pos       (7U)\n#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */\n\n#define TIM_CCMR2_CC4S_Pos        (8U)\n#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\n#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR2_OC4FE_Pos       (10U)\n#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */\n#define TIM_CCMR2_OC4PE_Pos       (11U)\n#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */\n\n#define TIM_CCMR2_OC4M_Pos        (12U)\n#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\n#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR2_OC4CE_Pos       (15U)\n#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR2_IC3PSC_Pos      (2U)\n#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\n#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR2_IC3F_Pos        (4U)\n#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\n#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR2_IC4PSC_Pos      (10U)\n#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\n#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR2_IC4F_Pos        (12U)\n#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\n#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */\n\n/*******************  Bit definition for TIM_CCER register  *******************/\n#define TIM_CCER_CC1E_Pos         (0U)\n#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */\n#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */\n#define TIM_CCER_CC1P_Pos         (1U)\n#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */\n#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */\n#define TIM_CCER_CC1NE_Pos        (2U)\n#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */\n#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */\n#define TIM_CCER_CC1NP_Pos        (3U)\n#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */\n#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */\n#define TIM_CCER_CC2E_Pos         (4U)\n#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */\n#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */\n#define TIM_CCER_CC2P_Pos         (5U)\n#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */\n#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */\n#define TIM_CCER_CC2NE_Pos        (6U)\n#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */\n#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */\n#define TIM_CCER_CC2NP_Pos        (7U)\n#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */\n#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */\n#define TIM_CCER_CC3E_Pos         (8U)\n#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */\n#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */\n#define TIM_CCER_CC3P_Pos         (9U)\n#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */\n#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */\n#define TIM_CCER_CC3NE_Pos        (10U)\n#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */\n#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */\n#define TIM_CCER_CC3NP_Pos        (11U)\n#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */\n#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */\n#define TIM_CCER_CC4E_Pos         (12U)\n#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */\n#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */\n#define TIM_CCER_CC4P_Pos         (13U)\n#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */\n#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */\n#define TIM_CCER_CC4NP_Pos        (15U)\n#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */\n#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */\n\n/*******************  Bit definition for TIM_CNT register  ********************/\n#define TIM_CNT_CNT_Pos           (0U)\n#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0xFFFFFFFF */\n#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                                  /*!<Counter Value            */\n\n/*******************  Bit definition for TIM_PSC register  ********************/\n#define TIM_PSC_PSC_Pos           (0U)\n#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */\n#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */\n\n/*******************  Bit definition for TIM_ARR register  ********************/\n#define TIM_ARR_ARR_Pos           (0U)\n#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */\n#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */\n\n/*******************  Bit definition for TIM_RCR register  ********************/\n#define TIM_RCR_REP_Pos           (0U)\n#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */\n#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */\n\n/*******************  Bit definition for TIM_CCR1 register  *******************/\n#define TIM_CCR1_CCR1_Pos         (0U)\n#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */\n\n/*******************  Bit definition for TIM_CCR2 register  *******************/\n#define TIM_CCR2_CCR2_Pos         (0U)\n#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */\n\n/*******************  Bit definition for TIM_CCR3 register  *******************/\n#define TIM_CCR3_CCR3_Pos         (0U)\n#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */\n\n/*******************  Bit definition for TIM_CCR4 register  *******************/\n#define TIM_CCR4_CCR4_Pos         (0U)\n#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */\n\n/*******************  Bit definition for TIM_BDTR register  *******************/\n#define TIM_BDTR_DTG_Pos          (0U)\n#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */\n#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\n#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */\n#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */\n#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */\n#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */\n#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */\n#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */\n#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */\n#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */\n\n#define TIM_BDTR_LOCK_Pos         (8U)\n#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */\n#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */\n#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */\n#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */\n\n#define TIM_BDTR_OSSI_Pos         (10U)\n#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */\n#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */\n#define TIM_BDTR_OSSR_Pos         (11U)\n#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */\n#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */\n#define TIM_BDTR_BKE_Pos          (12U)\n#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */\n#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */\n#define TIM_BDTR_BKP_Pos          (13U)\n#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */\n#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */\n#define TIM_BDTR_AOE_Pos          (14U)\n#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */\n#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */\n#define TIM_BDTR_MOE_Pos          (15U)\n#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */\n#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */\n\n/*******************  Bit definition for TIM_DCR register  ********************/\n#define TIM_DCR_DBA_Pos           (0U)\n#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */\n#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */\n#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */\n#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */\n#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */\n#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */\n#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */\n\n#define TIM_DCR_DBL_Pos           (8U)\n#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */\n#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */\n#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */\n#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */\n#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */\n#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */\n#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */\n\n/*******************  Bit definition for TIM_DMAR register  *******************/\n#define TIM_DMAR_DMAB_Pos         (0U)\n#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */\n#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */\n\n/*******************  Bit definition for TIM_OR register  *********************/\n#define TIM_OR_TI1_RMP_Pos        (0U)\n#define TIM_OR_TI1_RMP_Msk        (0x3UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000003 */\n#define TIM_OR_TI1_RMP            TIM_OR_TI1_RMP_Msk                           /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */\n#define TIM_OR_TI1_RMP_0          (0x1UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000001 */\n#define TIM_OR_TI1_RMP_1          (0x2UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000002 */\n\n#define TIM_OR_TI4_RMP_Pos        (6U)\n#define TIM_OR_TI4_RMP_Msk        (0x3UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */\n#define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */\n#define TIM_OR_TI4_RMP_0          (0x1UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */\n#define TIM_OR_TI4_RMP_1          (0x2UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */\n#define TIM_OR_ITR1_RMP_Pos       (10U)\n#define TIM_OR_ITR1_RMP_Msk       (0x3UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */\n#define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\n#define TIM_OR_ITR1_RMP_0         (0x1UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */\n#define TIM_OR_ITR1_RMP_1         (0x2UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Low Power Timer (LPTIM)                            */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for LPTIM_ISR register  *******************/\n#define LPTIM_ISR_CMPM_Pos            (0U)\n#define LPTIM_ISR_CMPM_Msk            (0x1UL << LPTIM_ISR_CMPM_Pos)             /*!< 0x00000001 */\n#define LPTIM_ISR_CMPM                LPTIM_ISR_CMPM_Msk                       /*!< Compare match                       */\n#define LPTIM_ISR_ARRM_Pos            (1U)\n#define LPTIM_ISR_ARRM_Msk            (0x1UL << LPTIM_ISR_ARRM_Pos)             /*!< 0x00000002 */\n#define LPTIM_ISR_ARRM                LPTIM_ISR_ARRM_Msk                       /*!< Autoreload match                    */\n#define LPTIM_ISR_EXTTRIG_Pos         (2U)\n#define LPTIM_ISR_EXTTRIG_Msk         (0x1UL << LPTIM_ISR_EXTTRIG_Pos)          /*!< 0x00000004 */\n#define LPTIM_ISR_EXTTRIG             LPTIM_ISR_EXTTRIG_Msk                    /*!< External trigger edge event         */\n#define LPTIM_ISR_CMPOK_Pos           (3U)\n#define LPTIM_ISR_CMPOK_Msk           (0x1UL << LPTIM_ISR_CMPOK_Pos)            /*!< 0x00000008 */\n#define LPTIM_ISR_CMPOK               LPTIM_ISR_CMPOK_Msk                      /*!< Compare register update OK          */\n#define LPTIM_ISR_ARROK_Pos           (4U)\n#define LPTIM_ISR_ARROK_Msk           (0x1UL << LPTIM_ISR_ARROK_Pos)            /*!< 0x00000010 */\n#define LPTIM_ISR_ARROK               LPTIM_ISR_ARROK_Msk                      /*!< Autoreload register update OK       */\n#define LPTIM_ISR_UP_Pos              (5U)\n#define LPTIM_ISR_UP_Msk              (0x1UL << LPTIM_ISR_UP_Pos)               /*!< 0x00000020 */\n#define LPTIM_ISR_UP                  LPTIM_ISR_UP_Msk                         /*!< Counter direction change down to up */\n#define LPTIM_ISR_DOWN_Pos            (6U)\n#define LPTIM_ISR_DOWN_Msk            (0x1UL << LPTIM_ISR_DOWN_Pos)             /*!< 0x00000040 */\n#define LPTIM_ISR_DOWN                LPTIM_ISR_DOWN_Msk                       /*!< Counter direction change up to down */\n\n/******************  Bit definition for LPTIM_ICR register  *******************/\n#define LPTIM_ICR_CMPMCF_Pos          (0U)\n#define LPTIM_ICR_CMPMCF_Msk          (0x1UL << LPTIM_ICR_CMPMCF_Pos)           /*!< 0x00000001 */\n#define LPTIM_ICR_CMPMCF              LPTIM_ICR_CMPMCF_Msk                     /*!< Compare match Clear Flag                       */\n#define LPTIM_ICR_ARRMCF_Pos          (1U)\n#define LPTIM_ICR_ARRMCF_Msk          (0x1UL << LPTIM_ICR_ARRMCF_Pos)           /*!< 0x00000002 */\n#define LPTIM_ICR_ARRMCF              LPTIM_ICR_ARRMCF_Msk                     /*!< Autoreload match Clear Flag                    */\n#define LPTIM_ICR_EXTTRIGCF_Pos       (2U)\n#define LPTIM_ICR_EXTTRIGCF_Msk       (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)        /*!< 0x00000004 */\n#define LPTIM_ICR_EXTTRIGCF           LPTIM_ICR_EXTTRIGCF_Msk                  /*!< External trigger edge event Clear Flag         */\n#define LPTIM_ICR_CMPOKCF_Pos         (3U)\n#define LPTIM_ICR_CMPOKCF_Msk         (0x1UL << LPTIM_ICR_CMPOKCF_Pos)          /*!< 0x00000008 */\n#define LPTIM_ICR_CMPOKCF             LPTIM_ICR_CMPOKCF_Msk                    /*!< Compare register update OK Clear Flag          */\n#define LPTIM_ICR_ARROKCF_Pos         (4U)\n#define LPTIM_ICR_ARROKCF_Msk         (0x1UL << LPTIM_ICR_ARROKCF_Pos)          /*!< 0x00000010 */\n#define LPTIM_ICR_ARROKCF             LPTIM_ICR_ARROKCF_Msk                    /*!< Autoreload register update OK Clear Flag       */\n#define LPTIM_ICR_UPCF_Pos            (5U)\n#define LPTIM_ICR_UPCF_Msk            (0x1UL << LPTIM_ICR_UPCF_Pos)             /*!< 0x00000020 */\n#define LPTIM_ICR_UPCF                LPTIM_ICR_UPCF_Msk                       /*!< Counter direction change down to up Clear Flag */\n#define LPTIM_ICR_DOWNCF_Pos          (6U)\n#define LPTIM_ICR_DOWNCF_Msk          (0x1UL << LPTIM_ICR_DOWNCF_Pos)           /*!< 0x00000040 */\n#define LPTIM_ICR_DOWNCF              LPTIM_ICR_DOWNCF_Msk                     /*!< Counter direction change up to down Clear Flag */\n\n/******************  Bit definition for LPTIM_IER register ********************/\n#define LPTIM_IER_CMPMIE_Pos          (0U)\n#define LPTIM_IER_CMPMIE_Msk          (0x1UL << LPTIM_IER_CMPMIE_Pos)           /*!< 0x00000001 */\n#define LPTIM_IER_CMPMIE              LPTIM_IER_CMPMIE_Msk                     /*!< Compare match Interrupt Enable                       */\n#define LPTIM_IER_ARRMIE_Pos          (1U)\n#define LPTIM_IER_ARRMIE_Msk          (0x1UL << LPTIM_IER_ARRMIE_Pos)           /*!< 0x00000002 */\n#define LPTIM_IER_ARRMIE              LPTIM_IER_ARRMIE_Msk                     /*!< Autoreload match Interrupt Enable                    */\n#define LPTIM_IER_EXTTRIGIE_Pos       (2U)\n#define LPTIM_IER_EXTTRIGIE_Msk       (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)        /*!< 0x00000004 */\n#define LPTIM_IER_EXTTRIGIE           LPTIM_IER_EXTTRIGIE_Msk                  /*!< External trigger edge event Interrupt Enable         */\n#define LPTIM_IER_CMPOKIE_Pos         (3U)\n#define LPTIM_IER_CMPOKIE_Msk         (0x1UL << LPTIM_IER_CMPOKIE_Pos)          /*!< 0x00000008 */\n#define LPTIM_IER_CMPOKIE             LPTIM_IER_CMPOKIE_Msk                    /*!< Compare register update OK Interrupt Enable          */\n#define LPTIM_IER_ARROKIE_Pos         (4U)\n#define LPTIM_IER_ARROKIE_Msk         (0x1UL << LPTIM_IER_ARROKIE_Pos)          /*!< 0x00000010 */\n#define LPTIM_IER_ARROKIE             LPTIM_IER_ARROKIE_Msk                    /*!< Autoreload register update OK Interrupt Enable       */\n#define LPTIM_IER_UPIE_Pos            (5U)\n#define LPTIM_IER_UPIE_Msk            (0x1UL << LPTIM_IER_UPIE_Pos)             /*!< 0x00000020 */\n#define LPTIM_IER_UPIE                LPTIM_IER_UPIE_Msk                       /*!< Counter direction change down to up Interrupt Enable */\n#define LPTIM_IER_DOWNIE_Pos          (6U)\n#define LPTIM_IER_DOWNIE_Msk          (0x1UL << LPTIM_IER_DOWNIE_Pos)           /*!< 0x00000040 */\n#define LPTIM_IER_DOWNIE              LPTIM_IER_DOWNIE_Msk                     /*!< Counter direction change up to down Interrupt Enable */\n\n/******************  Bit definition for LPTIM_CFGR register *******************/\n#define LPTIM_CFGR_CKSEL_Pos          (0U)\n#define LPTIM_CFGR_CKSEL_Msk          (0x1UL << LPTIM_CFGR_CKSEL_Pos)           /*!< 0x00000001 */\n#define LPTIM_CFGR_CKSEL              LPTIM_CFGR_CKSEL_Msk                     /*!< Clock selector */\n\n#define LPTIM_CFGR_CKPOL_Pos          (1U)\n#define LPTIM_CFGR_CKPOL_Msk          (0x3UL << LPTIM_CFGR_CKPOL_Pos)           /*!< 0x00000006 */\n#define LPTIM_CFGR_CKPOL              LPTIM_CFGR_CKPOL_Msk                     /*!< CKPOL[1:0] bits (Clock polarity) */\n#define LPTIM_CFGR_CKPOL_0            (0x1UL << LPTIM_CFGR_CKPOL_Pos)           /*!< 0x00000002 */\n#define LPTIM_CFGR_CKPOL_1            (0x2UL << LPTIM_CFGR_CKPOL_Pos)           /*!< 0x00000004 */\n\n#define LPTIM_CFGR_CKFLT_Pos          (3U)\n#define LPTIM_CFGR_CKFLT_Msk          (0x3UL << LPTIM_CFGR_CKFLT_Pos)           /*!< 0x00000018 */\n#define LPTIM_CFGR_CKFLT              LPTIM_CFGR_CKFLT_Msk                     /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */\n#define LPTIM_CFGR_CKFLT_0            (0x1UL << LPTIM_CFGR_CKFLT_Pos)           /*!< 0x00000008 */\n#define LPTIM_CFGR_CKFLT_1            (0x2UL << LPTIM_CFGR_CKFLT_Pos)           /*!< 0x00000010 */\n\n#define LPTIM_CFGR_TRGFLT_Pos         (6U)\n#define LPTIM_CFGR_TRGFLT_Msk         (0x3UL << LPTIM_CFGR_TRGFLT_Pos)          /*!< 0x000000C0 */\n#define LPTIM_CFGR_TRGFLT             LPTIM_CFGR_TRGFLT_Msk                    /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */\n#define LPTIM_CFGR_TRGFLT_0           (0x1UL << LPTIM_CFGR_TRGFLT_Pos)          /*!< 0x00000040 */\n#define LPTIM_CFGR_TRGFLT_1           (0x2UL << LPTIM_CFGR_TRGFLT_Pos)          /*!< 0x00000080 */\n\n#define LPTIM_CFGR_PRESC_Pos          (9U)\n#define LPTIM_CFGR_PRESC_Msk          (0x7UL << LPTIM_CFGR_PRESC_Pos)           /*!< 0x00000E00 */\n#define LPTIM_CFGR_PRESC              LPTIM_CFGR_PRESC_Msk                     /*!< PRESC[2:0] bits (Clock prescaler) */\n#define LPTIM_CFGR_PRESC_0            (0x1UL << LPTIM_CFGR_PRESC_Pos)           /*!< 0x00000200 */\n#define LPTIM_CFGR_PRESC_1            (0x2UL << LPTIM_CFGR_PRESC_Pos)           /*!< 0x00000400 */\n#define LPTIM_CFGR_PRESC_2            (0x4UL << LPTIM_CFGR_PRESC_Pos)           /*!< 0x00000800 */\n\n#define LPTIM_CFGR_TRIGSEL_Pos        (13U)\n#define LPTIM_CFGR_TRIGSEL_Msk        (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)         /*!< 0x0000E000 */\n#define LPTIM_CFGR_TRIGSEL            LPTIM_CFGR_TRIGSEL_Msk                   /*!< TRIGSEL[2:0]] bits (Trigger selector) */\n#define LPTIM_CFGR_TRIGSEL_0          (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)         /*!< 0x00002000 */\n#define LPTIM_CFGR_TRIGSEL_1          (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)         /*!< 0x00004000 */\n#define LPTIM_CFGR_TRIGSEL_2          (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)         /*!< 0x00008000 */\n\n#define LPTIM_CFGR_TRIGEN_Pos         (17U)\n#define LPTIM_CFGR_TRIGEN_Msk         (0x3UL << LPTIM_CFGR_TRIGEN_Pos)          /*!< 0x00060000 */\n#define LPTIM_CFGR_TRIGEN             LPTIM_CFGR_TRIGEN_Msk                    /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */\n#define LPTIM_CFGR_TRIGEN_0           (0x1UL << LPTIM_CFGR_TRIGEN_Pos)          /*!< 0x00020000 */\n#define LPTIM_CFGR_TRIGEN_1           (0x2UL << LPTIM_CFGR_TRIGEN_Pos)          /*!< 0x00040000 */\n\n#define LPTIM_CFGR_TIMOUT_Pos         (19U)\n#define LPTIM_CFGR_TIMOUT_Msk         (0x1UL << LPTIM_CFGR_TIMOUT_Pos)          /*!< 0x00080000 */\n#define LPTIM_CFGR_TIMOUT             LPTIM_CFGR_TIMOUT_Msk                    /*!< Timout enable           */\n#define LPTIM_CFGR_WAVE_Pos           (20U)\n#define LPTIM_CFGR_WAVE_Msk           (0x1UL << LPTIM_CFGR_WAVE_Pos)            /*!< 0x00100000 */\n#define LPTIM_CFGR_WAVE               LPTIM_CFGR_WAVE_Msk                      /*!< Waveform shape          */\n#define LPTIM_CFGR_WAVPOL_Pos         (21U)\n#define LPTIM_CFGR_WAVPOL_Msk         (0x1UL << LPTIM_CFGR_WAVPOL_Pos)          /*!< 0x00200000 */\n#define LPTIM_CFGR_WAVPOL             LPTIM_CFGR_WAVPOL_Msk                    /*!< Waveform shape polarity */\n#define LPTIM_CFGR_PRELOAD_Pos        (22U)\n#define LPTIM_CFGR_PRELOAD_Msk        (0x1UL << LPTIM_CFGR_PRELOAD_Pos)         /*!< 0x00400000 */\n#define LPTIM_CFGR_PRELOAD            LPTIM_CFGR_PRELOAD_Msk                   /*!< Reg update mode         */\n#define LPTIM_CFGR_COUNTMODE_Pos      (23U)\n#define LPTIM_CFGR_COUNTMODE_Msk      (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)       /*!< 0x00800000 */\n#define LPTIM_CFGR_COUNTMODE          LPTIM_CFGR_COUNTMODE_Msk                 /*!< Counter mode enable     */\n#define LPTIM_CFGR_ENC_Pos            (24U)\n#define LPTIM_CFGR_ENC_Msk            (0x1UL << LPTIM_CFGR_ENC_Pos)             /*!< 0x01000000 */\n#define LPTIM_CFGR_ENC                LPTIM_CFGR_ENC_Msk                       /*!< Encoder mode enable     */\n\n/******************  Bit definition for LPTIM_CR register  ********************/\n#define LPTIM_CR_ENABLE_Pos           (0U)\n#define LPTIM_CR_ENABLE_Msk           (0x1UL << LPTIM_CR_ENABLE_Pos)            /*!< 0x00000001 */\n#define LPTIM_CR_ENABLE               LPTIM_CR_ENABLE_Msk                      /*!< LPTIMer enable                 */\n#define LPTIM_CR_SNGSTRT_Pos          (1U)\n#define LPTIM_CR_SNGSTRT_Msk          (0x1UL << LPTIM_CR_SNGSTRT_Pos)           /*!< 0x00000002 */\n#define LPTIM_CR_SNGSTRT              LPTIM_CR_SNGSTRT_Msk                     /*!< Timer start in single mode     */\n#define LPTIM_CR_CNTSTRT_Pos          (2U)\n#define LPTIM_CR_CNTSTRT_Msk          (0x1UL << LPTIM_CR_CNTSTRT_Pos)           /*!< 0x00000004 */\n#define LPTIM_CR_CNTSTRT              LPTIM_CR_CNTSTRT_Msk                     /*!< Timer start in continuous mode */\n\n/******************  Bit definition for LPTIM_CMP register  *******************/\n#define LPTIM_CMP_CMP_Pos             (0U)\n#define LPTIM_CMP_CMP_Msk             (0xFFFFUL << LPTIM_CMP_CMP_Pos)           /*!< 0x0000FFFF */\n#define LPTIM_CMP_CMP                 LPTIM_CMP_CMP_Msk                        /*!< Compare register     */\n\n/******************  Bit definition for LPTIM_ARR register  *******************/\n#define LPTIM_ARR_ARR_Pos             (0U)\n#define LPTIM_ARR_ARR_Msk             (0xFFFFUL << LPTIM_ARR_ARR_Pos)           /*!< 0x0000FFFF */\n#define LPTIM_ARR_ARR                 LPTIM_ARR_ARR_Msk                        /*!< Auto reload register */\n\n/******************  Bit definition for LPTIM_CNT register  *******************/\n#define LPTIM_CNT_CNT_Pos             (0U)\n#define LPTIM_CNT_CNT_Msk             (0xFFFFUL << LPTIM_CNT_CNT_Pos)           /*!< 0x0000FFFF */\n#define LPTIM_CNT_CNT                 LPTIM_CNT_CNT_Msk                        /*!< Counter register     */\n\n/******************  Bit definition for LPTIM_OR register  *******************/\n#define LPTIM_OR_LPT_IN1_RMP_Pos      (0U)\n#define LPTIM_OR_LPT_IN1_RMP_Msk      (0x3UL << LPTIM_OR_LPT_IN1_RMP_Pos)       /*!< 0x00000003 */\n#define LPTIM_OR_LPT_IN1_RMP          LPTIM_OR_LPT_IN1_RMP_Msk                 /*!< LPTIMER[1:0] bits (Remap selection) */\n#define LPTIM_OR_LPT_IN1_RMP_0        (0x1UL << LPTIM_OR_LPT_IN1_RMP_Pos)       /*!< 0x00000001 */\n#define LPTIM_OR_LPT_IN1_RMP_1        (0x2UL << LPTIM_OR_LPT_IN1_RMP_Pos)       /*!< 0x00000002 */\n#define LPTIM_OR_TIM1_ITR2_RMP_Pos    (2U)\n#define LPTIM_OR_TIM1_ITR2_RMP_Msk    (0x1UL << LPTIM_OR_TIM1_ITR2_RMP_Pos)     /*!< 0x00000004 */\n#define LPTIM_OR_TIM1_ITR2_RMP        LPTIM_OR_TIM1_ITR2_RMP_Msk               /*!< Bit 2 */\n#define LPTIM_OR_TIM5_ITR1_RMP_Pos    (3U)\n#define LPTIM_OR_TIM5_ITR1_RMP_Msk    (0x1UL << LPTIM_OR_TIM5_ITR1_RMP_Pos)     /*!< 0x00000008 */\n#define LPTIM_OR_TIM5_ITR1_RMP        LPTIM_OR_TIM5_ITR1_RMP_Msk               /*!< Bit 3 */\n#define LPTIM_OR_TIM9_ITR1_RMP_Pos    (4U)\n#define LPTIM_OR_TIM9_ITR1_RMP_Msk    (0x1UL << LPTIM_OR_TIM9_ITR1_RMP_Pos)     /*!< 0x00000010 */\n#define LPTIM_OR_TIM9_ITR1_RMP        LPTIM_OR_TIM9_ITR1_RMP_Msk               /*!< Bit 4 */\n\n/* Legacy Defines */\n#define  LPTIM_OR_OR                           LPTIM_OR_LPT_IN1_RMP\n#define  LPTIM_OR_OR_0                         LPTIM_OR_LPT_IN1_RMP_0\n#define  LPTIM_OR_OR_1                         LPTIM_OR_LPT_IN1_RMP_1\n\n\n/******************************************************************************/\n/*                                                                            */\n/*         Universal Synchronous Asynchronous Receiver Transmitter            */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for USART_SR register  *******************/\n#define USART_SR_PE_Pos               (0U)\n#define USART_SR_PE_Msk               (0x1UL << USART_SR_PE_Pos)                /*!< 0x00000001 */\n#define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */\n#define USART_SR_FE_Pos               (1U)\n#define USART_SR_FE_Msk               (0x1UL << USART_SR_FE_Pos)                /*!< 0x00000002 */\n#define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */\n#define USART_SR_NE_Pos               (2U)\n#define USART_SR_NE_Msk               (0x1UL << USART_SR_NE_Pos)                /*!< 0x00000004 */\n#define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */\n#define USART_SR_ORE_Pos              (3U)\n#define USART_SR_ORE_Msk              (0x1UL << USART_SR_ORE_Pos)               /*!< 0x00000008 */\n#define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */\n#define USART_SR_IDLE_Pos             (4U)\n#define USART_SR_IDLE_Msk             (0x1UL << USART_SR_IDLE_Pos)              /*!< 0x00000010 */\n#define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */\n#define USART_SR_RXNE_Pos             (5U)\n#define USART_SR_RXNE_Msk             (0x1UL << USART_SR_RXNE_Pos)              /*!< 0x00000020 */\n#define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */\n#define USART_SR_TC_Pos               (6U)\n#define USART_SR_TC_Msk               (0x1UL << USART_SR_TC_Pos)                /*!< 0x00000040 */\n#define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */\n#define USART_SR_TXE_Pos              (7U)\n#define USART_SR_TXE_Msk              (0x1UL << USART_SR_TXE_Pos)               /*!< 0x00000080 */\n#define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */\n#define USART_SR_LBD_Pos              (8U)\n#define USART_SR_LBD_Msk              (0x1UL << USART_SR_LBD_Pos)               /*!< 0x00000100 */\n#define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */\n#define USART_SR_CTS_Pos              (9U)\n#define USART_SR_CTS_Msk              (0x1UL << USART_SR_CTS_Pos)               /*!< 0x00000200 */\n#define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */\n\n/*******************  Bit definition for USART_DR register  *******************/\n#define USART_DR_DR_Pos               (0U)\n#define USART_DR_DR_Msk               (0x1FFUL << USART_DR_DR_Pos)              /*!< 0x000001FF */\n#define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */\n\n/******************  Bit definition for USART_BRR register  *******************/\n#define USART_BRR_DIV_Fraction_Pos    (0U)\n#define USART_BRR_DIV_Fraction_Msk    (0xFUL << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */\n#define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */\n#define USART_BRR_DIV_Mantissa_Pos    (4U)\n#define USART_BRR_DIV_Mantissa_Msk    (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */\n#define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */\n\n/******************  Bit definition for USART_CR1 register  *******************/\n#define USART_CR1_SBK_Pos             (0U)\n#define USART_CR1_SBK_Msk             (0x1UL << USART_CR1_SBK_Pos)              /*!< 0x00000001 */\n#define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */\n#define USART_CR1_RWU_Pos             (1U)\n#define USART_CR1_RWU_Msk             (0x1UL << USART_CR1_RWU_Pos)              /*!< 0x00000002 */\n#define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */\n#define USART_CR1_RE_Pos              (2U)\n#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */\n#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */\n#define USART_CR1_TE_Pos              (3U)\n#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */\n#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */\n#define USART_CR1_IDLEIE_Pos          (4U)\n#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */\n#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */\n#define USART_CR1_RXNEIE_Pos          (5U)\n#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */\n#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */\n#define USART_CR1_TCIE_Pos            (6U)\n#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */\n#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */\n#define USART_CR1_TXEIE_Pos           (7U)\n#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */\n#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<TXE Interrupt Enable                   */\n#define USART_CR1_PEIE_Pos            (8U)\n#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */\n#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */\n#define USART_CR1_PS_Pos              (9U)\n#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */\n#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */\n#define USART_CR1_PCE_Pos             (10U)\n#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */\n#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */\n#define USART_CR1_WAKE_Pos            (11U)\n#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */\n#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */\n#define USART_CR1_M_Pos               (12U)\n#define USART_CR1_M_Msk               (0x1UL << USART_CR1_M_Pos)                /*!< 0x00001000 */\n#define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */\n#define USART_CR1_UE_Pos              (13U)\n#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00002000 */\n#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */\n#define USART_CR1_OVER8_Pos           (15U)\n#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */\n#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */\n\n/******************  Bit definition for USART_CR2 register  *******************/\n#define USART_CR2_ADD_Pos             (0U)\n#define USART_CR2_ADD_Msk             (0xFUL << USART_CR2_ADD_Pos)              /*!< 0x0000000F */\n#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */\n#define USART_CR2_LBDL_Pos            (5U)\n#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */\n#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */\n#define USART_CR2_LBDIE_Pos           (6U)\n#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */\n#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */\n#define USART_CR2_LBCL_Pos            (8U)\n#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */\n#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */\n#define USART_CR2_CPHA_Pos            (9U)\n#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */\n#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */\n#define USART_CR2_CPOL_Pos            (10U)\n#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */\n#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */\n#define USART_CR2_CLKEN_Pos           (11U)\n#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */\n#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */\n\n#define USART_CR2_STOP_Pos            (12U)\n#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */\n#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */\n#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x1000 */\n#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x2000 */\n\n#define USART_CR2_LINEN_Pos           (14U)\n#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */\n#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */\n\n/******************  Bit definition for USART_CR3 register  *******************/\n#define USART_CR3_EIE_Pos             (0U)\n#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */\n#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */\n#define USART_CR3_IREN_Pos            (1U)\n#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */\n#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */\n#define USART_CR3_IRLP_Pos            (2U)\n#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */\n#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */\n#define USART_CR3_HDSEL_Pos           (3U)\n#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */\n#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */\n#define USART_CR3_NACK_Pos            (4U)\n#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */\n#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */\n#define USART_CR3_SCEN_Pos            (5U)\n#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */\n#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */\n#define USART_CR3_DMAR_Pos            (6U)\n#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */\n#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */\n#define USART_CR3_DMAT_Pos            (7U)\n#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */\n#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */\n#define USART_CR3_RTSE_Pos            (8U)\n#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */\n#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */\n#define USART_CR3_CTSE_Pos            (9U)\n#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */\n#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */\n#define USART_CR3_CTSIE_Pos           (10U)\n#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */\n#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */\n#define USART_CR3_ONEBIT_Pos          (11U)\n#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */\n#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */\n\n/******************  Bit definition for USART_GTPR register  ******************/\n#define USART_GTPR_PSC_Pos            (0U)\n#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */\n#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */\n#define USART_GTPR_PSC_0              (0x01UL << USART_GTPR_PSC_Pos)            /*!< 0x0001 */\n#define USART_GTPR_PSC_1              (0x02UL << USART_GTPR_PSC_Pos)            /*!< 0x0002 */\n#define USART_GTPR_PSC_2              (0x04UL << USART_GTPR_PSC_Pos)            /*!< 0x0004 */\n#define USART_GTPR_PSC_3              (0x08UL << USART_GTPR_PSC_Pos)            /*!< 0x0008 */\n#define USART_GTPR_PSC_4              (0x10UL << USART_GTPR_PSC_Pos)            /*!< 0x0010 */\n#define USART_GTPR_PSC_5              (0x20UL << USART_GTPR_PSC_Pos)            /*!< 0x0020 */\n#define USART_GTPR_PSC_6              (0x40UL << USART_GTPR_PSC_Pos)            /*!< 0x0040 */\n#define USART_GTPR_PSC_7              (0x80UL << USART_GTPR_PSC_Pos)            /*!< 0x0080 */\n\n#define USART_GTPR_GT_Pos             (8U)\n#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */\n#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            Window WATCHDOG                                 */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for WWDG_CR register  ********************/\n#define WWDG_CR_T_Pos           (0U)\n#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */\n#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\n#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x01 */\n#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x02 */\n#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x04 */\n#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x08 */\n#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x10 */\n#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x20 */\n#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x40 */\n/* Legacy defines */\n#define  WWDG_CR_T0                          WWDG_CR_T_0\n#define  WWDG_CR_T1                          WWDG_CR_T_1\n#define  WWDG_CR_T2                          WWDG_CR_T_2\n#define  WWDG_CR_T3                          WWDG_CR_T_3\n#define  WWDG_CR_T4                          WWDG_CR_T_4\n#define  WWDG_CR_T5                          WWDG_CR_T_5\n#define  WWDG_CR_T6                          WWDG_CR_T_6\n\n#define WWDG_CR_WDGA_Pos        (7U)\n#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */\n#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */\n\n/*******************  Bit definition for WWDG_CFR register  *******************/\n#define WWDG_CFR_W_Pos          (0U)\n#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */\n#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */\n#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x0001 */\n#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x0002 */\n#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x0004 */\n#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x0008 */\n#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x0010 */\n#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x0020 */\n#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x0040 */\n/* Legacy defines */\n#define  WWDG_CFR_W0                         WWDG_CFR_W_0\n#define  WWDG_CFR_W1                         WWDG_CFR_W_1\n#define  WWDG_CFR_W2                         WWDG_CFR_W_2\n#define  WWDG_CFR_W3                         WWDG_CFR_W_3\n#define  WWDG_CFR_W4                         WWDG_CFR_W_4\n#define  WWDG_CFR_W5                         WWDG_CFR_W_5\n#define  WWDG_CFR_W6                         WWDG_CFR_W_6\n\n#define WWDG_CFR_WDGTB_Pos      (7U)\n#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */\n#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */\n#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */\n#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */\n/* Legacy defines */\n#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0\n#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1\n\n#define WWDG_CFR_EWI_Pos        (9U)\n#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */\n#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */\n\n/*******************  Bit definition for WWDG_SR register  ********************/\n#define WWDG_SR_EWIF_Pos        (0U)\n#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */\n#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                DBG                                         */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for DBGMCU_IDCODE register  *************/\n#define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)\n#define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\n#define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk\n#define DBGMCU_IDCODE_REV_ID_Pos                     (16U)\n#define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\n#define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk\n\n/********************  Bit definition for DBGMCU_CR register  *****************/\n#define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)\n#define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */\n#define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk\n#define DBGMCU_CR_DBG_STOP_Pos                       (1U)\n#define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk\n#define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)\n#define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */\n#define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk\n#define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)\n#define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */\n#define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk\n\n#define DBGMCU_CR_TRACE_MODE_Pos                     (6U)\n#define DBGMCU_CR_TRACE_MODE_Msk                     (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */\n#define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk\n#define DBGMCU_CR_TRACE_MODE_0                       (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */\n#define DBGMCU_CR_TRACE_MODE_1                       (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */\n\n/********************  Bit definition for DBGMCU_APB1_FZ register  ************/\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Pos            (9U)\n#define DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Pos) /*!< 0x00000200 */\n#define DBGMCU_APB1_FZ_DBG_LPTIM_STOP                DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos    (24U)\n#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */\n#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos             (27U)\n#define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos) /*!< 0x08000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN3_STOP                 DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk\n\n/********************  Bit definition for DBGMCU_APB2_FZ register  ************/\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                                       USB_OTG                              */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/\n#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)\n#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */\n#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)\n#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\n#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */\n#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)\n#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */\n#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)\n#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */\n#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */\n#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)\n#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */\n#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)\n#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */\n#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */\n#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)\n#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */\n#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)\n#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */\n#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)\n#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)\n#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */\n#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)\n#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)\n#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */\n#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */\n#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)\n#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */\n#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */\n#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)\n#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */\n#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */\n#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)\n#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */\n#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)\n#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */\n#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)\n#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */\n#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)\n#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */\n#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */\n\n/********************  Bit definition forUSB_OTG_HCFG register  ********************/\n\n#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)\n#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\n#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */\n#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCFG_FSLSS_Pos                   (2U)\n#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */\n\n/********************  Bit definition for USB_OTG_DCFG register  ********************/\n\n#define USB_OTG_DCFG_DSPD_Pos                    (0U)\n#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\n#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */\n#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)\n#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */\n\n#define USB_OTG_DCFG_DAD_Pos                     (4U)\n#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\n#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */\n#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\n\n#define USB_OTG_DCFG_PFIVL_Pos                   (11U)\n#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\n#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */\n#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\n\n#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)\n#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */\n#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk        /*!< Transceiver delay */\n\n#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)\n#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */\n#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk        /*!< Erratic error interrupt mask */\n\n#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)\n#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\n#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */\n#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\n#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\n\n/********************  Bit definition for USB_OTG_PCGCR register  ********************/\n#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)\n#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */\n#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)\n#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */\n#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)\n#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */\n\n/********************  Bit definition for USB_OTG_GOTGINT register  ********************/\n#define USB_OTG_GOTGINT_SEDET_Pos                (2U)\n#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */\n#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)\n#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */\n#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)\n#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */\n#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)\n#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */\n#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)\n#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */\n#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)\n#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */\n#define USB_OTG_GOTGINT_IDCHNG_Pos               (20U)\n#define USB_OTG_GOTGINT_IDCHNG_Msk               (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */\n#define USB_OTG_GOTGINT_IDCHNG                   USB_OTG_GOTGINT_IDCHNG_Msk    /*!< Change in ID pin input value           */\n\n/********************  Bit definition for USB_OTG_DCTL register  ********************/\n#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)\n#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */\n#define USB_OTG_DCTL_SDIS_Pos                    (1U)\n#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */\n#define USB_OTG_DCTL_GINSTS_Pos                  (2U)\n#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */\n#define USB_OTG_DCTL_GONSTS_Pos                  (3U)\n#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\n#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */\n\n#define USB_OTG_DCTL_TCTL_Pos                    (4U)\n#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\n#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */\n#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCTL_SGINAK_Pos                  (7U)\n#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */\n#define USB_OTG_DCTL_CGINAK_Pos                  (8U)\n#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */\n#define USB_OTG_DCTL_SGONAK_Pos                  (9U)\n#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */\n#define USB_OTG_DCTL_CGONAK_Pos                  (10U)\n#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\n#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */\n#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)\n#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */\n\n/********************  Bit definition for USB_OTG_HFIR register  ********************/\n#define USB_OTG_HFIR_FRIVL_Pos                   (0U)\n#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */\n\n/********************  Bit definition for USB_OTG_HFNUM register  ********************/\n#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)\n#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */\n#define USB_OTG_HFNUM_FTREM_Pos                  (16U)\n#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */\n\n/********************  Bit definition for USB_OTG_DSTS register  ********************/\n#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)\n#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */\n\n#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)\n#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\n#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */\n#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\n#define USB_OTG_DSTS_EERR_Pos                    (3U)\n#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\n#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */\n#define USB_OTG_DSTS_FNSOF_Pos                   (8U)\n#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\n#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */\n\n/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/\n#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)\n#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\n#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */\n#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)\n#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\n#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */\n#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */\n#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */\n#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */\n#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */\n#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */\n#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)\n#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */\n#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)\n#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */\n#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)\n#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\n#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */\n\n/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/\n\n#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)\n#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\n#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */\n#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\n#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\n#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\n#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)\n#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\n#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\n#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)\n#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\n#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */\n#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)\n#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\n#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */\n#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)\n#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\n#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */\n#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\n#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\n#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\n#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\n#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)\n#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */\n#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)\n#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\n#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */\n#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)\n#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\n#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */\n#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)\n#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\n#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */\n#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)\n#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\n#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */\n#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)\n#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\n#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */\n#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)\n#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\n#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */\n#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)\n#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\n#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */\n#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)\n#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\n#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */\n#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)\n#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\n#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */\n#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)\n#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */\n\n/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/\n#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)\n#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\n#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */\n#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)\n#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\n#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */\n#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)\n#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\n#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */\n#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)\n#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\n#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */\n#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)\n#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\n#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */\n\n\n#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)\n#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\n#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */\n#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\n#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\n#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)\n#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\n#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */\n#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)\n#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\n#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */\n\n/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/\n#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)\n#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)\n#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)\n#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)\n#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)\n#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/\n#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)\n#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */\n#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)\n#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */\n#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)\n#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */\n#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\n\n/********************  Bit definition for USB_OTG_HAINT register  ********************/\n#define USB_OTG_HAINT_HAINT_Pos                  (0U)\n#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */\n\n/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/\n#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask              */\n#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */\n#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)\n#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */\n#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */\n#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)\n#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */\n#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)\n#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */\n#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)\n#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */\n#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */\n#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)\n#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */\n#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)\n#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */\n#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)\n#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */\n#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)\n#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */\n#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)\n#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */\n/********************  Bit definition for USB_OTG_GINTSTS register  ********************/\n#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)\n#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\n#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */\n#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)\n#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */\n#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)\n#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */\n#define USB_OTG_GINTSTS_SOF_Pos                  (3U)\n#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */\n#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)\n#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */\n#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)\n#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */\n#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)\n#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */\n#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)\n#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */\n#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)\n#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */\n#define USB_OTG_GINTSTS_USBRST_Pos               (12U)\n#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */\n#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)\n#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */\n#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)\n#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */\n#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)\n#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */\n#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)\n#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */\n#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)\n#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */\n#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)\n#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */\n#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)\n#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */\n#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)\n#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */\n#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */\n#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)\n#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */\n#define USB_OTG_GINTSTS_HCINT_Pos                (25U)\n#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */\n#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)\n#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */\n#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)\n#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */\n#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */\n#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)\n#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */\n#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)\n#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */\n#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)\n#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */\n#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)\n#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */\n\n/********************  Bit definition for USB_OTG_GINTMSK register  ********************/\n#define USB_OTG_GINTMSK_MMISM_Pos                (1U)\n#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */\n#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)\n#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */\n#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)\n#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */\n#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)\n#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */\n#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)\n#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */\n#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)\n#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */\n#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)\n#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */\n#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)\n#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */\n#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)\n#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */\n#define USB_OTG_GINTMSK_USBRST_Pos               (12U)\n#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */\n#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)\n#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */\n#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)\n#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */\n#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)\n#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */\n#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)\n#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\n#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */\n#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)\n#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */\n#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)\n#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */\n#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)\n#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */\n#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)\n#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */\n#define USB_OTG_GINTMSK_RSTDETM_Pos              (23U)\n#define USB_OTG_GINTMSK_RSTDETM_Msk              (0x1UL << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */\n#define USB_OTG_GINTMSK_RSTDETM                  USB_OTG_GINTMSK_RSTDETM_Msk   /*!< Reset detected interrupt mask */\n#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)\n#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */\n#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)\n#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */\n#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)\n#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */\n#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)\n#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */\n#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */\n#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)\n#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */\n#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)\n#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */\n#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)\n#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */\n#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)\n#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */\n\n/********************  Bit definition for USB_OTG_DAINT register  ********************/\n#define USB_OTG_DAINT_IEPINT_Pos                 (0U)\n#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */\n#define USB_OTG_DAINT_OEPINT_Pos                 (16U)\n#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */\n\n/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/\n#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)\n#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */\n\n/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/\n#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)\n#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\n#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */\n#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)\n#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\n#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)\n#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\n#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)\n#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/\n#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)\n#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */\n#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)\n#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/\n#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)\n#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/\n#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)\n#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */\n\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_NPTXFSA_Pos                      (0U)\n#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */\n#define USB_OTG_NPTXFD_Pos                       (16U)\n#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */\n#define USB_OTG_TX0FSA_Pos                       (0U)\n#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */\n#define USB_OTG_TX0FD_Pos                        (16U)\n#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */\n\n/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/\n#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)\n#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\n#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\n\n/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\n\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/\n#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)\n#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\n#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\n#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)\n#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\n#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */\n\n#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)\n#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\n#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */\n#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)\n#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\n#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */\n\n#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)\n#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */\n#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\n#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)\n#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\n#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */\n\n/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DEACHINT register  ********************/\n#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)\n#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */\n#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)\n#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */\n\n/********************  Bit definition for USB_OTG_GCCFG register  ********************/\n#define USB_OTG_GCCFG_DCDET_Pos                  (0U)\n#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */\n#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */\n#define USB_OTG_GCCFG_PDET_Pos                   (1U)\n#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */\n#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */\n#define USB_OTG_GCCFG_SDET_Pos                   (2U)\n#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */\n#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */\n#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)\n#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */\n#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */\n#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)\n#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\n#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */\n#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)\n#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */\n#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)\n#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/\n#define USB_OTG_GCCFG_PDEN_Pos                   (19U)\n#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/\n#define USB_OTG_GCCFG_SDEN_Pos                   (20U)\n#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */\n#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)\n#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< USB VBUS Detection Enable */\n\n/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\n\n/********************  Bit definition for USB_OTG_CID register  ********************/\n#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)\n#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */\n\n/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/\n#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)\n#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */\n#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */\n#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)\n#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */\n#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */\n#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)\n#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */\n#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */\n#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)\n#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */\n#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */\n#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)\n#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */\n#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)\n#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */\n#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */\n#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)\n#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */\n#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */\n#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)\n#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */\n#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */\n#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)\n#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */\n#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)\n#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */\n#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */\n#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)\n#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */\n#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)\n#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */\n#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */\n#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)\n#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */\n#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */\n#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)\n#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */\n#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */\n\n/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */\n#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPRT register  ********************/\n#define USB_OTG_HPRT_PCSTS_Pos                   (0U)\n#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */\n#define USB_OTG_HPRT_PCDET_Pos                   (1U)\n#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\n#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */\n#define USB_OTG_HPRT_PENA_Pos                    (2U)\n#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\n#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */\n#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)\n#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\n#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */\n#define USB_OTG_HPRT_POCA_Pos                    (4U)\n#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\n#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */\n#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)\n#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\n#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */\n#define USB_OTG_HPRT_PRES_Pos                    (6U)\n#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\n#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */\n#define USB_OTG_HPRT_PSUSP_Pos                   (7U)\n#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\n#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */\n#define USB_OTG_HPRT_PRST_Pos                    (8U)\n#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\n#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */\n\n#define USB_OTG_HPRT_PLSTS_Pos                   (10U)\n#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\n#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */\n#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\n#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_HPRT_PPWR_Pos                    (12U)\n#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */\n\n#define USB_OTG_HPRT_PTCTL_Pos                   (13U)\n#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\n#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */\n#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\n#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\n#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\n#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\n\n#define USB_OTG_HPRT_PSPD_Pos                    (17U)\n#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\n#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */\n#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\n\n/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */\n#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */\n#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */\n#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)\n#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */\n#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)\n#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */\n\n/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/\n#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)\n#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */\n#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)\n#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */\n\n/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/\n#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */\n#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */\n#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)\n#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\n#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */\n#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */\n\n#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */\n#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DIEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */\n\n#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)\n#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\n#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */\n#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\n#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\n#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\n#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\n#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */\n#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */\n#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */\n#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */\n#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */\n\n/********************  Bit definition for USB_OTG_HCCHAR register  ********************/\n#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)\n#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */\n\n#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)\n#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\n#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */\n#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\n#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)\n#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */\n#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)\n#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */\n\n#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)\n#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */\n#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\n\n#define USB_OTG_HCCHAR_MC_Pos                    (20U)\n#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\n#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */\n#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\n#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\n\n#define USB_OTG_HCCHAR_DAD_Pos                   (22U)\n#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\n#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */\n#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\n#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\n#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\n#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\n#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\n#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\n#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\n#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)\n#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */\n#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)\n#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */\n#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)\n#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */\n\n/********************  Bit definition for USB_OTG_HCSPLT register  ********************/\n\n#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)\n#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\n#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */\n#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\n\n#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)\n#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\n#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */\n#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\n\n#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)\n#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\n#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */\n#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)\n#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\n#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */\n#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)\n#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */\n\n/********************  Bit definition for USB_OTG_HCINT register  ********************/\n#define USB_OTG_HCINT_XFRC_Pos                   (0U)\n#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */\n#define USB_OTG_HCINT_CHH_Pos                    (1U)\n#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */\n#define USB_OTG_HCINT_AHBERR_Pos                 (2U)\n#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */\n#define USB_OTG_HCINT_STALL_Pos                  (3U)\n#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */\n#define USB_OTG_HCINT_NAK_Pos                    (4U)\n#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */\n#define USB_OTG_HCINT_ACK_Pos                    (5U)\n#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */\n#define USB_OTG_HCINT_NYET_Pos                   (6U)\n#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */\n#define USB_OTG_HCINT_TXERR_Pos                  (7U)\n#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */\n#define USB_OTG_HCINT_BBERR_Pos                  (8U)\n#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */\n#define USB_OTG_HCINT_FRMOR_Pos                  (9U)\n#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */\n#define USB_OTG_HCINT_DTERR_Pos                  (10U)\n#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */\n\n/********************  Bit definition for USB_OTG_DIEPINT register  ********************/\n#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)\n#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */\n#define USB_OTG_DIEPINT_TOC_Pos                  (3U)\n#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */\n#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)\n#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */\n#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)\n#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */\n#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */\n#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)\n#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */\n#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)\n#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\n#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\n#define USB_OTG_DIEPINT_BNA_Pos                  (9U)\n#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */\n#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)\n#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\n#define USB_OTG_DIEPINT_BERR_Pos                 (12U)\n#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\n#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */\n#define USB_OTG_DIEPINT_NAK_Pos                  (13U)\n#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */\n\n/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/\n#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)\n#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */\n#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)\n#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */\n#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)\n#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */\n#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)\n#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */\n#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)\n#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */\n#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)\n#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */\n#define USB_OTG_HCINTMSK_NYET_Pos                (6U)\n#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */\n#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)\n#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */\n#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)\n#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */\n#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)\n#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */\n#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)\n#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */\n\n/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/\n\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)\n#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */\n/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/\n#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)\n#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */\n#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)\n#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */\n#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)\n#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */\n#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)\n#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\n#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */\n#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/\n#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)\n#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_HCDMA register  ********************/\n#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)\n#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/\n#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)\n#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */\n\n/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/\n#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)\n#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */\n#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)\n#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/\n\n#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */\n#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */\n#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\n#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */\n#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */\n#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)\n#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\n#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */\n#define USB_OTG_DOEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */\n#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */\n#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */\n#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */\n\n/********************  Bit definition for USB_OTG_DOEPINT register  ********************/\n#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)\n#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */\n#define USB_OTG_DOEPINT_STUP_Pos                 (3U)\n#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */\n#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)\n#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */\n#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)\n#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */\n#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */\n#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)\n#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */\n#define USB_OTG_DOEPINT_NAK_Pos                  (13U)\n#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */\n#define USB_OTG_DOEPINT_NYET_Pos                 (14U)\n#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */\n#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)\n#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */\n/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/\n\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n\n#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)\n#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */\n#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for PCGCCTL register  ********************/\n#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)\n#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */\n#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)\n#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */\n#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)\n#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */\n\n/* Legacy define */\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_CHNUM_Pos                        (0U)\n#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\n#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\n#define USB_OTG_BCNT_Pos                         (4U)\n#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\n\n#define USB_OTG_DPID_Pos                         (15U)\n#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)    /*!< 0x00018000 */\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\n#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\n#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\n\n#define USB_OTG_PKTSTS_Pos                       (17U)\n#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\n#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\n#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\n#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\n#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\n\n#define USB_OTG_EPNUM_Pos                        (0U)\n#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\n#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\n\n#define USB_OTG_FRMNUM_Pos                       (21U)\n#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\n#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\n#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\n#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\n#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_macros\n  * @{\n  */\n\n/******************************* ADC Instances ********************************/\n#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\n\n#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)\n\n/******************************* CAN Instances ********************************/\n#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \\\n                                       ((INSTANCE) == CAN2) || \\\n                                       ((INSTANCE) == CAN3))\n\n/****************************** DFSDM Instances *******************************/\n#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \\\n                                                ((INSTANCE) == DFSDM1_Filter1) || \\\n                                                ((INSTANCE) == DFSDM2_Filter0) || \\\n                                                ((INSTANCE) == DFSDM2_Filter1) || \\\n                                                ((INSTANCE) == DFSDM2_Filter2) || \\\n                                                ((INSTANCE) == DFSDM2_Filter3))\n\n#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel1) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel2) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel3) || \\\n                                                 ((INSTANCE) == DFSDM2_Channel0) || \\\n                                                 ((INSTANCE) == DFSDM2_Channel1) || \\\n                                                 ((INSTANCE) == DFSDM2_Channel2) || \\\n                                                 ((INSTANCE) == DFSDM2_Channel3) || \\\n                                                 ((INSTANCE) == DFSDM2_Channel4) || \\\n                                                 ((INSTANCE) == DFSDM2_Channel5) || \\\n                                                 ((INSTANCE) == DFSDM2_Channel6) || \\\n                                                 ((INSTANCE) == DFSDM2_Channel7))\n/******************************* CRC Instances ********************************/\n#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\n\n/******************************* DAC Instances ********************************/\n#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)\n\n\n/******************************** DMA Instances *******************************/\n#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \\\n                                              ((INSTANCE) == DMA1_Stream1) || \\\n                                              ((INSTANCE) == DMA1_Stream2) || \\\n                                              ((INSTANCE) == DMA1_Stream3) || \\\n                                              ((INSTANCE) == DMA1_Stream4) || \\\n                                              ((INSTANCE) == DMA1_Stream5) || \\\n                                              ((INSTANCE) == DMA1_Stream6) || \\\n                                              ((INSTANCE) == DMA1_Stream7) || \\\n                                              ((INSTANCE) == DMA2_Stream0) || \\\n                                              ((INSTANCE) == DMA2_Stream1) || \\\n                                              ((INSTANCE) == DMA2_Stream2) || \\\n                                              ((INSTANCE) == DMA2_Stream3) || \\\n                                              ((INSTANCE) == DMA2_Stream4) || \\\n                                              ((INSTANCE) == DMA2_Stream5) || \\\n                                              ((INSTANCE) == DMA2_Stream6) || \\\n                                              ((INSTANCE) == DMA2_Stream7))\n\n/******************************* GPIO Instances *******************************/\n#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\\n                                        ((INSTANCE) == GPIOB) || \\\n                                        ((INSTANCE) == GPIOC) || \\\n                                        ((INSTANCE) == GPIOD) || \\\n                                        ((INSTANCE) == GPIOE) || \\\n                                        ((INSTANCE) == GPIOF) || \\\n                                        ((INSTANCE) == GPIOG) || \\\n                                        ((INSTANCE) == GPIOH))\n\n/******************************** I2C Instances *******************************/\n#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\n                                       ((INSTANCE) == I2C2) || \\\n                                       ((INSTANCE) == I2C3))\n\n/******************************* SMBUS Instances ******************************/\n#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE\n\n/******************************** I2S Instances *******************************/\n#define IS_I2S_APB1_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \\\n                                         ((INSTANCE) == SPI3))\n\n#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI1) || \\\n                                        ((INSTANCE) == SPI2) || \\\n                                        ((INSTANCE) == SPI3) || \\\n                                        ((INSTANCE) == SPI4) || \\\n                                        ((INSTANCE) == SPI5))\n\n/*************************** I2S Extended Instances ***************************/\n#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \\\n                                           ((INSTANCE) == I2S3ext))\n/* Legacy Defines */\n#define IS_I2S_ALL_INSTANCE_EXT    IS_I2S_EXT_ALL_INSTANCE\n\n/******************************* LPTIM Instances ******************************/\n#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)\n\n/******************************* RNG Instances ********************************/\n#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)\n\n/****************************** RTC Instances *********************************/\n#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\n\n\n/******************************** SPI Instances *******************************/\n\n#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\\n                                       ((INSTANCE) == SPI2) || \\\n                                       ((INSTANCE) == SPI3) || \\\n                                       ((INSTANCE) == SPI4) || \\\n                                       ((INSTANCE) == SPI5))\n\n\n/*************************** SPI Extended Instances ***************************/\n#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1)    || \\\n                                           ((INSTANCE) == SPI2)    || \\\n                                           ((INSTANCE) == SPI3)    || \\\n                                           ((INSTANCE) == SPI4)    || \\\n                                           ((INSTANCE) == SPI5)    || \\\n                                           ((INSTANCE) == I2S2ext) || \\\n                                           ((INSTANCE) == I2S3ext))\n/******************************* SAI Instances ********************************/\n#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \\\n                                     ((PERIPH) == SAI1_Block_B))\n/****************** TIM Instances : All supported instances *******************/\n#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                    ((INSTANCE) == TIM2) || \\\n                                    ((INSTANCE) == TIM3) || \\\n                                    ((INSTANCE) == TIM4) || \\\n                                    ((INSTANCE) == TIM5) || \\\n                                    ((INSTANCE) == TIM6) || \\\n                                    ((INSTANCE) == TIM7) || \\\n                                    ((INSTANCE) == TIM8) || \\\n                                    ((INSTANCE) == TIM9) || \\\n                                    ((INSTANCE) == TIM10)|| \\\n                                    ((INSTANCE) == TIM11)|| \\\n                                    ((INSTANCE) == TIM12)|| \\\n                                    ((INSTANCE) == TIM13)|| \\\n                                    ((INSTANCE) == TIM14))\n\n/************* TIM Instances : at least 1 capture/compare channel *************/\n#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \\\n                                         ((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM3)  || \\\n                                         ((INSTANCE) == TIM4)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM8)  || \\\n                                         ((INSTANCE) == TIM9)  || \\\n                                         ((INSTANCE) == TIM10) || \\\n                                         ((INSTANCE) == TIM11) || \\\n                                         ((INSTANCE) == TIM12) || \\\n                                         ((INSTANCE) == TIM13) || \\\n                                         ((INSTANCE) == TIM14))\n\n/************ TIM Instances : at least 2 capture/compare channels *************/\n#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8) || \\\n                                       ((INSTANCE) == TIM9) || \\\n                                       ((INSTANCE) == TIM12))\n\n/************ TIM Instances : at least 3 capture/compare channels *************/\n#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/************ TIM Instances : at least 4 capture/compare channels *************/\n#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : Advanced-control timers *****************/\n#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                           ((INSTANCE) == TIM8))\n\n/******************* TIM Instances : Timer input XOR function *****************/\n#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : DMA requests generation (UDE) *************/\n#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM6) || \\\n                                       ((INSTANCE) == TIM7) || \\\n                                       ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (CCxDE) *****************/\n#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (COMDE) *****************/\n#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : DMA burst feature ***********************/\n#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                             ((INSTANCE) == TIM2) || \\\n                                             ((INSTANCE) == TIM3) || \\\n                                             ((INSTANCE) == TIM4) || \\\n                                             ((INSTANCE) == TIM5) || \\\n                                             ((INSTANCE) == TIM8))\n\n/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\n#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                          ((INSTANCE) == TIM2)  || \\\n                                          ((INSTANCE) == TIM3)  || \\\n                                          ((INSTANCE) == TIM4)  || \\\n                                          ((INSTANCE) == TIM5)  || \\\n                                          ((INSTANCE) == TIM6)  || \\\n                                          ((INSTANCE) == TIM7)  || \\\n                                          ((INSTANCE) == TIM8))\n\n/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\n#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8) || \\\n                                         ((INSTANCE) == TIM9) || \\\n                                         ((INSTANCE) == TIM12))\n/********************** TIM Instances : 32 bit Counter ************************/\n#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \\\n                                              ((INSTANCE) == TIM5))\n\n/***************** TIM Instances : external trigger input availabe ************/\n#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                        ((INSTANCE) == TIM2) || \\\n                                        ((INSTANCE) == TIM3) || \\\n                                        ((INSTANCE) == TIM4) || \\\n                                        ((INSTANCE) == TIM5) || \\\n                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : remapping capability **********************/\n#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM11))\n\n/******************* TIM Instances : output(s) available **********************/\n#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\\n    ((((INSTANCE) == TIM1) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM2) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM3) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM4) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM5) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM8) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM9) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM10) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM11) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM12) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM13) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM14) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1))))\n\n/************ TIM Instances : complementary output(s) available ***************/\n#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\\n   ((((INSTANCE) == TIM1) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3)))            \\\n    ||                                          \\\n    (((INSTANCE) == TIM8) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3))))\n\n/****************** TIM Instances : supporting counting mode selection ********/\n#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting clock division *****************/\n#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                                  ((INSTANCE) == TIM2) || \\\n                                                  ((INSTANCE) == TIM3) || \\\n                                                  ((INSTANCE) == TIM4) || \\\n                                                  ((INSTANCE) == TIM5) || \\\n                                                  ((INSTANCE) == TIM8) || \\\n                                                  ((INSTANCE) == TIM9) || \\\n                                                  ((INSTANCE) == TIM10)|| \\\n                                                  ((INSTANCE) == TIM11)|| \\\n                                                  ((INSTANCE) == TIM12)|| \\\n                                                  ((INSTANCE) == TIM13)|| \\\n                                                  ((INSTANCE) == TIM14))\n\n/****************** TIM Instances : supporting commutation event generation ***/\n#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \\\n                                                     ((INSTANCE) == TIM8))\n\n\n/****************** TIM Instances : supporting OCxREF clear *******************/\n#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM2) || \\\n                                                       ((INSTANCE) == TIM3) || \\\n                                                       ((INSTANCE) == TIM4) || \\\n                                                       ((INSTANCE) == TIM5) || \\\n                                                       ((INSTANCE) == TIM8))\n\n/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8))\n\n/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/\n#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/********** TIM Instances : supporting internal trigger inputs(ITRX) *********/\n#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/****************** TIM Instances : supporting repetition counter *************/\n#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting encoder interface **************/\n#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                      ((INSTANCE) == TIM2) || \\\n                                                      ((INSTANCE) == TIM3) || \\\n                                                      ((INSTANCE) == TIM4) || \\\n                                                      ((INSTANCE) == TIM5) || \\\n                                                      ((INSTANCE) == TIM8) || \\\n                                                      ((INSTANCE) == TIM9))\n/****************** TIM Instances : supporting Hall sensor interface **********/\n#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                          ((INSTANCE) == TIM2) || \\\n                                                          ((INSTANCE) == TIM3) || \\\n                                                          ((INSTANCE) == TIM4) || \\\n                                                          ((INSTANCE) == TIM5) || \\\n                                                          ((INSTANCE) == TIM8))\n/****************** TIM Instances : supporting the break function *************/\n#define IS_TIM_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM8))\n\n/******************** USART Instances : Synchronous mode **********************/\n#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                     ((INSTANCE) == USART2) || \\\n                                     ((INSTANCE) == USART3) || \\\n                                     ((INSTANCE) == USART6))\n\n/******************** UART Instances : Half-Duplex mode **********************/\n#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                               ((INSTANCE) == USART2) || \\\n                                               ((INSTANCE) == USART3) || \\\n                                               ((INSTANCE) == UART4)  || \\\n                                               ((INSTANCE) == UART5)  || \\\n                                               ((INSTANCE) == USART6) || \\\n                                               ((INSTANCE) == UART7)  || \\\n                                               ((INSTANCE) == UART8)  || \\\n                                               ((INSTANCE) == UART9)  || \\\n                                               ((INSTANCE) == UART10))\n\n/* Legacy defines */\n#define IS_UART_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE\n\n/****************** UART Instances : Hardware Flow control ********************/\n#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                           ((INSTANCE) == USART2) || \\\n                                           ((INSTANCE) == USART3) || \\\n                                           ((INSTANCE) == USART6))\n/******************** UART Instances : LIN mode **********************/\n#define IS_UART_LIN_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE\n\n/********************* UART Instances : Smart card mode ***********************/\n#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                         ((INSTANCE) == USART2) || \\\n                                         ((INSTANCE) == USART3) || \\\n                                         ((INSTANCE) == USART6))\n\n/*********************** UART Instances : IRDA mode ***************************/\n#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2) || \\\n                                    ((INSTANCE) == USART3) || \\\n                                    ((INSTANCE) == UART4)  || \\\n                                    ((INSTANCE) == UART5)  || \\\n                                    ((INSTANCE) == USART6) || \\\n                                    ((INSTANCE) == UART7)  || \\\n                                    ((INSTANCE) == UART8)  || \\\n                                    ((INSTANCE) == UART9)  || \\\n                                    ((INSTANCE) == UART10))\n\n/*********************** PCD Instances ****************************************/\n#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))\n\n/*********************** HCD Instances ****************************************/\n#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))\n\n/****************************** SDIO Instances ********************************/\n#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)\n\n/****************************** IWDG Instances ********************************/\n#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)\n\n/****************************** WWDG Instances ********************************/\n#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)\n\n\n/***************************** FMPI2C Instances *******************************/\n#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)\n#define IS_FMPSMBUS_ALL_INSTANCE         IS_FMPI2C_ALL_INSTANCE\n\n/****************************** QSPI Instances ********************************/\n#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)\n/****************************** USB Exported Constants ************************/\n#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                12U\n#define USB_OTG_FS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */\n#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */\n#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */\n\n/*\n * @brief Specific devices reset values definitions\n */\n#define RCC_PLLCFGR_RST_VALUE              0x24003010U\n#define RCC_PLLI2SCFGR_RST_VALUE           0x24003010U\n\n#define RCC_MAX_FREQUENCY           100000000U         /*!< Max frequency of family in Hz*/\n#define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */\n#define RCC_MAX_FREQUENCY_SCALE2     84000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */\n#define RCC_MAX_FREQUENCY_SCALE3     64000000U         /*!< Maximum frequency for system clock at power scale3, in Hz */\n#define RCC_PLLVCO_OUTPUT_MIN       100000000U       /*!< Frequency min for PLLVCO output, in Hz */\n#define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */\n\n#define RCC_PLLN_MIN_VALUE                 50U\n#define RCC_PLLN_MAX_VALUE                432U\n\n#define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */\n#define FLASH_SCALE1_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */\n#define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */\n\n#define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */\n#define FLASH_SCALE2_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */\n\n#define FLASH_SCALE3_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */\n#define FLASH_SCALE3_LATENCY2_FREQ   64000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */\n\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32F413xx_H */\n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f446xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f446xx.h\n  * @author  MCD Application Team\n  * @version V2.6.4\n  * @date    06-December-2019\n  * @brief   CMSIS STM32F446xx Device Peripheral Access Layer Header File.\n  *\n  *          This file contains:\n  *           - Data structures and the address mapping for all peripherals\n  *           - peripherals registers declarations and bits definition\n  *           - Macros to access peripheral's registers hardware\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS_Device\n  * @{\n  */\n\n/** @addtogroup stm32f446xx\n  * @{\n  */\n\n#ifndef __STM32F446xx_H\n#define __STM32F446xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Configuration_section_for_CMSIS\n  * @{\n  */\n\n/**\n  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals\n  */\n#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */\n#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */\n#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */\n#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */\n#define __FPU_PRESENT             1U       /*!< FPU present                                   */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_interrupt_number_definition\n  * @{\n  */\n\n/**\n * @brief STM32F4XX Interrupt Number Definition, according to the selected device\n *        in @ref Library_configuration_section\n */\ntypedef enum\n{\n/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */\n  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */\n  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */\n  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */\n  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */\n  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */\n/******  STM32 specific Interrupt Numbers **********************************************************************/\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */\n  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */\n  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\n  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\n  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\n  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\n  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\n  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\n  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\n  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\n  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\n  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */\n  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */\n  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */\n  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */\n  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */\n  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */\n  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */\n  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */\n  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */\n  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */\n  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */\n  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\n  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */\n  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */\n  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\n  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\n  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */\n  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */\n  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */\n  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\n  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */\n  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */\n  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */\n  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\n  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */\n  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */\n  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */\n  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */\n  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */\n  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */\n  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */\n  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */\n  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */\n  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */\n  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */\n  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */\n  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */\n  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */\n  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */\n  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */\n  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */\n  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */\n  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\n  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\n  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */\n  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */\n  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */\n  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */\n  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */\n  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */\n  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */\n  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */\n  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */\n  QUADSPI_IRQn                = 92,     /*!< QuadSPI global Interrupt                                          */\n  CEC_IRQn                    = 93,     /*!< CEC global Interrupt                                              */\n  SPDIF_RX_IRQn               = 94,     /*!< SPDIF-RX global Interrupt                                          */\n  FMPI2C1_EV_IRQn             = 95,     /*!< FMPI2C1 Event Interrupt                                           */\n  FMPI2C1_ER_IRQn             = 96      /*!< FMPI2C1 Error Interrupt                                           */\n} IRQn_Type;\n\n/**\n  * @}\n  */\n\n#include \"core_cm4.h\"             /* Cortex-M4 processor and core peripherals */\n#include \"system_stm32f4xx.h\"\n#include <sys/stdint.h>\n\n/** @addtogroup Peripheral_registers_structures\n  * @{\n  */\n\n/**\n  * @brief Analog to Digital Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */\n  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */\n  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */\n  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */\n  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */\n  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\n  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\n  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\n  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\n  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */\n  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */\n  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */\n  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */\n  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */\n  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/\n  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */\n  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */\n  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */\n  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */\n  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */\n} ADC_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */\n  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */\n  __IO uint32_t CDR;    /*!< ADC common regular data register for dual\n                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */\n} ADC_Common_TypeDef;\n\n\n/**\n  * @brief Controller Area Network TxMailBox\n  */\n\ntypedef struct\n{\n  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */\n  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\n  __IO uint32_t TDLR; /*!< CAN mailbox data low register */\n  __IO uint32_t TDHR; /*!< CAN mailbox data high register */\n} CAN_TxMailBox_TypeDef;\n\n/**\n  * @brief Controller Area Network FIFOMailBox\n  */\n\ntypedef struct\n{\n  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */\n  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\n  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\n  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\n} CAN_FIFOMailBox_TypeDef;\n\n/**\n  * @brief Controller Area Network FilterRegister\n  */\n\ntypedef struct\n{\n  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\n  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\n} CAN_FilterRegister_TypeDef;\n\n/**\n  * @brief Controller Area Network\n  */\n\ntypedef struct\n{\n  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */\n  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */\n  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */\n  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */\n  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */\n  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */\n  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */\n  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */\n  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */\n  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */\n  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */\n  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */\n  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */\n  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */\n  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */\n  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */\n  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */\n  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */\n  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */\n  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */\n  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */\n  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */\n} CAN_TypeDef;\n\n\n/**\n  * @brief Consumer Electronics Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */\n  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */\n  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */\n  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */\n  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */\n  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */\n}CEC_TypeDef;\n/**\n  * @brief CRC calculation unit\n  */\n\ntypedef struct\n{\n  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */\n  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */\n  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */\n  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */\n  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */\n} CRC_TypeDef;\n\n/**\n  * @brief Digital to Analog Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */\n  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */\n  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\n  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */\n  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */\n  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\n  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */\n  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */\n  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */\n  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */\n  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */\n  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */\n  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */\n  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */\n} DAC_TypeDef;\n\n/**\n  * @brief Debug MCU\n  */\n\ntypedef struct\n{\n  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */\n  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */\n  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */\n  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */\n}DBGMCU_TypeDef;\n\n/**\n  * @brief DCMI\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */\n  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */\n  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */\n  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */\n  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */\n  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */\n  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */\n  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */\n  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */\n  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */\n  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */\n} DCMI_TypeDef;\n\n/**\n  * @brief DMA Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;     /*!< DMA stream x configuration register      */\n  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */\n  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */\n  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */\n  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */\n  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */\n} DMA_Stream_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */\n  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */\n  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */\n  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\n} DMA_TypeDef;\n\n/**\n  * @brief External Interrupt/Event Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */\n  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */\n  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */\n  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\n  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */\n  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */\n} EXTI_TypeDef;\n\n/**\n  * @brief FLASH Registers\n  */\n\ntypedef struct\n{\n  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */\n  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */\n  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */\n  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */\n  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */\n  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */\n  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */\n} FLASH_TypeDef;\n\n/**\n  * @brief Flexible Memory Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\n} FMC_Bank1_TypeDef;\n\n/**\n  * @brief Flexible Memory Controller Bank1E\n  */\n\ntypedef struct\n{\n  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\n} FMC_Bank1E_TypeDef;\n\n/**\n  * @brief Flexible Memory Controller Bank3\n  */\n\ntypedef struct\n{\n  __IO uint32_t PCR;       /*!< NAND Flash control register,                       Address offset: 0x80 */\n  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */\n  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */\n  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */\n  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                          */\n  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */\n} FMC_Bank3_TypeDef;\n\n/**\n  * @brief Flexible Memory Controller Bank5_6\n  */\n\ntypedef struct\n{\n  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */\n  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */\n  __IO uint32_t SDCMR;          /*!< SDRAM Command Mode register,   Address offset: 0x150        */\n  __IO uint32_t SDRTR;          /*!< SDRAM Refresh Timer register,  Address offset: 0x154        */\n  __IO uint32_t SDSR;           /*!< SDRAM Status register,         Address offset: 0x158        */\n} FMC_Bank5_6_TypeDef;\n\n/**\n  * @brief General Purpose I/O\n  */\n\ntypedef struct\n{\n  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */\n  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */\n  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */\n  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\n  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */\n  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */\n  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */\n  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */\n  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\n} GPIO_TypeDef;\n\n/**\n  * @brief System configuration controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */\n  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */\n  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\n  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */\n  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */\n  uint32_t      RESERVED1[2]; /*!< Reserved, 0x24-0x28                                                          */\n  __IO uint32_t CFGR;         /*!< SYSCFG Configuration register,                     Address offset: 0x2C      */\n} SYSCFG_TypeDef;\n\n/**\n  * @brief Inter-integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */\n  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */\n  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */\n  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */\n  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */\n  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */\n  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */\n  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */\n  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */\n} I2C_TypeDef;\n\n/**\n  * @brief Inter-integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< FMPI2C Control register 1,            Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< FMPI2C Control register 2,            Address offset: 0x04 */\n  __IO uint32_t OAR1;        /*!< FMPI2C Own address 1 register,        Address offset: 0x08 */\n  __IO uint32_t OAR2;        /*!< FMPI2C Own address 2 register,        Address offset: 0x0C */\n  __IO uint32_t TIMINGR;     /*!< FMPI2C Timing register,               Address offset: 0x10 */\n  __IO uint32_t TIMEOUTR;    /*!< FMPI2C Timeout register,              Address offset: 0x14 */\n  __IO uint32_t ISR;         /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */\n  __IO uint32_t ICR;         /*!< FMPI2C Interrupt clear register,      Address offset: 0x1C */\n  __IO uint32_t PECR;        /*!< FMPI2C PEC register,                  Address offset: 0x20 */\n  __IO uint32_t RXDR;        /*!< FMPI2C Receive data register,         Address offset: 0x24 */\n  __IO uint32_t TXDR;        /*!< FMPI2C Transmit data register,        Address offset: 0x28 */\n} FMPI2C_TypeDef;\n\n/**\n  * @brief Independent WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */\n  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */\n  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */\n  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */\n} IWDG_TypeDef;\n\n\n/**\n  * @brief Power Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */\n  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */\n} PWR_TypeDef;\n\n/**\n  * @brief Reset and Clock Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */\n  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */\n  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */\n  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */\n  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */\n  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */\n  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */\n  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */\n  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */\n  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */\n  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */\n  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */\n  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */\n  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */\n  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */\n  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */\n  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */\n  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\n  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\n  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\n  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */\n  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\n  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\n  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */\n  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */\n  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */\n  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */\n  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */\n  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */\n  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */\n  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */\n  __IO uint32_t CKGATENR;      /*!< RCC Clocks Gated ENable Register,                            Address offset: 0x90 */\n  __IO uint32_t DCKCFGR2;      /*!< RCC Dedicated Clocks configuration register 2,               Address offset: 0x94 */\n} RCC_TypeDef;\n\n/**\n  * @brief Real-Time Clock\n  */\n\ntypedef struct\n{\n  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */\n  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */\n  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */\n  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */\n  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */\n  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */\n  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */\n  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */\n  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */\n  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */\n  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */\n  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */\n  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */\n  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */\n  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */\n  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */\n  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */\n  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */\n  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */\n  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */\n  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */\n  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */\n  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */\n  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */\n  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */\n  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */\n  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */\n  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */\n  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */\n  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */\n  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */\n  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */\n  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */\n  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */\n  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */\n  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */\n  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */\n  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */\n  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */\n  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */\n} RTC_TypeDef;\n\n/**\n  * @brief Serial Audio Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */\n} SAI_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */\n  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */\n  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */\n  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */\n  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */\n  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */\n  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */\n  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */\n} SAI_Block_TypeDef;\n\n/**\n  * @brief SD host Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t POWER;                 /*!< SDIO power control register,    Address offset: 0x00 */\n  __IO uint32_t CLKCR;                 /*!< SDI clock control register,     Address offset: 0x04 */\n  __IO uint32_t ARG;                   /*!< SDIO argument register,         Address offset: 0x08 */\n  __IO uint32_t CMD;                   /*!< SDIO command register,          Address offset: 0x0C */\n  __IO const uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */\n  __IO const uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */\n  __IO const uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */\n  __IO const uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */\n  __IO const uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */\n  __IO uint32_t DTIMER;                /*!< SDIO data timer register,       Address offset: 0x24 */\n  __IO uint32_t DLEN;                  /*!< SDIO data length register,      Address offset: 0x28 */\n  __IO uint32_t DCTRL;                 /*!< SDIO data control register,     Address offset: 0x2C */\n  __IO const uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */\n  __IO const uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */\n  __IO uint32_t ICR;                   /*!< SDIO interrupt clear register,  Address offset: 0x38 */\n  __IO uint32_t MASK;                  /*!< SDIO mask register,             Address offset: 0x3C */\n  uint32_t      RESERVED0[2];          /*!< Reserved, 0x40-0x44                                  */\n  __IO const uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */\n  uint32_t      RESERVED1[13];         /*!< Reserved, 0x4C-0x7C                                  */\n  __IO uint32_t FIFO;                  /*!< SDIO data FIFO register,        Address offset: 0x80 */\n} SDIO_TypeDef;\n\n/**\n  * @brief Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */\n  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */\n  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */\n  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\n  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */\n  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */\n  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */\n  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */\n} SPI_TypeDef;\n\n/**\n  * @brief QUAD Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */\n  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */\n  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */\n  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */\n  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */\n  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */\n  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */\n  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */\n  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */\n  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */\n  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */\n  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */\n  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */\n} QUADSPI_TypeDef;\n\n/**\n  * @brief SPDIFRX Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */\n  __IO uint16_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */\n  uint16_t        RESERVED0;    /*!< Reserved,  0x06                                          */\n  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */\n  __IO uint16_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */\n  uint16_t        RESERVED1;    /*!< Reserved,  0x0E                                          */\n  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */\n  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */\n   __IO uint32_t  DIR;          /*!< Debug Information register,         Address offset: 0x18 */\n  uint16_t        RESERVED2;    /*!< Reserved,  0x1A                                          */\n} SPDIFRX_TypeDef;\n\n/**\n  * @brief TIM\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */\n  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */\n  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */\n  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */\n  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */\n  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\n  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\n  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */\n  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */\n  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */\n  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */\n  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */\n  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */\n  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */\n  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */\n  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */\n  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */\n  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */\n  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */\n  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */\n} TIM_TypeDef;\n\n/**\n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */\n  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */\n  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */\n  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */\n  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */\n  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */\n  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */\n} USART_TypeDef;\n\n/**\n  * @brief Window WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */\n  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */\n  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */\n} WWDG_TypeDef;\n/**\n  * @brief USB_OTG_Core_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */\n  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */\n  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */\n  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */\n  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */\n  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */\n  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */\n  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */\n  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */\n  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */\n  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */\n  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */\n  uint32_t Reserved30[2];             /*!< Reserved                                     030h */\n  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */\n  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */\n  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */\n  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */\n  uint32_t  Reserved6;                /*!< Reserved                                     050h */\n  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */\n  uint32_t  Reserved;                 /*!< Reserved                                     058h */\n  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */\n  uint32_t  Reserved43[40];           /*!< Reserved                                058h-0FFh */\n  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */\n  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                        */\n} USB_OTG_GlobalTypeDef;\n\n/**\n  * @brief USB_OTG_device_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */\n  __IO uint32_t DCTL;            /*!< dev Control Register         804h */\n  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */\n  uint32_t Reserved0C;           /*!< Reserved                     80Ch */\n  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */\n  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */\n  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */\n  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */\n  uint32_t  Reserved20;          /*!< Reserved                     820h */\n  uint32_t Reserved9;            /*!< Reserved                     824h */\n  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */\n  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */\n  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */\n  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */\n  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */\n  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */\n  uint32_t Reserved40;           /*!< dedicated EP mask            840h */\n  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */\n  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */\n  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */\n} USB_OTG_DeviceTypeDef;\n\n/**\n  * @brief USB_OTG_IN_Endpoint-Specific_Register\n  */\ntypedef struct\n{\n  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */\n  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */\n  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */\n  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\n  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\n} USB_OTG_INEndpointTypeDef;\n\n/**\n  * @brief USB_OTG_OUT_Endpoint-Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */\n  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */\n  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */\n  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\n} USB_OTG_OUTEndpointTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Mode_Register_Structures\n  */\ntypedef struct\n{\n  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */\n  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */\n  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */\n  uint32_t Reserved40C;           /*!< Reserved                             40Ch */\n  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */\n  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */\n  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */\n} USB_OTG_HostTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Channel_Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */\n  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */\n  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */\n  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */\n  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */\n  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */\n  uint32_t Reserved[2];           /*!< Reserved                                      */\n} USB_OTG_HostChannelTypeDef;\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_memory_map\n  * @{\n  */\n#define FLASH_BASE            0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region                         */\n#define SRAM1_BASE            0x20000000UL /*!< SRAM1(112 KB) base address in the alias region                              */\n#define SRAM2_BASE            0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region                              */\n#define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */\n#define BKPSRAM_BASE          0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region                         */\n#define FMC_R_BASE            0xA0000000UL /*!< FMC registers base address                                                 */\n#define QSPI_R_BASE           0xA0001000UL /*!< QuadSPI registers base address                                             */\n#define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region                          */\n#define SRAM2_BB_BASE         0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region                           */\n#define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */\n#define BKPSRAM_BB_BASE       0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region                      */\n#define FLASH_END             0x0807FFFFUL /*!< FLASH end address                                                          */\n#define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */\n#define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */\n\n/* Legacy defines */\n#define SRAM_BASE             SRAM1_BASE\n#define SRAM_BB_BASE          SRAM1_BB_BASE\n\n/*!< Peripheral memory map */\n#define APB1PERIPH_BASE       PERIPH_BASE\n#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)\n#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)\n#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)\n\n/*!< APB1 peripherals */\n#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)\n#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)\n#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)\n#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)\n#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)\n#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)\n#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)\n#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)\n#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)\n#define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)\n#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)\n#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)\n#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)\n#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)\n#define SPDIFRX_BASE          (APB1PERIPH_BASE + 0x4000UL)\n#define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)\n#define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)\n#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)\n#define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)\n#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)\n#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)\n#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)\n#define FMPI2C1_BASE          (APB1PERIPH_BASE + 0x6000UL)\n#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)\n#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)\n#define CEC_BASE              (APB1PERIPH_BASE + 0x6C00UL)\n#define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)\n#define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)\n\n/*!< APB2 peripherals */\n#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)\n#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)\n#define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)\n#define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)\n#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)\n#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100UL)\n#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200UL)\n#define ADC123_COMMON_BASE    (APB2PERIPH_BASE + 0x2300UL)\n/* Legacy define */\n#define ADC_BASE               ADC123_COMMON_BASE\n#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)\n#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)\n#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400UL)\n#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)\n#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)\n#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)\n#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)\n#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)\n#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800UL)\n#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)\n#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)\n#define SAI2_BASE             (APB2PERIPH_BASE + 0x5C00UL)\n#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)\n#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)\n\n/*!< AHB1 peripherals */\n#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)\n#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)\n#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)\n#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)\n#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)\n#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)\n#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)\n#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)\n#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)\n#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)\n#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)\n#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)\n#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)\n#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)\n#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)\n#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)\n#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)\n#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)\n#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)\n#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)\n#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)\n#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)\n#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)\n#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)\n#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)\n#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)\n#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)\n#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)\n#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)\n\n/*!< AHB2 peripherals */\n#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000UL)\n\n/*!< FMC Bankx registers base address */\n#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)\n#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)\n#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)\n#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)\n\n\n/*!< Debug MCU registers base address */\n#define DBGMCU_BASE           0xE0042000UL\n/*!< USB registers base address */\n#define USB_OTG_HS_PERIPH_BASE               0x40040000UL\n#define USB_OTG_FS_PERIPH_BASE               0x50000000UL\n\n#define USB_OTG_GLOBAL_BASE                  0x000UL\n#define USB_OTG_DEVICE_BASE                  0x800UL\n#define USB_OTG_IN_ENDPOINT_BASE             0x900UL\n#define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL\n#define USB_OTG_EP_REG_SIZE                  0x20UL\n#define USB_OTG_HOST_BASE                    0x400UL\n#define USB_OTG_HOST_PORT_BASE               0x440UL\n#define USB_OTG_HOST_CHANNEL_BASE            0x500UL\n#define USB_OTG_HOST_CHANNEL_SIZE            0x20UL\n#define USB_OTG_PCGCCTL_BASE                 0xE00UL\n#define USB_OTG_FIFO_BASE                    0x1000UL\n#define USB_OTG_FIFO_SIZE                    0x1000UL\n\n#define UID_BASE                     0x1FFF7A10UL           /*!< Unique device ID register base address */\n#define FLASHSIZE_BASE               0x1FFF7A22UL           /*!< FLASH Size register base address       */\n#define PACKAGE_BASE                 0x1FFF7BF0UL           /*!< Package size register base address     */\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_declaration\n  * @{\n  */\n#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\n#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\n#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\n#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\n#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\n#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\n#define TIM12               ((TIM_TypeDef *) TIM12_BASE)\n#define TIM13               ((TIM_TypeDef *) TIM13_BASE)\n#define TIM14               ((TIM_TypeDef *) TIM14_BASE)\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\n#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\n#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\n#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\n#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\n#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)\n#define USART2              ((USART_TypeDef *) USART2_BASE)\n#define USART3              ((USART_TypeDef *) USART3_BASE)\n#define UART4               ((USART_TypeDef *) UART4_BASE)\n#define UART5               ((USART_TypeDef *) UART5_BASE)\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\n#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\n#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\n#define FMPI2C1             ((FMPI2C_TypeDef *) FMPI2C1_BASE)\n#define CAN1                ((CAN_TypeDef *) CAN1_BASE)\n#define CAN2                ((CAN_TypeDef *) CAN2_BASE)\n#define CEC                 ((CEC_TypeDef *) CEC_BASE)\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\n#define DAC1                ((DAC_TypeDef *) DAC_BASE)\n#define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */\n#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\n#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\n#define USART1              ((USART_TypeDef *) USART1_BASE)\n#define USART6              ((USART_TypeDef *) USART6_BASE)\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\n#define ADC2                ((ADC_TypeDef *) ADC2_BASE)\n#define ADC3                ((ADC_TypeDef *) ADC3_BASE)\n#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)\n/* Legacy define */\n#define ADC                  ADC123_COMMON\n#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\n#define SPI4                ((SPI_TypeDef *) SPI4_BASE)\n#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\n#define TIM9                ((TIM_TypeDef *) TIM9_BASE)\n#define TIM10               ((TIM_TypeDef *) TIM10_BASE)\n#define TIM11               ((TIM_TypeDef *) TIM11_BASE)\n#define SAI1                ((SAI_TypeDef *) SAI1_BASE)\n#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\n#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\n#define SAI2                ((SAI_TypeDef *) SAI2_BASE)\n#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)\n#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\n#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\n#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\n#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)\n#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\n#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\n#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\n#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\n#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\n#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\n#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\n#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\n#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\n#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\n#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\n#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\n#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\n#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\n#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\n#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\n#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\n#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\n#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)\n#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)\n#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)\n#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)\n#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)\n#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)\n#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\n#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\n#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_constants\n  * @{\n  */\n\n  /** @addtogroup Peripheral_Registers_Bits_Definition\n  * @{\n  */\n\n/******************************************************************************/\n/*                         Peripheral Registers_Bits_Definition               */\n/******************************************************************************/\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Analog to Digital Converter                         */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define ADC_MULTIMODE_SUPPORT                                                  /*!<ADC Multimode feature available on specific devices */\n\n/********************  Bit definition for ADC_SR register  ********************/\n#define ADC_SR_AWD_Pos            (0U)\n#define ADC_SR_AWD_Msk            (0x1UL << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */\n#define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */\n#define ADC_SR_EOC_Pos            (1U)\n#define ADC_SR_EOC_Msk            (0x1UL << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */\n#define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */\n#define ADC_SR_JEOC_Pos           (2U)\n#define ADC_SR_JEOC_Msk           (0x1UL << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */\n#define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */\n#define ADC_SR_JSTRT_Pos          (3U)\n#define ADC_SR_JSTRT_Msk          (0x1UL << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */\n#define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */\n#define ADC_SR_STRT_Pos           (4U)\n#define ADC_SR_STRT_Msk           (0x1UL << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */\n#define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */\n#define ADC_SR_OVR_Pos            (5U)\n#define ADC_SR_OVR_Msk            (0x1UL << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */\n#define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */\n\n/*******************  Bit definition for ADC_CR1 register  ********************/\n#define ADC_CR1_AWDCH_Pos         (0U)\n#define ADC_CR1_AWDCH_Msk         (0x1FUL << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */\n#define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\n#define ADC_CR1_AWDCH_0           (0x01UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */\n#define ADC_CR1_AWDCH_1           (0x02UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */\n#define ADC_CR1_AWDCH_2           (0x04UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */\n#define ADC_CR1_AWDCH_3           (0x08UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */\n#define ADC_CR1_AWDCH_4           (0x10UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */\n#define ADC_CR1_EOCIE_Pos         (5U)\n#define ADC_CR1_EOCIE_Msk         (0x1UL << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */\n#define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */\n#define ADC_CR1_AWDIE_Pos         (6U)\n#define ADC_CR1_AWDIE_Msk         (0x1UL << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */\n#define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */\n#define ADC_CR1_JEOCIE_Pos        (7U)\n#define ADC_CR1_JEOCIE_Msk        (0x1UL << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */\n#define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */\n#define ADC_CR1_SCAN_Pos          (8U)\n#define ADC_CR1_SCAN_Msk          (0x1UL << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */\n#define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */\n#define ADC_CR1_AWDSGL_Pos        (9U)\n#define ADC_CR1_AWDSGL_Msk        (0x1UL << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */\n#define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */\n#define ADC_CR1_JAUTO_Pos         (10U)\n#define ADC_CR1_JAUTO_Msk         (0x1UL << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */\n#define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */\n#define ADC_CR1_DISCEN_Pos        (11U)\n#define ADC_CR1_DISCEN_Msk        (0x1UL << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */\n#define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */\n#define ADC_CR1_JDISCEN_Pos       (12U)\n#define ADC_CR1_JDISCEN_Msk       (0x1UL << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */\n#define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */\n#define ADC_CR1_DISCNUM_Pos       (13U)\n#define ADC_CR1_DISCNUM_Msk       (0x7UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */\n#define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\n#define ADC_CR1_DISCNUM_0         (0x1UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */\n#define ADC_CR1_DISCNUM_1         (0x2UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */\n#define ADC_CR1_DISCNUM_2         (0x4UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */\n#define ADC_CR1_JAWDEN_Pos        (22U)\n#define ADC_CR1_JAWDEN_Msk        (0x1UL << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */\n#define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */\n#define ADC_CR1_AWDEN_Pos         (23U)\n#define ADC_CR1_AWDEN_Msk         (0x1UL << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */\n#define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */\n#define ADC_CR1_RES_Pos           (24U)\n#define ADC_CR1_RES_Msk           (0x3UL << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */\n#define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */\n#define ADC_CR1_RES_0             (0x1UL << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */\n#define ADC_CR1_RES_1             (0x2UL << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */\n#define ADC_CR1_OVRIE_Pos         (26U)\n#define ADC_CR1_OVRIE_Msk         (0x1UL << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */\n#define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */\n\n/*******************  Bit definition for ADC_CR2 register  ********************/\n#define ADC_CR2_ADON_Pos          (0U)\n#define ADC_CR2_ADON_Msk          (0x1UL << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */\n#define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */\n#define ADC_CR2_CONT_Pos          (1U)\n#define ADC_CR2_CONT_Msk          (0x1UL << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */\n#define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */\n#define ADC_CR2_DMA_Pos           (8U)\n#define ADC_CR2_DMA_Msk           (0x1UL << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */\n#define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */\n#define ADC_CR2_DDS_Pos           (9U)\n#define ADC_CR2_DDS_Msk           (0x1UL << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */\n#define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */\n#define ADC_CR2_EOCS_Pos          (10U)\n#define ADC_CR2_EOCS_Msk          (0x1UL << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */\n#define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */\n#define ADC_CR2_ALIGN_Pos         (11U)\n#define ADC_CR2_ALIGN_Msk         (0x1UL << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */\n#define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */\n#define ADC_CR2_JEXTSEL_Pos       (16U)\n#define ADC_CR2_JEXTSEL_Msk       (0xFUL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */\n#define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */\n#define ADC_CR2_JEXTSEL_0         (0x1UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */\n#define ADC_CR2_JEXTSEL_1         (0x2UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */\n#define ADC_CR2_JEXTSEL_2         (0x4UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */\n#define ADC_CR2_JEXTSEL_3         (0x8UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */\n#define ADC_CR2_JEXTEN_Pos        (20U)\n#define ADC_CR2_JEXTEN_Msk        (0x3UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */\n#define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\n#define ADC_CR2_JEXTEN_0          (0x1UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */\n#define ADC_CR2_JEXTEN_1          (0x2UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */\n#define ADC_CR2_JSWSTART_Pos      (22U)\n#define ADC_CR2_JSWSTART_Msk      (0x1UL << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */\n#define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */\n#define ADC_CR2_EXTSEL_Pos        (24U)\n#define ADC_CR2_EXTSEL_Msk        (0xFUL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */\n#define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\n#define ADC_CR2_EXTSEL_0          (0x1UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */\n#define ADC_CR2_EXTSEL_1          (0x2UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */\n#define ADC_CR2_EXTSEL_2          (0x4UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */\n#define ADC_CR2_EXTSEL_3          (0x8UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */\n#define ADC_CR2_EXTEN_Pos         (28U)\n#define ADC_CR2_EXTEN_Msk         (0x3UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */\n#define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\n#define ADC_CR2_EXTEN_0           (0x1UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */\n#define ADC_CR2_EXTEN_1           (0x2UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */\n#define ADC_CR2_SWSTART_Pos       (30U)\n#define ADC_CR2_SWSTART_Msk       (0x1UL << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */\n#define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */\n\n/******************  Bit definition for ADC_SMPR1 register  *******************/\n#define ADC_SMPR1_SMP10_Pos       (0U)\n#define ADC_SMPR1_SMP10_Msk       (0x7UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */\n#define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\n#define ADC_SMPR1_SMP10_0         (0x1UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */\n#define ADC_SMPR1_SMP10_1         (0x2UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */\n#define ADC_SMPR1_SMP10_2         (0x4UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */\n#define ADC_SMPR1_SMP11_Pos       (3U)\n#define ADC_SMPR1_SMP11_Msk       (0x7UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */\n#define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\n#define ADC_SMPR1_SMP11_0         (0x1UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */\n#define ADC_SMPR1_SMP11_1         (0x2UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */\n#define ADC_SMPR1_SMP11_2         (0x4UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */\n#define ADC_SMPR1_SMP12_Pos       (6U)\n#define ADC_SMPR1_SMP12_Msk       (0x7UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */\n#define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\n#define ADC_SMPR1_SMP12_0         (0x1UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */\n#define ADC_SMPR1_SMP12_1         (0x2UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */\n#define ADC_SMPR1_SMP12_2         (0x4UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */\n#define ADC_SMPR1_SMP13_Pos       (9U)\n#define ADC_SMPR1_SMP13_Msk       (0x7UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */\n#define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\n#define ADC_SMPR1_SMP13_0         (0x1UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */\n#define ADC_SMPR1_SMP13_1         (0x2UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */\n#define ADC_SMPR1_SMP13_2         (0x4UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */\n#define ADC_SMPR1_SMP14_Pos       (12U)\n#define ADC_SMPR1_SMP14_Msk       (0x7UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */\n#define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\n#define ADC_SMPR1_SMP14_0         (0x1UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */\n#define ADC_SMPR1_SMP14_1         (0x2UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */\n#define ADC_SMPR1_SMP14_2         (0x4UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */\n#define ADC_SMPR1_SMP15_Pos       (15U)\n#define ADC_SMPR1_SMP15_Msk       (0x7UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */\n#define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\n#define ADC_SMPR1_SMP15_0         (0x1UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */\n#define ADC_SMPR1_SMP15_1         (0x2UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */\n#define ADC_SMPR1_SMP15_2         (0x4UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */\n#define ADC_SMPR1_SMP16_Pos       (18U)\n#define ADC_SMPR1_SMP16_Msk       (0x7UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */\n#define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\n#define ADC_SMPR1_SMP16_0         (0x1UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */\n#define ADC_SMPR1_SMP16_1         (0x2UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */\n#define ADC_SMPR1_SMP16_2         (0x4UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */\n#define ADC_SMPR1_SMP17_Pos       (21U)\n#define ADC_SMPR1_SMP17_Msk       (0x7UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */\n#define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\n#define ADC_SMPR1_SMP17_0         (0x1UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */\n#define ADC_SMPR1_SMP17_1         (0x2UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */\n#define ADC_SMPR1_SMP17_2         (0x4UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */\n#define ADC_SMPR1_SMP18_Pos       (24U)\n#define ADC_SMPR1_SMP18_Msk       (0x7UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */\n#define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\n#define ADC_SMPR1_SMP18_0         (0x1UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */\n#define ADC_SMPR1_SMP18_1         (0x2UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */\n#define ADC_SMPR1_SMP18_2         (0x4UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */\n\n/******************  Bit definition for ADC_SMPR2 register  *******************/\n#define ADC_SMPR2_SMP0_Pos        (0U)\n#define ADC_SMPR2_SMP0_Msk        (0x7UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */\n#define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\n#define ADC_SMPR2_SMP0_0          (0x1UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */\n#define ADC_SMPR2_SMP0_1          (0x2UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */\n#define ADC_SMPR2_SMP0_2          (0x4UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */\n#define ADC_SMPR2_SMP1_Pos        (3U)\n#define ADC_SMPR2_SMP1_Msk        (0x7UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */\n#define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\n#define ADC_SMPR2_SMP1_0          (0x1UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */\n#define ADC_SMPR2_SMP1_1          (0x2UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */\n#define ADC_SMPR2_SMP1_2          (0x4UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */\n#define ADC_SMPR2_SMP2_Pos        (6U)\n#define ADC_SMPR2_SMP2_Msk        (0x7UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */\n#define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\n#define ADC_SMPR2_SMP2_0          (0x1UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */\n#define ADC_SMPR2_SMP2_1          (0x2UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */\n#define ADC_SMPR2_SMP2_2          (0x4UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */\n#define ADC_SMPR2_SMP3_Pos        (9U)\n#define ADC_SMPR2_SMP3_Msk        (0x7UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */\n#define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\n#define ADC_SMPR2_SMP3_0          (0x1UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */\n#define ADC_SMPR2_SMP3_1          (0x2UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */\n#define ADC_SMPR2_SMP3_2          (0x4UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */\n#define ADC_SMPR2_SMP4_Pos        (12U)\n#define ADC_SMPR2_SMP4_Msk        (0x7UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */\n#define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\n#define ADC_SMPR2_SMP4_0          (0x1UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */\n#define ADC_SMPR2_SMP4_1          (0x2UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */\n#define ADC_SMPR2_SMP4_2          (0x4UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */\n#define ADC_SMPR2_SMP5_Pos        (15U)\n#define ADC_SMPR2_SMP5_Msk        (0x7UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */\n#define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\n#define ADC_SMPR2_SMP5_0          (0x1UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */\n#define ADC_SMPR2_SMP5_1          (0x2UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */\n#define ADC_SMPR2_SMP5_2          (0x4UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */\n#define ADC_SMPR2_SMP6_Pos        (18U)\n#define ADC_SMPR2_SMP6_Msk        (0x7UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */\n#define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\n#define ADC_SMPR2_SMP6_0          (0x1UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */\n#define ADC_SMPR2_SMP6_1          (0x2UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */\n#define ADC_SMPR2_SMP6_2          (0x4UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */\n#define ADC_SMPR2_SMP7_Pos        (21U)\n#define ADC_SMPR2_SMP7_Msk        (0x7UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */\n#define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\n#define ADC_SMPR2_SMP7_0          (0x1UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */\n#define ADC_SMPR2_SMP7_1          (0x2UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */\n#define ADC_SMPR2_SMP7_2          (0x4UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */\n#define ADC_SMPR2_SMP8_Pos        (24U)\n#define ADC_SMPR2_SMP8_Msk        (0x7UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */\n#define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\n#define ADC_SMPR2_SMP8_0          (0x1UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */\n#define ADC_SMPR2_SMP8_1          (0x2UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */\n#define ADC_SMPR2_SMP8_2          (0x4UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */\n#define ADC_SMPR2_SMP9_Pos        (27U)\n#define ADC_SMPR2_SMP9_Msk        (0x7UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */\n#define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\n#define ADC_SMPR2_SMP9_0          (0x1UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */\n#define ADC_SMPR2_SMP9_1          (0x2UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */\n#define ADC_SMPR2_SMP9_2          (0x4UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */\n\n/******************  Bit definition for ADC_JOFR1 register  *******************/\n#define ADC_JOFR1_JOFFSET1_Pos    (0U)\n#define ADC_JOFR1_JOFFSET1_Msk    (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */\n\n/******************  Bit definition for ADC_JOFR2 register  *******************/\n#define ADC_JOFR2_JOFFSET2_Pos    (0U)\n#define ADC_JOFR2_JOFFSET2_Msk    (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */\n\n/******************  Bit definition for ADC_JOFR3 register  *******************/\n#define ADC_JOFR3_JOFFSET3_Pos    (0U)\n#define ADC_JOFR3_JOFFSET3_Msk    (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */\n\n/******************  Bit definition for ADC_JOFR4 register  *******************/\n#define ADC_JOFR4_JOFFSET4_Pos    (0U)\n#define ADC_JOFR4_JOFFSET4_Msk    (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */\n\n/*******************  Bit definition for ADC_HTR register  ********************/\n#define ADC_HTR_HT_Pos            (0U)\n#define ADC_HTR_HT_Msk            (0xFFFUL << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */\n#define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */\n\n/*******************  Bit definition for ADC_LTR register  ********************/\n#define ADC_LTR_LT_Pos            (0U)\n#define ADC_LTR_LT_Msk            (0xFFFUL << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */\n#define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */\n\n/*******************  Bit definition for ADC_SQR1 register  *******************/\n#define ADC_SQR1_SQ13_Pos         (0U)\n#define ADC_SQR1_SQ13_Msk         (0x1FUL << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */\n#define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\n#define ADC_SQR1_SQ13_0           (0x01UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */\n#define ADC_SQR1_SQ13_1           (0x02UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */\n#define ADC_SQR1_SQ13_2           (0x04UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */\n#define ADC_SQR1_SQ13_3           (0x08UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */\n#define ADC_SQR1_SQ13_4           (0x10UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */\n#define ADC_SQR1_SQ14_Pos         (5U)\n#define ADC_SQR1_SQ14_Msk         (0x1FUL << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */\n#define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\n#define ADC_SQR1_SQ14_0           (0x01UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */\n#define ADC_SQR1_SQ14_1           (0x02UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */\n#define ADC_SQR1_SQ14_2           (0x04UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */\n#define ADC_SQR1_SQ14_3           (0x08UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */\n#define ADC_SQR1_SQ14_4           (0x10UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */\n#define ADC_SQR1_SQ15_Pos         (10U)\n#define ADC_SQR1_SQ15_Msk         (0x1FUL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */\n#define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\n#define ADC_SQR1_SQ15_0           (0x01UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */\n#define ADC_SQR1_SQ15_1           (0x02UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */\n#define ADC_SQR1_SQ15_2           (0x04UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */\n#define ADC_SQR1_SQ15_3           (0x08UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */\n#define ADC_SQR1_SQ15_4           (0x10UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */\n#define ADC_SQR1_SQ16_Pos         (15U)\n#define ADC_SQR1_SQ16_Msk         (0x1FUL << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\n#define ADC_SQR1_SQ16_0           (0x01UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR1_SQ16_1           (0x02UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR1_SQ16_2           (0x04UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR1_SQ16_3           (0x08UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR1_SQ16_4           (0x10UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR1_L_Pos            (20U)\n#define ADC_SQR1_L_Msk            (0xFUL << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */\n#define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */\n#define ADC_SQR1_L_0              (0x1UL << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */\n#define ADC_SQR1_L_1              (0x2UL << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */\n#define ADC_SQR1_L_2              (0x4UL << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */\n#define ADC_SQR1_L_3              (0x8UL << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */\n\n/*******************  Bit definition for ADC_SQR2 register  *******************/\n#define ADC_SQR2_SQ7_Pos          (0U)\n#define ADC_SQR2_SQ7_Msk          (0x1FUL << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\n#define ADC_SQR2_SQ7_0            (0x01UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR2_SQ7_1            (0x02UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR2_SQ7_2            (0x04UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR2_SQ7_3            (0x08UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR2_SQ7_4            (0x10UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR2_SQ8_Pos          (5U)\n#define ADC_SQR2_SQ8_Msk          (0x1FUL << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\n#define ADC_SQR2_SQ8_0            (0x01UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR2_SQ8_1            (0x02UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR2_SQ8_2            (0x04UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR2_SQ8_3            (0x08UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR2_SQ8_4            (0x10UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR2_SQ9_Pos          (10U)\n#define ADC_SQR2_SQ9_Msk          (0x1FUL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\n#define ADC_SQR2_SQ9_0            (0x01UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR2_SQ9_1            (0x02UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR2_SQ9_2            (0x04UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR2_SQ9_3            (0x08UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR2_SQ9_4            (0x10UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR2_SQ10_Pos         (15U)\n#define ADC_SQR2_SQ10_Msk         (0x1FUL << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\n#define ADC_SQR2_SQ10_0           (0x01UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR2_SQ10_1           (0x02UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR2_SQ10_2           (0x04UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR2_SQ10_3           (0x08UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR2_SQ10_4           (0x10UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR2_SQ11_Pos         (20U)\n#define ADC_SQR2_SQ11_Msk         (0x1FUL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */\n#define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\n#define ADC_SQR2_SQ11_0           (0x01UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */\n#define ADC_SQR2_SQ11_1           (0x02UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */\n#define ADC_SQR2_SQ11_2           (0x04UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */\n#define ADC_SQR2_SQ11_3           (0x08UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */\n#define ADC_SQR2_SQ11_4           (0x10UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */\n#define ADC_SQR2_SQ12_Pos         (25U)\n#define ADC_SQR2_SQ12_Msk         (0x1FUL << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */\n#define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\n#define ADC_SQR2_SQ12_0           (0x01UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */\n#define ADC_SQR2_SQ12_1           (0x02UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */\n#define ADC_SQR2_SQ12_2           (0x04UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */\n#define ADC_SQR2_SQ12_3           (0x08UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */\n#define ADC_SQR2_SQ12_4           (0x10UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_SQR3 register  *******************/\n#define ADC_SQR3_SQ1_Pos          (0U)\n#define ADC_SQR3_SQ1_Msk          (0x1FUL << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\n#define ADC_SQR3_SQ1_0            (0x01UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR3_SQ1_1            (0x02UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR3_SQ1_2            (0x04UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR3_SQ1_3            (0x08UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR3_SQ1_4            (0x10UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR3_SQ2_Pos          (5U)\n#define ADC_SQR3_SQ2_Msk          (0x1FUL << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\n#define ADC_SQR3_SQ2_0            (0x01UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR3_SQ2_1            (0x02UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR3_SQ2_2            (0x04UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR3_SQ2_3            (0x08UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR3_SQ2_4            (0x10UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR3_SQ3_Pos          (10U)\n#define ADC_SQR3_SQ3_Msk          (0x1FUL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\n#define ADC_SQR3_SQ3_0            (0x01UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR3_SQ3_1            (0x02UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR3_SQ3_2            (0x04UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR3_SQ3_3            (0x08UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR3_SQ3_4            (0x10UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR3_SQ4_Pos          (15U)\n#define ADC_SQR3_SQ4_Msk          (0x1FUL << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */\n#define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\n#define ADC_SQR3_SQ4_0            (0x01UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */\n#define ADC_SQR3_SQ4_1            (0x02UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */\n#define ADC_SQR3_SQ4_2            (0x04UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */\n#define ADC_SQR3_SQ4_3            (0x08UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */\n#define ADC_SQR3_SQ4_4            (0x10UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */\n#define ADC_SQR3_SQ5_Pos          (20U)\n#define ADC_SQR3_SQ5_Msk          (0x1FUL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */\n#define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\n#define ADC_SQR3_SQ5_0            (0x01UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */\n#define ADC_SQR3_SQ5_1            (0x02UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */\n#define ADC_SQR3_SQ5_2            (0x04UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */\n#define ADC_SQR3_SQ5_3            (0x08UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */\n#define ADC_SQR3_SQ5_4            (0x10UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */\n#define ADC_SQR3_SQ6_Pos          (25U)\n#define ADC_SQR3_SQ6_Msk          (0x1FUL << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */\n#define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\n#define ADC_SQR3_SQ6_0            (0x01UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */\n#define ADC_SQR3_SQ6_1            (0x02UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */\n#define ADC_SQR3_SQ6_2            (0x04UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */\n#define ADC_SQR3_SQ6_3            (0x08UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */\n#define ADC_SQR3_SQ6_4            (0x10UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_JSQR register  *******************/\n#define ADC_JSQR_JSQ1_Pos         (0U)\n#define ADC_JSQR_JSQ1_Msk         (0x1FUL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */\n#define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */\n#define ADC_JSQR_JSQ1_0           (0x01UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */\n#define ADC_JSQR_JSQ1_1           (0x02UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */\n#define ADC_JSQR_JSQ1_2           (0x04UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */\n#define ADC_JSQR_JSQ1_3           (0x08UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */\n#define ADC_JSQR_JSQ1_4           (0x10UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */\n#define ADC_JSQR_JSQ2_Pos         (5U)\n#define ADC_JSQR_JSQ2_Msk         (0x1FUL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */\n#define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\n#define ADC_JSQR_JSQ2_0           (0x01UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */\n#define ADC_JSQR_JSQ2_1           (0x02UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */\n#define ADC_JSQR_JSQ2_2           (0x04UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */\n#define ADC_JSQR_JSQ2_3           (0x08UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */\n#define ADC_JSQR_JSQ2_4           (0x10UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */\n#define ADC_JSQR_JSQ3_Pos         (10U)\n#define ADC_JSQR_JSQ3_Msk         (0x1FUL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */\n#define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\n#define ADC_JSQR_JSQ3_0           (0x01UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */\n#define ADC_JSQR_JSQ3_1           (0x02UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */\n#define ADC_JSQR_JSQ3_2           (0x04UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */\n#define ADC_JSQR_JSQ3_3           (0x08UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */\n#define ADC_JSQR_JSQ3_4           (0x10UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */\n#define ADC_JSQR_JSQ4_Pos         (15U)\n#define ADC_JSQR_JSQ4_Msk         (0x1FUL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */\n#define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\n#define ADC_JSQR_JSQ4_0           (0x01UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */\n#define ADC_JSQR_JSQ4_1           (0x02UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */\n#define ADC_JSQR_JSQ4_2           (0x04UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */\n#define ADC_JSQR_JSQ4_3           (0x08UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */\n#define ADC_JSQR_JSQ4_4           (0x10UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */\n#define ADC_JSQR_JL_Pos           (20U)\n#define ADC_JSQR_JL_Msk           (0x3UL << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */\n#define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */\n#define ADC_JSQR_JL_0             (0x1UL << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */\n#define ADC_JSQR_JL_1             (0x2UL << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */\n\n/*******************  Bit definition for ADC_JDR1 register  *******************/\n#define ADC_JDR1_JDATA_Pos        (0U)\n#define ADC_JDR1_JDATA_Msk        (0xFFFFUL << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR2 register  *******************/\n#define ADC_JDR2_JDATA_Pos        (0U)\n#define ADC_JDR2_JDATA_Msk        (0xFFFFUL << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR3 register  *******************/\n#define ADC_JDR3_JDATA_Pos        (0U)\n#define ADC_JDR3_JDATA_Msk        (0xFFFFUL << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR4 register  *******************/\n#define ADC_JDR4_JDATA_Pos        (0U)\n#define ADC_JDR4_JDATA_Msk        (0xFFFFUL << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */\n\n/********************  Bit definition for ADC_DR register  ********************/\n#define ADC_DR_DATA_Pos           (0U)\n#define ADC_DR_DATA_Msk           (0xFFFFUL << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */\n#define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */\n#define ADC_DR_ADC2DATA_Pos       (16U)\n#define ADC_DR_ADC2DATA_Msk       (0xFFFFUL << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */\n#define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */\n\n/*******************  Bit definition for ADC_CSR register  ********************/\n#define ADC_CSR_AWD1_Pos          (0U)\n#define ADC_CSR_AWD1_Msk          (0x1UL << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */\n#define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */\n#define ADC_CSR_EOC1_Pos          (1U)\n#define ADC_CSR_EOC1_Msk          (0x1UL << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */\n#define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */\n#define ADC_CSR_JEOC1_Pos         (2U)\n#define ADC_CSR_JEOC1_Msk         (0x1UL << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */\n#define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */\n#define ADC_CSR_JSTRT1_Pos        (3U)\n#define ADC_CSR_JSTRT1_Msk        (0x1UL << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */\n#define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */\n#define ADC_CSR_STRT1_Pos         (4U)\n#define ADC_CSR_STRT1_Msk         (0x1UL << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */\n#define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */\n#define ADC_CSR_OVR1_Pos          (5U)\n#define ADC_CSR_OVR1_Msk          (0x1UL << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */\n#define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */\n#define ADC_CSR_AWD2_Pos          (8U)\n#define ADC_CSR_AWD2_Msk          (0x1UL << ADC_CSR_AWD2_Pos)                   /*!< 0x00000100 */\n#define ADC_CSR_AWD2              ADC_CSR_AWD2_Msk                             /*!<ADC2 Analog watchdog flag */\n#define ADC_CSR_EOC2_Pos          (9U)\n#define ADC_CSR_EOC2_Msk          (0x1UL << ADC_CSR_EOC2_Pos)                   /*!< 0x00000200 */\n#define ADC_CSR_EOC2              ADC_CSR_EOC2_Msk                             /*!<ADC2 End of conversion */\n#define ADC_CSR_JEOC2_Pos         (10U)\n#define ADC_CSR_JEOC2_Msk         (0x1UL << ADC_CSR_JEOC2_Pos)                  /*!< 0x00000400 */\n#define ADC_CSR_JEOC2             ADC_CSR_JEOC2_Msk                            /*!<ADC2 Injected channel end of conversion */\n#define ADC_CSR_JSTRT2_Pos        (11U)\n#define ADC_CSR_JSTRT2_Msk        (0x1UL << ADC_CSR_JSTRT2_Pos)                 /*!< 0x00000800 */\n#define ADC_CSR_JSTRT2            ADC_CSR_JSTRT2_Msk                           /*!<ADC2 Injected channel Start flag */\n#define ADC_CSR_STRT2_Pos         (12U)\n#define ADC_CSR_STRT2_Msk         (0x1UL << ADC_CSR_STRT2_Pos)                  /*!< 0x00001000 */\n#define ADC_CSR_STRT2             ADC_CSR_STRT2_Msk                            /*!<ADC2 Regular channel Start flag */\n#define ADC_CSR_OVR2_Pos          (13U)\n#define ADC_CSR_OVR2_Msk          (0x1UL << ADC_CSR_OVR2_Pos)                   /*!< 0x00002000 */\n#define ADC_CSR_OVR2              ADC_CSR_OVR2_Msk                             /*!<ADC2 DMA overrun  flag */\n#define ADC_CSR_AWD3_Pos          (16U)\n#define ADC_CSR_AWD3_Msk          (0x1UL << ADC_CSR_AWD3_Pos)                   /*!< 0x00010000 */\n#define ADC_CSR_AWD3              ADC_CSR_AWD3_Msk                             /*!<ADC3 Analog watchdog flag */\n#define ADC_CSR_EOC3_Pos          (17U)\n#define ADC_CSR_EOC3_Msk          (0x1UL << ADC_CSR_EOC3_Pos)                   /*!< 0x00020000 */\n#define ADC_CSR_EOC3              ADC_CSR_EOC3_Msk                             /*!<ADC3 End of conversion */\n#define ADC_CSR_JEOC3_Pos         (18U)\n#define ADC_CSR_JEOC3_Msk         (0x1UL << ADC_CSR_JEOC3_Pos)                  /*!< 0x00040000 */\n#define ADC_CSR_JEOC3             ADC_CSR_JEOC3_Msk                            /*!<ADC3 Injected channel end of conversion */\n#define ADC_CSR_JSTRT3_Pos        (19U)\n#define ADC_CSR_JSTRT3_Msk        (0x1UL << ADC_CSR_JSTRT3_Pos)                 /*!< 0x00080000 */\n#define ADC_CSR_JSTRT3            ADC_CSR_JSTRT3_Msk                           /*!<ADC3 Injected channel Start flag */\n#define ADC_CSR_STRT3_Pos         (20U)\n#define ADC_CSR_STRT3_Msk         (0x1UL << ADC_CSR_STRT3_Pos)                  /*!< 0x00100000 */\n#define ADC_CSR_STRT3             ADC_CSR_STRT3_Msk                            /*!<ADC3 Regular channel Start flag */\n#define ADC_CSR_OVR3_Pos          (21U)\n#define ADC_CSR_OVR3_Msk          (0x1UL << ADC_CSR_OVR3_Pos)                   /*!< 0x00200000 */\n#define ADC_CSR_OVR3              ADC_CSR_OVR3_Msk                             /*!<ADC3 DMA overrun  flag */\n\n/* Legacy defines */\n#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1\n#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2\n#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3\n\n/*******************  Bit definition for ADC_CCR register  ********************/\n#define ADC_CCR_MULTI_Pos         (0U)\n#define ADC_CCR_MULTI_Msk         (0x1FUL << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */\n#define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */\n#define ADC_CCR_MULTI_0           (0x01UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */\n#define ADC_CCR_MULTI_1           (0x02UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */\n#define ADC_CCR_MULTI_2           (0x04UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */\n#define ADC_CCR_MULTI_3           (0x08UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */\n#define ADC_CCR_MULTI_4           (0x10UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */\n#define ADC_CCR_DELAY_Pos         (8U)\n#define ADC_CCR_DELAY_Msk         (0xFUL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */\n#define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */\n#define ADC_CCR_DELAY_0           (0x1UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */\n#define ADC_CCR_DELAY_1           (0x2UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */\n#define ADC_CCR_DELAY_2           (0x4UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */\n#define ADC_CCR_DELAY_3           (0x8UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */\n#define ADC_CCR_DDS_Pos           (13U)\n#define ADC_CCR_DDS_Msk           (0x1UL << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */\n#define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */\n#define ADC_CCR_DMA_Pos           (14U)\n#define ADC_CCR_DMA_Msk           (0x3UL << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */\n#define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */\n#define ADC_CCR_DMA_0             (0x1UL << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */\n#define ADC_CCR_DMA_1             (0x2UL << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */\n#define ADC_CCR_ADCPRE_Pos        (16U)\n#define ADC_CCR_ADCPRE_Msk        (0x3UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */\n#define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */\n#define ADC_CCR_ADCPRE_0          (0x1UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */\n#define ADC_CCR_ADCPRE_1          (0x2UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */\n#define ADC_CCR_VBATE_Pos         (22U)\n#define ADC_CCR_VBATE_Msk         (0x1UL << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */\n#define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */\n#define ADC_CCR_TSVREFE_Pos       (23U)\n#define ADC_CCR_TSVREFE_Msk       (0x1UL << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */\n#define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */\n\n/*******************  Bit definition for ADC_CDR register  ********************/\n#define ADC_CDR_DATA1_Pos         (0U)\n#define ADC_CDR_DATA1_Msk         (0xFFFFUL << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */\n#define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */\n#define ADC_CDR_DATA2_Pos         (16U)\n#define ADC_CDR_DATA2_Msk         (0xFFFFUL << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */\n#define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */\n\n/* Legacy defines */\n#define ADC_CDR_RDATA_MST         ADC_CDR_DATA1\n#define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Controller Area Network                            */\n/*                                                                            */\n/******************************************************************************/\n/*!<CAN control and status registers */\n/*******************  Bit definition for CAN_MCR register  ********************/\n#define CAN_MCR_INRQ_Pos       (0U)\n#define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */\n#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */\n#define CAN_MCR_SLEEP_Pos      (1U)\n#define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */\n#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */\n#define CAN_MCR_TXFP_Pos       (2U)\n#define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */\n#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */\n#define CAN_MCR_RFLM_Pos       (3U)\n#define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */\n#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */\n#define CAN_MCR_NART_Pos       (4U)\n#define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */\n#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */\n#define CAN_MCR_AWUM_Pos       (5U)\n#define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */\n#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */\n#define CAN_MCR_ABOM_Pos       (6U)\n#define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */\n#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */\n#define CAN_MCR_TTCM_Pos       (7U)\n#define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */\n#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */\n#define CAN_MCR_RESET_Pos      (15U)\n#define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */\n#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */\n#define CAN_MCR_DBF_Pos        (16U)\n#define CAN_MCR_DBF_Msk        (0x1UL << CAN_MCR_DBF_Pos)                       /*!< 0x00010000 */\n#define CAN_MCR_DBF            CAN_MCR_DBF_Msk                                 /*!<bxCAN Debug freeze */\n/*******************  Bit definition for CAN_MSR register  ********************/\n#define CAN_MSR_INAK_Pos       (0U)\n#define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */\n#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */\n#define CAN_MSR_SLAK_Pos       (1U)\n#define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */\n#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */\n#define CAN_MSR_ERRI_Pos       (2U)\n#define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */\n#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */\n#define CAN_MSR_WKUI_Pos       (3U)\n#define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */\n#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */\n#define CAN_MSR_SLAKI_Pos      (4U)\n#define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */\n#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */\n#define CAN_MSR_TXM_Pos        (8U)\n#define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */\n#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */\n#define CAN_MSR_RXM_Pos        (9U)\n#define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */\n#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */\n#define CAN_MSR_SAMP_Pos       (10U)\n#define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */\n#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */\n#define CAN_MSR_RX_Pos         (11U)\n#define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */\n#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */\n\n/*******************  Bit definition for CAN_TSR register  ********************/\n#define CAN_TSR_RQCP0_Pos      (0U)\n#define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */\n#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */\n#define CAN_TSR_TXOK0_Pos      (1U)\n#define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */\n#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */\n#define CAN_TSR_ALST0_Pos      (2U)\n#define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */\n#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */\n#define CAN_TSR_TERR0_Pos      (3U)\n#define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */\n#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */\n#define CAN_TSR_ABRQ0_Pos      (7U)\n#define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */\n#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */\n#define CAN_TSR_RQCP1_Pos      (8U)\n#define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */\n#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */\n#define CAN_TSR_TXOK1_Pos      (9U)\n#define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */\n#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */\n#define CAN_TSR_ALST1_Pos      (10U)\n#define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */\n#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */\n#define CAN_TSR_TERR1_Pos      (11U)\n#define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */\n#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */\n#define CAN_TSR_ABRQ1_Pos      (15U)\n#define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */\n#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */\n#define CAN_TSR_RQCP2_Pos      (16U)\n#define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */\n#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */\n#define CAN_TSR_TXOK2_Pos      (17U)\n#define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */\n#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */\n#define CAN_TSR_ALST2_Pos      (18U)\n#define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */\n#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */\n#define CAN_TSR_TERR2_Pos      (19U)\n#define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */\n#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */\n#define CAN_TSR_ABRQ2_Pos      (23U)\n#define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */\n#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */\n#define CAN_TSR_CODE_Pos       (24U)\n#define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */\n#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */\n\n#define CAN_TSR_TME_Pos        (26U)\n#define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */\n#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */\n#define CAN_TSR_TME0_Pos       (26U)\n#define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */\n#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */\n#define CAN_TSR_TME1_Pos       (27U)\n#define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */\n#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */\n#define CAN_TSR_TME2_Pos       (28U)\n#define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */\n#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */\n\n#define CAN_TSR_LOW_Pos        (29U)\n#define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */\n#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */\n#define CAN_TSR_LOW0_Pos       (29U)\n#define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */\n#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */\n#define CAN_TSR_LOW1_Pos       (30U)\n#define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */\n#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */\n#define CAN_TSR_LOW2_Pos       (31U)\n#define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */\n#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */\n\n/*******************  Bit definition for CAN_RF0R register  *******************/\n#define CAN_RF0R_FMP0_Pos      (0U)\n#define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */\n#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */\n#define CAN_RF0R_FULL0_Pos     (3U)\n#define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */\n#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */\n#define CAN_RF0R_FOVR0_Pos     (4U)\n#define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */\n#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */\n#define CAN_RF0R_RFOM0_Pos     (5U)\n#define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */\n#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */\n\n/*******************  Bit definition for CAN_RF1R register  *******************/\n#define CAN_RF1R_FMP1_Pos      (0U)\n#define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */\n#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */\n#define CAN_RF1R_FULL1_Pos     (3U)\n#define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */\n#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */\n#define CAN_RF1R_FOVR1_Pos     (4U)\n#define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */\n#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */\n#define CAN_RF1R_RFOM1_Pos     (5U)\n#define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */\n#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */\n\n/********************  Bit definition for CAN_IER register  *******************/\n#define CAN_IER_TMEIE_Pos      (0U)\n#define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */\n#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */\n#define CAN_IER_FMPIE0_Pos     (1U)\n#define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */\n#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE0_Pos      (2U)\n#define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */\n#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE0_Pos     (3U)\n#define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */\n#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_FMPIE1_Pos     (4U)\n#define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */\n#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE1_Pos      (5U)\n#define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */\n#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE1_Pos     (6U)\n#define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */\n#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)\n#define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */\n#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */\n#define CAN_IER_EPVIE_Pos      (9U)\n#define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */\n#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */\n#define CAN_IER_BOFIE_Pos      (10U)\n#define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */\n#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */\n#define CAN_IER_LECIE_Pos      (11U)\n#define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */\n#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */\n#define CAN_IER_ERRIE_Pos      (15U)\n#define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */\n#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */\n#define CAN_IER_WKUIE_Pos      (16U)\n#define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */\n#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */\n#define CAN_IER_SLKIE_Pos      (17U)\n#define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */\n#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)\n\n/********************  Bit definition for CAN_ESR register  *******************/\n#define CAN_ESR_EWGF_Pos       (0U)\n#define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */\n#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */\n#define CAN_ESR_EPVF_Pos       (1U)\n#define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */\n#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */\n#define CAN_ESR_BOFF_Pos       (2U)\n#define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */\n#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */\n\n#define CAN_ESR_LEC_Pos        (4U)\n#define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */\n#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */\n#define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */\n#define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */\n#define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */\n\n#define CAN_ESR_TEC_Pos        (16U)\n#define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */\n#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */\n#define CAN_ESR_REC_Pos        (24U)\n#define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */\n#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */\n\n/*******************  Bit definition for CAN_BTR register  ********************/\n#define CAN_BTR_BRP_Pos        (0U)\n#define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */\n#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */\n#define CAN_BTR_TS1_Pos        (16U)\n#define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */\n#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */\n#define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */\n#define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */\n#define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */\n#define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */\n#define CAN_BTR_TS2_Pos        (20U)\n#define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */\n#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */\n#define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */\n#define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */\n#define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */\n#define CAN_BTR_SJW_Pos        (24U)\n#define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */\n#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */\n#define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */\n#define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */\n#define CAN_BTR_LBKM_Pos       (30U)\n#define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */\n#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */\n#define CAN_BTR_SILM_Pos       (31U)\n#define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */\n#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */\n\n\n/*!<Mailbox registers */\n/******************  Bit definition for CAN_TI0R register  ********************/\n#define CAN_TI0R_TXRQ_Pos      (0U)\n#define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI0R_RTR_Pos       (1U)\n#define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI0R_IDE_Pos       (2U)\n#define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI0R_EXID_Pos      (3U)\n#define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI0R_STID_Pos      (21U)\n#define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/******************  Bit definition for CAN_TDT0R register  *******************/\n#define CAN_TDT0R_DLC_Pos      (0U)\n#define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT0R_TGT_Pos      (8U)\n#define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT0R_TIME_Pos     (16U)\n#define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/******************  Bit definition for CAN_TDL0R register  *******************/\n#define CAN_TDL0R_DATA0_Pos    (0U)\n#define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL0R_DATA1_Pos    (8U)\n#define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL0R_DATA2_Pos    (16U)\n#define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL0R_DATA3_Pos    (24U)\n#define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/******************  Bit definition for CAN_TDH0R register  *******************/\n#define CAN_TDH0R_DATA4_Pos    (0U)\n#define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH0R_DATA5_Pos    (8U)\n#define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH0R_DATA6_Pos    (16U)\n#define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH0R_DATA7_Pos    (24U)\n#define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI1R register  *******************/\n#define CAN_TI1R_TXRQ_Pos      (0U)\n#define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI1R_RTR_Pos       (1U)\n#define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI1R_IDE_Pos       (2U)\n#define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI1R_EXID_Pos      (3U)\n#define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI1R_STID_Pos      (21U)\n#define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT1R register  ******************/\n#define CAN_TDT1R_DLC_Pos      (0U)\n#define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT1R_TGT_Pos      (8U)\n#define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT1R_TIME_Pos     (16U)\n#define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL1R register  ******************/\n#define CAN_TDL1R_DATA0_Pos    (0U)\n#define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL1R_DATA1_Pos    (8U)\n#define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL1R_DATA2_Pos    (16U)\n#define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL1R_DATA3_Pos    (24U)\n#define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH1R register  ******************/\n#define CAN_TDH1R_DATA4_Pos    (0U)\n#define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH1R_DATA5_Pos    (8U)\n#define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH1R_DATA6_Pos    (16U)\n#define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH1R_DATA7_Pos    (24U)\n#define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI2R register  *******************/\n#define CAN_TI2R_TXRQ_Pos      (0U)\n#define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI2R_RTR_Pos       (1U)\n#define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI2R_IDE_Pos       (2U)\n#define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI2R_EXID_Pos      (3U)\n#define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_TI2R_STID_Pos      (21U)\n#define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT2R register  ******************/\n#define CAN_TDT2R_DLC_Pos      (0U)\n#define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT2R_TGT_Pos      (8U)\n#define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT2R_TIME_Pos     (16U)\n#define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL2R register  ******************/\n#define CAN_TDL2R_DATA0_Pos    (0U)\n#define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL2R_DATA1_Pos    (8U)\n#define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL2R_DATA2_Pos    (16U)\n#define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL2R_DATA3_Pos    (24U)\n#define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH2R register  ******************/\n#define CAN_TDH2R_DATA4_Pos    (0U)\n#define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH2R_DATA5_Pos    (8U)\n#define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH2R_DATA6_Pos    (16U)\n#define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH2R_DATA7_Pos    (24U)\n#define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI0R register  *******************/\n#define CAN_RI0R_RTR_Pos       (1U)\n#define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI0R_IDE_Pos       (2U)\n#define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI0R_EXID_Pos      (3U)\n#define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_RI0R_STID_Pos      (21U)\n#define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT0R register  ******************/\n#define CAN_RDT0R_DLC_Pos      (0U)\n#define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT0R_FMI_Pos      (8U)\n#define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT0R_TIME_Pos     (16U)\n#define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL0R register  ******************/\n#define CAN_RDL0R_DATA0_Pos    (0U)\n#define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL0R_DATA1_Pos    (8U)\n#define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL0R_DATA2_Pos    (16U)\n#define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL0R_DATA3_Pos    (24U)\n#define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH0R register  ******************/\n#define CAN_RDH0R_DATA4_Pos    (0U)\n#define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH0R_DATA5_Pos    (8U)\n#define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH0R_DATA6_Pos    (16U)\n#define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH0R_DATA7_Pos    (24U)\n#define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI1R register  *******************/\n#define CAN_RI1R_RTR_Pos       (1U)\n#define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI1R_IDE_Pos       (2U)\n#define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI1R_EXID_Pos      (3U)\n#define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_RI1R_STID_Pos      (21U)\n#define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT1R register  ******************/\n#define CAN_RDT1R_DLC_Pos      (0U)\n#define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT1R_FMI_Pos      (8U)\n#define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT1R_TIME_Pos     (16U)\n#define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL1R register  ******************/\n#define CAN_RDL1R_DATA0_Pos    (0U)\n#define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL1R_DATA1_Pos    (8U)\n#define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL1R_DATA2_Pos    (16U)\n#define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL1R_DATA3_Pos    (24U)\n#define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH1R register  ******************/\n#define CAN_RDH1R_DATA4_Pos    (0U)\n#define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH1R_DATA5_Pos    (8U)\n#define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH1R_DATA6_Pos    (16U)\n#define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH1R_DATA7_Pos    (24U)\n#define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*!<CAN filter registers */\n/*******************  Bit definition for CAN_FMR register  ********************/\n#define CAN_FMR_FINIT_Pos      (0U)\n#define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */\n#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */\n#define CAN_FMR_CAN2SB_Pos     (8U)\n#define CAN_FMR_CAN2SB_Msk     (0x3FUL << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */\n#define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */\n\n/*******************  Bit definition for CAN_FM1R register  *******************/\n#define CAN_FM1R_FBM_Pos       (0U)\n#define CAN_FM1R_FBM_Msk       (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */\n#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */\n#define CAN_FM1R_FBM0_Pos      (0U)\n#define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */\n#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */\n#define CAN_FM1R_FBM1_Pos      (1U)\n#define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */\n#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */\n#define CAN_FM1R_FBM2_Pos      (2U)\n#define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */\n#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */\n#define CAN_FM1R_FBM3_Pos      (3U)\n#define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */\n#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */\n#define CAN_FM1R_FBM4_Pos      (4U)\n#define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */\n#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */\n#define CAN_FM1R_FBM5_Pos      (5U)\n#define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */\n#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */\n#define CAN_FM1R_FBM6_Pos      (6U)\n#define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */\n#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */\n#define CAN_FM1R_FBM7_Pos      (7U)\n#define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */\n#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */\n#define CAN_FM1R_FBM8_Pos      (8U)\n#define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */\n#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */\n#define CAN_FM1R_FBM9_Pos      (9U)\n#define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */\n#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */\n#define CAN_FM1R_FBM10_Pos     (10U)\n#define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */\n#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */\n#define CAN_FM1R_FBM11_Pos     (11U)\n#define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */\n#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */\n#define CAN_FM1R_FBM12_Pos     (12U)\n#define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */\n#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */\n#define CAN_FM1R_FBM13_Pos     (13U)\n#define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */\n#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */\n#define CAN_FM1R_FBM14_Pos     (14U)\n#define CAN_FM1R_FBM14_Msk     (0x1UL << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */\n#define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */\n#define CAN_FM1R_FBM15_Pos     (15U)\n#define CAN_FM1R_FBM15_Msk     (0x1UL << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */\n#define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */\n#define CAN_FM1R_FBM16_Pos     (16U)\n#define CAN_FM1R_FBM16_Msk     (0x1UL << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */\n#define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */\n#define CAN_FM1R_FBM17_Pos     (17U)\n#define CAN_FM1R_FBM17_Msk     (0x1UL << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */\n#define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */\n#define CAN_FM1R_FBM18_Pos     (18U)\n#define CAN_FM1R_FBM18_Msk     (0x1UL << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */\n#define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */\n#define CAN_FM1R_FBM19_Pos     (19U)\n#define CAN_FM1R_FBM19_Msk     (0x1UL << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */\n#define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */\n#define CAN_FM1R_FBM20_Pos     (20U)\n#define CAN_FM1R_FBM20_Msk     (0x1UL << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */\n#define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */\n#define CAN_FM1R_FBM21_Pos     (21U)\n#define CAN_FM1R_FBM21_Msk     (0x1UL << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */\n#define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */\n#define CAN_FM1R_FBM22_Pos     (22U)\n#define CAN_FM1R_FBM22_Msk     (0x1UL << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */\n#define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */\n#define CAN_FM1R_FBM23_Pos     (23U)\n#define CAN_FM1R_FBM23_Msk     (0x1UL << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */\n#define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */\n#define CAN_FM1R_FBM24_Pos     (24U)\n#define CAN_FM1R_FBM24_Msk     (0x1UL << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */\n#define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */\n#define CAN_FM1R_FBM25_Pos     (25U)\n#define CAN_FM1R_FBM25_Msk     (0x1UL << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */\n#define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */\n#define CAN_FM1R_FBM26_Pos     (26U)\n#define CAN_FM1R_FBM26_Msk     (0x1UL << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */\n#define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */\n#define CAN_FM1R_FBM27_Pos     (27U)\n#define CAN_FM1R_FBM27_Msk     (0x1UL << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */\n#define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */\n\n/*******************  Bit definition for CAN_FS1R register  *******************/\n#define CAN_FS1R_FSC_Pos       (0U)\n#define CAN_FS1R_FSC_Msk       (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */\n#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */\n#define CAN_FS1R_FSC0_Pos      (0U)\n#define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */\n#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */\n#define CAN_FS1R_FSC1_Pos      (1U)\n#define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */\n#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */\n#define CAN_FS1R_FSC2_Pos      (2U)\n#define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */\n#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */\n#define CAN_FS1R_FSC3_Pos      (3U)\n#define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */\n#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */\n#define CAN_FS1R_FSC4_Pos      (4U)\n#define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */\n#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */\n#define CAN_FS1R_FSC5_Pos      (5U)\n#define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */\n#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */\n#define CAN_FS1R_FSC6_Pos      (6U)\n#define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */\n#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */\n#define CAN_FS1R_FSC7_Pos      (7U)\n#define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */\n#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */\n#define CAN_FS1R_FSC8_Pos      (8U)\n#define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */\n#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */\n#define CAN_FS1R_FSC9_Pos      (9U)\n#define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */\n#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */\n#define CAN_FS1R_FSC10_Pos     (10U)\n#define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */\n#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */\n#define CAN_FS1R_FSC11_Pos     (11U)\n#define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */\n#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */\n#define CAN_FS1R_FSC12_Pos     (12U)\n#define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */\n#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */\n#define CAN_FS1R_FSC13_Pos     (13U)\n#define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */\n#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */\n#define CAN_FS1R_FSC14_Pos     (14U)\n#define CAN_FS1R_FSC14_Msk     (0x1UL << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */\n#define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */\n#define CAN_FS1R_FSC15_Pos     (15U)\n#define CAN_FS1R_FSC15_Msk     (0x1UL << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */\n#define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */\n#define CAN_FS1R_FSC16_Pos     (16U)\n#define CAN_FS1R_FSC16_Msk     (0x1UL << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */\n#define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */\n#define CAN_FS1R_FSC17_Pos     (17U)\n#define CAN_FS1R_FSC17_Msk     (0x1UL << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */\n#define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */\n#define CAN_FS1R_FSC18_Pos     (18U)\n#define CAN_FS1R_FSC18_Msk     (0x1UL << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */\n#define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */\n#define CAN_FS1R_FSC19_Pos     (19U)\n#define CAN_FS1R_FSC19_Msk     (0x1UL << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */\n#define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */\n#define CAN_FS1R_FSC20_Pos     (20U)\n#define CAN_FS1R_FSC20_Msk     (0x1UL << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */\n#define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */\n#define CAN_FS1R_FSC21_Pos     (21U)\n#define CAN_FS1R_FSC21_Msk     (0x1UL << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */\n#define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */\n#define CAN_FS1R_FSC22_Pos     (22U)\n#define CAN_FS1R_FSC22_Msk     (0x1UL << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */\n#define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */\n#define CAN_FS1R_FSC23_Pos     (23U)\n#define CAN_FS1R_FSC23_Msk     (0x1UL << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */\n#define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */\n#define CAN_FS1R_FSC24_Pos     (24U)\n#define CAN_FS1R_FSC24_Msk     (0x1UL << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */\n#define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */\n#define CAN_FS1R_FSC25_Pos     (25U)\n#define CAN_FS1R_FSC25_Msk     (0x1UL << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */\n#define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */\n#define CAN_FS1R_FSC26_Pos     (26U)\n#define CAN_FS1R_FSC26_Msk     (0x1UL << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */\n#define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */\n#define CAN_FS1R_FSC27_Pos     (27U)\n#define CAN_FS1R_FSC27_Msk     (0x1UL << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */\n#define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */\n\n/******************  Bit definition for CAN_FFA1R register  *******************/\n#define CAN_FFA1R_FFA_Pos      (0U)\n#define CAN_FFA1R_FFA_Msk      (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */\n#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */\n#define CAN_FFA1R_FFA0_Pos     (0U)\n#define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */\n#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */\n#define CAN_FFA1R_FFA1_Pos     (1U)\n#define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */\n#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */\n#define CAN_FFA1R_FFA2_Pos     (2U)\n#define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */\n#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */\n#define CAN_FFA1R_FFA3_Pos     (3U)\n#define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */\n#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */\n#define CAN_FFA1R_FFA4_Pos     (4U)\n#define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */\n#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */\n#define CAN_FFA1R_FFA5_Pos     (5U)\n#define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */\n#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */\n#define CAN_FFA1R_FFA6_Pos     (6U)\n#define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */\n#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */\n#define CAN_FFA1R_FFA7_Pos     (7U)\n#define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */\n#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */\n#define CAN_FFA1R_FFA8_Pos     (8U)\n#define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */\n#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */\n#define CAN_FFA1R_FFA9_Pos     (9U)\n#define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */\n#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */\n#define CAN_FFA1R_FFA10_Pos    (10U)\n#define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */\n#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */\n#define CAN_FFA1R_FFA11_Pos    (11U)\n#define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */\n#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */\n#define CAN_FFA1R_FFA12_Pos    (12U)\n#define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */\n#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */\n#define CAN_FFA1R_FFA13_Pos    (13U)\n#define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */\n#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */\n#define CAN_FFA1R_FFA14_Pos    (14U)\n#define CAN_FFA1R_FFA14_Msk    (0x1UL << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */\n#define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */\n#define CAN_FFA1R_FFA15_Pos    (15U)\n#define CAN_FFA1R_FFA15_Msk    (0x1UL << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */\n#define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */\n#define CAN_FFA1R_FFA16_Pos    (16U)\n#define CAN_FFA1R_FFA16_Msk    (0x1UL << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */\n#define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */\n#define CAN_FFA1R_FFA17_Pos    (17U)\n#define CAN_FFA1R_FFA17_Msk    (0x1UL << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */\n#define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */\n#define CAN_FFA1R_FFA18_Pos    (18U)\n#define CAN_FFA1R_FFA18_Msk    (0x1UL << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */\n#define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */\n#define CAN_FFA1R_FFA19_Pos    (19U)\n#define CAN_FFA1R_FFA19_Msk    (0x1UL << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */\n#define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */\n#define CAN_FFA1R_FFA20_Pos    (20U)\n#define CAN_FFA1R_FFA20_Msk    (0x1UL << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */\n#define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */\n#define CAN_FFA1R_FFA21_Pos    (21U)\n#define CAN_FFA1R_FFA21_Msk    (0x1UL << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */\n#define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */\n#define CAN_FFA1R_FFA22_Pos    (22U)\n#define CAN_FFA1R_FFA22_Msk    (0x1UL << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */\n#define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */\n#define CAN_FFA1R_FFA23_Pos    (23U)\n#define CAN_FFA1R_FFA23_Msk    (0x1UL << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */\n#define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */\n#define CAN_FFA1R_FFA24_Pos    (24U)\n#define CAN_FFA1R_FFA24_Msk    (0x1UL << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */\n#define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */\n#define CAN_FFA1R_FFA25_Pos    (25U)\n#define CAN_FFA1R_FFA25_Msk    (0x1UL << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */\n#define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */\n#define CAN_FFA1R_FFA26_Pos    (26U)\n#define CAN_FFA1R_FFA26_Msk    (0x1UL << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */\n#define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */\n#define CAN_FFA1R_FFA27_Pos    (27U)\n#define CAN_FFA1R_FFA27_Msk    (0x1UL << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */\n#define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */\n\n/*******************  Bit definition for CAN_FA1R register  *******************/\n#define CAN_FA1R_FACT_Pos      (0U)\n#define CAN_FA1R_FACT_Msk      (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */\n#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */\n#define CAN_FA1R_FACT0_Pos     (0U)\n#define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */\n#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */\n#define CAN_FA1R_FACT1_Pos     (1U)\n#define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */\n#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */\n#define CAN_FA1R_FACT2_Pos     (2U)\n#define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */\n#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */\n#define CAN_FA1R_FACT3_Pos     (3U)\n#define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */\n#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */\n#define CAN_FA1R_FACT4_Pos     (4U)\n#define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */\n#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */\n#define CAN_FA1R_FACT5_Pos     (5U)\n#define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */\n#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */\n#define CAN_FA1R_FACT6_Pos     (6U)\n#define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */\n#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */\n#define CAN_FA1R_FACT7_Pos     (7U)\n#define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */\n#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */\n#define CAN_FA1R_FACT8_Pos     (8U)\n#define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */\n#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */\n#define CAN_FA1R_FACT9_Pos     (9U)\n#define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */\n#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */\n#define CAN_FA1R_FACT10_Pos    (10U)\n#define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */\n#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */\n#define CAN_FA1R_FACT11_Pos    (11U)\n#define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */\n#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */\n#define CAN_FA1R_FACT12_Pos    (12U)\n#define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */\n#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */\n#define CAN_FA1R_FACT13_Pos    (13U)\n#define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */\n#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */\n#define CAN_FA1R_FACT14_Pos    (14U)\n#define CAN_FA1R_FACT14_Msk    (0x1UL << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */\n#define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */\n#define CAN_FA1R_FACT15_Pos    (15U)\n#define CAN_FA1R_FACT15_Msk    (0x1UL << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */\n#define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */\n#define CAN_FA1R_FACT16_Pos    (16U)\n#define CAN_FA1R_FACT16_Msk    (0x1UL << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */\n#define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */\n#define CAN_FA1R_FACT17_Pos    (17U)\n#define CAN_FA1R_FACT17_Msk    (0x1UL << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */\n#define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */\n#define CAN_FA1R_FACT18_Pos    (18U)\n#define CAN_FA1R_FACT18_Msk    (0x1UL << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */\n#define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */\n#define CAN_FA1R_FACT19_Pos    (19U)\n#define CAN_FA1R_FACT19_Msk    (0x1UL << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */\n#define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */\n#define CAN_FA1R_FACT20_Pos    (20U)\n#define CAN_FA1R_FACT20_Msk    (0x1UL << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */\n#define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */\n#define CAN_FA1R_FACT21_Pos    (21U)\n#define CAN_FA1R_FACT21_Msk    (0x1UL << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */\n#define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */\n#define CAN_FA1R_FACT22_Pos    (22U)\n#define CAN_FA1R_FACT22_Msk    (0x1UL << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */\n#define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */\n#define CAN_FA1R_FACT23_Pos    (23U)\n#define CAN_FA1R_FACT23_Msk    (0x1UL << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */\n#define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */\n#define CAN_FA1R_FACT24_Pos    (24U)\n#define CAN_FA1R_FACT24_Msk    (0x1UL << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */\n#define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */\n#define CAN_FA1R_FACT25_Pos    (25U)\n#define CAN_FA1R_FACT25_Msk    (0x1UL << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */\n#define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */\n#define CAN_FA1R_FACT26_Pos    (26U)\n#define CAN_FA1R_FACT26_Msk    (0x1UL << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */\n#define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */\n#define CAN_FA1R_FACT27_Pos    (27U)\n#define CAN_FA1R_FACT27_Msk    (0x1UL << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */\n#define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */\n\n\n/*******************  Bit definition for CAN_F0R1 register  *******************/\n#define CAN_F0R1_FB0_Pos       (0U)\n#define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R1_FB1_Pos       (1U)\n#define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R1_FB2_Pos       (2U)\n#define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R1_FB3_Pos       (3U)\n#define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R1_FB4_Pos       (4U)\n#define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R1_FB5_Pos       (5U)\n#define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R1_FB6_Pos       (6U)\n#define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R1_FB7_Pos       (7U)\n#define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R1_FB8_Pos       (8U)\n#define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R1_FB9_Pos       (9U)\n#define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R1_FB10_Pos      (10U)\n#define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R1_FB11_Pos      (11U)\n#define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R1_FB12_Pos      (12U)\n#define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R1_FB13_Pos      (13U)\n#define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R1_FB14_Pos      (14U)\n#define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R1_FB15_Pos      (15U)\n#define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R1_FB16_Pos      (16U)\n#define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R1_FB17_Pos      (17U)\n#define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R1_FB18_Pos      (18U)\n#define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R1_FB19_Pos      (19U)\n#define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R1_FB20_Pos      (20U)\n#define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R1_FB21_Pos      (21U)\n#define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R1_FB22_Pos      (22U)\n#define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R1_FB23_Pos      (23U)\n#define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R1_FB24_Pos      (24U)\n#define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R1_FB25_Pos      (25U)\n#define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R1_FB26_Pos      (26U)\n#define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R1_FB27_Pos      (27U)\n#define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R1_FB28_Pos      (28U)\n#define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R1_FB29_Pos      (29U)\n#define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R1_FB30_Pos      (30U)\n#define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R1_FB31_Pos      (31U)\n#define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R1 register  *******************/\n#define CAN_F1R1_FB0_Pos       (0U)\n#define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R1_FB1_Pos       (1U)\n#define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R1_FB2_Pos       (2U)\n#define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R1_FB3_Pos       (3U)\n#define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R1_FB4_Pos       (4U)\n#define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R1_FB5_Pos       (5U)\n#define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R1_FB6_Pos       (6U)\n#define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R1_FB7_Pos       (7U)\n#define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R1_FB8_Pos       (8U)\n#define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R1_FB9_Pos       (9U)\n#define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R1_FB10_Pos      (10U)\n#define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R1_FB11_Pos      (11U)\n#define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R1_FB12_Pos      (12U)\n#define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R1_FB13_Pos      (13U)\n#define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R1_FB14_Pos      (14U)\n#define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R1_FB15_Pos      (15U)\n#define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R1_FB16_Pos      (16U)\n#define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R1_FB17_Pos      (17U)\n#define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R1_FB18_Pos      (18U)\n#define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R1_FB19_Pos      (19U)\n#define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R1_FB20_Pos      (20U)\n#define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R1_FB21_Pos      (21U)\n#define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R1_FB22_Pos      (22U)\n#define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R1_FB23_Pos      (23U)\n#define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R1_FB24_Pos      (24U)\n#define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R1_FB25_Pos      (25U)\n#define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R1_FB26_Pos      (26U)\n#define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R1_FB27_Pos      (27U)\n#define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R1_FB28_Pos      (28U)\n#define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R1_FB29_Pos      (29U)\n#define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R1_FB30_Pos      (30U)\n#define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R1_FB31_Pos      (31U)\n#define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R1 register  *******************/\n#define CAN_F2R1_FB0_Pos       (0U)\n#define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R1_FB1_Pos       (1U)\n#define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R1_FB2_Pos       (2U)\n#define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R1_FB3_Pos       (3U)\n#define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R1_FB4_Pos       (4U)\n#define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R1_FB5_Pos       (5U)\n#define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R1_FB6_Pos       (6U)\n#define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R1_FB7_Pos       (7U)\n#define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R1_FB8_Pos       (8U)\n#define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R1_FB9_Pos       (9U)\n#define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R1_FB10_Pos      (10U)\n#define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R1_FB11_Pos      (11U)\n#define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R1_FB12_Pos      (12U)\n#define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R1_FB13_Pos      (13U)\n#define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R1_FB14_Pos      (14U)\n#define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R1_FB15_Pos      (15U)\n#define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R1_FB16_Pos      (16U)\n#define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R1_FB17_Pos      (17U)\n#define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R1_FB18_Pos      (18U)\n#define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R1_FB19_Pos      (19U)\n#define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R1_FB20_Pos      (20U)\n#define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R1_FB21_Pos      (21U)\n#define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R1_FB22_Pos      (22U)\n#define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R1_FB23_Pos      (23U)\n#define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R1_FB24_Pos      (24U)\n#define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R1_FB25_Pos      (25U)\n#define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R1_FB26_Pos      (26U)\n#define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R1_FB27_Pos      (27U)\n#define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R1_FB28_Pos      (28U)\n#define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R1_FB29_Pos      (29U)\n#define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R1_FB30_Pos      (30U)\n#define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R1_FB31_Pos      (31U)\n#define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R1 register  *******************/\n#define CAN_F3R1_FB0_Pos       (0U)\n#define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R1_FB1_Pos       (1U)\n#define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R1_FB2_Pos       (2U)\n#define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R1_FB3_Pos       (3U)\n#define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R1_FB4_Pos       (4U)\n#define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R1_FB5_Pos       (5U)\n#define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R1_FB6_Pos       (6U)\n#define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R1_FB7_Pos       (7U)\n#define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R1_FB8_Pos       (8U)\n#define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R1_FB9_Pos       (9U)\n#define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R1_FB10_Pos      (10U)\n#define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R1_FB11_Pos      (11U)\n#define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R1_FB12_Pos      (12U)\n#define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R1_FB13_Pos      (13U)\n#define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R1_FB14_Pos      (14U)\n#define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R1_FB15_Pos      (15U)\n#define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R1_FB16_Pos      (16U)\n#define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R1_FB17_Pos      (17U)\n#define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R1_FB18_Pos      (18U)\n#define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R1_FB19_Pos      (19U)\n#define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R1_FB20_Pos      (20U)\n#define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R1_FB21_Pos      (21U)\n#define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R1_FB22_Pos      (22U)\n#define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R1_FB23_Pos      (23U)\n#define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R1_FB24_Pos      (24U)\n#define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R1_FB25_Pos      (25U)\n#define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R1_FB26_Pos      (26U)\n#define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R1_FB27_Pos      (27U)\n#define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R1_FB28_Pos      (28U)\n#define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R1_FB29_Pos      (29U)\n#define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R1_FB30_Pos      (30U)\n#define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R1_FB31_Pos      (31U)\n#define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R1 register  *******************/\n#define CAN_F4R1_FB0_Pos       (0U)\n#define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R1_FB1_Pos       (1U)\n#define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R1_FB2_Pos       (2U)\n#define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R1_FB3_Pos       (3U)\n#define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R1_FB4_Pos       (4U)\n#define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R1_FB5_Pos       (5U)\n#define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R1_FB6_Pos       (6U)\n#define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R1_FB7_Pos       (7U)\n#define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R1_FB8_Pos       (8U)\n#define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R1_FB9_Pos       (9U)\n#define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R1_FB10_Pos      (10U)\n#define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R1_FB11_Pos      (11U)\n#define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R1_FB12_Pos      (12U)\n#define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R1_FB13_Pos      (13U)\n#define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R1_FB14_Pos      (14U)\n#define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R1_FB15_Pos      (15U)\n#define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R1_FB16_Pos      (16U)\n#define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R1_FB17_Pos      (17U)\n#define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R1_FB18_Pos      (18U)\n#define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R1_FB19_Pos      (19U)\n#define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R1_FB20_Pos      (20U)\n#define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R1_FB21_Pos      (21U)\n#define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R1_FB22_Pos      (22U)\n#define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R1_FB23_Pos      (23U)\n#define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R1_FB24_Pos      (24U)\n#define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R1_FB25_Pos      (25U)\n#define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R1_FB26_Pos      (26U)\n#define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R1_FB27_Pos      (27U)\n#define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R1_FB28_Pos      (28U)\n#define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R1_FB29_Pos      (29U)\n#define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R1_FB30_Pos      (30U)\n#define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R1_FB31_Pos      (31U)\n#define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R1 register  *******************/\n#define CAN_F5R1_FB0_Pos       (0U)\n#define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R1_FB1_Pos       (1U)\n#define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R1_FB2_Pos       (2U)\n#define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R1_FB3_Pos       (3U)\n#define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R1_FB4_Pos       (4U)\n#define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R1_FB5_Pos       (5U)\n#define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R1_FB6_Pos       (6U)\n#define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R1_FB7_Pos       (7U)\n#define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R1_FB8_Pos       (8U)\n#define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R1_FB9_Pos       (9U)\n#define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R1_FB10_Pos      (10U)\n#define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R1_FB11_Pos      (11U)\n#define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R1_FB12_Pos      (12U)\n#define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R1_FB13_Pos      (13U)\n#define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R1_FB14_Pos      (14U)\n#define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R1_FB15_Pos      (15U)\n#define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R1_FB16_Pos      (16U)\n#define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R1_FB17_Pos      (17U)\n#define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R1_FB18_Pos      (18U)\n#define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R1_FB19_Pos      (19U)\n#define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R1_FB20_Pos      (20U)\n#define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R1_FB21_Pos      (21U)\n#define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R1_FB22_Pos      (22U)\n#define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R1_FB23_Pos      (23U)\n#define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R1_FB24_Pos      (24U)\n#define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R1_FB25_Pos      (25U)\n#define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R1_FB26_Pos      (26U)\n#define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R1_FB27_Pos      (27U)\n#define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R1_FB28_Pos      (28U)\n#define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R1_FB29_Pos      (29U)\n#define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R1_FB30_Pos      (30U)\n#define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R1_FB31_Pos      (31U)\n#define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R1 register  *******************/\n#define CAN_F6R1_FB0_Pos       (0U)\n#define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R1_FB1_Pos       (1U)\n#define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R1_FB2_Pos       (2U)\n#define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R1_FB3_Pos       (3U)\n#define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R1_FB4_Pos       (4U)\n#define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R1_FB5_Pos       (5U)\n#define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R1_FB6_Pos       (6U)\n#define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R1_FB7_Pos       (7U)\n#define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R1_FB8_Pos       (8U)\n#define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R1_FB9_Pos       (9U)\n#define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R1_FB10_Pos      (10U)\n#define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R1_FB11_Pos      (11U)\n#define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R1_FB12_Pos      (12U)\n#define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R1_FB13_Pos      (13U)\n#define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R1_FB14_Pos      (14U)\n#define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R1_FB15_Pos      (15U)\n#define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R1_FB16_Pos      (16U)\n#define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R1_FB17_Pos      (17U)\n#define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R1_FB18_Pos      (18U)\n#define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R1_FB19_Pos      (19U)\n#define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R1_FB20_Pos      (20U)\n#define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R1_FB21_Pos      (21U)\n#define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R1_FB22_Pos      (22U)\n#define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R1_FB23_Pos      (23U)\n#define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R1_FB24_Pos      (24U)\n#define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R1_FB25_Pos      (25U)\n#define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R1_FB26_Pos      (26U)\n#define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R1_FB27_Pos      (27U)\n#define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R1_FB28_Pos      (28U)\n#define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R1_FB29_Pos      (29U)\n#define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R1_FB30_Pos      (30U)\n#define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R1_FB31_Pos      (31U)\n#define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R1 register  *******************/\n#define CAN_F7R1_FB0_Pos       (0U)\n#define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R1_FB1_Pos       (1U)\n#define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R1_FB2_Pos       (2U)\n#define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R1_FB3_Pos       (3U)\n#define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R1_FB4_Pos       (4U)\n#define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R1_FB5_Pos       (5U)\n#define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R1_FB6_Pos       (6U)\n#define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R1_FB7_Pos       (7U)\n#define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R1_FB8_Pos       (8U)\n#define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R1_FB9_Pos       (9U)\n#define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R1_FB10_Pos      (10U)\n#define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R1_FB11_Pos      (11U)\n#define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R1_FB12_Pos      (12U)\n#define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R1_FB13_Pos      (13U)\n#define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R1_FB14_Pos      (14U)\n#define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R1_FB15_Pos      (15U)\n#define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R1_FB16_Pos      (16U)\n#define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R1_FB17_Pos      (17U)\n#define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R1_FB18_Pos      (18U)\n#define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R1_FB19_Pos      (19U)\n#define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R1_FB20_Pos      (20U)\n#define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R1_FB21_Pos      (21U)\n#define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R1_FB22_Pos      (22U)\n#define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R1_FB23_Pos      (23U)\n#define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R1_FB24_Pos      (24U)\n#define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R1_FB25_Pos      (25U)\n#define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R1_FB26_Pos      (26U)\n#define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R1_FB27_Pos      (27U)\n#define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R1_FB28_Pos      (28U)\n#define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R1_FB29_Pos      (29U)\n#define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R1_FB30_Pos      (30U)\n#define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R1_FB31_Pos      (31U)\n#define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R1 register  *******************/\n#define CAN_F8R1_FB0_Pos       (0U)\n#define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R1_FB1_Pos       (1U)\n#define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R1_FB2_Pos       (2U)\n#define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R1_FB3_Pos       (3U)\n#define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R1_FB4_Pos       (4U)\n#define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R1_FB5_Pos       (5U)\n#define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R1_FB6_Pos       (6U)\n#define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R1_FB7_Pos       (7U)\n#define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R1_FB8_Pos       (8U)\n#define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R1_FB9_Pos       (9U)\n#define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R1_FB10_Pos      (10U)\n#define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R1_FB11_Pos      (11U)\n#define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R1_FB12_Pos      (12U)\n#define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R1_FB13_Pos      (13U)\n#define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R1_FB14_Pos      (14U)\n#define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R1_FB15_Pos      (15U)\n#define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R1_FB16_Pos      (16U)\n#define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R1_FB17_Pos      (17U)\n#define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R1_FB18_Pos      (18U)\n#define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R1_FB19_Pos      (19U)\n#define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R1_FB20_Pos      (20U)\n#define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R1_FB21_Pos      (21U)\n#define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R1_FB22_Pos      (22U)\n#define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R1_FB23_Pos      (23U)\n#define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R1_FB24_Pos      (24U)\n#define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R1_FB25_Pos      (25U)\n#define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R1_FB26_Pos      (26U)\n#define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R1_FB27_Pos      (27U)\n#define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R1_FB28_Pos      (28U)\n#define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R1_FB29_Pos      (29U)\n#define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R1_FB30_Pos      (30U)\n#define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R1_FB31_Pos      (31U)\n#define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R1 register  *******************/\n#define CAN_F9R1_FB0_Pos       (0U)\n#define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R1_FB1_Pos       (1U)\n#define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R1_FB2_Pos       (2U)\n#define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R1_FB3_Pos       (3U)\n#define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R1_FB4_Pos       (4U)\n#define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R1_FB5_Pos       (5U)\n#define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R1_FB6_Pos       (6U)\n#define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R1_FB7_Pos       (7U)\n#define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R1_FB8_Pos       (8U)\n#define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R1_FB9_Pos       (9U)\n#define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R1_FB10_Pos      (10U)\n#define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R1_FB11_Pos      (11U)\n#define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R1_FB12_Pos      (12U)\n#define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R1_FB13_Pos      (13U)\n#define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R1_FB14_Pos      (14U)\n#define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R1_FB15_Pos      (15U)\n#define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R1_FB16_Pos      (16U)\n#define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R1_FB17_Pos      (17U)\n#define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R1_FB18_Pos      (18U)\n#define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R1_FB19_Pos      (19U)\n#define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R1_FB20_Pos      (20U)\n#define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R1_FB21_Pos      (21U)\n#define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R1_FB22_Pos      (22U)\n#define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R1_FB23_Pos      (23U)\n#define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R1_FB24_Pos      (24U)\n#define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R1_FB25_Pos      (25U)\n#define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R1_FB26_Pos      (26U)\n#define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R1_FB27_Pos      (27U)\n#define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R1_FB28_Pos      (28U)\n#define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R1_FB29_Pos      (29U)\n#define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R1_FB30_Pos      (30U)\n#define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R1_FB31_Pos      (31U)\n#define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R1 register  ******************/\n#define CAN_F10R1_FB0_Pos      (0U)\n#define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R1_FB1_Pos      (1U)\n#define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R1_FB2_Pos      (2U)\n#define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R1_FB3_Pos      (3U)\n#define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R1_FB4_Pos      (4U)\n#define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R1_FB5_Pos      (5U)\n#define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R1_FB6_Pos      (6U)\n#define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R1_FB7_Pos      (7U)\n#define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R1_FB8_Pos      (8U)\n#define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R1_FB9_Pos      (9U)\n#define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R1_FB10_Pos     (10U)\n#define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R1_FB11_Pos     (11U)\n#define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R1_FB12_Pos     (12U)\n#define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R1_FB13_Pos     (13U)\n#define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R1_FB14_Pos     (14U)\n#define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R1_FB15_Pos     (15U)\n#define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R1_FB16_Pos     (16U)\n#define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R1_FB17_Pos     (17U)\n#define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R1_FB18_Pos     (18U)\n#define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R1_FB19_Pos     (19U)\n#define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R1_FB20_Pos     (20U)\n#define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R1_FB21_Pos     (21U)\n#define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R1_FB22_Pos     (22U)\n#define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R1_FB23_Pos     (23U)\n#define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R1_FB24_Pos     (24U)\n#define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R1_FB25_Pos     (25U)\n#define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R1_FB26_Pos     (26U)\n#define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R1_FB27_Pos     (27U)\n#define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R1_FB28_Pos     (28U)\n#define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R1_FB29_Pos     (29U)\n#define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R1_FB30_Pos     (30U)\n#define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R1_FB31_Pos     (31U)\n#define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R1 register  ******************/\n#define CAN_F11R1_FB0_Pos      (0U)\n#define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R1_FB1_Pos      (1U)\n#define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R1_FB2_Pos      (2U)\n#define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R1_FB3_Pos      (3U)\n#define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R1_FB4_Pos      (4U)\n#define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R1_FB5_Pos      (5U)\n#define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R1_FB6_Pos      (6U)\n#define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R1_FB7_Pos      (7U)\n#define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R1_FB8_Pos      (8U)\n#define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R1_FB9_Pos      (9U)\n#define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R1_FB10_Pos     (10U)\n#define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R1_FB11_Pos     (11U)\n#define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R1_FB12_Pos     (12U)\n#define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R1_FB13_Pos     (13U)\n#define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R1_FB14_Pos     (14U)\n#define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R1_FB15_Pos     (15U)\n#define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R1_FB16_Pos     (16U)\n#define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R1_FB17_Pos     (17U)\n#define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R1_FB18_Pos     (18U)\n#define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R1_FB19_Pos     (19U)\n#define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R1_FB20_Pos     (20U)\n#define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R1_FB21_Pos     (21U)\n#define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R1_FB22_Pos     (22U)\n#define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R1_FB23_Pos     (23U)\n#define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R1_FB24_Pos     (24U)\n#define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R1_FB25_Pos     (25U)\n#define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R1_FB26_Pos     (26U)\n#define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R1_FB27_Pos     (27U)\n#define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R1_FB28_Pos     (28U)\n#define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R1_FB29_Pos     (29U)\n#define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R1_FB30_Pos     (30U)\n#define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R1_FB31_Pos     (31U)\n#define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R1 register  ******************/\n#define CAN_F12R1_FB0_Pos      (0U)\n#define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R1_FB1_Pos      (1U)\n#define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R1_FB2_Pos      (2U)\n#define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R1_FB3_Pos      (3U)\n#define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R1_FB4_Pos      (4U)\n#define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R1_FB5_Pos      (5U)\n#define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R1_FB6_Pos      (6U)\n#define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R1_FB7_Pos      (7U)\n#define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R1_FB8_Pos      (8U)\n#define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R1_FB9_Pos      (9U)\n#define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R1_FB10_Pos     (10U)\n#define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R1_FB11_Pos     (11U)\n#define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R1_FB12_Pos     (12U)\n#define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R1_FB13_Pos     (13U)\n#define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R1_FB14_Pos     (14U)\n#define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R1_FB15_Pos     (15U)\n#define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R1_FB16_Pos     (16U)\n#define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R1_FB17_Pos     (17U)\n#define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R1_FB18_Pos     (18U)\n#define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R1_FB19_Pos     (19U)\n#define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R1_FB20_Pos     (20U)\n#define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R1_FB21_Pos     (21U)\n#define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R1_FB22_Pos     (22U)\n#define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R1_FB23_Pos     (23U)\n#define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R1_FB24_Pos     (24U)\n#define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R1_FB25_Pos     (25U)\n#define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R1_FB26_Pos     (26U)\n#define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R1_FB27_Pos     (27U)\n#define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R1_FB28_Pos     (28U)\n#define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R1_FB29_Pos     (29U)\n#define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R1_FB30_Pos     (30U)\n#define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R1_FB31_Pos     (31U)\n#define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R1 register  ******************/\n#define CAN_F13R1_FB0_Pos      (0U)\n#define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R1_FB1_Pos      (1U)\n#define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R1_FB2_Pos      (2U)\n#define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R1_FB3_Pos      (3U)\n#define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R1_FB4_Pos      (4U)\n#define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R1_FB5_Pos      (5U)\n#define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R1_FB6_Pos      (6U)\n#define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R1_FB7_Pos      (7U)\n#define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R1_FB8_Pos      (8U)\n#define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R1_FB9_Pos      (9U)\n#define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R1_FB10_Pos     (10U)\n#define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R1_FB11_Pos     (11U)\n#define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R1_FB12_Pos     (12U)\n#define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R1_FB13_Pos     (13U)\n#define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R1_FB14_Pos     (14U)\n#define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R1_FB15_Pos     (15U)\n#define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R1_FB16_Pos     (16U)\n#define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R1_FB17_Pos     (17U)\n#define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R1_FB18_Pos     (18U)\n#define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R1_FB19_Pos     (19U)\n#define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R1_FB20_Pos     (20U)\n#define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R1_FB21_Pos     (21U)\n#define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R1_FB22_Pos     (22U)\n#define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R1_FB23_Pos     (23U)\n#define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R1_FB24_Pos     (24U)\n#define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R1_FB25_Pos     (25U)\n#define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R1_FB26_Pos     (26U)\n#define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R1_FB27_Pos     (27U)\n#define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R1_FB28_Pos     (28U)\n#define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R1_FB29_Pos     (29U)\n#define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R1_FB30_Pos     (30U)\n#define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R1_FB31_Pos     (31U)\n#define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F0R2 register  *******************/\n#define CAN_F0R2_FB0_Pos       (0U)\n#define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R2_FB1_Pos       (1U)\n#define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R2_FB2_Pos       (2U)\n#define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R2_FB3_Pos       (3U)\n#define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R2_FB4_Pos       (4U)\n#define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R2_FB5_Pos       (5U)\n#define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R2_FB6_Pos       (6U)\n#define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R2_FB7_Pos       (7U)\n#define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R2_FB8_Pos       (8U)\n#define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R2_FB9_Pos       (9U)\n#define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R2_FB10_Pos      (10U)\n#define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R2_FB11_Pos      (11U)\n#define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R2_FB12_Pos      (12U)\n#define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R2_FB13_Pos      (13U)\n#define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R2_FB14_Pos      (14U)\n#define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R2_FB15_Pos      (15U)\n#define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R2_FB16_Pos      (16U)\n#define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R2_FB17_Pos      (17U)\n#define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R2_FB18_Pos      (18U)\n#define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R2_FB19_Pos      (19U)\n#define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R2_FB20_Pos      (20U)\n#define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R2_FB21_Pos      (21U)\n#define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R2_FB22_Pos      (22U)\n#define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R2_FB23_Pos      (23U)\n#define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R2_FB24_Pos      (24U)\n#define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R2_FB25_Pos      (25U)\n#define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R2_FB26_Pos      (26U)\n#define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R2_FB27_Pos      (27U)\n#define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R2_FB28_Pos      (28U)\n#define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R2_FB29_Pos      (29U)\n#define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R2_FB30_Pos      (30U)\n#define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R2_FB31_Pos      (31U)\n#define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R2 register  *******************/\n#define CAN_F1R2_FB0_Pos       (0U)\n#define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R2_FB1_Pos       (1U)\n#define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R2_FB2_Pos       (2U)\n#define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R2_FB3_Pos       (3U)\n#define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R2_FB4_Pos       (4U)\n#define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R2_FB5_Pos       (5U)\n#define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R2_FB6_Pos       (6U)\n#define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R2_FB7_Pos       (7U)\n#define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R2_FB8_Pos       (8U)\n#define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R2_FB9_Pos       (9U)\n#define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R2_FB10_Pos      (10U)\n#define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R2_FB11_Pos      (11U)\n#define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R2_FB12_Pos      (12U)\n#define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R2_FB13_Pos      (13U)\n#define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R2_FB14_Pos      (14U)\n#define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R2_FB15_Pos      (15U)\n#define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R2_FB16_Pos      (16U)\n#define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R2_FB17_Pos      (17U)\n#define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R2_FB18_Pos      (18U)\n#define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R2_FB19_Pos      (19U)\n#define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R2_FB20_Pos      (20U)\n#define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R2_FB21_Pos      (21U)\n#define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R2_FB22_Pos      (22U)\n#define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R2_FB23_Pos      (23U)\n#define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R2_FB24_Pos      (24U)\n#define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R2_FB25_Pos      (25U)\n#define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R2_FB26_Pos      (26U)\n#define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R2_FB27_Pos      (27U)\n#define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R2_FB28_Pos      (28U)\n#define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R2_FB29_Pos      (29U)\n#define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R2_FB30_Pos      (30U)\n#define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R2_FB31_Pos      (31U)\n#define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R2 register  *******************/\n#define CAN_F2R2_FB0_Pos       (0U)\n#define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R2_FB1_Pos       (1U)\n#define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R2_FB2_Pos       (2U)\n#define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R2_FB3_Pos       (3U)\n#define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R2_FB4_Pos       (4U)\n#define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R2_FB5_Pos       (5U)\n#define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R2_FB6_Pos       (6U)\n#define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R2_FB7_Pos       (7U)\n#define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R2_FB8_Pos       (8U)\n#define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R2_FB9_Pos       (9U)\n#define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R2_FB10_Pos      (10U)\n#define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R2_FB11_Pos      (11U)\n#define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R2_FB12_Pos      (12U)\n#define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R2_FB13_Pos      (13U)\n#define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R2_FB14_Pos      (14U)\n#define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R2_FB15_Pos      (15U)\n#define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R2_FB16_Pos      (16U)\n#define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R2_FB17_Pos      (17U)\n#define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R2_FB18_Pos      (18U)\n#define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R2_FB19_Pos      (19U)\n#define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R2_FB20_Pos      (20U)\n#define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R2_FB21_Pos      (21U)\n#define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R2_FB22_Pos      (22U)\n#define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R2_FB23_Pos      (23U)\n#define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R2_FB24_Pos      (24U)\n#define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R2_FB25_Pos      (25U)\n#define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R2_FB26_Pos      (26U)\n#define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R2_FB27_Pos      (27U)\n#define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R2_FB28_Pos      (28U)\n#define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R2_FB29_Pos      (29U)\n#define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R2_FB30_Pos      (30U)\n#define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R2_FB31_Pos      (31U)\n#define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R2 register  *******************/\n#define CAN_F3R2_FB0_Pos       (0U)\n#define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R2_FB1_Pos       (1U)\n#define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R2_FB2_Pos       (2U)\n#define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R2_FB3_Pos       (3U)\n#define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R2_FB4_Pos       (4U)\n#define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R2_FB5_Pos       (5U)\n#define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R2_FB6_Pos       (6U)\n#define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R2_FB7_Pos       (7U)\n#define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R2_FB8_Pos       (8U)\n#define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R2_FB9_Pos       (9U)\n#define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R2_FB10_Pos      (10U)\n#define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R2_FB11_Pos      (11U)\n#define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R2_FB12_Pos      (12U)\n#define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R2_FB13_Pos      (13U)\n#define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R2_FB14_Pos      (14U)\n#define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R2_FB15_Pos      (15U)\n#define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R2_FB16_Pos      (16U)\n#define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R2_FB17_Pos      (17U)\n#define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R2_FB18_Pos      (18U)\n#define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R2_FB19_Pos      (19U)\n#define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R2_FB20_Pos      (20U)\n#define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R2_FB21_Pos      (21U)\n#define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R2_FB22_Pos      (22U)\n#define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R2_FB23_Pos      (23U)\n#define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R2_FB24_Pos      (24U)\n#define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R2_FB25_Pos      (25U)\n#define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R2_FB26_Pos      (26U)\n#define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R2_FB27_Pos      (27U)\n#define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R2_FB28_Pos      (28U)\n#define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R2_FB29_Pos      (29U)\n#define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R2_FB30_Pos      (30U)\n#define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R2_FB31_Pos      (31U)\n#define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R2 register  *******************/\n#define CAN_F4R2_FB0_Pos       (0U)\n#define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R2_FB1_Pos       (1U)\n#define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R2_FB2_Pos       (2U)\n#define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R2_FB3_Pos       (3U)\n#define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R2_FB4_Pos       (4U)\n#define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R2_FB5_Pos       (5U)\n#define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R2_FB6_Pos       (6U)\n#define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R2_FB7_Pos       (7U)\n#define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R2_FB8_Pos       (8U)\n#define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R2_FB9_Pos       (9U)\n#define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R2_FB10_Pos      (10U)\n#define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R2_FB11_Pos      (11U)\n#define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R2_FB12_Pos      (12U)\n#define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R2_FB13_Pos      (13U)\n#define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R2_FB14_Pos      (14U)\n#define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R2_FB15_Pos      (15U)\n#define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R2_FB16_Pos      (16U)\n#define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R2_FB17_Pos      (17U)\n#define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R2_FB18_Pos      (18U)\n#define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R2_FB19_Pos      (19U)\n#define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R2_FB20_Pos      (20U)\n#define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R2_FB21_Pos      (21U)\n#define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R2_FB22_Pos      (22U)\n#define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R2_FB23_Pos      (23U)\n#define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R2_FB24_Pos      (24U)\n#define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R2_FB25_Pos      (25U)\n#define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R2_FB26_Pos      (26U)\n#define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R2_FB27_Pos      (27U)\n#define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R2_FB28_Pos      (28U)\n#define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R2_FB29_Pos      (29U)\n#define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R2_FB30_Pos      (30U)\n#define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R2_FB31_Pos      (31U)\n#define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R2 register  *******************/\n#define CAN_F5R2_FB0_Pos       (0U)\n#define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R2_FB1_Pos       (1U)\n#define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R2_FB2_Pos       (2U)\n#define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R2_FB3_Pos       (3U)\n#define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R2_FB4_Pos       (4U)\n#define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R2_FB5_Pos       (5U)\n#define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R2_FB6_Pos       (6U)\n#define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R2_FB7_Pos       (7U)\n#define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R2_FB8_Pos       (8U)\n#define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R2_FB9_Pos       (9U)\n#define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R2_FB10_Pos      (10U)\n#define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R2_FB11_Pos      (11U)\n#define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R2_FB12_Pos      (12U)\n#define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R2_FB13_Pos      (13U)\n#define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R2_FB14_Pos      (14U)\n#define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R2_FB15_Pos      (15U)\n#define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R2_FB16_Pos      (16U)\n#define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R2_FB17_Pos      (17U)\n#define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R2_FB18_Pos      (18U)\n#define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R2_FB19_Pos      (19U)\n#define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R2_FB20_Pos      (20U)\n#define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R2_FB21_Pos      (21U)\n#define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R2_FB22_Pos      (22U)\n#define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R2_FB23_Pos      (23U)\n#define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R2_FB24_Pos      (24U)\n#define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R2_FB25_Pos      (25U)\n#define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R2_FB26_Pos      (26U)\n#define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R2_FB27_Pos      (27U)\n#define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R2_FB28_Pos      (28U)\n#define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R2_FB29_Pos      (29U)\n#define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R2_FB30_Pos      (30U)\n#define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R2_FB31_Pos      (31U)\n#define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R2 register  *******************/\n#define CAN_F6R2_FB0_Pos       (0U)\n#define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R2_FB1_Pos       (1U)\n#define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R2_FB2_Pos       (2U)\n#define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R2_FB3_Pos       (3U)\n#define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R2_FB4_Pos       (4U)\n#define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R2_FB5_Pos       (5U)\n#define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R2_FB6_Pos       (6U)\n#define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R2_FB7_Pos       (7U)\n#define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R2_FB8_Pos       (8U)\n#define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R2_FB9_Pos       (9U)\n#define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R2_FB10_Pos      (10U)\n#define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R2_FB11_Pos      (11U)\n#define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R2_FB12_Pos      (12U)\n#define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R2_FB13_Pos      (13U)\n#define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R2_FB14_Pos      (14U)\n#define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R2_FB15_Pos      (15U)\n#define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R2_FB16_Pos      (16U)\n#define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R2_FB17_Pos      (17U)\n#define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R2_FB18_Pos      (18U)\n#define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R2_FB19_Pos      (19U)\n#define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R2_FB20_Pos      (20U)\n#define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R2_FB21_Pos      (21U)\n#define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R2_FB22_Pos      (22U)\n#define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R2_FB23_Pos      (23U)\n#define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R2_FB24_Pos      (24U)\n#define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R2_FB25_Pos      (25U)\n#define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R2_FB26_Pos      (26U)\n#define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R2_FB27_Pos      (27U)\n#define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R2_FB28_Pos      (28U)\n#define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R2_FB29_Pos      (29U)\n#define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R2_FB30_Pos      (30U)\n#define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R2_FB31_Pos      (31U)\n#define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R2 register  *******************/\n#define CAN_F7R2_FB0_Pos       (0U)\n#define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R2_FB1_Pos       (1U)\n#define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R2_FB2_Pos       (2U)\n#define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R2_FB3_Pos       (3U)\n#define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R2_FB4_Pos       (4U)\n#define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R2_FB5_Pos       (5U)\n#define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R2_FB6_Pos       (6U)\n#define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R2_FB7_Pos       (7U)\n#define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R2_FB8_Pos       (8U)\n#define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R2_FB9_Pos       (9U)\n#define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R2_FB10_Pos      (10U)\n#define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R2_FB11_Pos      (11U)\n#define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R2_FB12_Pos      (12U)\n#define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R2_FB13_Pos      (13U)\n#define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R2_FB14_Pos      (14U)\n#define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R2_FB15_Pos      (15U)\n#define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R2_FB16_Pos      (16U)\n#define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R2_FB17_Pos      (17U)\n#define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R2_FB18_Pos      (18U)\n#define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R2_FB19_Pos      (19U)\n#define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R2_FB20_Pos      (20U)\n#define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R2_FB21_Pos      (21U)\n#define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R2_FB22_Pos      (22U)\n#define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R2_FB23_Pos      (23U)\n#define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R2_FB24_Pos      (24U)\n#define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R2_FB25_Pos      (25U)\n#define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R2_FB26_Pos      (26U)\n#define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R2_FB27_Pos      (27U)\n#define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R2_FB28_Pos      (28U)\n#define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R2_FB29_Pos      (29U)\n#define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R2_FB30_Pos      (30U)\n#define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R2_FB31_Pos      (31U)\n#define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R2 register  *******************/\n#define CAN_F8R2_FB0_Pos       (0U)\n#define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R2_FB1_Pos       (1U)\n#define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R2_FB2_Pos       (2U)\n#define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R2_FB3_Pos       (3U)\n#define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R2_FB4_Pos       (4U)\n#define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R2_FB5_Pos       (5U)\n#define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R2_FB6_Pos       (6U)\n#define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R2_FB7_Pos       (7U)\n#define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R2_FB8_Pos       (8U)\n#define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R2_FB9_Pos       (9U)\n#define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R2_FB10_Pos      (10U)\n#define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R2_FB11_Pos      (11U)\n#define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R2_FB12_Pos      (12U)\n#define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R2_FB13_Pos      (13U)\n#define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R2_FB14_Pos      (14U)\n#define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R2_FB15_Pos      (15U)\n#define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R2_FB16_Pos      (16U)\n#define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R2_FB17_Pos      (17U)\n#define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R2_FB18_Pos      (18U)\n#define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R2_FB19_Pos      (19U)\n#define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R2_FB20_Pos      (20U)\n#define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R2_FB21_Pos      (21U)\n#define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R2_FB22_Pos      (22U)\n#define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R2_FB23_Pos      (23U)\n#define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R2_FB24_Pos      (24U)\n#define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R2_FB25_Pos      (25U)\n#define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R2_FB26_Pos      (26U)\n#define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R2_FB27_Pos      (27U)\n#define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R2_FB28_Pos      (28U)\n#define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R2_FB29_Pos      (29U)\n#define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R2_FB30_Pos      (30U)\n#define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R2_FB31_Pos      (31U)\n#define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R2 register  *******************/\n#define CAN_F9R2_FB0_Pos       (0U)\n#define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R2_FB1_Pos       (1U)\n#define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R2_FB2_Pos       (2U)\n#define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R2_FB3_Pos       (3U)\n#define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R2_FB4_Pos       (4U)\n#define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R2_FB5_Pos       (5U)\n#define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R2_FB6_Pos       (6U)\n#define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R2_FB7_Pos       (7U)\n#define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R2_FB8_Pos       (8U)\n#define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R2_FB9_Pos       (9U)\n#define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R2_FB10_Pos      (10U)\n#define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R2_FB11_Pos      (11U)\n#define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R2_FB12_Pos      (12U)\n#define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R2_FB13_Pos      (13U)\n#define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R2_FB14_Pos      (14U)\n#define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R2_FB15_Pos      (15U)\n#define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R2_FB16_Pos      (16U)\n#define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R2_FB17_Pos      (17U)\n#define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R2_FB18_Pos      (18U)\n#define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R2_FB19_Pos      (19U)\n#define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R2_FB20_Pos      (20U)\n#define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R2_FB21_Pos      (21U)\n#define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R2_FB22_Pos      (22U)\n#define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R2_FB23_Pos      (23U)\n#define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R2_FB24_Pos      (24U)\n#define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R2_FB25_Pos      (25U)\n#define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R2_FB26_Pos      (26U)\n#define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R2_FB27_Pos      (27U)\n#define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R2_FB28_Pos      (28U)\n#define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R2_FB29_Pos      (29U)\n#define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R2_FB30_Pos      (30U)\n#define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R2_FB31_Pos      (31U)\n#define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R2 register  ******************/\n#define CAN_F10R2_FB0_Pos      (0U)\n#define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R2_FB1_Pos      (1U)\n#define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R2_FB2_Pos      (2U)\n#define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R2_FB3_Pos      (3U)\n#define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R2_FB4_Pos      (4U)\n#define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R2_FB5_Pos      (5U)\n#define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R2_FB6_Pos      (6U)\n#define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R2_FB7_Pos      (7U)\n#define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R2_FB8_Pos      (8U)\n#define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R2_FB9_Pos      (9U)\n#define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R2_FB10_Pos     (10U)\n#define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R2_FB11_Pos     (11U)\n#define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R2_FB12_Pos     (12U)\n#define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R2_FB13_Pos     (13U)\n#define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R2_FB14_Pos     (14U)\n#define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R2_FB15_Pos     (15U)\n#define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R2_FB16_Pos     (16U)\n#define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R2_FB17_Pos     (17U)\n#define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R2_FB18_Pos     (18U)\n#define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R2_FB19_Pos     (19U)\n#define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R2_FB20_Pos     (20U)\n#define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R2_FB21_Pos     (21U)\n#define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R2_FB22_Pos     (22U)\n#define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R2_FB23_Pos     (23U)\n#define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R2_FB24_Pos     (24U)\n#define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R2_FB25_Pos     (25U)\n#define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R2_FB26_Pos     (26U)\n#define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R2_FB27_Pos     (27U)\n#define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R2_FB28_Pos     (28U)\n#define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R2_FB29_Pos     (29U)\n#define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R2_FB30_Pos     (30U)\n#define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R2_FB31_Pos     (31U)\n#define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R2 register  ******************/\n#define CAN_F11R2_FB0_Pos      (0U)\n#define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R2_FB1_Pos      (1U)\n#define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R2_FB2_Pos      (2U)\n#define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R2_FB3_Pos      (3U)\n#define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R2_FB4_Pos      (4U)\n#define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R2_FB5_Pos      (5U)\n#define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R2_FB6_Pos      (6U)\n#define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R2_FB7_Pos      (7U)\n#define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R2_FB8_Pos      (8U)\n#define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R2_FB9_Pos      (9U)\n#define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R2_FB10_Pos     (10U)\n#define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R2_FB11_Pos     (11U)\n#define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R2_FB12_Pos     (12U)\n#define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R2_FB13_Pos     (13U)\n#define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R2_FB14_Pos     (14U)\n#define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R2_FB15_Pos     (15U)\n#define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R2_FB16_Pos     (16U)\n#define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R2_FB17_Pos     (17U)\n#define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R2_FB18_Pos     (18U)\n#define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R2_FB19_Pos     (19U)\n#define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R2_FB20_Pos     (20U)\n#define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R2_FB21_Pos     (21U)\n#define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R2_FB22_Pos     (22U)\n#define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R2_FB23_Pos     (23U)\n#define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R2_FB24_Pos     (24U)\n#define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R2_FB25_Pos     (25U)\n#define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R2_FB26_Pos     (26U)\n#define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R2_FB27_Pos     (27U)\n#define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R2_FB28_Pos     (28U)\n#define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R2_FB29_Pos     (29U)\n#define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R2_FB30_Pos     (30U)\n#define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R2_FB31_Pos     (31U)\n#define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R2 register  ******************/\n#define CAN_F12R2_FB0_Pos      (0U)\n#define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R2_FB1_Pos      (1U)\n#define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R2_FB2_Pos      (2U)\n#define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R2_FB3_Pos      (3U)\n#define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R2_FB4_Pos      (4U)\n#define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R2_FB5_Pos      (5U)\n#define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R2_FB6_Pos      (6U)\n#define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R2_FB7_Pos      (7U)\n#define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R2_FB8_Pos      (8U)\n#define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R2_FB9_Pos      (9U)\n#define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R2_FB10_Pos     (10U)\n#define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R2_FB11_Pos     (11U)\n#define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R2_FB12_Pos     (12U)\n#define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R2_FB13_Pos     (13U)\n#define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R2_FB14_Pos     (14U)\n#define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R2_FB15_Pos     (15U)\n#define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R2_FB16_Pos     (16U)\n#define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R2_FB17_Pos     (17U)\n#define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R2_FB18_Pos     (18U)\n#define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R2_FB19_Pos     (19U)\n#define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R2_FB20_Pos     (20U)\n#define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R2_FB21_Pos     (21U)\n#define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R2_FB22_Pos     (22U)\n#define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R2_FB23_Pos     (23U)\n#define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R2_FB24_Pos     (24U)\n#define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R2_FB25_Pos     (25U)\n#define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R2_FB26_Pos     (26U)\n#define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R2_FB27_Pos     (27U)\n#define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R2_FB28_Pos     (28U)\n#define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R2_FB29_Pos     (29U)\n#define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R2_FB30_Pos     (30U)\n#define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R2_FB31_Pos     (31U)\n#define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R2 register  ******************/\n#define CAN_F13R2_FB0_Pos      (0U)\n#define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R2_FB1_Pos      (1U)\n#define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R2_FB2_Pos      (2U)\n#define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R2_FB3_Pos      (3U)\n#define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R2_FB4_Pos      (4U)\n#define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R2_FB5_Pos      (5U)\n#define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R2_FB6_Pos      (6U)\n#define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R2_FB7_Pos      (7U)\n#define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R2_FB8_Pos      (8U)\n#define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R2_FB9_Pos      (9U)\n#define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R2_FB10_Pos     (10U)\n#define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R2_FB11_Pos     (11U)\n#define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R2_FB12_Pos     (12U)\n#define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R2_FB13_Pos     (13U)\n#define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R2_FB14_Pos     (14U)\n#define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R2_FB15_Pos     (15U)\n#define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R2_FB16_Pos     (16U)\n#define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R2_FB17_Pos     (17U)\n#define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R2_FB18_Pos     (18U)\n#define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R2_FB19_Pos     (19U)\n#define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R2_FB20_Pos     (20U)\n#define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R2_FB21_Pos     (21U)\n#define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R2_FB22_Pos     (22U)\n#define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R2_FB23_Pos     (23U)\n#define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R2_FB24_Pos     (24U)\n#define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R2_FB25_Pos     (25U)\n#define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R2_FB26_Pos     (26U)\n#define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R2_FB27_Pos     (27U)\n#define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R2_FB28_Pos     (28U)\n#define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R2_FB29_Pos     (29U)\n#define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R2_FB30_Pos     (30U)\n#define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R2_FB31_Pos     (31U)\n#define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          HDMI-CEC (CEC)                                    */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for CEC_CR register  *********************/\n#define CEC_CR_CECEN_Pos         (0U)\n#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                    /*!< 0x00000001 */\n#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                              */\n#define CEC_CR_TXSOM_Pos         (1U)\n#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                    /*!< 0x00000002 */\n#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                 */\n#define CEC_CR_TXEOM_Pos         (2U)\n#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                    /*!< 0x00000004 */\n#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                   */\n\n/*******************  Bit definition for CEC_CFGR register  *******************/\n#define CEC_CFGR_SFT_Pos         (0U)\n#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                    /*!< 0x00000007 */\n#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                    */\n#define CEC_CFGR_RXTOL_Pos       (3U)\n#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                  /*!< 0x00000008 */\n#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                           */\n#define CEC_CFGR_BRESTP_Pos      (4U)\n#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                 /*!< 0x00000010 */\n#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                             */\n#define CEC_CFGR_BREGEN_Pos      (5U)\n#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                 /*!< 0x00000020 */\n#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation         */\n#define CEC_CFGR_LBPEGEN_Pos     (6U)\n#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)                /*!< 0x00000040 */\n#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation    */\n#define CEC_CFGR_SFTOPT_Pos      (8U)\n#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                 /*!< 0x00000100 */\n#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional           */\n#define CEC_CFGR_BRDNOGEN_Pos    (7U)\n#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)               /*!< 0x00000080 */\n#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation       */\n#define CEC_CFGR_OAR_Pos         (16U)\n#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                 /*!< 0x7FFF0000 */\n#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                         */\n#define CEC_CFGR_LSTN_Pos        (31U)\n#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                   /*!< 0x80000000 */\n#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                         */\n\n/*******************  Bit definition for CEC_TXDR register  *******************/\n#define CEC_TXDR_TXD_Pos         (0U)\n#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                   /*!< 0x000000FF */\n#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                              */\n\n/*******************  Bit definition for CEC_RXDR register  *******************/\n#define CEC_RXDR_RXD_Pos         (0U)\n#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                   /*!< 0x000000FF */\n#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                              */\n/*legacy define*/\n#define  CEC_TXDR_RXD                        CEC_RXDR_RXD      /*!< CEC Rx Data                              */\n\n/*******************  Bit definition for CEC_ISR register  ********************/\n#define CEC_ISR_RXBR_Pos         (0U)\n#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                    /*!< 0x00000001 */\n#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */\n#define CEC_ISR_RXEND_Pos        (1U)\n#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                   /*!< 0x00000002 */\n#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */\n#define CEC_ISR_RXOVR_Pos        (2U)\n#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                   /*!< 0x00000004 */\n#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */\n#define CEC_ISR_BRE_Pos          (3U)\n#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                     /*!< 0x00000008 */\n#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */\n#define CEC_ISR_SBPE_Pos         (4U)\n#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                    /*!< 0x00000010 */\n#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */\n#define CEC_ISR_LBPE_Pos         (5U)\n#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                    /*!< 0x00000020 */\n#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */\n#define CEC_ISR_RXACKE_Pos       (6U)\n#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                  /*!< 0x00000040 */\n#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */\n#define CEC_ISR_ARBLST_Pos       (7U)\n#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                  /*!< 0x00000080 */\n#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */\n#define CEC_ISR_TXBR_Pos         (8U)\n#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                    /*!< 0x00000100 */\n#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */\n#define CEC_ISR_TXEND_Pos        (9U)\n#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                   /*!< 0x00000200 */\n#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */\n#define CEC_ISR_TXUDR_Pos        (10U)\n#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                   /*!< 0x00000400 */\n#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */\n#define CEC_ISR_TXERR_Pos        (11U)\n#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                   /*!< 0x00000800 */\n#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */\n#define CEC_ISR_TXACKE_Pos       (12U)\n#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                  /*!< 0x00001000 */\n#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */\n\n/*******************  Bit definition for CEC_IER register  ********************/\n#define CEC_IER_RXBRIE_Pos       (0U)\n#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                  /*!< 0x00000001 */\n#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */\n#define CEC_IER_RXENDIE_Pos      (1U)\n#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                 /*!< 0x00000002 */\n#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */\n#define CEC_IER_RXOVRIE_Pos      (2U)\n#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                 /*!< 0x00000004 */\n#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */\n#define CEC_IER_BREIE_Pos        (3U)\n#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                   /*!< 0x00000008 */\n#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */\n#define CEC_IER_SBPEIE_Pos       (4U)\n#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                  /*!< 0x00000010 */\n#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */\n#define CEC_IER_LBPEIE_Pos       (5U)\n#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                  /*!< 0x00000020 */\n#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */\n#define CEC_IER_RXACKEIE_Pos     (6U)\n#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)                /*!< 0x00000040 */\n#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */\n#define CEC_IER_ARBLSTIE_Pos     (7U)\n#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)                /*!< 0x00000080 */\n#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */\n#define CEC_IER_TXBRIE_Pos       (8U)\n#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                  /*!< 0x00000100 */\n#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */\n#define CEC_IER_TXENDIE_Pos      (9U)\n#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                 /*!< 0x00000200 */\n#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */\n#define CEC_IER_TXUDRIE_Pos      (10U)\n#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                 /*!< 0x00000400 */\n#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */\n#define CEC_IER_TXERRIE_Pos      (11U)\n#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                 /*!< 0x00000800 */\n#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */\n#define CEC_IER_TXACKEIE_Pos     (12U)\n#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)                /*!< 0x00001000 */\n#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          CRC calculation unit                              */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for CRC_DR register  *********************/\n#define CRC_DR_DR_Pos       (0U)\n#define CRC_DR_DR_Msk       (0xFFFFFFFFUL << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */\n#define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */\n\n\n/*******************  Bit definition for CRC_IDR register  ********************/\n#define CRC_IDR_IDR_Pos     (0U)\n#define CRC_IDR_IDR_Msk     (0xFFUL << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */\n#define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */\n\n\n/********************  Bit definition for CRC_CR register  ********************/\n#define CRC_CR_RESET_Pos    (0U)\n#define CRC_CR_RESET_Msk    (0x1UL << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */\n#define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Digital to Analog Converter                           */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define DAC_CHANNEL2_SUPPORT                                    /*!< DAC feature available only on specific devices: availability of DAC channel 2 */\n/********************  Bit definition for DAC_CR register  ********************/\n#define DAC_CR_EN1_Pos              (0U)\n#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */\n#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */\n#define DAC_CR_BOFF1_Pos            (1U)\n#define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */\n#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable */\n#define DAC_CR_TEN1_Pos             (2U)\n#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */\n#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */\n\n#define DAC_CR_TSEL1_Pos            (3U)\n#define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */\n#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\n#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */\n#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */\n#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */\n\n#define DAC_CR_WAVE1_Pos            (6U)\n#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */\n#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */\n#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */\n\n#define DAC_CR_MAMP1_Pos            (8U)\n#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */\n#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\n#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */\n#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */\n#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */\n#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */\n\n#define DAC_CR_DMAEN1_Pos           (12U)\n#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */\n#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */\n#define DAC_CR_DMAUDRIE1_Pos        (13U)\n#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */\n#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable*/\n#define DAC_CR_EN2_Pos              (16U)\n#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */\n#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */\n#define DAC_CR_BOFF2_Pos            (17U)\n#define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */\n#define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable */\n#define DAC_CR_TEN2_Pos             (18U)\n#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */\n#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */\n\n#define DAC_CR_TSEL2_Pos            (19U)\n#define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */\n#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\n#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */\n#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */\n#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */\n\n#define DAC_CR_WAVE2_Pos            (22U)\n#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */\n#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */\n#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */\n\n#define DAC_CR_MAMP2_Pos            (24U)\n#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */\n#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\n#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */\n#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */\n#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */\n#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */\n\n#define DAC_CR_DMAEN2_Pos           (28U)\n#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */\n#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */\n#define DAC_CR_DMAUDRIE2_Pos        (29U)\n#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */\n#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable*/\n\n/*****************  Bit definition for DAC_SWTRIGR register  ******************/\n#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)\n#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */\n#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */\n#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)\n#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */\n#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */\n\n/*****************  Bit definition for DAC_DHR12R1 register  ******************/\n#define DAC_DHR12R1_DACC1DHR_Pos    (0U)\n#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L1 register  ******************/\n#define DAC_DHR12L1_DACC1DHR_Pos    (4U)\n#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R1 register  ******************/\n#define DAC_DHR8R1_DACC1DHR_Pos     (0U)\n#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12R2 register  ******************/\n#define DAC_DHR12R2_DACC2DHR_Pos    (0U)\n#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L2 register  ******************/\n#define DAC_DHR12L2_DACC2DHR_Pos    (4U)\n#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R2 register  ******************/\n#define DAC_DHR8R2_DACC2DHR_Pos     (0U)\n#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12RD register  ******************/\n#define DAC_DHR12RD_DACC1DHR_Pos    (0U)\n#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\n#define DAC_DHR12RD_DACC2DHR_Pos    (16U)\n#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */\n#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12LD register  ******************/\n#define DAC_DHR12LD_DACC1DHR_Pos    (4U)\n#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\n#define DAC_DHR12LD_DACC2DHR_Pos    (20U)\n#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */\n#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8RD register  ******************/\n#define DAC_DHR8RD_DACC1DHR_Pos     (0U)\n#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\n#define DAC_DHR8RD_DACC2DHR_Pos     (8U)\n#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */\n#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\n\n/*******************  Bit definition for DAC_DOR1 register  *******************/\n#define DAC_DOR1_DACC1DOR_Pos       (0U)\n#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */\n#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */\n\n/*******************  Bit definition for DAC_DOR2 register  *******************/\n#define DAC_DOR2_DACC2DOR_Pos       (0U)\n#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */\n#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */\n\n/********************  Bit definition for DAC_SR register  ********************/\n#define DAC_SR_DMAUDR1_Pos          (13U)\n#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */\n#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */\n#define DAC_SR_DMAUDR2_Pos          (29U)\n#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */\n#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    DCMI                                    */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DCMI_CR register  ******************/\n#define DCMI_CR_CAPTURE_Pos        (0U)\n#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)               /*!< 0x00000001 */\n#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk\n#define DCMI_CR_CM_Pos             (1U)\n#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                    /*!< 0x00000002 */\n#define DCMI_CR_CM                 DCMI_CR_CM_Msk\n#define DCMI_CR_CROP_Pos           (2U)\n#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                  /*!< 0x00000004 */\n#define DCMI_CR_CROP               DCMI_CR_CROP_Msk\n#define DCMI_CR_JPEG_Pos           (3U)\n#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                  /*!< 0x00000008 */\n#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk\n#define DCMI_CR_ESS_Pos            (4U)\n#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                   /*!< 0x00000010 */\n#define DCMI_CR_ESS                DCMI_CR_ESS_Msk\n#define DCMI_CR_PCKPOL_Pos         (5U)\n#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)                /*!< 0x00000020 */\n#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk\n#define DCMI_CR_HSPOL_Pos          (6U)\n#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                 /*!< 0x00000040 */\n#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk\n#define DCMI_CR_VSPOL_Pos          (7U)\n#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                 /*!< 0x00000080 */\n#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk\n#define DCMI_CR_FCRC_0             0x00000100U\n#define DCMI_CR_FCRC_1             0x00000200U\n#define DCMI_CR_EDM_0              0x00000400U\n#define DCMI_CR_EDM_1              0x00000800U\n#define DCMI_CR_OUTEN_Pos          (13U)\n#define DCMI_CR_OUTEN_Msk          (0x1UL << DCMI_CR_OUTEN_Pos)                 /*!< 0x00002000 */\n#define DCMI_CR_OUTEN              DCMI_CR_OUTEN_Msk\n#define DCMI_CR_ENABLE_Pos         (14U)\n#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)                /*!< 0x00004000 */\n#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk\n#define DCMI_CR_BSM_0              0x00010000U\n#define DCMI_CR_BSM_1              0x00020000U\n#define DCMI_CR_OEBS_Pos           (18U)\n#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                  /*!< 0x00040000 */\n#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk\n#define DCMI_CR_LSM_Pos            (19U)\n#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                   /*!< 0x00080000 */\n#define DCMI_CR_LSM                DCMI_CR_LSM_Msk\n#define DCMI_CR_OELS_Pos           (20U)\n#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                  /*!< 0x00100000 */\n#define DCMI_CR_OELS               DCMI_CR_OELS_Msk\n\n/********************  Bits definition for DCMI_SR register  ******************/\n#define DCMI_SR_HSYNC_Pos          (0U)\n#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                 /*!< 0x00000001 */\n#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk\n#define DCMI_SR_VSYNC_Pos          (1U)\n#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                 /*!< 0x00000002 */\n#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk\n#define DCMI_SR_FNE_Pos            (2U)\n#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                   /*!< 0x00000004 */\n#define DCMI_SR_FNE                DCMI_SR_FNE_Msk\n\n/********************  Bits definition for DCMI_RIS register  *****************/\n#define DCMI_RIS_FRAME_RIS_Pos     (0U)\n#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)            /*!< 0x00000001 */\n#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk\n#define DCMI_RIS_OVR_RIS_Pos       (1U)\n#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)              /*!< 0x00000002 */\n#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk\n#define DCMI_RIS_ERR_RIS_Pos       (2U)\n#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)              /*!< 0x00000004 */\n#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk\n#define DCMI_RIS_VSYNC_RIS_Pos     (3U)\n#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)            /*!< 0x00000008 */\n#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk\n#define DCMI_RIS_LINE_RIS_Pos      (4U)\n#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)             /*!< 0x00000010 */\n#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk\n/* Legacy defines */\n#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS\n#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS\n#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS\n#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS\n#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS\n#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS\n\n/********************  Bits definition for DCMI_IER register  *****************/\n#define DCMI_IER_FRAME_IE_Pos      (0U)\n#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)             /*!< 0x00000001 */\n#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk\n#define DCMI_IER_OVR_IE_Pos        (1U)\n#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)               /*!< 0x00000002 */\n#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk\n#define DCMI_IER_ERR_IE_Pos        (2U)\n#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)               /*!< 0x00000004 */\n#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk\n#define DCMI_IER_VSYNC_IE_Pos      (3U)\n#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)             /*!< 0x00000008 */\n#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk\n#define DCMI_IER_LINE_IE_Pos       (4U)\n#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)              /*!< 0x00000010 */\n#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk\n/* Legacy defines */\n#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE\n\n/********************  Bits definition for DCMI_MIS register  *****************/\n#define DCMI_MIS_FRAME_MIS_Pos     (0U)\n#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)            /*!< 0x00000001 */\n#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk\n#define DCMI_MIS_OVR_MIS_Pos       (1U)\n#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)              /*!< 0x00000002 */\n#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk\n#define DCMI_MIS_ERR_MIS_Pos       (2U)\n#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)              /*!< 0x00000004 */\n#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk\n#define DCMI_MIS_VSYNC_MIS_Pos     (3U)\n#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)            /*!< 0x00000008 */\n#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk\n#define DCMI_MIS_LINE_MIS_Pos      (4U)\n#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)             /*!< 0x00000010 */\n#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk\n\n/* Legacy defines */\n#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS\n#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS\n#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS\n#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS\n#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS\n\n/********************  Bits definition for DCMI_ICR register  *****************/\n#define DCMI_ICR_FRAME_ISC_Pos     (0U)\n#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)            /*!< 0x00000001 */\n#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk\n#define DCMI_ICR_OVR_ISC_Pos       (1U)\n#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)              /*!< 0x00000002 */\n#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk\n#define DCMI_ICR_ERR_ISC_Pos       (2U)\n#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)              /*!< 0x00000004 */\n#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk\n#define DCMI_ICR_VSYNC_ISC_Pos     (3U)\n#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)            /*!< 0x00000008 */\n#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk\n#define DCMI_ICR_LINE_ISC_Pos      (4U)\n#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)             /*!< 0x00000010 */\n#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk\n\n/* Legacy defines */\n#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC\n\n/********************  Bits definition for DCMI_ESCR register  ******************/\n#define DCMI_ESCR_FSC_Pos          (0U)\n#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)                /*!< 0x000000FF */\n#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk\n#define DCMI_ESCR_LSC_Pos          (8U)\n#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)                /*!< 0x0000FF00 */\n#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk\n#define DCMI_ESCR_LEC_Pos          (16U)\n#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)                /*!< 0x00FF0000 */\n#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk\n#define DCMI_ESCR_FEC_Pos          (24U)\n#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)                /*!< 0xFF000000 */\n#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk\n\n/********************  Bits definition for DCMI_ESUR register  ******************/\n#define DCMI_ESUR_FSU_Pos          (0U)\n#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)                /*!< 0x000000FF */\n#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk\n#define DCMI_ESUR_LSU_Pos          (8U)\n#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)                /*!< 0x0000FF00 */\n#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk\n#define DCMI_ESUR_LEU_Pos          (16U)\n#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)                /*!< 0x00FF0000 */\n#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk\n#define DCMI_ESUR_FEU_Pos          (24U)\n#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)                /*!< 0xFF000000 */\n#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk\n\n/********************  Bits definition for DCMI_CWSTRT register  ******************/\n#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)\n#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)        /*!< 0x00003FFF */\n#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk\n#define DCMI_CWSTRT_VST_Pos        (16U)\n#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)            /*!< 0x1FFF0000 */\n#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk\n\n/********************  Bits definition for DCMI_CWSIZE register  ******************/\n#define DCMI_CWSIZE_CAPCNT_Pos     (0U)\n#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)         /*!< 0x00003FFF */\n#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk\n#define DCMI_CWSIZE_VLINE_Pos      (16U)\n#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)          /*!< 0x3FFF0000 */\n#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk\n\n/********************  Bits definition for DCMI_DR register  *********************/\n#define DCMI_DR_BYTE0_Pos          (0U)\n#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)                /*!< 0x000000FF */\n#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk\n#define DCMI_DR_BYTE1_Pos          (8U)\n#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)                /*!< 0x0000FF00 */\n#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk\n#define DCMI_DR_BYTE2_Pos          (16U)\n#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)                /*!< 0x00FF0000 */\n#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk\n#define DCMI_DR_BYTE3_Pos          (24U)\n#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)                /*!< 0xFF000000 */\n#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                             DMA Controller                                 */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DMA_SxCR register  *****************/\n#define DMA_SxCR_CHSEL_Pos       (25U)\n#define DMA_SxCR_CHSEL_Msk       (0x7UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */\n#define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk\n#define DMA_SxCR_CHSEL_0         0x02000000U\n#define DMA_SxCR_CHSEL_1         0x04000000U\n#define DMA_SxCR_CHSEL_2         0x08000000U\n#define DMA_SxCR_MBURST_Pos      (23U)\n#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */\n#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk\n#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */\n#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */\n#define DMA_SxCR_PBURST_Pos      (21U)\n#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */\n#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk\n#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */\n#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */\n#define DMA_SxCR_CT_Pos          (19U)\n#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */\n#define DMA_SxCR_CT              DMA_SxCR_CT_Msk\n#define DMA_SxCR_DBM_Pos         (18U)\n#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */\n#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk\n#define DMA_SxCR_PL_Pos          (16U)\n#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */\n#define DMA_SxCR_PL              DMA_SxCR_PL_Msk\n#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */\n#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */\n#define DMA_SxCR_PINCOS_Pos      (15U)\n#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */\n#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk\n#define DMA_SxCR_MSIZE_Pos       (13U)\n#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */\n#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk\n#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */\n#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */\n#define DMA_SxCR_PSIZE_Pos       (11U)\n#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */\n#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk\n#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */\n#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */\n#define DMA_SxCR_MINC_Pos        (10U)\n#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */\n#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk\n#define DMA_SxCR_PINC_Pos        (9U)\n#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */\n#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk\n#define DMA_SxCR_CIRC_Pos        (8U)\n#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */\n#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk\n#define DMA_SxCR_DIR_Pos         (6U)\n#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */\n#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk\n#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */\n#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */\n#define DMA_SxCR_PFCTRL_Pos      (5U)\n#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */\n#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk\n#define DMA_SxCR_TCIE_Pos        (4U)\n#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */\n#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk\n#define DMA_SxCR_HTIE_Pos        (3U)\n#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */\n#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk\n#define DMA_SxCR_TEIE_Pos        (2U)\n#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */\n#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk\n#define DMA_SxCR_DMEIE_Pos       (1U)\n#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */\n#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk\n#define DMA_SxCR_EN_Pos          (0U)\n#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */\n#define DMA_SxCR_EN              DMA_SxCR_EN_Msk\n\n/* Legacy defines */\n#define DMA_SxCR_ACK_Pos         (20U)\n#define DMA_SxCR_ACK_Msk         (0x1UL << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */\n#define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk\n\n/********************  Bits definition for DMA_SxCNDTR register  **************/\n#define DMA_SxNDT_Pos            (0U)\n#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */\n#define DMA_SxNDT                DMA_SxNDT_Msk\n#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */\n#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */\n#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */\n#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */\n#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */\n#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */\n#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */\n#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */\n#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */\n#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */\n#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */\n#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */\n#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */\n#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */\n#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */\n#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */\n\n/********************  Bits definition for DMA_SxFCR register  ****************/\n#define DMA_SxFCR_FEIE_Pos       (7U)\n#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */\n#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk\n#define DMA_SxFCR_FS_Pos         (3U)\n#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */\n#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk\n#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */\n#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */\n#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */\n#define DMA_SxFCR_DMDIS_Pos      (2U)\n#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */\n#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk\n#define DMA_SxFCR_FTH_Pos        (0U)\n#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */\n#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk\n#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */\n#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */\n\n/********************  Bits definition for DMA_LISR register  *****************/\n#define DMA_LISR_TCIF3_Pos       (27U)\n#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */\n#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk\n#define DMA_LISR_HTIF3_Pos       (26U)\n#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */\n#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk\n#define DMA_LISR_TEIF3_Pos       (25U)\n#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */\n#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk\n#define DMA_LISR_DMEIF3_Pos      (24U)\n#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */\n#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk\n#define DMA_LISR_FEIF3_Pos       (22U)\n#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */\n#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk\n#define DMA_LISR_TCIF2_Pos       (21U)\n#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */\n#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk\n#define DMA_LISR_HTIF2_Pos       (20U)\n#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */\n#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk\n#define DMA_LISR_TEIF2_Pos       (19U)\n#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */\n#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk\n#define DMA_LISR_DMEIF2_Pos      (18U)\n#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */\n#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk\n#define DMA_LISR_FEIF2_Pos       (16U)\n#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */\n#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk\n#define DMA_LISR_TCIF1_Pos       (11U)\n#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */\n#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk\n#define DMA_LISR_HTIF1_Pos       (10U)\n#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */\n#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk\n#define DMA_LISR_TEIF1_Pos       (9U)\n#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */\n#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk\n#define DMA_LISR_DMEIF1_Pos      (8U)\n#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */\n#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk\n#define DMA_LISR_FEIF1_Pos       (6U)\n#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */\n#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk\n#define DMA_LISR_TCIF0_Pos       (5U)\n#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */\n#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk\n#define DMA_LISR_HTIF0_Pos       (4U)\n#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */\n#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk\n#define DMA_LISR_TEIF0_Pos       (3U)\n#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */\n#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk\n#define DMA_LISR_DMEIF0_Pos      (2U)\n#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */\n#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk\n#define DMA_LISR_FEIF0_Pos       (0U)\n#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */\n#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk\n\n/********************  Bits definition for DMA_HISR register  *****************/\n#define DMA_HISR_TCIF7_Pos       (27U)\n#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */\n#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk\n#define DMA_HISR_HTIF7_Pos       (26U)\n#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */\n#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk\n#define DMA_HISR_TEIF7_Pos       (25U)\n#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */\n#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk\n#define DMA_HISR_DMEIF7_Pos      (24U)\n#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */\n#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk\n#define DMA_HISR_FEIF7_Pos       (22U)\n#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */\n#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk\n#define DMA_HISR_TCIF6_Pos       (21U)\n#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */\n#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk\n#define DMA_HISR_HTIF6_Pos       (20U)\n#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */\n#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk\n#define DMA_HISR_TEIF6_Pos       (19U)\n#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */\n#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk\n#define DMA_HISR_DMEIF6_Pos      (18U)\n#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */\n#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk\n#define DMA_HISR_FEIF6_Pos       (16U)\n#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */\n#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk\n#define DMA_HISR_TCIF5_Pos       (11U)\n#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */\n#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk\n#define DMA_HISR_HTIF5_Pos       (10U)\n#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */\n#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk\n#define DMA_HISR_TEIF5_Pos       (9U)\n#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */\n#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk\n#define DMA_HISR_DMEIF5_Pos      (8U)\n#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */\n#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk\n#define DMA_HISR_FEIF5_Pos       (6U)\n#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */\n#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk\n#define DMA_HISR_TCIF4_Pos       (5U)\n#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */\n#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk\n#define DMA_HISR_HTIF4_Pos       (4U)\n#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */\n#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk\n#define DMA_HISR_TEIF4_Pos       (3U)\n#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */\n#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk\n#define DMA_HISR_DMEIF4_Pos      (2U)\n#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */\n#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk\n#define DMA_HISR_FEIF4_Pos       (0U)\n#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */\n#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk\n\n/********************  Bits definition for DMA_LIFCR register  ****************/\n#define DMA_LIFCR_CTCIF3_Pos     (27U)\n#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */\n#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk\n#define DMA_LIFCR_CHTIF3_Pos     (26U)\n#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */\n#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk\n#define DMA_LIFCR_CTEIF3_Pos     (25U)\n#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */\n#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk\n#define DMA_LIFCR_CDMEIF3_Pos    (24U)\n#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */\n#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk\n#define DMA_LIFCR_CFEIF3_Pos     (22U)\n#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */\n#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk\n#define DMA_LIFCR_CTCIF2_Pos     (21U)\n#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */\n#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk\n#define DMA_LIFCR_CHTIF2_Pos     (20U)\n#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */\n#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk\n#define DMA_LIFCR_CTEIF2_Pos     (19U)\n#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */\n#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk\n#define DMA_LIFCR_CDMEIF2_Pos    (18U)\n#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */\n#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk\n#define DMA_LIFCR_CFEIF2_Pos     (16U)\n#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */\n#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk\n#define DMA_LIFCR_CTCIF1_Pos     (11U)\n#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */\n#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk\n#define DMA_LIFCR_CHTIF1_Pos     (10U)\n#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */\n#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk\n#define DMA_LIFCR_CTEIF1_Pos     (9U)\n#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */\n#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk\n#define DMA_LIFCR_CDMEIF1_Pos    (8U)\n#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */\n#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk\n#define DMA_LIFCR_CFEIF1_Pos     (6U)\n#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */\n#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk\n#define DMA_LIFCR_CTCIF0_Pos     (5U)\n#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */\n#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk\n#define DMA_LIFCR_CHTIF0_Pos     (4U)\n#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */\n#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk\n#define DMA_LIFCR_CTEIF0_Pos     (3U)\n#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */\n#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk\n#define DMA_LIFCR_CDMEIF0_Pos    (2U)\n#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */\n#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk\n#define DMA_LIFCR_CFEIF0_Pos     (0U)\n#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */\n#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk\n\n/********************  Bits definition for DMA_HIFCR  register  ****************/\n#define DMA_HIFCR_CTCIF7_Pos     (27U)\n#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */\n#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk\n#define DMA_HIFCR_CHTIF7_Pos     (26U)\n#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */\n#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk\n#define DMA_HIFCR_CTEIF7_Pos     (25U)\n#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */\n#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk\n#define DMA_HIFCR_CDMEIF7_Pos    (24U)\n#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */\n#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk\n#define DMA_HIFCR_CFEIF7_Pos     (22U)\n#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */\n#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk\n#define DMA_HIFCR_CTCIF6_Pos     (21U)\n#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */\n#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk\n#define DMA_HIFCR_CHTIF6_Pos     (20U)\n#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */\n#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk\n#define DMA_HIFCR_CTEIF6_Pos     (19U)\n#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */\n#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk\n#define DMA_HIFCR_CDMEIF6_Pos    (18U)\n#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */\n#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk\n#define DMA_HIFCR_CFEIF6_Pos     (16U)\n#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */\n#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk\n#define DMA_HIFCR_CTCIF5_Pos     (11U)\n#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */\n#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk\n#define DMA_HIFCR_CHTIF5_Pos     (10U)\n#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */\n#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk\n#define DMA_HIFCR_CTEIF5_Pos     (9U)\n#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */\n#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk\n#define DMA_HIFCR_CDMEIF5_Pos    (8U)\n#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */\n#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk\n#define DMA_HIFCR_CFEIF5_Pos     (6U)\n#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */\n#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk\n#define DMA_HIFCR_CTCIF4_Pos     (5U)\n#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */\n#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk\n#define DMA_HIFCR_CHTIF4_Pos     (4U)\n#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */\n#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk\n#define DMA_HIFCR_CTEIF4_Pos     (3U)\n#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */\n#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk\n#define DMA_HIFCR_CDMEIF4_Pos    (2U)\n#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */\n#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk\n#define DMA_HIFCR_CFEIF4_Pos     (0U)\n#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */\n#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk\n\n/******************  Bit definition for DMA_SxPAR register  ********************/\n#define DMA_SxPAR_PA_Pos         (0U)\n#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */\n#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */\n\n/******************  Bit definition for DMA_SxM0AR register  ********************/\n#define DMA_SxM0AR_M0A_Pos       (0U)\n#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */\n\n/******************  Bit definition for DMA_SxM1AR register  ********************/\n#define DMA_SxM1AR_M1A_Pos       (0U)\n#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                    External Interrupt/Event Controller                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for EXTI_IMR register  *******************/\n#define EXTI_IMR_MR0_Pos          (0U)\n#define EXTI_IMR_MR0_Msk          (0x1UL << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */\n#define EXTI_IMR_MR1_Pos          (1U)\n#define EXTI_IMR_MR1_Msk          (0x1UL << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */\n#define EXTI_IMR_MR2_Pos          (2U)\n#define EXTI_IMR_MR2_Msk          (0x1UL << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */\n#define EXTI_IMR_MR3_Pos          (3U)\n#define EXTI_IMR_MR3_Msk          (0x1UL << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */\n#define EXTI_IMR_MR4_Pos          (4U)\n#define EXTI_IMR_MR4_Msk          (0x1UL << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */\n#define EXTI_IMR_MR5_Pos          (5U)\n#define EXTI_IMR_MR5_Msk          (0x1UL << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */\n#define EXTI_IMR_MR6_Pos          (6U)\n#define EXTI_IMR_MR6_Msk          (0x1UL << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */\n#define EXTI_IMR_MR7_Pos          (7U)\n#define EXTI_IMR_MR7_Msk          (0x1UL << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */\n#define EXTI_IMR_MR8_Pos          (8U)\n#define EXTI_IMR_MR8_Msk          (0x1UL << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */\n#define EXTI_IMR_MR9_Pos          (9U)\n#define EXTI_IMR_MR9_Msk          (0x1UL << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */\n#define EXTI_IMR_MR10_Pos         (10U)\n#define EXTI_IMR_MR10_Msk         (0x1UL << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */\n#define EXTI_IMR_MR11_Pos         (11U)\n#define EXTI_IMR_MR11_Msk         (0x1UL << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */\n#define EXTI_IMR_MR12_Pos         (12U)\n#define EXTI_IMR_MR12_Msk         (0x1UL << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */\n#define EXTI_IMR_MR13_Pos         (13U)\n#define EXTI_IMR_MR13_Msk         (0x1UL << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */\n#define EXTI_IMR_MR14_Pos         (14U)\n#define EXTI_IMR_MR14_Msk         (0x1UL << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */\n#define EXTI_IMR_MR15_Pos         (15U)\n#define EXTI_IMR_MR15_Msk         (0x1UL << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */\n#define EXTI_IMR_MR16_Pos         (16U)\n#define EXTI_IMR_MR16_Msk         (0x1UL << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */\n#define EXTI_IMR_MR17_Pos         (17U)\n#define EXTI_IMR_MR17_Msk         (0x1UL << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */\n#define EXTI_IMR_MR18_Pos         (18U)\n#define EXTI_IMR_MR18_Msk         (0x1UL << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */\n#define EXTI_IMR_MR19_Pos         (19U)\n#define EXTI_IMR_MR19_Msk         (0x1UL << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */\n#define EXTI_IMR_MR20_Pos         (20U)\n#define EXTI_IMR_MR20_Msk         (0x1UL << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */\n#define EXTI_IMR_MR21_Pos         (21U)\n#define EXTI_IMR_MR21_Msk         (0x1UL << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */\n#define EXTI_IMR_MR22_Pos         (22U)\n#define EXTI_IMR_MR22_Msk         (0x1UL << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */\n\n/* Reference Defines */\n#define  EXTI_IMR_IM0                        EXTI_IMR_MR0\n#define  EXTI_IMR_IM1                        EXTI_IMR_MR1\n#define  EXTI_IMR_IM2                        EXTI_IMR_MR2\n#define  EXTI_IMR_IM3                        EXTI_IMR_MR3\n#define  EXTI_IMR_IM4                        EXTI_IMR_MR4\n#define  EXTI_IMR_IM5                        EXTI_IMR_MR5\n#define  EXTI_IMR_IM6                        EXTI_IMR_MR6\n#define  EXTI_IMR_IM7                        EXTI_IMR_MR7\n#define  EXTI_IMR_IM8                        EXTI_IMR_MR8\n#define  EXTI_IMR_IM9                        EXTI_IMR_MR9\n#define  EXTI_IMR_IM10                       EXTI_IMR_MR10\n#define  EXTI_IMR_IM11                       EXTI_IMR_MR11\n#define  EXTI_IMR_IM12                       EXTI_IMR_MR12\n#define  EXTI_IMR_IM13                       EXTI_IMR_MR13\n#define  EXTI_IMR_IM14                       EXTI_IMR_MR14\n#define  EXTI_IMR_IM15                       EXTI_IMR_MR15\n#define  EXTI_IMR_IM16                       EXTI_IMR_MR16\n#define  EXTI_IMR_IM17                       EXTI_IMR_MR17\n#define  EXTI_IMR_IM18                       EXTI_IMR_MR18\n#define  EXTI_IMR_IM19                       EXTI_IMR_MR19\n#define  EXTI_IMR_IM20                       EXTI_IMR_MR20\n#define  EXTI_IMR_IM21                       EXTI_IMR_MR21\n#define  EXTI_IMR_IM22                       EXTI_IMR_MR22\n#define EXTI_IMR_IM_Pos           (0U)\n#define EXTI_IMR_IM_Msk           (0x7FFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x007FFFFF */\n#define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */\n\n/*******************  Bit definition for EXTI_EMR register  *******************/\n#define EXTI_EMR_MR0_Pos          (0U)\n#define EXTI_EMR_MR0_Msk          (0x1UL << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */\n#define EXTI_EMR_MR1_Pos          (1U)\n#define EXTI_EMR_MR1_Msk          (0x1UL << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */\n#define EXTI_EMR_MR2_Pos          (2U)\n#define EXTI_EMR_MR2_Msk          (0x1UL << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */\n#define EXTI_EMR_MR3_Pos          (3U)\n#define EXTI_EMR_MR3_Msk          (0x1UL << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */\n#define EXTI_EMR_MR4_Pos          (4U)\n#define EXTI_EMR_MR4_Msk          (0x1UL << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */\n#define EXTI_EMR_MR5_Pos          (5U)\n#define EXTI_EMR_MR5_Msk          (0x1UL << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */\n#define EXTI_EMR_MR6_Pos          (6U)\n#define EXTI_EMR_MR6_Msk          (0x1UL << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */\n#define EXTI_EMR_MR7_Pos          (7U)\n#define EXTI_EMR_MR7_Msk          (0x1UL << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */\n#define EXTI_EMR_MR8_Pos          (8U)\n#define EXTI_EMR_MR8_Msk          (0x1UL << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */\n#define EXTI_EMR_MR9_Pos          (9U)\n#define EXTI_EMR_MR9_Msk          (0x1UL << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */\n#define EXTI_EMR_MR10_Pos         (10U)\n#define EXTI_EMR_MR10_Msk         (0x1UL << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */\n#define EXTI_EMR_MR11_Pos         (11U)\n#define EXTI_EMR_MR11_Msk         (0x1UL << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */\n#define EXTI_EMR_MR12_Pos         (12U)\n#define EXTI_EMR_MR12_Msk         (0x1UL << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */\n#define EXTI_EMR_MR13_Pos         (13U)\n#define EXTI_EMR_MR13_Msk         (0x1UL << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */\n#define EXTI_EMR_MR14_Pos         (14U)\n#define EXTI_EMR_MR14_Msk         (0x1UL << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */\n#define EXTI_EMR_MR15_Pos         (15U)\n#define EXTI_EMR_MR15_Msk         (0x1UL << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */\n#define EXTI_EMR_MR16_Pos         (16U)\n#define EXTI_EMR_MR16_Msk         (0x1UL << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */\n#define EXTI_EMR_MR17_Pos         (17U)\n#define EXTI_EMR_MR17_Msk         (0x1UL << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */\n#define EXTI_EMR_MR18_Pos         (18U)\n#define EXTI_EMR_MR18_Msk         (0x1UL << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */\n#define EXTI_EMR_MR19_Pos         (19U)\n#define EXTI_EMR_MR19_Msk         (0x1UL << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */\n#define EXTI_EMR_MR20_Pos         (20U)\n#define EXTI_EMR_MR20_Msk         (0x1UL << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */\n#define EXTI_EMR_MR21_Pos         (21U)\n#define EXTI_EMR_MR21_Msk         (0x1UL << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */\n#define EXTI_EMR_MR22_Pos         (22U)\n#define EXTI_EMR_MR22_Msk         (0x1UL << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */\n\n/* Reference Defines */\n#define  EXTI_EMR_EM0                        EXTI_EMR_MR0\n#define  EXTI_EMR_EM1                        EXTI_EMR_MR1\n#define  EXTI_EMR_EM2                        EXTI_EMR_MR2\n#define  EXTI_EMR_EM3                        EXTI_EMR_MR3\n#define  EXTI_EMR_EM4                        EXTI_EMR_MR4\n#define  EXTI_EMR_EM5                        EXTI_EMR_MR5\n#define  EXTI_EMR_EM6                        EXTI_EMR_MR6\n#define  EXTI_EMR_EM7                        EXTI_EMR_MR7\n#define  EXTI_EMR_EM8                        EXTI_EMR_MR8\n#define  EXTI_EMR_EM9                        EXTI_EMR_MR9\n#define  EXTI_EMR_EM10                       EXTI_EMR_MR10\n#define  EXTI_EMR_EM11                       EXTI_EMR_MR11\n#define  EXTI_EMR_EM12                       EXTI_EMR_MR12\n#define  EXTI_EMR_EM13                       EXTI_EMR_MR13\n#define  EXTI_EMR_EM14                       EXTI_EMR_MR14\n#define  EXTI_EMR_EM15                       EXTI_EMR_MR15\n#define  EXTI_EMR_EM16                       EXTI_EMR_MR16\n#define  EXTI_EMR_EM17                       EXTI_EMR_MR17\n#define  EXTI_EMR_EM18                       EXTI_EMR_MR18\n#define  EXTI_EMR_EM19                       EXTI_EMR_MR19\n#define  EXTI_EMR_EM20                       EXTI_EMR_MR20\n#define  EXTI_EMR_EM21                       EXTI_EMR_MR21\n#define  EXTI_EMR_EM22                       EXTI_EMR_MR22\n\n/******************  Bit definition for EXTI_RTSR register  *******************/\n#define EXTI_RTSR_TR0_Pos         (0U)\n#define EXTI_RTSR_TR0_Msk         (0x1UL << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */\n#define EXTI_RTSR_TR1_Pos         (1U)\n#define EXTI_RTSR_TR1_Msk         (0x1UL << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */\n#define EXTI_RTSR_TR2_Pos         (2U)\n#define EXTI_RTSR_TR2_Msk         (0x1UL << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */\n#define EXTI_RTSR_TR3_Pos         (3U)\n#define EXTI_RTSR_TR3_Msk         (0x1UL << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */\n#define EXTI_RTSR_TR4_Pos         (4U)\n#define EXTI_RTSR_TR4_Msk         (0x1UL << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */\n#define EXTI_RTSR_TR5_Pos         (5U)\n#define EXTI_RTSR_TR5_Msk         (0x1UL << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */\n#define EXTI_RTSR_TR6_Pos         (6U)\n#define EXTI_RTSR_TR6_Msk         (0x1UL << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */\n#define EXTI_RTSR_TR7_Pos         (7U)\n#define EXTI_RTSR_TR7_Msk         (0x1UL << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */\n#define EXTI_RTSR_TR8_Pos         (8U)\n#define EXTI_RTSR_TR8_Msk         (0x1UL << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */\n#define EXTI_RTSR_TR9_Pos         (9U)\n#define EXTI_RTSR_TR9_Msk         (0x1UL << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */\n#define EXTI_RTSR_TR10_Pos        (10U)\n#define EXTI_RTSR_TR10_Msk        (0x1UL << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */\n#define EXTI_RTSR_TR11_Pos        (11U)\n#define EXTI_RTSR_TR11_Msk        (0x1UL << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */\n#define EXTI_RTSR_TR12_Pos        (12U)\n#define EXTI_RTSR_TR12_Msk        (0x1UL << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */\n#define EXTI_RTSR_TR13_Pos        (13U)\n#define EXTI_RTSR_TR13_Msk        (0x1UL << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */\n#define EXTI_RTSR_TR14_Pos        (14U)\n#define EXTI_RTSR_TR14_Msk        (0x1UL << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */\n#define EXTI_RTSR_TR15_Pos        (15U)\n#define EXTI_RTSR_TR15_Msk        (0x1UL << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */\n#define EXTI_RTSR_TR16_Pos        (16U)\n#define EXTI_RTSR_TR16_Msk        (0x1UL << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */\n#define EXTI_RTSR_TR17_Pos        (17U)\n#define EXTI_RTSR_TR17_Msk        (0x1UL << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */\n#define EXTI_RTSR_TR18_Pos        (18U)\n#define EXTI_RTSR_TR18_Msk        (0x1UL << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */\n#define EXTI_RTSR_TR19_Pos        (19U)\n#define EXTI_RTSR_TR19_Msk        (0x1UL << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */\n#define EXTI_RTSR_TR20_Pos        (20U)\n#define EXTI_RTSR_TR20_Msk        (0x1UL << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */\n#define EXTI_RTSR_TR21_Pos        (21U)\n#define EXTI_RTSR_TR21_Msk        (0x1UL << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */\n#define EXTI_RTSR_TR22_Pos        (22U)\n#define EXTI_RTSR_TR22_Msk        (0x1UL << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_FTSR register  *******************/\n#define EXTI_FTSR_TR0_Pos         (0U)\n#define EXTI_FTSR_TR0_Msk         (0x1UL << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */\n#define EXTI_FTSR_TR1_Pos         (1U)\n#define EXTI_FTSR_TR1_Msk         (0x1UL << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */\n#define EXTI_FTSR_TR2_Pos         (2U)\n#define EXTI_FTSR_TR2_Msk         (0x1UL << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */\n#define EXTI_FTSR_TR3_Pos         (3U)\n#define EXTI_FTSR_TR3_Msk         (0x1UL << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */\n#define EXTI_FTSR_TR4_Pos         (4U)\n#define EXTI_FTSR_TR4_Msk         (0x1UL << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */\n#define EXTI_FTSR_TR5_Pos         (5U)\n#define EXTI_FTSR_TR5_Msk         (0x1UL << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */\n#define EXTI_FTSR_TR6_Pos         (6U)\n#define EXTI_FTSR_TR6_Msk         (0x1UL << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */\n#define EXTI_FTSR_TR7_Pos         (7U)\n#define EXTI_FTSR_TR7_Msk         (0x1UL << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */\n#define EXTI_FTSR_TR8_Pos         (8U)\n#define EXTI_FTSR_TR8_Msk         (0x1UL << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */\n#define EXTI_FTSR_TR9_Pos         (9U)\n#define EXTI_FTSR_TR9_Msk         (0x1UL << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */\n#define EXTI_FTSR_TR10_Pos        (10U)\n#define EXTI_FTSR_TR10_Msk        (0x1UL << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */\n#define EXTI_FTSR_TR11_Pos        (11U)\n#define EXTI_FTSR_TR11_Msk        (0x1UL << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */\n#define EXTI_FTSR_TR12_Pos        (12U)\n#define EXTI_FTSR_TR12_Msk        (0x1UL << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */\n#define EXTI_FTSR_TR13_Pos        (13U)\n#define EXTI_FTSR_TR13_Msk        (0x1UL << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */\n#define EXTI_FTSR_TR14_Pos        (14U)\n#define EXTI_FTSR_TR14_Msk        (0x1UL << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */\n#define EXTI_FTSR_TR15_Pos        (15U)\n#define EXTI_FTSR_TR15_Msk        (0x1UL << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */\n#define EXTI_FTSR_TR16_Pos        (16U)\n#define EXTI_FTSR_TR16_Msk        (0x1UL << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */\n#define EXTI_FTSR_TR17_Pos        (17U)\n#define EXTI_FTSR_TR17_Msk        (0x1UL << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */\n#define EXTI_FTSR_TR18_Pos        (18U)\n#define EXTI_FTSR_TR18_Msk        (0x1UL << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */\n#define EXTI_FTSR_TR19_Pos        (19U)\n#define EXTI_FTSR_TR19_Msk        (0x1UL << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */\n#define EXTI_FTSR_TR20_Pos        (20U)\n#define EXTI_FTSR_TR20_Msk        (0x1UL << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */\n#define EXTI_FTSR_TR21_Pos        (21U)\n#define EXTI_FTSR_TR21_Msk        (0x1UL << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */\n#define EXTI_FTSR_TR22_Pos        (22U)\n#define EXTI_FTSR_TR22_Msk        (0x1UL << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_SWIER register  ******************/\n#define EXTI_SWIER_SWIER0_Pos     (0U)\n#define EXTI_SWIER_SWIER0_Msk     (0x1UL << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */\n#define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */\n#define EXTI_SWIER_SWIER1_Pos     (1U)\n#define EXTI_SWIER_SWIER1_Msk     (0x1UL << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */\n#define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */\n#define EXTI_SWIER_SWIER2_Pos     (2U)\n#define EXTI_SWIER_SWIER2_Msk     (0x1UL << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */\n#define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */\n#define EXTI_SWIER_SWIER3_Pos     (3U)\n#define EXTI_SWIER_SWIER3_Msk     (0x1UL << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */\n#define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */\n#define EXTI_SWIER_SWIER4_Pos     (4U)\n#define EXTI_SWIER_SWIER4_Msk     (0x1UL << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */\n#define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */\n#define EXTI_SWIER_SWIER5_Pos     (5U)\n#define EXTI_SWIER_SWIER5_Msk     (0x1UL << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */\n#define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */\n#define EXTI_SWIER_SWIER6_Pos     (6U)\n#define EXTI_SWIER_SWIER6_Msk     (0x1UL << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */\n#define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */\n#define EXTI_SWIER_SWIER7_Pos     (7U)\n#define EXTI_SWIER_SWIER7_Msk     (0x1UL << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */\n#define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */\n#define EXTI_SWIER_SWIER8_Pos     (8U)\n#define EXTI_SWIER_SWIER8_Msk     (0x1UL << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */\n#define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */\n#define EXTI_SWIER_SWIER9_Pos     (9U)\n#define EXTI_SWIER_SWIER9_Msk     (0x1UL << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */\n#define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */\n#define EXTI_SWIER_SWIER10_Pos    (10U)\n#define EXTI_SWIER_SWIER10_Msk    (0x1UL << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */\n#define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */\n#define EXTI_SWIER_SWIER11_Pos    (11U)\n#define EXTI_SWIER_SWIER11_Msk    (0x1UL << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */\n#define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */\n#define EXTI_SWIER_SWIER12_Pos    (12U)\n#define EXTI_SWIER_SWIER12_Msk    (0x1UL << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */\n#define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */\n#define EXTI_SWIER_SWIER13_Pos    (13U)\n#define EXTI_SWIER_SWIER13_Msk    (0x1UL << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */\n#define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */\n#define EXTI_SWIER_SWIER14_Pos    (14U)\n#define EXTI_SWIER_SWIER14_Msk    (0x1UL << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */\n#define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */\n#define EXTI_SWIER_SWIER15_Pos    (15U)\n#define EXTI_SWIER_SWIER15_Msk    (0x1UL << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */\n#define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */\n#define EXTI_SWIER_SWIER16_Pos    (16U)\n#define EXTI_SWIER_SWIER16_Msk    (0x1UL << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */\n#define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */\n#define EXTI_SWIER_SWIER17_Pos    (17U)\n#define EXTI_SWIER_SWIER17_Msk    (0x1UL << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */\n#define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */\n#define EXTI_SWIER_SWIER18_Pos    (18U)\n#define EXTI_SWIER_SWIER18_Msk    (0x1UL << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */\n#define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */\n#define EXTI_SWIER_SWIER19_Pos    (19U)\n#define EXTI_SWIER_SWIER19_Msk    (0x1UL << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */\n#define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */\n#define EXTI_SWIER_SWIER20_Pos    (20U)\n#define EXTI_SWIER_SWIER20_Msk    (0x1UL << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */\n#define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */\n#define EXTI_SWIER_SWIER21_Pos    (21U)\n#define EXTI_SWIER_SWIER21_Msk    (0x1UL << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */\n#define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */\n#define EXTI_SWIER_SWIER22_Pos    (22U)\n#define EXTI_SWIER_SWIER22_Msk    (0x1UL << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */\n#define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */\n\n/*******************  Bit definition for EXTI_PR register  ********************/\n#define EXTI_PR_PR0_Pos           (0U)\n#define EXTI_PR_PR0_Msk           (0x1UL << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */\n#define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */\n#define EXTI_PR_PR1_Pos           (1U)\n#define EXTI_PR_PR1_Msk           (0x1UL << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */\n#define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */\n#define EXTI_PR_PR2_Pos           (2U)\n#define EXTI_PR_PR2_Msk           (0x1UL << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */\n#define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */\n#define EXTI_PR_PR3_Pos           (3U)\n#define EXTI_PR_PR3_Msk           (0x1UL << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */\n#define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */\n#define EXTI_PR_PR4_Pos           (4U)\n#define EXTI_PR_PR4_Msk           (0x1UL << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */\n#define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */\n#define EXTI_PR_PR5_Pos           (5U)\n#define EXTI_PR_PR5_Msk           (0x1UL << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */\n#define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */\n#define EXTI_PR_PR6_Pos           (6U)\n#define EXTI_PR_PR6_Msk           (0x1UL << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */\n#define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */\n#define EXTI_PR_PR7_Pos           (7U)\n#define EXTI_PR_PR7_Msk           (0x1UL << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */\n#define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */\n#define EXTI_PR_PR8_Pos           (8U)\n#define EXTI_PR_PR8_Msk           (0x1UL << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */\n#define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */\n#define EXTI_PR_PR9_Pos           (9U)\n#define EXTI_PR_PR9_Msk           (0x1UL << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */\n#define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */\n#define EXTI_PR_PR10_Pos          (10U)\n#define EXTI_PR_PR10_Msk          (0x1UL << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */\n#define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */\n#define EXTI_PR_PR11_Pos          (11U)\n#define EXTI_PR_PR11_Msk          (0x1UL << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */\n#define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */\n#define EXTI_PR_PR12_Pos          (12U)\n#define EXTI_PR_PR12_Msk          (0x1UL << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */\n#define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */\n#define EXTI_PR_PR13_Pos          (13U)\n#define EXTI_PR_PR13_Msk          (0x1UL << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */\n#define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */\n#define EXTI_PR_PR14_Pos          (14U)\n#define EXTI_PR_PR14_Msk          (0x1UL << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */\n#define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */\n#define EXTI_PR_PR15_Pos          (15U)\n#define EXTI_PR_PR15_Msk          (0x1UL << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */\n#define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */\n#define EXTI_PR_PR16_Pos          (16U)\n#define EXTI_PR_PR16_Msk          (0x1UL << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */\n#define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */\n#define EXTI_PR_PR17_Pos          (17U)\n#define EXTI_PR_PR17_Msk          (0x1UL << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */\n#define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */\n#define EXTI_PR_PR18_Pos          (18U)\n#define EXTI_PR_PR18_Msk          (0x1UL << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */\n#define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */\n#define EXTI_PR_PR19_Pos          (19U)\n#define EXTI_PR_PR19_Msk          (0x1UL << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */\n#define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */\n#define EXTI_PR_PR20_Pos          (20U)\n#define EXTI_PR_PR20_Msk          (0x1UL << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */\n#define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */\n#define EXTI_PR_PR21_Pos          (21U)\n#define EXTI_PR_PR21_Msk          (0x1UL << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */\n#define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */\n#define EXTI_PR_PR22_Pos          (22U)\n#define EXTI_PR_PR22_Msk          (0x1UL << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */\n#define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    FLASH                                   */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bits definition for FLASH_ACR register  *****************/\n#define FLASH_ACR_LATENCY_Pos          (0U)\n#define FLASH_ACR_LATENCY_Msk          (0xFUL << FLASH_ACR_LATENCY_Pos)         /*!< 0x0000000F */\n#define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk\n#define FLASH_ACR_LATENCY_0WS          0x00000000U\n#define FLASH_ACR_LATENCY_1WS          0x00000001U\n#define FLASH_ACR_LATENCY_2WS          0x00000002U\n#define FLASH_ACR_LATENCY_3WS          0x00000003U\n#define FLASH_ACR_LATENCY_4WS          0x00000004U\n#define FLASH_ACR_LATENCY_5WS          0x00000005U\n#define FLASH_ACR_LATENCY_6WS          0x00000006U\n#define FLASH_ACR_LATENCY_7WS          0x00000007U\n\n#define FLASH_ACR_LATENCY_8WS          0x00000008U\n#define FLASH_ACR_LATENCY_9WS          0x00000009U\n#define FLASH_ACR_LATENCY_10WS         0x0000000AU\n#define FLASH_ACR_LATENCY_11WS         0x0000000BU\n#define FLASH_ACR_LATENCY_12WS         0x0000000CU\n#define FLASH_ACR_LATENCY_13WS         0x0000000DU\n#define FLASH_ACR_LATENCY_14WS         0x0000000EU\n#define FLASH_ACR_LATENCY_15WS         0x0000000FU\n#define FLASH_ACR_PRFTEN_Pos           (8U)\n#define FLASH_ACR_PRFTEN_Msk           (0x1UL << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */\n#define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk\n#define FLASH_ACR_ICEN_Pos             (9U)\n#define FLASH_ACR_ICEN_Msk             (0x1UL << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */\n#define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk\n#define FLASH_ACR_DCEN_Pos             (10U)\n#define FLASH_ACR_DCEN_Msk             (0x1UL << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */\n#define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk\n#define FLASH_ACR_ICRST_Pos            (11U)\n#define FLASH_ACR_ICRST_Msk            (0x1UL << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */\n#define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk\n#define FLASH_ACR_DCRST_Pos            (12U)\n#define FLASH_ACR_DCRST_Msk            (0x1UL << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */\n#define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk\n#define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)\n#define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */\n#define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk\n#define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)\n#define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */\n#define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk\n\n/*******************  Bits definition for FLASH_SR register  ******************/\n#define FLASH_SR_EOP_Pos               (0U)\n#define FLASH_SR_EOP_Msk               (0x1UL << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */\n#define FLASH_SR_EOP                   FLASH_SR_EOP_Msk\n#define FLASH_SR_SOP_Pos               (1U)\n#define FLASH_SR_SOP_Msk               (0x1UL << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */\n#define FLASH_SR_SOP                   FLASH_SR_SOP_Msk\n#define FLASH_SR_WRPERR_Pos            (4U)\n#define FLASH_SR_WRPERR_Msk            (0x1UL << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */\n#define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk\n#define FLASH_SR_PGAERR_Pos            (5U)\n#define FLASH_SR_PGAERR_Msk            (0x1UL << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */\n#define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk\n#define FLASH_SR_PGPERR_Pos            (6U)\n#define FLASH_SR_PGPERR_Msk            (0x1UL << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */\n#define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk\n#define FLASH_SR_PGSERR_Pos            (7U)\n#define FLASH_SR_PGSERR_Msk            (0x1UL << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */\n#define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk\n#define FLASH_SR_RDERR_Pos            (8U)\n#define FLASH_SR_RDERR_Msk            (0x1UL << FLASH_SR_RDERR_Pos)             /*!< 0x00000100 */\n#define FLASH_SR_RDERR                FLASH_SR_RDERR_Msk\n#define FLASH_SR_BSY_Pos               (16U)\n#define FLASH_SR_BSY_Msk               (0x1UL << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */\n#define FLASH_SR_BSY                   FLASH_SR_BSY_Msk\n\n/*******************  Bits definition for FLASH_CR register  ******************/\n#define FLASH_CR_PG_Pos                (0U)\n#define FLASH_CR_PG_Msk                (0x1UL << FLASH_CR_PG_Pos)               /*!< 0x00000001 */\n#define FLASH_CR_PG                    FLASH_CR_PG_Msk\n#define FLASH_CR_SER_Pos               (1U)\n#define FLASH_CR_SER_Msk               (0x1UL << FLASH_CR_SER_Pos)              /*!< 0x00000002 */\n#define FLASH_CR_SER                   FLASH_CR_SER_Msk\n#define FLASH_CR_MER_Pos               (2U)\n#define FLASH_CR_MER_Msk               (0x1UL << FLASH_CR_MER_Pos)              /*!< 0x00000004 */\n#define FLASH_CR_MER                   FLASH_CR_MER_Msk\n#define FLASH_CR_MER1                        FLASH_CR_MER\n#define FLASH_CR_SNB_Pos               (3U)\n#define FLASH_CR_SNB_Msk               (0x1FUL << FLASH_CR_SNB_Pos)             /*!< 0x000000F8 */\n#define FLASH_CR_SNB                   FLASH_CR_SNB_Msk\n#define FLASH_CR_SNB_0                 (0x01UL << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */\n#define FLASH_CR_SNB_1                 (0x02UL << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */\n#define FLASH_CR_SNB_2                 (0x04UL << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */\n#define FLASH_CR_SNB_3                 (0x08UL << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */\n#define FLASH_CR_SNB_4                 (0x10UL << FLASH_CR_SNB_Pos)             /*!< 0x00000080 */\n#define FLASH_CR_PSIZE_Pos             (8U)\n#define FLASH_CR_PSIZE_Msk             (0x3UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */\n#define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk\n#define FLASH_CR_PSIZE_0               (0x1UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */\n#define FLASH_CR_PSIZE_1               (0x2UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */\n#define FLASH_CR_MER2_Pos              (15U)\n#define FLASH_CR_MER2_Msk              (0x1UL << FLASH_CR_MER2_Pos)             /*!< 0x00008000 */\n#define FLASH_CR_MER2                  FLASH_CR_MER2_Msk\n#define FLASH_CR_STRT_Pos              (16U)\n#define FLASH_CR_STRT_Msk              (0x1UL << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */\n#define FLASH_CR_STRT                  FLASH_CR_STRT_Msk\n#define FLASH_CR_EOPIE_Pos             (24U)\n#define FLASH_CR_EOPIE_Msk             (0x1UL << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */\n#define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk\n#define FLASH_CR_LOCK_Pos              (31U)\n#define FLASH_CR_LOCK_Msk              (0x1UL << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */\n#define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk\n\n/*******************  Bits definition for FLASH_OPTCR register  ***************/\n#define FLASH_OPTCR_OPTLOCK_Pos        (0U)\n#define FLASH_OPTCR_OPTLOCK_Msk        (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */\n#define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk\n#define FLASH_OPTCR_OPTSTRT_Pos        (1U)\n#define FLASH_OPTCR_OPTSTRT_Msk        (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */\n#define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk\n\n#define FLASH_OPTCR_BOR_LEV_0          0x00000004U\n#define FLASH_OPTCR_BOR_LEV_1          0x00000008U\n#define FLASH_OPTCR_BOR_LEV_Pos        (2U)\n#define FLASH_OPTCR_BOR_LEV_Msk        (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */\n#define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk\n#define FLASH_OPTCR_BFB2_Pos           (4U)\n#define FLASH_OPTCR_BFB2_Msk           (0x1UL << FLASH_OPTCR_BFB2_Pos)          /*!< 0x00000010 */\n#define FLASH_OPTCR_BFB2               FLASH_OPTCR_BFB2_Msk\n#define FLASH_OPTCR_WDG_SW_Pos         (5U)\n#define FLASH_OPTCR_WDG_SW_Msk         (0x1UL << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */\n#define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk\n#define FLASH_OPTCR_nRST_STOP_Pos      (6U)\n#define FLASH_OPTCR_nRST_STOP_Msk      (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */\n#define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk\n#define FLASH_OPTCR_nRST_STDBY_Pos     (7U)\n#define FLASH_OPTCR_nRST_STDBY_Msk     (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */\n#define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk\n#define FLASH_OPTCR_RDP_Pos            (8U)\n#define FLASH_OPTCR_RDP_Msk            (0xFFUL << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */\n#define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk\n#define FLASH_OPTCR_RDP_0              (0x01UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */\n#define FLASH_OPTCR_RDP_1              (0x02UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */\n#define FLASH_OPTCR_RDP_2              (0x04UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */\n#define FLASH_OPTCR_RDP_3              (0x08UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */\n#define FLASH_OPTCR_RDP_4              (0x10UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */\n#define FLASH_OPTCR_RDP_5              (0x20UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */\n#define FLASH_OPTCR_RDP_6              (0x40UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */\n#define FLASH_OPTCR_RDP_7              (0x80UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */\n#define FLASH_OPTCR_nWRP_Pos           (16U)\n#define FLASH_OPTCR_nWRP_Msk           (0xFFFUL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x0FFF0000 */\n#define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk\n#define FLASH_OPTCR_nWRP_0             0x00010000U\n#define FLASH_OPTCR_nWRP_1             0x00020000U\n#define FLASH_OPTCR_nWRP_2             0x00040000U\n#define FLASH_OPTCR_nWRP_3             0x00080000U\n#define FLASH_OPTCR_nWRP_4             0x00100000U\n#define FLASH_OPTCR_nWRP_5             0x00200000U\n#define FLASH_OPTCR_nWRP_6             0x00400000U\n#define FLASH_OPTCR_nWRP_7             0x00800000U\n#define FLASH_OPTCR_nWRP_8             0x01000000U\n#define FLASH_OPTCR_nWRP_9             0x02000000U\n#define FLASH_OPTCR_nWRP_10            0x04000000U\n#define FLASH_OPTCR_nWRP_11            0x08000000U\n#define FLASH_OPTCR_DB1M_Pos           (30U)\n#define FLASH_OPTCR_DB1M_Msk           (0x1UL << FLASH_OPTCR_DB1M_Pos)          /*!< 0x40000000 */\n#define FLASH_OPTCR_DB1M               FLASH_OPTCR_DB1M_Msk\n#define FLASH_OPTCR_SPRMOD_Pos         (31U)\n#define FLASH_OPTCR_SPRMOD_Msk         (0x1UL << FLASH_OPTCR_SPRMOD_Pos)        /*!< 0x80000000 */\n#define FLASH_OPTCR_SPRMOD             FLASH_OPTCR_SPRMOD_Msk\n\n/******************  Bits definition for FLASH_OPTCR1 register  ***************/\n#define FLASH_OPTCR1_nWRP_Pos          (16U)\n#define FLASH_OPTCR1_nWRP_Msk          (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */\n#define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk\n#define FLASH_OPTCR1_nWRP_0            (0x001UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */\n#define FLASH_OPTCR1_nWRP_1            (0x002UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */\n#define FLASH_OPTCR1_nWRP_2            (0x004UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */\n#define FLASH_OPTCR1_nWRP_3            (0x008UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */\n#define FLASH_OPTCR1_nWRP_4            (0x010UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */\n#define FLASH_OPTCR1_nWRP_5            (0x020UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */\n#define FLASH_OPTCR1_nWRP_6            (0x040UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */\n#define FLASH_OPTCR1_nWRP_7            (0x080UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */\n#define FLASH_OPTCR1_nWRP_8            (0x100UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */\n#define FLASH_OPTCR1_nWRP_9            (0x200UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */\n#define FLASH_OPTCR1_nWRP_10           (0x400UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */\n#define FLASH_OPTCR1_nWRP_11           (0x800UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          Flexible Memory Controller                        */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for FMC_BCR1 register  *******************/\n#define FMC_BCR1_MBKEN_Pos          (0U)\n#define FMC_BCR1_MBKEN_Msk          (0x1UL << FMC_BCR1_MBKEN_Pos)               /*!< 0x00000001 */\n#define FMC_BCR1_MBKEN              FMC_BCR1_MBKEN_Msk                         /*!<Memory bank enable bit                 */\n#define FMC_BCR1_MUXEN_Pos          (1U)\n#define FMC_BCR1_MUXEN_Msk          (0x1UL << FMC_BCR1_MUXEN_Pos)               /*!< 0x00000002 */\n#define FMC_BCR1_MUXEN              FMC_BCR1_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */\n\n#define FMC_BCR1_MTYP_Pos           (2U)\n#define FMC_BCR1_MTYP_Msk           (0x3UL << FMC_BCR1_MTYP_Pos)                /*!< 0x0000000C */\n#define FMC_BCR1_MTYP               FMC_BCR1_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */\n#define FMC_BCR1_MTYP_0             (0x1UL << FMC_BCR1_MTYP_Pos)                /*!< 0x00000004 */\n#define FMC_BCR1_MTYP_1             (0x2UL << FMC_BCR1_MTYP_Pos)                /*!< 0x00000008 */\n\n#define FMC_BCR1_MWID_Pos           (4U)\n#define FMC_BCR1_MWID_Msk           (0x3UL << FMC_BCR1_MWID_Pos)                /*!< 0x00000030 */\n#define FMC_BCR1_MWID               FMC_BCR1_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */\n#define FMC_BCR1_MWID_0             (0x1UL << FMC_BCR1_MWID_Pos)                /*!< 0x00000010 */\n#define FMC_BCR1_MWID_1             (0x2UL << FMC_BCR1_MWID_Pos)                /*!< 0x00000020 */\n\n#define FMC_BCR1_FACCEN_Pos         (6U)\n#define FMC_BCR1_FACCEN_Msk         (0x1UL << FMC_BCR1_FACCEN_Pos)              /*!< 0x00000040 */\n#define FMC_BCR1_FACCEN             FMC_BCR1_FACCEN_Msk                        /*!<Flash access enable        */\n#define FMC_BCR1_BURSTEN_Pos        (8U)\n#define FMC_BCR1_BURSTEN_Msk        (0x1UL << FMC_BCR1_BURSTEN_Pos)             /*!< 0x00000100 */\n#define FMC_BCR1_BURSTEN            FMC_BCR1_BURSTEN_Msk                       /*!<Burst enable bit           */\n#define FMC_BCR1_WAITPOL_Pos        (9U)\n#define FMC_BCR1_WAITPOL_Msk        (0x1UL << FMC_BCR1_WAITPOL_Pos)             /*!< 0x00000200 */\n#define FMC_BCR1_WAITPOL            FMC_BCR1_WAITPOL_Msk                       /*!<Wait signal polarity bit   */\n#define FMC_BCR1_WAITCFG_Pos        (11U)\n#define FMC_BCR1_WAITCFG_Msk        (0x1UL << FMC_BCR1_WAITCFG_Pos)             /*!< 0x00000800 */\n#define FMC_BCR1_WAITCFG            FMC_BCR1_WAITCFG_Msk                       /*!<Wait timing configuration  */\n#define FMC_BCR1_WREN_Pos           (12U)\n#define FMC_BCR1_WREN_Msk           (0x1UL << FMC_BCR1_WREN_Pos)                /*!< 0x00001000 */\n#define FMC_BCR1_WREN               FMC_BCR1_WREN_Msk                          /*!<Write enable bit           */\n#define FMC_BCR1_WAITEN_Pos         (13U)\n#define FMC_BCR1_WAITEN_Msk         (0x1UL << FMC_BCR1_WAITEN_Pos)              /*!< 0x00002000 */\n#define FMC_BCR1_WAITEN             FMC_BCR1_WAITEN_Msk                        /*!<Wait enable bit            */\n#define FMC_BCR1_EXTMOD_Pos         (14U)\n#define FMC_BCR1_EXTMOD_Msk         (0x1UL << FMC_BCR1_EXTMOD_Pos)              /*!< 0x00004000 */\n#define FMC_BCR1_EXTMOD             FMC_BCR1_EXTMOD_Msk                        /*!<Extended mode enable       */\n#define FMC_BCR1_ASYNCWAIT_Pos      (15U)\n#define FMC_BCR1_ASYNCWAIT_Msk      (0x1UL << FMC_BCR1_ASYNCWAIT_Pos)           /*!< 0x00008000 */\n#define FMC_BCR1_ASYNCWAIT          FMC_BCR1_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */\n#define FMC_BCR1_CPSIZE_Pos         (16U)\n#define FMC_BCR1_CPSIZE_Msk         (0x7UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00070000 */\n#define FMC_BCR1_CPSIZE             FMC_BCR1_CPSIZE_Msk                        /*!<CRAM page size             */\n#define FMC_BCR1_CPSIZE_0           (0x1UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00010000 */\n#define FMC_BCR1_CPSIZE_1           (0x2UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00020000 */\n#define FMC_BCR1_CPSIZE_2           (0x4UL << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00040000 */\n#define FMC_BCR1_CBURSTRW_Pos       (19U)\n#define FMC_BCR1_CBURSTRW_Msk       (0x1UL << FMC_BCR1_CBURSTRW_Pos)            /*!< 0x00080000 */\n#define FMC_BCR1_CBURSTRW           FMC_BCR1_CBURSTRW_Msk                      /*!<Write burst enable         */\n#define FMC_BCR1_CCLKEN_Pos         (20U)\n#define FMC_BCR1_CCLKEN_Msk         (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */\n#define FMC_BCR1_CCLKEN             FMC_BCR1_CCLKEN_Msk                        /*!<Continous clock enable     */\n#define FMC_BCR1_WFDIS_Pos          (21U)\n#define FMC_BCR1_WFDIS_Msk          (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */\n#define FMC_BCR1_WFDIS              FMC_BCR1_WFDIS_Msk                         /*!<Write FIFO Disable         */\n\n/******************  Bit definition for FMC_BCR2 register  *******************/\n#define FMC_BCR2_MBKEN_Pos          (0U)\n#define FMC_BCR2_MBKEN_Msk          (0x1UL << FMC_BCR2_MBKEN_Pos)               /*!< 0x00000001 */\n#define FMC_BCR2_MBKEN              FMC_BCR2_MBKEN_Msk                         /*!<Memory bank enable bit                 */\n#define FMC_BCR2_MUXEN_Pos          (1U)\n#define FMC_BCR2_MUXEN_Msk          (0x1UL << FMC_BCR2_MUXEN_Pos)               /*!< 0x00000002 */\n#define FMC_BCR2_MUXEN              FMC_BCR2_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */\n\n#define FMC_BCR2_MTYP_Pos           (2U)\n#define FMC_BCR2_MTYP_Msk           (0x3UL << FMC_BCR2_MTYP_Pos)                /*!< 0x0000000C */\n#define FMC_BCR2_MTYP               FMC_BCR2_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */\n#define FMC_BCR2_MTYP_0             (0x1UL << FMC_BCR2_MTYP_Pos)                /*!< 0x00000004 */\n#define FMC_BCR2_MTYP_1             (0x2UL << FMC_BCR2_MTYP_Pos)                /*!< 0x00000008 */\n\n#define FMC_BCR2_MWID_Pos           (4U)\n#define FMC_BCR2_MWID_Msk           (0x3UL << FMC_BCR2_MWID_Pos)                /*!< 0x00000030 */\n#define FMC_BCR2_MWID               FMC_BCR2_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */\n#define FMC_BCR2_MWID_0             (0x1UL << FMC_BCR2_MWID_Pos)                /*!< 0x00000010 */\n#define FMC_BCR2_MWID_1             (0x2UL << FMC_BCR2_MWID_Pos)                /*!< 0x00000020 */\n\n#define FMC_BCR2_FACCEN_Pos         (6U)\n#define FMC_BCR2_FACCEN_Msk         (0x1UL << FMC_BCR2_FACCEN_Pos)              /*!< 0x00000040 */\n#define FMC_BCR2_FACCEN             FMC_BCR2_FACCEN_Msk                        /*!<Flash access enable        */\n#define FMC_BCR2_BURSTEN_Pos        (8U)\n#define FMC_BCR2_BURSTEN_Msk        (0x1UL << FMC_BCR2_BURSTEN_Pos)             /*!< 0x00000100 */\n#define FMC_BCR2_BURSTEN            FMC_BCR2_BURSTEN_Msk                       /*!<Burst enable bit           */\n#define FMC_BCR2_WAITPOL_Pos        (9U)\n#define FMC_BCR2_WAITPOL_Msk        (0x1UL << FMC_BCR2_WAITPOL_Pos)             /*!< 0x00000200 */\n#define FMC_BCR2_WAITPOL            FMC_BCR2_WAITPOL_Msk                       /*!<Wait signal polarity bit   */\n#define FMC_BCR2_WAITCFG_Pos        (11U)\n#define FMC_BCR2_WAITCFG_Msk        (0x1UL << FMC_BCR2_WAITCFG_Pos)             /*!< 0x00000800 */\n#define FMC_BCR2_WAITCFG            FMC_BCR2_WAITCFG_Msk                       /*!<Wait timing configuration  */\n#define FMC_BCR2_WREN_Pos           (12U)\n#define FMC_BCR2_WREN_Msk           (0x1UL << FMC_BCR2_WREN_Pos)                /*!< 0x00001000 */\n#define FMC_BCR2_WREN               FMC_BCR2_WREN_Msk                          /*!<Write enable bit           */\n#define FMC_BCR2_WAITEN_Pos         (13U)\n#define FMC_BCR2_WAITEN_Msk         (0x1UL << FMC_BCR2_WAITEN_Pos)              /*!< 0x00002000 */\n#define FMC_BCR2_WAITEN             FMC_BCR2_WAITEN_Msk                        /*!<Wait enable bit            */\n#define FMC_BCR2_EXTMOD_Pos         (14U)\n#define FMC_BCR2_EXTMOD_Msk         (0x1UL << FMC_BCR2_EXTMOD_Pos)              /*!< 0x00004000 */\n#define FMC_BCR2_EXTMOD             FMC_BCR2_EXTMOD_Msk                        /*!<Extended mode enable       */\n#define FMC_BCR2_ASYNCWAIT_Pos      (15U)\n#define FMC_BCR2_ASYNCWAIT_Msk      (0x1UL << FMC_BCR2_ASYNCWAIT_Pos)           /*!< 0x00008000 */\n#define FMC_BCR2_ASYNCWAIT          FMC_BCR2_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */\n#define FMC_BCR2_CBURSTRW_Pos       (19U)\n#define FMC_BCR2_CBURSTRW_Msk       (0x1UL << FMC_BCR2_CBURSTRW_Pos)            /*!< 0x00080000 */\n#define FMC_BCR2_CBURSTRW           FMC_BCR2_CBURSTRW_Msk                      /*!<Write burst enable         */\n\n/******************  Bit definition for FMC_BCR3 register  *******************/\n#define FMC_BCR3_MBKEN_Pos          (0U)\n#define FMC_BCR3_MBKEN_Msk          (0x1UL << FMC_BCR3_MBKEN_Pos)               /*!< 0x00000001 */\n#define FMC_BCR3_MBKEN              FMC_BCR3_MBKEN_Msk                         /*!<Memory bank enable bit                 */\n#define FMC_BCR3_MUXEN_Pos          (1U)\n#define FMC_BCR3_MUXEN_Msk          (0x1UL << FMC_BCR3_MUXEN_Pos)               /*!< 0x00000002 */\n#define FMC_BCR3_MUXEN              FMC_BCR3_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */\n\n#define FMC_BCR3_MTYP_Pos           (2U)\n#define FMC_BCR3_MTYP_Msk           (0x3UL << FMC_BCR3_MTYP_Pos)                /*!< 0x0000000C */\n#define FMC_BCR3_MTYP               FMC_BCR3_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */\n#define FMC_BCR3_MTYP_0             (0x1UL << FMC_BCR3_MTYP_Pos)                /*!< 0x00000004 */\n#define FMC_BCR3_MTYP_1             (0x2UL << FMC_BCR3_MTYP_Pos)                /*!< 0x00000008 */\n\n#define FMC_BCR3_MWID_Pos           (4U)\n#define FMC_BCR3_MWID_Msk           (0x3UL << FMC_BCR3_MWID_Pos)                /*!< 0x00000030 */\n#define FMC_BCR3_MWID               FMC_BCR3_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */\n#define FMC_BCR3_MWID_0             (0x1UL << FMC_BCR3_MWID_Pos)                /*!< 0x00000010 */\n#define FMC_BCR3_MWID_1             (0x2UL << FMC_BCR3_MWID_Pos)                /*!< 0x00000020 */\n\n#define FMC_BCR3_FACCEN_Pos         (6U)\n#define FMC_BCR3_FACCEN_Msk         (0x1UL << FMC_BCR3_FACCEN_Pos)              /*!< 0x00000040 */\n#define FMC_BCR3_FACCEN             FMC_BCR3_FACCEN_Msk                        /*!<Flash access enable        */\n#define FMC_BCR3_BURSTEN_Pos        (8U)\n#define FMC_BCR3_BURSTEN_Msk        (0x1UL << FMC_BCR3_BURSTEN_Pos)             /*!< 0x00000100 */\n#define FMC_BCR3_BURSTEN            FMC_BCR3_BURSTEN_Msk                       /*!<Burst enable bit           */\n#define FMC_BCR3_WAITPOL_Pos        (9U)\n#define FMC_BCR3_WAITPOL_Msk        (0x1UL << FMC_BCR3_WAITPOL_Pos)             /*!< 0x00000200 */\n#define FMC_BCR3_WAITPOL            FMC_BCR3_WAITPOL_Msk                       /*!<Wait signal polarity bit   */\n#define FMC_BCR3_WAITCFG_Pos        (11U)\n#define FMC_BCR3_WAITCFG_Msk        (0x1UL << FMC_BCR3_WAITCFG_Pos)             /*!< 0x00000800 */\n#define FMC_BCR3_WAITCFG            FMC_BCR3_WAITCFG_Msk                       /*!<Wait timing configuration  */\n#define FMC_BCR3_WREN_Pos           (12U)\n#define FMC_BCR3_WREN_Msk           (0x1UL << FMC_BCR3_WREN_Pos)                /*!< 0x00001000 */\n#define FMC_BCR3_WREN               FMC_BCR3_WREN_Msk                          /*!<Write enable bit           */\n#define FMC_BCR3_WAITEN_Pos         (13U)\n#define FMC_BCR3_WAITEN_Msk         (0x1UL << FMC_BCR3_WAITEN_Pos)              /*!< 0x00002000 */\n#define FMC_BCR3_WAITEN             FMC_BCR3_WAITEN_Msk                        /*!<Wait enable bit            */\n#define FMC_BCR3_EXTMOD_Pos         (14U)\n#define FMC_BCR3_EXTMOD_Msk         (0x1UL << FMC_BCR3_EXTMOD_Pos)              /*!< 0x00004000 */\n#define FMC_BCR3_EXTMOD             FMC_BCR3_EXTMOD_Msk                        /*!<Extended mode enable       */\n#define FMC_BCR3_ASYNCWAIT_Pos      (15U)\n#define FMC_BCR3_ASYNCWAIT_Msk      (0x1UL << FMC_BCR3_ASYNCWAIT_Pos)           /*!< 0x00008000 */\n#define FMC_BCR3_ASYNCWAIT          FMC_BCR3_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */\n#define FMC_BCR3_CBURSTRW_Pos       (19U)\n#define FMC_BCR3_CBURSTRW_Msk       (0x1UL << FMC_BCR3_CBURSTRW_Pos)            /*!< 0x00080000 */\n#define FMC_BCR3_CBURSTRW           FMC_BCR3_CBURSTRW_Msk                      /*!<Write burst enable         */\n\n/******************  Bit definition for FMC_BCR4 register  *******************/\n#define FMC_BCR4_MBKEN_Pos          (0U)\n#define FMC_BCR4_MBKEN_Msk          (0x1UL << FMC_BCR4_MBKEN_Pos)               /*!< 0x00000001 */\n#define FMC_BCR4_MBKEN              FMC_BCR4_MBKEN_Msk                         /*!<Memory bank enable bit                 */\n#define FMC_BCR4_MUXEN_Pos          (1U)\n#define FMC_BCR4_MUXEN_Msk          (0x1UL << FMC_BCR4_MUXEN_Pos)               /*!< 0x00000002 */\n#define FMC_BCR4_MUXEN              FMC_BCR4_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */\n\n#define FMC_BCR4_MTYP_Pos           (2U)\n#define FMC_BCR4_MTYP_Msk           (0x3UL << FMC_BCR4_MTYP_Pos)                /*!< 0x0000000C */\n#define FMC_BCR4_MTYP               FMC_BCR4_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */\n#define FMC_BCR4_MTYP_0             (0x1UL << FMC_BCR4_MTYP_Pos)                /*!< 0x00000004 */\n#define FMC_BCR4_MTYP_1             (0x2UL << FMC_BCR4_MTYP_Pos)                /*!< 0x00000008 */\n\n#define FMC_BCR4_MWID_Pos           (4U)\n#define FMC_BCR4_MWID_Msk           (0x3UL << FMC_BCR4_MWID_Pos)                /*!< 0x00000030 */\n#define FMC_BCR4_MWID               FMC_BCR4_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */\n#define FMC_BCR4_MWID_0             (0x1UL << FMC_BCR4_MWID_Pos)                /*!< 0x00000010 */\n#define FMC_BCR4_MWID_1             (0x2UL << FMC_BCR4_MWID_Pos)                /*!< 0x00000020 */\n\n#define FMC_BCR4_FACCEN_Pos         (6U)\n#define FMC_BCR4_FACCEN_Msk         (0x1UL << FMC_BCR4_FACCEN_Pos)              /*!< 0x00000040 */\n#define FMC_BCR4_FACCEN             FMC_BCR4_FACCEN_Msk                        /*!<Flash access enable        */\n#define FMC_BCR4_BURSTEN_Pos        (8U)\n#define FMC_BCR4_BURSTEN_Msk        (0x1UL << FMC_BCR4_BURSTEN_Pos)             /*!< 0x00000100 */\n#define FMC_BCR4_BURSTEN            FMC_BCR4_BURSTEN_Msk                       /*!<Burst enable bit           */\n#define FMC_BCR4_WAITPOL_Pos        (9U)\n#define FMC_BCR4_WAITPOL_Msk        (0x1UL << FMC_BCR4_WAITPOL_Pos)             /*!< 0x00000200 */\n#define FMC_BCR4_WAITPOL            FMC_BCR4_WAITPOL_Msk                       /*!<Wait signal polarity bit   */\n#define FMC_BCR4_WAITCFG_Pos        (11U)\n#define FMC_BCR4_WAITCFG_Msk        (0x1UL << FMC_BCR4_WAITCFG_Pos)             /*!< 0x00000800 */\n#define FMC_BCR4_WAITCFG            FMC_BCR4_WAITCFG_Msk                       /*!<Wait timing configuration  */\n#define FMC_BCR4_WREN_Pos           (12U)\n#define FMC_BCR4_WREN_Msk           (0x1UL << FMC_BCR4_WREN_Pos)                /*!< 0x00001000 */\n#define FMC_BCR4_WREN               FMC_BCR4_WREN_Msk                          /*!<Write enable bit           */\n#define FMC_BCR4_WAITEN_Pos         (13U)\n#define FMC_BCR4_WAITEN_Msk         (0x1UL << FMC_BCR4_WAITEN_Pos)              /*!< 0x00002000 */\n#define FMC_BCR4_WAITEN             FMC_BCR4_WAITEN_Msk                        /*!<Wait enable bit            */\n#define FMC_BCR4_EXTMOD_Pos         (14U)\n#define FMC_BCR4_EXTMOD_Msk         (0x1UL << FMC_BCR4_EXTMOD_Pos)              /*!< 0x00004000 */\n#define FMC_BCR4_EXTMOD             FMC_BCR4_EXTMOD_Msk                        /*!<Extended mode enable       */\n#define FMC_BCR4_ASYNCWAIT_Pos      (15U)\n#define FMC_BCR4_ASYNCWAIT_Msk      (0x1UL << FMC_BCR4_ASYNCWAIT_Pos)           /*!< 0x00008000 */\n#define FMC_BCR4_ASYNCWAIT          FMC_BCR4_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */\n#define FMC_BCR4_CBURSTRW_Pos       (19U)\n#define FMC_BCR4_CBURSTRW_Msk       (0x1UL << FMC_BCR4_CBURSTRW_Pos)            /*!< 0x00080000 */\n#define FMC_BCR4_CBURSTRW           FMC_BCR4_CBURSTRW_Msk                      /*!<Write burst enable         */\n\n/******************  Bit definition for FMC_BTR1 register  ******************/\n#define FMC_BTR1_ADDSET_Pos         (0U)\n#define FMC_BTR1_ADDSET_Msk         (0xFUL << FMC_BTR1_ADDSET_Pos)              /*!< 0x0000000F */\n#define FMC_BTR1_ADDSET             FMC_BTR1_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BTR1_ADDSET_0           (0x1UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000001 */\n#define FMC_BTR1_ADDSET_1           (0x2UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000002 */\n#define FMC_BTR1_ADDSET_2           (0x4UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000004 */\n#define FMC_BTR1_ADDSET_3           (0x8UL << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000008 */\n\n#define FMC_BTR1_ADDHLD_Pos         (4U)\n#define FMC_BTR1_ADDHLD_Msk         (0xFUL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x000000F0 */\n#define FMC_BTR1_ADDHLD             FMC_BTR1_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */\n#define FMC_BTR1_ADDHLD_0           (0x1UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000010 */\n#define FMC_BTR1_ADDHLD_1           (0x2UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000020 */\n#define FMC_BTR1_ADDHLD_2           (0x4UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000040 */\n#define FMC_BTR1_ADDHLD_3           (0x8UL << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000080 */\n\n#define FMC_BTR1_DATAST_Pos         (8U)\n#define FMC_BTR1_DATAST_Msk         (0xFFUL << FMC_BTR1_DATAST_Pos)             /*!< 0x0000FF00 */\n#define FMC_BTR1_DATAST             FMC_BTR1_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BTR1_DATAST_0           (0x01UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000100 */\n#define FMC_BTR1_DATAST_1           (0x02UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000200 */\n#define FMC_BTR1_DATAST_2           (0x04UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000400 */\n#define FMC_BTR1_DATAST_3           (0x08UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00000800 */\n#define FMC_BTR1_DATAST_4           (0x10UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00001000 */\n#define FMC_BTR1_DATAST_5           (0x20UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00002000 */\n#define FMC_BTR1_DATAST_6           (0x40UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00004000 */\n#define FMC_BTR1_DATAST_7           (0x80UL << FMC_BTR1_DATAST_Pos)             /*!< 0x00008000 */\n\n#define FMC_BTR1_BUSTURN_Pos        (16U)\n#define FMC_BTR1_BUSTURN_Msk        (0xFUL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x000F0000 */\n#define FMC_BTR1_BUSTURN            FMC_BTR1_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FMC_BTR1_BUSTURN_0          (0x1UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00010000 */\n#define FMC_BTR1_BUSTURN_1          (0x2UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00020000 */\n#define FMC_BTR1_BUSTURN_2          (0x4UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00040000 */\n#define FMC_BTR1_BUSTURN_3          (0x8UL << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00080000 */\n\n#define FMC_BTR1_CLKDIV_Pos         (20U)\n#define FMC_BTR1_CLKDIV_Msk         (0xFUL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00F00000 */\n#define FMC_BTR1_CLKDIV             FMC_BTR1_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FMC_BTR1_CLKDIV_0           (0x1UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00100000 */\n#define FMC_BTR1_CLKDIV_1           (0x2UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00200000 */\n#define FMC_BTR1_CLKDIV_2           (0x4UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00400000 */\n#define FMC_BTR1_CLKDIV_3           (0x8UL << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00800000 */\n\n#define FMC_BTR1_DATLAT_Pos         (24U)\n#define FMC_BTR1_DATLAT_Msk         (0xFUL << FMC_BTR1_DATLAT_Pos)              /*!< 0x0F000000 */\n#define FMC_BTR1_DATLAT             FMC_BTR1_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */\n#define FMC_BTR1_DATLAT_0           (0x1UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x01000000 */\n#define FMC_BTR1_DATLAT_1           (0x2UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x02000000 */\n#define FMC_BTR1_DATLAT_2           (0x4UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x04000000 */\n#define FMC_BTR1_DATLAT_3           (0x8UL << FMC_BTR1_DATLAT_Pos)              /*!< 0x08000000 */\n\n#define FMC_BTR1_ACCMOD_Pos         (28U)\n#define FMC_BTR1_ACCMOD_Msk         (0x3UL << FMC_BTR1_ACCMOD_Pos)              /*!< 0x30000000 */\n#define FMC_BTR1_ACCMOD             FMC_BTR1_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BTR1_ACCMOD_0           (0x1UL << FMC_BTR1_ACCMOD_Pos)              /*!< 0x10000000 */\n#define FMC_BTR1_ACCMOD_1           (0x2UL << FMC_BTR1_ACCMOD_Pos)              /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_BTR2 register  *******************/\n#define FMC_BTR2_ADDSET_Pos         (0U)\n#define FMC_BTR2_ADDSET_Msk         (0xFUL << FMC_BTR2_ADDSET_Pos)              /*!< 0x0000000F */\n#define FMC_BTR2_ADDSET             FMC_BTR2_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BTR2_ADDSET_0           (0x1UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000001 */\n#define FMC_BTR2_ADDSET_1           (0x2UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000002 */\n#define FMC_BTR2_ADDSET_2           (0x4UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000004 */\n#define FMC_BTR2_ADDSET_3           (0x8UL << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000008 */\n\n#define FMC_BTR2_ADDHLD_Pos         (4U)\n#define FMC_BTR2_ADDHLD_Msk         (0xFUL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x000000F0 */\n#define FMC_BTR2_ADDHLD             FMC_BTR2_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BTR2_ADDHLD_0           (0x1UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000010 */\n#define FMC_BTR2_ADDHLD_1           (0x2UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000020 */\n#define FMC_BTR2_ADDHLD_2           (0x4UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000040 */\n#define FMC_BTR2_ADDHLD_3           (0x8UL << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000080 */\n\n#define FMC_BTR2_DATAST_Pos         (8U)\n#define FMC_BTR2_DATAST_Msk         (0xFFUL << FMC_BTR2_DATAST_Pos)             /*!< 0x0000FF00 */\n#define FMC_BTR2_DATAST             FMC_BTR2_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BTR2_DATAST_0           (0x01UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000100 */\n#define FMC_BTR2_DATAST_1           (0x02UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000200 */\n#define FMC_BTR2_DATAST_2           (0x04UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000400 */\n#define FMC_BTR2_DATAST_3           (0x08UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00000800 */\n#define FMC_BTR2_DATAST_4           (0x10UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00001000 */\n#define FMC_BTR2_DATAST_5           (0x20UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00002000 */\n#define FMC_BTR2_DATAST_6           (0x40UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00004000 */\n#define FMC_BTR2_DATAST_7           (0x80UL << FMC_BTR2_DATAST_Pos)             /*!< 0x00008000 */\n\n#define FMC_BTR2_BUSTURN_Pos        (16U)\n#define FMC_BTR2_BUSTURN_Msk        (0xFUL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x000F0000 */\n#define FMC_BTR2_BUSTURN            FMC_BTR2_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FMC_BTR2_BUSTURN_0          (0x1UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00010000 */\n#define FMC_BTR2_BUSTURN_1          (0x2UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00020000 */\n#define FMC_BTR2_BUSTURN_2          (0x4UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00040000 */\n#define FMC_BTR2_BUSTURN_3          (0x8UL << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00080000 */\n\n#define FMC_BTR2_CLKDIV_Pos         (20U)\n#define FMC_BTR2_CLKDIV_Msk         (0xFUL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00F00000 */\n#define FMC_BTR2_CLKDIV             FMC_BTR2_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FMC_BTR2_CLKDIV_0           (0x1UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00100000 */\n#define FMC_BTR2_CLKDIV_1           (0x2UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00200000 */\n#define FMC_BTR2_CLKDIV_2           (0x4UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00400000 */\n#define FMC_BTR2_CLKDIV_3           (0x8UL << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00800000 */\n\n#define FMC_BTR2_DATLAT_Pos         (24U)\n#define FMC_BTR2_DATLAT_Msk         (0xFUL << FMC_BTR2_DATLAT_Pos)              /*!< 0x0F000000 */\n#define FMC_BTR2_DATLAT             FMC_BTR2_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */\n#define FMC_BTR2_DATLAT_0           (0x1UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x01000000 */\n#define FMC_BTR2_DATLAT_1           (0x2UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x02000000 */\n#define FMC_BTR2_DATLAT_2           (0x4UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x04000000 */\n#define FMC_BTR2_DATLAT_3           (0x8UL << FMC_BTR2_DATLAT_Pos)              /*!< 0x08000000 */\n\n#define FMC_BTR2_ACCMOD_Pos         (28U)\n#define FMC_BTR2_ACCMOD_Msk         (0x3UL << FMC_BTR2_ACCMOD_Pos)              /*!< 0x30000000 */\n#define FMC_BTR2_ACCMOD             FMC_BTR2_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BTR2_ACCMOD_0           (0x1UL << FMC_BTR2_ACCMOD_Pos)              /*!< 0x10000000 */\n#define FMC_BTR2_ACCMOD_1           (0x2UL << FMC_BTR2_ACCMOD_Pos)              /*!< 0x20000000 */\n\n/*******************  Bit definition for FMC_BTR3 register  *******************/\n#define FMC_BTR3_ADDSET_Pos         (0U)\n#define FMC_BTR3_ADDSET_Msk         (0xFUL << FMC_BTR3_ADDSET_Pos)              /*!< 0x0000000F */\n#define FMC_BTR3_ADDSET             FMC_BTR3_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BTR3_ADDSET_0           (0x1UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000001 */\n#define FMC_BTR3_ADDSET_1           (0x2UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000002 */\n#define FMC_BTR3_ADDSET_2           (0x4UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000004 */\n#define FMC_BTR3_ADDSET_3           (0x8UL << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000008 */\n\n#define FMC_BTR3_ADDHLD_Pos         (4U)\n#define FMC_BTR3_ADDHLD_Msk         (0xFUL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x000000F0 */\n#define FMC_BTR3_ADDHLD             FMC_BTR3_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BTR3_ADDHLD_0           (0x1UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000010 */\n#define FMC_BTR3_ADDHLD_1           (0x2UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000020 */\n#define FMC_BTR3_ADDHLD_2           (0x4UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000040 */\n#define FMC_BTR3_ADDHLD_3           (0x8UL << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000080 */\n\n#define FMC_BTR3_DATAST_Pos         (8U)\n#define FMC_BTR3_DATAST_Msk         (0xFFUL << FMC_BTR3_DATAST_Pos)             /*!< 0x0000FF00 */\n#define FMC_BTR3_DATAST             FMC_BTR3_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BTR3_DATAST_0           (0x01UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000100 */\n#define FMC_BTR3_DATAST_1           (0x02UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000200 */\n#define FMC_BTR3_DATAST_2           (0x04UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000400 */\n#define FMC_BTR3_DATAST_3           (0x08UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00000800 */\n#define FMC_BTR3_DATAST_4           (0x10UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00001000 */\n#define FMC_BTR3_DATAST_5           (0x20UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00002000 */\n#define FMC_BTR3_DATAST_6           (0x40UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00004000 */\n#define FMC_BTR3_DATAST_7           (0x80UL << FMC_BTR3_DATAST_Pos)             /*!< 0x00008000 */\n\n#define FMC_BTR3_BUSTURN_Pos        (16U)\n#define FMC_BTR3_BUSTURN_Msk        (0xFUL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x000F0000 */\n#define FMC_BTR3_BUSTURN            FMC_BTR3_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FMC_BTR3_BUSTURN_0          (0x1UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00010000 */\n#define FMC_BTR3_BUSTURN_1          (0x2UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00020000 */\n#define FMC_BTR3_BUSTURN_2          (0x4UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00040000 */\n#define FMC_BTR3_BUSTURN_3          (0x8UL << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00080000 */\n\n#define FMC_BTR3_CLKDIV_Pos         (20U)\n#define FMC_BTR3_CLKDIV_Msk         (0xFUL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00F00000 */\n#define FMC_BTR3_CLKDIV             FMC_BTR3_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FMC_BTR3_CLKDIV_0           (0x1UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00100000 */\n#define FMC_BTR3_CLKDIV_1           (0x2UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00200000 */\n#define FMC_BTR3_CLKDIV_2           (0x4UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00400000 */\n#define FMC_BTR3_CLKDIV_3           (0x8UL << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00800000 */\n\n#define FMC_BTR3_DATLAT_Pos         (24U)\n#define FMC_BTR3_DATLAT_Msk         (0xFUL << FMC_BTR3_DATLAT_Pos)              /*!< 0x0F000000 */\n#define FMC_BTR3_DATLAT             FMC_BTR3_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */\n#define FMC_BTR3_DATLAT_0           (0x1UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x01000000 */\n#define FMC_BTR3_DATLAT_1           (0x2UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x02000000 */\n#define FMC_BTR3_DATLAT_2           (0x4UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x04000000 */\n#define FMC_BTR3_DATLAT_3           (0x8UL << FMC_BTR3_DATLAT_Pos)              /*!< 0x08000000 */\n\n#define FMC_BTR3_ACCMOD_Pos         (28U)\n#define FMC_BTR3_ACCMOD_Msk         (0x3UL << FMC_BTR3_ACCMOD_Pos)              /*!< 0x30000000 */\n#define FMC_BTR3_ACCMOD             FMC_BTR3_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BTR3_ACCMOD_0           (0x1UL << FMC_BTR3_ACCMOD_Pos)              /*!< 0x10000000 */\n#define FMC_BTR3_ACCMOD_1           (0x2UL << FMC_BTR3_ACCMOD_Pos)              /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_BTR4 register  *******************/\n#define FMC_BTR4_ADDSET_Pos         (0U)\n#define FMC_BTR4_ADDSET_Msk         (0xFUL << FMC_BTR4_ADDSET_Pos)              /*!< 0x0000000F */\n#define FMC_BTR4_ADDSET             FMC_BTR4_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BTR4_ADDSET_0           (0x1UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000001 */\n#define FMC_BTR4_ADDSET_1           (0x2UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000002 */\n#define FMC_BTR4_ADDSET_2           (0x4UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000004 */\n#define FMC_BTR4_ADDSET_3           (0x8UL << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000008 */\n\n#define FMC_BTR4_ADDHLD_Pos         (4U)\n#define FMC_BTR4_ADDHLD_Msk         (0xFUL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x000000F0 */\n#define FMC_BTR4_ADDHLD             FMC_BTR4_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BTR4_ADDHLD_0           (0x1UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000010 */\n#define FMC_BTR4_ADDHLD_1           (0x2UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000020 */\n#define FMC_BTR4_ADDHLD_2           (0x4UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000040 */\n#define FMC_BTR4_ADDHLD_3           (0x8UL << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000080 */\n\n#define FMC_BTR4_DATAST_Pos         (8U)\n#define FMC_BTR4_DATAST_Msk         (0xFFUL << FMC_BTR4_DATAST_Pos)             /*!< 0x0000FF00 */\n#define FMC_BTR4_DATAST             FMC_BTR4_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BTR4_DATAST_0           (0x01UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000100 */\n#define FMC_BTR4_DATAST_1           (0x02UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000200 */\n#define FMC_BTR4_DATAST_2           (0x04UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000400 */\n#define FMC_BTR4_DATAST_3           (0x08UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00000800 */\n#define FMC_BTR4_DATAST_4           (0x10UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00001000 */\n#define FMC_BTR4_DATAST_5           (0x20UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00002000 */\n#define FMC_BTR4_DATAST_6           (0x40UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00004000 */\n#define FMC_BTR4_DATAST_7           (0x80UL << FMC_BTR4_DATAST_Pos)             /*!< 0x00008000 */\n\n#define FMC_BTR4_BUSTURN_Pos        (16U)\n#define FMC_BTR4_BUSTURN_Msk        (0xFUL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x000F0000 */\n#define FMC_BTR4_BUSTURN            FMC_BTR4_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FMC_BTR4_BUSTURN_0          (0x1UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00010000 */\n#define FMC_BTR4_BUSTURN_1          (0x2UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00020000 */\n#define FMC_BTR4_BUSTURN_2          (0x4UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00040000 */\n#define FMC_BTR4_BUSTURN_3          (0x8UL << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00080000 */\n\n#define FMC_BTR4_CLKDIV_Pos         (20U)\n#define FMC_BTR4_CLKDIV_Msk         (0xFUL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00F00000 */\n#define FMC_BTR4_CLKDIV             FMC_BTR4_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FMC_BTR4_CLKDIV_0           (0x1UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00100000 */\n#define FMC_BTR4_CLKDIV_1           (0x2UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00200000 */\n#define FMC_BTR4_CLKDIV_2           (0x4UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00400000 */\n#define FMC_BTR4_CLKDIV_3           (0x8UL << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00800000 */\n\n#define FMC_BTR4_DATLAT_Pos         (24U)\n#define FMC_BTR4_DATLAT_Msk         (0xFUL << FMC_BTR4_DATLAT_Pos)              /*!< 0x0F000000 */\n#define FMC_BTR4_DATLAT             FMC_BTR4_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */\n#define FMC_BTR4_DATLAT_0           (0x1UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x01000000 */\n#define FMC_BTR4_DATLAT_1           (0x2UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x02000000 */\n#define FMC_BTR4_DATLAT_2           (0x4UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x04000000 */\n#define FMC_BTR4_DATLAT_3           (0x8UL << FMC_BTR4_DATLAT_Pos)              /*!< 0x08000000 */\n\n#define FMC_BTR4_ACCMOD_Pos         (28U)\n#define FMC_BTR4_ACCMOD_Msk         (0x3UL << FMC_BTR4_ACCMOD_Pos)              /*!< 0x30000000 */\n#define FMC_BTR4_ACCMOD             FMC_BTR4_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BTR4_ACCMOD_0           (0x1UL << FMC_BTR4_ACCMOD_Pos)              /*!< 0x10000000 */\n#define FMC_BTR4_ACCMOD_1           (0x2UL << FMC_BTR4_ACCMOD_Pos)              /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_BWTR1 register  ******************/\n#define FMC_BWTR1_ADDSET_Pos        (0U)\n#define FMC_BWTR1_ADDSET_Msk        (0xFUL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x0000000F */\n#define FMC_BWTR1_ADDSET            FMC_BWTR1_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BWTR1_ADDSET_0          (0x1UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000001 */\n#define FMC_BWTR1_ADDSET_1          (0x2UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000002 */\n#define FMC_BWTR1_ADDSET_2          (0x4UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000004 */\n#define FMC_BWTR1_ADDSET_3          (0x8UL << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000008 */\n\n#define FMC_BWTR1_ADDHLD_Pos        (4U)\n#define FMC_BWTR1_ADDHLD_Msk        (0xFUL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x000000F0 */\n#define FMC_BWTR1_ADDHLD            FMC_BWTR1_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BWTR1_ADDHLD_0          (0x1UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000010 */\n#define FMC_BWTR1_ADDHLD_1          (0x2UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000020 */\n#define FMC_BWTR1_ADDHLD_2          (0x4UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000040 */\n#define FMC_BWTR1_ADDHLD_3          (0x8UL << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000080 */\n\n#define FMC_BWTR1_DATAST_Pos        (8U)\n#define FMC_BWTR1_DATAST_Msk        (0xFFUL << FMC_BWTR1_DATAST_Pos)            /*!< 0x0000FF00 */\n#define FMC_BWTR1_DATAST            FMC_BWTR1_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BWTR1_DATAST_0          (0x01UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000100 */\n#define FMC_BWTR1_DATAST_1          (0x02UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000200 */\n#define FMC_BWTR1_DATAST_2          (0x04UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000400 */\n#define FMC_BWTR1_DATAST_3          (0x08UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000800 */\n#define FMC_BWTR1_DATAST_4          (0x10UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00001000 */\n#define FMC_BWTR1_DATAST_5          (0x20UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00002000 */\n#define FMC_BWTR1_DATAST_6          (0x40UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00004000 */\n#define FMC_BWTR1_DATAST_7          (0x80UL << FMC_BWTR1_DATAST_Pos)            /*!< 0x00008000 */\n\n#define FMC_BWTR1_BUSTURN_Pos       (16U)\n#define FMC_BWTR1_BUSTURN_Msk       (0xFUL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x000F0000 */\n#define FMC_BWTR1_BUSTURN           FMC_BWTR1_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FMC_BWTR1_BUSTURN_0         (0x1UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00010000 */\n#define FMC_BWTR1_BUSTURN_1         (0x2UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00020000 */\n#define FMC_BWTR1_BUSTURN_2         (0x4UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00040000 */\n#define FMC_BWTR1_BUSTURN_3         (0x8UL << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00080000 */\n\n#define FMC_BWTR1_ACCMOD_Pos        (28U)\n#define FMC_BWTR1_ACCMOD_Msk        (0x3UL << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x30000000 */\n#define FMC_BWTR1_ACCMOD            FMC_BWTR1_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BWTR1_ACCMOD_0          (0x1UL << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x10000000 */\n#define FMC_BWTR1_ACCMOD_1          (0x2UL << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_BWTR2 register  ******************/\n#define FMC_BWTR2_ADDSET_Pos        (0U)\n#define FMC_BWTR2_ADDSET_Msk        (0xFUL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x0000000F */\n#define FMC_BWTR2_ADDSET            FMC_BWTR2_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BWTR2_ADDSET_0          (0x1UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000001 */\n#define FMC_BWTR2_ADDSET_1          (0x2UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000002 */\n#define FMC_BWTR2_ADDSET_2          (0x4UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000004 */\n#define FMC_BWTR2_ADDSET_3          (0x8UL << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000008 */\n\n#define FMC_BWTR2_ADDHLD_Pos        (4U)\n#define FMC_BWTR2_ADDHLD_Msk        (0xFUL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x000000F0 */\n#define FMC_BWTR2_ADDHLD            FMC_BWTR2_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BWTR2_ADDHLD_0          (0x1UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000010 */\n#define FMC_BWTR2_ADDHLD_1          (0x2UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000020 */\n#define FMC_BWTR2_ADDHLD_2          (0x4UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000040 */\n#define FMC_BWTR2_ADDHLD_3          (0x8UL << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000080 */\n\n#define FMC_BWTR2_DATAST_Pos        (8U)\n#define FMC_BWTR2_DATAST_Msk        (0xFFUL << FMC_BWTR2_DATAST_Pos)            /*!< 0x0000FF00 */\n#define FMC_BWTR2_DATAST            FMC_BWTR2_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BWTR2_DATAST_0          (0x01UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000100 */\n#define FMC_BWTR2_DATAST_1          (0x02UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000200 */\n#define FMC_BWTR2_DATAST_2          (0x04UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000400 */\n#define FMC_BWTR2_DATAST_3          (0x08UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000800 */\n#define FMC_BWTR2_DATAST_4          (0x10UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00001000 */\n#define FMC_BWTR2_DATAST_5          (0x20UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00002000 */\n#define FMC_BWTR2_DATAST_6          (0x40UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00004000 */\n#define FMC_BWTR2_DATAST_7          (0x80UL << FMC_BWTR2_DATAST_Pos)            /*!< 0x00008000 */\n\n#define FMC_BWTR2_BUSTURN_Pos       (16U)\n#define FMC_BWTR2_BUSTURN_Msk       (0xFUL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x000F0000 */\n#define FMC_BWTR2_BUSTURN           FMC_BWTR2_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FMC_BWTR2_BUSTURN_0         (0x1UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00010000 */\n#define FMC_BWTR2_BUSTURN_1         (0x2UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00020000 */\n#define FMC_BWTR2_BUSTURN_2         (0x4UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00040000 */\n#define FMC_BWTR2_BUSTURN_3         (0x8UL << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00080000 */\n\n#define FMC_BWTR2_ACCMOD_Pos        (28U)\n#define FMC_BWTR2_ACCMOD_Msk        (0x3UL << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x30000000 */\n#define FMC_BWTR2_ACCMOD            FMC_BWTR2_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BWTR2_ACCMOD_0          (0x1UL << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x10000000 */\n#define FMC_BWTR2_ACCMOD_1          (0x2UL << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_BWTR3 register  ******************/\n#define FMC_BWTR3_ADDSET_Pos        (0U)\n#define FMC_BWTR3_ADDSET_Msk        (0xFUL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x0000000F */\n#define FMC_BWTR3_ADDSET            FMC_BWTR3_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BWTR3_ADDSET_0          (0x1UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000001 */\n#define FMC_BWTR3_ADDSET_1          (0x2UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000002 */\n#define FMC_BWTR3_ADDSET_2          (0x4UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000004 */\n#define FMC_BWTR3_ADDSET_3          (0x8UL << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000008 */\n\n#define FMC_BWTR3_ADDHLD_Pos        (4U)\n#define FMC_BWTR3_ADDHLD_Msk        (0xFUL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x000000F0 */\n#define FMC_BWTR3_ADDHLD            FMC_BWTR3_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BWTR3_ADDHLD_0          (0x1UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000010 */\n#define FMC_BWTR3_ADDHLD_1          (0x2UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000020 */\n#define FMC_BWTR3_ADDHLD_2          (0x4UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000040 */\n#define FMC_BWTR3_ADDHLD_3          (0x8UL << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000080 */\n\n#define FMC_BWTR3_DATAST_Pos        (8U)\n#define FMC_BWTR3_DATAST_Msk        (0xFFUL << FMC_BWTR3_DATAST_Pos)            /*!< 0x0000FF00 */\n#define FMC_BWTR3_DATAST            FMC_BWTR3_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BWTR3_DATAST_0          (0x01UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000100 */\n#define FMC_BWTR3_DATAST_1          (0x02UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000200 */\n#define FMC_BWTR3_DATAST_2          (0x04UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000400 */\n#define FMC_BWTR3_DATAST_3          (0x08UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000800 */\n#define FMC_BWTR3_DATAST_4          (0x10UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00001000 */\n#define FMC_BWTR3_DATAST_5          (0x20UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00002000 */\n#define FMC_BWTR3_DATAST_6          (0x40UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00004000 */\n#define FMC_BWTR3_DATAST_7          (0x80UL << FMC_BWTR3_DATAST_Pos)            /*!< 0x00008000 */\n\n#define FMC_BWTR3_BUSTURN_Pos       (16U)\n#define FMC_BWTR3_BUSTURN_Msk       (0xFUL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x000F0000 */\n#define FMC_BWTR3_BUSTURN           FMC_BWTR3_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FMC_BWTR3_BUSTURN_0         (0x1UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00010000 */\n#define FMC_BWTR3_BUSTURN_1         (0x2UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00020000 */\n#define FMC_BWTR3_BUSTURN_2         (0x4UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00040000 */\n#define FMC_BWTR3_BUSTURN_3         (0x8UL << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00080000 */\n\n#define FMC_BWTR3_ACCMOD_Pos        (28U)\n#define FMC_BWTR3_ACCMOD_Msk        (0x3UL << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x30000000 */\n#define FMC_BWTR3_ACCMOD            FMC_BWTR3_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BWTR3_ACCMOD_0          (0x1UL << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x10000000 */\n#define FMC_BWTR3_ACCMOD_1          (0x2UL << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_BWTR4 register  ******************/\n#define FMC_BWTR4_ADDSET_Pos        (0U)\n#define FMC_BWTR4_ADDSET_Msk        (0xFUL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x0000000F */\n#define FMC_BWTR4_ADDSET            FMC_BWTR4_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BWTR4_ADDSET_0          (0x1UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000001 */\n#define FMC_BWTR4_ADDSET_1          (0x2UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000002 */\n#define FMC_BWTR4_ADDSET_2          (0x4UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000004 */\n#define FMC_BWTR4_ADDSET_3          (0x8UL << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000008 */\n\n#define FMC_BWTR4_ADDHLD_Pos        (4U)\n#define FMC_BWTR4_ADDHLD_Msk        (0xFUL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x000000F0 */\n#define FMC_BWTR4_ADDHLD            FMC_BWTR4_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BWTR4_ADDHLD_0          (0x1UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000010 */\n#define FMC_BWTR4_ADDHLD_1          (0x2UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000020 */\n#define FMC_BWTR4_ADDHLD_2          (0x4UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000040 */\n#define FMC_BWTR4_ADDHLD_3          (0x8UL << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000080 */\n\n#define FMC_BWTR4_DATAST_Pos        (8U)\n#define FMC_BWTR4_DATAST_Msk        (0xFFUL << FMC_BWTR4_DATAST_Pos)            /*!< 0x0000FF00 */\n#define FMC_BWTR4_DATAST            FMC_BWTR4_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BWTR4_DATAST_0          (0x01UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000100 */\n#define FMC_BWTR4_DATAST_1          (0x02UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000200 */\n#define FMC_BWTR4_DATAST_2          (0x04UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000400 */\n#define FMC_BWTR4_DATAST_3          (0x08UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000800 */\n#define FMC_BWTR4_DATAST_4          (0x10UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00001000 */\n#define FMC_BWTR4_DATAST_5          (0x20UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00002000 */\n#define FMC_BWTR4_DATAST_6          (0x40UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00004000 */\n#define FMC_BWTR4_DATAST_7          (0x80UL << FMC_BWTR4_DATAST_Pos)            /*!< 0x00008000 */\n\n#define FMC_BWTR4_BUSTURN_Pos       (16U)\n#define FMC_BWTR4_BUSTURN_Msk       (0xFUL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x000F0000 */\n#define FMC_BWTR4_BUSTURN           FMC_BWTR4_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FMC_BWTR4_BUSTURN_0         (0x1UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00010000 */\n#define FMC_BWTR4_BUSTURN_1         (0x2UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00020000 */\n#define FMC_BWTR4_BUSTURN_2         (0x4UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00040000 */\n#define FMC_BWTR4_BUSTURN_3         (0x8UL << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00080000 */\n\n#define FMC_BWTR4_ACCMOD_Pos        (28U)\n#define FMC_BWTR4_ACCMOD_Msk        (0x3UL << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x30000000 */\n#define FMC_BWTR4_ACCMOD            FMC_BWTR4_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BWTR4_ACCMOD_0          (0x1UL << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x10000000 */\n#define FMC_BWTR4_ACCMOD_1          (0x2UL << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_PCR register  *******************/\n#define FMC_PCR_PWAITEN_Pos         (1U)\n#define FMC_PCR_PWAITEN_Msk         (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */\n#define FMC_PCR_PWAITEN             FMC_PCR_PWAITEN_Msk                        /*!<Wait feature enable bit                   */\n#define FMC_PCR_PBKEN_Pos           (2U)\n#define FMC_PCR_PBKEN_Msk           (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */\n#define FMC_PCR_PBKEN               FMC_PCR_PBKEN_Msk                          /*!<PC Card/NAND Flash memory bank enable bit */\n#define FMC_PCR_PTYP_Pos            (3U)\n#define FMC_PCR_PTYP_Msk            (0x1UL << FMC_PCR_PTYP_Pos)                 /*!< 0x00000008 */\n#define FMC_PCR_PTYP                FMC_PCR_PTYP_Msk                           /*!<Memory type                               */\n\n#define FMC_PCR_PWID_Pos            (4U)\n#define FMC_PCR_PWID_Msk            (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */\n#define FMC_PCR_PWID                FMC_PCR_PWID_Msk                           /*!<PWID[1:0] bits (NAND Flash databus width) */\n#define FMC_PCR_PWID_0              (0x1UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000010 */\n#define FMC_PCR_PWID_1              (0x2UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000020 */\n\n#define FMC_PCR_ECCEN_Pos           (6U)\n#define FMC_PCR_ECCEN_Msk           (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */\n#define FMC_PCR_ECCEN               FMC_PCR_ECCEN_Msk                          /*!<ECC computation logic enable bit          */\n\n#define FMC_PCR_TCLR_Pos            (9U)\n#define FMC_PCR_TCLR_Msk            (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */\n#define FMC_PCR_TCLR                FMC_PCR_TCLR_Msk                           /*!<TCLR[3:0] bits (CLE to RE delay)          */\n#define FMC_PCR_TCLR_0              (0x1UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000200 */\n#define FMC_PCR_TCLR_1              (0x2UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000400 */\n#define FMC_PCR_TCLR_2              (0x4UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00000800 */\n#define FMC_PCR_TCLR_3              (0x8UL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001000 */\n\n#define FMC_PCR_TAR_Pos             (13U)\n#define FMC_PCR_TAR_Msk             (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */\n#define FMC_PCR_TAR                 FMC_PCR_TAR_Msk                            /*!<TAR[3:0] bits (ALE to RE delay)           */\n#define FMC_PCR_TAR_0               (0x1UL << FMC_PCR_TAR_Pos)                  /*!< 0x00002000 */\n#define FMC_PCR_TAR_1               (0x2UL << FMC_PCR_TAR_Pos)                  /*!< 0x00004000 */\n#define FMC_PCR_TAR_2               (0x4UL << FMC_PCR_TAR_Pos)                  /*!< 0x00008000 */\n#define FMC_PCR_TAR_3               (0x8UL << FMC_PCR_TAR_Pos)                  /*!< 0x00010000 */\n\n#define FMC_PCR_ECCPS_Pos           (17U)\n#define FMC_PCR_ECCPS_Msk           (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */\n#define FMC_PCR_ECCPS               FMC_PCR_ECCPS_Msk                          /*!<ECCPS[1:0] bits (ECC page size)           */\n#define FMC_PCR_ECCPS_0             (0x1UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00020000 */\n#define FMC_PCR_ECCPS_1             (0x2UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00040000 */\n#define FMC_PCR_ECCPS_2             (0x4UL << FMC_PCR_ECCPS_Pos)                /*!< 0x00080000 */\n\n/*******************  Bit definition for FMC_SR register  *******************/\n#define FMC_SR_IRS_Pos              (0U)\n#define FMC_SR_IRS_Msk              (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */\n#define FMC_SR_IRS                  FMC_SR_IRS_Msk                             /*!<Interrupt Rising Edge status                */\n#define FMC_SR_ILS_Pos              (1U)\n#define FMC_SR_ILS_Msk              (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */\n#define FMC_SR_ILS                  FMC_SR_ILS_Msk                             /*!<Interrupt Level status                      */\n#define FMC_SR_IFS_Pos              (2U)\n#define FMC_SR_IFS_Msk              (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */\n#define FMC_SR_IFS                  FMC_SR_IFS_Msk                             /*!<Interrupt Falling Edge status               */\n#define FMC_SR_IREN_Pos             (3U)\n#define FMC_SR_IREN_Msk             (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */\n#define FMC_SR_IREN                 FMC_SR_IREN_Msk                            /*!<Interrupt Rising Edge detection Enable bit  */\n#define FMC_SR_ILEN_Pos             (4U)\n#define FMC_SR_ILEN_Msk             (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */\n#define FMC_SR_ILEN                 FMC_SR_ILEN_Msk                            /*!<Interrupt Level detection Enable bit        */\n#define FMC_SR_IFEN_Pos             (5U)\n#define FMC_SR_IFEN_Msk             (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */\n#define FMC_SR_IFEN                 FMC_SR_IFEN_Msk                            /*!<Interrupt Falling Edge detection Enable bit */\n#define FMC_SR_FEMPT_Pos            (6U)\n#define FMC_SR_FEMPT_Msk            (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */\n#define FMC_SR_FEMPT                FMC_SR_FEMPT_Msk                           /*!<FIFO empty                                  */\n\n/******************  Bit definition for FMC_PMEM register  ******************/\n#define FMC_PMEM_MEMSET2_Pos        (0U)\n#define FMC_PMEM_MEMSET2_Msk        (0xFFUL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x000000FF */\n#define FMC_PMEM_MEMSET2            FMC_PMEM_MEMSET2_Msk                       /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */\n#define FMC_PMEM_MEMSET2_0          (0x01UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000001 */\n#define FMC_PMEM_MEMSET2_1          (0x02UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000002 */\n#define FMC_PMEM_MEMSET2_2          (0x04UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000004 */\n#define FMC_PMEM_MEMSET2_3          (0x08UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000008 */\n#define FMC_PMEM_MEMSET2_4          (0x10UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000010 */\n#define FMC_PMEM_MEMSET2_5          (0x20UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000020 */\n#define FMC_PMEM_MEMSET2_6          (0x40UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000040 */\n#define FMC_PMEM_MEMSET2_7          (0x80UL << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000080 */\n\n#define FMC_PMEM_MEMWAIT2_Pos       (8U)\n#define FMC_PMEM_MEMWAIT2_Msk       (0xFFUL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x0000FF00 */\n#define FMC_PMEM_MEMWAIT2           FMC_PMEM_MEMWAIT2_Msk                      /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */\n#define FMC_PMEM_MEMWAIT2_0         (0x01UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00000100 */\n#define FMC_PMEM_MEMWAIT2_1         (0x02UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00000200 */\n#define FMC_PMEM_MEMWAIT2_2         (0x04UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00000400 */\n#define FMC_PMEM_MEMWAIT2_3         (0x08UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00000800 */\n#define FMC_PMEM_MEMWAIT2_4         (0x10UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00001000 */\n#define FMC_PMEM_MEMWAIT2_5         (0x20UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00002000 */\n#define FMC_PMEM_MEMWAIT2_6         (0x40UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00004000 */\n#define FMC_PMEM_MEMWAIT2_7         (0x80UL << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00008000 */\n\n#define FMC_PMEM_MEMHOLD2_Pos       (16U)\n#define FMC_PMEM_MEMHOLD2_Msk       (0xFFUL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00FF0000 */\n#define FMC_PMEM_MEMHOLD2           FMC_PMEM_MEMHOLD2_Msk                      /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */\n#define FMC_PMEM_MEMHOLD2_0         (0x01UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00010000 */\n#define FMC_PMEM_MEMHOLD2_1         (0x02UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00020000 */\n#define FMC_PMEM_MEMHOLD2_2         (0x04UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00040000 */\n#define FMC_PMEM_MEMHOLD2_3         (0x08UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00080000 */\n#define FMC_PMEM_MEMHOLD2_4         (0x10UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00100000 */\n#define FMC_PMEM_MEMHOLD2_5         (0x20UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00200000 */\n#define FMC_PMEM_MEMHOLD2_6         (0x40UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00400000 */\n#define FMC_PMEM_MEMHOLD2_7         (0x80UL << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00800000 */\n\n#define FMC_PMEM_MEMHIZ2_Pos        (24U)\n#define FMC_PMEM_MEMHIZ2_Msk        (0xFFUL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0xFF000000 */\n#define FMC_PMEM_MEMHIZ2            FMC_PMEM_MEMHIZ2_Msk                       /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */\n#define FMC_PMEM_MEMHIZ2_0          (0x01UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x01000000 */\n#define FMC_PMEM_MEMHIZ2_1          (0x02UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x02000000 */\n#define FMC_PMEM_MEMHIZ2_2          (0x04UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x04000000 */\n#define FMC_PMEM_MEMHIZ2_3          (0x08UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x08000000 */\n#define FMC_PMEM_MEMHIZ2_4          (0x10UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x10000000 */\n#define FMC_PMEM_MEMHIZ2_5          (0x20UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x20000000 */\n#define FMC_PMEM_MEMHIZ2_6          (0x40UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x40000000 */\n#define FMC_PMEM_MEMHIZ2_7          (0x80UL << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x80000000 */\n\n/******************  Bit definition for FMC_PATT register  ******************/\n#define FMC_PATT_ATTSET2_Pos        (0U)\n#define FMC_PATT_ATTSET2_Msk        (0xFFUL << FMC_PATT_ATTSET2_Pos)            /*!< 0x000000FF */\n#define FMC_PATT_ATTSET2            FMC_PATT_ATTSET2_Msk                       /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */\n#define FMC_PATT_ATTSET2_0          (0x01UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000001 */\n#define FMC_PATT_ATTSET2_1          (0x02UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000002 */\n#define FMC_PATT_ATTSET2_2          (0x04UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000004 */\n#define FMC_PATT_ATTSET2_3          (0x08UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000008 */\n#define FMC_PATT_ATTSET2_4          (0x10UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000010 */\n#define FMC_PATT_ATTSET2_5          (0x20UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000020 */\n#define FMC_PATT_ATTSET2_6          (0x40UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000040 */\n#define FMC_PATT_ATTSET2_7          (0x80UL << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000080 */\n\n#define FMC_PATT_ATTWAIT2_Pos       (8U)\n#define FMC_PATT_ATTWAIT2_Msk       (0xFFUL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x0000FF00 */\n#define FMC_PATT_ATTWAIT2           FMC_PATT_ATTWAIT2_Msk                      /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */\n#define FMC_PATT_ATTWAIT2_0         (0x01UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00000100 */\n#define FMC_PATT_ATTWAIT2_1         (0x02UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00000200 */\n#define FMC_PATT_ATTWAIT2_2         (0x04UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00000400 */\n#define FMC_PATT_ATTWAIT2_3         (0x08UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00000800 */\n#define FMC_PATT_ATTWAIT2_4         (0x10UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00001000 */\n#define FMC_PATT_ATTWAIT2_5         (0x20UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00002000 */\n#define FMC_PATT_ATTWAIT2_6         (0x40UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00004000 */\n#define FMC_PATT_ATTWAIT2_7         (0x80UL << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00008000 */\n\n#define FMC_PATT_ATTHOLD2_Pos       (16U)\n#define FMC_PATT_ATTHOLD2_Msk       (0xFFUL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00FF0000 */\n#define FMC_PATT_ATTHOLD2           FMC_PATT_ATTHOLD2_Msk                      /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */\n#define FMC_PATT_ATTHOLD2_0         (0x01UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00010000 */\n#define FMC_PATT_ATTHOLD2_1         (0x02UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00020000 */\n#define FMC_PATT_ATTHOLD2_2         (0x04UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00040000 */\n#define FMC_PATT_ATTHOLD2_3         (0x08UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00080000 */\n#define FMC_PATT_ATTHOLD2_4         (0x10UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00100000 */\n#define FMC_PATT_ATTHOLD2_5         (0x20UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00200000 */\n#define FMC_PATT_ATTHOLD2_6         (0x40UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00400000 */\n#define FMC_PATT_ATTHOLD2_7         (0x80UL << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00800000 */\n\n#define FMC_PATT_ATTHIZ2_Pos        (24U)\n#define FMC_PATT_ATTHIZ2_Msk        (0xFFUL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0xFF000000 */\n#define FMC_PATT_ATTHIZ2            FMC_PATT_ATTHIZ2_Msk                       /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */\n#define FMC_PATT_ATTHIZ2_0          (0x01UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x01000000 */\n#define FMC_PATT_ATTHIZ2_1          (0x02UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x02000000 */\n#define FMC_PATT_ATTHIZ2_2          (0x04UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x04000000 */\n#define FMC_PATT_ATTHIZ2_3          (0x08UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x08000000 */\n#define FMC_PATT_ATTHIZ2_4          (0x10UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x10000000 */\n#define FMC_PATT_ATTHIZ2_5          (0x20UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x20000000 */\n#define FMC_PATT_ATTHIZ2_6          (0x40UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x40000000 */\n#define FMC_PATT_ATTHIZ2_7          (0x80UL << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x80000000 */\n\n/******************  Bit definition for FMC_ECCR register  ******************/\n#define FMC_ECCR_ECC2_Pos           (0U)\n#define FMC_ECCR_ECC2_Msk           (0xFFFFFFFFUL << FMC_ECCR_ECC2_Pos)         /*!< 0xFFFFFFFF */\n#define FMC_ECCR_ECC2               FMC_ECCR_ECC2_Msk                          /*!<ECC result */\n\n/******************  Bit definition for FMC_SDCR1 register  ******************/\n#define FMC_SDCR1_NC_Pos            (0U)\n#define FMC_SDCR1_NC_Msk            (0x3UL << FMC_SDCR1_NC_Pos)                 /*!< 0x00000003 */\n#define FMC_SDCR1_NC                FMC_SDCR1_NC_Msk                           /*!<NC[1:0] bits (Number of column bits) */\n#define FMC_SDCR1_NC_0              (0x1UL << FMC_SDCR1_NC_Pos)                 /*!< 0x00000001 */\n#define FMC_SDCR1_NC_1              (0x2UL << FMC_SDCR1_NC_Pos)                 /*!< 0x00000002 */\n\n#define FMC_SDCR1_NR_Pos            (2U)\n#define FMC_SDCR1_NR_Msk            (0x3UL << FMC_SDCR1_NR_Pos)                 /*!< 0x0000000C */\n#define FMC_SDCR1_NR                FMC_SDCR1_NR_Msk                           /*!<NR[1:0] bits (Number of row bits) */\n#define FMC_SDCR1_NR_0              (0x1UL << FMC_SDCR1_NR_Pos)                 /*!< 0x00000004 */\n#define FMC_SDCR1_NR_1              (0x2UL << FMC_SDCR1_NR_Pos)                 /*!< 0x00000008 */\n\n#define FMC_SDCR1_MWID_Pos          (4U)\n#define FMC_SDCR1_MWID_Msk          (0x3UL << FMC_SDCR1_MWID_Pos)               /*!< 0x00000030 */\n#define FMC_SDCR1_MWID              FMC_SDCR1_MWID_Msk                         /*!<NR[1:0] bits (Number of row bits) */\n#define FMC_SDCR1_MWID_0            (0x1UL << FMC_SDCR1_MWID_Pos)               /*!< 0x00000010 */\n#define FMC_SDCR1_MWID_1            (0x2UL << FMC_SDCR1_MWID_Pos)               /*!< 0x00000020 */\n\n#define FMC_SDCR1_NB_Pos            (6U)\n#define FMC_SDCR1_NB_Msk            (0x1UL << FMC_SDCR1_NB_Pos)                 /*!< 0x00000040 */\n#define FMC_SDCR1_NB                FMC_SDCR1_NB_Msk                           /*!<Number of internal bank */\n\n#define FMC_SDCR1_CAS_Pos           (7U)\n#define FMC_SDCR1_CAS_Msk           (0x3UL << FMC_SDCR1_CAS_Pos)                /*!< 0x00000180 */\n#define FMC_SDCR1_CAS               FMC_SDCR1_CAS_Msk                          /*!<CAS[1:0] bits (CAS latency) */\n#define FMC_SDCR1_CAS_0             (0x1UL << FMC_SDCR1_CAS_Pos)                /*!< 0x00000080 */\n#define FMC_SDCR1_CAS_1             (0x2UL << FMC_SDCR1_CAS_Pos)                /*!< 0x00000100 */\n\n#define FMC_SDCR1_WP_Pos            (9U)\n#define FMC_SDCR1_WP_Msk            (0x1UL << FMC_SDCR1_WP_Pos)                 /*!< 0x00000200 */\n#define FMC_SDCR1_WP                FMC_SDCR1_WP_Msk                           /*!<Write protection */\n\n#define FMC_SDCR1_SDCLK_Pos         (10U)\n#define FMC_SDCR1_SDCLK_Msk         (0x3UL << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000C00 */\n#define FMC_SDCR1_SDCLK             FMC_SDCR1_SDCLK_Msk                        /*!<SDRAM clock configuration */\n#define FMC_SDCR1_SDCLK_0           (0x1UL << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000400 */\n#define FMC_SDCR1_SDCLK_1           (0x2UL << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000800 */\n\n#define FMC_SDCR1_RBURST_Pos        (12U)\n#define FMC_SDCR1_RBURST_Msk        (0x1UL << FMC_SDCR1_RBURST_Pos)             /*!< 0x00001000 */\n#define FMC_SDCR1_RBURST            FMC_SDCR1_RBURST_Msk                       /*!<Read burst */\n\n#define FMC_SDCR1_RPIPE_Pos         (13U)\n#define FMC_SDCR1_RPIPE_Msk         (0x3UL << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00006000 */\n#define FMC_SDCR1_RPIPE             FMC_SDCR1_RPIPE_Msk                        /*!<Write protection */\n#define FMC_SDCR1_RPIPE_0           (0x1UL << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00002000 */\n#define FMC_SDCR1_RPIPE_1           (0x2UL << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00004000 */\n\n/******************  Bit definition for FMC_SDCR2 register  ******************/\n#define FMC_SDCR2_NC_Pos            (0U)\n#define FMC_SDCR2_NC_Msk            (0x3UL << FMC_SDCR2_NC_Pos)                 /*!< 0x00000003 */\n#define FMC_SDCR2_NC                FMC_SDCR2_NC_Msk                           /*!<NC[1:0] bits (Number of column bits) */\n#define FMC_SDCR2_NC_0              (0x1UL << FMC_SDCR2_NC_Pos)                 /*!< 0x00000001 */\n#define FMC_SDCR2_NC_1              (0x2UL << FMC_SDCR2_NC_Pos)                 /*!< 0x00000002 */\n\n#define FMC_SDCR2_NR_Pos            (2U)\n#define FMC_SDCR2_NR_Msk            (0x3UL << FMC_SDCR2_NR_Pos)                 /*!< 0x0000000C */\n#define FMC_SDCR2_NR                FMC_SDCR2_NR_Msk                           /*!<NR[1:0] bits (Number of row bits) */\n#define FMC_SDCR2_NR_0              (0x1UL << FMC_SDCR2_NR_Pos)                 /*!< 0x00000004 */\n#define FMC_SDCR2_NR_1              (0x2UL << FMC_SDCR2_NR_Pos)                 /*!< 0x00000008 */\n\n#define FMC_SDCR2_MWID_Pos          (4U)\n#define FMC_SDCR2_MWID_Msk          (0x3UL << FMC_SDCR2_MWID_Pos)               /*!< 0x00000030 */\n#define FMC_SDCR2_MWID              FMC_SDCR2_MWID_Msk                         /*!<NR[1:0] bits (Number of row bits) */\n#define FMC_SDCR2_MWID_0            (0x1UL << FMC_SDCR2_MWID_Pos)               /*!< 0x00000010 */\n#define FMC_SDCR2_MWID_1            (0x2UL << FMC_SDCR2_MWID_Pos)               /*!< 0x00000020 */\n\n#define FMC_SDCR2_NB_Pos            (6U)\n#define FMC_SDCR2_NB_Msk            (0x1UL << FMC_SDCR2_NB_Pos)                 /*!< 0x00000040 */\n#define FMC_SDCR2_NB                FMC_SDCR2_NB_Msk                           /*!<Number of internal bank */\n\n#define FMC_SDCR2_CAS_Pos           (7U)\n#define FMC_SDCR2_CAS_Msk           (0x3UL << FMC_SDCR2_CAS_Pos)                /*!< 0x00000180 */\n#define FMC_SDCR2_CAS               FMC_SDCR2_CAS_Msk                          /*!<CAS[1:0] bits (CAS latency) */\n#define FMC_SDCR2_CAS_0             (0x1UL << FMC_SDCR2_CAS_Pos)                /*!< 0x00000080 */\n#define FMC_SDCR2_CAS_1             (0x2UL << FMC_SDCR2_CAS_Pos)                /*!< 0x00000100 */\n\n#define FMC_SDCR2_WP_Pos            (9U)\n#define FMC_SDCR2_WP_Msk            (0x1UL << FMC_SDCR2_WP_Pos)                 /*!< 0x00000200 */\n#define FMC_SDCR2_WP                FMC_SDCR2_WP_Msk                           /*!<Write protection */\n\n#define FMC_SDCR2_SDCLK_Pos         (10U)\n#define FMC_SDCR2_SDCLK_Msk         (0x3UL << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000C00 */\n#define FMC_SDCR2_SDCLK             FMC_SDCR2_SDCLK_Msk                        /*!<SDCLK[1:0] (SDRAM clock configuration) */\n#define FMC_SDCR2_SDCLK_0           (0x1UL << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000400 */\n#define FMC_SDCR2_SDCLK_1           (0x2UL << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000800 */\n\n#define FMC_SDCR2_RBURST_Pos        (12U)\n#define FMC_SDCR2_RBURST_Msk        (0x1UL << FMC_SDCR2_RBURST_Pos)             /*!< 0x00001000 */\n#define FMC_SDCR2_RBURST            FMC_SDCR2_RBURST_Msk                       /*!<Read burst */\n\n#define FMC_SDCR2_RPIPE_Pos         (13U)\n#define FMC_SDCR2_RPIPE_Msk         (0x3UL << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00006000 */\n#define FMC_SDCR2_RPIPE             FMC_SDCR2_RPIPE_Msk                        /*!<RPIPE[1:0](Read pipe) */\n#define FMC_SDCR2_RPIPE_0           (0x1UL << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00002000 */\n#define FMC_SDCR2_RPIPE_1           (0x2UL << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00004000 */\n\n/******************  Bit definition for FMC_SDTR1 register  ******************/\n#define FMC_SDTR1_TMRD_Pos          (0U)\n#define FMC_SDTR1_TMRD_Msk          (0xFUL << FMC_SDTR1_TMRD_Pos)               /*!< 0x0000000F */\n#define FMC_SDTR1_TMRD              FMC_SDTR1_TMRD_Msk                         /*!<TMRD[3:0] bits (Load mode register to active) */\n#define FMC_SDTR1_TMRD_0            (0x1UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000001 */\n#define FMC_SDTR1_TMRD_1            (0x2UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000002 */\n#define FMC_SDTR1_TMRD_2            (0x4UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000004 */\n#define FMC_SDTR1_TMRD_3            (0x8UL << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000008 */\n\n#define FMC_SDTR1_TXSR_Pos          (4U)\n#define FMC_SDTR1_TXSR_Msk          (0xFUL << FMC_SDTR1_TXSR_Pos)               /*!< 0x000000F0 */\n#define FMC_SDTR1_TXSR              FMC_SDTR1_TXSR_Msk                         /*!<TXSR[3:0] bits (Exit self refresh) */\n#define FMC_SDTR1_TXSR_0            (0x1UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000010 */\n#define FMC_SDTR1_TXSR_1            (0x2UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000020 */\n#define FMC_SDTR1_TXSR_2            (0x4UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000040 */\n#define FMC_SDTR1_TXSR_3            (0x8UL << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000080 */\n\n#define FMC_SDTR1_TRAS_Pos          (8U)\n#define FMC_SDTR1_TRAS_Msk          (0xFUL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000F00 */\n#define FMC_SDTR1_TRAS              FMC_SDTR1_TRAS_Msk                         /*!<TRAS[3:0] bits (Self refresh time) */\n#define FMC_SDTR1_TRAS_0            (0x1UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000100 */\n#define FMC_SDTR1_TRAS_1            (0x2UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000200 */\n#define FMC_SDTR1_TRAS_2            (0x4UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000400 */\n#define FMC_SDTR1_TRAS_3            (0x8UL << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000800 */\n\n#define FMC_SDTR1_TRC_Pos           (12U)\n#define FMC_SDTR1_TRC_Msk           (0xFUL << FMC_SDTR1_TRC_Pos)                /*!< 0x0000F000 */\n#define FMC_SDTR1_TRC               FMC_SDTR1_TRC_Msk                          /*!<TRC[2:0] bits (Row cycle delay) */\n#define FMC_SDTR1_TRC_0             (0x1UL << FMC_SDTR1_TRC_Pos)                /*!< 0x00001000 */\n#define FMC_SDTR1_TRC_1             (0x2UL << FMC_SDTR1_TRC_Pos)                /*!< 0x00002000 */\n#define FMC_SDTR1_TRC_2             (0x4UL << FMC_SDTR1_TRC_Pos)                /*!< 0x00004000 */\n\n#define FMC_SDTR1_TWR_Pos           (16U)\n#define FMC_SDTR1_TWR_Msk           (0xFUL << FMC_SDTR1_TWR_Pos)                /*!< 0x000F0000 */\n#define FMC_SDTR1_TWR               FMC_SDTR1_TWR_Msk                          /*!<TRC[2:0] bits (Write recovery delay) */\n#define FMC_SDTR1_TWR_0             (0x1UL << FMC_SDTR1_TWR_Pos)                /*!< 0x00010000 */\n#define FMC_SDTR1_TWR_1             (0x2UL << FMC_SDTR1_TWR_Pos)                /*!< 0x00020000 */\n#define FMC_SDTR1_TWR_2             (0x4UL << FMC_SDTR1_TWR_Pos)                /*!< 0x00040000 */\n\n#define FMC_SDTR1_TRP_Pos           (20U)\n#define FMC_SDTR1_TRP_Msk           (0xFUL << FMC_SDTR1_TRP_Pos)                /*!< 0x00F00000 */\n#define FMC_SDTR1_TRP               FMC_SDTR1_TRP_Msk                          /*!<TRP[2:0] bits (Row precharge delay) */\n#define FMC_SDTR1_TRP_0             (0x1UL << FMC_SDTR1_TRP_Pos)                /*!< 0x00100000 */\n#define FMC_SDTR1_TRP_1             (0x2UL << FMC_SDTR1_TRP_Pos)                /*!< 0x00200000 */\n#define FMC_SDTR1_TRP_2             (0x4UL << FMC_SDTR1_TRP_Pos)                /*!< 0x00400000 */\n\n#define FMC_SDTR1_TRCD_Pos          (24U)\n#define FMC_SDTR1_TRCD_Msk          (0xFUL << FMC_SDTR1_TRCD_Pos)               /*!< 0x0F000000 */\n#define FMC_SDTR1_TRCD              FMC_SDTR1_TRCD_Msk                         /*!<TRP[2:0] bits (Row to column delay) */\n#define FMC_SDTR1_TRCD_0            (0x1UL << FMC_SDTR1_TRCD_Pos)               /*!< 0x01000000 */\n#define FMC_SDTR1_TRCD_1            (0x2UL << FMC_SDTR1_TRCD_Pos)               /*!< 0x02000000 */\n#define FMC_SDTR1_TRCD_2            (0x4UL << FMC_SDTR1_TRCD_Pos)               /*!< 0x04000000 */\n\n/******************  Bit definition for FMC_SDTR2 register  ******************/\n#define FMC_SDTR2_TMRD_Pos          (0U)\n#define FMC_SDTR2_TMRD_Msk          (0xFUL << FMC_SDTR2_TMRD_Pos)               /*!< 0x0000000F */\n#define FMC_SDTR2_TMRD              FMC_SDTR2_TMRD_Msk                         /*!<TMRD[3:0] bits (Load mode register to active) */\n#define FMC_SDTR2_TMRD_0            (0x1UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000001 */\n#define FMC_SDTR2_TMRD_1            (0x2UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000002 */\n#define FMC_SDTR2_TMRD_2            (0x4UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000004 */\n#define FMC_SDTR2_TMRD_3            (0x8UL << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000008 */\n\n#define FMC_SDTR2_TXSR_Pos          (4U)\n#define FMC_SDTR2_TXSR_Msk          (0xFUL << FMC_SDTR2_TXSR_Pos)               /*!< 0x000000F0 */\n#define FMC_SDTR2_TXSR              FMC_SDTR2_TXSR_Msk                         /*!<TXSR[3:0] bits (Exit self refresh) */\n#define FMC_SDTR2_TXSR_0            (0x1UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000010 */\n#define FMC_SDTR2_TXSR_1            (0x2UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000020 */\n#define FMC_SDTR2_TXSR_2            (0x4UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000040 */\n#define FMC_SDTR2_TXSR_3            (0x8UL << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000080 */\n\n#define FMC_SDTR2_TRAS_Pos          (8U)\n#define FMC_SDTR2_TRAS_Msk          (0xFUL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000F00 */\n#define FMC_SDTR2_TRAS              FMC_SDTR2_TRAS_Msk                         /*!<TRAS[3:0] bits (Self refresh time) */\n#define FMC_SDTR2_TRAS_0            (0x1UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000100 */\n#define FMC_SDTR2_TRAS_1            (0x2UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000200 */\n#define FMC_SDTR2_TRAS_2            (0x4UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000400 */\n#define FMC_SDTR2_TRAS_3            (0x8UL << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000800 */\n\n#define FMC_SDTR2_TRC_Pos           (12U)\n#define FMC_SDTR2_TRC_Msk           (0xFUL << FMC_SDTR2_TRC_Pos)                /*!< 0x0000F000 */\n#define FMC_SDTR2_TRC               FMC_SDTR2_TRC_Msk                          /*!<TRC[2:0] bits (Row cycle delay) */\n#define FMC_SDTR2_TRC_0             (0x1UL << FMC_SDTR2_TRC_Pos)                /*!< 0x00001000 */\n#define FMC_SDTR2_TRC_1             (0x2UL << FMC_SDTR2_TRC_Pos)                /*!< 0x00002000 */\n#define FMC_SDTR2_TRC_2             (0x4UL << FMC_SDTR2_TRC_Pos)                /*!< 0x00004000 */\n\n#define FMC_SDTR2_TWR_Pos           (16U)\n#define FMC_SDTR2_TWR_Msk           (0xFUL << FMC_SDTR2_TWR_Pos)                /*!< 0x000F0000 */\n#define FMC_SDTR2_TWR               FMC_SDTR2_TWR_Msk                          /*!<TRC[2:0] bits (Write recovery delay) */\n#define FMC_SDTR2_TWR_0             (0x1UL << FMC_SDTR2_TWR_Pos)                /*!< 0x00010000 */\n#define FMC_SDTR2_TWR_1             (0x2UL << FMC_SDTR2_TWR_Pos)                /*!< 0x00020000 */\n#define FMC_SDTR2_TWR_2             (0x4UL << FMC_SDTR2_TWR_Pos)                /*!< 0x00040000 */\n\n#define FMC_SDTR2_TRP_Pos           (20U)\n#define FMC_SDTR2_TRP_Msk           (0xFUL << FMC_SDTR2_TRP_Pos)                /*!< 0x00F00000 */\n#define FMC_SDTR2_TRP               FMC_SDTR2_TRP_Msk                          /*!<TRP[2:0] bits (Row precharge delay) */\n#define FMC_SDTR2_TRP_0             (0x1UL << FMC_SDTR2_TRP_Pos)                /*!< 0x00100000 */\n#define FMC_SDTR2_TRP_1             (0x2UL << FMC_SDTR2_TRP_Pos)                /*!< 0x00200000 */\n#define FMC_SDTR2_TRP_2             (0x4UL << FMC_SDTR2_TRP_Pos)                /*!< 0x00400000 */\n\n#define FMC_SDTR2_TRCD_Pos          (24U)\n#define FMC_SDTR2_TRCD_Msk          (0xFUL << FMC_SDTR2_TRCD_Pos)               /*!< 0x0F000000 */\n#define FMC_SDTR2_TRCD              FMC_SDTR2_TRCD_Msk                         /*!<TRP[2:0] bits (Row to column delay) */\n#define FMC_SDTR2_TRCD_0            (0x1UL << FMC_SDTR2_TRCD_Pos)               /*!< 0x01000000 */\n#define FMC_SDTR2_TRCD_1            (0x2UL << FMC_SDTR2_TRCD_Pos)               /*!< 0x02000000 */\n#define FMC_SDTR2_TRCD_2            (0x4UL << FMC_SDTR2_TRCD_Pos)               /*!< 0x04000000 */\n\n/******************  Bit definition for FMC_SDCMR register  ******************/\n#define FMC_SDCMR_MODE_Pos          (0U)\n#define FMC_SDCMR_MODE_Msk          (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */\n#define FMC_SDCMR_MODE              FMC_SDCMR_MODE_Msk                         /*!<MODE[2:0] bits (Command mode) */\n#define FMC_SDCMR_MODE_0            (0x1UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000001 */\n#define FMC_SDCMR_MODE_1            (0x2UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000002 */\n#define FMC_SDCMR_MODE_2            (0x4UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000004 */\n\n#define FMC_SDCMR_CTB2_Pos          (3U)\n#define FMC_SDCMR_CTB2_Msk          (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */\n#define FMC_SDCMR_CTB2              FMC_SDCMR_CTB2_Msk                         /*!<Command target 2 */\n\n#define FMC_SDCMR_CTB1_Pos          (4U)\n#define FMC_SDCMR_CTB1_Msk          (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */\n#define FMC_SDCMR_CTB1              FMC_SDCMR_CTB1_Msk                         /*!<Command target 1 */\n\n#define FMC_SDCMR_NRFS_Pos          (5U)\n#define FMC_SDCMR_NRFS_Msk          (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */\n#define FMC_SDCMR_NRFS              FMC_SDCMR_NRFS_Msk                         /*!<NRFS[3:0] bits (Number of auto-refresh) */\n#define FMC_SDCMR_NRFS_0            (0x1UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000020 */\n#define FMC_SDCMR_NRFS_1            (0x2UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000040 */\n#define FMC_SDCMR_NRFS_2            (0x4UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000080 */\n#define FMC_SDCMR_NRFS_3            (0x8UL << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000100 */\n\n#define FMC_SDCMR_MRD_Pos           (9U)\n#define FMC_SDCMR_MRD_Msk           (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */\n#define FMC_SDCMR_MRD               FMC_SDCMR_MRD_Msk                          /*!<MRD[12:0] bits (Mode register definition) */\n\n/******************  Bit definition for FMC_SDRTR register  ******************/\n#define FMC_SDRTR_CRE_Pos           (0U)\n#define FMC_SDRTR_CRE_Msk           (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */\n#define FMC_SDRTR_CRE               FMC_SDRTR_CRE_Msk                          /*!<Clear refresh error flag */\n\n#define FMC_SDRTR_COUNT_Pos         (1U)\n#define FMC_SDRTR_COUNT_Msk         (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */\n#define FMC_SDRTR_COUNT             FMC_SDRTR_COUNT_Msk                        /*!<COUNT[12:0] bits (Refresh timer count) */\n\n#define FMC_SDRTR_REIE_Pos          (14U)\n#define FMC_SDRTR_REIE_Msk          (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */\n#define FMC_SDRTR_REIE              FMC_SDRTR_REIE_Msk                         /*!<RES interupt enable */\n\n/******************  Bit definition for FMC_SDSR register  ******************/\n#define FMC_SDSR_RE_Pos             (0U)\n#define FMC_SDSR_RE_Msk             (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */\n#define FMC_SDSR_RE                 FMC_SDSR_RE_Msk                            /*!<Refresh error flag */\n\n#define FMC_SDSR_MODES1_Pos         (1U)\n#define FMC_SDSR_MODES1_Msk         (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */\n#define FMC_SDSR_MODES1             FMC_SDSR_MODES1_Msk                        /*!<MODES1[1:0]bits (Status mode for bank 1) */\n#define FMC_SDSR_MODES1_0           (0x1UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000002 */\n#define FMC_SDSR_MODES1_1           (0x2UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000004 */\n\n#define FMC_SDSR_MODES2_Pos         (3U)\n#define FMC_SDSR_MODES2_Msk         (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */\n#define FMC_SDSR_MODES2             FMC_SDSR_MODES2_Msk                        /*!<MODES2[1:0]bits (Status mode for bank 2) */\n#define FMC_SDSR_MODES2_0           (0x1UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000008 */\n#define FMC_SDSR_MODES2_1           (0x2UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000010 */\n#define FMC_SDSR_BUSY_Pos           (5U)\n#define FMC_SDSR_BUSY_Msk           (0x1UL << FMC_SDSR_BUSY_Pos)                /*!< 0x00000020 */\n#define FMC_SDSR_BUSY               FMC_SDSR_BUSY_Msk                          /*!<Busy status */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            General Purpose I/O                             */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bits definition for GPIO_MODER register  *****************/\n#define GPIO_MODER_MODER0_Pos            (0U)\n#define GPIO_MODER_MODER0_Msk            (0x3UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */\n#define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk\n#define GPIO_MODER_MODER0_0              (0x1UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */\n#define GPIO_MODER_MODER0_1              (0x2UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */\n#define GPIO_MODER_MODER1_Pos            (2U)\n#define GPIO_MODER_MODER1_Msk            (0x3UL << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */\n#define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk\n#define GPIO_MODER_MODER1_0              (0x1UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */\n#define GPIO_MODER_MODER1_1              (0x2UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */\n#define GPIO_MODER_MODER2_Pos            (4U)\n#define GPIO_MODER_MODER2_Msk            (0x3UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */\n#define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk\n#define GPIO_MODER_MODER2_0              (0x1UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */\n#define GPIO_MODER_MODER2_1              (0x2UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */\n#define GPIO_MODER_MODER3_Pos            (6U)\n#define GPIO_MODER_MODER3_Msk            (0x3UL << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */\n#define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk\n#define GPIO_MODER_MODER3_0              (0x1UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */\n#define GPIO_MODER_MODER3_1              (0x2UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */\n#define GPIO_MODER_MODER4_Pos            (8U)\n#define GPIO_MODER_MODER4_Msk            (0x3UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */\n#define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk\n#define GPIO_MODER_MODER4_0              (0x1UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */\n#define GPIO_MODER_MODER4_1              (0x2UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */\n#define GPIO_MODER_MODER5_Pos            (10U)\n#define GPIO_MODER_MODER5_Msk            (0x3UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */\n#define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk\n#define GPIO_MODER_MODER5_0              (0x1UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */\n#define GPIO_MODER_MODER5_1              (0x2UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */\n#define GPIO_MODER_MODER6_Pos            (12U)\n#define GPIO_MODER_MODER6_Msk            (0x3UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */\n#define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk\n#define GPIO_MODER_MODER6_0              (0x1UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */\n#define GPIO_MODER_MODER6_1              (0x2UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */\n#define GPIO_MODER_MODER7_Pos            (14U)\n#define GPIO_MODER_MODER7_Msk            (0x3UL << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */\n#define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk\n#define GPIO_MODER_MODER7_0              (0x1UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */\n#define GPIO_MODER_MODER7_1              (0x2UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */\n#define GPIO_MODER_MODER8_Pos            (16U)\n#define GPIO_MODER_MODER8_Msk            (0x3UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */\n#define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk\n#define GPIO_MODER_MODER8_0              (0x1UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */\n#define GPIO_MODER_MODER8_1              (0x2UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */\n#define GPIO_MODER_MODER9_Pos            (18U)\n#define GPIO_MODER_MODER9_Msk            (0x3UL << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */\n#define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk\n#define GPIO_MODER_MODER9_0              (0x1UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */\n#define GPIO_MODER_MODER9_1              (0x2UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */\n#define GPIO_MODER_MODER10_Pos           (20U)\n#define GPIO_MODER_MODER10_Msk           (0x3UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */\n#define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk\n#define GPIO_MODER_MODER10_0             (0x1UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */\n#define GPIO_MODER_MODER10_1             (0x2UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */\n#define GPIO_MODER_MODER11_Pos           (22U)\n#define GPIO_MODER_MODER11_Msk           (0x3UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */\n#define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk\n#define GPIO_MODER_MODER11_0             (0x1UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */\n#define GPIO_MODER_MODER11_1             (0x2UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */\n#define GPIO_MODER_MODER12_Pos           (24U)\n#define GPIO_MODER_MODER12_Msk           (0x3UL << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */\n#define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk\n#define GPIO_MODER_MODER12_0             (0x1UL << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */\n#define GPIO_MODER_MODER12_1             (0x2UL << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */\n#define GPIO_MODER_MODER13_Pos           (26U)\n#define GPIO_MODER_MODER13_Msk           (0x3UL << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */\n#define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk\n#define GPIO_MODER_MODER13_0             (0x1UL << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */\n#define GPIO_MODER_MODER13_1             (0x2UL << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */\n#define GPIO_MODER_MODER14_Pos           (28U)\n#define GPIO_MODER_MODER14_Msk           (0x3UL << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */\n#define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk\n#define GPIO_MODER_MODER14_0             (0x1UL << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */\n#define GPIO_MODER_MODER14_1             (0x2UL << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */\n#define GPIO_MODER_MODER15_Pos           (30U)\n#define GPIO_MODER_MODER15_Msk           (0x3UL << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */\n#define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk\n#define GPIO_MODER_MODER15_0             (0x1UL << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */\n#define GPIO_MODER_MODER15_1             (0x2UL << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_MODER_MODE0_Pos             GPIO_MODER_MODER0_Pos\n#define GPIO_MODER_MODE0_Msk             GPIO_MODER_MODER0_Msk\n#define GPIO_MODER_MODE0                 GPIO_MODER_MODER0\n#define GPIO_MODER_MODE0_0               GPIO_MODER_MODER0_0\n#define GPIO_MODER_MODE0_1               GPIO_MODER_MODER0_1\n#define GPIO_MODER_MODE1_Pos             GPIO_MODER_MODER1_Pos\n#define GPIO_MODER_MODE1_Msk             GPIO_MODER_MODER1_Msk\n#define GPIO_MODER_MODE1                 GPIO_MODER_MODER1\n#define GPIO_MODER_MODE1_0               GPIO_MODER_MODER1_0\n#define GPIO_MODER_MODE1_1               GPIO_MODER_MODER1_1\n#define GPIO_MODER_MODE2_Pos             GPIO_MODER_MODER2_PoS\n#define GPIO_MODER_MODE2_Msk             GPIO_MODER_MODER2_Msk\n#define GPIO_MODER_MODE2                 GPIO_MODER_MODER2\n#define GPIO_MODER_MODE2_0               GPIO_MODER_MODER2_0\n#define GPIO_MODER_MODE2_1               GPIO_MODER_MODER2_1\n#define GPIO_MODER_MODE3_Pos             GPIO_MODER_MODER3_Pos\n#define GPIO_MODER_MODE3_Msk             GPIO_MODER_MODER3_Msk\n#define GPIO_MODER_MODE3                 GPIO_MODER_MODER3\n#define GPIO_MODER_MODE3_0               GPIO_MODER_MODER3_0\n#define GPIO_MODER_MODE3_1               GPIO_MODER_MODER3_1\n#define GPIO_MODER_MODE4_Pos             GPIO_MODER_MODER4_Pos\n#define GPIO_MODER_MODE4_Msk             GPIO_MODER_MODER4_Msk\n#define GPIO_MODER_MODE4                 GPIO_MODER_MODER4\n#define GPIO_MODER_MODE4_0               GPIO_MODER_MODER4_0\n#define GPIO_MODER_MODE4_1               GPIO_MODER_MODER4_1\n#define GPIO_MODER_MODE5_Pos             GPIO_MODER_MODER5_Pos\n#define GPIO_MODER_MODE5_Msk             GPIO_MODER_MODER5_Msk\n#define GPIO_MODER_MODE5                 GPIO_MODER_MODER5\n#define GPIO_MODER_MODE5_0               GPIO_MODER_MODER5_0\n#define GPIO_MODER_MODE5_1               GPIO_MODER_MODER5_1\n#define GPIO_MODER_MODE6_Pos             GPIO_MODER_MODER6_Pos\n#define GPIO_MODER_MODE6_Msk             GPIO_MODER_MODER6_Msk\n#define GPIO_MODER_MODE6                 GPIO_MODER_MODER6\n#define GPIO_MODER_MODE6_0               GPIO_MODER_MODER6_0\n#define GPIO_MODER_MODE6_1               GPIO_MODER_MODER6_1\n#define GPIO_MODER_MODE7_Pos             GPIO_MODER_MODER7_Pos\n#define GPIO_MODER_MODE7_Msk             GPIO_MODER_MODER7_Msk\n#define GPIO_MODER_MODE7                 GPIO_MODER_MODER7\n#define GPIO_MODER_MODE7_0               GPIO_MODER_MODER7_0\n#define GPIO_MODER_MODE7_1               GPIO_MODER_MODER7_1\n#define GPIO_MODER_MODE8_Pos             GPIO_MODER_MODER8_Pos\n#define GPIO_MODER_MODE8_Msk             GPIO_MODER_MODER2_Msk\n#define GPIO_MODER_MODE8                 GPIO_MODER_MODER8\n#define GPIO_MODER_MODE8_0               GPIO_MODER_MODER8_0\n#define GPIO_MODER_MODE8_1               GPIO_MODER_MODER8_1\n#define GPIO_MODER_MODE9_Pos             GPIO_MODER_MODER9_Pos\n#define GPIO_MODER_MODE9_Msk             GPIO_MODER_MODER9_Msk\n#define GPIO_MODER_MODE9                 GPIO_MODER_MODER9\n#define GPIO_MODER_MODE9_0               GPIO_MODER_MODER9_0\n#define GPIO_MODER_MODE9_1               GPIO_MODER_MODER9_1\n#define GPIO_MODER_MODE10_Pos            GPIO_MODER_MODER10_Pos\n#define GPIO_MODER_MODE10_Msk            GPIO_MODER_MODER10_Msk\n#define GPIO_MODER_MODE10                GPIO_MODER_MODER10\n#define GPIO_MODER_MODE10_0              GPIO_MODER_MODER10_0\n#define GPIO_MODER_MODE10_1              GPIO_MODER_MODER10_1\n#define GPIO_MODER_MODE11_Pos            GPIO_MODER_MODER11_Pos\n#define GPIO_MODER_MODE11_Msk            GPIO_MODER_MODER11_Msk\n#define GPIO_MODER_MODE11                GPIO_MODER_MODER11\n#define GPIO_MODER_MODE11_0              GPIO_MODER_MODER11_0\n#define GPIO_MODER_MODE11_1              GPIO_MODER_MODER11_1\n#define GPIO_MODER_MODE12_Pos            GPIO_MODER_MODER12_Pos\n#define GPIO_MODER_MODE12_Msk            GPIO_MODER_MODER12_Msk\n#define GPIO_MODER_MODE12                GPIO_MODER_MODER12\n#define GPIO_MODER_MODE12_0              GPIO_MODER_MODER12_0\n#define GPIO_MODER_MODE12_1              GPIO_MODER_MODER12_1\n#define GPIO_MODER_MODE13_Pos            GPIO_MODER_MODER13_Pos\n#define GPIO_MODER_MODE13_Msk            GPIO_MODER_MODER13_Msk\n#define GPIO_MODER_MODE13                GPIO_MODER_MODER13\n#define GPIO_MODER_MODE13_0              GPIO_MODER_MODER13_0\n#define GPIO_MODER_MODE13_1              GPIO_MODER_MODER13_1\n#define GPIO_MODER_MODE14_Pos            GPIO_MODER_MODER14_Pos\n#define GPIO_MODER_MODE14_Msk            GPIO_MODER_MODER14_Msk\n#define GPIO_MODER_MODE14                GPIO_MODER_MODER14\n#define GPIO_MODER_MODE14_0              GPIO_MODER_MODER14_0\n#define GPIO_MODER_MODE14_1              GPIO_MODER_MODER14_1\n#define GPIO_MODER_MODE15_Pos            GPIO_MODER_MODER15_Pos\n#define GPIO_MODER_MODE15_Msk            GPIO_MODER_MODER15_Msk\n#define GPIO_MODER_MODE15                GPIO_MODER_MODER15\n#define GPIO_MODER_MODE15_0              GPIO_MODER_MODER15_0\n#define GPIO_MODER_MODE15_1              GPIO_MODER_MODER15_1\n\n/******************  Bits definition for GPIO_OTYPER register  ****************/\n#define GPIO_OTYPER_OT0_Pos              (0U)\n#define GPIO_OTYPER_OT0_Msk              (0x1UL << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */\n#define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk\n#define GPIO_OTYPER_OT1_Pos              (1U)\n#define GPIO_OTYPER_OT1_Msk              (0x1UL << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */\n#define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk\n#define GPIO_OTYPER_OT2_Pos              (2U)\n#define GPIO_OTYPER_OT2_Msk              (0x1UL << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */\n#define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk\n#define GPIO_OTYPER_OT3_Pos              (3U)\n#define GPIO_OTYPER_OT3_Msk              (0x1UL << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */\n#define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk\n#define GPIO_OTYPER_OT4_Pos              (4U)\n#define GPIO_OTYPER_OT4_Msk              (0x1UL << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */\n#define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk\n#define GPIO_OTYPER_OT5_Pos              (5U)\n#define GPIO_OTYPER_OT5_Msk              (0x1UL << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */\n#define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk\n#define GPIO_OTYPER_OT6_Pos              (6U)\n#define GPIO_OTYPER_OT6_Msk              (0x1UL << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */\n#define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk\n#define GPIO_OTYPER_OT7_Pos              (7U)\n#define GPIO_OTYPER_OT7_Msk              (0x1UL << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */\n#define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk\n#define GPIO_OTYPER_OT8_Pos              (8U)\n#define GPIO_OTYPER_OT8_Msk              (0x1UL << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */\n#define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk\n#define GPIO_OTYPER_OT9_Pos              (9U)\n#define GPIO_OTYPER_OT9_Msk              (0x1UL << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */\n#define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk\n#define GPIO_OTYPER_OT10_Pos             (10U)\n#define GPIO_OTYPER_OT10_Msk             (0x1UL << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */\n#define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk\n#define GPIO_OTYPER_OT11_Pos             (11U)\n#define GPIO_OTYPER_OT11_Msk             (0x1UL << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */\n#define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk\n#define GPIO_OTYPER_OT12_Pos             (12U)\n#define GPIO_OTYPER_OT12_Msk             (0x1UL << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */\n#define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk\n#define GPIO_OTYPER_OT13_Pos             (13U)\n#define GPIO_OTYPER_OT13_Msk             (0x1UL << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */\n#define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk\n#define GPIO_OTYPER_OT14_Pos             (14U)\n#define GPIO_OTYPER_OT14_Msk             (0x1UL << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */\n#define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk\n#define GPIO_OTYPER_OT15_Pos             (15U)\n#define GPIO_OTYPER_OT15_Msk             (0x1UL << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */\n#define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk\n\n/* Legacy defines */\n#define GPIO_OTYPER_OT_0                 GPIO_OTYPER_OT0\n#define GPIO_OTYPER_OT_1                 GPIO_OTYPER_OT1\n#define GPIO_OTYPER_OT_2                 GPIO_OTYPER_OT2\n#define GPIO_OTYPER_OT_3                 GPIO_OTYPER_OT3\n#define GPIO_OTYPER_OT_4                 GPIO_OTYPER_OT4\n#define GPIO_OTYPER_OT_5                 GPIO_OTYPER_OT5\n#define GPIO_OTYPER_OT_6                 GPIO_OTYPER_OT6\n#define GPIO_OTYPER_OT_7                 GPIO_OTYPER_OT7\n#define GPIO_OTYPER_OT_8                 GPIO_OTYPER_OT8\n#define GPIO_OTYPER_OT_9                 GPIO_OTYPER_OT9\n#define GPIO_OTYPER_OT_10                GPIO_OTYPER_OT10\n#define GPIO_OTYPER_OT_11                GPIO_OTYPER_OT11\n#define GPIO_OTYPER_OT_12                GPIO_OTYPER_OT12\n#define GPIO_OTYPER_OT_13                GPIO_OTYPER_OT13\n#define GPIO_OTYPER_OT_14                GPIO_OTYPER_OT14\n#define GPIO_OTYPER_OT_15                GPIO_OTYPER_OT15\n\n/******************  Bits definition for GPIO_OSPEEDR register  ***************/\n#define GPIO_OSPEEDR_OSPEED0_Pos         (0U)\n#define GPIO_OSPEEDR_OSPEED0_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000003 */\n#define GPIO_OSPEEDR_OSPEED0             GPIO_OSPEEDR_OSPEED0_Msk\n#define GPIO_OSPEEDR_OSPEED0_0           (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000001 */\n#define GPIO_OSPEEDR_OSPEED0_1           (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000002 */\n#define GPIO_OSPEEDR_OSPEED1_Pos         (2U)\n#define GPIO_OSPEEDR_OSPEED1_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x0000000C */\n#define GPIO_OSPEEDR_OSPEED1             GPIO_OSPEEDR_OSPEED1_Msk\n#define GPIO_OSPEEDR_OSPEED1_0           (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000004 */\n#define GPIO_OSPEEDR_OSPEED1_1           (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000008 */\n#define GPIO_OSPEEDR_OSPEED2_Pos         (4U)\n#define GPIO_OSPEEDR_OSPEED2_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000030 */\n#define GPIO_OSPEEDR_OSPEED2             GPIO_OSPEEDR_OSPEED2_Msk\n#define GPIO_OSPEEDR_OSPEED2_0           (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000010 */\n#define GPIO_OSPEEDR_OSPEED2_1           (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000020 */\n#define GPIO_OSPEEDR_OSPEED3_Pos         (6U)\n#define GPIO_OSPEEDR_OSPEED3_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x000000C0 */\n#define GPIO_OSPEEDR_OSPEED3             GPIO_OSPEEDR_OSPEED3_Msk\n#define GPIO_OSPEEDR_OSPEED3_0           (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000040 */\n#define GPIO_OSPEEDR_OSPEED3_1           (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000080 */\n#define GPIO_OSPEEDR_OSPEED4_Pos         (8U)\n#define GPIO_OSPEEDR_OSPEED4_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000300 */\n#define GPIO_OSPEEDR_OSPEED4             GPIO_OSPEEDR_OSPEED4_Msk\n#define GPIO_OSPEEDR_OSPEED4_0           (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000100 */\n#define GPIO_OSPEEDR_OSPEED4_1           (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000200 */\n#define GPIO_OSPEEDR_OSPEED5_Pos         (10U)\n#define GPIO_OSPEEDR_OSPEED5_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000C00 */\n#define GPIO_OSPEEDR_OSPEED5             GPIO_OSPEEDR_OSPEED5_Msk\n#define GPIO_OSPEEDR_OSPEED5_0           (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000400 */\n#define GPIO_OSPEEDR_OSPEED5_1           (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000800 */\n#define GPIO_OSPEEDR_OSPEED6_Pos         (12U)\n#define GPIO_OSPEEDR_OSPEED6_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00003000 */\n#define GPIO_OSPEEDR_OSPEED6             GPIO_OSPEEDR_OSPEED6_Msk\n#define GPIO_OSPEEDR_OSPEED6_0           (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00001000 */\n#define GPIO_OSPEEDR_OSPEED6_1           (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00002000 */\n#define GPIO_OSPEEDR_OSPEED7_Pos         (14U)\n#define GPIO_OSPEEDR_OSPEED7_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x0000C000 */\n#define GPIO_OSPEEDR_OSPEED7             GPIO_OSPEEDR_OSPEED7_Msk\n#define GPIO_OSPEEDR_OSPEED7_0           (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00004000 */\n#define GPIO_OSPEEDR_OSPEED7_1           (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00008000 */\n#define GPIO_OSPEEDR_OSPEED8_Pos         (16U)\n#define GPIO_OSPEEDR_OSPEED8_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00030000 */\n#define GPIO_OSPEEDR_OSPEED8             GPIO_OSPEEDR_OSPEED8_Msk\n#define GPIO_OSPEEDR_OSPEED8_0           (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00010000 */\n#define GPIO_OSPEEDR_OSPEED8_1           (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00020000 */\n#define GPIO_OSPEEDR_OSPEED9_Pos         (18U)\n#define GPIO_OSPEEDR_OSPEED9_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x000C0000 */\n#define GPIO_OSPEEDR_OSPEED9             GPIO_OSPEEDR_OSPEED9_Msk\n#define GPIO_OSPEEDR_OSPEED9_0           (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00040000 */\n#define GPIO_OSPEEDR_OSPEED9_1           (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00080000 */\n#define GPIO_OSPEEDR_OSPEED10_Pos        (20U)\n#define GPIO_OSPEEDR_OSPEED10_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00300000 */\n#define GPIO_OSPEEDR_OSPEED10            GPIO_OSPEEDR_OSPEED10_Msk\n#define GPIO_OSPEEDR_OSPEED10_0          (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00100000 */\n#define GPIO_OSPEEDR_OSPEED10_1          (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00200000 */\n#define GPIO_OSPEEDR_OSPEED11_Pos        (22U)\n#define GPIO_OSPEEDR_OSPEED11_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00C00000 */\n#define GPIO_OSPEEDR_OSPEED11            GPIO_OSPEEDR_OSPEED11_Msk\n#define GPIO_OSPEEDR_OSPEED11_0          (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00400000 */\n#define GPIO_OSPEEDR_OSPEED11_1          (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00800000 */\n#define GPIO_OSPEEDR_OSPEED12_Pos        (24U)\n#define GPIO_OSPEEDR_OSPEED12_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x03000000 */\n#define GPIO_OSPEEDR_OSPEED12            GPIO_OSPEEDR_OSPEED12_Msk\n#define GPIO_OSPEEDR_OSPEED12_0          (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x01000000 */\n#define GPIO_OSPEEDR_OSPEED12_1          (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x02000000 */\n#define GPIO_OSPEEDR_OSPEED13_Pos        (26U)\n#define GPIO_OSPEEDR_OSPEED13_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x0C000000 */\n#define GPIO_OSPEEDR_OSPEED13            GPIO_OSPEEDR_OSPEED13_Msk\n#define GPIO_OSPEEDR_OSPEED13_0          (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x04000000 */\n#define GPIO_OSPEEDR_OSPEED13_1          (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x08000000 */\n#define GPIO_OSPEEDR_OSPEED14_Pos        (28U)\n#define GPIO_OSPEEDR_OSPEED14_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x30000000 */\n#define GPIO_OSPEEDR_OSPEED14            GPIO_OSPEEDR_OSPEED14_Msk\n#define GPIO_OSPEEDR_OSPEED14_0          (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x10000000 */\n#define GPIO_OSPEEDR_OSPEED14_1          (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x20000000 */\n#define GPIO_OSPEEDR_OSPEED15_Pos        (30U)\n#define GPIO_OSPEEDR_OSPEED15_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0xC0000000 */\n#define GPIO_OSPEEDR_OSPEED15            GPIO_OSPEEDR_OSPEED15_Msk\n#define GPIO_OSPEEDR_OSPEED15_0          (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x40000000 */\n#define GPIO_OSPEEDR_OSPEED15_1          (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDR_OSPEED0\n#define GPIO_OSPEEDER_OSPEEDR0_0         GPIO_OSPEEDR_OSPEED0_0\n#define GPIO_OSPEEDER_OSPEEDR0_1         GPIO_OSPEEDR_OSPEED0_1\n#define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDR_OSPEED1\n#define GPIO_OSPEEDER_OSPEEDR1_0         GPIO_OSPEEDR_OSPEED1_0\n#define GPIO_OSPEEDER_OSPEEDR1_1         GPIO_OSPEEDR_OSPEED1_1\n#define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDR_OSPEED2\n#define GPIO_OSPEEDER_OSPEEDR2_0         GPIO_OSPEEDR_OSPEED2_0\n#define GPIO_OSPEEDER_OSPEEDR2_1         GPIO_OSPEEDR_OSPEED2_1\n#define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDR_OSPEED3\n#define GPIO_OSPEEDER_OSPEEDR3_0         GPIO_OSPEEDR_OSPEED3_0\n#define GPIO_OSPEEDER_OSPEEDR3_1         GPIO_OSPEEDR_OSPEED3_1\n#define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDR_OSPEED4\n#define GPIO_OSPEEDER_OSPEEDR4_0         GPIO_OSPEEDR_OSPEED4_0\n#define GPIO_OSPEEDER_OSPEEDR4_1         GPIO_OSPEEDR_OSPEED4_1\n#define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDR_OSPEED5\n#define GPIO_OSPEEDER_OSPEEDR5_0         GPIO_OSPEEDR_OSPEED5_0\n#define GPIO_OSPEEDER_OSPEEDR5_1         GPIO_OSPEEDR_OSPEED5_1\n#define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDR_OSPEED6\n#define GPIO_OSPEEDER_OSPEEDR6_0         GPIO_OSPEEDR_OSPEED6_0\n#define GPIO_OSPEEDER_OSPEEDR6_1         GPIO_OSPEEDR_OSPEED6_1\n#define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDR_OSPEED7\n#define GPIO_OSPEEDER_OSPEEDR7_0         GPIO_OSPEEDR_OSPEED7_0\n#define GPIO_OSPEEDER_OSPEEDR7_1         GPIO_OSPEEDR_OSPEED7_1\n#define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDR_OSPEED8\n#define GPIO_OSPEEDER_OSPEEDR8_0         GPIO_OSPEEDR_OSPEED8_0\n#define GPIO_OSPEEDER_OSPEEDR8_1         GPIO_OSPEEDR_OSPEED8_1\n#define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDR_OSPEED9\n#define GPIO_OSPEEDER_OSPEEDR9_0         GPIO_OSPEEDR_OSPEED9_0\n#define GPIO_OSPEEDER_OSPEEDR9_1         GPIO_OSPEEDR_OSPEED9_1\n#define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDR_OSPEED10\n#define GPIO_OSPEEDER_OSPEEDR10_0        GPIO_OSPEEDR_OSPEED10_0\n#define GPIO_OSPEEDER_OSPEEDR10_1        GPIO_OSPEEDR_OSPEED10_1\n#define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDR_OSPEED11\n#define GPIO_OSPEEDER_OSPEEDR11_0        GPIO_OSPEEDR_OSPEED11_0\n#define GPIO_OSPEEDER_OSPEEDR11_1        GPIO_OSPEEDR_OSPEED11_1\n#define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDR_OSPEED12\n#define GPIO_OSPEEDER_OSPEEDR12_0        GPIO_OSPEEDR_OSPEED12_0\n#define GPIO_OSPEEDER_OSPEEDR12_1        GPIO_OSPEEDR_OSPEED12_1\n#define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDR_OSPEED13\n#define GPIO_OSPEEDER_OSPEEDR13_0        GPIO_OSPEEDR_OSPEED13_0\n#define GPIO_OSPEEDER_OSPEEDR13_1        GPIO_OSPEEDR_OSPEED13_1\n#define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDR_OSPEED14\n#define GPIO_OSPEEDER_OSPEEDR14_0        GPIO_OSPEEDR_OSPEED14_0\n#define GPIO_OSPEEDER_OSPEEDR14_1        GPIO_OSPEEDR_OSPEED14_1\n#define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDR_OSPEED15\n#define GPIO_OSPEEDER_OSPEEDR15_0        GPIO_OSPEEDR_OSPEED15_0\n#define GPIO_OSPEEDER_OSPEEDR15_1        GPIO_OSPEEDR_OSPEED15_1\n\n/******************  Bits definition for GPIO_PUPDR register  *****************/\n#define GPIO_PUPDR_PUPD0_Pos             (0U)\n#define GPIO_PUPDR_PUPD0_Msk             (0x3UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000003 */\n#define GPIO_PUPDR_PUPD0                 GPIO_PUPDR_PUPD0_Msk\n#define GPIO_PUPDR_PUPD0_0               (0x1UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000001 */\n#define GPIO_PUPDR_PUPD0_1               (0x2UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000002 */\n#define GPIO_PUPDR_PUPD1_Pos             (2U)\n#define GPIO_PUPDR_PUPD1_Msk             (0x3UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x0000000C */\n#define GPIO_PUPDR_PUPD1                 GPIO_PUPDR_PUPD1_Msk\n#define GPIO_PUPDR_PUPD1_0               (0x1UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000004 */\n#define GPIO_PUPDR_PUPD1_1               (0x2UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000008 */\n#define GPIO_PUPDR_PUPD2_Pos             (4U)\n#define GPIO_PUPDR_PUPD2_Msk             (0x3UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000030 */\n#define GPIO_PUPDR_PUPD2                 GPIO_PUPDR_PUPD2_Msk\n#define GPIO_PUPDR_PUPD2_0               (0x1UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000010 */\n#define GPIO_PUPDR_PUPD2_1               (0x2UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000020 */\n#define GPIO_PUPDR_PUPD3_Pos             (6U)\n#define GPIO_PUPDR_PUPD3_Msk             (0x3UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x000000C0 */\n#define GPIO_PUPDR_PUPD3                 GPIO_PUPDR_PUPD3_Msk\n#define GPIO_PUPDR_PUPD3_0               (0x1UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000040 */\n#define GPIO_PUPDR_PUPD3_1               (0x2UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000080 */\n#define GPIO_PUPDR_PUPD4_Pos             (8U)\n#define GPIO_PUPDR_PUPD4_Msk             (0x3UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000300 */\n#define GPIO_PUPDR_PUPD4                 GPIO_PUPDR_PUPD4_Msk\n#define GPIO_PUPDR_PUPD4_0               (0x1UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000100 */\n#define GPIO_PUPDR_PUPD4_1               (0x2UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000200 */\n#define GPIO_PUPDR_PUPD5_Pos             (10U)\n#define GPIO_PUPDR_PUPD5_Msk             (0x3UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000C00 */\n#define GPIO_PUPDR_PUPD5                 GPIO_PUPDR_PUPD5_Msk\n#define GPIO_PUPDR_PUPD5_0               (0x1UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000400 */\n#define GPIO_PUPDR_PUPD5_1               (0x2UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000800 */\n#define GPIO_PUPDR_PUPD6_Pos             (12U)\n#define GPIO_PUPDR_PUPD6_Msk             (0x3UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00003000 */\n#define GPIO_PUPDR_PUPD6                 GPIO_PUPDR_PUPD6_Msk\n#define GPIO_PUPDR_PUPD6_0               (0x1UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00001000 */\n#define GPIO_PUPDR_PUPD6_1               (0x2UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00002000 */\n#define GPIO_PUPDR_PUPD7_Pos             (14U)\n#define GPIO_PUPDR_PUPD7_Msk             (0x3UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x0000C000 */\n#define GPIO_PUPDR_PUPD7                 GPIO_PUPDR_PUPD7_Msk\n#define GPIO_PUPDR_PUPD7_0               (0x1UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00004000 */\n#define GPIO_PUPDR_PUPD7_1               (0x2UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00008000 */\n#define GPIO_PUPDR_PUPD8_Pos             (16U)\n#define GPIO_PUPDR_PUPD8_Msk             (0x3UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00030000 */\n#define GPIO_PUPDR_PUPD8                 GPIO_PUPDR_PUPD8_Msk\n#define GPIO_PUPDR_PUPD8_0               (0x1UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00010000 */\n#define GPIO_PUPDR_PUPD8_1               (0x2UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00020000 */\n#define GPIO_PUPDR_PUPD9_Pos             (18U)\n#define GPIO_PUPDR_PUPD9_Msk             (0x3UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x000C0000 */\n#define GPIO_PUPDR_PUPD9                 GPIO_PUPDR_PUPD9_Msk\n#define GPIO_PUPDR_PUPD9_0               (0x1UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00040000 */\n#define GPIO_PUPDR_PUPD9_1               (0x2UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00080000 */\n#define GPIO_PUPDR_PUPD10_Pos            (20U)\n#define GPIO_PUPDR_PUPD10_Msk            (0x3UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00300000 */\n#define GPIO_PUPDR_PUPD10                GPIO_PUPDR_PUPD10_Msk\n#define GPIO_PUPDR_PUPD10_0              (0x1UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00100000 */\n#define GPIO_PUPDR_PUPD10_1              (0x2UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00200000 */\n#define GPIO_PUPDR_PUPD11_Pos            (22U)\n#define GPIO_PUPDR_PUPD11_Msk            (0x3UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00C00000 */\n#define GPIO_PUPDR_PUPD11                GPIO_PUPDR_PUPD11_Msk\n#define GPIO_PUPDR_PUPD11_0              (0x1UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00400000 */\n#define GPIO_PUPDR_PUPD11_1              (0x2UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00800000 */\n#define GPIO_PUPDR_PUPD12_Pos            (24U)\n#define GPIO_PUPDR_PUPD12_Msk            (0x3UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x03000000 */\n#define GPIO_PUPDR_PUPD12                GPIO_PUPDR_PUPD12_Msk\n#define GPIO_PUPDR_PUPD12_0              (0x1UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x01000000 */\n#define GPIO_PUPDR_PUPD12_1              (0x2UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x02000000 */\n#define GPIO_PUPDR_PUPD13_Pos            (26U)\n#define GPIO_PUPDR_PUPD13_Msk            (0x3UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x0C000000 */\n#define GPIO_PUPDR_PUPD13                GPIO_PUPDR_PUPD13_Msk\n#define GPIO_PUPDR_PUPD13_0              (0x1UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x04000000 */\n#define GPIO_PUPDR_PUPD13_1              (0x2UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x08000000 */\n#define GPIO_PUPDR_PUPD14_Pos            (28U)\n#define GPIO_PUPDR_PUPD14_Msk            (0x3UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x30000000 */\n#define GPIO_PUPDR_PUPD14                GPIO_PUPDR_PUPD14_Msk\n#define GPIO_PUPDR_PUPD14_0              (0x1UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x10000000 */\n#define GPIO_PUPDR_PUPD14_1              (0x2UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x20000000 */\n#define GPIO_PUPDR_PUPD15_Pos            (30U)\n#define GPIO_PUPDR_PUPD15_Msk            (0x3UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0xC0000000 */\n#define GPIO_PUPDR_PUPD15                GPIO_PUPDR_PUPD15_Msk\n#define GPIO_PUPDR_PUPD15_0              (0x1UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x40000000 */\n#define GPIO_PUPDR_PUPD15_1              (0x2UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPD0\n#define GPIO_PUPDR_PUPDR0_0              GPIO_PUPDR_PUPD0_0\n#define GPIO_PUPDR_PUPDR0_1              GPIO_PUPDR_PUPD0_1\n#define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPD1\n#define GPIO_PUPDR_PUPDR1_0              GPIO_PUPDR_PUPD1_0\n#define GPIO_PUPDR_PUPDR1_1              GPIO_PUPDR_PUPD1_1\n#define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPD2\n#define GPIO_PUPDR_PUPDR2_0              GPIO_PUPDR_PUPD2_0\n#define GPIO_PUPDR_PUPDR2_1              GPIO_PUPDR_PUPD2_1\n#define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPD3\n#define GPIO_PUPDR_PUPDR3_0              GPIO_PUPDR_PUPD3_0\n#define GPIO_PUPDR_PUPDR3_1              GPIO_PUPDR_PUPD3_1\n#define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPD4\n#define GPIO_PUPDR_PUPDR4_0              GPIO_PUPDR_PUPD4_0\n#define GPIO_PUPDR_PUPDR4_1              GPIO_PUPDR_PUPD4_1\n#define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPD5\n#define GPIO_PUPDR_PUPDR5_0              GPIO_PUPDR_PUPD5_0\n#define GPIO_PUPDR_PUPDR5_1              GPIO_PUPDR_PUPD5_1\n#define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPD6\n#define GPIO_PUPDR_PUPDR6_0              GPIO_PUPDR_PUPD6_0\n#define GPIO_PUPDR_PUPDR6_1              GPIO_PUPDR_PUPD6_1\n#define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPD7\n#define GPIO_PUPDR_PUPDR7_0              GPIO_PUPDR_PUPD7_0\n#define GPIO_PUPDR_PUPDR7_1              GPIO_PUPDR_PUPD7_1\n#define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPD8\n#define GPIO_PUPDR_PUPDR8_0              GPIO_PUPDR_PUPD8_0\n#define GPIO_PUPDR_PUPDR8_1              GPIO_PUPDR_PUPD8_1\n#define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPD9\n#define GPIO_PUPDR_PUPDR9_0              GPIO_PUPDR_PUPD9_0\n#define GPIO_PUPDR_PUPDR9_1              GPIO_PUPDR_PUPD9_1\n#define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPD10\n#define GPIO_PUPDR_PUPDR10_0             GPIO_PUPDR_PUPD10_0\n#define GPIO_PUPDR_PUPDR10_1             GPIO_PUPDR_PUPD10_1\n#define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPD11\n#define GPIO_PUPDR_PUPDR11_0             GPIO_PUPDR_PUPD11_0\n#define GPIO_PUPDR_PUPDR11_1             GPIO_PUPDR_PUPD11_1\n#define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPD12\n#define GPIO_PUPDR_PUPDR12_0             GPIO_PUPDR_PUPD12_0\n#define GPIO_PUPDR_PUPDR12_1             GPIO_PUPDR_PUPD12_1\n#define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPD13\n#define GPIO_PUPDR_PUPDR13_0             GPIO_PUPDR_PUPD13_0\n#define GPIO_PUPDR_PUPDR13_1             GPIO_PUPDR_PUPD13_1\n#define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPD14\n#define GPIO_PUPDR_PUPDR14_0             GPIO_PUPDR_PUPD14_0\n#define GPIO_PUPDR_PUPDR14_1             GPIO_PUPDR_PUPD14_1\n#define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPD15\n#define GPIO_PUPDR_PUPDR15_0             GPIO_PUPDR_PUPD15_0\n#define GPIO_PUPDR_PUPDR15_1             GPIO_PUPDR_PUPD15_1\n\n/******************  Bits definition for GPIO_IDR register  *******************/\n#define GPIO_IDR_ID0_Pos                 (0U)\n#define GPIO_IDR_ID0_Msk                 (0x1UL << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */\n#define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk\n#define GPIO_IDR_ID1_Pos                 (1U)\n#define GPIO_IDR_ID1_Msk                 (0x1UL << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */\n#define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk\n#define GPIO_IDR_ID2_Pos                 (2U)\n#define GPIO_IDR_ID2_Msk                 (0x1UL << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */\n#define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk\n#define GPIO_IDR_ID3_Pos                 (3U)\n#define GPIO_IDR_ID3_Msk                 (0x1UL << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */\n#define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk\n#define GPIO_IDR_ID4_Pos                 (4U)\n#define GPIO_IDR_ID4_Msk                 (0x1UL << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */\n#define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk\n#define GPIO_IDR_ID5_Pos                 (5U)\n#define GPIO_IDR_ID5_Msk                 (0x1UL << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */\n#define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk\n#define GPIO_IDR_ID6_Pos                 (6U)\n#define GPIO_IDR_ID6_Msk                 (0x1UL << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */\n#define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk\n#define GPIO_IDR_ID7_Pos                 (7U)\n#define GPIO_IDR_ID7_Msk                 (0x1UL << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */\n#define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk\n#define GPIO_IDR_ID8_Pos                 (8U)\n#define GPIO_IDR_ID8_Msk                 (0x1UL << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */\n#define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk\n#define GPIO_IDR_ID9_Pos                 (9U)\n#define GPIO_IDR_ID9_Msk                 (0x1UL << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */\n#define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk\n#define GPIO_IDR_ID10_Pos                (10U)\n#define GPIO_IDR_ID10_Msk                (0x1UL << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */\n#define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk\n#define GPIO_IDR_ID11_Pos                (11U)\n#define GPIO_IDR_ID11_Msk                (0x1UL << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */\n#define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk\n#define GPIO_IDR_ID12_Pos                (12U)\n#define GPIO_IDR_ID12_Msk                (0x1UL << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */\n#define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk\n#define GPIO_IDR_ID13_Pos                (13U)\n#define GPIO_IDR_ID13_Msk                (0x1UL << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */\n#define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk\n#define GPIO_IDR_ID14_Pos                (14U)\n#define GPIO_IDR_ID14_Msk                (0x1UL << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */\n#define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk\n#define GPIO_IDR_ID15_Pos                (15U)\n#define GPIO_IDR_ID15_Msk                (0x1UL << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */\n#define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk\n\n/* Legacy defines */\n#define GPIO_IDR_IDR_0                   GPIO_IDR_ID0\n#define GPIO_IDR_IDR_1                   GPIO_IDR_ID1\n#define GPIO_IDR_IDR_2                   GPIO_IDR_ID2\n#define GPIO_IDR_IDR_3                   GPIO_IDR_ID3\n#define GPIO_IDR_IDR_4                   GPIO_IDR_ID4\n#define GPIO_IDR_IDR_5                   GPIO_IDR_ID5\n#define GPIO_IDR_IDR_6                   GPIO_IDR_ID6\n#define GPIO_IDR_IDR_7                   GPIO_IDR_ID7\n#define GPIO_IDR_IDR_8                   GPIO_IDR_ID8\n#define GPIO_IDR_IDR_9                   GPIO_IDR_ID9\n#define GPIO_IDR_IDR_10                  GPIO_IDR_ID10\n#define GPIO_IDR_IDR_11                  GPIO_IDR_ID11\n#define GPIO_IDR_IDR_12                  GPIO_IDR_ID12\n#define GPIO_IDR_IDR_13                  GPIO_IDR_ID13\n#define GPIO_IDR_IDR_14                  GPIO_IDR_ID14\n#define GPIO_IDR_IDR_15                  GPIO_IDR_ID15\n\n/******************  Bits definition for GPIO_ODR register  *******************/\n#define GPIO_ODR_OD0_Pos                 (0U)\n#define GPIO_ODR_OD0_Msk                 (0x1UL << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */\n#define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk\n#define GPIO_ODR_OD1_Pos                 (1U)\n#define GPIO_ODR_OD1_Msk                 (0x1UL << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */\n#define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk\n#define GPIO_ODR_OD2_Pos                 (2U)\n#define GPIO_ODR_OD2_Msk                 (0x1UL << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */\n#define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk\n#define GPIO_ODR_OD3_Pos                 (3U)\n#define GPIO_ODR_OD3_Msk                 (0x1UL << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */\n#define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk\n#define GPIO_ODR_OD4_Pos                 (4U)\n#define GPIO_ODR_OD4_Msk                 (0x1UL << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */\n#define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk\n#define GPIO_ODR_OD5_Pos                 (5U)\n#define GPIO_ODR_OD5_Msk                 (0x1UL << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */\n#define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk\n#define GPIO_ODR_OD6_Pos                 (6U)\n#define GPIO_ODR_OD6_Msk                 (0x1UL << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */\n#define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk\n#define GPIO_ODR_OD7_Pos                 (7U)\n#define GPIO_ODR_OD7_Msk                 (0x1UL << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */\n#define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk\n#define GPIO_ODR_OD8_Pos                 (8U)\n#define GPIO_ODR_OD8_Msk                 (0x1UL << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */\n#define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk\n#define GPIO_ODR_OD9_Pos                 (9U)\n#define GPIO_ODR_OD9_Msk                 (0x1UL << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */\n#define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk\n#define GPIO_ODR_OD10_Pos                (10U)\n#define GPIO_ODR_OD10_Msk                (0x1UL << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */\n#define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk\n#define GPIO_ODR_OD11_Pos                (11U)\n#define GPIO_ODR_OD11_Msk                (0x1UL << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */\n#define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk\n#define GPIO_ODR_OD12_Pos                (12U)\n#define GPIO_ODR_OD12_Msk                (0x1UL << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */\n#define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk\n#define GPIO_ODR_OD13_Pos                (13U)\n#define GPIO_ODR_OD13_Msk                (0x1UL << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */\n#define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk\n#define GPIO_ODR_OD14_Pos                (14U)\n#define GPIO_ODR_OD14_Msk                (0x1UL << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */\n#define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk\n#define GPIO_ODR_OD15_Pos                (15U)\n#define GPIO_ODR_OD15_Msk                (0x1UL << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */\n#define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk\n/* Legacy defines */\n#define GPIO_ODR_ODR_0                   GPIO_ODR_OD0\n#define GPIO_ODR_ODR_1                   GPIO_ODR_OD1\n#define GPIO_ODR_ODR_2                   GPIO_ODR_OD2\n#define GPIO_ODR_ODR_3                   GPIO_ODR_OD3\n#define GPIO_ODR_ODR_4                   GPIO_ODR_OD4\n#define GPIO_ODR_ODR_5                   GPIO_ODR_OD5\n#define GPIO_ODR_ODR_6                   GPIO_ODR_OD6\n#define GPIO_ODR_ODR_7                   GPIO_ODR_OD7\n#define GPIO_ODR_ODR_8                   GPIO_ODR_OD8\n#define GPIO_ODR_ODR_9                   GPIO_ODR_OD9\n#define GPIO_ODR_ODR_10                  GPIO_ODR_OD10\n#define GPIO_ODR_ODR_11                  GPIO_ODR_OD11\n#define GPIO_ODR_ODR_12                  GPIO_ODR_OD12\n#define GPIO_ODR_ODR_13                  GPIO_ODR_OD13\n#define GPIO_ODR_ODR_14                  GPIO_ODR_OD14\n#define GPIO_ODR_ODR_15                  GPIO_ODR_OD15\n\n/******************  Bits definition for GPIO_BSRR register  ******************/\n#define GPIO_BSRR_BS0_Pos                (0U)\n#define GPIO_BSRR_BS0_Msk                (0x1UL << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */\n#define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk\n#define GPIO_BSRR_BS1_Pos                (1U)\n#define GPIO_BSRR_BS1_Msk                (0x1UL << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */\n#define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk\n#define GPIO_BSRR_BS2_Pos                (2U)\n#define GPIO_BSRR_BS2_Msk                (0x1UL << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */\n#define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk\n#define GPIO_BSRR_BS3_Pos                (3U)\n#define GPIO_BSRR_BS3_Msk                (0x1UL << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */\n#define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk\n#define GPIO_BSRR_BS4_Pos                (4U)\n#define GPIO_BSRR_BS4_Msk                (0x1UL << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */\n#define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk\n#define GPIO_BSRR_BS5_Pos                (5U)\n#define GPIO_BSRR_BS5_Msk                (0x1UL << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */\n#define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk\n#define GPIO_BSRR_BS6_Pos                (6U)\n#define GPIO_BSRR_BS6_Msk                (0x1UL << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */\n#define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk\n#define GPIO_BSRR_BS7_Pos                (7U)\n#define GPIO_BSRR_BS7_Msk                (0x1UL << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */\n#define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk\n#define GPIO_BSRR_BS8_Pos                (8U)\n#define GPIO_BSRR_BS8_Msk                (0x1UL << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */\n#define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk\n#define GPIO_BSRR_BS9_Pos                (9U)\n#define GPIO_BSRR_BS9_Msk                (0x1UL << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */\n#define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk\n#define GPIO_BSRR_BS10_Pos               (10U)\n#define GPIO_BSRR_BS10_Msk               (0x1UL << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */\n#define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk\n#define GPIO_BSRR_BS11_Pos               (11U)\n#define GPIO_BSRR_BS11_Msk               (0x1UL << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */\n#define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk\n#define GPIO_BSRR_BS12_Pos               (12U)\n#define GPIO_BSRR_BS12_Msk               (0x1UL << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */\n#define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk\n#define GPIO_BSRR_BS13_Pos               (13U)\n#define GPIO_BSRR_BS13_Msk               (0x1UL << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */\n#define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk\n#define GPIO_BSRR_BS14_Pos               (14U)\n#define GPIO_BSRR_BS14_Msk               (0x1UL << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */\n#define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk\n#define GPIO_BSRR_BS15_Pos               (15U)\n#define GPIO_BSRR_BS15_Msk               (0x1UL << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */\n#define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk\n#define GPIO_BSRR_BR0_Pos                (16U)\n#define GPIO_BSRR_BR0_Msk                (0x1UL << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */\n#define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk\n#define GPIO_BSRR_BR1_Pos                (17U)\n#define GPIO_BSRR_BR1_Msk                (0x1UL << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */\n#define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk\n#define GPIO_BSRR_BR2_Pos                (18U)\n#define GPIO_BSRR_BR2_Msk                (0x1UL << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */\n#define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk\n#define GPIO_BSRR_BR3_Pos                (19U)\n#define GPIO_BSRR_BR3_Msk                (0x1UL << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */\n#define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk\n#define GPIO_BSRR_BR4_Pos                (20U)\n#define GPIO_BSRR_BR4_Msk                (0x1UL << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */\n#define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk\n#define GPIO_BSRR_BR5_Pos                (21U)\n#define GPIO_BSRR_BR5_Msk                (0x1UL << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */\n#define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk\n#define GPIO_BSRR_BR6_Pos                (22U)\n#define GPIO_BSRR_BR6_Msk                (0x1UL << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */\n#define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk\n#define GPIO_BSRR_BR7_Pos                (23U)\n#define GPIO_BSRR_BR7_Msk                (0x1UL << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */\n#define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk\n#define GPIO_BSRR_BR8_Pos                (24U)\n#define GPIO_BSRR_BR8_Msk                (0x1UL << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */\n#define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk\n#define GPIO_BSRR_BR9_Pos                (25U)\n#define GPIO_BSRR_BR9_Msk                (0x1UL << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */\n#define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk\n#define GPIO_BSRR_BR10_Pos               (26U)\n#define GPIO_BSRR_BR10_Msk               (0x1UL << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */\n#define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk\n#define GPIO_BSRR_BR11_Pos               (27U)\n#define GPIO_BSRR_BR11_Msk               (0x1UL << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */\n#define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk\n#define GPIO_BSRR_BR12_Pos               (28U)\n#define GPIO_BSRR_BR12_Msk               (0x1UL << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */\n#define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk\n#define GPIO_BSRR_BR13_Pos               (29U)\n#define GPIO_BSRR_BR13_Msk               (0x1UL << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */\n#define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk\n#define GPIO_BSRR_BR14_Pos               (30U)\n#define GPIO_BSRR_BR14_Msk               (0x1UL << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */\n#define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk\n#define GPIO_BSRR_BR15_Pos               (31U)\n#define GPIO_BSRR_BR15_Msk               (0x1UL << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */\n#define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk\n\n/* Legacy defines */\n#define GPIO_BSRR_BS_0                   GPIO_BSRR_BS0\n#define GPIO_BSRR_BS_1                   GPIO_BSRR_BS1\n#define GPIO_BSRR_BS_2                   GPIO_BSRR_BS2\n#define GPIO_BSRR_BS_3                   GPIO_BSRR_BS3\n#define GPIO_BSRR_BS_4                   GPIO_BSRR_BS4\n#define GPIO_BSRR_BS_5                   GPIO_BSRR_BS5\n#define GPIO_BSRR_BS_6                   GPIO_BSRR_BS6\n#define GPIO_BSRR_BS_7                   GPIO_BSRR_BS7\n#define GPIO_BSRR_BS_8                   GPIO_BSRR_BS8\n#define GPIO_BSRR_BS_9                   GPIO_BSRR_BS9\n#define GPIO_BSRR_BS_10                  GPIO_BSRR_BS10\n#define GPIO_BSRR_BS_11                  GPIO_BSRR_BS11\n#define GPIO_BSRR_BS_12                  GPIO_BSRR_BS12\n#define GPIO_BSRR_BS_13                  GPIO_BSRR_BS13\n#define GPIO_BSRR_BS_14                  GPIO_BSRR_BS14\n#define GPIO_BSRR_BS_15                  GPIO_BSRR_BS15\n#define GPIO_BSRR_BR_0                   GPIO_BSRR_BR0\n#define GPIO_BSRR_BR_1                   GPIO_BSRR_BR1\n#define GPIO_BSRR_BR_2                   GPIO_BSRR_BR2\n#define GPIO_BSRR_BR_3                   GPIO_BSRR_BR3\n#define GPIO_BSRR_BR_4                   GPIO_BSRR_BR4\n#define GPIO_BSRR_BR_5                   GPIO_BSRR_BR5\n#define GPIO_BSRR_BR_6                   GPIO_BSRR_BR6\n#define GPIO_BSRR_BR_7                   GPIO_BSRR_BR7\n#define GPIO_BSRR_BR_8                   GPIO_BSRR_BR8\n#define GPIO_BSRR_BR_9                   GPIO_BSRR_BR9\n#define GPIO_BSRR_BR_10                  GPIO_BSRR_BR10\n#define GPIO_BSRR_BR_11                  GPIO_BSRR_BR11\n#define GPIO_BSRR_BR_12                  GPIO_BSRR_BR12\n#define GPIO_BSRR_BR_13                  GPIO_BSRR_BR13\n#define GPIO_BSRR_BR_14                  GPIO_BSRR_BR14\n#define GPIO_BSRR_BR_15                  GPIO_BSRR_BR15\n#define GPIO_BRR_BR0                     GPIO_BSRR_BR0\n#define GPIO_BRR_BR0_Pos                 GPIO_BSRR_BR0_Pos\n#define GPIO_BRR_BR0_Msk                 GPIO_BSRR_BR0_Msk\n#define GPIO_BRR_BR1                     GPIO_BSRR_BR1\n#define GPIO_BRR_BR1_Pos                 GPIO_BSRR_BR1_Pos\n#define GPIO_BRR_BR1_Msk                 GPIO_BSRR_BR1_Msk\n#define GPIO_BRR_BR2                     GPIO_BSRR_BR2\n#define GPIO_BRR_BR2_Pos                 GPIO_BSRR_BR2_Pos\n#define GPIO_BRR_BR2_Msk                 GPIO_BSRR_BR2_Msk\n#define GPIO_BRR_BR3                     GPIO_BSRR_BR3\n#define GPIO_BRR_BR3_Pos                 GPIO_BSRR_BR3_Pos\n#define GPIO_BRR_BR3_Msk                 GPIO_BSRR_BR3_Msk\n#define GPIO_BRR_BR4                     GPIO_BSRR_BR4\n#define GPIO_BRR_BR4_Pos                 GPIO_BSRR_BR4_Pos\n#define GPIO_BRR_BR4_Msk                 GPIO_BSRR_BR4_Msk\n#define GPIO_BRR_BR5                     GPIO_BSRR_BR5\n#define GPIO_BRR_BR5_Pos                 GPIO_BSRR_BR5_Pos\n#define GPIO_BRR_BR5_Msk                 GPIO_BSRR_BR5_Msk\n#define GPIO_BRR_BR6                     GPIO_BSRR_BR6\n#define GPIO_BRR_BR6_Pos                 GPIO_BSRR_BR6_Pos\n#define GPIO_BRR_BR6_Msk                 GPIO_BSRR_BR6_Msk\n#define GPIO_BRR_BR7                     GPIO_BSRR_BR7\n#define GPIO_BRR_BR7_Pos                 GPIO_BSRR_BR7_Pos\n#define GPIO_BRR_BR7_Msk                 GPIO_BSRR_BR7_Msk\n#define GPIO_BRR_BR8                     GPIO_BSRR_BR8\n#define GPIO_BRR_BR8_Pos                 GPIO_BSRR_BR8_Pos\n#define GPIO_BRR_BR8_Msk                 GPIO_BSRR_BR8_Msk\n#define GPIO_BRR_BR9                     GPIO_BSRR_BR9\n#define GPIO_BRR_BR9_Pos                 GPIO_BSRR_BR9_Pos\n#define GPIO_BRR_BR9_Msk                 GPIO_BSRR_BR9_Msk\n#define GPIO_BRR_BR10                    GPIO_BSRR_BR10\n#define GPIO_BRR_BR10_Pos                GPIO_BSRR_BR10_Pos\n#define GPIO_BRR_BR10_Msk                GPIO_BSRR_BR10_Msk\n#define GPIO_BRR_BR11                    GPIO_BSRR_BR11\n#define GPIO_BRR_BR11_Pos                GPIO_BSRR_BR11_Pos\n#define GPIO_BRR_BR11_Msk                GPIO_BSRR_BR11_Msk\n#define GPIO_BRR_BR12                    GPIO_BSRR_BR12\n#define GPIO_BRR_BR12_Pos                GPIO_BSRR_BR12_Pos\n#define GPIO_BRR_BR12_Msk                GPIO_BSRR_BR12_Msk\n#define GPIO_BRR_BR13                    GPIO_BSRR_BR13\n#define GPIO_BRR_BR13_Pos                GPIO_BSRR_BR13_Pos\n#define GPIO_BRR_BR13_Msk                GPIO_BSRR_BR13_Msk\n#define GPIO_BRR_BR14                    GPIO_BSRR_BR14\n#define GPIO_BRR_BR14_Pos                GPIO_BSRR_BR14_Pos\n#define GPIO_BRR_BR14_Msk                GPIO_BSRR_BR14_Msk\n#define GPIO_BRR_BR15                    GPIO_BSRR_BR15\n#define GPIO_BRR_BR15_Pos                GPIO_BSRR_BR15_Pos\n#define GPIO_BRR_BR15_Msk                GPIO_BSRR_BR15_Msk\n/****************** Bit definition for GPIO_LCKR register *********************/\n#define GPIO_LCKR_LCK0_Pos               (0U)\n#define GPIO_LCKR_LCK0_Msk               (0x1UL << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */\n#define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk\n#define GPIO_LCKR_LCK1_Pos               (1U)\n#define GPIO_LCKR_LCK1_Msk               (0x1UL << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */\n#define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk\n#define GPIO_LCKR_LCK2_Pos               (2U)\n#define GPIO_LCKR_LCK2_Msk               (0x1UL << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */\n#define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk\n#define GPIO_LCKR_LCK3_Pos               (3U)\n#define GPIO_LCKR_LCK3_Msk               (0x1UL << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */\n#define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk\n#define GPIO_LCKR_LCK4_Pos               (4U)\n#define GPIO_LCKR_LCK4_Msk               (0x1UL << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */\n#define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk\n#define GPIO_LCKR_LCK5_Pos               (5U)\n#define GPIO_LCKR_LCK5_Msk               (0x1UL << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */\n#define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk\n#define GPIO_LCKR_LCK6_Pos               (6U)\n#define GPIO_LCKR_LCK6_Msk               (0x1UL << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */\n#define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk\n#define GPIO_LCKR_LCK7_Pos               (7U)\n#define GPIO_LCKR_LCK7_Msk               (0x1UL << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */\n#define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk\n#define GPIO_LCKR_LCK8_Pos               (8U)\n#define GPIO_LCKR_LCK8_Msk               (0x1UL << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */\n#define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk\n#define GPIO_LCKR_LCK9_Pos               (9U)\n#define GPIO_LCKR_LCK9_Msk               (0x1UL << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */\n#define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk\n#define GPIO_LCKR_LCK10_Pos              (10U)\n#define GPIO_LCKR_LCK10_Msk              (0x1UL << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */\n#define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk\n#define GPIO_LCKR_LCK11_Pos              (11U)\n#define GPIO_LCKR_LCK11_Msk              (0x1UL << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */\n#define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk\n#define GPIO_LCKR_LCK12_Pos              (12U)\n#define GPIO_LCKR_LCK12_Msk              (0x1UL << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */\n#define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk\n#define GPIO_LCKR_LCK13_Pos              (13U)\n#define GPIO_LCKR_LCK13_Msk              (0x1UL << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */\n#define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk\n#define GPIO_LCKR_LCK14_Pos              (14U)\n#define GPIO_LCKR_LCK14_Msk              (0x1UL << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */\n#define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk\n#define GPIO_LCKR_LCK15_Pos              (15U)\n#define GPIO_LCKR_LCK15_Msk              (0x1UL << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */\n#define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk\n#define GPIO_LCKR_LCKK_Pos               (16U)\n#define GPIO_LCKR_LCKK_Msk               (0x1UL << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */\n#define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk\n/****************** Bit definition for GPIO_AFRL register *********************/\n#define GPIO_AFRL_AFSEL0_Pos             (0U)\n#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk\n#define GPIO_AFRL_AFSEL0_0               (0x1UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRL_AFSEL0_1               (0x2UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRL_AFSEL0_2               (0x4UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRL_AFSEL0_3               (0x8UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRL_AFSEL1_Pos             (4U)\n#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk\n#define GPIO_AFRL_AFSEL1_0               (0x1UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRL_AFSEL1_1               (0x2UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRL_AFSEL1_2               (0x4UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRL_AFSEL1_3               (0x8UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRL_AFSEL2_Pos             (8U)\n#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */\n#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk\n#define GPIO_AFRL_AFSEL2_0               (0x1UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */\n#define GPIO_AFRL_AFSEL2_1               (0x2UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */\n#define GPIO_AFRL_AFSEL2_2               (0x4UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */\n#define GPIO_AFRL_AFSEL2_3               (0x8UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */\n#define GPIO_AFRL_AFSEL3_Pos             (12U)\n#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */\n#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk\n#define GPIO_AFRL_AFSEL3_0               (0x1UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */\n#define GPIO_AFRL_AFSEL3_1               (0x2UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */\n#define GPIO_AFRL_AFSEL3_2               (0x4UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */\n#define GPIO_AFRL_AFSEL3_3               (0x8UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */\n#define GPIO_AFRL_AFSEL4_Pos             (16U)\n#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */\n#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk\n#define GPIO_AFRL_AFSEL4_0               (0x1UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */\n#define GPIO_AFRL_AFSEL4_1               (0x2UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */\n#define GPIO_AFRL_AFSEL4_2               (0x4UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */\n#define GPIO_AFRL_AFSEL4_3               (0x8UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */\n#define GPIO_AFRL_AFSEL5_Pos             (20U)\n#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */\n#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk\n#define GPIO_AFRL_AFSEL5_0               (0x1UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */\n#define GPIO_AFRL_AFSEL5_1               (0x2UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */\n#define GPIO_AFRL_AFSEL5_2               (0x4UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */\n#define GPIO_AFRL_AFSEL5_3               (0x8UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */\n#define GPIO_AFRL_AFSEL6_Pos             (24U)\n#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */\n#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk\n#define GPIO_AFRL_AFSEL6_0               (0x1UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */\n#define GPIO_AFRL_AFSEL6_1               (0x2UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */\n#define GPIO_AFRL_AFSEL6_2               (0x4UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */\n#define GPIO_AFRL_AFSEL6_3               (0x8UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */\n#define GPIO_AFRL_AFSEL7_Pos             (28U)\n#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */\n#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk\n#define GPIO_AFRL_AFSEL7_0               (0x1UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */\n#define GPIO_AFRL_AFSEL7_1               (0x2UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */\n#define GPIO_AFRL_AFSEL7_2               (0x4UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */\n#define GPIO_AFRL_AFSEL7_3               (0x8UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFSEL0\n#define GPIO_AFRL_AFRL0_0                GPIO_AFRL_AFSEL0_0\n#define GPIO_AFRL_AFRL0_1                GPIO_AFRL_AFSEL0_1\n#define GPIO_AFRL_AFRL0_2                GPIO_AFRL_AFSEL0_2\n#define GPIO_AFRL_AFRL0_3                GPIO_AFRL_AFSEL0_3\n#define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFSEL1\n#define GPIO_AFRL_AFRL1_0                GPIO_AFRL_AFSEL1_0\n#define GPIO_AFRL_AFRL1_1                GPIO_AFRL_AFSEL1_1\n#define GPIO_AFRL_AFRL1_2                GPIO_AFRL_AFSEL1_2\n#define GPIO_AFRL_AFRL1_3                GPIO_AFRL_AFSEL1_3\n#define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFSEL2\n#define GPIO_AFRL_AFRL2_0                GPIO_AFRL_AFSEL2_0\n#define GPIO_AFRL_AFRL2_1                GPIO_AFRL_AFSEL2_1\n#define GPIO_AFRL_AFRL2_2                GPIO_AFRL_AFSEL2_2\n#define GPIO_AFRL_AFRL2_3                GPIO_AFRL_AFSEL2_3\n#define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFSEL3\n#define GPIO_AFRL_AFRL3_0                GPIO_AFRL_AFSEL3_0\n#define GPIO_AFRL_AFRL3_1                GPIO_AFRL_AFSEL3_1\n#define GPIO_AFRL_AFRL3_2                GPIO_AFRL_AFSEL3_2\n#define GPIO_AFRL_AFRL3_3                GPIO_AFRL_AFSEL3_3\n#define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFSEL4\n#define GPIO_AFRL_AFRL4_0                GPIO_AFRL_AFSEL4_0\n#define GPIO_AFRL_AFRL4_1                GPIO_AFRL_AFSEL4_1\n#define GPIO_AFRL_AFRL4_2                GPIO_AFRL_AFSEL4_2\n#define GPIO_AFRL_AFRL4_3                GPIO_AFRL_AFSEL4_3\n#define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFSEL5\n#define GPIO_AFRL_AFRL5_0                GPIO_AFRL_AFSEL5_0\n#define GPIO_AFRL_AFRL5_1                GPIO_AFRL_AFSEL5_1\n#define GPIO_AFRL_AFRL5_2                GPIO_AFRL_AFSEL5_2\n#define GPIO_AFRL_AFRL5_3                GPIO_AFRL_AFSEL5_3\n#define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFSEL6\n#define GPIO_AFRL_AFRL6_0                GPIO_AFRL_AFSEL6_0\n#define GPIO_AFRL_AFRL6_1                GPIO_AFRL_AFSEL6_1\n#define GPIO_AFRL_AFRL6_2                GPIO_AFRL_AFSEL6_2\n#define GPIO_AFRL_AFRL6_3                GPIO_AFRL_AFSEL6_3\n#define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFSEL7\n#define GPIO_AFRL_AFRL7_0                GPIO_AFRL_AFSEL7_0\n#define GPIO_AFRL_AFRL7_1                GPIO_AFRL_AFSEL7_1\n#define GPIO_AFRL_AFRL7_2                GPIO_AFRL_AFSEL7_2\n#define GPIO_AFRL_AFRL7_3                GPIO_AFRL_AFSEL7_3\n\n/****************** Bit definition for GPIO_AFRH register *********************/\n#define GPIO_AFRH_AFSEL8_Pos             (0U)\n#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk\n#define GPIO_AFRH_AFSEL8_0               (0x1UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRH_AFSEL8_1               (0x2UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRH_AFSEL8_2               (0x4UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRH_AFSEL8_3               (0x8UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRH_AFSEL9_Pos             (4U)\n#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk\n#define GPIO_AFRH_AFSEL9_0               (0x1UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRH_AFSEL9_1               (0x2UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRH_AFSEL9_2               (0x4UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRH_AFSEL9_3               (0x8UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRH_AFSEL10_Pos            (8U)\n#define GPIO_AFRH_AFSEL10_Msk            (0xFUL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */\n#define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk\n#define GPIO_AFRH_AFSEL10_0              (0x1UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */\n#define GPIO_AFRH_AFSEL10_1              (0x2UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */\n#define GPIO_AFRH_AFSEL10_2              (0x4UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */\n#define GPIO_AFRH_AFSEL10_3              (0x8UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */\n#define GPIO_AFRH_AFSEL11_Pos            (12U)\n#define GPIO_AFRH_AFSEL11_Msk            (0xFUL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */\n#define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk\n#define GPIO_AFRH_AFSEL11_0              (0x1UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */\n#define GPIO_AFRH_AFSEL11_1              (0x2UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */\n#define GPIO_AFRH_AFSEL11_2              (0x4UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */\n#define GPIO_AFRH_AFSEL11_3              (0x8UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */\n#define GPIO_AFRH_AFSEL12_Pos            (16U)\n#define GPIO_AFRH_AFSEL12_Msk            (0xFUL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */\n#define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk\n#define GPIO_AFRH_AFSEL12_0              (0x1UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */\n#define GPIO_AFRH_AFSEL12_1              (0x2UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */\n#define GPIO_AFRH_AFSEL12_2              (0x4UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */\n#define GPIO_AFRH_AFSEL12_3              (0x8UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */\n#define GPIO_AFRH_AFSEL13_Pos            (20U)\n#define GPIO_AFRH_AFSEL13_Msk            (0xFUL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */\n#define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk\n#define GPIO_AFRH_AFSEL13_0              (0x1UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */\n#define GPIO_AFRH_AFSEL13_1              (0x2UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */\n#define GPIO_AFRH_AFSEL13_2              (0x4UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */\n#define GPIO_AFRH_AFSEL13_3              (0x8UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */\n#define GPIO_AFRH_AFSEL14_Pos            (24U)\n#define GPIO_AFRH_AFSEL14_Msk            (0xFUL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */\n#define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk\n#define GPIO_AFRH_AFSEL14_0              (0x1UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */\n#define GPIO_AFRH_AFSEL14_1              (0x2UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */\n#define GPIO_AFRH_AFSEL14_2              (0x4UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */\n#define GPIO_AFRH_AFSEL14_3              (0x8UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */\n#define GPIO_AFRH_AFSEL15_Pos            (28U)\n#define GPIO_AFRH_AFSEL15_Msk            (0xFUL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */\n#define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk\n#define GPIO_AFRH_AFSEL15_0              (0x1UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */\n#define GPIO_AFRH_AFSEL15_1              (0x2UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */\n#define GPIO_AFRH_AFSEL15_2              (0x4UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */\n#define GPIO_AFRH_AFSEL15_3              (0x8UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFSEL8\n#define GPIO_AFRH_AFRH0_0                GPIO_AFRH_AFSEL8_0\n#define GPIO_AFRH_AFRH0_1                GPIO_AFRH_AFSEL8_1\n#define GPIO_AFRH_AFRH0_2                GPIO_AFRH_AFSEL8_2\n#define GPIO_AFRH_AFRH0_3                GPIO_AFRH_AFSEL8_3\n#define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFSEL9\n#define GPIO_AFRH_AFRH1_0                GPIO_AFRH_AFSEL9_0\n#define GPIO_AFRH_AFRH1_1                GPIO_AFRH_AFSEL9_1\n#define GPIO_AFRH_AFRH1_2                GPIO_AFRH_AFSEL9_2\n#define GPIO_AFRH_AFRH1_3                GPIO_AFRH_AFSEL9_3\n#define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFSEL10\n#define GPIO_AFRH_AFRH2_0                GPIO_AFRH_AFSEL10_0\n#define GPIO_AFRH_AFRH2_1                GPIO_AFRH_AFSEL10_1\n#define GPIO_AFRH_AFRH2_2                GPIO_AFRH_AFSEL10_2\n#define GPIO_AFRH_AFRH2_3                GPIO_AFRH_AFSEL10_3\n#define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFSEL11\n#define GPIO_AFRH_AFRH3_0                GPIO_AFRH_AFSEL11_0\n#define GPIO_AFRH_AFRH3_1                GPIO_AFRH_AFSEL11_1\n#define GPIO_AFRH_AFRH3_2                GPIO_AFRH_AFSEL11_2\n#define GPIO_AFRH_AFRH3_3                GPIO_AFRH_AFSEL11_3\n#define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFSEL12\n#define GPIO_AFRH_AFRH4_0                GPIO_AFRH_AFSEL12_0\n#define GPIO_AFRH_AFRH4_1                GPIO_AFRH_AFSEL12_1\n#define GPIO_AFRH_AFRH4_2                GPIO_AFRH_AFSEL12_2\n#define GPIO_AFRH_AFRH4_3                GPIO_AFRH_AFSEL12_3\n#define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFSEL13\n#define GPIO_AFRH_AFRH5_0                GPIO_AFRH_AFSEL13_0\n#define GPIO_AFRH_AFRH5_1                GPIO_AFRH_AFSEL13_1\n#define GPIO_AFRH_AFRH5_2                GPIO_AFRH_AFSEL13_2\n#define GPIO_AFRH_AFRH5_3                GPIO_AFRH_AFSEL13_3\n#define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFSEL14\n#define GPIO_AFRH_AFRH6_0                GPIO_AFRH_AFSEL14_0\n#define GPIO_AFRH_AFRH6_1                GPIO_AFRH_AFSEL14_1\n#define GPIO_AFRH_AFRH6_2                GPIO_AFRH_AFSEL14_2\n#define GPIO_AFRH_AFRH6_3                GPIO_AFRH_AFSEL14_3\n#define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFSEL15\n#define GPIO_AFRH_AFRH7_0                GPIO_AFRH_AFSEL15_0\n#define GPIO_AFRH_AFRH7_1                GPIO_AFRH_AFSEL15_1\n#define GPIO_AFRH_AFRH7_2                GPIO_AFRH_AFSEL15_2\n#define GPIO_AFRH_AFRH7_3                GPIO_AFRH_AFSEL15_3\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Inter-integrated Circuit Interface                    */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for I2C_CR1 register  ********************/\n#define I2C_CR1_PE_Pos            (0U)\n#define I2C_CR1_PE_Msk            (0x1UL << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */\n#define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */\n#define I2C_CR1_SMBUS_Pos         (1U)\n#define I2C_CR1_SMBUS_Msk         (0x1UL << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */\n#define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */\n#define I2C_CR1_SMBTYPE_Pos       (3U)\n#define I2C_CR1_SMBTYPE_Msk       (0x1UL << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */\n#define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */\n#define I2C_CR1_ENARP_Pos         (4U)\n#define I2C_CR1_ENARP_Msk         (0x1UL << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */\n#define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */\n#define I2C_CR1_ENPEC_Pos         (5U)\n#define I2C_CR1_ENPEC_Msk         (0x1UL << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */\n#define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */\n#define I2C_CR1_ENGC_Pos          (6U)\n#define I2C_CR1_ENGC_Msk          (0x1UL << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */\n#define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */\n#define I2C_CR1_NOSTRETCH_Pos     (7U)\n#define I2C_CR1_NOSTRETCH_Msk     (0x1UL << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */\n#define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */\n#define I2C_CR1_START_Pos         (8U)\n#define I2C_CR1_START_Msk         (0x1UL << I2C_CR1_START_Pos)                  /*!< 0x00000100 */\n#define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */\n#define I2C_CR1_STOP_Pos          (9U)\n#define I2C_CR1_STOP_Msk          (0x1UL << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */\n#define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */\n#define I2C_CR1_ACK_Pos           (10U)\n#define I2C_CR1_ACK_Msk           (0x1UL << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */\n#define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */\n#define I2C_CR1_POS_Pos           (11U)\n#define I2C_CR1_POS_Msk           (0x1UL << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */\n#define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */\n#define I2C_CR1_PEC_Pos           (12U)\n#define I2C_CR1_PEC_Msk           (0x1UL << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */\n#define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */\n#define I2C_CR1_ALERT_Pos         (13U)\n#define I2C_CR1_ALERT_Msk         (0x1UL << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */\n#define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */\n#define I2C_CR1_SWRST_Pos         (15U)\n#define I2C_CR1_SWRST_Msk         (0x1UL << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */\n#define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */\n\n/*******************  Bit definition for I2C_CR2 register  ********************/\n#define I2C_CR2_FREQ_Pos          (0U)\n#define I2C_CR2_FREQ_Msk          (0x3FUL << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */\n#define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */\n#define I2C_CR2_FREQ_0            (0x01UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */\n#define I2C_CR2_FREQ_1            (0x02UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */\n#define I2C_CR2_FREQ_2            (0x04UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */\n#define I2C_CR2_FREQ_3            (0x08UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */\n#define I2C_CR2_FREQ_4            (0x10UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */\n#define I2C_CR2_FREQ_5            (0x20UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */\n\n#define I2C_CR2_ITERREN_Pos       (8U)\n#define I2C_CR2_ITERREN_Msk       (0x1UL << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */\n#define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */\n#define I2C_CR2_ITEVTEN_Pos       (9U)\n#define I2C_CR2_ITEVTEN_Msk       (0x1UL << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */\n#define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */\n#define I2C_CR2_ITBUFEN_Pos       (10U)\n#define I2C_CR2_ITBUFEN_Msk       (0x1UL << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */\n#define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */\n#define I2C_CR2_DMAEN_Pos         (11U)\n#define I2C_CR2_DMAEN_Msk         (0x1UL << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */\n#define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */\n#define I2C_CR2_LAST_Pos          (12U)\n#define I2C_CR2_LAST_Msk          (0x1UL << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */\n#define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */\n\n/*******************  Bit definition for I2C_OAR1 register  *******************/\n#define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */\n#define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */\n\n#define I2C_OAR1_ADD0_Pos         (0U)\n#define I2C_OAR1_ADD0_Msk         (0x1UL << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */\n#define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */\n#define I2C_OAR1_ADD1_Pos         (1U)\n#define I2C_OAR1_ADD1_Msk         (0x1UL << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */\n#define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */\n#define I2C_OAR1_ADD2_Pos         (2U)\n#define I2C_OAR1_ADD2_Msk         (0x1UL << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */\n#define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */\n#define I2C_OAR1_ADD3_Pos         (3U)\n#define I2C_OAR1_ADD3_Msk         (0x1UL << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */\n#define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */\n#define I2C_OAR1_ADD4_Pos         (4U)\n#define I2C_OAR1_ADD4_Msk         (0x1UL << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */\n#define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */\n#define I2C_OAR1_ADD5_Pos         (5U)\n#define I2C_OAR1_ADD5_Msk         (0x1UL << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */\n#define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */\n#define I2C_OAR1_ADD6_Pos         (6U)\n#define I2C_OAR1_ADD6_Msk         (0x1UL << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */\n#define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */\n#define I2C_OAR1_ADD7_Pos         (7U)\n#define I2C_OAR1_ADD7_Msk         (0x1UL << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */\n#define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */\n#define I2C_OAR1_ADD8_Pos         (8U)\n#define I2C_OAR1_ADD8_Msk         (0x1UL << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */\n#define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */\n#define I2C_OAR1_ADD9_Pos         (9U)\n#define I2C_OAR1_ADD9_Msk         (0x1UL << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */\n#define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */\n\n#define I2C_OAR1_ADDMODE_Pos      (15U)\n#define I2C_OAR1_ADDMODE_Msk      (0x1UL << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */\n#define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */\n\n/*******************  Bit definition for I2C_OAR2 register  *******************/\n#define I2C_OAR2_ENDUAL_Pos       (0U)\n#define I2C_OAR2_ENDUAL_Msk       (0x1UL << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */\n#define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */\n#define I2C_OAR2_ADD2_Pos         (1U)\n#define I2C_OAR2_ADD2_Msk         (0x7FUL << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */\n#define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */\n\n/********************  Bit definition for I2C_DR register  ********************/\n#define I2C_DR_DR_Pos             (0U)\n#define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */\n#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */\n\n/*******************  Bit definition for I2C_SR1 register  ********************/\n#define I2C_SR1_SB_Pos            (0U)\n#define I2C_SR1_SB_Msk            (0x1UL << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */\n#define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */\n#define I2C_SR1_ADDR_Pos          (1U)\n#define I2C_SR1_ADDR_Msk          (0x1UL << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */\n#define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */\n#define I2C_SR1_BTF_Pos           (2U)\n#define I2C_SR1_BTF_Msk           (0x1UL << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */\n#define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */\n#define I2C_SR1_ADD10_Pos         (3U)\n#define I2C_SR1_ADD10_Msk         (0x1UL << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */\n#define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */\n#define I2C_SR1_STOPF_Pos         (4U)\n#define I2C_SR1_STOPF_Msk         (0x1UL << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */\n#define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */\n#define I2C_SR1_RXNE_Pos          (6U)\n#define I2C_SR1_RXNE_Msk          (0x1UL << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */\n#define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */\n#define I2C_SR1_TXE_Pos           (7U)\n#define I2C_SR1_TXE_Msk           (0x1UL << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */\n#define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */\n#define I2C_SR1_BERR_Pos          (8U)\n#define I2C_SR1_BERR_Msk          (0x1UL << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */\n#define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */\n#define I2C_SR1_ARLO_Pos          (9U)\n#define I2C_SR1_ARLO_Msk          (0x1UL << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */\n#define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */\n#define I2C_SR1_AF_Pos            (10U)\n#define I2C_SR1_AF_Msk            (0x1UL << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */\n#define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */\n#define I2C_SR1_OVR_Pos           (11U)\n#define I2C_SR1_OVR_Msk           (0x1UL << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */\n#define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */\n#define I2C_SR1_PECERR_Pos        (12U)\n#define I2C_SR1_PECERR_Msk        (0x1UL << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */\n#define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */\n#define I2C_SR1_TIMEOUT_Pos       (14U)\n#define I2C_SR1_TIMEOUT_Msk       (0x1UL << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */\n#define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */\n#define I2C_SR1_SMBALERT_Pos      (15U)\n#define I2C_SR1_SMBALERT_Msk      (0x1UL << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */\n#define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */\n\n/*******************  Bit definition for I2C_SR2 register  ********************/\n#define I2C_SR2_MSL_Pos           (0U)\n#define I2C_SR2_MSL_Msk           (0x1UL << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */\n#define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */\n#define I2C_SR2_BUSY_Pos          (1U)\n#define I2C_SR2_BUSY_Msk          (0x1UL << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */\n#define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */\n#define I2C_SR2_TRA_Pos           (2U)\n#define I2C_SR2_TRA_Msk           (0x1UL << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */\n#define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */\n#define I2C_SR2_GENCALL_Pos       (4U)\n#define I2C_SR2_GENCALL_Msk       (0x1UL << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */\n#define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */\n#define I2C_SR2_SMBDEFAULT_Pos    (5U)\n#define I2C_SR2_SMBDEFAULT_Msk    (0x1UL << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */\n#define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */\n#define I2C_SR2_SMBHOST_Pos       (6U)\n#define I2C_SR2_SMBHOST_Msk       (0x1UL << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */\n#define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */\n#define I2C_SR2_DUALF_Pos         (7U)\n#define I2C_SR2_DUALF_Msk         (0x1UL << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */\n#define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */\n#define I2C_SR2_PEC_Pos           (8U)\n#define I2C_SR2_PEC_Msk           (0xFFUL << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */\n#define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */\n\n/*******************  Bit definition for I2C_CCR register  ********************/\n#define I2C_CCR_CCR_Pos           (0U)\n#define I2C_CCR_CCR_Msk           (0xFFFUL << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */\n#define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */\n#define I2C_CCR_DUTY_Pos          (14U)\n#define I2C_CCR_DUTY_Msk          (0x1UL << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */\n#define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */\n#define I2C_CCR_FS_Pos            (15U)\n#define I2C_CCR_FS_Msk            (0x1UL << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */\n#define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */\n\n/******************  Bit definition for I2C_TRISE register  *******************/\n#define I2C_TRISE_TRISE_Pos       (0U)\n#define I2C_TRISE_TRISE_Msk       (0x3FUL << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */\n#define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */\n\n/******************  Bit definition for I2C_FLTR register  *******************/\n#define I2C_FLTR_DNF_Pos          (0U)\n#define I2C_FLTR_DNF_Msk          (0xFUL << I2C_FLTR_DNF_Pos)                   /*!< 0x0000000F */\n#define I2C_FLTR_DNF              I2C_FLTR_DNF_Msk                             /*!<Digital Noise Filter */\n#define I2C_FLTR_ANOFF_Pos        (4U)\n#define I2C_FLTR_ANOFF_Msk        (0x1UL << I2C_FLTR_ANOFF_Pos)                 /*!< 0x00000010 */\n#define I2C_FLTR_ANOFF            I2C_FLTR_ANOFF_Msk                           /*!<Analog Noise Filter OFF */\n\n/******************************************************************************/\n/*                                                                            */\n/*        Fast Mode Plus Inter-integrated Circuit Interface (I2C)             */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for I2C_CR1 register  *******************/\n#define FMPI2C_CR1_PE_Pos               (0U)\n#define FMPI2C_CR1_PE_Msk               (0x1UL << FMPI2C_CR1_PE_Pos)            /*!< 0x00000001 */\n#define FMPI2C_CR1_PE                   FMPI2C_CR1_PE_Msk                      /*!< Peripheral enable                   */\n#define FMPI2C_CR1_TXIE_Pos             (1U)\n#define FMPI2C_CR1_TXIE_Msk             (0x1UL << FMPI2C_CR1_TXIE_Pos)          /*!< 0x00000002 */\n#define FMPI2C_CR1_TXIE                 FMPI2C_CR1_TXIE_Msk                    /*!< TX interrupt enable                 */\n#define FMPI2C_CR1_RXIE_Pos             (2U)\n#define FMPI2C_CR1_RXIE_Msk             (0x1UL << FMPI2C_CR1_RXIE_Pos)          /*!< 0x00000004 */\n#define FMPI2C_CR1_RXIE                 FMPI2C_CR1_RXIE_Msk                    /*!< RX interrupt enable                 */\n#define FMPI2C_CR1_ADDRIE_Pos           (3U)\n#define FMPI2C_CR1_ADDRIE_Msk           (0x1UL << FMPI2C_CR1_ADDRIE_Pos)        /*!< 0x00000008 */\n#define FMPI2C_CR1_ADDRIE               FMPI2C_CR1_ADDRIE_Msk                  /*!< Address match interrupt enable      */\n#define FMPI2C_CR1_NACKIE_Pos           (4U)\n#define FMPI2C_CR1_NACKIE_Msk           (0x1UL << FMPI2C_CR1_NACKIE_Pos)        /*!< 0x00000010 */\n#define FMPI2C_CR1_NACKIE               FMPI2C_CR1_NACKIE_Msk                  /*!< NACK received interrupt enable      */\n#define FMPI2C_CR1_STOPIE_Pos           (5U)\n#define FMPI2C_CR1_STOPIE_Msk           (0x1UL << FMPI2C_CR1_STOPIE_Pos)        /*!< 0x00000020 */\n#define FMPI2C_CR1_STOPIE               FMPI2C_CR1_STOPIE_Msk                  /*!< STOP detection interrupt enable     */\n#define FMPI2C_CR1_TCIE_Pos             (6U)\n#define FMPI2C_CR1_TCIE_Msk             (0x1UL << FMPI2C_CR1_TCIE_Pos)          /*!< 0x00000040 */\n#define FMPI2C_CR1_TCIE                 FMPI2C_CR1_TCIE_Msk                    /*!< Transfer complete interrupt enable  */\n#define FMPI2C_CR1_ERRIE_Pos            (7U)\n#define FMPI2C_CR1_ERRIE_Msk            (0x1UL << FMPI2C_CR1_ERRIE_Pos)         /*!< 0x00000080 */\n#define FMPI2C_CR1_ERRIE                FMPI2C_CR1_ERRIE_Msk                   /*!< Errors interrupt enable             */\n#define FMPI2C_CR1_DNF_Pos              (8U)\n#define FMPI2C_CR1_DNF_Msk              (0xFUL << FMPI2C_CR1_DNF_Pos)           /*!< 0x00000F00 */\n#define FMPI2C_CR1_DNF                  FMPI2C_CR1_DNF_Msk                     /*!< Digital noise filter                */\n#define FMPI2C_CR1_ANFOFF_Pos           (12U)\n#define FMPI2C_CR1_ANFOFF_Msk           (0x1UL << FMPI2C_CR1_ANFOFF_Pos)        /*!< 0x00001000 */\n#define FMPI2C_CR1_ANFOFF               FMPI2C_CR1_ANFOFF_Msk                  /*!< Analog noise filter OFF             */\n#define FMPI2C_CR1_TXDMAEN_Pos          (14U)\n#define FMPI2C_CR1_TXDMAEN_Msk          (0x1UL << FMPI2C_CR1_TXDMAEN_Pos)       /*!< 0x00004000 */\n#define FMPI2C_CR1_TXDMAEN              FMPI2C_CR1_TXDMAEN_Msk                 /*!< DMA transmission requests enable    */\n#define FMPI2C_CR1_RXDMAEN_Pos          (15U)\n#define FMPI2C_CR1_RXDMAEN_Msk          (0x1UL << FMPI2C_CR1_RXDMAEN_Pos)       /*!< 0x00008000 */\n#define FMPI2C_CR1_RXDMAEN              FMPI2C_CR1_RXDMAEN_Msk                 /*!< DMA reception requests enable       */\n#define FMPI2C_CR1_SBC_Pos              (16U)\n#define FMPI2C_CR1_SBC_Msk              (0x1UL << FMPI2C_CR1_SBC_Pos)           /*!< 0x00010000 */\n#define FMPI2C_CR1_SBC                  FMPI2C_CR1_SBC_Msk                     /*!< Slave byte control                  */\n#define FMPI2C_CR1_NOSTRETCH_Pos        (17U)\n#define FMPI2C_CR1_NOSTRETCH_Msk        (0x1UL << FMPI2C_CR1_NOSTRETCH_Pos)     /*!< 0x00020000 */\n#define FMPI2C_CR1_NOSTRETCH            FMPI2C_CR1_NOSTRETCH_Msk               /*!< Clock stretching disable            */\n#define FMPI2C_CR1_GCEN_Pos             (19U)\n#define FMPI2C_CR1_GCEN_Msk             (0x1UL << FMPI2C_CR1_GCEN_Pos)          /*!< 0x00080000 */\n#define FMPI2C_CR1_GCEN                 FMPI2C_CR1_GCEN_Msk                    /*!< General call enable                 */\n#define FMPI2C_CR1_SMBHEN_Pos           (20U)\n#define FMPI2C_CR1_SMBHEN_Msk           (0x1UL << FMPI2C_CR1_SMBHEN_Pos)        /*!< 0x00100000 */\n#define FMPI2C_CR1_SMBHEN               FMPI2C_CR1_SMBHEN_Msk                  /*!< SMBus host address enable           */\n#define FMPI2C_CR1_SMBDEN_Pos           (21U)\n#define FMPI2C_CR1_SMBDEN_Msk           (0x1UL << FMPI2C_CR1_SMBDEN_Pos)        /*!< 0x00200000 */\n#define FMPI2C_CR1_SMBDEN               FMPI2C_CR1_SMBDEN_Msk                  /*!< SMBus device default address enable */\n#define FMPI2C_CR1_ALERTEN_Pos          (22U)\n#define FMPI2C_CR1_ALERTEN_Msk          (0x1UL << FMPI2C_CR1_ALERTEN_Pos)       /*!< 0x00400000 */\n#define FMPI2C_CR1_ALERTEN              FMPI2C_CR1_ALERTEN_Msk                 /*!< SMBus alert enable                  */\n#define FMPI2C_CR1_PECEN_Pos            (23U)\n#define FMPI2C_CR1_PECEN_Msk            (0x1UL << FMPI2C_CR1_PECEN_Pos)         /*!< 0x00800000 */\n#define FMPI2C_CR1_PECEN                FMPI2C_CR1_PECEN_Msk                   /*!< PEC enable                          */\n\n/* Legacy Defines */\n#define FMPI2C_CR1_DFN_Pos              FMPI2C_CR1_DNF_Pos\n#define FMPI2C_CR1_DFN_Msk              FMPI2C_CR1_DNF_Msk\n#define FMPI2C_CR1_DFN                  FMPI2C_CR1_DNF\n/******************  Bit definition for I2C_CR2 register  ********************/\n#define FMPI2C_CR2_SADD_Pos             (0U)\n#define FMPI2C_CR2_SADD_Msk             (0x3FFUL << FMPI2C_CR2_SADD_Pos)        /*!< 0x000003FF */\n#define FMPI2C_CR2_SADD                 FMPI2C_CR2_SADD_Msk                    /*!< Slave address (master mode)                             */\n#define FMPI2C_CR2_RD_WRN_Pos           (10U)\n#define FMPI2C_CR2_RD_WRN_Msk           (0x1UL << FMPI2C_CR2_RD_WRN_Pos)        /*!< 0x00000400 */\n#define FMPI2C_CR2_RD_WRN               FMPI2C_CR2_RD_WRN_Msk                  /*!< Transfer direction (master mode)                        */\n#define FMPI2C_CR2_ADD10_Pos            (11U)\n#define FMPI2C_CR2_ADD10_Msk            (0x1UL << FMPI2C_CR2_ADD10_Pos)         /*!< 0x00000800 */\n#define FMPI2C_CR2_ADD10                FMPI2C_CR2_ADD10_Msk                   /*!< 10-bit addressing mode (master mode)                    */\n#define FMPI2C_CR2_HEAD10R_Pos          (12U)\n#define FMPI2C_CR2_HEAD10R_Msk          (0x1UL << FMPI2C_CR2_HEAD10R_Pos)       /*!< 0x00001000 */\n#define FMPI2C_CR2_HEAD10R              FMPI2C_CR2_HEAD10R_Msk                 /*!< 10-bit address header only read direction (master mode) */\n#define FMPI2C_CR2_START_Pos            (13U)\n#define FMPI2C_CR2_START_Msk            (0x1UL << FMPI2C_CR2_START_Pos)         /*!< 0x00002000 */\n#define FMPI2C_CR2_START                FMPI2C_CR2_START_Msk                   /*!< START generation                                        */\n#define FMPI2C_CR2_STOP_Pos             (14U)\n#define FMPI2C_CR2_STOP_Msk             (0x1UL << FMPI2C_CR2_STOP_Pos)          /*!< 0x00004000 */\n#define FMPI2C_CR2_STOP                 FMPI2C_CR2_STOP_Msk                    /*!< STOP generation (master mode)                           */\n#define FMPI2C_CR2_NACK_Pos             (15U)\n#define FMPI2C_CR2_NACK_Msk             (0x1UL << FMPI2C_CR2_NACK_Pos)          /*!< 0x00008000 */\n#define FMPI2C_CR2_NACK                 FMPI2C_CR2_NACK_Msk                    /*!< NACK generation (slave mode)                            */\n#define FMPI2C_CR2_NBYTES_Pos           (16U)\n#define FMPI2C_CR2_NBYTES_Msk           (0xFFUL << FMPI2C_CR2_NBYTES_Pos)       /*!< 0x00FF0000 */\n#define FMPI2C_CR2_NBYTES               FMPI2C_CR2_NBYTES_Msk                  /*!< Number of bytes                                         */\n#define FMPI2C_CR2_RELOAD_Pos           (24U)\n#define FMPI2C_CR2_RELOAD_Msk           (0x1UL << FMPI2C_CR2_RELOAD_Pos)        /*!< 0x01000000 */\n#define FMPI2C_CR2_RELOAD               FMPI2C_CR2_RELOAD_Msk                  /*!< NBYTES reload mode                                      */\n#define FMPI2C_CR2_AUTOEND_Pos          (25U)\n#define FMPI2C_CR2_AUTOEND_Msk          (0x1UL << FMPI2C_CR2_AUTOEND_Pos)       /*!< 0x02000000 */\n#define FMPI2C_CR2_AUTOEND              FMPI2C_CR2_AUTOEND_Msk                 /*!< Automatic end mode (master mode)                        */\n#define FMPI2C_CR2_PECBYTE_Pos          (26U)\n#define FMPI2C_CR2_PECBYTE_Msk          (0x1UL << FMPI2C_CR2_PECBYTE_Pos)       /*!< 0x04000000 */\n#define FMPI2C_CR2_PECBYTE              FMPI2C_CR2_PECBYTE_Msk                 /*!< Packet error checking byte                              */\n\n/*******************  Bit definition for I2C_OAR1 register  ******************/\n#define FMPI2C_OAR1_OA1_Pos             (0U)\n#define FMPI2C_OAR1_OA1_Msk             (0x3FFUL << FMPI2C_OAR1_OA1_Pos)        /*!< 0x000003FF */\n#define FMPI2C_OAR1_OA1                 FMPI2C_OAR1_OA1_Msk                    /*!< Interface own address 1   */\n#define FMPI2C_OAR1_OA1MODE_Pos         (10U)\n#define FMPI2C_OAR1_OA1MODE_Msk         (0x1UL << FMPI2C_OAR1_OA1MODE_Pos)      /*!< 0x00000400 */\n#define FMPI2C_OAR1_OA1MODE             FMPI2C_OAR1_OA1MODE_Msk                /*!< Own address 1 10-bit mode */\n#define FMPI2C_OAR1_OA1EN_Pos           (15U)\n#define FMPI2C_OAR1_OA1EN_Msk           (0x1UL << FMPI2C_OAR1_OA1EN_Pos)        /*!< 0x00008000 */\n#define FMPI2C_OAR1_OA1EN               FMPI2C_OAR1_OA1EN_Msk                  /*!< Own address 1 enable      */\n\n/*******************  Bit definition for I2C_OAR2 register  ******************/\n#define FMPI2C_OAR2_OA2_Pos             (1U)\n#define FMPI2C_OAR2_OA2_Msk             (0x7FUL << FMPI2C_OAR2_OA2_Pos)         /*!< 0x000000FE */\n#define FMPI2C_OAR2_OA2                 FMPI2C_OAR2_OA2_Msk                    /*!< Interface own address 2 */\n#define FMPI2C_OAR2_OA2MSK_Pos          (8U)\n#define FMPI2C_OAR2_OA2MSK_Msk          (0x7UL << FMPI2C_OAR2_OA2MSK_Pos)       /*!< 0x00000700 */\n#define FMPI2C_OAR2_OA2MSK              FMPI2C_OAR2_OA2MSK_Msk                 /*!< Own address 2 masks     */\n#define FMPI2C_OAR2_OA2EN_Pos           (15U)\n#define FMPI2C_OAR2_OA2EN_Msk           (0x1UL << FMPI2C_OAR2_OA2EN_Pos)        /*!< 0x00008000 */\n#define FMPI2C_OAR2_OA2EN               FMPI2C_OAR2_OA2EN_Msk                  /*!< Own address 2 enable    */\n\n/*******************  Bit definition for I2C_TIMINGR register *******************/\n#define FMPI2C_TIMINGR_SCLL_Pos         (0U)\n#define FMPI2C_TIMINGR_SCLL_Msk         (0xFFUL << FMPI2C_TIMINGR_SCLL_Pos)     /*!< 0x000000FF */\n#define FMPI2C_TIMINGR_SCLL             FMPI2C_TIMINGR_SCLL_Msk                /*!< SCL low period (master mode)  */\n#define FMPI2C_TIMINGR_SCLH_Pos         (8U)\n#define FMPI2C_TIMINGR_SCLH_Msk         (0xFFUL << FMPI2C_TIMINGR_SCLH_Pos)     /*!< 0x0000FF00 */\n#define FMPI2C_TIMINGR_SCLH             FMPI2C_TIMINGR_SCLH_Msk                /*!< SCL high period (master mode) */\n#define FMPI2C_TIMINGR_SDADEL_Pos       (16U)\n#define FMPI2C_TIMINGR_SDADEL_Msk       (0xFUL << FMPI2C_TIMINGR_SDADEL_Pos)    /*!< 0x000F0000 */\n#define FMPI2C_TIMINGR_SDADEL           FMPI2C_TIMINGR_SDADEL_Msk              /*!< Data hold time                */\n#define FMPI2C_TIMINGR_SCLDEL_Pos       (20U)\n#define FMPI2C_TIMINGR_SCLDEL_Msk       (0xFUL << FMPI2C_TIMINGR_SCLDEL_Pos)    /*!< 0x00F00000 */\n#define FMPI2C_TIMINGR_SCLDEL           FMPI2C_TIMINGR_SCLDEL_Msk              /*!< Data setup time               */\n#define FMPI2C_TIMINGR_PRESC_Pos        (28U)\n#define FMPI2C_TIMINGR_PRESC_Msk        (0xFUL << FMPI2C_TIMINGR_PRESC_Pos)     /*!< 0xF0000000 */\n#define FMPI2C_TIMINGR_PRESC            FMPI2C_TIMINGR_PRESC_Msk               /*!< Timings prescaler             */\n\n/******************* Bit definition for I2C_TIMEOUTR register *******************/\n#define FMPI2C_TIMEOUTR_TIMEOUTA_Pos    (0U)\n#define FMPI2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */\n#define FMPI2C_TIMEOUTR_TIMEOUTA        FMPI2C_TIMEOUTR_TIMEOUTA_Msk           /*!< Bus timeout A                 */\n#define FMPI2C_TIMEOUTR_TIDLE_Pos       (12U)\n#define FMPI2C_TIMEOUTR_TIDLE_Msk       (0x1UL << FMPI2C_TIMEOUTR_TIDLE_Pos)    /*!< 0x00001000 */\n#define FMPI2C_TIMEOUTR_TIDLE           FMPI2C_TIMEOUTR_TIDLE_Msk              /*!< Idle clock timeout detection  */\n#define FMPI2C_TIMEOUTR_TIMOUTEN_Pos    (15U)\n#define FMPI2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */\n#define FMPI2C_TIMEOUTR_TIMOUTEN        FMPI2C_TIMEOUTR_TIMOUTEN_Msk           /*!< Clock timeout enable          */\n#define FMPI2C_TIMEOUTR_TIMEOUTB_Pos    (16U)\n#define FMPI2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */\n#define FMPI2C_TIMEOUTR_TIMEOUTB        FMPI2C_TIMEOUTR_TIMEOUTB_Msk           /*!< Bus timeout B                 */\n#define FMPI2C_TIMEOUTR_TEXTEN_Pos      (31U)\n#define FMPI2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << FMPI2C_TIMEOUTR_TEXTEN_Pos)   /*!< 0x80000000 */\n#define FMPI2C_TIMEOUTR_TEXTEN          FMPI2C_TIMEOUTR_TEXTEN_Msk             /*!< Extended clock timeout enable */\n\n/******************  Bit definition for I2C_ISR register  *********************/\n#define FMPI2C_ISR_TXE_Pos              (0U)\n#define FMPI2C_ISR_TXE_Msk              (0x1UL << FMPI2C_ISR_TXE_Pos)           /*!< 0x00000001 */\n#define FMPI2C_ISR_TXE                  FMPI2C_ISR_TXE_Msk                     /*!< Transmit data register empty     */\n#define FMPI2C_ISR_TXIS_Pos             (1U)\n#define FMPI2C_ISR_TXIS_Msk             (0x1UL << FMPI2C_ISR_TXIS_Pos)          /*!< 0x00000002 */\n#define FMPI2C_ISR_TXIS                 FMPI2C_ISR_TXIS_Msk                    /*!< Transmit interrupt status        */\n#define FMPI2C_ISR_RXNE_Pos             (2U)\n#define FMPI2C_ISR_RXNE_Msk             (0x1UL << FMPI2C_ISR_RXNE_Pos)          /*!< 0x00000004 */\n#define FMPI2C_ISR_RXNE                 FMPI2C_ISR_RXNE_Msk                    /*!< Receive data register not empty  */\n#define FMPI2C_ISR_ADDR_Pos             (3U)\n#define FMPI2C_ISR_ADDR_Msk             (0x1UL << FMPI2C_ISR_ADDR_Pos)          /*!< 0x00000008 */\n#define FMPI2C_ISR_ADDR                 FMPI2C_ISR_ADDR_Msk                    /*!< Address matched (slave mode)     */\n#define FMPI2C_ISR_NACKF_Pos            (4U)\n#define FMPI2C_ISR_NACKF_Msk            (0x1UL << FMPI2C_ISR_NACKF_Pos)         /*!< 0x00000010 */\n#define FMPI2C_ISR_NACKF                FMPI2C_ISR_NACKF_Msk                   /*!< NACK received flag               */\n#define FMPI2C_ISR_STOPF_Pos            (5U)\n#define FMPI2C_ISR_STOPF_Msk            (0x1UL << FMPI2C_ISR_STOPF_Pos)         /*!< 0x00000020 */\n#define FMPI2C_ISR_STOPF                FMPI2C_ISR_STOPF_Msk                   /*!< STOP detection flag              */\n#define FMPI2C_ISR_TC_Pos               (6U)\n#define FMPI2C_ISR_TC_Msk               (0x1UL << FMPI2C_ISR_TC_Pos)            /*!< 0x00000040 */\n#define FMPI2C_ISR_TC                   FMPI2C_ISR_TC_Msk                      /*!< Transfer complete (master mode)  */\n#define FMPI2C_ISR_TCR_Pos              (7U)\n#define FMPI2C_ISR_TCR_Msk              (0x1UL << FMPI2C_ISR_TCR_Pos)           /*!< 0x00000080 */\n#define FMPI2C_ISR_TCR                  FMPI2C_ISR_TCR_Msk                     /*!< Transfer complete reload         */\n#define FMPI2C_ISR_BERR_Pos             (8U)\n#define FMPI2C_ISR_BERR_Msk             (0x1UL << FMPI2C_ISR_BERR_Pos)          /*!< 0x00000100 */\n#define FMPI2C_ISR_BERR                 FMPI2C_ISR_BERR_Msk                    /*!< Bus error                        */\n#define FMPI2C_ISR_ARLO_Pos             (9U)\n#define FMPI2C_ISR_ARLO_Msk             (0x1UL << FMPI2C_ISR_ARLO_Pos)          /*!< 0x00000200 */\n#define FMPI2C_ISR_ARLO                 FMPI2C_ISR_ARLO_Msk                    /*!< Arbitration lost                 */\n#define FMPI2C_ISR_OVR_Pos              (10U)\n#define FMPI2C_ISR_OVR_Msk              (0x1UL << FMPI2C_ISR_OVR_Pos)           /*!< 0x00000400 */\n#define FMPI2C_ISR_OVR                  FMPI2C_ISR_OVR_Msk                     /*!< Overrun/Underrun                 */\n#define FMPI2C_ISR_PECERR_Pos           (11U)\n#define FMPI2C_ISR_PECERR_Msk           (0x1UL << FMPI2C_ISR_PECERR_Pos)        /*!< 0x00000800 */\n#define FMPI2C_ISR_PECERR               FMPI2C_ISR_PECERR_Msk                  /*!< PEC error in reception           */\n#define FMPI2C_ISR_TIMEOUT_Pos          (12U)\n#define FMPI2C_ISR_TIMEOUT_Msk          (0x1UL << FMPI2C_ISR_TIMEOUT_Pos)       /*!< 0x00001000 */\n#define FMPI2C_ISR_TIMEOUT              FMPI2C_ISR_TIMEOUT_Msk                 /*!< Timeout or Tlow detection flag   */\n#define FMPI2C_ISR_ALERT_Pos            (13U)\n#define FMPI2C_ISR_ALERT_Msk            (0x1UL << FMPI2C_ISR_ALERT_Pos)         /*!< 0x00002000 */\n#define FMPI2C_ISR_ALERT                FMPI2C_ISR_ALERT_Msk                   /*!< SMBus alert                      */\n#define FMPI2C_ISR_BUSY_Pos             (15U)\n#define FMPI2C_ISR_BUSY_Msk             (0x1UL << FMPI2C_ISR_BUSY_Pos)          /*!< 0x00008000 */\n#define FMPI2C_ISR_BUSY                 FMPI2C_ISR_BUSY_Msk                    /*!< Bus busy                         */\n#define FMPI2C_ISR_DIR_Pos              (16U)\n#define FMPI2C_ISR_DIR_Msk              (0x1UL << FMPI2C_ISR_DIR_Pos)           /*!< 0x00010000 */\n#define FMPI2C_ISR_DIR                  FMPI2C_ISR_DIR_Msk                     /*!< Transfer direction (slave mode)  */\n#define FMPI2C_ISR_ADDCODE_Pos          (17U)\n#define FMPI2C_ISR_ADDCODE_Msk          (0x7FUL << FMPI2C_ISR_ADDCODE_Pos)      /*!< 0x00FE0000 */\n#define FMPI2C_ISR_ADDCODE              FMPI2C_ISR_ADDCODE_Msk                 /*!< Address match code (slave mode)  */\n\n/******************  Bit definition for I2C_ICR register  *********************/\n#define FMPI2C_ICR_ADDRCF_Pos           (3U)\n#define FMPI2C_ICR_ADDRCF_Msk           (0x1UL << FMPI2C_ICR_ADDRCF_Pos)        /*!< 0x00000008 */\n#define FMPI2C_ICR_ADDRCF               FMPI2C_ICR_ADDRCF_Msk                  /*!< Address matched clear flag  */\n#define FMPI2C_ICR_NACKCF_Pos           (4U)\n#define FMPI2C_ICR_NACKCF_Msk           (0x1UL << FMPI2C_ICR_NACKCF_Pos)        /*!< 0x00000010 */\n#define FMPI2C_ICR_NACKCF               FMPI2C_ICR_NACKCF_Msk                  /*!< NACK clear flag             */\n#define FMPI2C_ICR_STOPCF_Pos           (5U)\n#define FMPI2C_ICR_STOPCF_Msk           (0x1UL << FMPI2C_ICR_STOPCF_Pos)        /*!< 0x00000020 */\n#define FMPI2C_ICR_STOPCF               FMPI2C_ICR_STOPCF_Msk                  /*!< STOP detection clear flag   */\n#define FMPI2C_ICR_BERRCF_Pos           (8U)\n#define FMPI2C_ICR_BERRCF_Msk           (0x1UL << FMPI2C_ICR_BERRCF_Pos)        /*!< 0x00000100 */\n#define FMPI2C_ICR_BERRCF               FMPI2C_ICR_BERRCF_Msk                  /*!< Bus error clear flag        */\n#define FMPI2C_ICR_ARLOCF_Pos           (9U)\n#define FMPI2C_ICR_ARLOCF_Msk           (0x1UL << FMPI2C_ICR_ARLOCF_Pos)        /*!< 0x00000200 */\n#define FMPI2C_ICR_ARLOCF               FMPI2C_ICR_ARLOCF_Msk                  /*!< Arbitration lost clear flag */\n#define FMPI2C_ICR_OVRCF_Pos            (10U)\n#define FMPI2C_ICR_OVRCF_Msk            (0x1UL << FMPI2C_ICR_OVRCF_Pos)         /*!< 0x00000400 */\n#define FMPI2C_ICR_OVRCF                FMPI2C_ICR_OVRCF_Msk                   /*!< Overrun/Underrun clear flag */\n#define FMPI2C_ICR_PECCF_Pos            (11U)\n#define FMPI2C_ICR_PECCF_Msk            (0x1UL << FMPI2C_ICR_PECCF_Pos)         /*!< 0x00000800 */\n#define FMPI2C_ICR_PECCF                FMPI2C_ICR_PECCF_Msk                   /*!< PAC error clear flag        */\n#define FMPI2C_ICR_TIMOUTCF_Pos         (12U)\n#define FMPI2C_ICR_TIMOUTCF_Msk         (0x1UL << FMPI2C_ICR_TIMOUTCF_Pos)      /*!< 0x00001000 */\n#define FMPI2C_ICR_TIMOUTCF             FMPI2C_ICR_TIMOUTCF_Msk                /*!< Timeout clear flag          */\n#define FMPI2C_ICR_ALERTCF_Pos          (13U)\n#define FMPI2C_ICR_ALERTCF_Msk          (0x1UL << FMPI2C_ICR_ALERTCF_Pos)       /*!< 0x00002000 */\n#define FMPI2C_ICR_ALERTCF              FMPI2C_ICR_ALERTCF_Msk                 /*!< Alert clear flag            */\n\n/******************  Bit definition for I2C_PECR register  *********************/\n#define FMPI2C_PECR_PEC_Pos             (0U)\n#define FMPI2C_PECR_PEC_Msk             (0xFFUL << FMPI2C_PECR_PEC_Pos)         /*!< 0x000000FF */\n#define FMPI2C_PECR_PEC                 FMPI2C_PECR_PEC_Msk                    /*!< PEC register */\n\n/******************  Bit definition for I2C_RXDR register  *********************/\n#define FMPI2C_RXDR_RXDATA_Pos          (0U)\n#define FMPI2C_RXDR_RXDATA_Msk          (0xFFUL << FMPI2C_RXDR_RXDATA_Pos)      /*!< 0x000000FF */\n#define FMPI2C_RXDR_RXDATA              FMPI2C_RXDR_RXDATA_Msk                 /*!< 8-bit receive data */\n\n/******************  Bit definition for I2C_TXDR register  *********************/\n#define FMPI2C_TXDR_TXDATA_Pos          (0U)\n#define FMPI2C_TXDR_TXDATA_Msk          (0xFFUL << FMPI2C_TXDR_TXDATA_Pos)      /*!< 0x000000FF */\n#define FMPI2C_TXDR_TXDATA              FMPI2C_TXDR_TXDATA_Msk                 /*!< 8-bit transmit data */\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Independent WATCHDOG                             */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define IWDG_KR_KEY_Pos     (0U)\n#define IWDG_KR_KEY_Msk     (0xFFFFUL << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */\n#define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */\n\n/*******************  Bit definition for IWDG_PR register  ********************/\n#define IWDG_PR_PR_Pos      (0U)\n#define IWDG_PR_PR_Msk      (0x7UL << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */\n#define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */\n#define IWDG_PR_PR_0        (0x1UL << IWDG_PR_PR_Pos)                           /*!< 0x01 */\n#define IWDG_PR_PR_1        (0x2UL << IWDG_PR_PR_Pos)                           /*!< 0x02 */\n#define IWDG_PR_PR_2        (0x4UL << IWDG_PR_PR_Pos)                           /*!< 0x04 */\n\n/*******************  Bit definition for IWDG_RLR register  *******************/\n#define IWDG_RLR_RL_Pos     (0U)\n#define IWDG_RLR_RL_Msk     (0xFFFUL << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */\n#define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */\n\n/*******************  Bit definition for IWDG_SR register  ********************/\n#define IWDG_SR_PVU_Pos     (0U)\n#define IWDG_SR_PVU_Msk     (0x1UL << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */\n#define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */\n#define IWDG_SR_RVU_Pos     (1U)\n#define IWDG_SR_RVU_Msk     (0x1UL << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */\n#define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                             Power Control                                  */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for PWR_CR register  ********************/\n#define PWR_CR_LPDS_Pos        (0U)\n#define PWR_CR_LPDS_Msk        (0x1UL << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */\n#define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */\n#define PWR_CR_PDDS_Pos        (1U)\n#define PWR_CR_PDDS_Msk        (0x1UL << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */\n#define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */\n#define PWR_CR_CWUF_Pos        (2U)\n#define PWR_CR_CWUF_Msk        (0x1UL << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */\n#define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */\n#define PWR_CR_CSBF_Pos        (3U)\n#define PWR_CR_CSBF_Msk        (0x1UL << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */\n#define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */\n#define PWR_CR_PVDE_Pos        (4U)\n#define PWR_CR_PVDE_Msk        (0x1UL << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */\n#define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */\n\n#define PWR_CR_PLS_Pos         (5U)\n#define PWR_CR_PLS_Msk         (0x7UL << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */\n#define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */\n#define PWR_CR_PLS_0           (0x1UL << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */\n#define PWR_CR_PLS_1           (0x2UL << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */\n#define PWR_CR_PLS_2           (0x4UL << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */\n\n/*!< PVD level configuration */\n#define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */\n#define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */\n#define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */\n#define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */\n#define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */\n#define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */\n#define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */\n#define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */\n#define PWR_CR_DBP_Pos         (8U)\n#define PWR_CR_DBP_Msk         (0x1UL << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */\n#define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */\n#define PWR_CR_FPDS_Pos        (9U)\n#define PWR_CR_FPDS_Msk        (0x1UL << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */\n#define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */\n#define PWR_CR_LPLVDS_Pos      (10U)\n#define PWR_CR_LPLVDS_Msk      (0x1UL << PWR_CR_LPLVDS_Pos)                     /*!< 0x00000400 */\n#define PWR_CR_LPLVDS          PWR_CR_LPLVDS_Msk                               /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */\n#define PWR_CR_MRLVDS_Pos      (11U)\n#define PWR_CR_MRLVDS_Msk      (0x1UL << PWR_CR_MRLVDS_Pos)                     /*!< 0x00000800 */\n#define PWR_CR_MRLVDS          PWR_CR_MRLVDS_Msk                               /*!< Main regulator Low Voltage Scaling in Stop mode            */\n#define PWR_CR_ADCDC1_Pos      (13U)\n#define PWR_CR_ADCDC1_Msk      (0x1UL << PWR_CR_ADCDC1_Pos)                     /*!< 0x00002000 */\n#define PWR_CR_ADCDC1          PWR_CR_ADCDC1_Msk                               /*!< Refer to AN4073 on how to use this bit                     */\n#define PWR_CR_VOS_Pos         (14U)\n#define PWR_CR_VOS_Msk         (0x3UL << PWR_CR_VOS_Pos)                        /*!< 0x0000C000 */\n#define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\n#define PWR_CR_VOS_0           0x00004000U                                     /*!< Bit 0 */\n#define PWR_CR_VOS_1           0x00008000U                                     /*!< Bit 1 */\n#define PWR_CR_ODEN_Pos        (16U)\n#define PWR_CR_ODEN_Msk        (0x1UL << PWR_CR_ODEN_Pos)                       /*!< 0x00010000 */\n#define PWR_CR_ODEN            PWR_CR_ODEN_Msk                                 /*!< Over Drive enable                   */\n#define PWR_CR_ODSWEN_Pos      (17U)\n#define PWR_CR_ODSWEN_Msk      (0x1UL << PWR_CR_ODSWEN_Pos)                     /*!< 0x00020000 */\n#define PWR_CR_ODSWEN          PWR_CR_ODSWEN_Msk                               /*!< Over Drive switch enabled           */\n#define PWR_CR_UDEN_Pos        (18U)\n#define PWR_CR_UDEN_Msk        (0x3UL << PWR_CR_UDEN_Pos)                       /*!< 0x000C0000 */\n#define PWR_CR_UDEN            PWR_CR_UDEN_Msk                                 /*!< Under Drive enable in stop mode     */\n#define PWR_CR_UDEN_0          (0x1UL << PWR_CR_UDEN_Pos)                       /*!< 0x00040000 */\n#define PWR_CR_UDEN_1          (0x2UL << PWR_CR_UDEN_Pos)                       /*!< 0x00080000 */\n#define PWR_CR_FMSSR_Pos       (20U)\n#define PWR_CR_FMSSR_Msk       (0x1UL << PWR_CR_FMSSR_Pos)                      /*!< 0x00100000 */\n#define PWR_CR_FMSSR           PWR_CR_FMSSR_Msk                                /*!< Flash Memory Sleep System Run        */\n#define PWR_CR_FISSR_Pos       (21U)\n#define PWR_CR_FISSR_Msk       (0x1UL << PWR_CR_FISSR_Pos)                      /*!< 0x00200000 */\n#define PWR_CR_FISSR           PWR_CR_FISSR_Msk                                /*!< Flash Interface Stop while System Run */\n\n/* Legacy define */\n#define  PWR_CR_PMODE                        PWR_CR_VOS\n#define  PWR_CR_LPUDS                        PWR_CR_LPLVDS     /*!< Low-Power Regulator in deepsleep under-drive mode        */\n#define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode             */\n\n/*******************  Bit definition for PWR_CSR register  ********************/\n#define PWR_CSR_WUF_Pos        (0U)\n#define PWR_CSR_WUF_Msk        (0x1UL << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */\n#define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */\n#define PWR_CSR_SBF_Pos        (1U)\n#define PWR_CSR_SBF_Msk        (0x1UL << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */\n#define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */\n#define PWR_CSR_PVDO_Pos       (2U)\n#define PWR_CSR_PVDO_Msk       (0x1UL << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */\n#define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */\n#define PWR_CSR_BRR_Pos        (3U)\n#define PWR_CSR_BRR_Msk        (0x1UL << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */\n#define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */\n#define PWR_CSR_EWUP2_Pos      (7U)\n#define PWR_CSR_EWUP2_Msk      (0x1UL << PWR_CSR_EWUP2_Pos)                     /*!< 0x00000080 */\n#define PWR_CSR_EWUP2          PWR_CSR_EWUP2_Msk                               /*!< Enable WKUP pin 2                                */\n#define PWR_CSR_EWUP1_Pos      (8U)\n#define PWR_CSR_EWUP1_Msk      (0x1UL << PWR_CSR_EWUP1_Pos)                     /*!< 0x00000100 */\n#define PWR_CSR_EWUP1          PWR_CSR_EWUP1_Msk                               /*!< Enable WKUP pin 1                                */\n#define PWR_CSR_BRE_Pos        (9U)\n#define PWR_CSR_BRE_Msk        (0x1UL << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */\n#define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */\n#define PWR_CSR_VOSRDY_Pos     (14U)\n#define PWR_CSR_VOSRDY_Msk     (0x1UL << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */\n#define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */\n#define PWR_CSR_ODRDY_Pos      (16U)\n#define PWR_CSR_ODRDY_Msk      (0x1UL << PWR_CSR_ODRDY_Pos)                     /*!< 0x00010000 */\n#define PWR_CSR_ODRDY          PWR_CSR_ODRDY_Msk                               /*!< Over Drive generator ready                       */\n#define PWR_CSR_ODSWRDY_Pos    (17U)\n#define PWR_CSR_ODSWRDY_Msk    (0x1UL << PWR_CSR_ODSWRDY_Pos)                   /*!< 0x00020000 */\n#define PWR_CSR_ODSWRDY        PWR_CSR_ODSWRDY_Msk                             /*!< Over Drive Switch ready                          */\n#define PWR_CSR_UDRDY_Pos      (18U)\n#define PWR_CSR_UDRDY_Msk      (0x3UL << PWR_CSR_UDRDY_Pos)                     /*!< 0x000C0000 */\n#define PWR_CSR_UDRDY          PWR_CSR_UDRDY_Msk                               /*!< Under Drive ready                                */\n/* Legacy define */\n#define  PWR_CSR_UDSWRDY                     PWR_CSR_UDRDY\n\n/* Legacy define */\n#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    QUADSPI                                 */\n/*                                                                            */\n/******************************************************************************/\n/*****************  Bit definition for QUADSPI_CR register  *******************/\n#define QUADSPI_CR_EN_Pos                (0U)\n#define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)           /*!< 0x00000001 */\n#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable                             */\n#define QUADSPI_CR_ABORT_Pos             (1U)\n#define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)        /*!< 0x00000002 */\n#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request                      */\n#define QUADSPI_CR_DMAEN_Pos             (2U)\n#define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)        /*!< 0x00000004 */\n#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable                         */\n#define QUADSPI_CR_TCEN_Pos              (3U)\n#define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)         /*!< 0x00000008 */\n#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable             */\n#define QUADSPI_CR_SSHIFT_Pos            (4U)\n#define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)       /*!< 0x00000010 */\n#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift                */\n#define QUADSPI_CR_DFM_Pos               (6U)\n#define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)          /*!< 0x00000040 */\n#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode                    */\n#define QUADSPI_CR_FSEL_Pos              (7U)\n#define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)         /*!< 0x00000080 */\n#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select                       */\n#define QUADSPI_CR_FTHRES_Pos            (8U)\n#define QUADSPI_CR_FTHRES_Msk            (0x1FUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */\n#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level             */\n#define QUADSPI_CR_FTHRES_0              (0x01UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */\n#define QUADSPI_CR_FTHRES_1              (0x02UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */\n#define QUADSPI_CR_FTHRES_2              (0x04UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */\n#define QUADSPI_CR_FTHRES_3              (0x08UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */\n#define QUADSPI_CR_FTHRES_4              (0x10UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001000 */\n#define QUADSPI_CR_TEIE_Pos              (16U)\n#define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)         /*!< 0x00010000 */\n#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable    */\n#define QUADSPI_CR_TCIE_Pos              (17U)\n#define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)         /*!< 0x00020000 */\n#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */\n#define QUADSPI_CR_FTIE_Pos              (18U)\n#define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)         /*!< 0x00040000 */\n#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable    */\n#define QUADSPI_CR_SMIE_Pos              (19U)\n#define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)         /*!< 0x00080000 */\n#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable      */\n#define QUADSPI_CR_TOIE_Pos              (20U)\n#define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)         /*!< 0x00100000 */\n#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable           */\n#define QUADSPI_CR_APMS_Pos              (22U)\n#define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)         /*!< 0x00400000 */\n#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1                              */\n#define QUADSPI_CR_PMM_Pos               (23U)\n#define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)          /*!< 0x00800000 */\n#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode                 */\n#define QUADSPI_CR_PRESCALER_Pos         (24U)\n#define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0xFF000000 */\n#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler     */\n#define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x01000000 */\n#define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x02000000 */\n#define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x04000000 */\n#define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x08000000 */\n#define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x10000000 */\n#define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x20000000 */\n#define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x40000000 */\n#define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x80000000 */\n\n/*****************  Bit definition for QUADSPI_DCR register  ******************/\n#define QUADSPI_DCR_CKMODE_Pos           (0U)\n#define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)      /*!< 0x00000001 */\n#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3                 */\n#define QUADSPI_DCR_CSHT_Pos             (8U)\n#define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000700 */\n#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */\n#define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000100 */\n#define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000200 */\n#define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000400 */\n#define QUADSPI_DCR_FSIZE_Pos            (16U)\n#define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x001F0000 */\n#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size          */\n#define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00010000 */\n#define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00020000 */\n#define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00040000 */\n#define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00080000 */\n#define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00100000 */\n\n/******************  Bit definition for QUADSPI_SR register  *******************/\n#define QUADSPI_SR_TEF_Pos               (0U)\n#define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)          /*!< 0x00000001 */\n#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag    */\n#define QUADSPI_SR_TCF_Pos               (1U)\n#define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)          /*!< 0x00000002 */\n#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */\n#define QUADSPI_SR_FTF_Pos               (2U)\n#define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)          /*!< 0x00000004 */\n#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag    */\n#define QUADSPI_SR_SMF_Pos               (3U)\n#define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)          /*!< 0x00000008 */\n#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag      */\n#define QUADSPI_SR_TOF_Pos               (4U)\n#define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)          /*!< 0x00000010 */\n#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag           */\n#define QUADSPI_SR_BUSY_Pos              (5U)\n#define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)         /*!< 0x00000020 */\n#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy                   */\n#define QUADSPI_SR_FLEVEL_Pos            (8U)\n#define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00003F00 */\n#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag    */\n#define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000100 */\n#define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000200 */\n#define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000400 */\n#define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000800 */\n#define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00001000 */\n#define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00002000 */\n\n/******************  Bit definition for QUADSPI_FCR register  ******************/\n#define QUADSPI_FCR_CTEF_Pos             (0U)\n#define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)        /*!< 0x00000001 */\n#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag    */\n#define QUADSPI_FCR_CTCF_Pos             (1U)\n#define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)        /*!< 0x00000002 */\n#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */\n#define QUADSPI_FCR_CSMF_Pos             (3U)\n#define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)        /*!< 0x00000008 */\n#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag      */\n#define QUADSPI_FCR_CTOF_Pos             (4U)\n#define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)        /*!< 0x00000010 */\n#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag           */\n\n/******************  Bit definition for QUADSPI_DLR register  ******************/\n#define QUADSPI_DLR_DL_Pos               (0U)\n#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)   /*!< 0xFFFFFFFF */\n#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */\n\n/******************  Bit definition for QUADSPI_CCR register  ******************/\n#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)\n#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */\n#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk           /*!< INSTRUCTION[7:0]: Instruction         */\n#define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */\n#define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */\n#define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */\n#define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */\n#define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */\n#define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */\n#define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */\n#define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */\n#define QUADSPI_CCR_IMODE_Pos            (8U)\n#define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000300 */\n#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                 /*!< IMODE[1:0]: Instruction Mode          */\n#define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000100 */\n#define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000200 */\n#define QUADSPI_CCR_ADMODE_Pos           (10U)\n#define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000C00 */\n#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                /*!< ADMODE[1:0]: Address Mode             */\n#define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000400 */\n#define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000800 */\n#define QUADSPI_CCR_ADSIZE_Pos           (12U)\n#define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00003000 */\n#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                /*!< ADSIZE[1:0]: Address Size             */\n#define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00001000 */\n#define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00002000 */\n#define QUADSPI_CCR_ABMODE_Pos           (14U)\n#define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x0000C000 */\n#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                /*!< ABMODE[1:0]: Alternate Bytes Mode     */\n#define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00004000 */\n#define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00008000 */\n#define QUADSPI_CCR_ABSIZE_Pos           (16U)\n#define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00030000 */\n#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                /*!< ABSIZE[1:0]: Instruction Mode         */\n#define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00010000 */\n#define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00020000 */\n#define QUADSPI_CCR_DCYC_Pos             (18U)\n#define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x007C0000 */\n#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                  /*!< DCYC[4:0]: Dummy Cycles               */\n#define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00040000 */\n#define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00080000 */\n#define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00100000 */\n#define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00200000 */\n#define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00400000 */\n#define QUADSPI_CCR_DMODE_Pos            (24U)\n#define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x03000000 */\n#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                 /*!< DMODE[1:0]: Data Mode                 */\n#define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x01000000 */\n#define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)       /*!< 0x02000000 */\n#define QUADSPI_CCR_FMODE_Pos            (26U)\n#define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x0C000000 */\n#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                 /*!< FMODE[1:0]: Functional Mode           */\n#define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x04000000 */\n#define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)       /*!< 0x08000000 */\n#define QUADSPI_CCR_SIOO_Pos             (28U)\n#define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)        /*!< 0x10000000 */\n#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                  /*!< SIOO: Send Instruction Only Once Mode */\n#define QUADSPI_CCR_DHHC_Pos             (30U)\n#define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)        /*!< 0x40000000 */\n#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                  /*!< DHHC: Delay Half Hclk Cycle           */\n#define QUADSPI_CCR_DDRM_Pos             (31U)\n#define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)        /*!< 0x80000000 */\n#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                  /*!< DDRM: Double Data Rate Mode           */\n/******************  Bit definition for QUADSPI_AR register  *******************/\n#define QUADSPI_AR_ADDRESS_Pos           (0U)\n#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address                */\n\n/******************  Bit definition for QUADSPI_ABR register  ******************/\n#define QUADSPI_ABR_ALTERNATE_Pos        (0U)\n#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes      */\n\n/******************  Bit definition for QUADSPI_DR register  *******************/\n#define QUADSPI_DR_DATA_Pos              (0U)\n#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)  /*!< 0xFFFFFFFF */\n#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data                      */\n\n/******************  Bit definition for QUADSPI_PSMKR register  ****************/\n#define QUADSPI_PSMKR_MASK_Pos           (0U)\n#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask               */\n\n/******************  Bit definition for QUADSPI_PSMAR register  ****************/\n#define QUADSPI_PSMAR_MATCH_Pos          (0U)\n#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match             */\n\n/******************  Bit definition for QUADSPI_PIR register  *****************/\n#define QUADSPI_PIR_INTERVAL_Pos         (0U)\n#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */\n#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval      */\n\n/******************  Bit definition for QUADSPI_LPTR register  *****************/\n#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)\n#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */\n#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period         */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Reset and Clock Control                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for RCC_CR register  ********************/\n#define RCC_CR_HSION_Pos                   (0U)\n#define RCC_CR_HSION_Msk                   (0x1UL << RCC_CR_HSION_Pos)          /*!< 0x00000001 */\n#define RCC_CR_HSION                       RCC_CR_HSION_Msk\n#define RCC_CR_HSIRDY_Pos                  (1U)\n#define RCC_CR_HSIRDY_Msk                  (0x1UL << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */\n#define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk\n\n#define RCC_CR_HSITRIM_Pos                 (3U)\n#define RCC_CR_HSITRIM_Msk                 (0x1FUL << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */\n#define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk\n#define RCC_CR_HSITRIM_0                   (0x01UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */\n#define RCC_CR_HSITRIM_1                   (0x02UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */\n#define RCC_CR_HSITRIM_2                   (0x04UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */\n#define RCC_CR_HSITRIM_3                   (0x08UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */\n#define RCC_CR_HSITRIM_4                   (0x10UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */\n\n#define RCC_CR_HSICAL_Pos                  (8U)\n#define RCC_CR_HSICAL_Msk                  (0xFFUL << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */\n#define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk\n#define RCC_CR_HSICAL_0                    (0x01UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */\n#define RCC_CR_HSICAL_1                    (0x02UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */\n#define RCC_CR_HSICAL_2                    (0x04UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */\n#define RCC_CR_HSICAL_3                    (0x08UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */\n#define RCC_CR_HSICAL_4                    (0x10UL << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */\n#define RCC_CR_HSICAL_5                    (0x20UL << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */\n#define RCC_CR_HSICAL_6                    (0x40UL << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */\n#define RCC_CR_HSICAL_7                    (0x80UL << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */\n\n#define RCC_CR_HSEON_Pos                   (16U)\n#define RCC_CR_HSEON_Msk                   (0x1UL << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */\n#define RCC_CR_HSEON                       RCC_CR_HSEON_Msk\n#define RCC_CR_HSERDY_Pos                  (17U)\n#define RCC_CR_HSERDY_Msk                  (0x1UL << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */\n#define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk\n#define RCC_CR_HSEBYP_Pos                  (18U)\n#define RCC_CR_HSEBYP_Msk                  (0x1UL << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */\n#define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk\n#define RCC_CR_CSSON_Pos                   (19U)\n#define RCC_CR_CSSON_Msk                   (0x1UL << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */\n#define RCC_CR_CSSON                       RCC_CR_CSSON_Msk\n#define RCC_CR_PLLON_Pos                   (24U)\n#define RCC_CR_PLLON_Msk                   (0x1UL << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */\n#define RCC_CR_PLLON                       RCC_CR_PLLON_Msk\n#define RCC_CR_PLLRDY_Pos                  (25U)\n#define RCC_CR_PLLRDY_Msk                  (0x1UL << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */\n#define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_PLLI2S_SUPPORT                                                     /*!< Support PLLI2S oscillator */\n\n#define RCC_CR_PLLI2SON_Pos                (26U)\n#define RCC_CR_PLLI2SON_Msk                (0x1UL << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */\n#define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk\n#define RCC_CR_PLLI2SRDY_Pos               (27U)\n#define RCC_CR_PLLI2SRDY_Msk               (0x1UL << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */\n#define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_PLLSAI_SUPPORT                                                     /*!< Support PLLSAI oscillator */\n\n#define RCC_CR_PLLSAION_Pos                (28U)\n#define RCC_CR_PLLSAION_Msk                (0x1UL << RCC_CR_PLLSAION_Pos)       /*!< 0x10000000 */\n#define RCC_CR_PLLSAION                    RCC_CR_PLLSAION_Msk\n#define RCC_CR_PLLSAIRDY_Pos               (29U)\n#define RCC_CR_PLLSAIRDY_Msk               (0x1UL << RCC_CR_PLLSAIRDY_Pos)      /*!< 0x20000000 */\n#define RCC_CR_PLLSAIRDY                   RCC_CR_PLLSAIRDY_Msk\n\n/********************  Bit definition for RCC_PLLCFGR register  ***************/\n#define RCC_PLLCFGR_PLLM_Pos               (0U)\n#define RCC_PLLCFGR_PLLM_Msk               (0x3FUL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */\n#define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk\n#define RCC_PLLCFGR_PLLM_0                 (0x01UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */\n#define RCC_PLLCFGR_PLLM_1                 (0x02UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */\n#define RCC_PLLCFGR_PLLM_2                 (0x04UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */\n#define RCC_PLLCFGR_PLLM_3                 (0x08UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */\n#define RCC_PLLCFGR_PLLM_4                 (0x10UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */\n#define RCC_PLLCFGR_PLLM_5                 (0x20UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */\n\n#define RCC_PLLCFGR_PLLN_Pos               (6U)\n#define RCC_PLLCFGR_PLLN_Msk               (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */\n#define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk\n#define RCC_PLLCFGR_PLLN_0                 (0x001UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */\n#define RCC_PLLCFGR_PLLN_1                 (0x002UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */\n#define RCC_PLLCFGR_PLLN_2                 (0x004UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */\n#define RCC_PLLCFGR_PLLN_3                 (0x008UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */\n#define RCC_PLLCFGR_PLLN_4                 (0x010UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */\n#define RCC_PLLCFGR_PLLN_5                 (0x020UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */\n#define RCC_PLLCFGR_PLLN_6                 (0x040UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */\n#define RCC_PLLCFGR_PLLN_7                 (0x080UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */\n#define RCC_PLLCFGR_PLLN_8                 (0x100UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */\n\n#define RCC_PLLCFGR_PLLP_Pos               (16U)\n#define RCC_PLLCFGR_PLLP_Msk               (0x3UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */\n#define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk\n#define RCC_PLLCFGR_PLLP_0                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */\n#define RCC_PLLCFGR_PLLP_1                 (0x2UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */\n\n#define RCC_PLLCFGR_PLLSRC_Pos             (22U)\n#define RCC_PLLCFGR_PLLSRC_Msk             (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk\n#define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)\n#define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk\n#define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U\n\n#define RCC_PLLCFGR_PLLQ_Pos               (24U)\n#define RCC_PLLCFGR_PLLQ_Msk               (0xFUL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */\n#define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk\n#define RCC_PLLCFGR_PLLQ_0                 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */\n#define RCC_PLLCFGR_PLLQ_1                 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */\n#define RCC_PLLCFGR_PLLQ_2                 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */\n#define RCC_PLLCFGR_PLLQ_3                 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_PLLR_SYSCLK_SUPPORT            /*!< Support PLLR as system clock */\n#define RCC_PLLR_I2S_CLKSOURCE_SUPPORT     /*!< Support PLLR clock as I2S clock source */\n\n#define RCC_PLLCFGR_PLLR_Pos               (28U)\n#define RCC_PLLCFGR_PLLR_Msk               (0x7UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x70000000 */\n#define RCC_PLLCFGR_PLLR                   RCC_PLLCFGR_PLLR_Msk\n#define RCC_PLLCFGR_PLLR_0                 (0x1UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x10000000 */\n#define RCC_PLLCFGR_PLLR_1                 (0x2UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x20000000 */\n#define RCC_PLLCFGR_PLLR_2                 (0x4UL << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x40000000 */\n\n/********************  Bit definition for RCC_CFGR register  ******************/\n/*!< SW configuration */\n#define RCC_CFGR_SW_Pos                    (0U)\n#define RCC_CFGR_SW_Msk                    (0x3UL << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */\n#define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */\n#define RCC_CFGR_SW_0                      (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */\n#define RCC_CFGR_SW_1                      (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */\n\n#define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */\n#define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */\n#define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */\n#define RCC_CFGR_SW_PLLR                   0x00000003U                         /*!< PLL/PLLR selected as system clock */\n\n/*!< SWS configuration */\n#define RCC_CFGR_SWS_Pos                   (2U)\n#define RCC_CFGR_SWS_Msk                   (0x3UL << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */\n#define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */\n#define RCC_CFGR_SWS_0                     (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */\n#define RCC_CFGR_SWS_1                     (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */\n\n#define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */\n#define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */\n#define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */\n#define RCC_CFGR_SWS_PLLR                  0x0000000CU                         /*!< PLL/PLLR used as system clock       */\n\n/*!< HPRE configuration */\n#define RCC_CFGR_HPRE_Pos                  (4U)\n#define RCC_CFGR_HPRE_Msk                  (0xFUL << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */\n#define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */\n#define RCC_CFGR_HPRE_0                    (0x1UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */\n#define RCC_CFGR_HPRE_1                    (0x2UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */\n#define RCC_CFGR_HPRE_2                    (0x4UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */\n#define RCC_CFGR_HPRE_3                    (0x8UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */\n\n#define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */\n#define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */\n#define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */\n#define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */\n#define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */\n#define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */\n#define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */\n#define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */\n#define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */\n\n/*!< PPRE1 configuration */\n#define RCC_CFGR_PPRE1_Pos                 (10U)\n#define RCC_CFGR_PPRE1_Msk                 (0x7UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */\n#define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */\n#define RCC_CFGR_PPRE1_0                   (0x1UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */\n#define RCC_CFGR_PPRE1_1                   (0x2UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */\n#define RCC_CFGR_PPRE1_2                   (0x4UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */\n\n#define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */\n\n/*!< PPRE2 configuration */\n#define RCC_CFGR_PPRE2_Pos                 (13U)\n#define RCC_CFGR_PPRE2_Msk                 (0x7UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */\n#define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */\n#define RCC_CFGR_PPRE2_0                   (0x1UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */\n#define RCC_CFGR_PPRE2_1                   (0x2UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */\n#define RCC_CFGR_PPRE2_2                   (0x4UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */\n\n#define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */\n\n/*!< RTCPRE configuration */\n#define RCC_CFGR_RTCPRE_Pos                (16U)\n#define RCC_CFGR_RTCPRE_Msk                (0x1FUL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */\n#define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk\n#define RCC_CFGR_RTCPRE_0                  (0x01UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */\n#define RCC_CFGR_RTCPRE_1                  (0x02UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */\n#define RCC_CFGR_RTCPRE_2                  (0x04UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */\n#define RCC_CFGR_RTCPRE_3                  (0x08UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */\n#define RCC_CFGR_RTCPRE_4                  (0x10UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */\n\n/*!< MCO1 configuration */\n#define RCC_CFGR_MCO1_Pos                  (21U)\n#define RCC_CFGR_MCO1_Msk                  (0x3UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */\n#define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk\n#define RCC_CFGR_MCO1_0                    (0x1UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */\n#define RCC_CFGR_MCO1_1                    (0x2UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */\n\n\n#define RCC_CFGR_MCO1PRE_Pos               (24U)\n#define RCC_CFGR_MCO1PRE_Msk               (0x7UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */\n#define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk\n#define RCC_CFGR_MCO1PRE_0                 (0x1UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */\n#define RCC_CFGR_MCO1PRE_1                 (0x2UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */\n#define RCC_CFGR_MCO1PRE_2                 (0x4UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */\n\n#define RCC_CFGR_MCO2PRE_Pos               (27U)\n#define RCC_CFGR_MCO2PRE_Msk               (0x7UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */\n#define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk\n#define RCC_CFGR_MCO2PRE_0                 (0x1UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */\n#define RCC_CFGR_MCO2PRE_1                 (0x2UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */\n#define RCC_CFGR_MCO2PRE_2                 (0x4UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */\n\n#define RCC_CFGR_MCO2_Pos                  (30U)\n#define RCC_CFGR_MCO2_Msk                  (0x3UL << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */\n#define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk\n#define RCC_CFGR_MCO2_0                    (0x1UL << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */\n#define RCC_CFGR_MCO2_1                    (0x2UL << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */\n\n/********************  Bit definition for RCC_CIR register  *******************/\n#define RCC_CIR_LSIRDYF_Pos                (0U)\n#define RCC_CIR_LSIRDYF_Msk                (0x1UL << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */\n#define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk\n#define RCC_CIR_LSERDYF_Pos                (1U)\n#define RCC_CIR_LSERDYF_Msk                (0x1UL << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */\n#define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk\n#define RCC_CIR_HSIRDYF_Pos                (2U)\n#define RCC_CIR_HSIRDYF_Msk                (0x1UL << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */\n#define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk\n#define RCC_CIR_HSERDYF_Pos                (3U)\n#define RCC_CIR_HSERDYF_Msk                (0x1UL << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */\n#define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk\n#define RCC_CIR_PLLRDYF_Pos                (4U)\n#define RCC_CIR_PLLRDYF_Msk                (0x1UL << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */\n#define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk\n#define RCC_CIR_PLLI2SRDYF_Pos             (5U)\n#define RCC_CIR_PLLI2SRDYF_Msk             (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */\n#define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk\n\n#define RCC_CIR_PLLSAIRDYF_Pos             (6U)\n#define RCC_CIR_PLLSAIRDYF_Msk             (0x1UL << RCC_CIR_PLLSAIRDYF_Pos)    /*!< 0x00000040 */\n#define RCC_CIR_PLLSAIRDYF                 RCC_CIR_PLLSAIRDYF_Msk\n#define RCC_CIR_CSSF_Pos                   (7U)\n#define RCC_CIR_CSSF_Msk                   (0x1UL << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */\n#define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk\n#define RCC_CIR_LSIRDYIE_Pos               (8U)\n#define RCC_CIR_LSIRDYIE_Msk               (0x1UL << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */\n#define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk\n#define RCC_CIR_LSERDYIE_Pos               (9U)\n#define RCC_CIR_LSERDYIE_Msk               (0x1UL << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */\n#define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk\n#define RCC_CIR_HSIRDYIE_Pos               (10U)\n#define RCC_CIR_HSIRDYIE_Msk               (0x1UL << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */\n#define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk\n#define RCC_CIR_HSERDYIE_Pos               (11U)\n#define RCC_CIR_HSERDYIE_Msk               (0x1UL << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */\n#define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk\n#define RCC_CIR_PLLRDYIE_Pos               (12U)\n#define RCC_CIR_PLLRDYIE_Msk               (0x1UL << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */\n#define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk\n#define RCC_CIR_PLLI2SRDYIE_Pos            (13U)\n#define RCC_CIR_PLLI2SRDYIE_Msk            (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */\n#define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk\n\n#define RCC_CIR_PLLSAIRDYIE_Pos            (14U)\n#define RCC_CIR_PLLSAIRDYIE_Msk            (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos)   /*!< 0x00004000 */\n#define RCC_CIR_PLLSAIRDYIE                RCC_CIR_PLLSAIRDYIE_Msk\n#define RCC_CIR_LSIRDYC_Pos                (16U)\n#define RCC_CIR_LSIRDYC_Msk                (0x1UL << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */\n#define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk\n#define RCC_CIR_LSERDYC_Pos                (17U)\n#define RCC_CIR_LSERDYC_Msk                (0x1UL << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */\n#define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk\n#define RCC_CIR_HSIRDYC_Pos                (18U)\n#define RCC_CIR_HSIRDYC_Msk                (0x1UL << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */\n#define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk\n#define RCC_CIR_HSERDYC_Pos                (19U)\n#define RCC_CIR_HSERDYC_Msk                (0x1UL << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */\n#define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk\n#define RCC_CIR_PLLRDYC_Pos                (20U)\n#define RCC_CIR_PLLRDYC_Msk                (0x1UL << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */\n#define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk\n#define RCC_CIR_PLLI2SRDYC_Pos             (21U)\n#define RCC_CIR_PLLI2SRDYC_Msk             (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */\n#define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk\n#define RCC_CIR_PLLSAIRDYC_Pos             (22U)\n#define RCC_CIR_PLLSAIRDYC_Msk             (0x1UL << RCC_CIR_PLLSAIRDYC_Pos)    /*!< 0x00400000 */\n#define RCC_CIR_PLLSAIRDYC                 RCC_CIR_PLLSAIRDYC_Msk\n\n#define RCC_CIR_CSSC_Pos                   (23U)\n#define RCC_CIR_CSSC_Msk                   (0x1UL << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */\n#define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk\n\n/********************  Bit definition for RCC_AHB1RSTR register  **************/\n#define RCC_AHB1RSTR_GPIOARST_Pos          (0U)\n#define RCC_AHB1RSTR_GPIOARST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */\n#define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk\n#define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)\n#define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */\n#define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk\n#define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)\n#define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */\n#define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk\n#define RCC_AHB1RSTR_GPIODRST_Pos          (3U)\n#define RCC_AHB1RSTR_GPIODRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */\n#define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk\n#define RCC_AHB1RSTR_GPIOERST_Pos          (4U)\n#define RCC_AHB1RSTR_GPIOERST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */\n#define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk\n#define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)\n#define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */\n#define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk\n#define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)\n#define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */\n#define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk\n#define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)\n#define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk\n#define RCC_AHB1RSTR_CRCRST_Pos            (12U)\n#define RCC_AHB1RSTR_CRCRST_Msk            (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */\n#define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk\n#define RCC_AHB1RSTR_DMA1RST_Pos           (21U)\n#define RCC_AHB1RSTR_DMA1RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */\n#define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk\n#define RCC_AHB1RSTR_DMA2RST_Pos           (22U)\n#define RCC_AHB1RSTR_DMA2RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */\n#define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk\n#define RCC_AHB1RSTR_OTGHRST_Pos           (29U)\n#define RCC_AHB1RSTR_OTGHRST_Msk           (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)  /*!< 0x20000000 */\n#define RCC_AHB1RSTR_OTGHRST               RCC_AHB1RSTR_OTGHRST_Msk\n\n/********************  Bit definition for RCC_AHB2RSTR register  **************/\n#define RCC_AHB2RSTR_DCMIRST_Pos           (0U)\n#define RCC_AHB2RSTR_DCMIRST_Msk           (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)  /*!< 0x00000001 */\n#define RCC_AHB2RSTR_DCMIRST               RCC_AHB2RSTR_DCMIRST_Msk\n#define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)\n#define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk\n/********************  Bit definition for RCC_AHB3RSTR register  **************/\n#define RCC_AHB3RSTR_FMCRST_Pos            (0U)\n#define RCC_AHB3RSTR_FMCRST_Msk            (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)   /*!< 0x00000001 */\n#define RCC_AHB3RSTR_FMCRST                RCC_AHB3RSTR_FMCRST_Msk\n#define RCC_AHB3RSTR_QSPIRST_Pos           (1U)\n#define RCC_AHB3RSTR_QSPIRST_Msk           (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)  /*!< 0x00000002 */\n#define RCC_AHB3RSTR_QSPIRST               RCC_AHB3RSTR_QSPIRST_Msk\n\n\n/********************  Bit definition for RCC_APB1RSTR register  **************/\n#define RCC_APB1RSTR_TIM2RST_Pos           (0U)\n#define RCC_APB1RSTR_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk\n#define RCC_APB1RSTR_TIM3RST_Pos           (1U)\n#define RCC_APB1RSTR_TIM3RST_Msk           (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk\n#define RCC_APB1RSTR_TIM4RST_Pos           (2U)\n#define RCC_APB1RSTR_TIM4RST_Msk           (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */\n#define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk\n#define RCC_APB1RSTR_TIM5RST_Pos           (3U)\n#define RCC_APB1RSTR_TIM5RST_Msk           (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */\n#define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk\n#define RCC_APB1RSTR_TIM6RST_Pos           (4U)\n#define RCC_APB1RSTR_TIM6RST_Msk           (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */\n#define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk\n#define RCC_APB1RSTR_TIM7RST_Pos           (5U)\n#define RCC_APB1RSTR_TIM7RST_Msk           (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */\n#define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk\n#define RCC_APB1RSTR_TIM12RST_Pos          (6U)\n#define RCC_APB1RSTR_TIM12RST_Msk          (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */\n#define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk\n#define RCC_APB1RSTR_TIM13RST_Pos          (7U)\n#define RCC_APB1RSTR_TIM13RST_Msk          (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */\n#define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk\n#define RCC_APB1RSTR_TIM14RST_Pos          (8U)\n#define RCC_APB1RSTR_TIM14RST_Msk          (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */\n#define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk\n#define RCC_APB1RSTR_WWDGRST_Pos           (11U)\n#define RCC_APB1RSTR_WWDGRST_Msk           (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */\n#define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk\n#define RCC_APB1RSTR_SPI2RST_Pos           (14U)\n#define RCC_APB1RSTR_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */\n#define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk\n#define RCC_APB1RSTR_SPI3RST_Pos           (15U)\n#define RCC_APB1RSTR_SPI3RST_Msk           (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */\n#define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk\n#define RCC_APB1RSTR_SPDIFRXRST_Pos        (16U)\n#define RCC_APB1RSTR_SPDIFRXRST_Msk        (0x1UL << RCC_APB1RSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */\n#define RCC_APB1RSTR_SPDIFRXRST            RCC_APB1RSTR_SPDIFRXRST_Msk\n#define RCC_APB1RSTR_USART2RST_Pos         (17U)\n#define RCC_APB1RSTR_USART2RST_Msk         (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */\n#define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk\n#define RCC_APB1RSTR_USART3RST_Pos         (18U)\n#define RCC_APB1RSTR_USART3RST_Msk         (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */\n#define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk\n#define RCC_APB1RSTR_UART4RST_Pos          (19U)\n#define RCC_APB1RSTR_UART4RST_Msk          (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */\n#define RCC_APB1RSTR_UART4RST              RCC_APB1RSTR_UART4RST_Msk\n#define RCC_APB1RSTR_UART5RST_Pos          (20U)\n#define RCC_APB1RSTR_UART5RST_Msk          (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */\n#define RCC_APB1RSTR_UART5RST              RCC_APB1RSTR_UART5RST_Msk\n#define RCC_APB1RSTR_I2C1RST_Pos           (21U)\n#define RCC_APB1RSTR_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */\n#define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk\n#define RCC_APB1RSTR_I2C2RST_Pos           (22U)\n#define RCC_APB1RSTR_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */\n#define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk\n#define RCC_APB1RSTR_I2C3RST_Pos           (23U)\n#define RCC_APB1RSTR_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */\n#define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk\n#define RCC_APB1RSTR_FMPI2C1RST_Pos        (24U)\n#define RCC_APB1RSTR_FMPI2C1RST_Msk        (0x1UL << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */\n#define RCC_APB1RSTR_FMPI2C1RST            RCC_APB1RSTR_FMPI2C1RST_Msk\n#define RCC_APB1RSTR_CAN1RST_Pos           (25U)\n#define RCC_APB1RSTR_CAN1RST_Msk           (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */\n#define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk\n#define RCC_APB1RSTR_CAN2RST_Pos           (26U)\n#define RCC_APB1RSTR_CAN2RST_Msk           (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */\n#define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk\n#define RCC_APB1RSTR_CECRST_Pos            (27U)\n#define RCC_APB1RSTR_CECRST_Msk            (0x1UL << RCC_APB1RSTR_CECRST_Pos)   /*!< 0x08000000 */\n#define RCC_APB1RSTR_CECRST                RCC_APB1RSTR_CECRST_Msk\n#define RCC_APB1RSTR_PWRRST_Pos            (28U)\n#define RCC_APB1RSTR_PWRRST_Msk            (0x1UL << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */\n#define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk\n#define RCC_APB1RSTR_DACRST_Pos            (29U)\n#define RCC_APB1RSTR_DACRST_Msk            (0x1UL << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */\n#define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk\n\n/********************  Bit definition for RCC_APB2RSTR register  **************/\n#define RCC_APB2RSTR_TIM1RST_Pos           (0U)\n#define RCC_APB2RSTR_TIM1RST_Msk           (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk\n#define RCC_APB2RSTR_TIM8RST_Pos           (1U)\n#define RCC_APB2RSTR_TIM8RST_Msk           (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk\n#define RCC_APB2RSTR_USART1RST_Pos         (4U)\n#define RCC_APB2RSTR_USART1RST_Msk         (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */\n#define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk\n#define RCC_APB2RSTR_USART6RST_Pos         (5U)\n#define RCC_APB2RSTR_USART6RST_Msk         (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */\n#define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk\n#define RCC_APB2RSTR_ADCRST_Pos            (8U)\n#define RCC_APB2RSTR_ADCRST_Msk            (0x1UL << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */\n#define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk\n#define RCC_APB2RSTR_SDIORST_Pos           (11U)\n#define RCC_APB2RSTR_SDIORST_Msk           (0x1UL << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */\n#define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk\n#define RCC_APB2RSTR_SPI1RST_Pos           (12U)\n#define RCC_APB2RSTR_SPI1RST_Msk           (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */\n#define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk\n#define RCC_APB2RSTR_SPI4RST_Pos           (13U)\n#define RCC_APB2RSTR_SPI4RST_Msk           (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)  /*!< 0x00002000 */\n#define RCC_APB2RSTR_SPI4RST               RCC_APB2RSTR_SPI4RST_Msk\n#define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)\n#define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */\n#define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk\n#define RCC_APB2RSTR_TIM9RST_Pos           (16U)\n#define RCC_APB2RSTR_TIM9RST_Msk           (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */\n#define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk\n#define RCC_APB2RSTR_TIM10RST_Pos          (17U)\n#define RCC_APB2RSTR_TIM10RST_Msk          (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */\n#define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk\n#define RCC_APB2RSTR_TIM11RST_Pos          (18U)\n#define RCC_APB2RSTR_TIM11RST_Msk          (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */\n#define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk\n#define RCC_APB2RSTR_SAI1RST_Pos           (22U)\n#define RCC_APB2RSTR_SAI1RST_Msk           (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)  /*!< 0x00400000 */\n#define RCC_APB2RSTR_SAI1RST               RCC_APB2RSTR_SAI1RST_Msk\n#define RCC_APB2RSTR_SAI2RST_Pos           (23U)\n#define RCC_APB2RSTR_SAI2RST_Msk           (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)  /*!< 0x00800000 */\n#define RCC_APB2RSTR_SAI2RST               RCC_APB2RSTR_SAI2RST_Msk\n\n/* Old SPI1RST bit definition, maintained for legacy purpose */\n#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST\n\n/********************  Bit definition for RCC_AHB1ENR register  ***************/\n#define RCC_AHB1ENR_GPIOAEN_Pos            (0U)\n#define RCC_AHB1ENR_GPIOAEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */\n#define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk\n#define RCC_AHB1ENR_GPIOBEN_Pos            (1U)\n#define RCC_AHB1ENR_GPIOBEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */\n#define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk\n#define RCC_AHB1ENR_GPIOCEN_Pos            (2U)\n#define RCC_AHB1ENR_GPIOCEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */\n#define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk\n#define RCC_AHB1ENR_GPIODEN_Pos            (3U)\n#define RCC_AHB1ENR_GPIODEN_Msk            (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */\n#define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk\n#define RCC_AHB1ENR_GPIOEEN_Pos            (4U)\n#define RCC_AHB1ENR_GPIOEEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */\n#define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk\n#define RCC_AHB1ENR_GPIOFEN_Pos            (5U)\n#define RCC_AHB1ENR_GPIOFEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */\n#define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk\n#define RCC_AHB1ENR_GPIOGEN_Pos            (6U)\n#define RCC_AHB1ENR_GPIOGEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */\n#define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk\n#define RCC_AHB1ENR_GPIOHEN_Pos            (7U)\n#define RCC_AHB1ENR_GPIOHEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk\n#define RCC_AHB1ENR_CRCEN_Pos              (12U)\n#define RCC_AHB1ENR_CRCEN_Msk              (0x1UL << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */\n#define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk\n#define RCC_AHB1ENR_BKPSRAMEN_Pos          (18U)\n#define RCC_AHB1ENR_BKPSRAMEN_Msk          (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */\n#define RCC_AHB1ENR_BKPSRAMEN              RCC_AHB1ENR_BKPSRAMEN_Msk\n#define RCC_AHB1ENR_DMA1EN_Pos             (21U)\n#define RCC_AHB1ENR_DMA1EN_Msk             (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */\n#define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk\n#define RCC_AHB1ENR_DMA2EN_Pos             (22U)\n#define RCC_AHB1ENR_DMA2EN_Msk             (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */\n#define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk\n#define RCC_AHB1ENR_OTGHSEN_Pos            (29U)\n#define RCC_AHB1ENR_OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)   /*!< 0x20000000 */\n#define RCC_AHB1ENR_OTGHSEN                RCC_AHB1ENR_OTGHSEN_Msk\n#define RCC_AHB1ENR_OTGHSULPIEN_Pos        (30U)\n#define RCC_AHB1ENR_OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */\n#define RCC_AHB1ENR_OTGHSULPIEN            RCC_AHB1ENR_OTGHSULPIEN_Msk\n/********************  Bit definition for RCC_AHB2ENR register  ***************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_AHB2_SUPPORT                   /*!< AHB2 Bus is supported */\n\n#define RCC_AHB2ENR_DCMIEN_Pos             (0U)\n#define RCC_AHB2ENR_DCMIEN_Msk             (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)    /*!< 0x00000001 */\n#define RCC_AHB2ENR_DCMIEN                 RCC_AHB2ENR_DCMIEN_Msk\n#define RCC_AHB2ENR_OTGFSEN_Pos            (7U)\n#define RCC_AHB2ENR_OTGFSEN_Msk            (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk\n\n/********************  Bit definition for RCC_AHB3ENR register  ***************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_AHB3_SUPPORT                   /*!< AHB3 Bus is supported */\n\n#define RCC_AHB3ENR_FMCEN_Pos              (0U)\n#define RCC_AHB3ENR_FMCEN_Msk              (0x1UL << RCC_AHB3ENR_FMCEN_Pos)     /*!< 0x00000001 */\n#define RCC_AHB3ENR_FMCEN                  RCC_AHB3ENR_FMCEN_Msk\n#define RCC_AHB3ENR_QSPIEN_Pos             (1U)\n#define RCC_AHB3ENR_QSPIEN_Msk             (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)    /*!< 0x00000002 */\n#define RCC_AHB3ENR_QSPIEN                 RCC_AHB3ENR_QSPIEN_Msk\n\n/********************  Bit definition for RCC_APB1ENR register  ***************/\n#define RCC_APB1ENR_TIM2EN_Pos             (0U)\n#define RCC_APB1ENR_TIM2EN_Msk             (0x1UL << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk\n#define RCC_APB1ENR_TIM3EN_Pos             (1U)\n#define RCC_APB1ENR_TIM3EN_Msk             (0x1UL << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk\n#define RCC_APB1ENR_TIM4EN_Pos             (2U)\n#define RCC_APB1ENR_TIM4EN_Msk             (0x1UL << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */\n#define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk\n#define RCC_APB1ENR_TIM5EN_Pos             (3U)\n#define RCC_APB1ENR_TIM5EN_Msk             (0x1UL << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */\n#define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk\n#define RCC_APB1ENR_TIM6EN_Pos             (4U)\n#define RCC_APB1ENR_TIM6EN_Msk             (0x1UL << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */\n#define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk\n#define RCC_APB1ENR_TIM7EN_Pos             (5U)\n#define RCC_APB1ENR_TIM7EN_Msk             (0x1UL << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */\n#define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk\n#define RCC_APB1ENR_TIM12EN_Pos            (6U)\n#define RCC_APB1ENR_TIM12EN_Msk            (0x1UL << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */\n#define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk\n#define RCC_APB1ENR_TIM13EN_Pos            (7U)\n#define RCC_APB1ENR_TIM13EN_Msk            (0x1UL << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */\n#define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk\n#define RCC_APB1ENR_TIM14EN_Pos            (8U)\n#define RCC_APB1ENR_TIM14EN_Msk            (0x1UL << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */\n#define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk\n#define RCC_APB1ENR_WWDGEN_Pos             (11U)\n#define RCC_APB1ENR_WWDGEN_Msk             (0x1UL << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk\n#define RCC_APB1ENR_SPI2EN_Pos             (14U)\n#define RCC_APB1ENR_SPI2EN_Msk             (0x1UL << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */\n#define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk\n#define RCC_APB1ENR_SPI3EN_Pos             (15U)\n#define RCC_APB1ENR_SPI3EN_Msk             (0x1UL << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */\n#define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk\n#define RCC_APB1ENR_SPDIFRXEN_Pos          (16U)\n#define RCC_APB1ENR_SPDIFRXEN_Msk          (0x1UL << RCC_APB1ENR_SPDIFRXEN_Pos) /*!< 0x00010000 */\n#define RCC_APB1ENR_SPDIFRXEN              RCC_APB1ENR_SPDIFRXEN_Msk\n#define RCC_APB1ENR_USART2EN_Pos           (17U)\n#define RCC_APB1ENR_USART2EN_Msk           (0x1UL << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */\n#define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk\n#define RCC_APB1ENR_USART3EN_Pos           (18U)\n#define RCC_APB1ENR_USART3EN_Msk           (0x1UL << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */\n#define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk\n#define RCC_APB1ENR_UART4EN_Pos            (19U)\n#define RCC_APB1ENR_UART4EN_Msk            (0x1UL << RCC_APB1ENR_UART4EN_Pos)   /*!< 0x00080000 */\n#define RCC_APB1ENR_UART4EN                RCC_APB1ENR_UART4EN_Msk\n#define RCC_APB1ENR_UART5EN_Pos            (20U)\n#define RCC_APB1ENR_UART5EN_Msk            (0x1UL << RCC_APB1ENR_UART5EN_Pos)   /*!< 0x00100000 */\n#define RCC_APB1ENR_UART5EN                RCC_APB1ENR_UART5EN_Msk\n#define RCC_APB1ENR_I2C1EN_Pos             (21U)\n#define RCC_APB1ENR_I2C1EN_Msk             (0x1UL << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */\n#define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk\n#define RCC_APB1ENR_I2C2EN_Pos             (22U)\n#define RCC_APB1ENR_I2C2EN_Msk             (0x1UL << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */\n#define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk\n#define RCC_APB1ENR_I2C3EN_Pos             (23U)\n#define RCC_APB1ENR_I2C3EN_Msk             (0x1UL << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */\n#define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk\n#define RCC_APB1ENR_FMPI2C1EN_Pos          (24U)\n#define RCC_APB1ENR_FMPI2C1EN_Msk          (0x1UL << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */\n#define RCC_APB1ENR_FMPI2C1EN              RCC_APB1ENR_FMPI2C1EN_Msk\n#define RCC_APB1ENR_CAN1EN_Pos             (25U)\n#define RCC_APB1ENR_CAN1EN_Msk             (0x1UL << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */\n#define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk\n#define RCC_APB1ENR_CAN2EN_Pos             (26U)\n#define RCC_APB1ENR_CAN2EN_Msk             (0x1UL << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */\n#define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk\n#define RCC_APB1ENR_CECEN_Pos              (27U)\n#define RCC_APB1ENR_CECEN_Msk              (0x1UL << RCC_APB1ENR_CECEN_Pos)     /*!< 0x08000000 */\n#define RCC_APB1ENR_CECEN                  RCC_APB1ENR_CECEN_Msk\n#define RCC_APB1ENR_PWREN_Pos              (28U)\n#define RCC_APB1ENR_PWREN_Msk              (0x1UL << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */\n#define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk\n#define RCC_APB1ENR_DACEN_Pos              (29U)\n#define RCC_APB1ENR_DACEN_Msk              (0x1UL << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */\n#define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk\n\n/********************  Bit definition for RCC_APB2ENR register  ***************/\n#define RCC_APB2ENR_TIM1EN_Pos             (0U)\n#define RCC_APB2ENR_TIM1EN_Msk             (0x1UL << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk\n#define RCC_APB2ENR_TIM8EN_Pos             (1U)\n#define RCC_APB2ENR_TIM8EN_Msk             (0x1UL << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk\n#define RCC_APB2ENR_USART1EN_Pos           (4U)\n#define RCC_APB2ENR_USART1EN_Msk           (0x1UL << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */\n#define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk\n#define RCC_APB2ENR_USART6EN_Pos           (5U)\n#define RCC_APB2ENR_USART6EN_Msk           (0x1UL << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */\n#define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk\n#define RCC_APB2ENR_ADC1EN_Pos             (8U)\n#define RCC_APB2ENR_ADC1EN_Msk             (0x1UL << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */\n#define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk\n#define RCC_APB2ENR_ADC2EN_Pos             (9U)\n#define RCC_APB2ENR_ADC2EN_Msk             (0x1UL << RCC_APB2ENR_ADC2EN_Pos)    /*!< 0x00000200 */\n#define RCC_APB2ENR_ADC2EN                 RCC_APB2ENR_ADC2EN_Msk\n#define RCC_APB2ENR_ADC3EN_Pos             (10U)\n#define RCC_APB2ENR_ADC3EN_Msk             (0x1UL << RCC_APB2ENR_ADC3EN_Pos)    /*!< 0x00000400 */\n#define RCC_APB2ENR_ADC3EN                 RCC_APB2ENR_ADC3EN_Msk\n#define RCC_APB2ENR_SDIOEN_Pos             (11U)\n#define RCC_APB2ENR_SDIOEN_Msk             (0x1UL << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk\n#define RCC_APB2ENR_SPI1EN_Pos             (12U)\n#define RCC_APB2ENR_SPI1EN_Msk             (0x1UL << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */\n#define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk\n#define RCC_APB2ENR_SPI4EN_Pos             (13U)\n#define RCC_APB2ENR_SPI4EN_Msk             (0x1UL << RCC_APB2ENR_SPI4EN_Pos)    /*!< 0x00002000 */\n#define RCC_APB2ENR_SPI4EN                 RCC_APB2ENR_SPI4EN_Msk\n#define RCC_APB2ENR_SYSCFGEN_Pos           (14U)\n#define RCC_APB2ENR_SYSCFGEN_Msk           (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */\n#define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk\n#define RCC_APB2ENR_TIM9EN_Pos             (16U)\n#define RCC_APB2ENR_TIM9EN_Msk             (0x1UL << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */\n#define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk\n#define RCC_APB2ENR_TIM10EN_Pos            (17U)\n#define RCC_APB2ENR_TIM10EN_Msk            (0x1UL << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */\n#define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk\n#define RCC_APB2ENR_TIM11EN_Pos            (18U)\n#define RCC_APB2ENR_TIM11EN_Msk            (0x1UL << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */\n#define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk\n#define RCC_APB2ENR_SAI1EN_Pos             (22U)\n#define RCC_APB2ENR_SAI1EN_Msk             (0x1UL << RCC_APB2ENR_SAI1EN_Pos)    /*!< 0x00400000 */\n#define RCC_APB2ENR_SAI1EN                 RCC_APB2ENR_SAI1EN_Msk\n#define RCC_APB2ENR_SAI2EN_Pos             (23U)\n#define RCC_APB2ENR_SAI2EN_Msk             (0x1UL << RCC_APB2ENR_SAI2EN_Pos)    /*!< 0x00800000 */\n#define RCC_APB2ENR_SAI2EN                 RCC_APB2ENR_SAI2EN_Msk\n\n/********************  Bit definition for RCC_AHB1LPENR register  *************/\n#define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)\n#define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk\n#define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)\n#define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk\n#define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)\n#define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */\n#define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk\n#define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)\n#define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */\n#define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk\n#define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)\n#define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */\n#define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk\n#define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)\n#define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */\n#define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk\n#define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)\n#define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk\n#define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)\n#define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk\n#define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)\n#define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */\n#define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk\n#define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)\n#define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */\n#define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk\n#define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)\n#define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */\n#define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk\n#define RCC_AHB1LPENR_SRAM2LPEN_Pos        (17U)\n#define RCC_AHB1LPENR_SRAM2LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */\n#define RCC_AHB1LPENR_SRAM2LPEN            RCC_AHB1LPENR_SRAM2LPEN_Msk\n#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos      (18U)\n#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk      (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */\n#define RCC_AHB1LPENR_BKPSRAMLPEN          RCC_AHB1LPENR_BKPSRAMLPEN_Msk\n#define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)\n#define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk\n#define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)\n#define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk\n\n#define RCC_AHB1LPENR_OTGHSLPEN_Pos        (29U)\n#define RCC_AHB1LPENR_OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */\n#define RCC_AHB1LPENR_OTGHSLPEN            RCC_AHB1LPENR_OTGHSLPEN_Msk\n#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos    (30U)\n#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */\n#define RCC_AHB1LPENR_OTGHSULPILPEN        RCC_AHB1LPENR_OTGHSULPILPEN_Msk\n\n/********************  Bit definition for RCC_AHB2LPENR register  *************/\n#define RCC_AHB2LPENR_DCMILPEN_Pos         (0U)\n#define RCC_AHB2LPENR_DCMILPEN_Msk         (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB2LPENR_DCMILPEN             RCC_AHB2LPENR_DCMILPEN_Msk\n#define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)\n#define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk\n\n/********************  Bit definition for RCC_AHB3LPENR register  *************/\n#define RCC_AHB3LPENR_FMCLPEN_Pos          (0U)\n#define RCC_AHB3LPENR_FMCLPEN_Msk          (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB3LPENR_FMCLPEN              RCC_AHB3LPENR_FMCLPEN_Msk\n#define RCC_AHB3LPENR_QSPILPEN_Pos         (1U)\n#define RCC_AHB3LPENR_QSPILPEN_Msk         (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB3LPENR_QSPILPEN             RCC_AHB3LPENR_QSPILPEN_Msk\n\n/********************  Bit definition for RCC_APB1LPENR register  *************/\n#define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)\n#define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk\n#define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)\n#define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk\n#define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)\n#define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */\n#define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk\n#define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)\n#define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */\n#define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk\n#define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)\n#define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk\n#define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)\n#define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk\n#define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)\n#define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */\n#define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk\n#define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)\n#define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */\n#define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk\n#define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)\n#define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk\n#define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)\n#define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk\n#define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)\n#define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk\n#define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)\n#define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */\n#define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk\n#define RCC_APB1LPENR_SPDIFRXLPEN_Pos      (16U)\n#define RCC_APB1LPENR_SPDIFRXLPEN_Msk      (0x1UL << RCC_APB1LPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */\n#define RCC_APB1LPENR_SPDIFRXLPEN          RCC_APB1LPENR_SPDIFRXLPEN_Msk\n#define RCC_APB1LPENR_USART2LPEN_Pos       (17U)\n#define RCC_APB1LPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk\n#define RCC_APB1LPENR_USART3LPEN_Pos       (18U)\n#define RCC_APB1LPENR_USART3LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk\n#define RCC_APB1LPENR_UART4LPEN_Pos        (19U)\n#define RCC_APB1LPENR_UART4LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */\n#define RCC_APB1LPENR_UART4LPEN            RCC_APB1LPENR_UART4LPEN_Msk\n#define RCC_APB1LPENR_UART5LPEN_Pos        (20U)\n#define RCC_APB1LPENR_UART5LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */\n#define RCC_APB1LPENR_UART5LPEN            RCC_APB1LPENR_UART5LPEN_Msk\n#define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)\n#define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk\n#define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)\n#define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk\n#define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)\n#define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */\n#define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk\n#define RCC_APB1LPENR_FMPI2C1LPEN_Pos      (24U)\n#define RCC_APB1LPENR_FMPI2C1LPEN_Msk      (0x1UL << RCC_APB1LPENR_FMPI2C1LPEN_Pos) /*!< 0x01000000 */\n#define RCC_APB1LPENR_FMPI2C1LPEN          RCC_APB1LPENR_FMPI2C1LPEN_Msk\n#define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)\n#define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */\n#define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk\n#define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)\n#define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */\n#define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk\n#define RCC_APB1LPENR_CECLPEN_Pos          (27U)\n#define RCC_APB1LPENR_CECLPEN_Msk          (0x1UL << RCC_APB1LPENR_CECLPEN_Pos) /*!< 0x08000000 */\n#define RCC_APB1LPENR_CECLPEN              RCC_APB1LPENR_CECLPEN_Msk\n#define RCC_APB1LPENR_PWRLPEN_Pos          (28U)\n#define RCC_APB1LPENR_PWRLPEN_Msk          (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */\n#define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk\n#define RCC_APB1LPENR_DACLPEN_Pos          (29U)\n#define RCC_APB1LPENR_DACLPEN_Msk          (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */\n#define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk\n\n/********************  Bit definition for RCC_APB2LPENR register  *************/\n#define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)\n#define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk\n#define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)\n#define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk\n#define RCC_APB2LPENR_USART1LPEN_Pos       (4U)\n#define RCC_APB2LPENR_USART1LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk\n#define RCC_APB2LPENR_USART6LPEN_Pos       (5U)\n#define RCC_APB2LPENR_USART6LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk\n#define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)\n#define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk\n#define RCC_APB2LPENR_ADC2LPEN_Pos         (9U)\n#define RCC_APB2LPENR_ADC2LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */\n#define RCC_APB2LPENR_ADC2LPEN             RCC_APB2LPENR_ADC2LPEN_Msk\n#define RCC_APB2LPENR_ADC3LPEN_Pos         (10U)\n#define RCC_APB2LPENR_ADC3LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */\n#define RCC_APB2LPENR_ADC3LPEN             RCC_APB2LPENR_ADC3LPEN_Msk\n#define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)\n#define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk\n#define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)\n#define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */\n#define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk\n#define RCC_APB2LPENR_SPI4LPEN_Pos         (13U)\n#define RCC_APB2LPENR_SPI4LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */\n#define RCC_APB2LPENR_SPI4LPEN             RCC_APB2LPENR_SPI4LPEN_Msk\n#define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)\n#define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk\n#define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)\n#define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */\n#define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk\n#define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)\n#define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk\n#define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)\n#define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk\n#define RCC_APB2LPENR_SAI1LPEN_Pos         (22U)\n#define RCC_APB2LPENR_SAI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */\n#define RCC_APB2LPENR_SAI1LPEN             RCC_APB2LPENR_SAI1LPEN_Msk\n#define RCC_APB2LPENR_SAI2LPEN_Pos         (23U)\n#define RCC_APB2LPENR_SAI2LPEN_Msk         (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */\n#define RCC_APB2LPENR_SAI2LPEN             RCC_APB2LPENR_SAI2LPEN_Msk\n\n/********************  Bit definition for RCC_BDCR register  ******************/\n#define RCC_BDCR_LSEON_Pos                 (0U)\n#define RCC_BDCR_LSEON_Msk                 (0x1UL << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */\n#define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk\n#define RCC_BDCR_LSERDY_Pos                (1U)\n#define RCC_BDCR_LSERDY_Msk                (0x1UL << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */\n#define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk\n#define RCC_BDCR_LSEBYP_Pos                (2U)\n#define RCC_BDCR_LSEBYP_Msk                (0x1UL << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */\n#define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk\n#define RCC_BDCR_LSEMOD_Pos                (3U)\n#define RCC_BDCR_LSEMOD_Msk                (0x1UL << RCC_BDCR_LSEMOD_Pos)       /*!< 0x00000008 */\n#define RCC_BDCR_LSEMOD                    RCC_BDCR_LSEMOD_Msk\n\n#define RCC_BDCR_RTCSEL_Pos                (8U)\n#define RCC_BDCR_RTCSEL_Msk                (0x3UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */\n#define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk\n#define RCC_BDCR_RTCSEL_0                  (0x1UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */\n#define RCC_BDCR_RTCSEL_1                  (0x2UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */\n\n#define RCC_BDCR_RTCEN_Pos                 (15U)\n#define RCC_BDCR_RTCEN_Msk                 (0x1UL << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */\n#define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk\n#define RCC_BDCR_BDRST_Pos                 (16U)\n#define RCC_BDCR_BDRST_Msk                 (0x1UL << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */\n#define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk\n\n/********************  Bit definition for RCC_CSR register  *******************/\n#define RCC_CSR_LSION_Pos                  (0U)\n#define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */\n#define RCC_CSR_LSION                      RCC_CSR_LSION_Msk\n#define RCC_CSR_LSIRDY_Pos                 (1U)\n#define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */\n#define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk\n#define RCC_CSR_RMVF_Pos                   (24U)\n#define RCC_CSR_RMVF_Msk                   (0x1UL << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */\n#define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk\n#define RCC_CSR_BORRSTF_Pos                (25U)\n#define RCC_CSR_BORRSTF_Msk                (0x1UL << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */\n#define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk\n#define RCC_CSR_PINRSTF_Pos                (26U)\n#define RCC_CSR_PINRSTF_Msk                (0x1UL << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */\n#define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk\n#define RCC_CSR_PORRSTF_Pos                (27U)\n#define RCC_CSR_PORRSTF_Msk                (0x1UL << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */\n#define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk\n#define RCC_CSR_SFTRSTF_Pos                (28U)\n#define RCC_CSR_SFTRSTF_Msk                (0x1UL << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */\n#define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk\n#define RCC_CSR_IWDGRSTF_Pos               (29U)\n#define RCC_CSR_IWDGRSTF_Msk               (0x1UL << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */\n#define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk\n#define RCC_CSR_WWDGRSTF_Pos               (30U)\n#define RCC_CSR_WWDGRSTF_Msk               (0x1UL << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */\n#define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk\n#define RCC_CSR_LPWRRSTF_Pos               (31U)\n#define RCC_CSR_LPWRRSTF_Msk               (0x1UL << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */\n#define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk\n/* Legacy defines */\n#define RCC_CSR_PADRSTF                    RCC_CSR_PINRSTF\n#define RCC_CSR_WDGRSTF                    RCC_CSR_IWDGRSTF\n\n/********************  Bit definition for RCC_SSCGR register  *****************/\n#define RCC_SSCGR_MODPER_Pos               (0U)\n#define RCC_SSCGR_MODPER_Msk               (0x1FFFUL << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */\n#define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk\n#define RCC_SSCGR_INCSTEP_Pos              (13U)\n#define RCC_SSCGR_INCSTEP_Msk              (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */\n#define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk\n#define RCC_SSCGR_SPREADSEL_Pos            (30U)\n#define RCC_SSCGR_SPREADSEL_Msk            (0x1UL << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */\n#define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk\n#define RCC_SSCGR_SSCGEN_Pos               (31U)\n#define RCC_SSCGR_SSCGEN_Msk               (0x1UL << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */\n#define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk\n\n/********************  Bit definition for RCC_PLLI2SCFGR register  ************/\n#define RCC_PLLI2SCFGR_PLLI2SM_Pos         (0U)\n#define RCC_PLLI2SCFGR_PLLI2SM_Msk         (0x3FUL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */\n#define RCC_PLLI2SCFGR_PLLI2SM             RCC_PLLI2SCFGR_PLLI2SM_Msk\n#define RCC_PLLI2SCFGR_PLLI2SM_0           (0x01UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */\n#define RCC_PLLI2SCFGR_PLLI2SM_1           (0x02UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */\n#define RCC_PLLI2SCFGR_PLLI2SM_2           (0x04UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */\n#define RCC_PLLI2SCFGR_PLLI2SM_3           (0x08UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */\n#define RCC_PLLI2SCFGR_PLLI2SM_4           (0x10UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */\n#define RCC_PLLI2SCFGR_PLLI2SM_5           (0x20UL << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */\n\n#define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)\n#define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */\n#define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk\n#define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */\n#define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */\n#define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */\n#define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */\n#define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */\n#define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */\n#define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */\n\n#define RCC_PLLI2SCFGR_PLLI2SP_Pos         (16U)\n#define RCC_PLLI2SCFGR_PLLI2SP_Msk         (0x3UL << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00030000 */\n#define RCC_PLLI2SCFGR_PLLI2SP             RCC_PLLI2SCFGR_PLLI2SP_Msk\n#define RCC_PLLI2SCFGR_PLLI2SP_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00010000 */\n#define RCC_PLLI2SCFGR_PLLI2SP_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00020000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_Pos         (24U)\n#define RCC_PLLI2SCFGR_PLLI2SQ_Msk         (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ             RCC_PLLI2SCFGR_PLLI2SQ_Msk\n#define RCC_PLLI2SCFGR_PLLI2SQ_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_3           (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)\n#define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk\n#define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for RCC_PLLSAICFGR register  ************/\n#define RCC_PLLSAICFGR_PLLSAIM_Pos         (0U)\n#define RCC_PLLSAICFGR_PLLSAIM_Msk         (0x3FUL << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x0000003F */\n#define RCC_PLLSAICFGR_PLLSAIM             RCC_PLLSAICFGR_PLLSAIM_Msk\n#define RCC_PLLSAICFGR_PLLSAIM_0           (0x01UL << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000001 */\n#define RCC_PLLSAICFGR_PLLSAIM_1           (0x02UL << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000002 */\n#define RCC_PLLSAICFGR_PLLSAIM_2           (0x04UL << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000004 */\n#define RCC_PLLSAICFGR_PLLSAIM_3           (0x08UL << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000008 */\n#define RCC_PLLSAICFGR_PLLSAIM_4           (0x10UL << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000010 */\n#define RCC_PLLSAICFGR_PLLSAIM_5           (0x20UL << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000020 */\n#define RCC_PLLSAICFGR_PLLSAIN_Pos         (6U)\n#define RCC_PLLSAICFGR_PLLSAIN_Msk         (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */\n#define RCC_PLLSAICFGR_PLLSAIN             RCC_PLLSAICFGR_PLLSAIN_Msk\n#define RCC_PLLSAICFGR_PLLSAIN_0           (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */\n#define RCC_PLLSAICFGR_PLLSAIN_1           (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */\n#define RCC_PLLSAICFGR_PLLSAIN_2           (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */\n#define RCC_PLLSAICFGR_PLLSAIN_3           (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */\n#define RCC_PLLSAICFGR_PLLSAIN_4           (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */\n#define RCC_PLLSAICFGR_PLLSAIN_5           (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */\n#define RCC_PLLSAICFGR_PLLSAIN_6           (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */\n#define RCC_PLLSAICFGR_PLLSAIN_7           (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */\n#define RCC_PLLSAICFGR_PLLSAIN_8           (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */\n\n#define RCC_PLLSAICFGR_PLLSAIP_Pos         (16U)\n#define RCC_PLLSAICFGR_PLLSAIP_Msk         (0x3UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */\n#define RCC_PLLSAICFGR_PLLSAIP             RCC_PLLSAICFGR_PLLSAIP_Msk\n#define RCC_PLLSAICFGR_PLLSAIP_0           (0x1UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */\n#define RCC_PLLSAICFGR_PLLSAIP_1           (0x2UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */\n\n#define RCC_PLLSAICFGR_PLLSAIQ_Pos         (24U)\n#define RCC_PLLSAICFGR_PLLSAIQ_Msk         (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */\n#define RCC_PLLSAICFGR_PLLSAIQ             RCC_PLLSAICFGR_PLLSAIQ_Msk\n#define RCC_PLLSAICFGR_PLLSAIQ_0           (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */\n#define RCC_PLLSAICFGR_PLLSAIQ_1           (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */\n#define RCC_PLLSAICFGR_PLLSAIQ_2           (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */\n#define RCC_PLLSAICFGR_PLLSAIQ_3           (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */\n\n\n/********************  Bit definition for RCC_DCKCFGR register  ***************/\n#define RCC_DCKCFGR_PLLI2SDIVQ_Pos        (0U)\n#define RCC_DCKCFGR_PLLI2SDIVQ_Msk        (0x1FUL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */\n#define RCC_DCKCFGR_PLLI2SDIVQ            RCC_DCKCFGR_PLLI2SDIVQ_Msk\n#define RCC_DCKCFGR_PLLI2SDIVQ_0          (0x01UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */\n#define RCC_DCKCFGR_PLLI2SDIVQ_1          (0x02UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */\n#define RCC_DCKCFGR_PLLI2SDIVQ_2          (0x04UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */\n#define RCC_DCKCFGR_PLLI2SDIVQ_3          (0x08UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */\n#define RCC_DCKCFGR_PLLI2SDIVQ_4          (0x10UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */\n\n#define RCC_DCKCFGR_PLLSAIDIVQ_Pos        (8U)\n#define RCC_DCKCFGR_PLLSAIDIVQ_Msk        (0x1FUL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */\n#define RCC_DCKCFGR_PLLSAIDIVQ            RCC_DCKCFGR_PLLSAIDIVQ_Msk\n#define RCC_DCKCFGR_PLLSAIDIVQ_0          (0x01UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */\n#define RCC_DCKCFGR_PLLSAIDIVQ_1          (0x02UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */\n#define RCC_DCKCFGR_PLLSAIDIVQ_2          (0x04UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */\n#define RCC_DCKCFGR_PLLSAIDIVQ_3          (0x08UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */\n#define RCC_DCKCFGR_PLLSAIDIVQ_4          (0x10UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */\n#define RCC_DCKCFGR_SAI1SRC_Pos            (20U)\n#define RCC_DCKCFGR_SAI1SRC_Msk            (0x3UL << RCC_DCKCFGR_SAI1SRC_Pos)   /*!< 0x00300000 */\n#define RCC_DCKCFGR_SAI1SRC                RCC_DCKCFGR_SAI1SRC_Msk\n#define RCC_DCKCFGR_SAI1SRC_0              (0x1UL << RCC_DCKCFGR_SAI1SRC_Pos)   /*!< 0x00100000 */\n#define RCC_DCKCFGR_SAI1SRC_1              (0x2UL << RCC_DCKCFGR_SAI1SRC_Pos)   /*!< 0x00200000 */\n#define RCC_DCKCFGR_SAI2SRC_Pos            (22U)\n#define RCC_DCKCFGR_SAI2SRC_Msk            (0x3UL << RCC_DCKCFGR_SAI2SRC_Pos)   /*!< 0x00C00000 */\n#define RCC_DCKCFGR_SAI2SRC                RCC_DCKCFGR_SAI2SRC_Msk\n#define RCC_DCKCFGR_SAI2SRC_0              (0x1UL << RCC_DCKCFGR_SAI2SRC_Pos)   /*!< 0x00400000 */\n#define RCC_DCKCFGR_SAI2SRC_1              (0x2UL << RCC_DCKCFGR_SAI2SRC_Pos)   /*!< 0x00800000 */\n\n#define RCC_DCKCFGR_TIMPRE_Pos             (24U)\n#define RCC_DCKCFGR_TIMPRE_Msk             (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)    /*!< 0x01000000 */\n#define RCC_DCKCFGR_TIMPRE                 RCC_DCKCFGR_TIMPRE_Msk\n#define RCC_DCKCFGR_I2S1SRC_Pos            (25U)\n#define RCC_DCKCFGR_I2S1SRC_Msk            (0x3UL << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x06000000 */\n#define RCC_DCKCFGR_I2S1SRC                RCC_DCKCFGR_I2S1SRC_Msk\n#define RCC_DCKCFGR_I2S1SRC_0              (0x1UL << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x02000000 */\n#define RCC_DCKCFGR_I2S1SRC_1              (0x2UL << RCC_DCKCFGR_I2S1SRC_Pos)   /*!< 0x04000000 */\n\n#define RCC_DCKCFGR_I2S2SRC_Pos            (27U)\n#define RCC_DCKCFGR_I2S2SRC_Msk            (0x3UL << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x18000000 */\n#define RCC_DCKCFGR_I2S2SRC                RCC_DCKCFGR_I2S2SRC_Msk\n#define RCC_DCKCFGR_I2S2SRC_0              (0x1UL << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x08000000 */\n#define RCC_DCKCFGR_I2S2SRC_1              (0x2UL << RCC_DCKCFGR_I2S2SRC_Pos)   /*!< 0x10000000 */\n\n/********************  Bit definition for RCC_CKGATENR register  ***************/\n#define RCC_CKGATENR_AHB2APB1_CKEN_Pos     (0U)\n#define RCC_CKGATENR_AHB2APB1_CKEN_Msk     (0x1UL << RCC_CKGATENR_AHB2APB1_CKEN_Pos) /*!< 0x00000001 */\n#define RCC_CKGATENR_AHB2APB1_CKEN         RCC_CKGATENR_AHB2APB1_CKEN_Msk\n#define RCC_CKGATENR_AHB2APB2_CKEN_Pos     (1U)\n#define RCC_CKGATENR_AHB2APB2_CKEN_Msk     (0x1UL << RCC_CKGATENR_AHB2APB2_CKEN_Pos) /*!< 0x00000002 */\n#define RCC_CKGATENR_AHB2APB2_CKEN         RCC_CKGATENR_AHB2APB2_CKEN_Msk\n#define RCC_CKGATENR_CM4DBG_CKEN_Pos       (2U)\n#define RCC_CKGATENR_CM4DBG_CKEN_Msk       (0x1UL << RCC_CKGATENR_CM4DBG_CKEN_Pos) /*!< 0x00000004 */\n#define RCC_CKGATENR_CM4DBG_CKEN           RCC_CKGATENR_CM4DBG_CKEN_Msk\n#define RCC_CKGATENR_SPARE_CKEN_Pos        (3U)\n#define RCC_CKGATENR_SPARE_CKEN_Msk        (0x1UL << RCC_CKGATENR_SPARE_CKEN_Pos) /*!< 0x00000008 */\n#define RCC_CKGATENR_SPARE_CKEN            RCC_CKGATENR_SPARE_CKEN_Msk\n#define RCC_CKGATENR_SRAM_CKEN_Pos         (4U)\n#define RCC_CKGATENR_SRAM_CKEN_Msk         (0x1UL << RCC_CKGATENR_SRAM_CKEN_Pos) /*!< 0x00000010 */\n#define RCC_CKGATENR_SRAM_CKEN             RCC_CKGATENR_SRAM_CKEN_Msk\n#define RCC_CKGATENR_FLITF_CKEN_Pos        (5U)\n#define RCC_CKGATENR_FLITF_CKEN_Msk        (0x1UL << RCC_CKGATENR_FLITF_CKEN_Pos) /*!< 0x00000020 */\n#define RCC_CKGATENR_FLITF_CKEN            RCC_CKGATENR_FLITF_CKEN_Msk\n#define RCC_CKGATENR_RCC_CKEN_Pos          (6U)\n#define RCC_CKGATENR_RCC_CKEN_Msk          (0x1UL << RCC_CKGATENR_RCC_CKEN_Pos) /*!< 0x00000040 */\n#define RCC_CKGATENR_RCC_CKEN              RCC_CKGATENR_RCC_CKEN_Msk\n\n/********************  Bit definition for RCC_DCKCFGR2 register  ***************/\n#define RCC_DCKCFGR2_FMPI2C1SEL_Pos        (22U)\n#define RCC_DCKCFGR2_FMPI2C1SEL_Msk        (0x3UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */\n#define RCC_DCKCFGR2_FMPI2C1SEL            RCC_DCKCFGR2_FMPI2C1SEL_Msk\n#define RCC_DCKCFGR2_FMPI2C1SEL_0          (0x1UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */\n#define RCC_DCKCFGR2_FMPI2C1SEL_1          (0x2UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */\n#define RCC_DCKCFGR2_CECSEL_Pos            (26U)\n#define RCC_DCKCFGR2_CECSEL_Msk            (0x1UL << RCC_DCKCFGR2_CECSEL_Pos)   /*!< 0x04000000 */\n#define RCC_DCKCFGR2_CECSEL                RCC_DCKCFGR2_CECSEL_Msk\n#define RCC_DCKCFGR2_CK48MSEL_Pos          (27U)\n#define RCC_DCKCFGR2_CK48MSEL_Msk          (0x1UL << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */\n#define RCC_DCKCFGR2_CK48MSEL              RCC_DCKCFGR2_CK48MSEL_Msk\n#define RCC_DCKCFGR2_SDIOSEL_Pos           (28U)\n#define RCC_DCKCFGR2_SDIOSEL_Msk           (0x1UL << RCC_DCKCFGR2_SDIOSEL_Pos)  /*!< 0x10000000 */\n#define RCC_DCKCFGR2_SDIOSEL               RCC_DCKCFGR2_SDIOSEL_Msk\n#define RCC_DCKCFGR2_SPDIFRXSEL_Pos        (29U)\n#define RCC_DCKCFGR2_SPDIFRXSEL_Msk        (0x1UL << RCC_DCKCFGR2_SPDIFRXSEL_Pos) /*!< 0x20000000 */\n#define RCC_DCKCFGR2_SPDIFRXSEL            RCC_DCKCFGR2_SPDIFRXSEL_Msk\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Real-Time Clock (RTC)                            */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions  (not present on all devices in the STM32F4 serie)\n */\n#define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */\n#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */\n/********************  Bits definition for RTC_TR register  *******************/\n#define RTC_TR_PM_Pos                 (22U)\n#define RTC_TR_PM_Msk                 (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */\n#define RTC_TR_PM                     RTC_TR_PM_Msk\n#define RTC_TR_HT_Pos                 (20U)\n#define RTC_TR_HT_Msk                 (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */\n#define RTC_TR_HT                     RTC_TR_HT_Msk\n#define RTC_TR_HT_0                   (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */\n#define RTC_TR_HT_1                   (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */\n#define RTC_TR_HU_Pos                 (16U)\n#define RTC_TR_HU_Msk                 (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */\n#define RTC_TR_HU                     RTC_TR_HU_Msk\n#define RTC_TR_HU_0                   (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */\n#define RTC_TR_HU_1                   (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */\n#define RTC_TR_HU_2                   (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */\n#define RTC_TR_HU_3                   (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */\n#define RTC_TR_MNT_Pos                (12U)\n#define RTC_TR_MNT_Msk                (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */\n#define RTC_TR_MNT                    RTC_TR_MNT_Msk\n#define RTC_TR_MNT_0                  (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */\n#define RTC_TR_MNT_1                  (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */\n#define RTC_TR_MNT_2                  (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */\n#define RTC_TR_MNU_Pos                (8U)\n#define RTC_TR_MNU_Msk                (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */\n#define RTC_TR_MNU                    RTC_TR_MNU_Msk\n#define RTC_TR_MNU_0                  (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */\n#define RTC_TR_MNU_1                  (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */\n#define RTC_TR_MNU_2                  (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */\n#define RTC_TR_MNU_3                  (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */\n#define RTC_TR_ST_Pos                 (4U)\n#define RTC_TR_ST_Msk                 (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */\n#define RTC_TR_ST                     RTC_TR_ST_Msk\n#define RTC_TR_ST_0                   (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */\n#define RTC_TR_ST_1                   (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */\n#define RTC_TR_ST_2                   (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */\n#define RTC_TR_SU_Pos                 (0U)\n#define RTC_TR_SU_Msk                 (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */\n#define RTC_TR_SU                     RTC_TR_SU_Msk\n#define RTC_TR_SU_0                   (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */\n#define RTC_TR_SU_1                   (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */\n#define RTC_TR_SU_2                   (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */\n#define RTC_TR_SU_3                   (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_DR register  *******************/\n#define RTC_DR_YT_Pos                 (20U)\n#define RTC_DR_YT_Msk                 (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */\n#define RTC_DR_YT                     RTC_DR_YT_Msk\n#define RTC_DR_YT_0                   (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */\n#define RTC_DR_YT_1                   (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */\n#define RTC_DR_YT_2                   (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */\n#define RTC_DR_YT_3                   (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */\n#define RTC_DR_YU_Pos                 (16U)\n#define RTC_DR_YU_Msk                 (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */\n#define RTC_DR_YU                     RTC_DR_YU_Msk\n#define RTC_DR_YU_0                   (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */\n#define RTC_DR_YU_1                   (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */\n#define RTC_DR_YU_2                   (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */\n#define RTC_DR_YU_3                   (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */\n#define RTC_DR_WDU_Pos                (13U)\n#define RTC_DR_WDU_Msk                (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */\n#define RTC_DR_WDU                    RTC_DR_WDU_Msk\n#define RTC_DR_WDU_0                  (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */\n#define RTC_DR_WDU_1                  (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */\n#define RTC_DR_WDU_2                  (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */\n#define RTC_DR_MT_Pos                 (12U)\n#define RTC_DR_MT_Msk                 (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */\n#define RTC_DR_MT                     RTC_DR_MT_Msk\n#define RTC_DR_MU_Pos                 (8U)\n#define RTC_DR_MU_Msk                 (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */\n#define RTC_DR_MU                     RTC_DR_MU_Msk\n#define RTC_DR_MU_0                   (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */\n#define RTC_DR_MU_1                   (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */\n#define RTC_DR_MU_2                   (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */\n#define RTC_DR_MU_3                   (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */\n#define RTC_DR_DT_Pos                 (4U)\n#define RTC_DR_DT_Msk                 (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */\n#define RTC_DR_DT                     RTC_DR_DT_Msk\n#define RTC_DR_DT_0                   (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */\n#define RTC_DR_DT_1                   (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */\n#define RTC_DR_DU_Pos                 (0U)\n#define RTC_DR_DU_Msk                 (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */\n#define RTC_DR_DU                     RTC_DR_DU_Msk\n#define RTC_DR_DU_0                   (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */\n#define RTC_DR_DU_1                   (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */\n#define RTC_DR_DU_2                   (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */\n#define RTC_DR_DU_3                   (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_CR register  *******************/\n#define RTC_CR_COE_Pos                (23U)\n#define RTC_CR_COE_Msk                (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */\n#define RTC_CR_COE                    RTC_CR_COE_Msk\n#define RTC_CR_OSEL_Pos               (21U)\n#define RTC_CR_OSEL_Msk               (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */\n#define RTC_CR_OSEL                   RTC_CR_OSEL_Msk\n#define RTC_CR_OSEL_0                 (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */\n#define RTC_CR_OSEL_1                 (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */\n#define RTC_CR_POL_Pos                (20U)\n#define RTC_CR_POL_Msk                (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */\n#define RTC_CR_POL                    RTC_CR_POL_Msk\n#define RTC_CR_COSEL_Pos              (19U)\n#define RTC_CR_COSEL_Msk              (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */\n#define RTC_CR_COSEL                  RTC_CR_COSEL_Msk\n#define RTC_CR_BKP_Pos                 (18U)\n#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */\n#define RTC_CR_BKP                     RTC_CR_BKP_Msk\n#define RTC_CR_SUB1H_Pos              (17U)\n#define RTC_CR_SUB1H_Msk              (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */\n#define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk\n#define RTC_CR_ADD1H_Pos              (16U)\n#define RTC_CR_ADD1H_Msk              (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */\n#define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk\n#define RTC_CR_TSIE_Pos               (15U)\n#define RTC_CR_TSIE_Msk               (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */\n#define RTC_CR_TSIE                   RTC_CR_TSIE_Msk\n#define RTC_CR_WUTIE_Pos              (14U)\n#define RTC_CR_WUTIE_Msk              (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */\n#define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk\n#define RTC_CR_ALRBIE_Pos             (13U)\n#define RTC_CR_ALRBIE_Msk             (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */\n#define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk\n#define RTC_CR_ALRAIE_Pos             (12U)\n#define RTC_CR_ALRAIE_Msk             (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */\n#define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk\n#define RTC_CR_TSE_Pos                (11U)\n#define RTC_CR_TSE_Msk                (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */\n#define RTC_CR_TSE                    RTC_CR_TSE_Msk\n#define RTC_CR_WUTE_Pos               (10U)\n#define RTC_CR_WUTE_Msk               (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */\n#define RTC_CR_WUTE                   RTC_CR_WUTE_Msk\n#define RTC_CR_ALRBE_Pos              (9U)\n#define RTC_CR_ALRBE_Msk              (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */\n#define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk\n#define RTC_CR_ALRAE_Pos              (8U)\n#define RTC_CR_ALRAE_Msk              (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */\n#define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk\n#define RTC_CR_DCE_Pos                (7U)\n#define RTC_CR_DCE_Msk                (0x1UL << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */\n#define RTC_CR_DCE                    RTC_CR_DCE_Msk\n#define RTC_CR_FMT_Pos                (6U)\n#define RTC_CR_FMT_Msk                (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */\n#define RTC_CR_FMT                    RTC_CR_FMT_Msk\n#define RTC_CR_BYPSHAD_Pos            (5U)\n#define RTC_CR_BYPSHAD_Msk            (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */\n#define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk\n#define RTC_CR_REFCKON_Pos            (4U)\n#define RTC_CR_REFCKON_Msk            (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */\n#define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk\n#define RTC_CR_TSEDGE_Pos             (3U)\n#define RTC_CR_TSEDGE_Msk             (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */\n#define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk\n#define RTC_CR_WUCKSEL_Pos            (0U)\n#define RTC_CR_WUCKSEL_Msk            (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */\n#define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk\n#define RTC_CR_WUCKSEL_0              (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */\n#define RTC_CR_WUCKSEL_1              (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */\n#define RTC_CR_WUCKSEL_2              (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */\n\n/* Legacy defines */\n#define RTC_CR_BCK                     RTC_CR_BKP\n\n/********************  Bits definition for RTC_ISR register  ******************/\n#define RTC_ISR_RECALPF_Pos           (16U)\n#define RTC_ISR_RECALPF_Msk           (0x1UL << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */\n#define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk\n#define RTC_ISR_TAMP1F_Pos            (13U)\n#define RTC_ISR_TAMP1F_Msk            (0x1UL << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */\n#define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk\n#define RTC_ISR_TAMP2F_Pos            (14U)\n#define RTC_ISR_TAMP2F_Msk            (0x1UL << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */\n#define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk\n#define RTC_ISR_TSOVF_Pos             (12U)\n#define RTC_ISR_TSOVF_Msk             (0x1UL << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */\n#define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk\n#define RTC_ISR_TSF_Pos               (11U)\n#define RTC_ISR_TSF_Msk               (0x1UL << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */\n#define RTC_ISR_TSF                   RTC_ISR_TSF_Msk\n#define RTC_ISR_WUTF_Pos              (10U)\n#define RTC_ISR_WUTF_Msk              (0x1UL << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */\n#define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk\n#define RTC_ISR_ALRBF_Pos             (9U)\n#define RTC_ISR_ALRBF_Msk             (0x1UL << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */\n#define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk\n#define RTC_ISR_ALRAF_Pos             (8U)\n#define RTC_ISR_ALRAF_Msk             (0x1UL << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */\n#define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk\n#define RTC_ISR_INIT_Pos              (7U)\n#define RTC_ISR_INIT_Msk              (0x1UL << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */\n#define RTC_ISR_INIT                  RTC_ISR_INIT_Msk\n#define RTC_ISR_INITF_Pos             (6U)\n#define RTC_ISR_INITF_Msk             (0x1UL << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */\n#define RTC_ISR_INITF                 RTC_ISR_INITF_Msk\n#define RTC_ISR_RSF_Pos               (5U)\n#define RTC_ISR_RSF_Msk               (0x1UL << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */\n#define RTC_ISR_RSF                   RTC_ISR_RSF_Msk\n#define RTC_ISR_INITS_Pos             (4U)\n#define RTC_ISR_INITS_Msk             (0x1UL << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */\n#define RTC_ISR_INITS                 RTC_ISR_INITS_Msk\n#define RTC_ISR_SHPF_Pos              (3U)\n#define RTC_ISR_SHPF_Msk              (0x1UL << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */\n#define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk\n#define RTC_ISR_WUTWF_Pos             (2U)\n#define RTC_ISR_WUTWF_Msk             (0x1UL << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */\n#define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk\n#define RTC_ISR_ALRBWF_Pos            (1U)\n#define RTC_ISR_ALRBWF_Msk            (0x1UL << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */\n#define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk\n#define RTC_ISR_ALRAWF_Pos            (0U)\n#define RTC_ISR_ALRAWF_Msk            (0x1UL << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */\n#define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk\n\n/********************  Bits definition for RTC_PRER register  *****************/\n#define RTC_PRER_PREDIV_A_Pos         (16U)\n#define RTC_PRER_PREDIV_A_Msk         (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */\n#define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk\n#define RTC_PRER_PREDIV_S_Pos         (0U)\n#define RTC_PRER_PREDIV_S_Msk         (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */\n#define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk\n\n/********************  Bits definition for RTC_WUTR register  *****************/\n#define RTC_WUTR_WUT_Pos              (0U)\n#define RTC_WUTR_WUT_Msk              (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */\n#define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk\n\n/********************  Bits definition for RTC_CALIBR register  ***************/\n#define RTC_CALIBR_DCS_Pos            (7U)\n#define RTC_CALIBR_DCS_Msk            (0x1UL << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */\n#define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk\n#define RTC_CALIBR_DC_Pos             (0U)\n#define RTC_CALIBR_DC_Msk             (0x1FUL << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */\n#define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk\n\n/********************  Bits definition for RTC_ALRMAR register  ***************/\n#define RTC_ALRMAR_MSK4_Pos           (31U)\n#define RTC_ALRMAR_MSK4_Msk           (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk\n#define RTC_ALRMAR_WDSEL_Pos          (30U)\n#define RTC_ALRMAR_WDSEL_Msk          (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk\n#define RTC_ALRMAR_DT_Pos             (28U)\n#define RTC_ALRMAR_DT_Msk             (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk\n#define RTC_ALRMAR_DT_0               (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMAR_DT_1               (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMAR_DU_Pos             (24U)\n#define RTC_ALRMAR_DU_Msk             (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk\n#define RTC_ALRMAR_DU_0               (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMAR_DU_1               (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMAR_DU_2               (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMAR_DU_3               (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMAR_MSK3_Pos           (23U)\n#define RTC_ALRMAR_MSK3_Msk           (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk\n#define RTC_ALRMAR_PM_Pos             (22U)\n#define RTC_ALRMAR_PM_Msk             (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk\n#define RTC_ALRMAR_HT_Pos             (20U)\n#define RTC_ALRMAR_HT_Msk             (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk\n#define RTC_ALRMAR_HT_0               (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMAR_HT_1               (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMAR_HU_Pos             (16U)\n#define RTC_ALRMAR_HU_Msk             (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk\n#define RTC_ALRMAR_HU_0               (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMAR_HU_1               (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMAR_HU_2               (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMAR_HU_3               (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMAR_MSK2_Pos           (15U)\n#define RTC_ALRMAR_MSK2_Msk           (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk\n#define RTC_ALRMAR_MNT_Pos            (12U)\n#define RTC_ALRMAR_MNT_Msk            (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk\n#define RTC_ALRMAR_MNT_0              (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMAR_MNT_1              (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMAR_MNT_2              (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMAR_MNU_Pos            (8U)\n#define RTC_ALRMAR_MNU_Msk            (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk\n#define RTC_ALRMAR_MNU_0              (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMAR_MNU_1              (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMAR_MNU_2              (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMAR_MNU_3              (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMAR_MSK1_Pos           (7U)\n#define RTC_ALRMAR_MSK1_Msk           (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk\n#define RTC_ALRMAR_ST_Pos             (4U)\n#define RTC_ALRMAR_ST_Msk             (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk\n#define RTC_ALRMAR_ST_0               (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMAR_ST_1               (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMAR_ST_2               (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMAR_SU_Pos             (0U)\n#define RTC_ALRMAR_SU_Msk             (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk\n#define RTC_ALRMAR_SU_0               (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMAR_SU_1               (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMAR_SU_2               (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMAR_SU_3               (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_ALRMBR register  ***************/\n#define RTC_ALRMBR_MSK4_Pos           (31U)\n#define RTC_ALRMBR_MSK4_Msk           (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk\n#define RTC_ALRMBR_WDSEL_Pos          (30U)\n#define RTC_ALRMBR_WDSEL_Msk          (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk\n#define RTC_ALRMBR_DT_Pos             (28U)\n#define RTC_ALRMBR_DT_Msk             (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk\n#define RTC_ALRMBR_DT_0               (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMBR_DT_1               (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMBR_DU_Pos             (24U)\n#define RTC_ALRMBR_DU_Msk             (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk\n#define RTC_ALRMBR_DU_0               (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMBR_DU_1               (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMBR_DU_2               (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMBR_DU_3               (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMBR_MSK3_Pos           (23U)\n#define RTC_ALRMBR_MSK3_Msk           (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk\n#define RTC_ALRMBR_PM_Pos             (22U)\n#define RTC_ALRMBR_PM_Msk             (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk\n#define RTC_ALRMBR_HT_Pos             (20U)\n#define RTC_ALRMBR_HT_Msk             (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk\n#define RTC_ALRMBR_HT_0               (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMBR_HT_1               (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMBR_HU_Pos             (16U)\n#define RTC_ALRMBR_HU_Msk             (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk\n#define RTC_ALRMBR_HU_0               (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMBR_HU_1               (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMBR_HU_2               (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMBR_HU_3               (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMBR_MSK2_Pos           (15U)\n#define RTC_ALRMBR_MSK2_Msk           (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk\n#define RTC_ALRMBR_MNT_Pos            (12U)\n#define RTC_ALRMBR_MNT_Msk            (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk\n#define RTC_ALRMBR_MNT_0              (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMBR_MNT_1              (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMBR_MNT_2              (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMBR_MNU_Pos            (8U)\n#define RTC_ALRMBR_MNU_Msk            (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk\n#define RTC_ALRMBR_MNU_0              (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMBR_MNU_1              (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMBR_MNU_2              (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMBR_MNU_3              (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMBR_MSK1_Pos           (7U)\n#define RTC_ALRMBR_MSK1_Msk           (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk\n#define RTC_ALRMBR_ST_Pos             (4U)\n#define RTC_ALRMBR_ST_Msk             (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk\n#define RTC_ALRMBR_ST_0               (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMBR_ST_1               (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMBR_ST_2               (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMBR_SU_Pos             (0U)\n#define RTC_ALRMBR_SU_Msk             (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk\n#define RTC_ALRMBR_SU_0               (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMBR_SU_1               (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMBR_SU_2               (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMBR_SU_3               (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_WPR register  ******************/\n#define RTC_WPR_KEY_Pos               (0U)\n#define RTC_WPR_KEY_Msk               (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */\n#define RTC_WPR_KEY                   RTC_WPR_KEY_Msk\n\n/********************  Bits definition for RTC_SSR register  ******************/\n#define RTC_SSR_SS_Pos                (0U)\n#define RTC_SSR_SS_Msk                (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */\n#define RTC_SSR_SS                    RTC_SSR_SS_Msk\n\n/********************  Bits definition for RTC_SHIFTR register  ***************/\n#define RTC_SHIFTR_SUBFS_Pos          (0U)\n#define RTC_SHIFTR_SUBFS_Msk          (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */\n#define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk\n#define RTC_SHIFTR_ADD1S_Pos          (31U)\n#define RTC_SHIFTR_ADD1S_Msk          (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */\n#define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk\n\n/********************  Bits definition for RTC_TSTR register  *****************/\n#define RTC_TSTR_PM_Pos               (22U)\n#define RTC_TSTR_PM_Msk               (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */\n#define RTC_TSTR_PM                   RTC_TSTR_PM_Msk\n#define RTC_TSTR_HT_Pos               (20U)\n#define RTC_TSTR_HT_Msk               (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */\n#define RTC_TSTR_HT                   RTC_TSTR_HT_Msk\n#define RTC_TSTR_HT_0                 (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */\n#define RTC_TSTR_HT_1                 (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */\n#define RTC_TSTR_HU_Pos               (16U)\n#define RTC_TSTR_HU_Msk               (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */\n#define RTC_TSTR_HU                   RTC_TSTR_HU_Msk\n#define RTC_TSTR_HU_0                 (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */\n#define RTC_TSTR_HU_1                 (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */\n#define RTC_TSTR_HU_2                 (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */\n#define RTC_TSTR_HU_3                 (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */\n#define RTC_TSTR_MNT_Pos              (12U)\n#define RTC_TSTR_MNT_Msk              (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */\n#define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk\n#define RTC_TSTR_MNT_0                (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */\n#define RTC_TSTR_MNT_1                (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */\n#define RTC_TSTR_MNT_2                (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */\n#define RTC_TSTR_MNU_Pos              (8U)\n#define RTC_TSTR_MNU_Msk              (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */\n#define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk\n#define RTC_TSTR_MNU_0                (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */\n#define RTC_TSTR_MNU_1                (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */\n#define RTC_TSTR_MNU_2                (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */\n#define RTC_TSTR_MNU_3                (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */\n#define RTC_TSTR_ST_Pos               (4U)\n#define RTC_TSTR_ST_Msk               (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */\n#define RTC_TSTR_ST                   RTC_TSTR_ST_Msk\n#define RTC_TSTR_ST_0                 (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */\n#define RTC_TSTR_ST_1                 (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */\n#define RTC_TSTR_ST_2                 (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */\n#define RTC_TSTR_SU_Pos               (0U)\n#define RTC_TSTR_SU_Msk               (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */\n#define RTC_TSTR_SU                   RTC_TSTR_SU_Msk\n#define RTC_TSTR_SU_0                 (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */\n#define RTC_TSTR_SU_1                 (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */\n#define RTC_TSTR_SU_2                 (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */\n#define RTC_TSTR_SU_3                 (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSDR register  *****************/\n#define RTC_TSDR_WDU_Pos              (13U)\n#define RTC_TSDR_WDU_Msk              (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */\n#define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk\n#define RTC_TSDR_WDU_0                (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */\n#define RTC_TSDR_WDU_1                (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */\n#define RTC_TSDR_WDU_2                (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */\n#define RTC_TSDR_MT_Pos               (12U)\n#define RTC_TSDR_MT_Msk               (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */\n#define RTC_TSDR_MT                   RTC_TSDR_MT_Msk\n#define RTC_TSDR_MU_Pos               (8U)\n#define RTC_TSDR_MU_Msk               (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */\n#define RTC_TSDR_MU                   RTC_TSDR_MU_Msk\n#define RTC_TSDR_MU_0                 (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */\n#define RTC_TSDR_MU_1                 (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */\n#define RTC_TSDR_MU_2                 (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */\n#define RTC_TSDR_MU_3                 (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */\n#define RTC_TSDR_DT_Pos               (4U)\n#define RTC_TSDR_DT_Msk               (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */\n#define RTC_TSDR_DT                   RTC_TSDR_DT_Msk\n#define RTC_TSDR_DT_0                 (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */\n#define RTC_TSDR_DT_1                 (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */\n#define RTC_TSDR_DU_Pos               (0U)\n#define RTC_TSDR_DU_Msk               (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */\n#define RTC_TSDR_DU                   RTC_TSDR_DU_Msk\n#define RTC_TSDR_DU_0                 (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */\n#define RTC_TSDR_DU_1                 (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */\n#define RTC_TSDR_DU_2                 (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */\n#define RTC_TSDR_DU_3                 (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSSSR register  ****************/\n#define RTC_TSSSR_SS_Pos              (0U)\n#define RTC_TSSSR_SS_Msk              (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */\n#define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk\n\n/********************  Bits definition for RTC_CAL register  *****************/\n#define RTC_CALR_CALP_Pos             (15U)\n#define RTC_CALR_CALP_Msk             (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */\n#define RTC_CALR_CALP                 RTC_CALR_CALP_Msk\n#define RTC_CALR_CALW8_Pos            (14U)\n#define RTC_CALR_CALW8_Msk            (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */\n#define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk\n#define RTC_CALR_CALW16_Pos           (13U)\n#define RTC_CALR_CALW16_Msk           (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */\n#define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk\n#define RTC_CALR_CALM_Pos             (0U)\n#define RTC_CALR_CALM_Msk             (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */\n#define RTC_CALR_CALM                 RTC_CALR_CALM_Msk\n#define RTC_CALR_CALM_0               (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */\n#define RTC_CALR_CALM_1               (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */\n#define RTC_CALR_CALM_2               (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */\n#define RTC_CALR_CALM_3               (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */\n#define RTC_CALR_CALM_4               (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */\n#define RTC_CALR_CALM_5               (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */\n#define RTC_CALR_CALM_6               (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */\n#define RTC_CALR_CALM_7               (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */\n#define RTC_CALR_CALM_8               (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */\n\n/********************  Bits definition for RTC_TAFCR register  ****************/\n#define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)\n#define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */\n#define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk\n#define RTC_TAFCR_TSINSEL_Pos         (17U)\n#define RTC_TAFCR_TSINSEL_Msk         (0x1UL << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */\n#define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk\n#define RTC_TAFCR_TAMP1INSEL_Pos      (16U)\n#define RTC_TAFCR_TAMP1INSEL_Msk      (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)        /*!< 0x00010000 */\n#define RTC_TAFCR_TAMP1INSEL          RTC_TAFCR_TAMP1INSEL_Msk\n#define RTC_TAFCR_TAMPPUDIS_Pos       (15U)\n#define RTC_TAFCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */\n#define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk\n#define RTC_TAFCR_TAMPPRCH_Pos        (13U)\n#define RTC_TAFCR_TAMPPRCH_Msk        (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */\n#define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk\n#define RTC_TAFCR_TAMPPRCH_0          (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */\n#define RTC_TAFCR_TAMPPRCH_1          (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */\n#define RTC_TAFCR_TAMPFLT_Pos         (11U)\n#define RTC_TAFCR_TAMPFLT_Msk         (0x3UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */\n#define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk\n#define RTC_TAFCR_TAMPFLT_0           (0x1UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */\n#define RTC_TAFCR_TAMPFLT_1           (0x2UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */\n#define RTC_TAFCR_TAMPFREQ_Pos        (8U)\n#define RTC_TAFCR_TAMPFREQ_Msk        (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */\n#define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk\n#define RTC_TAFCR_TAMPFREQ_0          (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */\n#define RTC_TAFCR_TAMPFREQ_1          (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */\n#define RTC_TAFCR_TAMPFREQ_2          (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */\n#define RTC_TAFCR_TAMPTS_Pos          (7U)\n#define RTC_TAFCR_TAMPTS_Msk          (0x1UL << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */\n#define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk\n#define RTC_TAFCR_TAMP2TRG_Pos        (4U)\n#define RTC_TAFCR_TAMP2TRG_Msk        (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */\n#define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk\n#define RTC_TAFCR_TAMP2E_Pos          (3U)\n#define RTC_TAFCR_TAMP2E_Msk          (0x1UL << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */\n#define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk\n#define RTC_TAFCR_TAMPIE_Pos          (2U)\n#define RTC_TAFCR_TAMPIE_Msk          (0x1UL << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */\n#define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk\n#define RTC_TAFCR_TAMP1TRG_Pos        (1U)\n#define RTC_TAFCR_TAMP1TRG_Msk        (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */\n#define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk\n#define RTC_TAFCR_TAMP1E_Pos          (0U)\n#define RTC_TAFCR_TAMP1E_Msk          (0x1UL << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */\n#define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk\n\n/* Legacy defines */\n#define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMP1INSEL\n\n/********************  Bits definition for RTC_ALRMASSR register  *************/\n#define RTC_ALRMASSR_MASKSS_Pos       (24U)\n#define RTC_ALRMASSR_MASKSS_Msk       (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk\n#define RTC_ALRMASSR_MASKSS_0         (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMASSR_MASKSS_1         (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMASSR_MASKSS_2         (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMASSR_MASKSS_3         (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMASSR_SS_Pos           (0U)\n#define RTC_ALRMASSR_SS_Msk           (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk\n\n/********************  Bits definition for RTC_ALRMBSSR register  *************/\n#define RTC_ALRMBSSR_MASKSS_Pos       (24U)\n#define RTC_ALRMBSSR_MASKSS_Msk       (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk\n#define RTC_ALRMBSSR_MASKSS_0         (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMBSSR_MASKSS_1         (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMBSSR_MASKSS_2         (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMBSSR_MASKSS_3         (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMBSSR_SS_Pos           (0U)\n#define RTC_ALRMBSSR_SS_Msk           (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk\n\n/********************  Bits definition for RTC_BKP0R register  ****************/\n#define RTC_BKP0R_Pos                 (0U)\n#define RTC_BKP0R_Msk                 (0xFFFFFFFFUL << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP0R                     RTC_BKP0R_Msk\n\n/********************  Bits definition for RTC_BKP1R register  ****************/\n#define RTC_BKP1R_Pos                 (0U)\n#define RTC_BKP1R_Msk                 (0xFFFFFFFFUL << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP1R                     RTC_BKP1R_Msk\n\n/********************  Bits definition for RTC_BKP2R register  ****************/\n#define RTC_BKP2R_Pos                 (0U)\n#define RTC_BKP2R_Msk                 (0xFFFFFFFFUL << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP2R                     RTC_BKP2R_Msk\n\n/********************  Bits definition for RTC_BKP3R register  ****************/\n#define RTC_BKP3R_Pos                 (0U)\n#define RTC_BKP3R_Msk                 (0xFFFFFFFFUL << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP3R                     RTC_BKP3R_Msk\n\n/********************  Bits definition for RTC_BKP4R register  ****************/\n#define RTC_BKP4R_Pos                 (0U)\n#define RTC_BKP4R_Msk                 (0xFFFFFFFFUL << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP4R                     RTC_BKP4R_Msk\n\n/********************  Bits definition for RTC_BKP5R register  ****************/\n#define RTC_BKP5R_Pos                 (0U)\n#define RTC_BKP5R_Msk                 (0xFFFFFFFFUL << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP5R                     RTC_BKP5R_Msk\n\n/********************  Bits definition for RTC_BKP6R register  ****************/\n#define RTC_BKP6R_Pos                 (0U)\n#define RTC_BKP6R_Msk                 (0xFFFFFFFFUL << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP6R                     RTC_BKP6R_Msk\n\n/********************  Bits definition for RTC_BKP7R register  ****************/\n#define RTC_BKP7R_Pos                 (0U)\n#define RTC_BKP7R_Msk                 (0xFFFFFFFFUL << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP7R                     RTC_BKP7R_Msk\n\n/********************  Bits definition for RTC_BKP8R register  ****************/\n#define RTC_BKP8R_Pos                 (0U)\n#define RTC_BKP8R_Msk                 (0xFFFFFFFFUL << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP8R                     RTC_BKP8R_Msk\n\n/********************  Bits definition for RTC_BKP9R register  ****************/\n#define RTC_BKP9R_Pos                 (0U)\n#define RTC_BKP9R_Msk                 (0xFFFFFFFFUL << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP9R                     RTC_BKP9R_Msk\n\n/********************  Bits definition for RTC_BKP10R register  ***************/\n#define RTC_BKP10R_Pos                (0U)\n#define RTC_BKP10R_Msk                (0xFFFFFFFFUL << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP10R                    RTC_BKP10R_Msk\n\n/********************  Bits definition for RTC_BKP11R register  ***************/\n#define RTC_BKP11R_Pos                (0U)\n#define RTC_BKP11R_Msk                (0xFFFFFFFFUL << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP11R                    RTC_BKP11R_Msk\n\n/********************  Bits definition for RTC_BKP12R register  ***************/\n#define RTC_BKP12R_Pos                (0U)\n#define RTC_BKP12R_Msk                (0xFFFFFFFFUL << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP12R                    RTC_BKP12R_Msk\n\n/********************  Bits definition for RTC_BKP13R register  ***************/\n#define RTC_BKP13R_Pos                (0U)\n#define RTC_BKP13R_Msk                (0xFFFFFFFFUL << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP13R                    RTC_BKP13R_Msk\n\n/********************  Bits definition for RTC_BKP14R register  ***************/\n#define RTC_BKP14R_Pos                (0U)\n#define RTC_BKP14R_Msk                (0xFFFFFFFFUL << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP14R                    RTC_BKP14R_Msk\n\n/********************  Bits definition for RTC_BKP15R register  ***************/\n#define RTC_BKP15R_Pos                (0U)\n#define RTC_BKP15R_Msk                (0xFFFFFFFFUL << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP15R                    RTC_BKP15R_Msk\n\n/********************  Bits definition for RTC_BKP16R register  ***************/\n#define RTC_BKP16R_Pos                (0U)\n#define RTC_BKP16R_Msk                (0xFFFFFFFFUL << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP16R                    RTC_BKP16R_Msk\n\n/********************  Bits definition for RTC_BKP17R register  ***************/\n#define RTC_BKP17R_Pos                (0U)\n#define RTC_BKP17R_Msk                (0xFFFFFFFFUL << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP17R                    RTC_BKP17R_Msk\n\n/********************  Bits definition for RTC_BKP18R register  ***************/\n#define RTC_BKP18R_Pos                (0U)\n#define RTC_BKP18R_Msk                (0xFFFFFFFFUL << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP18R                    RTC_BKP18R_Msk\n\n/********************  Bits definition for RTC_BKP19R register  ***************/\n#define RTC_BKP19R_Pos                (0U)\n#define RTC_BKP19R_Msk                (0xFFFFFFFFUL << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP19R                    RTC_BKP19R_Msk\n\n/******************** Number of backup registers ******************************/\n#define RTC_BKP_NUMBER                       0x000000014U\n\n/******************************************************************************/\n/*                                                                            */\n/*                          Serial Audio Interface                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for SAI_GCR register  *******************/\n#define SAI_GCR_SYNCIN_Pos         (0U)\n#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */\n#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */\n#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */\n#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */\n\n#define SAI_GCR_SYNCOUT_Pos        (4U)\n#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */\n#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\n#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */\n#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */\n\n/*******************  Bit definition for SAI_xCR1 register  *******************/\n#define SAI_xCR1_MODE_Pos          (0U)\n#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */\n#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */\n#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */\n#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */\n\n#define SAI_xCR1_PRTCFG_Pos        (2U)\n#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */\n#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */\n#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */\n#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */\n\n#define SAI_xCR1_DS_Pos            (5U)\n#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */\n#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */\n#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */\n#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */\n#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */\n\n#define SAI_xCR1_LSBFIRST_Pos      (8U)\n#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */\n#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */\n#define SAI_xCR1_CKSTR_Pos         (9U)\n#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */\n#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */\n\n#define SAI_xCR1_SYNCEN_Pos        (10U)\n#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */\n#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */\n#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */\n#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */\n\n#define SAI_xCR1_MONO_Pos          (12U)\n#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */\n#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */\n#define SAI_xCR1_OUTDRIV_Pos       (13U)\n#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */\n#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */\n#define SAI_xCR1_SAIEN_Pos         (16U)\n#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */\n#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */\n#define SAI_xCR1_DMAEN_Pos         (17U)\n#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */\n#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */\n#define SAI_xCR1_NODIV_Pos         (19U)\n#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */\n#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */\n\n#define SAI_xCR1_MCKDIV_Pos        (20U)\n#define SAI_xCR1_MCKDIV_Msk        (0xFUL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */\n#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */\n#define SAI_xCR1_MCKDIV_0          (0x1UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00100000 */\n#define SAI_xCR1_MCKDIV_1          (0x2UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00200000 */\n#define SAI_xCR1_MCKDIV_2          (0x4UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00400000 */\n#define SAI_xCR1_MCKDIV_3          (0x8UL << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00800000 */\n\n/*******************  Bit definition for SAI_xCR2 register  *******************/\n#define SAI_xCR2_FTH_Pos           (0U)\n#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */\n#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */\n#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */\n#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */\n#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */\n\n#define SAI_xCR2_FFLUSH_Pos        (3U)\n#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */\n#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */\n#define SAI_xCR2_TRIS_Pos          (4U)\n#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */\n#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */\n#define SAI_xCR2_MUTE_Pos          (5U)\n#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */\n#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */\n#define SAI_xCR2_MUTEVAL_Pos       (6U)\n#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */\n#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */\n\n#define SAI_xCR2_MUTECNT_Pos       (7U)\n#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */\n#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */\n#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */\n#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */\n#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */\n#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */\n#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */\n#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */\n\n#define SAI_xCR2_CPL_Pos           (13U)\n#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */\n#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */\n\n#define SAI_xCR2_COMP_Pos          (14U)\n#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */\n#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */\n#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */\n#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */\n\n/******************  Bit definition for SAI_xFRCR register  *******************/\n#define SAI_xFRCR_FRL_Pos          (0U)\n#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */\n#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */\n#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */\n#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */\n#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */\n#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */\n#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */\n#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */\n#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */\n#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */\n\n#define SAI_xFRCR_FSALL_Pos        (8U)\n#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */\n#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */\n#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */\n#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */\n#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */\n#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */\n#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */\n#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */\n#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */\n\n#define SAI_xFRCR_FSDEF_Pos        (16U)\n#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */\n#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */\n#define SAI_xFRCR_FSPOL_Pos        (17U)\n#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */\n#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */\n#define SAI_xFRCR_FSOFF_Pos        (18U)\n#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */\n#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */\n/* Legacy defines */\n#define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL\n\n/******************  Bit definition for SAI_xSLOTR register  *******************/\n#define SAI_xSLOTR_FBOFF_Pos       (0U)\n#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */\n#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */\n#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */\n#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */\n#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */\n#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */\n#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */\n\n#define SAI_xSLOTR_SLOTSZ_Pos      (6U)\n#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */\n#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */\n#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */\n#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */\n\n#define SAI_xSLOTR_NBSLOT_Pos      (8U)\n#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */\n#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */\n#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */\n#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */\n#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */\n#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */\n\n#define SAI_xSLOTR_SLOTEN_Pos      (16U)\n#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */\n#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */\n\n/*******************  Bit definition for SAI_xIMR register  *******************/\n#define SAI_xIMR_OVRUDRIE_Pos      (0U)\n#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */\n#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */\n#define SAI_xIMR_MUTEDETIE_Pos     (1U)\n#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */\n#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */\n#define SAI_xIMR_WCKCFGIE_Pos      (2U)\n#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */\n#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */\n#define SAI_xIMR_FREQIE_Pos        (3U)\n#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */\n#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */\n#define SAI_xIMR_CNRDYIE_Pos       (4U)\n#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */\n#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */\n#define SAI_xIMR_AFSDETIE_Pos      (5U)\n#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */\n#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */\n#define SAI_xIMR_LFSDETIE_Pos      (6U)\n#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */\n#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */\n\n/********************  Bit definition for SAI_xSR register  *******************/\n#define SAI_xSR_OVRUDR_Pos         (0U)\n#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */\n#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */\n#define SAI_xSR_MUTEDET_Pos        (1U)\n#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */\n#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */\n#define SAI_xSR_WCKCFG_Pos         (2U)\n#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */\n#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */\n#define SAI_xSR_FREQ_Pos           (3U)\n#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */\n#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */\n#define SAI_xSR_CNRDY_Pos          (4U)\n#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */\n#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */\n#define SAI_xSR_AFSDET_Pos         (5U)\n#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */\n#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */\n#define SAI_xSR_LFSDET_Pos         (6U)\n#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */\n#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */\n\n#define SAI_xSR_FLVL_Pos           (16U)\n#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */\n#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */\n#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */\n#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */\n#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */\n\n/******************  Bit definition for SAI_xCLRFR register  ******************/\n#define SAI_xCLRFR_COVRUDR_Pos     (0U)\n#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */\n#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */\n#define SAI_xCLRFR_CMUTEDET_Pos    (1U)\n#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */\n#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */\n#define SAI_xCLRFR_CWCKCFG_Pos     (2U)\n#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */\n#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */\n#define SAI_xCLRFR_CFREQ_Pos       (3U)\n#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */\n#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */\n#define SAI_xCLRFR_CCNRDY_Pos      (4U)\n#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */\n#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */\n#define SAI_xCLRFR_CAFSDET_Pos     (5U)\n#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */\n#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */\n#define SAI_xCLRFR_CLFSDET_Pos     (6U)\n#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */\n#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */\n\n/******************  Bit definition for SAI_xDR register  ******************/\n#define SAI_xDR_DATA_Pos           (0U)\n#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */\n#define SAI_xDR_DATA               SAI_xDR_DATA_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                              SPDIF-RX Interface                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for SPDIFRX_CR register  *******************/\n#define SPDIFRX_CR_SPDIFEN_Pos      (0U)\n#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)           /*!< 0x00000003 */\n#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */\n#define SPDIFRX_CR_RXDMAEN_Pos      (2U)\n#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)           /*!< 0x00000004 */\n#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */\n#define SPDIFRX_CR_RXSTEO_Pos       (3U)\n#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)            /*!< 0x00000008 */\n#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */\n#define SPDIFRX_CR_DRFMT_Pos        (4U)\n#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)             /*!< 0x00000030 */\n#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */\n#define SPDIFRX_CR_PMSK_Pos         (6U)\n#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)              /*!< 0x00000040 */\n#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */\n#define SPDIFRX_CR_VMSK_Pos         (7U)\n#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)              /*!< 0x00000080 */\n#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */\n#define SPDIFRX_CR_CUMSK_Pos        (8U)\n#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)             /*!< 0x00000100 */\n#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */\n#define SPDIFRX_CR_PTMSK_Pos        (9U)\n#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)             /*!< 0x00000200 */\n#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */\n#define SPDIFRX_CR_CBDMAEN_Pos      (10U)\n#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)           /*!< 0x00000400 */\n#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */\n#define SPDIFRX_CR_CHSEL_Pos        (11U)\n#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)             /*!< 0x00000800 */\n#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */\n#define SPDIFRX_CR_NBTR_Pos         (12U)\n#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)              /*!< 0x00003000 */\n#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */\n#define SPDIFRX_CR_WFA_Pos          (14U)\n#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)               /*!< 0x00004000 */\n#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */\n#define SPDIFRX_CR_INSEL_Pos        (16U)\n#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)             /*!< 0x00070000 */\n#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIFRX input selection */\n\n/*******************  Bit definition for SPDIFRX_IMR register  *******************/\n#define SPDIFRX_IMR_RXNEIE_Pos      (0U)\n#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)           /*!< 0x00000001 */\n#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */\n#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)\n#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)          /*!< 0x00000002 */\n#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */\n#define SPDIFRX_IMR_PERRIE_Pos      (2U)\n#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)           /*!< 0x00000004 */\n#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */\n#define SPDIFRX_IMR_OVRIE_Pos       (3U)\n#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)            /*!< 0x00000008 */\n#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */\n#define SPDIFRX_IMR_SBLKIE_Pos      (4U)\n#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)           /*!< 0x00000010 */\n#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */\n#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)\n#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)          /*!< 0x00000020 */\n#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */\n#define SPDIFRX_IMR_IFEIE_Pos       (6U)\n#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)            /*!< 0x00000040 */\n#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */\n\n/*******************  Bit definition for SPDIFRX_SR register  *******************/\n#define SPDIFRX_SR_RXNE_Pos         (0U)\n#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)              /*!< 0x00000001 */\n#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */\n#define SPDIFRX_SR_CSRNE_Pos        (1U)\n#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)             /*!< 0x00000002 */\n#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */\n#define SPDIFRX_SR_PERR_Pos         (2U)\n#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)              /*!< 0x00000004 */\n#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */\n#define SPDIFRX_SR_OVR_Pos          (3U)\n#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)               /*!< 0x00000008 */\n#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */\n#define SPDIFRX_SR_SBD_Pos          (4U)\n#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)               /*!< 0x00000010 */\n#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */\n#define SPDIFRX_SR_SYNCD_Pos        (5U)\n#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)             /*!< 0x00000020 */\n#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */\n#define SPDIFRX_SR_FERR_Pos         (6U)\n#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)              /*!< 0x00000040 */\n#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */\n#define SPDIFRX_SR_SERR_Pos         (7U)\n#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)              /*!< 0x00000080 */\n#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */\n#define SPDIFRX_SR_TERR_Pos         (8U)\n#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)              /*!< 0x00000100 */\n#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */\n#define SPDIFRX_SR_WIDTH5_Pos       (16U)\n#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)         /*!< 0x7FFF0000 */\n#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with SPDIFRX_clk        */\n\n/*******************  Bit definition for SPDIFRX_IFCR register  *******************/\n#define SPDIFRX_IFCR_PERRCF_Pos     (2U)\n#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)          /*!< 0x00000004 */\n#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */\n#define SPDIFRX_IFCR_OVRCF_Pos      (3U)\n#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)           /*!< 0x00000008 */\n#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */\n#define SPDIFRX_IFCR_SBDCF_Pos      (4U)\n#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)           /*!< 0x00000010 */\n#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */\n#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)\n#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)         /*!< 0x00000020 */\n#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */\n\n/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/\n#define SPDIFRX_DR0_DR_Pos          (0U)\n#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)          /*!< 0x00FFFFFF */\n#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */\n#define SPDIFRX_DR0_PE_Pos          (24U)\n#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)               /*!< 0x01000000 */\n#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */\n#define SPDIFRX_DR0_V_Pos           (25U)\n#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)                /*!< 0x02000000 */\n#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */\n#define SPDIFRX_DR0_U_Pos           (26U)\n#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)                /*!< 0x04000000 */\n#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */\n#define SPDIFRX_DR0_C_Pos           (27U)\n#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)                /*!< 0x08000000 */\n#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */\n#define SPDIFRX_DR0_PT_Pos          (28U)\n#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)               /*!< 0x30000000 */\n#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */\n\n/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/\n#define SPDIFRX_DR1_DR_Pos          (8U)\n#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)          /*!< 0xFFFFFF00 */\n#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */\n#define SPDIFRX_DR1_PT_Pos          (4U)\n#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)               /*!< 0x00000030 */\n#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */\n#define SPDIFRX_DR1_C_Pos           (3U)\n#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)                /*!< 0x00000008 */\n#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */\n#define SPDIFRX_DR1_U_Pos           (2U)\n#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)                /*!< 0x00000004 */\n#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */\n#define SPDIFRX_DR1_V_Pos           (1U)\n#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)                /*!< 0x00000002 */\n#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */\n#define SPDIFRX_DR1_PE_Pos          (0U)\n#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)               /*!< 0x00000001 */\n#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */\n\n/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/\n#define SPDIFRX_DR1_DRNL1_Pos       (16U)\n#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)         /*!< 0xFFFF0000 */\n#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */\n#define SPDIFRX_DR1_DRNL2_Pos       (0U)\n#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)         /*!< 0x0000FFFF */\n#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */\n\n/*******************  Bit definition for SPDIFRX_CSR register   *******************/\n#define SPDIFRX_CSR_USR_Pos         (0U)\n#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)           /*!< 0x0000FFFF */\n#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */\n#define SPDIFRX_CSR_CS_Pos          (16U)\n#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)              /*!< 0x00FF0000 */\n#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */\n#define SPDIFRX_CSR_SOB_Pos         (24U)\n#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)              /*!< 0x01000000 */\n#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */\n\n/*******************  Bit definition for SPDIFRX_DIR register    *******************/\n#define SPDIFRX_DIR_THI_Pos         (0U)\n#define SPDIFRX_DIR_THI_Msk         (0x13FFUL << SPDIFRX_DIR_THI_Pos)           /*!< 0x000013FF */\n#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */\n#define SPDIFRX_DIR_TLO_Pos         (16U)\n#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)           /*!< 0x1FFF0000 */\n#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                          SD host Interface                                 */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SDIO_POWER register  ******************/\n#define SDIO_POWER_PWRCTRL_Pos         (0U)\n#define SDIO_POWER_PWRCTRL_Msk         (0x3UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */\n#define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */\n#define SDIO_POWER_PWRCTRL_0           (0x1UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x01 */\n#define SDIO_POWER_PWRCTRL_1           (0x2UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x02 */\n\n/******************  Bit definition for SDIO_CLKCR register  ******************/\n#define SDIO_CLKCR_CLKDIV_Pos          (0U)\n#define SDIO_CLKCR_CLKDIV_Msk          (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */\n#define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor             */\n#define SDIO_CLKCR_CLKEN_Pos           (8U)\n#define SDIO_CLKCR_CLKEN_Msk           (0x1UL << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */\n#define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit                */\n#define SDIO_CLKCR_PWRSAV_Pos          (9U)\n#define SDIO_CLKCR_PWRSAV_Msk          (0x1UL << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */\n#define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit  */\n#define SDIO_CLKCR_BYPASS_Pos          (10U)\n#define SDIO_CLKCR_BYPASS_Msk          (0x1UL << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */\n#define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */\n\n#define SDIO_CLKCR_WIDBUS_Pos          (11U)\n#define SDIO_CLKCR_WIDBUS_Msk          (0x3UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */\n#define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\n#define SDIO_CLKCR_WIDBUS_0            (0x1UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x0800 */\n#define SDIO_CLKCR_WIDBUS_1            (0x2UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x1000 */\n\n#define SDIO_CLKCR_NEGEDGE_Pos         (13U)\n#define SDIO_CLKCR_NEGEDGE_Msk         (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */\n#define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */\n#define SDIO_CLKCR_HWFC_EN_Pos         (14U)\n#define SDIO_CLKCR_HWFC_EN_Msk         (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */\n#define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable          */\n\n/*******************  Bit definition for SDIO_ARG register  *******************/\n#define SDIO_ARG_CMDARG_Pos            (0U)\n#define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */\n#define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */\n\n/*******************  Bit definition for SDIO_CMD register  *******************/\n#define SDIO_CMD_CMDINDEX_Pos          (0U)\n#define SDIO_CMD_CMDINDEX_Msk          (0x3FUL << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */\n#define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index                               */\n\n#define SDIO_CMD_WAITRESP_Pos          (6U)\n#define SDIO_CMD_WAITRESP_Msk          (0x3UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */\n#define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */\n#define SDIO_CMD_WAITRESP_0            (0x1UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0040 */\n#define SDIO_CMD_WAITRESP_1            (0x2UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0080 */\n\n#define SDIO_CMD_WAITINT_Pos           (8U)\n#define SDIO_CMD_WAITINT_Msk           (0x1UL << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */\n#define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request                               */\n#define SDIO_CMD_WAITPEND_Pos          (9U)\n#define SDIO_CMD_WAITPEND_Msk          (0x1UL << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */\n#define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\n#define SDIO_CMD_CPSMEN_Pos            (10U)\n#define SDIO_CMD_CPSMEN_Msk            (0x1UL << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */\n#define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit                   */\n#define SDIO_CMD_SDIOSUSPEND_Pos       (11U)\n#define SDIO_CMD_SDIOSUSPEND_Msk       (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */\n#define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command                                         */\n\n/*****************  Bit definition for SDIO_RESPCMD register  *****************/\n#define SDIO_RESPCMD_RESPCMD_Pos       (0U)\n#define SDIO_RESPCMD_RESPCMD_Msk       (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */\n#define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */\n\n/******************  Bit definition for SDIO_RESP0 register  ******************/\n#define SDIO_RESP0_CARDSTATUS0_Pos     (0U)\n#define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP1 register  ******************/\n#define SDIO_RESP1_CARDSTATUS1_Pos     (0U)\n#define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP2 register  ******************/\n#define SDIO_RESP2_CARDSTATUS2_Pos     (0U)\n#define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP3 register  ******************/\n#define SDIO_RESP3_CARDSTATUS3_Pos     (0U)\n#define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP4 register  ******************/\n#define SDIO_RESP4_CARDSTATUS4_Pos     (0U)\n#define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_DTIMER register  *****************/\n#define SDIO_DTIMER_DATATIME_Pos       (0U)\n#define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */\n\n/******************  Bit definition for SDIO_DLEN register  *******************/\n#define SDIO_DLEN_DATALENGTH_Pos       (0U)\n#define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */\n\n/******************  Bit definition for SDIO_DCTRL register  ******************/\n#define SDIO_DCTRL_DTEN_Pos            (0U)\n#define SDIO_DCTRL_DTEN_Msk            (0x1UL << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */\n#define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit         */\n#define SDIO_DCTRL_DTDIR_Pos           (1U)\n#define SDIO_DCTRL_DTDIR_Msk           (0x1UL << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */\n#define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */\n#define SDIO_DCTRL_DTMODE_Pos          (2U)\n#define SDIO_DCTRL_DTMODE_Msk          (0x1UL << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */\n#define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection      */\n#define SDIO_DCTRL_DMAEN_Pos           (3U)\n#define SDIO_DCTRL_DMAEN_Msk           (0x1UL << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */\n#define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit                   */\n\n#define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)\n#define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */\n#define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */\n#define SDIO_DCTRL_DBLOCKSIZE_0        (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0010 */\n#define SDIO_DCTRL_DBLOCKSIZE_1        (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0020 */\n#define SDIO_DCTRL_DBLOCKSIZE_2        (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0040 */\n#define SDIO_DCTRL_DBLOCKSIZE_3        (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0080 */\n\n#define SDIO_DCTRL_RWSTART_Pos         (8U)\n#define SDIO_DCTRL_RWSTART_Msk         (0x1UL << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */\n#define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start         */\n#define SDIO_DCTRL_RWSTOP_Pos          (9U)\n#define SDIO_DCTRL_RWSTOP_Msk          (0x1UL << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */\n#define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop          */\n#define SDIO_DCTRL_RWMOD_Pos           (10U)\n#define SDIO_DCTRL_RWMOD_Msk           (0x1UL << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */\n#define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode          */\n#define SDIO_DCTRL_SDIOEN_Pos          (11U)\n#define SDIO_DCTRL_SDIOEN_Msk          (0x1UL << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */\n#define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */\n\n/******************  Bit definition for SDIO_DCOUNT register  *****************/\n#define SDIO_DCOUNT_DATACOUNT_Pos      (0U)\n#define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */\n\n/******************  Bit definition for SDIO_STA register  ********************/\n#define SDIO_STA_CCRCFAIL_Pos          (0U)\n#define SDIO_STA_CCRCFAIL_Msk          (0x1UL << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */\n#define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */\n#define SDIO_STA_DCRCFAIL_Pos          (1U)\n#define SDIO_STA_DCRCFAIL_Msk          (0x1UL << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */\n#define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */\n#define SDIO_STA_CTIMEOUT_Pos          (2U)\n#define SDIO_STA_CTIMEOUT_Msk          (0x1UL << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */\n#define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */\n#define SDIO_STA_DTIMEOUT_Pos          (3U)\n#define SDIO_STA_DTIMEOUT_Msk          (0x1UL << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */\n#define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */\n#define SDIO_STA_TXUNDERR_Pos          (4U)\n#define SDIO_STA_TXUNDERR_Msk          (0x1UL << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */\n#define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */\n#define SDIO_STA_RXOVERR_Pos           (5U)\n#define SDIO_STA_RXOVERR_Msk           (0x1UL << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */\n#define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */\n#define SDIO_STA_CMDREND_Pos           (6U)\n#define SDIO_STA_CMDREND_Msk           (0x1UL << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */\n#define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */\n#define SDIO_STA_CMDSENT_Pos           (7U)\n#define SDIO_STA_CMDSENT_Msk           (0x1UL << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */\n#define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */\n#define SDIO_STA_DATAEND_Pos           (8U)\n#define SDIO_STA_DATAEND_Msk           (0x1UL << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */\n#define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */\n#define SDIO_STA_DBCKEND_Pos           (10U)\n#define SDIO_STA_DBCKEND_Msk           (0x1UL << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */\n#define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */\n#define SDIO_STA_CMDACT_Pos            (11U)\n#define SDIO_STA_CMDACT_Msk            (0x1UL << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */\n#define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */\n#define SDIO_STA_TXACT_Pos             (12U)\n#define SDIO_STA_TXACT_Msk             (0x1UL << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */\n#define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */\n#define SDIO_STA_RXACT_Pos             (13U)\n#define SDIO_STA_RXACT_Msk             (0x1UL << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */\n#define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */\n#define SDIO_STA_TXFIFOHE_Pos          (14U)\n#define SDIO_STA_TXFIFOHE_Msk          (0x1UL << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */\n#define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\n#define SDIO_STA_RXFIFOHF_Pos          (15U)\n#define SDIO_STA_RXFIFOHF_Msk          (0x1UL << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */\n#define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\n#define SDIO_STA_TXFIFOF_Pos           (16U)\n#define SDIO_STA_TXFIFOF_Msk           (0x1UL << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */\n#define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */\n#define SDIO_STA_RXFIFOF_Pos           (17U)\n#define SDIO_STA_RXFIFOF_Msk           (0x1UL << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */\n#define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */\n#define SDIO_STA_TXFIFOE_Pos           (18U)\n#define SDIO_STA_TXFIFOE_Msk           (0x1UL << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */\n#define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */\n#define SDIO_STA_RXFIFOE_Pos           (19U)\n#define SDIO_STA_RXFIFOE_Msk           (0x1UL << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */\n#define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */\n#define SDIO_STA_TXDAVL_Pos            (20U)\n#define SDIO_STA_TXDAVL_Msk            (0x1UL << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */\n#define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */\n#define SDIO_STA_RXDAVL_Pos            (21U)\n#define SDIO_STA_RXDAVL_Msk            (0x1UL << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */\n#define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */\n#define SDIO_STA_SDIOIT_Pos            (22U)\n#define SDIO_STA_SDIOIT_Msk            (0x1UL << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */\n#define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */\n\n/*******************  Bit definition for SDIO_ICR register  *******************/\n#define SDIO_ICR_CCRCFAILC_Pos         (0U)\n#define SDIO_ICR_CCRCFAILC_Msk         (0x1UL << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */\n#define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */\n#define SDIO_ICR_DCRCFAILC_Pos         (1U)\n#define SDIO_ICR_DCRCFAILC_Msk         (0x1UL << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */\n#define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */\n#define SDIO_ICR_CTIMEOUTC_Pos         (2U)\n#define SDIO_ICR_CTIMEOUTC_Msk         (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */\n#define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */\n#define SDIO_ICR_DTIMEOUTC_Pos         (3U)\n#define SDIO_ICR_DTIMEOUTC_Msk         (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */\n#define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */\n#define SDIO_ICR_TXUNDERRC_Pos         (4U)\n#define SDIO_ICR_TXUNDERRC_Msk         (0x1UL << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */\n#define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */\n#define SDIO_ICR_RXOVERRC_Pos          (5U)\n#define SDIO_ICR_RXOVERRC_Msk          (0x1UL << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */\n#define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */\n#define SDIO_ICR_CMDRENDC_Pos          (6U)\n#define SDIO_ICR_CMDRENDC_Msk          (0x1UL << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */\n#define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */\n#define SDIO_ICR_CMDSENTC_Pos          (7U)\n#define SDIO_ICR_CMDSENTC_Msk          (0x1UL << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */\n#define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */\n#define SDIO_ICR_DATAENDC_Pos          (8U)\n#define SDIO_ICR_DATAENDC_Msk          (0x1UL << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */\n#define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */\n#define SDIO_ICR_DBCKENDC_Pos          (10U)\n#define SDIO_ICR_DBCKENDC_Msk          (0x1UL << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */\n#define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */\n#define SDIO_ICR_SDIOITC_Pos           (22U)\n#define SDIO_ICR_SDIOITC_Msk           (0x1UL << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */\n#define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */\n\n/******************  Bit definition for SDIO_MASK register  *******************/\n#define SDIO_MASK_CCRCFAILIE_Pos       (0U)\n#define SDIO_MASK_CCRCFAILIE_Msk       (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */\n#define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */\n#define SDIO_MASK_DCRCFAILIE_Pos       (1U)\n#define SDIO_MASK_DCRCFAILIE_Msk       (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */\n#define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */\n#define SDIO_MASK_CTIMEOUTIE_Pos       (2U)\n#define SDIO_MASK_CTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */\n#define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */\n#define SDIO_MASK_DTIMEOUTIE_Pos       (3U)\n#define SDIO_MASK_DTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */\n#define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */\n#define SDIO_MASK_TXUNDERRIE_Pos       (4U)\n#define SDIO_MASK_TXUNDERRIE_Msk       (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */\n#define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */\n#define SDIO_MASK_RXOVERRIE_Pos        (5U)\n#define SDIO_MASK_RXOVERRIE_Msk        (0x1UL << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */\n#define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */\n#define SDIO_MASK_CMDRENDIE_Pos        (6U)\n#define SDIO_MASK_CMDRENDIE_Msk        (0x1UL << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */\n#define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */\n#define SDIO_MASK_CMDSENTIE_Pos        (7U)\n#define SDIO_MASK_CMDSENTIE_Msk        (0x1UL << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */\n#define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */\n#define SDIO_MASK_DATAENDIE_Pos        (8U)\n#define SDIO_MASK_DATAENDIE_Msk        (0x1UL << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */\n#define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */\n#define SDIO_MASK_DBCKENDIE_Pos        (10U)\n#define SDIO_MASK_DBCKENDIE_Msk        (0x1UL << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */\n#define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */\n#define SDIO_MASK_CMDACTIE_Pos         (11U)\n#define SDIO_MASK_CMDACTIE_Msk         (0x1UL << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */\n#define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */\n#define SDIO_MASK_TXACTIE_Pos          (12U)\n#define SDIO_MASK_TXACTIE_Msk          (0x1UL << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */\n#define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */\n#define SDIO_MASK_RXACTIE_Pos          (13U)\n#define SDIO_MASK_RXACTIE_Msk          (0x1UL << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */\n#define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */\n#define SDIO_MASK_TXFIFOHEIE_Pos       (14U)\n#define SDIO_MASK_TXFIFOHEIE_Msk       (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */\n#define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */\n#define SDIO_MASK_RXFIFOHFIE_Pos       (15U)\n#define SDIO_MASK_RXFIFOHFIE_Msk       (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */\n#define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */\n#define SDIO_MASK_TXFIFOFIE_Pos        (16U)\n#define SDIO_MASK_TXFIFOFIE_Msk        (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */\n#define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */\n#define SDIO_MASK_RXFIFOFIE_Pos        (17U)\n#define SDIO_MASK_RXFIFOFIE_Msk        (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */\n#define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */\n#define SDIO_MASK_TXFIFOEIE_Pos        (18U)\n#define SDIO_MASK_TXFIFOEIE_Msk        (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */\n#define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_RXFIFOEIE_Pos        (19U)\n#define SDIO_MASK_RXFIFOEIE_Msk        (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */\n#define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_TXDAVLIE_Pos         (20U)\n#define SDIO_MASK_TXDAVLIE_Msk         (0x1UL << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */\n#define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */\n#define SDIO_MASK_RXDAVLIE_Pos         (21U)\n#define SDIO_MASK_RXDAVLIE_Msk         (0x1UL << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */\n#define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */\n#define SDIO_MASK_SDIOITIE_Pos         (22U)\n#define SDIO_MASK_SDIOITIE_Msk         (0x1UL << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */\n#define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */\n\n/*****************  Bit definition for SDIO_FIFOCNT register  *****************/\n#define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)\n#define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */\n#define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */\n\n/******************  Bit definition for SDIO_FIFO register  *******************/\n#define SDIO_FIFO_FIFODATA_Pos         (0U)\n#define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Serial Peripheral Interface                         */\n/*                                                                            */\n/******************************************************************************/\n#define I2S_APB1_APB2_FEATURE                                                  /*!< I2S IP's are splited between RCC APB1 and APB2 interfaces */\n\n/*******************  Bit definition for SPI_CR1 register  ********************/\n#define SPI_CR1_CPHA_Pos            (0U)\n#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */\n#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */\n#define SPI_CR1_CPOL_Pos            (1U)\n#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */\n#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */\n#define SPI_CR1_MSTR_Pos            (2U)\n#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */\n#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */\n\n#define SPI_CR1_BR_Pos              (3U)\n#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */\n#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */\n#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */\n#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */\n#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */\n\n#define SPI_CR1_SPE_Pos             (6U)\n#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */\n#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */\n#define SPI_CR1_LSBFIRST_Pos        (7U)\n#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */\n#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */\n#define SPI_CR1_SSI_Pos             (8U)\n#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */\n#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */\n#define SPI_CR1_SSM_Pos             (9U)\n#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */\n#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */\n#define SPI_CR1_RXONLY_Pos          (10U)\n#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */\n#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */\n#define SPI_CR1_DFF_Pos             (11U)\n#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */\n#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */\n#define SPI_CR1_CRCNEXT_Pos         (12U)\n#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */\n#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */\n#define SPI_CR1_CRCEN_Pos           (13U)\n#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */\n#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */\n#define SPI_CR1_BIDIOE_Pos          (14U)\n#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */\n#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */\n#define SPI_CR1_BIDIMODE_Pos        (15U)\n#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */\n#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */\n\n/*******************  Bit definition for SPI_CR2 register  ********************/\n#define SPI_CR2_RXDMAEN_Pos         (0U)\n#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */\n#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */\n#define SPI_CR2_TXDMAEN_Pos         (1U)\n#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */\n#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */\n#define SPI_CR2_SSOE_Pos            (2U)\n#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */\n#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */\n#define SPI_CR2_FRF_Pos             (4U)\n#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */\n#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */\n#define SPI_CR2_ERRIE_Pos           (5U)\n#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */\n#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */\n#define SPI_CR2_RXNEIE_Pos          (6U)\n#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */\n#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */\n#define SPI_CR2_TXEIE_Pos           (7U)\n#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */\n#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */\n\n/********************  Bit definition for SPI_SR register  ********************/\n#define SPI_SR_RXNE_Pos             (0U)\n#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */\n#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */\n#define SPI_SR_TXE_Pos              (1U)\n#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */\n#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */\n#define SPI_SR_CHSIDE_Pos           (2U)\n#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */\n#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */\n#define SPI_SR_UDR_Pos              (3U)\n#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */\n#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */\n#define SPI_SR_CRCERR_Pos           (4U)\n#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */\n#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */\n#define SPI_SR_MODF_Pos             (5U)\n#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */\n#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */\n#define SPI_SR_OVR_Pos              (6U)\n#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */\n#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */\n#define SPI_SR_BSY_Pos              (7U)\n#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */\n#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */\n#define SPI_SR_FRE_Pos              (8U)\n#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */\n#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */\n\n/********************  Bit definition for SPI_DR register  ********************/\n#define SPI_DR_DR_Pos               (0U)\n#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */\n#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */\n\n/*******************  Bit definition for SPI_CRCPR register  ******************/\n#define SPI_CRCPR_CRCPOLY_Pos       (0U)\n#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */\n#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */\n\n/******************  Bit definition for SPI_RXCRCR register  ******************/\n#define SPI_RXCRCR_RXCRC_Pos        (0U)\n#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */\n\n/******************  Bit definition for SPI_TXCRCR register  ******************/\n#define SPI_TXCRCR_TXCRC_Pos        (0U)\n#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */\n\n/******************  Bit definition for SPI_I2SCFGR register  *****************/\n#define SPI_I2SCFGR_CHLEN_Pos       (0U)\n#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */\n#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */\n\n#define SPI_I2SCFGR_DATLEN_Pos      (1U)\n#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */\n#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */\n#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */\n#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */\n\n#define SPI_I2SCFGR_CKPOL_Pos       (3U)\n#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */\n#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */\n\n#define SPI_I2SCFGR_I2SSTD_Pos      (4U)\n#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */\n#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */\n#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */\n#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */\n\n#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)\n#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */\n#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */\n\n#define SPI_I2SCFGR_I2SCFG_Pos      (8U)\n#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */\n#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */\n#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */\n#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */\n\n#define SPI_I2SCFGR_I2SE_Pos        (10U)\n#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */\n#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */\n#define SPI_I2SCFGR_I2SMOD_Pos      (11U)\n#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */\n#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */\n#define SPI_I2SCFGR_ASTRTEN_Pos     (12U)\n#define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)          /*!< 0x00001000 */\n#define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */\n\n/******************  Bit definition for SPI_I2SPR register  *******************/\n#define SPI_I2SPR_I2SDIV_Pos        (0U)\n#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */\n#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */\n#define SPI_I2SPR_ODD_Pos           (8U)\n#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */\n#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */\n#define SPI_I2SPR_MCKOE_Pos         (9U)\n#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */\n#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                 SYSCFG                                     */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SYSCFG_MEMRMP register  ***************/\n#define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)\n#define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */\n#define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */\n#define SYSCFG_MEMRMP_MEM_MODE_0             (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */\n#define SYSCFG_MEMRMP_MEM_MODE_1             (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */\n#define SYSCFG_MEMRMP_MEM_MODE_2             (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */\n#define SYSCFG_MEMRMP_UFB_MODE_Pos           (8U)\n#define SYSCFG_MEMRMP_UFB_MODE_Msk           (0x1UL << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */\n#define SYSCFG_MEMRMP_UFB_MODE               SYSCFG_MEMRMP_UFB_MODE_Msk        /*!< User Flash Bank mode    */\n#define SYSCFG_MEMRMP_SWP_FMC_Pos            (10U)\n#define SYSCFG_MEMRMP_SWP_FMC_Msk            (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */\n#define SYSCFG_MEMRMP_SWP_FMC                SYSCFG_MEMRMP_SWP_FMC_Msk         /*!< FMC memory mapping swap */\n#define SYSCFG_MEMRMP_SWP_FMC_0              (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */\n/* Legacy Defines */\n#define SYSCFG_SWP_FMC                  SYSCFG_MEMRMP_SWP_FMC\n/******************  Bit definition for SYSCFG_PMC register  ******************/\n#define SYSCFG_PMC_ADCxDC2_Pos               (16U)\n#define SYSCFG_PMC_ADCxDC2_Msk               (0x7UL << SYSCFG_PMC_ADCxDC2_Pos)  /*!< 0x00070000 */\n#define SYSCFG_PMC_ADCxDC2                   SYSCFG_PMC_ADCxDC2_Msk            /*!< Refer to AN4073 on how to use this bit  */\n#define SYSCFG_PMC_ADC1DC2_Pos               (16U)\n#define SYSCFG_PMC_ADC1DC2_Msk               (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)  /*!< 0x00010000 */\n#define SYSCFG_PMC_ADC1DC2                   SYSCFG_PMC_ADC1DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */\n#define SYSCFG_PMC_ADC2DC2_Pos               (17U)\n#define SYSCFG_PMC_ADC2DC2_Msk               (0x1UL << SYSCFG_PMC_ADC2DC2_Pos)  /*!< 0x00020000 */\n#define SYSCFG_PMC_ADC2DC2                   SYSCFG_PMC_ADC2DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */\n#define SYSCFG_PMC_ADC3DC2_Pos               (18U)\n#define SYSCFG_PMC_ADC3DC2_Msk               (0x1UL << SYSCFG_PMC_ADC3DC2_Pos)  /*!< 0x00040000 */\n#define SYSCFG_PMC_ADC3DC2                   SYSCFG_PMC_ADC3DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */\n\n/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\n#define SYSCFG_EXTICR1_EXTI0_Pos             (0U)\n#define SYSCFG_EXTICR1_EXTI0_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */\n#define SYSCFG_EXTICR1_EXTI1_Pos             (4U)\n#define SYSCFG_EXTICR1_EXTI1_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */\n#define SYSCFG_EXTICR1_EXTI2_Pos             (8U)\n#define SYSCFG_EXTICR1_EXTI2_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */\n#define SYSCFG_EXTICR1_EXTI3_Pos             (12U)\n#define SYSCFG_EXTICR1_EXTI3_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */\n/**\n  * @brief   EXTI0 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PD              0x0003U                           /*!<PD[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PE              0x0004U                           /*!<PE[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PF              0x0005U                           /*!<PF[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PG              0x0006U                           /*!<PG[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PI              0x0008U                           /*!<PI[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PJ              0x0009U                           /*!<PJ[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PK              0x000AU                           /*!<PK[0] pin */\n\n/**\n  * @brief   EXTI1 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PD              0x0030U                           /*!<PD[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PE              0x0040U                           /*!<PE[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PF              0x0050U                           /*!<PF[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PG              0x0060U                           /*!<PG[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PI              0x0080U                           /*!<PI[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PJ              0x0090U                           /*!<PJ[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PK              0x00A0U                           /*!<PK[1] pin */\n\n/**\n  * @brief   EXTI2 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PD              0x0300U                           /*!<PD[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PE              0x0400U                           /*!<PE[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PF              0x0500U                           /*!<PF[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PG              0x0600U                           /*!<PG[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PI              0x0800U                           /*!<PI[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PJ              0x0900U                           /*!<PJ[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PK              0x0A00U                           /*!<PK[2] pin */\n\n/**\n  * @brief   EXTI3 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PD              0x3000U                           /*!<PD[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PE              0x4000U                           /*!<PE[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PF              0x5000U                           /*!<PF[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PG              0x6000U                           /*!<PG[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PI              0x8000U                           /*!<PI[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PJ              0x9000U                           /*!<PJ[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PK              0xA000U                           /*!<PK[3] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\n#define SYSCFG_EXTICR2_EXTI4_Pos             (0U)\n#define SYSCFG_EXTICR2_EXTI4_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */\n#define SYSCFG_EXTICR2_EXTI5_Pos             (4U)\n#define SYSCFG_EXTICR2_EXTI5_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */\n#define SYSCFG_EXTICR2_EXTI6_Pos             (8U)\n#define SYSCFG_EXTICR2_EXTI6_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */\n#define SYSCFG_EXTICR2_EXTI7_Pos             (12U)\n#define SYSCFG_EXTICR2_EXTI7_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */\n\n/**\n  * @brief   EXTI4 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PD              0x0003U                           /*!<PD[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PE              0x0004U                           /*!<PE[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PF              0x0005U                           /*!<PF[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PG              0x0006U                           /*!<PG[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PI              0x0008U                           /*!<PI[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PJ              0x0009U                           /*!<PJ[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PK              0x000AU                           /*!<PK[4] pin */\n\n/**\n  * @brief   EXTI5 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PD              0x0030U                           /*!<PD[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PE              0x0040U                           /*!<PE[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PF              0x0050U                           /*!<PF[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PG              0x0060U                           /*!<PG[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PI              0x0080U                           /*!<PI[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PJ              0x0090U                           /*!<PJ[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PK              0x00A0U                           /*!<PK[5] pin */\n\n/**\n  * @brief   EXTI6 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PD              0x0300U                           /*!<PD[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PE              0x0400U                           /*!<PE[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PF              0x0500U                           /*!<PF[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PG              0x0600U                           /*!<PG[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PI              0x0800U                           /*!<PI[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PJ              0x0900U                           /*!<PJ[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PK              0x0A00U                           /*!<PK[6] pin */\n\n/**\n  * @brief   EXTI7 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PD              0x3000U                           /*!<PD[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PE              0x4000U                           /*!<PE[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PF              0x5000U                           /*!<PF[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PG              0x6000U                           /*!<PG[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PI              0x8000U                           /*!<PI[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PJ              0x9000U                           /*!<PJ[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PK              0xA000U                           /*!<PK[7] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\n#define SYSCFG_EXTICR3_EXTI8_Pos             (0U)\n#define SYSCFG_EXTICR3_EXTI8_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */\n#define SYSCFG_EXTICR3_EXTI9_Pos             (4U)\n#define SYSCFG_EXTICR3_EXTI9_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */\n#define SYSCFG_EXTICR3_EXTI10_Pos            (8U)\n#define SYSCFG_EXTICR3_EXTI10_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */\n#define SYSCFG_EXTICR3_EXTI11_Pos            (12U)\n#define SYSCFG_EXTICR3_EXTI11_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */\n\n/**\n  * @brief   EXTI8 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PD              0x0003U                           /*!<PD[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PE              0x0004U                           /*!<PE[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PF              0x0005U                           /*!<PF[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PG              0x0006U                           /*!<PG[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PI              0x0008U                           /*!<PI[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PJ              0x0009U                           /*!<PJ[8] pin */\n\n/**\n  * @brief   EXTI9 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PD              0x0030U                           /*!<PD[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PE              0x0040U                           /*!<PE[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PF              0x0050U                           /*!<PF[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PG              0x0060U                           /*!<PG[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PI              0x0080U                           /*!<PI[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PJ              0x0090U                           /*!<PJ[9] pin */\n\n/**\n  * @brief   EXTI10 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PD             0x0300U                           /*!<PD[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PE             0x0400U                           /*!<PE[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PF             0x0500U                           /*!<PF[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PG             0x0600U                           /*!<PG[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PI             0x0800U                           /*!<PI[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PJ             0x0900U                           /*!<PJ[10] pin */\n\n/**\n  * @brief   EXTI11 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PD             0x3000U                           /*!<PD[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PE             0x4000U                           /*!<PE[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PF             0x5000U                           /*!<PF[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PG             0x6000U                           /*!<PG[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PI             0x8000U                           /*!<PI[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PJ             0x9000U                           /*!<PJ[11] pin */\n\n\n/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\n#define SYSCFG_EXTICR4_EXTI12_Pos            (0U)\n#define SYSCFG_EXTICR4_EXTI12_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */\n#define SYSCFG_EXTICR4_EXTI13_Pos            (4U)\n#define SYSCFG_EXTICR4_EXTI13_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */\n#define SYSCFG_EXTICR4_EXTI14_Pos            (8U)\n#define SYSCFG_EXTICR4_EXTI14_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */\n#define SYSCFG_EXTICR4_EXTI15_Pos            (12U)\n#define SYSCFG_EXTICR4_EXTI15_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */\n\n/**\n  * @brief   EXTI12 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PD             0x0003U                           /*!<PD[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PE             0x0004U                           /*!<PE[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PF             0x0005U                           /*!<PF[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PG             0x0006U                           /*!<PG[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PI             0x0008U                           /*!<PI[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PJ             0x0009U                           /*!<PJ[12] pin */\n\n/**\n  * @brief   EXTI13 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PD             0x0030U                           /*!<PD[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PE             0x0040U                           /*!<PE[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PF             0x0050U                           /*!<PF[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PG             0x0060U                           /*!<PG[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PI             0x0008U                           /*!<PI[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PJ             0x0009U                           /*!<PJ[13] pin */\n\n/**\n  * @brief   EXTI14 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PD             0x0300U                           /*!<PD[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PE             0x0400U                           /*!<PE[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PF             0x0500U                           /*!<PF[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PG             0x0600U                           /*!<PG[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PI             0x0800U                           /*!<PI[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PJ             0x0900U                           /*!<PJ[14] pin */\n\n/**\n  * @brief   EXTI15 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PD             0x3000U                           /*!<PD[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PE             0x4000U                           /*!<PE[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PF             0x5000U                           /*!<PF[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PG             0x6000U                           /*!<PG[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PI             0x8000U                           /*!<PI[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PJ             0x9000U                           /*!<PJ[15] pin */\n\n/******************  Bit definition for SYSCFG_CMPCR register  ****************/\n#define SYSCFG_CMPCR_CMP_PD_Pos              (0U)\n#define SYSCFG_CMPCR_CMP_PD_Msk              (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */\n#define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */\n#define SYSCFG_CMPCR_READY_Pos               (8U)\n#define SYSCFG_CMPCR_READY_Msk               (0x1UL << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */\n#define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */\n/******************  Bit definition for SYSCFG_CFGR register  ****************/\n#define SYSCFG_CFGR_FMPI2C1_SCL_Pos          (0U)\n#define SYSCFG_CFGR_FMPI2C1_SCL_Msk          (0x1UL << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */\n#define SYSCFG_CFGR_FMPI2C1_SCL              SYSCFG_CFGR_FMPI2C1_SCL_Msk       /*!<FM+ drive capability for FMPI2C1_SCL pin */\n#define SYSCFG_CFGR_FMPI2C1_SDA_Pos          (1U)\n#define SYSCFG_CFGR_FMPI2C1_SDA_Msk          (0x1UL << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */\n#define SYSCFG_CFGR_FMPI2C1_SDA              SYSCFG_CFGR_FMPI2C1_SDA_Msk       /*!<FM+ drive capability for FMPI2C1_SDA pin */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    TIM                                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for TIM_CR1 register  ********************/\n#define TIM_CR1_CEN_Pos           (0U)\n#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */\n#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */\n#define TIM_CR1_UDIS_Pos          (1U)\n#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */\n#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */\n#define TIM_CR1_URS_Pos           (2U)\n#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */\n#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */\n#define TIM_CR1_OPM_Pos           (3U)\n#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */\n#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */\n#define TIM_CR1_DIR_Pos           (4U)\n#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */\n#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */\n\n#define TIM_CR1_CMS_Pos           (5U)\n#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */\n#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */\n#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR1_ARPE_Pos          (7U)\n#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */\n#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */\n\n#define TIM_CR1_CKD_Pos           (8U)\n#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */\n#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */\n#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */\n#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */\n\n/*******************  Bit definition for TIM_CR2 register  ********************/\n#define TIM_CR2_CCPC_Pos          (0U)\n#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */\n#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */\n#define TIM_CR2_CCUS_Pos          (2U)\n#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */\n#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */\n#define TIM_CR2_CCDS_Pos          (3U)\n#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */\n#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */\n\n#define TIM_CR2_MMS_Pos           (4U)\n#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */\n#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */\n#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */\n#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR2_TI1S_Pos          (7U)\n#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */\n#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */\n#define TIM_CR2_OIS1_Pos          (8U)\n#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */\n#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */\n#define TIM_CR2_OIS1N_Pos         (9U)\n#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */\n#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */\n#define TIM_CR2_OIS2_Pos          (10U)\n#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */\n#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */\n#define TIM_CR2_OIS2N_Pos         (11U)\n#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */\n#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */\n#define TIM_CR2_OIS3_Pos          (12U)\n#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */\n#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */\n#define TIM_CR2_OIS3N_Pos         (13U)\n#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */\n#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */\n#define TIM_CR2_OIS4_Pos          (14U)\n#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */\n#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */\n\n/*******************  Bit definition for TIM_SMCR register  *******************/\n#define TIM_SMCR_SMS_Pos          (0U)\n#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */\n#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */\n#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */\n#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */\n#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */\n\n#define TIM_SMCR_TS_Pos           (4U)\n#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */\n#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */\n#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */\n#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */\n#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */\n\n#define TIM_SMCR_MSM_Pos          (7U)\n#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */\n#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */\n\n#define TIM_SMCR_ETF_Pos          (8U)\n#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */\n#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */\n#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */\n#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */\n#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */\n#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */\n\n#define TIM_SMCR_ETPS_Pos         (12U)\n#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */\n#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */\n#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */\n#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */\n\n#define TIM_SMCR_ECE_Pos          (14U)\n#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */\n#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */\n#define TIM_SMCR_ETP_Pos          (15U)\n#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */\n#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */\n\n/*******************  Bit definition for TIM_DIER register  *******************/\n#define TIM_DIER_UIE_Pos          (0U)\n#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */\n#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */\n#define TIM_DIER_CC1IE_Pos        (1U)\n#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */\n#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */\n#define TIM_DIER_CC2IE_Pos        (2U)\n#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */\n#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */\n#define TIM_DIER_CC3IE_Pos        (3U)\n#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */\n#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */\n#define TIM_DIER_CC4IE_Pos        (4U)\n#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */\n#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */\n#define TIM_DIER_COMIE_Pos        (5U)\n#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */\n#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */\n#define TIM_DIER_TIE_Pos          (6U)\n#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */\n#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */\n#define TIM_DIER_BIE_Pos          (7U)\n#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */\n#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */\n#define TIM_DIER_UDE_Pos          (8U)\n#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */\n#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */\n#define TIM_DIER_CC1DE_Pos        (9U)\n#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */\n#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */\n#define TIM_DIER_CC2DE_Pos        (10U)\n#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */\n#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */\n#define TIM_DIER_CC3DE_Pos        (11U)\n#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */\n#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */\n#define TIM_DIER_CC4DE_Pos        (12U)\n#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */\n#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */\n#define TIM_DIER_COMDE_Pos        (13U)\n#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */\n#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */\n#define TIM_DIER_TDE_Pos          (14U)\n#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */\n#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */\n\n/********************  Bit definition for TIM_SR register  ********************/\n#define TIM_SR_UIF_Pos            (0U)\n#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */\n#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */\n#define TIM_SR_CC1IF_Pos          (1U)\n#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */\n#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */\n#define TIM_SR_CC2IF_Pos          (2U)\n#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */\n#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */\n#define TIM_SR_CC3IF_Pos          (3U)\n#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */\n#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */\n#define TIM_SR_CC4IF_Pos          (4U)\n#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */\n#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */\n#define TIM_SR_COMIF_Pos          (5U)\n#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */\n#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */\n#define TIM_SR_TIF_Pos            (6U)\n#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */\n#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */\n#define TIM_SR_BIF_Pos            (7U)\n#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */\n#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */\n#define TIM_SR_CC1OF_Pos          (9U)\n#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */\n#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */\n#define TIM_SR_CC2OF_Pos          (10U)\n#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */\n#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */\n#define TIM_SR_CC3OF_Pos          (11U)\n#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */\n#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */\n#define TIM_SR_CC4OF_Pos          (12U)\n#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */\n#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */\n\n/*******************  Bit definition for TIM_EGR register  ********************/\n#define TIM_EGR_UG_Pos            (0U)\n#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */\n#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */\n#define TIM_EGR_CC1G_Pos          (1U)\n#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */\n#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */\n#define TIM_EGR_CC2G_Pos          (2U)\n#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */\n#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */\n#define TIM_EGR_CC3G_Pos          (3U)\n#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */\n#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */\n#define TIM_EGR_CC4G_Pos          (4U)\n#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */\n#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */\n#define TIM_EGR_COMG_Pos          (5U)\n#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */\n#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */\n#define TIM_EGR_TG_Pos            (6U)\n#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */\n#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */\n#define TIM_EGR_BG_Pos            (7U)\n#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */\n#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */\n\n/******************  Bit definition for TIM_CCMR1 register  *******************/\n#define TIM_CCMR1_CC1S_Pos        (0U)\n#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\n#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR1_OC1FE_Pos       (2U)\n#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */\n#define TIM_CCMR1_OC1PE_Pos       (3U)\n#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */\n\n#define TIM_CCMR1_OC1M_Pos        (4U)\n#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */\n#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR1_OC1CE_Pos       (7U)\n#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */\n\n#define TIM_CCMR1_CC2S_Pos        (8U)\n#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\n#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR1_OC2FE_Pos       (10U)\n#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */\n#define TIM_CCMR1_OC2PE_Pos       (11U)\n#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */\n\n#define TIM_CCMR1_OC2M_Pos        (12U)\n#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */\n#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR1_OC2CE_Pos       (15U)\n#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR1_IC1PSC_Pos      (2U)\n#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\n#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR1_IC1F_Pos        (4U)\n#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */\n#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR1_IC2PSC_Pos      (10U)\n#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */\n#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR1_IC2F_Pos        (12U)\n#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */\n#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */\n\n/******************  Bit definition for TIM_CCMR2 register  *******************/\n#define TIM_CCMR2_CC3S_Pos        (0U)\n#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */\n#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR2_OC3FE_Pos       (2U)\n#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */\n#define TIM_CCMR2_OC3PE_Pos       (3U)\n#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */\n\n#define TIM_CCMR2_OC3M_Pos        (4U)\n#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\n#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR2_OC3CE_Pos       (7U)\n#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */\n\n#define TIM_CCMR2_CC4S_Pos        (8U)\n#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\n#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR2_OC4FE_Pos       (10U)\n#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */\n#define TIM_CCMR2_OC4PE_Pos       (11U)\n#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */\n\n#define TIM_CCMR2_OC4M_Pos        (12U)\n#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\n#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR2_OC4CE_Pos       (15U)\n#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR2_IC3PSC_Pos      (2U)\n#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\n#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR2_IC3F_Pos        (4U)\n#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\n#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR2_IC4PSC_Pos      (10U)\n#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\n#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR2_IC4F_Pos        (12U)\n#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\n#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */\n\n/*******************  Bit definition for TIM_CCER register  *******************/\n#define TIM_CCER_CC1E_Pos         (0U)\n#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */\n#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */\n#define TIM_CCER_CC1P_Pos         (1U)\n#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */\n#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */\n#define TIM_CCER_CC1NE_Pos        (2U)\n#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */\n#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */\n#define TIM_CCER_CC1NP_Pos        (3U)\n#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */\n#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */\n#define TIM_CCER_CC2E_Pos         (4U)\n#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */\n#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */\n#define TIM_CCER_CC2P_Pos         (5U)\n#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */\n#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */\n#define TIM_CCER_CC2NE_Pos        (6U)\n#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */\n#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */\n#define TIM_CCER_CC2NP_Pos        (7U)\n#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */\n#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */\n#define TIM_CCER_CC3E_Pos         (8U)\n#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */\n#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */\n#define TIM_CCER_CC3P_Pos         (9U)\n#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */\n#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */\n#define TIM_CCER_CC3NE_Pos        (10U)\n#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */\n#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */\n#define TIM_CCER_CC3NP_Pos        (11U)\n#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */\n#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */\n#define TIM_CCER_CC4E_Pos         (12U)\n#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */\n#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */\n#define TIM_CCER_CC4P_Pos         (13U)\n#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */\n#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */\n#define TIM_CCER_CC4NP_Pos        (15U)\n#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */\n#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */\n\n/*******************  Bit definition for TIM_CNT register  ********************/\n#define TIM_CNT_CNT_Pos           (0U)\n#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0xFFFFFFFF */\n#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                                  /*!<Counter Value            */\n\n/*******************  Bit definition for TIM_PSC register  ********************/\n#define TIM_PSC_PSC_Pos           (0U)\n#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */\n#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */\n\n/*******************  Bit definition for TIM_ARR register  ********************/\n#define TIM_ARR_ARR_Pos           (0U)\n#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */\n#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */\n\n/*******************  Bit definition for TIM_RCR register  ********************/\n#define TIM_RCR_REP_Pos           (0U)\n#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */\n#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */\n\n/*******************  Bit definition for TIM_CCR1 register  *******************/\n#define TIM_CCR1_CCR1_Pos         (0U)\n#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */\n\n/*******************  Bit definition for TIM_CCR2 register  *******************/\n#define TIM_CCR2_CCR2_Pos         (0U)\n#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */\n\n/*******************  Bit definition for TIM_CCR3 register  *******************/\n#define TIM_CCR3_CCR3_Pos         (0U)\n#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */\n\n/*******************  Bit definition for TIM_CCR4 register  *******************/\n#define TIM_CCR4_CCR4_Pos         (0U)\n#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */\n\n/*******************  Bit definition for TIM_BDTR register  *******************/\n#define TIM_BDTR_DTG_Pos          (0U)\n#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */\n#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\n#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */\n#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */\n#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */\n#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */\n#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */\n#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */\n#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */\n#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */\n\n#define TIM_BDTR_LOCK_Pos         (8U)\n#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */\n#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */\n#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */\n#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */\n\n#define TIM_BDTR_OSSI_Pos         (10U)\n#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */\n#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */\n#define TIM_BDTR_OSSR_Pos         (11U)\n#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */\n#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */\n#define TIM_BDTR_BKE_Pos          (12U)\n#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */\n#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */\n#define TIM_BDTR_BKP_Pos          (13U)\n#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */\n#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */\n#define TIM_BDTR_AOE_Pos          (14U)\n#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */\n#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */\n#define TIM_BDTR_MOE_Pos          (15U)\n#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */\n#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */\n\n/*******************  Bit definition for TIM_DCR register  ********************/\n#define TIM_DCR_DBA_Pos           (0U)\n#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */\n#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */\n#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */\n#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */\n#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */\n#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */\n#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */\n\n#define TIM_DCR_DBL_Pos           (8U)\n#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */\n#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */\n#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */\n#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */\n#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */\n#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */\n#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */\n\n/*******************  Bit definition for TIM_DMAR register  *******************/\n#define TIM_DMAR_DMAB_Pos         (0U)\n#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */\n#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */\n\n/*******************  Bit definition for TIM_OR register  *********************/\n#define TIM_OR_TI1_RMP_Pos        (0U)\n#define TIM_OR_TI1_RMP_Msk        (0x3UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000003 */\n#define TIM_OR_TI1_RMP            TIM_OR_TI1_RMP_Msk                           /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */\n#define TIM_OR_TI1_RMP_0          (0x1UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000001 */\n#define TIM_OR_TI1_RMP_1          (0x2UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000002 */\n\n#define TIM_OR_TI4_RMP_Pos        (6U)\n#define TIM_OR_TI4_RMP_Msk        (0x3UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */\n#define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */\n#define TIM_OR_TI4_RMP_0          (0x1UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */\n#define TIM_OR_TI4_RMP_1          (0x2UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */\n#define TIM_OR_ITR1_RMP_Pos       (10U)\n#define TIM_OR_ITR1_RMP_Msk       (0x3UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */\n#define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\n#define TIM_OR_ITR1_RMP_0         (0x1UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */\n#define TIM_OR_ITR1_RMP_1         (0x2UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*         Universal Synchronous Asynchronous Receiver Transmitter            */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for USART_SR register  *******************/\n#define USART_SR_PE_Pos               (0U)\n#define USART_SR_PE_Msk               (0x1UL << USART_SR_PE_Pos)                /*!< 0x00000001 */\n#define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */\n#define USART_SR_FE_Pos               (1U)\n#define USART_SR_FE_Msk               (0x1UL << USART_SR_FE_Pos)                /*!< 0x00000002 */\n#define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */\n#define USART_SR_NE_Pos               (2U)\n#define USART_SR_NE_Msk               (0x1UL << USART_SR_NE_Pos)                /*!< 0x00000004 */\n#define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */\n#define USART_SR_ORE_Pos              (3U)\n#define USART_SR_ORE_Msk              (0x1UL << USART_SR_ORE_Pos)               /*!< 0x00000008 */\n#define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */\n#define USART_SR_IDLE_Pos             (4U)\n#define USART_SR_IDLE_Msk             (0x1UL << USART_SR_IDLE_Pos)              /*!< 0x00000010 */\n#define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */\n#define USART_SR_RXNE_Pos             (5U)\n#define USART_SR_RXNE_Msk             (0x1UL << USART_SR_RXNE_Pos)              /*!< 0x00000020 */\n#define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */\n#define USART_SR_TC_Pos               (6U)\n#define USART_SR_TC_Msk               (0x1UL << USART_SR_TC_Pos)                /*!< 0x00000040 */\n#define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */\n#define USART_SR_TXE_Pos              (7U)\n#define USART_SR_TXE_Msk              (0x1UL << USART_SR_TXE_Pos)               /*!< 0x00000080 */\n#define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */\n#define USART_SR_LBD_Pos              (8U)\n#define USART_SR_LBD_Msk              (0x1UL << USART_SR_LBD_Pos)               /*!< 0x00000100 */\n#define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */\n#define USART_SR_CTS_Pos              (9U)\n#define USART_SR_CTS_Msk              (0x1UL << USART_SR_CTS_Pos)               /*!< 0x00000200 */\n#define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */\n\n/*******************  Bit definition for USART_DR register  *******************/\n#define USART_DR_DR_Pos               (0U)\n#define USART_DR_DR_Msk               (0x1FFUL << USART_DR_DR_Pos)              /*!< 0x000001FF */\n#define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */\n\n/******************  Bit definition for USART_BRR register  *******************/\n#define USART_BRR_DIV_Fraction_Pos    (0U)\n#define USART_BRR_DIV_Fraction_Msk    (0xFUL << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */\n#define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */\n#define USART_BRR_DIV_Mantissa_Pos    (4U)\n#define USART_BRR_DIV_Mantissa_Msk    (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */\n#define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */\n\n/******************  Bit definition for USART_CR1 register  *******************/\n#define USART_CR1_SBK_Pos             (0U)\n#define USART_CR1_SBK_Msk             (0x1UL << USART_CR1_SBK_Pos)              /*!< 0x00000001 */\n#define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */\n#define USART_CR1_RWU_Pos             (1U)\n#define USART_CR1_RWU_Msk             (0x1UL << USART_CR1_RWU_Pos)              /*!< 0x00000002 */\n#define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */\n#define USART_CR1_RE_Pos              (2U)\n#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */\n#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */\n#define USART_CR1_TE_Pos              (3U)\n#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */\n#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */\n#define USART_CR1_IDLEIE_Pos          (4U)\n#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */\n#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */\n#define USART_CR1_RXNEIE_Pos          (5U)\n#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */\n#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */\n#define USART_CR1_TCIE_Pos            (6U)\n#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */\n#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */\n#define USART_CR1_TXEIE_Pos           (7U)\n#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */\n#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<TXE Interrupt Enable                   */\n#define USART_CR1_PEIE_Pos            (8U)\n#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */\n#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */\n#define USART_CR1_PS_Pos              (9U)\n#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */\n#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */\n#define USART_CR1_PCE_Pos             (10U)\n#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */\n#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */\n#define USART_CR1_WAKE_Pos            (11U)\n#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */\n#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */\n#define USART_CR1_M_Pos               (12U)\n#define USART_CR1_M_Msk               (0x1UL << USART_CR1_M_Pos)                /*!< 0x00001000 */\n#define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */\n#define USART_CR1_UE_Pos              (13U)\n#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00002000 */\n#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */\n#define USART_CR1_OVER8_Pos           (15U)\n#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */\n#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */\n\n/******************  Bit definition for USART_CR2 register  *******************/\n#define USART_CR2_ADD_Pos             (0U)\n#define USART_CR2_ADD_Msk             (0xFUL << USART_CR2_ADD_Pos)              /*!< 0x0000000F */\n#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */\n#define USART_CR2_LBDL_Pos            (5U)\n#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */\n#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */\n#define USART_CR2_LBDIE_Pos           (6U)\n#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */\n#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */\n#define USART_CR2_LBCL_Pos            (8U)\n#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */\n#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */\n#define USART_CR2_CPHA_Pos            (9U)\n#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */\n#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */\n#define USART_CR2_CPOL_Pos            (10U)\n#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */\n#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */\n#define USART_CR2_CLKEN_Pos           (11U)\n#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */\n#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */\n\n#define USART_CR2_STOP_Pos            (12U)\n#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */\n#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */\n#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x1000 */\n#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x2000 */\n\n#define USART_CR2_LINEN_Pos           (14U)\n#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */\n#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */\n\n/******************  Bit definition for USART_CR3 register  *******************/\n#define USART_CR3_EIE_Pos             (0U)\n#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */\n#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */\n#define USART_CR3_IREN_Pos            (1U)\n#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */\n#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */\n#define USART_CR3_IRLP_Pos            (2U)\n#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */\n#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */\n#define USART_CR3_HDSEL_Pos           (3U)\n#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */\n#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */\n#define USART_CR3_NACK_Pos            (4U)\n#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */\n#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */\n#define USART_CR3_SCEN_Pos            (5U)\n#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */\n#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */\n#define USART_CR3_DMAR_Pos            (6U)\n#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */\n#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */\n#define USART_CR3_DMAT_Pos            (7U)\n#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */\n#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */\n#define USART_CR3_RTSE_Pos            (8U)\n#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */\n#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */\n#define USART_CR3_CTSE_Pos            (9U)\n#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */\n#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */\n#define USART_CR3_CTSIE_Pos           (10U)\n#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */\n#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */\n#define USART_CR3_ONEBIT_Pos          (11U)\n#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */\n#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */\n\n/******************  Bit definition for USART_GTPR register  ******************/\n#define USART_GTPR_PSC_Pos            (0U)\n#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */\n#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */\n#define USART_GTPR_PSC_0              (0x01UL << USART_GTPR_PSC_Pos)            /*!< 0x0001 */\n#define USART_GTPR_PSC_1              (0x02UL << USART_GTPR_PSC_Pos)            /*!< 0x0002 */\n#define USART_GTPR_PSC_2              (0x04UL << USART_GTPR_PSC_Pos)            /*!< 0x0004 */\n#define USART_GTPR_PSC_3              (0x08UL << USART_GTPR_PSC_Pos)            /*!< 0x0008 */\n#define USART_GTPR_PSC_4              (0x10UL << USART_GTPR_PSC_Pos)            /*!< 0x0010 */\n#define USART_GTPR_PSC_5              (0x20UL << USART_GTPR_PSC_Pos)            /*!< 0x0020 */\n#define USART_GTPR_PSC_6              (0x40UL << USART_GTPR_PSC_Pos)            /*!< 0x0040 */\n#define USART_GTPR_PSC_7              (0x80UL << USART_GTPR_PSC_Pos)            /*!< 0x0080 */\n\n#define USART_GTPR_GT_Pos             (8U)\n#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */\n#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            Window WATCHDOG                                 */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for WWDG_CR register  ********************/\n#define WWDG_CR_T_Pos           (0U)\n#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */\n#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\n#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x01 */\n#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x02 */\n#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x04 */\n#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x08 */\n#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x10 */\n#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x20 */\n#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x40 */\n/* Legacy defines */\n#define  WWDG_CR_T0                          WWDG_CR_T_0\n#define  WWDG_CR_T1                          WWDG_CR_T_1\n#define  WWDG_CR_T2                          WWDG_CR_T_2\n#define  WWDG_CR_T3                          WWDG_CR_T_3\n#define  WWDG_CR_T4                          WWDG_CR_T_4\n#define  WWDG_CR_T5                          WWDG_CR_T_5\n#define  WWDG_CR_T6                          WWDG_CR_T_6\n\n#define WWDG_CR_WDGA_Pos        (7U)\n#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */\n#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */\n\n/*******************  Bit definition for WWDG_CFR register  *******************/\n#define WWDG_CFR_W_Pos          (0U)\n#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */\n#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */\n#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x0001 */\n#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x0002 */\n#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x0004 */\n#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x0008 */\n#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x0010 */\n#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x0020 */\n#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x0040 */\n/* Legacy defines */\n#define  WWDG_CFR_W0                         WWDG_CFR_W_0\n#define  WWDG_CFR_W1                         WWDG_CFR_W_1\n#define  WWDG_CFR_W2                         WWDG_CFR_W_2\n#define  WWDG_CFR_W3                         WWDG_CFR_W_3\n#define  WWDG_CFR_W4                         WWDG_CFR_W_4\n#define  WWDG_CFR_W5                         WWDG_CFR_W_5\n#define  WWDG_CFR_W6                         WWDG_CFR_W_6\n\n#define WWDG_CFR_WDGTB_Pos      (7U)\n#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */\n#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */\n#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */\n#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */\n/* Legacy defines */\n#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0\n#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1\n\n#define WWDG_CFR_EWI_Pos        (9U)\n#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */\n#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */\n\n/*******************  Bit definition for WWDG_SR register  ********************/\n#define WWDG_SR_EWIF_Pos        (0U)\n#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */\n#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                DBG                                         */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for DBGMCU_IDCODE register  *************/\n#define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)\n#define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\n#define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk\n#define DBGMCU_IDCODE_REV_ID_Pos                     (16U)\n#define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\n#define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk\n\n/********************  Bit definition for DBGMCU_CR register  *****************/\n#define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)\n#define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */\n#define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk\n#define DBGMCU_CR_DBG_STOP_Pos                       (1U)\n#define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk\n#define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)\n#define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */\n#define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk\n#define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)\n#define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */\n#define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk\n\n#define DBGMCU_CR_TRACE_MODE_Pos                     (6U)\n#define DBGMCU_CR_TRACE_MODE_Msk                     (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */\n#define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk\n#define DBGMCU_CR_TRACE_MODE_0                       (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */\n#define DBGMCU_CR_TRACE_MODE_1                       (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */\n\n/********************  Bit definition for DBGMCU_APB1_FZ register  ************/\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos    (24U)\n#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */\n#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk\n/* Old IWDGSTOP bit definition, maintained for legacy purpose */\n#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP\n\n/********************  Bit definition for DBGMCU_APB2_FZ register  ************/\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                                       USB_OTG                              */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/\n#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)\n#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */\n#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)\n#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\n#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */\n#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)\n#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */\n#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)\n#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */\n#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */\n#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)\n#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */\n#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)\n#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */\n#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */\n#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)\n#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */\n#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)\n#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */\n#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)\n#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)\n#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */\n#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)\n#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)\n#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */\n#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */\n#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)\n#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */\n#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */\n#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)\n#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */\n#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */\n#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)\n#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */\n#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)\n#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */\n#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)\n#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */\n#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)\n#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */\n#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */\n\n/********************  Bit definition forUSB_OTG_HCFG register  ********************/\n\n#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)\n#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\n#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */\n#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCFG_FSLSS_Pos                   (2U)\n#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */\n\n/********************  Bit definition for USB_OTG_DCFG register  ********************/\n\n#define USB_OTG_DCFG_DSPD_Pos                    (0U)\n#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\n#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */\n#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)\n#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */\n\n#define USB_OTG_DCFG_DAD_Pos                     (4U)\n#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\n#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */\n#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\n\n#define USB_OTG_DCFG_PFIVL_Pos                   (11U)\n#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\n#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */\n#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\n\n#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)\n#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */\n#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk        /*!< Transceiver delay */\n\n#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)\n#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */\n#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk        /*!< Erratic error interrupt mask */\n\n#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)\n#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\n#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */\n#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\n#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\n\n/********************  Bit definition for USB_OTG_PCGCR register  ********************/\n#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)\n#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */\n#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)\n#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */\n#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)\n#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */\n\n/********************  Bit definition for USB_OTG_GOTGINT register  ********************/\n#define USB_OTG_GOTGINT_SEDET_Pos                (2U)\n#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */\n#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)\n#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */\n#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)\n#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */\n#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)\n#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */\n#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)\n#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */\n#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)\n#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */\n#define USB_OTG_GOTGINT_IDCHNG_Pos               (20U)\n#define USB_OTG_GOTGINT_IDCHNG_Msk               (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */\n#define USB_OTG_GOTGINT_IDCHNG                   USB_OTG_GOTGINT_IDCHNG_Msk    /*!< Change in ID pin input value           */\n\n/********************  Bit definition for USB_OTG_DCTL register  ********************/\n#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)\n#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */\n#define USB_OTG_DCTL_SDIS_Pos                    (1U)\n#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */\n#define USB_OTG_DCTL_GINSTS_Pos                  (2U)\n#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */\n#define USB_OTG_DCTL_GONSTS_Pos                  (3U)\n#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\n#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */\n\n#define USB_OTG_DCTL_TCTL_Pos                    (4U)\n#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\n#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */\n#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCTL_SGINAK_Pos                  (7U)\n#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */\n#define USB_OTG_DCTL_CGINAK_Pos                  (8U)\n#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */\n#define USB_OTG_DCTL_SGONAK_Pos                  (9U)\n#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */\n#define USB_OTG_DCTL_CGONAK_Pos                  (10U)\n#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\n#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */\n#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)\n#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */\n\n/********************  Bit definition for USB_OTG_HFIR register  ********************/\n#define USB_OTG_HFIR_FRIVL_Pos                   (0U)\n#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */\n\n/********************  Bit definition for USB_OTG_HFNUM register  ********************/\n#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)\n#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */\n#define USB_OTG_HFNUM_FTREM_Pos                  (16U)\n#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */\n\n/********************  Bit definition for USB_OTG_DSTS register  ********************/\n#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)\n#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */\n\n#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)\n#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\n#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */\n#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\n#define USB_OTG_DSTS_EERR_Pos                    (3U)\n#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\n#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */\n#define USB_OTG_DSTS_FNSOF_Pos                   (8U)\n#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\n#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */\n\n/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/\n#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)\n#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\n#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */\n#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)\n#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\n#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */\n#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */\n#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */\n#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */\n#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */\n#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */\n#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)\n#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */\n#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)\n#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */\n#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)\n#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\n#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */\n\n/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/\n\n#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)\n#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\n#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */\n#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\n#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\n#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\n#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)\n#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\n#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\n#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)\n#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\n#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */\n#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)\n#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\n#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */\n#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)\n#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\n#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */\n#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\n#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\n#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\n#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\n#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)\n#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */\n#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)\n#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\n#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */\n#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)\n#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\n#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */\n#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)\n#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\n#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */\n#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)\n#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\n#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */\n#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)\n#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\n#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */\n#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)\n#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\n#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */\n#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)\n#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\n#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */\n#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)\n#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\n#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */\n#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)\n#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\n#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */\n#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)\n#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */\n\n/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/\n#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)\n#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\n#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */\n#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)\n#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\n#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */\n#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)\n#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\n#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */\n#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)\n#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\n#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */\n#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)\n#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\n#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */\n\n\n#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)\n#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\n#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */\n#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\n#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\n#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)\n#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\n#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */\n#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)\n#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\n#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */\n\n/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/\n#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)\n#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)\n#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)\n#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)\n#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)\n#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/\n#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)\n#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */\n#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)\n#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */\n#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)\n#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */\n#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\n\n/********************  Bit definition for USB_OTG_HAINT register  ********************/\n#define USB_OTG_HAINT_HAINT_Pos                  (0U)\n#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */\n\n/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/\n#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask              */\n#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */\n#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)\n#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */\n#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */\n#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)\n#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */\n#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)\n#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */\n#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)\n#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */\n#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */\n#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)\n#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */\n#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)\n#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */\n#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)\n#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */\n#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)\n#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */\n#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)\n#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */\n/********************  Bit definition for USB_OTG_GINTSTS register  ********************/\n#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)\n#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\n#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */\n#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)\n#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */\n#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)\n#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */\n#define USB_OTG_GINTSTS_SOF_Pos                  (3U)\n#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */\n#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)\n#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */\n#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)\n#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */\n#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)\n#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */\n#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)\n#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */\n#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)\n#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */\n#define USB_OTG_GINTSTS_USBRST_Pos               (12U)\n#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */\n#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)\n#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */\n#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)\n#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */\n#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)\n#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */\n#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)\n#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */\n#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)\n#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */\n#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)\n#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */\n#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)\n#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */\n#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)\n#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */\n#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */\n#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)\n#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */\n#define USB_OTG_GINTSTS_HCINT_Pos                (25U)\n#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */\n#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)\n#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */\n#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)\n#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */\n#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */\n#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)\n#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */\n#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)\n#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */\n#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)\n#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */\n#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)\n#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */\n\n/********************  Bit definition for USB_OTG_GINTMSK register  ********************/\n#define USB_OTG_GINTMSK_MMISM_Pos                (1U)\n#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */\n#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)\n#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */\n#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)\n#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */\n#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)\n#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */\n#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)\n#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */\n#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)\n#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */\n#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)\n#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */\n#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)\n#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */\n#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)\n#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */\n#define USB_OTG_GINTMSK_USBRST_Pos               (12U)\n#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */\n#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)\n#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */\n#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)\n#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */\n#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)\n#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */\n#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)\n#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\n#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */\n#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)\n#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */\n#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)\n#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */\n#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)\n#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */\n#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)\n#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */\n#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)\n#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */\n#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */\n#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)\n#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */\n#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)\n#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */\n#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)\n#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */\n#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)\n#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */\n#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */\n#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)\n#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */\n#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)\n#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */\n#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)\n#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */\n#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)\n#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */\n\n/********************  Bit definition for USB_OTG_DAINT register  ********************/\n#define USB_OTG_DAINT_IEPINT_Pos                 (0U)\n#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */\n#define USB_OTG_DAINT_OEPINT_Pos                 (16U)\n#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */\n\n/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/\n#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)\n#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */\n\n/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/\n#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)\n#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\n#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */\n#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)\n#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\n#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)\n#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\n#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)\n#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/\n#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)\n#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */\n#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)\n#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/\n#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)\n#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/\n#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)\n#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */\n\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_NPTXFSA_Pos                      (0U)\n#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */\n#define USB_OTG_NPTXFD_Pos                       (16U)\n#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */\n#define USB_OTG_TX0FSA_Pos                       (0U)\n#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */\n#define USB_OTG_TX0FD_Pos                        (16U)\n#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */\n\n/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/\n#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)\n#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\n#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\n\n/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\n\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/\n#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)\n#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\n#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\n#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)\n#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\n#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */\n\n#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)\n#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\n#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */\n#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)\n#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\n#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */\n\n#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)\n#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */\n#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\n#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)\n#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\n#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */\n\n/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DEACHINT register  ********************/\n#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)\n#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */\n#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)\n#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */\n\n/********************  Bit definition for USB_OTG_GCCFG register  ********************/\n#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)\n#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\n#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */\n#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)\n#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< USB VBUS Detection Enable */\n\n/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\n\n/********************  Bit definition for USB_OTG_CID register  ********************/\n#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)\n#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */\n\n/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/\n#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)\n#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */\n#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */\n#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)\n#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */\n#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */\n#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)\n#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */\n#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */\n#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)\n#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */\n#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */\n#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)\n#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */\n#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)\n#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */\n#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */\n#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)\n#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */\n#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */\n#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)\n#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */\n#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */\n#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)\n#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */\n#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)\n#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */\n#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */\n#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)\n#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */\n#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)\n#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */\n#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */\n#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)\n#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */\n#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */\n#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)\n#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */\n#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */\n\n/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */\n#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPRT register  ********************/\n#define USB_OTG_HPRT_PCSTS_Pos                   (0U)\n#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */\n#define USB_OTG_HPRT_PCDET_Pos                   (1U)\n#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\n#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */\n#define USB_OTG_HPRT_PENA_Pos                    (2U)\n#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\n#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */\n#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)\n#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\n#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */\n#define USB_OTG_HPRT_POCA_Pos                    (4U)\n#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\n#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */\n#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)\n#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\n#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */\n#define USB_OTG_HPRT_PRES_Pos                    (6U)\n#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\n#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */\n#define USB_OTG_HPRT_PSUSP_Pos                   (7U)\n#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\n#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */\n#define USB_OTG_HPRT_PRST_Pos                    (8U)\n#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\n#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */\n\n#define USB_OTG_HPRT_PLSTS_Pos                   (10U)\n#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\n#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */\n#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\n#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_HPRT_PPWR_Pos                    (12U)\n#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */\n\n#define USB_OTG_HPRT_PTCTL_Pos                   (13U)\n#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\n#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */\n#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\n#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\n#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\n#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\n\n#define USB_OTG_HPRT_PSPD_Pos                    (17U)\n#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\n#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */\n#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\n\n/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */\n#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */\n#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */\n#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)\n#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */\n#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)\n#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */\n\n/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/\n#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)\n#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */\n#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)\n#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */\n\n/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/\n#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */\n#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */\n#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)\n#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\n#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */\n#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */\n\n#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */\n#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DIEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */\n\n#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)\n#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\n#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */\n#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\n#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\n#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\n#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\n#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */\n#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */\n#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */\n#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */\n#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */\n\n/********************  Bit definition for USB_OTG_HCCHAR register  ********************/\n#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)\n#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */\n\n#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)\n#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\n#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */\n#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\n#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)\n#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */\n#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)\n#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */\n\n#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)\n#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */\n#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\n\n#define USB_OTG_HCCHAR_MC_Pos                    (20U)\n#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\n#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */\n#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\n#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\n\n#define USB_OTG_HCCHAR_DAD_Pos                   (22U)\n#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\n#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */\n#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\n#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\n#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\n#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\n#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\n#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\n#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\n#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)\n#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */\n#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)\n#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */\n#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)\n#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */\n\n/********************  Bit definition for USB_OTG_HCSPLT register  ********************/\n\n#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)\n#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\n#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */\n#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\n\n#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)\n#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\n#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */\n#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\n\n#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)\n#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\n#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */\n#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)\n#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\n#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */\n#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)\n#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */\n\n/********************  Bit definition for USB_OTG_HCINT register  ********************/\n#define USB_OTG_HCINT_XFRC_Pos                   (0U)\n#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */\n#define USB_OTG_HCINT_CHH_Pos                    (1U)\n#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */\n#define USB_OTG_HCINT_AHBERR_Pos                 (2U)\n#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */\n#define USB_OTG_HCINT_STALL_Pos                  (3U)\n#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */\n#define USB_OTG_HCINT_NAK_Pos                    (4U)\n#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */\n#define USB_OTG_HCINT_ACK_Pos                    (5U)\n#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */\n#define USB_OTG_HCINT_NYET_Pos                   (6U)\n#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */\n#define USB_OTG_HCINT_TXERR_Pos                  (7U)\n#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */\n#define USB_OTG_HCINT_BBERR_Pos                  (8U)\n#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */\n#define USB_OTG_HCINT_FRMOR_Pos                  (9U)\n#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */\n#define USB_OTG_HCINT_DTERR_Pos                  (10U)\n#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */\n\n/********************  Bit definition for USB_OTG_DIEPINT register  ********************/\n#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)\n#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */\n#define USB_OTG_DIEPINT_TOC_Pos                  (3U)\n#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */\n#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)\n#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */\n#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)\n#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */\n#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */\n#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)\n#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */\n#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)\n#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\n#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\n#define USB_OTG_DIEPINT_BNA_Pos                  (9U)\n#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */\n#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)\n#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\n#define USB_OTG_DIEPINT_BERR_Pos                 (12U)\n#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\n#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */\n#define USB_OTG_DIEPINT_NAK_Pos                  (13U)\n#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */\n\n/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/\n#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)\n#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */\n#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)\n#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */\n#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)\n#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */\n#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)\n#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */\n#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)\n#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */\n#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)\n#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */\n#define USB_OTG_HCINTMSK_NYET_Pos                (6U)\n#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */\n#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)\n#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */\n#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)\n#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */\n#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)\n#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */\n#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)\n#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */\n\n/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/\n\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)\n#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */\n/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/\n#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)\n#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */\n#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)\n#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */\n#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)\n#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */\n#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)\n#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\n#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */\n#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/\n#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)\n#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_HCDMA register  ********************/\n#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)\n#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/\n#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)\n#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */\n\n/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/\n#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)\n#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */\n#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)\n#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/\n\n#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */\n#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */\n#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\n#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */\n#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */\n#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)\n#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\n#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */\n#define USB_OTG_DOEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */\n#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */\n#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */\n#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */\n\n/********************  Bit definition for USB_OTG_DOEPINT register  ********************/\n#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)\n#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */\n#define USB_OTG_DOEPINT_STUP_Pos                 (3U)\n#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */\n#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)\n#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */\n#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)\n#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */\n#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */\n#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)\n#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */\n#define USB_OTG_DOEPINT_NAK_Pos                  (13U)\n#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */\n#define USB_OTG_DOEPINT_NYET_Pos                 (14U)\n#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */\n#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)\n#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */\n/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/\n\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n\n#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)\n#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */\n#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for PCGCCTL register  ********************/\n#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)\n#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */\n#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)\n#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */\n#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)\n#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */\n\n/* Legacy define */\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_CHNUM_Pos                        (0U)\n#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\n#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\n#define USB_OTG_BCNT_Pos                         (4U)\n#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\n\n#define USB_OTG_DPID_Pos                         (15U)\n#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)    /*!< 0x00018000 */\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\n#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\n#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\n\n#define USB_OTG_PKTSTS_Pos                       (17U)\n#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\n#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\n#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\n#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\n#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\n\n#define USB_OTG_EPNUM_Pos                        (0U)\n#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\n#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\n\n#define USB_OTG_FRMNUM_Pos                       (21U)\n#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\n#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\n#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\n#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\n#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_macros\n  * @{\n  */\n\n/******************************* ADC Instances ********************************/\n#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \\\n                                       ((INSTANCE) == ADC2) || \\\n                                       ((INSTANCE) == ADC3))\n\n#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\n\n#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)\n\n/******************************* CAN Instances ********************************/\n#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \\\n                                       ((INSTANCE) == CAN2))\n/******************************* CRC Instances ********************************/\n#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\n\n/******************************* DAC Instances ********************************/\n#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)\n\n/******************************* DCMI Instances *******************************/\n#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)\n\n/******************************** DMA Instances *******************************/\n#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \\\n                                              ((INSTANCE) == DMA1_Stream1) || \\\n                                              ((INSTANCE) == DMA1_Stream2) || \\\n                                              ((INSTANCE) == DMA1_Stream3) || \\\n                                              ((INSTANCE) == DMA1_Stream4) || \\\n                                              ((INSTANCE) == DMA1_Stream5) || \\\n                                              ((INSTANCE) == DMA1_Stream6) || \\\n                                              ((INSTANCE) == DMA1_Stream7) || \\\n                                              ((INSTANCE) == DMA2_Stream0) || \\\n                                              ((INSTANCE) == DMA2_Stream1) || \\\n                                              ((INSTANCE) == DMA2_Stream2) || \\\n                                              ((INSTANCE) == DMA2_Stream3) || \\\n                                              ((INSTANCE) == DMA2_Stream4) || \\\n                                              ((INSTANCE) == DMA2_Stream5) || \\\n                                              ((INSTANCE) == DMA2_Stream6) || \\\n                                              ((INSTANCE) == DMA2_Stream7))\n\n/******************************* GPIO Instances *******************************/\n#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\\n                                        ((INSTANCE) == GPIOB) || \\\n                                        ((INSTANCE) == GPIOC) || \\\n                                        ((INSTANCE) == GPIOD) || \\\n                                        ((INSTANCE) == GPIOE) || \\\n                                        ((INSTANCE) == GPIOF) || \\\n                                        ((INSTANCE) == GPIOG) || \\\n                                        ((INSTANCE) == GPIOH))\n\n/******************************** I2C Instances *******************************/\n#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\n                                       ((INSTANCE) == I2C2) || \\\n                                       ((INSTANCE) == I2C3))\n\n/******************************* SMBUS Instances ******************************/\n#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE\n\n/******************************** I2S Instances *******************************/\n#define IS_I2S_APB1_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \\\n                                         ((INSTANCE) == SPI3))\n\n#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI1) || \\\n                                        ((INSTANCE) == SPI2) || \\\n                                        ((INSTANCE) == SPI3))\n\n\n\n/****************************** RTC Instances *********************************/\n#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\n\n/******************************* SAI Instances ********************************/\n#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A)  || \\\n                                     ((PERIPH) == SAI1_Block_B)  || \\\n                                     ((PERIPH) == SAI2_Block_A)  || \\\n                                     ((PERIPH) == SAI2_Block_B))\n/* Legacy define */\n\n#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE\n\n/******************************** SPI Instances *******************************/\n#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\\n                                       ((INSTANCE) == SPI2) || \\\n                                       ((INSTANCE) == SPI3) || \\\n                                       ((INSTANCE) == SPI4))\n\n\n/****************** TIM Instances : All supported instances *******************/\n#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                    ((INSTANCE) == TIM2) || \\\n                                    ((INSTANCE) == TIM3) || \\\n                                    ((INSTANCE) == TIM4) || \\\n                                    ((INSTANCE) == TIM5) || \\\n                                    ((INSTANCE) == TIM6) || \\\n                                    ((INSTANCE) == TIM7) || \\\n                                    ((INSTANCE) == TIM8) || \\\n                                    ((INSTANCE) == TIM9) || \\\n                                    ((INSTANCE) == TIM10)|| \\\n                                    ((INSTANCE) == TIM11)|| \\\n                                    ((INSTANCE) == TIM12)|| \\\n                                    ((INSTANCE) == TIM13)|| \\\n                                    ((INSTANCE) == TIM14))\n\n/************* TIM Instances : at least 1 capture/compare channel *************/\n#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \\\n                                         ((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM3)  || \\\n                                         ((INSTANCE) == TIM4)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM8)  || \\\n                                         ((INSTANCE) == TIM9)  || \\\n                                         ((INSTANCE) == TIM10) || \\\n                                         ((INSTANCE) == TIM11) || \\\n                                         ((INSTANCE) == TIM12) || \\\n                                         ((INSTANCE) == TIM13) || \\\n                                         ((INSTANCE) == TIM14))\n\n/************ TIM Instances : at least 2 capture/compare channels *************/\n#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8) || \\\n                                       ((INSTANCE) == TIM9) || \\\n                                       ((INSTANCE) == TIM12))\n\n/************ TIM Instances : at least 3 capture/compare channels *************/\n#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/************ TIM Instances : at least 4 capture/compare channels *************/\n#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : Advanced-control timers *****************/\n#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                           ((INSTANCE) == TIM8))\n\n/******************* TIM Instances : Timer input XOR function *****************/\n#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : DMA requests generation (UDE) *************/\n#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM6) || \\\n                                       ((INSTANCE) == TIM7) || \\\n                                       ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (CCxDE) *****************/\n#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (COMDE) *****************/\n#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : DMA burst feature ***********************/\n#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                             ((INSTANCE) == TIM2) || \\\n                                             ((INSTANCE) == TIM3) || \\\n                                             ((INSTANCE) == TIM4) || \\\n                                             ((INSTANCE) == TIM5) || \\\n                                             ((INSTANCE) == TIM8))\n\n/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\n#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                          ((INSTANCE) == TIM2)  || \\\n                                          ((INSTANCE) == TIM3)  || \\\n                                          ((INSTANCE) == TIM4)  || \\\n                                          ((INSTANCE) == TIM5)  || \\\n                                          ((INSTANCE) == TIM6)  || \\\n                                          ((INSTANCE) == TIM7)  || \\\n                                          ((INSTANCE) == TIM8))\n\n/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\n#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8) || \\\n                                         ((INSTANCE) == TIM9) || \\\n                                         ((INSTANCE) == TIM12))\n/********************** TIM Instances : 32 bit Counter ************************/\n#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \\\n                                              ((INSTANCE) == TIM5))\n\n/***************** TIM Instances : external trigger input availabe ************/\n#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                        ((INSTANCE) == TIM2) || \\\n                                        ((INSTANCE) == TIM3) || \\\n                                        ((INSTANCE) == TIM4) || \\\n                                        ((INSTANCE) == TIM5) || \\\n                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : remapping capability **********************/\n#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM11))\n\n/******************* TIM Instances : output(s) available **********************/\n#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\\n    ((((INSTANCE) == TIM1) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM2) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM3) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM4) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM5) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM8) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM9) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM10) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM11) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM12) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM13) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM14) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1))))\n\n/************ TIM Instances : complementary output(s) available ***************/\n#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\\n   ((((INSTANCE) == TIM1) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3)))            \\\n    ||                                          \\\n    (((INSTANCE) == TIM8) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3))))\n\n/****************** TIM Instances : supporting counting mode selection ********/\n#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting clock division *****************/\n#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                                  ((INSTANCE) == TIM2) || \\\n                                                  ((INSTANCE) == TIM3) || \\\n                                                  ((INSTANCE) == TIM4) || \\\n                                                  ((INSTANCE) == TIM5) || \\\n                                                  ((INSTANCE) == TIM8) || \\\n                                                  ((INSTANCE) == TIM9) || \\\n                                                  ((INSTANCE) == TIM10)|| \\\n                                                  ((INSTANCE) == TIM11)|| \\\n                                                  ((INSTANCE) == TIM12)|| \\\n                                                  ((INSTANCE) == TIM13)|| \\\n                                                  ((INSTANCE) == TIM14))\n\n/****************** TIM Instances : supporting commutation event generation ***/\n#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \\\n                                                     ((INSTANCE) == TIM8))\n\n\n/****************** TIM Instances : supporting OCxREF clear *******************/\n#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM2) || \\\n                                                       ((INSTANCE) == TIM3) || \\\n                                                       ((INSTANCE) == TIM4) || \\\n                                                       ((INSTANCE) == TIM5) || \\\n                                                       ((INSTANCE) == TIM8))\n\n/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8))\n\n/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/\n#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/********** TIM Instances : supporting internal trigger inputs(ITRX) *********/\n#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/****************** TIM Instances : supporting repetition counter *************/\n#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting encoder interface **************/\n#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                      ((INSTANCE) == TIM2) || \\\n                                                      ((INSTANCE) == TIM3) || \\\n                                                      ((INSTANCE) == TIM4) || \\\n                                                      ((INSTANCE) == TIM5) || \\\n                                                      ((INSTANCE) == TIM8) || \\\n                                                      ((INSTANCE) == TIM9) || \\\n                                                      ((INSTANCE) == TIM12))\n/****************** TIM Instances : supporting Hall sensor interface **********/\n#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                          ((INSTANCE) == TIM2) || \\\n                                                          ((INSTANCE) == TIM3) || \\\n                                                          ((INSTANCE) == TIM4) || \\\n                                                          ((INSTANCE) == TIM5) || \\\n                                                          ((INSTANCE) == TIM8))\n/****************** TIM Instances : supporting the break function *************/\n#define IS_TIM_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM8))\n\n/******************** USART Instances : Synchronous mode **********************/\n#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                     ((INSTANCE) == USART2) || \\\n                                     ((INSTANCE) == USART3) || \\\n                                     ((INSTANCE) == USART6))\n\n/******************** UART Instances : Half-Duplex mode **********************/\n#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                               ((INSTANCE) == USART2) || \\\n                                               ((INSTANCE) == USART3) || \\\n                                               ((INSTANCE) == UART4)  || \\\n                                               ((INSTANCE) == UART5)  || \\\n                                               ((INSTANCE) == USART6))\n\n/* Legacy defines */\n#define IS_UART_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE\n\n/****************** UART Instances : Hardware Flow control ********************/\n#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                           ((INSTANCE) == USART2) || \\\n                                           ((INSTANCE) == USART3) || \\\n                                           ((INSTANCE) == UART4)  || \\\n                                           ((INSTANCE) == UART5)  || \\\n                                           ((INSTANCE) == USART6))\n/******************** UART Instances : LIN mode **********************/\n#define IS_UART_LIN_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE\n\n/********************* UART Instances : Smart card mode ***********************/\n#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                         ((INSTANCE) == USART2) || \\\n                                         ((INSTANCE) == USART3) || \\\n                                         ((INSTANCE) == USART6))\n\n/*********************** UART Instances : IRDA mode ***************************/\n#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2) || \\\n                                    ((INSTANCE) == USART3) || \\\n                                    ((INSTANCE) == UART4)  || \\\n                                    ((INSTANCE) == UART5)  || \\\n                                    ((INSTANCE) == USART6))\n\n\n/*********************** PCD Instances ****************************************/\n#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\\n                                       ((INSTANCE) == USB_OTG_HS))\n\n/*********************** HCD Instances ****************************************/\n#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\\n                                       ((INSTANCE) == USB_OTG_HS))\n\n/****************************** SDIO Instances ********************************/\n#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)\n\n/****************************** IWDG Instances ********************************/\n#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)\n\n/****************************** WWDG Instances ********************************/\n#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)\n\n\n/****************************** QSPI Instances ********************************/\n#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)\n\n/******************************* CEC Instances ********************************/\n#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)\n\n/***************************** FMPI2C Instances *******************************/\n#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)\n#define IS_FMPSMBUS_ALL_INSTANCE         IS_FMPI2C_ALL_INSTANCE\n\n/******************************* SPDIFRX Instances ********************************/\n#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)\n/****************************** USB Exported Constants ************************/\n#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U\n#define USB_OTG_FS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */\n#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */\n#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */\n#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                16U\n#define USB_OTG_HS_MAX_IN_ENDPOINTS                    9U    /* Including EP0 */\n#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   9U    /* Including EP0 */\n#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */\n\n/*\n * @brief Specific devices reset values definitions\n */\n#define RCC_PLLCFGR_RST_VALUE              0x24003010U\n#define RCC_PLLI2SCFGR_RST_VALUE           0x24003010U\n#define RCC_PLLSAICFGR_RST_VALUE           0x04003010U\n\n#define RCC_MAX_FREQUENCY           180000000U         /*!< Max frequency of family in Hz*/\n#define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */\n#define RCC_MAX_FREQUENCY_SCALE2    168000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */\n#define RCC_MAX_FREQUENCY_SCALE3    120000000U         /*!< Maximum frequency for system clock at power scale3, in Hz */\n#define RCC_PLLVCO_OUTPUT_MIN       100000000U       /*!< Frequency min for PLLVCO output, in Hz */\n#define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */\n\n#define RCC_PLLN_MIN_VALUE                 50U\n#define RCC_PLLN_MAX_VALUE                432U\n\n#define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */\n#define FLASH_SCALE1_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */\n#define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */\n#define FLASH_SCALE1_LATENCY4_FREQ   120000000U     /*!< HCLK frequency to set FLASH latency 4 in power scale 1  */\n#define FLASH_SCALE1_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */\n\n#define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */\n#define FLASH_SCALE2_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */\n#define FLASH_SCALE2_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */\n#define FLASH_SCALE2_LATENCY4_FREQ   12000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 2  */\n#define FLASH_SCALE2_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 2  */\n\n#define FLASH_SCALE3_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */\n#define FLASH_SCALE3_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */\n#define FLASH_SCALE3_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 3  */\n\n/******************************************************************************/\n/*  For a painless codes migration between the STM32F4xx device product       */\n/*  lines, the aliases defined below are put in place to overcome the         */\n/*  differences in the interrupt handlers and IRQn definitions.               */\n/*  No need to update developed interrupt code when moving across             */\n/*  product lines within the same STM32F4 Family                              */\n/******************************************************************************/\n/* Aliases for __IRQn */\n#define FSMC_IRQn              FMC_IRQn\n\n/* Aliases for __IRQHandler */\n#define FSMC_IRQHandler        FMC_IRQHandler\n#define QuadSPI_IRQHandler     QUADSPI_IRQHandler\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32F446xx_H */\n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f469xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f469xx.h\n  * @author  MCD Application Team\n  * @version V2.6.1\n  * @date    14-February-2017\n  * @brief   CMSIS STM32F469xx Device Peripheral Access Layer Header File.\n  *\n  *          This file contains:\n  *           - Data structures and the address mapping for all peripherals\n  *           - peripherals registers declarations and bits definition\n  *           - Macros to access peripheral's registers hardware\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS_Device\n  * @{\n  */\n\n/** @addtogroup stm32f469xx\n  * @{\n  */\n\n#ifndef __STM32F469xx_H\n#define __STM32F469xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Configuration_section_for_CMSIS\n  * @{\n  */\n\n/**\n  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals\n  */\n#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */\n#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */\n#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */\n#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */\n#define __FPU_PRESENT             1U       /*!< FPU present                                   */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_interrupt_number_definition\n  * @{\n  */\n\n/**\n * @brief STM32F4XX Interrupt Number Definition, according to the selected device\n *        in @ref Library_configuration_section\n */\ntypedef enum\n{\n/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */\n  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */\n  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */\n  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */\n  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */\n  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */\n/******  STM32 specific Interrupt Numbers **********************************************************************/\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */\n  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */\n  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\n  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\n  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\n  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\n  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\n  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\n  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\n  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\n  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\n  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */\n  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */\n  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */\n  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */\n  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */\n  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */\n  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */\n  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */\n  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */\n  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */\n  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */\n  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\n  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */\n  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */\n  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\n  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\n  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */\n  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */\n  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */\n  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\n  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */\n  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */\n  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */\n  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\n  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */\n  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */\n  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */\n  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */\n  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */\n  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */\n  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */\n  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */\n  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */\n  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */\n  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */\n  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */\n  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */\n  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */\n  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */\n  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */\n  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */\n  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */\n  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */\n  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */\n  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\n  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\n  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */\n  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */\n  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */\n  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */\n  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */\n  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */\n  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */\n  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */\n  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */\n  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */\n  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */\n  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */\n  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */\n  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                              */\n  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                        */\n  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */\n  QUADSPI_IRQn                = 91,     /*!< QUADSPI global Interrupt                                          */\n  DSI_IRQn                    = 92      /*!< DSI global Interrupt                                              */\n} IRQn_Type;\n\n/**\n  * @}\n  */\n\n#include \"core_cm4.h\"             /* Cortex-M4 processor and core peripherals */\n#include \"system_stm32f4xx.h\"\n#include <sys/stdint.h>\n\n/** @addtogroup Peripheral_registers_structures\n  * @{\n  */\n\n/**\n  * @brief Analog to Digital Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */\n  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */\n  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */\n  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */\n  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */\n  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\n  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\n  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\n  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\n  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */\n  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */\n  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */\n  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */\n  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */\n  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/\n  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */\n  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */\n  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */\n  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */\n  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */\n} ADC_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */\n  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */\n  __IO uint32_t CDR;    /*!< ADC common regular data register for dual\n                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */\n} ADC_Common_TypeDef;\n\n\n/**\n  * @brief Controller Area Network TxMailBox\n  */\n\ntypedef struct\n{\n  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */\n  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\n  __IO uint32_t TDLR; /*!< CAN mailbox data low register */\n  __IO uint32_t TDHR; /*!< CAN mailbox data high register */\n} CAN_TxMailBox_TypeDef;\n\n/**\n  * @brief Controller Area Network FIFOMailBox\n  */\n\ntypedef struct\n{\n  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */\n  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\n  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\n  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\n} CAN_FIFOMailBox_TypeDef;\n\n/**\n  * @brief Controller Area Network FilterRegister\n  */\n\ntypedef struct\n{\n  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\n  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\n} CAN_FilterRegister_TypeDef;\n\n/**\n  * @brief Controller Area Network\n  */\n\ntypedef struct\n{\n  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */\n  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */\n  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */\n  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */\n  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */\n  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */\n  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */\n  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */\n  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */\n  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */\n  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */\n  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */\n  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */\n  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */\n  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */\n  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */\n  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */\n  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */\n  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */\n  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */\n  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */\n  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */\n} CAN_TypeDef;\n\n/**\n  * @brief CRC calculation unit\n  */\n\ntypedef struct\n{\n  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */\n  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */\n  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */\n  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */\n  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */\n} CRC_TypeDef;\n\n/**\n  * @brief Digital to Analog Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */\n  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */\n  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\n  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */\n  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */\n  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\n  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */\n  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */\n  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */\n  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */\n  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */\n  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */\n  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */\n  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */\n} DAC_TypeDef;\n\n/**\n  * @brief Debug MCU\n  */\n\ntypedef struct\n{\n  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */\n  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */\n  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */\n  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */\n}DBGMCU_TypeDef;\n\n/**\n  * @brief DCMI\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */\n  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */\n  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */\n  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */\n  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */\n  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */\n  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */\n  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */\n  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */\n  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */\n  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */\n} DCMI_TypeDef;\n\n/**\n  * @brief DMA Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;     /*!< DMA stream x configuration register      */\n  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */\n  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */\n  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */\n  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */\n  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */\n} DMA_Stream_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */\n  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */\n  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */\n  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\n} DMA_TypeDef;\n\n/**\n  * @brief DMA2D Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */\n  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */\n  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */\n  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */\n  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */\n  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */\n  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */\n  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */\n  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */\n  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */\n  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */\n  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */\n  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */\n  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */\n  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */\n  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */\n  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */\n  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */\n  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */\n  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */\n  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */\n  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */\n  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */\n} DMA2D_TypeDef;\n\n/**\n  * @brief DSI Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t VR;            /*!< DSI Host Version Register,                                 Address offset: 0x00        */\n  __IO uint32_t CR;            /*!< DSI Host Control Register,                                 Address offset: 0x04        */\n  __IO uint32_t CCR;           /*!< DSI HOST Clock Control Register,                           Address offset: 0x08        */\n  __IO uint32_t LVCIDR;        /*!< DSI Host LTDC VCID Register,                               Address offset: 0x0C        */\n  __IO uint32_t LCOLCR;        /*!< DSI Host LTDC Color Coding Register,                       Address offset: 0x10        */\n  __IO uint32_t LPCR;          /*!< DSI Host LTDC Polarity Configuration Register,             Address offset: 0x14        */\n  __IO uint32_t LPMCR;         /*!< DSI Host Low-Power Mode Configuration Register,            Address offset: 0x18        */\n  uint32_t      RESERVED0[4];  /*!< Reserved, 0x1C - 0x2B                                                                  */\n  __IO uint32_t PCR;           /*!< DSI Host Protocol Configuration Register,                  Address offset: 0x2C        */\n  __IO uint32_t GVCIDR;        /*!< DSI Host Generic VCID Register,                            Address offset: 0x30        */\n  __IO uint32_t MCR;           /*!< DSI Host Mode Configuration Register,                      Address offset: 0x34        */\n  __IO uint32_t VMCR;          /*!< DSI Host Video Mode Configuration Register,                Address offset: 0x38        */\n  __IO uint32_t VPCR;          /*!< DSI Host Video Packet Configuration Register,              Address offset: 0x3C        */\n  __IO uint32_t VCCR;          /*!< DSI Host Video Chunks Configuration Register,              Address offset: 0x40        */\n  __IO uint32_t VNPCR;         /*!< DSI Host Video Null Packet Configuration Register,         Address offset: 0x44        */\n  __IO uint32_t VHSACR;        /*!< DSI Host Video HSA Configuration Register,                 Address offset: 0x48        */\n  __IO uint32_t VHBPCR;        /*!< DSI Host Video HBP Configuration Register,                 Address offset: 0x4C        */\n  __IO uint32_t VLCR;          /*!< DSI Host Video Line Configuration Register,                Address offset: 0x50        */\n  __IO uint32_t VVSACR;        /*!< DSI Host Video VSA Configuration Register,                 Address offset: 0x54        */\n  __IO uint32_t VVBPCR;        /*!< DSI Host Video VBP Configuration Register,                 Address offset: 0x58        */\n  __IO uint32_t VVFPCR;        /*!< DSI Host Video VFP Configuration Register,                 Address offset: 0x5C        */\n  __IO uint32_t VVACR;         /*!< DSI Host Video VA Configuration Register,                  Address offset: 0x60        */\n  __IO uint32_t LCCR;          /*!< DSI Host LTDC Command Configuration Register,              Address offset: 0x64        */\n  __IO uint32_t CMCR;          /*!< DSI Host Command Mode Configuration Register,              Address offset: 0x68        */\n  __IO uint32_t GHCR;          /*!< DSI Host Generic Header Configuration Register,            Address offset: 0x6C        */\n  __IO uint32_t GPDR;          /*!< DSI Host Generic Payload Data Register,                    Address offset: 0x70        */\n  __IO uint32_t GPSR;          /*!< DSI Host Generic Packet Status Register,                   Address offset: 0x74        */\n  __IO uint32_t TCCR[6];       /*!< DSI Host Timeout Counter Configuration Register,           Address offset: 0x78-0x8F   */\n  __IO uint32_t TDCR;          /*!< DSI Host 3D Configuration Register,                        Address offset: 0x90        */\n  __IO uint32_t CLCR;          /*!< DSI Host Clock Lane Configuration Register,                Address offset: 0x94        */\n  __IO uint32_t CLTCR;         /*!< DSI Host Clock Lane Timer Configuration Register,          Address offset: 0x98        */\n  __IO uint32_t DLTCR;         /*!< DSI Host Data Lane Timer Configuration Register,           Address offset: 0x9C        */\n  __IO uint32_t PCTLR;         /*!< DSI Host PHY Control Register,                             Address offset: 0xA0        */\n  __IO uint32_t PCONFR;        /*!< DSI Host PHY Configuration Register,                       Address offset: 0xA4        */\n  __IO uint32_t PUCR;          /*!< DSI Host PHY ULPS Control Register,                        Address offset: 0xA8        */\n  __IO uint32_t PTTCR;         /*!< DSI Host PHY TX Triggers Configuration Register,           Address offset: 0xAC        */\n  __IO uint32_t PSR;           /*!< DSI Host PHY Status Register,                              Address offset: 0xB0        */\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0xB4 - 0xBB                                                                  */\n  __IO uint32_t ISR[2];        /*!< DSI Host Interrupt & Status Register,                      Address offset: 0xBC-0xC3   */\n  __IO uint32_t IER[2];        /*!< DSI Host Interrupt Enable Register,                        Address offset: 0xC4-0xCB   */\n  uint32_t      RESERVED2[3];  /*!< Reserved, 0xD0 - 0xD7                                                                  */\n  __IO uint32_t FIR[2];        /*!< DSI Host Force Interrupt Register,                         Address offset: 0xD8-0xDF   */\n  uint32_t      RESERVED3[8];  /*!< Reserved, 0xE0 - 0xFF                                                                  */\n  __IO uint32_t VSCR;          /*!< DSI Host Video Shadow Control Register,                    Address offset: 0x100       */\n  uint32_t      RESERVED4[2];  /*!< Reserved, 0x104 - 0x10B                                                                */\n  __IO uint32_t LCVCIDR;       /*!< DSI Host LTDC Current VCID Register,                       Address offset: 0x10C       */\n  __IO uint32_t LCCCR;         /*!< DSI Host LTDC Current Color Coding Register,               Address offset: 0x110       */\n  uint32_t      RESERVED5;     /*!< Reserved, 0x114                                                                        */\n  __IO uint32_t LPMCCR;        /*!< DSI Host Low-power Mode Current Configuration Register,    Address offset: 0x118       */\n  uint32_t      RESERVED6[7];  /*!< Reserved, 0x11C - 0x137                                                                */\n  __IO uint32_t VMCCR;         /*!< DSI Host Video Mode Current Configuration Register,        Address offset: 0x138       */\n  __IO uint32_t VPCCR;         /*!< DSI Host Video Packet Current Configuration Register,      Address offset: 0x13C       */\n  __IO uint32_t VCCCR;         /*!< DSI Host Video Chuncks Current Configuration Register,     Address offset: 0x140       */\n  __IO uint32_t VNPCCR;        /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144       */\n  __IO uint32_t VHSACCR;       /*!< DSI Host Video HSA Current Configuration Register,         Address offset: 0x148       */\n  __IO uint32_t VHBPCCR;       /*!< DSI Host Video HBP Current Configuration Register,         Address offset: 0x14C       */\n  __IO uint32_t VLCCR;         /*!< DSI Host Video Line Current Configuration Register,        Address offset: 0x150       */\n  __IO uint32_t VVSACCR;       /*!< DSI Host Video VSA Current Configuration Register,         Address offset: 0x154       */\n  __IO uint32_t VVBPCCR;       /*!< DSI Host Video VBP Current Configuration Register,         Address offset: 0x158       */\n  __IO uint32_t VVFPCCR;       /*!< DSI Host Video VFP Current Configuration Register,         Address offset: 0x15C       */\n  __IO uint32_t VVACCR;        /*!< DSI Host Video VA Current Configuration Register,          Address offset: 0x160       */\n  uint32_t      RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F                                                                */\n  __IO uint32_t TDCCR;         /*!< DSI Host 3D Current Configuration Register,                Address offset: 0x190       */\n  uint32_t      RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF                                                               */\n  __IO uint32_t WCFGR;          /*!< DSI Wrapper Configuration Register,                       Address offset: 0x400       */\n  __IO uint32_t WCR;            /*!< DSI Wrapper Control Register,                             Address offset: 0x404       */\n  __IO uint32_t WIER;           /*!< DSI Wrapper Interrupt Enable Register,                    Address offset: 0x408       */\n  __IO uint32_t WISR;           /*!< DSI Wrapper Interrupt and Status Register,                Address offset: 0x40C       */\n  __IO uint32_t WIFCR;          /*!< DSI Wrapper Interrupt Flag Clear Register,                Address offset: 0x410       */\n  uint32_t      RESERVED9;      /*!< Reserved, 0x414                                                                       */\n  __IO uint32_t WPCR[5];        /*!< DSI Wrapper PHY Configuration Register,                   Address offset: 0x418-0x42B */\n  uint32_t      RESERVED10;     /*!< Reserved, 0x42C                                                                       */\n  __IO uint32_t WRPCR;          /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430                 */\n} DSI_TypeDef;\n\n/**\n  * @brief Ethernet MAC\n  */\n\ntypedef struct\n{\n  __IO uint32_t MACCR;\n  __IO uint32_t MACFFR;\n  __IO uint32_t MACHTHR;\n  __IO uint32_t MACHTLR;\n  __IO uint32_t MACMIIAR;\n  __IO uint32_t MACMIIDR;\n  __IO uint32_t MACFCR;\n  __IO uint32_t MACVLANTR;             /*    8 */\n  uint32_t      RESERVED0[2];\n  __IO uint32_t MACRWUFFR;             /*   11 */\n  __IO uint32_t MACPMTCSR;\n  uint32_t      RESERVED1;\n  __IO uint32_t MACDBGR;\n  __IO uint32_t MACSR;                 /*   15 */\n  __IO uint32_t MACIMR;\n  __IO uint32_t MACA0HR;\n  __IO uint32_t MACA0LR;\n  __IO uint32_t MACA1HR;\n  __IO uint32_t MACA1LR;\n  __IO uint32_t MACA2HR;\n  __IO uint32_t MACA2LR;\n  __IO uint32_t MACA3HR;\n  __IO uint32_t MACA3LR;               /*   24 */\n  uint32_t      RESERVED2[40];\n  __IO uint32_t MMCCR;                 /*   65 */\n  __IO uint32_t MMCRIR;\n  __IO uint32_t MMCTIR;\n  __IO uint32_t MMCRIMR;\n  __IO uint32_t MMCTIMR;               /*   69 */\n  uint32_t      RESERVED3[14];\n  __IO uint32_t MMCTGFSCCR;            /*   84 */\n  __IO uint32_t MMCTGFMSCCR;\n  uint32_t      RESERVED4[5];\n  __IO uint32_t MMCTGFCR;\n  uint32_t      RESERVED5[10];\n  __IO uint32_t MMCRFCECR;\n  __IO uint32_t MMCRFAECR;\n  uint32_t      RESERVED6[10];\n  __IO uint32_t MMCRGUFCR;\n  uint32_t      RESERVED7[334];\n  __IO uint32_t PTPTSCR;\n  __IO uint32_t PTPSSIR;\n  __IO uint32_t PTPTSHR;\n  __IO uint32_t PTPTSLR;\n  __IO uint32_t PTPTSHUR;\n  __IO uint32_t PTPTSLUR;\n  __IO uint32_t PTPTSAR;\n  __IO uint32_t PTPTTHR;\n  __IO uint32_t PTPTTLR;\n  __IO uint32_t RESERVED8;\n  __IO uint32_t PTPTSSR;\n  uint32_t      RESERVED9[565];\n  __IO uint32_t DMABMR;\n  __IO uint32_t DMATPDR;\n  __IO uint32_t DMARPDR;\n  __IO uint32_t DMARDLAR;\n  __IO uint32_t DMATDLAR;\n  __IO uint32_t DMASR;\n  __IO uint32_t DMAOMR;\n  __IO uint32_t DMAIER;\n  __IO uint32_t DMAMFBOCR;\n  __IO uint32_t DMARSWTR;\n  uint32_t      RESERVED10[8];\n  __IO uint32_t DMACHTDR;\n  __IO uint32_t DMACHRDR;\n  __IO uint32_t DMACHTBAR;\n  __IO uint32_t DMACHRBAR;\n} ETH_TypeDef;\n\n/**\n  * @brief External Interrupt/Event Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */\n  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */\n  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */\n  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\n  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */\n  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */\n} EXTI_TypeDef;\n\n/**\n  * @brief FLASH Registers\n  */\n\ntypedef struct\n{\n  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */\n  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */\n  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */\n  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */\n  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */\n  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */\n  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */\n} FLASH_TypeDef;\n\n/**\n  * @brief Flexible Memory Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\n} FMC_Bank1_TypeDef;\n\n/**\n  * @brief Flexible Memory Controller Bank1E\n  */\n\ntypedef struct\n{\n  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\n} FMC_Bank1E_TypeDef;\n\n/**\n  * @brief Flexible Memory Controller Bank3\n  */\n\ntypedef struct\n{\n  __IO uint32_t PCR;       /*!< NAND Flash control register,                       Address offset: 0x80 */\n  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */\n  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */\n  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */\n  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                          */\n  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */\n} FMC_Bank3_TypeDef;\n\n/**\n  * @brief Flexible Memory Controller Bank5_6\n  */\n\ntypedef struct\n{\n  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */\n  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */\n  __IO uint32_t SDCMR;          /*!< SDRAM Command Mode register,   Address offset: 0x150        */\n  __IO uint32_t SDRTR;          /*!< SDRAM Refresh Timer register,  Address offset: 0x154        */\n  __IO uint32_t SDSR;           /*!< SDRAM Status register,         Address offset: 0x158        */\n} FMC_Bank5_6_TypeDef;\n\n/**\n  * @brief General Purpose I/O\n  */\n\ntypedef struct\n{\n  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */\n  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */\n  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */\n  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\n  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */\n  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */\n  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */\n  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */\n  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\n} GPIO_TypeDef;\n\n/**\n  * @brief System configuration controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */\n  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */\n  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\n  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */\n  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */\n} SYSCFG_TypeDef;\n\n/**\n  * @brief Inter-integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */\n  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */\n  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */\n  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */\n  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */\n  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */\n  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */\n  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */\n  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */\n} I2C_TypeDef;\n\n/**\n  * @brief Independent WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */\n  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */\n  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */\n  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */\n} IWDG_TypeDef;\n\n/**\n  * @brief LCD-TFT Display Controller\n  */\n\ntypedef struct\n{\n  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */\n  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */\n  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */\n  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */\n  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */\n  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */\n  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */\n  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */\n  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */\n  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */\n  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */\n  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */\n  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */\n  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */\n  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */\n  __IO uint32_t CDSR;          /*!< LTDC Current Display Status Register,                Address offset: 0x48 */\n} LTDC_TypeDef;\n\n/**\n  * @brief LCD-TFT Display layer x Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */\n  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */\n  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */\n  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */\n  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */\n  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */\n  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */\n  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */\n  uint32_t      RESERVED0[2];  /*!< Reserved                                                                           */\n  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */\n  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */\n  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */\n  uint32_t      RESERVED1[3];  /*!< Reserved                                                                           */\n  __IO uint32_t CLUTWR;        /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144*/\n} LTDC_Layer_TypeDef;\n\n/**\n  * @brief Power Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */\n  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */\n} PWR_TypeDef;\n\n/**\n  * @brief Reset and Clock Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */\n  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */\n  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */\n  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */\n  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */\n  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */\n  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */\n  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */\n  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */\n  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */\n  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */\n  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */\n  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */\n  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */\n  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */\n  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */\n  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */\n  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\n  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\n  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\n  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */\n  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\n  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\n  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */\n  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */\n  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */\n  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */\n  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */\n  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */\n  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */\n  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */\n} RCC_TypeDef;\n\n/**\n  * @brief Real-Time Clock\n  */\n\ntypedef struct\n{\n  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */\n  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */\n  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */\n  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */\n  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */\n  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */\n  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */\n  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */\n  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */\n  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */\n  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */\n  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */\n  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */\n  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */\n  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */\n  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */\n  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */\n  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */\n  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */\n  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */\n  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */\n  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */\n  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */\n  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */\n  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */\n  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */\n  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */\n  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */\n  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */\n  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */\n  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */\n  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */\n  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */\n  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */\n  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */\n  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */\n  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */\n  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */\n  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */\n  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */\n} RTC_TypeDef;\n\n/**\n  * @brief Serial Audio Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */\n} SAI_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */\n  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */\n  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */\n  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */\n  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */\n  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */\n  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */\n  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */\n} SAI_Block_TypeDef;\n\n/**\n  * @brief SD host Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t POWER;                 /*!< SDIO power control register,    Address offset: 0x00 */\n  __IO uint32_t CLKCR;                 /*!< SDI clock control register,     Address offset: 0x04 */\n  __IO uint32_t ARG;                   /*!< SDIO argument register,         Address offset: 0x08 */\n  __IO uint32_t CMD;                   /*!< SDIO command register,          Address offset: 0x0C */\n  __IO const uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */\n  __IO const uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */\n  __IO const uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */\n  __IO const uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */\n  __IO const uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */\n  __IO uint32_t DTIMER;                /*!< SDIO data timer register,       Address offset: 0x24 */\n  __IO uint32_t DLEN;                  /*!< SDIO data length register,      Address offset: 0x28 */\n  __IO uint32_t DCTRL;                 /*!< SDIO data control register,     Address offset: 0x2C */\n  __IO const uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */\n  __IO const uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */\n  __IO uint32_t ICR;                   /*!< SDIO interrupt clear register,  Address offset: 0x38 */\n  __IO uint32_t MASK;                  /*!< SDIO mask register,             Address offset: 0x3C */\n  uint32_t      RESERVED0[2];          /*!< Reserved, 0x40-0x44                                  */\n  __IO const uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */\n  uint32_t      RESERVED1[13];         /*!< Reserved, 0x4C-0x7C                                  */\n  __IO uint32_t FIFO;                  /*!< SDIO data FIFO register,        Address offset: 0x80 */\n} SDIO_TypeDef;\n\n/**\n  * @brief Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */\n  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */\n  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */\n  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\n  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */\n  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */\n  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */\n  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */\n} SPI_TypeDef;\n\n/**\n  * @brief QUAD Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */\n  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */\n  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */\n  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */\n  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */\n  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */\n  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */\n  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */\n  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */\n  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */\n  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */\n  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */\n  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */\n} QUADSPI_TypeDef;\n\n/**\n  * @brief TIM\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */\n  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */\n  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */\n  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */\n  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */\n  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\n  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\n  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */\n  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */\n  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */\n  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */\n  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */\n  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */\n  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */\n  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */\n  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */\n  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */\n  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */\n  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */\n  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */\n} TIM_TypeDef;\n\n/**\n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */\n  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */\n  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */\n  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */\n  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */\n  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */\n  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */\n} USART_TypeDef;\n\n/**\n  * @brief Window WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */\n  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */\n  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */\n} WWDG_TypeDef;\n\n/**\n  * @brief RNG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */\n  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */\n  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */\n} RNG_TypeDef;\n\n/**\n  * @brief USB_OTG_Core_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */\n  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */\n  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */\n  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */\n  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */\n  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */\n  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */\n  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */\n  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */\n  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */\n  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */\n  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */\n  uint32_t Reserved30[2];             /*!< Reserved                                     030h */\n  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */\n  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */\n  uint32_t  Reserved5[3];             /*!< Reserved                                040h-048h */\n  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */\n  uint32_t  Reserved6;                /*!< Reserved                                     050h */\n  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */\n  uint32_t  Reserved;                 /*!< Reserved                                     058h */\n  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */\n  uint32_t  Reserved43[40];           /*!< Reserved                                058h-0FFh */\n  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */\n  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                        */\n} USB_OTG_GlobalTypeDef;\n\n/**\n  * @brief USB_OTG_device_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */\n  __IO uint32_t DCTL;            /*!< dev Control Register         804h */\n  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */\n  uint32_t Reserved0C;           /*!< Reserved                     80Ch */\n  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */\n  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */\n  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */\n  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */\n  uint32_t  Reserved20;          /*!< Reserved                     820h */\n  uint32_t Reserved9;            /*!< Reserved                     824h */\n  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */\n  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */\n  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */\n  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */\n  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */\n  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */\n  uint32_t Reserved40;           /*!< dedicated EP mask            840h */\n  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */\n  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */\n  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */\n} USB_OTG_DeviceTypeDef;\n\n/**\n  * @brief USB_OTG_IN_Endpoint-Specific_Register\n  */\ntypedef struct\n{\n  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */\n  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */\n  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */\n  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\n  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\n} USB_OTG_INEndpointTypeDef;\n\n/**\n  * @brief USB_OTG_OUT_Endpoint-Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */\n  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */\n  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */\n  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\n} USB_OTG_OUTEndpointTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Mode_Register_Structures\n  */\ntypedef struct\n{\n  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */\n  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */\n  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */\n  uint32_t Reserved40C;           /*!< Reserved                             40Ch */\n  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */\n  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */\n  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */\n} USB_OTG_HostTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Channel_Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */\n  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */\n  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */\n  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */\n  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */\n  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */\n  uint32_t Reserved[2];           /*!< Reserved                                      */\n} USB_OTG_HostChannelTypeDef;\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_memory_map\n  * @{\n  */\n#define FLASH_BASE            0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region                         */\n#define CCMDATARAM_BASE       0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */\n#define SRAM1_BASE            0x20000000U /*!< SRAM1(160 KB) base address in the alias region                             */\n#define SRAM2_BASE            0x20028000U /*!< SRAM2(32 KB) base address in the alias region                              */\n#define SRAM3_BASE            0x20030000U /*!< SRAM3(128 KB) base address in the alias region                              */\n#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */\n#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */\n#define FMC_R_BASE            0xA0000000U /*!< FMC registers base address                                                 */\n#define QSPI_R_BASE           0xA0001000U /*!< QuadSPI registers base address                                             */\n#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                          */\n#define SRAM2_BB_BASE         0x22500000U /*!< SRAM2(16 KB) base address in the bit-band region                           */\n#define SRAM3_BB_BASE         0x22600000U /*!< SRAM3(64 KB) base address in the bit-band region                           */\n#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                             */\n#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                      */\n#define FLASH_END             0x081FFFFFU /*!< FLASH end address                                                          */\n#define FLASH_OTP_BASE        0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */\n#define FLASH_OTP_END         0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */\n#define CCMDATARAM_END        0x1000FFFFU /*!< CCM data RAM end address                                                   */\n\n/* Legacy defines */\n#define SRAM_BASE             SRAM1_BASE\n#define SRAM_BB_BASE          SRAM1_BB_BASE\n\n/*!< Peripheral memory map */\n#define APB1PERIPH_BASE       PERIPH_BASE\n#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)\n#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)\n#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)\n\n/*!< APB1 peripherals */\n#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)\n#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)\n#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)\n#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)\n#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)\n#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)\n#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)\n#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)\n#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)\n#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)\n#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)\n#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)\n#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)\n#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)\n#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)\n#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)\n#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)\n#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)\n#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)\n#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)\n#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)\n#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)\n#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)\n#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)\n#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)\n#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)\n#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)\n#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)\n#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)\n\n/*!< APB2 peripherals */\n#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)\n#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)\n#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)\n#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)\n#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)\n#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)\n#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)\n#define ADC123_COMMON_BASE    (APB2PERIPH_BASE + 0x2300U)\n/* Legacy define */\n#define ADC_BASE               ADC123_COMMON_BASE\n#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)\n#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)\n#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)\n#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)\n#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)\n#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)\n#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)\n#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)\n#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)\n#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400U)\n#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)\n#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)\n#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)\n#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800U)\n#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84U)\n#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104U)\n#define DSI_BASE              (APB2PERIPH_BASE + 0x6C00U)\n\n/*!< AHB1 peripherals */\n#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)\n#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)\n#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)\n#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)\n#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)\n#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)\n#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)\n#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)\n#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)\n#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400U)\n#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800U)\n#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)\n#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)\n#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)\n#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)\n#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)\n#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)\n#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)\n#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)\n#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)\n#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)\n#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)\n#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)\n#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)\n#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)\n#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)\n#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)\n#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)\n#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)\n#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)\n#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)\n#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)\n#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)\n#define ETH_MAC_BASE          (ETH_BASE)\n#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)\n#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)\n#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)\n#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)\n\n/*!< AHB2 peripherals */\n#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)\n#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)\n\n/*!< FMC Bankx registers base address */\n#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)\n#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)\n#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)\n#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)\n\n\n/*!< Debug MCU registers base address */\n#define DBGMCU_BASE           0xE0042000U\n/*!< USB registers base address */\n#define USB_OTG_HS_PERIPH_BASE               0x40040000U\n#define USB_OTG_FS_PERIPH_BASE               0x50000000U\n\n#define USB_OTG_GLOBAL_BASE                  0x000U\n#define USB_OTG_DEVICE_BASE                  0x800U\n#define USB_OTG_IN_ENDPOINT_BASE             0x900U\n#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U\n#define USB_OTG_EP_REG_SIZE                  0x20U\n#define USB_OTG_HOST_BASE                    0x400U\n#define USB_OTG_HOST_PORT_BASE               0x440U\n#define USB_OTG_HOST_CHANNEL_BASE            0x500U\n#define USB_OTG_HOST_CHANNEL_SIZE            0x20U\n#define USB_OTG_PCGCCTL_BASE                 0xE00U\n#define USB_OTG_FIFO_BASE                    0x1000U\n#define USB_OTG_FIFO_SIZE                    0x1000U\n\n#define UID_BASE                     0x1FFF7A10U           /*!< Unique device ID register base address */\n#define FLASHSIZE_BASE               0x1FFF7A22U           /*!< FLASH Size register base address       */\n#define PACKAGE_BASE                 0x1FFF7BF0U           /*!< Package size register base address     */\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_declaration\n  * @{\n  */\n#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\n#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\n#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\n#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\n#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\n#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\n#define TIM12               ((TIM_TypeDef *) TIM12_BASE)\n#define TIM13               ((TIM_TypeDef *) TIM13_BASE)\n#define TIM14               ((TIM_TypeDef *) TIM14_BASE)\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\n#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\n#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\n#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)\n#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\n#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\n#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)\n#define USART2              ((USART_TypeDef *) USART2_BASE)\n#define USART3              ((USART_TypeDef *) USART3_BASE)\n#define UART4               ((USART_TypeDef *) UART4_BASE)\n#define UART5               ((USART_TypeDef *) UART5_BASE)\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\n#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\n#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\n#define CAN1                ((CAN_TypeDef *) CAN1_BASE)\n#define CAN2                ((CAN_TypeDef *) CAN2_BASE)\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\n#define DAC1                ((DAC_TypeDef *) DAC_BASE)\n#define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */\n#define UART7               ((USART_TypeDef *) UART7_BASE)\n#define UART8               ((USART_TypeDef *) UART8_BASE)\n#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\n#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\n#define USART1              ((USART_TypeDef *) USART1_BASE)\n#define USART6              ((USART_TypeDef *) USART6_BASE)\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\n#define ADC2                ((ADC_TypeDef *) ADC2_BASE)\n#define ADC3                ((ADC_TypeDef *) ADC3_BASE)\n#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)\n/* Legacy define */\n#define ADC                  ADC123_COMMON\n#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\n#define SPI4                ((SPI_TypeDef *) SPI4_BASE)\n#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\n#define TIM9                ((TIM_TypeDef *) TIM9_BASE)\n#define TIM10               ((TIM_TypeDef *) TIM10_BASE)\n#define TIM11               ((TIM_TypeDef *) TIM11_BASE)\n#define SPI5                ((SPI_TypeDef *) SPI5_BASE)\n#define SPI6                ((SPI_TypeDef *) SPI6_BASE)\n#define SAI1                ((SAI_TypeDef *) SAI1_BASE)\n#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\n#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\n#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)\n#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)\n#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)\n#define DSI                 ((DSI_TypeDef *)DSI_BASE)\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\n#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\n#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\n#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)\n#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\n#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)\n#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)\n#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\n#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\n#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\n#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\n#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\n#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\n#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\n#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\n#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\n#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\n#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\n#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\n#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\n#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\n#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\n#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\n#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\n#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\n#define ETH                 ((ETH_TypeDef *) ETH_BASE)\n#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)\n#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)\n#define RNG                 ((RNG_TypeDef *) RNG_BASE)\n#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)\n#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)\n#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)\n#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)\n#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)\n#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\n#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\n#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_constants\n  * @{\n  */\n\n  /** @addtogroup Peripheral_Registers_Bits_Definition\n  * @{\n  */\n\n/******************************************************************************/\n/*                         Peripheral Registers_Bits_Definition               */\n/******************************************************************************/\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Analog to Digital Converter                         */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define ADC_MULTIMODE_SUPPORT                                                  /*!<ADC Multimode feature available on specific devices */\n\n/********************  Bit definition for ADC_SR register  ********************/\n#define ADC_SR_AWD_Pos            (0U)\n#define ADC_SR_AWD_Msk            (0x1U << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */\n#define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */\n#define ADC_SR_EOC_Pos            (1U)\n#define ADC_SR_EOC_Msk            (0x1U << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */\n#define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */\n#define ADC_SR_JEOC_Pos           (2U)\n#define ADC_SR_JEOC_Msk           (0x1U << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */\n#define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */\n#define ADC_SR_JSTRT_Pos          (3U)\n#define ADC_SR_JSTRT_Msk          (0x1U << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */\n#define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */\n#define ADC_SR_STRT_Pos           (4U)\n#define ADC_SR_STRT_Msk           (0x1U << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */\n#define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */\n#define ADC_SR_OVR_Pos            (5U)\n#define ADC_SR_OVR_Msk            (0x1U << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */\n#define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */\n\n/*******************  Bit definition for ADC_CR1 register  ********************/\n#define ADC_CR1_AWDCH_Pos         (0U)\n#define ADC_CR1_AWDCH_Msk         (0x1FU << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */\n#define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\n#define ADC_CR1_AWDCH_0           (0x01U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */\n#define ADC_CR1_AWDCH_1           (0x02U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */\n#define ADC_CR1_AWDCH_2           (0x04U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */\n#define ADC_CR1_AWDCH_3           (0x08U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */\n#define ADC_CR1_AWDCH_4           (0x10U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */\n#define ADC_CR1_EOCIE_Pos         (5U)\n#define ADC_CR1_EOCIE_Msk         (0x1U << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */\n#define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */\n#define ADC_CR1_AWDIE_Pos         (6U)\n#define ADC_CR1_AWDIE_Msk         (0x1U << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */\n#define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */\n#define ADC_CR1_JEOCIE_Pos        (7U)\n#define ADC_CR1_JEOCIE_Msk        (0x1U << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */\n#define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */\n#define ADC_CR1_SCAN_Pos          (8U)\n#define ADC_CR1_SCAN_Msk          (0x1U << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */\n#define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */\n#define ADC_CR1_AWDSGL_Pos        (9U)\n#define ADC_CR1_AWDSGL_Msk        (0x1U << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */\n#define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */\n#define ADC_CR1_JAUTO_Pos         (10U)\n#define ADC_CR1_JAUTO_Msk         (0x1U << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */\n#define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */\n#define ADC_CR1_DISCEN_Pos        (11U)\n#define ADC_CR1_DISCEN_Msk        (0x1U << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */\n#define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */\n#define ADC_CR1_JDISCEN_Pos       (12U)\n#define ADC_CR1_JDISCEN_Msk       (0x1U << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */\n#define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */\n#define ADC_CR1_DISCNUM_Pos       (13U)\n#define ADC_CR1_DISCNUM_Msk       (0x7U << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */\n#define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\n#define ADC_CR1_DISCNUM_0         (0x1U << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */\n#define ADC_CR1_DISCNUM_1         (0x2U << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */\n#define ADC_CR1_DISCNUM_2         (0x4U << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */\n#define ADC_CR1_JAWDEN_Pos        (22U)\n#define ADC_CR1_JAWDEN_Msk        (0x1U << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */\n#define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */\n#define ADC_CR1_AWDEN_Pos         (23U)\n#define ADC_CR1_AWDEN_Msk         (0x1U << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */\n#define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */\n#define ADC_CR1_RES_Pos           (24U)\n#define ADC_CR1_RES_Msk           (0x3U << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */\n#define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */\n#define ADC_CR1_RES_0             (0x1U << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */\n#define ADC_CR1_RES_1             (0x2U << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */\n#define ADC_CR1_OVRIE_Pos         (26U)\n#define ADC_CR1_OVRIE_Msk         (0x1U << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */\n#define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */\n\n/*******************  Bit definition for ADC_CR2 register  ********************/\n#define ADC_CR2_ADON_Pos          (0U)\n#define ADC_CR2_ADON_Msk          (0x1U << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */\n#define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */\n#define ADC_CR2_CONT_Pos          (1U)\n#define ADC_CR2_CONT_Msk          (0x1U << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */\n#define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */\n#define ADC_CR2_DMA_Pos           (8U)\n#define ADC_CR2_DMA_Msk           (0x1U << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */\n#define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */\n#define ADC_CR2_DDS_Pos           (9U)\n#define ADC_CR2_DDS_Msk           (0x1U << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */\n#define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */\n#define ADC_CR2_EOCS_Pos          (10U)\n#define ADC_CR2_EOCS_Msk          (0x1U << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */\n#define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */\n#define ADC_CR2_ALIGN_Pos         (11U)\n#define ADC_CR2_ALIGN_Msk         (0x1U << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */\n#define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */\n#define ADC_CR2_JEXTSEL_Pos       (16U)\n#define ADC_CR2_JEXTSEL_Msk       (0xFU << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */\n#define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */\n#define ADC_CR2_JEXTSEL_0         (0x1U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */\n#define ADC_CR2_JEXTSEL_1         (0x2U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */\n#define ADC_CR2_JEXTSEL_2         (0x4U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */\n#define ADC_CR2_JEXTSEL_3         (0x8U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */\n#define ADC_CR2_JEXTEN_Pos        (20U)\n#define ADC_CR2_JEXTEN_Msk        (0x3U << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */\n#define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\n#define ADC_CR2_JEXTEN_0          (0x1U << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */\n#define ADC_CR2_JEXTEN_1          (0x2U << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */\n#define ADC_CR2_JSWSTART_Pos      (22U)\n#define ADC_CR2_JSWSTART_Msk      (0x1U << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */\n#define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */\n#define ADC_CR2_EXTSEL_Pos        (24U)\n#define ADC_CR2_EXTSEL_Msk        (0xFU << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */\n#define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\n#define ADC_CR2_EXTSEL_0          (0x1U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */\n#define ADC_CR2_EXTSEL_1          (0x2U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */\n#define ADC_CR2_EXTSEL_2          (0x4U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */\n#define ADC_CR2_EXTSEL_3          (0x8U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */\n#define ADC_CR2_EXTEN_Pos         (28U)\n#define ADC_CR2_EXTEN_Msk         (0x3U << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */\n#define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\n#define ADC_CR2_EXTEN_0           (0x1U << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */\n#define ADC_CR2_EXTEN_1           (0x2U << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */\n#define ADC_CR2_SWSTART_Pos       (30U)\n#define ADC_CR2_SWSTART_Msk       (0x1U << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */\n#define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */\n\n/******************  Bit definition for ADC_SMPR1 register  *******************/\n#define ADC_SMPR1_SMP10_Pos       (0U)\n#define ADC_SMPR1_SMP10_Msk       (0x7U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */\n#define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\n#define ADC_SMPR1_SMP10_0         (0x1U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */\n#define ADC_SMPR1_SMP10_1         (0x2U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */\n#define ADC_SMPR1_SMP10_2         (0x4U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */\n#define ADC_SMPR1_SMP11_Pos       (3U)\n#define ADC_SMPR1_SMP11_Msk       (0x7U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */\n#define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\n#define ADC_SMPR1_SMP11_0         (0x1U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */\n#define ADC_SMPR1_SMP11_1         (0x2U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */\n#define ADC_SMPR1_SMP11_2         (0x4U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */\n#define ADC_SMPR1_SMP12_Pos       (6U)\n#define ADC_SMPR1_SMP12_Msk       (0x7U << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */\n#define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\n#define ADC_SMPR1_SMP12_0         (0x1U << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */\n#define ADC_SMPR1_SMP12_1         (0x2U << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */\n#define ADC_SMPR1_SMP12_2         (0x4U << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */\n#define ADC_SMPR1_SMP13_Pos       (9U)\n#define ADC_SMPR1_SMP13_Msk       (0x7U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */\n#define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\n#define ADC_SMPR1_SMP13_0         (0x1U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */\n#define ADC_SMPR1_SMP13_1         (0x2U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */\n#define ADC_SMPR1_SMP13_2         (0x4U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */\n#define ADC_SMPR1_SMP14_Pos       (12U)\n#define ADC_SMPR1_SMP14_Msk       (0x7U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */\n#define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\n#define ADC_SMPR1_SMP14_0         (0x1U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */\n#define ADC_SMPR1_SMP14_1         (0x2U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */\n#define ADC_SMPR1_SMP14_2         (0x4U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */\n#define ADC_SMPR1_SMP15_Pos       (15U)\n#define ADC_SMPR1_SMP15_Msk       (0x7U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */\n#define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\n#define ADC_SMPR1_SMP15_0         (0x1U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */\n#define ADC_SMPR1_SMP15_1         (0x2U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */\n#define ADC_SMPR1_SMP15_2         (0x4U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */\n#define ADC_SMPR1_SMP16_Pos       (18U)\n#define ADC_SMPR1_SMP16_Msk       (0x7U << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */\n#define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\n#define ADC_SMPR1_SMP16_0         (0x1U << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */\n#define ADC_SMPR1_SMP16_1         (0x2U << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */\n#define ADC_SMPR1_SMP16_2         (0x4U << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */\n#define ADC_SMPR1_SMP17_Pos       (21U)\n#define ADC_SMPR1_SMP17_Msk       (0x7U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */\n#define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\n#define ADC_SMPR1_SMP17_0         (0x1U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */\n#define ADC_SMPR1_SMP17_1         (0x2U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */\n#define ADC_SMPR1_SMP17_2         (0x4U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */\n#define ADC_SMPR1_SMP18_Pos       (24U)\n#define ADC_SMPR1_SMP18_Msk       (0x7U << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */\n#define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\n#define ADC_SMPR1_SMP18_0         (0x1U << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */\n#define ADC_SMPR1_SMP18_1         (0x2U << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */\n#define ADC_SMPR1_SMP18_2         (0x4U << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */\n\n/******************  Bit definition for ADC_SMPR2 register  *******************/\n#define ADC_SMPR2_SMP0_Pos        (0U)\n#define ADC_SMPR2_SMP0_Msk        (0x7U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */\n#define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\n#define ADC_SMPR2_SMP0_0          (0x1U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */\n#define ADC_SMPR2_SMP0_1          (0x2U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */\n#define ADC_SMPR2_SMP0_2          (0x4U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */\n#define ADC_SMPR2_SMP1_Pos        (3U)\n#define ADC_SMPR2_SMP1_Msk        (0x7U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */\n#define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\n#define ADC_SMPR2_SMP1_0          (0x1U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */\n#define ADC_SMPR2_SMP1_1          (0x2U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */\n#define ADC_SMPR2_SMP1_2          (0x4U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */\n#define ADC_SMPR2_SMP2_Pos        (6U)\n#define ADC_SMPR2_SMP2_Msk        (0x7U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */\n#define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\n#define ADC_SMPR2_SMP2_0          (0x1U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */\n#define ADC_SMPR2_SMP2_1          (0x2U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */\n#define ADC_SMPR2_SMP2_2          (0x4U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */\n#define ADC_SMPR2_SMP3_Pos        (9U)\n#define ADC_SMPR2_SMP3_Msk        (0x7U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */\n#define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\n#define ADC_SMPR2_SMP3_0          (0x1U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */\n#define ADC_SMPR2_SMP3_1          (0x2U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */\n#define ADC_SMPR2_SMP3_2          (0x4U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */\n#define ADC_SMPR2_SMP4_Pos        (12U)\n#define ADC_SMPR2_SMP4_Msk        (0x7U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */\n#define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\n#define ADC_SMPR2_SMP4_0          (0x1U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */\n#define ADC_SMPR2_SMP4_1          (0x2U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */\n#define ADC_SMPR2_SMP4_2          (0x4U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */\n#define ADC_SMPR2_SMP5_Pos        (15U)\n#define ADC_SMPR2_SMP5_Msk        (0x7U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */\n#define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\n#define ADC_SMPR2_SMP5_0          (0x1U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */\n#define ADC_SMPR2_SMP5_1          (0x2U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */\n#define ADC_SMPR2_SMP5_2          (0x4U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */\n#define ADC_SMPR2_SMP6_Pos        (18U)\n#define ADC_SMPR2_SMP6_Msk        (0x7U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */\n#define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\n#define ADC_SMPR2_SMP6_0          (0x1U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */\n#define ADC_SMPR2_SMP6_1          (0x2U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */\n#define ADC_SMPR2_SMP6_2          (0x4U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */\n#define ADC_SMPR2_SMP7_Pos        (21U)\n#define ADC_SMPR2_SMP7_Msk        (0x7U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */\n#define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\n#define ADC_SMPR2_SMP7_0          (0x1U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */\n#define ADC_SMPR2_SMP7_1          (0x2U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */\n#define ADC_SMPR2_SMP7_2          (0x4U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */\n#define ADC_SMPR2_SMP8_Pos        (24U)\n#define ADC_SMPR2_SMP8_Msk        (0x7U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */\n#define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\n#define ADC_SMPR2_SMP8_0          (0x1U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */\n#define ADC_SMPR2_SMP8_1          (0x2U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */\n#define ADC_SMPR2_SMP8_2          (0x4U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */\n#define ADC_SMPR2_SMP9_Pos        (27U)\n#define ADC_SMPR2_SMP9_Msk        (0x7U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */\n#define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\n#define ADC_SMPR2_SMP9_0          (0x1U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */\n#define ADC_SMPR2_SMP9_1          (0x2U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */\n#define ADC_SMPR2_SMP9_2          (0x4U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */\n\n/******************  Bit definition for ADC_JOFR1 register  *******************/\n#define ADC_JOFR1_JOFFSET1_Pos    (0U)\n#define ADC_JOFR1_JOFFSET1_Msk    (0xFFFU << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */\n\n/******************  Bit definition for ADC_JOFR2 register  *******************/\n#define ADC_JOFR2_JOFFSET2_Pos    (0U)\n#define ADC_JOFR2_JOFFSET2_Msk    (0xFFFU << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */\n\n/******************  Bit definition for ADC_JOFR3 register  *******************/\n#define ADC_JOFR3_JOFFSET3_Pos    (0U)\n#define ADC_JOFR3_JOFFSET3_Msk    (0xFFFU << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */\n\n/******************  Bit definition for ADC_JOFR4 register  *******************/\n#define ADC_JOFR4_JOFFSET4_Pos    (0U)\n#define ADC_JOFR4_JOFFSET4_Msk    (0xFFFU << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */\n\n/*******************  Bit definition for ADC_HTR register  ********************/\n#define ADC_HTR_HT_Pos            (0U)\n#define ADC_HTR_HT_Msk            (0xFFFU << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */\n#define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */\n\n/*******************  Bit definition for ADC_LTR register  ********************/\n#define ADC_LTR_LT_Pos            (0U)\n#define ADC_LTR_LT_Msk            (0xFFFU << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */\n#define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */\n\n/*******************  Bit definition for ADC_SQR1 register  *******************/\n#define ADC_SQR1_SQ13_Pos         (0U)\n#define ADC_SQR1_SQ13_Msk         (0x1FU << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */\n#define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\n#define ADC_SQR1_SQ13_0           (0x01U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */\n#define ADC_SQR1_SQ13_1           (0x02U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */\n#define ADC_SQR1_SQ13_2           (0x04U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */\n#define ADC_SQR1_SQ13_3           (0x08U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */\n#define ADC_SQR1_SQ13_4           (0x10U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */\n#define ADC_SQR1_SQ14_Pos         (5U)\n#define ADC_SQR1_SQ14_Msk         (0x1FU << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */\n#define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\n#define ADC_SQR1_SQ14_0           (0x01U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */\n#define ADC_SQR1_SQ14_1           (0x02U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */\n#define ADC_SQR1_SQ14_2           (0x04U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */\n#define ADC_SQR1_SQ14_3           (0x08U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */\n#define ADC_SQR1_SQ14_4           (0x10U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */\n#define ADC_SQR1_SQ15_Pos         (10U)\n#define ADC_SQR1_SQ15_Msk         (0x1FU << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */\n#define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\n#define ADC_SQR1_SQ15_0           (0x01U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */\n#define ADC_SQR1_SQ15_1           (0x02U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */\n#define ADC_SQR1_SQ15_2           (0x04U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */\n#define ADC_SQR1_SQ15_3           (0x08U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */\n#define ADC_SQR1_SQ15_4           (0x10U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */\n#define ADC_SQR1_SQ16_Pos         (15U)\n#define ADC_SQR1_SQ16_Msk         (0x1FU << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\n#define ADC_SQR1_SQ16_0           (0x01U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR1_SQ16_1           (0x02U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR1_SQ16_2           (0x04U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR1_SQ16_3           (0x08U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR1_SQ16_4           (0x10U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR1_L_Pos            (20U)\n#define ADC_SQR1_L_Msk            (0xFU << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */\n#define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */\n#define ADC_SQR1_L_0              (0x1U << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */\n#define ADC_SQR1_L_1              (0x2U << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */\n#define ADC_SQR1_L_2              (0x4U << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */\n#define ADC_SQR1_L_3              (0x8U << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */\n\n/*******************  Bit definition for ADC_SQR2 register  *******************/\n#define ADC_SQR2_SQ7_Pos          (0U)\n#define ADC_SQR2_SQ7_Msk          (0x1FU << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\n#define ADC_SQR2_SQ7_0            (0x01U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR2_SQ7_1            (0x02U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR2_SQ7_2            (0x04U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR2_SQ7_3            (0x08U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR2_SQ7_4            (0x10U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR2_SQ8_Pos          (5U)\n#define ADC_SQR2_SQ8_Msk          (0x1FU << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\n#define ADC_SQR2_SQ8_0            (0x01U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR2_SQ8_1            (0x02U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR2_SQ8_2            (0x04U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR2_SQ8_3            (0x08U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR2_SQ8_4            (0x10U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR2_SQ9_Pos          (10U)\n#define ADC_SQR2_SQ9_Msk          (0x1FU << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\n#define ADC_SQR2_SQ9_0            (0x01U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR2_SQ9_1            (0x02U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR2_SQ9_2            (0x04U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR2_SQ9_3            (0x08U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR2_SQ9_4            (0x10U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR2_SQ10_Pos         (15U)\n#define ADC_SQR2_SQ10_Msk         (0x1FU << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\n#define ADC_SQR2_SQ10_0           (0x01U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR2_SQ10_1           (0x02U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR2_SQ10_2           (0x04U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR2_SQ10_3           (0x08U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR2_SQ10_4           (0x10U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR2_SQ11_Pos         (20U)\n#define ADC_SQR2_SQ11_Msk         (0x1FU << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */\n#define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\n#define ADC_SQR2_SQ11_0           (0x01U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */\n#define ADC_SQR2_SQ11_1           (0x02U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */\n#define ADC_SQR2_SQ11_2           (0x04U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */\n#define ADC_SQR2_SQ11_3           (0x08U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */\n#define ADC_SQR2_SQ11_4           (0x10U << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */\n#define ADC_SQR2_SQ12_Pos         (25U)\n#define ADC_SQR2_SQ12_Msk         (0x1FU << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */\n#define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\n#define ADC_SQR2_SQ12_0           (0x01U << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */\n#define ADC_SQR2_SQ12_1           (0x02U << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */\n#define ADC_SQR2_SQ12_2           (0x04U << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */\n#define ADC_SQR2_SQ12_3           (0x08U << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */\n#define ADC_SQR2_SQ12_4           (0x10U << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_SQR3 register  *******************/\n#define ADC_SQR3_SQ1_Pos          (0U)\n#define ADC_SQR3_SQ1_Msk          (0x1FU << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\n#define ADC_SQR3_SQ1_0            (0x01U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR3_SQ1_1            (0x02U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR3_SQ1_2            (0x04U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR3_SQ1_3            (0x08U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR3_SQ1_4            (0x10U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR3_SQ2_Pos          (5U)\n#define ADC_SQR3_SQ2_Msk          (0x1FU << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\n#define ADC_SQR3_SQ2_0            (0x01U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR3_SQ2_1            (0x02U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR3_SQ2_2            (0x04U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR3_SQ2_3            (0x08U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR3_SQ2_4            (0x10U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR3_SQ3_Pos          (10U)\n#define ADC_SQR3_SQ3_Msk          (0x1FU << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\n#define ADC_SQR3_SQ3_0            (0x01U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR3_SQ3_1            (0x02U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR3_SQ3_2            (0x04U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR3_SQ3_3            (0x08U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR3_SQ3_4            (0x10U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR3_SQ4_Pos          (15U)\n#define ADC_SQR3_SQ4_Msk          (0x1FU << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */\n#define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\n#define ADC_SQR3_SQ4_0            (0x01U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */\n#define ADC_SQR3_SQ4_1            (0x02U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */\n#define ADC_SQR3_SQ4_2            (0x04U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */\n#define ADC_SQR3_SQ4_3            (0x08U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */\n#define ADC_SQR3_SQ4_4            (0x10U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */\n#define ADC_SQR3_SQ5_Pos          (20U)\n#define ADC_SQR3_SQ5_Msk          (0x1FU << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */\n#define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\n#define ADC_SQR3_SQ5_0            (0x01U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */\n#define ADC_SQR3_SQ5_1            (0x02U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */\n#define ADC_SQR3_SQ5_2            (0x04U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */\n#define ADC_SQR3_SQ5_3            (0x08U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */\n#define ADC_SQR3_SQ5_4            (0x10U << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */\n#define ADC_SQR3_SQ6_Pos          (25U)\n#define ADC_SQR3_SQ6_Msk          (0x1FU << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */\n#define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\n#define ADC_SQR3_SQ6_0            (0x01U << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */\n#define ADC_SQR3_SQ6_1            (0x02U << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */\n#define ADC_SQR3_SQ6_2            (0x04U << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */\n#define ADC_SQR3_SQ6_3            (0x08U << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */\n#define ADC_SQR3_SQ6_4            (0x10U << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_JSQR register  *******************/\n#define ADC_JSQR_JSQ1_Pos         (0U)\n#define ADC_JSQR_JSQ1_Msk         (0x1FU << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */\n#define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */\n#define ADC_JSQR_JSQ1_0           (0x01U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */\n#define ADC_JSQR_JSQ1_1           (0x02U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */\n#define ADC_JSQR_JSQ1_2           (0x04U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */\n#define ADC_JSQR_JSQ1_3           (0x08U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */\n#define ADC_JSQR_JSQ1_4           (0x10U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */\n#define ADC_JSQR_JSQ2_Pos         (5U)\n#define ADC_JSQR_JSQ2_Msk         (0x1FU << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */\n#define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\n#define ADC_JSQR_JSQ2_0           (0x01U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */\n#define ADC_JSQR_JSQ2_1           (0x02U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */\n#define ADC_JSQR_JSQ2_2           (0x04U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */\n#define ADC_JSQR_JSQ2_3           (0x08U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */\n#define ADC_JSQR_JSQ2_4           (0x10U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */\n#define ADC_JSQR_JSQ3_Pos         (10U)\n#define ADC_JSQR_JSQ3_Msk         (0x1FU << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */\n#define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\n#define ADC_JSQR_JSQ3_0           (0x01U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */\n#define ADC_JSQR_JSQ3_1           (0x02U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */\n#define ADC_JSQR_JSQ3_2           (0x04U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */\n#define ADC_JSQR_JSQ3_3           (0x08U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */\n#define ADC_JSQR_JSQ3_4           (0x10U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */\n#define ADC_JSQR_JSQ4_Pos         (15U)\n#define ADC_JSQR_JSQ4_Msk         (0x1FU << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */\n#define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\n#define ADC_JSQR_JSQ4_0           (0x01U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */\n#define ADC_JSQR_JSQ4_1           (0x02U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */\n#define ADC_JSQR_JSQ4_2           (0x04U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */\n#define ADC_JSQR_JSQ4_3           (0x08U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */\n#define ADC_JSQR_JSQ4_4           (0x10U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */\n#define ADC_JSQR_JL_Pos           (20U)\n#define ADC_JSQR_JL_Msk           (0x3U << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */\n#define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */\n#define ADC_JSQR_JL_0             (0x1U << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */\n#define ADC_JSQR_JL_1             (0x2U << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */\n\n/*******************  Bit definition for ADC_JDR1 register  *******************/\n#define ADC_JDR1_JDATA_Pos        (0U)\n#define ADC_JDR1_JDATA_Msk        (0xFFFFU << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR2 register  *******************/\n#define ADC_JDR2_JDATA_Pos        (0U)\n#define ADC_JDR2_JDATA_Msk        (0xFFFFU << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR3 register  *******************/\n#define ADC_JDR3_JDATA_Pos        (0U)\n#define ADC_JDR3_JDATA_Msk        (0xFFFFU << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR4 register  *******************/\n#define ADC_JDR4_JDATA_Pos        (0U)\n#define ADC_JDR4_JDATA_Msk        (0xFFFFU << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */\n\n/********************  Bit definition for ADC_DR register  ********************/\n#define ADC_DR_DATA_Pos           (0U)\n#define ADC_DR_DATA_Msk           (0xFFFFU << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */\n#define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */\n#define ADC_DR_ADC2DATA_Pos       (16U)\n#define ADC_DR_ADC2DATA_Msk       (0xFFFFU << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */\n#define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */\n\n/*******************  Bit definition for ADC_CSR register  ********************/\n#define ADC_CSR_AWD1_Pos          (0U)\n#define ADC_CSR_AWD1_Msk          (0x1U << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */\n#define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */\n#define ADC_CSR_EOC1_Pos          (1U)\n#define ADC_CSR_EOC1_Msk          (0x1U << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */\n#define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */\n#define ADC_CSR_JEOC1_Pos         (2U)\n#define ADC_CSR_JEOC1_Msk         (0x1U << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */\n#define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */\n#define ADC_CSR_JSTRT1_Pos        (3U)\n#define ADC_CSR_JSTRT1_Msk        (0x1U << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */\n#define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */\n#define ADC_CSR_STRT1_Pos         (4U)\n#define ADC_CSR_STRT1_Msk         (0x1U << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */\n#define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */\n#define ADC_CSR_OVR1_Pos          (5U)\n#define ADC_CSR_OVR1_Msk          (0x1U << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */\n#define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */\n#define ADC_CSR_AWD2_Pos          (8U)\n#define ADC_CSR_AWD2_Msk          (0x1U << ADC_CSR_AWD2_Pos)                   /*!< 0x00000100 */\n#define ADC_CSR_AWD2              ADC_CSR_AWD2_Msk                             /*!<ADC2 Analog watchdog flag */\n#define ADC_CSR_EOC2_Pos          (9U)\n#define ADC_CSR_EOC2_Msk          (0x1U << ADC_CSR_EOC2_Pos)                   /*!< 0x00000200 */\n#define ADC_CSR_EOC2              ADC_CSR_EOC2_Msk                             /*!<ADC2 End of conversion */\n#define ADC_CSR_JEOC2_Pos         (10U)\n#define ADC_CSR_JEOC2_Msk         (0x1U << ADC_CSR_JEOC2_Pos)                  /*!< 0x00000400 */\n#define ADC_CSR_JEOC2             ADC_CSR_JEOC2_Msk                            /*!<ADC2 Injected channel end of conversion */\n#define ADC_CSR_JSTRT2_Pos        (11U)\n#define ADC_CSR_JSTRT2_Msk        (0x1U << ADC_CSR_JSTRT2_Pos)                 /*!< 0x00000800 */\n#define ADC_CSR_JSTRT2            ADC_CSR_JSTRT2_Msk                           /*!<ADC2 Injected channel Start flag */\n#define ADC_CSR_STRT2_Pos         (12U)\n#define ADC_CSR_STRT2_Msk         (0x1U << ADC_CSR_STRT2_Pos)                  /*!< 0x00001000 */\n#define ADC_CSR_STRT2             ADC_CSR_STRT2_Msk                            /*!<ADC2 Regular channel Start flag */\n#define ADC_CSR_OVR2_Pos          (13U)\n#define ADC_CSR_OVR2_Msk          (0x1U << ADC_CSR_OVR2_Pos)                   /*!< 0x00002000 */\n#define ADC_CSR_OVR2              ADC_CSR_OVR2_Msk                             /*!<ADC2 DMA overrun  flag */\n#define ADC_CSR_AWD3_Pos          (16U)\n#define ADC_CSR_AWD3_Msk          (0x1U << ADC_CSR_AWD3_Pos)                   /*!< 0x00010000 */\n#define ADC_CSR_AWD3              ADC_CSR_AWD3_Msk                             /*!<ADC3 Analog watchdog flag */\n#define ADC_CSR_EOC3_Pos          (17U)\n#define ADC_CSR_EOC3_Msk          (0x1U << ADC_CSR_EOC3_Pos)                   /*!< 0x00020000 */\n#define ADC_CSR_EOC3              ADC_CSR_EOC3_Msk                             /*!<ADC3 End of conversion */\n#define ADC_CSR_JEOC3_Pos         (18U)\n#define ADC_CSR_JEOC3_Msk         (0x1U << ADC_CSR_JEOC3_Pos)                  /*!< 0x00040000 */\n#define ADC_CSR_JEOC3             ADC_CSR_JEOC3_Msk                            /*!<ADC3 Injected channel end of conversion */\n#define ADC_CSR_JSTRT3_Pos        (19U)\n#define ADC_CSR_JSTRT3_Msk        (0x1U << ADC_CSR_JSTRT3_Pos)                 /*!< 0x00080000 */\n#define ADC_CSR_JSTRT3            ADC_CSR_JSTRT3_Msk                           /*!<ADC3 Injected channel Start flag */\n#define ADC_CSR_STRT3_Pos         (20U)\n#define ADC_CSR_STRT3_Msk         (0x1U << ADC_CSR_STRT3_Pos)                  /*!< 0x00100000 */\n#define ADC_CSR_STRT3             ADC_CSR_STRT3_Msk                            /*!<ADC3 Regular channel Start flag */\n#define ADC_CSR_OVR3_Pos          (21U)\n#define ADC_CSR_OVR3_Msk          (0x1U << ADC_CSR_OVR3_Pos)                   /*!< 0x00200000 */\n#define ADC_CSR_OVR3              ADC_CSR_OVR3_Msk                             /*!<ADC3 DMA overrun  flag */\n\n/* Legacy defines */\n#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1\n#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2\n#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3\n\n/*******************  Bit definition for ADC_CCR register  ********************/\n#define ADC_CCR_MULTI_Pos         (0U)\n#define ADC_CCR_MULTI_Msk         (0x1FU << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */\n#define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */\n#define ADC_CCR_MULTI_0           (0x01U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */\n#define ADC_CCR_MULTI_1           (0x02U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */\n#define ADC_CCR_MULTI_2           (0x04U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */\n#define ADC_CCR_MULTI_3           (0x08U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */\n#define ADC_CCR_MULTI_4           (0x10U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */\n#define ADC_CCR_DELAY_Pos         (8U)\n#define ADC_CCR_DELAY_Msk         (0xFU << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */\n#define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */\n#define ADC_CCR_DELAY_0           (0x1U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */\n#define ADC_CCR_DELAY_1           (0x2U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */\n#define ADC_CCR_DELAY_2           (0x4U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */\n#define ADC_CCR_DELAY_3           (0x8U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */\n#define ADC_CCR_DDS_Pos           (13U)\n#define ADC_CCR_DDS_Msk           (0x1U << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */\n#define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */\n#define ADC_CCR_DMA_Pos           (14U)\n#define ADC_CCR_DMA_Msk           (0x3U << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */\n#define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */\n#define ADC_CCR_DMA_0             (0x1U << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */\n#define ADC_CCR_DMA_1             (0x2U << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */\n#define ADC_CCR_ADCPRE_Pos        (16U)\n#define ADC_CCR_ADCPRE_Msk        (0x3U << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */\n#define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */\n#define ADC_CCR_ADCPRE_0          (0x1U << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */\n#define ADC_CCR_ADCPRE_1          (0x2U << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */\n#define ADC_CCR_VBATE_Pos         (22U)\n#define ADC_CCR_VBATE_Msk         (0x1U << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */\n#define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */\n#define ADC_CCR_TSVREFE_Pos       (23U)\n#define ADC_CCR_TSVREFE_Msk       (0x1U << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */\n#define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */\n\n/*******************  Bit definition for ADC_CDR register  ********************/\n#define ADC_CDR_DATA1_Pos         (0U)\n#define ADC_CDR_DATA1_Msk         (0xFFFFU << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */\n#define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */\n#define ADC_CDR_DATA2_Pos         (16U)\n#define ADC_CDR_DATA2_Msk         (0xFFFFU << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */\n#define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */\n\n/* Legacy defines */\n#define ADC_CDR_RDATA_MST         ADC_CDR_DATA1\n#define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Controller Area Network                            */\n/*                                                                            */\n/******************************************************************************/\n/*!<CAN control and status registers */\n/*******************  Bit definition for CAN_MCR register  ********************/\n#define CAN_MCR_INRQ_Pos       (0U)\n#define CAN_MCR_INRQ_Msk       (0x1U << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */\n#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */\n#define CAN_MCR_SLEEP_Pos      (1U)\n#define CAN_MCR_SLEEP_Msk      (0x1U << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */\n#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */\n#define CAN_MCR_TXFP_Pos       (2U)\n#define CAN_MCR_TXFP_Msk       (0x1U << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */\n#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */\n#define CAN_MCR_RFLM_Pos       (3U)\n#define CAN_MCR_RFLM_Msk       (0x1U << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */\n#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */\n#define CAN_MCR_NART_Pos       (4U)\n#define CAN_MCR_NART_Msk       (0x1U << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */\n#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */\n#define CAN_MCR_AWUM_Pos       (5U)\n#define CAN_MCR_AWUM_Msk       (0x1U << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */\n#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */\n#define CAN_MCR_ABOM_Pos       (6U)\n#define CAN_MCR_ABOM_Msk       (0x1U << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */\n#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */\n#define CAN_MCR_TTCM_Pos       (7U)\n#define CAN_MCR_TTCM_Msk       (0x1U << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */\n#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */\n#define CAN_MCR_RESET_Pos      (15U)\n#define CAN_MCR_RESET_Msk      (0x1U << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */\n#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */\n#define CAN_MCR_DBF_Pos        (16U)\n#define CAN_MCR_DBF_Msk        (0x1U << CAN_MCR_DBF_Pos)                       /*!< 0x00010000 */\n#define CAN_MCR_DBF            CAN_MCR_DBF_Msk                                 /*!<bxCAN Debug freeze */\n/*******************  Bit definition for CAN_MSR register  ********************/\n#define CAN_MSR_INAK_Pos       (0U)\n#define CAN_MSR_INAK_Msk       (0x1U << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */\n#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */\n#define CAN_MSR_SLAK_Pos       (1U)\n#define CAN_MSR_SLAK_Msk       (0x1U << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */\n#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */\n#define CAN_MSR_ERRI_Pos       (2U)\n#define CAN_MSR_ERRI_Msk       (0x1U << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */\n#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */\n#define CAN_MSR_WKUI_Pos       (3U)\n#define CAN_MSR_WKUI_Msk       (0x1U << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */\n#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */\n#define CAN_MSR_SLAKI_Pos      (4U)\n#define CAN_MSR_SLAKI_Msk      (0x1U << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */\n#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */\n#define CAN_MSR_TXM_Pos        (8U)\n#define CAN_MSR_TXM_Msk        (0x1U << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */\n#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */\n#define CAN_MSR_RXM_Pos        (9U)\n#define CAN_MSR_RXM_Msk        (0x1U << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */\n#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */\n#define CAN_MSR_SAMP_Pos       (10U)\n#define CAN_MSR_SAMP_Msk       (0x1U << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */\n#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */\n#define CAN_MSR_RX_Pos         (11U)\n#define CAN_MSR_RX_Msk         (0x1U << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */\n#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */\n\n/*******************  Bit definition for CAN_TSR register  ********************/\n#define CAN_TSR_RQCP0_Pos      (0U)\n#define CAN_TSR_RQCP0_Msk      (0x1U << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */\n#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */\n#define CAN_TSR_TXOK0_Pos      (1U)\n#define CAN_TSR_TXOK0_Msk      (0x1U << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */\n#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */\n#define CAN_TSR_ALST0_Pos      (2U)\n#define CAN_TSR_ALST0_Msk      (0x1U << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */\n#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */\n#define CAN_TSR_TERR0_Pos      (3U)\n#define CAN_TSR_TERR0_Msk      (0x1U << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */\n#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */\n#define CAN_TSR_ABRQ0_Pos      (7U)\n#define CAN_TSR_ABRQ0_Msk      (0x1U << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */\n#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */\n#define CAN_TSR_RQCP1_Pos      (8U)\n#define CAN_TSR_RQCP1_Msk      (0x1U << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */\n#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */\n#define CAN_TSR_TXOK1_Pos      (9U)\n#define CAN_TSR_TXOK1_Msk      (0x1U << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */\n#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */\n#define CAN_TSR_ALST1_Pos      (10U)\n#define CAN_TSR_ALST1_Msk      (0x1U << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */\n#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */\n#define CAN_TSR_TERR1_Pos      (11U)\n#define CAN_TSR_TERR1_Msk      (0x1U << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */\n#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */\n#define CAN_TSR_ABRQ1_Pos      (15U)\n#define CAN_TSR_ABRQ1_Msk      (0x1U << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */\n#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */\n#define CAN_TSR_RQCP2_Pos      (16U)\n#define CAN_TSR_RQCP2_Msk      (0x1U << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */\n#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */\n#define CAN_TSR_TXOK2_Pos      (17U)\n#define CAN_TSR_TXOK2_Msk      (0x1U << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */\n#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */\n#define CAN_TSR_ALST2_Pos      (18U)\n#define CAN_TSR_ALST2_Msk      (0x1U << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */\n#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */\n#define CAN_TSR_TERR2_Pos      (19U)\n#define CAN_TSR_TERR2_Msk      (0x1U << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */\n#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */\n#define CAN_TSR_ABRQ2_Pos      (23U)\n#define CAN_TSR_ABRQ2_Msk      (0x1U << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */\n#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */\n#define CAN_TSR_CODE_Pos       (24U)\n#define CAN_TSR_CODE_Msk       (0x3U << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */\n#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */\n\n#define CAN_TSR_TME_Pos        (26U)\n#define CAN_TSR_TME_Msk        (0x7U << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */\n#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */\n#define CAN_TSR_TME0_Pos       (26U)\n#define CAN_TSR_TME0_Msk       (0x1U << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */\n#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */\n#define CAN_TSR_TME1_Pos       (27U)\n#define CAN_TSR_TME1_Msk       (0x1U << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */\n#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */\n#define CAN_TSR_TME2_Pos       (28U)\n#define CAN_TSR_TME2_Msk       (0x1U << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */\n#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */\n\n#define CAN_TSR_LOW_Pos        (29U)\n#define CAN_TSR_LOW_Msk        (0x7U << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */\n#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */\n#define CAN_TSR_LOW0_Pos       (29U)\n#define CAN_TSR_LOW0_Msk       (0x1U << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */\n#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */\n#define CAN_TSR_LOW1_Pos       (30U)\n#define CAN_TSR_LOW1_Msk       (0x1U << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */\n#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */\n#define CAN_TSR_LOW2_Pos       (31U)\n#define CAN_TSR_LOW2_Msk       (0x1U << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */\n#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */\n\n/*******************  Bit definition for CAN_RF0R register  *******************/\n#define CAN_RF0R_FMP0_Pos      (0U)\n#define CAN_RF0R_FMP0_Msk      (0x3U << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */\n#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */\n#define CAN_RF0R_FULL0_Pos     (3U)\n#define CAN_RF0R_FULL0_Msk     (0x1U << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */\n#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */\n#define CAN_RF0R_FOVR0_Pos     (4U)\n#define CAN_RF0R_FOVR0_Msk     (0x1U << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */\n#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */\n#define CAN_RF0R_RFOM0_Pos     (5U)\n#define CAN_RF0R_RFOM0_Msk     (0x1U << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */\n#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */\n\n/*******************  Bit definition for CAN_RF1R register  *******************/\n#define CAN_RF1R_FMP1_Pos      (0U)\n#define CAN_RF1R_FMP1_Msk      (0x3U << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */\n#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */\n#define CAN_RF1R_FULL1_Pos     (3U)\n#define CAN_RF1R_FULL1_Msk     (0x1U << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */\n#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */\n#define CAN_RF1R_FOVR1_Pos     (4U)\n#define CAN_RF1R_FOVR1_Msk     (0x1U << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */\n#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */\n#define CAN_RF1R_RFOM1_Pos     (5U)\n#define CAN_RF1R_RFOM1_Msk     (0x1U << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */\n#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */\n\n/********************  Bit definition for CAN_IER register  *******************/\n#define CAN_IER_TMEIE_Pos      (0U)\n#define CAN_IER_TMEIE_Msk      (0x1U << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */\n#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */\n#define CAN_IER_FMPIE0_Pos     (1U)\n#define CAN_IER_FMPIE0_Msk     (0x1U << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */\n#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE0_Pos      (2U)\n#define CAN_IER_FFIE0_Msk      (0x1U << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */\n#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE0_Pos     (3U)\n#define CAN_IER_FOVIE0_Msk     (0x1U << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */\n#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_FMPIE1_Pos     (4U)\n#define CAN_IER_FMPIE1_Msk     (0x1U << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */\n#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE1_Pos      (5U)\n#define CAN_IER_FFIE1_Msk      (0x1U << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */\n#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE1_Pos     (6U)\n#define CAN_IER_FOVIE1_Msk     (0x1U << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */\n#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)\n#define CAN_IER_EWGIE_Msk      (0x1U << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */\n#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */\n#define CAN_IER_EPVIE_Pos      (9U)\n#define CAN_IER_EPVIE_Msk      (0x1U << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */\n#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */\n#define CAN_IER_BOFIE_Pos      (10U)\n#define CAN_IER_BOFIE_Msk      (0x1U << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */\n#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */\n#define CAN_IER_LECIE_Pos      (11U)\n#define CAN_IER_LECIE_Msk      (0x1U << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */\n#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */\n#define CAN_IER_ERRIE_Pos      (15U)\n#define CAN_IER_ERRIE_Msk      (0x1U << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */\n#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */\n#define CAN_IER_WKUIE_Pos      (16U)\n#define CAN_IER_WKUIE_Msk      (0x1U << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */\n#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */\n#define CAN_IER_SLKIE_Pos      (17U)\n#define CAN_IER_SLKIE_Msk      (0x1U << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */\n#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)\n\n/********************  Bit definition for CAN_ESR register  *******************/\n#define CAN_ESR_EWGF_Pos       (0U)\n#define CAN_ESR_EWGF_Msk       (0x1U << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */\n#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */\n#define CAN_ESR_EPVF_Pos       (1U)\n#define CAN_ESR_EPVF_Msk       (0x1U << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */\n#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */\n#define CAN_ESR_BOFF_Pos       (2U)\n#define CAN_ESR_BOFF_Msk       (0x1U << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */\n#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */\n\n#define CAN_ESR_LEC_Pos        (4U)\n#define CAN_ESR_LEC_Msk        (0x7U << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */\n#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */\n#define CAN_ESR_LEC_0          (0x1U << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */\n#define CAN_ESR_LEC_1          (0x2U << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */\n#define CAN_ESR_LEC_2          (0x4U << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */\n\n#define CAN_ESR_TEC_Pos        (16U)\n#define CAN_ESR_TEC_Msk        (0xFFU << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */\n#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */\n#define CAN_ESR_REC_Pos        (24U)\n#define CAN_ESR_REC_Msk        (0xFFU << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */\n#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */\n\n/*******************  Bit definition for CAN_BTR register  ********************/\n#define CAN_BTR_BRP_Pos        (0U)\n#define CAN_BTR_BRP_Msk        (0x3FFU << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */\n#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */\n#define CAN_BTR_TS1_Pos        (16U)\n#define CAN_BTR_TS1_Msk        (0xFU << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */\n#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */\n#define CAN_BTR_TS1_0          (0x1U << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */\n#define CAN_BTR_TS1_1          (0x2U << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */\n#define CAN_BTR_TS1_2          (0x4U << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */\n#define CAN_BTR_TS1_3          (0x8U << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */\n#define CAN_BTR_TS2_Pos        (20U)\n#define CAN_BTR_TS2_Msk        (0x7U << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */\n#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */\n#define CAN_BTR_TS2_0          (0x1U << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */\n#define CAN_BTR_TS2_1          (0x2U << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */\n#define CAN_BTR_TS2_2          (0x4U << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */\n#define CAN_BTR_SJW_Pos        (24U)\n#define CAN_BTR_SJW_Msk        (0x3U << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */\n#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */\n#define CAN_BTR_SJW_0          (0x1U << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */\n#define CAN_BTR_SJW_1          (0x2U << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */\n#define CAN_BTR_LBKM_Pos       (30U)\n#define CAN_BTR_LBKM_Msk       (0x1U << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */\n#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */\n#define CAN_BTR_SILM_Pos       (31U)\n#define CAN_BTR_SILM_Msk       (0x1U << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */\n#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */\n\n\n/*!<Mailbox registers */\n/******************  Bit definition for CAN_TI0R register  ********************/\n#define CAN_TI0R_TXRQ_Pos      (0U)\n#define CAN_TI0R_TXRQ_Msk      (0x1U << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI0R_RTR_Pos       (1U)\n#define CAN_TI0R_RTR_Msk       (0x1U << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI0R_IDE_Pos       (2U)\n#define CAN_TI0R_IDE_Msk       (0x1U << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI0R_EXID_Pos      (3U)\n#define CAN_TI0R_EXID_Msk      (0x3FFFFU << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI0R_STID_Pos      (21U)\n#define CAN_TI0R_STID_Msk      (0x7FFU << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/******************  Bit definition for CAN_TDT0R register  *******************/\n#define CAN_TDT0R_DLC_Pos      (0U)\n#define CAN_TDT0R_DLC_Msk      (0xFU << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT0R_TGT_Pos      (8U)\n#define CAN_TDT0R_TGT_Msk      (0x1U << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT0R_TIME_Pos     (16U)\n#define CAN_TDT0R_TIME_Msk     (0xFFFFU << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/******************  Bit definition for CAN_TDL0R register  *******************/\n#define CAN_TDL0R_DATA0_Pos    (0U)\n#define CAN_TDL0R_DATA0_Msk    (0xFFU << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL0R_DATA1_Pos    (8U)\n#define CAN_TDL0R_DATA1_Msk    (0xFFU << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL0R_DATA2_Pos    (16U)\n#define CAN_TDL0R_DATA2_Msk    (0xFFU << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL0R_DATA3_Pos    (24U)\n#define CAN_TDL0R_DATA3_Msk    (0xFFU << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/******************  Bit definition for CAN_TDH0R register  *******************/\n#define CAN_TDH0R_DATA4_Pos    (0U)\n#define CAN_TDH0R_DATA4_Msk    (0xFFU << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH0R_DATA5_Pos    (8U)\n#define CAN_TDH0R_DATA5_Msk    (0xFFU << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH0R_DATA6_Pos    (16U)\n#define CAN_TDH0R_DATA6_Msk    (0xFFU << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH0R_DATA7_Pos    (24U)\n#define CAN_TDH0R_DATA7_Msk    (0xFFU << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI1R register  *******************/\n#define CAN_TI1R_TXRQ_Pos      (0U)\n#define CAN_TI1R_TXRQ_Msk      (0x1U << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI1R_RTR_Pos       (1U)\n#define CAN_TI1R_RTR_Msk       (0x1U << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI1R_IDE_Pos       (2U)\n#define CAN_TI1R_IDE_Msk       (0x1U << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI1R_EXID_Pos      (3U)\n#define CAN_TI1R_EXID_Msk      (0x3FFFFU << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI1R_STID_Pos      (21U)\n#define CAN_TI1R_STID_Msk      (0x7FFU << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT1R register  ******************/\n#define CAN_TDT1R_DLC_Pos      (0U)\n#define CAN_TDT1R_DLC_Msk      (0xFU << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT1R_TGT_Pos      (8U)\n#define CAN_TDT1R_TGT_Msk      (0x1U << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT1R_TIME_Pos     (16U)\n#define CAN_TDT1R_TIME_Msk     (0xFFFFU << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL1R register  ******************/\n#define CAN_TDL1R_DATA0_Pos    (0U)\n#define CAN_TDL1R_DATA0_Msk    (0xFFU << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL1R_DATA1_Pos    (8U)\n#define CAN_TDL1R_DATA1_Msk    (0xFFU << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL1R_DATA2_Pos    (16U)\n#define CAN_TDL1R_DATA2_Msk    (0xFFU << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL1R_DATA3_Pos    (24U)\n#define CAN_TDL1R_DATA3_Msk    (0xFFU << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH1R register  ******************/\n#define CAN_TDH1R_DATA4_Pos    (0U)\n#define CAN_TDH1R_DATA4_Msk    (0xFFU << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH1R_DATA5_Pos    (8U)\n#define CAN_TDH1R_DATA5_Msk    (0xFFU << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH1R_DATA6_Pos    (16U)\n#define CAN_TDH1R_DATA6_Msk    (0xFFU << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH1R_DATA7_Pos    (24U)\n#define CAN_TDH1R_DATA7_Msk    (0xFFU << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI2R register  *******************/\n#define CAN_TI2R_TXRQ_Pos      (0U)\n#define CAN_TI2R_TXRQ_Msk      (0x1U << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI2R_RTR_Pos       (1U)\n#define CAN_TI2R_RTR_Msk       (0x1U << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI2R_IDE_Pos       (2U)\n#define CAN_TI2R_IDE_Msk       (0x1U << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI2R_EXID_Pos      (3U)\n#define CAN_TI2R_EXID_Msk      (0x3FFFFU << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_TI2R_STID_Pos      (21U)\n#define CAN_TI2R_STID_Msk      (0x7FFU << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT2R register  ******************/\n#define CAN_TDT2R_DLC_Pos      (0U)\n#define CAN_TDT2R_DLC_Msk      (0xFU << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT2R_TGT_Pos      (8U)\n#define CAN_TDT2R_TGT_Msk      (0x1U << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT2R_TIME_Pos     (16U)\n#define CAN_TDT2R_TIME_Msk     (0xFFFFU << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL2R register  ******************/\n#define CAN_TDL2R_DATA0_Pos    (0U)\n#define CAN_TDL2R_DATA0_Msk    (0xFFU << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL2R_DATA1_Pos    (8U)\n#define CAN_TDL2R_DATA1_Msk    (0xFFU << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL2R_DATA2_Pos    (16U)\n#define CAN_TDL2R_DATA2_Msk    (0xFFU << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL2R_DATA3_Pos    (24U)\n#define CAN_TDL2R_DATA3_Msk    (0xFFU << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH2R register  ******************/\n#define CAN_TDH2R_DATA4_Pos    (0U)\n#define CAN_TDH2R_DATA4_Msk    (0xFFU << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH2R_DATA5_Pos    (8U)\n#define CAN_TDH2R_DATA5_Msk    (0xFFU << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH2R_DATA6_Pos    (16U)\n#define CAN_TDH2R_DATA6_Msk    (0xFFU << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH2R_DATA7_Pos    (24U)\n#define CAN_TDH2R_DATA7_Msk    (0xFFU << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI0R register  *******************/\n#define CAN_RI0R_RTR_Pos       (1U)\n#define CAN_RI0R_RTR_Msk       (0x1U << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI0R_IDE_Pos       (2U)\n#define CAN_RI0R_IDE_Msk       (0x1U << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI0R_EXID_Pos      (3U)\n#define CAN_RI0R_EXID_Msk      (0x3FFFFU << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_RI0R_STID_Pos      (21U)\n#define CAN_RI0R_STID_Msk      (0x7FFU << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT0R register  ******************/\n#define CAN_RDT0R_DLC_Pos      (0U)\n#define CAN_RDT0R_DLC_Msk      (0xFU << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT0R_FMI_Pos      (8U)\n#define CAN_RDT0R_FMI_Msk      (0xFFU << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT0R_TIME_Pos     (16U)\n#define CAN_RDT0R_TIME_Msk     (0xFFFFU << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL0R register  ******************/\n#define CAN_RDL0R_DATA0_Pos    (0U)\n#define CAN_RDL0R_DATA0_Msk    (0xFFU << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL0R_DATA1_Pos    (8U)\n#define CAN_RDL0R_DATA1_Msk    (0xFFU << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL0R_DATA2_Pos    (16U)\n#define CAN_RDL0R_DATA2_Msk    (0xFFU << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL0R_DATA3_Pos    (24U)\n#define CAN_RDL0R_DATA3_Msk    (0xFFU << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH0R register  ******************/\n#define CAN_RDH0R_DATA4_Pos    (0U)\n#define CAN_RDH0R_DATA4_Msk    (0xFFU << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH0R_DATA5_Pos    (8U)\n#define CAN_RDH0R_DATA5_Msk    (0xFFU << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH0R_DATA6_Pos    (16U)\n#define CAN_RDH0R_DATA6_Msk    (0xFFU << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH0R_DATA7_Pos    (24U)\n#define CAN_RDH0R_DATA7_Msk    (0xFFU << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI1R register  *******************/\n#define CAN_RI1R_RTR_Pos       (1U)\n#define CAN_RI1R_RTR_Msk       (0x1U << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI1R_IDE_Pos       (2U)\n#define CAN_RI1R_IDE_Msk       (0x1U << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI1R_EXID_Pos      (3U)\n#define CAN_RI1R_EXID_Msk      (0x3FFFFU << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_RI1R_STID_Pos      (21U)\n#define CAN_RI1R_STID_Msk      (0x7FFU << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT1R register  ******************/\n#define CAN_RDT1R_DLC_Pos      (0U)\n#define CAN_RDT1R_DLC_Msk      (0xFU << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT1R_FMI_Pos      (8U)\n#define CAN_RDT1R_FMI_Msk      (0xFFU << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT1R_TIME_Pos     (16U)\n#define CAN_RDT1R_TIME_Msk     (0xFFFFU << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL1R register  ******************/\n#define CAN_RDL1R_DATA0_Pos    (0U)\n#define CAN_RDL1R_DATA0_Msk    (0xFFU << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL1R_DATA1_Pos    (8U)\n#define CAN_RDL1R_DATA1_Msk    (0xFFU << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL1R_DATA2_Pos    (16U)\n#define CAN_RDL1R_DATA2_Msk    (0xFFU << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL1R_DATA3_Pos    (24U)\n#define CAN_RDL1R_DATA3_Msk    (0xFFU << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH1R register  ******************/\n#define CAN_RDH1R_DATA4_Pos    (0U)\n#define CAN_RDH1R_DATA4_Msk    (0xFFU << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH1R_DATA5_Pos    (8U)\n#define CAN_RDH1R_DATA5_Msk    (0xFFU << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH1R_DATA6_Pos    (16U)\n#define CAN_RDH1R_DATA6_Msk    (0xFFU << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH1R_DATA7_Pos    (24U)\n#define CAN_RDH1R_DATA7_Msk    (0xFFU << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*!<CAN filter registers */\n/*******************  Bit definition for CAN_FMR register  ********************/\n#define CAN_FMR_FINIT_Pos      (0U)\n#define CAN_FMR_FINIT_Msk      (0x1U << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */\n#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */\n#define CAN_FMR_CAN2SB_Pos     (8U)\n#define CAN_FMR_CAN2SB_Msk     (0x3FU << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */\n#define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */\n\n/*******************  Bit definition for CAN_FM1R register  *******************/\n#define CAN_FM1R_FBM_Pos       (0U)\n#define CAN_FM1R_FBM_Msk       (0xFFFFFFFU << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */\n#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */\n#define CAN_FM1R_FBM0_Pos      (0U)\n#define CAN_FM1R_FBM0_Msk      (0x1U << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */\n#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */\n#define CAN_FM1R_FBM1_Pos      (1U)\n#define CAN_FM1R_FBM1_Msk      (0x1U << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */\n#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */\n#define CAN_FM1R_FBM2_Pos      (2U)\n#define CAN_FM1R_FBM2_Msk      (0x1U << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */\n#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */\n#define CAN_FM1R_FBM3_Pos      (3U)\n#define CAN_FM1R_FBM3_Msk      (0x1U << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */\n#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */\n#define CAN_FM1R_FBM4_Pos      (4U)\n#define CAN_FM1R_FBM4_Msk      (0x1U << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */\n#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */\n#define CAN_FM1R_FBM5_Pos      (5U)\n#define CAN_FM1R_FBM5_Msk      (0x1U << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */\n#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */\n#define CAN_FM1R_FBM6_Pos      (6U)\n#define CAN_FM1R_FBM6_Msk      (0x1U << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */\n#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */\n#define CAN_FM1R_FBM7_Pos      (7U)\n#define CAN_FM1R_FBM7_Msk      (0x1U << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */\n#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */\n#define CAN_FM1R_FBM8_Pos      (8U)\n#define CAN_FM1R_FBM8_Msk      (0x1U << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */\n#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */\n#define CAN_FM1R_FBM9_Pos      (9U)\n#define CAN_FM1R_FBM9_Msk      (0x1U << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */\n#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */\n#define CAN_FM1R_FBM10_Pos     (10U)\n#define CAN_FM1R_FBM10_Msk     (0x1U << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */\n#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */\n#define CAN_FM1R_FBM11_Pos     (11U)\n#define CAN_FM1R_FBM11_Msk     (0x1U << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */\n#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */\n#define CAN_FM1R_FBM12_Pos     (12U)\n#define CAN_FM1R_FBM12_Msk     (0x1U << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */\n#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */\n#define CAN_FM1R_FBM13_Pos     (13U)\n#define CAN_FM1R_FBM13_Msk     (0x1U << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */\n#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */\n#define CAN_FM1R_FBM14_Pos     (14U)\n#define CAN_FM1R_FBM14_Msk     (0x1U << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */\n#define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */\n#define CAN_FM1R_FBM15_Pos     (15U)\n#define CAN_FM1R_FBM15_Msk     (0x1U << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */\n#define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */\n#define CAN_FM1R_FBM16_Pos     (16U)\n#define CAN_FM1R_FBM16_Msk     (0x1U << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */\n#define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */\n#define CAN_FM1R_FBM17_Pos     (17U)\n#define CAN_FM1R_FBM17_Msk     (0x1U << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */\n#define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */\n#define CAN_FM1R_FBM18_Pos     (18U)\n#define CAN_FM1R_FBM18_Msk     (0x1U << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */\n#define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */\n#define CAN_FM1R_FBM19_Pos     (19U)\n#define CAN_FM1R_FBM19_Msk     (0x1U << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */\n#define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */\n#define CAN_FM1R_FBM20_Pos     (20U)\n#define CAN_FM1R_FBM20_Msk     (0x1U << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */\n#define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */\n#define CAN_FM1R_FBM21_Pos     (21U)\n#define CAN_FM1R_FBM21_Msk     (0x1U << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */\n#define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */\n#define CAN_FM1R_FBM22_Pos     (22U)\n#define CAN_FM1R_FBM22_Msk     (0x1U << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */\n#define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */\n#define CAN_FM1R_FBM23_Pos     (23U)\n#define CAN_FM1R_FBM23_Msk     (0x1U << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */\n#define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */\n#define CAN_FM1R_FBM24_Pos     (24U)\n#define CAN_FM1R_FBM24_Msk     (0x1U << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */\n#define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */\n#define CAN_FM1R_FBM25_Pos     (25U)\n#define CAN_FM1R_FBM25_Msk     (0x1U << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */\n#define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */\n#define CAN_FM1R_FBM26_Pos     (26U)\n#define CAN_FM1R_FBM26_Msk     (0x1U << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */\n#define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */\n#define CAN_FM1R_FBM27_Pos     (27U)\n#define CAN_FM1R_FBM27_Msk     (0x1U << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */\n#define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */\n\n/*******************  Bit definition for CAN_FS1R register  *******************/\n#define CAN_FS1R_FSC_Pos       (0U)\n#define CAN_FS1R_FSC_Msk       (0xFFFFFFFU << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */\n#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */\n#define CAN_FS1R_FSC0_Pos      (0U)\n#define CAN_FS1R_FSC0_Msk      (0x1U << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */\n#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */\n#define CAN_FS1R_FSC1_Pos      (1U)\n#define CAN_FS1R_FSC1_Msk      (0x1U << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */\n#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */\n#define CAN_FS1R_FSC2_Pos      (2U)\n#define CAN_FS1R_FSC2_Msk      (0x1U << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */\n#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */\n#define CAN_FS1R_FSC3_Pos      (3U)\n#define CAN_FS1R_FSC3_Msk      (0x1U << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */\n#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */\n#define CAN_FS1R_FSC4_Pos      (4U)\n#define CAN_FS1R_FSC4_Msk      (0x1U << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */\n#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */\n#define CAN_FS1R_FSC5_Pos      (5U)\n#define CAN_FS1R_FSC5_Msk      (0x1U << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */\n#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */\n#define CAN_FS1R_FSC6_Pos      (6U)\n#define CAN_FS1R_FSC6_Msk      (0x1U << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */\n#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */\n#define CAN_FS1R_FSC7_Pos      (7U)\n#define CAN_FS1R_FSC7_Msk      (0x1U << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */\n#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */\n#define CAN_FS1R_FSC8_Pos      (8U)\n#define CAN_FS1R_FSC8_Msk      (0x1U << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */\n#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */\n#define CAN_FS1R_FSC9_Pos      (9U)\n#define CAN_FS1R_FSC9_Msk      (0x1U << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */\n#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */\n#define CAN_FS1R_FSC10_Pos     (10U)\n#define CAN_FS1R_FSC10_Msk     (0x1U << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */\n#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */\n#define CAN_FS1R_FSC11_Pos     (11U)\n#define CAN_FS1R_FSC11_Msk     (0x1U << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */\n#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */\n#define CAN_FS1R_FSC12_Pos     (12U)\n#define CAN_FS1R_FSC12_Msk     (0x1U << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */\n#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */\n#define CAN_FS1R_FSC13_Pos     (13U)\n#define CAN_FS1R_FSC13_Msk     (0x1U << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */\n#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */\n#define CAN_FS1R_FSC14_Pos     (14U)\n#define CAN_FS1R_FSC14_Msk     (0x1U << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */\n#define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */\n#define CAN_FS1R_FSC15_Pos     (15U)\n#define CAN_FS1R_FSC15_Msk     (0x1U << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */\n#define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */\n#define CAN_FS1R_FSC16_Pos     (16U)\n#define CAN_FS1R_FSC16_Msk     (0x1U << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */\n#define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */\n#define CAN_FS1R_FSC17_Pos     (17U)\n#define CAN_FS1R_FSC17_Msk     (0x1U << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */\n#define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */\n#define CAN_FS1R_FSC18_Pos     (18U)\n#define CAN_FS1R_FSC18_Msk     (0x1U << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */\n#define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */\n#define CAN_FS1R_FSC19_Pos     (19U)\n#define CAN_FS1R_FSC19_Msk     (0x1U << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */\n#define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */\n#define CAN_FS1R_FSC20_Pos     (20U)\n#define CAN_FS1R_FSC20_Msk     (0x1U << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */\n#define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */\n#define CAN_FS1R_FSC21_Pos     (21U)\n#define CAN_FS1R_FSC21_Msk     (0x1U << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */\n#define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */\n#define CAN_FS1R_FSC22_Pos     (22U)\n#define CAN_FS1R_FSC22_Msk     (0x1U << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */\n#define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */\n#define CAN_FS1R_FSC23_Pos     (23U)\n#define CAN_FS1R_FSC23_Msk     (0x1U << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */\n#define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */\n#define CAN_FS1R_FSC24_Pos     (24U)\n#define CAN_FS1R_FSC24_Msk     (0x1U << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */\n#define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */\n#define CAN_FS1R_FSC25_Pos     (25U)\n#define CAN_FS1R_FSC25_Msk     (0x1U << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */\n#define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */\n#define CAN_FS1R_FSC26_Pos     (26U)\n#define CAN_FS1R_FSC26_Msk     (0x1U << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */\n#define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */\n#define CAN_FS1R_FSC27_Pos     (27U)\n#define CAN_FS1R_FSC27_Msk     (0x1U << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */\n#define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */\n\n/******************  Bit definition for CAN_FFA1R register  *******************/\n#define CAN_FFA1R_FFA_Pos      (0U)\n#define CAN_FFA1R_FFA_Msk      (0xFFFFFFFU << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */\n#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */\n#define CAN_FFA1R_FFA0_Pos     (0U)\n#define CAN_FFA1R_FFA0_Msk     (0x1U << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */\n#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */\n#define CAN_FFA1R_FFA1_Pos     (1U)\n#define CAN_FFA1R_FFA1_Msk     (0x1U << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */\n#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */\n#define CAN_FFA1R_FFA2_Pos     (2U)\n#define CAN_FFA1R_FFA2_Msk     (0x1U << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */\n#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */\n#define CAN_FFA1R_FFA3_Pos     (3U)\n#define CAN_FFA1R_FFA3_Msk     (0x1U << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */\n#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */\n#define CAN_FFA1R_FFA4_Pos     (4U)\n#define CAN_FFA1R_FFA4_Msk     (0x1U << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */\n#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */\n#define CAN_FFA1R_FFA5_Pos     (5U)\n#define CAN_FFA1R_FFA5_Msk     (0x1U << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */\n#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */\n#define CAN_FFA1R_FFA6_Pos     (6U)\n#define CAN_FFA1R_FFA6_Msk     (0x1U << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */\n#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */\n#define CAN_FFA1R_FFA7_Pos     (7U)\n#define CAN_FFA1R_FFA7_Msk     (0x1U << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */\n#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */\n#define CAN_FFA1R_FFA8_Pos     (8U)\n#define CAN_FFA1R_FFA8_Msk     (0x1U << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */\n#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */\n#define CAN_FFA1R_FFA9_Pos     (9U)\n#define CAN_FFA1R_FFA9_Msk     (0x1U << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */\n#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */\n#define CAN_FFA1R_FFA10_Pos    (10U)\n#define CAN_FFA1R_FFA10_Msk    (0x1U << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */\n#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */\n#define CAN_FFA1R_FFA11_Pos    (11U)\n#define CAN_FFA1R_FFA11_Msk    (0x1U << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */\n#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */\n#define CAN_FFA1R_FFA12_Pos    (12U)\n#define CAN_FFA1R_FFA12_Msk    (0x1U << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */\n#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */\n#define CAN_FFA1R_FFA13_Pos    (13U)\n#define CAN_FFA1R_FFA13_Msk    (0x1U << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */\n#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */\n#define CAN_FFA1R_FFA14_Pos    (14U)\n#define CAN_FFA1R_FFA14_Msk    (0x1U << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */\n#define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */\n#define CAN_FFA1R_FFA15_Pos    (15U)\n#define CAN_FFA1R_FFA15_Msk    (0x1U << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */\n#define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */\n#define CAN_FFA1R_FFA16_Pos    (16U)\n#define CAN_FFA1R_FFA16_Msk    (0x1U << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */\n#define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */\n#define CAN_FFA1R_FFA17_Pos    (17U)\n#define CAN_FFA1R_FFA17_Msk    (0x1U << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */\n#define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */\n#define CAN_FFA1R_FFA18_Pos    (18U)\n#define CAN_FFA1R_FFA18_Msk    (0x1U << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */\n#define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */\n#define CAN_FFA1R_FFA19_Pos    (19U)\n#define CAN_FFA1R_FFA19_Msk    (0x1U << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */\n#define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */\n#define CAN_FFA1R_FFA20_Pos    (20U)\n#define CAN_FFA1R_FFA20_Msk    (0x1U << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */\n#define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */\n#define CAN_FFA1R_FFA21_Pos    (21U)\n#define CAN_FFA1R_FFA21_Msk    (0x1U << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */\n#define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */\n#define CAN_FFA1R_FFA22_Pos    (22U)\n#define CAN_FFA1R_FFA22_Msk    (0x1U << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */\n#define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */\n#define CAN_FFA1R_FFA23_Pos    (23U)\n#define CAN_FFA1R_FFA23_Msk    (0x1U << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */\n#define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */\n#define CAN_FFA1R_FFA24_Pos    (24U)\n#define CAN_FFA1R_FFA24_Msk    (0x1U << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */\n#define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */\n#define CAN_FFA1R_FFA25_Pos    (25U)\n#define CAN_FFA1R_FFA25_Msk    (0x1U << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */\n#define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */\n#define CAN_FFA1R_FFA26_Pos    (26U)\n#define CAN_FFA1R_FFA26_Msk    (0x1U << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */\n#define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */\n#define CAN_FFA1R_FFA27_Pos    (27U)\n#define CAN_FFA1R_FFA27_Msk    (0x1U << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */\n#define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */\n\n/*******************  Bit definition for CAN_FA1R register  *******************/\n#define CAN_FA1R_FACT_Pos      (0U)\n#define CAN_FA1R_FACT_Msk      (0xFFFFFFFU << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */\n#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */\n#define CAN_FA1R_FACT0_Pos     (0U)\n#define CAN_FA1R_FACT0_Msk     (0x1U << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */\n#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */\n#define CAN_FA1R_FACT1_Pos     (1U)\n#define CAN_FA1R_FACT1_Msk     (0x1U << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */\n#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */\n#define CAN_FA1R_FACT2_Pos     (2U)\n#define CAN_FA1R_FACT2_Msk     (0x1U << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */\n#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */\n#define CAN_FA1R_FACT3_Pos     (3U)\n#define CAN_FA1R_FACT3_Msk     (0x1U << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */\n#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */\n#define CAN_FA1R_FACT4_Pos     (4U)\n#define CAN_FA1R_FACT4_Msk     (0x1U << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */\n#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */\n#define CAN_FA1R_FACT5_Pos     (5U)\n#define CAN_FA1R_FACT5_Msk     (0x1U << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */\n#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */\n#define CAN_FA1R_FACT6_Pos     (6U)\n#define CAN_FA1R_FACT6_Msk     (0x1U << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */\n#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */\n#define CAN_FA1R_FACT7_Pos     (7U)\n#define CAN_FA1R_FACT7_Msk     (0x1U << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */\n#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */\n#define CAN_FA1R_FACT8_Pos     (8U)\n#define CAN_FA1R_FACT8_Msk     (0x1U << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */\n#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */\n#define CAN_FA1R_FACT9_Pos     (9U)\n#define CAN_FA1R_FACT9_Msk     (0x1U << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */\n#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */\n#define CAN_FA1R_FACT10_Pos    (10U)\n#define CAN_FA1R_FACT10_Msk    (0x1U << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */\n#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */\n#define CAN_FA1R_FACT11_Pos    (11U)\n#define CAN_FA1R_FACT11_Msk    (0x1U << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */\n#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */\n#define CAN_FA1R_FACT12_Pos    (12U)\n#define CAN_FA1R_FACT12_Msk    (0x1U << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */\n#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */\n#define CAN_FA1R_FACT13_Pos    (13U)\n#define CAN_FA1R_FACT13_Msk    (0x1U << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */\n#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */\n#define CAN_FA1R_FACT14_Pos    (14U)\n#define CAN_FA1R_FACT14_Msk    (0x1U << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */\n#define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */\n#define CAN_FA1R_FACT15_Pos    (15U)\n#define CAN_FA1R_FACT15_Msk    (0x1U << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */\n#define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */\n#define CAN_FA1R_FACT16_Pos    (16U)\n#define CAN_FA1R_FACT16_Msk    (0x1U << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */\n#define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */\n#define CAN_FA1R_FACT17_Pos    (17U)\n#define CAN_FA1R_FACT17_Msk    (0x1U << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */\n#define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */\n#define CAN_FA1R_FACT18_Pos    (18U)\n#define CAN_FA1R_FACT18_Msk    (0x1U << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */\n#define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */\n#define CAN_FA1R_FACT19_Pos    (19U)\n#define CAN_FA1R_FACT19_Msk    (0x1U << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */\n#define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */\n#define CAN_FA1R_FACT20_Pos    (20U)\n#define CAN_FA1R_FACT20_Msk    (0x1U << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */\n#define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */\n#define CAN_FA1R_FACT21_Pos    (21U)\n#define CAN_FA1R_FACT21_Msk    (0x1U << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */\n#define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */\n#define CAN_FA1R_FACT22_Pos    (22U)\n#define CAN_FA1R_FACT22_Msk    (0x1U << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */\n#define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */\n#define CAN_FA1R_FACT23_Pos    (23U)\n#define CAN_FA1R_FACT23_Msk    (0x1U << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */\n#define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */\n#define CAN_FA1R_FACT24_Pos    (24U)\n#define CAN_FA1R_FACT24_Msk    (0x1U << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */\n#define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */\n#define CAN_FA1R_FACT25_Pos    (25U)\n#define CAN_FA1R_FACT25_Msk    (0x1U << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */\n#define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */\n#define CAN_FA1R_FACT26_Pos    (26U)\n#define CAN_FA1R_FACT26_Msk    (0x1U << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */\n#define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */\n#define CAN_FA1R_FACT27_Pos    (27U)\n#define CAN_FA1R_FACT27_Msk    (0x1U << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */\n#define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */\n\n\n/*******************  Bit definition for CAN_F0R1 register  *******************/\n#define CAN_F0R1_FB0_Pos       (0U)\n#define CAN_F0R1_FB0_Msk       (0x1U << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R1_FB1_Pos       (1U)\n#define CAN_F0R1_FB1_Msk       (0x1U << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R1_FB2_Pos       (2U)\n#define CAN_F0R1_FB2_Msk       (0x1U << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R1_FB3_Pos       (3U)\n#define CAN_F0R1_FB3_Msk       (0x1U << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R1_FB4_Pos       (4U)\n#define CAN_F0R1_FB4_Msk       (0x1U << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R1_FB5_Pos       (5U)\n#define CAN_F0R1_FB5_Msk       (0x1U << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R1_FB6_Pos       (6U)\n#define CAN_F0R1_FB6_Msk       (0x1U << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R1_FB7_Pos       (7U)\n#define CAN_F0R1_FB7_Msk       (0x1U << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R1_FB8_Pos       (8U)\n#define CAN_F0R1_FB8_Msk       (0x1U << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R1_FB9_Pos       (9U)\n#define CAN_F0R1_FB9_Msk       (0x1U << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R1_FB10_Pos      (10U)\n#define CAN_F0R1_FB10_Msk      (0x1U << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R1_FB11_Pos      (11U)\n#define CAN_F0R1_FB11_Msk      (0x1U << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R1_FB12_Pos      (12U)\n#define CAN_F0R1_FB12_Msk      (0x1U << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R1_FB13_Pos      (13U)\n#define CAN_F0R1_FB13_Msk      (0x1U << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R1_FB14_Pos      (14U)\n#define CAN_F0R1_FB14_Msk      (0x1U << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R1_FB15_Pos      (15U)\n#define CAN_F0R1_FB15_Msk      (0x1U << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R1_FB16_Pos      (16U)\n#define CAN_F0R1_FB16_Msk      (0x1U << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R1_FB17_Pos      (17U)\n#define CAN_F0R1_FB17_Msk      (0x1U << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R1_FB18_Pos      (18U)\n#define CAN_F0R1_FB18_Msk      (0x1U << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R1_FB19_Pos      (19U)\n#define CAN_F0R1_FB19_Msk      (0x1U << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R1_FB20_Pos      (20U)\n#define CAN_F0R1_FB20_Msk      (0x1U << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R1_FB21_Pos      (21U)\n#define CAN_F0R1_FB21_Msk      (0x1U << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R1_FB22_Pos      (22U)\n#define CAN_F0R1_FB22_Msk      (0x1U << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R1_FB23_Pos      (23U)\n#define CAN_F0R1_FB23_Msk      (0x1U << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R1_FB24_Pos      (24U)\n#define CAN_F0R1_FB24_Msk      (0x1U << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R1_FB25_Pos      (25U)\n#define CAN_F0R1_FB25_Msk      (0x1U << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R1_FB26_Pos      (26U)\n#define CAN_F0R1_FB26_Msk      (0x1U << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R1_FB27_Pos      (27U)\n#define CAN_F0R1_FB27_Msk      (0x1U << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R1_FB28_Pos      (28U)\n#define CAN_F0R1_FB28_Msk      (0x1U << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R1_FB29_Pos      (29U)\n#define CAN_F0R1_FB29_Msk      (0x1U << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R1_FB30_Pos      (30U)\n#define CAN_F0R1_FB30_Msk      (0x1U << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R1_FB31_Pos      (31U)\n#define CAN_F0R1_FB31_Msk      (0x1U << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R1 register  *******************/\n#define CAN_F1R1_FB0_Pos       (0U)\n#define CAN_F1R1_FB0_Msk       (0x1U << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R1_FB1_Pos       (1U)\n#define CAN_F1R1_FB1_Msk       (0x1U << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R1_FB2_Pos       (2U)\n#define CAN_F1R1_FB2_Msk       (0x1U << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R1_FB3_Pos       (3U)\n#define CAN_F1R1_FB3_Msk       (0x1U << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R1_FB4_Pos       (4U)\n#define CAN_F1R1_FB4_Msk       (0x1U << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R1_FB5_Pos       (5U)\n#define CAN_F1R1_FB5_Msk       (0x1U << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R1_FB6_Pos       (6U)\n#define CAN_F1R1_FB6_Msk       (0x1U << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R1_FB7_Pos       (7U)\n#define CAN_F1R1_FB7_Msk       (0x1U << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R1_FB8_Pos       (8U)\n#define CAN_F1R1_FB8_Msk       (0x1U << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R1_FB9_Pos       (9U)\n#define CAN_F1R1_FB9_Msk       (0x1U << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R1_FB10_Pos      (10U)\n#define CAN_F1R1_FB10_Msk      (0x1U << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R1_FB11_Pos      (11U)\n#define CAN_F1R1_FB11_Msk      (0x1U << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R1_FB12_Pos      (12U)\n#define CAN_F1R1_FB12_Msk      (0x1U << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R1_FB13_Pos      (13U)\n#define CAN_F1R1_FB13_Msk      (0x1U << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R1_FB14_Pos      (14U)\n#define CAN_F1R1_FB14_Msk      (0x1U << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R1_FB15_Pos      (15U)\n#define CAN_F1R1_FB15_Msk      (0x1U << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R1_FB16_Pos      (16U)\n#define CAN_F1R1_FB16_Msk      (0x1U << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R1_FB17_Pos      (17U)\n#define CAN_F1R1_FB17_Msk      (0x1U << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R1_FB18_Pos      (18U)\n#define CAN_F1R1_FB18_Msk      (0x1U << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R1_FB19_Pos      (19U)\n#define CAN_F1R1_FB19_Msk      (0x1U << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R1_FB20_Pos      (20U)\n#define CAN_F1R1_FB20_Msk      (0x1U << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R1_FB21_Pos      (21U)\n#define CAN_F1R1_FB21_Msk      (0x1U << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R1_FB22_Pos      (22U)\n#define CAN_F1R1_FB22_Msk      (0x1U << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R1_FB23_Pos      (23U)\n#define CAN_F1R1_FB23_Msk      (0x1U << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R1_FB24_Pos      (24U)\n#define CAN_F1R1_FB24_Msk      (0x1U << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R1_FB25_Pos      (25U)\n#define CAN_F1R1_FB25_Msk      (0x1U << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R1_FB26_Pos      (26U)\n#define CAN_F1R1_FB26_Msk      (0x1U << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R1_FB27_Pos      (27U)\n#define CAN_F1R1_FB27_Msk      (0x1U << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R1_FB28_Pos      (28U)\n#define CAN_F1R1_FB28_Msk      (0x1U << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R1_FB29_Pos      (29U)\n#define CAN_F1R1_FB29_Msk      (0x1U << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R1_FB30_Pos      (30U)\n#define CAN_F1R1_FB30_Msk      (0x1U << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R1_FB31_Pos      (31U)\n#define CAN_F1R1_FB31_Msk      (0x1U << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R1 register  *******************/\n#define CAN_F2R1_FB0_Pos       (0U)\n#define CAN_F2R1_FB0_Msk       (0x1U << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R1_FB1_Pos       (1U)\n#define CAN_F2R1_FB1_Msk       (0x1U << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R1_FB2_Pos       (2U)\n#define CAN_F2R1_FB2_Msk       (0x1U << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R1_FB3_Pos       (3U)\n#define CAN_F2R1_FB3_Msk       (0x1U << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R1_FB4_Pos       (4U)\n#define CAN_F2R1_FB4_Msk       (0x1U << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R1_FB5_Pos       (5U)\n#define CAN_F2R1_FB5_Msk       (0x1U << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R1_FB6_Pos       (6U)\n#define CAN_F2R1_FB6_Msk       (0x1U << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R1_FB7_Pos       (7U)\n#define CAN_F2R1_FB7_Msk       (0x1U << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R1_FB8_Pos       (8U)\n#define CAN_F2R1_FB8_Msk       (0x1U << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R1_FB9_Pos       (9U)\n#define CAN_F2R1_FB9_Msk       (0x1U << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R1_FB10_Pos      (10U)\n#define CAN_F2R1_FB10_Msk      (0x1U << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R1_FB11_Pos      (11U)\n#define CAN_F2R1_FB11_Msk      (0x1U << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R1_FB12_Pos      (12U)\n#define CAN_F2R1_FB12_Msk      (0x1U << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R1_FB13_Pos      (13U)\n#define CAN_F2R1_FB13_Msk      (0x1U << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R1_FB14_Pos      (14U)\n#define CAN_F2R1_FB14_Msk      (0x1U << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R1_FB15_Pos      (15U)\n#define CAN_F2R1_FB15_Msk      (0x1U << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R1_FB16_Pos      (16U)\n#define CAN_F2R1_FB16_Msk      (0x1U << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R1_FB17_Pos      (17U)\n#define CAN_F2R1_FB17_Msk      (0x1U << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R1_FB18_Pos      (18U)\n#define CAN_F2R1_FB18_Msk      (0x1U << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R1_FB19_Pos      (19U)\n#define CAN_F2R1_FB19_Msk      (0x1U << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R1_FB20_Pos      (20U)\n#define CAN_F2R1_FB20_Msk      (0x1U << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R1_FB21_Pos      (21U)\n#define CAN_F2R1_FB21_Msk      (0x1U << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R1_FB22_Pos      (22U)\n#define CAN_F2R1_FB22_Msk      (0x1U << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R1_FB23_Pos      (23U)\n#define CAN_F2R1_FB23_Msk      (0x1U << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R1_FB24_Pos      (24U)\n#define CAN_F2R1_FB24_Msk      (0x1U << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R1_FB25_Pos      (25U)\n#define CAN_F2R1_FB25_Msk      (0x1U << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R1_FB26_Pos      (26U)\n#define CAN_F2R1_FB26_Msk      (0x1U << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R1_FB27_Pos      (27U)\n#define CAN_F2R1_FB27_Msk      (0x1U << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R1_FB28_Pos      (28U)\n#define CAN_F2R1_FB28_Msk      (0x1U << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R1_FB29_Pos      (29U)\n#define CAN_F2R1_FB29_Msk      (0x1U << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R1_FB30_Pos      (30U)\n#define CAN_F2R1_FB30_Msk      (0x1U << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R1_FB31_Pos      (31U)\n#define CAN_F2R1_FB31_Msk      (0x1U << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R1 register  *******************/\n#define CAN_F3R1_FB0_Pos       (0U)\n#define CAN_F3R1_FB0_Msk       (0x1U << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R1_FB1_Pos       (1U)\n#define CAN_F3R1_FB1_Msk       (0x1U << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R1_FB2_Pos       (2U)\n#define CAN_F3R1_FB2_Msk       (0x1U << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R1_FB3_Pos       (3U)\n#define CAN_F3R1_FB3_Msk       (0x1U << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R1_FB4_Pos       (4U)\n#define CAN_F3R1_FB4_Msk       (0x1U << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R1_FB5_Pos       (5U)\n#define CAN_F3R1_FB5_Msk       (0x1U << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R1_FB6_Pos       (6U)\n#define CAN_F3R1_FB6_Msk       (0x1U << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R1_FB7_Pos       (7U)\n#define CAN_F3R1_FB7_Msk       (0x1U << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R1_FB8_Pos       (8U)\n#define CAN_F3R1_FB8_Msk       (0x1U << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R1_FB9_Pos       (9U)\n#define CAN_F3R1_FB9_Msk       (0x1U << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R1_FB10_Pos      (10U)\n#define CAN_F3R1_FB10_Msk      (0x1U << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R1_FB11_Pos      (11U)\n#define CAN_F3R1_FB11_Msk      (0x1U << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R1_FB12_Pos      (12U)\n#define CAN_F3R1_FB12_Msk      (0x1U << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R1_FB13_Pos      (13U)\n#define CAN_F3R1_FB13_Msk      (0x1U << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R1_FB14_Pos      (14U)\n#define CAN_F3R1_FB14_Msk      (0x1U << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R1_FB15_Pos      (15U)\n#define CAN_F3R1_FB15_Msk      (0x1U << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R1_FB16_Pos      (16U)\n#define CAN_F3R1_FB16_Msk      (0x1U << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R1_FB17_Pos      (17U)\n#define CAN_F3R1_FB17_Msk      (0x1U << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R1_FB18_Pos      (18U)\n#define CAN_F3R1_FB18_Msk      (0x1U << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R1_FB19_Pos      (19U)\n#define CAN_F3R1_FB19_Msk      (0x1U << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R1_FB20_Pos      (20U)\n#define CAN_F3R1_FB20_Msk      (0x1U << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R1_FB21_Pos      (21U)\n#define CAN_F3R1_FB21_Msk      (0x1U << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R1_FB22_Pos      (22U)\n#define CAN_F3R1_FB22_Msk      (0x1U << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R1_FB23_Pos      (23U)\n#define CAN_F3R1_FB23_Msk      (0x1U << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R1_FB24_Pos      (24U)\n#define CAN_F3R1_FB24_Msk      (0x1U << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R1_FB25_Pos      (25U)\n#define CAN_F3R1_FB25_Msk      (0x1U << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R1_FB26_Pos      (26U)\n#define CAN_F3R1_FB26_Msk      (0x1U << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R1_FB27_Pos      (27U)\n#define CAN_F3R1_FB27_Msk      (0x1U << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R1_FB28_Pos      (28U)\n#define CAN_F3R1_FB28_Msk      (0x1U << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R1_FB29_Pos      (29U)\n#define CAN_F3R1_FB29_Msk      (0x1U << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R1_FB30_Pos      (30U)\n#define CAN_F3R1_FB30_Msk      (0x1U << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R1_FB31_Pos      (31U)\n#define CAN_F3R1_FB31_Msk      (0x1U << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R1 register  *******************/\n#define CAN_F4R1_FB0_Pos       (0U)\n#define CAN_F4R1_FB0_Msk       (0x1U << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R1_FB1_Pos       (1U)\n#define CAN_F4R1_FB1_Msk       (0x1U << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R1_FB2_Pos       (2U)\n#define CAN_F4R1_FB2_Msk       (0x1U << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R1_FB3_Pos       (3U)\n#define CAN_F4R1_FB3_Msk       (0x1U << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R1_FB4_Pos       (4U)\n#define CAN_F4R1_FB4_Msk       (0x1U << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R1_FB5_Pos       (5U)\n#define CAN_F4R1_FB5_Msk       (0x1U << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R1_FB6_Pos       (6U)\n#define CAN_F4R1_FB6_Msk       (0x1U << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R1_FB7_Pos       (7U)\n#define CAN_F4R1_FB7_Msk       (0x1U << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R1_FB8_Pos       (8U)\n#define CAN_F4R1_FB8_Msk       (0x1U << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R1_FB9_Pos       (9U)\n#define CAN_F4R1_FB9_Msk       (0x1U << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R1_FB10_Pos      (10U)\n#define CAN_F4R1_FB10_Msk      (0x1U << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R1_FB11_Pos      (11U)\n#define CAN_F4R1_FB11_Msk      (0x1U << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R1_FB12_Pos      (12U)\n#define CAN_F4R1_FB12_Msk      (0x1U << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R1_FB13_Pos      (13U)\n#define CAN_F4R1_FB13_Msk      (0x1U << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R1_FB14_Pos      (14U)\n#define CAN_F4R1_FB14_Msk      (0x1U << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R1_FB15_Pos      (15U)\n#define CAN_F4R1_FB15_Msk      (0x1U << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R1_FB16_Pos      (16U)\n#define CAN_F4R1_FB16_Msk      (0x1U << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R1_FB17_Pos      (17U)\n#define CAN_F4R1_FB17_Msk      (0x1U << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R1_FB18_Pos      (18U)\n#define CAN_F4R1_FB18_Msk      (0x1U << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R1_FB19_Pos      (19U)\n#define CAN_F4R1_FB19_Msk      (0x1U << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R1_FB20_Pos      (20U)\n#define CAN_F4R1_FB20_Msk      (0x1U << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R1_FB21_Pos      (21U)\n#define CAN_F4R1_FB21_Msk      (0x1U << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R1_FB22_Pos      (22U)\n#define CAN_F4R1_FB22_Msk      (0x1U << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R1_FB23_Pos      (23U)\n#define CAN_F4R1_FB23_Msk      (0x1U << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R1_FB24_Pos      (24U)\n#define CAN_F4R1_FB24_Msk      (0x1U << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R1_FB25_Pos      (25U)\n#define CAN_F4R1_FB25_Msk      (0x1U << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R1_FB26_Pos      (26U)\n#define CAN_F4R1_FB26_Msk      (0x1U << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R1_FB27_Pos      (27U)\n#define CAN_F4R1_FB27_Msk      (0x1U << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R1_FB28_Pos      (28U)\n#define CAN_F4R1_FB28_Msk      (0x1U << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R1_FB29_Pos      (29U)\n#define CAN_F4R1_FB29_Msk      (0x1U << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R1_FB30_Pos      (30U)\n#define CAN_F4R1_FB30_Msk      (0x1U << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R1_FB31_Pos      (31U)\n#define CAN_F4R1_FB31_Msk      (0x1U << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R1 register  *******************/\n#define CAN_F5R1_FB0_Pos       (0U)\n#define CAN_F5R1_FB0_Msk       (0x1U << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R1_FB1_Pos       (1U)\n#define CAN_F5R1_FB1_Msk       (0x1U << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R1_FB2_Pos       (2U)\n#define CAN_F5R1_FB2_Msk       (0x1U << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R1_FB3_Pos       (3U)\n#define CAN_F5R1_FB3_Msk       (0x1U << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R1_FB4_Pos       (4U)\n#define CAN_F5R1_FB4_Msk       (0x1U << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R1_FB5_Pos       (5U)\n#define CAN_F5R1_FB5_Msk       (0x1U << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R1_FB6_Pos       (6U)\n#define CAN_F5R1_FB6_Msk       (0x1U << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R1_FB7_Pos       (7U)\n#define CAN_F5R1_FB7_Msk       (0x1U << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R1_FB8_Pos       (8U)\n#define CAN_F5R1_FB8_Msk       (0x1U << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R1_FB9_Pos       (9U)\n#define CAN_F5R1_FB9_Msk       (0x1U << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R1_FB10_Pos      (10U)\n#define CAN_F5R1_FB10_Msk      (0x1U << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R1_FB11_Pos      (11U)\n#define CAN_F5R1_FB11_Msk      (0x1U << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R1_FB12_Pos      (12U)\n#define CAN_F5R1_FB12_Msk      (0x1U << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R1_FB13_Pos      (13U)\n#define CAN_F5R1_FB13_Msk      (0x1U << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R1_FB14_Pos      (14U)\n#define CAN_F5R1_FB14_Msk      (0x1U << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R1_FB15_Pos      (15U)\n#define CAN_F5R1_FB15_Msk      (0x1U << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R1_FB16_Pos      (16U)\n#define CAN_F5R1_FB16_Msk      (0x1U << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R1_FB17_Pos      (17U)\n#define CAN_F5R1_FB17_Msk      (0x1U << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R1_FB18_Pos      (18U)\n#define CAN_F5R1_FB18_Msk      (0x1U << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R1_FB19_Pos      (19U)\n#define CAN_F5R1_FB19_Msk      (0x1U << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R1_FB20_Pos      (20U)\n#define CAN_F5R1_FB20_Msk      (0x1U << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R1_FB21_Pos      (21U)\n#define CAN_F5R1_FB21_Msk      (0x1U << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R1_FB22_Pos      (22U)\n#define CAN_F5R1_FB22_Msk      (0x1U << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R1_FB23_Pos      (23U)\n#define CAN_F5R1_FB23_Msk      (0x1U << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R1_FB24_Pos      (24U)\n#define CAN_F5R1_FB24_Msk      (0x1U << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R1_FB25_Pos      (25U)\n#define CAN_F5R1_FB25_Msk      (0x1U << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R1_FB26_Pos      (26U)\n#define CAN_F5R1_FB26_Msk      (0x1U << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R1_FB27_Pos      (27U)\n#define CAN_F5R1_FB27_Msk      (0x1U << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R1_FB28_Pos      (28U)\n#define CAN_F5R1_FB28_Msk      (0x1U << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R1_FB29_Pos      (29U)\n#define CAN_F5R1_FB29_Msk      (0x1U << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R1_FB30_Pos      (30U)\n#define CAN_F5R1_FB30_Msk      (0x1U << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R1_FB31_Pos      (31U)\n#define CAN_F5R1_FB31_Msk      (0x1U << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R1 register  *******************/\n#define CAN_F6R1_FB0_Pos       (0U)\n#define CAN_F6R1_FB0_Msk       (0x1U << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R1_FB1_Pos       (1U)\n#define CAN_F6R1_FB1_Msk       (0x1U << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R1_FB2_Pos       (2U)\n#define CAN_F6R1_FB2_Msk       (0x1U << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R1_FB3_Pos       (3U)\n#define CAN_F6R1_FB3_Msk       (0x1U << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R1_FB4_Pos       (4U)\n#define CAN_F6R1_FB4_Msk       (0x1U << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R1_FB5_Pos       (5U)\n#define CAN_F6R1_FB5_Msk       (0x1U << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R1_FB6_Pos       (6U)\n#define CAN_F6R1_FB6_Msk       (0x1U << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R1_FB7_Pos       (7U)\n#define CAN_F6R1_FB7_Msk       (0x1U << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R1_FB8_Pos       (8U)\n#define CAN_F6R1_FB8_Msk       (0x1U << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R1_FB9_Pos       (9U)\n#define CAN_F6R1_FB9_Msk       (0x1U << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R1_FB10_Pos      (10U)\n#define CAN_F6R1_FB10_Msk      (0x1U << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R1_FB11_Pos      (11U)\n#define CAN_F6R1_FB11_Msk      (0x1U << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R1_FB12_Pos      (12U)\n#define CAN_F6R1_FB12_Msk      (0x1U << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R1_FB13_Pos      (13U)\n#define CAN_F6R1_FB13_Msk      (0x1U << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R1_FB14_Pos      (14U)\n#define CAN_F6R1_FB14_Msk      (0x1U << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R1_FB15_Pos      (15U)\n#define CAN_F6R1_FB15_Msk      (0x1U << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R1_FB16_Pos      (16U)\n#define CAN_F6R1_FB16_Msk      (0x1U << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R1_FB17_Pos      (17U)\n#define CAN_F6R1_FB17_Msk      (0x1U << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R1_FB18_Pos      (18U)\n#define CAN_F6R1_FB18_Msk      (0x1U << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R1_FB19_Pos      (19U)\n#define CAN_F6R1_FB19_Msk      (0x1U << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R1_FB20_Pos      (20U)\n#define CAN_F6R1_FB20_Msk      (0x1U << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R1_FB21_Pos      (21U)\n#define CAN_F6R1_FB21_Msk      (0x1U << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R1_FB22_Pos      (22U)\n#define CAN_F6R1_FB22_Msk      (0x1U << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R1_FB23_Pos      (23U)\n#define CAN_F6R1_FB23_Msk      (0x1U << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R1_FB24_Pos      (24U)\n#define CAN_F6R1_FB24_Msk      (0x1U << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R1_FB25_Pos      (25U)\n#define CAN_F6R1_FB25_Msk      (0x1U << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R1_FB26_Pos      (26U)\n#define CAN_F6R1_FB26_Msk      (0x1U << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R1_FB27_Pos      (27U)\n#define CAN_F6R1_FB27_Msk      (0x1U << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R1_FB28_Pos      (28U)\n#define CAN_F6R1_FB28_Msk      (0x1U << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R1_FB29_Pos      (29U)\n#define CAN_F6R1_FB29_Msk      (0x1U << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R1_FB30_Pos      (30U)\n#define CAN_F6R1_FB30_Msk      (0x1U << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R1_FB31_Pos      (31U)\n#define CAN_F6R1_FB31_Msk      (0x1U << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R1 register  *******************/\n#define CAN_F7R1_FB0_Pos       (0U)\n#define CAN_F7R1_FB0_Msk       (0x1U << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R1_FB1_Pos       (1U)\n#define CAN_F7R1_FB1_Msk       (0x1U << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R1_FB2_Pos       (2U)\n#define CAN_F7R1_FB2_Msk       (0x1U << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R1_FB3_Pos       (3U)\n#define CAN_F7R1_FB3_Msk       (0x1U << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R1_FB4_Pos       (4U)\n#define CAN_F7R1_FB4_Msk       (0x1U << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R1_FB5_Pos       (5U)\n#define CAN_F7R1_FB5_Msk       (0x1U << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R1_FB6_Pos       (6U)\n#define CAN_F7R1_FB6_Msk       (0x1U << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R1_FB7_Pos       (7U)\n#define CAN_F7R1_FB7_Msk       (0x1U << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R1_FB8_Pos       (8U)\n#define CAN_F7R1_FB8_Msk       (0x1U << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R1_FB9_Pos       (9U)\n#define CAN_F7R1_FB9_Msk       (0x1U << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R1_FB10_Pos      (10U)\n#define CAN_F7R1_FB10_Msk      (0x1U << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R1_FB11_Pos      (11U)\n#define CAN_F7R1_FB11_Msk      (0x1U << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R1_FB12_Pos      (12U)\n#define CAN_F7R1_FB12_Msk      (0x1U << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R1_FB13_Pos      (13U)\n#define CAN_F7R1_FB13_Msk      (0x1U << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R1_FB14_Pos      (14U)\n#define CAN_F7R1_FB14_Msk      (0x1U << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R1_FB15_Pos      (15U)\n#define CAN_F7R1_FB15_Msk      (0x1U << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R1_FB16_Pos      (16U)\n#define CAN_F7R1_FB16_Msk      (0x1U << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R1_FB17_Pos      (17U)\n#define CAN_F7R1_FB17_Msk      (0x1U << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R1_FB18_Pos      (18U)\n#define CAN_F7R1_FB18_Msk      (0x1U << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R1_FB19_Pos      (19U)\n#define CAN_F7R1_FB19_Msk      (0x1U << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R1_FB20_Pos      (20U)\n#define CAN_F7R1_FB20_Msk      (0x1U << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R1_FB21_Pos      (21U)\n#define CAN_F7R1_FB21_Msk      (0x1U << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R1_FB22_Pos      (22U)\n#define CAN_F7R1_FB22_Msk      (0x1U << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R1_FB23_Pos      (23U)\n#define CAN_F7R1_FB23_Msk      (0x1U << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R1_FB24_Pos      (24U)\n#define CAN_F7R1_FB24_Msk      (0x1U << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R1_FB25_Pos      (25U)\n#define CAN_F7R1_FB25_Msk      (0x1U << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R1_FB26_Pos      (26U)\n#define CAN_F7R1_FB26_Msk      (0x1U << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R1_FB27_Pos      (27U)\n#define CAN_F7R1_FB27_Msk      (0x1U << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R1_FB28_Pos      (28U)\n#define CAN_F7R1_FB28_Msk      (0x1U << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R1_FB29_Pos      (29U)\n#define CAN_F7R1_FB29_Msk      (0x1U << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R1_FB30_Pos      (30U)\n#define CAN_F7R1_FB30_Msk      (0x1U << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R1_FB31_Pos      (31U)\n#define CAN_F7R1_FB31_Msk      (0x1U << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R1 register  *******************/\n#define CAN_F8R1_FB0_Pos       (0U)\n#define CAN_F8R1_FB0_Msk       (0x1U << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R1_FB1_Pos       (1U)\n#define CAN_F8R1_FB1_Msk       (0x1U << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R1_FB2_Pos       (2U)\n#define CAN_F8R1_FB2_Msk       (0x1U << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R1_FB3_Pos       (3U)\n#define CAN_F8R1_FB3_Msk       (0x1U << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R1_FB4_Pos       (4U)\n#define CAN_F8R1_FB4_Msk       (0x1U << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R1_FB5_Pos       (5U)\n#define CAN_F8R1_FB5_Msk       (0x1U << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R1_FB6_Pos       (6U)\n#define CAN_F8R1_FB6_Msk       (0x1U << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R1_FB7_Pos       (7U)\n#define CAN_F8R1_FB7_Msk       (0x1U << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R1_FB8_Pos       (8U)\n#define CAN_F8R1_FB8_Msk       (0x1U << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R1_FB9_Pos       (9U)\n#define CAN_F8R1_FB9_Msk       (0x1U << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R1_FB10_Pos      (10U)\n#define CAN_F8R1_FB10_Msk      (0x1U << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R1_FB11_Pos      (11U)\n#define CAN_F8R1_FB11_Msk      (0x1U << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R1_FB12_Pos      (12U)\n#define CAN_F8R1_FB12_Msk      (0x1U << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R1_FB13_Pos      (13U)\n#define CAN_F8R1_FB13_Msk      (0x1U << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R1_FB14_Pos      (14U)\n#define CAN_F8R1_FB14_Msk      (0x1U << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R1_FB15_Pos      (15U)\n#define CAN_F8R1_FB15_Msk      (0x1U << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R1_FB16_Pos      (16U)\n#define CAN_F8R1_FB16_Msk      (0x1U << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R1_FB17_Pos      (17U)\n#define CAN_F8R1_FB17_Msk      (0x1U << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R1_FB18_Pos      (18U)\n#define CAN_F8R1_FB18_Msk      (0x1U << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R1_FB19_Pos      (19U)\n#define CAN_F8R1_FB19_Msk      (0x1U << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R1_FB20_Pos      (20U)\n#define CAN_F8R1_FB20_Msk      (0x1U << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R1_FB21_Pos      (21U)\n#define CAN_F8R1_FB21_Msk      (0x1U << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R1_FB22_Pos      (22U)\n#define CAN_F8R1_FB22_Msk      (0x1U << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R1_FB23_Pos      (23U)\n#define CAN_F8R1_FB23_Msk      (0x1U << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R1_FB24_Pos      (24U)\n#define CAN_F8R1_FB24_Msk      (0x1U << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R1_FB25_Pos      (25U)\n#define CAN_F8R1_FB25_Msk      (0x1U << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R1_FB26_Pos      (26U)\n#define CAN_F8R1_FB26_Msk      (0x1U << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R1_FB27_Pos      (27U)\n#define CAN_F8R1_FB27_Msk      (0x1U << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R1_FB28_Pos      (28U)\n#define CAN_F8R1_FB28_Msk      (0x1U << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R1_FB29_Pos      (29U)\n#define CAN_F8R1_FB29_Msk      (0x1U << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R1_FB30_Pos      (30U)\n#define CAN_F8R1_FB30_Msk      (0x1U << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R1_FB31_Pos      (31U)\n#define CAN_F8R1_FB31_Msk      (0x1U << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R1 register  *******************/\n#define CAN_F9R1_FB0_Pos       (0U)\n#define CAN_F9R1_FB0_Msk       (0x1U << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R1_FB1_Pos       (1U)\n#define CAN_F9R1_FB1_Msk       (0x1U << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R1_FB2_Pos       (2U)\n#define CAN_F9R1_FB2_Msk       (0x1U << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R1_FB3_Pos       (3U)\n#define CAN_F9R1_FB3_Msk       (0x1U << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R1_FB4_Pos       (4U)\n#define CAN_F9R1_FB4_Msk       (0x1U << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R1_FB5_Pos       (5U)\n#define CAN_F9R1_FB5_Msk       (0x1U << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R1_FB6_Pos       (6U)\n#define CAN_F9R1_FB6_Msk       (0x1U << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R1_FB7_Pos       (7U)\n#define CAN_F9R1_FB7_Msk       (0x1U << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R1_FB8_Pos       (8U)\n#define CAN_F9R1_FB8_Msk       (0x1U << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R1_FB9_Pos       (9U)\n#define CAN_F9R1_FB9_Msk       (0x1U << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R1_FB10_Pos      (10U)\n#define CAN_F9R1_FB10_Msk      (0x1U << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R1_FB11_Pos      (11U)\n#define CAN_F9R1_FB11_Msk      (0x1U << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R1_FB12_Pos      (12U)\n#define CAN_F9R1_FB12_Msk      (0x1U << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R1_FB13_Pos      (13U)\n#define CAN_F9R1_FB13_Msk      (0x1U << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R1_FB14_Pos      (14U)\n#define CAN_F9R1_FB14_Msk      (0x1U << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R1_FB15_Pos      (15U)\n#define CAN_F9R1_FB15_Msk      (0x1U << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R1_FB16_Pos      (16U)\n#define CAN_F9R1_FB16_Msk      (0x1U << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R1_FB17_Pos      (17U)\n#define CAN_F9R1_FB17_Msk      (0x1U << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R1_FB18_Pos      (18U)\n#define CAN_F9R1_FB18_Msk      (0x1U << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R1_FB19_Pos      (19U)\n#define CAN_F9R1_FB19_Msk      (0x1U << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R1_FB20_Pos      (20U)\n#define CAN_F9R1_FB20_Msk      (0x1U << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R1_FB21_Pos      (21U)\n#define CAN_F9R1_FB21_Msk      (0x1U << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R1_FB22_Pos      (22U)\n#define CAN_F9R1_FB22_Msk      (0x1U << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R1_FB23_Pos      (23U)\n#define CAN_F9R1_FB23_Msk      (0x1U << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R1_FB24_Pos      (24U)\n#define CAN_F9R1_FB24_Msk      (0x1U << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R1_FB25_Pos      (25U)\n#define CAN_F9R1_FB25_Msk      (0x1U << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R1_FB26_Pos      (26U)\n#define CAN_F9R1_FB26_Msk      (0x1U << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R1_FB27_Pos      (27U)\n#define CAN_F9R1_FB27_Msk      (0x1U << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R1_FB28_Pos      (28U)\n#define CAN_F9R1_FB28_Msk      (0x1U << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R1_FB29_Pos      (29U)\n#define CAN_F9R1_FB29_Msk      (0x1U << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R1_FB30_Pos      (30U)\n#define CAN_F9R1_FB30_Msk      (0x1U << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R1_FB31_Pos      (31U)\n#define CAN_F9R1_FB31_Msk      (0x1U << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R1 register  ******************/\n#define CAN_F10R1_FB0_Pos      (0U)\n#define CAN_F10R1_FB0_Msk      (0x1U << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R1_FB1_Pos      (1U)\n#define CAN_F10R1_FB1_Msk      (0x1U << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R1_FB2_Pos      (2U)\n#define CAN_F10R1_FB2_Msk      (0x1U << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R1_FB3_Pos      (3U)\n#define CAN_F10R1_FB3_Msk      (0x1U << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R1_FB4_Pos      (4U)\n#define CAN_F10R1_FB4_Msk      (0x1U << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R1_FB5_Pos      (5U)\n#define CAN_F10R1_FB5_Msk      (0x1U << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R1_FB6_Pos      (6U)\n#define CAN_F10R1_FB6_Msk      (0x1U << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R1_FB7_Pos      (7U)\n#define CAN_F10R1_FB7_Msk      (0x1U << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R1_FB8_Pos      (8U)\n#define CAN_F10R1_FB8_Msk      (0x1U << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R1_FB9_Pos      (9U)\n#define CAN_F10R1_FB9_Msk      (0x1U << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R1_FB10_Pos     (10U)\n#define CAN_F10R1_FB10_Msk     (0x1U << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R1_FB11_Pos     (11U)\n#define CAN_F10R1_FB11_Msk     (0x1U << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R1_FB12_Pos     (12U)\n#define CAN_F10R1_FB12_Msk     (0x1U << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R1_FB13_Pos     (13U)\n#define CAN_F10R1_FB13_Msk     (0x1U << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R1_FB14_Pos     (14U)\n#define CAN_F10R1_FB14_Msk     (0x1U << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R1_FB15_Pos     (15U)\n#define CAN_F10R1_FB15_Msk     (0x1U << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R1_FB16_Pos     (16U)\n#define CAN_F10R1_FB16_Msk     (0x1U << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R1_FB17_Pos     (17U)\n#define CAN_F10R1_FB17_Msk     (0x1U << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R1_FB18_Pos     (18U)\n#define CAN_F10R1_FB18_Msk     (0x1U << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R1_FB19_Pos     (19U)\n#define CAN_F10R1_FB19_Msk     (0x1U << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R1_FB20_Pos     (20U)\n#define CAN_F10R1_FB20_Msk     (0x1U << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R1_FB21_Pos     (21U)\n#define CAN_F10R1_FB21_Msk     (0x1U << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R1_FB22_Pos     (22U)\n#define CAN_F10R1_FB22_Msk     (0x1U << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R1_FB23_Pos     (23U)\n#define CAN_F10R1_FB23_Msk     (0x1U << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R1_FB24_Pos     (24U)\n#define CAN_F10R1_FB24_Msk     (0x1U << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R1_FB25_Pos     (25U)\n#define CAN_F10R1_FB25_Msk     (0x1U << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R1_FB26_Pos     (26U)\n#define CAN_F10R1_FB26_Msk     (0x1U << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R1_FB27_Pos     (27U)\n#define CAN_F10R1_FB27_Msk     (0x1U << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R1_FB28_Pos     (28U)\n#define CAN_F10R1_FB28_Msk     (0x1U << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R1_FB29_Pos     (29U)\n#define CAN_F10R1_FB29_Msk     (0x1U << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R1_FB30_Pos     (30U)\n#define CAN_F10R1_FB30_Msk     (0x1U << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R1_FB31_Pos     (31U)\n#define CAN_F10R1_FB31_Msk     (0x1U << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R1 register  ******************/\n#define CAN_F11R1_FB0_Pos      (0U)\n#define CAN_F11R1_FB0_Msk      (0x1U << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R1_FB1_Pos      (1U)\n#define CAN_F11R1_FB1_Msk      (0x1U << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R1_FB2_Pos      (2U)\n#define CAN_F11R1_FB2_Msk      (0x1U << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R1_FB3_Pos      (3U)\n#define CAN_F11R1_FB3_Msk      (0x1U << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R1_FB4_Pos      (4U)\n#define CAN_F11R1_FB4_Msk      (0x1U << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R1_FB5_Pos      (5U)\n#define CAN_F11R1_FB5_Msk      (0x1U << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R1_FB6_Pos      (6U)\n#define CAN_F11R1_FB6_Msk      (0x1U << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R1_FB7_Pos      (7U)\n#define CAN_F11R1_FB7_Msk      (0x1U << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R1_FB8_Pos      (8U)\n#define CAN_F11R1_FB8_Msk      (0x1U << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R1_FB9_Pos      (9U)\n#define CAN_F11R1_FB9_Msk      (0x1U << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R1_FB10_Pos     (10U)\n#define CAN_F11R1_FB10_Msk     (0x1U << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R1_FB11_Pos     (11U)\n#define CAN_F11R1_FB11_Msk     (0x1U << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R1_FB12_Pos     (12U)\n#define CAN_F11R1_FB12_Msk     (0x1U << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R1_FB13_Pos     (13U)\n#define CAN_F11R1_FB13_Msk     (0x1U << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R1_FB14_Pos     (14U)\n#define CAN_F11R1_FB14_Msk     (0x1U << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R1_FB15_Pos     (15U)\n#define CAN_F11R1_FB15_Msk     (0x1U << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R1_FB16_Pos     (16U)\n#define CAN_F11R1_FB16_Msk     (0x1U << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R1_FB17_Pos     (17U)\n#define CAN_F11R1_FB17_Msk     (0x1U << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R1_FB18_Pos     (18U)\n#define CAN_F11R1_FB18_Msk     (0x1U << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R1_FB19_Pos     (19U)\n#define CAN_F11R1_FB19_Msk     (0x1U << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R1_FB20_Pos     (20U)\n#define CAN_F11R1_FB20_Msk     (0x1U << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R1_FB21_Pos     (21U)\n#define CAN_F11R1_FB21_Msk     (0x1U << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R1_FB22_Pos     (22U)\n#define CAN_F11R1_FB22_Msk     (0x1U << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R1_FB23_Pos     (23U)\n#define CAN_F11R1_FB23_Msk     (0x1U << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R1_FB24_Pos     (24U)\n#define CAN_F11R1_FB24_Msk     (0x1U << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R1_FB25_Pos     (25U)\n#define CAN_F11R1_FB25_Msk     (0x1U << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R1_FB26_Pos     (26U)\n#define CAN_F11R1_FB26_Msk     (0x1U << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R1_FB27_Pos     (27U)\n#define CAN_F11R1_FB27_Msk     (0x1U << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R1_FB28_Pos     (28U)\n#define CAN_F11R1_FB28_Msk     (0x1U << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R1_FB29_Pos     (29U)\n#define CAN_F11R1_FB29_Msk     (0x1U << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R1_FB30_Pos     (30U)\n#define CAN_F11R1_FB30_Msk     (0x1U << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R1_FB31_Pos     (31U)\n#define CAN_F11R1_FB31_Msk     (0x1U << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R1 register  ******************/\n#define CAN_F12R1_FB0_Pos      (0U)\n#define CAN_F12R1_FB0_Msk      (0x1U << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R1_FB1_Pos      (1U)\n#define CAN_F12R1_FB1_Msk      (0x1U << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R1_FB2_Pos      (2U)\n#define CAN_F12R1_FB2_Msk      (0x1U << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R1_FB3_Pos      (3U)\n#define CAN_F12R1_FB3_Msk      (0x1U << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R1_FB4_Pos      (4U)\n#define CAN_F12R1_FB4_Msk      (0x1U << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R1_FB5_Pos      (5U)\n#define CAN_F12R1_FB5_Msk      (0x1U << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R1_FB6_Pos      (6U)\n#define CAN_F12R1_FB6_Msk      (0x1U << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R1_FB7_Pos      (7U)\n#define CAN_F12R1_FB7_Msk      (0x1U << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R1_FB8_Pos      (8U)\n#define CAN_F12R1_FB8_Msk      (0x1U << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R1_FB9_Pos      (9U)\n#define CAN_F12R1_FB9_Msk      (0x1U << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R1_FB10_Pos     (10U)\n#define CAN_F12R1_FB10_Msk     (0x1U << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R1_FB11_Pos     (11U)\n#define CAN_F12R1_FB11_Msk     (0x1U << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R1_FB12_Pos     (12U)\n#define CAN_F12R1_FB12_Msk     (0x1U << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R1_FB13_Pos     (13U)\n#define CAN_F12R1_FB13_Msk     (0x1U << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R1_FB14_Pos     (14U)\n#define CAN_F12R1_FB14_Msk     (0x1U << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R1_FB15_Pos     (15U)\n#define CAN_F12R1_FB15_Msk     (0x1U << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R1_FB16_Pos     (16U)\n#define CAN_F12R1_FB16_Msk     (0x1U << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R1_FB17_Pos     (17U)\n#define CAN_F12R1_FB17_Msk     (0x1U << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R1_FB18_Pos     (18U)\n#define CAN_F12R1_FB18_Msk     (0x1U << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R1_FB19_Pos     (19U)\n#define CAN_F12R1_FB19_Msk     (0x1U << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R1_FB20_Pos     (20U)\n#define CAN_F12R1_FB20_Msk     (0x1U << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R1_FB21_Pos     (21U)\n#define CAN_F12R1_FB21_Msk     (0x1U << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R1_FB22_Pos     (22U)\n#define CAN_F12R1_FB22_Msk     (0x1U << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R1_FB23_Pos     (23U)\n#define CAN_F12R1_FB23_Msk     (0x1U << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R1_FB24_Pos     (24U)\n#define CAN_F12R1_FB24_Msk     (0x1U << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R1_FB25_Pos     (25U)\n#define CAN_F12R1_FB25_Msk     (0x1U << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R1_FB26_Pos     (26U)\n#define CAN_F12R1_FB26_Msk     (0x1U << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R1_FB27_Pos     (27U)\n#define CAN_F12R1_FB27_Msk     (0x1U << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R1_FB28_Pos     (28U)\n#define CAN_F12R1_FB28_Msk     (0x1U << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R1_FB29_Pos     (29U)\n#define CAN_F12R1_FB29_Msk     (0x1U << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R1_FB30_Pos     (30U)\n#define CAN_F12R1_FB30_Msk     (0x1U << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R1_FB31_Pos     (31U)\n#define CAN_F12R1_FB31_Msk     (0x1U << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R1 register  ******************/\n#define CAN_F13R1_FB0_Pos      (0U)\n#define CAN_F13R1_FB0_Msk      (0x1U << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R1_FB1_Pos      (1U)\n#define CAN_F13R1_FB1_Msk      (0x1U << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R1_FB2_Pos      (2U)\n#define CAN_F13R1_FB2_Msk      (0x1U << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R1_FB3_Pos      (3U)\n#define CAN_F13R1_FB3_Msk      (0x1U << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R1_FB4_Pos      (4U)\n#define CAN_F13R1_FB4_Msk      (0x1U << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R1_FB5_Pos      (5U)\n#define CAN_F13R1_FB5_Msk      (0x1U << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R1_FB6_Pos      (6U)\n#define CAN_F13R1_FB6_Msk      (0x1U << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R1_FB7_Pos      (7U)\n#define CAN_F13R1_FB7_Msk      (0x1U << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R1_FB8_Pos      (8U)\n#define CAN_F13R1_FB8_Msk      (0x1U << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R1_FB9_Pos      (9U)\n#define CAN_F13R1_FB9_Msk      (0x1U << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R1_FB10_Pos     (10U)\n#define CAN_F13R1_FB10_Msk     (0x1U << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R1_FB11_Pos     (11U)\n#define CAN_F13R1_FB11_Msk     (0x1U << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R1_FB12_Pos     (12U)\n#define CAN_F13R1_FB12_Msk     (0x1U << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R1_FB13_Pos     (13U)\n#define CAN_F13R1_FB13_Msk     (0x1U << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R1_FB14_Pos     (14U)\n#define CAN_F13R1_FB14_Msk     (0x1U << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R1_FB15_Pos     (15U)\n#define CAN_F13R1_FB15_Msk     (0x1U << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R1_FB16_Pos     (16U)\n#define CAN_F13R1_FB16_Msk     (0x1U << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R1_FB17_Pos     (17U)\n#define CAN_F13R1_FB17_Msk     (0x1U << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R1_FB18_Pos     (18U)\n#define CAN_F13R1_FB18_Msk     (0x1U << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R1_FB19_Pos     (19U)\n#define CAN_F13R1_FB19_Msk     (0x1U << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R1_FB20_Pos     (20U)\n#define CAN_F13R1_FB20_Msk     (0x1U << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R1_FB21_Pos     (21U)\n#define CAN_F13R1_FB21_Msk     (0x1U << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R1_FB22_Pos     (22U)\n#define CAN_F13R1_FB22_Msk     (0x1U << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R1_FB23_Pos     (23U)\n#define CAN_F13R1_FB23_Msk     (0x1U << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R1_FB24_Pos     (24U)\n#define CAN_F13R1_FB24_Msk     (0x1U << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R1_FB25_Pos     (25U)\n#define CAN_F13R1_FB25_Msk     (0x1U << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R1_FB26_Pos     (26U)\n#define CAN_F13R1_FB26_Msk     (0x1U << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R1_FB27_Pos     (27U)\n#define CAN_F13R1_FB27_Msk     (0x1U << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R1_FB28_Pos     (28U)\n#define CAN_F13R1_FB28_Msk     (0x1U << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R1_FB29_Pos     (29U)\n#define CAN_F13R1_FB29_Msk     (0x1U << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R1_FB30_Pos     (30U)\n#define CAN_F13R1_FB30_Msk     (0x1U << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R1_FB31_Pos     (31U)\n#define CAN_F13R1_FB31_Msk     (0x1U << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F0R2 register  *******************/\n#define CAN_F0R2_FB0_Pos       (0U)\n#define CAN_F0R2_FB0_Msk       (0x1U << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R2_FB1_Pos       (1U)\n#define CAN_F0R2_FB1_Msk       (0x1U << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R2_FB2_Pos       (2U)\n#define CAN_F0R2_FB2_Msk       (0x1U << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R2_FB3_Pos       (3U)\n#define CAN_F0R2_FB3_Msk       (0x1U << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R2_FB4_Pos       (4U)\n#define CAN_F0R2_FB4_Msk       (0x1U << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R2_FB5_Pos       (5U)\n#define CAN_F0R2_FB5_Msk       (0x1U << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R2_FB6_Pos       (6U)\n#define CAN_F0R2_FB6_Msk       (0x1U << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R2_FB7_Pos       (7U)\n#define CAN_F0R2_FB7_Msk       (0x1U << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R2_FB8_Pos       (8U)\n#define CAN_F0R2_FB8_Msk       (0x1U << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R2_FB9_Pos       (9U)\n#define CAN_F0R2_FB9_Msk       (0x1U << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R2_FB10_Pos      (10U)\n#define CAN_F0R2_FB10_Msk      (0x1U << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R2_FB11_Pos      (11U)\n#define CAN_F0R2_FB11_Msk      (0x1U << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R2_FB12_Pos      (12U)\n#define CAN_F0R2_FB12_Msk      (0x1U << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R2_FB13_Pos      (13U)\n#define CAN_F0R2_FB13_Msk      (0x1U << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R2_FB14_Pos      (14U)\n#define CAN_F0R2_FB14_Msk      (0x1U << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R2_FB15_Pos      (15U)\n#define CAN_F0R2_FB15_Msk      (0x1U << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R2_FB16_Pos      (16U)\n#define CAN_F0R2_FB16_Msk      (0x1U << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R2_FB17_Pos      (17U)\n#define CAN_F0R2_FB17_Msk      (0x1U << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R2_FB18_Pos      (18U)\n#define CAN_F0R2_FB18_Msk      (0x1U << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R2_FB19_Pos      (19U)\n#define CAN_F0R2_FB19_Msk      (0x1U << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R2_FB20_Pos      (20U)\n#define CAN_F0R2_FB20_Msk      (0x1U << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R2_FB21_Pos      (21U)\n#define CAN_F0R2_FB21_Msk      (0x1U << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R2_FB22_Pos      (22U)\n#define CAN_F0R2_FB22_Msk      (0x1U << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R2_FB23_Pos      (23U)\n#define CAN_F0R2_FB23_Msk      (0x1U << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R2_FB24_Pos      (24U)\n#define CAN_F0R2_FB24_Msk      (0x1U << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R2_FB25_Pos      (25U)\n#define CAN_F0R2_FB25_Msk      (0x1U << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R2_FB26_Pos      (26U)\n#define CAN_F0R2_FB26_Msk      (0x1U << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R2_FB27_Pos      (27U)\n#define CAN_F0R2_FB27_Msk      (0x1U << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R2_FB28_Pos      (28U)\n#define CAN_F0R2_FB28_Msk      (0x1U << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R2_FB29_Pos      (29U)\n#define CAN_F0R2_FB29_Msk      (0x1U << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R2_FB30_Pos      (30U)\n#define CAN_F0R2_FB30_Msk      (0x1U << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R2_FB31_Pos      (31U)\n#define CAN_F0R2_FB31_Msk      (0x1U << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R2 register  *******************/\n#define CAN_F1R2_FB0_Pos       (0U)\n#define CAN_F1R2_FB0_Msk       (0x1U << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R2_FB1_Pos       (1U)\n#define CAN_F1R2_FB1_Msk       (0x1U << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R2_FB2_Pos       (2U)\n#define CAN_F1R2_FB2_Msk       (0x1U << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R2_FB3_Pos       (3U)\n#define CAN_F1R2_FB3_Msk       (0x1U << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R2_FB4_Pos       (4U)\n#define CAN_F1R2_FB4_Msk       (0x1U << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R2_FB5_Pos       (5U)\n#define CAN_F1R2_FB5_Msk       (0x1U << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R2_FB6_Pos       (6U)\n#define CAN_F1R2_FB6_Msk       (0x1U << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R2_FB7_Pos       (7U)\n#define CAN_F1R2_FB7_Msk       (0x1U << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R2_FB8_Pos       (8U)\n#define CAN_F1R2_FB8_Msk       (0x1U << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R2_FB9_Pos       (9U)\n#define CAN_F1R2_FB9_Msk       (0x1U << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R2_FB10_Pos      (10U)\n#define CAN_F1R2_FB10_Msk      (0x1U << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R2_FB11_Pos      (11U)\n#define CAN_F1R2_FB11_Msk      (0x1U << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R2_FB12_Pos      (12U)\n#define CAN_F1R2_FB12_Msk      (0x1U << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R2_FB13_Pos      (13U)\n#define CAN_F1R2_FB13_Msk      (0x1U << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R2_FB14_Pos      (14U)\n#define CAN_F1R2_FB14_Msk      (0x1U << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R2_FB15_Pos      (15U)\n#define CAN_F1R2_FB15_Msk      (0x1U << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R2_FB16_Pos      (16U)\n#define CAN_F1R2_FB16_Msk      (0x1U << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R2_FB17_Pos      (17U)\n#define CAN_F1R2_FB17_Msk      (0x1U << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R2_FB18_Pos      (18U)\n#define CAN_F1R2_FB18_Msk      (0x1U << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R2_FB19_Pos      (19U)\n#define CAN_F1R2_FB19_Msk      (0x1U << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R2_FB20_Pos      (20U)\n#define CAN_F1R2_FB20_Msk      (0x1U << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R2_FB21_Pos      (21U)\n#define CAN_F1R2_FB21_Msk      (0x1U << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R2_FB22_Pos      (22U)\n#define CAN_F1R2_FB22_Msk      (0x1U << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R2_FB23_Pos      (23U)\n#define CAN_F1R2_FB23_Msk      (0x1U << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R2_FB24_Pos      (24U)\n#define CAN_F1R2_FB24_Msk      (0x1U << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R2_FB25_Pos      (25U)\n#define CAN_F1R2_FB25_Msk      (0x1U << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R2_FB26_Pos      (26U)\n#define CAN_F1R2_FB26_Msk      (0x1U << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R2_FB27_Pos      (27U)\n#define CAN_F1R2_FB27_Msk      (0x1U << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R2_FB28_Pos      (28U)\n#define CAN_F1R2_FB28_Msk      (0x1U << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R2_FB29_Pos      (29U)\n#define CAN_F1R2_FB29_Msk      (0x1U << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R2_FB30_Pos      (30U)\n#define CAN_F1R2_FB30_Msk      (0x1U << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R2_FB31_Pos      (31U)\n#define CAN_F1R2_FB31_Msk      (0x1U << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R2 register  *******************/\n#define CAN_F2R2_FB0_Pos       (0U)\n#define CAN_F2R2_FB0_Msk       (0x1U << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R2_FB1_Pos       (1U)\n#define CAN_F2R2_FB1_Msk       (0x1U << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R2_FB2_Pos       (2U)\n#define CAN_F2R2_FB2_Msk       (0x1U << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R2_FB3_Pos       (3U)\n#define CAN_F2R2_FB3_Msk       (0x1U << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R2_FB4_Pos       (4U)\n#define CAN_F2R2_FB4_Msk       (0x1U << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R2_FB5_Pos       (5U)\n#define CAN_F2R2_FB5_Msk       (0x1U << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R2_FB6_Pos       (6U)\n#define CAN_F2R2_FB6_Msk       (0x1U << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R2_FB7_Pos       (7U)\n#define CAN_F2R2_FB7_Msk       (0x1U << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R2_FB8_Pos       (8U)\n#define CAN_F2R2_FB8_Msk       (0x1U << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R2_FB9_Pos       (9U)\n#define CAN_F2R2_FB9_Msk       (0x1U << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R2_FB10_Pos      (10U)\n#define CAN_F2R2_FB10_Msk      (0x1U << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R2_FB11_Pos      (11U)\n#define CAN_F2R2_FB11_Msk      (0x1U << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R2_FB12_Pos      (12U)\n#define CAN_F2R2_FB12_Msk      (0x1U << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R2_FB13_Pos      (13U)\n#define CAN_F2R2_FB13_Msk      (0x1U << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R2_FB14_Pos      (14U)\n#define CAN_F2R2_FB14_Msk      (0x1U << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R2_FB15_Pos      (15U)\n#define CAN_F2R2_FB15_Msk      (0x1U << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R2_FB16_Pos      (16U)\n#define CAN_F2R2_FB16_Msk      (0x1U << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R2_FB17_Pos      (17U)\n#define CAN_F2R2_FB17_Msk      (0x1U << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R2_FB18_Pos      (18U)\n#define CAN_F2R2_FB18_Msk      (0x1U << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R2_FB19_Pos      (19U)\n#define CAN_F2R2_FB19_Msk      (0x1U << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R2_FB20_Pos      (20U)\n#define CAN_F2R2_FB20_Msk      (0x1U << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R2_FB21_Pos      (21U)\n#define CAN_F2R2_FB21_Msk      (0x1U << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R2_FB22_Pos      (22U)\n#define CAN_F2R2_FB22_Msk      (0x1U << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R2_FB23_Pos      (23U)\n#define CAN_F2R2_FB23_Msk      (0x1U << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R2_FB24_Pos      (24U)\n#define CAN_F2R2_FB24_Msk      (0x1U << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R2_FB25_Pos      (25U)\n#define CAN_F2R2_FB25_Msk      (0x1U << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R2_FB26_Pos      (26U)\n#define CAN_F2R2_FB26_Msk      (0x1U << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R2_FB27_Pos      (27U)\n#define CAN_F2R2_FB27_Msk      (0x1U << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R2_FB28_Pos      (28U)\n#define CAN_F2R2_FB28_Msk      (0x1U << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R2_FB29_Pos      (29U)\n#define CAN_F2R2_FB29_Msk      (0x1U << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R2_FB30_Pos      (30U)\n#define CAN_F2R2_FB30_Msk      (0x1U << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R2_FB31_Pos      (31U)\n#define CAN_F2R2_FB31_Msk      (0x1U << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R2 register  *******************/\n#define CAN_F3R2_FB0_Pos       (0U)\n#define CAN_F3R2_FB0_Msk       (0x1U << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R2_FB1_Pos       (1U)\n#define CAN_F3R2_FB1_Msk       (0x1U << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R2_FB2_Pos       (2U)\n#define CAN_F3R2_FB2_Msk       (0x1U << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R2_FB3_Pos       (3U)\n#define CAN_F3R2_FB3_Msk       (0x1U << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R2_FB4_Pos       (4U)\n#define CAN_F3R2_FB4_Msk       (0x1U << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R2_FB5_Pos       (5U)\n#define CAN_F3R2_FB5_Msk       (0x1U << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R2_FB6_Pos       (6U)\n#define CAN_F3R2_FB6_Msk       (0x1U << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R2_FB7_Pos       (7U)\n#define CAN_F3R2_FB7_Msk       (0x1U << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R2_FB8_Pos       (8U)\n#define CAN_F3R2_FB8_Msk       (0x1U << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R2_FB9_Pos       (9U)\n#define CAN_F3R2_FB9_Msk       (0x1U << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R2_FB10_Pos      (10U)\n#define CAN_F3R2_FB10_Msk      (0x1U << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R2_FB11_Pos      (11U)\n#define CAN_F3R2_FB11_Msk      (0x1U << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R2_FB12_Pos      (12U)\n#define CAN_F3R2_FB12_Msk      (0x1U << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R2_FB13_Pos      (13U)\n#define CAN_F3R2_FB13_Msk      (0x1U << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R2_FB14_Pos      (14U)\n#define CAN_F3R2_FB14_Msk      (0x1U << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R2_FB15_Pos      (15U)\n#define CAN_F3R2_FB15_Msk      (0x1U << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R2_FB16_Pos      (16U)\n#define CAN_F3R2_FB16_Msk      (0x1U << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R2_FB17_Pos      (17U)\n#define CAN_F3R2_FB17_Msk      (0x1U << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R2_FB18_Pos      (18U)\n#define CAN_F3R2_FB18_Msk      (0x1U << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R2_FB19_Pos      (19U)\n#define CAN_F3R2_FB19_Msk      (0x1U << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R2_FB20_Pos      (20U)\n#define CAN_F3R2_FB20_Msk      (0x1U << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R2_FB21_Pos      (21U)\n#define CAN_F3R2_FB21_Msk      (0x1U << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R2_FB22_Pos      (22U)\n#define CAN_F3R2_FB22_Msk      (0x1U << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R2_FB23_Pos      (23U)\n#define CAN_F3R2_FB23_Msk      (0x1U << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R2_FB24_Pos      (24U)\n#define CAN_F3R2_FB24_Msk      (0x1U << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R2_FB25_Pos      (25U)\n#define CAN_F3R2_FB25_Msk      (0x1U << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R2_FB26_Pos      (26U)\n#define CAN_F3R2_FB26_Msk      (0x1U << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R2_FB27_Pos      (27U)\n#define CAN_F3R2_FB27_Msk      (0x1U << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R2_FB28_Pos      (28U)\n#define CAN_F3R2_FB28_Msk      (0x1U << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R2_FB29_Pos      (29U)\n#define CAN_F3R2_FB29_Msk      (0x1U << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R2_FB30_Pos      (30U)\n#define CAN_F3R2_FB30_Msk      (0x1U << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R2_FB31_Pos      (31U)\n#define CAN_F3R2_FB31_Msk      (0x1U << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R2 register  *******************/\n#define CAN_F4R2_FB0_Pos       (0U)\n#define CAN_F4R2_FB0_Msk       (0x1U << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R2_FB1_Pos       (1U)\n#define CAN_F4R2_FB1_Msk       (0x1U << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R2_FB2_Pos       (2U)\n#define CAN_F4R2_FB2_Msk       (0x1U << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R2_FB3_Pos       (3U)\n#define CAN_F4R2_FB3_Msk       (0x1U << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R2_FB4_Pos       (4U)\n#define CAN_F4R2_FB4_Msk       (0x1U << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R2_FB5_Pos       (5U)\n#define CAN_F4R2_FB5_Msk       (0x1U << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R2_FB6_Pos       (6U)\n#define CAN_F4R2_FB6_Msk       (0x1U << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R2_FB7_Pos       (7U)\n#define CAN_F4R2_FB7_Msk       (0x1U << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R2_FB8_Pos       (8U)\n#define CAN_F4R2_FB8_Msk       (0x1U << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R2_FB9_Pos       (9U)\n#define CAN_F4R2_FB9_Msk       (0x1U << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R2_FB10_Pos      (10U)\n#define CAN_F4R2_FB10_Msk      (0x1U << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R2_FB11_Pos      (11U)\n#define CAN_F4R2_FB11_Msk      (0x1U << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R2_FB12_Pos      (12U)\n#define CAN_F4R2_FB12_Msk      (0x1U << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R2_FB13_Pos      (13U)\n#define CAN_F4R2_FB13_Msk      (0x1U << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R2_FB14_Pos      (14U)\n#define CAN_F4R2_FB14_Msk      (0x1U << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R2_FB15_Pos      (15U)\n#define CAN_F4R2_FB15_Msk      (0x1U << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R2_FB16_Pos      (16U)\n#define CAN_F4R2_FB16_Msk      (0x1U << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R2_FB17_Pos      (17U)\n#define CAN_F4R2_FB17_Msk      (0x1U << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R2_FB18_Pos      (18U)\n#define CAN_F4R2_FB18_Msk      (0x1U << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R2_FB19_Pos      (19U)\n#define CAN_F4R2_FB19_Msk      (0x1U << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R2_FB20_Pos      (20U)\n#define CAN_F4R2_FB20_Msk      (0x1U << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R2_FB21_Pos      (21U)\n#define CAN_F4R2_FB21_Msk      (0x1U << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R2_FB22_Pos      (22U)\n#define CAN_F4R2_FB22_Msk      (0x1U << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R2_FB23_Pos      (23U)\n#define CAN_F4R2_FB23_Msk      (0x1U << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R2_FB24_Pos      (24U)\n#define CAN_F4R2_FB24_Msk      (0x1U << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R2_FB25_Pos      (25U)\n#define CAN_F4R2_FB25_Msk      (0x1U << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R2_FB26_Pos      (26U)\n#define CAN_F4R2_FB26_Msk      (0x1U << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R2_FB27_Pos      (27U)\n#define CAN_F4R2_FB27_Msk      (0x1U << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R2_FB28_Pos      (28U)\n#define CAN_F4R2_FB28_Msk      (0x1U << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R2_FB29_Pos      (29U)\n#define CAN_F4R2_FB29_Msk      (0x1U << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R2_FB30_Pos      (30U)\n#define CAN_F4R2_FB30_Msk      (0x1U << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R2_FB31_Pos      (31U)\n#define CAN_F4R2_FB31_Msk      (0x1U << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R2 register  *******************/\n#define CAN_F5R2_FB0_Pos       (0U)\n#define CAN_F5R2_FB0_Msk       (0x1U << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R2_FB1_Pos       (1U)\n#define CAN_F5R2_FB1_Msk       (0x1U << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R2_FB2_Pos       (2U)\n#define CAN_F5R2_FB2_Msk       (0x1U << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R2_FB3_Pos       (3U)\n#define CAN_F5R2_FB3_Msk       (0x1U << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R2_FB4_Pos       (4U)\n#define CAN_F5R2_FB4_Msk       (0x1U << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R2_FB5_Pos       (5U)\n#define CAN_F5R2_FB5_Msk       (0x1U << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R2_FB6_Pos       (6U)\n#define CAN_F5R2_FB6_Msk       (0x1U << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R2_FB7_Pos       (7U)\n#define CAN_F5R2_FB7_Msk       (0x1U << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R2_FB8_Pos       (8U)\n#define CAN_F5R2_FB8_Msk       (0x1U << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R2_FB9_Pos       (9U)\n#define CAN_F5R2_FB9_Msk       (0x1U << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R2_FB10_Pos      (10U)\n#define CAN_F5R2_FB10_Msk      (0x1U << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R2_FB11_Pos      (11U)\n#define CAN_F5R2_FB11_Msk      (0x1U << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R2_FB12_Pos      (12U)\n#define CAN_F5R2_FB12_Msk      (0x1U << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R2_FB13_Pos      (13U)\n#define CAN_F5R2_FB13_Msk      (0x1U << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R2_FB14_Pos      (14U)\n#define CAN_F5R2_FB14_Msk      (0x1U << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R2_FB15_Pos      (15U)\n#define CAN_F5R2_FB15_Msk      (0x1U << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R2_FB16_Pos      (16U)\n#define CAN_F5R2_FB16_Msk      (0x1U << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R2_FB17_Pos      (17U)\n#define CAN_F5R2_FB17_Msk      (0x1U << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R2_FB18_Pos      (18U)\n#define CAN_F5R2_FB18_Msk      (0x1U << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R2_FB19_Pos      (19U)\n#define CAN_F5R2_FB19_Msk      (0x1U << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R2_FB20_Pos      (20U)\n#define CAN_F5R2_FB20_Msk      (0x1U << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R2_FB21_Pos      (21U)\n#define CAN_F5R2_FB21_Msk      (0x1U << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R2_FB22_Pos      (22U)\n#define CAN_F5R2_FB22_Msk      (0x1U << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R2_FB23_Pos      (23U)\n#define CAN_F5R2_FB23_Msk      (0x1U << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R2_FB24_Pos      (24U)\n#define CAN_F5R2_FB24_Msk      (0x1U << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R2_FB25_Pos      (25U)\n#define CAN_F5R2_FB25_Msk      (0x1U << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R2_FB26_Pos      (26U)\n#define CAN_F5R2_FB26_Msk      (0x1U << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R2_FB27_Pos      (27U)\n#define CAN_F5R2_FB27_Msk      (0x1U << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R2_FB28_Pos      (28U)\n#define CAN_F5R2_FB28_Msk      (0x1U << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R2_FB29_Pos      (29U)\n#define CAN_F5R2_FB29_Msk      (0x1U << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R2_FB30_Pos      (30U)\n#define CAN_F5R2_FB30_Msk      (0x1U << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R2_FB31_Pos      (31U)\n#define CAN_F5R2_FB31_Msk      (0x1U << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R2 register  *******************/\n#define CAN_F6R2_FB0_Pos       (0U)\n#define CAN_F6R2_FB0_Msk       (0x1U << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R2_FB1_Pos       (1U)\n#define CAN_F6R2_FB1_Msk       (0x1U << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R2_FB2_Pos       (2U)\n#define CAN_F6R2_FB2_Msk       (0x1U << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R2_FB3_Pos       (3U)\n#define CAN_F6R2_FB3_Msk       (0x1U << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R2_FB4_Pos       (4U)\n#define CAN_F6R2_FB4_Msk       (0x1U << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R2_FB5_Pos       (5U)\n#define CAN_F6R2_FB5_Msk       (0x1U << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R2_FB6_Pos       (6U)\n#define CAN_F6R2_FB6_Msk       (0x1U << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R2_FB7_Pos       (7U)\n#define CAN_F6R2_FB7_Msk       (0x1U << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R2_FB8_Pos       (8U)\n#define CAN_F6R2_FB8_Msk       (0x1U << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R2_FB9_Pos       (9U)\n#define CAN_F6R2_FB9_Msk       (0x1U << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R2_FB10_Pos      (10U)\n#define CAN_F6R2_FB10_Msk      (0x1U << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R2_FB11_Pos      (11U)\n#define CAN_F6R2_FB11_Msk      (0x1U << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R2_FB12_Pos      (12U)\n#define CAN_F6R2_FB12_Msk      (0x1U << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R2_FB13_Pos      (13U)\n#define CAN_F6R2_FB13_Msk      (0x1U << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R2_FB14_Pos      (14U)\n#define CAN_F6R2_FB14_Msk      (0x1U << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R2_FB15_Pos      (15U)\n#define CAN_F6R2_FB15_Msk      (0x1U << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R2_FB16_Pos      (16U)\n#define CAN_F6R2_FB16_Msk      (0x1U << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R2_FB17_Pos      (17U)\n#define CAN_F6R2_FB17_Msk      (0x1U << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R2_FB18_Pos      (18U)\n#define CAN_F6R2_FB18_Msk      (0x1U << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R2_FB19_Pos      (19U)\n#define CAN_F6R2_FB19_Msk      (0x1U << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R2_FB20_Pos      (20U)\n#define CAN_F6R2_FB20_Msk      (0x1U << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R2_FB21_Pos      (21U)\n#define CAN_F6R2_FB21_Msk      (0x1U << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R2_FB22_Pos      (22U)\n#define CAN_F6R2_FB22_Msk      (0x1U << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R2_FB23_Pos      (23U)\n#define CAN_F6R2_FB23_Msk      (0x1U << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R2_FB24_Pos      (24U)\n#define CAN_F6R2_FB24_Msk      (0x1U << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R2_FB25_Pos      (25U)\n#define CAN_F6R2_FB25_Msk      (0x1U << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R2_FB26_Pos      (26U)\n#define CAN_F6R2_FB26_Msk      (0x1U << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R2_FB27_Pos      (27U)\n#define CAN_F6R2_FB27_Msk      (0x1U << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R2_FB28_Pos      (28U)\n#define CAN_F6R2_FB28_Msk      (0x1U << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R2_FB29_Pos      (29U)\n#define CAN_F6R2_FB29_Msk      (0x1U << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R2_FB30_Pos      (30U)\n#define CAN_F6R2_FB30_Msk      (0x1U << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R2_FB31_Pos      (31U)\n#define CAN_F6R2_FB31_Msk      (0x1U << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R2 register  *******************/\n#define CAN_F7R2_FB0_Pos       (0U)\n#define CAN_F7R2_FB0_Msk       (0x1U << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R2_FB1_Pos       (1U)\n#define CAN_F7R2_FB1_Msk       (0x1U << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R2_FB2_Pos       (2U)\n#define CAN_F7R2_FB2_Msk       (0x1U << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R2_FB3_Pos       (3U)\n#define CAN_F7R2_FB3_Msk       (0x1U << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R2_FB4_Pos       (4U)\n#define CAN_F7R2_FB4_Msk       (0x1U << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R2_FB5_Pos       (5U)\n#define CAN_F7R2_FB5_Msk       (0x1U << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R2_FB6_Pos       (6U)\n#define CAN_F7R2_FB6_Msk       (0x1U << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R2_FB7_Pos       (7U)\n#define CAN_F7R2_FB7_Msk       (0x1U << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R2_FB8_Pos       (8U)\n#define CAN_F7R2_FB8_Msk       (0x1U << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R2_FB9_Pos       (9U)\n#define CAN_F7R2_FB9_Msk       (0x1U << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R2_FB10_Pos      (10U)\n#define CAN_F7R2_FB10_Msk      (0x1U << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R2_FB11_Pos      (11U)\n#define CAN_F7R2_FB11_Msk      (0x1U << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R2_FB12_Pos      (12U)\n#define CAN_F7R2_FB12_Msk      (0x1U << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R2_FB13_Pos      (13U)\n#define CAN_F7R2_FB13_Msk      (0x1U << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R2_FB14_Pos      (14U)\n#define CAN_F7R2_FB14_Msk      (0x1U << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R2_FB15_Pos      (15U)\n#define CAN_F7R2_FB15_Msk      (0x1U << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R2_FB16_Pos      (16U)\n#define CAN_F7R2_FB16_Msk      (0x1U << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R2_FB17_Pos      (17U)\n#define CAN_F7R2_FB17_Msk      (0x1U << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R2_FB18_Pos      (18U)\n#define CAN_F7R2_FB18_Msk      (0x1U << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R2_FB19_Pos      (19U)\n#define CAN_F7R2_FB19_Msk      (0x1U << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R2_FB20_Pos      (20U)\n#define CAN_F7R2_FB20_Msk      (0x1U << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R2_FB21_Pos      (21U)\n#define CAN_F7R2_FB21_Msk      (0x1U << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R2_FB22_Pos      (22U)\n#define CAN_F7R2_FB22_Msk      (0x1U << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R2_FB23_Pos      (23U)\n#define CAN_F7R2_FB23_Msk      (0x1U << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R2_FB24_Pos      (24U)\n#define CAN_F7R2_FB24_Msk      (0x1U << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R2_FB25_Pos      (25U)\n#define CAN_F7R2_FB25_Msk      (0x1U << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R2_FB26_Pos      (26U)\n#define CAN_F7R2_FB26_Msk      (0x1U << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R2_FB27_Pos      (27U)\n#define CAN_F7R2_FB27_Msk      (0x1U << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R2_FB28_Pos      (28U)\n#define CAN_F7R2_FB28_Msk      (0x1U << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R2_FB29_Pos      (29U)\n#define CAN_F7R2_FB29_Msk      (0x1U << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R2_FB30_Pos      (30U)\n#define CAN_F7R2_FB30_Msk      (0x1U << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R2_FB31_Pos      (31U)\n#define CAN_F7R2_FB31_Msk      (0x1U << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R2 register  *******************/\n#define CAN_F8R2_FB0_Pos       (0U)\n#define CAN_F8R2_FB0_Msk       (0x1U << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R2_FB1_Pos       (1U)\n#define CAN_F8R2_FB1_Msk       (0x1U << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R2_FB2_Pos       (2U)\n#define CAN_F8R2_FB2_Msk       (0x1U << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R2_FB3_Pos       (3U)\n#define CAN_F8R2_FB3_Msk       (0x1U << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R2_FB4_Pos       (4U)\n#define CAN_F8R2_FB4_Msk       (0x1U << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R2_FB5_Pos       (5U)\n#define CAN_F8R2_FB5_Msk       (0x1U << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R2_FB6_Pos       (6U)\n#define CAN_F8R2_FB6_Msk       (0x1U << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R2_FB7_Pos       (7U)\n#define CAN_F8R2_FB7_Msk       (0x1U << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R2_FB8_Pos       (8U)\n#define CAN_F8R2_FB8_Msk       (0x1U << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R2_FB9_Pos       (9U)\n#define CAN_F8R2_FB9_Msk       (0x1U << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R2_FB10_Pos      (10U)\n#define CAN_F8R2_FB10_Msk      (0x1U << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R2_FB11_Pos      (11U)\n#define CAN_F8R2_FB11_Msk      (0x1U << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R2_FB12_Pos      (12U)\n#define CAN_F8R2_FB12_Msk      (0x1U << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R2_FB13_Pos      (13U)\n#define CAN_F8R2_FB13_Msk      (0x1U << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R2_FB14_Pos      (14U)\n#define CAN_F8R2_FB14_Msk      (0x1U << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R2_FB15_Pos      (15U)\n#define CAN_F8R2_FB15_Msk      (0x1U << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R2_FB16_Pos      (16U)\n#define CAN_F8R2_FB16_Msk      (0x1U << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R2_FB17_Pos      (17U)\n#define CAN_F8R2_FB17_Msk      (0x1U << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R2_FB18_Pos      (18U)\n#define CAN_F8R2_FB18_Msk      (0x1U << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R2_FB19_Pos      (19U)\n#define CAN_F8R2_FB19_Msk      (0x1U << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R2_FB20_Pos      (20U)\n#define CAN_F8R2_FB20_Msk      (0x1U << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R2_FB21_Pos      (21U)\n#define CAN_F8R2_FB21_Msk      (0x1U << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R2_FB22_Pos      (22U)\n#define CAN_F8R2_FB22_Msk      (0x1U << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R2_FB23_Pos      (23U)\n#define CAN_F8R2_FB23_Msk      (0x1U << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R2_FB24_Pos      (24U)\n#define CAN_F8R2_FB24_Msk      (0x1U << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R2_FB25_Pos      (25U)\n#define CAN_F8R2_FB25_Msk      (0x1U << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R2_FB26_Pos      (26U)\n#define CAN_F8R2_FB26_Msk      (0x1U << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R2_FB27_Pos      (27U)\n#define CAN_F8R2_FB27_Msk      (0x1U << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R2_FB28_Pos      (28U)\n#define CAN_F8R2_FB28_Msk      (0x1U << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R2_FB29_Pos      (29U)\n#define CAN_F8R2_FB29_Msk      (0x1U << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R2_FB30_Pos      (30U)\n#define CAN_F8R2_FB30_Msk      (0x1U << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R2_FB31_Pos      (31U)\n#define CAN_F8R2_FB31_Msk      (0x1U << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R2 register  *******************/\n#define CAN_F9R2_FB0_Pos       (0U)\n#define CAN_F9R2_FB0_Msk       (0x1U << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R2_FB1_Pos       (1U)\n#define CAN_F9R2_FB1_Msk       (0x1U << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R2_FB2_Pos       (2U)\n#define CAN_F9R2_FB2_Msk       (0x1U << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R2_FB3_Pos       (3U)\n#define CAN_F9R2_FB3_Msk       (0x1U << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R2_FB4_Pos       (4U)\n#define CAN_F9R2_FB4_Msk       (0x1U << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R2_FB5_Pos       (5U)\n#define CAN_F9R2_FB5_Msk       (0x1U << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R2_FB6_Pos       (6U)\n#define CAN_F9R2_FB6_Msk       (0x1U << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R2_FB7_Pos       (7U)\n#define CAN_F9R2_FB7_Msk       (0x1U << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R2_FB8_Pos       (8U)\n#define CAN_F9R2_FB8_Msk       (0x1U << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R2_FB9_Pos       (9U)\n#define CAN_F9R2_FB9_Msk       (0x1U << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R2_FB10_Pos      (10U)\n#define CAN_F9R2_FB10_Msk      (0x1U << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R2_FB11_Pos      (11U)\n#define CAN_F9R2_FB11_Msk      (0x1U << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R2_FB12_Pos      (12U)\n#define CAN_F9R2_FB12_Msk      (0x1U << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R2_FB13_Pos      (13U)\n#define CAN_F9R2_FB13_Msk      (0x1U << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R2_FB14_Pos      (14U)\n#define CAN_F9R2_FB14_Msk      (0x1U << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R2_FB15_Pos      (15U)\n#define CAN_F9R2_FB15_Msk      (0x1U << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R2_FB16_Pos      (16U)\n#define CAN_F9R2_FB16_Msk      (0x1U << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R2_FB17_Pos      (17U)\n#define CAN_F9R2_FB17_Msk      (0x1U << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R2_FB18_Pos      (18U)\n#define CAN_F9R2_FB18_Msk      (0x1U << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R2_FB19_Pos      (19U)\n#define CAN_F9R2_FB19_Msk      (0x1U << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R2_FB20_Pos      (20U)\n#define CAN_F9R2_FB20_Msk      (0x1U << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R2_FB21_Pos      (21U)\n#define CAN_F9R2_FB21_Msk      (0x1U << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R2_FB22_Pos      (22U)\n#define CAN_F9R2_FB22_Msk      (0x1U << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R2_FB23_Pos      (23U)\n#define CAN_F9R2_FB23_Msk      (0x1U << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R2_FB24_Pos      (24U)\n#define CAN_F9R2_FB24_Msk      (0x1U << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R2_FB25_Pos      (25U)\n#define CAN_F9R2_FB25_Msk      (0x1U << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R2_FB26_Pos      (26U)\n#define CAN_F9R2_FB26_Msk      (0x1U << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R2_FB27_Pos      (27U)\n#define CAN_F9R2_FB27_Msk      (0x1U << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R2_FB28_Pos      (28U)\n#define CAN_F9R2_FB28_Msk      (0x1U << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R2_FB29_Pos      (29U)\n#define CAN_F9R2_FB29_Msk      (0x1U << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R2_FB30_Pos      (30U)\n#define CAN_F9R2_FB30_Msk      (0x1U << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R2_FB31_Pos      (31U)\n#define CAN_F9R2_FB31_Msk      (0x1U << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R2 register  ******************/\n#define CAN_F10R2_FB0_Pos      (0U)\n#define CAN_F10R2_FB0_Msk      (0x1U << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R2_FB1_Pos      (1U)\n#define CAN_F10R2_FB1_Msk      (0x1U << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R2_FB2_Pos      (2U)\n#define CAN_F10R2_FB2_Msk      (0x1U << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R2_FB3_Pos      (3U)\n#define CAN_F10R2_FB3_Msk      (0x1U << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R2_FB4_Pos      (4U)\n#define CAN_F10R2_FB4_Msk      (0x1U << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R2_FB5_Pos      (5U)\n#define CAN_F10R2_FB5_Msk      (0x1U << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R2_FB6_Pos      (6U)\n#define CAN_F10R2_FB6_Msk      (0x1U << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R2_FB7_Pos      (7U)\n#define CAN_F10R2_FB7_Msk      (0x1U << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R2_FB8_Pos      (8U)\n#define CAN_F10R2_FB8_Msk      (0x1U << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R2_FB9_Pos      (9U)\n#define CAN_F10R2_FB9_Msk      (0x1U << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R2_FB10_Pos     (10U)\n#define CAN_F10R2_FB10_Msk     (0x1U << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R2_FB11_Pos     (11U)\n#define CAN_F10R2_FB11_Msk     (0x1U << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R2_FB12_Pos     (12U)\n#define CAN_F10R2_FB12_Msk     (0x1U << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R2_FB13_Pos     (13U)\n#define CAN_F10R2_FB13_Msk     (0x1U << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R2_FB14_Pos     (14U)\n#define CAN_F10R2_FB14_Msk     (0x1U << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R2_FB15_Pos     (15U)\n#define CAN_F10R2_FB15_Msk     (0x1U << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R2_FB16_Pos     (16U)\n#define CAN_F10R2_FB16_Msk     (0x1U << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R2_FB17_Pos     (17U)\n#define CAN_F10R2_FB17_Msk     (0x1U << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R2_FB18_Pos     (18U)\n#define CAN_F10R2_FB18_Msk     (0x1U << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R2_FB19_Pos     (19U)\n#define CAN_F10R2_FB19_Msk     (0x1U << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R2_FB20_Pos     (20U)\n#define CAN_F10R2_FB20_Msk     (0x1U << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R2_FB21_Pos     (21U)\n#define CAN_F10R2_FB21_Msk     (0x1U << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R2_FB22_Pos     (22U)\n#define CAN_F10R2_FB22_Msk     (0x1U << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R2_FB23_Pos     (23U)\n#define CAN_F10R2_FB23_Msk     (0x1U << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R2_FB24_Pos     (24U)\n#define CAN_F10R2_FB24_Msk     (0x1U << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R2_FB25_Pos     (25U)\n#define CAN_F10R2_FB25_Msk     (0x1U << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R2_FB26_Pos     (26U)\n#define CAN_F10R2_FB26_Msk     (0x1U << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R2_FB27_Pos     (27U)\n#define CAN_F10R2_FB27_Msk     (0x1U << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R2_FB28_Pos     (28U)\n#define CAN_F10R2_FB28_Msk     (0x1U << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R2_FB29_Pos     (29U)\n#define CAN_F10R2_FB29_Msk     (0x1U << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R2_FB30_Pos     (30U)\n#define CAN_F10R2_FB30_Msk     (0x1U << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R2_FB31_Pos     (31U)\n#define CAN_F10R2_FB31_Msk     (0x1U << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R2 register  ******************/\n#define CAN_F11R2_FB0_Pos      (0U)\n#define CAN_F11R2_FB0_Msk      (0x1U << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R2_FB1_Pos      (1U)\n#define CAN_F11R2_FB1_Msk      (0x1U << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R2_FB2_Pos      (2U)\n#define CAN_F11R2_FB2_Msk      (0x1U << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R2_FB3_Pos      (3U)\n#define CAN_F11R2_FB3_Msk      (0x1U << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R2_FB4_Pos      (4U)\n#define CAN_F11R2_FB4_Msk      (0x1U << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R2_FB5_Pos      (5U)\n#define CAN_F11R2_FB5_Msk      (0x1U << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R2_FB6_Pos      (6U)\n#define CAN_F11R2_FB6_Msk      (0x1U << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R2_FB7_Pos      (7U)\n#define CAN_F11R2_FB7_Msk      (0x1U << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R2_FB8_Pos      (8U)\n#define CAN_F11R2_FB8_Msk      (0x1U << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R2_FB9_Pos      (9U)\n#define CAN_F11R2_FB9_Msk      (0x1U << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R2_FB10_Pos     (10U)\n#define CAN_F11R2_FB10_Msk     (0x1U << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R2_FB11_Pos     (11U)\n#define CAN_F11R2_FB11_Msk     (0x1U << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R2_FB12_Pos     (12U)\n#define CAN_F11R2_FB12_Msk     (0x1U << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R2_FB13_Pos     (13U)\n#define CAN_F11R2_FB13_Msk     (0x1U << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R2_FB14_Pos     (14U)\n#define CAN_F11R2_FB14_Msk     (0x1U << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R2_FB15_Pos     (15U)\n#define CAN_F11R2_FB15_Msk     (0x1U << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R2_FB16_Pos     (16U)\n#define CAN_F11R2_FB16_Msk     (0x1U << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R2_FB17_Pos     (17U)\n#define CAN_F11R2_FB17_Msk     (0x1U << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R2_FB18_Pos     (18U)\n#define CAN_F11R2_FB18_Msk     (0x1U << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R2_FB19_Pos     (19U)\n#define CAN_F11R2_FB19_Msk     (0x1U << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R2_FB20_Pos     (20U)\n#define CAN_F11R2_FB20_Msk     (0x1U << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R2_FB21_Pos     (21U)\n#define CAN_F11R2_FB21_Msk     (0x1U << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R2_FB22_Pos     (22U)\n#define CAN_F11R2_FB22_Msk     (0x1U << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R2_FB23_Pos     (23U)\n#define CAN_F11R2_FB23_Msk     (0x1U << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R2_FB24_Pos     (24U)\n#define CAN_F11R2_FB24_Msk     (0x1U << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R2_FB25_Pos     (25U)\n#define CAN_F11R2_FB25_Msk     (0x1U << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R2_FB26_Pos     (26U)\n#define CAN_F11R2_FB26_Msk     (0x1U << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R2_FB27_Pos     (27U)\n#define CAN_F11R2_FB27_Msk     (0x1U << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R2_FB28_Pos     (28U)\n#define CAN_F11R2_FB28_Msk     (0x1U << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R2_FB29_Pos     (29U)\n#define CAN_F11R2_FB29_Msk     (0x1U << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R2_FB30_Pos     (30U)\n#define CAN_F11R2_FB30_Msk     (0x1U << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R2_FB31_Pos     (31U)\n#define CAN_F11R2_FB31_Msk     (0x1U << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R2 register  ******************/\n#define CAN_F12R2_FB0_Pos      (0U)\n#define CAN_F12R2_FB0_Msk      (0x1U << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R2_FB1_Pos      (1U)\n#define CAN_F12R2_FB1_Msk      (0x1U << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R2_FB2_Pos      (2U)\n#define CAN_F12R2_FB2_Msk      (0x1U << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R2_FB3_Pos      (3U)\n#define CAN_F12R2_FB3_Msk      (0x1U << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R2_FB4_Pos      (4U)\n#define CAN_F12R2_FB4_Msk      (0x1U << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R2_FB5_Pos      (5U)\n#define CAN_F12R2_FB5_Msk      (0x1U << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R2_FB6_Pos      (6U)\n#define CAN_F12R2_FB6_Msk      (0x1U << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R2_FB7_Pos      (7U)\n#define CAN_F12R2_FB7_Msk      (0x1U << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R2_FB8_Pos      (8U)\n#define CAN_F12R2_FB8_Msk      (0x1U << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R2_FB9_Pos      (9U)\n#define CAN_F12R2_FB9_Msk      (0x1U << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R2_FB10_Pos     (10U)\n#define CAN_F12R2_FB10_Msk     (0x1U << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R2_FB11_Pos     (11U)\n#define CAN_F12R2_FB11_Msk     (0x1U << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R2_FB12_Pos     (12U)\n#define CAN_F12R2_FB12_Msk     (0x1U << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R2_FB13_Pos     (13U)\n#define CAN_F12R2_FB13_Msk     (0x1U << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R2_FB14_Pos     (14U)\n#define CAN_F12R2_FB14_Msk     (0x1U << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R2_FB15_Pos     (15U)\n#define CAN_F12R2_FB15_Msk     (0x1U << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R2_FB16_Pos     (16U)\n#define CAN_F12R2_FB16_Msk     (0x1U << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R2_FB17_Pos     (17U)\n#define CAN_F12R2_FB17_Msk     (0x1U << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R2_FB18_Pos     (18U)\n#define CAN_F12R2_FB18_Msk     (0x1U << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R2_FB19_Pos     (19U)\n#define CAN_F12R2_FB19_Msk     (0x1U << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R2_FB20_Pos     (20U)\n#define CAN_F12R2_FB20_Msk     (0x1U << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R2_FB21_Pos     (21U)\n#define CAN_F12R2_FB21_Msk     (0x1U << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R2_FB22_Pos     (22U)\n#define CAN_F12R2_FB22_Msk     (0x1U << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R2_FB23_Pos     (23U)\n#define CAN_F12R2_FB23_Msk     (0x1U << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R2_FB24_Pos     (24U)\n#define CAN_F12R2_FB24_Msk     (0x1U << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R2_FB25_Pos     (25U)\n#define CAN_F12R2_FB25_Msk     (0x1U << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R2_FB26_Pos     (26U)\n#define CAN_F12R2_FB26_Msk     (0x1U << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R2_FB27_Pos     (27U)\n#define CAN_F12R2_FB27_Msk     (0x1U << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R2_FB28_Pos     (28U)\n#define CAN_F12R2_FB28_Msk     (0x1U << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R2_FB29_Pos     (29U)\n#define CAN_F12R2_FB29_Msk     (0x1U << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R2_FB30_Pos     (30U)\n#define CAN_F12R2_FB30_Msk     (0x1U << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R2_FB31_Pos     (31U)\n#define CAN_F12R2_FB31_Msk     (0x1U << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R2 register  ******************/\n#define CAN_F13R2_FB0_Pos      (0U)\n#define CAN_F13R2_FB0_Msk      (0x1U << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R2_FB1_Pos      (1U)\n#define CAN_F13R2_FB1_Msk      (0x1U << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R2_FB2_Pos      (2U)\n#define CAN_F13R2_FB2_Msk      (0x1U << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R2_FB3_Pos      (3U)\n#define CAN_F13R2_FB3_Msk      (0x1U << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R2_FB4_Pos      (4U)\n#define CAN_F13R2_FB4_Msk      (0x1U << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R2_FB5_Pos      (5U)\n#define CAN_F13R2_FB5_Msk      (0x1U << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R2_FB6_Pos      (6U)\n#define CAN_F13R2_FB6_Msk      (0x1U << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R2_FB7_Pos      (7U)\n#define CAN_F13R2_FB7_Msk      (0x1U << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R2_FB8_Pos      (8U)\n#define CAN_F13R2_FB8_Msk      (0x1U << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R2_FB9_Pos      (9U)\n#define CAN_F13R2_FB9_Msk      (0x1U << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R2_FB10_Pos     (10U)\n#define CAN_F13R2_FB10_Msk     (0x1U << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R2_FB11_Pos     (11U)\n#define CAN_F13R2_FB11_Msk     (0x1U << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R2_FB12_Pos     (12U)\n#define CAN_F13R2_FB12_Msk     (0x1U << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R2_FB13_Pos     (13U)\n#define CAN_F13R2_FB13_Msk     (0x1U << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R2_FB14_Pos     (14U)\n#define CAN_F13R2_FB14_Msk     (0x1U << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R2_FB15_Pos     (15U)\n#define CAN_F13R2_FB15_Msk     (0x1U << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R2_FB16_Pos     (16U)\n#define CAN_F13R2_FB16_Msk     (0x1U << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R2_FB17_Pos     (17U)\n#define CAN_F13R2_FB17_Msk     (0x1U << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R2_FB18_Pos     (18U)\n#define CAN_F13R2_FB18_Msk     (0x1U << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R2_FB19_Pos     (19U)\n#define CAN_F13R2_FB19_Msk     (0x1U << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R2_FB20_Pos     (20U)\n#define CAN_F13R2_FB20_Msk     (0x1U << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R2_FB21_Pos     (21U)\n#define CAN_F13R2_FB21_Msk     (0x1U << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R2_FB22_Pos     (22U)\n#define CAN_F13R2_FB22_Msk     (0x1U << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R2_FB23_Pos     (23U)\n#define CAN_F13R2_FB23_Msk     (0x1U << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R2_FB24_Pos     (24U)\n#define CAN_F13R2_FB24_Msk     (0x1U << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R2_FB25_Pos     (25U)\n#define CAN_F13R2_FB25_Msk     (0x1U << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R2_FB26_Pos     (26U)\n#define CAN_F13R2_FB26_Msk     (0x1U << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R2_FB27_Pos     (27U)\n#define CAN_F13R2_FB27_Msk     (0x1U << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R2_FB28_Pos     (28U)\n#define CAN_F13R2_FB28_Msk     (0x1U << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R2_FB29_Pos     (29U)\n#define CAN_F13R2_FB29_Msk     (0x1U << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R2_FB30_Pos     (30U)\n#define CAN_F13R2_FB30_Msk     (0x1U << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R2_FB31_Pos     (31U)\n#define CAN_F13R2_FB31_Msk     (0x1U << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          CRC calculation unit                              */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for CRC_DR register  *********************/\n#define CRC_DR_DR_Pos       (0U)\n#define CRC_DR_DR_Msk       (0xFFFFFFFFU << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */\n#define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */\n\n\n/*******************  Bit definition for CRC_IDR register  ********************/\n#define CRC_IDR_IDR_Pos     (0U)\n#define CRC_IDR_IDR_Msk     (0xFFU << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */\n#define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */\n\n\n/********************  Bit definition for CRC_CR register  ********************/\n#define CRC_CR_RESET_Pos    (0U)\n#define CRC_CR_RESET_Msk    (0x1U << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */\n#define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Digital to Analog Converter                           */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define DAC_CHANNEL2_SUPPORT                                    /*!< DAC feature available only on specific devices: availability of DAC channel 2 */\n/********************  Bit definition for DAC_CR register  ********************/\n#define DAC_CR_EN1_Pos              (0U)\n#define DAC_CR_EN1_Msk              (0x1U << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */\n#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */\n#define DAC_CR_BOFF1_Pos            (1U)\n#define DAC_CR_BOFF1_Msk            (0x1U << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */\n#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable */\n#define DAC_CR_TEN1_Pos             (2U)\n#define DAC_CR_TEN1_Msk             (0x1U << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */\n#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */\n\n#define DAC_CR_TSEL1_Pos            (3U)\n#define DAC_CR_TSEL1_Msk            (0x7U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */\n#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\n#define DAC_CR_TSEL1_0              (0x1U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */\n#define DAC_CR_TSEL1_1              (0x2U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */\n#define DAC_CR_TSEL1_2              (0x4U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */\n\n#define DAC_CR_WAVE1_Pos            (6U)\n#define DAC_CR_WAVE1_Msk            (0x3U << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */\n#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE1_0              (0x1U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */\n#define DAC_CR_WAVE1_1              (0x2U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */\n\n#define DAC_CR_MAMP1_Pos            (8U)\n#define DAC_CR_MAMP1_Msk            (0xFU << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */\n#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\n#define DAC_CR_MAMP1_0              (0x1U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */\n#define DAC_CR_MAMP1_1              (0x2U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */\n#define DAC_CR_MAMP1_2              (0x4U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */\n#define DAC_CR_MAMP1_3              (0x8U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */\n\n#define DAC_CR_DMAEN1_Pos           (12U)\n#define DAC_CR_DMAEN1_Msk           (0x1U << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */\n#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */\n#define DAC_CR_DMAUDRIE1_Pos        (13U)\n#define DAC_CR_DMAUDRIE1_Msk        (0x1U << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */\n#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable*/\n#define DAC_CR_EN2_Pos              (16U)\n#define DAC_CR_EN2_Msk              (0x1U << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */\n#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */\n#define DAC_CR_BOFF2_Pos            (17U)\n#define DAC_CR_BOFF2_Msk            (0x1U << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */\n#define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable */\n#define DAC_CR_TEN2_Pos             (18U)\n#define DAC_CR_TEN2_Msk             (0x1U << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */\n#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */\n\n#define DAC_CR_TSEL2_Pos            (19U)\n#define DAC_CR_TSEL2_Msk            (0x7U << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */\n#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\n#define DAC_CR_TSEL2_0              (0x1U << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */\n#define DAC_CR_TSEL2_1              (0x2U << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */\n#define DAC_CR_TSEL2_2              (0x4U << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */\n\n#define DAC_CR_WAVE2_Pos            (22U)\n#define DAC_CR_WAVE2_Msk            (0x3U << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */\n#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE2_0              (0x1U << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */\n#define DAC_CR_WAVE2_1              (0x2U << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */\n\n#define DAC_CR_MAMP2_Pos            (24U)\n#define DAC_CR_MAMP2_Msk            (0xFU << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */\n#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\n#define DAC_CR_MAMP2_0              (0x1U << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */\n#define DAC_CR_MAMP2_1              (0x2U << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */\n#define DAC_CR_MAMP2_2              (0x4U << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */\n#define DAC_CR_MAMP2_3              (0x8U << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */\n\n#define DAC_CR_DMAEN2_Pos           (28U)\n#define DAC_CR_DMAEN2_Msk           (0x1U << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */\n#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */\n#define DAC_CR_DMAUDRIE2_Pos        (29U)\n#define DAC_CR_DMAUDRIE2_Msk        (0x1U << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */\n#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable*/\n\n/*****************  Bit definition for DAC_SWTRIGR register  ******************/\n#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)\n#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */\n#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */\n#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)\n#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1U << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */\n#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */\n\n/*****************  Bit definition for DAC_DHR12R1 register  ******************/\n#define DAC_DHR12R1_DACC1DHR_Pos    (0U)\n#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L1 register  ******************/\n#define DAC_DHR12L1_DACC1DHR_Pos    (4U)\n#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R1 register  ******************/\n#define DAC_DHR8R1_DACC1DHR_Pos     (0U)\n#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12R2 register  ******************/\n#define DAC_DHR12R2_DACC2DHR_Pos    (0U)\n#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L2 register  ******************/\n#define DAC_DHR12L2_DACC2DHR_Pos    (4U)\n#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R2 register  ******************/\n#define DAC_DHR8R2_DACC2DHR_Pos     (0U)\n#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFU << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12RD register  ******************/\n#define DAC_DHR12RD_DACC1DHR_Pos    (0U)\n#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\n#define DAC_DHR12RD_DACC2DHR_Pos    (16U)\n#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */\n#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12LD register  ******************/\n#define DAC_DHR12LD_DACC1DHR_Pos    (4U)\n#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\n#define DAC_DHR12LD_DACC2DHR_Pos    (20U)\n#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */\n#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8RD register  ******************/\n#define DAC_DHR8RD_DACC1DHR_Pos     (0U)\n#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFU << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\n#define DAC_DHR8RD_DACC2DHR_Pos     (8U)\n#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFU << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */\n#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\n\n/*******************  Bit definition for DAC_DOR1 register  *******************/\n#define DAC_DOR1_DACC1DOR_Pos       (0U)\n#define DAC_DOR1_DACC1DOR_Msk       (0xFFFU << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */\n#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */\n\n/*******************  Bit definition for DAC_DOR2 register  *******************/\n#define DAC_DOR2_DACC2DOR_Pos       (0U)\n#define DAC_DOR2_DACC2DOR_Msk       (0xFFFU << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */\n#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */\n\n/********************  Bit definition for DAC_SR register  ********************/\n#define DAC_SR_DMAUDR1_Pos          (13U)\n#define DAC_SR_DMAUDR1_Msk          (0x1U << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */\n#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */\n#define DAC_SR_DMAUDR2_Pos          (29U)\n#define DAC_SR_DMAUDR2_Msk          (0x1U << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */\n#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    DCMI                                    */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DCMI_CR register  ******************/\n#define DCMI_CR_CAPTURE_Pos        (0U)\n#define DCMI_CR_CAPTURE_Msk        (0x1U << DCMI_CR_CAPTURE_Pos)               /*!< 0x00000001 */\n#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk\n#define DCMI_CR_CM_Pos             (1U)\n#define DCMI_CR_CM_Msk             (0x1U << DCMI_CR_CM_Pos)                    /*!< 0x00000002 */\n#define DCMI_CR_CM                 DCMI_CR_CM_Msk\n#define DCMI_CR_CROP_Pos           (2U)\n#define DCMI_CR_CROP_Msk           (0x1U << DCMI_CR_CROP_Pos)                  /*!< 0x00000004 */\n#define DCMI_CR_CROP               DCMI_CR_CROP_Msk\n#define DCMI_CR_JPEG_Pos           (3U)\n#define DCMI_CR_JPEG_Msk           (0x1U << DCMI_CR_JPEG_Pos)                  /*!< 0x00000008 */\n#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk\n#define DCMI_CR_ESS_Pos            (4U)\n#define DCMI_CR_ESS_Msk            (0x1U << DCMI_CR_ESS_Pos)                   /*!< 0x00000010 */\n#define DCMI_CR_ESS                DCMI_CR_ESS_Msk\n#define DCMI_CR_PCKPOL_Pos         (5U)\n#define DCMI_CR_PCKPOL_Msk         (0x1U << DCMI_CR_PCKPOL_Pos)                /*!< 0x00000020 */\n#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk\n#define DCMI_CR_HSPOL_Pos          (6U)\n#define DCMI_CR_HSPOL_Msk          (0x1U << DCMI_CR_HSPOL_Pos)                 /*!< 0x00000040 */\n#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk\n#define DCMI_CR_VSPOL_Pos          (7U)\n#define DCMI_CR_VSPOL_Msk          (0x1U << DCMI_CR_VSPOL_Pos)                 /*!< 0x00000080 */\n#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk\n#define DCMI_CR_FCRC_0             0x00000100U\n#define DCMI_CR_FCRC_1             0x00000200U\n#define DCMI_CR_EDM_0              0x00000400U\n#define DCMI_CR_EDM_1              0x00000800U\n#define DCMI_CR_OUTEN_Pos          (13U)\n#define DCMI_CR_OUTEN_Msk          (0x1U << DCMI_CR_OUTEN_Pos)                 /*!< 0x00002000 */\n#define DCMI_CR_OUTEN              DCMI_CR_OUTEN_Msk\n#define DCMI_CR_ENABLE_Pos         (14U)\n#define DCMI_CR_ENABLE_Msk         (0x1U << DCMI_CR_ENABLE_Pos)                /*!< 0x00004000 */\n#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk\n#define DCMI_CR_BSM_0              0x00010000U\n#define DCMI_CR_BSM_1              0x00020000U\n#define DCMI_CR_OEBS_Pos           (18U)\n#define DCMI_CR_OEBS_Msk           (0x1U << DCMI_CR_OEBS_Pos)                  /*!< 0x00040000 */\n#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk\n#define DCMI_CR_LSM_Pos            (19U)\n#define DCMI_CR_LSM_Msk            (0x1U << DCMI_CR_LSM_Pos)                   /*!< 0x00080000 */\n#define DCMI_CR_LSM                DCMI_CR_LSM_Msk\n#define DCMI_CR_OELS_Pos           (20U)\n#define DCMI_CR_OELS_Msk           (0x1U << DCMI_CR_OELS_Pos)                  /*!< 0x00100000 */\n#define DCMI_CR_OELS               DCMI_CR_OELS_Msk\n\n/********************  Bits definition for DCMI_SR register  ******************/\n#define DCMI_SR_HSYNC_Pos          (0U)\n#define DCMI_SR_HSYNC_Msk          (0x1U << DCMI_SR_HSYNC_Pos)                 /*!< 0x00000001 */\n#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk\n#define DCMI_SR_VSYNC_Pos          (1U)\n#define DCMI_SR_VSYNC_Msk          (0x1U << DCMI_SR_VSYNC_Pos)                 /*!< 0x00000002 */\n#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk\n#define DCMI_SR_FNE_Pos            (2U)\n#define DCMI_SR_FNE_Msk            (0x1U << DCMI_SR_FNE_Pos)                   /*!< 0x00000004 */\n#define DCMI_SR_FNE                DCMI_SR_FNE_Msk\n\n/********************  Bits definition for DCMI_RIS register  *****************/\n#define DCMI_RIS_FRAME_RIS_Pos     (0U)\n#define DCMI_RIS_FRAME_RIS_Msk     (0x1U << DCMI_RIS_FRAME_RIS_Pos)            /*!< 0x00000001 */\n#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk\n#define DCMI_RIS_OVR_RIS_Pos       (1U)\n#define DCMI_RIS_OVR_RIS_Msk       (0x1U << DCMI_RIS_OVR_RIS_Pos)              /*!< 0x00000002 */\n#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk\n#define DCMI_RIS_ERR_RIS_Pos       (2U)\n#define DCMI_RIS_ERR_RIS_Msk       (0x1U << DCMI_RIS_ERR_RIS_Pos)              /*!< 0x00000004 */\n#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk\n#define DCMI_RIS_VSYNC_RIS_Pos     (3U)\n#define DCMI_RIS_VSYNC_RIS_Msk     (0x1U << DCMI_RIS_VSYNC_RIS_Pos)            /*!< 0x00000008 */\n#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk\n#define DCMI_RIS_LINE_RIS_Pos      (4U)\n#define DCMI_RIS_LINE_RIS_Msk      (0x1U << DCMI_RIS_LINE_RIS_Pos)             /*!< 0x00000010 */\n#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk\n/* Legacy defines */\n#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS\n#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS\n#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS\n#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS\n#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS\n#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS\n\n/********************  Bits definition for DCMI_IER register  *****************/\n#define DCMI_IER_FRAME_IE_Pos      (0U)\n#define DCMI_IER_FRAME_IE_Msk      (0x1U << DCMI_IER_FRAME_IE_Pos)             /*!< 0x00000001 */\n#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk\n#define DCMI_IER_OVR_IE_Pos        (1U)\n#define DCMI_IER_OVR_IE_Msk        (0x1U << DCMI_IER_OVR_IE_Pos)               /*!< 0x00000002 */\n#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk\n#define DCMI_IER_ERR_IE_Pos        (2U)\n#define DCMI_IER_ERR_IE_Msk        (0x1U << DCMI_IER_ERR_IE_Pos)               /*!< 0x00000004 */\n#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk\n#define DCMI_IER_VSYNC_IE_Pos      (3U)\n#define DCMI_IER_VSYNC_IE_Msk      (0x1U << DCMI_IER_VSYNC_IE_Pos)             /*!< 0x00000008 */\n#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk\n#define DCMI_IER_LINE_IE_Pos       (4U)\n#define DCMI_IER_LINE_IE_Msk       (0x1U << DCMI_IER_LINE_IE_Pos)              /*!< 0x00000010 */\n#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk\n/* Legacy defines */\n#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE\n\n/********************  Bits definition for DCMI_MIS register  *****************/\n#define DCMI_MIS_FRAME_MIS_Pos     (0U)\n#define DCMI_MIS_FRAME_MIS_Msk     (0x1U << DCMI_MIS_FRAME_MIS_Pos)            /*!< 0x00000001 */\n#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk\n#define DCMI_MIS_OVR_MIS_Pos       (1U)\n#define DCMI_MIS_OVR_MIS_Msk       (0x1U << DCMI_MIS_OVR_MIS_Pos)              /*!< 0x00000002 */\n#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk\n#define DCMI_MIS_ERR_MIS_Pos       (2U)\n#define DCMI_MIS_ERR_MIS_Msk       (0x1U << DCMI_MIS_ERR_MIS_Pos)              /*!< 0x00000004 */\n#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk\n#define DCMI_MIS_VSYNC_MIS_Pos     (3U)\n#define DCMI_MIS_VSYNC_MIS_Msk     (0x1U << DCMI_MIS_VSYNC_MIS_Pos)            /*!< 0x00000008 */\n#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk\n#define DCMI_MIS_LINE_MIS_Pos      (4U)\n#define DCMI_MIS_LINE_MIS_Msk      (0x1U << DCMI_MIS_LINE_MIS_Pos)             /*!< 0x00000010 */\n#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk\n\n/* Legacy defines */\n#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS\n#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS\n#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS\n#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS\n#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS\n\n/********************  Bits definition for DCMI_ICR register  *****************/\n#define DCMI_ICR_FRAME_ISC_Pos     (0U)\n#define DCMI_ICR_FRAME_ISC_Msk     (0x1U << DCMI_ICR_FRAME_ISC_Pos)            /*!< 0x00000001 */\n#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk\n#define DCMI_ICR_OVR_ISC_Pos       (1U)\n#define DCMI_ICR_OVR_ISC_Msk       (0x1U << DCMI_ICR_OVR_ISC_Pos)              /*!< 0x00000002 */\n#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk\n#define DCMI_ICR_ERR_ISC_Pos       (2U)\n#define DCMI_ICR_ERR_ISC_Msk       (0x1U << DCMI_ICR_ERR_ISC_Pos)              /*!< 0x00000004 */\n#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk\n#define DCMI_ICR_VSYNC_ISC_Pos     (3U)\n#define DCMI_ICR_VSYNC_ISC_Msk     (0x1U << DCMI_ICR_VSYNC_ISC_Pos)            /*!< 0x00000008 */\n#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk\n#define DCMI_ICR_LINE_ISC_Pos      (4U)\n#define DCMI_ICR_LINE_ISC_Msk      (0x1U << DCMI_ICR_LINE_ISC_Pos)             /*!< 0x00000010 */\n#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk\n\n/* Legacy defines */\n#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC\n\n/********************  Bits definition for DCMI_ESCR register  ******************/\n#define DCMI_ESCR_FSC_Pos          (0U)\n#define DCMI_ESCR_FSC_Msk          (0xFFU << DCMI_ESCR_FSC_Pos)                /*!< 0x000000FF */\n#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk\n#define DCMI_ESCR_LSC_Pos          (8U)\n#define DCMI_ESCR_LSC_Msk          (0xFFU << DCMI_ESCR_LSC_Pos)                /*!< 0x0000FF00 */\n#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk\n#define DCMI_ESCR_LEC_Pos          (16U)\n#define DCMI_ESCR_LEC_Msk          (0xFFU << DCMI_ESCR_LEC_Pos)                /*!< 0x00FF0000 */\n#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk\n#define DCMI_ESCR_FEC_Pos          (24U)\n#define DCMI_ESCR_FEC_Msk          (0xFFU << DCMI_ESCR_FEC_Pos)                /*!< 0xFF000000 */\n#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk\n\n/********************  Bits definition for DCMI_ESUR register  ******************/\n#define DCMI_ESUR_FSU_Pos          (0U)\n#define DCMI_ESUR_FSU_Msk          (0xFFU << DCMI_ESUR_FSU_Pos)                /*!< 0x000000FF */\n#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk\n#define DCMI_ESUR_LSU_Pos          (8U)\n#define DCMI_ESUR_LSU_Msk          (0xFFU << DCMI_ESUR_LSU_Pos)                /*!< 0x0000FF00 */\n#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk\n#define DCMI_ESUR_LEU_Pos          (16U)\n#define DCMI_ESUR_LEU_Msk          (0xFFU << DCMI_ESUR_LEU_Pos)                /*!< 0x00FF0000 */\n#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk\n#define DCMI_ESUR_FEU_Pos          (24U)\n#define DCMI_ESUR_FEU_Msk          (0xFFU << DCMI_ESUR_FEU_Pos)                /*!< 0xFF000000 */\n#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk\n\n/********************  Bits definition for DCMI_CWSTRT register  ******************/\n#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)\n#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos)        /*!< 0x00003FFF */\n#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk\n#define DCMI_CWSTRT_VST_Pos        (16U)\n#define DCMI_CWSTRT_VST_Msk        (0x1FFFU << DCMI_CWSTRT_VST_Pos)            /*!< 0x1FFF0000 */\n#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk\n\n/********************  Bits definition for DCMI_CWSIZE register  ******************/\n#define DCMI_CWSIZE_CAPCNT_Pos     (0U)\n#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos)         /*!< 0x00003FFF */\n#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk\n#define DCMI_CWSIZE_VLINE_Pos      (16U)\n#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFU << DCMI_CWSIZE_VLINE_Pos)          /*!< 0x3FFF0000 */\n#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk\n\n/********************  Bits definition for DCMI_DR register  *********************/\n#define DCMI_DR_BYTE0_Pos          (0U)\n#define DCMI_DR_BYTE0_Msk          (0xFFU << DCMI_DR_BYTE0_Pos)                /*!< 0x000000FF */\n#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk\n#define DCMI_DR_BYTE1_Pos          (8U)\n#define DCMI_DR_BYTE1_Msk          (0xFFU << DCMI_DR_BYTE1_Pos)                /*!< 0x0000FF00 */\n#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk\n#define DCMI_DR_BYTE2_Pos          (16U)\n#define DCMI_DR_BYTE2_Msk          (0xFFU << DCMI_DR_BYTE2_Pos)                /*!< 0x00FF0000 */\n#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk\n#define DCMI_DR_BYTE3_Pos          (24U)\n#define DCMI_DR_BYTE3_Msk          (0xFFU << DCMI_DR_BYTE3_Pos)                /*!< 0xFF000000 */\n#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                             DMA Controller                                 */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DMA_SxCR register  *****************/\n#define DMA_SxCR_CHSEL_Pos       (25U)\n#define DMA_SxCR_CHSEL_Msk       (0x7U << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */\n#define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk\n#define DMA_SxCR_CHSEL_0         0x02000000U\n#define DMA_SxCR_CHSEL_1         0x04000000U\n#define DMA_SxCR_CHSEL_2         0x08000000U\n#define DMA_SxCR_MBURST_Pos      (23U)\n#define DMA_SxCR_MBURST_Msk      (0x3U << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */\n#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk\n#define DMA_SxCR_MBURST_0        (0x1U << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */\n#define DMA_SxCR_MBURST_1        (0x2U << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */\n#define DMA_SxCR_PBURST_Pos      (21U)\n#define DMA_SxCR_PBURST_Msk      (0x3U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */\n#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk\n#define DMA_SxCR_PBURST_0        (0x1U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */\n#define DMA_SxCR_PBURST_1        (0x2U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */\n#define DMA_SxCR_CT_Pos          (19U)\n#define DMA_SxCR_CT_Msk          (0x1U << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */\n#define DMA_SxCR_CT              DMA_SxCR_CT_Msk\n#define DMA_SxCR_DBM_Pos         (18U)\n#define DMA_SxCR_DBM_Msk         (0x1U << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */\n#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk\n#define DMA_SxCR_PL_Pos          (16U)\n#define DMA_SxCR_PL_Msk          (0x3U << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */\n#define DMA_SxCR_PL              DMA_SxCR_PL_Msk\n#define DMA_SxCR_PL_0            (0x1U << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */\n#define DMA_SxCR_PL_1            (0x2U << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */\n#define DMA_SxCR_PINCOS_Pos      (15U)\n#define DMA_SxCR_PINCOS_Msk      (0x1U << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */\n#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk\n#define DMA_SxCR_MSIZE_Pos       (13U)\n#define DMA_SxCR_MSIZE_Msk       (0x3U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */\n#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk\n#define DMA_SxCR_MSIZE_0         (0x1U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */\n#define DMA_SxCR_MSIZE_1         (0x2U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */\n#define DMA_SxCR_PSIZE_Pos       (11U)\n#define DMA_SxCR_PSIZE_Msk       (0x3U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */\n#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk\n#define DMA_SxCR_PSIZE_0         (0x1U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */\n#define DMA_SxCR_PSIZE_1         (0x2U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */\n#define DMA_SxCR_MINC_Pos        (10U)\n#define DMA_SxCR_MINC_Msk        (0x1U << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */\n#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk\n#define DMA_SxCR_PINC_Pos        (9U)\n#define DMA_SxCR_PINC_Msk        (0x1U << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */\n#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk\n#define DMA_SxCR_CIRC_Pos        (8U)\n#define DMA_SxCR_CIRC_Msk        (0x1U << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */\n#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk\n#define DMA_SxCR_DIR_Pos         (6U)\n#define DMA_SxCR_DIR_Msk         (0x3U << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */\n#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk\n#define DMA_SxCR_DIR_0           (0x1U << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */\n#define DMA_SxCR_DIR_1           (0x2U << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */\n#define DMA_SxCR_PFCTRL_Pos      (5U)\n#define DMA_SxCR_PFCTRL_Msk      (0x1U << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */\n#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk\n#define DMA_SxCR_TCIE_Pos        (4U)\n#define DMA_SxCR_TCIE_Msk        (0x1U << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */\n#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk\n#define DMA_SxCR_HTIE_Pos        (3U)\n#define DMA_SxCR_HTIE_Msk        (0x1U << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */\n#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk\n#define DMA_SxCR_TEIE_Pos        (2U)\n#define DMA_SxCR_TEIE_Msk        (0x1U << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */\n#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk\n#define DMA_SxCR_DMEIE_Pos       (1U)\n#define DMA_SxCR_DMEIE_Msk       (0x1U << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */\n#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk\n#define DMA_SxCR_EN_Pos          (0U)\n#define DMA_SxCR_EN_Msk          (0x1U << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */\n#define DMA_SxCR_EN              DMA_SxCR_EN_Msk\n\n/* Legacy defines */\n#define DMA_SxCR_ACK_Pos         (20U)\n#define DMA_SxCR_ACK_Msk         (0x1U << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */\n#define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk\n\n/********************  Bits definition for DMA_SxCNDTR register  **************/\n#define DMA_SxNDT_Pos            (0U)\n#define DMA_SxNDT_Msk            (0xFFFFU << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */\n#define DMA_SxNDT                DMA_SxNDT_Msk\n#define DMA_SxNDT_0              (0x0001U << DMA_SxNDT_Pos)                    /*!< 0x00000001 */\n#define DMA_SxNDT_1              (0x0002U << DMA_SxNDT_Pos)                    /*!< 0x00000002 */\n#define DMA_SxNDT_2              (0x0004U << DMA_SxNDT_Pos)                    /*!< 0x00000004 */\n#define DMA_SxNDT_3              (0x0008U << DMA_SxNDT_Pos)                    /*!< 0x00000008 */\n#define DMA_SxNDT_4              (0x0010U << DMA_SxNDT_Pos)                    /*!< 0x00000010 */\n#define DMA_SxNDT_5              (0x0020U << DMA_SxNDT_Pos)                    /*!< 0x00000020 */\n#define DMA_SxNDT_6              (0x0040U << DMA_SxNDT_Pos)                    /*!< 0x00000040 */\n#define DMA_SxNDT_7              (0x0080U << DMA_SxNDT_Pos)                    /*!< 0x00000080 */\n#define DMA_SxNDT_8              (0x0100U << DMA_SxNDT_Pos)                    /*!< 0x00000100 */\n#define DMA_SxNDT_9              (0x0200U << DMA_SxNDT_Pos)                    /*!< 0x00000200 */\n#define DMA_SxNDT_10             (0x0400U << DMA_SxNDT_Pos)                    /*!< 0x00000400 */\n#define DMA_SxNDT_11             (0x0800U << DMA_SxNDT_Pos)                    /*!< 0x00000800 */\n#define DMA_SxNDT_12             (0x1000U << DMA_SxNDT_Pos)                    /*!< 0x00001000 */\n#define DMA_SxNDT_13             (0x2000U << DMA_SxNDT_Pos)                    /*!< 0x00002000 */\n#define DMA_SxNDT_14             (0x4000U << DMA_SxNDT_Pos)                    /*!< 0x00004000 */\n#define DMA_SxNDT_15             (0x8000U << DMA_SxNDT_Pos)                    /*!< 0x00008000 */\n\n/********************  Bits definition for DMA_SxFCR register  ****************/\n#define DMA_SxFCR_FEIE_Pos       (7U)\n#define DMA_SxFCR_FEIE_Msk       (0x1U << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */\n#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk\n#define DMA_SxFCR_FS_Pos         (3U)\n#define DMA_SxFCR_FS_Msk         (0x7U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */\n#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk\n#define DMA_SxFCR_FS_0           (0x1U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */\n#define DMA_SxFCR_FS_1           (0x2U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */\n#define DMA_SxFCR_FS_2           (0x4U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */\n#define DMA_SxFCR_DMDIS_Pos      (2U)\n#define DMA_SxFCR_DMDIS_Msk      (0x1U << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */\n#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk\n#define DMA_SxFCR_FTH_Pos        (0U)\n#define DMA_SxFCR_FTH_Msk        (0x3U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */\n#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk\n#define DMA_SxFCR_FTH_0          (0x1U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */\n#define DMA_SxFCR_FTH_1          (0x2U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */\n\n/********************  Bits definition for DMA_LISR register  *****************/\n#define DMA_LISR_TCIF3_Pos       (27U)\n#define DMA_LISR_TCIF3_Msk       (0x1U << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */\n#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk\n#define DMA_LISR_HTIF3_Pos       (26U)\n#define DMA_LISR_HTIF3_Msk       (0x1U << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */\n#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk\n#define DMA_LISR_TEIF3_Pos       (25U)\n#define DMA_LISR_TEIF3_Msk       (0x1U << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */\n#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk\n#define DMA_LISR_DMEIF3_Pos      (24U)\n#define DMA_LISR_DMEIF3_Msk      (0x1U << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */\n#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk\n#define DMA_LISR_FEIF3_Pos       (22U)\n#define DMA_LISR_FEIF3_Msk       (0x1U << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */\n#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk\n#define DMA_LISR_TCIF2_Pos       (21U)\n#define DMA_LISR_TCIF2_Msk       (0x1U << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */\n#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk\n#define DMA_LISR_HTIF2_Pos       (20U)\n#define DMA_LISR_HTIF2_Msk       (0x1U << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */\n#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk\n#define DMA_LISR_TEIF2_Pos       (19U)\n#define DMA_LISR_TEIF2_Msk       (0x1U << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */\n#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk\n#define DMA_LISR_DMEIF2_Pos      (18U)\n#define DMA_LISR_DMEIF2_Msk      (0x1U << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */\n#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk\n#define DMA_LISR_FEIF2_Pos       (16U)\n#define DMA_LISR_FEIF2_Msk       (0x1U << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */\n#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk\n#define DMA_LISR_TCIF1_Pos       (11U)\n#define DMA_LISR_TCIF1_Msk       (0x1U << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */\n#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk\n#define DMA_LISR_HTIF1_Pos       (10U)\n#define DMA_LISR_HTIF1_Msk       (0x1U << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */\n#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk\n#define DMA_LISR_TEIF1_Pos       (9U)\n#define DMA_LISR_TEIF1_Msk       (0x1U << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */\n#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk\n#define DMA_LISR_DMEIF1_Pos      (8U)\n#define DMA_LISR_DMEIF1_Msk      (0x1U << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */\n#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk\n#define DMA_LISR_FEIF1_Pos       (6U)\n#define DMA_LISR_FEIF1_Msk       (0x1U << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */\n#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk\n#define DMA_LISR_TCIF0_Pos       (5U)\n#define DMA_LISR_TCIF0_Msk       (0x1U << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */\n#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk\n#define DMA_LISR_HTIF0_Pos       (4U)\n#define DMA_LISR_HTIF0_Msk       (0x1U << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */\n#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk\n#define DMA_LISR_TEIF0_Pos       (3U)\n#define DMA_LISR_TEIF0_Msk       (0x1U << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */\n#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk\n#define DMA_LISR_DMEIF0_Pos      (2U)\n#define DMA_LISR_DMEIF0_Msk      (0x1U << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */\n#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk\n#define DMA_LISR_FEIF0_Pos       (0U)\n#define DMA_LISR_FEIF0_Msk       (0x1U << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */\n#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk\n\n/********************  Bits definition for DMA_HISR register  *****************/\n#define DMA_HISR_TCIF7_Pos       (27U)\n#define DMA_HISR_TCIF7_Msk       (0x1U << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */\n#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk\n#define DMA_HISR_HTIF7_Pos       (26U)\n#define DMA_HISR_HTIF7_Msk       (0x1U << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */\n#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk\n#define DMA_HISR_TEIF7_Pos       (25U)\n#define DMA_HISR_TEIF7_Msk       (0x1U << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */\n#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk\n#define DMA_HISR_DMEIF7_Pos      (24U)\n#define DMA_HISR_DMEIF7_Msk      (0x1U << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */\n#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk\n#define DMA_HISR_FEIF7_Pos       (22U)\n#define DMA_HISR_FEIF7_Msk       (0x1U << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */\n#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk\n#define DMA_HISR_TCIF6_Pos       (21U)\n#define DMA_HISR_TCIF6_Msk       (0x1U << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */\n#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk\n#define DMA_HISR_HTIF6_Pos       (20U)\n#define DMA_HISR_HTIF6_Msk       (0x1U << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */\n#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk\n#define DMA_HISR_TEIF6_Pos       (19U)\n#define DMA_HISR_TEIF6_Msk       (0x1U << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */\n#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk\n#define DMA_HISR_DMEIF6_Pos      (18U)\n#define DMA_HISR_DMEIF6_Msk      (0x1U << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */\n#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk\n#define DMA_HISR_FEIF6_Pos       (16U)\n#define DMA_HISR_FEIF6_Msk       (0x1U << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */\n#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk\n#define DMA_HISR_TCIF5_Pos       (11U)\n#define DMA_HISR_TCIF5_Msk       (0x1U << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */\n#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk\n#define DMA_HISR_HTIF5_Pos       (10U)\n#define DMA_HISR_HTIF5_Msk       (0x1U << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */\n#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk\n#define DMA_HISR_TEIF5_Pos       (9U)\n#define DMA_HISR_TEIF5_Msk       (0x1U << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */\n#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk\n#define DMA_HISR_DMEIF5_Pos      (8U)\n#define DMA_HISR_DMEIF5_Msk      (0x1U << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */\n#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk\n#define DMA_HISR_FEIF5_Pos       (6U)\n#define DMA_HISR_FEIF5_Msk       (0x1U << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */\n#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk\n#define DMA_HISR_TCIF4_Pos       (5U)\n#define DMA_HISR_TCIF4_Msk       (0x1U << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */\n#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk\n#define DMA_HISR_HTIF4_Pos       (4U)\n#define DMA_HISR_HTIF4_Msk       (0x1U << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */\n#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk\n#define DMA_HISR_TEIF4_Pos       (3U)\n#define DMA_HISR_TEIF4_Msk       (0x1U << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */\n#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk\n#define DMA_HISR_DMEIF4_Pos      (2U)\n#define DMA_HISR_DMEIF4_Msk      (0x1U << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */\n#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk\n#define DMA_HISR_FEIF4_Pos       (0U)\n#define DMA_HISR_FEIF4_Msk       (0x1U << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */\n#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk\n\n/********************  Bits definition for DMA_LIFCR register  ****************/\n#define DMA_LIFCR_CTCIF3_Pos     (27U)\n#define DMA_LIFCR_CTCIF3_Msk     (0x1U << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */\n#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk\n#define DMA_LIFCR_CHTIF3_Pos     (26U)\n#define DMA_LIFCR_CHTIF3_Msk     (0x1U << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */\n#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk\n#define DMA_LIFCR_CTEIF3_Pos     (25U)\n#define DMA_LIFCR_CTEIF3_Msk     (0x1U << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */\n#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk\n#define DMA_LIFCR_CDMEIF3_Pos    (24U)\n#define DMA_LIFCR_CDMEIF3_Msk    (0x1U << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */\n#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk\n#define DMA_LIFCR_CFEIF3_Pos     (22U)\n#define DMA_LIFCR_CFEIF3_Msk     (0x1U << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */\n#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk\n#define DMA_LIFCR_CTCIF2_Pos     (21U)\n#define DMA_LIFCR_CTCIF2_Msk     (0x1U << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */\n#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk\n#define DMA_LIFCR_CHTIF2_Pos     (20U)\n#define DMA_LIFCR_CHTIF2_Msk     (0x1U << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */\n#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk\n#define DMA_LIFCR_CTEIF2_Pos     (19U)\n#define DMA_LIFCR_CTEIF2_Msk     (0x1U << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */\n#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk\n#define DMA_LIFCR_CDMEIF2_Pos    (18U)\n#define DMA_LIFCR_CDMEIF2_Msk    (0x1U << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */\n#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk\n#define DMA_LIFCR_CFEIF2_Pos     (16U)\n#define DMA_LIFCR_CFEIF2_Msk     (0x1U << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */\n#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk\n#define DMA_LIFCR_CTCIF1_Pos     (11U)\n#define DMA_LIFCR_CTCIF1_Msk     (0x1U << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */\n#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk\n#define DMA_LIFCR_CHTIF1_Pos     (10U)\n#define DMA_LIFCR_CHTIF1_Msk     (0x1U << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */\n#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk\n#define DMA_LIFCR_CTEIF1_Pos     (9U)\n#define DMA_LIFCR_CTEIF1_Msk     (0x1U << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */\n#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk\n#define DMA_LIFCR_CDMEIF1_Pos    (8U)\n#define DMA_LIFCR_CDMEIF1_Msk    (0x1U << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */\n#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk\n#define DMA_LIFCR_CFEIF1_Pos     (6U)\n#define DMA_LIFCR_CFEIF1_Msk     (0x1U << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */\n#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk\n#define DMA_LIFCR_CTCIF0_Pos     (5U)\n#define DMA_LIFCR_CTCIF0_Msk     (0x1U << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */\n#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk\n#define DMA_LIFCR_CHTIF0_Pos     (4U)\n#define DMA_LIFCR_CHTIF0_Msk     (0x1U << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */\n#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk\n#define DMA_LIFCR_CTEIF0_Pos     (3U)\n#define DMA_LIFCR_CTEIF0_Msk     (0x1U << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */\n#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk\n#define DMA_LIFCR_CDMEIF0_Pos    (2U)\n#define DMA_LIFCR_CDMEIF0_Msk    (0x1U << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */\n#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk\n#define DMA_LIFCR_CFEIF0_Pos     (0U)\n#define DMA_LIFCR_CFEIF0_Msk     (0x1U << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */\n#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk\n\n/********************  Bits definition for DMA_HIFCR  register  ****************/\n#define DMA_HIFCR_CTCIF7_Pos     (27U)\n#define DMA_HIFCR_CTCIF7_Msk     (0x1U << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */\n#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk\n#define DMA_HIFCR_CHTIF7_Pos     (26U)\n#define DMA_HIFCR_CHTIF7_Msk     (0x1U << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */\n#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk\n#define DMA_HIFCR_CTEIF7_Pos     (25U)\n#define DMA_HIFCR_CTEIF7_Msk     (0x1U << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */\n#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk\n#define DMA_HIFCR_CDMEIF7_Pos    (24U)\n#define DMA_HIFCR_CDMEIF7_Msk    (0x1U << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */\n#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk\n#define DMA_HIFCR_CFEIF7_Pos     (22U)\n#define DMA_HIFCR_CFEIF7_Msk     (0x1U << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */\n#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk\n#define DMA_HIFCR_CTCIF6_Pos     (21U)\n#define DMA_HIFCR_CTCIF6_Msk     (0x1U << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */\n#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk\n#define DMA_HIFCR_CHTIF6_Pos     (20U)\n#define DMA_HIFCR_CHTIF6_Msk     (0x1U << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */\n#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk\n#define DMA_HIFCR_CTEIF6_Pos     (19U)\n#define DMA_HIFCR_CTEIF6_Msk     (0x1U << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */\n#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk\n#define DMA_HIFCR_CDMEIF6_Pos    (18U)\n#define DMA_HIFCR_CDMEIF6_Msk    (0x1U << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */\n#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk\n#define DMA_HIFCR_CFEIF6_Pos     (16U)\n#define DMA_HIFCR_CFEIF6_Msk     (0x1U << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */\n#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk\n#define DMA_HIFCR_CTCIF5_Pos     (11U)\n#define DMA_HIFCR_CTCIF5_Msk     (0x1U << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */\n#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk\n#define DMA_HIFCR_CHTIF5_Pos     (10U)\n#define DMA_HIFCR_CHTIF5_Msk     (0x1U << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */\n#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk\n#define DMA_HIFCR_CTEIF5_Pos     (9U)\n#define DMA_HIFCR_CTEIF5_Msk     (0x1U << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */\n#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk\n#define DMA_HIFCR_CDMEIF5_Pos    (8U)\n#define DMA_HIFCR_CDMEIF5_Msk    (0x1U << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */\n#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk\n#define DMA_HIFCR_CFEIF5_Pos     (6U)\n#define DMA_HIFCR_CFEIF5_Msk     (0x1U << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */\n#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk\n#define DMA_HIFCR_CTCIF4_Pos     (5U)\n#define DMA_HIFCR_CTCIF4_Msk     (0x1U << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */\n#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk\n#define DMA_HIFCR_CHTIF4_Pos     (4U)\n#define DMA_HIFCR_CHTIF4_Msk     (0x1U << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */\n#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk\n#define DMA_HIFCR_CTEIF4_Pos     (3U)\n#define DMA_HIFCR_CTEIF4_Msk     (0x1U << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */\n#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk\n#define DMA_HIFCR_CDMEIF4_Pos    (2U)\n#define DMA_HIFCR_CDMEIF4_Msk    (0x1U << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */\n#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk\n#define DMA_HIFCR_CFEIF4_Pos     (0U)\n#define DMA_HIFCR_CFEIF4_Msk     (0x1U << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */\n#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk\n\n/******************  Bit definition for DMA_SxPAR register  ********************/\n#define DMA_SxPAR_PA_Pos         (0U)\n#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFU << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */\n#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */\n\n/******************  Bit definition for DMA_SxM0AR register  ********************/\n#define DMA_SxM0AR_M0A_Pos       (0U)\n#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */\n\n/******************  Bit definition for DMA_SxM1AR register  ********************/\n#define DMA_SxM1AR_M1A_Pos       (0U)\n#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                         AHB Master DMA2D Controller (DMA2D)                */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for DMA2D_CR register  ******************/\n\n#define DMA2D_CR_START_Pos         (0U)\n#define DMA2D_CR_START_Msk         (0x1U << DMA2D_CR_START_Pos)                /*!< 0x00000001 */\n#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer */\n#define DMA2D_CR_SUSP_Pos          (1U)\n#define DMA2D_CR_SUSP_Msk          (0x1U << DMA2D_CR_SUSP_Pos)                 /*!< 0x00000002 */\n#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer */\n#define DMA2D_CR_ABORT_Pos         (2U)\n#define DMA2D_CR_ABORT_Msk         (0x1U << DMA2D_CR_ABORT_Pos)                /*!< 0x00000004 */\n#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer */\n#define DMA2D_CR_TEIE_Pos          (8U)\n#define DMA2D_CR_TEIE_Msk          (0x1U << DMA2D_CR_TEIE_Pos)                 /*!< 0x00000100 */\n#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable */\n#define DMA2D_CR_TCIE_Pos          (9U)\n#define DMA2D_CR_TCIE_Msk          (0x1U << DMA2D_CR_TCIE_Pos)                 /*!< 0x00000200 */\n#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable */\n#define DMA2D_CR_TWIE_Pos          (10U)\n#define DMA2D_CR_TWIE_Msk          (0x1U << DMA2D_CR_TWIE_Pos)                 /*!< 0x00000400 */\n#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable */\n#define DMA2D_CR_CAEIE_Pos         (11U)\n#define DMA2D_CR_CAEIE_Msk         (0x1U << DMA2D_CR_CAEIE_Pos)                /*!< 0x00000800 */\n#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable */\n#define DMA2D_CR_CTCIE_Pos         (12U)\n#define DMA2D_CR_CTCIE_Msk         (0x1U << DMA2D_CR_CTCIE_Pos)                /*!< 0x00001000 */\n#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */\n#define DMA2D_CR_CEIE_Pos          (13U)\n#define DMA2D_CR_CEIE_Msk          (0x1U << DMA2D_CR_CEIE_Pos)                 /*!< 0x00002000 */\n#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable */\n#define DMA2D_CR_MODE_Pos          (16U)\n#define DMA2D_CR_MODE_Msk          (0x3U << DMA2D_CR_MODE_Pos)                 /*!< 0x00030000 */\n#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[1:0] */\n#define DMA2D_CR_MODE_0            (0x1U << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */\n#define DMA2D_CR_MODE_1            (0x2U << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */\n\n/********************  Bit definition for DMA2D_ISR register  *****************/\n\n#define DMA2D_ISR_TEIF_Pos         (0U)\n#define DMA2D_ISR_TEIF_Msk         (0x1U << DMA2D_ISR_TEIF_Pos)                /*!< 0x00000001 */\n#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag */\n#define DMA2D_ISR_TCIF_Pos         (1U)\n#define DMA2D_ISR_TCIF_Msk         (0x1U << DMA2D_ISR_TCIF_Pos)                /*!< 0x00000002 */\n#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag */\n#define DMA2D_ISR_TWIF_Pos         (2U)\n#define DMA2D_ISR_TWIF_Msk         (0x1U << DMA2D_ISR_TWIF_Pos)                /*!< 0x00000004 */\n#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag */\n#define DMA2D_ISR_CAEIF_Pos        (3U)\n#define DMA2D_ISR_CAEIF_Msk        (0x1U << DMA2D_ISR_CAEIF_Pos)               /*!< 0x00000008 */\n#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag */\n#define DMA2D_ISR_CTCIF_Pos        (4U)\n#define DMA2D_ISR_CTCIF_Msk        (0x1U << DMA2D_ISR_CTCIF_Pos)               /*!< 0x00000010 */\n#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */\n#define DMA2D_ISR_CEIF_Pos         (5U)\n#define DMA2D_ISR_CEIF_Msk         (0x1U << DMA2D_ISR_CEIF_Pos)                /*!< 0x00000020 */\n#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag */\n\n/********************  Bit definition for DMA2D_IFCR register  ****************/\n\n#define DMA2D_IFCR_CTEIF_Pos       (0U)\n#define DMA2D_IFCR_CTEIF_Msk       (0x1U << DMA2D_IFCR_CTEIF_Pos)              /*!< 0x00000001 */\n#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */\n#define DMA2D_IFCR_CTCIF_Pos       (1U)\n#define DMA2D_IFCR_CTCIF_Msk       (0x1U << DMA2D_IFCR_CTCIF_Pos)              /*!< 0x00000002 */\n#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */\n#define DMA2D_IFCR_CTWIF_Pos       (2U)\n#define DMA2D_IFCR_CTWIF_Msk       (0x1U << DMA2D_IFCR_CTWIF_Pos)              /*!< 0x00000004 */\n#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */\n#define DMA2D_IFCR_CAECIF_Pos      (3U)\n#define DMA2D_IFCR_CAECIF_Msk      (0x1U << DMA2D_IFCR_CAECIF_Pos)             /*!< 0x00000008 */\n#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */\n#define DMA2D_IFCR_CCTCIF_Pos      (4U)\n#define DMA2D_IFCR_CCTCIF_Msk      (0x1U << DMA2D_IFCR_CCTCIF_Pos)             /*!< 0x00000010 */\n#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */\n#define DMA2D_IFCR_CCEIF_Pos       (5U)\n#define DMA2D_IFCR_CCEIF_Msk       (0x1U << DMA2D_IFCR_CCEIF_Pos)              /*!< 0x00000020 */\n#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */\n\n/* Legacy defines */\n#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */\n#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */\n#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */\n#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */\n#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */\n#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */\n\n/********************  Bit definition for DMA2D_FGMAR register  ***************/\n\n#define DMA2D_FGMAR_MA_Pos         (0U)\n#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos)         /*!< 0xFFFFFFFF */\n#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Memory Address */\n\n/********************  Bit definition for DMA2D_FGOR register  ****************/\n\n#define DMA2D_FGOR_LO_Pos          (0U)\n#define DMA2D_FGOR_LO_Msk          (0x3FFFU << DMA2D_FGOR_LO_Pos)              /*!< 0x00003FFF */\n#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */\n\n/********************  Bit definition for DMA2D_BGMAR register  ***************/\n\n#define DMA2D_BGMAR_MA_Pos         (0U)\n#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos)         /*!< 0xFFFFFFFF */\n#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Memory Address */\n\n/********************  Bit definition for DMA2D_BGOR register  ****************/\n\n#define DMA2D_BGOR_LO_Pos          (0U)\n#define DMA2D_BGOR_LO_Msk          (0x3FFFU << DMA2D_BGOR_LO_Pos)              /*!< 0x00003FFF */\n#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */\n\n/********************  Bit definition for DMA2D_FGPFCCR register  *************/\n\n#define DMA2D_FGPFCCR_CM_Pos       (0U)\n#define DMA2D_FGPFCCR_CM_Msk       (0xFU << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x0000000F */\n#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */\n#define DMA2D_FGPFCCR_CM_0         (0x1U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */\n#define DMA2D_FGPFCCR_CM_1         (0x2U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */\n#define DMA2D_FGPFCCR_CM_2         (0x4U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */\n#define DMA2D_FGPFCCR_CM_3         (0x8U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */\n#define DMA2D_FGPFCCR_CCM_Pos      (4U)\n#define DMA2D_FGPFCCR_CCM_Msk      (0x1U << DMA2D_FGPFCCR_CCM_Pos)             /*!< 0x00000010 */\n#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */\n#define DMA2D_FGPFCCR_START_Pos    (5U)\n#define DMA2D_FGPFCCR_START_Msk    (0x1U << DMA2D_FGPFCCR_START_Pos)           /*!< 0x00000020 */\n#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */\n#define DMA2D_FGPFCCR_CS_Pos       (8U)\n#define DMA2D_FGPFCCR_CS_Msk       (0xFFU << DMA2D_FGPFCCR_CS_Pos)             /*!< 0x0000FF00 */\n#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */\n#define DMA2D_FGPFCCR_AM_Pos       (16U)\n#define DMA2D_FGPFCCR_AM_Msk       (0x3U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00030000 */\n#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */\n#define DMA2D_FGPFCCR_AM_0         (0x1U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */\n#define DMA2D_FGPFCCR_AM_1         (0x2U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */\n#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)\n#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */\n#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */\n\n/********************  Bit definition for DMA2D_FGCOLR register  **************/\n\n#define DMA2D_FGCOLR_BLUE_Pos      (0U)\n#define DMA2D_FGCOLR_BLUE_Msk      (0xFFU << DMA2D_FGCOLR_BLUE_Pos)            /*!< 0x000000FF */\n#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Blue Value */\n#define DMA2D_FGCOLR_GREEN_Pos     (8U)\n#define DMA2D_FGCOLR_GREEN_Msk     (0xFFU << DMA2D_FGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */\n#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Green Value */\n#define DMA2D_FGCOLR_RED_Pos       (16U)\n#define DMA2D_FGCOLR_RED_Msk       (0xFFU << DMA2D_FGCOLR_RED_Pos)             /*!< 0x00FF0000 */\n#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Red Value */\n\n/********************  Bit definition for DMA2D_BGPFCCR register  *************/\n\n#define DMA2D_BGPFCCR_CM_Pos       (0U)\n#define DMA2D_BGPFCCR_CM_Msk       (0xFU << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x0000000F */\n#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */\n#define DMA2D_BGPFCCR_CM_0         (0x1U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */\n#define DMA2D_BGPFCCR_CM_1         (0x2U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */\n#define DMA2D_BGPFCCR_CM_2         (0x4U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */\n#define DMA2D_BGPFCCR_CM_3         0x00000008U                                 /*!< Input color mode CM bit 3 */\n#define DMA2D_BGPFCCR_CCM_Pos      (4U)\n#define DMA2D_BGPFCCR_CCM_Msk      (0x1U << DMA2D_BGPFCCR_CCM_Pos)             /*!< 0x00000010 */\n#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */\n#define DMA2D_BGPFCCR_START_Pos    (5U)\n#define DMA2D_BGPFCCR_START_Msk    (0x1U << DMA2D_BGPFCCR_START_Pos)           /*!< 0x00000020 */\n#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */\n#define DMA2D_BGPFCCR_CS_Pos       (8U)\n#define DMA2D_BGPFCCR_CS_Msk       (0xFFU << DMA2D_BGPFCCR_CS_Pos)             /*!< 0x0000FF00 */\n#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */\n#define DMA2D_BGPFCCR_AM_Pos       (16U)\n#define DMA2D_BGPFCCR_AM_Msk       (0x3U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00030000 */\n#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */\n#define DMA2D_BGPFCCR_AM_0         (0x1U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */\n#define DMA2D_BGPFCCR_AM_1         (0x2U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */\n#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)\n#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */\n#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */\n\n/********************  Bit definition for DMA2D_BGCOLR register  **************/\n\n#define DMA2D_BGCOLR_BLUE_Pos      (0U)\n#define DMA2D_BGCOLR_BLUE_Msk      (0xFFU << DMA2D_BGCOLR_BLUE_Pos)            /*!< 0x000000FF */\n#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Blue Value */\n#define DMA2D_BGCOLR_GREEN_Pos     (8U)\n#define DMA2D_BGCOLR_GREEN_Msk     (0xFFU << DMA2D_BGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */\n#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Green Value */\n#define DMA2D_BGCOLR_RED_Pos       (16U)\n#define DMA2D_BGCOLR_RED_Msk       (0xFFU << DMA2D_BGCOLR_RED_Pos)             /*!< 0x00FF0000 */\n#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Red Value */\n\n/********************  Bit definition for DMA2D_FGCMAR register  **************/\n\n#define DMA2D_FGCMAR_MA_Pos        (0U)\n#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */\n#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Memory Address */\n\n/********************  Bit definition for DMA2D_BGCMAR register  **************/\n\n#define DMA2D_BGCMAR_MA_Pos        (0U)\n#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */\n#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Memory Address */\n\n/********************  Bit definition for DMA2D_OPFCCR register  **************/\n\n#define DMA2D_OPFCCR_CM_Pos        (0U)\n#define DMA2D_OPFCCR_CM_Msk        (0x7U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000007 */\n#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Color mode CM[2:0] */\n#define DMA2D_OPFCCR_CM_0          (0x1U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000001 */\n#define DMA2D_OPFCCR_CM_1          (0x2U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000002 */\n#define DMA2D_OPFCCR_CM_2          (0x4U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000004 */\n\n/********************  Bit definition for DMA2D_OCOLR register  ***************/\n\n/*!<Mode_ARGB8888/RGB888 */\n\n#define DMA2D_OCOLR_BLUE_1         0x000000FFU                                 /*!< BLUE Value */\n#define DMA2D_OCOLR_GREEN_1        0x0000FF00U                                 /*!< GREEN Value  */\n#define DMA2D_OCOLR_RED_1          0x00FF0000U                                 /*!< Red Value */\n#define DMA2D_OCOLR_ALPHA_1        0xFF000000U                                 /*!< Alpha Channel Value */\n\n/*!<Mode_RGB565 */\n#define DMA2D_OCOLR_BLUE_2         0x0000001FU                                 /*!< BLUE Value */\n#define DMA2D_OCOLR_GREEN_2        0x000007E0U                                 /*!< GREEN Value  */\n#define DMA2D_OCOLR_RED_2          0x0000F800U                                 /*!< Red Value */\n\n/*!<Mode_ARGB1555 */\n#define DMA2D_OCOLR_BLUE_3         0x0000001FU                                 /*!< BLUE Value */\n#define DMA2D_OCOLR_GREEN_3        0x000003E0U                                 /*!< GREEN Value  */\n#define DMA2D_OCOLR_RED_3          0x00007C00U                                 /*!< Red Value */\n#define DMA2D_OCOLR_ALPHA_3        0x00008000U                                 /*!< Alpha Channel Value */\n\n/*!<Mode_ARGB4444 */\n#define DMA2D_OCOLR_BLUE_4         0x0000000FU                                 /*!< BLUE Value */\n#define DMA2D_OCOLR_GREEN_4        0x000000F0U                                 /*!< GREEN Value  */\n#define DMA2D_OCOLR_RED_4          0x00000F00U                                 /*!< Red Value */\n#define DMA2D_OCOLR_ALPHA_4        0x0000F000U                                 /*!< Alpha Channel Value */\n\n/********************  Bit definition for DMA2D_OMAR register  ****************/\n\n#define DMA2D_OMAR_MA_Pos          (0U)\n#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos)          /*!< 0xFFFFFFFF */\n#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Memory Address */\n\n/********************  Bit definition for DMA2D_OOR register  *****************/\n\n#define DMA2D_OOR_LO_Pos           (0U)\n#define DMA2D_OOR_LO_Msk           (0x3FFFU << DMA2D_OOR_LO_Pos)               /*!< 0x00003FFF */\n#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Line Offset */\n\n/********************  Bit definition for DMA2D_NLR register  *****************/\n\n#define DMA2D_NLR_NL_Pos           (0U)\n#define DMA2D_NLR_NL_Msk           (0xFFFFU << DMA2D_NLR_NL_Pos)               /*!< 0x0000FFFF */\n#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */\n#define DMA2D_NLR_PL_Pos           (16U)\n#define DMA2D_NLR_PL_Msk           (0x3FFFU << DMA2D_NLR_PL_Pos)               /*!< 0x3FFF0000 */\n#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */\n\n/********************  Bit definition for DMA2D_LWR register  *****************/\n\n#define DMA2D_LWR_LW_Pos           (0U)\n#define DMA2D_LWR_LW_Msk           (0xFFFFU << DMA2D_LWR_LW_Pos)               /*!< 0x0000FFFF */\n#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */\n\n/********************  Bit definition for DMA2D_AMTCR register  ***************/\n\n#define DMA2D_AMTCR_EN_Pos         (0U)\n#define DMA2D_AMTCR_EN_Msk         (0x1U << DMA2D_AMTCR_EN_Pos)                /*!< 0x00000001 */\n#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */\n#define DMA2D_AMTCR_DT_Pos         (8U)\n#define DMA2D_AMTCR_DT_Msk         (0xFFU << DMA2D_AMTCR_DT_Pos)               /*!< 0x0000FF00 */\n#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */\n\n/********************  Bit definition for DMA2D_FGCLUT register  **************/\n\n/********************  Bit definition for DMA2D_BGCLUT register  **************/\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                     Display Serial Interface (DSI)                         */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for DSI_VR register  *****************/\n#define DSI_VR_Pos                    (1U)\n#define DSI_VR_Msk                    (0x18999815U << DSI_VR_Pos)              /*!< 0x3133302A */\n#define DSI_VR                        DSI_VR_Msk                               /*!< DSI Host Version */\n\n/*******************  Bit definition for DSI_CR register  *****************/\n#define DSI_CR_EN_Pos                 (0U)\n#define DSI_CR_EN_Msk                 (0x1U << DSI_CR_EN_Pos)                  /*!< 0x00000001 */\n#define DSI_CR_EN                     DSI_CR_EN_Msk                            /*!< DSI Host power up and reset */\n\n/*******************  Bit definition for DSI_CCR register  ****************/\n#define DSI_CCR_TXECKDIV_Pos          (0U)\n#define DSI_CCR_TXECKDIV_Msk          (0xFFU << DSI_CCR_TXECKDIV_Pos)          /*!< 0x000000FF */\n#define DSI_CCR_TXECKDIV              DSI_CCR_TXECKDIV_Msk                     /*!< TX Escape Clock Division */\n#define DSI_CCR_TXECKDIV0_Pos         (0U)\n#define DSI_CCR_TXECKDIV0_Msk         (0x1U << DSI_CCR_TXECKDIV0_Pos)          /*!< 0x00000001 */\n#define DSI_CCR_TXECKDIV0             DSI_CCR_TXECKDIV0_Msk\n#define DSI_CCR_TXECKDIV1_Pos         (1U)\n#define DSI_CCR_TXECKDIV1_Msk         (0x1U << DSI_CCR_TXECKDIV1_Pos)          /*!< 0x00000002 */\n#define DSI_CCR_TXECKDIV1             DSI_CCR_TXECKDIV1_Msk\n#define DSI_CCR_TXECKDIV2_Pos         (2U)\n#define DSI_CCR_TXECKDIV2_Msk         (0x1U << DSI_CCR_TXECKDIV2_Pos)          /*!< 0x00000004 */\n#define DSI_CCR_TXECKDIV2             DSI_CCR_TXECKDIV2_Msk\n#define DSI_CCR_TXECKDIV3_Pos         (3U)\n#define DSI_CCR_TXECKDIV3_Msk         (0x1U << DSI_CCR_TXECKDIV3_Pos)          /*!< 0x00000008 */\n#define DSI_CCR_TXECKDIV3             DSI_CCR_TXECKDIV3_Msk\n#define DSI_CCR_TXECKDIV4_Pos         (4U)\n#define DSI_CCR_TXECKDIV4_Msk         (0x1U << DSI_CCR_TXECKDIV4_Pos)          /*!< 0x00000010 */\n#define DSI_CCR_TXECKDIV4             DSI_CCR_TXECKDIV4_Msk\n#define DSI_CCR_TXECKDIV5_Pos         (5U)\n#define DSI_CCR_TXECKDIV5_Msk         (0x1U << DSI_CCR_TXECKDIV5_Pos)          /*!< 0x00000020 */\n#define DSI_CCR_TXECKDIV5             DSI_CCR_TXECKDIV5_Msk\n#define DSI_CCR_TXECKDIV6_Pos         (6U)\n#define DSI_CCR_TXECKDIV6_Msk         (0x1U << DSI_CCR_TXECKDIV6_Pos)          /*!< 0x00000040 */\n#define DSI_CCR_TXECKDIV6             DSI_CCR_TXECKDIV6_Msk\n#define DSI_CCR_TXECKDIV7_Pos         (7U)\n#define DSI_CCR_TXECKDIV7_Msk         (0x1U << DSI_CCR_TXECKDIV7_Pos)          /*!< 0x00000080 */\n#define DSI_CCR_TXECKDIV7             DSI_CCR_TXECKDIV7_Msk\n\n#define DSI_CCR_TOCKDIV_Pos           (8U)\n#define DSI_CCR_TOCKDIV_Msk           (0xFFU << DSI_CCR_TOCKDIV_Pos)           /*!< 0x0000FF00 */\n#define DSI_CCR_TOCKDIV               DSI_CCR_TOCKDIV_Msk                      /*!< Timeout Clock Division */\n#define DSI_CCR_TOCKDIV0_Pos          (8U)\n#define DSI_CCR_TOCKDIV0_Msk          (0x1U << DSI_CCR_TOCKDIV0_Pos)           /*!< 0x00000100 */\n#define DSI_CCR_TOCKDIV0              DSI_CCR_TOCKDIV0_Msk\n#define DSI_CCR_TOCKDIV1_Pos          (9U)\n#define DSI_CCR_TOCKDIV1_Msk          (0x1U << DSI_CCR_TOCKDIV1_Pos)           /*!< 0x00000200 */\n#define DSI_CCR_TOCKDIV1              DSI_CCR_TOCKDIV1_Msk\n#define DSI_CCR_TOCKDIV2_Pos          (10U)\n#define DSI_CCR_TOCKDIV2_Msk          (0x1U << DSI_CCR_TOCKDIV2_Pos)           /*!< 0x00000400 */\n#define DSI_CCR_TOCKDIV2              DSI_CCR_TOCKDIV2_Msk\n#define DSI_CCR_TOCKDIV3_Pos          (11U)\n#define DSI_CCR_TOCKDIV3_Msk          (0x1U << DSI_CCR_TOCKDIV3_Pos)           /*!< 0x00000800 */\n#define DSI_CCR_TOCKDIV3              DSI_CCR_TOCKDIV3_Msk\n#define DSI_CCR_TOCKDIV4_Pos          (12U)\n#define DSI_CCR_TOCKDIV4_Msk          (0x1U << DSI_CCR_TOCKDIV4_Pos)           /*!< 0x00001000 */\n#define DSI_CCR_TOCKDIV4              DSI_CCR_TOCKDIV4_Msk\n#define DSI_CCR_TOCKDIV5_Pos          (13U)\n#define DSI_CCR_TOCKDIV5_Msk          (0x1U << DSI_CCR_TOCKDIV5_Pos)           /*!< 0x00002000 */\n#define DSI_CCR_TOCKDIV5              DSI_CCR_TOCKDIV5_Msk\n#define DSI_CCR_TOCKDIV6_Pos          (14U)\n#define DSI_CCR_TOCKDIV6_Msk          (0x1U << DSI_CCR_TOCKDIV6_Pos)           /*!< 0x00004000 */\n#define DSI_CCR_TOCKDIV6              DSI_CCR_TOCKDIV6_Msk\n#define DSI_CCR_TOCKDIV7_Pos          (15U)\n#define DSI_CCR_TOCKDIV7_Msk          (0x1U << DSI_CCR_TOCKDIV7_Pos)           /*!< 0x00008000 */\n#define DSI_CCR_TOCKDIV7              DSI_CCR_TOCKDIV7_Msk\n\n/*******************  Bit definition for DSI_LVCIDR register  *************/\n#define DSI_LVCIDR_VCID_Pos           (0U)\n#define DSI_LVCIDR_VCID_Msk           (0x3U << DSI_LVCIDR_VCID_Pos)            /*!< 0x00000003 */\n#define DSI_LVCIDR_VCID               DSI_LVCIDR_VCID_Msk                      /*!< Virtual Channel ID */\n#define DSI_LVCIDR_VCID0_Pos          (0U)\n#define DSI_LVCIDR_VCID0_Msk          (0x1U << DSI_LVCIDR_VCID0_Pos)           /*!< 0x00000001 */\n#define DSI_LVCIDR_VCID0              DSI_LVCIDR_VCID0_Msk\n#define DSI_LVCIDR_VCID1_Pos          (1U)\n#define DSI_LVCIDR_VCID1_Msk          (0x1U << DSI_LVCIDR_VCID1_Pos)           /*!< 0x00000002 */\n#define DSI_LVCIDR_VCID1              DSI_LVCIDR_VCID1_Msk\n\n/*******************  Bit definition for DSI_LCOLCR register  *************/\n#define DSI_LCOLCR_COLC_Pos           (0U)\n#define DSI_LCOLCR_COLC_Msk           (0xFU << DSI_LCOLCR_COLC_Pos)            /*!< 0x0000000F */\n#define DSI_LCOLCR_COLC               DSI_LCOLCR_COLC_Msk                      /*!< Color Coding */\n#define DSI_LCOLCR_COLC0_Pos          (0U)\n#define DSI_LCOLCR_COLC0_Msk          (0x1U << DSI_LCOLCR_COLC0_Pos)           /*!< 0x00000001 */\n#define DSI_LCOLCR_COLC0              DSI_LCOLCR_COLC0_Msk\n#define DSI_LCOLCR_COLC1_Pos          (5U)\n#define DSI_LCOLCR_COLC1_Msk          (0x1U << DSI_LCOLCR_COLC1_Pos)           /*!< 0x00000020 */\n#define DSI_LCOLCR_COLC1              DSI_LCOLCR_COLC1_Msk\n#define DSI_LCOLCR_COLC2_Pos          (6U)\n#define DSI_LCOLCR_COLC2_Msk          (0x1U << DSI_LCOLCR_COLC2_Pos)           /*!< 0x00000040 */\n#define DSI_LCOLCR_COLC2              DSI_LCOLCR_COLC2_Msk\n#define DSI_LCOLCR_COLC3_Pos          (7U)\n#define DSI_LCOLCR_COLC3_Msk          (0x1U << DSI_LCOLCR_COLC3_Pos)           /*!< 0x00000080 */\n#define DSI_LCOLCR_COLC3              DSI_LCOLCR_COLC3_Msk\n\n#define DSI_LCOLCR_LPE_Pos            (8U)\n#define DSI_LCOLCR_LPE_Msk            (0x1U << DSI_LCOLCR_LPE_Pos)             /*!< 0x00000100 */\n#define DSI_LCOLCR_LPE                DSI_LCOLCR_LPE_Msk                       /*!< Loosly Packet Enable */\n\n/*******************  Bit definition for DSI_LPCR register  ***************/\n#define DSI_LPCR_DEP_Pos              (0U)\n#define DSI_LPCR_DEP_Msk              (0x1U << DSI_LPCR_DEP_Pos)               /*!< 0x00000001 */\n#define DSI_LPCR_DEP                  DSI_LPCR_DEP_Msk                         /*!< Data Enable Polarity */\n#define DSI_LPCR_VSP_Pos              (1U)\n#define DSI_LPCR_VSP_Msk              (0x1U << DSI_LPCR_VSP_Pos)               /*!< 0x00000002 */\n#define DSI_LPCR_VSP                  DSI_LPCR_VSP_Msk                         /*!< VSYNC Polarity */\n#define DSI_LPCR_HSP_Pos              (2U)\n#define DSI_LPCR_HSP_Msk              (0x1U << DSI_LPCR_HSP_Pos)               /*!< 0x00000004 */\n#define DSI_LPCR_HSP                  DSI_LPCR_HSP_Msk                         /*!< HSYNC Polarity */\n\n/*******************  Bit definition for DSI_LPMCR register  **************/\n#define DSI_LPMCR_VLPSIZE_Pos         (0U)\n#define DSI_LPMCR_VLPSIZE_Msk         (0xFFU << DSI_LPMCR_VLPSIZE_Pos)         /*!< 0x000000FF */\n#define DSI_LPMCR_VLPSIZE             DSI_LPMCR_VLPSIZE_Msk                    /*!< VACT Largest Packet Size */\n#define DSI_LPMCR_VLPSIZE0_Pos        (0U)\n#define DSI_LPMCR_VLPSIZE0_Msk        (0x1U << DSI_LPMCR_VLPSIZE0_Pos)         /*!< 0x00000001 */\n#define DSI_LPMCR_VLPSIZE0            DSI_LPMCR_VLPSIZE0_Msk\n#define DSI_LPMCR_VLPSIZE1_Pos        (1U)\n#define DSI_LPMCR_VLPSIZE1_Msk        (0x1U << DSI_LPMCR_VLPSIZE1_Pos)         /*!< 0x00000002 */\n#define DSI_LPMCR_VLPSIZE1            DSI_LPMCR_VLPSIZE1_Msk\n#define DSI_LPMCR_VLPSIZE2_Pos        (2U)\n#define DSI_LPMCR_VLPSIZE2_Msk        (0x1U << DSI_LPMCR_VLPSIZE2_Pos)         /*!< 0x00000004 */\n#define DSI_LPMCR_VLPSIZE2            DSI_LPMCR_VLPSIZE2_Msk\n#define DSI_LPMCR_VLPSIZE3_Pos        (3U)\n#define DSI_LPMCR_VLPSIZE3_Msk        (0x1U << DSI_LPMCR_VLPSIZE3_Pos)         /*!< 0x00000008 */\n#define DSI_LPMCR_VLPSIZE3            DSI_LPMCR_VLPSIZE3_Msk\n#define DSI_LPMCR_VLPSIZE4_Pos        (4U)\n#define DSI_LPMCR_VLPSIZE4_Msk        (0x1U << DSI_LPMCR_VLPSIZE4_Pos)         /*!< 0x00000010 */\n#define DSI_LPMCR_VLPSIZE4            DSI_LPMCR_VLPSIZE4_Msk\n#define DSI_LPMCR_VLPSIZE5_Pos        (5U)\n#define DSI_LPMCR_VLPSIZE5_Msk        (0x1U << DSI_LPMCR_VLPSIZE5_Pos)         /*!< 0x00000020 */\n#define DSI_LPMCR_VLPSIZE5            DSI_LPMCR_VLPSIZE5_Msk\n#define DSI_LPMCR_VLPSIZE6_Pos        (6U)\n#define DSI_LPMCR_VLPSIZE6_Msk        (0x1U << DSI_LPMCR_VLPSIZE6_Pos)         /*!< 0x00000040 */\n#define DSI_LPMCR_VLPSIZE6            DSI_LPMCR_VLPSIZE6_Msk\n#define DSI_LPMCR_VLPSIZE7_Pos        (7U)\n#define DSI_LPMCR_VLPSIZE7_Msk        (0x1U << DSI_LPMCR_VLPSIZE7_Pos)         /*!< 0x00000080 */\n#define DSI_LPMCR_VLPSIZE7            DSI_LPMCR_VLPSIZE7_Msk\n\n#define DSI_LPMCR_LPSIZE_Pos          (16U)\n#define DSI_LPMCR_LPSIZE_Msk          (0xFFU << DSI_LPMCR_LPSIZE_Pos)          /*!< 0x00FF0000 */\n#define DSI_LPMCR_LPSIZE              DSI_LPMCR_LPSIZE_Msk                     /*!< Largest Packet Size */\n#define DSI_LPMCR_LPSIZE0_Pos         (16U)\n#define DSI_LPMCR_LPSIZE0_Msk         (0x1U << DSI_LPMCR_LPSIZE0_Pos)          /*!< 0x00010000 */\n#define DSI_LPMCR_LPSIZE0             DSI_LPMCR_LPSIZE0_Msk\n#define DSI_LPMCR_LPSIZE1_Pos         (17U)\n#define DSI_LPMCR_LPSIZE1_Msk         (0x1U << DSI_LPMCR_LPSIZE1_Pos)          /*!< 0x00020000 */\n#define DSI_LPMCR_LPSIZE1             DSI_LPMCR_LPSIZE1_Msk\n#define DSI_LPMCR_LPSIZE2_Pos         (18U)\n#define DSI_LPMCR_LPSIZE2_Msk         (0x1U << DSI_LPMCR_LPSIZE2_Pos)          /*!< 0x00040000 */\n#define DSI_LPMCR_LPSIZE2             DSI_LPMCR_LPSIZE2_Msk\n#define DSI_LPMCR_LPSIZE3_Pos         (19U)\n#define DSI_LPMCR_LPSIZE3_Msk         (0x1U << DSI_LPMCR_LPSIZE3_Pos)          /*!< 0x00080000 */\n#define DSI_LPMCR_LPSIZE3             DSI_LPMCR_LPSIZE3_Msk\n#define DSI_LPMCR_LPSIZE4_Pos         (20U)\n#define DSI_LPMCR_LPSIZE4_Msk         (0x1U << DSI_LPMCR_LPSIZE4_Pos)          /*!< 0x00100000 */\n#define DSI_LPMCR_LPSIZE4             DSI_LPMCR_LPSIZE4_Msk\n#define DSI_LPMCR_LPSIZE5_Pos         (21U)\n#define DSI_LPMCR_LPSIZE5_Msk         (0x1U << DSI_LPMCR_LPSIZE5_Pos)          /*!< 0x00200000 */\n#define DSI_LPMCR_LPSIZE5             DSI_LPMCR_LPSIZE5_Msk\n#define DSI_LPMCR_LPSIZE6_Pos         (22U)\n#define DSI_LPMCR_LPSIZE6_Msk         (0x1U << DSI_LPMCR_LPSIZE6_Pos)          /*!< 0x00400000 */\n#define DSI_LPMCR_LPSIZE6             DSI_LPMCR_LPSIZE6_Msk\n#define DSI_LPMCR_LPSIZE7_Pos         (23U)\n#define DSI_LPMCR_LPSIZE7_Msk         (0x1U << DSI_LPMCR_LPSIZE7_Pos)          /*!< 0x00800000 */\n#define DSI_LPMCR_LPSIZE7             DSI_LPMCR_LPSIZE7_Msk\n\n/*******************  Bit definition for DSI_PCR register  ****************/\n#define DSI_PCR_ETTXE_Pos             (0U)\n#define DSI_PCR_ETTXE_Msk             (0x1U << DSI_PCR_ETTXE_Pos)              /*!< 0x00000001 */\n#define DSI_PCR_ETTXE                 DSI_PCR_ETTXE_Msk                        /*!< EoTp Transmission Enable */\n#define DSI_PCR_ETRXE_Pos             (1U)\n#define DSI_PCR_ETRXE_Msk             (0x1U << DSI_PCR_ETRXE_Pos)              /*!< 0x00000002 */\n#define DSI_PCR_ETRXE                 DSI_PCR_ETRXE_Msk                        /*!< EoTp Reception Enable */\n#define DSI_PCR_BTAE_Pos              (2U)\n#define DSI_PCR_BTAE_Msk              (0x1U << DSI_PCR_BTAE_Pos)               /*!< 0x00000004 */\n#define DSI_PCR_BTAE                  DSI_PCR_BTAE_Msk                         /*!< Bus Turn Around Enable */\n#define DSI_PCR_ECCRXE_Pos            (3U)\n#define DSI_PCR_ECCRXE_Msk            (0x1U << DSI_PCR_ECCRXE_Pos)             /*!< 0x00000008 */\n#define DSI_PCR_ECCRXE                DSI_PCR_ECCRXE_Msk                       /*!< ECC Reception Enable */\n#define DSI_PCR_CRCRXE_Pos            (4U)\n#define DSI_PCR_CRCRXE_Msk            (0x1U << DSI_PCR_CRCRXE_Pos)             /*!< 0x00000010 */\n#define DSI_PCR_CRCRXE                DSI_PCR_CRCRXE_Msk                       /*!< CRC Reception Enable */\n\n/*******************  Bit definition for DSI_GVCIDR register  *************/\n#define DSI_GVCIDR_VCID_Pos           (0U)\n#define DSI_GVCIDR_VCID_Msk           (0x3U << DSI_GVCIDR_VCID_Pos)            /*!< 0x00000003 */\n#define DSI_GVCIDR_VCID               DSI_GVCIDR_VCID_Msk                      /*!< Virtual Channel ID */\n#define DSI_GVCIDR_VCID0_Pos          (0U)\n#define DSI_GVCIDR_VCID0_Msk          (0x1U << DSI_GVCIDR_VCID0_Pos)           /*!< 0x00000001 */\n#define DSI_GVCIDR_VCID0              DSI_GVCIDR_VCID0_Msk\n#define DSI_GVCIDR_VCID1_Pos          (1U)\n#define DSI_GVCIDR_VCID1_Msk          (0x1U << DSI_GVCIDR_VCID1_Pos)           /*!< 0x00000002 */\n#define DSI_GVCIDR_VCID1              DSI_GVCIDR_VCID1_Msk\n\n/*******************  Bit definition for DSI_MCR register  ****************/\n#define DSI_MCR_CMDM_Pos              (0U)\n#define DSI_MCR_CMDM_Msk              (0x1U << DSI_MCR_CMDM_Pos)               /*!< 0x00000001 */\n#define DSI_MCR_CMDM                  DSI_MCR_CMDM_Msk                         /*!< Command Mode */\n\n/*******************  Bit definition for DSI_VMCR register  ***************/\n#define DSI_VMCR_VMT_Pos              (0U)\n#define DSI_VMCR_VMT_Msk              (0x3U << DSI_VMCR_VMT_Pos)               /*!< 0x00000003 */\n#define DSI_VMCR_VMT                  DSI_VMCR_VMT_Msk                         /*!< Video Mode Type */\n#define DSI_VMCR_VMT0_Pos             (0U)\n#define DSI_VMCR_VMT0_Msk             (0x1U << DSI_VMCR_VMT0_Pos)              /*!< 0x00000001 */\n#define DSI_VMCR_VMT0                 DSI_VMCR_VMT0_Msk\n#define DSI_VMCR_VMT1_Pos             (1U)\n#define DSI_VMCR_VMT1_Msk             (0x1U << DSI_VMCR_VMT1_Pos)              /*!< 0x00000002 */\n#define DSI_VMCR_VMT1                 DSI_VMCR_VMT1_Msk\n\n#define DSI_VMCR_LPVSAE_Pos           (8U)\n#define DSI_VMCR_LPVSAE_Msk           (0x1U << DSI_VMCR_LPVSAE_Pos)            /*!< 0x00000100 */\n#define DSI_VMCR_LPVSAE               DSI_VMCR_LPVSAE_Msk                      /*!< Low-Power Vertical Sync Active Enable */\n#define DSI_VMCR_LPVBPE_Pos           (9U)\n#define DSI_VMCR_LPVBPE_Msk           (0x1U << DSI_VMCR_LPVBPE_Pos)            /*!< 0x00000200 */\n#define DSI_VMCR_LPVBPE               DSI_VMCR_LPVBPE_Msk                      /*!< Low-power Vertical Back-Porch Enable */\n#define DSI_VMCR_LPVFPE_Pos           (10U)\n#define DSI_VMCR_LPVFPE_Msk           (0x1U << DSI_VMCR_LPVFPE_Pos)            /*!< 0x00000400 */\n#define DSI_VMCR_LPVFPE               DSI_VMCR_LPVFPE_Msk                      /*!< Low-power Vertical Front-porch Enable */\n#define DSI_VMCR_LPVAE_Pos            (11U)\n#define DSI_VMCR_LPVAE_Msk            (0x1U << DSI_VMCR_LPVAE_Pos)             /*!< 0x00000800 */\n#define DSI_VMCR_LPVAE                DSI_VMCR_LPVAE_Msk                       /*!< Low-Power Vertical Active Enable */\n#define DSI_VMCR_LPHBPE_Pos           (12U)\n#define DSI_VMCR_LPHBPE_Msk           (0x1U << DSI_VMCR_LPHBPE_Pos)            /*!< 0x00001000 */\n#define DSI_VMCR_LPHBPE               DSI_VMCR_LPHBPE_Msk                      /*!< Low-Power Horizontal Back-Porch Enable */\n#define DSI_VMCR_LPHFPE_Pos           (13U)\n#define DSI_VMCR_LPHFPE_Msk           (0x1U << DSI_VMCR_LPHFPE_Pos)            /*!< 0x00002000 */\n#define DSI_VMCR_LPHFPE               DSI_VMCR_LPHFPE_Msk                      /*!< Low-Power Horizontal Front-Porch Enable */\n#define DSI_VMCR_FBTAAE_Pos           (14U)\n#define DSI_VMCR_FBTAAE_Msk           (0x1U << DSI_VMCR_FBTAAE_Pos)            /*!< 0x00004000 */\n#define DSI_VMCR_FBTAAE               DSI_VMCR_FBTAAE_Msk                      /*!< Frame Bus-Turn-Around Acknowledge Enable */\n#define DSI_VMCR_LPCE_Pos             (15U)\n#define DSI_VMCR_LPCE_Msk             (0x1U << DSI_VMCR_LPCE_Pos)              /*!< 0x00008000 */\n#define DSI_VMCR_LPCE                 DSI_VMCR_LPCE_Msk                        /*!< Low-Power Command Enable */\n#define DSI_VMCR_PGE_Pos              (16U)\n#define DSI_VMCR_PGE_Msk              (0x1U << DSI_VMCR_PGE_Pos)               /*!< 0x00010000 */\n#define DSI_VMCR_PGE                  DSI_VMCR_PGE_Msk                         /*!< Pattern Generator Enable */\n#define DSI_VMCR_PGM_Pos              (20U)\n#define DSI_VMCR_PGM_Msk              (0x1U << DSI_VMCR_PGM_Pos)               /*!< 0x00100000 */\n#define DSI_VMCR_PGM                  DSI_VMCR_PGM_Msk                         /*!< Pattern Generator Mode */\n#define DSI_VMCR_PGO_Pos              (24U)\n#define DSI_VMCR_PGO_Msk              (0x1U << DSI_VMCR_PGO_Pos)               /*!< 0x01000000 */\n#define DSI_VMCR_PGO                  DSI_VMCR_PGO_Msk                         /*!< Pattern Generator Orientation */\n\n/*******************  Bit definition for DSI_VPCR register  ***************/\n#define DSI_VPCR_VPSIZE_Pos           (0U)\n#define DSI_VPCR_VPSIZE_Msk           (0x3FFFU << DSI_VPCR_VPSIZE_Pos)         /*!< 0x00003FFF */\n#define DSI_VPCR_VPSIZE               DSI_VPCR_VPSIZE_Msk                      /*!< Video Packet Size */\n#define DSI_VPCR_VPSIZE0_Pos          (0U)\n#define DSI_VPCR_VPSIZE0_Msk          (0x1U << DSI_VPCR_VPSIZE0_Pos)           /*!< 0x00000001 */\n#define DSI_VPCR_VPSIZE0              DSI_VPCR_VPSIZE0_Msk\n#define DSI_VPCR_VPSIZE1_Pos          (1U)\n#define DSI_VPCR_VPSIZE1_Msk          (0x1U << DSI_VPCR_VPSIZE1_Pos)           /*!< 0x00000002 */\n#define DSI_VPCR_VPSIZE1              DSI_VPCR_VPSIZE1_Msk\n#define DSI_VPCR_VPSIZE2_Pos          (2U)\n#define DSI_VPCR_VPSIZE2_Msk          (0x1U << DSI_VPCR_VPSIZE2_Pos)           /*!< 0x00000004 */\n#define DSI_VPCR_VPSIZE2              DSI_VPCR_VPSIZE2_Msk\n#define DSI_VPCR_VPSIZE3_Pos          (3U)\n#define DSI_VPCR_VPSIZE3_Msk          (0x1U << DSI_VPCR_VPSIZE3_Pos)           /*!< 0x00000008 */\n#define DSI_VPCR_VPSIZE3              DSI_VPCR_VPSIZE3_Msk\n#define DSI_VPCR_VPSIZE4_Pos          (4U)\n#define DSI_VPCR_VPSIZE4_Msk          (0x1U << DSI_VPCR_VPSIZE4_Pos)           /*!< 0x00000010 */\n#define DSI_VPCR_VPSIZE4              DSI_VPCR_VPSIZE4_Msk\n#define DSI_VPCR_VPSIZE5_Pos          (5U)\n#define DSI_VPCR_VPSIZE5_Msk          (0x1U << DSI_VPCR_VPSIZE5_Pos)           /*!< 0x00000020 */\n#define DSI_VPCR_VPSIZE5              DSI_VPCR_VPSIZE5_Msk\n#define DSI_VPCR_VPSIZE6_Pos          (6U)\n#define DSI_VPCR_VPSIZE6_Msk          (0x1U << DSI_VPCR_VPSIZE6_Pos)           /*!< 0x00000040 */\n#define DSI_VPCR_VPSIZE6              DSI_VPCR_VPSIZE6_Msk\n#define DSI_VPCR_VPSIZE7_Pos          (7U)\n#define DSI_VPCR_VPSIZE7_Msk          (0x1U << DSI_VPCR_VPSIZE7_Pos)           /*!< 0x00000080 */\n#define DSI_VPCR_VPSIZE7              DSI_VPCR_VPSIZE7_Msk\n#define DSI_VPCR_VPSIZE8_Pos          (8U)\n#define DSI_VPCR_VPSIZE8_Msk          (0x1U << DSI_VPCR_VPSIZE8_Pos)           /*!< 0x00000100 */\n#define DSI_VPCR_VPSIZE8              DSI_VPCR_VPSIZE8_Msk\n#define DSI_VPCR_VPSIZE9_Pos          (9U)\n#define DSI_VPCR_VPSIZE9_Msk          (0x1U << DSI_VPCR_VPSIZE9_Pos)           /*!< 0x00000200 */\n#define DSI_VPCR_VPSIZE9              DSI_VPCR_VPSIZE9_Msk\n#define DSI_VPCR_VPSIZE10_Pos         (10U)\n#define DSI_VPCR_VPSIZE10_Msk         (0x1U << DSI_VPCR_VPSIZE10_Pos)          /*!< 0x00000400 */\n#define DSI_VPCR_VPSIZE10             DSI_VPCR_VPSIZE10_Msk\n#define DSI_VPCR_VPSIZE11_Pos         (11U)\n#define DSI_VPCR_VPSIZE11_Msk         (0x1U << DSI_VPCR_VPSIZE11_Pos)          /*!< 0x00000800 */\n#define DSI_VPCR_VPSIZE11             DSI_VPCR_VPSIZE11_Msk\n#define DSI_VPCR_VPSIZE12_Pos         (12U)\n#define DSI_VPCR_VPSIZE12_Msk         (0x1U << DSI_VPCR_VPSIZE12_Pos)          /*!< 0x00001000 */\n#define DSI_VPCR_VPSIZE12             DSI_VPCR_VPSIZE12_Msk\n#define DSI_VPCR_VPSIZE13_Pos         (13U)\n#define DSI_VPCR_VPSIZE13_Msk         (0x1U << DSI_VPCR_VPSIZE13_Pos)          /*!< 0x00002000 */\n#define DSI_VPCR_VPSIZE13             DSI_VPCR_VPSIZE13_Msk\n\n/*******************  Bit definition for DSI_VCCR register  ***************/\n#define DSI_VCCR_NUMC_Pos             (0U)\n#define DSI_VCCR_NUMC_Msk             (0x1FFFU << DSI_VCCR_NUMC_Pos)           /*!< 0x00001FFF */\n#define DSI_VCCR_NUMC                 DSI_VCCR_NUMC_Msk                        /*!< Number of Chunks */\n#define DSI_VCCR_NUMC0_Pos            (0U)\n#define DSI_VCCR_NUMC0_Msk            (0x1U << DSI_VCCR_NUMC0_Pos)             /*!< 0x00000001 */\n#define DSI_VCCR_NUMC0                DSI_VCCR_NUMC0_Msk\n#define DSI_VCCR_NUMC1_Pos            (1U)\n#define DSI_VCCR_NUMC1_Msk            (0x1U << DSI_VCCR_NUMC1_Pos)             /*!< 0x00000002 */\n#define DSI_VCCR_NUMC1                DSI_VCCR_NUMC1_Msk\n#define DSI_VCCR_NUMC2_Pos            (2U)\n#define DSI_VCCR_NUMC2_Msk            (0x1U << DSI_VCCR_NUMC2_Pos)             /*!< 0x00000004 */\n#define DSI_VCCR_NUMC2                DSI_VCCR_NUMC2_Msk\n#define DSI_VCCR_NUMC3_Pos            (3U)\n#define DSI_VCCR_NUMC3_Msk            (0x1U << DSI_VCCR_NUMC3_Pos)             /*!< 0x00000008 */\n#define DSI_VCCR_NUMC3                DSI_VCCR_NUMC3_Msk\n#define DSI_VCCR_NUMC4_Pos            (4U)\n#define DSI_VCCR_NUMC4_Msk            (0x1U << DSI_VCCR_NUMC4_Pos)             /*!< 0x00000010 */\n#define DSI_VCCR_NUMC4                DSI_VCCR_NUMC4_Msk\n#define DSI_VCCR_NUMC5_Pos            (5U)\n#define DSI_VCCR_NUMC5_Msk            (0x1U << DSI_VCCR_NUMC5_Pos)             /*!< 0x00000020 */\n#define DSI_VCCR_NUMC5                DSI_VCCR_NUMC5_Msk\n#define DSI_VCCR_NUMC6_Pos            (6U)\n#define DSI_VCCR_NUMC6_Msk            (0x1U << DSI_VCCR_NUMC6_Pos)             /*!< 0x00000040 */\n#define DSI_VCCR_NUMC6                DSI_VCCR_NUMC6_Msk\n#define DSI_VCCR_NUMC7_Pos            (7U)\n#define DSI_VCCR_NUMC7_Msk            (0x1U << DSI_VCCR_NUMC7_Pos)             /*!< 0x00000080 */\n#define DSI_VCCR_NUMC7                DSI_VCCR_NUMC7_Msk\n#define DSI_VCCR_NUMC8_Pos            (8U)\n#define DSI_VCCR_NUMC8_Msk            (0x1U << DSI_VCCR_NUMC8_Pos)             /*!< 0x00000100 */\n#define DSI_VCCR_NUMC8                DSI_VCCR_NUMC8_Msk\n#define DSI_VCCR_NUMC9_Pos            (9U)\n#define DSI_VCCR_NUMC9_Msk            (0x1U << DSI_VCCR_NUMC9_Pos)             /*!< 0x00000200 */\n#define DSI_VCCR_NUMC9                DSI_VCCR_NUMC9_Msk\n#define DSI_VCCR_NUMC10_Pos           (10U)\n#define DSI_VCCR_NUMC10_Msk           (0x1U << DSI_VCCR_NUMC10_Pos)            /*!< 0x00000400 */\n#define DSI_VCCR_NUMC10               DSI_VCCR_NUMC10_Msk\n#define DSI_VCCR_NUMC11_Pos           (11U)\n#define DSI_VCCR_NUMC11_Msk           (0x1U << DSI_VCCR_NUMC11_Pos)            /*!< 0x00000800 */\n#define DSI_VCCR_NUMC11               DSI_VCCR_NUMC11_Msk\n#define DSI_VCCR_NUMC12_Pos           (12U)\n#define DSI_VCCR_NUMC12_Msk           (0x1U << DSI_VCCR_NUMC12_Pos)            /*!< 0x00001000 */\n#define DSI_VCCR_NUMC12               DSI_VCCR_NUMC12_Msk\n\n/*******************  Bit definition for DSI_VNPCR register  **************/\n#define DSI_VNPCR_NPSIZE_Pos          (0U)\n#define DSI_VNPCR_NPSIZE_Msk          (0x1FFFU << DSI_VNPCR_NPSIZE_Pos)        /*!< 0x00001FFF */\n#define DSI_VNPCR_NPSIZE              DSI_VNPCR_NPSIZE_Msk                     /*!< Null Packet Size */\n#define DSI_VNPCR_NPSIZE0_Pos         (0U)\n#define DSI_VNPCR_NPSIZE0_Msk         (0x1U << DSI_VNPCR_NPSIZE0_Pos)          /*!< 0x00000001 */\n#define DSI_VNPCR_NPSIZE0             DSI_VNPCR_NPSIZE0_Msk\n#define DSI_VNPCR_NPSIZE1_Pos         (1U)\n#define DSI_VNPCR_NPSIZE1_Msk         (0x1U << DSI_VNPCR_NPSIZE1_Pos)          /*!< 0x00000002 */\n#define DSI_VNPCR_NPSIZE1             DSI_VNPCR_NPSIZE1_Msk\n#define DSI_VNPCR_NPSIZE2_Pos         (2U)\n#define DSI_VNPCR_NPSIZE2_Msk         (0x1U << DSI_VNPCR_NPSIZE2_Pos)          /*!< 0x00000004 */\n#define DSI_VNPCR_NPSIZE2             DSI_VNPCR_NPSIZE2_Msk\n#define DSI_VNPCR_NPSIZE3_Pos         (3U)\n#define DSI_VNPCR_NPSIZE3_Msk         (0x1U << DSI_VNPCR_NPSIZE3_Pos)          /*!< 0x00000008 */\n#define DSI_VNPCR_NPSIZE3             DSI_VNPCR_NPSIZE3_Msk\n#define DSI_VNPCR_NPSIZE4_Pos         (4U)\n#define DSI_VNPCR_NPSIZE4_Msk         (0x1U << DSI_VNPCR_NPSIZE4_Pos)          /*!< 0x00000010 */\n#define DSI_VNPCR_NPSIZE4             DSI_VNPCR_NPSIZE4_Msk\n#define DSI_VNPCR_NPSIZE5_Pos         (5U)\n#define DSI_VNPCR_NPSIZE5_Msk         (0x1U << DSI_VNPCR_NPSIZE5_Pos)          /*!< 0x00000020 */\n#define DSI_VNPCR_NPSIZE5             DSI_VNPCR_NPSIZE5_Msk\n#define DSI_VNPCR_NPSIZE6_Pos         (6U)\n#define DSI_VNPCR_NPSIZE6_Msk         (0x1U << DSI_VNPCR_NPSIZE6_Pos)          /*!< 0x00000040 */\n#define DSI_VNPCR_NPSIZE6             DSI_VNPCR_NPSIZE6_Msk\n#define DSI_VNPCR_NPSIZE7_Pos         (7U)\n#define DSI_VNPCR_NPSIZE7_Msk         (0x1U << DSI_VNPCR_NPSIZE7_Pos)          /*!< 0x00000080 */\n#define DSI_VNPCR_NPSIZE7             DSI_VNPCR_NPSIZE7_Msk\n#define DSI_VNPCR_NPSIZE8_Pos         (8U)\n#define DSI_VNPCR_NPSIZE8_Msk         (0x1U << DSI_VNPCR_NPSIZE8_Pos)          /*!< 0x00000100 */\n#define DSI_VNPCR_NPSIZE8             DSI_VNPCR_NPSIZE8_Msk\n#define DSI_VNPCR_NPSIZE9_Pos         (9U)\n#define DSI_VNPCR_NPSIZE9_Msk         (0x1U << DSI_VNPCR_NPSIZE9_Pos)          /*!< 0x00000200 */\n#define DSI_VNPCR_NPSIZE9             DSI_VNPCR_NPSIZE9_Msk\n#define DSI_VNPCR_NPSIZE10_Pos        (10U)\n#define DSI_VNPCR_NPSIZE10_Msk        (0x1U << DSI_VNPCR_NPSIZE10_Pos)         /*!< 0x00000400 */\n#define DSI_VNPCR_NPSIZE10            DSI_VNPCR_NPSIZE10_Msk\n#define DSI_VNPCR_NPSIZE11_Pos        (11U)\n#define DSI_VNPCR_NPSIZE11_Msk        (0x1U << DSI_VNPCR_NPSIZE11_Pos)         /*!< 0x00000800 */\n#define DSI_VNPCR_NPSIZE11            DSI_VNPCR_NPSIZE11_Msk\n#define DSI_VNPCR_NPSIZE12_Pos        (12U)\n#define DSI_VNPCR_NPSIZE12_Msk        (0x1U << DSI_VNPCR_NPSIZE12_Pos)         /*!< 0x00001000 */\n#define DSI_VNPCR_NPSIZE12            DSI_VNPCR_NPSIZE12_Msk\n\n/*******************  Bit definition for DSI_VHSACR register  *************/\n#define DSI_VHSACR_HSA_Pos            (0U)\n#define DSI_VHSACR_HSA_Msk            (0xFFFU << DSI_VHSACR_HSA_Pos)           /*!< 0x00000FFF */\n#define DSI_VHSACR_HSA                DSI_VHSACR_HSA_Msk                       /*!< Horizontal Synchronism Active duration */\n#define DSI_VHSACR_HSA0_Pos           (0U)\n#define DSI_VHSACR_HSA0_Msk           (0x1U << DSI_VHSACR_HSA0_Pos)            /*!< 0x00000001 */\n#define DSI_VHSACR_HSA0               DSI_VHSACR_HSA0_Msk\n#define DSI_VHSACR_HSA1_Pos           (1U)\n#define DSI_VHSACR_HSA1_Msk           (0x1U << DSI_VHSACR_HSA1_Pos)            /*!< 0x00000002 */\n#define DSI_VHSACR_HSA1               DSI_VHSACR_HSA1_Msk\n#define DSI_VHSACR_HSA2_Pos           (2U)\n#define DSI_VHSACR_HSA2_Msk           (0x1U << DSI_VHSACR_HSA2_Pos)            /*!< 0x00000004 */\n#define DSI_VHSACR_HSA2               DSI_VHSACR_HSA2_Msk\n#define DSI_VHSACR_HSA3_Pos           (3U)\n#define DSI_VHSACR_HSA3_Msk           (0x1U << DSI_VHSACR_HSA3_Pos)            /*!< 0x00000008 */\n#define DSI_VHSACR_HSA3               DSI_VHSACR_HSA3_Msk\n#define DSI_VHSACR_HSA4_Pos           (4U)\n#define DSI_VHSACR_HSA4_Msk           (0x1U << DSI_VHSACR_HSA4_Pos)            /*!< 0x00000010 */\n#define DSI_VHSACR_HSA4               DSI_VHSACR_HSA4_Msk\n#define DSI_VHSACR_HSA5_Pos           (5U)\n#define DSI_VHSACR_HSA5_Msk           (0x1U << DSI_VHSACR_HSA5_Pos)            /*!< 0x00000020 */\n#define DSI_VHSACR_HSA5               DSI_VHSACR_HSA5_Msk\n#define DSI_VHSACR_HSA6_Pos           (6U)\n#define DSI_VHSACR_HSA6_Msk           (0x1U << DSI_VHSACR_HSA6_Pos)            /*!< 0x00000040 */\n#define DSI_VHSACR_HSA6               DSI_VHSACR_HSA6_Msk\n#define DSI_VHSACR_HSA7_Pos           (7U)\n#define DSI_VHSACR_HSA7_Msk           (0x1U << DSI_VHSACR_HSA7_Pos)            /*!< 0x00000080 */\n#define DSI_VHSACR_HSA7               DSI_VHSACR_HSA7_Msk\n#define DSI_VHSACR_HSA8_Pos           (8U)\n#define DSI_VHSACR_HSA8_Msk           (0x1U << DSI_VHSACR_HSA8_Pos)            /*!< 0x00000100 */\n#define DSI_VHSACR_HSA8               DSI_VHSACR_HSA8_Msk\n#define DSI_VHSACR_HSA9_Pos           (9U)\n#define DSI_VHSACR_HSA9_Msk           (0x1U << DSI_VHSACR_HSA9_Pos)            /*!< 0x00000200 */\n#define DSI_VHSACR_HSA9               DSI_VHSACR_HSA9_Msk\n#define DSI_VHSACR_HSA10_Pos          (10U)\n#define DSI_VHSACR_HSA10_Msk          (0x1U << DSI_VHSACR_HSA10_Pos)           /*!< 0x00000400 */\n#define DSI_VHSACR_HSA10              DSI_VHSACR_HSA10_Msk\n#define DSI_VHSACR_HSA11_Pos          (11U)\n#define DSI_VHSACR_HSA11_Msk          (0x1U << DSI_VHSACR_HSA11_Pos)           /*!< 0x00000800 */\n#define DSI_VHSACR_HSA11              DSI_VHSACR_HSA11_Msk\n\n/*******************  Bit definition for DSI_VHBPCR register  *************/\n#define DSI_VHBPCR_HBP_Pos            (0U)\n#define DSI_VHBPCR_HBP_Msk            (0xFFFU << DSI_VHBPCR_HBP_Pos)           /*!< 0x00000FFF */\n#define DSI_VHBPCR_HBP                DSI_VHBPCR_HBP_Msk                       /*!< Horizontal Back-Porch duration */\n#define DSI_VHBPCR_HBP0_Pos           (0U)\n#define DSI_VHBPCR_HBP0_Msk           (0x1U << DSI_VHBPCR_HBP0_Pos)            /*!< 0x00000001 */\n#define DSI_VHBPCR_HBP0               DSI_VHBPCR_HBP0_Msk\n#define DSI_VHBPCR_HBP1_Pos           (1U)\n#define DSI_VHBPCR_HBP1_Msk           (0x1U << DSI_VHBPCR_HBP1_Pos)            /*!< 0x00000002 */\n#define DSI_VHBPCR_HBP1               DSI_VHBPCR_HBP1_Msk\n#define DSI_VHBPCR_HBP2_Pos           (2U)\n#define DSI_VHBPCR_HBP2_Msk           (0x1U << DSI_VHBPCR_HBP2_Pos)            /*!< 0x00000004 */\n#define DSI_VHBPCR_HBP2               DSI_VHBPCR_HBP2_Msk\n#define DSI_VHBPCR_HBP3_Pos           (3U)\n#define DSI_VHBPCR_HBP3_Msk           (0x1U << DSI_VHBPCR_HBP3_Pos)            /*!< 0x00000008 */\n#define DSI_VHBPCR_HBP3               DSI_VHBPCR_HBP3_Msk\n#define DSI_VHBPCR_HBP4_Pos           (4U)\n#define DSI_VHBPCR_HBP4_Msk           (0x1U << DSI_VHBPCR_HBP4_Pos)            /*!< 0x00000010 */\n#define DSI_VHBPCR_HBP4               DSI_VHBPCR_HBP4_Msk\n#define DSI_VHBPCR_HBP5_Pos           (5U)\n#define DSI_VHBPCR_HBP5_Msk           (0x1U << DSI_VHBPCR_HBP5_Pos)            /*!< 0x00000020 */\n#define DSI_VHBPCR_HBP5               DSI_VHBPCR_HBP5_Msk\n#define DSI_VHBPCR_HBP6_Pos           (6U)\n#define DSI_VHBPCR_HBP6_Msk           (0x1U << DSI_VHBPCR_HBP6_Pos)            /*!< 0x00000040 */\n#define DSI_VHBPCR_HBP6               DSI_VHBPCR_HBP6_Msk\n#define DSI_VHBPCR_HBP7_Pos           (7U)\n#define DSI_VHBPCR_HBP7_Msk           (0x1U << DSI_VHBPCR_HBP7_Pos)            /*!< 0x00000080 */\n#define DSI_VHBPCR_HBP7               DSI_VHBPCR_HBP7_Msk\n#define DSI_VHBPCR_HBP8_Pos           (8U)\n#define DSI_VHBPCR_HBP8_Msk           (0x1U << DSI_VHBPCR_HBP8_Pos)            /*!< 0x00000100 */\n#define DSI_VHBPCR_HBP8               DSI_VHBPCR_HBP8_Msk\n#define DSI_VHBPCR_HBP9_Pos           (9U)\n#define DSI_VHBPCR_HBP9_Msk           (0x1U << DSI_VHBPCR_HBP9_Pos)            /*!< 0x00000200 */\n#define DSI_VHBPCR_HBP9               DSI_VHBPCR_HBP9_Msk\n#define DSI_VHBPCR_HBP10_Pos          (10U)\n#define DSI_VHBPCR_HBP10_Msk          (0x1U << DSI_VHBPCR_HBP10_Pos)           /*!< 0x00000400 */\n#define DSI_VHBPCR_HBP10              DSI_VHBPCR_HBP10_Msk\n#define DSI_VHBPCR_HBP11_Pos          (11U)\n#define DSI_VHBPCR_HBP11_Msk          (0x1U << DSI_VHBPCR_HBP11_Pos)           /*!< 0x00000800 */\n#define DSI_VHBPCR_HBP11              DSI_VHBPCR_HBP11_Msk\n\n/*******************  Bit definition for DSI_VLCR register  ***************/\n#define DSI_VLCR_HLINE_Pos            (0U)\n#define DSI_VLCR_HLINE_Msk            (0x7FFFU << DSI_VLCR_HLINE_Pos)          /*!< 0x00007FFF */\n#define DSI_VLCR_HLINE                DSI_VLCR_HLINE_Msk                       /*!< Horizontal Line duration */\n#define DSI_VLCR_HLINE0_Pos           (0U)\n#define DSI_VLCR_HLINE0_Msk           (0x1U << DSI_VLCR_HLINE0_Pos)            /*!< 0x00000001 */\n#define DSI_VLCR_HLINE0               DSI_VLCR_HLINE0_Msk\n#define DSI_VLCR_HLINE1_Pos           (1U)\n#define DSI_VLCR_HLINE1_Msk           (0x1U << DSI_VLCR_HLINE1_Pos)            /*!< 0x00000002 */\n#define DSI_VLCR_HLINE1               DSI_VLCR_HLINE1_Msk\n#define DSI_VLCR_HLINE2_Pos           (2U)\n#define DSI_VLCR_HLINE2_Msk           (0x1U << DSI_VLCR_HLINE2_Pos)            /*!< 0x00000004 */\n#define DSI_VLCR_HLINE2               DSI_VLCR_HLINE2_Msk\n#define DSI_VLCR_HLINE3_Pos           (3U)\n#define DSI_VLCR_HLINE3_Msk           (0x1U << DSI_VLCR_HLINE3_Pos)            /*!< 0x00000008 */\n#define DSI_VLCR_HLINE3               DSI_VLCR_HLINE3_Msk\n#define DSI_VLCR_HLINE4_Pos           (4U)\n#define DSI_VLCR_HLINE4_Msk           (0x1U << DSI_VLCR_HLINE4_Pos)            /*!< 0x00000010 */\n#define DSI_VLCR_HLINE4               DSI_VLCR_HLINE4_Msk\n#define DSI_VLCR_HLINE5_Pos           (5U)\n#define DSI_VLCR_HLINE5_Msk           (0x1U << DSI_VLCR_HLINE5_Pos)            /*!< 0x00000020 */\n#define DSI_VLCR_HLINE5               DSI_VLCR_HLINE5_Msk\n#define DSI_VLCR_HLINE6_Pos           (6U)\n#define DSI_VLCR_HLINE6_Msk           (0x1U << DSI_VLCR_HLINE6_Pos)            /*!< 0x00000040 */\n#define DSI_VLCR_HLINE6               DSI_VLCR_HLINE6_Msk\n#define DSI_VLCR_HLINE7_Pos           (7U)\n#define DSI_VLCR_HLINE7_Msk           (0x1U << DSI_VLCR_HLINE7_Pos)            /*!< 0x00000080 */\n#define DSI_VLCR_HLINE7               DSI_VLCR_HLINE7_Msk\n#define DSI_VLCR_HLINE8_Pos           (8U)\n#define DSI_VLCR_HLINE8_Msk           (0x1U << DSI_VLCR_HLINE8_Pos)            /*!< 0x00000100 */\n#define DSI_VLCR_HLINE8               DSI_VLCR_HLINE8_Msk\n#define DSI_VLCR_HLINE9_Pos           (9U)\n#define DSI_VLCR_HLINE9_Msk           (0x1U << DSI_VLCR_HLINE9_Pos)            /*!< 0x00000200 */\n#define DSI_VLCR_HLINE9               DSI_VLCR_HLINE9_Msk\n#define DSI_VLCR_HLINE10_Pos          (10U)\n#define DSI_VLCR_HLINE10_Msk          (0x1U << DSI_VLCR_HLINE10_Pos)           /*!< 0x00000400 */\n#define DSI_VLCR_HLINE10              DSI_VLCR_HLINE10_Msk\n#define DSI_VLCR_HLINE11_Pos          (11U)\n#define DSI_VLCR_HLINE11_Msk          (0x1U << DSI_VLCR_HLINE11_Pos)           /*!< 0x00000800 */\n#define DSI_VLCR_HLINE11              DSI_VLCR_HLINE11_Msk\n#define DSI_VLCR_HLINE12_Pos          (12U)\n#define DSI_VLCR_HLINE12_Msk          (0x1U << DSI_VLCR_HLINE12_Pos)           /*!< 0x00001000 */\n#define DSI_VLCR_HLINE12              DSI_VLCR_HLINE12_Msk\n#define DSI_VLCR_HLINE13_Pos          (13U)\n#define DSI_VLCR_HLINE13_Msk          (0x1U << DSI_VLCR_HLINE13_Pos)           /*!< 0x00002000 */\n#define DSI_VLCR_HLINE13              DSI_VLCR_HLINE13_Msk\n#define DSI_VLCR_HLINE14_Pos          (14U)\n#define DSI_VLCR_HLINE14_Msk          (0x1U << DSI_VLCR_HLINE14_Pos)           /*!< 0x00004000 */\n#define DSI_VLCR_HLINE14              DSI_VLCR_HLINE14_Msk\n\n/*******************  Bit definition for DSI_VVSACR register  *************/\n#define DSI_VVSACR_VSA_Pos            (0U)\n#define DSI_VVSACR_VSA_Msk            (0x3FFU << DSI_VVSACR_VSA_Pos)           /*!< 0x000003FF */\n#define DSI_VVSACR_VSA                DSI_VVSACR_VSA_Msk                       /*!< Vertical Synchronism Active duration */\n#define DSI_VVSACR_VSA0_Pos           (0U)\n#define DSI_VVSACR_VSA0_Msk           (0x1U << DSI_VVSACR_VSA0_Pos)            /*!< 0x00000001 */\n#define DSI_VVSACR_VSA0               DSI_VVSACR_VSA0_Msk\n#define DSI_VVSACR_VSA1_Pos           (1U)\n#define DSI_VVSACR_VSA1_Msk           (0x1U << DSI_VVSACR_VSA1_Pos)            /*!< 0x00000002 */\n#define DSI_VVSACR_VSA1               DSI_VVSACR_VSA1_Msk\n#define DSI_VVSACR_VSA2_Pos           (2U)\n#define DSI_VVSACR_VSA2_Msk           (0x1U << DSI_VVSACR_VSA2_Pos)            /*!< 0x00000004 */\n#define DSI_VVSACR_VSA2               DSI_VVSACR_VSA2_Msk\n#define DSI_VVSACR_VSA3_Pos           (3U)\n#define DSI_VVSACR_VSA3_Msk           (0x1U << DSI_VVSACR_VSA3_Pos)            /*!< 0x00000008 */\n#define DSI_VVSACR_VSA3               DSI_VVSACR_VSA3_Msk\n#define DSI_VVSACR_VSA4_Pos           (4U)\n#define DSI_VVSACR_VSA4_Msk           (0x1U << DSI_VVSACR_VSA4_Pos)            /*!< 0x00000010 */\n#define DSI_VVSACR_VSA4               DSI_VVSACR_VSA4_Msk\n#define DSI_VVSACR_VSA5_Pos           (5U)\n#define DSI_VVSACR_VSA5_Msk           (0x1U << DSI_VVSACR_VSA5_Pos)            /*!< 0x00000020 */\n#define DSI_VVSACR_VSA5               DSI_VVSACR_VSA5_Msk\n#define DSI_VVSACR_VSA6_Pos           (6U)\n#define DSI_VVSACR_VSA6_Msk           (0x1U << DSI_VVSACR_VSA6_Pos)            /*!< 0x00000040 */\n#define DSI_VVSACR_VSA6               DSI_VVSACR_VSA6_Msk\n#define DSI_VVSACR_VSA7_Pos           (7U)\n#define DSI_VVSACR_VSA7_Msk           (0x1U << DSI_VVSACR_VSA7_Pos)            /*!< 0x00000080 */\n#define DSI_VVSACR_VSA7               DSI_VVSACR_VSA7_Msk\n#define DSI_VVSACR_VSA8_Pos           (8U)\n#define DSI_VVSACR_VSA8_Msk           (0x1U << DSI_VVSACR_VSA8_Pos)            /*!< 0x00000100 */\n#define DSI_VVSACR_VSA8               DSI_VVSACR_VSA8_Msk\n#define DSI_VVSACR_VSA9_Pos           (9U)\n#define DSI_VVSACR_VSA9_Msk           (0x1U << DSI_VVSACR_VSA9_Pos)            /*!< 0x00000200 */\n#define DSI_VVSACR_VSA9               DSI_VVSACR_VSA9_Msk\n\n/*******************  Bit definition for DSI_VVBPCR register  *************/\n#define DSI_VVBPCR_VBP_Pos            (0U)\n#define DSI_VVBPCR_VBP_Msk            (0x3FFU << DSI_VVBPCR_VBP_Pos)           /*!< 0x000003FF */\n#define DSI_VVBPCR_VBP                DSI_VVBPCR_VBP_Msk                       /*!< Vertical Back-Porch duration */\n#define DSI_VVBPCR_VBP0_Pos           (0U)\n#define DSI_VVBPCR_VBP0_Msk           (0x1U << DSI_VVBPCR_VBP0_Pos)            /*!< 0x00000001 */\n#define DSI_VVBPCR_VBP0               DSI_VVBPCR_VBP0_Msk\n#define DSI_VVBPCR_VBP1_Pos           (1U)\n#define DSI_VVBPCR_VBP1_Msk           (0x1U << DSI_VVBPCR_VBP1_Pos)            /*!< 0x00000002 */\n#define DSI_VVBPCR_VBP1               DSI_VVBPCR_VBP1_Msk\n#define DSI_VVBPCR_VBP2_Pos           (2U)\n#define DSI_VVBPCR_VBP2_Msk           (0x1U << DSI_VVBPCR_VBP2_Pos)            /*!< 0x00000004 */\n#define DSI_VVBPCR_VBP2               DSI_VVBPCR_VBP2_Msk\n#define DSI_VVBPCR_VBP3_Pos           (3U)\n#define DSI_VVBPCR_VBP3_Msk           (0x1U << DSI_VVBPCR_VBP3_Pos)            /*!< 0x00000008 */\n#define DSI_VVBPCR_VBP3               DSI_VVBPCR_VBP3_Msk\n#define DSI_VVBPCR_VBP4_Pos           (4U)\n#define DSI_VVBPCR_VBP4_Msk           (0x1U << DSI_VVBPCR_VBP4_Pos)            /*!< 0x00000010 */\n#define DSI_VVBPCR_VBP4               DSI_VVBPCR_VBP4_Msk\n#define DSI_VVBPCR_VBP5_Pos           (5U)\n#define DSI_VVBPCR_VBP5_Msk           (0x1U << DSI_VVBPCR_VBP5_Pos)            /*!< 0x00000020 */\n#define DSI_VVBPCR_VBP5               DSI_VVBPCR_VBP5_Msk\n#define DSI_VVBPCR_VBP6_Pos           (6U)\n#define DSI_VVBPCR_VBP6_Msk           (0x1U << DSI_VVBPCR_VBP6_Pos)            /*!< 0x00000040 */\n#define DSI_VVBPCR_VBP6               DSI_VVBPCR_VBP6_Msk\n#define DSI_VVBPCR_VBP7_Pos           (7U)\n#define DSI_VVBPCR_VBP7_Msk           (0x1U << DSI_VVBPCR_VBP7_Pos)            /*!< 0x00000080 */\n#define DSI_VVBPCR_VBP7               DSI_VVBPCR_VBP7_Msk\n#define DSI_VVBPCR_VBP8_Pos           (8U)\n#define DSI_VVBPCR_VBP8_Msk           (0x1U << DSI_VVBPCR_VBP8_Pos)            /*!< 0x00000100 */\n#define DSI_VVBPCR_VBP8               DSI_VVBPCR_VBP8_Msk\n#define DSI_VVBPCR_VBP9_Pos           (9U)\n#define DSI_VVBPCR_VBP9_Msk           (0x1U << DSI_VVBPCR_VBP9_Pos)            /*!< 0x00000200 */\n#define DSI_VVBPCR_VBP9               DSI_VVBPCR_VBP9_Msk\n\n/*******************  Bit definition for DSI_VVFPCR register  *************/\n#define DSI_VVFPCR_VFP_Pos            (0U)\n#define DSI_VVFPCR_VFP_Msk            (0x3FFU << DSI_VVFPCR_VFP_Pos)           /*!< 0x000003FF */\n#define DSI_VVFPCR_VFP                DSI_VVFPCR_VFP_Msk                       /*!< Vertical Front-Porch duration */\n#define DSI_VVFPCR_VFP0_Pos           (0U)\n#define DSI_VVFPCR_VFP0_Msk           (0x1U << DSI_VVFPCR_VFP0_Pos)            /*!< 0x00000001 */\n#define DSI_VVFPCR_VFP0               DSI_VVFPCR_VFP0_Msk\n#define DSI_VVFPCR_VFP1_Pos           (1U)\n#define DSI_VVFPCR_VFP1_Msk           (0x1U << DSI_VVFPCR_VFP1_Pos)            /*!< 0x00000002 */\n#define DSI_VVFPCR_VFP1               DSI_VVFPCR_VFP1_Msk\n#define DSI_VVFPCR_VFP2_Pos           (2U)\n#define DSI_VVFPCR_VFP2_Msk           (0x1U << DSI_VVFPCR_VFP2_Pos)            /*!< 0x00000004 */\n#define DSI_VVFPCR_VFP2               DSI_VVFPCR_VFP2_Msk\n#define DSI_VVFPCR_VFP3_Pos           (3U)\n#define DSI_VVFPCR_VFP3_Msk           (0x1U << DSI_VVFPCR_VFP3_Pos)            /*!< 0x00000008 */\n#define DSI_VVFPCR_VFP3               DSI_VVFPCR_VFP3_Msk\n#define DSI_VVFPCR_VFP4_Pos           (4U)\n#define DSI_VVFPCR_VFP4_Msk           (0x1U << DSI_VVFPCR_VFP4_Pos)            /*!< 0x00000010 */\n#define DSI_VVFPCR_VFP4               DSI_VVFPCR_VFP4_Msk\n#define DSI_VVFPCR_VFP5_Pos           (5U)\n#define DSI_VVFPCR_VFP5_Msk           (0x1U << DSI_VVFPCR_VFP5_Pos)            /*!< 0x00000020 */\n#define DSI_VVFPCR_VFP5               DSI_VVFPCR_VFP5_Msk\n#define DSI_VVFPCR_VFP6_Pos           (6U)\n#define DSI_VVFPCR_VFP6_Msk           (0x1U << DSI_VVFPCR_VFP6_Pos)            /*!< 0x00000040 */\n#define DSI_VVFPCR_VFP6               DSI_VVFPCR_VFP6_Msk\n#define DSI_VVFPCR_VFP7_Pos           (7U)\n#define DSI_VVFPCR_VFP7_Msk           (0x1U << DSI_VVFPCR_VFP7_Pos)            /*!< 0x00000080 */\n#define DSI_VVFPCR_VFP7               DSI_VVFPCR_VFP7_Msk\n#define DSI_VVFPCR_VFP8_Pos           (8U)\n#define DSI_VVFPCR_VFP8_Msk           (0x1U << DSI_VVFPCR_VFP8_Pos)            /*!< 0x00000100 */\n#define DSI_VVFPCR_VFP8               DSI_VVFPCR_VFP8_Msk\n#define DSI_VVFPCR_VFP9_Pos           (9U)\n#define DSI_VVFPCR_VFP9_Msk           (0x1U << DSI_VVFPCR_VFP9_Pos)            /*!< 0x00000200 */\n#define DSI_VVFPCR_VFP9               DSI_VVFPCR_VFP9_Msk\n\n/*******************  Bit definition for DSI_VVACR register  **************/\n#define DSI_VVACR_VA_Pos              (0U)\n#define DSI_VVACR_VA_Msk              (0x3FFFU << DSI_VVACR_VA_Pos)            /*!< 0x00003FFF */\n#define DSI_VVACR_VA                  DSI_VVACR_VA_Msk                         /*!< Vertical Active duration */\n#define DSI_VVACR_VA0_Pos             (0U)\n#define DSI_VVACR_VA0_Msk             (0x1U << DSI_VVACR_VA0_Pos)              /*!< 0x00000001 */\n#define DSI_VVACR_VA0                 DSI_VVACR_VA0_Msk\n#define DSI_VVACR_VA1_Pos             (1U)\n#define DSI_VVACR_VA1_Msk             (0x1U << DSI_VVACR_VA1_Pos)              /*!< 0x00000002 */\n#define DSI_VVACR_VA1                 DSI_VVACR_VA1_Msk\n#define DSI_VVACR_VA2_Pos             (2U)\n#define DSI_VVACR_VA2_Msk             (0x1U << DSI_VVACR_VA2_Pos)              /*!< 0x00000004 */\n#define DSI_VVACR_VA2                 DSI_VVACR_VA2_Msk\n#define DSI_VVACR_VA3_Pos             (3U)\n#define DSI_VVACR_VA3_Msk             (0x1U << DSI_VVACR_VA3_Pos)              /*!< 0x00000008 */\n#define DSI_VVACR_VA3                 DSI_VVACR_VA3_Msk\n#define DSI_VVACR_VA4_Pos             (4U)\n#define DSI_VVACR_VA4_Msk             (0x1U << DSI_VVACR_VA4_Pos)              /*!< 0x00000010 */\n#define DSI_VVACR_VA4                 DSI_VVACR_VA4_Msk\n#define DSI_VVACR_VA5_Pos             (5U)\n#define DSI_VVACR_VA5_Msk             (0x1U << DSI_VVACR_VA5_Pos)              /*!< 0x00000020 */\n#define DSI_VVACR_VA5                 DSI_VVACR_VA5_Msk\n#define DSI_VVACR_VA6_Pos             (6U)\n#define DSI_VVACR_VA6_Msk             (0x1U << DSI_VVACR_VA6_Pos)              /*!< 0x00000040 */\n#define DSI_VVACR_VA6                 DSI_VVACR_VA6_Msk\n#define DSI_VVACR_VA7_Pos             (7U)\n#define DSI_VVACR_VA7_Msk             (0x1U << DSI_VVACR_VA7_Pos)              /*!< 0x00000080 */\n#define DSI_VVACR_VA7                 DSI_VVACR_VA7_Msk\n#define DSI_VVACR_VA8_Pos             (8U)\n#define DSI_VVACR_VA8_Msk             (0x1U << DSI_VVACR_VA8_Pos)              /*!< 0x00000100 */\n#define DSI_VVACR_VA8                 DSI_VVACR_VA8_Msk\n#define DSI_VVACR_VA9_Pos             (9U)\n#define DSI_VVACR_VA9_Msk             (0x1U << DSI_VVACR_VA9_Pos)              /*!< 0x00000200 */\n#define DSI_VVACR_VA9                 DSI_VVACR_VA9_Msk\n#define DSI_VVACR_VA10_Pos            (10U)\n#define DSI_VVACR_VA10_Msk            (0x1U << DSI_VVACR_VA10_Pos)             /*!< 0x00000400 */\n#define DSI_VVACR_VA10                DSI_VVACR_VA10_Msk\n#define DSI_VVACR_VA11_Pos            (11U)\n#define DSI_VVACR_VA11_Msk            (0x1U << DSI_VVACR_VA11_Pos)             /*!< 0x00000800 */\n#define DSI_VVACR_VA11                DSI_VVACR_VA11_Msk\n#define DSI_VVACR_VA12_Pos            (12U)\n#define DSI_VVACR_VA12_Msk            (0x1U << DSI_VVACR_VA12_Pos)             /*!< 0x00001000 */\n#define DSI_VVACR_VA12                DSI_VVACR_VA12_Msk\n#define DSI_VVACR_VA13_Pos            (13U)\n#define DSI_VVACR_VA13_Msk            (0x1U << DSI_VVACR_VA13_Pos)             /*!< 0x00002000 */\n#define DSI_VVACR_VA13                DSI_VVACR_VA13_Msk\n\n/*******************  Bit definition for DSI_LCCR register  ***************/\n#define DSI_LCCR_CMDSIZE_Pos          (0U)\n#define DSI_LCCR_CMDSIZE_Msk          (0xFFFFU << DSI_LCCR_CMDSIZE_Pos)        /*!< 0x0000FFFF */\n#define DSI_LCCR_CMDSIZE              DSI_LCCR_CMDSIZE_Msk                     /*!< Command Size */\n#define DSI_LCCR_CMDSIZE0_Pos         (0U)\n#define DSI_LCCR_CMDSIZE0_Msk         (0x1U << DSI_LCCR_CMDSIZE0_Pos)          /*!< 0x00000001 */\n#define DSI_LCCR_CMDSIZE0             DSI_LCCR_CMDSIZE0_Msk\n#define DSI_LCCR_CMDSIZE1_Pos         (1U)\n#define DSI_LCCR_CMDSIZE1_Msk         (0x1U << DSI_LCCR_CMDSIZE1_Pos)          /*!< 0x00000002 */\n#define DSI_LCCR_CMDSIZE1             DSI_LCCR_CMDSIZE1_Msk\n#define DSI_LCCR_CMDSIZE2_Pos         (2U)\n#define DSI_LCCR_CMDSIZE2_Msk         (0x1U << DSI_LCCR_CMDSIZE2_Pos)          /*!< 0x00000004 */\n#define DSI_LCCR_CMDSIZE2             DSI_LCCR_CMDSIZE2_Msk\n#define DSI_LCCR_CMDSIZE3_Pos         (3U)\n#define DSI_LCCR_CMDSIZE3_Msk         (0x1U << DSI_LCCR_CMDSIZE3_Pos)          /*!< 0x00000008 */\n#define DSI_LCCR_CMDSIZE3             DSI_LCCR_CMDSIZE3_Msk\n#define DSI_LCCR_CMDSIZE4_Pos         (4U)\n#define DSI_LCCR_CMDSIZE4_Msk         (0x1U << DSI_LCCR_CMDSIZE4_Pos)          /*!< 0x00000010 */\n#define DSI_LCCR_CMDSIZE4             DSI_LCCR_CMDSIZE4_Msk\n#define DSI_LCCR_CMDSIZE5_Pos         (5U)\n#define DSI_LCCR_CMDSIZE5_Msk         (0x1U << DSI_LCCR_CMDSIZE5_Pos)          /*!< 0x00000020 */\n#define DSI_LCCR_CMDSIZE5             DSI_LCCR_CMDSIZE5_Msk\n#define DSI_LCCR_CMDSIZE6_Pos         (6U)\n#define DSI_LCCR_CMDSIZE6_Msk         (0x1U << DSI_LCCR_CMDSIZE6_Pos)          /*!< 0x00000040 */\n#define DSI_LCCR_CMDSIZE6             DSI_LCCR_CMDSIZE6_Msk\n#define DSI_LCCR_CMDSIZE7_Pos         (7U)\n#define DSI_LCCR_CMDSIZE7_Msk         (0x1U << DSI_LCCR_CMDSIZE7_Pos)          /*!< 0x00000080 */\n#define DSI_LCCR_CMDSIZE7             DSI_LCCR_CMDSIZE7_Msk\n#define DSI_LCCR_CMDSIZE8_Pos         (8U)\n#define DSI_LCCR_CMDSIZE8_Msk         (0x1U << DSI_LCCR_CMDSIZE8_Pos)          /*!< 0x00000100 */\n#define DSI_LCCR_CMDSIZE8             DSI_LCCR_CMDSIZE8_Msk\n#define DSI_LCCR_CMDSIZE9_Pos         (9U)\n#define DSI_LCCR_CMDSIZE9_Msk         (0x1U << DSI_LCCR_CMDSIZE9_Pos)          /*!< 0x00000200 */\n#define DSI_LCCR_CMDSIZE9             DSI_LCCR_CMDSIZE9_Msk\n#define DSI_LCCR_CMDSIZE10_Pos        (10U)\n#define DSI_LCCR_CMDSIZE10_Msk        (0x1U << DSI_LCCR_CMDSIZE10_Pos)         /*!< 0x00000400 */\n#define DSI_LCCR_CMDSIZE10            DSI_LCCR_CMDSIZE10_Msk\n#define DSI_LCCR_CMDSIZE11_Pos        (11U)\n#define DSI_LCCR_CMDSIZE11_Msk        (0x1U << DSI_LCCR_CMDSIZE11_Pos)         /*!< 0x00000800 */\n#define DSI_LCCR_CMDSIZE11            DSI_LCCR_CMDSIZE11_Msk\n#define DSI_LCCR_CMDSIZE12_Pos        (12U)\n#define DSI_LCCR_CMDSIZE12_Msk        (0x1U << DSI_LCCR_CMDSIZE12_Pos)         /*!< 0x00001000 */\n#define DSI_LCCR_CMDSIZE12            DSI_LCCR_CMDSIZE12_Msk\n#define DSI_LCCR_CMDSIZE13_Pos        (13U)\n#define DSI_LCCR_CMDSIZE13_Msk        (0x1U << DSI_LCCR_CMDSIZE13_Pos)         /*!< 0x00002000 */\n#define DSI_LCCR_CMDSIZE13            DSI_LCCR_CMDSIZE13_Msk\n#define DSI_LCCR_CMDSIZE14_Pos        (14U)\n#define DSI_LCCR_CMDSIZE14_Msk        (0x1U << DSI_LCCR_CMDSIZE14_Pos)         /*!< 0x00004000 */\n#define DSI_LCCR_CMDSIZE14            DSI_LCCR_CMDSIZE14_Msk\n#define DSI_LCCR_CMDSIZE15_Pos        (15U)\n#define DSI_LCCR_CMDSIZE15_Msk        (0x1U << DSI_LCCR_CMDSIZE15_Pos)         /*!< 0x00008000 */\n#define DSI_LCCR_CMDSIZE15            DSI_LCCR_CMDSIZE15_Msk\n\n/*******************  Bit definition for DSI_CMCR register  ***************/\n#define DSI_CMCR_TEARE_Pos            (0U)\n#define DSI_CMCR_TEARE_Msk            (0x1U << DSI_CMCR_TEARE_Pos)             /*!< 0x00000001 */\n#define DSI_CMCR_TEARE                DSI_CMCR_TEARE_Msk                       /*!< Tearing Effect Acknowledge Request Enable */\n#define DSI_CMCR_ARE_Pos              (1U)\n#define DSI_CMCR_ARE_Msk              (0x1U << DSI_CMCR_ARE_Pos)               /*!< 0x00000002 */\n#define DSI_CMCR_ARE                  DSI_CMCR_ARE_Msk                         /*!< Acknowledge Request Enable */\n#define DSI_CMCR_GSW0TX_Pos           (8U)\n#define DSI_CMCR_GSW0TX_Msk           (0x1U << DSI_CMCR_GSW0TX_Pos)            /*!< 0x00000100 */\n#define DSI_CMCR_GSW0TX               DSI_CMCR_GSW0TX_Msk                      /*!< Generic Short Write Zero parameters Transmission */\n#define DSI_CMCR_GSW1TX_Pos           (9U)\n#define DSI_CMCR_GSW1TX_Msk           (0x1U << DSI_CMCR_GSW1TX_Pos)            /*!< 0x00000200 */\n#define DSI_CMCR_GSW1TX               DSI_CMCR_GSW1TX_Msk                      /*!< Generic Short Write One parameters Transmission */\n#define DSI_CMCR_GSW2TX_Pos           (10U)\n#define DSI_CMCR_GSW2TX_Msk           (0x1U << DSI_CMCR_GSW2TX_Pos)            /*!< 0x00000400 */\n#define DSI_CMCR_GSW2TX               DSI_CMCR_GSW2TX_Msk                      /*!< Generic Short Write Two parameters Transmission */\n#define DSI_CMCR_GSR0TX_Pos           (11U)\n#define DSI_CMCR_GSR0TX_Msk           (0x1U << DSI_CMCR_GSR0TX_Pos)            /*!< 0x00000800 */\n#define DSI_CMCR_GSR0TX               DSI_CMCR_GSR0TX_Msk                      /*!< Generic Short Read Zero parameters Transmission */\n#define DSI_CMCR_GSR1TX_Pos           (12U)\n#define DSI_CMCR_GSR1TX_Msk           (0x1U << DSI_CMCR_GSR1TX_Pos)            /*!< 0x00001000 */\n#define DSI_CMCR_GSR1TX               DSI_CMCR_GSR1TX_Msk                      /*!< Generic Short Read One parameters Transmission */\n#define DSI_CMCR_GSR2TX_Pos           (13U)\n#define DSI_CMCR_GSR2TX_Msk           (0x1U << DSI_CMCR_GSR2TX_Pos)            /*!< 0x00002000 */\n#define DSI_CMCR_GSR2TX               DSI_CMCR_GSR2TX_Msk                      /*!< Generic Short Read Two parameters Transmission */\n#define DSI_CMCR_GLWTX_Pos            (14U)\n#define DSI_CMCR_GLWTX_Msk            (0x1U << DSI_CMCR_GLWTX_Pos)             /*!< 0x00004000 */\n#define DSI_CMCR_GLWTX                DSI_CMCR_GLWTX_Msk                       /*!< Generic Long Write Transmission */\n#define DSI_CMCR_DSW0TX_Pos           (16U)\n#define DSI_CMCR_DSW0TX_Msk           (0x1U << DSI_CMCR_DSW0TX_Pos)            /*!< 0x00010000 */\n#define DSI_CMCR_DSW0TX               DSI_CMCR_DSW0TX_Msk                      /*!< DCS Short Write Zero parameter Transmission */\n#define DSI_CMCR_DSW1TX_Pos           (17U)\n#define DSI_CMCR_DSW1TX_Msk           (0x1U << DSI_CMCR_DSW1TX_Pos)            /*!< 0x00020000 */\n#define DSI_CMCR_DSW1TX               DSI_CMCR_DSW1TX_Msk                      /*!< DCS Short Read One parameter Transmission */\n#define DSI_CMCR_DSR0TX_Pos           (18U)\n#define DSI_CMCR_DSR0TX_Msk           (0x1U << DSI_CMCR_DSR0TX_Pos)            /*!< 0x00040000 */\n#define DSI_CMCR_DSR0TX               DSI_CMCR_DSR0TX_Msk                      /*!< DCS Short Read Zero parameter Transmission */\n#define DSI_CMCR_DLWTX_Pos            (19U)\n#define DSI_CMCR_DLWTX_Msk            (0x1U << DSI_CMCR_DLWTX_Pos)             /*!< 0x00080000 */\n#define DSI_CMCR_DLWTX                DSI_CMCR_DLWTX_Msk                       /*!< DCS Long Write Transmission */\n#define DSI_CMCR_MRDPS_Pos            (24U)\n#define DSI_CMCR_MRDPS_Msk            (0x1U << DSI_CMCR_MRDPS_Pos)             /*!< 0x01000000 */\n#define DSI_CMCR_MRDPS                DSI_CMCR_MRDPS_Msk                       /*!< Maximum Read Packet Size */\n\n/*******************  Bit definition for DSI_GHCR register  ***************/\n#define DSI_GHCR_DT_Pos               (0U)\n#define DSI_GHCR_DT_Msk               (0x3FU << DSI_GHCR_DT_Pos)               /*!< 0x0000003F */\n#define DSI_GHCR_DT                   DSI_GHCR_DT_Msk                          /*!< Type */\n#define DSI_GHCR_DT0_Pos              (0U)\n#define DSI_GHCR_DT0_Msk              (0x1U << DSI_GHCR_DT0_Pos)               /*!< 0x00000001 */\n#define DSI_GHCR_DT0                  DSI_GHCR_DT0_Msk\n#define DSI_GHCR_DT1_Pos              (1U)\n#define DSI_GHCR_DT1_Msk              (0x1U << DSI_GHCR_DT1_Pos)               /*!< 0x00000002 */\n#define DSI_GHCR_DT1                  DSI_GHCR_DT1_Msk\n#define DSI_GHCR_DT2_Pos              (2U)\n#define DSI_GHCR_DT2_Msk              (0x1U << DSI_GHCR_DT2_Pos)               /*!< 0x00000004 */\n#define DSI_GHCR_DT2                  DSI_GHCR_DT2_Msk\n#define DSI_GHCR_DT3_Pos              (3U)\n#define DSI_GHCR_DT3_Msk              (0x1U << DSI_GHCR_DT3_Pos)               /*!< 0x00000008 */\n#define DSI_GHCR_DT3                  DSI_GHCR_DT3_Msk\n#define DSI_GHCR_DT4_Pos              (4U)\n#define DSI_GHCR_DT4_Msk              (0x1U << DSI_GHCR_DT4_Pos)               /*!< 0x00000010 */\n#define DSI_GHCR_DT4                  DSI_GHCR_DT4_Msk\n#define DSI_GHCR_DT5_Pos              (5U)\n#define DSI_GHCR_DT5_Msk              (0x1U << DSI_GHCR_DT5_Pos)               /*!< 0x00000020 */\n#define DSI_GHCR_DT5                  DSI_GHCR_DT5_Msk\n\n#define DSI_GHCR_VCID_Pos             (6U)\n#define DSI_GHCR_VCID_Msk             (0x3U << DSI_GHCR_VCID_Pos)              /*!< 0x000000C0 */\n#define DSI_GHCR_VCID                 DSI_GHCR_VCID_Msk                        /*!< Channel */\n#define DSI_GHCR_VCID0_Pos            (6U)\n#define DSI_GHCR_VCID0_Msk            (0x1U << DSI_GHCR_VCID0_Pos)             /*!< 0x00000040 */\n#define DSI_GHCR_VCID0                DSI_GHCR_VCID0_Msk\n#define DSI_GHCR_VCID1_Pos            (7U)\n#define DSI_GHCR_VCID1_Msk            (0x1U << DSI_GHCR_VCID1_Pos)             /*!< 0x00000080 */\n#define DSI_GHCR_VCID1                DSI_GHCR_VCID1_Msk\n\n#define DSI_GHCR_WCLSB_Pos            (8U)\n#define DSI_GHCR_WCLSB_Msk            (0xFFU << DSI_GHCR_WCLSB_Pos)            /*!< 0x0000FF00 */\n#define DSI_GHCR_WCLSB                DSI_GHCR_WCLSB_Msk                       /*!< WordCount LSB */\n#define DSI_GHCR_WCLSB0_Pos           (8U)\n#define DSI_GHCR_WCLSB0_Msk           (0x1U << DSI_GHCR_WCLSB0_Pos)            /*!< 0x00000100 */\n#define DSI_GHCR_WCLSB0               DSI_GHCR_WCLSB0_Msk\n#define DSI_GHCR_WCLSB1_Pos           (9U)\n#define DSI_GHCR_WCLSB1_Msk           (0x1U << DSI_GHCR_WCLSB1_Pos)            /*!< 0x00000200 */\n#define DSI_GHCR_WCLSB1               DSI_GHCR_WCLSB1_Msk\n#define DSI_GHCR_WCLSB2_Pos           (10U)\n#define DSI_GHCR_WCLSB2_Msk           (0x1U << DSI_GHCR_WCLSB2_Pos)            /*!< 0x00000400 */\n#define DSI_GHCR_WCLSB2               DSI_GHCR_WCLSB2_Msk\n#define DSI_GHCR_WCLSB3_Pos           (11U)\n#define DSI_GHCR_WCLSB3_Msk           (0x1U << DSI_GHCR_WCLSB3_Pos)            /*!< 0x00000800 */\n#define DSI_GHCR_WCLSB3               DSI_GHCR_WCLSB3_Msk\n#define DSI_GHCR_WCLSB4_Pos           (12U)\n#define DSI_GHCR_WCLSB4_Msk           (0x1U << DSI_GHCR_WCLSB4_Pos)            /*!< 0x00001000 */\n#define DSI_GHCR_WCLSB4               DSI_GHCR_WCLSB4_Msk\n#define DSI_GHCR_WCLSB5_Pos           (13U)\n#define DSI_GHCR_WCLSB5_Msk           (0x1U << DSI_GHCR_WCLSB5_Pos)            /*!< 0x00002000 */\n#define DSI_GHCR_WCLSB5               DSI_GHCR_WCLSB5_Msk\n#define DSI_GHCR_WCLSB6_Pos           (14U)\n#define DSI_GHCR_WCLSB6_Msk           (0x1U << DSI_GHCR_WCLSB6_Pos)            /*!< 0x00004000 */\n#define DSI_GHCR_WCLSB6               DSI_GHCR_WCLSB6_Msk\n#define DSI_GHCR_WCLSB7_Pos           (15U)\n#define DSI_GHCR_WCLSB7_Msk           (0x1U << DSI_GHCR_WCLSB7_Pos)            /*!< 0x00008000 */\n#define DSI_GHCR_WCLSB7               DSI_GHCR_WCLSB7_Msk\n\n#define DSI_GHCR_WCMSB_Pos            (16U)\n#define DSI_GHCR_WCMSB_Msk            (0xFFU << DSI_GHCR_WCMSB_Pos)            /*!< 0x00FF0000 */\n#define DSI_GHCR_WCMSB                DSI_GHCR_WCMSB_Msk                       /*!< WordCount MSB */\n#define DSI_GHCR_WCMSB0_Pos           (16U)\n#define DSI_GHCR_WCMSB0_Msk           (0x1U << DSI_GHCR_WCMSB0_Pos)            /*!< 0x00010000 */\n#define DSI_GHCR_WCMSB0               DSI_GHCR_WCMSB0_Msk\n#define DSI_GHCR_WCMSB1_Pos           (17U)\n#define DSI_GHCR_WCMSB1_Msk           (0x1U << DSI_GHCR_WCMSB1_Pos)            /*!< 0x00020000 */\n#define DSI_GHCR_WCMSB1               DSI_GHCR_WCMSB1_Msk\n#define DSI_GHCR_WCMSB2_Pos           (18U)\n#define DSI_GHCR_WCMSB2_Msk           (0x1U << DSI_GHCR_WCMSB2_Pos)            /*!< 0x00040000 */\n#define DSI_GHCR_WCMSB2               DSI_GHCR_WCMSB2_Msk\n#define DSI_GHCR_WCMSB3_Pos           (19U)\n#define DSI_GHCR_WCMSB3_Msk           (0x1U << DSI_GHCR_WCMSB3_Pos)            /*!< 0x00080000 */\n#define DSI_GHCR_WCMSB3               DSI_GHCR_WCMSB3_Msk\n#define DSI_GHCR_WCMSB4_Pos           (20U)\n#define DSI_GHCR_WCMSB4_Msk           (0x1U << DSI_GHCR_WCMSB4_Pos)            /*!< 0x00100000 */\n#define DSI_GHCR_WCMSB4               DSI_GHCR_WCMSB4_Msk\n#define DSI_GHCR_WCMSB5_Pos           (21U)\n#define DSI_GHCR_WCMSB5_Msk           (0x1U << DSI_GHCR_WCMSB5_Pos)            /*!< 0x00200000 */\n#define DSI_GHCR_WCMSB5               DSI_GHCR_WCMSB5_Msk\n#define DSI_GHCR_WCMSB6_Pos           (22U)\n#define DSI_GHCR_WCMSB6_Msk           (0x1U << DSI_GHCR_WCMSB6_Pos)            /*!< 0x00400000 */\n#define DSI_GHCR_WCMSB6               DSI_GHCR_WCMSB6_Msk\n#define DSI_GHCR_WCMSB7_Pos           (23U)\n#define DSI_GHCR_WCMSB7_Msk           (0x1U << DSI_GHCR_WCMSB7_Pos)            /*!< 0x00800000 */\n#define DSI_GHCR_WCMSB7               DSI_GHCR_WCMSB7_Msk\n\n/*******************  Bit definition for DSI_GPDR register  ***************/\n#define DSI_GPDR_DATA1_Pos            (0U)\n#define DSI_GPDR_DATA1_Msk            (0xFFU << DSI_GPDR_DATA1_Pos)            /*!< 0x000000FF */\n#define DSI_GPDR_DATA1                DSI_GPDR_DATA1_Msk                       /*!< Payload Byte 1 */\n#define DSI_GPDR_DATA1_0              (0x01U << DSI_GPDR_DATA1_Pos)            /*!< 0x00000001 */\n#define DSI_GPDR_DATA1_1              (0x02U << DSI_GPDR_DATA1_Pos)            /*!< 0x00000002 */\n#define DSI_GPDR_DATA1_2              (0x04U << DSI_GPDR_DATA1_Pos)            /*!< 0x00000004 */\n#define DSI_GPDR_DATA1_3              (0x08U << DSI_GPDR_DATA1_Pos)            /*!< 0x00000008 */\n#define DSI_GPDR_DATA1_4              (0x10U << DSI_GPDR_DATA1_Pos)            /*!< 0x00000010 */\n#define DSI_GPDR_DATA1_5              (0x20U << DSI_GPDR_DATA1_Pos)            /*!< 0x00000020 */\n#define DSI_GPDR_DATA1_6              (0x40U << DSI_GPDR_DATA1_Pos)            /*!< 0x00000040 */\n#define DSI_GPDR_DATA1_7              (0x80U << DSI_GPDR_DATA1_Pos)            /*!< 0x00000080 */\n\n#define DSI_GPDR_DATA2_Pos            (8U)\n#define DSI_GPDR_DATA2_Msk            (0xFFU << DSI_GPDR_DATA2_Pos)            /*!< 0x0000FF00 */\n#define DSI_GPDR_DATA2                DSI_GPDR_DATA2_Msk                       /*!< Payload Byte 2 */\n#define DSI_GPDR_DATA2_0              (0x01U << DSI_GPDR_DATA2_Pos)            /*!< 0x00000100 */\n#define DSI_GPDR_DATA2_1              (0x02U << DSI_GPDR_DATA2_Pos)            /*!< 0x00000200 */\n#define DSI_GPDR_DATA2_2              (0x04U << DSI_GPDR_DATA2_Pos)            /*!< 0x00000400 */\n#define DSI_GPDR_DATA2_3              (0x08U << DSI_GPDR_DATA2_Pos)            /*!< 0x00000800 */\n#define DSI_GPDR_DATA2_4              (0x10U << DSI_GPDR_DATA2_Pos)            /*!< 0x00001000 */\n#define DSI_GPDR_DATA2_5              (0x20U << DSI_GPDR_DATA2_Pos)            /*!< 0x00002000 */\n#define DSI_GPDR_DATA2_6              (0x40U << DSI_GPDR_DATA2_Pos)            /*!< 0x00004000 */\n#define DSI_GPDR_DATA2_7              (0x80U << DSI_GPDR_DATA2_Pos)            /*!< 0x00008000 */\n\n#define DSI_GPDR_DATA3_Pos            (16U)\n#define DSI_GPDR_DATA3_Msk            (0xFFU << DSI_GPDR_DATA3_Pos)            /*!< 0x00FF0000 */\n#define DSI_GPDR_DATA3                DSI_GPDR_DATA3_Msk                       /*!< Payload Byte 3 */\n#define DSI_GPDR_DATA3_0              (0x01U << DSI_GPDR_DATA3_Pos)            /*!< 0x00010000 */\n#define DSI_GPDR_DATA3_1              (0x02U << DSI_GPDR_DATA3_Pos)            /*!< 0x00020000 */\n#define DSI_GPDR_DATA3_2              (0x04U << DSI_GPDR_DATA3_Pos)            /*!< 0x00040000 */\n#define DSI_GPDR_DATA3_3              (0x08U << DSI_GPDR_DATA3_Pos)            /*!< 0x00080000 */\n#define DSI_GPDR_DATA3_4              (0x10U << DSI_GPDR_DATA3_Pos)            /*!< 0x00100000 */\n#define DSI_GPDR_DATA3_5              (0x20U << DSI_GPDR_DATA3_Pos)            /*!< 0x00200000 */\n#define DSI_GPDR_DATA3_6              (0x40U << DSI_GPDR_DATA3_Pos)            /*!< 0x00400000 */\n#define DSI_GPDR_DATA3_7              (0x80U << DSI_GPDR_DATA3_Pos)            /*!< 0x00800000 */\n\n#define DSI_GPDR_DATA4_Pos            (24U)\n#define DSI_GPDR_DATA4_Msk            (0xFFU << DSI_GPDR_DATA4_Pos)            /*!< 0xFF000000 */\n#define DSI_GPDR_DATA4                DSI_GPDR_DATA4_Msk                       /*!< Payload Byte 4 */\n#define DSI_GPDR_DATA4_0              (0x01U << DSI_GPDR_DATA4_Pos)            /*!< 0x01000000 */\n#define DSI_GPDR_DATA4_1              (0x02U << DSI_GPDR_DATA4_Pos)            /*!< 0x02000000 */\n#define DSI_GPDR_DATA4_2              (0x04U << DSI_GPDR_DATA4_Pos)            /*!< 0x04000000 */\n#define DSI_GPDR_DATA4_3              (0x08U << DSI_GPDR_DATA4_Pos)            /*!< 0x08000000 */\n#define DSI_GPDR_DATA4_4              (0x10U << DSI_GPDR_DATA4_Pos)            /*!< 0x10000000 */\n#define DSI_GPDR_DATA4_5              (0x20U << DSI_GPDR_DATA4_Pos)            /*!< 0x20000000 */\n#define DSI_GPDR_DATA4_6              (0x40U << DSI_GPDR_DATA4_Pos)            /*!< 0x40000000 */\n#define DSI_GPDR_DATA4_7              (0x80U << DSI_GPDR_DATA4_Pos)            /*!< 0x80000000 */\n\n/*******************  Bit definition for DSI_GPSR register  ***************/\n#define DSI_GPSR_CMDFE_Pos            (0U)\n#define DSI_GPSR_CMDFE_Msk            (0x1U << DSI_GPSR_CMDFE_Pos)             /*!< 0x00000001 */\n#define DSI_GPSR_CMDFE                DSI_GPSR_CMDFE_Msk                       /*!< Command FIFO Empty */\n#define DSI_GPSR_CMDFF_Pos            (1U)\n#define DSI_GPSR_CMDFF_Msk            (0x1U << DSI_GPSR_CMDFF_Pos)             /*!< 0x00000002 */\n#define DSI_GPSR_CMDFF                DSI_GPSR_CMDFF_Msk                       /*!< Command FIFO Full */\n#define DSI_GPSR_PWRFE_Pos            (2U)\n#define DSI_GPSR_PWRFE_Msk            (0x1U << DSI_GPSR_PWRFE_Pos)             /*!< 0x00000004 */\n#define DSI_GPSR_PWRFE                DSI_GPSR_PWRFE_Msk                       /*!< Payload Write FIFO Empty */\n#define DSI_GPSR_PWRFF_Pos            (3U)\n#define DSI_GPSR_PWRFF_Msk            (0x1U << DSI_GPSR_PWRFF_Pos)             /*!< 0x00000008 */\n#define DSI_GPSR_PWRFF                DSI_GPSR_PWRFF_Msk                       /*!< Payload Write FIFO Full */\n#define DSI_GPSR_PRDFE_Pos            (4U)\n#define DSI_GPSR_PRDFE_Msk            (0x1U << DSI_GPSR_PRDFE_Pos)             /*!< 0x00000010 */\n#define DSI_GPSR_PRDFE                DSI_GPSR_PRDFE_Msk                       /*!< Payload Read FIFO Empty */\n#define DSI_GPSR_PRDFF_Pos            (5U)\n#define DSI_GPSR_PRDFF_Msk            (0x1U << DSI_GPSR_PRDFF_Pos)             /*!< 0x00000020 */\n#define DSI_GPSR_PRDFF                DSI_GPSR_PRDFF_Msk                       /*!< Payload Read FIFO Full */\n#define DSI_GPSR_RCB_Pos              (6U)\n#define DSI_GPSR_RCB_Msk              (0x1U << DSI_GPSR_RCB_Pos)               /*!< 0x00000040 */\n#define DSI_GPSR_RCB                  DSI_GPSR_RCB_Msk                         /*!< Read Command Busy */\n\n/*******************  Bit definition for DSI_TCCR0 register  **************/\n#define DSI_TCCR0_LPRX_TOCNT_Pos      (0U)\n#define DSI_TCCR0_LPRX_TOCNT_Msk      (0xFFFFU << DSI_TCCR0_LPRX_TOCNT_Pos)    /*!< 0x0000FFFF */\n#define DSI_TCCR0_LPRX_TOCNT          DSI_TCCR0_LPRX_TOCNT_Msk                 /*!< Low-power Reception Timeout Counter */\n#define DSI_TCCR0_LPRX_TOCNT0_Pos     (0U)\n#define DSI_TCCR0_LPRX_TOCNT0_Msk     (0x1U << DSI_TCCR0_LPRX_TOCNT0_Pos)      /*!< 0x00000001 */\n#define DSI_TCCR0_LPRX_TOCNT0         DSI_TCCR0_LPRX_TOCNT0_Msk\n#define DSI_TCCR0_LPRX_TOCNT1_Pos     (1U)\n#define DSI_TCCR0_LPRX_TOCNT1_Msk     (0x1U << DSI_TCCR0_LPRX_TOCNT1_Pos)      /*!< 0x00000002 */\n#define DSI_TCCR0_LPRX_TOCNT1         DSI_TCCR0_LPRX_TOCNT1_Msk\n#define DSI_TCCR0_LPRX_TOCNT2_Pos     (2U)\n#define DSI_TCCR0_LPRX_TOCNT2_Msk     (0x1U << DSI_TCCR0_LPRX_TOCNT2_Pos)      /*!< 0x00000004 */\n#define DSI_TCCR0_LPRX_TOCNT2         DSI_TCCR0_LPRX_TOCNT2_Msk\n#define DSI_TCCR0_LPRX_TOCNT3_Pos     (3U)\n#define DSI_TCCR0_LPRX_TOCNT3_Msk     (0x1U << DSI_TCCR0_LPRX_TOCNT3_Pos)      /*!< 0x00000008 */\n#define DSI_TCCR0_LPRX_TOCNT3         DSI_TCCR0_LPRX_TOCNT3_Msk\n#define DSI_TCCR0_LPRX_TOCNT4_Pos     (4U)\n#define DSI_TCCR0_LPRX_TOCNT4_Msk     (0x1U << DSI_TCCR0_LPRX_TOCNT4_Pos)      /*!< 0x00000010 */\n#define DSI_TCCR0_LPRX_TOCNT4         DSI_TCCR0_LPRX_TOCNT4_Msk\n#define DSI_TCCR0_LPRX_TOCNT5_Pos     (5U)\n#define DSI_TCCR0_LPRX_TOCNT5_Msk     (0x1U << DSI_TCCR0_LPRX_TOCNT5_Pos)      /*!< 0x00000020 */\n#define DSI_TCCR0_LPRX_TOCNT5         DSI_TCCR0_LPRX_TOCNT5_Msk\n#define DSI_TCCR0_LPRX_TOCNT6_Pos     (6U)\n#define DSI_TCCR0_LPRX_TOCNT6_Msk     (0x1U << DSI_TCCR0_LPRX_TOCNT6_Pos)      /*!< 0x00000040 */\n#define DSI_TCCR0_LPRX_TOCNT6         DSI_TCCR0_LPRX_TOCNT6_Msk\n#define DSI_TCCR0_LPRX_TOCNT7_Pos     (7U)\n#define DSI_TCCR0_LPRX_TOCNT7_Msk     (0x1U << DSI_TCCR0_LPRX_TOCNT7_Pos)      /*!< 0x00000080 */\n#define DSI_TCCR0_LPRX_TOCNT7         DSI_TCCR0_LPRX_TOCNT7_Msk\n#define DSI_TCCR0_LPRX_TOCNT8_Pos     (8U)\n#define DSI_TCCR0_LPRX_TOCNT8_Msk     (0x1U << DSI_TCCR0_LPRX_TOCNT8_Pos)      /*!< 0x00000100 */\n#define DSI_TCCR0_LPRX_TOCNT8         DSI_TCCR0_LPRX_TOCNT8_Msk\n#define DSI_TCCR0_LPRX_TOCNT9_Pos     (9U)\n#define DSI_TCCR0_LPRX_TOCNT9_Msk     (0x1U << DSI_TCCR0_LPRX_TOCNT9_Pos)      /*!< 0x00000200 */\n#define DSI_TCCR0_LPRX_TOCNT9         DSI_TCCR0_LPRX_TOCNT9_Msk\n#define DSI_TCCR0_LPRX_TOCNT10_Pos    (10U)\n#define DSI_TCCR0_LPRX_TOCNT10_Msk    (0x1U << DSI_TCCR0_LPRX_TOCNT10_Pos)     /*!< 0x00000400 */\n#define DSI_TCCR0_LPRX_TOCNT10        DSI_TCCR0_LPRX_TOCNT10_Msk\n#define DSI_TCCR0_LPRX_TOCNT11_Pos    (11U)\n#define DSI_TCCR0_LPRX_TOCNT11_Msk    (0x1U << DSI_TCCR0_LPRX_TOCNT11_Pos)     /*!< 0x00000800 */\n#define DSI_TCCR0_LPRX_TOCNT11        DSI_TCCR0_LPRX_TOCNT11_Msk\n#define DSI_TCCR0_LPRX_TOCNT12_Pos    (12U)\n#define DSI_TCCR0_LPRX_TOCNT12_Msk    (0x1U << DSI_TCCR0_LPRX_TOCNT12_Pos)     /*!< 0x00001000 */\n#define DSI_TCCR0_LPRX_TOCNT12        DSI_TCCR0_LPRX_TOCNT12_Msk\n#define DSI_TCCR0_LPRX_TOCNT13_Pos    (13U)\n#define DSI_TCCR0_LPRX_TOCNT13_Msk    (0x1U << DSI_TCCR0_LPRX_TOCNT13_Pos)     /*!< 0x00002000 */\n#define DSI_TCCR0_LPRX_TOCNT13        DSI_TCCR0_LPRX_TOCNT13_Msk\n#define DSI_TCCR0_LPRX_TOCNT14_Pos    (14U)\n#define DSI_TCCR0_LPRX_TOCNT14_Msk    (0x1U << DSI_TCCR0_LPRX_TOCNT14_Pos)     /*!< 0x00004000 */\n#define DSI_TCCR0_LPRX_TOCNT14        DSI_TCCR0_LPRX_TOCNT14_Msk\n#define DSI_TCCR0_LPRX_TOCNT15_Pos    (15U)\n#define DSI_TCCR0_LPRX_TOCNT15_Msk    (0x1U << DSI_TCCR0_LPRX_TOCNT15_Pos)     /*!< 0x00008000 */\n#define DSI_TCCR0_LPRX_TOCNT15        DSI_TCCR0_LPRX_TOCNT15_Msk\n\n#define DSI_TCCR0_HSTX_TOCNT_Pos      (16U)\n#define DSI_TCCR0_HSTX_TOCNT_Msk      (0xFFFFU << DSI_TCCR0_HSTX_TOCNT_Pos)    /*!< 0xFFFF0000 */\n#define DSI_TCCR0_HSTX_TOCNT          DSI_TCCR0_HSTX_TOCNT_Msk                 /*!< High-Speed Transmission Timeout Counter */\n#define DSI_TCCR0_HSTX_TOCNT0_Pos     (16U)\n#define DSI_TCCR0_HSTX_TOCNT0_Msk     (0x1U << DSI_TCCR0_HSTX_TOCNT0_Pos)      /*!< 0x00010000 */\n#define DSI_TCCR0_HSTX_TOCNT0         DSI_TCCR0_HSTX_TOCNT0_Msk\n#define DSI_TCCR0_HSTX_TOCNT1_Pos     (17U)\n#define DSI_TCCR0_HSTX_TOCNT1_Msk     (0x1U << DSI_TCCR0_HSTX_TOCNT1_Pos)      /*!< 0x00020000 */\n#define DSI_TCCR0_HSTX_TOCNT1         DSI_TCCR0_HSTX_TOCNT1_Msk\n#define DSI_TCCR0_HSTX_TOCNT2_Pos     (18U)\n#define DSI_TCCR0_HSTX_TOCNT2_Msk     (0x1U << DSI_TCCR0_HSTX_TOCNT2_Pos)      /*!< 0x00040000 */\n#define DSI_TCCR0_HSTX_TOCNT2         DSI_TCCR0_HSTX_TOCNT2_Msk\n#define DSI_TCCR0_HSTX_TOCNT3_Pos     (19U)\n#define DSI_TCCR0_HSTX_TOCNT3_Msk     (0x1U << DSI_TCCR0_HSTX_TOCNT3_Pos)      /*!< 0x00080000 */\n#define DSI_TCCR0_HSTX_TOCNT3         DSI_TCCR0_HSTX_TOCNT3_Msk\n#define DSI_TCCR0_HSTX_TOCNT4_Pos     (20U)\n#define DSI_TCCR0_HSTX_TOCNT4_Msk     (0x1U << DSI_TCCR0_HSTX_TOCNT4_Pos)      /*!< 0x00100000 */\n#define DSI_TCCR0_HSTX_TOCNT4         DSI_TCCR0_HSTX_TOCNT4_Msk\n#define DSI_TCCR0_HSTX_TOCNT5_Pos     (21U)\n#define DSI_TCCR0_HSTX_TOCNT5_Msk     (0x1U << DSI_TCCR0_HSTX_TOCNT5_Pos)      /*!< 0x00200000 */\n#define DSI_TCCR0_HSTX_TOCNT5         DSI_TCCR0_HSTX_TOCNT5_Msk\n#define DSI_TCCR0_HSTX_TOCNT6_Pos     (22U)\n#define DSI_TCCR0_HSTX_TOCNT6_Msk     (0x1U << DSI_TCCR0_HSTX_TOCNT6_Pos)      /*!< 0x00400000 */\n#define DSI_TCCR0_HSTX_TOCNT6         DSI_TCCR0_HSTX_TOCNT6_Msk\n#define DSI_TCCR0_HSTX_TOCNT7_Pos     (23U)\n#define DSI_TCCR0_HSTX_TOCNT7_Msk     (0x1U << DSI_TCCR0_HSTX_TOCNT7_Pos)      /*!< 0x00800000 */\n#define DSI_TCCR0_HSTX_TOCNT7         DSI_TCCR0_HSTX_TOCNT7_Msk\n#define DSI_TCCR0_HSTX_TOCNT8_Pos     (24U)\n#define DSI_TCCR0_HSTX_TOCNT8_Msk     (0x1U << DSI_TCCR0_HSTX_TOCNT8_Pos)      /*!< 0x01000000 */\n#define DSI_TCCR0_HSTX_TOCNT8         DSI_TCCR0_HSTX_TOCNT8_Msk\n#define DSI_TCCR0_HSTX_TOCNT9_Pos     (25U)\n#define DSI_TCCR0_HSTX_TOCNT9_Msk     (0x1U << DSI_TCCR0_HSTX_TOCNT9_Pos)      /*!< 0x02000000 */\n#define DSI_TCCR0_HSTX_TOCNT9         DSI_TCCR0_HSTX_TOCNT9_Msk\n#define DSI_TCCR0_HSTX_TOCNT10_Pos    (26U)\n#define DSI_TCCR0_HSTX_TOCNT10_Msk    (0x1U << DSI_TCCR0_HSTX_TOCNT10_Pos)     /*!< 0x04000000 */\n#define DSI_TCCR0_HSTX_TOCNT10        DSI_TCCR0_HSTX_TOCNT10_Msk\n#define DSI_TCCR0_HSTX_TOCNT11_Pos    (27U)\n#define DSI_TCCR0_HSTX_TOCNT11_Msk    (0x1U << DSI_TCCR0_HSTX_TOCNT11_Pos)     /*!< 0x08000000 */\n#define DSI_TCCR0_HSTX_TOCNT11        DSI_TCCR0_HSTX_TOCNT11_Msk\n#define DSI_TCCR0_HSTX_TOCNT12_Pos    (28U)\n#define DSI_TCCR0_HSTX_TOCNT12_Msk    (0x1U << DSI_TCCR0_HSTX_TOCNT12_Pos)     /*!< 0x10000000 */\n#define DSI_TCCR0_HSTX_TOCNT12        DSI_TCCR0_HSTX_TOCNT12_Msk\n#define DSI_TCCR0_HSTX_TOCNT13_Pos    (29U)\n#define DSI_TCCR0_HSTX_TOCNT13_Msk    (0x1U << DSI_TCCR0_HSTX_TOCNT13_Pos)     /*!< 0x20000000 */\n#define DSI_TCCR0_HSTX_TOCNT13        DSI_TCCR0_HSTX_TOCNT13_Msk\n#define DSI_TCCR0_HSTX_TOCNT14_Pos    (30U)\n#define DSI_TCCR0_HSTX_TOCNT14_Msk    (0x1U << DSI_TCCR0_HSTX_TOCNT14_Pos)     /*!< 0x40000000 */\n#define DSI_TCCR0_HSTX_TOCNT14        DSI_TCCR0_HSTX_TOCNT14_Msk\n#define DSI_TCCR0_HSTX_TOCNT15_Pos    (31U)\n#define DSI_TCCR0_HSTX_TOCNT15_Msk    (0x1U << DSI_TCCR0_HSTX_TOCNT15_Pos)     /*!< 0x80000000 */\n#define DSI_TCCR0_HSTX_TOCNT15        DSI_TCCR0_HSTX_TOCNT15_Msk\n\n/*******************  Bit definition for DSI_TCCR1 register  **************/\n#define DSI_TCCR1_HSRD_TOCNT_Pos      (0U)\n#define DSI_TCCR1_HSRD_TOCNT_Msk      (0xFFFFU << DSI_TCCR1_HSRD_TOCNT_Pos)    /*!< 0x0000FFFF */\n#define DSI_TCCR1_HSRD_TOCNT          DSI_TCCR1_HSRD_TOCNT_Msk                 /*!< High-Speed Read Timeout Counter */\n#define DSI_TCCR1_HSRD_TOCNT0_Pos     (0U)\n#define DSI_TCCR1_HSRD_TOCNT0_Msk     (0x1U << DSI_TCCR1_HSRD_TOCNT0_Pos)      /*!< 0x00000001 */\n#define DSI_TCCR1_HSRD_TOCNT0         DSI_TCCR1_HSRD_TOCNT0_Msk\n#define DSI_TCCR1_HSRD_TOCNT1_Pos     (1U)\n#define DSI_TCCR1_HSRD_TOCNT1_Msk     (0x1U << DSI_TCCR1_HSRD_TOCNT1_Pos)      /*!< 0x00000002 */\n#define DSI_TCCR1_HSRD_TOCNT1         DSI_TCCR1_HSRD_TOCNT1_Msk\n#define DSI_TCCR1_HSRD_TOCNT2_Pos     (2U)\n#define DSI_TCCR1_HSRD_TOCNT2_Msk     (0x1U << DSI_TCCR1_HSRD_TOCNT2_Pos)      /*!< 0x00000004 */\n#define DSI_TCCR1_HSRD_TOCNT2         DSI_TCCR1_HSRD_TOCNT2_Msk\n#define DSI_TCCR1_HSRD_TOCNT3_Pos     (3U)\n#define DSI_TCCR1_HSRD_TOCNT3_Msk     (0x1U << DSI_TCCR1_HSRD_TOCNT3_Pos)      /*!< 0x00000008 */\n#define DSI_TCCR1_HSRD_TOCNT3         DSI_TCCR1_HSRD_TOCNT3_Msk\n#define DSI_TCCR1_HSRD_TOCNT4_Pos     (4U)\n#define DSI_TCCR1_HSRD_TOCNT4_Msk     (0x1U << DSI_TCCR1_HSRD_TOCNT4_Pos)      /*!< 0x00000010 */\n#define DSI_TCCR1_HSRD_TOCNT4         DSI_TCCR1_HSRD_TOCNT4_Msk\n#define DSI_TCCR1_HSRD_TOCNT5_Pos     (5U)\n#define DSI_TCCR1_HSRD_TOCNT5_Msk     (0x1U << DSI_TCCR1_HSRD_TOCNT5_Pos)      /*!< 0x00000020 */\n#define DSI_TCCR1_HSRD_TOCNT5         DSI_TCCR1_HSRD_TOCNT5_Msk\n#define DSI_TCCR1_HSRD_TOCNT6_Pos     (6U)\n#define DSI_TCCR1_HSRD_TOCNT6_Msk     (0x1U << DSI_TCCR1_HSRD_TOCNT6_Pos)      /*!< 0x00000040 */\n#define DSI_TCCR1_HSRD_TOCNT6         DSI_TCCR1_HSRD_TOCNT6_Msk\n#define DSI_TCCR1_HSRD_TOCNT7_Pos     (7U)\n#define DSI_TCCR1_HSRD_TOCNT7_Msk     (0x1U << DSI_TCCR1_HSRD_TOCNT7_Pos)      /*!< 0x00000080 */\n#define DSI_TCCR1_HSRD_TOCNT7         DSI_TCCR1_HSRD_TOCNT7_Msk\n#define DSI_TCCR1_HSRD_TOCNT8_Pos     (8U)\n#define DSI_TCCR1_HSRD_TOCNT8_Msk     (0x1U << DSI_TCCR1_HSRD_TOCNT8_Pos)      /*!< 0x00000100 */\n#define DSI_TCCR1_HSRD_TOCNT8         DSI_TCCR1_HSRD_TOCNT8_Msk\n#define DSI_TCCR1_HSRD_TOCNT9_Pos     (9U)\n#define DSI_TCCR1_HSRD_TOCNT9_Msk     (0x1U << DSI_TCCR1_HSRD_TOCNT9_Pos)      /*!< 0x00000200 */\n#define DSI_TCCR1_HSRD_TOCNT9         DSI_TCCR1_HSRD_TOCNT9_Msk\n#define DSI_TCCR1_HSRD_TOCNT10_Pos    (10U)\n#define DSI_TCCR1_HSRD_TOCNT10_Msk    (0x1U << DSI_TCCR1_HSRD_TOCNT10_Pos)     /*!< 0x00000400 */\n#define DSI_TCCR1_HSRD_TOCNT10        DSI_TCCR1_HSRD_TOCNT10_Msk\n#define DSI_TCCR1_HSRD_TOCNT11_Pos    (11U)\n#define DSI_TCCR1_HSRD_TOCNT11_Msk    (0x1U << DSI_TCCR1_HSRD_TOCNT11_Pos)     /*!< 0x00000800 */\n#define DSI_TCCR1_HSRD_TOCNT11        DSI_TCCR1_HSRD_TOCNT11_Msk\n#define DSI_TCCR1_HSRD_TOCNT12_Pos    (12U)\n#define DSI_TCCR1_HSRD_TOCNT12_Msk    (0x1U << DSI_TCCR1_HSRD_TOCNT12_Pos)     /*!< 0x00001000 */\n#define DSI_TCCR1_HSRD_TOCNT12        DSI_TCCR1_HSRD_TOCNT12_Msk\n#define DSI_TCCR1_HSRD_TOCNT13_Pos    (13U)\n#define DSI_TCCR1_HSRD_TOCNT13_Msk    (0x1U << DSI_TCCR1_HSRD_TOCNT13_Pos)     /*!< 0x00002000 */\n#define DSI_TCCR1_HSRD_TOCNT13        DSI_TCCR1_HSRD_TOCNT13_Msk\n#define DSI_TCCR1_HSRD_TOCNT14_Pos    (14U)\n#define DSI_TCCR1_HSRD_TOCNT14_Msk    (0x1U << DSI_TCCR1_HSRD_TOCNT14_Pos)     /*!< 0x00004000 */\n#define DSI_TCCR1_HSRD_TOCNT14        DSI_TCCR1_HSRD_TOCNT14_Msk\n#define DSI_TCCR1_HSRD_TOCNT15_Pos    (15U)\n#define DSI_TCCR1_HSRD_TOCNT15_Msk    (0x1U << DSI_TCCR1_HSRD_TOCNT15_Pos)     /*!< 0x00008000 */\n#define DSI_TCCR1_HSRD_TOCNT15        DSI_TCCR1_HSRD_TOCNT15_Msk\n\n/*******************  Bit definition for DSI_TCCR2 register  **************/\n#define DSI_TCCR2_LPRD_TOCNT_Pos      (0U)\n#define DSI_TCCR2_LPRD_TOCNT_Msk      (0xFFFFU << DSI_TCCR2_LPRD_TOCNT_Pos)    /*!< 0x0000FFFF */\n#define DSI_TCCR2_LPRD_TOCNT          DSI_TCCR2_LPRD_TOCNT_Msk                 /*!< Low-Power Read Timeout Counter */\n#define DSI_TCCR2_LPRD_TOCNT0_Pos     (0U)\n#define DSI_TCCR2_LPRD_TOCNT0_Msk     (0x1U << DSI_TCCR2_LPRD_TOCNT0_Pos)      /*!< 0x00000001 */\n#define DSI_TCCR2_LPRD_TOCNT0         DSI_TCCR2_LPRD_TOCNT0_Msk\n#define DSI_TCCR2_LPRD_TOCNT1_Pos     (1U)\n#define DSI_TCCR2_LPRD_TOCNT1_Msk     (0x1U << DSI_TCCR2_LPRD_TOCNT1_Pos)      /*!< 0x00000002 */\n#define DSI_TCCR2_LPRD_TOCNT1         DSI_TCCR2_LPRD_TOCNT1_Msk\n#define DSI_TCCR2_LPRD_TOCNT2_Pos     (2U)\n#define DSI_TCCR2_LPRD_TOCNT2_Msk     (0x1U << DSI_TCCR2_LPRD_TOCNT2_Pos)      /*!< 0x00000004 */\n#define DSI_TCCR2_LPRD_TOCNT2         DSI_TCCR2_LPRD_TOCNT2_Msk\n#define DSI_TCCR2_LPRD_TOCNT3_Pos     (3U)\n#define DSI_TCCR2_LPRD_TOCNT3_Msk     (0x1U << DSI_TCCR2_LPRD_TOCNT3_Pos)      /*!< 0x00000008 */\n#define DSI_TCCR2_LPRD_TOCNT3         DSI_TCCR2_LPRD_TOCNT3_Msk\n#define DSI_TCCR2_LPRD_TOCNT4_Pos     (4U)\n#define DSI_TCCR2_LPRD_TOCNT4_Msk     (0x1U << DSI_TCCR2_LPRD_TOCNT4_Pos)      /*!< 0x00000010 */\n#define DSI_TCCR2_LPRD_TOCNT4         DSI_TCCR2_LPRD_TOCNT4_Msk\n#define DSI_TCCR2_LPRD_TOCNT5_Pos     (5U)\n#define DSI_TCCR2_LPRD_TOCNT5_Msk     (0x1U << DSI_TCCR2_LPRD_TOCNT5_Pos)      /*!< 0x00000020 */\n#define DSI_TCCR2_LPRD_TOCNT5         DSI_TCCR2_LPRD_TOCNT5_Msk\n#define DSI_TCCR2_LPRD_TOCNT6_Pos     (6U)\n#define DSI_TCCR2_LPRD_TOCNT6_Msk     (0x1U << DSI_TCCR2_LPRD_TOCNT6_Pos)      /*!< 0x00000040 */\n#define DSI_TCCR2_LPRD_TOCNT6         DSI_TCCR2_LPRD_TOCNT6_Msk\n#define DSI_TCCR2_LPRD_TOCNT7_Pos     (7U)\n#define DSI_TCCR2_LPRD_TOCNT7_Msk     (0x1U << DSI_TCCR2_LPRD_TOCNT7_Pos)      /*!< 0x00000080 */\n#define DSI_TCCR2_LPRD_TOCNT7         DSI_TCCR2_LPRD_TOCNT7_Msk\n#define DSI_TCCR2_LPRD_TOCNT8_Pos     (8U)\n#define DSI_TCCR2_LPRD_TOCNT8_Msk     (0x1U << DSI_TCCR2_LPRD_TOCNT8_Pos)      /*!< 0x00000100 */\n#define DSI_TCCR2_LPRD_TOCNT8         DSI_TCCR2_LPRD_TOCNT8_Msk\n#define DSI_TCCR2_LPRD_TOCNT9_Pos     (9U)\n#define DSI_TCCR2_LPRD_TOCNT9_Msk     (0x1U << DSI_TCCR2_LPRD_TOCNT9_Pos)      /*!< 0x00000200 */\n#define DSI_TCCR2_LPRD_TOCNT9         DSI_TCCR2_LPRD_TOCNT9_Msk\n#define DSI_TCCR2_LPRD_TOCNT10_Pos    (10U)\n#define DSI_TCCR2_LPRD_TOCNT10_Msk    (0x1U << DSI_TCCR2_LPRD_TOCNT10_Pos)     /*!< 0x00000400 */\n#define DSI_TCCR2_LPRD_TOCNT10        DSI_TCCR2_LPRD_TOCNT10_Msk\n#define DSI_TCCR2_LPRD_TOCNT11_Pos    (11U)\n#define DSI_TCCR2_LPRD_TOCNT11_Msk    (0x1U << DSI_TCCR2_LPRD_TOCNT11_Pos)     /*!< 0x00000800 */\n#define DSI_TCCR2_LPRD_TOCNT11        DSI_TCCR2_LPRD_TOCNT11_Msk\n#define DSI_TCCR2_LPRD_TOCNT12_Pos    (12U)\n#define DSI_TCCR2_LPRD_TOCNT12_Msk    (0x1U << DSI_TCCR2_LPRD_TOCNT12_Pos)     /*!< 0x00001000 */\n#define DSI_TCCR2_LPRD_TOCNT12        DSI_TCCR2_LPRD_TOCNT12_Msk\n#define DSI_TCCR2_LPRD_TOCNT13_Pos    (13U)\n#define DSI_TCCR2_LPRD_TOCNT13_Msk    (0x1U << DSI_TCCR2_LPRD_TOCNT13_Pos)     /*!< 0x00002000 */\n#define DSI_TCCR2_LPRD_TOCNT13        DSI_TCCR2_LPRD_TOCNT13_Msk\n#define DSI_TCCR2_LPRD_TOCNT14_Pos    (14U)\n#define DSI_TCCR2_LPRD_TOCNT14_Msk    (0x1U << DSI_TCCR2_LPRD_TOCNT14_Pos)     /*!< 0x00004000 */\n#define DSI_TCCR2_LPRD_TOCNT14        DSI_TCCR2_LPRD_TOCNT14_Msk\n#define DSI_TCCR2_LPRD_TOCNT15_Pos    (15U)\n#define DSI_TCCR2_LPRD_TOCNT15_Msk    (0x1U << DSI_TCCR2_LPRD_TOCNT15_Pos)     /*!< 0x00008000 */\n#define DSI_TCCR2_LPRD_TOCNT15        DSI_TCCR2_LPRD_TOCNT15_Msk\n\n/*******************  Bit definition for DSI_TCCR3 register  **************/\n#define DSI_TCCR3_HSWR_TOCNT_Pos      (0U)\n#define DSI_TCCR3_HSWR_TOCNT_Msk      (0xFFFFU << DSI_TCCR3_HSWR_TOCNT_Pos)    /*!< 0x0000FFFF */\n#define DSI_TCCR3_HSWR_TOCNT          DSI_TCCR3_HSWR_TOCNT_Msk                 /*!< High-Speed Write Timeout Counter */\n#define DSI_TCCR3_HSWR_TOCNT0_Pos     (0U)\n#define DSI_TCCR3_HSWR_TOCNT0_Msk     (0x1U << DSI_TCCR3_HSWR_TOCNT0_Pos)      /*!< 0x00000001 */\n#define DSI_TCCR3_HSWR_TOCNT0         DSI_TCCR3_HSWR_TOCNT0_Msk\n#define DSI_TCCR3_HSWR_TOCNT1_Pos     (1U)\n#define DSI_TCCR3_HSWR_TOCNT1_Msk     (0x1U << DSI_TCCR3_HSWR_TOCNT1_Pos)      /*!< 0x00000002 */\n#define DSI_TCCR3_HSWR_TOCNT1         DSI_TCCR3_HSWR_TOCNT1_Msk\n#define DSI_TCCR3_HSWR_TOCNT2_Pos     (2U)\n#define DSI_TCCR3_HSWR_TOCNT2_Msk     (0x1U << DSI_TCCR3_HSWR_TOCNT2_Pos)      /*!< 0x00000004 */\n#define DSI_TCCR3_HSWR_TOCNT2         DSI_TCCR3_HSWR_TOCNT2_Msk\n#define DSI_TCCR3_HSWR_TOCNT3_Pos     (3U)\n#define DSI_TCCR3_HSWR_TOCNT3_Msk     (0x1U << DSI_TCCR3_HSWR_TOCNT3_Pos)      /*!< 0x00000008 */\n#define DSI_TCCR3_HSWR_TOCNT3         DSI_TCCR3_HSWR_TOCNT3_Msk\n#define DSI_TCCR3_HSWR_TOCNT4_Pos     (4U)\n#define DSI_TCCR3_HSWR_TOCNT4_Msk     (0x1U << DSI_TCCR3_HSWR_TOCNT4_Pos)      /*!< 0x00000010 */\n#define DSI_TCCR3_HSWR_TOCNT4         DSI_TCCR3_HSWR_TOCNT4_Msk\n#define DSI_TCCR3_HSWR_TOCNT5_Pos     (5U)\n#define DSI_TCCR3_HSWR_TOCNT5_Msk     (0x1U << DSI_TCCR3_HSWR_TOCNT5_Pos)      /*!< 0x00000020 */\n#define DSI_TCCR3_HSWR_TOCNT5         DSI_TCCR3_HSWR_TOCNT5_Msk\n#define DSI_TCCR3_HSWR_TOCNT6_Pos     (6U)\n#define DSI_TCCR3_HSWR_TOCNT6_Msk     (0x1U << DSI_TCCR3_HSWR_TOCNT6_Pos)      /*!< 0x00000040 */\n#define DSI_TCCR3_HSWR_TOCNT6         DSI_TCCR3_HSWR_TOCNT6_Msk\n#define DSI_TCCR3_HSWR_TOCNT7_Pos     (7U)\n#define DSI_TCCR3_HSWR_TOCNT7_Msk     (0x1U << DSI_TCCR3_HSWR_TOCNT7_Pos)      /*!< 0x00000080 */\n#define DSI_TCCR3_HSWR_TOCNT7         DSI_TCCR3_HSWR_TOCNT7_Msk\n#define DSI_TCCR3_HSWR_TOCNT8_Pos     (8U)\n#define DSI_TCCR3_HSWR_TOCNT8_Msk     (0x1U << DSI_TCCR3_HSWR_TOCNT8_Pos)      /*!< 0x00000100 */\n#define DSI_TCCR3_HSWR_TOCNT8         DSI_TCCR3_HSWR_TOCNT8_Msk\n#define DSI_TCCR3_HSWR_TOCNT9_Pos     (9U)\n#define DSI_TCCR3_HSWR_TOCNT9_Msk     (0x1U << DSI_TCCR3_HSWR_TOCNT9_Pos)      /*!< 0x00000200 */\n#define DSI_TCCR3_HSWR_TOCNT9         DSI_TCCR3_HSWR_TOCNT9_Msk\n#define DSI_TCCR3_HSWR_TOCNT10_Pos    (10U)\n#define DSI_TCCR3_HSWR_TOCNT10_Msk    (0x1U << DSI_TCCR3_HSWR_TOCNT10_Pos)     /*!< 0x00000400 */\n#define DSI_TCCR3_HSWR_TOCNT10        DSI_TCCR3_HSWR_TOCNT10_Msk\n#define DSI_TCCR3_HSWR_TOCNT11_Pos    (11U)\n#define DSI_TCCR3_HSWR_TOCNT11_Msk    (0x1U << DSI_TCCR3_HSWR_TOCNT11_Pos)     /*!< 0x00000800 */\n#define DSI_TCCR3_HSWR_TOCNT11        DSI_TCCR3_HSWR_TOCNT11_Msk\n#define DSI_TCCR3_HSWR_TOCNT12_Pos    (12U)\n#define DSI_TCCR3_HSWR_TOCNT12_Msk    (0x1U << DSI_TCCR3_HSWR_TOCNT12_Pos)     /*!< 0x00001000 */\n#define DSI_TCCR3_HSWR_TOCNT12        DSI_TCCR3_HSWR_TOCNT12_Msk\n#define DSI_TCCR3_HSWR_TOCNT13_Pos    (13U)\n#define DSI_TCCR3_HSWR_TOCNT13_Msk    (0x1U << DSI_TCCR3_HSWR_TOCNT13_Pos)     /*!< 0x00002000 */\n#define DSI_TCCR3_HSWR_TOCNT13        DSI_TCCR3_HSWR_TOCNT13_Msk\n#define DSI_TCCR3_HSWR_TOCNT14_Pos    (14U)\n#define DSI_TCCR3_HSWR_TOCNT14_Msk    (0x1U << DSI_TCCR3_HSWR_TOCNT14_Pos)     /*!< 0x00004000 */\n#define DSI_TCCR3_HSWR_TOCNT14        DSI_TCCR3_HSWR_TOCNT14_Msk\n#define DSI_TCCR3_HSWR_TOCNT15_Pos    (15U)\n#define DSI_TCCR3_HSWR_TOCNT15_Msk    (0x1U << DSI_TCCR3_HSWR_TOCNT15_Pos)     /*!< 0x00008000 */\n#define DSI_TCCR3_HSWR_TOCNT15        DSI_TCCR3_HSWR_TOCNT15_Msk\n\n#define DSI_TCCR3_PM_Pos              (24U)\n#define DSI_TCCR3_PM_Msk              (0x1U << DSI_TCCR3_PM_Pos)               /*!< 0x01000000 */\n#define DSI_TCCR3_PM                  DSI_TCCR3_PM_Msk                         /*!< Presp Mode */\n\n/*******************  Bit definition for DSI_TCCR4 register  **************/\n#define DSI_TCCR4_LPWR_TOCNT_Pos      (0U)\n#define DSI_TCCR4_LPWR_TOCNT_Msk      (0xFFFFU << DSI_TCCR4_LPWR_TOCNT_Pos)    /*!< 0x0000FFFF */\n#define DSI_TCCR4_LPWR_TOCNT          DSI_TCCR4_LPWR_TOCNT_Msk                 /*!< Low-Power Write Timeout Counter */\n#define DSI_TCCR4_LPWR_TOCNT0_Pos     (0U)\n#define DSI_TCCR4_LPWR_TOCNT0_Msk     (0x1U << DSI_TCCR4_LPWR_TOCNT0_Pos)      /*!< 0x00000001 */\n#define DSI_TCCR4_LPWR_TOCNT0         DSI_TCCR4_LPWR_TOCNT0_Msk\n#define DSI_TCCR4_LPWR_TOCNT1_Pos     (1U)\n#define DSI_TCCR4_LPWR_TOCNT1_Msk     (0x1U << DSI_TCCR4_LPWR_TOCNT1_Pos)      /*!< 0x00000002 */\n#define DSI_TCCR4_LPWR_TOCNT1         DSI_TCCR4_LPWR_TOCNT1_Msk\n#define DSI_TCCR4_LPWR_TOCNT2_Pos     (2U)\n#define DSI_TCCR4_LPWR_TOCNT2_Msk     (0x1U << DSI_TCCR4_LPWR_TOCNT2_Pos)      /*!< 0x00000004 */\n#define DSI_TCCR4_LPWR_TOCNT2         DSI_TCCR4_LPWR_TOCNT2_Msk\n#define DSI_TCCR4_LPWR_TOCNT3_Pos     (3U)\n#define DSI_TCCR4_LPWR_TOCNT3_Msk     (0x1U << DSI_TCCR4_LPWR_TOCNT3_Pos)      /*!< 0x00000008 */\n#define DSI_TCCR4_LPWR_TOCNT3         DSI_TCCR4_LPWR_TOCNT3_Msk\n#define DSI_TCCR4_LPWR_TOCNT4_Pos     (4U)\n#define DSI_TCCR4_LPWR_TOCNT4_Msk     (0x1U << DSI_TCCR4_LPWR_TOCNT4_Pos)      /*!< 0x00000010 */\n#define DSI_TCCR4_LPWR_TOCNT4         DSI_TCCR4_LPWR_TOCNT4_Msk\n#define DSI_TCCR4_LPWR_TOCNT5_Pos     (5U)\n#define DSI_TCCR4_LPWR_TOCNT5_Msk     (0x1U << DSI_TCCR4_LPWR_TOCNT5_Pos)      /*!< 0x00000020 */\n#define DSI_TCCR4_LPWR_TOCNT5         DSI_TCCR4_LPWR_TOCNT5_Msk\n#define DSI_TCCR4_LPWR_TOCNT6_Pos     (6U)\n#define DSI_TCCR4_LPWR_TOCNT6_Msk     (0x1U << DSI_TCCR4_LPWR_TOCNT6_Pos)      /*!< 0x00000040 */\n#define DSI_TCCR4_LPWR_TOCNT6         DSI_TCCR4_LPWR_TOCNT6_Msk\n#define DSI_TCCR4_LPWR_TOCNT7_Pos     (7U)\n#define DSI_TCCR4_LPWR_TOCNT7_Msk     (0x1U << DSI_TCCR4_LPWR_TOCNT7_Pos)      /*!< 0x00000080 */\n#define DSI_TCCR4_LPWR_TOCNT7         DSI_TCCR4_LPWR_TOCNT7_Msk\n#define DSI_TCCR4_LPWR_TOCNT8_Pos     (8U)\n#define DSI_TCCR4_LPWR_TOCNT8_Msk     (0x1U << DSI_TCCR4_LPWR_TOCNT8_Pos)      /*!< 0x00000100 */\n#define DSI_TCCR4_LPWR_TOCNT8         DSI_TCCR4_LPWR_TOCNT8_Msk\n#define DSI_TCCR4_LPWR_TOCNT9_Pos     (9U)\n#define DSI_TCCR4_LPWR_TOCNT9_Msk     (0x1U << DSI_TCCR4_LPWR_TOCNT9_Pos)      /*!< 0x00000200 */\n#define DSI_TCCR4_LPWR_TOCNT9         DSI_TCCR4_LPWR_TOCNT9_Msk\n#define DSI_TCCR4_LPWR_TOCNT10_Pos    (10U)\n#define DSI_TCCR4_LPWR_TOCNT10_Msk    (0x1U << DSI_TCCR4_LPWR_TOCNT10_Pos)     /*!< 0x00000400 */\n#define DSI_TCCR4_LPWR_TOCNT10        DSI_TCCR4_LPWR_TOCNT10_Msk\n#define DSI_TCCR4_LPWR_TOCNT11_Pos    (11U)\n#define DSI_TCCR4_LPWR_TOCNT11_Msk    (0x1U << DSI_TCCR4_LPWR_TOCNT11_Pos)     /*!< 0x00000800 */\n#define DSI_TCCR4_LPWR_TOCNT11        DSI_TCCR4_LPWR_TOCNT11_Msk\n#define DSI_TCCR4_LPWR_TOCNT12_Pos    (12U)\n#define DSI_TCCR4_LPWR_TOCNT12_Msk    (0x1U << DSI_TCCR4_LPWR_TOCNT12_Pos)     /*!< 0x00001000 */\n#define DSI_TCCR4_LPWR_TOCNT12        DSI_TCCR4_LPWR_TOCNT12_Msk\n#define DSI_TCCR4_LPWR_TOCNT13_Pos    (13U)\n#define DSI_TCCR4_LPWR_TOCNT13_Msk    (0x1U << DSI_TCCR4_LPWR_TOCNT13_Pos)     /*!< 0x00002000 */\n#define DSI_TCCR4_LPWR_TOCNT13        DSI_TCCR4_LPWR_TOCNT13_Msk\n#define DSI_TCCR4_LPWR_TOCNT14_Pos    (14U)\n#define DSI_TCCR4_LPWR_TOCNT14_Msk    (0x1U << DSI_TCCR4_LPWR_TOCNT14_Pos)     /*!< 0x00004000 */\n#define DSI_TCCR4_LPWR_TOCNT14        DSI_TCCR4_LPWR_TOCNT14_Msk\n#define DSI_TCCR4_LPWR_TOCNT15_Pos    (15U)\n#define DSI_TCCR4_LPWR_TOCNT15_Msk    (0x1U << DSI_TCCR4_LPWR_TOCNT15_Pos)     /*!< 0x00008000 */\n#define DSI_TCCR4_LPWR_TOCNT15        DSI_TCCR4_LPWR_TOCNT15_Msk\n\n/*******************  Bit definition for DSI_TCCR5 register  **************/\n#define DSI_TCCR5_BTA_TOCNT_Pos       (0U)\n#define DSI_TCCR5_BTA_TOCNT_Msk       (0xFFFFU << DSI_TCCR5_BTA_TOCNT_Pos)     /*!< 0x0000FFFF */\n#define DSI_TCCR5_BTA_TOCNT           DSI_TCCR5_BTA_TOCNT_Msk                  /*!< Bus-Turn-Around Timeout Counter */\n#define DSI_TCCR5_BTA_TOCNT0_Pos      (0U)\n#define DSI_TCCR5_BTA_TOCNT0_Msk      (0x1U << DSI_TCCR5_BTA_TOCNT0_Pos)       /*!< 0x00000001 */\n#define DSI_TCCR5_BTA_TOCNT0          DSI_TCCR5_BTA_TOCNT0_Msk\n#define DSI_TCCR5_BTA_TOCNT1_Pos      (1U)\n#define DSI_TCCR5_BTA_TOCNT1_Msk      (0x1U << DSI_TCCR5_BTA_TOCNT1_Pos)       /*!< 0x00000002 */\n#define DSI_TCCR5_BTA_TOCNT1          DSI_TCCR5_BTA_TOCNT1_Msk\n#define DSI_TCCR5_BTA_TOCNT2_Pos      (2U)\n#define DSI_TCCR5_BTA_TOCNT2_Msk      (0x1U << DSI_TCCR5_BTA_TOCNT2_Pos)       /*!< 0x00000004 */\n#define DSI_TCCR5_BTA_TOCNT2          DSI_TCCR5_BTA_TOCNT2_Msk\n#define DSI_TCCR5_BTA_TOCNT3_Pos      (3U)\n#define DSI_TCCR5_BTA_TOCNT3_Msk      (0x1U << DSI_TCCR5_BTA_TOCNT3_Pos)       /*!< 0x00000008 */\n#define DSI_TCCR5_BTA_TOCNT3          DSI_TCCR5_BTA_TOCNT3_Msk\n#define DSI_TCCR5_BTA_TOCNT4_Pos      (4U)\n#define DSI_TCCR5_BTA_TOCNT4_Msk      (0x1U << DSI_TCCR5_BTA_TOCNT4_Pos)       /*!< 0x00000010 */\n#define DSI_TCCR5_BTA_TOCNT4          DSI_TCCR5_BTA_TOCNT4_Msk\n#define DSI_TCCR5_BTA_TOCNT5_Pos      (5U)\n#define DSI_TCCR5_BTA_TOCNT5_Msk      (0x1U << DSI_TCCR5_BTA_TOCNT5_Pos)       /*!< 0x00000020 */\n#define DSI_TCCR5_BTA_TOCNT5          DSI_TCCR5_BTA_TOCNT5_Msk\n#define DSI_TCCR5_BTA_TOCNT6_Pos      (6U)\n#define DSI_TCCR5_BTA_TOCNT6_Msk      (0x1U << DSI_TCCR5_BTA_TOCNT6_Pos)       /*!< 0x00000040 */\n#define DSI_TCCR5_BTA_TOCNT6          DSI_TCCR5_BTA_TOCNT6_Msk\n#define DSI_TCCR5_BTA_TOCNT7_Pos      (7U)\n#define DSI_TCCR5_BTA_TOCNT7_Msk      (0x1U << DSI_TCCR5_BTA_TOCNT7_Pos)       /*!< 0x00000080 */\n#define DSI_TCCR5_BTA_TOCNT7          DSI_TCCR5_BTA_TOCNT7_Msk\n#define DSI_TCCR5_BTA_TOCNT8_Pos      (8U)\n#define DSI_TCCR5_BTA_TOCNT8_Msk      (0x1U << DSI_TCCR5_BTA_TOCNT8_Pos)       /*!< 0x00000100 */\n#define DSI_TCCR5_BTA_TOCNT8          DSI_TCCR5_BTA_TOCNT8_Msk\n#define DSI_TCCR5_BTA_TOCNT9_Pos      (9U)\n#define DSI_TCCR5_BTA_TOCNT9_Msk      (0x1U << DSI_TCCR5_BTA_TOCNT9_Pos)       /*!< 0x00000200 */\n#define DSI_TCCR5_BTA_TOCNT9          DSI_TCCR5_BTA_TOCNT9_Msk\n#define DSI_TCCR5_BTA_TOCNT10_Pos     (10U)\n#define DSI_TCCR5_BTA_TOCNT10_Msk     (0x1U << DSI_TCCR5_BTA_TOCNT10_Pos)      /*!< 0x00000400 */\n#define DSI_TCCR5_BTA_TOCNT10         DSI_TCCR5_BTA_TOCNT10_Msk\n#define DSI_TCCR5_BTA_TOCNT11_Pos     (11U)\n#define DSI_TCCR5_BTA_TOCNT11_Msk     (0x1U << DSI_TCCR5_BTA_TOCNT11_Pos)      /*!< 0x00000800 */\n#define DSI_TCCR5_BTA_TOCNT11         DSI_TCCR5_BTA_TOCNT11_Msk\n#define DSI_TCCR5_BTA_TOCNT12_Pos     (12U)\n#define DSI_TCCR5_BTA_TOCNT12_Msk     (0x1U << DSI_TCCR5_BTA_TOCNT12_Pos)      /*!< 0x00001000 */\n#define DSI_TCCR5_BTA_TOCNT12         DSI_TCCR5_BTA_TOCNT12_Msk\n#define DSI_TCCR5_BTA_TOCNT13_Pos     (13U)\n#define DSI_TCCR5_BTA_TOCNT13_Msk     (0x1U << DSI_TCCR5_BTA_TOCNT13_Pos)      /*!< 0x00002000 */\n#define DSI_TCCR5_BTA_TOCNT13         DSI_TCCR5_BTA_TOCNT13_Msk\n#define DSI_TCCR5_BTA_TOCNT14_Pos     (14U)\n#define DSI_TCCR5_BTA_TOCNT14_Msk     (0x1U << DSI_TCCR5_BTA_TOCNT14_Pos)      /*!< 0x00004000 */\n#define DSI_TCCR5_BTA_TOCNT14         DSI_TCCR5_BTA_TOCNT14_Msk\n#define DSI_TCCR5_BTA_TOCNT15_Pos     (15U)\n#define DSI_TCCR5_BTA_TOCNT15_Msk     (0x1U << DSI_TCCR5_BTA_TOCNT15_Pos)      /*!< 0x00008000 */\n#define DSI_TCCR5_BTA_TOCNT15         DSI_TCCR5_BTA_TOCNT15_Msk\n\n/*******************  Bit definition for DSI_TDCR register  ***************/\n#define DSI_TDCR_3DM                  0x00000003U                              /*!< 3D Mode */\n#define DSI_TDCR_3DM0                 0x00000001U\n#define DSI_TDCR_3DM1                 0x00000002U\n\n#define DSI_TDCR_3DF                  0x0000000CU                              /*!< 3D Format */\n#define DSI_TDCR_3DF0                 0x00000004U\n#define DSI_TDCR_3DF1                 0x00000008U\n\n#define DSI_TDCR_SVS_Pos              (4U)\n#define DSI_TDCR_SVS_Msk              (0x1U << DSI_TDCR_SVS_Pos)               /*!< 0x00000010 */\n#define DSI_TDCR_SVS                  DSI_TDCR_SVS_Msk                         /*!< Second VSYNC */\n#define DSI_TDCR_RF_Pos               (5U)\n#define DSI_TDCR_RF_Msk               (0x1U << DSI_TDCR_RF_Pos)                /*!< 0x00000020 */\n#define DSI_TDCR_RF                   DSI_TDCR_RF_Msk                          /*!< Right First */\n#define DSI_TDCR_S3DC_Pos             (16U)\n#define DSI_TDCR_S3DC_Msk             (0x1U << DSI_TDCR_S3DC_Pos)              /*!< 0x00010000 */\n#define DSI_TDCR_S3DC                 DSI_TDCR_S3DC_Msk                        /*!< Send 3D Control */\n\n/*******************  Bit definition for DSI_CLCR register  ***************/\n#define DSI_CLCR_DPCC_Pos             (0U)\n#define DSI_CLCR_DPCC_Msk             (0x1U << DSI_CLCR_DPCC_Pos)              /*!< 0x00000001 */\n#define DSI_CLCR_DPCC                 DSI_CLCR_DPCC_Msk                        /*!< D-PHY Clock Control */\n#define DSI_CLCR_ACR_Pos              (1U)\n#define DSI_CLCR_ACR_Msk              (0x1U << DSI_CLCR_ACR_Pos)               /*!< 0x00000002 */\n#define DSI_CLCR_ACR                  DSI_CLCR_ACR_Msk                         /*!< Automatic Clocklane Control */\n\n/*******************  Bit definition for DSI_CLTCR register  **************/\n#define DSI_CLTCR_LP2HS_TIME_Pos      (0U)\n#define DSI_CLTCR_LP2HS_TIME_Msk      (0x3FFU << DSI_CLTCR_LP2HS_TIME_Pos)     /*!< 0x000003FF */\n#define DSI_CLTCR_LP2HS_TIME          DSI_CLTCR_LP2HS_TIME_Msk                 /*!< Low-Power to High-Speed Time */\n#define DSI_CLTCR_LP2HS_TIME0_Pos     (0U)\n#define DSI_CLTCR_LP2HS_TIME0_Msk     (0x1U << DSI_CLTCR_LP2HS_TIME0_Pos)      /*!< 0x00000001 */\n#define DSI_CLTCR_LP2HS_TIME0         DSI_CLTCR_LP2HS_TIME0_Msk\n#define DSI_CLTCR_LP2HS_TIME1_Pos     (1U)\n#define DSI_CLTCR_LP2HS_TIME1_Msk     (0x1U << DSI_CLTCR_LP2HS_TIME1_Pos)      /*!< 0x00000002 */\n#define DSI_CLTCR_LP2HS_TIME1         DSI_CLTCR_LP2HS_TIME1_Msk\n#define DSI_CLTCR_LP2HS_TIME2_Pos     (2U)\n#define DSI_CLTCR_LP2HS_TIME2_Msk     (0x1U << DSI_CLTCR_LP2HS_TIME2_Pos)      /*!< 0x00000004 */\n#define DSI_CLTCR_LP2HS_TIME2         DSI_CLTCR_LP2HS_TIME2_Msk\n#define DSI_CLTCR_LP2HS_TIME3_Pos     (3U)\n#define DSI_CLTCR_LP2HS_TIME3_Msk     (0x1U << DSI_CLTCR_LP2HS_TIME3_Pos)      /*!< 0x00000008 */\n#define DSI_CLTCR_LP2HS_TIME3         DSI_CLTCR_LP2HS_TIME3_Msk\n#define DSI_CLTCR_LP2HS_TIME4_Pos     (4U)\n#define DSI_CLTCR_LP2HS_TIME4_Msk     (0x1U << DSI_CLTCR_LP2HS_TIME4_Pos)      /*!< 0x00000010 */\n#define DSI_CLTCR_LP2HS_TIME4         DSI_CLTCR_LP2HS_TIME4_Msk\n#define DSI_CLTCR_LP2HS_TIME5_Pos     (5U)\n#define DSI_CLTCR_LP2HS_TIME5_Msk     (0x1U << DSI_CLTCR_LP2HS_TIME5_Pos)      /*!< 0x00000020 */\n#define DSI_CLTCR_LP2HS_TIME5         DSI_CLTCR_LP2HS_TIME5_Msk\n#define DSI_CLTCR_LP2HS_TIME6_Pos     (6U)\n#define DSI_CLTCR_LP2HS_TIME6_Msk     (0x1U << DSI_CLTCR_LP2HS_TIME6_Pos)      /*!< 0x00000040 */\n#define DSI_CLTCR_LP2HS_TIME6         DSI_CLTCR_LP2HS_TIME6_Msk\n#define DSI_CLTCR_LP2HS_TIME7_Pos     (7U)\n#define DSI_CLTCR_LP2HS_TIME7_Msk     (0x1U << DSI_CLTCR_LP2HS_TIME7_Pos)      /*!< 0x00000080 */\n#define DSI_CLTCR_LP2HS_TIME7         DSI_CLTCR_LP2HS_TIME7_Msk\n#define DSI_CLTCR_LP2HS_TIME8_Pos     (8U)\n#define DSI_CLTCR_LP2HS_TIME8_Msk     (0x1U << DSI_CLTCR_LP2HS_TIME8_Pos)      /*!< 0x00000100 */\n#define DSI_CLTCR_LP2HS_TIME8         DSI_CLTCR_LP2HS_TIME8_Msk\n#define DSI_CLTCR_LP2HS_TIME9_Pos     (9U)\n#define DSI_CLTCR_LP2HS_TIME9_Msk     (0x1U << DSI_CLTCR_LP2HS_TIME9_Pos)      /*!< 0x00000200 */\n#define DSI_CLTCR_LP2HS_TIME9         DSI_CLTCR_LP2HS_TIME9_Msk\n\n#define DSI_CLTCR_HS2LP_TIME_Pos      (16U)\n#define DSI_CLTCR_HS2LP_TIME_Msk      (0x3FFU << DSI_CLTCR_HS2LP_TIME_Pos)     /*!< 0x03FF0000 */\n#define DSI_CLTCR_HS2LP_TIME          DSI_CLTCR_HS2LP_TIME_Msk                 /*!< High-Speed to Low-Power Time */\n#define DSI_CLTCR_HS2LP_TIME0_Pos     (16U)\n#define DSI_CLTCR_HS2LP_TIME0_Msk     (0x1U << DSI_CLTCR_HS2LP_TIME0_Pos)      /*!< 0x00010000 */\n#define DSI_CLTCR_HS2LP_TIME0         DSI_CLTCR_HS2LP_TIME0_Msk\n#define DSI_CLTCR_HS2LP_TIME1_Pos     (17U)\n#define DSI_CLTCR_HS2LP_TIME1_Msk     (0x1U << DSI_CLTCR_HS2LP_TIME1_Pos)      /*!< 0x00020000 */\n#define DSI_CLTCR_HS2LP_TIME1         DSI_CLTCR_HS2LP_TIME1_Msk\n#define DSI_CLTCR_HS2LP_TIME2_Pos     (18U)\n#define DSI_CLTCR_HS2LP_TIME2_Msk     (0x1U << DSI_CLTCR_HS2LP_TIME2_Pos)      /*!< 0x00040000 */\n#define DSI_CLTCR_HS2LP_TIME2         DSI_CLTCR_HS2LP_TIME2_Msk\n#define DSI_CLTCR_HS2LP_TIME3_Pos     (19U)\n#define DSI_CLTCR_HS2LP_TIME3_Msk     (0x1U << DSI_CLTCR_HS2LP_TIME3_Pos)      /*!< 0x00080000 */\n#define DSI_CLTCR_HS2LP_TIME3         DSI_CLTCR_HS2LP_TIME3_Msk\n#define DSI_CLTCR_HS2LP_TIME4_Pos     (20U)\n#define DSI_CLTCR_HS2LP_TIME4_Msk     (0x1U << DSI_CLTCR_HS2LP_TIME4_Pos)      /*!< 0x00100000 */\n#define DSI_CLTCR_HS2LP_TIME4         DSI_CLTCR_HS2LP_TIME4_Msk\n#define DSI_CLTCR_HS2LP_TIME5_Pos     (21U)\n#define DSI_CLTCR_HS2LP_TIME5_Msk     (0x1U << DSI_CLTCR_HS2LP_TIME5_Pos)      /*!< 0x00200000 */\n#define DSI_CLTCR_HS2LP_TIME5         DSI_CLTCR_HS2LP_TIME5_Msk\n#define DSI_CLTCR_HS2LP_TIME6_Pos     (22U)\n#define DSI_CLTCR_HS2LP_TIME6_Msk     (0x1U << DSI_CLTCR_HS2LP_TIME6_Pos)      /*!< 0x00400000 */\n#define DSI_CLTCR_HS2LP_TIME6         DSI_CLTCR_HS2LP_TIME6_Msk\n#define DSI_CLTCR_HS2LP_TIME7_Pos     (23U)\n#define DSI_CLTCR_HS2LP_TIME7_Msk     (0x1U << DSI_CLTCR_HS2LP_TIME7_Pos)      /*!< 0x00800000 */\n#define DSI_CLTCR_HS2LP_TIME7         DSI_CLTCR_HS2LP_TIME7_Msk\n#define DSI_CLTCR_HS2LP_TIME8_Pos     (24U)\n#define DSI_CLTCR_HS2LP_TIME8_Msk     (0x1U << DSI_CLTCR_HS2LP_TIME8_Pos)      /*!< 0x01000000 */\n#define DSI_CLTCR_HS2LP_TIME8         DSI_CLTCR_HS2LP_TIME8_Msk\n#define DSI_CLTCR_HS2LP_TIME9_Pos     (25U)\n#define DSI_CLTCR_HS2LP_TIME9_Msk     (0x1U << DSI_CLTCR_HS2LP_TIME9_Pos)      /*!< 0x02000000 */\n#define DSI_CLTCR_HS2LP_TIME9         DSI_CLTCR_HS2LP_TIME9_Msk\n\n/*******************  Bit definition for DSI_DLTCR register  **************/\n#define DSI_DLTCR_MRD_TIME_Pos        (0U)\n#define DSI_DLTCR_MRD_TIME_Msk        (0x7FFFU << DSI_DLTCR_MRD_TIME_Pos)      /*!< 0x00007FFF */\n#define DSI_DLTCR_MRD_TIME            DSI_DLTCR_MRD_TIME_Msk                   /*!< Maximum Read Time */\n#define DSI_DLTCR_MRD_TIME0_Pos       (0U)\n#define DSI_DLTCR_MRD_TIME0_Msk       (0x1U << DSI_DLTCR_MRD_TIME0_Pos)        /*!< 0x00000001 */\n#define DSI_DLTCR_MRD_TIME0           DSI_DLTCR_MRD_TIME0_Msk\n#define DSI_DLTCR_MRD_TIME1_Pos       (1U)\n#define DSI_DLTCR_MRD_TIME1_Msk       (0x1U << DSI_DLTCR_MRD_TIME1_Pos)        /*!< 0x00000002 */\n#define DSI_DLTCR_MRD_TIME1           DSI_DLTCR_MRD_TIME1_Msk\n#define DSI_DLTCR_MRD_TIME2_Pos       (2U)\n#define DSI_DLTCR_MRD_TIME2_Msk       (0x1U << DSI_DLTCR_MRD_TIME2_Pos)        /*!< 0x00000004 */\n#define DSI_DLTCR_MRD_TIME2           DSI_DLTCR_MRD_TIME2_Msk\n#define DSI_DLTCR_MRD_TIME3_Pos       (3U)\n#define DSI_DLTCR_MRD_TIME3_Msk       (0x1U << DSI_DLTCR_MRD_TIME3_Pos)        /*!< 0x00000008 */\n#define DSI_DLTCR_MRD_TIME3           DSI_DLTCR_MRD_TIME3_Msk\n#define DSI_DLTCR_MRD_TIME4_Pos       (4U)\n#define DSI_DLTCR_MRD_TIME4_Msk       (0x1U << DSI_DLTCR_MRD_TIME4_Pos)        /*!< 0x00000010 */\n#define DSI_DLTCR_MRD_TIME4           DSI_DLTCR_MRD_TIME4_Msk\n#define DSI_DLTCR_MRD_TIME5_Pos       (5U)\n#define DSI_DLTCR_MRD_TIME5_Msk       (0x1U << DSI_DLTCR_MRD_TIME5_Pos)        /*!< 0x00000020 */\n#define DSI_DLTCR_MRD_TIME5           DSI_DLTCR_MRD_TIME5_Msk\n#define DSI_DLTCR_MRD_TIME6_Pos       (6U)\n#define DSI_DLTCR_MRD_TIME6_Msk       (0x1U << DSI_DLTCR_MRD_TIME6_Pos)        /*!< 0x00000040 */\n#define DSI_DLTCR_MRD_TIME6           DSI_DLTCR_MRD_TIME6_Msk\n#define DSI_DLTCR_MRD_TIME7_Pos       (7U)\n#define DSI_DLTCR_MRD_TIME7_Msk       (0x1U << DSI_DLTCR_MRD_TIME7_Pos)        /*!< 0x00000080 */\n#define DSI_DLTCR_MRD_TIME7           DSI_DLTCR_MRD_TIME7_Msk\n#define DSI_DLTCR_MRD_TIME8_Pos       (8U)\n#define DSI_DLTCR_MRD_TIME8_Msk       (0x1U << DSI_DLTCR_MRD_TIME8_Pos)        /*!< 0x00000100 */\n#define DSI_DLTCR_MRD_TIME8           DSI_DLTCR_MRD_TIME8_Msk\n#define DSI_DLTCR_MRD_TIME9_Pos       (9U)\n#define DSI_DLTCR_MRD_TIME9_Msk       (0x1U << DSI_DLTCR_MRD_TIME9_Pos)        /*!< 0x00000200 */\n#define DSI_DLTCR_MRD_TIME9           DSI_DLTCR_MRD_TIME9_Msk\n#define DSI_DLTCR_MRD_TIME10_Pos      (10U)\n#define DSI_DLTCR_MRD_TIME10_Msk      (0x1U << DSI_DLTCR_MRD_TIME10_Pos)       /*!< 0x00000400 */\n#define DSI_DLTCR_MRD_TIME10          DSI_DLTCR_MRD_TIME10_Msk\n#define DSI_DLTCR_MRD_TIME11_Pos      (11U)\n#define DSI_DLTCR_MRD_TIME11_Msk      (0x1U << DSI_DLTCR_MRD_TIME11_Pos)       /*!< 0x00000800 */\n#define DSI_DLTCR_MRD_TIME11          DSI_DLTCR_MRD_TIME11_Msk\n#define DSI_DLTCR_MRD_TIME12_Pos      (12U)\n#define DSI_DLTCR_MRD_TIME12_Msk      (0x1U << DSI_DLTCR_MRD_TIME12_Pos)       /*!< 0x00001000 */\n#define DSI_DLTCR_MRD_TIME12          DSI_DLTCR_MRD_TIME12_Msk\n#define DSI_DLTCR_MRD_TIME13_Pos      (13U)\n#define DSI_DLTCR_MRD_TIME13_Msk      (0x1U << DSI_DLTCR_MRD_TIME13_Pos)       /*!< 0x00002000 */\n#define DSI_DLTCR_MRD_TIME13          DSI_DLTCR_MRD_TIME13_Msk\n#define DSI_DLTCR_MRD_TIME14_Pos      (14U)\n#define DSI_DLTCR_MRD_TIME14_Msk      (0x1U << DSI_DLTCR_MRD_TIME14_Pos)       /*!< 0x00004000 */\n#define DSI_DLTCR_MRD_TIME14          DSI_DLTCR_MRD_TIME14_Msk\n\n#define DSI_DLTCR_LP2HS_TIME_Pos      (16U)\n#define DSI_DLTCR_LP2HS_TIME_Msk      (0xFFU << DSI_DLTCR_LP2HS_TIME_Pos)      /*!< 0x00FF0000 */\n#define DSI_DLTCR_LP2HS_TIME          DSI_DLTCR_LP2HS_TIME_Msk                 /*!< Low-Power To High-Speed Time */\n#define DSI_DLTCR_LP2HS_TIME0_Pos     (16U)\n#define DSI_DLTCR_LP2HS_TIME0_Msk     (0x1U << DSI_DLTCR_LP2HS_TIME0_Pos)      /*!< 0x00010000 */\n#define DSI_DLTCR_LP2HS_TIME0         DSI_DLTCR_LP2HS_TIME0_Msk\n#define DSI_DLTCR_LP2HS_TIME1_Pos     (17U)\n#define DSI_DLTCR_LP2HS_TIME1_Msk     (0x1U << DSI_DLTCR_LP2HS_TIME1_Pos)      /*!< 0x00020000 */\n#define DSI_DLTCR_LP2HS_TIME1         DSI_DLTCR_LP2HS_TIME1_Msk\n#define DSI_DLTCR_LP2HS_TIME2_Pos     (18U)\n#define DSI_DLTCR_LP2HS_TIME2_Msk     (0x1U << DSI_DLTCR_LP2HS_TIME2_Pos)      /*!< 0x00040000 */\n#define DSI_DLTCR_LP2HS_TIME2         DSI_DLTCR_LP2HS_TIME2_Msk\n#define DSI_DLTCR_LP2HS_TIME3_Pos     (19U)\n#define DSI_DLTCR_LP2HS_TIME3_Msk     (0x1U << DSI_DLTCR_LP2HS_TIME3_Pos)      /*!< 0x00080000 */\n#define DSI_DLTCR_LP2HS_TIME3         DSI_DLTCR_LP2HS_TIME3_Msk\n#define DSI_DLTCR_LP2HS_TIME4_Pos     (20U)\n#define DSI_DLTCR_LP2HS_TIME4_Msk     (0x1U << DSI_DLTCR_LP2HS_TIME4_Pos)      /*!< 0x00100000 */\n#define DSI_DLTCR_LP2HS_TIME4         DSI_DLTCR_LP2HS_TIME4_Msk\n#define DSI_DLTCR_LP2HS_TIME5_Pos     (21U)\n#define DSI_DLTCR_LP2HS_TIME5_Msk     (0x1U << DSI_DLTCR_LP2HS_TIME5_Pos)      /*!< 0x00200000 */\n#define DSI_DLTCR_LP2HS_TIME5         DSI_DLTCR_LP2HS_TIME5_Msk\n#define DSI_DLTCR_LP2HS_TIME6_Pos     (22U)\n#define DSI_DLTCR_LP2HS_TIME6_Msk     (0x1U << DSI_DLTCR_LP2HS_TIME6_Pos)      /*!< 0x00400000 */\n#define DSI_DLTCR_LP2HS_TIME6         DSI_DLTCR_LP2HS_TIME6_Msk\n#define DSI_DLTCR_LP2HS_TIME7_Pos     (23U)\n#define DSI_DLTCR_LP2HS_TIME7_Msk     (0x1U << DSI_DLTCR_LP2HS_TIME7_Pos)      /*!< 0x00800000 */\n#define DSI_DLTCR_LP2HS_TIME7         DSI_DLTCR_LP2HS_TIME7_Msk\n\n#define DSI_DLTCR_HS2LP_TIME_Pos      (24U)\n#define DSI_DLTCR_HS2LP_TIME_Msk      (0xFFU << DSI_DLTCR_HS2LP_TIME_Pos)      /*!< 0xFF000000 */\n#define DSI_DLTCR_HS2LP_TIME          DSI_DLTCR_HS2LP_TIME_Msk                 /*!< High-Speed To Low-Power Time */\n#define DSI_DLTCR_HS2LP_TIME0_Pos     (24U)\n#define DSI_DLTCR_HS2LP_TIME0_Msk     (0x1U << DSI_DLTCR_HS2LP_TIME0_Pos)      /*!< 0x01000000 */\n#define DSI_DLTCR_HS2LP_TIME0         DSI_DLTCR_HS2LP_TIME0_Msk\n#define DSI_DLTCR_HS2LP_TIME1_Pos     (25U)\n#define DSI_DLTCR_HS2LP_TIME1_Msk     (0x1U << DSI_DLTCR_HS2LP_TIME1_Pos)      /*!< 0x02000000 */\n#define DSI_DLTCR_HS2LP_TIME1         DSI_DLTCR_HS2LP_TIME1_Msk\n#define DSI_DLTCR_HS2LP_TIME2_Pos     (26U)\n#define DSI_DLTCR_HS2LP_TIME2_Msk     (0x1U << DSI_DLTCR_HS2LP_TIME2_Pos)      /*!< 0x04000000 */\n#define DSI_DLTCR_HS2LP_TIME2         DSI_DLTCR_HS2LP_TIME2_Msk\n#define DSI_DLTCR_HS2LP_TIME3_Pos     (27U)\n#define DSI_DLTCR_HS2LP_TIME3_Msk     (0x1U << DSI_DLTCR_HS2LP_TIME3_Pos)      /*!< 0x08000000 */\n#define DSI_DLTCR_HS2LP_TIME3         DSI_DLTCR_HS2LP_TIME3_Msk\n#define DSI_DLTCR_HS2LP_TIME4_Pos     (28U)\n#define DSI_DLTCR_HS2LP_TIME4_Msk     (0x1U << DSI_DLTCR_HS2LP_TIME4_Pos)      /*!< 0x10000000 */\n#define DSI_DLTCR_HS2LP_TIME4         DSI_DLTCR_HS2LP_TIME4_Msk\n#define DSI_DLTCR_HS2LP_TIME5_Pos     (29U)\n#define DSI_DLTCR_HS2LP_TIME5_Msk     (0x1U << DSI_DLTCR_HS2LP_TIME5_Pos)      /*!< 0x20000000 */\n#define DSI_DLTCR_HS2LP_TIME5         DSI_DLTCR_HS2LP_TIME5_Msk\n#define DSI_DLTCR_HS2LP_TIME6_Pos     (30U)\n#define DSI_DLTCR_HS2LP_TIME6_Msk     (0x1U << DSI_DLTCR_HS2LP_TIME6_Pos)      /*!< 0x40000000 */\n#define DSI_DLTCR_HS2LP_TIME6         DSI_DLTCR_HS2LP_TIME6_Msk\n#define DSI_DLTCR_HS2LP_TIME7_Pos     (31U)\n#define DSI_DLTCR_HS2LP_TIME7_Msk     (0x1U << DSI_DLTCR_HS2LP_TIME7_Pos)      /*!< 0x80000000 */\n#define DSI_DLTCR_HS2LP_TIME7         DSI_DLTCR_HS2LP_TIME7_Msk\n\n/*******************  Bit definition for DSI_PCTLR register  **************/\n#define DSI_PCTLR_DEN_Pos             (1U)\n#define DSI_PCTLR_DEN_Msk             (0x1U << DSI_PCTLR_DEN_Pos)              /*!< 0x00000002 */\n#define DSI_PCTLR_DEN                 DSI_PCTLR_DEN_Msk                        /*!< Digital Enable */\n#define DSI_PCTLR_CKE_Pos             (2U)\n#define DSI_PCTLR_CKE_Msk             (0x1U << DSI_PCTLR_CKE_Pos)              /*!< 0x00000004 */\n#define DSI_PCTLR_CKE                 DSI_PCTLR_CKE_Msk                        /*!< Clock Enable */\n\n/*******************  Bit definition for DSI_PCONFR register  *************/\n#define DSI_PCONFR_NL_Pos             (0U)\n#define DSI_PCONFR_NL_Msk             (0x3U << DSI_PCONFR_NL_Pos)              /*!< 0x00000003 */\n#define DSI_PCONFR_NL                 DSI_PCONFR_NL_Msk                        /*!< Number of Lanes */\n#define DSI_PCONFR_NL0_Pos            (0U)\n#define DSI_PCONFR_NL0_Msk            (0x1U << DSI_PCONFR_NL0_Pos)             /*!< 0x00000001 */\n#define DSI_PCONFR_NL0                DSI_PCONFR_NL0_Msk\n#define DSI_PCONFR_NL1_Pos            (1U)\n#define DSI_PCONFR_NL1_Msk            (0x1U << DSI_PCONFR_NL1_Pos)             /*!< 0x00000002 */\n#define DSI_PCONFR_NL1                DSI_PCONFR_NL1_Msk\n\n#define DSI_PCONFR_SW_TIME_Pos        (8U)\n#define DSI_PCONFR_SW_TIME_Msk        (0xFFU << DSI_PCONFR_SW_TIME_Pos)        /*!< 0x0000FF00 */\n#define DSI_PCONFR_SW_TIME            DSI_PCONFR_SW_TIME_Msk                   /*!< Stop Wait Time */\n#define DSI_PCONFR_SW_TIME0_Pos       (8U)\n#define DSI_PCONFR_SW_TIME0_Msk       (0x1U << DSI_PCONFR_SW_TIME0_Pos)        /*!< 0x00000100 */\n#define DSI_PCONFR_SW_TIME0           DSI_PCONFR_SW_TIME0_Msk\n#define DSI_PCONFR_SW_TIME1_Pos       (9U)\n#define DSI_PCONFR_SW_TIME1_Msk       (0x1U << DSI_PCONFR_SW_TIME1_Pos)        /*!< 0x00000200 */\n#define DSI_PCONFR_SW_TIME1           DSI_PCONFR_SW_TIME1_Msk\n#define DSI_PCONFR_SW_TIME2_Pos       (10U)\n#define DSI_PCONFR_SW_TIME2_Msk       (0x1U << DSI_PCONFR_SW_TIME2_Pos)        /*!< 0x00000400 */\n#define DSI_PCONFR_SW_TIME2           DSI_PCONFR_SW_TIME2_Msk\n#define DSI_PCONFR_SW_TIME3_Pos       (11U)\n#define DSI_PCONFR_SW_TIME3_Msk       (0x1U << DSI_PCONFR_SW_TIME3_Pos)        /*!< 0x00000800 */\n#define DSI_PCONFR_SW_TIME3           DSI_PCONFR_SW_TIME3_Msk\n#define DSI_PCONFR_SW_TIME4_Pos       (12U)\n#define DSI_PCONFR_SW_TIME4_Msk       (0x1U << DSI_PCONFR_SW_TIME4_Pos)        /*!< 0x00001000 */\n#define DSI_PCONFR_SW_TIME4           DSI_PCONFR_SW_TIME4_Msk\n#define DSI_PCONFR_SW_TIME5_Pos       (13U)\n#define DSI_PCONFR_SW_TIME5_Msk       (0x1U << DSI_PCONFR_SW_TIME5_Pos)        /*!< 0x00002000 */\n#define DSI_PCONFR_SW_TIME5           DSI_PCONFR_SW_TIME5_Msk\n#define DSI_PCONFR_SW_TIME6_Pos       (14U)\n#define DSI_PCONFR_SW_TIME6_Msk       (0x1U << DSI_PCONFR_SW_TIME6_Pos)        /*!< 0x00004000 */\n#define DSI_PCONFR_SW_TIME6           DSI_PCONFR_SW_TIME6_Msk\n#define DSI_PCONFR_SW_TIME7_Pos       (15U)\n#define DSI_PCONFR_SW_TIME7_Msk       (0x1U << DSI_PCONFR_SW_TIME7_Pos)        /*!< 0x00008000 */\n#define DSI_PCONFR_SW_TIME7           DSI_PCONFR_SW_TIME7_Msk\n\n/*******************  Bit definition for DSI_PUCR register  ***************/\n#define DSI_PUCR_URCL_Pos             (0U)\n#define DSI_PUCR_URCL_Msk             (0x1U << DSI_PUCR_URCL_Pos)              /*!< 0x00000001 */\n#define DSI_PUCR_URCL                 DSI_PUCR_URCL_Msk                        /*!< ULPS Request on Clock Lane */\n#define DSI_PUCR_UECL_Pos             (1U)\n#define DSI_PUCR_UECL_Msk             (0x1U << DSI_PUCR_UECL_Pos)              /*!< 0x00000002 */\n#define DSI_PUCR_UECL                 DSI_PUCR_UECL_Msk                        /*!< ULPS Exit on Clock Lane */\n#define DSI_PUCR_URDL_Pos             (2U)\n#define DSI_PUCR_URDL_Msk             (0x1U << DSI_PUCR_URDL_Pos)              /*!< 0x00000004 */\n#define DSI_PUCR_URDL                 DSI_PUCR_URDL_Msk                        /*!< ULPS Request on Data Lane */\n#define DSI_PUCR_UEDL_Pos             (3U)\n#define DSI_PUCR_UEDL_Msk             (0x1U << DSI_PUCR_UEDL_Pos)              /*!< 0x00000008 */\n#define DSI_PUCR_UEDL                 DSI_PUCR_UEDL_Msk                        /*!< ULPS Exit on Data Lane */\n\n/*******************  Bit definition for DSI_PTTCR register  **************/\n#define DSI_PTTCR_TX_TRIG_Pos         (0U)\n#define DSI_PTTCR_TX_TRIG_Msk         (0xFU << DSI_PTTCR_TX_TRIG_Pos)          /*!< 0x0000000F */\n#define DSI_PTTCR_TX_TRIG             DSI_PTTCR_TX_TRIG_Msk                    /*!< Transmission Trigger */\n#define DSI_PTTCR_TX_TRIG0_Pos        (0U)\n#define DSI_PTTCR_TX_TRIG0_Msk        (0x1U << DSI_PTTCR_TX_TRIG0_Pos)         /*!< 0x00000001 */\n#define DSI_PTTCR_TX_TRIG0            DSI_PTTCR_TX_TRIG0_Msk\n#define DSI_PTTCR_TX_TRIG1_Pos        (1U)\n#define DSI_PTTCR_TX_TRIG1_Msk        (0x1U << DSI_PTTCR_TX_TRIG1_Pos)         /*!< 0x00000002 */\n#define DSI_PTTCR_TX_TRIG1            DSI_PTTCR_TX_TRIG1_Msk\n#define DSI_PTTCR_TX_TRIG2_Pos        (2U)\n#define DSI_PTTCR_TX_TRIG2_Msk        (0x1U << DSI_PTTCR_TX_TRIG2_Pos)         /*!< 0x00000004 */\n#define DSI_PTTCR_TX_TRIG2            DSI_PTTCR_TX_TRIG2_Msk\n#define DSI_PTTCR_TX_TRIG3_Pos        (3U)\n#define DSI_PTTCR_TX_TRIG3_Msk        (0x1U << DSI_PTTCR_TX_TRIG3_Pos)         /*!< 0x00000008 */\n#define DSI_PTTCR_TX_TRIG3            DSI_PTTCR_TX_TRIG3_Msk\n\n/*******************  Bit definition for DSI_PSR register  ****************/\n#define DSI_PSR_PD_Pos                (1U)\n#define DSI_PSR_PD_Msk                (0x1U << DSI_PSR_PD_Pos)                 /*!< 0x00000002 */\n#define DSI_PSR_PD                    DSI_PSR_PD_Msk                           /*!< PHY Direction */\n#define DSI_PSR_PSSC_Pos              (2U)\n#define DSI_PSR_PSSC_Msk              (0x1U << DSI_PSR_PSSC_Pos)               /*!< 0x00000004 */\n#define DSI_PSR_PSSC                  DSI_PSR_PSSC_Msk                         /*!< PHY Stop State Clock lane */\n#define DSI_PSR_UANC_Pos              (3U)\n#define DSI_PSR_UANC_Msk              (0x1U << DSI_PSR_UANC_Pos)               /*!< 0x00000008 */\n#define DSI_PSR_UANC                  DSI_PSR_UANC_Msk                         /*!< ULPS Active Not Clock lane */\n#define DSI_PSR_PSS0_Pos              (4U)\n#define DSI_PSR_PSS0_Msk              (0x1U << DSI_PSR_PSS0_Pos)               /*!< 0x00000010 */\n#define DSI_PSR_PSS0                  DSI_PSR_PSS0_Msk                         /*!< PHY Stop State lane 0 */\n#define DSI_PSR_UAN0_Pos              (5U)\n#define DSI_PSR_UAN0_Msk              (0x1U << DSI_PSR_UAN0_Pos)               /*!< 0x00000020 */\n#define DSI_PSR_UAN0                  DSI_PSR_UAN0_Msk                         /*!< ULPS Active Not lane 0 */\n#define DSI_PSR_RUE0_Pos              (6U)\n#define DSI_PSR_RUE0_Msk              (0x1U << DSI_PSR_RUE0_Pos)               /*!< 0x00000040 */\n#define DSI_PSR_RUE0                  DSI_PSR_RUE0_Msk                         /*!< RX ULPS Escape lane 0 */\n#define DSI_PSR_PSS1_Pos              (7U)\n#define DSI_PSR_PSS1_Msk              (0x1U << DSI_PSR_PSS1_Pos)               /*!< 0x00000080 */\n#define DSI_PSR_PSS1                  DSI_PSR_PSS1_Msk                         /*!< PHY Stop State lane 1 */\n#define DSI_PSR_UAN1_Pos              (8U)\n#define DSI_PSR_UAN1_Msk              (0x1U << DSI_PSR_UAN1_Pos)               /*!< 0x00000100 */\n#define DSI_PSR_UAN1                  DSI_PSR_UAN1_Msk                         /*!< ULPS Active Not lane 1 */\n\n/*******************  Bit definition for DSI_ISR0 register  ***************/\n#define DSI_ISR0_AE0_Pos              (0U)\n#define DSI_ISR0_AE0_Msk              (0x1U << DSI_ISR0_AE0_Pos)               /*!< 0x00000001 */\n#define DSI_ISR0_AE0                  DSI_ISR0_AE0_Msk                         /*!< Acknowledge Error 0 */\n#define DSI_ISR0_AE1_Pos              (1U)\n#define DSI_ISR0_AE1_Msk              (0x1U << DSI_ISR0_AE1_Pos)               /*!< 0x00000002 */\n#define DSI_ISR0_AE1                  DSI_ISR0_AE1_Msk                         /*!< Acknowledge Error 1 */\n#define DSI_ISR0_AE2_Pos              (2U)\n#define DSI_ISR0_AE2_Msk              (0x1U << DSI_ISR0_AE2_Pos)               /*!< 0x00000004 */\n#define DSI_ISR0_AE2                  DSI_ISR0_AE2_Msk                         /*!< Acknowledge Error 2 */\n#define DSI_ISR0_AE3_Pos              (3U)\n#define DSI_ISR0_AE3_Msk              (0x1U << DSI_ISR0_AE3_Pos)               /*!< 0x00000008 */\n#define DSI_ISR0_AE3                  DSI_ISR0_AE3_Msk                         /*!< Acknowledge Error 3 */\n#define DSI_ISR0_AE4_Pos              (4U)\n#define DSI_ISR0_AE4_Msk              (0x1U << DSI_ISR0_AE4_Pos)               /*!< 0x00000010 */\n#define DSI_ISR0_AE4                  DSI_ISR0_AE4_Msk                         /*!< Acknowledge Error 4 */\n#define DSI_ISR0_AE5_Pos              (5U)\n#define DSI_ISR0_AE5_Msk              (0x1U << DSI_ISR0_AE5_Pos)               /*!< 0x00000020 */\n#define DSI_ISR0_AE5                  DSI_ISR0_AE5_Msk                         /*!< Acknowledge Error 5 */\n#define DSI_ISR0_AE6_Pos              (6U)\n#define DSI_ISR0_AE6_Msk              (0x1U << DSI_ISR0_AE6_Pos)               /*!< 0x00000040 */\n#define DSI_ISR0_AE6                  DSI_ISR0_AE6_Msk                         /*!< Acknowledge Error 6 */\n#define DSI_ISR0_AE7_Pos              (7U)\n#define DSI_ISR0_AE7_Msk              (0x1U << DSI_ISR0_AE7_Pos)               /*!< 0x00000080 */\n#define DSI_ISR0_AE7                  DSI_ISR0_AE7_Msk                         /*!< Acknowledge Error 7 */\n#define DSI_ISR0_AE8_Pos              (8U)\n#define DSI_ISR0_AE8_Msk              (0x1U << DSI_ISR0_AE8_Pos)               /*!< 0x00000100 */\n#define DSI_ISR0_AE8                  DSI_ISR0_AE8_Msk                         /*!< Acknowledge Error 8 */\n#define DSI_ISR0_AE9_Pos              (9U)\n#define DSI_ISR0_AE9_Msk              (0x1U << DSI_ISR0_AE9_Pos)               /*!< 0x00000200 */\n#define DSI_ISR0_AE9                  DSI_ISR0_AE9_Msk                         /*!< Acknowledge Error 9 */\n#define DSI_ISR0_AE10_Pos             (10U)\n#define DSI_ISR0_AE10_Msk             (0x1U << DSI_ISR0_AE10_Pos)              /*!< 0x00000400 */\n#define DSI_ISR0_AE10                 DSI_ISR0_AE10_Msk                        /*!< Acknowledge Error 10 */\n#define DSI_ISR0_AE11_Pos             (11U)\n#define DSI_ISR0_AE11_Msk             (0x1U << DSI_ISR0_AE11_Pos)              /*!< 0x00000800 */\n#define DSI_ISR0_AE11                 DSI_ISR0_AE11_Msk                        /*!< Acknowledge Error 11 */\n#define DSI_ISR0_AE12_Pos             (12U)\n#define DSI_ISR0_AE12_Msk             (0x1U << DSI_ISR0_AE12_Pos)              /*!< 0x00001000 */\n#define DSI_ISR0_AE12                 DSI_ISR0_AE12_Msk                        /*!< Acknowledge Error 12 */\n#define DSI_ISR0_AE13_Pos             (13U)\n#define DSI_ISR0_AE13_Msk             (0x1U << DSI_ISR0_AE13_Pos)              /*!< 0x00002000 */\n#define DSI_ISR0_AE13                 DSI_ISR0_AE13_Msk                        /*!< Acknowledge Error 13 */\n#define DSI_ISR0_AE14_Pos             (14U)\n#define DSI_ISR0_AE14_Msk             (0x1U << DSI_ISR0_AE14_Pos)              /*!< 0x00004000 */\n#define DSI_ISR0_AE14                 DSI_ISR0_AE14_Msk                        /*!< Acknowledge Error 14 */\n#define DSI_ISR0_AE15_Pos             (15U)\n#define DSI_ISR0_AE15_Msk             (0x1U << DSI_ISR0_AE15_Pos)              /*!< 0x00008000 */\n#define DSI_ISR0_AE15                 DSI_ISR0_AE15_Msk                        /*!< Acknowledge Error 15 */\n#define DSI_ISR0_PE0_Pos              (16U)\n#define DSI_ISR0_PE0_Msk              (0x1U << DSI_ISR0_PE0_Pos)               /*!< 0x00010000 */\n#define DSI_ISR0_PE0                  DSI_ISR0_PE0_Msk                         /*!< PHY Error 0 */\n#define DSI_ISR0_PE1_Pos              (17U)\n#define DSI_ISR0_PE1_Msk              (0x1U << DSI_ISR0_PE1_Pos)               /*!< 0x00020000 */\n#define DSI_ISR0_PE1                  DSI_ISR0_PE1_Msk                         /*!< PHY Error 1 */\n#define DSI_ISR0_PE2_Pos              (18U)\n#define DSI_ISR0_PE2_Msk              (0x1U << DSI_ISR0_PE2_Pos)               /*!< 0x00040000 */\n#define DSI_ISR0_PE2                  DSI_ISR0_PE2_Msk                         /*!< PHY Error 2 */\n#define DSI_ISR0_PE3_Pos              (19U)\n#define DSI_ISR0_PE3_Msk              (0x1U << DSI_ISR0_PE3_Pos)               /*!< 0x00080000 */\n#define DSI_ISR0_PE3                  DSI_ISR0_PE3_Msk                         /*!< PHY Error 3 */\n#define DSI_ISR0_PE4_Pos              (20U)\n#define DSI_ISR0_PE4_Msk              (0x1U << DSI_ISR0_PE4_Pos)               /*!< 0x00100000 */\n#define DSI_ISR0_PE4                  DSI_ISR0_PE4_Msk                         /*!< PHY Error 4 */\n\n/*******************  Bit definition for DSI_ISR1 register  ***************/\n#define DSI_ISR1_TOHSTX_Pos           (0U)\n#define DSI_ISR1_TOHSTX_Msk           (0x1U << DSI_ISR1_TOHSTX_Pos)            /*!< 0x00000001 */\n#define DSI_ISR1_TOHSTX               DSI_ISR1_TOHSTX_Msk                      /*!< Timeout High-Speed Transmission */\n#define DSI_ISR1_TOLPRX_Pos           (1U)\n#define DSI_ISR1_TOLPRX_Msk           (0x1U << DSI_ISR1_TOLPRX_Pos)            /*!< 0x00000002 */\n#define DSI_ISR1_TOLPRX               DSI_ISR1_TOLPRX_Msk                      /*!< Timeout Low-Power Reception */\n#define DSI_ISR1_ECCSE_Pos            (2U)\n#define DSI_ISR1_ECCSE_Msk            (0x1U << DSI_ISR1_ECCSE_Pos)             /*!< 0x00000004 */\n#define DSI_ISR1_ECCSE                DSI_ISR1_ECCSE_Msk                       /*!< ECC Single-bit Error */\n#define DSI_ISR1_ECCME_Pos            (3U)\n#define DSI_ISR1_ECCME_Msk            (0x1U << DSI_ISR1_ECCME_Pos)             /*!< 0x00000008 */\n#define DSI_ISR1_ECCME                DSI_ISR1_ECCME_Msk                       /*!< ECC Multi-bit Error */\n#define DSI_ISR1_CRCE_Pos             (4U)\n#define DSI_ISR1_CRCE_Msk             (0x1U << DSI_ISR1_CRCE_Pos)              /*!< 0x00000010 */\n#define DSI_ISR1_CRCE                 DSI_ISR1_CRCE_Msk                        /*!< CRC Error */\n#define DSI_ISR1_PSE_Pos              (5U)\n#define DSI_ISR1_PSE_Msk              (0x1U << DSI_ISR1_PSE_Pos)               /*!< 0x00000020 */\n#define DSI_ISR1_PSE                  DSI_ISR1_PSE_Msk                         /*!< Packet Size Error */\n#define DSI_ISR1_EOTPE_Pos            (6U)\n#define DSI_ISR1_EOTPE_Msk            (0x1U << DSI_ISR1_EOTPE_Pos)             /*!< 0x00000040 */\n#define DSI_ISR1_EOTPE                DSI_ISR1_EOTPE_Msk                       /*!< EoTp Error */\n#define DSI_ISR1_LPWRE_Pos            (7U)\n#define DSI_ISR1_LPWRE_Msk            (0x1U << DSI_ISR1_LPWRE_Pos)             /*!< 0x00000080 */\n#define DSI_ISR1_LPWRE                DSI_ISR1_LPWRE_Msk                       /*!< LTDC Payload Write Error */\n#define DSI_ISR1_GCWRE_Pos            (8U)\n#define DSI_ISR1_GCWRE_Msk            (0x1U << DSI_ISR1_GCWRE_Pos)             /*!< 0x00000100 */\n#define DSI_ISR1_GCWRE                DSI_ISR1_GCWRE_Msk                       /*!< Generic Command Write Error */\n#define DSI_ISR1_GPWRE_Pos            (9U)\n#define DSI_ISR1_GPWRE_Msk            (0x1U << DSI_ISR1_GPWRE_Pos)             /*!< 0x00000200 */\n#define DSI_ISR1_GPWRE                DSI_ISR1_GPWRE_Msk                       /*!< Generic Payload Write Error */\n#define DSI_ISR1_GPTXE_Pos            (10U)\n#define DSI_ISR1_GPTXE_Msk            (0x1U << DSI_ISR1_GPTXE_Pos)             /*!< 0x00000400 */\n#define DSI_ISR1_GPTXE                DSI_ISR1_GPTXE_Msk                       /*!< Generic Payload Transmit Error */\n#define DSI_ISR1_GPRDE_Pos            (11U)\n#define DSI_ISR1_GPRDE_Msk            (0x1U << DSI_ISR1_GPRDE_Pos)             /*!< 0x00000800 */\n#define DSI_ISR1_GPRDE                DSI_ISR1_GPRDE_Msk                       /*!< Generic Payload Read Error */\n#define DSI_ISR1_GPRXE_Pos            (12U)\n#define DSI_ISR1_GPRXE_Msk            (0x1U << DSI_ISR1_GPRXE_Pos)             /*!< 0x00001000 */\n#define DSI_ISR1_GPRXE                DSI_ISR1_GPRXE_Msk                       /*!< Generic Payload Receive Error */\n\n/*******************  Bit definition for DSI_IER0 register  ***************/\n#define DSI_IER0_AE0IE_Pos            (0U)\n#define DSI_IER0_AE0IE_Msk            (0x1U << DSI_IER0_AE0IE_Pos)             /*!< 0x00000001 */\n#define DSI_IER0_AE0IE                DSI_IER0_AE0IE_Msk                       /*!< Acknowledge Error 0 Interrupt Enable */\n#define DSI_IER0_AE1IE_Pos            (1U)\n#define DSI_IER0_AE1IE_Msk            (0x1U << DSI_IER0_AE1IE_Pos)             /*!< 0x00000002 */\n#define DSI_IER0_AE1IE                DSI_IER0_AE1IE_Msk                       /*!< Acknowledge Error 1 Interrupt Enable */\n#define DSI_IER0_AE2IE_Pos            (2U)\n#define DSI_IER0_AE2IE_Msk            (0x1U << DSI_IER0_AE2IE_Pos)             /*!< 0x00000004 */\n#define DSI_IER0_AE2IE                DSI_IER0_AE2IE_Msk                       /*!< Acknowledge Error 2 Interrupt Enable */\n#define DSI_IER0_AE3IE_Pos            (3U)\n#define DSI_IER0_AE3IE_Msk            (0x1U << DSI_IER0_AE3IE_Pos)             /*!< 0x00000008 */\n#define DSI_IER0_AE3IE                DSI_IER0_AE3IE_Msk                       /*!< Acknowledge Error 3 Interrupt Enable */\n#define DSI_IER0_AE4IE_Pos            (4U)\n#define DSI_IER0_AE4IE_Msk            (0x1U << DSI_IER0_AE4IE_Pos)             /*!< 0x00000010 */\n#define DSI_IER0_AE4IE                DSI_IER0_AE4IE_Msk                       /*!< Acknowledge Error 4 Interrupt Enable */\n#define DSI_IER0_AE5IE_Pos            (5U)\n#define DSI_IER0_AE5IE_Msk            (0x1U << DSI_IER0_AE5IE_Pos)             /*!< 0x00000020 */\n#define DSI_IER0_AE5IE                DSI_IER0_AE5IE_Msk                       /*!< Acknowledge Error 5 Interrupt Enable */\n#define DSI_IER0_AE6IE_Pos            (6U)\n#define DSI_IER0_AE6IE_Msk            (0x1U << DSI_IER0_AE6IE_Pos)             /*!< 0x00000040 */\n#define DSI_IER0_AE6IE                DSI_IER0_AE6IE_Msk                       /*!< Acknowledge Error 6 Interrupt Enable */\n#define DSI_IER0_AE7IE_Pos            (7U)\n#define DSI_IER0_AE7IE_Msk            (0x1U << DSI_IER0_AE7IE_Pos)             /*!< 0x00000080 */\n#define DSI_IER0_AE7IE                DSI_IER0_AE7IE_Msk                       /*!< Acknowledge Error 7 Interrupt Enable */\n#define DSI_IER0_AE8IE_Pos            (8U)\n#define DSI_IER0_AE8IE_Msk            (0x1U << DSI_IER0_AE8IE_Pos)             /*!< 0x00000100 */\n#define DSI_IER0_AE8IE                DSI_IER0_AE8IE_Msk                       /*!< Acknowledge Error 8 Interrupt Enable */\n#define DSI_IER0_AE9IE_Pos            (9U)\n#define DSI_IER0_AE9IE_Msk            (0x1U << DSI_IER0_AE9IE_Pos)             /*!< 0x00000200 */\n#define DSI_IER0_AE9IE                DSI_IER0_AE9IE_Msk                       /*!< Acknowledge Error 9 Interrupt Enable */\n#define DSI_IER0_AE10IE_Pos           (10U)\n#define DSI_IER0_AE10IE_Msk           (0x1U << DSI_IER0_AE10IE_Pos)            /*!< 0x00000400 */\n#define DSI_IER0_AE10IE               DSI_IER0_AE10IE_Msk                      /*!< Acknowledge Error 10 Interrupt Enable */\n#define DSI_IER0_AE11IE_Pos           (11U)\n#define DSI_IER0_AE11IE_Msk           (0x1U << DSI_IER0_AE11IE_Pos)            /*!< 0x00000800 */\n#define DSI_IER0_AE11IE               DSI_IER0_AE11IE_Msk                      /*!< Acknowledge Error 11 Interrupt Enable */\n#define DSI_IER0_AE12IE_Pos           (12U)\n#define DSI_IER0_AE12IE_Msk           (0x1U << DSI_IER0_AE12IE_Pos)            /*!< 0x00001000 */\n#define DSI_IER0_AE12IE               DSI_IER0_AE12IE_Msk                      /*!< Acknowledge Error 12 Interrupt Enable */\n#define DSI_IER0_AE13IE_Pos           (13U)\n#define DSI_IER0_AE13IE_Msk           (0x1U << DSI_IER0_AE13IE_Pos)            /*!< 0x00002000 */\n#define DSI_IER0_AE13IE               DSI_IER0_AE13IE_Msk                      /*!< Acknowledge Error 13 Interrupt Enable */\n#define DSI_IER0_AE14IE_Pos           (14U)\n#define DSI_IER0_AE14IE_Msk           (0x1U << DSI_IER0_AE14IE_Pos)            /*!< 0x00004000 */\n#define DSI_IER0_AE14IE               DSI_IER0_AE14IE_Msk                      /*!< Acknowledge Error 14 Interrupt Enable */\n#define DSI_IER0_AE15IE_Pos           (15U)\n#define DSI_IER0_AE15IE_Msk           (0x1U << DSI_IER0_AE15IE_Pos)            /*!< 0x00008000 */\n#define DSI_IER0_AE15IE               DSI_IER0_AE15IE_Msk                      /*!< Acknowledge Error 15 Interrupt Enable */\n#define DSI_IER0_PE0IE_Pos            (16U)\n#define DSI_IER0_PE0IE_Msk            (0x1U << DSI_IER0_PE0IE_Pos)             /*!< 0x00010000 */\n#define DSI_IER0_PE0IE                DSI_IER0_PE0IE_Msk                       /*!< PHY Error 0 Interrupt Enable */\n#define DSI_IER0_PE1IE_Pos            (17U)\n#define DSI_IER0_PE1IE_Msk            (0x1U << DSI_IER0_PE1IE_Pos)             /*!< 0x00020000 */\n#define DSI_IER0_PE1IE                DSI_IER0_PE1IE_Msk                       /*!< PHY Error 1 Interrupt Enable */\n#define DSI_IER0_PE2IE_Pos            (18U)\n#define DSI_IER0_PE2IE_Msk            (0x1U << DSI_IER0_PE2IE_Pos)             /*!< 0x00040000 */\n#define DSI_IER0_PE2IE                DSI_IER0_PE2IE_Msk                       /*!< PHY Error 2 Interrupt Enable */\n#define DSI_IER0_PE3IE_Pos            (19U)\n#define DSI_IER0_PE3IE_Msk            (0x1U << DSI_IER0_PE3IE_Pos)             /*!< 0x00080000 */\n#define DSI_IER0_PE3IE                DSI_IER0_PE3IE_Msk                       /*!< PHY Error 3 Interrupt Enable */\n#define DSI_IER0_PE4IE_Pos            (20U)\n#define DSI_IER0_PE4IE_Msk            (0x1U << DSI_IER0_PE4IE_Pos)             /*!< 0x00100000 */\n#define DSI_IER0_PE4IE                DSI_IER0_PE4IE_Msk                       /*!< PHY Error 4 Interrupt Enable */\n\n/*******************  Bit definition for DSI_IER1 register  ***************/\n#define DSI_IER1_TOHSTXIE_Pos         (0U)\n#define DSI_IER1_TOHSTXIE_Msk         (0x1U << DSI_IER1_TOHSTXIE_Pos)          /*!< 0x00000001 */\n#define DSI_IER1_TOHSTXIE             DSI_IER1_TOHSTXIE_Msk                    /*!< Timeout High-Speed Transmission Interrupt Enable */\n#define DSI_IER1_TOLPRXIE_Pos         (1U)\n#define DSI_IER1_TOLPRXIE_Msk         (0x1U << DSI_IER1_TOLPRXIE_Pos)          /*!< 0x00000002 */\n#define DSI_IER1_TOLPRXIE             DSI_IER1_TOLPRXIE_Msk                    /*!< Timeout Low-Power Reception Interrupt Enable */\n#define DSI_IER1_ECCSEIE_Pos          (2U)\n#define DSI_IER1_ECCSEIE_Msk          (0x1U << DSI_IER1_ECCSEIE_Pos)           /*!< 0x00000004 */\n#define DSI_IER1_ECCSEIE              DSI_IER1_ECCSEIE_Msk                     /*!< ECC Single-bit Error Interrupt Enable */\n#define DSI_IER1_ECCMEIE_Pos          (3U)\n#define DSI_IER1_ECCMEIE_Msk          (0x1U << DSI_IER1_ECCMEIE_Pos)           /*!< 0x00000008 */\n#define DSI_IER1_ECCMEIE              DSI_IER1_ECCMEIE_Msk                     /*!< ECC Multi-bit Error Interrupt Enable */\n#define DSI_IER1_CRCEIE_Pos           (4U)\n#define DSI_IER1_CRCEIE_Msk           (0x1U << DSI_IER1_CRCEIE_Pos)            /*!< 0x00000010 */\n#define DSI_IER1_CRCEIE               DSI_IER1_CRCEIE_Msk                      /*!< CRC Error Interrupt Enable */\n#define DSI_IER1_PSEIE_Pos            (5U)\n#define DSI_IER1_PSEIE_Msk            (0x1U << DSI_IER1_PSEIE_Pos)             /*!< 0x00000020 */\n#define DSI_IER1_PSEIE                DSI_IER1_PSEIE_Msk                       /*!< Packet Size Error Interrupt Enable */\n#define DSI_IER1_EOTPEIE_Pos          (6U)\n#define DSI_IER1_EOTPEIE_Msk          (0x1U << DSI_IER1_EOTPEIE_Pos)           /*!< 0x00000040 */\n#define DSI_IER1_EOTPEIE              DSI_IER1_EOTPEIE_Msk                     /*!< EoTp Error Interrupt Enable */\n#define DSI_IER1_LPWREIE_Pos          (7U)\n#define DSI_IER1_LPWREIE_Msk          (0x1U << DSI_IER1_LPWREIE_Pos)           /*!< 0x00000080 */\n#define DSI_IER1_LPWREIE              DSI_IER1_LPWREIE_Msk                     /*!< LTDC Payload Write Error Interrupt Enable */\n#define DSI_IER1_GCWREIE_Pos          (8U)\n#define DSI_IER1_GCWREIE_Msk          (0x1U << DSI_IER1_GCWREIE_Pos)           /*!< 0x00000100 */\n#define DSI_IER1_GCWREIE              DSI_IER1_GCWREIE_Msk                     /*!< Generic Command Write Error Interrupt Enable */\n#define DSI_IER1_GPWREIE_Pos          (9U)\n#define DSI_IER1_GPWREIE_Msk          (0x1U << DSI_IER1_GPWREIE_Pos)           /*!< 0x00000200 */\n#define DSI_IER1_GPWREIE              DSI_IER1_GPWREIE_Msk                     /*!< Generic Payload Write Error Interrupt Enable */\n#define DSI_IER1_GPTXEIE_Pos          (10U)\n#define DSI_IER1_GPTXEIE_Msk          (0x1U << DSI_IER1_GPTXEIE_Pos)           /*!< 0x00000400 */\n#define DSI_IER1_GPTXEIE              DSI_IER1_GPTXEIE_Msk                     /*!< Generic Payload Transmit Error Interrupt Enable */\n#define DSI_IER1_GPRDEIE_Pos          (11U)\n#define DSI_IER1_GPRDEIE_Msk          (0x1U << DSI_IER1_GPRDEIE_Pos)           /*!< 0x00000800 */\n#define DSI_IER1_GPRDEIE              DSI_IER1_GPRDEIE_Msk                     /*!< Generic Payload Read Error Interrupt Enable */\n#define DSI_IER1_GPRXEIE_Pos          (12U)\n#define DSI_IER1_GPRXEIE_Msk          (0x1U << DSI_IER1_GPRXEIE_Pos)           /*!< 0x00001000 */\n#define DSI_IER1_GPRXEIE              DSI_IER1_GPRXEIE_Msk                     /*!< Generic Payload Receive Error Interrupt Enable */\n\n/*******************  Bit definition for DSI_FIR0 register  ***************/\n#define DSI_FIR0_FAE0_Pos             (0U)\n#define DSI_FIR0_FAE0_Msk             (0x1U << DSI_FIR0_FAE0_Pos)              /*!< 0x00000001 */\n#define DSI_FIR0_FAE0                 DSI_FIR0_FAE0_Msk                        /*!< Force Acknowledge Error 0 */\n#define DSI_FIR0_FAE1_Pos             (1U)\n#define DSI_FIR0_FAE1_Msk             (0x1U << DSI_FIR0_FAE1_Pos)              /*!< 0x00000002 */\n#define DSI_FIR0_FAE1                 DSI_FIR0_FAE1_Msk                        /*!< Force Acknowledge Error 1 */\n#define DSI_FIR0_FAE2_Pos             (2U)\n#define DSI_FIR0_FAE2_Msk             (0x1U << DSI_FIR0_FAE2_Pos)              /*!< 0x00000004 */\n#define DSI_FIR0_FAE2                 DSI_FIR0_FAE2_Msk                        /*!< Force Acknowledge Error 2 */\n#define DSI_FIR0_FAE3_Pos             (3U)\n#define DSI_FIR0_FAE3_Msk             (0x1U << DSI_FIR0_FAE3_Pos)              /*!< 0x00000008 */\n#define DSI_FIR0_FAE3                 DSI_FIR0_FAE3_Msk                        /*!< Force Acknowledge Error 3 */\n#define DSI_FIR0_FAE4_Pos             (4U)\n#define DSI_FIR0_FAE4_Msk             (0x1U << DSI_FIR0_FAE4_Pos)              /*!< 0x00000010 */\n#define DSI_FIR0_FAE4                 DSI_FIR0_FAE4_Msk                        /*!< Force Acknowledge Error 4 */\n#define DSI_FIR0_FAE5_Pos             (5U)\n#define DSI_FIR0_FAE5_Msk             (0x1U << DSI_FIR0_FAE5_Pos)              /*!< 0x00000020 */\n#define DSI_FIR0_FAE5                 DSI_FIR0_FAE5_Msk                        /*!< Force Acknowledge Error 5 */\n#define DSI_FIR0_FAE6_Pos             (6U)\n#define DSI_FIR0_FAE6_Msk             (0x1U << DSI_FIR0_FAE6_Pos)              /*!< 0x00000040 */\n#define DSI_FIR0_FAE6                 DSI_FIR0_FAE6_Msk                        /*!< Force Acknowledge Error 6 */\n#define DSI_FIR0_FAE7_Pos             (7U)\n#define DSI_FIR0_FAE7_Msk             (0x1U << DSI_FIR0_FAE7_Pos)              /*!< 0x00000080 */\n#define DSI_FIR0_FAE7                 DSI_FIR0_FAE7_Msk                        /*!< Force Acknowledge Error 7 */\n#define DSI_FIR0_FAE8_Pos             (8U)\n#define DSI_FIR0_FAE8_Msk             (0x1U << DSI_FIR0_FAE8_Pos)              /*!< 0x00000100 */\n#define DSI_FIR0_FAE8                 DSI_FIR0_FAE8_Msk                        /*!< Force Acknowledge Error 8 */\n#define DSI_FIR0_FAE9_Pos             (9U)\n#define DSI_FIR0_FAE9_Msk             (0x1U << DSI_FIR0_FAE9_Pos)              /*!< 0x00000200 */\n#define DSI_FIR0_FAE9                 DSI_FIR0_FAE9_Msk                        /*!< Force Acknowledge Error 9 */\n#define DSI_FIR0_FAE10_Pos            (10U)\n#define DSI_FIR0_FAE10_Msk            (0x1U << DSI_FIR0_FAE10_Pos)             /*!< 0x00000400 */\n#define DSI_FIR0_FAE10                DSI_FIR0_FAE10_Msk                       /*!< Force Acknowledge Error 10 */\n#define DSI_FIR0_FAE11_Pos            (11U)\n#define DSI_FIR0_FAE11_Msk            (0x1U << DSI_FIR0_FAE11_Pos)             /*!< 0x00000800 */\n#define DSI_FIR0_FAE11                DSI_FIR0_FAE11_Msk                       /*!< Force Acknowledge Error 11 */\n#define DSI_FIR0_FAE12_Pos            (12U)\n#define DSI_FIR0_FAE12_Msk            (0x1U << DSI_FIR0_FAE12_Pos)             /*!< 0x00001000 */\n#define DSI_FIR0_FAE12                DSI_FIR0_FAE12_Msk                       /*!< Force Acknowledge Error 12 */\n#define DSI_FIR0_FAE13_Pos            (13U)\n#define DSI_FIR0_FAE13_Msk            (0x1U << DSI_FIR0_FAE13_Pos)             /*!< 0x00002000 */\n#define DSI_FIR0_FAE13                DSI_FIR0_FAE13_Msk                       /*!< Force Acknowledge Error 13 */\n#define DSI_FIR0_FAE14_Pos            (14U)\n#define DSI_FIR0_FAE14_Msk            (0x1U << DSI_FIR0_FAE14_Pos)             /*!< 0x00004000 */\n#define DSI_FIR0_FAE14                DSI_FIR0_FAE14_Msk                       /*!< Force Acknowledge Error 14 */\n#define DSI_FIR0_FAE15_Pos            (15U)\n#define DSI_FIR0_FAE15_Msk            (0x1U << DSI_FIR0_FAE15_Pos)             /*!< 0x00008000 */\n#define DSI_FIR0_FAE15                DSI_FIR0_FAE15_Msk                       /*!< Force Acknowledge Error 15 */\n#define DSI_FIR0_FPE0_Pos             (16U)\n#define DSI_FIR0_FPE0_Msk             (0x1U << DSI_FIR0_FPE0_Pos)              /*!< 0x00010000 */\n#define DSI_FIR0_FPE0                 DSI_FIR0_FPE0_Msk                        /*!< Force PHY Error 0 */\n#define DSI_FIR0_FPE1_Pos             (17U)\n#define DSI_FIR0_FPE1_Msk             (0x1U << DSI_FIR0_FPE1_Pos)              /*!< 0x00020000 */\n#define DSI_FIR0_FPE1                 DSI_FIR0_FPE1_Msk                        /*!< Force PHY Error 1 */\n#define DSI_FIR0_FPE2_Pos             (18U)\n#define DSI_FIR0_FPE2_Msk             (0x1U << DSI_FIR0_FPE2_Pos)              /*!< 0x00040000 */\n#define DSI_FIR0_FPE2                 DSI_FIR0_FPE2_Msk                        /*!< Force PHY Error 2 */\n#define DSI_FIR0_FPE3_Pos             (19U)\n#define DSI_FIR0_FPE3_Msk             (0x1U << DSI_FIR0_FPE3_Pos)              /*!< 0x00080000 */\n#define DSI_FIR0_FPE3                 DSI_FIR0_FPE3_Msk                        /*!< Force PHY Error 3 */\n#define DSI_FIR0_FPE4_Pos             (20U)\n#define DSI_FIR0_FPE4_Msk             (0x1U << DSI_FIR0_FPE4_Pos)              /*!< 0x00100000 */\n#define DSI_FIR0_FPE4                 DSI_FIR0_FPE4_Msk                        /*!< Force PHY Error 4 */\n\n/*******************  Bit definition for DSI_FIR1 register  ***************/\n#define DSI_FIR1_FTOHSTX_Pos          (0U)\n#define DSI_FIR1_FTOHSTX_Msk          (0x1U << DSI_FIR1_FTOHSTX_Pos)           /*!< 0x00000001 */\n#define DSI_FIR1_FTOHSTX              DSI_FIR1_FTOHSTX_Msk                     /*!< Force Timeout High-Speed Transmission */\n#define DSI_FIR1_FTOLPRX_Pos          (1U)\n#define DSI_FIR1_FTOLPRX_Msk          (0x1U << DSI_FIR1_FTOLPRX_Pos)           /*!< 0x00000002 */\n#define DSI_FIR1_FTOLPRX              DSI_FIR1_FTOLPRX_Msk                     /*!< Force Timeout Low-Power Reception */\n#define DSI_FIR1_FECCSE_Pos           (2U)\n#define DSI_FIR1_FECCSE_Msk           (0x1U << DSI_FIR1_FECCSE_Pos)            /*!< 0x00000004 */\n#define DSI_FIR1_FECCSE               DSI_FIR1_FECCSE_Msk                      /*!< Force ECC Single-bit Error */\n#define DSI_FIR1_FECCME_Pos           (3U)\n#define DSI_FIR1_FECCME_Msk           (0x1U << DSI_FIR1_FECCME_Pos)            /*!< 0x00000008 */\n#define DSI_FIR1_FECCME               DSI_FIR1_FECCME_Msk                      /*!< Force ECC Multi-bit Error */\n#define DSI_FIR1_FCRCE_Pos            (4U)\n#define DSI_FIR1_FCRCE_Msk            (0x1U << DSI_FIR1_FCRCE_Pos)             /*!< 0x00000010 */\n#define DSI_FIR1_FCRCE                DSI_FIR1_FCRCE_Msk                       /*!< Force CRC Error */\n#define DSI_FIR1_FPSE_Pos             (5U)\n#define DSI_FIR1_FPSE_Msk             (0x1U << DSI_FIR1_FPSE_Pos)              /*!< 0x00000020 */\n#define DSI_FIR1_FPSE                 DSI_FIR1_FPSE_Msk                        /*!< Force Packet Size Error */\n#define DSI_FIR1_FEOTPE_Pos           (6U)\n#define DSI_FIR1_FEOTPE_Msk           (0x1U << DSI_FIR1_FEOTPE_Pos)            /*!< 0x00000040 */\n#define DSI_FIR1_FEOTPE               DSI_FIR1_FEOTPE_Msk                      /*!< Force EoTp Error */\n#define DSI_FIR1_FLPWRE_Pos           (7U)\n#define DSI_FIR1_FLPWRE_Msk           (0x1U << DSI_FIR1_FLPWRE_Pos)            /*!< 0x00000080 */\n#define DSI_FIR1_FLPWRE               DSI_FIR1_FLPWRE_Msk                      /*!< Force LTDC Payload Write Error */\n#define DSI_FIR1_FGCWRE_Pos           (8U)\n#define DSI_FIR1_FGCWRE_Msk           (0x1U << DSI_FIR1_FGCWRE_Pos)            /*!< 0x00000100 */\n#define DSI_FIR1_FGCWRE               DSI_FIR1_FGCWRE_Msk                      /*!< Force Generic Command Write Error */\n#define DSI_FIR1_FGPWRE_Pos           (9U)\n#define DSI_FIR1_FGPWRE_Msk           (0x1U << DSI_FIR1_FGPWRE_Pos)            /*!< 0x00000200 */\n#define DSI_FIR1_FGPWRE               DSI_FIR1_FGPWRE_Msk                      /*!< Force Generic Payload Write Error */\n#define DSI_FIR1_FGPTXE_Pos           (10U)\n#define DSI_FIR1_FGPTXE_Msk           (0x1U << DSI_FIR1_FGPTXE_Pos)            /*!< 0x00000400 */\n#define DSI_FIR1_FGPTXE               DSI_FIR1_FGPTXE_Msk                      /*!< Force Generic Payload Transmit Error */\n#define DSI_FIR1_FGPRDE_Pos           (11U)\n#define DSI_FIR1_FGPRDE_Msk           (0x1U << DSI_FIR1_FGPRDE_Pos)            /*!< 0x00000800 */\n#define DSI_FIR1_FGPRDE               DSI_FIR1_FGPRDE_Msk                      /*!< Force Generic Payload Read Error */\n#define DSI_FIR1_FGPRXE_Pos           (12U)\n#define DSI_FIR1_FGPRXE_Msk           (0x1U << DSI_FIR1_FGPRXE_Pos)            /*!< 0x00001000 */\n#define DSI_FIR1_FGPRXE               DSI_FIR1_FGPRXE_Msk                      /*!< Force Generic Payload Receive Error */\n\n/*******************  Bit definition for DSI_VSCR register  ***************/\n#define DSI_VSCR_EN_Pos               (0U)\n#define DSI_VSCR_EN_Msk               (0x1U << DSI_VSCR_EN_Pos)                /*!< 0x00000001 */\n#define DSI_VSCR_EN                   DSI_VSCR_EN_Msk                          /*!< Enable */\n#define DSI_VSCR_UR_Pos               (8U)\n#define DSI_VSCR_UR_Msk               (0x1U << DSI_VSCR_UR_Pos)                /*!< 0x00000100 */\n#define DSI_VSCR_UR                   DSI_VSCR_UR_Msk                          /*!< Update Register */\n\n/*******************  Bit definition for DSI_LCVCIDR register  ************/\n#define DSI_LCVCIDR_VCID_Pos          (0U)\n#define DSI_LCVCIDR_VCID_Msk          (0x3U << DSI_LCVCIDR_VCID_Pos)           /*!< 0x00000003 */\n#define DSI_LCVCIDR_VCID              DSI_LCVCIDR_VCID_Msk                     /*!< Virtual Channel ID */\n#define DSI_LCVCIDR_VCID0_Pos         (0U)\n#define DSI_LCVCIDR_VCID0_Msk         (0x1U << DSI_LCVCIDR_VCID0_Pos)          /*!< 0x00000001 */\n#define DSI_LCVCIDR_VCID0             DSI_LCVCIDR_VCID0_Msk\n#define DSI_LCVCIDR_VCID1_Pos         (1U)\n#define DSI_LCVCIDR_VCID1_Msk         (0x1U << DSI_LCVCIDR_VCID1_Pos)          /*!< 0x00000002 */\n#define DSI_LCVCIDR_VCID1             DSI_LCVCIDR_VCID1_Msk\n\n/*******************  Bit definition for DSI_LCCCR register  **************/\n#define DSI_LCCCR_COLC_Pos            (0U)\n#define DSI_LCCCR_COLC_Msk            (0xFU << DSI_LCCCR_COLC_Pos)             /*!< 0x0000000F */\n#define DSI_LCCCR_COLC                DSI_LCCCR_COLC_Msk                       /*!< Color Coding */\n#define DSI_LCCCR_COLC0_Pos           (0U)\n#define DSI_LCCCR_COLC0_Msk           (0x1U << DSI_LCCCR_COLC0_Pos)            /*!< 0x00000001 */\n#define DSI_LCCCR_COLC0               DSI_LCCCR_COLC0_Msk\n#define DSI_LCCCR_COLC1_Pos           (1U)\n#define DSI_LCCCR_COLC1_Msk           (0x1U << DSI_LCCCR_COLC1_Pos)            /*!< 0x00000002 */\n#define DSI_LCCCR_COLC1               DSI_LCCCR_COLC1_Msk\n#define DSI_LCCCR_COLC2_Pos           (2U)\n#define DSI_LCCCR_COLC2_Msk           (0x1U << DSI_LCCCR_COLC2_Pos)            /*!< 0x00000004 */\n#define DSI_LCCCR_COLC2               DSI_LCCCR_COLC2_Msk\n#define DSI_LCCCR_COLC3_Pos           (3U)\n#define DSI_LCCCR_COLC3_Msk           (0x1U << DSI_LCCCR_COLC3_Pos)            /*!< 0x00000008 */\n#define DSI_LCCCR_COLC3               DSI_LCCCR_COLC3_Msk\n\n#define DSI_LCCCR_LPE_Pos             (8U)\n#define DSI_LCCCR_LPE_Msk             (0x1U << DSI_LCCCR_LPE_Pos)              /*!< 0x00000100 */\n#define DSI_LCCCR_LPE                 DSI_LCCCR_LPE_Msk                        /*!< Loosely Packed Enable */\n\n/*******************  Bit definition for DSI_LPMCCR register  *************/\n#define DSI_LPMCCR_VLPSIZE_Pos        (0U)\n#define DSI_LPMCCR_VLPSIZE_Msk        (0xFFU << DSI_LPMCCR_VLPSIZE_Pos)        /*!< 0x000000FF */\n#define DSI_LPMCCR_VLPSIZE            DSI_LPMCCR_VLPSIZE_Msk                   /*!< VACT Largest Packet Size */\n#define DSI_LPMCCR_VLPSIZE0_Pos       (0U)\n#define DSI_LPMCCR_VLPSIZE0_Msk       (0x1U << DSI_LPMCCR_VLPSIZE0_Pos)        /*!< 0x00000001 */\n#define DSI_LPMCCR_VLPSIZE0           DSI_LPMCCR_VLPSIZE0_Msk\n#define DSI_LPMCCR_VLPSIZE1_Pos       (1U)\n#define DSI_LPMCCR_VLPSIZE1_Msk       (0x1U << DSI_LPMCCR_VLPSIZE1_Pos)        /*!< 0x00000002 */\n#define DSI_LPMCCR_VLPSIZE1           DSI_LPMCCR_VLPSIZE1_Msk\n#define DSI_LPMCCR_VLPSIZE2_Pos       (2U)\n#define DSI_LPMCCR_VLPSIZE2_Msk       (0x1U << DSI_LPMCCR_VLPSIZE2_Pos)        /*!< 0x00000004 */\n#define DSI_LPMCCR_VLPSIZE2           DSI_LPMCCR_VLPSIZE2_Msk\n#define DSI_LPMCCR_VLPSIZE3_Pos       (3U)\n#define DSI_LPMCCR_VLPSIZE3_Msk       (0x1U << DSI_LPMCCR_VLPSIZE3_Pos)        /*!< 0x00000008 */\n#define DSI_LPMCCR_VLPSIZE3           DSI_LPMCCR_VLPSIZE3_Msk\n#define DSI_LPMCCR_VLPSIZE4_Pos       (4U)\n#define DSI_LPMCCR_VLPSIZE4_Msk       (0x1U << DSI_LPMCCR_VLPSIZE4_Pos)        /*!< 0x00000010 */\n#define DSI_LPMCCR_VLPSIZE4           DSI_LPMCCR_VLPSIZE4_Msk\n#define DSI_LPMCCR_VLPSIZE5_Pos       (5U)\n#define DSI_LPMCCR_VLPSIZE5_Msk       (0x1U << DSI_LPMCCR_VLPSIZE5_Pos)        /*!< 0x00000020 */\n#define DSI_LPMCCR_VLPSIZE5           DSI_LPMCCR_VLPSIZE5_Msk\n#define DSI_LPMCCR_VLPSIZE6_Pos       (6U)\n#define DSI_LPMCCR_VLPSIZE6_Msk       (0x1U << DSI_LPMCCR_VLPSIZE6_Pos)        /*!< 0x00000040 */\n#define DSI_LPMCCR_VLPSIZE6           DSI_LPMCCR_VLPSIZE6_Msk\n#define DSI_LPMCCR_VLPSIZE7_Pos       (7U)\n#define DSI_LPMCCR_VLPSIZE7_Msk       (0x1U << DSI_LPMCCR_VLPSIZE7_Pos)        /*!< 0x00000080 */\n#define DSI_LPMCCR_VLPSIZE7           DSI_LPMCCR_VLPSIZE7_Msk\n\n#define DSI_LPMCCR_LPSIZE_Pos         (16U)\n#define DSI_LPMCCR_LPSIZE_Msk         (0xFFU << DSI_LPMCCR_LPSIZE_Pos)         /*!< 0x00FF0000 */\n#define DSI_LPMCCR_LPSIZE             DSI_LPMCCR_LPSIZE_Msk                    /*!< Largest Packet Size */\n#define DSI_LPMCCR_LPSIZE0_Pos        (16U)\n#define DSI_LPMCCR_LPSIZE0_Msk        (0x1U << DSI_LPMCCR_LPSIZE0_Pos)         /*!< 0x00010000 */\n#define DSI_LPMCCR_LPSIZE0            DSI_LPMCCR_LPSIZE0_Msk\n#define DSI_LPMCCR_LPSIZE1_Pos        (17U)\n#define DSI_LPMCCR_LPSIZE1_Msk        (0x1U << DSI_LPMCCR_LPSIZE1_Pos)         /*!< 0x00020000 */\n#define DSI_LPMCCR_LPSIZE1            DSI_LPMCCR_LPSIZE1_Msk\n#define DSI_LPMCCR_LPSIZE2_Pos        (18U)\n#define DSI_LPMCCR_LPSIZE2_Msk        (0x1U << DSI_LPMCCR_LPSIZE2_Pos)         /*!< 0x00040000 */\n#define DSI_LPMCCR_LPSIZE2            DSI_LPMCCR_LPSIZE2_Msk\n#define DSI_LPMCCR_LPSIZE3_Pos        (19U)\n#define DSI_LPMCCR_LPSIZE3_Msk        (0x1U << DSI_LPMCCR_LPSIZE3_Pos)         /*!< 0x00080000 */\n#define DSI_LPMCCR_LPSIZE3            DSI_LPMCCR_LPSIZE3_Msk\n#define DSI_LPMCCR_LPSIZE4_Pos        (20U)\n#define DSI_LPMCCR_LPSIZE4_Msk        (0x1U << DSI_LPMCCR_LPSIZE4_Pos)         /*!< 0x00100000 */\n#define DSI_LPMCCR_LPSIZE4            DSI_LPMCCR_LPSIZE4_Msk\n#define DSI_LPMCCR_LPSIZE5_Pos        (21U)\n#define DSI_LPMCCR_LPSIZE5_Msk        (0x1U << DSI_LPMCCR_LPSIZE5_Pos)         /*!< 0x00200000 */\n#define DSI_LPMCCR_LPSIZE5            DSI_LPMCCR_LPSIZE5_Msk\n#define DSI_LPMCCR_LPSIZE6_Pos        (22U)\n#define DSI_LPMCCR_LPSIZE6_Msk        (0x1U << DSI_LPMCCR_LPSIZE6_Pos)         /*!< 0x00400000 */\n#define DSI_LPMCCR_LPSIZE6            DSI_LPMCCR_LPSIZE6_Msk\n#define DSI_LPMCCR_LPSIZE7_Pos        (23U)\n#define DSI_LPMCCR_LPSIZE7_Msk        (0x1U << DSI_LPMCCR_LPSIZE7_Pos)         /*!< 0x00800000 */\n#define DSI_LPMCCR_LPSIZE7            DSI_LPMCCR_LPSIZE7_Msk\n\n/*******************  Bit definition for DSI_VMCCR register  **************/\n#define DSI_VMCCR_VMT_Pos             (0U)\n#define DSI_VMCCR_VMT_Msk             (0x3U << DSI_VMCCR_VMT_Pos)              /*!< 0x00000003 */\n#define DSI_VMCCR_VMT                 DSI_VMCCR_VMT_Msk                        /*!< Video Mode Type */\n#define DSI_VMCCR_VMT0_Pos            (0U)\n#define DSI_VMCCR_VMT0_Msk            (0x1U << DSI_VMCCR_VMT0_Pos)             /*!< 0x00000001 */\n#define DSI_VMCCR_VMT0                DSI_VMCCR_VMT0_Msk\n#define DSI_VMCCR_VMT1_Pos            (1U)\n#define DSI_VMCCR_VMT1_Msk            (0x1U << DSI_VMCCR_VMT1_Pos)             /*!< 0x00000002 */\n#define DSI_VMCCR_VMT1                DSI_VMCCR_VMT1_Msk\n\n#define DSI_VMCCR_LPVSAE_Pos          (8U)\n#define DSI_VMCCR_LPVSAE_Msk          (0x1U << DSI_VMCCR_LPVSAE_Pos)           /*!< 0x00000100 */\n#define DSI_VMCCR_LPVSAE              DSI_VMCCR_LPVSAE_Msk                     /*!< Low-power Vertical Sync time Enable */\n#define DSI_VMCCR_LPVBPE_Pos          (9U)\n#define DSI_VMCCR_LPVBPE_Msk          (0x1U << DSI_VMCCR_LPVBPE_Pos)           /*!< 0x00000200 */\n#define DSI_VMCCR_LPVBPE              DSI_VMCCR_LPVBPE_Msk                     /*!< Low-power Vertical Back-porch Enable */\n#define DSI_VMCCR_LPVFPE_Pos          (10U)\n#define DSI_VMCCR_LPVFPE_Msk          (0x1U << DSI_VMCCR_LPVFPE_Pos)           /*!< 0x00000400 */\n#define DSI_VMCCR_LPVFPE              DSI_VMCCR_LPVFPE_Msk                     /*!< Low-power Vertical Front-porch Enable */\n#define DSI_VMCCR_LPVAE_Pos           (11U)\n#define DSI_VMCCR_LPVAE_Msk           (0x1U << DSI_VMCCR_LPVAE_Pos)            /*!< 0x00000800 */\n#define DSI_VMCCR_LPVAE               DSI_VMCCR_LPVAE_Msk                      /*!< Low-power Vertical Active Enable */\n#define DSI_VMCCR_LPHBPE_Pos          (12U)\n#define DSI_VMCCR_LPHBPE_Msk          (0x1U << DSI_VMCCR_LPHBPE_Pos)           /*!< 0x00001000 */\n#define DSI_VMCCR_LPHBPE              DSI_VMCCR_LPHBPE_Msk                     /*!< Low-power Horizontal Back-porch Enable */\n#define DSI_VMCCR_LPHFE_Pos           (13U)\n#define DSI_VMCCR_LPHFE_Msk           (0x1U << DSI_VMCCR_LPHFE_Pos)            /*!< 0x00002000 */\n#define DSI_VMCCR_LPHFE               DSI_VMCCR_LPHFE_Msk                      /*!< Low-power Horizontal Front-porch Enable */\n#define DSI_VMCCR_FBTAAE_Pos          (14U)\n#define DSI_VMCCR_FBTAAE_Msk          (0x1U << DSI_VMCCR_FBTAAE_Pos)           /*!< 0x00004000 */\n#define DSI_VMCCR_FBTAAE              DSI_VMCCR_FBTAAE_Msk                     /*!< Frame BTA Acknowledge Enable */\n#define DSI_VMCCR_LPCE_Pos            (15U)\n#define DSI_VMCCR_LPCE_Msk            (0x1U << DSI_VMCCR_LPCE_Pos)             /*!< 0x00008000 */\n#define DSI_VMCCR_LPCE                DSI_VMCCR_LPCE_Msk                       /*!< Low-power Command Enable */\n\n/*******************  Bit definition for DSI_VPCCR register  **************/\n#define DSI_VPCCR_VPSIZE_Pos          (0U)\n#define DSI_VPCCR_VPSIZE_Msk          (0x3FFFU << DSI_VPCCR_VPSIZE_Pos)        /*!< 0x00003FFF */\n#define DSI_VPCCR_VPSIZE              DSI_VPCCR_VPSIZE_Msk                     /*!< Video Packet Size */\n#define DSI_VPCCR_VPSIZE0_Pos         (0U)\n#define DSI_VPCCR_VPSIZE0_Msk         (0x1U << DSI_VPCCR_VPSIZE0_Pos)          /*!< 0x00000001 */\n#define DSI_VPCCR_VPSIZE0             DSI_VPCCR_VPSIZE0_Msk\n#define DSI_VPCCR_VPSIZE1_Pos         (1U)\n#define DSI_VPCCR_VPSIZE1_Msk         (0x1U << DSI_VPCCR_VPSIZE1_Pos)          /*!< 0x00000002 */\n#define DSI_VPCCR_VPSIZE1             DSI_VPCCR_VPSIZE1_Msk\n#define DSI_VPCCR_VPSIZE2_Pos         (2U)\n#define DSI_VPCCR_VPSIZE2_Msk         (0x1U << DSI_VPCCR_VPSIZE2_Pos)          /*!< 0x00000004 */\n#define DSI_VPCCR_VPSIZE2             DSI_VPCCR_VPSIZE2_Msk\n#define DSI_VPCCR_VPSIZE3_Pos         (3U)\n#define DSI_VPCCR_VPSIZE3_Msk         (0x1U << DSI_VPCCR_VPSIZE3_Pos)          /*!< 0x00000008 */\n#define DSI_VPCCR_VPSIZE3             DSI_VPCCR_VPSIZE3_Msk\n#define DSI_VPCCR_VPSIZE4_Pos         (4U)\n#define DSI_VPCCR_VPSIZE4_Msk         (0x1U << DSI_VPCCR_VPSIZE4_Pos)          /*!< 0x00000010 */\n#define DSI_VPCCR_VPSIZE4             DSI_VPCCR_VPSIZE4_Msk\n#define DSI_VPCCR_VPSIZE5_Pos         (5U)\n#define DSI_VPCCR_VPSIZE5_Msk         (0x1U << DSI_VPCCR_VPSIZE5_Pos)          /*!< 0x00000020 */\n#define DSI_VPCCR_VPSIZE5             DSI_VPCCR_VPSIZE5_Msk\n#define DSI_VPCCR_VPSIZE6_Pos         (6U)\n#define DSI_VPCCR_VPSIZE6_Msk         (0x1U << DSI_VPCCR_VPSIZE6_Pos)          /*!< 0x00000040 */\n#define DSI_VPCCR_VPSIZE6             DSI_VPCCR_VPSIZE6_Msk\n#define DSI_VPCCR_VPSIZE7_Pos         (7U)\n#define DSI_VPCCR_VPSIZE7_Msk         (0x1U << DSI_VPCCR_VPSIZE7_Pos)          /*!< 0x00000080 */\n#define DSI_VPCCR_VPSIZE7             DSI_VPCCR_VPSIZE7_Msk\n#define DSI_VPCCR_VPSIZE8_Pos         (8U)\n#define DSI_VPCCR_VPSIZE8_Msk         (0x1U << DSI_VPCCR_VPSIZE8_Pos)          /*!< 0x00000100 */\n#define DSI_VPCCR_VPSIZE8             DSI_VPCCR_VPSIZE8_Msk\n#define DSI_VPCCR_VPSIZE9_Pos         (9U)\n#define DSI_VPCCR_VPSIZE9_Msk         (0x1U << DSI_VPCCR_VPSIZE9_Pos)          /*!< 0x00000200 */\n#define DSI_VPCCR_VPSIZE9             DSI_VPCCR_VPSIZE9_Msk\n#define DSI_VPCCR_VPSIZE10_Pos        (10U)\n#define DSI_VPCCR_VPSIZE10_Msk        (0x1U << DSI_VPCCR_VPSIZE10_Pos)         /*!< 0x00000400 */\n#define DSI_VPCCR_VPSIZE10            DSI_VPCCR_VPSIZE10_Msk\n#define DSI_VPCCR_VPSIZE11_Pos        (11U)\n#define DSI_VPCCR_VPSIZE11_Msk        (0x1U << DSI_VPCCR_VPSIZE11_Pos)         /*!< 0x00000800 */\n#define DSI_VPCCR_VPSIZE11            DSI_VPCCR_VPSIZE11_Msk\n#define DSI_VPCCR_VPSIZE12_Pos        (12U)\n#define DSI_VPCCR_VPSIZE12_Msk        (0x1U << DSI_VPCCR_VPSIZE12_Pos)         /*!< 0x00001000 */\n#define DSI_VPCCR_VPSIZE12            DSI_VPCCR_VPSIZE12_Msk\n#define DSI_VPCCR_VPSIZE13_Pos        (13U)\n#define DSI_VPCCR_VPSIZE13_Msk        (0x1U << DSI_VPCCR_VPSIZE13_Pos)         /*!< 0x00002000 */\n#define DSI_VPCCR_VPSIZE13            DSI_VPCCR_VPSIZE13_Msk\n\n/*******************  Bit definition for DSI_VCCCR register  **************/\n#define DSI_VCCCR_NUMC_Pos            (0U)\n#define DSI_VCCCR_NUMC_Msk            (0x1FFFU << DSI_VCCCR_NUMC_Pos)          /*!< 0x00001FFF */\n#define DSI_VCCCR_NUMC                DSI_VCCCR_NUMC_Msk                       /*!< Number of Chunks */\n#define DSI_VCCCR_NUMC0_Pos           (0U)\n#define DSI_VCCCR_NUMC0_Msk           (0x1U << DSI_VCCCR_NUMC0_Pos)            /*!< 0x00000001 */\n#define DSI_VCCCR_NUMC0               DSI_VCCCR_NUMC0_Msk\n#define DSI_VCCCR_NUMC1_Pos           (1U)\n#define DSI_VCCCR_NUMC1_Msk           (0x1U << DSI_VCCCR_NUMC1_Pos)            /*!< 0x00000002 */\n#define DSI_VCCCR_NUMC1               DSI_VCCCR_NUMC1_Msk\n#define DSI_VCCCR_NUMC2_Pos           (2U)\n#define DSI_VCCCR_NUMC2_Msk           (0x1U << DSI_VCCCR_NUMC2_Pos)            /*!< 0x00000004 */\n#define DSI_VCCCR_NUMC2               DSI_VCCCR_NUMC2_Msk\n#define DSI_VCCCR_NUMC3_Pos           (3U)\n#define DSI_VCCCR_NUMC3_Msk           (0x1U << DSI_VCCCR_NUMC3_Pos)            /*!< 0x00000008 */\n#define DSI_VCCCR_NUMC3               DSI_VCCCR_NUMC3_Msk\n#define DSI_VCCCR_NUMC4_Pos           (4U)\n#define DSI_VCCCR_NUMC4_Msk           (0x1U << DSI_VCCCR_NUMC4_Pos)            /*!< 0x00000010 */\n#define DSI_VCCCR_NUMC4               DSI_VCCCR_NUMC4_Msk\n#define DSI_VCCCR_NUMC5_Pos           (5U)\n#define DSI_VCCCR_NUMC5_Msk           (0x1U << DSI_VCCCR_NUMC5_Pos)            /*!< 0x00000020 */\n#define DSI_VCCCR_NUMC5               DSI_VCCCR_NUMC5_Msk\n#define DSI_VCCCR_NUMC6_Pos           (6U)\n#define DSI_VCCCR_NUMC6_Msk           (0x1U << DSI_VCCCR_NUMC6_Pos)            /*!< 0x00000040 */\n#define DSI_VCCCR_NUMC6               DSI_VCCCR_NUMC6_Msk\n#define DSI_VCCCR_NUMC7_Pos           (7U)\n#define DSI_VCCCR_NUMC7_Msk           (0x1U << DSI_VCCCR_NUMC7_Pos)            /*!< 0x00000080 */\n#define DSI_VCCCR_NUMC7               DSI_VCCCR_NUMC7_Msk\n#define DSI_VCCCR_NUMC8_Pos           (8U)\n#define DSI_VCCCR_NUMC8_Msk           (0x1U << DSI_VCCCR_NUMC8_Pos)            /*!< 0x00000100 */\n#define DSI_VCCCR_NUMC8               DSI_VCCCR_NUMC8_Msk\n#define DSI_VCCCR_NUMC9_Pos           (9U)\n#define DSI_VCCCR_NUMC9_Msk           (0x1U << DSI_VCCCR_NUMC9_Pos)            /*!< 0x00000200 */\n#define DSI_VCCCR_NUMC9               DSI_VCCCR_NUMC9_Msk\n#define DSI_VCCCR_NUMC10_Pos          (10U)\n#define DSI_VCCCR_NUMC10_Msk          (0x1U << DSI_VCCCR_NUMC10_Pos)           /*!< 0x00000400 */\n#define DSI_VCCCR_NUMC10              DSI_VCCCR_NUMC10_Msk\n#define DSI_VCCCR_NUMC11_Pos          (11U)\n#define DSI_VCCCR_NUMC11_Msk          (0x1U << DSI_VCCCR_NUMC11_Pos)           /*!< 0x00000800 */\n#define DSI_VCCCR_NUMC11              DSI_VCCCR_NUMC11_Msk\n#define DSI_VCCCR_NUMC12_Pos          (12U)\n#define DSI_VCCCR_NUMC12_Msk          (0x1U << DSI_VCCCR_NUMC12_Pos)           /*!< 0x00001000 */\n#define DSI_VCCCR_NUMC12              DSI_VCCCR_NUMC12_Msk\n\n/*******************  Bit definition for DSI_VNPCCR register  *************/\n#define DSI_VNPCCR_NPSIZE_Pos         (0U)\n#define DSI_VNPCCR_NPSIZE_Msk         (0x1FFFU << DSI_VNPCCR_NPSIZE_Pos)       /*!< 0x00001FFF */\n#define DSI_VNPCCR_NPSIZE             DSI_VNPCCR_NPSIZE_Msk                    /*!< Number of Chunks */\n#define DSI_VNPCCR_NPSIZE0_Pos        (0U)\n#define DSI_VNPCCR_NPSIZE0_Msk        (0x1U << DSI_VNPCCR_NPSIZE0_Pos)         /*!< 0x00000001 */\n#define DSI_VNPCCR_NPSIZE0            DSI_VNPCCR_NPSIZE0_Msk\n#define DSI_VNPCCR_NPSIZE1_Pos        (1U)\n#define DSI_VNPCCR_NPSIZE1_Msk        (0x1U << DSI_VNPCCR_NPSIZE1_Pos)         /*!< 0x00000002 */\n#define DSI_VNPCCR_NPSIZE1            DSI_VNPCCR_NPSIZE1_Msk\n#define DSI_VNPCCR_NPSIZE2_Pos        (2U)\n#define DSI_VNPCCR_NPSIZE2_Msk        (0x1U << DSI_VNPCCR_NPSIZE2_Pos)         /*!< 0x00000004 */\n#define DSI_VNPCCR_NPSIZE2            DSI_VNPCCR_NPSIZE2_Msk\n#define DSI_VNPCCR_NPSIZE3_Pos        (3U)\n#define DSI_VNPCCR_NPSIZE3_Msk        (0x1U << DSI_VNPCCR_NPSIZE3_Pos)         /*!< 0x00000008 */\n#define DSI_VNPCCR_NPSIZE3            DSI_VNPCCR_NPSIZE3_Msk\n#define DSI_VNPCCR_NPSIZE4_Pos        (4U)\n#define DSI_VNPCCR_NPSIZE4_Msk        (0x1U << DSI_VNPCCR_NPSIZE4_Pos)         /*!< 0x00000010 */\n#define DSI_VNPCCR_NPSIZE4            DSI_VNPCCR_NPSIZE4_Msk\n#define DSI_VNPCCR_NPSIZE5_Pos        (5U)\n#define DSI_VNPCCR_NPSIZE5_Msk        (0x1U << DSI_VNPCCR_NPSIZE5_Pos)         /*!< 0x00000020 */\n#define DSI_VNPCCR_NPSIZE5            DSI_VNPCCR_NPSIZE5_Msk\n#define DSI_VNPCCR_NPSIZE6_Pos        (6U)\n#define DSI_VNPCCR_NPSIZE6_Msk        (0x1U << DSI_VNPCCR_NPSIZE6_Pos)         /*!< 0x00000040 */\n#define DSI_VNPCCR_NPSIZE6            DSI_VNPCCR_NPSIZE6_Msk\n#define DSI_VNPCCR_NPSIZE7_Pos        (7U)\n#define DSI_VNPCCR_NPSIZE7_Msk        (0x1U << DSI_VNPCCR_NPSIZE7_Pos)         /*!< 0x00000080 */\n#define DSI_VNPCCR_NPSIZE7            DSI_VNPCCR_NPSIZE7_Msk\n#define DSI_VNPCCR_NPSIZE8_Pos        (8U)\n#define DSI_VNPCCR_NPSIZE8_Msk        (0x1U << DSI_VNPCCR_NPSIZE8_Pos)         /*!< 0x00000100 */\n#define DSI_VNPCCR_NPSIZE8            DSI_VNPCCR_NPSIZE8_Msk\n#define DSI_VNPCCR_NPSIZE9_Pos        (9U)\n#define DSI_VNPCCR_NPSIZE9_Msk        (0x1U << DSI_VNPCCR_NPSIZE9_Pos)         /*!< 0x00000200 */\n#define DSI_VNPCCR_NPSIZE9            DSI_VNPCCR_NPSIZE9_Msk\n#define DSI_VNPCCR_NPSIZE10_Pos       (10U)\n#define DSI_VNPCCR_NPSIZE10_Msk       (0x1U << DSI_VNPCCR_NPSIZE10_Pos)        /*!< 0x00000400 */\n#define DSI_VNPCCR_NPSIZE10           DSI_VNPCCR_NPSIZE10_Msk\n#define DSI_VNPCCR_NPSIZE11_Pos       (11U)\n#define DSI_VNPCCR_NPSIZE11_Msk       (0x1U << DSI_VNPCCR_NPSIZE11_Pos)        /*!< 0x00000800 */\n#define DSI_VNPCCR_NPSIZE11           DSI_VNPCCR_NPSIZE11_Msk\n#define DSI_VNPCCR_NPSIZE12_Pos       (12U)\n#define DSI_VNPCCR_NPSIZE12_Msk       (0x1U << DSI_VNPCCR_NPSIZE12_Pos)        /*!< 0x00001000 */\n#define DSI_VNPCCR_NPSIZE12           DSI_VNPCCR_NPSIZE12_Msk\n\n/*******************  Bit definition for DSI_VHSACCR register  ************/\n#define DSI_VHSACCR_HSA_Pos           (0U)\n#define DSI_VHSACCR_HSA_Msk           (0xFFFU << DSI_VHSACCR_HSA_Pos)          /*!< 0x00000FFF */\n#define DSI_VHSACCR_HSA               DSI_VHSACCR_HSA_Msk                      /*!< Horizontal Synchronism Active duration */\n#define DSI_VHSACCR_HSA0_Pos          (0U)\n#define DSI_VHSACCR_HSA0_Msk          (0x1U << DSI_VHSACCR_HSA0_Pos)           /*!< 0x00000001 */\n#define DSI_VHSACCR_HSA0              DSI_VHSACCR_HSA0_Msk\n#define DSI_VHSACCR_HSA1_Pos          (1U)\n#define DSI_VHSACCR_HSA1_Msk          (0x1U << DSI_VHSACCR_HSA1_Pos)           /*!< 0x00000002 */\n#define DSI_VHSACCR_HSA1              DSI_VHSACCR_HSA1_Msk\n#define DSI_VHSACCR_HSA2_Pos          (2U)\n#define DSI_VHSACCR_HSA2_Msk          (0x1U << DSI_VHSACCR_HSA2_Pos)           /*!< 0x00000004 */\n#define DSI_VHSACCR_HSA2              DSI_VHSACCR_HSA2_Msk\n#define DSI_VHSACCR_HSA3_Pos          (3U)\n#define DSI_VHSACCR_HSA3_Msk          (0x1U << DSI_VHSACCR_HSA3_Pos)           /*!< 0x00000008 */\n#define DSI_VHSACCR_HSA3              DSI_VHSACCR_HSA3_Msk\n#define DSI_VHSACCR_HSA4_Pos          (4U)\n#define DSI_VHSACCR_HSA4_Msk          (0x1U << DSI_VHSACCR_HSA4_Pos)           /*!< 0x00000010 */\n#define DSI_VHSACCR_HSA4              DSI_VHSACCR_HSA4_Msk\n#define DSI_VHSACCR_HSA5_Pos          (5U)\n#define DSI_VHSACCR_HSA5_Msk          (0x1U << DSI_VHSACCR_HSA5_Pos)           /*!< 0x00000020 */\n#define DSI_VHSACCR_HSA5              DSI_VHSACCR_HSA5_Msk\n#define DSI_VHSACCR_HSA6_Pos          (6U)\n#define DSI_VHSACCR_HSA6_Msk          (0x1U << DSI_VHSACCR_HSA6_Pos)           /*!< 0x00000040 */\n#define DSI_VHSACCR_HSA6              DSI_VHSACCR_HSA6_Msk\n#define DSI_VHSACCR_HSA7_Pos          (7U)\n#define DSI_VHSACCR_HSA7_Msk          (0x1U << DSI_VHSACCR_HSA7_Pos)           /*!< 0x00000080 */\n#define DSI_VHSACCR_HSA7              DSI_VHSACCR_HSA7_Msk\n#define DSI_VHSACCR_HSA8_Pos          (8U)\n#define DSI_VHSACCR_HSA8_Msk          (0x1U << DSI_VHSACCR_HSA8_Pos)           /*!< 0x00000100 */\n#define DSI_VHSACCR_HSA8              DSI_VHSACCR_HSA8_Msk\n#define DSI_VHSACCR_HSA9_Pos          (9U)\n#define DSI_VHSACCR_HSA9_Msk          (0x1U << DSI_VHSACCR_HSA9_Pos)           /*!< 0x00000200 */\n#define DSI_VHSACCR_HSA9              DSI_VHSACCR_HSA9_Msk\n#define DSI_VHSACCR_HSA10_Pos         (10U)\n#define DSI_VHSACCR_HSA10_Msk         (0x1U << DSI_VHSACCR_HSA10_Pos)          /*!< 0x00000400 */\n#define DSI_VHSACCR_HSA10             DSI_VHSACCR_HSA10_Msk\n#define DSI_VHSACCR_HSA11_Pos         (11U)\n#define DSI_VHSACCR_HSA11_Msk         (0x1U << DSI_VHSACCR_HSA11_Pos)          /*!< 0x00000800 */\n#define DSI_VHSACCR_HSA11             DSI_VHSACCR_HSA11_Msk\n\n/*******************  Bit definition for DSI_VHBPCCR register  ************/\n#define DSI_VHBPCCR_HBP_Pos           (0U)\n#define DSI_VHBPCCR_HBP_Msk           (0xFFFU << DSI_VHBPCCR_HBP_Pos)          /*!< 0x00000FFF */\n#define DSI_VHBPCCR_HBP               DSI_VHBPCCR_HBP_Msk                      /*!< Horizontal Back-Porch duration */\n#define DSI_VHBPCCR_HBP0_Pos          (0U)\n#define DSI_VHBPCCR_HBP0_Msk          (0x1U << DSI_VHBPCCR_HBP0_Pos)           /*!< 0x00000001 */\n#define DSI_VHBPCCR_HBP0              DSI_VHBPCCR_HBP0_Msk\n#define DSI_VHBPCCR_HBP1_Pos          (1U)\n#define DSI_VHBPCCR_HBP1_Msk          (0x1U << DSI_VHBPCCR_HBP1_Pos)           /*!< 0x00000002 */\n#define DSI_VHBPCCR_HBP1              DSI_VHBPCCR_HBP1_Msk\n#define DSI_VHBPCCR_HBP2_Pos          (2U)\n#define DSI_VHBPCCR_HBP2_Msk          (0x1U << DSI_VHBPCCR_HBP2_Pos)           /*!< 0x00000004 */\n#define DSI_VHBPCCR_HBP2              DSI_VHBPCCR_HBP2_Msk\n#define DSI_VHBPCCR_HBP3_Pos          (3U)\n#define DSI_VHBPCCR_HBP3_Msk          (0x1U << DSI_VHBPCCR_HBP3_Pos)           /*!< 0x00000008 */\n#define DSI_VHBPCCR_HBP3              DSI_VHBPCCR_HBP3_Msk\n#define DSI_VHBPCCR_HBP4_Pos          (4U)\n#define DSI_VHBPCCR_HBP4_Msk          (0x1U << DSI_VHBPCCR_HBP4_Pos)           /*!< 0x00000010 */\n#define DSI_VHBPCCR_HBP4              DSI_VHBPCCR_HBP4_Msk\n#define DSI_VHBPCCR_HBP5_Pos          (5U)\n#define DSI_VHBPCCR_HBP5_Msk          (0x1U << DSI_VHBPCCR_HBP5_Pos)           /*!< 0x00000020 */\n#define DSI_VHBPCCR_HBP5              DSI_VHBPCCR_HBP5_Msk\n#define DSI_VHBPCCR_HBP6_Pos          (6U)\n#define DSI_VHBPCCR_HBP6_Msk          (0x1U << DSI_VHBPCCR_HBP6_Pos)           /*!< 0x00000040 */\n#define DSI_VHBPCCR_HBP6              DSI_VHBPCCR_HBP6_Msk\n#define DSI_VHBPCCR_HBP7_Pos          (7U)\n#define DSI_VHBPCCR_HBP7_Msk          (0x1U << DSI_VHBPCCR_HBP7_Pos)           /*!< 0x00000080 */\n#define DSI_VHBPCCR_HBP7              DSI_VHBPCCR_HBP7_Msk\n#define DSI_VHBPCCR_HBP8_Pos          (8U)\n#define DSI_VHBPCCR_HBP8_Msk          (0x1U << DSI_VHBPCCR_HBP8_Pos)           /*!< 0x00000100 */\n#define DSI_VHBPCCR_HBP8              DSI_VHBPCCR_HBP8_Msk\n#define DSI_VHBPCCR_HBP9_Pos          (9U)\n#define DSI_VHBPCCR_HBP9_Msk          (0x1U << DSI_VHBPCCR_HBP9_Pos)           /*!< 0x00000200 */\n#define DSI_VHBPCCR_HBP9              DSI_VHBPCCR_HBP9_Msk\n#define DSI_VHBPCCR_HBP10_Pos         (10U)\n#define DSI_VHBPCCR_HBP10_Msk         (0x1U << DSI_VHBPCCR_HBP10_Pos)          /*!< 0x00000400 */\n#define DSI_VHBPCCR_HBP10             DSI_VHBPCCR_HBP10_Msk\n#define DSI_VHBPCCR_HBP11_Pos         (11U)\n#define DSI_VHBPCCR_HBP11_Msk         (0x1U << DSI_VHBPCCR_HBP11_Pos)          /*!< 0x00000800 */\n#define DSI_VHBPCCR_HBP11             DSI_VHBPCCR_HBP11_Msk\n\n/*******************  Bit definition for DSI_VLCCR register  **************/\n#define DSI_VLCCR_HLINE_Pos           (0U)\n#define DSI_VLCCR_HLINE_Msk           (0x7FFFU << DSI_VLCCR_HLINE_Pos)         /*!< 0x00007FFF */\n#define DSI_VLCCR_HLINE               DSI_VLCCR_HLINE_Msk                      /*!< Horizontal Line duration */\n#define DSI_VLCCR_HLINE0_Pos          (0U)\n#define DSI_VLCCR_HLINE0_Msk          (0x1U << DSI_VLCCR_HLINE0_Pos)           /*!< 0x00000001 */\n#define DSI_VLCCR_HLINE0              DSI_VLCCR_HLINE0_Msk\n#define DSI_VLCCR_HLINE1_Pos          (1U)\n#define DSI_VLCCR_HLINE1_Msk          (0x1U << DSI_VLCCR_HLINE1_Pos)           /*!< 0x00000002 */\n#define DSI_VLCCR_HLINE1              DSI_VLCCR_HLINE1_Msk\n#define DSI_VLCCR_HLINE2_Pos          (2U)\n#define DSI_VLCCR_HLINE2_Msk          (0x1U << DSI_VLCCR_HLINE2_Pos)           /*!< 0x00000004 */\n#define DSI_VLCCR_HLINE2              DSI_VLCCR_HLINE2_Msk\n#define DSI_VLCCR_HLINE3_Pos          (3U)\n#define DSI_VLCCR_HLINE3_Msk          (0x1U << DSI_VLCCR_HLINE3_Pos)           /*!< 0x00000008 */\n#define DSI_VLCCR_HLINE3              DSI_VLCCR_HLINE3_Msk\n#define DSI_VLCCR_HLINE4_Pos          (4U)\n#define DSI_VLCCR_HLINE4_Msk          (0x1U << DSI_VLCCR_HLINE4_Pos)           /*!< 0x00000010 */\n#define DSI_VLCCR_HLINE4              DSI_VLCCR_HLINE4_Msk\n#define DSI_VLCCR_HLINE5_Pos          (5U)\n#define DSI_VLCCR_HLINE5_Msk          (0x1U << DSI_VLCCR_HLINE5_Pos)           /*!< 0x00000020 */\n#define DSI_VLCCR_HLINE5              DSI_VLCCR_HLINE5_Msk\n#define DSI_VLCCR_HLINE6_Pos          (6U)\n#define DSI_VLCCR_HLINE6_Msk          (0x1U << DSI_VLCCR_HLINE6_Pos)           /*!< 0x00000040 */\n#define DSI_VLCCR_HLINE6              DSI_VLCCR_HLINE6_Msk\n#define DSI_VLCCR_HLINE7_Pos          (7U)\n#define DSI_VLCCR_HLINE7_Msk          (0x1U << DSI_VLCCR_HLINE7_Pos)           /*!< 0x00000080 */\n#define DSI_VLCCR_HLINE7              DSI_VLCCR_HLINE7_Msk\n#define DSI_VLCCR_HLINE8_Pos          (8U)\n#define DSI_VLCCR_HLINE8_Msk          (0x1U << DSI_VLCCR_HLINE8_Pos)           /*!< 0x00000100 */\n#define DSI_VLCCR_HLINE8              DSI_VLCCR_HLINE8_Msk\n#define DSI_VLCCR_HLINE9_Pos          (9U)\n#define DSI_VLCCR_HLINE9_Msk          (0x1U << DSI_VLCCR_HLINE9_Pos)           /*!< 0x00000200 */\n#define DSI_VLCCR_HLINE9              DSI_VLCCR_HLINE9_Msk\n#define DSI_VLCCR_HLINE10_Pos         (10U)\n#define DSI_VLCCR_HLINE10_Msk         (0x1U << DSI_VLCCR_HLINE10_Pos)          /*!< 0x00000400 */\n#define DSI_VLCCR_HLINE10             DSI_VLCCR_HLINE10_Msk\n#define DSI_VLCCR_HLINE11_Pos         (11U)\n#define DSI_VLCCR_HLINE11_Msk         (0x1U << DSI_VLCCR_HLINE11_Pos)          /*!< 0x00000800 */\n#define DSI_VLCCR_HLINE11             DSI_VLCCR_HLINE11_Msk\n#define DSI_VLCCR_HLINE12_Pos         (12U)\n#define DSI_VLCCR_HLINE12_Msk         (0x1U << DSI_VLCCR_HLINE12_Pos)          /*!< 0x00001000 */\n#define DSI_VLCCR_HLINE12             DSI_VLCCR_HLINE12_Msk\n#define DSI_VLCCR_HLINE13_Pos         (13U)\n#define DSI_VLCCR_HLINE13_Msk         (0x1U << DSI_VLCCR_HLINE13_Pos)          /*!< 0x00002000 */\n#define DSI_VLCCR_HLINE13             DSI_VLCCR_HLINE13_Msk\n#define DSI_VLCCR_HLINE14_Pos         (14U)\n#define DSI_VLCCR_HLINE14_Msk         (0x1U << DSI_VLCCR_HLINE14_Pos)          /*!< 0x00004000 */\n#define DSI_VLCCR_HLINE14             DSI_VLCCR_HLINE14_Msk\n\n/*******************  Bit definition for DSI_VVSACCR register  ***************/\n#define DSI_VVSACCR_VSA_Pos           (0U)\n#define DSI_VVSACCR_VSA_Msk           (0x3FFU << DSI_VVSACCR_VSA_Pos)          /*!< 0x000003FF */\n#define DSI_VVSACCR_VSA               DSI_VVSACCR_VSA_Msk                      /*!< Vertical Synchronism Active duration */\n#define DSI_VVSACCR_VSA0_Pos          (0U)\n#define DSI_VVSACCR_VSA0_Msk          (0x1U << DSI_VVSACCR_VSA0_Pos)           /*!< 0x00000001 */\n#define DSI_VVSACCR_VSA0              DSI_VVSACCR_VSA0_Msk\n#define DSI_VVSACCR_VSA1_Pos          (1U)\n#define DSI_VVSACCR_VSA1_Msk          (0x1U << DSI_VVSACCR_VSA1_Pos)           /*!< 0x00000002 */\n#define DSI_VVSACCR_VSA1              DSI_VVSACCR_VSA1_Msk\n#define DSI_VVSACCR_VSA2_Pos          (2U)\n#define DSI_VVSACCR_VSA2_Msk          (0x1U << DSI_VVSACCR_VSA2_Pos)           /*!< 0x00000004 */\n#define DSI_VVSACCR_VSA2              DSI_VVSACCR_VSA2_Msk\n#define DSI_VVSACCR_VSA3_Pos          (3U)\n#define DSI_VVSACCR_VSA3_Msk          (0x1U << DSI_VVSACCR_VSA3_Pos)           /*!< 0x00000008 */\n#define DSI_VVSACCR_VSA3              DSI_VVSACCR_VSA3_Msk\n#define DSI_VVSACCR_VSA4_Pos          (4U)\n#define DSI_VVSACCR_VSA4_Msk          (0x1U << DSI_VVSACCR_VSA4_Pos)           /*!< 0x00000010 */\n#define DSI_VVSACCR_VSA4              DSI_VVSACCR_VSA4_Msk\n#define DSI_VVSACCR_VSA5_Pos          (5U)\n#define DSI_VVSACCR_VSA5_Msk          (0x1U << DSI_VVSACCR_VSA5_Pos)           /*!< 0x00000020 */\n#define DSI_VVSACCR_VSA5              DSI_VVSACCR_VSA5_Msk\n#define DSI_VVSACCR_VSA6_Pos          (6U)\n#define DSI_VVSACCR_VSA6_Msk          (0x1U << DSI_VVSACCR_VSA6_Pos)           /*!< 0x00000040 */\n#define DSI_VVSACCR_VSA6              DSI_VVSACCR_VSA6_Msk\n#define DSI_VVSACCR_VSA7_Pos          (7U)\n#define DSI_VVSACCR_VSA7_Msk          (0x1U << DSI_VVSACCR_VSA7_Pos)           /*!< 0x00000080 */\n#define DSI_VVSACCR_VSA7              DSI_VVSACCR_VSA7_Msk\n#define DSI_VVSACCR_VSA8_Pos          (8U)\n#define DSI_VVSACCR_VSA8_Msk          (0x1U << DSI_VVSACCR_VSA8_Pos)           /*!< 0x00000100 */\n#define DSI_VVSACCR_VSA8              DSI_VVSACCR_VSA8_Msk\n#define DSI_VVSACCR_VSA9_Pos          (9U)\n#define DSI_VVSACCR_VSA9_Msk          (0x1U << DSI_VVSACCR_VSA9_Pos)           /*!< 0x00000200 */\n#define DSI_VVSACCR_VSA9              DSI_VVSACCR_VSA9_Msk\n\n/*******************  Bit definition for DSI_VVBPCCR register  ************/\n#define DSI_VVBPCCR_VBP_Pos           (0U)\n#define DSI_VVBPCCR_VBP_Msk           (0x3FFU << DSI_VVBPCCR_VBP_Pos)          /*!< 0x000003FF */\n#define DSI_VVBPCCR_VBP               DSI_VVBPCCR_VBP_Msk                      /*!< Vertical Back-Porch duration */\n#define DSI_VVBPCCR_VBP0_Pos          (0U)\n#define DSI_VVBPCCR_VBP0_Msk          (0x1U << DSI_VVBPCCR_VBP0_Pos)           /*!< 0x00000001 */\n#define DSI_VVBPCCR_VBP0              DSI_VVBPCCR_VBP0_Msk\n#define DSI_VVBPCCR_VBP1_Pos          (1U)\n#define DSI_VVBPCCR_VBP1_Msk          (0x1U << DSI_VVBPCCR_VBP1_Pos)           /*!< 0x00000002 */\n#define DSI_VVBPCCR_VBP1              DSI_VVBPCCR_VBP1_Msk\n#define DSI_VVBPCCR_VBP2_Pos          (2U)\n#define DSI_VVBPCCR_VBP2_Msk          (0x1U << DSI_VVBPCCR_VBP2_Pos)           /*!< 0x00000004 */\n#define DSI_VVBPCCR_VBP2              DSI_VVBPCCR_VBP2_Msk\n#define DSI_VVBPCCR_VBP3_Pos          (3U)\n#define DSI_VVBPCCR_VBP3_Msk          (0x1U << DSI_VVBPCCR_VBP3_Pos)           /*!< 0x00000008 */\n#define DSI_VVBPCCR_VBP3              DSI_VVBPCCR_VBP3_Msk\n#define DSI_VVBPCCR_VBP4_Pos          (4U)\n#define DSI_VVBPCCR_VBP4_Msk          (0x1U << DSI_VVBPCCR_VBP4_Pos)           /*!< 0x00000010 */\n#define DSI_VVBPCCR_VBP4              DSI_VVBPCCR_VBP4_Msk\n#define DSI_VVBPCCR_VBP5_Pos          (5U)\n#define DSI_VVBPCCR_VBP5_Msk          (0x1U << DSI_VVBPCCR_VBP5_Pos)           /*!< 0x00000020 */\n#define DSI_VVBPCCR_VBP5              DSI_VVBPCCR_VBP5_Msk\n#define DSI_VVBPCCR_VBP6_Pos          (6U)\n#define DSI_VVBPCCR_VBP6_Msk          (0x1U << DSI_VVBPCCR_VBP6_Pos)           /*!< 0x00000040 */\n#define DSI_VVBPCCR_VBP6              DSI_VVBPCCR_VBP6_Msk\n#define DSI_VVBPCCR_VBP7_Pos          (7U)\n#define DSI_VVBPCCR_VBP7_Msk          (0x1U << DSI_VVBPCCR_VBP7_Pos)           /*!< 0x00000080 */\n#define DSI_VVBPCCR_VBP7              DSI_VVBPCCR_VBP7_Msk\n#define DSI_VVBPCCR_VBP8_Pos          (8U)\n#define DSI_VVBPCCR_VBP8_Msk          (0x1U << DSI_VVBPCCR_VBP8_Pos)           /*!< 0x00000100 */\n#define DSI_VVBPCCR_VBP8              DSI_VVBPCCR_VBP8_Msk\n#define DSI_VVBPCCR_VBP9_Pos          (9U)\n#define DSI_VVBPCCR_VBP9_Msk          (0x1U << DSI_VVBPCCR_VBP9_Pos)           /*!< 0x00000200 */\n#define DSI_VVBPCCR_VBP9              DSI_VVBPCCR_VBP9_Msk\n\n/*******************  Bit definition for DSI_VVFPCCR register  ************/\n#define DSI_VVFPCCR_VFP_Pos           (0U)\n#define DSI_VVFPCCR_VFP_Msk           (0x3FFU << DSI_VVFPCCR_VFP_Pos)          /*!< 0x000003FF */\n#define DSI_VVFPCCR_VFP               DSI_VVFPCCR_VFP_Msk                      /*!< Vertical Front-Porch duration */\n#define DSI_VVFPCCR_VFP0_Pos          (0U)\n#define DSI_VVFPCCR_VFP0_Msk          (0x1U << DSI_VVFPCCR_VFP0_Pos)           /*!< 0x00000001 */\n#define DSI_VVFPCCR_VFP0              DSI_VVFPCCR_VFP0_Msk\n#define DSI_VVFPCCR_VFP1_Pos          (1U)\n#define DSI_VVFPCCR_VFP1_Msk          (0x1U << DSI_VVFPCCR_VFP1_Pos)           /*!< 0x00000002 */\n#define DSI_VVFPCCR_VFP1              DSI_VVFPCCR_VFP1_Msk\n#define DSI_VVFPCCR_VFP2_Pos          (2U)\n#define DSI_VVFPCCR_VFP2_Msk          (0x1U << DSI_VVFPCCR_VFP2_Pos)           /*!< 0x00000004 */\n#define DSI_VVFPCCR_VFP2              DSI_VVFPCCR_VFP2_Msk\n#define DSI_VVFPCCR_VFP3_Pos          (3U)\n#define DSI_VVFPCCR_VFP3_Msk          (0x1U << DSI_VVFPCCR_VFP3_Pos)           /*!< 0x00000008 */\n#define DSI_VVFPCCR_VFP3              DSI_VVFPCCR_VFP3_Msk\n#define DSI_VVFPCCR_VFP4_Pos          (4U)\n#define DSI_VVFPCCR_VFP4_Msk          (0x1U << DSI_VVFPCCR_VFP4_Pos)           /*!< 0x00000010 */\n#define DSI_VVFPCCR_VFP4              DSI_VVFPCCR_VFP4_Msk\n#define DSI_VVFPCCR_VFP5_Pos          (5U)\n#define DSI_VVFPCCR_VFP5_Msk          (0x1U << DSI_VVFPCCR_VFP5_Pos)           /*!< 0x00000020 */\n#define DSI_VVFPCCR_VFP5              DSI_VVFPCCR_VFP5_Msk\n#define DSI_VVFPCCR_VFP6_Pos          (6U)\n#define DSI_VVFPCCR_VFP6_Msk          (0x1U << DSI_VVFPCCR_VFP6_Pos)           /*!< 0x00000040 */\n#define DSI_VVFPCCR_VFP6              DSI_VVFPCCR_VFP6_Msk\n#define DSI_VVFPCCR_VFP7_Pos          (7U)\n#define DSI_VVFPCCR_VFP7_Msk          (0x1U << DSI_VVFPCCR_VFP7_Pos)           /*!< 0x00000080 */\n#define DSI_VVFPCCR_VFP7              DSI_VVFPCCR_VFP7_Msk\n#define DSI_VVFPCCR_VFP8_Pos          (8U)\n#define DSI_VVFPCCR_VFP8_Msk          (0x1U << DSI_VVFPCCR_VFP8_Pos)           /*!< 0x00000100 */\n#define DSI_VVFPCCR_VFP8              DSI_VVFPCCR_VFP8_Msk\n#define DSI_VVFPCCR_VFP9_Pos          (9U)\n#define DSI_VVFPCCR_VFP9_Msk          (0x1U << DSI_VVFPCCR_VFP9_Pos)           /*!< 0x00000200 */\n#define DSI_VVFPCCR_VFP9              DSI_VVFPCCR_VFP9_Msk\n\n/*******************  Bit definition for DSI_VVACCR register  *************/\n#define DSI_VVACCR_VA_Pos             (0U)\n#define DSI_VVACCR_VA_Msk             (0x3FFFU << DSI_VVACCR_VA_Pos)           /*!< 0x00003FFF */\n#define DSI_VVACCR_VA                 DSI_VVACCR_VA_Msk                        /*!< Vertical Active duration */\n#define DSI_VVACCR_VA0_Pos            (0U)\n#define DSI_VVACCR_VA0_Msk            (0x1U << DSI_VVACCR_VA0_Pos)             /*!< 0x00000001 */\n#define DSI_VVACCR_VA0                DSI_VVACCR_VA0_Msk\n#define DSI_VVACCR_VA1_Pos            (1U)\n#define DSI_VVACCR_VA1_Msk            (0x1U << DSI_VVACCR_VA1_Pos)             /*!< 0x00000002 */\n#define DSI_VVACCR_VA1                DSI_VVACCR_VA1_Msk\n#define DSI_VVACCR_VA2_Pos            (2U)\n#define DSI_VVACCR_VA2_Msk            (0x1U << DSI_VVACCR_VA2_Pos)             /*!< 0x00000004 */\n#define DSI_VVACCR_VA2                DSI_VVACCR_VA2_Msk\n#define DSI_VVACCR_VA3_Pos            (3U)\n#define DSI_VVACCR_VA3_Msk            (0x1U << DSI_VVACCR_VA3_Pos)             /*!< 0x00000008 */\n#define DSI_VVACCR_VA3                DSI_VVACCR_VA3_Msk\n#define DSI_VVACCR_VA4_Pos            (4U)\n#define DSI_VVACCR_VA4_Msk            (0x1U << DSI_VVACCR_VA4_Pos)             /*!< 0x00000010 */\n#define DSI_VVACCR_VA4                DSI_VVACCR_VA4_Msk\n#define DSI_VVACCR_VA5_Pos            (5U)\n#define DSI_VVACCR_VA5_Msk            (0x1U << DSI_VVACCR_VA5_Pos)             /*!< 0x00000020 */\n#define DSI_VVACCR_VA5                DSI_VVACCR_VA5_Msk\n#define DSI_VVACCR_VA6_Pos            (6U)\n#define DSI_VVACCR_VA6_Msk            (0x1U << DSI_VVACCR_VA6_Pos)             /*!< 0x00000040 */\n#define DSI_VVACCR_VA6                DSI_VVACCR_VA6_Msk\n#define DSI_VVACCR_VA7_Pos            (7U)\n#define DSI_VVACCR_VA7_Msk            (0x1U << DSI_VVACCR_VA7_Pos)             /*!< 0x00000080 */\n#define DSI_VVACCR_VA7                DSI_VVACCR_VA7_Msk\n#define DSI_VVACCR_VA8_Pos            (8U)\n#define DSI_VVACCR_VA8_Msk            (0x1U << DSI_VVACCR_VA8_Pos)             /*!< 0x00000100 */\n#define DSI_VVACCR_VA8                DSI_VVACCR_VA8_Msk\n#define DSI_VVACCR_VA9_Pos            (9U)\n#define DSI_VVACCR_VA9_Msk            (0x1U << DSI_VVACCR_VA9_Pos)             /*!< 0x00000200 */\n#define DSI_VVACCR_VA9                DSI_VVACCR_VA9_Msk\n#define DSI_VVACCR_VA10_Pos           (10U)\n#define DSI_VVACCR_VA10_Msk           (0x1U << DSI_VVACCR_VA10_Pos)            /*!< 0x00000400 */\n#define DSI_VVACCR_VA10               DSI_VVACCR_VA10_Msk\n#define DSI_VVACCR_VA11_Pos           (11U)\n#define DSI_VVACCR_VA11_Msk           (0x1U << DSI_VVACCR_VA11_Pos)            /*!< 0x00000800 */\n#define DSI_VVACCR_VA11               DSI_VVACCR_VA11_Msk\n#define DSI_VVACCR_VA12_Pos           (12U)\n#define DSI_VVACCR_VA12_Msk           (0x1U << DSI_VVACCR_VA12_Pos)            /*!< 0x00001000 */\n#define DSI_VVACCR_VA12               DSI_VVACCR_VA12_Msk\n#define DSI_VVACCR_VA13_Pos           (13U)\n#define DSI_VVACCR_VA13_Msk           (0x1U << DSI_VVACCR_VA13_Pos)            /*!< 0x00002000 */\n#define DSI_VVACCR_VA13               DSI_VVACCR_VA13_Msk\n\n/*******************  Bit definition for DSI_TDCCR register  **************/\n#define DSI_TDCCR_3DM                 0x00000003U                              /*!< 3D Mode */\n#define DSI_TDCCR_3DM0                0x00000001U\n#define DSI_TDCCR_3DM1                0x00000002U\n\n#define DSI_TDCCR_3DF                 0x0000000CU                              /*!< 3D Format */\n#define DSI_TDCCR_3DF0                0x00000004U\n#define DSI_TDCCR_3DF1                0x00000008U\n\n#define DSI_TDCCR_SVS_Pos             (4U)\n#define DSI_TDCCR_SVS_Msk             (0x1U << DSI_TDCCR_SVS_Pos)              /*!< 0x00000010 */\n#define DSI_TDCCR_SVS                 DSI_TDCCR_SVS_Msk                        /*!< Second VSYNC */\n#define DSI_TDCCR_RF_Pos              (5U)\n#define DSI_TDCCR_RF_Msk              (0x1U << DSI_TDCCR_RF_Pos)               /*!< 0x00000020 */\n#define DSI_TDCCR_RF                  DSI_TDCCR_RF_Msk                         /*!< Right First */\n#define DSI_TDCCR_S3DC_Pos            (16U)\n#define DSI_TDCCR_S3DC_Msk            (0x1U << DSI_TDCCR_S3DC_Pos)             /*!< 0x00010000 */\n#define DSI_TDCCR_S3DC                DSI_TDCCR_S3DC_Msk                       /*!< Send 3D Control */\n\n/*******************  Bit definition for DSI_WCFGR register  ***************/\n#define DSI_WCFGR_DSIM_Pos            (0U)\n#define DSI_WCFGR_DSIM_Msk            (0x1U << DSI_WCFGR_DSIM_Pos)             /*!< 0x00000001 */\n#define DSI_WCFGR_DSIM                DSI_WCFGR_DSIM_Msk                       /*!< DSI Mode */\n#define DSI_WCFGR_COLMUX_Pos          (1U)\n#define DSI_WCFGR_COLMUX_Msk          (0x7U << DSI_WCFGR_COLMUX_Pos)           /*!< 0x0000000E */\n#define DSI_WCFGR_COLMUX              DSI_WCFGR_COLMUX_Msk                     /*!< Color Multiplexing */\n#define DSI_WCFGR_COLMUX0_Pos         (1U)\n#define DSI_WCFGR_COLMUX0_Msk         (0x1U << DSI_WCFGR_COLMUX0_Pos)          /*!< 0x00000002 */\n#define DSI_WCFGR_COLMUX0             DSI_WCFGR_COLMUX0_Msk\n#define DSI_WCFGR_COLMUX1_Pos         (2U)\n#define DSI_WCFGR_COLMUX1_Msk         (0x1U << DSI_WCFGR_COLMUX1_Pos)          /*!< 0x00000004 */\n#define DSI_WCFGR_COLMUX1             DSI_WCFGR_COLMUX1_Msk\n#define DSI_WCFGR_COLMUX2_Pos         (3U)\n#define DSI_WCFGR_COLMUX2_Msk         (0x1U << DSI_WCFGR_COLMUX2_Pos)          /*!< 0x00000008 */\n#define DSI_WCFGR_COLMUX2             DSI_WCFGR_COLMUX2_Msk\n\n#define DSI_WCFGR_TESRC_Pos           (4U)\n#define DSI_WCFGR_TESRC_Msk           (0x1U << DSI_WCFGR_TESRC_Pos)            /*!< 0x00000010 */\n#define DSI_WCFGR_TESRC               DSI_WCFGR_TESRC_Msk                      /*!< Tearing Effect Source */\n#define DSI_WCFGR_TEPOL_Pos           (5U)\n#define DSI_WCFGR_TEPOL_Msk           (0x1U << DSI_WCFGR_TEPOL_Pos)            /*!< 0x00000020 */\n#define DSI_WCFGR_TEPOL               DSI_WCFGR_TEPOL_Msk                      /*!< Tearing Effect Polarity */\n#define DSI_WCFGR_AR_Pos              (6U)\n#define DSI_WCFGR_AR_Msk              (0x1U << DSI_WCFGR_AR_Pos)               /*!< 0x00000040 */\n#define DSI_WCFGR_AR                  DSI_WCFGR_AR_Msk                         /*!< Automatic Refresh */\n#define DSI_WCFGR_VSPOL_Pos           (7U)\n#define DSI_WCFGR_VSPOL_Msk           (0x1U << DSI_WCFGR_VSPOL_Pos)            /*!< 0x00000080 */\n#define DSI_WCFGR_VSPOL               DSI_WCFGR_VSPOL_Msk                      /*!< VSync Polarity */\n\n/*******************  Bit definition for DSI_WCR register  *****************/\n#define DSI_WCR_COLM_Pos              (0U)\n#define DSI_WCR_COLM_Msk              (0x1U << DSI_WCR_COLM_Pos)               /*!< 0x00000001 */\n#define DSI_WCR_COLM                  DSI_WCR_COLM_Msk                         /*!< Color Mode */\n#define DSI_WCR_SHTDN_Pos             (1U)\n#define DSI_WCR_SHTDN_Msk             (0x1U << DSI_WCR_SHTDN_Pos)              /*!< 0x00000002 */\n#define DSI_WCR_SHTDN                 DSI_WCR_SHTDN_Msk                        /*!< Shutdown */\n#define DSI_WCR_LTDCEN_Pos            (2U)\n#define DSI_WCR_LTDCEN_Msk            (0x1U << DSI_WCR_LTDCEN_Pos)             /*!< 0x00000004 */\n#define DSI_WCR_LTDCEN                DSI_WCR_LTDCEN_Msk                       /*!< LTDC Enable */\n#define DSI_WCR_DSIEN_Pos             (3U)\n#define DSI_WCR_DSIEN_Msk             (0x1U << DSI_WCR_DSIEN_Pos)              /*!< 0x00000008 */\n#define DSI_WCR_DSIEN                 DSI_WCR_DSIEN_Msk                        /*!< DSI Enable */\n\n/*******************  Bit definition for DSI_WIER register  ****************/\n#define DSI_WIER_TEIE_Pos             (0U)\n#define DSI_WIER_TEIE_Msk             (0x1U << DSI_WIER_TEIE_Pos)              /*!< 0x00000001 */\n#define DSI_WIER_TEIE                 DSI_WIER_TEIE_Msk                        /*!< Tearing Effect Interrupt Enable */\n#define DSI_WIER_ERIE_Pos             (1U)\n#define DSI_WIER_ERIE_Msk             (0x1U << DSI_WIER_ERIE_Pos)              /*!< 0x00000002 */\n#define DSI_WIER_ERIE                 DSI_WIER_ERIE_Msk                        /*!< End of Refresh Interrupt Enable */\n#define DSI_WIER_PLLLIE_Pos           (9U)\n#define DSI_WIER_PLLLIE_Msk           (0x1U << DSI_WIER_PLLLIE_Pos)            /*!< 0x00000200 */\n#define DSI_WIER_PLLLIE               DSI_WIER_PLLLIE_Msk                      /*!< PLL Lock Interrupt Enable */\n#define DSI_WIER_PLLUIE_Pos           (10U)\n#define DSI_WIER_PLLUIE_Msk           (0x1U << DSI_WIER_PLLUIE_Pos)            /*!< 0x00000400 */\n#define DSI_WIER_PLLUIE               DSI_WIER_PLLUIE_Msk                      /*!< PLL Unlock Interrupt Enable */\n#define DSI_WIER_RRIE_Pos             (13U)\n#define DSI_WIER_RRIE_Msk             (0x1U << DSI_WIER_RRIE_Pos)              /*!< 0x00002000 */\n#define DSI_WIER_RRIE                 DSI_WIER_RRIE_Msk                        /*!< Regulator Ready Interrupt Enable */\n\n/*******************  Bit definition for DSI_WISR register  ****************/\n#define DSI_WISR_TEIF_Pos             (0U)\n#define DSI_WISR_TEIF_Msk             (0x1U << DSI_WISR_TEIF_Pos)              /*!< 0x00000001 */\n#define DSI_WISR_TEIF                 DSI_WISR_TEIF_Msk                        /*!< Tearing Effect Interrupt Flag */\n#define DSI_WISR_ERIF_Pos             (1U)\n#define DSI_WISR_ERIF_Msk             (0x1U << DSI_WISR_ERIF_Pos)              /*!< 0x00000002 */\n#define DSI_WISR_ERIF                 DSI_WISR_ERIF_Msk                        /*!< End of Refresh Interrupt Flag */\n#define DSI_WISR_BUSY_Pos             (2U)\n#define DSI_WISR_BUSY_Msk             (0x1U << DSI_WISR_BUSY_Pos)              /*!< 0x00000004 */\n#define DSI_WISR_BUSY                 DSI_WISR_BUSY_Msk                        /*!< Busy Flag */\n#define DSI_WISR_PLLLS_Pos            (8U)\n#define DSI_WISR_PLLLS_Msk            (0x1U << DSI_WISR_PLLLS_Pos)             /*!< 0x00000100 */\n#define DSI_WISR_PLLLS                DSI_WISR_PLLLS_Msk                       /*!< PLL Lock Status */\n#define DSI_WISR_PLLLIF_Pos           (9U)\n#define DSI_WISR_PLLLIF_Msk           (0x1U << DSI_WISR_PLLLIF_Pos)            /*!< 0x00000200 */\n#define DSI_WISR_PLLLIF               DSI_WISR_PLLLIF_Msk                      /*!< PLL Lock Interrupt Flag */\n#define DSI_WISR_PLLUIF_Pos           (10U)\n#define DSI_WISR_PLLUIF_Msk           (0x1U << DSI_WISR_PLLUIF_Pos)            /*!< 0x00000400 */\n#define DSI_WISR_PLLUIF               DSI_WISR_PLLUIF_Msk                      /*!< PLL Unlock Interrupt Flag */\n#define DSI_WISR_RRS_Pos              (12U)\n#define DSI_WISR_RRS_Msk              (0x1U << DSI_WISR_RRS_Pos)               /*!< 0x00001000 */\n#define DSI_WISR_RRS                  DSI_WISR_RRS_Msk                         /*!< Regulator Ready Flag */\n#define DSI_WISR_RRIF_Pos             (13U)\n#define DSI_WISR_RRIF_Msk             (0x1U << DSI_WISR_RRIF_Pos)              /*!< 0x00002000 */\n#define DSI_WISR_RRIF                 DSI_WISR_RRIF_Msk                        /*!< Regulator Ready Interrupt Flag */\n\n/*******************  Bit definition for DSI_WIFCR register  ***************/\n#define DSI_WIFCR_CTEIF_Pos           (0U)\n#define DSI_WIFCR_CTEIF_Msk           (0x1U << DSI_WIFCR_CTEIF_Pos)            /*!< 0x00000001 */\n#define DSI_WIFCR_CTEIF               DSI_WIFCR_CTEIF_Msk                      /*!< Clear Tearing Effect Interrupt Flag */\n#define DSI_WIFCR_CERIF_Pos           (1U)\n#define DSI_WIFCR_CERIF_Msk           (0x1U << DSI_WIFCR_CERIF_Pos)            /*!< 0x00000002 */\n#define DSI_WIFCR_CERIF               DSI_WIFCR_CERIF_Msk                      /*!< Clear End of Refresh Interrupt Flag */\n#define DSI_WIFCR_CPLLLIF_Pos         (9U)\n#define DSI_WIFCR_CPLLLIF_Msk         (0x1U << DSI_WIFCR_CPLLLIF_Pos)          /*!< 0x00000200 */\n#define DSI_WIFCR_CPLLLIF             DSI_WIFCR_CPLLLIF_Msk                    /*!< Clear PLL Lock Interrupt Flag */\n#define DSI_WIFCR_CPLLUIF_Pos         (10U)\n#define DSI_WIFCR_CPLLUIF_Msk         (0x1U << DSI_WIFCR_CPLLUIF_Pos)          /*!< 0x00000400 */\n#define DSI_WIFCR_CPLLUIF             DSI_WIFCR_CPLLUIF_Msk                    /*!< Clear PLL Unlock Interrupt Flag */\n#define DSI_WIFCR_CRRIF_Pos           (13U)\n#define DSI_WIFCR_CRRIF_Msk           (0x1U << DSI_WIFCR_CRRIF_Pos)            /*!< 0x00002000 */\n#define DSI_WIFCR_CRRIF               DSI_WIFCR_CRRIF_Msk                      /*!< Clear Regulator Ready Interrupt Flag */\n\n/*******************  Bit definition for DSI_WPCR0 register  ***************/\n#define DSI_WPCR0_UIX4_Pos            (0U)\n#define DSI_WPCR0_UIX4_Msk            (0x3FU << DSI_WPCR0_UIX4_Pos)            /*!< 0x0000003F */\n#define DSI_WPCR0_UIX4                DSI_WPCR0_UIX4_Msk                       /*!< Unit Interval multiplied by 4 */\n#define DSI_WPCR0_UIX4_0              (0x01U << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000001 */\n#define DSI_WPCR0_UIX4_1              (0x02U << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000002 */\n#define DSI_WPCR0_UIX4_2              (0x04U << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000004 */\n#define DSI_WPCR0_UIX4_3              (0x08U << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000008 */\n#define DSI_WPCR0_UIX4_4              (0x10U << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000010 */\n#define DSI_WPCR0_UIX4_5              (0x20U << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000020 */\n\n#define DSI_WPCR0_SWCL_Pos            (6U)\n#define DSI_WPCR0_SWCL_Msk            (0x1U << DSI_WPCR0_SWCL_Pos)             /*!< 0x00000040 */\n#define DSI_WPCR0_SWCL                DSI_WPCR0_SWCL_Msk                       /*!< Swap pins on clock lane */\n#define DSI_WPCR0_SWDL0_Pos           (7U)\n#define DSI_WPCR0_SWDL0_Msk           (0x1U << DSI_WPCR0_SWDL0_Pos)            /*!< 0x00000080 */\n#define DSI_WPCR0_SWDL0               DSI_WPCR0_SWDL0_Msk                      /*!< Swap pins on data lane 1 */\n#define DSI_WPCR0_SWDL1_Pos           (8U)\n#define DSI_WPCR0_SWDL1_Msk           (0x1U << DSI_WPCR0_SWDL1_Pos)            /*!< 0x00000100 */\n#define DSI_WPCR0_SWDL1               DSI_WPCR0_SWDL1_Msk                      /*!< Swap pins on data lane 2 */\n#define DSI_WPCR0_HSICL_Pos           (9U)\n#define DSI_WPCR0_HSICL_Msk           (0x1U << DSI_WPCR0_HSICL_Pos)            /*!< 0x00000200 */\n#define DSI_WPCR0_HSICL               DSI_WPCR0_HSICL_Msk                      /*!< Invert the high-speed data signal on clock lane */\n#define DSI_WPCR0_HSIDL0_Pos          (10U)\n#define DSI_WPCR0_HSIDL0_Msk          (0x1U << DSI_WPCR0_HSIDL0_Pos)           /*!< 0x00000400 */\n#define DSI_WPCR0_HSIDL0              DSI_WPCR0_HSIDL0_Msk                     /*!< Invert the high-speed data signal on lane 1 */\n#define DSI_WPCR0_HSIDL1_Pos          (11U)\n#define DSI_WPCR0_HSIDL1_Msk          (0x1U << DSI_WPCR0_HSIDL1_Pos)           /*!< 0x00000800 */\n#define DSI_WPCR0_HSIDL1              DSI_WPCR0_HSIDL1_Msk                     /*!< Invert the high-speed data signal on lane 2 */\n#define DSI_WPCR0_FTXSMCL_Pos         (12U)\n#define DSI_WPCR0_FTXSMCL_Msk         (0x1U << DSI_WPCR0_FTXSMCL_Pos)          /*!< 0x00001000 */\n#define DSI_WPCR0_FTXSMCL             DSI_WPCR0_FTXSMCL_Msk                    /*!< Force clock lane in TX stop mode */\n#define DSI_WPCR0_FTXSMDL_Pos         (13U)\n#define DSI_WPCR0_FTXSMDL_Msk         (0x1U << DSI_WPCR0_FTXSMDL_Pos)          /*!< 0x00002000 */\n#define DSI_WPCR0_FTXSMDL             DSI_WPCR0_FTXSMDL_Msk                    /*!< Force data lanes in TX stop mode */\n#define DSI_WPCR0_CDOFFDL_Pos         (14U)\n#define DSI_WPCR0_CDOFFDL_Msk         (0x1U << DSI_WPCR0_CDOFFDL_Pos)          /*!< 0x00004000 */\n#define DSI_WPCR0_CDOFFDL             DSI_WPCR0_CDOFFDL_Msk                    /*!< Contention detection OFF */\n#define DSI_WPCR0_TDDL_Pos            (16U)\n#define DSI_WPCR0_TDDL_Msk            (0x1U << DSI_WPCR0_TDDL_Pos)             /*!< 0x00010000 */\n#define DSI_WPCR0_TDDL                DSI_WPCR0_TDDL_Msk                       /*!< Turn Disable Data Lanes */\n#define DSI_WPCR0_PDEN_Pos            (18U)\n#define DSI_WPCR0_PDEN_Msk            (0x1U << DSI_WPCR0_PDEN_Pos)             /*!< 0x00040000 */\n#define DSI_WPCR0_PDEN                DSI_WPCR0_PDEN_Msk                       /*!< Pull-Down Enable */\n#define DSI_WPCR0_TCLKPREPEN_Pos      (19U)\n#define DSI_WPCR0_TCLKPREPEN_Msk      (0x1U << DSI_WPCR0_TCLKPREPEN_Pos)       /*!< 0x00080000 */\n#define DSI_WPCR0_TCLKPREPEN          DSI_WPCR0_TCLKPREPEN_Msk                 /*!< Timer for t-CLKPREP Enable */\n#define DSI_WPCR0_TCLKZEROEN_Pos      (20U)\n#define DSI_WPCR0_TCLKZEROEN_Msk      (0x1U << DSI_WPCR0_TCLKZEROEN_Pos)       /*!< 0x00100000 */\n#define DSI_WPCR0_TCLKZEROEN          DSI_WPCR0_TCLKZEROEN_Msk                 /*!< Timer for t-CLKZERO Enable */\n#define DSI_WPCR0_THSPREPEN_Pos       (21U)\n#define DSI_WPCR0_THSPREPEN_Msk       (0x1U << DSI_WPCR0_THSPREPEN_Pos)        /*!< 0x00200000 */\n#define DSI_WPCR0_THSPREPEN           DSI_WPCR0_THSPREPEN_Msk                  /*!< Timer for t-HSPREP Enable */\n#define DSI_WPCR0_THSTRAILEN_Pos      (22U)\n#define DSI_WPCR0_THSTRAILEN_Msk      (0x1U << DSI_WPCR0_THSTRAILEN_Pos)       /*!< 0x00400000 */\n#define DSI_WPCR0_THSTRAILEN          DSI_WPCR0_THSTRAILEN_Msk                 /*!< Timer for t-HSTRAIL Enable */\n#define DSI_WPCR0_THSZEROEN_Pos       (23U)\n#define DSI_WPCR0_THSZEROEN_Msk       (0x1U << DSI_WPCR0_THSZEROEN_Pos)        /*!< 0x00800000 */\n#define DSI_WPCR0_THSZEROEN           DSI_WPCR0_THSZEROEN_Msk                  /*!< Timer for t-HSZERO Enable */\n#define DSI_WPCR0_TLPXDEN_Pos         (24U)\n#define DSI_WPCR0_TLPXDEN_Msk         (0x1U << DSI_WPCR0_TLPXDEN_Pos)          /*!< 0x01000000 */\n#define DSI_WPCR0_TLPXDEN             DSI_WPCR0_TLPXDEN_Msk                    /*!< Timer for t-LPXD Enable */\n#define DSI_WPCR0_THSEXITEN_Pos       (25U)\n#define DSI_WPCR0_THSEXITEN_Msk       (0x1U << DSI_WPCR0_THSEXITEN_Pos)        /*!< 0x02000000 */\n#define DSI_WPCR0_THSEXITEN           DSI_WPCR0_THSEXITEN_Msk                  /*!< Timer for t-HSEXIT Enable */\n#define DSI_WPCR0_TLPXCEN_Pos         (26U)\n#define DSI_WPCR0_TLPXCEN_Msk         (0x1U << DSI_WPCR0_TLPXCEN_Pos)          /*!< 0x04000000 */\n#define DSI_WPCR0_TLPXCEN             DSI_WPCR0_TLPXCEN_Msk                    /*!< Timer for t-LPXC Enable */\n#define DSI_WPCR0_TCLKPOSTEN_Pos      (27U)\n#define DSI_WPCR0_TCLKPOSTEN_Msk      (0x1U << DSI_WPCR0_TCLKPOSTEN_Pos)       /*!< 0x08000000 */\n#define DSI_WPCR0_TCLKPOSTEN          DSI_WPCR0_TCLKPOSTEN_Msk                 /*!< Timer for t-CLKPOST Enable */\n\n/*******************  Bit definition for DSI_WPCR1 register  ***************/\n#define DSI_WPCR1_HSTXDCL_Pos         (0U)\n#define DSI_WPCR1_HSTXDCL_Msk         (0x3U << DSI_WPCR1_HSTXDCL_Pos)          /*!< 0x00000003 */\n#define DSI_WPCR1_HSTXDCL             DSI_WPCR1_HSTXDCL_Msk                    /*!< High-Speed Transmission Delay on Clock Lane */\n#define DSI_WPCR1_HSTXDCL0_Pos        (0U)\n#define DSI_WPCR1_HSTXDCL0_Msk        (0x1U << DSI_WPCR1_HSTXDCL0_Pos)         /*!< 0x00000001 */\n#define DSI_WPCR1_HSTXDCL0            DSI_WPCR1_HSTXDCL0_Msk\n#define DSI_WPCR1_HSTXDCL1_Pos        (1U)\n#define DSI_WPCR1_HSTXDCL1_Msk        (0x1U << DSI_WPCR1_HSTXDCL1_Pos)         /*!< 0x00000002 */\n#define DSI_WPCR1_HSTXDCL1            DSI_WPCR1_HSTXDCL1_Msk\n\n#define DSI_WPCR1_HSTXDDL_Pos         (2U)\n#define DSI_WPCR1_HSTXDDL_Msk         (0x3U << DSI_WPCR1_HSTXDDL_Pos)          /*!< 0x0000000C */\n#define DSI_WPCR1_HSTXDDL             DSI_WPCR1_HSTXDDL_Msk                    /*!< High-Speed Transmission Delay on Data Lane */\n#define DSI_WPCR1_HSTXDDL0_Pos        (2U)\n#define DSI_WPCR1_HSTXDDL0_Msk        (0x1U << DSI_WPCR1_HSTXDDL0_Pos)         /*!< 0x00000004 */\n#define DSI_WPCR1_HSTXDDL0            DSI_WPCR1_HSTXDDL0_Msk\n#define DSI_WPCR1_HSTXDDL1_Pos        (3U)\n#define DSI_WPCR1_HSTXDDL1_Msk        (0x1U << DSI_WPCR1_HSTXDDL1_Pos)         /*!< 0x00000008 */\n#define DSI_WPCR1_HSTXDDL1            DSI_WPCR1_HSTXDDL1_Msk\n\n#define DSI_WPCR1_LPSRCCL_Pos         (6U)\n#define DSI_WPCR1_LPSRCCL_Msk         (0x3U << DSI_WPCR1_LPSRCCL_Pos)          /*!< 0x000000C0 */\n#define DSI_WPCR1_LPSRCCL             DSI_WPCR1_LPSRCCL_Msk                    /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */\n#define DSI_WPCR1_LPSRCCL0_Pos        (6U)\n#define DSI_WPCR1_LPSRCCL0_Msk        (0x1U << DSI_WPCR1_LPSRCCL0_Pos)         /*!< 0x00000040 */\n#define DSI_WPCR1_LPSRCCL0            DSI_WPCR1_LPSRCCL0_Msk\n#define DSI_WPCR1_LPSRCCL1_Pos        (7U)\n#define DSI_WPCR1_LPSRCCL1_Msk        (0x1U << DSI_WPCR1_LPSRCCL1_Pos)         /*!< 0x00000080 */\n#define DSI_WPCR1_LPSRCCL1            DSI_WPCR1_LPSRCCL1_Msk\n\n#define DSI_WPCR1_LPSRCDL_Pos         (8U)\n#define DSI_WPCR1_LPSRCDL_Msk         (0x3U << DSI_WPCR1_LPSRCDL_Pos)          /*!< 0x00000300 */\n#define DSI_WPCR1_LPSRCDL             DSI_WPCR1_LPSRCDL_Msk                    /*!< Low-Power transmission Slew Rate Compensation on Data Lane */\n#define DSI_WPCR1_LPSRCDL0_Pos        (8U)\n#define DSI_WPCR1_LPSRCDL0_Msk        (0x1U << DSI_WPCR1_LPSRCDL0_Pos)         /*!< 0x00000100 */\n#define DSI_WPCR1_LPSRCDL0            DSI_WPCR1_LPSRCDL0_Msk\n#define DSI_WPCR1_LPSRCDL1_Pos        (9U)\n#define DSI_WPCR1_LPSRCDL1_Msk        (0x1U << DSI_WPCR1_LPSRCDL1_Pos)         /*!< 0x00000200 */\n#define DSI_WPCR1_LPSRCDL1            DSI_WPCR1_LPSRCDL1_Msk\n\n#define DSI_WPCR1_SDDC_Pos            (12U)\n#define DSI_WPCR1_SDDC_Msk            (0x1U << DSI_WPCR1_SDDC_Pos)             /*!< 0x00001000 */\n#define DSI_WPCR1_SDDC                DSI_WPCR1_SDDC_Msk                       /*!< SDD Control */\n\n#define DSI_WPCR1_LPRXVCDL_Pos        (14U)\n#define DSI_WPCR1_LPRXVCDL_Msk        (0x3U << DSI_WPCR1_LPRXVCDL_Pos)         /*!< 0x0000C000 */\n#define DSI_WPCR1_LPRXVCDL            DSI_WPCR1_LPRXVCDL_Msk                   /*!< Low-Power Reception V-IL Compensation on Data Lanes */\n#define DSI_WPCR1_LPRXVCDL0_Pos       (14U)\n#define DSI_WPCR1_LPRXVCDL0_Msk       (0x1U << DSI_WPCR1_LPRXVCDL0_Pos)        /*!< 0x00004000 */\n#define DSI_WPCR1_LPRXVCDL0           DSI_WPCR1_LPRXVCDL0_Msk\n#define DSI_WPCR1_LPRXVCDL1_Pos       (15U)\n#define DSI_WPCR1_LPRXVCDL1_Msk       (0x1U << DSI_WPCR1_LPRXVCDL1_Pos)        /*!< 0x00008000 */\n#define DSI_WPCR1_LPRXVCDL1           DSI_WPCR1_LPRXVCDL1_Msk\n\n#define DSI_WPCR1_HSTXSRCCL_Pos       (16U)\n#define DSI_WPCR1_HSTXSRCCL_Msk       (0x3U << DSI_WPCR1_HSTXSRCCL_Pos)        /*!< 0x00030000 */\n#define DSI_WPCR1_HSTXSRCCL           DSI_WPCR1_HSTXSRCCL_Msk                  /*!< High-Speed Transmission Delay on Clock Lane */\n#define DSI_WPCR1_HSTXSRCCL0_Pos      (16U)\n#define DSI_WPCR1_HSTXSRCCL0_Msk      (0x1U << DSI_WPCR1_HSTXSRCCL0_Pos)       /*!< 0x00010000 */\n#define DSI_WPCR1_HSTXSRCCL0          DSI_WPCR1_HSTXSRCCL0_Msk\n#define DSI_WPCR1_HSTXSRCCL1_Pos      (17U)\n#define DSI_WPCR1_HSTXSRCCL1_Msk      (0x1U << DSI_WPCR1_HSTXSRCCL1_Pos)       /*!< 0x00020000 */\n#define DSI_WPCR1_HSTXSRCCL1          DSI_WPCR1_HSTXSRCCL1_Msk\n\n#define DSI_WPCR1_HSTXSRCDL_Pos       (18U)\n#define DSI_WPCR1_HSTXSRCDL_Msk       (0x3U << DSI_WPCR1_HSTXSRCDL_Pos)        /*!< 0x000C0000 */\n#define DSI_WPCR1_HSTXSRCDL           DSI_WPCR1_HSTXSRCDL_Msk                  /*!< High-Speed Transmission Delay on Data Lane */\n#define DSI_WPCR1_HSTXSRCDL0_Pos      (18U)\n#define DSI_WPCR1_HSTXSRCDL0_Msk      (0x1U << DSI_WPCR1_HSTXSRCDL0_Pos)       /*!< 0x00040000 */\n#define DSI_WPCR1_HSTXSRCDL0          DSI_WPCR1_HSTXSRCDL0_Msk\n#define DSI_WPCR1_HSTXSRCDL1_Pos      (19U)\n#define DSI_WPCR1_HSTXSRCDL1_Msk      (0x1U << DSI_WPCR1_HSTXSRCDL1_Pos)       /*!< 0x00080000 */\n#define DSI_WPCR1_HSTXSRCDL1          DSI_WPCR1_HSTXSRCDL1_Msk\n\n#define DSI_WPCR1_FLPRXLPM_Pos        (22U)\n#define DSI_WPCR1_FLPRXLPM_Msk        (0x1U << DSI_WPCR1_FLPRXLPM_Pos)         /*!< 0x00400000 */\n#define DSI_WPCR1_FLPRXLPM            DSI_WPCR1_FLPRXLPM_Msk                   /*!< Forces LP Receiver in Low-Power Mode */\n\n#define DSI_WPCR1_LPRXFT_Pos          (25U)\n#define DSI_WPCR1_LPRXFT_Msk          (0x3U << DSI_WPCR1_LPRXFT_Pos)           /*!< 0x06000000 */\n#define DSI_WPCR1_LPRXFT              DSI_WPCR1_LPRXFT_Msk                     /*!< Low-Power RX low-pass Filtering Tuning */\n#define DSI_WPCR1_LPRXFT0_Pos         (25U)\n#define DSI_WPCR1_LPRXFT0_Msk         (0x1U << DSI_WPCR1_LPRXFT0_Pos)          /*!< 0x02000000 */\n#define DSI_WPCR1_LPRXFT0             DSI_WPCR1_LPRXFT0_Msk\n#define DSI_WPCR1_LPRXFT1_Pos         (26U)\n#define DSI_WPCR1_LPRXFT1_Msk         (0x1U << DSI_WPCR1_LPRXFT1_Pos)          /*!< 0x04000000 */\n#define DSI_WPCR1_LPRXFT1             DSI_WPCR1_LPRXFT1_Msk\n\n/*******************  Bit definition for DSI_WPCR2 register  ***************/\n#define DSI_WPCR2_TCLKPREP_Pos        (0U)\n#define DSI_WPCR2_TCLKPREP_Msk        (0xFFU << DSI_WPCR2_TCLKPREP_Pos)        /*!< 0x000000FF */\n#define DSI_WPCR2_TCLKPREP            DSI_WPCR2_TCLKPREP_Msk                   /*!< t-CLKPREP */\n#define DSI_WPCR2_TCLKPREP0_Pos       (0U)\n#define DSI_WPCR2_TCLKPREP0_Msk       (0x1U << DSI_WPCR2_TCLKPREP0_Pos)        /*!< 0x00000001 */\n#define DSI_WPCR2_TCLKPREP0           DSI_WPCR2_TCLKPREP0_Msk\n#define DSI_WPCR2_TCLKPREP1_Pos       (1U)\n#define DSI_WPCR2_TCLKPREP1_Msk       (0x1U << DSI_WPCR2_TCLKPREP1_Pos)        /*!< 0x00000002 */\n#define DSI_WPCR2_TCLKPREP1           DSI_WPCR2_TCLKPREP1_Msk\n#define DSI_WPCR2_TCLKPREP2_Pos       (2U)\n#define DSI_WPCR2_TCLKPREP2_Msk       (0x1U << DSI_WPCR2_TCLKPREP2_Pos)        /*!< 0x00000004 */\n#define DSI_WPCR2_TCLKPREP2           DSI_WPCR2_TCLKPREP2_Msk\n#define DSI_WPCR2_TCLKPREP3_Pos       (3U)\n#define DSI_WPCR2_TCLKPREP3_Msk       (0x1U << DSI_WPCR2_TCLKPREP3_Pos)        /*!< 0x00000008 */\n#define DSI_WPCR2_TCLKPREP3           DSI_WPCR2_TCLKPREP3_Msk\n#define DSI_WPCR2_TCLKPREP4_Pos       (4U)\n#define DSI_WPCR2_TCLKPREP4_Msk       (0x1U << DSI_WPCR2_TCLKPREP4_Pos)        /*!< 0x00000010 */\n#define DSI_WPCR2_TCLKPREP4           DSI_WPCR2_TCLKPREP4_Msk\n#define DSI_WPCR2_TCLKPREP5_Pos       (5U)\n#define DSI_WPCR2_TCLKPREP5_Msk       (0x1U << DSI_WPCR2_TCLKPREP5_Pos)        /*!< 0x00000020 */\n#define DSI_WPCR2_TCLKPREP5           DSI_WPCR2_TCLKPREP5_Msk\n#define DSI_WPCR2_TCLKPREP6_Pos       (6U)\n#define DSI_WPCR2_TCLKPREP6_Msk       (0x1U << DSI_WPCR2_TCLKPREP6_Pos)        /*!< 0x00000040 */\n#define DSI_WPCR2_TCLKPREP6           DSI_WPCR2_TCLKPREP6_Msk\n#define DSI_WPCR2_TCLKPREP7_Pos       (7U)\n#define DSI_WPCR2_TCLKPREP7_Msk       (0x1U << DSI_WPCR2_TCLKPREP7_Pos)        /*!< 0x00000080 */\n#define DSI_WPCR2_TCLKPREP7           DSI_WPCR2_TCLKPREP7_Msk\n\n#define DSI_WPCR2_TCLKZERO_Pos        (8U)\n#define DSI_WPCR2_TCLKZERO_Msk        (0xFFU << DSI_WPCR2_TCLKZERO_Pos)        /*!< 0x0000FF00 */\n#define DSI_WPCR2_TCLKZERO            DSI_WPCR2_TCLKZERO_Msk                   /*!< t-CLKZERO */\n#define DSI_WPCR2_TCLKZERO0_Pos       (8U)\n#define DSI_WPCR2_TCLKZERO0_Msk       (0x1U << DSI_WPCR2_TCLKZERO0_Pos)        /*!< 0x00000100 */\n#define DSI_WPCR2_TCLKZERO0           DSI_WPCR2_TCLKZERO0_Msk\n#define DSI_WPCR2_TCLKZERO1_Pos       (9U)\n#define DSI_WPCR2_TCLKZERO1_Msk       (0x1U << DSI_WPCR2_TCLKZERO1_Pos)        /*!< 0x00000200 */\n#define DSI_WPCR2_TCLKZERO1           DSI_WPCR2_TCLKZERO1_Msk\n#define DSI_WPCR2_TCLKZERO2_Pos       (10U)\n#define DSI_WPCR2_TCLKZERO2_Msk       (0x1U << DSI_WPCR2_TCLKZERO2_Pos)        /*!< 0x00000400 */\n#define DSI_WPCR2_TCLKZERO2           DSI_WPCR2_TCLKZERO2_Msk\n#define DSI_WPCR2_TCLKZERO3_Pos       (11U)\n#define DSI_WPCR2_TCLKZERO3_Msk       (0x1U << DSI_WPCR2_TCLKZERO3_Pos)        /*!< 0x00000800 */\n#define DSI_WPCR2_TCLKZERO3           DSI_WPCR2_TCLKZERO3_Msk\n#define DSI_WPCR2_TCLKZERO4_Pos       (12U)\n#define DSI_WPCR2_TCLKZERO4_Msk       (0x1U << DSI_WPCR2_TCLKZERO4_Pos)        /*!< 0x00001000 */\n#define DSI_WPCR2_TCLKZERO4           DSI_WPCR2_TCLKZERO4_Msk\n#define DSI_WPCR2_TCLKZERO5_Pos       (13U)\n#define DSI_WPCR2_TCLKZERO5_Msk       (0x1U << DSI_WPCR2_TCLKZERO5_Pos)        /*!< 0x00002000 */\n#define DSI_WPCR2_TCLKZERO5           DSI_WPCR2_TCLKZERO5_Msk\n#define DSI_WPCR2_TCLKZERO6_Pos       (14U)\n#define DSI_WPCR2_TCLKZERO6_Msk       (0x1U << DSI_WPCR2_TCLKZERO6_Pos)        /*!< 0x00004000 */\n#define DSI_WPCR2_TCLKZERO6           DSI_WPCR2_TCLKZERO6_Msk\n#define DSI_WPCR2_TCLKZERO7_Pos       (15U)\n#define DSI_WPCR2_TCLKZERO7_Msk       (0x1U << DSI_WPCR2_TCLKZERO7_Pos)        /*!< 0x00008000 */\n#define DSI_WPCR2_TCLKZERO7           DSI_WPCR2_TCLKZERO7_Msk\n\n#define DSI_WPCR2_THSPREP_Pos         (16U)\n#define DSI_WPCR2_THSPREP_Msk         (0xFFU << DSI_WPCR2_THSPREP_Pos)         /*!< 0x00FF0000 */\n#define DSI_WPCR2_THSPREP             DSI_WPCR2_THSPREP_Msk                    /*!< t-HSPREP */\n#define DSI_WPCR2_THSPREP0_Pos        (16U)\n#define DSI_WPCR2_THSPREP0_Msk        (0x1U << DSI_WPCR2_THSPREP0_Pos)         /*!< 0x00010000 */\n#define DSI_WPCR2_THSPREP0            DSI_WPCR2_THSPREP0_Msk\n#define DSI_WPCR2_THSPREP1_Pos        (17U)\n#define DSI_WPCR2_THSPREP1_Msk        (0x1U << DSI_WPCR2_THSPREP1_Pos)         /*!< 0x00020000 */\n#define DSI_WPCR2_THSPREP1            DSI_WPCR2_THSPREP1_Msk\n#define DSI_WPCR2_THSPREP2_Pos        (18U)\n#define DSI_WPCR2_THSPREP2_Msk        (0x1U << DSI_WPCR2_THSPREP2_Pos)         /*!< 0x00040000 */\n#define DSI_WPCR2_THSPREP2            DSI_WPCR2_THSPREP2_Msk\n#define DSI_WPCR2_THSPREP3_Pos        (19U)\n#define DSI_WPCR2_THSPREP3_Msk        (0x1U << DSI_WPCR2_THSPREP3_Pos)         /*!< 0x00080000 */\n#define DSI_WPCR2_THSPREP3            DSI_WPCR2_THSPREP3_Msk\n#define DSI_WPCR2_THSPREP4_Pos        (20U)\n#define DSI_WPCR2_THSPREP4_Msk        (0x1U << DSI_WPCR2_THSPREP4_Pos)         /*!< 0x00100000 */\n#define DSI_WPCR2_THSPREP4            DSI_WPCR2_THSPREP4_Msk\n#define DSI_WPCR2_THSPREP5_Pos        (21U)\n#define DSI_WPCR2_THSPREP5_Msk        (0x1U << DSI_WPCR2_THSPREP5_Pos)         /*!< 0x00200000 */\n#define DSI_WPCR2_THSPREP5            DSI_WPCR2_THSPREP5_Msk\n#define DSI_WPCR2_THSPREP6_Pos        (22U)\n#define DSI_WPCR2_THSPREP6_Msk        (0x1U << DSI_WPCR2_THSPREP6_Pos)         /*!< 0x00400000 */\n#define DSI_WPCR2_THSPREP6            DSI_WPCR2_THSPREP6_Msk\n#define DSI_WPCR2_THSPREP7_Pos        (23U)\n#define DSI_WPCR2_THSPREP7_Msk        (0x1U << DSI_WPCR2_THSPREP7_Pos)         /*!< 0x00800000 */\n#define DSI_WPCR2_THSPREP7            DSI_WPCR2_THSPREP7_Msk\n\n#define DSI_WPCR2_THSTRAIL_Pos        (24U)\n#define DSI_WPCR2_THSTRAIL_Msk        (0xFFU << DSI_WPCR2_THSTRAIL_Pos)        /*!< 0xFF000000 */\n#define DSI_WPCR2_THSTRAIL            DSI_WPCR2_THSTRAIL_Msk                   /*!< t-HSTRAIL */\n#define DSI_WPCR2_THSTRAIL0_Pos       (24U)\n#define DSI_WPCR2_THSTRAIL0_Msk       (0x1U << DSI_WPCR2_THSTRAIL0_Pos)        /*!< 0x01000000 */\n#define DSI_WPCR2_THSTRAIL0           DSI_WPCR2_THSTRAIL0_Msk\n#define DSI_WPCR2_THSTRAIL1_Pos       (25U)\n#define DSI_WPCR2_THSTRAIL1_Msk       (0x1U << DSI_WPCR2_THSTRAIL1_Pos)        /*!< 0x02000000 */\n#define DSI_WPCR2_THSTRAIL1           DSI_WPCR2_THSTRAIL1_Msk\n#define DSI_WPCR2_THSTRAIL2_Pos       (26U)\n#define DSI_WPCR2_THSTRAIL2_Msk       (0x1U << DSI_WPCR2_THSTRAIL2_Pos)        /*!< 0x04000000 */\n#define DSI_WPCR2_THSTRAIL2           DSI_WPCR2_THSTRAIL2_Msk\n#define DSI_WPCR2_THSTRAIL3_Pos       (27U)\n#define DSI_WPCR2_THSTRAIL3_Msk       (0x1U << DSI_WPCR2_THSTRAIL3_Pos)        /*!< 0x08000000 */\n#define DSI_WPCR2_THSTRAIL3           DSI_WPCR2_THSTRAIL3_Msk\n#define DSI_WPCR2_THSTRAIL4_Pos       (28U)\n#define DSI_WPCR2_THSTRAIL4_Msk       (0x1U << DSI_WPCR2_THSTRAIL4_Pos)        /*!< 0x10000000 */\n#define DSI_WPCR2_THSTRAIL4           DSI_WPCR2_THSTRAIL4_Msk\n#define DSI_WPCR2_THSTRAIL5_Pos       (29U)\n#define DSI_WPCR2_THSTRAIL5_Msk       (0x1U << DSI_WPCR2_THSTRAIL5_Pos)        /*!< 0x20000000 */\n#define DSI_WPCR2_THSTRAIL5           DSI_WPCR2_THSTRAIL5_Msk\n#define DSI_WPCR2_THSTRAIL6_Pos       (30U)\n#define DSI_WPCR2_THSTRAIL6_Msk       (0x1U << DSI_WPCR2_THSTRAIL6_Pos)        /*!< 0x40000000 */\n#define DSI_WPCR2_THSTRAIL6           DSI_WPCR2_THSTRAIL6_Msk\n#define DSI_WPCR2_THSTRAIL7_Pos       (31U)\n#define DSI_WPCR2_THSTRAIL7_Msk       (0x1U << DSI_WPCR2_THSTRAIL7_Pos)        /*!< 0x80000000 */\n#define DSI_WPCR2_THSTRAIL7           DSI_WPCR2_THSTRAIL7_Msk\n\n/*******************  Bit definition for DSI_WPCR3 register  ***************/\n#define DSI_WPCR3_THSZERO_Pos         (0U)\n#define DSI_WPCR3_THSZERO_Msk         (0xFFU << DSI_WPCR3_THSZERO_Pos)         /*!< 0x000000FF */\n#define DSI_WPCR3_THSZERO             DSI_WPCR3_THSZERO_Msk                    /*!< t-HSZERO */\n#define DSI_WPCR3_THSZERO0_Pos        (0U)\n#define DSI_WPCR3_THSZERO0_Msk        (0x1U << DSI_WPCR3_THSZERO0_Pos)         /*!< 0x00000001 */\n#define DSI_WPCR3_THSZERO0            DSI_WPCR3_THSZERO0_Msk\n#define DSI_WPCR3_THSZERO1_Pos        (1U)\n#define DSI_WPCR3_THSZERO1_Msk        (0x1U << DSI_WPCR3_THSZERO1_Pos)         /*!< 0x00000002 */\n#define DSI_WPCR3_THSZERO1            DSI_WPCR3_THSZERO1_Msk\n#define DSI_WPCR3_THSZERO2_Pos        (2U)\n#define DSI_WPCR3_THSZERO2_Msk        (0x1U << DSI_WPCR3_THSZERO2_Pos)         /*!< 0x00000004 */\n#define DSI_WPCR3_THSZERO2            DSI_WPCR3_THSZERO2_Msk\n#define DSI_WPCR3_THSZERO3_Pos        (3U)\n#define DSI_WPCR3_THSZERO3_Msk        (0x1U << DSI_WPCR3_THSZERO3_Pos)         /*!< 0x00000008 */\n#define DSI_WPCR3_THSZERO3            DSI_WPCR3_THSZERO3_Msk\n#define DSI_WPCR3_THSZERO4_Pos        (4U)\n#define DSI_WPCR3_THSZERO4_Msk        (0x1U << DSI_WPCR3_THSZERO4_Pos)         /*!< 0x00000010 */\n#define DSI_WPCR3_THSZERO4            DSI_WPCR3_THSZERO4_Msk\n#define DSI_WPCR3_THSZERO5_Pos        (5U)\n#define DSI_WPCR3_THSZERO5_Msk        (0x1U << DSI_WPCR3_THSZERO5_Pos)         /*!< 0x00000020 */\n#define DSI_WPCR3_THSZERO5            DSI_WPCR3_THSZERO5_Msk\n#define DSI_WPCR3_THSZERO6_Pos        (6U)\n#define DSI_WPCR3_THSZERO6_Msk        (0x1U << DSI_WPCR3_THSZERO6_Pos)         /*!< 0x00000040 */\n#define DSI_WPCR3_THSZERO6            DSI_WPCR3_THSZERO6_Msk\n#define DSI_WPCR3_THSZERO7_Pos        (7U)\n#define DSI_WPCR3_THSZERO7_Msk        (0x1U << DSI_WPCR3_THSZERO7_Pos)         /*!< 0x00000080 */\n#define DSI_WPCR3_THSZERO7            DSI_WPCR3_THSZERO7_Msk\n\n#define DSI_WPCR3_TLPXD_Pos           (8U)\n#define DSI_WPCR3_TLPXD_Msk           (0xFFU << DSI_WPCR3_TLPXD_Pos)           /*!< 0x0000FF00 */\n#define DSI_WPCR3_TLPXD               DSI_WPCR3_TLPXD_Msk                      /*!< t-LPXD */\n#define DSI_WPCR3_TLPXD0_Pos          (8U)\n#define DSI_WPCR3_TLPXD0_Msk          (0x1U << DSI_WPCR3_TLPXD0_Pos)           /*!< 0x00000100 */\n#define DSI_WPCR3_TLPXD0              DSI_WPCR3_TLPXD0_Msk\n#define DSI_WPCR3_TLPXD1_Pos          (9U)\n#define DSI_WPCR3_TLPXD1_Msk          (0x1U << DSI_WPCR3_TLPXD1_Pos)           /*!< 0x00000200 */\n#define DSI_WPCR3_TLPXD1              DSI_WPCR3_TLPXD1_Msk\n#define DSI_WPCR3_TLPXD2_Pos          (10U)\n#define DSI_WPCR3_TLPXD2_Msk          (0x1U << DSI_WPCR3_TLPXD2_Pos)           /*!< 0x00000400 */\n#define DSI_WPCR3_TLPXD2              DSI_WPCR3_TLPXD2_Msk\n#define DSI_WPCR3_TLPXD3_Pos          (11U)\n#define DSI_WPCR3_TLPXD3_Msk          (0x1U << DSI_WPCR3_TLPXD3_Pos)           /*!< 0x00000800 */\n#define DSI_WPCR3_TLPXD3              DSI_WPCR3_TLPXD3_Msk\n#define DSI_WPCR3_TLPXD4_Pos          (12U)\n#define DSI_WPCR3_TLPXD4_Msk          (0x1U << DSI_WPCR3_TLPXD4_Pos)           /*!< 0x00001000 */\n#define DSI_WPCR3_TLPXD4              DSI_WPCR3_TLPXD4_Msk\n#define DSI_WPCR3_TLPXD5_Pos          (13U)\n#define DSI_WPCR3_TLPXD5_Msk          (0x1U << DSI_WPCR3_TLPXD5_Pos)           /*!< 0x00002000 */\n#define DSI_WPCR3_TLPXD5              DSI_WPCR3_TLPXD5_Msk\n#define DSI_WPCR3_TLPXD6_Pos          (14U)\n#define DSI_WPCR3_TLPXD6_Msk          (0x1U << DSI_WPCR3_TLPXD6_Pos)           /*!< 0x00004000 */\n#define DSI_WPCR3_TLPXD6              DSI_WPCR3_TLPXD6_Msk\n#define DSI_WPCR3_TLPXD7_Pos          (15U)\n#define DSI_WPCR3_TLPXD7_Msk          (0x1U << DSI_WPCR3_TLPXD7_Pos)           /*!< 0x00008000 */\n#define DSI_WPCR3_TLPXD7              DSI_WPCR3_TLPXD7_Msk\n\n#define DSI_WPCR3_THSEXIT_Pos         (16U)\n#define DSI_WPCR3_THSEXIT_Msk         (0xFFU << DSI_WPCR3_THSEXIT_Pos)         /*!< 0x00FF0000 */\n#define DSI_WPCR3_THSEXIT             DSI_WPCR3_THSEXIT_Msk                    /*!< t-HSEXIT */\n#define DSI_WPCR3_THSEXIT0_Pos        (16U)\n#define DSI_WPCR3_THSEXIT0_Msk        (0x1U << DSI_WPCR3_THSEXIT0_Pos)         /*!< 0x00010000 */\n#define DSI_WPCR3_THSEXIT0            DSI_WPCR3_THSEXIT0_Msk\n#define DSI_WPCR3_THSEXIT1_Pos        (17U)\n#define DSI_WPCR3_THSEXIT1_Msk        (0x1U << DSI_WPCR3_THSEXIT1_Pos)         /*!< 0x00020000 */\n#define DSI_WPCR3_THSEXIT1            DSI_WPCR3_THSEXIT1_Msk\n#define DSI_WPCR3_THSEXIT2_Pos        (18U)\n#define DSI_WPCR3_THSEXIT2_Msk        (0x1U << DSI_WPCR3_THSEXIT2_Pos)         /*!< 0x00040000 */\n#define DSI_WPCR3_THSEXIT2            DSI_WPCR3_THSEXIT2_Msk\n#define DSI_WPCR3_THSEXIT3_Pos        (19U)\n#define DSI_WPCR3_THSEXIT3_Msk        (0x1U << DSI_WPCR3_THSEXIT3_Pos)         /*!< 0x00080000 */\n#define DSI_WPCR3_THSEXIT3            DSI_WPCR3_THSEXIT3_Msk\n#define DSI_WPCR3_THSEXIT4_Pos        (20U)\n#define DSI_WPCR3_THSEXIT4_Msk        (0x1U << DSI_WPCR3_THSEXIT4_Pos)         /*!< 0x00100000 */\n#define DSI_WPCR3_THSEXIT4            DSI_WPCR3_THSEXIT4_Msk\n#define DSI_WPCR3_THSEXIT5_Pos        (21U)\n#define DSI_WPCR3_THSEXIT5_Msk        (0x1U << DSI_WPCR3_THSEXIT5_Pos)         /*!< 0x00200000 */\n#define DSI_WPCR3_THSEXIT5            DSI_WPCR3_THSEXIT5_Msk\n#define DSI_WPCR3_THSEXIT6_Pos        (22U)\n#define DSI_WPCR3_THSEXIT6_Msk        (0x1U << DSI_WPCR3_THSEXIT6_Pos)         /*!< 0x00400000 */\n#define DSI_WPCR3_THSEXIT6            DSI_WPCR3_THSEXIT6_Msk\n#define DSI_WPCR3_THSEXIT7_Pos        (23U)\n#define DSI_WPCR3_THSEXIT7_Msk        (0x1U << DSI_WPCR3_THSEXIT7_Pos)         /*!< 0x00800000 */\n#define DSI_WPCR3_THSEXIT7            DSI_WPCR3_THSEXIT7_Msk\n\n#define DSI_WPCR3_TLPXC_Pos           (24U)\n#define DSI_WPCR3_TLPXC_Msk           (0xFFU << DSI_WPCR3_TLPXC_Pos)           /*!< 0xFF000000 */\n#define DSI_WPCR3_TLPXC               DSI_WPCR3_TLPXC_Msk                      /*!< t-LPXC */\n#define DSI_WPCR3_TLPXC0_Pos          (24U)\n#define DSI_WPCR3_TLPXC0_Msk          (0x1U << DSI_WPCR3_TLPXC0_Pos)           /*!< 0x01000000 */\n#define DSI_WPCR3_TLPXC0              DSI_WPCR3_TLPXC0_Msk\n#define DSI_WPCR3_TLPXC1_Pos          (25U)\n#define DSI_WPCR3_TLPXC1_Msk          (0x1U << DSI_WPCR3_TLPXC1_Pos)           /*!< 0x02000000 */\n#define DSI_WPCR3_TLPXC1              DSI_WPCR3_TLPXC1_Msk\n#define DSI_WPCR3_TLPXC2_Pos          (26U)\n#define DSI_WPCR3_TLPXC2_Msk          (0x1U << DSI_WPCR3_TLPXC2_Pos)           /*!< 0x04000000 */\n#define DSI_WPCR3_TLPXC2              DSI_WPCR3_TLPXC2_Msk\n#define DSI_WPCR3_TLPXC3_Pos          (27U)\n#define DSI_WPCR3_TLPXC3_Msk          (0x1U << DSI_WPCR3_TLPXC3_Pos)           /*!< 0x08000000 */\n#define DSI_WPCR3_TLPXC3              DSI_WPCR3_TLPXC3_Msk\n#define DSI_WPCR3_TLPXC4_Pos          (28U)\n#define DSI_WPCR3_TLPXC4_Msk          (0x1U << DSI_WPCR3_TLPXC4_Pos)           /*!< 0x10000000 */\n#define DSI_WPCR3_TLPXC4              DSI_WPCR3_TLPXC4_Msk\n#define DSI_WPCR3_TLPXC5_Pos          (29U)\n#define DSI_WPCR3_TLPXC5_Msk          (0x1U << DSI_WPCR3_TLPXC5_Pos)           /*!< 0x20000000 */\n#define DSI_WPCR3_TLPXC5              DSI_WPCR3_TLPXC5_Msk\n#define DSI_WPCR3_TLPXC6_Pos          (30U)\n#define DSI_WPCR3_TLPXC6_Msk          (0x1U << DSI_WPCR3_TLPXC6_Pos)           /*!< 0x40000000 */\n#define DSI_WPCR3_TLPXC6              DSI_WPCR3_TLPXC6_Msk\n#define DSI_WPCR3_TLPXC7_Pos          (31U)\n#define DSI_WPCR3_TLPXC7_Msk          (0x1U << DSI_WPCR3_TLPXC7_Pos)           /*!< 0x80000000 */\n#define DSI_WPCR3_TLPXC7              DSI_WPCR3_TLPXC7_Msk\n\n/*******************  Bit definition for DSI_WPCR4 register  ***************/\n#define DSI_WPCR4_TCLKPOST_Pos        (0U)\n#define DSI_WPCR4_TCLKPOST_Msk        (0xFFU << DSI_WPCR4_TCLKPOST_Pos)        /*!< 0x000000FF */\n#define DSI_WPCR4_TCLKPOST            DSI_WPCR4_TCLKPOST_Msk                   /*!< t-CLKPOST */\n#define DSI_WPCR4_TCLKPOST0_Pos       (0U)\n#define DSI_WPCR4_TCLKPOST0_Msk       (0x1U << DSI_WPCR4_TCLKPOST0_Pos)        /*!< 0x00000001 */\n#define DSI_WPCR4_TCLKPOST0           DSI_WPCR4_TCLKPOST0_Msk\n#define DSI_WPCR4_TCLKPOST1_Pos       (1U)\n#define DSI_WPCR4_TCLKPOST1_Msk       (0x1U << DSI_WPCR4_TCLKPOST1_Pos)        /*!< 0x00000002 */\n#define DSI_WPCR4_TCLKPOST1           DSI_WPCR4_TCLKPOST1_Msk\n#define DSI_WPCR4_TCLKPOST2_Pos       (2U)\n#define DSI_WPCR4_TCLKPOST2_Msk       (0x1U << DSI_WPCR4_TCLKPOST2_Pos)        /*!< 0x00000004 */\n#define DSI_WPCR4_TCLKPOST2           DSI_WPCR4_TCLKPOST2_Msk\n#define DSI_WPCR4_TCLKPOST3_Pos       (3U)\n#define DSI_WPCR4_TCLKPOST3_Msk       (0x1U << DSI_WPCR4_TCLKPOST3_Pos)        /*!< 0x00000008 */\n#define DSI_WPCR4_TCLKPOST3           DSI_WPCR4_TCLKPOST3_Msk\n#define DSI_WPCR4_TCLKPOST4_Pos       (4U)\n#define DSI_WPCR4_TCLKPOST4_Msk       (0x1U << DSI_WPCR4_TCLKPOST4_Pos)        /*!< 0x00000010 */\n#define DSI_WPCR4_TCLKPOST4           DSI_WPCR4_TCLKPOST4_Msk\n#define DSI_WPCR4_TCLKPOST5_Pos       (5U)\n#define DSI_WPCR4_TCLKPOST5_Msk       (0x1U << DSI_WPCR4_TCLKPOST5_Pos)        /*!< 0x00000020 */\n#define DSI_WPCR4_TCLKPOST5           DSI_WPCR4_TCLKPOST5_Msk\n#define DSI_WPCR4_TCLKPOST6_Pos       (6U)\n#define DSI_WPCR4_TCLKPOST6_Msk       (0x1U << DSI_WPCR4_TCLKPOST6_Pos)        /*!< 0x00000040 */\n#define DSI_WPCR4_TCLKPOST6           DSI_WPCR4_TCLKPOST6_Msk\n#define DSI_WPCR4_TCLKPOST7_Pos       (7U)\n#define DSI_WPCR4_TCLKPOST7_Msk       (0x1U << DSI_WPCR4_TCLKPOST7_Pos)        /*!< 0x00000080 */\n#define DSI_WPCR4_TCLKPOST7           DSI_WPCR4_TCLKPOST7_Msk\n\n/*******************  Bit definition for DSI_WRPCR register  ***************/\n#define DSI_WRPCR_PLLEN_Pos           (0U)\n#define DSI_WRPCR_PLLEN_Msk           (0x1U << DSI_WRPCR_PLLEN_Pos)            /*!< 0x00000001 */\n#define DSI_WRPCR_PLLEN               DSI_WRPCR_PLLEN_Msk                      /*!< PLL Enable */\n#define DSI_WRPCR_PLL_NDIV_Pos        (2U)\n#define DSI_WRPCR_PLL_NDIV_Msk        (0x7FU << DSI_WRPCR_PLL_NDIV_Pos)        /*!< 0x000001FC */\n#define DSI_WRPCR_PLL_NDIV            DSI_WRPCR_PLL_NDIV_Msk                   /*!< PLL Loop Division Factor */\n#define DSI_WRPCR_PLL_NDIV0_Pos       (2U)\n#define DSI_WRPCR_PLL_NDIV0_Msk       (0x1U << DSI_WRPCR_PLL_NDIV0_Pos)        /*!< 0x00000004 */\n#define DSI_WRPCR_PLL_NDIV0           DSI_WRPCR_PLL_NDIV0_Msk\n#define DSI_WRPCR_PLL_NDIV1_Pos       (3U)\n#define DSI_WRPCR_PLL_NDIV1_Msk       (0x1U << DSI_WRPCR_PLL_NDIV1_Pos)        /*!< 0x00000008 */\n#define DSI_WRPCR_PLL_NDIV1           DSI_WRPCR_PLL_NDIV1_Msk\n#define DSI_WRPCR_PLL_NDIV2_Pos       (4U)\n#define DSI_WRPCR_PLL_NDIV2_Msk       (0x1U << DSI_WRPCR_PLL_NDIV2_Pos)        /*!< 0x00000010 */\n#define DSI_WRPCR_PLL_NDIV2           DSI_WRPCR_PLL_NDIV2_Msk\n#define DSI_WRPCR_PLL_NDIV3_Pos       (5U)\n#define DSI_WRPCR_PLL_NDIV3_Msk       (0x1U << DSI_WRPCR_PLL_NDIV3_Pos)        /*!< 0x00000020 */\n#define DSI_WRPCR_PLL_NDIV3           DSI_WRPCR_PLL_NDIV3_Msk\n#define DSI_WRPCR_PLL_NDIV4_Pos       (6U)\n#define DSI_WRPCR_PLL_NDIV4_Msk       (0x1U << DSI_WRPCR_PLL_NDIV4_Pos)        /*!< 0x00000040 */\n#define DSI_WRPCR_PLL_NDIV4           DSI_WRPCR_PLL_NDIV4_Msk\n#define DSI_WRPCR_PLL_NDIV5_Pos       (7U)\n#define DSI_WRPCR_PLL_NDIV5_Msk       (0x1U << DSI_WRPCR_PLL_NDIV5_Pos)        /*!< 0x00000080 */\n#define DSI_WRPCR_PLL_NDIV5           DSI_WRPCR_PLL_NDIV5_Msk\n#define DSI_WRPCR_PLL_NDIV6_Pos       (8U)\n#define DSI_WRPCR_PLL_NDIV6_Msk       (0x1U << DSI_WRPCR_PLL_NDIV6_Pos)        /*!< 0x00000100 */\n#define DSI_WRPCR_PLL_NDIV6           DSI_WRPCR_PLL_NDIV6_Msk\n\n#define DSI_WRPCR_PLL_IDF_Pos         (11U)\n#define DSI_WRPCR_PLL_IDF_Msk         (0xFU << DSI_WRPCR_PLL_IDF_Pos)          /*!< 0x00007800 */\n#define DSI_WRPCR_PLL_IDF             DSI_WRPCR_PLL_IDF_Msk                    /*!< PLL Input Division Factor */\n#define DSI_WRPCR_PLL_IDF0_Pos        (11U)\n#define DSI_WRPCR_PLL_IDF0_Msk        (0x1U << DSI_WRPCR_PLL_IDF0_Pos)         /*!< 0x00000800 */\n#define DSI_WRPCR_PLL_IDF0            DSI_WRPCR_PLL_IDF0_Msk\n#define DSI_WRPCR_PLL_IDF1_Pos        (12U)\n#define DSI_WRPCR_PLL_IDF1_Msk        (0x1U << DSI_WRPCR_PLL_IDF1_Pos)         /*!< 0x00001000 */\n#define DSI_WRPCR_PLL_IDF1            DSI_WRPCR_PLL_IDF1_Msk\n#define DSI_WRPCR_PLL_IDF2_Pos        (13U)\n#define DSI_WRPCR_PLL_IDF2_Msk        (0x1U << DSI_WRPCR_PLL_IDF2_Pos)         /*!< 0x00002000 */\n#define DSI_WRPCR_PLL_IDF2            DSI_WRPCR_PLL_IDF2_Msk\n#define DSI_WRPCR_PLL_IDF3_Pos        (14U)\n#define DSI_WRPCR_PLL_IDF3_Msk        (0x1U << DSI_WRPCR_PLL_IDF3_Pos)         /*!< 0x00004000 */\n#define DSI_WRPCR_PLL_IDF3            DSI_WRPCR_PLL_IDF3_Msk\n\n#define DSI_WRPCR_PLL_ODF_Pos         (16U)\n#define DSI_WRPCR_PLL_ODF_Msk         (0x3U << DSI_WRPCR_PLL_ODF_Pos)          /*!< 0x00030000 */\n#define DSI_WRPCR_PLL_ODF             DSI_WRPCR_PLL_ODF_Msk                    /*!< PLL Output Division Factor */\n#define DSI_WRPCR_PLL_ODF0_Pos        (16U)\n#define DSI_WRPCR_PLL_ODF0_Msk        (0x1U << DSI_WRPCR_PLL_ODF0_Pos)         /*!< 0x00010000 */\n#define DSI_WRPCR_PLL_ODF0            DSI_WRPCR_PLL_ODF0_Msk\n#define DSI_WRPCR_PLL_ODF1_Pos        (17U)\n#define DSI_WRPCR_PLL_ODF1_Msk        (0x1U << DSI_WRPCR_PLL_ODF1_Pos)         /*!< 0x00020000 */\n#define DSI_WRPCR_PLL_ODF1            DSI_WRPCR_PLL_ODF1_Msk\n\n#define DSI_WRPCR_REGEN_Pos           (24U)\n#define DSI_WRPCR_REGEN_Msk           (0x1U << DSI_WRPCR_REGEN_Pos)            /*!< 0x01000000 */\n#define DSI_WRPCR_REGEN               DSI_WRPCR_REGEN_Msk                      /*!< Regulator Enable */\n\n/******************************************************************************/\n/*                                                                            */\n/*                    External Interrupt/Event Controller                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for EXTI_IMR register  *******************/\n#define EXTI_IMR_MR0_Pos          (0U)\n#define EXTI_IMR_MR0_Msk          (0x1U << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */\n#define EXTI_IMR_MR1_Pos          (1U)\n#define EXTI_IMR_MR1_Msk          (0x1U << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */\n#define EXTI_IMR_MR2_Pos          (2U)\n#define EXTI_IMR_MR2_Msk          (0x1U << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */\n#define EXTI_IMR_MR3_Pos          (3U)\n#define EXTI_IMR_MR3_Msk          (0x1U << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */\n#define EXTI_IMR_MR4_Pos          (4U)\n#define EXTI_IMR_MR4_Msk          (0x1U << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */\n#define EXTI_IMR_MR5_Pos          (5U)\n#define EXTI_IMR_MR5_Msk          (0x1U << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */\n#define EXTI_IMR_MR6_Pos          (6U)\n#define EXTI_IMR_MR6_Msk          (0x1U << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */\n#define EXTI_IMR_MR7_Pos          (7U)\n#define EXTI_IMR_MR7_Msk          (0x1U << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */\n#define EXTI_IMR_MR8_Pos          (8U)\n#define EXTI_IMR_MR8_Msk          (0x1U << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */\n#define EXTI_IMR_MR9_Pos          (9U)\n#define EXTI_IMR_MR9_Msk          (0x1U << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */\n#define EXTI_IMR_MR10_Pos         (10U)\n#define EXTI_IMR_MR10_Msk         (0x1U << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */\n#define EXTI_IMR_MR11_Pos         (11U)\n#define EXTI_IMR_MR11_Msk         (0x1U << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */\n#define EXTI_IMR_MR12_Pos         (12U)\n#define EXTI_IMR_MR12_Msk         (0x1U << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */\n#define EXTI_IMR_MR13_Pos         (13U)\n#define EXTI_IMR_MR13_Msk         (0x1U << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */\n#define EXTI_IMR_MR14_Pos         (14U)\n#define EXTI_IMR_MR14_Msk         (0x1U << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */\n#define EXTI_IMR_MR15_Pos         (15U)\n#define EXTI_IMR_MR15_Msk         (0x1U << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */\n#define EXTI_IMR_MR16_Pos         (16U)\n#define EXTI_IMR_MR16_Msk         (0x1U << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */\n#define EXTI_IMR_MR17_Pos         (17U)\n#define EXTI_IMR_MR17_Msk         (0x1U << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */\n#define EXTI_IMR_MR18_Pos         (18U)\n#define EXTI_IMR_MR18_Msk         (0x1U << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */\n#define EXTI_IMR_MR19_Pos         (19U)\n#define EXTI_IMR_MR19_Msk         (0x1U << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */\n#define EXTI_IMR_MR20_Pos         (20U)\n#define EXTI_IMR_MR20_Msk         (0x1U << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */\n#define EXTI_IMR_MR21_Pos         (21U)\n#define EXTI_IMR_MR21_Msk         (0x1U << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */\n#define EXTI_IMR_MR22_Pos         (22U)\n#define EXTI_IMR_MR22_Msk         (0x1U << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */\n\n/* Reference Defines */\n#define  EXTI_IMR_IM0                        EXTI_IMR_MR0\n#define  EXTI_IMR_IM1                        EXTI_IMR_MR1\n#define  EXTI_IMR_IM2                        EXTI_IMR_MR2\n#define  EXTI_IMR_IM3                        EXTI_IMR_MR3\n#define  EXTI_IMR_IM4                        EXTI_IMR_MR4\n#define  EXTI_IMR_IM5                        EXTI_IMR_MR5\n#define  EXTI_IMR_IM6                        EXTI_IMR_MR6\n#define  EXTI_IMR_IM7                        EXTI_IMR_MR7\n#define  EXTI_IMR_IM8                        EXTI_IMR_MR8\n#define  EXTI_IMR_IM9                        EXTI_IMR_MR9\n#define  EXTI_IMR_IM10                       EXTI_IMR_MR10\n#define  EXTI_IMR_IM11                       EXTI_IMR_MR11\n#define  EXTI_IMR_IM12                       EXTI_IMR_MR12\n#define  EXTI_IMR_IM13                       EXTI_IMR_MR13\n#define  EXTI_IMR_IM14                       EXTI_IMR_MR14\n#define  EXTI_IMR_IM15                       EXTI_IMR_MR15\n#define  EXTI_IMR_IM16                       EXTI_IMR_MR16\n#define  EXTI_IMR_IM17                       EXTI_IMR_MR17\n#define  EXTI_IMR_IM18                       EXTI_IMR_MR18\n#define  EXTI_IMR_IM19                       EXTI_IMR_MR19\n#define  EXTI_IMR_IM20                       EXTI_IMR_MR20\n#define  EXTI_IMR_IM21                       EXTI_IMR_MR21\n#define  EXTI_IMR_IM22                       EXTI_IMR_MR22\n#define EXTI_IMR_IM_Pos           (0U)\n#define EXTI_IMR_IM_Msk           (0x7FFFFFU << EXTI_IMR_IM_Pos)               /*!< 0x007FFFFF */\n#define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */\n\n/*******************  Bit definition for EXTI_EMR register  *******************/\n#define EXTI_EMR_MR0_Pos          (0U)\n#define EXTI_EMR_MR0_Msk          (0x1U << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */\n#define EXTI_EMR_MR1_Pos          (1U)\n#define EXTI_EMR_MR1_Msk          (0x1U << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */\n#define EXTI_EMR_MR2_Pos          (2U)\n#define EXTI_EMR_MR2_Msk          (0x1U << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */\n#define EXTI_EMR_MR3_Pos          (3U)\n#define EXTI_EMR_MR3_Msk          (0x1U << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */\n#define EXTI_EMR_MR4_Pos          (4U)\n#define EXTI_EMR_MR4_Msk          (0x1U << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */\n#define EXTI_EMR_MR5_Pos          (5U)\n#define EXTI_EMR_MR5_Msk          (0x1U << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */\n#define EXTI_EMR_MR6_Pos          (6U)\n#define EXTI_EMR_MR6_Msk          (0x1U << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */\n#define EXTI_EMR_MR7_Pos          (7U)\n#define EXTI_EMR_MR7_Msk          (0x1U << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */\n#define EXTI_EMR_MR8_Pos          (8U)\n#define EXTI_EMR_MR8_Msk          (0x1U << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */\n#define EXTI_EMR_MR9_Pos          (9U)\n#define EXTI_EMR_MR9_Msk          (0x1U << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */\n#define EXTI_EMR_MR10_Pos         (10U)\n#define EXTI_EMR_MR10_Msk         (0x1U << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */\n#define EXTI_EMR_MR11_Pos         (11U)\n#define EXTI_EMR_MR11_Msk         (0x1U << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */\n#define EXTI_EMR_MR12_Pos         (12U)\n#define EXTI_EMR_MR12_Msk         (0x1U << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */\n#define EXTI_EMR_MR13_Pos         (13U)\n#define EXTI_EMR_MR13_Msk         (0x1U << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */\n#define EXTI_EMR_MR14_Pos         (14U)\n#define EXTI_EMR_MR14_Msk         (0x1U << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */\n#define EXTI_EMR_MR15_Pos         (15U)\n#define EXTI_EMR_MR15_Msk         (0x1U << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */\n#define EXTI_EMR_MR16_Pos         (16U)\n#define EXTI_EMR_MR16_Msk         (0x1U << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */\n#define EXTI_EMR_MR17_Pos         (17U)\n#define EXTI_EMR_MR17_Msk         (0x1U << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */\n#define EXTI_EMR_MR18_Pos         (18U)\n#define EXTI_EMR_MR18_Msk         (0x1U << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */\n#define EXTI_EMR_MR19_Pos         (19U)\n#define EXTI_EMR_MR19_Msk         (0x1U << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */\n#define EXTI_EMR_MR20_Pos         (20U)\n#define EXTI_EMR_MR20_Msk         (0x1U << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */\n#define EXTI_EMR_MR21_Pos         (21U)\n#define EXTI_EMR_MR21_Msk         (0x1U << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */\n#define EXTI_EMR_MR22_Pos         (22U)\n#define EXTI_EMR_MR22_Msk         (0x1U << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */\n\n/* Reference Defines */\n#define  EXTI_EMR_EM0                        EXTI_EMR_MR0\n#define  EXTI_EMR_EM1                        EXTI_EMR_MR1\n#define  EXTI_EMR_EM2                        EXTI_EMR_MR2\n#define  EXTI_EMR_EM3                        EXTI_EMR_MR3\n#define  EXTI_EMR_EM4                        EXTI_EMR_MR4\n#define  EXTI_EMR_EM5                        EXTI_EMR_MR5\n#define  EXTI_EMR_EM6                        EXTI_EMR_MR6\n#define  EXTI_EMR_EM7                        EXTI_EMR_MR7\n#define  EXTI_EMR_EM8                        EXTI_EMR_MR8\n#define  EXTI_EMR_EM9                        EXTI_EMR_MR9\n#define  EXTI_EMR_EM10                       EXTI_EMR_MR10\n#define  EXTI_EMR_EM11                       EXTI_EMR_MR11\n#define  EXTI_EMR_EM12                       EXTI_EMR_MR12\n#define  EXTI_EMR_EM13                       EXTI_EMR_MR13\n#define  EXTI_EMR_EM14                       EXTI_EMR_MR14\n#define  EXTI_EMR_EM15                       EXTI_EMR_MR15\n#define  EXTI_EMR_EM16                       EXTI_EMR_MR16\n#define  EXTI_EMR_EM17                       EXTI_EMR_MR17\n#define  EXTI_EMR_EM18                       EXTI_EMR_MR18\n#define  EXTI_EMR_EM19                       EXTI_EMR_MR19\n#define  EXTI_EMR_EM20                       EXTI_EMR_MR20\n#define  EXTI_EMR_EM21                       EXTI_EMR_MR21\n#define  EXTI_EMR_EM22                       EXTI_EMR_MR22\n\n/******************  Bit definition for EXTI_RTSR register  *******************/\n#define EXTI_RTSR_TR0_Pos         (0U)\n#define EXTI_RTSR_TR0_Msk         (0x1U << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */\n#define EXTI_RTSR_TR1_Pos         (1U)\n#define EXTI_RTSR_TR1_Msk         (0x1U << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */\n#define EXTI_RTSR_TR2_Pos         (2U)\n#define EXTI_RTSR_TR2_Msk         (0x1U << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */\n#define EXTI_RTSR_TR3_Pos         (3U)\n#define EXTI_RTSR_TR3_Msk         (0x1U << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */\n#define EXTI_RTSR_TR4_Pos         (4U)\n#define EXTI_RTSR_TR4_Msk         (0x1U << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */\n#define EXTI_RTSR_TR5_Pos         (5U)\n#define EXTI_RTSR_TR5_Msk         (0x1U << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */\n#define EXTI_RTSR_TR6_Pos         (6U)\n#define EXTI_RTSR_TR6_Msk         (0x1U << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */\n#define EXTI_RTSR_TR7_Pos         (7U)\n#define EXTI_RTSR_TR7_Msk         (0x1U << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */\n#define EXTI_RTSR_TR8_Pos         (8U)\n#define EXTI_RTSR_TR8_Msk         (0x1U << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */\n#define EXTI_RTSR_TR9_Pos         (9U)\n#define EXTI_RTSR_TR9_Msk         (0x1U << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */\n#define EXTI_RTSR_TR10_Pos        (10U)\n#define EXTI_RTSR_TR10_Msk        (0x1U << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */\n#define EXTI_RTSR_TR11_Pos        (11U)\n#define EXTI_RTSR_TR11_Msk        (0x1U << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */\n#define EXTI_RTSR_TR12_Pos        (12U)\n#define EXTI_RTSR_TR12_Msk        (0x1U << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */\n#define EXTI_RTSR_TR13_Pos        (13U)\n#define EXTI_RTSR_TR13_Msk        (0x1U << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */\n#define EXTI_RTSR_TR14_Pos        (14U)\n#define EXTI_RTSR_TR14_Msk        (0x1U << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */\n#define EXTI_RTSR_TR15_Pos        (15U)\n#define EXTI_RTSR_TR15_Msk        (0x1U << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */\n#define EXTI_RTSR_TR16_Pos        (16U)\n#define EXTI_RTSR_TR16_Msk        (0x1U << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */\n#define EXTI_RTSR_TR17_Pos        (17U)\n#define EXTI_RTSR_TR17_Msk        (0x1U << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */\n#define EXTI_RTSR_TR18_Pos        (18U)\n#define EXTI_RTSR_TR18_Msk        (0x1U << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */\n#define EXTI_RTSR_TR19_Pos        (19U)\n#define EXTI_RTSR_TR19_Msk        (0x1U << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */\n#define EXTI_RTSR_TR20_Pos        (20U)\n#define EXTI_RTSR_TR20_Msk        (0x1U << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */\n#define EXTI_RTSR_TR21_Pos        (21U)\n#define EXTI_RTSR_TR21_Msk        (0x1U << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */\n#define EXTI_RTSR_TR22_Pos        (22U)\n#define EXTI_RTSR_TR22_Msk        (0x1U << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_FTSR register  *******************/\n#define EXTI_FTSR_TR0_Pos         (0U)\n#define EXTI_FTSR_TR0_Msk         (0x1U << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */\n#define EXTI_FTSR_TR1_Pos         (1U)\n#define EXTI_FTSR_TR1_Msk         (0x1U << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */\n#define EXTI_FTSR_TR2_Pos         (2U)\n#define EXTI_FTSR_TR2_Msk         (0x1U << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */\n#define EXTI_FTSR_TR3_Pos         (3U)\n#define EXTI_FTSR_TR3_Msk         (0x1U << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */\n#define EXTI_FTSR_TR4_Pos         (4U)\n#define EXTI_FTSR_TR4_Msk         (0x1U << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */\n#define EXTI_FTSR_TR5_Pos         (5U)\n#define EXTI_FTSR_TR5_Msk         (0x1U << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */\n#define EXTI_FTSR_TR6_Pos         (6U)\n#define EXTI_FTSR_TR6_Msk         (0x1U << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */\n#define EXTI_FTSR_TR7_Pos         (7U)\n#define EXTI_FTSR_TR7_Msk         (0x1U << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */\n#define EXTI_FTSR_TR8_Pos         (8U)\n#define EXTI_FTSR_TR8_Msk         (0x1U << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */\n#define EXTI_FTSR_TR9_Pos         (9U)\n#define EXTI_FTSR_TR9_Msk         (0x1U << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */\n#define EXTI_FTSR_TR10_Pos        (10U)\n#define EXTI_FTSR_TR10_Msk        (0x1U << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */\n#define EXTI_FTSR_TR11_Pos        (11U)\n#define EXTI_FTSR_TR11_Msk        (0x1U << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */\n#define EXTI_FTSR_TR12_Pos        (12U)\n#define EXTI_FTSR_TR12_Msk        (0x1U << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */\n#define EXTI_FTSR_TR13_Pos        (13U)\n#define EXTI_FTSR_TR13_Msk        (0x1U << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */\n#define EXTI_FTSR_TR14_Pos        (14U)\n#define EXTI_FTSR_TR14_Msk        (0x1U << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */\n#define EXTI_FTSR_TR15_Pos        (15U)\n#define EXTI_FTSR_TR15_Msk        (0x1U << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */\n#define EXTI_FTSR_TR16_Pos        (16U)\n#define EXTI_FTSR_TR16_Msk        (0x1U << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */\n#define EXTI_FTSR_TR17_Pos        (17U)\n#define EXTI_FTSR_TR17_Msk        (0x1U << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */\n#define EXTI_FTSR_TR18_Pos        (18U)\n#define EXTI_FTSR_TR18_Msk        (0x1U << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */\n#define EXTI_FTSR_TR19_Pos        (19U)\n#define EXTI_FTSR_TR19_Msk        (0x1U << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */\n#define EXTI_FTSR_TR20_Pos        (20U)\n#define EXTI_FTSR_TR20_Msk        (0x1U << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */\n#define EXTI_FTSR_TR21_Pos        (21U)\n#define EXTI_FTSR_TR21_Msk        (0x1U << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */\n#define EXTI_FTSR_TR22_Pos        (22U)\n#define EXTI_FTSR_TR22_Msk        (0x1U << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_SWIER register  ******************/\n#define EXTI_SWIER_SWIER0_Pos     (0U)\n#define EXTI_SWIER_SWIER0_Msk     (0x1U << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */\n#define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */\n#define EXTI_SWIER_SWIER1_Pos     (1U)\n#define EXTI_SWIER_SWIER1_Msk     (0x1U << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */\n#define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */\n#define EXTI_SWIER_SWIER2_Pos     (2U)\n#define EXTI_SWIER_SWIER2_Msk     (0x1U << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */\n#define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */\n#define EXTI_SWIER_SWIER3_Pos     (3U)\n#define EXTI_SWIER_SWIER3_Msk     (0x1U << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */\n#define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */\n#define EXTI_SWIER_SWIER4_Pos     (4U)\n#define EXTI_SWIER_SWIER4_Msk     (0x1U << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */\n#define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */\n#define EXTI_SWIER_SWIER5_Pos     (5U)\n#define EXTI_SWIER_SWIER5_Msk     (0x1U << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */\n#define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */\n#define EXTI_SWIER_SWIER6_Pos     (6U)\n#define EXTI_SWIER_SWIER6_Msk     (0x1U << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */\n#define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */\n#define EXTI_SWIER_SWIER7_Pos     (7U)\n#define EXTI_SWIER_SWIER7_Msk     (0x1U << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */\n#define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */\n#define EXTI_SWIER_SWIER8_Pos     (8U)\n#define EXTI_SWIER_SWIER8_Msk     (0x1U << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */\n#define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */\n#define EXTI_SWIER_SWIER9_Pos     (9U)\n#define EXTI_SWIER_SWIER9_Msk     (0x1U << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */\n#define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */\n#define EXTI_SWIER_SWIER10_Pos    (10U)\n#define EXTI_SWIER_SWIER10_Msk    (0x1U << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */\n#define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */\n#define EXTI_SWIER_SWIER11_Pos    (11U)\n#define EXTI_SWIER_SWIER11_Msk    (0x1U << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */\n#define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */\n#define EXTI_SWIER_SWIER12_Pos    (12U)\n#define EXTI_SWIER_SWIER12_Msk    (0x1U << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */\n#define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */\n#define EXTI_SWIER_SWIER13_Pos    (13U)\n#define EXTI_SWIER_SWIER13_Msk    (0x1U << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */\n#define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */\n#define EXTI_SWIER_SWIER14_Pos    (14U)\n#define EXTI_SWIER_SWIER14_Msk    (0x1U << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */\n#define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */\n#define EXTI_SWIER_SWIER15_Pos    (15U)\n#define EXTI_SWIER_SWIER15_Msk    (0x1U << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */\n#define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */\n#define EXTI_SWIER_SWIER16_Pos    (16U)\n#define EXTI_SWIER_SWIER16_Msk    (0x1U << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */\n#define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */\n#define EXTI_SWIER_SWIER17_Pos    (17U)\n#define EXTI_SWIER_SWIER17_Msk    (0x1U << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */\n#define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */\n#define EXTI_SWIER_SWIER18_Pos    (18U)\n#define EXTI_SWIER_SWIER18_Msk    (0x1U << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */\n#define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */\n#define EXTI_SWIER_SWIER19_Pos    (19U)\n#define EXTI_SWIER_SWIER19_Msk    (0x1U << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */\n#define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */\n#define EXTI_SWIER_SWIER20_Pos    (20U)\n#define EXTI_SWIER_SWIER20_Msk    (0x1U << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */\n#define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */\n#define EXTI_SWIER_SWIER21_Pos    (21U)\n#define EXTI_SWIER_SWIER21_Msk    (0x1U << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */\n#define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */\n#define EXTI_SWIER_SWIER22_Pos    (22U)\n#define EXTI_SWIER_SWIER22_Msk    (0x1U << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */\n#define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */\n\n/*******************  Bit definition for EXTI_PR register  ********************/\n#define EXTI_PR_PR0_Pos           (0U)\n#define EXTI_PR_PR0_Msk           (0x1U << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */\n#define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */\n#define EXTI_PR_PR1_Pos           (1U)\n#define EXTI_PR_PR1_Msk           (0x1U << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */\n#define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */\n#define EXTI_PR_PR2_Pos           (2U)\n#define EXTI_PR_PR2_Msk           (0x1U << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */\n#define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */\n#define EXTI_PR_PR3_Pos           (3U)\n#define EXTI_PR_PR3_Msk           (0x1U << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */\n#define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */\n#define EXTI_PR_PR4_Pos           (4U)\n#define EXTI_PR_PR4_Msk           (0x1U << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */\n#define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */\n#define EXTI_PR_PR5_Pos           (5U)\n#define EXTI_PR_PR5_Msk           (0x1U << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */\n#define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */\n#define EXTI_PR_PR6_Pos           (6U)\n#define EXTI_PR_PR6_Msk           (0x1U << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */\n#define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */\n#define EXTI_PR_PR7_Pos           (7U)\n#define EXTI_PR_PR7_Msk           (0x1U << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */\n#define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */\n#define EXTI_PR_PR8_Pos           (8U)\n#define EXTI_PR_PR8_Msk           (0x1U << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */\n#define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */\n#define EXTI_PR_PR9_Pos           (9U)\n#define EXTI_PR_PR9_Msk           (0x1U << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */\n#define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */\n#define EXTI_PR_PR10_Pos          (10U)\n#define EXTI_PR_PR10_Msk          (0x1U << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */\n#define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */\n#define EXTI_PR_PR11_Pos          (11U)\n#define EXTI_PR_PR11_Msk          (0x1U << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */\n#define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */\n#define EXTI_PR_PR12_Pos          (12U)\n#define EXTI_PR_PR12_Msk          (0x1U << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */\n#define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */\n#define EXTI_PR_PR13_Pos          (13U)\n#define EXTI_PR_PR13_Msk          (0x1U << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */\n#define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */\n#define EXTI_PR_PR14_Pos          (14U)\n#define EXTI_PR_PR14_Msk          (0x1U << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */\n#define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */\n#define EXTI_PR_PR15_Pos          (15U)\n#define EXTI_PR_PR15_Msk          (0x1U << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */\n#define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */\n#define EXTI_PR_PR16_Pos          (16U)\n#define EXTI_PR_PR16_Msk          (0x1U << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */\n#define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */\n#define EXTI_PR_PR17_Pos          (17U)\n#define EXTI_PR_PR17_Msk          (0x1U << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */\n#define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */\n#define EXTI_PR_PR18_Pos          (18U)\n#define EXTI_PR_PR18_Msk          (0x1U << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */\n#define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */\n#define EXTI_PR_PR19_Pos          (19U)\n#define EXTI_PR_PR19_Msk          (0x1U << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */\n#define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */\n#define EXTI_PR_PR20_Pos          (20U)\n#define EXTI_PR_PR20_Msk          (0x1U << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */\n#define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */\n#define EXTI_PR_PR21_Pos          (21U)\n#define EXTI_PR_PR21_Msk          (0x1U << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */\n#define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */\n#define EXTI_PR_PR22_Pos          (22U)\n#define EXTI_PR_PR22_Msk          (0x1U << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */\n#define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    FLASH                                   */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bits definition for FLASH_ACR register  *****************/\n#define FLASH_ACR_LATENCY_Pos          (0U)\n#define FLASH_ACR_LATENCY_Msk          (0xFU << FLASH_ACR_LATENCY_Pos)         /*!< 0x0000000F */\n#define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk\n#define FLASH_ACR_LATENCY_0WS          0x00000000U\n#define FLASH_ACR_LATENCY_1WS          0x00000001U\n#define FLASH_ACR_LATENCY_2WS          0x00000002U\n#define FLASH_ACR_LATENCY_3WS          0x00000003U\n#define FLASH_ACR_LATENCY_4WS          0x00000004U\n#define FLASH_ACR_LATENCY_5WS          0x00000005U\n#define FLASH_ACR_LATENCY_6WS          0x00000006U\n#define FLASH_ACR_LATENCY_7WS          0x00000007U\n\n#define FLASH_ACR_LATENCY_8WS          0x00000008U\n#define FLASH_ACR_LATENCY_9WS          0x00000009U\n#define FLASH_ACR_LATENCY_10WS         0x0000000AU\n#define FLASH_ACR_LATENCY_11WS         0x0000000BU\n#define FLASH_ACR_LATENCY_12WS         0x0000000CU\n#define FLASH_ACR_LATENCY_13WS         0x0000000DU\n#define FLASH_ACR_LATENCY_14WS         0x0000000EU\n#define FLASH_ACR_LATENCY_15WS         0x0000000FU\n#define FLASH_ACR_PRFTEN_Pos           (8U)\n#define FLASH_ACR_PRFTEN_Msk           (0x1U << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */\n#define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk\n#define FLASH_ACR_ICEN_Pos             (9U)\n#define FLASH_ACR_ICEN_Msk             (0x1U << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */\n#define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk\n#define FLASH_ACR_DCEN_Pos             (10U)\n#define FLASH_ACR_DCEN_Msk             (0x1U << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */\n#define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk\n#define FLASH_ACR_ICRST_Pos            (11U)\n#define FLASH_ACR_ICRST_Msk            (0x1U << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */\n#define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk\n#define FLASH_ACR_DCRST_Pos            (12U)\n#define FLASH_ACR_DCRST_Msk            (0x1U << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */\n#define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk\n#define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)\n#define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */\n#define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk\n#define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)\n#define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */\n#define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk\n\n/*******************  Bits definition for FLASH_SR register  ******************/\n#define FLASH_SR_EOP_Pos               (0U)\n#define FLASH_SR_EOP_Msk               (0x1U << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */\n#define FLASH_SR_EOP                   FLASH_SR_EOP_Msk\n#define FLASH_SR_SOP_Pos               (1U)\n#define FLASH_SR_SOP_Msk               (0x1U << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */\n#define FLASH_SR_SOP                   FLASH_SR_SOP_Msk\n#define FLASH_SR_WRPERR_Pos            (4U)\n#define FLASH_SR_WRPERR_Msk            (0x1U << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */\n#define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk\n#define FLASH_SR_PGAERR_Pos            (5U)\n#define FLASH_SR_PGAERR_Msk            (0x1U << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */\n#define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk\n#define FLASH_SR_PGPERR_Pos            (6U)\n#define FLASH_SR_PGPERR_Msk            (0x1U << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */\n#define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk\n#define FLASH_SR_PGSERR_Pos            (7U)\n#define FLASH_SR_PGSERR_Msk            (0x1U << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */\n#define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk\n#define FLASH_SR_RDERR_Pos            (8U)\n#define FLASH_SR_RDERR_Msk            (0x1U << FLASH_SR_RDERR_Pos)             /*!< 0x00000100 */\n#define FLASH_SR_RDERR                FLASH_SR_RDERR_Msk\n#define FLASH_SR_BSY_Pos               (16U)\n#define FLASH_SR_BSY_Msk               (0x1U << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */\n#define FLASH_SR_BSY                   FLASH_SR_BSY_Msk\n\n/*******************  Bits definition for FLASH_CR register  ******************/\n#define FLASH_CR_PG_Pos                (0U)\n#define FLASH_CR_PG_Msk                (0x1U << FLASH_CR_PG_Pos)               /*!< 0x00000001 */\n#define FLASH_CR_PG                    FLASH_CR_PG_Msk\n#define FLASH_CR_SER_Pos               (1U)\n#define FLASH_CR_SER_Msk               (0x1U << FLASH_CR_SER_Pos)              /*!< 0x00000002 */\n#define FLASH_CR_SER                   FLASH_CR_SER_Msk\n#define FLASH_CR_MER_Pos               (2U)\n#define FLASH_CR_MER_Msk               (0x1U << FLASH_CR_MER_Pos)              /*!< 0x00000004 */\n#define FLASH_CR_MER                   FLASH_CR_MER_Msk\n#define FLASH_CR_MER1                        FLASH_CR_MER\n#define FLASH_CR_SNB_Pos               (3U)\n#define FLASH_CR_SNB_Msk               (0x1FU << FLASH_CR_SNB_Pos)             /*!< 0x000000F8 */\n#define FLASH_CR_SNB                   FLASH_CR_SNB_Msk\n#define FLASH_CR_SNB_0                 (0x01U << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */\n#define FLASH_CR_SNB_1                 (0x02U << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */\n#define FLASH_CR_SNB_2                 (0x04U << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */\n#define FLASH_CR_SNB_3                 (0x08U << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */\n#define FLASH_CR_SNB_4                 (0x10U << FLASH_CR_SNB_Pos)             /*!< 0x00000080 */\n#define FLASH_CR_PSIZE_Pos             (8U)\n#define FLASH_CR_PSIZE_Msk             (0x3U << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */\n#define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk\n#define FLASH_CR_PSIZE_0               (0x1U << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */\n#define FLASH_CR_PSIZE_1               (0x2U << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */\n#define FLASH_CR_MER2_Pos              (15U)\n#define FLASH_CR_MER2_Msk              (0x1U << FLASH_CR_MER2_Pos)             /*!< 0x00008000 */\n#define FLASH_CR_MER2                  FLASH_CR_MER2_Msk\n#define FLASH_CR_STRT_Pos              (16U)\n#define FLASH_CR_STRT_Msk              (0x1U << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */\n#define FLASH_CR_STRT                  FLASH_CR_STRT_Msk\n#define FLASH_CR_EOPIE_Pos             (24U)\n#define FLASH_CR_EOPIE_Msk             (0x1U << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */\n#define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk\n#define FLASH_CR_LOCK_Pos              (31U)\n#define FLASH_CR_LOCK_Msk              (0x1U << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */\n#define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk\n\n/*******************  Bits definition for FLASH_OPTCR register  ***************/\n#define FLASH_OPTCR_OPTLOCK_Pos        (0U)\n#define FLASH_OPTCR_OPTLOCK_Msk        (0x1U << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */\n#define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk\n#define FLASH_OPTCR_OPTSTRT_Pos        (1U)\n#define FLASH_OPTCR_OPTSTRT_Msk        (0x1U << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */\n#define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk\n\n#define FLASH_OPTCR_BOR_LEV_0          0x00000004U\n#define FLASH_OPTCR_BOR_LEV_1          0x00000008U\n#define FLASH_OPTCR_BOR_LEV_Pos        (2U)\n#define FLASH_OPTCR_BOR_LEV_Msk        (0x3U << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */\n#define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk\n#define FLASH_OPTCR_BFB2_Pos           (4U)\n#define FLASH_OPTCR_BFB2_Msk           (0x1U << FLASH_OPTCR_BFB2_Pos)          /*!< 0x00000010 */\n#define FLASH_OPTCR_BFB2               FLASH_OPTCR_BFB2_Msk\n#define FLASH_OPTCR_WDG_SW_Pos         (5U)\n#define FLASH_OPTCR_WDG_SW_Msk         (0x1U << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */\n#define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk\n#define FLASH_OPTCR_nRST_STOP_Pos      (6U)\n#define FLASH_OPTCR_nRST_STOP_Msk      (0x1U << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */\n#define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk\n#define FLASH_OPTCR_nRST_STDBY_Pos     (7U)\n#define FLASH_OPTCR_nRST_STDBY_Msk     (0x1U << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */\n#define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk\n#define FLASH_OPTCR_RDP_Pos            (8U)\n#define FLASH_OPTCR_RDP_Msk            (0xFFU << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */\n#define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk\n#define FLASH_OPTCR_RDP_0              (0x01U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */\n#define FLASH_OPTCR_RDP_1              (0x02U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */\n#define FLASH_OPTCR_RDP_2              (0x04U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */\n#define FLASH_OPTCR_RDP_3              (0x08U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */\n#define FLASH_OPTCR_RDP_4              (0x10U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */\n#define FLASH_OPTCR_RDP_5              (0x20U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */\n#define FLASH_OPTCR_RDP_6              (0x40U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */\n#define FLASH_OPTCR_RDP_7              (0x80U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */\n#define FLASH_OPTCR_nWRP_Pos           (16U)\n#define FLASH_OPTCR_nWRP_Msk           (0xFFFU << FLASH_OPTCR_nWRP_Pos)        /*!< 0x0FFF0000 */\n#define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk\n#define FLASH_OPTCR_nWRP_0             0x00010000U\n#define FLASH_OPTCR_nWRP_1             0x00020000U\n#define FLASH_OPTCR_nWRP_2             0x00040000U\n#define FLASH_OPTCR_nWRP_3             0x00080000U\n#define FLASH_OPTCR_nWRP_4             0x00100000U\n#define FLASH_OPTCR_nWRP_5             0x00200000U\n#define FLASH_OPTCR_nWRP_6             0x00400000U\n#define FLASH_OPTCR_nWRP_7             0x00800000U\n#define FLASH_OPTCR_nWRP_8             0x01000000U\n#define FLASH_OPTCR_nWRP_9             0x02000000U\n#define FLASH_OPTCR_nWRP_10            0x04000000U\n#define FLASH_OPTCR_nWRP_11            0x08000000U\n#define FLASH_OPTCR_DB1M_Pos           (30U)\n#define FLASH_OPTCR_DB1M_Msk           (0x1U << FLASH_OPTCR_DB1M_Pos)          /*!< 0x40000000 */\n#define FLASH_OPTCR_DB1M               FLASH_OPTCR_DB1M_Msk\n#define FLASH_OPTCR_SPRMOD_Pos         (31U)\n#define FLASH_OPTCR_SPRMOD_Msk         (0x1U << FLASH_OPTCR_SPRMOD_Pos)        /*!< 0x80000000 */\n#define FLASH_OPTCR_SPRMOD             FLASH_OPTCR_SPRMOD_Msk\n\n/******************  Bits definition for FLASH_OPTCR1 register  ***************/\n#define FLASH_OPTCR1_nWRP_Pos          (16U)\n#define FLASH_OPTCR1_nWRP_Msk          (0xFFFU << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */\n#define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk\n#define FLASH_OPTCR1_nWRP_0            (0x001U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */\n#define FLASH_OPTCR1_nWRP_1            (0x002U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */\n#define FLASH_OPTCR1_nWRP_2            (0x004U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */\n#define FLASH_OPTCR1_nWRP_3            (0x008U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */\n#define FLASH_OPTCR1_nWRP_4            (0x010U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */\n#define FLASH_OPTCR1_nWRP_5            (0x020U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */\n#define FLASH_OPTCR1_nWRP_6            (0x040U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */\n#define FLASH_OPTCR1_nWRP_7            (0x080U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */\n#define FLASH_OPTCR1_nWRP_8            (0x100U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */\n#define FLASH_OPTCR1_nWRP_9            (0x200U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */\n#define FLASH_OPTCR1_nWRP_10           (0x400U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */\n#define FLASH_OPTCR1_nWRP_11           (0x800U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          Flexible Memory Controller                        */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for FMC_BCR1 register  *******************/\n#define FMC_BCR1_MBKEN_Pos          (0U)\n#define FMC_BCR1_MBKEN_Msk          (0x1U << FMC_BCR1_MBKEN_Pos)               /*!< 0x00000001 */\n#define FMC_BCR1_MBKEN              FMC_BCR1_MBKEN_Msk                         /*!<Memory bank enable bit                 */\n#define FMC_BCR1_MUXEN_Pos          (1U)\n#define FMC_BCR1_MUXEN_Msk          (0x1U << FMC_BCR1_MUXEN_Pos)               /*!< 0x00000002 */\n#define FMC_BCR1_MUXEN              FMC_BCR1_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */\n\n#define FMC_BCR1_MTYP_Pos           (2U)\n#define FMC_BCR1_MTYP_Msk           (0x3U << FMC_BCR1_MTYP_Pos)                /*!< 0x0000000C */\n#define FMC_BCR1_MTYP               FMC_BCR1_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */\n#define FMC_BCR1_MTYP_0             (0x1U << FMC_BCR1_MTYP_Pos)                /*!< 0x00000004 */\n#define FMC_BCR1_MTYP_1             (0x2U << FMC_BCR1_MTYP_Pos)                /*!< 0x00000008 */\n\n#define FMC_BCR1_MWID_Pos           (4U)\n#define FMC_BCR1_MWID_Msk           (0x3U << FMC_BCR1_MWID_Pos)                /*!< 0x00000030 */\n#define FMC_BCR1_MWID               FMC_BCR1_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */\n#define FMC_BCR1_MWID_0             (0x1U << FMC_BCR1_MWID_Pos)                /*!< 0x00000010 */\n#define FMC_BCR1_MWID_1             (0x2U << FMC_BCR1_MWID_Pos)                /*!< 0x00000020 */\n\n#define FMC_BCR1_FACCEN_Pos         (6U)\n#define FMC_BCR1_FACCEN_Msk         (0x1U << FMC_BCR1_FACCEN_Pos)              /*!< 0x00000040 */\n#define FMC_BCR1_FACCEN             FMC_BCR1_FACCEN_Msk                        /*!<Flash access enable        */\n#define FMC_BCR1_BURSTEN_Pos        (8U)\n#define FMC_BCR1_BURSTEN_Msk        (0x1U << FMC_BCR1_BURSTEN_Pos)             /*!< 0x00000100 */\n#define FMC_BCR1_BURSTEN            FMC_BCR1_BURSTEN_Msk                       /*!<Burst enable bit           */\n#define FMC_BCR1_WAITPOL_Pos        (9U)\n#define FMC_BCR1_WAITPOL_Msk        (0x1U << FMC_BCR1_WAITPOL_Pos)             /*!< 0x00000200 */\n#define FMC_BCR1_WAITPOL            FMC_BCR1_WAITPOL_Msk                       /*!<Wait signal polarity bit   */\n#define FMC_BCR1_WAITCFG_Pos        (11U)\n#define FMC_BCR1_WAITCFG_Msk        (0x1U << FMC_BCR1_WAITCFG_Pos)             /*!< 0x00000800 */\n#define FMC_BCR1_WAITCFG            FMC_BCR1_WAITCFG_Msk                       /*!<Wait timing configuration  */\n#define FMC_BCR1_WREN_Pos           (12U)\n#define FMC_BCR1_WREN_Msk           (0x1U << FMC_BCR1_WREN_Pos)                /*!< 0x00001000 */\n#define FMC_BCR1_WREN               FMC_BCR1_WREN_Msk                          /*!<Write enable bit           */\n#define FMC_BCR1_WAITEN_Pos         (13U)\n#define FMC_BCR1_WAITEN_Msk         (0x1U << FMC_BCR1_WAITEN_Pos)              /*!< 0x00002000 */\n#define FMC_BCR1_WAITEN             FMC_BCR1_WAITEN_Msk                        /*!<Wait enable bit            */\n#define FMC_BCR1_EXTMOD_Pos         (14U)\n#define FMC_BCR1_EXTMOD_Msk         (0x1U << FMC_BCR1_EXTMOD_Pos)              /*!< 0x00004000 */\n#define FMC_BCR1_EXTMOD             FMC_BCR1_EXTMOD_Msk                        /*!<Extended mode enable       */\n#define FMC_BCR1_ASYNCWAIT_Pos      (15U)\n#define FMC_BCR1_ASYNCWAIT_Msk      (0x1U << FMC_BCR1_ASYNCWAIT_Pos)           /*!< 0x00008000 */\n#define FMC_BCR1_ASYNCWAIT          FMC_BCR1_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */\n#define FMC_BCR1_CPSIZE_Pos         (16U)\n#define FMC_BCR1_CPSIZE_Msk         (0x7U << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00070000 */\n#define FMC_BCR1_CPSIZE             FMC_BCR1_CPSIZE_Msk                        /*!<CRAM page size             */\n#define FMC_BCR1_CPSIZE_0           (0x1U << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00010000 */\n#define FMC_BCR1_CPSIZE_1           (0x2U << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00020000 */\n#define FMC_BCR1_CPSIZE_2           (0x4U << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00040000 */\n#define FMC_BCR1_CBURSTRW_Pos       (19U)\n#define FMC_BCR1_CBURSTRW_Msk       (0x1U << FMC_BCR1_CBURSTRW_Pos)            /*!< 0x00080000 */\n#define FMC_BCR1_CBURSTRW           FMC_BCR1_CBURSTRW_Msk                      /*!<Write burst enable         */\n#define FMC_BCR1_CCLKEN_Pos         (20U)\n#define FMC_BCR1_CCLKEN_Msk         (0x1U << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */\n#define FMC_BCR1_CCLKEN             FMC_BCR1_CCLKEN_Msk                        /*!<Continous clock enable     */\n#define FMC_BCR1_WFDIS_Pos          (21U)\n#define FMC_BCR1_WFDIS_Msk          (0x1U << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */\n#define FMC_BCR1_WFDIS              FMC_BCR1_WFDIS_Msk                         /*!<Write FIFO Disable         */\n\n/******************  Bit definition for FMC_BCR2 register  *******************/\n#define FMC_BCR2_MBKEN_Pos          (0U)\n#define FMC_BCR2_MBKEN_Msk          (0x1U << FMC_BCR2_MBKEN_Pos)               /*!< 0x00000001 */\n#define FMC_BCR2_MBKEN              FMC_BCR2_MBKEN_Msk                         /*!<Memory bank enable bit                 */\n#define FMC_BCR2_MUXEN_Pos          (1U)\n#define FMC_BCR2_MUXEN_Msk          (0x1U << FMC_BCR2_MUXEN_Pos)               /*!< 0x00000002 */\n#define FMC_BCR2_MUXEN              FMC_BCR2_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */\n\n#define FMC_BCR2_MTYP_Pos           (2U)\n#define FMC_BCR2_MTYP_Msk           (0x3U << FMC_BCR2_MTYP_Pos)                /*!< 0x0000000C */\n#define FMC_BCR2_MTYP               FMC_BCR2_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */\n#define FMC_BCR2_MTYP_0             (0x1U << FMC_BCR2_MTYP_Pos)                /*!< 0x00000004 */\n#define FMC_BCR2_MTYP_1             (0x2U << FMC_BCR2_MTYP_Pos)                /*!< 0x00000008 */\n\n#define FMC_BCR2_MWID_Pos           (4U)\n#define FMC_BCR2_MWID_Msk           (0x3U << FMC_BCR2_MWID_Pos)                /*!< 0x00000030 */\n#define FMC_BCR2_MWID               FMC_BCR2_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */\n#define FMC_BCR2_MWID_0             (0x1U << FMC_BCR2_MWID_Pos)                /*!< 0x00000010 */\n#define FMC_BCR2_MWID_1             (0x2U << FMC_BCR2_MWID_Pos)                /*!< 0x00000020 */\n\n#define FMC_BCR2_FACCEN_Pos         (6U)\n#define FMC_BCR2_FACCEN_Msk         (0x1U << FMC_BCR2_FACCEN_Pos)              /*!< 0x00000040 */\n#define FMC_BCR2_FACCEN             FMC_BCR2_FACCEN_Msk                        /*!<Flash access enable        */\n#define FMC_BCR2_BURSTEN_Pos        (8U)\n#define FMC_BCR2_BURSTEN_Msk        (0x1U << FMC_BCR2_BURSTEN_Pos)             /*!< 0x00000100 */\n#define FMC_BCR2_BURSTEN            FMC_BCR2_BURSTEN_Msk                       /*!<Burst enable bit           */\n#define FMC_BCR2_WAITPOL_Pos        (9U)\n#define FMC_BCR2_WAITPOL_Msk        (0x1U << FMC_BCR2_WAITPOL_Pos)             /*!< 0x00000200 */\n#define FMC_BCR2_WAITPOL            FMC_BCR2_WAITPOL_Msk                       /*!<Wait signal polarity bit   */\n#define FMC_BCR2_WAITCFG_Pos        (11U)\n#define FMC_BCR2_WAITCFG_Msk        (0x1U << FMC_BCR2_WAITCFG_Pos)             /*!< 0x00000800 */\n#define FMC_BCR2_WAITCFG            FMC_BCR2_WAITCFG_Msk                       /*!<Wait timing configuration  */\n#define FMC_BCR2_WREN_Pos           (12U)\n#define FMC_BCR2_WREN_Msk           (0x1U << FMC_BCR2_WREN_Pos)                /*!< 0x00001000 */\n#define FMC_BCR2_WREN               FMC_BCR2_WREN_Msk                          /*!<Write enable bit           */\n#define FMC_BCR2_WAITEN_Pos         (13U)\n#define FMC_BCR2_WAITEN_Msk         (0x1U << FMC_BCR2_WAITEN_Pos)              /*!< 0x00002000 */\n#define FMC_BCR2_WAITEN             FMC_BCR2_WAITEN_Msk                        /*!<Wait enable bit            */\n#define FMC_BCR2_EXTMOD_Pos         (14U)\n#define FMC_BCR2_EXTMOD_Msk         (0x1U << FMC_BCR2_EXTMOD_Pos)              /*!< 0x00004000 */\n#define FMC_BCR2_EXTMOD             FMC_BCR2_EXTMOD_Msk                        /*!<Extended mode enable       */\n#define FMC_BCR2_ASYNCWAIT_Pos      (15U)\n#define FMC_BCR2_ASYNCWAIT_Msk      (0x1U << FMC_BCR2_ASYNCWAIT_Pos)           /*!< 0x00008000 */\n#define FMC_BCR2_ASYNCWAIT          FMC_BCR2_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */\n#define FMC_BCR2_CBURSTRW_Pos       (19U)\n#define FMC_BCR2_CBURSTRW_Msk       (0x1U << FMC_BCR2_CBURSTRW_Pos)            /*!< 0x00080000 */\n#define FMC_BCR2_CBURSTRW           FMC_BCR2_CBURSTRW_Msk                      /*!<Write burst enable         */\n\n/******************  Bit definition for FMC_BCR3 register  *******************/\n#define FMC_BCR3_MBKEN_Pos          (0U)\n#define FMC_BCR3_MBKEN_Msk          (0x1U << FMC_BCR3_MBKEN_Pos)               /*!< 0x00000001 */\n#define FMC_BCR3_MBKEN              FMC_BCR3_MBKEN_Msk                         /*!<Memory bank enable bit                 */\n#define FMC_BCR3_MUXEN_Pos          (1U)\n#define FMC_BCR3_MUXEN_Msk          (0x1U << FMC_BCR3_MUXEN_Pos)               /*!< 0x00000002 */\n#define FMC_BCR3_MUXEN              FMC_BCR3_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */\n\n#define FMC_BCR3_MTYP_Pos           (2U)\n#define FMC_BCR3_MTYP_Msk           (0x3U << FMC_BCR3_MTYP_Pos)                /*!< 0x0000000C */\n#define FMC_BCR3_MTYP               FMC_BCR3_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */\n#define FMC_BCR3_MTYP_0             (0x1U << FMC_BCR3_MTYP_Pos)                /*!< 0x00000004 */\n#define FMC_BCR3_MTYP_1             (0x2U << FMC_BCR3_MTYP_Pos)                /*!< 0x00000008 */\n\n#define FMC_BCR3_MWID_Pos           (4U)\n#define FMC_BCR3_MWID_Msk           (0x3U << FMC_BCR3_MWID_Pos)                /*!< 0x00000030 */\n#define FMC_BCR3_MWID               FMC_BCR3_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */\n#define FMC_BCR3_MWID_0             (0x1U << FMC_BCR3_MWID_Pos)                /*!< 0x00000010 */\n#define FMC_BCR3_MWID_1             (0x2U << FMC_BCR3_MWID_Pos)                /*!< 0x00000020 */\n\n#define FMC_BCR3_FACCEN_Pos         (6U)\n#define FMC_BCR3_FACCEN_Msk         (0x1U << FMC_BCR3_FACCEN_Pos)              /*!< 0x00000040 */\n#define FMC_BCR3_FACCEN             FMC_BCR3_FACCEN_Msk                        /*!<Flash access enable        */\n#define FMC_BCR3_BURSTEN_Pos        (8U)\n#define FMC_BCR3_BURSTEN_Msk        (0x1U << FMC_BCR3_BURSTEN_Pos)             /*!< 0x00000100 */\n#define FMC_BCR3_BURSTEN            FMC_BCR3_BURSTEN_Msk                       /*!<Burst enable bit           */\n#define FMC_BCR3_WAITPOL_Pos        (9U)\n#define FMC_BCR3_WAITPOL_Msk        (0x1U << FMC_BCR3_WAITPOL_Pos)             /*!< 0x00000200 */\n#define FMC_BCR3_WAITPOL            FMC_BCR3_WAITPOL_Msk                       /*!<Wait signal polarity bit   */\n#define FMC_BCR3_WAITCFG_Pos        (11U)\n#define FMC_BCR3_WAITCFG_Msk        (0x1U << FMC_BCR3_WAITCFG_Pos)             /*!< 0x00000800 */\n#define FMC_BCR3_WAITCFG            FMC_BCR3_WAITCFG_Msk                       /*!<Wait timing configuration  */\n#define FMC_BCR3_WREN_Pos           (12U)\n#define FMC_BCR3_WREN_Msk           (0x1U << FMC_BCR3_WREN_Pos)                /*!< 0x00001000 */\n#define FMC_BCR3_WREN               FMC_BCR3_WREN_Msk                          /*!<Write enable bit           */\n#define FMC_BCR3_WAITEN_Pos         (13U)\n#define FMC_BCR3_WAITEN_Msk         (0x1U << FMC_BCR3_WAITEN_Pos)              /*!< 0x00002000 */\n#define FMC_BCR3_WAITEN             FMC_BCR3_WAITEN_Msk                        /*!<Wait enable bit            */\n#define FMC_BCR3_EXTMOD_Pos         (14U)\n#define FMC_BCR3_EXTMOD_Msk         (0x1U << FMC_BCR3_EXTMOD_Pos)              /*!< 0x00004000 */\n#define FMC_BCR3_EXTMOD             FMC_BCR3_EXTMOD_Msk                        /*!<Extended mode enable       */\n#define FMC_BCR3_ASYNCWAIT_Pos      (15U)\n#define FMC_BCR3_ASYNCWAIT_Msk      (0x1U << FMC_BCR3_ASYNCWAIT_Pos)           /*!< 0x00008000 */\n#define FMC_BCR3_ASYNCWAIT          FMC_BCR3_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */\n#define FMC_BCR3_CBURSTRW_Pos       (19U)\n#define FMC_BCR3_CBURSTRW_Msk       (0x1U << FMC_BCR3_CBURSTRW_Pos)            /*!< 0x00080000 */\n#define FMC_BCR3_CBURSTRW           FMC_BCR3_CBURSTRW_Msk                      /*!<Write burst enable         */\n\n/******************  Bit definition for FMC_BCR4 register  *******************/\n#define FMC_BCR4_MBKEN_Pos          (0U)\n#define FMC_BCR4_MBKEN_Msk          (0x1U << FMC_BCR4_MBKEN_Pos)               /*!< 0x00000001 */\n#define FMC_BCR4_MBKEN              FMC_BCR4_MBKEN_Msk                         /*!<Memory bank enable bit                 */\n#define FMC_BCR4_MUXEN_Pos          (1U)\n#define FMC_BCR4_MUXEN_Msk          (0x1U << FMC_BCR4_MUXEN_Pos)               /*!< 0x00000002 */\n#define FMC_BCR4_MUXEN              FMC_BCR4_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */\n\n#define FMC_BCR4_MTYP_Pos           (2U)\n#define FMC_BCR4_MTYP_Msk           (0x3U << FMC_BCR4_MTYP_Pos)                /*!< 0x0000000C */\n#define FMC_BCR4_MTYP               FMC_BCR4_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */\n#define FMC_BCR4_MTYP_0             (0x1U << FMC_BCR4_MTYP_Pos)                /*!< 0x00000004 */\n#define FMC_BCR4_MTYP_1             (0x2U << FMC_BCR4_MTYP_Pos)                /*!< 0x00000008 */\n\n#define FMC_BCR4_MWID_Pos           (4U)\n#define FMC_BCR4_MWID_Msk           (0x3U << FMC_BCR4_MWID_Pos)                /*!< 0x00000030 */\n#define FMC_BCR4_MWID               FMC_BCR4_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */\n#define FMC_BCR4_MWID_0             (0x1U << FMC_BCR4_MWID_Pos)                /*!< 0x00000010 */\n#define FMC_BCR4_MWID_1             (0x2U << FMC_BCR4_MWID_Pos)                /*!< 0x00000020 */\n\n#define FMC_BCR4_FACCEN_Pos         (6U)\n#define FMC_BCR4_FACCEN_Msk         (0x1U << FMC_BCR4_FACCEN_Pos)              /*!< 0x00000040 */\n#define FMC_BCR4_FACCEN             FMC_BCR4_FACCEN_Msk                        /*!<Flash access enable        */\n#define FMC_BCR4_BURSTEN_Pos        (8U)\n#define FMC_BCR4_BURSTEN_Msk        (0x1U << FMC_BCR4_BURSTEN_Pos)             /*!< 0x00000100 */\n#define FMC_BCR4_BURSTEN            FMC_BCR4_BURSTEN_Msk                       /*!<Burst enable bit           */\n#define FMC_BCR4_WAITPOL_Pos        (9U)\n#define FMC_BCR4_WAITPOL_Msk        (0x1U << FMC_BCR4_WAITPOL_Pos)             /*!< 0x00000200 */\n#define FMC_BCR4_WAITPOL            FMC_BCR4_WAITPOL_Msk                       /*!<Wait signal polarity bit   */\n#define FMC_BCR4_WAITCFG_Pos        (11U)\n#define FMC_BCR4_WAITCFG_Msk        (0x1U << FMC_BCR4_WAITCFG_Pos)             /*!< 0x00000800 */\n#define FMC_BCR4_WAITCFG            FMC_BCR4_WAITCFG_Msk                       /*!<Wait timing configuration  */\n#define FMC_BCR4_WREN_Pos           (12U)\n#define FMC_BCR4_WREN_Msk           (0x1U << FMC_BCR4_WREN_Pos)                /*!< 0x00001000 */\n#define FMC_BCR4_WREN               FMC_BCR4_WREN_Msk                          /*!<Write enable bit           */\n#define FMC_BCR4_WAITEN_Pos         (13U)\n#define FMC_BCR4_WAITEN_Msk         (0x1U << FMC_BCR4_WAITEN_Pos)              /*!< 0x00002000 */\n#define FMC_BCR4_WAITEN             FMC_BCR4_WAITEN_Msk                        /*!<Wait enable bit            */\n#define FMC_BCR4_EXTMOD_Pos         (14U)\n#define FMC_BCR4_EXTMOD_Msk         (0x1U << FMC_BCR4_EXTMOD_Pos)              /*!< 0x00004000 */\n#define FMC_BCR4_EXTMOD             FMC_BCR4_EXTMOD_Msk                        /*!<Extended mode enable       */\n#define FMC_BCR4_ASYNCWAIT_Pos      (15U)\n#define FMC_BCR4_ASYNCWAIT_Msk      (0x1U << FMC_BCR4_ASYNCWAIT_Pos)           /*!< 0x00008000 */\n#define FMC_BCR4_ASYNCWAIT          FMC_BCR4_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */\n#define FMC_BCR4_CBURSTRW_Pos       (19U)\n#define FMC_BCR4_CBURSTRW_Msk       (0x1U << FMC_BCR4_CBURSTRW_Pos)            /*!< 0x00080000 */\n#define FMC_BCR4_CBURSTRW           FMC_BCR4_CBURSTRW_Msk                      /*!<Write burst enable         */\n\n/******************  Bit definition for FMC_BTR1 register  ******************/\n#define FMC_BTR1_ADDSET_Pos         (0U)\n#define FMC_BTR1_ADDSET_Msk         (0xFU << FMC_BTR1_ADDSET_Pos)              /*!< 0x0000000F */\n#define FMC_BTR1_ADDSET             FMC_BTR1_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BTR1_ADDSET_0           (0x1U << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000001 */\n#define FMC_BTR1_ADDSET_1           (0x2U << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000002 */\n#define FMC_BTR1_ADDSET_2           (0x4U << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000004 */\n#define FMC_BTR1_ADDSET_3           (0x8U << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000008 */\n\n#define FMC_BTR1_ADDHLD_Pos         (4U)\n#define FMC_BTR1_ADDHLD_Msk         (0xFU << FMC_BTR1_ADDHLD_Pos)              /*!< 0x000000F0 */\n#define FMC_BTR1_ADDHLD             FMC_BTR1_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */\n#define FMC_BTR1_ADDHLD_0           (0x1U << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000010 */\n#define FMC_BTR1_ADDHLD_1           (0x2U << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000020 */\n#define FMC_BTR1_ADDHLD_2           (0x4U << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000040 */\n#define FMC_BTR1_ADDHLD_3           (0x8U << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000080 */\n\n#define FMC_BTR1_DATAST_Pos         (8U)\n#define FMC_BTR1_DATAST_Msk         (0xFFU << FMC_BTR1_DATAST_Pos)             /*!< 0x0000FF00 */\n#define FMC_BTR1_DATAST             FMC_BTR1_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BTR1_DATAST_0           (0x01U << FMC_BTR1_DATAST_Pos)             /*!< 0x00000100 */\n#define FMC_BTR1_DATAST_1           (0x02U << FMC_BTR1_DATAST_Pos)             /*!< 0x00000200 */\n#define FMC_BTR1_DATAST_2           (0x04U << FMC_BTR1_DATAST_Pos)             /*!< 0x00000400 */\n#define FMC_BTR1_DATAST_3           (0x08U << FMC_BTR1_DATAST_Pos)             /*!< 0x00000800 */\n#define FMC_BTR1_DATAST_4           (0x10U << FMC_BTR1_DATAST_Pos)             /*!< 0x00001000 */\n#define FMC_BTR1_DATAST_5           (0x20U << FMC_BTR1_DATAST_Pos)             /*!< 0x00002000 */\n#define FMC_BTR1_DATAST_6           (0x40U << FMC_BTR1_DATAST_Pos)             /*!< 0x00004000 */\n#define FMC_BTR1_DATAST_7           (0x80U << FMC_BTR1_DATAST_Pos)             /*!< 0x00008000 */\n\n#define FMC_BTR1_BUSTURN_Pos        (16U)\n#define FMC_BTR1_BUSTURN_Msk        (0xFU << FMC_BTR1_BUSTURN_Pos)             /*!< 0x000F0000 */\n#define FMC_BTR1_BUSTURN            FMC_BTR1_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FMC_BTR1_BUSTURN_0          (0x1U << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00010000 */\n#define FMC_BTR1_BUSTURN_1          (0x2U << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00020000 */\n#define FMC_BTR1_BUSTURN_2          (0x4U << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00040000 */\n#define FMC_BTR1_BUSTURN_3          (0x8U << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00080000 */\n\n#define FMC_BTR1_CLKDIV_Pos         (20U)\n#define FMC_BTR1_CLKDIV_Msk         (0xFU << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00F00000 */\n#define FMC_BTR1_CLKDIV             FMC_BTR1_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FMC_BTR1_CLKDIV_0           (0x1U << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00100000 */\n#define FMC_BTR1_CLKDIV_1           (0x2U << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00200000 */\n#define FMC_BTR1_CLKDIV_2           (0x4U << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00400000 */\n#define FMC_BTR1_CLKDIV_3           (0x8U << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00800000 */\n\n#define FMC_BTR1_DATLAT_Pos         (24U)\n#define FMC_BTR1_DATLAT_Msk         (0xFU << FMC_BTR1_DATLAT_Pos)              /*!< 0x0F000000 */\n#define FMC_BTR1_DATLAT             FMC_BTR1_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */\n#define FMC_BTR1_DATLAT_0           (0x1U << FMC_BTR1_DATLAT_Pos)              /*!< 0x01000000 */\n#define FMC_BTR1_DATLAT_1           (0x2U << FMC_BTR1_DATLAT_Pos)              /*!< 0x02000000 */\n#define FMC_BTR1_DATLAT_2           (0x4U << FMC_BTR1_DATLAT_Pos)              /*!< 0x04000000 */\n#define FMC_BTR1_DATLAT_3           (0x8U << FMC_BTR1_DATLAT_Pos)              /*!< 0x08000000 */\n\n#define FMC_BTR1_ACCMOD_Pos         (28U)\n#define FMC_BTR1_ACCMOD_Msk         (0x3U << FMC_BTR1_ACCMOD_Pos)              /*!< 0x30000000 */\n#define FMC_BTR1_ACCMOD             FMC_BTR1_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BTR1_ACCMOD_0           (0x1U << FMC_BTR1_ACCMOD_Pos)              /*!< 0x10000000 */\n#define FMC_BTR1_ACCMOD_1           (0x2U << FMC_BTR1_ACCMOD_Pos)              /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_BTR2 register  *******************/\n#define FMC_BTR2_ADDSET_Pos         (0U)\n#define FMC_BTR2_ADDSET_Msk         (0xFU << FMC_BTR2_ADDSET_Pos)              /*!< 0x0000000F */\n#define FMC_BTR2_ADDSET             FMC_BTR2_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BTR2_ADDSET_0           (0x1U << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000001 */\n#define FMC_BTR2_ADDSET_1           (0x2U << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000002 */\n#define FMC_BTR2_ADDSET_2           (0x4U << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000004 */\n#define FMC_BTR2_ADDSET_3           (0x8U << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000008 */\n\n#define FMC_BTR2_ADDHLD_Pos         (4U)\n#define FMC_BTR2_ADDHLD_Msk         (0xFU << FMC_BTR2_ADDHLD_Pos)              /*!< 0x000000F0 */\n#define FMC_BTR2_ADDHLD             FMC_BTR2_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BTR2_ADDHLD_0           (0x1U << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000010 */\n#define FMC_BTR2_ADDHLD_1           (0x2U << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000020 */\n#define FMC_BTR2_ADDHLD_2           (0x4U << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000040 */\n#define FMC_BTR2_ADDHLD_3           (0x8U << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000080 */\n\n#define FMC_BTR2_DATAST_Pos         (8U)\n#define FMC_BTR2_DATAST_Msk         (0xFFU << FMC_BTR2_DATAST_Pos)             /*!< 0x0000FF00 */\n#define FMC_BTR2_DATAST             FMC_BTR2_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BTR2_DATAST_0           (0x01U << FMC_BTR2_DATAST_Pos)             /*!< 0x00000100 */\n#define FMC_BTR2_DATAST_1           (0x02U << FMC_BTR2_DATAST_Pos)             /*!< 0x00000200 */\n#define FMC_BTR2_DATAST_2           (0x04U << FMC_BTR2_DATAST_Pos)             /*!< 0x00000400 */\n#define FMC_BTR2_DATAST_3           (0x08U << FMC_BTR2_DATAST_Pos)             /*!< 0x00000800 */\n#define FMC_BTR2_DATAST_4           (0x10U << FMC_BTR2_DATAST_Pos)             /*!< 0x00001000 */\n#define FMC_BTR2_DATAST_5           (0x20U << FMC_BTR2_DATAST_Pos)             /*!< 0x00002000 */\n#define FMC_BTR2_DATAST_6           (0x40U << FMC_BTR2_DATAST_Pos)             /*!< 0x00004000 */\n#define FMC_BTR2_DATAST_7           (0x80U << FMC_BTR2_DATAST_Pos)             /*!< 0x00008000 */\n\n#define FMC_BTR2_BUSTURN_Pos        (16U)\n#define FMC_BTR2_BUSTURN_Msk        (0xFU << FMC_BTR2_BUSTURN_Pos)             /*!< 0x000F0000 */\n#define FMC_BTR2_BUSTURN            FMC_BTR2_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FMC_BTR2_BUSTURN_0          (0x1U << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00010000 */\n#define FMC_BTR2_BUSTURN_1          (0x2U << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00020000 */\n#define FMC_BTR2_BUSTURN_2          (0x4U << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00040000 */\n#define FMC_BTR2_BUSTURN_3          (0x8U << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00080000 */\n\n#define FMC_BTR2_CLKDIV_Pos         (20U)\n#define FMC_BTR2_CLKDIV_Msk         (0xFU << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00F00000 */\n#define FMC_BTR2_CLKDIV             FMC_BTR2_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FMC_BTR2_CLKDIV_0           (0x1U << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00100000 */\n#define FMC_BTR2_CLKDIV_1           (0x2U << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00200000 */\n#define FMC_BTR2_CLKDIV_2           (0x4U << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00400000 */\n#define FMC_BTR2_CLKDIV_3           (0x8U << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00800000 */\n\n#define FMC_BTR2_DATLAT_Pos         (24U)\n#define FMC_BTR2_DATLAT_Msk         (0xFU << FMC_BTR2_DATLAT_Pos)              /*!< 0x0F000000 */\n#define FMC_BTR2_DATLAT             FMC_BTR2_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */\n#define FMC_BTR2_DATLAT_0           (0x1U << FMC_BTR2_DATLAT_Pos)              /*!< 0x01000000 */\n#define FMC_BTR2_DATLAT_1           (0x2U << FMC_BTR2_DATLAT_Pos)              /*!< 0x02000000 */\n#define FMC_BTR2_DATLAT_2           (0x4U << FMC_BTR2_DATLAT_Pos)              /*!< 0x04000000 */\n#define FMC_BTR2_DATLAT_3           (0x8U << FMC_BTR2_DATLAT_Pos)              /*!< 0x08000000 */\n\n#define FMC_BTR2_ACCMOD_Pos         (28U)\n#define FMC_BTR2_ACCMOD_Msk         (0x3U << FMC_BTR2_ACCMOD_Pos)              /*!< 0x30000000 */\n#define FMC_BTR2_ACCMOD             FMC_BTR2_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BTR2_ACCMOD_0           (0x1U << FMC_BTR2_ACCMOD_Pos)              /*!< 0x10000000 */\n#define FMC_BTR2_ACCMOD_1           (0x2U << FMC_BTR2_ACCMOD_Pos)              /*!< 0x20000000 */\n\n/*******************  Bit definition for FMC_BTR3 register  *******************/\n#define FMC_BTR3_ADDSET_Pos         (0U)\n#define FMC_BTR3_ADDSET_Msk         (0xFU << FMC_BTR3_ADDSET_Pos)              /*!< 0x0000000F */\n#define FMC_BTR3_ADDSET             FMC_BTR3_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BTR3_ADDSET_0           (0x1U << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000001 */\n#define FMC_BTR3_ADDSET_1           (0x2U << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000002 */\n#define FMC_BTR3_ADDSET_2           (0x4U << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000004 */\n#define FMC_BTR3_ADDSET_3           (0x8U << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000008 */\n\n#define FMC_BTR3_ADDHLD_Pos         (4U)\n#define FMC_BTR3_ADDHLD_Msk         (0xFU << FMC_BTR3_ADDHLD_Pos)              /*!< 0x000000F0 */\n#define FMC_BTR3_ADDHLD             FMC_BTR3_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BTR3_ADDHLD_0           (0x1U << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000010 */\n#define FMC_BTR3_ADDHLD_1           (0x2U << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000020 */\n#define FMC_BTR3_ADDHLD_2           (0x4U << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000040 */\n#define FMC_BTR3_ADDHLD_3           (0x8U << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000080 */\n\n#define FMC_BTR3_DATAST_Pos         (8U)\n#define FMC_BTR3_DATAST_Msk         (0xFFU << FMC_BTR3_DATAST_Pos)             /*!< 0x0000FF00 */\n#define FMC_BTR3_DATAST             FMC_BTR3_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BTR3_DATAST_0           (0x01U << FMC_BTR3_DATAST_Pos)             /*!< 0x00000100 */\n#define FMC_BTR3_DATAST_1           (0x02U << FMC_BTR3_DATAST_Pos)             /*!< 0x00000200 */\n#define FMC_BTR3_DATAST_2           (0x04U << FMC_BTR3_DATAST_Pos)             /*!< 0x00000400 */\n#define FMC_BTR3_DATAST_3           (0x08U << FMC_BTR3_DATAST_Pos)             /*!< 0x00000800 */\n#define FMC_BTR3_DATAST_4           (0x10U << FMC_BTR3_DATAST_Pos)             /*!< 0x00001000 */\n#define FMC_BTR3_DATAST_5           (0x20U << FMC_BTR3_DATAST_Pos)             /*!< 0x00002000 */\n#define FMC_BTR3_DATAST_6           (0x40U << FMC_BTR3_DATAST_Pos)             /*!< 0x00004000 */\n#define FMC_BTR3_DATAST_7           (0x80U << FMC_BTR3_DATAST_Pos)             /*!< 0x00008000 */\n\n#define FMC_BTR3_BUSTURN_Pos        (16U)\n#define FMC_BTR3_BUSTURN_Msk        (0xFU << FMC_BTR3_BUSTURN_Pos)             /*!< 0x000F0000 */\n#define FMC_BTR3_BUSTURN            FMC_BTR3_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FMC_BTR3_BUSTURN_0          (0x1U << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00010000 */\n#define FMC_BTR3_BUSTURN_1          (0x2U << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00020000 */\n#define FMC_BTR3_BUSTURN_2          (0x4U << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00040000 */\n#define FMC_BTR3_BUSTURN_3          (0x8U << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00080000 */\n\n#define FMC_BTR3_CLKDIV_Pos         (20U)\n#define FMC_BTR3_CLKDIV_Msk         (0xFU << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00F00000 */\n#define FMC_BTR3_CLKDIV             FMC_BTR3_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FMC_BTR3_CLKDIV_0           (0x1U << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00100000 */\n#define FMC_BTR3_CLKDIV_1           (0x2U << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00200000 */\n#define FMC_BTR3_CLKDIV_2           (0x4U << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00400000 */\n#define FMC_BTR3_CLKDIV_3           (0x8U << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00800000 */\n\n#define FMC_BTR3_DATLAT_Pos         (24U)\n#define FMC_BTR3_DATLAT_Msk         (0xFU << FMC_BTR3_DATLAT_Pos)              /*!< 0x0F000000 */\n#define FMC_BTR3_DATLAT             FMC_BTR3_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */\n#define FMC_BTR3_DATLAT_0           (0x1U << FMC_BTR3_DATLAT_Pos)              /*!< 0x01000000 */\n#define FMC_BTR3_DATLAT_1           (0x2U << FMC_BTR3_DATLAT_Pos)              /*!< 0x02000000 */\n#define FMC_BTR3_DATLAT_2           (0x4U << FMC_BTR3_DATLAT_Pos)              /*!< 0x04000000 */\n#define FMC_BTR3_DATLAT_3           (0x8U << FMC_BTR3_DATLAT_Pos)              /*!< 0x08000000 */\n\n#define FMC_BTR3_ACCMOD_Pos         (28U)\n#define FMC_BTR3_ACCMOD_Msk         (0x3U << FMC_BTR3_ACCMOD_Pos)              /*!< 0x30000000 */\n#define FMC_BTR3_ACCMOD             FMC_BTR3_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BTR3_ACCMOD_0           (0x1U << FMC_BTR3_ACCMOD_Pos)              /*!< 0x10000000 */\n#define FMC_BTR3_ACCMOD_1           (0x2U << FMC_BTR3_ACCMOD_Pos)              /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_BTR4 register  *******************/\n#define FMC_BTR4_ADDSET_Pos         (0U)\n#define FMC_BTR4_ADDSET_Msk         (0xFU << FMC_BTR4_ADDSET_Pos)              /*!< 0x0000000F */\n#define FMC_BTR4_ADDSET             FMC_BTR4_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BTR4_ADDSET_0           (0x1U << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000001 */\n#define FMC_BTR4_ADDSET_1           (0x2U << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000002 */\n#define FMC_BTR4_ADDSET_2           (0x4U << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000004 */\n#define FMC_BTR4_ADDSET_3           (0x8U << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000008 */\n\n#define FMC_BTR4_ADDHLD_Pos         (4U)\n#define FMC_BTR4_ADDHLD_Msk         (0xFU << FMC_BTR4_ADDHLD_Pos)              /*!< 0x000000F0 */\n#define FMC_BTR4_ADDHLD             FMC_BTR4_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BTR4_ADDHLD_0           (0x1U << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000010 */\n#define FMC_BTR4_ADDHLD_1           (0x2U << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000020 */\n#define FMC_BTR4_ADDHLD_2           (0x4U << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000040 */\n#define FMC_BTR4_ADDHLD_3           (0x8U << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000080 */\n\n#define FMC_BTR4_DATAST_Pos         (8U)\n#define FMC_BTR4_DATAST_Msk         (0xFFU << FMC_BTR4_DATAST_Pos)             /*!< 0x0000FF00 */\n#define FMC_BTR4_DATAST             FMC_BTR4_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BTR4_DATAST_0           (0x01U << FMC_BTR4_DATAST_Pos)             /*!< 0x00000100 */\n#define FMC_BTR4_DATAST_1           (0x02U << FMC_BTR4_DATAST_Pos)             /*!< 0x00000200 */\n#define FMC_BTR4_DATAST_2           (0x04U << FMC_BTR4_DATAST_Pos)             /*!< 0x00000400 */\n#define FMC_BTR4_DATAST_3           (0x08U << FMC_BTR4_DATAST_Pos)             /*!< 0x00000800 */\n#define FMC_BTR4_DATAST_4           (0x10U << FMC_BTR4_DATAST_Pos)             /*!< 0x00001000 */\n#define FMC_BTR4_DATAST_5           (0x20U << FMC_BTR4_DATAST_Pos)             /*!< 0x00002000 */\n#define FMC_BTR4_DATAST_6           (0x40U << FMC_BTR4_DATAST_Pos)             /*!< 0x00004000 */\n#define FMC_BTR4_DATAST_7           (0x80U << FMC_BTR4_DATAST_Pos)             /*!< 0x00008000 */\n\n#define FMC_BTR4_BUSTURN_Pos        (16U)\n#define FMC_BTR4_BUSTURN_Msk        (0xFU << FMC_BTR4_BUSTURN_Pos)             /*!< 0x000F0000 */\n#define FMC_BTR4_BUSTURN            FMC_BTR4_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FMC_BTR4_BUSTURN_0          (0x1U << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00010000 */\n#define FMC_BTR4_BUSTURN_1          (0x2U << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00020000 */\n#define FMC_BTR4_BUSTURN_2          (0x4U << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00040000 */\n#define FMC_BTR4_BUSTURN_3          (0x8U << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00080000 */\n\n#define FMC_BTR4_CLKDIV_Pos         (20U)\n#define FMC_BTR4_CLKDIV_Msk         (0xFU << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00F00000 */\n#define FMC_BTR4_CLKDIV             FMC_BTR4_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FMC_BTR4_CLKDIV_0           (0x1U << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00100000 */\n#define FMC_BTR4_CLKDIV_1           (0x2U << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00200000 */\n#define FMC_BTR4_CLKDIV_2           (0x4U << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00400000 */\n#define FMC_BTR4_CLKDIV_3           (0x8U << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00800000 */\n\n#define FMC_BTR4_DATLAT_Pos         (24U)\n#define FMC_BTR4_DATLAT_Msk         (0xFU << FMC_BTR4_DATLAT_Pos)              /*!< 0x0F000000 */\n#define FMC_BTR4_DATLAT             FMC_BTR4_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */\n#define FMC_BTR4_DATLAT_0           (0x1U << FMC_BTR4_DATLAT_Pos)              /*!< 0x01000000 */\n#define FMC_BTR4_DATLAT_1           (0x2U << FMC_BTR4_DATLAT_Pos)              /*!< 0x02000000 */\n#define FMC_BTR4_DATLAT_2           (0x4U << FMC_BTR4_DATLAT_Pos)              /*!< 0x04000000 */\n#define FMC_BTR4_DATLAT_3           (0x8U << FMC_BTR4_DATLAT_Pos)              /*!< 0x08000000 */\n\n#define FMC_BTR4_ACCMOD_Pos         (28U)\n#define FMC_BTR4_ACCMOD_Msk         (0x3U << FMC_BTR4_ACCMOD_Pos)              /*!< 0x30000000 */\n#define FMC_BTR4_ACCMOD             FMC_BTR4_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BTR4_ACCMOD_0           (0x1U << FMC_BTR4_ACCMOD_Pos)              /*!< 0x10000000 */\n#define FMC_BTR4_ACCMOD_1           (0x2U << FMC_BTR4_ACCMOD_Pos)              /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_BWTR1 register  ******************/\n#define FMC_BWTR1_ADDSET_Pos        (0U)\n#define FMC_BWTR1_ADDSET_Msk        (0xFU << FMC_BWTR1_ADDSET_Pos)             /*!< 0x0000000F */\n#define FMC_BWTR1_ADDSET            FMC_BWTR1_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BWTR1_ADDSET_0          (0x1U << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000001 */\n#define FMC_BWTR1_ADDSET_1          (0x2U << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000002 */\n#define FMC_BWTR1_ADDSET_2          (0x4U << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000004 */\n#define FMC_BWTR1_ADDSET_3          (0x8U << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000008 */\n\n#define FMC_BWTR1_ADDHLD_Pos        (4U)\n#define FMC_BWTR1_ADDHLD_Msk        (0xFU << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x000000F0 */\n#define FMC_BWTR1_ADDHLD            FMC_BWTR1_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BWTR1_ADDHLD_0          (0x1U << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000010 */\n#define FMC_BWTR1_ADDHLD_1          (0x2U << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000020 */\n#define FMC_BWTR1_ADDHLD_2          (0x4U << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000040 */\n#define FMC_BWTR1_ADDHLD_3          (0x8U << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000080 */\n\n#define FMC_BWTR1_DATAST_Pos        (8U)\n#define FMC_BWTR1_DATAST_Msk        (0xFFU << FMC_BWTR1_DATAST_Pos)            /*!< 0x0000FF00 */\n#define FMC_BWTR1_DATAST            FMC_BWTR1_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BWTR1_DATAST_0          (0x01U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000100 */\n#define FMC_BWTR1_DATAST_1          (0x02U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000200 */\n#define FMC_BWTR1_DATAST_2          (0x04U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000400 */\n#define FMC_BWTR1_DATAST_3          (0x08U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000800 */\n#define FMC_BWTR1_DATAST_4          (0x10U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00001000 */\n#define FMC_BWTR1_DATAST_5          (0x20U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00002000 */\n#define FMC_BWTR1_DATAST_6          (0x40U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00004000 */\n#define FMC_BWTR1_DATAST_7          (0x80U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00008000 */\n\n#define FMC_BWTR1_BUSTURN_Pos       (16U)\n#define FMC_BWTR1_BUSTURN_Msk       (0xFU << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x000F0000 */\n#define FMC_BWTR1_BUSTURN           FMC_BWTR1_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FMC_BWTR1_BUSTURN_0         (0x1U << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00010000 */\n#define FMC_BWTR1_BUSTURN_1         (0x2U << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00020000 */\n#define FMC_BWTR1_BUSTURN_2         (0x4U << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00040000 */\n#define FMC_BWTR1_BUSTURN_3         (0x8U << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00080000 */\n\n#define FMC_BWTR1_ACCMOD_Pos        (28U)\n#define FMC_BWTR1_ACCMOD_Msk        (0x3U << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x30000000 */\n#define FMC_BWTR1_ACCMOD            FMC_BWTR1_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BWTR1_ACCMOD_0          (0x1U << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x10000000 */\n#define FMC_BWTR1_ACCMOD_1          (0x2U << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_BWTR2 register  ******************/\n#define FMC_BWTR2_ADDSET_Pos        (0U)\n#define FMC_BWTR2_ADDSET_Msk        (0xFU << FMC_BWTR2_ADDSET_Pos)             /*!< 0x0000000F */\n#define FMC_BWTR2_ADDSET            FMC_BWTR2_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BWTR2_ADDSET_0          (0x1U << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000001 */\n#define FMC_BWTR2_ADDSET_1          (0x2U << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000002 */\n#define FMC_BWTR2_ADDSET_2          (0x4U << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000004 */\n#define FMC_BWTR2_ADDSET_3          (0x8U << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000008 */\n\n#define FMC_BWTR2_ADDHLD_Pos        (4U)\n#define FMC_BWTR2_ADDHLD_Msk        (0xFU << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x000000F0 */\n#define FMC_BWTR2_ADDHLD            FMC_BWTR2_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BWTR2_ADDHLD_0          (0x1U << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000010 */\n#define FMC_BWTR2_ADDHLD_1          (0x2U << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000020 */\n#define FMC_BWTR2_ADDHLD_2          (0x4U << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000040 */\n#define FMC_BWTR2_ADDHLD_3          (0x8U << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000080 */\n\n#define FMC_BWTR2_DATAST_Pos        (8U)\n#define FMC_BWTR2_DATAST_Msk        (0xFFU << FMC_BWTR2_DATAST_Pos)            /*!< 0x0000FF00 */\n#define FMC_BWTR2_DATAST            FMC_BWTR2_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BWTR2_DATAST_0          (0x01U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000100 */\n#define FMC_BWTR2_DATAST_1          (0x02U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000200 */\n#define FMC_BWTR2_DATAST_2          (0x04U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000400 */\n#define FMC_BWTR2_DATAST_3          (0x08U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000800 */\n#define FMC_BWTR2_DATAST_4          (0x10U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00001000 */\n#define FMC_BWTR2_DATAST_5          (0x20U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00002000 */\n#define FMC_BWTR2_DATAST_6          (0x40U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00004000 */\n#define FMC_BWTR2_DATAST_7          (0x80U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00008000 */\n\n#define FMC_BWTR2_BUSTURN_Pos       (16U)\n#define FMC_BWTR2_BUSTURN_Msk       (0xFU << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x000F0000 */\n#define FMC_BWTR2_BUSTURN           FMC_BWTR2_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FMC_BWTR2_BUSTURN_0         (0x1U << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00010000 */\n#define FMC_BWTR2_BUSTURN_1         (0x2U << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00020000 */\n#define FMC_BWTR2_BUSTURN_2         (0x4U << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00040000 */\n#define FMC_BWTR2_BUSTURN_3         (0x8U << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00080000 */\n\n#define FMC_BWTR2_ACCMOD_Pos        (28U)\n#define FMC_BWTR2_ACCMOD_Msk        (0x3U << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x30000000 */\n#define FMC_BWTR2_ACCMOD            FMC_BWTR2_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BWTR2_ACCMOD_0          (0x1U << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x10000000 */\n#define FMC_BWTR2_ACCMOD_1          (0x2U << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_BWTR3 register  ******************/\n#define FMC_BWTR3_ADDSET_Pos        (0U)\n#define FMC_BWTR3_ADDSET_Msk        (0xFU << FMC_BWTR3_ADDSET_Pos)             /*!< 0x0000000F */\n#define FMC_BWTR3_ADDSET            FMC_BWTR3_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BWTR3_ADDSET_0          (0x1U << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000001 */\n#define FMC_BWTR3_ADDSET_1          (0x2U << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000002 */\n#define FMC_BWTR3_ADDSET_2          (0x4U << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000004 */\n#define FMC_BWTR3_ADDSET_3          (0x8U << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000008 */\n\n#define FMC_BWTR3_ADDHLD_Pos        (4U)\n#define FMC_BWTR3_ADDHLD_Msk        (0xFU << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x000000F0 */\n#define FMC_BWTR3_ADDHLD            FMC_BWTR3_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BWTR3_ADDHLD_0          (0x1U << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000010 */\n#define FMC_BWTR3_ADDHLD_1          (0x2U << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000020 */\n#define FMC_BWTR3_ADDHLD_2          (0x4U << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000040 */\n#define FMC_BWTR3_ADDHLD_3          (0x8U << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000080 */\n\n#define FMC_BWTR3_DATAST_Pos        (8U)\n#define FMC_BWTR3_DATAST_Msk        (0xFFU << FMC_BWTR3_DATAST_Pos)            /*!< 0x0000FF00 */\n#define FMC_BWTR3_DATAST            FMC_BWTR3_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BWTR3_DATAST_0          (0x01U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000100 */\n#define FMC_BWTR3_DATAST_1          (0x02U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000200 */\n#define FMC_BWTR3_DATAST_2          (0x04U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000400 */\n#define FMC_BWTR3_DATAST_3          (0x08U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000800 */\n#define FMC_BWTR3_DATAST_4          (0x10U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00001000 */\n#define FMC_BWTR3_DATAST_5          (0x20U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00002000 */\n#define FMC_BWTR3_DATAST_6          (0x40U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00004000 */\n#define FMC_BWTR3_DATAST_7          (0x80U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00008000 */\n\n#define FMC_BWTR3_BUSTURN_Pos       (16U)\n#define FMC_BWTR3_BUSTURN_Msk       (0xFU << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x000F0000 */\n#define FMC_BWTR3_BUSTURN           FMC_BWTR3_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FMC_BWTR3_BUSTURN_0         (0x1U << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00010000 */\n#define FMC_BWTR3_BUSTURN_1         (0x2U << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00020000 */\n#define FMC_BWTR3_BUSTURN_2         (0x4U << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00040000 */\n#define FMC_BWTR3_BUSTURN_3         (0x8U << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00080000 */\n\n#define FMC_BWTR3_ACCMOD_Pos        (28U)\n#define FMC_BWTR3_ACCMOD_Msk        (0x3U << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x30000000 */\n#define FMC_BWTR3_ACCMOD            FMC_BWTR3_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BWTR3_ACCMOD_0          (0x1U << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x10000000 */\n#define FMC_BWTR3_ACCMOD_1          (0x2U << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_BWTR4 register  ******************/\n#define FMC_BWTR4_ADDSET_Pos        (0U)\n#define FMC_BWTR4_ADDSET_Msk        (0xFU << FMC_BWTR4_ADDSET_Pos)             /*!< 0x0000000F */\n#define FMC_BWTR4_ADDSET            FMC_BWTR4_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BWTR4_ADDSET_0          (0x1U << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000001 */\n#define FMC_BWTR4_ADDSET_1          (0x2U << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000002 */\n#define FMC_BWTR4_ADDSET_2          (0x4U << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000004 */\n#define FMC_BWTR4_ADDSET_3          (0x8U << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000008 */\n\n#define FMC_BWTR4_ADDHLD_Pos        (4U)\n#define FMC_BWTR4_ADDHLD_Msk        (0xFU << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x000000F0 */\n#define FMC_BWTR4_ADDHLD            FMC_BWTR4_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BWTR4_ADDHLD_0          (0x1U << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000010 */\n#define FMC_BWTR4_ADDHLD_1          (0x2U << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000020 */\n#define FMC_BWTR4_ADDHLD_2          (0x4U << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000040 */\n#define FMC_BWTR4_ADDHLD_3          (0x8U << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000080 */\n\n#define FMC_BWTR4_DATAST_Pos        (8U)\n#define FMC_BWTR4_DATAST_Msk        (0xFFU << FMC_BWTR4_DATAST_Pos)            /*!< 0x0000FF00 */\n#define FMC_BWTR4_DATAST            FMC_BWTR4_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BWTR4_DATAST_0          (0x01U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000100 */\n#define FMC_BWTR4_DATAST_1          (0x02U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000200 */\n#define FMC_BWTR4_DATAST_2          (0x04U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000400 */\n#define FMC_BWTR4_DATAST_3          (0x08U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000800 */\n#define FMC_BWTR4_DATAST_4          (0x10U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00001000 */\n#define FMC_BWTR4_DATAST_5          (0x20U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00002000 */\n#define FMC_BWTR4_DATAST_6          (0x40U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00004000 */\n#define FMC_BWTR4_DATAST_7          (0x80U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00008000 */\n\n#define FMC_BWTR4_BUSTURN_Pos       (16U)\n#define FMC_BWTR4_BUSTURN_Msk       (0xFU << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x000F0000 */\n#define FMC_BWTR4_BUSTURN           FMC_BWTR4_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FMC_BWTR4_BUSTURN_0         (0x1U << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00010000 */\n#define FMC_BWTR4_BUSTURN_1         (0x2U << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00020000 */\n#define FMC_BWTR4_BUSTURN_2         (0x4U << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00040000 */\n#define FMC_BWTR4_BUSTURN_3         (0x8U << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00080000 */\n\n#define FMC_BWTR4_ACCMOD_Pos        (28U)\n#define FMC_BWTR4_ACCMOD_Msk        (0x3U << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x30000000 */\n#define FMC_BWTR4_ACCMOD            FMC_BWTR4_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BWTR4_ACCMOD_0          (0x1U << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x10000000 */\n#define FMC_BWTR4_ACCMOD_1          (0x2U << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_PCR register  *******************/\n#define FMC_PCR_PWAITEN_Pos         (1U)\n#define FMC_PCR_PWAITEN_Msk         (0x1U << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */\n#define FMC_PCR_PWAITEN             FMC_PCR_PWAITEN_Msk                        /*!<Wait feature enable bit                   */\n#define FMC_PCR_PBKEN_Pos           (2U)\n#define FMC_PCR_PBKEN_Msk           (0x1U << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */\n#define FMC_PCR_PBKEN               FMC_PCR_PBKEN_Msk                          /*!<PC Card/NAND Flash memory bank enable bit */\n#define FMC_PCR_PTYP_Pos            (3U)\n#define FMC_PCR_PTYP_Msk            (0x1U << FMC_PCR_PTYP_Pos)                 /*!< 0x00000008 */\n#define FMC_PCR_PTYP                FMC_PCR_PTYP_Msk                           /*!<Memory type                               */\n\n#define FMC_PCR_PWID_Pos            (4U)\n#define FMC_PCR_PWID_Msk            (0x3U << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */\n#define FMC_PCR_PWID                FMC_PCR_PWID_Msk                           /*!<PWID[1:0] bits (NAND Flash databus width) */\n#define FMC_PCR_PWID_0              (0x1U << FMC_PCR_PWID_Pos)                 /*!< 0x00000010 */\n#define FMC_PCR_PWID_1              (0x2U << FMC_PCR_PWID_Pos)                 /*!< 0x00000020 */\n\n#define FMC_PCR_ECCEN_Pos           (6U)\n#define FMC_PCR_ECCEN_Msk           (0x1U << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */\n#define FMC_PCR_ECCEN               FMC_PCR_ECCEN_Msk                          /*!<ECC computation logic enable bit          */\n\n#define FMC_PCR_TCLR_Pos            (9U)\n#define FMC_PCR_TCLR_Msk            (0xFU << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */\n#define FMC_PCR_TCLR                FMC_PCR_TCLR_Msk                           /*!<TCLR[3:0] bits (CLE to RE delay)          */\n#define FMC_PCR_TCLR_0              (0x1U << FMC_PCR_TCLR_Pos)                 /*!< 0x00000200 */\n#define FMC_PCR_TCLR_1              (0x2U << FMC_PCR_TCLR_Pos)                 /*!< 0x00000400 */\n#define FMC_PCR_TCLR_2              (0x4U << FMC_PCR_TCLR_Pos)                 /*!< 0x00000800 */\n#define FMC_PCR_TCLR_3              (0x8U << FMC_PCR_TCLR_Pos)                 /*!< 0x00001000 */\n\n#define FMC_PCR_TAR_Pos             (13U)\n#define FMC_PCR_TAR_Msk             (0xFU << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */\n#define FMC_PCR_TAR                 FMC_PCR_TAR_Msk                            /*!<TAR[3:0] bits (ALE to RE delay)           */\n#define FMC_PCR_TAR_0               (0x1U << FMC_PCR_TAR_Pos)                  /*!< 0x00002000 */\n#define FMC_PCR_TAR_1               (0x2U << FMC_PCR_TAR_Pos)                  /*!< 0x00004000 */\n#define FMC_PCR_TAR_2               (0x4U << FMC_PCR_TAR_Pos)                  /*!< 0x00008000 */\n#define FMC_PCR_TAR_3               (0x8U << FMC_PCR_TAR_Pos)                  /*!< 0x00010000 */\n\n#define FMC_PCR_ECCPS_Pos           (17U)\n#define FMC_PCR_ECCPS_Msk           (0x7U << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */\n#define FMC_PCR_ECCPS               FMC_PCR_ECCPS_Msk                          /*!<ECCPS[1:0] bits (ECC page size)           */\n#define FMC_PCR_ECCPS_0             (0x1U << FMC_PCR_ECCPS_Pos)                /*!< 0x00020000 */\n#define FMC_PCR_ECCPS_1             (0x2U << FMC_PCR_ECCPS_Pos)                /*!< 0x00040000 */\n#define FMC_PCR_ECCPS_2             (0x4U << FMC_PCR_ECCPS_Pos)                /*!< 0x00080000 */\n\n/*******************  Bit definition for FMC_SR register  *******************/\n#define FMC_SR_IRS_Pos              (0U)\n#define FMC_SR_IRS_Msk              (0x1U << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */\n#define FMC_SR_IRS                  FMC_SR_IRS_Msk                             /*!<Interrupt Rising Edge status                */\n#define FMC_SR_ILS_Pos              (1U)\n#define FMC_SR_ILS_Msk              (0x1U << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */\n#define FMC_SR_ILS                  FMC_SR_ILS_Msk                             /*!<Interrupt Level status                      */\n#define FMC_SR_IFS_Pos              (2U)\n#define FMC_SR_IFS_Msk              (0x1U << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */\n#define FMC_SR_IFS                  FMC_SR_IFS_Msk                             /*!<Interrupt Falling Edge status               */\n#define FMC_SR_IREN_Pos             (3U)\n#define FMC_SR_IREN_Msk             (0x1U << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */\n#define FMC_SR_IREN                 FMC_SR_IREN_Msk                            /*!<Interrupt Rising Edge detection Enable bit  */\n#define FMC_SR_ILEN_Pos             (4U)\n#define FMC_SR_ILEN_Msk             (0x1U << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */\n#define FMC_SR_ILEN                 FMC_SR_ILEN_Msk                            /*!<Interrupt Level detection Enable bit        */\n#define FMC_SR_IFEN_Pos             (5U)\n#define FMC_SR_IFEN_Msk             (0x1U << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */\n#define FMC_SR_IFEN                 FMC_SR_IFEN_Msk                            /*!<Interrupt Falling Edge detection Enable bit */\n#define FMC_SR_FEMPT_Pos            (6U)\n#define FMC_SR_FEMPT_Msk            (0x1U << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */\n#define FMC_SR_FEMPT                FMC_SR_FEMPT_Msk                           /*!<FIFO empty                                  */\n\n/******************  Bit definition for FMC_PMEM register  ******************/\n#define FMC_PMEM_MEMSET2_Pos        (0U)\n#define FMC_PMEM_MEMSET2_Msk        (0xFFU << FMC_PMEM_MEMSET2_Pos)            /*!< 0x000000FF */\n#define FMC_PMEM_MEMSET2            FMC_PMEM_MEMSET2_Msk                       /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */\n#define FMC_PMEM_MEMSET2_0          (0x01U << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000001 */\n#define FMC_PMEM_MEMSET2_1          (0x02U << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000002 */\n#define FMC_PMEM_MEMSET2_2          (0x04U << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000004 */\n#define FMC_PMEM_MEMSET2_3          (0x08U << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000008 */\n#define FMC_PMEM_MEMSET2_4          (0x10U << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000010 */\n#define FMC_PMEM_MEMSET2_5          (0x20U << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000020 */\n#define FMC_PMEM_MEMSET2_6          (0x40U << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000040 */\n#define FMC_PMEM_MEMSET2_7          (0x80U << FMC_PMEM_MEMSET2_Pos)            /*!< 0x00000080 */\n\n#define FMC_PMEM_MEMWAIT2_Pos       (8U)\n#define FMC_PMEM_MEMWAIT2_Msk       (0xFFU << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x0000FF00 */\n#define FMC_PMEM_MEMWAIT2           FMC_PMEM_MEMWAIT2_Msk                      /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */\n#define FMC_PMEM_MEMWAIT2_0         (0x01U << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00000100 */\n#define FMC_PMEM_MEMWAIT2_1         (0x02U << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00000200 */\n#define FMC_PMEM_MEMWAIT2_2         (0x04U << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00000400 */\n#define FMC_PMEM_MEMWAIT2_3         (0x08U << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00000800 */\n#define FMC_PMEM_MEMWAIT2_4         (0x10U << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00001000 */\n#define FMC_PMEM_MEMWAIT2_5         (0x20U << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00002000 */\n#define FMC_PMEM_MEMWAIT2_6         (0x40U << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00004000 */\n#define FMC_PMEM_MEMWAIT2_7         (0x80U << FMC_PMEM_MEMWAIT2_Pos)           /*!< 0x00008000 */\n\n#define FMC_PMEM_MEMHOLD2_Pos       (16U)\n#define FMC_PMEM_MEMHOLD2_Msk       (0xFFU << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00FF0000 */\n#define FMC_PMEM_MEMHOLD2           FMC_PMEM_MEMHOLD2_Msk                      /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */\n#define FMC_PMEM_MEMHOLD2_0         (0x01U << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00010000 */\n#define FMC_PMEM_MEMHOLD2_1         (0x02U << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00020000 */\n#define FMC_PMEM_MEMHOLD2_2         (0x04U << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00040000 */\n#define FMC_PMEM_MEMHOLD2_3         (0x08U << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00080000 */\n#define FMC_PMEM_MEMHOLD2_4         (0x10U << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00100000 */\n#define FMC_PMEM_MEMHOLD2_5         (0x20U << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00200000 */\n#define FMC_PMEM_MEMHOLD2_6         (0x40U << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00400000 */\n#define FMC_PMEM_MEMHOLD2_7         (0x80U << FMC_PMEM_MEMHOLD2_Pos)           /*!< 0x00800000 */\n\n#define FMC_PMEM_MEMHIZ2_Pos        (24U)\n#define FMC_PMEM_MEMHIZ2_Msk        (0xFFU << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0xFF000000 */\n#define FMC_PMEM_MEMHIZ2            FMC_PMEM_MEMHIZ2_Msk                       /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */\n#define FMC_PMEM_MEMHIZ2_0          (0x01U << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x01000000 */\n#define FMC_PMEM_MEMHIZ2_1          (0x02U << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x02000000 */\n#define FMC_PMEM_MEMHIZ2_2          (0x04U << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x04000000 */\n#define FMC_PMEM_MEMHIZ2_3          (0x08U << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x08000000 */\n#define FMC_PMEM_MEMHIZ2_4          (0x10U << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x10000000 */\n#define FMC_PMEM_MEMHIZ2_5          (0x20U << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x20000000 */\n#define FMC_PMEM_MEMHIZ2_6          (0x40U << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x40000000 */\n#define FMC_PMEM_MEMHIZ2_7          (0x80U << FMC_PMEM_MEMHIZ2_Pos)            /*!< 0x80000000 */\n\n/******************  Bit definition for FMC_PATT register  ******************/\n#define FMC_PATT_ATTSET2_Pos        (0U)\n#define FMC_PATT_ATTSET2_Msk        (0xFFU << FMC_PATT_ATTSET2_Pos)            /*!< 0x000000FF */\n#define FMC_PATT_ATTSET2            FMC_PATT_ATTSET2_Msk                       /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */\n#define FMC_PATT_ATTSET2_0          (0x01U << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000001 */\n#define FMC_PATT_ATTSET2_1          (0x02U << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000002 */\n#define FMC_PATT_ATTSET2_2          (0x04U << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000004 */\n#define FMC_PATT_ATTSET2_3          (0x08U << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000008 */\n#define FMC_PATT_ATTSET2_4          (0x10U << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000010 */\n#define FMC_PATT_ATTSET2_5          (0x20U << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000020 */\n#define FMC_PATT_ATTSET2_6          (0x40U << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000040 */\n#define FMC_PATT_ATTSET2_7          (0x80U << FMC_PATT_ATTSET2_Pos)            /*!< 0x00000080 */\n\n#define FMC_PATT_ATTWAIT2_Pos       (8U)\n#define FMC_PATT_ATTWAIT2_Msk       (0xFFU << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x0000FF00 */\n#define FMC_PATT_ATTWAIT2           FMC_PATT_ATTWAIT2_Msk                      /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */\n#define FMC_PATT_ATTWAIT2_0         (0x01U << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00000100 */\n#define FMC_PATT_ATTWAIT2_1         (0x02U << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00000200 */\n#define FMC_PATT_ATTWAIT2_2         (0x04U << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00000400 */\n#define FMC_PATT_ATTWAIT2_3         (0x08U << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00000800 */\n#define FMC_PATT_ATTWAIT2_4         (0x10U << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00001000 */\n#define FMC_PATT_ATTWAIT2_5         (0x20U << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00002000 */\n#define FMC_PATT_ATTWAIT2_6         (0x40U << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00004000 */\n#define FMC_PATT_ATTWAIT2_7         (0x80U << FMC_PATT_ATTWAIT2_Pos)           /*!< 0x00008000 */\n\n#define FMC_PATT_ATTHOLD2_Pos       (16U)\n#define FMC_PATT_ATTHOLD2_Msk       (0xFFU << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00FF0000 */\n#define FMC_PATT_ATTHOLD2           FMC_PATT_ATTHOLD2_Msk                      /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */\n#define FMC_PATT_ATTHOLD2_0         (0x01U << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00010000 */\n#define FMC_PATT_ATTHOLD2_1         (0x02U << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00020000 */\n#define FMC_PATT_ATTHOLD2_2         (0x04U << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00040000 */\n#define FMC_PATT_ATTHOLD2_3         (0x08U << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00080000 */\n#define FMC_PATT_ATTHOLD2_4         (0x10U << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00100000 */\n#define FMC_PATT_ATTHOLD2_5         (0x20U << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00200000 */\n#define FMC_PATT_ATTHOLD2_6         (0x40U << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00400000 */\n#define FMC_PATT_ATTHOLD2_7         (0x80U << FMC_PATT_ATTHOLD2_Pos)           /*!< 0x00800000 */\n\n#define FMC_PATT_ATTHIZ2_Pos        (24U)\n#define FMC_PATT_ATTHIZ2_Msk        (0xFFU << FMC_PATT_ATTHIZ2_Pos)            /*!< 0xFF000000 */\n#define FMC_PATT_ATTHIZ2            FMC_PATT_ATTHIZ2_Msk                       /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */\n#define FMC_PATT_ATTHIZ2_0          (0x01U << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x01000000 */\n#define FMC_PATT_ATTHIZ2_1          (0x02U << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x02000000 */\n#define FMC_PATT_ATTHIZ2_2          (0x04U << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x04000000 */\n#define FMC_PATT_ATTHIZ2_3          (0x08U << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x08000000 */\n#define FMC_PATT_ATTHIZ2_4          (0x10U << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x10000000 */\n#define FMC_PATT_ATTHIZ2_5          (0x20U << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x20000000 */\n#define FMC_PATT_ATTHIZ2_6          (0x40U << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x40000000 */\n#define FMC_PATT_ATTHIZ2_7          (0x80U << FMC_PATT_ATTHIZ2_Pos)            /*!< 0x80000000 */\n\n/******************  Bit definition for FMC_ECCR register  ******************/\n#define FMC_ECCR_ECC2_Pos           (0U)\n#define FMC_ECCR_ECC2_Msk           (0xFFFFFFFFU << FMC_ECCR_ECC2_Pos)         /*!< 0xFFFFFFFF */\n#define FMC_ECCR_ECC2               FMC_ECCR_ECC2_Msk                          /*!<ECC result */\n\n/******************  Bit definition for FMC_SDCR1 register  ******************/\n#define FMC_SDCR1_NC_Pos            (0U)\n#define FMC_SDCR1_NC_Msk            (0x3U << FMC_SDCR1_NC_Pos)                 /*!< 0x00000003 */\n#define FMC_SDCR1_NC                FMC_SDCR1_NC_Msk                           /*!<NC[1:0] bits (Number of column bits) */\n#define FMC_SDCR1_NC_0              (0x1U << FMC_SDCR1_NC_Pos)                 /*!< 0x00000001 */\n#define FMC_SDCR1_NC_1              (0x2U << FMC_SDCR1_NC_Pos)                 /*!< 0x00000002 */\n\n#define FMC_SDCR1_NR_Pos            (2U)\n#define FMC_SDCR1_NR_Msk            (0x3U << FMC_SDCR1_NR_Pos)                 /*!< 0x0000000C */\n#define FMC_SDCR1_NR                FMC_SDCR1_NR_Msk                           /*!<NR[1:0] bits (Number of row bits) */\n#define FMC_SDCR1_NR_0              (0x1U << FMC_SDCR1_NR_Pos)                 /*!< 0x00000004 */\n#define FMC_SDCR1_NR_1              (0x2U << FMC_SDCR1_NR_Pos)                 /*!< 0x00000008 */\n\n#define FMC_SDCR1_MWID_Pos          (4U)\n#define FMC_SDCR1_MWID_Msk          (0x3U << FMC_SDCR1_MWID_Pos)               /*!< 0x00000030 */\n#define FMC_SDCR1_MWID              FMC_SDCR1_MWID_Msk                         /*!<NR[1:0] bits (Number of row bits) */\n#define FMC_SDCR1_MWID_0            (0x1U << FMC_SDCR1_MWID_Pos)               /*!< 0x00000010 */\n#define FMC_SDCR1_MWID_1            (0x2U << FMC_SDCR1_MWID_Pos)               /*!< 0x00000020 */\n\n#define FMC_SDCR1_NB_Pos            (6U)\n#define FMC_SDCR1_NB_Msk            (0x1U << FMC_SDCR1_NB_Pos)                 /*!< 0x00000040 */\n#define FMC_SDCR1_NB                FMC_SDCR1_NB_Msk                           /*!<Number of internal bank */\n\n#define FMC_SDCR1_CAS_Pos           (7U)\n#define FMC_SDCR1_CAS_Msk           (0x3U << FMC_SDCR1_CAS_Pos)                /*!< 0x00000180 */\n#define FMC_SDCR1_CAS               FMC_SDCR1_CAS_Msk                          /*!<CAS[1:0] bits (CAS latency) */\n#define FMC_SDCR1_CAS_0             (0x1U << FMC_SDCR1_CAS_Pos)                /*!< 0x00000080 */\n#define FMC_SDCR1_CAS_1             (0x2U << FMC_SDCR1_CAS_Pos)                /*!< 0x00000100 */\n\n#define FMC_SDCR1_WP_Pos            (9U)\n#define FMC_SDCR1_WP_Msk            (0x1U << FMC_SDCR1_WP_Pos)                 /*!< 0x00000200 */\n#define FMC_SDCR1_WP                FMC_SDCR1_WP_Msk                           /*!<Write protection */\n\n#define FMC_SDCR1_SDCLK_Pos         (10U)\n#define FMC_SDCR1_SDCLK_Msk         (0x3U << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000C00 */\n#define FMC_SDCR1_SDCLK             FMC_SDCR1_SDCLK_Msk                        /*!<SDRAM clock configuration */\n#define FMC_SDCR1_SDCLK_0           (0x1U << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000400 */\n#define FMC_SDCR1_SDCLK_1           (0x2U << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000800 */\n\n#define FMC_SDCR1_RBURST_Pos        (12U)\n#define FMC_SDCR1_RBURST_Msk        (0x1U << FMC_SDCR1_RBURST_Pos)             /*!< 0x00001000 */\n#define FMC_SDCR1_RBURST            FMC_SDCR1_RBURST_Msk                       /*!<Read burst */\n\n#define FMC_SDCR1_RPIPE_Pos         (13U)\n#define FMC_SDCR1_RPIPE_Msk         (0x3U << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00006000 */\n#define FMC_SDCR1_RPIPE             FMC_SDCR1_RPIPE_Msk                        /*!<Write protection */\n#define FMC_SDCR1_RPIPE_0           (0x1U << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00002000 */\n#define FMC_SDCR1_RPIPE_1           (0x2U << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00004000 */\n\n/******************  Bit definition for FMC_SDCR2 register  ******************/\n#define FMC_SDCR2_NC_Pos            (0U)\n#define FMC_SDCR2_NC_Msk            (0x3U << FMC_SDCR2_NC_Pos)                 /*!< 0x00000003 */\n#define FMC_SDCR2_NC                FMC_SDCR2_NC_Msk                           /*!<NC[1:0] bits (Number of column bits) */\n#define FMC_SDCR2_NC_0              (0x1U << FMC_SDCR2_NC_Pos)                 /*!< 0x00000001 */\n#define FMC_SDCR2_NC_1              (0x2U << FMC_SDCR2_NC_Pos)                 /*!< 0x00000002 */\n\n#define FMC_SDCR2_NR_Pos            (2U)\n#define FMC_SDCR2_NR_Msk            (0x3U << FMC_SDCR2_NR_Pos)                 /*!< 0x0000000C */\n#define FMC_SDCR2_NR                FMC_SDCR2_NR_Msk                           /*!<NR[1:0] bits (Number of row bits) */\n#define FMC_SDCR2_NR_0              (0x1U << FMC_SDCR2_NR_Pos)                 /*!< 0x00000004 */\n#define FMC_SDCR2_NR_1              (0x2U << FMC_SDCR2_NR_Pos)                 /*!< 0x00000008 */\n\n#define FMC_SDCR2_MWID_Pos          (4U)\n#define FMC_SDCR2_MWID_Msk          (0x3U << FMC_SDCR2_MWID_Pos)               /*!< 0x00000030 */\n#define FMC_SDCR2_MWID              FMC_SDCR2_MWID_Msk                         /*!<NR[1:0] bits (Number of row bits) */\n#define FMC_SDCR2_MWID_0            (0x1U << FMC_SDCR2_MWID_Pos)               /*!< 0x00000010 */\n#define FMC_SDCR2_MWID_1            (0x2U << FMC_SDCR2_MWID_Pos)               /*!< 0x00000020 */\n\n#define FMC_SDCR2_NB_Pos            (6U)\n#define FMC_SDCR2_NB_Msk            (0x1U << FMC_SDCR2_NB_Pos)                 /*!< 0x00000040 */\n#define FMC_SDCR2_NB                FMC_SDCR2_NB_Msk                           /*!<Number of internal bank */\n\n#define FMC_SDCR2_CAS_Pos           (7U)\n#define FMC_SDCR2_CAS_Msk           (0x3U << FMC_SDCR2_CAS_Pos)                /*!< 0x00000180 */\n#define FMC_SDCR2_CAS               FMC_SDCR2_CAS_Msk                          /*!<CAS[1:0] bits (CAS latency) */\n#define FMC_SDCR2_CAS_0             (0x1U << FMC_SDCR2_CAS_Pos)                /*!< 0x00000080 */\n#define FMC_SDCR2_CAS_1             (0x2U << FMC_SDCR2_CAS_Pos)                /*!< 0x00000100 */\n\n#define FMC_SDCR2_WP_Pos            (9U)\n#define FMC_SDCR2_WP_Msk            (0x1U << FMC_SDCR2_WP_Pos)                 /*!< 0x00000200 */\n#define FMC_SDCR2_WP                FMC_SDCR2_WP_Msk                           /*!<Write protection */\n\n#define FMC_SDCR2_SDCLK_Pos         (10U)\n#define FMC_SDCR2_SDCLK_Msk         (0x3U << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000C00 */\n#define FMC_SDCR2_SDCLK             FMC_SDCR2_SDCLK_Msk                        /*!<SDCLK[1:0] (SDRAM clock configuration) */\n#define FMC_SDCR2_SDCLK_0           (0x1U << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000400 */\n#define FMC_SDCR2_SDCLK_1           (0x2U << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000800 */\n\n#define FMC_SDCR2_RBURST_Pos        (12U)\n#define FMC_SDCR2_RBURST_Msk        (0x1U << FMC_SDCR2_RBURST_Pos)             /*!< 0x00001000 */\n#define FMC_SDCR2_RBURST            FMC_SDCR2_RBURST_Msk                       /*!<Read burst */\n\n#define FMC_SDCR2_RPIPE_Pos         (13U)\n#define FMC_SDCR2_RPIPE_Msk         (0x3U << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00006000 */\n#define FMC_SDCR2_RPIPE             FMC_SDCR2_RPIPE_Msk                        /*!<RPIPE[1:0](Read pipe) */\n#define FMC_SDCR2_RPIPE_0           (0x1U << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00002000 */\n#define FMC_SDCR2_RPIPE_1           (0x2U << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00004000 */\n\n/******************  Bit definition for FMC_SDTR1 register  ******************/\n#define FMC_SDTR1_TMRD_Pos          (0U)\n#define FMC_SDTR1_TMRD_Msk          (0xFU << FMC_SDTR1_TMRD_Pos)               /*!< 0x0000000F */\n#define FMC_SDTR1_TMRD              FMC_SDTR1_TMRD_Msk                         /*!<TMRD[3:0] bits (Load mode register to active) */\n#define FMC_SDTR1_TMRD_0            (0x1U << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000001 */\n#define FMC_SDTR1_TMRD_1            (0x2U << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000002 */\n#define FMC_SDTR1_TMRD_2            (0x4U << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000004 */\n#define FMC_SDTR1_TMRD_3            (0x8U << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000008 */\n\n#define FMC_SDTR1_TXSR_Pos          (4U)\n#define FMC_SDTR1_TXSR_Msk          (0xFU << FMC_SDTR1_TXSR_Pos)               /*!< 0x000000F0 */\n#define FMC_SDTR1_TXSR              FMC_SDTR1_TXSR_Msk                         /*!<TXSR[3:0] bits (Exit self refresh) */\n#define FMC_SDTR1_TXSR_0            (0x1U << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000010 */\n#define FMC_SDTR1_TXSR_1            (0x2U << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000020 */\n#define FMC_SDTR1_TXSR_2            (0x4U << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000040 */\n#define FMC_SDTR1_TXSR_3            (0x8U << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000080 */\n\n#define FMC_SDTR1_TRAS_Pos          (8U)\n#define FMC_SDTR1_TRAS_Msk          (0xFU << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000F00 */\n#define FMC_SDTR1_TRAS              FMC_SDTR1_TRAS_Msk                         /*!<TRAS[3:0] bits (Self refresh time) */\n#define FMC_SDTR1_TRAS_0            (0x1U << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000100 */\n#define FMC_SDTR1_TRAS_1            (0x2U << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000200 */\n#define FMC_SDTR1_TRAS_2            (0x4U << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000400 */\n#define FMC_SDTR1_TRAS_3            (0x8U << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000800 */\n\n#define FMC_SDTR1_TRC_Pos           (12U)\n#define FMC_SDTR1_TRC_Msk           (0xFU << FMC_SDTR1_TRC_Pos)                /*!< 0x0000F000 */\n#define FMC_SDTR1_TRC               FMC_SDTR1_TRC_Msk                          /*!<TRC[2:0] bits (Row cycle delay) */\n#define FMC_SDTR1_TRC_0             (0x1U << FMC_SDTR1_TRC_Pos)                /*!< 0x00001000 */\n#define FMC_SDTR1_TRC_1             (0x2U << FMC_SDTR1_TRC_Pos)                /*!< 0x00002000 */\n#define FMC_SDTR1_TRC_2             (0x4U << FMC_SDTR1_TRC_Pos)                /*!< 0x00004000 */\n\n#define FMC_SDTR1_TWR_Pos           (16U)\n#define FMC_SDTR1_TWR_Msk           (0xFU << FMC_SDTR1_TWR_Pos)                /*!< 0x000F0000 */\n#define FMC_SDTR1_TWR               FMC_SDTR1_TWR_Msk                          /*!<TRC[2:0] bits (Write recovery delay) */\n#define FMC_SDTR1_TWR_0             (0x1U << FMC_SDTR1_TWR_Pos)                /*!< 0x00010000 */\n#define FMC_SDTR1_TWR_1             (0x2U << FMC_SDTR1_TWR_Pos)                /*!< 0x00020000 */\n#define FMC_SDTR1_TWR_2             (0x4U << FMC_SDTR1_TWR_Pos)                /*!< 0x00040000 */\n\n#define FMC_SDTR1_TRP_Pos           (20U)\n#define FMC_SDTR1_TRP_Msk           (0xFU << FMC_SDTR1_TRP_Pos)                /*!< 0x00F00000 */\n#define FMC_SDTR1_TRP               FMC_SDTR1_TRP_Msk                          /*!<TRP[2:0] bits (Row precharge delay) */\n#define FMC_SDTR1_TRP_0             (0x1U << FMC_SDTR1_TRP_Pos)                /*!< 0x00100000 */\n#define FMC_SDTR1_TRP_1             (0x2U << FMC_SDTR1_TRP_Pos)                /*!< 0x00200000 */\n#define FMC_SDTR1_TRP_2             (0x4U << FMC_SDTR1_TRP_Pos)                /*!< 0x00400000 */\n\n#define FMC_SDTR1_TRCD_Pos          (24U)\n#define FMC_SDTR1_TRCD_Msk          (0xFU << FMC_SDTR1_TRCD_Pos)               /*!< 0x0F000000 */\n#define FMC_SDTR1_TRCD              FMC_SDTR1_TRCD_Msk                         /*!<TRP[2:0] bits (Row to column delay) */\n#define FMC_SDTR1_TRCD_0            (0x1U << FMC_SDTR1_TRCD_Pos)               /*!< 0x01000000 */\n#define FMC_SDTR1_TRCD_1            (0x2U << FMC_SDTR1_TRCD_Pos)               /*!< 0x02000000 */\n#define FMC_SDTR1_TRCD_2            (0x4U << FMC_SDTR1_TRCD_Pos)               /*!< 0x04000000 */\n\n/******************  Bit definition for FMC_SDTR2 register  ******************/\n#define FMC_SDTR2_TMRD_Pos          (0U)\n#define FMC_SDTR2_TMRD_Msk          (0xFU << FMC_SDTR2_TMRD_Pos)               /*!< 0x0000000F */\n#define FMC_SDTR2_TMRD              FMC_SDTR2_TMRD_Msk                         /*!<TMRD[3:0] bits (Load mode register to active) */\n#define FMC_SDTR2_TMRD_0            (0x1U << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000001 */\n#define FMC_SDTR2_TMRD_1            (0x2U << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000002 */\n#define FMC_SDTR2_TMRD_2            (0x4U << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000004 */\n#define FMC_SDTR2_TMRD_3            (0x8U << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000008 */\n\n#define FMC_SDTR2_TXSR_Pos          (4U)\n#define FMC_SDTR2_TXSR_Msk          (0xFU << FMC_SDTR2_TXSR_Pos)               /*!< 0x000000F0 */\n#define FMC_SDTR2_TXSR              FMC_SDTR2_TXSR_Msk                         /*!<TXSR[3:0] bits (Exit self refresh) */\n#define FMC_SDTR2_TXSR_0            (0x1U << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000010 */\n#define FMC_SDTR2_TXSR_1            (0x2U << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000020 */\n#define FMC_SDTR2_TXSR_2            (0x4U << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000040 */\n#define FMC_SDTR2_TXSR_3            (0x8U << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000080 */\n\n#define FMC_SDTR2_TRAS_Pos          (8U)\n#define FMC_SDTR2_TRAS_Msk          (0xFU << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000F00 */\n#define FMC_SDTR2_TRAS              FMC_SDTR2_TRAS_Msk                         /*!<TRAS[3:0] bits (Self refresh time) */\n#define FMC_SDTR2_TRAS_0            (0x1U << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000100 */\n#define FMC_SDTR2_TRAS_1            (0x2U << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000200 */\n#define FMC_SDTR2_TRAS_2            (0x4U << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000400 */\n#define FMC_SDTR2_TRAS_3            (0x8U << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000800 */\n\n#define FMC_SDTR2_TRC_Pos           (12U)\n#define FMC_SDTR2_TRC_Msk           (0xFU << FMC_SDTR2_TRC_Pos)                /*!< 0x0000F000 */\n#define FMC_SDTR2_TRC               FMC_SDTR2_TRC_Msk                          /*!<TRC[2:0] bits (Row cycle delay) */\n#define FMC_SDTR2_TRC_0             (0x1U << FMC_SDTR2_TRC_Pos)                /*!< 0x00001000 */\n#define FMC_SDTR2_TRC_1             (0x2U << FMC_SDTR2_TRC_Pos)                /*!< 0x00002000 */\n#define FMC_SDTR2_TRC_2             (0x4U << FMC_SDTR2_TRC_Pos)                /*!< 0x00004000 */\n\n#define FMC_SDTR2_TWR_Pos           (16U)\n#define FMC_SDTR2_TWR_Msk           (0xFU << FMC_SDTR2_TWR_Pos)                /*!< 0x000F0000 */\n#define FMC_SDTR2_TWR               FMC_SDTR2_TWR_Msk                          /*!<TRC[2:0] bits (Write recovery delay) */\n#define FMC_SDTR2_TWR_0             (0x1U << FMC_SDTR2_TWR_Pos)                /*!< 0x00010000 */\n#define FMC_SDTR2_TWR_1             (0x2U << FMC_SDTR2_TWR_Pos)                /*!< 0x00020000 */\n#define FMC_SDTR2_TWR_2             (0x4U << FMC_SDTR2_TWR_Pos)                /*!< 0x00040000 */\n\n#define FMC_SDTR2_TRP_Pos           (20U)\n#define FMC_SDTR2_TRP_Msk           (0xFU << FMC_SDTR2_TRP_Pos)                /*!< 0x00F00000 */\n#define FMC_SDTR2_TRP               FMC_SDTR2_TRP_Msk                          /*!<TRP[2:0] bits (Row precharge delay) */\n#define FMC_SDTR2_TRP_0             (0x1U << FMC_SDTR2_TRP_Pos)                /*!< 0x00100000 */\n#define FMC_SDTR2_TRP_1             (0x2U << FMC_SDTR2_TRP_Pos)                /*!< 0x00200000 */\n#define FMC_SDTR2_TRP_2             (0x4U << FMC_SDTR2_TRP_Pos)                /*!< 0x00400000 */\n\n#define FMC_SDTR2_TRCD_Pos          (24U)\n#define FMC_SDTR2_TRCD_Msk          (0xFU << FMC_SDTR2_TRCD_Pos)               /*!< 0x0F000000 */\n#define FMC_SDTR2_TRCD              FMC_SDTR2_TRCD_Msk                         /*!<TRP[2:0] bits (Row to column delay) */\n#define FMC_SDTR2_TRCD_0            (0x1U << FMC_SDTR2_TRCD_Pos)               /*!< 0x01000000 */\n#define FMC_SDTR2_TRCD_1            (0x2U << FMC_SDTR2_TRCD_Pos)               /*!< 0x02000000 */\n#define FMC_SDTR2_TRCD_2            (0x4U << FMC_SDTR2_TRCD_Pos)               /*!< 0x04000000 */\n\n/******************  Bit definition for FMC_SDCMR register  ******************/\n#define FMC_SDCMR_MODE_Pos          (0U)\n#define FMC_SDCMR_MODE_Msk          (0x7U << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */\n#define FMC_SDCMR_MODE              FMC_SDCMR_MODE_Msk                         /*!<MODE[2:0] bits (Command mode) */\n#define FMC_SDCMR_MODE_0            (0x1U << FMC_SDCMR_MODE_Pos)               /*!< 0x00000001 */\n#define FMC_SDCMR_MODE_1            (0x2U << FMC_SDCMR_MODE_Pos)               /*!< 0x00000002 */\n#define FMC_SDCMR_MODE_2            (0x4U << FMC_SDCMR_MODE_Pos)               /*!< 0x00000004 */\n\n#define FMC_SDCMR_CTB2_Pos          (3U)\n#define FMC_SDCMR_CTB2_Msk          (0x1U << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */\n#define FMC_SDCMR_CTB2              FMC_SDCMR_CTB2_Msk                         /*!<Command target 2 */\n\n#define FMC_SDCMR_CTB1_Pos          (4U)\n#define FMC_SDCMR_CTB1_Msk          (0x1U << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */\n#define FMC_SDCMR_CTB1              FMC_SDCMR_CTB1_Msk                         /*!<Command target 1 */\n\n#define FMC_SDCMR_NRFS_Pos          (5U)\n#define FMC_SDCMR_NRFS_Msk          (0xFU << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */\n#define FMC_SDCMR_NRFS              FMC_SDCMR_NRFS_Msk                         /*!<NRFS[3:0] bits (Number of auto-refresh) */\n#define FMC_SDCMR_NRFS_0            (0x1U << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000020 */\n#define FMC_SDCMR_NRFS_1            (0x2U << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000040 */\n#define FMC_SDCMR_NRFS_2            (0x4U << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000080 */\n#define FMC_SDCMR_NRFS_3            (0x8U << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000100 */\n\n#define FMC_SDCMR_MRD_Pos           (9U)\n#define FMC_SDCMR_MRD_Msk           (0x1FFFU << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */\n#define FMC_SDCMR_MRD               FMC_SDCMR_MRD_Msk                          /*!<MRD[12:0] bits (Mode register definition) */\n\n/******************  Bit definition for FMC_SDRTR register  ******************/\n#define FMC_SDRTR_CRE_Pos           (0U)\n#define FMC_SDRTR_CRE_Msk           (0x1U << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */\n#define FMC_SDRTR_CRE               FMC_SDRTR_CRE_Msk                          /*!<Clear refresh error flag */\n\n#define FMC_SDRTR_COUNT_Pos         (1U)\n#define FMC_SDRTR_COUNT_Msk         (0x1FFFU << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */\n#define FMC_SDRTR_COUNT             FMC_SDRTR_COUNT_Msk                        /*!<COUNT[12:0] bits (Refresh timer count) */\n\n#define FMC_SDRTR_REIE_Pos          (14U)\n#define FMC_SDRTR_REIE_Msk          (0x1U << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */\n#define FMC_SDRTR_REIE              FMC_SDRTR_REIE_Msk                         /*!<RES interupt enable */\n\n/******************  Bit definition for FMC_SDSR register  ******************/\n#define FMC_SDSR_RE_Pos             (0U)\n#define FMC_SDSR_RE_Msk             (0x1U << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */\n#define FMC_SDSR_RE                 FMC_SDSR_RE_Msk                            /*!<Refresh error flag */\n\n#define FMC_SDSR_MODES1_Pos         (1U)\n#define FMC_SDSR_MODES1_Msk         (0x3U << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */\n#define FMC_SDSR_MODES1             FMC_SDSR_MODES1_Msk                        /*!<MODES1[1:0]bits (Status mode for bank 1) */\n#define FMC_SDSR_MODES1_0           (0x1U << FMC_SDSR_MODES1_Pos)              /*!< 0x00000002 */\n#define FMC_SDSR_MODES1_1           (0x2U << FMC_SDSR_MODES1_Pos)              /*!< 0x00000004 */\n\n#define FMC_SDSR_MODES2_Pos         (3U)\n#define FMC_SDSR_MODES2_Msk         (0x3U << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */\n#define FMC_SDSR_MODES2             FMC_SDSR_MODES2_Msk                        /*!<MODES2[1:0]bits (Status mode for bank 2) */\n#define FMC_SDSR_MODES2_0           (0x1U << FMC_SDSR_MODES2_Pos)              /*!< 0x00000008 */\n#define FMC_SDSR_MODES2_1           (0x2U << FMC_SDSR_MODES2_Pos)              /*!< 0x00000010 */\n#define FMC_SDSR_BUSY_Pos           (5U)\n#define FMC_SDSR_BUSY_Msk           (0x1U << FMC_SDSR_BUSY_Pos)                /*!< 0x00000020 */\n#define FMC_SDSR_BUSY               FMC_SDSR_BUSY_Msk                          /*!<Busy status */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            General Purpose I/O                             */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bits definition for GPIO_MODER register  *****************/\n#define GPIO_MODER_MODE0_Pos             (0U)\n#define GPIO_MODER_MODE0_Msk             (0x3U << GPIO_MODER_MODE0_Pos)        /*!< 0x00000003 */\n#define GPIO_MODER_MODE0                 GPIO_MODER_MODE0_Msk\n#define GPIO_MODER_MODE0_0               (0x1U << GPIO_MODER_MODE0_Pos)        /*!< 0x00000001 */\n#define GPIO_MODER_MODE0_1               (0x2U << GPIO_MODER_MODE0_Pos)        /*!< 0x00000002 */\n#define GPIO_MODER_MODE1_Pos             (2U)\n#define GPIO_MODER_MODE1_Msk             (0x3U << GPIO_MODER_MODE1_Pos)        /*!< 0x0000000C */\n#define GPIO_MODER_MODE1                 GPIO_MODER_MODE1_Msk\n#define GPIO_MODER_MODE1_0               (0x1U << GPIO_MODER_MODE1_Pos)        /*!< 0x00000004 */\n#define GPIO_MODER_MODE1_1               (0x2U << GPIO_MODER_MODE1_Pos)        /*!< 0x00000008 */\n#define GPIO_MODER_MODE2_Pos             (4U)\n#define GPIO_MODER_MODE2_Msk             (0x3U << GPIO_MODER_MODE2_Pos)        /*!< 0x00000030 */\n#define GPIO_MODER_MODE2                 GPIO_MODER_MODE2_Msk\n#define GPIO_MODER_MODE2_0               (0x1U << GPIO_MODER_MODE2_Pos)        /*!< 0x00000010 */\n#define GPIO_MODER_MODE2_1               (0x2U << GPIO_MODER_MODE2_Pos)        /*!< 0x00000020 */\n#define GPIO_MODER_MODE3_Pos             (6U)\n#define GPIO_MODER_MODE3_Msk             (0x3U << GPIO_MODER_MODE3_Pos)        /*!< 0x000000C0 */\n#define GPIO_MODER_MODE3                 GPIO_MODER_MODE3_Msk\n#define GPIO_MODER_MODE3_0               (0x1U << GPIO_MODER_MODE3_Pos)        /*!< 0x00000040 */\n#define GPIO_MODER_MODE3_1               (0x2U << GPIO_MODER_MODE3_Pos)        /*!< 0x00000080 */\n#define GPIO_MODER_MODE4_Pos             (8U)\n#define GPIO_MODER_MODE4_Msk             (0x3U << GPIO_MODER_MODE4_Pos)        /*!< 0x00000300 */\n#define GPIO_MODER_MODE4                 GPIO_MODER_MODE4_Msk\n#define GPIO_MODER_MODE4_0               (0x1U << GPIO_MODER_MODE4_Pos)        /*!< 0x00000100 */\n#define GPIO_MODER_MODE4_1               (0x2U << GPIO_MODER_MODE4_Pos)        /*!< 0x00000200 */\n#define GPIO_MODER_MODE5_Pos             (10U)\n#define GPIO_MODER_MODE5_Msk             (0x3U << GPIO_MODER_MODE5_Pos)        /*!< 0x00000C00 */\n#define GPIO_MODER_MODE5                 GPIO_MODER_MODE5_Msk\n#define GPIO_MODER_MODE5_0               (0x1U << GPIO_MODER_MODE5_Pos)        /*!< 0x00000400 */\n#define GPIO_MODER_MODE5_1               (0x2U << GPIO_MODER_MODE5_Pos)        /*!< 0x00000800 */\n#define GPIO_MODER_MODE6_Pos             (12U)\n#define GPIO_MODER_MODE6_Msk             (0x3U << GPIO_MODER_MODE6_Pos)        /*!< 0x00003000 */\n#define GPIO_MODER_MODE6                 GPIO_MODER_MODE6_Msk\n#define GPIO_MODER_MODE6_0               (0x1U << GPIO_MODER_MODE6_Pos)        /*!< 0x00001000 */\n#define GPIO_MODER_MODE6_1               (0x2U << GPIO_MODER_MODE6_Pos)        /*!< 0x00002000 */\n#define GPIO_MODER_MODE7_Pos             (14U)\n#define GPIO_MODER_MODE7_Msk             (0x3U << GPIO_MODER_MODE7_Pos)        /*!< 0x0000C000 */\n#define GPIO_MODER_MODE7                 GPIO_MODER_MODE7_Msk\n#define GPIO_MODER_MODE7_0               (0x1U << GPIO_MODER_MODE7_Pos)        /*!< 0x00004000 */\n#define GPIO_MODER_MODE7_1               (0x2U << GPIO_MODER_MODE7_Pos)        /*!< 0x00008000 */\n#define GPIO_MODER_MODE8_Pos             (16U)\n#define GPIO_MODER_MODE8_Msk             (0x3U << GPIO_MODER_MODE8_Pos)        /*!< 0x00030000 */\n#define GPIO_MODER_MODE8                 GPIO_MODER_MODE8_Msk\n#define GPIO_MODER_MODE8_0               (0x1U << GPIO_MODER_MODE8_Pos)        /*!< 0x00010000 */\n#define GPIO_MODER_MODE8_1               (0x2U << GPIO_MODER_MODE8_Pos)        /*!< 0x00020000 */\n#define GPIO_MODER_MODE9_Pos             (18U)\n#define GPIO_MODER_MODE9_Msk             (0x3U << GPIO_MODER_MODE9_Pos)        /*!< 0x000C0000 */\n#define GPIO_MODER_MODE9                 GPIO_MODER_MODE9_Msk\n#define GPIO_MODER_MODE9_0               (0x1U << GPIO_MODER_MODE9_Pos)        /*!< 0x00040000 */\n#define GPIO_MODER_MODE9_1               (0x2U << GPIO_MODER_MODE9_Pos)        /*!< 0x00080000 */\n#define GPIO_MODER_MODE10_Pos            (20U)\n#define GPIO_MODER_MODE10_Msk            (0x3U << GPIO_MODER_MODE10_Pos)       /*!< 0x00300000 */\n#define GPIO_MODER_MODE10                GPIO_MODER_MODE10_Msk\n#define GPIO_MODER_MODE10_0              (0x1U << GPIO_MODER_MODE10_Pos)       /*!< 0x00100000 */\n#define GPIO_MODER_MODE10_1              (0x2U << GPIO_MODER_MODE10_Pos)       /*!< 0x00200000 */\n#define GPIO_MODER_MODE11_Pos            (22U)\n#define GPIO_MODER_MODE11_Msk            (0x3U << GPIO_MODER_MODE11_Pos)       /*!< 0x00C00000 */\n#define GPIO_MODER_MODE11                GPIO_MODER_MODE11_Msk\n#define GPIO_MODER_MODE11_0              (0x1U << GPIO_MODER_MODE11_Pos)       /*!< 0x00400000 */\n#define GPIO_MODER_MODE11_1              (0x2U << GPIO_MODER_MODE11_Pos)       /*!< 0x00800000 */\n#define GPIO_MODER_MODE12_Pos            (24U)\n#define GPIO_MODER_MODE12_Msk            (0x3U << GPIO_MODER_MODE12_Pos)       /*!< 0x03000000 */\n#define GPIO_MODER_MODE12                GPIO_MODER_MODE12_Msk\n#define GPIO_MODER_MODE12_0              (0x1U << GPIO_MODER_MODE12_Pos)       /*!< 0x01000000 */\n#define GPIO_MODER_MODE12_1              (0x2U << GPIO_MODER_MODE12_Pos)       /*!< 0x02000000 */\n#define GPIO_MODER_MODE13_Pos            (26U)\n#define GPIO_MODER_MODE13_Msk            (0x3U << GPIO_MODER_MODE13_Pos)       /*!< 0x0C000000 */\n#define GPIO_MODER_MODE13                GPIO_MODER_MODE13_Msk\n#define GPIO_MODER_MODE13_0              (0x1U << GPIO_MODER_MODE13_Pos)       /*!< 0x04000000 */\n#define GPIO_MODER_MODE13_1              (0x2U << GPIO_MODER_MODE13_Pos)       /*!< 0x08000000 */\n#define GPIO_MODER_MODE14_Pos            (28U)\n#define GPIO_MODER_MODE14_Msk            (0x3U << GPIO_MODER_MODE14_Pos)       /*!< 0x30000000 */\n#define GPIO_MODER_MODE14                GPIO_MODER_MODE14_Msk\n#define GPIO_MODER_MODE14_0              (0x1U << GPIO_MODER_MODE14_Pos)       /*!< 0x10000000 */\n#define GPIO_MODER_MODE14_1              (0x2U << GPIO_MODER_MODE14_Pos)       /*!< 0x20000000 */\n#define GPIO_MODER_MODE15_Pos            (30U)\n#define GPIO_MODER_MODE15_Msk            (0x3U << GPIO_MODER_MODE15_Pos)       /*!< 0xC0000000 */\n#define GPIO_MODER_MODE15                GPIO_MODER_MODE15_Msk\n#define GPIO_MODER_MODE15_0              (0x1U << GPIO_MODER_MODE15_Pos)       /*!< 0x40000000 */\n#define GPIO_MODER_MODE15_1              (0x2U << GPIO_MODER_MODE15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_MODER_MODER0_Pos            (0U)\n#define GPIO_MODER_MODER0_Msk            (0x3U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */\n#define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk\n#define GPIO_MODER_MODER0_0              (0x1U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */\n#define GPIO_MODER_MODER0_1              (0x2U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */\n#define GPIO_MODER_MODER1_Pos            (2U)\n#define GPIO_MODER_MODER1_Msk            (0x3U << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */\n#define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk\n#define GPIO_MODER_MODER1_0              (0x1U << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */\n#define GPIO_MODER_MODER1_1              (0x2U << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */\n#define GPIO_MODER_MODER2_Pos            (4U)\n#define GPIO_MODER_MODER2_Msk            (0x3U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */\n#define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk\n#define GPIO_MODER_MODER2_0              (0x1U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */\n#define GPIO_MODER_MODER2_1              (0x2U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */\n#define GPIO_MODER_MODER3_Pos            (6U)\n#define GPIO_MODER_MODER3_Msk            (0x3U << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */\n#define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk\n#define GPIO_MODER_MODER3_0              (0x1U << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */\n#define GPIO_MODER_MODER3_1              (0x2U << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */\n#define GPIO_MODER_MODER4_Pos            (8U)\n#define GPIO_MODER_MODER4_Msk            (0x3U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */\n#define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk\n#define GPIO_MODER_MODER4_0              (0x1U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */\n#define GPIO_MODER_MODER4_1              (0x2U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */\n#define GPIO_MODER_MODER5_Pos            (10U)\n#define GPIO_MODER_MODER5_Msk            (0x3U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */\n#define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk\n#define GPIO_MODER_MODER5_0              (0x1U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */\n#define GPIO_MODER_MODER5_1              (0x2U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */\n#define GPIO_MODER_MODER6_Pos            (12U)\n#define GPIO_MODER_MODER6_Msk            (0x3U << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */\n#define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk\n#define GPIO_MODER_MODER6_0              (0x1U << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */\n#define GPIO_MODER_MODER6_1              (0x2U << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */\n#define GPIO_MODER_MODER7_Pos            (14U)\n#define GPIO_MODER_MODER7_Msk            (0x3U << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */\n#define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk\n#define GPIO_MODER_MODER7_0              (0x1U << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */\n#define GPIO_MODER_MODER7_1              (0x2U << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */\n#define GPIO_MODER_MODER8_Pos            (16U)\n#define GPIO_MODER_MODER8_Msk            (0x3U << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */\n#define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk\n#define GPIO_MODER_MODER8_0              (0x1U << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */\n#define GPIO_MODER_MODER8_1              (0x2U << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */\n#define GPIO_MODER_MODER9_Pos            (18U)\n#define GPIO_MODER_MODER9_Msk            (0x3U << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */\n#define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk\n#define GPIO_MODER_MODER9_0              (0x1U << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */\n#define GPIO_MODER_MODER9_1              (0x2U << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */\n#define GPIO_MODER_MODER10_Pos           (20U)\n#define GPIO_MODER_MODER10_Msk           (0x3U << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */\n#define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk\n#define GPIO_MODER_MODER10_0             (0x1U << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */\n#define GPIO_MODER_MODER10_1             (0x2U << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */\n#define GPIO_MODER_MODER11_Pos           (22U)\n#define GPIO_MODER_MODER11_Msk           (0x3U << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */\n#define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk\n#define GPIO_MODER_MODER11_0             (0x1U << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */\n#define GPIO_MODER_MODER11_1             (0x2U << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */\n#define GPIO_MODER_MODER12_Pos           (24U)\n#define GPIO_MODER_MODER12_Msk           (0x3U << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */\n#define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk\n#define GPIO_MODER_MODER12_0             (0x1U << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */\n#define GPIO_MODER_MODER12_1             (0x2U << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */\n#define GPIO_MODER_MODER13_Pos           (26U)\n#define GPIO_MODER_MODER13_Msk           (0x3U << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */\n#define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk\n#define GPIO_MODER_MODER13_0             (0x1U << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */\n#define GPIO_MODER_MODER13_1             (0x2U << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */\n#define GPIO_MODER_MODER14_Pos           (28U)\n#define GPIO_MODER_MODER14_Msk           (0x3U << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */\n#define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk\n#define GPIO_MODER_MODER14_0             (0x1U << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */\n#define GPIO_MODER_MODER14_1             (0x2U << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */\n#define GPIO_MODER_MODER15_Pos           (30U)\n#define GPIO_MODER_MODER15_Msk           (0x3U << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */\n#define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk\n#define GPIO_MODER_MODER15_0             (0x1U << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */\n#define GPIO_MODER_MODER15_1             (0x2U << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */\n\n/******************  Bits definition for GPIO_OTYPER register  ****************/\n#define GPIO_OTYPER_OT0_Pos              (0U)\n#define GPIO_OTYPER_OT0_Msk              (0x1U << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */\n#define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk\n#define GPIO_OTYPER_OT1_Pos              (1U)\n#define GPIO_OTYPER_OT1_Msk              (0x1U << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */\n#define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk\n#define GPIO_OTYPER_OT2_Pos              (2U)\n#define GPIO_OTYPER_OT2_Msk              (0x1U << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */\n#define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk\n#define GPIO_OTYPER_OT3_Pos              (3U)\n#define GPIO_OTYPER_OT3_Msk              (0x1U << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */\n#define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk\n#define GPIO_OTYPER_OT4_Pos              (4U)\n#define GPIO_OTYPER_OT4_Msk              (0x1U << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */\n#define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk\n#define GPIO_OTYPER_OT5_Pos              (5U)\n#define GPIO_OTYPER_OT5_Msk              (0x1U << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */\n#define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk\n#define GPIO_OTYPER_OT6_Pos              (6U)\n#define GPIO_OTYPER_OT6_Msk              (0x1U << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */\n#define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk\n#define GPIO_OTYPER_OT7_Pos              (7U)\n#define GPIO_OTYPER_OT7_Msk              (0x1U << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */\n#define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk\n#define GPIO_OTYPER_OT8_Pos              (8U)\n#define GPIO_OTYPER_OT8_Msk              (0x1U << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */\n#define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk\n#define GPIO_OTYPER_OT9_Pos              (9U)\n#define GPIO_OTYPER_OT9_Msk              (0x1U << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */\n#define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk\n#define GPIO_OTYPER_OT10_Pos             (10U)\n#define GPIO_OTYPER_OT10_Msk             (0x1U << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */\n#define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk\n#define GPIO_OTYPER_OT11_Pos             (11U)\n#define GPIO_OTYPER_OT11_Msk             (0x1U << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */\n#define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk\n#define GPIO_OTYPER_OT12_Pos             (12U)\n#define GPIO_OTYPER_OT12_Msk             (0x1U << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */\n#define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk\n#define GPIO_OTYPER_OT13_Pos             (13U)\n#define GPIO_OTYPER_OT13_Msk             (0x1U << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */\n#define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk\n#define GPIO_OTYPER_OT14_Pos             (14U)\n#define GPIO_OTYPER_OT14_Msk             (0x1U << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */\n#define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk\n#define GPIO_OTYPER_OT15_Pos             (15U)\n#define GPIO_OTYPER_OT15_Msk             (0x1U << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */\n#define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk\n\n/* Legacy defines */\n#define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0\n#define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1\n#define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2\n#define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3\n#define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4\n#define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5\n#define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6\n#define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7\n#define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8\n#define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9\n#define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10\n#define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11\n#define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12\n#define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13\n#define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14\n#define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15\n\n/******************  Bits definition for GPIO_OSPEEDR register  ***************/\n#define GPIO_OSPEEDR_OSPEED0_Pos         (0U)\n#define GPIO_OSPEEDR_OSPEED0_Msk         (0x3U << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000003 */\n#define GPIO_OSPEEDR_OSPEED0             GPIO_OSPEEDR_OSPEED0_Msk\n#define GPIO_OSPEEDR_OSPEED0_0           (0x1U << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000001 */\n#define GPIO_OSPEEDR_OSPEED0_1           (0x2U << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000002 */\n#define GPIO_OSPEEDR_OSPEED1_Pos         (2U)\n#define GPIO_OSPEEDR_OSPEED1_Msk         (0x3U << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x0000000C */\n#define GPIO_OSPEEDR_OSPEED1             GPIO_OSPEEDR_OSPEED1_Msk\n#define GPIO_OSPEEDR_OSPEED1_0           (0x1U << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000004 */\n#define GPIO_OSPEEDR_OSPEED1_1           (0x2U << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000008 */\n#define GPIO_OSPEEDR_OSPEED2_Pos         (4U)\n#define GPIO_OSPEEDR_OSPEED2_Msk         (0x3U << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000030 */\n#define GPIO_OSPEEDR_OSPEED2             GPIO_OSPEEDR_OSPEED2_Msk\n#define GPIO_OSPEEDR_OSPEED2_0           (0x1U << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000010 */\n#define GPIO_OSPEEDR_OSPEED2_1           (0x2U << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000020 */\n#define GPIO_OSPEEDR_OSPEED3_Pos         (6U)\n#define GPIO_OSPEEDR_OSPEED3_Msk         (0x3U << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x000000C0 */\n#define GPIO_OSPEEDR_OSPEED3             GPIO_OSPEEDR_OSPEED3_Msk\n#define GPIO_OSPEEDR_OSPEED3_0           (0x1U << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000040 */\n#define GPIO_OSPEEDR_OSPEED3_1           (0x2U << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000080 */\n#define GPIO_OSPEEDR_OSPEED4_Pos         (8U)\n#define GPIO_OSPEEDR_OSPEED4_Msk         (0x3U << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000300 */\n#define GPIO_OSPEEDR_OSPEED4             GPIO_OSPEEDR_OSPEED4_Msk\n#define GPIO_OSPEEDR_OSPEED4_0           (0x1U << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000100 */\n#define GPIO_OSPEEDR_OSPEED4_1           (0x2U << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000200 */\n#define GPIO_OSPEEDR_OSPEED5_Pos         (10U)\n#define GPIO_OSPEEDR_OSPEED5_Msk         (0x3U << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000C00 */\n#define GPIO_OSPEEDR_OSPEED5             GPIO_OSPEEDR_OSPEED5_Msk\n#define GPIO_OSPEEDR_OSPEED5_0           (0x1U << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000400 */\n#define GPIO_OSPEEDR_OSPEED5_1           (0x2U << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000800 */\n#define GPIO_OSPEEDR_OSPEED6_Pos         (12U)\n#define GPIO_OSPEEDR_OSPEED6_Msk         (0x3U << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00003000 */\n#define GPIO_OSPEEDR_OSPEED6             GPIO_OSPEEDR_OSPEED6_Msk\n#define GPIO_OSPEEDR_OSPEED6_0           (0x1U << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00001000 */\n#define GPIO_OSPEEDR_OSPEED6_1           (0x2U << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00002000 */\n#define GPIO_OSPEEDR_OSPEED7_Pos         (14U)\n#define GPIO_OSPEEDR_OSPEED7_Msk         (0x3U << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x0000C000 */\n#define GPIO_OSPEEDR_OSPEED7             GPIO_OSPEEDR_OSPEED7_Msk\n#define GPIO_OSPEEDR_OSPEED7_0           (0x1U << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00004000 */\n#define GPIO_OSPEEDR_OSPEED7_1           (0x2U << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00008000 */\n#define GPIO_OSPEEDR_OSPEED8_Pos         (16U)\n#define GPIO_OSPEEDR_OSPEED8_Msk         (0x3U << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00030000 */\n#define GPIO_OSPEEDR_OSPEED8             GPIO_OSPEEDR_OSPEED8_Msk\n#define GPIO_OSPEEDR_OSPEED8_0           (0x1U << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00010000 */\n#define GPIO_OSPEEDR_OSPEED8_1           (0x2U << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00020000 */\n#define GPIO_OSPEEDR_OSPEED9_Pos         (18U)\n#define GPIO_OSPEEDR_OSPEED9_Msk         (0x3U << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x000C0000 */\n#define GPIO_OSPEEDR_OSPEED9             GPIO_OSPEEDR_OSPEED9_Msk\n#define GPIO_OSPEEDR_OSPEED9_0           (0x1U << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00040000 */\n#define GPIO_OSPEEDR_OSPEED9_1           (0x2U << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00080000 */\n#define GPIO_OSPEEDR_OSPEED10_Pos        (20U)\n#define GPIO_OSPEEDR_OSPEED10_Msk        (0x3U << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00300000 */\n#define GPIO_OSPEEDR_OSPEED10            GPIO_OSPEEDR_OSPEED10_Msk\n#define GPIO_OSPEEDR_OSPEED10_0          (0x1U << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00100000 */\n#define GPIO_OSPEEDR_OSPEED10_1          (0x2U << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00200000 */\n#define GPIO_OSPEEDR_OSPEED11_Pos        (22U)\n#define GPIO_OSPEEDR_OSPEED11_Msk        (0x3U << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00C00000 */\n#define GPIO_OSPEEDR_OSPEED11            GPIO_OSPEEDR_OSPEED11_Msk\n#define GPIO_OSPEEDR_OSPEED11_0          (0x1U << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00400000 */\n#define GPIO_OSPEEDR_OSPEED11_1          (0x2U << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00800000 */\n#define GPIO_OSPEEDR_OSPEED12_Pos        (24U)\n#define GPIO_OSPEEDR_OSPEED12_Msk        (0x3U << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x03000000 */\n#define GPIO_OSPEEDR_OSPEED12            GPIO_OSPEEDR_OSPEED12_Msk\n#define GPIO_OSPEEDR_OSPEED12_0          (0x1U << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x01000000 */\n#define GPIO_OSPEEDR_OSPEED12_1          (0x2U << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x02000000 */\n#define GPIO_OSPEEDR_OSPEED13_Pos        (26U)\n#define GPIO_OSPEEDR_OSPEED13_Msk        (0x3U << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x0C000000 */\n#define GPIO_OSPEEDR_OSPEED13            GPIO_OSPEEDR_OSPEED13_Msk\n#define GPIO_OSPEEDR_OSPEED13_0          (0x1U << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x04000000 */\n#define GPIO_OSPEEDR_OSPEED13_1          (0x2U << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x08000000 */\n#define GPIO_OSPEEDR_OSPEED14_Pos        (28U)\n#define GPIO_OSPEEDR_OSPEED14_Msk        (0x3U << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x30000000 */\n#define GPIO_OSPEEDR_OSPEED14            GPIO_OSPEEDR_OSPEED14_Msk\n#define GPIO_OSPEEDR_OSPEED14_0          (0x1U << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x10000000 */\n#define GPIO_OSPEEDR_OSPEED14_1          (0x2U << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x20000000 */\n#define GPIO_OSPEEDR_OSPEED15_Pos        (30U)\n#define GPIO_OSPEEDR_OSPEED15_Msk        (0x3U << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0xC0000000 */\n#define GPIO_OSPEEDR_OSPEED15            GPIO_OSPEEDR_OSPEED15_Msk\n#define GPIO_OSPEEDR_OSPEED15_0          (0x1U << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x40000000 */\n#define GPIO_OSPEEDR_OSPEED15_1          (0x2U << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0\n#define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0\n#define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1\n#define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1\n#define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0\n#define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1\n#define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2\n#define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0\n#define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1\n#define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3\n#define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0\n#define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1\n#define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4\n#define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0\n#define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1\n#define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5\n#define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0\n#define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1\n#define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6\n#define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0\n#define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1\n#define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7\n#define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0\n#define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1\n#define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8\n#define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0\n#define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1\n#define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9\n#define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0\n#define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1\n#define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10\n#define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0\n#define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1\n#define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11\n#define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0\n#define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1\n#define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12\n#define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0\n#define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1\n#define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13\n#define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0\n#define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1\n#define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14\n#define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0\n#define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1\n#define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15\n#define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0\n#define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1\n\n/******************  Bits definition for GPIO_PUPDR register  *****************/\n#define GPIO_PUPDR_PUPD0_Pos             (0U)\n#define GPIO_PUPDR_PUPD0_Msk             (0x3U << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000003 */\n#define GPIO_PUPDR_PUPD0                 GPIO_PUPDR_PUPD0_Msk\n#define GPIO_PUPDR_PUPD0_0               (0x1U << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000001 */\n#define GPIO_PUPDR_PUPD0_1               (0x2U << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000002 */\n#define GPIO_PUPDR_PUPD1_Pos             (2U)\n#define GPIO_PUPDR_PUPD1_Msk             (0x3U << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x0000000C */\n#define GPIO_PUPDR_PUPD1                 GPIO_PUPDR_PUPD1_Msk\n#define GPIO_PUPDR_PUPD1_0               (0x1U << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000004 */\n#define GPIO_PUPDR_PUPD1_1               (0x2U << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000008 */\n#define GPIO_PUPDR_PUPD2_Pos             (4U)\n#define GPIO_PUPDR_PUPD2_Msk             (0x3U << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000030 */\n#define GPIO_PUPDR_PUPD2                 GPIO_PUPDR_PUPD2_Msk\n#define GPIO_PUPDR_PUPD2_0               (0x1U << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000010 */\n#define GPIO_PUPDR_PUPD2_1               (0x2U << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000020 */\n#define GPIO_PUPDR_PUPD3_Pos             (6U)\n#define GPIO_PUPDR_PUPD3_Msk             (0x3U << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x000000C0 */\n#define GPIO_PUPDR_PUPD3                 GPIO_PUPDR_PUPD3_Msk\n#define GPIO_PUPDR_PUPD3_0               (0x1U << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000040 */\n#define GPIO_PUPDR_PUPD3_1               (0x2U << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000080 */\n#define GPIO_PUPDR_PUPD4_Pos             (8U)\n#define GPIO_PUPDR_PUPD4_Msk             (0x3U << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000300 */\n#define GPIO_PUPDR_PUPD4                 GPIO_PUPDR_PUPD4_Msk\n#define GPIO_PUPDR_PUPD4_0               (0x1U << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000100 */\n#define GPIO_PUPDR_PUPD4_1               (0x2U << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000200 */\n#define GPIO_PUPDR_PUPD5_Pos             (10U)\n#define GPIO_PUPDR_PUPD5_Msk             (0x3U << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000C00 */\n#define GPIO_PUPDR_PUPD5                 GPIO_PUPDR_PUPD5_Msk\n#define GPIO_PUPDR_PUPD5_0               (0x1U << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000400 */\n#define GPIO_PUPDR_PUPD5_1               (0x2U << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000800 */\n#define GPIO_PUPDR_PUPD6_Pos             (12U)\n#define GPIO_PUPDR_PUPD6_Msk             (0x3U << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00003000 */\n#define GPIO_PUPDR_PUPD6                 GPIO_PUPDR_PUPD6_Msk\n#define GPIO_PUPDR_PUPD6_0               (0x1U << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00001000 */\n#define GPIO_PUPDR_PUPD6_1               (0x2U << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00002000 */\n#define GPIO_PUPDR_PUPD7_Pos             (14U)\n#define GPIO_PUPDR_PUPD7_Msk             (0x3U << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x0000C000 */\n#define GPIO_PUPDR_PUPD7                 GPIO_PUPDR_PUPD7_Msk\n#define GPIO_PUPDR_PUPD7_0               (0x1U << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00004000 */\n#define GPIO_PUPDR_PUPD7_1               (0x2U << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00008000 */\n#define GPIO_PUPDR_PUPD8_Pos             (16U)\n#define GPIO_PUPDR_PUPD8_Msk             (0x3U << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00030000 */\n#define GPIO_PUPDR_PUPD8                 GPIO_PUPDR_PUPD8_Msk\n#define GPIO_PUPDR_PUPD8_0               (0x1U << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00010000 */\n#define GPIO_PUPDR_PUPD8_1               (0x2U << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00020000 */\n#define GPIO_PUPDR_PUPD9_Pos             (18U)\n#define GPIO_PUPDR_PUPD9_Msk             (0x3U << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x000C0000 */\n#define GPIO_PUPDR_PUPD9                 GPIO_PUPDR_PUPD9_Msk\n#define GPIO_PUPDR_PUPD9_0               (0x1U << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00040000 */\n#define GPIO_PUPDR_PUPD9_1               (0x2U << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00080000 */\n#define GPIO_PUPDR_PUPD10_Pos            (20U)\n#define GPIO_PUPDR_PUPD10_Msk            (0x3U << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00300000 */\n#define GPIO_PUPDR_PUPD10                GPIO_PUPDR_PUPD10_Msk\n#define GPIO_PUPDR_PUPD10_0              (0x1U << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00100000 */\n#define GPIO_PUPDR_PUPD10_1              (0x2U << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00200000 */\n#define GPIO_PUPDR_PUPD11_Pos            (22U)\n#define GPIO_PUPDR_PUPD11_Msk            (0x3U << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00C00000 */\n#define GPIO_PUPDR_PUPD11                GPIO_PUPDR_PUPD11_Msk\n#define GPIO_PUPDR_PUPD11_0              (0x1U << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00400000 */\n#define GPIO_PUPDR_PUPD11_1              (0x2U << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00800000 */\n#define GPIO_PUPDR_PUPD12_Pos            (24U)\n#define GPIO_PUPDR_PUPD12_Msk            (0x3U << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x03000000 */\n#define GPIO_PUPDR_PUPD12                GPIO_PUPDR_PUPD12_Msk\n#define GPIO_PUPDR_PUPD12_0              (0x1U << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x01000000 */\n#define GPIO_PUPDR_PUPD12_1              (0x2U << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x02000000 */\n#define GPIO_PUPDR_PUPD13_Pos            (26U)\n#define GPIO_PUPDR_PUPD13_Msk            (0x3U << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x0C000000 */\n#define GPIO_PUPDR_PUPD13                GPIO_PUPDR_PUPD13_Msk\n#define GPIO_PUPDR_PUPD13_0              (0x1U << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x04000000 */\n#define GPIO_PUPDR_PUPD13_1              (0x2U << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x08000000 */\n#define GPIO_PUPDR_PUPD14_Pos            (28U)\n#define GPIO_PUPDR_PUPD14_Msk            (0x3U << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x30000000 */\n#define GPIO_PUPDR_PUPD14                GPIO_PUPDR_PUPD14_Msk\n#define GPIO_PUPDR_PUPD14_0              (0x1U << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x10000000 */\n#define GPIO_PUPDR_PUPD14_1              (0x2U << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x20000000 */\n#define GPIO_PUPDR_PUPD15_Pos            (30U)\n#define GPIO_PUPDR_PUPD15_Msk            (0x3U << GPIO_PUPDR_PUPD15_Pos)       /*!< 0xC0000000 */\n#define GPIO_PUPDR_PUPD15                GPIO_PUPDR_PUPD15_Msk\n#define GPIO_PUPDR_PUPD15_0              (0x1U << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x40000000 */\n#define GPIO_PUPDR_PUPD15_1              (0x2U << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0\n#define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0\n#define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1\n#define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1\n#define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0\n#define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1\n#define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2\n#define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0\n#define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1\n#define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3\n#define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0\n#define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1\n#define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4\n#define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0\n#define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1\n#define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5\n#define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0\n#define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1\n#define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6\n#define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0\n#define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1\n#define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7\n#define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0\n#define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1\n#define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8\n#define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0\n#define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1\n#define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9\n#define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0\n#define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1\n#define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10\n#define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0\n#define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1\n#define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11\n#define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0\n#define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1\n#define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12\n#define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0\n#define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1\n#define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13\n#define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0\n#define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1\n#define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14\n#define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0\n#define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1\n#define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15\n#define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0\n#define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1\n\n/******************  Bits definition for GPIO_IDR register  *******************/\n#define GPIO_IDR_ID0_Pos                 (0U)\n#define GPIO_IDR_ID0_Msk                 (0x1U << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */\n#define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk\n#define GPIO_IDR_ID1_Pos                 (1U)\n#define GPIO_IDR_ID1_Msk                 (0x1U << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */\n#define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk\n#define GPIO_IDR_ID2_Pos                 (2U)\n#define GPIO_IDR_ID2_Msk                 (0x1U << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */\n#define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk\n#define GPIO_IDR_ID3_Pos                 (3U)\n#define GPIO_IDR_ID3_Msk                 (0x1U << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */\n#define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk\n#define GPIO_IDR_ID4_Pos                 (4U)\n#define GPIO_IDR_ID4_Msk                 (0x1U << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */\n#define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk\n#define GPIO_IDR_ID5_Pos                 (5U)\n#define GPIO_IDR_ID5_Msk                 (0x1U << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */\n#define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk\n#define GPIO_IDR_ID6_Pos                 (6U)\n#define GPIO_IDR_ID6_Msk                 (0x1U << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */\n#define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk\n#define GPIO_IDR_ID7_Pos                 (7U)\n#define GPIO_IDR_ID7_Msk                 (0x1U << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */\n#define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk\n#define GPIO_IDR_ID8_Pos                 (8U)\n#define GPIO_IDR_ID8_Msk                 (0x1U << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */\n#define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk\n#define GPIO_IDR_ID9_Pos                 (9U)\n#define GPIO_IDR_ID9_Msk                 (0x1U << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */\n#define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk\n#define GPIO_IDR_ID10_Pos                (10U)\n#define GPIO_IDR_ID10_Msk                (0x1U << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */\n#define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk\n#define GPIO_IDR_ID11_Pos                (11U)\n#define GPIO_IDR_ID11_Msk                (0x1U << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */\n#define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk\n#define GPIO_IDR_ID12_Pos                (12U)\n#define GPIO_IDR_ID12_Msk                (0x1U << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */\n#define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk\n#define GPIO_IDR_ID13_Pos                (13U)\n#define GPIO_IDR_ID13_Msk                (0x1U << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */\n#define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk\n#define GPIO_IDR_ID14_Pos                (14U)\n#define GPIO_IDR_ID14_Msk                (0x1U << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */\n#define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk\n#define GPIO_IDR_ID15_Pos                (15U)\n#define GPIO_IDR_ID15_Msk                (0x1U << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */\n#define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk\n\n/* Legacy defines */\n#define GPIO_IDR_IDR_0                      GPIO_IDR_ID0\n#define GPIO_IDR_IDR_1                      GPIO_IDR_ID1\n#define GPIO_IDR_IDR_2                      GPIO_IDR_ID2\n#define GPIO_IDR_IDR_3                      GPIO_IDR_ID3\n#define GPIO_IDR_IDR_4                      GPIO_IDR_ID4\n#define GPIO_IDR_IDR_5                      GPIO_IDR_ID5\n#define GPIO_IDR_IDR_6                      GPIO_IDR_ID6\n#define GPIO_IDR_IDR_7                      GPIO_IDR_ID7\n#define GPIO_IDR_IDR_8                      GPIO_IDR_ID8\n#define GPIO_IDR_IDR_9                      GPIO_IDR_ID9\n#define GPIO_IDR_IDR_10                     GPIO_IDR_ID10\n#define GPIO_IDR_IDR_11                     GPIO_IDR_ID11\n#define GPIO_IDR_IDR_12                     GPIO_IDR_ID12\n#define GPIO_IDR_IDR_13                     GPIO_IDR_ID13\n#define GPIO_IDR_IDR_14                     GPIO_IDR_ID14\n#define GPIO_IDR_IDR_15                     GPIO_IDR_ID15\n\n/******************  Bits definition for GPIO_ODR register  *******************/\n#define GPIO_ODR_OD0_Pos                 (0U)\n#define GPIO_ODR_OD0_Msk                 (0x1U << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */\n#define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk\n#define GPIO_ODR_OD1_Pos                 (1U)\n#define GPIO_ODR_OD1_Msk                 (0x1U << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */\n#define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk\n#define GPIO_ODR_OD2_Pos                 (2U)\n#define GPIO_ODR_OD2_Msk                 (0x1U << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */\n#define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk\n#define GPIO_ODR_OD3_Pos                 (3U)\n#define GPIO_ODR_OD3_Msk                 (0x1U << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */\n#define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk\n#define GPIO_ODR_OD4_Pos                 (4U)\n#define GPIO_ODR_OD4_Msk                 (0x1U << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */\n#define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk\n#define GPIO_ODR_OD5_Pos                 (5U)\n#define GPIO_ODR_OD5_Msk                 (0x1U << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */\n#define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk\n#define GPIO_ODR_OD6_Pos                 (6U)\n#define GPIO_ODR_OD6_Msk                 (0x1U << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */\n#define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk\n#define GPIO_ODR_OD7_Pos                 (7U)\n#define GPIO_ODR_OD7_Msk                 (0x1U << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */\n#define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk\n#define GPIO_ODR_OD8_Pos                 (8U)\n#define GPIO_ODR_OD8_Msk                 (0x1U << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */\n#define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk\n#define GPIO_ODR_OD9_Pos                 (9U)\n#define GPIO_ODR_OD9_Msk                 (0x1U << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */\n#define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk\n#define GPIO_ODR_OD10_Pos                (10U)\n#define GPIO_ODR_OD10_Msk                (0x1U << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */\n#define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk\n#define GPIO_ODR_OD11_Pos                (11U)\n#define GPIO_ODR_OD11_Msk                (0x1U << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */\n#define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk\n#define GPIO_ODR_OD12_Pos                (12U)\n#define GPIO_ODR_OD12_Msk                (0x1U << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */\n#define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk\n#define GPIO_ODR_OD13_Pos                (13U)\n#define GPIO_ODR_OD13_Msk                (0x1U << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */\n#define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk\n#define GPIO_ODR_OD14_Pos                (14U)\n#define GPIO_ODR_OD14_Msk                (0x1U << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */\n#define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk\n#define GPIO_ODR_OD15_Pos                (15U)\n#define GPIO_ODR_OD15_Msk                (0x1U << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */\n#define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk\n/* Legacy defines */\n#define GPIO_ODR_ODR_0                       GPIO_ODR_OD0\n#define GPIO_ODR_ODR_1                       GPIO_ODR_OD1\n#define GPIO_ODR_ODR_2                       GPIO_ODR_OD2\n#define GPIO_ODR_ODR_3                       GPIO_ODR_OD3\n#define GPIO_ODR_ODR_4                       GPIO_ODR_OD4\n#define GPIO_ODR_ODR_5                       GPIO_ODR_OD5\n#define GPIO_ODR_ODR_6                       GPIO_ODR_OD6\n#define GPIO_ODR_ODR_7                       GPIO_ODR_OD7\n#define GPIO_ODR_ODR_8                       GPIO_ODR_OD8\n#define GPIO_ODR_ODR_9                       GPIO_ODR_OD9\n#define GPIO_ODR_ODR_10                      GPIO_ODR_OD10\n#define GPIO_ODR_ODR_11                      GPIO_ODR_OD11\n#define GPIO_ODR_ODR_12                      GPIO_ODR_OD12\n#define GPIO_ODR_ODR_13                      GPIO_ODR_OD13\n#define GPIO_ODR_ODR_14                      GPIO_ODR_OD14\n#define GPIO_ODR_ODR_15                      GPIO_ODR_OD15\n\n/******************  Bits definition for GPIO_BSRR register  ******************/\n#define GPIO_BSRR_BS0_Pos                (0U)\n#define GPIO_BSRR_BS0_Msk                (0x1U << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */\n#define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk\n#define GPIO_BSRR_BS1_Pos                (1U)\n#define GPIO_BSRR_BS1_Msk                (0x1U << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */\n#define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk\n#define GPIO_BSRR_BS2_Pos                (2U)\n#define GPIO_BSRR_BS2_Msk                (0x1U << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */\n#define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk\n#define GPIO_BSRR_BS3_Pos                (3U)\n#define GPIO_BSRR_BS3_Msk                (0x1U << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */\n#define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk\n#define GPIO_BSRR_BS4_Pos                (4U)\n#define GPIO_BSRR_BS4_Msk                (0x1U << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */\n#define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk\n#define GPIO_BSRR_BS5_Pos                (5U)\n#define GPIO_BSRR_BS5_Msk                (0x1U << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */\n#define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk\n#define GPIO_BSRR_BS6_Pos                (6U)\n#define GPIO_BSRR_BS6_Msk                (0x1U << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */\n#define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk\n#define GPIO_BSRR_BS7_Pos                (7U)\n#define GPIO_BSRR_BS7_Msk                (0x1U << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */\n#define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk\n#define GPIO_BSRR_BS8_Pos                (8U)\n#define GPIO_BSRR_BS8_Msk                (0x1U << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */\n#define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk\n#define GPIO_BSRR_BS9_Pos                (9U)\n#define GPIO_BSRR_BS9_Msk                (0x1U << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */\n#define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk\n#define GPIO_BSRR_BS10_Pos               (10U)\n#define GPIO_BSRR_BS10_Msk               (0x1U << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */\n#define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk\n#define GPIO_BSRR_BS11_Pos               (11U)\n#define GPIO_BSRR_BS11_Msk               (0x1U << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */\n#define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk\n#define GPIO_BSRR_BS12_Pos               (12U)\n#define GPIO_BSRR_BS12_Msk               (0x1U << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */\n#define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk\n#define GPIO_BSRR_BS13_Pos               (13U)\n#define GPIO_BSRR_BS13_Msk               (0x1U << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */\n#define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk\n#define GPIO_BSRR_BS14_Pos               (14U)\n#define GPIO_BSRR_BS14_Msk               (0x1U << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */\n#define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk\n#define GPIO_BSRR_BS15_Pos               (15U)\n#define GPIO_BSRR_BS15_Msk               (0x1U << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */\n#define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk\n#define GPIO_BSRR_BR0_Pos                (16U)\n#define GPIO_BSRR_BR0_Msk                (0x1U << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */\n#define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk\n#define GPIO_BSRR_BR1_Pos                (17U)\n#define GPIO_BSRR_BR1_Msk                (0x1U << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */\n#define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk\n#define GPIO_BSRR_BR2_Pos                (18U)\n#define GPIO_BSRR_BR2_Msk                (0x1U << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */\n#define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk\n#define GPIO_BSRR_BR3_Pos                (19U)\n#define GPIO_BSRR_BR3_Msk                (0x1U << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */\n#define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk\n#define GPIO_BSRR_BR4_Pos                (20U)\n#define GPIO_BSRR_BR4_Msk                (0x1U << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */\n#define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk\n#define GPIO_BSRR_BR5_Pos                (21U)\n#define GPIO_BSRR_BR5_Msk                (0x1U << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */\n#define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk\n#define GPIO_BSRR_BR6_Pos                (22U)\n#define GPIO_BSRR_BR6_Msk                (0x1U << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */\n#define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk\n#define GPIO_BSRR_BR7_Pos                (23U)\n#define GPIO_BSRR_BR7_Msk                (0x1U << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */\n#define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk\n#define GPIO_BSRR_BR8_Pos                (24U)\n#define GPIO_BSRR_BR8_Msk                (0x1U << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */\n#define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk\n#define GPIO_BSRR_BR9_Pos                (25U)\n#define GPIO_BSRR_BR9_Msk                (0x1U << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */\n#define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk\n#define GPIO_BSRR_BR10_Pos               (26U)\n#define GPIO_BSRR_BR10_Msk               (0x1U << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */\n#define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk\n#define GPIO_BSRR_BR11_Pos               (27U)\n#define GPIO_BSRR_BR11_Msk               (0x1U << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */\n#define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk\n#define GPIO_BSRR_BR12_Pos               (28U)\n#define GPIO_BSRR_BR12_Msk               (0x1U << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */\n#define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk\n#define GPIO_BSRR_BR13_Pos               (29U)\n#define GPIO_BSRR_BR13_Msk               (0x1U << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */\n#define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk\n#define GPIO_BSRR_BR14_Pos               (30U)\n#define GPIO_BSRR_BR14_Msk               (0x1U << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */\n#define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk\n#define GPIO_BSRR_BR15_Pos               (31U)\n#define GPIO_BSRR_BR15_Msk               (0x1U << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */\n#define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk\n\n/* Legacy defines */\n#define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0\n#define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1\n#define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2\n#define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3\n#define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4\n#define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5\n#define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6\n#define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7\n#define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8\n#define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9\n#define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10\n#define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11\n#define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12\n#define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13\n#define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14\n#define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15\n#define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0\n#define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1\n#define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2\n#define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3\n#define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4\n#define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5\n#define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6\n#define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7\n#define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8\n#define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9\n#define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10\n#define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11\n#define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12\n#define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13\n#define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14\n#define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15\n/****************** Bit definition for GPIO_LCKR register *********************/\n#define GPIO_LCKR_LCK0_Pos               (0U)\n#define GPIO_LCKR_LCK0_Msk               (0x1U << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */\n#define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk\n#define GPIO_LCKR_LCK1_Pos               (1U)\n#define GPIO_LCKR_LCK1_Msk               (0x1U << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */\n#define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk\n#define GPIO_LCKR_LCK2_Pos               (2U)\n#define GPIO_LCKR_LCK2_Msk               (0x1U << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */\n#define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk\n#define GPIO_LCKR_LCK3_Pos               (3U)\n#define GPIO_LCKR_LCK3_Msk               (0x1U << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */\n#define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk\n#define GPIO_LCKR_LCK4_Pos               (4U)\n#define GPIO_LCKR_LCK4_Msk               (0x1U << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */\n#define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk\n#define GPIO_LCKR_LCK5_Pos               (5U)\n#define GPIO_LCKR_LCK5_Msk               (0x1U << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */\n#define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk\n#define GPIO_LCKR_LCK6_Pos               (6U)\n#define GPIO_LCKR_LCK6_Msk               (0x1U << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */\n#define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk\n#define GPIO_LCKR_LCK7_Pos               (7U)\n#define GPIO_LCKR_LCK7_Msk               (0x1U << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */\n#define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk\n#define GPIO_LCKR_LCK8_Pos               (8U)\n#define GPIO_LCKR_LCK8_Msk               (0x1U << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */\n#define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk\n#define GPIO_LCKR_LCK9_Pos               (9U)\n#define GPIO_LCKR_LCK9_Msk               (0x1U << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */\n#define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk\n#define GPIO_LCKR_LCK10_Pos              (10U)\n#define GPIO_LCKR_LCK10_Msk              (0x1U << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */\n#define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk\n#define GPIO_LCKR_LCK11_Pos              (11U)\n#define GPIO_LCKR_LCK11_Msk              (0x1U << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */\n#define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk\n#define GPIO_LCKR_LCK12_Pos              (12U)\n#define GPIO_LCKR_LCK12_Msk              (0x1U << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */\n#define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk\n#define GPIO_LCKR_LCK13_Pos              (13U)\n#define GPIO_LCKR_LCK13_Msk              (0x1U << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */\n#define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk\n#define GPIO_LCKR_LCK14_Pos              (14U)\n#define GPIO_LCKR_LCK14_Msk              (0x1U << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */\n#define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk\n#define GPIO_LCKR_LCK15_Pos              (15U)\n#define GPIO_LCKR_LCK15_Msk              (0x1U << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */\n#define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk\n#define GPIO_LCKR_LCKK_Pos               (16U)\n#define GPIO_LCKR_LCKK_Msk               (0x1U << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */\n#define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk\n/****************** Bit definition for GPIO_AFRL register *********************/\n#define GPIO_AFRL_AFSEL0_Pos             (0U)\n#define GPIO_AFRL_AFSEL0_Msk             (0xFU << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk\n#define GPIO_AFRL_AFSEL0_0               (0x1U << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRL_AFSEL0_1               (0x2U << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRL_AFSEL0_2               (0x4U << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRL_AFSEL0_3               (0x8U << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRL_AFSEL1_Pos             (4U)\n#define GPIO_AFRL_AFSEL1_Msk             (0xFU << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk\n#define GPIO_AFRL_AFSEL1_0               (0x1U << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRL_AFSEL1_1               (0x2U << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRL_AFSEL1_2               (0x4U << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRL_AFSEL1_3               (0x8U << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRL_AFSEL2_Pos             (8U)\n#define GPIO_AFRL_AFSEL2_Msk             (0xFU << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */\n#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk\n#define GPIO_AFRL_AFSEL2_0               (0x1U << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */\n#define GPIO_AFRL_AFSEL2_1               (0x2U << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */\n#define GPIO_AFRL_AFSEL2_2               (0x4U << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */\n#define GPIO_AFRL_AFSEL2_3               (0x8U << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */\n#define GPIO_AFRL_AFSEL3_Pos             (12U)\n#define GPIO_AFRL_AFSEL3_Msk             (0xFU << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */\n#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk\n#define GPIO_AFRL_AFSEL3_0               (0x1U << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */\n#define GPIO_AFRL_AFSEL3_1               (0x2U << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */\n#define GPIO_AFRL_AFSEL3_2               (0x4U << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */\n#define GPIO_AFRL_AFSEL3_3               (0x8U << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */\n#define GPIO_AFRL_AFSEL4_Pos             (16U)\n#define GPIO_AFRL_AFSEL4_Msk             (0xFU << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */\n#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk\n#define GPIO_AFRL_AFSEL4_0               (0x1U << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */\n#define GPIO_AFRL_AFSEL4_1               (0x2U << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */\n#define GPIO_AFRL_AFSEL4_2               (0x4U << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */\n#define GPIO_AFRL_AFSEL4_3               (0x8U << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */\n#define GPIO_AFRL_AFSEL5_Pos             (20U)\n#define GPIO_AFRL_AFSEL5_Msk             (0xFU << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */\n#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk\n#define GPIO_AFRL_AFSEL5_0               (0x1U << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */\n#define GPIO_AFRL_AFSEL5_1               (0x2U << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */\n#define GPIO_AFRL_AFSEL5_2               (0x4U << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */\n#define GPIO_AFRL_AFSEL5_3               (0x8U << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */\n#define GPIO_AFRL_AFSEL6_Pos             (24U)\n#define GPIO_AFRL_AFSEL6_Msk             (0xFU << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */\n#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk\n#define GPIO_AFRL_AFSEL6_0               (0x1U << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */\n#define GPIO_AFRL_AFSEL6_1               (0x2U << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */\n#define GPIO_AFRL_AFSEL6_2               (0x4U << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */\n#define GPIO_AFRL_AFSEL6_3               (0x8U << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */\n#define GPIO_AFRL_AFSEL7_Pos             (28U)\n#define GPIO_AFRL_AFSEL7_Msk             (0xFU << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */\n#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk\n#define GPIO_AFRL_AFSEL7_0               (0x1U << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */\n#define GPIO_AFRL_AFSEL7_1               (0x2U << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */\n#define GPIO_AFRL_AFSEL7_2               (0x4U << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */\n#define GPIO_AFRL_AFSEL7_3               (0x8U << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0\n#define GPIO_AFRL_AFRL0_0                    GPIO_AFRL_AFSEL0_0\n#define GPIO_AFRL_AFRL0_1                    GPIO_AFRL_AFSEL0_1\n#define GPIO_AFRL_AFRL0_2                    GPIO_AFRL_AFSEL0_2\n#define GPIO_AFRL_AFRL0_3                    GPIO_AFRL_AFSEL0_3\n#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1\n#define GPIO_AFRL_AFRL1_0                    GPIO_AFRL_AFSEL1_0\n#define GPIO_AFRL_AFRL1_1                    GPIO_AFRL_AFSEL1_1\n#define GPIO_AFRL_AFRL1_2                    GPIO_AFRL_AFSEL1_2\n#define GPIO_AFRL_AFRL1_3                    GPIO_AFRL_AFSEL1_3\n#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2\n#define GPIO_AFRL_AFRL2_0                    GPIO_AFRL_AFSEL2_0\n#define GPIO_AFRL_AFRL2_1                    GPIO_AFRL_AFSEL2_1\n#define GPIO_AFRL_AFRL2_2                    GPIO_AFRL_AFSEL2_2\n#define GPIO_AFRL_AFRL2_3                    GPIO_AFRL_AFSEL2_3\n#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3\n#define GPIO_AFRL_AFRL3_0                    GPIO_AFRL_AFSEL3_0\n#define GPIO_AFRL_AFRL3_1                    GPIO_AFRL_AFSEL3_1\n#define GPIO_AFRL_AFRL3_2                    GPIO_AFRL_AFSEL3_2\n#define GPIO_AFRL_AFRL3_3                    GPIO_AFRL_AFSEL3_3\n#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4\n#define GPIO_AFRL_AFRL4_0                    GPIO_AFRL_AFSEL4_0\n#define GPIO_AFRL_AFRL4_1                    GPIO_AFRL_AFSEL4_1\n#define GPIO_AFRL_AFRL4_2                    GPIO_AFRL_AFSEL4_2\n#define GPIO_AFRL_AFRL4_3                    GPIO_AFRL_AFSEL4_3\n#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5\n#define GPIO_AFRL_AFRL5_0                    GPIO_AFRL_AFSEL5_0\n#define GPIO_AFRL_AFRL5_1                    GPIO_AFRL_AFSEL5_1\n#define GPIO_AFRL_AFRL5_2                    GPIO_AFRL_AFSEL5_2\n#define GPIO_AFRL_AFRL5_3                    GPIO_AFRL_AFSEL5_3\n#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6\n#define GPIO_AFRL_AFRL6_0                    GPIO_AFRL_AFSEL6_0\n#define GPIO_AFRL_AFRL6_1                    GPIO_AFRL_AFSEL6_1\n#define GPIO_AFRL_AFRL6_2                    GPIO_AFRL_AFSEL6_2\n#define GPIO_AFRL_AFRL6_3                    GPIO_AFRL_AFSEL6_3\n#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7\n#define GPIO_AFRL_AFRL7_0                    GPIO_AFRL_AFSEL7_0\n#define GPIO_AFRL_AFRL7_1                    GPIO_AFRL_AFSEL7_1\n#define GPIO_AFRL_AFRL7_2                    GPIO_AFRL_AFSEL7_2\n#define GPIO_AFRL_AFRL7_3                    GPIO_AFRL_AFSEL7_3\n\n/****************** Bit definition for GPIO_AFRH register *********************/\n#define GPIO_AFRH_AFSEL8_Pos             (0U)\n#define GPIO_AFRH_AFSEL8_Msk             (0xFU << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk\n#define GPIO_AFRH_AFSEL8_0               (0x1U << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRH_AFSEL8_1               (0x2U << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRH_AFSEL8_2               (0x4U << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRH_AFSEL8_3               (0x8U << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRH_AFSEL9_Pos             (4U)\n#define GPIO_AFRH_AFSEL9_Msk             (0xFU << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk\n#define GPIO_AFRH_AFSEL9_0               (0x1U << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRH_AFSEL9_1               (0x2U << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRH_AFSEL9_2               (0x4U << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRH_AFSEL9_3               (0x8U << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRH_AFSEL10_Pos            (8U)\n#define GPIO_AFRH_AFSEL10_Msk            (0xFU << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */\n#define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk\n#define GPIO_AFRH_AFSEL10_0              (0x1U << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */\n#define GPIO_AFRH_AFSEL10_1              (0x2U << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */\n#define GPIO_AFRH_AFSEL10_2              (0x4U << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */\n#define GPIO_AFRH_AFSEL10_3              (0x8U << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */\n#define GPIO_AFRH_AFSEL11_Pos            (12U)\n#define GPIO_AFRH_AFSEL11_Msk            (0xFU << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */\n#define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk\n#define GPIO_AFRH_AFSEL11_0              (0x1U << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */\n#define GPIO_AFRH_AFSEL11_1              (0x2U << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */\n#define GPIO_AFRH_AFSEL11_2              (0x4U << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */\n#define GPIO_AFRH_AFSEL11_3              (0x8U << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */\n#define GPIO_AFRH_AFSEL12_Pos            (16U)\n#define GPIO_AFRH_AFSEL12_Msk            (0xFU << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */\n#define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk\n#define GPIO_AFRH_AFSEL12_0              (0x1U << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */\n#define GPIO_AFRH_AFSEL12_1              (0x2U << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */\n#define GPIO_AFRH_AFSEL12_2              (0x4U << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */\n#define GPIO_AFRH_AFSEL12_3              (0x8U << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */\n#define GPIO_AFRH_AFSEL13_Pos            (20U)\n#define GPIO_AFRH_AFSEL13_Msk            (0xFU << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */\n#define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk\n#define GPIO_AFRH_AFSEL13_0              (0x1U << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */\n#define GPIO_AFRH_AFSEL13_1              (0x2U << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */\n#define GPIO_AFRH_AFSEL13_2              (0x4U << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */\n#define GPIO_AFRH_AFSEL13_3              (0x8U << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */\n#define GPIO_AFRH_AFSEL14_Pos            (24U)\n#define GPIO_AFRH_AFSEL14_Msk            (0xFU << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */\n#define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk\n#define GPIO_AFRH_AFSEL14_0              (0x1U << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */\n#define GPIO_AFRH_AFSEL14_1              (0x2U << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */\n#define GPIO_AFRH_AFSEL14_2              (0x4U << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */\n#define GPIO_AFRH_AFSEL14_3              (0x8U << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */\n#define GPIO_AFRH_AFSEL15_Pos            (28U)\n#define GPIO_AFRH_AFSEL15_Msk            (0xFU << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */\n#define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk\n#define GPIO_AFRH_AFSEL15_0              (0x1U << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */\n#define GPIO_AFRH_AFSEL15_1              (0x2U << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */\n#define GPIO_AFRH_AFSEL15_2              (0x4U << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */\n#define GPIO_AFRH_AFSEL15_3              (0x8U << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8\n#define GPIO_AFRH_AFRH0_0                    GPIO_AFRH_AFSEL8_0\n#define GPIO_AFRH_AFRH0_1                    GPIO_AFRH_AFSEL8_1\n#define GPIO_AFRH_AFRH0_2                    GPIO_AFRH_AFSEL8_2\n#define GPIO_AFRH_AFRH0_3                    GPIO_AFRH_AFSEL8_3\n#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9\n#define GPIO_AFRH_AFRH1_0                    GPIO_AFRH_AFSEL9_0\n#define GPIO_AFRH_AFRH1_1                    GPIO_AFRH_AFSEL9_1\n#define GPIO_AFRH_AFRH1_2                    GPIO_AFRH_AFSEL9_2\n#define GPIO_AFRH_AFRH1_3                    GPIO_AFRH_AFSEL9_3\n#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10\n#define GPIO_AFRH_AFRH2_0                    GPIO_AFRH_AFSEL10_0\n#define GPIO_AFRH_AFRH2_1                    GPIO_AFRH_AFSEL10_1\n#define GPIO_AFRH_AFRH2_2                    GPIO_AFRH_AFSEL10_2\n#define GPIO_AFRH_AFRH2_3                    GPIO_AFRH_AFSEL10_3\n#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11\n#define GPIO_AFRH_AFRH3_0                    GPIO_AFRH_AFSEL11_0\n#define GPIO_AFRH_AFRH3_1                    GPIO_AFRH_AFSEL11_1\n#define GPIO_AFRH_AFRH3_2                    GPIO_AFRH_AFSEL11_2\n#define GPIO_AFRH_AFRH3_3                    GPIO_AFRH_AFSEL11_3\n#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12\n#define GPIO_AFRH_AFRH4_0                    GPIO_AFRH_AFSEL12_0\n#define GPIO_AFRH_AFRH4_1                    GPIO_AFRH_AFSEL12_1\n#define GPIO_AFRH_AFRH4_2                    GPIO_AFRH_AFSEL12_2\n#define GPIO_AFRH_AFRH4_3                    GPIO_AFRH_AFSEL12_3\n#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13\n#define GPIO_AFRH_AFRH5_0                    GPIO_AFRH_AFSEL13_0\n#define GPIO_AFRH_AFRH5_1                    GPIO_AFRH_AFSEL13_1\n#define GPIO_AFRH_AFRH5_2                    GPIO_AFRH_AFSEL13_2\n#define GPIO_AFRH_AFRH5_3                    GPIO_AFRH_AFSEL13_3\n#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14\n#define GPIO_AFRH_AFRH6_0                    GPIO_AFRH_AFSEL14_0\n#define GPIO_AFRH_AFRH6_1                    GPIO_AFRH_AFSEL14_1\n#define GPIO_AFRH_AFRH6_2                    GPIO_AFRH_AFSEL14_2\n#define GPIO_AFRH_AFRH6_3                    GPIO_AFRH_AFSEL14_3\n#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15\n#define GPIO_AFRH_AFRH7_0                    GPIO_AFRH_AFSEL15_0\n#define GPIO_AFRH_AFRH7_1                    GPIO_AFRH_AFSEL15_1\n#define GPIO_AFRH_AFRH7_2                    GPIO_AFRH_AFSEL15_2\n#define GPIO_AFRH_AFRH7_3                    GPIO_AFRH_AFSEL15_3\n\n/******************  Bits definition for GPIO_BRR register  ******************/\n#define GPIO_BRR_BR0_Pos                 (0U)\n#define GPIO_BRR_BR0_Msk                 (0x1U << GPIO_BRR_BR0_Pos)            /*!< 0x00000001 */\n#define GPIO_BRR_BR0                     GPIO_BRR_BR0_Msk\n#define GPIO_BRR_BR1_Pos                 (1U)\n#define GPIO_BRR_BR1_Msk                 (0x1U << GPIO_BRR_BR1_Pos)            /*!< 0x00000002 */\n#define GPIO_BRR_BR1                     GPIO_BRR_BR1_Msk\n#define GPIO_BRR_BR2_Pos                 (2U)\n#define GPIO_BRR_BR2_Msk                 (0x1U << GPIO_BRR_BR2_Pos)            /*!< 0x00000004 */\n#define GPIO_BRR_BR2                     GPIO_BRR_BR2_Msk\n#define GPIO_BRR_BR3_Pos                 (3U)\n#define GPIO_BRR_BR3_Msk                 (0x1U << GPIO_BRR_BR3_Pos)            /*!< 0x00000008 */\n#define GPIO_BRR_BR3                     GPIO_BRR_BR3_Msk\n#define GPIO_BRR_BR4_Pos                 (4U)\n#define GPIO_BRR_BR4_Msk                 (0x1U << GPIO_BRR_BR4_Pos)            /*!< 0x00000010 */\n#define GPIO_BRR_BR4                     GPIO_BRR_BR4_Msk\n#define GPIO_BRR_BR5_Pos                 (5U)\n#define GPIO_BRR_BR5_Msk                 (0x1U << GPIO_BRR_BR5_Pos)            /*!< 0x00000020 */\n#define GPIO_BRR_BR5                     GPIO_BRR_BR5_Msk\n#define GPIO_BRR_BR6_Pos                 (6U)\n#define GPIO_BRR_BR6_Msk                 (0x1U << GPIO_BRR_BR6_Pos)            /*!< 0x00000040 */\n#define GPIO_BRR_BR6                     GPIO_BRR_BR6_Msk\n#define GPIO_BRR_BR7_Pos                 (7U)\n#define GPIO_BRR_BR7_Msk                 (0x1U << GPIO_BRR_BR7_Pos)            /*!< 0x00000080 */\n#define GPIO_BRR_BR7                     GPIO_BRR_BR7_Msk\n#define GPIO_BRR_BR8_Pos                 (8U)\n#define GPIO_BRR_BR8_Msk                 (0x1U << GPIO_BRR_BR8_Pos)            /*!< 0x00000100 */\n#define GPIO_BRR_BR8                     GPIO_BRR_BR8_Msk\n#define GPIO_BRR_BR9_Pos                 (9U)\n#define GPIO_BRR_BR9_Msk                 (0x1U << GPIO_BRR_BR9_Pos)            /*!< 0x00000200 */\n#define GPIO_BRR_BR9                     GPIO_BRR_BR9_Msk\n#define GPIO_BRR_BR10_Pos                (10U)\n#define GPIO_BRR_BR10_Msk                (0x1U << GPIO_BRR_BR10_Pos)           /*!< 0x00000400 */\n#define GPIO_BRR_BR10                    GPIO_BRR_BR10_Msk\n#define GPIO_BRR_BR11_Pos                (11U)\n#define GPIO_BRR_BR11_Msk                (0x1U << GPIO_BRR_BR11_Pos)           /*!< 0x00000800 */\n#define GPIO_BRR_BR11                    GPIO_BRR_BR11_Msk\n#define GPIO_BRR_BR12_Pos                (12U)\n#define GPIO_BRR_BR12_Msk                (0x1U << GPIO_BRR_BR12_Pos)           /*!< 0x00001000 */\n#define GPIO_BRR_BR12                    GPIO_BRR_BR12_Msk\n#define GPIO_BRR_BR13_Pos                (13U)\n#define GPIO_BRR_BR13_Msk                (0x1U << GPIO_BRR_BR13_Pos)           /*!< 0x00002000 */\n#define GPIO_BRR_BR13                    GPIO_BRR_BR13_Msk\n#define GPIO_BRR_BR14_Pos                (14U)\n#define GPIO_BRR_BR14_Msk                (0x1U << GPIO_BRR_BR14_Pos)           /*!< 0x00004000 */\n#define GPIO_BRR_BR14                    GPIO_BRR_BR14_Msk\n#define GPIO_BRR_BR15_Pos                (15U)\n#define GPIO_BRR_BR15_Msk                (0x1U << GPIO_BRR_BR15_Pos)           /*!< 0x00008000 */\n#define GPIO_BRR_BR15                    GPIO_BRR_BR15_Msk\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Inter-integrated Circuit Interface                    */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for I2C_CR1 register  ********************/\n#define I2C_CR1_PE_Pos            (0U)\n#define I2C_CR1_PE_Msk            (0x1U << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */\n#define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */\n#define I2C_CR1_SMBUS_Pos         (1U)\n#define I2C_CR1_SMBUS_Msk         (0x1U << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */\n#define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */\n#define I2C_CR1_SMBTYPE_Pos       (3U)\n#define I2C_CR1_SMBTYPE_Msk       (0x1U << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */\n#define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */\n#define I2C_CR1_ENARP_Pos         (4U)\n#define I2C_CR1_ENARP_Msk         (0x1U << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */\n#define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */\n#define I2C_CR1_ENPEC_Pos         (5U)\n#define I2C_CR1_ENPEC_Msk         (0x1U << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */\n#define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */\n#define I2C_CR1_ENGC_Pos          (6U)\n#define I2C_CR1_ENGC_Msk          (0x1U << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */\n#define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */\n#define I2C_CR1_NOSTRETCH_Pos     (7U)\n#define I2C_CR1_NOSTRETCH_Msk     (0x1U << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */\n#define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */\n#define I2C_CR1_START_Pos         (8U)\n#define I2C_CR1_START_Msk         (0x1U << I2C_CR1_START_Pos)                  /*!< 0x00000100 */\n#define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */\n#define I2C_CR1_STOP_Pos          (9U)\n#define I2C_CR1_STOP_Msk          (0x1U << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */\n#define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */\n#define I2C_CR1_ACK_Pos           (10U)\n#define I2C_CR1_ACK_Msk           (0x1U << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */\n#define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */\n#define I2C_CR1_POS_Pos           (11U)\n#define I2C_CR1_POS_Msk           (0x1U << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */\n#define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */\n#define I2C_CR1_PEC_Pos           (12U)\n#define I2C_CR1_PEC_Msk           (0x1U << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */\n#define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */\n#define I2C_CR1_ALERT_Pos         (13U)\n#define I2C_CR1_ALERT_Msk         (0x1U << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */\n#define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */\n#define I2C_CR1_SWRST_Pos         (15U)\n#define I2C_CR1_SWRST_Msk         (0x1U << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */\n#define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */\n\n/*******************  Bit definition for I2C_CR2 register  ********************/\n#define I2C_CR2_FREQ_Pos          (0U)\n#define I2C_CR2_FREQ_Msk          (0x3FU << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */\n#define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */\n#define I2C_CR2_FREQ_0            (0x01U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */\n#define I2C_CR2_FREQ_1            (0x02U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */\n#define I2C_CR2_FREQ_2            (0x04U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */\n#define I2C_CR2_FREQ_3            (0x08U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */\n#define I2C_CR2_FREQ_4            (0x10U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */\n#define I2C_CR2_FREQ_5            (0x20U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */\n\n#define I2C_CR2_ITERREN_Pos       (8U)\n#define I2C_CR2_ITERREN_Msk       (0x1U << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */\n#define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */\n#define I2C_CR2_ITEVTEN_Pos       (9U)\n#define I2C_CR2_ITEVTEN_Msk       (0x1U << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */\n#define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */\n#define I2C_CR2_ITBUFEN_Pos       (10U)\n#define I2C_CR2_ITBUFEN_Msk       (0x1U << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */\n#define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */\n#define I2C_CR2_DMAEN_Pos         (11U)\n#define I2C_CR2_DMAEN_Msk         (0x1U << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */\n#define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */\n#define I2C_CR2_LAST_Pos          (12U)\n#define I2C_CR2_LAST_Msk          (0x1U << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */\n#define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */\n\n/*******************  Bit definition for I2C_OAR1 register  *******************/\n#define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */\n#define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */\n\n#define I2C_OAR1_ADD0_Pos         (0U)\n#define I2C_OAR1_ADD0_Msk         (0x1U << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */\n#define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */\n#define I2C_OAR1_ADD1_Pos         (1U)\n#define I2C_OAR1_ADD1_Msk         (0x1U << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */\n#define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */\n#define I2C_OAR1_ADD2_Pos         (2U)\n#define I2C_OAR1_ADD2_Msk         (0x1U << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */\n#define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */\n#define I2C_OAR1_ADD3_Pos         (3U)\n#define I2C_OAR1_ADD3_Msk         (0x1U << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */\n#define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */\n#define I2C_OAR1_ADD4_Pos         (4U)\n#define I2C_OAR1_ADD4_Msk         (0x1U << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */\n#define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */\n#define I2C_OAR1_ADD5_Pos         (5U)\n#define I2C_OAR1_ADD5_Msk         (0x1U << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */\n#define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */\n#define I2C_OAR1_ADD6_Pos         (6U)\n#define I2C_OAR1_ADD6_Msk         (0x1U << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */\n#define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */\n#define I2C_OAR1_ADD7_Pos         (7U)\n#define I2C_OAR1_ADD7_Msk         (0x1U << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */\n#define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */\n#define I2C_OAR1_ADD8_Pos         (8U)\n#define I2C_OAR1_ADD8_Msk         (0x1U << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */\n#define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */\n#define I2C_OAR1_ADD9_Pos         (9U)\n#define I2C_OAR1_ADD9_Msk         (0x1U << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */\n#define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */\n\n#define I2C_OAR1_ADDMODE_Pos      (15U)\n#define I2C_OAR1_ADDMODE_Msk      (0x1U << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */\n#define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */\n\n/*******************  Bit definition for I2C_OAR2 register  *******************/\n#define I2C_OAR2_ENDUAL_Pos       (0U)\n#define I2C_OAR2_ENDUAL_Msk       (0x1U << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */\n#define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */\n#define I2C_OAR2_ADD2_Pos         (1U)\n#define I2C_OAR2_ADD2_Msk         (0x7FU << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */\n#define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */\n\n/********************  Bit definition for I2C_DR register  ********************/\n#define I2C_DR_DR_Pos             (0U)\n#define I2C_DR_DR_Msk             (0xFFU << I2C_DR_DR_Pos)                     /*!< 0x000000FF */\n#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */\n\n/*******************  Bit definition for I2C_SR1 register  ********************/\n#define I2C_SR1_SB_Pos            (0U)\n#define I2C_SR1_SB_Msk            (0x1U << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */\n#define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */\n#define I2C_SR1_ADDR_Pos          (1U)\n#define I2C_SR1_ADDR_Msk          (0x1U << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */\n#define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */\n#define I2C_SR1_BTF_Pos           (2U)\n#define I2C_SR1_BTF_Msk           (0x1U << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */\n#define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */\n#define I2C_SR1_ADD10_Pos         (3U)\n#define I2C_SR1_ADD10_Msk         (0x1U << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */\n#define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */\n#define I2C_SR1_STOPF_Pos         (4U)\n#define I2C_SR1_STOPF_Msk         (0x1U << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */\n#define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */\n#define I2C_SR1_RXNE_Pos          (6U)\n#define I2C_SR1_RXNE_Msk          (0x1U << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */\n#define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */\n#define I2C_SR1_TXE_Pos           (7U)\n#define I2C_SR1_TXE_Msk           (0x1U << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */\n#define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */\n#define I2C_SR1_BERR_Pos          (8U)\n#define I2C_SR1_BERR_Msk          (0x1U << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */\n#define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */\n#define I2C_SR1_ARLO_Pos          (9U)\n#define I2C_SR1_ARLO_Msk          (0x1U << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */\n#define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */\n#define I2C_SR1_AF_Pos            (10U)\n#define I2C_SR1_AF_Msk            (0x1U << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */\n#define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */\n#define I2C_SR1_OVR_Pos           (11U)\n#define I2C_SR1_OVR_Msk           (0x1U << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */\n#define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */\n#define I2C_SR1_PECERR_Pos        (12U)\n#define I2C_SR1_PECERR_Msk        (0x1U << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */\n#define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */\n#define I2C_SR1_TIMEOUT_Pos       (14U)\n#define I2C_SR1_TIMEOUT_Msk       (0x1U << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */\n#define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */\n#define I2C_SR1_SMBALERT_Pos      (15U)\n#define I2C_SR1_SMBALERT_Msk      (0x1U << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */\n#define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */\n\n/*******************  Bit definition for I2C_SR2 register  ********************/\n#define I2C_SR2_MSL_Pos           (0U)\n#define I2C_SR2_MSL_Msk           (0x1U << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */\n#define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */\n#define I2C_SR2_BUSY_Pos          (1U)\n#define I2C_SR2_BUSY_Msk          (0x1U << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */\n#define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */\n#define I2C_SR2_TRA_Pos           (2U)\n#define I2C_SR2_TRA_Msk           (0x1U << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */\n#define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */\n#define I2C_SR2_GENCALL_Pos       (4U)\n#define I2C_SR2_GENCALL_Msk       (0x1U << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */\n#define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */\n#define I2C_SR2_SMBDEFAULT_Pos    (5U)\n#define I2C_SR2_SMBDEFAULT_Msk    (0x1U << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */\n#define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */\n#define I2C_SR2_SMBHOST_Pos       (6U)\n#define I2C_SR2_SMBHOST_Msk       (0x1U << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */\n#define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */\n#define I2C_SR2_DUALF_Pos         (7U)\n#define I2C_SR2_DUALF_Msk         (0x1U << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */\n#define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */\n#define I2C_SR2_PEC_Pos           (8U)\n#define I2C_SR2_PEC_Msk           (0xFFU << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */\n#define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */\n\n/*******************  Bit definition for I2C_CCR register  ********************/\n#define I2C_CCR_CCR_Pos           (0U)\n#define I2C_CCR_CCR_Msk           (0xFFFU << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */\n#define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */\n#define I2C_CCR_DUTY_Pos          (14U)\n#define I2C_CCR_DUTY_Msk          (0x1U << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */\n#define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */\n#define I2C_CCR_FS_Pos            (15U)\n#define I2C_CCR_FS_Msk            (0x1U << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */\n#define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */\n\n/******************  Bit definition for I2C_TRISE register  *******************/\n#define I2C_TRISE_TRISE_Pos       (0U)\n#define I2C_TRISE_TRISE_Msk       (0x3FU << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */\n#define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */\n\n/******************  Bit definition for I2C_FLTR register  *******************/\n#define I2C_FLTR_DNF_Pos          (0U)\n#define I2C_FLTR_DNF_Msk          (0xFU << I2C_FLTR_DNF_Pos)                   /*!< 0x0000000F */\n#define I2C_FLTR_DNF              I2C_FLTR_DNF_Msk                             /*!<Digital Noise Filter */\n#define I2C_FLTR_ANOFF_Pos        (4U)\n#define I2C_FLTR_ANOFF_Msk        (0x1U << I2C_FLTR_ANOFF_Pos)                 /*!< 0x00000010 */\n#define I2C_FLTR_ANOFF            I2C_FLTR_ANOFF_Msk                           /*!<Analog Noise Filter OFF */\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Independent WATCHDOG                             */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define IWDG_KR_KEY_Pos     (0U)\n#define IWDG_KR_KEY_Msk     (0xFFFFU << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */\n#define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */\n\n/*******************  Bit definition for IWDG_PR register  ********************/\n#define IWDG_PR_PR_Pos      (0U)\n#define IWDG_PR_PR_Msk      (0x7U << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */\n#define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */\n#define IWDG_PR_PR_0        (0x1U << IWDG_PR_PR_Pos)                           /*!< 0x01 */\n#define IWDG_PR_PR_1        (0x2U << IWDG_PR_PR_Pos)                           /*!< 0x02 */\n#define IWDG_PR_PR_2        (0x4U << IWDG_PR_PR_Pos)                           /*!< 0x04 */\n\n/*******************  Bit definition for IWDG_RLR register  *******************/\n#define IWDG_RLR_RL_Pos     (0U)\n#define IWDG_RLR_RL_Msk     (0xFFFU << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */\n#define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */\n\n/*******************  Bit definition for IWDG_SR register  ********************/\n#define IWDG_SR_PVU_Pos     (0U)\n#define IWDG_SR_PVU_Msk     (0x1U << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */\n#define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */\n#define IWDG_SR_RVU_Pos     (1U)\n#define IWDG_SR_RVU_Msk     (0x1U << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */\n#define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                      LCD-TFT Display Controller (LTDC)                     */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for LTDC_SSCR register  *****************/\n\n#define LTDC_SSCR_VSH_Pos            (0U)\n#define LTDC_SSCR_VSH_Msk            (0x7FFU << LTDC_SSCR_VSH_Pos)             /*!< 0x000007FF */\n#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height */\n#define LTDC_SSCR_HSW_Pos            (16U)\n#define LTDC_SSCR_HSW_Msk            (0xFFFU << LTDC_SSCR_HSW_Pos)             /*!< 0x0FFF0000 */\n#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */\n\n/********************  Bit definition for LTDC_BPCR register  *****************/\n\n#define LTDC_BPCR_AVBP_Pos           (0U)\n#define LTDC_BPCR_AVBP_Msk           (0x7FFU << LTDC_BPCR_AVBP_Pos)            /*!< 0x000007FF */\n#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch */\n#define LTDC_BPCR_AHBP_Pos           (16U)\n#define LTDC_BPCR_AHBP_Msk           (0xFFFU << LTDC_BPCR_AHBP_Pos)            /*!< 0x0FFF0000 */\n#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */\n\n/********************  Bit definition for LTDC_AWCR register  *****************/\n\n#define LTDC_AWCR_AAH_Pos            (0U)\n#define LTDC_AWCR_AAH_Msk            (0x7FFU << LTDC_AWCR_AAH_Pos)             /*!< 0x000007FF */\n#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */\n#define LTDC_AWCR_AAW_Pos            (16U)\n#define LTDC_AWCR_AAW_Msk            (0xFFFU << LTDC_AWCR_AAW_Pos)             /*!< 0x0FFF0000 */\n#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */\n\n/********************  Bit definition for LTDC_TWCR register  *****************/\n\n#define LTDC_TWCR_TOTALH_Pos         (0U)\n#define LTDC_TWCR_TOTALH_Msk         (0x7FFU << LTDC_TWCR_TOTALH_Pos)          /*!< 0x000007FF */\n#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */\n#define LTDC_TWCR_TOTALW_Pos         (16U)\n#define LTDC_TWCR_TOTALW_Msk         (0xFFFU << LTDC_TWCR_TOTALW_Pos)          /*!< 0x0FFF0000 */\n#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */\n\n/********************  Bit definition for LTDC_GCR register  ******************/\n\n#define LTDC_GCR_LTDCEN_Pos          (0U)\n#define LTDC_GCR_LTDCEN_Msk          (0x1U << LTDC_GCR_LTDCEN_Pos)             /*!< 0x00000001 */\n#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit */\n#define LTDC_GCR_DBW_Pos             (4U)\n#define LTDC_GCR_DBW_Msk             (0x7U << LTDC_GCR_DBW_Pos)                /*!< 0x00000070 */\n#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width */\n#define LTDC_GCR_DGW_Pos             (8U)\n#define LTDC_GCR_DGW_Msk             (0x7U << LTDC_GCR_DGW_Pos)                /*!< 0x00000700 */\n#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width */\n#define LTDC_GCR_DRW_Pos             (12U)\n#define LTDC_GCR_DRW_Msk             (0x7U << LTDC_GCR_DRW_Pos)                /*!< 0x00007000 */\n#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width */\n#define LTDC_GCR_DEN_Pos             (16U)\n#define LTDC_GCR_DEN_Msk             (0x1U << LTDC_GCR_DEN_Pos)                /*!< 0x00010000 */\n#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable */\n#define LTDC_GCR_PCPOL_Pos           (28U)\n#define LTDC_GCR_PCPOL_Msk           (0x1U << LTDC_GCR_PCPOL_Pos)              /*!< 0x10000000 */\n#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity */\n#define LTDC_GCR_DEPOL_Pos           (29U)\n#define LTDC_GCR_DEPOL_Msk           (0x1U << LTDC_GCR_DEPOL_Pos)              /*!< 0x20000000 */\n#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity */\n#define LTDC_GCR_VSPOL_Pos           (30U)\n#define LTDC_GCR_VSPOL_Msk           (0x1U << LTDC_GCR_VSPOL_Pos)              /*!< 0x40000000 */\n#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity */\n#define LTDC_GCR_HSPOL_Pos           (31U)\n#define LTDC_GCR_HSPOL_Msk           (0x1U << LTDC_GCR_HSPOL_Pos)              /*!< 0x80000000 */\n#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */\n\n/* Legacy defines */\n#define LTDC_GCR_DTEN                       LTDC_GCR_DEN\n\n/********************  Bit definition for LTDC_SRCR register  *****************/\n\n#define LTDC_SRCR_IMR_Pos            (0U)\n#define LTDC_SRCR_IMR_Msk            (0x1U << LTDC_SRCR_IMR_Pos)               /*!< 0x00000001 */\n#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload */\n#define LTDC_SRCR_VBR_Pos            (1U)\n#define LTDC_SRCR_VBR_Msk            (0x1U << LTDC_SRCR_VBR_Pos)               /*!< 0x00000002 */\n#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */\n\n/********************  Bit definition for LTDC_BCCR register  *****************/\n\n#define LTDC_BCCR_BCBLUE_Pos         (0U)\n#define LTDC_BCCR_BCBLUE_Msk         (0xFFU << LTDC_BCCR_BCBLUE_Pos)           /*!< 0x000000FF */\n#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value */\n#define LTDC_BCCR_BCGREEN_Pos        (8U)\n#define LTDC_BCCR_BCGREEN_Msk        (0xFFU << LTDC_BCCR_BCGREEN_Pos)          /*!< 0x0000FF00 */\n#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */\n#define LTDC_BCCR_BCRED_Pos          (16U)\n#define LTDC_BCCR_BCRED_Msk          (0xFFU << LTDC_BCCR_BCRED_Pos)            /*!< 0x00FF0000 */\n#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value */\n\n/********************  Bit definition for LTDC_IER register  ******************/\n\n#define LTDC_IER_LIE_Pos             (0U)\n#define LTDC_IER_LIE_Msk             (0x1U << LTDC_IER_LIE_Pos)                /*!< 0x00000001 */\n#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable */\n#define LTDC_IER_FUIE_Pos            (1U)\n#define LTDC_IER_FUIE_Msk            (0x1U << LTDC_IER_FUIE_Pos)               /*!< 0x00000002 */\n#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable */\n#define LTDC_IER_TERRIE_Pos          (2U)\n#define LTDC_IER_TERRIE_Msk          (0x1U << LTDC_IER_TERRIE_Pos)             /*!< 0x00000004 */\n#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable */\n#define LTDC_IER_RRIE_Pos            (3U)\n#define LTDC_IER_RRIE_Msk            (0x1U << LTDC_IER_RRIE_Pos)               /*!< 0x00000008 */\n#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */\n\n/********************  Bit definition for LTDC_ISR register  ******************/\n\n#define LTDC_ISR_LIF_Pos             (0U)\n#define LTDC_ISR_LIF_Msk             (0x1U << LTDC_ISR_LIF_Pos)                /*!< 0x00000001 */\n#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */\n#define LTDC_ISR_FUIF_Pos            (1U)\n#define LTDC_ISR_FUIF_Msk            (0x1U << LTDC_ISR_FUIF_Pos)               /*!< 0x00000002 */\n#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */\n#define LTDC_ISR_TERRIF_Pos          (2U)\n#define LTDC_ISR_TERRIF_Msk          (0x1U << LTDC_ISR_TERRIF_Pos)             /*!< 0x00000004 */\n#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */\n#define LTDC_ISR_RRIF_Pos            (3U)\n#define LTDC_ISR_RRIF_Msk            (0x1U << LTDC_ISR_RRIF_Pos)               /*!< 0x00000008 */\n#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */\n\n/********************  Bit definition for LTDC_ICR register  ******************/\n\n#define LTDC_ICR_CLIF_Pos            (0U)\n#define LTDC_ICR_CLIF_Msk            (0x1U << LTDC_ICR_CLIF_Pos)               /*!< 0x00000001 */\n#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */\n#define LTDC_ICR_CFUIF_Pos           (1U)\n#define LTDC_ICR_CFUIF_Msk           (0x1U << LTDC_ICR_CFUIF_Pos)              /*!< 0x00000002 */\n#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */\n#define LTDC_ICR_CTERRIF_Pos         (2U)\n#define LTDC_ICR_CTERRIF_Msk         (0x1U << LTDC_ICR_CTERRIF_Pos)            /*!< 0x00000004 */\n#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */\n#define LTDC_ICR_CRRIF_Pos           (3U)\n#define LTDC_ICR_CRRIF_Msk           (0x1U << LTDC_ICR_CRRIF_Pos)              /*!< 0x00000008 */\n#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */\n\n/********************  Bit definition for LTDC_LIPCR register  ****************/\n\n#define LTDC_LIPCR_LIPOS_Pos         (0U)\n#define LTDC_LIPCR_LIPOS_Msk         (0x7FFU << LTDC_LIPCR_LIPOS_Pos)          /*!< 0x000007FF */\n#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */\n\n/********************  Bit definition for LTDC_CPSR register  *****************/\n\n#define LTDC_CPSR_CYPOS_Pos          (0U)\n#define LTDC_CPSR_CYPOS_Msk          (0xFFFFU << LTDC_CPSR_CYPOS_Pos)          /*!< 0x0000FFFF */\n#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */\n#define LTDC_CPSR_CXPOS_Pos          (16U)\n#define LTDC_CPSR_CXPOS_Msk          (0xFFFFU << LTDC_CPSR_CXPOS_Pos)          /*!< 0xFFFF0000 */\n#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */\n\n/********************  Bit definition for LTDC_CDSR register  *****************/\n\n#define LTDC_CDSR_VDES_Pos           (0U)\n#define LTDC_CDSR_VDES_Msk           (0x1U << LTDC_CDSR_VDES_Pos)              /*!< 0x00000001 */\n#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status */\n#define LTDC_CDSR_HDES_Pos           (1U)\n#define LTDC_CDSR_HDES_Msk           (0x1U << LTDC_CDSR_HDES_Pos)              /*!< 0x00000002 */\n#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status */\n#define LTDC_CDSR_VSYNCS_Pos         (2U)\n#define LTDC_CDSR_VSYNCS_Msk         (0x1U << LTDC_CDSR_VSYNCS_Pos)            /*!< 0x00000004 */\n#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status */\n#define LTDC_CDSR_HSYNCS_Pos         (3U)\n#define LTDC_CDSR_HSYNCS_Msk         (0x1U << LTDC_CDSR_HSYNCS_Pos)            /*!< 0x00000008 */\n#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */\n\n/********************  Bit definition for LTDC_LxCR register  *****************/\n\n#define LTDC_LxCR_LEN_Pos            (0U)\n#define LTDC_LxCR_LEN_Msk            (0x1U << LTDC_LxCR_LEN_Pos)               /*!< 0x00000001 */\n#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable */\n#define LTDC_LxCR_COLKEN_Pos         (1U)\n#define LTDC_LxCR_COLKEN_Msk         (0x1U << LTDC_LxCR_COLKEN_Pos)            /*!< 0x00000002 */\n#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable */\n#define LTDC_LxCR_CLUTEN_Pos         (4U)\n#define LTDC_LxCR_CLUTEN_Msk         (0x1U << LTDC_LxCR_CLUTEN_Pos)            /*!< 0x00000010 */\n#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */\n\n/********************  Bit definition for LTDC_LxWHPCR register  **************/\n\n#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)\n#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos)      /*!< 0x00000FFF */\n#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */\n#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)\n#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos)     /*!< 0xFFFF0000 */\n#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position */\n\n/********************  Bit definition for LTDC_LxWVPCR register  **************/\n\n#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)\n#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos)      /*!< 0x00000FFF */\n#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */\n#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)\n#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos)     /*!< 0xFFFF0000 */\n#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position */\n\n/********************  Bit definition for LTDC_LxCKCR register  ***************/\n\n#define LTDC_LxCKCR_CKBLUE_Pos       (0U)\n#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFU << LTDC_LxCKCR_CKBLUE_Pos)         /*!< 0x000000FF */\n#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value */\n#define LTDC_LxCKCR_CKGREEN_Pos      (8U)\n#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFU << LTDC_LxCKCR_CKGREEN_Pos)        /*!< 0x0000FF00 */\n#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */\n#define LTDC_LxCKCR_CKRED_Pos        (16U)\n#define LTDC_LxCKCR_CKRED_Msk        (0xFFU << LTDC_LxCKCR_CKRED_Pos)          /*!< 0x00FF0000 */\n#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value */\n\n/********************  Bit definition for LTDC_LxPFCR register  ***************/\n\n#define LTDC_LxPFCR_PF_Pos           (0U)\n#define LTDC_LxPFCR_PF_Msk           (0x7U << LTDC_LxPFCR_PF_Pos)              /*!< 0x00000007 */\n#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */\n\n/********************  Bit definition for LTDC_LxCACR register  ***************/\n\n#define LTDC_LxCACR_CONSTA_Pos       (0U)\n#define LTDC_LxCACR_CONSTA_Msk       (0xFFU << LTDC_LxCACR_CONSTA_Pos)         /*!< 0x000000FF */\n#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */\n\n/********************  Bit definition for LTDC_LxDCCR register  ***************/\n\n#define LTDC_LxDCCR_DCBLUE_Pos       (0U)\n#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFU << LTDC_LxDCCR_DCBLUE_Pos)         /*!< 0x000000FF */\n#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue */\n#define LTDC_LxDCCR_DCGREEN_Pos      (8U)\n#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFU << LTDC_LxDCCR_DCGREEN_Pos)        /*!< 0x0000FF00 */\n#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */\n#define LTDC_LxDCCR_DCRED_Pos        (16U)\n#define LTDC_LxDCCR_DCRED_Msk        (0xFFU << LTDC_LxDCCR_DCRED_Pos)          /*!< 0x00FF0000 */\n#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red */\n#define LTDC_LxDCCR_DCALPHA_Pos      (24U)\n#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFU << LTDC_LxDCCR_DCALPHA_Pos)        /*!< 0xFF000000 */\n#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */\n\n/********************  Bit definition for LTDC_LxBFCR register  ***************/\n\n#define LTDC_LxBFCR_BF2_Pos          (0U)\n#define LTDC_LxBFCR_BF2_Msk          (0x7U << LTDC_LxBFCR_BF2_Pos)             /*!< 0x00000007 */\n#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */\n#define LTDC_LxBFCR_BF1_Pos          (8U)\n#define LTDC_LxBFCR_BF1_Msk          (0x7U << LTDC_LxBFCR_BF1_Pos)             /*!< 0x00000700 */\n#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */\n\n/********************  Bit definition for LTDC_LxCFBAR register  **************/\n\n#define LTDC_LxCFBAR_CFBADD_Pos      (0U)\n#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos)  /*!< 0xFFFFFFFF */\n#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */\n\n/********************  Bit definition for LTDC_LxCFBLR register  **************/\n\n#define LTDC_LxCFBLR_CFBLL_Pos       (0U)\n#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos)       /*!< 0x00001FFF */\n#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length */\n#define LTDC_LxCFBLR_CFBP_Pos        (16U)\n#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos)        /*!< 0x1FFF0000 */\n#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */\n\n/********************  Bit definition for LTDC_LxCFBLNR register  *************/\n\n#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)\n#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos)     /*!< 0x000007FF */\n#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */\n\n/********************  Bit definition for LTDC_LxCLUTWR register  *************/\n\n#define LTDC_LxCLUTWR_BLUE_Pos       (0U)\n#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFU << LTDC_LxCLUTWR_BLUE_Pos)         /*!< 0x000000FF */\n#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value */\n#define LTDC_LxCLUTWR_GREEN_Pos      (8U)\n#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFU << LTDC_LxCLUTWR_GREEN_Pos)        /*!< 0x0000FF00 */\n#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value */\n#define LTDC_LxCLUTWR_RED_Pos        (16U)\n#define LTDC_LxCLUTWR_RED_Msk        (0xFFU << LTDC_LxCLUTWR_RED_Pos)          /*!< 0x00FF0000 */\n#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value */\n#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)\n#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos)      /*!< 0xFF000000 */\n#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                             Power Control                                  */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for PWR_CR register  ********************/\n#define PWR_CR_LPDS_Pos        (0U)\n#define PWR_CR_LPDS_Msk        (0x1U << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */\n#define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */\n#define PWR_CR_PDDS_Pos        (1U)\n#define PWR_CR_PDDS_Msk        (0x1U << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */\n#define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */\n#define PWR_CR_CWUF_Pos        (2U)\n#define PWR_CR_CWUF_Msk        (0x1U << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */\n#define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */\n#define PWR_CR_CSBF_Pos        (3U)\n#define PWR_CR_CSBF_Msk        (0x1U << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */\n#define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */\n#define PWR_CR_PVDE_Pos        (4U)\n#define PWR_CR_PVDE_Msk        (0x1U << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */\n#define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */\n\n#define PWR_CR_PLS_Pos         (5U)\n#define PWR_CR_PLS_Msk         (0x7U << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */\n#define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */\n#define PWR_CR_PLS_0           (0x1U << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */\n#define PWR_CR_PLS_1           (0x2U << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */\n#define PWR_CR_PLS_2           (0x4U << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */\n\n/*!< PVD level configuration */\n#define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */\n#define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */\n#define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */\n#define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */\n#define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */\n#define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */\n#define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */\n#define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */\n#define PWR_CR_DBP_Pos         (8U)\n#define PWR_CR_DBP_Msk         (0x1U << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */\n#define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */\n#define PWR_CR_FPDS_Pos        (9U)\n#define PWR_CR_FPDS_Msk        (0x1U << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */\n#define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */\n#define PWR_CR_LPLVDS_Pos      (10U)\n#define PWR_CR_LPLVDS_Msk      (0x1U << PWR_CR_LPLVDS_Pos)                     /*!< 0x00000400 */\n#define PWR_CR_LPLVDS          PWR_CR_LPLVDS_Msk                               /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */\n#define PWR_CR_MRLVDS_Pos      (11U)\n#define PWR_CR_MRLVDS_Msk      (0x1U << PWR_CR_MRLVDS_Pos)                     /*!< 0x00000800 */\n#define PWR_CR_MRLVDS          PWR_CR_MRLVDS_Msk                               /*!< Main regulator Low Voltage Scaling in Stop mode            */\n#define PWR_CR_ADCDC1_Pos      (13U)\n#define PWR_CR_ADCDC1_Msk      (0x1U << PWR_CR_ADCDC1_Pos)                     /*!< 0x00002000 */\n#define PWR_CR_ADCDC1          PWR_CR_ADCDC1_Msk                               /*!< Refer to AN4073 on how to use this bit                     */\n#define PWR_CR_VOS_Pos         (14U)\n#define PWR_CR_VOS_Msk         (0x3U << PWR_CR_VOS_Pos)                        /*!< 0x0000C000 */\n#define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\n#define PWR_CR_VOS_0           0x00004000U                                     /*!< Bit 0 */\n#define PWR_CR_VOS_1           0x00008000U                                     /*!< Bit 1 */\n#define PWR_CR_ODEN_Pos        (16U)\n#define PWR_CR_ODEN_Msk        (0x1U << PWR_CR_ODEN_Pos)                       /*!< 0x00010000 */\n#define PWR_CR_ODEN            PWR_CR_ODEN_Msk                                 /*!< Over Drive enable                   */\n#define PWR_CR_ODSWEN_Pos      (17U)\n#define PWR_CR_ODSWEN_Msk      (0x1U << PWR_CR_ODSWEN_Pos)                     /*!< 0x00020000 */\n#define PWR_CR_ODSWEN          PWR_CR_ODSWEN_Msk                               /*!< Over Drive switch enabled           */\n#define PWR_CR_UDEN_Pos        (18U)\n#define PWR_CR_UDEN_Msk        (0x3U << PWR_CR_UDEN_Pos)                       /*!< 0x000C0000 */\n#define PWR_CR_UDEN            PWR_CR_UDEN_Msk                                 /*!< Under Drive enable in stop mode     */\n#define PWR_CR_UDEN_0          (0x1U << PWR_CR_UDEN_Pos)                       /*!< 0x00040000 */\n#define PWR_CR_UDEN_1          (0x2U << PWR_CR_UDEN_Pos)                       /*!< 0x00080000 */\n\n/* Legacy define */\n#define  PWR_CR_PMODE                        PWR_CR_VOS\n#define  PWR_CR_LPUDS                        PWR_CR_LPLVDS     /*!< Low-Power Regulator in deepsleep under-drive mode        */\n#define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode             */\n\n/*******************  Bit definition for PWR_CSR register  ********************/\n#define PWR_CSR_WUF_Pos        (0U)\n#define PWR_CSR_WUF_Msk        (0x1U << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */\n#define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */\n#define PWR_CSR_SBF_Pos        (1U)\n#define PWR_CSR_SBF_Msk        (0x1U << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */\n#define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */\n#define PWR_CSR_PVDO_Pos       (2U)\n#define PWR_CSR_PVDO_Msk       (0x1U << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */\n#define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */\n#define PWR_CSR_BRR_Pos        (3U)\n#define PWR_CSR_BRR_Msk        (0x1U << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */\n#define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */\n#define PWR_CSR_WUPP_Pos       (7U)\n#define PWR_CSR_WUPP_Msk       (0x1U << PWR_CSR_WUPP_Pos)                      /*!< 0x00000080 */\n#define PWR_CSR_WUPP           PWR_CSR_WUPP_Msk                                /*!< WKUP pin Polarity                                */\n#define PWR_CSR_EWUP_Pos       (8U)\n#define PWR_CSR_EWUP_Msk       (0x1U << PWR_CSR_EWUP_Pos)                      /*!< 0x00000100 */\n#define PWR_CSR_EWUP           PWR_CSR_EWUP_Msk                                /*!< Enable WKUP pin                                  */\n#define PWR_CSR_BRE_Pos        (9U)\n#define PWR_CSR_BRE_Msk        (0x1U << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */\n#define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */\n#define PWR_CSR_VOSRDY_Pos     (14U)\n#define PWR_CSR_VOSRDY_Msk     (0x1U << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */\n#define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */\n#define PWR_CSR_ODRDY_Pos      (16U)\n#define PWR_CSR_ODRDY_Msk      (0x1U << PWR_CSR_ODRDY_Pos)                     /*!< 0x00010000 */\n#define PWR_CSR_ODRDY          PWR_CSR_ODRDY_Msk                               /*!< Over Drive generator ready                       */\n#define PWR_CSR_ODSWRDY_Pos    (17U)\n#define PWR_CSR_ODSWRDY_Msk    (0x1U << PWR_CSR_ODSWRDY_Pos)                   /*!< 0x00020000 */\n#define PWR_CSR_ODSWRDY        PWR_CSR_ODSWRDY_Msk                             /*!< Over Drive Switch ready                          */\n#define PWR_CSR_UDRDY_Pos      (18U)\n#define PWR_CSR_UDRDY_Msk      (0x3U << PWR_CSR_UDRDY_Pos)                     /*!< 0x000C0000 */\n#define PWR_CSR_UDRDY          PWR_CSR_UDRDY_Msk                               /*!< Under Drive ready                                */\n/* Legacy define */\n#define  PWR_CSR_UDSWRDY                     PWR_CSR_UDRDY\n\n/* Legacy define */\n#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    QUADSPI                                 */\n/*                                                                            */\n/******************************************************************************/\n/*****************  Bit definition for QUADSPI_CR register  *******************/\n#define QUADSPI_CR_EN_Pos                (0U)\n#define QUADSPI_CR_EN_Msk                (0x1U << QUADSPI_CR_EN_Pos)           /*!< 0x00000001 */\n#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable                             */\n#define QUADSPI_CR_ABORT_Pos             (1U)\n#define QUADSPI_CR_ABORT_Msk             (0x1U << QUADSPI_CR_ABORT_Pos)        /*!< 0x00000002 */\n#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request                      */\n#define QUADSPI_CR_DMAEN_Pos             (2U)\n#define QUADSPI_CR_DMAEN_Msk             (0x1U << QUADSPI_CR_DMAEN_Pos)        /*!< 0x00000004 */\n#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable                         */\n#define QUADSPI_CR_TCEN_Pos              (3U)\n#define QUADSPI_CR_TCEN_Msk              (0x1U << QUADSPI_CR_TCEN_Pos)         /*!< 0x00000008 */\n#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable             */\n#define QUADSPI_CR_SSHIFT_Pos            (4U)\n#define QUADSPI_CR_SSHIFT_Msk            (0x1U << QUADSPI_CR_SSHIFT_Pos)       /*!< 0x00000010 */\n#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift                */\n#define QUADSPI_CR_DFM_Pos               (6U)\n#define QUADSPI_CR_DFM_Msk               (0x1U << QUADSPI_CR_DFM_Pos)          /*!< 0x00000040 */\n#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode                    */\n#define QUADSPI_CR_FSEL_Pos              (7U)\n#define QUADSPI_CR_FSEL_Msk              (0x1U << QUADSPI_CR_FSEL_Pos)         /*!< 0x00000080 */\n#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select                       */\n#define QUADSPI_CR_FTHRES_Pos            (8U)\n#define QUADSPI_CR_FTHRES_Msk            (0x1FU << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */\n#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level             */\n#define QUADSPI_CR_FTHRES_0              (0x01U << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */\n#define QUADSPI_CR_FTHRES_1              (0x02U << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */\n#define QUADSPI_CR_FTHRES_2              (0x04U << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */\n#define QUADSPI_CR_FTHRES_3              (0x08U << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */\n#define QUADSPI_CR_FTHRES_4              (0x10U << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001000 */\n#define QUADSPI_CR_TEIE_Pos              (16U)\n#define QUADSPI_CR_TEIE_Msk              (0x1U << QUADSPI_CR_TEIE_Pos)         /*!< 0x00010000 */\n#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable    */\n#define QUADSPI_CR_TCIE_Pos              (17U)\n#define QUADSPI_CR_TCIE_Msk              (0x1U << QUADSPI_CR_TCIE_Pos)         /*!< 0x00020000 */\n#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */\n#define QUADSPI_CR_FTIE_Pos              (18U)\n#define QUADSPI_CR_FTIE_Msk              (0x1U << QUADSPI_CR_FTIE_Pos)         /*!< 0x00040000 */\n#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable    */\n#define QUADSPI_CR_SMIE_Pos              (19U)\n#define QUADSPI_CR_SMIE_Msk              (0x1U << QUADSPI_CR_SMIE_Pos)         /*!< 0x00080000 */\n#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable      */\n#define QUADSPI_CR_TOIE_Pos              (20U)\n#define QUADSPI_CR_TOIE_Msk              (0x1U << QUADSPI_CR_TOIE_Pos)         /*!< 0x00100000 */\n#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable           */\n#define QUADSPI_CR_APMS_Pos              (22U)\n#define QUADSPI_CR_APMS_Msk              (0x1U << QUADSPI_CR_APMS_Pos)         /*!< 0x00400000 */\n#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1                              */\n#define QUADSPI_CR_PMM_Pos               (23U)\n#define QUADSPI_CR_PMM_Msk               (0x1U << QUADSPI_CR_PMM_Pos)          /*!< 0x00800000 */\n#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode                 */\n#define QUADSPI_CR_PRESCALER_Pos         (24U)\n#define QUADSPI_CR_PRESCALER_Msk         (0xFFU << QUADSPI_CR_PRESCALER_Pos)   /*!< 0xFF000000 */\n#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler     */\n#define QUADSPI_CR_PRESCALER_0           (0x01U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x01000000 */\n#define QUADSPI_CR_PRESCALER_1           (0x02U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x02000000 */\n#define QUADSPI_CR_PRESCALER_2           (0x04U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x04000000 */\n#define QUADSPI_CR_PRESCALER_3           (0x08U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x08000000 */\n#define QUADSPI_CR_PRESCALER_4           (0x10U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x10000000 */\n#define QUADSPI_CR_PRESCALER_5           (0x20U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x20000000 */\n#define QUADSPI_CR_PRESCALER_6           (0x40U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x40000000 */\n#define QUADSPI_CR_PRESCALER_7           (0x80U << QUADSPI_CR_PRESCALER_Pos)   /*!< 0x80000000 */\n\n/*****************  Bit definition for QUADSPI_DCR register  ******************/\n#define QUADSPI_DCR_CKMODE_Pos           (0U)\n#define QUADSPI_DCR_CKMODE_Msk           (0x1U << QUADSPI_DCR_CKMODE_Pos)      /*!< 0x00000001 */\n#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3                 */\n#define QUADSPI_DCR_CSHT_Pos             (8U)\n#define QUADSPI_DCR_CSHT_Msk             (0x7U << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000700 */\n#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */\n#define QUADSPI_DCR_CSHT_0               (0x1U << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000100 */\n#define QUADSPI_DCR_CSHT_1               (0x2U << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000200 */\n#define QUADSPI_DCR_CSHT_2               (0x4U << QUADSPI_DCR_CSHT_Pos)        /*!< 0x00000400 */\n#define QUADSPI_DCR_FSIZE_Pos            (16U)\n#define QUADSPI_DCR_FSIZE_Msk            (0x1FU << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x001F0000 */\n#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size          */\n#define QUADSPI_DCR_FSIZE_0              (0x01U << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00010000 */\n#define QUADSPI_DCR_FSIZE_1              (0x02U << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00020000 */\n#define QUADSPI_DCR_FSIZE_2              (0x04U << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00040000 */\n#define QUADSPI_DCR_FSIZE_3              (0x08U << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00080000 */\n#define QUADSPI_DCR_FSIZE_4              (0x10U << QUADSPI_DCR_FSIZE_Pos)      /*!< 0x00100000 */\n\n/******************  Bit definition for QUADSPI_SR register  *******************/\n#define QUADSPI_SR_TEF_Pos               (0U)\n#define QUADSPI_SR_TEF_Msk               (0x1U << QUADSPI_SR_TEF_Pos)          /*!< 0x00000001 */\n#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag    */\n#define QUADSPI_SR_TCF_Pos               (1U)\n#define QUADSPI_SR_TCF_Msk               (0x1U << QUADSPI_SR_TCF_Pos)          /*!< 0x00000002 */\n#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */\n#define QUADSPI_SR_FTF_Pos               (2U)\n#define QUADSPI_SR_FTF_Msk               (0x1U << QUADSPI_SR_FTF_Pos)          /*!< 0x00000004 */\n#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag    */\n#define QUADSPI_SR_SMF_Pos               (3U)\n#define QUADSPI_SR_SMF_Msk               (0x1U << QUADSPI_SR_SMF_Pos)          /*!< 0x00000008 */\n#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag      */\n#define QUADSPI_SR_TOF_Pos               (4U)\n#define QUADSPI_SR_TOF_Msk               (0x1U << QUADSPI_SR_TOF_Pos)          /*!< 0x00000010 */\n#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag           */\n#define QUADSPI_SR_BUSY_Pos              (5U)\n#define QUADSPI_SR_BUSY_Msk              (0x1U << QUADSPI_SR_BUSY_Pos)         /*!< 0x00000020 */\n#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy                   */\n#define QUADSPI_SR_FLEVEL_Pos            (8U)\n#define QUADSPI_SR_FLEVEL_Msk            (0x3FU << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00003F00 */\n#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag    */\n#define QUADSPI_SR_FLEVEL_0              (0x01U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000100 */\n#define QUADSPI_SR_FLEVEL_1              (0x02U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000200 */\n#define QUADSPI_SR_FLEVEL_2              (0x04U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000400 */\n#define QUADSPI_SR_FLEVEL_3              (0x08U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00000800 */\n#define QUADSPI_SR_FLEVEL_4              (0x10U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00001000 */\n#define QUADSPI_SR_FLEVEL_5              (0x20U << QUADSPI_SR_FLEVEL_Pos)      /*!< 0x00002000 */\n\n/******************  Bit definition for QUADSPI_FCR register  ******************/\n#define QUADSPI_FCR_CTEF_Pos             (0U)\n#define QUADSPI_FCR_CTEF_Msk             (0x1U << QUADSPI_FCR_CTEF_Pos)        /*!< 0x00000001 */\n#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag    */\n#define QUADSPI_FCR_CTCF_Pos             (1U)\n#define QUADSPI_FCR_CTCF_Msk             (0x1U << QUADSPI_FCR_CTCF_Pos)        /*!< 0x00000002 */\n#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */\n#define QUADSPI_FCR_CSMF_Pos             (3U)\n#define QUADSPI_FCR_CSMF_Msk             (0x1U << QUADSPI_FCR_CSMF_Pos)        /*!< 0x00000008 */\n#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag      */\n#define QUADSPI_FCR_CTOF_Pos             (4U)\n#define QUADSPI_FCR_CTOF_Msk             (0x1U << QUADSPI_FCR_CTOF_Pos)        /*!< 0x00000010 */\n#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag           */\n\n/******************  Bit definition for QUADSPI_DLR register  ******************/\n#define QUADSPI_DLR_DL_Pos               (0U)\n#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos)   /*!< 0xFFFFFFFF */\n#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */\n\n/******************  Bit definition for QUADSPI_CCR register  ******************/\n#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)\n#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */\n#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk           /*!< INSTRUCTION[7:0]: Instruction         */\n#define QUADSPI_CCR_INSTRUCTION_0        (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */\n#define QUADSPI_CCR_INSTRUCTION_1        (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */\n#define QUADSPI_CCR_INSTRUCTION_2        (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */\n#define QUADSPI_CCR_INSTRUCTION_3        (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */\n#define QUADSPI_CCR_INSTRUCTION_4        (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */\n#define QUADSPI_CCR_INSTRUCTION_5        (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */\n#define QUADSPI_CCR_INSTRUCTION_6        (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */\n#define QUADSPI_CCR_INSTRUCTION_7        (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */\n#define QUADSPI_CCR_IMODE_Pos            (8U)\n#define QUADSPI_CCR_IMODE_Msk            (0x3U << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000300 */\n#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                 /*!< IMODE[1:0]: Instruction Mode          */\n#define QUADSPI_CCR_IMODE_0              (0x1U << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000100 */\n#define QUADSPI_CCR_IMODE_1              (0x2U << QUADSPI_CCR_IMODE_Pos)       /*!< 0x00000200 */\n#define QUADSPI_CCR_ADMODE_Pos           (10U)\n#define QUADSPI_CCR_ADMODE_Msk           (0x3U << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000C00 */\n#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                /*!< ADMODE[1:0]: Address Mode             */\n#define QUADSPI_CCR_ADMODE_0             (0x1U << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000400 */\n#define QUADSPI_CCR_ADMODE_1             (0x2U << QUADSPI_CCR_ADMODE_Pos)      /*!< 0x00000800 */\n#define QUADSPI_CCR_ADSIZE_Pos           (12U)\n#define QUADSPI_CCR_ADSIZE_Msk           (0x3U << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00003000 */\n#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                /*!< ADSIZE[1:0]: Address Size             */\n#define QUADSPI_CCR_ADSIZE_0             (0x1U << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00001000 */\n#define QUADSPI_CCR_ADSIZE_1             (0x2U << QUADSPI_CCR_ADSIZE_Pos)      /*!< 0x00002000 */\n#define QUADSPI_CCR_ABMODE_Pos           (14U)\n#define QUADSPI_CCR_ABMODE_Msk           (0x3U << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x0000C000 */\n#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                /*!< ABMODE[1:0]: Alternate Bytes Mode     */\n#define QUADSPI_CCR_ABMODE_0             (0x1U << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00004000 */\n#define QUADSPI_CCR_ABMODE_1             (0x2U << QUADSPI_CCR_ABMODE_Pos)      /*!< 0x00008000 */\n#define QUADSPI_CCR_ABSIZE_Pos           (16U)\n#define QUADSPI_CCR_ABSIZE_Msk           (0x3U << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00030000 */\n#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                /*!< ABSIZE[1:0]: Instruction Mode         */\n#define QUADSPI_CCR_ABSIZE_0             (0x1U << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00010000 */\n#define QUADSPI_CCR_ABSIZE_1             (0x2U << QUADSPI_CCR_ABSIZE_Pos)      /*!< 0x00020000 */\n#define QUADSPI_CCR_DCYC_Pos             (18U)\n#define QUADSPI_CCR_DCYC_Msk             (0x1FU << QUADSPI_CCR_DCYC_Pos)       /*!< 0x007C0000 */\n#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                  /*!< DCYC[4:0]: Dummy Cycles               */\n#define QUADSPI_CCR_DCYC_0               (0x01U << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00040000 */\n#define QUADSPI_CCR_DCYC_1               (0x02U << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00080000 */\n#define QUADSPI_CCR_DCYC_2               (0x04U << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00100000 */\n#define QUADSPI_CCR_DCYC_3               (0x08U << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00200000 */\n#define QUADSPI_CCR_DCYC_4               (0x10U << QUADSPI_CCR_DCYC_Pos)       /*!< 0x00400000 */\n#define QUADSPI_CCR_DMODE_Pos            (24U)\n#define QUADSPI_CCR_DMODE_Msk            (0x3U << QUADSPI_CCR_DMODE_Pos)       /*!< 0x03000000 */\n#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                 /*!< DMODE[1:0]: Data Mode                 */\n#define QUADSPI_CCR_DMODE_0              (0x1U << QUADSPI_CCR_DMODE_Pos)       /*!< 0x01000000 */\n#define QUADSPI_CCR_DMODE_1              (0x2U << QUADSPI_CCR_DMODE_Pos)       /*!< 0x02000000 */\n#define QUADSPI_CCR_FMODE_Pos            (26U)\n#define QUADSPI_CCR_FMODE_Msk            (0x3U << QUADSPI_CCR_FMODE_Pos)       /*!< 0x0C000000 */\n#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                 /*!< FMODE[1:0]: Functional Mode           */\n#define QUADSPI_CCR_FMODE_0              (0x1U << QUADSPI_CCR_FMODE_Pos)       /*!< 0x04000000 */\n#define QUADSPI_CCR_FMODE_1              (0x2U << QUADSPI_CCR_FMODE_Pos)       /*!< 0x08000000 */\n#define QUADSPI_CCR_SIOO_Pos             (28U)\n#define QUADSPI_CCR_SIOO_Msk             (0x1U << QUADSPI_CCR_SIOO_Pos)        /*!< 0x10000000 */\n#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                  /*!< SIOO: Send Instruction Only Once Mode */\n#define QUADSPI_CCR_DHHC_Pos             (30U)\n#define QUADSPI_CCR_DHHC_Msk             (0x1U << QUADSPI_CCR_DHHC_Pos)        /*!< 0x40000000 */\n#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                  /*!< DHHC: Delay Half Hclk Cycle           */\n#define QUADSPI_CCR_DDRM_Pos             (31U)\n#define QUADSPI_CCR_DDRM_Msk             (0x1U << QUADSPI_CCR_DDRM_Pos)        /*!< 0x80000000 */\n#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                  /*!< DDRM: Double Data Rate Mode           */\n/******************  Bit definition for QUADSPI_AR register  *******************/\n#define QUADSPI_AR_ADDRESS_Pos           (0U)\n#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address                */\n\n/******************  Bit definition for QUADSPI_ABR register  ******************/\n#define QUADSPI_ABR_ALTERNATE_Pos        (0U)\n#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes      */\n\n/******************  Bit definition for QUADSPI_DR register  *******************/\n#define QUADSPI_DR_DATA_Pos              (0U)\n#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos)  /*!< 0xFFFFFFFF */\n#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data                      */\n\n/******************  Bit definition for QUADSPI_PSMKR register  ****************/\n#define QUADSPI_PSMKR_MASK_Pos           (0U)\n#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask               */\n\n/******************  Bit definition for QUADSPI_PSMAR register  ****************/\n#define QUADSPI_PSMAR_MATCH_Pos          (0U)\n#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match             */\n\n/******************  Bit definition for QUADSPI_PIR register  *****************/\n#define QUADSPI_PIR_INTERVAL_Pos         (0U)\n#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */\n#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval      */\n\n/******************  Bit definition for QUADSPI_LPTR register  *****************/\n#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)\n#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */\n#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period         */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Reset and Clock Control                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for RCC_CR register  ********************/\n#define RCC_CR_HSION_Pos                   (0U)\n#define RCC_CR_HSION_Msk                   (0x1U << RCC_CR_HSION_Pos)          /*!< 0x00000001 */\n#define RCC_CR_HSION                       RCC_CR_HSION_Msk\n#define RCC_CR_HSIRDY_Pos                  (1U)\n#define RCC_CR_HSIRDY_Msk                  (0x1U << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */\n#define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk\n\n#define RCC_CR_HSITRIM_Pos                 (3U)\n#define RCC_CR_HSITRIM_Msk                 (0x1FU << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */\n#define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk\n#define RCC_CR_HSITRIM_0                   (0x01U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */\n#define RCC_CR_HSITRIM_1                   (0x02U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */\n#define RCC_CR_HSITRIM_2                   (0x04U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */\n#define RCC_CR_HSITRIM_3                   (0x08U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */\n#define RCC_CR_HSITRIM_4                   (0x10U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */\n\n#define RCC_CR_HSICAL_Pos                  (8U)\n#define RCC_CR_HSICAL_Msk                  (0xFFU << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */\n#define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk\n#define RCC_CR_HSICAL_0                    (0x01U << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */\n#define RCC_CR_HSICAL_1                    (0x02U << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */\n#define RCC_CR_HSICAL_2                    (0x04U << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */\n#define RCC_CR_HSICAL_3                    (0x08U << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */\n#define RCC_CR_HSICAL_4                    (0x10U << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */\n#define RCC_CR_HSICAL_5                    (0x20U << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */\n#define RCC_CR_HSICAL_6                    (0x40U << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */\n#define RCC_CR_HSICAL_7                    (0x80U << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */\n\n#define RCC_CR_HSEON_Pos                   (16U)\n#define RCC_CR_HSEON_Msk                   (0x1U << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */\n#define RCC_CR_HSEON                       RCC_CR_HSEON_Msk\n#define RCC_CR_HSERDY_Pos                  (17U)\n#define RCC_CR_HSERDY_Msk                  (0x1U << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */\n#define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk\n#define RCC_CR_HSEBYP_Pos                  (18U)\n#define RCC_CR_HSEBYP_Msk                  (0x1U << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */\n#define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk\n#define RCC_CR_CSSON_Pos                   (19U)\n#define RCC_CR_CSSON_Msk                   (0x1U << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */\n#define RCC_CR_CSSON                       RCC_CR_CSSON_Msk\n#define RCC_CR_PLLON_Pos                   (24U)\n#define RCC_CR_PLLON_Msk                   (0x1U << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */\n#define RCC_CR_PLLON                       RCC_CR_PLLON_Msk\n#define RCC_CR_PLLRDY_Pos                  (25U)\n#define RCC_CR_PLLRDY_Msk                  (0x1U << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */\n#define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_PLLI2S_SUPPORT                                                     /*!< Support PLLI2S oscillator */\n\n#define RCC_CR_PLLI2SON_Pos                (26U)\n#define RCC_CR_PLLI2SON_Msk                (0x1U << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */\n#define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk\n#define RCC_CR_PLLI2SRDY_Pos               (27U)\n#define RCC_CR_PLLI2SRDY_Msk               (0x1U << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */\n#define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_PLLSAI_SUPPORT                                                     /*!< Support PLLSAI oscillator */\n\n#define RCC_CR_PLLSAION_Pos                (28U)\n#define RCC_CR_PLLSAION_Msk                (0x1U << RCC_CR_PLLSAION_Pos)       /*!< 0x10000000 */\n#define RCC_CR_PLLSAION                    RCC_CR_PLLSAION_Msk\n#define RCC_CR_PLLSAIRDY_Pos               (29U)\n#define RCC_CR_PLLSAIRDY_Msk               (0x1U << RCC_CR_PLLSAIRDY_Pos)      /*!< 0x20000000 */\n#define RCC_CR_PLLSAIRDY                   RCC_CR_PLLSAIRDY_Msk\n\n/********************  Bit definition for RCC_PLLCFGR register  ***************/\n#define RCC_PLLCFGR_PLLM_Pos               (0U)\n#define RCC_PLLCFGR_PLLM_Msk               (0x3FU << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */\n#define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk\n#define RCC_PLLCFGR_PLLM_0                 (0x01U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */\n#define RCC_PLLCFGR_PLLM_1                 (0x02U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */\n#define RCC_PLLCFGR_PLLM_2                 (0x04U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */\n#define RCC_PLLCFGR_PLLM_3                 (0x08U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */\n#define RCC_PLLCFGR_PLLM_4                 (0x10U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */\n#define RCC_PLLCFGR_PLLM_5                 (0x20U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */\n\n#define RCC_PLLCFGR_PLLN_Pos               (6U)\n#define RCC_PLLCFGR_PLLN_Msk               (0x1FFU << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */\n#define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk\n#define RCC_PLLCFGR_PLLN_0                 (0x001U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */\n#define RCC_PLLCFGR_PLLN_1                 (0x002U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */\n#define RCC_PLLCFGR_PLLN_2                 (0x004U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */\n#define RCC_PLLCFGR_PLLN_3                 (0x008U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */\n#define RCC_PLLCFGR_PLLN_4                 (0x010U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */\n#define RCC_PLLCFGR_PLLN_5                 (0x020U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */\n#define RCC_PLLCFGR_PLLN_6                 (0x040U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */\n#define RCC_PLLCFGR_PLLN_7                 (0x080U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */\n#define RCC_PLLCFGR_PLLN_8                 (0x100U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */\n\n#define RCC_PLLCFGR_PLLP_Pos               (16U)\n#define RCC_PLLCFGR_PLLP_Msk               (0x3U << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */\n#define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk\n#define RCC_PLLCFGR_PLLP_0                 (0x1U << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */\n#define RCC_PLLCFGR_PLLP_1                 (0x2U << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */\n\n#define RCC_PLLCFGR_PLLSRC_Pos             (22U)\n#define RCC_PLLCFGR_PLLSRC_Msk             (0x1U << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk\n#define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)\n#define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk\n#define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U\n\n#define RCC_PLLCFGR_PLLQ_Pos               (24U)\n#define RCC_PLLCFGR_PLLQ_Msk               (0xFU << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */\n#define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk\n#define RCC_PLLCFGR_PLLQ_0                 (0x1U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */\n#define RCC_PLLCFGR_PLLQ_1                 (0x2U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */\n#define RCC_PLLCFGR_PLLQ_2                 (0x4U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */\n#define RCC_PLLCFGR_PLLQ_3                 (0x8U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */\n\n#define RCC_PLLCFGR_PLLR_Pos               (28U)\n#define RCC_PLLCFGR_PLLR_Msk               (0x7U << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x70000000 */\n#define RCC_PLLCFGR_PLLR                   RCC_PLLCFGR_PLLR_Msk\n#define RCC_PLLCFGR_PLLR_0                 (0x1U << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x10000000 */\n#define RCC_PLLCFGR_PLLR_1                 (0x2U << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x20000000 */\n#define RCC_PLLCFGR_PLLR_2                 (0x4U << RCC_PLLCFGR_PLLR_Pos)      /*!< 0x40000000 */\n\n/********************  Bit definition for RCC_CFGR register  ******************/\n/*!< SW configuration */\n#define RCC_CFGR_SW_Pos                    (0U)\n#define RCC_CFGR_SW_Msk                    (0x3U << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */\n#define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */\n#define RCC_CFGR_SW_0                      (0x1U << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */\n#define RCC_CFGR_SW_1                      (0x2U << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */\n\n#define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */\n#define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */\n#define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */\n\n/*!< SWS configuration */\n#define RCC_CFGR_SWS_Pos                   (2U)\n#define RCC_CFGR_SWS_Msk                   (0x3U << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */\n#define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */\n#define RCC_CFGR_SWS_0                     (0x1U << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */\n#define RCC_CFGR_SWS_1                     (0x2U << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */\n\n#define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */\n#define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */\n#define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */\n\n/*!< HPRE configuration */\n#define RCC_CFGR_HPRE_Pos                  (4U)\n#define RCC_CFGR_HPRE_Msk                  (0xFU << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */\n#define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */\n#define RCC_CFGR_HPRE_0                    (0x1U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */\n#define RCC_CFGR_HPRE_1                    (0x2U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */\n#define RCC_CFGR_HPRE_2                    (0x4U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */\n#define RCC_CFGR_HPRE_3                    (0x8U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */\n\n#define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */\n#define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */\n#define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */\n#define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */\n#define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */\n#define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */\n#define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */\n#define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */\n#define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */\n\n/*!< PPRE1 configuration */\n#define RCC_CFGR_PPRE1_Pos                 (10U)\n#define RCC_CFGR_PPRE1_Msk                 (0x7U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */\n#define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */\n#define RCC_CFGR_PPRE1_0                   (0x1U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */\n#define RCC_CFGR_PPRE1_1                   (0x2U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */\n#define RCC_CFGR_PPRE1_2                   (0x4U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */\n\n#define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */\n\n/*!< PPRE2 configuration */\n#define RCC_CFGR_PPRE2_Pos                 (13U)\n#define RCC_CFGR_PPRE2_Msk                 (0x7U << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */\n#define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */\n#define RCC_CFGR_PPRE2_0                   (0x1U << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */\n#define RCC_CFGR_PPRE2_1                   (0x2U << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */\n#define RCC_CFGR_PPRE2_2                   (0x4U << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */\n\n#define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */\n\n/*!< RTCPRE configuration */\n#define RCC_CFGR_RTCPRE_Pos                (16U)\n#define RCC_CFGR_RTCPRE_Msk                (0x1FU << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */\n#define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk\n#define RCC_CFGR_RTCPRE_0                  (0x01U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */\n#define RCC_CFGR_RTCPRE_1                  (0x02U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */\n#define RCC_CFGR_RTCPRE_2                  (0x04U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */\n#define RCC_CFGR_RTCPRE_3                  (0x08U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */\n#define RCC_CFGR_RTCPRE_4                  (0x10U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */\n\n/*!< MCO1 configuration */\n#define RCC_CFGR_MCO1_Pos                  (21U)\n#define RCC_CFGR_MCO1_Msk                  (0x3U << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */\n#define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk\n#define RCC_CFGR_MCO1_0                    (0x1U << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */\n#define RCC_CFGR_MCO1_1                    (0x2U << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */\n\n#define RCC_CFGR_I2SSRC_Pos                (23U)\n#define RCC_CFGR_I2SSRC_Msk                (0x1U << RCC_CFGR_I2SSRC_Pos)       /*!< 0x00800000 */\n#define RCC_CFGR_I2SSRC                    RCC_CFGR_I2SSRC_Msk\n\n#define RCC_CFGR_MCO1PRE_Pos               (24U)\n#define RCC_CFGR_MCO1PRE_Msk               (0x7U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */\n#define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk\n#define RCC_CFGR_MCO1PRE_0                 (0x1U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */\n#define RCC_CFGR_MCO1PRE_1                 (0x2U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */\n#define RCC_CFGR_MCO1PRE_2                 (0x4U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */\n\n#define RCC_CFGR_MCO2PRE_Pos               (27U)\n#define RCC_CFGR_MCO2PRE_Msk               (0x7U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */\n#define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk\n#define RCC_CFGR_MCO2PRE_0                 (0x1U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */\n#define RCC_CFGR_MCO2PRE_1                 (0x2U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */\n#define RCC_CFGR_MCO2PRE_2                 (0x4U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */\n\n#define RCC_CFGR_MCO2_Pos                  (30U)\n#define RCC_CFGR_MCO2_Msk                  (0x3U << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */\n#define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk\n#define RCC_CFGR_MCO2_0                    (0x1U << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */\n#define RCC_CFGR_MCO2_1                    (0x2U << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */\n\n/********************  Bit definition for RCC_CIR register  *******************/\n#define RCC_CIR_LSIRDYF_Pos                (0U)\n#define RCC_CIR_LSIRDYF_Msk                (0x1U << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */\n#define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk\n#define RCC_CIR_LSERDYF_Pos                (1U)\n#define RCC_CIR_LSERDYF_Msk                (0x1U << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */\n#define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk\n#define RCC_CIR_HSIRDYF_Pos                (2U)\n#define RCC_CIR_HSIRDYF_Msk                (0x1U << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */\n#define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk\n#define RCC_CIR_HSERDYF_Pos                (3U)\n#define RCC_CIR_HSERDYF_Msk                (0x1U << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */\n#define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk\n#define RCC_CIR_PLLRDYF_Pos                (4U)\n#define RCC_CIR_PLLRDYF_Msk                (0x1U << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */\n#define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk\n#define RCC_CIR_PLLI2SRDYF_Pos             (5U)\n#define RCC_CIR_PLLI2SRDYF_Msk             (0x1U << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */\n#define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk\n\n#define RCC_CIR_PLLSAIRDYF_Pos             (6U)\n#define RCC_CIR_PLLSAIRDYF_Msk             (0x1U << RCC_CIR_PLLSAIRDYF_Pos)    /*!< 0x00000040 */\n#define RCC_CIR_PLLSAIRDYF                 RCC_CIR_PLLSAIRDYF_Msk\n#define RCC_CIR_CSSF_Pos                   (7U)\n#define RCC_CIR_CSSF_Msk                   (0x1U << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */\n#define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk\n#define RCC_CIR_LSIRDYIE_Pos               (8U)\n#define RCC_CIR_LSIRDYIE_Msk               (0x1U << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */\n#define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk\n#define RCC_CIR_LSERDYIE_Pos               (9U)\n#define RCC_CIR_LSERDYIE_Msk               (0x1U << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */\n#define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk\n#define RCC_CIR_HSIRDYIE_Pos               (10U)\n#define RCC_CIR_HSIRDYIE_Msk               (0x1U << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */\n#define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk\n#define RCC_CIR_HSERDYIE_Pos               (11U)\n#define RCC_CIR_HSERDYIE_Msk               (0x1U << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */\n#define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk\n#define RCC_CIR_PLLRDYIE_Pos               (12U)\n#define RCC_CIR_PLLRDYIE_Msk               (0x1U << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */\n#define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk\n#define RCC_CIR_PLLI2SRDYIE_Pos            (13U)\n#define RCC_CIR_PLLI2SRDYIE_Msk            (0x1U << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */\n#define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk\n\n#define RCC_CIR_PLLSAIRDYIE_Pos            (14U)\n#define RCC_CIR_PLLSAIRDYIE_Msk            (0x1U << RCC_CIR_PLLSAIRDYIE_Pos)   /*!< 0x00004000 */\n#define RCC_CIR_PLLSAIRDYIE                RCC_CIR_PLLSAIRDYIE_Msk\n#define RCC_CIR_LSIRDYC_Pos                (16U)\n#define RCC_CIR_LSIRDYC_Msk                (0x1U << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */\n#define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk\n#define RCC_CIR_LSERDYC_Pos                (17U)\n#define RCC_CIR_LSERDYC_Msk                (0x1U << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */\n#define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk\n#define RCC_CIR_HSIRDYC_Pos                (18U)\n#define RCC_CIR_HSIRDYC_Msk                (0x1U << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */\n#define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk\n#define RCC_CIR_HSERDYC_Pos                (19U)\n#define RCC_CIR_HSERDYC_Msk                (0x1U << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */\n#define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk\n#define RCC_CIR_PLLRDYC_Pos                (20U)\n#define RCC_CIR_PLLRDYC_Msk                (0x1U << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */\n#define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk\n#define RCC_CIR_PLLI2SRDYC_Pos             (21U)\n#define RCC_CIR_PLLI2SRDYC_Msk             (0x1U << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */\n#define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk\n#define RCC_CIR_PLLSAIRDYC_Pos             (22U)\n#define RCC_CIR_PLLSAIRDYC_Msk             (0x1U << RCC_CIR_PLLSAIRDYC_Pos)    /*!< 0x00400000 */\n#define RCC_CIR_PLLSAIRDYC                 RCC_CIR_PLLSAIRDYC_Msk\n\n#define RCC_CIR_CSSC_Pos                   (23U)\n#define RCC_CIR_CSSC_Msk                   (0x1U << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */\n#define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk\n\n/********************  Bit definition for RCC_AHB1RSTR register  **************/\n#define RCC_AHB1RSTR_GPIOARST_Pos          (0U)\n#define RCC_AHB1RSTR_GPIOARST_Msk          (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */\n#define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk\n#define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)\n#define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */\n#define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk\n#define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)\n#define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */\n#define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk\n#define RCC_AHB1RSTR_GPIODRST_Pos          (3U)\n#define RCC_AHB1RSTR_GPIODRST_Msk          (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */\n#define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk\n#define RCC_AHB1RSTR_GPIOERST_Pos          (4U)\n#define RCC_AHB1RSTR_GPIOERST_Msk          (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */\n#define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk\n#define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)\n#define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */\n#define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk\n#define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)\n#define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */\n#define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk\n#define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)\n#define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk\n#define RCC_AHB1RSTR_GPIOIRST_Pos          (8U)\n#define RCC_AHB1RSTR_GPIOIRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */\n#define RCC_AHB1RSTR_GPIOIRST              RCC_AHB1RSTR_GPIOIRST_Msk\n#define RCC_AHB1RSTR_GPIOJRST_Pos          (9U)\n#define RCC_AHB1RSTR_GPIOJRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */\n#define RCC_AHB1RSTR_GPIOJRST              RCC_AHB1RSTR_GPIOJRST_Msk\n#define RCC_AHB1RSTR_GPIOKRST_Pos          (10U)\n#define RCC_AHB1RSTR_GPIOKRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */\n#define RCC_AHB1RSTR_GPIOKRST              RCC_AHB1RSTR_GPIOKRST_Msk\n#define RCC_AHB1RSTR_CRCRST_Pos            (12U)\n#define RCC_AHB1RSTR_CRCRST_Msk            (0x1U << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */\n#define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk\n#define RCC_AHB1RSTR_DMA1RST_Pos           (21U)\n#define RCC_AHB1RSTR_DMA1RST_Msk           (0x1U << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */\n#define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk\n#define RCC_AHB1RSTR_DMA2RST_Pos           (22U)\n#define RCC_AHB1RSTR_DMA2RST_Msk           (0x1U << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */\n#define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk\n#define RCC_AHB1RSTR_DMA2DRST_Pos          (23U)\n#define RCC_AHB1RSTR_DMA2DRST_Msk          (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */\n#define RCC_AHB1RSTR_DMA2DRST              RCC_AHB1RSTR_DMA2DRST_Msk\n#define RCC_AHB1RSTR_ETHMACRST_Pos         (25U)\n#define RCC_AHB1RSTR_ETHMACRST_Msk         (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */\n#define RCC_AHB1RSTR_ETHMACRST             RCC_AHB1RSTR_ETHMACRST_Msk\n#define RCC_AHB1RSTR_OTGHRST_Pos           (29U)\n#define RCC_AHB1RSTR_OTGHRST_Msk           (0x1U << RCC_AHB1RSTR_OTGHRST_Pos)  /*!< 0x20000000 */\n#define RCC_AHB1RSTR_OTGHRST               RCC_AHB1RSTR_OTGHRST_Msk\n\n/********************  Bit definition for RCC_AHB2RSTR register  **************/\n#define RCC_AHB2RSTR_DCMIRST_Pos           (0U)\n#define RCC_AHB2RSTR_DCMIRST_Msk           (0x1U << RCC_AHB2RSTR_DCMIRST_Pos)  /*!< 0x00000001 */\n#define RCC_AHB2RSTR_DCMIRST               RCC_AHB2RSTR_DCMIRST_Msk\n#define RCC_AHB2RSTR_RNGRST_Pos            (6U)\n#define RCC_AHB2RSTR_RNGRST_Msk            (0x1U << RCC_AHB2RSTR_RNGRST_Pos)   /*!< 0x00000040 */\n#define RCC_AHB2RSTR_RNGRST                RCC_AHB2RSTR_RNGRST_Msk\n#define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)\n#define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk\n/********************  Bit definition for RCC_AHB3RSTR register  **************/\n#define RCC_AHB3RSTR_FMCRST_Pos            (0U)\n#define RCC_AHB3RSTR_FMCRST_Msk            (0x1U << RCC_AHB3RSTR_FMCRST_Pos)   /*!< 0x00000001 */\n#define RCC_AHB3RSTR_FMCRST                RCC_AHB3RSTR_FMCRST_Msk\n#define RCC_AHB3RSTR_QSPIRST_Pos           (1U)\n#define RCC_AHB3RSTR_QSPIRST_Msk           (0x1U << RCC_AHB3RSTR_QSPIRST_Pos)  /*!< 0x00000002 */\n#define RCC_AHB3RSTR_QSPIRST               RCC_AHB3RSTR_QSPIRST_Msk\n\n\n/********************  Bit definition for RCC_APB1RSTR register  **************/\n#define RCC_APB1RSTR_TIM2RST_Pos           (0U)\n#define RCC_APB1RSTR_TIM2RST_Msk           (0x1U << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk\n#define RCC_APB1RSTR_TIM3RST_Pos           (1U)\n#define RCC_APB1RSTR_TIM3RST_Msk           (0x1U << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk\n#define RCC_APB1RSTR_TIM4RST_Pos           (2U)\n#define RCC_APB1RSTR_TIM4RST_Msk           (0x1U << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */\n#define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk\n#define RCC_APB1RSTR_TIM5RST_Pos           (3U)\n#define RCC_APB1RSTR_TIM5RST_Msk           (0x1U << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */\n#define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk\n#define RCC_APB1RSTR_TIM6RST_Pos           (4U)\n#define RCC_APB1RSTR_TIM6RST_Msk           (0x1U << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */\n#define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk\n#define RCC_APB1RSTR_TIM7RST_Pos           (5U)\n#define RCC_APB1RSTR_TIM7RST_Msk           (0x1U << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */\n#define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk\n#define RCC_APB1RSTR_TIM12RST_Pos          (6U)\n#define RCC_APB1RSTR_TIM12RST_Msk          (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */\n#define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk\n#define RCC_APB1RSTR_TIM13RST_Pos          (7U)\n#define RCC_APB1RSTR_TIM13RST_Msk          (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */\n#define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk\n#define RCC_APB1RSTR_TIM14RST_Pos          (8U)\n#define RCC_APB1RSTR_TIM14RST_Msk          (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */\n#define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk\n#define RCC_APB1RSTR_WWDGRST_Pos           (11U)\n#define RCC_APB1RSTR_WWDGRST_Msk           (0x1U << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */\n#define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk\n#define RCC_APB1RSTR_SPI2RST_Pos           (14U)\n#define RCC_APB1RSTR_SPI2RST_Msk           (0x1U << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */\n#define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk\n#define RCC_APB1RSTR_SPI3RST_Pos           (15U)\n#define RCC_APB1RSTR_SPI3RST_Msk           (0x1U << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */\n#define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk\n#define RCC_APB1RSTR_USART2RST_Pos         (17U)\n#define RCC_APB1RSTR_USART2RST_Msk         (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */\n#define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk\n#define RCC_APB1RSTR_USART3RST_Pos         (18U)\n#define RCC_APB1RSTR_USART3RST_Msk         (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */\n#define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk\n#define RCC_APB1RSTR_UART4RST_Pos          (19U)\n#define RCC_APB1RSTR_UART4RST_Msk          (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */\n#define RCC_APB1RSTR_UART4RST              RCC_APB1RSTR_UART4RST_Msk\n#define RCC_APB1RSTR_UART5RST_Pos          (20U)\n#define RCC_APB1RSTR_UART5RST_Msk          (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */\n#define RCC_APB1RSTR_UART5RST              RCC_APB1RSTR_UART5RST_Msk\n#define RCC_APB1RSTR_I2C1RST_Pos           (21U)\n#define RCC_APB1RSTR_I2C1RST_Msk           (0x1U << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */\n#define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk\n#define RCC_APB1RSTR_I2C2RST_Pos           (22U)\n#define RCC_APB1RSTR_I2C2RST_Msk           (0x1U << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */\n#define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk\n#define RCC_APB1RSTR_I2C3RST_Pos           (23U)\n#define RCC_APB1RSTR_I2C3RST_Msk           (0x1U << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */\n#define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk\n#define RCC_APB1RSTR_CAN1RST_Pos           (25U)\n#define RCC_APB1RSTR_CAN1RST_Msk           (0x1U << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */\n#define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk\n#define RCC_APB1RSTR_CAN2RST_Pos           (26U)\n#define RCC_APB1RSTR_CAN2RST_Msk           (0x1U << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */\n#define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk\n#define RCC_APB1RSTR_PWRRST_Pos            (28U)\n#define RCC_APB1RSTR_PWRRST_Msk            (0x1U << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */\n#define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk\n#define RCC_APB1RSTR_DACRST_Pos            (29U)\n#define RCC_APB1RSTR_DACRST_Msk            (0x1U << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */\n#define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk\n#define RCC_APB1RSTR_UART7RST_Pos          (30U)\n#define RCC_APB1RSTR_UART7RST_Msk          (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */\n#define RCC_APB1RSTR_UART7RST              RCC_APB1RSTR_UART7RST_Msk\n#define RCC_APB1RSTR_UART8RST_Pos          (31U)\n#define RCC_APB1RSTR_UART8RST_Msk          (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */\n#define RCC_APB1RSTR_UART8RST              RCC_APB1RSTR_UART8RST_Msk\n\n/********************  Bit definition for RCC_APB2RSTR register  **************/\n#define RCC_APB2RSTR_TIM1RST_Pos           (0U)\n#define RCC_APB2RSTR_TIM1RST_Msk           (0x1U << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk\n#define RCC_APB2RSTR_TIM8RST_Pos           (1U)\n#define RCC_APB2RSTR_TIM8RST_Msk           (0x1U << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk\n#define RCC_APB2RSTR_USART1RST_Pos         (4U)\n#define RCC_APB2RSTR_USART1RST_Msk         (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */\n#define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk\n#define RCC_APB2RSTR_USART6RST_Pos         (5U)\n#define RCC_APB2RSTR_USART6RST_Msk         (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */\n#define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk\n#define RCC_APB2RSTR_ADCRST_Pos            (8U)\n#define RCC_APB2RSTR_ADCRST_Msk            (0x1U << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */\n#define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk\n#define RCC_APB2RSTR_SDIORST_Pos           (11U)\n#define RCC_APB2RSTR_SDIORST_Msk           (0x1U << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */\n#define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk\n#define RCC_APB2RSTR_SPI1RST_Pos           (12U)\n#define RCC_APB2RSTR_SPI1RST_Msk           (0x1U << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */\n#define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk\n#define RCC_APB2RSTR_SPI4RST_Pos           (13U)\n#define RCC_APB2RSTR_SPI4RST_Msk           (0x1U << RCC_APB2RSTR_SPI4RST_Pos)  /*!< 0x00002000 */\n#define RCC_APB2RSTR_SPI4RST               RCC_APB2RSTR_SPI4RST_Msk\n#define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)\n#define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */\n#define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk\n#define RCC_APB2RSTR_TIM9RST_Pos           (16U)\n#define RCC_APB2RSTR_TIM9RST_Msk           (0x1U << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */\n#define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk\n#define RCC_APB2RSTR_TIM10RST_Pos          (17U)\n#define RCC_APB2RSTR_TIM10RST_Msk          (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */\n#define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk\n#define RCC_APB2RSTR_TIM11RST_Pos          (18U)\n#define RCC_APB2RSTR_TIM11RST_Msk          (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */\n#define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk\n#define RCC_APB2RSTR_SPI5RST_Pos           (20U)\n#define RCC_APB2RSTR_SPI5RST_Msk           (0x1U << RCC_APB2RSTR_SPI5RST_Pos)  /*!< 0x00100000 */\n#define RCC_APB2RSTR_SPI5RST               RCC_APB2RSTR_SPI5RST_Msk\n#define RCC_APB2RSTR_SPI6RST_Pos           (21U)\n#define RCC_APB2RSTR_SPI6RST_Msk           (0x1U << RCC_APB2RSTR_SPI6RST_Pos)  /*!< 0x00200000 */\n#define RCC_APB2RSTR_SPI6RST               RCC_APB2RSTR_SPI6RST_Msk\n#define RCC_APB2RSTR_SAI1RST_Pos           (22U)\n#define RCC_APB2RSTR_SAI1RST_Msk           (0x1U << RCC_APB2RSTR_SAI1RST_Pos)  /*!< 0x00400000 */\n#define RCC_APB2RSTR_SAI1RST               RCC_APB2RSTR_SAI1RST_Msk\n#define RCC_APB2RSTR_LTDCRST_Pos           (26U)\n#define RCC_APB2RSTR_LTDCRST_Msk           (0x1U << RCC_APB2RSTR_LTDCRST_Pos)  /*!< 0x04000000 */\n#define RCC_APB2RSTR_LTDCRST               RCC_APB2RSTR_LTDCRST_Msk\n#define RCC_APB2RSTR_DSIRST_Pos            (27U)\n#define RCC_APB2RSTR_DSIRST_Msk            (0x1U << RCC_APB2RSTR_DSIRST_Pos)   /*!< 0x08000000 */\n#define RCC_APB2RSTR_DSIRST                RCC_APB2RSTR_DSIRST_Msk\n\n/* Old SPI1RST bit definition, maintained for legacy purpose */\n#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST\n\n/********************  Bit definition for RCC_AHB1ENR register  ***************/\n#define RCC_AHB1ENR_GPIOAEN_Pos            (0U)\n#define RCC_AHB1ENR_GPIOAEN_Msk            (0x1U << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */\n#define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk\n#define RCC_AHB1ENR_GPIOBEN_Pos            (1U)\n#define RCC_AHB1ENR_GPIOBEN_Msk            (0x1U << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */\n#define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk\n#define RCC_AHB1ENR_GPIOCEN_Pos            (2U)\n#define RCC_AHB1ENR_GPIOCEN_Msk            (0x1U << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */\n#define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk\n#define RCC_AHB1ENR_GPIODEN_Pos            (3U)\n#define RCC_AHB1ENR_GPIODEN_Msk            (0x1U << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */\n#define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk\n#define RCC_AHB1ENR_GPIOEEN_Pos            (4U)\n#define RCC_AHB1ENR_GPIOEEN_Msk            (0x1U << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */\n#define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk\n#define RCC_AHB1ENR_GPIOFEN_Pos            (5U)\n#define RCC_AHB1ENR_GPIOFEN_Msk            (0x1U << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */\n#define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk\n#define RCC_AHB1ENR_GPIOGEN_Pos            (6U)\n#define RCC_AHB1ENR_GPIOGEN_Msk            (0x1U << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */\n#define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk\n#define RCC_AHB1ENR_GPIOHEN_Pos            (7U)\n#define RCC_AHB1ENR_GPIOHEN_Msk            (0x1U << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk\n#define RCC_AHB1ENR_GPIOIEN_Pos            (8U)\n#define RCC_AHB1ENR_GPIOIEN_Msk            (0x1U << RCC_AHB1ENR_GPIOIEN_Pos)   /*!< 0x00000100 */\n#define RCC_AHB1ENR_GPIOIEN                RCC_AHB1ENR_GPIOIEN_Msk\n#define RCC_AHB1ENR_GPIOJEN_Pos            (9U)\n#define RCC_AHB1ENR_GPIOJEN_Msk            (0x1U << RCC_AHB1ENR_GPIOJEN_Pos)   /*!< 0x00000200 */\n#define RCC_AHB1ENR_GPIOJEN                RCC_AHB1ENR_GPIOJEN_Msk\n#define RCC_AHB1ENR_GPIOKEN_Pos            (10U)\n#define RCC_AHB1ENR_GPIOKEN_Msk            (0x1U << RCC_AHB1ENR_GPIOKEN_Pos)   /*!< 0x00000400 */\n#define RCC_AHB1ENR_GPIOKEN                RCC_AHB1ENR_GPIOKEN_Msk\n#define RCC_AHB1ENR_CRCEN_Pos              (12U)\n#define RCC_AHB1ENR_CRCEN_Msk              (0x1U << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */\n#define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk\n#define RCC_AHB1ENR_BKPSRAMEN_Pos          (18U)\n#define RCC_AHB1ENR_BKPSRAMEN_Msk          (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */\n#define RCC_AHB1ENR_BKPSRAMEN              RCC_AHB1ENR_BKPSRAMEN_Msk\n#define RCC_AHB1ENR_CCMDATARAMEN_Pos       (20U)\n#define RCC_AHB1ENR_CCMDATARAMEN_Msk       (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */\n#define RCC_AHB1ENR_CCMDATARAMEN           RCC_AHB1ENR_CCMDATARAMEN_Msk\n#define RCC_AHB1ENR_DMA1EN_Pos             (21U)\n#define RCC_AHB1ENR_DMA1EN_Msk             (0x1U << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */\n#define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk\n#define RCC_AHB1ENR_DMA2EN_Pos             (22U)\n#define RCC_AHB1ENR_DMA2EN_Msk             (0x1U << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */\n#define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk\n#define RCC_AHB1ENR_DMA2DEN_Pos            (23U)\n#define RCC_AHB1ENR_DMA2DEN_Msk            (0x1U << RCC_AHB1ENR_DMA2DEN_Pos)   /*!< 0x00800000 */\n#define RCC_AHB1ENR_DMA2DEN                RCC_AHB1ENR_DMA2DEN_Msk\n#define RCC_AHB1ENR_ETHMACEN_Pos           (25U)\n#define RCC_AHB1ENR_ETHMACEN_Msk           (0x1U << RCC_AHB1ENR_ETHMACEN_Pos)  /*!< 0x02000000 */\n#define RCC_AHB1ENR_ETHMACEN               RCC_AHB1ENR_ETHMACEN_Msk\n#define RCC_AHB1ENR_ETHMACTXEN_Pos         (26U)\n#define RCC_AHB1ENR_ETHMACTXEN_Msk         (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */\n#define RCC_AHB1ENR_ETHMACTXEN             RCC_AHB1ENR_ETHMACTXEN_Msk\n#define RCC_AHB1ENR_ETHMACRXEN_Pos         (27U)\n#define RCC_AHB1ENR_ETHMACRXEN_Msk         (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */\n#define RCC_AHB1ENR_ETHMACRXEN             RCC_AHB1ENR_ETHMACRXEN_Msk\n#define RCC_AHB1ENR_ETHMACPTPEN_Pos        (28U)\n#define RCC_AHB1ENR_ETHMACPTPEN_Msk        (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */\n#define RCC_AHB1ENR_ETHMACPTPEN            RCC_AHB1ENR_ETHMACPTPEN_Msk\n#define RCC_AHB1ENR_OTGHSEN_Pos            (29U)\n#define RCC_AHB1ENR_OTGHSEN_Msk            (0x1U << RCC_AHB1ENR_OTGHSEN_Pos)   /*!< 0x20000000 */\n#define RCC_AHB1ENR_OTGHSEN                RCC_AHB1ENR_OTGHSEN_Msk\n#define RCC_AHB1ENR_OTGHSULPIEN_Pos        (30U)\n#define RCC_AHB1ENR_OTGHSULPIEN_Msk        (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */\n#define RCC_AHB1ENR_OTGHSULPIEN            RCC_AHB1ENR_OTGHSULPIEN_Msk\n/********************  Bit definition for RCC_AHB2ENR register  ***************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_AHB2_SUPPORT                   /*!< AHB2 Bus is supported */\n\n#define RCC_AHB2ENR_DCMIEN_Pos             (0U)\n#define RCC_AHB2ENR_DCMIEN_Msk             (0x1U << RCC_AHB2ENR_DCMIEN_Pos)    /*!< 0x00000001 */\n#define RCC_AHB2ENR_DCMIEN                 RCC_AHB2ENR_DCMIEN_Msk\n#define RCC_AHB2ENR_RNGEN_Pos              (6U)\n#define RCC_AHB2ENR_RNGEN_Msk              (0x1U << RCC_AHB2ENR_RNGEN_Pos)     /*!< 0x00000040 */\n#define RCC_AHB2ENR_RNGEN                  RCC_AHB2ENR_RNGEN_Msk\n#define RCC_AHB2ENR_OTGFSEN_Pos            (7U)\n#define RCC_AHB2ENR_OTGFSEN_Msk            (0x1U << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk\n\n/********************  Bit definition for RCC_AHB3ENR register  ***************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_AHB3_SUPPORT                   /*!< AHB3 Bus is supported */\n\n#define RCC_AHB3ENR_FMCEN_Pos              (0U)\n#define RCC_AHB3ENR_FMCEN_Msk              (0x1U << RCC_AHB3ENR_FMCEN_Pos)     /*!< 0x00000001 */\n#define RCC_AHB3ENR_FMCEN                  RCC_AHB3ENR_FMCEN_Msk\n#define RCC_AHB3ENR_QSPIEN_Pos             (1U)\n#define RCC_AHB3ENR_QSPIEN_Msk             (0x1U << RCC_AHB3ENR_QSPIEN_Pos)    /*!< 0x00000002 */\n#define RCC_AHB3ENR_QSPIEN                 RCC_AHB3ENR_QSPIEN_Msk\n\n/********************  Bit definition for RCC_APB1ENR register  ***************/\n#define RCC_APB1ENR_TIM2EN_Pos             (0U)\n#define RCC_APB1ENR_TIM2EN_Msk             (0x1U << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk\n#define RCC_APB1ENR_TIM3EN_Pos             (1U)\n#define RCC_APB1ENR_TIM3EN_Msk             (0x1U << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk\n#define RCC_APB1ENR_TIM4EN_Pos             (2U)\n#define RCC_APB1ENR_TIM4EN_Msk             (0x1U << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */\n#define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk\n#define RCC_APB1ENR_TIM5EN_Pos             (3U)\n#define RCC_APB1ENR_TIM5EN_Msk             (0x1U << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */\n#define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk\n#define RCC_APB1ENR_TIM6EN_Pos             (4U)\n#define RCC_APB1ENR_TIM6EN_Msk             (0x1U << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */\n#define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk\n#define RCC_APB1ENR_TIM7EN_Pos             (5U)\n#define RCC_APB1ENR_TIM7EN_Msk             (0x1U << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */\n#define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk\n#define RCC_APB1ENR_TIM12EN_Pos            (6U)\n#define RCC_APB1ENR_TIM12EN_Msk            (0x1U << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */\n#define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk\n#define RCC_APB1ENR_TIM13EN_Pos            (7U)\n#define RCC_APB1ENR_TIM13EN_Msk            (0x1U << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */\n#define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk\n#define RCC_APB1ENR_TIM14EN_Pos            (8U)\n#define RCC_APB1ENR_TIM14EN_Msk            (0x1U << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */\n#define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk\n#define RCC_APB1ENR_WWDGEN_Pos             (11U)\n#define RCC_APB1ENR_WWDGEN_Msk             (0x1U << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk\n#define RCC_APB1ENR_SPI2EN_Pos             (14U)\n#define RCC_APB1ENR_SPI2EN_Msk             (0x1U << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */\n#define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk\n#define RCC_APB1ENR_SPI3EN_Pos             (15U)\n#define RCC_APB1ENR_SPI3EN_Msk             (0x1U << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */\n#define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk\n#define RCC_APB1ENR_USART2EN_Pos           (17U)\n#define RCC_APB1ENR_USART2EN_Msk           (0x1U << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */\n#define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk\n#define RCC_APB1ENR_USART3EN_Pos           (18U)\n#define RCC_APB1ENR_USART3EN_Msk           (0x1U << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */\n#define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk\n#define RCC_APB1ENR_UART4EN_Pos            (19U)\n#define RCC_APB1ENR_UART4EN_Msk            (0x1U << RCC_APB1ENR_UART4EN_Pos)   /*!< 0x00080000 */\n#define RCC_APB1ENR_UART4EN                RCC_APB1ENR_UART4EN_Msk\n#define RCC_APB1ENR_UART5EN_Pos            (20U)\n#define RCC_APB1ENR_UART5EN_Msk            (0x1U << RCC_APB1ENR_UART5EN_Pos)   /*!< 0x00100000 */\n#define RCC_APB1ENR_UART5EN                RCC_APB1ENR_UART5EN_Msk\n#define RCC_APB1ENR_I2C1EN_Pos             (21U)\n#define RCC_APB1ENR_I2C1EN_Msk             (0x1U << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */\n#define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk\n#define RCC_APB1ENR_I2C2EN_Pos             (22U)\n#define RCC_APB1ENR_I2C2EN_Msk             (0x1U << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */\n#define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk\n#define RCC_APB1ENR_I2C3EN_Pos             (23U)\n#define RCC_APB1ENR_I2C3EN_Msk             (0x1U << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */\n#define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk\n#define RCC_APB1ENR_CAN1EN_Pos             (25U)\n#define RCC_APB1ENR_CAN1EN_Msk             (0x1U << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */\n#define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk\n#define RCC_APB1ENR_CAN2EN_Pos             (26U)\n#define RCC_APB1ENR_CAN2EN_Msk             (0x1U << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */\n#define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk\n#define RCC_APB1ENR_PWREN_Pos              (28U)\n#define RCC_APB1ENR_PWREN_Msk              (0x1U << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */\n#define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk\n#define RCC_APB1ENR_DACEN_Pos              (29U)\n#define RCC_APB1ENR_DACEN_Msk              (0x1U << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */\n#define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk\n#define RCC_APB1ENR_UART7EN_Pos            (30U)\n#define RCC_APB1ENR_UART7EN_Msk            (0x1U << RCC_APB1ENR_UART7EN_Pos)   /*!< 0x40000000 */\n#define RCC_APB1ENR_UART7EN                RCC_APB1ENR_UART7EN_Msk\n#define RCC_APB1ENR_UART8EN_Pos            (31U)\n#define RCC_APB1ENR_UART8EN_Msk            (0x1U << RCC_APB1ENR_UART8EN_Pos)   /*!< 0x80000000 */\n#define RCC_APB1ENR_UART8EN                RCC_APB1ENR_UART8EN_Msk\n\n/********************  Bit definition for RCC_APB2ENR register  ***************/\n#define RCC_APB2ENR_TIM1EN_Pos             (0U)\n#define RCC_APB2ENR_TIM1EN_Msk             (0x1U << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk\n#define RCC_APB2ENR_TIM8EN_Pos             (1U)\n#define RCC_APB2ENR_TIM8EN_Msk             (0x1U << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk\n#define RCC_APB2ENR_USART1EN_Pos           (4U)\n#define RCC_APB2ENR_USART1EN_Msk           (0x1U << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */\n#define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk\n#define RCC_APB2ENR_USART6EN_Pos           (5U)\n#define RCC_APB2ENR_USART6EN_Msk           (0x1U << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */\n#define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk\n#define RCC_APB2ENR_ADC1EN_Pos             (8U)\n#define RCC_APB2ENR_ADC1EN_Msk             (0x1U << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */\n#define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk\n#define RCC_APB2ENR_ADC2EN_Pos             (9U)\n#define RCC_APB2ENR_ADC2EN_Msk             (0x1U << RCC_APB2ENR_ADC2EN_Pos)    /*!< 0x00000200 */\n#define RCC_APB2ENR_ADC2EN                 RCC_APB2ENR_ADC2EN_Msk\n#define RCC_APB2ENR_ADC3EN_Pos             (10U)\n#define RCC_APB2ENR_ADC3EN_Msk             (0x1U << RCC_APB2ENR_ADC3EN_Pos)    /*!< 0x00000400 */\n#define RCC_APB2ENR_ADC3EN                 RCC_APB2ENR_ADC3EN_Msk\n#define RCC_APB2ENR_SDIOEN_Pos             (11U)\n#define RCC_APB2ENR_SDIOEN_Msk             (0x1U << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk\n#define RCC_APB2ENR_SPI1EN_Pos             (12U)\n#define RCC_APB2ENR_SPI1EN_Msk             (0x1U << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */\n#define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk\n#define RCC_APB2ENR_SPI4EN_Pos             (13U)\n#define RCC_APB2ENR_SPI4EN_Msk             (0x1U << RCC_APB2ENR_SPI4EN_Pos)    /*!< 0x00002000 */\n#define RCC_APB2ENR_SPI4EN                 RCC_APB2ENR_SPI4EN_Msk\n#define RCC_APB2ENR_SYSCFGEN_Pos           (14U)\n#define RCC_APB2ENR_SYSCFGEN_Msk           (0x1U << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */\n#define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk\n#define RCC_APB2ENR_TIM9EN_Pos             (16U)\n#define RCC_APB2ENR_TIM9EN_Msk             (0x1U << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */\n#define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk\n#define RCC_APB2ENR_TIM10EN_Pos            (17U)\n#define RCC_APB2ENR_TIM10EN_Msk            (0x1U << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */\n#define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk\n#define RCC_APB2ENR_TIM11EN_Pos            (18U)\n#define RCC_APB2ENR_TIM11EN_Msk            (0x1U << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */\n#define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk\n#define RCC_APB2ENR_SPI5EN_Pos             (20U)\n#define RCC_APB2ENR_SPI5EN_Msk             (0x1U << RCC_APB2ENR_SPI5EN_Pos)    /*!< 0x00100000 */\n#define RCC_APB2ENR_SPI5EN                 RCC_APB2ENR_SPI5EN_Msk\n#define RCC_APB2ENR_SPI6EN_Pos             (21U)\n#define RCC_APB2ENR_SPI6EN_Msk             (0x1U << RCC_APB2ENR_SPI6EN_Pos)    /*!< 0x00200000 */\n#define RCC_APB2ENR_SPI6EN                 RCC_APB2ENR_SPI6EN_Msk\n#define RCC_APB2ENR_SAI1EN_Pos             (22U)\n#define RCC_APB2ENR_SAI1EN_Msk             (0x1U << RCC_APB2ENR_SAI1EN_Pos)    /*!< 0x00400000 */\n#define RCC_APB2ENR_SAI1EN                 RCC_APB2ENR_SAI1EN_Msk\n#define RCC_APB2ENR_LTDCEN_Pos             (26U)\n#define RCC_APB2ENR_LTDCEN_Msk             (0x1U << RCC_APB2ENR_LTDCEN_Pos)    /*!< 0x04000000 */\n#define RCC_APB2ENR_LTDCEN                 RCC_APB2ENR_LTDCEN_Msk\n#define RCC_APB2ENR_DSIEN_Pos              (27U)\n#define RCC_APB2ENR_DSIEN_Msk              (0x1U << RCC_APB2ENR_DSIEN_Pos)     /*!< 0x08000000 */\n#define RCC_APB2ENR_DSIEN                  RCC_APB2ENR_DSIEN_Msk\n\n/********************  Bit definition for RCC_AHB1LPENR register  *************/\n#define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)\n#define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk\n#define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)\n#define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk\n#define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)\n#define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */\n#define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk\n#define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)\n#define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */\n#define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk\n#define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)\n#define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */\n#define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk\n#define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)\n#define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */\n#define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk\n#define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)\n#define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk\n#define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)\n#define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk\n#define RCC_AHB1LPENR_GPIOILPEN_Pos        (8U)\n#define RCC_AHB1LPENR_GPIOILPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */\n#define RCC_AHB1LPENR_GPIOILPEN            RCC_AHB1LPENR_GPIOILPEN_Msk\n#define RCC_AHB1LPENR_GPIOJLPEN_Pos        (9U)\n#define RCC_AHB1LPENR_GPIOJLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */\n#define RCC_AHB1LPENR_GPIOJLPEN            RCC_AHB1LPENR_GPIOJLPEN_Msk\n#define RCC_AHB1LPENR_GPIOKLPEN_Pos        (10U)\n#define RCC_AHB1LPENR_GPIOKLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */\n#define RCC_AHB1LPENR_GPIOKLPEN            RCC_AHB1LPENR_GPIOKLPEN_Msk\n#define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)\n#define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */\n#define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk\n#define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)\n#define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */\n#define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk\n#define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)\n#define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */\n#define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk\n#define RCC_AHB1LPENR_SRAM2LPEN_Pos        (17U)\n#define RCC_AHB1LPENR_SRAM2LPEN_Msk        (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */\n#define RCC_AHB1LPENR_SRAM2LPEN            RCC_AHB1LPENR_SRAM2LPEN_Msk\n#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos      (18U)\n#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk      (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */\n#define RCC_AHB1LPENR_BKPSRAMLPEN          RCC_AHB1LPENR_BKPSRAMLPEN_Msk\n#define RCC_AHB1LPENR_SRAM3LPEN_Pos        (19U)\n#define RCC_AHB1LPENR_SRAM3LPEN_Msk        (0x1U << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */\n#define RCC_AHB1LPENR_SRAM3LPEN            RCC_AHB1LPENR_SRAM3LPEN_Msk\n#define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)\n#define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk\n#define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)\n#define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk\n#define RCC_AHB1LPENR_DMA2DLPEN_Pos        (23U)\n#define RCC_AHB1LPENR_DMA2DLPEN_Msk        (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */\n#define RCC_AHB1LPENR_DMA2DLPEN            RCC_AHB1LPENR_DMA2DLPEN_Msk\n\n#define RCC_AHB1LPENR_ETHMACLPEN_Pos       (25U)\n#define RCC_AHB1LPENR_ETHMACLPEN_Msk       (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */\n#define RCC_AHB1LPENR_ETHMACLPEN           RCC_AHB1LPENR_ETHMACLPEN_Msk\n#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos     (26U)\n#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk     (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */\n#define RCC_AHB1LPENR_ETHMACTXLPEN         RCC_AHB1LPENR_ETHMACTXLPEN_Msk\n#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos     (27U)\n#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk     (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */\n#define RCC_AHB1LPENR_ETHMACRXLPEN         RCC_AHB1LPENR_ETHMACRXLPEN_Msk\n#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos    (28U)\n#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk    (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */\n#define RCC_AHB1LPENR_ETHMACPTPLPEN        RCC_AHB1LPENR_ETHMACPTPLPEN_Msk\n#define RCC_AHB1LPENR_OTGHSLPEN_Pos        (29U)\n#define RCC_AHB1LPENR_OTGHSLPEN_Msk        (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */\n#define RCC_AHB1LPENR_OTGHSLPEN            RCC_AHB1LPENR_OTGHSLPEN_Msk\n#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos    (30U)\n#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk    (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */\n#define RCC_AHB1LPENR_OTGHSULPILPEN        RCC_AHB1LPENR_OTGHSULPILPEN_Msk\n\n/********************  Bit definition for RCC_AHB2LPENR register  *************/\n#define RCC_AHB2LPENR_DCMILPEN_Pos         (0U)\n#define RCC_AHB2LPENR_DCMILPEN_Msk         (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB2LPENR_DCMILPEN             RCC_AHB2LPENR_DCMILPEN_Msk\n#define RCC_AHB2LPENR_RNGLPEN_Pos          (6U)\n#define RCC_AHB2LPENR_RNGLPEN_Msk          (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB2LPENR_RNGLPEN              RCC_AHB2LPENR_RNGLPEN_Msk\n#define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)\n#define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk\n\n/********************  Bit definition for RCC_AHB3LPENR register  *************/\n#define RCC_AHB3LPENR_FMCLPEN_Pos          (0U)\n#define RCC_AHB3LPENR_FMCLPEN_Msk          (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB3LPENR_FMCLPEN              RCC_AHB3LPENR_FMCLPEN_Msk\n#define RCC_AHB3LPENR_QSPILPEN_Pos         (1U)\n#define RCC_AHB3LPENR_QSPILPEN_Msk         (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB3LPENR_QSPILPEN             RCC_AHB3LPENR_QSPILPEN_Msk\n\n/********************  Bit definition for RCC_APB1LPENR register  *************/\n#define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)\n#define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk\n#define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)\n#define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk\n#define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)\n#define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */\n#define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk\n#define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)\n#define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */\n#define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk\n#define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)\n#define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk\n#define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)\n#define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk\n#define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)\n#define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */\n#define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk\n#define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)\n#define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */\n#define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk\n#define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)\n#define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk\n#define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)\n#define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk\n#define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)\n#define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk\n#define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)\n#define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */\n#define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk\n#define RCC_APB1LPENR_USART2LPEN_Pos       (17U)\n#define RCC_APB1LPENR_USART2LPEN_Msk       (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk\n#define RCC_APB1LPENR_USART3LPEN_Pos       (18U)\n#define RCC_APB1LPENR_USART3LPEN_Msk       (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk\n#define RCC_APB1LPENR_UART4LPEN_Pos        (19U)\n#define RCC_APB1LPENR_UART4LPEN_Msk        (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */\n#define RCC_APB1LPENR_UART4LPEN            RCC_APB1LPENR_UART4LPEN_Msk\n#define RCC_APB1LPENR_UART5LPEN_Pos        (20U)\n#define RCC_APB1LPENR_UART5LPEN_Msk        (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */\n#define RCC_APB1LPENR_UART5LPEN            RCC_APB1LPENR_UART5LPEN_Msk\n#define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)\n#define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk\n#define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)\n#define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk\n#define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)\n#define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */\n#define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk\n#define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)\n#define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */\n#define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk\n#define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)\n#define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */\n#define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk\n#define RCC_APB1LPENR_PWRLPEN_Pos          (28U)\n#define RCC_APB1LPENR_PWRLPEN_Msk          (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */\n#define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk\n#define RCC_APB1LPENR_DACLPEN_Pos          (29U)\n#define RCC_APB1LPENR_DACLPEN_Msk          (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */\n#define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk\n#define RCC_APB1LPENR_UART7LPEN_Pos        (30U)\n#define RCC_APB1LPENR_UART7LPEN_Msk        (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */\n#define RCC_APB1LPENR_UART7LPEN            RCC_APB1LPENR_UART7LPEN_Msk\n#define RCC_APB1LPENR_UART8LPEN_Pos        (31U)\n#define RCC_APB1LPENR_UART8LPEN_Msk        (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */\n#define RCC_APB1LPENR_UART8LPEN            RCC_APB1LPENR_UART8LPEN_Msk\n\n/********************  Bit definition for RCC_APB2LPENR register  *************/\n#define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)\n#define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk\n#define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)\n#define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk\n#define RCC_APB2LPENR_USART1LPEN_Pos       (4U)\n#define RCC_APB2LPENR_USART1LPEN_Msk       (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk\n#define RCC_APB2LPENR_USART6LPEN_Pos       (5U)\n#define RCC_APB2LPENR_USART6LPEN_Msk       (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk\n#define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)\n#define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk\n#define RCC_APB2LPENR_ADC2LPEN_Pos         (9U)\n#define RCC_APB2LPENR_ADC2LPEN_Msk         (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */\n#define RCC_APB2LPENR_ADC2LPEN             RCC_APB2LPENR_ADC2LPEN_Msk\n#define RCC_APB2LPENR_ADC3LPEN_Pos         (10U)\n#define RCC_APB2LPENR_ADC3LPEN_Msk         (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */\n#define RCC_APB2LPENR_ADC3LPEN             RCC_APB2LPENR_ADC3LPEN_Msk\n#define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)\n#define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk\n#define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)\n#define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */\n#define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk\n#define RCC_APB2LPENR_SPI4LPEN_Pos         (13U)\n#define RCC_APB2LPENR_SPI4LPEN_Msk         (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */\n#define RCC_APB2LPENR_SPI4LPEN             RCC_APB2LPENR_SPI4LPEN_Msk\n#define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)\n#define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk\n#define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)\n#define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */\n#define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk\n#define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)\n#define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk\n#define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)\n#define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk\n#define RCC_APB2LPENR_SPI5LPEN_Pos         (20U)\n#define RCC_APB2LPENR_SPI5LPEN_Msk         (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */\n#define RCC_APB2LPENR_SPI5LPEN             RCC_APB2LPENR_SPI5LPEN_Msk\n#define RCC_APB2LPENR_SPI6LPEN_Pos         (21U)\n#define RCC_APB2LPENR_SPI6LPEN_Msk         (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */\n#define RCC_APB2LPENR_SPI6LPEN             RCC_APB2LPENR_SPI6LPEN_Msk\n#define RCC_APB2LPENR_SAI1LPEN_Pos         (22U)\n#define RCC_APB2LPENR_SAI1LPEN_Msk         (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */\n#define RCC_APB2LPENR_SAI1LPEN             RCC_APB2LPENR_SAI1LPEN_Msk\n#define RCC_APB2LPENR_LTDCLPEN_Pos         (26U)\n#define RCC_APB2LPENR_LTDCLPEN_Msk         (0x1U << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */\n#define RCC_APB2LPENR_LTDCLPEN             RCC_APB2LPENR_LTDCLPEN_Msk\n#define RCC_APB2LPENR_DSILPEN_Pos          (27U)\n#define RCC_APB2LPENR_DSILPEN_Msk          (0x1U << RCC_APB2LPENR_DSILPEN_Pos) /*!< 0x08000000 */\n#define RCC_APB2LPENR_DSILPEN              RCC_APB2LPENR_DSILPEN_Msk\n\n/********************  Bit definition for RCC_BDCR register  ******************/\n#define RCC_BDCR_LSEON_Pos                 (0U)\n#define RCC_BDCR_LSEON_Msk                 (0x1U << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */\n#define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk\n#define RCC_BDCR_LSERDY_Pos                (1U)\n#define RCC_BDCR_LSERDY_Msk                (0x1U << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */\n#define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk\n#define RCC_BDCR_LSEBYP_Pos                (2U)\n#define RCC_BDCR_LSEBYP_Msk                (0x1U << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */\n#define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk\n#define RCC_BDCR_LSEMOD_Pos                (3U)\n#define RCC_BDCR_LSEMOD_Msk                (0x1U << RCC_BDCR_LSEMOD_Pos)       /*!< 0x00000008 */\n#define RCC_BDCR_LSEMOD                    RCC_BDCR_LSEMOD_Msk\n\n#define RCC_BDCR_RTCSEL_Pos                (8U)\n#define RCC_BDCR_RTCSEL_Msk                (0x3U << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */\n#define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk\n#define RCC_BDCR_RTCSEL_0                  (0x1U << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */\n#define RCC_BDCR_RTCSEL_1                  (0x2U << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */\n\n#define RCC_BDCR_RTCEN_Pos                 (15U)\n#define RCC_BDCR_RTCEN_Msk                 (0x1U << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */\n#define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk\n#define RCC_BDCR_BDRST_Pos                 (16U)\n#define RCC_BDCR_BDRST_Msk                 (0x1U << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */\n#define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk\n\n/********************  Bit definition for RCC_CSR register  *******************/\n#define RCC_CSR_LSION_Pos                  (0U)\n#define RCC_CSR_LSION_Msk                  (0x1U << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */\n#define RCC_CSR_LSION                      RCC_CSR_LSION_Msk\n#define RCC_CSR_LSIRDY_Pos                 (1U)\n#define RCC_CSR_LSIRDY_Msk                 (0x1U << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */\n#define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk\n#define RCC_CSR_RMVF_Pos                   (24U)\n#define RCC_CSR_RMVF_Msk                   (0x1U << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */\n#define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk\n#define RCC_CSR_BORRSTF_Pos                (25U)\n#define RCC_CSR_BORRSTF_Msk                (0x1U << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */\n#define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk\n#define RCC_CSR_PINRSTF_Pos                (26U)\n#define RCC_CSR_PINRSTF_Msk                (0x1U << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */\n#define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk\n#define RCC_CSR_PORRSTF_Pos                (27U)\n#define RCC_CSR_PORRSTF_Msk                (0x1U << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */\n#define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk\n#define RCC_CSR_SFTRSTF_Pos                (28U)\n#define RCC_CSR_SFTRSTF_Msk                (0x1U << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */\n#define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk\n#define RCC_CSR_IWDGRSTF_Pos               (29U)\n#define RCC_CSR_IWDGRSTF_Msk               (0x1U << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */\n#define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk\n#define RCC_CSR_WWDGRSTF_Pos               (30U)\n#define RCC_CSR_WWDGRSTF_Msk               (0x1U << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */\n#define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk\n#define RCC_CSR_LPWRRSTF_Pos               (31U)\n#define RCC_CSR_LPWRRSTF_Msk               (0x1U << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */\n#define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk\n/* Legacy defines */\n#define RCC_CSR_PADRSTF                    RCC_CSR_PINRSTF\n#define RCC_CSR_WDGRSTF                    RCC_CSR_IWDGRSTF\n\n/********************  Bit definition for RCC_SSCGR register  *****************/\n#define RCC_SSCGR_MODPER_Pos               (0U)\n#define RCC_SSCGR_MODPER_Msk               (0x1FFFU << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */\n#define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk\n#define RCC_SSCGR_INCSTEP_Pos              (13U)\n#define RCC_SSCGR_INCSTEP_Msk              (0x7FFFU << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */\n#define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk\n#define RCC_SSCGR_SPREADSEL_Pos            (30U)\n#define RCC_SSCGR_SPREADSEL_Msk            (0x1U << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */\n#define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk\n#define RCC_SSCGR_SSCGEN_Pos               (31U)\n#define RCC_SSCGR_SSCGEN_Msk               (0x1U << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */\n#define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk\n\n/********************  Bit definition for RCC_PLLI2SCFGR register  ************/\n#define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)\n#define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */\n#define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk\n#define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */\n#define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */\n#define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */\n#define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */\n#define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */\n#define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */\n#define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */\n\n#define RCC_PLLI2SCFGR_PLLI2SQ_Pos         (24U)\n#define RCC_PLLI2SCFGR_PLLI2SQ_Msk         (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ             RCC_PLLI2SCFGR_PLLI2SQ_Msk\n#define RCC_PLLI2SCFGR_PLLI2SQ_0           (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_1           (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_2           (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_3           (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)\n#define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk\n#define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for RCC_PLLSAICFGR register  ************/\n#define RCC_PLLSAICFGR_PLLSAIN_Pos         (6U)\n#define RCC_PLLSAICFGR_PLLSAIN_Msk         (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */\n#define RCC_PLLSAICFGR_PLLSAIN             RCC_PLLSAICFGR_PLLSAIN_Msk\n#define RCC_PLLSAICFGR_PLLSAIN_0           (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */\n#define RCC_PLLSAICFGR_PLLSAIN_1           (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */\n#define RCC_PLLSAICFGR_PLLSAIN_2           (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */\n#define RCC_PLLSAICFGR_PLLSAIN_3           (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */\n#define RCC_PLLSAICFGR_PLLSAIN_4           (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */\n#define RCC_PLLSAICFGR_PLLSAIN_5           (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */\n#define RCC_PLLSAICFGR_PLLSAIN_6           (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */\n#define RCC_PLLSAICFGR_PLLSAIN_7           (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */\n#define RCC_PLLSAICFGR_PLLSAIN_8           (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */\n\n#define RCC_PLLSAICFGR_PLLSAIP_Pos         (16U)\n#define RCC_PLLSAICFGR_PLLSAIP_Msk         (0x3U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */\n#define RCC_PLLSAICFGR_PLLSAIP             RCC_PLLSAICFGR_PLLSAIP_Msk\n#define RCC_PLLSAICFGR_PLLSAIP_0           (0x1U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */\n#define RCC_PLLSAICFGR_PLLSAIP_1           (0x2U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */\n\n#define RCC_PLLSAICFGR_PLLSAIQ_Pos         (24U)\n#define RCC_PLLSAICFGR_PLLSAIQ_Msk         (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */\n#define RCC_PLLSAICFGR_PLLSAIQ             RCC_PLLSAICFGR_PLLSAIQ_Msk\n#define RCC_PLLSAICFGR_PLLSAIQ_0           (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */\n#define RCC_PLLSAICFGR_PLLSAIQ_1           (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */\n#define RCC_PLLSAICFGR_PLLSAIQ_2           (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */\n#define RCC_PLLSAICFGR_PLLSAIQ_3           (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */\n\n#define RCC_PLLSAICFGR_PLLSAIR_Pos         (28U)\n#define RCC_PLLSAICFGR_PLLSAIR_Msk         (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */\n#define RCC_PLLSAICFGR_PLLSAIR             RCC_PLLSAICFGR_PLLSAIR_Msk\n#define RCC_PLLSAICFGR_PLLSAIR_0           (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */\n#define RCC_PLLSAICFGR_PLLSAIR_1           (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */\n#define RCC_PLLSAICFGR_PLLSAIR_2           (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for RCC_DCKCFGR register  ***************/\n#define RCC_DCKCFGR_PLLI2SDIVQ_Pos        (0U)\n#define RCC_DCKCFGR_PLLI2SDIVQ_Msk        (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */\n#define RCC_DCKCFGR_PLLI2SDIVQ            RCC_DCKCFGR_PLLI2SDIVQ_Msk\n#define RCC_DCKCFGR_PLLI2SDIVQ_0          (0x01U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */\n#define RCC_DCKCFGR_PLLI2SDIVQ_1          (0x02U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */\n#define RCC_DCKCFGR_PLLI2SDIVQ_2          (0x04U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */\n#define RCC_DCKCFGR_PLLI2SDIVQ_3          (0x08U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */\n#define RCC_DCKCFGR_PLLI2SDIVQ_4          (0x10U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */\n\n#define RCC_DCKCFGR_PLLSAIDIVQ_Pos        (8U)\n#define RCC_DCKCFGR_PLLSAIDIVQ_Msk        (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */\n#define RCC_DCKCFGR_PLLSAIDIVQ            RCC_DCKCFGR_PLLSAIDIVQ_Msk\n#define RCC_DCKCFGR_PLLSAIDIVQ_0          (0x01U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */\n#define RCC_DCKCFGR_PLLSAIDIVQ_1          (0x02U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */\n#define RCC_DCKCFGR_PLLSAIDIVQ_2          (0x04U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */\n#define RCC_DCKCFGR_PLLSAIDIVQ_3          (0x08U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */\n#define RCC_DCKCFGR_PLLSAIDIVQ_4          (0x10U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */\n#define RCC_DCKCFGR_PLLSAIDIVR_Pos        (16U)\n#define RCC_DCKCFGR_PLLSAIDIVR_Msk        (0x3U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */\n#define RCC_DCKCFGR_PLLSAIDIVR            RCC_DCKCFGR_PLLSAIDIVR_Msk\n#define RCC_DCKCFGR_PLLSAIDIVR_0          (0x1U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */\n#define RCC_DCKCFGR_PLLSAIDIVR_1          (0x2U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */\n\n#define RCC_DCKCFGR_SAI1ASRC_Pos           (20U)\n#define RCC_DCKCFGR_SAI1ASRC_Msk           (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00300000 */\n#define RCC_DCKCFGR_SAI1ASRC               RCC_DCKCFGR_SAI1ASRC_Msk\n#define RCC_DCKCFGR_SAI1ASRC_0             (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00100000 */\n#define RCC_DCKCFGR_SAI1ASRC_1             (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00200000 */\n#define RCC_DCKCFGR_SAI1BSRC_Pos           (22U)\n#define RCC_DCKCFGR_SAI1BSRC_Msk           (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00C00000 */\n#define RCC_DCKCFGR_SAI1BSRC               RCC_DCKCFGR_SAI1BSRC_Msk\n#define RCC_DCKCFGR_SAI1BSRC_0             (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00400000 */\n#define RCC_DCKCFGR_SAI1BSRC_1             (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00800000 */\n#define RCC_DCKCFGR_TIMPRE_Pos             (24U)\n#define RCC_DCKCFGR_TIMPRE_Msk             (0x1U << RCC_DCKCFGR_TIMPRE_Pos)    /*!< 0x01000000 */\n#define RCC_DCKCFGR_TIMPRE                 RCC_DCKCFGR_TIMPRE_Msk\n#define RCC_DCKCFGR_CK48MSEL_Pos           (27U)\n#define RCC_DCKCFGR_CK48MSEL_Msk           (0x1U << RCC_DCKCFGR_CK48MSEL_Pos)  /*!< 0x08000000 */\n#define RCC_DCKCFGR_CK48MSEL               RCC_DCKCFGR_CK48MSEL_Msk\n#define RCC_DCKCFGR_SDIOSEL_Pos            (28U)\n#define RCC_DCKCFGR_SDIOSEL_Msk            (0x1U << RCC_DCKCFGR_SDIOSEL_Pos)   /*!< 0x10000000 */\n#define RCC_DCKCFGR_SDIOSEL                RCC_DCKCFGR_SDIOSEL_Msk\n#define RCC_DCKCFGR_DSISEL_Pos             (29U)\n#define RCC_DCKCFGR_DSISEL_Msk             (0x1U << RCC_DCKCFGR_DSISEL_Pos)    /*!< 0x20000000 */\n#define RCC_DCKCFGR_DSISEL                 RCC_DCKCFGR_DSISEL_Msk\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    RNG                                     */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RNG_CR register  *******************/\n#define RNG_CR_RNGEN_Pos    (2U)\n#define RNG_CR_RNGEN_Msk    (0x1U << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */\n#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk\n#define RNG_CR_IE_Pos       (3U)\n#define RNG_CR_IE_Msk       (0x1U << RNG_CR_IE_Pos)                            /*!< 0x00000008 */\n#define RNG_CR_IE           RNG_CR_IE_Msk\n\n/********************  Bits definition for RNG_SR register  *******************/\n#define RNG_SR_DRDY_Pos     (0U)\n#define RNG_SR_DRDY_Msk     (0x1U << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */\n#define RNG_SR_DRDY         RNG_SR_DRDY_Msk\n#define RNG_SR_CECS_Pos     (1U)\n#define RNG_SR_CECS_Msk     (0x1U << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */\n#define RNG_SR_CECS         RNG_SR_CECS_Msk\n#define RNG_SR_SECS_Pos     (2U)\n#define RNG_SR_SECS_Msk     (0x1U << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */\n#define RNG_SR_SECS         RNG_SR_SECS_Msk\n#define RNG_SR_CEIS_Pos     (5U)\n#define RNG_SR_CEIS_Msk     (0x1U << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */\n#define RNG_SR_CEIS         RNG_SR_CEIS_Msk\n#define RNG_SR_SEIS_Pos     (6U)\n#define RNG_SR_SEIS_Msk     (0x1U << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */\n#define RNG_SR_SEIS         RNG_SR_SEIS_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Real-Time Clock (RTC)                            */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions  (not present on all devices in the STM32F4 serie)\n */\n#define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */\n#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */\n/********************  Bits definition for RTC_TR register  *******************/\n#define RTC_TR_PM_Pos                 (22U)\n#define RTC_TR_PM_Msk                 (0x1U << RTC_TR_PM_Pos)                  /*!< 0x00400000 */\n#define RTC_TR_PM                     RTC_TR_PM_Msk\n#define RTC_TR_HT_Pos                 (20U)\n#define RTC_TR_HT_Msk                 (0x3U << RTC_TR_HT_Pos)                  /*!< 0x00300000 */\n#define RTC_TR_HT                     RTC_TR_HT_Msk\n#define RTC_TR_HT_0                   (0x1U << RTC_TR_HT_Pos)                  /*!< 0x00100000 */\n#define RTC_TR_HT_1                   (0x2U << RTC_TR_HT_Pos)                  /*!< 0x00200000 */\n#define RTC_TR_HU_Pos                 (16U)\n#define RTC_TR_HU_Msk                 (0xFU << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */\n#define RTC_TR_HU                     RTC_TR_HU_Msk\n#define RTC_TR_HU_0                   (0x1U << RTC_TR_HU_Pos)                  /*!< 0x00010000 */\n#define RTC_TR_HU_1                   (0x2U << RTC_TR_HU_Pos)                  /*!< 0x00020000 */\n#define RTC_TR_HU_2                   (0x4U << RTC_TR_HU_Pos)                  /*!< 0x00040000 */\n#define RTC_TR_HU_3                   (0x8U << RTC_TR_HU_Pos)                  /*!< 0x00080000 */\n#define RTC_TR_MNT_Pos                (12U)\n#define RTC_TR_MNT_Msk                (0x7U << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */\n#define RTC_TR_MNT                    RTC_TR_MNT_Msk\n#define RTC_TR_MNT_0                  (0x1U << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */\n#define RTC_TR_MNT_1                  (0x2U << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */\n#define RTC_TR_MNT_2                  (0x4U << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */\n#define RTC_TR_MNU_Pos                (8U)\n#define RTC_TR_MNU_Msk                (0xFU << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */\n#define RTC_TR_MNU                    RTC_TR_MNU_Msk\n#define RTC_TR_MNU_0                  (0x1U << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */\n#define RTC_TR_MNU_1                  (0x2U << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */\n#define RTC_TR_MNU_2                  (0x4U << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */\n#define RTC_TR_MNU_3                  (0x8U << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */\n#define RTC_TR_ST_Pos                 (4U)\n#define RTC_TR_ST_Msk                 (0x7U << RTC_TR_ST_Pos)                  /*!< 0x00000070 */\n#define RTC_TR_ST                     RTC_TR_ST_Msk\n#define RTC_TR_ST_0                   (0x1U << RTC_TR_ST_Pos)                  /*!< 0x00000010 */\n#define RTC_TR_ST_1                   (0x2U << RTC_TR_ST_Pos)                  /*!< 0x00000020 */\n#define RTC_TR_ST_2                   (0x4U << RTC_TR_ST_Pos)                  /*!< 0x00000040 */\n#define RTC_TR_SU_Pos                 (0U)\n#define RTC_TR_SU_Msk                 (0xFU << RTC_TR_SU_Pos)                  /*!< 0x0000000F */\n#define RTC_TR_SU                     RTC_TR_SU_Msk\n#define RTC_TR_SU_0                   (0x1U << RTC_TR_SU_Pos)                  /*!< 0x00000001 */\n#define RTC_TR_SU_1                   (0x2U << RTC_TR_SU_Pos)                  /*!< 0x00000002 */\n#define RTC_TR_SU_2                   (0x4U << RTC_TR_SU_Pos)                  /*!< 0x00000004 */\n#define RTC_TR_SU_3                   (0x8U << RTC_TR_SU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_DR register  *******************/\n#define RTC_DR_YT_Pos                 (20U)\n#define RTC_DR_YT_Msk                 (0xFU << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */\n#define RTC_DR_YT                     RTC_DR_YT_Msk\n#define RTC_DR_YT_0                   (0x1U << RTC_DR_YT_Pos)                  /*!< 0x00100000 */\n#define RTC_DR_YT_1                   (0x2U << RTC_DR_YT_Pos)                  /*!< 0x00200000 */\n#define RTC_DR_YT_2                   (0x4U << RTC_DR_YT_Pos)                  /*!< 0x00400000 */\n#define RTC_DR_YT_3                   (0x8U << RTC_DR_YT_Pos)                  /*!< 0x00800000 */\n#define RTC_DR_YU_Pos                 (16U)\n#define RTC_DR_YU_Msk                 (0xFU << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */\n#define RTC_DR_YU                     RTC_DR_YU_Msk\n#define RTC_DR_YU_0                   (0x1U << RTC_DR_YU_Pos)                  /*!< 0x00010000 */\n#define RTC_DR_YU_1                   (0x2U << RTC_DR_YU_Pos)                  /*!< 0x00020000 */\n#define RTC_DR_YU_2                   (0x4U << RTC_DR_YU_Pos)                  /*!< 0x00040000 */\n#define RTC_DR_YU_3                   (0x8U << RTC_DR_YU_Pos)                  /*!< 0x00080000 */\n#define RTC_DR_WDU_Pos                (13U)\n#define RTC_DR_WDU_Msk                (0x7U << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */\n#define RTC_DR_WDU                    RTC_DR_WDU_Msk\n#define RTC_DR_WDU_0                  (0x1U << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */\n#define RTC_DR_WDU_1                  (0x2U << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */\n#define RTC_DR_WDU_2                  (0x4U << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */\n#define RTC_DR_MT_Pos                 (12U)\n#define RTC_DR_MT_Msk                 (0x1U << RTC_DR_MT_Pos)                  /*!< 0x00001000 */\n#define RTC_DR_MT                     RTC_DR_MT_Msk\n#define RTC_DR_MU_Pos                 (8U)\n#define RTC_DR_MU_Msk                 (0xFU << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */\n#define RTC_DR_MU                     RTC_DR_MU_Msk\n#define RTC_DR_MU_0                   (0x1U << RTC_DR_MU_Pos)                  /*!< 0x00000100 */\n#define RTC_DR_MU_1                   (0x2U << RTC_DR_MU_Pos)                  /*!< 0x00000200 */\n#define RTC_DR_MU_2                   (0x4U << RTC_DR_MU_Pos)                  /*!< 0x00000400 */\n#define RTC_DR_MU_3                   (0x8U << RTC_DR_MU_Pos)                  /*!< 0x00000800 */\n#define RTC_DR_DT_Pos                 (4U)\n#define RTC_DR_DT_Msk                 (0x3U << RTC_DR_DT_Pos)                  /*!< 0x00000030 */\n#define RTC_DR_DT                     RTC_DR_DT_Msk\n#define RTC_DR_DT_0                   (0x1U << RTC_DR_DT_Pos)                  /*!< 0x00000010 */\n#define RTC_DR_DT_1                   (0x2U << RTC_DR_DT_Pos)                  /*!< 0x00000020 */\n#define RTC_DR_DU_Pos                 (0U)\n#define RTC_DR_DU_Msk                 (0xFU << RTC_DR_DU_Pos)                  /*!< 0x0000000F */\n#define RTC_DR_DU                     RTC_DR_DU_Msk\n#define RTC_DR_DU_0                   (0x1U << RTC_DR_DU_Pos)                  /*!< 0x00000001 */\n#define RTC_DR_DU_1                   (0x2U << RTC_DR_DU_Pos)                  /*!< 0x00000002 */\n#define RTC_DR_DU_2                   (0x4U << RTC_DR_DU_Pos)                  /*!< 0x00000004 */\n#define RTC_DR_DU_3                   (0x8U << RTC_DR_DU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_CR register  *******************/\n#define RTC_CR_COE_Pos                (23U)\n#define RTC_CR_COE_Msk                (0x1U << RTC_CR_COE_Pos)                 /*!< 0x00800000 */\n#define RTC_CR_COE                    RTC_CR_COE_Msk\n#define RTC_CR_OSEL_Pos               (21U)\n#define RTC_CR_OSEL_Msk               (0x3U << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */\n#define RTC_CR_OSEL                   RTC_CR_OSEL_Msk\n#define RTC_CR_OSEL_0                 (0x1U << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */\n#define RTC_CR_OSEL_1                 (0x2U << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */\n#define RTC_CR_POL_Pos                (20U)\n#define RTC_CR_POL_Msk                (0x1U << RTC_CR_POL_Pos)                 /*!< 0x00100000 */\n#define RTC_CR_POL                    RTC_CR_POL_Msk\n#define RTC_CR_COSEL_Pos              (19U)\n#define RTC_CR_COSEL_Msk              (0x1U << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */\n#define RTC_CR_COSEL                  RTC_CR_COSEL_Msk\n#define RTC_CR_BKP_Pos                 (18U)\n#define RTC_CR_BKP_Msk                 (0x1U << RTC_CR_BKP_Pos)                /*!< 0x00040000 */\n#define RTC_CR_BKP                     RTC_CR_BKP_Msk\n#define RTC_CR_SUB1H_Pos              (17U)\n#define RTC_CR_SUB1H_Msk              (0x1U << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */\n#define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk\n#define RTC_CR_ADD1H_Pos              (16U)\n#define RTC_CR_ADD1H_Msk              (0x1U << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */\n#define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk\n#define RTC_CR_TSIE_Pos               (15U)\n#define RTC_CR_TSIE_Msk               (0x1U << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */\n#define RTC_CR_TSIE                   RTC_CR_TSIE_Msk\n#define RTC_CR_WUTIE_Pos              (14U)\n#define RTC_CR_WUTIE_Msk              (0x1U << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */\n#define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk\n#define RTC_CR_ALRBIE_Pos             (13U)\n#define RTC_CR_ALRBIE_Msk             (0x1U << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */\n#define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk\n#define RTC_CR_ALRAIE_Pos             (12U)\n#define RTC_CR_ALRAIE_Msk             (0x1U << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */\n#define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk\n#define RTC_CR_TSE_Pos                (11U)\n#define RTC_CR_TSE_Msk                (0x1U << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */\n#define RTC_CR_TSE                    RTC_CR_TSE_Msk\n#define RTC_CR_WUTE_Pos               (10U)\n#define RTC_CR_WUTE_Msk               (0x1U << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */\n#define RTC_CR_WUTE                   RTC_CR_WUTE_Msk\n#define RTC_CR_ALRBE_Pos              (9U)\n#define RTC_CR_ALRBE_Msk              (0x1U << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */\n#define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk\n#define RTC_CR_ALRAE_Pos              (8U)\n#define RTC_CR_ALRAE_Msk              (0x1U << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */\n#define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk\n#define RTC_CR_DCE_Pos                (7U)\n#define RTC_CR_DCE_Msk                (0x1U << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */\n#define RTC_CR_DCE                    RTC_CR_DCE_Msk\n#define RTC_CR_FMT_Pos                (6U)\n#define RTC_CR_FMT_Msk                (0x1U << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */\n#define RTC_CR_FMT                    RTC_CR_FMT_Msk\n#define RTC_CR_BYPSHAD_Pos            (5U)\n#define RTC_CR_BYPSHAD_Msk            (0x1U << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */\n#define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk\n#define RTC_CR_REFCKON_Pos            (4U)\n#define RTC_CR_REFCKON_Msk            (0x1U << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */\n#define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk\n#define RTC_CR_TSEDGE_Pos             (3U)\n#define RTC_CR_TSEDGE_Msk             (0x1U << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */\n#define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk\n#define RTC_CR_WUCKSEL_Pos            (0U)\n#define RTC_CR_WUCKSEL_Msk            (0x7U << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */\n#define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk\n#define RTC_CR_WUCKSEL_0              (0x1U << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */\n#define RTC_CR_WUCKSEL_1              (0x2U << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */\n#define RTC_CR_WUCKSEL_2              (0x4U << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */\n\n/* Legacy defines */\n#define RTC_CR_BCK                     RTC_CR_BKP\n\n/********************  Bits definition for RTC_ISR register  ******************/\n#define RTC_ISR_RECALPF_Pos           (16U)\n#define RTC_ISR_RECALPF_Msk           (0x1U << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */\n#define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk\n#define RTC_ISR_TAMP1F_Pos            (13U)\n#define RTC_ISR_TAMP1F_Msk            (0x1U << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */\n#define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk\n#define RTC_ISR_TAMP2F_Pos            (14U)\n#define RTC_ISR_TAMP2F_Msk            (0x1U << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */\n#define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk\n#define RTC_ISR_TSOVF_Pos             (12U)\n#define RTC_ISR_TSOVF_Msk             (0x1U << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */\n#define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk\n#define RTC_ISR_TSF_Pos               (11U)\n#define RTC_ISR_TSF_Msk               (0x1U << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */\n#define RTC_ISR_TSF                   RTC_ISR_TSF_Msk\n#define RTC_ISR_WUTF_Pos              (10U)\n#define RTC_ISR_WUTF_Msk              (0x1U << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */\n#define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk\n#define RTC_ISR_ALRBF_Pos             (9U)\n#define RTC_ISR_ALRBF_Msk             (0x1U << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */\n#define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk\n#define RTC_ISR_ALRAF_Pos             (8U)\n#define RTC_ISR_ALRAF_Msk             (0x1U << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */\n#define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk\n#define RTC_ISR_INIT_Pos              (7U)\n#define RTC_ISR_INIT_Msk              (0x1U << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */\n#define RTC_ISR_INIT                  RTC_ISR_INIT_Msk\n#define RTC_ISR_INITF_Pos             (6U)\n#define RTC_ISR_INITF_Msk             (0x1U << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */\n#define RTC_ISR_INITF                 RTC_ISR_INITF_Msk\n#define RTC_ISR_RSF_Pos               (5U)\n#define RTC_ISR_RSF_Msk               (0x1U << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */\n#define RTC_ISR_RSF                   RTC_ISR_RSF_Msk\n#define RTC_ISR_INITS_Pos             (4U)\n#define RTC_ISR_INITS_Msk             (0x1U << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */\n#define RTC_ISR_INITS                 RTC_ISR_INITS_Msk\n#define RTC_ISR_SHPF_Pos              (3U)\n#define RTC_ISR_SHPF_Msk              (0x1U << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */\n#define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk\n#define RTC_ISR_WUTWF_Pos             (2U)\n#define RTC_ISR_WUTWF_Msk             (0x1U << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */\n#define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk\n#define RTC_ISR_ALRBWF_Pos            (1U)\n#define RTC_ISR_ALRBWF_Msk            (0x1U << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */\n#define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk\n#define RTC_ISR_ALRAWF_Pos            (0U)\n#define RTC_ISR_ALRAWF_Msk            (0x1U << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */\n#define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk\n\n/********************  Bits definition for RTC_PRER register  *****************/\n#define RTC_PRER_PREDIV_A_Pos         (16U)\n#define RTC_PRER_PREDIV_A_Msk         (0x7FU << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */\n#define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk\n#define RTC_PRER_PREDIV_S_Pos         (0U)\n#define RTC_PRER_PREDIV_S_Msk         (0x7FFFU << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */\n#define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk\n\n/********************  Bits definition for RTC_WUTR register  *****************/\n#define RTC_WUTR_WUT_Pos              (0U)\n#define RTC_WUTR_WUT_Msk              (0xFFFFU << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */\n#define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk\n\n/********************  Bits definition for RTC_CALIBR register  ***************/\n#define RTC_CALIBR_DCS_Pos            (7U)\n#define RTC_CALIBR_DCS_Msk            (0x1U << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */\n#define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk\n#define RTC_CALIBR_DC_Pos             (0U)\n#define RTC_CALIBR_DC_Msk             (0x1FU << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */\n#define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk\n\n/********************  Bits definition for RTC_ALRMAR register  ***************/\n#define RTC_ALRMAR_MSK4_Pos           (31U)\n#define RTC_ALRMAR_MSK4_Msk           (0x1U << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk\n#define RTC_ALRMAR_WDSEL_Pos          (30U)\n#define RTC_ALRMAR_WDSEL_Msk          (0x1U << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk\n#define RTC_ALRMAR_DT_Pos             (28U)\n#define RTC_ALRMAR_DT_Msk             (0x3U << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk\n#define RTC_ALRMAR_DT_0               (0x1U << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMAR_DT_1               (0x2U << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMAR_DU_Pos             (24U)\n#define RTC_ALRMAR_DU_Msk             (0xFU << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk\n#define RTC_ALRMAR_DU_0               (0x1U << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMAR_DU_1               (0x2U << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMAR_DU_2               (0x4U << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMAR_DU_3               (0x8U << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMAR_MSK3_Pos           (23U)\n#define RTC_ALRMAR_MSK3_Msk           (0x1U << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk\n#define RTC_ALRMAR_PM_Pos             (22U)\n#define RTC_ALRMAR_PM_Msk             (0x1U << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk\n#define RTC_ALRMAR_HT_Pos             (20U)\n#define RTC_ALRMAR_HT_Msk             (0x3U << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk\n#define RTC_ALRMAR_HT_0               (0x1U << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMAR_HT_1               (0x2U << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMAR_HU_Pos             (16U)\n#define RTC_ALRMAR_HU_Msk             (0xFU << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk\n#define RTC_ALRMAR_HU_0               (0x1U << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMAR_HU_1               (0x2U << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMAR_HU_2               (0x4U << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMAR_HU_3               (0x8U << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMAR_MSK2_Pos           (15U)\n#define RTC_ALRMAR_MSK2_Msk           (0x1U << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk\n#define RTC_ALRMAR_MNT_Pos            (12U)\n#define RTC_ALRMAR_MNT_Msk            (0x7U << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk\n#define RTC_ALRMAR_MNT_0              (0x1U << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMAR_MNT_1              (0x2U << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMAR_MNT_2              (0x4U << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMAR_MNU_Pos            (8U)\n#define RTC_ALRMAR_MNU_Msk            (0xFU << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk\n#define RTC_ALRMAR_MNU_0              (0x1U << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMAR_MNU_1              (0x2U << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMAR_MNU_2              (0x4U << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMAR_MNU_3              (0x8U << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMAR_MSK1_Pos           (7U)\n#define RTC_ALRMAR_MSK1_Msk           (0x1U << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk\n#define RTC_ALRMAR_ST_Pos             (4U)\n#define RTC_ALRMAR_ST_Msk             (0x7U << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk\n#define RTC_ALRMAR_ST_0               (0x1U << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMAR_ST_1               (0x2U << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMAR_ST_2               (0x4U << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMAR_SU_Pos             (0U)\n#define RTC_ALRMAR_SU_Msk             (0xFU << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk\n#define RTC_ALRMAR_SU_0               (0x1U << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMAR_SU_1               (0x2U << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMAR_SU_2               (0x4U << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMAR_SU_3               (0x8U << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_ALRMBR register  ***************/\n#define RTC_ALRMBR_MSK4_Pos           (31U)\n#define RTC_ALRMBR_MSK4_Msk           (0x1U << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk\n#define RTC_ALRMBR_WDSEL_Pos          (30U)\n#define RTC_ALRMBR_WDSEL_Msk          (0x1U << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk\n#define RTC_ALRMBR_DT_Pos             (28U)\n#define RTC_ALRMBR_DT_Msk             (0x3U << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk\n#define RTC_ALRMBR_DT_0               (0x1U << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMBR_DT_1               (0x2U << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMBR_DU_Pos             (24U)\n#define RTC_ALRMBR_DU_Msk             (0xFU << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk\n#define RTC_ALRMBR_DU_0               (0x1U << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMBR_DU_1               (0x2U << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMBR_DU_2               (0x4U << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMBR_DU_3               (0x8U << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMBR_MSK3_Pos           (23U)\n#define RTC_ALRMBR_MSK3_Msk           (0x1U << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk\n#define RTC_ALRMBR_PM_Pos             (22U)\n#define RTC_ALRMBR_PM_Msk             (0x1U << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk\n#define RTC_ALRMBR_HT_Pos             (20U)\n#define RTC_ALRMBR_HT_Msk             (0x3U << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk\n#define RTC_ALRMBR_HT_0               (0x1U << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMBR_HT_1               (0x2U << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMBR_HU_Pos             (16U)\n#define RTC_ALRMBR_HU_Msk             (0xFU << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk\n#define RTC_ALRMBR_HU_0               (0x1U << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMBR_HU_1               (0x2U << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMBR_HU_2               (0x4U << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMBR_HU_3               (0x8U << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMBR_MSK2_Pos           (15U)\n#define RTC_ALRMBR_MSK2_Msk           (0x1U << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk\n#define RTC_ALRMBR_MNT_Pos            (12U)\n#define RTC_ALRMBR_MNT_Msk            (0x7U << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk\n#define RTC_ALRMBR_MNT_0              (0x1U << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMBR_MNT_1              (0x2U << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMBR_MNT_2              (0x4U << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMBR_MNU_Pos            (8U)\n#define RTC_ALRMBR_MNU_Msk            (0xFU << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk\n#define RTC_ALRMBR_MNU_0              (0x1U << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMBR_MNU_1              (0x2U << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMBR_MNU_2              (0x4U << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMBR_MNU_3              (0x8U << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMBR_MSK1_Pos           (7U)\n#define RTC_ALRMBR_MSK1_Msk           (0x1U << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk\n#define RTC_ALRMBR_ST_Pos             (4U)\n#define RTC_ALRMBR_ST_Msk             (0x7U << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk\n#define RTC_ALRMBR_ST_0               (0x1U << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMBR_ST_1               (0x2U << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMBR_ST_2               (0x4U << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMBR_SU_Pos             (0U)\n#define RTC_ALRMBR_SU_Msk             (0xFU << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk\n#define RTC_ALRMBR_SU_0               (0x1U << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMBR_SU_1               (0x2U << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMBR_SU_2               (0x4U << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMBR_SU_3               (0x8U << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_WPR register  ******************/\n#define RTC_WPR_KEY_Pos               (0U)\n#define RTC_WPR_KEY_Msk               (0xFFU << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */\n#define RTC_WPR_KEY                   RTC_WPR_KEY_Msk\n\n/********************  Bits definition for RTC_SSR register  ******************/\n#define RTC_SSR_SS_Pos                (0U)\n#define RTC_SSR_SS_Msk                (0xFFFFU << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */\n#define RTC_SSR_SS                    RTC_SSR_SS_Msk\n\n/********************  Bits definition for RTC_SHIFTR register  ***************/\n#define RTC_SHIFTR_SUBFS_Pos          (0U)\n#define RTC_SHIFTR_SUBFS_Msk          (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */\n#define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk\n#define RTC_SHIFTR_ADD1S_Pos          (31U)\n#define RTC_SHIFTR_ADD1S_Msk          (0x1U << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */\n#define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk\n\n/********************  Bits definition for RTC_TSTR register  *****************/\n#define RTC_TSTR_PM_Pos               (22U)\n#define RTC_TSTR_PM_Msk               (0x1U << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */\n#define RTC_TSTR_PM                   RTC_TSTR_PM_Msk\n#define RTC_TSTR_HT_Pos               (20U)\n#define RTC_TSTR_HT_Msk               (0x3U << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */\n#define RTC_TSTR_HT                   RTC_TSTR_HT_Msk\n#define RTC_TSTR_HT_0                 (0x1U << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */\n#define RTC_TSTR_HT_1                 (0x2U << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */\n#define RTC_TSTR_HU_Pos               (16U)\n#define RTC_TSTR_HU_Msk               (0xFU << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */\n#define RTC_TSTR_HU                   RTC_TSTR_HU_Msk\n#define RTC_TSTR_HU_0                 (0x1U << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */\n#define RTC_TSTR_HU_1                 (0x2U << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */\n#define RTC_TSTR_HU_2                 (0x4U << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */\n#define RTC_TSTR_HU_3                 (0x8U << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */\n#define RTC_TSTR_MNT_Pos              (12U)\n#define RTC_TSTR_MNT_Msk              (0x7U << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */\n#define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk\n#define RTC_TSTR_MNT_0                (0x1U << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */\n#define RTC_TSTR_MNT_1                (0x2U << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */\n#define RTC_TSTR_MNT_2                (0x4U << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */\n#define RTC_TSTR_MNU_Pos              (8U)\n#define RTC_TSTR_MNU_Msk              (0xFU << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */\n#define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk\n#define RTC_TSTR_MNU_0                (0x1U << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */\n#define RTC_TSTR_MNU_1                (0x2U << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */\n#define RTC_TSTR_MNU_2                (0x4U << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */\n#define RTC_TSTR_MNU_3                (0x8U << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */\n#define RTC_TSTR_ST_Pos               (4U)\n#define RTC_TSTR_ST_Msk               (0x7U << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */\n#define RTC_TSTR_ST                   RTC_TSTR_ST_Msk\n#define RTC_TSTR_ST_0                 (0x1U << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */\n#define RTC_TSTR_ST_1                 (0x2U << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */\n#define RTC_TSTR_ST_2                 (0x4U << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */\n#define RTC_TSTR_SU_Pos               (0U)\n#define RTC_TSTR_SU_Msk               (0xFU << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */\n#define RTC_TSTR_SU                   RTC_TSTR_SU_Msk\n#define RTC_TSTR_SU_0                 (0x1U << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */\n#define RTC_TSTR_SU_1                 (0x2U << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */\n#define RTC_TSTR_SU_2                 (0x4U << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */\n#define RTC_TSTR_SU_3                 (0x8U << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSDR register  *****************/\n#define RTC_TSDR_WDU_Pos              (13U)\n#define RTC_TSDR_WDU_Msk              (0x7U << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */\n#define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk\n#define RTC_TSDR_WDU_0                (0x1U << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */\n#define RTC_TSDR_WDU_1                (0x2U << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */\n#define RTC_TSDR_WDU_2                (0x4U << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */\n#define RTC_TSDR_MT_Pos               (12U)\n#define RTC_TSDR_MT_Msk               (0x1U << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */\n#define RTC_TSDR_MT                   RTC_TSDR_MT_Msk\n#define RTC_TSDR_MU_Pos               (8U)\n#define RTC_TSDR_MU_Msk               (0xFU << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */\n#define RTC_TSDR_MU                   RTC_TSDR_MU_Msk\n#define RTC_TSDR_MU_0                 (0x1U << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */\n#define RTC_TSDR_MU_1                 (0x2U << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */\n#define RTC_TSDR_MU_2                 (0x4U << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */\n#define RTC_TSDR_MU_3                 (0x8U << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */\n#define RTC_TSDR_DT_Pos               (4U)\n#define RTC_TSDR_DT_Msk               (0x3U << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */\n#define RTC_TSDR_DT                   RTC_TSDR_DT_Msk\n#define RTC_TSDR_DT_0                 (0x1U << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */\n#define RTC_TSDR_DT_1                 (0x2U << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */\n#define RTC_TSDR_DU_Pos               (0U)\n#define RTC_TSDR_DU_Msk               (0xFU << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */\n#define RTC_TSDR_DU                   RTC_TSDR_DU_Msk\n#define RTC_TSDR_DU_0                 (0x1U << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */\n#define RTC_TSDR_DU_1                 (0x2U << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */\n#define RTC_TSDR_DU_2                 (0x4U << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */\n#define RTC_TSDR_DU_3                 (0x8U << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSSSR register  ****************/\n#define RTC_TSSSR_SS_Pos              (0U)\n#define RTC_TSSSR_SS_Msk              (0xFFFFU << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */\n#define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk\n\n/********************  Bits definition for RTC_CAL register  *****************/\n#define RTC_CALR_CALP_Pos             (15U)\n#define RTC_CALR_CALP_Msk             (0x1U << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */\n#define RTC_CALR_CALP                 RTC_CALR_CALP_Msk\n#define RTC_CALR_CALW8_Pos            (14U)\n#define RTC_CALR_CALW8_Msk            (0x1U << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */\n#define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk\n#define RTC_CALR_CALW16_Pos           (13U)\n#define RTC_CALR_CALW16_Msk           (0x1U << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */\n#define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk\n#define RTC_CALR_CALM_Pos             (0U)\n#define RTC_CALR_CALM_Msk             (0x1FFU << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */\n#define RTC_CALR_CALM                 RTC_CALR_CALM_Msk\n#define RTC_CALR_CALM_0               (0x001U << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */\n#define RTC_CALR_CALM_1               (0x002U << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */\n#define RTC_CALR_CALM_2               (0x004U << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */\n#define RTC_CALR_CALM_3               (0x008U << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */\n#define RTC_CALR_CALM_4               (0x010U << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */\n#define RTC_CALR_CALM_5               (0x020U << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */\n#define RTC_CALR_CALM_6               (0x040U << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */\n#define RTC_CALR_CALM_7               (0x080U << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */\n#define RTC_CALR_CALM_8               (0x100U << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */\n\n/********************  Bits definition for RTC_TAFCR register  ****************/\n#define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)\n#define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */\n#define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk\n#define RTC_TAFCR_TSINSEL_Pos         (17U)\n#define RTC_TAFCR_TSINSEL_Msk         (0x1U << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */\n#define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk\n#define RTC_TAFCR_TAMP1INSEL_Pos      (16U)\n#define RTC_TAFCR_TAMP1INSEL_Msk      (0x1U << RTC_TAFCR_TAMP1INSEL_Pos)        /*!< 0x00010000 */\n#define RTC_TAFCR_TAMP1INSEL          RTC_TAFCR_TAMP1INSEL_Msk\n#define RTC_TAFCR_TAMPPUDIS_Pos       (15U)\n#define RTC_TAFCR_TAMPPUDIS_Msk       (0x1U << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */\n#define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk\n#define RTC_TAFCR_TAMPPRCH_Pos        (13U)\n#define RTC_TAFCR_TAMPPRCH_Msk        (0x3U << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */\n#define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk\n#define RTC_TAFCR_TAMPPRCH_0          (0x1U << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */\n#define RTC_TAFCR_TAMPPRCH_1          (0x2U << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */\n#define RTC_TAFCR_TAMPFLT_Pos         (11U)\n#define RTC_TAFCR_TAMPFLT_Msk         (0x3U << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */\n#define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk\n#define RTC_TAFCR_TAMPFLT_0           (0x1U << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */\n#define RTC_TAFCR_TAMPFLT_1           (0x2U << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */\n#define RTC_TAFCR_TAMPFREQ_Pos        (8U)\n#define RTC_TAFCR_TAMPFREQ_Msk        (0x7U << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */\n#define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk\n#define RTC_TAFCR_TAMPFREQ_0          (0x1U << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */\n#define RTC_TAFCR_TAMPFREQ_1          (0x2U << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */\n#define RTC_TAFCR_TAMPFREQ_2          (0x4U << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */\n#define RTC_TAFCR_TAMPTS_Pos          (7U)\n#define RTC_TAFCR_TAMPTS_Msk          (0x1U << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */\n#define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk\n#define RTC_TAFCR_TAMP2TRG_Pos        (4U)\n#define RTC_TAFCR_TAMP2TRG_Msk        (0x1U << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */\n#define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk\n#define RTC_TAFCR_TAMP2E_Pos          (3U)\n#define RTC_TAFCR_TAMP2E_Msk          (0x1U << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */\n#define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk\n#define RTC_TAFCR_TAMPIE_Pos          (2U)\n#define RTC_TAFCR_TAMPIE_Msk          (0x1U << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */\n#define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk\n#define RTC_TAFCR_TAMP1TRG_Pos        (1U)\n#define RTC_TAFCR_TAMP1TRG_Msk        (0x1U << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */\n#define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk\n#define RTC_TAFCR_TAMP1E_Pos          (0U)\n#define RTC_TAFCR_TAMP1E_Msk          (0x1U << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */\n#define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk\n\n/* Legacy defines */\n#define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMP1INSEL\n\n/********************  Bits definition for RTC_ALRMASSR register  *************/\n#define RTC_ALRMASSR_MASKSS_Pos       (24U)\n#define RTC_ALRMASSR_MASKSS_Msk       (0xFU << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk\n#define RTC_ALRMASSR_MASKSS_0         (0x1U << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMASSR_MASKSS_1         (0x2U << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMASSR_MASKSS_2         (0x4U << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMASSR_MASKSS_3         (0x8U << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMASSR_SS_Pos           (0U)\n#define RTC_ALRMASSR_SS_Msk           (0x7FFFU << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk\n\n/********************  Bits definition for RTC_ALRMBSSR register  *************/\n#define RTC_ALRMBSSR_MASKSS_Pos       (24U)\n#define RTC_ALRMBSSR_MASKSS_Msk       (0xFU << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk\n#define RTC_ALRMBSSR_MASKSS_0         (0x1U << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMBSSR_MASKSS_1         (0x2U << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMBSSR_MASKSS_2         (0x4U << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMBSSR_MASKSS_3         (0x8U << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMBSSR_SS_Pos           (0U)\n#define RTC_ALRMBSSR_SS_Msk           (0x7FFFU << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk\n\n/********************  Bits definition for RTC_BKP0R register  ****************/\n#define RTC_BKP0R_Pos                 (0U)\n#define RTC_BKP0R_Msk                 (0xFFFFFFFFU << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP0R                     RTC_BKP0R_Msk\n\n/********************  Bits definition for RTC_BKP1R register  ****************/\n#define RTC_BKP1R_Pos                 (0U)\n#define RTC_BKP1R_Msk                 (0xFFFFFFFFU << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP1R                     RTC_BKP1R_Msk\n\n/********************  Bits definition for RTC_BKP2R register  ****************/\n#define RTC_BKP2R_Pos                 (0U)\n#define RTC_BKP2R_Msk                 (0xFFFFFFFFU << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP2R                     RTC_BKP2R_Msk\n\n/********************  Bits definition for RTC_BKP3R register  ****************/\n#define RTC_BKP3R_Pos                 (0U)\n#define RTC_BKP3R_Msk                 (0xFFFFFFFFU << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP3R                     RTC_BKP3R_Msk\n\n/********************  Bits definition for RTC_BKP4R register  ****************/\n#define RTC_BKP4R_Pos                 (0U)\n#define RTC_BKP4R_Msk                 (0xFFFFFFFFU << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP4R                     RTC_BKP4R_Msk\n\n/********************  Bits definition for RTC_BKP5R register  ****************/\n#define RTC_BKP5R_Pos                 (0U)\n#define RTC_BKP5R_Msk                 (0xFFFFFFFFU << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP5R                     RTC_BKP5R_Msk\n\n/********************  Bits definition for RTC_BKP6R register  ****************/\n#define RTC_BKP6R_Pos                 (0U)\n#define RTC_BKP6R_Msk                 (0xFFFFFFFFU << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP6R                     RTC_BKP6R_Msk\n\n/********************  Bits definition for RTC_BKP7R register  ****************/\n#define RTC_BKP7R_Pos                 (0U)\n#define RTC_BKP7R_Msk                 (0xFFFFFFFFU << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP7R                     RTC_BKP7R_Msk\n\n/********************  Bits definition for RTC_BKP8R register  ****************/\n#define RTC_BKP8R_Pos                 (0U)\n#define RTC_BKP8R_Msk                 (0xFFFFFFFFU << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP8R                     RTC_BKP8R_Msk\n\n/********************  Bits definition for RTC_BKP9R register  ****************/\n#define RTC_BKP9R_Pos                 (0U)\n#define RTC_BKP9R_Msk                 (0xFFFFFFFFU << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP9R                     RTC_BKP9R_Msk\n\n/********************  Bits definition for RTC_BKP10R register  ***************/\n#define RTC_BKP10R_Pos                (0U)\n#define RTC_BKP10R_Msk                (0xFFFFFFFFU << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP10R                    RTC_BKP10R_Msk\n\n/********************  Bits definition for RTC_BKP11R register  ***************/\n#define RTC_BKP11R_Pos                (0U)\n#define RTC_BKP11R_Msk                (0xFFFFFFFFU << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP11R                    RTC_BKP11R_Msk\n\n/********************  Bits definition for RTC_BKP12R register  ***************/\n#define RTC_BKP12R_Pos                (0U)\n#define RTC_BKP12R_Msk                (0xFFFFFFFFU << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP12R                    RTC_BKP12R_Msk\n\n/********************  Bits definition for RTC_BKP13R register  ***************/\n#define RTC_BKP13R_Pos                (0U)\n#define RTC_BKP13R_Msk                (0xFFFFFFFFU << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP13R                    RTC_BKP13R_Msk\n\n/********************  Bits definition for RTC_BKP14R register  ***************/\n#define RTC_BKP14R_Pos                (0U)\n#define RTC_BKP14R_Msk                (0xFFFFFFFFU << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP14R                    RTC_BKP14R_Msk\n\n/********************  Bits definition for RTC_BKP15R register  ***************/\n#define RTC_BKP15R_Pos                (0U)\n#define RTC_BKP15R_Msk                (0xFFFFFFFFU << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP15R                    RTC_BKP15R_Msk\n\n/********************  Bits definition for RTC_BKP16R register  ***************/\n#define RTC_BKP16R_Pos                (0U)\n#define RTC_BKP16R_Msk                (0xFFFFFFFFU << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP16R                    RTC_BKP16R_Msk\n\n/********************  Bits definition for RTC_BKP17R register  ***************/\n#define RTC_BKP17R_Pos                (0U)\n#define RTC_BKP17R_Msk                (0xFFFFFFFFU << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP17R                    RTC_BKP17R_Msk\n\n/********************  Bits definition for RTC_BKP18R register  ***************/\n#define RTC_BKP18R_Pos                (0U)\n#define RTC_BKP18R_Msk                (0xFFFFFFFFU << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP18R                    RTC_BKP18R_Msk\n\n/********************  Bits definition for RTC_BKP19R register  ***************/\n#define RTC_BKP19R_Pos                (0U)\n#define RTC_BKP19R_Msk                (0xFFFFFFFFU << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP19R                    RTC_BKP19R_Msk\n\n/******************** Number of backup registers ******************************/\n#define RTC_BKP_NUMBER                       0x000000014U\n\n/******************************************************************************/\n/*                                                                            */\n/*                          Serial Audio Interface                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for SAI_GCR register  *******************/\n#define SAI_GCR_SYNCIN_Pos         (0U)\n#define SAI_GCR_SYNCIN_Msk         (0x3U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */\n#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */\n#define SAI_GCR_SYNCIN_0           (0x1U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */\n#define SAI_GCR_SYNCIN_1           (0x2U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */\n\n#define SAI_GCR_SYNCOUT_Pos        (4U)\n#define SAI_GCR_SYNCOUT_Msk        (0x3U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */\n#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\n#define SAI_GCR_SYNCOUT_0          (0x1U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */\n#define SAI_GCR_SYNCOUT_1          (0x2U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */\n\n/*******************  Bit definition for SAI_xCR1 register  *******************/\n#define SAI_xCR1_MODE_Pos          (0U)\n#define SAI_xCR1_MODE_Msk          (0x3U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */\n#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */\n#define SAI_xCR1_MODE_0            (0x1U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */\n#define SAI_xCR1_MODE_1            (0x2U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */\n\n#define SAI_xCR1_PRTCFG_Pos        (2U)\n#define SAI_xCR1_PRTCFG_Msk        (0x3U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */\n#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */\n#define SAI_xCR1_PRTCFG_0          (0x1U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */\n#define SAI_xCR1_PRTCFG_1          (0x2U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */\n\n#define SAI_xCR1_DS_Pos            (5U)\n#define SAI_xCR1_DS_Msk            (0x7U << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */\n#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */\n#define SAI_xCR1_DS_0              (0x1U << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */\n#define SAI_xCR1_DS_1              (0x2U << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */\n#define SAI_xCR1_DS_2              (0x4U << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */\n\n#define SAI_xCR1_LSBFIRST_Pos      (8U)\n#define SAI_xCR1_LSBFIRST_Msk      (0x1U << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */\n#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */\n#define SAI_xCR1_CKSTR_Pos         (9U)\n#define SAI_xCR1_CKSTR_Msk         (0x1U << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */\n#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */\n\n#define SAI_xCR1_SYNCEN_Pos        (10U)\n#define SAI_xCR1_SYNCEN_Msk        (0x3U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */\n#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */\n#define SAI_xCR1_SYNCEN_0          (0x1U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */\n#define SAI_xCR1_SYNCEN_1          (0x2U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */\n\n#define SAI_xCR1_MONO_Pos          (12U)\n#define SAI_xCR1_MONO_Msk          (0x1U << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */\n#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */\n#define SAI_xCR1_OUTDRIV_Pos       (13U)\n#define SAI_xCR1_OUTDRIV_Msk       (0x1U << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */\n#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */\n#define SAI_xCR1_SAIEN_Pos         (16U)\n#define SAI_xCR1_SAIEN_Msk         (0x1U << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */\n#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */\n#define SAI_xCR1_DMAEN_Pos         (17U)\n#define SAI_xCR1_DMAEN_Msk         (0x1U << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */\n#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */\n#define SAI_xCR1_NODIV_Pos         (19U)\n#define SAI_xCR1_NODIV_Msk         (0x1U << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */\n#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */\n\n#define SAI_xCR1_MCKDIV_Pos        (20U)\n#define SAI_xCR1_MCKDIV_Msk        (0xFU << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */\n#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */\n#define SAI_xCR1_MCKDIV_0          (0x1U << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00100000 */\n#define SAI_xCR1_MCKDIV_1          (0x2U << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00200000 */\n#define SAI_xCR1_MCKDIV_2          (0x4U << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00400000 */\n#define SAI_xCR1_MCKDIV_3          (0x8U << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00800000 */\n\n/*******************  Bit definition for SAI_xCR2 register  *******************/\n#define SAI_xCR2_FTH_Pos           (0U)\n#define SAI_xCR2_FTH_Msk           (0x7U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */\n#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */\n#define SAI_xCR2_FTH_0             (0x1U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */\n#define SAI_xCR2_FTH_1             (0x2U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */\n#define SAI_xCR2_FTH_2             (0x4U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */\n\n#define SAI_xCR2_FFLUSH_Pos        (3U)\n#define SAI_xCR2_FFLUSH_Msk        (0x1U << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */\n#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */\n#define SAI_xCR2_TRIS_Pos          (4U)\n#define SAI_xCR2_TRIS_Msk          (0x1U << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */\n#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */\n#define SAI_xCR2_MUTE_Pos          (5U)\n#define SAI_xCR2_MUTE_Msk          (0x1U << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */\n#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */\n#define SAI_xCR2_MUTEVAL_Pos       (6U)\n#define SAI_xCR2_MUTEVAL_Msk       (0x1U << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */\n#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */\n\n#define SAI_xCR2_MUTECNT_Pos       (7U)\n#define SAI_xCR2_MUTECNT_Msk       (0x3FU << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */\n#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */\n#define SAI_xCR2_MUTECNT_0         (0x01U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */\n#define SAI_xCR2_MUTECNT_1         (0x02U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */\n#define SAI_xCR2_MUTECNT_2         (0x04U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */\n#define SAI_xCR2_MUTECNT_3         (0x08U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */\n#define SAI_xCR2_MUTECNT_4         (0x10U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */\n#define SAI_xCR2_MUTECNT_5         (0x20U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */\n\n#define SAI_xCR2_CPL_Pos           (13U)\n#define SAI_xCR2_CPL_Msk           (0x1U << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */\n#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */\n\n#define SAI_xCR2_COMP_Pos          (14U)\n#define SAI_xCR2_COMP_Msk          (0x3U << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */\n#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */\n#define SAI_xCR2_COMP_0            (0x1U << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */\n#define SAI_xCR2_COMP_1            (0x2U << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */\n\n/******************  Bit definition for SAI_xFRCR register  *******************/\n#define SAI_xFRCR_FRL_Pos          (0U)\n#define SAI_xFRCR_FRL_Msk          (0xFFU << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */\n#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[1:0](Frame length)  */\n#define SAI_xFRCR_FRL_0            (0x01U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */\n#define SAI_xFRCR_FRL_1            (0x02U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */\n#define SAI_xFRCR_FRL_2            (0x04U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */\n#define SAI_xFRCR_FRL_3            (0x08U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */\n#define SAI_xFRCR_FRL_4            (0x10U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */\n#define SAI_xFRCR_FRL_5            (0x20U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */\n#define SAI_xFRCR_FRL_6            (0x40U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */\n#define SAI_xFRCR_FRL_7            (0x80U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */\n\n#define SAI_xFRCR_FSALL_Pos        (8U)\n#define SAI_xFRCR_FSALL_Msk        (0x7FU << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */\n#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[1:0] (Frame synchronization active level length)  */\n#define SAI_xFRCR_FSALL_0          (0x01U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */\n#define SAI_xFRCR_FSALL_1          (0x02U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */\n#define SAI_xFRCR_FSALL_2          (0x04U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */\n#define SAI_xFRCR_FSALL_3          (0x08U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */\n#define SAI_xFRCR_FSALL_4          (0x10U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */\n#define SAI_xFRCR_FSALL_5          (0x20U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */\n#define SAI_xFRCR_FSALL_6          (0x40U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */\n\n#define SAI_xFRCR_FSDEF_Pos        (16U)\n#define SAI_xFRCR_FSDEF_Msk        (0x1U << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */\n#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */\n#define SAI_xFRCR_FSPOL_Pos        (17U)\n#define SAI_xFRCR_FSPOL_Msk        (0x1U << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */\n#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */\n#define SAI_xFRCR_FSOFF_Pos        (18U)\n#define SAI_xFRCR_FSOFF_Msk        (0x1U << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */\n#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */\n/* Legacy defines */\n#define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL\n\n/******************  Bit definition for SAI_xSLOTR register  *******************/\n#define SAI_xSLOTR_FBOFF_Pos       (0U)\n#define SAI_xSLOTR_FBOFF_Msk       (0x1FU << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */\n#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */\n#define SAI_xSLOTR_FBOFF_0         (0x01U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */\n#define SAI_xSLOTR_FBOFF_1         (0x02U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */\n#define SAI_xSLOTR_FBOFF_2         (0x04U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */\n#define SAI_xSLOTR_FBOFF_3         (0x08U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */\n#define SAI_xSLOTR_FBOFF_4         (0x10U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */\n\n#define SAI_xSLOTR_SLOTSZ_Pos      (6U)\n#define SAI_xSLOTR_SLOTSZ_Msk      (0x3U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */\n#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */\n#define SAI_xSLOTR_SLOTSZ_0        (0x1U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */\n#define SAI_xSLOTR_SLOTSZ_1        (0x2U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */\n\n#define SAI_xSLOTR_NBSLOT_Pos      (8U)\n#define SAI_xSLOTR_NBSLOT_Msk      (0xFU << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */\n#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */\n#define SAI_xSLOTR_NBSLOT_0        (0x1U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */\n#define SAI_xSLOTR_NBSLOT_1        (0x2U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */\n#define SAI_xSLOTR_NBSLOT_2        (0x4U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */\n#define SAI_xSLOTR_NBSLOT_3        (0x8U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */\n\n#define SAI_xSLOTR_SLOTEN_Pos      (16U)\n#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */\n#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */\n\n/*******************  Bit definition for SAI_xIMR register  *******************/\n#define SAI_xIMR_OVRUDRIE_Pos      (0U)\n#define SAI_xIMR_OVRUDRIE_Msk      (0x1U << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */\n#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */\n#define SAI_xIMR_MUTEDETIE_Pos     (1U)\n#define SAI_xIMR_MUTEDETIE_Msk     (0x1U << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */\n#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */\n#define SAI_xIMR_WCKCFGIE_Pos      (2U)\n#define SAI_xIMR_WCKCFGIE_Msk      (0x1U << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */\n#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */\n#define SAI_xIMR_FREQIE_Pos        (3U)\n#define SAI_xIMR_FREQIE_Msk        (0x1U << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */\n#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */\n#define SAI_xIMR_CNRDYIE_Pos       (4U)\n#define SAI_xIMR_CNRDYIE_Msk       (0x1U << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */\n#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */\n#define SAI_xIMR_AFSDETIE_Pos      (5U)\n#define SAI_xIMR_AFSDETIE_Msk      (0x1U << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */\n#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */\n#define SAI_xIMR_LFSDETIE_Pos      (6U)\n#define SAI_xIMR_LFSDETIE_Msk      (0x1U << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */\n#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */\n\n/********************  Bit definition for SAI_xSR register  *******************/\n#define SAI_xSR_OVRUDR_Pos         (0U)\n#define SAI_xSR_OVRUDR_Msk         (0x1U << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */\n#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */\n#define SAI_xSR_MUTEDET_Pos        (1U)\n#define SAI_xSR_MUTEDET_Msk        (0x1U << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */\n#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */\n#define SAI_xSR_WCKCFG_Pos         (2U)\n#define SAI_xSR_WCKCFG_Msk         (0x1U << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */\n#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */\n#define SAI_xSR_FREQ_Pos           (3U)\n#define SAI_xSR_FREQ_Msk           (0x1U << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */\n#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */\n#define SAI_xSR_CNRDY_Pos          (4U)\n#define SAI_xSR_CNRDY_Msk          (0x1U << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */\n#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */\n#define SAI_xSR_AFSDET_Pos         (5U)\n#define SAI_xSR_AFSDET_Msk         (0x1U << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */\n#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */\n#define SAI_xSR_LFSDET_Pos         (6U)\n#define SAI_xSR_LFSDET_Msk         (0x1U << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */\n#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */\n\n#define SAI_xSR_FLVL_Pos           (16U)\n#define SAI_xSR_FLVL_Msk           (0x7U << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */\n#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */\n#define SAI_xSR_FLVL_0             (0x1U << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */\n#define SAI_xSR_FLVL_1             (0x2U << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */\n#define SAI_xSR_FLVL_2             (0x4U << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */\n\n/******************  Bit definition for SAI_xCLRFR register  ******************/\n#define SAI_xCLRFR_COVRUDR_Pos     (0U)\n#define SAI_xCLRFR_COVRUDR_Msk     (0x1U << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */\n#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */\n#define SAI_xCLRFR_CMUTEDET_Pos    (1U)\n#define SAI_xCLRFR_CMUTEDET_Msk    (0x1U << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */\n#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */\n#define SAI_xCLRFR_CWCKCFG_Pos     (2U)\n#define SAI_xCLRFR_CWCKCFG_Msk     (0x1U << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */\n#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */\n#define SAI_xCLRFR_CFREQ_Pos       (3U)\n#define SAI_xCLRFR_CFREQ_Msk       (0x1U << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */\n#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */\n#define SAI_xCLRFR_CCNRDY_Pos      (4U)\n#define SAI_xCLRFR_CCNRDY_Msk      (0x1U << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */\n#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */\n#define SAI_xCLRFR_CAFSDET_Pos     (5U)\n#define SAI_xCLRFR_CAFSDET_Msk     (0x1U << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */\n#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */\n#define SAI_xCLRFR_CLFSDET_Pos     (6U)\n#define SAI_xCLRFR_CLFSDET_Msk     (0x1U << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */\n#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */\n\n/******************  Bit definition for SAI_xDR register  ******************/\n#define SAI_xDR_DATA_Pos           (0U)\n#define SAI_xDR_DATA_Msk           (0xFFFFFFFFU << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */\n#define SAI_xDR_DATA               SAI_xDR_DATA_Msk\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                          SD host Interface                                 */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SDIO_POWER register  ******************/\n#define SDIO_POWER_PWRCTRL_Pos         (0U)\n#define SDIO_POWER_PWRCTRL_Msk         (0x3U << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */\n#define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */\n#define SDIO_POWER_PWRCTRL_0           (0x1U << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x01 */\n#define SDIO_POWER_PWRCTRL_1           (0x2U << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x02 */\n\n/******************  Bit definition for SDIO_CLKCR register  ******************/\n#define SDIO_CLKCR_CLKDIV_Pos          (0U)\n#define SDIO_CLKCR_CLKDIV_Msk          (0xFFU << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */\n#define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor             */\n#define SDIO_CLKCR_CLKEN_Pos           (8U)\n#define SDIO_CLKCR_CLKEN_Msk           (0x1U << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */\n#define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit                */\n#define SDIO_CLKCR_PWRSAV_Pos          (9U)\n#define SDIO_CLKCR_PWRSAV_Msk          (0x1U << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */\n#define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit  */\n#define SDIO_CLKCR_BYPASS_Pos          (10U)\n#define SDIO_CLKCR_BYPASS_Msk          (0x1U << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */\n#define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */\n\n#define SDIO_CLKCR_WIDBUS_Pos          (11U)\n#define SDIO_CLKCR_WIDBUS_Msk          (0x3U << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */\n#define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\n#define SDIO_CLKCR_WIDBUS_0            (0x1U << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x0800 */\n#define SDIO_CLKCR_WIDBUS_1            (0x2U << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x1000 */\n\n#define SDIO_CLKCR_NEGEDGE_Pos         (13U)\n#define SDIO_CLKCR_NEGEDGE_Msk         (0x1U << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */\n#define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */\n#define SDIO_CLKCR_HWFC_EN_Pos         (14U)\n#define SDIO_CLKCR_HWFC_EN_Msk         (0x1U << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */\n#define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable          */\n\n/*******************  Bit definition for SDIO_ARG register  *******************/\n#define SDIO_ARG_CMDARG_Pos            (0U)\n#define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */\n#define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */\n\n/*******************  Bit definition for SDIO_CMD register  *******************/\n#define SDIO_CMD_CMDINDEX_Pos          (0U)\n#define SDIO_CMD_CMDINDEX_Msk          (0x3FU << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */\n#define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index                               */\n\n#define SDIO_CMD_WAITRESP_Pos          (6U)\n#define SDIO_CMD_WAITRESP_Msk          (0x3U << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */\n#define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */\n#define SDIO_CMD_WAITRESP_0            (0x1U << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0040 */\n#define SDIO_CMD_WAITRESP_1            (0x2U << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0080 */\n\n#define SDIO_CMD_WAITINT_Pos           (8U)\n#define SDIO_CMD_WAITINT_Msk           (0x1U << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */\n#define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request                               */\n#define SDIO_CMD_WAITPEND_Pos          (9U)\n#define SDIO_CMD_WAITPEND_Msk          (0x1U << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */\n#define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\n#define SDIO_CMD_CPSMEN_Pos            (10U)\n#define SDIO_CMD_CPSMEN_Msk            (0x1U << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */\n#define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit                   */\n#define SDIO_CMD_SDIOSUSPEND_Pos       (11U)\n#define SDIO_CMD_SDIOSUSPEND_Msk       (0x1U << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */\n#define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command                                         */\n\n/*****************  Bit definition for SDIO_RESPCMD register  *****************/\n#define SDIO_RESPCMD_RESPCMD_Pos       (0U)\n#define SDIO_RESPCMD_RESPCMD_Msk       (0x3FU << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */\n#define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */\n\n/******************  Bit definition for SDIO_RESP0 register  ******************/\n#define SDIO_RESP0_CARDSTATUS0_Pos     (0U)\n#define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP1 register  ******************/\n#define SDIO_RESP1_CARDSTATUS1_Pos     (0U)\n#define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP2 register  ******************/\n#define SDIO_RESP2_CARDSTATUS2_Pos     (0U)\n#define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP3 register  ******************/\n#define SDIO_RESP3_CARDSTATUS3_Pos     (0U)\n#define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP4 register  ******************/\n#define SDIO_RESP4_CARDSTATUS4_Pos     (0U)\n#define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_DTIMER register  *****************/\n#define SDIO_DTIMER_DATATIME_Pos       (0U)\n#define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */\n\n/******************  Bit definition for SDIO_DLEN register  *******************/\n#define SDIO_DLEN_DATALENGTH_Pos       (0U)\n#define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */\n\n/******************  Bit definition for SDIO_DCTRL register  ******************/\n#define SDIO_DCTRL_DTEN_Pos            (0U)\n#define SDIO_DCTRL_DTEN_Msk            (0x1U << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */\n#define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit         */\n#define SDIO_DCTRL_DTDIR_Pos           (1U)\n#define SDIO_DCTRL_DTDIR_Msk           (0x1U << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */\n#define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */\n#define SDIO_DCTRL_DTMODE_Pos          (2U)\n#define SDIO_DCTRL_DTMODE_Msk          (0x1U << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */\n#define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection      */\n#define SDIO_DCTRL_DMAEN_Pos           (3U)\n#define SDIO_DCTRL_DMAEN_Msk           (0x1U << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */\n#define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit                   */\n\n#define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)\n#define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */\n#define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */\n#define SDIO_DCTRL_DBLOCKSIZE_0        (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0010 */\n#define SDIO_DCTRL_DBLOCKSIZE_1        (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0020 */\n#define SDIO_DCTRL_DBLOCKSIZE_2        (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0040 */\n#define SDIO_DCTRL_DBLOCKSIZE_3        (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0080 */\n\n#define SDIO_DCTRL_RWSTART_Pos         (8U)\n#define SDIO_DCTRL_RWSTART_Msk         (0x1U << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */\n#define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start         */\n#define SDIO_DCTRL_RWSTOP_Pos          (9U)\n#define SDIO_DCTRL_RWSTOP_Msk          (0x1U << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */\n#define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop          */\n#define SDIO_DCTRL_RWMOD_Pos           (10U)\n#define SDIO_DCTRL_RWMOD_Msk           (0x1U << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */\n#define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode          */\n#define SDIO_DCTRL_SDIOEN_Pos          (11U)\n#define SDIO_DCTRL_SDIOEN_Msk          (0x1U << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */\n#define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */\n\n/******************  Bit definition for SDIO_DCOUNT register  *****************/\n#define SDIO_DCOUNT_DATACOUNT_Pos      (0U)\n#define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */\n\n/******************  Bit definition for SDIO_STA register  ********************/\n#define SDIO_STA_CCRCFAIL_Pos          (0U)\n#define SDIO_STA_CCRCFAIL_Msk          (0x1U << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */\n#define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */\n#define SDIO_STA_DCRCFAIL_Pos          (1U)\n#define SDIO_STA_DCRCFAIL_Msk          (0x1U << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */\n#define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */\n#define SDIO_STA_CTIMEOUT_Pos          (2U)\n#define SDIO_STA_CTIMEOUT_Msk          (0x1U << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */\n#define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */\n#define SDIO_STA_DTIMEOUT_Pos          (3U)\n#define SDIO_STA_DTIMEOUT_Msk          (0x1U << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */\n#define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */\n#define SDIO_STA_TXUNDERR_Pos          (4U)\n#define SDIO_STA_TXUNDERR_Msk          (0x1U << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */\n#define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */\n#define SDIO_STA_RXOVERR_Pos           (5U)\n#define SDIO_STA_RXOVERR_Msk           (0x1U << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */\n#define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */\n#define SDIO_STA_CMDREND_Pos           (6U)\n#define SDIO_STA_CMDREND_Msk           (0x1U << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */\n#define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */\n#define SDIO_STA_CMDSENT_Pos           (7U)\n#define SDIO_STA_CMDSENT_Msk           (0x1U << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */\n#define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */\n#define SDIO_STA_DATAEND_Pos           (8U)\n#define SDIO_STA_DATAEND_Msk           (0x1U << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */\n#define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */\n#define SDIO_STA_DBCKEND_Pos           (10U)\n#define SDIO_STA_DBCKEND_Msk           (0x1U << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */\n#define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */\n#define SDIO_STA_CMDACT_Pos            (11U)\n#define SDIO_STA_CMDACT_Msk            (0x1U << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */\n#define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */\n#define SDIO_STA_TXACT_Pos             (12U)\n#define SDIO_STA_TXACT_Msk             (0x1U << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */\n#define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */\n#define SDIO_STA_RXACT_Pos             (13U)\n#define SDIO_STA_RXACT_Msk             (0x1U << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */\n#define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */\n#define SDIO_STA_TXFIFOHE_Pos          (14U)\n#define SDIO_STA_TXFIFOHE_Msk          (0x1U << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */\n#define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\n#define SDIO_STA_RXFIFOHF_Pos          (15U)\n#define SDIO_STA_RXFIFOHF_Msk          (0x1U << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */\n#define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\n#define SDIO_STA_TXFIFOF_Pos           (16U)\n#define SDIO_STA_TXFIFOF_Msk           (0x1U << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */\n#define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */\n#define SDIO_STA_RXFIFOF_Pos           (17U)\n#define SDIO_STA_RXFIFOF_Msk           (0x1U << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */\n#define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */\n#define SDIO_STA_TXFIFOE_Pos           (18U)\n#define SDIO_STA_TXFIFOE_Msk           (0x1U << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */\n#define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */\n#define SDIO_STA_RXFIFOE_Pos           (19U)\n#define SDIO_STA_RXFIFOE_Msk           (0x1U << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */\n#define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */\n#define SDIO_STA_TXDAVL_Pos            (20U)\n#define SDIO_STA_TXDAVL_Msk            (0x1U << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */\n#define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */\n#define SDIO_STA_RXDAVL_Pos            (21U)\n#define SDIO_STA_RXDAVL_Msk            (0x1U << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */\n#define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */\n#define SDIO_STA_SDIOIT_Pos            (22U)\n#define SDIO_STA_SDIOIT_Msk            (0x1U << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */\n#define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */\n\n/*******************  Bit definition for SDIO_ICR register  *******************/\n#define SDIO_ICR_CCRCFAILC_Pos         (0U)\n#define SDIO_ICR_CCRCFAILC_Msk         (0x1U << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */\n#define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */\n#define SDIO_ICR_DCRCFAILC_Pos         (1U)\n#define SDIO_ICR_DCRCFAILC_Msk         (0x1U << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */\n#define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */\n#define SDIO_ICR_CTIMEOUTC_Pos         (2U)\n#define SDIO_ICR_CTIMEOUTC_Msk         (0x1U << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */\n#define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */\n#define SDIO_ICR_DTIMEOUTC_Pos         (3U)\n#define SDIO_ICR_DTIMEOUTC_Msk         (0x1U << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */\n#define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */\n#define SDIO_ICR_TXUNDERRC_Pos         (4U)\n#define SDIO_ICR_TXUNDERRC_Msk         (0x1U << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */\n#define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */\n#define SDIO_ICR_RXOVERRC_Pos          (5U)\n#define SDIO_ICR_RXOVERRC_Msk          (0x1U << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */\n#define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */\n#define SDIO_ICR_CMDRENDC_Pos          (6U)\n#define SDIO_ICR_CMDRENDC_Msk          (0x1U << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */\n#define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */\n#define SDIO_ICR_CMDSENTC_Pos          (7U)\n#define SDIO_ICR_CMDSENTC_Msk          (0x1U << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */\n#define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */\n#define SDIO_ICR_DATAENDC_Pos          (8U)\n#define SDIO_ICR_DATAENDC_Msk          (0x1U << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */\n#define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */\n#define SDIO_ICR_DBCKENDC_Pos          (10U)\n#define SDIO_ICR_DBCKENDC_Msk          (0x1U << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */\n#define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */\n#define SDIO_ICR_SDIOITC_Pos           (22U)\n#define SDIO_ICR_SDIOITC_Msk           (0x1U << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */\n#define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */\n\n/******************  Bit definition for SDIO_MASK register  *******************/\n#define SDIO_MASK_CCRCFAILIE_Pos       (0U)\n#define SDIO_MASK_CCRCFAILIE_Msk       (0x1U << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */\n#define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */\n#define SDIO_MASK_DCRCFAILIE_Pos       (1U)\n#define SDIO_MASK_DCRCFAILIE_Msk       (0x1U << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */\n#define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */\n#define SDIO_MASK_CTIMEOUTIE_Pos       (2U)\n#define SDIO_MASK_CTIMEOUTIE_Msk       (0x1U << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */\n#define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */\n#define SDIO_MASK_DTIMEOUTIE_Pos       (3U)\n#define SDIO_MASK_DTIMEOUTIE_Msk       (0x1U << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */\n#define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */\n#define SDIO_MASK_TXUNDERRIE_Pos       (4U)\n#define SDIO_MASK_TXUNDERRIE_Msk       (0x1U << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */\n#define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */\n#define SDIO_MASK_RXOVERRIE_Pos        (5U)\n#define SDIO_MASK_RXOVERRIE_Msk        (0x1U << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */\n#define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */\n#define SDIO_MASK_CMDRENDIE_Pos        (6U)\n#define SDIO_MASK_CMDRENDIE_Msk        (0x1U << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */\n#define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */\n#define SDIO_MASK_CMDSENTIE_Pos        (7U)\n#define SDIO_MASK_CMDSENTIE_Msk        (0x1U << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */\n#define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */\n#define SDIO_MASK_DATAENDIE_Pos        (8U)\n#define SDIO_MASK_DATAENDIE_Msk        (0x1U << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */\n#define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */\n#define SDIO_MASK_DBCKENDIE_Pos        (10U)\n#define SDIO_MASK_DBCKENDIE_Msk        (0x1U << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */\n#define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */\n#define SDIO_MASK_CMDACTIE_Pos         (11U)\n#define SDIO_MASK_CMDACTIE_Msk         (0x1U << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */\n#define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */\n#define SDIO_MASK_TXACTIE_Pos          (12U)\n#define SDIO_MASK_TXACTIE_Msk          (0x1U << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */\n#define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */\n#define SDIO_MASK_RXACTIE_Pos          (13U)\n#define SDIO_MASK_RXACTIE_Msk          (0x1U << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */\n#define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */\n#define SDIO_MASK_TXFIFOHEIE_Pos       (14U)\n#define SDIO_MASK_TXFIFOHEIE_Msk       (0x1U << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */\n#define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */\n#define SDIO_MASK_RXFIFOHFIE_Pos       (15U)\n#define SDIO_MASK_RXFIFOHFIE_Msk       (0x1U << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */\n#define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */\n#define SDIO_MASK_TXFIFOFIE_Pos        (16U)\n#define SDIO_MASK_TXFIFOFIE_Msk        (0x1U << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */\n#define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */\n#define SDIO_MASK_RXFIFOFIE_Pos        (17U)\n#define SDIO_MASK_RXFIFOFIE_Msk        (0x1U << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */\n#define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */\n#define SDIO_MASK_TXFIFOEIE_Pos        (18U)\n#define SDIO_MASK_TXFIFOEIE_Msk        (0x1U << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */\n#define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_RXFIFOEIE_Pos        (19U)\n#define SDIO_MASK_RXFIFOEIE_Msk        (0x1U << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */\n#define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_TXDAVLIE_Pos         (20U)\n#define SDIO_MASK_TXDAVLIE_Msk         (0x1U << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */\n#define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */\n#define SDIO_MASK_RXDAVLIE_Pos         (21U)\n#define SDIO_MASK_RXDAVLIE_Msk         (0x1U << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */\n#define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */\n#define SDIO_MASK_SDIOITIE_Pos         (22U)\n#define SDIO_MASK_SDIOITIE_Msk         (0x1U << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */\n#define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */\n\n/*****************  Bit definition for SDIO_FIFOCNT register  *****************/\n#define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)\n#define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */\n#define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */\n\n/******************  Bit definition for SDIO_FIFO register  *******************/\n#define SDIO_FIFO_FIFODATA_Pos         (0U)\n#define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Serial Peripheral Interface                         */\n/*                                                                            */\n/******************************************************************************/\n#define SPI_I2S_FULLDUPLEX_SUPPORT                                             /*!< I2S Full-Duplex support */\n\n/*******************  Bit definition for SPI_CR1 register  ********************/\n#define SPI_CR1_CPHA_Pos            (0U)\n#define SPI_CR1_CPHA_Msk            (0x1U << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */\n#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */\n#define SPI_CR1_CPOL_Pos            (1U)\n#define SPI_CR1_CPOL_Msk            (0x1U << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */\n#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */\n#define SPI_CR1_MSTR_Pos            (2U)\n#define SPI_CR1_MSTR_Msk            (0x1U << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */\n#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */\n\n#define SPI_CR1_BR_Pos              (3U)\n#define SPI_CR1_BR_Msk              (0x7U << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */\n#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */\n#define SPI_CR1_BR_0                (0x1U << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */\n#define SPI_CR1_BR_1                (0x2U << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */\n#define SPI_CR1_BR_2                (0x4U << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */\n\n#define SPI_CR1_SPE_Pos             (6U)\n#define SPI_CR1_SPE_Msk             (0x1U << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */\n#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */\n#define SPI_CR1_LSBFIRST_Pos        (7U)\n#define SPI_CR1_LSBFIRST_Msk        (0x1U << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */\n#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */\n#define SPI_CR1_SSI_Pos             (8U)\n#define SPI_CR1_SSI_Msk             (0x1U << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */\n#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */\n#define SPI_CR1_SSM_Pos             (9U)\n#define SPI_CR1_SSM_Msk             (0x1U << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */\n#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */\n#define SPI_CR1_RXONLY_Pos          (10U)\n#define SPI_CR1_RXONLY_Msk          (0x1U << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */\n#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */\n#define SPI_CR1_DFF_Pos             (11U)\n#define SPI_CR1_DFF_Msk             (0x1U << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */\n#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */\n#define SPI_CR1_CRCNEXT_Pos         (12U)\n#define SPI_CR1_CRCNEXT_Msk         (0x1U << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */\n#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */\n#define SPI_CR1_CRCEN_Pos           (13U)\n#define SPI_CR1_CRCEN_Msk           (0x1U << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */\n#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */\n#define SPI_CR1_BIDIOE_Pos          (14U)\n#define SPI_CR1_BIDIOE_Msk          (0x1U << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */\n#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */\n#define SPI_CR1_BIDIMODE_Pos        (15U)\n#define SPI_CR1_BIDIMODE_Msk        (0x1U << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */\n#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */\n\n/*******************  Bit definition for SPI_CR2 register  ********************/\n#define SPI_CR2_RXDMAEN_Pos         (0U)\n#define SPI_CR2_RXDMAEN_Msk         (0x1U << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */\n#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */\n#define SPI_CR2_TXDMAEN_Pos         (1U)\n#define SPI_CR2_TXDMAEN_Msk         (0x1U << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */\n#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */\n#define SPI_CR2_SSOE_Pos            (2U)\n#define SPI_CR2_SSOE_Msk            (0x1U << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */\n#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */\n#define SPI_CR2_FRF_Pos             (4U)\n#define SPI_CR2_FRF_Msk             (0x1U << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */\n#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */\n#define SPI_CR2_ERRIE_Pos           (5U)\n#define SPI_CR2_ERRIE_Msk           (0x1U << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */\n#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */\n#define SPI_CR2_RXNEIE_Pos          (6U)\n#define SPI_CR2_RXNEIE_Msk          (0x1U << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */\n#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */\n#define SPI_CR2_TXEIE_Pos           (7U)\n#define SPI_CR2_TXEIE_Msk           (0x1U << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */\n#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */\n\n/********************  Bit definition for SPI_SR register  ********************/\n#define SPI_SR_RXNE_Pos             (0U)\n#define SPI_SR_RXNE_Msk             (0x1U << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */\n#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */\n#define SPI_SR_TXE_Pos              (1U)\n#define SPI_SR_TXE_Msk              (0x1U << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */\n#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */\n#define SPI_SR_CHSIDE_Pos           (2U)\n#define SPI_SR_CHSIDE_Msk           (0x1U << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */\n#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */\n#define SPI_SR_UDR_Pos              (3U)\n#define SPI_SR_UDR_Msk              (0x1U << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */\n#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */\n#define SPI_SR_CRCERR_Pos           (4U)\n#define SPI_SR_CRCERR_Msk           (0x1U << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */\n#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */\n#define SPI_SR_MODF_Pos             (5U)\n#define SPI_SR_MODF_Msk             (0x1U << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */\n#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */\n#define SPI_SR_OVR_Pos              (6U)\n#define SPI_SR_OVR_Msk              (0x1U << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */\n#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */\n#define SPI_SR_BSY_Pos              (7U)\n#define SPI_SR_BSY_Msk              (0x1U << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */\n#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */\n#define SPI_SR_FRE_Pos              (8U)\n#define SPI_SR_FRE_Msk              (0x1U << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */\n#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */\n\n/********************  Bit definition for SPI_DR register  ********************/\n#define SPI_DR_DR_Pos               (0U)\n#define SPI_DR_DR_Msk               (0xFFFFU << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */\n#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */\n\n/*******************  Bit definition for SPI_CRCPR register  ******************/\n#define SPI_CRCPR_CRCPOLY_Pos       (0U)\n#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */\n#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */\n\n/******************  Bit definition for SPI_RXCRCR register  ******************/\n#define SPI_RXCRCR_RXCRC_Pos        (0U)\n#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */\n\n/******************  Bit definition for SPI_TXCRCR register  ******************/\n#define SPI_TXCRCR_TXCRC_Pos        (0U)\n#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */\n\n/******************  Bit definition for SPI_I2SCFGR register  *****************/\n#define SPI_I2SCFGR_CHLEN_Pos       (0U)\n#define SPI_I2SCFGR_CHLEN_Msk       (0x1U << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */\n#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */\n\n#define SPI_I2SCFGR_DATLEN_Pos      (1U)\n#define SPI_I2SCFGR_DATLEN_Msk      (0x3U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */\n#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */\n#define SPI_I2SCFGR_DATLEN_0        (0x1U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */\n#define SPI_I2SCFGR_DATLEN_1        (0x2U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */\n\n#define SPI_I2SCFGR_CKPOL_Pos       (3U)\n#define SPI_I2SCFGR_CKPOL_Msk       (0x1U << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */\n#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */\n\n#define SPI_I2SCFGR_I2SSTD_Pos      (4U)\n#define SPI_I2SCFGR_I2SSTD_Msk      (0x3U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */\n#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */\n#define SPI_I2SCFGR_I2SSTD_0        (0x1U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */\n#define SPI_I2SCFGR_I2SSTD_1        (0x2U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */\n\n#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)\n#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1U << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */\n#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */\n\n#define SPI_I2SCFGR_I2SCFG_Pos      (8U)\n#define SPI_I2SCFGR_I2SCFG_Msk      (0x3U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */\n#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */\n#define SPI_I2SCFGR_I2SCFG_0        (0x1U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */\n#define SPI_I2SCFGR_I2SCFG_1        (0x2U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */\n\n#define SPI_I2SCFGR_I2SE_Pos        (10U)\n#define SPI_I2SCFGR_I2SE_Msk        (0x1U << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */\n#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */\n#define SPI_I2SCFGR_I2SMOD_Pos      (11U)\n#define SPI_I2SCFGR_I2SMOD_Msk      (0x1U << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */\n#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */\n#define SPI_I2SCFGR_ASTRTEN_Pos     (12U)\n#define SPI_I2SCFGR_ASTRTEN_Msk     (0x1U << SPI_I2SCFGR_ASTRTEN_Pos)          /*!< 0x00001000 */\n#define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */\n\n/******************  Bit definition for SPI_I2SPR register  *******************/\n#define SPI_I2SPR_I2SDIV_Pos        (0U)\n#define SPI_I2SPR_I2SDIV_Msk        (0xFFU << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */\n#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */\n#define SPI_I2SPR_ODD_Pos           (8U)\n#define SPI_I2SPR_ODD_Msk           (0x1U << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */\n#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */\n#define SPI_I2SPR_MCKOE_Pos         (9U)\n#define SPI_I2SPR_MCKOE_Msk         (0x1U << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */\n#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                 SYSCFG                                     */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SYSCFG_MEMRMP register  ***************/\n#define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)\n#define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */\n#define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */\n#define SYSCFG_MEMRMP_MEM_MODE_0             (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */\n#define SYSCFG_MEMRMP_MEM_MODE_1             (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */\n#define SYSCFG_MEMRMP_MEM_MODE_2             (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */\n#define SYSCFG_MEMRMP_UFB_MODE_Pos           (8U)\n#define SYSCFG_MEMRMP_UFB_MODE_Msk           (0x1U << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */\n#define SYSCFG_MEMRMP_UFB_MODE               SYSCFG_MEMRMP_UFB_MODE_Msk        /*!< User Flash Bank mode    */\n#define SYSCFG_MEMRMP_SWP_FMC_Pos            (10U)\n#define SYSCFG_MEMRMP_SWP_FMC_Msk            (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */\n#define SYSCFG_MEMRMP_SWP_FMC                SYSCFG_MEMRMP_SWP_FMC_Msk         /*!< FMC memory mapping swap */\n#define SYSCFG_MEMRMP_SWP_FMC_0              (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */\n/* Legacy Defines */\n#define SYSCFG_SWP_FMC                  SYSCFG_MEMRMP_SWP_FMC\n/******************  Bit definition for SYSCFG_PMC register  ******************/\n#define SYSCFG_PMC_ADCxDC2_Pos               (16U)\n#define SYSCFG_PMC_ADCxDC2_Msk               (0x7U << SYSCFG_PMC_ADCxDC2_Pos)  /*!< 0x00070000 */\n#define SYSCFG_PMC_ADCxDC2                   SYSCFG_PMC_ADCxDC2_Msk            /*!< Refer to AN4073 on how to use this bit  */\n#define SYSCFG_PMC_ADC1DC2_Pos               (16U)\n#define SYSCFG_PMC_ADC1DC2_Msk               (0x1U << SYSCFG_PMC_ADC1DC2_Pos)  /*!< 0x00010000 */\n#define SYSCFG_PMC_ADC1DC2                   SYSCFG_PMC_ADC1DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */\n#define SYSCFG_PMC_ADC2DC2_Pos               (17U)\n#define SYSCFG_PMC_ADC2DC2_Msk               (0x1U << SYSCFG_PMC_ADC2DC2_Pos)  /*!< 0x00020000 */\n#define SYSCFG_PMC_ADC2DC2                   SYSCFG_PMC_ADC2DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */\n#define SYSCFG_PMC_ADC3DC2_Pos               (18U)\n#define SYSCFG_PMC_ADC3DC2_Msk               (0x1U << SYSCFG_PMC_ADC3DC2_Pos)  /*!< 0x00040000 */\n#define SYSCFG_PMC_ADC3DC2                   SYSCFG_PMC_ADC3DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */\n#define SYSCFG_PMC_MII_RMII_SEL_Pos          (23U)\n#define SYSCFG_PMC_MII_RMII_SEL_Msk          (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */\n#define SYSCFG_PMC_MII_RMII_SEL              SYSCFG_PMC_MII_RMII_SEL_Msk       /*!<Ethernet PHY interface selection */\n\n/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\n#define SYSCFG_EXTICR1_EXTI0_Pos             (0U)\n#define SYSCFG_EXTICR1_EXTI0_Msk             (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */\n#define SYSCFG_EXTICR1_EXTI1_Pos             (4U)\n#define SYSCFG_EXTICR1_EXTI1_Msk             (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */\n#define SYSCFG_EXTICR1_EXTI2_Pos             (8U)\n#define SYSCFG_EXTICR1_EXTI2_Msk             (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */\n#define SYSCFG_EXTICR1_EXTI3_Pos             (12U)\n#define SYSCFG_EXTICR1_EXTI3_Msk             (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */\n/**\n  * @brief   EXTI0 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PD              0x0003U                           /*!<PD[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PE              0x0004U                           /*!<PE[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PF              0x0005U                           /*!<PF[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PG              0x0006U                           /*!<PG[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PI              0x0008U                           /*!<PI[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PJ              0x0009U                           /*!<PJ[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PK              0x000AU                           /*!<PK[0] pin */\n\n/**\n  * @brief   EXTI1 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PD              0x0030U                           /*!<PD[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PE              0x0040U                           /*!<PE[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PF              0x0050U                           /*!<PF[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PG              0x0060U                           /*!<PG[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PI              0x0080U                           /*!<PI[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PJ              0x0090U                           /*!<PJ[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PK              0x00A0U                           /*!<PK[1] pin */\n\n/**\n  * @brief   EXTI2 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PD              0x0300U                           /*!<PD[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PE              0x0400U                           /*!<PE[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PF              0x0500U                           /*!<PF[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PG              0x0600U                           /*!<PG[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PI              0x0800U                           /*!<PI[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PJ              0x0900U                           /*!<PJ[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PK              0x0A00U                           /*!<PK[2] pin */\n\n/**\n  * @brief   EXTI3 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PD              0x3000U                           /*!<PD[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PE              0x4000U                           /*!<PE[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PF              0x5000U                           /*!<PF[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PG              0x6000U                           /*!<PG[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PI              0x8000U                           /*!<PI[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PJ              0x9000U                           /*!<PJ[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PK              0xA000U                           /*!<PK[3] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\n#define SYSCFG_EXTICR2_EXTI4_Pos             (0U)\n#define SYSCFG_EXTICR2_EXTI4_Msk             (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */\n#define SYSCFG_EXTICR2_EXTI5_Pos             (4U)\n#define SYSCFG_EXTICR2_EXTI5_Msk             (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */\n#define SYSCFG_EXTICR2_EXTI6_Pos             (8U)\n#define SYSCFG_EXTICR2_EXTI6_Msk             (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */\n#define SYSCFG_EXTICR2_EXTI7_Pos             (12U)\n#define SYSCFG_EXTICR2_EXTI7_Msk             (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */\n\n/**\n  * @brief   EXTI4 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PD              0x0003U                           /*!<PD[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PE              0x0004U                           /*!<PE[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PF              0x0005U                           /*!<PF[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PG              0x0006U                           /*!<PG[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PI              0x0008U                           /*!<PI[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PJ              0x0009U                           /*!<PJ[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PK              0x000AU                           /*!<PK[4] pin */\n\n/**\n  * @brief   EXTI5 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PD              0x0030U                           /*!<PD[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PE              0x0040U                           /*!<PE[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PF              0x0050U                           /*!<PF[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PG              0x0060U                           /*!<PG[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PI              0x0080U                           /*!<PI[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PJ              0x0090U                           /*!<PJ[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PK              0x00A0U                           /*!<PK[5] pin */\n\n/**\n  * @brief   EXTI6 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PD              0x0300U                           /*!<PD[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PE              0x0400U                           /*!<PE[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PF              0x0500U                           /*!<PF[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PG              0x0600U                           /*!<PG[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PI              0x0800U                           /*!<PI[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PJ              0x0900U                           /*!<PJ[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PK              0x0A00U                           /*!<PK[6] pin */\n\n/**\n  * @brief   EXTI7 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PD              0x3000U                           /*!<PD[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PE              0x4000U                           /*!<PE[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PF              0x5000U                           /*!<PF[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PG              0x6000U                           /*!<PG[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PI              0x8000U                           /*!<PI[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PJ              0x9000U                           /*!<PJ[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PK              0xA000U                           /*!<PK[7] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\n#define SYSCFG_EXTICR3_EXTI8_Pos             (0U)\n#define SYSCFG_EXTICR3_EXTI8_Msk             (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */\n#define SYSCFG_EXTICR3_EXTI9_Pos             (4U)\n#define SYSCFG_EXTICR3_EXTI9_Msk             (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */\n#define SYSCFG_EXTICR3_EXTI10_Pos            (8U)\n#define SYSCFG_EXTICR3_EXTI10_Msk            (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */\n#define SYSCFG_EXTICR3_EXTI11_Pos            (12U)\n#define SYSCFG_EXTICR3_EXTI11_Msk            (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */\n\n/**\n  * @brief   EXTI8 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PD              0x0003U                           /*!<PD[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PE              0x0004U                           /*!<PE[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PF              0x0005U                           /*!<PF[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PG              0x0006U                           /*!<PG[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PI              0x0008U                           /*!<PI[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PJ              0x0009U                           /*!<PJ[8] pin */\n\n/**\n  * @brief   EXTI9 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PD              0x0030U                           /*!<PD[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PE              0x0040U                           /*!<PE[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PF              0x0050U                           /*!<PF[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PG              0x0060U                           /*!<PG[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PI              0x0080U                           /*!<PI[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PJ              0x0090U                           /*!<PJ[9] pin */\n\n/**\n  * @brief   EXTI10 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PD             0x0300U                           /*!<PD[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PE             0x0400U                           /*!<PE[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PF             0x0500U                           /*!<PF[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PG             0x0600U                           /*!<PG[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PI             0x0800U                           /*!<PI[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PJ             0x0900U                           /*!<PJ[10] pin */\n\n/**\n  * @brief   EXTI11 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PD             0x3000U                           /*!<PD[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PE             0x4000U                           /*!<PE[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PF             0x5000U                           /*!<PF[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PG             0x6000U                           /*!<PG[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PI             0x8000U                           /*!<PI[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PJ             0x9000U                           /*!<PJ[11] pin */\n\n\n/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\n#define SYSCFG_EXTICR4_EXTI12_Pos            (0U)\n#define SYSCFG_EXTICR4_EXTI12_Msk            (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */\n#define SYSCFG_EXTICR4_EXTI13_Pos            (4U)\n#define SYSCFG_EXTICR4_EXTI13_Msk            (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */\n#define SYSCFG_EXTICR4_EXTI14_Pos            (8U)\n#define SYSCFG_EXTICR4_EXTI14_Msk            (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */\n#define SYSCFG_EXTICR4_EXTI15_Pos            (12U)\n#define SYSCFG_EXTICR4_EXTI15_Msk            (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */\n\n/**\n  * @brief   EXTI12 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PD             0x0003U                           /*!<PD[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PE             0x0004U                           /*!<PE[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PF             0x0005U                           /*!<PF[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PG             0x0006U                           /*!<PG[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PI             0x0008U                           /*!<PI[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PJ             0x0009U                           /*!<PJ[12] pin */\n\n/**\n  * @brief   EXTI13 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PD             0x0030U                           /*!<PD[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PE             0x0040U                           /*!<PE[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PF             0x0050U                           /*!<PF[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PG             0x0060U                           /*!<PG[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PI             0x0008U                           /*!<PI[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PJ             0x0009U                           /*!<PJ[13] pin */\n\n/**\n  * @brief   EXTI14 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PD             0x0300U                           /*!<PD[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PE             0x0400U                           /*!<PE[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PF             0x0500U                           /*!<PF[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PG             0x0600U                           /*!<PG[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PI             0x0800U                           /*!<PI[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PJ             0x0900U                           /*!<PJ[14] pin */\n\n/**\n  * @brief   EXTI15 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PD             0x3000U                           /*!<PD[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PE             0x4000U                           /*!<PE[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PF             0x5000U                           /*!<PF[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PG             0x6000U                           /*!<PG[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PI             0x8000U                           /*!<PI[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PJ             0x9000U                           /*!<PJ[15] pin */\n\n/******************  Bit definition for SYSCFG_CMPCR register  ****************/\n#define SYSCFG_CMPCR_CMP_PD_Pos              (0U)\n#define SYSCFG_CMPCR_CMP_PD_Msk              (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */\n#define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */\n#define SYSCFG_CMPCR_READY_Pos               (8U)\n#define SYSCFG_CMPCR_READY_Msk               (0x1U << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */\n#define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    TIM                                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for TIM_CR1 register  ********************/\n#define TIM_CR1_CEN_Pos           (0U)\n#define TIM_CR1_CEN_Msk           (0x1U << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */\n#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */\n#define TIM_CR1_UDIS_Pos          (1U)\n#define TIM_CR1_UDIS_Msk          (0x1U << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */\n#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */\n#define TIM_CR1_URS_Pos           (2U)\n#define TIM_CR1_URS_Msk           (0x1U << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */\n#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */\n#define TIM_CR1_OPM_Pos           (3U)\n#define TIM_CR1_OPM_Msk           (0x1U << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */\n#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */\n#define TIM_CR1_DIR_Pos           (4U)\n#define TIM_CR1_DIR_Msk           (0x1U << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */\n#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */\n\n#define TIM_CR1_CMS_Pos           (5U)\n#define TIM_CR1_CMS_Msk           (0x3U << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */\n#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */\n#define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR1_ARPE_Pos          (7U)\n#define TIM_CR1_ARPE_Msk          (0x1U << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */\n#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */\n\n#define TIM_CR1_CKD_Pos           (8U)\n#define TIM_CR1_CKD_Msk           (0x3U << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */\n#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */\n#define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */\n#define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */\n\n/*******************  Bit definition for TIM_CR2 register  ********************/\n#define TIM_CR2_CCPC_Pos          (0U)\n#define TIM_CR2_CCPC_Msk          (0x1U << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */\n#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */\n#define TIM_CR2_CCUS_Pos          (2U)\n#define TIM_CR2_CCUS_Msk          (0x1U << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */\n#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */\n#define TIM_CR2_CCDS_Pos          (3U)\n#define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */\n#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */\n\n#define TIM_CR2_MMS_Pos           (4U)\n#define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */\n#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */\n#define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */\n#define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR2_TI1S_Pos          (7U)\n#define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */\n#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */\n#define TIM_CR2_OIS1_Pos          (8U)\n#define TIM_CR2_OIS1_Msk          (0x1U << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */\n#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */\n#define TIM_CR2_OIS1N_Pos         (9U)\n#define TIM_CR2_OIS1N_Msk         (0x1U << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */\n#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */\n#define TIM_CR2_OIS2_Pos          (10U)\n#define TIM_CR2_OIS2_Msk          (0x1U << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */\n#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */\n#define TIM_CR2_OIS2N_Pos         (11U)\n#define TIM_CR2_OIS2N_Msk         (0x1U << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */\n#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */\n#define TIM_CR2_OIS3_Pos          (12U)\n#define TIM_CR2_OIS3_Msk          (0x1U << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */\n#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */\n#define TIM_CR2_OIS3N_Pos         (13U)\n#define TIM_CR2_OIS3N_Msk         (0x1U << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */\n#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */\n#define TIM_CR2_OIS4_Pos          (14U)\n#define TIM_CR2_OIS4_Msk          (0x1U << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */\n#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */\n\n/*******************  Bit definition for TIM_SMCR register  *******************/\n#define TIM_SMCR_SMS_Pos          (0U)\n#define TIM_SMCR_SMS_Msk          (0x7U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */\n#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */\n#define TIM_SMCR_SMS_0            (0x1U << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */\n#define TIM_SMCR_SMS_1            (0x2U << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */\n#define TIM_SMCR_SMS_2            (0x4U << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */\n\n#define TIM_SMCR_TS_Pos           (4U)\n#define TIM_SMCR_TS_Msk           (0x7U << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */\n#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */\n#define TIM_SMCR_TS_0             (0x1U << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */\n#define TIM_SMCR_TS_1             (0x2U << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */\n#define TIM_SMCR_TS_2             (0x4U << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */\n\n#define TIM_SMCR_MSM_Pos          (7U)\n#define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */\n#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */\n\n#define TIM_SMCR_ETF_Pos          (8U)\n#define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */\n#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */\n#define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */\n#define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */\n#define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */\n#define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */\n\n#define TIM_SMCR_ETPS_Pos         (12U)\n#define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */\n#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */\n#define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */\n#define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */\n\n#define TIM_SMCR_ECE_Pos          (14U)\n#define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */\n#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */\n#define TIM_SMCR_ETP_Pos          (15U)\n#define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */\n#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */\n\n/*******************  Bit definition for TIM_DIER register  *******************/\n#define TIM_DIER_UIE_Pos          (0U)\n#define TIM_DIER_UIE_Msk          (0x1U << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */\n#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */\n#define TIM_DIER_CC1IE_Pos        (1U)\n#define TIM_DIER_CC1IE_Msk        (0x1U << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */\n#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */\n#define TIM_DIER_CC2IE_Pos        (2U)\n#define TIM_DIER_CC2IE_Msk        (0x1U << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */\n#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */\n#define TIM_DIER_CC3IE_Pos        (3U)\n#define TIM_DIER_CC3IE_Msk        (0x1U << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */\n#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */\n#define TIM_DIER_CC4IE_Pos        (4U)\n#define TIM_DIER_CC4IE_Msk        (0x1U << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */\n#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */\n#define TIM_DIER_COMIE_Pos        (5U)\n#define TIM_DIER_COMIE_Msk        (0x1U << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */\n#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */\n#define TIM_DIER_TIE_Pos          (6U)\n#define TIM_DIER_TIE_Msk          (0x1U << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */\n#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */\n#define TIM_DIER_BIE_Pos          (7U)\n#define TIM_DIER_BIE_Msk          (0x1U << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */\n#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */\n#define TIM_DIER_UDE_Pos          (8U)\n#define TIM_DIER_UDE_Msk          (0x1U << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */\n#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */\n#define TIM_DIER_CC1DE_Pos        (9U)\n#define TIM_DIER_CC1DE_Msk        (0x1U << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */\n#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */\n#define TIM_DIER_CC2DE_Pos        (10U)\n#define TIM_DIER_CC2DE_Msk        (0x1U << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */\n#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */\n#define TIM_DIER_CC3DE_Pos        (11U)\n#define TIM_DIER_CC3DE_Msk        (0x1U << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */\n#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */\n#define TIM_DIER_CC4DE_Pos        (12U)\n#define TIM_DIER_CC4DE_Msk        (0x1U << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */\n#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */\n#define TIM_DIER_COMDE_Pos        (13U)\n#define TIM_DIER_COMDE_Msk        (0x1U << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */\n#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */\n#define TIM_DIER_TDE_Pos          (14U)\n#define TIM_DIER_TDE_Msk          (0x1U << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */\n#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */\n\n/********************  Bit definition for TIM_SR register  ********************/\n#define TIM_SR_UIF_Pos            (0U)\n#define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */\n#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */\n#define TIM_SR_CC1IF_Pos          (1U)\n#define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */\n#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */\n#define TIM_SR_CC2IF_Pos          (2U)\n#define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */\n#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */\n#define TIM_SR_CC3IF_Pos          (3U)\n#define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */\n#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */\n#define TIM_SR_CC4IF_Pos          (4U)\n#define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */\n#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */\n#define TIM_SR_COMIF_Pos          (5U)\n#define TIM_SR_COMIF_Msk          (0x1U << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */\n#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */\n#define TIM_SR_TIF_Pos            (6U)\n#define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */\n#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */\n#define TIM_SR_BIF_Pos            (7U)\n#define TIM_SR_BIF_Msk            (0x1U << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */\n#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */\n#define TIM_SR_CC1OF_Pos          (9U)\n#define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */\n#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */\n#define TIM_SR_CC2OF_Pos          (10U)\n#define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */\n#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */\n#define TIM_SR_CC3OF_Pos          (11U)\n#define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */\n#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */\n#define TIM_SR_CC4OF_Pos          (12U)\n#define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */\n#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */\n\n/*******************  Bit definition for TIM_EGR register  ********************/\n#define TIM_EGR_UG_Pos            (0U)\n#define TIM_EGR_UG_Msk            (0x1U << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */\n#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */\n#define TIM_EGR_CC1G_Pos          (1U)\n#define TIM_EGR_CC1G_Msk          (0x1U << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */\n#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */\n#define TIM_EGR_CC2G_Pos          (2U)\n#define TIM_EGR_CC2G_Msk          (0x1U << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */\n#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */\n#define TIM_EGR_CC3G_Pos          (3U)\n#define TIM_EGR_CC3G_Msk          (0x1U << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */\n#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */\n#define TIM_EGR_CC4G_Pos          (4U)\n#define TIM_EGR_CC4G_Msk          (0x1U << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */\n#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */\n#define TIM_EGR_COMG_Pos          (5U)\n#define TIM_EGR_COMG_Msk          (0x1U << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */\n#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */\n#define TIM_EGR_TG_Pos            (6U)\n#define TIM_EGR_TG_Msk            (0x1U << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */\n#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */\n#define TIM_EGR_BG_Pos            (7U)\n#define TIM_EGR_BG_Msk            (0x1U << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */\n#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */\n\n/******************  Bit definition for TIM_CCMR1 register  *******************/\n#define TIM_CCMR1_CC1S_Pos        (0U)\n#define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\n#define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR1_OC1FE_Pos       (2U)\n#define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */\n#define TIM_CCMR1_OC1PE_Pos       (3U)\n#define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */\n\n#define TIM_CCMR1_OC1M_Pos        (4U)\n#define TIM_CCMR1_OC1M_Msk        (0x7U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */\n#define TIM_CCMR1_OC1M_0          (0x1U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_OC1M_1          (0x2U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_OC1M_2          (0x4U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR1_OC1CE_Pos       (7U)\n#define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */\n\n#define TIM_CCMR1_CC2S_Pos        (8U)\n#define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\n#define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR1_OC2FE_Pos       (10U)\n#define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */\n#define TIM_CCMR1_OC2PE_Pos       (11U)\n#define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */\n\n#define TIM_CCMR1_OC2M_Pos        (12U)\n#define TIM_CCMR1_OC2M_Msk        (0x7U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */\n#define TIM_CCMR1_OC2M_0          (0x1U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_OC2M_1          (0x2U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_OC2M_2          (0x4U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR1_OC2CE_Pos       (15U)\n#define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR1_IC1PSC_Pos      (2U)\n#define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\n#define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR1_IC1F_Pos        (4U)\n#define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */\n#define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR1_IC2PSC_Pos      (10U)\n#define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */\n#define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR1_IC2F_Pos        (12U)\n#define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */\n#define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */\n\n/******************  Bit definition for TIM_CCMR2 register  *******************/\n#define TIM_CCMR2_CC3S_Pos        (0U)\n#define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */\n#define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR2_OC3FE_Pos       (2U)\n#define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */\n#define TIM_CCMR2_OC3PE_Pos       (3U)\n#define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */\n\n#define TIM_CCMR2_OC3M_Pos        (4U)\n#define TIM_CCMR2_OC3M_Msk        (0x7U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\n#define TIM_CCMR2_OC3M_0          (0x1U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_OC3M_1          (0x2U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_OC3M_2          (0x4U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR2_OC3CE_Pos       (7U)\n#define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */\n\n#define TIM_CCMR2_CC4S_Pos        (8U)\n#define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\n#define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR2_OC4FE_Pos       (10U)\n#define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */\n#define TIM_CCMR2_OC4PE_Pos       (11U)\n#define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */\n\n#define TIM_CCMR2_OC4M_Pos        (12U)\n#define TIM_CCMR2_OC4M_Msk        (0x7U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\n#define TIM_CCMR2_OC4M_0          (0x1U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_OC4M_1          (0x2U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_OC4M_2          (0x4U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR2_OC4CE_Pos       (15U)\n#define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR2_IC3PSC_Pos      (2U)\n#define TIM_CCMR2_IC3PSC_Msk      (0x3U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\n#define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR2_IC3F_Pos        (4U)\n#define TIM_CCMR2_IC3F_Msk        (0xFU << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\n#define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR2_IC4PSC_Pos      (10U)\n#define TIM_CCMR2_IC4PSC_Msk      (0x3U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\n#define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR2_IC4F_Pos        (12U)\n#define TIM_CCMR2_IC4F_Msk        (0xFU << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\n#define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */\n\n/*******************  Bit definition for TIM_CCER register  *******************/\n#define TIM_CCER_CC1E_Pos         (0U)\n#define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */\n#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */\n#define TIM_CCER_CC1P_Pos         (1U)\n#define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */\n#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */\n#define TIM_CCER_CC1NE_Pos        (2U)\n#define TIM_CCER_CC1NE_Msk        (0x1U << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */\n#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */\n#define TIM_CCER_CC1NP_Pos        (3U)\n#define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */\n#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */\n#define TIM_CCER_CC2E_Pos         (4U)\n#define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */\n#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */\n#define TIM_CCER_CC2P_Pos         (5U)\n#define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */\n#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */\n#define TIM_CCER_CC2NE_Pos        (6U)\n#define TIM_CCER_CC2NE_Msk        (0x1U << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */\n#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */\n#define TIM_CCER_CC2NP_Pos        (7U)\n#define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */\n#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */\n#define TIM_CCER_CC3E_Pos         (8U)\n#define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */\n#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */\n#define TIM_CCER_CC3P_Pos         (9U)\n#define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */\n#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */\n#define TIM_CCER_CC3NE_Pos        (10U)\n#define TIM_CCER_CC3NE_Msk        (0x1U << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */\n#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */\n#define TIM_CCER_CC3NP_Pos        (11U)\n#define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */\n#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */\n#define TIM_CCER_CC4E_Pos         (12U)\n#define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */\n#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */\n#define TIM_CCER_CC4P_Pos         (13U)\n#define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */\n#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */\n#define TIM_CCER_CC4NP_Pos        (15U)\n#define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */\n#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */\n\n/*******************  Bit definition for TIM_CNT register  ********************/\n#define TIM_CNT_CNT_Pos           (0U)\n#define TIM_CNT_CNT_Msk           (0xFFFFFFFFU << TIM_CNT_CNT_Pos)                 /*!< 0xFFFFFFFF */\n#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                                  /*!<Counter Value            */\n\n/*******************  Bit definition for TIM_PSC register  ********************/\n#define TIM_PSC_PSC_Pos           (0U)\n#define TIM_PSC_PSC_Msk           (0xFFFFU << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */\n#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */\n\n/*******************  Bit definition for TIM_ARR register  ********************/\n#define TIM_ARR_ARR_Pos           (0U)\n#define TIM_ARR_ARR_Msk           (0xFFFFFFFFU << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */\n#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */\n\n/*******************  Bit definition for TIM_RCR register  ********************/\n#define TIM_RCR_REP_Pos           (0U)\n#define TIM_RCR_REP_Msk           (0xFFU << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */\n#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */\n\n/*******************  Bit definition for TIM_CCR1 register  *******************/\n#define TIM_CCR1_CCR1_Pos         (0U)\n#define TIM_CCR1_CCR1_Msk         (0xFFFFU << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */\n\n/*******************  Bit definition for TIM_CCR2 register  *******************/\n#define TIM_CCR2_CCR2_Pos         (0U)\n#define TIM_CCR2_CCR2_Msk         (0xFFFFU << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */\n\n/*******************  Bit definition for TIM_CCR3 register  *******************/\n#define TIM_CCR3_CCR3_Pos         (0U)\n#define TIM_CCR3_CCR3_Msk         (0xFFFFU << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */\n\n/*******************  Bit definition for TIM_CCR4 register  *******************/\n#define TIM_CCR4_CCR4_Pos         (0U)\n#define TIM_CCR4_CCR4_Msk         (0xFFFFU << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */\n\n/*******************  Bit definition for TIM_BDTR register  *******************/\n#define TIM_BDTR_DTG_Pos          (0U)\n#define TIM_BDTR_DTG_Msk          (0xFFU << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */\n#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\n#define TIM_BDTR_DTG_0            (0x01U << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */\n#define TIM_BDTR_DTG_1            (0x02U << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */\n#define TIM_BDTR_DTG_2            (0x04U << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */\n#define TIM_BDTR_DTG_3            (0x08U << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */\n#define TIM_BDTR_DTG_4            (0x10U << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */\n#define TIM_BDTR_DTG_5            (0x20U << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */\n#define TIM_BDTR_DTG_6            (0x40U << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */\n#define TIM_BDTR_DTG_7            (0x80U << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */\n\n#define TIM_BDTR_LOCK_Pos         (8U)\n#define TIM_BDTR_LOCK_Msk         (0x3U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */\n#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */\n#define TIM_BDTR_LOCK_0           (0x1U << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */\n#define TIM_BDTR_LOCK_1           (0x2U << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */\n\n#define TIM_BDTR_OSSI_Pos         (10U)\n#define TIM_BDTR_OSSI_Msk         (0x1U << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */\n#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */\n#define TIM_BDTR_OSSR_Pos         (11U)\n#define TIM_BDTR_OSSR_Msk         (0x1U << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */\n#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */\n#define TIM_BDTR_BKE_Pos          (12U)\n#define TIM_BDTR_BKE_Msk          (0x1U << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */\n#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */\n#define TIM_BDTR_BKP_Pos          (13U)\n#define TIM_BDTR_BKP_Msk          (0x1U << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */\n#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */\n#define TIM_BDTR_AOE_Pos          (14U)\n#define TIM_BDTR_AOE_Msk          (0x1U << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */\n#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */\n#define TIM_BDTR_MOE_Pos          (15U)\n#define TIM_BDTR_MOE_Msk          (0x1U << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */\n#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */\n\n/*******************  Bit definition for TIM_DCR register  ********************/\n#define TIM_DCR_DBA_Pos           (0U)\n#define TIM_DCR_DBA_Msk           (0x1FU << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */\n#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */\n#define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */\n#define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */\n#define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */\n#define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */\n#define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */\n\n#define TIM_DCR_DBL_Pos           (8U)\n#define TIM_DCR_DBL_Msk           (0x1FU << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */\n#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */\n#define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */\n#define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */\n#define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */\n#define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */\n#define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */\n\n/*******************  Bit definition for TIM_DMAR register  *******************/\n#define TIM_DMAR_DMAB_Pos         (0U)\n#define TIM_DMAR_DMAB_Msk         (0xFFFFU << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */\n#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */\n\n/*******************  Bit definition for TIM_OR register  *********************/\n#define TIM_OR_TI1_RMP_Pos        (0U)\n#define TIM_OR_TI1_RMP_Msk        (0x3U << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000003 */\n#define TIM_OR_TI1_RMP            TIM_OR_TI1_RMP_Msk                           /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */\n#define TIM_OR_TI1_RMP_0          (0x1U << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000001 */\n#define TIM_OR_TI1_RMP_1          (0x2U << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000002 */\n\n#define TIM_OR_TI4_RMP_Pos        (6U)\n#define TIM_OR_TI4_RMP_Msk        (0x3U << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */\n#define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */\n#define TIM_OR_TI4_RMP_0          (0x1U << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */\n#define TIM_OR_TI4_RMP_1          (0x2U << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */\n#define TIM_OR_ITR1_RMP_Pos       (10U)\n#define TIM_OR_ITR1_RMP_Msk       (0x3U << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */\n#define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\n#define TIM_OR_ITR1_RMP_0         (0x1U << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */\n#define TIM_OR_ITR1_RMP_1         (0x2U << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*         Universal Synchronous Asynchronous Receiver Transmitter            */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for USART_SR register  *******************/\n#define USART_SR_PE_Pos               (0U)\n#define USART_SR_PE_Msk               (0x1U << USART_SR_PE_Pos)                /*!< 0x00000001 */\n#define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */\n#define USART_SR_FE_Pos               (1U)\n#define USART_SR_FE_Msk               (0x1U << USART_SR_FE_Pos)                /*!< 0x00000002 */\n#define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */\n#define USART_SR_NE_Pos               (2U)\n#define USART_SR_NE_Msk               (0x1U << USART_SR_NE_Pos)                /*!< 0x00000004 */\n#define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */\n#define USART_SR_ORE_Pos              (3U)\n#define USART_SR_ORE_Msk              (0x1U << USART_SR_ORE_Pos)               /*!< 0x00000008 */\n#define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */\n#define USART_SR_IDLE_Pos             (4U)\n#define USART_SR_IDLE_Msk             (0x1U << USART_SR_IDLE_Pos)              /*!< 0x00000010 */\n#define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */\n#define USART_SR_RXNE_Pos             (5U)\n#define USART_SR_RXNE_Msk             (0x1U << USART_SR_RXNE_Pos)              /*!< 0x00000020 */\n#define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */\n#define USART_SR_TC_Pos               (6U)\n#define USART_SR_TC_Msk               (0x1U << USART_SR_TC_Pos)                /*!< 0x00000040 */\n#define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */\n#define USART_SR_TXE_Pos              (7U)\n#define USART_SR_TXE_Msk              (0x1U << USART_SR_TXE_Pos)               /*!< 0x00000080 */\n#define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */\n#define USART_SR_LBD_Pos              (8U)\n#define USART_SR_LBD_Msk              (0x1U << USART_SR_LBD_Pos)               /*!< 0x00000100 */\n#define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */\n#define USART_SR_CTS_Pos              (9U)\n#define USART_SR_CTS_Msk              (0x1U << USART_SR_CTS_Pos)               /*!< 0x00000200 */\n#define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */\n\n/*******************  Bit definition for USART_DR register  *******************/\n#define USART_DR_DR_Pos               (0U)\n#define USART_DR_DR_Msk               (0x1FFU << USART_DR_DR_Pos)              /*!< 0x000001FF */\n#define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */\n\n/******************  Bit definition for USART_BRR register  *******************/\n#define USART_BRR_DIV_Fraction_Pos    (0U)\n#define USART_BRR_DIV_Fraction_Msk    (0xFU << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */\n#define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */\n#define USART_BRR_DIV_Mantissa_Pos    (4U)\n#define USART_BRR_DIV_Mantissa_Msk    (0xFFFU << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */\n#define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */\n\n/******************  Bit definition for USART_CR1 register  *******************/\n#define USART_CR1_SBK_Pos             (0U)\n#define USART_CR1_SBK_Msk             (0x1U << USART_CR1_SBK_Pos)              /*!< 0x00000001 */\n#define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */\n#define USART_CR1_RWU_Pos             (1U)\n#define USART_CR1_RWU_Msk             (0x1U << USART_CR1_RWU_Pos)              /*!< 0x00000002 */\n#define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */\n#define USART_CR1_RE_Pos              (2U)\n#define USART_CR1_RE_Msk              (0x1U << USART_CR1_RE_Pos)               /*!< 0x00000004 */\n#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */\n#define USART_CR1_TE_Pos              (3U)\n#define USART_CR1_TE_Msk              (0x1U << USART_CR1_TE_Pos)               /*!< 0x00000008 */\n#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */\n#define USART_CR1_IDLEIE_Pos          (4U)\n#define USART_CR1_IDLEIE_Msk          (0x1U << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */\n#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */\n#define USART_CR1_RXNEIE_Pos          (5U)\n#define USART_CR1_RXNEIE_Msk          (0x1U << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */\n#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */\n#define USART_CR1_TCIE_Pos            (6U)\n#define USART_CR1_TCIE_Msk            (0x1U << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */\n#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */\n#define USART_CR1_TXEIE_Pos           (7U)\n#define USART_CR1_TXEIE_Msk           (0x1U << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */\n#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<PE Interrupt Enable                    */\n#define USART_CR1_PEIE_Pos            (8U)\n#define USART_CR1_PEIE_Msk            (0x1U << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */\n#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */\n#define USART_CR1_PS_Pos              (9U)\n#define USART_CR1_PS_Msk              (0x1U << USART_CR1_PS_Pos)               /*!< 0x00000200 */\n#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */\n#define USART_CR1_PCE_Pos             (10U)\n#define USART_CR1_PCE_Msk             (0x1U << USART_CR1_PCE_Pos)              /*!< 0x00000400 */\n#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */\n#define USART_CR1_WAKE_Pos            (11U)\n#define USART_CR1_WAKE_Msk            (0x1U << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */\n#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */\n#define USART_CR1_M_Pos               (12U)\n#define USART_CR1_M_Msk               (0x1U << USART_CR1_M_Pos)                /*!< 0x00001000 */\n#define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */\n#define USART_CR1_UE_Pos              (13U)\n#define USART_CR1_UE_Msk              (0x1U << USART_CR1_UE_Pos)               /*!< 0x00002000 */\n#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */\n#define USART_CR1_OVER8_Pos           (15U)\n#define USART_CR1_OVER8_Msk           (0x1U << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */\n#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */\n\n/******************  Bit definition for USART_CR2 register  *******************/\n#define USART_CR2_ADD_Pos             (0U)\n#define USART_CR2_ADD_Msk             (0xFU << USART_CR2_ADD_Pos)              /*!< 0x0000000F */\n#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */\n#define USART_CR2_LBDL_Pos            (5U)\n#define USART_CR2_LBDL_Msk            (0x1U << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */\n#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */\n#define USART_CR2_LBDIE_Pos           (6U)\n#define USART_CR2_LBDIE_Msk           (0x1U << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */\n#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */\n#define USART_CR2_LBCL_Pos            (8U)\n#define USART_CR2_LBCL_Msk            (0x1U << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */\n#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */\n#define USART_CR2_CPHA_Pos            (9U)\n#define USART_CR2_CPHA_Msk            (0x1U << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */\n#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */\n#define USART_CR2_CPOL_Pos            (10U)\n#define USART_CR2_CPOL_Msk            (0x1U << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */\n#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */\n#define USART_CR2_CLKEN_Pos           (11U)\n#define USART_CR2_CLKEN_Msk           (0x1U << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */\n#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */\n\n#define USART_CR2_STOP_Pos            (12U)\n#define USART_CR2_STOP_Msk            (0x3U << USART_CR2_STOP_Pos)             /*!< 0x00003000 */\n#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */\n#define USART_CR2_STOP_0              (0x1U << USART_CR2_STOP_Pos)             /*!< 0x1000 */\n#define USART_CR2_STOP_1              (0x2U << USART_CR2_STOP_Pos)             /*!< 0x2000 */\n\n#define USART_CR2_LINEN_Pos           (14U)\n#define USART_CR2_LINEN_Msk           (0x1U << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */\n#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */\n\n/******************  Bit definition for USART_CR3 register  *******************/\n#define USART_CR3_EIE_Pos             (0U)\n#define USART_CR3_EIE_Msk             (0x1U << USART_CR3_EIE_Pos)              /*!< 0x00000001 */\n#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */\n#define USART_CR3_IREN_Pos            (1U)\n#define USART_CR3_IREN_Msk            (0x1U << USART_CR3_IREN_Pos)             /*!< 0x00000002 */\n#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */\n#define USART_CR3_IRLP_Pos            (2U)\n#define USART_CR3_IRLP_Msk            (0x1U << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */\n#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */\n#define USART_CR3_HDSEL_Pos           (3U)\n#define USART_CR3_HDSEL_Msk           (0x1U << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */\n#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */\n#define USART_CR3_NACK_Pos            (4U)\n#define USART_CR3_NACK_Msk            (0x1U << USART_CR3_NACK_Pos)             /*!< 0x00000010 */\n#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */\n#define USART_CR3_SCEN_Pos            (5U)\n#define USART_CR3_SCEN_Msk            (0x1U << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */\n#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */\n#define USART_CR3_DMAR_Pos            (6U)\n#define USART_CR3_DMAR_Msk            (0x1U << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */\n#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */\n#define USART_CR3_DMAT_Pos            (7U)\n#define USART_CR3_DMAT_Msk            (0x1U << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */\n#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */\n#define USART_CR3_RTSE_Pos            (8U)\n#define USART_CR3_RTSE_Msk            (0x1U << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */\n#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */\n#define USART_CR3_CTSE_Pos            (9U)\n#define USART_CR3_CTSE_Msk            (0x1U << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */\n#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */\n#define USART_CR3_CTSIE_Pos           (10U)\n#define USART_CR3_CTSIE_Msk           (0x1U << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */\n#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */\n#define USART_CR3_ONEBIT_Pos          (11U)\n#define USART_CR3_ONEBIT_Msk          (0x1U << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */\n#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */\n\n/******************  Bit definition for USART_GTPR register  ******************/\n#define USART_GTPR_PSC_Pos            (0U)\n#define USART_GTPR_PSC_Msk            (0xFFU << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */\n#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */\n#define USART_GTPR_PSC_0              (0x01U << USART_GTPR_PSC_Pos)            /*!< 0x0001 */\n#define USART_GTPR_PSC_1              (0x02U << USART_GTPR_PSC_Pos)            /*!< 0x0002 */\n#define USART_GTPR_PSC_2              (0x04U << USART_GTPR_PSC_Pos)            /*!< 0x0004 */\n#define USART_GTPR_PSC_3              (0x08U << USART_GTPR_PSC_Pos)            /*!< 0x0008 */\n#define USART_GTPR_PSC_4              (0x10U << USART_GTPR_PSC_Pos)            /*!< 0x0010 */\n#define USART_GTPR_PSC_5              (0x20U << USART_GTPR_PSC_Pos)            /*!< 0x0020 */\n#define USART_GTPR_PSC_6              (0x40U << USART_GTPR_PSC_Pos)            /*!< 0x0040 */\n#define USART_GTPR_PSC_7              (0x80U << USART_GTPR_PSC_Pos)            /*!< 0x0080 */\n\n#define USART_GTPR_GT_Pos             (8U)\n#define USART_GTPR_GT_Msk             (0xFFU << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */\n#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            Window WATCHDOG                                 */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for WWDG_CR register  ********************/\n#define WWDG_CR_T_Pos           (0U)\n#define WWDG_CR_T_Msk           (0x7FU << WWDG_CR_T_Pos)                       /*!< 0x0000007F */\n#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\n#define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x01 */\n#define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x02 */\n#define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x04 */\n#define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x08 */\n#define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x10 */\n#define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x20 */\n#define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x40 */\n/* Legacy defines */\n#define  WWDG_CR_T0                          WWDG_CR_T_0\n#define  WWDG_CR_T1                          WWDG_CR_T_1\n#define  WWDG_CR_T2                          WWDG_CR_T_2\n#define  WWDG_CR_T3                          WWDG_CR_T_3\n#define  WWDG_CR_T4                          WWDG_CR_T_4\n#define  WWDG_CR_T5                          WWDG_CR_T_5\n#define  WWDG_CR_T6                          WWDG_CR_T_6\n\n#define WWDG_CR_WDGA_Pos        (7U)\n#define WWDG_CR_WDGA_Msk        (0x1U << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */\n#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */\n\n/*******************  Bit definition for WWDG_CFR register  *******************/\n#define WWDG_CFR_W_Pos          (0U)\n#define WWDG_CFR_W_Msk          (0x7FU << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */\n#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */\n#define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x0001 */\n#define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x0002 */\n#define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x0004 */\n#define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x0008 */\n#define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x0010 */\n#define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x0020 */\n#define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x0040 */\n/* Legacy defines */\n#define  WWDG_CFR_W0                         WWDG_CFR_W_0\n#define  WWDG_CFR_W1                         WWDG_CFR_W_1\n#define  WWDG_CFR_W2                         WWDG_CFR_W_2\n#define  WWDG_CFR_W3                         WWDG_CFR_W_3\n#define  WWDG_CFR_W4                         WWDG_CFR_W_4\n#define  WWDG_CFR_W5                         WWDG_CFR_W_5\n#define  WWDG_CFR_W6                         WWDG_CFR_W_6\n\n#define WWDG_CFR_WDGTB_Pos      (7U)\n#define WWDG_CFR_WDGTB_Msk      (0x3U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */\n#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */\n#define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */\n#define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */\n/* Legacy defines */\n#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0\n#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1\n\n#define WWDG_CFR_EWI_Pos        (9U)\n#define WWDG_CFR_EWI_Msk        (0x1U << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */\n#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */\n\n/*******************  Bit definition for WWDG_SR register  ********************/\n#define WWDG_SR_EWIF_Pos        (0U)\n#define WWDG_SR_EWIF_Msk        (0x1U << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */\n#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                DBG                                         */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for DBGMCU_IDCODE register  *************/\n#define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)\n#define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\n#define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk\n#define DBGMCU_IDCODE_REV_ID_Pos                     (16U)\n#define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\n#define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk\n\n/********************  Bit definition for DBGMCU_CR register  *****************/\n#define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)\n#define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */\n#define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk\n#define DBGMCU_CR_DBG_STOP_Pos                       (1U)\n#define DBGMCU_CR_DBG_STOP_Msk                       (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk\n#define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)\n#define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */\n#define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk\n#define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)\n#define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */\n#define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk\n\n#define DBGMCU_CR_TRACE_MODE_Pos                     (6U)\n#define DBGMCU_CR_TRACE_MODE_Msk                     (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */\n#define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk\n#define DBGMCU_CR_TRACE_MODE_0                       (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */\n#define DBGMCU_CR_TRACE_MODE_1                       (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */\n\n/********************  Bit definition for DBGMCU_APB1_FZ register  ************/\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos    (24U)\n#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */\n#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk\n/* Old IWDGSTOP bit definition, maintained for legacy purpose */\n#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP\n\n/********************  Bit definition for DBGMCU_APB2_FZ register  ************/\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                Ethernet MAC Registers bits definitions                     */\n/*                                                                            */\n/******************************************************************************/\n/* Bit definition for Ethernet MAC Control Register register */\n#define ETH_MACCR_WD_Pos                              (23U)\n#define ETH_MACCR_WD_Msk                              (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */\n#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */\n#define ETH_MACCR_JD_Pos                              (22U)\n#define ETH_MACCR_JD_Msk                              (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */\n#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */\n#define ETH_MACCR_IFG_Pos                             (17U)\n#define ETH_MACCR_IFG_Msk                             (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */\n#define ETH_MACCR_IFG                                 ETH_MACCR_IFG_Msk        /* Inter-frame gap */\n#define ETH_MACCR_IFG_96Bit                           0x00000000U              /* Minimum IFG between frames during transmission is 96Bit */\n#define ETH_MACCR_IFG_88Bit                           0x00020000U              /* Minimum IFG between frames during transmission is 88Bit */\n#define ETH_MACCR_IFG_80Bit                           0x00040000U              /* Minimum IFG between frames during transmission is 80Bit */\n#define ETH_MACCR_IFG_72Bit                           0x00060000U              /* Minimum IFG between frames during transmission is 72Bit */\n#define ETH_MACCR_IFG_64Bit                           0x00080000U              /* Minimum IFG between frames during transmission is 64Bit */\n#define ETH_MACCR_IFG_56Bit                           0x000A0000U              /* Minimum IFG between frames during transmission is 56Bit */\n#define ETH_MACCR_IFG_48Bit                           0x000C0000U              /* Minimum IFG between frames during transmission is 48Bit */\n#define ETH_MACCR_IFG_40Bit                           0x000E0000U              /* Minimum IFG between frames during transmission is 40Bit */\n#define ETH_MACCR_CSD_Pos                             (16U)\n#define ETH_MACCR_CSD_Msk                             (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */\n#define ETH_MACCR_CSD                                 ETH_MACCR_CSD_Msk        /* Carrier sense disable (during transmission) */\n#define ETH_MACCR_FES_Pos                             (14U)\n#define ETH_MACCR_FES_Msk                             (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */\n#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */\n#define ETH_MACCR_ROD_Pos                             (13U)\n#define ETH_MACCR_ROD_Msk                             (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */\n#define ETH_MACCR_ROD                                 ETH_MACCR_ROD_Msk        /* Receive own disable */\n#define ETH_MACCR_LM_Pos                              (12U)\n#define ETH_MACCR_LM_Msk                              (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */\n#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */\n#define ETH_MACCR_DM_Pos                              (11U)\n#define ETH_MACCR_DM_Msk                              (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */\n#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */\n#define ETH_MACCR_IPCO_Pos                            (10U)\n#define ETH_MACCR_IPCO_Msk                            (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */\n#define ETH_MACCR_IPCO                                ETH_MACCR_IPCO_Msk       /* IP Checksum offload */\n#define ETH_MACCR_RD_Pos                              (9U)\n#define ETH_MACCR_RD_Msk                              (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */\n#define ETH_MACCR_RD                                  ETH_MACCR_RD_Msk         /* Retry disable */\n#define ETH_MACCR_APCS_Pos                            (7U)\n#define ETH_MACCR_APCS_Msk                            (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */\n#define ETH_MACCR_APCS                                ETH_MACCR_APCS_Msk       /* Automatic Pad/CRC stripping */\n#define ETH_MACCR_BL_Pos                              (5U)\n#define ETH_MACCR_BL_Msk                              (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */\n#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit: random integer number (r) of slot time delays before rescheduling\n                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */\n#define ETH_MACCR_BL_10                               0x00000000U              /* k = min (n, 10) */\n#define ETH_MACCR_BL_8                                0x00000020U              /* k = min (n, 8) */\n#define ETH_MACCR_BL_4                                0x00000040U              /* k = min (n, 4) */\n#define ETH_MACCR_BL_1                                0x00000060U              /* k = min (n, 1) */\n#define ETH_MACCR_DC_Pos                              (4U)\n#define ETH_MACCR_DC_Msk                              (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */\n#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */\n#define ETH_MACCR_TE_Pos                              (3U)\n#define ETH_MACCR_TE_Msk                              (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */\n#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */\n#define ETH_MACCR_RE_Pos                              (2U)\n#define ETH_MACCR_RE_Msk                              (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */\n#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */\n\n/* Bit definition for Ethernet MAC Frame Filter Register */\n#define ETH_MACFFR_RA_Pos                             (31U)\n#define ETH_MACFFR_RA_Msk                             (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */\n#define ETH_MACFFR_RA                                 ETH_MACFFR_RA_Msk        /* Receive all */\n#define ETH_MACFFR_HPF_Pos                            (10U)\n#define ETH_MACFFR_HPF_Msk                            (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */\n#define ETH_MACFFR_HPF                                ETH_MACFFR_HPF_Msk       /* Hash or perfect filter */\n#define ETH_MACFFR_SAF_Pos                            (9U)\n#define ETH_MACFFR_SAF_Msk                            (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */\n#define ETH_MACFFR_SAF                                ETH_MACFFR_SAF_Msk       /* Source address filter enable */\n#define ETH_MACFFR_SAIF_Pos                           (8U)\n#define ETH_MACFFR_SAIF_Msk                           (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */\n#define ETH_MACFFR_SAIF                               ETH_MACFFR_SAIF_Msk      /* SA inverse filtering */\n#define ETH_MACFFR_PCF_Pos                            (6U)\n#define ETH_MACFFR_PCF_Msk                            (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */\n#define ETH_MACFFR_PCF                                ETH_MACFFR_PCF_Msk       /* Pass control frames: 3 cases */\n#define ETH_MACFFR_PCF_BlockAll_Pos                   (6U)\n#define ETH_MACFFR_PCF_BlockAll_Msk                   (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */\n#define ETH_MACFFR_PCF_BlockAll                       ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */\n#define ETH_MACFFR_PCF_ForwardAll_Pos                 (7U)\n#define ETH_MACFFR_PCF_ForwardAll_Msk                 (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */\n#define ETH_MACFFR_PCF_ForwardAll                     ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */\n#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos    (6U)\n#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk    (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */\n#define ETH_MACFFR_PCF_ForwardPassedAddrFilter        ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */\n#define ETH_MACFFR_BFD_Pos                            (5U)\n#define ETH_MACFFR_BFD_Msk                            (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */\n#define ETH_MACFFR_BFD                                ETH_MACFFR_BFD_Msk       /* Broadcast frame disable */\n#define ETH_MACFFR_PAM_Pos                            (4U)\n#define ETH_MACFFR_PAM_Msk                            (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */\n#define ETH_MACFFR_PAM                                ETH_MACFFR_PAM_Msk       /* Pass all mutlicast */\n#define ETH_MACFFR_DAIF_Pos                           (3U)\n#define ETH_MACFFR_DAIF_Msk                           (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */\n#define ETH_MACFFR_DAIF                               ETH_MACFFR_DAIF_Msk      /* DA Inverse filtering */\n#define ETH_MACFFR_HM_Pos                             (2U)\n#define ETH_MACFFR_HM_Msk                             (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */\n#define ETH_MACFFR_HM                                 ETH_MACFFR_HM_Msk        /* Hash multicast */\n#define ETH_MACFFR_HU_Pos                             (1U)\n#define ETH_MACFFR_HU_Msk                             (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */\n#define ETH_MACFFR_HU                                 ETH_MACFFR_HU_Msk        /* Hash unicast */\n#define ETH_MACFFR_PM_Pos                             (0U)\n#define ETH_MACFFR_PM_Msk                             (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */\n#define ETH_MACFFR_PM                                 ETH_MACFFR_PM_Msk        /* Promiscuous mode */\n\n/* Bit definition for Ethernet MAC Hash Table High Register */\n#define ETH_MACHTHR_HTH_Pos                           (0U)\n#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */\n\n/* Bit definition for Ethernet MAC Hash Table Low Register */\n#define ETH_MACHTLR_HTL_Pos                           (0U)\n#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */\n\n/* Bit definition for Ethernet MAC MII Address Register */\n#define ETH_MACMIIAR_PA_Pos                           (11U)\n#define ETH_MACMIIAR_PA_Msk                           (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */\n#define ETH_MACMIIAR_PA                               ETH_MACMIIAR_PA_Msk      /* Physical layer address */\n#define ETH_MACMIIAR_MR_Pos                           (6U)\n#define ETH_MACMIIAR_MR_Msk                           (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */\n#define ETH_MACMIIAR_MR                               ETH_MACMIIAR_MR_Msk      /* MII register in the selected PHY */\n#define ETH_MACMIIAR_CR_Pos                           (2U)\n#define ETH_MACMIIAR_CR_Msk                           (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */\n#define ETH_MACMIIAR_CR                               ETH_MACMIIAR_CR_Msk      /* CR clock range: 6 cases */\n#define ETH_MACMIIAR_CR_Div42                         0x00000000U              /* HCLK:60-100 MHz; MDC clock= HCLK/42   */\n#define ETH_MACMIIAR_CR_Div62_Pos                     (2U)\n#define ETH_MACMIIAR_CR_Div62_Msk                     (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */\n#define ETH_MACMIIAR_CR_Div62                         ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62  */\n#define ETH_MACMIIAR_CR_Div16_Pos                     (3U)\n#define ETH_MACMIIAR_CR_Div16_Msk                     (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */\n#define ETH_MACMIIAR_CR_Div16                         ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16    */\n#define ETH_MACMIIAR_CR_Div26_Pos                     (2U)\n#define ETH_MACMIIAR_CR_Div26_Msk                     (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */\n#define ETH_MACMIIAR_CR_Div26                         ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26    */\n#define ETH_MACMIIAR_CR_Div102_Pos                    (4U)\n#define ETH_MACMIIAR_CR_Div102_Msk                    (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */\n#define ETH_MACMIIAR_CR_Div102                        ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */\n#define ETH_MACMIIAR_MW_Pos                           (1U)\n#define ETH_MACMIIAR_MW_Msk                           (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */\n#define ETH_MACMIIAR_MW                               ETH_MACMIIAR_MW_Msk      /* MII write */\n#define ETH_MACMIIAR_MB_Pos                           (0U)\n#define ETH_MACMIIAR_MB_Msk                           (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */\n#define ETH_MACMIIAR_MB                               ETH_MACMIIAR_MB_Msk      /* MII busy  */\n\n/* Bit definition for Ethernet MAC MII Data Register */\n#define ETH_MACMIIDR_MD_Pos                           (0U)\n#define ETH_MACMIIDR_MD_Msk                           (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */\n#define ETH_MACMIIDR_MD                               ETH_MACMIIDR_MD_Msk      /* MII data: read/write data from/to PHY */\n\n/* Bit definition for Ethernet MAC Flow Control Register */\n#define ETH_MACFCR_PT_Pos                             (16U)\n#define ETH_MACFCR_PT_Msk                             (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */\n#define ETH_MACFCR_PT                                 ETH_MACFCR_PT_Msk        /* Pause time */\n#define ETH_MACFCR_ZQPD_Pos                           (7U)\n#define ETH_MACFCR_ZQPD_Msk                           (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */\n#define ETH_MACFCR_ZQPD                               ETH_MACFCR_ZQPD_Msk      /* Zero-quanta pause disable */\n#define ETH_MACFCR_PLT_Pos                            (4U)\n#define ETH_MACFCR_PLT_Msk                            (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */\n#define ETH_MACFCR_PLT                                ETH_MACFCR_PLT_Msk       /* Pause low threshold: 4 cases */\n#define ETH_MACFCR_PLT_Minus4                         0x00000000U              /* Pause time minus 4 slot times   */\n#define ETH_MACFCR_PLT_Minus28_Pos                    (4U)\n#define ETH_MACFCR_PLT_Minus28_Msk                    (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */\n#define ETH_MACFCR_PLT_Minus28                        ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times  */\n#define ETH_MACFCR_PLT_Minus144_Pos                   (5U)\n#define ETH_MACFCR_PLT_Minus144_Msk                   (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */\n#define ETH_MACFCR_PLT_Minus144                       ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */\n#define ETH_MACFCR_PLT_Minus256_Pos                   (4U)\n#define ETH_MACFCR_PLT_Minus256_Msk                   (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */\n#define ETH_MACFCR_PLT_Minus256                       ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */\n#define ETH_MACFCR_UPFD_Pos                           (3U)\n#define ETH_MACFCR_UPFD_Msk                           (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */\n#define ETH_MACFCR_UPFD                               ETH_MACFCR_UPFD_Msk      /* Unicast pause frame detect */\n#define ETH_MACFCR_RFCE_Pos                           (2U)\n#define ETH_MACFCR_RFCE_Msk                           (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */\n#define ETH_MACFCR_RFCE                               ETH_MACFCR_RFCE_Msk      /* Receive flow control enable */\n#define ETH_MACFCR_TFCE_Pos                           (1U)\n#define ETH_MACFCR_TFCE_Msk                           (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */\n#define ETH_MACFCR_TFCE                               ETH_MACFCR_TFCE_Msk      /* Transmit flow control enable */\n#define ETH_MACFCR_FCBBPA_Pos                         (0U)\n#define ETH_MACFCR_FCBBPA_Msk                         (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */\n#define ETH_MACFCR_FCBBPA                             ETH_MACFCR_FCBBPA_Msk    /* Flow control busy/backpressure activate */\n\n/* Bit definition for Ethernet MAC VLAN Tag Register */\n#define ETH_MACVLANTR_VLANTC_Pos                      (16U)\n#define ETH_MACVLANTR_VLANTC_Msk                      (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */\n#define ETH_MACVLANTR_VLANTC                          ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */\n#define ETH_MACVLANTR_VLANTI_Pos                      (0U)\n#define ETH_MACVLANTR_VLANTI_Msk                      (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */\n#define ETH_MACVLANTR_VLANTI                          ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */\n\n/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */\n#define ETH_MACRWUFFR_D_Pos                           (0U)\n#define ETH_MACRWUFFR_D_Msk                           (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACRWUFFR_D                               ETH_MACRWUFFR_D_Msk      /* Wake-up frame filter register data */\n/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.\n   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */\n/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask\n   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask\n   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask\n   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask\n   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -\n                              RSVD - Filter1 Command - RSVD - Filter0 Command\n   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset\n   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16\n   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */\n\n/* Bit definition for Ethernet MAC PMT Control and Status Register */\n#define ETH_MACPMTCSR_WFFRPR_Pos                      (31U)\n#define ETH_MACPMTCSR_WFFRPR_Msk                      (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */\n#define ETH_MACPMTCSR_WFFRPR                          ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */\n#define ETH_MACPMTCSR_GU_Pos                          (9U)\n#define ETH_MACPMTCSR_GU_Msk                          (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */\n#define ETH_MACPMTCSR_GU                              ETH_MACPMTCSR_GU_Msk     /* Global Unicast                              */\n#define ETH_MACPMTCSR_WFR_Pos                         (6U)\n#define ETH_MACPMTCSR_WFR_Msk                         (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */\n#define ETH_MACPMTCSR_WFR                             ETH_MACPMTCSR_WFR_Msk    /* Wake-Up Frame Received                      */\n#define ETH_MACPMTCSR_MPR_Pos                         (5U)\n#define ETH_MACPMTCSR_MPR_Msk                         (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */\n#define ETH_MACPMTCSR_MPR                             ETH_MACPMTCSR_MPR_Msk    /* Magic Packet Received                       */\n#define ETH_MACPMTCSR_WFE_Pos                         (2U)\n#define ETH_MACPMTCSR_WFE_Msk                         (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */\n#define ETH_MACPMTCSR_WFE                             ETH_MACPMTCSR_WFE_Msk    /* Wake-Up Frame Enable                        */\n#define ETH_MACPMTCSR_MPE_Pos                         (1U)\n#define ETH_MACPMTCSR_MPE_Msk                         (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */\n#define ETH_MACPMTCSR_MPE                             ETH_MACPMTCSR_MPE_Msk    /* Magic Packet Enable                         */\n#define ETH_MACPMTCSR_PD_Pos                          (0U)\n#define ETH_MACPMTCSR_PD_Msk                          (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */\n#define ETH_MACPMTCSR_PD                              ETH_MACPMTCSR_PD_Msk     /* Power Down                                  */\n\n/* Bit definition for Ethernet MAC debug Register */\n#define ETH_MACDBGR_TFF_Pos                           (25U)\n#define ETH_MACDBGR_TFF_Msk                           (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */\n#define ETH_MACDBGR_TFF                               ETH_MACDBGR_TFF_Msk      /* Tx FIFO full                                                            */\n#define ETH_MACDBGR_TFNE_Pos                          (24U)\n#define ETH_MACDBGR_TFNE_Msk                          (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */\n#define ETH_MACDBGR_TFNE                              ETH_MACDBGR_TFNE_Msk     /* Tx FIFO not empty                                                       */\n#define ETH_MACDBGR_TFWA_Pos                          (22U)\n#define ETH_MACDBGR_TFWA_Msk                          (0x1U << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */\n#define ETH_MACDBGR_TFWA                              ETH_MACDBGR_TFWA_Msk     /* Tx FIFO write active                                                    */\n#define ETH_MACDBGR_TFRS_Pos                          (20U)\n#define ETH_MACDBGR_TFRS_Msk                          (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */\n#define ETH_MACDBGR_TFRS                              ETH_MACDBGR_TFRS_Msk     /* Tx FIFO read status mask                                                */\n#define ETH_MACDBGR_TFRS_WRITING_Pos                  (20U)\n#define ETH_MACDBGR_TFRS_WRITING_Msk                  (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */\n#define ETH_MACDBGR_TFRS_WRITING                      ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO                    */\n#define ETH_MACDBGR_TFRS_WAITING_Pos                  (21U)\n#define ETH_MACDBGR_TFRS_WAITING_Msk                  (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */\n#define ETH_MACDBGR_TFRS_WAITING                      ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter                               */\n#define ETH_MACDBGR_TFRS_READ_Pos                     (20U)\n#define ETH_MACDBGR_TFRS_READ_Msk                     (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */\n#define ETH_MACDBGR_TFRS_READ                         ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter)                   */\n#define ETH_MACDBGR_TFRS_IDLE                         0x00000000U              /* Idle state                                                              */\n#define ETH_MACDBGR_MTP_Pos                           (19U)\n#define ETH_MACDBGR_MTP_Msk                           (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */\n#define ETH_MACDBGR_MTP                               ETH_MACDBGR_MTP_Msk      /* MAC transmitter in pause                                                */\n#define ETH_MACDBGR_MTFCS_Pos                         (17U)\n#define ETH_MACDBGR_MTFCS_Msk                         (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */\n#define ETH_MACDBGR_MTFCS                             ETH_MACDBGR_MTFCS_Msk    /* MAC transmit frame controller status mask                               */\n#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos            (17U)\n#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk            (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */\n#define ETH_MACDBGR_MTFCS_TRANSFERRING                ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission                               */\n#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos           (18U)\n#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk           (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */\n#define ETH_MACDBGR_MTFCS_GENERATINGPCF               ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */\n#define ETH_MACDBGR_MTFCS_WAITING_Pos                 (17U)\n#define ETH_MACDBGR_MTFCS_WAITING_Msk                 (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */\n#define ETH_MACDBGR_MTFCS_WAITING                     ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over   */\n#define ETH_MACDBGR_MTFCS_IDLE                        0x00000000U              /* Idle                                                                    */\n#define ETH_MACDBGR_MMTEA_Pos                         (16U)\n#define ETH_MACDBGR_MMTEA_Msk                         (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */\n#define ETH_MACDBGR_MMTEA                             ETH_MACDBGR_MMTEA_Msk    /* MAC MII transmit engine active                                          */\n#define ETH_MACDBGR_RFFL_Pos                          (8U)\n#define ETH_MACDBGR_RFFL_Msk                          (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */\n#define ETH_MACDBGR_RFFL                              ETH_MACDBGR_RFFL_Msk     /* Rx FIFO fill level mask                                                 */\n#define ETH_MACDBGR_RFFL_FULL_Pos                     (8U)\n#define ETH_MACDBGR_RFFL_FULL_Msk                     (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */\n#define ETH_MACDBGR_RFFL_FULL                         ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full                                                             */\n#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos                 (9U)\n#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk                 (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */\n#define ETH_MACDBGR_RFFL_ABOVEFCT                     ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold                 */\n#define ETH_MACDBGR_RFFL_BELOWFCT_Pos                 (8U)\n#define ETH_MACDBGR_RFFL_BELOWFCT_Msk                 (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */\n#define ETH_MACDBGR_RFFL_BELOWFCT                     ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold              */\n#define ETH_MACDBGR_RFFL_EMPTY                        0x00000000U              /* RxFIFO empty                                                            */\n#define ETH_MACDBGR_RFRCS_Pos                         (5U)\n#define ETH_MACDBGR_RFRCS_Msk                         (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */\n#define ETH_MACDBGR_RFRCS                             ETH_MACDBGR_RFRCS_Msk    /* Rx FIFO read controller status mask                                     */\n#define ETH_MACDBGR_RFRCS_FLUSHING_Pos                (5U)\n#define ETH_MACDBGR_RFRCS_FLUSHING_Msk                (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */\n#define ETH_MACDBGR_RFRCS_FLUSHING                    ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status                                      */\n#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos           (6U)\n#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk           (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */\n#define ETH_MACDBGR_RFRCS_STATUSREADING               ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp)                                    */\n#define ETH_MACDBGR_RFRCS_DATAREADING_Pos             (5U)\n#define ETH_MACDBGR_RFRCS_DATAREADING_Msk             (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */\n#define ETH_MACDBGR_RFRCS_DATAREADING                 ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data                                                      */\n#define ETH_MACDBGR_RFRCS_IDLE                        0x00000000U              /* IDLE state                                                              */\n#define ETH_MACDBGR_RFWRA_Pos                         (4U)\n#define ETH_MACDBGR_RFWRA_Msk                         (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */\n#define ETH_MACDBGR_RFWRA                             ETH_MACDBGR_RFWRA_Msk    /* Rx FIFO write controller active                                         */\n#define ETH_MACDBGR_MSFRWCS_Pos                       (1U)\n#define ETH_MACDBGR_MSFRWCS_Msk                       (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */\n#define ETH_MACDBGR_MSFRWCS                           ETH_MACDBGR_MSFRWCS_Msk  /* MAC small FIFO read / write controllers status  mask                    */\n#define ETH_MACDBGR_MSFRWCS_1                         (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */\n#define ETH_MACDBGR_MSFRWCS_0                         (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */\n#define ETH_MACDBGR_MMRPEA_Pos                        (0U)\n#define ETH_MACDBGR_MMRPEA_Msk                        (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */\n#define ETH_MACDBGR_MMRPEA                            ETH_MACDBGR_MMRPEA_Msk   /* MAC MII receive protocol engine active                                  */\n\n/* Bit definition for Ethernet MAC Status Register */\n#define ETH_MACSR_TSTS_Pos                            (9U)\n#define ETH_MACSR_TSTS_Msk                            (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */\n#define ETH_MACSR_TSTS                                ETH_MACSR_TSTS_Msk       /* Time stamp trigger status */\n#define ETH_MACSR_MMCTS_Pos                           (6U)\n#define ETH_MACSR_MMCTS_Msk                           (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */\n#define ETH_MACSR_MMCTS                               ETH_MACSR_MMCTS_Msk      /* MMC transmit status       */\n#define ETH_MACSR_MMMCRS_Pos                          (5U)\n#define ETH_MACSR_MMMCRS_Msk                          (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */\n#define ETH_MACSR_MMMCRS                              ETH_MACSR_MMMCRS_Msk     /* MMC receive status        */\n#define ETH_MACSR_MMCS_Pos                            (4U)\n#define ETH_MACSR_MMCS_Msk                            (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */\n#define ETH_MACSR_MMCS                                ETH_MACSR_MMCS_Msk       /* MMC status                */\n#define ETH_MACSR_PMTS_Pos                            (3U)\n#define ETH_MACSR_PMTS_Msk                            (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */\n#define ETH_MACSR_PMTS                                ETH_MACSR_PMTS_Msk       /* PMT status                */\n\n/* Bit definition for Ethernet MAC Interrupt Mask Register */\n#define ETH_MACIMR_TSTIM_Pos                          (9U)\n#define ETH_MACIMR_TSTIM_Msk                          (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */\n#define ETH_MACIMR_TSTIM                              ETH_MACIMR_TSTIM_Msk     /* Time stamp trigger interrupt mask */\n#define ETH_MACIMR_PMTIM_Pos                          (3U)\n#define ETH_MACIMR_PMTIM_Msk                          (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */\n#define ETH_MACIMR_PMTIM                              ETH_MACIMR_PMTIM_Msk     /* PMT interrupt mask                */\n\n/* Bit definition for Ethernet MAC Address0 High Register */\n#define ETH_MACA0HR_MACA0H_Pos                        (0U)\n#define ETH_MACA0HR_MACA0H_Msk                        (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */\n#define ETH_MACA0HR_MACA0H                            ETH_MACA0HR_MACA0H_Msk   /* MAC address0 high */\n\n/* Bit definition for Ethernet MAC Address0 Low Register */\n#define ETH_MACA0LR_MACA0L_Pos                        (0U)\n#define ETH_MACA0LR_MACA0L_Msk                        (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACA0LR_MACA0L                            ETH_MACA0LR_MACA0L_Msk   /* MAC address0 low */\n\n/* Bit definition for Ethernet MAC Address1 High Register */\n#define ETH_MACA1HR_AE_Pos                            (31U)\n#define ETH_MACA1HR_AE_Msk                            (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */\n#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk       /* Address enable */\n#define ETH_MACA1HR_SA_Pos                            (30U)\n#define ETH_MACA1HR_SA_Msk                            (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */\n#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk       /* Source address */\n#define ETH_MACA1HR_MBC_Pos                           (24U)\n#define ETH_MACA1HR_MBC_Msk                           (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */\n#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk      /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\n#define ETH_MACA1HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */\n#define ETH_MACA1HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */\n#define ETH_MACA1HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */\n#define ETH_MACA1HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */\n#define ETH_MACA1HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */\n#define ETH_MACA1HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [7:0]   */\n#define ETH_MACA1HR_MACA1H_Pos                        (0U)\n#define ETH_MACA1HR_MACA1H_Msk                        (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */\n#define ETH_MACA1HR_MACA1H                            ETH_MACA1HR_MACA1H_Msk   /* MAC address1 high */\n\n/* Bit definition for Ethernet MAC Address1 Low Register */\n#define ETH_MACA1LR_MACA1L_Pos                        (0U)\n#define ETH_MACA1LR_MACA1L_Msk                        (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACA1LR_MACA1L                            ETH_MACA1LR_MACA1L_Msk   /* MAC address1 low */\n\n/* Bit definition for Ethernet MAC Address2 High Register */\n#define ETH_MACA2HR_AE_Pos                            (31U)\n#define ETH_MACA2HR_AE_Msk                            (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */\n#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk       /* Address enable */\n#define ETH_MACA2HR_SA_Pos                            (30U)\n#define ETH_MACA2HR_SA_Msk                            (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */\n#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk       /* Source address */\n#define ETH_MACA2HR_MBC_Pos                           (24U)\n#define ETH_MACA2HR_MBC_Msk                           (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */\n#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk      /* Mask byte control */\n#define ETH_MACA2HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */\n#define ETH_MACA2HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */\n#define ETH_MACA2HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */\n#define ETH_MACA2HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */\n#define ETH_MACA2HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */\n#define ETH_MACA2HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70]    */\n#define ETH_MACA2HR_MACA2H_Pos                        (0U)\n#define ETH_MACA2HR_MACA2H_Msk                        (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */\n#define ETH_MACA2HR_MACA2H                            ETH_MACA2HR_MACA2H_Msk   /* MAC address1 high */\n\n/* Bit definition for Ethernet MAC Address2 Low Register */\n#define ETH_MACA2LR_MACA2L_Pos                        (0U)\n#define ETH_MACA2LR_MACA2L_Msk                        (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACA2LR_MACA2L                            ETH_MACA2LR_MACA2L_Msk   /* MAC address2 low */\n\n/* Bit definition for Ethernet MAC Address3 High Register */\n#define ETH_MACA3HR_AE_Pos                            (31U)\n#define ETH_MACA3HR_AE_Msk                            (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */\n#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk       /* Address enable */\n#define ETH_MACA3HR_SA_Pos                            (30U)\n#define ETH_MACA3HR_SA_Msk                            (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */\n#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk       /* Source address */\n#define ETH_MACA3HR_MBC_Pos                           (24U)\n#define ETH_MACA3HR_MBC_Msk                           (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */\n#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk      /* Mask byte control */\n#define ETH_MACA3HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */\n#define ETH_MACA3HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */\n#define ETH_MACA3HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */\n#define ETH_MACA3HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */\n#define ETH_MACA3HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */\n#define ETH_MACA3HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70]    */\n#define ETH_MACA3HR_MACA3H_Pos                        (0U)\n#define ETH_MACA3HR_MACA3H_Msk                        (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */\n#define ETH_MACA3HR_MACA3H                            ETH_MACA3HR_MACA3H_Msk   /* MAC address3 high */\n\n/* Bit definition for Ethernet MAC Address3 Low Register */\n#define ETH_MACA3LR_MACA3L_Pos                        (0U)\n#define ETH_MACA3LR_MACA3L_Msk                        (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACA3LR_MACA3L                            ETH_MACA3LR_MACA3L_Msk   /* MAC address3 low */\n\n/******************************************************************************/\n/*                Ethernet MMC Registers bits definition                      */\n/******************************************************************************/\n\n/* Bit definition for Ethernet MMC Contol Register */\n#define ETH_MMCCR_MCFHP_Pos                           (5U)\n#define ETH_MMCCR_MCFHP_Msk                           (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */\n#define ETH_MMCCR_MCFHP                               ETH_MMCCR_MCFHP_Msk      /* MMC counter Full-Half preset */\n#define ETH_MMCCR_MCP_Pos                             (4U)\n#define ETH_MMCCR_MCP_Msk                             (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */\n#define ETH_MMCCR_MCP                                 ETH_MMCCR_MCP_Msk        /* MMC counter preset           */\n#define ETH_MMCCR_MCF_Pos                             (3U)\n#define ETH_MMCCR_MCF_Msk                             (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */\n#define ETH_MMCCR_MCF                                 ETH_MMCCR_MCF_Msk        /* MMC Counter Freeze           */\n#define ETH_MMCCR_ROR_Pos                             (2U)\n#define ETH_MMCCR_ROR_Msk                             (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */\n#define ETH_MMCCR_ROR                                 ETH_MMCCR_ROR_Msk        /* Reset on Read                */\n#define ETH_MMCCR_CSR_Pos                             (1U)\n#define ETH_MMCCR_CSR_Msk                             (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */\n#define ETH_MMCCR_CSR                                 ETH_MMCCR_CSR_Msk        /* Counter Stop Rollover        */\n#define ETH_MMCCR_CR_Pos                              (0U)\n#define ETH_MMCCR_CR_Msk                              (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */\n#define ETH_MMCCR_CR                                  ETH_MMCCR_CR_Msk         /* Counters Reset               */\n\n/* Bit definition for Ethernet MMC Receive Interrupt Register */\n#define ETH_MMCRIR_RGUFS_Pos                          (17U)\n#define ETH_MMCRIR_RGUFS_Msk                          (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */\n#define ETH_MMCRIR_RGUFS                              ETH_MMCRIR_RGUFS_Msk     /* Set when Rx good unicast frames counter reaches half the maximum value */\n#define ETH_MMCRIR_RFAES_Pos                          (6U)\n#define ETH_MMCRIR_RFAES_Msk                          (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */\n#define ETH_MMCRIR_RFAES                              ETH_MMCRIR_RFAES_Msk     /* Set when Rx alignment error counter reaches half the maximum value */\n#define ETH_MMCRIR_RFCES_Pos                          (5U)\n#define ETH_MMCRIR_RFCES_Msk                          (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */\n#define ETH_MMCRIR_RFCES                              ETH_MMCRIR_RFCES_Msk     /* Set when Rx crc error counter reaches half the maximum value */\n\n/* Bit definition for Ethernet MMC Transmit Interrupt Register */\n#define ETH_MMCTIR_TGFS_Pos                           (21U)\n#define ETH_MMCTIR_TGFS_Msk                           (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */\n#define ETH_MMCTIR_TGFS                               ETH_MMCTIR_TGFS_Msk      /* Set when Tx good frame count counter reaches half the maximum value */\n#define ETH_MMCTIR_TGFMSCS_Pos                        (15U)\n#define ETH_MMCTIR_TGFMSCS_Msk                        (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */\n#define ETH_MMCTIR_TGFMSCS                            ETH_MMCTIR_TGFMSCS_Msk   /* Set when Tx good multi col counter reaches half the maximum value */\n#define ETH_MMCTIR_TGFSCS_Pos                         (14U)\n#define ETH_MMCTIR_TGFSCS_Msk                         (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */\n#define ETH_MMCTIR_TGFSCS                             ETH_MMCTIR_TGFSCS_Msk    /* Set when Tx good single col counter reaches half the maximum value */\n\n/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */\n#define ETH_MMCRIMR_RGUFM_Pos                         (17U)\n#define ETH_MMCRIMR_RGUFM_Msk                         (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */\n#define ETH_MMCRIMR_RGUFM                             ETH_MMCRIMR_RGUFM_Msk    /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */\n#define ETH_MMCRIMR_RFAEM_Pos                         (6U)\n#define ETH_MMCRIMR_RFAEM_Msk                         (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */\n#define ETH_MMCRIMR_RFAEM                             ETH_MMCRIMR_RFAEM_Msk    /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */\n#define ETH_MMCRIMR_RFCEM_Pos                         (5U)\n#define ETH_MMCRIMR_RFCEM_Msk                         (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */\n#define ETH_MMCRIMR_RFCEM                             ETH_MMCRIMR_RFCEM_Msk    /* Mask the interrupt when Rx crc error counter reaches half the maximum value */\n\n/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */\n#define ETH_MMCTIMR_TGFM_Pos                          (21U)\n#define ETH_MMCTIMR_TGFM_Msk                          (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */\n#define ETH_MMCTIMR_TGFM                              ETH_MMCTIMR_TGFM_Msk     /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */\n#define ETH_MMCTIMR_TGFMSCM_Pos                       (15U)\n#define ETH_MMCTIMR_TGFMSCM_Msk                       (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */\n#define ETH_MMCTIMR_TGFMSCM                           ETH_MMCTIMR_TGFMSCM_Msk  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */\n#define ETH_MMCTIMR_TGFSCM_Pos                        (14U)\n#define ETH_MMCTIMR_TGFSCM_Msk                        (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */\n#define ETH_MMCTIMR_TGFSCM                            ETH_MMCTIMR_TGFSCM_Msk   /* Mask the interrupt when Tx good single col counter reaches half the maximum value */\n\n/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */\n#define ETH_MMCTGFSCCR_TGFSCC_Pos                     (0U)\n#define ETH_MMCTGFSCCR_TGFSCC_Msk                     (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCTGFSCCR_TGFSCC                         ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */\n\n/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */\n#define ETH_MMCTGFMSCCR_TGFMSCC_Pos                   (0U)\n#define ETH_MMCTGFMSCCR_TGFMSCC_Msk                   (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCTGFMSCCR_TGFMSCC                       ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */\n\n/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */\n#define ETH_MMCTGFCR_TGFC_Pos                         (0U)\n#define ETH_MMCTGFCR_TGFC_Msk                         (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCTGFCR_TGFC                             ETH_MMCTGFCR_TGFC_Msk    /* Number of good frames transmitted. */\n\n/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */\n#define ETH_MMCRFCECR_RFCEC_Pos                       (0U)\n#define ETH_MMCRFCECR_RFCEC_Msk                       (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCRFCECR_RFCEC                           ETH_MMCRFCECR_RFCEC_Msk  /* Number of frames received with CRC error. */\n\n/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */\n#define ETH_MMCRFAECR_RFAEC_Pos                       (0U)\n#define ETH_MMCRFAECR_RFAEC_Msk                       (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCRFAECR_RFAEC                           ETH_MMCRFAECR_RFAEC_Msk  /* Number of frames received with alignment (dribble) error */\n\n/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */\n#define ETH_MMCRGUFCR_RGUFC_Pos                       (0U)\n#define ETH_MMCRGUFCR_RGUFC_Msk                       (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCRGUFCR_RGUFC                           ETH_MMCRGUFCR_RGUFC_Msk  /* Number of good unicast frames received. */\n\n/******************************************************************************/\n/*               Ethernet PTP Registers bits definition                       */\n/******************************************************************************/\n\n/* Bit definition for Ethernet PTP Time Stamp Contol Register */\n#define ETH_PTPTSCR_TSCNT_Pos                         (16U)\n#define ETH_PTPTSCR_TSCNT_Msk                         (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */\n#define ETH_PTPTSCR_TSCNT                             ETH_PTPTSCR_TSCNT_Msk    /* Time stamp clock node type */\n#define ETH_PTPTSSR_TSSMRME_Pos                       (15U)\n#define ETH_PTPTSSR_TSSMRME_Msk                       (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */\n#define ETH_PTPTSSR_TSSMRME                           ETH_PTPTSSR_TSSMRME_Msk  /* Time stamp snapshot for message relevant to master enable */\n#define ETH_PTPTSSR_TSSEME_Pos                        (14U)\n#define ETH_PTPTSSR_TSSEME_Msk                        (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */\n#define ETH_PTPTSSR_TSSEME                            ETH_PTPTSSR_TSSEME_Msk   /* Time stamp snapshot for event message enable */\n#define ETH_PTPTSSR_TSSIPV4FE_Pos                     (13U)\n#define ETH_PTPTSSR_TSSIPV4FE_Msk                     (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */\n#define ETH_PTPTSSR_TSSIPV4FE                         ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */\n#define ETH_PTPTSSR_TSSIPV6FE_Pos                     (12U)\n#define ETH_PTPTSSR_TSSIPV6FE_Msk                     (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */\n#define ETH_PTPTSSR_TSSIPV6FE                         ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */\n#define ETH_PTPTSSR_TSSPTPOEFE_Pos                    (11U)\n#define ETH_PTPTSSR_TSSPTPOEFE_Msk                    (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */\n#define ETH_PTPTSSR_TSSPTPOEFE                        ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */\n#define ETH_PTPTSSR_TSPTPPSV2E_Pos                    (10U)\n#define ETH_PTPTSSR_TSPTPPSV2E_Msk                    (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */\n#define ETH_PTPTSSR_TSPTPPSV2E                        ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */\n#define ETH_PTPTSSR_TSSSR_Pos                         (9U)\n#define ETH_PTPTSSR_TSSSR_Msk                         (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */\n#define ETH_PTPTSSR_TSSSR                             ETH_PTPTSSR_TSSSR_Msk    /* Time stamp Sub-seconds rollover */\n#define ETH_PTPTSSR_TSSARFE_Pos                       (8U)\n#define ETH_PTPTSSR_TSSARFE_Msk                       (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */\n#define ETH_PTPTSSR_TSSARFE                           ETH_PTPTSSR_TSSARFE_Msk  /* Time stamp snapshot for all received frames enable */\n\n#define ETH_PTPTSCR_TSARU_Pos                         (5U)\n#define ETH_PTPTSCR_TSARU_Msk                         (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */\n#define ETH_PTPTSCR_TSARU                             ETH_PTPTSCR_TSARU_Msk    /* Addend register update */\n#define ETH_PTPTSCR_TSITE_Pos                         (4U)\n#define ETH_PTPTSCR_TSITE_Msk                         (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */\n#define ETH_PTPTSCR_TSITE                             ETH_PTPTSCR_TSITE_Msk    /* Time stamp interrupt trigger enable */\n#define ETH_PTPTSCR_TSSTU_Pos                         (3U)\n#define ETH_PTPTSCR_TSSTU_Msk                         (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */\n#define ETH_PTPTSCR_TSSTU                             ETH_PTPTSCR_TSSTU_Msk    /* Time stamp update */\n#define ETH_PTPTSCR_TSSTI_Pos                         (2U)\n#define ETH_PTPTSCR_TSSTI_Msk                         (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */\n#define ETH_PTPTSCR_TSSTI                             ETH_PTPTSCR_TSSTI_Msk    /* Time stamp initialize */\n#define ETH_PTPTSCR_TSFCU_Pos                         (1U)\n#define ETH_PTPTSCR_TSFCU_Msk                         (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */\n#define ETH_PTPTSCR_TSFCU                             ETH_PTPTSCR_TSFCU_Msk    /* Time stamp fine or coarse update */\n#define ETH_PTPTSCR_TSE_Pos                           (0U)\n#define ETH_PTPTSCR_TSE_Msk                           (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */\n#define ETH_PTPTSCR_TSE                               ETH_PTPTSCR_TSE_Msk      /* Time stamp enable */\n\n/* Bit definition for Ethernet PTP Sub-Second Increment Register */\n#define ETH_PTPSSIR_STSSI_Pos                         (0U)\n#define ETH_PTPSSIR_STSSI_Msk                         (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */\n#define ETH_PTPSSIR_STSSI                             ETH_PTPSSIR_STSSI_Msk    /* System time Sub-second increment value */\n\n/* Bit definition for Ethernet PTP Time Stamp High Register */\n#define ETH_PTPTSHR_STS_Pos                           (0U)\n#define ETH_PTPTSHR_STS_Msk                           (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */\n#define ETH_PTPTSHR_STS                               ETH_PTPTSHR_STS_Msk      /* System Time second */\n\n/* Bit definition for Ethernet PTP Time Stamp Low Register */\n#define ETH_PTPTSLR_STPNS_Pos                         (31U)\n#define ETH_PTPTSLR_STPNS_Msk                         (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */\n#define ETH_PTPTSLR_STPNS                             ETH_PTPTSLR_STPNS_Msk    /* System Time Positive or negative time */\n#define ETH_PTPTSLR_STSS_Pos                          (0U)\n#define ETH_PTPTSLR_STSS_Msk                          (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */\n#define ETH_PTPTSLR_STSS                              ETH_PTPTSLR_STSS_Msk     /* System Time sub-seconds */\n\n/* Bit definition for Ethernet PTP Time Stamp High Update Register */\n#define ETH_PTPTSHUR_TSUS_Pos                         (0U)\n#define ETH_PTPTSHUR_TSUS_Msk                         (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */\n#define ETH_PTPTSHUR_TSUS                             ETH_PTPTSHUR_TSUS_Msk    /* Time stamp update seconds */\n\n/* Bit definition for Ethernet PTP Time Stamp Low Update Register */\n#define ETH_PTPTSLUR_TSUPNS_Pos                       (31U)\n#define ETH_PTPTSLUR_TSUPNS_Msk                       (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */\n#define ETH_PTPTSLUR_TSUPNS                           ETH_PTPTSLUR_TSUPNS_Msk  /* Time stamp update Positive or negative time */\n#define ETH_PTPTSLUR_TSUSS_Pos                        (0U)\n#define ETH_PTPTSLUR_TSUSS_Msk                        (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */\n#define ETH_PTPTSLUR_TSUSS                            ETH_PTPTSLUR_TSUSS_Msk   /* Time stamp update sub-seconds */\n\n/* Bit definition for Ethernet PTP Time Stamp Addend Register */\n#define ETH_PTPTSAR_TSA_Pos                           (0U)\n#define ETH_PTPTSAR_TSA_Msk                           (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */\n#define ETH_PTPTSAR_TSA                               ETH_PTPTSAR_TSA_Msk      /* Time stamp addend */\n\n/* Bit definition for Ethernet PTP Target Time High Register */\n#define ETH_PTPTTHR_TTSH_Pos                          (0U)\n#define ETH_PTPTTHR_TTSH_Msk                          (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */\n#define ETH_PTPTTHR_TTSH                              ETH_PTPTTHR_TTSH_Msk     /* Target time stamp high */\n\n/* Bit definition for Ethernet PTP Target Time Low Register */\n#define ETH_PTPTTLR_TTSL_Pos                          (0U)\n#define ETH_PTPTTLR_TTSL_Msk                          (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */\n#define ETH_PTPTTLR_TTSL                              ETH_PTPTTLR_TTSL_Msk     /* Target time stamp low */\n\n/* Bit definition for Ethernet PTP Time Stamp Status Register */\n#define ETH_PTPTSSR_TSTTR_Pos                         (5U)\n#define ETH_PTPTSSR_TSTTR_Msk                         (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */\n#define ETH_PTPTSSR_TSTTR                             ETH_PTPTSSR_TSTTR_Msk    /* Time stamp target time reached */\n#define ETH_PTPTSSR_TSSO_Pos                          (4U)\n#define ETH_PTPTSSR_TSSO_Msk                          (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */\n#define ETH_PTPTSSR_TSSO                              ETH_PTPTSSR_TSSO_Msk     /* Time stamp seconds overflow */\n\n/******************************************************************************/\n/*                 Ethernet DMA Registers bits definition                     */\n/******************************************************************************/\n\n/* Bit definition for Ethernet DMA Bus Mode Register */\n#define ETH_DMABMR_AAB_Pos                            (25U)\n#define ETH_DMABMR_AAB_Msk                            (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */\n#define ETH_DMABMR_AAB                                ETH_DMABMR_AAB_Msk       /* Address-Aligned beats */\n#define ETH_DMABMR_FPM_Pos                            (24U)\n#define ETH_DMABMR_FPM_Msk                            (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */\n#define ETH_DMABMR_FPM                                ETH_DMABMR_FPM_Msk       /* 4xPBL mode */\n#define ETH_DMABMR_USP_Pos                            (23U)\n#define ETH_DMABMR_USP_Msk                            (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */\n#define ETH_DMABMR_USP                                ETH_DMABMR_USP_Msk       /* Use separate PBL */\n#define ETH_DMABMR_RDP_Pos                            (17U)\n#define ETH_DMABMR_RDP_Msk                            (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */\n#define ETH_DMABMR_RDP                                ETH_DMABMR_RDP_Msk       /* RxDMA PBL */\n#define ETH_DMABMR_RDP_1Beat                          0x00020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 1 */\n#define ETH_DMABMR_RDP_2Beat                          0x00040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 2 */\n#define ETH_DMABMR_RDP_4Beat                          0x00080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\n#define ETH_DMABMR_RDP_8Beat                          0x00100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\n#define ETH_DMABMR_RDP_16Beat                         0x00200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\n#define ETH_DMABMR_RDP_32Beat                         0x00400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\n#define ETH_DMABMR_RDP_4xPBL_4Beat                    0x01020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\n#define ETH_DMABMR_RDP_4xPBL_8Beat                    0x01040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\n#define ETH_DMABMR_RDP_4xPBL_16Beat                   0x01080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\n#define ETH_DMABMR_RDP_4xPBL_32Beat                   0x01100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\n#define ETH_DMABMR_RDP_4xPBL_64Beat                   0x01200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 64 */\n#define ETH_DMABMR_RDP_4xPBL_128Beat                  0x01400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 128 */\n#define ETH_DMABMR_FB_Pos                             (16U)\n#define ETH_DMABMR_FB_Msk                             (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */\n#define ETH_DMABMR_FB                                 ETH_DMABMR_FB_Msk        /* Fixed Burst */\n#define ETH_DMABMR_RTPR_Pos                           (14U)\n#define ETH_DMABMR_RTPR_Msk                           (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */\n#define ETH_DMABMR_RTPR                               ETH_DMABMR_RTPR_Msk      /* Rx Tx priority ratio */\n#define ETH_DMABMR_RTPR_1_1                           0x00000000U              /* Rx Tx priority ratio */\n#define ETH_DMABMR_RTPR_2_1                           0x00004000U              /* Rx Tx priority ratio */\n#define ETH_DMABMR_RTPR_3_1                           0x00008000U              /* Rx Tx priority ratio */\n#define ETH_DMABMR_RTPR_4_1                           0x0000C000U              /* Rx Tx priority ratio */\n#define ETH_DMABMR_PBL_Pos                            (8U)\n#define ETH_DMABMR_PBL_Msk                            (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */\n#define ETH_DMABMR_PBL                                ETH_DMABMR_PBL_Msk       /* Programmable burst length */\n#define ETH_DMABMR_PBL_1Beat                          0x00000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\n#define ETH_DMABMR_PBL_2Beat                          0x00000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\n#define ETH_DMABMR_PBL_4Beat                          0x00000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\n#define ETH_DMABMR_PBL_8Beat                          0x00000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\n#define ETH_DMABMR_PBL_16Beat                         0x00001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\n#define ETH_DMABMR_PBL_32Beat                         0x00002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\n#define ETH_DMABMR_PBL_4xPBL_4Beat                    0x01000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\n#define ETH_DMABMR_PBL_4xPBL_8Beat                    0x01000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\n#define ETH_DMABMR_PBL_4xPBL_16Beat                   0x01000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\n#define ETH_DMABMR_PBL_4xPBL_32Beat                   0x01000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\n#define ETH_DMABMR_PBL_4xPBL_64Beat                   0x01001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\n#define ETH_DMABMR_PBL_4xPBL_128Beat                  0x01002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\n#define ETH_DMABMR_EDE_Pos                            (7U)\n#define ETH_DMABMR_EDE_Msk                            (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */\n#define ETH_DMABMR_EDE                                ETH_DMABMR_EDE_Msk       /* Enhanced Descriptor Enable */\n#define ETH_DMABMR_DSL_Pos                            (2U)\n#define ETH_DMABMR_DSL_Msk                            (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */\n#define ETH_DMABMR_DSL                                ETH_DMABMR_DSL_Msk       /* Descriptor Skip Length */\n#define ETH_DMABMR_DA_Pos                             (1U)\n#define ETH_DMABMR_DA_Msk                             (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */\n#define ETH_DMABMR_DA                                 ETH_DMABMR_DA_Msk        /* DMA arbitration scheme */\n#define ETH_DMABMR_SR_Pos                             (0U)\n#define ETH_DMABMR_SR_Msk                             (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */\n#define ETH_DMABMR_SR                                 ETH_DMABMR_SR_Msk        /* Software reset */\n\n/* Bit definition for Ethernet DMA Transmit Poll Demand Register */\n#define ETH_DMATPDR_TPD_Pos                           (0U)\n#define ETH_DMATPDR_TPD_Msk                           (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMATPDR_TPD                               ETH_DMATPDR_TPD_Msk      /* Transmit poll demand */\n\n/* Bit definition for Ethernet DMA Receive Poll Demand Register */\n#define ETH_DMARPDR_RPD_Pos                           (0U)\n#define ETH_DMARPDR_RPD_Msk                           (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMARPDR_RPD                               ETH_DMARPDR_RPD_Msk      /* Receive poll demand  */\n\n/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */\n#define ETH_DMARDLAR_SRL_Pos                          (0U)\n#define ETH_DMARDLAR_SRL_Msk                          (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMARDLAR_SRL                              ETH_DMARDLAR_SRL_Msk     /* Start of receive list */\n\n/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */\n#define ETH_DMATDLAR_STL_Pos                          (0U)\n#define ETH_DMATDLAR_STL_Msk                          (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMATDLAR_STL                              ETH_DMATDLAR_STL_Msk     /* Start of transmit list */\n\n/* Bit definition for Ethernet DMA Status Register */\n#define ETH_DMASR_TSTS_Pos                            (29U)\n#define ETH_DMASR_TSTS_Msk                            (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */\n#define ETH_DMASR_TSTS                                ETH_DMASR_TSTS_Msk       /* Time-stamp trigger status */\n#define ETH_DMASR_PMTS_Pos                            (28U)\n#define ETH_DMASR_PMTS_Msk                            (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */\n#define ETH_DMASR_PMTS                                ETH_DMASR_PMTS_Msk       /* PMT status */\n#define ETH_DMASR_MMCS_Pos                            (27U)\n#define ETH_DMASR_MMCS_Msk                            (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */\n#define ETH_DMASR_MMCS                                ETH_DMASR_MMCS_Msk       /* MMC status */\n#define ETH_DMASR_EBS_Pos                             (23U)\n#define ETH_DMASR_EBS_Msk                             (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */\n#define ETH_DMASR_EBS                                 ETH_DMASR_EBS_Msk        /* Error bits status */\n  /* combination with EBS[2:0] for GetFlagStatus function */\n#define ETH_DMASR_EBS_DescAccess_Pos                  (25U)\n#define ETH_DMASR_EBS_DescAccess_Msk                  (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */\n#define ETH_DMASR_EBS_DescAccess                      ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */\n#define ETH_DMASR_EBS_ReadTransf_Pos                  (24U)\n#define ETH_DMASR_EBS_ReadTransf_Msk                  (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */\n#define ETH_DMASR_EBS_ReadTransf                      ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */\n#define ETH_DMASR_EBS_DataTransfTx_Pos                (23U)\n#define ETH_DMASR_EBS_DataTransfTx_Msk                (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */\n#define ETH_DMASR_EBS_DataTransfTx                    ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */\n#define ETH_DMASR_TPS_Pos                             (20U)\n#define ETH_DMASR_TPS_Msk                             (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */\n#define ETH_DMASR_TPS                                 ETH_DMASR_TPS_Msk        /* Transmit process state */\n#define ETH_DMASR_TPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Tx Command issued  */\n#define ETH_DMASR_TPS_Fetching_Pos                    (20U)\n#define ETH_DMASR_TPS_Fetching_Msk                    (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */\n#define ETH_DMASR_TPS_Fetching                        ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */\n#define ETH_DMASR_TPS_Waiting_Pos                     (21U)\n#define ETH_DMASR_TPS_Waiting_Msk                     (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */\n#define ETH_DMASR_TPS_Waiting                         ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */\n#define ETH_DMASR_TPS_Reading_Pos                     (20U)\n#define ETH_DMASR_TPS_Reading_Msk                     (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */\n#define ETH_DMASR_TPS_Reading                         ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */\n#define ETH_DMASR_TPS_Suspended_Pos                   (21U)\n#define ETH_DMASR_TPS_Suspended_Msk                   (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */\n#define ETH_DMASR_TPS_Suspended                       ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */\n#define ETH_DMASR_TPS_Closing_Pos                     (20U)\n#define ETH_DMASR_TPS_Closing_Msk                     (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */\n#define ETH_DMASR_TPS_Closing                         ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */\n#define ETH_DMASR_RPS_Pos                             (17U)\n#define ETH_DMASR_RPS_Msk                             (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */\n#define ETH_DMASR_RPS                                 ETH_DMASR_RPS_Msk        /* Receive process state */\n#define ETH_DMASR_RPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Rx Command issued */\n#define ETH_DMASR_RPS_Fetching_Pos                    (17U)\n#define ETH_DMASR_RPS_Fetching_Msk                    (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */\n#define ETH_DMASR_RPS_Fetching                        ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */\n#define ETH_DMASR_RPS_Waiting_Pos                     (17U)\n#define ETH_DMASR_RPS_Waiting_Msk                     (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */\n#define ETH_DMASR_RPS_Waiting                         ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */\n#define ETH_DMASR_RPS_Suspended_Pos                   (19U)\n#define ETH_DMASR_RPS_Suspended_Msk                   (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */\n#define ETH_DMASR_RPS_Suspended                       ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */\n#define ETH_DMASR_RPS_Closing_Pos                     (17U)\n#define ETH_DMASR_RPS_Closing_Msk                     (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */\n#define ETH_DMASR_RPS_Closing                         ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */\n#define ETH_DMASR_RPS_Queuing_Pos                     (17U)\n#define ETH_DMASR_RPS_Queuing_Msk                     (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */\n#define ETH_DMASR_RPS_Queuing                         ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */\n#define ETH_DMASR_NIS_Pos                             (16U)\n#define ETH_DMASR_NIS_Msk                             (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */\n#define ETH_DMASR_NIS                                 ETH_DMASR_NIS_Msk        /* Normal interrupt summary */\n#define ETH_DMASR_AIS_Pos                             (15U)\n#define ETH_DMASR_AIS_Msk                             (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */\n#define ETH_DMASR_AIS                                 ETH_DMASR_AIS_Msk        /* Abnormal interrupt summary */\n#define ETH_DMASR_ERS_Pos                             (14U)\n#define ETH_DMASR_ERS_Msk                             (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */\n#define ETH_DMASR_ERS                                 ETH_DMASR_ERS_Msk        /* Early receive status */\n#define ETH_DMASR_FBES_Pos                            (13U)\n#define ETH_DMASR_FBES_Msk                            (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */\n#define ETH_DMASR_FBES                                ETH_DMASR_FBES_Msk       /* Fatal bus error status */\n#define ETH_DMASR_ETS_Pos                             (10U)\n#define ETH_DMASR_ETS_Msk                             (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */\n#define ETH_DMASR_ETS                                 ETH_DMASR_ETS_Msk        /* Early transmit status */\n#define ETH_DMASR_RWTS_Pos                            (9U)\n#define ETH_DMASR_RWTS_Msk                            (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */\n#define ETH_DMASR_RWTS                                ETH_DMASR_RWTS_Msk       /* Receive watchdog timeout status */\n#define ETH_DMASR_RPSS_Pos                            (8U)\n#define ETH_DMASR_RPSS_Msk                            (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */\n#define ETH_DMASR_RPSS                                ETH_DMASR_RPSS_Msk       /* Receive process stopped status */\n#define ETH_DMASR_RBUS_Pos                            (7U)\n#define ETH_DMASR_RBUS_Msk                            (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */\n#define ETH_DMASR_RBUS                                ETH_DMASR_RBUS_Msk       /* Receive buffer unavailable status */\n#define ETH_DMASR_RS_Pos                              (6U)\n#define ETH_DMASR_RS_Msk                              (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */\n#define ETH_DMASR_RS                                  ETH_DMASR_RS_Msk         /* Receive status */\n#define ETH_DMASR_TUS_Pos                             (5U)\n#define ETH_DMASR_TUS_Msk                             (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */\n#define ETH_DMASR_TUS                                 ETH_DMASR_TUS_Msk        /* Transmit underflow status */\n#define ETH_DMASR_ROS_Pos                             (4U)\n#define ETH_DMASR_ROS_Msk                             (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */\n#define ETH_DMASR_ROS                                 ETH_DMASR_ROS_Msk        /* Receive overflow status */\n#define ETH_DMASR_TJTS_Pos                            (3U)\n#define ETH_DMASR_TJTS_Msk                            (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */\n#define ETH_DMASR_TJTS                                ETH_DMASR_TJTS_Msk       /* Transmit jabber timeout status */\n#define ETH_DMASR_TBUS_Pos                            (2U)\n#define ETH_DMASR_TBUS_Msk                            (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */\n#define ETH_DMASR_TBUS                                ETH_DMASR_TBUS_Msk       /* Transmit buffer unavailable status */\n#define ETH_DMASR_TPSS_Pos                            (1U)\n#define ETH_DMASR_TPSS_Msk                            (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */\n#define ETH_DMASR_TPSS                                ETH_DMASR_TPSS_Msk       /* Transmit process stopped status */\n#define ETH_DMASR_TS_Pos                              (0U)\n#define ETH_DMASR_TS_Msk                              (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */\n#define ETH_DMASR_TS                                  ETH_DMASR_TS_Msk         /* Transmit status */\n\n/* Bit definition for Ethernet DMA Operation Mode Register */\n#define ETH_DMAOMR_DTCEFD_Pos                         (26U)\n#define ETH_DMAOMR_DTCEFD_Msk                         (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */\n#define ETH_DMAOMR_DTCEFD                             ETH_DMAOMR_DTCEFD_Msk    /* Disable Dropping of TCP/IP checksum error frames */\n#define ETH_DMAOMR_RSF_Pos                            (25U)\n#define ETH_DMAOMR_RSF_Msk                            (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */\n#define ETH_DMAOMR_RSF                                ETH_DMAOMR_RSF_Msk       /* Receive store and forward */\n#define ETH_DMAOMR_DFRF_Pos                           (24U)\n#define ETH_DMAOMR_DFRF_Msk                           (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */\n#define ETH_DMAOMR_DFRF                               ETH_DMAOMR_DFRF_Msk      /* Disable flushing of received frames */\n#define ETH_DMAOMR_TSF_Pos                            (21U)\n#define ETH_DMAOMR_TSF_Msk                            (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */\n#define ETH_DMAOMR_TSF                                ETH_DMAOMR_TSF_Msk       /* Transmit store and forward */\n#define ETH_DMAOMR_FTF_Pos                            (20U)\n#define ETH_DMAOMR_FTF_Msk                            (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */\n#define ETH_DMAOMR_FTF                                ETH_DMAOMR_FTF_Msk       /* Flush transmit FIFO */\n#define ETH_DMAOMR_TTC_Pos                            (14U)\n#define ETH_DMAOMR_TTC_Msk                            (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */\n#define ETH_DMAOMR_TTC                                ETH_DMAOMR_TTC_Msk       /* Transmit threshold control */\n#define ETH_DMAOMR_TTC_64Bytes                        0x00000000U              /* threshold level of the MTL Transmit FIFO is 64 Bytes */\n#define ETH_DMAOMR_TTC_128Bytes                       0x00004000U              /* threshold level of the MTL Transmit FIFO is 128 Bytes */\n#define ETH_DMAOMR_TTC_192Bytes                       0x00008000U              /* threshold level of the MTL Transmit FIFO is 192 Bytes */\n#define ETH_DMAOMR_TTC_256Bytes                       0x0000C000U              /* threshold level of the MTL Transmit FIFO is 256 Bytes */\n#define ETH_DMAOMR_TTC_40Bytes                        0x00010000U              /* threshold level of the MTL Transmit FIFO is 40 Bytes */\n#define ETH_DMAOMR_TTC_32Bytes                        0x00014000U              /* threshold level of the MTL Transmit FIFO is 32 Bytes */\n#define ETH_DMAOMR_TTC_24Bytes                        0x00018000U              /* threshold level of the MTL Transmit FIFO is 24 Bytes */\n#define ETH_DMAOMR_TTC_16Bytes                        0x0001C000U              /* threshold level of the MTL Transmit FIFO is 16 Bytes */\n#define ETH_DMAOMR_ST_Pos                             (13U)\n#define ETH_DMAOMR_ST_Msk                             (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */\n#define ETH_DMAOMR_ST                                 ETH_DMAOMR_ST_Msk        /* Start/stop transmission command */\n#define ETH_DMAOMR_FEF_Pos                            (7U)\n#define ETH_DMAOMR_FEF_Msk                            (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */\n#define ETH_DMAOMR_FEF                                ETH_DMAOMR_FEF_Msk       /* Forward error frames */\n#define ETH_DMAOMR_FUGF_Pos                           (6U)\n#define ETH_DMAOMR_FUGF_Msk                           (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */\n#define ETH_DMAOMR_FUGF                               ETH_DMAOMR_FUGF_Msk      /* Forward undersized good frames */\n#define ETH_DMAOMR_RTC_Pos                            (3U)\n#define ETH_DMAOMR_RTC_Msk                            (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */\n#define ETH_DMAOMR_RTC                                ETH_DMAOMR_RTC_Msk       /* receive threshold control */\n#define ETH_DMAOMR_RTC_64Bytes                        0x00000000U              /* threshold level of the MTL Receive FIFO is 64 Bytes */\n#define ETH_DMAOMR_RTC_32Bytes                        0x00000008U              /* threshold level of the MTL Receive FIFO is 32 Bytes */\n#define ETH_DMAOMR_RTC_96Bytes                        0x00000010U              /* threshold level of the MTL Receive FIFO is 96 Bytes */\n#define ETH_DMAOMR_RTC_128Bytes                       0x00000018U              /* threshold level of the MTL Receive FIFO is 128 Bytes */\n#define ETH_DMAOMR_OSF_Pos                            (2U)\n#define ETH_DMAOMR_OSF_Msk                            (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */\n#define ETH_DMAOMR_OSF                                ETH_DMAOMR_OSF_Msk       /* operate on second frame */\n#define ETH_DMAOMR_SR_Pos                             (1U)\n#define ETH_DMAOMR_SR_Msk                             (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */\n#define ETH_DMAOMR_SR                                 ETH_DMAOMR_SR_Msk        /* Start/stop receive */\n\n/* Bit definition for Ethernet DMA Interrupt Enable Register */\n#define ETH_DMAIER_NISE_Pos                           (16U)\n#define ETH_DMAIER_NISE_Msk                           (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */\n#define ETH_DMAIER_NISE                               ETH_DMAIER_NISE_Msk      /* Normal interrupt summary enable */\n#define ETH_DMAIER_AISE_Pos                           (15U)\n#define ETH_DMAIER_AISE_Msk                           (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */\n#define ETH_DMAIER_AISE                               ETH_DMAIER_AISE_Msk      /* Abnormal interrupt summary enable */\n#define ETH_DMAIER_ERIE_Pos                           (14U)\n#define ETH_DMAIER_ERIE_Msk                           (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */\n#define ETH_DMAIER_ERIE                               ETH_DMAIER_ERIE_Msk      /* Early receive interrupt enable */\n#define ETH_DMAIER_FBEIE_Pos                          (13U)\n#define ETH_DMAIER_FBEIE_Msk                          (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */\n#define ETH_DMAIER_FBEIE                              ETH_DMAIER_FBEIE_Msk     /* Fatal bus error interrupt enable */\n#define ETH_DMAIER_ETIE_Pos                           (10U)\n#define ETH_DMAIER_ETIE_Msk                           (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */\n#define ETH_DMAIER_ETIE                               ETH_DMAIER_ETIE_Msk      /* Early transmit interrupt enable */\n#define ETH_DMAIER_RWTIE_Pos                          (9U)\n#define ETH_DMAIER_RWTIE_Msk                          (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */\n#define ETH_DMAIER_RWTIE                              ETH_DMAIER_RWTIE_Msk     /* Receive watchdog timeout interrupt enable */\n#define ETH_DMAIER_RPSIE_Pos                          (8U)\n#define ETH_DMAIER_RPSIE_Msk                          (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */\n#define ETH_DMAIER_RPSIE                              ETH_DMAIER_RPSIE_Msk     /* Receive process stopped interrupt enable */\n#define ETH_DMAIER_RBUIE_Pos                          (7U)\n#define ETH_DMAIER_RBUIE_Msk                          (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */\n#define ETH_DMAIER_RBUIE                              ETH_DMAIER_RBUIE_Msk     /* Receive buffer unavailable interrupt enable */\n#define ETH_DMAIER_RIE_Pos                            (6U)\n#define ETH_DMAIER_RIE_Msk                            (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */\n#define ETH_DMAIER_RIE                                ETH_DMAIER_RIE_Msk       /* Receive interrupt enable */\n#define ETH_DMAIER_TUIE_Pos                           (5U)\n#define ETH_DMAIER_TUIE_Msk                           (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */\n#define ETH_DMAIER_TUIE                               ETH_DMAIER_TUIE_Msk      /* Transmit Underflow interrupt enable */\n#define ETH_DMAIER_ROIE_Pos                           (4U)\n#define ETH_DMAIER_ROIE_Msk                           (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */\n#define ETH_DMAIER_ROIE                               ETH_DMAIER_ROIE_Msk      /* Receive Overflow interrupt enable */\n#define ETH_DMAIER_TJTIE_Pos                          (3U)\n#define ETH_DMAIER_TJTIE_Msk                          (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */\n#define ETH_DMAIER_TJTIE                              ETH_DMAIER_TJTIE_Msk     /* Transmit jabber timeout interrupt enable */\n#define ETH_DMAIER_TBUIE_Pos                          (2U)\n#define ETH_DMAIER_TBUIE_Msk                          (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */\n#define ETH_DMAIER_TBUIE                              ETH_DMAIER_TBUIE_Msk     /* Transmit buffer unavailable interrupt enable */\n#define ETH_DMAIER_TPSIE_Pos                          (1U)\n#define ETH_DMAIER_TPSIE_Msk                          (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */\n#define ETH_DMAIER_TPSIE                              ETH_DMAIER_TPSIE_Msk     /* Transmit process stopped interrupt enable */\n#define ETH_DMAIER_TIE_Pos                            (0U)\n#define ETH_DMAIER_TIE_Msk                            (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */\n#define ETH_DMAIER_TIE                                ETH_DMAIER_TIE_Msk       /* Transmit interrupt enable */\n\n/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */\n#define ETH_DMAMFBOCR_OFOC_Pos                        (28U)\n#define ETH_DMAMFBOCR_OFOC_Msk                        (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */\n#define ETH_DMAMFBOCR_OFOC                            ETH_DMAMFBOCR_OFOC_Msk   /* Overflow bit for FIFO overflow counter */\n#define ETH_DMAMFBOCR_MFA_Pos                         (17U)\n#define ETH_DMAMFBOCR_MFA_Msk                         (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */\n#define ETH_DMAMFBOCR_MFA                             ETH_DMAMFBOCR_MFA_Msk    /* Number of frames missed by the application */\n#define ETH_DMAMFBOCR_OMFC_Pos                        (16U)\n#define ETH_DMAMFBOCR_OMFC_Msk                        (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */\n#define ETH_DMAMFBOCR_OMFC                            ETH_DMAMFBOCR_OMFC_Msk   /* Overflow bit for missed frame counter */\n#define ETH_DMAMFBOCR_MFC_Pos                         (0U)\n#define ETH_DMAMFBOCR_MFC_Msk                         (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */\n#define ETH_DMAMFBOCR_MFC                             ETH_DMAMFBOCR_MFC_Msk    /* Number of frames missed by the controller */\n\n/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */\n#define ETH_DMACHTDR_HTDAP_Pos                        (0U)\n#define ETH_DMACHTDR_HTDAP_Msk                        (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMACHTDR_HTDAP                            ETH_DMACHTDR_HTDAP_Msk   /* Host transmit descriptor address pointer */\n\n/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */\n#define ETH_DMACHRDR_HRDAP_Pos                        (0U)\n#define ETH_DMACHRDR_HRDAP_Msk                        (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMACHRDR_HRDAP                            ETH_DMACHRDR_HRDAP_Msk   /* Host receive descriptor address pointer */\n\n/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */\n#define ETH_DMACHTBAR_HTBAP_Pos                       (0U)\n#define ETH_DMACHTBAR_HTBAP_Msk                       (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMACHTBAR_HTBAP                           ETH_DMACHTBAR_HTBAP_Msk  /* Host transmit buffer address pointer */\n\n/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */\n#define ETH_DMACHRBAR_HRBAP_Pos                       (0U)\n#define ETH_DMACHRBAR_HRBAP_Msk                       (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMACHRBAR_HRBAP                           ETH_DMACHRBAR_HRBAP_Msk  /* Host receive buffer address pointer */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                       USB_OTG                              */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/\n#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)\n#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */\n#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)\n#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\n#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */\n#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)\n#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */\n#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)\n#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */\n#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */\n#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)\n#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */\n#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)\n#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */\n#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */\n#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)\n#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */\n#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)\n#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */\n#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)\n#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)\n#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */\n#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)\n#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)\n#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */\n#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */\n#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)\n#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */\n#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */\n#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)\n#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */\n#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */\n#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)\n#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */\n#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)\n#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */\n#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)\n#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */\n#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)\n#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */\n#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */\n\n/********************  Bit definition forUSB_OTG_HCFG register  ********************/\n\n#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)\n#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\n#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */\n#define USB_OTG_HCFG_FSLSPCS_0                   (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCFG_FSLSPCS_1                   (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCFG_FSLSS_Pos                   (2U)\n#define USB_OTG_HCFG_FSLSS_Msk                   (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */\n\n/********************  Bit definition for USB_OTG_DCFG register  ********************/\n\n#define USB_OTG_DCFG_DSPD_Pos                    (0U)\n#define USB_OTG_DCFG_DSPD_Msk                    (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\n#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */\n#define USB_OTG_DCFG_DSPD_0                      (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCFG_DSPD_1                      (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)\n#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */\n\n#define USB_OTG_DCFG_DAD_Pos                     (4U)\n#define USB_OTG_DCFG_DAD_Msk                     (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\n#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */\n#define USB_OTG_DCFG_DAD_0                       (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCFG_DAD_1                       (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCFG_DAD_2                       (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCFG_DAD_3                       (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCFG_DAD_4                       (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCFG_DAD_5                       (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCFG_DAD_6                       (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\n\n#define USB_OTG_DCFG_PFIVL_Pos                   (11U)\n#define USB_OTG_DCFG_PFIVL_Msk                   (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\n#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */\n#define USB_OTG_DCFG_PFIVL_0                     (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCFG_PFIVL_1                     (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\n\n#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)\n#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\n#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */\n#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\n#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\n\n/********************  Bit definition for USB_OTG_PCGCR register  ********************/\n#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)\n#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */\n#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)\n#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */\n#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)\n#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */\n\n/********************  Bit definition for USB_OTG_GOTGINT register  ********************/\n#define USB_OTG_GOTGINT_SEDET_Pos                (2U)\n#define USB_OTG_GOTGINT_SEDET_Msk                (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */\n#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)\n#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */\n#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)\n#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */\n#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)\n#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */\n#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)\n#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */\n#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)\n#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */\n#define USB_OTG_GOTGINT_IDCHNG_Pos               (20U)\n#define USB_OTG_GOTGINT_IDCHNG_Msk               (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */\n#define USB_OTG_GOTGINT_IDCHNG                   USB_OTG_GOTGINT_IDCHNG_Msk    /*!< Change in ID pin input value           */\n\n/********************  Bit definition for USB_OTG_DCTL register  ********************/\n#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)\n#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */\n#define USB_OTG_DCTL_SDIS_Pos                    (1U)\n#define USB_OTG_DCTL_SDIS_Msk                    (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */\n#define USB_OTG_DCTL_GINSTS_Pos                  (2U)\n#define USB_OTG_DCTL_GINSTS_Msk                  (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */\n#define USB_OTG_DCTL_GONSTS_Pos                  (3U)\n#define USB_OTG_DCTL_GONSTS_Msk                  (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\n#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */\n\n#define USB_OTG_DCTL_TCTL_Pos                    (4U)\n#define USB_OTG_DCTL_TCTL_Msk                    (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\n#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */\n#define USB_OTG_DCTL_TCTL_0                      (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCTL_TCTL_1                      (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCTL_TCTL_2                      (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCTL_SGINAK_Pos                  (7U)\n#define USB_OTG_DCTL_SGINAK_Msk                  (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */\n#define USB_OTG_DCTL_CGINAK_Pos                  (8U)\n#define USB_OTG_DCTL_CGINAK_Msk                  (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */\n#define USB_OTG_DCTL_SGONAK_Pos                  (9U)\n#define USB_OTG_DCTL_SGONAK_Msk                  (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */\n#define USB_OTG_DCTL_CGONAK_Pos                  (10U)\n#define USB_OTG_DCTL_CGONAK_Msk                  (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\n#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */\n#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)\n#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */\n\n/********************  Bit definition for USB_OTG_HFIR register  ********************/\n#define USB_OTG_HFIR_FRIVL_Pos                   (0U)\n#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */\n\n/********************  Bit definition for USB_OTG_HFNUM register  ********************/\n#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)\n#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */\n#define USB_OTG_HFNUM_FTREM_Pos                  (16U)\n#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */\n\n/********************  Bit definition for USB_OTG_DSTS register  ********************/\n#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)\n#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */\n\n#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)\n#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\n#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */\n#define USB_OTG_DSTS_ENUMSPD_0                   (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DSTS_ENUMSPD_1                   (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\n#define USB_OTG_DSTS_EERR_Pos                    (3U)\n#define USB_OTG_DSTS_EERR_Msk                    (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\n#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */\n#define USB_OTG_DSTS_FNSOF_Pos                   (8U)\n#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\n#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */\n\n/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/\n#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)\n#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\n#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */\n#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)\n#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\n#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */\n#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */\n#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */\n#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */\n#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */\n#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */\n#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)\n#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */\n#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)\n#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */\n#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)\n#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\n#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */\n\n/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/\n\n#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)\n#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\n#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */\n#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\n#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\n#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\n#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)\n#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\n#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\n#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)\n#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\n#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */\n#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)\n#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\n#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */\n#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)\n#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\n#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */\n#define USB_OTG_GUSBCFG_TRDT_0                   (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\n#define USB_OTG_GUSBCFG_TRDT_1                   (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\n#define USB_OTG_GUSBCFG_TRDT_2                   (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\n#define USB_OTG_GUSBCFG_TRDT_3                   (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\n#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)\n#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */\n#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)\n#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\n#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */\n#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)\n#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\n#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */\n#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)\n#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\n#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */\n#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)\n#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\n#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */\n#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)\n#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\n#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */\n#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)\n#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\n#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */\n#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)\n#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\n#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */\n#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)\n#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\n#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */\n#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)\n#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\n#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */\n#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)\n#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */\n\n/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/\n#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)\n#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\n#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */\n#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)\n#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\n#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */\n#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)\n#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\n#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */\n#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)\n#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\n#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */\n#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)\n#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\n#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */\n\n\n#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)\n#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\n#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */\n#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\n#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\n#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)\n#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\n#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */\n#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)\n#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\n#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */\n\n/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/\n#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)\n#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)\n#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)\n#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)\n#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)\n#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/\n#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)\n#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */\n#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)\n#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */\n#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)\n#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */\n#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\n\n/********************  Bit definition for USB_OTG_HAINT register  ********************/\n#define USB_OTG_HAINT_HAINT_Pos                  (0U)\n#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */\n\n/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/\n#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */\n#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */\n#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)\n#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */\n#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)\n#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */\n#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)\n#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */\n#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask */\n#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)\n#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */\n#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)\n#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */\n\n/********************  Bit definition for USB_OTG_GINTSTS register  ********************/\n#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)\n#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\n#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */\n#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)\n#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */\n#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)\n#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */\n#define USB_OTG_GINTSTS_SOF_Pos                  (3U)\n#define USB_OTG_GINTSTS_SOF_Msk                  (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */\n#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)\n#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */\n#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)\n#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */\n#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)\n#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */\n#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)\n#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */\n#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)\n#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */\n#define USB_OTG_GINTSTS_USBRST_Pos               (12U)\n#define USB_OTG_GINTSTS_USBRST_Msk               (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */\n#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)\n#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */\n#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)\n#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */\n#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)\n#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */\n#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)\n#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */\n#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)\n#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */\n#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)\n#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */\n#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)\n#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */\n#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)\n#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */\n#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */\n#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)\n#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */\n#define USB_OTG_GINTSTS_HCINT_Pos                (25U)\n#define USB_OTG_GINTSTS_HCINT_Msk                (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */\n#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)\n#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */\n#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)\n#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */\n#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */\n#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)\n#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */\n#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)\n#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */\n#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)\n#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */\n#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)\n#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */\n\n/********************  Bit definition for USB_OTG_GINTMSK register  ********************/\n#define USB_OTG_GINTMSK_MMISM_Pos                (1U)\n#define USB_OTG_GINTMSK_MMISM_Msk                (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */\n#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)\n#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */\n#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)\n#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */\n#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)\n#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */\n#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)\n#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */\n#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)\n#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */\n#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)\n#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */\n#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)\n#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */\n#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)\n#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */\n#define USB_OTG_GINTMSK_USBRST_Pos               (12U)\n#define USB_OTG_GINTMSK_USBRST_Msk               (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */\n#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)\n#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */\n#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)\n#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */\n#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)\n#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */\n#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)\n#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\n#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */\n#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)\n#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */\n#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)\n#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */\n#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)\n#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */\n#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)\n#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */\n#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)\n#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1U << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */\n#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */\n#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)\n#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */\n#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)\n#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */\n#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)\n#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */\n#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)\n#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */\n#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */\n#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)\n#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */\n#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)\n#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */\n#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)\n#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */\n#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)\n#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */\n\n/********************  Bit definition for USB_OTG_DAINT register  ********************/\n#define USB_OTG_DAINT_IEPINT_Pos                 (0U)\n#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */\n#define USB_OTG_DAINT_OEPINT_Pos                 (16U)\n#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */\n\n/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/\n#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)\n#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */\n\n/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/\n#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)\n#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\n#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */\n#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)\n#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\n#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)\n#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\n#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)\n#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/\n#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)\n#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */\n#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)\n#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for OTG register  ********************/\n\n#define USB_OTG_CHNUM_Pos                        (0U)\n#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\n#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\n#define USB_OTG_BCNT_Pos                         (4U)\n#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\n\n#define USB_OTG_DPID_Pos                         (15U)\n#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\n#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\n#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\n\n#define USB_OTG_PKTSTS_Pos                       (17U)\n#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\n#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\n#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\n#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\n#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\n\n#define USB_OTG_EPNUM_Pos                        (0U)\n#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\n#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\n\n#define USB_OTG_FRMNUM_Pos                       (21U)\n#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\n#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\n#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\n#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\n#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\n\n/********************  Bit definition for OTG register  ********************/\n\n#define USB_OTG_CHNUM_Pos                        (0U)\n#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\n#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\n#define USB_OTG_BCNT_Pos                         (4U)\n#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\n\n#define USB_OTG_DPID_Pos                         (15U)\n#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\n#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\n#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\n\n#define USB_OTG_PKTSTS_Pos                       (17U)\n#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\n#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\n#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\n#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\n#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\n\n#define USB_OTG_EPNUM_Pos                        (0U)\n#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\n#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\n\n#define USB_OTG_FRMNUM_Pos                       (21U)\n#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\n#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\n#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\n#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\n#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\n\n/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/\n#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)\n#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/\n#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)\n#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */\n\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_NPTXFSA_Pos                      (0U)\n#define USB_OTG_NPTXFSA_Msk                      (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */\n#define USB_OTG_NPTXFD_Pos                       (16U)\n#define USB_OTG_NPTXFD_Msk                       (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */\n#define USB_OTG_TX0FSA_Pos                       (0U)\n#define USB_OTG_TX0FSA_Msk                       (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */\n#define USB_OTG_TX0FD_Pos                        (16U)\n#define USB_OTG_TX0FD_Msk                        (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */\n\n/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/\n#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)\n#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\n#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\n\n/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\n\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/\n#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)\n#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\n#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\n#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)\n#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\n#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */\n\n#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)\n#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\n#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */\n#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)\n#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\n#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */\n\n#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)\n#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */\n#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\n#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)\n#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\n#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */\n\n/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DEACHINT register  ********************/\n#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)\n#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */\n#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)\n#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */\n\n/********************  Bit definition for USB_OTG_GCCFG register  ********************/\n#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)\n#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\n#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */\n#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)\n#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< USB VBUS Detection Enable */\n\n/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\n\n/********************  Bit definition for USB_OTG_CID register  ********************/\n#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)\n#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */\n\n/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/\n#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)\n#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */\n#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */\n#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)\n#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */\n#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */\n#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)\n#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */\n#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */\n#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)\n#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */\n#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */\n#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)\n#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */\n#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)\n#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */\n#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */\n#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)\n#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */\n#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */\n#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)\n#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */\n#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */\n#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)\n#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */\n#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)\n#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */\n#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */\n#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)\n#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */\n#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)\n#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */\n#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */\n#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)\n#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */\n#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */\n#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)\n#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */\n#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */\n\n/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */\n#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPRT register  ********************/\n#define USB_OTG_HPRT_PCSTS_Pos                   (0U)\n#define USB_OTG_HPRT_PCSTS_Msk                   (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */\n#define USB_OTG_HPRT_PCDET_Pos                   (1U)\n#define USB_OTG_HPRT_PCDET_Msk                   (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\n#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */\n#define USB_OTG_HPRT_PENA_Pos                    (2U)\n#define USB_OTG_HPRT_PENA_Msk                    (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\n#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */\n#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)\n#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\n#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */\n#define USB_OTG_HPRT_POCA_Pos                    (4U)\n#define USB_OTG_HPRT_POCA_Msk                    (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\n#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */\n#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)\n#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\n#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */\n#define USB_OTG_HPRT_PRES_Pos                    (6U)\n#define USB_OTG_HPRT_PRES_Msk                    (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\n#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */\n#define USB_OTG_HPRT_PSUSP_Pos                   (7U)\n#define USB_OTG_HPRT_PSUSP_Msk                   (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\n#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */\n#define USB_OTG_HPRT_PRST_Pos                    (8U)\n#define USB_OTG_HPRT_PRST_Msk                    (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\n#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */\n\n#define USB_OTG_HPRT_PLSTS_Pos                   (10U)\n#define USB_OTG_HPRT_PLSTS_Msk                   (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\n#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */\n#define USB_OTG_HPRT_PLSTS_0                     (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\n#define USB_OTG_HPRT_PLSTS_1                     (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_HPRT_PPWR_Pos                    (12U)\n#define USB_OTG_HPRT_PPWR_Msk                    (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */\n\n#define USB_OTG_HPRT_PTCTL_Pos                   (13U)\n#define USB_OTG_HPRT_PTCTL_Msk                   (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\n#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */\n#define USB_OTG_HPRT_PTCTL_0                     (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\n#define USB_OTG_HPRT_PTCTL_1                     (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\n#define USB_OTG_HPRT_PTCTL_2                     (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\n#define USB_OTG_HPRT_PTCTL_3                     (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\n\n#define USB_OTG_HPRT_PSPD_Pos                    (17U)\n#define USB_OTG_HPRT_PSPD_Msk                    (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\n#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */\n#define USB_OTG_HPRT_PSPD_0                      (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPRT_PSPD_1                      (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\n\n/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */\n#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */\n#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */\n#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)\n#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */\n#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)\n#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */\n\n/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/\n#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)\n#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */\n#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)\n#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */\n\n/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/\n#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */\n#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */\n#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)\n#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\n#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */\n#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */\n\n#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */\n#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DIEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DIEPCTL_STALL_Msk                (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */\n\n#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)\n#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\n#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */\n#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\n#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\n#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\n#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\n#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */\n#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */\n#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */\n#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */\n#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */\n\n/********************  Bit definition for USB_OTG_HCCHAR register  ********************/\n#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)\n#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */\n\n#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)\n#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\n#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */\n#define USB_OTG_HCCHAR_EPNUM_0                   (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCCHAR_EPNUM_1                   (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCCHAR_EPNUM_2                   (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\n#define USB_OTG_HCCHAR_EPNUM_3                   (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)\n#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */\n#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)\n#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */\n\n#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)\n#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */\n#define USB_OTG_HCCHAR_EPTYP_0                   (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_HCCHAR_EPTYP_1                   (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\n\n#define USB_OTG_HCCHAR_MC_Pos                    (20U)\n#define USB_OTG_HCCHAR_MC_Msk                    (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\n#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */\n#define USB_OTG_HCCHAR_MC_0                      (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\n#define USB_OTG_HCCHAR_MC_1                      (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\n\n#define USB_OTG_HCCHAR_DAD_Pos                   (22U)\n#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\n#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */\n#define USB_OTG_HCCHAR_DAD_0                     (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\n#define USB_OTG_HCCHAR_DAD_1                     (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\n#define USB_OTG_HCCHAR_DAD_2                     (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\n#define USB_OTG_HCCHAR_DAD_3                     (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\n#define USB_OTG_HCCHAR_DAD_4                     (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\n#define USB_OTG_HCCHAR_DAD_5                     (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\n#define USB_OTG_HCCHAR_DAD_6                     (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\n#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)\n#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */\n#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)\n#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */\n#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)\n#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */\n\n/********************  Bit definition for USB_OTG_HCSPLT register  ********************/\n\n#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)\n#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\n#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */\n#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\n\n#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)\n#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\n#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */\n#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\n\n#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)\n#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\n#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */\n#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)\n#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\n#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */\n#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)\n#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */\n\n/********************  Bit definition for USB_OTG_HCINT register  ********************/\n#define USB_OTG_HCINT_XFRC_Pos                   (0U)\n#define USB_OTG_HCINT_XFRC_Msk                   (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */\n#define USB_OTG_HCINT_CHH_Pos                    (1U)\n#define USB_OTG_HCINT_CHH_Msk                    (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */\n#define USB_OTG_HCINT_AHBERR_Pos                 (2U)\n#define USB_OTG_HCINT_AHBERR_Msk                 (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */\n#define USB_OTG_HCINT_STALL_Pos                  (3U)\n#define USB_OTG_HCINT_STALL_Msk                  (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */\n#define USB_OTG_HCINT_NAK_Pos                    (4U)\n#define USB_OTG_HCINT_NAK_Msk                    (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */\n#define USB_OTG_HCINT_ACK_Pos                    (5U)\n#define USB_OTG_HCINT_ACK_Msk                    (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */\n#define USB_OTG_HCINT_NYET_Pos                   (6U)\n#define USB_OTG_HCINT_NYET_Msk                   (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */\n#define USB_OTG_HCINT_TXERR_Pos                  (7U)\n#define USB_OTG_HCINT_TXERR_Msk                  (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */\n#define USB_OTG_HCINT_BBERR_Pos                  (8U)\n#define USB_OTG_HCINT_BBERR_Msk                  (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */\n#define USB_OTG_HCINT_FRMOR_Pos                  (9U)\n#define USB_OTG_HCINT_FRMOR_Msk                  (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */\n#define USB_OTG_HCINT_DTERR_Pos                  (10U)\n#define USB_OTG_HCINT_DTERR_Msk                  (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */\n\n/********************  Bit definition for USB_OTG_DIEPINT register  ********************/\n#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DIEPINT_TOC_Pos                  (3U)\n#define USB_OTG_DIEPINT_TOC_Msk                  (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */\n#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)\n#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */\n#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)\n#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */\n#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)\n#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\n#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\n#define USB_OTG_DIEPINT_BNA_Pos                  (9U)\n#define USB_OTG_DIEPINT_BNA_Msk                  (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */\n#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)\n#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\n#define USB_OTG_DIEPINT_BERR_Pos                 (12U)\n#define USB_OTG_DIEPINT_BERR_Msk                 (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\n#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */\n#define USB_OTG_DIEPINT_NAK_Pos                  (13U)\n#define USB_OTG_DIEPINT_NAK_Msk                  (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */\n\n/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/\n#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)\n#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */\n#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)\n#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */\n#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)\n#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */\n#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)\n#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */\n#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)\n#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */\n#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)\n#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */\n#define USB_OTG_HCINTMSK_NYET_Pos                (6U)\n#define USB_OTG_HCINTMSK_NYET_Msk                (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */\n#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)\n#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */\n#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)\n#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */\n#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)\n#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */\n#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)\n#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */\n\n/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/\n\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)\n#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */\n/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/\n#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)\n#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */\n#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)\n#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */\n#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)\n#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */\n#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)\n#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\n#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */\n#define USB_OTG_HCTSIZ_DPID_0                    (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCTSIZ_DPID_1                    (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/\n#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)\n#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_HCDMA register  ********************/\n#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)\n#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/\n#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)\n#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */\n\n/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/\n#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)\n#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */\n#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)\n#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/\n\n#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */\n#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */\n#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\n#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */\n#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */\n#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)\n#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\n#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */\n#define USB_OTG_DOEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DOEPCTL_STALL_Msk                (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */\n#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */\n#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */\n#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */\n\n/********************  Bit definition for USB_OTG_DOEPINT register  ********************/\n#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DOEPINT_STUP_Pos                 (3U)\n#define USB_OTG_DOEPINT_STUP_Msk                 (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */\n#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)\n#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */\n#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)\n#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */\n#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */\n#define USB_OTG_DOEPINT_NYET_Pos                 (14U)\n#define USB_OTG_DOEPINT_NYET_Msk                 (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */\n\n/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/\n\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n\n#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)\n#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */\n#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for PCGCCTL register  ********************/\n#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)\n#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */\n#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)\n#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */\n#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)\n#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_macros\n  * @{\n  */\n\n/******************************* ADC Instances ********************************/\n#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \\\n                                       ((INSTANCE) == ADC2) || \\\n                                       ((INSTANCE) == ADC3))\n\n#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\n\n#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)\n\n/******************************* CAN Instances ********************************/\n#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \\\n                                       ((INSTANCE) == CAN2))\n/******************************* CRC Instances ********************************/\n#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\n\n/******************************* DAC Instances ********************************/\n#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)\n\n/******************************* DCMI Instances *******************************/\n#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)\n\n/******************************* DMA2D Instances *******************************/\n#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)\n\n/******************************** DMA Instances *******************************/\n#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \\\n                                              ((INSTANCE) == DMA1_Stream1) || \\\n                                              ((INSTANCE) == DMA1_Stream2) || \\\n                                              ((INSTANCE) == DMA1_Stream3) || \\\n                                              ((INSTANCE) == DMA1_Stream4) || \\\n                                              ((INSTANCE) == DMA1_Stream5) || \\\n                                              ((INSTANCE) == DMA1_Stream6) || \\\n                                              ((INSTANCE) == DMA1_Stream7) || \\\n                                              ((INSTANCE) == DMA2_Stream0) || \\\n                                              ((INSTANCE) == DMA2_Stream1) || \\\n                                              ((INSTANCE) == DMA2_Stream2) || \\\n                                              ((INSTANCE) == DMA2_Stream3) || \\\n                                              ((INSTANCE) == DMA2_Stream4) || \\\n                                              ((INSTANCE) == DMA2_Stream5) || \\\n                                              ((INSTANCE) == DMA2_Stream6) || \\\n                                              ((INSTANCE) == DMA2_Stream7))\n\n/******************************* GPIO Instances *******************************/\n#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\\n                                        ((INSTANCE) == GPIOB) || \\\n                                        ((INSTANCE) == GPIOC) || \\\n                                        ((INSTANCE) == GPIOD) || \\\n                                        ((INSTANCE) == GPIOE) || \\\n                                        ((INSTANCE) == GPIOF) || \\\n                                        ((INSTANCE) == GPIOG) || \\\n                                        ((INSTANCE) == GPIOH) || \\\n                                        ((INSTANCE) == GPIOI) || \\\n                                        ((INSTANCE) == GPIOJ) || \\\n                                        ((INSTANCE) == GPIOK))\n\n/******************************** I2C Instances *******************************/\n#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\n                                       ((INSTANCE) == I2C2) || \\\n                                       ((INSTANCE) == I2C3))\n\n/******************************* SMBUS Instances ******************************/\n#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE\n\n/******************************** I2S Instances *******************************/\n\n#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \\\n                                       ((INSTANCE) == SPI3))\n\n/*************************** I2S Extended Instances ***************************/\n#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \\\n                                           ((INSTANCE) == I2S3ext))\n/* Legacy Defines */\n#define IS_I2S_ALL_INSTANCE_EXT    IS_I2S_EXT_ALL_INSTANCE\n\n/****************************** LTDC Instances ********************************/\n#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)\n/******************************* RNG Instances ********************************/\n#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)\n\n/****************************** RTC Instances *********************************/\n#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\n\n/******************************* SAI Instances ********************************/\n#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \\\n                                     ((PERIPH) == SAI1_Block_B))\n/* Legacy define */\n\n#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE\n\n/******************************** SPI Instances *******************************/\n#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1)  || \\\n                                       ((INSTANCE) == SPI2)  || \\\n                                       ((INSTANCE) == SPI3)  || \\\n                                       ((INSTANCE) == SPI4)  || \\\n                                       ((INSTANCE) == SPI5)  || \\\n                                       ((INSTANCE) == SPI6))\n\n\n/****************** TIM Instances : All supported instances *******************/\n#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                    ((INSTANCE) == TIM2) || \\\n                                    ((INSTANCE) == TIM3) || \\\n                                    ((INSTANCE) == TIM4) || \\\n                                    ((INSTANCE) == TIM5) || \\\n                                    ((INSTANCE) == TIM6) || \\\n                                    ((INSTANCE) == TIM7) || \\\n                                    ((INSTANCE) == TIM8) || \\\n                                    ((INSTANCE) == TIM9) || \\\n                                    ((INSTANCE) == TIM10)|| \\\n                                    ((INSTANCE) == TIM11)|| \\\n                                    ((INSTANCE) == TIM12)|| \\\n                                    ((INSTANCE) == TIM13)|| \\\n                                    ((INSTANCE) == TIM14))\n\n/************* TIM Instances : at least 1 capture/compare channel *************/\n#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \\\n                                         ((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM3)  || \\\n                                         ((INSTANCE) == TIM4)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM8)  || \\\n                                         ((INSTANCE) == TIM9)  || \\\n                                         ((INSTANCE) == TIM10) || \\\n                                         ((INSTANCE) == TIM11) || \\\n                                         ((INSTANCE) == TIM12) || \\\n                                         ((INSTANCE) == TIM13) || \\\n                                         ((INSTANCE) == TIM14))\n\n/************ TIM Instances : at least 2 capture/compare channels *************/\n#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8) || \\\n                                       ((INSTANCE) == TIM9) || \\\n                                       ((INSTANCE) == TIM12))\n\n/************ TIM Instances : at least 3 capture/compare channels *************/\n#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/************ TIM Instances : at least 4 capture/compare channels *************/\n#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : Advanced-control timers *****************/\n#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                           ((INSTANCE) == TIM8))\n\n/******************* TIM Instances : Timer input XOR function *****************/\n#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : DMA requests generation (UDE) *************/\n#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM6) || \\\n                                       ((INSTANCE) == TIM7) || \\\n                                       ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (CCxDE) *****************/\n#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (COMDE) *****************/\n#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : DMA burst feature ***********************/\n#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                             ((INSTANCE) == TIM2) || \\\n                                             ((INSTANCE) == TIM3) || \\\n                                             ((INSTANCE) == TIM4) || \\\n                                             ((INSTANCE) == TIM5) || \\\n                                             ((INSTANCE) == TIM8))\n\n/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\n#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                          ((INSTANCE) == TIM2)  || \\\n                                          ((INSTANCE) == TIM3)  || \\\n                                          ((INSTANCE) == TIM4)  || \\\n                                          ((INSTANCE) == TIM5)  || \\\n                                          ((INSTANCE) == TIM6)  || \\\n                                          ((INSTANCE) == TIM7)  || \\\n                                          ((INSTANCE) == TIM8))\n\n/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\n#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8) || \\\n                                         ((INSTANCE) == TIM9) || \\\n                                         ((INSTANCE) == TIM12))\n\n/********************** TIM Instances : 32 bit Counter ************************/\n#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \\\n                                              ((INSTANCE) == TIM5))\n\n/***************** TIM Instances : external trigger input availabe ************/\n#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                        ((INSTANCE) == TIM2) || \\\n                                        ((INSTANCE) == TIM3) || \\\n                                        ((INSTANCE) == TIM4) || \\\n                                        ((INSTANCE) == TIM5) || \\\n                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : remapping capability **********************/\n#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM11))\n\n/******************* TIM Instances : output(s) available **********************/\n#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\\n    ((((INSTANCE) == TIM1) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM2) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM3) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM4) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM5) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM8) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM9) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM10) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM11) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM12) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM13) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM14) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1))))\n\n/************ TIM Instances : complementary output(s) available ***************/\n#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\\n   ((((INSTANCE) == TIM1) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3)))            \\\n    ||                                          \\\n    (((INSTANCE) == TIM8) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3))))\n\n/****************** TIM Instances : supporting counting mode selection ********/\n#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting clock division *****************/\n#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                                  ((INSTANCE) == TIM2) || \\\n                                                  ((INSTANCE) == TIM3) || \\\n                                                  ((INSTANCE) == TIM4) || \\\n                                                  ((INSTANCE) == TIM5) || \\\n                                                  ((INSTANCE) == TIM8) || \\\n                                                  ((INSTANCE) == TIM9) || \\\n                                                  ((INSTANCE) == TIM10)|| \\\n                                                  ((INSTANCE) == TIM11)|| \\\n                                                  ((INSTANCE) == TIM12)|| \\\n                                                  ((INSTANCE) == TIM13)|| \\\n                                                  ((INSTANCE) == TIM14))\n\n/****************** TIM Instances : supporting commutation event generation ***/\n#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \\\n                                                     ((INSTANCE) == TIM8))\n\n\n/****************** TIM Instances : supporting OCxREF clear *******************/\n#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM2) || \\\n                                                       ((INSTANCE) == TIM3) || \\\n                                                       ((INSTANCE) == TIM4) || \\\n                                                       ((INSTANCE) == TIM5) || \\\n                                                       ((INSTANCE) == TIM8))\n\n/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting repetition counter *************/\n#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting encoder interface **************/\n#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                      ((INSTANCE) == TIM2) || \\\n                                                      ((INSTANCE) == TIM3) || \\\n                                                      ((INSTANCE) == TIM4) || \\\n                                                      ((INSTANCE) == TIM5) || \\\n                                                      ((INSTANCE) == TIM8) || \\\n                                                      ((INSTANCE) == TIM9) || \\\n                                                      ((INSTANCE) == TIM12))\n/****************** TIM Instances : supporting Hall sensor interface **********/\n#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                          ((INSTANCE) == TIM2) || \\\n                                                          ((INSTANCE) == TIM3) || \\\n                                                          ((INSTANCE) == TIM4) || \\\n                                                          ((INSTANCE) == TIM5) || \\\n                                                          ((INSTANCE) == TIM8))\n/****************** TIM Instances : supporting the break function *************/\n#define IS_TIM_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM8))\n\n/******************** USART Instances : Synchronous mode **********************/\n#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                     ((INSTANCE) == USART2) || \\\n                                     ((INSTANCE) == USART3) || \\\n                                     ((INSTANCE) == USART6))\n\n/******************** UART Instances : Half-Duplex mode **********************/\n#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                               ((INSTANCE) == USART2) || \\\n                                               ((INSTANCE) == USART3) || \\\n                                               ((INSTANCE) == UART4)  || \\\n                                               ((INSTANCE) == UART5)  || \\\n                                               ((INSTANCE) == USART6) || \\\n                                               ((INSTANCE) == UART7)  || \\\n                                               ((INSTANCE) == UART8))\n\n/* Legacy defines */\n#define IS_UART_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE\n\n/****************** UART Instances : Hardware Flow control ********************/\n#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                           ((INSTANCE) == USART2) || \\\n                                           ((INSTANCE) == USART3) || \\\n                                           ((INSTANCE) == USART6))\n/******************** UART Instances : LIN mode **********************/\n#define IS_UART_LIN_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE\n\n/********************* UART Instances : Smart card mode ***********************/\n#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                         ((INSTANCE) == USART2) || \\\n                                         ((INSTANCE) == USART3) || \\\n                                         ((INSTANCE) == USART6))\n\n/*********************** UART Instances : IRDA mode ***************************/\n#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2) || \\\n                                    ((INSTANCE) == USART3) || \\\n                                    ((INSTANCE) == UART4)  || \\\n                                    ((INSTANCE) == UART5)  || \\\n                                    ((INSTANCE) == USART6) || \\\n                                    ((INSTANCE) == UART7)  || \\\n                                    ((INSTANCE) == UART8))\n\n/*********************** PCD Instances ****************************************/\n#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\\n                                       ((INSTANCE) == USB_OTG_HS))\n\n/*********************** HCD Instances ****************************************/\n#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\\n                                       ((INSTANCE) == USB_OTG_HS))\n\n/****************************** SDIO Instances ********************************/\n#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)\n\n/****************************** IWDG Instances ********************************/\n#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)\n\n/****************************** WWDG Instances ********************************/\n#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)\n\n\n/****************************** QSPI Instances ********************************/\n#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)\n/****************************** USB Exported Constants ************************/\n#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                12U\n#define USB_OTG_FS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */\n#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */\n#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */\n#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                16U\n#define USB_OTG_HS_MAX_IN_ENDPOINTS                    8U    /* Including EP0 */\n#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   8U    /* Including EP0 */\n#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */\n\n/*\n * @brief Specific devices reset values definitions\n */\n#define RCC_PLLCFGR_RST_VALUE              0x24003010U\n#define RCC_PLLI2SCFGR_RST_VALUE           0x24003000U\n#define RCC_PLLSAICFGR_RST_VALUE           0x24003000U\n\n#define RCC_MAX_FREQUENCY           180000000U         /*!< Max frequency of family in Hz*/\n#define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */\n#define RCC_MAX_FREQUENCY_SCALE2    168000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */\n#define RCC_MAX_FREQUENCY_SCALE3    120000000U         /*!< Maximum frequency for system clock at power scale3, in Hz */\n#define RCC_PLLVCO_OUTPUT_MIN       192000000U       /*!< Frequency min for PLLVCO output, in Hz */\n#define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */\n\n#define RCC_PLLN_MIN_VALUE                 50U\n#define RCC_PLLN_MAX_VALUE                432U\n\n#define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */\n#define FLASH_SCALE1_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */\n#define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */\n#define FLASH_SCALE1_LATENCY4_FREQ   120000000U     /*!< HCLK frequency to set FLASH latency 4 in power scale 1  */\n#define FLASH_SCALE1_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */\n\n#define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */\n#define FLASH_SCALE2_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */\n#define FLASH_SCALE2_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */\n#define FLASH_SCALE2_LATENCY4_FREQ   12000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 2  */\n#define FLASH_SCALE2_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 2  */\n\n#define FLASH_SCALE3_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */\n#define FLASH_SCALE3_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */\n#define FLASH_SCALE3_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 3  */\n\n/******************************************************************************/\n/*  For a painless codes migration between the STM32F4xx device product       */\n/*  lines, the aliases defined below are put in place to overcome the         */\n/*  differences in the interrupt handlers and IRQn definitions.               */\n/*  No need to update developed interrupt code when moving across             */\n/*  product lines within the same STM32F4 Family                              */\n/******************************************************************************/\n/* Aliases for __IRQn */\n#define FSMC_IRQn              FMC_IRQn\n\n/* Aliases for __IRQHandler */\n#define FSMC_IRQHandler        FMC_IRQHandler\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32F469xx_H */\n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx.h\n  * @author  MCD Application Team\n  * @version V2.6.3\n  * @date    08-February-2019\n  * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.\n  *\n  *          The file is the unique include file that the application programmer\n  *          is using in the C source code, usually in main.c. This file contains:\n  *           - Configuration section that allows to select:\n  *              - The STM32F4xx device used in the target application\n  *              - To use or not the peripheral's drivers in application code(i.e.\n  *                code will be based on direct access to peripheral's registers\n  *                rather than drivers API), this option is controlled by\n  *                \"#define USE_HAL_DRIVER\"\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32f4xx\n  * @{\n  */\n\n#ifndef __STM32F4xx_H\n#define __STM32F4xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Library_configuration_section\n  * @{\n  */\n\n/**\n  * @brief STM32 Family\n  */\n#if !defined  (STM32F4)\n#define STM32F4\n#endif /* STM32F4 */\n\n/* Uncomment the line below according to the target STM32 device used in your\n   application\n  */\n#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \\\n    !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \\\n    !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \\\n    !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \\\n    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \\\n    !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)\n  /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */\n  /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */\n  /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */\n  /* #define STM32F417xx */   /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */\n  /* #define STM32F427xx */   /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */\n  /* #define STM32F437xx */   /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */\n  /* #define STM32F429xx */   /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,\n                                   STM32F439NI, STM32F429IG  and STM32F429II Devices */\n  /* #define STM32F439xx */   /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,\n                                   STM32F439NI, STM32F439IG and STM32F439II Devices */\n  /* #define STM32F401xC */   /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */\n  /* #define STM32F401xE */   /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */\n  /* #define STM32F410Tx */   /*!< STM32F410T8 and STM32F410TB Devices */\n  /* #define STM32F410Cx */   /*!< STM32F410C8 and STM32F410CB Devices */\n  /* #define STM32F410Rx */   /*!< STM32F410R8 and STM32F410RB Devices */\n  /* #define STM32F411xE */   /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */\n  /* #define STM32F446xx */   /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,\n                                   and STM32F446ZE Devices */\n  /* #define STM32F469xx */   /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,\n                                   STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */\n  /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG\n                                   and STM32F479NG Devices */\n  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */\n  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */\n  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */\n  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */\n  /* #define STM32F413xx */   /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,\n                                   STM32F413RG, STM32F413VG and STM32F413ZG Devices */\n  /* #define STM32F423xx */   /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */\n#endif\n\n/*  Tip: To avoid modifying this file each time you need to switch between these\n        devices, you can define the device in your toolchain compiler preprocessor.\n  */\n#if !defined  (USE_HAL_DRIVER)\n/**\n * @brief Comment the line below if you will not use the peripherals drivers.\n   In this case, these drivers will not be included and the application code will\n   be based on direct access to peripherals registers\n   */\n  /*#define USE_HAL_DRIVER */\n#endif /* USE_HAL_DRIVER */\n\n/**\n  * @brief CMSIS version number V2.6.3\n  */\n#define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */\n#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x06U) /*!< [23:16] sub1 version */\n#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x03U) /*!< [15:8]  sub2 version */\n#define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */\n#define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\\\n                                         |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\\\n                                         |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\\\n                                         |(__STM32F4xx_CMSIS_VERSION))\n\n/**\n  * @}\n  */\n\n/** @addtogroup Device_Included\n  * @{\n  */\n\n#if defined(STM32F405xx)\n  #include \"stm32f405xx.h\"\n#elif defined(STM32F415xx)\n  #include \"stm32f415xx.h\"\n#elif defined(STM32F407xx)\n  #include \"stm32f407xx.h\"\n#elif defined(STM32F417xx)\n  #include \"stm32f417xx.h\"\n#elif defined(STM32F427xx)\n  #include \"stm32f427xx.h\"\n#elif defined(STM32F437xx)\n  #include \"stm32f437xx.h\"\n#elif defined(STM32F429xx)\n  #include \"stm32f429xx.h\"\n#elif defined(STM32F439xx)\n  #include \"stm32f439xx.h\"\n#elif defined(STM32F401xC)\n  #include \"stm32f401xc.h\"\n#elif defined(STM32F401xE)\n  #include \"stm32f401xe.h\"\n#elif defined(STM32F410Tx)\n  #include \"stm32f410tx.h\"\n#elif defined(STM32F410Cx)\n  #include \"stm32f410cx.h\"\n#elif defined(STM32F410Rx)\n  #include \"stm32f410rx.h\"\n#elif defined(STM32F411xE)\n  #include \"stm32f411xe.h\"\n#elif defined(STM32F446xx)\n  #include \"stm32f446xx.h\"\n#elif defined(STM32F469xx)\n  #include \"stm32f469xx.h\"\n#elif defined(STM32F479xx)\n  #include \"stm32f479xx.h\"\n#elif defined(STM32F412Cx)\n  #include \"stm32f412cx.h\"\n#elif defined(STM32F412Zx)\n  #include \"stm32f412zx.h\"\n#elif defined(STM32F412Rx)\n  #include \"stm32f412rx.h\"\n#elif defined(STM32F412Vx)\n  #include \"stm32f412vx.h\"\n#elif defined(STM32F413xx)\n  #include \"stm32f413xx.h\"\n#elif defined(STM32F423xx)\n  #include \"stm32f423xx.h\"\n#else\n #error \"Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)\"\n#endif\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_types\n  * @{\n  */\ntypedef enum\n{\n  RESET = 0U,\n  SET = !RESET\n} FlagStatus, ITStatus;\n\ntypedef enum\n{\n  DISABLE = 0U,\n  ENABLE = !DISABLE\n} FunctionalState;\n#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\n\ntypedef enum\n{\n  SUCCESS = 0U,\n  ERROR = !SUCCESS\n} ErrorStatus;\n\n/**\n  * @}\n  */\n\n\n/** @addtogroup Exported_macro\n  * @{\n  */\n#define SET_BIT(REG, BIT)     ((REG) |= (BIT))\n\n#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))\n\n#define READ_BIT(REG, BIT)    ((REG) & (BIT))\n\n#define CLEAR_REG(REG)        ((REG) = (0x0))\n\n#define WRITE_REG(REG, VAL)   ((REG) = (VAL))\n\n#define READ_REG(REG)         ((REG))\n\n#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\n\n#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))\n\n\n/**\n  * @}\n  */\n\n#if defined (USE_HAL_DRIVER)\n #include \"stm32f4xx_hal.h\"\n#endif /* USE_HAL_DRIVER */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32F4xx_H */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_hal.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal.c\n  * @author  MCD Application Team\n  * @version V1.7.1\n  * @date    14-April-2017\n  * @brief   HAL module driver.\n  *          This is the common part of the HAL initialization\n  *\n  @verbatim\n  ==============================================================================\n                     ##### How to use this driver #####\n  ==============================================================================\n    [..]\n    The common HAL driver contains a set of generic and common APIs that can be\n    used by the PPP peripheral drivers and the user to start using the HAL.\n    [..]\n    The HAL contains two APIs' categories:\n         (+) Common HAL APIs\n         (+) Services HAL APIs\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n#include \"stm32f4xx_ll_system.h\" // XXX For LL_FLASH_* functions.\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup HAL HAL\n  * @brief HAL module driver.\n  * @{\n  */\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/** @addtogroup HAL_Private_Constants\n  * @{\n  */\n/**\n  * @brief STM32F4xx HAL Driver version number V1.7.1\n  */\n#define __STM32F4xx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */\n#define __STM32F4xx_HAL_VERSION_SUB1   (0x07U) /*!< [23:16] sub1 version */\n#define __STM32F4xx_HAL_VERSION_SUB2   (0x01U) /*!< [15:8]  sub2 version */\n#define __STM32F4xx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */\n#define __STM32F4xx_HAL_VERSION         ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\\\n                                        |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\\\n                                        |(__STM32F4xx_HAL_VERSION_SUB2 << 8U )\\\n                                        |(__STM32F4xx_HAL_VERSION_RC))\n\n#define IDCODE_DEVID_MASK    0x00000FFFU\n\n/* ------------ RCC registers bit address in the alias region ----------- */\n#define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)\n/* ---  MEMRMP Register ---*/\n/* Alias word address of UFB_MODE bit */\n#define MEMRMP_OFFSET             SYSCFG_OFFSET\n#define UFB_MODE_BIT_NUMBER       POSITION_VAL(SYSCFG_MEMRMP_UFB_MODE)\n#define UFB_MODE_BB               (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U))\n\n/* ---  CMPCR Register ---*/\n/* Alias word address of CMP_PD bit */\n#define CMPCR_OFFSET              (SYSCFG_OFFSET + 0x20U)\n#define CMP_PD_BIT_NUMBER         POSITION_VAL(SYSCFG_CMPCR_CMP_PD)\n#define CMPCR_CMP_PD_BB           (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U))\n\n/* ---  MCHDLYCR Register ---*/\n/* Alias word address of BSCKSEL bit */\n#define MCHDLYCR_OFFSET            (SYSCFG_OFFSET + 0x30U)\n#define BSCKSEL_BIT_NUMBER         POSITION_VAL(SYSCFG_MCHDLYCR_BSCKSEL)\n#define MCHDLYCR_BSCKSEL_BB        (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET * 32U) + (BSCKSEL_BIT_NUMBER * 4U))\n/**\n  * @}\n  */\n\n/* Private macro -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/** @addtogroup HAL_Private_Variables\n  * @{\n  */\n__IO uint32_t uwTick;\n/**\n  * @}\n  */\n/* Private function prototypes -----------------------------------------------*/\n/* Private functions ---------------------------------------------------------*/\n\n/** @defgroup HAL_Exported_Functions HAL Exported Functions\n  * @{\n  */\n\n/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions\n *  @brief    Initialization and de-initialization functions\n *\n@verbatim\n ===============================================================================\n              ##### Initialization and de-initialization functions #####\n ===============================================================================\n    [..]  This section provides functions allowing to:\n      (+) Initializes the Flash interface the NVIC allocation and initial clock\n          configuration. It initializes the systick also when timeout is needed\n          and the backup domain when enabled.\n      (+) de-Initializes common part of the HAL\n      (+) Configure The time base source to have 1ms time base with a dedicated\n          Tick interrupt priority.\n        (++) Systick timer is used by default as source of time base, but user\n             can eventually implement his proper time base source (a general purpose\n             timer for example or other time source), keeping in mind that Time base\n             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and\n             handled in milliseconds basis.\n        (++) Time base configuration function (HAL_InitTick ()) is called automatically\n             at the beginning of the program after reset by HAL_Init() or at any time\n             when clock is configured, by HAL_RCC_ClockConfig().\n        (++) Source of time base is configured  to generate interrupts at regular\n             time intervals. Care must be taken if HAL_Delay() is called from a\n             peripheral ISR process, the Tick interrupt line must have higher priority\n            (numerically lower) than the peripheral interrupt. Otherwise the caller\n            ISR process will be blocked.\n       (++) functions affecting time base configurations are declared as __weak\n             to make  override possible  in case of other  implementations in user file.\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  This function is used to initialize the HAL Library; it must be the first\n  *         instruction to be executed in the main program (before to call any other\n  *         HAL function), it performs the following:\n  *           Configure the Flash prefetch, instruction and Data caches.\n  *           Configures the SysTick to generate an interrupt each 1 millisecond,\n  *           which is clocked by the HSI (at this stage, the clock is not yet\n  *           configured and thus the system is running from the internal HSI at 16 MHz).\n  *           Set NVIC Group Priority to 4.\n  *           Calls the HAL_MspInit() callback function defined in user file\n  *           \"stm32f4xx_hal_msp.c\" to do the global low level hardware initialization\n  *\n  * @note   SysTick is used as time base for the HAL_Delay() function, the application\n  *         need to ensure that the SysTick time base is always set to 1 millisecond\n  *         to have correct HAL operation.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_Init(void)\n{\n  /* Configure Flash prefetch, Instruction cache, Data cache */\n#if (INSTRUCTION_CACHE_ENABLE != 0U)\n  LL_FLASH_EnableInstCache();\n// XXX  __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();\n#endif /* INSTRUCTION_CACHE_ENABLE */\n\n#if (DATA_CACHE_ENABLE != 0U)\n  LL_FLASH_EnableDataCache();\n// XXX  __HAL_FLASH_DATA_CACHE_ENABLE();\n#endif /* DATA_CACHE_ENABLE */\n\n#if (PREFETCH_ENABLE != 0U)\n  LL_FLASH_EnablePrefetch();\n// XXX  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();\n#endif /* PREFETCH_ENABLE */\n\n#ifdef __thumb2__\n  /* Set Interrupt Group Priority */\n  NVIC_SetPriorityGrouping(0);\n// XXX  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);\n#endif\n\n  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */\n// XXX  HAL_InitTick(TICK_INT_PRIORITY);\n\n  /* Init the low level hardware */\n  HAL_MspInit();\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  This function de-Initializes common part of the HAL and stops the systick.\n  *         This function is optional.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_DeInit(void)\n{\n#if 0 // XXX to change to LL_RCC functions.\n  /* Reset of all peripherals */\n  __HAL_RCC_APB1_FORCE_RESET();\n  __HAL_RCC_APB1_RELEASE_RESET();\n\n  __HAL_RCC_APB2_FORCE_RESET();\n  __HAL_RCC_APB2_RELEASE_RESET();\n\n  __HAL_RCC_AHB1_FORCE_RESET();\n  __HAL_RCC_AHB1_RELEASE_RESET();\n\n  __HAL_RCC_AHB2_FORCE_RESET();\n  __HAL_RCC_AHB2_RELEASE_RESET();\n\n  __HAL_RCC_AHB3_FORCE_RESET();\n  __HAL_RCC_AHB3_RELEASE_RESET();\n#endif // XXX\n\n  /* De-Init the low level hardware */\n  HAL_MspDeInit();\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initializes the MSP.\n  * @retval None\n  */\n__weak void HAL_MspInit(void)\n{\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_MspInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  DeInitializes the MSP.\n  * @retval None\n  */\n__weak void HAL_MspDeInit(void)\n{\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_MspDeInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief This function configures the source of the time base.\n  *        The time source is configured  to have 1ms time base with a dedicated\n  *        Tick interrupt priority.\n  * @note This function is called  automatically at the beginning of program after\n  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().\n  * @note In the default implementation, SysTick timer is the source of time base.\n  *       It is used to generate interrupts at regular time intervals.\n  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,\n  *       The the SysTick interrupt must have higher priority (numerically lower)\n  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.\n  *       The function is declared as __weak  to be overwritten  in case of other\n  *       implementation  in user file.\n  * @param TickPriority: Tick interrupt priority.\n  * @retval HAL status\n  */\n__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)\n{\n  /*Configure the SysTick to have interrupt in 1ms time basis*/\n// XXX  HAL_SYSTICK_Config(SystemCoreClock/1000U);\n  SysTick_Config(SystemCoreClock/1000U);\n\n  /*Configure the SysTick IRQ priority */\n// XXX  HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);\n  NVIC_SetPriority(SysTick_IRQn, TickPriority);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions\n *  @brief    HAL Control functions\n *\n@verbatim\n ===============================================================================\n                      ##### HAL Control functions #####\n ===============================================================================\n    [..]  This section provides functions allowing to:\n      (+) Provide a tick value in millisecond\n      (+) Provide a blocking delay in millisecond\n      (+) Suspend the time base source interrupt\n      (+) Resume the time base source interrupt\n      (+) Get the HAL API driver version\n      (+) Get the device identifier\n      (+) Get the device revision identifier\n      (+) Enable/Disable Debug module during SLEEP mode\n      (+) Enable/Disable Debug module during STOP mode\n      (+) Enable/Disable Debug module during STANDBY mode\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief This function is called to increment  a global variable \"uwTick\"\n  *        used as application time base.\n  * @note In the default implementation, this variable is incremented each 1ms\n  *       in Systick ISR.\n * @note This function is declared as __weak to be overwritten in case of other\n  *      implementations in user file.\n  * @retval None\n  */\n__weak void HAL_IncTick(void)\n{\n  uwTick++;\n}\n\n/**\n  * @brief Provides a tick value in millisecond.\n  * @note This function is declared as __weak to be overwritten in case of other\n  *       implementations in user file.\n  * @retval tick value\n  */\n__weak uint32_t HAL_GetTick(void)\n{\n  return uwTick;\n}\n\n/**\n  * @brief This function provides minimum delay (in milliseconds) based\n  *        on variable incremented.\n  * @note In the default implementation , SysTick timer is the source of time base.\n  *       It is used to generate interrupts at regular time intervals where uwTick\n  *       is incremented.\n  * @note This function is declared as __weak to be overwritten in case of other\n  *       implementations in user file.\n  * @param Delay: specifies the delay time length, in milliseconds.\n  * @retval None\n  */\n__weak void HAL_Delay(__IO uint32_t Delay)\n{\n  uint32_t tickstart = HAL_GetTick();\n  uint32_t wait = Delay;\n\n  /* Add a period to guarantee minimum wait */\n  if (wait < HAL_MAX_DELAY)\n  {\n     wait++;\n  }\n\n  while((HAL_GetTick() - tickstart) < wait)\n  {\n  }\n}\n\n/**\n  * @brief Suspend Tick increment.\n  * @note In the default implementation , SysTick timer is the source of time base. It is\n  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()\n  *       is called, the SysTick interrupt will be disabled and so Tick increment\n  *       is suspended.\n  * @note This function is declared as __weak to be overwritten in case of other\n  *       implementations in user file.\n  * @retval None\n  */\n__weak void HAL_SuspendTick(void)\n{\n  /* Disable SysTick Interrupt */\n  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;\n}\n\n/**\n  * @brief Resume Tick increment.\n  * @note In the default implementation , SysTick timer is the source of time base. It is\n  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()\n  *       is called, the SysTick interrupt will be enabled and so Tick increment\n  *       is resumed.\n  * @note This function is declared as __weak to be overwritten in case of other\n  *       implementations in user file.\n  * @retval None\n  */\n__weak void HAL_ResumeTick(void)\n{\n  /* Enable SysTick Interrupt */\n  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;\n}\n\n/**\n  * @brief  Returns the HAL revision\n  * @retval version : 0xXYZR (8bits for each decimal, R for RC)\n  */\nuint32_t HAL_GetHalVersion(void)\n{\n return __STM32F4xx_HAL_VERSION;\n}\n\n/**\n  * @brief  Returns the device revision identifier.\n  * @retval Device revision identifier\n  */\nuint32_t HAL_GetREVID(void)\n{\n   return((DBGMCU->IDCODE) >> 16U);\n}\n\n/**\n  * @brief  Returns the device identifier.\n  * @retval Device identifier\n  */\nuint32_t HAL_GetDEVID(void)\n{\n   return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);\n}\n\n/**\n  * @brief  Enable the Debug Module during SLEEP mode\n  * @retval None\n  */\nvoid HAL_DBGMCU_EnableDBGSleepMode(void)\n{\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\n}\n\n/**\n  * @brief  Disable the Debug Module during SLEEP mode\n  * @retval None\n  */\nvoid HAL_DBGMCU_DisableDBGSleepMode(void)\n{\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\n}\n\n/**\n  * @brief  Enable the Debug Module during STOP mode\n  * @retval None\n  */\nvoid HAL_DBGMCU_EnableDBGStopMode(void)\n{\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\n}\n\n/**\n  * @brief  Disable the Debug Module during STOP mode\n  * @retval None\n  */\nvoid HAL_DBGMCU_DisableDBGStopMode(void)\n{\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\n}\n\n/**\n  * @brief  Enable the Debug Module during STANDBY mode\n  * @retval None\n  */\nvoid HAL_DBGMCU_EnableDBGStandbyMode(void)\n{\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\n}\n\n/**\n  * @brief  Disable the Debug Module during STANDBY mode\n  * @retval None\n  */\nvoid HAL_DBGMCU_DisableDBGStandbyMode(void)\n{\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\n}\n\n/**\n  * @brief  Enables the I/O Compensation Cell.\n  * @note   The I/O compensation cell can be used only when the device supply\n  *         voltage ranges from 2.4 to 3.6 V.\n  * @retval None\n  */\nvoid HAL_EnableCompensationCell(void)\n{\n  *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)ENABLE;\n}\n\n/**\n  * @brief  Power-down the I/O Compensation Cell.\n  * @note   The I/O compensation cell can be used only when the device supply\n  *         voltage ranges from 2.4 to 3.6 V.\n  * @retval None\n  */\nvoid HAL_DisableCompensationCell(void)\n{\n  *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE;\n}\n\n/**\n  * @brief Return the unique device identifier (UID based on 96 bits)\n  * @param UID: pointer to 3 words array.\n  * @retval Device identifier\n  */\nvoid HAL_GetUID(uint32_t *UID)\n{\n  UID[0] = (uint32_t)(READ_REG(*((uint32_t *)UID_BASE)));\n  UID[1] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 4U))));\n  UID[2] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 8U))));\n}\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx)\n/**\n  * @brief  Enables the Internal FLASH Bank Swapping.\n  *\n  * @note   This function can be used only for STM32F42xxx/43xxx devices.\n  *\n  * @note   Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)\n  *         and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)\n  *\n  * @retval None\n  */\nvoid HAL_EnableMemorySwappingBank(void)\n{\n  *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)ENABLE;\n}\n\n/**\n  * @brief  Disables the Internal FLASH Bank Swapping.\n  *\n  * @note   This function can be used only for STM32F42xxx/43xxx devices.\n  *\n  * @note   The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000)\n  *         and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)\n  *\n  * @retval None\n  */\nvoid HAL_DisableMemorySwappingBank(void)\n{\n\n  *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE;\n}\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_hal.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal.h\n  * @author  MCD Application Team\n  * @version V1.7.1\n  * @date    14-April-2017\n  * @brief   This file contains all the functions prototypes for the HAL\n  *          module driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_H\n#define __STM32F4xx_HAL_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_conf.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup HAL\n  * @{\n  */\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup HAL_Exported_Macros HAL Exported Macros\n  * @{\n  */\n\n/** @brief  Freeze/Unfreeze Peripherals in Debug mode\n  */\n#define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM4()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM5()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM12()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM13()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))\n#define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))\n#define __HAL_DBGMCU_FREEZE_WWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))\n#define __HAL_DBGMCU_FREEZE_IWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))\n#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))\n#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))\n#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))\n#define __HAL_DBGMCU_FREEZE_CAN1()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))\n#define __HAL_DBGMCU_FREEZE_CAN2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM8()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM9()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM10()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM11()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))\n\n#define __HAL_DBGMCU_UNFREEZE_TIM2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM3()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM4()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM5()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM6()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM7()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM12()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM13()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM14()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))\n#define __HAL_DBGMCU_UNFREEZE_RTC()            (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))\n#define __HAL_DBGMCU_UNFREEZE_WWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))\n#define __HAL_DBGMCU_UNFREEZE_IWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))\n#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))\n#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))\n#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))\n#define __HAL_DBGMCU_UNFREEZE_CAN1()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))\n#define __HAL_DBGMCU_UNFREEZE_CAN2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM1()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM8()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM9()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM10()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM11()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))\n\n/** @brief  Main Flash memory mapped at 0x00000000\n  */\n#define __HAL_SYSCFG_REMAPMEMORY_FLASH()             (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))\n\n/** @brief  System Flash memory mapped at 0x00000000\n  */\n#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\\\n                                                         SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\\\n                                                        }while(0);\n\n/** @brief  Embedded SRAM mapped at 0x00000000\n  */\n#define __HAL_SYSCFG_REMAPMEMORY_SRAM()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\\\n                                                  SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\\\n                                                 }while(0);\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\n/** @brief  FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000\n  */\n#define __HAL_SYSCFG_REMAPMEMORY_FSMC()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\\\n                                                  SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\\\n                                                 }while(0);\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx)\n/** @brief  FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000\n  */\n#define __HAL_SYSCFG_REMAPMEMORY_FMC()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\\\n                                                 SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\\\n                                                }while(0);\n\n/** @brief  FMC/SDRAM Bank 1 and 2 mapped at 0x00000000\n  */\n#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\\\n                                                       SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\\\n                                                      }while(0);\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)\n/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable\n  * @{\n  */\n/** @brief  SYSCFG Break Lockup lock\n  *         Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input\n  * @note   The selected configuration is locked and can be unlocked by system reset\n  */\n#define __HAL_SYSCFG_BREAK_PVD_LOCK()      do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \\\n                                               SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK;    \\\n                                              }while(0)\n/**\n * @}\n */\n\n/** @defgroup PVD_Lock_Enable PVD Lock\n  * @{\n  */\n/** @brief  SYSCFG Break PVD lock\n  *         Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register\n  * @note   The selected configuration is locked and can be unlocked by system reset\n  */\n#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \\\n                                                 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK;    \\\n                                                }while(0)\n/**\n * @}\n */\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup HAL_Exported_Functions\n  * @{\n  */\n/** @addtogroup HAL_Exported_Functions_Group1\n  * @{\n  */\n/* Initialization and de-initialization functions  ******************************/\nHAL_StatusTypeDef HAL_Init(void);\nHAL_StatusTypeDef HAL_DeInit(void);\nvoid HAL_MspInit(void);\nvoid HAL_MspDeInit(void);\nHAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);\n/**\n  * @}\n  */\n\n/** @addtogroup HAL_Exported_Functions_Group2\n  * @{\n  */\n/* Peripheral Control functions  ************************************************/\nvoid HAL_IncTick(void);\nvoid HAL_Delay(__IO uint32_t Delay);\nuint32_t HAL_GetTick(void);\nvoid HAL_SuspendTick(void);\nvoid HAL_ResumeTick(void);\nuint32_t HAL_GetHalVersion(void);\nuint32_t HAL_GetREVID(void);\nuint32_t HAL_GetDEVID(void);\nvoid HAL_DBGMCU_EnableDBGSleepMode(void);\nvoid HAL_DBGMCU_DisableDBGSleepMode(void);\nvoid HAL_DBGMCU_EnableDBGStopMode(void);\nvoid HAL_DBGMCU_DisableDBGStopMode(void);\nvoid HAL_DBGMCU_EnableDBGStandbyMode(void);\nvoid HAL_DBGMCU_DisableDBGStandbyMode(void);\nvoid HAL_EnableCompensationCell(void);\nvoid HAL_DisableCompensationCell(void);\nvoid HAL_GetUID(uint32_t *UID);\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx)\nvoid HAL_EnableMemorySwappingBank(void);\nvoid HAL_DisableMemorySwappingBank(void);\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/** @defgroup HAL_Private_Variables HAL Private Variables\n  * @{\n  */\n/**\n  * @}\n  */\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup HAL_Private_Constants HAL Private Constants\n  * @{\n  */\n/**\n  * @}\n  */\n/* Private macros ------------------------------------------------------------*/\n/* Private functions ---------------------------------------------------------*/\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_HAL_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_hal_conf.h",
    "content": "/**\n  ******************************************************************************\n  * @file    BSP/inc/stm32f4xx_hal_conf.h\n  * @author  MCD Application Team\n  * @version V1.1.0\n  * @date    17-February-2017\n  * @brief   HAL configuration file.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_CONF_H\n#define __STM32F4xx_HAL_CONF_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n\n/* ########################## Module Selection ############################## */\n/**\n  * @brief This is the list of modules to be used in the HAL driver\n  */\n\n#define HAL_MODULE_ENABLED\n#define HAL_SD_MODULE_ENABLED\n#define HAL_SPI_MODULE_ENABLED\n\n/* ########################## HSE/HSI Values adaptation ##################### */\n/**\n  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.\n  *        This value is used by the RCC HAL module to compute the system frequency\n  *        (when HSE is used as system clock source, directly or through the PLL).\n  */\n#if !defined  (HSE_VALUE)\n#if defined(USE_STM32469I_DISCO_REVA)\n  #define HSE_VALUE    (25000000U)  /*!< Default value of the External oscillator in Hz */\n#else\n  #define HSE_VALUE    (8000000U)   /*!< Default value of the External oscillator in Hz */\n#endif /* USE_STM32469I_DISCO_REVA */\n#endif /* HSE_VALUE */\n\n#if !defined  (HSE_STARTUP_TIMEOUT)\n  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */\n#endif /* HSE_STARTUP_TIMEOUT */\n\n/**\n  * @brief Internal High Speed oscillator (HSI) value.\n  *        This value is used by the RCC HAL module to compute the system frequency\n  *        (when HSI is used as system clock source, directly or through the PLL).\n  */\n#if !defined  (HSI_VALUE)\n  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/\n#endif /* HSI_VALUE */\n\n/**\n  * @brief Internal Low Speed oscillator (LSI) value.\n  */\n#if !defined  (LSI_VALUE)\n #define LSI_VALUE  (32000U)\n#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz\n                                             The real value may vary depending on the variations\n                                             in voltage and temperature.  */\n/**\n  * @brief External Low Speed oscillator (LSE) value.\n  */\n#if !defined  (LSE_VALUE)\n #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */\n#endif /* LSE_VALUE */\n\n#if !defined  (LSE_STARTUP_TIMEOUT)\n  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */\n#endif /* LSE_STARTUP_TIMEOUT */\n\n/**\n  * @brief External clock source for I2S peripheral\n  *        This value is used by the I2S HAL module to compute the I2S clock source\n  *        frequency, this source is inserted directly through I2S_CKIN pad.\n  */\n#if !defined  (EXTERNAL_CLOCK_VALUE)\n  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the external oscillator in Hz*/\n#endif /* EXTERNAL_CLOCK_VALUE */\n\n/* Tip: To avoid modifying this file each time you need to use different HSE,\n   ===  you can define the HSE value in your toolchain compiler preprocessor. */\n\n/* ########################### System Configuration ######################### */\n/**\n  * @brief This is the HAL system configuration section\n  */\n#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */\n#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */\n#define  USE_RTOS                     0\n#define  PREFETCH_ENABLE              1\n#define  INSTRUCTION_CACHE_ENABLE     1\n#define  DATA_CACHE_ENABLE            1\n\n/* ########################## Assert Selection ############################## */\n/**\n  * @brief Uncomment the line below to expanse the \"assert_param\" macro in the\n  *        HAL drivers code\n  */\n// XXX #define USE_FULL_ASSERT    0\n\n\n/* ################## SPI peripheral configuration ########################## */\n\n/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver\n* Activated: CRC code is present inside driver\n* Deactivated: CRC code cleaned from driver\n*/\n\n#define USE_SPI_CRC                     1U\n\n/* Includes ------------------------------------------------------------------*/\n/**\n  * @brief Include module's header file\n  */\n\n#ifdef HAL_SD_MODULE_ENABLED\n #include \"stm32f4xx_hal_sd.h\"\n#endif /* HAL_SD_MODULE_ENABLED */\n\n#ifdef HAL_SPI_MODULE_ENABLED\n #include \"stm32f4xx_hal_spi.h\"\n#endif /* HAL_SPI_MODULE_ENABLED */\n\n/* Exported macro ------------------------------------------------------------*/\n#ifdef  USE_FULL_ASSERT\n/**\n  * @brief  The assert_param macro is used for function's parameters check.\n  * @param  expr: If expr is false, it calls assert_failed function\n  *         which reports the name of the source file and the source\n  *         line number of the call that failed.\n  *         If expr is true, it returns no value.\n  * @retval None\n  */\n  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))\n/* Exported functions ------------------------------------------------------- */\n  void assert_failed(uint8_t* file, uint32_t line);\n#else\n  #define assert_param(expr) ((void)0U)\n#endif /* USE_FULL_ASSERT */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_HAL_CONF_H */\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_hal_def.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_def.h\n  * @author  MCD Application Team\n  * @version V1.7.1\n  * @date    14-April-2017\n  * @brief   This file contains HAL common defines, enumeration, macros and\n  *          structures definitions.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_DEF\n#define __STM32F4xx_HAL_DEF\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n#include <sys/param.h>\n\n/* Exported types ------------------------------------------------------------*/\n\n/**\n  * @brief  HAL Status structures definition\n  */\ntypedef enum\n{\n  HAL_OK       = 0x00U,\n  HAL_ERROR    = 0x01U,\n  HAL_BUSY     = 0x02U,\n  HAL_TIMEOUT  = 0x03U\n} HAL_StatusTypeDef;\n\n/**\n  * @brief  HAL Lock structures definition\n  */\ntypedef enum\n{\n  HAL_UNLOCKED = 0x00U,\n  HAL_LOCKED   = 0x01U\n} HAL_LockTypeDef;\n\n/* Exported macro ------------------------------------------------------------*/\n#define HAL_MAX_DELAY      0xFFFFFFFFU\n\n#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) != RESET)\n#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == RESET)\n\n#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \\\n                        do{                                                      \\\n                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \\\n                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \\\n                          } while(0)\n\n#define UNUSED(x) ((void)(x))\n\n/** @brief Reset the Handle's State field.\n  * @param __HANDLE__: specifies the Peripheral Handle.\n  * @note  This macro can be used for the following purpose:\n  *          - When the Handle is declared as local variable; before passing it as parameter\n  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro\n  *            to set to 0 the Handle's \"State\" field.\n  *            Otherwise, \"State\" field may have any random value and the first time the function\n  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed\n  *            (i.e. HAL_PPP_MspInit() will not be executed).\n  *          - When there is a need to reconfigure the low level hardware: instead of calling\n  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().\n  *            In this later function, when the Handle's \"State\" field is set to 0, it will execute the function\n  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.\n  * @retval None\n  */\n#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)\n\n#if (USE_RTOS == 1U)\n  /* Reserved for future use */\n  #error \"USE_RTOS should be 0 in the current HAL release\"\n#else\n  #define __HAL_LOCK(__HANDLE__)                                           \\\n                                do{                                        \\\n                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \\\n                                    {                                      \\\n                                       return HAL_BUSY;                    \\\n                                    }                                      \\\n                                    else                                   \\\n                                    {                                      \\\n                                       (__HANDLE__)->Lock = HAL_LOCKED;    \\\n                                    }                                      \\\n                                  }while (0U)\n\n  #define __HAL_UNLOCK(__HANDLE__)                                          \\\n                                  do{                                       \\\n                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \\\n                                    }while (0U)\n#endif /* USE_RTOS */\n\n#if  defined ( __GNUC__ )\n  #ifndef __weak\n    #define __weak   __attribute__((weak))\n  #endif /* __weak */\n  #ifndef __packed\n    #define __packed __attribute__((__packed__))\n  #endif /* __packed */\n#endif /* __GNUC__ */\n\n\n/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive \"#pragma data_alignment=4\" must be used instead */\n#if defined   (__GNUC__)        /* GNU Compiler */\n  #ifndef __ALIGN_END\n    #define __ALIGN_END    __attribute__ ((aligned (4)))\n  #endif /* __ALIGN_END */\n  #ifndef __ALIGN_BEGIN\n    #define __ALIGN_BEGIN\n  #endif /* __ALIGN_BEGIN */\n#else\n  #ifndef __ALIGN_END\n    #define __ALIGN_END\n  #endif /* __ALIGN_END */\n  #ifndef __ALIGN_BEGIN\n    #if defined   (__CC_ARM)      /* ARM Compiler */\n      #define __ALIGN_BEGIN    __align(4)\n    #elif defined (__ICCARM__)    /* IAR Compiler */\n      #define __ALIGN_BEGIN\n    #endif /* __CC_ARM */\n  #endif /* __ALIGN_BEGIN */\n#endif /* __GNUC__ */\n\n\n/**\n  * @brief  __RAM_FUNC definition\n  */\n#if defined ( __CC_ARM   )\n/* ARM Compiler\n   ------------\n   RAM functions are defined using the toolchain options.\n   Functions that are executed in RAM should reside in a separate source module.\n   Using the 'Options for File' dialog you can simply change the 'Code / Const'\n   area of a module to a memory space in physical RAM.\n   Available memory areas are declared in the 'Target' tab of the 'Options for Target'\n   dialog.\n*/\n#define __RAM_FUNC HAL_StatusTypeDef\n\n#elif defined ( __ICCARM__ )\n/* ICCARM Compiler\n   ---------------\n   RAM functions are defined using a specific toolchain keyword \"__ramfunc\".\n*/\n#define __RAM_FUNC __ramfunc HAL_StatusTypeDef\n\n#elif defined   (  __GNUC__  )\n/* GNU Compiler\n   ------------\n  RAM functions are defined using a specific toolchain attribute\n   \"__attribute__((section(\".RamFunc\")))\".\n*/\n#define __RAM_FUNC HAL_StatusTypeDef  __attribute__((section(\".RamFunc\")))\n\n#endif\n\n/**\n  * @brief  __NOINLINE definition\n  */\n#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )\n/* ARM & GNUCompiler\n   ----------------\n*/\n#define __NOINLINE __attribute__ ( (noinline) )\n\n#elif defined ( __ICCARM__ )\n/* ICCARM Compiler\n   ---------------\n*/\n#define __NOINLINE _Pragma(\"optimize = no_inline\")\n\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* ___STM32F4xx_HAL_DEF */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_hal_sd.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_sd.c\n  * @author  MCD Application Team\n  * @version V1.7.1\n  * @date    14-April-2017\n  * @brief   SD card HAL module driver.\n  *          This file provides firmware functions to manage the following\n  *          functionalities of the Secure Digital (SD) peripheral:\n  *           + Initialization and de-initialization functions\n  *           + IO operation functions\n  *           + Peripheral Control functions\n  *           + Peripheral State functions\n  *\n  @verbatim\n  ==============================================================================\n                        ##### How to use this driver #####\n  ==============================================================================\n  [..]\n    This driver implements a high level communication layer for read and write from/to\n    this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by\n    the user in HAL_SD_MspInit() function (MSP layer).\n    Basically, the MSP layer configuration should be the same as we provide in the\n    examples.\n    You can easily tailor this configuration according to hardware resources.\n\n  [..]\n    This driver is a generic layered driver for SDIO memories which uses the HAL\n    SDIO driver functions to interface with SD and uSD cards devices.\n    It is used as follows:\n\n    (#) Initialize the SDIO low level resources by implementing the HAL_SD_MspInit() API:\n        (##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE();\n        (##) SDIO pins configuration for SD card\n            (+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();\n            (+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init()\n                  and according to your pin assignment;\n        (##) DMA configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()\n             and HAL_SD_WriteBlocks_DMA() APIs).\n            (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();\n            (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.\n        (##) NVIC configuration if you need to use interrupt process when using DMA transfer.\n            (+++) Configure the SDIO and DMA interrupt priorities using functions\n                  HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority\n            (+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ()\n            (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()\n                  and __HAL_SD_DISABLE_IT() inside the communication process.\n            (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()\n                  and __HAL_SD_CLEAR_IT()\n        (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()\n             and HAL_SD_WriteBlocks_IT() APIs).\n            (+++) Configure the SDIO interrupt priorities using function HAL_NVIC_SetPriority();\n            (+++) Enable the NVIC SDIO IRQs using function HAL_NVIC_EnableIRQ()\n            (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()\n                  and __HAL_SD_DISABLE_IT() inside the communication process.\n            (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()\n                  and __HAL_SD_CLEAR_IT()\n    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization\n\n\n  *** SD Card Initialization and configuration ***\n  ================================================\n  [..]\n    To initialize the SD Card, use the HAL_SD_Init() function. It Initializes\n    SDIO Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).\n    This function provide the following operations:\n\n    (#) Apply the SD Card initialization process at 400KHz and check the SD Card\n        type (Standard Capacity or High Capacity). You can change or adapt this\n        frequency by adjusting the \"ClockDiv\" field.\n        The SD Card frequency (SDIO_CK) is computed as follows:\n\n           SDIO_CK = SDIOCLK / (ClockDiv + 2)\n\n        In initialization mode and according to the SD Card standard,\n        make sure that the SDIO_CK frequency doesn't exceed 400KHz.\n\n        This phase of initialization is done through SDIO_Init() and\n        SDIO_PowerState_ON() SDIO low level APIs.\n\n    (#) Initialize the SD card. The API used is HAL_SD_InitCard().\n        This phase allows the card initialization and identification\n        and check the SD Card type (Standard Capacity or High Capacity)\n        The initialization flow is compatible with SD standard.\n\n        This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case\n        of plug-off plug-in.\n\n    (#) Configure the SD Card Data transfer frequency. You can change or adapt this\n        frequency by adjusting the \"ClockDiv\" field.\n        In transfer mode and according to the SD Card standard, make sure that the\n        SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.\n        To be able to use a frequency higher than 24MHz, you should use the SDIO\n        peripheral in bypass mode. Refer to the corresponding reference manual\n        for more details.\n\n    (#) Select the corresponding SD Card according to the address read with the step 2.\n\n    (#) Configure the SD Card in wide bus mode: 4-bits data.\n\n  *** SD Card Read operation ***\n  ==============================\n  [..]\n    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().\n        This function support only 512-bytes block length (the block size should be\n        chosen as 512 bytes).\n        You can choose either one block read operation or multiple block read operation\n        by adjusting the \"NumberOfBlocks\" parameter.\n        After this, you have to ensure that the transfer is done correctly. The check is done\n        through HAL_SD_GetCardState() function for SD card state.\n\n    (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().\n        This function support only 512-bytes block length (the block size should be\n        chosen as 512 bytes).\n        You can choose either one block read operation or multiple block read operation\n        by adjusting the \"NumberOfBlocks\" parameter.\n        After this, you have to ensure that the transfer is done correctly. The check is done\n        through HAL_SD_GetCardState() function for SD card state.\n        You could also check the DMA transfer process through the SD Rx interrupt event.\n\n    (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().\n        This function support only 512-bytes block length (the block size should be\n        chosen as 512 bytes).\n        You can choose either one block read operation or multiple block read operation\n        by adjusting the \"NumberOfBlocks\" parameter.\n        After this, you have to ensure that the transfer is done correctly. The check is done\n        through HAL_SD_GetCardState() function for SD card state.\n        You could also check the IT transfer process through the SD Rx interrupt event.\n\n  *** SD Card Write operation ***\n  ===============================\n  [..]\n    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().\n        This function support only 512-bytes block length (the block size should be\n        chosen as 512 bytes).\n        You can choose either one block read operation or multiple block read operation\n        by adjusting the \"NumberOfBlocks\" parameter.\n        After this, you have to ensure that the transfer is done correctly. The check is done\n        through HAL_SD_GetCardState() function for SD card state.\n\n    (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().\n        This function support only 512-bytes block length (the block size should be\n        chosen as 512 bytes).\n        You can choose either one block read operation or multiple block read operation\n        by adjusting the \"NumberOfBlocks\" parameter.\n        After this, you have to ensure that the transfer is done correctly. The check is done\n        through HAL_SD_GetCardState() function for SD card state.\n        You could also check the DMA transfer process through the SD Tx interrupt event.\n\n    (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().\n        This function support only 512-bytes block length (the block size should be\n        chosen as 512 bytes).\n        You can choose either one block read operation or multiple block read operation\n        by adjusting the \"NumberOfBlocks\" parameter.\n        After this, you have to ensure that the transfer is done correctly. The check is done\n        through HAL_SD_GetCardState() function for SD card state.\n        You could also check the IT transfer process through the SD Tx interrupt event.\n\n  *** SD card status ***\n  ======================\n  [..]\n    (+) The SD Status contains status bits that are related to the SD Memory\n        Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().\n\n  *** SD card information ***\n  ===========================\n  [..]\n    (+) To get SD card information, you can use the function HAL_SD_GetCardInfo().\n        It returns useful information about the SD card such as block size, card type,\n        block number ...\n\n  *** SD card CSD register ***\n  ============================\n    (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.\n        Some of the CSD parameters are useful for card initialization and identification.\n\n  *** SD card CID register ***\n  ============================\n    (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.\n        Some of the CSD parameters are useful for card initialization and identification.\n\n  *** SD HAL driver macros list ***\n  ==================================\n  [..]\n    Below the list of most used macros in SD HAL driver.\n\n    (+) __HAL_SD_ENABLE : Enable the SD device\n    (+) __HAL_SD_DISABLE : Disable the SD device\n    (+) __HAL_SD_DMA_ENABLE: Enable the SDIO DMA transfer\n    (+) __HAL_SD_DMA_DISABLE: Disable the SDIO DMA transfer\n    (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt\n    (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt\n    (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not\n    (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags\n\n    (@) You can refer to the SD HAL driver header file for more useful macros\n\n  *** Callback registration ***\n  =============================================\n  [..]\n    The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1\n    allows the user to configure dynamically the driver callbacks.\n\n    Use Functions @ref HAL_SD_RegisterCallback() to register a user callback,\n    it allows to register following callbacks:\n      (+) TxCpltCallback : callback when a transmission transfer is completed.\n      (+) RxCpltCallback : callback when a reception transfer is completed.\n      (+) ErrorCallback : callback when error occurs.\n      (+) AbortCpltCallback : callback when abort is completed.\n      (+) MspInitCallback    : SD MspInit.\n      (+) MspDeInitCallback  : SD MspDeInit.\n    This function takes as parameters the HAL peripheral handle, the Callback ID\n    and a pointer to the user callback function.\n\n    Use function @ref HAL_SD_UnRegisterCallback() to reset a callback to the default\n    weak (surcharged) function. It allows to reset following callbacks:\n      (+) TxCpltCallback : callback when a transmission transfer is completed.\n      (+) RxCpltCallback : callback when a reception transfer is completed.\n      (+) ErrorCallback : callback when error occurs.\n      (+) AbortCpltCallback : callback when abort is completed.\n      (+) MspInitCallback    : SD MspInit.\n      (+) MspDeInitCallback  : SD MspDeInit.\n    This function takes as parameters the HAL peripheral handle and the Callback ID.\n\n    By default, after the @ref HAL_SD_Init and if the state is HAL_SD_STATE_RESET\n    all callbacks are reset to the corresponding legacy weak (surcharged) functions.\n    Exception done for MspInit and MspDeInit callbacks that are respectively\n    reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init\n    and @ref  HAL_SD_DeInit only when these callbacks are null (not registered beforehand).\n    If not, MspInit or MspDeInit are not null, the @ref HAL_SD_Init and @ref HAL_SD_DeInit\n    keep and use the user MspInit/MspDeInit callbacks (registered beforehand)\n\n    Callbacks can be registered/unregistered in READY state only.\n    Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered\n    in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used\n    during the Init/DeInit.\n    In that case first register the MspInit/MspDeInit user callbacks\n    using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit\n    or @ref HAL_SD_Init function.\n\n    When the compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or\n    not defined, the callback registering feature is not available\n    and weak (surcharged) callbacks are used.\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup SD\n  * @{\n  */\n\n#ifdef HAL_SD_MODULE_ENABLED\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \\\n    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \\\n    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \\\n    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/** @addtogroup SD_Private_Defines\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/* Private macro -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\n/* Private functions ---------------------------------------------------------*/\n/** @defgroup SD_Private_Functions SD Private Functions\n  * @{\n  */\nstatic uint32_t SD_InitCard(SD_HandleTypeDef *hsd);\nstatic uint32_t SD_PowerON(SD_HandleTypeDef *hsd);\nstatic uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);\nstatic uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);\nstatic uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);\nstatic uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);\nstatic uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);\nstatic void SD_PowerOFF(SD_HandleTypeDef *hsd);\nstatic void SD_Write_IT(SD_HandleTypeDef *hsd);\nstatic void SD_Read_IT(SD_HandleTypeDef *hsd);\n#if 0 // XXX DMA\nstatic void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma);\nstatic void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\nstatic void SD_DMAError(DMA_HandleTypeDef *hdma);\nstatic void SD_DMATxAbort(DMA_HandleTypeDef *hdma);\nstatic void SD_DMARxAbort(DMA_HandleTypeDef *hdma);\n#endif // XXX DMA\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup SD_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup SD_Exported_Functions_Group1\n *  @brief   Initialization and de-initialization functions\n *\n@verbatim\n  ==============================================================================\n          ##### Initialization and de-initialization functions #####\n  ==============================================================================\n  [..]\n    This section provides functions allowing to initialize/de-initialize the SD\n    card device to be ready for use.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Initializes the SD according to the specified parameters in the\n            SD_HandleTypeDef and create the associated handle.\n  * @param  hsd: Pointer to the SD handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)\n{\n  /* Check the SD handle allocation */\n  if(hsd == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance));\n  assert_param(IS_SDIO_CLOCK_EDGE(hsd->Init.ClockEdge));\n  assert_param(IS_SDIO_CLOCK_BYPASS(hsd->Init.ClockBypass));\n  assert_param(IS_SDIO_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));\n  assert_param(IS_SDIO_BUS_WIDE(hsd->Init.BusWide));\n  assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));\n  assert_param(IS_SDIO_CLKDIV(hsd->Init.ClockDiv));\n\n  if(hsd->State == HAL_SD_STATE_RESET)\n  {\n    /* Allocate lock resource and initialize it */\n    hsd->Lock = HAL_UNLOCKED;\n#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)\n    /* Reset Callback pointers in HAL_SD_STATE_RESET only */\n    hsd->TxCpltCallback    = HAL_SD_TxCpltCallback;\n    hsd->RxCpltCallback    = HAL_SD_RxCpltCallback;\n    hsd->ErrorCallback     = HAL_SD_ErrorCallback;\n    hsd->AbortCpltCallback = HAL_SD_AbortCallback;\n\n    if(hsd->MspInitCallback == NULL)\n    {\n      hsd->MspInitCallback = HAL_SD_MspInit;\n    }\n\n    /* Init the low level hardware */\n    hsd->MspInitCallback(hsd);\n#else\n    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */\n    HAL_SD_MspInit(hsd);\n#endif /* USE_HAL_SD_REGISTER_CALLBACKS */\n  }\n\n  hsd->State = HAL_SD_STATE_BUSY;\n\n  /* Initialize the Card parameters */\n  if (HAL_SD_InitCard(hsd) != HAL_OK)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Initialize the error code */\n  hsd->ErrorCode = HAL_SD_ERROR_NONE;\n\n  /* Initialize the SD operation */\n  hsd->Context = SD_CONTEXT_NONE;\n\n  /* Initialize the SD state */\n  hsd->State = HAL_SD_STATE_READY;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initializes the SD Card.\n  * @param  hsd: Pointer to SD handle\n  * @note   This function initializes the SD card. It could be used when a card\n            re-initialization is needed.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)\n{\n  uint32_t errorstate;\n  HAL_StatusTypeDef status;\n  SD_InitTypeDef Init;\n\n  /* Default SDIO peripheral configuration for SD card initialization */\n  Init.ClockEdge           = SDIO_CLOCK_EDGE_RISING;\n  Init.ClockBypass         = SDIO_CLOCK_BYPASS_DISABLE;\n  Init.ClockPowerSave      = SDIO_CLOCK_POWER_SAVE_DISABLE;\n  Init.BusWide             = SDIO_BUS_WIDE_1B;\n  Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;\n  Init.ClockDiv            = SDIO_INIT_CLK_DIV;\n\n  /* Initialize SDIO peripheral interface with default configuration */\n  status = SDIO_Init(hsd->Instance, Init);\n  if(status != HAL_OK)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Disable SDIO Clock */\n  __HAL_SD_DISABLE(hsd);\n\n  /* Set Power State to ON */\n  (void)SDIO_PowerState_ON(hsd->Instance);\n\n  /* Enable SDIO Clock */\n  __HAL_SD_ENABLE(hsd);\n\n  /* Identify card operating voltage */\n  errorstate = SD_PowerON(hsd);\n  if(errorstate != HAL_SD_ERROR_NONE)\n  {\n    hsd->State = HAL_SD_STATE_READY;\n    hsd->ErrorCode |= errorstate;\n    return HAL_ERROR;\n  }\n\n  /* Card initialization */\n  errorstate = SD_InitCard(hsd);\n  if(errorstate != HAL_SD_ERROR_NONE)\n  {\n    hsd->State = HAL_SD_STATE_READY;\n    hsd->ErrorCode |= errorstate;\n    return HAL_ERROR;\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  De-Initializes the SD card.\n  * @param  hsd: Pointer to SD handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)\n{\n  /* Check the SD handle allocation */\n  if(hsd == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance));\n\n  hsd->State = HAL_SD_STATE_BUSY;\n\n  /* Set SD power state to off */\n  SD_PowerOFF(hsd);\n\n#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)\n  if(hsd->MspDeInitCallback == NULL)\n  {\n    hsd->MspDeInitCallback = HAL_SD_MspDeInit;\n  }\n\n  /* DeInit the low level hardware */\n  hsd->MspDeInitCallback(hsd);\n#else\n  /* De-Initialize the MSP layer */\n  HAL_SD_MspDeInit(hsd);\n#endif /* USE_HAL_SD_REGISTER_CALLBACKS */\n\n  hsd->ErrorCode = HAL_SD_ERROR_NONE;\n  hsd->State = HAL_SD_STATE_RESET;\n\n  return HAL_OK;\n}\n\n\n/**\n  * @brief  Initializes the SD MSP.\n  * @param  hsd: Pointer to SD handle\n  * @retval None\n  */\n__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hsd);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SD_MspInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  De-Initialize SD MSP.\n  * @param  hsd: Pointer to SD handle\n  * @retval None\n  */\n__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hsd);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SD_MspDeInit could be implemented in the user file\n   */\n}\n\n/**\n  * @}\n  */\n\n/** @addtogroup SD_Exported_Functions_Group2\n *  @brief   Data transfer functions\n *\n@verbatim\n  ==============================================================================\n                        ##### IO operation functions #####\n  ==============================================================================\n  [..]\n    This subsection provides a set of functions allowing to manage the data\n    transfer from/to SD card.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Reads block(s) from a specified address in a card. The Data transfer\n  *         is managed by polling mode.\n  * @note   This API should be followed by a check on the card state through\n  *         HAL_SD_GetCardState().\n  * @param  hsd: Pointer to SD handle\n  * @param  pData: pointer to the buffer that will contain the received data\n  * @param  BlockAdd: Block Address from where data is to be read\n  * @param  NumberOfBlocks: Number of SD blocks to read\n  * @param  Timeout: Specify timeout value\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)\n{\n  SDIO_DataInitTypeDef config;\n  uint32_t errorstate;\n  uint32_t tickstart = HAL_GetTick();\n  uint32_t count, data, dataremaining;\n  uint32_t add = BlockAdd;\n  uint8_t *tempbuff = pData;\n\n  if(NULL == pData)\n  {\n    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;\n    return HAL_ERROR;\n  }\n\n  if(hsd->State == HAL_SD_STATE_READY)\n  {\n    hsd->ErrorCode = HAL_SD_ERROR_NONE;\n\n    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))\n    {\n      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;\n      return HAL_ERROR;\n    }\n\n    hsd->State = HAL_SD_STATE_BUSY;\n\n    /* Initialize data control register */\n    hsd->Instance->DCTRL = 0U;\n\n    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)\n    {\n      add *= 512U;\n    }\n\n    /* Set Block Size for Card */\n    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      /* Clear all the static flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= errorstate;\n      hsd->State = HAL_SD_STATE_READY;\n      return HAL_ERROR;\n    }\n\n    /* Configure the SD DPSM (Data Path State Machine) */\n    config.DataTimeOut   = SDMMC_DATATIMEOUT;\n    config.DataLength    = NumberOfBlocks * BLOCKSIZE;\n    config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;\n    config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;\n    config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;\n    config.DPSM          = SDIO_DPSM_ENABLE;\n    (void)SDIO_ConfigData(hsd->Instance, &config);\n\n    /* Read block(s) in polling mode */\n    if(NumberOfBlocks > 1U)\n    {\n      hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;\n\n      /* Read Multi Block command */\n      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);\n    }\n    else\n    {\n      hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;\n\n      /* Read Single Block command */\n      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);\n    }\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      /* Clear all the static flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= errorstate;\n      hsd->State = HAL_SD_STATE_READY;\n      hsd->Context = SD_CONTEXT_NONE;\n      return HAL_ERROR;\n    }\n\n    /* Poll on SDIO flags */\n    dataremaining = config.DataLength;\n#if defined(SDIO_STA_STBITERR)\n    while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))\n#else /* SDIO_STA_STBITERR not defined */\n    while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))\n#endif /* SDIO_STA_STBITERR */\n    {\n      if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF) && (dataremaining > 0U))\n      {\n        /* Read data from SDIO Rx FIFO */\n        for(count = 0U; count < 8U; count++)\n        {\n          data = SDIO_ReadFIFO(hsd->Instance);\n          *tempbuff = (uint8_t)(data & 0xFFU);\n          tempbuff++;\n          dataremaining--;\n          *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);\n          tempbuff++;\n          dataremaining--;\n          *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);\n          tempbuff++;\n          dataremaining--;\n          *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);\n          tempbuff++;\n          dataremaining--;\n        }\n      }\n\n      if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))\n      {\n        /* Clear all the static flags */\n        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n        hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;\n        hsd->State= HAL_SD_STATE_READY;\n        hsd->Context = SD_CONTEXT_NONE;\n        return HAL_TIMEOUT;\n      }\n    }\n\n    /* Send stop transmission command in case of multiblock read */\n    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))\n    {\n      if(hsd->SdCard.CardType != CARD_SECURED)\n      {\n        /* Send stop transmission command */\n        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);\n        if(errorstate != HAL_SD_ERROR_NONE)\n        {\n          /* Clear all the static flags */\n          __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n          hsd->ErrorCode |= errorstate;\n          hsd->State = HAL_SD_STATE_READY;\n          hsd->Context = SD_CONTEXT_NONE;\n          return HAL_ERROR;\n        }\n      }\n    }\n\n    /* Get error state */\n    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))\n    {\n      /* Clear all the static flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;\n      hsd->State = HAL_SD_STATE_READY;\n      hsd->Context = SD_CONTEXT_NONE;\n      return HAL_ERROR;\n    }\n    else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))\n    {\n      /* Clear all the static flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;\n      hsd->State = HAL_SD_STATE_READY;\n      hsd->Context = SD_CONTEXT_NONE;\n      return HAL_ERROR;\n    }\n    else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))\n    {\n      /* Clear all the static flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;\n      hsd->State = HAL_SD_STATE_READY;\n      hsd->Context = SD_CONTEXT_NONE;\n      return HAL_ERROR;\n    }\n    else\n    {\n      /* Nothing to do */\n    }\n\n    /* Empty FIFO if there is still any data */\n    while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (dataremaining > 0U))\n    {\n      data = SDIO_ReadFIFO(hsd->Instance);\n      *tempbuff = (uint8_t)(data & 0xFFU);\n      tempbuff++;\n      dataremaining--;\n      *tempbuff = (uint8_t)((data >> 8U) & 0xFFU);\n      tempbuff++;\n      dataremaining--;\n      *tempbuff = (uint8_t)((data >> 16U) & 0xFFU);\n      tempbuff++;\n      dataremaining--;\n      *tempbuff = (uint8_t)((data >> 24U) & 0xFFU);\n      tempbuff++;\n      dataremaining--;\n\n      if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))\n      {\n        /* Clear all the static flags */\n        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n        hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;\n        hsd->State= HAL_SD_STATE_READY;\n        hsd->Context = SD_CONTEXT_NONE;\n        return HAL_ERROR;\n      }\n    }\n\n    /* Clear all the static flags */\n    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);\n\n    hsd->State = HAL_SD_STATE_READY;\n\n    return HAL_OK;\n  }\n  else\n  {\n    hsd->ErrorCode |= HAL_SD_ERROR_BUSY;\n    return HAL_ERROR;\n  }\n}\n\n/**\n  * @brief  Allows to write block(s) to a specified address in a card. The Data\n  *         transfer is managed by polling mode.\n  * @note   This API should be followed by a check on the card state through\n  *         HAL_SD_GetCardState().\n  * @param  hsd: Pointer to SD handle\n  * @param  pData: pointer to the buffer that will contain the data to transmit\n  * @param  BlockAdd: Block Address where data will be written\n  * @param  NumberOfBlocks: Number of SD blocks to write\n  * @param  Timeout: Specify timeout value\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)\n{\n  SDIO_DataInitTypeDef config;\n  uint32_t errorstate;\n  uint32_t tickstart = HAL_GetTick();\n  uint32_t count, data, dataremaining;\n  uint32_t add = BlockAdd;\n  uint8_t *tempbuff = pData;\n\n  if(NULL == pData)\n  {\n    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;\n    return HAL_ERROR;\n  }\n\n  if(hsd->State == HAL_SD_STATE_READY)\n  {\n    hsd->ErrorCode = HAL_SD_ERROR_NONE;\n\n    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))\n    {\n      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;\n      return HAL_ERROR;\n    }\n\n    hsd->State = HAL_SD_STATE_BUSY;\n\n    /* Initialize data control register */\n    hsd->Instance->DCTRL = 0U;\n\n    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)\n    {\n      add *= 512U;\n    }\n\n    /* Set Block Size for Card */\n    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      /* Clear all the static flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= errorstate;\n      hsd->State = HAL_SD_STATE_READY;\n      return HAL_ERROR;\n    }\n\n    /* Configure the SD DPSM (Data Path State Machine) */\n    config.DataTimeOut   = SDMMC_DATATIMEOUT;\n    config.DataLength    = NumberOfBlocks * BLOCKSIZE;\n    config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;\n    config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;\n    config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;\n    config.DPSM          = SDIO_DPSM_ENABLE;\n    (void)SDIO_ConfigData(hsd->Instance, &config);\n\n    /* Write Blocks in Polling mode */\n    if(NumberOfBlocks > 1U)\n    {\n      hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;\n\n      /* Write Multi Block command */\n      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);\n    }\n    else\n    {\n      hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;\n\n      /* Write Single Block command */\n      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);\n    }\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      /* Clear all the static flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= errorstate;\n      hsd->State = HAL_SD_STATE_READY;\n      hsd->Context = SD_CONTEXT_NONE;\n      return HAL_ERROR;\n    }\n\n    /* Write block(s) in polling mode */\n    dataremaining = config.DataLength;\n#if defined(SDIO_STA_STBITERR)\n    while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))\n#else /* SDIO_STA_STBITERR not defined */\n    while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))\n#endif /* SDIO_STA_STBITERR */\n    {\n      if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE) && (dataremaining > 0U))\n      {\n        /* Write data to SDIO Tx FIFO */\n        for(count = 0U; count < 8U; count++)\n        {\n          data = (uint32_t)(*tempbuff);\n          tempbuff++;\n          dataremaining--;\n          data |= ((uint32_t)(*tempbuff) << 8U);\n          tempbuff++;\n          dataremaining--;\n          data |= ((uint32_t)(*tempbuff) << 16U);\n          tempbuff++;\n          dataremaining--;\n          data |= ((uint32_t)(*tempbuff) << 24U);\n          tempbuff++;\n          dataremaining--;\n          (void)SDIO_WriteFIFO(hsd->Instance, &data);\n        }\n      }\n\n      if(((HAL_GetTick()-tickstart) >=  Timeout) || (Timeout == 0U))\n      {\n        /* Clear all the static flags */\n        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n        hsd->ErrorCode |= errorstate;\n        hsd->State = HAL_SD_STATE_READY;\n        hsd->Context = SD_CONTEXT_NONE;\n        return HAL_TIMEOUT;\n      }\n    }\n\n    /* Send stop transmission command in case of multiblock write */\n    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))\n    {\n      if(hsd->SdCard.CardType != CARD_SECURED)\n      {\n        /* Send stop transmission command */\n        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);\n        if(errorstate != HAL_SD_ERROR_NONE)\n        {\n          /* Clear all the static flags */\n          __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n          hsd->ErrorCode |= errorstate;\n          hsd->State = HAL_SD_STATE_READY;\n          hsd->Context = SD_CONTEXT_NONE;\n          return HAL_ERROR;\n        }\n      }\n    }\n\n    /* Get error state */\n    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))\n    {\n      /* Clear all the static flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;\n      hsd->State = HAL_SD_STATE_READY;\n      hsd->Context = SD_CONTEXT_NONE;\n      return HAL_ERROR;\n    }\n    else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))\n    {\n      /* Clear all the static flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;\n      hsd->State = HAL_SD_STATE_READY;\n      hsd->Context = SD_CONTEXT_NONE;\n      return HAL_ERROR;\n    }\n    else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR))\n    {\n      /* Clear all the static flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;\n      hsd->State = HAL_SD_STATE_READY;\n      hsd->Context = SD_CONTEXT_NONE;\n      return HAL_ERROR;\n    }\n    else\n    {\n      /* Nothing to do */\n    }\n\n    /* Clear all the static flags */\n    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);\n\n    hsd->State = HAL_SD_STATE_READY;\n\n    return HAL_OK;\n  }\n  else\n  {\n    hsd->ErrorCode |= HAL_SD_ERROR_BUSY;\n    return HAL_ERROR;\n  }\n}\n\n/**\n  * @brief  Reads block(s) from a specified address in a card. The Data transfer\n  *         is managed in interrupt mode.\n  * @note   This API should be followed by a check on the card state through\n  *         HAL_SD_GetCardState().\n  * @note   You could also check the IT transfer process through the SD Rx\n  *         interrupt event.\n  * @param  hsd: Pointer to SD handle\n  * @param  pData: Pointer to the buffer that will contain the received data\n  * @param  BlockAdd: Block Address from where data is to be read\n  * @param  NumberOfBlocks: Number of blocks to read.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)\n{\n  SDIO_DataInitTypeDef config;\n  uint32_t errorstate;\n  uint32_t add = BlockAdd;\n\n  if(NULL == pData)\n  {\n    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;\n    return HAL_ERROR;\n  }\n\n  if(hsd->State == HAL_SD_STATE_READY)\n  {\n    hsd->ErrorCode = HAL_SD_ERROR_NONE;\n\n    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))\n    {\n      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;\n      return HAL_ERROR;\n    }\n\n    hsd->State = HAL_SD_STATE_BUSY;\n\n    /* Initialize data control register */\n    hsd->Instance->DCTRL = 0U;\n\n    hsd->pRxBuffPtr = pData;\n    hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;\n\n#if defined(SDIO_STA_STBITERR)\n    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF | SDIO_IT_STBITERR));\n#else /* SDIO_STA_STBITERR not defined */\n    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF));\n#endif /* SDIO_STA_STBITERR */\n\n    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)\n    {\n      add *= 512U;\n    }\n\n    /* Set Block Size for Card */\n    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      /* Clear all the static flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= errorstate;\n      hsd->State = HAL_SD_STATE_READY;\n      return HAL_ERROR;\n    }\n\n    /* Configure the SD DPSM (Data Path State Machine) */\n    config.DataTimeOut   = SDMMC_DATATIMEOUT;\n    config.DataLength    = BLOCKSIZE * NumberOfBlocks;\n    config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;\n    config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;\n    config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;\n    config.DPSM          = SDIO_DPSM_ENABLE;\n    (void)SDIO_ConfigData(hsd->Instance, &config);\n\n    /* Read Blocks in IT mode */\n    if(NumberOfBlocks > 1U)\n    {\n      hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);\n\n      /* Read Multi Block command */\n      errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);\n    }\n    else\n    {\n      hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);\n\n      /* Read Single Block command */\n      errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);\n    }\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      /* Clear all the static flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= errorstate;\n      hsd->State = HAL_SD_STATE_READY;\n      hsd->Context = SD_CONTEXT_NONE;\n      return HAL_ERROR;\n    }\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Writes block(s) to a specified address in a card. The Data transfer\n  *         is managed in interrupt mode.\n  * @note   This API should be followed by a check on the card state through\n  *         HAL_SD_GetCardState().\n  * @note   You could also check the IT transfer process through the SD Tx\n  *         interrupt event.\n  * @param  hsd: Pointer to SD handle\n  * @param  pData: Pointer to the buffer that will contain the data to transmit\n  * @param  BlockAdd: Block Address where data will be written\n  * @param  NumberOfBlocks: Number of blocks to write\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)\n{\n  SDIO_DataInitTypeDef config;\n  uint32_t errorstate;\n  uint32_t add = BlockAdd;\n\n  if(NULL == pData)\n  {\n    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;\n    return HAL_ERROR;\n  }\n\n  if(hsd->State == HAL_SD_STATE_READY)\n  {\n    hsd->ErrorCode = HAL_SD_ERROR_NONE;\n\n    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))\n    {\n      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;\n      return HAL_ERROR;\n    }\n\n    hsd->State = HAL_SD_STATE_BUSY;\n\n    /* Initialize data control register */\n    hsd->Instance->DCTRL = 0U;\n\n    hsd->pTxBuffPtr = pData;\n    hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;\n\n    /* Enable transfer interrupts */\n#if defined(SDIO_STA_STBITERR)\n    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE | SDIO_IT_STBITERR));\n#else /* SDIO_STA_STBITERR not defined */\n    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE));\n#endif /* SDIO_STA_STBITERR */\n\n    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)\n    {\n      add *= 512U;\n    }\n\n    /* Set Block Size for Card */\n    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      /* Clear all the static flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= errorstate;\n      hsd->State = HAL_SD_STATE_READY;\n      return HAL_ERROR;\n    }\n\n    /* Write Blocks in Polling mode */\n    if(NumberOfBlocks > 1U)\n    {\n      hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);\n\n      /* Write Multi Block command */\n      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);\n    }\n    else\n    {\n      hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);\n\n      /* Write Single Block command */\n      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);\n    }\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      /* Clear all the static flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= errorstate;\n      hsd->State = HAL_SD_STATE_READY;\n      hsd->Context = SD_CONTEXT_NONE;\n      return HAL_ERROR;\n    }\n\n    /* Configure the SD DPSM (Data Path State Machine) */\n    config.DataTimeOut   = SDMMC_DATATIMEOUT;\n    config.DataLength    = BLOCKSIZE * NumberOfBlocks;\n    config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;\n    config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;\n    config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;\n    config.DPSM          = SDIO_DPSM_ENABLE;\n    (void)SDIO_ConfigData(hsd->Instance, &config);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n#if 0 // XXX DMA\n/**\n  * @brief  Reads block(s) from a specified address in a card. The Data transfer\n  *         is managed by DMA mode.\n  * @note   This API should be followed by a check on the card state through\n  *         HAL_SD_GetCardState().\n  * @note   You could also check the DMA transfer process through the SD Rx\n  *         interrupt event.\n  * @param  hsd: Pointer SD handle\n  * @param  pData: Pointer to the buffer that will contain the received data\n  * @param  BlockAdd: Block Address from where data is to be read\n  * @param  NumberOfBlocks: Number of blocks to read.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)\n{\n  SDIO_DataInitTypeDef config;\n  uint32_t errorstate;\n  uint32_t add = BlockAdd;\n\n  if(NULL == pData)\n  {\n    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;\n    return HAL_ERROR;\n  }\n\n  if(hsd->State == HAL_SD_STATE_READY)\n  {\n    hsd->ErrorCode = HAL_SD_ERROR_NONE;\n\n    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))\n    {\n      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;\n      return HAL_ERROR;\n    }\n\n    hsd->State = HAL_SD_STATE_BUSY;\n\n    /* Initialize data control register */\n    hsd->Instance->DCTRL = 0U;\n\n#if defined(SDIO_STA_STBITERR)\n    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR));\n#else /* SDIO_STA_STBITERR not defined */\n    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));\n#endif /* SDIO_STA_STBITERR */\n\n    /* Set the DMA transfer complete callback */\n    hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt;\n\n    /* Set the DMA error callback */\n    hsd->hdmarx->XferErrorCallback = SD_DMAError;\n\n    /* Set the DMA Abort callback */\n    hsd->hdmarx->XferAbortCallback = NULL;\n\n    /* Enable the DMA Channel */\n    if(HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)\n    {\n      __HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= HAL_SD_ERROR_DMA;\n      hsd->State = HAL_SD_STATE_READY;\n      return HAL_ERROR;\n    }\n    else\n    {\n      /* Enable SD DMA transfer */\n      __HAL_SD_DMA_ENABLE(hsd);\n\n      if(hsd->SdCard.CardType != CARD_SDHC_SDXC)\n      {\n        add *= 512U;\n      }\n\n      /* Set Block Size for Card */\n      errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);\n      if(errorstate != HAL_SD_ERROR_NONE)\n      {\n        /* Clear all the static flags */\n        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n        hsd->ErrorCode |= errorstate;\n        hsd->State = HAL_SD_STATE_READY;\n        return HAL_ERROR;\n      }\n\n      /* Configure the SD DPSM (Data Path State Machine) */\n      config.DataTimeOut   = SDMMC_DATATIMEOUT;\n      config.DataLength    = BLOCKSIZE * NumberOfBlocks;\n      config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;\n      config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;\n      config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;\n      config.DPSM          = SDIO_DPSM_ENABLE;\n      (void)SDIO_ConfigData(hsd->Instance, &config);\n\n      /* Read Blocks in DMA mode */\n      if(NumberOfBlocks > 1U)\n      {\n        hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);\n\n        /* Read Multi Block command */\n        errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);\n      }\n      else\n      {\n        hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);\n\n        /* Read Single Block command */\n        errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);\n      }\n      if(errorstate != HAL_SD_ERROR_NONE)\n      {\n        /* Clear all the static flags */\n        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n        hsd->ErrorCode |= errorstate;\n        hsd->State = HAL_SD_STATE_READY;\n        hsd->Context = SD_CONTEXT_NONE;\n        return HAL_ERROR;\n      }\n\n      return HAL_OK;\n    }\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Writes block(s) to a specified address in a card. The Data transfer\n  *         is managed by DMA mode.\n  * @note   This API should be followed by a check on the card state through\n  *         HAL_SD_GetCardState().\n  * @note   You could also check the DMA transfer process through the SD Tx\n  *         interrupt event.\n  * @param  hsd: Pointer to SD handle\n  * @param  pData: Pointer to the buffer that will contain the data to transmit\n  * @param  BlockAdd: Block Address where data will be written\n  * @param  NumberOfBlocks: Number of blocks to write\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)\n{\n  SDIO_DataInitTypeDef config;\n  uint32_t errorstate;\n  uint32_t add = BlockAdd;\n\n  if(NULL == pData)\n  {\n    hsd->ErrorCode |= HAL_SD_ERROR_PARAM;\n    return HAL_ERROR;\n  }\n\n  if(hsd->State == HAL_SD_STATE_READY)\n  {\n    hsd->ErrorCode = HAL_SD_ERROR_NONE;\n\n    if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))\n    {\n      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;\n      return HAL_ERROR;\n    }\n\n    hsd->State = HAL_SD_STATE_BUSY;\n\n    /* Initialize data control register */\n    hsd->Instance->DCTRL = 0U;\n\n    /* Enable SD Error interrupts */\n#if defined(SDIO_STA_STBITERR)\n    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));\n#else /* SDIO_STA_STBITERR not defined */\n    __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));\n#endif /* SDIO_STA_STBITERR */\n\n    /* Set the DMA transfer complete callback */\n    hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;\n\n    /* Set the DMA error callback */\n    hsd->hdmatx->XferErrorCallback = SD_DMAError;\n\n    /* Set the DMA Abort callback */\n    hsd->hdmatx->XferAbortCallback = NULL;\n\n    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)\n    {\n      add *= 512U;\n    }\n\n    /* Set Block Size for Card */\n    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      /* Clear all the static flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= errorstate;\n      hsd->State = HAL_SD_STATE_READY;\n      return HAL_ERROR;\n    }\n\n    /* Write Blocks in Polling mode */\n    if(NumberOfBlocks > 1U)\n    {\n      hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);\n\n      /* Write Multi Block command */\n      errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);\n    }\n    else\n    {\n      hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);\n\n      /* Write Single Block command */\n      errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);\n    }\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      /* Clear all the static flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= errorstate;\n      hsd->State = HAL_SD_STATE_READY;\n      hsd->Context = SD_CONTEXT_NONE;\n      return HAL_ERROR;\n    }\n\n    /* Enable SDIO DMA transfer */\n    __HAL_SD_DMA_ENABLE(hsd);\n\n    /* Enable the DMA Channel */\n    if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)\n    {\n#if defined(SDIO_STA_STBITERR)\n      __HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));\n#else /* SDIO_STA_STBITERR not defined */\n      __HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));\n#endif /* SDIO_STA_STBITERR */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= HAL_SD_ERROR_DMA;\n      hsd->State = HAL_SD_STATE_READY;\n      hsd->Context = SD_CONTEXT_NONE;\n      return HAL_ERROR;\n    }\n    else\n    {\n      /* Configure the SD DPSM (Data Path State Machine) */\n      config.DataTimeOut   = SDMMC_DATATIMEOUT;\n      config.DataLength    = BLOCKSIZE * NumberOfBlocks;\n      config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;\n      config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;\n      config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;\n      config.DPSM          = SDIO_DPSM_ENABLE;\n      (void)SDIO_ConfigData(hsd->Instance, &config);\n\n      return HAL_OK;\n    }\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n#endif // XXX DMA\n\n/**\n  * @brief  Erases the specified memory area of the given SD card.\n  * @note   This API should be followed by a check on the card state through\n  *         HAL_SD_GetCardState().\n  * @param  hsd: Pointer to SD handle\n  * @param  BlockStartAdd: Start Block address\n  * @param  BlockEndAdd: End Block address\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)\n{\n  uint32_t errorstate;\n  uint32_t start_add = BlockStartAdd;\n  uint32_t end_add = BlockEndAdd;\n\n  if(hsd->State == HAL_SD_STATE_READY)\n  {\n    hsd->ErrorCode = HAL_SD_ERROR_NONE;\n\n    if(end_add < start_add)\n    {\n      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;\n      return HAL_ERROR;\n    }\n\n    if(end_add > (hsd->SdCard.LogBlockNbr))\n    {\n      hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;\n      return HAL_ERROR;\n    }\n\n    hsd->State = HAL_SD_STATE_BUSY;\n\n    /* Check if the card command class supports erase command */\n    if(((hsd->SdCard.Class) & SDIO_CCCC_ERASE) == 0U)\n    {\n      /* Clear all the static flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;\n      hsd->State = HAL_SD_STATE_READY;\n      return HAL_ERROR;\n    }\n\n    if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)\n    {\n      /* Clear all the static flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;\n      hsd->State = HAL_SD_STATE_READY;\n      return HAL_ERROR;\n    }\n\n    /* Get start and end block for high capacity cards */\n    if(hsd->SdCard.CardType != CARD_SDHC_SDXC)\n    {\n      start_add *= 512U;\n      end_add   *= 512U;\n    }\n\n    /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */\n    if(hsd->SdCard.CardType != CARD_SECURED)\n    {\n      /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */\n      errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add);\n      if(errorstate != HAL_SD_ERROR_NONE)\n      {\n        /* Clear all the static flags */\n        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n        hsd->ErrorCode |= errorstate;\n        hsd->State = HAL_SD_STATE_READY;\n        return HAL_ERROR;\n      }\n\n      /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */\n      errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add);\n      if(errorstate != HAL_SD_ERROR_NONE)\n      {\n        /* Clear all the static flags */\n        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n        hsd->ErrorCode |= errorstate;\n        hsd->State = HAL_SD_STATE_READY;\n        return HAL_ERROR;\n      }\n    }\n\n    /* Send CMD38 ERASE */\n    errorstate = SDMMC_CmdErase(hsd->Instance);\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      /* Clear all the static flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n      hsd->ErrorCode |= errorstate;\n      hsd->State = HAL_SD_STATE_READY;\n      return HAL_ERROR;\n    }\n\n    hsd->State = HAL_SD_STATE_READY;\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  This function handles SD card interrupt request.\n  * @param  hsd: Pointer to SD handle\n  * @retval None\n  */\nvoid HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)\n{\n  uint32_t errorstate;\n  uint32_t context = hsd->Context;\n\n  /* Check for SDIO interrupt flags */\n  if((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U))\n  {\n    SD_Read_IT(hsd);\n  }\n  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) != RESET)\n  {\n    __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DATAEND);\n\n#if defined(SDIO_STA_STBITERR)\n    __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND  | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\\\n                             SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR  | SDIO_IT_TXFIFOHE |\\\n                             SDIO_IT_RXFIFOHF | SDIO_IT_STBITERR);\n#else /* SDIO_STA_STBITERR not defined */\n    __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND  | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\\\n                             SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR  | SDIO_IT_TXFIFOHE |\\\n                             SDIO_IT_RXFIFOHF);\n#endif /* SDIO_STA_STBITERR */\n\n    hsd->Instance->DCTRL &= ~(SDIO_DCTRL_DTEN);\n\n    if((context & SD_CONTEXT_IT) != 0U)\n    {\n      if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))\n      {\n        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);\n        if(errorstate != HAL_SD_ERROR_NONE)\n        {\n          hsd->ErrorCode |= errorstate;\n#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)\n          hsd->ErrorCallback(hsd);\n#else\n          HAL_SD_ErrorCallback(hsd);\n#endif /* USE_HAL_SD_REGISTER_CALLBACKS */\n        }\n      }\n\n      /* Clear all the static flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);\n\n      hsd->State = HAL_SD_STATE_READY;\n      hsd->Context = SD_CONTEXT_NONE;\n      if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))\n      {\n#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)\n        hsd->RxCpltCallback(hsd);\n#else\n        HAL_SD_RxCpltCallback(hsd);\n#endif /* USE_HAL_SD_REGISTER_CALLBACKS */\n      }\n      else\n      {\n#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)\n        hsd->TxCpltCallback(hsd);\n#else\n        HAL_SD_TxCpltCallback(hsd);\n#endif /* USE_HAL_SD_REGISTER_CALLBACKS */\n      }\n    }\n    else if((context & SD_CONTEXT_DMA) != 0U)\n    {\n      if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)\n      {\n        errorstate = SDMMC_CmdStopTransfer(hsd->Instance);\n        if(errorstate != HAL_SD_ERROR_NONE)\n        {\n          hsd->ErrorCode |= errorstate;\n#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)\n          hsd->ErrorCallback(hsd);\n#else\n          HAL_SD_ErrorCallback(hsd);\n#endif /* USE_HAL_SD_REGISTER_CALLBACKS */\n        }\n      }\n      if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == 0U))\n      {\n        /* Disable the DMA transfer for transmit request by setting the DMAEN bit\n        in the SD DCTRL register */\n        hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);\n\n        hsd->State = HAL_SD_STATE_READY;\n\n#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)\n        hsd->TxCpltCallback(hsd);\n#else\n        HAL_SD_TxCpltCallback(hsd);\n#endif /* USE_HAL_SD_REGISTER_CALLBACKS */\n      }\n    }\n    else\n    {\n      /* Nothing to do */\n    }\n  }\n  else if((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U))\n  {\n    SD_Write_IT(hsd);\n  }\n\n#if defined(SDIO_STA_STBITERR)\n  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_RXOVERR | SDIO_FLAG_TXUNDERR | SDIO_FLAG_STBITERR) != RESET)\n#else /* SDIO_STA_STBITERR not defined */\n  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_RXOVERR | SDIO_FLAG_TXUNDERR) != RESET)\n#endif /* SDIO_STA_STBITERR */\n  {\n    /* Set Error code */\n    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL) != RESET)\n    {\n      hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;\n    }\n    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT) != RESET)\n    {\n      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;\n    }\n    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR) != RESET)\n    {\n      hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;\n    }\n    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR) != RESET)\n    {\n      hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;\n    }\n#if defined(SDIO_STA_STBITERR)\n    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_STBITERR) != RESET)\n    {\n      hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;\n    }\n#endif /* SDIO_STA_STBITERR */\n\n#if defined(SDIO_STA_STBITERR)\n    /* Clear All flags */\n    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS | SDIO_FLAG_STBITERR);\n\n    /* Disable all interrupts */\n    __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\\\n                             SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR | SDIO_IT_STBITERR);\n#else /* SDIO_STA_STBITERR not defined */\n    /* Clear All flags */\n    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);\n\n    /* Disable all interrupts */\n    __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\\\n                             SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);\n#endif /* SDIO_STA_STBITERR */\n\n    hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);\n\n    if((context & SD_CONTEXT_IT) != 0U)\n    {\n      /* Set the SD state to ready to be able to start again the process */\n      hsd->State = HAL_SD_STATE_READY;\n      hsd->Context = SD_CONTEXT_NONE;\n#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)\n      hsd->ErrorCallback(hsd);\n#else\n      HAL_SD_ErrorCallback(hsd);\n#endif /* USE_HAL_SD_REGISTER_CALLBACKS */\n    }\n    else if((context & SD_CONTEXT_DMA) != 0U)\n    {\n#if 0 // XXX DMA\n      /* Abort the SD DMA channel */\n      if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))\n      {\n        /* Set the DMA Tx abort callback */\n        hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;\n        /* Abort DMA in IT mode */\n        if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)\n        {\n          SD_DMATxAbort(hsd->hdmatx);\n        }\n      }\n      else if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))\n      {\n        /* Set the DMA Rx abort callback */\n        hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;\n        /* Abort DMA in IT mode */\n        if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)\n        {\n          SD_DMARxAbort(hsd->hdmarx);\n        }\n      }\n      else\n      {\n        hsd->ErrorCode = HAL_SD_ERROR_NONE;\n        hsd->State = HAL_SD_STATE_READY;\n        hsd->Context = SD_CONTEXT_NONE;\n#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)\n        hsd->AbortCpltCallback(hsd);\n#else\n        HAL_SD_AbortCallback(hsd);\n#endif /* USE_HAL_SD_REGISTER_CALLBACKS */\n      }\n#endif // XXX DMA\n    }\n    else\n    {\n      /* Nothing to do */\n    }\n  }\n  else\n  {\n    /* Nothing to do */\n  }\n}\n\n/**\n  * @brief return the SD state\n  * @param hsd: Pointer to sd handle\n  * @retval HAL state\n  */\nHAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)\n{\n  return hsd->State;\n}\n\n/**\n* @brief  Return the SD error code\n* @param  hsd : Pointer to a SD_HandleTypeDef structure that contains\n  *              the configuration information.\n* @retval SD Error Code\n*/\nuint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)\n{\n  return hsd->ErrorCode;\n}\n\n/**\n  * @brief Tx Transfer completed callbacks\n  * @param hsd: Pointer to SD handle\n  * @retval None\n  */\n__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hsd);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SD_TxCpltCallback can be implemented in the user file\n   */\n}\n\n/**\n  * @brief Rx Transfer completed callbacks\n  * @param hsd: Pointer SD handle\n  * @retval None\n  */\n__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hsd);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SD_RxCpltCallback can be implemented in the user file\n   */\n}\n\n/**\n  * @brief SD error callbacks\n  * @param hsd: Pointer SD handle\n  * @retval None\n  */\n__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hsd);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SD_ErrorCallback can be implemented in the user file\n   */\n}\n\n/**\n  * @brief SD Abort callbacks\n  * @param hsd: Pointer SD handle\n  * @retval None\n  */\n__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hsd);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SD_AbortCallback can be implemented in the user file\n   */\n}\n\n#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)\n/**\n  * @brief  Register a User SD Callback\n  *         To be used instead of the weak (surcharged) predefined callback\n  * @param hsd : SD handle\n  * @param CallbackID : ID of the callback to be registered\n  *        This parameter can be one of the following values:\n  *          @arg @ref HAL_SD_TX_CPLT_CB_ID    SD Tx Complete Callback ID\n  *          @arg @ref HAL_SD_RX_CPLT_CB_ID    SD Rx Complete Callback ID\n  *          @arg @ref HAL_SD_ERROR_CB_ID      SD Error Callback ID\n  *          @arg @ref HAL_SD_ABORT_CB_ID      SD Abort Callback ID\n  *          @arg @ref HAL_SD_MSP_INIT_CB_ID   SD MspInit Callback ID\n  *          @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID\n  * @param pCallback : pointer to the Callback function\n  * @retval status\n  */\nHAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  if(pCallback == NULL)\n  {\n    /* Update the error code */\n    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;\n    return HAL_ERROR;\n  }\n\n  /* Process locked */\n  __HAL_LOCK(hsd);\n\n  if(hsd->State == HAL_SD_STATE_READY)\n  {\n    switch (CallbackID)\n    {\n    case HAL_SD_TX_CPLT_CB_ID :\n      hsd->TxCpltCallback = pCallback;\n      break;\n    case HAL_SD_RX_CPLT_CB_ID :\n      hsd->RxCpltCallback = pCallback;\n      break;\n    case HAL_SD_ERROR_CB_ID :\n      hsd->ErrorCallback = pCallback;\n      break;\n    case HAL_SD_ABORT_CB_ID :\n      hsd->AbortCpltCallback = pCallback;\n      break;\n    case HAL_SD_MSP_INIT_CB_ID :\n      hsd->MspInitCallback = pCallback;\n      break;\n    case HAL_SD_MSP_DEINIT_CB_ID :\n      hsd->MspDeInitCallback = pCallback;\n      break;\n    default :\n      /* Update the error code */\n      hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;\n      /* update return status */\n      status =  HAL_ERROR;\n      break;\n    }\n  }\n  else if (hsd->State == HAL_SD_STATE_RESET)\n  {\n    switch (CallbackID)\n    {\n    case HAL_SD_MSP_INIT_CB_ID :\n      hsd->MspInitCallback = pCallback;\n      break;\n    case HAL_SD_MSP_DEINIT_CB_ID :\n      hsd->MspDeInitCallback = pCallback;\n      break;\n    default :\n      /* Update the error code */\n      hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;\n      /* update return status */\n      status =  HAL_ERROR;\n      break;\n    }\n  }\n  else\n  {\n    /* Update the error code */\n    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;\n    /* update return status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hsd);\n  return status;\n}\n\n/**\n  * @brief  Unregister a User SD Callback\n  *         SD Callback is redirected to the weak (surcharged) predefined callback\n  * @param hsd : SD handle\n  * @param CallbackID : ID of the callback to be unregistered\n  *        This parameter can be one of the following values:\n  *          @arg @ref HAL_SD_TX_CPLT_CB_ID    SD Tx Complete Callback ID\n  *          @arg @ref HAL_SD_RX_CPLT_CB_ID    SD Rx Complete Callback ID\n  *          @arg @ref HAL_SD_ERROR_CB_ID      SD Error Callback ID\n  *          @arg @ref HAL_SD_ABORT_CB_ID      SD Abort Callback ID\n  *          @arg @ref HAL_SD_MSP_INIT_CB_ID   SD MspInit Callback ID\n  *          @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID\n  * @retval status\n  */\nHAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  /* Process locked */\n  __HAL_LOCK(hsd);\n\n  if(hsd->State == HAL_SD_STATE_READY)\n  {\n    switch (CallbackID)\n    {\n    case HAL_SD_TX_CPLT_CB_ID :\n      hsd->TxCpltCallback = HAL_SD_TxCpltCallback;\n      break;\n    case HAL_SD_RX_CPLT_CB_ID :\n      hsd->RxCpltCallback = HAL_SD_RxCpltCallback;\n      break;\n    case HAL_SD_ERROR_CB_ID :\n      hsd->ErrorCallback = HAL_SD_ErrorCallback;\n      break;\n    case HAL_SD_ABORT_CB_ID :\n      hsd->AbortCpltCallback = HAL_SD_AbortCallback;\n      break;\n    case HAL_SD_MSP_INIT_CB_ID :\n      hsd->MspInitCallback = HAL_SD_MspInit;\n      break;\n    case HAL_SD_MSP_DEINIT_CB_ID :\n      hsd->MspDeInitCallback = HAL_SD_MspDeInit;\n      break;\n    default :\n      /* Update the error code */\n      hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;\n      /* update return status */\n      status =  HAL_ERROR;\n      break;\n    }\n  }\n  else if (hsd->State == HAL_SD_STATE_RESET)\n  {\n    switch (CallbackID)\n    {\n    case HAL_SD_MSP_INIT_CB_ID :\n      hsd->MspInitCallback = HAL_SD_MspInit;\n      break;\n    case HAL_SD_MSP_DEINIT_CB_ID :\n      hsd->MspDeInitCallback = HAL_SD_MspDeInit;\n      break;\n    default :\n      /* Update the error code */\n      hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;\n      /* update return status */\n      status =  HAL_ERROR;\n      break;\n    }\n  }\n  else\n  {\n    /* Update the error code */\n    hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK;\n    /* update return status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hsd);\n  return status;\n}\n#endif /* USE_HAL_SD_REGISTER_CALLBACKS */\n\n/**\n  * @}\n  */\n\n/** @addtogroup SD_Exported_Functions_Group3\n *  @brief   management functions\n *\n@verbatim\n  ==============================================================================\n                      ##### Peripheral Control functions #####\n  ==============================================================================\n  [..]\n    This subsection provides a set of functions allowing to control the SD card\n    operations and get the related information\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Returns information the information of the card which are stored on\n  *         the CID register.\n  * @param  hsd: Pointer to SD handle\n  * @param  pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that\n  *         contains all CID register parameters\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)\n{\n  pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U);\n\n  pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U);\n\n  pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U));\n\n  pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU);\n\n  pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U);\n\n  pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U));\n\n  pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U);\n\n  pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U);\n\n  pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U);\n\n  pCID->Reserved2 = 1U;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Returns information the information of the card which are stored on\n  *         the CSD register.\n  * @param  hsd: Pointer to SD handle\n  * @param  pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that\n  *         contains all CSD register parameters\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)\n{\n  pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U);\n\n  pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U);\n\n  pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U);\n\n  pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U);\n\n  pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U);\n\n  pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU);\n\n  pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U);\n\n  pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U);\n\n  pCSD->PartBlockRead   = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U);\n\n  pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U);\n\n  pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U);\n\n  pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U);\n\n  pCSD->Reserved2 = 0U; /*!< Reserved */\n\n  if(hsd->SdCard.CardType == CARD_SDSC)\n  {\n    pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U));\n\n    pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U);\n\n    pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U);\n\n    pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U);\n\n    pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U);\n\n    pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U);\n\n    hsd->SdCard.BlockNbr  = (pCSD->DeviceSize + 1U) ;\n    hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));\n    hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));\n\n    hsd->SdCard.LogBlockNbr =  (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);\n    hsd->SdCard.LogBlockSize = 512U;\n  }\n  else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)\n  {\n    /* Byte 7 */\n    pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U));\n\n    hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U);\n    hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;\n    hsd->SdCard.BlockSize = 512U;\n    hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize;\n  }\n  else\n  {\n    /* Clear all the static flags */\n    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n    hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;\n    hsd->State = HAL_SD_STATE_READY;\n    return HAL_ERROR;\n  }\n\n  pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U);\n\n  pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U);\n\n  pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU);\n\n  pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U);\n\n  pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U);\n\n  pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U);\n\n  pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);\n\n  pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U);\n\n  pCSD->Reserved3 = 0;\n\n  pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U);\n\n  pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U);\n\n  pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U);\n\n  pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U);\n\n  pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U);\n\n  pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U);\n\n  pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);\n\n  pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U);\n\n  pCSD->Reserved4 = 1;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Gets the SD status info.\n  * @param  hsd: Pointer to SD handle\n  * @param  pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that\n  *         will contain the SD card status information\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)\n{\n  uint32_t sd_status[16];\n  uint32_t errorstate;\n\n  errorstate = SD_SendSDStatus(hsd, sd_status);\n  if(errorstate != HAL_SD_ERROR_NONE)\n  {\n    /* Clear all the static flags */\n    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n    hsd->ErrorCode |= errorstate;\n    hsd->State = HAL_SD_STATE_READY;\n    return HAL_ERROR;\n  }\n  else\n  {\n    pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U);\n\n    pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U);\n\n    pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U));\n\n    pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U)    | ((sd_status[1] & 0xFF00U) << 8U) |\n                                  ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U));\n\n    pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU);\n\n    pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U);\n\n    pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U);\n\n    pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU));\n\n    pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U);\n\n    pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U);\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Gets the SD card info.\n  * @param  hsd: Pointer to SD handle\n  * @param  pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that\n  *         will contain the SD card status information\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)\n{\n  pCardInfo->CardType     = (uint32_t)(hsd->SdCard.CardType);\n  pCardInfo->CardVersion  = (uint32_t)(hsd->SdCard.CardVersion);\n  pCardInfo->Class        = (uint32_t)(hsd->SdCard.Class);\n  pCardInfo->RelCardAdd   = (uint32_t)(hsd->SdCard.RelCardAdd);\n  pCardInfo->BlockNbr     = (uint32_t)(hsd->SdCard.BlockNbr);\n  pCardInfo->BlockSize    = (uint32_t)(hsd->SdCard.BlockSize);\n  pCardInfo->LogBlockNbr  = (uint32_t)(hsd->SdCard.LogBlockNbr);\n  pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Enables wide bus operation for the requested card if supported by\n  *         card.\n  * @param  hsd: Pointer to SD handle\n  * @param  WideMode: Specifies the SD card wide bus mode\n  *          This parameter can be one of the following values:\n  *            @arg SDIO_BUS_WIDE_8B: 8-bit data transfer\n  *            @arg SDIO_BUS_WIDE_4B: 4-bit data transfer\n  *            @arg SDIO_BUS_WIDE_1B: 1-bit data transfer\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)\n{\n  SDIO_InitTypeDef Init;\n  uint32_t errorstate;\n\n  /* Check the parameters */\n  assert_param(IS_SDIO_BUS_WIDE(WideMode));\n\n  /* Change State */\n  hsd->State = HAL_SD_STATE_BUSY;\n\n  if(hsd->SdCard.CardType != CARD_SECURED)\n  {\n    if(WideMode == SDIO_BUS_WIDE_8B)\n    {\n      hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;\n    }\n    else if(WideMode == SDIO_BUS_WIDE_4B)\n    {\n      errorstate = SD_WideBus_Enable(hsd);\n\n      hsd->ErrorCode |= errorstate;\n    }\n    else if(WideMode == SDIO_BUS_WIDE_1B)\n    {\n      errorstate = SD_WideBus_Disable(hsd);\n\n      hsd->ErrorCode |= errorstate;\n    }\n    else\n    {\n      /* WideMode is not a valid argument*/\n      hsd->ErrorCode |= HAL_SD_ERROR_PARAM;\n    }\n  }\n  else\n  {\n    /* MMC Card does not support this feature */\n    hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;\n  }\n\n  if(hsd->ErrorCode != HAL_SD_ERROR_NONE)\n  {\n    /* Clear all the static flags */\n    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n    hsd->State = HAL_SD_STATE_READY;\n    return HAL_ERROR;\n  }\n  else\n  {\n    /* Configure the SDIO peripheral */\n    Init.ClockEdge           = hsd->Init.ClockEdge;\n    Init.ClockBypass         = hsd->Init.ClockBypass;\n    Init.ClockPowerSave      = hsd->Init.ClockPowerSave;\n    Init.BusWide             = WideMode;\n    Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;\n    Init.ClockDiv            = hsd->Init.ClockDiv;\n    (void)SDIO_Init(hsd->Instance, Init);\n  }\n\n  /* Change State */\n  hsd->State = HAL_SD_STATE_READY;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Gets the current sd card data state.\n  * @param  hsd: pointer to SD handle\n  * @retval Card state\n  */\nHAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)\n{\n  uint32_t cardstate;\n  uint32_t errorstate;\n  uint32_t resp1 = 0;\n\n  errorstate = SD_SendStatus(hsd, &resp1);\n  if(errorstate != HAL_SD_ERROR_NONE)\n  {\n    hsd->ErrorCode |= errorstate;\n  }\n\n  cardstate = ((resp1 >> 9U) & 0x0FU);\n\n  return (HAL_SD_CardStateTypeDef)cardstate;\n}\n\n/**\n  * @brief  Abort the current transfer and disable the SD.\n  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains\n  *                the configuration information for SD module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)\n{\n  HAL_SD_CardStateTypeDef CardState;\n#if 0 // XXX DMA\n  uint32_t context = hsd->Context;\n#endif // XXX DMA\n\n  /* DIsable All interrupts */\n  __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\\\n                           SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);\n\n  /* Clear All flags */\n  __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);\n\n  CLEAR_BIT(hsd->Instance->DCTRL, SDIO_DCTRL_DTEN);\n\n#if 0 // XXX DMA\n  if ((context & SD_CONTEXT_DMA) != 0U)\n  {\n    /* Disable the SD DMA request */\n    hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);\n\n    /* Abort the SD DMA Tx channel */\n    if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))\n    {\n      if(HAL_DMA_Abort(hsd->hdmatx) != HAL_OK)\n      {\n        hsd->ErrorCode |= HAL_SD_ERROR_DMA;\n      }\n    }\n    /* Abort the SD DMA Rx channel */\n    else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))\n    {\n      if(HAL_DMA_Abort(hsd->hdmarx) != HAL_OK)\n      {\n        hsd->ErrorCode |= HAL_SD_ERROR_DMA;\n      }\n    }\n    else\n    {\n      /* Nothing to do */\n    }\n  }\n#endif // XXX DMA\n\n  hsd->State = HAL_SD_STATE_READY;\n\n  /* Initialize the SD operation */\n  hsd->Context = SD_CONTEXT_NONE;\n\n  CardState = HAL_SD_GetCardState(hsd);\n  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))\n  {\n    hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);\n  }\n  if(hsd->ErrorCode != HAL_SD_ERROR_NONE)\n  {\n    return HAL_ERROR;\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  Abort the current transfer and disable the SD (IT mode).\n  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains\n  *                the configuration information for SD module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)\n{\n#if 0 // XXX DMA\n  HAL_SD_CardStateTypeDef CardState;\n  uint32_t context = hsd->Context;\n#endif // XXX DMA\n\n  /* Disable All interrupts */\n  __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\\\n                           SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);\n\n  CLEAR_BIT(hsd->Instance->DCTRL, SDIO_DCTRL_DTEN);\n\n#if 0 // XXX DMA\n  if ((context & SD_CONTEXT_DMA) != 0U)\n  {\n    /* Disable the SD DMA request */\n    hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);\n\n    /* Abort the SD DMA Tx channel */\n    if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))\n    {\n      hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;\n      if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)\n      {\n        hsd->hdmatx = NULL;\n      }\n    }\n    /* Abort the SD DMA Rx channel */\n    else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))\n    {\n      hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;\n      if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)\n      {\n        hsd->hdmarx = NULL;\n      }\n    }\n    else\n    {\n      /* Nothing to do */\n    }\n  }\n  /* No transfer ongoing on both DMA channels*/\n  else\n  {\n    /* Clear All flags */\n    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);\n\n    CardState = HAL_SD_GetCardState(hsd);\n    hsd->State = HAL_SD_STATE_READY;\n    hsd->Context = SD_CONTEXT_NONE;\n    if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))\n    {\n      hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);\n    }\n    if(hsd->ErrorCode != HAL_SD_ERROR_NONE)\n    {\n      return HAL_ERROR;\n    }\n    else\n    {\n#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)\n      hsd->AbortCpltCallback(hsd);\n#else\n      HAL_SD_AbortCallback(hsd);\n#endif /* USE_HAL_SD_REGISTER_CALLBACKS */\n    }\n  }\n#endif // XXX DMA\n\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Private function ----------------------------------------------------------*/\n/** @addtogroup SD_Private_Functions\n  * @{\n  */\n\n#if 0 // XXX DMA\n/**\n  * @brief  DMA SD transmit process complete callback\n  * @param  hdma: DMA handle\n  * @retval None\n  */\nstatic void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)\n{\n  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);\n\n  /* Enable DATAEND Interrupt */\n  __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DATAEND));\n}\n\n/**\n  * @brief  DMA SD receive process complete callback\n  * @param  hdma: DMA handle\n  * @retval None\n  */\nstatic void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\n{\n  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);\n  uint32_t errorstate;\n\n  /* Send stop command in multiblock write */\n  if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA))\n  {\n    errorstate = SDMMC_CmdStopTransfer(hsd->Instance);\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      hsd->ErrorCode |= errorstate;\n#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)\n      hsd->ErrorCallback(hsd);\n#else\n      HAL_SD_ErrorCallback(hsd);\n#endif\n    }\n  }\n\n  /* Disable the DMA transfer for transmit request by setting the DMAEN bit\n  in the SD DCTRL register */\n  hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);\n\n  /* Clear all the static flags */\n  __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);\n\n  hsd->State = HAL_SD_STATE_READY;\n  hsd->Context = SD_CONTEXT_NONE;\n\n#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)\n  hsd->RxCpltCallback(hsd);\n#else\n  HAL_SD_RxCpltCallback(hsd);\n#endif\n}\n\n/**\n  * @brief  DMA SD communication error callback\n  * @param  hdma: DMA handle\n  * @retval None\n  */\nstatic void SD_DMAError(DMA_HandleTypeDef *hdma)\n{\n  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);\n  HAL_SD_CardStateTypeDef CardState;\n  uint32_t RxErrorCode, TxErrorCode;\n\n  /* if DMA error is FIFO error ignore it */\n  if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)\n  {\n    RxErrorCode = hsd->hdmarx->ErrorCode;\n    TxErrorCode = hsd->hdmatx->ErrorCode;\n    if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE))\n    {\n      /* Clear All flags */\n      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);\n\n      /* Disable All interrupts */\n      __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\\\n        SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);\n\n      hsd->ErrorCode |= HAL_SD_ERROR_DMA;\n      CardState = HAL_SD_GetCardState(hsd);\n      if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))\n      {\n        hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);\n      }\n\n      hsd->State = HAL_SD_STATE_READY;\n      hsd->Context = SD_CONTEXT_NONE;\n    }\n\n#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)\n    hsd->ErrorCallback(hsd);\n#else\n    HAL_SD_ErrorCallback(hsd);\n#endif\n  }\n}\n\n/**\n  * @brief  DMA SD Tx Abort callback\n  * @param  hdma: DMA handle\n  * @retval None\n  */\nstatic void SD_DMATxAbort(DMA_HandleTypeDef *hdma)\n{\n  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);\n  HAL_SD_CardStateTypeDef CardState;\n\n  /* Clear All flags */\n  __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);\n\n  CardState = HAL_SD_GetCardState(hsd);\n  hsd->State = HAL_SD_STATE_READY;\n  hsd->Context = SD_CONTEXT_NONE;\n  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))\n  {\n    hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);\n  }\n\n  if(hsd->ErrorCode == HAL_SD_ERROR_NONE)\n  {\n#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)\n    hsd->AbortCpltCallback(hsd);\n#else\n    HAL_SD_AbortCallback(hsd);\n#endif\n  }\n  else\n  {\n#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)\n    hsd->ErrorCallback(hsd);\n#else\n    HAL_SD_ErrorCallback(hsd);\n#endif\n  }\n}\n\n/**\n  * @brief  DMA SD Rx Abort callback\n  * @param  hdma: DMA handle\n  * @retval None\n  */\nstatic void SD_DMARxAbort(DMA_HandleTypeDef *hdma)\n{\n  SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);\n  HAL_SD_CardStateTypeDef CardState;\n\n  /* Clear All flags */\n  __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);\n\n  CardState = HAL_SD_GetCardState(hsd);\n  hsd->State = HAL_SD_STATE_READY;\n  hsd->Context = SD_CONTEXT_NONE;\n  if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))\n  {\n    hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);\n  }\n\n  if(hsd->ErrorCode == HAL_SD_ERROR_NONE)\n  {\n#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)\n    hsd->AbortCpltCallback(hsd);\n#else\n    HAL_SD_AbortCallback(hsd);\n#endif\n  }\n  else\n  {\n#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)\n    hsd->ErrorCallback(hsd);\n#else\n    HAL_SD_ErrorCallback(hsd);\n#endif\n  }\n}\n#endif // XXX DMA\n\n/**\n  * @brief  Initializes the sd card.\n  * @param  hsd: Pointer to SD handle\n  * @retval SD Card error state\n  */\nstatic uint32_t SD_InitCard(SD_HandleTypeDef *hsd)\n{\n  HAL_SD_CardCSDTypeDef CSD;\n  uint32_t errorstate;\n  uint16_t sd_rca = 1U;\n\n  /* Check the power State */\n  if(SDIO_GetPowerState(hsd->Instance) == 0U)\n  {\n    /* Power off */\n    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;\n  }\n\n  if(hsd->SdCard.CardType != CARD_SECURED)\n  {\n    /* Send CMD2 ALL_SEND_CID */\n    errorstate = SDMMC_CmdSendCID(hsd->Instance);\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      return errorstate;\n    }\n    else\n    {\n      /* Get Card identification number data */\n      hsd->CID[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);\n      hsd->CID[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);\n      hsd->CID[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);\n      hsd->CID[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);\n    }\n  }\n\n  if(hsd->SdCard.CardType != CARD_SECURED)\n  {\n    /* Send CMD3 SET_REL_ADDR with argument 0 */\n    /* SD Card publishes its RCA. */\n    errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      return errorstate;\n    }\n  }\n  if(hsd->SdCard.CardType != CARD_SECURED)\n  {\n    /* Get the SD card RCA */\n    hsd->SdCard.RelCardAdd = sd_rca;\n\n    /* Send CMD9 SEND_CSD with argument as card's RCA */\n    errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      return errorstate;\n    }\n    else\n    {\n      /* Get Card Specific Data */\n      hsd->CSD[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);\n      hsd->CSD[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);\n      hsd->CSD[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);\n      hsd->CSD[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);\n    }\n  }\n\n  /* Get the Card Class */\n  hsd->SdCard.Class = (SDIO_GetResponse(hsd->Instance, SDIO_RESP2) >> 20U);\n\n  /* Get CSD parameters */\n  if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK)\n  {\n    return HAL_SD_ERROR_UNSUPPORTED_FEATURE;\n  }\n\n  /* Select the Card */\n  errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));\n  if(errorstate != HAL_SD_ERROR_NONE)\n  {\n    return errorstate;\n  }\n\n  /* Configure SDIO peripheral interface */\n  (void)SDIO_Init(hsd->Instance, hsd->Init);\n\n  /* All cards are initialized */\n  return HAL_SD_ERROR_NONE;\n}\n\n/**\n  * @brief  Enquires cards about their operating voltage and configures clock\n  *         controls and stores SD information that will be needed in future\n  *         in the SD handle.\n  * @param  hsd: Pointer to SD handle\n  * @retval error state\n  */\nstatic uint32_t SD_PowerON(SD_HandleTypeDef *hsd)\n{\n  __IO uint32_t count = 0U;\n  uint32_t response = 0U, validvoltage = 0U;\n  uint32_t errorstate;\n\n  /* CMD0: GO_IDLE_STATE */\n  errorstate = SDMMC_CmdGoIdleState(hsd->Instance);\n  if(errorstate != HAL_SD_ERROR_NONE)\n  {\n    return errorstate;\n  }\n\n  /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */\n  errorstate = SDMMC_CmdOperCond(hsd->Instance);\n  if(errorstate != HAL_SD_ERROR_NONE)\n  {\n    hsd->SdCard.CardVersion = CARD_V1_X;\n    /* CMD0: GO_IDLE_STATE */\n    errorstate = SDMMC_CmdGoIdleState(hsd->Instance);\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      return errorstate;\n    }\n  }\n  else\n  {\n    hsd->SdCard.CardVersion = CARD_V2_X;\n  }\n\n  if( hsd->SdCard.CardVersion == CARD_V2_X)\n  {\n    /* SEND CMD55 APP_CMD with RCA as 0 */\n    errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      return HAL_SD_ERROR_UNSUPPORTED_FEATURE;\n    }\n  }\n  /* SD CARD */\n  /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */\n  while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))\n  {\n    /* SEND CMD55 APP_CMD with RCA as 0 */\n    errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      return errorstate;\n    }\n\n    /* Send CMD41 */\n    errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY);\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      return HAL_SD_ERROR_UNSUPPORTED_FEATURE;\n    }\n\n    /* Get command response */\n    response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);\n\n    /* Get operating voltage */\n    validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);\n\n    count++;\n  }\n\n  if(count >= SDMMC_MAX_VOLT_TRIAL)\n  {\n    return HAL_SD_ERROR_INVALID_VOLTRANGE;\n  }\n\n  if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */\n  {\n    hsd->SdCard.CardType = CARD_SDHC_SDXC;\n  }\n  else\n  {\n    hsd->SdCard.CardType = CARD_SDSC;\n  }\n\n  return HAL_SD_ERROR_NONE;\n}\n\n/**\n  * @brief  Turns the SDIO output signals off.\n  * @param  hsd: Pointer to SD handle\n  * @retval None\n  */\nstatic void SD_PowerOFF(SD_HandleTypeDef *hsd)\n{\n  /* Set Power State to OFF */\n  (void)SDIO_PowerState_OFF(hsd->Instance);\n}\n\n/**\n  * @brief  Send Status info command.\n  * @param  hsd: pointer to SD handle\n  * @param  pSDstatus: Pointer to the buffer that will contain the SD card status\n  *         SD Status register)\n  * @retval error state\n  */\nstatic uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)\n{\n  SDIO_DataInitTypeDef config;\n  uint32_t errorstate;\n  uint32_t tickstart = HAL_GetTick();\n  uint32_t count;\n  uint32_t *pData = pSDstatus;\n\n  /* Check SD response */\n  if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)\n  {\n    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;\n  }\n\n  /* Set block size for card if it is not equal to current block size for card */\n  errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);\n  if(errorstate != HAL_SD_ERROR_NONE)\n  {\n    hsd->ErrorCode |= HAL_SD_ERROR_NONE;\n    return errorstate;\n  }\n\n  /* Send CMD55 */\n  errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));\n  if(errorstate != HAL_SD_ERROR_NONE)\n  {\n    hsd->ErrorCode |= HAL_SD_ERROR_NONE;\n    return errorstate;\n  }\n\n  /* Configure the SD DPSM (Data Path State Machine) */\n  config.DataTimeOut   = SDMMC_DATATIMEOUT;\n  config.DataLength    = 64U;\n  config.DataBlockSize = SDIO_DATABLOCK_SIZE_64B;\n  config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;\n  config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;\n  config.DPSM          = SDIO_DPSM_ENABLE;\n  (void)SDIO_ConfigData(hsd->Instance, &config);\n\n  /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */\n  errorstate = SDMMC_CmdStatusRegister(hsd->Instance);\n  if(errorstate != HAL_SD_ERROR_NONE)\n  {\n    hsd->ErrorCode |= HAL_SD_ERROR_NONE;\n    return errorstate;\n  }\n\n  /* Get status data */\n  while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))\n  {\n    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))\n    {\n      for(count = 0U; count < 8U; count++)\n      {\n        *pData = SDIO_ReadFIFO(hsd->Instance);\n        pData++;\n      }\n    }\n\n    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)\n    {\n      return HAL_SD_ERROR_TIMEOUT;\n    }\n  }\n\n  if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))\n  {\n    return HAL_SD_ERROR_DATA_TIMEOUT;\n  }\n  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))\n  {\n    return HAL_SD_ERROR_DATA_CRC_FAIL;\n  }\n  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))\n  {\n    return HAL_SD_ERROR_RX_OVERRUN;\n  }\n  else\n  {\n    /* Nothing to do */\n  }\n\n  while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)))\n  {\n    *pData = SDIO_ReadFIFO(hsd->Instance);\n    pData++;\n\n    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)\n    {\n      return HAL_SD_ERROR_TIMEOUT;\n    }\n  }\n\n  /* Clear all the static status flags*/\n  __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);\n\n  return HAL_SD_ERROR_NONE;\n}\n\n/**\n  * @brief  Returns the current card's status.\n  * @param  hsd: Pointer to SD handle\n  * @param  pCardStatus: pointer to the buffer that will contain the SD card\n  *         status (Card Status register)\n  * @retval error state\n  */\nstatic uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)\n{\n  uint32_t errorstate;\n\n  if(pCardStatus == NULL)\n  {\n    return HAL_SD_ERROR_PARAM;\n  }\n\n  /* Send Status command */\n  errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));\n  if(errorstate != HAL_SD_ERROR_NONE)\n  {\n    return errorstate;\n  }\n\n  /* Get SD card status */\n  *pCardStatus = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);\n\n  return HAL_SD_ERROR_NONE;\n}\n\n/**\n  * @brief  Enables the SDIO wide bus mode.\n  * @param  hsd: pointer to SD handle\n  * @retval error state\n  */\nstatic uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)\n{\n  uint32_t scr[2U] = {0U, 0U};\n  uint32_t errorstate;\n\n  if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)\n  {\n    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;\n  }\n\n  /* Get SCR Register */\n  errorstate = SD_FindSCR(hsd, scr);\n  if(errorstate != HAL_SD_ERROR_NONE)\n  {\n    return errorstate;\n  }\n\n  /* If requested card supports wide bus operation */\n  if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)\n  {\n    /* Send CMD55 APP_CMD with argument as card's RCA.*/\n    errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      return errorstate;\n    }\n\n    /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */\n    errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      return errorstate;\n    }\n\n    return HAL_SD_ERROR_NONE;\n  }\n  else\n  {\n    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;\n  }\n}\n\n/**\n  * @brief  Disables the SDIO wide bus mode.\n  * @param  hsd: Pointer to SD handle\n  * @retval error state\n  */\nstatic uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)\n{\n  uint32_t scr[2U] = {0U, 0U};\n  uint32_t errorstate;\n\n  if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)\n  {\n    return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;\n  }\n\n  /* Get SCR Register */\n  errorstate = SD_FindSCR(hsd, scr);\n  if(errorstate != HAL_SD_ERROR_NONE)\n  {\n    return errorstate;\n  }\n\n  /* If requested card supports 1 bit mode operation */\n  if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)\n  {\n    /* Send CMD55 APP_CMD with argument as card's RCA */\n    errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      return errorstate;\n    }\n\n    /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */\n    errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);\n    if(errorstate != HAL_SD_ERROR_NONE)\n    {\n      return errorstate;\n    }\n\n    return HAL_SD_ERROR_NONE;\n  }\n  else\n  {\n    return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;\n  }\n}\n\n\n/**\n  * @brief  Finds the SD card SCR register value.\n  * @param  hsd: Pointer to SD handle\n  * @param  pSCR: pointer to the buffer that will contain the SCR value\n  * @retval error state\n  */\nstatic uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)\n{\n  SDIO_DataInitTypeDef config;\n  uint32_t errorstate;\n  uint32_t tickstart = HAL_GetTick();\n  uint32_t index = 0U;\n  uint32_t tempscr[2U] = {0U, 0U};\n  uint32_t *scr = pSCR;\n\n  /* Set Block Size To 8 Bytes */\n  errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);\n  if(errorstate != HAL_SD_ERROR_NONE)\n  {\n    return errorstate;\n  }\n\n  /* Send CMD55 APP_CMD with argument as card's RCA */\n  errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));\n  if(errorstate != HAL_SD_ERROR_NONE)\n  {\n    return errorstate;\n  }\n\n  config.DataTimeOut   = SDMMC_DATATIMEOUT;\n  config.DataLength    = 8U;\n  config.DataBlockSize = SDIO_DATABLOCK_SIZE_8B;\n  config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;\n  config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;\n  config.DPSM          = SDIO_DPSM_ENABLE;\n  (void)SDIO_ConfigData(hsd->Instance, &config);\n\n  /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */\n  errorstate = SDMMC_CmdSendSCR(hsd->Instance);\n  if(errorstate != HAL_SD_ERROR_NONE)\n  {\n    return errorstate;\n  }\n\n  while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))\n  {\n    if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))\n    {\n      *(tempscr + index) = SDIO_ReadFIFO(hsd->Instance);\n      index++;\n    }\n\n    if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)\n    {\n      return HAL_SD_ERROR_TIMEOUT;\n    }\n  }\n\n  if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))\n  {\n    __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);\n\n    return HAL_SD_ERROR_DATA_TIMEOUT;\n  }\n  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))\n  {\n    __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);\n\n    return HAL_SD_ERROR_DATA_CRC_FAIL;\n  }\n  else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))\n  {\n    __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);\n\n    return HAL_SD_ERROR_RX_OVERRUN;\n  }\n  else\n  {\n    /* No error flag set */\n    /* Clear all the static flags */\n    __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);\n\n    *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24)  | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\\\n            ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));\n    scr++;\n    *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24)  | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\\\n            ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));\n\n  }\n\n  return HAL_SD_ERROR_NONE;\n}\n\n/**\n  * @brief  Wrap up reading in non-blocking mode.\n  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains\n  *              the configuration information.\n  * @retval None\n  */\nstatic void SD_Read_IT(SD_HandleTypeDef *hsd)\n{\n  uint32_t count, data, dataremaining;\n  uint8_t* tmp;\n\n  tmp = hsd->pRxBuffPtr;\n  dataremaining = hsd->RxXferSize;\n\n  if (dataremaining > 0U)\n  {\n    /* Read data from SDIO Rx FIFO */\n    for(count = 0U; count < 8U; count++)\n    {\n      data = SDIO_ReadFIFO(hsd->Instance);\n      *tmp = (uint8_t)(data & 0xFFU);\n      tmp++;\n      dataremaining--;\n      *tmp = (uint8_t)((data >> 8U) & 0xFFU);\n      tmp++;\n      dataremaining--;\n      *tmp = (uint8_t)((data >> 16U) & 0xFFU);\n      tmp++;\n      dataremaining--;\n      *tmp = (uint8_t)((data >> 24U) & 0xFFU);\n      tmp++;\n      dataremaining--;\n    }\n\n    hsd->pRxBuffPtr = tmp;\n    hsd->RxXferSize = dataremaining;\n  }\n}\n\n/**\n  * @brief  Wrap up writing in non-blocking mode.\n  * @param  hsd: pointer to a SD_HandleTypeDef structure that contains\n  *              the configuration information.\n  * @retval None\n  */\nstatic void SD_Write_IT(SD_HandleTypeDef *hsd)\n{\n  uint32_t count, data, dataremaining;\n  uint8_t* tmp;\n\n  tmp = hsd->pTxBuffPtr;\n  dataremaining = hsd->TxXferSize;\n\n  if (dataremaining > 0U)\n  {\n    /* Write data to SDIO Tx FIFO */\n    for(count = 0U; count < 8U; count++)\n    {\n      data = (uint32_t)(*tmp);\n      tmp++;\n      dataremaining--;\n      data |= ((uint32_t)(*tmp) << 8U);\n      tmp++;\n      dataremaining--;\n      data |= ((uint32_t)(*tmp) << 16U);\n      tmp++;\n      dataremaining--;\n      data |= ((uint32_t)(*tmp) << 24U);\n      tmp++;\n      dataremaining--;\n      (void)SDIO_WriteFIFO(hsd->Instance, &data);\n    }\n\n    hsd->pTxBuffPtr = tmp;\n    hsd->TxXferSize = dataremaining;\n  }\n}\n\n/**\n  * @}\n  */\n\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\n          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\n          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n\n#endif /* HAL_SD_MODULE_ENABLED */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_hal_sd.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_sd.h\n  * @author  MCD Application Team\n  * @version V1.7.1\n  * @date    14-April-2017\n  * @brief   Header file of SD HAL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_SD_H\n#define __STM32F4xx_HAL_SD_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \\\n    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \\\n    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \\\n    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_ll_sdmmc.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup SD SD\n  * @brief SD HAL module driver\n  * @{\n  */\n\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup SD_Exported_Types SD Exported Types\n  * @{\n  */\n\n/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure\n  * @{\n  */\ntypedef enum\n{\n  HAL_SD_STATE_RESET                  = 0x00000000U,  /*!< SD not yet initialized or disabled  */\n  HAL_SD_STATE_READY                  = 0x00000001U,  /*!< SD initialized and ready for use    */\n  HAL_SD_STATE_TIMEOUT                = 0x00000002U,  /*!< SD Timeout state                    */\n  HAL_SD_STATE_BUSY                   = 0x00000003U,  /*!< SD process ongoing                  */\n  HAL_SD_STATE_PROGRAMMING            = 0x00000004U,  /*!< SD Programming State                */\n  HAL_SD_STATE_RECEIVING              = 0x00000005U,  /*!< SD Receiving State                  */\n  HAL_SD_STATE_TRANSFER               = 0x00000006U,  /*!< SD Transfert State                  */\n  HAL_SD_STATE_ERROR                  = 0x0000000FU   /*!< SD is in error state                */\n}HAL_SD_StateTypeDef;\n/**\n  * @}\n  */\n\n/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure\n  * @{\n  */\ntypedef uint32_t HAL_SD_CardStateTypeDef;\n\n#define HAL_SD_CARD_READY          0x00000001U  /*!< Card state is ready                     */\n#define HAL_SD_CARD_IDENTIFICATION 0x00000002U  /*!< Card is in identification state         */\n#define HAL_SD_CARD_STANDBY        0x00000003U  /*!< Card is in standby state                */\n#define HAL_SD_CARD_TRANSFER       0x00000004U  /*!< Card is in transfer state               */\n#define HAL_SD_CARD_SENDING        0x00000005U  /*!< Card is sending an operation            */\n#define HAL_SD_CARD_RECEIVING      0x00000006U  /*!< Card is receiving operation information */\n#define HAL_SD_CARD_PROGRAMMING    0x00000007U  /*!< Card is in programming state            */\n#define HAL_SD_CARD_DISCONNECTED   0x00000008U  /*!< Card is disconnected                    */\n#define HAL_SD_CARD_ERROR          0x000000FFU  /*!< Card response Error                     */\n/**\n  * @}\n  */\n\n/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition\n  * @{\n  */\n#define SD_InitTypeDef      SDIO_InitTypeDef\n#define SD_TypeDef          SDIO_TypeDef\n\n/**\n  * @brief  SD Card Information Structure definition\n  */\ntypedef struct\n{\n  uint32_t CardType;                     /*!< Specifies the card Type                         */\n\n  uint32_t CardVersion;                  /*!< Specifies the card version                      */\n\n  uint32_t Class;                        /*!< Specifies the class of the card class           */\n\n  uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address             */\n\n  uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */\n\n  uint32_t BlockSize;                    /*!< Specifies one block size in bytes               */\n\n  uint32_t LogBlockNbr;                  /*!< Specifies the Card logical Capacity in blocks   */\n\n  uint32_t LogBlockSize;                 /*!< Specifies logical block size in bytes           */\n\n}HAL_SD_CardInfoTypeDef;\n\n/**\n  * @brief  SD handle Structure definition\n  */\n#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)\ntypedef struct __SD_HandleTypeDef\n#else\ntypedef struct\n#endif /* USE_HAL_SD_REGISTER_CALLBACKS */\n{\n  SD_TypeDef                   *Instance;        /*!< SD registers base address           */\n\n  SD_InitTypeDef               Init;             /*!< SD required parameters              */\n\n  HAL_LockTypeDef              Lock;             /*!< SD locking object                   */\n\n  uint8_t                      *pTxBuffPtr;      /*!< Pointer to SD Tx transfer Buffer    */\n\n  uint32_t                     TxXferSize;       /*!< SD Tx Transfer size                 */\n\n  uint8_t                      *pRxBuffPtr;      /*!< Pointer to SD Rx transfer Buffer    */\n\n  uint32_t                     RxXferSize;       /*!< SD Rx Transfer size                 */\n\n  __IO uint32_t                Context;          /*!< SD transfer context                 */\n\n  __IO HAL_SD_StateTypeDef     State;            /*!< SD card State                       */\n\n  __IO uint32_t                ErrorCode;        /*!< SD Card Error codes                 */\n\n#if 0 // XXX DMA\n  DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters         */\n\n  DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters         */\n#endif // XXX DMA\n\n  HAL_SD_CardInfoTypeDef       SdCard;           /*!< SD Card information                 */\n\n  uint32_t                     CSD[4];           /*!< SD card specific data table         */\n\n  uint32_t                     CID[4];           /*!< SD card identification number table */\n\n#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)\n  void (* TxCpltCallback)                 (struct __SD_HandleTypeDef *hsd);\n  void (* RxCpltCallback)                 (struct __SD_HandleTypeDef *hsd);\n  void (* ErrorCallback)                  (struct __SD_HandleTypeDef *hsd);\n  void (* AbortCpltCallback)              (struct __SD_HandleTypeDef *hsd);\n\n  void (* MspInitCallback)                (struct __SD_HandleTypeDef *hsd);\n  void (* MspDeInitCallback)              (struct __SD_HandleTypeDef *hsd);\n#endif /* USE_HAL_SD_REGISTER_CALLBACKS */\n}SD_HandleTypeDef;\n\n/**\n  * @}\n  */\n\n/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register\n  * @{\n  */\ntypedef struct\n{\n  __IO uint8_t  CSDStruct;            /*!< CSD structure                         */\n  __IO uint8_t  SysSpecVersion;       /*!< System specification version          */\n  __IO uint8_t  Reserved1;            /*!< Reserved                              */\n  __IO uint8_t  TAAC;                 /*!< Data read access time 1               */\n  __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */\n  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */\n  __IO uint16_t CardComdClasses;      /*!< Card command classes                  */\n  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */\n  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */\n  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */\n  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */\n  __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */\n  __IO uint8_t  Reserved2;            /*!< Reserved                              */\n  __IO uint32_t DeviceSize;           /*!< Device Size                           */\n  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */\n  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */\n  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */\n  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */\n  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */\n  __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */\n  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */\n  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */\n  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */\n  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */\n  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */\n  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */\n  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */\n  __IO uint8_t  Reserved3;            /*!< Reserved                              */\n  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */\n  __IO uint8_t  FileFormatGroup;      /*!< File format group                     */\n  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */\n  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */\n  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */\n  __IO uint8_t  FileFormat;           /*!< File format                           */\n  __IO uint8_t  ECC;                  /*!< ECC code                              */\n  __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */\n  __IO uint8_t  Reserved4;            /*!< Always 1                              */\n}HAL_SD_CardCSDTypeDef;\n/**\n  * @}\n  */\n\n/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register\n  * @{\n  */\ntypedef struct\n{\n  __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */\n  __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */\n  __IO uint32_t ProdName1;       /*!< Product Name part1    */\n  __IO uint8_t  ProdName2;       /*!< Product Name part2    */\n  __IO uint8_t  ProdRev;         /*!< Product Revision      */\n  __IO uint32_t ProdSN;          /*!< Product Serial Number */\n  __IO uint8_t  Reserved1;       /*!< Reserved1             */\n  __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */\n  __IO uint8_t  CID_CRC;         /*!< CID CRC               */\n  __IO uint8_t  Reserved2;       /*!< Always 1              */\n\n}HAL_SD_CardCIDTypeDef;\n/**\n  * @}\n  */\n\n/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13\n  * @{\n  */\ntypedef struct\n{\n  __IO uint8_t  DataBusWidth;           /*!< Shows the currently defined data bus width                 */\n  __IO uint8_t  SecuredMode;            /*!< Card is in secured mode of operation                       */\n  __IO uint16_t CardType;               /*!< Carries information about card type                        */\n  __IO uint32_t ProtectedAreaSize;      /*!< Carries information about the capacity of protected area   */\n  __IO uint8_t  SpeedClass;             /*!< Carries information about the speed class of the card      */\n  __IO uint8_t  PerformanceMove;        /*!< Carries information about the card's performance move      */\n  __IO uint8_t  AllocationUnitSize;     /*!< Carries information about the card's allocation unit size  */\n  __IO uint16_t EraseSize;              /*!< Determines the number of AUs to be erased in one operation */\n  __IO uint8_t  EraseTimeout;           /*!< Determines the timeout for any number of AU erase          */\n  __IO uint8_t  EraseOffset;            /*!< Carries information about the erase offset                 */\n\n}HAL_SD_CardStatusTypeDef;\n/**\n  * @}\n  */\n\n#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)\n/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition\n  * @{\n  */\ntypedef enum\n{\n  HAL_SD_TX_CPLT_CB_ID                 = 0x00U,  /*!< SD Tx Complete Callback ID                     */\n  HAL_SD_RX_CPLT_CB_ID                 = 0x01U,  /*!< SD Rx Complete Callback ID                     */\n  HAL_SD_ERROR_CB_ID                   = 0x02U,  /*!< SD Error Callback ID                           */\n  HAL_SD_ABORT_CB_ID                   = 0x03U,  /*!< SD Abort Callback ID                           */\n\n  HAL_SD_MSP_INIT_CB_ID                = 0x10U,  /*!< SD MspInit Callback ID                         */\n  HAL_SD_MSP_DEINIT_CB_ID              = 0x11U   /*!< SD MspDeInit Callback ID                       */\n}HAL_SD_CallbackIDTypeDef;\n/**\n  * @}\n  */\n\n/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition\n  * @{\n  */\ntypedef void (*pSD_CallbackTypeDef)           (SD_HandleTypeDef *hsd);\n/**\n  * @}\n  */\n#endif /* USE_HAL_SD_REGISTER_CALLBACKS */\n/**\n  * @}\n  */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup SD_Exported_Constants Exported Constants\n  * @{\n  */\n\n#define BLOCKSIZE   512U /*!< Block size is 512 bytes */\n\n/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition\n  * @{\n  */\n#define HAL_SD_ERROR_NONE                     SDMMC_ERROR_NONE                    /*!< No error                                                      */\n#define HAL_SD_ERROR_CMD_CRC_FAIL             SDMMC_ERROR_CMD_CRC_FAIL            /*!< Command response received (but CRC check failed)              */\n#define HAL_SD_ERROR_DATA_CRC_FAIL            SDMMC_ERROR_DATA_CRC_FAIL           /*!< Data block sent/received (CRC check failed)                   */\n#define HAL_SD_ERROR_CMD_RSP_TIMEOUT          SDMMC_ERROR_CMD_RSP_TIMEOUT         /*!< Command response timeout                                      */\n#define HAL_SD_ERROR_DATA_TIMEOUT             SDMMC_ERROR_DATA_TIMEOUT            /*!< Data timeout                                                  */\n#define HAL_SD_ERROR_TX_UNDERRUN              SDMMC_ERROR_TX_UNDERRUN             /*!< Transmit FIFO underrun                                        */\n#define HAL_SD_ERROR_RX_OVERRUN               SDMMC_ERROR_RX_OVERRUN              /*!< Receive FIFO overrun                                          */\n#define HAL_SD_ERROR_ADDR_MISALIGNED          SDMMC_ERROR_ADDR_MISALIGNED         /*!< Misaligned address                                            */\n#define HAL_SD_ERROR_BLOCK_LEN_ERR            SDMMC_ERROR_BLOCK_LEN_ERR           /*!< Transferred block length is not allowed for the card or the\n                                                                                       number of transferred bytes does not match the block length   */\n#define HAL_SD_ERROR_ERASE_SEQ_ERR            SDMMC_ERROR_ERASE_SEQ_ERR           /*!< An error in the sequence of erase command occurs              */\n#define HAL_SD_ERROR_BAD_ERASE_PARAM          SDMMC_ERROR_BAD_ERASE_PARAM         /*!< An invalid selection for erase groups                         */\n#define HAL_SD_ERROR_WRITE_PROT_VIOLATION     SDMMC_ERROR_WRITE_PROT_VIOLATION    /*!< Attempt to program a write protect block                      */\n#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED       SDMMC_ERROR_LOCK_UNLOCK_FAILED      /*!< Sequence or password error has been detected in unlock\n                                                                                       command or if there was an attempt to access a locked card    */\n#define HAL_SD_ERROR_COM_CRC_FAILED           SDMMC_ERROR_COM_CRC_FAILED          /*!< CRC check of the previous command failed                      */\n#define HAL_SD_ERROR_ILLEGAL_CMD              SDMMC_ERROR_ILLEGAL_CMD             /*!< Command is not legal for the card state                       */\n#define HAL_SD_ERROR_CARD_ECC_FAILED          SDMMC_ERROR_CARD_ECC_FAILED         /*!< Card internal ECC was applied but failed to correct the data  */\n#define HAL_SD_ERROR_CC_ERR                   SDMMC_ERROR_CC_ERR                  /*!< Internal card controller error                                */\n#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR      SDMMC_ERROR_GENERAL_UNKNOWN_ERR     /*!< General or unknown error                                      */\n#define HAL_SD_ERROR_STREAM_READ_UNDERRUN     SDMMC_ERROR_STREAM_READ_UNDERRUN    /*!< The card could not sustain data reading in stream rmode       */\n#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN     SDMMC_ERROR_STREAM_WRITE_OVERRUN    /*!< The card could not sustain data programming in stream mode    */\n#define HAL_SD_ERROR_CID_CSD_OVERWRITE        SDMMC_ERROR_CID_CSD_OVERWRITE       /*!< CID/CSD overwrite error                                       */\n#define HAL_SD_ERROR_WP_ERASE_SKIP            SDMMC_ERROR_WP_ERASE_SKIP           /*!< Only partial address space was erased                         */\n#define HAL_SD_ERROR_CARD_ECC_DISABLED        SDMMC_ERROR_CARD_ECC_DISABLED       /*!< Command has been executed without using internal ECC          */\n#define HAL_SD_ERROR_ERASE_RESET              SDMMC_ERROR_ERASE_RESET             /*!< Erase sequence was cleared before executing because an out\n                                                                                       of erase sequence command was received                        */\n#define HAL_SD_ERROR_AKE_SEQ_ERR              SDMMC_ERROR_AKE_SEQ_ERR             /*!< Error in sequence of authentication                           */\n#define HAL_SD_ERROR_INVALID_VOLTRANGE        SDMMC_ERROR_INVALID_VOLTRANGE       /*!< Error in case of invalid voltage range                        */\n#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE        SDMMC_ERROR_ADDR_OUT_OF_RANGE       /*!< Error when addressed block is out of range                    */\n#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE   SDMMC_ERROR_REQUEST_NOT_APPLICABLE  /*!< Error when command request is not applicable                  */\n#define HAL_SD_ERROR_PARAM                    SDMMC_ERROR_INVALID_PARAMETER       /*!< the used parameter is not valid                               */\n#define HAL_SD_ERROR_UNSUPPORTED_FEATURE      SDMMC_ERROR_UNSUPPORTED_FEATURE     /*!< Error when feature is not insupported                         */\n#define HAL_SD_ERROR_BUSY                     SDMMC_ERROR_BUSY                    /*!< Error when transfer process is busy                           */\n#define HAL_SD_ERROR_DMA                      SDMMC_ERROR_DMA                     /*!< Error while DMA transfer                                      */\n#define HAL_SD_ERROR_TIMEOUT                  SDMMC_ERROR_TIMEOUT                 /*!< Timeout error                                                 */\n\n#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)\n#define HAL_SD_ERROR_INVALID_CALLBACK         SDMMC_ERROR_INVALID_PARAMETER       /*!< Invalid callback error                                        */\n#endif /* USE_HAL_SD_REGISTER_CALLBACKS */\n/**\n  * @}\n  */\n\n/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration\n  * @{\n  */\n#define SD_CONTEXT_NONE                            0x00000000U   /*!< None                             */\n#define SD_CONTEXT_READ_SINGLE_BLOCK               0x00000001U   /*!< Read single block operation      */\n#define SD_CONTEXT_READ_MULTIPLE_BLOCK             0x00000002U   /*!< Read multiple blocks operation   */\n#define SD_CONTEXT_WRITE_SINGLE_BLOCK              0x00000010U   /*!< Write single block operation     */\n#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK            0x00000020U   /*!< Write multiple blocks operation  */\n#define SD_CONTEXT_IT                              0x00000008U   /*!< Process in Interrupt mode        */\n#define SD_CONTEXT_DMA                             0x00000080U   /*!< Process in DMA mode              */\n\n/**\n  * @}\n  */\n\n/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards\n  * @{\n  */\n#define CARD_SDSC                  0x00000000U  /*!< SD Standard Capacity <2Go                          */\n#define CARD_SDHC_SDXC             0x00000001U  /*!< SD High Capacity <32Go, SD Extended Capacity <2To  */\n#define CARD_SECURED               0x00000003U\n\n/**\n  * @}\n  */\n\n/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version\n  * @{\n  */\n#define CARD_V1_X                  0x00000000U\n#define CARD_V2_X                  0x00000001U\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup SD_Exported_macros SD Exported Macros\n *  @brief macros to handle interrupts and specific clock configurations\n * @{\n */\n/** @brief Reset SD handle state.\n  * @param  __HANDLE__ : SD handle.\n  * @retval None\n  */\n#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)\n#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \\\n                                                               (__HANDLE__)->State = HAL_SD_STATE_RESET; \\\n                                                               (__HANDLE__)->MspInitCallback = NULL;       \\\n                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \\\n                                                             } while(0)\n#else\n#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_SD_STATE_RESET)\n#endif /* USE_HAL_SD_REGISTER_CALLBACKS */\n\n/**\n  * @brief  Enable the SD device.\n  * @retval None\n  */\n#define __HAL_SD_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)\n\n/**\n  * @brief  Disable the SD device.\n  * @retval None\n  */\n#define __HAL_SD_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)\n\n/**\n  * @brief  Enable the SDMMC DMA transfer.\n  * @retval None\n  */\n#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)\n\n/**\n  * @brief  Disable the SDMMC DMA transfer.\n  * @retval None\n  */\n#define __HAL_SD_DMA_DISABLE(__HANDLE__)  __SDIO_DMA_DISABLE((__HANDLE__)->Instance)\n\n/**\n  * @brief  Enable the SD device interrupt.\n  * @param  __HANDLE__: SD Handle\n  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.\n  *         This parameter can be one or a combination of the following values:\n  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\n  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\n  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\n  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\n  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\n  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt\n  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt\n  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt\n  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt\n  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\n  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt\n  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt\n  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt\n  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\n  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt\n  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt\n  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt\n  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt\n  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt\n  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt\n  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt\n  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt\n  * @retval None\n  */\n#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))\n\n/**\n  * @brief  Disable the SD device interrupt.\n  * @param  __HANDLE__: SD Handle\n  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.\n  *          This parameter can be one or a combination of the following values:\n  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\n  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\n  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\n  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\n  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\n  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt\n  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt\n  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt\n  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt\n  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\n  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt\n  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt\n  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt\n  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\n  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt\n  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt\n  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt\n  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt\n  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt\n  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt\n  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt\n  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt\n  * @retval None\n  */\n#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))\n\n/**\n  * @brief  Check whether the specified SD flag is set or not.\n  * @param  __HANDLE__: SD Handle\n  * @param  __FLAG__: specifies the flag to check.\n  *          This parameter can be one of the following values:\n  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)\n  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\n  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout\n  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout\n  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error\n  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error\n  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)\n  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)\n  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)\n  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)\n  *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress\n  *            @arg SDIO_FLAG_TXACT:    Data transmit in progress\n  *            @arg SDIO_FLAG_RXACT:    Data receive in progress\n  *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty\n  *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full\n  *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full\n  *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full\n  *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty\n  *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty\n  *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO\n  *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO\n  *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received\n  * @retval The new state of SD FLAG (SET or RESET).\n  */\n#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))\n\n/**\n  * @brief  Clear the SD's pending flags.\n  * @param  __HANDLE__: SD Handle\n  * @param  __FLAG__: specifies the flag to clear.\n  *          This parameter can be one or a combination of the following values:\n  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)\n  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\n  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout\n  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout\n  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error\n  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error\n  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)\n  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)\n  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)\n  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)\n  *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received\n  * @retval None\n  */\n#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))\n\n/**\n  * @brief  Check whether the specified SD interrupt has occurred or not.\n  * @param  __HANDLE__: SD Handle\n  * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check.\n  *          This parameter can be one of the following values:\n  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\n  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\n  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\n  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\n  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\n  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt\n  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt\n  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt\n  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt\n  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\n  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt\n  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt\n  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt\n  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\n  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt\n  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt\n  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt\n  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt\n  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt\n  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt\n  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt\n  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt\n  * @retval The new state of SD IT (SET or RESET).\n  */\n#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))\n\n/**\n  * @brief  Clear the SD's interrupt pending bits.\n  * @param  __HANDLE__: SD Handle\n  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.\n  *          This parameter can be one or a combination of the following values:\n  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\n  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\n  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\n  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\n  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\n  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt\n  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt\n  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt\n  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt\n  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt\n  * @retval None\n  */\n#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup SD_Exported_Functions SD Exported Functions\n  * @{\n  */\n\n/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions\n  * @{\n  */\nHAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);\nHAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);\nHAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);\nvoid HAL_SD_MspInit(SD_HandleTypeDef *hsd);\nvoid HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);\n/**\n  * @}\n  */\n\n/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions\n  * @{\n  */\n/* Blocking mode: Polling */\nHAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);\nHAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);\nHAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);\n/* Non-Blocking mode: IT */\nHAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);\nHAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);\n#if 0 // XXX DMA\n/* Non-Blocking mode: DMA */\nHAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);\nHAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);\n#endif // XXX DMA\n\nvoid HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);\n\n/* Callback in non blocking modes (DMA) */\nvoid HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);\nvoid HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);\nvoid HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);\nvoid HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);\n\n#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)\n/* SD callback registering/unregistering */\nHAL_StatusTypeDef HAL_SD_RegisterCallback  (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback);\nHAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId);\n#endif /* USE_HAL_SD_REGISTER_CALLBACKS */\n\n/**\n  * @}\n  */\n\n/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions\n  * @{\n  */\nHAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);\n/**\n  * @}\n  */\n\n/** @defgroup SD_Exported_Functions_Group4 SD card related functions\n  * @{\n  */\nHAL_StatusTypeDef       HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);\nHAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);\nHAL_StatusTypeDef       HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);\nHAL_StatusTypeDef       HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);\nHAL_StatusTypeDef       HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);\nHAL_StatusTypeDef       HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);\n/**\n  * @}\n  */\n\n/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions\n  * @{\n  */\nHAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);\nuint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);\n/**\n  * @}\n  */\n\n/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management\n  * @{\n  */\nHAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);\nHAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);\n/**\n  * @}\n  */\n\n/* Private types -------------------------------------------------------------*/\n/** @defgroup SD_Private_Types SD Private Types\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/* Private defines -----------------------------------------------------------*/\n/** @defgroup SD_Private_Defines SD Private Defines\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/* Private variables ---------------------------------------------------------*/\n/** @defgroup SD_Private_Variables SD Private Variables\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup SD_Private_Constants SD Private Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup SD_Private_Macros SD Private Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/* Private functions prototypes ----------------------------------------------*/\n/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/* Private functions ---------------------------------------------------------*/\n/** @defgroup SD_Private_Functions SD Private Functions\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\n          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\n          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif /* __STM32F4xx_HAL_SD_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_hal_spi.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_spi.c\n  * @author  MCD Application Team\n  * @version V1.7.1\n  * @date    14-April-2017\n  * @brief   SPI HAL module driver.\n  *          This file provides firmware functions to manage the following\n  *          functionalities of the Serial Peripheral Interface (SPI) peripheral:\n  *           + Initialization and de-initialization functions\n  *           + IO operation functions\n  *           + Peripheral Control functions\n  *           + Peripheral State functions\n  *\n  @verbatim\n  ==============================================================================\n                        ##### How to use this driver #####\n  ==============================================================================\n    [..]\n      The SPI HAL driver can be used as follows:\n\n      (#) Declare a SPI_HandleTypeDef handle structure, for example:\n          SPI_HandleTypeDef  hspi;\n\n      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:\n          (##) Enable the SPIx interface clock\n          (##) SPI pins configuration\n              (+++) Enable the clock for the SPI GPIOs\n              (+++) Configure these SPI pins as alternate function push-pull\n          (##) NVIC configuration if you need to use interrupt process\n              (+++) Configure the SPIx interrupt priority\n              (+++) Enable the NVIC SPI IRQ handle\n          (##) DMA Configuration if you need to use DMA process\n              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream\n              (+++) Enable the DMAx clock\n              (+++) Configure the DMA handle parameters\n              (+++) Configure the DMA Tx or Rx stream\n              (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle\n              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx stream\n\n      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS\n          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.\n\n      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:\n          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)\n              by calling the customized HAL_SPI_MspInit() API.\n     [..]\n       Circular mode restriction:\n      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:\n          (##) Master 2Lines RxOnly\n          (##) Master 1Line Rx\n      (#) The CRC feature is not managed when the DMA circular mode is enabled\n      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs\n          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks\n     [..]\n       Master Receive mode restriction:\n      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or\n          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI\n          does not initiate a new transfer the following procedure has to be respected:\n          (##) HAL_SPI_DeInit()\n          (##) HAL_SPI_Init()\n\n  @endverbatim\n\n    Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,\n    the following tables resume the max SPI frequency reached with data size 8bits/16bits,\n    according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :\n\n    DataSize = SPI_DATASIZE_8BIT:\n    +----------------------------------------------------------------------------------------------+\n    |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |\n    | Process | Tranfert mode  |---------------------|----------------------|----------------------|\n    |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |\n    |==============================================================================================|\n    |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |\n    |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\n    |    /    |     Interrupt  | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |\n    |    R    |----------------|----------|----------|-----------|----------|-----------|----------|\n    |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |\n    |=========|================|==========|==========|===========|==========|===========|==========|\n    |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |\n    |         |----------------|----------|----------|-----------|----------|-----------|----------|\n    |    R    |     Interrupt  | Fpclk/8  | Fpclk/8  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |\n    |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\n    |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |\n    |=========|================|==========|==========|===========|==========|===========|==========|\n    |         |     Polling    | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |\n    |         |----------------|----------|----------|-----------|----------|-----------|----------|\n    |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |\n    |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\n    |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|\n    +----------------------------------------------------------------------------------------------+\n\n    DataSize = SPI_DATASIZE_16BIT:\n    +----------------------------------------------------------------------------------------------+\n    |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |\n    | Process | Tranfert mode  |---------------------|----------------------|----------------------|\n    |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |\n    |==============================================================================================|\n    |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |\n    |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\n    |    /    |     Interrupt  | Fpclk/4  | Fpclk/4  |    NA     |    NA    |    NA     |   NA     |\n    |    R    |----------------|----------|----------|-----------|----------|-----------|----------|\n    |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |\n    |=========|================|==========|==========|===========|==========|===========|==========|\n    |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/32  | Fpclk/2  |\n    |         |----------------|----------|----------|-----------|----------|-----------|----------|\n    |    R    |     Interrupt  | Fpclk/4  | Fpclk/4  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |\n    |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\n    |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |\n    |=========|================|==========|==========|===========|==========|===========|==========|\n    |         |     Polling    | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/32 |\n    |         |----------------|----------|----------|-----------|----------|-----------|----------|\n    |    T    |     Interrupt  | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |\n    |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\n    |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|\n    +----------------------------------------------------------------------------------------------+\n     [..]\n       (@) The max SPI frequency depend on SPI data size (8bits, 16bits),\n           SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).\n       (@)\n            (+@) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()\n            (+@) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()\n            (+@) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n/** @defgroup SPI SPI\n  * @brief SPI HAL module driver\n  * @{\n  */\n#ifdef HAL_SPI_MODULE_ENABLED\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private defines -----------------------------------------------------------*/\n/** @defgroup SPI_Private_Constants SPI Private Constants\n  * @{\n  */\n#define SPI_DEFAULT_TIMEOUT 100U\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\n/** @addtogroup SPI_Private_Functions\n  * @{\n  */\n#if 0 // XXX DMA\nstatic void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);\nstatic void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\nstatic void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);\nstatic void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);\nstatic void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);\nstatic void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);\nstatic void SPI_DMAError(DMA_HandleTypeDef *hdma);\nstatic void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);\nstatic void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);\nstatic void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);\n#endif // XXX DMA\nstatic HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart);\nstatic void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\nstatic void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\nstatic void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\nstatic void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\nstatic void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\nstatic void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\nstatic void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\nstatic void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\n#if (USE_SPI_CRC != 0U)\nstatic void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);\nstatic void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);\nstatic void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);\nstatic void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);\n#endif /* USE_SPI_CRC */\nstatic void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);\nstatic void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);\nstatic void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);\nstatic void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);\nstatic void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);\nstatic HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup SPI_Exported_Functions SPI Exported Functions\n  * @{\n  */\n\n/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions\n *  @brief    Initialization and Configuration functions\n *\n@verbatim\n ===============================================================================\n              ##### Initialization and de-initialization functions #####\n ===============================================================================\n    [..]  This subsection provides a set of functions allowing to initialize and\n          de-initialize the SPIx peripheral:\n\n      (+) User must implement HAL_SPI_MspInit() function in which he configures\n          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\n\n      (+) Call the function HAL_SPI_Init() to configure the selected device with\n          the selected configuration:\n        (++) Mode\n        (++) Direction\n        (++) Data Size\n        (++) Clock Polarity and Phase\n        (++) NSS Management\n        (++) BaudRate Prescaler\n        (++) FirstBit\n        (++) TIMode\n        (++) CRC Calculation\n        (++) CRC Polynomial if CRC enabled\n\n      (+) Call the function HAL_SPI_DeInit() to restore the default configuration\n          of the selected SPIx peripheral.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Initialize the SPI according to the specified parameters\n  *         in the SPI_InitTypeDef and initialize the associated handle.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)\n{\n  /* Check the SPI handle allocation */\n  if(hspi == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));\n  assert_param(IS_SPI_MODE(hspi->Init.Mode));\n  assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));\n  assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));\n  assert_param(IS_SPI_NSS(hspi->Init.NSS));\n  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));\n  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));\n  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));\n  if(hspi->Init.TIMode == SPI_TIMODE_DISABLE)\n  {\n    assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));\n    assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));\n  }\n#if (USE_SPI_CRC != 0U)\n  assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));\n  }\n#else\n  hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\n#endif /* USE_SPI_CRC */\n\n  if(hspi->State == HAL_SPI_STATE_RESET)\n  {\n    /* Allocate lock resource and initialize it */\n    hspi->Lock = HAL_UNLOCKED;\n\n    /* Init the low level hardware : GPIO, CLOCK, NVIC... */\n    HAL_SPI_MspInit(hspi);\n  }\n\n  hspi->State = HAL_SPI_STATE_BUSY;\n\n  /* Disable the selected SPI peripheral */\n  __HAL_SPI_DISABLE(hspi);\n\n  /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/\n  /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,\n  Communication speed, First bit and CRC calculation state */\n  WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |\n                                  hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |\n                                  hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation) );\n\n  /* Configure : NSS management */\n  WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));\n\n#if (USE_SPI_CRC != 0U)\n  /*---------------------------- SPIx CRCPOLY Configuration ------------------*/\n  /* Configure : CRC Polynomial */\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);\n  }\n#endif /* USE_SPI_CRC */\n\n#if defined(SPI_I2SCFGR_I2SMOD)\n  /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */\n  CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);\n#endif /* USE_SPI_CRC */\n\n  hspi->ErrorCode = HAL_SPI_ERROR_NONE;\n  hspi->State     = HAL_SPI_STATE_READY;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  De Initialize the SPI peripheral.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)\n{\n  /* Check the SPI handle allocation */\n  if(hspi == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check SPI Instance parameter */\n  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));\n\n  hspi->State = HAL_SPI_STATE_BUSY;\n\n  /* Disable the SPI Peripheral Clock */\n  __HAL_SPI_DISABLE(hspi);\n\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\n  HAL_SPI_MspDeInit(hspi);\n\n  hspi->ErrorCode = HAL_SPI_ERROR_NONE;\n  hspi->State = HAL_SPI_STATE_RESET;\n\n  /* Release Lock */\n  __HAL_UNLOCK(hspi);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initialize the SPI MSP.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\n__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hspi);\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SPI_MspInit should be implemented in the user file\n  */\n}\n\n/**\n  * @brief  De-Initialize the SPI MSP.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\n__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hspi);\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SPI_MspDeInit should be implemented in the user file\n  */\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup SPI_Exported_Functions_Group2 IO operation functions\n *  @brief   Data transfers functions\n *\n@verbatim\n  ==============================================================================\n                      ##### IO operation functions #####\n ===============================================================================\n [..]\n    This subsection provides a set of functions allowing to manage the SPI\n    data transfers.\n\n    [..] The SPI supports master and slave mode :\n\n    (#) There are two modes of transfer:\n       (++) Blocking mode: The communication is performed in polling mode.\n            The HAL status of all data processing is returned by the same function\n            after finishing transfer.\n       (++) No-Blocking mode: The communication is performed using Interrupts\n            or DMA, These APIs return the HAL status.\n            The end of the data processing will be indicated through the\n            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when\n            using DMA mode.\n            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks\n            will be executed respectively at the end of the transmit or Receive process\n            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected\n\n    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)\n        exist for 1Line (simplex) and 2Lines (full duplex) modes.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Transmit an amount of data in blocking mode.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @param  pData: pointer to data buffer\n  * @param  Size: amount of data to be sent\n  * @param  Timeout: Timeout duration\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)\n{\n  uint32_t tickstart = 0U;\n  HAL_StatusTypeDef errorcode = HAL_OK;\n\n  /* Check Direction parameter */\n  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\n\n  /* Process Locked */\n  __HAL_LOCK(hspi);\n\n  /* Init tickstart for timeout management*/\n  tickstart = HAL_GetTick();\n\n  if(hspi->State != HAL_SPI_STATE_READY)\n  {\n    errorcode = HAL_BUSY;\n    goto error;\n  }\n\n  if((pData == NULL ) || (Size == 0))\n  {\n    errorcode = HAL_ERROR;\n    goto error;\n  }\n\n  /* Set the transaction information */\n  hspi->State       = HAL_SPI_STATE_BUSY_TX;\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\n  hspi->pTxBuffPtr  = (uint8_t *)pData;\n  hspi->TxXferSize  = Size;\n  hspi->TxXferCount = Size;\n\n  /*Init field not used in handle to zero */\n  hspi->pRxBuffPtr  = (uint8_t *)NULL;\n  hspi->RxXferSize  = 0U;\n  hspi->RxXferCount = 0U;\n  hspi->TxISR       = NULL;\n  hspi->RxISR       = NULL;\n\n  /* Configure communication direction : 1Line */\n  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\n  {\n    SPI_1LINE_TX(hspi);\n  }\n\n#if (USE_SPI_CRC != 0U)\n  /* Reset CRC Calculation */\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    SPI_RESET_CRC(hspi);\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Check if the SPI is already enabled */\n  if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\n  {\n    /* Enable SPI peripheral */\n    __HAL_SPI_ENABLE(hspi);\n  }\n\n  /* Transmit data in 16 Bit mode */\n  if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)\n  {\n    if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))\n    {\n      hspi->Instance->DR = *((uint16_t *)pData);\n      pData += sizeof(uint16_t);\n      hspi->TxXferCount--;\n    }\n    /* Transmit data in 16 Bit mode */\n    while (hspi->TxXferCount > 0U)\n    {\n      /* Wait until TXE flag is set to send data */\n      if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))\n      {\n          hspi->Instance->DR = *((uint16_t *)pData);\n          pData += sizeof(uint16_t);\n          hspi->TxXferCount--;\n      }\n      else\n      {\n        /* Timeout management */\n        if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))\n        {\n          errorcode = HAL_TIMEOUT;\n          goto error;\n        }\n      }\n    }\n  }\n  /* Transmit data in 8 Bit mode */\n  else\n  {\n    if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01))\n    {\n      *((__IO uint8_t*)&hspi->Instance->DR) = (*pData);\n      pData += sizeof(uint8_t);\n      hspi->TxXferCount--;\n    }\n    while (hspi->TxXferCount > 0U)\n    {\n      /* Wait until TXE flag is set to send data */\n      if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))\n      {\n        *((__IO uint8_t*)&hspi->Instance->DR) = (*pData);\n        pData += sizeof(uint8_t);\n        hspi->TxXferCount--;\n      }\n      else\n      {\n        /* Timeout management */\n        if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))\n        {\n          errorcode = HAL_TIMEOUT;\n          goto error;\n        }\n      }\n    }\n  }\n\n  /* Wait until TXE flag */\n  if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK)\n  {\n    errorcode = HAL_TIMEOUT;\n    goto error;\n  }\n\n  /* Check Busy flag */\n  if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)\n  {\n    errorcode = HAL_ERROR;\n    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\n    goto error;\n  }\n\n  /* Clear overrun flag in 2 Lines communication mode because received is not read */\n  if(hspi->Init.Direction == SPI_DIRECTION_2LINES)\n  {\n    __HAL_SPI_CLEAR_OVRFLAG(hspi);\n  }\n#if (USE_SPI_CRC != 0U)\n  /* Enable CRC Transmission */\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\n  }\n#endif /* USE_SPI_CRC */\n\n  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\n  {\n    errorcode = HAL_ERROR;\n  }\n\nerror:\n  hspi->State = HAL_SPI_STATE_READY;\n  /* Process Unlocked */\n  __HAL_UNLOCK(hspi);\n  return errorcode;\n}\n\n/**\n  * @brief  Receive an amount of data in blocking mode.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @param  pData: pointer to data buffer\n  * @param  Size: amount of data to be received\n  * @param  Timeout: Timeout duration\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)\n{\n#if (USE_SPI_CRC != 0U)\n  __IO uint16_t tmpreg = 0U;\n#endif /* USE_SPI_CRC */\n  uint32_t tickstart = 0U;\n  HAL_StatusTypeDef errorcode = HAL_OK;\n\n  if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))\n  {\n     hspi->State = HAL_SPI_STATE_BUSY_RX;\n     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */\n    return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);\n  }\n\n  /* Process Locked */\n  __HAL_LOCK(hspi);\n\n  /* Init tickstart for timeout management*/\n  tickstart = HAL_GetTick();\n\n  if(hspi->State != HAL_SPI_STATE_READY)\n  {\n    errorcode = HAL_BUSY;\n    goto error;\n  }\n\n  if((pData == NULL ) || (Size == 0))\n  {\n    errorcode = HAL_ERROR;\n    goto error;\n  }\n\n  /* Set the transaction information */\n  hspi->State       = HAL_SPI_STATE_BUSY_RX;\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\n  hspi->pRxBuffPtr  = (uint8_t *)pData;\n  hspi->RxXferSize  = Size;\n  hspi->RxXferCount = Size;\n\n  /*Init field not used in handle to zero */\n  hspi->pTxBuffPtr  = (uint8_t *)NULL;\n  hspi->TxXferSize  = 0U;\n  hspi->TxXferCount = 0U;\n  hspi->RxISR       = NULL;\n  hspi->TxISR       = NULL;\n\n#if (USE_SPI_CRC != 0U)\n  /* Reset CRC Calculation */\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    SPI_RESET_CRC(hspi);\n    /* this is done to handle the CRCNEXT before the latest data */\n    hspi->RxXferCount--;\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Configure communication direction: 1Line */\n  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\n  {\n    SPI_1LINE_RX(hspi);\n  }\n\n  /* Check if the SPI is already enabled */\n  if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\n  {\n    /* Enable SPI peripheral */\n    __HAL_SPI_ENABLE(hspi);\n  }\n\n    /* Receive data in 8 Bit mode */\n  if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)\n  {\n    /* Transfer loop */\n    while(hspi->RxXferCount > 0U)\n    {\n      /* Check the RXNE flag */\n      if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))\n      {\n        /* read the received data */\n        (* (uint8_t *)pData)= *(__IO uint8_t *)&hspi->Instance->DR;\n        pData += sizeof(uint8_t);\n        hspi->RxXferCount--;\n      }\n      else\n      {\n        /* Timeout management */\n        if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))\n        {\n          errorcode = HAL_TIMEOUT;\n          goto error;\n        }\n      }\n    }\n  }\n  else\n  {\n    /* Transfer loop */\n    while(hspi->RxXferCount > 0U)\n    {\n      /* Check the RXNE flag */\n      if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))\n      {\n        *((uint16_t*)pData) = hspi->Instance->DR;\n        pData += sizeof(uint16_t);\n        hspi->RxXferCount--;\n      }\n      else\n      {\n        /* Timeout management */\n        if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))\n        {\n          errorcode = HAL_TIMEOUT;\n          goto error;\n        }\n      }\n    }\n  }\n\n#if (USE_SPI_CRC != 0U)\n  /* Handle the CRC Transmission */\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    /* freeze the CRC before the latest data */\n    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\n\n    /* Read the latest data */\n    if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\n    {\n      /* the latest data has not been received */\n      errorcode = HAL_TIMEOUT;\n      goto error;\n    }\n\n    /* Receive last data in 16 Bit mode */\n    if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)\n    {\n      *((uint16_t*)pData) = hspi->Instance->DR;\n    }\n    /* Receive last data in 8 Bit mode */\n    else\n    {\n      (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;\n    }\n\n    /* Wait the CRC data */\n    if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\n      errorcode = HAL_TIMEOUT;\n      goto error;\n    }\n\n    /* Read CRC to Flush DR and RXNE flag */\n    tmpreg = hspi->Instance->DR;\n    /* To avoid GCC warning */\n    UNUSED(tmpreg);\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Check the end of the transaction */\n  if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\n  {\n    /* Disable SPI peripheral */\n    __HAL_SPI_DISABLE(hspi);\n  }\n\n#if (USE_SPI_CRC != 0U)\n  /* Check if CRC error occurred */\n  if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\n  {\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\n    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\n  }\n#endif /* USE_SPI_CRC */\n\n  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\n  {\n    errorcode = HAL_ERROR;\n  }\n\nerror :\n  hspi->State = HAL_SPI_STATE_READY;\n  __HAL_UNLOCK(hspi);\n  return errorcode;\n}\n\n/**\n  * @brief  Transmit and Receive an amount of data in blocking mode.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @param  pTxData: pointer to transmission data buffer\n  * @param  pRxData: pointer to reception data buffer\n  * @param  Size: amount of data to be sent and received\n  * @param  Timeout: Timeout duration\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)\n{\n  uint32_t tmp = 0U, tmp1 = 0U;\n#if (USE_SPI_CRC != 0U)\n  __IO uint16_t tmpreg1 = 0U;\n#endif /* USE_SPI_CRC */\n  uint32_t tickstart = 0U;\n  /* Variable used to alternate Rx and Tx during transfer */\n  uint32_t txallowed = 1U;\n  HAL_StatusTypeDef errorcode = HAL_OK;\n\n  /* Check Direction parameter */\n  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\n\n  /* Process Locked */\n  __HAL_LOCK(hspi);\n\n  /* Init tickstart for timeout management*/\n  tickstart = HAL_GetTick();\n\n  tmp  = hspi->State;\n  tmp1 = hspi->Init.Mode;\n\n  if(!((tmp == HAL_SPI_STATE_READY) || \\\n    ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))\n  {\n    errorcode = HAL_BUSY;\n    goto error;\n  }\n\n  if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))\n  {\n    errorcode = HAL_ERROR;\n    goto error;\n  }\n\n  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */\n  if(hspi->State == HAL_SPI_STATE_READY)\n  {\n    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\n  }\n\n  /* Set the transaction information */\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\n  hspi->pRxBuffPtr  = (uint8_t *)pRxData;\n  hspi->RxXferCount = Size;\n  hspi->RxXferSize  = Size;\n  hspi->pTxBuffPtr  = (uint8_t *)pTxData;\n  hspi->TxXferCount = Size;\n  hspi->TxXferSize  = Size;\n\n  /*Init field not used in handle to zero */\n  hspi->RxISR       = NULL;\n  hspi->TxISR       = NULL;\n\n#if (USE_SPI_CRC != 0U)\n  /* Reset CRC Calculation */\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    SPI_RESET_CRC(hspi);\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Check if the SPI is already enabled */\n  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)\n  {\n    /* Enable SPI peripheral */\n    __HAL_SPI_ENABLE(hspi);\n  }\n\n  /* Transmit and Receive data in 16 Bit mode */\n  if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)\n  {\n    if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))\n    {\n      hspi->Instance->DR = *((uint16_t *)pTxData);\n      pTxData += sizeof(uint16_t);\n      hspi->TxXferCount--;\n    }\n    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))\n    {\n      /* Check TXE flag */\n      if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))\n      {\n        hspi->Instance->DR = *((uint16_t *)pTxData);\n        pTxData += sizeof(uint16_t);\n        hspi->TxXferCount--;\n        /* Next Data is a reception (Rx). Tx not allowed */\n        txallowed = 0U;\n\n#if (USE_SPI_CRC != 0U)\n        /* Enable CRC Transmission */\n        if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\n        {\n          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\n        }\n#endif /* USE_SPI_CRC */\n      }\n\n      /* Check RXNE flag */\n      if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))\n      {\n        *((uint16_t *)pRxData) = hspi->Instance->DR;\n        pRxData += sizeof(uint16_t);\n        hspi->RxXferCount--;\n        /* Next Data is a Transmission (Tx). Tx is allowed */\n        txallowed = 1U;\n      }\n      if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout))\n      {\n        errorcode = HAL_TIMEOUT;\n        goto error;\n      }\n    }\n  }\n  /* Transmit and Receive data in 8 Bit mode */\n  else\n  {\n    if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))\n    {\n      *((__IO uint8_t*)&hspi->Instance->DR) = (*pTxData);\n      pTxData += sizeof(uint8_t);\n      hspi->TxXferCount--;\n    }\n    while((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))\n    {\n      /* check TXE flag */\n      if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))\n      {\n        *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);\n        hspi->TxXferCount--;\n        /* Next Data is a reception (Rx). Tx not allowed */\n        txallowed = 0U;\n\n#if (USE_SPI_CRC != 0U)\n        /* Enable CRC Transmission */\n        if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\n        {\n          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\n        }\n#endif /* USE_SPI_CRC */\n      }\n\n      /* Wait until RXNE flag is reset */\n      if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))\n      {\n        (*(uint8_t *)pRxData++) = hspi->Instance->DR;\n        hspi->RxXferCount--;\n        /* Next Data is a Transmission (Tx). Tx is allowed */\n        txallowed = 1U;\n      }\n      if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout))\n      {\n        errorcode = HAL_TIMEOUT;\n        goto error;\n      }\n    }\n  }\n\n#if (USE_SPI_CRC != 0U)\n  /* Read CRC from DR to close CRC calculation process */\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    /* Wait until TXE flag */\n    if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\n    {\n      /* Error on the CRC reception */\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\n      errorcode = HAL_TIMEOUT;\n      goto error;\n    }\n    /* Read CRC */\n    tmpreg1 = hspi->Instance->DR;\n    /* To avoid GCC warning */\n    UNUSED(tmpreg1);\n  }\n\n  /* Check if CRC error occurred */\n  if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\n  {\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\n    /* Clear CRC Flag */\n    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\n\n    errorcode = HAL_ERROR;\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Wait until TXE flag */\n  if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK)\n  {\n    errorcode = HAL_TIMEOUT;\n    goto error;\n  }\n\n  /* Check Busy flag */\n  if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)\n  {\n    errorcode = HAL_ERROR;\n    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\n    goto error;\n  }\n\n  /* Clear overrun flag in 2 Lines communication mode because received is not read */\n  if(hspi->Init.Direction == SPI_DIRECTION_2LINES)\n  {\n    __HAL_SPI_CLEAR_OVRFLAG(hspi);\n  }\n\nerror :\n  hspi->State = HAL_SPI_STATE_READY;\n  __HAL_UNLOCK(hspi);\n  return errorcode;\n}\n\n/**\n  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @param  pData: pointer to data buffer\n  * @param  Size: amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\n{\n  HAL_StatusTypeDef errorcode = HAL_OK;\n\n  /* Check Direction parameter */\n  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\n\n  /* Process Locked */\n  __HAL_LOCK(hspi);\n\n  if((pData == NULL) || (Size == 0))\n  {\n    errorcode = HAL_ERROR;\n    goto error;\n  }\n\n  if(hspi->State != HAL_SPI_STATE_READY)\n  {\n    errorcode = HAL_BUSY;\n    goto error;\n  }\n\n  /* Set the transaction information */\n  hspi->State       = HAL_SPI_STATE_BUSY_TX;\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\n  hspi->pTxBuffPtr  = (uint8_t *)pData;\n  hspi->TxXferSize  = Size;\n  hspi->TxXferCount = Size;\n\n  /* Init field not used in handle to zero */\n  hspi->pRxBuffPtr  = (uint8_t *)NULL;\n  hspi->RxXferSize  = 0U;\n  hspi->RxXferCount = 0U;\n  hspi->RxISR       = NULL;\n\n  /* Set the function for IT treatment */\n  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )\n  {\n    hspi->TxISR = SPI_TxISR_16BIT;\n  }\n  else\n  {\n    hspi->TxISR = SPI_TxISR_8BIT;\n  }\n\n  /* Configure communication direction : 1Line */\n  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\n  {\n    SPI_1LINE_TX(hspi);\n  }\n\n#if (USE_SPI_CRC != 0U)\n  /* Reset CRC Calculation */\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    SPI_RESET_CRC(hspi);\n  }\n#endif /* USE_SPI_CRC */\n\n  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)\n  {\n    /* Enable TXE interrupt */\n    __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));\n  }\n  else\n  {\n    /* Enable TXE and ERR interrupt */\n    __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));\n  }\n\n  /* Check if the SPI is already enabled */\n  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)\n  {\n    /* Enable SPI peripheral */\n    __HAL_SPI_ENABLE(hspi);\n  }\n\nerror :\n  __HAL_UNLOCK(hspi);\n  return errorcode;\n}\n\n/**\n  * @brief  Receive an amount of data in non-blocking mode with Interrupt.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @param  pData: pointer to data buffer\n  * @param  Size: amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\n{\n  HAL_StatusTypeDef errorcode = HAL_OK;\n\n  if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))\n  {\n     hspi->State = HAL_SPI_STATE_BUSY_RX;\n     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */\n     return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);\n  }\n\n  /* Process Locked */\n  __HAL_LOCK(hspi);\n\n  if(hspi->State != HAL_SPI_STATE_READY)\n  {\n    errorcode = HAL_BUSY;\n    goto error;\n  }\n\n  if((pData == NULL) || (Size == 0))\n  {\n    errorcode = HAL_ERROR;\n    goto error;\n  }\n\n  /* Set the transaction information */\n  hspi->State       = HAL_SPI_STATE_BUSY_RX;\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\n  hspi->pRxBuffPtr  = (uint8_t *)pData;\n  hspi->RxXferSize  = Size;\n  hspi->RxXferCount = Size;\n\n  /* Init field not used in handle to zero */\n  hspi->pTxBuffPtr  = (uint8_t *)NULL;\n  hspi->TxXferSize  = 0U;\n  hspi->TxXferCount = 0U;\n  hspi->TxISR       = NULL;\n\n  /* Set the function for IT treatment */\n  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )\n  {\n    hspi->RxISR = SPI_RxISR_16BIT;\n  }\n  else\n  {\n    hspi->RxISR = SPI_RxISR_8BIT;\n  }\n\n  /* Configure communication direction : 1Line */\n  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\n  {\n    SPI_1LINE_RX(hspi);\n  }\n\n#if (USE_SPI_CRC != 0U)\n  /* Reset CRC Calculation */\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    SPI_RESET_CRC(hspi);\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Enable TXE and ERR interrupt */\n  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\n\n  /* Note : The SPI must be enabled after unlocking current process\n            to avoid the risk of SPI interrupt handle execution before current\n            process unlock */\n\n  /* Check if the SPI is already enabled */\n  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)\n  {\n    /* Enable SPI peripheral */\n    __HAL_SPI_ENABLE(hspi);\n  }\n\nerror :\n  /* Process Unlocked */\n  __HAL_UNLOCK(hspi);\n  return errorcode;\n}\n\n/**\n  * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @param  pTxData: pointer to transmission data buffer\n  * @param  pRxData: pointer to reception data buffer\n  * @param  Size: amount of data to be sent and received\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\n{\n  uint32_t tmp = 0U, tmp1 = 0U;\n  HAL_StatusTypeDef errorcode = HAL_OK;\n\n  /* Check Direction parameter */\n  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\n\n  /* Process locked */\n  __HAL_LOCK(hspi);\n\n  tmp  = hspi->State;\n  tmp1 = hspi->Init.Mode;\n\n  if(!((tmp == HAL_SPI_STATE_READY) || \\\n    ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))\n  {\n    errorcode = HAL_BUSY;\n    goto error;\n  }\n\n  if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))\n  {\n    errorcode = HAL_ERROR;\n    goto error;\n  }\n\n  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */\n  if(hspi->State == HAL_SPI_STATE_READY)\n  {\n    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\n  }\n\n  /* Set the transaction information */\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\n  hspi->pTxBuffPtr  = (uint8_t *)pTxData;\n  hspi->TxXferSize  = Size;\n  hspi->TxXferCount = Size;\n  hspi->pRxBuffPtr  = (uint8_t *)pRxData;\n  hspi->RxXferSize  = Size;\n  hspi->RxXferCount = Size;\n\n  /* Set the function for IT treatment */\n  if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )\n  {\n    hspi->RxISR     = SPI_2linesRxISR_16BIT;\n    hspi->TxISR     = SPI_2linesTxISR_16BIT;\n  }\n  else\n  {\n    hspi->RxISR     = SPI_2linesRxISR_8BIT;\n    hspi->TxISR     = SPI_2linesTxISR_8BIT;\n  }\n\n#if (USE_SPI_CRC != 0U)\n  /* Reset CRC Calculation */\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    SPI_RESET_CRC(hspi);\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Enable TXE, RXNE and ERR interrupt */\n  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\n\n  /* Check if the SPI is already enabled */\n  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)\n  {\n    /* Enable SPI peripheral */\n    __HAL_SPI_ENABLE(hspi);\n  }\n\nerror :\n  /* Process Unlocked */\n  __HAL_UNLOCK(hspi);\n  return errorcode;\n}\n\n#if 0 // XXX DMA\n/**\n  * @brief  Transmit an amount of data in non-blocking mode with DMA.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @param  pData: pointer to data buffer\n  * @param  Size: amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\n{\n  HAL_StatusTypeDef errorcode = HAL_OK;\n\n  /* Check Direction parameter */\n  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\n\n  /* Process Locked */\n  __HAL_LOCK(hspi);\n\n  if(hspi->State != HAL_SPI_STATE_READY)\n  {\n    errorcode = HAL_BUSY;\n    goto error;\n  }\n\n  if((pData == NULL) || (Size == 0))\n  {\n    errorcode = HAL_ERROR;\n    goto error;\n  }\n\n  /* Set the transaction information */\n  hspi->State       = HAL_SPI_STATE_BUSY_TX;\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\n  hspi->pTxBuffPtr  = (uint8_t *)pData;\n  hspi->TxXferSize  = Size;\n  hspi->TxXferCount = Size;\n\n  /* Init field not used in handle to zero */\n  hspi->pRxBuffPtr  = (uint8_t *)NULL;\n  hspi->TxISR       = NULL;\n  hspi->RxISR       = NULL;\n  hspi->RxXferSize  = 0U;\n  hspi->RxXferCount = 0U;\n\n  /* Configure communication direction : 1Line */\n  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\n  {\n    SPI_1LINE_TX(hspi);\n  }\n\n#if (USE_SPI_CRC != 0U)\n  /* Reset CRC Calculation */\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    SPI_RESET_CRC(hspi);\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Set the SPI TxDMA Half transfer complete callback */\n  hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;\n\n  /* Set the SPI TxDMA transfer complete callback */\n  hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;\n\n  /* Set the DMA error callback */\n  hspi->hdmatx->XferErrorCallback = SPI_DMAError;\n\n  /* Set the DMA AbortCpltCallback */\n  hspi->hdmatx->XferAbortCallback = NULL;\n\n  /* Enable the Tx DMA Stream */\n  HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);\n\n  /* Check if the SPI is already enabled */\n  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)\n  {\n    /* Enable SPI peripheral */\n    __HAL_SPI_ENABLE(hspi);\n  }\n\n  /* Enable the SPI Error Interrupt Bit */\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);\n\n  /* Enable Tx DMA Request */\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\n\nerror :\n  /* Process Unlocked */\n  __HAL_UNLOCK(hspi);\n  return errorcode;\n}\n\n/**\n  * @brief  Receive an amount of data in non-blocking mode with DMA.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @param  pData: pointer to data buffer\n  * @note   When the CRC feature is enabled the pData Length must be Size + 1.\n  * @param  Size: amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\n{\n  HAL_StatusTypeDef errorcode = HAL_OK;\n\n  if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))\n  {\n     hspi->State = HAL_SPI_STATE_BUSY_RX;\n     /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */\n     return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);\n  }\n\n  /* Process Locked */\n  __HAL_LOCK(hspi);\n\n  if(hspi->State != HAL_SPI_STATE_READY)\n  {\n    errorcode = HAL_BUSY;\n    goto error;\n  }\n\n  if((pData == NULL) || (Size == 0))\n  {\n    errorcode = HAL_ERROR;\n    goto error;\n  }\n\n  /* Set the transaction information */\n  hspi->State       = HAL_SPI_STATE_BUSY_RX;\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\n  hspi->pRxBuffPtr  = (uint8_t *)pData;\n  hspi->RxXferSize  = Size;\n  hspi->RxXferCount = Size;\n\n  /*Init field not used in handle to zero */\n  hspi->RxISR       = NULL;\n  hspi->TxISR       = NULL;\n  hspi->TxXferSize  = 0U;\n  hspi->TxXferCount = 0U;\n\n  /* Configure communication direction : 1Line */\n  if(hspi->Init.Direction == SPI_DIRECTION_1LINE)\n  {\n    SPI_1LINE_RX(hspi);\n  }\n\n#if (USE_SPI_CRC != 0U)\n  /* Reset CRC Calculation */\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    SPI_RESET_CRC(hspi);\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Set the SPI RxDMA Half transfer complete callback */\n  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;\n\n  /* Set the SPI Rx DMA transfer complete callback */\n  hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;\n\n  /* Set the DMA error callback */\n  hspi->hdmarx->XferErrorCallback = SPI_DMAError;\n\n /* Set the DMA AbortCpltCallback */\n  hspi->hdmarx->XferAbortCallback = NULL;\n\n  /* Enable the Rx DMA Stream */\n  HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);\n\n  /* Check if the SPI is already enabled */\n  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)\n  {\n    /* Enable SPI peripheral */\n    __HAL_SPI_ENABLE(hspi);\n  }\n\n  /* Enable the SPI Error Interrupt Bit */\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);\n\n  /* Enable Rx DMA Request */\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\n\nerror:\n  /* Process Unlocked */\n  __HAL_UNLOCK(hspi);\n  return errorcode;\n}\n\n/**\n  * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @param  pTxData: pointer to transmission data buffer\n  * @param  pRxData: pointer to reception data buffer\n  * @note   When the CRC feature is enabled the pRxData Length must be Size + 1\n  * @param  Size: amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\n{\n  uint32_t tmp = 0U, tmp1 = 0U;\n  HAL_StatusTypeDef errorcode = HAL_OK;\n\n  /* Check Direction parameter */\n  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\n\n  /* Process locked */\n  __HAL_LOCK(hspi);\n\n  tmp  = hspi->State;\n  tmp1 = hspi->Init.Mode;\n  if(!((tmp == HAL_SPI_STATE_READY) ||\n      ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))\n  {\n    errorcode = HAL_BUSY;\n    goto error;\n  }\n\n  if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))\n  {\n    errorcode = HAL_ERROR;\n    goto error;\n  }\n\n  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */\n  if(hspi->State == HAL_SPI_STATE_READY)\n  {\n    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\n  }\n\n  /* Set the transaction information */\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\n  hspi->pTxBuffPtr  = (uint8_t*)pTxData;\n  hspi->TxXferSize  = Size;\n  hspi->TxXferCount = Size;\n  hspi->pRxBuffPtr  = (uint8_t*)pRxData;\n  hspi->RxXferSize  = Size;\n  hspi->RxXferCount = Size;\n\n  /* Init field not used in handle to zero */\n  hspi->RxISR       = NULL;\n  hspi->TxISR       = NULL;\n\n#if (USE_SPI_CRC != 0U)\n  /* Reset CRC Calculation */\n  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    SPI_RESET_CRC(hspi);\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */\n  if(hspi->State == HAL_SPI_STATE_BUSY_RX)\n  {\n    /* Set the SPI Rx DMA Half transfer complete callback */\n    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;\n    hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;\n  }\n  else\n  {\n    /* Set the SPI Tx/Rx DMA Half transfer complete callback */\n    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;\n    hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;\n  }\n\n  /* Set the DMA error callback */\n  hspi->hdmarx->XferErrorCallback = SPI_DMAError;\n\n  /* Set the DMA AbortCpltCallback */\n  hspi->hdmarx->XferAbortCallback = NULL;\n\n  /* Enable the Rx DMA Stream */\n  HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);\n\n  /* Enable Rx DMA Request */\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\n\n  /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing\n  is performed in DMA reception complete callback  */\n  hspi->hdmatx->XferHalfCpltCallback = NULL;\n  hspi->hdmatx->XferCpltCallback     = NULL;\n  hspi->hdmatx->XferErrorCallback    = NULL;\n  hspi->hdmatx->XferAbortCallback    = NULL;\n\n  /* Enable the Tx DMA Stream */\n  HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);\n\n  /* Check if the SPI is already enabled */\n  if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)\n  {\n    /* Enable SPI peripheral */\n    __HAL_SPI_ENABLE(hspi);\n  }\n  /* Enable the SPI Error Interrupt Bit */\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);\n\n  /* Enable Tx DMA Request */\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\n\nerror :\n  /* Process Unlocked */\n  __HAL_UNLOCK(hspi);\n  return errorcode;\n}\n#endif // XXX DMA\n\n/**\n  * @brief  Abort ongoing transfer (blocking mode).\n  * @param  hspi SPI handle.\n  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),\n  *         started in Interrupt or DMA mode.\n  *         This procedure performs following operations :\n  *           - Disable SPI Interrupts (depending of transfer direction)\n  *           - Disable the DMA transfer in the peripheral register (if enabled)\n  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\n  *           - Set handle State to READY\n  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\n  * @note   Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application\n  *         before starting new SPI receive process.\n  * @retval HAL status\n*/\nHAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)\n{\n#if 0 // XXX DMA\n  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\n#endif // XXX DMA\n\n  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */\n  if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))\n  {\n    hspi->TxISR = SPI_AbortTx_ISR;\n  }\n\n  if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))\n  {\n    hspi->RxISR = SPI_AbortRx_ISR;\n  }\n\n  /* Clear ERRIE interrupts in case of DMA Mode */\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);\n\n  /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */\n  if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))\n  {\n#if 0 // XXX DMA\n    /* Abort the SPI DMA Tx channel : use blocking DMA Abort API (no callback) */\n    if(hspi->hdmatx != NULL)\n    {\n      /* Set the SPI DMA Abort callback :\n      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */\n      hspi->hdmatx->XferAbortCallback = NULL;\n\n      /* Abort DMA Tx Handle linked to SPI Peripheral */\n      HAL_DMA_Abort(hspi->hdmatx);\n\n      /* Disable Tx DMA Request */\n      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));\n\n      /* Wait until TXE flag is set */\n      do\n      {\n        if(count-- == 0U)\n        {\n          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n          break;\n        }\n      }\n      while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);\n    }\n    /* Abort the SPI DMA Rx channel : use blocking DMA Abort API (no callback) */\n    if(hspi->hdmarx != NULL)\n    {\n      /* Set the SPI DMA Abort callback :\n      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */\n      hspi->hdmarx->XferAbortCallback = NULL;\n\n      /* Abort DMA Rx Handle linked to SPI Peripheral */\n      HAL_DMA_Abort(hspi->hdmarx);\n\n      /* Disable peripheral */\n      __HAL_SPI_DISABLE(hspi);\n\n      /* Disable Rx DMA Request */\n      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));\n\n    }\n#endif // XXX DMA\n  }\n  /* Reset Tx and Rx transfer counters */\n  hspi->RxXferCount = 0U;\n  hspi->TxXferCount = 0U;\n\n  /* Reset errorCode */\n  hspi->ErrorCode = HAL_SPI_ERROR_NONE;\n\n  /* Clear the Error flags in the SR register */\n  __HAL_SPI_CLEAR_OVRFLAG(hspi);\n  __HAL_SPI_CLEAR_FREFLAG(hspi);\n\n  /* Restore hspi->state to ready */\n  hspi->State = HAL_SPI_STATE_READY;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Abort ongoing transfer (Interrupt mode).\n  * @param  hspi SPI handle.\n  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),\n  *         started in Interrupt or DMA mode.\n  *         This procedure performs following operations :\n  *           - Disable SPI Interrupts (depending of transfer direction)\n  *           - Disable the DMA transfer in the peripheral register (if enabled)\n  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\n  *           - Set handle State to READY\n  *           - At abort completion, call user abort complete callback\n  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be\n  *         considered as completed only when user abort complete callback is executed (not when exiting function).\n  * @note   Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application\n  *         before starting new SPI receive process.\n  * @retval HAL status\n*/\nHAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)\n{\n  uint32_t abortcplt;\n\n  /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */\n  if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))\n  {\n    hspi->TxISR = SPI_AbortTx_ISR;\n  }\n\n  if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))\n  {\n    hspi->RxISR = SPI_AbortRx_ISR;\n  }\n\n  /* Clear ERRIE interrupts in case of DMA Mode */\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);\n\n  abortcplt = 1U;\n\n#if 0 // XXX DMA\n  /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized\n     before any call to DMA Abort functions */\n  /* DMA Tx Handle is valid */\n  if(hspi->hdmatx != NULL)\n  {\n    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.\n       Otherwise, set it to NULL */\n    if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))\n    {\n      hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;\n    }\n    else\n    {\n      hspi->hdmatx->XferAbortCallback = NULL;\n    }\n  }\n  /* DMA Rx Handle is valid */\n  if(hspi->hdmarx != NULL)\n  {\n    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.\n       Otherwise, set it to NULL */\n    if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))\n    {\n      hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;\n    }\n    else\n    {\n      hspi->hdmarx->XferAbortCallback = NULL;\n    }\n  }\n\n  /* Disable the SPI DMA Tx or the SPI Rx request if enabled */\n  if((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))\n  {\n    /* Abort the SPI DMA Tx channel */\n    if(hspi->hdmatx != NULL)\n    {\n      /* Abort DMA Tx Handle linked to SPI Peripheral */\n      if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)\n      {\n        hspi->hdmatx->XferAbortCallback = NULL;\n      }\n      else\n      {\n        abortcplt = 0U;\n      }\n    }\n    /* Abort the SPI DMA Rx channel */\n    if(hspi->hdmarx != NULL)\n    {\n      /* Abort DMA Rx Handle linked to SPI Peripheral */\n      if(HAL_DMA_Abort_IT(hspi->hdmarx)!=  HAL_OK)\n      {\n        hspi->hdmarx->XferAbortCallback = NULL;\n        abortcplt = 1U;\n      }\n      else\n      {\n        abortcplt = 0U;\n      }\n    }\n  }\n\n  /* Disable the SPI DMA Tx or the SPI Rx request if enabled */\n  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))\n  {\n    /* Abort the SPI DMA Tx channel */\n    if(hspi->hdmatx != NULL)\n    {\n      /* Abort DMA Tx Handle linked to SPI Peripheral */\n      if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)\n      {\n        hspi->hdmatx->XferAbortCallback = NULL;\n      }\n      else\n      {\n        abortcplt = 0U;\n      }\n    }\n  }\n  /* Disable the SPI DMA Tx or the SPI Rx request if enabled */\n  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))\n  {\n    /* Abort the SPI DMA Rx channel */\n    if(hspi->hdmarx != NULL)\n    {\n      /* Abort DMA Rx Handle linked to SPI Peripheral */\n      if(HAL_DMA_Abort_IT(hspi->hdmarx)!=  HAL_OK)\n      {\n        hspi->hdmarx->XferAbortCallback = NULL;\n      }\n      else\n      {\n        abortcplt = 0U;\n      }\n    }\n  }\n#endif // XXX DMA\n\n  if(abortcplt == 1U)\n  {\n    /* Reset Tx and Rx transfer counters */\n    hspi->RxXferCount = 0U;\n    hspi->TxXferCount = 0U;\n\n    /* Reset errorCode */\n    hspi->ErrorCode = HAL_SPI_ERROR_NONE;\n\n    /* Clear the Error flags in the SR register */\n    __HAL_SPI_CLEAR_OVRFLAG(hspi);\n    __HAL_SPI_CLEAR_FREFLAG(hspi);\n\n    /* Restore hspi->State to Ready */\n    hspi->State = HAL_SPI_STATE_READY;\n\n    /* As no DMA to be aborted, call directly user Abort complete callback */\n    HAL_SPI_AbortCpltCallback(hspi);\n  }\n  return HAL_OK;\n}\n\n#if 0 // XXX DMA\n/**\n  * @brief  Pause the DMA Transfer.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for the specified SPI module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)\n{\n  /* Process Locked */\n  __HAL_LOCK(hspi);\n\n  /* Disable the SPI DMA Tx & Rx requests */\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\n\n  /* Process Unlocked */\n  __HAL_UNLOCK(hspi);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Resume the DMA Transfer.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for the specified SPI module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)\n{\n  /* Process Locked */\n  __HAL_LOCK(hspi);\n\n  /* Enable the SPI DMA Tx & Rx requests */\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\n\n  /* Process Unlocked */\n  __HAL_UNLOCK(hspi);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief Stop the DMA Transfer.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for the specified SPI module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)\n{\n  /* The Lock is not implemented on this API to allow the user application\n     to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():\n     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated\n     and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()\n     */\n\n  /* Abort the SPI DMA tx Stream */\n  if(hspi->hdmatx != NULL)\n  {\n    HAL_DMA_Abort(hspi->hdmatx);\n  }\n  /* Abort the SPI DMA rx Stream */\n  if(hspi->hdmarx != NULL)\n  {\n    HAL_DMA_Abort(hspi->hdmarx);\n  }\n\n  /* Disable the SPI DMA Tx & Rx requests */\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\n  hspi->State = HAL_SPI_STATE_READY;\n  return HAL_OK;\n}\n#endif // XXX DMA\n\n/**\n  * @brief  Handle SPI interrupt request.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for the specified SPI module.\n  * @retval None\n  */\nvoid HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)\n{\n  uint32_t itsource = hspi->Instance->CR2;\n  uint32_t itflag   = hspi->Instance->SR;\n\n  /* SPI in mode Receiver ----------------------------------------------------*/\n  if(((itflag & SPI_FLAG_OVR) == RESET) &&\n     ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))\n  {\n    hspi->RxISR(hspi);\n    return;\n  }\n\n  /* SPI in mode Transmitter -------------------------------------------------*/\n  if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))\n  {\n    hspi->TxISR(hspi);\n    return;\n  }\n\n  /* SPI in Error Treatment --------------------------------------------------*/\n  if(((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))\n  {\n    /* SPI Overrun error interrupt occurred ----------------------------------*/\n    if((itflag & SPI_FLAG_OVR) != RESET)\n    {\n      if(hspi->State != HAL_SPI_STATE_BUSY_TX)\n      {\n        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);\n        __HAL_SPI_CLEAR_OVRFLAG(hspi);\n      }\n      else\n      {\n        __HAL_SPI_CLEAR_OVRFLAG(hspi);\n        return;\n      }\n    }\n\n    /* SPI Mode Fault error interrupt occurred -------------------------------*/\n    if((itflag & SPI_FLAG_MODF) != RESET)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);\n      __HAL_SPI_CLEAR_MODFFLAG(hspi);\n    }\n\n    /* SPI Frame error interrupt occurred ------------------------------------*/\n    if((itflag & SPI_FLAG_FRE) != RESET)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);\n      __HAL_SPI_CLEAR_FREFLAG(hspi);\n    }\n\n    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\n    {\n      /* Disable all interrupts */\n      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);\n\n      hspi->State = HAL_SPI_STATE_READY;\n      /* Disable the SPI DMA requests if enabled */\n      if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN))||(HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))\n      {\n#if 0 // XXX DMA\n        CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));\n\n        /* Abort the SPI DMA Rx channel */\n        if(hspi->hdmarx != NULL)\n        {\n          /* Set the SPI DMA Abort callback :\n          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */\n          hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;\n          HAL_DMA_Abort_IT(hspi->hdmarx);\n        }\n        /* Abort the SPI DMA Tx channel */\n        if(hspi->hdmatx != NULL)\n        {\n          /* Set the SPI DMA Abort callback :\n          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */\n          hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;\n          HAL_DMA_Abort_IT(hspi->hdmatx);\n        }\n#endif // XXX DMA\n      }\n      else\n      {\n        /* Call user error callback */\n        HAL_SPI_ErrorCallback(hspi);\n      }\n    }\n    return;\n  }\n}\n\n/**\n  * @brief Tx Transfer completed callback.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\n__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hspi);\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SPI_TxCpltCallback should be implemented in the user file\n  */\n}\n\n/**\n  * @brief Rx Transfer completed callback.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\n__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hspi);\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SPI_RxCpltCallback should be implemented in the user file\n  */\n}\n\n/**\n  * @brief Tx and Rx Transfer completed callback.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\n__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hspi);\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SPI_TxRxCpltCallback should be implemented in the user file\n  */\n}\n\n/**\n  * @brief Tx Half Transfer completed callback.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\n__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hspi);\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SPI_TxHalfCpltCallback should be implemented in the user file\n  */\n}\n\n/**\n  * @brief Rx Half Transfer completed callback.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\n__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hspi);\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file\n  */\n}\n\n/**\n  * @brief Tx and Rx Half Transfer callback.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\n__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hspi);\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file\n  */\n}\n\n/**\n  * @brief SPI error callback.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\n __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hspi);\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SPI_ErrorCallback should be implemented in the user file\n   */\n  /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes\n            and user can use HAL_SPI_GetError() API to check the latest error occurred\n  */\n}\n\n/**\n  * @brief  SPI Abort Complete callback.\n  * @param  hspi SPI handle.\n  * @retval None\n  */\n__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hspi);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SPI_AbortCpltCallback can be implemented in the user file.\n   */\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions\n  * @brief   SPI control functions\n  *\n@verbatim\n ===============================================================================\n                      ##### Peripheral State and Errors functions #####\n ===============================================================================\n    [..]\n    This subsection provides a set of functions allowing to control the SPI.\n     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral\n     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Return the SPI handle state.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval SPI state\n  */\nHAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)\n{\n  /* Return SPI handle state */\n  return hspi->State;\n}\n\n/**\n  * @brief  Return the SPI error code.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval SPI error code in bitmap format\n  */\nuint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)\n{\n  /* Return SPI ErrorCode */\n  return hspi->ErrorCode;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup SPI_Private_Functions\n  * @brief   Private functions\n  * @{\n  */\n\n#if 0 // XXX DMA\n/**\n  * @brief DMA SPI transmit process complete callback.\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)\n{\n  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\n  uint32_t tickstart = 0U;\n\n  /* Init tickstart for timeout managment*/\n  tickstart = HAL_GetTick();\n\n  /* DMA Normal Mode */\n  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\n  {\n    /* Disable Tx DMA Request */\n    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\n\n    /* Check the end of the transaction */\n    if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n    }\n\n    /* Clear overrun flag in 2 Lines communication mode because received data is not read */\n    if(hspi->Init.Direction == SPI_DIRECTION_2LINES)\n    {\n      __HAL_SPI_CLEAR_OVRFLAG(hspi);\n    }\n\n    hspi->TxXferCount = 0U;\n    hspi->State = HAL_SPI_STATE_READY;\n\n    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\n    {\n      HAL_SPI_ErrorCallback(hspi);\n      return;\n    }\n  }\n  HAL_SPI_TxCpltCallback(hspi);\n}\n\n/**\n  * @brief DMA SPI receive process complete callback.\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\n{\n  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\n#if (USE_SPI_CRC != 0U)\n  uint32_t tickstart = 0U;\n  __IO uint16_t tmpreg = 0U;\n\n  /* Init tickstart for timeout management*/\n  tickstart = HAL_GetTick();\n#endif /* USE_SPI_CRC */\n\n  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\n  {\n#if (USE_SPI_CRC != 0U)\n    /* CRC handling */\n    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n    {\n      /* Wait until RXNE flag */\n      if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\n      {\n        /* Error on the CRC reception */\n        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\n      }\n      /* Read CRC */\n      tmpreg = hspi->Instance->DR;\n      /* To avoid GCC warning */\n      UNUSED(tmpreg);\n    }\n#endif /* USE_SPI_CRC */\n\n    /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */\n    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\n\n    /* Check the end of the transaction */\n    if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\n    {\n      /* Disable SPI peripheral */\n      __HAL_SPI_DISABLE(hspi);\n    }\n\n    hspi->RxXferCount = 0U;\n    hspi->State = HAL_SPI_STATE_READY;\n\n#if (USE_SPI_CRC != 0U)\n    /* Check if CRC error occurred */\n    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\n      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\n    }\n#endif /* USE_SPI_CRC */\n\n    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\n    {\n      HAL_SPI_ErrorCallback(hspi);\n      return;\n    }\n  }\n  HAL_SPI_RxCpltCallback(hspi);\n}\n\n/**\n  * @brief  DMA SPI transmit receive process complete callback.\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)\n{\n  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\n  uint32_t tickstart = 0U;\n#if (USE_SPI_CRC != 0U)\n  __IO int16_t tmpreg = 0U;\n#endif /* USE_SPI_CRC */\n  /* Init tickstart for timeout management*/\n  tickstart = HAL_GetTick();\n\n  if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\n  {\n#if (USE_SPI_CRC != 0U)\n    /* CRC handling */\n    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n    {\n      /* Wait the CRC data */\n      if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\n      {\n        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\n      }\n      /* Read CRC to Flush DR and RXNE flag */\n      tmpreg = hspi->Instance->DR;\n      /* To avoid GCC warning */\n      UNUSED(tmpreg);\n    }\n#endif /* USE_SPI_CRC */\n    /* Check the end of the transaction */\n    if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n    }\n\n    /* Disable Rx/Tx DMA Request */\n    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\n\n    hspi->TxXferCount = 0U;\n    hspi->RxXferCount = 0U;\n    hspi->State = HAL_SPI_STATE_READY;\n\n#if (USE_SPI_CRC != 0U)\n    /* Check if CRC error occurred */\n    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\n      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\n    }\n#endif /* USE_SPI_CRC */\n\n    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\n    {\n      HAL_SPI_ErrorCallback(hspi);\n      return;\n    }\n  }\n  HAL_SPI_TxRxCpltCallback(hspi);\n}\n\n/**\n  * @brief  DMA SPI half transmit process complete callback.\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)\n{\n  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\n\n  HAL_SPI_TxHalfCpltCallback(hspi);\n}\n\n/**\n  * @brief  DMA SPI half receive process complete callback\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)\n{\n  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\n\n  HAL_SPI_RxHalfCpltCallback(hspi);\n}\n\n/**\n  * @brief  DMA SPI half transmit receive process complete callback.\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)\n{\n  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\n\n  HAL_SPI_TxRxHalfCpltCallback(hspi);\n}\n\n/**\n  * @brief  DMA SPI communication error callback.\n  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void SPI_DMAError(DMA_HandleTypeDef *hdma)\n{\n  SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\n\n/* Stop the disable DMA transfer on SPI side */\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\n\n  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\n  hspi->State = HAL_SPI_STATE_READY;\n  HAL_SPI_ErrorCallback(hspi);\n}\n\n/**\n  * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error\n  *         (To be called at end of DMA Abort procedure following error occurrence).\n  * @param  hdma DMA handle.\n  * @retval None\n  */\nstatic void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)\n{\n  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\n  hspi->RxXferCount = 0U;\n  hspi->TxXferCount = 0U;\n\n  HAL_SPI_ErrorCallback(hspi);\n}\n\n/**\n  * @brief  DMA SPI Tx communication abort callback, when initiated by user\n  *         (To be called at end of DMA Tx Abort procedure following user abort request).\n  * @note   When this callback is executed, User Abort complete call back is called only if no\n  *         Abort still ongoing for Rx DMA Handle.\n  * @param  hdma DMA handle.\n  * @retval None\n  */\nstatic void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)\n{\n  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\n  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\n\n  hspi->hdmatx->XferAbortCallback = NULL;\n\n  /* Disable Tx DMA Request */\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN );\n\n  /* Wait until TXE flag is set */\n  do\n  {\n    if(count-- == 0U)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n      break;\n    }\n  }\n  while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);\n\n  /* Check if an Abort process is still ongoing */\n  if(hspi->hdmarx != NULL)\n  {\n    if(hspi->hdmarx->XferAbortCallback != NULL)\n    {\n      return;\n    }\n  }\n\n  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */\n  hspi->RxXferCount = 0U;\n  hspi->TxXferCount = 0U;\n\n  /* Reset errorCode */\n  hspi->ErrorCode = HAL_SPI_ERROR_NONE;\n\n  /* Clear the Error flags in the SR register */\n  __HAL_SPI_CLEAR_FREFLAG(hspi);\n\n  /* Restore hspi->State to Ready */\n  hspi->State  = HAL_SPI_STATE_READY;\n\n  /* Call user Abort complete callback */\n  HAL_SPI_AbortCpltCallback(hspi);\n}\n\n/**\n  * @brief  DMA SPI Rx communication abort callback, when initiated by user\n  *         (To be called at end of DMA Rx Abort procedure following user abort request).\n  * @note   When this callback is executed, User Abort complete call back is called only if no\n  *         Abort still ongoing for Tx DMA Handle.\n  * @param  hdma DMA handle.\n  * @retval None\n  */\nstatic void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)\n{\n  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\n\n  /* Disable SPI Peripheral */\n  __HAL_SPI_DISABLE(hspi);\n\n  hspi->hdmarx->XferAbortCallback = NULL;\n\n  /* Disable Rx DMA Request */\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\n\n  /* Check if an Abort process is still ongoing */\n  if(hspi->hdmatx != NULL)\n  {\n    if(hspi->hdmatx->XferAbortCallback != NULL)\n    {\n      return;\n    }\n  }\n\n  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */\n  hspi->RxXferCount = 0U;\n  hspi->TxXferCount = 0U;\n\n  /* Reset errorCode */\n  hspi->ErrorCode = HAL_SPI_ERROR_NONE;\n\n  /* Clear the Error flags in the SR register */\n  __HAL_SPI_CLEAR_OVRFLAG(hspi);\n  __HAL_SPI_CLEAR_FREFLAG(hspi);\n\n  /* Restore hspi->State to Ready */\n  hspi->State  = HAL_SPI_STATE_READY;\n\n  /* Call user Abort complete callback */\n  HAL_SPI_AbortCpltCallback(hspi);\n}\n#endif // XXX DMA\n\n/**\n  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\n{\n  /* Receive data in 8bit mode */\n  *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);\n  hspi->RxXferCount--;\n\n  /* check end of the reception */\n  if(hspi->RxXferCount == 0U)\n  {\n#if (USE_SPI_CRC != 0U)\n    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n    {\n      hspi->RxISR =  SPI_2linesRxISR_8BITCRC;\n      return;\n    }\n#endif /* USE_SPI_CRC */\n\n    /* Disable RXNE interrupt */\n    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\n\n    if(hspi->TxXferCount == 0U)\n    {\n      SPI_CloseRxTx_ISR(hspi);\n    }\n  }\n}\n\n#if (USE_SPI_CRC != 0U)\n/**\n  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)\n{\n  __IO uint8_t tmpreg = 0U;\n\n  /* Read data register to flush CRC */\n  tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);\n\n  /* To avoid GCC warning */\n\n  UNUSED(tmpreg);\n\n   /* Disable RXNE interrupt */\n  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\n\n  if(hspi->TxXferCount == 0U)\n  {\n    SPI_CloseRxTx_ISR(hspi);\n  }\n}\n#endif /* USE_SPI_CRC */\n\n/**\n  * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\n{\n  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);\n  hspi->TxXferCount--;\n\n  /* check the end of the transmission */\n  if(hspi->TxXferCount == 0U)\n  {\n#if (USE_SPI_CRC != 0U)\n    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n    {\n      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\n      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\n      return;\n    }\n#endif /* USE_SPI_CRC */\n\n    /* Disable TXE interrupt */\n    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\n\n    if(hspi->RxXferCount == 0U)\n    {\n      SPI_CloseRxTx_ISR(hspi);\n    }\n  }\n}\n\n/**\n  * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\n{\n  /* Receive data in 16 Bit mode */\n  *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;\n  hspi->pRxBuffPtr += sizeof(uint16_t);\n  hspi->RxXferCount--;\n\n  if(hspi->RxXferCount == 0U)\n  {\n#if (USE_SPI_CRC != 0U)\n    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n    {\n      hspi->RxISR =  SPI_2linesRxISR_16BITCRC;\n      return;\n    }\n#endif /* USE_SPI_CRC */\n\n    /* Disable RXNE interrupt */\n    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\n\n    if(hspi->TxXferCount == 0U)\n    {\n      SPI_CloseRxTx_ISR(hspi);\n    }\n  }\n}\n\n#if (USE_SPI_CRC != 0U)\n/**\n  * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)\n{\n  /* Receive data in 16 Bit mode */\n  __IO uint16_t tmpreg = 0U;\n\n  /* Read data register to flush CRC */\n  tmpreg = hspi->Instance->DR;\n\n  /* To avoid GCC warning */\n  UNUSED(tmpreg);\n\n  /* Disable RXNE interrupt */\n  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\n\n  SPI_CloseRxTx_ISR(hspi);\n}\n#endif /* USE_SPI_CRC */\n\n/**\n  * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\n{\n  /* Transmit data in 16 Bit mode */\n  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\n  hspi->pTxBuffPtr += sizeof(uint16_t);\n  hspi->TxXferCount--;\n\n  /* Enable CRC Transmission */\n  if(hspi->TxXferCount == 0U)\n  {\n#if (USE_SPI_CRC != 0U)\n    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n    {\n      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\n      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\n      return;\n    }\n#endif /* USE_SPI_CRC */\n\n    /* Disable TXE interrupt */\n    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\n\n    if(hspi->RxXferCount == 0U)\n    {\n      SPI_CloseRxTx_ISR(hspi);\n    }\n  }\n}\n\n#if (USE_SPI_CRC != 0U)\n/**\n  * @brief  Manage the CRC 8-bit receive in Interrupt context.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)\n{\n  __IO uint8_t tmpreg = 0U;\n\n  /* Read data register to flush CRC */\n  tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);\n\n  /* To avoid GCC warning */\n  UNUSED(tmpreg);\n\n  SPI_CloseRx_ISR(hspi);\n}\n#endif /* USE_SPI_CRC */\n\n/**\n  * @brief  Manage the receive 8-bit in Interrupt context.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\n{\n  *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);\n  hspi->RxXferCount--;\n\n#if (USE_SPI_CRC != 0U)\n  /* Enable CRC Transmission */\n  if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\n  {\n    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\n  }\n#endif /* USE_SPI_CRC */\n\n  if(hspi->RxXferCount == 0U)\n  {\n#if (USE_SPI_CRC != 0U)\n    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n    {\n      hspi->RxISR =  SPI_RxISR_8BITCRC;\n      return;\n    }\n#endif /* USE_SPI_CRC */\n    SPI_CloseRx_ISR(hspi);\n  }\n}\n\n#if (USE_SPI_CRC != 0U)\n/**\n  * @brief  Manage the CRC 16-bit receive in Interrupt context.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)\n{\n  __IO uint16_t tmpreg = 0U;\n\n  /* Read data register to flush CRC */\n  tmpreg = hspi->Instance->DR;\n\n  /* To avoid GCC warning */\n  UNUSED(tmpreg);\n\n  /* Disable RXNE and ERR interrupt */\n  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\n\n  SPI_CloseRx_ISR(hspi);\n}\n#endif /* USE_SPI_CRC */\n\n/**\n  * @brief  Manage the 16-bit receive in Interrupt context.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\n{\n  *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;\n  hspi->pRxBuffPtr += sizeof(uint16_t);\n  hspi->RxXferCount--;\n\n#if (USE_SPI_CRC != 0U)\n  /* Enable CRC Transmission */\n  if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\n  {\n    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\n  }\n#endif /* USE_SPI_CRC */\n\n  if(hspi->RxXferCount == 0U)\n  {\n#if (USE_SPI_CRC != 0U)\n    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n    {\n      hspi->RxISR = SPI_RxISR_16BITCRC;\n      return;\n    }\n#endif /* USE_SPI_CRC */\n    SPI_CloseRx_ISR(hspi);\n  }\n}\n\n/**\n  * @brief  Handle the data 8-bit transmit in Interrupt mode.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\n{\n  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);\n  hspi->TxXferCount--;\n\n  if(hspi->TxXferCount == 0U)\n  {\n#if (USE_SPI_CRC != 0U)\n    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n    {\n      /* Enable CRC Transmission */\n      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\n    }\n#endif /* USE_SPI_CRC */\n    SPI_CloseTx_ISR(hspi);\n  }\n}\n\n/**\n  * @brief  Handle the data 16-bit transmit in Interrupt mode.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\n{\n  /* Transmit data in 16 Bit mode */\n  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\n  hspi->pTxBuffPtr += sizeof(uint16_t);\n  hspi->TxXferCount--;\n\n  if(hspi->TxXferCount == 0U)\n  {\n#if (USE_SPI_CRC != 0U)\n    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n    {\n      /* Enable CRC Transmission */\n      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\n    }\n#endif /* USE_SPI_CRC */\n    SPI_CloseTx_ISR(hspi);\n  }\n}\n\n/**\n  * @brief Handle SPI Communication Timeout.\n  * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *              the configuration information for SPI module.\n  * @param Flag: SPI flag to check\n  * @param State: flag state to check\n  * @param Timeout: Timeout duration\n  * @param Tickstart: tick start value\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)\n{\n  while((((hspi->Instance->SR & Flag) == (Flag)) ? SET : RESET) != State)\n  {\n    if(Timeout != HAL_MAX_DELAY)\n    {\n      if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) >= Timeout))\n      {\n        /* Disable the SPI and reset the CRC: the CRC value should be cleared\n        on both master and slave sides in order to resynchronize the master\n        and slave for their respective CRC calculation */\n\n        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */\n        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\n\n        if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\n        {\n          /* Disable SPI peripheral */\n          __HAL_SPI_DISABLE(hspi);\n        }\n\n        /* Reset CRC Calculation */\n        if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n        {\n          SPI_RESET_CRC(hspi);\n        }\n\n        hspi->State= HAL_SPI_STATE_READY;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hspi);\n\n        return HAL_TIMEOUT;\n      }\n    }\n  }\n\n  return HAL_OK;\n}\n/**\n  * @brief Handle to check BSY flag before start a new transaction.\n  * @param hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *              the configuration information for SPI module.\n  * @param Timeout: Timeout duration\n  * @param Tickstart: tick start value\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)\n{\n  /* Control the BSY flag */\n  if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)\n  {\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n    return HAL_TIMEOUT;\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  Handle the end of the RXTX transaction.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)\n{\n  uint32_t tickstart = 0U;\n  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\n  /* Init tickstart for timeout managment*/\n  tickstart = HAL_GetTick();\n\n  /* Disable ERR interrupt */\n  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\n\n  /* Wait until TXE flag is set */\n  do\n  {\n    if(count-- == 0U)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n      break;\n    }\n  }\n  while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);\n\n  /* Check the end of the transaction */\n  if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK)\n  {\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n  }\n\n  /* Clear overrun flag in 2 Lines communication mode because received is not read */\n  if(hspi->Init.Direction == SPI_DIRECTION_2LINES)\n  {\n    __HAL_SPI_CLEAR_OVRFLAG(hspi);\n  }\n\n#if (USE_SPI_CRC != 0U)\n  /* Check if CRC error occurred */\n  if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\n  {\n    hspi->State = HAL_SPI_STATE_READY;\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\n    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\n    HAL_SPI_ErrorCallback(hspi);\n  }\n  else\n  {\n#endif /* USE_SPI_CRC */\n    if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)\n    {\n      if(hspi->State == HAL_SPI_STATE_BUSY_RX)\n      {\n        hspi->State = HAL_SPI_STATE_READY;\n        HAL_SPI_RxCpltCallback(hspi);\n      }\n      else\n      {\n        hspi->State = HAL_SPI_STATE_READY;\n        HAL_SPI_TxRxCpltCallback(hspi);\n      }\n    }\n    else\n    {\n      hspi->State = HAL_SPI_STATE_READY;\n      HAL_SPI_ErrorCallback(hspi);\n    }\n#if (USE_SPI_CRC != 0U)\n  }\n#endif /* USE_SPI_CRC */\n}\n\n/**\n  * @brief  Handle the end of the RX transaction.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)\n{\n    /* Disable RXNE and ERR interrupt */\n    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\n\n    /* Check the end of the transaction */\n    if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\n    {\n      /* Disable SPI peripheral */\n      __HAL_SPI_DISABLE(hspi);\n    }\n\n    /* Clear overrun flag in 2 Lines communication mode because received is not read */\n    if(hspi->Init.Direction == SPI_DIRECTION_2LINES)\n    {\n      __HAL_SPI_CLEAR_OVRFLAG(hspi);\n    }\n    hspi->State = HAL_SPI_STATE_READY;\n\n#if (USE_SPI_CRC != 0U)\n    /* Check if CRC error occurred */\n    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\n      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\n      HAL_SPI_ErrorCallback(hspi);\n    }\n    else\n    {\n#endif /* USE_SPI_CRC */\n      if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)\n      {\n        HAL_SPI_RxCpltCallback(hspi);\n      }\n      else\n      {\n        HAL_SPI_ErrorCallback(hspi);\n      }\n#if (USE_SPI_CRC != 0U)\n    }\n#endif /* USE_SPI_CRC */\n}\n\n/**\n  * @brief  Handle the end of the TX transaction.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)\n{\n  uint32_t tickstart = 0U;\n  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\n\n  /* Init tickstart for timeout management*/\n  tickstart = HAL_GetTick();\n\n  /* Wait until TXE flag is set */\n  do\n  {\n    if(count-- == 0U)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n      break;\n    }\n  }\n  while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);\n\n  /* Disable TXE and ERR interrupt */\n  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));\n\n  /* Check Busy flag */\n  if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\n  {\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n  }\n\n  /* Clear overrun flag in 2 Lines communication mode because received is not read */\n  if(hspi->Init.Direction == SPI_DIRECTION_2LINES)\n  {\n    __HAL_SPI_CLEAR_OVRFLAG(hspi);\n  }\n\n  hspi->State = HAL_SPI_STATE_READY;\n  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)\n  {\n    HAL_SPI_ErrorCallback(hspi);\n  }\n  else\n  {\n    HAL_SPI_TxCpltCallback(hspi);\n  }\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @brief  Handle abort a Tx or Rx transaction.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)\n{\n  __IO uint32_t tmpreg = 0U;\n  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\n\n  /* Wait until TXE flag is set */\n  do\n  {\n    if(count-- == 0U)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n      break;\n    }\n  }\n  while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);\n\n  /* Disable SPI Peripheral */\n  __HAL_SPI_DISABLE(hspi);\n\n  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */\n  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));\n\n  /* Flush DR Register */\n  tmpreg = (*(__IO uint32_t *)&hspi->Instance->DR);\n\n  /* To avoid GCC warning */\n  UNUSED(tmpreg);\n}\n\n/**\n  * @brief  Handle abort a Tx or Rx transaction.\n  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)\n{\n  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */\n  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));\n\n  /* Disable SPI Peripheral */\n  __HAL_SPI_DISABLE(hspi);\n}\n/**\n  * @}\n  */\n#endif /* HAL_SPI_MODULE_ENABLED */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_hal_spi.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_spi.h\n  * @author  MCD Application Team\n  * @version V1.7.1\n  * @date    14-April-2017\n  * @brief   Header file of SPI HAL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_SPI_H\n#define __STM32F4xx_HAL_SPI_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup SPI\n  * @{\n  */\n\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup SPI_Exported_Types SPI Exported Types\n  * @{\n  */\n\n/**\n  * @brief  SPI Configuration Structure definition\n  */\ntypedef struct\n{\n  uint32_t Mode;               /*!< Specifies the SPI operating mode.\n                                     This parameter can be a value of @ref SPI_Mode */\n\n  uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.\n                                     This parameter can be a value of @ref SPI_Direction */\n\n  uint32_t DataSize;           /*!< Specifies the SPI data size.\n                                     This parameter can be a value of @ref SPI_Data_Size */\n\n  uint32_t CLKPolarity;        /*!< Specifies the serial clock steady state.\n                                    This parameter can be a value of @ref SPI_Clock_Polarity */\n\n  uint32_t CLKPhase;           /*!< Specifies the clock active edge for the bit capture.\n                                    This parameter can be a value of @ref SPI_Clock_Phase */\n\n  uint32_t NSS;                /*!< Specifies whether the NSS signal is managed by\n                                    hardware (NSS pin) or by software using the SSI bit.\n                                    This parameter can be a value of @ref SPI_Slave_Select_management */\n\n  uint32_t BaudRatePrescaler;  /*!< Specifies the Baud Rate prescaler value which will be\n                                    used to configure the transmit and receive SCK clock.\n                                    This parameter can be a value of @ref SPI_BaudRate_Prescaler\n                                    @note The communication clock is derived from the master\n                                     clock. The slave clock does not need to be set. */\n\n  uint32_t FirstBit;           /*!< Specifies whether data transfers start from MSB or LSB bit.\n                                    This parameter can be a value of @ref SPI_MSB_LSB_transmission */\n\n  uint32_t TIMode;             /*!< Specifies if the TI mode is enabled or not.\n                                    This parameter can be a value of @ref SPI_TI_mode */\n\n  uint32_t CRCCalculation;     /*!< Specifies if the CRC calculation is enabled or not.\n                                    This parameter can be a value of @ref SPI_CRC_Calculation */\n\n  uint32_t CRCPolynomial;      /*!< Specifies the polynomial used for the CRC calculation.\n                                    This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */\n}SPI_InitTypeDef;\n\n/**\n  * @brief  HAL SPI State structure definition\n  */\ntypedef enum\n{\n  HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */\n  HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */\n  HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */\n  HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */\n  HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */\n  HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */\n  HAL_SPI_STATE_ERROR      = 0x06U     /*!< SPI error state                                    */\n}HAL_SPI_StateTypeDef;\n\n/**\n  * @brief  SPI handle Structure definition\n  */\ntypedef struct __SPI_HandleTypeDef\n{\n  SPI_TypeDef                *Instance;    /* SPI registers base address */\n\n  SPI_InitTypeDef            Init;         /* SPI communication parameters */\n\n  uint8_t                    *pTxBuffPtr;  /* Pointer to SPI Tx transfer Buffer */\n\n  uint16_t                   TxXferSize;   /* SPI Tx Transfer size */\n\n  __IO uint16_t              TxXferCount;  /* SPI Tx Transfer Counter */\n\n  uint8_t                    *pRxBuffPtr;  /* Pointer to SPI Rx transfer Buffer */\n\n  uint16_t                   RxXferSize;   /* SPI Rx Transfer size */\n\n  __IO uint16_t              RxXferCount;  /* SPI Rx Transfer Counter */\n\n  void                       (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */\n\n  void                       (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */\n\n#if 0 // XXX DMA\n  DMA_HandleTypeDef          *hdmatx;      /* SPI Tx DMA Handle parameters   */\n\n  DMA_HandleTypeDef          *hdmarx;      /* SPI Rx DMA Handle parameters   */\n#endif // XXX DMA\n\n  HAL_LockTypeDef            Lock;         /* Locking object                 */\n\n  __IO HAL_SPI_StateTypeDef  State;        /* SPI communication state */\n\n  __IO uint32_t              ErrorCode;    /* SPI Error code */\n\n}SPI_HandleTypeDef;\n\n/**\n  * @}\n  */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup SPI_Exported_Constants SPI Exported Constants\n  * @{\n  */\n\n/** @defgroup SPI_Error_Code SPI Error Code\n  * @{\n  */\n#define HAL_SPI_ERROR_NONE              0x00000000U   /*!< No error             */\n#define HAL_SPI_ERROR_MODF              0x00000001U   /*!< MODF error           */\n#define HAL_SPI_ERROR_CRC               0x00000002U   /*!< CRC error            */\n#define HAL_SPI_ERROR_OVR               0x00000004U   /*!< OVR error            */\n#define HAL_SPI_ERROR_FRE               0x00000008U   /*!< FRE error            */\n#define HAL_SPI_ERROR_DMA               0x00000010U   /*!< DMA transfer error   */\n#define HAL_SPI_ERROR_FLAG              0x00000020U   /*!< Flag: RXNE,TXE, BSY  */\n/**\n  * @}\n  */\n\n/** @defgroup SPI_Mode SPI Mode\n  * @{\n  */\n#define SPI_MODE_SLAVE                  0x00000000U\n#define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)\n/**\n  * @}\n  */\n\n/** @defgroup SPI_Direction SPI Direction Mode\n  * @{\n  */\n#define SPI_DIRECTION_2LINES            0x00000000U\n#define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY\n#define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE\n/**\n  * @}\n  */\n\n/** @defgroup SPI_Data_Size SPI Data Size\n  * @{\n  */\n#define SPI_DATASIZE_8BIT               0x00000000U\n#define SPI_DATASIZE_16BIT              SPI_CR1_DFF\n/**\n  * @}\n  */\n\n/** @defgroup SPI_Clock_Polarity SPI Clock Polarity\n  * @{\n  */\n#define SPI_POLARITY_LOW                0x00000000U\n#define SPI_POLARITY_HIGH               SPI_CR1_CPOL\n/**\n  * @}\n  */\n\n/** @defgroup SPI_Clock_Phase SPI Clock Phase\n  * @{\n  */\n#define SPI_PHASE_1EDGE                 0x00000000U\n#define SPI_PHASE_2EDGE                 SPI_CR1_CPHA\n/**\n  * @}\n  */\n\n/** @defgroup SPI_Slave_Select_management SPI Slave Select Management\n  * @{\n  */\n#define SPI_NSS_SOFT                    SPI_CR1_SSM\n#define SPI_NSS_HARD_INPUT              0x00000000U\n#define SPI_NSS_HARD_OUTPUT             0x00040000U\n/**\n  * @}\n  */\n\n/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler\n  * @{\n  */\n#define SPI_BAUDRATEPRESCALER_2         0x00000000U\n#define SPI_BAUDRATEPRESCALER_4         0x00000008U\n#define SPI_BAUDRATEPRESCALER_8         0x00000010U\n#define SPI_BAUDRATEPRESCALER_16        0x00000018U\n#define SPI_BAUDRATEPRESCALER_32        0x00000020U\n#define SPI_BAUDRATEPRESCALER_64        0x00000028U\n#define SPI_BAUDRATEPRESCALER_128       0x00000030U\n#define SPI_BAUDRATEPRESCALER_256       0x00000038U\n/**\n  * @}\n  */\n\n/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission\n  * @{\n  */\n#define SPI_FIRSTBIT_MSB                0x00000000U\n#define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST\n/**\n  * @}\n  */\n\n/** @defgroup SPI_TI_mode SPI TI Mode\n  * @{\n  */\n#define SPI_TIMODE_DISABLE             0x00000000U\n#define SPI_TIMODE_ENABLE              SPI_CR2_FRF\n/**\n  * @}\n  */\n\n/** @defgroup SPI_CRC_Calculation SPI CRC Calculation\n  * @{\n  */\n#define SPI_CRCCALCULATION_DISABLE     0x00000000U\n#define SPI_CRCCALCULATION_ENABLE      SPI_CR1_CRCEN\n/**\n  * @}\n  */\n\n/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition\n  * @{\n  */\n#define SPI_IT_TXE                      SPI_CR2_TXEIE\n#define SPI_IT_RXNE                     SPI_CR2_RXNEIE\n#define SPI_IT_ERR                      SPI_CR2_ERRIE\n/**\n  * @}\n  */\n\n/** @defgroup SPI_Flags_definition SPI Flags Definition\n  * @{\n  */\n#define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag */\n#define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag */\n#define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag */\n#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag */\n#define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag */\n#define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag */\n#define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup SPI_Exported_Macros SPI Exported Macros\n  * @{\n  */\n\n/** @brief  Reset SPI handle state.\n  * @param  __HANDLE__: specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @retval None\n  */\n#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)\n\n/** @brief  Enable or disable the specified SPI interrupts.\n  * @param  __HANDLE__: specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.\n  *         This parameter can be one of the following values:\n  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable\n  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\n  *            @arg SPI_IT_ERR: Error interrupt enable\n  * @retval None\n  */\n#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))\n#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))\n\n/** @brief  Check whether the specified SPI interrupt source is enabled or not.\n  * @param  __HANDLE__: specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @param  __INTERRUPT__: specifies the SPI interrupt source to check.\n  *          This parameter can be one of the following values:\n  *             @arg SPI_IT_TXE: Tx buffer empty interrupt enable\n  *             @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\n  *             @arg SPI_IT_ERR: Error interrupt enable\n  * @retval The new state of __IT__ (TRUE or FALSE).\n  */\n#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\n\n/** @brief  Check whether the specified SPI flag is set or not.\n  * @param  __HANDLE__: specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @param  __FLAG__: specifies the flag to check.\n  *         This parameter can be one of the following values:\n  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag\n  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag\n  *            @arg SPI_FLAG_CRCERR: CRC error flag\n  *            @arg SPI_FLAG_MODF: Mode fault flag\n  *            @arg SPI_FLAG_OVR: Overrun flag\n  *            @arg SPI_FLAG_BSY: Busy flag\n  *            @arg SPI_FLAG_FRE: Frame format error flag\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\n  */\n#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\n\n/** @brief  Clear the SPI CRCERR pending flag.\n  * @param  __HANDLE__: specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @retval None\n  */\n#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))\n\n/** @brief  Clear the SPI MODF pending flag.\n  * @param  __HANDLE__: specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @retval None\n  */\n#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)       \\\n  do{                                              \\\n    __IO uint32_t tmpreg_modf = 0x00U;             \\\n    tmpreg_modf = (__HANDLE__)->Instance->SR;      \\\n    (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \\\n    UNUSED(tmpreg_modf);                           \\\n  } while(0U)\n\n/** @brief  Clear the SPI OVR pending flag.\n  * @param  __HANDLE__: specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @retval None\n  */\n#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \\\n  do{                                              \\\n    __IO uint32_t tmpreg_ovr = 0x00U;              \\\n    tmpreg_ovr = (__HANDLE__)->Instance->DR;       \\\n    tmpreg_ovr = (__HANDLE__)->Instance->SR;       \\\n    UNUSED(tmpreg_ovr);                            \\\n  } while(0U)\n\n/** @brief  Clear the SPI FRE pending flag.\n  * @param  __HANDLE__: specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @retval None\n  */\n#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \\\n  do{                                              \\\n  __IO uint32_t tmpreg_fre = 0x00U;                \\\n  tmpreg_fre = (__HANDLE__)->Instance->SR;         \\\n  UNUSED(tmpreg_fre);                              \\\n  }while(0U)\n\n/** @brief  Enable the SPI peripheral.\n  * @param  __HANDLE__: specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @retval None\n  */\n#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SPI_CR1_SPE)\n\n/** @brief  Disable the SPI peripheral.\n  * @param  __HANDLE__: specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @retval None\n  */\n#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup SPI_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup SPI_Exported_Functions_Group1\n  * @{\n  */\n/* Initialization/de-initialization functions  **********************************/\nHAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);\nHAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);\nvoid HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);\nvoid HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);\n/**\n  * @}\n  */\n\n/** @addtogroup SPI_Exported_Functions_Group2\n  * @{\n  */\n/* I/O operation functions  *****************************************************/\nHAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);\nHAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);\nHAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);\nHAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);\n#if 0 // XXX DMA\nHAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);\nHAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);\nHAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);\nHAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);\n#endif // XXX DMA\n/* Transfer Abort functions */\nHAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);\nHAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);\n\nvoid HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);\nvoid HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);\nvoid HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);\nvoid HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);\nvoid HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);\nvoid HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);\nvoid HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);\nvoid HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);\nvoid HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);\n/**\n  * @}\n  */\n\n/** @addtogroup SPI_Exported_Functions_Group3\n  * @{\n  */\n/* Peripheral State and Error functions ***************************************/\nHAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);\nuint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup SPI_Private_Macros SPI Private Macros\n  * @{\n  */\n\n/** @brief  Set the SPI transmit-only mode.\n  * @param  __HANDLE__: specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @retval None\n  */\n#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)\n\n/** @brief  Set the SPI receive-only mode.\n  * @param  __HANDLE__: specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @retval None\n  */\n#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))\n\n/** @brief  Reset the CRC calculation of the SPI.\n  * @param  __HANDLE__: specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @retval None\n  */\n#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\\\n                                     (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0U)\n\n#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \\\n                           ((MODE) == SPI_MODE_MASTER))\n\n#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES)        || \\\n                                ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \\\n                                ((MODE) == SPI_DIRECTION_1LINE))\n\n#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)\n\n#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)  || \\\n                                                ((MODE) == SPI_DIRECTION_1LINE))\n\n#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \\\n                                   ((DATASIZE) == SPI_DATASIZE_8BIT))\n\n#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \\\n                           ((CPOL) == SPI_POLARITY_HIGH))\n\n#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \\\n                           ((CPHA) == SPI_PHASE_2EDGE))\n\n#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT)       || \\\n                         ((NSS) == SPI_NSS_HARD_INPUT) || \\\n                         ((NSS) == SPI_NSS_HARD_OUTPUT))\n\n#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \\\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \\\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \\\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \\\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \\\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \\\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \\\n                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))\n\n#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \\\n                               ((BIT) == SPI_FIRSTBIT_LSB))\n\n#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \\\n                             ((MODE) == SPI_TIMODE_ENABLE))\n\n#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \\\n                                             ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))\n\n#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))\n\n/**\n  * @}\n  */\n\n/* Private functions ---------------------------------------------------------*/\n/** @defgroup SPI_Private_Functions SPI Private Functions\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_HAL_SPI_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_ll_bus.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_bus.h\n  * @author  MCD Application Team\n  * @version V1.7.1\n  * @date    14-April-2017\n  * @brief   Header file of BUS LL module.\n\n  @verbatim\n                      ##### RCC Limitations #####\n  ==============================================================================\n    [..]\n      A delay between an RCC peripheral clock enable and the effective peripheral\n      enabling should be taken into account in order to manage the peripheral read/write\n      from/to registers.\n      (+) This delay depends on the peripheral mapping.\n        (++) AHB & APB peripherals, 1 dummy read is necessary\n\n    [..]\n      Workarounds:\n      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been\n          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_LL_BUS_H\n#define __STM32F4xx_LL_BUS_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined(RCC)\n\n/** @defgroup BUS_LL BUS\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants\n  * @{\n  */\n\n/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH\n  * @{\n  */\n#define LL_AHB1_GRP1_PERIPH_ALL             0xFFFFFFFFU\n#define LL_AHB1_GRP1_PERIPH_GPIOA           RCC_AHB1ENR_GPIOAEN\n#define LL_AHB1_GRP1_PERIPH_GPIOB           RCC_AHB1ENR_GPIOBEN\n#define LL_AHB1_GRP1_PERIPH_GPIOC           RCC_AHB1ENR_GPIOCEN\n#if defined(GPIOD)\n#define LL_AHB1_GRP1_PERIPH_GPIOD           RCC_AHB1ENR_GPIODEN\n#endif /* GPIOD */\n#if defined(GPIOE)\n#define LL_AHB1_GRP1_PERIPH_GPIOE           RCC_AHB1ENR_GPIOEEN\n#endif /* GPIOE */\n#if defined(GPIOF)\n#define LL_AHB1_GRP1_PERIPH_GPIOF           RCC_AHB1ENR_GPIOFEN\n#endif /* GPIOF */\n#if defined(GPIOG)\n#define LL_AHB1_GRP1_PERIPH_GPIOG           RCC_AHB1ENR_GPIOGEN\n#endif /* GPIOG */\n#if defined(GPIOH)\n#define LL_AHB1_GRP1_PERIPH_GPIOH           RCC_AHB1ENR_GPIOHEN\n#endif /* GPIOH */\n#if defined(GPIOI)\n#define LL_AHB1_GRP1_PERIPH_GPIOI           RCC_AHB1ENR_GPIOIEN\n#endif /* GPIOI */\n#if defined(GPIOJ)\n#define LL_AHB1_GRP1_PERIPH_GPIOJ           RCC_AHB1ENR_GPIOJEN\n#endif /* GPIOJ */\n#if defined(GPIOK)\n#define LL_AHB1_GRP1_PERIPH_GPIOK           RCC_AHB1ENR_GPIOKEN\n#endif /* GPIOK */\n#define LL_AHB1_GRP1_PERIPH_CRC             RCC_AHB1ENR_CRCEN\n#if defined(RCC_AHB1ENR_BKPSRAMEN)\n#define LL_AHB1_GRP1_PERIPH_BKPSRAM         RCC_AHB1ENR_BKPSRAMEN\n#endif /* RCC_AHB1ENR_BKPSRAMEN */\n#if defined(RCC_AHB1ENR_CCMDATARAMEN)\n#define LL_AHB1_GRP1_PERIPH_CCMDATARAM      RCC_AHB1ENR_CCMDATARAMEN\n#endif /* RCC_AHB1ENR_CCMDATARAMEN */\n#define LL_AHB1_GRP1_PERIPH_DMA1            RCC_AHB1ENR_DMA1EN\n#define LL_AHB1_GRP1_PERIPH_DMA2            RCC_AHB1ENR_DMA2EN\n#if defined(RCC_AHB1ENR_RNGEN)\n#define LL_AHB1_GRP1_PERIPH_RNG             RCC_AHB1ENR_RNGEN\n#endif /* RCC_AHB1ENR_RNGEN */\n#if defined(DMA2D)\n#define LL_AHB1_GRP1_PERIPH_DMA2D           RCC_AHB1ENR_DMA2DEN\n#endif /* DMA2D */\n#if defined(ETH)\n#define LL_AHB1_GRP1_PERIPH_ETHMAC          RCC_AHB1ENR_ETHMACEN\n#define LL_AHB1_GRP1_PERIPH_ETHMACTX        RCC_AHB1ENR_ETHMACTXEN\n#define LL_AHB1_GRP1_PERIPH_ETHMACRX        RCC_AHB1ENR_ETHMACRXEN\n#define LL_AHB1_GRP1_PERIPH_ETHMACPTP       RCC_AHB1ENR_ETHMACPTPEN\n#endif /* ETH */\n#if defined(USB_OTG_HS)\n#define LL_AHB1_GRP1_PERIPH_OTGHS           RCC_AHB1ENR_OTGHSEN\n#define LL_AHB1_GRP1_PERIPH_OTGHSULPI       RCC_AHB1ENR_OTGHSULPIEN\n#endif /* USB_OTG_HS */\n#define LL_AHB1_GRP1_PERIPH_FLITF           RCC_AHB1LPENR_FLITFLPEN\n#define LL_AHB1_GRP1_PERIPH_SRAM1           RCC_AHB1LPENR_SRAM1LPEN\n#if defined(RCC_AHB1LPENR_SRAM2LPEN)\n#define LL_AHB1_GRP1_PERIPH_SRAM2           RCC_AHB1LPENR_SRAM2LPEN\n#endif /* RCC_AHB1LPENR_SRAM2LPEN */\n#if defined(RCC_AHB1LPENR_SRAM3LPEN)\n#define LL_AHB1_GRP1_PERIPH_SRAM3           RCC_AHB1LPENR_SRAM3LPEN\n#endif /* RCC_AHB1LPENR_SRAM3LPEN */\n/**\n  * @}\n  */\n\n#if defined(RCC_AHB2_SUPPORT)\n/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH\n  * @{\n  */\n#define LL_AHB2_GRP1_PERIPH_ALL            0xFFFFFFFFU\n#if defined(DCMI)\n#define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN\n#endif /* DCMI */\n#if defined(CRYP)\n#define LL_AHB2_GRP1_PERIPH_CRYP           RCC_AHB2ENR_CRYPEN\n#endif /* CRYP */\n#if defined(AES)\n#define LL_AHB2_GRP1_PERIPH_AES            RCC_AHB2ENR_AESEN\n#endif /* AES */\n#if defined(HASH)\n#define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN\n#endif /* HASH */\n#if defined(RCC_AHB2ENR_RNGEN)\n#define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN\n#endif /* RCC_AHB2ENR_RNGEN */\n#if defined(USB_OTG_FS)\n#define LL_AHB2_GRP1_PERIPH_OTGFS          RCC_AHB2ENR_OTGFSEN\n#endif /* USB_OTG_FS */\n/**\n  * @}\n  */\n#endif /* RCC_AHB2_SUPPORT */\n\n#if defined(RCC_AHB3_SUPPORT)\n/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH\n  * @{\n  */\n#define LL_AHB3_GRP1_PERIPH_ALL            0xFFFFFFFFU\n#if defined(FSMC_Bank1)\n#define LL_AHB3_GRP1_PERIPH_FSMC           RCC_AHB3ENR_FSMCEN\n#endif /* FSMC_Bank1 */\n#if defined(FMC_Bank1)\n#define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN\n#endif /* FMC_Bank1 */\n#if defined(QUADSPI)\n#define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN\n#endif /* QUADSPI */\n/**\n  * @}\n  */\n#endif /* RCC_AHB3_SUPPORT */\n\n/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH\n  * @{\n  */\n#define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU\n#if defined(TIM2)\n#define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR_TIM2EN\n#endif /* TIM2 */\n#if defined(TIM3)\n#define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR_TIM3EN\n#endif /* TIM3 */\n#if defined(TIM4)\n#define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR_TIM4EN\n#endif /* TIM4 */\n#define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR_TIM5EN\n#if defined(TIM6)\n#define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR_TIM6EN\n#endif /* TIM6 */\n#if defined(TIM7)\n#define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR_TIM7EN\n#endif /* TIM7 */\n#if defined(TIM12)\n#define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1ENR_TIM12EN\n#endif /* TIM12 */\n#if defined(TIM13)\n#define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1ENR_TIM13EN\n#endif /* TIM13 */\n#if defined(TIM14)\n#define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1ENR_TIM14EN\n#endif /* TIM14 */\n#if defined(LPTIM1)\n#define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR_LPTIM1EN\n#endif /* LPTIM1 */\n#if defined(RCC_APB1ENR_RTCAPBEN)\n#define LL_APB1_GRP1_PERIPH_RTCAPB         RCC_APB1ENR_RTCAPBEN\n#endif /* RCC_APB1ENR_RTCAPBEN */\n#define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR_WWDGEN\n#if defined(SPI2)\n#define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR_SPI2EN\n#endif /* SPI2 */\n#if defined(SPI3)\n#define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR_SPI3EN\n#endif /* SPI3 */\n#if defined(SPDIFRX)\n#define LL_APB1_GRP1_PERIPH_SPDIFRX        RCC_APB1ENR_SPDIFRXEN\n#endif /* SPDIFRX */\n#define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR_USART2EN\n#if defined(USART3)\n#define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR_USART3EN\n#endif /* USART3 */\n#if defined(UART4)\n#define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR_UART4EN\n#endif /* UART4 */\n#if defined(UART5)\n#define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR_UART5EN\n#endif /* UART5 */\n#define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR_I2C1EN\n#define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR_I2C2EN\n#if defined(I2C3)\n#define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR_I2C3EN\n#endif /* I2C3 */\n#if defined(FMPI2C1)\n#define LL_APB1_GRP1_PERIPH_FMPI2C1        RCC_APB1ENR_FMPI2C1EN\n#endif /* FMPI2C1 */\n#if defined(CAN1)\n#define LL_APB1_GRP1_PERIPH_CAN1           RCC_APB1ENR_CAN1EN\n#endif /* CAN1 */\n#if defined(CAN2)\n#define LL_APB1_GRP1_PERIPH_CAN2           RCC_APB1ENR_CAN2EN\n#endif /* CAN2 */\n#if defined(CAN3)\n#define LL_APB1_GRP1_PERIPH_CAN3           RCC_APB1ENR_CAN3EN\n#endif /* CAN3 */\n#if defined(CEC)\n#define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1ENR_CECEN\n#endif /* CEC */\n#define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR_PWREN\n#if defined(DAC1)\n#define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR_DACEN\n#endif /* DAC1 */\n#if defined(UART7)\n#define LL_APB1_GRP1_PERIPH_UART7          RCC_APB1ENR_UART7EN\n#endif /* UART7 */\n#if defined(UART8)\n#define LL_APB1_GRP1_PERIPH_UART8          RCC_APB1ENR_UART8EN\n#endif /* UART8 */\n/**\n  * @}\n  */\n\n/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH\n  * @{\n  */\n#define LL_APB2_GRP1_PERIPH_ALL          0xFFFFFFFFU\n#define LL_APB2_GRP1_PERIPH_TIM1         RCC_APB2ENR_TIM1EN\n#if defined(TIM8)\n#define LL_APB2_GRP1_PERIPH_TIM8         RCC_APB2ENR_TIM8EN\n#endif /* TIM8 */\n#define LL_APB2_GRP1_PERIPH_USART1       RCC_APB2ENR_USART1EN\n#if defined(USART6)\n#define LL_APB2_GRP1_PERIPH_USART6       RCC_APB2ENR_USART6EN\n#endif /* USART6 */\n#if defined(UART9)\n#define LL_APB2_GRP1_PERIPH_UART9        RCC_APB2ENR_UART9EN\n#endif /* UART9 */\n#if defined(UART10)\n#define LL_APB2_GRP1_PERIPH_UART10       RCC_APB2ENR_UART10EN\n#endif /* UART10 */\n#define LL_APB2_GRP1_PERIPH_ADC1         RCC_APB2ENR_ADC1EN\n#if defined(ADC2)\n#define LL_APB2_GRP1_PERIPH_ADC2         RCC_APB2ENR_ADC2EN\n#endif /* ADC2 */\n#if defined(ADC3)\n#define LL_APB2_GRP1_PERIPH_ADC3         RCC_APB2ENR_ADC3EN\n#endif /* ADC3 */\n#if defined(SDIO)\n#define LL_APB2_GRP1_PERIPH_SDIO         RCC_APB2ENR_SDIOEN\n#endif /* SDIO */\n#define LL_APB2_GRP1_PERIPH_SPI1         RCC_APB2ENR_SPI1EN\n#if defined(SPI4)\n#define LL_APB2_GRP1_PERIPH_SPI4         RCC_APB2ENR_SPI4EN\n#endif /* SPI4 */\n#define LL_APB2_GRP1_PERIPH_SYSCFG       RCC_APB2ENR_SYSCFGEN\n#if defined(RCC_APB2ENR_EXTITEN)\n#define LL_APB2_GRP1_PERIPH_EXTI         RCC_APB2ENR_EXTITEN\n#endif /* RCC_APB2ENR_EXTITEN */\n#define LL_APB2_GRP1_PERIPH_TIM9         RCC_APB2ENR_TIM9EN\n#if defined(TIM10)\n#define LL_APB2_GRP1_PERIPH_TIM10        RCC_APB2ENR_TIM10EN\n#endif /* TIM10 */\n#define LL_APB2_GRP1_PERIPH_TIM11        RCC_APB2ENR_TIM11EN\n#if defined(SPI5)\n#define LL_APB2_GRP1_PERIPH_SPI5         RCC_APB2ENR_SPI5EN\n#endif /* SPI5 */\n#if defined(SPI6)\n#define LL_APB2_GRP1_PERIPH_SPI6         RCC_APB2ENR_SPI6EN\n#endif /* SPI6 */\n#if defined(SAI1)\n#define LL_APB2_GRP1_PERIPH_SAI1         RCC_APB2ENR_SAI1EN\n#endif /* SAI1 */\n#if defined(SAI2)\n#define LL_APB2_GRP1_PERIPH_SAI2         RCC_APB2ENR_SAI2EN\n#endif /* SAI2 */\n#if defined(LTDC)\n#define LL_APB2_GRP1_PERIPH_LTDC         RCC_APB2ENR_LTDCEN\n#endif /* LTDC */\n#if defined(DSI)\n#define LL_APB2_GRP1_PERIPH_DSI          RCC_APB2ENR_DSIEN\n#endif /* DSI */\n#if defined(DFSDM1_Channel0)\n#define LL_APB2_GRP1_PERIPH_DFSDM1       RCC_APB2ENR_DFSDM1EN\n#endif /* DFSDM1_Channel0 */\n#if defined(DFSDM2_Channel0)\n#define LL_APB2_GRP1_PERIPH_DFSDM2       RCC_APB2ENR_DFSDM2EN\n#endif /* DFSDM2_Channel0 */\n#define LL_APB2_GRP1_PERIPH_ADC          RCC_APB2RSTR_ADCRST\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions\n  * @{\n  */\n\n/** @defgroup BUS_LL_EF_AHB1 AHB1\n  * @{\n  */\n\n/**\n  * @brief  Enable AHB1 peripherals clock.\n  * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      CRCEN              LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      CCMDATARAMEN       LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      RNGEN              LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_EnableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->AHB1ENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Check if AHB1 peripheral clock is enabled or not\n  * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      CRCEN              LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      CCMDATARAMEN       LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      RNGEN              LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_IsEnabledClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval State of Periphs (1 or 0).\n*/\n__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)\n{\n  return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);\n}\n\n/**\n  * @brief  Disable AHB1 peripherals clock.\n  * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      CRCEN              LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      CCMDATARAMEN       LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      RNGEN              LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_DisableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB1ENR, Periphs);\n}\n\n/**\n  * @brief  Force AHB1 peripherals reset.\n  * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     RNGRST        LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ForceReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)\n{\n  SET_BIT(RCC->AHB1RSTR, Periphs);\n}\n\n/**\n  * @brief  Release AHB1 peripherals reset.\n  * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     RNGRST        LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ReleaseReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB1RSTR, Periphs);\n}\n\n/**\n  * @brief  Enable AHB1 peripheral clocks in low-power mode\n  * @rmtoll AHB1LPENR    GPIOALPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    GPIOBLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    GPIOCLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    GPIODLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    GPIOELPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    GPIOFLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    GPIOGLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    GPIOHLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    GPIOILPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    GPIOJLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    GPIOKLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    CRCLPEN        LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    FLITFLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    SRAM1LPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    SRAM2LPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    SRAM3LPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    DMA1LPEN       LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    DMA2LPEN       LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    DMA2DLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    RNGLPEN        LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    ETHMACLPEN     LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    ETHMACTXLPEN   LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    ETHMACRXLPEN   LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    ETHMACPTPLPEN  LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    OTGHSLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockLowPower\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLITF\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->AHB1LPENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Disable AHB1 peripheral clocks in low-power mode\n  * @rmtoll AHB1LPENR    GPIOALPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    GPIOBLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    GPIOCLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    GPIODLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    GPIOELPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    GPIOFLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    GPIOGLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    GPIOHLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    GPIOILPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    GPIOJLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    GPIOKLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    CRCLPEN        LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    FLITFLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    SRAM1LPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    SRAM2LPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    SRAM3LPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    DMA1LPEN       LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    DMA2LPEN       LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    DMA2DLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    RNGLPEN        LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    ETHMACLPEN     LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    ETHMACTXLPEN   LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    ETHMACRXLPEN   LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    ETHMACPTPLPEN  LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    OTGHSLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockLowPower\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLITF\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB1LPENR, Periphs);\n}\n\n/**\n  * @}\n  */\n\n#if defined(RCC_AHB2_SUPPORT)\n/** @defgroup BUS_LL_EF_AHB2 AHB2\n  * @{\n  */\n\n/**\n  * @brief  Enable AHB2 peripherals clock.\n  * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      AESEN        LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      HASHEN       LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      RNGEN        LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_EnableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->AHB2ENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Check if AHB2 peripheral clock is enabled or not\n  * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      AESEN        LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      HASHEN       LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      RNGEN        LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_IsEnabledClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval State of Periphs (1 or 0).\n*/\n__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)\n{\n  return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);\n}\n\n/**\n  * @brief  Disable AHB2 peripherals clock.\n  * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      AESEN        LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      HASHEN       LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      RNGEN        LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_DisableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB2ENR, Periphs);\n}\n\n/**\n  * @brief  Force AHB2 peripherals reset.\n  * @rmtoll AHB2RSTR     DCMIRST      LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     CRYPRST      LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     AESRST       LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     HASHRST      LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     RNGRST       LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     OTGFSRST     LL_AHB2_GRP1_ForceReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)\n{\n  SET_BIT(RCC->AHB2RSTR, Periphs);\n}\n\n/**\n  * @brief  Release AHB2 peripherals reset.\n  * @rmtoll AHB2RSTR     DCMIRST      LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     CRYPRST      LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     AESRST       LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     HASHRST      LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     RNGRST       LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     OTGFSRST     LL_AHB2_GRP1_ReleaseReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB2RSTR, Periphs);\n}\n\n/**\n  * @brief  Enable AHB2 peripheral clocks in low-power mode\n  * @rmtoll AHB2LPENR    DCMILPEN     LL_AHB2_GRP1_EnableClockLowPower\\n\n  *         AHB2LPENR    CRYPLPEN     LL_AHB2_GRP1_EnableClockLowPower\\n\n  *         AHB2LPENR    AESLPEN      LL_AHB2_GRP1_EnableClockLowPower\\n\n  *         AHB2LPENR    HASHLPEN     LL_AHB2_GRP1_EnableClockLowPower\\n\n  *         AHB2LPENR    RNGLPEN      LL_AHB2_GRP1_EnableClockLowPower\\n\n  *         AHB2LPENR    OTGFSLPEN    LL_AHB2_GRP1_EnableClockLowPower\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->AHB2LPENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Disable AHB2 peripheral clocks in low-power mode\n  * @rmtoll AHB2LPENR    DCMILPEN     LL_AHB2_GRP1_DisableClockLowPower\\n\n  *         AHB2LPENR    CRYPLPEN     LL_AHB2_GRP1_DisableClockLowPower\\n\n  *         AHB2LPENR    AESLPEN      LL_AHB2_GRP1_DisableClockLowPower\\n\n  *         AHB2LPENR    HASHLPEN     LL_AHB2_GRP1_DisableClockLowPower\\n\n  *         AHB2LPENR    RNGLPEN      LL_AHB2_GRP1_DisableClockLowPower\\n\n  *         AHB2LPENR    OTGFSLPEN    LL_AHB2_GRP1_DisableClockLowPower\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB2LPENR, Periphs);\n}\n\n/**\n  * @}\n  */\n#endif /* RCC_AHB2_SUPPORT */\n\n#if defined(RCC_AHB3_SUPPORT)\n/** @defgroup BUS_LL_EF_AHB3 AHB3\n  * @{\n  */\n\n/**\n  * @brief  Enable AHB3 peripherals clock.\n  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\\n\n  *         AHB3ENR      FSMCEN        LL_AHB3_GRP1_EnableClock\\n\n  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->AHB3ENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Check if AHB3 peripheral clock is enabled or not\n  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\\n\n  *         AHB3ENR      FSMCEN        LL_AHB3_GRP1_IsEnabledClock\\n\n  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval State of Periphs (1 or 0).\n*/\n__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)\n{\n  return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);\n}\n\n/**\n  * @brief  Disable AHB3 peripherals clock.\n  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\\n\n  *         AHB3ENR      FSMCEN        LL_AHB3_GRP1_DisableClock\\n\n  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB3ENR, Periphs);\n}\n\n/**\n  * @brief  Force AHB3 peripherals reset.\n  * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\\n\n  *         AHB3RSTR     FSMCRST       LL_AHB3_GRP1_ForceReset\\n\n  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_ALL\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)\n{\n  SET_BIT(RCC->AHB3RSTR, Periphs);\n}\n\n/**\n  * @brief  Release AHB3 peripherals reset.\n  * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\\n\n  *         AHB3RSTR     FSMCRST       LL_AHB3_GRP1_ReleaseReset\\n\n  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB3RSTR, Periphs);\n}\n\n/**\n  * @brief  Enable AHB3 peripheral clocks in low-power mode\n  * @rmtoll AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_EnableClockLowPower\\n\n  *         AHB3LPENR    FSMCLPEN      LL_AHB3_GRP1_EnableClockLowPower\\n\n  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_EnableClockLowPower\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->AHB3LPENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Disable AHB3 peripheral clocks in low-power mode\n  * @rmtoll AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_DisableClockLowPower\\n\n  *         AHB3LPENR    FSMCLPEN      LL_AHB3_GRP1_DisableClockLowPower\\n\n  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_DisableClockLowPower\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB3LPENR, Periphs);\n}\n\n/**\n  * @}\n  */\n#endif /* RCC_AHB3_SUPPORT */\n\n/** @defgroup BUS_LL_EF_APB1 APB1\n  * @{\n  */\n\n/**\n  * @brief  Enable APB1 peripherals clock.\n  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     TIM3EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     TIM4EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     TIM5EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     TIM6EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     TIM7EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     TIM12EN       LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     TIM13EN       LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     TIM14EN       LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     WWDGEN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     SPI2EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     SPI3EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     USART2EN      LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     USART3EN      LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     UART4EN       LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     UART5EN       LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     I2C1EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     I2C2EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     I2C3EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     FMPI2C1EN     LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     CAN1EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     CAN2EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     CAN3EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     CECEN         LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     PWREN         LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     DACEN         LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     UART7EN       LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     UART8EN       LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     RTCAPBEN      LL_APB1_GRP1_EnableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->APB1ENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->APB1ENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Check if APB1 peripheral clock is enabled or not\n  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     TIM3EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     TIM4EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     TIM5EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     TIM6EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     TIM7EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     TIM12EN       LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     TIM13EN       LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     TIM14EN       LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     WWDGEN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     SPI2EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     SPI3EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     USART2EN      LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     USART3EN      LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     UART4EN       LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     UART5EN       LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     I2C1EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     I2C2EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     I2C3EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     FMPI2C1EN     LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     CAN1EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     CAN2EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     CAN3EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     CECEN         LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     PWREN         LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     DACEN         LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     UART7EN       LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     UART8EN       LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     RTCAPBEN      LL_APB1_GRP1_IsEnabledClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval State of Periphs (1 or 0).\n*/\n__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)\n{\n  return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);\n}\n\n/**\n  * @brief  Disable APB1 peripherals clock.\n  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     TIM3EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     TIM4EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     TIM5EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     TIM6EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     TIM7EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     TIM12EN       LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     TIM13EN       LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     TIM14EN       LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     WWDGEN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     SPI2EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     SPI3EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     USART2EN      LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     USART3EN      LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     UART4EN       LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     UART5EN       LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     I2C1EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     I2C2EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     I2C3EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     FMPI2C1EN     LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     CAN1EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     CAN2EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     CAN3EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     CECEN         LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     PWREN         LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     DACEN         LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     UART7EN       LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     UART8EN       LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     RTCAPBEN      LL_APB1_GRP1_DisableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB1ENR, Periphs);\n}\n\n/**\n  * @brief  Force APB1 peripherals reset.\n  * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     TIM4RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     TIM5RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     TIM12RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     TIM13RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     TIM14RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     SPI3RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     SPDIFRXRST     LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     USART2RST      LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     USART3RST      LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     UART4RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     UART5RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     FMPI2C1RST     LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     CAN1RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     CAN2RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     CAN3RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     CECRST         LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     PWRRST         LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     DACRST         LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     UART7RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     UART8RST       LL_APB1_GRP1_ForceReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)\n{\n  SET_BIT(RCC->APB1RSTR, Periphs);\n}\n\n/**\n  * @brief  Release APB1 peripherals reset.\n  * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     TIM4RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     TIM5RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     TIM12RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     TIM13RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     TIM14RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     SPI3RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     SPDIFRXRST     LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     USART2RST      LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     USART3RST      LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     UART4RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     UART5RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     FMPI2C1RST     LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     CAN1RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     CAN2RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     CAN3RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     CECRST         LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     PWRRST         LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     DACRST         LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     UART7RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     UART8RST       LL_APB1_GRP1_ReleaseReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB1RSTR, Periphs);\n}\n\n/**\n  * @brief  Enable APB1 peripheral clocks in low-power mode\n  * @rmtoll APB1LPENR     TIM2LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     TIM3LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     TIM4LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     TIM5LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     TIM6LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     TIM7LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     TIM12LPEN       LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     TIM13LPEN       LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     TIM14LPEN       LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     LPTIM1LPEN      LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     WWDGLPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     SPI2LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     SPI3LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     SPDIFRXLPEN     LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     USART2LPEN      LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     USART3LPEN      LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     UART4LPEN       LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     UART5LPEN       LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     I2C1LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     I2C2LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     I2C3LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     FMPI2C1LPEN     LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     CAN1LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     CAN2LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     CAN3LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     CECLPEN         LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     PWRLPEN         LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     DACLPEN         LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     UART7LPEN       LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     UART8LPEN       LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     RTCAPBLPEN      LL_APB1_GRP1_EnableClockLowPower\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->APB1LPENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Disable APB1 peripheral clocks in low-power mode\n  * @rmtoll APB1LPENR     TIM2LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     TIM3LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     TIM4LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     TIM5LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     TIM6LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     TIM7LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     TIM12LPEN       LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     TIM13LPEN       LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     TIM14LPEN       LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     LPTIM1LPEN      LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     WWDGLPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     SPI2LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     SPI3LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     SPDIFRXLPEN     LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     USART2LPEN      LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     USART3LPEN      LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     UART4LPEN       LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     UART5LPEN       LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     I2C1LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     I2C2LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     I2C3LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     FMPI2C1LPEN     LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     CAN1LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     CAN2LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     CAN3LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     CECLPEN         LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     PWRLPEN         LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     DACLPEN         LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     UART7LPEN       LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     UART8LPEN       LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     RTCAPBLPEN      LL_APB1_GRP1_DisableClockLowPower\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB1LPENR, Periphs);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup BUS_LL_EF_APB2 APB2\n  * @{\n  */\n\n/**\n  * @brief  Enable APB2 peripherals clock.\n  * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     TIM8EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     USART1EN      LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     USART6EN      LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     UART9EN       LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     UART10EN      LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     ADC1EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     ADC2EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     ADC3EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     SDIOEN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     SPI1EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     SPI4EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     EXTITEN       LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     TIM9EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     TIM10EN       LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     TIM11EN       LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     SPI5EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     SPI6EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     SAI1EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     SAI2EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     LTDCEN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     DSIEN         LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     DFSDM2EN      LL_APB2_GRP1_EnableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)\n\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->APB2ENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->APB2ENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Check if APB2 peripheral clock is enabled or not\n  * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     TIM8EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     USART1EN      LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     USART6EN      LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     UART9EN       LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     UART10EN      LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     ADC1EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     ADC2EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     ADC3EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     SDIOEN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     SPI1EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     SPI4EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     EXTITEN       LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     TIM9EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     TIM10EN       LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     TIM11EN       LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     SPI5EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     SPI6EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     SAI1EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     SAI2EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     LTDCEN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     DSIEN         LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     DFSDM2EN      LL_APB2_GRP1_IsEnabledClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval State of Periphs (1 or 0).\n*/\n__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)\n{\n  return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);\n}\n\n/**\n  * @brief  Disable APB2 peripherals clock.\n  * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     TIM8EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     USART1EN      LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     USART6EN      LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     UART9EN       LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     UART10EN      LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     ADC1EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     ADC2EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     ADC3EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     SDIOEN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     SPI1EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     SPI4EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     EXTITEN       LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     TIM9EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     TIM10EN       LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     TIM11EN       LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     SPI5EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     SPI6EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     SAI1EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     SAI2EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     LTDCEN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     DSIEN         LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     DFSDM2EN      LL_APB2_GRP1_DisableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB2ENR, Periphs);\n}\n\n/**\n  * @brief  Force APB2 peripherals reset.\n  * @rmtoll APB2RSTR     TIM1RST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     TIM8RST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     USART1RST      LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     USART6RST      LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     UART9RST       LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     UART10RST      LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     ADCRST         LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     SDIORST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     SPI1RST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     SPI4RST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     SYSCFGRST      LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     TIM9RST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     TIM10RST       LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     TIM11RST       LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     SPI5RST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     SPI6RST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     SAI1RST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     SAI2RST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     LTDCRST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     DSIRST         LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     DFSDM1RST      LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     DFSDM2RST      LL_APB2_GRP1_ForceReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)\n{\n  SET_BIT(RCC->APB2RSTR, Periphs);\n}\n\n/**\n  * @brief  Release APB2 peripherals reset.\n  * @rmtoll APB2RSTR     TIM1RST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     TIM8RST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     USART1RST      LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     USART6RST      LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     UART9RST       LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     UART10RST      LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     ADCRST         LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     SDIORST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     SPI1RST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     SPI4RST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     SYSCFGRST      LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     TIM9RST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     TIM10RST       LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     TIM11RST       LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     SPI5RST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     SPI6RST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     SAI1RST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     SAI2RST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     LTDCRST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     DSIRST         LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     DFSDM1RST      LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     DFSDM2RST      LL_APB2_GRP1_ReleaseReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB2RSTR, Periphs);\n}\n\n/**\n  * @brief  Enable APB2 peripheral clocks in low-power mode\n  * @rmtoll APB2LPENR     TIM1LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     TIM8LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     USART1LPEN      LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     USART6LPEN      LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     UART9LPEN       LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     UART10LPEN      LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     ADC1LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     ADC2LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     ADC3LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     SDIOLPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     SPI1LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     SPI4LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     SYSCFGLPEN      LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     EXTITLPEN       LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     TIM9LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     TIM10LPEN       LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     TIM11LPEN       LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     SPI5LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     SPI6LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     SAI1LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     SAI2LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     LTDCLPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     DFSDM1LPEN      LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     DFSDM2LPEN      LL_APB2_GRP1_EnableClockLowPower\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->APB2LPENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Disable APB2 peripheral clocks in low-power mode\n  * @rmtoll APB2LPENR     TIM1LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     TIM8LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     USART1LPEN      LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     USART6LPEN      LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     UART9LPEN       LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     UART10LPEN      LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     ADC1LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     ADC2LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     ADC3LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     SDIOLPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     SPI1LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     SPI4LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     SYSCFGLPEN      LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     EXTITLPEN       LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     TIM9LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     TIM10LPEN       LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     TIM11LPEN       LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     SPI5LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     SPI6LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     SAI1LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     SAI2LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     LTDCLPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     DFSDM1LPEN      LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     DFSDM2LPEN      LL_APB2_GRP1_DisableClockLowPower\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB2LPENR, Periphs);\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined(RCC) */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_LL_BUS_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_ll_cortex.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_cortex.h\n  * @author  MCD Application Team\n  * @version V1.8.2\n  * @date    08-November-2023\n  * @brief   Header file of CORTEX LL module.\n  @verbatim\n  ==============================================================================\n                     ##### How to use this driver #####\n  ==============================================================================\n    [..]\n    The LL CORTEX driver contains a set of generic APIs that can be\n    used by user:\n      (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick\n          functions\n      (+) Low power mode configuration (SCB register of Cortex-MCU)\n      (+) MPU API to configure and enable regions\n          (MPU services provided only on some devices)\n      (+) API to access to MCU info (CPUID register)\n      (+) API to enable fault handler (SHCSR accesses)\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_LL_CORTEX_H\n#define __STM32F4xx_LL_CORTEX_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n/** @defgroup CORTEX_LL CORTEX\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n\n/* Private constants ---------------------------------------------------------*/\n\n/* Private macros ------------------------------------------------------------*/\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants\n  * @{\n  */\n\n/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source\n  * @{\n  */\n#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/\n#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type\n  * @{\n  */\n#define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */\n#define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */\n#define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */\n/**\n  * @}\n  */\n\n#if __MPU_PRESENT\n\n/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control\n  * @{\n  */\n#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */\n#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */\n#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */\n#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_REGION MPU Region Number\n  * @{\n  */\n#define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */\n#define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */\n#define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */\n#define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */\n#define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */\n#define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */\n#define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */\n#define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size\n  * @{\n  */\n#define LL_MPU_REGION_SIZE_32B             (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_64B             (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_128B            (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges\n  * @{\n  */\n#define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/\n#define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/\n#define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */\n#define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */\n#define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/\n#define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level\n  * @{\n  */\n#define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */\n#define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */\n#define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */\n#define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access\n  * @{\n  */\n#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */\n#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access\n  * @{\n  */\n#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */\n#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access\n  * @{\n  */\n#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */\n#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access\n  * @{\n  */\n#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */\n#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */\n/**\n  * @}\n  */\n#endif /* __MPU_PRESENT */\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions\n  * @{\n  */\n\n/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK\n  * @{\n  */\n\n/**\n  * @brief  This function checks if the Systick counter flag is active or not.\n  * @note   It can be used in timeout function on application side.\n  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)\n{\n  return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));\n}\n\n/**\n  * @brief  Configures the SysTick clock source\n  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8\n  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)\n{\n  if (Source == LL_SYSTICK_CLKSOURCE_HCLK)\n  {\n    SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);\n  }\n  else\n  {\n    CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);\n  }\n}\n\n/**\n  * @brief  Get the SysTick clock source\n  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8\n  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK\n  */\n__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)\n{\n  return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);\n}\n\n/**\n  * @brief  Enable SysTick exception request\n  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSTICK_EnableIT(void)\n{\n  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);\n}\n\n/**\n  * @brief  Disable SysTick exception request\n  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSTICK_DisableIT(void)\n{\n  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);\n}\n\n/**\n  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.\n  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)\n{\n  return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE\n  * @{\n  */\n\n/**\n  * @brief  Processor uses sleep as its low power mode\n  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPM_EnableSleep(void)\n{\n  /* Clear SLEEPDEEP bit of Cortex System Control Register */\n  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\n}\n\n/**\n  * @brief  Processor uses deep sleep as its low power mode\n  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)\n{\n  /* Set SLEEPDEEP bit of Cortex System Control Register */\n  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\n}\n\n/**\n  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.\n  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an\n  *         empty main application.\n  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)\n{\n  /* Set SLEEPONEXIT bit of Cortex System Control Register */\n  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\n}\n\n/**\n  * @brief  Do not sleep when returning to Thread mode.\n  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)\n{\n  /* Clear SLEEPONEXIT bit of Cortex System Control Register */\n  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\n}\n\n/**\n  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the\n  *         processor.\n  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)\n{\n  /* Set SEVEONPEND bit of Cortex System Control Register */\n  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\n}\n\n/**\n  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are\n  *         excluded\n  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)\n{\n  /* Clear SEVEONPEND bit of Cortex System Control Register */\n  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\n}\n\n/**\n  * @brief  Clear pending events.\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPM_ClearEvent(void)\n{\n  __SEV();\n  __WFE();\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EF_HANDLER HANDLER\n  * @{\n  */\n\n/**\n  * @brief  Enable a fault in System handler control register (SHCSR)\n  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault\n  * @param  Fault This parameter can be a combination of the following values:\n  *         @arg @ref LL_HANDLER_FAULT_USG\n  *         @arg @ref LL_HANDLER_FAULT_BUS\n  *         @arg @ref LL_HANDLER_FAULT_MEM\n  * @retval None\n  */\n__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)\n{\n  /* Enable the system handler fault */\n  SET_BIT(SCB->SHCSR, Fault);\n}\n\n/**\n  * @brief  Disable a fault in System handler control register (SHCSR)\n  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault\n  * @param  Fault This parameter can be a combination of the following values:\n  *         @arg @ref LL_HANDLER_FAULT_USG\n  *         @arg @ref LL_HANDLER_FAULT_BUS\n  *         @arg @ref LL_HANDLER_FAULT_MEM\n  * @retval None\n  */\n__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)\n{\n  /* Disable the system handler fault */\n  CLEAR_BIT(SCB->SHCSR, Fault);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO\n  * @{\n  */\n\n/**\n  * @brief  Get Implementer code\n  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer\n  * @retval Value should be equal to 0x41 for ARM\n  */\n__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)\n{\n  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);\n}\n\n/**\n  * @brief  Get Variant number (The r value in the rnpn product revision identifier)\n  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant\n  * @retval Value between 0 and 255 (0x0: revision 0)\n  */\n__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)\n{\n  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);\n}\n\n/**\n  * @brief  Get Constant number\n  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant\n  * @retval Value should be equal to 0xF for Cortex-M4 devices\n  */\n__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)\n{\n  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);\n}\n\n/**\n  * @brief  Get Part number\n  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo\n  * @retval Value should be equal to 0xC24 for Cortex-M4\n  */\n__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)\n{\n  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);\n}\n\n/**\n  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)\n  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision\n  * @retval Value between 0 and 255 (0x1: patch 1)\n  */\n__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)\n{\n  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);\n}\n\n/**\n  * @}\n  */\n\n#if __MPU_PRESENT\n/** @defgroup CORTEX_LL_EF_MPU MPU\n  * @{\n  */\n\n/**\n  * @brief  Enable MPU with input Options\n  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable\n  * @param  Options This parameter can be one of the following values:\n  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE\n  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI\n  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT\n  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF\n  * @retval None\n  */\n__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)\n{\n  /* Enable MPU. */\n  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));\n\n  /* Ensure MPU settings take effect. */\n  __DSB();\n\n  /* Sequence instruction fetches using updated settings. */\n  __ISB();\n}\n\n/**\n  * @brief  Disable MPU\n  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_MPU_Disable(void)\n{\n  /* Make sure outstanding transfers are done. */\n  __DMB();\n\n  /* Disable MPU. */\n  WRITE_REG(MPU->CTRL, 0U);\n}\n\n/**\n  * @brief  Check if MPU is enabled or not\n  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)\n{\n  return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));\n}\n\n/**\n  * @brief  Enable MPU Region\n  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion\n  * @param  Region This parameter can be one of the following values:\n  *         @arg @ref LL_MPU_REGION_NUMBER0\n  *         @arg @ref LL_MPU_REGION_NUMBER1\n  *         @arg @ref LL_MPU_REGION_NUMBER2\n  *         @arg @ref LL_MPU_REGION_NUMBER3\n  *         @arg @ref LL_MPU_REGION_NUMBER4\n  *         @arg @ref LL_MPU_REGION_NUMBER5\n  *         @arg @ref LL_MPU_REGION_NUMBER6\n  *         @arg @ref LL_MPU_REGION_NUMBER7\n  * @retval None\n  */\n__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)\n{\n  /* Set Region number. */\n  WRITE_REG(MPU->RNR, Region);\n\n  /* Enable MPU Region. */\n  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);\n}\n\n/**\n  * @brief  Configure and enable Region\n  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\\n\n  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\\n\n  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\\n\n  *         MPU_RASR     XN            LL_MPU_ConfigRegion\\n\n  *         MPU_RASR     AP            LL_MPU_ConfigRegion\\n\n  *         MPU_RASR     S             LL_MPU_ConfigRegion\\n\n  *         MPU_RASR     C             LL_MPU_ConfigRegion\\n\n  *         MPU_RASR     B             LL_MPU_ConfigRegion\\n\n  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion\n  * @param  Region This parameter can be one of the following values:\n  *         @arg @ref LL_MPU_REGION_NUMBER0\n  *         @arg @ref LL_MPU_REGION_NUMBER1\n  *         @arg @ref LL_MPU_REGION_NUMBER2\n  *         @arg @ref LL_MPU_REGION_NUMBER3\n  *         @arg @ref LL_MPU_REGION_NUMBER4\n  *         @arg @ref LL_MPU_REGION_NUMBER5\n  *         @arg @ref LL_MPU_REGION_NUMBER6\n  *         @arg @ref LL_MPU_REGION_NUMBER7\n  * @param  Address Value of Region Base Address\n  * @param  SubRegionDisable Sub-Region disable value between Min_Data = 0x00 and Max_Data = 0xFF\n  * @param  Attributes This parameter can be a combination of the following values:\n  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B\n  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB\n  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB\n  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB\n  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB\n  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB\n  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS\n  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO\n  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4\n  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE\n  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE\n  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE\n  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE\n  * @retval None\n  */\n__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)\n{\n  /* Set Region number. */\n  WRITE_REG(MPU->RNR, Region);\n\n  /* Set Base Address. */\n  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));\n\n  /* Configure MPU. */\n  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));\n}\n\n/**\n  * @brief  Disable Region\n  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\\n\n  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion\n  * @param  Region This parameter can be one of the following values:\n  *         @arg @ref LL_MPU_REGION_NUMBER0\n  *         @arg @ref LL_MPU_REGION_NUMBER1\n  *         @arg @ref LL_MPU_REGION_NUMBER2\n  *         @arg @ref LL_MPU_REGION_NUMBER3\n  *         @arg @ref LL_MPU_REGION_NUMBER4\n  *         @arg @ref LL_MPU_REGION_NUMBER5\n  *         @arg @ref LL_MPU_REGION_NUMBER6\n  *         @arg @ref LL_MPU_REGION_NUMBER7\n  * @retval None\n  */\n__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)\n{\n  /* Set Region number. */\n  WRITE_REG(MPU->RNR, Region);\n\n  /* Disable MPU Region. */\n  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);\n}\n\n/**\n  * @brief  Get MPU Control Register.\n  * @note   This function is an extension to the LL_CORTEX library.\n  * @retval Values of MPU Enable, Hard Fault NMI Enable, and Background Region Enable.\n  */\n__STATIC_INLINE uint32_t LL_MPU_GetCtrl(void)\n{\n  return (uint32_t)(READ_REG(MPU->CTRL));\n}\n\n/**\n  * @brief  Set MPU Control Register with Options.\n  * @note   This function is an extension to the LL_CORTEX library.\n  * @retval None\n  */\n__STATIC_INLINE void LL_MPU_SetCtrl(uint32_t Options)\n{\n  /* Configure MPU Control Register. */\n  WRITE_REG(MPU->CTRL, ((MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_ENABLE_Msk) & Options));\n\n  /* Ensure MPU settings take effect. */\n  __DSB();\n\n  /* Sequence instruction fetches using updated settings. */\n  __ISB();\n}\n\n/**\n  * @brief  Get number of Regions the MPU supports.\n  * @note   This function is an extension to the LL_CORTEX library.\n  * @retval Value should be equal to 0x8 for Cortex-M4 devices; 0x0 if no MPU implemented.\n  */\n__STATIC_INLINE uint32_t LL_MPU_GetNumRegions(void)\n{\n  return (uint32_t)(READ_BIT(MPU->TYPE, MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);\n}\n\n/**\n  * @brief  Check if the MPU supports separate instruction and data address maps.\n  * @note   This function is an extension to the LL_CORTEX library.\n  * @retval Value should be equal to 0x0 for Cortex-M4 devices; ARMv7-M only supports a unified MPU.\n  */\n__STATIC_INLINE uint32_t LL_MPU_GetSeparate(void)\n{\n  return (uint32_t)(READ_BIT(MPU->TYPE, MPU_TYPE_SEPARATE_Msk) >> MPU_TYPE_SEPARATE_Pos);\n}\n\n/**\n  * @brief  Get MPU Region's Region Base Address.\n  * @rmtoll MPU_RNR      REGION        LL_MPU_GetRegionBaseAddress\n  * @param  Region This parameter can be one of the following values:\n  *         @arg @ref LL_MPU_REGION_NUMBER0\n  *         @arg @ref LL_MPU_REGION_NUMBER1\n  *         @arg @ref LL_MPU_REGION_NUMBER2\n  *         @arg @ref LL_MPU_REGION_NUMBER3\n  *         @arg @ref LL_MPU_REGION_NUMBER4\n  *         @arg @ref LL_MPU_REGION_NUMBER5\n  *         @arg @ref LL_MPU_REGION_NUMBER6\n  *         @arg @ref LL_MPU_REGION_NUMBER7\n  * @note   This function is an extension to the LL_CORTEX library.\n  * @retval Value of the Region Base Address Register for the supplied Region parameter.\n  */\n__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region)\n{\n  /* Set Region number. */\n  WRITE_REG(MPU->RNR, Region);\n\n  return (uint32_t)(READ_REG(MPU->RBAR & MPU_RBAR_ADDR_Msk));\n}\n\n/**\n  * @brief  Get MPU Region's Region Attribute and Size Register.\n  * @rmtoll MPU_RNR      REGION        LL_MPU_GetRegionAttrSize\n  * @param  Region This parameter can be one of the following values:\n  *         @arg @ref LL_MPU_REGION_NUMBER0\n  *         @arg @ref LL_MPU_REGION_NUMBER1\n  *         @arg @ref LL_MPU_REGION_NUMBER2\n  *         @arg @ref LL_MPU_REGION_NUMBER3\n  *         @arg @ref LL_MPU_REGION_NUMBER4\n  *         @arg @ref LL_MPU_REGION_NUMBER5\n  *         @arg @ref LL_MPU_REGION_NUMBER6\n  *         @arg @ref LL_MPU_REGION_NUMBER7\n  * @note   This function is an extension to the LL_CORTEX library.\n  * @retval Value of the Region Attribute and Size Register for the supplied Region parameter.\n  */\n__STATIC_INLINE uint32_t LL_MPU_GetRegionAttrSize(uint32_t Region)\n{\n  /* Set Region number. */\n  WRITE_REG(MPU->RNR, Region);\n\n  return (uint32_t)(READ_REG(MPU->RASR));\n}\n\n/**\n  * @}\n  */\n\n#endif /* __MPU_PRESENT */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_LL_CORTEX_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_ll_gpio.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_gpio.h\n  * @author  MCD Application Team\n  * @version V1.7.1\n  * @date    14-April-2017\n  * @brief   Header file of GPIO LL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_LL_GPIO_H\n#define __STM32F4xx_LL_GPIO_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)\n\n/** @defgroup GPIO_LL GPIO\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n#endif /*USE_FULL_LL_DRIVER*/\n\n/* Exported types ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures\n  * @{\n  */\n\n/**\n  * @brief LL GPIO Init Structure definition\n  */\ntypedef struct\n{\n  uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.\n                              This parameter can be any value of @ref GPIO_LL_EC_PIN */\n\n  uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.\n                              This parameter can be a value of @ref GPIO_LL_EC_MODE.\n\n                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/\n\n  uint32_t Speed;        /*!< Specifies the speed for the selected pins.\n                              This parameter can be a value of @ref GPIO_LL_EC_SPEED.\n\n                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/\n\n  uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.\n                              This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.\n\n                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/\n\n  uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.\n                              This parameter can be a value of @ref GPIO_LL_EC_PULL.\n\n                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/\n\n  uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.\n                              This parameter can be a value of @ref GPIO_LL_EC_AF.\n\n                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/\n} LL_GPIO_InitTypeDef;\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants\n  * @{\n  */\n\n/** @defgroup GPIO_LL_EC_PIN PIN\n  * @{\n  */\n#define LL_GPIO_PIN_0                      GPIO_BSRR_BS_0 /*!< Select pin 0 */\n#define LL_GPIO_PIN_1                      GPIO_BSRR_BS_1 /*!< Select pin 1 */\n#define LL_GPIO_PIN_2                      GPIO_BSRR_BS_2 /*!< Select pin 2 */\n#define LL_GPIO_PIN_3                      GPIO_BSRR_BS_3 /*!< Select pin 3 */\n#define LL_GPIO_PIN_4                      GPIO_BSRR_BS_4 /*!< Select pin 4 */\n#define LL_GPIO_PIN_5                      GPIO_BSRR_BS_5 /*!< Select pin 5 */\n#define LL_GPIO_PIN_6                      GPIO_BSRR_BS_6 /*!< Select pin 6 */\n#define LL_GPIO_PIN_7                      GPIO_BSRR_BS_7 /*!< Select pin 7 */\n#define LL_GPIO_PIN_8                      GPIO_BSRR_BS_8 /*!< Select pin 8 */\n#define LL_GPIO_PIN_9                      GPIO_BSRR_BS_9 /*!< Select pin 9 */\n#define LL_GPIO_PIN_10                     GPIO_BSRR_BS_10 /*!< Select pin 10 */\n#define LL_GPIO_PIN_11                     GPIO_BSRR_BS_11 /*!< Select pin 11 */\n#define LL_GPIO_PIN_12                     GPIO_BSRR_BS_12 /*!< Select pin 12 */\n#define LL_GPIO_PIN_13                     GPIO_BSRR_BS_13 /*!< Select pin 13 */\n#define LL_GPIO_PIN_14                     GPIO_BSRR_BS_14 /*!< Select pin 14 */\n#define LL_GPIO_PIN_15                     GPIO_BSRR_BS_15 /*!< Select pin 15 */\n#define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1  | GPIO_BSRR_BS_2  | \\\n                                           GPIO_BSRR_BS_3  | GPIO_BSRR_BS_4  | GPIO_BSRR_BS_5  | \\\n                                           GPIO_BSRR_BS_6  | GPIO_BSRR_BS_7  | GPIO_BSRR_BS_8  | \\\n                                           GPIO_BSRR_BS_9  | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \\\n                                           GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \\\n                                           GPIO_BSRR_BS_15) /*!< Select all pins */\n/**\n  * @}\n  */\n\n/** @defgroup GPIO_LL_EC_MODE Mode\n  * @{\n  */\n#define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */\n#define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODER0_0  /*!< Select output mode */\n#define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODER0_1  /*!< Select alternate function mode */\n#define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODER0    /*!< Select analog mode */\n/**\n  * @}\n  */\n\n/** @defgroup GPIO_LL_EC_OUTPUT Output Type\n  * @{\n  */\n#define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */\n#define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */\n/**\n  * @}\n  */\n\n/** @defgroup GPIO_LL_EC_SPEED Output Speed\n  * @{\n  */\n#define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */\n#define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */\n#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed   */\n#define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDER_OSPEEDR0   /*!< Select I/O high output speed   */\n/**\n  * @}\n  */\n\n/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down\n  * @{\n  */\n#define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */\n#define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */\n#define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */\n/**\n  * @}\n  */\n\n/** @defgroup GPIO_LL_EC_AF Alternate Function\n  * @{\n  */\n#define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */\n#define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */\n#define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */\n#define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */\n#define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */\n#define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */\n#define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */\n#define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */\n#define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */\n#define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */\n#define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */\n#define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */\n#define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */\n#define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */\n#define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */\n#define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros\n  * @{\n  */\n\n/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros\n  * @{\n  */\n\n/**\n  * @brief  Write a value in GPIO register\n  * @param  __INSTANCE__ GPIO Instance\n  * @param  __REG__ Register to be written\n  * @param  __VALUE__ Value to be written in the register\n  * @retval None\n  */\n#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))\n\n/**\n  * @brief  Read a value in GPIO register\n  * @param  __INSTANCE__ GPIO Instance\n  * @param  __REG__ Register to be read\n  * @retval Register value\n  */\n#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions\n  * @{\n  */\n\n/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration\n  * @{\n  */\n\n/**\n  * @brief  Configure gpio mode for a dedicated pin on dedicated port.\n  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @param  Mode This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_MODE_INPUT\n  *         @arg @ref LL_GPIO_MODE_OUTPUT\n  *         @arg @ref LL_GPIO_MODE_ALTERNATE\n  *         @arg @ref LL_GPIO_MODE_ANALOG\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)\n{\n  MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));\n}\n\n/**\n  * @brief  Return gpio mode for a dedicated pin on dedicated port.\n  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_GPIO_MODE_INPUT\n  *         @arg @ref LL_GPIO_MODE_OUTPUT\n  *         @arg @ref LL_GPIO_MODE_ALTERNATE\n  *         @arg @ref LL_GPIO_MODE_ANALOG\n  */\n__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)\n{\n  return (uint32_t)(READ_BIT(GPIOx->MODER,\n                             (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));\n}\n\n/**\n  * @brief  Configure gpio output type for several pins on dedicated port.\n  * @note   Output type as to be set when gpio pin is in output or\n  *         alternate modes. Possible type are Push-pull or Open-drain.\n  * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @param  OutputType This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL\n  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType)\n{\n  MODIFY_REG(GPIOx->OTYPER, (GPIO_OTYPER_OT_0 << POSITION_VAL(Pin)), (OutputType << POSITION_VAL(Pin)));\n}\n\n/**\n  * @brief  Return gpio output type for several pins on dedicated port.\n  * @note   Output type as to be set when gpio pin is in output or\n  *         alternate modes. Possible type are Push-pull or Open-drain.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL\n  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN\n  */\n__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)\n{\n  return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));\n}\n\n/**\n  * @brief  Configure gpio speed for a dedicated pin on dedicated port.\n  * @note   I/O speed can be Low, Medium, Fast or High speed.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @note   Refer to datasheet for frequency specifications and the power\n  *         supply and load conditions for each speed.\n  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @param  Speed This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW\n  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM\n  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH\n  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)\n{\n  MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),\n             (Speed << (POSITION_VAL(Pin) * 2U)));\n}\n\n/**\n  * @brief  Return gpio speed for a dedicated pin on dedicated port.\n  * @note   I/O speed can be Low, Medium, Fast or High speed.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @note   Refer to datasheet for frequency specifications and the power\n  *         supply and load conditions for each speed.\n  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW\n  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM\n  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH\n  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH\n  */\n__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)\n{\n  return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,\n                             (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));\n}\n\n/**\n  * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @param  Pull This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PULL_NO\n  *         @arg @ref LL_GPIO_PULL_UP\n  *         @arg @ref LL_GPIO_PULL_DOWN\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)\n{\n  MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));\n}\n\n/**\n  * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_GPIO_PULL_NO\n  *         @arg @ref LL_GPIO_PULL_UP\n  *         @arg @ref LL_GPIO_PULL_DOWN\n  */\n__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)\n{\n  return (uint32_t)(READ_BIT(GPIOx->PUPDR,\n                             (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));\n}\n\n/**\n  * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.\n  * @note   Possible values are from AF0 to AF15 depending on target.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  * @param  Alternate This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_AF_0\n  *         @arg @ref LL_GPIO_AF_1\n  *         @arg @ref LL_GPIO_AF_2\n  *         @arg @ref LL_GPIO_AF_3\n  *         @arg @ref LL_GPIO_AF_4\n  *         @arg @ref LL_GPIO_AF_5\n  *         @arg @ref LL_GPIO_AF_6\n  *         @arg @ref LL_GPIO_AF_7\n  *         @arg @ref LL_GPIO_AF_8\n  *         @arg @ref LL_GPIO_AF_9\n  *         @arg @ref LL_GPIO_AF_10\n  *         @arg @ref LL_GPIO_AF_11\n  *         @arg @ref LL_GPIO_AF_12\n  *         @arg @ref LL_GPIO_AF_13\n  *         @arg @ref LL_GPIO_AF_14\n  *         @arg @ref LL_GPIO_AF_15\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)\n{\n  MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),\n             (Alternate << (POSITION_VAL(Pin) * 4U)));\n}\n\n/**\n  * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.\n  * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_GPIO_AF_0\n  *         @arg @ref LL_GPIO_AF_1\n  *         @arg @ref LL_GPIO_AF_2\n  *         @arg @ref LL_GPIO_AF_3\n  *         @arg @ref LL_GPIO_AF_4\n  *         @arg @ref LL_GPIO_AF_5\n  *         @arg @ref LL_GPIO_AF_6\n  *         @arg @ref LL_GPIO_AF_7\n  *         @arg @ref LL_GPIO_AF_8\n  *         @arg @ref LL_GPIO_AF_9\n  *         @arg @ref LL_GPIO_AF_10\n  *         @arg @ref LL_GPIO_AF_11\n  *         @arg @ref LL_GPIO_AF_12\n  *         @arg @ref LL_GPIO_AF_13\n  *         @arg @ref LL_GPIO_AF_14\n  *         @arg @ref LL_GPIO_AF_15\n  */\n__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)\n{\n  return (uint32_t)(READ_BIT(GPIOx->AFR[0],\n                             (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));\n}\n\n/**\n  * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.\n  * @note   Possible values are from AF0 to AF15 depending on target.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @param  Alternate This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_AF_0\n  *         @arg @ref LL_GPIO_AF_1\n  *         @arg @ref LL_GPIO_AF_2\n  *         @arg @ref LL_GPIO_AF_3\n  *         @arg @ref LL_GPIO_AF_4\n  *         @arg @ref LL_GPIO_AF_5\n  *         @arg @ref LL_GPIO_AF_6\n  *         @arg @ref LL_GPIO_AF_7\n  *         @arg @ref LL_GPIO_AF_8\n  *         @arg @ref LL_GPIO_AF_9\n  *         @arg @ref LL_GPIO_AF_10\n  *         @arg @ref LL_GPIO_AF_11\n  *         @arg @ref LL_GPIO_AF_12\n  *         @arg @ref LL_GPIO_AF_13\n  *         @arg @ref LL_GPIO_AF_14\n  *         @arg @ref LL_GPIO_AF_15\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)\n{\n  MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),\n             (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));\n}\n\n/**\n  * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.\n  * @note   Possible values are from AF0 to AF15 depending on target.\n  * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_GPIO_AF_0\n  *         @arg @ref LL_GPIO_AF_1\n  *         @arg @ref LL_GPIO_AF_2\n  *         @arg @ref LL_GPIO_AF_3\n  *         @arg @ref LL_GPIO_AF_4\n  *         @arg @ref LL_GPIO_AF_5\n  *         @arg @ref LL_GPIO_AF_6\n  *         @arg @ref LL_GPIO_AF_7\n  *         @arg @ref LL_GPIO_AF_8\n  *         @arg @ref LL_GPIO_AF_9\n  *         @arg @ref LL_GPIO_AF_10\n  *         @arg @ref LL_GPIO_AF_11\n  *         @arg @ref LL_GPIO_AF_12\n  *         @arg @ref LL_GPIO_AF_13\n  *         @arg @ref LL_GPIO_AF_14\n  *         @arg @ref LL_GPIO_AF_15\n  */\n__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)\n{\n  return (uint32_t)(READ_BIT(GPIOx->AFR[1],\n                             (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));\n}\n\n\n/**\n  * @brief  Lock configuration of several pins for a dedicated port.\n  * @note   When the lock sequence has been applied on a port bit, the\n  *         value of this port bit can no longer be modified until the\n  *         next reset.\n  * @note   Each lock bit freezes a specific configuration register\n  *         (control and alternate function registers).\n  * @rmtoll LCKR         LCKK          LL_GPIO_LockPin\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  __IO uint32_t temp;\n  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);\n  WRITE_REG(GPIOx->LCKR, PinMask);\n  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);\n  temp = READ_REG(GPIOx->LCKR);\n  (void) temp;\n}\n\n/**\n  * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.\n  * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));\n}\n\n/**\n  * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.\n  * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked\n  * @param  GPIOx GPIO Port\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)\n{\n  return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup GPIO_LL_EF_Data_Access Data Access\n  * @{\n  */\n\n/**\n  * @brief  Return full input data register value for a dedicated port.\n  * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort\n  * @param  GPIOx GPIO Port\n  * @retval Input data register value of port\n  */\n__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)\n{\n  return (uint32_t)(READ_REG(GPIOx->IDR));\n}\n\n/**\n  * @brief  Return if input data level for several pins of dedicated port is high or low.\n  * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));\n}\n\n/**\n  * @brief  Write output data register for the port.\n  * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort\n  * @param  GPIOx GPIO Port\n  * @param  PortValue Level value for each pin of the port\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)\n{\n  WRITE_REG(GPIOx->ODR, PortValue);\n}\n\n/**\n  * @brief  Return full output data register value for a dedicated port.\n  * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort\n  * @param  GPIOx GPIO Port\n  * @retval Output data register value of port\n  */\n__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)\n{\n  return (uint32_t)(READ_REG(GPIOx->ODR));\n}\n\n/**\n  * @brief  Return if input data level for several pins of dedicated port is high or low.\n  * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));\n}\n\n/**\n  * @brief  Set several pins to high level on dedicated gpio port.\n  * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  WRITE_REG(GPIOx->BSRR, PinMask);\n}\n\n/**\n  * @brief  Set several pins to low level on dedicated gpio port.\n  * @rmtoll BSRR         BRy           LL_GPIO_ResetOutputPin\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  WRITE_REG(GPIOx->BSRR, (PinMask << 16));\n}\n\n/**\n  * @brief  Toggle data value for several pin of dedicated port.\n  * @rmtoll ODR          ODy           LL_GPIO_TogglePin\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);\n}\n\n/**\n  * @brief  Call proper function to configure gpio alternate function of a dedicated pin for a dedicated port.\n  * @note   This function is an extension to the LL_GPIO library.\n  */\n__STATIC_INLINE void LL_GPIO_SetAFPin(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)\n{\n  if (Pin >= LL_GPIO_PIN_0 && Pin <= LL_GPIO_PIN_7) {\n    LL_GPIO_SetAFPin_0_7(GPIOx, Pin, Alternate);\n  } else {\n    LL_GPIO_SetAFPin_8_15(GPIOx, Pin, Alternate);\n  }\n}\n\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions\n  * @{\n  */\n\nErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);\nErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);\nvoid        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_LL_GPIO_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_ll_pwr.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_pwr.h\n  * @author  MCD Application Team\n  * @version V1.7.1\n  * @date    14-April-2017\n  * @brief   Header file of PWR LL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_LL_PWR_H\n#define __STM32F4xx_LL_PWR_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined(PWR)\n\n/** @defgroup PWR_LL PWR\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants\n  * @{\n  */\n\n/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines\n  * @brief    Flags defines which can be used with LL_PWR_WriteReg function\n  * @{\n  */\n#define LL_PWR_CR_CSBF                     PWR_CR_CSBF            /*!< Clear standby flag */\n#define LL_PWR_CR_CWUF                     PWR_CR_CWUF            /*!< Clear wakeup flag */\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines\n  * @brief    Flags defines which can be used with LL_PWR_ReadReg function\n  * @{\n  */\n#define LL_PWR_CSR_WUF                     PWR_CSR_WUF            /*!< Wakeup flag */\n#define LL_PWR_CSR_SBF                     PWR_CSR_SBF            /*!< Standby flag */\n#define LL_PWR_CSR_PVDO                    PWR_CSR_PVDO           /*!< Power voltage detector output flag */\n#define LL_PWR_CSR_VOS                     PWR_CSR_VOSRDY            /*!< Voltage scaling select flag */\n#if defined(PWR_CSR_EWUP)\n#define LL_PWR_CSR_EWUP1                   PWR_CSR_EWUP           /*!< Enable WKUP pin */\n#elif defined(PWR_CSR_EWUP1)\n#define LL_PWR_CSR_EWUP1                   PWR_CSR_EWUP1          /*!< Enable WKUP pin 1 */\n#endif /* PWR_CSR_EWUP */\n#if defined(PWR_CSR_EWUP2)\n#define LL_PWR_CSR_EWUP2                   PWR_CSR_EWUP2          /*!< Enable WKUP pin 2 */\n#endif /* PWR_CSR_EWUP2 */\n#if defined(PWR_CSR_EWUP3)\n#define LL_PWR_CSR_EWUP3                   PWR_CSR_EWUP3          /*!< Enable WKUP pin 3 */\n#endif /* PWR_CSR_EWUP3 */\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage\n  * @{\n  */\n#if defined(PWR_CR_VOS_0)\n#define LL_PWR_REGU_VOLTAGE_SCALE3         (PWR_CR_VOS_0)\n#define LL_PWR_REGU_VOLTAGE_SCALE2         (PWR_CR_VOS_1)\n#define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR_VOS_0 | PWR_CR_VOS_1) /* The SCALE1 is not available for STM32F401xx devices */\n#else\n#define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR_VOS)\n#define LL_PWR_REGU_VOLTAGE_SCALE2         0x00000000U\n#endif /* PWR_CR_VOS_0 */\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EC_MODE_PWR Mode Power\n  * @{\n  */\n#define LL_PWR_MODE_STOP_MAINREGU             0x00000000U                    /*!< Enter Stop mode when the CPU enters deepsleep */\n#define LL_PWR_MODE_STOP_LPREGU               (PWR_CR_LPDS)                  /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */\n#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)\n#define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE  (PWR_CR_MRUDS | PWR_CR_FPDS)                 /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */\n#define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE    (PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_FPDS)   /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */\n#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */\n#if defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)\n#define LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP  (PWR_CR_MRLVDS | PWR_CR_FPDS)                 /*!< Enter Stop mode (with main Regulator in Deep Sleep mode) when the CPU enters deepsleep */\n#define LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP    (PWR_CR_LPDS | PWR_CR_LPLVDS | PWR_CR_FPDS)   /*!< Enter Stop mode (with low power Regulator in Deep Sleep mode) when the CPU enters deepsleep */\n#endif /* PWR_CR_MRLVDS && PWR_CR_LPLVDS && PWR_CR_FPDS */\n#define LL_PWR_MODE_STANDBY                   (PWR_CR_PDDS)                  /*!< Enter Standby mode when the CPU enters deepsleep */\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode\n * @{\n */\n#define LL_PWR_REGU_DSMODE_MAIN        0x00000000U           /*!< Voltage Regulator in main mode during deepsleep mode */\n#define LL_PWR_REGU_DSMODE_LOW_POWER   (PWR_CR_LPDS)         /*!< Voltage Regulator in low-power mode during deepsleep mode */\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level\n  * @{\n  */\n#define LL_PWR_PVDLEVEL_0                  (PWR_CR_PLS_LEV0)      /*!< Voltage threshold detected by PVD 2.2 V */\n#define LL_PWR_PVDLEVEL_1                  (PWR_CR_PLS_LEV1)      /*!< Voltage threshold detected by PVD 2.3 V */\n#define LL_PWR_PVDLEVEL_2                  (PWR_CR_PLS_LEV2)      /*!< Voltage threshold detected by PVD 2.4 V */\n#define LL_PWR_PVDLEVEL_3                  (PWR_CR_PLS_LEV3)      /*!< Voltage threshold detected by PVD 2.5 V */\n#define LL_PWR_PVDLEVEL_4                  (PWR_CR_PLS_LEV4)      /*!< Voltage threshold detected by PVD 2.6 V */\n#define LL_PWR_PVDLEVEL_5                  (PWR_CR_PLS_LEV5)      /*!< Voltage threshold detected by PVD 2.7 V */\n#define LL_PWR_PVDLEVEL_6                  (PWR_CR_PLS_LEV6)      /*!< Voltage threshold detected by PVD 2.8 V */\n#define LL_PWR_PVDLEVEL_7                  (PWR_CR_PLS_LEV7)      /*!< Voltage threshold detected by PVD 2.9 V */\n/**\n  * @}\n  */\n/** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins\n  * @{\n  */\n#if defined(PWR_CSR_EWUP)\n#define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP)         /*!< WKUP pin : PA0 */\n#endif /* PWR_CSR_EWUP */\n#if defined(PWR_CSR_EWUP1)\n#define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP1)        /*!< WKUP pin 1 : PA0 */\n#endif /* PWR_CSR_EWUP1 */\n#if defined(PWR_CSR_EWUP2)\n#define LL_PWR_WAKEUP_PIN2                 (PWR_CSR_EWUP2)        /*!< WKUP pin 2 : PC0 or PC13 according to device */\n#endif /* PWR_CSR_EWUP2 */\n#if defined(PWR_CSR_EWUP3)\n#define LL_PWR_WAKEUP_PIN3                 (PWR_CSR_EWUP3)        /*!< WKUP pin 3 : PC1 */\n#endif /* PWR_CSR_EWUP3 */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros\n  * @{\n  */\n\n/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros\n  * @{\n  */\n\n/**\n  * @brief  Write a value in PWR register\n  * @param  __REG__ Register to be written\n  * @param  __VALUE__ Value to be written in the register\n  * @retval None\n  */\n#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))\n\n/**\n  * @brief  Read a value in PWR register\n  * @param  __REG__ Register to be read\n  * @retval Register value\n  */\n#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions\n  * @{\n  */\n\n/** @defgroup PWR_LL_EF_Configuration Configuration\n  * @{\n  */\n#if defined(PWR_CR_FISSR)\n/**\n  * @brief  Enable FLASH interface STOP while system Run is ON\n  * @rmtoll CR    FISSR       LL_PWR_EnableFLASHInterfaceSTOP\n  * @note  This mode is enabled only with STOP low power mode.\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableFLASHInterfaceSTOP(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_FISSR);\n}\n\n/**\n  * @brief  Disable FLASH Interface STOP while system Run is ON\n  * @rmtoll CR    FISSR       LL_PWR_DisableFLASHInterfaceSTOP\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableFLASHInterfaceSTOP(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_FISSR);\n}\n\n/**\n  * @brief  Check if FLASH Interface STOP while system Run feature is enabled\n  * @rmtoll CR    FISSR       LL_PWR_IsEnabledFLASHInterfaceSTOP\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHInterfaceSTOP(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_FISSR) == (PWR_CR_FISSR));\n}\n#endif /* PWR_CR_FISSR */\n\n#if defined(PWR_CR_FMSSR)\n/**\n  * @brief  Enable FLASH Memory STOP while system Run is ON\n  * @rmtoll CR    FMSSR       LL_PWR_EnableFLASHMemorySTOP\n  * @note  This mode is enabled only with STOP low power mode.\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableFLASHMemorySTOP(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_FMSSR);\n}\n\n/**\n  * @brief  Disable FLASH Memory STOP while system Run is ON\n  * @rmtoll CR    FMSSR       LL_PWR_DisableFLASHMemorySTOP\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableFLASHMemorySTOP(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);\n}\n\n/**\n  * @brief  Check if FLASH Memory STOP while system Run feature is enabled\n  * @rmtoll CR    FMSSR       LL_PWR_IsEnabledFLASHMemorySTOP\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_FMSSR) == (PWR_CR_FMSSR));\n}\n#endif /* PWR_CR_FMSSR */\n#if defined(PWR_CR_UDEN)\n/**\n  * @brief  Enable Under Drive Mode\n  * @rmtoll CR    UDEN       LL_PWR_EnableUnderDriveMode\n  * @note  This mode is enabled only with STOP low power mode.\n  *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This\n  *        mode is only available when the main Regulator or the low power Regulator\n  *        is in low voltage mode.\n  * @note  If the Under-drive mode was enabled, it is automatically disabled after\n  *        exiting Stop mode.\n  *        When the voltage Regulator operates in Under-drive mode, an additional\n  *        startup delay is induced when waking up from Stop mode.\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_UDEN);\n}\n\n/**\n  * @brief  Disable Under Drive Mode\n  * @rmtoll CR    UDEN       LL_PWR_DisableUnderDriveMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_UDEN);\n}\n\n/**\n  * @brief  Check if Under Drive Mode is enabled\n  * @rmtoll CR    UDEN       LL_PWR_IsEnabledUnderDriveMode\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_UDEN) == (PWR_CR_UDEN));\n}\n#endif /* PWR_CR_UDEN */\n\n#if defined(PWR_CR_ODSWEN)\n/**\n  * @brief  Enable Over drive switching\n  * @rmtoll CR    ODSWEN       LL_PWR_EnableOverDriveSwitching\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_ODSWEN);\n}\n\n/**\n  * @brief  Disable Over drive switching\n  * @rmtoll CR    ODSWEN       LL_PWR_DisableOverDriveSwitching\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_ODSWEN);\n}\n\n/**\n  * @brief  Check if Over drive switching is enabled\n  * @rmtoll CR    ODSWEN       LL_PWR_IsEnabledOverDriveSwitching\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_ODSWEN) == (PWR_CR_ODSWEN));\n}\n#endif /* PWR_CR_ODSWEN */\n#if defined(PWR_CR_ODEN)\n/**\n  * @brief  Enable Over drive Mode\n  * @rmtoll CR    ODEN       LL_PWR_EnableOverDriveMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableOverDriveMode(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_ODEN);\n}\n\n/**\n  * @brief  Disable Over drive Mode\n  * @rmtoll CR    ODEN       LL_PWR_DisableOverDriveMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableOverDriveMode(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_ODEN);\n}\n\n/**\n  * @brief  Check if Over drive switching is enabled\n  * @rmtoll CR    ODEN       LL_PWR_IsEnabledOverDriveMode\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_ODEN) == (PWR_CR_ODEN));\n}\n#endif /* PWR_CR_ODEN */\n#if defined(PWR_CR_MRUDS)\n/**\n  * @brief  Enable Main Regulator in deepsleep under-drive Mode\n  * @rmtoll CR    MRUDS       LL_PWR_EnableMainRegulatorDeepSleepUDMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_MRUDS);\n}\n\n/**\n  * @brief  Disable Main Regulator in deepsleep under-drive Mode\n  * @rmtoll CR    MRUDS       LL_PWR_DisableMainRegulatorDeepSleepUDMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_MRUDS);\n}\n\n/**\n  * @brief  Check if Main Regulator in deepsleep under-drive Mode is enabled\n  * @rmtoll CR    MRUDS       LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_MRUDS) == (PWR_CR_MRUDS));\n}\n#endif /* PWR_CR_MRUDS */\n\n#if defined(PWR_CR_LPUDS)\n/**\n  * @brief  Enable Low Power Regulator in deepsleep under-drive Mode\n  * @rmtoll CR    LPUDS       LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_LPUDS);\n}\n\n/**\n  * @brief  Disable Low Power Regulator in deepsleep under-drive Mode\n  * @rmtoll CR    LPUDS       LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_LPUDS);\n}\n\n/**\n  * @brief  Check if Low Power Regulator in deepsleep under-drive Mode is enabled\n  * @rmtoll CR    LPUDS       LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_LPUDS) == (PWR_CR_LPUDS));\n}\n#endif /* PWR_CR_LPUDS */\n\n#if defined(PWR_CR_MRLVDS)\n/**\n  * @brief  Enable Main Regulator low voltage Mode\n  * @rmtoll CR    MRLVDS       LL_PWR_EnableMainRegulatorLowVoltageMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableMainRegulatorLowVoltageMode(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_MRLVDS);\n}\n\n/**\n  * @brief  Disable Main Regulator low voltage Mode\n  * @rmtoll CR    MRLVDS       LL_PWR_DisableMainRegulatorLowVoltageMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableMainRegulatorLowVoltageMode(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_MRLVDS);\n}\n\n/**\n  * @brief  Check if Main Regulator low voltage Mode is enabled\n  * @rmtoll CR    MRLVDS       LL_PWR_IsEnabledMainRegulatorLowVoltageMode\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorLowVoltageMode(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_MRLVDS) == (PWR_CR_MRLVDS));\n}\n#endif /* PWR_CR_MRLVDS */\n\n#if defined(PWR_CR_LPLVDS)\n/**\n  * @brief  Enable Low Power Regulator low voltage Mode\n  * @rmtoll CR    LPLVDS       LL_PWR_EnableLowPowerRegulatorLowVoltageMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorLowVoltageMode(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_LPLVDS);\n}\n\n/**\n  * @brief  Disable Low Power Regulator low voltage Mode\n  * @rmtoll CR    LPLVDS       LL_PWR_DisableLowPowerRegulatorLowVoltageMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorLowVoltageMode(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_LPLVDS);\n}\n\n/**\n  * @brief  Check if Low Power Regulator low voltage Mode is enabled\n  * @rmtoll CR    LPLVDS       LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_LPLVDS) == (PWR_CR_LPLVDS));\n}\n#endif /* PWR_CR_LPLVDS */\n/**\n  * @brief  Set the main internal Regulator output voltage\n  * @rmtoll CR    VOS       LL_PWR_SetRegulVoltageScaling\n  * @param  VoltageScaling This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)\n  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2\n  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3\n  *         (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)\n{\n  MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);\n}\n\n/**\n  * @brief  Get the main internal Regulator output voltage\n  * @rmtoll CR    VOS       LL_PWR_GetRegulVoltageScaling\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)\n  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2\n  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3\n  *         (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices\n  */\n__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)\n{\n  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));\n}\n/**\n  * @brief  Enable the Flash Power Down in Stop Mode\n  * @rmtoll CR    FPDS       LL_PWR_EnableFlashPowerDown\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_FPDS);\n}\n\n/**\n  * @brief  Disable the Flash Power Down in Stop Mode\n  * @rmtoll CR    FPDS       LL_PWR_DisableFlashPowerDown\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_FPDS);\n}\n\n/**\n  * @brief  Check if the Flash Power Down in Stop Mode is enabled\n  * @rmtoll CR    FPDS       LL_PWR_IsEnabledFlashPowerDown\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS));\n}\n\n/**\n  * @brief  Enable access to the backup domain\n  * @rmtoll CR    DBP       LL_PWR_EnableBkUpAccess\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_DBP);\n}\n\n/**\n  * @brief  Disable access to the backup domain\n  * @rmtoll CR    DBP       LL_PWR_DisableBkUpAccess\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_DBP);\n}\n\n/**\n  * @brief  Check if the backup domain is enabled\n  * @rmtoll CR    DBP       LL_PWR_IsEnabledBkUpAccess\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));\n}\n/**\n  * @brief  Enable the backup Regulator\n  * @rmtoll CSR    BRE       LL_PWR_EnableBkUpRegulator\n  * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.\n  * The LL_PWR_EnableBkUpAccess() must be called before using this API.\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)\n{\n  SET_BIT(PWR->CSR, PWR_CSR_BRE);\n}\n\n/**\n  * @brief  Disable the backup Regulator\n  * @rmtoll CSR    BRE       LL_PWR_DisableBkUpRegulator\n  * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.\n  * The LL_PWR_EnableBkUpAccess() must be called before using this API.\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)\n{\n  CLEAR_BIT(PWR->CSR, PWR_CSR_BRE);\n}\n\n/**\n  * @brief  Check if the backup Regulator is enabled\n  * @rmtoll CSR    BRE       LL_PWR_IsEnabledBkUpRegulator\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)\n{\n  return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE));\n}\n\n/**\n  * @brief  Set voltage Regulator mode during deep sleep mode\n  * @rmtoll CR    LPDS         LL_PWR_SetRegulModeDS\n  * @param  RegulMode This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN\n  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)\n{\n  MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);\n}\n\n/**\n  * @brief  Get voltage Regulator mode during deep sleep mode\n  * @rmtoll CR    LPDS         LL_PWR_GetRegulModeDS\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN\n  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER\n  */\n__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)\n{\n  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));\n}\n\n/**\n  * @brief  Set Power Down mode when CPU enters deepsleep\n  * @rmtoll CR    PDDS         LL_PWR_SetPowerMode\\n\n  * @rmtoll CR    MRUDS        LL_PWR_SetPowerMode\\n\n  * @rmtoll CR    LPUDS        LL_PWR_SetPowerMode\\n\n  * @rmtoll CR    FPDS         LL_PWR_SetPowerMode\\n\n  * @rmtoll CR    MRLVDS       LL_PWR_SetPowerMode\\n\n  * @rmtoll CR    LPlVDS       LL_PWR_SetPowerMode\\n\n  * @rmtoll CR    FPDS         LL_PWR_SetPowerMode\\n\n  * @rmtoll CR    LPDS         LL_PWR_SetPowerMode\n  * @param  PDMode This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU\n  *         @arg @ref LL_PWR_MODE_STOP_LPREGU\n  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)\n  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)\n  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)\n  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)\n  *\n  *         (*) not available on all devices\n  *         @arg @ref LL_PWR_MODE_STANDBY\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)\n{\n#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)\n  MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS), PDMode);\n#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)\n  MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS), PDMode);\n#else\n  MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);\n#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */\n}\n\n/**\n  * @brief  Get Power Down mode when CPU enters deepsleep\n  * @rmtoll CR    PDDS         LL_PWR_GetPowerMode\\n\n  * @rmtoll CR    MRUDS        LL_PWR_GetPowerMode\\n\n  * @rmtoll CR    LPUDS        LL_PWR_GetPowerMode\\n\n  * @rmtoll CR    FPDS         LL_PWR_GetPowerMode\\n\n  * @rmtoll CR    MRLVDS       LL_PWR_GetPowerMode\\n\n  * @rmtoll CR    LPLVDS       LL_PWR_GetPowerMode\\n\n  * @rmtoll CR    FPDS         LL_PWR_GetPowerMode\\n\n  * @rmtoll CR    LPDS         LL_PWR_GetPowerMode\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU\n  *         @arg @ref LL_PWR_MODE_STOP_LPREGU\n  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)\n  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)\n  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)\n  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)\n  *\n  *         (*) not available on all devices\n  *         @arg @ref LL_PWR_MODE_STANDBY\n  */\n__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)\n{\n#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)\n  return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS)));\n#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)\n  return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS)));\n#else\n  return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));\n#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */\n}\n\n/**\n  * @brief  Configure the voltage threshold detected by the Power Voltage Detector\n  * @rmtoll CR    PLS       LL_PWR_SetPVDLevel\n  * @param  PVDLevel This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_PVDLEVEL_0\n  *         @arg @ref LL_PWR_PVDLEVEL_1\n  *         @arg @ref LL_PWR_PVDLEVEL_2\n  *         @arg @ref LL_PWR_PVDLEVEL_3\n  *         @arg @ref LL_PWR_PVDLEVEL_4\n  *         @arg @ref LL_PWR_PVDLEVEL_5\n  *         @arg @ref LL_PWR_PVDLEVEL_6\n  *         @arg @ref LL_PWR_PVDLEVEL_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)\n{\n  MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);\n}\n\n/**\n  * @brief  Get the voltage threshold detection\n  * @rmtoll CR    PLS       LL_PWR_GetPVDLevel\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_PWR_PVDLEVEL_0\n  *         @arg @ref LL_PWR_PVDLEVEL_1\n  *         @arg @ref LL_PWR_PVDLEVEL_2\n  *         @arg @ref LL_PWR_PVDLEVEL_3\n  *         @arg @ref LL_PWR_PVDLEVEL_4\n  *         @arg @ref LL_PWR_PVDLEVEL_5\n  *         @arg @ref LL_PWR_PVDLEVEL_6\n  *         @arg @ref LL_PWR_PVDLEVEL_7\n  */\n__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)\n{\n  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));\n}\n\n/**\n  * @brief  Enable Power Voltage Detector\n  * @rmtoll CR    PVDE       LL_PWR_EnablePVD\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnablePVD(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_PVDE);\n}\n\n/**\n  * @brief  Disable Power Voltage Detector\n  * @rmtoll CR    PVDE       LL_PWR_DisablePVD\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisablePVD(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_PVDE);\n}\n\n/**\n  * @brief  Check if Power Voltage Detector is enabled\n  * @rmtoll CR    PVDE       LL_PWR_IsEnabledPVD\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));\n}\n\n/**\n  * @brief  Enable the WakeUp PINx functionality\n  * @rmtoll CSR   EWUP        LL_PWR_EnableWakeUpPin\\n\n  * @rmtoll CSR   EWUP1       LL_PWR_EnableWakeUpPin\\n\n  * @rmtoll CSR   EWUP2       LL_PWR_EnableWakeUpPin\\n\n  * @rmtoll CSR   EWUP3       LL_PWR_EnableWakeUpPin\n  * @param  WakeUpPin This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_WAKEUP_PIN1\n  *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)\n  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)\n  *\n  *         (*) not available on all devices\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)\n{\n  SET_BIT(PWR->CSR, WakeUpPin);\n}\n\n/**\n  * @brief  Disable the WakeUp PINx functionality\n  * @rmtoll CSR   EWUP        LL_PWR_DisableWakeUpPin\\n\n  * @rmtoll CSR   EWUP1       LL_PWR_DisableWakeUpPin\\n\n  * @rmtoll CSR   EWUP2       LL_PWR_DisableWakeUpPin\\n\n  * @rmtoll CSR   EWUP3       LL_PWR_DisableWakeUpPin\n  * @param  WakeUpPin This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_WAKEUP_PIN1\n  *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)\n  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)\n  *\n  *         (*) not available on all devices\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)\n{\n  CLEAR_BIT(PWR->CSR, WakeUpPin);\n}\n\n/**\n  * @brief  Check if the WakeUp PINx functionality is enabled\n  * @rmtoll CSR   EWUP        LL_PWR_IsEnabledWakeUpPin\\n\n  * @rmtoll CSR   EWUP1       LL_PWR_IsEnabledWakeUpPin\\n\n  * @rmtoll CSR   EWUP2       LL_PWR_IsEnabledWakeUpPin\\n\n  * @rmtoll CSR   EWUP3       LL_PWR_IsEnabledWakeUpPin\n  * @param  WakeUpPin This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_WAKEUP_PIN1\n  *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)\n  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)\n  *\n  *         (*) not available on all devices\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)\n{\n  return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));\n}\n\n\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management\n  * @{\n  */\n\n/**\n  * @brief  Get Wake-up Flag\n  * @rmtoll CSR   WUF       LL_PWR_IsActiveFlag_WU\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)\n{\n  return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));\n}\n\n/**\n  * @brief  Get Standby Flag\n  * @rmtoll CSR   SBF       LL_PWR_IsActiveFlag_SB\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)\n{\n  return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));\n}\n\n/**\n  * @brief  Get Backup Regulator ready Flag\n  * @rmtoll CSR   BRR       LL_PWR_IsActiveFlag_BRR\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)\n{\n  return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR));\n}\n/**\n  * @brief  Indicate whether VDD voltage is below the selected PVD threshold\n  * @rmtoll CSR   PVDO       LL_PWR_IsActiveFlag_PVDO\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)\n{\n  return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));\n}\n\n/**\n  * @brief  Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level\n  * @rmtoll CSR   VOS       LL_PWR_IsActiveFlag_VOS\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)\n{\n  return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS));\n}\n#if defined(PWR_CR_ODEN)\n/**\n  * @brief  Indicate whether the Over-Drive mode is ready or not\n  * @rmtoll CSR   ODRDY       LL_PWR_IsActiveFlag_OD\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void)\n{\n  return (READ_BIT(PWR->CSR, PWR_CSR_ODRDY) == (PWR_CSR_ODRDY));\n}\n#endif /* PWR_CR_ODEN */\n\n#if defined(PWR_CR_ODSWEN)\n/**\n  * @brief  Indicate whether the Over-Drive mode switching is ready or not\n  * @rmtoll CSR   ODSWRDY       LL_PWR_IsActiveFlag_ODSW\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void)\n{\n  return (READ_BIT(PWR->CSR, PWR_CSR_ODSWRDY) == (PWR_CSR_ODSWRDY));\n}\n#endif /* PWR_CR_ODSWEN */\n\n#if defined(PWR_CR_UDEN)\n/**\n  * @brief  Indicate whether the Under-Drive mode is ready or not\n  * @rmtoll CSR   UDRDY       LL_PWR_IsActiveFlag_UD\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void)\n{\n  return (READ_BIT(PWR->CSR, PWR_CSR_UDRDY) == (PWR_CSR_UDRDY));\n}\n#endif /* PWR_CR_UDEN */\n/**\n  * @brief  Clear Standby Flag\n  * @rmtoll CR   CSBF       LL_PWR_ClearFlag_SB\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_CSBF);\n}\n\n/**\n  * @brief  Clear Wake-up Flags\n  * @rmtoll CR   CWUF       LL_PWR_ClearFlag_WU\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_CWUF);\n}\n#if defined(PWR_CSR_UDRDY)\n/**\n  * @brief  Clear Under-Drive ready Flag\n  * @rmtoll CSR          UDRDY         LL_PWR_ClearFlag_UD\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_ClearFlag_UD(void)\n{\n  WRITE_REG(PWR->CSR, PWR_CSR_UDRDY);\n}\n#endif /* PWR_CSR_UDRDY */\n\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup PWR_LL_EF_Init De-initialization function\n  * @{\n  */\nErrorStatus LL_PWR_DeInit(void);\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined(PWR) */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_LL_PWR_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_ll_rcc.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_rcc.c\n  * @author  MCD Application Team\n  * @version V1.7.1\n  * @date    14-April-2017\n  * @brief   RCC LL module driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n#if defined(USE_FULL_LL_DRIVER)\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_ll_rcc.h\"\n#ifdef  USE_FULL_ASSERT\n  #include \"stm32_assert.h\"\n#else\n  #define assert_param(expr) ((void)0U)\n#endif\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined(RCC)\n\n/** @addtogroup RCC_LL\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/** @addtogroup RCC_LL_Private_Macros\n  * @{\n  */\n#if defined(FMPI2C1)\n#define IS_LL_RCC_FMPI2C_CLKSOURCE(__VALUE__)     ((__VALUE__) == LL_RCC_FMPI2C1_CLKSOURCE)\n#endif /* FMPI2C1 */\n\n#if defined(LPTIM1)\n#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))\n#endif /* LPTIM1 */\n\n#if defined(SAI1)\n#if defined(RCC_DCKCFGR_SAI1SRC)\n#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \\\n                                            || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))\n#elif defined(RCC_DCKCFGR_SAI1ASRC)\n#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SAI1_A_CLKSOURCE) \\\n                                            || ((__VALUE__) == LL_RCC_SAI1_B_CLKSOURCE))\n#endif /* RCC_DCKCFGR_SAI1SRC */\n#endif /* SAI1 */\n\n#if defined(SDIO)\n#define IS_LL_RCC_SDIO_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_SDIO_CLKSOURCE))\n#endif /* SDIO */\n\n#if defined(RNG)\n#define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))\n#endif /* RNG */\n\n#if defined(USB_OTG_FS) || defined(USB_OTG_HS)\n#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_USB_CLKSOURCE))\n#endif /* USB_OTG_FS || USB_OTG_HS */\n\n#if defined(DFSDM2_Channel0)\n#define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))\n\n#define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE) \\\n                                                    || ((__VALUE__) == LL_RCC_DFSDM2_AUDIO_CLKSOURCE))\n#elif defined(DFSDM1_Channel0)\n#define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))\n\n#define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))\n#endif /* DFSDM2_Channel0 */\n\n#if defined(RCC_DCKCFGR_I2S2SRC)\n#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE) \\\n                                            || ((__VALUE__) == LL_RCC_I2S2_CLKSOURCE))\n#else\n#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))\n#endif /* RCC_DCKCFGR_I2S2SRC */\n\n#if defined(CEC)\n#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))\n#endif /* CEC */\n\n#if defined(DSI)\n#define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))\n#endif /* DSI */\n\n#if defined(LTDC)\n#define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))\n#endif /* LTDC */\n\n#if defined(SPDIFRX)\n#define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE))\n#endif /* SPDIFRX */\n/**\n  * @}\n  */\n\n/* Private function prototypes -----------------------------------------------*/\n/** @defgroup RCC_LL_Private_Functions RCC Private functions\n  * @{\n  */\nuint32_t RCC_GetSystemClockFreq(void);\nuint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);\nuint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);\nuint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);\nuint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source);\nuint32_t RCC_PLL_GetFreqDomain_48M(void);\n#if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)\nuint32_t RCC_PLL_GetFreqDomain_I2S(void);\n#endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */\n#if defined(SPDIFRX)\nuint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void);\n#endif /* SPDIFRX */\n#if defined(RCC_PLLCFGR_PLLR)\n#if defined(SAI1)\nuint32_t RCC_PLL_GetFreqDomain_SAI(void);\n#endif /* SAI1 */\n#endif /* RCC_PLLCFGR_PLLR */\n#if defined(DSI)\nuint32_t RCC_PLL_GetFreqDomain_DSI(void);\n#endif /* DSI */\n#if defined(RCC_PLLSAI_SUPPORT)\nuint32_t RCC_PLLSAI_GetFreqDomain_SAI(void);\n#if defined(RCC_PLLSAICFGR_PLLSAIP)\nuint32_t RCC_PLLSAI_GetFreqDomain_48M(void);\n#endif /* RCC_PLLSAICFGR_PLLSAIP */\n#if defined(LTDC)\nuint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void);\n#endif /* LTDC */\n#endif /* RCC_PLLSAI_SUPPORT */\n#if defined(RCC_PLLI2S_SUPPORT)\nuint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)\nuint32_t RCC_PLLI2S_GetFreqDomain_48M(void);\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */\n#if defined(SAI1)\nuint32_t RCC_PLLI2S_GetFreqDomain_SAI(void);\n#endif /* SAI1 */\n#if defined(SPDIFRX)\nuint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void);\n#endif /* SPDIFRX */\n#endif /* RCC_PLLI2S_SUPPORT */\n/**\n  * @}\n  */\n\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup RCC_LL_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup RCC_LL_EF_Init\n  * @{\n  */\n\n/**\n  * @brief  Reset the RCC clock configuration to the default reset state.\n  * @note   The default reset state of the clock configuration is given below:\n  *         - HSI ON and used as system clock source\n  *         - HSE and PLL OFF\n  *         - AHB, APB1 and APB2 prescaler set to 1.\n  *         - CSS, MCO OFF\n  *         - All interrupts disabled\n  * @note   This function doesn't modify the configuration of the\n  *         - Peripheral clocks\n  *         - LSI, LSE and RTC clocks\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: RCC registers are de-initialized\n  *          - ERROR: not applicable\n  */\nErrorStatus LL_RCC_DeInit(void)\n{\n  __IO uint32_t vl_mask;\n\n  /* Set HSION bit */\n  LL_RCC_HSI_Enable();\n\n  /* Wait for HSI READY bit */\n  while(LL_RCC_HSI_IsReady() != 1U)\n  {}\n\n  /* Reset CFGR register */\n  LL_RCC_WriteReg(CFGR, 0x00000000U);\n\n  /* Read CR register */\n  vl_mask = LL_RCC_ReadReg(CR);\n\n  /* Reset HSEON, HSEBYP, PLLON, CSSON bits */\n  CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON));\n\n#if defined(RCC_PLLSAI_SUPPORT)\n  /* Reset PLLSAION bit */\n  CLEAR_BIT(vl_mask, RCC_CR_PLLSAION);\n#endif /* RCC_PLLSAI_SUPPORT */\n\n#if defined(RCC_PLLI2S_SUPPORT)\n  /* Reset PLLI2SON bit */\n  CLEAR_BIT(vl_mask, RCC_CR_PLLI2SON);\n#endif /* RCC_PLLI2S_SUPPORT */\n\n  /* Write new value in CR register */\n  LL_RCC_WriteReg(CR, vl_mask);\n\n  /* Set HSITRIM bits to the reset value*/\n  LL_RCC_HSI_SetCalibTrimming(0x10U);\n\n  /* Wait for PLL READY bit to be reset */\n  while(LL_RCC_PLL_IsReady() != 0U)\n  {}\n\n  /* Reset PLLCFGR register */\n  LL_RCC_WriteReg(PLLCFGR, RCC_PLLCFGR_RST_VALUE);\n\n#if defined(RCC_PLLI2S_SUPPORT)\n  /* Reset PLLI2SCFGR register */\n  LL_RCC_WriteReg(PLLI2SCFGR, RCC_PLLI2SCFGR_RST_VALUE);\n#endif /* RCC_PLLI2S_SUPPORT */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n  /* Reset PLLSAICFGR register */\n  LL_RCC_WriteReg(PLLSAICFGR, RCC_PLLSAICFGR_RST_VALUE);\n#endif /* RCC_PLLSAI_SUPPORT */\n\n  /* Disable all interrupts */\n  CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE);\n\n#if defined(RCC_CIR_PLLI2SRDYIE)\n  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);\n#endif /* RCC_CIR_PLLI2SRDYIE */\n\n#if defined(RCC_CIR_PLLSAIRDYIE)\n  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);\n#endif /* RCC_CIR_PLLSAIRDYIE */\n\n  /* Clear all interrupt flags */\n  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC);\n\n#if defined(RCC_CIR_PLLI2SRDYC)\n  SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);\n#endif /* RCC_CIR_PLLI2SRDYC */\n\n#if defined(RCC_CIR_PLLSAIRDYC)\n  SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);\n#endif /* RCC_CIR_PLLSAIRDYC */\n\n  /* Clear LSION bit */\n  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);\n\n  /* Reset all CSR flags */\n  SET_BIT(RCC->CSR, RCC_CSR_RMVF);\n\n  return SUCCESS;\n}\n\n/**\n  * @}\n  */\n\n/** @addtogroup RCC_LL_EF_Get_Freq\n  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks\n  *         and different peripheral clocks available on the device.\n  * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)\n  * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)\n  * @note   If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)\n  *         or HSI_VALUE(**) multiplied/divided by the PLL factors.\n  * @note   (**) HSI_VALUE is a constant defined in this file (default value\n  *              16 MHz) but the real value may vary depending on the variations\n  *              in voltage and temperature.\n  * @note   (***) HSE_VALUE is a constant defined in this file (default value\n  *               25 MHz), user has to ensure that HSE_VALUE is same as the real\n  *               frequency of the crystal used. Otherwise, this function may\n  *               have wrong result.\n  * @note   The result of this function could be incorrect when using fractional\n  *         value for HSE crystal.\n  * @note   This function can be used by the user application to compute the\n  *         baud-rate for the communication peripherals or configure other parameters.\n  * @{\n  */\n\n/**\n  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks\n  * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function\n  *         must be called to update structure fields. Otherwise, any\n  *         configuration based on this function will be incorrect.\n  * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies\n  * @retval None\n  */\nvoid LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)\n{\n  /* Get SYSCLK frequency */\n  RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();\n\n  /* HCLK clock frequency */\n  RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);\n\n  /* PCLK1 clock frequency */\n  RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);\n\n  /* PCLK2 clock frequency */\n  RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);\n}\n\n#if defined(FMPI2C1)\n/**\n  * @brief  Return FMPI2Cx clock frequency\n  * @param  FMPI2CxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE\n  * @retval FMPI2C clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready\n  */\nuint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource)\n{\n  uint32_t FMPI2C_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_FMPI2C_CLKSOURCE(FMPI2CxSource));\n\n  if (FMPI2CxSource == LL_RCC_FMPI2C1_CLKSOURCE)\n  {\n    /* FMPI2C1 CLK clock frequency */\n    switch (LL_RCC_GetFMPI2CClockSource(FMPI2CxSource))\n    {\n      case LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK: /* FMPI2C1 Clock is System Clock */\n        FMPI2C_frequency = RCC_GetSystemClockFreq();\n        break;\n\n      case LL_RCC_FMPI2C1_CLKSOURCE_HSI:    /* FMPI2C1 Clock is HSI Osc. */\n        if (LL_RCC_HSI_IsReady())\n        {\n          FMPI2C_frequency = HSI_VALUE;\n        }\n        break;\n\n      case LL_RCC_FMPI2C1_CLKSOURCE_PCLK1:  /* FMPI2C1 Clock is PCLK1 */\n      default:\n        FMPI2C_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n        break;\n    }\n  }\n\n  return FMPI2C_frequency;\n}\n#endif /* FMPI2C1 */\n\n/**\n  * @brief  Return I2Sx clock frequency\n  * @param  I2SxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_I2S1_CLKSOURCE\n  *         @arg @ref LL_RCC_I2S2_CLKSOURCE (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval I2S clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready\n  */\nuint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)\n{\n  uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));\n\n  if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)\n  {\n    /* I2S1 CLK clock frequency */\n    switch (LL_RCC_GetI2SClockSource(I2SxSource))\n    {\n#if defined(RCC_PLLI2S_SUPPORT)\n      case LL_RCC_I2S1_CLKSOURCE_PLLI2S:       /* I2S1 Clock is PLLI2S */\n        if (LL_RCC_PLLI2S_IsReady())\n        {\n          i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();\n        }\n        break;\n#endif /* RCC_PLLI2S_SUPPORT */\n\n#if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)\n      case LL_RCC_I2S1_CLKSOURCE_PLL:          /* I2S1 Clock is PLL */\n        if (LL_RCC_PLL_IsReady())\n        {\n          i2s_frequency = RCC_PLL_GetFreqDomain_I2S();\n        }\n        break;\n\n      case LL_RCC_I2S1_CLKSOURCE_PLLSRC:       /* I2S1 Clock is PLL Main source */\n        switch (LL_RCC_PLL_GetMainSource())\n        {\n           case LL_RCC_PLLSOURCE_HSE:          /* I2S1 Clock is HSE Osc. */\n             if (LL_RCC_HSE_IsReady())\n             {\n               i2s_frequency = HSE_VALUE;\n             }\n             break;\n\n           case LL_RCC_PLLSOURCE_HSI:          /* I2S1 Clock is HSI Osc. */\n           default:\n             if (LL_RCC_HSI_IsReady())\n             {\n               i2s_frequency = HSI_VALUE;\n             }\n             break;\n        }\n        break;\n#endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */\n\n      case LL_RCC_I2S1_CLKSOURCE_PIN:          /* I2S1 Clock is External clock */\n      default:\n        i2s_frequency = EXTERNAL_CLOCK_VALUE;\n        break;\n    }\n  }\n#if defined(RCC_DCKCFGR_I2S2SRC)\n  else\n  {\n    /* I2S2 CLK clock frequency */\n    switch (LL_RCC_GetI2SClockSource(I2SxSource))\n    {\n      case LL_RCC_I2S2_CLKSOURCE_PLLI2S:       /* I2S2 Clock is PLLI2S */\n        if (LL_RCC_PLLI2S_IsReady())\n        {\n          i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();\n        }\n        break;\n\n      case LL_RCC_I2S2_CLKSOURCE_PLL:          /* I2S2 Clock is PLL */\n        if (LL_RCC_PLL_IsReady())\n        {\n          i2s_frequency = RCC_PLL_GetFreqDomain_I2S();\n        }\n        break;\n\n      case LL_RCC_I2S2_CLKSOURCE_PLLSRC:       /* I2S2 Clock is PLL Main source */\n        switch (LL_RCC_PLL_GetMainSource())\n        {\n           case LL_RCC_PLLSOURCE_HSE:          /* I2S2 Clock is HSE Osc. */\n             if (LL_RCC_HSE_IsReady())\n             {\n               i2s_frequency = HSE_VALUE;\n             }\n             break;\n\n           case LL_RCC_PLLSOURCE_HSI:          /* I2S2 Clock is HSI Osc. */\n           default:\n             if (LL_RCC_HSI_IsReady())\n             {\n               i2s_frequency = HSI_VALUE;\n             }\n             break;\n        }\n        break;\n\n      case LL_RCC_I2S2_CLKSOURCE_PIN:          /* I2S2 Clock is External clock */\n      default:\n        i2s_frequency = EXTERNAL_CLOCK_VALUE;\n        break;\n    }\n  }\n#endif /* RCC_DCKCFGR_I2S2SRC */\n\n  return i2s_frequency;\n}\n\n#if defined(LPTIM1)\n/**\n  * @brief  Return LPTIMx clock frequency\n  * @param  LPTIMxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE\n  * @retval LPTIM clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready\n  */\nuint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)\n{\n  uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));\n\n  if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)\n  {\n    /* LPTIM1CLK clock frequency */\n    switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))\n    {\n      case LL_RCC_LPTIM1_CLKSOURCE_LSI:    /* LPTIM1 Clock is LSI Osc. */\n        if (LL_RCC_LSI_IsReady())\n        {\n          lptim_frequency = LSI_VALUE;\n        }\n        break;\n\n      case LL_RCC_LPTIM1_CLKSOURCE_HSI:    /* LPTIM1 Clock is HSI Osc. */\n        if (LL_RCC_HSI_IsReady())\n        {\n          lptim_frequency = HSI_VALUE;\n        }\n        break;\n\n      case LL_RCC_LPTIM1_CLKSOURCE_LSE:    /* LPTIM1 Clock is LSE Osc. */\n        if (LL_RCC_LSE_IsReady())\n        {\n          lptim_frequency = LSE_VALUE;\n        }\n        break;\n\n      case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:  /* LPTIM1 Clock is PCLK1 */\n      default:\n        lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n        break;\n    }\n  }\n\n  return lptim_frequency;\n}\n#endif /* LPTIM1 */\n\n#if defined(SAI1)\n/**\n  * @brief  Return SAIx clock frequency\n  * @param  SAIxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval SAI clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready\n  */\nuint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)\n{\n  uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));\n\n#if defined(RCC_DCKCFGR_SAI1SRC)\n  if ((SAIxSource == LL_RCC_SAI1_CLKSOURCE) || (SAIxSource == LL_RCC_SAI2_CLKSOURCE))\n  {\n    /* SAI1CLK clock frequency */\n    switch (LL_RCC_GetSAIClockSource(SAIxSource))\n    {\n      case LL_RCC_SAI1_CLKSOURCE_PLLSAI:     /* PLLSAI clock used as SAI1 clock source */\n      case LL_RCC_SAI2_CLKSOURCE_PLLSAI:     /* PLLSAI clock used as SAI2 clock source */\n        if (LL_RCC_PLLSAI_IsReady())\n        {\n          sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();\n        }\n        break;\n\n      case LL_RCC_SAI1_CLKSOURCE_PLLI2S:     /* PLLI2S clock used as SAI1 clock source */\n      case LL_RCC_SAI2_CLKSOURCE_PLLI2S:     /* PLLI2S clock used as SAI2 clock source */\n        if (LL_RCC_PLLI2S_IsReady())\n        {\n          sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();\n        }\n        break;\n\n      case LL_RCC_SAI1_CLKSOURCE_PLL:        /* PLL clock used as SAI1 clock source */\n      case LL_RCC_SAI2_CLKSOURCE_PLL:        /* PLL clock used as SAI2 clock source */\n        if (LL_RCC_PLL_IsReady())\n        {\n          sai_frequency = RCC_PLL_GetFreqDomain_SAI();\n        }\n        break;\n\n      case LL_RCC_SAI2_CLKSOURCE_PLLSRC:\n        switch (LL_RCC_PLL_GetMainSource())\n        {\n           case LL_RCC_PLLSOURCE_HSE:        /* HSE clock used as SAI2 clock source */\n             if (LL_RCC_HSE_IsReady())\n             {\n               sai_frequency = HSE_VALUE;\n             }\n             break;\n\n           case LL_RCC_PLLSOURCE_HSI:        /* HSI clock used as SAI2 clock source */\n           default:\n             if (LL_RCC_HSI_IsReady())\n             {\n               sai_frequency = HSI_VALUE;\n             }\n             break;\n        }\n        break;\n\n      case LL_RCC_SAI1_CLKSOURCE_PIN:        /* External input clock used as SAI1 clock source */\n      default:\n        sai_frequency = EXTERNAL_CLOCK_VALUE;\n        break;\n    }\n  }\n#endif /* RCC_DCKCFGR_SAI1SRC */\n#if defined(RCC_DCKCFGR_SAI1ASRC)\n  if ((SAIxSource == LL_RCC_SAI1_A_CLKSOURCE) || (SAIxSource == LL_RCC_SAI1_B_CLKSOURCE))\n  {\n    /* SAI1CLK clock frequency */\n    switch (LL_RCC_GetSAIClockSource(SAIxSource))\n    {\n#if defined(RCC_PLLSAI_SUPPORT)\n      case LL_RCC_SAI1_A_CLKSOURCE_PLLSAI:     /* PLLSAI clock used as SAI1 Block A clock source */\n      case LL_RCC_SAI1_B_CLKSOURCE_PLLSAI:     /* PLLSAI clock used as SAI1 Block B clock source */\n        if (LL_RCC_PLLSAI_IsReady())\n        {\n          sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();\n        }\n        break;\n#endif /* RCC_PLLSAI_SUPPORT */\n\n      case LL_RCC_SAI1_A_CLKSOURCE_PLLI2S:     /* PLLI2S clock used as SAI1 Block A clock source */\n      case LL_RCC_SAI1_B_CLKSOURCE_PLLI2S:     /* PLLI2S clock used as SAI1 Block B clock source */\n        if (LL_RCC_PLLI2S_IsReady())\n        {\n          sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();\n        }\n        break;\n\n#if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)\n      case LL_RCC_SAI1_A_CLKSOURCE_PLL:        /* PLL clock used as SAI1 Block A clock source */\n      case LL_RCC_SAI1_B_CLKSOURCE_PLL:        /* PLL clock used as SAI1 Block B clock source */\n        if (LL_RCC_PLL_IsReady())\n        {\n          sai_frequency = RCC_PLL_GetFreqDomain_SAI();\n        }\n        break;\n\n      case LL_RCC_SAI1_A_CLKSOURCE_PLLSRC:\n      case LL_RCC_SAI1_B_CLKSOURCE_PLLSRC:\n        switch (LL_RCC_PLL_GetMainSource())\n        {\n           case LL_RCC_PLLSOURCE_HSE:          /* HSE clock used as SAI1 Block A or B clock source */\n             if (LL_RCC_HSE_IsReady())\n             {\n               sai_frequency = HSE_VALUE;\n             }\n             break;\n\n           case LL_RCC_PLLSOURCE_HSI:          /* HSI clock used as SAI1 Block A or B clock source */\n           default:\n             if (LL_RCC_HSI_IsReady())\n             {\n               sai_frequency = HSI_VALUE;\n             }\n             break;\n        }\n        break;\n#endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */\n\n      case LL_RCC_SAI1_A_CLKSOURCE_PIN:        /* External input clock used as SAI1 Block A clock source */\n      case LL_RCC_SAI1_B_CLKSOURCE_PIN:        /* External input clock used as SAI1 Block B clock source */\n      default:\n        sai_frequency = EXTERNAL_CLOCK_VALUE;\n        break;\n    }\n  }\n#endif /* RCC_DCKCFGR_SAI1ASRC */\n\n  return sai_frequency;\n}\n#endif /* SAI1 */\n\n#if defined(SDIO)\n/**\n  * @brief  Return SDIOx clock frequency\n  * @param  SDIOxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SDIO_CLKSOURCE\n  * @retval SDIO clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready\n  */\nuint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource)\n{\n  uint32_t SDIO_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_SDIO_CLKSOURCE(SDIOxSource));\n\n  if (SDIOxSource == LL_RCC_SDIO_CLKSOURCE)\n  {\n#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)\n    /* SDIOCLK clock frequency */\n    switch (LL_RCC_GetSDIOClockSource(SDIOxSource))\n    {\n      case LL_RCC_SDIO_CLKSOURCE_PLL48CLK:         /* PLL48M clock used as SDIO clock source */\n        switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))\n        {\n          case LL_RCC_CK48M_CLKSOURCE_PLL:         /* PLL clock used as 48Mhz domain clock */\n            if (LL_RCC_PLL_IsReady())\n            {\n              SDIO_frequency = RCC_PLL_GetFreqDomain_48M();\n            }\n          break;\n\n#if defined(RCC_PLLSAI_SUPPORT)\n          case LL_RCC_CK48M_CLKSOURCE_PLLSAI:      /* PLLSAI clock used as 48Mhz domain clock */\n          default:\n            if (LL_RCC_PLLSAI_IsReady())\n            {\n              SDIO_frequency = RCC_PLLSAI_GetFreqDomain_48M();\n            }\n            break;\n#endif /* RCC_PLLSAI_SUPPORT */\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)\n          case LL_RCC_CK48M_CLKSOURCE_PLLI2S:      /* PLLI2S clock used as 48Mhz domain clock */\n          default:\n            if (LL_RCC_PLLI2S_IsReady())\n            {\n              SDIO_frequency = RCC_PLLI2S_GetFreqDomain_48M();\n            }\n            break;\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */\n        }\n        break;\n\n      case LL_RCC_SDIO_CLKSOURCE_SYSCLK:           /* PLL clock used as SDIO clock source */\n      default:\n      SDIO_frequency = RCC_GetSystemClockFreq();\n      break;\n    }\n#else\n    /* PLL clock used as 48Mhz domain clock */\n    if (LL_RCC_PLL_IsReady())\n    {\n      SDIO_frequency = RCC_PLL_GetFreqDomain_48M();\n    }\n#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */\n  }\n\n  return SDIO_frequency;\n}\n#endif /* SDIO */\n\n#if defined(RNG)\n/**\n  * @brief  Return RNGx clock frequency\n  * @param  RNGxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE\n  * @retval RNG clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready\n  */\nuint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)\n{\n  uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));\n\n#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)\n  /* RNGCLK clock frequency */\n  switch (LL_RCC_GetRNGClockSource(RNGxSource))\n  {\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)\n    case LL_RCC_RNG_CLKSOURCE_PLLI2S:        /* PLLI2S clock used as RNG clock source */\n      if (LL_RCC_PLLI2S_IsReady())\n      {\n        rng_frequency = RCC_PLLI2S_GetFreqDomain_48M();\n      }\n      break;\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n    case LL_RCC_RNG_CLKSOURCE_PLLSAI:        /* PLLSAI clock used as RNG clock source */\n      if (LL_RCC_PLLSAI_IsReady())\n      {\n        rng_frequency = RCC_PLLSAI_GetFreqDomain_48M();\n      }\n      break;\n#endif /* RCC_PLLSAI_SUPPORT */\n\n    case LL_RCC_RNG_CLKSOURCE_PLL:           /* PLL clock used as RNG clock source */\n    default:\n      if (LL_RCC_PLL_IsReady())\n      {\n        rng_frequency = RCC_PLL_GetFreqDomain_48M();\n      }\n      break;\n  }\n#else\n  /* PLL clock used as RNG clock source */\n  if (LL_RCC_PLL_IsReady())\n  {\n    rng_frequency = RCC_PLL_GetFreqDomain_48M();\n  }\n#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */\n\n  return rng_frequency;\n}\n#endif /* RNG */\n\n#if defined(CEC)\n/**\n  * @brief  Return CEC clock frequency\n  * @param  CECxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_CEC_CLKSOURCE\n  * @retval CEC clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready\n  */\nuint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)\n{\n  uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));\n\n  /* CECCLK clock frequency */\n  switch (LL_RCC_GetCECClockSource(CECxSource))\n  {\n    case LL_RCC_CEC_CLKSOURCE_LSE:           /* CEC Clock is LSE Osc. */\n      if (LL_RCC_LSE_IsReady())\n      {\n        cec_frequency = LSE_VALUE;\n      }\n      break;\n\n    case LL_RCC_CEC_CLKSOURCE_HSI_DIV488:    /* CEC Clock is HSI Osc. */\n    default:\n      if (LL_RCC_HSI_IsReady())\n      {\n        cec_frequency = HSI_VALUE/488U;\n      }\n      break;\n  }\n\n  return cec_frequency;\n}\n#endif /* CEC */\n\n#if defined(USB_OTG_FS) || defined(USB_OTG_HS)\n/**\n  * @brief  Return USBx clock frequency\n  * @param  USBxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_USB_CLKSOURCE\n  * @retval USB clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready\n  */\nuint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)\n{\n  uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));\n\n#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)\n  /* USBCLK clock frequency */\n  switch (LL_RCC_GetUSBClockSource(USBxSource))\n  {\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)\n    case LL_RCC_USB_CLKSOURCE_PLLI2S:       /* PLLI2S clock used as USB clock source */\n      if (LL_RCC_PLLI2S_IsReady())\n      {\n        usb_frequency = RCC_PLLI2S_GetFreqDomain_48M();\n      }\n      break;\n\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n    case LL_RCC_USB_CLKSOURCE_PLLSAI:       /* PLLSAI clock used as USB clock source */\n      if (LL_RCC_PLLSAI_IsReady())\n      {\n        usb_frequency = RCC_PLLSAI_GetFreqDomain_48M();\n      }\n      break;\n#endif /* RCC_PLLSAI_SUPPORT */\n\n    case LL_RCC_USB_CLKSOURCE_PLL:          /* PLL clock used as USB clock source */\n    default:\n      if (LL_RCC_PLL_IsReady())\n      {\n        usb_frequency = RCC_PLL_GetFreqDomain_48M();\n      }\n      break;\n  }\n#else\n  /* PLL clock used as USB clock source */\n  if (LL_RCC_PLL_IsReady())\n  {\n    usb_frequency = RCC_PLL_GetFreqDomain_48M();\n  }\n#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */\n\n  return usb_frequency;\n}\n#endif /* USB_OTG_FS || USB_OTG_HS */\n\n#if defined(DFSDM1_Channel0)\n/**\n  * @brief  Return DFSDMx clock frequency\n  * @param  DFSDMxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE\n  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval DFSDM clock frequency (in Hz)\n  */\nuint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)\n{\n  uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));\n\n  if (DFSDMxSource == LL_RCC_DFSDM1_CLKSOURCE)\n  {\n    /* DFSDM1CLK clock frequency */\n    switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))\n    {\n      case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK:      /* DFSDM1 Clock is SYSCLK */\n        dfsdm_frequency = RCC_GetSystemClockFreq();\n        break;\n\n      case LL_RCC_DFSDM1_CLKSOURCE_PCLK2:       /* DFSDM1 Clock is PCLK2 */\n      default:\n        dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n        break;\n    }\n  }\n#if defined(DFSDM2_Channel0)\n  else\n  {\n    /* DFSDM2CLK clock frequency */\n    switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))\n    {\n      case LL_RCC_DFSDM2_CLKSOURCE_SYSCLK:      /* DFSDM2 Clock is SYSCLK */\n        dfsdm_frequency = RCC_GetSystemClockFreq();\n        break;\n\n      case LL_RCC_DFSDM2_CLKSOURCE_PCLK2:       /* DFSDM2 Clock is PCLK2 */\n      default:\n        dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n        break;\n    }\n  }\n#endif /* DFSDM2_Channel0 */\n\n  return dfsdm_frequency;\n}\n\n/**\n  * @brief  Return DFSDMx Audio clock frequency\n  * @param  DFSDMxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE\n  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval DFSDM clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready\n  */\nuint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)\n{\n  uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));\n\n  if (DFSDMxSource == LL_RCC_DFSDM1_AUDIO_CLKSOURCE)\n  {\n    /* DFSDM1CLK clock frequency */\n    switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))\n    {\n      case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1:     /* I2S1 clock used as DFSDM1 clock */\n        dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);\n        break;\n\n      case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2:     /* I2S2 clock used as DFSDM1 clock */\n      default:\n        dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);\n        break;\n    }\n  }\n#if defined(DFSDM2_Channel0)\n  else\n  {\n    /* DFSDM2CLK clock frequency */\n    switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))\n    {\n      case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1:     /* I2S1 clock used as DFSDM2 clock */\n        dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);\n        break;\n\n      case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2:     /* I2S2 clock used as DFSDM2 clock */\n      default:\n        dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);\n        break;\n    }\n  }\n#endif /* DFSDM2_Channel0 */\n\n  return dfsdm_frequency;\n}\n#endif /* DFSDM1_Channel0 */\n\n#if defined(DSI)\n/**\n  * @brief  Return DSI clock frequency\n  * @param  DSIxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DSI_CLKSOURCE\n  * @retval DSI clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used\n  */\nuint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)\n{\n  uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));\n\n  /* DSICLK clock frequency */\n  switch (LL_RCC_GetDSIClockSource(DSIxSource))\n  {\n    case LL_RCC_DSI_CLKSOURCE_PLL:     /* DSI Clock is PLL Osc. */\n      if (LL_RCC_PLL_IsReady())\n      {\n        dsi_frequency = RCC_PLL_GetFreqDomain_DSI();\n      }\n      break;\n\n    case LL_RCC_DSI_CLKSOURCE_PHY:    /* DSI Clock is DSI physical clock. */\n    default:\n      dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;\n      break;\n  }\n\n  return dsi_frequency;\n}\n#endif /* DSI */\n\n#if defined(LTDC)\n/**\n  * @brief  Return LTDC clock frequency\n  * @param  LTDCxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_LTDC_CLKSOURCE\n  * @retval LTDC clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready\n  */\nuint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)\n{\n  uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));\n\n  if (LL_RCC_PLLSAI_IsReady())\n  {\n     ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC();\n  }\n\n  return ltdc_frequency;\n}\n#endif /* LTDC */\n\n#if defined(SPDIFRX)\n/**\n  * @brief  Return SPDIFRX clock frequency\n  * @param  SPDIFRXxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE\n  * @retval SPDIFRX clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready\n  */\nuint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)\n{\n  uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));\n\n  /* SPDIFRX1CLK clock frequency */\n  switch (LL_RCC_GetSPDIFRXClockSource(SPDIFRXxSource))\n  {\n    case LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S:  /* SPDIFRX Clock is PLLI2S Osc. */\n      if (LL_RCC_PLLI2S_IsReady())\n      {\n        spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX();\n      }\n      break;\n\n    case LL_RCC_SPDIFRX1_CLKSOURCE_PLL:     /* SPDIFRX Clock is PLL Osc. */\n    default:\n      if (LL_RCC_PLL_IsReady())\n      {\n        spdifrx_frequency = RCC_PLL_GetFreqDomain_SPDIFRX();\n      }\n      break;\n  }\n\n  return spdifrx_frequency;\n}\n#endif /* SPDIFRX */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup RCC_LL_Private_Functions\n  * @{\n  */\n\n/**\n  * @brief  Return SYSTEM clock frequency\n  * @retval SYSTEM clock frequency (in Hz)\n  */\nuint32_t RCC_GetSystemClockFreq(void)\n{\n  uint32_t frequency = 0U;\n\n  /* Get SYSCLK source -------------------------------------------------------*/\n  switch (LL_RCC_GetSysClkSource())\n  {\n    case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:  /* HSI used as system clock  source */\n      frequency = HSI_VALUE;\n      break;\n\n    case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */\n      frequency = HSE_VALUE;\n      break;\n\n    case LL_RCC_SYS_CLKSOURCE_STATUS_PLL:  /* PLL used as system clock  source */\n      frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLL);\n      break;\n\n#if defined(RCC_PLLR_SYSCLK_SUPPORT)\n    case LL_RCC_SYS_CLKSOURCE_STATUS_PLLR: /* PLLR used as system clock  source */\n      frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLLR);\n      break;\n#endif /* RCC_PLLR_SYSCLK_SUPPORT */\n\n    default:\n      frequency = HSI_VALUE;\n      break;\n  }\n\n  return frequency;\n}\n\n/**\n  * @brief  Return HCLK clock frequency\n  * @param  SYSCLK_Frequency SYSCLK clock frequency\n  * @retval HCLK clock frequency (in Hz)\n  */\nuint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)\n{\n  /* HCLK clock frequency */\n  return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());\n}\n\n/**\n  * @brief  Return PCLK1 clock frequency\n  * @param  HCLK_Frequency HCLK clock frequency\n  * @retval PCLK1 clock frequency (in Hz)\n  */\nuint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)\n{\n  /* PCLK1 clock frequency */\n  return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());\n}\n\n/**\n  * @brief  Return PCLK2 clock frequency\n  * @param  HCLK_Frequency HCLK clock frequency\n  * @retval PCLK2 clock frequency (in Hz)\n  */\nuint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)\n{\n  /* PCLK2 clock frequency */\n  return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());\n}\n\n/**\n  * @brief  Return PLL clock frequency used for system domain\n  * @param  SYSCLK_Source System clock source\n  * @retval PLL clock frequency (in Hz)\n  */\nuint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U;\n\n  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN\n     SYSCLK = PLL_VCO / (PLLP or PLLR)\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */\n      pllinputfreq = HSI_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    default:\n      pllinputfreq = HSI_VALUE;\n      break;\n  }\n\n  if (SYSCLK_Source == LL_RCC_SYS_CLKSOURCE_STATUS_PLL)\n  {\n    plloutputfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());\n  }\n#if defined(RCC_PLLR_SYSCLK_SUPPORT)\n  else\n  {\n    plloutputfreq = __LL_RCC_CALC_PLLRCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());\n  }\n#endif /* RCC_PLLR_SYSCLK_SUPPORT */\n\n  return plloutputfreq;\n}\n\n/**\n  * @brief  Return PLL clock frequency used for 48 MHz domain\n  * @retval PLL clock frequency (in Hz)\n  */\nuint32_t RCC_PLL_GetFreqDomain_48M(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN\n     48M Domain clock = PLL_VCO / PLLQ\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */\n      pllinputfreq = HSI_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    default:\n      pllinputfreq = HSI_VALUE;\n      break;\n  }\n  return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());\n}\n\n#if defined(DSI)\n/**\n  * @brief  Return PLL clock frequency used for DSI clock\n  * @retval PLL clock frequency (in Hz)\n  */\nuint32_t RCC_PLL_GetFreqDomain_DSI(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN\n     DSICLK = PLL_VCO / PLLR\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */\n    default:\n      pllinputfreq = HSI_VALUE;\n      break;\n  }\n  return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());\n}\n#endif /* DSI */\n\n#if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)\n/**\n  * @brief  Return PLL clock frequency used for I2S clock\n  * @retval PLL clock frequency (in Hz)\n  */\nuint32_t RCC_PLL_GetFreqDomain_I2S(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN\n     I2SCLK = PLL_VCO / PLLR\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */\n    default:\n      pllinputfreq = HSI_VALUE;\n      break;\n  }\n  return __LL_RCC_CALC_PLLCLK_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());\n}\n#endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */\n\n#if defined(SPDIFRX)\n/**\n  * @brief  Return PLL clock frequency used for SPDIFRX clock\n  * @retval PLL clock frequency (in Hz)\n  */\nuint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN\n     SPDIFRXCLK = PLL_VCO / PLLR\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */\n    default:\n      pllinputfreq = HSI_VALUE;\n      break;\n  }\n  return __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());\n}\n#endif /* SPDIFRX */\n\n#if defined(RCC_PLLCFGR_PLLR)\n#if defined(SAI1)\n/**\n  * @brief  Return PLL clock frequency used for SAI clock\n  * @retval PLL clock frequency (in Hz)\n  */\nuint32_t RCC_PLL_GetFreqDomain_SAI(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U;\n\n  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN\n     SAICLK = (PLL_VCO / PLLR) / PLLDIVR\n     or\n     SAICLK = PLL_VCO / PLLR\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */\n    default:\n      pllinputfreq = HSI_VALUE;\n      break;\n  }\n\n#if defined(RCC_DCKCFGR_PLLDIVR)\n  plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR(), LL_RCC_PLL_GetDIVR());\n#else\n  plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());\n#endif /* RCC_DCKCFGR_PLLDIVR */\n\n  return plloutputfreq;\n}\n#endif /* SAI1 */\n#endif /* RCC_PLLCFGR_PLLR */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n/**\n  * @brief  Return PLLSAI clock frequency used for SAI domain\n  * @retval PLLSAI clock frequency (in Hz)\n  */\nuint32_t RCC_PLLSAI_GetFreqDomain_SAI(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN\n     SAI domain clock  = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI clock source */\n      pllinputfreq = HSI_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    default:\n      pllinputfreq = HSI_VALUE;\n      break;\n  }\n  return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),\n                                        LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_GetDIVQ());\n}\n\n#if defined(RCC_PLLSAICFGR_PLLSAIP)\n/**\n  * @brief  Return PLLSAI clock frequency used for 48Mhz domain\n  * @retval PLLSAI clock frequency (in Hz)\n  */\nuint32_t RCC_PLLSAI_GetFreqDomain_48M(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN\n     48M Domain clock  = PLLSAI_VCO / PLLSAIP\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI clock source */\n      pllinputfreq = HSI_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    default:\n      pllinputfreq = HSI_VALUE;\n      break;\n  }\n  return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),\n                                        LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP());\n}\n#endif /* RCC_PLLSAICFGR_PLLSAIP */\n\n#if defined(LTDC)\n/**\n  * @brief  Return PLLSAI clock frequency used for LTDC domain\n  * @retval PLLSAI clock frequency (in Hz)\n  */\nuint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN\n     LTDC Domain clock  = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI clock source */\n      pllinputfreq = HSI_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    default:\n      pllinputfreq = HSI_VALUE;\n      break;\n  }\n  return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),\n                                        LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR());\n}\n#endif /* LTDC */\n#endif /* RCC_PLLSAI_SUPPORT */\n\n#if defined(RCC_PLLI2S_SUPPORT)\n#if defined(SAI1)\n/**\n  * @brief  Return PLLI2S clock frequency used for SAI domains\n  * @retval PLLI2S clock frequency (in Hz)\n  */\nuint32_t RCC_PLLI2S_GetFreqDomain_SAI(void)\n{\n  uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;\n\n  /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN\n     SAI domain clock  = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ\n     or\n     SAI domain clock  = (PLLI2S_VCO / PLLI2SR) / PLLI2SDIVR\n  */\n  plli2ssource = LL_RCC_PLLI2S_GetMainSource();\n\n  switch (plli2ssource)\n  {\n    case LL_RCC_PLLSOURCE_HSE:     /* HSE used as PLLI2S clock source */\n      plli2sinputfreq = HSE_VALUE;\n      break;\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)\n    case LL_RCC_PLLI2SSOURCE_PIN:  /* External pin input clock used as PLLI2S clock source */\n      plli2sinputfreq = EXTERNAL_CLOCK_VALUE;\n      break;\n#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */\n\n    case LL_RCC_PLLSOURCE_HSI:     /* HSI used as PLLI2S clock source */\n    default:\n      plli2sinputfreq = HSI_VALUE;\n      break;\n  }\n\n#if defined(RCC_DCKCFGR_PLLI2SDIVQ)\n  plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),\n                                          LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ());\n#else\n  plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),\n                                          LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR(), LL_RCC_PLLI2S_GetDIVR());\n#endif /* RCC_DCKCFGR_PLLI2SDIVQ */\n\n  return plli2soutputfreq;\n}\n#endif /* SAI1 */\n\n#if defined(SPDIFRX)\n/**\n  * @brief  Return PLLI2S clock frequency used for SPDIFRX domain\n  * @retval PLLI2S clock frequency (in Hz)\n  */\nuint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN\n     SPDIFRX Domain clock  = PLLI2S_VCO / PLLI2SP\n  */\n  pllsource = LL_RCC_PLLI2S_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLI2S clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLI2S clock source */\n    default:\n      pllinputfreq = HSI_VALUE;\n      break;\n  }\n\n  return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLLI2S_GetDivider(),\n                                           LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP());\n}\n#endif /* SPDIFRX */\n\n/**\n  * @brief  Return PLLI2S clock frequency used for I2S domain\n  * @retval PLLI2S clock frequency (in Hz)\n  */\nuint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)\n{\n  uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;\n\n  /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN\n     I2S Domain clock  = PLLI2S_VCO / PLLI2SR\n  */\n  plli2ssource = LL_RCC_PLLI2S_GetMainSource();\n\n  switch (plli2ssource)\n  {\n    case LL_RCC_PLLSOURCE_HSE:     /* HSE used as PLLI2S clock source */\n      plli2sinputfreq = HSE_VALUE;\n      break;\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)\n    case LL_RCC_PLLI2SSOURCE_PIN:  /* External pin input clock used as PLLI2S clock source */\n      plli2sinputfreq = EXTERNAL_CLOCK_VALUE;\n      break;\n#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */\n\n    case LL_RCC_PLLSOURCE_HSI:     /* HSI used as PLLI2S clock source */\n    default:\n      plli2sinputfreq = HSI_VALUE;\n      break;\n  }\n\n  plli2soutputfreq = __LL_RCC_CALC_PLLI2S_I2S_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),\n                                                   LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR());\n\n  return plli2soutputfreq;\n}\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)\n/**\n  * @brief  Return PLLI2S clock frequency used for 48Mhz domain\n  * @retval PLLI2S clock frequency (in Hz)\n  */\nuint32_t RCC_PLLI2S_GetFreqDomain_48M(void)\n{\n  uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;\n\n  /* PLL48M_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN\n     48M Domain clock  = PLLI2S_VCO / PLLI2SQ\n  */\n  plli2ssource = LL_RCC_PLLI2S_GetMainSource();\n\n  switch (plli2ssource)\n  {\n    case LL_RCC_PLLSOURCE_HSE:     /* HSE used as PLLI2S clock source */\n      plli2sinputfreq = HSE_VALUE;\n      break;\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)\n    case LL_RCC_PLLI2SSOURCE_PIN:  /* External pin input clock used as PLLI2S clock source */\n      plli2sinputfreq = EXTERNAL_CLOCK_VALUE;\n      break;\n#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */\n\n    case LL_RCC_PLLSOURCE_HSI:     /* HSI used as PLLI2S clock source */\n    default:\n      plli2sinputfreq = HSI_VALUE;\n      break;\n  }\n\n  plli2soutputfreq = __LL_RCC_CALC_PLLI2S_48M_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),\n                                                   LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ());\n\n  return plli2soutputfreq;\n}\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */\n#endif /* RCC_PLLI2S_SUPPORT */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined(RCC) */\n\n/**\n  * @}\n  */\n\n#endif /* USE_FULL_LL_DRIVER */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_ll_rcc.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_rcc.h\n  * @author  MCD Application Team\n  * @version V1.7.1\n  * @date    14-April-2017\n  * @brief   Header file of RCC LL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_LL_RCC_H\n#define __STM32F4xx_LL_RCC_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined(RCC)\n\n/** @defgroup RCC_LL RCC\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/** @defgroup RCC_LL_Private_Variables RCC Private Variables\n  * @{\n  */\n\n#if defined(RCC_DCKCFGR_PLLSAIDIVR)\nstatic const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};\n#endif /* RCC_DCKCFGR_PLLSAIDIVR */\n\n/**\n  * @}\n  */\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup RCC_LL_Private_Macros RCC Private Macros\n  * @{\n  */\n/**\n  * @}\n  */\n#endif /*USE_FULL_LL_DRIVER*/\n/* Exported types ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup RCC_LL_Exported_Types RCC Exported Types\n  * @{\n  */\n\n/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure\n  * @{\n  */\n\n/**\n  * @brief  RCC Clocks Frequency Structure\n  */\ntypedef struct\n{\n  uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */\n  uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */\n  uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */\n  uint32_t PCLK2_Frequency;         /*!< PCLK2 clock frequency */\n} LL_RCC_ClocksTypeDef;\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants\n  * @{\n  */\n\n/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation\n  * @brief    Defines used to adapt values of different oscillators\n  * @note     These values could be modified in the user environment according to\n  *           HW set-up.\n  * @{\n  */\n#if !defined  (HSE_VALUE)\n#define HSE_VALUE    25000000U  /*!< Value of the HSE oscillator in Hz */\n#endif /* HSE_VALUE */\n\n#if !defined  (HSI_VALUE)\n#define HSI_VALUE    16000000U  /*!< Value of the HSI oscillator in Hz */\n#endif /* HSI_VALUE */\n\n#if !defined  (LSE_VALUE)\n#define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */\n#endif /* LSE_VALUE */\n\n#if !defined  (LSI_VALUE)\n#define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */\n#endif /* LSI_VALUE */\n\n#if !defined  (EXTERNAL_CLOCK_VALUE)\n#define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */\n#endif /* EXTERNAL_CLOCK_VALUE */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines\n  * @brief    Flags defines which can be used with LL_RCC_WriteReg function\n  * @{\n  */\n#define LL_RCC_CIR_LSIRDYC                RCC_CIR_LSIRDYC     /*!< LSI Ready Interrupt Clear */\n#define LL_RCC_CIR_LSERDYC                RCC_CIR_LSERDYC     /*!< LSE Ready Interrupt Clear */\n#define LL_RCC_CIR_HSIRDYC                RCC_CIR_HSIRDYC     /*!< HSI Ready Interrupt Clear */\n#define LL_RCC_CIR_HSERDYC                RCC_CIR_HSERDYC     /*!< HSE Ready Interrupt Clear */\n#define LL_RCC_CIR_PLLRDYC                RCC_CIR_PLLRDYC     /*!< PLL Ready Interrupt Clear */\n#if defined(RCC_PLLI2S_SUPPORT)\n#define LL_RCC_CIR_PLLI2SRDYC             RCC_CIR_PLLI2SRDYC  /*!< PLLI2S Ready Interrupt Clear */\n#endif /* RCC_PLLI2S_SUPPORT */\n#if defined(RCC_PLLSAI_SUPPORT)\n#define LL_RCC_CIR_PLLSAIRDYC             RCC_CIR_PLLSAIRDYC  /*!< PLLSAI Ready Interrupt Clear */\n#endif /* RCC_PLLSAI_SUPPORT */\n#define LL_RCC_CIR_CSSC                   RCC_CIR_CSSC        /*!< Clock Security System Interrupt Clear */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines\n  * @brief    Flags defines which can be used with LL_RCC_ReadReg function\n  * @{\n  */\n#define LL_RCC_CIR_LSIRDYF                RCC_CIR_LSIRDYF     /*!< LSI Ready Interrupt flag */\n#define LL_RCC_CIR_LSERDYF                RCC_CIR_LSERDYF     /*!< LSE Ready Interrupt flag */\n#define LL_RCC_CIR_HSIRDYF                RCC_CIR_HSIRDYF     /*!< HSI Ready Interrupt flag */\n#define LL_RCC_CIR_HSERDYF                RCC_CIR_HSERDYF     /*!< HSE Ready Interrupt flag */\n#define LL_RCC_CIR_PLLRDYF                RCC_CIR_PLLRDYF     /*!< PLL Ready Interrupt flag */\n#if defined(RCC_PLLI2S_SUPPORT)\n#define LL_RCC_CIR_PLLI2SRDYF             RCC_CIR_PLLI2SRDYF  /*!< PLLI2S Ready Interrupt flag */\n#endif /* RCC_PLLI2S_SUPPORT */\n#if defined(RCC_PLLSAI_SUPPORT)\n#define LL_RCC_CIR_PLLSAIRDYF             RCC_CIR_PLLSAIRDYF  /*!< PLLSAI Ready Interrupt flag */\n#endif /* RCC_PLLSAI_SUPPORT */\n#define LL_RCC_CIR_CSSF                   RCC_CIR_CSSF        /*!< Clock Security System Interrupt flag */\n#define LL_RCC_CSR_LPWRRSTF                RCC_CSR_LPWRRSTF   /*!< Low-Power reset flag */\n#define LL_RCC_CSR_PINRSTF                 RCC_CSR_PINRSTF    /*!< PIN reset flag */\n#define LL_RCC_CSR_PORRSTF                 RCC_CSR_PORRSTF    /*!< POR/PDR reset flag */\n#define LL_RCC_CSR_SFTRSTF                 RCC_CSR_SFTRSTF    /*!< Software Reset flag */\n#define LL_RCC_CSR_IWDGRSTF                RCC_CSR_IWDGRSTF   /*!< Independent Watchdog reset flag */\n#define LL_RCC_CSR_WWDGRSTF                RCC_CSR_WWDGRSTF   /*!< Window watchdog reset flag */\n#if defined(RCC_CSR_BORRSTF)\n#define LL_RCC_CSR_BORRSTF                 RCC_CSR_BORRSTF    /*!< BOR reset flag */\n#endif /* RCC_CSR_BORRSTF */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_IT IT Defines\n  * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions\n  * @{\n  */\n#define LL_RCC_CIR_LSIRDYIE               RCC_CIR_LSIRDYIE      /*!< LSI Ready Interrupt Enable */\n#define LL_RCC_CIR_LSERDYIE               RCC_CIR_LSERDYIE      /*!< LSE Ready Interrupt Enable */\n#define LL_RCC_CIR_HSIRDYIE               RCC_CIR_HSIRDYIE      /*!< HSI Ready Interrupt Enable */\n#define LL_RCC_CIR_HSERDYIE               RCC_CIR_HSERDYIE      /*!< HSE Ready Interrupt Enable */\n#define LL_RCC_CIR_PLLRDYIE               RCC_CIR_PLLRDYIE      /*!< PLL Ready Interrupt Enable */\n#if defined(RCC_PLLI2S_SUPPORT)\n#define LL_RCC_CIR_PLLI2SRDYIE            RCC_CIR_PLLI2SRDYIE   /*!< PLLI2S Ready Interrupt Enable */\n#endif /* RCC_PLLI2S_SUPPORT */\n#if defined(RCC_PLLSAI_SUPPORT)\n#define LL_RCC_CIR_PLLSAIRDYIE            RCC_CIR_PLLSAIRDYIE   /*!< PLLSAI Ready Interrupt Enable */\n#endif /* RCC_PLLSAI_SUPPORT */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch\n  * @{\n  */\n#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */\n#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */\n#define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */\n#if defined(RCC_CFGR_SW_PLLR)\n#define LL_RCC_SYS_CLKSOURCE_PLLR          RCC_CFGR_SW_PLLR   /*!< PLLR selection as system clock */\n#endif /* RCC_CFGR_SW_PLLR */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status\n  * @{\n  */\n#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */\n#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */\n#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */\n#if defined(RCC_PLLR_SYSCLK_SUPPORT)\n#define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR   RCC_CFGR_SWS_PLLR  /*!< PLLR used as system clock */\n#endif /* RCC_PLLR_SYSCLK_SUPPORT */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler\n  * @{\n  */\n#define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */\n#define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */\n#define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */\n#define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */\n#define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */\n#define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */\n#define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */\n#define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */\n#define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)\n  * @{\n  */\n#define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */\n#define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */\n#define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */\n#define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */\n#define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)\n  * @{\n  */\n#define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */\n#define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */\n#define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */\n#define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */\n#define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_MCOxSOURCE  MCO source selection\n  * @{\n  */\n#define LL_RCC_MCO1SOURCE_HSI              (uint32_t)(RCC_CFGR_MCO1|0x00000000U)                    /*!< HSI selection as MCO1 source */\n#define LL_RCC_MCO1SOURCE_LSE              (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U))       /*!< LSE selection as MCO1 source */\n#define LL_RCC_MCO1SOURCE_HSE              (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U))       /*!< HSE selection as MCO1 source */\n#define LL_RCC_MCO1SOURCE_PLLCLK           (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U))       /*!< PLLCLK selection as MCO1 source */\n#if defined(RCC_CFGR_MCO2)\n#define LL_RCC_MCO2SOURCE_SYSCLK           (uint32_t)(RCC_CFGR_MCO2|0x00000000U)                    /*!< SYSCLK selection as MCO2 source */\n#define LL_RCC_MCO2SOURCE_PLLI2S           (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U))       /*!< PLLI2S selection as MCO2 source */\n#define LL_RCC_MCO2SOURCE_HSE              (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U))       /*!< HSE selection as MCO2 source */\n#define LL_RCC_MCO2SOURCE_PLLCLK           (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U))       /*!< PLLCLK selection as MCO2 source */\n#endif /* RCC_CFGR_MCO2 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_MCOx_DIV  MCO prescaler\n  * @{\n  */\n#define LL_RCC_MCO1_DIV_1                  (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U)                       /*!< MCO1 not divided */\n#define LL_RCC_MCO1_DIV_2                  (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U))       /*!< MCO1 divided by 2 */\n#define LL_RCC_MCO1_DIV_3                  (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U))       /*!< MCO1 divided by 3 */\n#define LL_RCC_MCO1_DIV_4                  (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U))       /*!< MCO1 divided by 4 */\n#define LL_RCC_MCO1_DIV_5                  (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U))         /*!< MCO1 divided by 5 */\n#if defined(RCC_CFGR_MCO2PRE)\n#define LL_RCC_MCO2_DIV_1                  (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U)                       /*!< MCO2 not divided */\n#define LL_RCC_MCO2_DIV_2                  (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U))       /*!< MCO2 divided by 2 */\n#define LL_RCC_MCO2_DIV_3                  (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U))       /*!< MCO2 divided by 3 */\n#define LL_RCC_MCO2_DIV_4                  (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U))       /*!< MCO2 divided by 4 */\n#define LL_RCC_MCO2_DIV_5                  (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U))         /*!< MCO2 divided by 5 */\n#endif /* RCC_CFGR_MCO2PRE */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_RTC_HSEDIV  HSE prescaler for RTC clock\n  * @{\n  */\n#define LL_RCC_RTC_NOCLOCK                  0x00000000U             /*!< HSE not divided */\n#define LL_RCC_RTC_HSE_DIV_2                RCC_CFGR_RTCPRE_1       /*!< HSE clock divided by 2 */\n#define LL_RCC_RTC_HSE_DIV_3                (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 3 */\n#define LL_RCC_RTC_HSE_DIV_4                RCC_CFGR_RTCPRE_2       /*!< HSE clock divided by 4 */\n#define LL_RCC_RTC_HSE_DIV_5                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 5 */\n#define LL_RCC_RTC_HSE_DIV_6                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 6 */\n#define LL_RCC_RTC_HSE_DIV_7                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 7 */\n#define LL_RCC_RTC_HSE_DIV_8                RCC_CFGR_RTCPRE_3       /*!< HSE clock divided by 8 */\n#define LL_RCC_RTC_HSE_DIV_9                (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 9 */\n#define LL_RCC_RTC_HSE_DIV_10               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 10 */\n#define LL_RCC_RTC_HSE_DIV_11               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 11 */\n#define LL_RCC_RTC_HSE_DIV_12               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)       /*!< HSE clock divided by 12 */\n#define LL_RCC_RTC_HSE_DIV_13               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 13 */\n#define LL_RCC_RTC_HSE_DIV_14               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 14 */\n#define LL_RCC_RTC_HSE_DIV_15               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 15 */\n#define LL_RCC_RTC_HSE_DIV_16               RCC_CFGR_RTCPRE_4       /*!< HSE clock divided by 16 */\n#define LL_RCC_RTC_HSE_DIV_17               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 17 */\n#define LL_RCC_RTC_HSE_DIV_18               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 18 */\n#define LL_RCC_RTC_HSE_DIV_19               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 19 */\n#define LL_RCC_RTC_HSE_DIV_20               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)       /*!< HSE clock divided by 20 */\n#define LL_RCC_RTC_HSE_DIV_21               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 21 */\n#define LL_RCC_RTC_HSE_DIV_22               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 22 */\n#define LL_RCC_RTC_HSE_DIV_23               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 23 */\n#define LL_RCC_RTC_HSE_DIV_24               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)       /*!< HSE clock divided by 24 */\n#define LL_RCC_RTC_HSE_DIV_25               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 25 */\n#define LL_RCC_RTC_HSE_DIV_26               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 26 */\n#define LL_RCC_RTC_HSE_DIV_27               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 27 */\n#define LL_RCC_RTC_HSE_DIV_28               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)       /*!< HSE clock divided by 28 */\n#define LL_RCC_RTC_HSE_DIV_29               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 29 */\n#define LL_RCC_RTC_HSE_DIV_30               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 30 */\n#define LL_RCC_RTC_HSE_DIV_31               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 31 */\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency\n  * @{\n  */\n#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U                 /*!< No clock enabled for the peripheral            */\n#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU                 /*!< Frequency cannot be provided as external clock */\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n#if defined(FMPI2C1)\n/** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE  Peripheral FMPI2C clock source selection\n  * @{\n  */\n#define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1        0x00000000U               /*!< PCLK1 clock used as FMPI2C1 clock source */\n#define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK       RCC_DCKCFGR2_FMPI2C1SEL_0 /*!< SYSCLK clock used as FMPI2C1 clock source */\n#define LL_RCC_FMPI2C1_CLKSOURCE_HSI          RCC_DCKCFGR2_FMPI2C1SEL_1 /*!< HSI clock used as FMPI2C1 clock source */\n/**\n  * @}\n  */\n#endif /* FMPI2C1 */\n\n#if defined(LPTIM1)\n/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE  Peripheral LPTIM clock source selection\n  * @{\n  */\n#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1       0x00000000U                 /*!< PCLK1 clock used as LPTIM1 clock */\n#define LL_RCC_LPTIM1_CLKSOURCE_HSI         RCC_DCKCFGR2_LPTIM1SEL_0    /*!< LSI oscillator clock used as LPTIM1 clock */\n#define LL_RCC_LPTIM1_CLKSOURCE_LSI         RCC_DCKCFGR2_LPTIM1SEL_1    /*!< HSI oscillator clock used as LPTIM1 clock */\n#define LL_RCC_LPTIM1_CLKSOURCE_LSE         (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0)      /*!< LSE oscillator clock used as LPTIM1 clock */\n/**\n  * @}\n  */\n#endif /* LPTIM1 */\n\n#if defined(SAI1)\n/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI clock source selection\n  * @{\n  */\n#if defined(RCC_DCKCFGR_SAI1SRC)\n#define LL_RCC_SAI1_CLKSOURCE_PLLSAI       (uint32_t)(RCC_DCKCFGR_SAI1SRC | 0x00000000U)                     /*!< PLLSAI clock used as SAI1 clock source */\n#define LL_RCC_SAI1_CLKSOURCE_PLLI2S       (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_0 >> 16))   /*!< PLLI2S clock used as SAI1 clock source */\n#define LL_RCC_SAI1_CLKSOURCE_PLL          (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_1 >> 16))   /*!< PLL clock used as SAI1 clock source */\n#define LL_RCC_SAI1_CLKSOURCE_PIN          (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC >> 16))     /*!< External pin clock used as SAI1 clock source */\n#endif /* RCC_DCKCFGR_SAI1SRC */\n#if defined(RCC_DCKCFGR_SAI2SRC)\n#define LL_RCC_SAI2_CLKSOURCE_PLLSAI       (uint32_t)(RCC_DCKCFGR_SAI2SRC | 0x00000000U)                     /*!< PLLSAI clock used as SAI2 clock source */\n#define LL_RCC_SAI2_CLKSOURCE_PLLI2S       (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_0 >> 16))   /*!< PLLI2S clock used as SAI2 clock source */\n#define LL_RCC_SAI2_CLKSOURCE_PLL          (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_1 >> 16))   /*!< PLL clock used as SAI2 clock source */\n#define LL_RCC_SAI2_CLKSOURCE_PLLSRC       (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC >> 16))     /*!< PLL Main clock used as SAI2 clock source */\n#endif /* RCC_DCKCFGR_SAI2SRC */\n#if defined(RCC_DCKCFGR_SAI1ASRC)\n#if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)\n#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U)                    /*!< PLLI2S clock used as SAI1 block A clock source */\n#define LL_RCC_SAI1_A_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< External pin used as SAI1 block A clock source */\n#define LL_RCC_SAI1_A_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< PLL clock used as SAI1 block A clock source */\n#define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC >> 16))   /*!< PLL Main clock used as SAI1 block A clock source */\n#else\n#define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI     (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U)                    /*!< PLLSAI clock used as SAI1 block A clock source */\n#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block A clock source */\n#define LL_RCC_SAI1_A_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< External pin clock used as SAI1 block A clock source */\n#endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */\n#endif /* RCC_DCKCFGR_SAI1ASRC */\n#if defined(RCC_DCKCFGR_SAI1BSRC)\n#if defined(RCC_SAI1B_PLLSOURCE_SUPPORT)\n#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U)                    /*!< PLLI2S clock used as SAI1 block B clock source */\n#define LL_RCC_SAI1_B_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< External pin used as SAI1 block B clock source */\n#define LL_RCC_SAI1_B_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< PLL clock used as SAI1 block B clock source */\n#define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC >> 16))   /*!< PLL Main clock used as SAI1 block B clock source */\n#else\n#define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI     (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U)                    /*!< PLLSAI clock used as SAI1 block B clock source */\n#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block B clock source */\n#define LL_RCC_SAI1_B_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< External pin clock used as SAI1 block B clock source */\n#endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */\n#endif /* RCC_DCKCFGR_SAI1BSRC */\n/**\n  * @}\n  */\n#endif /* SAI1 */\n\n#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)\n/** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE  Peripheral SDIO clock source selection\n  * @{\n  */\n#define LL_RCC_SDIO_CLKSOURCE_PLL48CLK       0x00000000U                 /*!< PLL 48M domain clock used as SDIO clock */\n#if defined(RCC_DCKCFGR_SDIOSEL)\n#define LL_RCC_SDIO_CLKSOURCE_SYSCLK         RCC_DCKCFGR_SDIOSEL         /*!< System clock clock used as SDIO clock */\n#else\n#define LL_RCC_SDIO_CLKSOURCE_SYSCLK         RCC_DCKCFGR2_SDIOSEL        /*!< System clock clock used as SDIO clock */\n#endif /* RCC_DCKCFGR_SDIOSEL */\n/**\n  * @}\n  */\n#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */\n\n#if defined(DSI)\n/** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral DSI clock source selection\n  * @{\n  */\n#define LL_RCC_DSI_CLKSOURCE_PHY          0x00000000U                       /*!< DSI-PHY clock used as DSI byte lane clock source */\n#define LL_RCC_DSI_CLKSOURCE_PLL          RCC_DCKCFGR_DSISEL                /*!< PLL clock used as DSI byte lane clock source */\n/**\n  * @}\n  */\n#endif /* DSI */\n\n#if defined(CEC)\n/** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC clock source selection\n  * @{\n  */\n#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488    0x00000000U                /*!< HSI oscillator clock divided by 488 used as CEC clock */\n#define LL_RCC_CEC_CLKSOURCE_LSE           RCC_DCKCFGR2_CECSEL        /*!< LSE oscillator clock used as CEC clock */\n/**\n  * @}\n  */\n#endif /* CEC */\n\n/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE  Peripheral I2S clock source selection\n  * @{\n  */\n#if defined(RCC_CFGR_I2SSRC)\n#define LL_RCC_I2S1_CLKSOURCE_PLLI2S     0x00000000U                /*!< I2S oscillator clock used as I2S1 clock */\n#define LL_RCC_I2S1_CLKSOURCE_PIN        RCC_CFGR_I2SSRC            /*!< External pin clock used as I2S1 clock */\n#endif /* RCC_CFGR_I2SSRC */\n#if defined(RCC_DCKCFGR_I2SSRC)\n#define LL_RCC_I2S1_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_I2SSRC | 0x00000000U)                    /*!< PLL clock used as I2S1 clock source */\n#define LL_RCC_I2S1_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_0 >> 16))   /*!< External pin used as I2S1 clock source */\n#define LL_RCC_I2S1_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_1 >> 16))   /*!< PLL Main clock used as I2S1 clock source */\n#endif /* RCC_DCKCFGR_I2SSRC */\n#if defined(RCC_DCKCFGR_I2S1SRC)\n#define LL_RCC_I2S1_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_I2S1SRC | 0x00000000U)                   /*!< PLLI2S clock used as I2S1 clock source */\n#define LL_RCC_I2S1_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /*!< External pin used as I2S1 clock source */\n#define LL_RCC_I2S1_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /*!< PLL clock used as I2S1 clock source */\n#define LL_RCC_I2S1_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC >> 16))   /*!< PLL Main clock used as I2S1 clock source */\n#endif /* RCC_DCKCFGR_I2S1SRC */\n#if defined(RCC_DCKCFGR_I2S2SRC)\n#define LL_RCC_I2S2_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_I2S2SRC | 0x00000000U)                   /*!< PLLI2S clock used as I2S2 clock source */\n#define LL_RCC_I2S2_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /*!< External pin used as I2S2 clock source */\n#define LL_RCC_I2S2_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /*!< PLL clock used as I2S2 clock source */\n#define LL_RCC_I2S2_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC >> 16))   /*!< PLL Main clock used as I2S2 clock source */\n#endif /* RCC_DCKCFGR_I2S2SRC */\n/**\n  * @}\n  */\n\n#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)\n/** @defgroup RCC_LL_EC_CK48M_CLKSOURCE  Peripheral 48Mhz domain clock source selection\n  * @{\n  */\n#if defined(RCC_DCKCFGR_CK48MSEL)\n#define LL_RCC_CK48M_CLKSOURCE_PLL         0x00000000U                /*!< PLL oscillator clock used as 48Mhz domain clock */\n#define LL_RCC_CK48M_CLKSOURCE_PLLSAI      RCC_DCKCFGR_CK48MSEL       /*!< PLLSAI oscillator clock used as 48Mhz domain clock */\n#endif /* RCC_DCKCFGR_CK48MSEL */\n#if defined(RCC_DCKCFGR2_CK48MSEL)\n#define LL_RCC_CK48M_CLKSOURCE_PLL         0x00000000U                /*!< PLL oscillator clock used as 48Mhz domain clock */\n#if defined(RCC_PLLSAI_SUPPORT)\n#define LL_RCC_CK48M_CLKSOURCE_PLLSAI      RCC_DCKCFGR2_CK48MSEL      /*!< PLLSAI oscillator clock used as 48Mhz domain clock */\n#endif /* RCC_PLLSAI_SUPPORT */\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)\n#define LL_RCC_CK48M_CLKSOURCE_PLLI2S      RCC_DCKCFGR2_CK48MSEL      /*!< PLLI2S oscillator clock used as 48Mhz domain clock */\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */\n#endif /* RCC_DCKCFGR2_CK48MSEL */\n/**\n  * @}\n  */\n\n#if defined(RNG)\n/** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection\n  * @{\n  */\n#define LL_RCC_RNG_CLKSOURCE_PLL          LL_RCC_CK48M_CLKSOURCE_PLL        /*!< PLL clock used as RNG clock source */\n#if defined(RCC_PLLSAI_SUPPORT)\n#define LL_RCC_RNG_CLKSOURCE_PLLSAI       LL_RCC_CK48M_CLKSOURCE_PLLSAI     /*!< PLLSAI clock used as RNG clock source */\n#endif /* RCC_PLLSAI_SUPPORT */\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)\n#define LL_RCC_RNG_CLKSOURCE_PLLI2S       LL_RCC_CK48M_CLKSOURCE_PLLI2S     /*!< PLLI2S clock used as RNG clock source */\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */\n/**\n  * @}\n  */\n#endif /* RNG */\n\n#if defined(USB_OTG_FS) || defined(USB_OTG_HS)\n/** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection\n  * @{\n  */\n#define LL_RCC_USB_CLKSOURCE_PLL          LL_RCC_CK48M_CLKSOURCE_PLL        /*!< PLL clock used as USB clock source */\n#if defined(RCC_PLLSAI_SUPPORT)\n#define LL_RCC_USB_CLKSOURCE_PLLSAI       LL_RCC_CK48M_CLKSOURCE_PLLSAI     /*!< PLLSAI clock used as USB clock source */\n#endif /* RCC_PLLSAI_SUPPORT */\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)\n#define LL_RCC_USB_CLKSOURCE_PLLI2S       LL_RCC_CK48M_CLKSOURCE_PLLI2S     /*!< PLLI2S clock used as USB clock source */\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */\n/**\n  * @}\n  */\n#endif /* USB_OTG_FS || USB_OTG_HS */\n\n#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */\n\n#if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)\n/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE  Peripheral DFSDM Audio clock source selection\n  * @{\n  */\n#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1     (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | 0x00000000U)                      /*!< I2S1 clock used as DFSDM1 Audio clock source */\n#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2     (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /*!< I2S2 clock used as DFSDM1 Audio clock source */\n#if defined(DFSDM2_Channel0)\n#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1     (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | 0x00000000U)                      /*!< I2S1 clock used as DFSDM2 Audio clock source */\n#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2     (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /*!< I2S2 clock used as DFSDM2 Audio clock source */\n#endif /* DFSDM2_Channel0 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE  Peripheral DFSDM clock source selection\n  * @{\n  */\n#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          0x00000000U                /*!< PCLK2 clock used as DFSDM1 clock */\n#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         RCC_DCKCFGR_CKDFSDM1SEL    /*!< System clock used as DFSDM1 clock */\n#if defined(DFSDM2_Channel0)\n#define LL_RCC_DFSDM2_CLKSOURCE_PCLK2          0x00000000U                /*!< PCLK2 clock used as DFSDM2 clock */\n#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK         RCC_DCKCFGR_CKDFSDM1SEL    /*!< System clock used as DFSDM2 clock */\n#endif /* DFSDM2_Channel0 */\n/**\n  * @}\n  */\n#endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */\n\n#if defined(FMPI2C1)\n/** @defgroup RCC_LL_EC_FMPI2C1  Peripheral FMPI2C get clock source\n  * @{\n  */\n#define LL_RCC_FMPI2C1_CLKSOURCE              RCC_DCKCFGR2_FMPI2C1SEL  /*!< FMPI2C1 Clock source selection */\n/**\n  * @}\n  */\n#endif /* FMPI2C1 */\n\n#if defined(SPDIFRX)\n/** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE  Peripheral SPDIFRX clock source selection\n  * @{\n  */\n#define LL_RCC_SPDIFRX1_CLKSOURCE_PLL          0x00000000U             /*!< PLL clock used as SPDIFRX clock source */\n#define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S       RCC_DCKCFGR2_SPDIFRXSEL /*!< PLLI2S clock used as SPDIFRX clock source */\n/**\n  * @}\n  */\n#endif /* SPDIFRX */\n\n#if defined(LPTIM1)\n/** @defgroup RCC_LL_EC_LPTIM1  Peripheral LPTIM get clock source\n  * @{\n  */\n#define LL_RCC_LPTIM1_CLKSOURCE            RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */\n/**\n  * @}\n  */\n#endif /* LPTIM1 */\n\n#if defined(SAI1)\n/** @defgroup RCC_LL_EC_SAIx  Peripheral SAI get clock source\n  * @{\n  */\n#if defined(RCC_DCKCFGR_SAI1ASRC)\n#define LL_RCC_SAI1_A_CLKSOURCE            RCC_DCKCFGR_SAI1ASRC /*!< SAI1 block A Clock source selection */\n#endif /* RCC_DCKCFGR_SAI1ASRC */\n#if defined(RCC_DCKCFGR_SAI1BSRC)\n#define LL_RCC_SAI1_B_CLKSOURCE            RCC_DCKCFGR_SAI1BSRC /*!< SAI1 block B Clock source selection */\n#endif /* RCC_DCKCFGR_SAI1BSRC */\n#if defined(RCC_DCKCFGR_SAI1SRC)\n#define LL_RCC_SAI1_CLKSOURCE              RCC_DCKCFGR_SAI1SRC  /*!< SAI1 Clock source selection */\n#endif /* RCC_DCKCFGR_SAI1SRC */\n#if defined(RCC_DCKCFGR_SAI2SRC)\n#define LL_RCC_SAI2_CLKSOURCE              RCC_DCKCFGR_SAI2SRC  /*!< SAI2 Clock source selection */\n#endif /* RCC_DCKCFGR_SAI2SRC */\n/**\n  * @}\n  */\n#endif /* SAI1 */\n\n#if defined(SDIO)\n/** @defgroup RCC_LL_EC_SDIOx  Peripheral SDIO get clock source\n  * @{\n  */\n#if defined(RCC_DCKCFGR_SDIOSEL)\n#define LL_RCC_SDIO_CLKSOURCE            RCC_DCKCFGR_SDIOSEL   /*!< SDIO Clock source selection */\n#elif defined(RCC_DCKCFGR2_SDIOSEL)\n#define LL_RCC_SDIO_CLKSOURCE            RCC_DCKCFGR2_SDIOSEL  /*!< SDIO Clock source selection */\n#else\n#define LL_RCC_SDIO_CLKSOURCE            RCC_PLLCFGR_PLLQ      /*!< SDIO Clock source selection */\n#endif\n/**\n  * @}\n  */\n#endif /* SDIO */\n\n#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)\n/** @defgroup RCC_LL_EC_CK48M  Peripheral CK48M get clock source\n  * @{\n  */\n#if defined(RCC_DCKCFGR_CK48MSEL)\n#define LL_RCC_CK48M_CLKSOURCE             RCC_DCKCFGR_CK48MSEL  /*!< CK48M Domain clock source selection */\n#endif /* RCC_DCKCFGR_CK48MSEL */\n#if defined(RCC_DCKCFGR2_CK48MSEL)\n#define LL_RCC_CK48M_CLKSOURCE             RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */\n#endif /* RCC_DCKCFGR_CK48MSEL */\n/**\n  * @}\n  */\n#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */\n\n#if defined(RNG)\n/** @defgroup RCC_LL_EC_RNG  Peripheral RNG get clock source\n  * @{\n  */\n#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)\n#define LL_RCC_RNG_CLKSOURCE               LL_RCC_CK48M_CLKSOURCE /*!< RNG Clock source selection */\n#else\n#define LL_RCC_RNG_CLKSOURCE               RCC_PLLCFGR_PLLQ       /*!< RNG Clock source selection */\n#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */\n/**\n  * @}\n  */\n#endif /* RNG */\n\n#if defined(USB_OTG_FS) || defined(USB_OTG_HS)\n/** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source\n  * @{\n  */\n#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)\n#define LL_RCC_USB_CLKSOURCE               LL_RCC_CK48M_CLKSOURCE /*!< USB Clock source selection */\n#else\n#define LL_RCC_USB_CLKSOURCE               RCC_PLLCFGR_PLLQ       /*!< USB Clock source selection */\n#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */\n/**\n  * @}\n  */\n#endif /* USB_OTG_FS || USB_OTG_HS */\n\n#if defined(CEC)\n/** @defgroup RCC_LL_EC_CEC  Peripheral CEC get clock source\n  * @{\n  */\n#define LL_RCC_CEC_CLKSOURCE               RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */\n/**\n  * @}\n  */\n#endif /* CEC */\n\n/** @defgroup RCC_LL_EC_I2S1  Peripheral I2S get clock source\n  * @{\n  */\n#if defined(RCC_CFGR_I2SSRC)\n#define LL_RCC_I2S1_CLKSOURCE              RCC_CFGR_I2SSRC     /*!< I2S1 Clock source selection */\n#endif /* RCC_CFGR_I2SSRC */\n#if defined(RCC_DCKCFGR_I2SSRC)\n#define LL_RCC_I2S1_CLKSOURCE              RCC_DCKCFGR_I2SSRC  /*!< I2S1 Clock source selection */\n#endif /* RCC_DCKCFGR_I2SSRC */\n#if defined(RCC_DCKCFGR_I2S1SRC)\n#define LL_RCC_I2S1_CLKSOURCE              RCC_DCKCFGR_I2S1SRC /*!< I2S1 Clock source selection */\n#endif /* RCC_DCKCFGR_I2S1SRC */\n#if defined(RCC_DCKCFGR_I2S2SRC)\n#define LL_RCC_I2S2_CLKSOURCE              RCC_DCKCFGR_I2S2SRC /*!< I2S2 Clock source selection */\n#endif /* RCC_DCKCFGR_I2S2SRC */\n/**\n  * @}\n  */\n\n#if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)\n/** @defgroup RCC_LL_EC_DFSDM_AUDIO  Peripheral DFSDM Audio get clock source\n  * @{\n  */\n#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE      RCC_DCKCFGR_CKDFSDM1ASEL /*!< DFSDM1 Audio Clock source selection */\n#if defined(DFSDM2_Channel0)\n#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE      RCC_DCKCFGR_CKDFSDM2ASEL /*!< DFSDM2 Audio Clock source selection */\n#endif /* DFSDM2_Channel0 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_DFSDM  Peripheral DFSDM get clock source\n  * @{\n  */\n#define LL_RCC_DFSDM1_CLKSOURCE            RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM1 Clock source selection */\n#if defined(DFSDM2_Channel0)\n#define LL_RCC_DFSDM2_CLKSOURCE            RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM2 Clock source selection */\n#endif /* DFSDM2_Channel0 */\n/**\n  * @}\n  */\n#endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */\n\n#if defined(SPDIFRX)\n/** @defgroup RCC_LL_EC_SPDIFRX  Peripheral SPDIFRX get clock source\n  * @{\n  */\n#define LL_RCC_SPDIFRX1_CLKSOURCE          RCC_DCKCFGR2_SPDIFRXSEL /*!< SPDIFRX Clock source selection */\n/**\n  * @}\n  */\n#endif /* SPDIFRX */\n\n#if defined(DSI)\n/** @defgroup RCC_LL_EC_DSI  Peripheral DSI get clock source\n  * @{\n  */\n#define LL_RCC_DSI_CLKSOURCE               RCC_DCKCFGR_DSISEL /*!< DSI Clock source selection */\n/**\n  * @}\n  */\n#endif /* DSI */\n\n#if defined(LTDC)\n/** @defgroup RCC_LL_EC_LTDC  Peripheral LTDC get clock source\n  * @{\n  */\n#define LL_RCC_LTDC_CLKSOURCE              RCC_DCKCFGR_PLLSAIDIVR /*!< LTDC Clock source selection */\n/**\n  * @}\n  */\n#endif /* LTDC */\n\n\n/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection\n  * @{\n  */\n#define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RTC clock */\n#define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */\n#define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */\n#define LL_RCC_RTC_CLKSOURCE_HSE           RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */\n/**\n  * @}\n  */\n\n#if defined(RCC_DCKCFGR_TIMPRE)\n/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER  Timers clocks prescalers selection\n  * @{\n  */\n#define LL_RCC_TIM_PRESCALER_TWICE          0x00000000U                  /*!< Timers clock to twice PCLK */\n#define LL_RCC_TIM_PRESCALER_FOUR_TIMES     RCC_DCKCFGR_TIMPRE          /*!< Timers clock to four time PCLK */\n/**\n  * @}\n  */\n#endif /* RCC_DCKCFGR_TIMPRE */\n\n/** @defgroup RCC_LL_EC_PLLSOURCE  PLL, PLLI2S and PLLSAI entry clock source\n  * @{\n  */\n#define LL_RCC_PLLSOURCE_HSI               RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI16 clock selected as PLL entry clock source */\n#define LL_RCC_PLLSOURCE_HSE               RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */\n#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)\n#define LL_RCC_PLLI2SSOURCE_PIN            (RCC_PLLI2SCFGR_PLLI2SSRC | 0x80U)  /*!< I2S External pin input clock selected as PLLI2S entry clock source */\n#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_PLLM_DIV  PLL, PLLI2S and PLLSAI division factor\n  * @{\n  */\n#define LL_RCC_PLLM_DIV_2                  (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */\n#define LL_RCC_PLLM_DIV_3                  (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */\n#define LL_RCC_PLLM_DIV_4                  (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */\n#define LL_RCC_PLLM_DIV_5                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */\n#define LL_RCC_PLLM_DIV_6                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */\n#define LL_RCC_PLLM_DIV_7                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */\n#define LL_RCC_PLLM_DIV_8                  (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */\n#define LL_RCC_PLLM_DIV_9                  (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */\n#define LL_RCC_PLLM_DIV_10                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */\n#define LL_RCC_PLLM_DIV_11                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */\n#define LL_RCC_PLLM_DIV_12                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */\n#define LL_RCC_PLLM_DIV_13                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */\n#define LL_RCC_PLLM_DIV_14                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */\n#define LL_RCC_PLLM_DIV_15                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */\n#define LL_RCC_PLLM_DIV_16                 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */\n#define LL_RCC_PLLM_DIV_17                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */\n#define LL_RCC_PLLM_DIV_18                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */\n#define LL_RCC_PLLM_DIV_19                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */\n#define LL_RCC_PLLM_DIV_20                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */\n#define LL_RCC_PLLM_DIV_21                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */\n#define LL_RCC_PLLM_DIV_22                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */\n#define LL_RCC_PLLM_DIV_23                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */\n#define LL_RCC_PLLM_DIV_24                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */\n#define LL_RCC_PLLM_DIV_25                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */\n#define LL_RCC_PLLM_DIV_26                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */\n#define LL_RCC_PLLM_DIV_27                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */\n#define LL_RCC_PLLM_DIV_28                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */\n#define LL_RCC_PLLM_DIV_29                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */\n#define LL_RCC_PLLM_DIV_30                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */\n#define LL_RCC_PLLM_DIV_31                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */\n#define LL_RCC_PLLM_DIV_32                 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */\n#define LL_RCC_PLLM_DIV_33                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */\n#define LL_RCC_PLLM_DIV_34                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */\n#define LL_RCC_PLLM_DIV_35                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */\n#define LL_RCC_PLLM_DIV_36                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */\n#define LL_RCC_PLLM_DIV_37                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */\n#define LL_RCC_PLLM_DIV_38                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */\n#define LL_RCC_PLLM_DIV_39                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */\n#define LL_RCC_PLLM_DIV_40                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */\n#define LL_RCC_PLLM_DIV_41                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */\n#define LL_RCC_PLLM_DIV_42                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */\n#define LL_RCC_PLLM_DIV_43                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */\n#define LL_RCC_PLLM_DIV_44                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */\n#define LL_RCC_PLLM_DIV_45                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */\n#define LL_RCC_PLLM_DIV_46                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */\n#define LL_RCC_PLLM_DIV_47                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */\n#define LL_RCC_PLLM_DIV_48                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */\n#define LL_RCC_PLLM_DIV_49                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */\n#define LL_RCC_PLLM_DIV_50                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */\n#define LL_RCC_PLLM_DIV_51                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */\n#define LL_RCC_PLLM_DIV_52                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */\n#define LL_RCC_PLLM_DIV_53                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */\n#define LL_RCC_PLLM_DIV_54                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */\n#define LL_RCC_PLLM_DIV_55                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */\n#define LL_RCC_PLLM_DIV_56                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */\n#define LL_RCC_PLLM_DIV_57                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */\n#define LL_RCC_PLLM_DIV_58                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */\n#define LL_RCC_PLLM_DIV_59                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */\n#define LL_RCC_PLLM_DIV_60                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */\n#define LL_RCC_PLLM_DIV_61                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */\n#define LL_RCC_PLLM_DIV_62                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */\n#define LL_RCC_PLLM_DIV_63                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */\n/**\n  * @}\n  */\n\n#if defined(RCC_PLLCFGR_PLLR)\n/** @defgroup RCC_LL_EC_PLLR_DIV  PLL division factor (PLLR)\n  * @{\n  */\n#define LL_RCC_PLLR_DIV_2                  (RCC_PLLCFGR_PLLR_1)                     /*!< Main PLL division factor for PLLCLK (system clock) by 2 */\n#define LL_RCC_PLLR_DIV_3                  (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL division factor for PLLCLK (system clock) by 3 */\n#define LL_RCC_PLLR_DIV_4                  (RCC_PLLCFGR_PLLR_2)                     /*!< Main PLL division factor for PLLCLK (system clock) by 4 */\n#define LL_RCC_PLLR_DIV_5                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL division factor for PLLCLK (system clock) by 5 */\n#define LL_RCC_PLLR_DIV_6                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1)  /*!< Main PLL division factor for PLLCLK (system clock) by 6 */\n#define LL_RCC_PLLR_DIV_7                  (RCC_PLLCFGR_PLLR)                       /*!< Main PLL division factor for PLLCLK (system clock) by 7 */\n/**\n  * @}\n  */\n#endif /* RCC_PLLCFGR_PLLR */\n\n#if defined(RCC_DCKCFGR_PLLDIVR)\n/** @defgroup RCC_LL_EC_PLLDIVR  PLLDIVR division factor (PLLDIVR)\n  * @{\n  */\n#define LL_RCC_PLLDIVR_DIV_1           (RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 1 */\n#define LL_RCC_PLLDIVR_DIV_2           (RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 2 */\n#define LL_RCC_PLLDIVR_DIV_3           (RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 3 */\n#define LL_RCC_PLLDIVR_DIV_4           (RCC_DCKCFGR_PLLDIVR_2)        /*!< PLL division factor for PLLDIVR output by 4 */\n#define LL_RCC_PLLDIVR_DIV_5           (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 5 */\n#define LL_RCC_PLLDIVR_DIV_6           (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 6 */\n#define LL_RCC_PLLDIVR_DIV_7           (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 7 */\n#define LL_RCC_PLLDIVR_DIV_8           (RCC_DCKCFGR_PLLDIVR_3)        /*!< PLL division factor for PLLDIVR output by 8 */\n#define LL_RCC_PLLDIVR_DIV_9           (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 9 */\n#define LL_RCC_PLLDIVR_DIV_10          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 10 */\n#define LL_RCC_PLLDIVR_DIV_11          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 11 */\n#define LL_RCC_PLLDIVR_DIV_12          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2)        /*!< PLL division factor for PLLDIVR output by 12 */\n#define LL_RCC_PLLDIVR_DIV_13          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 13 */\n#define LL_RCC_PLLDIVR_DIV_14          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 14 */\n#define LL_RCC_PLLDIVR_DIV_15          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 15 */\n#define LL_RCC_PLLDIVR_DIV_16          (RCC_DCKCFGR_PLLDIVR_4)             /*!< PLL division factor for PLLDIVR output by 16 */\n#define LL_RCC_PLLDIVR_DIV_17          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 17 */\n#define LL_RCC_PLLDIVR_DIV_18          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 18 */\n#define LL_RCC_PLLDIVR_DIV_19          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 19 */\n#define LL_RCC_PLLDIVR_DIV_20          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2)        /*!< PLL division factor for PLLDIVR output by 20 */\n#define LL_RCC_PLLDIVR_DIV_21          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 21 */\n#define LL_RCC_PLLDIVR_DIV_22          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 22 */\n#define LL_RCC_PLLDIVR_DIV_23          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 23 */\n#define LL_RCC_PLLDIVR_DIV_24          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3)        /*!< PLL division factor for PLLDIVR output by 24 */\n#define LL_RCC_PLLDIVR_DIV_25          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 25 */\n#define LL_RCC_PLLDIVR_DIV_26          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 26 */\n#define LL_RCC_PLLDIVR_DIV_27          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 27 */\n#define LL_RCC_PLLDIVR_DIV_28          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2)        /*!< PLL division factor for PLLDIVR output by 28 */\n#define LL_RCC_PLLDIVR_DIV_29          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 29 */\n#define LL_RCC_PLLDIVR_DIV_30          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 30 */\n#define LL_RCC_PLLDIVR_DIV_31          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 31 */\n/**\n  * @}\n  */\n#endif /* RCC_DCKCFGR_PLLDIVR */\n\n/** @defgroup RCC_LL_EC_PLLP_DIV  PLL division factor (PLLP)\n  * @{\n  */\n#define LL_RCC_PLLP_DIV_2                  0x00000000U            /*!< Main PLL division factor for PLLP output by 2 */\n#define LL_RCC_PLLP_DIV_4                  RCC_PLLCFGR_PLLP_0     /*!< Main PLL division factor for PLLP output by 4 */\n#define LL_RCC_PLLP_DIV_6                  RCC_PLLCFGR_PLLP_1     /*!< Main PLL division factor for PLLP output by 6 */\n#define LL_RCC_PLLP_DIV_8                  (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)   /*!< Main PLL division factor for PLLP output by 8 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_PLLQ_DIV  PLL division factor (PLLQ)\n  * @{\n  */\n#define LL_RCC_PLLQ_DIV_2                  RCC_PLLCFGR_PLLQ_1                      /*!< Main PLL division factor for PLLQ output by 2 */\n#define LL_RCC_PLLQ_DIV_3                  (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */\n#define LL_RCC_PLLQ_DIV_4                  RCC_PLLCFGR_PLLQ_2                      /*!< Main PLL division factor for PLLQ output by 4 */\n#define LL_RCC_PLLQ_DIV_5                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */\n#define LL_RCC_PLLQ_DIV_6                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */\n#define LL_RCC_PLLQ_DIV_7                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */\n#define LL_RCC_PLLQ_DIV_8                  RCC_PLLCFGR_PLLQ_3                      /*!< Main PLL division factor for PLLQ output by 8 */\n#define LL_RCC_PLLQ_DIV_9                  (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */\n#define LL_RCC_PLLQ_DIV_10                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */\n#define LL_RCC_PLLQ_DIV_11                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */\n#define LL_RCC_PLLQ_DIV_12                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */\n#define LL_RCC_PLLQ_DIV_13                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */\n#define LL_RCC_PLLQ_DIV_14                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */\n#define LL_RCC_PLLQ_DIV_15                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_PLL_SPRE_SEL  PLL Spread Spectrum Selection\n  * @{\n  */\n#define LL_RCC_SPREAD_SELECT_CENTER        0x00000000U                   /*!< PLL center spread spectrum selection */\n#define LL_RCC_SPREAD_SELECT_DOWN          RCC_SSCGR_SPREADSEL           /*!< PLL down spread spectrum selection */\n/**\n  * @}\n  */\n\n#if defined(RCC_PLLI2S_SUPPORT)\n/** @defgroup RCC_LL_EC_PLLI2SM  PLLI2SM division factor (PLLI2SM)\n  * @{\n  */\n#if defined(RCC_PLLI2SCFGR_PLLI2SM)\n#define LL_RCC_PLLI2SM_DIV_2             (RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 2 */\n#define LL_RCC_PLLI2SM_DIV_3             (RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 3 */\n#define LL_RCC_PLLI2SM_DIV_4             (RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 4 */\n#define LL_RCC_PLLI2SM_DIV_5             (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 5 */\n#define LL_RCC_PLLI2SM_DIV_6             (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 6 */\n#define LL_RCC_PLLI2SM_DIV_7             (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 7 */\n#define LL_RCC_PLLI2SM_DIV_8             (RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 8 */\n#define LL_RCC_PLLI2SM_DIV_9             (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 9 */\n#define LL_RCC_PLLI2SM_DIV_10            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 10 */\n#define LL_RCC_PLLI2SM_DIV_11            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 11 */\n#define LL_RCC_PLLI2SM_DIV_12            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 12 */\n#define LL_RCC_PLLI2SM_DIV_13            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 13 */\n#define LL_RCC_PLLI2SM_DIV_14            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 14 */\n#define LL_RCC_PLLI2SM_DIV_15            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 15 */\n#define LL_RCC_PLLI2SM_DIV_16            (RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 16 */\n#define LL_RCC_PLLI2SM_DIV_17            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 17 */\n#define LL_RCC_PLLI2SM_DIV_18            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 18 */\n#define LL_RCC_PLLI2SM_DIV_19            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 19 */\n#define LL_RCC_PLLI2SM_DIV_20            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 20 */\n#define LL_RCC_PLLI2SM_DIV_21            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 21 */\n#define LL_RCC_PLLI2SM_DIV_22            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 22 */\n#define LL_RCC_PLLI2SM_DIV_23            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 23 */\n#define LL_RCC_PLLI2SM_DIV_24            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 24 */\n#define LL_RCC_PLLI2SM_DIV_25            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 25 */\n#define LL_RCC_PLLI2SM_DIV_26            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 26 */\n#define LL_RCC_PLLI2SM_DIV_27            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 27 */\n#define LL_RCC_PLLI2SM_DIV_28            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 28 */\n#define LL_RCC_PLLI2SM_DIV_29            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 29 */\n#define LL_RCC_PLLI2SM_DIV_30            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 30 */\n#define LL_RCC_PLLI2SM_DIV_31            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 31 */\n#define LL_RCC_PLLI2SM_DIV_32            (RCC_PLLI2SCFGR_PLLI2SM_5) /*!< PLLI2S division factor for PLLI2SM output by 32 */\n#define LL_RCC_PLLI2SM_DIV_33            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 33 */\n#define LL_RCC_PLLI2SM_DIV_34            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 34 */\n#define LL_RCC_PLLI2SM_DIV_35            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 35 */\n#define LL_RCC_PLLI2SM_DIV_36            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 36 */\n#define LL_RCC_PLLI2SM_DIV_37            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 37 */\n#define LL_RCC_PLLI2SM_DIV_38            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 38 */\n#define LL_RCC_PLLI2SM_DIV_39            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 39 */\n#define LL_RCC_PLLI2SM_DIV_40            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 40 */\n#define LL_RCC_PLLI2SM_DIV_41            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 41 */\n#define LL_RCC_PLLI2SM_DIV_42            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 42 */\n#define LL_RCC_PLLI2SM_DIV_43            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 43 */\n#define LL_RCC_PLLI2SM_DIV_44            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 44 */\n#define LL_RCC_PLLI2SM_DIV_45            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 45 */\n#define LL_RCC_PLLI2SM_DIV_46            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 46 */\n#define LL_RCC_PLLI2SM_DIV_47            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 47 */\n#define LL_RCC_PLLI2SM_DIV_48            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 48 */\n#define LL_RCC_PLLI2SM_DIV_49            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 49 */\n#define LL_RCC_PLLI2SM_DIV_50            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 50 */\n#define LL_RCC_PLLI2SM_DIV_51            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 51 */\n#define LL_RCC_PLLI2SM_DIV_52            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 52 */\n#define LL_RCC_PLLI2SM_DIV_53            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 53 */\n#define LL_RCC_PLLI2SM_DIV_54            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 54 */\n#define LL_RCC_PLLI2SM_DIV_55            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 55 */\n#define LL_RCC_PLLI2SM_DIV_56            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 56 */\n#define LL_RCC_PLLI2SM_DIV_57            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 57 */\n#define LL_RCC_PLLI2SM_DIV_58            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 58 */\n#define LL_RCC_PLLI2SM_DIV_59            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 59 */\n#define LL_RCC_PLLI2SM_DIV_60            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 60 */\n#define LL_RCC_PLLI2SM_DIV_61            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 61 */\n#define LL_RCC_PLLI2SM_DIV_62            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 62 */\n#define LL_RCC_PLLI2SM_DIV_63            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 63 */\n#else\n#define LL_RCC_PLLI2SM_DIV_2              LL_RCC_PLLM_DIV_2      /*!< PLLI2S division factor for PLLI2SM output by 2 */\n#define LL_RCC_PLLI2SM_DIV_3              LL_RCC_PLLM_DIV_3      /*!< PLLI2S division factor for PLLI2SM output by 3 */\n#define LL_RCC_PLLI2SM_DIV_4              LL_RCC_PLLM_DIV_4      /*!< PLLI2S division factor for PLLI2SM output by 4 */\n#define LL_RCC_PLLI2SM_DIV_5              LL_RCC_PLLM_DIV_5      /*!< PLLI2S division factor for PLLI2SM output by 5 */\n#define LL_RCC_PLLI2SM_DIV_6              LL_RCC_PLLM_DIV_6      /*!< PLLI2S division factor for PLLI2SM output by 6 */\n#define LL_RCC_PLLI2SM_DIV_7              LL_RCC_PLLM_DIV_7      /*!< PLLI2S division factor for PLLI2SM output by 7 */\n#define LL_RCC_PLLI2SM_DIV_8              LL_RCC_PLLM_DIV_8      /*!< PLLI2S division factor for PLLI2SM output by 8 */\n#define LL_RCC_PLLI2SM_DIV_9              LL_RCC_PLLM_DIV_9      /*!< PLLI2S division factor for PLLI2SM output by 9 */\n#define LL_RCC_PLLI2SM_DIV_10             LL_RCC_PLLM_DIV_10     /*!< PLLI2S division factor for PLLI2SM output by 10 */\n#define LL_RCC_PLLI2SM_DIV_11             LL_RCC_PLLM_DIV_11     /*!< PLLI2S division factor for PLLI2SM output by 11 */\n#define LL_RCC_PLLI2SM_DIV_12             LL_RCC_PLLM_DIV_12     /*!< PLLI2S division factor for PLLI2SM output by 12 */\n#define LL_RCC_PLLI2SM_DIV_13             LL_RCC_PLLM_DIV_13     /*!< PLLI2S division factor for PLLI2SM output by 13 */\n#define LL_RCC_PLLI2SM_DIV_14             LL_RCC_PLLM_DIV_14     /*!< PLLI2S division factor for PLLI2SM output by 14 */\n#define LL_RCC_PLLI2SM_DIV_15             LL_RCC_PLLM_DIV_15     /*!< PLLI2S division factor for PLLI2SM output by 15 */\n#define LL_RCC_PLLI2SM_DIV_16             LL_RCC_PLLM_DIV_16     /*!< PLLI2S division factor for PLLI2SM output by 16 */\n#define LL_RCC_PLLI2SM_DIV_17             LL_RCC_PLLM_DIV_17     /*!< PLLI2S division factor for PLLI2SM output by 17 */\n#define LL_RCC_PLLI2SM_DIV_18             LL_RCC_PLLM_DIV_18     /*!< PLLI2S division factor for PLLI2SM output by 18 */\n#define LL_RCC_PLLI2SM_DIV_19             LL_RCC_PLLM_DIV_19     /*!< PLLI2S division factor for PLLI2SM output by 19 */\n#define LL_RCC_PLLI2SM_DIV_20             LL_RCC_PLLM_DIV_20     /*!< PLLI2S division factor for PLLI2SM output by 20 */\n#define LL_RCC_PLLI2SM_DIV_21             LL_RCC_PLLM_DIV_21     /*!< PLLI2S division factor for PLLI2SM output by 21 */\n#define LL_RCC_PLLI2SM_DIV_22             LL_RCC_PLLM_DIV_22     /*!< PLLI2S division factor for PLLI2SM output by 22 */\n#define LL_RCC_PLLI2SM_DIV_23             LL_RCC_PLLM_DIV_23     /*!< PLLI2S division factor for PLLI2SM output by 23 */\n#define LL_RCC_PLLI2SM_DIV_24             LL_RCC_PLLM_DIV_24     /*!< PLLI2S division factor for PLLI2SM output by 24 */\n#define LL_RCC_PLLI2SM_DIV_25             LL_RCC_PLLM_DIV_25     /*!< PLLI2S division factor for PLLI2SM output by 25 */\n#define LL_RCC_PLLI2SM_DIV_26             LL_RCC_PLLM_DIV_26     /*!< PLLI2S division factor for PLLI2SM output by 26 */\n#define LL_RCC_PLLI2SM_DIV_27             LL_RCC_PLLM_DIV_27     /*!< PLLI2S division factor for PLLI2SM output by 27 */\n#define LL_RCC_PLLI2SM_DIV_28             LL_RCC_PLLM_DIV_28     /*!< PLLI2S division factor for PLLI2SM output by 28 */\n#define LL_RCC_PLLI2SM_DIV_29             LL_RCC_PLLM_DIV_29     /*!< PLLI2S division factor for PLLI2SM output by 29 */\n#define LL_RCC_PLLI2SM_DIV_30             LL_RCC_PLLM_DIV_30     /*!< PLLI2S division factor for PLLI2SM output by 30 */\n#define LL_RCC_PLLI2SM_DIV_31             LL_RCC_PLLM_DIV_31     /*!< PLLI2S division factor for PLLI2SM output by 31 */\n#define LL_RCC_PLLI2SM_DIV_32             LL_RCC_PLLM_DIV_32     /*!< PLLI2S division factor for PLLI2SM output by 32 */\n#define LL_RCC_PLLI2SM_DIV_33             LL_RCC_PLLM_DIV_33     /*!< PLLI2S division factor for PLLI2SM output by 33 */\n#define LL_RCC_PLLI2SM_DIV_34             LL_RCC_PLLM_DIV_34     /*!< PLLI2S division factor for PLLI2SM output by 34 */\n#define LL_RCC_PLLI2SM_DIV_35             LL_RCC_PLLM_DIV_35     /*!< PLLI2S division factor for PLLI2SM output by 35 */\n#define LL_RCC_PLLI2SM_DIV_36             LL_RCC_PLLM_DIV_36     /*!< PLLI2S division factor for PLLI2SM output by 36 */\n#define LL_RCC_PLLI2SM_DIV_37             LL_RCC_PLLM_DIV_37     /*!< PLLI2S division factor for PLLI2SM output by 37 */\n#define LL_RCC_PLLI2SM_DIV_38             LL_RCC_PLLM_DIV_38     /*!< PLLI2S division factor for PLLI2SM output by 38 */\n#define LL_RCC_PLLI2SM_DIV_39             LL_RCC_PLLM_DIV_39     /*!< PLLI2S division factor for PLLI2SM output by 39 */\n#define LL_RCC_PLLI2SM_DIV_40             LL_RCC_PLLM_DIV_40     /*!< PLLI2S division factor for PLLI2SM output by 40 */\n#define LL_RCC_PLLI2SM_DIV_41             LL_RCC_PLLM_DIV_41     /*!< PLLI2S division factor for PLLI2SM output by 41 */\n#define LL_RCC_PLLI2SM_DIV_42             LL_RCC_PLLM_DIV_42     /*!< PLLI2S division factor for PLLI2SM output by 42 */\n#define LL_RCC_PLLI2SM_DIV_43             LL_RCC_PLLM_DIV_43     /*!< PLLI2S division factor for PLLI2SM output by 43 */\n#define LL_RCC_PLLI2SM_DIV_44             LL_RCC_PLLM_DIV_44     /*!< PLLI2S division factor for PLLI2SM output by 44 */\n#define LL_RCC_PLLI2SM_DIV_45             LL_RCC_PLLM_DIV_45     /*!< PLLI2S division factor for PLLI2SM output by 45 */\n#define LL_RCC_PLLI2SM_DIV_46             LL_RCC_PLLM_DIV_46     /*!< PLLI2S division factor for PLLI2SM output by 46 */\n#define LL_RCC_PLLI2SM_DIV_47             LL_RCC_PLLM_DIV_47     /*!< PLLI2S division factor for PLLI2SM output by 47 */\n#define LL_RCC_PLLI2SM_DIV_48             LL_RCC_PLLM_DIV_48     /*!< PLLI2S division factor for PLLI2SM output by 48 */\n#define LL_RCC_PLLI2SM_DIV_49             LL_RCC_PLLM_DIV_49     /*!< PLLI2S division factor for PLLI2SM output by 49 */\n#define LL_RCC_PLLI2SM_DIV_50             LL_RCC_PLLM_DIV_50     /*!< PLLI2S division factor for PLLI2SM output by 50 */\n#define LL_RCC_PLLI2SM_DIV_51             LL_RCC_PLLM_DIV_51     /*!< PLLI2S division factor for PLLI2SM output by 51 */\n#define LL_RCC_PLLI2SM_DIV_52             LL_RCC_PLLM_DIV_52     /*!< PLLI2S division factor for PLLI2SM output by 52 */\n#define LL_RCC_PLLI2SM_DIV_53             LL_RCC_PLLM_DIV_53     /*!< PLLI2S division factor for PLLI2SM output by 53 */\n#define LL_RCC_PLLI2SM_DIV_54             LL_RCC_PLLM_DIV_54     /*!< PLLI2S division factor for PLLI2SM output by 54 */\n#define LL_RCC_PLLI2SM_DIV_55             LL_RCC_PLLM_DIV_55     /*!< PLLI2S division factor for PLLI2SM output by 55 */\n#define LL_RCC_PLLI2SM_DIV_56             LL_RCC_PLLM_DIV_56     /*!< PLLI2S division factor for PLLI2SM output by 56 */\n#define LL_RCC_PLLI2SM_DIV_57             LL_RCC_PLLM_DIV_57     /*!< PLLI2S division factor for PLLI2SM output by 57 */\n#define LL_RCC_PLLI2SM_DIV_58             LL_RCC_PLLM_DIV_58     /*!< PLLI2S division factor for PLLI2SM output by 58 */\n#define LL_RCC_PLLI2SM_DIV_59             LL_RCC_PLLM_DIV_59     /*!< PLLI2S division factor for PLLI2SM output by 59 */\n#define LL_RCC_PLLI2SM_DIV_60             LL_RCC_PLLM_DIV_60     /*!< PLLI2S division factor for PLLI2SM output by 60 */\n#define LL_RCC_PLLI2SM_DIV_61             LL_RCC_PLLM_DIV_61     /*!< PLLI2S division factor for PLLI2SM output by 61 */\n#define LL_RCC_PLLI2SM_DIV_62             LL_RCC_PLLM_DIV_62     /*!< PLLI2S division factor for PLLI2SM output by 62 */\n#define LL_RCC_PLLI2SM_DIV_63             LL_RCC_PLLM_DIV_63     /*!< PLLI2S division factor for PLLI2SM output by 63 */\n#endif /* RCC_PLLI2SCFGR_PLLI2SM */\n/**\n  * @}\n  */\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ)\n/** @defgroup RCC_LL_EC_PLLI2SQ  PLLI2SQ division factor (PLLI2SQ)\n  * @{\n  */\n#define LL_RCC_PLLI2SQ_DIV_2              RCC_PLLI2SCFGR_PLLI2SQ_1        /*!< PLLI2S division factor for PLLI2SQ output by 2 */\n#define LL_RCC_PLLI2SQ_DIV_3              (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 3 */\n#define LL_RCC_PLLI2SQ_DIV_4              RCC_PLLI2SCFGR_PLLI2SQ_2        /*!< PLLI2S division factor for PLLI2SQ output by 4 */\n#define LL_RCC_PLLI2SQ_DIV_5              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 5 */\n#define LL_RCC_PLLI2SQ_DIV_6              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1)        /*!< PLLI2S division factor for PLLI2SQ output by 6 */\n#define LL_RCC_PLLI2SQ_DIV_7              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 7 */\n#define LL_RCC_PLLI2SQ_DIV_8              RCC_PLLI2SCFGR_PLLI2SQ_3        /*!< PLLI2S division factor for PLLI2SQ output by 8 */\n#define LL_RCC_PLLI2SQ_DIV_9              (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 9 */\n#define LL_RCC_PLLI2SQ_DIV_10             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1)        /*!< PLLI2S division factor for PLLI2SQ output by 10 */\n#define LL_RCC_PLLI2SQ_DIV_11             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 11 */\n#define LL_RCC_PLLI2SQ_DIV_12             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2)        /*!< PLLI2S division factor for PLLI2SQ output by 12 */\n#define LL_RCC_PLLI2SQ_DIV_13             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 13 */\n#define LL_RCC_PLLI2SQ_DIV_14             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1)        /*!< PLLI2S division factor for PLLI2SQ output by 14 */\n#define LL_RCC_PLLI2SQ_DIV_15             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 15 */\n/**\n  * @}\n  */\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ */\n\n#if defined(RCC_DCKCFGR_PLLI2SDIVQ)\n/** @defgroup RCC_LL_EC_PLLI2SDIVQ  PLLI2SDIVQ division factor (PLLI2SDIVQ)\n  * @{\n  */\n#define LL_RCC_PLLI2SDIVQ_DIV_1           0x00000000U                        /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */\n#define LL_RCC_PLLI2SDIVQ_DIV_2           RCC_DCKCFGR_PLLI2SDIVQ_0          /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */\n#define LL_RCC_PLLI2SDIVQ_DIV_3           RCC_DCKCFGR_PLLI2SDIVQ_1          /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */\n#define LL_RCC_PLLI2SDIVQ_DIV_4           (RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */\n#define LL_RCC_PLLI2SDIVQ_DIV_5           RCC_DCKCFGR_PLLI2SDIVQ_2          /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */\n#define LL_RCC_PLLI2SDIVQ_DIV_6           (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */\n#define LL_RCC_PLLI2SDIVQ_DIV_7           (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */\n#define LL_RCC_PLLI2SDIVQ_DIV_8           (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */\n#define LL_RCC_PLLI2SDIVQ_DIV_9           RCC_DCKCFGR_PLLI2SDIVQ_3          /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */\n#define LL_RCC_PLLI2SDIVQ_DIV_10          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */\n#define LL_RCC_PLLI2SDIVQ_DIV_11          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */\n#define LL_RCC_PLLI2SDIVQ_DIV_12          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */\n#define LL_RCC_PLLI2SDIVQ_DIV_13          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */\n#define LL_RCC_PLLI2SDIVQ_DIV_14          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */\n#define LL_RCC_PLLI2SDIVQ_DIV_15          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */\n#define LL_RCC_PLLI2SDIVQ_DIV_16          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */\n#define LL_RCC_PLLI2SDIVQ_DIV_17          RCC_DCKCFGR_PLLI2SDIVQ_4          /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */\n#define LL_RCC_PLLI2SDIVQ_DIV_18          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */\n#define LL_RCC_PLLI2SDIVQ_DIV_19          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */\n#define LL_RCC_PLLI2SDIVQ_DIV_20          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */\n#define LL_RCC_PLLI2SDIVQ_DIV_21          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */\n#define LL_RCC_PLLI2SDIVQ_DIV_22          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */\n#define LL_RCC_PLLI2SDIVQ_DIV_23          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */\n#define LL_RCC_PLLI2SDIVQ_DIV_24          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */\n#define LL_RCC_PLLI2SDIVQ_DIV_25          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */\n#define LL_RCC_PLLI2SDIVQ_DIV_26          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */\n#define LL_RCC_PLLI2SDIVQ_DIV_27          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */\n#define LL_RCC_PLLI2SDIVQ_DIV_28          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */\n#define LL_RCC_PLLI2SDIVQ_DIV_29          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */\n#define LL_RCC_PLLI2SDIVQ_DIV_30          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */\n#define LL_RCC_PLLI2SDIVQ_DIV_31          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */\n#define LL_RCC_PLLI2SDIVQ_DIV_32          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */\n/**\n  * @}\n  */\n#endif /* RCC_DCKCFGR_PLLI2SDIVQ */\n\n#if defined(RCC_DCKCFGR_PLLI2SDIVR)\n/** @defgroup RCC_LL_EC_PLLI2SDIVR  PLLI2SDIVR division factor (PLLI2SDIVR)\n  * @{\n  */\n#define LL_RCC_PLLI2SDIVR_DIV_1           (RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 1 */\n#define LL_RCC_PLLI2SDIVR_DIV_2           (RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 2 */\n#define LL_RCC_PLLI2SDIVR_DIV_3           (RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 3 */\n#define LL_RCC_PLLI2SDIVR_DIV_4           (RCC_DCKCFGR_PLLI2SDIVR_2)        /*!< PLLI2S division factor for PLLI2SDIVR output by 4 */\n#define LL_RCC_PLLI2SDIVR_DIV_5           (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 5 */\n#define LL_RCC_PLLI2SDIVR_DIV_6           (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 6 */\n#define LL_RCC_PLLI2SDIVR_DIV_7           (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 7 */\n#define LL_RCC_PLLI2SDIVR_DIV_8           (RCC_DCKCFGR_PLLI2SDIVR_3)        /*!< PLLI2S division factor for PLLI2SDIVR output by 8 */\n#define LL_RCC_PLLI2SDIVR_DIV_9           (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 9 */\n#define LL_RCC_PLLI2SDIVR_DIV_10          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 10 */\n#define LL_RCC_PLLI2SDIVR_DIV_11          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 11 */\n#define LL_RCC_PLLI2SDIVR_DIV_12          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2)        /*!< PLLI2S division factor for PLLI2SDIVR output by 12 */\n#define LL_RCC_PLLI2SDIVR_DIV_13          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 13 */\n#define LL_RCC_PLLI2SDIVR_DIV_14          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 14 */\n#define LL_RCC_PLLI2SDIVR_DIV_15          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 15 */\n#define LL_RCC_PLLI2SDIVR_DIV_16          (RCC_DCKCFGR_PLLI2SDIVR_4)             /*!< PLLI2S division factor for PLLI2SDIVR output by 16 */\n#define LL_RCC_PLLI2SDIVR_DIV_17          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 17 */\n#define LL_RCC_PLLI2SDIVR_DIV_18          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 18 */\n#define LL_RCC_PLLI2SDIVR_DIV_19          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 19 */\n#define LL_RCC_PLLI2SDIVR_DIV_20          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2)        /*!< PLLI2S division factor for PLLI2SDIVR output by 20 */\n#define LL_RCC_PLLI2SDIVR_DIV_21          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 21 */\n#define LL_RCC_PLLI2SDIVR_DIV_22          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 22 */\n#define LL_RCC_PLLI2SDIVR_DIV_23          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 23 */\n#define LL_RCC_PLLI2SDIVR_DIV_24          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3)        /*!< PLLI2S division factor for PLLI2SDIVR output by 24 */\n#define LL_RCC_PLLI2SDIVR_DIV_25          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 25 */\n#define LL_RCC_PLLI2SDIVR_DIV_26          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 26 */\n#define LL_RCC_PLLI2SDIVR_DIV_27          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 27 */\n#define LL_RCC_PLLI2SDIVR_DIV_28          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2)        /*!< PLLI2S division factor for PLLI2SDIVR output by 28 */\n#define LL_RCC_PLLI2SDIVR_DIV_29          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 29 */\n#define LL_RCC_PLLI2SDIVR_DIV_30          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 30 */\n#define LL_RCC_PLLI2SDIVR_DIV_31          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 31 */\n/**\n  * @}\n  */\n#endif /* RCC_DCKCFGR_PLLI2SDIVR */\n\n/** @defgroup RCC_LL_EC_PLLI2SR  PLLI2SR division factor (PLLI2SR)\n  * @{\n  */\n#define LL_RCC_PLLI2SR_DIV_2              RCC_PLLI2SCFGR_PLLI2SR_1                                     /*!< PLLI2S division factor for PLLI2SR output by 2 */\n#define LL_RCC_PLLI2SR_DIV_3              (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0)        /*!< PLLI2S division factor for PLLI2SR output by 3 */\n#define LL_RCC_PLLI2SR_DIV_4              RCC_PLLI2SCFGR_PLLI2SR_2                                     /*!< PLLI2S division factor for PLLI2SR output by 4 */\n#define LL_RCC_PLLI2SR_DIV_5              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0)        /*!< PLLI2S division factor for PLLI2SR output by 5 */\n#define LL_RCC_PLLI2SR_DIV_6              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1)        /*!< PLLI2S division factor for PLLI2SR output by 6 */\n#define LL_RCC_PLLI2SR_DIV_7              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0)        /*!< PLLI2S division factor for PLLI2SR output by 7 */\n/**\n  * @}\n  */\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SP)\n/** @defgroup RCC_LL_EC_PLLI2SP  PLLI2SP division factor (PLLI2SP)\n  * @{\n  */\n#define LL_RCC_PLLI2SP_DIV_2              0x00000000U            /*!< PLLI2S division factor for PLLI2SP output by 2 */\n#define LL_RCC_PLLI2SP_DIV_4              RCC_PLLI2SCFGR_PLLI2SP_0        /*!< PLLI2S division factor for PLLI2SP output by 4 */\n#define LL_RCC_PLLI2SP_DIV_6              RCC_PLLI2SCFGR_PLLI2SP_1        /*!< PLLI2S division factor for PLLI2SP output by 6 */\n#define LL_RCC_PLLI2SP_DIV_8              (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0)        /*!< PLLI2S division factor for PLLI2SP output by 8 */\n/**\n  * @}\n  */\n#endif /* RCC_PLLI2SCFGR_PLLI2SP */\n#endif /* RCC_PLLI2S_SUPPORT */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n/** @defgroup RCC_LL_EC_PLLSAIM  PLLSAIM division factor (PLLSAIM or PLLM)\n  * @{\n  */\n#if defined(RCC_PLLSAICFGR_PLLSAIM)\n#define LL_RCC_PLLSAIM_DIV_2             (RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 2 */\n#define LL_RCC_PLLSAIM_DIV_3             (RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 3 */\n#define LL_RCC_PLLSAIM_DIV_4             (RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 4 */\n#define LL_RCC_PLLSAIM_DIV_5             (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 5 */\n#define LL_RCC_PLLSAIM_DIV_6             (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 6 */\n#define LL_RCC_PLLSAIM_DIV_7             (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 7 */\n#define LL_RCC_PLLSAIM_DIV_8             (RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 8 */\n#define LL_RCC_PLLSAIM_DIV_9             (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 9 */\n#define LL_RCC_PLLSAIM_DIV_10            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 10 */\n#define LL_RCC_PLLSAIM_DIV_11            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 11 */\n#define LL_RCC_PLLSAIM_DIV_12            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 12 */\n#define LL_RCC_PLLSAIM_DIV_13            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 13 */\n#define LL_RCC_PLLSAIM_DIV_14            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 14 */\n#define LL_RCC_PLLSAIM_DIV_15            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 15 */\n#define LL_RCC_PLLSAIM_DIV_16            (RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 16 */\n#define LL_RCC_PLLSAIM_DIV_17            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 17 */\n#define LL_RCC_PLLSAIM_DIV_18            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 18 */\n#define LL_RCC_PLLSAIM_DIV_19            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 19 */\n#define LL_RCC_PLLSAIM_DIV_20            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 20 */\n#define LL_RCC_PLLSAIM_DIV_21            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 21 */\n#define LL_RCC_PLLSAIM_DIV_22            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 22 */\n#define LL_RCC_PLLSAIM_DIV_23            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 23 */\n#define LL_RCC_PLLSAIM_DIV_24            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 24 */\n#define LL_RCC_PLLSAIM_DIV_25            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 25 */\n#define LL_RCC_PLLSAIM_DIV_26            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 26 */\n#define LL_RCC_PLLSAIM_DIV_27            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 27 */\n#define LL_RCC_PLLSAIM_DIV_28            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 28 */\n#define LL_RCC_PLLSAIM_DIV_29            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 29 */\n#define LL_RCC_PLLSAIM_DIV_30            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 30 */\n#define LL_RCC_PLLSAIM_DIV_31            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 31 */\n#define LL_RCC_PLLSAIM_DIV_32            (RCC_PLLSAICFGR_PLLSAIM_5) /*!< PLLSAI division factor for PLLSAIM output by 32 */\n#define LL_RCC_PLLSAIM_DIV_33            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 33 */\n#define LL_RCC_PLLSAIM_DIV_34            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 34 */\n#define LL_RCC_PLLSAIM_DIV_35            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 35 */\n#define LL_RCC_PLLSAIM_DIV_36            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 36 */\n#define LL_RCC_PLLSAIM_DIV_37            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 37 */\n#define LL_RCC_PLLSAIM_DIV_38            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 38 */\n#define LL_RCC_PLLSAIM_DIV_39            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 39 */\n#define LL_RCC_PLLSAIM_DIV_40            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 40 */\n#define LL_RCC_PLLSAIM_DIV_41            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 41 */\n#define LL_RCC_PLLSAIM_DIV_42            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 42 */\n#define LL_RCC_PLLSAIM_DIV_43            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 43 */\n#define LL_RCC_PLLSAIM_DIV_44            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 44 */\n#define LL_RCC_PLLSAIM_DIV_45            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 45 */\n#define LL_RCC_PLLSAIM_DIV_46            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 46 */\n#define LL_RCC_PLLSAIM_DIV_47            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 47 */\n#define LL_RCC_PLLSAIM_DIV_48            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 48 */\n#define LL_RCC_PLLSAIM_DIV_49            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 49 */\n#define LL_RCC_PLLSAIM_DIV_50            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 50 */\n#define LL_RCC_PLLSAIM_DIV_51            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 51 */\n#define LL_RCC_PLLSAIM_DIV_52            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 52 */\n#define LL_RCC_PLLSAIM_DIV_53            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 53 */\n#define LL_RCC_PLLSAIM_DIV_54            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 54 */\n#define LL_RCC_PLLSAIM_DIV_55            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 55 */\n#define LL_RCC_PLLSAIM_DIV_56            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 56 */\n#define LL_RCC_PLLSAIM_DIV_57            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 57 */\n#define LL_RCC_PLLSAIM_DIV_58            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 58 */\n#define LL_RCC_PLLSAIM_DIV_59            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 59 */\n#define LL_RCC_PLLSAIM_DIV_60            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 60 */\n#define LL_RCC_PLLSAIM_DIV_61            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 61 */\n#define LL_RCC_PLLSAIM_DIV_62            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 62 */\n#define LL_RCC_PLLSAIM_DIV_63            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 63 */\n#else\n#define LL_RCC_PLLSAIM_DIV_2              LL_RCC_PLLM_DIV_2      /*!< PLLSAI division factor for PLLSAIM output by 2 */\n#define LL_RCC_PLLSAIM_DIV_3              LL_RCC_PLLM_DIV_3      /*!< PLLSAI division factor for PLLSAIM output by 3 */\n#define LL_RCC_PLLSAIM_DIV_4              LL_RCC_PLLM_DIV_4      /*!< PLLSAI division factor for PLLSAIM output by 4 */\n#define LL_RCC_PLLSAIM_DIV_5              LL_RCC_PLLM_DIV_5      /*!< PLLSAI division factor for PLLSAIM output by 5 */\n#define LL_RCC_PLLSAIM_DIV_6              LL_RCC_PLLM_DIV_6      /*!< PLLSAI division factor for PLLSAIM output by 6 */\n#define LL_RCC_PLLSAIM_DIV_7              LL_RCC_PLLM_DIV_7      /*!< PLLSAI division factor for PLLSAIM output by 7 */\n#define LL_RCC_PLLSAIM_DIV_8              LL_RCC_PLLM_DIV_8      /*!< PLLSAI division factor for PLLSAIM output by 8 */\n#define LL_RCC_PLLSAIM_DIV_9              LL_RCC_PLLM_DIV_9      /*!< PLLSAI division factor for PLLSAIM output by 9 */\n#define LL_RCC_PLLSAIM_DIV_10             LL_RCC_PLLM_DIV_10     /*!< PLLSAI division factor for PLLSAIM output by 10 */\n#define LL_RCC_PLLSAIM_DIV_11             LL_RCC_PLLM_DIV_11     /*!< PLLSAI division factor for PLLSAIM output by 11 */\n#define LL_RCC_PLLSAIM_DIV_12             LL_RCC_PLLM_DIV_12     /*!< PLLSAI division factor for PLLSAIM output by 12 */\n#define LL_RCC_PLLSAIM_DIV_13             LL_RCC_PLLM_DIV_13     /*!< PLLSAI division factor for PLLSAIM output by 13 */\n#define LL_RCC_PLLSAIM_DIV_14             LL_RCC_PLLM_DIV_14     /*!< PLLSAI division factor for PLLSAIM output by 14 */\n#define LL_RCC_PLLSAIM_DIV_15             LL_RCC_PLLM_DIV_15     /*!< PLLSAI division factor for PLLSAIM output by 15 */\n#define LL_RCC_PLLSAIM_DIV_16             LL_RCC_PLLM_DIV_16     /*!< PLLSAI division factor for PLLSAIM output by 16 */\n#define LL_RCC_PLLSAIM_DIV_17             LL_RCC_PLLM_DIV_17     /*!< PLLSAI division factor for PLLSAIM output by 17 */\n#define LL_RCC_PLLSAIM_DIV_18             LL_RCC_PLLM_DIV_18     /*!< PLLSAI division factor for PLLSAIM output by 18 */\n#define LL_RCC_PLLSAIM_DIV_19             LL_RCC_PLLM_DIV_19     /*!< PLLSAI division factor for PLLSAIM output by 19 */\n#define LL_RCC_PLLSAIM_DIV_20             LL_RCC_PLLM_DIV_20     /*!< PLLSAI division factor for PLLSAIM output by 20 */\n#define LL_RCC_PLLSAIM_DIV_21             LL_RCC_PLLM_DIV_21     /*!< PLLSAI division factor for PLLSAIM output by 21 */\n#define LL_RCC_PLLSAIM_DIV_22             LL_RCC_PLLM_DIV_22     /*!< PLLSAI division factor for PLLSAIM output by 22 */\n#define LL_RCC_PLLSAIM_DIV_23             LL_RCC_PLLM_DIV_23     /*!< PLLSAI division factor for PLLSAIM output by 23 */\n#define LL_RCC_PLLSAIM_DIV_24             LL_RCC_PLLM_DIV_24     /*!< PLLSAI division factor for PLLSAIM output by 24 */\n#define LL_RCC_PLLSAIM_DIV_25             LL_RCC_PLLM_DIV_25     /*!< PLLSAI division factor for PLLSAIM output by 25 */\n#define LL_RCC_PLLSAIM_DIV_26             LL_RCC_PLLM_DIV_26     /*!< PLLSAI division factor for PLLSAIM output by 26 */\n#define LL_RCC_PLLSAIM_DIV_27             LL_RCC_PLLM_DIV_27     /*!< PLLSAI division factor for PLLSAIM output by 27 */\n#define LL_RCC_PLLSAIM_DIV_28             LL_RCC_PLLM_DIV_28     /*!< PLLSAI division factor for PLLSAIM output by 28 */\n#define LL_RCC_PLLSAIM_DIV_29             LL_RCC_PLLM_DIV_29     /*!< PLLSAI division factor for PLLSAIM output by 29 */\n#define LL_RCC_PLLSAIM_DIV_30             LL_RCC_PLLM_DIV_30     /*!< PLLSAI division factor for PLLSAIM output by 30 */\n#define LL_RCC_PLLSAIM_DIV_31             LL_RCC_PLLM_DIV_31     /*!< PLLSAI division factor for PLLSAIM output by 31 */\n#define LL_RCC_PLLSAIM_DIV_32             LL_RCC_PLLM_DIV_32     /*!< PLLSAI division factor for PLLSAIM output by 32 */\n#define LL_RCC_PLLSAIM_DIV_33             LL_RCC_PLLM_DIV_33     /*!< PLLSAI division factor for PLLSAIM output by 33 */\n#define LL_RCC_PLLSAIM_DIV_34             LL_RCC_PLLM_DIV_34     /*!< PLLSAI division factor for PLLSAIM output by 34 */\n#define LL_RCC_PLLSAIM_DIV_35             LL_RCC_PLLM_DIV_35     /*!< PLLSAI division factor for PLLSAIM output by 35 */\n#define LL_RCC_PLLSAIM_DIV_36             LL_RCC_PLLM_DIV_36     /*!< PLLSAI division factor for PLLSAIM output by 36 */\n#define LL_RCC_PLLSAIM_DIV_37             LL_RCC_PLLM_DIV_37     /*!< PLLSAI division factor for PLLSAIM output by 37 */\n#define LL_RCC_PLLSAIM_DIV_38             LL_RCC_PLLM_DIV_38     /*!< PLLSAI division factor for PLLSAIM output by 38 */\n#define LL_RCC_PLLSAIM_DIV_39             LL_RCC_PLLM_DIV_39     /*!< PLLSAI division factor for PLLSAIM output by 39 */\n#define LL_RCC_PLLSAIM_DIV_40             LL_RCC_PLLM_DIV_40     /*!< PLLSAI division factor for PLLSAIM output by 40 */\n#define LL_RCC_PLLSAIM_DIV_41             LL_RCC_PLLM_DIV_41     /*!< PLLSAI division factor for PLLSAIM output by 41 */\n#define LL_RCC_PLLSAIM_DIV_42             LL_RCC_PLLM_DIV_42     /*!< PLLSAI division factor for PLLSAIM output by 42 */\n#define LL_RCC_PLLSAIM_DIV_43             LL_RCC_PLLM_DIV_43     /*!< PLLSAI division factor for PLLSAIM output by 43 */\n#define LL_RCC_PLLSAIM_DIV_44             LL_RCC_PLLM_DIV_44     /*!< PLLSAI division factor for PLLSAIM output by 44 */\n#define LL_RCC_PLLSAIM_DIV_45             LL_RCC_PLLM_DIV_45     /*!< PLLSAI division factor for PLLSAIM output by 45 */\n#define LL_RCC_PLLSAIM_DIV_46             LL_RCC_PLLM_DIV_46     /*!< PLLSAI division factor for PLLSAIM output by 46 */\n#define LL_RCC_PLLSAIM_DIV_47             LL_RCC_PLLM_DIV_47     /*!< PLLSAI division factor for PLLSAIM output by 47 */\n#define LL_RCC_PLLSAIM_DIV_48             LL_RCC_PLLM_DIV_48     /*!< PLLSAI division factor for PLLSAIM output by 48 */\n#define LL_RCC_PLLSAIM_DIV_49             LL_RCC_PLLM_DIV_49     /*!< PLLSAI division factor for PLLSAIM output by 49 */\n#define LL_RCC_PLLSAIM_DIV_50             LL_RCC_PLLM_DIV_50     /*!< PLLSAI division factor for PLLSAIM output by 50 */\n#define LL_RCC_PLLSAIM_DIV_51             LL_RCC_PLLM_DIV_51     /*!< PLLSAI division factor for PLLSAIM output by 51 */\n#define LL_RCC_PLLSAIM_DIV_52             LL_RCC_PLLM_DIV_52     /*!< PLLSAI division factor for PLLSAIM output by 52 */\n#define LL_RCC_PLLSAIM_DIV_53             LL_RCC_PLLM_DIV_53     /*!< PLLSAI division factor for PLLSAIM output by 53 */\n#define LL_RCC_PLLSAIM_DIV_54             LL_RCC_PLLM_DIV_54     /*!< PLLSAI division factor for PLLSAIM output by 54 */\n#define LL_RCC_PLLSAIM_DIV_55             LL_RCC_PLLM_DIV_55     /*!< PLLSAI division factor for PLLSAIM output by 55 */\n#define LL_RCC_PLLSAIM_DIV_56             LL_RCC_PLLM_DIV_56     /*!< PLLSAI division factor for PLLSAIM output by 56 */\n#define LL_RCC_PLLSAIM_DIV_57             LL_RCC_PLLM_DIV_57     /*!< PLLSAI division factor for PLLSAIM output by 57 */\n#define LL_RCC_PLLSAIM_DIV_58             LL_RCC_PLLM_DIV_58     /*!< PLLSAI division factor for PLLSAIM output by 58 */\n#define LL_RCC_PLLSAIM_DIV_59             LL_RCC_PLLM_DIV_59     /*!< PLLSAI division factor for PLLSAIM output by 59 */\n#define LL_RCC_PLLSAIM_DIV_60             LL_RCC_PLLM_DIV_60     /*!< PLLSAI division factor for PLLSAIM output by 60 */\n#define LL_RCC_PLLSAIM_DIV_61             LL_RCC_PLLM_DIV_61     /*!< PLLSAI division factor for PLLSAIM output by 61 */\n#define LL_RCC_PLLSAIM_DIV_62             LL_RCC_PLLM_DIV_62     /*!< PLLSAI division factor for PLLSAIM output by 62 */\n#define LL_RCC_PLLSAIM_DIV_63             LL_RCC_PLLM_DIV_63     /*!< PLLSAI division factor for PLLSAIM output by 63 */\n#endif /* RCC_PLLSAICFGR_PLLSAIM */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_PLLSAIQ  PLLSAIQ division factor (PLLSAIQ)\n  * @{\n  */\n#define LL_RCC_PLLSAIQ_DIV_2              RCC_PLLSAICFGR_PLLSAIQ_1        /*!< PLLSAI division factor for PLLSAIQ output by 2 */\n#define LL_RCC_PLLSAIQ_DIV_3              (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 3 */\n#define LL_RCC_PLLSAIQ_DIV_4              RCC_PLLSAICFGR_PLLSAIQ_2        /*!< PLLSAI division factor for PLLSAIQ output by 4 */\n#define LL_RCC_PLLSAIQ_DIV_5              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 5 */\n#define LL_RCC_PLLSAIQ_DIV_6              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1)        /*!< PLLSAI division factor for PLLSAIQ output by 6 */\n#define LL_RCC_PLLSAIQ_DIV_7              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 7 */\n#define LL_RCC_PLLSAIQ_DIV_8              RCC_PLLSAICFGR_PLLSAIQ_3        /*!< PLLSAI division factor for PLLSAIQ output by 8 */\n#define LL_RCC_PLLSAIQ_DIV_9              (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 9 */\n#define LL_RCC_PLLSAIQ_DIV_10             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1)        /*!< PLLSAI division factor for PLLSAIQ output by 10 */\n#define LL_RCC_PLLSAIQ_DIV_11             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 11 */\n#define LL_RCC_PLLSAIQ_DIV_12             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2)        /*!< PLLSAI division factor for PLLSAIQ output by 12 */\n#define LL_RCC_PLLSAIQ_DIV_13             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 13 */\n#define LL_RCC_PLLSAIQ_DIV_14             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1)        /*!< PLLSAI division factor for PLLSAIQ output by 14 */\n#define LL_RCC_PLLSAIQ_DIV_15             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 15 */\n/**\n  * @}\n  */\n\n#if defined(RCC_DCKCFGR_PLLSAIDIVQ)\n/** @defgroup RCC_LL_EC_PLLSAIDIVQ  PLLSAIDIVQ division factor (PLLSAIDIVQ)\n  * @{\n  */\n#define LL_RCC_PLLSAIDIVQ_DIV_1           0x00000000U               /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */\n#define LL_RCC_PLLSAIDIVQ_DIV_2           RCC_DCKCFGR_PLLSAIDIVQ_0          /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */\n#define LL_RCC_PLLSAIDIVQ_DIV_3           RCC_DCKCFGR_PLLSAIDIVQ_1          /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */\n#define LL_RCC_PLLSAIDIVQ_DIV_4           (RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */\n#define LL_RCC_PLLSAIDIVQ_DIV_5           RCC_DCKCFGR_PLLSAIDIVQ_2          /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */\n#define LL_RCC_PLLSAIDIVQ_DIV_6           (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */\n#define LL_RCC_PLLSAIDIVQ_DIV_7           (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */\n#define LL_RCC_PLLSAIDIVQ_DIV_8           (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */\n#define LL_RCC_PLLSAIDIVQ_DIV_9           RCC_DCKCFGR_PLLSAIDIVQ_3          /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */\n#define LL_RCC_PLLSAIDIVQ_DIV_10          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */\n#define LL_RCC_PLLSAIDIVQ_DIV_11          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */\n#define LL_RCC_PLLSAIDIVQ_DIV_12          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */\n#define LL_RCC_PLLSAIDIVQ_DIV_13          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */\n#define LL_RCC_PLLSAIDIVQ_DIV_14          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */\n#define LL_RCC_PLLSAIDIVQ_DIV_15          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */\n#define LL_RCC_PLLSAIDIVQ_DIV_16          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */\n#define LL_RCC_PLLSAIDIVQ_DIV_17          RCC_DCKCFGR_PLLSAIDIVQ_4         /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */\n#define LL_RCC_PLLSAIDIVQ_DIV_18          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */\n#define LL_RCC_PLLSAIDIVQ_DIV_19          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */\n#define LL_RCC_PLLSAIDIVQ_DIV_20          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */\n#define LL_RCC_PLLSAIDIVQ_DIV_21          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */\n#define LL_RCC_PLLSAIDIVQ_DIV_22          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */\n#define LL_RCC_PLLSAIDIVQ_DIV_23          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */\n#define LL_RCC_PLLSAIDIVQ_DIV_24          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */\n#define LL_RCC_PLLSAIDIVQ_DIV_25          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */\n#define LL_RCC_PLLSAIDIVQ_DIV_26          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */\n#define LL_RCC_PLLSAIDIVQ_DIV_27          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */\n#define LL_RCC_PLLSAIDIVQ_DIV_28          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */\n#define LL_RCC_PLLSAIDIVQ_DIV_29          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */\n#define LL_RCC_PLLSAIDIVQ_DIV_30          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */\n#define LL_RCC_PLLSAIDIVQ_DIV_31          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */\n#define LL_RCC_PLLSAIDIVQ_DIV_32          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */\n/**\n  * @}\n  */\n#endif /* RCC_DCKCFGR_PLLSAIDIVQ */\n\n#if defined(RCC_PLLSAICFGR_PLLSAIR)\n/** @defgroup RCC_LL_EC_PLLSAIR  PLLSAIR division factor (PLLSAIR)\n  * @{\n  */\n#define LL_RCC_PLLSAIR_DIV_2              RCC_PLLSAICFGR_PLLSAIR_1                                     /*!< PLLSAI division factor for PLLSAIR output by 2 */\n#define LL_RCC_PLLSAIR_DIV_3              (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0)        /*!< PLLSAI division factor for PLLSAIR output by 3 */\n#define LL_RCC_PLLSAIR_DIV_4              RCC_PLLSAICFGR_PLLSAIR_2                                     /*!< PLLSAI division factor for PLLSAIR output by 4 */\n#define LL_RCC_PLLSAIR_DIV_5              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0)        /*!< PLLSAI division factor for PLLSAIR output by 5 */\n#define LL_RCC_PLLSAIR_DIV_6              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1)        /*!< PLLSAI division factor for PLLSAIR output by 6 */\n#define LL_RCC_PLLSAIR_DIV_7              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0)        /*!< PLLSAI division factor for PLLSAIR output by 7 */\n/**\n  * @}\n  */\n#endif /* RCC_PLLSAICFGR_PLLSAIR */\n\n#if defined(RCC_DCKCFGR_PLLSAIDIVR)\n/** @defgroup RCC_LL_EC_PLLSAIDIVR  PLLSAIDIVR division factor (PLLSAIDIVR)\n  * @{\n  */\n#define LL_RCC_PLLSAIDIVR_DIV_2           0x00000000U             /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */\n#define LL_RCC_PLLSAIDIVR_DIV_4           RCC_DCKCFGR_PLLSAIDIVR_0        /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */\n#define LL_RCC_PLLSAIDIVR_DIV_8           RCC_DCKCFGR_PLLSAIDIVR_1        /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */\n#define LL_RCC_PLLSAIDIVR_DIV_16          (RCC_DCKCFGR_PLLSAIDIVR_1 | RCC_DCKCFGR_PLLSAIDIVR_0)        /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */\n/**\n  * @}\n  */\n#endif /* RCC_DCKCFGR_PLLSAIDIVR */\n\n#if defined(RCC_PLLSAICFGR_PLLSAIP)\n/** @defgroup RCC_LL_EC_PLLSAIP  PLLSAIP division factor (PLLSAIP)\n  * @{\n  */\n#define LL_RCC_PLLSAIP_DIV_2              0x00000000U               /*!< PLLSAI division factor for PLLSAIP output by 2 */\n#define LL_RCC_PLLSAIP_DIV_4              RCC_PLLSAICFGR_PLLSAIP_0        /*!< PLLSAI division factor for PLLSAIP output by 4 */\n#define LL_RCC_PLLSAIP_DIV_6              RCC_PLLSAICFGR_PLLSAIP_1        /*!< PLLSAI division factor for PLLSAIP output by 6 */\n#define LL_RCC_PLLSAIP_DIV_8              (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0)        /*!< PLLSAI division factor for PLLSAIP output by 8 */\n/**\n  * @}\n  */\n#endif /* RCC_PLLSAICFGR_PLLSAIP */\n#endif /* RCC_PLLSAI_SUPPORT */\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros\n  * @{\n  */\n\n/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros\n  * @{\n  */\n\n/**\n  * @brief  Write a value in RCC register\n  * @param  __REG__ Register to be written\n  * @param  __VALUE__ Value to be written in the register\n  * @retval None\n  */\n#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))\n\n/**\n  * @brief  Read a value in RCC register\n  * @param  __REG__ Register to be read\n  * @retval Register value\n  */\n#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies\n  * @{\n  */\n\n/**\n  * @brief  Helper macro to calculate the PLLCLK frequency on system domain\n  * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  __PLLN__ Between 50/192(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  __PLLP__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLP_DIV_2\n  *         @arg @ref LL_RCC_PLLP_DIV_4\n  *         @arg @ref LL_RCC_PLLP_DIV_6\n  *         @arg @ref LL_RCC_PLLP_DIV_8\n  * @retval PLL clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \\\n                   ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))\n\n#if defined(RCC_PLLR_SYSCLK_SUPPORT)\n/**\n  * @brief  Helper macro to calculate the PLLRCLK frequency on system domain\n  * @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  __PLLN__ Between 50 and 432\n  * @param  __PLLR__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_3\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_5\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_7\n  * @retval PLL clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \\\n                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))\n\n#endif /* RCC_PLLR_SYSCLK_SUPPORT */\n\n/**\n  * @brief  Helper macro to calculate the PLLCLK frequency used on 48M domain\n  * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  __PLLN__ Between 50/192(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  __PLLQ__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLQ_DIV_2\n  *         @arg @ref LL_RCC_PLLQ_DIV_3\n  *         @arg @ref LL_RCC_PLLQ_DIV_4\n  *         @arg @ref LL_RCC_PLLQ_DIV_5\n  *         @arg @ref LL_RCC_PLLQ_DIV_6\n  *         @arg @ref LL_RCC_PLLQ_DIV_7\n  *         @arg @ref LL_RCC_PLLQ_DIV_8\n  *         @arg @ref LL_RCC_PLLQ_DIV_9\n  *         @arg @ref LL_RCC_PLLQ_DIV_10\n  *         @arg @ref LL_RCC_PLLQ_DIV_11\n  *         @arg @ref LL_RCC_PLLQ_DIV_12\n  *         @arg @ref LL_RCC_PLLQ_DIV_13\n  *         @arg @ref LL_RCC_PLLQ_DIV_14\n  *         @arg @ref LL_RCC_PLLQ_DIV_15\n  * @retval PLL clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \\\n                   ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))\n\n#if defined(DSI)\n/**\n  * @brief  Helper macro to calculate the PLLCLK frequency used on DSI\n  * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  __PLLN__ Between 50 and 432\n  * @param  __PLLR__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_3\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_5\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_7\n  * @retval PLL clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \\\n                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))\n#endif /* DSI */\n\n#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)\n/**\n  * @brief  Helper macro to calculate the PLLCLK frequency used on I2S\n  * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  __PLLN__ Between 50 and 432\n  * @param  __PLLR__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_3\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_5\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_7\n  * @retval PLL clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \\\n                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))\n#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */\n\n#if defined(SPDIFRX)\n/**\n  * @brief  Helper macro to calculate the PLLCLK frequency used on SPDIFRX\n  * @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  __PLLN__ Between 50 and 432\n  * @param  __PLLR__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_3\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_5\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_7\n  * @retval PLL clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \\\n                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))\n#endif /* SPDIFRX */\n\n#if defined(RCC_PLLCFGR_PLLR)\n#if defined(SAI1)\n/**\n  * @brief  Helper macro to calculate the PLLCLK frequency used on SAI\n  * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  __PLLN__ Between 50 and 432\n  * @param  __PLLR__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_3\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_5\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_7\n  * @param  __PLLDIVR__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval PLL clock frequency (in Hz)\n  */\n#if defined(RCC_DCKCFGR_PLLDIVR)\n#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \\\n                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos ))\n#else\n#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \\\n                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))\n#endif /* RCC_DCKCFGR_PLLDIVR */\n#endif /* SAI1 */\n#endif /* RCC_PLLCFGR_PLLR */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n/**\n  * @brief  Helper macro to calculate the PLLSAI frequency used for SAI domain\n  * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),\n  *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_15\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_16\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_17\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_18\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_19\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_20\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_21\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_22\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_23\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_24\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_25\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_26\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_27\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_28\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_29\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_30\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_31\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_32\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_33\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_34\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_35\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_36\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_37\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_38\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_39\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_40\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_41\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_42\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_43\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_44\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_45\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_46\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_47\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_48\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_49\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_50\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_51\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_52\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_53\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_54\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_55\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_56\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_57\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_58\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_59\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_60\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_61\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_62\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_63\n  * @param  __PLLSAIN__ Between 49/50(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  __PLLSAIQ__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_15\n  * @param  __PLLSAIDIVQ__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32\n  * @retval PLLSAI clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \\\n                   (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U)))\n\n#if defined(RCC_PLLSAICFGR_PLLSAIP)\n/**\n  * @brief  Helper macro to calculate the PLLSAI frequency used on 48Mhz domain\n  * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),\n  *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_15\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_16\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_17\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_18\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_19\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_20\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_21\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_22\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_23\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_24\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_25\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_26\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_27\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_28\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_29\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_30\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_31\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_32\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_33\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_34\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_35\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_36\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_37\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_38\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_39\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_40\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_41\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_42\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_43\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_44\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_45\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_46\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_47\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_48\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_49\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_50\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_51\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_52\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_53\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_54\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_55\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_56\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_57\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_58\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_59\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_60\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_61\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_62\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_63\n  * @param  __PLLSAIN__ Between 50 and 432\n  * @param  __PLLSAIP__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_8\n  * @retval PLLSAI clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \\\n                   ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U))\n#endif /* RCC_PLLSAICFGR_PLLSAIP */\n\n#if defined(LTDC)\n/**\n  * @brief  Helper macro to calculate the PLLSAI frequency used for LTDC domain\n  * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),\n  *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_15\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_16\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_17\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_18\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_19\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_20\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_21\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_22\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_23\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_24\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_25\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_26\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_27\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_28\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_29\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_30\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_31\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_32\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_33\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_34\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_35\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_36\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_37\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_38\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_39\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_40\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_41\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_42\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_43\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_44\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_45\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_46\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_47\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_48\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_49\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_50\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_51\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_52\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_53\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_54\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_55\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_56\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_57\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_58\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_59\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_60\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_61\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_62\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_63\n  * @param  __PLLSAIN__ Between 49/50(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  __PLLSAIR__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_7\n  * @param  __PLLSAIDIVR__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16\n  * @retval PLLSAI clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \\\n                   (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos])))\n#endif /* LTDC */\n#endif /* RCC_PLLSAI_SUPPORT */\n\n#if defined(RCC_PLLI2S_SUPPORT)\n#if defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR)\n/**\n  * @brief  Helper macro to calculate the PLLI2S frequency used for SAI domain\n  * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),\n  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_31\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_32\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_33\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_34\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_35\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_36\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_37\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_38\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_39\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_40\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_41\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_42\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_43\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_44\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_45\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_46\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_47\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_48\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_49\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_50\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_51\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_52\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_53\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_54\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_55\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_56\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_57\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_58\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_59\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_60\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_61\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_62\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_63\n  * @param  __PLLI2SN__ Between 50/192(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  __PLLI2SQ_R__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @param  __PLLI2SDIVQ_R__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval PLLI2S clock frequency (in Hz)\n  */\n#if defined(RCC_DCKCFGR_PLLI2SDIVQ)\n#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \\\n                   (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U)))\n#else\n#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \\\n                   (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos)))\n\n#endif /* RCC_DCKCFGR_PLLI2SDIVQ */\n#endif /* RCC_DCKCFGR_PLLI2SDIVQ || RCC_DCKCFGR_PLLI2SDIVR */\n\n#if defined(SPDIFRX)\n/**\n  * @brief  Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain\n  * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),\n  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_31\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_32\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_33\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_34\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_35\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_36\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_37\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_38\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_39\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_40\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_41\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_42\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_43\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_44\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_45\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_46\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_47\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_48\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_49\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_50\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_51\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_52\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_53\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_54\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_55\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_56\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_57\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_58\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_59\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_60\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_61\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_62\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_63\n  * @param  __PLLI2SN__ Between 50 and 432\n  * @param  __PLLI2SP__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_8\n  * @retval PLLI2S clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \\\n                   ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))\n\n#endif /* SPDIFRX */\n\n/**\n  * @brief  Helper macro to calculate the PLLI2S frequency used for I2S domain\n  * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),\n  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_31\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_32\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_33\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_34\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_35\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_36\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_37\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_38\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_39\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_40\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_41\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_42\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_43\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_44\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_45\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_46\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_47\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_48\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_49\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_50\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_51\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_52\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_53\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_54\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_55\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_56\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_57\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_58\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_59\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_60\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_61\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_62\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_63\n  * @param  __PLLI2SN__ Between 50/192(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  __PLLI2SR__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_7\n  * @retval PLLI2S clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \\\n                   ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)\n/**\n  * @brief  Helper macro to calculate the PLLI2S frequency used for 48Mhz domain\n  * @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),\n  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_31\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_32\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_33\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_34\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_35\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_36\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_37\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_38\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_39\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_40\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_41\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_42\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_43\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_44\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_45\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_46\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_47\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_48\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_49\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_50\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_51\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_52\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_53\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_54\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_55\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_56\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_57\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_58\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_59\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_60\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_61\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_62\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_63\n  * @param  __PLLI2SN__ Between 50 and 432\n  * @param  __PLLI2SQ__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15\n  * @retval PLLI2S clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \\\n                   ((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos))\n\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */\n#endif /* RCC_PLLI2S_SUPPORT */\n\n/**\n  * @brief  Helper macro to calculate the HCLK frequency\n  * @param  __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)\n  * @param  __AHBPRESCALER__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SYSCLK_DIV_1\n  *         @arg @ref LL_RCC_SYSCLK_DIV_2\n  *         @arg @ref LL_RCC_SYSCLK_DIV_4\n  *         @arg @ref LL_RCC_SYSCLK_DIV_8\n  *         @arg @ref LL_RCC_SYSCLK_DIV_16\n  *         @arg @ref LL_RCC_SYSCLK_DIV_64\n  *         @arg @ref LL_RCC_SYSCLK_DIV_128\n  *         @arg @ref LL_RCC_SYSCLK_DIV_256\n  *         @arg @ref LL_RCC_SYSCLK_DIV_512\n  * @retval HCLK clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos])\n\n/**\n  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)\n  * @param  __HCLKFREQ__ HCLK frequency\n  * @param  __APB1PRESCALER__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_APB1_DIV_1\n  *         @arg @ref LL_RCC_APB1_DIV_2\n  *         @arg @ref LL_RCC_APB1_DIV_4\n  *         @arg @ref LL_RCC_APB1_DIV_8\n  *         @arg @ref LL_RCC_APB1_DIV_16\n  * @retval PCLK1 clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE1_Pos])\n\n/**\n  * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)\n  * @param  __HCLKFREQ__ HCLK frequency\n  * @param  __APB2PRESCALER__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_APB2_DIV_1\n  *         @arg @ref LL_RCC_APB2_DIV_2\n  *         @arg @ref LL_RCC_APB2_DIV_4\n  *         @arg @ref LL_RCC_APB2_DIV_8\n  *         @arg @ref LL_RCC_APB2_DIV_16\n  * @retval PCLK2 clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >>  RCC_CFGR_PPRE2_Pos])\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions\n  * @{\n  */\n\n/** @defgroup RCC_LL_EF_HSE HSE\n  * @{\n  */\n\n/**\n  * @brief  Enable the Clock Security System.\n  * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_CSSON);\n}\n\n/**\n  * @brief  Enable HSE external oscillator (HSE Bypass)\n  * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_HSEBYP);\n}\n\n/**\n  * @brief  Disable HSE external oscillator (HSE Bypass)\n  * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);\n}\n\n/**\n  * @brief  Enable HSE crystal oscillator (HSE ON)\n  * @rmtoll CR           HSEON         LL_RCC_HSE_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSE_Enable(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_HSEON);\n}\n\n/**\n  * @brief  Disable HSE crystal oscillator (HSE ON)\n  * @rmtoll CR           HSEON         LL_RCC_HSE_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSE_Disable(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);\n}\n\n/**\n  * @brief  Check if HSE oscillator Ready\n  * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)\n{\n  return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_HSI HSI\n  * @{\n  */\n\n/**\n  * @brief  Enable HSI oscillator\n  * @rmtoll CR           HSION         LL_RCC_HSI_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSI_Enable(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_HSION);\n}\n\n/**\n  * @brief  Disable HSI oscillator\n  * @rmtoll CR           HSION         LL_RCC_HSI_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSI_Disable(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_HSION);\n}\n\n/**\n  * @brief  Check if HSI clock is ready\n  * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)\n{\n  return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));\n}\n\n/**\n  * @brief  Get HSI Calibration value\n  * @note When HSITRIM is written, HSICAL is updated with the sum of\n  *       HSITRIM and the factory trim value\n  * @rmtoll CR        HSICAL        LL_RCC_HSI_GetCalibration\n  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF\n  */\n__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);\n}\n\n/**\n  * @brief  Set HSI Calibration trimming\n  * @note user-programmable trimming value that is added to the HSICAL\n  * @note Default value is 16, which, when added to the HSICAL value,\n  *       should trim the HSI to 16 MHz +/- 1 %\n  * @rmtoll CR        HSITRIM       LL_RCC_HSI_SetCalibTrimming\n  * @param  Value Between Min_Data = 0 and Max_Data = 31\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)\n{\n  MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);\n}\n\n/**\n  * @brief  Get HSI Calibration trimming\n  * @rmtoll CR        HSITRIM       LL_RCC_HSI_GetCalibTrimming\n  * @retval Between Min_Data = 0 and Max_Data = 31\n  */\n__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_LSE LSE\n  * @{\n  */\n\n/**\n  * @brief  Enable  Low Speed External (LSE) crystal.\n  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_Enable(void)\n{\n  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);\n}\n\n/**\n  * @brief  Disable  Low Speed External (LSE) crystal.\n  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_Disable(void)\n{\n  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);\n}\n\n/**\n  * @brief  Enable external clock source (LSE bypass).\n  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)\n{\n  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);\n}\n\n/**\n  * @brief  Disable external clock source (LSE bypass).\n  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)\n{\n  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);\n}\n\n/**\n  * @brief  Check if LSE oscillator Ready\n  * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)\n{\n  return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));\n}\n\n#if defined(RCC_BDCR_LSEMOD)\n/**\n  * @brief  Enable LSE high drive mode.\n  * @note LSE high drive mode can be enabled only when the LSE clock is disabled\n  * @rmtoll BDCR         LSEMOD      LL_RCC_LSE_EnableHighDriveMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void)\n{\n  SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);\n}\n\n/**\n  * @brief  Disable LSE high drive mode.\n  * @note LSE high drive mode can be disabled only when the LSE clock is disabled\n  * @rmtoll BDCR         LSEMOD      LL_RCC_LSE_DisableHighDriveMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void)\n{\n  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);\n}\n#endif /* RCC_BDCR_LSEMOD */\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_LSI LSI\n  * @{\n  */\n\n/**\n  * @brief  Enable LSI Oscillator\n  * @rmtoll CSR          LSION         LL_RCC_LSI_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSI_Enable(void)\n{\n  SET_BIT(RCC->CSR, RCC_CSR_LSION);\n}\n\n/**\n  * @brief  Disable LSI Oscillator\n  * @rmtoll CSR          LSION         LL_RCC_LSI_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSI_Disable(void)\n{\n  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);\n}\n\n/**\n  * @brief  Check if LSI is Ready\n  * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_System System\n  * @{\n  */\n\n/**\n  * @brief  Configure the system clock source\n  * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)\n{\n  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);\n}\n\n/**\n  * @brief  Get the system clock source\n  * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));\n}\n\n/**\n  * @brief  Set AHB prescaler\n  * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler\n  * @param  Prescaler This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SYSCLK_DIV_1\n  *         @arg @ref LL_RCC_SYSCLK_DIV_2\n  *         @arg @ref LL_RCC_SYSCLK_DIV_4\n  *         @arg @ref LL_RCC_SYSCLK_DIV_8\n  *         @arg @ref LL_RCC_SYSCLK_DIV_16\n  *         @arg @ref LL_RCC_SYSCLK_DIV_64\n  *         @arg @ref LL_RCC_SYSCLK_DIV_128\n  *         @arg @ref LL_RCC_SYSCLK_DIV_256\n  *         @arg @ref LL_RCC_SYSCLK_DIV_512\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)\n{\n  MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);\n}\n\n/**\n  * @brief  Set APB1 prescaler\n  * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler\n  * @param  Prescaler This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_APB1_DIV_1\n  *         @arg @ref LL_RCC_APB1_DIV_2\n  *         @arg @ref LL_RCC_APB1_DIV_4\n  *         @arg @ref LL_RCC_APB1_DIV_8\n  *         @arg @ref LL_RCC_APB1_DIV_16\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)\n{\n  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);\n}\n\n/**\n  * @brief  Set APB2 prescaler\n  * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler\n  * @param  Prescaler This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_APB2_DIV_1\n  *         @arg @ref LL_RCC_APB2_DIV_2\n  *         @arg @ref LL_RCC_APB2_DIV_4\n  *         @arg @ref LL_RCC_APB2_DIV_8\n  *         @arg @ref LL_RCC_APB2_DIV_16\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)\n{\n  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);\n}\n\n/**\n  * @brief  Get AHB prescaler\n  * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_SYSCLK_DIV_1\n  *         @arg @ref LL_RCC_SYSCLK_DIV_2\n  *         @arg @ref LL_RCC_SYSCLK_DIV_4\n  *         @arg @ref LL_RCC_SYSCLK_DIV_8\n  *         @arg @ref LL_RCC_SYSCLK_DIV_16\n  *         @arg @ref LL_RCC_SYSCLK_DIV_64\n  *         @arg @ref LL_RCC_SYSCLK_DIV_128\n  *         @arg @ref LL_RCC_SYSCLK_DIV_256\n  *         @arg @ref LL_RCC_SYSCLK_DIV_512\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));\n}\n\n/**\n  * @brief  Get APB1 prescaler\n  * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_APB1_DIV_1\n  *         @arg @ref LL_RCC_APB1_DIV_2\n  *         @arg @ref LL_RCC_APB1_DIV_4\n  *         @arg @ref LL_RCC_APB1_DIV_8\n  *         @arg @ref LL_RCC_APB1_DIV_16\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));\n}\n\n/**\n  * @brief  Get APB2 prescaler\n  * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_APB2_DIV_1\n  *         @arg @ref LL_RCC_APB2_DIV_2\n  *         @arg @ref LL_RCC_APB2_DIV_4\n  *         @arg @ref LL_RCC_APB2_DIV_8\n  *         @arg @ref LL_RCC_APB2_DIV_16\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_MCO MCO\n  * @{\n  */\n\n#if defined(RCC_CFGR_MCO1EN)\n/**\n  * @brief  Enable MCO1 output\n  * @rmtoll CFGR           RCC_CFGR_MCO1EN         LL_RCC_MCO1_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_MCO1_Enable(void)\n{\n  SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);\n}\n\n/**\n  * @brief  Disable MCO1 output\n  * @rmtoll CFGR           RCC_CFGR_MCO1EN         LL_RCC_MCO1_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_MCO1_Disable(void)\n{\n  CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);\n}\n#endif /* RCC_CFGR_MCO1EN */\n\n#if defined(RCC_CFGR_MCO2EN)\n/**\n  * @brief  Enable MCO2 output\n  * @rmtoll CFGR           RCC_CFGR_MCO2EN         LL_RCC_MCO2_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_MCO2_Enable(void)\n{\n  SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);\n}\n\n/**\n  * @brief  Disable MCO2 output\n  * @rmtoll CFGR           RCC_CFGR_MCO2EN         LL_RCC_MCO2_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_MCO2_Disable(void)\n{\n  CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);\n}\n#endif /* RCC_CFGR_MCO2EN */\n\n/**\n  * @brief  Configure MCOx\n  * @rmtoll CFGR         MCO1          LL_RCC_ConfigMCO\\n\n  *         CFGR         MCO1PRE       LL_RCC_ConfigMCO\\n\n  *         CFGR         MCO2          LL_RCC_ConfigMCO\\n\n  *         CFGR         MCO2PRE       LL_RCC_ConfigMCO\n  * @param  MCOxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_MCO1SOURCE_HSI\n  *         @arg @ref LL_RCC_MCO1SOURCE_LSE\n  *         @arg @ref LL_RCC_MCO1SOURCE_HSE\n  *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK\n  *         @arg @ref LL_RCC_MCO2SOURCE_SYSCLK\n  *         @arg @ref LL_RCC_MCO2SOURCE_PLLI2S\n  *         @arg @ref LL_RCC_MCO2SOURCE_HSE\n  *         @arg @ref LL_RCC_MCO2SOURCE_PLLCLK\n  * @param  MCOxPrescaler This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_MCO1_DIV_1\n  *         @arg @ref LL_RCC_MCO1_DIV_2\n  *         @arg @ref LL_RCC_MCO1_DIV_3\n  *         @arg @ref LL_RCC_MCO1_DIV_4\n  *         @arg @ref LL_RCC_MCO1_DIV_5\n  *         @arg @ref LL_RCC_MCO2_DIV_1\n  *         @arg @ref LL_RCC_MCO2_DIV_2\n  *         @arg @ref LL_RCC_MCO2_DIV_3\n  *         @arg @ref LL_RCC_MCO2_DIV_4\n  *         @arg @ref LL_RCC_MCO2_DIV_5\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)\n{\n  MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U),  (MCOxSource << 16U) | (MCOxPrescaler << 16U));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source\n  * @{\n  */\n#if defined(FMPI2C1)\n/**\n  * @brief  Configure FMPI2C clock source\n  * @rmtoll DCKCFGR2        FMPI2C1SEL       LL_RCC_SetFMPI2CClockSource\n  * @param  FMPI2CxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource)\n{\n  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource);\n}\n#endif /* FMPI2C1 */\n\n#if defined(LPTIM1)\n/**\n  * @brief  Configure LPTIMx clock source\n  * @rmtoll DCKCFGR2        LPTIM1SEL     LL_RCC_SetLPTIMClockSource\n  * @param  LPTIMxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)\n{\n  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);\n}\n#endif /* LPTIM1 */\n\n#if defined(SAI1)\n/**\n  * @brief  Configure SAIx clock source\n  * @rmtoll DCKCFGR        SAI1SRC       LL_RCC_SetSAIClockSource\\n\n  *         DCKCFGR        SAI2SRC       LL_RCC_SetSAIClockSource\\n\n  *         DCKCFGR        SAI1ASRC      LL_RCC_SetSAIClockSource\\n\n  *         DCKCFGR        SAI1BSRC      LL_RCC_SetSAIClockSource\n  * @param  SAIxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL  (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL  (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)\n{\n  MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));\n}\n#endif /* SAI1 */\n\n#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)\n/**\n  * @brief  Configure SDIO clock source\n  * @rmtoll DCKCFGR         SDIOSEL      LL_RCC_SetSDIOClockSource\\n\n  *         DCKCFGR2        SDIOSEL      LL_RCC_SetSDIOClockSource\n  * @param  SDIOxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK\n  *         @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource)\n{\n#if defined(RCC_DCKCFGR_SDIOSEL)\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource);\n#else\n  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource);\n#endif /* RCC_DCKCFGR_SDIOSEL */\n}\n#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */\n\n#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)\n/**\n  * @brief  Configure 48Mhz domain clock source\n  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_SetCK48MClockSource\\n\n  *         DCKCFGR2        CK48MSEL      LL_RCC_SetCK48MClockSource\n  * @param  CK48MxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)\n{\n#if defined(RCC_DCKCFGR_CK48MSEL)\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource);\n#else\n  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);\n#endif /* RCC_DCKCFGR_CK48MSEL */\n}\n\n#if defined(RNG)\n/**\n  * @brief  Configure RNG clock source\n  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_SetRNGClockSource\\n\n  *         DCKCFGR2        CK48MSEL      LL_RCC_SetRNGClockSource\n  * @param  RNGxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)\n{\n#if defined(RCC_DCKCFGR_CK48MSEL)\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource);\n#else\n  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);\n#endif /* RCC_DCKCFGR_CK48MSEL */\n}\n#endif /* RNG */\n\n#if defined(USB_OTG_FS) || defined(USB_OTG_HS)\n/**\n  * @brief  Configure USB clock source\n  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_SetUSBClockSource\\n\n  *         DCKCFGR2        CK48MSEL      LL_RCC_SetUSBClockSource\n  * @param  USBxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)\n{\n#if defined(RCC_DCKCFGR_CK48MSEL)\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource);\n#else\n  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);\n#endif /* RCC_DCKCFGR_CK48MSEL */\n}\n#endif /* USB_OTG_FS || USB_OTG_HS */\n#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */\n\n#if defined(CEC)\n/**\n  * @brief  Configure CEC clock source\n  * @rmtoll DCKCFGR2         CECSEL        LL_RCC_SetCECClockSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488\n  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)\n{\n  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);\n}\n#endif /* CEC */\n\n/**\n  * @brief  Configure I2S clock source\n  * @rmtoll CFGR         I2SSRC        LL_RCC_SetI2SClockSource\\n\n  *         DCKCFGR      I2SSRC        LL_RCC_SetI2SClockSource\\n\n  *         DCKCFGR      I2S1SRC       LL_RCC_SetI2SClockSource\\n\n  *         DCKCFGR      I2S2SRC       LL_RCC_SetI2SClockSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN\n  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)\n  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)\n  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)\n  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)\n  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)\n{\n#if defined(RCC_CFGR_I2SSRC)\n  MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);\n#else\n  MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U));\n#endif /* RCC_CFGR_I2SSRC */\n}\n\n#if defined(DSI)\n/**\n  * @brief  Configure DSI clock source\n  * @rmtoll DCKCFGR         DSISEL        LL_RCC_SetDSIClockSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY\n  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)\n{\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source);\n}\n#endif /* DSI */\n\n#if defined(DFSDM1_Channel0)\n/**\n  * @brief  Configure DFSDM Audio clock source\n  * @rmtoll DCKCFGR          CKDFSDM1ASEL        LL_RCC_SetDFSDMAudioClockSource\\n\n  *         DCKCFGR          CKDFSDM2ASEL        LL_RCC_SetDFSDMAudioClockSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1\n  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2\n  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)\n  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)\n{\n  MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U));\n}\n\n/**\n  * @brief  Configure DFSDM Kernel clock source\n  * @rmtoll DCKCFGR         CKDFSDM1SEL        LL_RCC_SetDFSDMClockSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2\n  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)\n  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)\n{\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source);\n}\n#endif /* DFSDM1_Channel0 */\n\n#if defined(SPDIFRX)\n/**\n  * @brief  Configure SPDIFRX clock source\n  * @rmtoll DCKCFGR2         SPDIFRXSEL      LL_RCC_SetSPDIFRXClockSource\n  * @param  SPDIFRXxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource)\n{\n  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource);\n}\n#endif /* SPDIFRX */\n\n#if defined(FMPI2C1)\n/**\n  * @brief  Get FMPI2C clock source\n  * @rmtoll DCKCFGR2        FMPI2C1SEL       LL_RCC_GetFMPI2CClockSource\n  * @param  FMPI2Cx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI\n */\n__STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx));\n}\n#endif /* FMPI2C1 */\n\n#if defined(LPTIM1)\n/**\n  * @brief  Get LPTIMx clock source\n  * @rmtoll DCKCFGR2        LPTIM1SEL     LL_RCC_GetLPTIMClockSource\n  * @param  LPTIMx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));\n}\n#endif /* LPTIM1 */\n\n#if defined(SAI1)\n/**\n  * @brief  Get SAIx clock source\n  * @rmtoll DCKCFGR         SAI1SEL       LL_RCC_GetSAIClockSource\\n\n  *         DCKCFGR         SAI2SEL       LL_RCC_GetSAIClockSource\\n\n  *         DCKCFGR         SAI1ASRC      LL_RCC_GetSAIClockSource\\n\n  *         DCKCFGR         SAI1BSRC      LL_RCC_GetSAIClockSource\n  * @param  SAIx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL  (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL  (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U | SAIx);\n}\n#endif /* SAI1 */\n\n#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)\n/**\n  * @brief  Get SDIOx clock source\n  * @rmtoll DCKCFGR        SDIOSEL      LL_RCC_GetSDIOClockSource\\n\n  *         DCKCFGR2       SDIOSEL      LL_RCC_GetSDIOClockSource\n  * @param  SDIOx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SDIO_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK\n  *         @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx)\n{\n#if defined(RCC_DCKCFGR_SDIOSEL)\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx));\n#else\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx));\n#endif /* RCC_DCKCFGR_SDIOSEL */\n}\n#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */\n\n#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)\n/**\n  * @brief  Get 48Mhz domain clock source\n  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_GetCK48MClockSource\\n\n  *         DCKCFGR2        CK48MSEL      LL_RCC_GetCK48MClockSource\n  * @param  CK48Mx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_CK48M_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)\n{\n#if defined(RCC_DCKCFGR_CK48MSEL)\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx));\n#else\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));\n#endif /* RCC_DCKCFGR_CK48MSEL */\n}\n\n#if defined(RNG)\n/**\n  * @brief  Get RNGx clock source\n  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_GetRNGClockSource\\n\n  *         DCKCFGR2        CK48MSEL      LL_RCC_GetRNGClockSource\n  * @param  RNGx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)\n{\n#if defined(RCC_DCKCFGR_CK48MSEL)\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx));\n#else\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));\n#endif /* RCC_DCKCFGR_CK48MSEL */\n}\n#endif /* RNG */\n\n#if defined(USB_OTG_FS) || defined(USB_OTG_HS)\n/**\n  * @brief  Get USBx clock source\n  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_GetUSBClockSource\\n\n  *         DCKCFGR2        CK48MSEL      LL_RCC_GetUSBClockSource\n  * @param  USBx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_USB_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)\n{\n#if defined(RCC_DCKCFGR_CK48MSEL)\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx));\n#else\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));\n#endif /* RCC_DCKCFGR_CK48MSEL */\n}\n#endif /* USB_OTG_FS || USB_OTG_HS */\n#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */\n\n#if defined(CEC)\n/**\n  * @brief  Get CEC Clock Source\n  * @rmtoll DCKCFGR2         CECSEL        LL_RCC_GetCECClockSource\n  * @param  CECx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_CEC_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488\n  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));\n}\n#endif /* CEC */\n\n/**\n  * @brief  Get I2S Clock Source\n  * @rmtoll CFGR         I2SSRC        LL_RCC_GetI2SClockSource\\n\n  *         DCKCFGR      I2SSRC        LL_RCC_GetI2SClockSource\\n\n  *         DCKCFGR      I2S1SRC       LL_RCC_GetI2SClockSource\\n\n  *         DCKCFGR      I2S2SRC       LL_RCC_GetI2SClockSource\n  * @param  I2Sx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_I2S1_CLKSOURCE\n  *         @arg @ref LL_RCC_I2S2_CLKSOURCE (*)\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN\n  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)\n  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)\n  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)\n  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)\n  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)\n{\n#if defined(RCC_CFGR_I2SSRC)\n  return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));\n#else\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U | I2Sx);\n#endif /* RCC_CFGR_I2SSRC */\n}\n\n#if defined(DFSDM1_Channel0)\n/**\n  * @brief  Get DFSDM Audio Clock Source\n  * @rmtoll DCKCFGR          CKDFSDM1ASEL        LL_RCC_GetDFSDMAudioClockSource\\n\n  *         DCKCFGR          CKDFSDM2ASEL        LL_RCC_GetDFSDMAudioClockSource\n  * @param  DFSDMx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE\n  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1\n  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2\n  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)\n  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U | DFSDMx);\n}\n\n/**\n  * @brief  Get DFSDM Audio Clock Source\n  * @rmtoll DCKCFGR         CKDFSDM1SEL        LL_RCC_GetDFSDMClockSource\n  * @param  DFSDMx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE\n  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2\n  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)\n  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx));\n}\n#endif /* DFSDM1_Channel0 */\n\n#if defined(SPDIFRX)\n/**\n  * @brief  Get SPDIFRX clock source\n  * @rmtoll DCKCFGR2         SPDIFRXSEL      LL_RCC_GetSPDIFRXClockSource\n  * @param  SPDIFRXx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx));\n}\n#endif /* SPDIFRX */\n\n#if defined(DSI)\n/**\n  * @brief  Get DSI Clock Source\n  * @rmtoll DCKCFGR         DSISEL        LL_RCC_GetDSIClockSource\n  * @param  DSIx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DSI_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY\n  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx));\n}\n#endif /* DSI */\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_RTC RTC\n  * @{\n  */\n\n/**\n  * @brief  Set RTC Clock Source\n  * @note Once the RTC clock source has been selected, it cannot be changed anymore unless\n  *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is\n  *       set). The BDRST bit can be used to reset them.\n  * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)\n{\n  MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);\n}\n\n/**\n  * @brief  Get RTC Clock Source\n  * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)\n{\n  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));\n}\n\n/**\n  * @brief  Enable RTC\n  * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableRTC(void)\n{\n  SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);\n}\n\n/**\n  * @brief  Disable RTC\n  * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableRTC(void)\n{\n  CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);\n}\n\n/**\n  * @brief  Check if RTC has been enabled or not\n  * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)\n{\n  return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));\n}\n\n/**\n  * @brief  Force the Backup domain reset\n  * @rmtoll BDCR         BDRST         LL_RCC_ForceBackupDomainReset\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)\n{\n  SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);\n}\n\n/**\n  * @brief  Release the Backup domain reset\n  * @rmtoll BDCR         BDRST         LL_RCC_ReleaseBackupDomainReset\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)\n{\n  CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);\n}\n\n/**\n  * @brief  Set HSE Prescalers for RTC Clock\n  * @rmtoll CFGR         RTCPRE        LL_RCC_SetRTC_HSEPrescaler\n  * @param  Prescaler This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_RTC_NOCLOCK\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_2\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_3\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_4\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_5\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_6\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_7\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_8\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_9\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_10\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_11\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_12\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_13\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_14\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_15\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_16\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_17\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_18\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_19\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_20\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_21\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_22\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_23\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_24\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_25\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_26\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_27\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_28\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_29\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_30\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_31\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)\n{\n  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);\n}\n\n/**\n  * @brief  Get HSE Prescalers for RTC Clock\n  * @rmtoll CFGR         RTCPRE        LL_RCC_GetRTC_HSEPrescaler\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_RTC_NOCLOCK\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_2\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_3\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_4\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_5\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_6\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_7\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_8\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_9\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_10\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_11\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_12\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_13\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_14\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_15\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_16\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_17\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_18\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_19\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_20\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_21\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_22\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_23\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_24\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_25\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_26\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_27\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_28\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_29\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_30\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_31\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));\n}\n\n/**\n  * @}\n  */\n\n#if defined(RCC_DCKCFGR_TIMPRE)\n/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM\n  * @{\n  */\n\n/**\n  * @brief  Set Timers Clock Prescalers\n  * @rmtoll DCKCFGR         TIMPRE        LL_RCC_SetTIMPrescaler\n  * @param  Prescaler This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE\n  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)\n{\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler);\n}\n\n/**\n  * @brief  Get Timers Clock Prescalers\n  * @rmtoll DCKCFGR         TIMPRE        LL_RCC_GetTIMPrescaler\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE\n  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE));\n}\n\n/**\n  * @}\n  */\n#endif /* RCC_DCKCFGR_TIMPRE */\n\n/** @defgroup RCC_LL_EF_PLL PLL\n  * @{\n  */\n\n/**\n  * @brief  Enable PLL\n  * @rmtoll CR           PLLON         LL_RCC_PLL_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_Enable(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_PLLON);\n}\n\n/**\n  * @brief  Disable PLL\n  * @note Cannot be disabled if the PLL clock is used as the system clock\n  * @rmtoll CR           PLLON         LL_RCC_PLL_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_Disable(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);\n}\n\n/**\n  * @brief  Check if PLL Ready\n  * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)\n{\n  return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));\n}\n\n/**\n  * @brief  Configure PLL used for SYSCLK Domain\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI(*) are disabled\n  * @note PLLN/PLLP can be written only when PLL is disabled\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SYS\\n\n  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SYS\\n\n  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SYS\\n\n  *         PLLCFGR      PLLP          LL_RCC_PLL_ConfigDomain_SYS\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  PLLN Between 50/192(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLP_R This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLP_DIV_2\n  *         @arg @ref LL_RCC_PLLP_DIV_4\n  *         @arg @ref LL_RCC_PLLP_DIV_6\n  *         @arg @ref LL_RCC_PLLP_DIV_8\n  *         @arg @ref LL_RCC_PLLR_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLR_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLR_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLR_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLR_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLR_DIV_7 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN,\n             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos);\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R);\n#if defined(RCC_PLLR_SYSCLK_SUPPORT)\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R);\n#endif /* RCC_PLLR_SYSCLK_SUPPORT */\n}\n\n/**\n  * @brief  Configure PLL used for 48Mhz domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI(*) are disabled\n  * @note PLLN/PLLQ can be written only when PLL is disabled\n  * @note This  can be selected for USB, RNG, SDIO\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_48M\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_48M\\n\n  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_48M\\n\n  *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_48M\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  PLLN Between 50/192(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLQ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLQ_DIV_2\n  *         @arg @ref LL_RCC_PLLQ_DIV_3\n  *         @arg @ref LL_RCC_PLLQ_DIV_4\n  *         @arg @ref LL_RCC_PLLQ_DIV_5\n  *         @arg @ref LL_RCC_PLLQ_DIV_6\n  *         @arg @ref LL_RCC_PLLQ_DIV_7\n  *         @arg @ref LL_RCC_PLLQ_DIV_8\n  *         @arg @ref LL_RCC_PLLQ_DIV_9\n  *         @arg @ref LL_RCC_PLLQ_DIV_10\n  *         @arg @ref LL_RCC_PLLQ_DIV_11\n  *         @arg @ref LL_RCC_PLLQ_DIV_12\n  *         @arg @ref LL_RCC_PLLQ_DIV_13\n  *         @arg @ref LL_RCC_PLLQ_DIV_14\n  *         @arg @ref LL_RCC_PLLQ_DIV_15\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,\n             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);\n}\n\n#if defined(DSI)\n/**\n  * @brief  Configure PLL used for DSI clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI are disabled\n  * @note PLLN/PLLR can be written only when PLL is disabled\n  * @note This  can be selected for DSI\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_DSI\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_DSI\\n\n  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_DSI\\n\n  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_DSI\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  PLLN Between 50 and 432\n  * @param  PLLR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_3\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_5\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,\n             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);\n}\n#endif /* DSI */\n\n#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)\n/**\n  * @brief  Configure PLL used for I2S clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI are disabled\n  * @note PLLN/PLLR can be written only when PLL is disabled\n  * @note This  can be selected for I2S\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_I2S\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_I2S\\n\n  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_I2S\\n\n  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_I2S\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  PLLN Between 50 and 432\n  * @param  PLLR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_3\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_5\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,\n             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);\n}\n#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */\n\n#if defined(SPDIFRX)\n/**\n  * @brief  Configure PLL used for SPDIFRX clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI are disabled\n  * @note PLLN/PLLR can be written only when PLL is disabled\n  * @note This  can be selected for SPDIFRX\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SPDIFRX\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SPDIFRX\\n\n  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SPDIFRX\\n\n  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SPDIFRX\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  PLLN Between 50 and 432\n  * @param  PLLR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_3\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_5\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,\n             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);\n}\n#endif /* SPDIFRX */\n\n#if defined(RCC_PLLCFGR_PLLR)\n#if defined(SAI1)\n/**\n  * @brief  Configure PLL used for SAI clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI are disabled\n  * @note PLLN/PLLR can be written only when PLL is disabled\n  * @note This  can be selected for SAI\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SAI\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SAI\\n\n  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SAI\\n\n  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SAI\\n\n  *         DCKCFGR      PLLDIVR       LL_RCC_PLL_ConfigDomain_SAI\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  PLLN Between 50 and 432\n  * @param  PLLR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_3\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_5\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_7\n  * @param  PLLDIVR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n#if defined(RCC_DCKCFGR_PLLDIVR)\n__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)\n#else\n__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)\n#endif /* RCC_DCKCFGR_PLLDIVR */\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,\n             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);\n#if defined(RCC_DCKCFGR_PLLDIVR)\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR);\n#endif /* RCC_DCKCFGR_PLLDIVR */\n}\n#endif /* SAI1 */\n#endif /* RCC_PLLCFGR_PLLR */\n\n/**\n  * @brief  Configure PLL clock source\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_SetMainSource\n  * @param PLLSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);\n}\n\n/**\n  * @brief  Get the oscillator used as PLL clock source.\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_GetMainSource\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));\n}\n\n/**\n  * @brief  Get Main PLL multiplication factor for VCO\n  * @rmtoll PLLCFGR      PLLN          LL_RCC_PLL_GetN\n  * @retval Between 50/192(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>  RCC_PLLCFGR_PLLN_Pos);\n}\n\n/**\n  * @brief  Get Main PLL division factor for PLLP\n  * @rmtoll PLLCFGR      PLLP       LL_RCC_PLL_GetP\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLP_DIV_2\n  *         @arg @ref LL_RCC_PLLP_DIV_4\n  *         @arg @ref LL_RCC_PLLP_DIV_6\n  *         @arg @ref LL_RCC_PLLP_DIV_8\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));\n}\n\n/**\n  * @brief  Get Main PLL division factor for PLLQ\n  * @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock)\n  * @rmtoll PLLCFGR      PLLQ          LL_RCC_PLL_GetQ\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLQ_DIV_2\n  *         @arg @ref LL_RCC_PLLQ_DIV_3\n  *         @arg @ref LL_RCC_PLLQ_DIV_4\n  *         @arg @ref LL_RCC_PLLQ_DIV_5\n  *         @arg @ref LL_RCC_PLLQ_DIV_6\n  *         @arg @ref LL_RCC_PLLQ_DIV_7\n  *         @arg @ref LL_RCC_PLLQ_DIV_8\n  *         @arg @ref LL_RCC_PLLQ_DIV_9\n  *         @arg @ref LL_RCC_PLLQ_DIV_10\n  *         @arg @ref LL_RCC_PLLQ_DIV_11\n  *         @arg @ref LL_RCC_PLLQ_DIV_12\n  *         @arg @ref LL_RCC_PLLQ_DIV_13\n  *         @arg @ref LL_RCC_PLLQ_DIV_14\n  *         @arg @ref LL_RCC_PLLQ_DIV_15\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));\n}\n\n#if defined(RCC_PLLCFGR_PLLR)\n/**\n  * @brief  Get Main PLL division factor for PLLR\n  * @note used for PLLCLK (system clock)\n  * @rmtoll PLLCFGR      PLLR          LL_RCC_PLL_GetR\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_3\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_5\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_7\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));\n}\n#endif /* RCC_PLLCFGR_PLLR */\n\n#if defined(RCC_DCKCFGR_PLLDIVR)\n/**\n  * @brief  Get Main PLL division factor for PLLDIVR\n  * @note used for PLLSAICLK (SAI1 and SAI2 clock)\n  * @rmtoll DCKCFGR      PLLDIVR          LL_RCC_PLL_GetDIVR\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_1\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_2\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_3\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_4\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_5\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_6\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_7\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_8\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_9\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_10\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_11\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_12\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_13\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_14\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_15\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_16\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_17\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_18\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_19\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_20\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_21\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_22\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_23\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_24\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_25\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_26\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_27\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_28\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_29\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_30\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_31\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR));\n}\n#endif /* RCC_DCKCFGR_PLLDIVR */\n\n/**\n  * @brief  Get Division factor for the main PLL and other PLL\n  * @rmtoll PLLCFGR      PLLM          LL_RCC_PLL_GetDivider\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));\n}\n\n/**\n  * @brief  Configure Spread Spectrum used for PLL\n  * @note These bits must be written before enabling PLL\n  * @rmtoll SSCGR        MODPER        LL_RCC_PLL_ConfigSpreadSpectrum\\n\n  *         SSCGR        INCSTEP       LL_RCC_PLL_ConfigSpreadSpectrum\\n\n  *         SSCGR        SPREADSEL     LL_RCC_PLL_ConfigSpreadSpectrum\n  * @param  Mod Between Min_Data=0 and Max_Data=8191\n  * @param  Inc Between Min_Data=0 and Max_Data=32767\n  * @param  Sel This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SPREAD_SELECT_CENTER\n  *         @arg @ref LL_RCC_SPREAD_SELECT_DOWN\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)\n{\n  MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel);\n}\n\n/**\n  * @brief  Get Spread Spectrum Modulation Period for PLL\n  * @rmtoll SSCGR         MODPER        LL_RCC_PLL_GetPeriodModulation\n  * @retval Between Min_Data=0 and Max_Data=8191\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)\n{\n  return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));\n}\n\n/**\n  * @brief  Get Spread Spectrum Incrementation Step for PLL\n  * @note Must be written before enabling PLL\n  * @rmtoll SSCGR         INCSTEP        LL_RCC_PLL_GetStepIncrementation\n  * @retval Between Min_Data=0 and Max_Data=32767\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)\n{\n  return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);\n}\n\n/**\n  * @brief  Get Spread Spectrum Selection for PLL\n  * @note Must be written before enabling PLL\n  * @rmtoll SSCGR         SPREADSEL        LL_RCC_PLL_GetSpreadSelection\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_SPREAD_SELECT_CENTER\n  *         @arg @ref LL_RCC_SPREAD_SELECT_DOWN\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)\n{\n  return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));\n}\n\n/**\n  * @brief  Enable Spread Spectrum for PLL.\n  * @rmtoll SSCGR         SSCGEN         LL_RCC_PLL_SpreadSpectrum_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)\n{\n  SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);\n}\n\n/**\n  * @brief  Disable Spread Spectrum for PLL.\n  * @rmtoll SSCGR         SSCGEN         LL_RCC_PLL_SpreadSpectrum_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)\n{\n  CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);\n}\n\n/**\n  * @}\n  */\n\n#if defined(RCC_PLLI2S_SUPPORT)\n/** @defgroup RCC_LL_EF_PLLI2S PLLI2S\n  * @{\n  */\n\n/**\n  * @brief  Enable PLLI2S\n  * @rmtoll CR           PLLI2SON     LL_RCC_PLLI2S_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_PLLI2SON);\n}\n\n/**\n  * @brief  Disable PLLI2S\n  * @rmtoll CR           PLLI2SON     LL_RCC_PLLI2S_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);\n}\n\n/**\n  * @brief  Check if PLLI2S Ready\n  * @rmtoll CR           PLLI2SRDY    LL_RCC_PLLI2S_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)\n{\n  return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));\n}\n\n#if (defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR))\n/**\n  * @brief  Configure PLLI2S used for SAI domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI(*) are disabled\n  * @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled\n  * @note This can be selected for SAI\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_SAI\\n\n  *         PLLI2SCFGR   PLLI2SSRC     LL_RCC_PLLI2S_ConfigDomain_SAI\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_SAI\\n\n  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_ConfigDomain_SAI\\n\n  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_SAI\\n\n  *         PLLI2SCFGR   PLLI2SQ       LL_RCC_PLLI2S_ConfigDomain_SAI\\n\n  *         PLLI2SCFGR   PLLI2SR       LL_RCC_PLLI2S_ConfigDomain_SAI\\n\n  *         DCKCFGR      PLLI2SDIVQ    LL_RCC_PLLI2S_ConfigDomain_SAI\\n\n  *         DCKCFGR      PLLI2SDIVR    LL_RCC_PLLI2S_ConfigDomain_SAI\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  *         @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_31\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_32\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_33\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_34\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_35\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_36\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_37\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_38\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_39\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_40\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_41\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_42\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_43\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_44\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_45\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_46\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_47\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_48\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_49\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_50\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_51\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_52\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_53\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_54\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_55\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_56\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_57\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_58\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_59\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_60\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_61\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_62\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_63\n  * @param  PLLN Between 50/192(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLQ_R This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLDIVQ_R This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R)\n{\n  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));\n  MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));\n#if defined(RCC_PLLI2SCFGR_PLLI2SM)\n  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);\n#else\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);\n#endif /* RCC_PLLI2SCFGR_PLLI2SM */\n  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos);\n#if defined(RCC_DCKCFGR_PLLI2SDIVQ)\n  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R);\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R);\n#else\n  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R);\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R);\n#endif /* RCC_DCKCFGR_PLLI2SDIVQ */\n}\n#endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)\n/**\n  * @brief  Configure PLLI2S used for 48Mhz domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI(*) are disabled\n  * @note PLLN/PLLQ can be written only when PLLI2S is disabled\n  * @note This can be selected for RNG, USB, SDIO\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_48M\\n\n  *         PLLI2SCFGR   PLLI2SSRC     LL_RCC_PLLI2S_ConfigDomain_48M\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_48M\\n\n  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_ConfigDomain_48M\\n\n  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_48M\\n\n  *         PLLI2SCFGR   PLLI2SQ       LL_RCC_PLLI2S_ConfigDomain_48M\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  *         @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_31\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_32\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_33\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_34\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_35\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_36\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_37\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_38\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_39\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_40\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_41\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_42\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_43\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_44\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_45\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_46\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_47\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_48\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_49\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_50\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_51\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_52\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_53\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_54\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_55\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_56\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_57\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_58\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_59\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_60\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_61\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_62\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_63\n  * @param  PLLN Between 50 and 432\n  * @param  PLLQ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)\n{\n  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));\n  MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));\n#if defined(RCC_PLLI2SCFGR_PLLI2SM)\n  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);\n#else\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);\n#endif /* RCC_PLLI2SCFGR_PLLI2SM */\n  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ);\n}\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */\n\n#if defined(SPDIFRX)\n/**\n  * @brief Configure PLLI2S used for SPDIFRX domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI(*) are disabled\n  * @note PLLN/PLLP can be written only when PLLI2S is disabled\n  * @note This  can be selected for SPDIFRX\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\\n\n  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\\n\n  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\\n\n  *         PLLI2SCFGR   PLLI2SP       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_31\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_32\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_33\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_34\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_35\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_36\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_37\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_38\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_39\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_40\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_41\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_42\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_43\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_44\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_45\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_46\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_47\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_48\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_49\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_50\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_51\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_52\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_53\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_54\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_55\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_56\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_57\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_58\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_59\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_60\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_61\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_62\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_63\n  * @param  PLLN Between 50 and 432\n  * @param  PLLP This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);\n#if defined(RCC_PLLI2SCFGR_PLLI2SM)\n  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);\n#else\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);\n#endif /* RCC_PLLI2SCFGR_PLLI2SM */\n  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP);\n}\n#endif /* SPDIFRX */\n\n/**\n  * @brief  Configure PLLI2S used for I2S1 domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI(*) are disabled\n  * @note PLLN/PLLR can be written only when PLLI2S is disabled\n  * @note This  can be selected for I2S\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_I2S\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_I2S\\n\n  *         PLLI2SCFGR   PLLI2SSRC     LL_RCC_PLLI2S_ConfigDomain_I2S\\n\n  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_ConfigDomain_I2S\\n\n  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_I2S\\n\n  *         PLLI2SCFGR   PLLI2SR       LL_RCC_PLLI2S_ConfigDomain_I2S\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  *         @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_31\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_32\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_33\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_34\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_35\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_36\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_37\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_38\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_39\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_40\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_41\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_42\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_43\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_44\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_45\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_46\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_47\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_48\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_49\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_50\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_51\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_52\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_53\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_54\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_55\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_56\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_57\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_58\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_59\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_60\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_61\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_62\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_63\n  * @param  PLLN Between 50/192(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)\n{\n  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));\n  MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));\n#if defined(RCC_PLLI2SCFGR_PLLI2SM)\n  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);\n#else\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);\n#endif /* RCC_PLLI2SCFGR_PLLI2SM */\n  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR);\n}\n\n/**\n  * @brief  Get I2SPLL multiplication factor for VCO\n  * @rmtoll PLLI2SCFGR  PLLI2SN      LL_RCC_PLLI2S_GetN\n  * @retval Between 50/192(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);\n}\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ)\n/**\n  * @brief  Get I2SPLL division factor for PLLI2SQ\n  * @rmtoll PLLI2SCFGR  PLLI2SQ      LL_RCC_PLLI2S_GetQ\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));\n}\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ */\n\n/**\n  * @brief  Get I2SPLL division factor for PLLI2SR\n  * @note used for PLLI2SCLK (I2S clock)\n  * @rmtoll PLLI2SCFGR  PLLI2SR      LL_RCC_PLLI2S_GetR\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_7\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));\n}\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SP)\n/**\n  * @brief  Get I2SPLL division factor for PLLI2SP\n  * @note used for PLLSPDIFRXCLK (SPDIFRX clock)\n  * @rmtoll PLLI2SCFGR  PLLI2SP      LL_RCC_PLLI2S_GetP\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_8\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));\n}\n#endif /* RCC_PLLI2SCFGR_PLLI2SP */\n\n#if defined(RCC_DCKCFGR_PLLI2SDIVQ)\n/**\n  * @brief  Get I2SPLL division factor for PLLI2SDIVQ\n  * @note used PLLSAICLK selected (SAI clock)\n  * @rmtoll DCKCFGR   PLLI2SDIVQ      LL_RCC_PLLI2S_GetDIVQ\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ));\n}\n#endif /* RCC_DCKCFGR_PLLI2SDIVQ */\n\n#if defined(RCC_DCKCFGR_PLLI2SDIVR)\n/**\n  * @brief  Get I2SPLL division factor for PLLI2SDIVR\n  * @note used PLLSAICLK selected (SAI clock)\n  * @rmtoll DCKCFGR   PLLI2SDIVR      LL_RCC_PLLI2S_GetDIVR\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_1\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_31\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR));\n}\n#endif /* RCC_DCKCFGR_PLLI2SDIVR */\n\n/**\n  * @brief  Get division factor for PLLI2S input clock\n  * @rmtoll PLLCFGR      PLLM          LL_RCC_PLLI2S_GetDivider\\n\n  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_GetDivider\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_31\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_32\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_33\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_34\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_35\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_36\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_37\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_38\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_39\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_40\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_41\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_42\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_43\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_44\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_45\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_46\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_47\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_48\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_49\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_50\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_51\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_52\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_53\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_54\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_55\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_56\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_57\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_58\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_59\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_60\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_61\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_62\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_63\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void)\n{\n#if defined(RCC_PLLI2SCFGR_PLLI2SM)\n  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM));\n#else\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));\n#endif /* RCC_PLLI2SCFGR_PLLI2SM */\n}\n\n/**\n  * @brief  Get the oscillator used as PLL clock source.\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_GetMainSource\\n\n  *         PLLI2SCFGR   PLLI2SSRC     LL_RCC_PLLI2S_GetMainSource\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  *         @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void)\n{\n#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)\n  register uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);\n  register uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC);\n  register uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U;\n  return (uint32_t)(pllsrc | plli2sssrc0 | plli2sssrc1);\n#else\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));\n#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */\n}\n\n/**\n  * @}\n  */\n#endif /* RCC_PLLI2S_SUPPORT */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n/** @defgroup RCC_LL_EF_PLLSAI PLLSAI\n  * @{\n  */\n\n/**\n  * @brief  Enable PLLSAI\n  * @rmtoll CR           PLLSAION     LL_RCC_PLLSAI_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_PLLSAION);\n}\n\n/**\n  * @brief  Disable PLLSAI\n  * @rmtoll CR           PLLSAION     LL_RCC_PLLSAI_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);\n}\n\n/**\n  * @brief  Check if PLLSAI Ready\n  * @rmtoll CR           PLLSAIRDY    LL_RCC_PLLSAI_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)\n{\n  return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));\n}\n\n/**\n  * @brief  Configure PLLSAI used for SAI domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI(*) are disabled\n  * @note PLLN/PLLQ can be written only when PLLSAI is disabled\n  * @note This can be selected for SAI\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_SAI\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_SAI\\n\n  *         PLLSAICFGR   PLLSAIM       LL_RCC_PLLSAI_ConfigDomain_SAI\\n\n  *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_SAI\\n\n  *         PLLSAICFGR   PLLSAIQ       LL_RCC_PLLSAI_ConfigDomain_SAI\\n\n  *         DCKCFGR      PLLSAIDIVQ    LL_RCC_PLLSAI_ConfigDomain_SAI\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_15\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_16\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_17\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_18\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_19\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_20\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_21\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_22\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_23\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_24\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_25\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_26\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_27\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_28\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_29\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_30\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_31\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_32\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_33\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_34\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_35\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_36\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_37\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_38\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_39\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_40\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_41\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_42\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_43\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_44\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_45\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_46\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_47\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_48\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_49\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_50\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_51\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_52\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_53\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_54\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_55\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_56\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_57\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_58\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_59\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_60\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_61\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_62\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_63\n  * @param  PLLN Between 49/50(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLQ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_15\n  * @param  PLLDIVQ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);\n#if defined(RCC_PLLSAICFGR_PLLSAIM)\n  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);\n#else\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);\n#endif /* RCC_PLLSAICFGR_PLLSAIM */\n  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ);\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ);\n}\n\n#if defined(RCC_PLLSAICFGR_PLLSAIP)\n/**\n  * @brief Configure PLLSAI used for 48Mhz domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI(*) are disabled\n  * @note PLLN/PLLP can be written only when PLLSAI is disabled\n  * @note This  can be selected for USB, RNG, SDIO\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_48M\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_48M\\n\n  *         PLLSAICFGR   PLLSAIM       LL_RCC_PLLSAI_ConfigDomain_48M\\n\n  *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_48M\\n\n  *         PLLSAICFGR   PLLSAIP       LL_RCC_PLLSAI_ConfigDomain_48M\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_15\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_16\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_17\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_18\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_19\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_20\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_21\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_22\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_23\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_24\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_25\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_26\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_27\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_28\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_29\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_30\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_31\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_32\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_33\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_34\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_35\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_36\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_37\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_38\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_39\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_40\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_41\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_42\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_43\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_44\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_45\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_46\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_47\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_48\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_49\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_50\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_51\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_52\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_53\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_54\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_55\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_56\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_57\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_58\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_59\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_60\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_61\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_62\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_63\n  * @param  PLLN Between 50 and 432\n  * @param  PLLP This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);\n#if defined(RCC_PLLSAICFGR_PLLSAIM)\n  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);\n#else\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);\n#endif /* RCC_PLLSAICFGR_PLLSAIM */\n  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP);\n}\n#endif /* RCC_PLLSAICFGR_PLLSAIP */\n\n#if defined(LTDC)\n/**\n  * @brief  Configure PLLSAI used for LTDC domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI(*) are disabled\n  * @note PLLN/PLLR can be written only when PLLSAI is disabled\n  * @note This  can be selected for LTDC\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_LTDC\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_LTDC\\n\n  *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_LTDC\\n\n  *         PLLSAICFGR   PLLSAIR       LL_RCC_PLLSAI_ConfigDomain_LTDC\\n\n  *         DCKCFGR      PLLSAIDIVR    LL_RCC_PLLSAI_ConfigDomain_LTDC\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_15\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_16\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_17\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_18\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_19\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_20\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_21\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_22\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_23\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_24\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_25\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_26\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_27\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_28\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_29\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_30\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_31\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_32\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_33\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_34\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_35\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_36\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_37\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_38\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_39\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_40\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_41\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_42\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_43\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_44\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_45\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_46\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_47\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_48\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_49\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_50\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_51\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_52\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_53\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_54\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_55\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_56\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_57\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_58\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_59\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_60\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_61\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_62\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_63\n  * @param  PLLN Between 49/50(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_7\n  * @param  PLLDIVR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);\n  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR);\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR);\n}\n#endif /* LTDC */\n\n/**\n  * @brief  Get division factor for PLLSAI input clock\n  * @rmtoll PLLCFGR      PLLM          LL_RCC_PLLSAI_GetDivider\\n\n  *         PLLSAICFGR   PLLSAIM       LL_RCC_PLLSAI_GetDivider\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_15\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_16\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_17\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_18\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_19\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_20\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_21\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_22\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_23\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_24\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_25\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_26\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_27\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_28\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_29\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_30\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_31\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_32\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_33\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_34\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_35\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_36\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_37\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_38\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_39\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_40\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_41\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_42\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_43\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_44\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_45\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_46\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_47\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_48\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_49\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_50\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_51\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_52\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_53\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_54\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_55\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_56\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_57\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_58\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_59\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_60\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_61\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_62\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_63\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void)\n{\n#if defined(RCC_PLLSAICFGR_PLLSAIM)\n  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM));\n#else\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));\n#endif /* RCC_PLLSAICFGR_PLLSAIM */\n}\n\n/**\n  * @brief  Get SAIPLL multiplication factor for VCO\n  * @rmtoll PLLSAICFGR  PLLSAIN      LL_RCC_PLLSAI_GetN\n  * @retval Between 49/50(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);\n}\n\n/**\n  * @brief  Get SAIPLL division factor for PLLSAIQ\n  * @rmtoll PLLSAICFGR  PLLSAIQ      LL_RCC_PLLSAI_GetQ\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_15\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));\n}\n\n#if defined(RCC_PLLSAICFGR_PLLSAIR)\n/**\n  * @brief  Get SAIPLL division factor for PLLSAIR\n  * @note used for PLLSAICLK (SAI clock)\n  * @rmtoll PLLSAICFGR  PLLSAIR      LL_RCC_PLLSAI_GetR\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_7\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));\n}\n#endif /* RCC_PLLSAICFGR_PLLSAIR */\n\n#if defined(RCC_PLLSAICFGR_PLLSAIP)\n/**\n  * @brief  Get SAIPLL division factor for PLLSAIP\n  * @note used for PLL48MCLK (48M domain clock)\n  * @rmtoll PLLSAICFGR  PLLSAIP      LL_RCC_PLLSAI_GetP\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_8\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));\n}\n#endif /* RCC_PLLSAICFGR_PLLSAIP */\n\n/**\n  * @brief  Get SAIPLL division factor for PLLSAIDIVQ\n  * @note used PLLSAICLK selected (SAI clock)\n  * @rmtoll DCKCFGR   PLLSAIDIVQ      LL_RCC_PLLSAI_GetDIVQ\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ));\n}\n\n#if defined(RCC_DCKCFGR_PLLSAIDIVR)\n/**\n  * @brief  Get SAIPLL division factor for PLLSAIDIVR\n  * @note used for LTDC domain clock\n  * @rmtoll DCKCFGR  PLLSAIDIVR      LL_RCC_PLLSAI_GetDIVR\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR));\n}\n#endif /* RCC_DCKCFGR_PLLSAIDIVR */\n\n/**\n  * @}\n  */\n#endif /* RCC_PLLSAI_SUPPORT */\n\n/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management\n  * @{\n  */\n\n/**\n  * @brief  Clear LSI ready interrupt flag\n  * @rmtoll CIR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);\n}\n\n/**\n  * @brief  Clear LSE ready interrupt flag\n  * @rmtoll CIR         LSERDYC       LL_RCC_ClearFlag_LSERDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);\n}\n\n/**\n  * @brief  Clear HSI ready interrupt flag\n  * @rmtoll CIR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);\n}\n\n/**\n  * @brief  Clear HSE ready interrupt flag\n  * @rmtoll CIR         HSERDYC       LL_RCC_ClearFlag_HSERDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);\n}\n\n/**\n  * @brief  Clear PLL ready interrupt flag\n  * @rmtoll CIR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);\n}\n\n#if defined(RCC_PLLI2S_SUPPORT)\n/**\n  * @brief  Clear PLLI2S ready interrupt flag\n  * @rmtoll CIR         PLLI2SRDYC   LL_RCC_ClearFlag_PLLI2SRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);\n}\n\n#endif /* RCC_PLLI2S_SUPPORT */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n/**\n  * @brief  Clear PLLSAI ready interrupt flag\n  * @rmtoll CIR         PLLSAIRDYC   LL_RCC_ClearFlag_PLLSAIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);\n}\n\n#endif /* RCC_PLLSAI_SUPPORT */\n\n/**\n  * @brief  Clear Clock security system interrupt flag\n  * @rmtoll CIR         CSSC          LL_RCC_ClearFlag_HSECSS\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_CSSC);\n}\n\n/**\n  * @brief  Check if LSI ready interrupt occurred or not\n  * @rmtoll CIR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));\n}\n\n/**\n  * @brief  Check if LSE ready interrupt occurred or not\n  * @rmtoll CIR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));\n}\n\n/**\n  * @brief  Check if HSI ready interrupt occurred or not\n  * @rmtoll CIR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));\n}\n\n/**\n  * @brief  Check if HSE ready interrupt occurred or not\n  * @rmtoll CIR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));\n}\n\n/**\n  * @brief  Check if PLL ready interrupt occurred or not\n  * @rmtoll CIR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));\n}\n\n#if defined(RCC_PLLI2S_SUPPORT)\n/**\n  * @brief  Check if PLLI2S ready interrupt occurred or not\n  * @rmtoll CIR         PLLI2SRDYF   LL_RCC_IsActiveFlag_PLLI2SRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));\n}\n#endif /* RCC_PLLI2S_SUPPORT */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n/**\n  * @brief  Check if PLLSAI ready interrupt occurred or not\n  * @rmtoll CIR         PLLSAIRDYF   LL_RCC_IsActiveFlag_PLLSAIRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));\n}\n#endif /* RCC_PLLSAI_SUPPORT */\n\n/**\n  * @brief  Check if Clock security system interrupt occurred or not\n  * @rmtoll CIR         CSSF          LL_RCC_IsActiveFlag_HSECSS\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));\n}\n\n/**\n  * @brief  Check if RCC flag Independent Watchdog reset is set or not.\n  * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));\n}\n\n/**\n  * @brief  Check if RCC flag Low Power reset is set or not.\n  * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));\n}\n\n/**\n  * @brief  Check if RCC flag Pin reset is set or not.\n  * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));\n}\n\n/**\n  * @brief  Check if RCC flag POR/PDR reset is set or not.\n  * @rmtoll CSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));\n}\n\n/**\n  * @brief  Check if RCC flag Software reset is set or not.\n  * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));\n}\n\n/**\n  * @brief  Check if RCC flag Window Watchdog reset is set or not.\n  * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));\n}\n\n#if defined(RCC_CSR_BORRSTF)\n/**\n  * @brief  Check if RCC flag BOR reset is set or not.\n  * @rmtoll CSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));\n}\n#endif /* RCC_CSR_BORRSTF */\n\n/**\n  * @brief  Set RMVF bit to clear the reset flags.\n  * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearResetFlags(void)\n{\n  SET_BIT(RCC->CSR, RCC_CSR_RMVF);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_IT_Management IT Management\n  * @{\n  */\n\n/**\n  * @brief  Enable LSI ready interrupt\n  * @rmtoll CIR         LSIRDYIE      LL_RCC_EnableIT_LSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);\n}\n\n/**\n  * @brief  Enable LSE ready interrupt\n  * @rmtoll CIR         LSERDYIE      LL_RCC_EnableIT_LSERDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);\n}\n\n/**\n  * @brief  Enable HSI ready interrupt\n  * @rmtoll CIR         HSIRDYIE      LL_RCC_EnableIT_HSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);\n}\n\n/**\n  * @brief  Enable HSE ready interrupt\n  * @rmtoll CIR         HSERDYIE      LL_RCC_EnableIT_HSERDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);\n}\n\n/**\n  * @brief  Enable PLL ready interrupt\n  * @rmtoll CIR         PLLRDYIE      LL_RCC_EnableIT_PLLRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);\n}\n\n#if defined(RCC_PLLI2S_SUPPORT)\n/**\n  * @brief  Enable PLLI2S ready interrupt\n  * @rmtoll CIR         PLLI2SRDYIE  LL_RCC_EnableIT_PLLI2SRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);\n}\n#endif /* RCC_PLLI2S_SUPPORT */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n/**\n  * @brief  Enable PLLSAI ready interrupt\n  * @rmtoll CIR         PLLSAIRDYIE  LL_RCC_EnableIT_PLLSAIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);\n}\n#endif /* RCC_PLLSAI_SUPPORT */\n\n/**\n  * @brief  Disable LSI ready interrupt\n  * @rmtoll CIR         LSIRDYIE      LL_RCC_DisableIT_LSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)\n{\n  CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);\n}\n\n/**\n  * @brief  Disable LSE ready interrupt\n  * @rmtoll CIR         LSERDYIE      LL_RCC_DisableIT_LSERDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)\n{\n  CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);\n}\n\n/**\n  * @brief  Disable HSI ready interrupt\n  * @rmtoll CIR         HSIRDYIE      LL_RCC_DisableIT_HSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)\n{\n  CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);\n}\n\n/**\n  * @brief  Disable HSE ready interrupt\n  * @rmtoll CIR         HSERDYIE      LL_RCC_DisableIT_HSERDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)\n{\n  CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);\n}\n\n/**\n  * @brief  Disable PLL ready interrupt\n  * @rmtoll CIR         PLLRDYIE      LL_RCC_DisableIT_PLLRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)\n{\n  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);\n}\n\n#if defined(RCC_PLLI2S_SUPPORT)\n/**\n  * @brief  Disable PLLI2S ready interrupt\n  * @rmtoll CIR         PLLI2SRDYIE  LL_RCC_DisableIT_PLLI2SRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)\n{\n  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);\n}\n\n#endif /* RCC_PLLI2S_SUPPORT */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n/**\n  * @brief  Disable PLLSAI ready interrupt\n  * @rmtoll CIR         PLLSAIRDYIE  LL_RCC_DisableIT_PLLSAIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)\n{\n  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);\n}\n#endif /* RCC_PLLSAI_SUPPORT */\n\n/**\n  * @brief  Checks if LSI ready interrupt source is enabled or disabled.\n  * @rmtoll CIR         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));\n}\n\n/**\n  * @brief  Checks if LSE ready interrupt source is enabled or disabled.\n  * @rmtoll CIR         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));\n}\n\n/**\n  * @brief  Checks if HSI ready interrupt source is enabled or disabled.\n  * @rmtoll CIR         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));\n}\n\n/**\n  * @brief  Checks if HSE ready interrupt source is enabled or disabled.\n  * @rmtoll CIR         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));\n}\n\n/**\n  * @brief  Checks if PLL ready interrupt source is enabled or disabled.\n  * @rmtoll CIR         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));\n}\n\n#if defined(RCC_PLLI2S_SUPPORT)\n/**\n  * @brief  Checks if PLLI2S ready interrupt source is enabled or disabled.\n  * @rmtoll CIR         PLLI2SRDYIE  LL_RCC_IsEnabledIT_PLLI2SRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));\n}\n\n#endif /* RCC_PLLI2S_SUPPORT */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n/**\n  * @brief  Checks if PLLSAI ready interrupt source is enabled or disabled.\n  * @rmtoll CIR         PLLSAIRDYIE  LL_RCC_IsEnabledIT_PLLSAIRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));\n}\n#endif /* RCC_PLLSAI_SUPPORT */\n\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup RCC_LL_EF_Init De-initialization function\n  * @{\n  */\nErrorStatus LL_RCC_DeInit(void);\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions\n  * @{\n  */\nvoid        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);\n#if defined(FMPI2C1)\nuint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource);\n#endif /* FMPI2C1 */\n#if defined(LPTIM1)\nuint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);\n#endif /* LPTIM1 */\n#if defined(SAI1)\nuint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);\n#endif /* SAI1 */\n#if defined(SDIO)\nuint32_t    LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource);\n#endif /* SDIO */\n#if defined(RNG)\nuint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);\n#endif /* RNG */\n#if defined(USB_OTG_FS) || defined(USB_OTG_HS)\nuint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);\n#endif /* USB_OTG_FS || USB_OTG_HS */\n#if defined(DFSDM1_Channel0)\nuint32_t    LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);\nuint32_t    LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);\n#endif /* DFSDM1_Channel0 */\nuint32_t    LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);\n#if defined(CEC)\nuint32_t    LL_RCC_GetCECClockFreq(uint32_t CECxSource);\n#endif /* CEC */\n#if defined(LTDC)\nuint32_t    LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);\n#endif /* LTDC */\n#if defined(SPDIFRX)\nuint32_t    LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);\n#endif /* SPDIFRX */\n#if defined(DSI)\nuint32_t    LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);\n#endif /* DSI */\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined(RCC) */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_LL_RCC_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_ll_sdmmc.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_sdmmc.c\n  * @author  MCD Application Team\n  * @version V1.7.1\n  * @date    14-April-2017\n  * @brief   SDMMC Low Layer HAL module driver.\n  *\n  *          This file provides firmware functions to manage the following\n  *          functionalities of the SDMMC peripheral:\n  *           + Initialization/de-initialization functions\n  *           + I/O operation functions\n  *           + Peripheral Control functions\n  *           + Peripheral State functions\n  *\n  @verbatim\n  ==============================================================================\n                       ##### SDMMC peripheral features #####\n  ==============================================================================\n    [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB\n         peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA\n         devices.\n\n    [..] The SDMMC features include the following:\n         (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support\n             for three different databus modes: 1-bit (default), 4-bit and 8-bit\n         (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)\n         (+) Full compliance with SD Memory Card Specifications Version 2.0\n         (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two\n             different data bus modes: 1-bit (default) and 4-bit\n         (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol\n             Rev1.1)\n         (+) Data transfer up to 48 MHz for the 8 bit mode\n         (+) Data and command output enable signals to control external bidirectional drivers\n\n                           ##### How to use this driver #####\n  ==============================================================================\n    [..]\n      This driver is a considered as a driver of service for external devices drivers\n      that interfaces with the SDMMC peripheral.\n      According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs\n      is used in the device's driver to perform SDMMC operations and functionalities.\n\n      This driver is almost transparent for the final user, it is only used to implement other\n      functionalities of the external device.\n\n    [..]\n      (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output (MSI, PLLUSB1CLK,\n          PLLUSB2CLK). Before start working with SDMMC peripheral make sure that the\n          PLL is well configured.\n          The SDMMC peripheral uses two clock signals:\n          (++) SDMMC adapter clock (SDMMCCLK = 48 MHz)\n          (++) APB2 bus clock (PCLK2)\n\n          -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:\n               Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK))\n\n      (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC\n          peripheral.\n\n      (+) Enable the Power ON State using the SDIO_PowerState_ON()\n          function and disable it using the function SDIO_PowerState_OFF().\n\n      (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.\n\n      (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT()\n          and __SDIO_DISABLE_IT() if you need to use interrupt mode.\n\n      (+) When using the DMA mode\n          (++) Configure the DMA in the MSP layer of the external device\n          (++) Active the needed channel Request\n          (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro\n               __SDIO_DMA_DISABLE().\n\n      (+) To control the CPSM (Command Path State Machine) and send\n          commands to the card use the SDIO_SendCommand(),\n          SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has\n          to fill the command structure (pointer to SDIO_CmdInitTypeDef) according\n          to the selected command to be sent.\n          The parameters that should be filled are:\n           (++) Command Argument\n           (++) Command Index\n           (++) Command Response type\n           (++) Command Wait\n           (++) CPSM Status (Enable or Disable).\n\n          -@@- To check if the command is well received, read the SDIO_CMDRESP\n              register using the SDIO_GetCommandResponse().\n              The SDMMC responses registers (SDIO_RESP1 to SDIO_RESP2), use the\n              SDIO_GetResponse() function.\n\n      (+) To control the DPSM (Data Path State Machine) and send/receive\n           data to/from the card use the SDIO_ConfigData(), SDIO_GetDataCounter(),\n          SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions.\n\n    *** Read Operations ***\n    =======================\n    [..]\n      (#) First, user has to fill the data structure (pointer to\n          SDIO_DataInitTypeDef) according to the selected data type to be received.\n          The parameters that should be filled are:\n           (++) Data TimeOut\n           (++) Data Length\n           (++) Data Block size\n           (++) Data Transfer direction: should be from card (To SDMMC)\n           (++) Data Transfer mode\n           (++) DPSM Status (Enable or Disable)\n\n      (#) Configure the SDMMC resources to receive the data from the card\n          according to selected transfer mode (Refer to Step 8, 9 and 10).\n\n      (#) Send the selected Read command (refer to step 11).\n\n      (#) Use the SDIO flags/interrupts to check the transfer status.\n\n    *** Write Operations ***\n    ========================\n    [..]\n     (#) First, user has to fill the data structure (pointer to\n         SDIO_DataInitTypeDef) according to the selected data type to be received.\n         The parameters that should be filled are:\n          (++) Data TimeOut\n          (++) Data Length\n          (++) Data Block size\n          (++) Data Transfer direction:  should be to card (To CARD)\n          (++) Data Transfer mode\n          (++) DPSM Status (Enable or Disable)\n\n     (#) Configure the SDMMC resources to send the data to the card according to\n         selected transfer mode.\n\n     (#) Send the selected Write command.\n\n     (#) Use the SDIO flags/interrupts to check the transfer status.\n\n    *** Command management operations ***\n    =====================================\n    [..]\n     (#) The commands used for Read/Write/Erase operations are managed in\n         separate functions.\n         Each function allows to send the needed command with the related argument,\n         then check the response.\n         By the same approach, you could implement a command and check the response.\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup SDMMC_LL SDMMC Low Layer\n  * @brief Low layer module for SD\n  * @{\n  */\n\n#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \\\n    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \\\n    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \\\n    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/* Private macro -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\nstatic uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx);\nstatic uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout);\nstatic uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx);\nstatic uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx);\nstatic uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx);\nstatic uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA);\n\n/* Exported functions --------------------------------------------------------*/\n\n/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions\n  * @{\n  */\n\n/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions\n *  @brief    Initialization and Configuration functions\n *\n@verbatim\n ===============================================================================\n              ##### Initialization/de-initialization functions #####\n ===============================================================================\n    [..]  This section provides functions allowing to:\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Initializes the SDMMC according to the specified\n  *         parameters in the SDMMC_InitTypeDef and create the associated handle.\n  * @param  SDIOx: Pointer to SDMMC register base\n  * @param  Init: SDMMC initialization structure\n  * @retval HAL status\n  */\nHAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)\n{\n  uint32_t tmpreg = 0;\n\n  /* Check the parameters */\n  assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));\n  assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge));\n  assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass));\n  assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave));\n  assert_param(IS_SDIO_BUS_WIDE(Init.BusWide));\n  assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));\n  assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));\n\n  /* Set SDMMC configuration parameters */\n  tmpreg |= (Init.ClockEdge           |\\\n             Init.ClockBypass         |\\\n             Init.ClockPowerSave      |\\\n             Init.BusWide             |\\\n             Init.HardwareFlowControl |\\\n             Init.ClockDiv\n             );\n\n  /* Write to SDMMC CLKCR */\n  MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);\n\n  return HAL_OK;\n}\n\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions\n *  @brief   Data transfers functions\n *\n@verbatim\n ===============================================================================\n                      ##### I/O operation functions #####\n ===============================================================================\n    [..]\n    This subsection provides a set of functions allowing to manage the SDMMC data\n    transfers.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Read data (word) from Rx FIFO in blocking mode (polling)\n  * @param  SDIOx: Pointer to SDMMC register base\n  * @retval HAL status\n  */\nuint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)\n{\n  /* Read data from Rx FIFO */\n  return (SDIOx->FIFO);\n}\n\n/**\n  * @brief  Write data (word) to Tx FIFO in blocking mode (polling)\n  * @param  SDIOx: Pointer to SDMMC register base\n  * @param  pWriteData: pointer to data to write\n  * @retval HAL status\n  */\nHAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)\n{\n  /* Write data to FIFO */\n  SDIOx->FIFO = *pWriteData;\n\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions\n *  @brief   management functions\n *\n@verbatim\n ===============================================================================\n                      ##### Peripheral Control functions #####\n ===============================================================================\n    [..]\n    This subsection provides a set of functions allowing to control the SDMMC data\n    transfers.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Set SDMMC Power state to ON.\n  * @param  SDIOx: Pointer to SDMMC register base\n  * @retval HAL status\n  */\nHAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)\n{\n  /* Set power state to ON */\n  SDIOx->POWER = SDIO_POWER_PWRCTRL;\n\n  /* Required power up waiting time before starting the SD initialization\n  sequence */\n  LL_mDelay(2U);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Set SDMMC Power state to OFF.\n  * @param  SDIOx: Pointer to SDMMC register base\n  * @retval HAL status\n  */\nHAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)\n{\n  /* Set power state to OFF */\n  SDIOx->POWER = (uint32_t)0x00000000;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Get SDMMC Power state.\n  * @param  SDIOx: Pointer to SDMMC register base\n  * @retval Power status of the controller. The returned value can be one of the\n  *         following values:\n  *            - 0x00: Power OFF\n  *            - 0x02: Power UP\n  *            - 0x03: Power ON\n  */\nuint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx)\n{\n  return (SDIOx->POWER & SDIO_POWER_PWRCTRL);\n}\n\n/**\n  * @brief  Configure the SDMMC command path according to the specified parameters in\n  *         SDIO_CmdInitTypeDef structure and send the command\n  * @param  SDIOx: Pointer to SDMMC register base\n  * @param  Command: pointer to a SDIO_CmdInitTypeDef structure that contains\n  *         the configuration information for the SDMMC command\n  * @retval HAL status\n  */\nHAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command)\n{\n  uint32_t tmpreg = 0;\n\n  /* Check the parameters */\n  assert_param(IS_SDIO_CMD_INDEX(Command->CmdIndex));\n  assert_param(IS_SDIO_RESPONSE(Command->Response));\n  assert_param(IS_SDIO_WAIT(Command->WaitForInterrupt));\n  assert_param(IS_SDIO_CPSM(Command->CPSM));\n\n  /* Set the SDMMC Argument value */\n  SDIOx->ARG = Command->Argument;\n\n  /* Set SDMMC command parameters */\n  tmpreg |= (uint32_t)(Command->CmdIndex         |\\\n                       Command->Response         |\\\n                       Command->WaitForInterrupt |\\\n                       Command->CPSM);\n\n  /* Write to SDMMC CMD register */\n  MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Return the command index of last command for which response received\n  * @param  SDIOx: Pointer to SDMMC register base\n  * @retval Command index of the last command response received\n  */\nuint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)\n{\n  return (uint8_t)(SDIOx->RESPCMD);\n}\n\n\n/**\n  * @brief  Return the response received from the card for the last command\n  * @param  SDIOx: Pointer to SDMMC register base\n  * @param  Response: Specifies the SDMMC response register.\n  *          This parameter can be one of the following values:\n  *            @arg SDIO_RESP1: Response Register 1\n  *            @arg SDIO_RESP2: Response Register 2\n  *            @arg SDIO_RESP3: Response Register 3\n  *            @arg SDIO_RESP4: Response Register 4\n  * @retval The Corresponding response register value\n  */\nuint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response)\n{\n  uint32_t tmp;\n\n  /* Check the parameters */\n  assert_param(IS_SDIO_RESP(Response));\n\n  /* Get the response */\n  tmp = (uint32_t)(&(SDIOx->RESP1)) + Response;\n\n  return (*(__IO uint32_t *) tmp);\n}\n\n/**\n  * @brief  Configure the SDMMC data path according to the specified\n  *         parameters in the SDIO_DataInitTypeDef.\n  * @param  SDIOx: Pointer to SDIO register base\n  * @param  Data : pointer to a SDIO_DataInitTypeDef structure\n  *         that contains the configuration information for the SDMMC data.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data)\n{\n  uint32_t tmpreg = 0;\n\n  /* Check the parameters */\n  assert_param(IS_SDIO_DATA_LENGTH(Data->DataLength));\n  assert_param(IS_SDIO_BLOCK_SIZE(Data->DataBlockSize));\n  assert_param(IS_SDIO_TRANSFER_DIR(Data->TransferDir));\n  assert_param(IS_SDIO_TRANSFER_MODE(Data->TransferMode));\n  assert_param(IS_SDIO_DPSM(Data->DPSM));\n\n  /* Set the SDMMC Data TimeOut value */\n  SDIOx->DTIMER = Data->DataTimeOut;\n\n  /* Set the SDMMC DataLength value */\n  SDIOx->DLEN = Data->DataLength;\n\n  /* Set the SDMMC data configuration parameters */\n  tmpreg |= (uint32_t)(Data->DataBlockSize |\\\n                       Data->TransferDir   |\\\n                       Data->TransferMode  |\\\n                       Data->DPSM);\n\n  /* Write to SDMMC DCTRL */\n  MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);\n\n  return HAL_OK;\n\n}\n\n/**\n  * @brief  Returns number of remaining data bytes to be transferred.\n  * @param  SDIOx: Pointer to SDIO register base\n  * @retval Number of remaining data bytes to be transferred\n  */\nuint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)\n{\n  return (SDIOx->DCOUNT);\n}\n\n/**\n  * @brief  Get the FIFO data\n  * @param  SDIOx: Pointer to SDIO register base\n  * @retval Data received\n  */\nuint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)\n{\n  return (SDIOx->FIFO);\n}\n\n/**\n  * @brief  Sets one of the two options of inserting read wait interval.\n  * @param  SDIOx: Pointer to SDIO register base\n  * @param  SDIO_ReadWaitMode: SDMMC Read Wait operation mode.\n  *          This parameter can be:\n  *            @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK\n  *            @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2\n  * @retval None\n  */\nHAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode)\n{\n  /* Check the parameters */\n  assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));\n\n  /* Set SDMMC read wait mode */\n  MODIFY_REG(SDIOx->DCTRL, SDIO_DCTRL_RWMOD, SDIO_ReadWaitMode);\n\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n\n/** @defgroup HAL_SDMMC_LL_Group4 Command management functions\n *  @brief   Data transfers functions\n *\n@verbatim\n ===============================================================================\n                   ##### Commands management functions #####\n ===============================================================================\n    [..]\n    This subsection provides a set of functions allowing to manage the needed commands.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Send the Data Block Lenght command and check the response\n  * @param  SDIOx: Pointer to SDIO register base\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  /* Set Block Size for Card */\n  sdmmc_cmdinit.Argument         = (uint32_t)BlockSize;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_BLOCKLEN;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCKLEN, SDIO_CMDTIMEOUT);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the Read Single Block command and check the response\n  * @param  SDIOx: Pointer to SDIO register base\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  /* Set Block Size for Card */\n  sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_SINGLE_BLOCK;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_SINGLE_BLOCK, SDIO_CMDTIMEOUT);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the Read Multi Block command and check the response\n  * @param  SDIOx: Pointer to SDIO register base\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  /* Set Block Size for Card */\n  sdmmc_cmdinit.Argument         = (uint32_t)ReadAdd;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_READ_MULT_BLOCK;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_MULT_BLOCK, SDIO_CMDTIMEOUT);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the Write Single Block command and check the response\n  * @param  SDIOx: Pointer to SDIO register base\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  /* Set Block Size for Card */\n  sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_SINGLE_BLOCK;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDIO_CMDTIMEOUT);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the Write Multi Block command and check the response\n  * @param  SDIOx: Pointer to SDIO register base\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  /* Set Block Size for Card */\n  sdmmc_cmdinit.Argument         = (uint32_t)WriteAdd;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_WRITE_MULT_BLOCK;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_MULT_BLOCK, SDIO_CMDTIMEOUT);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the Start Address Erase command for SD and check the response\n  * @param  SDIOx: Pointer to SDIO register base\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  /* Set Block Size for Card */\n  sdmmc_cmdinit.Argument         = (uint32_t)StartAdd;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_START;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_START, SDIO_CMDTIMEOUT);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the End Address Erase command for SD and check the response\n  * @param  SDIOx: Pointer to SDIO register base\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  /* Set Block Size for Card */\n  sdmmc_cmdinit.Argument         = (uint32_t)EndAdd;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_ERASE_GRP_END;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_END, SDIO_CMDTIMEOUT);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the Start Address Erase command and check the response\n  * @param  SDIOx: Pointer to SDIO register base\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  /* Set Block Size for Card */\n  sdmmc_cmdinit.Argument         = (uint32_t)StartAdd;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_START;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_START, SDIO_CMDTIMEOUT);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the End Address Erase command and check the response\n  * @param  SDIOx: Pointer to SDIO register base\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  /* Set Block Size for Card */\n  sdmmc_cmdinit.Argument         = (uint32_t)EndAdd;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE_GRP_END;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_END, SDIO_CMDTIMEOUT);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the Erase command and check the response\n  * @param  SDIOx: Pointer to SDIO register base\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  /* Set Block Size for Card */\n  sdmmc_cmdinit.Argument         = 0U;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ERASE;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE, SDIO_MAXERASETIMEOUT);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the Stop Transfer command and check the response.\n  * @param  SDIOx: Pointer to SDIO register base\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  /* Send CMD12 STOP_TRANSMISSION  */\n  sdmmc_cmdinit.Argument         = 0U;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_STOP_TRANSMISSION;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_STOP_TRANSMISSION, SDIO_STOPTRANSFERTIMEOUT);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the Select Deselect command and check the response.\n  * @param  SDIOx: Pointer to SDIO register base\n  * @param  addr: Address of the card to be selected\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  /* Send CMD7 SDMMC_SEL_DESEL_CARD */\n  sdmmc_cmdinit.Argument         = (uint32_t)Addr;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEL_DESEL_CARD;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEL_DESEL_CARD, SDIO_CMDTIMEOUT);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the Go Idle State command and check the response.\n  * @param  SDIOx: Pointer to SDIO register base\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  sdmmc_cmdinit.Argument         = 0U;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_GO_IDLE_STATE;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_NO;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdError(SDIOx);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the Operating Condition command and check the response.\n  * @param  SDIOx: Pointer to SDIO register base\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  /* Send CMD8 to verify SD card interface operating condition */\n  /* Argument: - [31:12]: Reserved (shall be set to '0')\n  - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)\n  - [7:0]: Check Pattern (recommended 0xAA) */\n  /* CMD Response: R7 */\n  sdmmc_cmdinit.Argument         = SDMMC_CHECK_PATTERN;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SEND_EXT_CSD;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp7(SDIOx);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the Application command to verify that that the next command\n  *         is an application specific com-mand rather than a standard command\n  *         and check the response.\n  * @param  SDIOx: Pointer to SDIO register base\n  * @param  Argument: Command Argument\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  sdmmc_cmdinit.Argument         = (uint32_t)Argument;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_CMD;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  /* If there is a HAL_ERROR, it is a MMC card, else\n  it is a SD card: SD card 2.0 (voltage range mismatch)\n     or SD card 1.x */\n  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_CMD, SDIO_CMDTIMEOUT);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the command asking the accessed card to send its operating\n  *         condition register (OCR)\n  * @param  SDIOx: Pointer to SDIO register base\n  * @param  Argument: Command Argument\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  sdmmc_cmdinit.Argument         = SDMMC_VOLTAGE_WINDOW_SD | Argument;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_OP_COND;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp3(SDIOx);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the Bus Width command and check the response.\n  * @param  SDIOx: Pointer to SDIO register base\n  * @param  BusWidth: BusWidth\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  sdmmc_cmdinit.Argument         = (uint32_t)BusWidth;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_APP_SD_SET_BUSWIDTH;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDIO_CMDTIMEOUT);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the Send SCR command and check the response.\n  * @param  SDIOx: Pointer to SDIO register base\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  /* Send CMD51 SD_APP_SEND_SCR */\n  sdmmc_cmdinit.Argument         = 0U;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_SEND_SCR;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_SEND_SCR, SDIO_CMDTIMEOUT);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the Send CID command and check the response.\n  * @param  SDIOx: Pointer to SDIO register base\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  /* Send CMD2 ALL_SEND_CID */\n  sdmmc_cmdinit.Argument         = 0U;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_ALL_SEND_CID;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_LONG;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp2(SDIOx);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the Send CSD command and check the response.\n  * @param  SDIOx: Pointer to SDIO register base\n  * @param  Argument: Command Argument\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  /* Send CMD9 SEND_CSD */\n  sdmmc_cmdinit.Argument         = Argument;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_CSD;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_LONG;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp2(SDIOx);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the Send CSD command and check the response.\n  * @param  SDIOx: Pointer to SDIO register base\n  * @param  pRCA: Card RCA\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  /* Send CMD3 SD_CMD_SET_REL_ADDR */\n  sdmmc_cmdinit.Argument         = 0U;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SET_REL_ADDR;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp6(SDIOx, SDMMC_CMD_SET_REL_ADDR, pRCA);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the Status command and check the response.\n  * @param  SDIOx: Pointer to SDIO register base\n  * @param  Argument: Command Argument\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  sdmmc_cmdinit.Argument         = Argument;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_STATUS;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEND_STATUS, SDIO_CMDTIMEOUT);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Send the Status register command and check the response.\n  * @param  SDIOx: Pointer to SDIO register base\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  sdmmc_cmdinit.Argument         = 0U;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SD_APP_STATUS;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_STATUS, SDIO_CMDTIMEOUT);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Sends host capacity support information and activates the card's\n  *         initialization process. Send SDMMC_CMD_SEND_OP_COND command\n  * @param  SDIOx: Pointer to SDIO register base\n  * @parame Argument: Argument used for the command\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  sdmmc_cmdinit.Argument         = Argument;\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_SEND_OP_COND;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp3(SDIOx);\n\n  return errorstate;\n}\n\n/**\n  * @brief  Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand\n  * @param  SDIOx: Pointer to SDIO register base\n  * @parame Argument: Argument used for the command\n  * @retval HAL status\n  */\nuint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument)\n{\n  SDIO_CmdInitTypeDef  sdmmc_cmdinit;\n  uint32_t errorstate;\n\n  /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */\n  /* CMD Response: R1 */\n  sdmmc_cmdinit.Argument         = Argument; /* SDMMC_SDR25_SWITCH_PATTERN */\n  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SWITCH;\n  sdmmc_cmdinit.Response         = SDIO_RESPONSE_SHORT;\n  sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;\n  sdmmc_cmdinit.CPSM             = SDIO_CPSM_ENABLE;\n  (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);\n\n  /* Check for error conditions */\n  errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SWITCH, SDIO_CMDTIMEOUT);\n\n  return errorstate;\n}\n\n/**\n  * @}\n  */\n\n/* Private function ----------------------------------------------------------*/\n/** @addtogroup SD_Private_Functions\n  * @{\n  */\n\n/**\n  * @brief  Checks for error conditions for CMD0.\n  * @param  hsd: SD handle\n  * @retval SD Card error state\n  */\nstatic uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx)\n{\n  /* 8 is the number of required instructions cycles for the below loop statement.\n  The SDIO_CMDTIMEOUT is expressed in ms */\n  register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);\n\n  do\n  {\n    if (count-- == 0U)\n    {\n      return SDMMC_ERROR_TIMEOUT;\n    }\n\n  }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT));\n\n  /* Clear all the static flags */\n  __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);\n\n  return SDMMC_ERROR_NONE;\n}\n\n/**\n  * @brief  Checks for error conditions for R1 response.\n  * @param  hsd: SD handle\n  * @param  SD_CMD: The sent command index\n  * @retval SD Card error state\n  */\nstatic uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout)\n{\n  uint32_t response_r1;\n  uint32_t sta_reg;\n\n  /* 8 is the number of required instructions cycles for the below loop statement.\n  The Timeout is expressed in ms */\n  register uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);\n\n  do\n  {\n    if (count-- == 0U)\n    {\n      return SDMMC_ERROR_TIMEOUT;\n    }\n    sta_reg = SDIOx->STA;\n  }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||\n         ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));\n\n  if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))\n  {\n    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);\n\n    return SDMMC_ERROR_CMD_RSP_TIMEOUT;\n  }\n  else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))\n  {\n    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);\n\n    return SDMMC_ERROR_CMD_CRC_FAIL;\n  }\n  else\n  {\n    /* Nothing to do */\n  }\n\n  /* Clear all the static flags */\n  __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);\n\n  /* Check response received is of desired command */\n  if(SDIO_GetCommandResponse(SDIOx) != SD_CMD)\n  {\n    return SDMMC_ERROR_CMD_CRC_FAIL;\n  }\n\n  /* We have received response, retrieve it for analysis  */\n  response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1);\n\n  if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)\n  {\n    return SDMMC_ERROR_NONE;\n  }\n  else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)\n  {\n    return SDMMC_ERROR_ADDR_OUT_OF_RANGE;\n  }\n  else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)\n  {\n    return SDMMC_ERROR_ADDR_MISALIGNED;\n  }\n  else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)\n  {\n    return SDMMC_ERROR_BLOCK_LEN_ERR;\n  }\n  else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)\n  {\n    return SDMMC_ERROR_ERASE_SEQ_ERR;\n  }\n  else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)\n  {\n    return SDMMC_ERROR_BAD_ERASE_PARAM;\n  }\n  else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)\n  {\n    return SDMMC_ERROR_WRITE_PROT_VIOLATION;\n  }\n  else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)\n  {\n    return SDMMC_ERROR_LOCK_UNLOCK_FAILED;\n  }\n  else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)\n  {\n    return SDMMC_ERROR_COM_CRC_FAILED;\n  }\n  else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)\n  {\n    return SDMMC_ERROR_ILLEGAL_CMD;\n  }\n  else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)\n  {\n    return SDMMC_ERROR_CARD_ECC_FAILED;\n  }\n  else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)\n  {\n    return SDMMC_ERROR_CC_ERR;\n  }\n  else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)\n  {\n    return SDMMC_ERROR_STREAM_READ_UNDERRUN;\n  }\n  else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)\n  {\n    return SDMMC_ERROR_STREAM_WRITE_OVERRUN;\n  }\n  else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)\n  {\n    return SDMMC_ERROR_CID_CSD_OVERWRITE;\n  }\n  else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)\n  {\n    return SDMMC_ERROR_WP_ERASE_SKIP;\n  }\n  else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)\n  {\n    return SDMMC_ERROR_CARD_ECC_DISABLED;\n  }\n  else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)\n  {\n    return SDMMC_ERROR_ERASE_RESET;\n  }\n  else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)\n  {\n    return SDMMC_ERROR_AKE_SEQ_ERR;\n  }\n  else\n  {\n    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;\n  }\n}\n\n/**\n  * @brief  Checks for error conditions for R2 (CID or CSD) response.\n  * @param  hsd: SD handle\n  * @retval SD Card error state\n  */\nstatic uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx)\n{\n  uint32_t sta_reg;\n  /* 8 is the number of required instructions cycles for the below loop statement.\n  The SDIO_CMDTIMEOUT is expressed in ms */\n  register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);\n\n  do\n  {\n    if (count-- == 0U)\n    {\n      return SDMMC_ERROR_TIMEOUT;\n    }\n    sta_reg = SDIOx->STA;\n  }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||\n         ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));\n\n  if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))\n  {\n    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);\n\n    return SDMMC_ERROR_CMD_RSP_TIMEOUT;\n  }\n  else if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))\n  {\n    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);\n\n    return SDMMC_ERROR_CMD_CRC_FAIL;\n  }\n  else\n  {\n    /* No error flag set */\n    /* Clear all the static flags */\n    __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);\n  }\n\n  return SDMMC_ERROR_NONE;\n}\n\n/**\n  * @brief  Checks for error conditions for R3 (OCR) response.\n  * @param  hsd: SD handle\n  * @retval SD Card error state\n  */\nstatic uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx)\n{\n  uint32_t sta_reg;\n  /* 8 is the number of required instructions cycles for the below loop statement.\n  The SDIO_CMDTIMEOUT is expressed in ms */\n  register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);\n\n  do\n  {\n    if (count-- == 0U)\n    {\n      return SDMMC_ERROR_TIMEOUT;\n    }\n    sta_reg = SDIOx->STA;\n  }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||\n         ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));\n\n  if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))\n  {\n    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);\n\n    return SDMMC_ERROR_CMD_RSP_TIMEOUT;\n  }\n  else\n  {\n    /* Clear all the static flags */\n    __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);\n  }\n\n  return SDMMC_ERROR_NONE;\n}\n\n/**\n  * @brief  Checks for error conditions for R6 (RCA) response.\n  * @param  hsd: SD handle\n  * @param  SD_CMD: The sent command index\n  * @param  pRCA: Pointer to the variable that will contain the SD card relative\n  *         address RCA\n  * @retval SD Card error state\n  */\nstatic uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA)\n{\n  uint32_t response_r1;\n  uint32_t sta_reg;\n\n  /* 8 is the number of required instructions cycles for the below loop statement.\n  The SDIO_CMDTIMEOUT is expressed in ms */\n  register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);\n\n  do\n  {\n    if (count-- == 0U)\n    {\n      return SDMMC_ERROR_TIMEOUT;\n    }\n    sta_reg = SDIOx->STA;\n  }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||\n         ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));\n\n  if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))\n  {\n    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);\n\n    return SDMMC_ERROR_CMD_RSP_TIMEOUT;\n  }\n  else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))\n  {\n    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);\n\n    return SDMMC_ERROR_CMD_CRC_FAIL;\n  }\n  else\n  {\n    /* Nothing to do */\n  }\n\n  /* Check response received is of desired command */\n  if(SDIO_GetCommandResponse(SDIOx) != SD_CMD)\n  {\n    return SDMMC_ERROR_CMD_CRC_FAIL;\n  }\n\n  /* Clear all the static flags */\n  __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);\n\n  /* We have received response, retrieve it.  */\n  response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1);\n\n  if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)\n  {\n    *pRCA = (uint16_t) (response_r1 >> 16);\n\n    return SDMMC_ERROR_NONE;\n  }\n  else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)\n  {\n    return SDMMC_ERROR_ILLEGAL_CMD;\n  }\n  else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)\n  {\n    return SDMMC_ERROR_COM_CRC_FAILED;\n  }\n  else\n  {\n    return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;\n  }\n}\n\n/**\n  * @brief  Checks for error conditions for R7 response.\n  * @param  hsd: SD handle\n  * @retval SD Card error state\n  */\nstatic uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx)\n{\n  uint32_t sta_reg;\n  /* 8 is the number of required instructions cycles for the below loop statement.\n  The SDIO_CMDTIMEOUT is expressed in ms */\n  register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);\n\n  do\n  {\n    if (count-- == 0U)\n    {\n      return SDMMC_ERROR_TIMEOUT;\n    }\n    sta_reg = SDIOx->STA;\n  }while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||\n         ((sta_reg & SDIO_FLAG_CMDACT) != 0U ));\n\n  if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))\n  {\n    /* Card is SD V2.0 compliant */\n    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);\n\n    return SDMMC_ERROR_CMD_RSP_TIMEOUT;\n  }\n  else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))\n  {\n    /* Card is SD V2.0 compliant */\n    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);\n\n    return SDMMC_ERROR_CMD_CRC_FAIL;\n  }\n  else\n  {\n    /* Nothing to do */\n  }\n\n  if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDREND))\n  {\n    /* Card is SD V2.0 compliant */\n    __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND);\n  }\n\n  return SDMMC_ERROR_NONE;\n\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\n          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\n          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n#endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_ll_sdmmc.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_sdmmc.h\n  * @author  MCD Application Team\n  * @version V1.7.1\n  * @date    14-April-2017\n  * @brief   Header file of SDMMC HAL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_LL_SDMMC_H\n#define __STM32F4xx_LL_SDMMC_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \\\n    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \\\n    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \\\n    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n#include \"stm32f4xx_ll_utils.h\" /* LL_mDelay() */\n\n/** @addtogroup STM32F4xx_Driver\n  * @{\n  */\n\n/** @addtogroup SDMMC_LL\n  * @{\n  */\n\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types\n  * @{\n  */\n\n/**\n  * @brief  SDMMC Configuration Structure definition\n  */\ntypedef struct\n{\n  uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.\n                                      This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */\n\n  uint32_t ClockBypass;          /*!< Specifies whether the SDMMC Clock divider bypass is\n                                      enabled or disabled.\n                                      This parameter can be a value of @ref SDMMC_LL_Clock_Bypass               */\n\n  uint32_t ClockPowerSave;       /*!< Specifies whether SDMMC Clock output is enabled or\n                                      disabled when the bus is idle.\n                                      This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */\n\n  uint32_t BusWide;              /*!< Specifies the SDMMC bus width.\n                                      This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */\n\n  uint32_t HardwareFlowControl;  /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.\n                                      This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */\n\n  uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDMMC controller.\n                                      This parameter can be a value between Min_Data = 0 and Max_Data = 255 */\n\n}SDIO_InitTypeDef;\n\n\n/**\n  * @brief  SDMMC Command Control structure\n  */\ntypedef struct\n{\n  uint32_t Argument;            /*!< Specifies the SDMMC command argument which is sent\n                                     to a card as part of a command message. If a command\n                                     contains an argument, it must be loaded into this register\n                                     before writing the command to the command register.              */\n\n  uint32_t CmdIndex;            /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and\n                                     Max_Data = 64                                                    */\n\n  uint32_t Response;            /*!< Specifies the SDMMC response type.\n                                     This parameter can be a value of @ref SDMMC_LL_Response_Type         */\n\n  uint32_t WaitForInterrupt;    /*!< Specifies whether SDMMC wait for interrupt request is\n                                     enabled or disabled.\n                                     This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */\n\n  uint32_t CPSM;                /*!< Specifies whether SDMMC Command path state machine (CPSM)\n                                     is enabled or disabled.\n                                     This parameter can be a value of @ref SDMMC_LL_CPSM_State            */\n}SDIO_CmdInitTypeDef;\n\n\n/**\n  * @brief  SDMMC Data Control structure\n  */\ntypedef struct\n{\n  uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */\n\n  uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */\n\n  uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.\n                                     This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */\n\n  uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer\n                                     is a read or write.\n                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */\n\n  uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.\n                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */\n\n  uint32_t DPSM;                /*!< Specifies whether SDMMC Data path state machine (DPSM)\n                                     is enabled or disabled.\n                                     This parameter can be a value of @ref SDMMC_LL_DPSM_State         */\n}SDIO_DataInitTypeDef;\n\n/**\n  * @}\n  */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants\n  * @{\n  */\n#define SDMMC_ERROR_NONE                     0x00000000U   /*!< No error                                                      */\n#define SDMMC_ERROR_CMD_CRC_FAIL             0x00000001U   /*!< Command response received (but CRC check failed)              */\n#define SDMMC_ERROR_DATA_CRC_FAIL            0x00000002U   /*!< Data block sent/received (CRC check failed)                   */\n#define SDMMC_ERROR_CMD_RSP_TIMEOUT          0x00000004U   /*!< Command response timeout                                      */\n#define SDMMC_ERROR_DATA_TIMEOUT             0x00000008U   /*!< Data timeout                                                  */\n#define SDMMC_ERROR_TX_UNDERRUN              0x00000010U   /*!< Transmit FIFO underrun                                        */\n#define SDMMC_ERROR_RX_OVERRUN               0x00000020U   /*!< Receive FIFO overrun                                          */\n#define SDMMC_ERROR_ADDR_MISALIGNED          0x00000040U   /*!< Misaligned address                                            */\n#define SDMMC_ERROR_BLOCK_LEN_ERR            0x00000080U   /*!< Transferred block length is not allowed for the card or the\n                                                                number of transferred bytes does not match the block length   */\n#define SDMMC_ERROR_ERASE_SEQ_ERR            0x00000100U   /*!< An error in the sequence of erase command occurs              */\n#define SDMMC_ERROR_BAD_ERASE_PARAM          0x00000200U   /*!< An invalid selection for erase groups                         */\n#define SDMMC_ERROR_WRITE_PROT_VIOLATION     0x00000400U   /*!< Attempt to program a write protect block                      */\n#define SDMMC_ERROR_LOCK_UNLOCK_FAILED       0x00000800U   /*!< Sequence or password error has been detected in unlock\n                                                                command or if there was an attempt to access a locked card    */\n#define SDMMC_ERROR_COM_CRC_FAILED           0x00001000U   /*!< CRC check of the previous command failed                      */\n#define SDMMC_ERROR_ILLEGAL_CMD              0x00002000U   /*!< Command is not legal for the card state                       */\n#define SDMMC_ERROR_CARD_ECC_FAILED          0x00004000U   /*!< Card internal ECC was applied but failed to correct the data  */\n#define SDMMC_ERROR_CC_ERR                   0x00008000U   /*!< Internal card controller error                                */\n#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR      0x00010000U   /*!< General or unknown error                                      */\n#define SDMMC_ERROR_STREAM_READ_UNDERRUN     0x00020000U   /*!< The card could not sustain data reading in stream rmode       */\n#define SDMMC_ERROR_STREAM_WRITE_OVERRUN     0x00040000U   /*!< The card could not sustain data programming in stream mode    */\n#define SDMMC_ERROR_CID_CSD_OVERWRITE        0x00080000U   /*!< CID/CSD overwrite error                                       */\n#define SDMMC_ERROR_WP_ERASE_SKIP            0x00100000U   /*!< Only partial address space was erased                         */\n#define SDMMC_ERROR_CARD_ECC_DISABLED        0x00200000U   /*!< Command has been executed without using internal ECC          */\n#define SDMMC_ERROR_ERASE_RESET              0x00400000U   /*!< Erase sequence was cleared before executing because an out\n                                                                of erase sequence command was received                        */\n#define SDMMC_ERROR_AKE_SEQ_ERR              0x00800000U   /*!< Error in sequence of authentication                           */\n#define SDMMC_ERROR_INVALID_VOLTRANGE        0x01000000U   /*!< Error in case of invalid voltage range                        */\n#define SDMMC_ERROR_ADDR_OUT_OF_RANGE        0x02000000U   /*!< Error when addressed block is out of range                    */\n#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE   0x04000000U   /*!< Error when command request is not applicable                  */\n#define SDMMC_ERROR_INVALID_PARAMETER        0x08000000U   /*!< the used parameter is not valid                               */\n#define SDMMC_ERROR_UNSUPPORTED_FEATURE      0x10000000U   /*!< Error when feature is not insupported                         */\n#define SDMMC_ERROR_BUSY                     0x20000000U   /*!< Error when transfer process is busy                           */\n#define SDMMC_ERROR_DMA                      0x40000000U   /*!< Error while DMA transfer                                      */\n#define SDMMC_ERROR_TIMEOUT                  0x80000000U   /*!< Timeout error                                                 */\n\n/**\n  * @brief SDMMC Commands Index\n  */\n#define SDMMC_CMD_GO_IDLE_STATE                                  0U  /*!< Resets the SD memory card.                                                               */\n#define SDMMC_CMD_SEND_OP_COND                                   1U  /*!< Sends host capacity support information and activates the card's initialization process. */\n#define SDMMC_CMD_ALL_SEND_CID                                   2U  /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */\n#define SDMMC_CMD_SET_REL_ADDR                                   3U  /*!< Asks the card to publish a new relative address (RCA).                                   */\n#define SDMMC_CMD_SET_DSR                                        4U  /*!< Programs the DSR of all cards.                                                           */\n#define SDMMC_CMD_SDMMC_SEN_OP_COND                              5U  /*!< Sends host capacity support information (HCS) and asks the accessed card to send its\n                                                                          operating condition register (OCR) content in the response on the CMD line.              */\n#define SDMMC_CMD_HS_SWITCH                                      6U  /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */\n#define SDMMC_CMD_SEL_DESEL_CARD                                 7U  /*!< Selects the card by its own relative address and gets deselected by any other address    */\n#define SDMMC_CMD_HS_SEND_EXT_CSD                                8U  /*!< Sends SD Memory Card interface condition, which includes host supply voltage information\n                                                                          and asks the card whether card supports voltage.                                         */\n#define SDMMC_CMD_SEND_CSD                                       9U  /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */\n#define SDMMC_CMD_SEND_CID                                      10U  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */\n#define SDMMC_CMD_READ_DAT_UNTIL_STOP                           11U  /*!< SD card doesn't support it.                                                              */\n#define SDMMC_CMD_STOP_TRANSMISSION                             12U  /*!< Forces the card to stop transmission.                                                    */\n#define SDMMC_CMD_SEND_STATUS                                   13U  /*!< Addressed card sends its status register.                                                */\n#define SDMMC_CMD_HS_BUSTEST_READ                               14U  /*!< Reserved                                                                                 */\n#define SDMMC_CMD_GO_INACTIVE_STATE                             15U  /*!< Sends an addressed card into the inactive state.                                         */\n#define SDMMC_CMD_SET_BLOCKLEN                                  16U  /*!< Sets the block length (in bytes for SDSC) for all following block commands\n                                                                          (read, write, lock). Default block length is fixed to 512 Bytes. Not effective\n                                                                          for SDHS and SDXC.                                                                       */\n#define SDMMC_CMD_READ_SINGLE_BLOCK                             17U  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of\n                                                                          fixed 512 bytes in case of SDHC and SDXC.                                                */\n#define SDMMC_CMD_READ_MULT_BLOCK                               18U  /*!< Continuously transfers data blocks from card to host until interrupted by\n                                                                          STOP_TRANSMISSION command.                                                               */\n#define SDMMC_CMD_HS_BUSTEST_WRITE                              19U  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */\n#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP                          20U  /*!< Speed class control command.                                                             */\n#define SDMMC_CMD_SET_BLOCK_COUNT                               23U  /*!< Specify block count for CMD18 and CMD25.                                                 */\n#define SDMMC_CMD_WRITE_SINGLE_BLOCK                            24U  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of\n                                                                          fixed 512 bytes in case of SDHC and SDXC.                                                */\n#define SDMMC_CMD_WRITE_MULT_BLOCK                              25U  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */\n#define SDMMC_CMD_PROG_CID                                      26U  /*!< Reserved for manufacturers.                                                              */\n#define SDMMC_CMD_PROG_CSD                                      27U  /*!< Programming of the programmable bits of the CSD.                                         */\n#define SDMMC_CMD_SET_WRITE_PROT                                28U  /*!< Sets the write protection bit of the addressed group.                                    */\n#define SDMMC_CMD_CLR_WRITE_PROT                                29U  /*!< Clears the write protection bit of the addressed group.                                  */\n#define SDMMC_CMD_SEND_WRITE_PROT                               30U  /*!< Asks the card to send the status of the write protection bits.                           */\n#define SDMMC_CMD_SD_ERASE_GRP_START                            32U  /*!< Sets the address of the first write block to be erased. (For SD card only).              */\n#define SDMMC_CMD_SD_ERASE_GRP_END                              33U  /*!< Sets the address of the last write block of the continuous range to be erased.           */\n#define SDMMC_CMD_ERASE_GRP_START                               35U  /*!< Sets the address of the first write block to be erased. Reserved for each command\n                                                                          system set by switch function command (CMD6).                                            */\n#define SDMMC_CMD_ERASE_GRP_END                                 36U  /*!< Sets the address of the last write block of the continuous range to be erased.\n                                                                          Reserved for each command system set by switch function command (CMD6).                  */\n#define SDMMC_CMD_ERASE                                         38U  /*!< Reserved for SD security applications.                                                   */\n#define SDMMC_CMD_FAST_IO                                       39U  /*!< SD card doesn't support it (Reserved).                                                   */\n#define SDMMC_CMD_GO_IRQ_STATE                                  40U  /*!< SD card doesn't support it (Reserved).                                                   */\n#define SDMMC_CMD_LOCK_UNLOCK                                   42U  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by\n                                                                          the SET_BLOCK_LEN command.                                                               */\n#define SDMMC_CMD_APP_CMD                                       55U  /*!< Indicates to the card that the next command is an application specific command rather\n                                                                          than a standard command.                                                                 */\n#define SDMMC_CMD_GEN_CMD                                       56U  /*!< Used either to transfer a data block to the card or to get a data block from the card\n                                                                          for general purpose/application specific commands.                                       */\n#define SDMMC_CMD_NO_CMD                                        64U  /*!< No command                                                                               */\n\n/**\n  * @brief Following commands are SD Card Specific commands.\n  *        SDMMC_APP_CMD should be sent before sending these commands.\n  */\n#define SDMMC_CMD_APP_SD_SET_BUSWIDTH                            6U  /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus\n                                                                          widths are given in SCR register.                                                        */\n#define SDMMC_CMD_SD_APP_STATUS                                 13U  /*!< (ACMD13) Sends the SD status.                                                            */\n#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS                  22U  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with\n                                                                          32bit+CRC data block.                                                                    */\n#define SDMMC_CMD_SD_APP_OP_COND                                41U  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to\n                                                                          send its operating condition register (OCR) content in the response on the CMD line.     */\n#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT                    42U  /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card  */\n#define SDMMC_CMD_SD_APP_SEND_SCR                               51U  /*!< Reads the SD Configuration Register (SCR).                                               */\n#define SDMMC_CMD_SDMMC_RW_DIRECT                               52U  /*!< For SD I/O card only, reserved for security specification.                               */\n#define SDMMC_CMD_SDMMC_RW_EXTENDED                             53U  /*!< For SD I/O card only, reserved for security specification.                               */\n\n/**\n  * @brief Following commands are SD Card Specific security commands.\n  *        SDMMC_CMD_APP_CMD should be sent before sending these commands.\n  */\n#define SDMMC_CMD_SD_APP_GET_MKB                                43U\n#define SDMMC_CMD_SD_APP_GET_MID                                44U\n#define SDMMC_CMD_SD_APP_SET_CER_RN1                            45U\n#define SDMMC_CMD_SD_APP_GET_CER_RN2                            46U\n#define SDMMC_CMD_SD_APP_SET_CER_RES2                           47U\n#define SDMMC_CMD_SD_APP_GET_CER_RES1                           48U\n#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK             18U\n#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK            25U\n#define SDMMC_CMD_SD_APP_SECURE_ERASE                           38U\n#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA                     49U\n#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB                       48U\n\n/**\n  * @brief  Masks for errors Card Status R1 (OCR Register)\n  */\n#define SDMMC_OCR_ADDR_OUT_OF_RANGE        0x80000000U\n#define SDMMC_OCR_ADDR_MISALIGNED          0x40000000U\n#define SDMMC_OCR_BLOCK_LEN_ERR            0x20000000U\n#define SDMMC_OCR_ERASE_SEQ_ERR            0x10000000U\n#define SDMMC_OCR_BAD_ERASE_PARAM          0x08000000U\n#define SDMMC_OCR_WRITE_PROT_VIOLATION     0x04000000U\n#define SDMMC_OCR_LOCK_UNLOCK_FAILED       0x01000000U\n#define SDMMC_OCR_COM_CRC_FAILED           0x00800000U\n#define SDMMC_OCR_ILLEGAL_CMD              0x00400000U\n#define SDMMC_OCR_CARD_ECC_FAILED          0x00200000U\n#define SDMMC_OCR_CC_ERROR                 0x00100000U\n#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR    0x00080000U\n#define SDMMC_OCR_STREAM_READ_UNDERRUN     0x00040000U\n#define SDMMC_OCR_STREAM_WRITE_OVERRUN     0x00020000U\n#define SDMMC_OCR_CID_CSD_OVERWRITE        0x00010000U\n#define SDMMC_OCR_WP_ERASE_SKIP            0x00008000U\n#define SDMMC_OCR_CARD_ECC_DISABLED        0x00004000U\n#define SDMMC_OCR_ERASE_RESET              0x00002000U\n#define SDMMC_OCR_AKE_SEQ_ERROR            0x00000008U\n#define SDMMC_OCR_ERRORBITS                0xFDFFE008U\n\n/**\n  * @brief  Masks for R6 Response\n  */\n#define SDMMC_R6_GENERAL_UNKNOWN_ERROR     0x00002000U\n#define SDMMC_R6_ILLEGAL_CMD               0x00004000U\n#define SDMMC_R6_COM_CRC_FAILED            0x00008000U\n\n#define SDMMC_VOLTAGE_WINDOW_SD            0x80100000U\n#define SDMMC_HIGH_CAPACITY                0x40000000U\n#define SDMMC_STD_CAPACITY                 0x00000000U\n#define SDMMC_CHECK_PATTERN                0x000001AAU\n#define SD_SWITCH_1_8V_CAPACITY            0x01000000U\n\n#define SDMMC_MAX_VOLT_TRIAL               0x0000FFFFU\n\n#define SDMMC_MAX_TRIAL                    0x0000FFFFU\n\n#define SDMMC_ALLZERO                      0x00000000U\n\n#define SDMMC_WIDE_BUS_SUPPORT             0x00040000U\n#define SDMMC_SINGLE_BUS_SUPPORT           0x00010000U\n#define SDMMC_CARD_LOCKED                  0x02000000U\n\n#define SDMMC_DATATIMEOUT                  0xFFFFFFFFU\n\n#define SDMMC_0TO7BITS                     0x000000FFU\n#define SDMMC_8TO15BITS                    0x0000FF00U\n#define SDMMC_16TO23BITS                   0x00FF0000U\n#define SDMMC_24TO31BITS                   0xFF000000U\n#define SDMMC_MAX_DATA_LENGTH              0x01FFFFFFU\n\n#define SDMMC_HALFFIFO                     0x00000008U\n#define SDMMC_HALFFIFOBYTES                0x00000020U\n\n/**\n  * @brief  Command Class supported\n  */\n#define SDIO_CCCC_ERASE                   0x00000020U\n\n#define SDIO_CMDTIMEOUT                   5000U        /* Command send and response timeout */\n#define SDIO_MAXERASETIMEOUT              63000U       /* Max erase Timeout 63 s            */\n#define SDIO_STOPTRANSFERTIMEOUT          100000000U   /* Timeout for STOP TRANSMISSION command */\n\n/** @defgroup SDIO_LL_Clock_Edge Clock Edge\n  * @{\n  */\n#define SDIO_CLOCK_EDGE_RISING               0x00000000U\n#define SDIO_CLOCK_EDGE_FALLING              SDIO_CLKCR_NEGEDGE\n\n#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \\\n                                   ((EDGE) == SDIO_CLOCK_EDGE_FALLING))\n/**\n  * @}\n  */\n\n/** @defgroup SDIO_LL_Clock_Bypass Clock Bypass\n  * @{\n  */\n#define SDIO_CLOCK_BYPASS_DISABLE             0x00000000U\n#define SDIO_CLOCK_BYPASS_ENABLE              SDIO_CLKCR_BYPASS\n\n#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \\\n                                       ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))\n/**\n  * @}\n  */\n\n/** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving\n  * @{\n  */\n#define SDIO_CLOCK_POWER_SAVE_DISABLE         0x00000000U\n#define SDIO_CLOCK_POWER_SAVE_ENABLE          SDIO_CLKCR_PWRSAV\n\n#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \\\n                                         ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))\n/**\n  * @}\n  */\n\n/** @defgroup SDIO_LL_Bus_Wide Bus Width\n  * @{\n  */\n#define SDIO_BUS_WIDE_1B                      0x00000000U\n#define SDIO_BUS_WIDE_4B                      SDIO_CLKCR_WIDBUS_0\n#define SDIO_BUS_WIDE_8B                      SDIO_CLKCR_WIDBUS_1\n\n#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \\\n                                 ((WIDE) == SDIO_BUS_WIDE_4B) || \\\n                                 ((WIDE) == SDIO_BUS_WIDE_8B))\n/**\n  * @}\n  */\n\n/** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control\n  * @{\n  */\n#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE    0x00000000U\n#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE     SDIO_CLKCR_HWFC_EN\n\n#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \\\n                                                 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))\n/**\n  * @}\n  */\n\n/** @defgroup SDIO_LL_Clock_Division Clock Division\n  * @{\n  */\n#define IS_SDIO_CLKDIV(DIV)   ((DIV) <= 0xFFU)\n/**\n  * @}\n  */\n\n/** @defgroup SDIO_LL_Command_Index Command Index\n  * @{\n  */\n#define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40U)\n/**\n  * @}\n  */\n\n/** @defgroup SDIO_LL_Response_Type Response Type\n  * @{\n  */\n#define SDIO_RESPONSE_NO                    0x00000000U\n#define SDIO_RESPONSE_SHORT                 SDIO_CMD_WAITRESP_0\n#define SDIO_RESPONSE_LONG                  SDIO_CMD_WAITRESP\n\n#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO)    || \\\n                                     ((RESPONSE) == SDIO_RESPONSE_SHORT) || \\\n                                     ((RESPONSE) == SDIO_RESPONSE_LONG))\n/**\n  * @}\n  */\n\n/** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt\n  * @{\n  */\n#define SDIO_WAIT_NO                        0x00000000U\n#define SDIO_WAIT_IT                        SDIO_CMD_WAITINT\n#define SDIO_WAIT_PEND                      SDIO_CMD_WAITPEND\n\n#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \\\n                             ((WAIT) == SDIO_WAIT_IT) || \\\n                             ((WAIT) == SDIO_WAIT_PEND))\n/**\n  * @}\n  */\n\n/** @defgroup SDIO_LL_CPSM_State CPSM State\n  * @{\n  */\n#define SDIO_CPSM_DISABLE                   0x00000000U\n#define SDIO_CPSM_ENABLE                    SDIO_CMD_CPSMEN\n\n#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \\\n                             ((CPSM) == SDIO_CPSM_ENABLE))\n/**\n  * @}\n  */\n\n/** @defgroup SDIO_LL_Response_Registers Response Register\n  * @{\n  */\n#define SDIO_RESP1                          0x00000000U\n#define SDIO_RESP2                          0x00000004U\n#define SDIO_RESP3                          0x00000008U\n#define SDIO_RESP4                          0x0000000CU\n\n#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \\\n                             ((RESP) == SDIO_RESP2) || \\\n                             ((RESP) == SDIO_RESP3) || \\\n                             ((RESP) == SDIO_RESP4))\n/**\n  * @}\n  */\n\n/** @defgroup SDIO_LL_Data_Length Data Lenght\n  * @{\n  */\n#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)\n/**\n  * @}\n  */\n\n/** @defgroup SDIO_LL_Data_Block_Size  Data Block Size\n  * @{\n  */\n#define SDIO_DATABLOCK_SIZE_1B               0x00000000U\n#define SDIO_DATABLOCK_SIZE_2B               SDIO_DCTRL_DBLOCKSIZE_0\n#define SDIO_DATABLOCK_SIZE_4B               SDIO_DCTRL_DBLOCKSIZE_1\n#define SDIO_DATABLOCK_SIZE_8B               (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1)\n#define SDIO_DATABLOCK_SIZE_16B              SDIO_DCTRL_DBLOCKSIZE_2\n#define SDIO_DATABLOCK_SIZE_32B              (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2)\n#define SDIO_DATABLOCK_SIZE_64B              (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)\n#define SDIO_DATABLOCK_SIZE_128B             (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)\n#define SDIO_DATABLOCK_SIZE_256B             SDIO_DCTRL_DBLOCKSIZE_3\n#define SDIO_DATABLOCK_SIZE_512B             (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3)\n#define SDIO_DATABLOCK_SIZE_1024B            (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)\n#define SDIO_DATABLOCK_SIZE_2048B            (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)\n#define SDIO_DATABLOCK_SIZE_4096B            (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)\n#define SDIO_DATABLOCK_SIZE_8192B            (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)\n#define SDIO_DATABLOCK_SIZE_16384B           (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)\n\n#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B)    || \\\n                                   ((SIZE) == SDIO_DATABLOCK_SIZE_2B)    || \\\n                                   ((SIZE) == SDIO_DATABLOCK_SIZE_4B)    || \\\n                                   ((SIZE) == SDIO_DATABLOCK_SIZE_8B)    || \\\n                                   ((SIZE) == SDIO_DATABLOCK_SIZE_16B)   || \\\n                                   ((SIZE) == SDIO_DATABLOCK_SIZE_32B)   || \\\n                                   ((SIZE) == SDIO_DATABLOCK_SIZE_64B)   || \\\n                                   ((SIZE) == SDIO_DATABLOCK_SIZE_128B)  || \\\n                                   ((SIZE) == SDIO_DATABLOCK_SIZE_256B)  || \\\n                                   ((SIZE) == SDIO_DATABLOCK_SIZE_512B)  || \\\n                                   ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \\\n                                   ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \\\n                                   ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \\\n                                   ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \\\n                                   ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))\n/**\n  * @}\n  */\n\n/** @defgroup SDIO_LL_Transfer_Direction Transfer Direction\n  * @{\n  */\n#define SDIO_TRANSFER_DIR_TO_CARD            0x00000000U\n#define SDIO_TRANSFER_DIR_TO_SDIO            SDIO_DCTRL_DTDIR\n\n#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \\\n                                    ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))\n/**\n  * @}\n  */\n\n/** @defgroup SDIO_LL_Transfer_Type Transfer Type\n  * @{\n  */\n#define SDIO_TRANSFER_MODE_BLOCK             0x00000000U\n#define SDIO_TRANSFER_MODE_STREAM            SDIO_DCTRL_DTMODE\n\n#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \\\n                                      ((MODE) == SDIO_TRANSFER_MODE_STREAM))\n/**\n  * @}\n  */\n\n/** @defgroup SDIO_LL_DPSM_State DPSM State\n  * @{\n  */\n#define SDIO_DPSM_DISABLE                    0x00000000U\n#define SDIO_DPSM_ENABLE                     SDIO_DCTRL_DTEN\n\n#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\\\n                             ((DPSM) == SDIO_DPSM_ENABLE))\n/**\n  * @}\n  */\n\n/** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode\n  * @{\n  */\n#define SDIO_READ_WAIT_MODE_DATA2                0x00000000U\n#define SDIO_READ_WAIT_MODE_CLK                  (SDIO_DCTRL_RWMOD)\n\n#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \\\n                                     ((MODE) == SDIO_READ_WAIT_MODE_DATA2))\n/**\n  * @}\n  */\n\n/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources\n  * @{\n  */\n#define SDIO_IT_CCRCFAIL                    SDIO_MASK_CCRCFAILIE\n#define SDIO_IT_DCRCFAIL                    SDIO_MASK_DCRCFAILIE\n#define SDIO_IT_CTIMEOUT                    SDIO_MASK_CTIMEOUTIE\n#define SDIO_IT_DTIMEOUT                    SDIO_MASK_DTIMEOUTIE\n#define SDIO_IT_TXUNDERR                    SDIO_MASK_TXUNDERRIE\n#define SDIO_IT_RXOVERR                     SDIO_MASK_RXOVERRIE\n#define SDIO_IT_CMDREND                     SDIO_MASK_CMDRENDIE\n#define SDIO_IT_CMDSENT                     SDIO_MASK_CMDSENTIE\n#define SDIO_IT_DATAEND                     SDIO_MASK_DATAENDIE\n#if defined(SDIO_STA_STBITERR)\n#define SDIO_IT_STBITERR                    SDIO_MASK_STBITERRIE\n#endif\n#define SDIO_IT_DBCKEND                     SDIO_MASK_DBCKENDIE\n#define SDIO_IT_CMDACT                      SDIO_MASK_CMDACTIE\n#define SDIO_IT_TXACT                       SDIO_MASK_TXACTIE\n#define SDIO_IT_RXACT                       SDIO_MASK_RXACTIE\n#define SDIO_IT_TXFIFOHE                    SDIO_MASK_TXFIFOHEIE\n#define SDIO_IT_RXFIFOHF                    SDIO_MASK_RXFIFOHFIE\n#define SDIO_IT_TXFIFOF                     SDIO_MASK_TXFIFOFIE\n#define SDIO_IT_RXFIFOF                     SDIO_MASK_RXFIFOFIE\n#define SDIO_IT_TXFIFOE                     SDIO_MASK_TXFIFOEIE\n#define SDIO_IT_RXFIFOE                     SDIO_MASK_RXFIFOEIE\n#define SDIO_IT_TXDAVL                      SDIO_MASK_TXDAVLIE\n#define SDIO_IT_RXDAVL                      SDIO_MASK_RXDAVLIE\n#define SDIO_IT_SDIOIT                      SDIO_MASK_SDIOITIE\n#if defined(SDIO_CMD_CEATACMD)\n#define SDIO_IT_CEATAEND                    SDIO_MASK_CEATAENDIE\n#endif\n/**\n  * @}\n  */\n\n/** @defgroup SDIO_LL_Flags Flags\n  * @{\n  */\n#define SDIO_FLAG_CCRCFAIL                  SDIO_STA_CCRCFAIL\n#define SDIO_FLAG_DCRCFAIL                  SDIO_STA_DCRCFAIL\n#define SDIO_FLAG_CTIMEOUT                  SDIO_STA_CTIMEOUT\n#define SDIO_FLAG_DTIMEOUT                  SDIO_STA_DTIMEOUT\n#define SDIO_FLAG_TXUNDERR                  SDIO_STA_TXUNDERR\n#define SDIO_FLAG_RXOVERR                   SDIO_STA_RXOVERR\n#define SDIO_FLAG_CMDREND                   SDIO_STA_CMDREND\n#define SDIO_FLAG_CMDSENT                   SDIO_STA_CMDSENT\n#define SDIO_FLAG_DATAEND                   SDIO_STA_DATAEND\n#if defined(SDIO_STA_STBITERR)\n#define SDIO_FLAG_STBITERR                  SDIO_STA_STBITERR\n#endif\n#define SDIO_FLAG_DBCKEND                   SDIO_STA_DBCKEND\n#define SDIO_FLAG_CMDACT                    SDIO_STA_CMDACT\n#define SDIO_FLAG_TXACT                     SDIO_STA_TXACT\n#define SDIO_FLAG_RXACT                     SDIO_STA_RXACT\n#define SDIO_FLAG_TXFIFOHE                  SDIO_STA_TXFIFOHE\n#define SDIO_FLAG_RXFIFOHF                  SDIO_STA_RXFIFOHF\n#define SDIO_FLAG_TXFIFOF                   SDIO_STA_TXFIFOF\n#define SDIO_FLAG_RXFIFOF                   SDIO_STA_RXFIFOF\n#define SDIO_FLAG_TXFIFOE                   SDIO_STA_TXFIFOE\n#define SDIO_FLAG_RXFIFOE                   SDIO_STA_RXFIFOE\n#define SDIO_FLAG_TXDAVL                    SDIO_STA_TXDAVL\n#define SDIO_FLAG_RXDAVL                    SDIO_STA_RXDAVL\n#define SDIO_FLAG_SDIOIT                    SDIO_STA_SDIOIT\n#if defined(SDIO_CMD_CEATACMD)\n#define SDIO_FLAG_CEATAEND                  SDIO_STA_CEATAEND\n#endif\n#define SDIO_STATIC_FLAGS                   ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\\\n                                                         SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR  |\\\n                                                         SDIO_FLAG_CMDREND  | SDIO_FLAG_CMDSENT  | SDIO_FLAG_DATAEND  |\\\n                                                         SDIO_FLAG_DBCKEND | SDIO_FLAG_SDIOIT))\n\n#define SDIO_STATIC_CMD_FLAGS               ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND |\\\n                                                         SDIO_FLAG_CMDSENT))\n\n#define SDIO_STATIC_DATA_FLAGS              ((uint32_t)(SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR |\\\n                                                         SDIO_FLAG_RXOVERR  | SDIO_FLAG_DATAEND  | SDIO_FLAG_DBCKEND))\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros\n  * @{\n  */\n\n/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region\n  * @{\n  */\n/* ------------ SDIO registers bit address in the alias region -------------- */\n#define SDIO_OFFSET               (SDIO_BASE - PERIPH_BASE)\n\n/* --- CLKCR Register ---*/\n/* Alias word address of CLKEN bit */\n#define CLKCR_OFFSET              (SDIO_OFFSET + 0x04U)\n#define CLKEN_BITNUMBER           0x08U\n#define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))\n\n/* --- CMD Register ---*/\n/* Alias word address of SDIOSUSPEND bit */\n#define CMD_OFFSET                (SDIO_OFFSET + 0x0CU)\n#define SDIOSUSPEND_BITNUMBER     0x0BU\n#define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))\n\n/* Alias word address of ENCMDCOMPL bit */\n#define ENCMDCOMPL_BITNUMBER      0x0CU\n#define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))\n\n/* Alias word address of NIEN bit */\n#define NIEN_BITNUMBER            0x0DU\n#define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))\n\n/* Alias word address of ATACMD bit */\n#define ATACMD_BITNUMBER          0x0EU\n#define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))\n\n/* --- DCTRL Register ---*/\n/* Alias word address of DMAEN bit */\n#define DCTRL_OFFSET              (SDIO_OFFSET + 0x2CU)\n#define DMAEN_BITNUMBER           0x03U\n#define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))\n\n/* Alias word address of RWSTART bit */\n#define RWSTART_BITNUMBER         0x08U\n#define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))\n\n/* Alias word address of RWSTOP bit */\n#define RWSTOP_BITNUMBER          0x09U\n#define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))\n\n/* Alias word address of RWMOD bit */\n#define RWMOD_BITNUMBER           0x0AU\n#define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))\n\n/* Alias word address of SDIOEN bit */\n#define SDIOEN_BITNUMBER          0x0BU\n#define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))\n/**\n  * @}\n  */\n\n/** @defgroup SDIO_LL_Register Bits And Addresses Definitions\n  * @brief SDIO_LL registers bit address in the alias region\n  * @{\n  */\n/* ---------------------- SDIO registers bit mask --------------------------- */\n/* --- CLKCR Register ---*/\n/* CLKCR register clear mask */\n#define CLKCR_CLEAR_MASK         ((uint32_t)(SDIO_CLKCR_CLKDIV  | SDIO_CLKCR_PWRSAV |\\\n                                             SDIO_CLKCR_BYPASS  | SDIO_CLKCR_WIDBUS |\\\n                                             SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))\n\n/* --- DCTRL Register ---*/\n/* SDIO DCTRL Clear Mask */\n#define DCTRL_CLEAR_MASK         ((uint32_t)(SDIO_DCTRL_DTEN    | SDIO_DCTRL_DTDIR |\\\n                                             SDIO_DCTRL_DTMODE  | SDIO_DCTRL_DBLOCKSIZE))\n\n/* --- CMD Register ---*/\n/* CMD Register clear mask */\n#define CMD_CLEAR_MASK           ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\\\n                                             SDIO_CMD_WAITINT  | SDIO_CMD_WAITPEND |\\\n                                             SDIO_CMD_CPSMEN   | SDIO_CMD_SDIOSUSPEND))\n\n/* SDIO Initialization Frequency (400KHz max) */\n#define SDIO_INIT_CLK_DIV     ((uint8_t)0x76)    /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */\n\n/* SDIO Data Transfer Frequency (25MHz max) */\n#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)     /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */\n\n/**\n  * @}\n  */\n\n/** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration\n *  @brief macros to handle interrupts and specific clock configurations\n * @{\n */\n\n/**\n  * @brief  Enable the SDIO device.\n  * @param  __INSTANCE__: SDIO Instance\n  * @retval None\n  */\n#define __SDIO_ENABLE(__INSTANCE__)  (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)\n\n/**\n  * @brief  Disable the SDIO device.\n  * @param  __INSTANCE__: SDIO Instance\n  * @retval None\n  */\n#define __SDIO_DISABLE(__INSTANCE__)  (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)\n\n/**\n  * @brief  Enable the SDIO DMA transfer.\n  * @param  __INSTANCE__: SDIO Instance\n  * @retval None\n  */\n#define __SDIO_DMA_ENABLE(__INSTANCE__)  (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)\n\n/**\n  * @brief  Disable the SDIO DMA transfer.\n  * @param  __INSTANCE__: SDIO Instance\n  * @retval None\n  */\n#define __SDIO_DMA_DISABLE(__INSTANCE__)  (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)\n\n/**\n  * @brief  Enable the SDIO device interrupt.\n  * @param  __INSTANCE__ : Pointer to SDIO register base\n  * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.\n  *         This parameter can be one or a combination of the following values:\n  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\n  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\n  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\n  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\n  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\n  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt\n  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt\n  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt\n  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt\n  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\n  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt\n  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt\n  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt\n  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\n  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt\n  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt\n  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt\n  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt\n  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt\n  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt\n  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt\n  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt\n  * @retval None\n  */\n#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))\n\n/**\n  * @brief  Disable the SDIO device interrupt.\n  * @param  __INSTANCE__ : Pointer to SDIO register base\n  * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.\n  *          This parameter can be one or a combination of the following values:\n  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\n  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\n  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\n  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\n  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\n  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt\n  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt\n  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt\n  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt\n  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\n  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt\n  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt\n  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt\n  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\n  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt\n  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt\n  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt\n  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt\n  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt\n  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt\n  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt\n  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt\n  * @retval None\n  */\n#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))\n\n/**\n  * @brief  Checks whether the specified SDIO flag is set or not.\n  * @param  __INSTANCE__ : Pointer to SDIO register base\n  * @param  __FLAG__: specifies the flag to check.\n  *          This parameter can be one of the following values:\n  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)\n  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\n  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout\n  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout\n  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error\n  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error\n  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)\n  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)\n  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)\n  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)\n  *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress\n  *            @arg SDIO_FLAG_TXACT:    Data transmit in progress\n  *            @arg SDIO_FLAG_RXACT:    Data receive in progress\n  *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty\n  *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full\n  *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full\n  *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full\n  *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty\n  *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty\n  *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO\n  *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO\n  *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received\n  * @retval The new state of SDIO_FLAG (SET or RESET).\n  */\n#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->STA &(__FLAG__)) != 0U)\n\n\n/**\n  * @brief  Clears the SDIO pending flags.\n  * @param  __INSTANCE__ : Pointer to SDIO register base\n  * @param  __FLAG__: specifies the flag to clear.\n  *          This parameter can be one or a combination of the following values:\n  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)\n  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\n  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout\n  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout\n  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error\n  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error\n  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)\n  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)\n  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, DATACOUNT, is zero)\n  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)\n  *            @arg SDIO_FLAG_SDIOIT:   SDIO interrupt received\n  * @retval None\n  */\n#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->ICR = (__FLAG__))\n\n/**\n  * @brief  Checks whether the specified SDIO interrupt has occurred or not.\n  * @param  __INSTANCE__ : Pointer to SDIO register base\n  * @param  __INTERRUPT__: specifies the SDIO interrupt source to check.\n  *          This parameter can be one of the following values:\n  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\n  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\n  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\n  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\n  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\n  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt\n  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt\n  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt\n  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt\n  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt\n  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt\n  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt\n  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt\n  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\n  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt\n  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt\n  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt\n  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt\n  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt\n  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt\n  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt\n  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt\n  * @retval The new state of SDIO_IT (SET or RESET).\n  */\n#define __SDIO_GET_IT  (__INSTANCE__, __INTERRUPT__)  (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))\n\n/**\n  * @brief  Clears the SDIO's interrupt pending bits.\n  * @param  __INSTANCE__ : Pointer to SDIO register base\n  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.\n  *          This parameter can be one or a combination of the following values:\n  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\n  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\n  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\n  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\n  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\n  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt\n  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt\n  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt\n  *            @arg SDIO_IT_DATAEND:  Data end (data counter, DATACOUNT, is zero) interrupt\n  *            @arg SDIO_IT_SDIOIT:   SDIO interrupt received interrupt\n  * @retval None\n  */\n#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->ICR = (__INTERRUPT__))\n\n/**\n  * @brief  Enable Start the SD I/O Read Wait operation.\n  * @param  __INSTANCE__ : Pointer to SDIO register base\n  * @retval None\n  */\n#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)\n\n/**\n  * @brief  Disable Start the SD I/O Read Wait operations.\n  * @param  __INSTANCE__ : Pointer to SDIO register base\n  * @retval None\n  */\n#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)\n\n/**\n  * @brief  Enable Start the SD I/O Read Wait operation.\n  * @param  __INSTANCE__ : Pointer to SDIO register base\n  * @retval None\n  */\n#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)\n\n/**\n  * @brief  Disable Stop the SD I/O Read Wait operations.\n  * @param  __INSTANCE__ : Pointer to SDIO register base\n  * @retval None\n  */\n#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)\n\n/**\n  * @brief  Enable the SD I/O Mode Operation.\n  * @param  __INSTANCE__ : Pointer to SDIO register base\n  * @retval None\n  */\n#define __SDIO_OPERATION_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)\n\n/**\n  * @brief  Disable the SD I/O Mode Operation.\n  * @param  __INSTANCE__ : Pointer to SDIO register base\n  * @retval None\n  */\n#define __SDIO_OPERATION_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)\n\n/**\n  * @brief  Enable the SD I/O Suspend command sending.\n  * @param  __INSTANCE__ : Pointer to SDIO register base\n  * @retval None\n  */\n#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)\n\n/**\n  * @brief  Disable the SD I/O Suspend command sending.\n  * @param  __INSTANCE__ : Pointer to SDIO register base\n  * @retval None\n  */\n#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)\n\n#if defined(SDIO_CMD_CEATACMD)\n/**\n  * @brief  Enable the command completion signal.\n  * @retval None\n  */\n#define __SDIO_CEATA_CMD_COMPLETION_ENABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)\n\n/**\n  * @brief  Disable the command completion signal.\n  * @retval None\n  */\n#define __SDIO_CEATA_CMD_COMPLETION_DISABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)\n\n/**\n  * @brief  Enable the CE-ATA interrupt.\n  * @retval None\n  */\n#define __SDIO_CEATA_ENABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U)\n\n/**\n  * @brief  Disable the CE-ATA interrupt.\n  * @retval None\n  */\n#define __SDIO_CEATA_DISABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U)\n\n/**\n  * @brief  Enable send CE-ATA command (CMD61).\n  * @retval None\n  */\n#define __SDIO_CEATA_SENDCMD_ENABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)\n\n/**\n  * @brief  Disable send CE-ATA command (CMD61).\n  * @retval None\n  */\n#define __SDIO_CEATA_SENDCMD_DISABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)\n#endif /* SDIO_CMD_CEATACMD */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup SDMMC_LL_Exported_Functions\n  * @{\n  */\n\n/* Initialization/de-initialization functions  **********************************/\n/** @addtogroup HAL_SDMMC_LL_Group1\n  * @{\n  */\nHAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);\n/**\n  * @}\n  */\n\n/* I/O operation functions  *****************************************************/\n/** @addtogroup HAL_SDMMC_LL_Group2\n  * @{\n  */\nuint32_t          SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);\nHAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);\n/**\n  * @}\n  */\n\n/* Peripheral Control functions  ************************************************/\n/** @addtogroup HAL_SDMMC_LL_Group3\n  * @{\n  */\nHAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);\nHAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);\nuint32_t          SDIO_GetPowerState(SDIO_TypeDef *SDIOx);\n\n/* Command path state machine (CPSM) management functions */\nHAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command);\nuint8_t           SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);\nuint32_t          SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);\n\n/* Data path state machine (DPSM) management functions */\nHAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data);\nuint32_t          SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);\nuint32_t          SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);\n\n/* SDMMC Cards mode management functions */\nHAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);\n\n/* SDMMC Commands management functions */\nuint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);\nuint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);\nuint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);\nuint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);\nuint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);\nuint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);\nuint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);\nuint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);\nuint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);\nuint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);\nuint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);\nuint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);\nuint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);\nuint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);\nuint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);\nuint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);\nuint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);\nuint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);\nuint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);\nuint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);\nuint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA);\nuint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);\nuint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);\nuint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);\nuint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\n          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\n          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_LL_SDMMC_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_ll_system.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_system.h\n  * @author  MCD Application Team\n  * @version V1.7.1\n  * @date    14-April-2017\n  * @brief   Header file of SYSTEM LL module.\n  @verbatim\n  ==============================================================================\n                     ##### How to use this driver #####\n  ==============================================================================\n    [..]\n    The LL SYSTEM driver contains a set of generic APIs that can be\n    used by user:\n      (+) Some of the FLASH features need to be handled in the SYSTEM file.\n      (+) Access to DBGCMU registers\n      (+) Access to SYSCFG registers\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_LL_SYSTEM_H\n#define __STM32F4xx_LL_SYSTEM_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)\n\n/** @defgroup SYSTEM_LL SYSTEM\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants\n  * @{\n  */\n\n/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP\n* @{\n*/\n#define LL_SYSCFG_REMAP_FLASH              (uint32_t)0x00000000                                  /*!< Main Flash memory mapped at 0x00000000              */\n#define LL_SYSCFG_REMAP_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0                              /*!< System Flash memory mapped at 0x00000000            */\n#if defined(FSMC_Bank1)\n#define LL_SYSCFG_REMAP_FSMC               SYSCFG_MEMRMP_MEM_MODE_1                              /*!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000                          */\n#endif /* FSMC_Bank1 */\n#if defined(FMC_Bank1)\n#define LL_SYSCFG_REMAP_FMC                SYSCFG_MEMRMP_MEM_MODE_1                              /*!< FMC(NOR/PSRAM 1 and 2) mapped at 0x00000000                          */\n#endif /* FMC_Bank1 */\n#define LL_SYSCFG_REMAP_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000                          */\n/**\n  * @}\n  */\n\n#if defined(SYSCFG_PMC_MII_RMII_SEL)\n /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC\n* @{\n*/\n#define LL_SYSCFG_PMC_ETHMII               (uint32_t)0x00000000                                /*!< ETH Media MII interface */\n#define LL_SYSCFG_PMC_ETHRMII              (uint32_t)SYSCFG_PMC_MII_RMII_SEL                   /*!< ETH Media RMII interface */\n\n/**\n  * @}\n  */\n#endif /* SYSCFG_PMC_MII_RMII_SEL */\n\n\n\n#if defined(SYSCFG_MEMRMP_UFB_MODE)\n/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE\n  * @{\n  */\n#define LL_SYSCFG_BANKMODE_BANK1          (uint32_t)0x00000000       /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM)\n                                                                      and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/\n#define LL_SYSCFG_BANKMODE_BANK2          SYSCFG_MEMRMP_UFB_MODE     /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM)\n                                                                      and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */\n/**\n  * @}\n  */\n#endif /* SYSCFG_MEMRMP_UFB_MODE */\n/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS\n  * @{\n  */\n#if defined(SYSCFG_CFGR_FMPI2C1_SCL)\n#define LL_SYSCFG_I2C_FASTMODEPLUS_SCL         SYSCFG_CFGR_FMPI2C1_SCL   /*!< Enable Fast Mode Plus on FMPI2C_SCL pin */\n#define LL_SYSCFG_I2C_FASTMODEPLUS_SDA         SYSCFG_CFGR_FMPI2C1_SDA   /*!< Enable Fast Mode Plus on FMPI2C_SDA pin*/\n#endif /* SYSCFG_CFGR_FMPI2C1_SCL */\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT\n  * @{\n  */\n#define LL_SYSCFG_EXTI_PORTA               (uint32_t)0               /*!< EXTI PORT A                        */\n#define LL_SYSCFG_EXTI_PORTB               (uint32_t)1               /*!< EXTI PORT B                        */\n#define LL_SYSCFG_EXTI_PORTC               (uint32_t)2               /*!< EXTI PORT C                        */\n#define LL_SYSCFG_EXTI_PORTD               (uint32_t)3               /*!< EXTI PORT D                        */\n#define LL_SYSCFG_EXTI_PORTE               (uint32_t)4               /*!< EXTI PORT E                        */\n#if defined(GPIOF)\n#define LL_SYSCFG_EXTI_PORTF               (uint32_t)5               /*!< EXTI PORT F                        */\n#endif /* GPIOF */\n#if defined(GPIOG)\n#define LL_SYSCFG_EXTI_PORTG               (uint32_t)6               /*!< EXTI PORT G                        */\n#endif /* GPIOG */\n#define LL_SYSCFG_EXTI_PORTH               (uint32_t)7               /*!< EXTI PORT H                        */\n#if defined(GPIOI)\n#define LL_SYSCFG_EXTI_PORTI               (uint32_t)8               /*!< EXTI PORT I                        */\n#endif /* GPIOI */\n#if defined(GPIOJ)\n#define LL_SYSCFG_EXTI_PORTJ               (uint32_t)9               /*!< EXTI PORT J                        */\n#endif /* GPIOJ */\n#if defined(GPIOK)\n#define LL_SYSCFG_EXTI_PORTK               (uint32_t)10              /*!< EXTI PORT k                        */\n#endif /* GPIOK */\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE\n  * @{\n  */\n#define LL_SYSCFG_EXTI_LINE0               (uint32_t)(0x000FU << 16 | 0)  /*!< EXTI_POSITION_0  | EXTICR[0] */\n#define LL_SYSCFG_EXTI_LINE1               (uint32_t)(0x00F0U << 16 | 0)  /*!< EXTI_POSITION_4  | EXTICR[0] */\n#define LL_SYSCFG_EXTI_LINE2               (uint32_t)(0x0F00U << 16 | 0)  /*!< EXTI_POSITION_8  | EXTICR[0] */\n#define LL_SYSCFG_EXTI_LINE3               (uint32_t)(0xF000U << 16 | 0)  /*!< EXTI_POSITION_12 | EXTICR[0] */\n#define LL_SYSCFG_EXTI_LINE4               (uint32_t)(0x000FU << 16 | 1)  /*!< EXTI_POSITION_0  | EXTICR[1] */\n#define LL_SYSCFG_EXTI_LINE5               (uint32_t)(0x00F0U << 16 | 1)  /*!< EXTI_POSITION_4  | EXTICR[1] */\n#define LL_SYSCFG_EXTI_LINE6               (uint32_t)(0x0F00U << 16 | 1)  /*!< EXTI_POSITION_8  | EXTICR[1] */\n#define LL_SYSCFG_EXTI_LINE7               (uint32_t)(0xF000U << 16 | 1)  /*!< EXTI_POSITION_12 | EXTICR[1] */\n#define LL_SYSCFG_EXTI_LINE8               (uint32_t)(0x000FU << 16 | 2)  /*!< EXTI_POSITION_0  | EXTICR[2] */\n#define LL_SYSCFG_EXTI_LINE9               (uint32_t)(0x00F0U << 16 | 2)  /*!< EXTI_POSITION_4  | EXTICR[2] */\n#define LL_SYSCFG_EXTI_LINE10              (uint32_t)(0x0F00U << 16 | 2)  /*!< EXTI_POSITION_8  | EXTICR[2] */\n#define LL_SYSCFG_EXTI_LINE11              (uint32_t)(0xF000U << 16 | 2)  /*!< EXTI_POSITION_12 | EXTICR[2] */\n#define LL_SYSCFG_EXTI_LINE12              (uint32_t)(0x000FU << 16 | 3)  /*!< EXTI_POSITION_0  | EXTICR[3] */\n#define LL_SYSCFG_EXTI_LINE13              (uint32_t)(0x00F0U << 16 | 3)  /*!< EXTI_POSITION_4  | EXTICR[3] */\n#define LL_SYSCFG_EXTI_LINE14              (uint32_t)(0x0F00U << 16 | 3)  /*!< EXTI_POSITION_8  | EXTICR[3] */\n#define LL_SYSCFG_EXTI_LINE15              (uint32_t)(0xF000U << 16 | 3)  /*!< EXTI_POSITION_12 | EXTICR[3] */\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK\n  * @{\n  */\n#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)\n#define LL_SYSCFG_TIMBREAK_LOCKUP          SYSCFG_CFGR2_LOCKUP_LOCK   /*!< Enables and locks the LOCKUP output of CortexM4\n                                                                      with Break Input of TIM1/8                                    */\n#define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR2_PVD_LOCK      /*!< Enables and locks the PVD connection with TIM1/8 Break Input\n                                                                      and also the PVDE and PLS bits of the Power Control Interface  */\n#endif /* SYSCFG_CFGR2_CLL */\n/**\n  * @}\n  */\n\n#if defined(SYSCFG_MCHDLYCR_BSCKSEL)\n/** @defgroup SYSTEM_LL_DFSDM_BitStream_ClockSource SYSCFG MCHDLY BCKKSEL\n  * @{\n  */\n#define LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1          (uint32_t)0x00000000\n#define LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2           SYSCFG_MCHDLYCR_BSCKSEL\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM_MCHDLYEN              SYSCFG MCHDLY MCHDLYEN\n  * @{\n  */\n#define LL_SYSCFG_DFSDM1_MCHDLYEN                  SYSCFG_MCHDLYCR_MCHDLY1EN\n#define LL_SYSCFG_DFSDM2_MCHDLYEN                  SYSCFG_MCHDLYCR_MCHDLY2EN\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM_DataIn0_Source       SYSCFG MCHDLY DFSDMD0SEL\n  * @{\n  */\n#define LL_SYSCFG_DFSDM1_DataIn0                   SYSCFG_MCHDLYCR_DFSDM1D0SEL\n#define LL_SYSCFG_DFSDM2_DataIn0                   SYSCFG_MCHDLYCR_DFSDM2D0SEL\n\n#define LL_SYSCFG_DFSDM1_DataIn0_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | 0x00000000)\n#define LL_SYSCFG_DFSDM1_DataIn0_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D0SEL)\n#define LL_SYSCFG_DFSDM2_DataIn0_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | 0x00000000)\n#define LL_SYSCFG_DFSDM2_DataIn0_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D0SEL)\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM_DataIn2_Source       SYSCFG MCHDLY DFSDMD2SEL\n  * @{\n  */\n#define LL_SYSCFG_DFSDM1_DataIn2                   SYSCFG_MCHDLYCR_DFSDM1D2SEL\n#define LL_SYSCFG_DFSDM2_DataIn2                   SYSCFG_MCHDLYCR_DFSDM2D2SEL\n\n#define LL_SYSCFG_DFSDM1_DataIn2_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | 0x00000000)\n#define LL_SYSCFG_DFSDM1_DataIn2_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D2SEL)\n#define LL_SYSCFG_DFSDM2_DataIn2_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | 0x00000000)\n#define LL_SYSCFG_DFSDM2_DataIn2_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D2SEL)\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC2_BitstreamDistribution  SYSCFG MCHDLY DFSDM1CK02SEL\n  * @{\n  */\n#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0           (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2           SYSCFG_MCHDLYCR_DFSDM1CK02SEL\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC1_BitstreamDistribution  SYSCFG MCHDLY DFSDM1CK13SEL\n  * @{\n  */\n#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1           (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3           SYSCFG_MCHDLYCR_DFSDM1CK13SEL\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM1_CLKIN_SourceSelection SYSCFG MCHDLY DFSDMCFG\n  * @{\n  */\n#define LL_SYSCFG_DFSDM1_CKIN_PAD                 (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM1_CKIN_DM                  SYSCFG_MCHDLYCR_DFSDM1CFG\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM1_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM1CKOSEL\n  * @{\n  */\n#define LL_SYSCFG_DFSDM1_CKOUT                    (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM1_CKOUT_M27                SYSCFG_MCHDLYCR_DFSDM1CKOSEL\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_DFSDM2_DataIn4_SourceSelection SYSCFG MCHDLY DFSDM2D4SEL\n  * @{\n  */\n#define LL_SYSCFG_DFSDM2_DataIn4_PAD              (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM2_DataIn4_DM               SYSCFG_MCHDLYCR_DFSDM2D4SEL\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM2_DataIn6_SourceSelection SYSCFG MCHDLY DFSDM2D6SEL\n  * @{\n  */\n#define LL_SYSCFG_DFSDM2_DataIn6_PAD              (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM2_DataIn6_DM               SYSCFG_MCHDLYCR_DFSDM2D6SEL\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC4_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK04SEL\n  * @{\n  */\n#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0           (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4           SYSCFG_MCHDLYCR_DFSDM2CK04SEL\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC3_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK15SEL\n  * @{\n  */\n#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1           (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5           SYSCFG_MCHDLYCR_DFSDM2CK15SEL\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC2_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK26SEL\n  * @{\n  */\n#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2           (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6           SYSCFG_MCHDLYCR_DFSDM2CK26SEL\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC1_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK37SEL\n  * @{\n  */\n#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3           (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7           SYSCFG_MCHDLYCR_DFSDM2CK37SEL\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM2_CLKIN_SourceSelection SYSCFG MCHDLY DFSDM2CFG\n  * @{\n  */\n#define LL_SYSCFG_DFSDM2_CKIN_PAD                 (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM2_CKIN_DM                  SYSCFG_MCHDLYCR_DFSDM2CFG\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM2_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM2CKOSEL\n  * @{\n  */\n#define LL_SYSCFG_DFSDM2_CKOUT                    (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM2_CKOUT_M27                SYSCFG_MCHDLYCR_DFSDM2CKOSEL\n/**\n  * @}\n  */\n#endif /* SYSCFG_MCHDLYCR_BSCKSEL */\n\n/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment\n  * @{\n  */\n#define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */\n#define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */\n#define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */\n#define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */\n#define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP\n  * @{\n  */\n#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)\n#define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1_FZ_DBG_TIM2_STOP          /*!< TIM2 counter stopped when core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */\n#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)\n#define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1_FZ_DBG_TIM3_STOP          /*!< TIM3 counter stopped when core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */\n#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)\n#define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1_FZ_DBG_TIM4_STOP          /*!< TIM4 counter stopped when core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */\n#define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1_FZ_DBG_TIM5_STOP          /*!< TIM5 counter stopped when core is halted */\n#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)\n#define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1_FZ_DBG_TIM6_STOP          /*!< TIM6 counter stopped when core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */\n#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)\n#define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1_FZ_DBG_TIM7_STOP          /*!< TIM7 counter stopped when core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */\n#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)\n#define LL_DBGMCU_APB1_GRP1_TIM12_STOP     DBGMCU_APB1_FZ_DBG_TIM12_STOP         /*!< TIM12 counter stopped when core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */\n#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)\n#define LL_DBGMCU_APB1_GRP1_TIM13_STOP     DBGMCU_APB1_FZ_DBG_TIM13_STOP         /*!< TIM13 counter stopped when core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */\n#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)\n#define LL_DBGMCU_APB1_GRP1_TIM14_STOP     DBGMCU_APB1_FZ_DBG_TIM14_STOP         /*!< TIM14 counter stopped when core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */\n#if defined(DBGMCU_APB1_FZ_DBG_LPTIM_STOP)\n#define LL_DBGMCU_APB1_GRP1_LPTIM_STOP     DBGMCU_APB1_FZ_DBG_LPTIM_STOP         /*!< LPTIM counter stopped when core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_LPTIM_STOP */\n#define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_APB1_FZ_DBG_RTC_STOP           /*!< RTC counter stopped when core is halted */\n#define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1_FZ_DBG_WWDG_STOP          /*!< Debug Window Watchdog stopped when Core is halted */\n#define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1_FZ_DBG_IWDG_STOP          /*!< Debug Independent Watchdog stopped when Core is halted */\n#define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */\n#define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */\n#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)\n#define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */\n#if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)\n#define LL_DBGMCU_APB1_GRP1_I2C4_STOP      DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS timeout mode stopped when Core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */\n#if defined(DBGMCU_APB1_FZ_DBG_CAN1_STOP)\n#define LL_DBGMCU_APB1_GRP1_CAN1_STOP      DBGMCU_APB1_FZ_DBG_CAN1_STOP          /*!< CAN1 debug stopped when Core is halted  */\n#endif /* DBGMCU_APB1_FZ_DBG_CAN1_STOP */\n#if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP)\n#define LL_DBGMCU_APB1_GRP1_CAN2_STOP      DBGMCU_APB1_FZ_DBG_CAN2_STOP          /*!< CAN2 debug stopped when Core is halted  */\n#endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */\n#if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP)\n#define LL_DBGMCU_APB1_GRP1_CAN3_STOP      DBGMCU_APB1_FZ_DBG_CAN3_STOP          /*!< CAN3 debug stopped when Core is halted  */\n#endif /* DBGMCU_APB1_FZ_DBG_CAN3_STOP */\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP\n  * @{\n  */\n#define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2_FZ_DBG_TIM1_STOP   /*!< TIM1 counter stopped when core is halted */\n#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)\n#define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2_FZ_DBG_TIM8_STOP   /*!< TIM8 counter stopped when core is halted */\n#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */\n#define LL_DBGMCU_APB2_GRP1_TIM9_STOP      DBGMCU_APB2_FZ_DBG_TIM9_STOP   /*!< TIM9 counter stopped when core is halted */\n#if defined(DBGMCU_APB2_FZ_DBG_TIM10_STOP)\n#define LL_DBGMCU_APB2_GRP1_TIM10_STOP     DBGMCU_APB2_FZ_DBG_TIM10_STOP   /*!< TIM10 counter stopped when core is halted */\n#endif /* DBGMCU_APB2_FZ_DBG_TIM10_STOP */\n#define LL_DBGMCU_APB2_GRP1_TIM11_STOP     DBGMCU_APB2_FZ_DBG_TIM11_STOP   /*!< TIM11 counter stopped when core is halted */\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY\n  * @{\n  */\n#define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */\n#define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */\n#define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */\n#define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */\n#define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */\n#define LL_FLASH_LATENCY_5                 FLASH_ACR_LATENCY_5WS   /*!< FLASH five wait state */\n#define LL_FLASH_LATENCY_6                 FLASH_ACR_LATENCY_6WS   /*!< FLASH six wait state */\n#define LL_FLASH_LATENCY_7                 FLASH_ACR_LATENCY_7WS   /*!< FLASH seven wait states */\n#define LL_FLASH_LATENCY_8                 FLASH_ACR_LATENCY_8WS   /*!< FLASH eight wait states */\n#define LL_FLASH_LATENCY_9                 FLASH_ACR_LATENCY_9WS   /*!< FLASH nine wait states */\n#define LL_FLASH_LATENCY_10                FLASH_ACR_LATENCY_10WS   /*!< FLASH ten wait states */\n#define LL_FLASH_LATENCY_11                FLASH_ACR_LATENCY_11WS   /*!< FLASH eleven wait states */\n#define LL_FLASH_LATENCY_12                FLASH_ACR_LATENCY_12WS   /*!< FLASH twelve wait states */\n#define LL_FLASH_LATENCY_13                FLASH_ACR_LATENCY_13WS   /*!< FLASH thirteen wait states */\n#define LL_FLASH_LATENCY_14                FLASH_ACR_LATENCY_14WS   /*!< FLASH fourteen wait states */\n#define LL_FLASH_LATENCY_15                FLASH_ACR_LATENCY_15WS   /*!< FLASH fifteen wait states */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions\n  * @{\n  */\n\n/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG\n  * @{\n  */\n/**\n  * @brief  Set memory mapping at address 0x00000000\n  * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_SetRemapMemory\n  * @param  Memory This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_REMAP_FLASH\n  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH\n  *         @arg @ref LL_SYSCFG_REMAP_SRAM\n  *         @arg @ref LL_SYSCFG_REMAP_FSMC (*)\n  *         @arg @ref LL_SYSCFG_REMAP_FMC (*)\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)\n{\n  MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);\n}\n\n/**\n  * @brief  Get memory mapping at address 0x00000000\n  * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_GetRemapMemory\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_REMAP_FLASH\n  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH\n  *         @arg @ref LL_SYSCFG_REMAP_SRAM\n  *         @arg @ref LL_SYSCFG_REMAP_FSMC (*)\n  *         @arg @ref LL_SYSCFG_REMAP_FMC (*)\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));\n}\n\n#if defined(SYSCFG_MEMRMP_SWP_FMC)\n/**\n  * @brief  Enables the FMC Memory Mapping Swapping\n  * @rmtoll SYSCFG_MEMRMP SWP_FMC      LL_SYSCFG_EnableFMCMemorySwapping\n  * @note   SDRAM is accessible at 0x60000000 and NOR/RAM\n  *         is accessible at 0xC0000000\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void)\n{\n  SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0);\n}\n\n/**\n  * @brief  Disables the FMC Memory Mapping Swapping\n  * @rmtoll SYSCFG_MEMRMP SWP_FMC      LL_SYSCFG_DisableFMCMemorySwapping\n  * @note   SDRAM is accessible at 0xC0000000 (default mapping)\n  *         and NOR/RAM is accessible at 0x60000000 (default mapping)\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void)\n{\n  CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC);\n}\n\n#endif /* SYSCFG_MEMRMP_SWP_FMC */\n/**\n  * @brief  Enables the Compensation cell Power Down\n  * @rmtoll SYSCFG_CMPCR CMP_PD      LL_SYSCFG_EnableCompensationCell\n  * @note   The I/O compensation cell can be used only when the device supply\n  *         voltage ranges from 2.4 to 3.6 V\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)\n{\n  SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);\n}\n\n/**\n  * @brief  Disables the Compensation cell Power Down\n  * @rmtoll SYSCFG_CMPCR CMP_PD      LL_SYSCFG_DisableCompensationCell\n  * @note   The I/O compensation cell can be used only when the device supply\n  *         voltage ranges from 2.4 to 3.6 V\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)\n{\n  CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);\n}\n\n/**\n  * @brief  Get Compensation Cell ready Flag\n  * @rmtoll SYSCFG_CMPCR READY  LL_SYSCFG_IsActiveFlag_CMPCR\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)\n{\n  return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));\n}\n\n#if defined(SYSCFG_PMC_MII_RMII_SEL)\n/**\n  * @brief  Select Ethernet PHY interface\n  * @rmtoll SYSCFG_PMC MII_RMII_SEL       LL_SYSCFG_SetPHYInterface\n  * @param  Interface This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_PMC_ETHMII\n  *         @arg @ref LL_SYSCFG_PMC_ETHRMII\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)\n{\n  MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface);\n}\n\n/**\n  * @brief  Get Ethernet PHY interface\n  * @rmtoll SYSCFG_PMC MII_RMII_SEL       LL_SYSCFG_GetPHYInterface\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_PMC_ETHMII\n  *         @arg @ref LL_SYSCFG_PMC_ETHRMII\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));\n}\n#endif /* SYSCFG_PMC_MII_RMII_SEL */\n\n\n\n#if defined(SYSCFG_MEMRMP_UFB_MODE)\n/**\n  * @brief  Select Flash bank mode (Bank flashed at 0x08000000)\n  * @rmtoll SYSCFG_MEMRMP UFB_MODE       LL_SYSCFG_SetFlashBankMode\n  * @param  Bank This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1\n  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)\n{\n  MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE, Bank);\n}\n\n/**\n  * @brief  Get Flash bank mode (Bank flashed at 0x08000000)\n  * @rmtoll SYSCFG_MEMRMP UFB_MODE       LL_SYSCFG_GetFlashBankMode\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1\n  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE));\n}\n#endif /* SYSCFG_MEMRMP_UFB_MODE */\n\n#if defined(SYSCFG_CFGR_FMPI2C1_SCL)\n/**\n  * @brief  Enable the I2C fast mode plus driving capability.\n  * @rmtoll SYSCFG_CFGR FMPI2C1_SCL   LL_SYSCFG_EnableFastModePlus\\n\n  *         SYSCFG_CFGR FMPI2C1_SDA   LL_SYSCFG_EnableFastModePlus\n  * @param  ConfigFastModePlus This parameter can be a combination of the following values:\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA\n  *         (*) value not defined in all devices\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)\n{\n  SET_BIT(SYSCFG->CFGR, ConfigFastModePlus);\n}\n\n/**\n  * @brief  Disable the I2C fast mode plus driving capability.\n  * @rmtoll SYSCFG_CFGR FMPI2C1_SCL  LL_SYSCFG_DisableFastModePlus\\n\n  *         SYSCFG_CFGR FMPI2C1_SDA  LL_SYSCFG_DisableFastModePlus\\n\n  * @param  ConfigFastModePlus This parameter can be a combination of the following values:\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA\n  *         (*) value not defined in all devices\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)\n{\n  CLEAR_BIT(SYSCFG->CFGR, ConfigFastModePlus);\n}\n#endif /* SYSCFG_CFGR_FMPI2C1_SCL */\n\n/**\n  * @brief  Configure source input for the EXTI external interrupt.\n  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_SetEXTISource\\n\n  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\\n\n  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\\n\n  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource\n  * @param  Port This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_EXTI_PORTA\n  *         @arg @ref LL_SYSCFG_EXTI_PORTB\n  *         @arg @ref LL_SYSCFG_EXTI_PORTC\n  *         @arg @ref LL_SYSCFG_EXTI_PORTD\n  *         @arg @ref LL_SYSCFG_EXTI_PORTE\n  *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)\n  *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)\n  *         @arg @ref LL_SYSCFG_EXTI_PORTH\n  *\n  *         (*) value not defined in all devices\n  * @param  Line This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_EXTI_LINE0\n  *         @arg @ref LL_SYSCFG_EXTI_LINE1\n  *         @arg @ref LL_SYSCFG_EXTI_LINE2\n  *         @arg @ref LL_SYSCFG_EXTI_LINE3\n  *         @arg @ref LL_SYSCFG_EXTI_LINE4\n  *         @arg @ref LL_SYSCFG_EXTI_LINE5\n  *         @arg @ref LL_SYSCFG_EXTI_LINE6\n  *         @arg @ref LL_SYSCFG_EXTI_LINE7\n  *         @arg @ref LL_SYSCFG_EXTI_LINE8\n  *         @arg @ref LL_SYSCFG_EXTI_LINE9\n  *         @arg @ref LL_SYSCFG_EXTI_LINE10\n  *         @arg @ref LL_SYSCFG_EXTI_LINE11\n  *         @arg @ref LL_SYSCFG_EXTI_LINE12\n  *         @arg @ref LL_SYSCFG_EXTI_LINE13\n  *         @arg @ref LL_SYSCFG_EXTI_LINE14\n  *         @arg @ref LL_SYSCFG_EXTI_LINE15\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)\n{\n  MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));\n}\n\n/**\n  * @brief  Get the configured defined for specific EXTI Line\n  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\\n\n  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\\n\n  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\\n\n  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource\n  * @param  Line This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_EXTI_LINE0\n  *         @arg @ref LL_SYSCFG_EXTI_LINE1\n  *         @arg @ref LL_SYSCFG_EXTI_LINE2\n  *         @arg @ref LL_SYSCFG_EXTI_LINE3\n  *         @arg @ref LL_SYSCFG_EXTI_LINE4\n  *         @arg @ref LL_SYSCFG_EXTI_LINE5\n  *         @arg @ref LL_SYSCFG_EXTI_LINE6\n  *         @arg @ref LL_SYSCFG_EXTI_LINE7\n  *         @arg @ref LL_SYSCFG_EXTI_LINE8\n  *         @arg @ref LL_SYSCFG_EXTI_LINE9\n  *         @arg @ref LL_SYSCFG_EXTI_LINE10\n  *         @arg @ref LL_SYSCFG_EXTI_LINE11\n  *         @arg @ref LL_SYSCFG_EXTI_LINE12\n  *         @arg @ref LL_SYSCFG_EXTI_LINE13\n  *         @arg @ref LL_SYSCFG_EXTI_LINE14\n  *         @arg @ref LL_SYSCFG_EXTI_LINE15\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_EXTI_PORTA\n  *         @arg @ref LL_SYSCFG_EXTI_PORTB\n  *         @arg @ref LL_SYSCFG_EXTI_PORTC\n  *         @arg @ref LL_SYSCFG_EXTI_PORTD\n  *         @arg @ref LL_SYSCFG_EXTI_PORTE\n  *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)\n  *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)\n  *         @arg @ref LL_SYSCFG_EXTI_PORTH\n  *         (*) value not defined in all devices\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));\n}\n\n#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)\n/**\n  * @brief  Set connections to TIM1/8 break inputs\n  * @rmtoll SYSCFG_CFGR2 LockUp Lock           LL_SYSCFG_SetTIMBreakInputs \\n\n  *         SYSCFG_CFGR2 PVD Lock              LL_SYSCFG_SetTIMBreakInputs\n  * @param  Break This parameter can be a combination of the following values:\n  *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP\n  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)\n{\n  MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK, Break);\n}\n\n/**\n  * @brief  Get connections to TIM1/8 Break inputs\n  * @rmtoll SYSCFG_CFGR2 LockUp Lock           LL_SYSCFG_SetTIMBreakInputs \\n\n  *         SYSCFG_CFGR2 PVD Lock              LL_SYSCFG_SetTIMBreakInputs\n  * @retval Returned value can be can be a combination of the following values:\n  *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP\n  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK));\n}\n#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */\n#if defined(SYSCFG_MCHDLYCR_BSCKSEL)\n/**\n  * @brief  Select the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.\n  * @rmtoll SYSCFG_MCHDLYCR BSCKSEL        LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection\n  * @param  ClockSource This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2\n  *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection(uint32_t ClockSource)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL, ClockSource);\n}\n/**\n  * @brief  Get the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.\n  * @rmtoll SYSCFG_MCHDLYCR BSCKSEL       LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2\n  *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL));\n}\n/**\n  * @brief  Enables the DFSDM1 or DFSDM2 Delay clock\n  * @rmtoll SYSCFG_MCHDLYCR MCHDLYEN      LL_SYSCFG_DFSDM_EnableDelayClock\n  * @param MCHDLY This paramater can be one of the following values\n  *         @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN\n  *         @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM_EnableDelayClock(uint32_t MCHDLY)\n{\n  SET_BIT(SYSCFG->MCHDLYCR, MCHDLY);\n}\n\n/**\n  * @brief  Disables the DFSDM1 or the DFSDM2 Delay clock\n  * @rmtoll SYSCFG_MCHDLYCR MCHDLY1EN      LL_SYSCFG_DFSDM1_DisableDelayClock\n  * @param MCHDLY This paramater can be one of the following values\n  *         @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN\n  *         @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM_DisableDelayClock(uint32_t MCHDLY)\n{\n  CLEAR_BIT(SYSCFG->MCHDLYCR, MCHDLY);\n}\n\n/**\n  * @brief  Select the source for DFSDM1 or DFSDM2 DatIn0\n  * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL        LL_SYSCFG_DFSDM_SetDataIn0Source\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn0Source(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));\n}\n/**\n  * @brief  Get the source for DFSDM1 or DFSDM2 DatIn0.\n  * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL       LL_SYSCFG_DFSDM_GetDataIn0Source\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn0Source(uint32_t Source)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));\n}\n/**\n  * @brief  Select the source for DFSDM1 or DFSDM2 DatIn2\n  * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL        LL_SYSCFG_DFSDM_SetDataIn2Source\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn2Source(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));\n}\n/**\n  * @brief  Get the source for DFSDM1 or DFSDM2 DatIn2.\n  * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL       LL_SYSCFG_DFSDM_GetDataIn2Source\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn2Source(uint32_t Source)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));\n}\n\n/**\n  * @brief  Select the distribution of the bitsream lock gated by TIM4 OC2\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK02SEL        LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0\n  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL, Source);\n}\n/**\n  * @brief  Get the distribution of the bitsream lock gated by TIM4 OC2\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL       LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0\n  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL));\n}\n\n/**\n  * @brief  Select the distribution of the bitsream lock gated by TIM4 OC1\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK13SEL        LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1\n  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL, Source);\n}\n/**\n  * @brief  Get the distribution of the bitsream lock gated by TIM4 OC1\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL       LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1\n  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL));\n}\n\n/**\n  * @brief  Select the DFSDM1 Clock In\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG        LL_SYSCFG_DFSDM1_SetClockInSourceSelection\n  * @param  ClockSource This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockInSourceSelection(uint32_t ClockSource)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG, ClockSource);\n}\n/**\n  * @brief  GET the DFSDM1 Clock In\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG       LL_SYSCFG_DFSDM1_GetClockInSourceSelection\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockInSourceSelection(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG));\n}\n\n/**\n  * @brief  Select the DFSDM1 Clock Out\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL        LL_SYSCFG_DFSDM1_SetClockOutSourceSelection\n  * @param  ClockSource This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT\n  *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockOutSourceSelection(uint32_t ClockSource)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL, ClockSource);\n}\n/**\n  * @brief  GET the DFSDM1 Clock Out\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL       LL_SYSCFG_DFSDM1_GetClockOutSourceSelection\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT\n  *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockOutSourceSelection(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL));\n}\n\n/**\n  * @brief  Enables the DFSDM2 Delay clock\n  * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN      LL_SYSCFG_DFSDM2_EnableDelayClock\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_EnableDelayClock(void)\n{\n  SET_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);\n}\n\n/**\n  * @brief  Disables the DFSDM2 Delay clock\n  * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN      LL_SYSCFG_DFSDM2_DisableDelayClock\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_DisableDelayClock(void)\n{\n  CLEAR_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);\n}\n/**\n  * @brief  Select the source for DFSDM2 DatIn0\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL        LL_SYSCFG_DFSDM2_SetDataIn0Source\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn0Source(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL, Source);\n}\n/**\n  * @brief  Get the source for DFSDM2 DatIn0.\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL       LL_SYSCFG_DFSDM2_GetDataIn0Source\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn0Source(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL));\n}\n\n/**\n  * @brief  Select the source for DFSDM2 DatIn2\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL        LL_SYSCFG_DFSDM2_SetDataIn2Source\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn2Source(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL, Source);\n}\n/**\n  * @brief  Get the source for DFSDM2 DatIn2.\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL       LL_SYSCFG_DFSDM2_GetDataIn2Source\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn2Source(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL));\n}\n\n/**\n  * @brief  Select the source for DFSDM2 DatIn4\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL        LL_SYSCFG_DFSDM2_SetDataIn4Source\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn4Source(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL, Source);\n}\n/**\n  * @brief  Get the source for DFSDM2 DatIn4.\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL       LL_SYSCFG_DFSDM2_GetDataIn4Source\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn4Source(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL));\n}\n\n/**\n  * @brief  Select the source for DFSDM2 DatIn6\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL        LL_SYSCFG_DFSDM2_SetDataIn6Source\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn6Source(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL, Source);\n}\n/**\n  * @brief  Get the source for DFSDM2 DatIn6.\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL       LL_SYSCFG_DFSDM2_GetDataIn6Source\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn6Source(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL));\n}\n\n/**\n  * @brief  Select the distribution of the bitsream lock gated by TIM3 OC4\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL        LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL, Source);\n}\n/**\n  * @brief  Get the distribution of the bitsream lock gated by TIM3 OC4\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL       LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL));\n}\n\n/**\n  * @brief  Select the distribution of the bitsream lock gated by TIM3 OC3\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK15SEL        LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL, Source);\n}\n/**\n  * @brief  Get the distribution of the bitsream lock gated by TIM3 OC4\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL       LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL));\n}\n\n/**\n  * @brief  Select the distribution of the bitsream lock gated by TIM3 OC2\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK26SEL        LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL, Source);\n}\n/**\n  * @brief  Get the distribution of the bitsream lock gated by TIM3 OC2\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL       LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL));\n}\n\n/**\n  * @brief  Select the distribution of the bitsream lock gated by TIM3 OC1\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL        LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL, Source);\n}\n/**\n  * @brief  Get the distribution of the bitsream lock gated by TIM3 OC1\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL       LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL));\n}\n\n/**\n  * @brief  Select the DFSDM2 Clock In\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG        LL_SYSCFG_DFSDM2_SetClockInSourceSelection\n  * @param  ClockSource This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockInSourceSelection(uint32_t ClockSource)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG, ClockSource);\n}\n/**\n  * @brief  GET the DFSDM2 Clock In\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG       LL_SYSCFG_DFSDM2_GetClockInSourceSelection\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockInSourceSelection(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG));\n}\n\n/**\n  * @brief  Select the DFSDM2 Clock Out\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL        LL_SYSCFG_DFSDM2_SetClockOutSourceSelection\n  * @param  ClockSource This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT\n  *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockOutSourceSelection(uint32_t ClockSource)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL, ClockSource);\n}\n/**\n  * @brief  GET the DFSDM2 Clock Out\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL       LL_SYSCFG_DFSDM2_GetClockOutSourceSelection\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT\n  *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockOutSourceSelection(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL));\n}\n\n#endif /* SYSCFG_MCHDLYCR_BSCKSEL */\n/**\n  * @}\n  */\n\n\n/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU\n  * @{\n  */\n\n/**\n  * @brief  Return the device identifier\n  * @note For STM32F405/407xx and STM32F415/417xx devices, the device ID is 0x413\n  * @note For STM32F42xxx and STM32F43xxx devices, the device ID is 0x419\n  * @note For STM32F401xx devices, the device ID is 0x423\n  * @note For STM32F401xx devices, the device ID is 0x433\n  * @note For STM32F411xx devices, the device ID is 0x431\n  * @note For STM32F410xx devices, the device ID is 0x458\n  * @note For STM32F412xx devices, the device ID is 0x441\n  * @note For STM32F413xx and STM32423xx devices, the device ID is 0x463\n  * @note For STM32F446xx devices, the device ID is 0x421\n  * @note For STM32F469xx and STM32F479xx devices, the device ID is 0x434\n  * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID\n  * @retval Values between Min_Data=0x00 and Max_Data=0xFFF\n  */\n__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)\n{\n  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));\n}\n\n/**\n  * @brief  Return the device revision identifier\n  * @note This field indicates the revision of the device.\n          For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001, rev1 -> 0x1003, rev2 ->0x1007, revY -> 0x100F for STM32F405/407xx and STM32F415/417xx devices\n          For example, it is read as RevA -> 0x1000, Cat 2 revY -> 0x1003, rev1 -> 0x1007, rev3 ->0x2001 for STM32F42xxx and STM32F43xxx devices\n          For example, it is read as RevZ -> 0x1000, Cat 2 revA -> 0x1001 for STM32F401xB/C devices\n          For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 for STM32F401xD/E devices\n          For example, it is read as RevA -> 0x1000 for STM32F411xx,STM32F413/423xx,STM32F469/423xx, STM32F446xx and STM32F410xx devices\n          For example, it is read as RevZ -> 0x1001, Cat 2 revB -> 0x2000, revC -> 0x3000 for STM32F412xx devices\n  * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID\n  * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF\n  */\n__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)\n{\n  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);\n}\n\n/**\n  * @brief  Enable the Debug Module during SLEEP mode\n  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)\n{\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\n}\n\n/**\n  * @brief  Disable the Debug Module during SLEEP mode\n  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)\n{\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\n}\n\n/**\n  * @brief  Enable the Debug Module during STOP mode\n  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)\n{\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\n}\n\n/**\n  * @brief  Disable the Debug Module during STOP mode\n  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)\n{\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\n}\n\n/**\n  * @brief  Enable the Debug Module during STANDBY mode\n  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)\n{\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\n}\n\n/**\n  * @brief  Disable the Debug Module during STANDBY mode\n  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)\n{\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\n}\n\n/**\n  * @brief  Set Trace pin assignment control\n  * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\\n\n  *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment\n  * @param  PinAssignment This parameter can be one of the following values:\n  *         @arg @ref LL_DBGMCU_TRACE_NONE\n  *         @arg @ref LL_DBGMCU_TRACE_ASYNCH\n  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1\n  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2\n  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)\n{\n  MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);\n}\n\n/**\n  * @brief  Get Trace pin assignment control\n  * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\\n\n  *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DBGMCU_TRACE_NONE\n  *         @arg @ref LL_DBGMCU_TRACE_ASYNCH\n  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1\n  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2\n  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4\n  */\n__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)\n{\n  return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));\n}\n\n/**\n  * @brief  Freeze APB1 peripherals (group1 peripherals)\n  * @rmtoll DBGMCU_APB1_FZ      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_LPTIM_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_I2C3_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_I2C4_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_CAN3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)\n{\n  SET_BIT(DBGMCU->APB1FZ, Periphs);\n}\n\n/**\n  * @brief  Unfreeze APB1 peripherals (group1 peripherals)\n  * @rmtoll DBGMCU_APB1_FZ      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_LPTIM_STOP         LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_I2C3_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_I2C4_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_CAN3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)\n{\n  CLEAR_BIT(DBGMCU->APB1FZ, Periphs);\n}\n\n/**\n  * @brief  Freeze APB2 peripherals\n  * @rmtoll DBGMCU_APB2_FZ      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB2_FZ      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB2_FZ      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB2_FZ      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB2_FZ      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)\n{\n  SET_BIT(DBGMCU->APB2FZ, Periphs);\n}\n\n/**\n  * @brief  Unfreeze APB2 peripherals\n  * @rmtoll DBGMCU_APB2_FZ      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB2_FZ      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB2_FZ      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB2_FZ      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB2_FZ      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)\n{\n  CLEAR_BIT(DBGMCU->APB2FZ, Periphs);\n}\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EF_FLASH FLASH\n  * @{\n  */\n\n/**\n  * @brief  Set FLASH Latency\n  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency\n  * @param  Latency This parameter can be one of the following values:\n  *         @arg @ref LL_FLASH_LATENCY_0\n  *         @arg @ref LL_FLASH_LATENCY_1\n  *         @arg @ref LL_FLASH_LATENCY_2\n  *         @arg @ref LL_FLASH_LATENCY_3\n  *         @arg @ref LL_FLASH_LATENCY_4\n  *         @arg @ref LL_FLASH_LATENCY_5\n  *         @arg @ref LL_FLASH_LATENCY_6\n  *         @arg @ref LL_FLASH_LATENCY_7\n  *         @arg @ref LL_FLASH_LATENCY_8\n  *         @arg @ref LL_FLASH_LATENCY_9\n  *         @arg @ref LL_FLASH_LATENCY_10\n  *         @arg @ref LL_FLASH_LATENCY_11\n  *         @arg @ref LL_FLASH_LATENCY_12\n  *         @arg @ref LL_FLASH_LATENCY_13\n  *         @arg @ref LL_FLASH_LATENCY_14\n  *         @arg @ref LL_FLASH_LATENCY_15\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)\n{\n  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);\n}\n\n/**\n  * @brief  Get FLASH Latency\n  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_FLASH_LATENCY_0\n  *         @arg @ref LL_FLASH_LATENCY_1\n  *         @arg @ref LL_FLASH_LATENCY_2\n  *         @arg @ref LL_FLASH_LATENCY_3\n  *         @arg @ref LL_FLASH_LATENCY_4\n  *         @arg @ref LL_FLASH_LATENCY_5\n  *         @arg @ref LL_FLASH_LATENCY_6\n  *         @arg @ref LL_FLASH_LATENCY_7\n  *         @arg @ref LL_FLASH_LATENCY_8\n  *         @arg @ref LL_FLASH_LATENCY_9\n  *         @arg @ref LL_FLASH_LATENCY_10\n  *         @arg @ref LL_FLASH_LATENCY_11\n  *         @arg @ref LL_FLASH_LATENCY_12\n  *         @arg @ref LL_FLASH_LATENCY_13\n  *         @arg @ref LL_FLASH_LATENCY_14\n  *         @arg @ref LL_FLASH_LATENCY_15\n  */\n__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)\n{\n  return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));\n}\n\n/**\n  * @brief  Enable Prefetch\n  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_EnablePrefetch\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)\n{\n  SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);\n}\n\n/**\n  * @brief  Disable Prefetch\n  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_DisablePrefetch\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)\n{\n  CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);\n}\n\n/**\n  * @brief  Check if Prefetch buffer is enabled\n  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_IsPrefetchEnabled\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)\n{\n  return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));\n}\n\n/**\n  * @brief  Enable Instruction cache\n  * @rmtoll FLASH_ACR    ICEN          LL_FLASH_EnableInstCache\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_EnableInstCache(void)\n{\n  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);\n}\n\n/**\n  * @brief  Disable Instruction cache\n  * @rmtoll FLASH_ACR    ICEN          LL_FLASH_DisableInstCache\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_DisableInstCache(void)\n{\n  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);\n}\n\n/**\n  * @brief  Enable Data cache\n  * @rmtoll FLASH_ACR    DCEN          LL_FLASH_EnableDataCache\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_EnableDataCache(void)\n{\n  SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);\n}\n\n/**\n  * @brief  Disable Data cache\n  * @rmtoll FLASH_ACR    DCEN          LL_FLASH_DisableDataCache\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_DisableDataCache(void)\n{\n  CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);\n}\n\n/**\n  * @brief  Enable Instruction cache reset\n  * @note  bit can be written only when the instruction cache is disabled\n  * @rmtoll FLASH_ACR    ICRST         LL_FLASH_EnableInstCacheReset\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)\n{\n  SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);\n}\n\n/**\n  * @brief  Disable Instruction cache reset\n  * @rmtoll FLASH_ACR    ICRST         LL_FLASH_DisableInstCacheReset\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)\n{\n  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);\n}\n\n/**\n  * @brief  Enable Data cache reset\n  * @note bit can be written only when the data cache is disabled\n  * @rmtoll FLASH_ACR    DCRST         LL_FLASH_EnableDataCacheReset\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)\n{\n  SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);\n}\n\n/**\n  * @brief  Disable Data cache reset\n  * @rmtoll FLASH_ACR    DCRST         LL_FLASH_DisableDataCacheReset\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)\n{\n  CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);\n}\n\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_LL_SYSTEM_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_ll_usart.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_usart.c\n  * @author  MCD Application Team\n  * @version V1.7.1\n  * @date    14-April-2017\n  * @brief   USART LL module driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n#if defined(USE_FULL_LL_DRIVER)\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_ll_usart.h\"\n#include \"stm32f4xx_ll_rcc.h\"\n#include \"stm32f4xx_ll_bus.h\"\n#ifdef  USE_FULL_ASSERT\n#include \"stm32_assert.h\"\n#else\n#define assert_param(expr) ((void)0U)\n#endif\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (UART10)\n\n/** @addtogroup USART_LL\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @addtogroup USART_LL_Private_Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n\n/* Private macros ------------------------------------------------------------*/\n/** @addtogroup USART_LL_Private_Macros\n  * @{\n  */\n\n/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available\n *              divided by the smallest oversampling used on the USART (i.e. 8)    */\n#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U)\n\n#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \\\n                                       || ((__VALUE__) == LL_USART_DIRECTION_RX) \\\n                                       || ((__VALUE__) == LL_USART_DIRECTION_TX) \\\n                                       || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))\n\n#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \\\n                                    || ((__VALUE__) == LL_USART_PARITY_EVEN) \\\n                                    || ((__VALUE__) == LL_USART_PARITY_ODD))\n\n#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \\\n                                       || ((__VALUE__) == LL_USART_DATAWIDTH_9B))\n\n#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \\\n                                          || ((__VALUE__) == LL_USART_OVERSAMPLING_8))\n\n#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \\\n                                              || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))\n\n#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \\\n                                        || ((__VALUE__) == LL_USART_PHASE_2EDGE))\n\n#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \\\n                                           || ((__VALUE__) == LL_USART_POLARITY_HIGH))\n\n#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \\\n                                         || ((__VALUE__) == LL_USART_CLOCK_ENABLE))\n\n#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \\\n                                      || ((__VALUE__) == LL_USART_STOPBITS_1) \\\n                                      || ((__VALUE__) == LL_USART_STOPBITS_1_5) \\\n                                      || ((__VALUE__) == LL_USART_STOPBITS_2))\n\n#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \\\n                                       || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \\\n                                       || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \\\n                                       || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))\n\n/**\n  * @}\n  */\n\n/* Private function prototypes -----------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup USART_LL_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup USART_LL_EF_Init\n  * @{\n  */\n\n/**\n  * @brief  De-initialize USART registers (Registers restored to their default values).\n  * @param  USARTx USART Instance\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: USART registers are de-initialized\n  *          - ERROR: USART registers are not de-initialized\n  */\nErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)\n{\n  ErrorStatus status = SUCCESS;\n\n  /* Check the parameters */\n  assert_param(IS_UART_INSTANCE(USARTx));\n\n  if (USARTx == USART1)\n  {\n    /* Force reset of USART clock */\n    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);\n\n    /* Release reset of USART clock */\n    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);\n  }\n  else if (USARTx == USART2)\n  {\n    /* Force reset of USART clock */\n    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);\n\n    /* Release reset of USART clock */\n    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);\n  }\n#if defined(USART3)\n  else if (USARTx == USART3)\n  {\n    /* Force reset of USART clock */\n    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);\n\n    /* Release reset of USART clock */\n    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);\n  }\n#endif /* USART3 */\n#if defined(USART6)\n  else if (USARTx == USART6)\n  {\n    /* Force reset of USART clock */\n    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);\n\n    /* Release reset of USART clock */\n    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);\n  }\n#endif /* USART6 */\n#if defined(UART4)\n  else if (USARTx == UART4)\n  {\n    /* Force reset of UART clock */\n    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);\n\n    /* Release reset of UART clock */\n    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);\n  }\n#endif /* UART4 */\n#if defined(UART5)\n  else if (USARTx == UART5)\n  {\n    /* Force reset of UART clock */\n    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);\n\n    /* Release reset of UART clock */\n    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);\n  }\n#endif /* UART5 */\n#if defined(UART7)\n  else if (USARTx == UART7)\n  {\n    /* Force reset of UART clock */\n    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7);\n\n    /* Release reset of UART clock */\n    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7);\n  }\n#endif /* UART7 */\n#if defined(UART8)\n  else if (USARTx == UART8)\n  {\n    /* Force reset of UART clock */\n    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8);\n\n    /* Release reset of UART clock */\n    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8);\n  }\n#endif /* UART8 */\n#if defined(UART9)\n  else if (USARTx == UART9)\n  {\n    /* Force reset of UART clock */\n    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART9);\n\n    /* Release reset of UART clock */\n    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART9);\n  }\n#endif /* UART9 */\n#if defined(UART10)\n  else if (USARTx == UART10)\n  {\n    /* Force reset of UART clock */\n    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART10);\n\n    /* Release reset of UART clock */\n    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART10);\n  }\n#endif /* UART10 */\n  else\n  {\n    status = ERROR;\n  }\n\n  return (status);\n}\n\n/**\n  * @brief  Initialize USART registers according to the specified\n  *         parameters in USART_InitStruct.\n  * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),\n  *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.\n  * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).\n  * @param  USARTx USART Instance\n  * @param  USART_InitStruct: pointer to a LL_USART_InitTypeDef structure\n  *         that contains the configuration information for the specified USART peripheral.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: USART registers are initialized according to USART_InitStruct content\n  *          - ERROR: Problem occurred during USART Registers initialization\n  */\nErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)\n{\n  ErrorStatus status = ERROR;\n  uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;\n  LL_RCC_ClocksTypeDef rcc_clocks;\n\n  /* Check the parameters */\n  assert_param(IS_UART_INSTANCE(USARTx));\n  assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));\n  assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));\n  assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));\n  assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));\n  assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));\n  assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));\n  assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));\n\n  /* USART needs to be in disabled state, in order to be able to configure some bits in\n     CRx registers */\n  if (LL_USART_IsEnabled(USARTx) == 0U)\n  {\n    /*---------------------------- USART CR1 Configuration -----------------------\n     * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:\n     * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value\n     * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value\n     * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value\n     * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.\n     */\n    MODIFY_REG(USARTx->CR1,\n               (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |\n                USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),\n               (USART_InitStruct->DataWidth | USART_InitStruct->Parity |\n                USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));\n\n    /*---------------------------- USART CR2 Configuration -----------------------\n     * Configure USARTx CR2 (Stop bits) with parameters:\n     * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.\n     * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().\n     */\n    LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);\n\n    /*---------------------------- USART CR3 Configuration -----------------------\n     * Configure USARTx CR3 (Hardware Flow Control) with parameters:\n     * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.\n     */\n    LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);\n\n    /*---------------------------- USART BRR Configuration -----------------------\n     * Retrieve Clock frequency used for USART Peripheral\n     */\n    LL_RCC_GetSystemClocksFreq(&rcc_clocks);\n    if (USARTx == USART1)\n    {\n      periphclk = rcc_clocks.PCLK2_Frequency;\n    }\n    else if (USARTx == USART2)\n    {\n      periphclk = rcc_clocks.PCLK1_Frequency;\n    }\n#if defined(USART3)\n    else if (USARTx == USART3)\n    {\n      periphclk = rcc_clocks.PCLK1_Frequency;\n    }\n#endif /* USART3 */\n#if defined(USART6)\n    else if (USARTx == USART6)\n    {\n      periphclk = rcc_clocks.PCLK2_Frequency;\n    }\n#endif /* USART6 */\n#if defined(UART4)\n    else if (USARTx == UART4)\n    {\n      periphclk = rcc_clocks.PCLK1_Frequency;\n    }\n#endif /* UART4 */\n#if defined(UART5)\n    else if (USARTx == UART5)\n    {\n      periphclk = rcc_clocks.PCLK1_Frequency;\n    }\n#endif /* UART5 */\n#if defined(UART7)\n    else if (USARTx == UART7)\n    {\n      periphclk = rcc_clocks.PCLK1_Frequency;\n    }\n#endif /* UART7 */\n#if defined(UART8)\n    else if (USARTx == UART8)\n    {\n      periphclk = rcc_clocks.PCLK1_Frequency;\n    }\n#endif /* UART8 */\n#if defined(UART9)\n    else if (USARTx == UART9)\n    {\n      periphclk = rcc_clocks.PCLK1_Frequency;\n    }\n#endif /* UART9 */\n#if defined(UART10)\n    else if (USARTx == UART5)\n    {\n      periphclk = rcc_clocks.PCLK1_Frequency;\n    }\n#endif /* UART10 */\n    else\n    {\n      /* Nothing to do, as error code is already assigned to ERROR value */\n    }\n\n    /* Configure the USART Baud Rate :\n       - valid baud rate value (different from 0) is required\n       - Peripheral clock as returned by RCC service, should be valid (different from 0).\n    */\n    if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)\n        && (USART_InitStruct->BaudRate != 0U))\n    {\n      status = SUCCESS;\n      LL_USART_SetBaudRate(USARTx,\n                           periphclk,\n                           USART_InitStruct->OverSampling,\n                           USART_InitStruct->BaudRate);\n    }\n  }\n  /* Endif (=> USART not in Disabled state => return ERROR) */\n\n  return (status);\n}\n\n/**\n  * @brief Set each @ref LL_USART_InitTypeDef field to default value.\n  * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure\n  *                          whose fields will be set to default values.\n  * @retval None\n  */\n\nvoid LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)\n{\n  /* Set USART_InitStruct fields to default values */\n  USART_InitStruct->BaudRate            = 9600U;\n  USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;\n  USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;\n  USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;\n  USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;\n  USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;\n  USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;\n}\n\n/**\n  * @brief  Initialize USART Clock related settings according to the\n  *         specified parameters in the USART_ClockInitStruct.\n  * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),\n  *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.\n  * @param  USARTx USART Instance\n  * @param  USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure\n  *         that contains the Clock configuration information for the specified USART peripheral.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content\n  *          - ERROR: Problem occurred during USART Registers initialization\n  */\nErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)\n{\n  ErrorStatus status = SUCCESS;\n\n  /* Check USART Instance and Clock signal output parameters */\n  assert_param(IS_UART_INSTANCE(USARTx));\n  assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));\n\n  /* USART needs to be in disabled state, in order to be able to configure some bits in\n     CRx registers */\n  if (LL_USART_IsEnabled(USARTx) == 0U)\n  {\n    /*---------------------------- USART CR2 Configuration -----------------------*/\n    /* If Clock signal has to be output */\n    if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)\n    {\n      /* Deactivate Clock signal delivery :\n       * - Disable Clock Output:        USART_CR2_CLKEN cleared\n       */\n      LL_USART_DisableSCLKOutput(USARTx);\n    }\n    else\n    {\n      /* Ensure USART instance is USART capable */\n      assert_param(IS_USART_INSTANCE(USARTx));\n\n      /* Check clock related parameters */\n      assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));\n      assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));\n      assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));\n\n      /*---------------------------- USART CR2 Configuration -----------------------\n       * Configure USARTx CR2 (Clock signal related bits) with parameters:\n       * - Enable Clock Output:         USART_CR2_CLKEN set\n       * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value\n       * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value\n       * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.\n       */\n      MODIFY_REG(USARTx->CR2,\n                 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,\n                 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |\n                 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);\n    }\n  }\n  /* Else (USART not in Disabled state => return ERROR */\n  else\n  {\n    status = ERROR;\n  }\n\n  return (status);\n}\n\n/**\n  * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.\n  * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure\n  *                               whose fields will be set to default values.\n  * @retval None\n  */\nvoid LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)\n{\n  /* Set LL_USART_ClockInitStruct fields with default values */\n  USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;\n  USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */\n  USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */\n  USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || UART10 */\n\n/**\n  * @}\n  */\n\n#endif /* USE_FULL_LL_DRIVER */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_ll_usart.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_usart.h\n  * @author  MCD Application Team\n  * @version V1.7.1\n  * @date    14-April-2017\n  * @brief   Header file of USART LL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_LL_USART_H\n#define __STM32F4xx_LL_USART_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (UART10)\n\n/** @defgroup USART_LL USART\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup USART_LL_Private_Constants USART Private Constants\n  * @{\n  */\n\n/* Defines used for the bit position in the register and perform offsets*/\n#define USART_POSITION_GTPR_GT                  USART_GTPR_GT_Pos\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup USART_LL_Private_Macros USART Private Macros\n  * @{\n  */\n/**\n  * @}\n  */\n#endif /*USE_FULL_LL_DRIVER*/\n\n/* Exported types ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup USART_LL_ES_INIT USART Exported Init structures\n  * @{\n  */\n\n/**\n  * @brief LL USART Init Structure definition\n  */\ntypedef struct\n{\n  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/\n\n  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.\n                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/\n\n  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.\n                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/\n\n  uint32_t Parity;                    /*!< Specifies the parity mode.\n                                           This parameter can be a value of @ref USART_LL_EC_PARITY.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/\n\n  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.\n                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/\n\n  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.\n                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/\n\n  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.\n                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/\n\n} LL_USART_InitTypeDef;\n\n/**\n  * @brief LL USART Clock Init Structure definition\n  */\ntypedef struct\n{\n  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.\n                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.\n\n                                           USART HW configuration can be modified afterwards using unitary functions\n                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().\n                                           For more details, refer to description of this function. */\n\n  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.\n                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.\n\n                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().\n                                           For more details, refer to description of this function. */\n\n  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.\n                                           This parameter can be a value of @ref USART_LL_EC_PHASE.\n\n                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().\n                                           For more details, refer to description of this function. */\n\n  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted\n                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.\n                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.\n\n                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().\n                                           For more details, refer to description of this function. */\n\n} LL_USART_ClockInitTypeDef;\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup USART_LL_Exported_Constants USART Exported Constants\n  * @{\n  */\n\n/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines\n  * @brief    Flags defines which can be used with LL_USART_ReadReg function\n  * @{\n  */\n#define LL_USART_SR_PE                          USART_SR_PE                   /*!< Parity error flag */\n#define LL_USART_SR_FE                          USART_SR_FE                   /*!< Framing error flag */\n#define LL_USART_SR_NE                          USART_SR_NE                   /*!< Noise detected flag */\n#define LL_USART_SR_ORE                         USART_SR_ORE                  /*!< Overrun error flag */\n#define LL_USART_SR_IDLE                        USART_SR_IDLE                 /*!< Idle line detected flag */\n#define LL_USART_SR_RXNE                        USART_SR_RXNE                 /*!< Read data register not empty flag */\n#define LL_USART_SR_TC                          USART_SR_TC                   /*!< Transmission complete flag */\n#define LL_USART_SR_TXE                         USART_SR_TXE                  /*!< Transmit data register empty flag */\n#define LL_USART_SR_LBD                         USART_SR_LBD                  /*!< LIN break detection flag */\n#define LL_USART_SR_CTS                         USART_SR_CTS                  /*!< CTS flag */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_IT IT Defines\n  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions\n  * @{\n  */\n#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */\n#define LL_USART_CR1_RXNEIE                     USART_CR1_RXNEIE              /*!< Read data register not empty interrupt enable */\n#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */\n#define LL_USART_CR1_TXEIE                      USART_CR1_TXEIE               /*!< Transmit data register empty interrupt enable */\n#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */\n#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */\n#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */\n#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_DIRECTION Communication Direction\n  * @{\n  */\n#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */\n#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */\n#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */\n#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_PARITY Parity Control\n  * @{\n  */\n#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */\n#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */\n#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_WAKEUP Wakeup\n  * @{\n  */\n#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */\n#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_DATAWIDTH Datawidth\n  * @{\n  */\n#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */\n#define LL_USART_DATAWIDTH_9B                   USART_CR1_M             /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling\n  * @{\n  */\n#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */\n#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup USART_LL_EC_CLOCK Clock Signal\n  * @{\n  */\n\n#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */\n#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */\n/**\n  * @}\n  */\n#endif /*USE_FULL_LL_DRIVER*/\n\n/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse\n  * @{\n  */\n#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */\n#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_PHASE Clock Phase\n  * @{\n  */\n#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */\n#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_POLARITY Clock Polarity\n  * @{\n  */\n#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/\n#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_STOPBITS Stop Bits\n  * @{\n  */\n#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */\n#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */\n#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */\n#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_HWCONTROL Hardware Control\n  * @{\n  */\n#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */\n#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */\n#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */\n#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power\n  * @{\n  */\n#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */\n#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length\n  * @{\n  */\n#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */\n#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup USART_LL_Exported_Macros USART Exported Macros\n  * @{\n  */\n\n/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros\n  * @{\n  */\n\n/**\n  * @brief  Write a value in USART register\n  * @param  __INSTANCE__ USART Instance\n  * @param  __REG__ Register to be written\n  * @param  __VALUE__ Value to be written in the register\n  * @retval None\n  */\n#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))\n\n/**\n  * @brief  Read a value in USART register\n  * @param  __INSTANCE__ USART Instance\n  * @param  __REG__ Register to be read\n  * @retval Register value\n  */\n#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper\n  * @{\n  */\n\n/**\n  * @brief  Compute USARTDIV value according to Peripheral Clock and\n  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)\n  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance\n  * @param  __BAUDRATE__ Baud rate value to achieve\n  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case\n  */\n#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__)      (((__PERIPHCLK__)*25)/(2*(__BAUDRATE__)))\n#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)      (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100)\n#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)      (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8 + 50) / 100)\n/* UART BRR = mantissa + overflow + fraction\n            = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */\n#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)             (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \\\n                                                                           ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \\\n                                                                           (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07))\n\n/**\n  * @brief  Compute USARTDIV value according to Peripheral Clock and\n  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)\n  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance\n  * @param  __BAUDRATE__ Baud rate value to achieve\n  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case\n  */\n#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__)     (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__)))\n#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)     (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)\n#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)     (((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16 + 50) / 100)\n/* USART BRR = mantissa + overflow + fraction\n            = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */\n#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)            (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \\\n                                                                           (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \\\n                                                                           (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F))\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n\n/** @defgroup USART_LL_Exported_Functions USART Exported Functions\n  * @{\n  */\n\n/** @defgroup USART_LL_EF_Configuration Configuration functions\n  * @{\n  */\n\n/**\n  * @brief  USART Enable\n  * @rmtoll CR1          UE            LL_USART_Enable\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_UE);\n}\n\n/**\n  * @brief  USART Disable (all USART prescalers and outputs are disabled)\n  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,\n  *         and current operations are discarded. The configuration of the USART is kept, but all the status\n  *         flags, in the USARTx_SR are set to their default values.\n  * @rmtoll CR1          UE            LL_USART_Disable\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);\n}\n\n/**\n  * @brief  Indicate if USART is enabled\n  * @rmtoll CR1          UE            LL_USART_IsEnabled\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));\n}\n\n/**\n  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)\n  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_RE);\n}\n\n/**\n  * @brief  Receiver Disable\n  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_RE);\n}\n\n/**\n  * @brief  Transmitter Enable\n  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_TE);\n}\n\n/**\n  * @brief  Transmitter Disable\n  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_TE);\n}\n\n/**\n  * @brief  Configure simultaneously enabled/disabled states\n  *         of Transmitter and Receiver\n  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\\n\n  *         CR1          TE            LL_USART_SetTransferDirection\n  * @param  USARTx USART Instance\n  * @param  TransferDirection This parameter can be one of the following values:\n  *         @arg @ref LL_USART_DIRECTION_NONE\n  *         @arg @ref LL_USART_DIRECTION_RX\n  *         @arg @ref LL_USART_DIRECTION_TX\n  *         @arg @ref LL_USART_DIRECTION_TX_RX\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)\n{\n  MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);\n}\n\n/**\n  * @brief  Return enabled/disabled states of Transmitter and Receiver\n  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\\n\n  *         CR1          TE            LL_USART_GetTransferDirection\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_DIRECTION_NONE\n  *         @arg @ref LL_USART_DIRECTION_RX\n  *         @arg @ref LL_USART_DIRECTION_TX\n  *         @arg @ref LL_USART_DIRECTION_TX_RX\n  */\n__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));\n}\n\n/**\n  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).\n  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.\n  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position\n  *         (9th or 8th bit depending on data width) and parity is checked on the received data.\n  * @rmtoll CR1          PS            LL_USART_SetParity\\n\n  *         CR1          PCE           LL_USART_SetParity\n  * @param  USARTx USART Instance\n  * @param  Parity This parameter can be one of the following values:\n  *         @arg @ref LL_USART_PARITY_NONE\n  *         @arg @ref LL_USART_PARITY_EVEN\n  *         @arg @ref LL_USART_PARITY_ODD\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)\n{\n  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);\n}\n\n/**\n  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)\n  * @rmtoll CR1          PS            LL_USART_GetParity\\n\n  *         CR1          PCE           LL_USART_GetParity\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_PARITY_NONE\n  *         @arg @ref LL_USART_PARITY_EVEN\n  *         @arg @ref LL_USART_PARITY_ODD\n  */\n__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));\n}\n\n/**\n  * @brief  Set Receiver Wake Up method from Mute mode.\n  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod\n  * @param  USARTx USART Instance\n  * @param  Method This parameter can be one of the following values:\n  *         @arg @ref LL_USART_WAKEUP_IDLELINE\n  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)\n{\n  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);\n}\n\n/**\n  * @brief  Return Receiver Wake Up method from Mute mode\n  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_WAKEUP_IDLELINE\n  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK\n  */\n__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));\n}\n\n/**\n  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)\n  * @rmtoll CR1          M             LL_USART_SetDataWidth\n  * @param  USARTx USART Instance\n  * @param  DataWidth This parameter can be one of the following values:\n  *         @arg @ref LL_USART_DATAWIDTH_8B\n  *         @arg @ref LL_USART_DATAWIDTH_9B\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)\n{\n  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);\n}\n\n/**\n  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)\n  * @rmtoll CR1          M             LL_USART_GetDataWidth\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_DATAWIDTH_8B\n  *         @arg @ref LL_USART_DATAWIDTH_9B\n  */\n__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));\n}\n\n/**\n  * @brief  Set Oversampling to 8-bit or 16-bit mode\n  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling\n  * @param  USARTx USART Instance\n  * @param  OverSampling This parameter can be one of the following values:\n  *         @arg @ref LL_USART_OVERSAMPLING_16\n  *         @arg @ref LL_USART_OVERSAMPLING_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)\n{\n  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);\n}\n\n/**\n  * @brief  Return Oversampling mode\n  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_OVERSAMPLING_16\n  *         @arg @ref LL_USART_OVERSAMPLING_8\n  */\n__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));\n}\n\n/**\n  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput\n  * @param  USARTx USART Instance\n  * @param  LastBitClockPulse This parameter can be one of the following values:\n  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT\n  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);\n}\n\n/**\n  * @brief  Retrieve Clock pulse of the last data bit output configuration\n  *         (Last bit Clock pulse output to the SCLK pin or not)\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT\n  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT\n  */\n__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));\n}\n\n/**\n  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase\n  * @param  USARTx USART Instance\n  * @param  ClockPhase This parameter can be one of the following values:\n  *         @arg @ref LL_USART_PHASE_1EDGE\n  *         @arg @ref LL_USART_PHASE_2EDGE\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);\n}\n\n/**\n  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_PHASE_1EDGE\n  *         @arg @ref LL_USART_PHASE_2EDGE\n  */\n__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));\n}\n\n/**\n  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity\n  * @param  USARTx USART Instance\n  * @param  ClockPolarity This parameter can be one of the following values:\n  *         @arg @ref LL_USART_POLARITY_LOW\n  *         @arg @ref LL_USART_POLARITY_HIGH\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);\n}\n\n/**\n  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_POLARITY_LOW\n  *         @arg @ref LL_USART_POLARITY_HIGH\n  */\n__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));\n}\n\n/**\n  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function\n  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function\n  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function\n  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\\n\n  *         CR2          CPOL          LL_USART_ConfigClock\\n\n  *         CR2          LBCL          LL_USART_ConfigClock\n  * @param  USARTx USART Instance\n  * @param  Phase This parameter can be one of the following values:\n  *         @arg @ref LL_USART_PHASE_1EDGE\n  *         @arg @ref LL_USART_PHASE_2EDGE\n  * @param  Polarity This parameter can be one of the following values:\n  *         @arg @ref LL_USART_POLARITY_LOW\n  *         @arg @ref LL_USART_POLARITY_HIGH\n  * @param  LBCPOutput This parameter can be one of the following values:\n  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT\n  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);\n}\n\n/**\n  * @brief  Enable Clock output on SCLK pin\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);\n}\n\n/**\n  * @brief  Disable Clock output on SCLK pin\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);\n}\n\n/**\n  * @brief  Indicate if Clock output on SCLK pin is enabled\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));\n}\n\n/**\n  * @brief  Set the length of the stop bits\n  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength\n  * @param  USARTx USART Instance\n  * @param  StopBits This parameter can be one of the following values:\n  *         @arg @ref LL_USART_STOPBITS_0_5\n  *         @arg @ref LL_USART_STOPBITS_1\n  *         @arg @ref LL_USART_STOPBITS_1_5\n  *         @arg @ref LL_USART_STOPBITS_2\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);\n}\n\n/**\n  * @brief  Retrieve the length of the stop bits\n  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_STOPBITS_0_5\n  *         @arg @ref LL_USART_STOPBITS_1\n  *         @arg @ref LL_USART_STOPBITS_1_5\n  *         @arg @ref LL_USART_STOPBITS_2\n  */\n__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));\n}\n\n/**\n  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function\n  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function\n  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function\n  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\\n\n  *         CR1          PCE           LL_USART_ConfigCharacter\\n\n  *         CR1          M             LL_USART_ConfigCharacter\\n\n  *         CR2          STOP          LL_USART_ConfigCharacter\n  * @param  USARTx USART Instance\n  * @param  DataWidth This parameter can be one of the following values:\n  *         @arg @ref LL_USART_DATAWIDTH_8B\n  *         @arg @ref LL_USART_DATAWIDTH_9B\n  * @param  Parity This parameter can be one of the following values:\n  *         @arg @ref LL_USART_PARITY_NONE\n  *         @arg @ref LL_USART_PARITY_EVEN\n  *         @arg @ref LL_USART_PARITY_ODD\n  * @param  StopBits This parameter can be one of the following values:\n  *         @arg @ref LL_USART_STOPBITS_0_5\n  *         @arg @ref LL_USART_STOPBITS_1\n  *         @arg @ref LL_USART_STOPBITS_1_5\n  *         @arg @ref LL_USART_STOPBITS_2\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,\n                                              uint32_t StopBits)\n{\n  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);\n  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);\n}\n\n/**\n  * @brief  Set Address of the USART node.\n  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,\n  *         for wake up with address mark detection.\n  * @rmtoll CR2          ADD           LL_USART_SetNodeAddress\n  * @param  USARTx USART Instance\n  * @param  NodeAddress 4 bit Address of the USART node.\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t NodeAddress)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_ADD, (NodeAddress & USART_CR2_ADD));\n}\n\n/**\n  * @brief  Return 4 bit Address of the USART node as set in ADD field of CR2.\n  * @note   only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)\n  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress\n  * @param  USARTx USART Instance\n  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)\n  */\n__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD));\n}\n\n/**\n  * @brief  Enable RTS HW Flow Control\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_RTSE);\n}\n\n/**\n  * @brief  Disable RTS HW Flow Control\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);\n}\n\n/**\n  * @brief  Enable CTS HW Flow Control\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_CTSE);\n}\n\n/**\n  * @brief  Disable CTS HW Flow Control\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);\n}\n\n/**\n  * @brief  Configure HW Flow Control mode (both CTS and RTS)\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\\n\n  *         CR3          CTSE          LL_USART_SetHWFlowCtrl\n  * @param  USARTx USART Instance\n  * @param  HardwareFlowControl This parameter can be one of the following values:\n  *         @arg @ref LL_USART_HWCONTROL_NONE\n  *         @arg @ref LL_USART_HWCONTROL_RTS\n  *         @arg @ref LL_USART_HWCONTROL_CTS\n  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)\n{\n  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);\n}\n\n/**\n  * @brief  Return HW Flow Control configuration (both CTS and RTS)\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\\n\n  *         CR3          CTSE          LL_USART_GetHWFlowCtrl\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_HWCONTROL_NONE\n  *         @arg @ref LL_USART_HWCONTROL_RTS\n  *         @arg @ref LL_USART_HWCONTROL_CTS\n  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS\n  */\n__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));\n}\n\n/**\n  * @brief  Enable One bit sampling method\n  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);\n}\n\n/**\n  * @brief  Disable One bit sampling method\n  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);\n}\n\n/**\n  * @brief  Indicate if One bit sampling method is enabled\n  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));\n}\n\n/**\n  * @brief  Configure USART BRR register for achieving expected Baud Rate value.\n  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)\n  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values\n  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid\n  *         (Baud rate value != 0)\n  * @rmtoll BRR          BRR           LL_USART_SetBaudRate\n  * @param  USARTx USART Instance\n  * @param  PeriphClk Peripheral Clock\n  * @param  OverSampling This parameter can be one of the following values:\n  *         @arg @ref LL_USART_OVERSAMPLING_16\n  *         @arg @ref LL_USART_OVERSAMPLING_8\n  * @param  BaudRate Baud Rate\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,\n                                          uint32_t BaudRate)\n{\n  if (OverSampling == LL_USART_OVERSAMPLING_8)\n  {\n    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));\n  }\n  else\n  {\n    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));\n  }\n}\n\n/**\n  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register\n  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values\n  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.\n  * @rmtoll BRR          BRR           LL_USART_GetBaudRate\n  * @param  USARTx USART Instance\n  * @param  PeriphClk Peripheral Clock\n  * @param  OverSampling This parameter can be one of the following values:\n  *         @arg @ref LL_USART_OVERSAMPLING_16\n  *         @arg @ref LL_USART_OVERSAMPLING_8\n  * @retval Baud Rate\n  */\n__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)\n{\n  register uint32_t usartdiv = 0x0U;\n  register uint32_t brrresult = 0x0U;\n\n  usartdiv = USARTx->BRR;\n\n  if (OverSampling == LL_USART_OVERSAMPLING_8)\n  {\n    if ((usartdiv & 0xFFF7U) != 0U)\n    {\n      usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;\n      brrresult = (PeriphClk * 2U) / usartdiv;\n    }\n  }\n  else\n  {\n    if ((usartdiv & 0xFFFFU) != 0U)\n    {\n      brrresult = PeriphClk / usartdiv;\n    }\n  }\n  return (brrresult);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature\n  * @{\n  */\n\n/**\n  * @brief  Enable IrDA mode\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll CR3          IREN          LL_USART_EnableIrda\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_IREN);\n}\n\n/**\n  * @brief  Disable IrDA mode\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll CR3          IREN          LL_USART_DisableIrda\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);\n}\n\n/**\n  * @brief  Indicate if IrDA mode is enabled\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));\n}\n\n/**\n  * @brief  Configure IrDA Power Mode (Normal or Low Power)\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode\n  * @param  USARTx USART Instance\n  * @param  PowerMode This parameter can be one of the following values:\n  *         @arg @ref LL_USART_IRDA_POWER_NORMAL\n  *         @arg @ref LL_USART_IRDA_POWER_LOW\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)\n{\n  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);\n}\n\n/**\n  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_IRDA_POWER_NORMAL\n  *         @arg @ref LL_USART_PHASE_2EDGE\n  */\n__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));\n}\n\n/**\n  * @brief  Set Irda prescaler value, used for dividing the USART clock source\n  *         to achieve the Irda Low Power frequency (8 bits value)\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler\n  * @param  USARTx USART Instance\n  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)\n{\n  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);\n}\n\n/**\n  * @brief  Return Irda prescaler value, used for dividing the USART clock source\n  *         to achieve the Irda Low Power frequency (8 bits value)\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler\n  * @param  USARTx USART Instance\n  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)\n  */\n__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature\n  * @{\n  */\n\n/**\n  * @brief  Enable Smartcard NACK transmission\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_NACK);\n}\n\n/**\n  * @brief  Disable Smartcard NACK transmission\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);\n}\n\n/**\n  * @brief  Indicate if Smartcard NACK transmission is enabled\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));\n}\n\n/**\n  * @brief  Enable Smartcard mode\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_SCEN);\n}\n\n/**\n  * @brief  Disable Smartcard mode\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);\n}\n\n/**\n  * @brief  Indicate if Smartcard mode is enabled\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));\n}\n\n/**\n  * @brief  Set Smartcard prescaler value, used for dividing the USART clock\n  *         source to provide the SMARTCARD Clock (5 bits value)\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler\n  * @param  USARTx USART Instance\n  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)\n{\n  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);\n}\n\n/**\n  * @brief  Return Smartcard prescaler value, used for dividing the USART clock\n  *         source to provide the SMARTCARD Clock (5 bits value)\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler\n  * @param  USARTx USART Instance\n  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)\n  */\n__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));\n}\n\n/**\n  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods\n  *         (GT[7:0] bits : Guard time value)\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime\n  * @param  USARTx USART Instance\n  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)\n{\n  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT);\n}\n\n/**\n  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods\n  *         (GT[7:0] bits : Guard time value)\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime\n  * @param  USARTx USART Instance\n  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)\n  */\n__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature\n  * @{\n  */\n\n/**\n  * @brief  Enable Single Wire Half-Duplex mode\n  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not\n  *         Half-Duplex mode is supported by the USARTx instance.\n  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);\n}\n\n/**\n  * @brief  Disable Single Wire Half-Duplex mode\n  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not\n  *         Half-Duplex mode is supported by the USARTx instance.\n  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);\n}\n\n/**\n  * @brief  Indicate if Single Wire Half-Duplex mode is enabled\n  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not\n  *         Half-Duplex mode is supported by the USARTx instance.\n  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature\n  * @{\n  */\n\n/**\n  * @brief  Set LIN Break Detection Length\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen\n  * @param  USARTx USART Instance\n  * @param  LINBDLength This parameter can be one of the following values:\n  *         @arg @ref LL_USART_LINBREAK_DETECT_10B\n  *         @arg @ref LL_USART_LINBREAK_DETECT_11B\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);\n}\n\n/**\n  * @brief  Return LIN Break Detection Length\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_LINBREAK_DETECT_10B\n  *         @arg @ref LL_USART_LINBREAK_DETECT_11B\n  */\n__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));\n}\n\n/**\n  * @brief  Enable LIN mode\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LINEN         LL_USART_EnableLIN\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR2, USART_CR2_LINEN);\n}\n\n/**\n  * @brief  Disable LIN mode\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LINEN         LL_USART_DisableLIN\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);\n}\n\n/**\n  * @brief  Indicate if LIN mode is enabled\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services\n  * @{\n  */\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)\n  * @note   In UART mode, the following bits must be kept cleared:\n  *           - LINEN bit in the USART_CR2 register,\n  *           - CLKEN bit in the USART_CR2 register,\n  *           - SCEN bit in the USART_CR3 register,\n  *           - IREN bit in the USART_CR3 register,\n  *           - HDSEL bit in the USART_CR3 register.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function\n  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function\n  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function\n  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function\n  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function\n  * @note   Other remaining configurations items related to Asynchronous Mode\n  *         (as Baud Rate, Word length, Parity, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\\n\n  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\\n\n  *         CR3          SCEN          LL_USART_ConfigAsyncMode\\n\n  *         CR3          IREN          LL_USART_ConfigAsyncMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigAsyncMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)\n{\n  /* In Asynchronous mode, the following bits must be kept cleared:\n  - LINEN, CLKEN bits in the USART_CR2 register,\n  - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));\n}\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode\n  * @note   In Synchronous mode, the following bits must be kept cleared:\n  *           - LINEN bit in the USART_CR2 register,\n  *           - SCEN bit in the USART_CR3 register,\n  *           - IREN bit in the USART_CR3 register,\n  *           - HDSEL bit in the USART_CR3 register.\n  *         This function also sets the USART in Synchronous mode.\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function\n  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function\n  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function\n  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function\n  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function\n  * @note   Other remaining configurations items related to Synchronous Mode\n  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\\n\n  *         CR2          CLKEN         LL_USART_ConfigSyncMode\\n\n  *         CR3          SCEN          LL_USART_ConfigSyncMode\\n\n  *         CR3          IREN          LL_USART_ConfigSyncMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigSyncMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)\n{\n  /* In Synchronous mode, the following bits must be kept cleared:\n  - LINEN bit in the USART_CR2 register,\n  - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));\n  /* set the UART/USART in Synchronous mode */\n  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);\n}\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in LIN Mode\n  * @note   In LIN mode, the following bits must be kept cleared:\n  *           - STOP and CLKEN bits in the USART_CR2 register,\n  *           - SCEN bit in the USART_CR3 register,\n  *           - IREN bit in the USART_CR3 register,\n  *           - HDSEL bit in the USART_CR3 register.\n  *         This function also set the UART/USART in LIN mode.\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function\n  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function\n  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function\n  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function\n  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function\n  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function\n  * @note   Other remaining configurations items related to LIN Mode\n  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\\n\n  *         CR2          STOP          LL_USART_ConfigLINMode\\n\n  *         CR2          LINEN         LL_USART_ConfigLINMode\\n\n  *         CR3          IREN          LL_USART_ConfigLINMode\\n\n  *         CR3          SCEN          LL_USART_ConfigLINMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigLINMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)\n{\n  /* In LIN mode, the following bits must be kept cleared:\n  - STOP and CLKEN bits in the USART_CR2 register,\n  - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));\n  /* Set the UART/USART in LIN mode */\n  SET_BIT(USARTx->CR2, USART_CR2_LINEN);\n}\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode\n  * @note   In Half Duplex mode, the following bits must be kept cleared:\n  *           - LINEN bit in the USART_CR2 register,\n  *           - CLKEN bit in the USART_CR2 register,\n  *           - SCEN bit in the USART_CR3 register,\n  *           - IREN bit in the USART_CR3 register,\n  *         This function also sets the UART/USART in Half Duplex mode.\n  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not\n  *         Half-Duplex mode is supported by the USARTx instance.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function\n  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function\n  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function\n  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function\n  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function\n  * @note   Other remaining configurations items related to Half Duplex Mode\n  *         (as Baud Rate, Word length, Parity, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\\n\n  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\\n\n  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\\n\n  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)\n{\n  /* In Half Duplex mode, the following bits must be kept cleared:\n  - LINEN and CLKEN bits in the USART_CR2 register,\n  - SCEN and IREN bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));\n  /* set the UART/USART in Half Duplex mode */\n  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);\n}\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode\n  * @note   In Smartcard mode, the following bits must be kept cleared:\n  *           - LINEN bit in the USART_CR2 register,\n  *           - IREN bit in the USART_CR3 register,\n  *           - HDSEL bit in the USART_CR3 register.\n  *         This function also configures Stop bits to 1.5 bits and\n  *         sets the USART in Smartcard mode (SCEN bit).\n  *         Clock Output is also enabled (CLKEN).\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function\n  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function\n  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function\n  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function\n  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function\n  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function\n  * @note   Other remaining configurations items related to Smartcard Mode\n  *         (as Baud Rate, Word length, Parity, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\\n\n  *         CR2          STOP          LL_USART_ConfigSmartcardMode\\n\n  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\\n\n  *         CR3          SCEN          LL_USART_ConfigSmartcardMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)\n{\n  /* In Smartcard mode, the following bits must be kept cleared:\n  - LINEN bit in the USART_CR2 register,\n  - IREN and HDSEL bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));\n  /* Configure Stop bits to 1.5 bits */\n  /* Synchronous mode is activated by default */\n  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));\n  /* set the UART/USART in Smartcard mode */\n  SET_BIT(USARTx->CR3, USART_CR3_SCEN);\n}\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in Irda Mode\n  * @note   In IRDA mode, the following bits must be kept cleared:\n  *           - LINEN bit in the USART_CR2 register,\n  *           - STOP and CLKEN bits in the USART_CR2 register,\n  *           - SCEN bit in the USART_CR3 register,\n  *           - HDSEL bit in the USART_CR3 register.\n  *         This function also sets the UART/USART in IRDA mode (IREN bit).\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function\n  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function\n  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function\n  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function\n  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function\n  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function\n  * @note   Other remaining configurations items related to Irda Mode\n  *         (as Baud Rate, Word length, Power mode, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\\n\n  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\\n\n  *         CR2          STOP          LL_USART_ConfigIrdaMode\\n\n  *         CR3          SCEN          LL_USART_ConfigIrdaMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\\n\n  *         CR3          IREN          LL_USART_ConfigIrdaMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)\n{\n  /* In IRDA mode, the following bits must be kept cleared:\n  - LINEN, STOP and CLKEN bits in the USART_CR2 register,\n  - SCEN and HDSEL bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));\n  /* set the UART/USART in IRDA mode */\n  SET_BIT(USARTx->CR3, USART_CR3_IREN);\n}\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode\n  *         (several USARTs connected in a network, one of the USARTs can be the master,\n  *         its TX output connected to the RX inputs of the other slaves USARTs).\n  * @note   In MultiProcessor mode, the following bits must be kept cleared:\n  *           - LINEN bit in the USART_CR2 register,\n  *           - CLKEN bit in the USART_CR2 register,\n  *           - SCEN bit in the USART_CR3 register,\n  *           - IREN bit in the USART_CR3 register,\n  *           - HDSEL bit in the USART_CR3 register.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function\n  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function\n  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function\n  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function\n  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function\n  * @note   Other remaining configurations items related to Multi processor Mode\n  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\\n\n  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\\n\n  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\\n\n  *         CR3          IREN          LL_USART_ConfigMultiProcessMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)\n{\n  /* In Multi Processor mode, the following bits must be kept cleared:\n  - LINEN and CLKEN bits in the USART_CR2 register,\n  - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management\n  * @{\n  */\n\n/**\n  * @brief  Check if the USART Parity Error Flag is set or not\n  * @rmtoll SR           PE            LL_USART_IsActiveFlag_PE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE));\n}\n\n/**\n  * @brief  Check if the USART Framing Error Flag is set or not\n  * @rmtoll SR           FE            LL_USART_IsActiveFlag_FE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE));\n}\n\n/**\n  * @brief  Check if the USART Noise error detected Flag is set or not\n  * @rmtoll SR           NF            LL_USART_IsActiveFlag_NE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE));\n}\n\n/**\n  * @brief  Check if the USART OverRun Error Flag is set or not\n  * @rmtoll SR           ORE           LL_USART_IsActiveFlag_ORE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE));\n}\n\n/**\n  * @brief  Check if the USART IDLE line detected Flag is set or not\n  * @rmtoll SR           IDLE          LL_USART_IsActiveFlag_IDLE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE));\n}\n\n/**\n  * @brief  Check if the USART Read Data Register Not Empty Flag is set or not\n  * @rmtoll SR           RXNE          LL_USART_IsActiveFlag_RXNE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE));\n}\n\n/**\n  * @brief  Check if the USART Transmission Complete Flag is set or not\n  * @rmtoll SR           TC            LL_USART_IsActiveFlag_TC\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC));\n}\n\n/**\n  * @brief  Check if the USART Transmit Data Register Empty Flag is set or not\n  * @rmtoll SR           TXE           LL_USART_IsActiveFlag_TXE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE));\n}\n\n/**\n  * @brief  Check if the USART LIN Break Detection Flag is set or not\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll SR           LBD           LL_USART_IsActiveFlag_LBD\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD));\n}\n\n/**\n  * @brief  Check if the USART CTS Flag is set or not\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll SR           CTS           LL_USART_IsActiveFlag_nCTS\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS));\n}\n\n/**\n  * @brief  Check if the USART Send Break Flag is set or not\n  * @rmtoll CR1          SBK           LL_USART_IsActiveFlag_SBK\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK));\n}\n\n/**\n  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not\n  * @rmtoll CR1          RWU           LL_USART_IsActiveFlag_RWU\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU));\n}\n\n/**\n  * @brief  Clear Parity Error Flag\n  * @note   Clearing this flag is done by a read access to the USARTx_SR\n  *         register followed by a read access to the USARTx_DR register.\n  * @note   Please also consider that when clearing this flag, other flags as\n  *         NE, FE, ORE, IDLE would also be cleared.\n  * @rmtoll SR           PE            LL_USART_ClearFlag_PE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)\n{\n  __IO uint32_t tmpreg;\n  tmpreg = USARTx->SR;\n  (void) tmpreg;\n  tmpreg = USARTx->DR;\n  (void) tmpreg;\n}\n\n/**\n  * @brief  Clear Framing Error Flag\n  * @note   Clearing this flag is done by a read access to the USARTx_SR\n  *         register followed by a read access to the USARTx_DR register.\n  * @note   Please also consider that when clearing this flag, other flags as\n  *         PE, NE, ORE, IDLE would also be cleared.\n  * @rmtoll SR           FE            LL_USART_ClearFlag_FE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)\n{\n  __IO uint32_t tmpreg;\n  tmpreg = USARTx->SR;\n  (void) tmpreg;\n  tmpreg = USARTx->DR;\n  (void) tmpreg;\n}\n\n/**\n  * @brief  Clear Noise detected Flag\n  * @note   Clearing this flag is done by a read access to the USARTx_SR\n  *         register followed by a read access to the USARTx_DR register.\n  * @note   Please also consider that when clearing this flag, other flags as\n  *         PE, FE, ORE, IDLE would also be cleared.\n  * @rmtoll SR           NF            LL_USART_ClearFlag_NE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)\n{\n  __IO uint32_t tmpreg;\n  tmpreg = USARTx->SR;\n  (void) tmpreg;\n  tmpreg = USARTx->DR;\n  (void) tmpreg;\n}\n\n/**\n  * @brief  Clear OverRun Error Flag\n  * @note   Clearing this flag is done by a read access to the USARTx_SR\n  *         register followed by a read access to the USARTx_DR register.\n  * @note   Please also consider that when clearing this flag, other flags as\n  *         PE, NE, FE, IDLE would also be cleared.\n  * @rmtoll SR           ORE           LL_USART_ClearFlag_ORE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)\n{\n  __IO uint32_t tmpreg;\n  tmpreg = USARTx->SR;\n  (void) tmpreg;\n  tmpreg = USARTx->DR;\n  (void) tmpreg;\n}\n\n/**\n  * @brief  Clear IDLE line detected Flag\n  * @note   Clearing this flag is done by a read access to the USARTx_SR\n  *         register followed by a read access to the USARTx_DR register.\n  * @note   Please also consider that when clearing this flag, other flags as\n  *         PE, NE, FE, ORE would also be cleared.\n  * @rmtoll SR           IDLE          LL_USART_ClearFlag_IDLE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)\n{\n  __IO uint32_t tmpreg;\n  tmpreg = USARTx->SR;\n  (void) tmpreg;\n  tmpreg = USARTx->DR;\n  (void) tmpreg;\n}\n\n/**\n  * @brief  Clear Transmission Complete Flag\n  * @rmtoll SR           TC            LL_USART_ClearFlag_TC\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->SR , ~(USART_SR_TC));\n}\n\n/**\n  * @brief  Clear RX Not Empty Flag\n  * @rmtoll SR           RXNE          LL_USART_ClearFlag_RXNE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->SR , ~(USART_SR_RXNE));\n}\n\n/**\n  * @brief  Clear LIN Break Detection Flag\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll SR           LBD           LL_USART_ClearFlag_LBD\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->SR , ~(USART_SR_LBD));\n}\n\n/**\n  * @brief  Clear CTS Interrupt Flag\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll SR           CTS           LL_USART_ClearFlag_nCTS\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->SR , ~(USART_SR_CTS));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_IT_Management IT_Management\n  * @{\n  */\n\n/**\n  * @brief  Enable IDLE Interrupt\n  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);\n}\n\n/**\n  * @brief  Enable RX Not Empty Interrupt\n  * @rmtoll CR1          RXNEIE        LL_USART_EnableIT_RXNE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);\n}\n\n/**\n  * @brief  Enable Transmission Complete Interrupt\n  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_TCIE);\n}\n\n/**\n  * @brief  Enable TX Empty Interrupt\n  * @rmtoll CR1          TXEIE         LL_USART_EnableIT_TXE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_TXEIE);\n}\n\n/**\n  * @brief  Enable Parity Error Interrupt\n  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_PEIE);\n}\n\n/**\n  * @brief  Enable LIN Break Detection Interrupt\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);\n}\n\n/**\n  * @brief  Enable Error Interrupt\n  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing\n  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).\n  *           0: Interrupt is inhibited\n  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.\n  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_EIE);\n}\n\n/**\n  * @brief  Enable CTS Interrupt\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_CTSIE);\n}\n\n/**\n  * @brief  Disable IDLE Interrupt\n  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);\n}\n\n/**\n  * @brief  Disable RX Not Empty Interrupt\n  * @rmtoll CR1          RXNEIE        LL_USART_DisableIT_RXNE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);\n}\n\n/**\n  * @brief  Disable Transmission Complete Interrupt\n  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);\n}\n\n/**\n  * @brief  Disable TX Empty Interrupt\n  * @rmtoll CR1          TXEIE         LL_USART_DisableIT_TXE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);\n}\n\n/**\n  * @brief  Disable Parity Error Interrupt\n  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);\n}\n\n/**\n  * @brief  Disable LIN Break Detection Interrupt\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);\n}\n\n/**\n  * @brief  Disable Error Interrupt\n  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing\n  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).\n  *           0: Interrupt is inhibited\n  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.\n  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);\n}\n\n/**\n  * @brief  Disable CTS Interrupt\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);\n}\n\n/**\n  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.\n  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));\n}\n\n/**\n  * @brief  Check if the USART RX Not Empty Interrupt is enabled or disabled.\n  * @rmtoll CR1          RXNEIE        LL_USART_IsEnabledIT_RXNE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));\n}\n\n/**\n  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.\n  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));\n}\n\n/**\n  * @brief  Check if the USART TX Empty Interrupt is enabled or disabled.\n  * @rmtoll CR1          TXEIE         LL_USART_IsEnabledIT_TXE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));\n}\n\n/**\n  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.\n  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));\n}\n\n/**\n  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));\n}\n\n/**\n  * @brief  Check if the USART Error Interrupt is enabled or disabled.\n  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));\n}\n\n/**\n  * @brief  Check if the USART CTS Interrupt is enabled or disabled.\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_DMA_Management DMA_Management\n  * @{\n  */\n\n/**\n  * @brief  Enable DMA Mode for reception\n  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_DMAR);\n}\n\n/**\n  * @brief  Disable DMA Mode for reception\n  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);\n}\n\n/**\n  * @brief  Check if DMA Mode is enabled for reception\n  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));\n}\n\n/**\n  * @brief  Enable DMA Mode for transmission\n  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_DMAT);\n}\n\n/**\n  * @brief  Disable DMA Mode for transmission\n  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);\n}\n\n/**\n  * @brief  Check if DMA Mode is enabled for transmission\n  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));\n}\n\n/**\n  * @brief  Get the data register address used for DMA transfer\n  * @rmtoll DR           DR            LL_USART_DMA_GetRegAddr\n  * @note   Address of Data Register is valid for both Transmit and Receive transfers.\n  * @param  USARTx USART Instance\n  * @retval Address of data register\n  */\n__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx)\n{\n  /* return address of DR register */\n  return ((uint32_t) &(USARTx->DR));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_Data_Management Data_Management\n  * @{\n  */\n\n/**\n  * @brief  Read Receiver Data register (Receive Data value, 8 bits)\n  * @rmtoll DR           DR            LL_USART_ReceiveData8\n  * @param  USARTx USART Instance\n  * @retval Value between Min_Data=0x00 and Max_Data=0xFF\n  */\n__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)\n{\n  return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR));\n}\n\n/**\n  * @brief  Read Receiver Data register (Receive Data value, 9 bits)\n  * @rmtoll DR           DR            LL_USART_ReceiveData9\n  * @param  USARTx USART Instance\n  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF\n  */\n__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)\n{\n  return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR));\n}\n\n/**\n  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)\n  * @rmtoll DR           DR            LL_USART_TransmitData8\n  * @param  USARTx USART Instance\n  * @param  Value between Min_Data=0x00 and Max_Data=0xFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)\n{\n  USARTx->DR = Value;\n}\n\n/**\n  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)\n  * @rmtoll DR           DR            LL_USART_TransmitData9\n  * @param  USARTx USART Instance\n  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)\n{\n  USARTx->DR = Value & 0x1FFU;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_Execution Execution\n  * @{\n  */\n\n/**\n  * @brief  Request Break sending\n  * @rmtoll CR1          SBK           LL_USART_RequestBreakSending\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_SBK);\n}\n\n/**\n  * @brief  Put USART in Mute mode\n  * @rmtoll CR1          RWU           LL_USART_RequestEnterMuteMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_RWU);\n}\n\n/**\n  * @brief  Put USART in Active mode\n  * @rmtoll CR1          RWU           LL_USART_RequestExitMuteMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_RWU);\n}\n\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions\n  * @{\n  */\nErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);\nErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);\nvoid        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);\nErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);\nvoid        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || UART10 */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_LL_USART_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_ll_utils.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_utils.c\n  * @author  MCD Application Team\n  * @version V1.7.1\n  * @date    14-April-2017\n  * @brief   UTILS LL module driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_ll_utils.h\"\n#include \"stm32f4xx_ll_rcc.h\"\n#include \"stm32f4xx_ll_system.h\"\n#include \"stm32f4xx_ll_pwr.h\"\n#ifdef  USE_FULL_ASSERT\n#include \"stm32_assert.h\"\n#else\n#define assert_param(expr) ((void)0U)\n#endif /* USE_FULL_ASSERT */\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n/** @addtogroup UTILS_LL\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @addtogroup UTILS_LL_Private_Constants\n  * @{\n  */\n#if defined(RCC_MAX_FREQUENCY_SCALE1)\n#define UTILS_MAX_FREQUENCY_SCALE1  RCC_MAX_FREQUENCY           /*!< Maximum frequency for system clock at power scale1, in Hz */\n#endif /*RCC_MAX_FREQUENCY_SCALE1 */\n#define UTILS_MAX_FREQUENCY_SCALE2  RCC_MAX_FREQUENCY_SCALE2    /*!< Maximum frequency for system clock at power scale2, in Hz */\n#if defined(RCC_MAX_FREQUENCY_SCALE3)\n#define UTILS_MAX_FREQUENCY_SCALE3  RCC_MAX_FREQUENCY_SCALE3    /*!< Maximum frequency for system clock at power scale3, in Hz */\n#endif /* MAX_FREQUENCY_SCALE3 */\n\n/* Defines used for PLL range */\n#define UTILS_PLLVCO_INPUT_MIN      RCC_PLLVCO_INPUT_MIN        /*!< Frequency min for PLLVCO input, in Hz   */\n#define UTILS_PLLVCO_INPUT_MAX      RCC_PLLVCO_INPUT_MAX        /*!< Frequency max for PLLVCO input, in Hz   */\n#define UTILS_PLLVCO_OUTPUT_MIN     RCC_PLLVCO_OUTPUT_MIN       /*!< Frequency min for PLLVCO output, in Hz  */\n#define UTILS_PLLVCO_OUTPUT_MAX     RCC_PLLVCO_OUTPUT_MAX       /*!< Frequency max for PLLVCO output, in Hz  */\n\n/* Defines used for HSE range */\n#define UTILS_HSE_FREQUENCY_MIN      4000000U        /*!< Frequency min for HSE frequency, in Hz   */\n#define UTILS_HSE_FREQUENCY_MAX     26000000U        /*!< Frequency max for HSE frequency, in Hz   */\n\n/* Defines used for FLASH latency according to HCLK Frequency */\n#if defined(FLASH_SCALE1_LATENCY1_FREQ)\n#define UTILS_SCALE1_LATENCY1_FREQ  FLASH_SCALE1_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */\n#endif\n#if defined(FLASH_SCALE1_LATENCY2_FREQ)\n#define UTILS_SCALE1_LATENCY2_FREQ  FLASH_SCALE1_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */\n#endif\n#if defined(FLASH_SCALE1_LATENCY3_FREQ)\n#define UTILS_SCALE1_LATENCY3_FREQ  FLASH_SCALE1_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */\n#endif\n#if defined(FLASH_SCALE1_LATENCY4_FREQ)\n#define UTILS_SCALE1_LATENCY4_FREQ  FLASH_SCALE1_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */\n#endif\n#if defined(FLASH_SCALE1_LATENCY5_FREQ)\n#define UTILS_SCALE1_LATENCY5_FREQ  FLASH_SCALE1_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */\n#endif\n#define UTILS_SCALE2_LATENCY1_FREQ  FLASH_SCALE2_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */\n#define UTILS_SCALE2_LATENCY2_FREQ  FLASH_SCALE2_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */\n#if defined(FLASH_SCALE2_LATENCY3_FREQ)\n#define UTILS_SCALE2_LATENCY3_FREQ  FLASH_SCALE2_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */\n#endif\n#if defined(FLASH_SCALE2_LATENCY4_FREQ)\n#define UTILS_SCALE2_LATENCY4_FREQ  FLASH_SCALE2_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */\n#endif\n#if defined(FLASH_SCALE2_LATENCY5_FREQ)\n#define UTILS_SCALE2_LATENCY5_FREQ  FLASH_SCALE2_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */\n#endif\n#if defined(FLASH_SCALE3_LATENCY1_FREQ)\n#define UTILS_SCALE3_LATENCY1_FREQ  FLASH_SCALE3_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */\n#endif\n#if defined(FLASH_SCALE3_LATENCY2_FREQ)\n#define UTILS_SCALE3_LATENCY2_FREQ  FLASH_SCALE3_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */\n#endif\n#if defined(FLASH_SCALE3_LATENCY3_FREQ)\n#define UTILS_SCALE3_LATENCY3_FREQ  FLASH_SCALE3_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */\n#endif\n#if defined(FLASH_SCALE3_LATENCY4_FREQ)\n#define UTILS_SCALE3_LATENCY4_FREQ  FLASH_SCALE3_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */\n#endif\n#if defined(FLASH_SCALE3_LATENCY5_FREQ)\n#define UTILS_SCALE3_LATENCY5_FREQ  FLASH_SCALE3_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 3 */\n#endif\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @addtogroup UTILS_LL_Private_Macros\n  * @{\n  */\n#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))\n\n#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \\\n                                      || ((__VALUE__) == LL_RCC_APB1_DIV_2) \\\n                                      || ((__VALUE__) == LL_RCC_APB1_DIV_4) \\\n                                      || ((__VALUE__) == LL_RCC_APB1_DIV_8) \\\n                                      || ((__VALUE__) == LL_RCC_APB1_DIV_16))\n\n#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \\\n                                      || ((__VALUE__) == LL_RCC_APB2_DIV_2) \\\n                                      || ((__VALUE__) == LL_RCC_APB2_DIV_4) \\\n                                      || ((__VALUE__) == LL_RCC_APB2_DIV_8) \\\n                                      || ((__VALUE__) == LL_RCC_APB2_DIV_16))\n\n#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2)  \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_3)  \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_4)  \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_5)  \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_6)  \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_7)  \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_8)  \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_9)  \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_63))\n\n#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((RCC_PLLN_MIN_VALUE <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLN_MAX_VALUE))\n\n#define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \\\n                                        || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \\\n                                        || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \\\n                                        || ((__VALUE__) == LL_RCC_PLLP_DIV_8))\n\n#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__)  ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))\n\n#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))\n\n#if !defined(RCC_MAX_FREQUENCY_SCALE1)\n#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \\\n                                             ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))\n\n#elif defined(RCC_MAX_FREQUENCY_SCALE3)\n#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \\\n                                              (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \\\n                                              ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))\n\n#else\n#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \\\n                                             ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))\n\n#endif /* RCC_MAX_FREQUENCY_SCALE1*/\n#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \\\n                                        || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))\n\n#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))\n/**\n  * @}\n  */\n/* Private function prototypes -----------------------------------------------*/\n/** @defgroup UTILS_LL_Private_Functions UTILS Private functions\n  * @{\n  */\nstatic uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,\n                                               LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);\nstatic ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);\nstatic ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);\nstatic ErrorStatus UTILS_PLL_IsBusy(void);\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup UTILS_LL_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup UTILS_LL_EF_DELAY\n  * @{\n  */\n\n/**\n  * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.\n  * @note   When a RTOS is used, it is recommended to avoid changing the Systick\n  *         configuration by calling this function, for a delay use rather osDelay RTOS service.\n  * @param  HCLKFrequency HCLK frequency in Hz\n  * @note   HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq\n  * @retval None\n  */\nvoid LL_Init1msTick(uint32_t HCLKFrequency)\n{\n  /* Use frequency provided in argument */\n  LL_InitTick(HCLKFrequency, 1000U);\n}\n\n/**\n  * @brief  This function provides accurate delay (in milliseconds) based\n  *         on SysTick counter flag\n  * @note   When a RTOS is used, it is recommended to avoid using blocking delay\n  *         and use rather osDelay service.\n  * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which\n  *         will configure Systick to 1ms\n  * @param  Delay specifies the delay time length, in milliseconds.\n  * @retval None\n  */\nvoid LL_mDelay(uint32_t Delay)\n{\n  __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */\n  /* Add this code to indicate that local variable is not used */\n  ((void)tmp);\n\n  /* Add a period to guaranty minimum wait */\n  if(Delay < LL_MAX_DELAY)\n  {\n    Delay++;\n  }\n\n  while (Delay)\n  {\n    if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)\n    {\n      Delay--;\n    }\n  }\n}\n\n/**\n  * @}\n  */\n\n/** @addtogroup UTILS_EF_SYSTEM\n  *  @brief    System Configuration functions\n  *\n  @verbatim\n ===============================================================================\n           ##### System Configuration functions #####\n ===============================================================================\n    [..]\n         System, AHB and APB buses clocks configuration\n\n         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 180000000 Hz.\n  @endverbatim\n  @internal\n             Depending on the device voltage range, the maximum frequency should be\n             adapted accordingly to the Refenece manual.\n  @endinternal\n  * @{\n  */\n\n/**\n  * @brief  This function sets directly SystemCoreClock CMSIS variable.\n  * @note   Variable can be calculated also through SystemCoreClockUpdate function.\n  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)\n  * @retval None\n  */\nvoid LL_SetSystemCoreClock(uint32_t HCLKFrequency)\n{\n  /* HCLK clock frequency */\n  SystemCoreClock = HCLKFrequency;\n}\n\n/**\n  * @brief  This function configures system clock at maximum frequency with HSI as clock source of the PLL\n  * @note   The application need to ensure that PLL is disabled.\n  * @note   Function is based on the following formula:\n  *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)\n  *         - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)\n  *         - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)\n  *         - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)\n  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains\n  *                             the configuration information for the PLL.\n  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains\n  *                             the configuration information for the BUS prescalers.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: Max frequency configuration done\n  *          - ERROR: Max frequency configuration not done\n  */\nErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,\n                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)\n{\n  ErrorStatus status = SUCCESS;\n  uint32_t pllfreq = 0U;\n\n  /* Check if one of the PLL is enabled */\n  if(UTILS_PLL_IsBusy() == SUCCESS)\n  {\n    /* Calculate the new PLL output frequency */\n    pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);\n\n    /* Enable HSI if not enabled */\n    if(LL_RCC_HSI_IsReady() != 1U)\n    {\n      LL_RCC_HSI_Enable();\n      while (LL_RCC_HSI_IsReady() != 1U)\n      {\n        /* Wait for HSI ready */\n      }\n    }\n\n    /* Configure PLL */\n    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,\n                                UTILS_PLLInitStruct->PLLP);\n\n    /* Enable PLL and switch system clock to PLL */\n    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);\n  }\n  else\n  {\n    /* Current PLL configuration cannot be modified */\n    status = ERROR;\n  }\n\n  return status;\n}\n\n/**\n  * @brief  This function configures system clock with HSE as clock source of the PLL\n  * @note   The application need to ensure that PLL is disabled.\n  *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)\n  *         - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)\n  *         - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)\n  *         - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)\n  * @param  HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000\n  * @param  HSEBypass This parameter can be one of the following values:\n  *         @arg @ref LL_UTILS_HSEBYPASS_ON\n  *         @arg @ref LL_UTILS_HSEBYPASS_OFF\n  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains\n  *                             the configuration information for the PLL.\n  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains\n  *                             the configuration information for the BUS prescalers.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: Max frequency configuration done\n  *          - ERROR: Max frequency configuration not done\n  */\nErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,\n                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)\n{\n  ErrorStatus status = SUCCESS;\n  uint32_t pllfreq = 0U;\n\n  /* Check the parameters */\n  assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));\n  assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));\n\n  /* Check if one of the PLL is enabled */\n  if(UTILS_PLL_IsBusy() == SUCCESS)\n  {\n    /* Calculate the new PLL output frequency */\n    pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);\n\n    /* Enable HSE if not enabled */\n    if(LL_RCC_HSE_IsReady() != 1U)\n    {\n      /* Check if need to enable HSE bypass feature or not */\n      if(HSEBypass == LL_UTILS_HSEBYPASS_ON)\n      {\n        LL_RCC_HSE_EnableBypass();\n      }\n      else\n      {\n        LL_RCC_HSE_DisableBypass();\n      }\n\n      /* Enable HSE */\n      LL_RCC_HSE_Enable();\n      while (LL_RCC_HSE_IsReady() != 1U)\n      {\n        /* Wait for HSE ready */\n      }\n    }\n\n    /* Configure PLL */\n    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,\n                                UTILS_PLLInitStruct->PLLP);\n\n    /* Enable PLL and switch system clock to PLL */\n    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);\n  }\n  else\n  {\n    /* Current PLL configuration cannot be modified */\n    status = ERROR;\n  }\n\n  return status;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup UTILS_LL_Private_Functions\n  * @{\n  */\n/**\n  * @brief  Update number of Flash wait states in line with new frequency and current\n            voltage range.\n  * @note   This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V\n  * @param  HCLK_Frequency  HCLK frequency\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: Latency has been modified\n  *          - ERROR: Latency cannot be modified\n  */\nstatic ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)\n{\n  ErrorStatus status = SUCCESS;\n\n  uint32_t latency = LL_FLASH_LATENCY_0;  /* default value 0WS */\n\n  /* Frequency cannot be equal to 0 */\n  if(HCLK_Frequency == 0U)\n  {\n    status = ERROR;\n  }\n  else\n  {\n    if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)\n    {\n#if defined (UTILS_SCALE1_LATENCY5_FREQ)\n      if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n      {\n        latency = LL_FLASH_LATENCY_5;\n      }\n#endif /*UTILS_SCALE1_LATENCY5_FREQ */\n#if defined (UTILS_SCALE1_LATENCY4_FREQ)\n      if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n      {\n        latency = LL_FLASH_LATENCY_4;\n      }\n#endif /* UTILS_SCALE1_LATENCY4_FREQ */\n#if defined (UTILS_SCALE1_LATENCY3_FREQ)\n      if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n      {\n        latency = LL_FLASH_LATENCY_3;\n      }\n#endif /* UTILS_SCALE1_LATENCY3_FREQ */\n#if defined (UTILS_SCALE1_LATENCY2_FREQ)\n      if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n      {\n        latency = LL_FLASH_LATENCY_2;\n      }\n      else\n      {\n        if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n        {\n          latency = LL_FLASH_LATENCY_1;\n        }\n      }\n#endif /* UTILS_SCALE1_LATENCY2_FREQ */\n    }\n    if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)\n    {\n#if defined (UTILS_SCALE2_LATENCY5_FREQ)\n      if((HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n      {\n        latency = LL_FLASH_LATENCY_5;\n      }\n#endif /*UTILS_SCALE1_LATENCY5_FREQ */\n#if defined (UTILS_SCALE2_LATENCY4_FREQ)\n      if((HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n      {\n        latency = LL_FLASH_LATENCY_4;\n      }\n#endif /*UTILS_SCALE1_LATENCY4_FREQ */\n#if defined (UTILS_SCALE2_LATENCY3_FREQ)\n      if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n      {\n        latency = LL_FLASH_LATENCY_3;\n      }\n#endif /*UTILS_SCALE1_LATENCY3_FREQ */\n      if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n      {\n        latency = LL_FLASH_LATENCY_2;\n      }\n      else\n      {\n        if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n        {\n          latency = LL_FLASH_LATENCY_1;\n        }\n      }\n    }\n#if defined (LL_PWR_REGU_VOLTAGE_SCALE3)\n    if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE3)\n    {\n#if defined (UTILS_SCALE3_LATENCY3_FREQ)\n      if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n      {\n        latency = LL_FLASH_LATENCY_3;\n      }\n#endif /*UTILS_SCALE1_LATENCY3_FREQ */\n#if defined (UTILS_SCALE3_LATENCY2_FREQ)\n      if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n      {\n        latency = LL_FLASH_LATENCY_2;\n      }\n      else\n      {\n        if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n        {\n          latency = LL_FLASH_LATENCY_1;\n        }\n      }\n    }\n#endif /*UTILS_SCALE1_LATENCY2_FREQ */\n#endif /* LL_PWR_REGU_VOLTAGE_SCALE3 */\n\n    LL_FLASH_SetLatency(latency);\n\n    /* Check that the new number of wait states is taken into account to access the Flash\n       memory by reading the FLASH_ACR register */\n    if(LL_FLASH_GetLatency() != latency)\n    {\n      status = ERROR;\n    }\n  }\n  return status;\n}\n\n/**\n  * @brief  Function to check that PLL can be modified\n  * @param  PLL_InputFrequency  PLL input frequency (in Hz)\n  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains\n  *                             the configuration information for the PLL.\n  * @retval PLL output frequency (in Hz)\n  */\nstatic uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)\n{\n  uint32_t pllfreq = 0U;\n\n  /* Check the parameters */\n  assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));\n  assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));\n  assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));\n\n  /* Check different PLL parameters according to RM                          */\n  /*  - PLLM: ensure that the VCO input frequency ranges from @ref UTILS_PLLVCO_INPUT_MIN to @ref UTILS_PLLVCO_INPUT_MAX MHz.   */\n  pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos));\n  assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));\n\n  /*  - PLLN: ensure that the VCO output frequency is between @ref UTILS_PLLVCO_OUTPUT_MIN and @ref UTILS_PLLVCO_OUTPUT_MAX .*/\n  pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));\n  assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));\n\n  /*  - PLLP: ensure that max frequency at @ref RCC_MAX_FREQUENCY Hz is reached     */\n  pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);\n  assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));\n\n  return pllfreq;\n}\n\n/**\n  * @brief  Function to check that PLL can be modified\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: PLL modification can be done\n  *          - ERROR: PLL is busy\n  */\nstatic ErrorStatus UTILS_PLL_IsBusy(void)\n{\n  ErrorStatus status = SUCCESS;\n\n  /* Check if PLL is busy*/\n  if(LL_RCC_PLL_IsReady() != 0U)\n  {\n    /* PLL configuration cannot be modified */\n    status = ERROR;\n  }\n\n#if defined(RCC_PLLSAI_SUPPORT)\n  /* Check if PLLSAI is busy*/\n  if(LL_RCC_PLLSAI_IsReady() != 0U)\n  {\n    /* PLLSAI1 configuration cannot be modified */\n    status = ERROR;\n  }\n#endif /*RCC_PLLSAI_SUPPORT*/\n#if defined(RCC_PLLI2S_SUPPORT)\n  /* Check if PLLI2S is busy*/\n  if(LL_RCC_PLLI2S_IsReady() != 0U)\n  {\n    /* PLLI2S configuration cannot be modified */\n    status = ERROR;\n  }\n#endif /*RCC_PLLI2S_SUPPORT*/\n  return status;\n}\n\n/**\n  * @brief  Function to enable PLL and switch system clock to PLL\n  * @param  SYSCLK_Frequency SYSCLK frequency\n  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains\n  *                             the configuration information for the BUS prescalers.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: No problem to switch system to PLL\n  *          - ERROR: Problem to switch system to PLL\n  */\nstatic ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)\n{\n  ErrorStatus status = SUCCESS;\n  uint32_t hclk_frequency = 0U;\n\n  assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));\n  assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));\n  assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));\n\n  /* Calculate HCLK frequency */\n  hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);\n\n  /* Increasing the number of wait states because of higher CPU frequency */\n  if(SystemCoreClock < hclk_frequency)\n  {\n    /* Set FLASH latency to highest latency */\n    status = UTILS_SetFlashLatency(hclk_frequency);\n  }\n\n  /* Update system clock configuration */\n  if(status == SUCCESS)\n  {\n    /* Enable PLL */\n    LL_RCC_PLL_Enable();\n    while (LL_RCC_PLL_IsReady() != 1U)\n    {\n      /* Wait for PLL ready */\n    }\n\n    /* Sysclk activation on the main PLL */\n    LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);\n    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);\n    while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)\n    {\n      /* Wait for system clock switch to PLL */\n    }\n\n    /* Set APB1 & APB2 prescaler*/\n    LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);\n    LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);\n  }\n\n  /* Decreasing the number of wait states because of lower CPU frequency */\n  if(SystemCoreClock > hclk_frequency)\n  {\n    /* Set FLASH latency to lowest latency */\n    status = UTILS_SetFlashLatency(hclk_frequency);\n  }\n\n  /* Update SystemCoreClock variable */\n  if(status == SUCCESS)\n  {\n    LL_SetSystemCoreClock(hclk_frequency);\n  }\n\n  return status;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/stm32f4xx_ll_utils.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_utils.h\n  * @author  MCD Application Team\n  * @version V1.7.1\n  * @date    14-April-2017\n  * @brief   Header file of UTILS LL module.\n  @verbatim\n  ==============================================================================\n                     ##### How to use this driver #####\n  ==============================================================================\n    [..]\n    The LL UTILS driver contains a set of generic APIs that can be\n    used by user:\n      (+) Device electronic signature\n      (+) Timing functions\n      (+) PLL configuration functions\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_LL_UTILS_H\n#define __STM32F4xx_LL_UTILS_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n/** @defgroup UTILS_LL UTILS\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants\n  * @{\n  */\n\n/* Max delay can be used in LL_mDelay */\n#define LL_MAX_DELAY                  0xFFFFFFFFU\n\n/**\n * @brief Unique device ID register base address\n */\n#define UID_BASE_ADDRESS              UID_BASE\n\n/**\n * @brief Flash size data register base address\n */\n#define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE\n\n/**\n * @brief Package data register base address\n */\n#define PACKAGE_BASE_ADDRESS          PACKAGE_BASE\n\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros\n  * @{\n  */\n/**\n  * @}\n  */\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures\n  * @{\n  */\n/**\n  * @brief  UTILS PLL structure definition\n  */\ntypedef struct\n{\n  uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.\n                        This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV\n\n                        This feature can be modified afterwards using unitary function\n                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */\n\n  uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.\n                        This parameter must be a number between Min_Data = @ref RCC_PLLN_MIN_VALUE\n                        and Max_Data = @ref RCC_PLLN_MIN_VALUE\n\n                        This feature can be modified afterwards using unitary function\n                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */\n\n  uint32_t PLLP;   /*!< Division for the main system clock.\n                        This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV\n\n                        This feature can be modified afterwards using unitary function\n                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */\n} LL_UTILS_PLLInitTypeDef;\n\n/**\n  * @brief  UTILS System, AHB and APB buses clock configuration structure definition\n  */\ntypedef struct\n{\n  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).\n                                       This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV\n\n                                       This feature can be modified afterwards using unitary function\n                                       @ref LL_RCC_SetAHBPrescaler(). */\n\n  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).\n                                       This parameter can be a value of @ref RCC_LL_EC_APB1_DIV\n\n                                       This feature can be modified afterwards using unitary function\n                                       @ref LL_RCC_SetAPB1Prescaler(). */\n\n  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).\n                                       This parameter can be a value of @ref RCC_LL_EC_APB2_DIV\n\n                                       This feature can be modified afterwards using unitary function\n                                       @ref LL_RCC_SetAPB2Prescaler(). */\n\n} LL_UTILS_ClkInitTypeDef;\n\n/**\n  * @}\n  */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants\n  * @{\n  */\n\n/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation\n  * @{\n  */\n#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */\n#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */\n/**\n  * @}\n  */\n\n/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE\n  * @{\n  */\n#define LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64                        0x00000000U /*!< WLCSP36 or UFQFPN48 or LQFP64 package type                         */\n#define LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48       0x00000100U /*!< WLCSP168 or FBGA169 or LQFP100 or LQFP64 or UFQFPN48 package type  */\n#define LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176               0x00000200U /*!< WLCSP64 or WLCSP81 or LQFP176 or UFBGA176 package type             */\n#define LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100             0x00000300U /*!< LQFP144 or UFBGA144 or UFBGA144 or UFBGA100 package type           */\n#define LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216                       0x00000400U /*!< LQFP100 or LQFP208 or TFBGA216 package type                        */\n#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216                               0x00000500U /*!< LQFP208 or TFBGA216 package type                                   */\n#define LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144                        0x00000700U /*!< TQFP64 or UFBGA144 or LQFP144 package type                         */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions\n  * @{\n  */\n\n/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE\n  * @{\n  */\n\n/**\n  * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)\n  * @retval UID[31:0]\n  */\n__STATIC_INLINE uint32_t LL_GetUID_Word0(void)\n{\n  return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));\n}\n\n/**\n  * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)\n  * @retval UID[63:32]\n  */\n__STATIC_INLINE uint32_t LL_GetUID_Word1(void)\n{\n  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));\n}\n\n/**\n  * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)\n  * @retval UID[95:64]\n  */\n__STATIC_INLINE uint32_t LL_GetUID_Word2(void)\n{\n  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));\n}\n\n/**\n  * @brief  Get Flash memory size\n  * @note   This bitfield indicates the size of the device Flash memory expressed in\n  *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.\n  * @retval FLASH_SIZE[15:0]: Flash memory size\n  */\n__STATIC_INLINE uint32_t LL_GetFlashSize(void)\n{\n  return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));\n}\n\n/**\n  * @brief  Get Package type\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_GetPackageType(void)\n{\n  return (uint8_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup UTILS_LL_EF_DELAY DELAY\n  * @{\n  */\n\n/**\n  * @brief  This function configures the Cortex-M SysTick source of the time base.\n  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)\n  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick\n  *         configuration by calling this function, for a delay use rather osDelay RTOS service.\n  * @param  Ticks Number of ticks\n  * @retval None\n  */\n__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)\n{\n  /* Configure the SysTick to have interrupt in 1ms time base */\n  SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */\n  SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */\n}\n\nvoid        LL_Init1msTick(uint32_t HCLKFrequency);\nvoid        LL_mDelay(uint32_t Delay);\n\n/**\n  * @}\n  */\n\n/** @defgroup UTILS_EF_SYSTEM SYSTEM\n  * @{\n  */\n\nvoid        LL_SetSystemCoreClock(uint32_t HCLKFrequency);\nErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,\n                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);\nErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,\n                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_LL_UTILS_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/system_stm32f4xx.c",
    "content": "/**\n  ******************************************************************************\n  * @file    system_stm32f4xx.c\n  * @author  MCD Application Team\n  * @version V1.0.0\n  * @date    17-February-2017\n  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.\n  *\n  *   This file provides two functions and one global variable to be called from\n  *   user application:\n  *      - SystemInit(): This function is called at startup just after reset and\n  *                      before branch to main program. This call is made inside\n  *                      the \"startup_stm32f4xx.s\" file.\n  *\n  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\n  *                                  by the user application to setup the SysTick\n  *                                  timer or configure other parameters.\n  *\n  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\n  *                                 be called whenever the core clock is changed\n  *                                 during program execution.\n  *\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32f4xx_system\n  * @{\n  */\n\n/** @addtogroup STM32F4xx_System_Private_Includes\n  * @{\n  */\n\n#include \"stm32f4xx.h\"\n\n#if !defined  (HSE_VALUE)\n  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */\n#endif /* HSE_VALUE */\n\n#if !defined  (HSI_VALUE)\n  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\n#endif /* HSI_VALUE */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Private_TypesDefinitions\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Private_Defines\n  * @{\n  */\n\n/************************* Miscellaneous Configuration ************************/\n\n/*!< Uncomment the following line if you need to relocate your vector Table in\n     Internal SRAM. */\n/* #define VECT_TAB_SRAM */\n#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.\n                                   This value must be a multiple of 0x200. */\n/******************************************************************************/\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Private_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Private_Variables\n  * @{\n  */\n  /* This variable is updated in three ways:\n      1) by calling CMSIS function SystemCoreClockUpdate()\n      2) by calling HAL API function HAL_RCC_GetHCLKFreq()\n      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\n         Note: If you use this function to configure the system clock; then there\n               is no need to call the 2 first functions listed above, since SystemCoreClock\n               variable is updated automatically.\n  */\nuint32_t SystemCoreClock = 16000000;\nconst uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\nconst uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Private_Functions\n  * @{\n  */\n\n/**\n  * @brief  Setup the microcontroller system\n  *         Initialize the FPU setting, vector table location and External memory\n  *         configuration.\n  * @param  None\n  * @retval None\n  */\nvoid SystemInit(void)\n{\n  /* Ensure double-word stack alignment is enabled. */\n  SCB->CCR |= SCB_CCR_STKALIGN_Msk;\n\n  /* FPU settings ------------------------------------------------------------*/\n  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\n    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */\n  #endif\n  /* Reset the RCC clock configuration to the default reset state ------------*/\n  /* Set HSION bit */\n  RCC->CR |= (uint32_t)0x00000001;\n\n  /* Reset CFGR register */\n  RCC->CFGR = 0x00000000;\n\n  /* Reset HSEON, CSSON and PLLON bits */\n  RCC->CR &= (uint32_t)0xFEF6FFFF;\n\n  /* Reset PLLCFGR register */\n  RCC->PLLCFGR = 0x24003010;\n\n  /* Reset HSEBYP bit */\n  RCC->CR &= (uint32_t)0xFFFBFFFF;\n\n  /* Disable all interrupts */\n  RCC->CIR = 0x00000000;\n\n  /* Configure the Vector Table location add offset address ------------------*/\n#ifdef VECT_TAB_SRAM\n  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\n#else\n  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\n#endif\n}\n\n/**\n   * @brief  Update SystemCoreClock variable according to Clock Register Values.\n  *         The SystemCoreClock variable contains the core clock (HCLK), it can\n  *         be used by the user application to setup the SysTick timer or configure\n  *         other parameters.\n  *\n  * @note   Each time the core clock (HCLK) changes, this function must be called\n  *         to update SystemCoreClock variable value. Otherwise, any configuration\n  *         based on this variable will be incorrect.\n  *\n  * @note   - The system frequency computed by this function is not the real\n  *           frequency in the chip. It is calculated based on the predefined\n  *           constant and the selected clock source:\n  *\n  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\n  *\n  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\n  *\n  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)\n  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.\n  *\n  *         (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value\n  *             16 MHz) but the real value may vary depending on the variations\n  *             in voltage and temperature.\n  *\n  *         (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value\n  *              depends on the application requirements), user has to ensure that HSE_VALUE\n  *              is same as the real frequency of the crystal used. Otherwise, this function\n  *              may have wrong result.\n  *\n  *         - The result of this function could be not correct when using fractional\n  *           value for HSE crystal.\n  *\n  * @param  None\n  * @retval None\n  */\nvoid SystemCoreClockUpdate(void)\n{\n  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;\n\n  /* Get SYSCLK source -------------------------------------------------------*/\n  tmp = RCC->CFGR & RCC_CFGR_SWS;\n\n  switch (tmp)\n  {\n    case 0x00:  /* HSI used as system clock source */\n      SystemCoreClock = HSI_VALUE;\n      break;\n    case 0x04:  /* HSE used as system clock source */\n      SystemCoreClock = HSE_VALUE;\n      break;\n    case 0x08:  /* PLL used as system clock source */\n\n      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N\n         SYSCLK = PLL_VCO / PLL_P\n         */\n      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;\n      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\n\n      if (pllsource != 0)\n      {\n        /* HSE used as PLL clock source */\n        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\n      }\n      else\n      {\n        /* HSI used as PLL clock source */\n        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\n      }\n\n      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;\n      SystemCoreClock = pllvco/pllp;\n      break;\n    default:\n      SystemCoreClock = HSI_VALUE;\n      break;\n  }\n  /* Compute HCLK frequency --------------------------------------------------*/\n  /* Get HCLK prescaler */\n  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\n  /* HCLK frequency */\n  SystemCoreClock >>= tmp;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/hal/system_stm32f4xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    system_stm32f4xx.h\n  * @author  MCD Application Team\n  * @version V2.6.1\n  * @date    14-February-2017\n  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32f4xx_system\n  * @{\n  */\n\n/**\n  * @brief Define to prevent recursive inclusion\n  */\n#ifndef __SYSTEM_STM32F4XX_H\n#define __SYSTEM_STM32F4XX_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/** @addtogroup STM32F4xx_System_Includes\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n\n/** @addtogroup STM32F4xx_System_Exported_types\n  * @{\n  */\n  /* This variable is updated in three ways:\n      1) by calling CMSIS function SystemCoreClockUpdate()\n      2) by calling HAL API function HAL_RCC_GetSysClockFreq()\n      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\n         Note: If you use this function to configure the system clock; then there\n               is no need to call the 2 first functions listed above, since SystemCoreClock\n               variable is updated automatically.\n  */\nextern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */\n\nextern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */\nextern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Exported_Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Exported_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Exported_Functions\n  * @{\n  */\n\nextern void SystemInit(void);\nextern void SystemCoreClockUpdate(void);\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /*__SYSTEM_STM32F4XX_H */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/include/_float.h",
    "content": "#ifndef _MACHINE__FLOAT_H_\n#define _MACHINE__FLOAT_H_\n\n/* Characteristics of IEEE floating types */\n\n#define FLT_RADIX       2\n#define FLT_ROUNDS      1\n\n/*\n * These values provide information pertaining to the float type.\n */\n#define FLT_EPSILON     1.19209290E-07F /* b**(1-p) */\n#define FLT_MAX         3.40282347E+38F /* (1-b**(-p))*b**emax */\n#define FLT_MIN         1.17549435E-38F /* b**(emin-1) */\n#define FLT_DIG         6               /* floor((p-1)*log10(b))+(b == 10) */\n#define FLT_MANT_DIG    24              /* p */\n#define FLT_MAX_10_EXP  38              /* floor(log10((1-b**(-p))*b**emax)) */\n#define FLT_MAX_EXP     128             /* emax */\n#define FLT_MIN_10_EXP  (-37)           /* ceil(log10(b**(emin-1))) */\n#define FLT_MIN_EXP     (-125)          /* emin */\n\n/*\n * These values provide information pertaining to the double type.\n */\n#define DBL_EPSILON     2.2204460492503131E-16\n#define DBL_MAX         1.7976931348623157E+308\n#define DBL_MIN         2.2250738585072014E-308\n#define DBL_DIG         15\n#define DBL_MANT_DIG    53\n#define DBL_MAX_10_EXP  308\n#define DBL_MAX_EXP     1024\n#define DBL_MIN_10_EXP  (-307)\n#define DBL_MIN_EXP     (-1021)\n\n/*\n * These values provide information pertaining to the long double type.\n */\n#define LDBL_EPSILON    DBL_EPSILON\n#define LDBL_MAX        DBL_MAX\n#define LDBL_MIN        DBL_MIN\n#define LDBL_DIG        DBL_DIG\n#define LDBL_MANT_DIG   DBL_MANT_DIG\n#define LDBL_MAX_10_EXP DBL_MAX_10_EXP\n#define LDBL_MAX_EXP    DBL_MAX_EXP\n#define LDBL_MIN_10_EXP DBL_MIN_10_EXP\n#define LDBL_MIN_EXP    DBL_MIN_EXP\n\n#endif /* _MACHINE__FLOAT_H_ */\n"
  },
  {
    "path": "sys/arch/stm32/include/cpu.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)cpu.h\t1.5 (2.11BSD GTE) 1998/4/3\n */\n\n/*\n * CTL_MACHDEP definitions.\n */\n#define\tCPU_CONSDEV\t\t1\t/* dev_t: console terminal device */\n#define\tCPU_ERRMSG\t\t2\t/* get error message by errno */\n#define\tCPU_NLIST\t\t3\t/* get name address */\n#define\tCPU_FREQ_KHZ\t\t4\t/* processor clock in kHz */\n#define\tCPU_BUS_KHZ\t\t5\t/* i/o bus clock in kHz */\n#define\tCPU_MPU\t\t\t6\t/* node: memory protection unit */\n#define\tCPU_MAXID\t\t7\t/* number of valid machdep ids */\n\n#ifndef\tKERNEL\n#define\tCTL_MACHDEP_NAMES { \\\n\t{ 0, 0 }, \\\n\t{ \"console_device\", CTLTYPE_STRUCT }, \\\n\t{ 0, 0 }, \\\n\t{ 0, 0 }, \\\n\t{ \"cpu_khz\", CTLTYPE_INT }, \\\n\t{ \"bus_khz\", CTLTYPE_INT }, \\\n\t{ \"mpu\", CTLTYPE_NODE }, \\\n}\n#endif\t/* !KERNEL */\n"
  },
  {
    "path": "sys/arch/stm32/include/debug.h",
    "content": "#ifndef _DEBUG_H\n#define _DEBUG_H\n\n#define DEBUG(...)\n#define DEBUG1(...)\n#define DEBUG2(...)\n#define DEBUG3(...)\n#define DEBUG4(...)\n#define DEBUG5(...)\n#define DEBUG6(...)\n#define DEBUG7(...)\n#define DEBUG8(...)\n#define DEBUG9(...)\n\n#ifdef GLOBAL_DEBUG\n#undef DEBUG\n#define DEBUG(...) printf(__VA_ARGS__)\n\n#if (GLOBAL_DEBUG>=1)\n#undef DEBUG1\n#define DEBUG1(...) printf(__VA_ARGS__)\n#endif\n\n#if (GLOBAL_DEBUG>=2)\n#undef DEBUG2\n#define DEBUG2(...) printf(__VA_ARGS__)\n#endif\n\n#if (GLOBAL_DEBUG>=3)\n#undef DEBUG3\n#define DEBUG3(...) printf(__VA_ARGS__)\n#endif\n\n#if (GLOBAL_DEBUG>=4)\n#undef DEBUG4\n#define DEBUG4(...) printf(__VA_ARGS__)\n#endif\n\n#if (GLOBAL_DEBUG>=5)\n#undef DEBUG5\n#define DEBUG5(...) printf(__VA_ARGS__)\n#endif\n\n#if (GLOBAL_DEBUG>=6)\n#undef DEBUG6\n#define DEBUG6(...) printf(__VA_ARGS__)\n#endif\n\n#if (GLOBAL_DEBUG>=7)\n#undef DEBUG7\n#define DEBUG7(...) printf(__VA_ARGS__)\n#endif\n\n#if (GLOBAL_DEBUG>=8)\n#undef DEBUG8\n#define DEBUG8(...) printf(__VA_ARGS__)\n#endif\n\n#if (GLOBAL_DEBUG>=9)\n#undef DEBUG9\n#define DEBUG9(...) printf(__VA_ARGS__)\n#endif\n\n#endif /* GLOBAL_DEBUG */\n\n#endif /* _DEBUG_H */\n"
  },
  {
    "path": "sys/arch/stm32/include/elf_machdep.h",
    "content": "/*\t$NetBSD: elf_machdep.h,v 1.19 2017/11/06 03:47:45 christos Exp $\t*/\n\n#ifndef _ARM_ELF_MACHDEP_H_\n#define _ARM_ELF_MACHDEP_H_\n\n#if defined(__ARMEB__)\n#define ELF32_MACHDEP_ENDIANNESS\tELFDATA2MSB\n#else\n#define ELF32_MACHDEP_ENDIANNESS\tELFDATA2LSB\n#endif\n\n#define ELF64_MACHDEP_ENDIANNESS\tXXX\t/* break compilation */\n#define ELF64_MACHDEP_ID_CASES                                          \\\n\t\t/* no 64-bit ELF machine types supported */\n\n/* Processor specific flags for the ELF header e_flags field.  */\n#define EF_ARM_RELEXEC\t\t0x00000001\n#define EF_ARM_HASENTRY\t\t0x00000002\n#define EF_ARM_INTERWORK\t0x00000004 /* GNU binutils 000413 */\n#define EF_ARM_SYMSARESORTED\t0x00000004 /* ARM ELF A08 */\n#define EF_ARM_APCS_26\t\t0x00000008 /* GNU binutils 000413 */\n#define EF_ARM_DYNSYMSUSESEGIDX\t0x00000008 /* ARM ELF B01 */\n#define EF_ARM_APCS_FLOAT\t0x00000010 /* GNU binutils 000413 */\n#define EF_ARM_MAPSYMSFIRST\t0x00000010 /* ARM ELF B01 */\n#define EF_ARM_PIC\t\t0x00000020\n#define EF_ARM_ALIGN8\t\t0x00000040 /* 8-bit structure alignment.  */\n#define EF_ARM_NEW_ABI\t\t0x00000080\n#define EF_ARM_OLD_ABI\t\t0x00000100\n#define EF_ARM_SOFT_FLOAT\t0x00000200\n#define EF_ARM_BE8\t\t0x00800000\n#define EF_ARM_EABIMASK\t\t0xff000000\n#define\tEF_ARM_EABI_VER1\t0x01000000\n#define\tEF_ARM_EABI_VER2\t0x02000000\n#define\tEF_ARM_EABI_VER3\t0x03000000\n#define\tEF_ARM_EABI_VER4\t0x04000000\n#define\tEF_ARM_EABI_VER5\t0x05000000\n\n#define\tELF32_MACHDEP_ID_CASES\t\t\t\t\t\t\\\n\t\tcase EM_ARM:\t\t\t\t\t\t\\\n\t\t\tbreak;\n\n#define\tELF32_MACHDEP_ID\tEM_ARM\n\n#define\tKERN_ELFSIZE\t\t32\n#define ARCH_ELFSIZE\t\t32\t/* MD native binary size */\n\n/* Processor specific relocation types */\n\n#define R_ARM_NONE\t\t0\n#define R_ARM_PC24\t\t1\n#define R_ARM_ABS32\t\t2\n#define R_ARM_REL32\t\t3\n#define R_ARM_PC13\t\t4\n#define R_ARM_ABS16\t\t5\n#define R_ARM_ABS12\t\t6\n#define R_ARM_THM_ABS5\t\t7\n#define R_ARM_ABS8\t\t8\n#define R_ARM_SBREL32\t\t9\n#define R_ARM_THM_PC22\t\t10\n#define R_ARM_THM_PC8\t\t11\n#define R_ARM_AMP_VCALL9\t12\n#define R_ARM_SWI24\t\t13\n#define R_ARM_THM_SWI8\t\t14\n#define R_ARM_XPC25\t\t15\n#define R_ARM_THM_XPC22\t\t16\n\n/* TLS relocations */\n#define R_ARM_TLS_DTPMOD32\t17\t/* ID of module containing symbol */\n#define R_ARM_TLS_DTPOFF32\t18\t/* Offset in TLS block */\n#define R_ARM_TLS_TPOFF32\t19\t/* Offset in static TLS block */\n\n/* 20-31 are reserved for ARM Linux. */\n#define R_ARM_COPY\t\t20\n#define R_ARM_GLOB_DAT\t\t21\n#define\tR_ARM_JUMP_SLOT\t\t22\n#define R_ARM_RELATIVE\t\t23\n#define\tR_ARM_GOTOFF\t\t24\n#define R_ARM_GOTPC\t\t25\n#define R_ARM_GOT32\t\t26\n#define R_ARM_PLT32\t\t27\n#define R_ARM_CALL\t\t28\n#define R_ARM_JUMP24\t\t29\n#define R_ARM_THM_JUMP24\t30\n#define R_ARM_BASE_ABS\t\t31\n#define R_ARM_ALU_PCREL_7_0\t32\n#define R_ARM_ALU_PCREL_15_8\t33\n#define R_ARM_ALU_PCREL_23_15\t34\n#define R_ARM_ALU_SBREL_11_0\t35\n#define R_ARM_ALU_SBREL_19_12\t36\n#define R_ARM_ALU_SBREL_27_20\t37\t/* deprecated */\n#define R_ARM_TARGET1\t\t38\n#define R_ARM_SBREL31\t\t39\t/* deprecated */\n#define R_ARM_V4BX\t\t40\n#define R_ARM_TARGET2\t\t41\n#define R_ARM_PREL31\t\t42\n#define R_ARM_MOVW_ABS_NC\t43\n#define R_ARM_MOVT_ABS\t\t44\n#define R_ARM_MOVW_PREL_NC\t45\n#define R_ARM_MOVT_PREL\t\t46\n#define R_ARM_THM_MOVW_ABS_NC\t47\n#define R_ARM_THM_MOVT_ABS\t48\n#define R_ARM_THM_MOVW_PREL_NC\t49\n#define R_ARM_THM_MOVT_PREL\t50\n\n/* 96-111 are reserved to G++. */\n#define R_ARM_GNU_VTENTRY\t100\n#define R_ARM_GNU_VTINHERIT\t101\n#define R_ARM_THM_PC11\t\t102\n#define R_ARM_THM_PC9\t\t103\n\n/* More TLS relocations */\n#define R_ARM_TLS_GD32\t\t104\t/* PC-rel 32 bit for global dynamic */\n#define R_ARM_TLS_LDM32\t\t105\t/* PC-rel 32 bit for local dynamic */\n#define R_ARM_TLS_LDO32\t\t106\t/* 32 bit offset relative to TLS */\n#define R_ARM_TLS_IE32\t\t107\t/* PC-rel 32 bit for GOT entry of */\n#define R_ARM_TLS_LE32\t\t108\n#define R_ARM_TLS_LDO12\t\t109\n#define R_ARM_TLS_LE12\t\t110\n#define R_ARM_TLS_IE12GP\t111\n\n/* 112-127 are reserved for private experiments. */\n\n#define R_ARM_IRELATIVE\t\t160\n\n#define R_ARM_RXPC25\t\t249\n#define R_ARM_RSBREL32\t\t250\n#define R_ARM_THM_RPC22\t\t251\n#define R_ARM_RREL32\t\t252\n#define R_ARM_RABS32\t\t253\n#define R_ARM_RPC24\t\t254\n#define R_ARM_RBASE\t\t255\n\n#define R_TYPE(name)\t\t__CONCAT(R_ARM_,name)\n\n/* Processor specific program header flags */\n#define PF_ARM_SB\t\t0x10000000\n#define PF_ARM_PI\t\t0x20000000\n#define PF_ARM_ENTRY\t\t0x80000000\n\n/* Processor specific program header types */\n#define PT_ARM_EXIDX\t\t(PT_LOPROC + 1)\n\n/* Processor specific section header flags */\n#define SHF_ENTRYSECT\t\t0x10000000\n#define SHF_COMDEF\t\t0x80000000\n\n/* Processor specific symbol types */\n#define STT_ARM_TFUNC\t\tSTT_LOPROC\n\n/*\n * Tell the kernel ELF exec code not to try relocating the interpreter\n * (ld.so) for dynamically-linked ELF binaries.\n */\n#ifdef _KERNEL\n#define ELF_INTERP_NON_RELOCATABLE\n#endif\n\n#endif /* _ARM_ELF_MACHDEP_H_ */\n"
  },
  {
    "path": "sys/arch/stm32/include/fault.h",
    "content": "/*\n * Copyright (c) 2023 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#ifndef\t_MACHINE_FAULT_H_\n#define\t_MACHINE_FAULT_H_\n\n/*\n * Fault types ARMv7-M\n *\n * Reference: \"ARMv7-M Architecture Reference Manual\"\n *\tDDI 0403E.d\n *\tJune 29, 2018\n *\tSections B3.2.14 - B3.2.18\n */\n\n/*\n * HardFault Status Register bit assignments\n * HFSR\n *\n * Bit position  |31                                          0|\n * HFSR register |          HardFault Status Register          |\n * Fault bits    | 11xx xxxx  xxxx xxxx   xxxx xxxx  xxxx xx1x |\n */\n\n#define\tFAULTED(reg, bit, mask)\t((((reg) & (mask)) >> (bit)) & 0x1)\n\n#define\tT_ALL_HARDF_MASK\t0xc0000002\t/* Fault bits of HFSR */\n#define\tHARD_FAULT(reg, bit)\tFAULTED(reg, bit, T_ALL_HARDF_MASK)\n\n/* HardFault */\n#define\tT_HF_VECTTBL\t\t 1\t/* vector read error */\n#define\tT_HF_FORCED\t\t30\t/* fault escalation */\n#define\tT_HF_DEBUGEVT\t\t31\t/* breakpoint escalation */\n\n/*\n * Configurable Fault Status Register bit assignments\n * CFSR = UFSR  UsageFault Status Register\n *\t| BFSR  BusFault Status Register\n *\t| MMFSR MemManage Fault Status Register\n *\n * Bit position  |31                 16|15        8|7         0|\n * CFSR register |      UsageFault     | BusFault  | MemManage |\n * Fault bits    | xxxx xx11 xxxx 1111 | xx11 1111 | xx11 1x11 |\n */\n\n#define\tT_CFSR_FAULTS_MASK\t0x030f3f3b\t/* Fault bits of CFSR */\n#define\tCFSR_FAULT(reg, bit)\tFAULTED(reg, bit, T_CFSR_FAULTS_MASK)\n\n/* MemManage Fault */\n#define\tT_MM_IACCVIOL\t\t 0\t/* instruction access */\n#define\tT_MM_DACCVIOL\t\t 1\t/* data access */\n#define\tT_MM_MUNSTKERR\t\t 3\t/* exception return unstacking */\n#define\tT_MM_MSTKERR\t\t 4\t/* exception entry stacking */\n#define\tT_MM_MLSPERR\t\t 5\t/* fp lazy state preservation */\n\n/* BusFault */\n#define\tT_BF_IBUSERR\t\t 8\t/* precise instruction prefetch */\n#define\tT_BF_PRECISERR\t\t 9\t/* precise data bus access */\n#define\tT_BF_IMPRECISERR\t10\t/* imprecise data bus access */\n#define\tT_BF_UNSTKERR\t\t11\t/* exception return unstacking */\n#define\tT_BF_STKERR\t\t12\t/* exception entry stacking */\n#define\tT_BF_LSPERR\t\t13\t/* fp lazy state preservation */\n\n/* UsageFault */\n#define\tT_UF_UNDEFINSTR\t\t16\t/* undefined instruction */\n#define\tT_UF_INVSTATE\t\t17\t/* invalid execution state */\n#define\tT_UF_INVPC\t\t18\t/* exception return integrity */\n#define\tT_UF_NOCP\t\t19\t/* no coprocessor access */\n#define\tT_UF_UNALIGNED\t\t24\t/* unaligned load or store */\n#define\tT_UF_DIVBYZERO\t\t25\t/* divide by zero */\n\n#define\tMMFARVALID_BIT\t\t0x0080\t/* CFSR bit[7] MMFAR contents valid */\n#define\tBFARVALID_BIT\t\t0x8000\t/* CFSR bit[15] BFAR contents valid */\n\n#define\tT_HF\t\t\t0x1\t/* Fault type HardFault */\n#define\tT_MM\t\t\t0x2\t/* Fault type MemManage Fault */\n#define\tT_BF\t\t\t0x4\t/* Fault type BusFault */\n#define\tT_UF\t\t\t0x8\t/* Fault type UsageFault */\n\n#define\tMM_FAULT_ENABLE\t\tSCB_SHCSR_MEMFAULTENA_Msk\n#define\tBF_FAULT_ENABLE\t\tSCB_SHCSR_BUSFAULTENA_Msk\n#define\tUF_FAULT_ENABLE\t\tSCB_SHCSR_USGFAULTENA_Msk\n\nstatic inline void\narm_disable_fault(uint32_t fault)\n{\n\tSCB->SHCSR &= ~fault;\n}\n\nstatic inline void\narm_enable_fault(uint32_t fault)\n{\n\tSCB->SHCSR |= fault;\n}\n\nstatic inline void\narm_clear_fault(int bit, int type)\n{\n\t/* Writing a 1 to the fault indicator bit will clear it. */\n\tswitch (type) {\n\t/* Fault type is HardFault. */\n\tcase T_HF:\n\t\tSCB->HFSR |= 1UL << bit;\n\t\tbreak;\n\t/* Fault type is MemManage Fault, BusFault, or UsageFault. */\n\tcase T_MM:\n\tcase T_BF:\n\tcase T_UF:\n\t\tSCB->CFSR |= 1UL << bit;\n\t\tbreak;\n\t/* Unknown fault type. */\n\tdefault:\n\t\tprintf(\"not clearing unknown fault type %d\\n\", type);\n\t\tbreak;\n\t}\n}\n\n#endif\t/* !_MACHINE_FAULT_H_ */\n"
  },
  {
    "path": "sys/arch/stm32/include/frame.h",
    "content": "/*\n * Copyright (c) 2021, 2022 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#ifndef _MACHINE_FRAME_H_\n#define _MACHINE_FRAME_H_\n\n#define\tINSN_SZ\t\t2\t/* Thumb are 2 bytes; some are 4 bytes. */\n\n#define\tPSR_C\t\t(1UL << 29U)\t/* Carry bit. */\n\nstruct\ttrapframe {\n/* The following 8 registers are pushed on stack by hardware in an SVCall. */\n\tu_int\ttf_r0;\t\t/* Argument / Scratch Register 1 */\n\tu_int\ttf_r1;\t\t/* Argument / Scratch Register 2 */\n\tu_int\ttf_r2;\t\t/* Argument / Scratch Register 3 */\n\tu_int\ttf_r3;\t\t/* Argument / Scratch Register 4 */\n\tu_int\ttf_ip;\t\t/* Stack Pointer (as passed by IP) */\n\tu_int\ttf_lr;\t\t/* Link Register */\n\tu_int\ttf_pc;\t\t/* Program Counter */\n\tu_int\ttf_psr;\t\t/* Program Status Register */\n/* The following 8 registers are manually pushed on stack in SVC_Handler. */\n\tu_int\ttf_r4;\t\t/* Variable Register 1 */\n\tu_int\ttf_r5;\t\t/* Variable Register 2 */\n\tu_int\ttf_r6;\t\t/* Variable Register 3 */\n\tu_int\ttf_r7;\t\t/* Variable Register 4 */\n\tu_int\ttf_r8;\t\t/* Variable Register 5 */\n\tu_int\ttf_r9;\t\t/* Variable Register 6 */\n\tu_int\ttf_r10;\t\t/* Variable Register 7 */\n\tu_int\ttf_r11;\t\t/* Variable Register 8 or Frame Pointer */\n};\n\n#define\ttf_r12\ttf_ip\t\t/* Intra-Procedure-Call Scratch Register */\n#define\ttf_sp\ttf_ip\t\t/* Stack Pointer (as passed by IP) */\n#define\ttf_r14\ttf_lr\t\t/* Link Register */\n#define\ttf_r15\ttf_pc\t\t/* Program Counter */\n\n/*\n * Exception stack frame of a SysTick exception.\n * A clockframe encapsulates the machine state when the SysTick\n * exception occured.\n * The clockframe is used by hardclock(), softclock(), and gatherstats().\n */\nstruct\tclockframe {\n/* These 8 registers are pushed on stack by hardware in an exception. */\n\tu_int\tcf_r0;\t\t/* Argument / Scratch Register 1 */\n\tu_int\tcf_r1;\t\t/* Argument / Scratch Register 2 */\n\tu_int\tcf_r2;\t\t/* Argument / Scratch Register 3 */\n\tu_int\tcf_r3;\t\t/* Argument / Scratch Register 4 */\n\tu_int\tcf_ip;\t\t/* Stack Pointer (as passed by IP) */\n\tu_int\tcf_lr;\t\t/* Link Register */\n\tu_int\tcf_pc;\t\t/* Program Counter */\n\tu_int\tcf_psr;\t\t/* Program Status Register */\n};\n\n#define\tcf_sp\tcf_ip\t\t/* Stack Pointer (as passed by IP) */\n\n/*\n * Exception stack frame of a fault exception.\n * A faultframe encapsulates the machine state when the fault occured.\n *\n * ARMv6-M fault types: HardFault\n * ARMv7-M fault types: HardFault, MemManage, BusFault, UsageFault\n */\nstruct\tfaultframe {\n/* These 8 registers are pushed on stack by hardware in a fault exception. */\n\tu_int\tff_r0;\t\t/* Argument / Scratch Register 1 */\n\tu_int\tff_r1;\t\t/* Argument / Scratch Register 2 */\n\tu_int\tff_r2;\t\t/* Argument / Scratch Register 3 */\n\tu_int\tff_r3;\t\t/* Argument / Scratch Register 4 */\n\tu_int\tff_ip;\t\t/* Stack Pointer (as passed by IP) */\n\tu_int\tff_lr;\t\t/* Link Register */\n\tu_int\tff_pc;\t\t/* Program Counter */\n\tu_int\tff_psr;\t\t/* Program Status Register */\n};\n\n#define\tff_sp\tff_ip\t\t/* Stack Pointer (as passed by IP) */\n\n#endif /* !_MACHINE_FRAME_H_ */\n"
  },
  {
    "path": "sys/arch/stm32/include/intr.h",
    "content": "/*\n * Copyright (c) 2022 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#ifndef\t_MACHINE_INTR_H_\n#define\t_MACHINE_INTR_H_\n\n#ifdef\tKERNEL\n\n#include <stm32/hal/stm32f4xx.h>\n\n/*\n * Logical interrupt priority level: low prio (0) -> high prio (6)\n * Interrupts at or lower than numerical level are blocked.\n *\n * Notes:\n * - IPLs are the inverse of the Cortex-M hardware interrupt scheme.\n *     low prio (0b111x.xxxx) -> high prio (0b001x.xxxx), 3 NVIC prio bits\n *     low prio (0b0111.xxxx) -> high prio (0b0001.xxxx), 4 NVIC prio bits\n * - A zero value disables BASEPRI register; IPL levels are 0 -> 6.\n * - PendSV exception is IPL level 0; SVCall exception is IPL level 7.\n */\n#define\tIPL_NONE\t0\t/* Blocks nothing. */\n#define\tIPL_SOFTCLOCK\t1\t/* Blocks low-priority clock processing. */\n#define\tIPL_NET\t\t2\t/* Blocks network protocol processing. */\n#define\tIPL_BIO\t\t3\t/* Blocks disk controllers. */\n#define\tIPL_TTY\t\t4\t/* Blocks terminal multiplexers. */\n#define\tIPL_CLOCK\t5\t/* Blocks high-priority clock processing. */\n#define\tIPL_HIGH\t6\t/* Blocks all interrupt activity. */\n\n#define\tIPL_TOP\t\t(IPL_HIGH + 1)\t/* +1 since zero disables BASEPRI. */\n#define\tIPL_BITS\t(8U - __NVIC_PRIO_BITS)\t/* MSB prio shift bits. */\n\n/* Cortex-M core exception/interrupt priority levels. */\n#define\tIPL_PENDSV\tIPL_NONE\t/* PendSV exception at lowest prio. */\n#define\tIPL_SVCALL\tIPL_TOP\t\t/* SVC exception at highest prio. */\n#define\tIPL_SYSTICK\tIPL_CLOCK\t/* SysTick exception at clock prio. */\n\n#define\tIPLTOREG(ipl) \\\n\t(uint8_t)((ipl) ? (((IPL_TOP - (ipl)) << IPL_BITS) & 0xFFUL) : 0)\n#define\tREGTOIPL(reg) \\\n\t(uint32_t)((reg) ? (IPL_TOP - ((reg) >> IPL_BITS)) : 0)\n\nstatic inline int\narm_intr_disable(void)\n{\n\tint s = __get_PRIMASK();\n\t__disable_irq();\t\t\t/* Disable interrupts. */\n\t__ISB();\n\treturn s;\n}\n\nstatic inline int\narm_intr_enable(void)\n{\n\tint s = __get_PRIMASK();\n\t__enable_irq();\t\t\t\t/* Enable interrupts. */\n\t__ISB();\n\treturn s;\n}\n\nstatic inline void\narm_intr_restore(int s)\n{\n\t__set_PRIMASK(s);\n\t__ISB();\n}\n\nstatic inline void\narm_intr_disable_irq(int irq)\n{\n\tNVIC_DisableIRQ(irq);\n}\n\nstatic inline void\narm_intr_enable_irq(int irq)\n{\n\tNVIC_EnableIRQ(irq);\n}\n\nstatic inline void\narm_intr_set_priority(int irq, int prio)\n{\n\t/*\n\t * This CMSIS function bitshifts prio into the most significant bits\n\t * and expects an inverted prio for the Cortex-M interrupt priority\n\t * scheme (zero has more priority than one), so IPL_TOP - prio.\n\t */\n\tNVIC_SetPriority(irq, IPL_TOP - prio);\n}\n\n#ifdef __thumb2__\n\nstatic inline int\nsplraise(int new)\n{\n\tint old;\n\n\told = REGTOIPL(__get_BASEPRI());\n\t__set_BASEPRI_MAX(IPLTOREG(new));\n\t__ISB();\n\n\treturn old;\n}\n\n#define\tsplhigh()\tsplraise(IPL_HIGH)\n#define\tsplclock()\tsplraise(IPL_CLOCK)\n#define\tspltty()\tsplraise(IPL_TTY)\n#define\tsplnet()\tsplraise(IPL_NET)\n#define\tsplbio()\tsplraise(IPL_BIO)\n\n#define\tsplsoftclock()\tsplraise(IPL_SOFTCLOCK)\n\nstatic inline void\nsplx(int s)\n{\n\t__set_BASEPRI(IPLTOREG(s));\n\t__ISB();\n}\n\nstatic inline int\nspl0(void)\n{\n\tint old;\n\n\told = REGTOIPL(__get_BASEPRI());\n\tsplx(IPL_NONE);\n\n\treturn old;\n}\n\n#else /* __thumb__ */\n\n#define\tsplhigh()\tarm_intr_disable()\n#define\tsplclock()\tarm_intr_disable()\n#define\tspltty()\tarm_intr_disable()\n#define\tsplnet()\tarm_intr_disable()\n#define\tsplbio()\tarm_intr_disable()\n\n#define\tsplsoftclock()\tarm_intr_enable()\n\n#define\tsplx(s)\t\tarm_intr_restore(s)\n\n#define\tspl0()\t\tarm_intr_enable()\n\n#endif\n\n#endif\t/* KERNEL */\n\n#endif\t/* !_MACHINE_INTR_H_ */\n"
  },
  {
    "path": "sys/arch/stm32/include/io.h",
    "content": "/*\n * Hardware register defines for MIPS32 architecture.\n *\n * Copyright (C) 2008-2010 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n\n#ifndef __ASSEMBLER__\n\n#ifndef KERNEL\n/*\n * 2BSD system call extensions: use with care.\n */\n\n/*\n * Read peripheral register.\n */\nunsigned ufetch (unsigned addr);\n\n/*\n * Write peripheral register.\n */\nunsigned ustore (unsigned addr, unsigned value);\n\n/*\n * Call a kernel function.\n */\nunsigned ucall (int priority, void *address, int arg1, int arg2);\n\n#endif /* KERNEL */\n\n#endif /* __ASSEMBLER__ */\n"
  },
  {
    "path": "sys/arch/stm32/include/limits.h",
    "content": "/*\n * Copyright (c) 1988, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n *\t@(#)limits.h\t8.3.1 (2.11BSD) 1996/1/11\n */\n\n#define CHAR_BIT        8               /* number of bits in a char */\n\n/*\n * According to ANSI (section 2.2.4.2), the values below must be usable by\n * #if preprocessing directives.  Additionally, the expression must have the\n * same type as would an expression that is an object of the corresponding\n * type converted according to the integral promotions.  The subtraction for\n * INT_MIN and LONG_MIN is so the value is not unsigned; 2147483648 is an\n * unsigned int for 32-bit two's complement ANSI compilers (section 3.1.3.2).\n * These numbers work for pcc as well.  The UINT_MAX and ULONG_MAX values\n * are written as hex so that GCC will be quiet about large integer constants.\n */\n#define SCHAR_MAX       127             /* min value for a signed char */\n#define SCHAR_MIN       (-128)          /* max value for a signed char */\n\n#define UCHAR_MAX       255             /* max value for an unsigned char */\n#define CHAR_MAX        127             /* max value for a char */\n#define CHAR_MIN        (-128)          /* min value for a char */\n\n#define USHRT_MAX       65535           /* max value for an unsigned short */\n#define SHRT_MAX        32767           /* max value for a short */\n#define SHRT_MIN        (-32768)        /* min value for a short */\n\n#define UINT_MAX        0xffffffff      /* max value for an unsigned int */\n#define INT_MAX         2147483647      /* max value for an int */\n#define INT_MIN         (-2147483647-1) /* min value for an int */\n\n#define ULONG_MAX       0xffffffff      /* max value for an unsigned long */\n#define LONG_MAX        2147483647L     /* max value for a long */\n#define LONG_MIN        (-2147483647L-1L)       /* min value for a long */\n\n#define SSIZE_MAX       INT_MAX         /* max value for a ssize_t */\n#define SIZE_T_MAX      UINT_MAX        /* max value for a size_t */\n"
  },
  {
    "path": "sys/arch/stm32/include/machparam.h",
    "content": "/*\n * Machine dependent constants for STM32.\n *\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)machparam.h\t1.4 (2.11BSD GTE) 1998/9/15\n */\n\n#ifndef ENDIAN\n\n#define MACHINE         \"stm32\"\n#define MACHINE_ARCH    \"arm\"\n\n/*\n * Definitions for byte order,\n * according to byte significance from low address to high.\n */\n#define LITTLE          1234            /* least-significant byte first (vax) */\n#define BIG             4321            /* most-significant byte first */\n#define PDP             3412            /* LSB first in word, MSW first in long (pdp) */\n#define ENDIAN          LITTLE          /* byte order on stm32 */\n\n/*\n * The time for a process to be blocked before being very swappable.\n * This is a number of seconds which the system takes as being a non-trivial\n * amount of real time.  You probably shouldn't change this;\n * it is used in subtle ways (fractions and multiples of it are, that is, like\n * half of a ``long time'', almost a long time, etc.)\n * It is related to human patience and other factors which don't really\n * change over time.\n */\n#define MAXSLP          20\n\n/*\n * Clock ticks per second. The HZ value must be an integer factor of 1000.\n * Cortex-M SysTick operates with a 1ms time base, hence 1000 for HZ.\n */\n#ifndef HZ\n#define HZ              1000\n#endif\n\n/*\n * System parameter formulae.\n */\n#ifndef NBUF\n#define NBUF            10                      /* number of i/o buffers */\n#endif\n#ifndef MAXUSERS\n#define MAXUSERS        1                       /* number of user logins */\n#endif\n#ifndef NPROC\n#define NPROC           25                      /* number of processes */\n#endif\n#ifndef NINODE\n#define NINODE          24\n#endif\n#ifndef NFILE\n#define NFILE           24\n#endif\n#define NNAMECACHE      (NINODE * 11/10)\n#define NCALL           (16 + 2 * MAXUSERS)\n#define NCLIST          32                      /* number or CBSIZE blocks */\n#ifndef SMAPSIZ\n#define SMAPSIZ         NPROC                   /* size of swap allocation map */\n#endif\n\n/*\n * Disk blocks.\n */\n#define DEV_BSIZE       1024            /* the same as MAXBSIZE */\n#define DEV_BSHIFT      10              /* log2(DEV_BSIZE) */\n#define DEV_BMASK       (DEV_BSIZE-1)\n\n/* Bytes to disk blocks */\n#define btod(x)         (((x) + DEV_BSIZE-1) >> DEV_BSHIFT)\n\n#if 1 /* XXX Needed for ps, w, smlrc. To be removed. */\n#define USER_DATA_START         (0x20000000)\n#define USER_DATA_SIZE          (96 * 1024)     /* 96kb for user RAM. */\n#define USER_DATA_END           (USER_DATA_START + USER_DATA_SIZE)\n\n#define stacktop(siz)           (USER_DATA_END)\n#define stackbas(siz)           (USER_DATA_END-(siz))\n#endif /* XXX Needed for ps, w, smlrc. To be removed. */\n\n/*\n * User area: a user structure, followed by the kernel\n * stack.  The number for USIZE is determined empirically.\n *\n * Note that the SBASE and STOP constants are only used by the assembly code,\n * but are defined here to localize information about the user area's\n * layout (see pdp/genassym.c).  Note also that a networking stack is always\n * allocated even for non-networking systems.  This prevents problems with\n * applications having to be recompiled for networking versus non-networking\n * systems.\n */\n#define USIZE           3072\n#define SSIZE           2048            /* initial stack size (bytes) */\n\n/*\n * Collect kernel statistics by default.\n */\n#if !defined(UCB_METER) && !defined(NO_UCB_METER)\n#define UCB_METER\n#endif\n\n#ifdef KERNEL\n#include <machine/intr.h>\n\n/*\n * Macros to decode processor status word.\n */\n#define USERMODE(psr)   ((psr & IPSR_ISR_Msk) == 0)     /* No exceptions. */\n#define BASEPRI(psr)    (__get_BASEPRI() == 0)          /* No masking. */\n\n#define noop()          asm volatile(\"nop\")\n\n/*\n * Wait for something to happen.\n */\nvoid idle(void);\n\n/*\n * Millisecond delay routine.\n */\nvoid mdelay(unsigned msec);\n\n/*\n * Setup system timer for `hz' timer interrupts per second.\n */\nvoid clkstart(void);\n\n/*\n * Control LEDs, installed on the board.\n */\n#define LED_TTY         0x08\n#define LED_SWAP        0x04\n#define LED_DISK        0x02\n#define LED_KERNEL      0x01\n#define LED_ALL         (LED_TTY | LED_SWAP | LED_DISK | LED_KERNEL)\n\nvoid led_control(int mask, int on);\n\nvoid LL_GPIO_EnableClock(GPIO_TypeDef *GPIOx);\n\n#endif /* KERNEL */\n\n#endif /* ENDIAN */\n"
  },
  {
    "path": "sys/arch/stm32/include/mpuvar.h",
    "content": "/*\n * Copyright (c) 2025 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#ifndef\t_MACHINE_MPUVAR_H_\n#define\t_MACHINE_MPUVAR_H_\n\nint\tmpu_sysctl(int *, u_int, void *, size_t *, void *, size_t);\n\n/*\n * CTL_MPU definitions.\n */\n#define\tCPU_MPU_ENABLE\t\t1\n#define\tCPU_MPU_CTRL\t\t2\n#define\tCPU_MPU_NREGIONS\t3\n#define\tCPU_MPU_SEPARATE\t4\n#define\tCPU_MPU_MAXID\t\t5\n\n#ifndef\tKERNEL\n#define\tCTL_MPU_NAMES { \\\n\t{ 0, 0 }, \\\n\t{ \"enable\", CTLTYPE_INT }, \\\n\t{ \"ctrl\", CTLTYPE_INT }, \\\n\t{ \"nregions\", CTLTYPE_INT }, \\\n\t{ \"separate\", CTLTYPE_INT }, \\\n}\n#endif\t/* !KERNEL */\n\n#endif\t/* !_MACHINE_MPUVAR_H_ */\n"
  },
  {
    "path": "sys/arch/stm32/include/setjmp.h",
    "content": "/*\n * Copyright (c) 2022 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#ifndef _MACHINE_SETJMP_H_\n#define _MACHINE_SETJMP_H_\n\n/*\n * Total 12 words for Arm architecture:\n * Two for signal mask:\n *\tenv[0]:\t\tsavesigs\n *\tenv[1]:\t\tsignal mask\n * Ten for registers:\n *\tenv[2-11]:\tv1-v8, ip, lr (r4-r11, r12, r14)\n */\n#define _JBLEN 12\n\n#endif /* !_MACHINE_SETJMP_H_ */\n"
  },
  {
    "path": "sys/arch/stm32/include/signal.h",
    "content": "/*\n * Copyright (c) 2021, 2022 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#ifndef _MACHINE_SIGNAL_H_\n#define _MACHINE_SIGNAL_H_\n\n/*\n * Information pushed on stack when a signal is delivered.\n * This is used by the kernel to restore state following\n * execution of the signal handler.  It is also made available\n * to the handler to allow it to properly restore state if\n * a non-standard exit is performed.\n */\nstruct\tsigcontext {\n\tint\tsc_onstack;\t/* sigstack state to restore */\n\tlong\tsc_mask;\t/* signal mask to restore */\n\tu_int\tsc_r0;\n\tu_int\tsc_r1;\n\tu_int\tsc_r2;\n\tu_int\tsc_r3;\n\tu_int\tsc_ip;\n\tu_int\tsc_lr;\n\tu_int\tsc_pc;\n\tu_int\tsc_psr;\n\tu_int\tsc_r4;\n\tu_int\tsc_r5;\n\tu_int\tsc_r6;\n\tu_int\tsc_r7;\n\tu_int\tsc_r8;\n\tu_int\tsc_r9;\n\tu_int\tsc_r10;\n\tu_int\tsc_r11;\n};\n\n#define\tsc_r12\tsc_ip\t\t/* Intra-Procedure-Call Scratch Register */\n#define\tsc_sp\tsc_ip\t\t/* Stack Pointer (as passed by IP) */\n#define\tsc_r14\tsc_lr\t\t/* Link Register */\n#define\tsc_r15\tsc_pc\t\t/* Program Counter */\n\n#endif /* !_MACHINE_SIGNAL_H_ */\n"
  },
  {
    "path": "sys/arch/stm32/include/types.h",
    "content": "/*\n * Copyright (c) 2022 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#ifndef\t_ARM_TYPES_H_\n#define\t_ARM_TYPES_H_\n\ntypedef\tstruct label_t {\n\t/* regs v1-v7, FP, IP/SP, LR (r4-r10, r11, r12, r14) */\n\tlong val[10];\n} label_t;\n\n#endif\t/* !_ARM_TYPES_H_ */\n"
  },
  {
    "path": "sys/arch/stm32/stm32/clock.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)clock.c\t1.1 (2.10BSD Berkeley) 12/1/86\n */\n\n#include <sys/param.h>\n\n/*\n * Setup core timer for `hz' timer interrupts per second.\n */\nvoid\nclkstart(void)\n{\n}\n"
  },
  {
    "path": "sys/arch/stm32/stm32/conf.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)conf.c\t3.2 (2.11BSD GTE) 1997/11/12\n */\n\n#include <sys/param.h>\n#include <sys/conf.h>\n#include <sys/buf.h>\n#include <sys/time.h>\n#include <sys/ioctl.h>\n#include <sys/resource.h>\n#include <sys/inode.h>\n#include <sys/proc.h>\n#include <sys/clist.h>\n#include <sys/tty.h>\n#include <sys/systm.h>\n#include <sys/errno.h>\n\n#include <sys/swap.h>\n\n#include <stm32/dev/spi.h>\n#include <stm32/dev/uart.h>\n\n#ifdef SD_ENABLED\n#include <stm32/dev/sd.h>\n#endif\n\n#ifdef PTY_ENABLED\n#include <sys/pty.h>\n#endif\n\n#ifdef SDIO_ENABLED\n#include <stm32/dev/sdio.h>\n#endif\n\n#define __unused\t__attribute__((__unused__))\t/* XXX */\n\nint\nnullopen(dev_t dev __unused, int flag __unused, int mode __unused)\n{\n\treturn 0;\n}\n\nint\nnullclose(dev_t dev __unused, int flag __unused, int mode __unused)\n{\n\treturn 0;\n}\n\nint\nnoopen(dev_t dev __unused, int flag __unused, int mode __unused)\n{\n\treturn ENXIO;\n}\n\nint\nnoclose(dev_t dev __unused, int flag __unused, int mode __unused)\n{\n\treturn ENXIO;\n}\n\nint\nnorw(dev_t dev __unused, struct uio *uio __unused, int flag __unused)\n{\n\treturn 0;\n}\n\nint\nnoioctl(dev_t dev __unused, u_int cmd __unused, caddr_t data __unused,\n    int flag __unused)\n{\n\treturn EIO;\n}\n\nint\nnullstop(struct tty *tp __unused, int flag __unused)\n{\n\treturn 0;\n}\n\n/*\n * root attach routine.\n */\ndaddr_t\nnosize(dev_t dev __unused)\n{\n\treturn 0;\n}\n\n#define NOBDEV \\\n\t\tnoopen,\t\tnoclose,\tnostrategy, \\\n\t\tnosize,\t\tnoioctl,\t0\n\n/*\n * The RetroDisks require the same master number as the disk entry in the\n * rdisk.c file.  A bit of a bind, but it means that the RetroDisk\n * devices must be numbered from master 0 upwards.\n */\nconst struct bdevsw bdevsw[] = {\n\t{\t/* 0 - sd */\n#ifdef SD_ENABLED\n\t\tsdopen,\t\tsdclose,\tsdstrategy,\n\t\tsdsize,\t\tsdioctl,\t0\n#else\n\t\tNOBDEV\n#endif\n\t},\n\t{\t/* 1 - sramc */\n\t\tNOBDEV\n\t},\n\t{\t/* 2 - sdramp */\n\t\tNOBDEV\n\t},\n\t{\t/* 3 - mrams */\n\t\tNOBDEV\n\t},\n\t{\t/* 4 - swap */\n\t\tswopen,\t\tswclose,\tswstrategy,\n\t\tswsize,\t\tswcioctl,\t0\n\t},\n\t{\t/* 5 - spirams */\n\t\tNOBDEV\n\t},\n\n\t/*\n\t * End the list with a blank entry.\n\t */\n\t{ 0 },\n};\n\nconst int nblkdev = sizeof(bdevsw) / sizeof(bdevsw[0]) - 1;\n\n#define NOCDEV \\\n\t\tnoopen,\t\tnoclose,\tnorw,\t\tnorw, \\\n\t\tnoioctl,\tnullstop,\t0,\t\tseltrue, \\\n\t\tnostrategy,\t0,\t\t0,\n\nconst struct cdevsw cdevsw[] = {\n\t/*\n\t * Static drivers - every system has these:\n\t */\n\t{\t/* 0 - console */\n\t\tcnopen,\t\tcnclose,\tcnread,\t\tcnwrite,\n\t\tcnioctl,\tnullstop,\tcnttys,\t\tcnselect,\n\t\tnostrategy,\t0,\t\t0,\n\t},\n\t{\t/* 1 - mem, kmem, null, zero */\n#if MEM_MAJOR != 1\n#error Wrong MEM_MAJOR value!\n#endif\n\t\tnullopen,\tnullclose,\tmmrw,\t\tmmrw,\n\t\tnoioctl,\tnullstop,\t0,\t\tseltrue,\n\t\tnostrategy,\t0,\t\t0,\n\t},\n\t{\t/* 2 - tty */\n\t\tsyopen,\t\tnullclose,\tsyread,\t\tsywrite,\n\t\tsyioctl,\tnullstop,\t0,\t\tsyselect,\n\t\tnostrategy,\t0,\t\t0,\n\t},\n\t{\t/* 3 - fd */\n\t\tfdopen,\t\tnullclose,\tnorw,\t\tnorw,\n\t\tnoioctl,\tnullstop,\t0,\t\tseltrue,\n\t\tnostrategy,\t0,\t\t0,\n\t},\n\t{\t/* 4 - temp (temporary allocation in swap space) */\n\t\tswcopen,\tswcclose,\tswcread,\tswcwrite,\n\t\tswcioctl,\tnullstop,\t0,\t\tseltrue,\n\t\tnostrategy,\t0,\t\t0,\n\t},\n\n\t/*\n\t * Optional drivers from here on:\n\t */\n\t{\t/* 5 - log */\n#ifdef LOG_ENABLED\n\t\tlogopen,\tlogclose,\tlogread,\tnorw,\n\t\tlogioctl,\tnullstop,\t0,\t\tlogselect,\n\t\tnostrategy,\t0,\t\t0,\n#else\n\t\tNOCDEV\n#endif\n\t},\n\t{\t/* 6 - tty uart */\n#if UART_MAJOR != 6\n#error Wrong UART_MAJOR value!\n#endif\n#if defined(UART1_ENABLED) || defined(UART2_ENABLED) || \\\n    defined(UART3_ENABLED) || defined(UART4_ENABLED) || \\\n    defined(UART5_ENABLED) || defined(UART6_ENABLED)\n\t\tuartopen,\tuartclose,\tuartread,\tuartwrite,\n\t\tuartioctl,\tnullstop,\tuartttys,\tuartselect,\n\t\tnostrategy,\tuartgetc,\tuartputc,\n#else\n\t\tNOCDEV\n#endif\n\t},\n\t{\t/* 7 - tty usb */\n\t\tNOCDEV\n\t},\n\t{\t/* 8, 9 - pty */\n#ifdef PTY_ENABLED\n\t\tptsopen,\tptsclose,\tptsread,\tptswrite,\n\t\tptyioctl,\tnullstop,\tpt_tty,\t\tptcselect,\n\t\tnostrategy,\t0,\t\t0,\n\t},\n\t{\n\t\tptcopen,\tptcclose,\tptcread,\tptcwrite,\n\t\tptyioctl,\tnullstop,\tpt_tty,\t\tptcselect,\n\t\tnostrategy,\t0,\t\t0,\n#else\n\t\tNOCDEV\n\t},\n\t{\n\t\tNOCDEV\n#endif\n\t},\n\t{\t/* 10 - gpio */\n\t\tNOCDEV\n\t},\n\t{\t/* 11 - adc */\n\t\tNOCDEV\n\t},\n\t{\t/* 12 - spi */\n#if defined(SPI1_ENABLED) || defined(SPI2_ENABLED) || \\\n    defined(SPI3_ENABLED) || defined(SPI4_ENABLED) || \\\n    defined(SPI5_ENABLED) || defined(SPI6_ENABLED) || \\\n    defined(SPI7_ENABLED) || defined(SPI8_ENABLED)\n\t\tspi_open,\tspi_close,\tspi_read,\tspi_write,\n\t\tspi_ioctl,\tnullstop,\t0,\t\tseltrue,\n\t\tnostrategy,\t0,\t\t0,\n#else\n\t\tNOCDEV\n#endif\n\t},\n\t{\t/* 13 - glcd */\n\t\tNOCDEV\n\t},\n\t{\t/* 14 - pwm */\n\t\tNOCDEV\n\t},\n\t{\t/* 15 - picga */\t/* Ignore this for now - it's WIP. */\n\t\tNOCDEV\n\t},\n\t{\t/* 16 - hxtft, gpanel, sgpanel */\n\t\tNOCDEV\n\t},\n\t{\t/* 17 - skel */\n\t\tNOCDEV\n\t},\n\t{\t/* 18 - sdio */\n#ifdef SDIO_ENABLED\n\t\tsdio_open,\tsdio_close,\tsdio_read,\tsdio_write,\n\t\tsdio_ioctl,\tnullstop,\t0,\t\tseltrue,\n\t\tnostrategy,\t0,\t\t0,\n#else\n\t\tNOCDEV\n#endif\n\t},\n\n\t/*\n\t * End the list with a blank entry.\n\t */\n\t{ 0 },\n};\n\nconst int nchrdev = sizeof(cdevsw) / sizeof(cdevsw[0]) - 1;\n\n/*\n * Routine that identifies /dev/mem and /dev/kmem.\n *\n * A minimal stub routine can always return 0.\n */\nint\niskmemdev(dev_t dev)\n{\n\tif (major(dev) == 1 && (minor(dev) == 0 || minor(dev) == 1))\n\t\treturn 1;\n\n\treturn 0;\n}\n\n/*\n * Routine to determine if a device is a disk.\n *\n * A minimal stub routine can always return 0.\n */\nint\nisdisk(dev_t dev, int type)\n{\n\tif (type != IFBLK)\n\t\treturn 0;\n\n\tswitch (major(dev)) {\n\tcase 0:\t\t\t\t/* rd0 */\n\tcase 1:\t\t\t\t/* rd1 */\n\tcase 2:\t\t\t\t/* rd2 */\n\tcase 3:\t\t\t\t/* rd3 */\n\tcase 4:\t\t\t\t/* sw */\n\t\treturn 1;\n\tdefault:\n\t\treturn 0;\n\t}\n\t/* NOTREACHED */\n}\n\n/*\n * Routine to convert from character to block device number.\n * A minimal stub routine can always return NODEV.\n */\nint\nchrtoblk(dev_t dev __unused)\n{\n\treturn NODEV;\n}\n"
  },
  {
    "path": "sys/arch/stm32/stm32/fault.c",
    "content": "/*\n * Copyright (c) 2022, 2023 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n/*\n * ARMv7-M Fault Handling\n */\n\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/vm.h>\n\n#include <machine/fault.h>\n#include <machine/frame.h>\n\n/*\n * Fault descriptions of Configurable Fault Status Register bits.\n */\nconst char * const fault_type[] = {\n\t\"instruction access\",\t\t\t/*  0 T_MM_IACCVIOL */\n\t\"data access\",\t\t\t\t/*  1 T_MM_DACCVIOL */\n\t\"reserved\",\n\t\"exception return unstacking\",\t\t/*  3 T_MM_MUNSTKERR */\n\t\"exception entry stacking\",\t\t/*  4 T_MM_MSTKERR */\n\t\"fp lazy state preservation\",\t\t/*  5 T_MM_MLSPERR */\n\t\"reserved\",\n\t\"reserved\",\n\t\"precise instruction prefetch\",\t\t/*  8 T_BF_IBUSERR */\n\t\"precise data bus access\",\t\t/*  9 T_BF_PRECISERR */\n\t\"imprecise data bus access\",\t\t/* 10 T_BF_IMPRECISERR */\n\t\"exception return unstacking\",\t\t/* 11 T_BF_UNSTKERR */\n\t\"exception entry stacking\",\t\t/* 12 T_BF_STKERR */\n\t\"fp lazy state preservation\",\t\t/* 13 T_BF_LSPERR */\n\t\"reserved\",\n\t\"reserved\",\n\t\"undefined instruction\",\t\t/* 16 T_UF_UNDEFINSTR */\n\t\"invalid execution state\",\t\t/* 17 T_UF_INVSTATE */\n\t\"exception return integrity\",\t\t/* 18 T_UF_INVPC */\n\t\"no coprocessor access\",\t\t/* 19 T_UF_NOCP */\n\t\"reserved\",\n\t\"reserved\",\n\t\"reserved\",\n\t\"reserved\",\n\t\"unaligned load or store\",\t\t/* 24 T_UF_UNALIGNED */\n\t\"divide by zero\",\t\t\t/* 25 T_UF_DIVBYZERO */\n};\n\nconst int fault_types = sizeof(fault_type) / sizeof(fault_type[0]);\n\n/*\n * Bus error received during vector fetch.\n * Escalation of configurable fault exceptions.\n * Execution of breakpoint instruction (BKPT) with a debugger attached\n * (halt debugging not enabled) and debug monitor exception not enabled.\n */\nvoid\nHardFault_Handler(void)\n{\n__asm volatile (\n\"\t.syntax\tunified\t\t\\n\\t\"\n\"\t.thumb\t\t\t\\n\\t\"\n\n\"\tmov\tr2, #(0x01)\t\\n\\t\"\t/* Fault type is HardFault T_HF. */\n\"\tmov\tr1, lr\t\t\\n\\t\"\t/* Value of lr when fault occurred. */\n\"\ttst\tlr, #0x4\t\\n\\t\"\t/* Test bit 2 (SPSEL) of EXC_RETURN. */\n\"\tite\teq\t\t\\n\\t\"\t/* Came from user or kernel mode? */\n\"\tmrseq\tr0, MSP\t\t\\n\\t\"\t/* Kernel mode; fault frame on MSP. */\n\"\tmrsne\tr0, PSP\t\t\\n\\t\"\t/* User mode; fault frame on PSP. */\n\"\tb\tarm_fault\t\\n\\t\"\t/* Call arm_fault(frame, lr, type); */\n);\n}\n\n/*\n * Violation of access rules defined by MPU configuration.\n * Attempt to execute program code in execute never (XN) region.\n */\nvoid\nMemManage_Handler(void)\n{\n__asm volatile (\n\"\t.syntax\tunified\t\t\\n\\t\"\n\"\t.thumb\t\t\t\\n\\t\"\n\n\"\tmov\tr2, #(0x02)\t\\n\\t\"\t/* Fault type is MemManage T_MM. */\n\"\tmov\tr1, lr\t\t\\n\\t\"\t/* Value of lr when fault occurred. */\n\"\ttst\tlr, #0x4\t\\n\\t\"\t/* Test bit 2 (SPSEL) of EXC_RETURN. */\n\"\tite\teq\t\t\\n\\t\"\t/* Came from user or kernel mode? */\n\"\tmrseq\tr0, MSP\t\t\\n\\t\"\t/* Kernel mode; fault frame on MSP. */\n\"\tmrsne\tr0, PSP\t\t\\n\\t\"\t/* User mode; fault frame on PSP. */\n\"\tb\tarm_fault\t\\n\\t\"\t/* Call arm_fault(frame, lr, type); */\n);\n}\n\n/*\n * Error responses received from the processor bus interface\n * during a memory access, for example:\n *   instruction fetch or read, also called prefetch abort;\n *   data read or write, also called data abort.\n * Bus fault during stacking/unstacking of exception handling sequence.\n *\n * Attempt to access an invalid memory location.\n * Unprivileged access to the Private Peripheral Bus (PPB) that\n * violates the default memory access permission.\n */\nvoid\nBusFault_Handler(void)\n{\n__asm volatile (\n\"\t.syntax\tunified\t\t\\n\\t\"\n\"\t.thumb\t\t\t\\n\\t\"\n\n\"\tmov\tr2, #(0x04)\t\\n\\t\"\t/* Fault type is BusFault T_BF. */\n\"\tmov\tr1, lr\t\t\\n\\t\"\t/* Value of lr when fault occurred. */\n\"\ttst\tlr, #0x4\t\\n\\t\"\t/* Test bit 2 (SPSEL) of EXC_RETURN. */\n\"\tite\teq\t\t\\n\\t\"\t/* Came from user or kernel mode? */\n\"\tmrseq\tr0, MSP\t\t\\n\\t\"\t/* Kernel mode; fault frame on MSP. */\n\"\tmrsne\tr0, PSP\t\t\\n\\t\"\t/* User mode; fault frame on PSP. */\n\"\tb\tarm_fault\t\\n\\t\"\t/* Call arm_fault(frame, lr, type); */\n);\n}\n\n/*\n * Execution of undefined instruction or co-processor instruction.\n * Trying to switch to ARM state (only Thumb ISA is supported).\n * Invalid EXC_RETURN code during exception return sequence.\n * Unaligned memory access with multiple load or store instructions.\n * Execution of SVC when priority level of SVC is same or lower\n * than current level.\n * Exception return with Interrupt-Continuable Instruction (ICI)\n * bits in unstacked xPSR, but instruction being executed after\n * exception return is not a multiple-load/store instruction.\n *\n * If Configuration Control Register (CCR) is set up:\n *   Divide by zero;\n *   All unaligned memory accesses.\n */\nvoid\nUsageFault_Handler(void)\n{\n__asm volatile (\n\"\t.syntax\tunified\t\t\\n\\t\"\n\"\t.thumb\t\t\t\\n\\t\"\n\n\"\tmov\tr2, #(0x08)\t\\n\\t\"\t/* Fault type is UsageFault T_UF. */\n\"\tmov\tr1, lr\t\t\\n\\t\"\t/* Value of lr when fault occurred. */\n\"\ttst\tlr, #0x4\t\\n\\t\"\t/* Test bit 2 (SPSEL) of EXC_RETURN. */\n\"\tite\teq\t\t\\n\\t\"\t/* Came from user or kernel mode? */\n\"\tmrseq\tr0, MSP\t\t\\n\\t\"\t/* Kernel mode; fault frame on MSP. */\n\"\tmrsne\tr0, PSP\t\t\\n\\t\"\t/* User mode; fault frame on PSP. */\n\"\tb\tarm_fault\t\\n\\t\"\t/* Call arm_fault(frame, lr, type); */\n);\n}\n\nvoid\narm_fault(struct faultframe *frame, uint32_t fault_lr, int type)\n{\n\tint psig = SIGILL;\t\t/* Default signal. */\n\ttime_t syst;\n\tint bit;\n\n\t/* MUST read MMFAR and BFAR registers before reading CFSR. */\n\tuint32_t mmfar = SCB->MMFAR;\t/* MemManage Fault Address */\n\tuint32_t bfar = SCB->BFAR;\t/* BusFault Address */\n\n\tuint32_t hfsr = SCB->HFSR;\t/* HardFault Status */\n\tuint32_t cfsr = SCB->CFSR;\t/* Configurable Fault Status */\n\n\t/* If true, MMFAR holds the MemManage fault-triggering address. */\n\tuint32_t mmfarvalid = cfsr & MMFARVALID_BIT;\t/* CFSR bit[7] */\n\n\t/* If true, BFAR holds the BusFault fault-triggering address. */\n\tuint32_t bfarvalid = cfsr & BFARVALID_BIT;\t/* CFSR bit[15] */\n\n\tled_control(LED_KERNEL, 1);\n\tsyst = u.u_ru.ru_stime;\n#ifdef UCB_METER\n\tcnt.v_trap++;\n#endif\n\n\tprintf(\"fault type: 0x%x\", type);\n\tprintf(\"%s\\n\", HARD_FAULT(hfsr, T_HF_FORCED) ?\n\t    \", fault escalated\" : \"\");\n\n\tfor (bit = 0; bit < fault_types; ++bit) {\n\t\tif (CFSR_FAULT(cfsr, bit)) {\n\t\t\tprintf(\"fault %d: %s, \", bit, fault_type[bit]);\n\t\t\tswitch (bit) {\n\t\t\tcase T_MM_IACCVIOL:\n\t\t\tcase T_MM_DACCVIOL:\n\t\t\tcase T_MM_MUNSTKERR:\n\t\t\tcase T_MM_MSTKERR:\n\t\t\tcase T_MM_MLSPERR:\n\t\t\t\tpsig = SIGSEGV;\n\t\t\t\tprintf(\"MemManage Fault\\n\");\n\t\t\t\tarm_clear_fault(bit, T_MM);\n\t\t\t\tbreak;\n\t\t\tcase T_BF_IBUSERR:\n\t\t\tcase T_BF_PRECISERR:\n\t\t\tcase T_BF_IMPRECISERR:\n\t\t\tcase T_BF_UNSTKERR:\n\t\t\tcase T_BF_STKERR:\n\t\t\tcase T_BF_LSPERR:\n\t\t\t\tpsig = SIGBUS;\n\t\t\t\tprintf(\"BusFault\\n\");\n\t\t\t\tarm_clear_fault(bit, T_BF);\n\t\t\t\tbreak;\n\t\t\tcase T_UF_UNDEFINSTR:\n\t\t\tcase T_UF_INVSTATE:\n\t\t\tcase T_UF_INVPC:\n\t\t\tcase T_UF_NOCP:\n\t\t\tcase T_UF_UNALIGNED:\n\t\t\tcase T_UF_DIVBYZERO:\n\t\t\t\tpsig = SIGILL;\n\t\t\t\tprintf(\"UsageFault\\n\");\n\t\t\t\tarm_clear_fault(bit, T_UF);\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tpsig = SIGILL;\n\t\t\t\tprintf(\"unknown fault type\\n\");\n\t\t\t\tarm_clear_fault(bit, type);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\tprintf(\"fault trap frame:\\n\");\n\tprintf(\" r0:\\t0x%08x\\tip:\\t0x%08x\\n\", frame->ff_r0, frame->ff_ip);\n\tprintf(\" r1:\\t0x%08x\\tlr:\\t0x%08x\\n\", frame->ff_r1, frame->ff_lr);\n\tprintf(\" r2:\\t0x%08x\\tpc:\\t0x%08x\\n\", frame->ff_r2, frame->ff_pc);\n\tprintf(\" r3:\\t0x%08x\\tpsr:\\t0x%08x\\n\", frame->ff_r3, frame->ff_psr);\n\n\tprintf(\"fault status registers:\\n\");\n\tprintf(\" hfsr:\\t0x%08x\\tcfsr:\\t0x%08x\\n\", hfsr, cfsr);\n\tprintf(\"fault address registers:\\n\");\n\tprintf(\" mmfar:\\t0x%08x\\t%svalid\\n\", mmfar, mmfarvalid ? \"\" : \"not \");\n\tprintf(\" bfar:\\t0x%08x\\t%svalid\\n\", bfar, bfarvalid ? \"\" : \"not \");\n\tprintf(\"fault entry EXC_RETURN value:\\n\");\n\tprintf(\" lr:\\t0x%08x\\n\", fault_lr);\n\n\tarm_intr_enable();\n\n\tpsignal(u.u_procp, psig);\n\tuserret(frame->ff_pc, syst);\n\n\tled_control(LED_KERNEL, 0);\n}\n"
  },
  {
    "path": "sys/arch/stm32/stm32/locore.S",
    "content": "/*\n * Copyright (c) 2022 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#define UBASE 0x20000000\t/* User space base address. */\n#define USIZE 3072\t\t/* From user.h */\n\n\t.syntax\tunified\n\t.thumb\n\n/*\n * setjmp(env)\n *\tlabel_t *env;\n *\n * setjmp(env) will save the process' current register context\n * and return a zero.\n */\n\t.text\n\t.align\t2\n\t.thumb_func\n\t.globl\tsetjmp\n\t.type\tsetjmp, %function\nsetjmp:\n\tmov\tip, sp\n#ifdef __thumb2__\n\tstmea\tr0!, {r4-r10,fp,ip,lr}\t/* Save regs in env arg. */\n#else /* __thumb__ */\n\tstmea\tr0!, {r4-r7}\t\t/* Save v1-v4 in env arg. Incr r0. */\n\tmov\tr4, r8\t\t\t/* Bring high register v5 to low. */\n\tmov\tr5, r9\t\t\t/* Bring high register v6 to low. */\n\tmov\tr6, r10\t\t\t/* Bring high register v7 to low. */\n\tmov\tr7, r11\t\t\t/* Bring high register v8 to low. */\n\tstmea\tr0!, {r4-r7}\t\t/* Save v5-v8 in env arg. Incr r0. */\n\tmov\tr4, ip\t\t\t/* Bring high register ip to low. */\n\tmov\tr5, lr\t\t\t/* Bring high register lr to low. */\n\tstmea\tr0!, {r4-r5}\t\t/* Save ip and lr in env arg. */\n#endif\n\tmovs\tr0, #0\t\t\t/* Returns zero. */\n\tbx\tlr\n\t.size\tsetjmp, . - setjmp\n\n/*\n * longjmp(u, env)\n * resume(u, env)\n *\tmemaddr\tu;\n *\tlabel_t\t*env;\n *\n * longjmp(u, env) (and resume) will generate a \"return(1)\" from the last\n * call to setjmp(env) by mapping in the user structure pointed to by u,\n * restoring the context saved by setjmp in env and returning a one.\n * Note that registers are recovered statically from the env buffer rather\n * than dynamically from the stack ...\n *\n * This longjmp differs from the longjmp found in the standard library and\n * the VAX 4.3 kernel - it's actually closer to the resume routine of the\n * 4.3 kernel and, indeed, even used to be called resume in the 2.9 kernel.\n * We've given it both names to promote some degree of compatibility between\n * the 4.3 and 2.10 C kernel source ...\n */\n\t.extern u0\n\t.extern u\n\n\t.text\n\t.align\t2\n\t.thumb_func\n\t.globl\tlongjmp\n\t.type\tlongjmp, %function\nlongjmp:\n\t.globl\tresume\n\t.type\tresume, %function\nresume:\n\tcpsid\ti\t\t\t/* Disable interrupts. */\n\n\tmov\tr10, a2\t\t\t/* Save env (second arg). */\n\tldr\tr1, =u0\t\t\t/* Pointer to u0. area start addr. */\n\tldr\tr2, =u\t\t\t/* Pointer to u. area start addr. */\n\tcmp\ta1, r2\t\t\t/* If u (first arg) is not u. area, */\n\tbne\t1f\t\t\t/*   then remap u. area. */\n\tldr\tr3, =(2f + 1)\t\t/*   else no need to remap u. area. */\n\tbx\tr3\t\t\t/*   The +1 sets Thumb mode bit. */\n\t.pool\t\t\t\t/* Insert literal pool for labels. */\n1:\n\tldr\tr3, [r2, #0]\t\t/* Pointer to u.u_procp structure. */\n\tstr\tr1, [r3, #60]\t\t/* Save &u0 in u.u_procp->p_addr. */\n\n\t/* Exchange contents of u. and u0. */\n\tmov\tr0, r2\t\t\t/* Pointer to u. area start addr. */\n\n\t.rept\tUSIZE / 3 / 4\t\t/* 4 * 3 * 256 = 3072 = USIZE */\n#ifdef __thumb2__\n\tldmia\tr0, {r2-r4}\n\tldmia\tr1, {r5-r7}\n#else /* __thumb__ */\n\tldmia\tr0!, {r2-r4}\n\tldmia\tr1!, {r5-r7}\n\tsubs\tr0, #(3 * 4)\n\tsubs\tr1, #(3 * 4)\n#endif\n\tstmia\tr1!, {r2-r4}\n\tstmia\tr0!, {r5-r7}\n\t.endr\n\n\tldr\tr2, =u\t\t\t/* Pointer to u. area start addr. */\n\n\tldr\tr3, [r2, #0]\t\t/* Pointer to u.u_procp structure. */\n\tstr\tr2, [r3, #60]\t\t/* Save &u in u.u_procp->p_addr. */\n2:\n\tmov\ta2, r10\t\t\t/* Restore env (second arg). */\n#ifdef __thumb2__\n\tldmia\ta2!, {r4-r10,fp,ip,lr}\t/* Restore regs from env arg. */\n#else /* __thumb__ */\n\tadds\ta2, #(8 * 4)\t\t/* Index to &env[8]. */\n\tldmia\ta2!, {r4-r5}\t\t/* Restore ip and lr to low regs. */\n\tmov\tip, r4\t\t\t/* Move temp low register to ip. */\n\tmov\tlr, r5\t\t\t/* Move temp low register to lr. */\n\tsubs\ta2, #(6 * 4)\t\t/* Index to &env[4]. */\n\tldmia\ta2!, {r4-r7}\t\t/* Restore v5-v8 to low regs. */\n\tmov\tr8, r4\t\t\t/* Move temp low register to v5. */\n\tmov\tr9, r5\t\t\t/* Move temp low register to v6. */\n\tmov\tr10, r6\t\t\t/* Move temp low register to v7. */\n\tmov\tr11, r7\t\t\t/* Move temp low register to v8. */\n\tsubs\ta2, #(8 * 4)\t\t/* Index to &env[0]. */\n\tldmia\ta2!, {r4-r7}\t\t/* Restore v1-v4 to own registers. */\n#endif\n\tmov\tsp, ip\n\n\tcpsie\ti\t\t\t/* Enable interrupts. */\n\n\tmovs\ta1, #1\t\t\t/* Transfer back to setjmp() return */\n\tbx\tlr\t\t\t/*   with a return value of one. */\n\t.pool\t\t\t\t/* Literal pool for local labels. */\n\t.size\tlongjmp, . - longjmp\n\n/*\n * icode() is copied out to process 1 to exec /sbin/init.\n * If the exec fails, process 1 exits.\n */\n\t.text\n\t.align\t2\n\t.globl\ticode\n\t.type\ticode, %object\nicode:\n\t.thumb_func\n\t.type\ticode1, %function\nicode1:\n\tmovs.n\tr0, #(sbininit - icode)\t/* Offset for /sbin/init path. */\n\tmovs.n\tr1, #(argv - icode)\t/* Offset for *argv[] array. */\n\tldr\tr2, =UBASE\t\t/* User space base address. */\n\tadd\tr0, r2\t\t\t/* execv() *name argument. */\n\tadd\tr1, r2\t\t\t/* execv() *argv[] argument. */\n\tsvc\t#11\t\t\t/* Make SYS_execv syscall. */\n\tsvc\t#1\t\t\t/* Make SYS_exit syscall. */\n\nforever:\t\t\t\t/* Catch runaway code. */\n\tb\tforever\n\t.pool\t\t\t\t/* Put literal pool inside icode(). */\n\n\t.align\t2\n\t.type\tsbininit, %object\nsbininit:\n\t.ascii\t\"/sbin/init\\0\"\n\n\t.globl\tinitflags\n\t.type\tinitflags, %object\ninitflags:\n\t.ascii\t\"-\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\t/* Space for options. */\n\n\t.align\t2\n\t.type\targv, %object\nargv:\n\t.word\tsbininit+6-icode+UBASE\t/* Address of \"init\\0\". */\n\t.word\tinitflags-icode+UBASE\t/* Init options. */\n\t.word\t0\n\n\t.globl\ticodeend\n\t.type\ticodeend, %object\nicodeend:\n\t.size\ticode, . - icode\n"
  },
  {
    "path": "sys/arch/stm32/stm32/locore0.S",
    "content": "/**\n  ******************************************************************************\n  * @file      startup_stm32f407xx.s\n  * @author    MCD Application Team\n  * @version   V1.0.0\n  * @date      17-February-2017\n  * @brief     STM32F407xx Devices vector table for GCC based toolchains.\n  *\n  *            After Reset the Cortex-M4 processor is in Thread mode,\n  *            priority is Privileged, and the Stack is set to Main.\n  *\n  *            This module performs:\n  *                - Set initial SP,\n  *                - Set initial PC == Reset_Handler,\n  *                - Set vector table entries with exception ISR addresses,\n  *                - Branch to main(), set up user mode, then run icode().\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n\t.syntax\tunified\n\t.cpu\tcortex-m4\n\t.fpu\tsoftvfp\n\t.thumb\n\n\t.globl\tg_pfnVectors\n\t.globl\tDefault_Handler\n\n\t/*\n\t * Memory addresses defined in linker script.\n\t */\n\t.word\t__user_data_start\t/* Start addr of user RAM. */\n\t.word\t__user_data_end\t\t/* End addr of user RAM. */\n\t.word\tu_end\t\t\t/* End addr of kernel RAM u. area. */\n\t.word\t_sidata\t\t\t/* Start addr for .data init values. */\n\t.word\t_sdata\t\t\t/* Start addr for .data section. */\n\t.word\t_edata\t\t\t/* End addr for .data section. */\n\t.word\t_sbss\t\t\t/* Start addr for .bss section. */\n\t.word\t_ebss\t\t\t/* End addr for .bss section. */\n\n\t.section\t.text.Reset_Handler\n\t.weak\tReset_Handler\n\t.type\tReset_Handler, %function\nReset_Handler:\n\tldr\tsp, =_estack\t/* Set Main Stack Pointer (MSP). */\n\n\t/* Zero fill the data segment. */\n\tldr\tr2, =_sdata\n\tb\tLoopFillZeroData\nFillZeroData:\n\tmovs\tr3, #0\n\tstr\tr3, [r2], #4\nLoopFillZeroData:\n\tldr\tr3, =u_end\n\tcmp\tr2, r3\n\tbcc\tFillZeroData\n\n\t/* Copy data segment initializers from flash to SRAM. */\n\tmovs\tr1, #0\n\tb\tLoopCopyDataInit\nCopyDataInit:\n\tldr\tr3, =_sidata\n\tldr\tr3, [r3, r1]\n\tstr\tr3, [r0, r1]\n\tadds\tr1, r1, #4\nLoopCopyDataInit:\n\tldr\tr0, =_sdata\n\tldr\tr3, =_edata\n\tadds\tr2, r0, r1\n\tcmp\tr2, r3\n\tbcc\tCopyDataInit\n\n\t/* Zero fill the bss segment. */\n\tldr\tr2, =_sbss\n\tb\tLoopFillZeroBss\nFillZeroBss:\n\tmovs\tr3, #0\n\tstr\tr3, [r2], #4\nLoopFillZeroBss:\n\tldr\tr3, =_ebss\n\tcmp\tr2, r3\n\tbcc\tFillZeroBss\n\nsystem_init_and_main:\n\tbl\tSystemInit\n\tbl\tmain\n\n\t/*\n\t * Switch from kernel mode to user mode in user space.\n\t */\nsetup_user_mode:\n\tcpsid\ti\t\t/* Disable interrupts. */\n\n\t/* Initialize BASEPRI register to spl0; no interrupt masking. */\n\tmovs\tr0, #0\t\t/* Turn BASEPRI off; mask nothing. */\n\tmsr\tBASEPRI, r0\n\n\t/* Switch SPSEL to Process Stack Pointer (PSP) for user space. */\n\tldr\tr0, =__user_data_end\n\tmsr\tPSP, r0\t\t/* PSP is the user space stack pointer. */\n\tisb\t\t\t/* Just to be safe. */\n\n\t/* nPRIV -> 1 sets unprivileged Thread Mode for user space. */\n\tmrs\tr0, CONTROL\n\torrs\tr0, r0, #0x1\t/* CONTROL[0] -> 1 sets unprivileged level. */\n\torrs\tr0, r0, #0x2\t/* CONTROL[1] -> 1 sets PSP as active. */\n\n\tcpsie\ti\t\t/* Enable interrupts. */\n\n\tmsr\tCONTROL, r0\t/* PSP is current sp; unprivileged level. */\n\tisb\t\t\t/* Just to be safe. */\n\n\t/* Run icode() in user space. */\n\tldr\tlr, =__user_data_start + 1\t/* In Thumb must set lsbit. */\n\tbx\tlr\n\t.size\tReset_Handler, . - Reset_Handler\n\n/**\n * @brief  This is the code that gets called when the processor receives an\n *         unexpected interrupt.  This simply enters an infinite loop,\n *         preserving the system state for examination by a debugger.\n * @param  None\n * @retval None\n*/\n\t.section\t.text.Default_Handler, \"ax\", %progbits\nDefault_Handler:\nInfinite_Loop:\n\tb\tInfinite_Loop\n\t.size\tDefault_Handler, . - Default_Handler\n/******************************************************************************\n*\n* The minimal vector table for a Cortex M4.  Note that the proper constructs\n* must be placed on this to ensure that it ends up at physical address\n* 0x0000.0000.\n*\n*******************************************************************************/\n\t.section\t.isr_vector, \"a\", %progbits\n\t.type\tg_pfnVectors, %object\n\t.size\tg_pfnVectors, . - g_pfnVectors\n\ng_pfnVectors:\n\t.word\t_estack\n\t.word\tReset_Handler\n\t.word\tNMI_Handler\n\t.word\tHardFault_Handler\n\t.word\tMemManage_Handler\n\t.word\tBusFault_Handler\n\t.word\tUsageFault_Handler\n\t.word\t0\n\t.word\t0\n\t.word\t0\n\t.word\t0\n\t.word\tSVC_Handler\n\t.word\tDebugMon_Handler\n\t.word\t0\n\t.word\tPendSV_Handler\n\t.word\tSysTick_Handler\n\n\t/* External Interrupts */\n\t.word\tWWDG_IRQHandler\t\t\t/* Window WatchDog\t*/\n\t.word\tPVD_IRQHandler\t\t\t/* PVD through EXTI Line detection\t\t*/\n\t.word\tTAMP_STAMP_IRQHandler\t\t/* Tamper and TimeStamps through the EXTI line\t*/\n\t.word\tRTC_WKUP_IRQHandler\t\t/* RTC Wakeup through the EXTI line\t\t*/\n\t.word\tFLASH_IRQHandler\t\t/* FLASH\t\t*/\n\t.word\tRCC_IRQHandler\t\t\t/* RCC\t\t\t*/\n\t.word\tEXTI0_IRQHandler\t\t/* EXTI Line0\t\t*/\n\t.word\tEXTI1_IRQHandler\t\t/* EXTI Line1\t\t*/\n\t.word\tEXTI2_IRQHandler\t\t/* EXTI Line2\t\t*/\n\t.word\tEXTI3_IRQHandler\t\t/* EXTI Line3\t\t*/\n\t.word\tEXTI4_IRQHandler\t\t/* EXTI Line4\t\t*/\n\t.word\tDMA1_Stream0_IRQHandler\t\t/* DMA1 Stream 0\t*/\n\t.word\tDMA1_Stream1_IRQHandler\t\t/* DMA1 Stream 1\t*/\n\t.word\tDMA1_Stream2_IRQHandler\t\t/* DMA1 Stream 2\t*/\n\t.word\tDMA1_Stream3_IRQHandler\t\t/* DMA1 Stream 3\t*/\n\t.word\tDMA1_Stream4_IRQHandler\t\t/* DMA1 Stream 4\t*/\n\t.word\tDMA1_Stream5_IRQHandler\t\t/* DMA1 Stream 5\t*/\n\t.word\tDMA1_Stream6_IRQHandler\t\t/* DMA1 Stream 6\t*/\n\t.word\tADC_IRQHandler\t\t\t/* ADC1, ADC2 and ADC3s\t*/\n\t.word\tCAN1_TX_IRQHandler\t\t/* CAN1 TX\t\t*/\n\t.word\tCAN1_RX0_IRQHandler\t\t/* CAN1 RX0\t\t*/\n\t.word\tCAN1_RX1_IRQHandler\t\t/* CAN1 RX1\t\t*/\n\t.word\tCAN1_SCE_IRQHandler\t\t/* CAN1 SCE\t\t*/\n\t.word\tEXTI9_5_IRQHandler\t\t/* External Line[9:5]s\t*/\n\t.word\tTIM1_BRK_TIM9_IRQHandler\t/* TIM1 Break and TIM9\t*/\n\t.word\tTIM1_UP_TIM10_IRQHandler\t/* TIM1 Update and TIM10\t\t\t*/\n\t.word\tTIM1_TRG_COM_TIM11_IRQHandler\t/* TIM1 Trigger and Commutation and TIM11\t*/\n\t.word\tTIM1_CC_IRQHandler\t\t/* TIM1 Capture Compare\t*/\n\t.word\tTIM2_IRQHandler\t\t\t/* TIM2\t\t\t*/\n\t.word\tTIM3_IRQHandler\t\t\t/* TIM3\t\t\t*/\n\t.word\tTIM4_IRQHandler\t\t\t/* TIM4\t\t\t*/\n\t.word\tI2C1_EV_IRQHandler\t\t/* I2C1 Event\t\t*/\n\t.word\tI2C1_ER_IRQHandler\t\t/* I2C1 Error\t\t*/\n\t.word\tI2C2_EV_IRQHandler\t\t/* I2C2 Event\t\t*/\n\t.word\tI2C2_ER_IRQHandler\t\t/* I2C2 Error\t\t*/\n\t.word\tSPI1_IRQHandler\t\t\t/* SPI1\t\t\t*/\n\t.word\tSPI2_IRQHandler\t\t\t/* SPI2\t\t\t*/\n\t.word\tUSART1_IRQHandler\t\t/* USART1\t\t*/\n\t.word\tUSART2_IRQHandler\t\t/* USART2\t\t*/\n\t.word\tUSART3_IRQHandler\t\t/* USART3\t\t*/\n\t.word\tEXTI15_10_IRQHandler\t\t/* External Line[15:10]s\t\t\t*/\n\t.word\tRTC_Alarm_IRQHandler\t\t/* RTC Alarm (A and B) through EXTI Line\t*/\n\t.word\tOTG_FS_WKUP_IRQHandler\t\t/* USB OTG FS Wakeup through EXTI line\t\t*/\n\t.word\tTIM8_BRK_TIM12_IRQHandler\t/* TIM8 Break and TIM12\t*/\n\t.word\tTIM8_UP_TIM13_IRQHandler\t/* TIM8 Update and TIM13\t\t\t*/\n\t.word\tTIM8_TRG_COM_TIM14_IRQHandler\t/* TIM8 Trigger and Commutation and TIM14\t*/\n\t.word\tTIM8_CC_IRQHandler\t\t/* TIM8 Capture Compare\t*/\n\t.word\tDMA1_Stream7_IRQHandler\t\t/* DMA1 Stream7\t\t*/\n\t.word\tFSMC_IRQHandler\t\t\t/* FSMC\t\t\t*/\n\t.word\tSDIO_IRQHandler\t\t\t/* SDIO\t\t\t*/\n\t.word\tTIM5_IRQHandler\t\t\t/* TIM5\t\t\t*/\n\t.word\tSPI3_IRQHandler\t\t\t/* SPI3\t\t\t*/\n\t.word\tUART4_IRQHandler\t\t/* UART4\t\t*/\n\t.word\tUART5_IRQHandler\t\t/* UART5\t\t*/\n\t.word\tTIM6_DAC_IRQHandler\t\t/* TIM6 and DAC1&2 underrun errors\t\t*/\n\t.word\tTIM7_IRQHandler\t\t\t/* TIM7\t\t\t*/\n\t.word\tDMA2_Stream0_IRQHandler\t\t/* DMA2 Stream 0\t*/\n\t.word\tDMA2_Stream1_IRQHandler\t\t/* DMA2 Stream 1\t*/\n\t.word\tDMA2_Stream2_IRQHandler\t\t/* DMA2 Stream 2\t*/\n\t.word\tDMA2_Stream3_IRQHandler\t\t/* DMA2 Stream 3\t*/\n\t.word\tDMA2_Stream4_IRQHandler\t\t/* DMA2 Stream 4\t*/\n\t.word\tETH_IRQHandler\t\t\t/* Ethernet\t\t*/\n\t.word\tETH_WKUP_IRQHandler\t\t/* Ethernet Wakeup through EXTI line\t\t*/\n\t.word\tCAN2_TX_IRQHandler\t\t/* CAN2 TX\t\t*/\n\t.word\tCAN2_RX0_IRQHandler\t\t/* CAN2 RX0\t\t*/\n\t.word\tCAN2_RX1_IRQHandler\t\t/* CAN2 RX1\t\t*/\n\t.word\tCAN2_SCE_IRQHandler\t\t/* CAN2 SCE\t\t*/\n\t.word\tOTG_FS_IRQHandler\t\t/* USB OTG FS\t\t*/\n\t.word\tDMA2_Stream5_IRQHandler\t\t/* DMA2 Stream 5\t*/\n\t.word\tDMA2_Stream6_IRQHandler\t\t/* DMA2 Stream 6\t*/\n\t.word\tDMA2_Stream7_IRQHandler\t\t/* DMA2 Stream 7\t*/\n\t.word\tUSART6_IRQHandler\t\t/* USART6\t\t*/\n\t.word\tI2C3_EV_IRQHandler\t\t/* I2C3 event\t\t*/\n\t.word\tI2C3_ER_IRQHandler\t\t/* I2C3 error\t\t*/\n\t.word\tOTG_HS_EP1_OUT_IRQHandler\t/* USB OTG HS End Point 1 Out\t\t\t*/\n\t.word\tOTG_HS_EP1_IN_IRQHandler\t/* USB OTG HS End Point 1 In\t\t\t*/\n\t.word\tOTG_HS_WKUP_IRQHandler\t\t/* USB OTG HS Wakeup through EXTI\t\t*/\n\t.word\tOTG_HS_IRQHandler\t\t/* USB OTG HS\t\t*/\n\t.word\tDCMI_IRQHandler\t\t\t/* DCMI\t\t\t*/\n\t.word\t0\t\t\t\t/* CRYP crypto\t\t*/\n\t.word\tHASH_RNG_IRQHandler\t\t/* Hash and Rng\t\t*/\n\t.word\tFPU_IRQHandler\t\t\t/* FPU\t\t\t*/\n\n\n/*******************************************************************************\n*\n* Provide weak aliases for each Exception handler to the Default_Handler.\n* As they are weak aliases, any function with the same name will override\n* this definition.\n*\n*******************************************************************************/\n\t.weak\t\tNMI_Handler\n\t.thumb_set\tNMI_Handler,Default_Handler\n\n\t.weak\t\tHardFault_Handler\n\t.thumb_set\tHardFault_Handler,Default_Handler\n\n\t.weak\t\tMemManage_Handler\n\t.thumb_set\tMemManage_Handler,Default_Handler\n\n\t.weak\t\tBusFault_Handler\n\t.thumb_set\tBusFault_Handler,Default_Handler\n\n\t.weak\t\tUsageFault_Handler\n\t.thumb_set\tUsageFault_Handler,Default_Handler\n\n\t.weak\t\tSVC_Handler\n\t.thumb_set\tSVC_Handler,Default_Handler\n\n\t.weak\t\tDebugMon_Handler\n\t.thumb_set\tDebugMon_Handler,Default_Handler\n\n\t.weak\t\tPendSV_Handler\n\t.thumb_set\tPendSV_Handler,Default_Handler\n\n\t.weak\t\tSysTick_Handler\n\t.thumb_set\tSysTick_Handler,Default_Handler\n\n\t.weak\t\tWWDG_IRQHandler\n\t.thumb_set\tWWDG_IRQHandler,Default_Handler\n\n\t.weak\t\tPVD_IRQHandler\n\t.thumb_set\tPVD_IRQHandler,Default_Handler\n\n\t.weak\t\tTAMP_STAMP_IRQHandler\n\t.thumb_set\tTAMP_STAMP_IRQHandler,Default_Handler\n\n\t.weak\t\tRTC_WKUP_IRQHandler\n\t.thumb_set\tRTC_WKUP_IRQHandler,Default_Handler\n\n\t.weak\t\tFLASH_IRQHandler\n\t.thumb_set\tFLASH_IRQHandler,Default_Handler\n\n\t.weak\t\tRCC_IRQHandler\n\t.thumb_set\tRCC_IRQHandler,Default_Handler\n\n\t.weak\t\tEXTI0_IRQHandler\n\t.thumb_set\tEXTI0_IRQHandler,Default_Handler\n\n\t.weak\t\tEXTI1_IRQHandler\n\t.thumb_set\tEXTI1_IRQHandler,Default_Handler\n\n\t.weak\t\tEXTI2_IRQHandler\n\t.thumb_set\tEXTI2_IRQHandler,Default_Handler\n\n\t.weak\t\tEXTI3_IRQHandler\n\t.thumb_set\tEXTI3_IRQHandler,Default_Handler\n\n\t.weak\t\tEXTI4_IRQHandler\n\t.thumb_set\tEXTI4_IRQHandler,Default_Handler\n\n\t.weak\t\tDMA1_Stream0_IRQHandler\n\t.thumb_set\tDMA1_Stream0_IRQHandler,Default_Handler\n\n\t.weak\t\tDMA1_Stream1_IRQHandler\n\t.thumb_set\tDMA1_Stream1_IRQHandler,Default_Handler\n\n\t.weak\t\tDMA1_Stream2_IRQHandler\n\t.thumb_set\tDMA1_Stream2_IRQHandler,Default_Handler\n\n\t.weak\t\tDMA1_Stream3_IRQHandler\n\t.thumb_set\tDMA1_Stream3_IRQHandler,Default_Handler\n\n\t.weak\t\tDMA1_Stream4_IRQHandler\n\t.thumb_set\tDMA1_Stream4_IRQHandler,Default_Handler\n\n\t.weak\t\tDMA1_Stream5_IRQHandler\n\t.thumb_set\tDMA1_Stream5_IRQHandler,Default_Handler\n\n\t.weak\t\tDMA1_Stream6_IRQHandler\n\t.thumb_set\tDMA1_Stream6_IRQHandler,Default_Handler\n\n\t.weak\t\tADC_IRQHandler\n\t.thumb_set\tADC_IRQHandler,Default_Handler\n\n\t.weak\t\tCAN1_TX_IRQHandler\n\t.thumb_set\tCAN1_TX_IRQHandler,Default_Handler\n\n\t.weak\t\tCAN1_RX0_IRQHandler\n\t.thumb_set\tCAN1_RX0_IRQHandler,Default_Handler\n\n\t.weak\t\tCAN1_RX1_IRQHandler\n\t.thumb_set\tCAN1_RX1_IRQHandler,Default_Handler\n\n\t.weak\t\tCAN1_SCE_IRQHandler\n\t.thumb_set\tCAN1_SCE_IRQHandler,Default_Handler\n\n\t.weak\t\tEXTI9_5_IRQHandler\n\t.thumb_set\tEXTI9_5_IRQHandler,Default_Handler\n\n\t.weak\t\tTIM1_BRK_TIM9_IRQHandler\n\t.thumb_set\tTIM1_BRK_TIM9_IRQHandler,Default_Handler\n\n\t.weak\t\tTIM1_UP_TIM10_IRQHandler\n\t.thumb_set\tTIM1_UP_TIM10_IRQHandler,Default_Handler\n\n\t.weak\t\tTIM1_TRG_COM_TIM11_IRQHandler\n\t.thumb_set\tTIM1_TRG_COM_TIM11_IRQHandler,Default_Handler\n\n\t.weak\t\tTIM1_CC_IRQHandler\n\t.thumb_set\tTIM1_CC_IRQHandler,Default_Handler\n\n\t.weak\t\tTIM2_IRQHandler\n\t.thumb_set\tTIM2_IRQHandler,Default_Handler\n\n\t.weak\t\tTIM3_IRQHandler\n\t.thumb_set\tTIM3_IRQHandler,Default_Handler\n\n\t.weak\t\tTIM4_IRQHandler\n\t.thumb_set\tTIM4_IRQHandler,Default_Handler\n\n\t.weak\t\tI2C1_EV_IRQHandler\n\t.thumb_set\tI2C1_EV_IRQHandler,Default_Handler\n\n\t.weak\t\tI2C1_ER_IRQHandler\n\t.thumb_set\tI2C1_ER_IRQHandler,Default_Handler\n\n\t.weak\t\tI2C2_EV_IRQHandler\n\t.thumb_set\tI2C2_EV_IRQHandler,Default_Handler\n\n\t.weak\t\tI2C2_ER_IRQHandler\n\t.thumb_set\tI2C2_ER_IRQHandler,Default_Handler\n\n\t.weak\t\tSPI1_IRQHandler\n\t.thumb_set\tSPI1_IRQHandler,Default_Handler\n\n\t.weak\t\tSPI2_IRQHandler\n\t.thumb_set\tSPI2_IRQHandler,Default_Handler\n\n\t.weak\t\tUSART1_IRQHandler\n\t.thumb_set\tUSART1_IRQHandler,Default_Handler\n\n\t.weak\t\tUSART2_IRQHandler\n\t.thumb_set\tUSART2_IRQHandler,Default_Handler\n\n\t.weak\t\tUSART3_IRQHandler\n\t.thumb_set\tUSART3_IRQHandler,Default_Handler\n\n\t.weak\t\tEXTI15_10_IRQHandler\n\t.thumb_set\tEXTI15_10_IRQHandler,Default_Handler\n\n\t.weak\t\tRTC_Alarm_IRQHandler\n\t.thumb_set\tRTC_Alarm_IRQHandler,Default_Handler\n\n\t.weak\t\tOTG_FS_WKUP_IRQHandler\n\t.thumb_set\tOTG_FS_WKUP_IRQHandler,Default_Handler\n\n\t.weak\t\tTIM8_BRK_TIM12_IRQHandler\n\t.thumb_set\tTIM8_BRK_TIM12_IRQHandler,Default_Handler\n\n\t.weak\t\tTIM8_UP_TIM13_IRQHandler\n\t.thumb_set\tTIM8_UP_TIM13_IRQHandler,Default_Handler\n\n\t.weak\t\tTIM8_TRG_COM_TIM14_IRQHandler\n\t.thumb_set\tTIM8_TRG_COM_TIM14_IRQHandler,Default_Handler\n\n\t.weak\t\tTIM8_CC_IRQHandler\n\t.thumb_set\tTIM8_CC_IRQHandler,Default_Handler\n\n\t.weak\t\tDMA1_Stream7_IRQHandler\n\t.thumb_set\tDMA1_Stream7_IRQHandler,Default_Handler\n\n\t.weak\t\tFSMC_IRQHandler\n\t.thumb_set\tFSMC_IRQHandler,Default_Handler\n\n\t.weak\t\tSDIO_IRQHandler\n\t.thumb_set\tSDIO_IRQHandler,Default_Handler\n\n\t.weak\t\tTIM5_IRQHandler\n\t.thumb_set\tTIM5_IRQHandler,Default_Handler\n\n\t.weak\t\tSPI3_IRQHandler\n\t.thumb_set\tSPI3_IRQHandler,Default_Handler\n\n\t.weak\t\tUART4_IRQHandler\n\t.thumb_set\tUART4_IRQHandler,Default_Handler\n\n\t.weak\t\tUART5_IRQHandler\n\t.thumb_set\tUART5_IRQHandler,Default_Handler\n\n\t.weak\t\tTIM6_DAC_IRQHandler\n\t.thumb_set\tTIM6_DAC_IRQHandler,Default_Handler\n\n\t.weak\t\tTIM7_IRQHandler\n\t.thumb_set\tTIM7_IRQHandler,Default_Handler\n\n\t.weak\t\tDMA2_Stream0_IRQHandler\n\t.thumb_set\tDMA2_Stream0_IRQHandler,Default_Handler\n\n\t.weak\t\tDMA2_Stream1_IRQHandler\n\t.thumb_set\tDMA2_Stream1_IRQHandler,Default_Handler\n\n\t.weak\t\tDMA2_Stream2_IRQHandler\n\t.thumb_set\tDMA2_Stream2_IRQHandler,Default_Handler\n\n\t.weak\t\tDMA2_Stream3_IRQHandler\n\t.thumb_set\tDMA2_Stream3_IRQHandler,Default_Handler\n\n\t.weak\t\tDMA2_Stream4_IRQHandler\n\t.thumb_set\tDMA2_Stream4_IRQHandler,Default_Handler\n\n\t.weak\t\tETH_IRQHandler\n\t.thumb_set\tETH_IRQHandler,Default_Handler\n\n\t.weak\t\tETH_WKUP_IRQHandler\n\t.thumb_set\tETH_WKUP_IRQHandler,Default_Handler\n\n\t.weak\t\tCAN2_TX_IRQHandler\n\t.thumb_set\tCAN2_TX_IRQHandler,Default_Handler\n\n\t.weak\t\tCAN2_RX0_IRQHandler\n\t.thumb_set\tCAN2_RX0_IRQHandler,Default_Handler\n\n\t.weak\t\tCAN2_RX1_IRQHandler\n\t.thumb_set\tCAN2_RX1_IRQHandler,Default_Handler\n\n\t.weak\t\tCAN2_SCE_IRQHandler\n\t.thumb_set\tCAN2_SCE_IRQHandler,Default_Handler\n\n\t.weak\t\tOTG_FS_IRQHandler\n\t.thumb_set\tOTG_FS_IRQHandler,Default_Handler\n\n\t.weak\t\tDMA2_Stream5_IRQHandler\n\t.thumb_set\tDMA2_Stream5_IRQHandler,Default_Handler\n\n\t.weak\t\tDMA2_Stream6_IRQHandler\n\t.thumb_set\tDMA2_Stream6_IRQHandler,Default_Handler\n\n\t.weak\t\tDMA2_Stream7_IRQHandler\n\t.thumb_set\tDMA2_Stream7_IRQHandler,Default_Handler\n\n\t.weak\t\tUSART6_IRQHandler\n\t.thumb_set\tUSART6_IRQHandler,Default_Handler\n\n\t.weak\t\tI2C3_EV_IRQHandler\n\t.thumb_set\tI2C3_EV_IRQHandler,Default_Handler\n\n\t.weak\t\tI2C3_ER_IRQHandler\n\t.thumb_set\tI2C3_ER_IRQHandler,Default_Handler\n\n\t.weak\t\tOTG_HS_EP1_OUT_IRQHandler\n\t.thumb_set\tOTG_HS_EP1_OUT_IRQHandler,Default_Handler\n\n\t.weak\t\tOTG_HS_EP1_IN_IRQHandler\n\t.thumb_set\tOTG_HS_EP1_IN_IRQHandler,Default_Handler\n\n\t.weak\t\tOTG_HS_WKUP_IRQHandler\n\t.thumb_set\tOTG_HS_WKUP_IRQHandler,Default_Handler\n\n\t.weak\t\tOTG_HS_IRQHandler\n\t.thumb_set\tOTG_HS_IRQHandler,Default_Handler\n\n\t.weak\t\tDCMI_IRQHandler\n\t.thumb_set\tDCMI_IRQHandler,Default_Handler\n\n\t.weak\t\tHASH_RNG_IRQHandler\n\t.thumb_set\tHASH_RNG_IRQHandler,Default_Handler\n\n\t.weak\t\tFPU_IRQHandler\n\t.thumb_set\tFPU_IRQHandler,Default_Handler\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "sys/arch/stm32/stm32/machdep.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)machdep.c\t2.4 (2.11BSD) 1999/9/13\n */\n\n#include <sys/param.h>\n#include <sys/dir.h>\n#include <sys/inode.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/fs.h>\n#include <sys/map.h>\n#include <sys/buf.h>\n#include <sys/file.h>\n#include <sys/clist.h>\n#include <sys/callout.h>\n#include <sys/reboot.h>\n#include <sys/msgbuf.h>\n#include <sys/namei.h>\n#include <sys/mount.h>\n#include <sys/systm.h>\n#include <sys/config.h>\n#include <sys/tty.h>\n\n#include <machine/fault.h>\n\n#include <stm32/dev/uart.h>\n#include <stm32/dev/stm32_bsp.h>\n\n#include <stm32/hal/stm32f4xx_ll_bus.h>\n#include <stm32/hal/stm32f4xx_ll_gpio.h>\n#include <stm32/hal/stm32f4xx_ll_pwr.h>\n#include <stm32/hal/stm32f4xx_ll_rcc.h>\n#include <stm32/hal/stm32f4xx_ll_system.h>\n#include <stm32/hal/stm32f4xx_ll_utils.h>\n#include <stm32/hal/stm32f4xx_hal.h>\n\n/*\n * Kernel-specific uses of LEDs and buttons provided by the\n * board support package and defined in the kernel Config.\n * LED activity indicators: TTY, SWAP, DISK, KERNEL\n * User Button: Enter single user mode when pressed during boot.\n */\n#if defined(BSP) && defined(BSP_LED_TTY)\n#define LED_TTY_INIT()\t\tBSP_LED_Init(BSP_LED_TTY)\n#define LED_TTY_ON()\t\tBSP_LED_On(BSP_LED_TTY)\n#define LED_TTY_OFF()\t\tBSP_LED_Off(BSP_LED_TTY)\n#else\n#define LED_TTY_INIT()\t\t/* Nothing. */\n#define LED_TTY_ON()\t\t/* Nothing. */\n#define LED_TTY_OFF()\t\t/* Nothing. */\n#endif\n\n#if defined(BSP) && defined(BSP_LED_SWAP)\n#define LED_SWAP_INIT()\t\tBSP_LED_Init(BSP_LED_SWAP)\n#define LED_SWAP_ON()\t\tBSP_LED_On(BSP_LED_SWAP)\n#define LED_SWAP_OFF()\t\tBSP_LED_Off(BSP_LED_SWAP)\n#else\n#define LED_SWAP_INIT()\t\t/* Nothing. */\n#define LED_SWAP_ON()\t\t/* Nothing. */\n#define LED_SWAP_OFF()\t\t/* Nothing. */\n#endif\n\n#if defined(BSP) && defined(BSP_LED_DISK)\n#define LED_DISK_INIT()\t\tBSP_LED_Init(BSP_LED_DISK)\n#define LED_DISK_ON()\t\tBSP_LED_On(BSP_LED_DISK)\n#define LED_DISK_OFF()\t\tBSP_LED_Off(BSP_LED_DISK)\n#else\n#define LED_DISK_INIT()\t\t/* Nothing. */\n#define LED_DISK_ON()\t\t/* Nothing. */\n#define LED_DISK_OFF()\t\t/* Nothing. */\n#endif\n\n#if defined(BSP) && defined(BSP_LED_KERNEL)\n#define LED_KERNEL_INIT()\tBSP_LED_Init(BSP_LED_KERNEL)\n#define LED_KERNEL_ON()\t\tBSP_LED_On(BSP_LED_KERNEL)\n#define LED_KERNEL_OFF()\tBSP_LED_Off(BSP_LED_KERNEL)\n#else\n#define LED_KERNEL_INIT()\t/* Nothing. */\n#define LED_KERNEL_ON()\t\t/* Nothing. */\n#define LED_KERNEL_OFF()\t/* Nothing. */\n#endif\n\n#if defined(BSP) && defined(BSP_BUTTON_USER)\n#define BUTTON_USER_INIT()\tBSP_PB_Init(BSP_BUTTON_USER)\n#define BUTTON_USER_PRESSED()\tBSP_PB_GetState(BSP_BUTTON_USER)\n#else\n#define BUTTON_USER_INIT()\t/* Nothing. */\n#define BUTTON_USER_PRESSED()\t(0)\t/* Not pressed. */\n#endif\n\nchar\tmachine[] = MACHINE;\t\t/* from <machine/machparam.h> */\nchar\tmachine_arch[] = MACHINE_ARCH;\t/* from <machine/machparam.h> */\nchar\tcpu_model[64];\n\nint\thz = HZ;\nint\tusechz = (1000000L + HZ - 1) / HZ;\n\n#ifdef TIMEZONE\nstruct timezone\t\ttz = { TIMEZONE, DST };\n#else\nstruct timezone\t\ttz = { 8 * 60, 1 };\n#endif\n\nint\t\t\tnproc = NPROC;\n\nstruct namecache\tnamecache[NNAMECACHE];\nchar\t\t\tbufdata[NBUF * MAXBSIZE];\nstruct inode\t\tinode[NINODE];\nstruct callout\t\tcallout[NCALL];\nstruct mount\t\tmount[NMOUNT];\nstruct buf\t\tbuf[NBUF], bfreelist[BQUEUES];\nstruct bufhd\t\tbufhash[BUFHSZ];\nstruct cblock\t\tcfree[NCLIST];\nstruct proc\t\tproc[NPROC];\nstruct file\t\tfile[NFILE];\n\n/*\n * Remove the ifdef/endif to run the kernel in unsecure mode even when in\n * a multiuser state.  Normally 'init' raises the security level to 1\n * upon transitioning to multiuser.  Setting the securelevel to -1 prevents\n * the secure level from being raised by init.\n */\n#ifdef PERMANENTLY_INSECURE\nint\tsecurelevel = -1;\n#else\nint\tsecurelevel = 0;\n#endif\n\nstruct mapent\tswapent[SMAPSIZ];\nstruct map\tswapmap[1] = {\n\t{ swapent,\n\t  &swapent[SMAPSIZ],\n\t  \"swapmap\" },\n};\n\nint\twaittime = -1;\n\nstatic int\nnodump(dev_t dev)\n{\n\tprintf(\"\\ndumping to dev %o off %D: not implemented\\n\",\n\t    dumpdev, dumplo);\n\n\treturn 0;\n}\n\nint (*dump)(dev_t) = nodump;\n\ndev_t\tpipedev;\ndaddr_t\tdumplo = (daddr_t)1024;\n\nstatic void\nSystemClock_Config(void)\n{\n\t/* Enable HSE oscillator. */\n#if defined(STM32F411xE) || defined(STM32F413xx)\n\tLL_RCC_HSE_EnableBypass();\n#endif\n\n\tLL_RCC_HSE_Enable();\n\twhile (LL_RCC_HSE_IsReady() != 1)\n\t\t;\n\n\t/* Set FLASH latency. */\n#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F446xx) || \\\n    defined(STM32F469xx)\n\tLL_FLASH_SetLatency(LL_FLASH_LATENCY_5);\n#endif\n#if defined(STM32F411xE) || defined(STM32F412Rx) || defined(STM32F412Zx) || \\\n    defined(STM32F413xx)\n\tLL_FLASH_SetLatency(LL_FLASH_LATENCY_3);\n#endif\n\n\t/* Enable PWR clock. */\n\tLL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);\n\n\tLL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);\n\n#if defined(STM32F446xx) || defined(STM32F469xx)\n\t/* Activation OverDrive Mode. */\n\tLL_PWR_EnableOverDriveMode();\n\twhile (LL_PWR_IsActiveFlag_OD() != 1)\n\t\t;\n\n\t/* Activation OverDrive Switching. */\n\tLL_PWR_EnableOverDriveSwitching();\n\twhile (LL_PWR_IsActiveFlag_ODSW() != 1)\n\t\t;\n#endif\n\n\t/* Main PLL configuration and activation. */\n#ifdef STM32F405xx\t/* 168 MHz */\n\tLL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE,\n\t    LL_RCC_PLLM_DIV_8, 336, LL_RCC_PLLP_DIV_2);\n#endif\n#ifdef STM32F407xx\t/* 168 MHz */\n\tLL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE,\n\t    LL_RCC_PLLM_DIV_8, 336, LL_RCC_PLLP_DIV_2);\n#endif\n#ifdef STM32F411xE\t/* 100 MHz */\n\tLL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE,\n\t    LL_RCC_PLLM_DIV_8, 400, LL_RCC_PLLP_DIV_4);\n#endif\n#ifdef STM32F412Rx\t/* 100 MHz */\n\tLL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE,\n\t    LL_RCC_PLLM_DIV_8, 200, LL_RCC_PLLP_DIV_2);\n#endif\n#ifdef STM32F412Zx\t/* 100 MHz */\n\tLL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE,\n\t    LL_RCC_PLLM_DIV_8, 200, LL_RCC_PLLP_DIV_2);\n#endif\n#ifdef STM32F413xx\t/* 100 MHz */\n\tLL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE,\n\t    LL_RCC_PLLM_DIV_8, 200, LL_RCC_PLLP_DIV_2);\n#endif\n#ifdef STM32F446xx\t/* 180 MHz */\n\tLL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE,\n\t    LL_RCC_PLLM_DIV_8, 360, LL_RCC_PLLP_DIV_2);\n#endif\n#ifdef STM32F469xx\t/* 180 MHz */\n\tLL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE,\n\t    LL_RCC_PLLM_DIV_8, 360, LL_RCC_PLLP_DIV_2);\n#endif\n\n\tLL_RCC_PLL_Enable();\n\twhile (LL_RCC_PLL_IsReady() != 1)\n\t\t;\n\n\t/* SysClk activation on the main PLL. */\n\tLL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);\n\tLL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);\n\twhile (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)\n\t\t;\n\n\t/* Set APB1 & APB2 prescaler. */\n#ifdef STM32F405xx\t/* 168 MHz */\n\tLL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_4);\n\tLL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2);\n#endif\n#ifdef STM32F407xx\t/* 168 MHz */\n\tLL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_4);\n\tLL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2);\n#endif\n#ifdef STM32F411xE\t/* 100 MHz */\n\tLL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);\n\tLL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);\n#endif\n#ifdef STM32F412Rx\t/* 100 MHz */\n\tLL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);\n\tLL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2);\n#endif\n#ifdef STM32F412Zx\t/* 100 MHz */\n\tLL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);\n\tLL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);\n#endif\n#ifdef STM32F413xx\t/* 100 MHz */\n\tLL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);\n\tLL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);\n#endif\n#ifdef STM32F446xx\t/* 180 MHz */\n\tLL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);\n\tLL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2);\n#endif\n#ifdef STM32F469xx\t/* 180 MHz */\n\tLL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);\n\tLL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2);\n#endif\n\n\t/* Set SysTick to 1ms. */\n\tSysTick_Config(CPU_KHZ);\n\n\t/* Update CMSIS variable (or through SystemCoreClockUpdate()). */\n\tSystemCoreClock = CPU_KHZ * 1000;\n}\n\n/*\n * Machine dependent startup code.\n */\nvoid\nstartup(void)\n{\n\tHAL_Init();\n\n\tSystemClock_Config();\n\n\t/* Enable all configurable fault handlers. */\n\tarm_enable_fault(MM_FAULT_ENABLE);\n\tarm_enable_fault(BF_FAULT_ENABLE);\n\tarm_enable_fault(UF_FAULT_ENABLE);\n\n\t/* Syscalls (via PendSV) have the lowest interrupt priority. */\n\tarm_intr_set_priority(PendSV_IRQn, IPL_PENDSV);\n\n\t/* SVCall exceptions have the highest interrupt priority. */\n\tarm_intr_set_priority(SVCall_IRQn, IPL_SVCALL);\n\n\t/* SysTick exceptions have the interrupt priority of IPL_CLOCK. */\n\tarm_intr_set_priority(SysTick_IRQn, IPL_SYSTICK);\n\n\t/*\n\t * Configure LED pins.\n\t */\n\tLED_TTY_INIT();\t\t\t/* Green.   Terminal i/o */\n\tLED_SWAP_INIT();\t\t/* Orange.  Auxiliary swap */\n\tLED_DISK_INIT();\t\t/* Red.\t    Disk i/o */\n\tLED_KERNEL_INIT();\t\t/* Blue.    Kernel activity */\n\n\tLED_TTY_ON();\n\tLED_SWAP_ON();\n\tLED_DISK_ON();\n\tLED_KERNEL_ON();\n\n\tLED_TTY_OFF();\n\tLED_SWAP_OFF();\n\tLED_DISK_OFF();\n\tLED_KERNEL_OFF();\n\n\tled_control(LED_ALL, 1);\n\tled_control(LED_ALL, 0);\n\n\t/*\n\t * Configure User Button.\n\t */\n\tBUTTON_USER_INIT();\n\n\t/*\n\t * Early setup for console devices.\n\t */\n#if CONS_MAJOR == UART_MAJOR\n\tuartinit(CONS_MINOR);\n#endif\n\n\t/*\n\t * When User button is pressed - boot to single user mode.\n\t */\n\tboothowto = 0;\n\tif (BUTTON_USER_PRESSED()) {\n\t\tboothowto |= RB_SINGLE;\n\t}\n}\n\nstatic void\ncpuidentify(void)\n{\n\tu_int devid = LL_DBGMCU_GetDeviceID();\n\tu_int revid = LL_DBGMCU_GetRevisionID();\n\n\tprintf(\"cpu: \");\n\tswitch (devid) {\n\t/*\n\t * Device errata 2.2.2: MCU device ID is incorrect.\n\t *\n\t * Revision A STM32F40x and STM32F41x devices have the same\n\t * MCU device ID as the STM32F20x and STM32F21x devices.\n\t * Reading the revision identifier returns 0x2000 instead of 0x1000.\n\t */\n\tcase 0x0411:\n\t\tphysmem = 192 * 1024;\t\t/* Total 192kb RAM size. */\n\t\tcopystr(\"STM32F405/407xx\", cpu_model, sizeof(cpu_model), NULL);\n\t\tprintf(\"STM32F405/407xx\");\n\t\tprintf(\" rev \");\n\t\tswitch (revid) {\n\t\tcase 0x2000:\n\t\t\tprintf(\"A\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprintf(\"unknown 0x%04x\", revid);\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase 0x0413:\n\t\tphysmem = 192 * 1024;\t\t/* Total 192kb RAM size. */\n\t\tcopystr(\"STM32F405/407xx\", cpu_model, sizeof(cpu_model), NULL);\n\t\tprintf(\"STM32F405/407xx\");\n\t\tprintf(\" rev \");\n\t\tswitch (revid) {\n\t\tcase 0x1000:\n\t\t\tprintf(\"A\");\n\t\t\tbreak;\n\t\tcase 0x1001:\n\t\t\tprintf(\"Z\");\n\t\t\tbreak;\n\t\tcase 0x1003:\n\t\t\tprintf(\"1\");\n\t\t\tbreak;\n\t\tcase 0x1007:\n\t\t\tprintf(\"2\");\n\t\t\tbreak;\n\t\tcase 0x100f:\n\t\t\t/* Device marking revisions 4 and Y. */\n\t\t\tprintf(\"4/Y\");\n\t\t\tbreak;\n\t\tcase 0x101f:\n\t\t\t/* Device marking revisions 5 and 6. */\n\t\t\tprintf(\"5/6\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprintf(\"unknown 0x%04x\", revid);\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase 0x0421:\n\t\tphysmem = 128 * 1024;\t\t/* Total 128kb RAM size. */\n\t\tcopystr(\"STM32F446xx\", cpu_model, sizeof(cpu_model), NULL);\n\t\tprintf(\"STM32F446xx\");\n\t\tprintf(\" rev \");\n\t\tswitch (revid) {\n\t\tcase 0x1000:\n\t\t\t/* Device marking revisions 1 and A. */\n\t\t\tprintf(\"1/A\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprintf(\"unknown 0x%04x\", revid);\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase 0x0431:\n\t\tphysmem = 128 * 1024;\t\t/* Total 128kb RAM size. */\n\t\tcopystr(\"STM32F411xC/E\", cpu_model, sizeof(cpu_model), NULL);\n\t\tprintf(\"STM32F411xC/E\");\n\t\tprintf(\" rev \");\n\t\tswitch (revid) {\n\t\tcase 0x1000:\n\t\t\t/* Device marking revisions 1, 2, and A. */\n\t\t\tprintf(\"1/2/A\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprintf(\"unknown 0x%04x\", revid);\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase 0x0434:\n\t\tphysmem = 384 * 1024;\t\t/* Total 384kb RAM size. */\n\t\tcopystr(\"STM32F469/479xx\", cpu_model, sizeof(cpu_model), NULL);\n\t\tprintf(\"STM32F469/479xx\");\n\t\tprintf(\" rev \");\n\t\tswitch (revid) {\n\t\tcase 0x1000:\n\t\t\t/* Device marking revisions 1 and A. */\n\t\t\tprintf(\"1/A\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprintf(\"unknown 0x%04x\", revid);\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase 0x0441:\n\t\tphysmem = 256 * 1024;\t\t/* Total 256kb RAM size. */\n\t\tcopystr(\"STM32F412xE/G\", cpu_model, sizeof(cpu_model), NULL);\n\t\tprintf(\"STM32F412xE/G\");\n\t\tprintf(\" rev \");\n\t\tswitch (revid) {\n\t\tcase 0x1001:\n\t\t\tprintf(\"Z\");\n\t\t\tbreak;\n\t\tcase 0x2000:\n\t\t\tprintf(\"B\");\n\t\t\tbreak;\n\t\tcase 0x3000:\n\t\t\t/* Device marking revisions 1 and C. */\n\t\t\tprintf(\"1/C\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprintf(\"unknown 0x%04x\", revid);\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase 0x0463:\n\t\tphysmem = 320 * 1024;\t\t/* Total 320kb RAM size. */\n\t\tcopystr(\"STM32F413xG/H\", cpu_model, sizeof(cpu_model), NULL);\n\t\tprintf(\"STM32F413xG/H\");\n\t\tprintf(\" rev \");\n\t\tswitch (revid) {\n\t\tcase 0x1000:\n\t\t\t/* Device marking revisions A and 1. */\n\t\t\tprintf(\"A/1\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprintf(\"unknown 0x%04x\", revid);\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tphysmem = 128 * 1024;\t/* Minimum of 128kb total RAM size. */\n\t\tcopystr(\"STM32 device unknown\", cpu_model, sizeof(cpu_model),\n\t\t    NULL);\n\t\tprintf(\"device unknown 0x%04x\", devid);\n\t\tprintf(\" rev unknown 0x%04x\", revid);\n\t\tbreak;\n\t}\n\tprintf(\", %u MHz, bus %u MHz\\n\", CPU_KHZ/1000, BUS_KHZ/1000);\n\n\tprintf(\"oscillator: \");\n\tswitch (LL_RCC_GetSysClkSource()) {\n\tcase LL_RCC_SYS_CLKSOURCE_STATUS_HSI:\n\t\tprintf(\"high speed internal\\n\");\n\t\tbreak;\n\tcase LL_RCC_SYS_CLKSOURCE_STATUS_HSE:\n\t\tprintf(\"high speed external\\n\");\n\t\tbreak;\n\tcase LL_RCC_SYS_CLKSOURCE_STATUS_PLL:\n\t\tprintf(\"phase-locked loop, clock source: \");\n\t\tswitch (LL_RCC_PLL_GetMainSource()) {\n\t\tcase LL_RCC_PLLSOURCE_HSI:\n\t\t\tprintf(\"high speed internal\\n\");\n\t\t\tbreak;\n\t\tcase LL_RCC_PLLSOURCE_HSE:\n\t\t\tprintf(\"high speed external\\n\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprintf(\"unknown\\n\");\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tprintf(\"unknown\\n\");\n\t\tbreak;\n\t}\n}\n\n/*\n * Check whether the controller has been successfully initialized.\n */\nstatic int\nis_controller_alive(struct driver *driver, int unit)\n{\n\tstruct conf_ctlr *ctlr;\n\n\t/* No controller - that's OK. */\n\tif (driver == 0)\n\t\treturn 1;\n\n\tfor (ctlr = conf_ctlr_init; ctlr->ctlr_driver; ctlr++) {\n\t\tif (ctlr->ctlr_driver == driver &&\n\t\t    ctlr->ctlr_unit == unit && ctlr->ctlr_alive) {\n\t\t\treturn 1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/*\n * Configure all controllers and devices as specified\n * in the kernel configuration file.\n */\nvoid\nconfig(void)\n{\n\tstruct conf_ctlr *ctlr;\n\tstruct conf_device *dev;\n\n\tcpuidentify();\n\n\t/* Probe and initialize controllers first. */\n\tfor (ctlr = conf_ctlr_init; ctlr->ctlr_driver; ctlr++) {\n\t\tif ((*ctlr->ctlr_driver->d_init)(ctlr)) {\n\t\t\tctlr->ctlr_alive = 1;\n\t\t}\n\t}\n\n\t/* Probe and initialize devices. */\n\tfor (dev = conf_device_init; dev->dev_driver; dev++) {\n\t\tif (is_controller_alive(dev->dev_cdriver, dev->dev_ctlr)) {\n\t\t\tif ((*dev->dev_driver->d_init)(dev)) {\n\t\t\t\tdev->dev_alive = 1;\n\t\t\t}\n\t\t}\n\t}\n}\n\n/*\n * Sit and wait for something to happen...\n */\nvoid\nidle(void)\n{\n\t/* Indicate that no process is running. */\n\tnoproc = 1;\n\n\t/* Set SPL low so we can be interrupted. */\n\tint x = spl0();\n\n\tled_control(LED_KERNEL, 0);\n\n\t/* Wait for something to happen. */\n\t__DSB();\n\t__ISB();\n\t__WFI();\n\n\t/* Restore previous SPL. */\n\tsplx(x);\n}\n\nvoid\nboot(dev_t dev, int howto)\n{\n\tif ((howto & RB_NOSYNC) == 0 && waittime < 0 && bfreelist[0].b_forw) {\n\t\tstruct fs *fp;\n\t\tstruct buf *bp;\n\t\tint iter, nbusy;\n\n\t\t/*\n\t\t * Force the root filesystem's superblock to be updated,\n\t\t * so the date will be as current as possible after\n\t\t * rebooting.\n\t\t */\n\t\tfp = getfs(rootdev);\n\t\tif (fp)\n\t\t\tfp->fs_fmod = 1;\n\t\twaittime = 0;\n\t\tprintf(\"syncing disks... \");\n\t\t(void)splnet();\n\t\tsync();\n\t\tfor (iter = 0; iter < 20; iter++) {\n\t\t\tnbusy = 0;\n\t\t\tfor (bp = &buf[NBUF]; --bp >= buf;)\n\t\t\t\tif (bp->b_flags & B_BUSY)\n\t\t\t\t\tnbusy++;\n\t\t\tif (nbusy == 0)\n\t\t\t\tbreak;\n\t\t\tprintf(\"%d \", nbusy);\n\t\t\tmdelay(40L * iter);\n\t\t}\n\t\tprintf(\"done\\n\");\n\t}\n\t(void)splhigh();\n\tif (!(howto & RB_HALT)) {\n\t\tif ((howto & RB_DUMP) && dumpdev != NODEV) {\n\t\t\t/*\n\t\t\t * Take a dump of memory by calling (*dump)(),\n\t\t\t * which must correspond to dumpdev.\n\t\t\t * It should dump from dumplo blocks to the end\n\t\t\t * of memory or to the end of the logical device.\n\t\t\t */\n\t\t\t(*dump)(dumpdev);\n\t\t}\n\t\t/* Restart from dev, howto. */\n\n\t\t/* Reset microcontroller. */\n\t\tNVIC_SystemReset();\n\t\t/* NOTREACHED */\n\t}\n\tprintf(\"halted\\n\");\n\n#ifdef HALTREBOOT\n\tprintf(\"press any key to reboot...\\n\");\n\tcngetc();\n\n\t/* Reset microcontroller. */\n\tNVIC_SystemReset();\n\t/* NOTREACHED */\n#endif\n\n\tprintf(\"reboot failed; spinning\\n\");\n\tfor (;;) {\n\t\t__DSB();\n\t\t__ISB();\n\t\t__WFI();\n\t}\n\t/* NOTREACHED */\n}\n\n/*\n * Millisecond delay routine.\n *\n * Uses SysTick, which must be configured to a 1ms timebase.\n * This is a busy-wait blocking delay, so be wise with use.\n */\nvoid\nmdelay(u_int msec)\n{\n\tLL_mDelay(msec);\n}\n\n/*\n * Control LEDs, installed on the board.\n */\nvoid\nled_control(int mask, int on)\n{\n\tif (mask & LED_TTY) {\t\t/* Terminal i/o */\n\t\tif (on)\n\t\t\tLED_TTY_ON();\n\t\telse\n\t\t\tLED_TTY_OFF();\n\t}\n\tif (mask & LED_SWAP) {\t\t/* Auxiliary swap */\n\t\tif (on)\n\t\t\tLED_SWAP_ON();\n\t\telse\n\t\t\tLED_SWAP_OFF();\n\t}\n\tif (mask & LED_DISK) {\t\t/* Disk i/o */\n\t\tif (on)\n\t\t\tLED_DISK_ON();\n\t\telse\n\t\t\tLED_DISK_OFF();\n\t}\n\tif (mask & LED_KERNEL) {\t/* Kernel activity */\n\t\tif (on)\n\t\t\tLED_KERNEL_ON();\n\t\telse\n\t\t\tLED_KERNEL_OFF();\n\t}\n}\n\n/*\n * Increment user profiling counters.\n */\nvoid\naddupc(caddr_t pc, struct uprof *pbuf, int ticks)\n{\n\tu_int indx;\n\n\tif (pc < (caddr_t)pbuf->pr_off)\n\t\treturn;\n\n\tindx = pc - (caddr_t)pbuf->pr_off;\n\tindx = (indx * pbuf->pr_scale) >> 16;\n\tif (indx >= pbuf->pr_size)\n\t\treturn;\n\n\tpbuf->pr_base[indx] += ticks;\n}\n\n/*\n * ffs -- vax ffs instruction\n */\nint\nffs(u_long mask)\n{\n\tint cnt;\n\n\tif (mask == 0)\n\t\treturn 0;\n\tfor (cnt = 1; !(mask & 1); cnt++)\n\t\tmask >>= 1;\n\n\treturn cnt;\n}\n\n/*\n * Copy a null terminated string from one point to another.\n * Returns zero on success, ENOENT if maxlength exceeded.\n * If lencopied is non-zero, *lencopied gets the length of the copy\n * (including the null terminating byte).\n */\nint\ncopystr(caddr_t src, caddr_t dest, u_int maxlength, u_int *lencopied)\n{\n\tcaddr_t dest0 = dest;\n\tint error = ENOENT;\n\n\tif (maxlength != 0) {\n\t\twhile ((*dest++ = *src++) != '\\0') {\n\t\t\tif (--maxlength == 0) {\n\t\t\t\t/* Failed. */\n\t\t\t\tgoto done;\n\t\t\t}\n\t\t}\n\t\t/* Succeeded. */\n\t\terror = 0;\n\t}\ndone:\n\tif (lencopied != 0)\n\t\t*lencopied = dest - dest0;\n\n\treturn error;\n}\n\n/*\n * Calculate the length of a string.\n */\nsize_t\nstrlen(const char *s)\n{\n\tconst char *s0 = s;\n\n\twhile (*s++ != '\\0')\n\t\t;\n\n\treturn s - s0 - 1;\n}\n\n/*\n * Return 0 if a user address is valid.\n * There is only one memory region allowed for user: RAM.\n */\nint\nbaduaddr(caddr_t addr)\n{\n\tif (addr >= (caddr_t)__user_data_start &&\n\t    addr < (caddr_t)__user_data_end)\n\t\treturn 0;\n\n\treturn 1;\n}\n\n/*\n * Return 0 if a kernel address is valid.\n * There are two memory regions allowed for kernel: RAM and flash.\n */\nint\nbadkaddr(caddr_t addr)\n{\n\tif (addr >= (caddr_t)__kernel_data_start &&\n\t    addr < (caddr_t)__kernel_data_end)\n\t\treturn 0;\n\tif (addr >= (caddr_t)__kernel_flash_start &&\n\t    addr < (caddr_t)__kernel_flash_end)\n\t\treturn 0;\n\n\treturn 1;\n}\n\n/*\n * Insert the specified element into a queue immediately after\n * the specified predecessor element.\n */\nvoid\ninsque(void *element, void *predecessor)\n{\n\tstruct que {\n\t\tstruct que *q_next;\n\t\tstruct que *q_prev;\n\t};\n\n\tstruct que *e = (struct que *)element;\n\tstruct que *prev = (struct que *)predecessor;\n\n\te->q_prev = prev;\n\te->q_next = prev->q_next;\n\tprev->q_next->q_prev = e;\n\tprev->q_next = e;\n}\n\n/*\n * Remove the specified element from the queue.\n */\nvoid\nremque(void *element)\n{\n\tstruct que {\n\t\tstruct que *q_next;\n\t\tstruct que *q_prev;\n\t};\n\n\tstruct que *e = (struct que *)element;\n\n\te->q_prev->q_next = e->q_next;\n\te->q_next->q_prev = e->q_prev;\n}\n\n/*\n * Compare strings.\n */\nint\nstrncmp(const char *s1, const char *s2, size_t n)\n{\n\tint ret, tmp;\n\n\tif (n == 0)\n\t\treturn 0;\n\n\tdo {\n\t\tret = *s1++ - (tmp = *s2++);\n\t} while ((ret == 0) && (tmp != 0) && --n);\n\n\treturn ret;\n}\n\n/* Nonzero if pointer is not aligned on a \"sz\" boundary. */\n#define UNALIGNED(p, sz)\t((u_int)(p) & ((sz) - 1))\n\n/*\n * Copy data from the memory region pointed to by src0 to the memory\n * region pointed to by dst0.\n * If the regions overlap, the behavior is undefined.\n */\nvoid\nbcopy(const void *src0, void *dst0, size_t nbytes)\n{\n\tu_char\t\t*dst = dst0;\n\tconst u_char\t*src = src0;\n\tu_int\t\t*aligned_dst;\n\tconst u_int\t*aligned_src;\n\n\t/* printf(\"bcopy (%08x, %08x, %d)\\n\", src0, dst0, nbytes); */\n\t/* If the size is small, or either SRC or DST is unaligned,\n\t * then punt into the byte copy loop.  This should be rare. */\n\tif (nbytes >= 4 * sizeof(u_int) &&\n\t    !UNALIGNED(src, sizeof(u_int)) &&\n\t    !UNALIGNED(dst, sizeof(u_int))) {\n\t\taligned_dst = (u_int *)dst;\n\t\taligned_src = (const u_int *)src;\n\n\t\t/* Copy 4X unsigned words at a time if possible. */\n\t\twhile (nbytes >= 4 * sizeof(u_int)) {\n\t\t\t*aligned_dst++ = *aligned_src++;\n\t\t\t*aligned_dst++ = *aligned_src++;\n\t\t\t*aligned_dst++ = *aligned_src++;\n\t\t\t*aligned_dst++ = *aligned_src++;\n\t\t\tnbytes -= 4 * sizeof(u_int);\n\t\t}\n\n\t\t/* Copy one unsigned word at a time if possible. */\n\t\twhile (nbytes >= sizeof(u_int)) {\n\t\t\t*aligned_dst++ = *aligned_src++;\n\t\t\tnbytes -= sizeof(u_int);\n\t\t}\n\n\t\t/* Pick up any residual with a byte copier. */\n\t\tdst = (u_char *)aligned_dst;\n\t\tsrc = (const u_char *)aligned_src;\n\t}\n\n\twhile (nbytes--)\n\t\t*dst++ = *src++;\n}\n\nvoid *\nmemcpy(void *dst, const void *src, size_t nbytes)\n{\n\tbcopy(src, dst, nbytes);\n\n\treturn dst;\n}\n\n/*\n * Fill the array with zeroes.\n */\nvoid\nbzero(void *dst0, size_t nbytes)\n{\n\tu_char *dst;\n\tu_int *aligned_dst;\n\n\tdst = (u_char *)dst0;\n\twhile (UNALIGNED(dst, sizeof(u_int))) {\n\t\t*dst++ = 0;\n\t\tif (--nbytes == 0)\n\t\t\treturn;\n\t}\n\n\tif (nbytes >= sizeof(u_int)) {\n\t\t/*\n\t\t * If we get this far, we know that nbytes is large\n\t\t * and dst is word-aligned.\n\t\t */\n\t\taligned_dst = (u_int *)dst;\n\n\t\twhile (nbytes >= 4 * sizeof(u_int)) {\n\t\t\t*aligned_dst++ = 0;\n\t\t\t*aligned_dst++ = 0;\n\t\t\t*aligned_dst++ = 0;\n\t\t\t*aligned_dst++ = 0;\n\t\t\tnbytes -= 4 * sizeof(u_int);\n\t\t}\n\t\twhile (nbytes >= sizeof(u_int)) {\n\t\t\t*aligned_dst++ = 0;\n\t\t\tnbytes -= sizeof(u_int);\n\t\t}\n\t\tdst = (u_char *)aligned_dst;\n\t}\n\n\t/* Pick up the remainder with a bytewise loop. */\n\twhile (nbytes--)\n\t\t*dst++ = 0;\n}\n\n/*\n * Compare not more than nbytes of data pointed to by m1 with\n * the data pointed to by m2.\n * Return an integer greater than, equal to or less than zero\n * according to whether the object pointed to by m1 is greater\n * than, equal to or less than the object pointed to by m2.\n */\nint\nbcmp(const void *m1, const void *m2, size_t nbytes)\n{\n\tconst u_char *s1 = (const u_char *)m1;\n\tconst u_char *s2 = (const u_char *)m2;\n\tconst u_int *aligned1, *aligned2;\n\n\t/*\n\t * If the size is too small, or either pointer is unaligned,\n\t * then we punt to the byte compare loop.\n\t * Hopefully this will not turn up in inner loops.\n\t */\n\tif (nbytes >= 4 * sizeof(u_int) &&\n\t    !UNALIGNED(s1, sizeof(u_int)) &&\n\t    !UNALIGNED(s2, sizeof(u_int))) {\n\t\t/* Otherwise, load and compare the blocks of memory one\n\t\t   word at a time. */\n\t\taligned1 = (const u_int *)s1;\n\t\taligned2 = (const u_int *)s2;\n\t\twhile (nbytes >= sizeof(u_int)) {\n\t\t\tif (*aligned1 != *aligned2)\n\t\t\t\tbreak;\n\t\t\taligned1++;\n\t\t\taligned2++;\n\t\t\tnbytes -= sizeof(u_int);\n\t\t}\n\n\t\t/* Check remaining characters. */\n\t\ts1 = (const u_char *)aligned1;\n\t\ts2 = (const u_char *)aligned2;\n\t}\n\twhile (nbytes--) {\n\t\tif (*s1 != *s2)\n\t\t\treturn *s1 - *s2;\n\t\ts1++;\n\t\ts2++;\n\t}\n\n\treturn 0;\n}\n\nint\ncopyout(caddr_t from, caddr_t to, u_int nbytes)\n{\n\t/* printf(\"copyout(from=%p, to=%p, nbytes=%u)\\n\", from, to, nbytes); */\n\tif (baduaddr(to) || baduaddr(to + nbytes - 1))\n\t\treturn EFAULT;\n\tbcopy(from, to, nbytes);\n\n\treturn 0;\n}\n\nint\ncopyin(caddr_t from, caddr_t to, u_int nbytes)\n{\n\tif (baduaddr(from) || baduaddr(from + nbytes - 1))\n\t\treturn EFAULT;\n\tbcopy(from, to, nbytes);\n\n\treturn 0;\n}\n\n/**\n  * @brief  Enable AHB1 peripherals clock on dedicated port.\n  * @param  GPIOx GPIO Port\n  * @note   This function is an extension to the LL_GPIO library.\n  */\nvoid\nLL_GPIO_EnableClock(GPIO_TypeDef *GPIOx)\n{\n\t/* Check the parameters. */\n\tassert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\n\n\tif (GPIOx == GPIOA) {\n\t\tLL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA);\n\t} else if (GPIOx == GPIOB) {\n\t\tLL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOB);\n\t} else if (GPIOx == GPIOC) {\n\t\tLL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOC);\n#if defined(GPIOD)\n\t} else if (GPIOx == GPIOD) {\n\t\tLL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOD);\n#endif\n#if defined(GPIOE)\n\t} else if (GPIOx == GPIOE) {\n\t\tLL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOE);\n#endif\n#if defined(GPIOF)\n\t} else if (GPIOx == GPIOF) {\n\t\tLL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOF);\n#endif\n#if defined(GPIOG)\n\t} else if (GPIOx == GPIOG) {\n\t\tLL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOG);\n#endif\n#if defined(GPIOH)\n\t} else if (GPIOx == GPIOH) {\n\t\tLL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOH);\n#endif\n#if defined(GPIOI)\n\t} else if (GPIOx == GPIOI) {\n\t\tLL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOI);\n#endif\n#if defined(GPIOJ)\n\t} else if (GPIOx == GPIOJ) {\n\t\tLL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOJ);\n#endif\n#if defined(GPIOK)\n\t} else if (GPIOx == GPIOK) {\n\t\tLL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOK);\n#endif\n\t}\n}\n"
  },
  {
    "path": "sys/arch/stm32/stm32/mpu.c",
    "content": "/*\n * Copyright (c) 2025 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/file.h>\n#include <sys/inode.h>\n#include <sys/sysctl.h>\n\n#include <machine/mpuvar.h>\n\n#include <stm32/hal/stm32f4xx_ll_cortex.h>\n\nint\nmpu_sysctl(int *name, u_int namelen, void *oldp, size_t *oldlenp, void *newp,\n    size_t newlen)\n{\n\n\t/* All sysctl names at this level are terminal. */\n\tif (namelen != 1)\n\t\treturn ENOTDIR;\n\n\tswitch (name[0]) {\n\tcase CPU_MPU_ENABLE:\n\t\treturn sysctl_rdint(oldp, oldlenp, newp,\n\t\t    LL_MPU_IsEnabled());\n\tcase CPU_MPU_CTRL:\n\t\treturn sysctl_rdint(oldp, oldlenp, newp,\n\t\t    LL_MPU_GetCtrl());\n\tcase CPU_MPU_NREGIONS:\n\t\treturn sysctl_rdint(oldp, oldlenp, newp,\n\t\t    LL_MPU_GetNumRegions());\n\tcase CPU_MPU_SEPARATE:\n\t\treturn sysctl_rdint(oldp, oldlenp, newp,\n\t\t    LL_MPU_GetSeparate());\n\tdefault:\n\t\treturn EOPNOTSUPP;\n\t}\n}\n"
  },
  {
    "path": "sys/arch/stm32/stm32/sig_machdep.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)machdep.c\t2.4 (2.11BSD) 1999/9/13\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/signalvar.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/buf.h>\n#include <sys/map.h>\n#include <sys/syslog.h>\n\n#include <machine/frame.h>\n\n#if 0\n#define DIAGNOSTIC\n#endif\n\n/*\n * Send an interrupt to process.\n *\n * Stack is set up to allow trampoline code stored at u.u_sigtramp (as\n * specified by the user process) to call the user's real signal catch\n * routine, followed by sys sigreturn to the sigreturn routine below\n * (see lib/libc/arm/sys/sigaction.S).  After sigreturn resets the signal\n * mask, the stack, and the frame pointer, it returns to the user specified\n * pc and regs.\n */\nvoid\nsendsig(sig_t p, int sig, long mask)\n{\n\tstruct sigframe {\n\t\tint\tsf_space[4];\n\t\tstruct\tsigcontext sf_sc;\n\t};\n\n\tstruct trapframe *regs = u.u_frame;\n\tstruct sigframe *sfp;\n\tint oonstack;\n\n#ifdef DIAGNOSTIC\n\tprintf(\"(%u)sendsig %d, mask=%#x, handler=%#x, tramp=%#x\\n\",\n\t    u.u_procp->p_pid, sig, mask, p, u.u_sigtramp);\n#endif\n\toonstack = u.u_sigstk.ss_flags & SA_ONSTACK;\n\n\t/*\n\t * Allocate and validate space for the signal frame.\n\t */\n\tif ((u.u_psflags & SAS_ALTSTACK) &&\n\t    !(u.u_sigstk.ss_flags & SA_ONSTACK) &&\n\t    (u.u_sigonstack & sigmask(sig))) {\n\t\tsfp = (struct sigframe *)(u.u_sigstk.ss_base +\n\t\t    u.u_sigstk.ss_size);\n\t\tu.u_sigstk.ss_flags |= SA_ONSTACK;\n\t} else\n\t\tsfp = (struct sigframe *)regs->tf_sp;\n\n\tsfp--;\n\tif (!(u.u_sigstk.ss_flags & SA_ONSTACK)) {\n\t\tif ((caddr_t)sfp < (caddr_t)u.u_procp->p_daddr + u.u_dsize) {\n\t\t\t/*\n\t\t\t * Process has trashed its stack; give it an illegal\n\t\t\t * instruction violation to halt it in its tracks.\n\t\t\t */\n\t\t\tfatalsig(SIGILL);\n\t\t\treturn;\n\t\t}\n\t\tif (u.u_procp->p_ssize < (size_t)__user_data_end - (u_int)sfp) {\n\t\t\tu.u_procp->p_ssize = (size_t)__user_data_end - (u_int)sfp;\n\t\t\tu.u_procp->p_saddr = (u_int)sfp;\n\t\t\tu.u_ssize = u.u_procp->p_ssize;\n\t\t}\n\t}\n\n\t/*\n\t * Build the signal context to be used by sigreturn.\n\t */\n\tsfp->sf_sc.sc_onstack = oonstack;\n\tsfp->sf_sc.sc_mask = mask;\n\tsfp->sf_sc.sc_r0  = regs->tf_r0;\n\tsfp->sf_sc.sc_r1  = regs->tf_r1;\n\tsfp->sf_sc.sc_r2  = regs->tf_r2;\n\tsfp->sf_sc.sc_r3  = regs->tf_r3;\n\tsfp->sf_sc.sc_sp  = regs->tf_sp;\n\tsfp->sf_sc.sc_lr  = regs->tf_lr;\n\tsfp->sf_sc.sc_pc  = regs->tf_pc;\n\tsfp->sf_sc.sc_psr = regs->tf_psr;\n\tsfp->sf_sc.sc_r4  = regs->tf_r4;\n\tsfp->sf_sc.sc_r5  = regs->tf_r5;\n\tsfp->sf_sc.sc_r6  = regs->tf_r6;\n\tsfp->sf_sc.sc_r7  = regs->tf_r7;\n\tsfp->sf_sc.sc_r8  = regs->tf_r8;\n\tsfp->sf_sc.sc_r9  = regs->tf_r9;\n\tsfp->sf_sc.sc_r10 = regs->tf_r10;\n\tsfp->sf_sc.sc_r11 = regs->tf_r11;\n\n\t/* Call signal handler. */\n\tregs->tf_r0 = sig;\t\t\t/* $a1 - signal number */\n\tregs->tf_r1 = u.u_code;\t\t\t/* $a2 - code */\n\tregs->tf_r2 = (int)&sfp->sf_sc;\t\t/* $a3 - addr of sigcontext */\n\tregs->tf_lr = (int)u.u_sigtramp;\t/* $lr - sigtramp */\n\tregs->tf_sp = (int)sfp;\t\t\t/* $sp - stack */\n\tregs->tf_pc = (int)p;\t\t\t/* $pc - handler */\n#ifdef DIAGNOSTIC\n\tprintf(\"    ...call handler %p (sig=%d, code=%#x, context=%p)\\n\",\n\t    p, sig, u.u_code, &sfp->sf_sc);\n\tprintf(\"    ...stack=%p, return to %p\\n\", sfp, u.u_sigtramp);\n#endif\n}\n\n/*\n * System call to cleanup state after a signal\n * has been taken.  Reset signal mask and\n * stack state from context left by sendsig (above).\n * Return to previous pc and ps as specified by\n * context left by sendsig. Check carefully to\n * make sure that the user has not modified the\n * ps to gain improper priviledges or to cause\n * a machine fault.\n */\nvoid\nsigreturn(void)\n{\n\tstruct trapframe *regs = u.u_frame;\n\tstruct sigcontext *scp =\n\t    (struct sigcontext *)(regs->tf_sp + 16);\n\n#ifdef DIAGNOSTIC\n\tprintf(\"(%u)sigreturn stack=%#x, context=%p\\n\",\n\t    u.u_procp->p_pid, regs->tf_sp, scp);\n#endif\n\tif (baduaddr((caddr_t)scp) ||\n\t    baduaddr((caddr_t)scp + sizeof(*scp))) {\n\t\tu.u_error = EFAULT;\n\t\treturn;\n\t}\n\tu.u_error = EJUSTRETURN;\n\tif (scp->sc_onstack & SA_ONSTACK)\n\t\tu.u_sigstk.ss_flags |= SA_ONSTACK;\n\telse\n\t\tu.u_sigstk.ss_flags &= ~SA_ONSTACK;\n\tu.u_procp->p_sigmask = scp->sc_mask & ~sigcantmask;\n\n\t/* Return from signal handler. */\n\tregs->tf_r0  = scp->sc_r0;\n\tregs->tf_r1  = scp->sc_r1;\n\tregs->tf_r2  = scp->sc_r2;\n\tregs->tf_r3  = scp->sc_r3;\n\tregs->tf_sp  = scp->sc_sp;\n\tregs->tf_lr  = scp->sc_lr;\n\tregs->tf_pc  = scp->sc_pc;\n\tregs->tf_psr = scp->sc_psr;\n\tregs->tf_r4  = scp->sc_r4;\n\tregs->tf_r5  = scp->sc_r5;\n\tregs->tf_r6  = scp->sc_r6;\n\tregs->tf_r7  = scp->sc_r7;\n\tregs->tf_r8  = scp->sc_r8;\n\tregs->tf_r9  = scp->sc_r9;\n\tregs->tf_r10 = scp->sc_r10;\n\tregs->tf_r11 = scp->sc_r11;\n#ifdef DIAGNOSTIC\n\tprintf(\"    ...to %#x, stack %#x\\n\", regs->tf_pc, regs->tf_sp);\n#endif\n}\n"
  },
  {
    "path": "sys/arch/stm32/stm32/syscall.c",
    "content": "/*\n * Copyright (c) 2022 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include <sys/param.h>\n#include <sys/signalvar.h>\n#include <sys/systm.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/vm.h>\n\n#include <machine/frame.h>\n\n/*\n * SVC_Handler(frame)\n *\tstruct trapframe *frame;\n *\n * Exception handler entry point for system calls (via 'svc' instruction).\n * The real work is done in PendSV_Handler at the lowest exception priority.\n */\nvoid\nSVC_Handler(void)\n{\n\t/* Set a PendSV exception to immediately tail-chain into. */\n\tSCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;\n\n\t__DSB();\n\t__ISB();\n\n\t/* PendSV has lowest priority, so need to allow it to fire. */\n\t(void)spl0();\n}\n\n/*\n * PendSV_Handler(frame)\n *\tstruct trapframe *frame;\n *\n * System call handler (via SVC_Handler pending a PendSV exception).\n * Save the processor state in a trap frame and pass it to syscall().\n * Restore processor state from returned trap frame on return from syscall().\n */\nvoid\nPendSV_Handler(void)\n{\n__asm volatile (\n\"\t.syntax\tunified\t\t\\n\\t\"\n\"\t.thumb\t\t\t\\n\\t\"\n\n\"\tcpsid\ti\t\t\\n\\t\"\t/* Disable interrupts. */\n\n#ifdef __thumb2__\n\t/*\n\t * ARMv7-M hardware already pushed r0-r3, ip, lr, pc, psr on PSP,\n\t * and then switched to MSP and is currently in Handler Mode.\n\t */\n\"\tpush\t{r4-r11}\t\\n\\t\"\t/* Push v1-v8 registers onto MSP. */\n\"\tmrs\tr1, PSP\t\t\\n\\t\"\t/* Get pointer to trap frame. */\n\"\tldmfd\tr1, {r2-r9}\t\\n\\t\"\t/* Copy trap frame from PSP. */\n\"\tmov\tr6, r1\t\t\\n\\t\"\t/* Set trap frame sp as PSP. */\n\"\tpush\t{r2-r9}\t\t\\n\\t\"\t/* Push that trap frame onto MSP. */\n\n\"\tmrs\tr0, MSP\t\t\\n\\t\"\t/* MSP trap frame is syscall() arg. */\n\"\tbl\tsyscall\t\t\\n\\t\"\t/* Call syscall() with MSP as arg. */\n\n\"\tpop\t{r2-r9}\t\t\\n\\t\"\t/* Pop off trap frame from MSP. */\n\"\tmov\tr1, r6\t\t\\n\\t\"\t/* PSP will be trap frame sp. */\n\"\tstmia\tr1, {r2-r9}\t\\n\\t\"\t/* Hardware pops off PSP on return. */\n\"\tmsr\tPSP, r1\t\t\\n\\t\"\t/* Set PSP as trap frame sp. */\n\"\tpop\t{r4-r11}\t\\n\\t\"\t/* Pop from MSP into v1-v8 regs. */\n\n\t/*\n\t * On return, ARMv7-M hardware sets PSP as stack pointer,\n\t * pops from PSP to registers r0-r3, ip, lr, pc, psr,\n\t * and then switches back to Thread Mode (exception completed).\n\t */\n\"\tmov\tlr, #0xFFFFFFFD\t\\n\\t\"\t/* EXC_RETURN Thread Mode, PSP */\n\t\t\t\t\t/* Return to Thread Mode. */\n#else /* __thumb__ */\n\t/*\n\t * ARMv6-M hardware already pushed r0-r3, ip, lr, pc, psr on PSP,\n\t * and then switched to MSP and is currently in Handler Mode.\n\t */\n\"\tmov\tr0, r8\t\t\\n\\t\"\t/* Bring high register v5 to low. */\n\"\tmov\tr1, r9\t\t\\n\\t\"\t/* Bring high register v6 to low. */\n\"\tmov\tr2, r10\t\t\\n\\t\"\t/* Bring high register v7 to low. */\n\"\tmov\tr3, r11\t\t\\n\\t\"\t/* Bring high register v8 to low. */\n\"\tpush\t{r0-r3}\t\t\\n\\t\"\t/* Push v5-v8 registers onto MSP. */\n\"\tpush\t{r4-r7}\t\t\\n\\t\"\t/* Push v1-v4 registers onto MSP. */\n\n\"\tmrs\tr1, PSP\t\t\\n\\t\"\t/* Get pointer to trap frame. */\n\"\tmov\tr2, r1\t\t\\n\\t\"\t/* Pointer to use for top half. */\n\"\tadds\tr2, #(4 * 4)\t\\n\\t\"\t/* Index to top half of trap frame. */\n\"\tldmfd\tr2!, {r4-r7}\t\\n\\t\"\t/* Copy frame top half from PSP. */\n\"\tmov\tr4, r1\t\t\\n\\t\"\t/* Set trap frame sp as PSP. */\n\"\tpush\t{r4-r7}\t\t\\n\\t\"\t/* Push frame top half onto MSP. */\n\"\tldmfd\tr1!, {r4-r7}\t\\n\\t\"\t/* Copy frame low half from PSP. */\n\"\tpush\t{r4-r7}\t\t\\n\\t\"\t/* Push frame low half onto MSP. */\n\n\"\tmrs\tr0, MSP\t\t\\n\\t\"\t/* MSP trap frame is syscall() arg. */\n\"\tbl\tsyscall\t\t\\n\\t\"\t/* Call syscall() with MSP as arg. */\n\n\"\tpop\t{r0-r7}\t\t\\n\\t\"\t/* Pop off trap frame from MSP. */\n\"\tmsr\tPSP, r4\t\t\\n\\t\"\t/* Set PSP as trap frame sp. */\n\"\tstmia\tr4!, {r0-r3}\t\\n\\t\"\t/* Copy trap frame low half to PSP. */\n\"\tmrs\tr1, PSP\t\t\\n\\t\"\t/* Get PSP again as trap frame sp. */\n\"\tstmia\tr4!, {r1,r5-r7}\t\\n\\t\"\t/* Copy trap frame top half to PSP. */\n\n\"\tpop\t{r4-r7}\t\t\\n\\t\"\t/* Pop from MSP into v1-v4 regs. */\n\"\tpop\t{r0-r3}\t\t\\n\\t\"\t/* Pop from MSP for v5-v8 regs. */\n\"\tmov\tr11, r3\t\t\\n\\t\"\t/* Move low register to high v8. */\n\"\tmov\tr10, r2\t\t\\n\\t\"\t/* Move low register to high v7. */\n\"\tmov\tr9, r1\t\t\\n\\t\"\t/* Move low register to high v6. */\n\"\tmov\tr8, r0\t\t\\n\\t\"\t/* Move low register to high v5. */\n\n\t/*\n\t * On return, ARMv6-M hardware sets PSP as stack pointer,\n\t * pops from PSP to registers r0-r3, ip, lr, pc, psr,\n\t * and then switches back to Thread Mode (exception completed).\n\t */\n\"\tldr\tr1, =0xFFFFFFFD\t\\n\\t\"\t/* EXC_RETURN Thread Mode, PSP */\n\"\tmov\tlr, r1\t\t\\n\\t\"\t/* Return to Thread Mode. */\n#endif\n);\n}\n\nvoid\nsyscall(struct trapframe *frame)\n{\n\tint psig;\n\ttime_t syst;\n\tint code;\n\tu_int sp;\n\n\tsyst = u.u_ru.ru_stime;\n\n\tif ((u_int)frame < (u_int)&u + sizeof(u)) {\n\t\tpanic(\"stack overflow\");\n\t\t/* NOTREACHED */\n\t}\n\n#ifdef UCB_METER\n\tcnt.v_trap++;\n\tcnt.v_syscall++;\n#endif\n\n\t/* Enable interrupts. */\n\t(void)arm_intr_enable();\n\n\tu.u_error = 0;\n\tu.u_frame = frame;\n\tu.u_code = u.u_frame->tf_pc - INSN_SZ;\t/* Syscall for sig handler. */\n\n\tled_control(LED_KERNEL, 1);\n\n\t/* Check stack. */\n\tsp = u.u_frame->tf_sp;\n\tif (sp < u.u_procp->p_daddr + u.u_dsize) {\n\t\t/* Process has trashed its stack; give it an illegal\n\t\t * instruction violation to halt it in its tracks. */\n\t\tpsig = SIGSEGV;\n\t\tgoto bad;\n\t}\n\tif (u.u_procp->p_ssize < (size_t)__user_data_end - sp) {\n\t\t/* Expand stack. */\n\t\tu.u_procp->p_ssize = (size_t)__user_data_end - sp;\n\t\tu.u_procp->p_saddr = sp;\n\t\tu.u_ssize = u.u_procp->p_ssize;\n\t}\n\n\tcode = *(int *)u.u_code & 0377;\t\t/* Bottom 8 bits are index. */\n\n\tconst struct sysent *callp = &sysent[0];\n\n\tif (code < nsysent)\n\t\tcallp += code;\n\n\tif (callp->sy_narg) {\n\t\t/* In AAPCS, first four args are from trapframe regs r0-r3. */\n\t\tu.u_arg[0] = u.u_frame->tf_r0;\t/* $a1 */\n\t\tu.u_arg[1] = u.u_frame->tf_r1;\t/* $a2 */\n\t\tu.u_arg[2] = u.u_frame->tf_r2;\t/* $a3 */\n\t\tu.u_arg[3] = u.u_frame->tf_r3;\t/* $a4 */\n\n\t\t/* In AAPCS, stack must be double-word aligned. */\n\t\tint stkalign = 0;\n\t\tif (u.u_frame->tf_psr & SCB_CCR_STKALIGN_Msk) {\n\t\t\tstkalign = 4;\t\t/* Skip over padding byte. */\n\t\t}\n\n\t\t/* Remaining args are from the stack, after the trapframe. */\n\t\tif (callp->sy_narg > 4) {\n\t\t\tu_int addr = (u.u_frame->tf_sp + 32 + stkalign) & ~3;\n\t\t\tif (!baduaddr((caddr_t)addr))\n\t\t\t\tu.u_arg[4] = *(u_int *)addr;\n\t\t}\n\t\tif (callp->sy_narg > 5) {\n\t\t\tu_int addr = (u.u_frame->tf_sp + 36 + stkalign) & ~3;\n\t\t\tif (!baduaddr((caddr_t)addr))\n\t\t\t\tu.u_arg[5] = *(u_int *)addr;\n\t\t}\n\t}\n\n\tu.u_rval = 0;\n\n\tif (setjmp(&u.u_qsave) == 0) {\n\t\t(*callp->sy_call)();\t\t/* Make syscall. */\n\t}\n\n\tswitch (u.u_error) {\n\tcase 0:\n\t\tu.u_frame->tf_psr &= ~PSR_C;\t/* Clear carry bit. */\n\t\tu.u_frame->tf_r0 = u.u_rval;\t/* $a1 - result. */\n\t\tbreak;\n\tcase ERESTART:\n\t\tu.u_frame->tf_pc -= INSN_SZ;\t/* Return to svc syscall. */\n\t\tbreak;\n\tcase EJUSTRETURN:\t\t\t/* Return from sig handler. */\n\t\tbreak;\n\tdefault:\n\t\tu.u_frame->tf_psr |= PSR_C;\t/* Set carry bit. */\n\t\tu.u_frame->tf_r0 = u.u_error;\t/* $a1 - result. */\n\t\tbreak;\n\t}\n\tgoto out;\n\nbad:\n\t/* From this point and further the interrupts must be enabled. */\n\tpsignal(u.u_procp, psig);\n\nout:\n\tuserret(u.u_frame->tf_pc, syst);\n\n\tled_control(LED_KERNEL, 0);\n}\n"
  },
  {
    "path": "sys/arch/stm32/stm32/sysctl.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)kern_pdp.c\t1.4 (2.11BSD) 1998/5/12\n */\n\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/ioctl.h>\n#include <sys/proc.h>\n#include <sys/kernel.h>\n#include <sys/file.h>\n#include <sys/inode.h>\n#include <sys/sysctl.h>\n#include <sys/tty.h>\n#include <sys/systm.h>\n#include <sys/dk.h>\n#include <sys/vmsystm.h>\n#include <sys/ptrace.h>\n#include <sys/namei.h>\n#include <sys/vmmeter.h>\n#include <sys/map.h>\n#include <sys/conf.h>\n#ifdef PTY_ENABLED\n#include <sys/pty.h>\n#endif\n\n#include <machine/cpu.h>\n#include <machine/mpuvar.h>\n\n/*\n * Errno messages.\n */\nstatic const char *errlist[] = {\n\t\"Undefined error: 0\",\t\t\t/*  0 - ENOERROR */\n\t\"Operation not permitted\",\t\t/*  1 - EPERM */\n\t\"No such file or directory\",\t\t/*  2 - ENOENT */\n\t\"No such process\",\t\t\t/*  3 - ESRCH */\n\t\"Interrupted system call\",\t\t/*  4 - EINTR */\n\t\"Input/output error\",\t\t\t/*  5 - EIO */\n\t\"Device not configured\",\t\t/*  6 - ENXIO */\n\t\"Argument list too long\",\t\t/*  7 - E2BIG */\n\t\"Exec format error\",\t\t\t/*  8 - ENOEXEC */\n\t\"Bad file descriptor\",\t\t\t/*  9 - EBADF */\n\t\"No child processes\",\t\t\t/* 10 - ECHILD */\n\t\"No more processes\",\t\t\t/* 11 - EAGAIN */\n\t\"Cannot allocate memory\",\t\t/* 12 - ENOMEM */\n\t\"Permission denied\",\t\t\t/* 13 - EACCES */\n\t\"Bad address\",\t\t\t\t/* 14 - EFAULT */\n\t\"Block device required\",\t\t/* 15 - ENOTBLK */\n\t\"Device busy\",\t\t\t\t/* 16 - EBUSY */\n\t\"File exists\",\t\t\t\t/* 17 - EEXIST */\n\t\"Cross-device link\",\t\t\t/* 18 - EXDEV */\n\t\"Operation not supported by device\",\t/* 19 - ENODEV */\n\t\"Not a directory\",\t\t\t/* 20 - ENOTDIR */\n\t\"Is a directory\",\t\t\t/* 21 - EISDIR */\n\t\"Invalid argument\",\t\t\t/* 22 - EINVAL */\n\t\"Too many open files in system\",\t/* 23 - ENFILE */\n\t\"Too many open files\",\t\t\t/* 24 - EMFILE */\n\t\"Inappropriate ioctl for device\",\t/* 25 - ENOTTY */\n\t\"Text file busy\",\t\t\t/* 26 - ETXTBSY */\n\t\"File too large\",\t\t\t/* 27 - EFBIG */\n\t\"No space left on device\",\t\t/* 28 - ENOSPC */\n\t\"Illegal seek\",\t\t\t\t/* 29 - ESPIPE */\n\t\"Read-only file system\",\t\t/* 30 - EROFS */\n\t\"Too many links\",\t\t\t/* 31 - EMLINK */\n\t\"Broken pipe\",\t\t\t\t/* 32 - EPIPE */\n\n\t/* math software */\n\t\"Numerical argument out of domain\",\t/* 33 - EDOM */\n\t\"Result too large\",\t\t\t/* 34 - ERANGE */\n\n\t/* non-blocking and interrupt i/o */\n\t\"Resource temporarily unavailable\",\t/* 35 - EWOULDBLOCK */\n\t\"Operation now in progress\",\t\t/* 36 - EINPROGRESS */\n\t\"Operation already in progress\",\t/* 37 - EALREADY */\n\n\t/* ipc/network software -- argument errors */\n\t\"Socket operation on non-socket\",\t/* 38 - ENOTSOCK */\n\t\"Destination address required\",\t\t/* 39 - EDESTADDRREQ */\n\t\"Message too long\",\t\t\t/* 40 - EMSGSIZE */\n\t\"Protocol wrong type for socket\",\t/* 41 - EPROTOTYPE */\n\t\"Protocol not available\",\t\t/* 42 - ENOPROTOOPT */\n\t\"Protocol not supported\",\t\t/* 43 - EPROTONOSUPPORT */\n\t\"Socket type not supported\",\t\t/* 44 - ESOCKTNOSUPPORT */\n\t\"Operation not supported\",\t\t/* 45 - EOPNOTSUPP */\n\t\"Protocol family not supported\",\t/* 46 - EPFNOSUPPORT */\n\t\t\t\t\t\t/* 47 - EAFNOSUPPORT */\n\t\"Address family not supported by protocol family\",\n\t\"Address already in use\",\t\t/* 48 - EADDRINUSE */\n\t\"Can't assign requested address\",\t/* 49 - EADDRNOTAVAIL */\n\n\t/* ipc/network software -- operational errors */\n\t\"Network is down\",\t\t\t/* 50 - ENETDOWN */\n\t\"Network is unreachable\",\t\t/* 51 - ENETUNREACH */\n\t\"Network dropped connection on reset\",\t/* 52 - ENETRESET */\n\t\"Software caused connection abort\",\t/* 53 - ECONNABORTED */\n\t\"Connection reset by peer\",\t\t/* 54 - ECONNRESET */\n\t\"No buffer space available\",\t\t/* 55 - ENOBUFS */\n\t\"Socket is already connected\",\t\t/* 56 - EISCONN */\n\t\"Socket is not connected\",\t\t/* 57 - ENOTCONN */\n\t\"Can't send after socket shutdown\",\t/* 58 - ESHUTDOWN */\n\t\"Too many references: can't splice\",\t/* 59 - ETOOMANYREFS */\n\t\"Operation timed out\",\t\t\t/* 60 - ETIMEDOUT */\n\t\"Connection refused\",\t\t\t/* 61 - ECONNREFUSED */\n\n\t\"Too many levels of symbolic links\",\t/* 62 - ELOOP */\n\t\"File name too long\",\t\t\t/* 63 - ENAMETOOLONG */\n\n\t/* should be rearranged */\n\t\"Host is down\",\t\t\t\t/* 64 - EHOSTDOWN */\n\t\"No route to host\",\t\t\t/* 65 - EHOSTUNREACH */\n\t\"Directory not empty\",\t\t\t/* 66 - ENOTEMPTY */\n\n\t/* quotas & mush */\n\t\"Too many processes\",\t\t\t/* 67 - EPROCLIM */\n\t\"Too many users\",\t\t\t/* 68 - EUSERS */\n\t\"Disc quota exceeded\",\t\t\t/* 69 - EDQUOT */\n\n\t/* Network File System */\n\t\"Stale NFS file handle\",\t\t/* 70 - ESTALE */\n\t\"Too many levels of remote in path\",\t/* 71 - EREMOTE */\n\t\"RPC struct is bad\",\t\t\t/* 72 - EBADRPC */\n\t\"RPC version wrong\",\t\t\t/* 73 - ERPCMISMATCH */\n\t\"RPC prog. not avail\",\t\t\t/* 74 - EPROGUNAVAIL */\n\t\"Program version wrong\",\t\t/* 75 - EPROGMISMATCH */\n\t\"Bad procedure for program\",\t\t/* 76 - EPROCUNAVAIL */\n\n\t\"No locks available\",\t\t\t/* 77 - ENOLCK */\n\t\"Function not implemented\",\t\t/* 78 - ENOSYS */\n\t\"Inappropriate file type or format\",\t/* 79 - EFTYPE */\n\t\"Authentication error\",\t\t\t/* 80 - EAUTH */\n\t\"Need authenticator\",\t\t\t/* 81 - ENEEDAUTH */\n};\n\n/*\n * Kernel symbol name list.\n */\nstatic const struct {\n\tconst char *name;\n\tint addr;\n} nlist[] = {\n\t{ \"_boottime\",\t(int)&boottime\t},\t/* vmstat */\n\t{ \"_cnttys\",\t(int)&cnttys\t},\t/* pstat */\n\t{ \"_cp_time\",\t(int)&cp_time\t},\t/* iostat\tvmstat */\n\t{ \"_dk_busy\",\t(int)&dk_busy\t},\t/* iostat */\n\t{ \"_dk_name\",\t(int)&dk_name\t},\t/* iostat\tvmstat */\n\t{ \"_dk_ndrive\",\t(int)&dk_ndrive\t},\t/* iostat\tvmstat */\n\t{ \"_dk_unit\",\t(int)&dk_unit\t},\t/* iostat\tvmstat */\n\t{ \"_dk_bytes\",\t(int)&dk_bytes\t},\t/* iostat */\n\t{ \"_dk_xfer\",\t(int)&dk_xfer\t},\t/* iostat\tvmstat */\n\t{ \"_file\",\t(int)&file\t},\t/* pstat */\n\t{ \"_forkstat\",\t(int)&forkstat\t},\t/* vmstat */\n#ifdef UCB_METER\n\t{ \"_freemem\",\t(int)&freemem\t},\t/* vmstat */\n#endif\n\t{ \"_hz\",\t(int)&hz\t},\t/* ps */\n\t{ \"_inode\",\t(int)&inode\t},\t/* pstat */\n\t{ \"_ipc\",\t(int)&ipc\t},\t/* ps */\n\t{ \"_lbolt\",\t(int)&lbolt\t},\t/* ps */\n\t{ \"_memlock\",\t(int)&memlock\t},\t/* ps */\n\t{ \"_nchstats\",\t(int)&nchstats\t},\t/* vmstat */\n\t{ \"_nproc\",\t(int)&nproc\t},\t/* ps\t\tpstat */\n\t{ \"_nswap\",\t(int)&nswap\t},\t/* pstat */\n\t{ \"_proc\",\t(int)&proc\t},\t/* ps\t\tpstat */\n\t{ \"_runin\",\t(int)&runin\t},\t/* ps */\n\t{ \"_runout\",\t(int)&runout\t},\t/* ps */\n\t{ \"_selwait\",\t(int)&selwait\t},\t/* ps */\n\t{ \"_swapmap\",\t(int)&swapmap\t},\t/* pstat */\n\t{ \"_tk_nin\",\t(int)&tk_nin\t},\t/* iostat */\n\t{ \"_tk_nout\",\t(int)&tk_nout\t},\t/* iostat */\n\t{ \"_total\",\t(int)&total\t},\t/* vmstat */\n\t{ \"_u\",\t\t(int)&u\t\t},\t/* ps */\n#ifdef PTY_ENABLED\n\t{ \"_npty\",\t(int)&npty\t},\t/* pstat */\n\t{ \"_pt_tty\",\t(int)&pt_tty\t},\t/* pstat */\n#endif\n#ifdef UCB_METER\n\t{ \"_rate\",\t(int)&rate\t},\t/* vmstat */\n\t{ \"_sum\",\t(int)&sum\t},\t/* vmstat */\n#endif\n\t{ \"_bdevsw\",\t(int)&bdevsw\t},\t/* devupdate */\n\t{ \"_cdevsw\",\t(int)&cdevsw\t},\t/* devupdate */\n\t{ \"_nblkdev\",\t(int)&nblkdev\t},\t/* devupdate */\n\t{ \"_nchrdev\",\t(int)&nchrdev\t},\t/* devupdate */\n\t{ 0,\t\t0\t\t},\n};\n\n/*\n * ucall allows user level code to call various kernel functions.\n * Autoconfig uses it to call the probe and attach routines of the\n * various device drivers.\n */\nvoid\nucall(void)\n{\n\tstruct a {\n\t\tint priority;\n\t\tint (*routine)();\n\t\tint arg1;\n\t\tint arg2;\n\t} *uap = (struct a *)u.u_arg;\n\n\tint s;\n\n\tif (!suser())\n\t\treturn;\n\tswitch (uap->priority) {\n\tcase 0:\n\t\ts = spl0();\n\t\tbreak;\n\tdefault:\n\t\ts = splhigh();\n\t\tbreak;\n\t}\n\tu.u_rval = (*uap->routine)(uap->arg1, uap->arg2);\n\tsplx(s);\n}\n\n/*\n * Fetch the word at addr from flash memory or i/o port.\n * This system call is required on PIC32 because in user mode\n * the access to flash memory region is not allowed.\n */\nvoid\nufetch(void)\n{\n\t/* Check root privileges */\n\tif (!suser())\n\t\treturn;\n\n\t/* XXX Not implemented */\n\tu.u_error = EOPNOTSUPP;\n\treturn;\n}\n\n/*\n * Store the word at addr of i/o port.\n */\nvoid\nustore(void)\n{\n\t/* Check root privileges */\n\tif (!suser())\n\t\treturn;\n\n\t/* XXX Not implemented */\n\tu.u_error = EOPNOTSUPP;\n\treturn;\n}\n\nvoid\nsc_msec(void)\n{\n\t/* XXX Not implemented */\n\tu.u_rval = 0;\n}\n\n/*\n * This was moved here when the TMSCP portion was added.  At that time it\n * became (even more) system specific and didn't belong in kern_sysctl.c\n */\nint\ncpu_sysctl(int *name, u_int namelen, void *oldp, size_t *oldlenp, void *newp,\n    size_t newlen)\n{\n\tint i, khz;\n\tdev_t dev;\n\n\t/* All sysctl names at this level except mpu are terminal. */\n\tswitch (name[0]) {\n\tcase CPU_CONSDEV:\n\t\tif (namelen != 1)\n\t\t\treturn ENOTDIR;\n\t\tdev = makedev(CONS_MAJOR, CONS_MINOR);\n\t\treturn sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof dev);\n#if NTMSCP > 0\n\tcase CPU_TMSCP:\n\t\tif (namelen != 2)\n\t\t\treturn ENOTDIR;\n\t\tswitch (name[1]) {\n\t\tcase TMSCP_CACHE:\n\t\t\treturn sysctl_int(oldp, oldlenp, newp, newlen,\n\t\t\t    &tmscpcache);\n\t\tcase TMSCP_PRINTF:\n\t\t\treturn sysctl_int(oldp, oldlenp, newp, newlen,\n\t\t\t    &tmscpprintf);\n\t\tdefault:\n\t\t}\n#endif\n\tcase CPU_ERRMSG:\n\t\tif (namelen != 2)\n\t\t\treturn ENOTDIR;\n\t\tif (name[1] < 1 ||\n\t\t    name[1] >= sizeof(errlist) / sizeof(errlist[0]))\n\t\t\treturn EOPNOTSUPP;\n\t\treturn sysctl_string(oldp, oldlenp, 0, 0,\n\t\t    (char *)errlist[name[1]], 1 + strlen(errlist[name[1]]));\n\n\tcase CPU_NLIST:\n\t\tfor (i = 0; nlist[i].name; i++) {\n\t\t\tif (strncmp(newp, nlist[i].name, newlen) == 0) {\n\t\t\t\tint addr = nlist[i].addr;\n\t\t\t\tif (!oldp)\n\t\t\t\t\treturn 0;\n\t\t\t\tif (*oldlenp < sizeof(int))\n\t\t\t\t\treturn ENOMEM;\n\t\t\t\t*oldlenp = sizeof(int);\n\t\t\t\treturn copyout((caddr_t)&addr, (caddr_t)oldp,\n\t\t\t\t    sizeof(int));\n\t\t\t}\n\t\t}\n\t\treturn EOPNOTSUPP;\n\n\tcase CPU_FREQ_KHZ:\n\t\tif (namelen != 1)\n\t\t\treturn ENOTDIR;\n\t\tkhz = CPU_KHZ;\n\t\treturn sysctl_rdstruct(oldp, oldlenp, newp, &khz, sizeof khz);\n\n\tcase CPU_BUS_KHZ:\n\t\tif (namelen != 1)\n\t\t\treturn ENOTDIR;\n\t\tkhz = BUS_KHZ;\n\t\treturn sysctl_rdstruct(oldp, oldlenp, newp, &khz, sizeof khz);\n\n\tcase CPU_MPU:\n\t\treturn mpu_sysctl(name + 1, namelen - 1, oldp, oldlenp, newp,\n\t\t    newlen);\n\n\tdefault:\n\t\treturn EOPNOTSUPP;\n\t}\n\t/* NOTREACHED */\n}\n"
  },
  {
    "path": "sys/arch/stm32/stm32/systick.c",
    "content": "/*\n * Copyright (c) 2022 Christopher Hettrick <chris@structfoo.com>\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include <sys/param.h>\n#include <sys/signalvar.h>\n#include <sys/systm.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/conf.h>\n#include <sys/tty.h>\n\n#include <machine/frame.h>\n\n#include <stm32/hal/stm32f4xx_hal.h>\n\nvoid\nSysTick_Handler(void)\n{\n__asm volatile (\n\"\t.syntax\tunified\t\t\\n\\t\"\n\"\t.thumb\t\t\t\\n\\t\"\n\n#ifdef __thumb2__\n\"\ttst\tlr, #0x4\t\\n\\t\"\t/* Test bit 2 (SPSEL) of EXC_RETURN. */\n\"\tite\teq\t\t\\n\\t\"\t/* Came from user or kernel mode? */\n\"\tmrseq\tr0, MSP\t\t\\n\\t\"\t/* Kernel mode; stack frame on MSP. */\n\"\tmrsne\tr0, PSP\t\t\\n\\t\"\t/* User mode; stack frame on PSP. */\n\"\tb\tsystick\t\t\\n\\t\"\t/* Call systick(frame); */\n#else /* __thumb__ */\n\"\tmovs\tr0, #0x4\t\\n\\t\"\t/* Test bit 2 (SPSEL).. */\n\"\tmov\tr1, lr\t\t\\n\\t\"\t/*   of EXC_RETURN in lr. */\n\"\ttst\tr0, r1\t\t\\n\\t\"\t/* Came from user or kernel mode? */\n\"\tbeq\t1f\t\t\\n\\t\"\n\"\tmrs\tr0, PSP\t\t\\n\\t\"\t/* User mode; stack frame on PSP. */\n\"\tldr\tr1, =systick\t\\n\\t\"\t/* Call systick(frame); */\n\"\tbx\tr1\t\t\\n\\t\"\n\"1:\tmrs\tr0, MSP\t\t\\n\\t\"\t/* Kernel mode; stack frame on MSP. */\n\"\tldr\tr1, =systick\t\\n\\t\"\t/* Call systick(frame); */\n\"\tbx\tr1\t\t\\n\\t\"\n#endif\n);\n}\n\n/*\n * Default system time base for Cortex-M.\n * Internal hardware SysTick interrupt every 1 millisecond.\n */\nvoid\nsystick(struct clockframe *frame)\n{\n\tHAL_IncTick();\t\t/* Required for HAL driver subsystems. */\n\n\thardclock((caddr_t)frame->cf_pc, frame->cf_psr);\n}\n"
  },
  {
    "path": "sys/conf/newvers.sh",
    "content": "#!/bin/sh -\n#\n# Copyright (c) 1980 Regents of the University of California.\n# All rights reserved.  The Berkeley software License Agreement\n# specifies the terms and conditions for redistribution.\n#\n\n# Things which need version number upgrades:\n#\tsys/conf/newvers.sh:\n#\t\tOSR\n#\tsys/sys/param.h:\n#\t\tDiscoBSD\n#\t\tDiscoBSD_X_X\n#\tshare/mk/sys.mk:\n#\t\tOSMAJOR\n#\t\tOSMINOR\n#\n# After a release, move to S=\"-current\" and keep same version number.\n# Before a release, move to S=\"-beta\" and increment version number.\n# For a release, move to S=\"\" and keep same version number.\n\nOST=\"DiscoBSD\"\nOSR=\"2.6\"\n\nS=\"-current\"\n#S=\"-beta\"\n#S=\"\"\n\nif [ ! -r .compileversion -o ! -s .compileversion ]\nthen\n    echo 0 >.compileversion\nfi\nCV=`cat .compileversion`\nCV=`expr $CV + 1`\n\nif [ ! -r .oldversion -o ! -s .oldversion ]\nthen\n    echo 0 >.oldversion\nfi\nOV=`cat .oldversion`\n\nGITREV=`git rev-list HEAD --count`\nGITDIR=`git rev-parse --show-toplevel`\n\nif [ \"x$GITREV\" = \"x\" ]\nthen\n    GITREV=\"Untracked\"\nfi\n\nif [ \"x$GITREV\" != \"x$OV\" ]\nthen\n    CV=1\nfi\necho $CV >.compileversion\necho $GITREV >.oldversion\n\nH=`hostname`\nD=${PWD#$GITDIR}\nID=`basename \"${D}\"`\n\necho $GITREV $CV ${USER-root} $H $D $OST $OSR $ID $S| \\\nawk '{\n    gitrev = $1;\n    cv = $2;\n    user = $3;\n    host = $4;\n    dir = $5;\n    date = strftime();\n    ost = $6;\n    osr = $7;\n    id = toupper($8);\n    status = $9;\n    printf \"const char version[] = \\\"%s %s%s (%s) #%d %s: %s\\\\n\", \\\n        ost, osr, status, id, cv, gitrev, date;\n    printf \"     %s@%s:%s\\\\n\\\";\\n\", user, host, dir;\n    printf \"const char ostype[] = \\\"%s\\\";\\n\", ost;\n    printf \"const char osversion[] = \\\"%s#%d\\\";\\n\", id, cv;\n    printf \"const char osrelease[] = \\\"%s\\\";\\n\", osr;\n}'\n"
  },
  {
    "path": "sys/dev/cons.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)cons.c\t1.3 (2.11BSD GTE) 1997/4/25\n */\n\n/*\n * Console driver.\n */\n\n#include <sys/param.h>\n#include <sys/conf.h>\n#include <sys/user.h>\n#include <sys/ioctl.h>\n#include <sys/tty.h>\n#include <sys/systm.h>\n\nstruct tty cnttys[1];\n\nint\ncnopen(dev_t cn, int flag, int mode)\n{\n\tdev_t dev = makedev(CONS_MAJOR, CONS_MINOR);\n\n\treturn cdevsw[CONS_MAJOR].d_open(dev, flag, mode);\n}\n\nint\ncnclose(dev_t cn, int flag, int mode)\n{\n\tdev_t dev = makedev(CONS_MAJOR, CONS_MINOR);\n\n\treturn cdevsw[CONS_MAJOR].d_close(dev, flag, mode);\n}\n\nint\ncnread(dev_t cn, struct uio *uio, int flag)\n{\n\tdev_t dev = makedev(CONS_MAJOR, CONS_MINOR);\n\n\treturn cdevsw[CONS_MAJOR].d_read(dev, uio, flag);\n}\n\nint\ncnwrite(dev_t cn, struct uio *uio, int flag)\n{\n\tdev_t dev = makedev(CONS_MAJOR, CONS_MINOR);\n\n\treturn cdevsw[CONS_MAJOR].d_write(dev, uio, flag);\n}\n\nint\ncnselect(dev_t cn, int rw)\n{\n\tdev_t dev = makedev(CONS_MAJOR, CONS_MINOR);\n\n\treturn cdevsw[CONS_MAJOR].d_select(dev, rw);\n}\n\nint\ncnioctl(dev_t cn, u_int cmd, caddr_t addr, int flag)\n{\n\tdev_t dev = makedev(CONS_MAJOR, CONS_MINOR);\n\n\treturn cdevsw[CONS_MAJOR].d_ioctl(dev, cmd, addr, flag);\n}\n\n/*\n * Put a symbol on console terminal.\n */\nvoid\ncnputc(char c)\n{\n\tif (cdevsw[CONS_MAJOR].r_write) {\n\t\tdev_t dev = makedev(CONS_MAJOR, CONS_MINOR);\n\n\t\tcdevsw[CONS_MAJOR].r_write(dev, c);\n\t} else {\n\t\tputc(c, &cdevsw[CONS_MAJOR].d_ttys[CONS_MINOR].t_outq);\n\t\tttstart(&cdevsw[CONS_MAJOR].d_ttys[CONS_MINOR]);\n\t\tttyflush(&cdevsw[CONS_MAJOR].d_ttys[CONS_MINOR], 0);\n\t}\n\n\tif (c == '\\n')\n\t\tcnputc('\\r');\n}\n\n/*\n * Receive a symbol from console terminal.\n */\nint\ncngetc(void)\n{\n\tif (cdevsw[CONS_MAJOR].r_read) {\n\t\tdev_t dev = makedev(CONS_MAJOR, CONS_MINOR);\n\n\t\treturn cdevsw[CONS_MAJOR].r_read(dev);\n\t} else {\n\t\treturn getc(&cdevsw[CONS_MAJOR].d_ttys[CONS_MINOR].t_rawq);\n\t}\n}\n"
  },
  {
    "path": "sys/dev/mem.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)mem.c\t1.3 (2.11BSD GTE) 1996/5/15\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/conf.h>\n#include <sys/systm.h>\n#include <sys/uio.h>\n\nvoid\nkmemdev(void)\n{\n\tu.u_rval = makedev(MEM_MAJOR, 1);\n}\n\n/*\n * Read/write routine for /dev/mem family.\n */\nint\nmmrw(dev_t dev, struct uio *uio, int flag)\n{\n\tstruct iovec *iov;\n\tint error = 0;\n\tu_int c;\n\tcaddr_t addr;\n\n#if 0\n\tprintf(\"mmrw(dev=%u, len=%u, flag=%d)\\n\",\n\t    dev, uio->uio_iov->iov_len, flag);\n#endif\n\twhile (uio->uio_resid && error == 0) {\n\t\tiov = uio->uio_iov;\n\t\tif (iov->iov_len == 0) {\n\t\t\tuio->uio_iov++;\n\t\t\tuio->uio_iovcnt--;\n\t\t\tif (uio->uio_iovcnt < 0)\n\t\t\t\tpanic(\"mmrw\");\n\t\t\tcontinue;\n\t\t}\n\t\tswitch (minor(dev)) {\n\t\tcase 0:\t/* minor device 0 is physical memory (/dev/mem) */\n\t\tcase 1:\t/* minor device 1 is kernel memory (/dev/kmem) */\n\t\t\taddr = (caddr_t)uio->uio_offset;\n\t\t\tif ((badkaddr(addr) && baduaddr(addr)) ||\n\t\t\t    (badkaddr(addr + iov->iov_len - 1) &&\n\t\t\t     baduaddr(addr + iov->iov_len - 1))) {\n\t\t\t\terror = EFAULT;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\terror = uiomove(addr, iov->iov_len, uio);\n\t\t\tbreak;\n\t\tcase 2:\t/* minor device 2 is EOF/RATHOLE (/dev/null) */\n\t\t\tif (uio->uio_rw == UIO_READ)\n\t\t\t\treturn 0;\n\t\t\tc = iov->iov_len;\n\t\t\tiov->iov_base += c;\n\t\t\tiov->iov_len -= c;\n\t\t\tuio->uio_offset += c;\n\t\t\tuio->uio_resid -= c;\n\t\t\tbreak;\n\t\tcase 3:\t/* minor device 3 is ZERO (/dev/zero) */\n\t\t\tif (uio->uio_rw == UIO_WRITE)\n\t\t\t\treturn EIO;\n\t\t\tc = iov->iov_len;\n\t\t\tbzero(iov->iov_base, c);\n\t\t\tiov->iov_base += c;\n\t\t\tiov->iov_len -= c;\n\t\t\tuio->uio_offset += c;\n\t\t\tuio->uio_resid -= c;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treturn EINVAL;\n\t\t}\n\t}\n\treturn error;\n}\n"
  },
  {
    "path": "sys/dev/swap.c",
    "content": "/*\n * Simple proxy for swap partition.\n *\n * Forwards requests for /dev/swap on to the\n * device specified by swapdev.\n */\n\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/buf.h>\n#include <sys/errno.h>\n#include <sys/dk.h>\n#include <sys/uio.h>\n#include <sys/conf.h>\n#include <sys/fcntl.h>\n#include <sys/map.h>\n#include <sys/swap.h>\n#include <sys/disk.h>\n\n#ifndef NTMP\n#define NTMP 3\n#endif\n\nextern struct buf *getnewbuf(void);\n\nstatic u_int\ttdsize[NTMP];\t\t/* Number of blocks allocated */\nstatic u_int\ttdstart[NTMP];\t\t/* Starting location in map */\n\nextern dev_t\tswapdev;\n\nextern int\tphysio(void (*strat)(struct buf *),\n    struct buf *bp, dev_t dev, int rw, struct uio *uio);\n\nextern void\tswap(size_t blkno, size_t coreaddr, int count, int rdflg);\n\nint\nswopen(dev_t dev, int mode, int flag)\n{\n\tint unit = minor(dev);\n\n\tif (unit == 64)\n\t\treturn bdevsw[major(swapdev)].d_open(swapdev, mode, flag);\n\n\tif (unit >= NTMP)\n\t\treturn ENODEV;\n\n\treturn 0;\n}\n\nint\nswclose(dev_t dev, int mode, int flag)\n{\n\tint unit = minor(dev);\n\n\tif (unit == 64)\n\t\treturn bdevsw[major(swapdev)].d_close(swapdev, mode, flag);\n\n\tif (unit >= NTMP)\n\t\treturn ENODEV;\n\n\treturn 0;\n}\n\ndaddr_t\nswsize(dev_t dev)\n{\n\tint unit = minor(dev);\n\n\tif (unit == 64)\n\t\treturn bdevsw[major(dev)].d_psize(dev);\n\n\tif (unit >= NTMP)\n\t\treturn ENODEV;\n\n\treturn tdsize[unit];\n}\n\nint\nswcopen(dev_t dev, int mode, int flag)\n{\n\tint unit = minor(dev);\n\n\tif (unit >= NTMP) {\n\t\tprintf(\"temp%d: Device number out of range\\n\", minor(dev));\n\t\treturn ENODEV;\n\t}\n\n\treturn 0;\n}\n\nint\nswcclose(dev_t dev, int mode, int flag)\n{\n\tint unit = minor(dev);\n\n\tif (unit >= NTMP)\n\t\treturn ENODEV;\n\n\treturn 0;\n}\n\nint\nswcread(dev_t dev, struct uio *uio, int flag)\n{\n\tu_int\t\t block;\n\tu_int\t\t boff;\n\tstruct buf\t*bp;\n\tu_int\t\t rsize;\n\tu_int\t\t rlen;\n\n\tint unit = minor(dev);\n\n\tif (unit >= NTMP) {\n\t\tprintf(\"temp%d: Device number out of range\\n\", minor(dev));\n\t\treturn ENODEV;\n\t}\n\n\tif (tdstart[unit] == 0)\n\t\treturn EIO;\n\n\tif (uio->uio_offset >= tdsize[unit] << 10)\n\t\treturn EIO;\n\n\tbp = getnewbuf();\n\n\tblock = uio->uio_offset >> 10;\n\tboff = uio->uio_offset - (block << 10);\n\n\trsize = DEV_BSIZE - boff;\n\trlen = uio->uio_iov->iov_len;\n\n\twhile ((rlen > 0) && (block < tdsize[unit])) {\n\t\tswap(tdstart[unit] + block, (size_t)bp->b_addr,\n\t\t    DEV_BSIZE, B_READ);\n\t\tuiomove(bp->b_addr + boff, rsize, uio);\n\t\tboff = 0;\n\t\tblock++;\n\t\trlen -= rsize;\n\t\trsize = rlen >= DEV_BSIZE ? DEV_BSIZE : rlen;\n\t}\n\n\tbrelse(bp);\n\n\treturn 0;\n}\n\nint\nswcwrite(dev_t dev, struct uio *uio, int flag)\n{\n\tu_int\t\t block;\n\tu_int\t\t boff;\n\tstruct buf\t*bp;\n\tu_int\t\t rsize;\n\tu_int\t\t rlen;\n\n\tint unit = minor(dev);\n\n\tif (unit >= NTMP) {\n\t\tprintf(\"temp%d: Device number out of range\\n\", minor(dev));\n\t\treturn ENODEV;\n\t}\n\n\tif (tdstart[unit] == 0) {\n\t\tprintf(\"temp%d: attempt to write with no allocation\\n\",\n\t\t    unit);\n\t\treturn EIO;\n\t}\n\n\tif (uio->uio_offset >= tdsize[unit] << 10) {\n\t\tprintf(\"temp%d: attempt to write past end of allocation\\n\",\n\t\t    unit);\n\t\treturn EIO;\n\t}\n\n\tbp = getnewbuf();\n\n\tblock = uio->uio_offset >> 10;\n\tboff = uio->uio_offset - (block << 10);\n\n\trsize = DEV_BSIZE - boff;\n\trlen = uio->uio_iov->iov_len;\n\n\twhile (rlen > 0 && block < tdsize[unit]) {\n\t\tuiomove(bp->b_addr + boff, rsize, uio);\n\t\tswap(tdstart[unit] + block, (size_t)bp->b_addr,\n\t\t    DEV_BSIZE, B_WRITE);\n\t\tboff = 0;\n\t\tblock++;\n\t\trlen -= rsize;\n\t\trsize = rlen >= DEV_BSIZE ? DEV_BSIZE : rlen;\n\t}\n\n\tbrelse(bp);\n\n\treturn 0;\n}\n\nint\nswcioctl(dev_t dev, u_int cmd, caddr_t addr, int flag)\n{\n\tu_int\t\t*uival;\n\toff_t\t\t*offtval;\n\n\tint unit = minor(dev);\n\n\tif (unit >= NTMP) {\n\t\tprintf(\"temp%d: Device number out of range\\n\", minor(dev));\n\t\treturn ENODEV;\n\t}\n\n\tuival = (u_int *)addr;\n\tofftval = (off_t *)addr;\n\n\tswitch (cmd) {\n\tcase TFALLOC:\n\t\tif (tdstart[unit] > 0)\n\t\t\tmfree(swapmap, tdsize[unit], tdstart[unit]);\n\n\t\tif (*offtval > 0) {\n\t\t\ttdstart[unit] = malloc(swapmap, *offtval);\n\t\t\tif (tdstart[unit] > 0) {\n\t\t\t\ttdsize[unit] = *offtval;\n\t\t\t\t/* printf(\"temp%d: allocated %lu blocks\\n\",\n\t\t\t\t    unit, tdsize[unit]); */\n\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t\t*offtval = 0;\n\t\t\tprintf(\"temp%d: failed to allocate %lu blocks\\n\",\n\t\t\t    tdsize[unit]);\n\n\t\t\treturn 0;\n\t\t} else {\n\t\t\t/* printf(\"temp%d: released allocation\\n\", unit); */\n\t\t}\n\t\tbreak;\n\n\tcase DIOCGETMEDIASIZE:\n\t\t*uival = swsize(dev);\n\t\tbreak;\n\t}\n\n\treturn EINVAL;\n}\n\nvoid\nswstrategy(struct buf *bp)\n{\n\tint unit = minor(bp->b_dev);\n\n\tif (unit == 64) {\n\t\tdev_t od = bp->b_dev;\n\t\tbp->b_dev = swapdev;\n\t\tbdevsw[major(swapdev)].d_strategy(bp);\n\t\tbp->b_dev = od;\n\t} else {\n\t\tif (unit >= NTMP)\n\t\t\treturn;\n\n\t\tif (tdstart[unit] == 0) {\n\t\t\tprintf(\"swap%d: attempt to access unallocated device\\n\",\n\t\t\t    unit);\n\t\t\treturn;\n\t\t}\n\n\t\tif (bp->b_blkno > tdsize[unit]) {\n\t\t\tprintf(\"swap%d: attempt to access past end of allocation\\n\",\n\t\t\t    unit);\n\t\t\treturn;\n\t\t}\n\n\t\tif (bp->b_flags & B_READ) {\n\t\t\tswap(tdstart[unit] + bp->b_blkno, (size_t)bp->b_addr,\n\t\t\t    bp->b_bcount, B_READ);\n\t\t} else {\n\t\t\tswap(tdstart[unit] + bp->b_blkno, (size_t)bp->b_addr,\n\t\t\t    bp->b_bcount, B_WRITE);\n\t\t}\n\n\t\tbiodone(bp);\n\t}\n}\n"
  },
  {
    "path": "sys/kern/exec_aout.c",
    "content": "#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/map.h>\n#include <sys/inode.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/buf.h>\n#include <sys/namei.h>\n#include <sys/fs.h>\n#include <sys/mount.h>\n#include <sys/file.h>\n#include <sys/resource.h>\n#include <sys/exec.h>\n#include <sys/exec_aout.h>\n#include <sys/dir.h>\n#include <sys/uio.h>\n#include <machine/debug.h>\n\nint exec_aout_check(struct exec_params *epp)\n{\n    int error;\n\n    DEBUG(\"\\texec_aout_check(): start\\n\");\n\n    if (epp->hdr_len < sizeof(struct exec)) {\n        DEBUG(\"\\texec_aout_check(): error: wrong header length\\n\");\n        DEBUG(\"\\texec_aout_check(): end\\n\");\n        return ENOEXEC;\n    }\n    if (!(N_GETMID(epp->hdr.aout) == MID_ZERO &&\n          N_GETFLAG(epp->hdr.aout) == 0)) {\n        DEBUG(\"\\texec_aout_check(): error: not an a.out\\n\");\n        DEBUG(\"\\texec_aout_check(): end\\n\");\n        return ENOEXEC;\n    }\n\n    switch (N_GETMAGIC(epp->hdr.aout)) {\n    case OMAGIC:\n        epp->hdr.aout.a_data += epp->hdr.aout.a_text;\n        epp->hdr.aout.a_text = 0;\n        break;\n    default:\n        printf(\"Bad a.out magic = %0o\\n\", N_GETMAGIC(epp->hdr.aout));\n        return ENOEXEC;\n    }\n\n    /*\n     * Save arglist\n     */\n    exec_save_args(epp);\n\n    DEBUG(\"\\texec_aout_check(): exec file header\\n\");\n    /* magic number */\n    DEBUG(\"\\texec_aout_check(): a_midmag  = %#x\\n\", epp->hdr.aout.a_midmag);\n    /* size of text segment */\n    DEBUG(\"\\texec_aout_check(): a_text    = %d\\n\",  epp->hdr.aout.a_text);\n    /* size of initialized data */\n    DEBUG(\"\\texec_aout_check(): a_data    = %d\\n\",  epp->hdr.aout.a_data);\n    /* size of uninitialized data */\n    DEBUG(\"\\texec_aout_check(): a_bss     = %d\\n\",  epp->hdr.aout.a_bss);\n    /* size of text relocation info */\n    DEBUG(\"\\texec_aout_check(): a_reltext = %d\\n\",  epp->hdr.aout.a_reltext);\n    /* size of data relocation info */\n    DEBUG(\"\\texec_aout_check(): a_reldata = %d\\n\",  epp->hdr.aout.a_reldata);\n    /* size of symbol table */\n    DEBUG(\"\\texec_aout_check(): a_syms    = %d\\n\",  epp->hdr.aout.a_syms);\n    /* entry point */\n    DEBUG(\"\\texec_aout_check(): a_entry   = %#x\\n\", epp->hdr.aout.a_entry);\n\n    /*\n     * Set up memory allocation\n     */\n    epp->text.vaddr = epp->heap.vaddr = NO_ADDR;\n    epp->text.len = epp->heap.len = 0;\n\n    epp->data.vaddr = (caddr_t)__user_data_start;\n    epp->data.len = epp->hdr.aout.a_data;\n    epp->bss.vaddr = epp->data.vaddr + epp->data.len;\n    epp->bss.len = epp->hdr.aout.a_bss;\n    epp->heap.vaddr = epp->bss.vaddr + epp->bss.len;\n    epp->heap.len = 0;\n    epp->stack.len = SSIZE + roundup(epp->argbc + epp->envbc, NBPW) + (epp->argc + epp->envc+4)*NBPW;\n    epp->stack.vaddr = (caddr_t)__user_data_end - epp->stack.len;\n\n    /*\n     * Allocate core at this point, committed to the new image.\n     * TODO: What to do for errors?\n     */\n    exec_estab(epp);\n\n    /* read in text and data */\n    DEBUG(\"\\texec_aout_check(): reading a.out image\\n\");\n    error = rdwri (UIO_READ, epp->ip,\n               (caddr_t)epp->data.vaddr, epp->hdr.aout.a_data,\n               sizeof(struct exec) + epp->hdr.aout.a_text, IO_UNIT, 0);\n    if (error)\n        DEBUG(\"\\texec_aout_check(): error: read image returned: %d\\n\", error);\n    if (error) {\n        /*\n         * Error - all is lost, when the old image is possible corrupt\n         * and we could not load a new.\n         */\n        psignal (u.u_procp, SIGSEGV);\n        return error;\n    }\n\n    exec_clear(epp);\n    exec_setupstack(epp->hdr.aout.a_entry, epp);\n\n    DEBUG(\"\\texec_aout_check(): end\\n\");\n\n    return 0;\n}\n"
  },
  {
    "path": "sys/kern/exec_conf.c",
    "content": "/*\n * Copyright (c) 1993, 1994 Christopher G. Demetriou\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *      This product includes software developed by Christopher G. Demetriou.\n * 4. The name of the author may not be used to endorse or promote products\n *    derived from this software without specific prior written permission\n *\n * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\n * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\n * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\n * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\n * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include <sys/param.h>\n#include <sys/inode.h>\n#include <sys/exec.h>\n\nint exec_script_check(struct exec_params *epp);\nint exec_aout_check(struct exec_params *epp);\nint exec_elf_check(struct exec_params *epp);\n\nconst struct execsw execsw[] = {\n    { exec_aout_check,      \"a.out\" },      /* a.out binaries */\n    { exec_elf_check,       \"elf\" },        /* 32bit ELF bins */\n    { exec_script_check,    \"script\" },     /* shell scripts */\n };\nint nexecs = (sizeof(execsw) / sizeof(*execsw));\nint exec_maxhdrsz;\n"
  },
  {
    "path": "sys/kern/exec_elf.c",
    "content": "/*-\n * Copyright (c) 1994 The NetBSD Foundation, Inc.\n * All rights reserved.\n *\n * This code is derived from software contributed to The NetBSD Foundation\n * by Christos Zoulas.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *  This product includes software developed by the NetBSD\n *  Foundation, Inc. and its contributors.\n * 4. Neither the name of The NetBSD Foundation nor the names of its\n *    contributors may be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS\n * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\n * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 1996 Christopher G. Demetriou\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. The name of the author may not be used to endorse or promote products\n *    derived from this software without specific prior written permission\n *\n * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\n * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\n * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\n * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\n * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\n * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/kernel.h>\n#include <sys/map.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/inode.h>\n#include <sys/namei.h>\n#include <sys/exec.h>\n#include <sys/exec_elf.h>\n#include <sys/fcntl.h>\n#include <sys/signalvar.h>\n#include <sys/mount.h>\n#include <sys/stat.h>\n#include <machine/debug.h>\n\nextern char sigcode[], esigcode[];\n\n/* round up and down to page boundaries. */\n#define ELF_ROUND(a, b)     (((a) + (b) - 1) & ~((b) - 1))\n#define ELF_TRUNC(a, b)     ((a) & ~((b) - 1))\n\n/*\n * elf_check(): Prepare an Elf binary's exec package\n *\n * First, set of the various offsets/lengths in the exec package.\n *\n * Then, mark the text image busy (so it can be demand paged) or error\n * out if this is not possible.  Finally, set up vmcmds for the\n * text, data, bss, and stack segments.\n */\nint\nexec_elf_check(struct exec_params *epp)\n{\n    struct elf_phdr *ph;\n    int error, i, phsize;\n\n    const char elfident[] = {ELFMAG0, ELFMAG1, ELFMAG2, ELFMAG3,\n                 ELFCLASS32, ELFDATA2LSB, EV_CURRENT, ELFOSABI_SYSV, 0};\n\n    DEBUG(\"\\texec_elf_check(): start\\n\");\n\n    /*\n     * Check that this is an ELF file that we can handle,\n     * and do some sanity checks on the header\n     */\n    if (epp->hdr_len < sizeof(struct elf_ehdr)) {\n        DEBUG(\"\\texec_elf_check(): error: wrong header length\\n\");\n        DEBUG(\"\\texec_elf_check(): end\\n\");\n        return ENOEXEC;\n    }\n    for (i = 0; i < sizeof elfident; i++) {\n        if (epp->hdr.elf.e_ident[i] !=  elfident[i]) {\n            DEBUG(\"\\texec_elf_check(): error: not an elf\\n\");\n            DEBUG(\"\\texec_elf_check(): end\\n\");\n            return ENOEXEC;\n        }\n    }\n    if (epp->hdr.elf.e_type != ET_EXEC)\n        return ENOEXEC;\n    if (epp->hdr.elf.e_machine != ELF32_MACHDEP_ID || epp->hdr.elf.e_version != EV_CURRENT)\n        return ENOEXEC;\n    if (epp->hdr.elf.e_phentsize != sizeof(struct elf_phdr) || epp->hdr.elf.e_phoff == 0 || epp->hdr.elf.e_phnum == 0)\n        return ENOEXEC;\n    if (epp->hdr.elf.e_shnum == 0 || epp->hdr.elf.e_shentsize != sizeof(struct elf_shdr))\n        return ENOEXEC;\n\n    /*\n     * Read program headers\n     */\n    phsize = epp->hdr.elf.e_phnum * sizeof(struct elf_phdr);\n    ph = exec_alloc(phsize, NBPW, epp);\n    if (ph == NULL) {\n        printf(\"can't alloc ph[] sz=%d\\n\", phsize);\n        return ENOEXEC;\n    }\n    if ((error = rdwri(UIO_READ, epp->ip, (caddr_t)ph, phsize, epp->hdr.elf.e_phoff, IO_UNIT, 0)) != 0)\n        return ENOEXEC;\n\n    epp->text.len = epp->data.len = epp->bss.len = epp->stack.len = epp->heap.len = 0;\n    epp->text.vaddr = epp->data.vaddr = epp->bss.vaddr = epp->stack.vaddr = epp->heap.vaddr = NO_ADDR;\n\n    if (epp->hdr.elf.e_phnum == 1 && ph[0].p_type == PT_LOAD && ph[0].p_flags == (PF_R|PF_W|PF_X)) {\n        /*\n         * In the simple a.out type link, in elf format, there is only\n         * one loadable segment that is RWE containing everything\n         * Here we fix the memory allocation, and we are done.\n         */\n        epp->data.vaddr = (caddr_t)ph[0].p_vaddr;\n        epp->data.len = ph[0].p_memsz;\n        epp->heap.vaddr = (caddr_t)ph[0].p_vaddr + ph[0].p_memsz;\n        epp->heap.len = 0;\n        epp->stack.len = SSIZE + epp->argbc + epp->envbc + (epp->argc+epp->envc+4)*NBPW;\n        epp->stack.vaddr = (caddr_t)__user_data_end - epp->stack.len;\n\n        /*\n         * We assume .bss is the different between the memory data\n         * section size and the file size.\n         */\n        epp->bss.vaddr = epp->data.vaddr + ph[0].p_filesz;\n        epp->bss.len = ph[0].p_memsz - ph[0].p_filesz;\n        epp->data.len = epp->bss.vaddr - epp->data.vaddr;\n    } else {\n        /*\n         * At the current moment we don't handle anything else\n         * The rest of the code is implemented as need arise.\n         */\n        return ENOEXEC;\n    }\n\n    /*\n     * Save arglist\n     */\n    exec_save_args(epp);\n\n    /*\n     * Establish memory\n     */\n    if ((error = exec_estab(epp)) != 0)\n        return error;\n\n    /*\n     * Now load the program sections into memory\n     */\n    for (i = 0; i < epp->hdr.elf.e_phnum; i++) {\n        if (ph[i].p_type != PT_LOAD)\n            continue;\n        /*\n         * Sanity check that the load is to our intended address space.\n         */\n        if (!((epp->text.vaddr != NO_ADDR\n               && ((caddr_t)ph[i].p_vaddr >= epp->text.vaddr\n                   && (caddr_t)ph[i].p_vaddr + ph[i].p_filesz <= epp->text.vaddr + epp->text.len))\n              || (epp->data.vaddr != NO_ADDR\n                  && (caddr_t)ph[i].p_vaddr >= epp->data.vaddr\n                  && (caddr_t)ph[i].p_vaddr + ph[i].p_filesz <= epp->data.vaddr + epp->data.len))\n            || ph[i].p_filesz >= ph[i].p_memsz || ph[i].p_filesz <= 0)\n                return ENOEXEC;\n\n        error = rdwri(UIO_READ, epp->ip, (caddr_t)ph[i].p_vaddr, ph[i].p_filesz, ph[i].p_offset, IO_UNIT, 0);\n    }\n\n    exec_clear(epp);\n    exec_setupstack(epp->hdr.elf.e_entry, epp);\n\n    DEBUG(\"\\texec_elf_check(): end\\n\");\n\n    return 0;\n}\n"
  },
  {
    "path": "sys/kern/exec_script.c",
    "content": "#include <sys/param.h>\n#include <sys/inode.h>\n#include <sys/dir.h>\n#include <sys/namei.h>\n#include <sys/exec.h>\n#include <sys/user.h>\n#include <sys/systm.h>\n#include <machine/debug.h>\n\nint\nexec_script_check(struct exec_params *epp)\n{\n    char *cp;\n    struct nameidata nd;\n    struct nameidata *ndp;\n    int error;\n    struct inode *ip = 0;\n\n    DEBUG(\"\\texec_script_check(): start\\n\");\n\n    /*\n     * We come here with the first line of the executable\n     * script file.\n     * Check is to see if it starts with the magic marker:  #!\n     */\n    if (epp->hdr.sh[0] != '#' || epp->hdr.sh[1] != '!' || epp->sh.interpreted)\n        return ENOEXEC;\n    epp->sh.interpreted = 1;\n\n    /*\n     * If setuid/gid scripts were to be disallowed this is where it would\n     * have to be done.\n     * u.u_uid = uid;\n     * u.u_gid = u_groups[0];\n     */\n\n    /*\n     * The first line of the text file\n     * should be one line on the format:\n     * #! <interpreter-name> <interpreter-argument>\\n\n     */\n    cp = &epp->hdr.sh[2];\n    while (cp < &epp->hdr.sh[MIN(epp->hdr_len, SHSIZE)]) {\n        if (*cp == '\\t')\n            *cp = ' ';\n        else if (*cp == '\\n') {\n            *cp = '\\0';\n            break;\n        }\n        cp++;\n    }\n    if (cp == &epp->hdr.sh[MIN(epp->hdr_len, SHSIZE)])\n        return ENOEXEC;\n\n    /*\n     * Pick up script interpreter file name\n     */\n    cp = &epp->hdr.sh[2];\n    while (*cp == ' ')\n        cp++;\n    if (!*cp)\n        return ENOEXEC;\n    bzero(&nd, sizeof nd);\n    ndp = &nd;\n    ndp->ni_dirp = cp;\n    while (*cp && *cp != ' ')\n        cp++;\n    if (*cp != '\\0') {\n        *cp++ = 0;\n        while (*cp && *cp == ' ')\n            cp++;\n        if (*cp) {\n            if ((error = copystr(cp, epp->sh.interparg, sizeof epp->sh.interparg, NULL)))\n                goto done;\n        }\n    }\n\n    /*\n     * the interpreter is the new file to exec\n     */\n    ndp->ni_nameiop = LOOKUP | FOLLOW;\n    ip = namei (ndp);\n    if (ip == NULL)\n        return u.u_error;\n    if ((error = copystr(ndp->ni_dent.d_name, epp->sh.interpname, sizeof epp->sh.interpname, NULL)))\n        goto done;\n\n    /*\n     * Everything set up, do the recursive exec()\n     */\n    DEBUG(\"\\texec_script_check(): do recursive exec\\n\");\n    epp->ip = ip;\n    error = exec_check(epp);\ndone:\n    if (ip)\n        iput(ip);\n\n    DEBUG(\"\\texec_script_check(): end\\n\");\n\n    return error;\n}\n"
  },
  {
    "path": "sys/kern/exec_subr.c",
    "content": "#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/map.h>\n#include <sys/inode.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/buf.h>\n#include <sys/namei.h>\n#include <sys/fs.h>\n#include <sys/mount.h>\n#include <sys/file.h>\n#include <sys/resource.h>\n#include <sys/exec.h>\n#include <sys/dir.h>\n#include <sys/uio.h>\n#include <machine/debug.h>\n#include <machine/frame.h>\n\n/*\n * How memory is set up.\n *\n * var a:\n *__user_data_end:!----------!\n *                ! +P_ssize ! stack\n * p_saddr ->     !----------!\n *\n *                !----------!\n *                ! +P_dsize ! .data + .bss + heap\n * P_daddr ->     !----------!\n *\n * var b:\n *\n *__user_data_end:!--------!\n *                ! +ssize ! stack\n * saddr ->       !--------!\n *                ! +hsize ! heap\n * haddr ->       !--------!\n *                ! +dsize ! .data + .bss\n * daddr ->       !--------!\n *                ! +tsize ! .text\n * taddr ->       !--------!\n * paddr -> +psize\n *\n * var c:\n *                !--------!\n *                ! +tsize ! .text (read only section)\n * taddr ->       !--------!\n *                ! +ssize ! stack\n * saddr ->       !--------!\n *                ! +hsize ! heap\n * haddr ->       !--------!\n *                ! +dsize ! .data + .bss\n * daddr ->       !--------!\n * paddr -> +psize\n */\n\n/*\n * Set up user memory.\n *\n * The following is a key to top of the stack and the variables used.\n *\n *  topp->      [argv]      top word for /bin/ps\n *               <0>\n *                n\n *                g\n *                r\n *                a\n *               ...\n *               <0>\n *                0\n *                g\n *                r\n *  ucp ->        a\n *               [0]\n *              [envn]\n *               ...\n *  envp ->     [env0]\n *               [0]\n *              [argn]      ptr to argn\n *               ...\n *  argp ->     [arg0]      ptr to arg0\n *               []       \\\n *               []       | 16 bytes for Mips\n *               []       | 64 bytes for Arm\n *    sp ->      []       /\n *\n */\nvoid exec_setupstack(unsigned entryaddr, struct exec_params *epp)\n{\n    int nc,i;\n    u_int len;\n    char *ucp;\n    char **argp, **envp, ***topp;\n\n    DEBUG(\"\\texec_setupstack(): start\\n\");\n\n    /*\n     * Set up top of stack structure as above\n     * This depends on that kernel and user spaces\n     * map to the same addresses.\n     */\n    topp = (char ***)(epp->stack.vaddr + epp->stack.len - NBPW);            /* Last word of RAM */\n    ucp = (char *)((unsigned)topp - roundup(epp->envbc + epp->argbc,NBPW)); /* arg string space */\n    envp = (char **)(ucp - (epp->envc+1)*NBPW); /* Make place for envp[...], +1 for the 0 */\n    argp = envp - (epp->argc+1)*NBPW;           /* Make place for argv[...] */\n\n#ifdef __mips__\n    u.u_frame->tf_sp = (int)(argp-16);\n    u.u_frame->tf_r4 = epp->argc;               /* $a0 := argc */\n    u.u_frame->tf_r5 = (int)argp;               /* $a1 := argp */\n    u.u_frame->tf_r6 = (int)envp;               /* $a2 := env */\n#elif __thumb2__ || __thumb__\n    u.u_frame->tf_sp = (int)(argp-0x40);        /* 0x40 for svc trap frame. */\n    u.u_frame->tf_r0 = epp->argc;               /* $a1 := argc */\n    u.u_rval         = epp->argc;               /* $a1 := argc via syscall() */\n    u.u_frame->tf_r1 = (int)argp;               /* $a2 := argp */\n    u.u_frame->tf_r2 = (int)envp;               /* $a3 := envp */\n\n    u.u_frame->tf_lr  = 0xffffffff;             /* lr, set -1 (reset value) */\n    u.u_frame->tf_psr = 0x01000000;             /* psr, Thumb state bit set */\n#else\n#error \"set up top of stack for unknown architecture\"\n#endif\n\n    *topp = argp;                               /* for /bin/ps */\n\n    /*\n     * copy the arguments into the structure\n     */\n    nc = 0;\n    for (i = 0; i < epp->argc; i++) {\n        argp[i] = (caddr_t)ucp;\n        if (copystr((caddr_t)epp->argp[i], (caddr_t)ucp, (caddr_t)topp-ucp, &len) == 0) {\n            nc += len;\n            ucp += len;\n        }\n    }\n    argp[epp->argc] = NULL;\n\n    for (i = 0; i < epp->envc; i++) {\n        envp[i] = ucp;\n        if (copystr((caddr_t)epp->envp[i], (caddr_t)ucp, (caddr_t)topp-ucp, &len) == 0) {\n            nc += len;\n            ucp += len;\n        }\n    }\n    envp[epp->envc] = NULL;\n\n    ucp = (caddr_t)roundup((unsigned)ucp, NBPW);\n    if ((caddr_t)ucp != (caddr_t)topp) {\n        DEBUG(\"\\texec_setupstack(): error: copy arg list, ucp = %#x, topp = %#x\\n\", ucp, topp);\n        panic(\"exec check\");\n    }\n\n    u.u_frame->tf_pc = entryaddr;\n    DEBUG(\"\\texec_setupstack(): new PC = %#x\\n\", entryaddr);\n\n    /*\n     * Remember file name for accounting.\n     */\n    (void) copystr(argp[0], u.u_comm, MAXCOMLEN, 0);\n\n    DEBUG(\"\\texec_setupstack(): end\\n\");\n}\n\n/*\n * A simple memory allocator used within exec code using file buffers as storage.\n * Will return NULL if allocation is not possible.\n * Total max memory allocatable is MAXALLOCBUF*MAXBSIZE\n * Max size of allocatable chunk is MAXBSIZE\n *\n * All memory allocated with this function will be freed by a call\n * to exec_alloc_freeall()\n */\nvoid *exec_alloc(int size, int ru, struct exec_params *epp)\n{\n    char *cp;\n    int i;\n\n    for (i = 0; i < MAXALLOCBUF; i++)\n        if (MAXBSIZE - (ru<=1?epp->alloc[i].fill:roundup(epp->alloc[i].fill,ru)) >= size)\n            break;\n    if (i == MAXALLOCBUF)\n        return NULL;\n    if (epp->alloc[i].bp == NULL) {\n        if ((epp->alloc[i].bp = geteblk()) == NULL) {\n            DEBUG(\"\\texec_alloc(): no buf\\n\");\n            return NULL;\n        }\n    }\n    if (ru > 1)\n        epp->alloc[i].fill = roundup(epp->alloc[i].fill, ru);\n    cp = epp->alloc[i].bp->b_addr + epp->alloc[i].fill;\n    epp->alloc[i].fill += size;\n    bzero (cp, size);\n    return cp;\n}\n\n/*\n * this will deallocate all memory allocated by exec_alloc\n */\nvoid exec_alloc_freeall(struct exec_params *epp)\n{\n    int i;\n    for (i = 0; i < MAXALLOCBUF; i++) {\n        if (epp->alloc[i].bp) {\n            brelse(epp->alloc[i].bp);\n            epp->alloc[i].bp = NULL;\n            epp->alloc[i].fill = 0;\n        }\n    }\n}\n\n/*\n * Establish memory for the image based on the\n * values picked up from the executable file and stored\n * in the exec params block.\n */\nint exec_estab(struct exec_params *epp)\n{\n    DEBUG(\"\\texec_estab(): start\\n\");\n\n    DEBUG(\"\\texec_estab(): text  = %#x..%#x, len = %d\\n\", epp->text.vaddr,\n      epp->text.vaddr + epp->text.len, epp->text.len);\n    DEBUG(\"\\texec_estab(): data  = %#x..%#x, len = %d\\n\", epp->data.vaddr,\n      epp->data.vaddr + epp->data.len, epp->data.len);\n    DEBUG(\"\\texec_estab(): bss   = %#x..%#x, len = %d\\n\", epp->bss.vaddr,\n      epp->bss.vaddr + epp->bss.len, epp->bss.len);\n    DEBUG(\"\\texec_estab(): heap  = %#x..%#x, len = %d\\n\", epp->heap.vaddr,\n      epp->heap.vaddr + epp->heap.len, epp->heap.len);\n    DEBUG(\"\\texec_estab(): stack = %#x..%#x, len = %d\\n\", epp->stack.vaddr,\n      epp->stack.vaddr + epp->stack.len, epp->stack.len);\n\n    /*\n     * Right now we can only handle the simple original a.out\n     * case, so we double check for that case here.\n     */\n    if (epp->text.vaddr != NO_ADDR || epp->data.vaddr == NO_ADDR ||\n      epp->data.vaddr != (caddr_t)__user_data_start ||\n      epp->stack.vaddr != (caddr_t)__user_data_end - epp->stack.len) {\n        DEBUG(\"\\texec_estab(): error: not an a.out executable\\n\");\n        return ENOMEM;\n    }\n\n    /*\n     * Try out for overflow\n     */\n    if (epp->text.len + epp->data.len + epp->heap.len + epp->stack.len > MAXMEM) {\n        DEBUG(\"\\texec_estab(): error: memory overflow\\n\");\n        return ENOMEM;\n    }\n\n    if (roundup((unsigned)epp->data.vaddr + epp->data.len, NBPW) != roundup((unsigned)epp->bss.vaddr, NBPW)) {\n        DEBUG(\"\\texec_estab(): error: .bss does not follow .data\\n\");\n        return ENOMEM;\n    }\n\n    /*\n     * Allocate core at this point, committed to the new image.\n     */\n    u.u_prof.pr_scale = 0;\n    if (u.u_procp->p_flag & SVFORK)\n        endvfork();\n    u.u_procp->p_dsize = epp->data.len + epp->bss.len;\n    u.u_procp->p_daddr = (size_t)epp->data.vaddr;\n    u.u_procp->p_ssize = epp->stack.len;\n    u.u_procp->p_saddr = (size_t)epp->stack.vaddr;\n\n    DEBUG(\"\\texec_estab(): core allocation\\n\");\n    DEBUG(\"\\texec_estab(): daddr = %#x..%#x, len = %d\\n\", u.u_procp->p_daddr,\n      u.u_procp->p_daddr + u.u_procp->p_dsize, u.u_procp->p_dsize);\n    DEBUG(\"\\texec_estab(): saddr = %#x..%#x, len = %d\\n\", u.u_procp->p_saddr,\n      u.u_procp->p_saddr + u.u_procp->p_ssize, u.u_procp->p_ssize);\n\n    DEBUG(\"\\texec_estab(): end\\n\");\n\n    return 0;\n}\n\n\n/*\n * Save argv[] and envp[]\n */\nvoid exec_save_args(struct exec_params *epp)\n{\n    unsigned len;\n    caddr_t cp;\n    int argc, i, l;\n    char **argp, *ap;\n\n    DEBUG(\"\\texec_save_args(): start\\n\");\n\n    epp->argc = epp->envc = 0;\n    epp->argbc = epp->envbc = 0;\n\n    argc = 0;\n    if ((argp = epp->userargp) != NULL)\n        while (argp[argc])\n            argc++;\n    if (epp->sh.interpreted) {\n        argc++;\n        if (epp->sh.interparg[0])\n            argc++;\n    }\n    if (argc != 0) {\n        if ((epp->argp = (char **)exec_alloc(argc * sizeof(char *), NBPW, epp)) == NULL)\n            return;\n        for (;;) {\n            /*\n             * For a interpreter script, the arg list is changed to\n             * #! <interpreter name> <interpreter arg>\n             * arg[0] - the interpreter executable name (path)\n             * arg[1] - interpreter arg (optional)\n             * arg[2 or 1] - script name\n             * arg[3 or 2...] - script arg[1...]\n             */\n            if (argp)\n                ap = *argp++;\n            else\n                ap = NULL;\n\n            if (epp->sh.interpreted) {\n                if (epp->argc == 0)\n                    ap = epp->sh.interpname;\n                else if (epp->argc == 1 && epp->sh.interparg[0]) {\n                    ap = epp->sh.interparg;\n                    --argp;\n                } else if ((epp->argc == 1 || (epp->argc == 2 && epp->sh.interparg[0]))) {\n                    ap = epp->userfname;\n                    --argp;\n                }\n            }\n            if (ap == 0)\n                break;\n            l = strlen(ap)+1;\n            if ((cp = exec_alloc(l, 1, epp)) == NULL)\n                return;\n            if (copystr(ap, cp, l, &len) != 0)\n                return;\n            epp->argp[epp->argc++] = cp;\n            epp->argbc += len;;\n        }\n    }\n    argc = 0;\n    if ((argp = epp->userenvp) != NULL)\n        while (argp[argc])\n            argc++;\n    epp->envc = 0;\n    epp->envbc = 0;\n    if (argc != 0) {\n        if ((epp->envp = (char **)exec_alloc(argc * sizeof(char *), NBPW, epp)) == NULL)\n            return;\n        for (;;) {\n            if (argp)\n                ap = *argp++;\n            else\n                ap = NULL;\n            if (ap == 0)\n                break;\n            l = strlen(ap)+1;\n            if ((cp = exec_alloc(l, 1, epp)) == NULL)\n                return;\n            if (copystr(ap, cp, l, &len) != 0)\n                return;\n            epp->envp[epp->envc++] = cp;\n            epp->envbc += len;\n        }\n    }\n\n    for (i = 0; i < epp->argc; i++)\n        DEBUG(\"\\texec_save_args(): arg[%d] = \\\"%s\\\"\\n\", i, epp->argp[i]);\n\n    for (i = 0; i < epp->envc; i++)\n        DEBUG(\"\\texec_save_args(): env[%d] = \\\"%s\\\"\\n\", i, epp->envp[i]);\n\n    DEBUG(\"\\texec_save_args(): end\\n\");\n}\n\nvoid exec_clear(struct exec_params *epp)\n{\n    char *cp;\n    int cc;\n\n    DEBUG(\"\\texec_clear(): start\\n\");\n\n    /* clear BSS  */\n    if (epp->bss.len > 0)\n        bzero((void *)epp->bss.vaddr, epp->bss.len);\n    if (epp->heap.len > 0)\n        bzero((void *)epp->heap.vaddr, epp->heap.len);\n    /* Clear stack */\n    bzero((void *)epp->stack.vaddr, epp->stack.len);\n\n    /*\n     * set SUID/SGID protections, if no tracing\n     */\n    if ((u.u_procp->p_flag & P_TRACED) == 0) {\n        u.u_uid = epp->uid;\n        u.u_procp->p_uid = epp->uid;\n        u.u_groups[0] = epp->gid;\n    } else\n        psignal (u.u_procp, SIGTRAP);\n    u.u_svuid = u.u_uid;\n    u.u_svgid = u.u_groups[0];\n\n    u.u_tsize = epp->text.len;\n    u.u_dsize = epp->data.len + epp->bss.len;\n    u.u_ssize = epp->stack.len;\n\n    /*\n     * Clear registers.\n     */\n#ifdef __mips__\n    u.u_frame->tf_r1  = 0;              /* $at */\n    u.u_frame->tf_r2  = 0;              /* $v0 */\n    u.u_frame->tf_r3  = 0;              /* $v1 */\n    u.u_frame->tf_r7  = 0;              /* $a3 */\n    u.u_frame->tf_r8  = 0;              /* $t0 */\n    u.u_frame->tf_r9  = 0;              /* $t1 */\n    u.u_frame->tf_r10 = 0;              /* $t2 */\n    u.u_frame->tf_r11 = 0;              /* $t3 */\n    u.u_frame->tf_r12 = 0;              /* $t4 */\n    u.u_frame->tf_r13 = 0;              /* $t5 */\n    u.u_frame->tf_r14 = 0;              /* $t6 */\n    u.u_frame->tf_r15 = 0;              /* $t7 */\n    u.u_frame->tf_r16 = 0;              /* $s0 */\n    u.u_frame->tf_r17 = 0;              /* $s1 */\n    u.u_frame->tf_r18 = 0;              /* $s2 */\n    u.u_frame->tf_r19 = 0;              /* $s3 */\n    u.u_frame->tf_r20 = 0;              /* $s4 */\n    u.u_frame->tf_r21 = 0;              /* $s5 */\n    u.u_frame->tf_r22 = 0;              /* $s6 */\n    u.u_frame->tf_r23 = 0;              /* $s7 */\n    u.u_frame->tf_r24 = 0;              /* $t8 */\n    u.u_frame->tf_r25 = 0;              /* $t9 */\n    u.u_frame->tf_fp  = 0;\n    u.u_frame->tf_ra  = 0;\n    u.u_frame->tf_lo  = 0;\n    u.u_frame->tf_hi  = 0;\n    u.u_frame->tf_gp  = 0;\n#elif __thumb2__ || __thumb__\n    u.u_frame->tf_r0  = 0;              /* a1 */\n    u.u_frame->tf_r1  = 0;              /* a2 */\n    u.u_frame->tf_r2  = 0;              /* a3 */\n    u.u_frame->tf_r3  = 0;              /* a4 */\n    u.u_frame->tf_ip  = 0;              /* sp, as passed as ip */\n    u.u_frame->tf_lr  = 0;              /* lr */\n    u.u_frame->tf_pc  = 0;              /* pc */\n    u.u_frame->tf_psr = 0;              /* psr */\n    u.u_frame->tf_r4  = 0;              /* v1 */\n    u.u_frame->tf_r5  = 0;              /* v2 */\n    u.u_frame->tf_r6  = 0;              /* v3 */\n    u.u_frame->tf_r7  = 0;              /* v4 */\n    u.u_frame->tf_r8  = 0;              /* v5 */\n    u.u_frame->tf_r9  = 0;              /* v6 */\n    u.u_frame->tf_r10 = 0;              /* v7 */\n    u.u_frame->tf_r11 = 0;              /* v8 */\n#else\n#error \"clear trap frame registers for unknown architecture\"\n#endif\n\n    execsigs (u.u_procp);\n\n    /*\n     * Clear (close) files\n     */\n    for (cp = u.u_pofile, cc = 0; cc <= u.u_lastfile; cc++, cp++) {\n        if (*cp & UF_EXCLOSE) {\n            (void) closef (u.u_ofile [cc]);\n            u.u_ofile [cc] = NULL;\n            *cp = 0;\n        }\n    }\n    while (u.u_lastfile >= 0 && u.u_ofile [u.u_lastfile] == NULL)\n        u.u_lastfile--;\n\n    DEBUG(\"\\texec_clear(): end\\n\");\n}\n"
  },
  {
    "path": "sys/kern/init_main.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *\t@(#)init_main.c\t2.5 (2.11BSD GTE) 1997/9/26\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/fs.h>\n#include <sys/mount.h>\n#include <sys/map.h>\n#include <sys/proc.h>\n#include <sys/ioctl.h>\n#include <sys/inode.h>\n#include <sys/conf.h>\n#include <sys/buf.h>\n#include <sys/fcntl.h>\n#include <sys/vm.h>\n#include <sys/clist.h>\n#include <sys/reboot.h>\n#include <sys/systm.h>\n#include <sys/kernel.h>\n#include <sys/namei.h>\n#include <sys/stat.h>\n#include <sys/config.h>\n\nstatic void\tbhinit(void);\nstatic void\tbinit(void);\nstatic void\tcinit(void);\n\nu_int\t\tswapstart, nswap;\t/* start and size of swap space */\nsize_t\t\tphysmem;\t\t/* total amount of physical memory */\nint\t\tboothowto;\t\t/* reboot flags, from boot */\n\n/*\n * Initialization code.\n * Called from cold start routine as\n * soon as a stack and segmentation\n * have been established.\n * Functions:\n *\tclear and free user core\n *\tturn on clock\n *\thand craft 0th process\n *\tcall all initialization routines\n *\tfork - process 0 to schedule\n *\t     - process 1 execute bootstrap\n */\nint\nmain(void)\n{\n\tstruct proc *p;\n\tint i;\n\tstruct fs *fs = NULL;\n\tint s __attribute__((unused));\n\n\tstartup();\n\tprintf(\"\\n%s\", version);\n\tconfig();\n\n\t/*\n\t * Set up system process 0 (swapper).\n\t */\n\tp = &proc[0];\n\tp->p_addr = (size_t)&u;\n\tp->p_stat = SRUN;\n\tp->p_flag |= SLOAD | SSYS;\n\tp->p_nice = NZERO;\n\n\tu.u_procp = p;\t\t\t/* init user structure */\n\tu.u_cmask = CMASK;\n\tu.u_lastfile = -1;\n\tfor (i = 1; i < NGROUPS; i++)\n\t\tu.u_groups[i] = NOGROUP;\n\tfor (i = 0; i < sizeof(u.u_rlimit)/sizeof(u.u_rlimit[0]); i++)\n\t\tu.u_rlimit[i].rlim_cur = u.u_rlimit[i].rlim_max =\n\t\t    RLIM_INFINITY;\n\n\t/* Initialize signal state for process 0 */\n\tsiginit(p);\n\n\t/*\n\t * Initialize tables, protocols, and set up well-known inodes.\n\t */\n#ifdef LOG_ENABLED\n\tloginit();\n#endif\n\tcoutinit();\n\tcinit();\n\tpqinit();\n\tihinit();\n\tbhinit();\n\tbinit();\n\tnchinit();\n\tclkstart();\n\n\tpipedev = rootdev;\n\n\t/* Attach services. */\n\tstruct conf_service *svc;\n\tfor (svc = conf_service_init; svc->svc_attach != NULL; svc++)\n\t\t(*svc->svc_attach)();\n\n\t/* Mount a root filesystem. */\n\ts = spl0();\n\tfs = mountfs(rootdev, (boothowto & RB_RDONLY) ? MNT_RDONLY : 0, 0);\n\tif (!fs)\n\t\tpanic(\"No root filesystem found!\");\n\tmount[0].m_inodp = (struct inode *)1;\t/* XXX */\n\tmount_updname(fs, \"/\", \"root\", 1, 4);\n\ttime.tv_sec = fs->fs_time;\n\tboottime = time;\n\n\t/* Find a swap file. */\n\tswapstart = 1;\n\t(*bdevsw[major(swapdev)].d_open)(swapdev, FREAD|FWRITE, S_IFBLK);\n\tnswap = (*bdevsw[major(swapdev)].d_psize)(swapdev);\n\tif (nswap <= 0)\n\t\tpanic(\"swap size\");\t/* don't want to panic, but what ? */\n\tmfree(swapmap, nswap, swapstart);\n\n\tprintf(\"phys mem  = %u kbytes\\n\", physmem / 1024);\n\tprintf(\"user mem  = %u kbytes\\n\", MAXMEM / 1024);\n\tprintf(\"root dev  = (%d,%d)\\n\", major(rootdev), minor(rootdev));\n\tprintf(\"swap dev  = (%d,%d)\\n\", major(swapdev), minor(swapdev));\n\tprintf(\"root size = %u kbytes\\n\", fs->fs_fsize * DEV_BSIZE / 1024);\n\tprintf(\"swap size = %u kbytes\\n\", nswap * DEV_BSIZE / 1024);\n\n\t/* Kick off timeout driven events by calling first time. */\n\tschedcpu(0);\n\n\t/* Set up the root file system. */\n\trootdir = iget(rootdev, &mount[0].m_filsys, (ino_t)ROOTINO);\n\tiunlock(rootdir);\n\tu.u_cdir = iget(rootdev, &mount[0].m_filsys, (ino_t)ROOTINO);\n\tiunlock(u.u_cdir);\n\tu.u_rdir = NULL;\n\n\t/*\n\t * Make init process.\n\t */\n\tif (newproc(0) == 0) {\n\t\t/* Parent process with pid 0: swapper. */\n\t\t/* No return from sched. */\n\t\tsched();\n\t}\n\n\t/* Child process with pid 1: init. */\n\ts = splhigh();\n\tp = u.u_procp;\n\tp->p_dsize = icodeend - icode;\n\tp->p_daddr = (size_t)__user_data_start;\n\tp->p_ssize = 1024;\t\t\t/* One kbyte of stack. */\n\tp->p_saddr = (size_t)__user_data_end - 1024;\n\tbcopy((caddr_t)icode, (caddr_t)__user_data_start, icodeend - icode);\n\n\t/* Start in single user mode, if asked. */\n\tif (boothowto & RB_SINGLE) {\n\t\tchar *iflags = (char *)__user_data_start + (initflags - icode);\n\n\t\t/* Call /sbin/init with option '-s'. */\n\t\tiflags[1] = 's';\n\t}\n\n\t/*\n\t * return goes to location 0 of user init code\n\t * just copied out.\n\t */\n\treturn 0;\n}\n\n/*\n * Initialize hash links for buffers.\n */\nstatic void\nbhinit(void)\n{\n\tint i;\n\tstruct bufhd *bp;\n\n\tfor (bp = bufhash, i = 0; i < BUFHSZ; i++, bp++)\n\t\tbp->b_forw = bp->b_back = (struct buf *)bp;\n}\n\n/*\n * Initialize the buffer I/O system by freeing\n * all buffers and setting all device buffer lists to empty.\n */\nstatic void\nbinit(void)\n{\n\tstruct buf *bp;\n\tint i;\n\tcaddr_t paddr;\n\n\tfor (bp = bfreelist; bp < &bfreelist[BQUEUES]; bp++)\n\t\tbp->b_forw = bp->b_back = bp->av_forw = bp->av_back = bp;\n\n\tpaddr = bufdata;\n\n\tfor (i = 0; i < NBUF; i++, paddr += MAXBSIZE) {\n\t\tbp = &buf[i];\n\t\tbp->b_dev = NODEV;\n\t\tbp->b_bcount = 0;\n\t\tbp->b_addr = paddr;\n\t\tbinshash(bp, &bfreelist[BQ_AGE]);\n\t\tbp->b_flags = B_BUSY|B_INVAL;\n\t\tbrelse(bp);\n\t}\n}\n\n/*\n * Initialize clist by freeing all character blocks, then count\n * number of character devices. (Once-only routine)\n */\nstatic void\ncinit(void)\n{\n\tint ccp;\n\tstruct cblock *cp;\n\n\tccp = (int)cfree;\n\tccp = (ccp + CROUND) & ~CROUND;\n\tfor (cp = (struct cblock *)ccp; cp <= &cfree[NCLIST - 1]; cp++) {\n\t\tcp->c_next = cfreelist;\n\t\tcfreelist = cp;\n\t\tcfreecount += CBSIZE;\n\t}\n}\n"
  },
  {
    "path": "sys/kern/init_sysent.c",
    "content": "/*\n * System call switch table.\n *\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/glob.h>\n\n#ifdef INET\n#   define ifnet(narg, name)    narg, name\n#   define errnet(narg, name)   narg, name\n#else\n#   define ifnet(narg, name)    0, nosys\n#   define errnet(narg, name)   0, nonet\n#endif\n\nextern void sc_msec();\n\n/*\n * Reserved/unimplemented system calls in the range 0-150 inclusive\n * are reserved for use in future Berkeley releases.\n * Additional system calls implemented in vendor and other\n * redistributions should be placed in the reserved range at the end\n * of the current calls.\n */\n/*\n * This table is the switch used to transfer to the appropriate routine for\n * processing a system call.  Each row contains the number of words of\n * arguments expected in registers, how many on the stack, and a pointer to\n * the routine.\n *\n * The maximum number of direct system calls is 255 since system call numbers\n * are encoded in the lower byte of the trap instruction -- see trap.c.\n */\nconst struct sysent sysent[] = {\n    { 1, nosys },               /*   0 = out-of-range */\n    { 1, rexit },               /*   1 = exit */\n    { 0, fork },                /*   2 = fork */\n    { 3, read },                /*   3 = read */\n    { 3, write },               /*   4 = write */\n    { 3, open },                /*   5 = open */\n    { 1, close },               /*   6 = close */\n    { 4, wait4 },               /*   7 = wait4 */\n    { 0, nosys },               /*   8 = (old creat) */\n    { 2, link },                /*   9 = link */\n    { 1, unlink },              /*  10 = unlink */\n    { 2, execv },               /*  11 = execv */\n    { 1, chdir },               /*  12 = chdir */\n    { 1, fchdir },              /*  13 = fchdir */\n    { 3, mknod },               /*  14 = mknod */\n    { 2, chmod },               /*  15 = chmod */\n    { 3, chown },               /*  16 = chown; now 3 args */\n    { 2, chflags },             /*  17 = chflags */\n    { 2, fchflags },            /*  18 = fchflags */\n    { 4, lseek },               /*  19 = lseek */\n    { 0, getpid },              /*  20 = getpid */\n    { 3, smount },              /*  21 = mount */\n    { 1, umount },              /*  22 = umount */\n    { 6, __sysctl },            /*  23 = __sysctl */\n    { 0, getuid },              /*  24 = getuid */\n    { 0, geteuid },             /*  25 = geteuid */\n    { 4, ptrace },              /*  26 = ptrace */\n    { 0, getppid },             /*  27 = getppid */\n    { 2, statfs },              /*  28 = statfs */\n    { 2, fstatfs },             /*  29 = fstatfs */\n    { 3, getfsstat },           /*  30 = getfsstat */\n    { 4, sigaction },           /*  31 = sigaction */\n    { 3, sigprocmask },         /*  32 = sigprocmask */\n    { 2, saccess },             /*  33 = access */\n    { 1, sigpending },          /*  34 = sigpending */\n    { 2, sigaltstack },         /*  35 = sigaltstack */\n    { 0, sync },                /*  36 = sync */\n    { 2, kill },                /*  37 = kill */\n    { 2, stat },                /*  38 = stat */\n    { 2, nosys },               /*  39 = getlogin */\n    { 2, lstat },               /*  40 = lstat */\n    { 1, dup },                 /*  41 = dup */\n    { 0, pipe },                /*  42 = pipe */\n    { 1, nosys },               /*  43 = setlogin */\n    { 4, profil },              /*  44 = profil */\n    { 1, setuid },              /*  45 = setuid */\n    { 1, seteuid },             /*  46 = seteuid */\n    { 0, getgid },              /*  47 = getgid */\n    { 0, getegid },             /*  48 = getegid */\n    { 1, setgid },              /*  49 = setgid */\n    { 1, setegid },             /*  50 = setegid */\n    { 0, kmemdev },             /*  51 = kmemdev */\n    { 3, nosys },               /*  52 = (2.9) set phys addr */\n    { 1, nosys },               /*  53 = (2.9) lock in core */\n    { 4, ioctl },               /*  54 = ioctl */\n    { 1, reboot },              /*  55 = reboot */\n    { 2, sigwait },             /*  56 = sigwait */\n    { 2, symlink },             /*  57 = symlink */\n    { 3, readlink },            /*  58 = readlink */\n    { 3, execve },              /*  59 = execve */\n    { 1, umask },               /*  60 = umask */\n    { 1, chroot },              /*  61 = chroot */\n    { 2, fstat },               /*  62 = fstat */\n    { 0, nosys },               /*  63 = reserved */\n    { 0, nosys },               /*  64 = (old getpagesize) */\n    { 6, pselect },             /*  65 = pselect */\n    { 0, vfork },               /*  66 = vfork */\n    { 0, nosys },               /*  67 = unused */\n    { 0, nosys },               /*  68 = unused */\n    { 1, brk },                 /*  69 = brk */\n#ifdef GLOB_ENABLED\n    { 1, rdglob },              /*  70 = read from global */\n    { 2, wrglob },              /*  71 = write to global */\n#else\n    { 1, nosys },\n    { 2, nosys },\n#endif\n    { 0, sc_msec },             /*  72 = msec */\n    { 0, nosys },               /*  73 = unused */\n    { 0, nosys },               /*  74 = unused */\n    { 0, nosys },               /*  75 = unused */\n    { 0, vhangup },             /*  76 = vhangup */\n    { 0, nosys },               /*  77 = unused */\n    { 0, nosys },               /*  78 = unused */\n    { 2, getgroups },           /*  79 = getgroups */\n    { 2, setgroups },           /*  80 = setgroups */\n    { 1, getpgrp },             /*  81 = getpgrp */\n    { 2, setpgrp },             /*  82 = setpgrp */\n    { 3, setitimer },           /*  83 = setitimer */\n    { 0, nosys },               /*  84 = (old wait,wait3) */\n    { 0, nosys },               /*  85 = unused */\n    { 2, getitimer },           /*  86 = getitimer */\n    { 0, nosys },               /*  87 = (old gethostname) */\n    { 0, nosys },               /*  88 = (old sethostname) */\n    { 0, getdtablesize },       /*  89 = getdtablesize */\n    { 2, dup2 },                /*  90 = dup2 */\n    { 0, nosys },               /*  91 = unused */\n    { 3, fcntl },               /*  92 = fcntl */\n    { 5, select },              /*  93 = select */\n    { 0, nosys },               /*  94 = unused */\n    { 1, fsync },               /*  95 = fsync */\n    { 3, setpriority },         /*  96 = setpriority */\n    { errnet(3, socket) },      /*  97 = socket */\n    { ifnet(3, connect) },      /*  98 = connect */\n    { ifnet(3, accept) },       /*  99 = accept */\n    { 2, getpriority },         /* 100 = getpriority */\n    { ifnet(4, send) },         /* 101 = send */\n    { ifnet(4, recv) },         /* 102 = recv */\n    { 1, sigreturn },           /* 103 = sigreturn */\n    { ifnet(3, bind) },         /* 104 = bind */\n    { ifnet(5, setsockopt) },   /* 105 = setsockopt */\n    { ifnet(2, listen) },       /* 106 = listen */\n    { 1, sigsuspend },          /* 107 = sigsuspend */\n    { 0, nosys },               /* 108 = (old sigvec) */\n    { 0, nosys },               /* 109 = (old sigblock) */\n    { 0, nosys },               /* 110 = (old sigsetmask) */\n    { 0, nosys },               /* 111 = (old sigpause)  */\n    { 2, sigstack },            /* 112 = sigstack COMPAT-43 */\n    { ifnet(3, recvmsg) },      /* 113 = recvmsg */\n    { ifnet(3, sendmsg) },      /* 114 = sendmsg */\n    { 0, nosys },               /* 115 = unused */\n    { 2, gettimeofday },        /* 116 = gettimeofday */\n    { 2, getrusage },           /* 117 = getrusage */\n    { ifnet(5, getsockopt) },   /* 118 = getsockopt */\n    { 0, nosys },               /* 119 = unused */\n    { 3, readv },               /* 120 = readv */\n    { 3, writev },              /* 121 = writev */\n    { 2, settimeofday },        /* 122 = settimeofday */\n    { 3, fchown },              /* 123 = fchown */\n    { 2, fchmod },              /* 124 = fchmod */\n    { ifnet(6, recvfrom) },     /* 125 = recvfrom */\n    { 0, nosys },               /* 126 = (old setreuid) */\n    { 0, nosys },               /* 127 = (old setregid) */\n    { 2, rename },              /* 128 = rename */\n    { 3, truncate },            /* 129 = truncate */\n    { 3, ftruncate },           /* 130 = ftruncate */\n    { 2, flock },               /* 131 = flock */\n    { 0, nosys },               /* 132 = nosys */\n    { ifnet(6, sendto) },       /* 133 = sendto */\n    { ifnet(2, shutdown) },     /* 134 = shutdown */\n    { errnet(4, socketpair) },  /* 135 = socketpair */\n    { 2, mkdir },               /* 136 = mkdir */\n    { 1, rmdir },               /* 137 = rmdir */\n    { 2, utimes },              /* 138 = utimes */\n    { 0, nosys },               /* 139 = unused */\n    { 2, adjtime },             /* 140 = adjtime */\n    { ifnet(3, getpeername) },  /* 141 = getpeername */\n    { 0, nosys },               /* 142 = (old gethostid) */\n    { 0, nosys },               /* 143 = (old sethostid) */\n    { 2, getrlimit },           /* 144 = getrlimit */\n    { 2, setrlimit },           /* 145 = setrlimit */\n    { 2, killpg },              /* 146 = killpg */\n    { 0, nosys },               /* 147 = nosys */\n    { 2, nosys },               /* 148 = quota */\n    { 4, nosys },               /* 149 = qquota */\n    { ifnet(3, getsockname) },  /* 150 = getsockname */\n    /*\n     * Syscalls 151-180 inclusive are reserved for vendor-specific\n     * system calls.  (This includes various calls added for compatibity\n     * with other Unix variants.)\n     */\n\n    /*\n     * 2BSD special calls\n     */\n    { 0, nosys },               /* 151 = unused */\n    { 2, ustore },              /* 152 = ustore */\n    { 1, ufetch },              /* 153 = ufetch */\n    { 4, ucall },               /* 154 = ucall */\n    { 0, nosys },               /* 155 = fperr */\n};\n\nconst int nsysent = sizeof (sysent) / sizeof (sysent[0]);\n"
  },
  {
    "path": "sys/kern/kern_clock.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/callout.h>\n#include <sys/dk.h>\n#include <sys/kernel.h>\n#include <sys/systm.h>\n\nint     noproc;         /* no one is running just now */\n\nstruct  callout *callfree, calltodo;\n\n#ifdef UCB_METER\nint dk_ndrive = DK_NDRIVE;\n\n/*\n * Gather statistics on resource utilization.\n *\n * We make a gross assumption: that the system has been in the\n * state it is in (user state, kernel state, interrupt state,\n * or idle state) for the entire last time interval, and\n * update statistics accordingly.\n */\n/*ARGSUSED*/\nvoid\ngatherstats(pc, ps)\n    caddr_t pc;\n    int ps;\n{\n    register int cpstate;\n\n    /*\n     * Determine what state the cpu is in.\n     */\n    if (USERMODE(ps)) {\n        /*\n         * CPU was in user state.\n         */\n        if (u.u_procp->p_nice > NZERO)\n            cpstate = CP_NICE;\n        else\n            cpstate = CP_USER;\n    } else {\n        /*\n         * CPU was in system state.  If profiling kernel\n         * increment a counter.  If no process is running\n         * then this is a system tick if we were running\n         * at a non-zero IPL (in a driver).  If a process is running,\n         * then we charge it with system time even if we were\n         * at a non-zero IPL, since the system often runs\n         * this way during processing of system calls.\n         * This is approximate, but the lack of true interval\n         * timers makes doing anything else difficult.\n         */\n        cpstate = CP_SYS;\n        if (noproc && BASEPRI(ps))\n            cpstate = CP_IDLE;\n    }\n    /*\n     * We maintain statistics shown by user-level statistics\n     * programs:  the amount of time in each cpu state, and\n     * the amount of time each of DK_NDRIVE ``drives'' is busy.\n     */\n    cp_time[cpstate]++;\n}\n#endif /* UCB_METER */\n\n/*\n * Software priority level clock interrupt.\n * Run periodic events from timeout queue.\n */\nvoid\nsoftclock(pc, ps)\n    caddr_t pc;\n    int ps;\n{\n    for (;;) {\n        register struct callout *p1;\n        register caddr_t arg;\n        register void (*func) (caddr_t);\n        register int s;\n\n        s = splhigh();\n        if ((p1 = calltodo.c_next) == 0 || p1->c_time > 0) {\n            splx(s);\n            break;\n        }\n        arg = p1->c_arg;\n        func = p1->c_func;\n        calltodo.c_next = p1->c_next;\n        p1->c_next = callfree;\n        callfree = p1;\n        splx(s);\n        (*func) (arg);\n    }\n    /*\n     * If trapped user-mode and profiling, give it\n     * a profiling tick.\n     */\n    if (USERMODE(ps)) {\n        register struct proc *p = u.u_procp;\n\n        if (u.u_prof.pr_scale)\n            addupc(pc, &u.u_prof, 1);\n        /*\n         * Check to see if process has accumulated\n         * more than 10 minutes of user time.  If so\n         * reduce priority to give others a chance.\n         */\n\n        if (p->p_uid && p->p_nice == NZERO &&\n            u.u_ru.ru_utime > 10L * 60L * hz) {\n            p->p_nice = NZERO+4;\n                (void) setpri(p);\n        }\n    }\n}\n\n/*\n * The hz hardware interval timer.\n * We update the events relating to real time.\n * Also gather statistics.\n *\n *  reprime clock\n *  implement callouts\n *  maintain user/system times\n *  maintain date\n *  profile\n */\nvoid\nhardclock(pc, ps)\n    caddr_t pc;\n    int ps;\n{\n    register struct callout *p1;\n    register struct proc *p;\n    register int needsoft = 0;\n\n    /*\n     * Update real-time timeout queue.\n     * At front of queue are some number of events which are ``due''.\n     * The time to these is <= 0 and if negative represents the\n     * number of ticks which have passed since it was supposed to happen.\n     * The rest of the q elements (times > 0) are events yet to happen,\n     * where the time for each is given as a delta from the previous.\n     * Decrementing just the first of these serves to decrement the time\n     * to all events.\n     */\n    p1 = calltodo.c_next;\n    while (p1) {\n        if (--p1->c_time > 0)\n            break;\n        needsoft = 1;\n        if (p1->c_time == 0)\n            break;\n        p1 = p1->c_next;\n    }\n\n    /*\n     * Charge the time out based on the mode the cpu is in.\n     * Here again we fudge for the lack of proper interval timers\n     * assuming that the current state has been around at least\n     * one tick.\n     */\n    if (USERMODE(ps)) {\n        if (u.u_prof.pr_scale)\n            needsoft = 1;\n        /*\n         * CPU was in user state.  Increment\n         * user time counter, and process process-virtual time\n         * interval timer.\n         */\n        u.u_ru.ru_utime++;\n        if (u.u_timer[ITIMER_VIRTUAL - 1].it_value &&\n            !--u.u_timer[ITIMER_VIRTUAL - 1].it_value) {\n            psignal(u.u_procp, SIGVTALRM);\n            u.u_timer[ITIMER_VIRTUAL - 1].it_value =\n                u.u_timer[ITIMER_VIRTUAL - 1].it_interval;\n        }\n    } else {\n        /*\n         * CPU was in system state.\n         */\n        if (!noproc)\n            u.u_ru.ru_stime++;\n    }\n\n    /*\n     * If the cpu is currently scheduled to a process, then\n     * charge it with resource utilization for a tick, updating\n     * statistics which run in (user+system) virtual time,\n     * such as the cpu time limit and profiling timers.\n     * This assumes that the current process has been running\n     * the entire last tick.\n     */\n    if (noproc == 0) {\n        p = u.u_procp;\n        if (++p->p_cpu == 0)\n            p->p_cpu--;\n        if ((u.u_ru.ru_utime+u.u_ru.ru_stime+1) >\n            u.u_rlimit[RLIMIT_CPU].rlim_cur) {\n            psignal(p, SIGXCPU);\n            if (u.u_rlimit[RLIMIT_CPU].rlim_cur <\n                u.u_rlimit[RLIMIT_CPU].rlim_max)\n                u.u_rlimit[RLIMIT_CPU].rlim_cur += 5 * hz;\n        }\n        if (u.u_timer[ITIMER_PROF - 1].it_value &&\n            !--u.u_timer[ITIMER_PROF - 1].it_value) {\n            psignal(p, SIGPROF);\n            u.u_timer[ITIMER_PROF - 1].it_value =\n                u.u_timer[ITIMER_PROF - 1].it_interval;\n        }\n    }\n\n#ifdef UCB_METER\n    gatherstats (pc, ps);\n#endif\n\n    /*\n     * Increment the time-of-day, process callouts at a very\n     * low cpu priority, so we don't keep the relatively high\n     * clock interrupt priority any longer than necessary.\n     */\n    if (adjdelta) {\n        if (adjdelta > 0) {\n            ++lbolt;\n            --adjdelta;\n        } else {\n            --lbolt;\n            ++adjdelta;\n        }\n    }\n    if (++lbolt >= hz) {\n        lbolt -= hz;\n        ++time.tv_sec;\n    }\n\n    if (needsoft && BASEPRI(ps)) {  /* if ps is high, just return */\n        (void) splsoftclock();\n        softclock (pc, ps);\n    }\n}\n\n/*\n * Arrange that (*fun)(arg) is called in t/hz seconds.\n */\nvoid\ntimeout (fun, arg, t)\n    void (*fun) (caddr_t);\n    caddr_t arg;\n    register int t;\n{\n    register struct callout *p1, *p2, *pnew;\n    register int s = splclock();\n\n    if (t <= 0)\n        t = 1;\n    pnew = callfree;\n    if (pnew == NULL)\n        panic(\"timeout table overflow\");\n    callfree = pnew->c_next;\n    pnew->c_arg = arg;\n    pnew->c_func = fun;\n    for (p1 = &calltodo; (p2 = p1->c_next) && p2->c_time < t; p1 = p2)\n        if (p2->c_time > 0)\n            t -= p2->c_time;\n    p1->c_next = pnew;\n    pnew->c_next = p2;\n    pnew->c_time = t;\n    if (p2)\n        p2->c_time -= t;\n    splx(s);\n}\n\n/*\n * untimeout is called to remove a function timeout call\n * from the callout structure.\n */\nvoid\nuntimeout (fun, arg)\n    void (*fun) (caddr_t);\n    caddr_t arg;\n{\n    register struct callout *p1, *p2;\n    register int s;\n\n    s = splclock();\n    for (p1 = &calltodo; (p2 = p1->c_next) != 0; p1 = p2) {\n        if (p2->c_func == fun && p2->c_arg == arg) {\n            if (p2->c_next && p2->c_time > 0)\n                p2->c_next->c_time += p2->c_time;\n            p1->c_next = p2->c_next;\n            p2->c_next = callfree;\n            callfree = p2;\n            break;\n        }\n    }\n    splx(s);\n}\n\nvoid\nprofil()\n{\n    register struct a {\n        unsigned *bufbase;\n        unsigned bufsize;\n        unsigned pcoffset;\n        unsigned pcscale;\n    } *uap = (struct a*) u.u_arg;\n    register struct uprof *upp = &u.u_prof;\n\n    upp->pr_base = uap->bufbase;\n    upp->pr_size = uap->bufsize;\n    upp->pr_off = uap->pcoffset;\n    upp->pr_scale = uap->pcscale;\n}\n\n/*\n * Compute number of hz until specified time.\n * Used to compute third argument to timeout() from an\n * absolute time.\n */\nint\nhzto(tv)\n    register struct timeval *tv;\n{\n    register long ticks;\n    register long sec;\n    register int s = splhigh();\n\n    /*\n     * If number of milliseconds will fit in 32 bit arithmetic,\n     * then compute number of milliseconds to time and scale to\n     * ticks.  Otherwise just compute number of hz in time, rounding\n     * times greater than representible to maximum value.\n     *\n     * Delta times less than 25 days can be computed ``exactly''.\n     * Maximum value for any timeout in 10ms ticks is 250 days.\n     */\n    sec = tv->tv_sec - time.tv_sec;\n    if (sec <= 0x7fffffff / 1000 - 1000)\n        ticks = ((tv->tv_sec - time.tv_sec) * 1000 +\n            (tv->tv_usec - time.tv_usec) / 1000) / (1000/hz);\n    else if (sec <= 0x7fffffff / hz)\n        ticks = sec * hz;\n    else\n        ticks = 0x7fffffff;\n    splx(s);\n#ifdef pdp11\n    /* stored in an \"int\", so 16-bit max */\n    if (ticks > 0x7fff)\n        ticks = 0x7fff;\n#endif\n    return ((int)ticks);\n}\n\n/*\n * Initialize callouts.\n */\nvoid\ncoutinit()\n{\n    int i;\n\n    callfree = callout;\n    for (i=1; i<NCALL; i++)\n        callout[i-1].c_next = &callout[i];\n}\n"
  },
  {
    "path": "sys/kern/kern_descrip.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/file.h>\n#include <sys/systm.h>\n#include <sys/inode.h>\n#include <sys/ioctl.h>\n#include <sys/stat.h>\n#include <sys/conf.h>\n#ifdef INET\n#include <sys/socket.h>\n#include <sys/socketvar.h>\n#endif\n#include <sys/syslog.h>\n\n/*\n * Descriptor management.\n */\n\n/*\n * Allocate a user file descriptor.\n */\nstatic int\nufalloc(i)\n    register int i;\n{\n    for (; i < NOFILE; i++)\n        if (u.u_ofile[i] == NULL) {\n            u.u_rval = i;\n            u.u_pofile[i] = 0;\n            if (i > u.u_lastfile)\n                u.u_lastfile = i;\n            return (i);\n        }\n    u.u_error = EMFILE;\n    return (-1);\n}\n\n/*\n * System calls on descriptors.\n */\nvoid\ngetdtablesize()\n{\n    u.u_rval = NOFILE;\n}\n\nstatic void\ndupit(fd, fp, flags)\n    register int fd;\n    register struct file *fp;\n    int flags;\n{\n    u.u_ofile[fd] = fp;\n    u.u_pofile[fd] = flags;\n    fp->f_count++;\n    if (fd > u.u_lastfile)\n        u.u_lastfile = fd;\n}\n\nvoid\ndup()\n{\n    register struct a {\n        int i;\n    } *uap = (struct a *) u.u_arg;\n    register struct file *fp;\n    register int j;\n\n    if (uap->i &~ 077) { uap->i &= 077; dup2(); return; }   /* XXX */\n\n    GETF(fp, uap->i);\n    j = ufalloc(0);\n    if (j < 0)\n        return;\n    dupit(j, fp, u.u_pofile[uap->i] &~ UF_EXCLOSE);\n}\n\nvoid\ndup2()\n{\n    register struct a {\n        int i, j;\n    } *uap = (struct a *) u.u_arg;\n    register struct file *fp;\n\n    GETF(fp, uap->i);\n    if (uap->j < 0 || uap->j >= NOFILE) {\n        u.u_error = EBADF;\n        return;\n    }\n    u.u_rval = uap->j;\n    if (uap->i == uap->j)\n        return;\n    if (u.u_ofile[uap->j])\n        /*\n         * dup2 must succeed even if the close has an error.\n         */\n        (void) closef(u.u_ofile[uap->j]);\n    dupit(uap->j, fp, u.u_pofile[uap->i] &~ UF_EXCLOSE);\n}\n\n/*\n * The file control system call.\n */\nvoid\nfcntl()\n{\n    register struct file *fp;\n    register struct a {\n        int fdes;\n        int cmd;\n        int arg;\n    } *uap;\n    register int i;\n    register char *pop;\n\n    uap = (struct a *)u.u_arg;\n    fp = getf(uap->fdes);\n    if (fp == NULL)\n        return;\n    pop = &u.u_pofile[uap->fdes];\n    switch(uap->cmd) {\n    case F_DUPFD:\n        i = uap->arg;\n        if (i < 0 || i >= NOFILE) {\n            u.u_error = EINVAL;\n            return;\n        }\n        if ((i = ufalloc(i)) < 0)\n            return;\n        dupit(i, fp, *pop &~ UF_EXCLOSE);\n        break;\n\n    case F_GETFD:\n        u.u_rval = *pop & 1;\n        break;\n\n    case F_SETFD:\n        *pop = (*pop &~ 1) | (uap->arg & 1);\n        break;\n\n    case F_GETFL:\n        u.u_rval = OFLAGS(fp->f_flag);\n        break;\n\n    case F_SETFL:\n        fp->f_flag &= ~FCNTLFLAGS;\n        fp->f_flag |= (FFLAGS(uap->arg)) & FCNTLFLAGS;\n        u.u_error = fset (fp, FNONBLOCK, fp->f_flag & FNONBLOCK);\n        if (u.u_error)\n            break;\n        u.u_error = fset (fp, FASYNC, fp->f_flag & FASYNC);\n        if (u.u_error)\n            (void) fset (fp, FNONBLOCK, 0);\n        break;\n\n    case F_GETOWN:\n        u.u_error = fgetown (fp, &u.u_rval);\n        break;\n\n    case F_SETOWN:\n        u.u_error = fsetown (fp, uap->arg);\n        break;\n\n    default:\n        u.u_error = EINVAL;\n    }\n}\n\nint\nfioctl(fp, cmd, value)\n    register struct file *fp;\n    u_int cmd;\n    caddr_t value;\n{\n    return ((*Fops[fp->f_type]->fo_ioctl)(fp, cmd, value));\n}\n\n/*\n * Set/clear file flags: nonblock and async.\n */\nint\nfset (fp, bit, value)\n    register struct file *fp;\n    int bit, value;\n{\n    if (value)\n        fp->f_flag |= bit;\n    else\n        fp->f_flag &= ~bit;\n    return (fioctl(fp, (u_int)(bit == FNONBLOCK ? FIONBIO : FIOASYNC),\n            (caddr_t)&value));\n}\n\n/*\n * Get process group id for a file.\n */\nint\nfgetown(fp, valuep)\n    register struct file *fp;\n    register int *valuep;\n{\n    register int error;\n\n#ifdef INET\n    if (fp->f_type == DTYPE_SOCKET) {\n        *valuep = mfsd(&fp->f_socket->so_pgrp);\n        return (0);\n    }\n#endif\n    error = fioctl(fp, (u_int)TIOCGPGRP, (caddr_t)valuep);\n    *valuep = -*valuep;\n    return (error);\n}\n\n/*\n * Set process group id for a file.\n */\nint\nfsetown(fp, value)\n    register struct file *fp;\n    int value;\n{\n#ifdef INET\n    if (fp->f_type == DTYPE_SOCKET) {\n        mtsd(&fp->f_socket->so_pgrp, value);\n        return (0);\n    }\n#endif\n    if (value > 0) {\n        register struct proc *p = pfind(value);\n        if (p == 0)\n            return (ESRCH);\n        value = p->p_pgrp;\n    } else\n        value = -value;\n    return (fioctl(fp, (u_int)TIOCSPGRP, (caddr_t)&value));\n}\n\nvoid\nclose()\n{\n    register struct a {\n        int i;\n    } *uap = (struct a *)u.u_arg;\n    register struct file *fp;\n\n    GETF(fp, uap->i);\n    u.u_ofile[uap->i] = NULL;\n    while (u.u_lastfile >= 0 && u.u_ofile[u.u_lastfile] == NULL)\n        u.u_lastfile--;\n    u.u_error = closef(fp);\n    /* WHAT IF u.u_error ? */\n}\n\nvoid\nfstat()\n{\n    register struct file *fp;\n    register struct a {\n        int fdes;\n        struct  stat *sb;\n    } *uap;\n    struct stat ub;\n\n    uap = (struct a *)u.u_arg;\n    fp = getf(uap->fdes);\n    if (fp == NULL)\n        return;\n    switch (fp->f_type) {\n\n    case DTYPE_PIPE:\n    case DTYPE_INODE:\n        u.u_error = ino_stat((struct inode *)fp->f_data, &ub);\n        if (fp->f_type == DTYPE_PIPE)\n            ub.st_size -= fp->f_offset;\n        break;\n\n#ifdef INET\n    case DTYPE_SOCKET:\n        u.u_error = SOO_STAT(fp->f_socket, &ub);\n        break;\n#endif\n    default:\n        u.u_error = EINVAL;\n        break;\n    }\n    if (u.u_error == 0)\n        u.u_error = copyout((caddr_t)&ub, (caddr_t)uap->sb,\n            sizeof (ub));\n}\n\nstruct  file *lastf;\n\n/*\n * Allocate a user file descriptor\n * and a file structure.\n * Initialize the descriptor\n * to point at the file structure.\n */\nstruct file *\nfalloc()\n{\n    register struct file *fp;\n    register int i;\n\n    i = ufalloc(0);\n    if (i < 0)\n        return (NULL);\n    if (lastf == 0)\n        lastf = file;\n    for (fp = lastf; fp < file+NFILE; fp++)\n        if (fp->f_count == 0)\n            goto slot;\n    for (fp = file; fp < lastf; fp++)\n        if (fp->f_count == 0)\n            goto slot;\n    log(LOG_ERR, \"file: table full\\n\");\n    u.u_error = ENFILE;\n    return (NULL);\nslot:\n    u.u_ofile[i] = fp;\n    fp->f_count = 1;\n    fp->f_data = 0;\n    fp->f_offset = 0;\n    lastf = fp + 1;\n    return (fp);\n}\n\n/*\n * Convert a user supplied file descriptor into a pointer\n * to a file structure.  Only task is to check range of the descriptor.\n * Critical paths should use the GETF macro unless code size is a\n * consideration.\n */\nstruct file *\ngetf(f)\n    register int f;\n{\n    register struct file *fp;\n\n    if ((unsigned)f >= NOFILE || (fp = u.u_ofile[f]) == NULL) {\n        u.u_error = EBADF;\n        return (NULL);\n    }\n    return (fp);\n}\n\n/*\n * Internal form of close.\n * Decrement reference count on file structure.\n */\nint\nclosef(fp)\n    register struct file *fp;\n{\n    int error;\n\n    if (fp == NULL)\n        return(0);\n    if (fp->f_count > 1) {\n        fp->f_count--;\n        return(0);\n    }\n\n    if  ((fp->f_flag & (FSHLOCK|FEXLOCK)) && fp->f_type == DTYPE_INODE)\n        ino_unlock(fp, FSHLOCK|FEXLOCK);\n\n    error = (*Fops[fp->f_type]->fo_close)(fp);\n    fp->f_count = 0;\n    return(error);\n}\n\n/*\n * Apply an advisory lock on a file descriptor.\n */\nvoid\nflock()\n{\n    register struct a {\n        int fd;\n        int how;\n    } *uap = (struct a *)u.u_arg;\n    register struct file *fp;\n    int error;\n\n    if ((fp = getf(uap->fd)) == NULL)\n        return;\n    if (fp->f_type != DTYPE_INODE) {\n        u.u_error = EOPNOTSUPP;\n        return;\n    }\n    if (uap->how & LOCK_UN) {\n        ino_unlock(fp, FSHLOCK | FEXLOCK);\n        return;\n    }\n    if ((uap->how & (LOCK_SH | LOCK_EX)) == 0)\n        return;                 /* error? */\n    if (uap->how & LOCK_EX)\n        uap->how &= ~LOCK_SH;\n    /* avoid work... */\n    if ((fp->f_flag & FEXLOCK) && (uap->how & LOCK_EX))\n        return;\n    if ((fp->f_flag & FSHLOCK) && (uap->how & LOCK_SH))\n        return;\n    error = ino_lock(fp, uap->how);\n    u.u_error = error;\n}\n\n/*\n * File Descriptor pseudo-device driver (/dev/fd/).\n *\n * Opening minor device N dup()s the file (if any) connected to file\n * descriptor N belonging to the calling process.  Note that this driver\n * consists of only the ``open()'' routine, because all subsequent\n * references to this file will be direct to the other driver.\n */\n/* ARGSUSED */\nint\nfdopen(dev, mode, type)\n    dev_t dev;\n    int mode, type;\n{\n    /*\n     * XXX Kludge: set u.u_dupfd to contain the value of the\n     * the file descriptor being sought for duplication. The error\n     * return ensures that the vnode for this device will be released\n     * by vn_open. Open will detect this special error and take the\n     * actions in dupfdopen below. Other callers of vn_open will\n     * simply report the error.\n     */\n    u.u_dupfd = minor(dev);\n    return(ENODEV);\n}\n\n/*\n * Duplicate the specified descriptor to a free descriptor.\n */\nint\ndupfdopen (indx, dfd, mode, error)\n    register int indx, dfd;\n    int mode;\n    int error;\n{\n    register struct file *wfp;\n    struct file *fp;\n\n    /*\n     * If the to-be-dup'd fd number is greater than the allowed number\n     * of file descriptors, or the fd to be dup'd has already been\n     * closed, reject.  Note, check for new == old is necessary as\n     * falloc could allocate an already closed to-be-dup'd descriptor\n     * as the new descriptor.\n     */\n    fp = u.u_ofile[indx];\n    if  (dfd >= NOFILE || (wfp = u.u_ofile[dfd]) == NULL || fp == wfp)\n        return(EBADF);\n\n    /*\n     * There are two cases of interest here.\n     *\n     * For ENODEV simply dup (dfd) to file descriptor\n     * (indx) and return.\n     *\n     * For ENXIO steal away the file structure from (dfd) and\n     * store it in (indx).  (dfd) is effectively closed by\n     * this operation.\n     *\n     * NOTE: ENXIO only comes out of the 'portal fs' code of 4.4 - since\n     * 2.11BSD does not implement the portal fs the code is ifdef'd out\n     * and a short message output.\n     *\n     * Any other error code is just returned.\n     */\n    switch  (error) {\n    case ENODEV:\n        /*\n         * Check that the mode the file is being opened for is a\n         * subset of the mode of the existing descriptor.\n         */\n        if (((mode & (FREAD|FWRITE)) | wfp->f_flag) != wfp->f_flag)\n            return(EACCES);\n        u.u_ofile[indx] = wfp;\n        u.u_pofile[indx] = u.u_pofile[dfd];\n        wfp->f_count++;\n        if  (indx > u.u_lastfile)\n            u.u_lastfile = indx;\n        return(0);\n#ifdef  haveportalfs\n    case ENXIO:\n        /*\n         * Steal away the file pointer from dfd, and stuff it into indx.\n         */\n        fdp->fd_ofiles[indx] = fdp->fd_ofiles[dfd];\n        fdp->fd_ofiles[dfd] = NULL;\n        fdp->fd_ofileflags[indx] = fdp->fd_ofileflags[dfd];\n        fdp->fd_ofileflags[dfd] = 0;\n        /*\n         * Complete the clean up of the filedesc structure by\n         * recomputing the various hints.\n         */\n        if (indx > fdp->fd_lastfile)\n            fdp->fd_lastfile = indx;\n        else\n            while (fdp->fd_lastfile > 0 &&\n                   fdp->fd_ofiles[fdp->fd_lastfile] == NULL)\n                fdp->fd_lastfile--;\n            if (dfd < fdp->fd_freefile)\n                fdp->fd_freefile = dfd;\n        return (0);\n#else\n        log(LOG_NOTICE, \"dupfdopen\");\n        /* FALLTHROUGH */\n#endif\n    default:\n        return(error);\n    }\n    /* NOTREACHED */\n}\n"
  },
  {
    "path": "sys/kern/kern_exec.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/map.h>\n#include <sys/inode.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/buf.h>\n#include <sys/namei.h>\n#include <sys/fs.h>\n#include <sys/mount.h>\n#include <sys/file.h>\n#include <sys/signalvar.h>\n#include <sys/exec.h>\n#include <machine/debug.h>\n\n/*\n * exec system call, with and without environments.\n */\nstruct execa {\n    char    *fname;\n    char    **argp;\n    char    **envp;\n};\n\n/*\n * This is the internal form of the exec() function.\n *\n * It is called with the inode of the executable\n * and the exec_params structure, which is used to\n * keep information during the exec.\n *\n * It returns the error code, and with the ip still locked.\n */\nint exec_check(struct exec_params *epp)\n{\n    int error, i, r;\n\n    DEBUG(\"\\texec_check(): start\\n\");\n    if (access (epp->ip, IEXEC))\n        return ENOEXEC;\n    if ((u.u_procp->p_flag & P_TRACED) && access (epp->ip, IREAD))\n        return ENOEXEC;\n    if ((epp->ip->i_mode & IFMT) != IFREG ||\n        (epp->ip->i_mode & (IEXEC | (IEXEC>>3) | (IEXEC>>6))) == 0)\n        return EACCES;\n\n    /*\n     * Read in first few bytes of file for segment sizes, magic number:\n     *  407 = plain executable\n     * Also an ASCII line beginning with #! is\n     * the file name of a ``interpreter'' and arguments may be prepended\n     * to the argument list if given here.\n     *\n     * INTERPRETER NAMES ARE LIMITED IN LENGTH.\n     *\n     * ONLY ONE ARGUMENT MAY BE PASSED TO THE INTERPRETER FROM\n     * THE ASCII LINE.\n     */\n\n    /*\n     * Read the first 'SHSIZE' bytes from the file to execute\n     */\n    DEBUG(\"\\texec_check(): read header %d bytes\\n\", sizeof(epp->hdr));\n    epp->hdr.sh[0] = '\\0';      /* for zero length files */\n    error = rdwri(UIO_READ, epp->ip, (caddr_t) &epp->hdr, sizeof(epp->hdr),\n               (off_t)0, IO_UNIT, &r);\n    if (error)\n        return error;\n    epp->hdr_len = sizeof(epp->hdr) - r;\n\n    /*\n     * Given the first part of the image\n     * loop through the exec file handlers to find\n     * someone who can handle this file format.\n     */\n    error = ENOEXEC;\n    DEBUG(\"\\texec_check(): trying %d exec formats\\n\", nexecs);\n    for (i = 0; i < nexecs && error != 0; i++) {\n        DEBUG(\"\\texec_check(): trying format %d: %s\\n\", i, execsw[i].es_name);\n        if (execsw[i].es_check == NULL)\n            continue;\n        error = (*execsw[i].es_check)(epp);\n        if (error == 0)\n            break;\n    }\n\n    DEBUG(\"\\texec_check(): end\\n\");\n\n    return error;\n}\n\nvoid\nexecv()\n{\n    struct execa *arg = (struct execa *)u.u_arg;\n\n    arg->envp = NULL;\n    execve();\n}\n\nvoid\nexecve()\n{\n    struct execa *uap = (struct execa *)u.u_arg;\n    int error;\n    struct inode *ip;\n    struct nameidata nd;\n    register struct nameidata *ndp = &nd;\n    struct exec_params eparam;\n\n    DEBUG(\"\\n\\texecve(): start\\n\");\n    DEBUG(\"\\texecve(): args: '%s', ['%s', '%s', ...]\\n\",\n      uap->fname, uap->argp[0], uap->argp[1]);\n    NDINIT (ndp, LOOKUP, FOLLOW, uap->fname);\n    ip = namei (ndp);\n    if (ip == NULL) {\n        DEBUG(\"\\texecve(): file '%s' not found\\n\", uap->fname);\n        return;\n    }\n    /*\n     * The exec_param structure is used to\n     * keep information about the executable during exec's processing\n     */\n    bzero(&eparam, sizeof eparam);\n    eparam.userfname = uap->fname;\n    eparam.userargp = uap->argp;\n    eparam.userenvp = uap->envp;\n    eparam.uid = u.u_uid;\n    eparam.gid = u.u_groups[0];\n\n    if (ip->i_fs->fs_flags & MNT_NOEXEC) {\n        u.u_error = EACCES;\n        DEBUG(\"\\texecve(): EACCES\\n\");\n        goto done;\n    }\n    if ((ip->i_fs->fs_flags & MNT_NOSUID) == 0) {\n        if (ip->i_mode & ISUID)\n            eparam.uid = ip->i_uid;\n        if (ip->i_mode & ISGID)\n            eparam.gid = ip->i_gid;\n    }\n\n    eparam.ip = ip;\n    if ((error = exec_check(&eparam)))\n        u.u_error = error;\ndone:\n    exec_alloc_freeall(&eparam);\n    if (ip)\n        iput(ip);\n\n    DEBUG(\"\\texecve(): end\\n\\n\");\n}\n"
  },
  {
    "path": "sys/kern/kern_exit.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/map.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/inode.h>\n#include <sys/vm.h>\n#include <sys/file.h>\n#include <sys/wait.h>\n#include <sys/kernel.h>\n\n/*\n * Notify parent that vfork child is finished with parent's data.  Called\n * during exit/exec(getxfile).  The child\n * must be locked in core so it will be in core when the parent runs.\n */\nvoid\nendvfork()\n{\n    register struct proc *rip, *rpp;\n\n    rpp = u.u_procp;\n    rip = rpp->p_pptr;\n    rpp->p_flag &= ~SVFORK;\n    rpp->p_flag |= SLOCK;\n    wakeup ((caddr_t) rpp);\n    while (! (rpp->p_flag & SVFDONE))\n        sleep ((caddr_t) rip, PZERO-1);\n    /*\n     * The parent has taken back our data+stack, set our sizes to 0.\n     */\n    u.u_dsize = rpp->p_dsize = 0;\n    u.u_ssize = rpp->p_ssize = 0;\n    rpp->p_flag &= ~(SVFDONE | SLOCK);\n}\n\n/*\n * Exit: deallocate address space and other resources,\n * change proc state to zombie, and unlink proc from allproc\n * list.  Save exit status and rusage for wait4().\n * Check for child processes and orphan them.\n */\nvoid\nexit (rv)\n    int rv;\n{\n    register int i;\n    register struct proc *p;\n    struct  proc **pp;\n\n    p = u.u_procp;\n    p->p_flag &= ~P_TRACED;\n    p->p_sigignore = ~0;\n    p->p_sig = 0;\n    /*\n     * 2.11 doesn't need to do this and it gets overwritten anyway.\n     * p->p_realtimer.it_value = 0;\n     */\n    for (i = 0; i <= u.u_lastfile; i++) {\n        register struct file *f;\n\n        f = u.u_ofile[i];\n        u.u_ofile[i] = NULL;\n        u.u_pofile[i] = 0;\n        (void) closef(f);\n    }\n    ilock(u.u_cdir);\n    iput(u.u_cdir);\n    if (u.u_rdir) {\n        ilock(u.u_rdir);\n        iput(u.u_rdir);\n    }\n    u.u_rlimit[RLIMIT_FSIZE].rlim_cur = RLIM_INFINITY;\n\n    if (p->p_flag & SVFORK)\n        endvfork();\n\n    if (p->p_pid == 1)\n        panic(\"init died\");\n    if ((*p->p_prev = p->p_nxt) != NULL)        /* off allproc queue */\n        p->p_nxt->p_prev = p->p_prev;\n    p->p_nxt = zombproc;                            /* onto zombproc */\n    if (p->p_nxt != NULL)\n        p->p_nxt->p_prev = &p->p_nxt;\n    p->p_prev = &zombproc;\n    zombproc = p;\n    p->p_stat = SZOMB;\n\n    noproc = 1;\n    for (pp = &pidhash[PIDHASH(p->p_pid)]; *pp; pp = &(*pp)->p_hash)\n        if (*pp == p) {\n            *pp = p->p_hash;\n            goto done;\n        }\n    panic(\"exit\");\ndone:\n    /*\n     * Overwrite p_alive substructure of proc - better not be anything\n     * important left!\n     */\n    p->p_xstat = rv;\n    p->p_ru = u.u_ru;\n    ruadd(&p->p_ru, &u.u_cru);\n    {\n        register struct proc *q;\n        int doingzomb = 0;\n\n        q = allproc;\nagain:\n        for(; q; q = q->p_nxt)\n            if (q->p_pptr == p) {\n                q->p_pptr = &proc[1];\n                q->p_ppid = 1;\n                wakeup((caddr_t)&proc[1]);\n                if (q->p_flag& P_TRACED) {\n                    q->p_flag &= ~P_TRACED;\n                    psignal(q, SIGKILL);\n                } else if (q->p_stat == SSTOP) {\n                    psignal(q, SIGHUP);\n                    psignal(q, SIGCONT);\n                }\n            }\n        if (!doingzomb) {\n            doingzomb = 1;\n            q = zombproc;\n            goto again;\n        }\n    }\n    psignal(p->p_pptr, SIGCHLD);\n    wakeup((caddr_t) p->p_pptr);\n    wakeup((caddr_t) &runin);\n    swtch();\n    /* NOTREACHED */\n}\n\n/*\n * exit system call: pass back caller's arg\n */\nvoid\nrexit()\n{\n    register struct a {\n        int rval;\n    } *uap = (struct a*) u.u_arg;\n\n    exit (W_EXITCODE (uap->rval, 0));\n    /* NOTREACHED */\n}\n\nstruct args {\n    int pid;\n    int *status;\n    int options;\n    struct rusage *rusage;\n};\n\n/*\n * Wait: check child processes to see if any have exited,\n * stopped under trace or (optionally) stopped by a signal.\n * Pass back status and make available for reuse the exited\n * child's proc structure.\n */\nstatic int\nwait1 (q, uap, retval)\n    struct proc *q;\n    register struct args *uap;\n    int retval[];\n{\n    int nfound, status;\n    struct rusage ru;                   /* used for local conversion */\n    register struct proc *p;\n    register int error;\n\n    if (uap->pid == WAIT_MYPGRP)        /* == 0 */\n        uap->pid = -q->p_pgrp;\nloop:\n    nfound = 0;\n    /*\n     * 4.X has child links in the proc structure, so they consolidate\n     * these two tests into one loop.  We only have the zombie chain\n     * and the allproc chain, so we check for ZOMBIES first, then for\n     * children that have changed state.  We check for ZOMBIES first\n     * because they are more common, and, as the list is typically small,\n     * a faster check.\n     */\n    for (p = zombproc; p; p = p->p_nxt) {\n        if (p->p_pptr != q) /* are we the parent of this process? */\n            continue;\n        if (uap->pid != WAIT_ANY &&\n            p->p_pid != uap->pid && p->p_pgrp != -uap->pid)\n            continue;\n        retval[0] = p->p_pid;\n        retval[1] = p->p_xstat;\n        if (uap->status && (error = copyout ((caddr_t) &p->p_xstat,\n            (caddr_t) uap->status, sizeof (uap->status))))\n            return(error);\n        if (uap->rusage) {\n            rucvt(&ru, &p->p_ru);\n            error = copyout ((caddr_t) &ru, (caddr_t) uap->rusage, sizeof (ru));\n            if (error)\n                return(error);\n        }\n        ruadd(&u.u_cru, &p->p_ru);\n        p->p_xstat = 0;\n        p->p_stat = NULL;\n        p->p_pid = 0;\n        p->p_ppid = 0;\n        if ((*p->p_prev = p->p_nxt) != NULL)    /* off zombproc */\n            p->p_nxt->p_prev = p->p_prev;\n        p->p_nxt = freeproc;                    /* onto freeproc */\n        freeproc = p;\n        p->p_pptr = 0;\n        p->p_sig = 0;\n        p->p_sigcatch = 0;\n        p->p_sigignore = 0;\n        p->p_sigmask = 0;\n        p->p_pgrp = 0;\n        p->p_flag = 0;\n        p->p_wchan = 0;\n        return (0);\n    }\n    for (p = allproc; p;p = p->p_nxt) {\n        if (p->p_pptr != q)\n            continue;\n        if (uap->pid != WAIT_ANY &&\n            p->p_pid != uap->pid && p->p_pgrp != -uap->pid)\n            continue;\n        ++nfound;\n        if (p->p_stat == SSTOP && ! (p->p_flag & P_WAITED) &&\n            (p->p_flag & P_TRACED || uap->options & WUNTRACED)) {\n            p->p_flag |= P_WAITED;\n            retval[0] = p->p_pid;\n            error = 0;\n            if (uap->status) {\n                status = W_STOPCODE(p->p_ptracesig);\n                error = copyout ((caddr_t) &status,\n                    (caddr_t) uap->status, sizeof (status));\n            }\n            return (error);\n        }\n    }\n    if (nfound == 0)\n        return (ECHILD);\n    if (uap->options&WNOHANG) {\n        retval[0] = 0;\n        return (0);\n    }\n    error = tsleep ((caddr_t) q, PWAIT|PCATCH, 0);\n    if (error == 0)\n        goto loop;\n    return(error);\n}\n\nvoid\nwait4()\n{\n    int retval[2];\n    register struct args *uap = (struct args*) u.u_arg;\n\n    retval[0] = 0;\n    u.u_error = wait1 (u.u_procp, uap, retval);\n    if (! u.u_error)\n        u.u_rval = retval[0];\n}\n\nvoid\nreboot()\n{\n    struct a {\n        int opt;\n    };\n\n    if (suser ())\n        boot (rootdev, ((struct a*)u.u_arg)->opt);\n}\n"
  },
  {
    "path": "sys/kern/kern_fork.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/map.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/inode.h>\n#include <sys/file.h>\n#include <sys/vm.h>\n#include <sys/kernel.h>\n#include <sys/syslog.h>\n\nint     mpid;           /* generic for unique process id's */\n\n/*\n * Create a new process -- the internal version of system call fork.\n * It returns 1 in the new process, 0 in the old.\n */\nint\nnewproc (isvfork)\n    int isvfork;\n{\n    register struct proc *child, *parent;\n    register int n;\n    static int pidchecked = 0;\n    struct file *fp;\n\n    /*\n     * First, just locate a slot for a process\n     * and copy the useful info from this process into it.\n     * The panic \"cannot happen\" because fork has already\n     * checked for the existence of a slot.\n     */\n    mpid++;\nretry:\n    if (mpid >= 30000) {\n        mpid = 100;\n        pidchecked = 0;\n    }\n    if (mpid >= pidchecked) {\n        int doingzomb = 0;\n\n        pidchecked = 30000;\n        /*\n         * Scan the proc table to check whether this pid\n         * is in use.  Remember the lowest pid that's greater\n         * than mpid, so we can avoid checking for a while.\n         */\n        child = allproc;\nagain:\n        for (; child != NULL; child = child->p_nxt) {\n            if (child->p_pid == mpid || child->p_pgrp == mpid) {\n                mpid++;\n                if (mpid >= pidchecked)\n                    goto retry;\n            }\n            if (child->p_pid > mpid && pidchecked > child->p_pid)\n                pidchecked = child->p_pid;\n            if (child->p_pgrp > mpid && pidchecked > child->p_pgrp)\n                pidchecked = child->p_pgrp;\n        }\n        if (!doingzomb) {\n            doingzomb = 1;\n            child = zombproc;\n            goto again;\n        }\n    }\n    child = freeproc;\n    if (child == NULL)\n        panic(\"no procs\");\n\n    freeproc = child->p_nxt;            /* off freeproc */\n\n    /*\n     * Make a proc table entry for the new process.\n     */\n    parent = u.u_procp;\n    child->p_stat = SIDL;\n    child->p_realtimer.it_value = 0;\n    child->p_flag = SLOAD;\n    child->p_uid = parent->p_uid;\n    child->p_pgrp = parent->p_pgrp;\n    child->p_nice = parent->p_nice;\n    child->p_pid = mpid;\n    child->p_ppid = parent->p_pid;\n    child->p_pptr = parent;\n    child->p_time = 0;\n    child->p_cpu = 0;\n    child->p_sigmask = parent->p_sigmask;\n    child->p_sigcatch = parent->p_sigcatch;\n    child->p_sigignore = parent->p_sigignore;\n    /* take along any pending signals like stops? */\n#ifdef UCB_METER\n    if (isvfork) {\n        forkstat.cntvfork++;\n        forkstat.sizvfork += (parent->p_dsize + parent->p_ssize) >> 10;\n    } else {\n        forkstat.cntfork++;\n        forkstat.sizfork += (parent->p_dsize + parent->p_ssize) >> 10;\n    }\n#endif\n    child->p_wchan = 0;\n    child->p_slptime = 0;\n    {\n    struct proc **hash = &pidhash [PIDHASH (child->p_pid)];\n\n    child->p_hash = *hash;\n    *hash = child;\n    }\n    /*\n     * some shuffling here -- in most UNIX kernels, the allproc assign\n     * is done after grabbing the struct off of the freeproc list.  We\n     * wait so that if the clock interrupts us and vmtotal walks allproc\n     * the text pointer isn't garbage.\n     */\n    child->p_nxt = allproc;             /* onto allproc */\n    child->p_nxt->p_prev = &child->p_nxt;   /*   (allproc is never NULL) */\n    child->p_prev = &allproc;\n    allproc = child;\n\n    /*\n     * Increase reference counts on shared objects.\n     */\n    for (n = 0; n <= u.u_lastfile; n++) {\n        fp = u.u_ofile[n];\n        if (fp == NULL)\n            continue;\n        fp->f_count++;\n    }\n    u.u_cdir->i_count++;\n    if (u.u_rdir)\n        u.u_rdir->i_count++;\n\n    /*\n     * When the longjmp is executed for the new process,\n     * here's where it will resume.\n     */\n    if (setjmp (&u.u_ssave)) {\n        return(1);\n    }\n\n    child->p_dsize = parent->p_dsize;\n    child->p_ssize = parent->p_ssize;\n    child->p_daddr = parent->p_daddr;\n    child->p_saddr = parent->p_saddr;\n\n    /*\n     * Partially simulate the environment of the new process so that\n     * when it is actually created (by copying) it will look right.\n     */\n    u.u_procp = child;\n\n    /*\n     * Swap out the current process to generate the copy.\n     */\n    parent->p_stat = SIDL;\n    child->p_addr = parent->p_addr;\n    child->p_stat = SRUN;\n    swapout (child, X_DONTFREE, X_OLDSIZE, X_OLDSIZE);\n    child->p_flag |= SSWAP;\n    parent->p_stat = SRUN;\n    u.u_procp = parent;\n\n    if (isvfork) {\n        /*\n         * Wait for the child to finish with it.\n         * RetroBSD: to make this work, significant\n         * changes in scheduler are required.\n         */\n        parent->p_dsize = 0;\n        parent->p_ssize = 0;\n        child->p_flag |= SVFORK;\n        parent->p_flag |= SVFPRNT;\n        while (child->p_flag & SVFORK)\n            sleep ((caddr_t)child, PSWP+1);\n        if ((child->p_flag & SLOAD) == 0)\n            panic (\"newproc vfork\");\n        u.u_dsize = parent->p_dsize = child->p_dsize;\n        parent->p_daddr = child->p_daddr;\n        child->p_dsize = 0;\n        u.u_ssize = parent->p_ssize = child->p_ssize;\n        parent->p_saddr = child->p_saddr;\n        child->p_ssize = 0;\n        child->p_flag |= SVFDONE;\n        wakeup ((caddr_t) parent);\n        parent->p_flag &= ~SVFPRNT;\n    }\n    return(0);\n}\n\nstatic void\nfork1 (isvfork)\n    int isvfork;\n{\n    register int a;\n    register struct proc *p1, *p2;\n\n    a = 0;\n    if (u.u_uid != 0) {\n        for (p1 = allproc; p1; p1 = p1->p_nxt)\n            if (p1->p_uid == u.u_uid)\n                a++;\n        for (p1 = zombproc; p1; p1 = p1->p_nxt)\n            if (p1->p_uid == u.u_uid)\n                a++;\n    }\n    /*\n     * Disallow if\n     *  No processes at all;\n     *  not su and too many procs owned; or\n     *  not su and would take last slot.\n     */\n    p2 = freeproc;\n    if (p2==NULL)\n        log(LOG_ERR, \"proc: table full\\n\");\n\n    if (p2==NULL || (u.u_uid!=0 && (p2->p_nxt == NULL || a>MAXUPRC))) {\n        u.u_error = EAGAIN;\n        return;\n    }\n    p1 = u.u_procp;\n    if (newproc (isvfork)) {\n        /* Child */\n        u.u_rval = 0;\n        u.u_start = time.tv_sec;\n        bzero(&u.u_ru, sizeof(u.u_ru));\n        bzero(&u.u_cru, sizeof(u.u_cru));\n        return;\n    }\n    /* Parent */\n    u.u_rval = p2->p_pid;\n}\n\n/*\n * fork system call\n */\nvoid\nfork()\n{\n    fork1 (0);\n}\n\n/*\n * vfork system call, fast version of fork\n */\nvoid\nvfork()\n{\n    fork1 (1);\n}\n"
  },
  {
    "path": "sys/kern/kern_glob.c",
    "content": "/*\n * Global memory area system.\n *\n * Works with two system calls:\n *\n * byte = rdglob(addr);\n * success = wrglob(addr,byte);\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/user.h>\n\n#ifndef GLOBSZ\n#define GLOBSZ 256\n#endif\n\nunsigned char global_segment[GLOBSZ];\n\nvoid rdglob()\n{\n    struct a {\n        int    addr;\n    } *uap = (struct a *)u.u_arg;\n\n    // Only root should have access to the shared memory block\n    if(u.u_uid!=0)\n    {\n        u.u_rval = -1;\n        return;\n    }\n\n    if(uap->addr>=GLOBSZ)\n    {\n        u.u_rval = -1;\n        return;\n    }\n    u.u_rval = global_segment[uap->addr];\n}\n\nvoid wrglob()\n{\n    struct a {\n        int         addr;\n        unsigned char   value;\n    } *uap = (struct a *)u.u_arg;\n\n    // Only root should have access to the shared memory block\n    if(u.u_uid!=0)\n    {\n        u.u_rval = -1;\n        return;\n    }\n\n    if(uap->addr>=GLOBSZ)\n    {\n        u.u_rval = -1;\n        return;\n    }\n    u.u_rval = 0;\n    global_segment[uap->addr] = uap->value;\n}\n"
  },
  {
    "path": "sys/kern/kern_mman.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/vm.h>\n#include <sys/systm.h>\n\nvoid\nbrk()\n{\n    struct a {\n        int naddr;\n    };\n    register int newsize, d;\n\n    /* set newsize to new data size */\n    newsize = ((struct a*)u.u_arg)->naddr - u.u_procp->p_daddr;\n    if (newsize < 0)\n        newsize = 0;\n    if (u.u_tsize + newsize + u.u_ssize > MAXMEM) {\n        u.u_error = ENOMEM;\n        return;\n    }\n\n    u.u_procp->p_dsize = newsize;\n\n    /* set d to (new - old) */\n    d = newsize - u.u_dsize;\n//printf (\"brk: new size %u bytes, incremented by %d\\n\", newsize, d);\n    if (d > 0)\n        bzero ((void*) (u.u_procp->p_daddr + u.u_dsize), d);\n    u.u_dsize = newsize;\n    u.u_rval = u.u_procp->p_daddr + u.u_dsize;\n}\n"
  },
  {
    "path": "sys/kern/kern_proc.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/systm.h>\n\n/*\n * Is p an inferior of the current process?\n */\nint\ninferior(p)\n    register struct proc *p;\n{\n    for (; p != u.u_procp; p = p->p_pptr)\n        if (p->p_ppid == 0)\n            return (0);\n    return (1);\n}\n\n/*\n * Find a process by pid.\n */\nstruct proc *\npfind (pid)\n    register int pid;\n{\n    register struct proc *p = pidhash [PIDHASH(pid)];\n\n    for (; p; p = p->p_hash)\n        if (p->p_pid == pid)\n            return (p);\n    return ((struct proc *)0);\n}\n\n/*\n * init the process queues\n */\nvoid\npqinit()\n{\n    register struct proc *p;\n\n    /*\n     * most procs are initially on freequeue\n     *  nb: we place them there in their \"natural\" order.\n     */\n\n    freeproc = NULL;\n    for (p = proc+NPROC; --p > proc; freeproc = p)\n        p->p_nxt = freeproc;\n\n    /*\n     * but proc[0] is special ...\n     */\n\n    allproc = p;\n    p->p_nxt = NULL;\n    p->p_prev = &allproc;\n\n    zombproc = NULL;\n}\n"
  },
  {
    "path": "sys/kern/kern_prot.c",
    "content": "/*\n * System calls related to processes and protection.\n *\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/systm.h>\n\nvoid\ngetpid()\n{\n    u.u_rval = u.u_procp->p_pid;\n}\n\nvoid\ngetppid()\n{\n    u.u_rval = u.u_procp->p_ppid;\n}\n\nvoid\ngetpgrp()\n{\n    register struct a {\n        int pid;\n    } *uap = (struct a *)u.u_arg;\n    register struct proc *p;\n\n    if (uap->pid == 0)      /* silly... */\n        uap->pid = u.u_procp->p_pid;\n    p = pfind(uap->pid);\n    if (p == 0) {\n        u.u_error = ESRCH;\n        return;\n    }\n    u.u_rval = p->p_pgrp;\n}\n\nvoid\ngetuid()\n{\n    u.u_rval = u.u_ruid;\n}\n\nvoid\ngeteuid()\n{\n    u.u_rval = u.u_uid;\n}\n\nvoid\ngetgid()\n{\n    u.u_rval = u.u_rgid;\n}\n\nvoid\ngetegid()\n{\n    u.u_rval = u.u_groups[0];\n}\n\n/*\n * getgroups and setgroups differ from 4.X because the VAX stores group\n * entries in the user structure as shorts and has to convert them to ints.\n */\nvoid\ngetgroups()\n{\n    register struct a {\n        u_int   gidsetsize;\n        int *gidset;\n    } *uap = (struct a *)u.u_arg;\n    register gid_t *gp;\n\n    for (gp = &u.u_groups[NGROUPS]; gp > u.u_groups; gp--)\n        if (gp[-1] != NOGROUP)\n            break;\n    if (uap->gidsetsize < gp - u.u_groups) {\n        u.u_error = EINVAL;\n        return;\n    }\n    uap->gidsetsize = gp - u.u_groups;\n    u.u_error = copyout((caddr_t)u.u_groups, (caddr_t)uap->gidset,\n        uap->gidsetsize * sizeof(u.u_groups[0]));\n    if (u.u_error)\n        return;\n    u.u_rval = uap->gidsetsize;\n}\n\nvoid\nsetpgrp()\n{\n    register struct proc *p;\n    register struct a {\n        int pid;\n        int pgrp;\n    } *uap = (struct a *)u.u_arg;\n\n    if (uap->pid == 0)      /* silly... */\n        uap->pid = u.u_procp->p_pid;\n    p = pfind(uap->pid);\n    if (p == 0) {\n        u.u_error = ESRCH;\n        return;\n    }\n    /* need better control mechanisms for process groups */\n    if (p->p_uid != u.u_uid && u.u_uid && !inferior(p)) {\n        u.u_error = EPERM;\n        return;\n    }\n    p->p_pgrp = uap->pgrp;\n}\n\nvoid\nsetgroups()\n{\n    register struct a {\n        u_int   gidsetsize;\n        int *gidset;\n    } *uap = (struct a *)u.u_arg;\n    register gid_t *gp;\n\n    if (!suser())\n        return;\n    if (uap->gidsetsize > sizeof (u.u_groups) / sizeof (u.u_groups[0])) {\n        u.u_error = EINVAL;\n        return;\n    }\n    u.u_error = copyin((caddr_t)uap->gidset, (caddr_t)u.u_groups,\n    uap->gidsetsize * sizeof (u.u_groups[0]));\n    if (u.u_error)\n        return;\n    for (gp = &u.u_groups[uap->gidsetsize]; gp < &u.u_groups[NGROUPS]; gp++)\n        *gp = NOGROUP;\n}\n\n/*\n * Check if gid is a member of the group set.\n */\nint\ngroupmember(gid)\n    gid_t gid;\n{\n    register gid_t *gp;\n\n    for (gp = u.u_groups; gp < &u.u_groups[NGROUPS] && *gp != NOGROUP; gp++)\n        if (*gp == gid)\n            return (1);\n    return (0);\n}\n"
  },
  {
    "path": "sys/kern/kern_prot2.c",
    "content": "/*\n * Copyright (c) 1982, 1986, 1989, 1990, 1991, 1993\n *  The Regents of the University of California.  All rights reserved.\n * (c) UNIX System Laboratories, Inc.\n * All or some portions of this file are derived from material licensed\n * to the University of California by American Telephone and Telegraph\n * Co. or Unix System Laboratories, Inc. and are reproduced herein with\n * the permission of UNIX System Laboratories, Inc.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *  This product includes software developed by the University of\n *  California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/systm.h>\n\nvoid\nsetuid()\n{\n    struct a {\n        uid_t uid;\n    } *uap = (struct a*) u.u_arg;\n    register uid_t uid;\n\n    uid = uap->uid;\n    if (uid != u.u_ruid && ! suser())\n        return;\n    /*\n     * Everything's okay, do it.\n     */\n    u.u_procp->p_uid = uid;\n    u.u_uid = uid;\n    u.u_ruid = uid;\n    u.u_svuid = uid;\n    u.u_error = 0;\n}\n\nvoid\nseteuid()\n{\n    struct a {\n        uid_t euid;\n    } *uap = (struct a *)u.u_arg;\n    register uid_t euid;\n\n    euid = uap->euid;\n    if (euid != u.u_ruid && euid != u.u_svuid && ! suser())\n        return;\n    /*\n     * Everything's okay, do it.\n     */\n    u.u_uid = euid;\n    u.u_error = 0;\n}\n\nvoid\nsetgid()\n{\n    struct a {\n        gid_t gid;\n    } *uap = (struct a *)u.u_arg;\n    register gid_t gid;\n\n    gid = uap->gid;\n    if (gid != u.u_rgid && ! suser())\n        return;\n\n    u.u_groups[0] = gid;        /* effective gid is u_groups[0] */\n    u.u_rgid = gid;\n    u.u_svgid = gid;\n    u.u_error = 0;\n}\n\nvoid\nsetegid()\n{\n    struct a {\n        gid_t egid;\n    } *uap = (struct a *)u.u_arg;\n    register gid_t egid;\n\n    egid = uap->egid;\n    if (egid != u.u_rgid && egid != u.u_svgid && ! suser())\n        return;\n\n    u.u_groups[0] = egid;\n    u.u_error = 0;\n}\n"
  },
  {
    "path": "sys/kern/kern_resource.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/systm.h>\n#include <sys/vm.h>\n#include <sys/kernel.h>\n\n/*\n * Resource controls and accounting.\n */\nvoid\ngetpriority()\n{\n    register struct a {\n        int which;\n        int who;\n    } *uap = (struct a *)u.u_arg;\n    register struct proc *p;\n    register int low = PRIO_MAX + 1;\n\n    switch (uap->which) {\n    case PRIO_PROCESS:\n        if (uap->who == 0)\n            p = u.u_procp;\n        else\n            p = pfind(uap->who);\n        if (p == 0)\n            break;\n        low = p->p_nice;\n        break;\n    case PRIO_PGRP:\n        if (uap->who == 0)\n            uap->who = u.u_procp->p_pgrp;\n        for (p = allproc; p != NULL; p = p->p_nxt) {\n            if (p->p_pgrp == uap->who &&\n                p->p_nice < low)\n                low = p->p_nice;\n        }\n        break;\n    case PRIO_USER:\n        if (uap->who == 0)\n            uap->who = u.u_uid;\n        for (p = allproc; p != NULL; p = p->p_nxt) {\n            if (p->p_uid == uap->who &&\n                p->p_nice < low)\n                low = p->p_nice;\n        }\n        break;\n    default:\n        u.u_error = EINVAL;\n        return;\n    }\n    if (low == PRIO_MAX + 1) {\n        u.u_error = ESRCH;\n        return;\n    }\n    u.u_rval = low;\n}\n\nstatic void\ndonice(p, n)\n    register struct proc *p;\n    register int n;\n{\n    if (u.u_uid && u.u_ruid &&\n        u.u_uid != p->p_uid && u.u_ruid != p->p_uid) {\n        u.u_error = EPERM;\n        return;\n    }\n    if (n > PRIO_MAX)\n        n = PRIO_MAX;\n    if (n < PRIO_MIN)\n        n = PRIO_MIN;\n    if (n < p->p_nice && !suser()) {\n        u.u_error = EACCES;\n        return;\n    }\n    p->p_nice = n;\n}\n\nvoid\nsetpriority()\n{\n    register struct a {\n        int which;\n        int who;\n        int prio;\n    } *uap = (struct a *)u.u_arg;\n    register struct proc *p;\n    register int found = 0;\n\n    switch (uap->which) {\n    case PRIO_PROCESS:\n        if (uap->who == 0)\n            p = u.u_procp;\n        else\n            p = pfind(uap->who);\n        if (p == 0)\n            break;\n        donice(p, uap->prio);\n        found++;\n        break;\n    case PRIO_PGRP:\n        if (uap->who == 0)\n            uap->who = u.u_procp->p_pgrp;\n        for (p = allproc; p != NULL; p = p->p_nxt)\n            if (p->p_pgrp == uap->who) {\n                donice(p, uap->prio);\n                found++;\n            }\n        break;\n    case PRIO_USER:\n        if (uap->who == 0)\n            uap->who = u.u_uid;\n        for (p = allproc; p != NULL; p = p->p_nxt)\n            if (p->p_uid == uap->who) {\n                donice(p, uap->prio);\n                found++;\n            }\n        break;\n    default:\n        u.u_error = EINVAL;\n        return;\n    }\n    if (found == 0)\n        u.u_error = ESRCH;\n}\n\nvoid\nsetrlimit()\n{\n    register struct a {\n        u_int   which;\n        struct  rlimit *lim;\n    } *uap = (struct a *)u.u_arg;\n    struct rlimit alim;\n    register struct rlimit *alimp;\n\n    if (uap->which >= RLIM_NLIMITS) {\n        u.u_error = EINVAL;\n        return;\n    }\n    alimp = &u.u_rlimit[uap->which];\n    u.u_error = copyin((caddr_t)uap->lim, (caddr_t)&alim,\n        sizeof (struct rlimit));\n    if (u.u_error)\n        return;\n    if (uap->which == RLIMIT_CPU) {\n        /*\n         * 2.11 stores RLIMIT_CPU as ticks to keep from making\n         * hardclock() do long multiplication/division.\n         */\n        if (alim.rlim_cur >= RLIM_INFINITY / hz)\n            alim.rlim_cur = RLIM_INFINITY;\n        else\n            alim.rlim_cur = alim.rlim_cur * hz;\n        if (alim.rlim_max >= RLIM_INFINITY / hz)\n            alim.rlim_max = RLIM_INFINITY;\n        else\n            alim.rlim_max = alim.rlim_max * hz;\n    }\n    if (alim.rlim_cur > alimp->rlim_max || alim.rlim_max > alimp->rlim_max)\n        if (!suser())\n            return;\n    *alimp = alim;\n}\n\nvoid\ngetrlimit()\n{\n    register struct a {\n        u_int   which;\n        struct  rlimit *rlp;\n    } *uap = (struct a *)u.u_arg;\n\n    if (uap->which >= RLIM_NLIMITS) {\n        u.u_error = EINVAL;\n        return;\n    }\n    if (uap->which == RLIMIT_CPU) {\n        struct rlimit alim;\n\n        alim = u.u_rlimit[uap->which];\n        if (alim.rlim_cur != RLIM_INFINITY)\n            alim.rlim_cur = alim.rlim_cur / hz;\n        if (alim.rlim_max != RLIM_INFINITY)\n            alim.rlim_max = alim.rlim_max / hz;\n        u.u_error = copyout((caddr_t)&alim,\n            (caddr_t)uap->rlp,sizeof (struct rlimit));\n    }\n    else u.u_error = copyout((caddr_t)&u.u_rlimit[uap->which],\n        (caddr_t)uap->rlp,sizeof (struct rlimit));\n}\n\nvoid\ngetrusage()\n{\n    register struct a {\n        int who;\n        struct  rusage *rusage;\n    } *uap = (struct a *)u.u_arg;\n    register struct k_rusage *rup;\n    struct rusage ru;\n\n    switch (uap->who) {\n\n    case RUSAGE_SELF:\n        rup = &u.u_ru;\n        break;\n\n    case RUSAGE_CHILDREN:\n        rup = &u.u_cru;\n        break;\n\n    default:\n        u.u_error = EINVAL;\n        return;\n    }\n    rucvt(&ru,rup);\n    u.u_error = copyout((caddr_t)&ru, (caddr_t)uap->rusage,\n        sizeof (struct rusage));\n}\n\n/*\n * Add resource usage data.\n */\nvoid\nruadd(ru, ru2)\n    struct k_rusage *ru, *ru2;\n{\n    register long *ip, *ip2;\n    register int i;\n\n    /*\n     * since the kernel timeval structures are single longs,\n     * fold them into the loop.\n     */\n    ip = &ru->k_ru_first;\n    ip2 = &ru2->k_ru_first;\n    for (i = &ru->k_ru_last - &ru->k_ru_first; i >= 0; i--)\n        *ip++ += *ip2++;\n}\n\n/*\n * Convert an internal kernel rusage structure into a `real' rusage structure.\n */\nvoid\nrucvt (rup, krup)\n    register struct rusage      *rup;\n    register struct k_rusage    *krup;\n{\n    bzero((caddr_t)rup, sizeof(*rup));\n    rup->ru_utime.tv_sec   = krup->ru_utime / hz;\n    rup->ru_utime.tv_usec  = (krup->ru_utime % hz) * usechz;\n    rup->ru_stime.tv_sec   = krup->ru_stime / hz;\n    rup->ru_stime.tv_usec  = (krup->ru_stime % hz) * usechz;\n    rup->ru_nswap = krup->ru_nswap;\n    rup->ru_inblock = krup->ru_inblock;\n    rup->ru_oublock = krup->ru_oublock;\n    rup->ru_msgsnd = krup->ru_msgsnd;\n    rup->ru_msgrcv = krup->ru_msgrcv;\n    rup->ru_nsignals = krup->ru_nsignals;\n    rup->ru_nvcsw = krup->ru_nvcsw;\n    rup->ru_nivcsw = krup->ru_nivcsw;\n}\n"
  },
  {
    "path": "sys/kern/kern_sig.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/user.h>\n#include <sys/inode.h>\n#include <sys/proc.h>\n#include <sys/namei.h>\n#include <sys/signalvar.h>\n\n/*\n * Can the current process send the signal `signum' to process `q'?\n * This is complicated by the need to access the `real uid' of `q'.\n * The 'real uid' is in the u area and `q' may be (but usually is not) swapped\n * out.  Use the routine `fill_from_u' which the sysctl() call uses.  See the\n * notes in kern_sysctl.c\n *\n * The previous checks for a process to post a signal to another process\n * checked _only_ the effective userid.  With the implementation of the\n * 'saved id' feature and the ability of a setuid program to assume either\n * uid that check was inadequate.\n *\n * The 'c'urrent process is allowed to send a signal to a 't'arget process if\n * 1) either the real or effective user ids match OR 2) if the signal is\n * SIGCONT and the target process is a descendant of the current process\n */\nstatic int\ncansignal (q, signum)\n    register struct proc *q;\n    int signum;\n{\n    register struct proc *curp = u.u_procp;\n    uid_t   ruid;\n\n    fill_from_u(q, &ruid, NULL, NULL);  /* XXX */\n    if (curp->p_uid == 0 ||     /* c effective root */\n        u.u_ruid == ruid ||     /* c real = t real */\n        curp->p_uid == ruid ||      /* c effective = t real */\n        u.u_ruid == q->p_uid || /* c real = t effective */\n        curp->p_uid == q->p_uid ||  /* c effective = t effective */\n        (signum == SIGCONT && inferior(q)))\n        return(1);\n    return(0);\n}\n\n/*\n * 4.3 Compatibility\n */\nvoid\nsigstack()\n{\n    register struct a {\n        struct  sigstack *nss;\n        struct  sigstack *oss;\n    } *uap = (struct a*) u.u_arg;\n    struct sigstack ss;\n    register int error = 0;\n\n    ss.ss_sp = u.u_sigstk.ss_base;\n    ss.ss_onstack = u.u_sigstk.ss_flags & SA_ONSTACK;\n    if(uap->oss && (error = copyout ((caddr_t) &ss,\n        (caddr_t) uap->oss, sizeof (ss))))\n        goto out;\n    if (uap->nss && (error = copyin ((caddr_t) uap->nss,\n        (caddr_t) &ss, sizeof (ss))) == 0) {\n        u.u_sigstk.ss_base = ss.ss_sp;\n        u.u_sigstk.ss_size = 0;\n        u.u_sigstk.ss_flags |= (ss.ss_onstack & SA_ONSTACK);\n        u.u_psflags |= SAS_ALTSTACK;\n    }\nout:\n    u.u_error = error;\n}\n\nstatic int\nkillpg1 (signo, pgrp, all)\n    int signo, pgrp, all;\n{\n    register struct proc *p;\n    int f, error = 0;\n\n    if (! all && pgrp == 0) {\n        /*\n         * Zero process id means send to my process group.\n         */\n        pgrp = u.u_procp->p_pgrp;\n        if (pgrp == 0)\n            return (ESRCH);\n    }\n    for (f = 0, p = allproc; p != NULL; p = p->p_nxt) {\n        if ((p->p_pgrp != pgrp && !all) || p->p_ppid == 0 ||\n            (p->p_flag&SSYS) || (all && p == u.u_procp))\n            continue;\n        if (! cansignal (p, signo)) {\n            if (!all)\n                error = EPERM;\n            continue;\n        }\n        f++;\n        if (signo)\n            psignal(p, signo);\n    }\n    return (error ? error : (f == 0 ? ESRCH : 0));\n}\n\nvoid\nkill()\n{\n    register struct a {\n        int pid;\n        int signo;\n    } *uap = (struct a *)u.u_arg;\n    register struct proc *p;\n    register int error = 0;\n\n    /*\n     * BSD4.3 botches the comparison against NSIG - it's a good thing for\n     * them psignal catches the error - however, since psignal is the\n     * kernel's internel signal mechanism and *should be getting correct\n     * parameters from the rest of the kernel, psignal shouldn't *have*\n     * to check it's parameters for validity.  If you feel differently,\n     * feel free to clutter up the entire inner kernel with parameter\n     * checks - start with postsig ...\n     */\n    if (uap->signo < 0 || uap->signo >= NSIG) {\n        error = EINVAL;\n        goto out;\n    }\n    if (uap->pid > 0) {\n        /* kill single process */\n        p = pfind(uap->pid);\n        if (p == 0) {\n            error = ESRCH;\n            goto out;\n        }\n        if (! cansignal (p, uap->signo))\n            error = EPERM;\n        else if (uap->signo)\n            psignal (p, uap->signo);\n        goto out;\n    }\n    switch (uap->pid) {\n    case -1:        /* broadcast signal */\n        error = killpg1 (uap->signo, 0, 1);\n        break;\n    case 0:         /* signal own process group */\n        error = killpg1 (uap->signo, 0, 0);\n        break;\n    default:        /* negative explicit process group */\n        error = killpg1 (uap->signo, -uap->pid, 0);\n        break;\n    }\nout:\n    u.u_error = error;\n}\n\nvoid\nkillpg()\n{\n    register struct a {\n        int pgrp;\n        int signo;\n    } *uap = (struct a *)u.u_arg;\n    register int error = 0;\n\n    if (uap->signo < 0 || uap->signo >= NSIG) {\n        error = EINVAL;\n        goto out;\n    }\n    error = killpg1 (uap->signo, uap->pgrp, 0);\nout:\n    u.u_error = error;\n}\n\n/*\n * Put the argument process into the stopped\n * state and notify the parent via wakeup.\n * Signals are handled elsewhere.\n */\nvoid\nstop(p)\n    register struct proc *p;\n{\n    p->p_stat = SSTOP;\n    p->p_flag &= ~P_WAITED;\n    wakeup((caddr_t)p->p_pptr);\n}\n\n/*\n * Send the specified signal to\n * all processes with 'pgrp' as\n * process group.\n */\nvoid\ngsignal (pgrp, sig)\n    register int pgrp;\n    register int sig;\n{\n    register struct proc *p;\n\n    if (pgrp == 0)\n        return;\n\n    for (p = allproc; p != NULL; p = p->p_nxt)\n        if (p->p_pgrp == pgrp)\n            psignal(p, sig);\n}\n\n/*\n * Send the specified signal to\n * the specified process.\n */\nvoid\npsignal(p, sig)\n    register struct proc *p;\n    register int sig;\n{\n    register int s;\n    sig_t action;\n    int prop;\n    long mask;\n\n    mask = sigmask(sig);\n    prop = sigprop[sig];\n\n    /*\n     * If proc is traced, always give parent a chance.\n     */\n    if (p->p_flag & P_TRACED)\n        action = SIG_DFL;\n    else {\n        /*\n         * If the signal is being ignored,\n         * then we forget about it immediately.\n         */\n        if (p->p_sigignore & mask)\n            return;\n        if (p->p_sigmask & mask)\n            action = SIG_HOLD;\n        else if (p->p_sigcatch & mask)\n            action = SIG_CATCH;\n        else\n            action = SIG_DFL;\n    }\n\n    if (p->p_nice > NZERO && action == SIG_DFL && (prop & SA_KILL) &&\n        (p->p_flag & P_TRACED) == 0)\n        p->p_nice = NZERO;\n\n    if (prop & SA_CONT)\n        p->p_sig &= ~stopsigmask;\n\n    if (prop & SA_STOP) {\n        /*\n         * If sending a tty stop signal to a member of an orphaned\n         * process group (i.e. a child of init), discard the signal\n         * here if the action is default; don't stop the process\n         * below if sleeping, and don't clear any pending SIGCONT.\n         */\n        if ((prop & SA_TTYSTOP) && (p->p_pptr == &proc[1]) &&\n            action == SIG_DFL)\n            return;\n        p->p_sig &= ~contsigmask;\n    }\n    p->p_sig |= mask;\n\n    /*\n     * Defer further processing for signals which are held.\n     */\n    if (action == SIG_HOLD && ((prop & SA_CONT) == 0 || p->p_stat != SSTOP))\n        return;\n    s = splhigh();\n    switch (p->p_stat) {\n\n    case SSLEEP:\n        /*\n         * If process is sleeping uninterruptibly we can not\n         * interrupt the sleep... the signal will be noticed\n         * when the process returns through trap() or syscall().\n         */\n        if ((p->p_flag & P_SINTR) == 0)\n            goto out;\n        /*\n         * Process is sleeping and traced... make it runnable\n         * so it can discover the signal in issignal() and stop\n         * for the parent.\n         */\n        if (p->p_flag & P_TRACED)\n            goto run;\n\n        /*\n         * If SIGCONT is default (or ignored) and process is\n         * asleep, we are finished; the process should not\n         * be awakened.\n         */\n        if ((prop & SA_CONT) && action == SIG_DFL) {\n            p->p_sig &= ~mask;\n            goto out;\n        }\n        /*\n         * When a sleeping process receives a stop\n         * signal, process immediately if possible.\n         * All other (caught or default) signals\n         * cause the process to run.\n         */\n        if (prop & SA_STOP) {\n            if (action != SIG_DFL)\n                goto run;\n            /*\n             * If a child holding parent blocked,\n             * stopping could cause deadlock.\n             */\n            if (p->p_flag & SVFORK)\n                goto out;\n            p->p_sig &= ~mask;\n            p->p_ptracesig = sig;\n            if ((p->p_pptr->p_flag & P_NOCLDSTOP) == 0)\n                psignal(p->p_pptr, SIGCHLD);\n            stop(p);\n            goto out;\n        } else\n            goto run;\n        /*NOTREACHED*/\n    case SSTOP:\n        /*\n         * If traced process is already stopped,\n         * then no further action is necessary.\n         */\n        if (p->p_flag & P_TRACED)\n            goto out;\n        if (sig == SIGKILL)\n            goto run;\n        if (prop & SA_CONT) {\n            /*\n             * If SIGCONT is default (or ignored), we continue the\n             * process but don't leave the signal in p_sig, as\n             * it has no further action.  If SIGCONT is held, we\n             * continue the process and leave the signal in\n             * p_sig.  If the process catches SIGCONT, let it\n             * handle the signal itself.  If it isn't waiting on\n             * an event, then it goes back to run state.\n             * Otherwise, process goes back to sleep state.\n             */\n            if (action == SIG_DFL)\n                p->p_sig &= ~mask;\n            if (action == SIG_CATCH || p->p_wchan == 0)\n                goto run;\n            p->p_stat = SSLEEP;\n            goto out;\n        }\n\n        if (prop & SA_STOP) {\n            /*\n             * Already stopped, don't need to stop again.\n             * (If we did the shell could get confused.)\n             */\n            p->p_sig &= ~mask;      /* take it away */\n            goto out;\n        }\n\n        /*\n         * If process is sleeping interruptibly, then simulate a\n         * wakeup so that when it is continued, it will be made\n         * runnable and can look at the signal.  But don't make\n         * the process runnable, leave it stopped.\n         */\n        if (p->p_wchan && (p->p_flag & P_SINTR))\n            unsleep(p);\n        goto out;\n        /*NOTREACHED*/\n\n    default:\n        /*\n         * SRUN, SIDL, SZOMB do nothing with the signal,\n         * other than kicking ourselves if we are running.\n         * It will either never be noticed, or noticed very soon.\n         */\n        goto out;\n    }\n    /*NOTREACHED*/\nrun:\n    /*\n     * Raise priority to at least PUSER.\n     */\n    if (p->p_pri > PUSER)\n        p->p_pri = PUSER;\n    setrun(p);\nout:\n    splx(s);\n}\n\n/*\n * If the current process has received a signal (should be caught\n * or cause termination, should interrupt current syscall) return the\n * signal number.  Stop signals with default action are processed\n * immediately then cleared; they are not returned.  This is checked\n * after each entry into the kernel for a syscall of trap (though this\n * can usually be done without calling issignal by checking the pending\n * signals masks in CURSIG)/  The normal sequence is:\n *\n *  while (signum = CURSIG(u.u_procp))\n *      postsig(signum);\n */\nint\nissignal (p)\n    register struct proc *p;\n{\n    register int sig;\n    long mask;\n    int prop;\n\n    for (;;) {\n        mask = p->p_sig & ~p->p_sigmask;\n        if (p->p_flag&SVFORK)\n            mask &= ~stopsigmask;\n        if (mask == 0)\n            return(0);      /* No signals to send */\n        sig = ffs(mask);\n        mask = sigmask(sig);\n        prop = sigprop[sig];\n        /*\n         * We should see pending but ignored signals\n         * only if P_TRACED was on when they were posted.\n        */\n        if ((mask & p->p_sigignore) && ! (p->p_flag & P_TRACED)) {\n            p->p_sig &= ~mask;\n            continue;\n        }\n        if ((p->p_flag & P_TRACED) && ! (p->p_flag & SVFORK)) {\n            /*\n             * If traced, always stop, and stay\n             * stopped until released by the parent.\n             *\n             * Note that we must clear the pending signal\n             * before we call procxmt since that routine\n             * might cause a fault, calling sleep and\n             * leading us back here again with the same signal.\n             * Then we would be deadlocked because the tracer\n             * would still be blocked on the ipc struct from\n             * the initial request.\n             */\n            p->p_sig &= ~mask;\n            p->p_ptracesig = sig;\n            psignal(p->p_pptr, SIGCHLD);\n            do {\n                stop(p);\n                swtch();\n            } while (! procxmt() && (p->p_flag & P_TRACED));\n\n            /*\n             * If parent wants us to take the signal,\n             * then it will leave it in p->p_ptracesig;\n             * otherwise we just look for signals again.\n             */\n            sig = p->p_ptracesig;\n            if (sig == 0)\n                continue;\n\n            /*\n             * Put the new signal into p_sig.  If the\n             * signal is being masked, look for other signals.\n             */\n            mask = sigmask(sig);\n            p->p_sig |= mask;\n            if (p->p_sigmask & mask)\n                continue;\n\n            /*\n             * If the traced bit got turned off, go back up\n             * to the top to rescan signals.  This ensures\n             * that p_sig* and u_signal are consistent.\n             */\n            if ((p->p_flag& P_TRACED) == 0)\n                continue;\n            prop = sigprop[sig];\n        }\n\n        switch ((int)u.u_signal[sig]) {\n\n        case (int)SIG_DFL:\n            /*\n             * Don't take default actions on system processes.\n             */\n            if (p->p_pid <= 1) {\n#ifdef DIAGNOSTIC\n                /*\n                 * Are you sure you want to ignore SIGSEGV\n                 * in init? XXX\n                 */\n                printf(\"Process (pid %d) got signal %d\\n\",\n                    p->p_pid, sig);\n#endif\n                break;\n            }\n            /*\n             * If there is a pending stop signal to process\n             * with default action, stop here,\n             * then clear the signal.  However,\n             * if process is member of an orphaned\n             * process group, ignore tty stop signals.\n             */\n            if (prop & SA_STOP) {\n                if (p->p_flag & P_TRACED ||\n                    (p->p_pptr == &proc[1] &&\n                    prop & SA_TTYSTOP))\n                    break;  /* == ignore */\n                p->p_ptracesig = sig;\n                if ((p->p_pptr->p_flag & P_NOCLDSTOP) == 0)\n                    psignal(p->p_pptr, SIGCHLD);\n                stop(p);\n                swtch();\n                break;\n            } else if (prop & SA_IGNORE) {\n                /*\n                 * Except for SIGCONT, shouldn't get here.\n                 * Default action is to ignore; drop it.\n                 */\n                break;      /* == ignore */\n            } else\n                return(sig);\n            /*NOTREACHED*/\n\n        case (int)SIG_IGN:\n            /*\n             * Masking above should prevent us\n             * ever trying to take action on a held\n             * or ignored signal, unless process is traced.\n             */\n            if ((prop & SA_CONT) == 0 &&\n                (p->p_flag & P_TRACED) == 0)\n                printf(\"issig\\n\");\n            break;          /* == ignore */\n\n        default:\n            /*\n             * This signal has an action, let postsig process it.\n             */\n            return(sig);\n        }\n        p->p_sig &= ~mask;      /* take the signal away! */\n    }\n    /* NOTREACHED */\n}\n\n/*\n * Create a core image on the file \"core\"\n * If you are looking for protection glitches,\n * there are probably a wealth of them here\n * when this occurs to a suid command.\n *\n * It writes UPAGES (USIZE for pdp11) block of the\n * user.h area followed by the entire\n * data+stack segments.\n */\nstatic int\ncore()\n{\n    register struct inode *ip;\n    struct  nameidata nd;\n    register struct nameidata *ndp = &nd;\n    register char *np;\n    char    *cp, name[MAXCOMLEN + 6];\n\n    /*\n     * Don't dump if not root.\n     */\n    if (! suser())\n        return(0);\n    if (USIZE + u.u_dsize + u.u_ssize >= u.u_rlimit[RLIMIT_CORE].rlim_cur)\n        return (0);\n    cp = u.u_comm;\n    np = name;\n    while ((*np++ = *cp++))\n        ;\n    cp = \".core\";\n    np--;\n    while ((*np++ = *cp++))\n        ;\n    u.u_error = 0;\n    NDINIT (ndp, CREATE, FOLLOW, name);\n    ip = namei(ndp);\n    if (ip == NULL) {\n        if (u.u_error)\n            return (0);\n        ip = maknode (0644, ndp);\n        if (ip==NULL)\n            return (0);\n    }\n    if (access(ip, IWRITE) ||\n       (ip->i_mode&IFMT) != IFREG ||\n       ip->i_nlink != 1) {\n        u.u_error = EFAULT;\n        goto out;\n    }\n    itrunc(ip, (u_long)0, 0);\n    u.u_error = rdwri (UIO_WRITE, ip, (caddr_t) &u,\n        USIZE, (off_t) 0, IO_UNIT, (int*) 0);\n    if (u.u_error)\n        goto out;\n\n    u.u_error = rdwri (UIO_WRITE, ip, (caddr_t)__user_data_start,\n        u.u_dsize, (off_t) USIZE, IO_UNIT, (int*) 0);\n    if (u.u_error)\n        goto out;\n\n    u.u_error = rdwri (UIO_WRITE, ip, (caddr_t)__user_data_end - u.u_ssize,\n        u.u_ssize, (off_t) USIZE + u.u_dsize,\n        IO_UNIT, (int*) 0);\nout:\n    iput(ip);\n    return (u.u_error == 0);\n}\n\n/*\n * Take the action for the specified signal\n * from the current set of pending signals.\n */\nvoid\npostsig(sig)\n    int sig;\n{\n    register struct proc *p = u.u_procp;\n    long mask = sigmask(sig), returnmask;\n    register sig_t action;\n\n    p->p_sig &= ~mask;\n    action = u.u_signal[sig];\n\n    if (action != SIG_DFL) {\n#ifdef DIAGNOSTIC\n        if (action == SIG_IGN || (p->p_sigmask & mask))\n            panic(\"postsig action\");\n#endif\n        u.u_error = 0;  /* XXX - why? */\n        /*\n         * Set the new mask value and also defer further\n         * occurences of this signal.\n         *\n         * Special case: user has done a sigsuspend.  Here the\n         * current mask is not of interest, but rather the\n         * mask from before the sigsuspend is what we want restored\n         * after the signal processing is completed.\n         */\n        (void) splhigh();\n        if (u.u_psflags & SAS_OLDMASK) {\n            returnmask = u.u_oldmask;\n            u.u_psflags &= ~SAS_OLDMASK;\n        } else\n            returnmask = p->p_sigmask;\n        p->p_sigmask |= u.u_sigmask[sig] | mask;\n        (void) spl0();\n        u.u_ru.ru_nsignals++;\n        sendsig(action, sig, returnmask);\n        return;\n    }\n    if (sigprop[sig] & SA_CORE) {\n        u.u_arg[0] = sig;\n        if (core())\n            sig |= 0200;\n    }\n    exit(sig);\n}\n\n/*\n * Reset signals for an exec of the specified process.  In 4.4 this function\n * was in kern_sig.c but since in 2.11 kern_sig and kern_exec will likely be\n * in different overlays placing this here potentially saves a kernel overlay\n * switch.\n */\nvoid\nexecsigs(register struct proc *p)\n{\n    register int nc;\n    unsigned long mask;\n\n    /*\n     * Reset caught signals.  Held signals remain held\n     * through p_sigmask (unless they were caught,\n     * and are now ignored by default).\n     */\n    while (p->p_sigcatch) {\n        nc = ffs(p->p_sigcatch);\n        mask = sigmask(nc);\n        p->p_sigcatch &= ~mask;\n        if (sigprop[nc] & SA_IGNORE) {\n            if (nc != SIGCONT)\n                p->p_sigignore |= mask;\n            p->p_sig &= ~mask;\n        }\n        u.u_signal[nc] = SIG_DFL;\n    }\n    /*\n     * Reset stack state to the user stack (disable the alternate stack).\n     */\n    u.u_sigstk.ss_flags = SA_DISABLE;\n    u.u_sigstk.ss_size = 0;\n    u.u_sigstk.ss_base = 0;\n    u.u_psflags = 0;\n}\n\n/*\n * nonexistent system call-- signal process (may want to handle it)\n * flag error if process won't see signal immediately\n * Q: should we do that all the time ??\n */\nvoid\nnosys()\n{\n    if (u.u_signal[SIGSYS] == SIG_IGN || u.u_signal[SIGSYS] == SIG_HOLD)\n        u.u_error = EINVAL;\n    psignal(u.u_procp, SIGSYS);\n}\n\nvoid\nuserret(int pc, time_t syst)\n{\n    int psig;\n\n    /* Process all received signals. */\n    for (;;) {\n        psig = CURSIG(u.u_procp);\n        if (psig <= 0)\n            break;\n        postsig(psig);\n    }\n    curpri = setpri(u.u_procp);\n\n    /* Switch to another process. */\n    if (runrun) {\n        setrq(u.u_procp);\n        u.u_ru.ru_nivcsw++;\n        swtch();\n    }\n\n    /* Update profiling information. */\n    if (u.u_prof.pr_scale)\n        addupc((caddr_t)pc, &u.u_prof, (int)(u.u_ru.ru_stime - syst));\n}\n"
  },
  {
    "path": "sys/kern/kern_sig2.c",
    "content": "/*\n * Copyright (c) 1982, 1986, 1989, 1991, 1993\n *  The Regents of the University of California.  All rights reserved.\n * (c) UNIX System Laboratories, Inc.\n * All or some portions of this file are derived from material licensed\n * to the University of California by American Telephone and Telegraph\n * Co. or Unix System Laboratories, Inc. and are reproduced herein with\n * the permission of UNIX System Laboratories, Inc.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *  This product includes software developed by the University of\n *  California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n/*\n * This module is a hacked down version of kern_sig.c from 4.4BSD.  The\n * original signal handling code is still present in 2.11's kern_sig.c.  This\n * was done because large modules are very hard to fit into the kernel's\n * overlay structure.  A smaller kern_sig2.c fits more easily into an overlaid\n * kernel.\n */\n#define SIGPROP     /* include signal properties table */\n#include <sys/param.h>\n#include <sys/signal.h>\n#include <sys/signalvar.h>\n#include <sys/dir.h>\n#include <sys/namei.h>\n#include <sys/time.h>\n#include <sys/resource.h>\n#include <sys/proc.h>\n#include <sys/systm.h>\n#include <sys/kernel.h>\n#include <sys/user.h>       /* for coredump */\n\nstatic void\nsetsigvec(signum, sa)\n    int signum;\n    register struct sigaction *sa;\n{\n    unsigned long bit;\n    register struct proc *p = u.u_procp;\n\n    bit = sigmask(signum);\n    /*\n     * Change setting atomically.\n     */\n    (void) splhigh();\n    u.u_signal[signum] = sa->sa_handler;\n    u.u_sigmask[signum] = sa->sa_mask &~ sigcantmask;\n    if ((sa->sa_flags & SA_RESTART) == 0)\n        u.u_sigintr |= bit;\n    else\n        u.u_sigintr &= ~bit;\n    if (sa->sa_flags & SA_ONSTACK)\n        u.u_sigonstack |= bit;\n    else\n        u.u_sigonstack &= ~bit;\n    if (signum == SIGCHLD) {\n        if (sa->sa_flags & SA_NOCLDSTOP)\n            p->p_flag |= P_NOCLDSTOP;\n        else\n            p->p_flag &= ~P_NOCLDSTOP;\n    }\n    /*\n     * Set bit in p_sigignore for signals that are set to SIG_IGN,\n     * and for signals set to SIG_DFL where the default is to ignore.\n     * However, don't put SIGCONT in p_sigignore,\n     * as we have to restart the process.\n     */\n    if (sa->sa_handler == SIG_IGN ||\n        (sigprop[signum] & SA_IGNORE && sa->sa_handler == SIG_DFL)) {\n        p->p_sig &= ~bit;       /* never to be seen again */\n        if (signum != SIGCONT)\n            p->p_sigignore |= bit;  /* easier in psignal */\n        p->p_sigcatch &= ~bit;\n    } else {\n        p->p_sigignore &= ~bit;\n        if (sa->sa_handler == SIG_DFL)\n            p->p_sigcatch &= ~bit;\n        else\n            p->p_sigcatch |= bit;\n    }\n    (void) spl0();\n}\n\nvoid\nsigaction()\n{\n    register struct a {\n        int signum;\n        struct  sigaction *nsa;\n        struct  sigaction *osa;\n        u_int   sigtramp;\n    } *uap = (struct a *)u.u_arg;\n    struct sigaction vec;\n    register struct sigaction *sa;\n    register int signum;\n    u_long bit;\n    int error = 0;\n\n    u.u_sigtramp = uap->sigtramp;   /* save trampoline address */\n\n    signum = uap->signum;\n    if (signum <= 0 || signum >= NSIG) {\n        error = EINVAL;\n        goto out;\n    }\n    if (uap->nsa && (signum == SIGKILL || signum == SIGSTOP)) {\n        error = EINVAL;\n        goto out;\n    }\n    sa = &vec;\n    if (uap->osa) {\n        sa->sa_handler = u.u_signal[signum];\n        sa->sa_mask = u.u_sigmask[signum];\n        bit = sigmask(signum);\n        sa->sa_flags = 0;\n        if ((u.u_sigonstack & bit) != 0)\n            sa->sa_flags |= SA_ONSTACK;\n        if ((u.u_sigintr & bit) == 0)\n            sa->sa_flags |= SA_RESTART;\n        if (u.u_procp->p_flag & P_NOCLDSTOP)\n            sa->sa_flags |= SA_NOCLDSTOP;\n        error = copyout ((caddr_t) sa, (caddr_t) uap->osa, sizeof(vec));\n        if (error != 0)\n            goto out;\n    }\n    if (uap->nsa) {\n        error = copyin ((caddr_t) uap->nsa, (caddr_t) sa, sizeof(vec));\n        if (error != 0)\n            goto out;\n        setsigvec(signum, sa);\n    }\nout:\n    u.u_error = error;\n}\n\n/*\n * Kill current process with the specified signal in an uncatchable manner;\n * used when process is too confused to continue, or we are unable to\n * reconstruct the process state safely.\n */\nvoid\nfatalsig(signum)\n    int signum;\n{\n    unsigned long mask;\n    register struct proc *p = u.u_procp;\n\n    u.u_signal[signum] = SIG_DFL;\n    mask = sigmask(signum);\n    p->p_sigignore &= ~mask;\n    p->p_sigcatch &= ~mask;\n    p->p_sigmask &= ~mask;\n    psignal(p, signum);\n}\n\n/*\n * Initialize signal state for process 0;\n * set to ignore signals that are ignored by default.\n */\nvoid\nsiginit(p)\n    register struct proc *p;\n{\n    register int i;\n\n    for (i = 0; i < NSIG; i++)\n        if (sigprop[i] & SA_IGNORE && i != SIGCONT)\n            p->p_sigignore |= sigmask(i);\n}\n\n/*\n * Manipulate signal mask.\n * Unlike 4.4BSD we do not receive a pointer to the new and old mask areas and\n * do a copyin/copyout instead of storing indirectly thru a 'retval' parameter.\n * This is because we have to return both an error indication (which is 16 bits)\n * _AND_ the new mask (which is 32 bits).  Can't do both at the same time with\n * the 2BSD syscall return mechanism.\n */\nvoid\nsigprocmask()\n{\n    register struct a {\n        int how;\n        sigset_t *set;\n        sigset_t *oset;\n    } *uap = (struct a *)u.u_arg;\n    int error = 0;\n    sigset_t oldmask, newmask;\n    register struct proc *p = u.u_procp;\n\n    oldmask = p->p_sigmask;\n    if (! uap->set) /* No new mask, go possibly return old mask */\n        goto out;\n    error = copyin ((caddr_t) uap->set, (caddr_t) &newmask, sizeof (newmask));\n    if (error)\n        goto out;\n    (void) splhigh();\n\n    switch (uap->how) {\n    case SIG_BLOCK:\n        p->p_sigmask |= (newmask &~ sigcantmask);\n        break;\n    case SIG_UNBLOCK:\n        p->p_sigmask &= ~newmask;\n        break;\n    case SIG_SETMASK:\n        p->p_sigmask = newmask &~ sigcantmask;\n        break;\n    default:\n        error = EINVAL;\n        break;\n    }\n    (void) spl0();\nout:\n    if (error == 0 && uap->oset)\n        error = copyout ((caddr_t) &oldmask, (caddr_t) uap->oset, sizeof (oldmask));\n    u.u_error = error;\n}\n\n/*\n * sigpending and sigsuspend use the standard calling sequence unlike 4.4 which\n * used a nonstandard (mask instead of pointer) calling convention.\n */\nvoid\nsigpending()\n{\n    register struct a {\n        struct sigset_t *set;\n    } *uap = (struct a *)u.u_arg;\n    register int error = 0;\n    struct  proc *p = u.u_procp;\n\n    if (uap->set)\n        error = copyout((caddr_t)&p->p_sig, (caddr_t)uap->set,\n                sizeof (p->p_sig));\n    else\n        error = EINVAL;\n    u.u_error = error;\n}\n\n/*\n * sigsuspend is supposed to always return EINTR so we ignore errors on the\n * copyin by assuming a mask of 0.\n */\nvoid\nsigsuspend()\n{\n    register struct a {\n        struct sigset_t *set;\n    } *uap = (struct a *)u.u_arg;\n    sigset_t nmask = 0;\n    struct proc *p = u.u_procp;\n    int error;\n\n    if (uap->set && (error = copyin ((caddr_t) uap->set, (caddr_t) &nmask, sizeof (nmask))))\n        nmask = 0;\n    /*\n     * When returning from sigsuspend, we want the old mask to be restored\n     * after the signal handler has finished.  Thus, we save it here and set\n     * a flag to indicate this.\n     */\n    u.u_oldmask = p->p_sigmask;\n    u.u_psflags |= SAS_OLDMASK;\n    p->p_sigmask = nmask &~ sigcantmask;\n    while (tsleep((caddr_t)&u, PPAUSE|PCATCH, 0) == 0)\n        ;\n    /* always return EINTR rather than ERESTART */\n    u.u_error = EINTR;\n}\n\nvoid\nsigaltstack()\n{\n    register struct a {\n        struct sigaltstack * nss;\n        struct sigaltstack * oss;\n    } *uap = (struct a *)u.u_arg;\n    struct sigaltstack ss;\n    int error = 0;\n\n    if ((u.u_psflags & SAS_ALTSTACK) == 0)\n        u.u_sigstk.ss_flags |= SA_DISABLE;\n    if (uap->oss && (error = copyout((caddr_t)&u.u_sigstk,\n        (caddr_t)uap->oss, sizeof (struct sigaltstack))))\n        goto out;\n    if (uap->nss == 0)\n        goto out;\n    error = copyin ((caddr_t) uap->nss, (caddr_t) &ss, sizeof(ss));\n    if (error != 0)\n        goto out;\n    if (ss.ss_flags & SA_DISABLE) {\n        if (u.u_sigstk.ss_flags & SA_ONSTACK)\n            {\n            error = EINVAL;\n            goto out;\n            }\n        u.u_psflags &= ~SAS_ALTSTACK;\n        u.u_sigstk.ss_flags = ss.ss_flags;\n        goto out;\n    }\n    if (ss.ss_size < MINSIGSTKSZ)\n        {\n        error = ENOMEM;\n        goto out;\n        }\n    u.u_psflags |= SAS_ALTSTACK;\n    u.u_sigstk = ss;\nout:\n    u.u_error = error;\n}\n\nvoid\nsigwait()\n{\n    register struct a {\n        sigset_t *set;\n        int *sig;\n    } *uap = (struct a *)u.u_arg;\n    sigset_t wanted, sigsavail;\n    register struct proc *p = u.u_procp;\n    int signo, error;\n\n    if (uap->set == 0 || uap->sig == 0) {\n        error = EINVAL;\n        goto out;\n    }\n    error = copyin ((caddr_t) uap->set, (caddr_t) &wanted, sizeof (sigset_t));\n    if (error)\n        goto out;\n\n    wanted |= sigcantmask;\n    while ((sigsavail = (wanted & p->p_sig)) == 0)\n        tsleep ((caddr_t) &u.u_signal[0], PPAUSE | PCATCH, 0);\n\n    if (sigsavail & sigcantmask) {\n        error = EINTR;\n        goto out;\n    }\n\n    signo = ffs(sigsavail);\n    p->p_sig &= ~sigmask(signo);\n    error = copyout ((caddr_t) &signo, (caddr_t) uap->sig, sizeof (int));\nout:\n    u.u_error = error;\n}\n"
  },
  {
    "path": "sys/kern/kern_subr.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/user.h>\n#include <sys/buf.h>\n#include <sys/uio.h>\n\n/*\n * Move data to/from user space.\n */\nint\nuiomove (cp, n, uio)\n    caddr_t cp;\n    u_int n;\n    register struct uio *uio;\n{\n    register struct iovec *iov;\n    int error = 0;\n    register u_int cnt;\n\n    while (n > 0 && uio->uio_resid) {\n        iov = uio->uio_iov;\n        cnt = iov->iov_len;\n        if (cnt == 0) {\n            uio->uio_iov++;\n            uio->uio_iovcnt--;\n            continue;\n        }\n        if (cnt > n)\n            cnt = n;\n        if (uio->uio_rw == UIO_READ)\n            bcopy ((caddr_t) cp, iov->iov_base, cnt);\n        else\n            bcopy (iov->iov_base, (caddr_t) cp, cnt);\n        iov->iov_base += cnt;\n        iov->iov_len -= cnt;\n        uio->uio_resid -= cnt;\n        uio->uio_offset += cnt;\n        cp += cnt;\n        n -= cnt;\n    }\n    return (error);\n}\n\n/*\n * Give next character to user as result of read.\n */\nint\nureadc (c, uio)\n    register int c;\n    register struct uio *uio;\n{\n    register struct iovec *iov;\n\nagain:\n    if (uio->uio_iovcnt == 0)\n        panic(\"ureadc\");\n    iov = uio->uio_iov;\n    if (iov->iov_len == 0 || uio->uio_resid == 0) {\n        uio->uio_iovcnt--;\n        uio->uio_iov++;\n        goto again;\n    }\n    *iov->iov_base = c;\n\n    iov->iov_base++;\n    iov->iov_len--;\n    uio->uio_resid--;\n    uio->uio_offset++;\n    return (0);\n}\n\n/*\n * Get next character written in by user from uio.\n */\nint\nuwritec(uio)\n    register struct uio *uio;\n{\n    register struct iovec *iov;\n    register int c;\n\n    if (uio->uio_resid == 0)\n        return (-1);\nagain:\n    if (uio->uio_iovcnt <= 0)\n        panic(\"uwritec\");\n    iov = uio->uio_iov;\n    if (iov->iov_len == 0) {\n        uio->uio_iov++;\n        if (--uio->uio_iovcnt == 0)\n            return (-1);\n        goto again;\n    }\n    c = (u_char) *iov->iov_base;\n\n    iov->iov_base++;\n    iov->iov_len--;\n    uio->uio_resid--;\n    uio->uio_offset++;\n    return (c & 0377);\n}\n\n/*\n * Copy bytes to/from the kernel and the user.\n */\nint\nuiofmove(cp, n, uio, iov)\n    caddr_t cp;\n    register int n;\n    struct uio *uio;\n    struct iovec *iov;\n{\n    if (uio->uio_rw == UIO_READ) {\n        /* From kernel to user. */\n        bcopy(cp, iov->iov_base, n);\n    } else {\n        /* From user to kernel. */\n        bcopy(iov->iov_base, cp, n);\n    }\n    return(0);\n}\n"
  },
  {
    "path": "sys/kern/kern_synch.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/buf.h>\n#include <sys/signal.h>\n#include <sys/signalvar.h>\n#include <sys/vm.h>\n#include <sys/kernel.h>\n#include <sys/systm.h>\n\n#define SQSIZE  16              /* Must be power of 2 */\n\n#define HASH(x) (((int)x >> 5) & (SQSIZE - 1))\n#define SCHMAG  8/10\n\nstruct  proc *slpque[SQSIZE];\n\nint     runrun;                 /* scheduling flag */\nchar    curpri;                 /* more scheduling */\n\n/*\n * Recompute process priorities, once a second\n */\nvoid\nschedcpu (caddr_t arg)\n{\n    register struct proc *p;\n    register int a;\n\n    wakeup((caddr_t)&lbolt);\n    for (p = allproc; p != NULL; p = p->p_nxt) {\n        if (p->p_time != 127)\n            p->p_time++;\n        /*\n         * this is where 2.11 does its real time alarms.  4.X uses\n         * timeouts, since it offers better than second resolution.\n         * Putting it here allows us to continue using use an int\n         * to store the number of ticks in the callout structure,\n         * since the kernel never has a timeout of greater than\n         * around 9 minutes.\n         */\n        if (p->p_realtimer.it_value && !--p->p_realtimer.it_value) {\n            psignal(p, SIGALRM);\n            p->p_realtimer.it_value = p->p_realtimer.it_interval;\n        }\n        if (p->p_stat == SSLEEP || p->p_stat == SSTOP)\n            if (p->p_slptime != 127)\n                p->p_slptime++;\n        if (p->p_slptime > 1)\n            continue;\n        a = (p->p_cpu & 0377) * SCHMAG + p->p_nice;\n        if (a < 0)\n            a = 0;\n        if (a > 255)\n            a = 255;\n        p->p_cpu = a;\n        if (p->p_pri >= PUSER)\n            setpri(p);\n    }\n    vmmeter();\n    if (runin != 0) {\n        runin = 0;\n        wakeup((caddr_t)&runin);\n    }\n    ++runrun;           /* swtch at least once a second */\n    timeout (schedcpu, (caddr_t) 0, hz);\n}\n\n/*\n * Recalculate the priority of a process after it has slept for a while.\n */\nvoid\nupdatepri(p)\n    register struct proc *p;\n{\n    register int a = p->p_cpu & 0377;\n\n    p->p_slptime--;     /* the first time was done in schedcpu */\n    while (a && --p->p_slptime)\n        a = (SCHMAG * a) /* + p->p_nice */;\n    if (a < 0)\n        a = 0;\n    if (a > 255)\n        a = 255;\n    p->p_cpu = a;\n    (void) setpri(p);\n}\n\n/*\n * Implement timeout for tsleep above.  If process hasn't been awakened\n * (p_wchan non zero) then set timeout flag and undo the sleep.  If proc\n * is stopped just unsleep so it will remain stopped.\n */\nstatic void\nendtsleep (p)\n    register struct proc *p;\n{\n    register int    s;\n\n    s = splhigh();\n    if (p->p_wchan) {\n        if (p->p_stat == SSLEEP)\n            setrun(p);\n        else\n            unsleep(p);\n        p->p_flag |= P_TIMEOUT;\n    }\n    splx(s);\n}\n\n/*\n * General sleep call \"borrowed\" from 4.4BSD - the 'wmesg' parameter was\n * removed due to data space concerns.  Sleeps at most timo/hz seconds\n * 0 means no timeout). NOTE: timeouts in 2.11BSD use a signed int and\n * thus can be at most 32767 'ticks' or about 540 seconds in the US with\n * 60hz power (~650 seconds if 50hz power is being used).\n *\n * If 'pri' includes the PCATCH flag signals are checked before and after\n * sleeping otherwise  signals are not checked.   Returns 0 if a wakeup was\n * done, EWOULDBLOCK if the timeout expired, ERESTART if the current system\n * call should be restarted, and EINTR if the system call should be\n * interrupted and EINTR returned to the user process.\n */\nint\ntsleep (ident, priority, timo)\n    caddr_t ident;\n    int priority;\n    u_int   timo;\n{\n    register struct proc *p = u.u_procp;\n    register struct proc **qp;\n    int s;\n    int sig, catch = priority & PCATCH;\n\n    s = splhigh();\n    if (panicstr) {\n        /*\n         * After a panic just give interrupts a chance then just return.  Don't\n         * run any other procs (or panic again below) in case this is the idle\n         * process and already asleep.  The splnet should be spl0 if the network\n         * was being used but for now avoid network interrupts that might cause\n         * another panic.\n         */\n        (void) splnet();\n        noop();\n        splx(s);\n        return(0);\n    }\n#ifdef  DIAGNOSTIC\n    if (ident == NULL || p->p_stat != SRUN)\n        panic(\"tsleep\");\n#endif\n    p->p_wchan = ident;\n    p->p_slptime = 0;\n    p->p_pri = priority & PRIMASK;\n    qp = &slpque[HASH(ident)];\n    p->p_link = *qp;\n    *qp = p;\n    if (timo)\n        timeout (endtsleep, (caddr_t)p, timo);\n    /*\n     * We put outselves on the sleep queue and start the timeout before calling\n     * CURSIG as we could stop there and a wakeup or a SIGCONT (or both) could\n     * occur while we were stopped.  A SIGCONT would cause us to be marked SSLEEP\n     * without resuming us thus we must be ready for sleep when CURSIG is called.\n     * If the wakeup happens while we're stopped p->p_wchan will be 0 upon\n     * return from CURSIG.\n     */\n    if (catch) {\n        p->p_flag |= P_SINTR;\n        sig = CURSIG(p);\n        if (sig) {\n            if (p->p_wchan)\n                unsleep(p);\n            p->p_stat = SRUN;\n            goto resume;\n        }\n        if (p->p_wchan == 0) {\n            catch = 0;\n            goto resume;\n        }\n    } else\n        sig = 0;\n\n    p->p_stat = SSLEEP;\n    if (p != &proc[0])\n        wakeup((caddr_t) &runin);\n    u.u_ru.ru_nvcsw++;\n    swtch();\nresume:\n    splx(s);\n    p->p_flag &= ~P_SINTR;\n    if (p->p_flag & P_TIMEOUT) {\n        p->p_flag &= ~P_TIMEOUT;\n        if (sig == 0)\n            return(EWOULDBLOCK);\n    } else if (timo)\n        untimeout (endtsleep, (caddr_t)p);\n    if (catch && (sig != 0 || (sig = CURSIG(p)))) {\n        if (u.u_sigintr & sigmask(sig))\n            return(EINTR);\n        return(ERESTART);\n    }\n    return(0);\n}\n\n/*\n * Give up the processor till a wakeup occurs on chan, at which time the\n * process enters the scheduling queue at priority pri.\n *\n * This routine was rewritten to use 'tsleep'.  The  old behaviour of sleep\n * being interruptible (if 'pri>PZERO') is emulated by setting PCATCH and\n * then performing the 'longjmp' if the return value of 'tsleep' is\n * ERESTART.\n *\n * Callers of this routine must be prepared for premature return, and check\n * that the reason for sleeping has gone away.\n */\nvoid\nsleep (chan, pri)\n    caddr_t chan;\n    int pri;\n{\n    register int priority = pri;\n\n    if (pri > PZERO)\n        priority |= PCATCH;\n\n    u.u_error = tsleep (chan, priority, 0);\n    /*\n     * sleep does not return anything.  If it was a non-interruptible sleep _or_\n     * a successful/normal sleep (one for which a wakeup was done) then return.\n     */\n    if ((priority & PCATCH) == 0 || (u.u_error == 0))\n        return;\n    /*\n     * XXX - compatibility uglyness.\n     *\n     * The tsleep() above will leave one of the following in u_error:\n     *\n     * 0 - a wakeup was done, this is handled above\n     * EWOULDBLOCK - since no timeout was passed to tsleep we will not see this\n     * EINTR - put into u_error for trap.c to find (interrupted syscall)\n     * ERESTART - system call to be restared\n     */\n    longjmp (u.u_procp->p_addr, &u.u_qsave);\n    /*NOTREACHED*/\n}\n\n/*\n * Remove a process from its wait queue\n */\nvoid\nunsleep (p)\n    register struct proc *p;\n{\n    register struct proc **hp;\n    register int s;\n\n    s = splhigh();\n    if (p->p_wchan) {\n        hp = &slpque[HASH(p->p_wchan)];\n        while (*hp != p)\n            hp = &(*hp)->p_link;\n        *hp = p->p_link;\n        p->p_wchan = 0;\n    }\n    splx(s);\n}\n\n/*\n * Wake up all processes sleeping on chan.\n */\nvoid\nwakeup (chan)\n    register caddr_t chan;\n{\n    register struct proc *p, **q;\n    struct proc **qp;\n    int s;\n\n    /*\n     * Since we are called at interrupt time, must insure normal\n     * kernel mapping to access proc.\n     */\n    s = splclock();\n    qp = &slpque[HASH(chan)];\nrestart:\n    for (q = qp; (p = *q); ) {\n        if (p->p_stat != SSLEEP && p->p_stat != SSTOP)\n            panic(\"wakeup\");\n        if (p->p_wchan==chan) {\n            p->p_wchan = 0;\n            *q = p->p_link;\n            if (p->p_stat == SSLEEP) {\n                /* OPTIMIZED INLINE EXPANSION OF setrun(p) */\n                if (p->p_slptime > 1)\n                    updatepri(p);\n                p->p_slptime = 0;\n                p->p_stat = SRUN;\n                if (p->p_flag & SLOAD)\n                    setrq(p);\n                /*\n                 * Since curpri is a usrpri,\n                 * p->p_pri is always better than curpri.\n                 */\n                runrun++;\n                if (! (p->p_flag & SLOAD)) {\n                    if (runout != 0) {\n                        runout = 0;\n                        wakeup((caddr_t)&runout);\n                    }\n                }\n                /* END INLINE EXPANSION */\n                goto restart;\n            }\n            p->p_slptime = 0;\n        } else\n            q = &p->p_link;\n    }\n    splx(s);\n}\n\n/*\n * Set the process running;\n * arrange for it to be swapped in if necessary.\n */\nvoid\nsetrun (p)\n    register struct proc *p;\n{\n    register int s;\n\n    s = splhigh();\n    switch (p->p_stat) {\n    case 0:\n    case SWAIT:\n    case SRUN:\n    case SZOMB:\n    default:\n        panic(\"setrun\");\n\n    case SSTOP:\n    case SSLEEP:\n        unsleep(p);     /* e.g. when sending signals */\n        break;\n\n    case SIDL:\n        break;\n    }\n    if (p->p_slptime > 1)\n        updatepri(p);\n    p->p_stat = SRUN;\n    if (p->p_flag & SLOAD)\n        setrq(p);\n    splx(s);\n    if (p->p_pri < curpri)\n        runrun++;\n    if (! (p->p_flag & SLOAD)) {\n        if (runout != 0) {\n            runout = 0;\n            wakeup((caddr_t)&runout);\n        }\n    }\n}\n\n/*\n * Set user priority.\n * The rescheduling flag (runrun)\n * is set if the priority is better\n * than the currently running process.\n */\nint\nsetpri (pp)\n    register struct proc *pp;\n{\n    register int p;\n\n    p = (pp->p_cpu & 0377)/16;\n    p += PUSER + pp->p_nice;\n    if (p > 127)\n        p = 127;\n    if (p < curpri)\n        runrun++;\n    pp->p_pri = p;\n    return (p);\n}\n\n/*\n * This routine is called to reschedule the CPU.  If the calling process is\n * not in RUN state, arrangements for it to restart must have been made\n * elsewhere, usually by calling via sleep.  There is a race here.  A process\n * may become ready after it has been examined.  In this case, idle() will be\n * called and will return in at most 1hz time, e.g. it's not worth putting an\n * spl() in.\n */\nvoid\nswtch()\n{\n    register struct proc *p, *q;\n    register int n;\n    struct proc *pp, *pq;\n    int s;\n\n#ifdef UCB_METER\n    cnt.v_swtch++;\n#endif\n    /* If not the idle process, resume the idle process. */\n    if (u.u_procp != &proc[0]) {\n        if (setjmp (&u.u_rsave)) {\n            /* Returned from swapper to user process. */\n            return;\n        }\n        /* Switch from user process to swapper. */\n        longjmp (proc[0].p_addr, &u.u_qsave);\n    }\n    /*\n     * The first save returns nonzero when proc 0 is resumed\n     * by another process (above); then the second is not done\n     * and the process-search loop is entered.\n     */\n    if (setjmp (&u.u_qsave)) {\n        /* Returned from user process. */\n        goto loop;\n    }\n    /*\n     * The first save returns 0 when swtch is called in proc 0\n     * from sched().  The second save returns 0 immediately, so\n     * in this case too the process-search loop is entered.\n     * Thus when proc 0 is awakened by being made runnable, it will\n     * find itself and resume itself at rsave, and return to sched().\n     */\n    if (setjmp (&u.u_rsave)) {\n        /* Swapper resumed by itself. */\n        return;\n    }\nloop:\n    s = splhigh();\n    noproc = 0;\n    runrun = 0;\n#ifdef DIAGNOSTIC\n    for (p = qs; p; p = p->p_link)\n        if (p->p_stat != SRUN)\n            panic (\"swtch SRUN\");\n#endif\n    pp = NULL;\n    q = NULL;\n    n = 128;\n    /*\n     * search for highest-priority runnable process\n     */\n    pq = 0;\n    for (p = qs; p; p = p->p_link) {\n        if (p->p_flag & SLOAD && p->p_pri < n) {\n            pp = p;\n            pq = q;\n            n = p->p_pri;\n        }\n        q = p;\n    }\n    /*\n     * if no process is runnable, idle.\n     */\n    p = pp;\n    if (p == NULL) {\n        idle();\n        goto loop;\n    }\n    if (pq)\n        pq->p_link = p->p_link;\n    else\n        qs = p->p_link;\n    curpri = n;\n    splx(s);\n    /*\n     * the rsave (ssave) contents are interpreted\n     * in the new address space\n     */\n    n = p->p_flag & SSWAP;\n    p->p_flag &= ~SSWAP;\n    longjmp (p->p_addr, n ? &u.u_ssave : &u.u_rsave);\n}\n\n/*\n * Put the process into the run queue.\n */\nvoid\nsetrq (p)\n    register struct proc *p;\n{\n    register int s;\n\n    s = splhigh();\n#ifdef DIAGNOSTIC\n    {           /* see if already on the run queue */\n        register struct proc *q;\n\n        for (q = qs;q != NULL;q = q->p_link)\n            if (q == p)\n                panic(\"setrq\");\n    }\n#endif\n    p->p_link = qs;\n    qs = p;\n    splx(s);\n}\n\n/*\n * Remove runnable job from run queue.  This is done when a runnable job\n * is swapped out so that it won't be selected in swtch().  It will be\n * reinserted in the qs with setrq when it is swapped back in.\n */\nvoid\nremrq (p)\n    register struct proc *p;\n{\n    register struct proc *q;\n    register int s;\n\n    s = splhigh();\n    if (p == qs)\n        qs = p->p_link;\n    else {\n        for (q = qs; q; q = q->p_link)\n            if (q->p_link == p) {\n                q->p_link = p->p_link;\n                goto done;\n            }\n        panic(\"remrq\");\n    }\ndone:\n    splx(s);\n}\n"
  },
  {
    "path": "sys/kern/kern_sysctl.c",
    "content": "/*-\n * Copyright (c) 1982, 1986, 1989, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Mike Karels at Berkeley Software Design, Inc.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n *\t@(#)kern_sysctl.c\t8.4.12 (2.11BSD) 2000/5/17\n */\n\n/*\n * sysctl system call.\n */\n\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/systm.h>\n#include <sys/proc.h>\n#include <sys/buf.h>\n#include <sys/kernel.h>\n#include <sys/file.h>\n#include <sys/inode.h>\n#include <sys/ioctl.h>\n#include <sys/tty.h>\n#include <sys/vm.h>\n#include <sys/map.h>\n#include <sys/sysctl.h>\n#include <machine/cpu.h>\n#include <sys/conf.h>\n\nsysctlfn kern_sysctl;\nsysctlfn hw_sysctl;\n#ifdef DEBUG\nsysctlfn debug_sysctl;\n#endif\nsysctlfn vm_sysctl;\nsysctlfn fs_sysctl;\n#ifdef INET\nsysctlfn net_sysctl;\n#endif\nsysctlfn cpu_sysctl;\n\nstruct sysctl_args {\n\tint\t*name;\n\tu_int\t namelen;\n\tvoid\t*old;\n\tsize_t\t*oldlenp;\n\tvoid\t*new;\n\tsize_t\t newlen;\n};\n\nvoid\n__sysctl()\n{\n\tstruct sysctl_args *uap = (struct sysctl_args *)u.u_arg;\n\tint error;\n\tu_int oldlen = 0;\n\tsysctlfn *fn;\n\tint name[CTL_MAXNAME];\n\n\tif (uap->new != NULL && !suser())\n\t\treturn;\n\t/*\n\t * All top-level sysctl names are non-terminal.\n\t */\n\tif (uap->namelen > CTL_MAXNAME || uap->namelen < 2) {\n\t\tu.u_error = EINVAL;\n\t\treturn;\n\t}\n\terror = copyin((caddr_t)uap->name, (caddr_t)&name,\n\t    uap->namelen * sizeof(int));\n\tif (error) {\n\t\tu.u_error = error;\n\t\treturn;\n\t}\n\n\tswitch (name[0]) {\n\tcase CTL_KERN:\n\t\tfn = kern_sysctl;\n\t\tbreak;\n\tcase CTL_HW:\n\t\tfn = hw_sysctl;\n\t\tbreak;\n\tcase CTL_VM:\n\t\tfn = vm_sysctl;\n\t\tbreak;\n#ifdef INET\n\tcase CTL_NET:\n\t\tfn = net_sysctl;\n\t\tbreak;\n#endif\n#ifdef notyet\n\tcase CTL_FS:\n\t\tfn = fs_sysctl;\n\t\tbreak;\n#endif\n\tcase CTL_MACHDEP:\n\t\tfn = cpu_sysctl;\n\t\tbreak;\n#ifdef DEBUG\n\tcase CTL_DEBUG:\n\t\tfn = debug_sysctl;\n\t\tbreak;\n#endif\n\tdefault:\n\t\tu.u_error = EOPNOTSUPP;\n\t\treturn;\n\t}\n\n\tif (uap->oldlenp && (error = copyin((caddr_t)uap->oldlenp,\n\t    (caddr_t)&oldlen, sizeof(oldlen)))) {\n\t\tu.u_error = error;\n\t\treturn;\n\t}\n\tif (uap->old != NULL) {\n\t\twhile (memlock.sl_lock) {\n\t\t\tmemlock.sl_want = 1;\n\t\t\tsleep((caddr_t)&memlock, PRIBIO + 1);\n\t\t\tmemlock.sl_locked++;\n\t\t}\n\t\tmemlock.sl_lock = 1;\n\t}\n\terror = (*fn)(name + 1, uap->namelen - 1, uap->old, &oldlen,\n\t    uap->new, uap->newlen);\n\tif (uap->old != NULL) {\n\t\tmemlock.sl_lock = 0;\n\t\tif (memlock.sl_want) {\n\t\t\tmemlock.sl_want = 0;\n\t\t\twakeup((caddr_t)&memlock);\n\t\t}\n\t}\n\tif (error) {\n\t\tu.u_error = error;\n\t\treturn;\n\t}\n\tif (uap->oldlenp) {\n\t\terror = copyout((caddr_t)&oldlen, (caddr_t)uap->oldlenp,\n\t\t    sizeof(oldlen));\n\t\tif (error) {\n\t\t\tu.u_error = error;\n\t\t\treturn;\n\t\t}\n\t}\n\tu.u_rval = oldlen;\n}\n\n/*\n * Kernel related system variables.\n */\nint\nkern_sysctl(int *name, u_int namelen, void *oldp, size_t *oldlenp,\n    void *newp, size_t newlen)\n{\n\tint error, level;\n\tu_long longhostid;\n\n\t/* All sysctl names at this level are terminal. */\n\tif (namelen != 1 && !(name[0] == KERN_PROC || name[0] == KERN_PROF))\n\t\treturn (ENOTDIR);\t\t/* overloaded */\n\n\tswitch (name[0]) {\n\tcase KERN_OSTYPE:\n\t\treturn (sysctl_rdstring(oldp, oldlenp, newp, ostype));\n\tcase KERN_OSRELEASE:\n\t\treturn (sysctl_rdstring(oldp, oldlenp, newp, osrelease));\n\tcase KERN_OSREV:\n\t\treturn (sysctl_rdlong(oldp, oldlenp, newp, (long)DiscoBSD));\n\tcase KERN_OSVERSION:\n\t\treturn (sysctl_rdstring(oldp, oldlenp, newp, osversion));\n\tcase KERN_VERSION:\n\t\treturn (sysctl_rdstring(oldp, oldlenp, newp, version));\n\tcase KERN_MAXINODES:\n\t\treturn (sysctl_rdint(oldp, oldlenp, newp, NINODE));\n\tcase KERN_MAXPROC:\n\t\treturn (sysctl_rdint(oldp, oldlenp, newp, NPROC));\n\tcase KERN_MAXFILES:\n\t\treturn (sysctl_rdint(oldp, oldlenp, newp, NFILE));\n\tcase KERN_ARGMAX:\n\t\treturn (sysctl_rdint(oldp, oldlenp, newp, NCARGS));\n\tcase KERN_SECURELVL:\n\t\tlevel = securelevel;\n\t\tif ((error = sysctl_int(oldp, oldlenp, newp, newlen, &level)) ||\n\t\t    newp == NULL)\n\t\t\treturn (error);\n\t\tif (level < securelevel && u.u_procp->p_pid != 1)\n\t\t\treturn (EPERM);\n\t\tsecurelevel = level;\n\t\treturn (0);\n\tcase KERN_HOSTNAME:\n\t\terror = sysctl_string(oldp, oldlenp, newp, newlen,\n\t\t    hostname, sizeof(hostname));\n\t\tif (newp && !error)\n\t\t\thostnamelen = newlen;\n\t\treturn (error);\n\tcase KERN_HOSTID:\n\t\tlonghostid = hostid;\n\t\terror = sysctl_long(oldp, oldlenp, newp, newlen,\n\t\t    (long *)&longhostid);\n\t\thostid = longhostid;\n\t\treturn (error);\n\tcase KERN_CLOCKRATE:\n\t\treturn (sysctl_clockrate(oldp, oldlenp));\n\tcase KERN_BOOTTIME:\n\t\treturn (sysctl_rdstruct(oldp, oldlenp, newp, &boottime,\n\t\t    sizeof(struct timeval)));\n\tcase KERN_INODE:\n\t\treturn (sysctl_inode(oldp, oldlenp));\n\tcase KERN_PROC:\n\t\treturn (sysctl_doproc(name + 1, namelen - 1, oldp, oldlenp));\n\tcase KERN_FILE:\n\t\treturn (sysctl_file(oldp, oldlenp));\n#ifdef GPROF\n\tcase KERN_PROF:\n\t\treturn (sysctl_doprof(name + 1, namelen - 1, oldp, oldlenp,\n\t\t    newp, newlen));\n#endif\n\tcase KERN_NGROUPS:\n\t\treturn (sysctl_rdint(oldp, oldlenp, newp, NGROUPS));\n\tcase KERN_JOB_CONTROL:\n\t\treturn (sysctl_rdint(oldp, oldlenp, newp, 1));\n\tcase KERN_POSIX1:\n\tcase KERN_SAVED_IDS:\n\t\treturn (sysctl_rdint(oldp, oldlenp, newp, 0));\n\tdefault:\n\t\treturn (EOPNOTSUPP);\n\t}\n\t/* NOTREACHED */\n}\n\n/*\n * Hardware related system variables.\n */\nint\nhw_sysctl(int *name, u_int namelen, void *oldp, size_t *oldlenp,\n    void *newp, size_t newlen)\n{\n\textern char machine[], machine_arch[], cpu_model[];\n\n\t/* All sysctl names at this level are terminal. */\n\tif (namelen != 1)\n\t\treturn (ENOTDIR);\t\t/* overloaded */\n\n\tswitch (name[0]) {\n\tcase HW_MACHINE:\n\t\treturn (sysctl_rdstring(oldp, oldlenp, newp, machine));\n\tcase HW_MODEL:\n\t\treturn (sysctl_rdstring(oldp, oldlenp, newp, cpu_model));\n\tcase HW_NCPU:\n\t\treturn (sysctl_rdint(oldp, oldlenp, newp, 1));\t/* XXX */\n\tcase HW_BYTEORDER:\n\t\treturn (sysctl_rdint(oldp, oldlenp, newp, ENDIAN));\n\tcase HW_PHYSMEM:\n\t\treturn (sysctl_rdlong(oldp, oldlenp, newp, physmem));\n#ifdef UCB_METER\n\tcase HW_USERMEM:\n\t\treturn (sysctl_rdlong(oldp, oldlenp, newp, freemem));\n#endif\n\tcase HW_PAGESIZE:\n\t\treturn (sysctl_rdint(oldp, oldlenp, newp, DEV_BSIZE));\n\tcase HW_MACHINE_ARCH:\n\t\treturn (sysctl_rdstring(oldp, oldlenp, newp, machine_arch));\n\tdefault:\n\t\treturn (EOPNOTSUPP);\n\t}\n\t/* NOTREACHED */\n}\n\n#ifdef DEBUG\n/*\n * Debugging related system variables.\n */\nstruct ctldebug debug0, debug1, debug2, debug3, debug4;\nstruct ctldebug debug5, debug6, debug7, debug8, debug9;\nstruct ctldebug debug10, debug11, debug12, debug13, debug14;\nstruct ctldebug debug15, debug16, debug17, debug18, debug19;\nstatic struct ctldebug *debugvars[CTL_DEBUG_MAXID] = {\n\t&debug0, &debug1, &debug2, &debug3, &debug4,\n\t&debug5, &debug6, &debug7, &debug8, &debug9,\n\t&debug10, &debug11, &debug12, &debug13, &debug14,\n\t&debug15, &debug16, &debug17, &debug18, &debug19,\n};\n\nint\ndebug_sysctl(int *name, u_int namelen, void *oldp, size_t *oldlenp,\n    void *newp, size_t newlen)\n{\n\tstruct ctldebug *cdp;\n\n\t/* All sysctl names at this level are name and field. */\n\tif (namelen != 2)\n\t\treturn (ENOTDIR);\t\t/* overloaded */\n\tcdp = debugvars[name[0]];\n\tif (cdp->debugname == 0)\n\t\treturn (EOPNOTSUPP);\n\tswitch (name[1]) {\n\tcase CTL_DEBUG_NAME:\n\t\treturn (sysctl_rdstring(oldp, oldlenp, newp, cdp->debugname));\n\tcase CTL_DEBUG_VALUE:\n\t\treturn (sysctl_int(oldp, oldlenp, newp, newlen, cdp->debugvar));\n\tdefault:\n\t\treturn (EOPNOTSUPP);\n\t}\n\t/* NOTREACHED */\n}\n#endif /* DEBUG */\n\n/*\n * Bit of a hack.  2.11 currently uses 'short avenrun[3]' and a fixed scale\n * of 256.  In order not to break all the applications which nlist() for\n * 'avenrun' we build a local 'averunnable' structure here to return to the\n * user.  Eventually (after all applications which look up the load average\n * the old way) have been converted we can change things.\n *\n * We do not call vmtotal(), that could get rather expensive, rather we rely\n * on the 5 second update.\n *\n * The swapmap case is a 2.11BSD extension.\n */\nint\nvm_sysctl(int *name, u_int namelen, void *oldp, size_t *oldlenp,\n    void *newp, size_t newlen)\n{\n\tstruct loadavg averunnable;\t\t/* loadavg in resource.h */\n\n\t/* All sysctl names at this level are terminal. */\n\tif (namelen != 1)\n\t\treturn (ENOTDIR);\t\t/* overloaded */\n\n\tswitch (name[0]) {\n\tcase VM_LOADAVG:\n\t\taverunnable.fscale = 256;\n\t\taverunnable.ldavg[0] = avenrun[0];\n\t\taverunnable.ldavg[1] = avenrun[1];\n\t\taverunnable.ldavg[2] = avenrun[2];\n\t\treturn (sysctl_rdstruct(oldp, oldlenp, newp, &averunnable,\n\t\t    sizeof(averunnable)));\n\tcase VM_METER:\n#ifdef notsure\n\t\tvmtotal();\t/* Could be expensive to do this every time. */\n#endif\n\t\treturn (sysctl_rdstruct(oldp, oldlenp, newp, &total,\n\t\t    sizeof(total)));\n\tcase VM_SWAPMAP:\n\t\tif (oldp == NULL) {\n\t\t\t*oldlenp = (char *)swapmap[0].m_limit -\n\t\t\t    (char *)swapmap[0].m_map;\n\t\t\treturn (0);\n\t\t}\n\t\treturn (sysctl_rdstruct(oldp, oldlenp, newp, swapmap,\n\t\t    (int)swapmap[0].m_limit - (int)swapmap[0].m_map));\n\tdefault:\n\t\treturn (EOPNOTSUPP);\n\t}\n\t/* NOTREACHED */\n}\n\n/*\n * Validate parameters and get old / set new parameters\n * for an integer-valued sysctl function.\n */\nint\nsysctl_int(void *oldp, size_t *oldlenp, void *newp, size_t newlen, int *valp)\n{\n\tint error = 0;\n\n\tif (oldp && *oldlenp < sizeof(int))\n\t\treturn (ENOMEM);\n\tif (newp && newlen != sizeof(int))\n\t\treturn (EINVAL);\n\t*oldlenp = sizeof(int);\n\tif (oldp)\n\t\terror = copyout((caddr_t)valp, (caddr_t)oldp, sizeof(int));\n\tif (error == 0 && newp)\n\t\terror = copyin((caddr_t)newp, (caddr_t)valp, sizeof(int));\n\treturn (error);\n}\n\n/*\n * As above, but read-only.\n */\nint\nsysctl_rdint(void *oldp, size_t *oldlenp, void *newp, int val)\n{\n\tint error = 0;\n\n\tif (oldp && *oldlenp < sizeof(int))\n\t\treturn (ENOMEM);\n\tif (newp)\n\t\treturn (EPERM);\n\t*oldlenp = sizeof(int);\n\tif (oldp)\n\t\terror = copyout((caddr_t)&val, oldp, sizeof(int));\n\treturn (error);\n}\n\n/*\n * Validate parameters and get old / set new parameters\n * for a long-valued sysctl function.\n */\nint\nsysctl_long(void *oldp, size_t *oldlenp, void *newp, size_t newlen, long *valp)\n{\n\tint error = 0;\n\n\tif (oldp && *oldlenp < sizeof(long))\n\t\treturn (ENOMEM);\n\tif (newp && newlen != sizeof(long))\n\t\treturn (EINVAL);\n\t*oldlenp = sizeof(long);\n\tif (oldp)\n\t\terror = copyout((caddr_t)valp, (caddr_t)oldp, sizeof(long));\n\tif (error == 0 && newp)\n\t\terror = copyin((caddr_t)newp, (caddr_t)valp, sizeof(long));\n\treturn (error);\n}\n\n/*\n * As above, but read-only.\n */\nint\nsysctl_rdlong(void *oldp, size_t *oldlenp, void *newp, long val)\n{\n\tint error = 0;\n\n\tif (oldp && *oldlenp < sizeof(long))\n\t\treturn (ENOMEM);\n\tif (newp)\n\t\treturn (EPERM);\n\t*oldlenp = sizeof(long);\n\tif (oldp)\n\t\terror = copyout((caddr_t)&val, oldp, sizeof(long));\n\treturn (error);\n}\n\n/*\n * Validate parameters and get old / set new parameters\n * for a string-valued sysctl function.\n */\nint\nsysctl_string(void *oldp, size_t *oldlenp, void *newp, size_t newlen,\n    char *str, int maxlen)\n{\n\tint len, error = 0;\n\n\tlen = strlen(str) + 1;\n\tif (oldp && *oldlenp < len)\n\t\treturn (ENOMEM);\n\tif (newp && newlen >= maxlen)\n\t\treturn (EINVAL);\n\tif (oldp) {\n\t\t*oldlenp = len;\n\t\terror = copyout(str, oldp, len);\n\t}\n\tif (error == 0 && newp) {\n\t\terror = copyin(newp, str, newlen);\n\t\tstr[newlen] = 0;\n\t}\n\treturn (error);\n}\n\n/*\n * As above, but read-only.\n */\nint\nsysctl_rdstring(void *oldp, size_t *oldlenp, void *newp, const char *str)\n{\n\tint len, error = 0;\n\n\tlen = strlen(str) + 1;\n\tif (oldp && *oldlenp < len)\n\t\treturn (ENOMEM);\n\tif (newp)\n\t\treturn (EPERM);\n\t*oldlenp = len;\n\tif (oldp)\n\t\terror = copyout((caddr_t)str, oldp, len);\n\treturn (error);\n}\n\n/*\n * Validate parameters and get old / set new parameters\n * for a structure-oriented sysctl function.\n */\nint\nsysctl_struct(void *oldp, size_t *oldlenp, void *newp, size_t newlen,\n    void *sp, int len)\n{\n\tint error = 0;\n\n\tif (oldp && *oldlenp < len)\n\t\treturn (ENOMEM);\n\tif (newp && newlen > len)\n\t\treturn (EINVAL);\n\tif (oldp) {\n\t\t*oldlenp = len;\n\t\terror = copyout(sp, oldp, len);\n\t}\n\tif (error == 0 && newp)\n\t\terror = copyin(newp, sp, len);\n\treturn (error);\n}\n\n/*\n * As above, but read-only.\n */\nint\nsysctl_rdstruct(void *oldp, size_t *oldlenp, void *newp, void *sp, int len)\n{\n\tint error = 0;\n\n\tif (oldp && *oldlenp < len)\n\t\treturn (ENOMEM);\n\tif (newp)\n\t\treturn (EPERM);\n\t*oldlenp = len;\n\tif (oldp)\n\t\terror = copyout(sp, oldp, len);\n\treturn (error);\n}\n\n/*\n * Get file structures.\n */\nint\nsysctl_file(char *where, size_t *sizep)\n{\n\tint buflen, error;\n\tstruct file *fp;\n\tstruct file *fpp;\n\tchar *start = where;\n\tint i;\n\n\tbuflen = *sizep;\n\tif (where == NULL) {\n\t\tfor (i = 0, fp = file; fp < file + NFILE; fp++)\n\t\t\tif (fp->f_count)\n\t\t\t\ti++;\n\n#define FPTRSZ\tsizeof(struct file *)\n#define FILESZ\tsizeof(struct file)\n\t\t/*\n\t\t * Overestimate by 5 files.\n\t\t */\n\t\t*sizep = (i + 5) * (FILESZ + FPTRSZ);\n\t\treturn (0);\n\t}\n\n\t/*\n\t * Array of extended file structures: first the address then the\n\t * file structure.\n\t */\n\tfor (fp = file; fp < file + NFILE; fp++) {\n\t\tif (fp->f_count == 0)\n\t\t\tcontinue;\n\t\tif (buflen < (FPTRSZ + FILESZ)) {\n\t\t\t*sizep = where - start;\n\t\t\treturn (ENOMEM);\n\t\t}\n\t\tfpp = fp;\n\t\tif ((error = copyout((caddr_t)&fpp, (caddr_t)where, FPTRSZ)) ||\n\t\t    (error = copyout((caddr_t)fp, (caddr_t)(where + FPTRSZ),\n\t\t    FILESZ)))\n\t\t\treturn (error);\n\t\tbuflen -= (FPTRSZ + FILESZ);\n\t\twhere += (FPTRSZ + FILESZ);\n\t}\n\t*sizep = where - start;\n\treturn (0);\n}\n\n/*\n * This one is in kern_clock.c in 4.4 but placed here for the reasons\n * given earlier (back around line 367).\n */\nint\nsysctl_clockrate(char *where, size_t *sizep)\n{\n\tstruct clockinfo clkinfo;\n\n\t/*\n\t * Construct clockinfo structure.\n\t */\n\tbzero(&clkinfo, sizeof clkinfo);\n\tclkinfo.tick = usechz;\n\tclkinfo.hz = hz;\n\tclkinfo.profhz = 0;\n\tclkinfo.stathz = hz;\n\treturn (sysctl_rdstruct(where, sizep, NULL, &clkinfo, sizeof clkinfo));\n}\n\n/*\n * Dump inode list (via sysctl).\n * Copyout address of inode followed by inode.\n */\n/* ARGSUSED */\nint\nsysctl_inode(char *where, size_t *sizep)\n{\n\tstruct inode *ip;\n\tchar *bp = where;\n\tstruct inode *ipp;\n\tchar *ewhere;\n\tint error, numi;\n\n\tfor (numi = 0, ip = inode; ip < inode + NINODE; ip++)\n\t\tif (ip->i_count)\n\t\t\tnumi++;\n\n#define IPTRSZ\tsizeof(struct inode *)\n#define INODESZ\tsizeof(struct inode)\n\tif (where == NULL) {\n\t\t*sizep = (numi + 5) * (IPTRSZ + INODESZ);\n\t\treturn (0);\n\t}\n\tewhere = where + *sizep;\n\n\tfor (ip = inode; ip < inode + NINODE; ip++) {\n\t\tif (ip->i_count == 0)\n\t\t\tcontinue;\n\t\tif (bp + IPTRSZ + INODESZ > ewhere) {\n\t\t\t*sizep = bp - where;\n\t\t\treturn (ENOMEM);\n\t\t}\n\t\tipp = ip;\n\t\tif ((error = copyout((caddr_t)&ipp, bp, IPTRSZ)) ||\n\t\t    (error = copyout((caddr_t)ip, bp + IPTRSZ, INODESZ)))\n\t\t\treturn (error);\n\t\tbp += IPTRSZ + INODESZ;\n\t}\n\n\t*sizep = bp - where;\n\treturn (0);\n}\n\n/*\n * Try overestimating by 5 procs.\n */\n#define KERN_PROCSLOP\t(5 * sizeof(struct kinfo_proc))\n\nint\nsysctl_doproc(int *name, u_int namelen, char *where, size_t *sizep)\n{\n\tstruct proc *p;\n\tstruct kinfo_proc *dp = (struct kinfo_proc *)where;\n\tint needed = 0;\n\tint buflen = where != NULL ? *sizep : 0;\n\tint doingzomb;\n\tstruct eproc eproc;\n\tint error = 0;\n\tdev_t ttyd;\n\tuid_t ruid;\n\tstruct tty *ttyp;\n\n\tif (namelen != 2 && !(namelen == 1 && name[0] == KERN_PROC_ALL))\n\t\treturn (EINVAL);\n\tp = (struct proc *)allproc;\n\tdoingzomb = 0;\nagain:\n\tfor (; p != NULL; p = p->p_nxt) {\n\t\t/*\n\t\t * Skip embryonic processes.\n\t\t */\n\t\tif (p->p_stat == SIDL)\n\t\t\tcontinue;\n\t\t/*\n\t\t * TODO: sysctl_oproc - make more efficient (see notes below).\n\t\t * do by session.\n\t\t */\n\t\tswitch (name[0]) {\n\t\tcase KERN_PROC_PID:\n\t\t\t/* Could do this with just a lookup. */\n\t\t\tif (p->p_pid != (pid_t)name[1])\n\t\t\t\tcontinue;\n\t\t\tbreak;\n\n\t\tcase KERN_PROC_PGRP:\n\t\t\t/* Could do this by traversing pgrp. */\n\t\t\tif (p->p_pgrp != (pid_t)name[1])\n\t\t\t\tcontinue;\n\t\t\tbreak;\n\n\t\tcase KERN_PROC_TTY:\n\t\t\tfill_from_u(p, &ruid, &ttyp, &ttyd);\n\t\t\tif (!ttyp || ttyd != (dev_t)name[1])\n\t\t\t\tcontinue;\n\t\t\tbreak;\n\n\t\tcase KERN_PROC_UID:\n\t\t\tif (p->p_uid != (uid_t)name[1])\n\t\t\t\tcontinue;\n\t\t\tbreak;\n\n\t\tcase KERN_PROC_RUID:\n\t\t\tfill_from_u(p, &ruid, &ttyp, &ttyd);\n\t\t\tif (ruid != (uid_t)name[1])\n\t\t\t\tcontinue;\n\t\t\tbreak;\n\n\t\tcase KERN_PROC_ALL:\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\treturn (EINVAL);\n\t\t}\n\t\tif (buflen >= sizeof(struct kinfo_proc)) {\n\t\t\tfill_eproc(p, &eproc);\n\t\t\tif ((error = copyout((caddr_t)p,\n\t\t\t    (caddr_t)&dp->kp_proc, sizeof(struct proc))))\n\t\t\t\treturn (error);\n\t\t\tif ((error = copyout((caddr_t)&eproc,\n\t\t\t    (caddr_t)&dp->kp_eproc, sizeof(eproc))))\n\t\t\t\treturn (error);\n\t\t\tdp++;\n\t\t\tbuflen -= sizeof(struct kinfo_proc);\n\t\t}\n\t\tneeded += sizeof(struct kinfo_proc);\n\t}\n\tif (doingzomb == 0) {\n\t\tp = zombproc;\n\t\tdoingzomb++;\n\t\tgoto again;\n\t}\n\tif (where != NULL) {\n\t\t*sizep = (caddr_t)dp - where;\n\t\tif (needed > *sizep)\n\t\t\treturn (ENOMEM);\n\t} else {\n\t\tneeded += KERN_PROCSLOP;\n\t\t*sizep = needed;\n\t}\n\treturn (0);\n}\n\n/*\n * Fill in an eproc structure for the specified process.  Slightly\n * inefficient because we have to access the u area again for the\n * information not kept in the proc structure itself.  Can't afford\n * to expand the proc struct so we take a slight speed hit here.\n */\nvoid\nfill_eproc(struct proc *p, struct eproc *ep)\n{\n\tstruct tty *ttyp;\n\n\tep->e_paddr = p;\n\tfill_from_u(p, &ep->e_ruid, &ttyp, &ep->e_tdev);\n\tif (ttyp)\n\t\tep->e_tpgid = ttyp->t_pgrp;\n\telse\n\t\tep->e_tpgid = 0;\n}\n\n/*\n * Three pieces of information we need about a process are not kept in\n * the proc table: real uid, controlling terminal device, and controlling\n * terminal tty struct pointer.  For these we must look in either the u\n * area or the swap area.  If the process is still in memory this is\n * easy but if the process has been swapped out we have to read in the\n * u area.\n *\n * XXX - We rely on the fact that u_ttyp, u_ttyd, and u_ruid are all within\n * XXX - the first 1kb of the u area.  If this ever changes the logic below\n * XXX - will break (and badly).  At the present time (97/9/2) the u area\n * XXX - is 856 bytes long.\n */\nvoid\nfill_from_u(struct proc *p, uid_t *rup, struct tty **ttp, dev_t *tdp)\n{\n\tstruct buf *bp;\n\tdev_t ttyd;\n\tuid_t ruid;\n\tstruct tty *ttyp;\n\tstruct user *up;\n\n\tif (p->p_stat == SZOMB) {\n\t\truid = (uid_t)-2;\n\t\tttyp = NULL;\n\t\tttyd = NODEV;\n\t\tgoto out;\n\t}\n\tif (p->p_flag & SLOAD) {\n\t\tttyd = ((struct user *)p->p_addr)->u_ttyd;\n\t\tttyp = ((struct user *)p->p_addr)->u_ttyp;\n\t\truid = ((struct user *)p->p_addr)->u_ruid;\n\t} else {\n\t\tbp = geteblk();\n\t\tbp->b_dev = swapdev;\n\t\tbp->b_blkno = (daddr_t)p->p_addr;\n\t\tbp->b_bcount = DEV_BSIZE;\t/* XXX */\n\t\tbp->b_flags = B_READ;\n\n\t\t(*bdevsw[major(swapdev)].d_strategy)(bp);\n\t\tbiowait(bp);\n\n\t\tif (u.u_error) {\n\t\t\tttyd = NODEV;\n\t\t\tttyp = NULL;\n\t\t\truid = (uid_t)-2;\n\t\t} else {\n\t\t\tup = (struct user *)bp->b_addr;\n\t\t\truid = up->u_ruid;\t/* u_ruid = offset 164 */\n\t\t\tttyd = up->u_ttyd;\t/* u_ttyd = offset 654 */\n\t\t\tttyp = up->u_ttyp;\t/* u_ttyp = offset 652 */\n\t\t}\n\t\tbp->b_flags |= B_AGE;\n\t\tbrelse(bp);\n\t\tu.u_error = 0;\t\t\t/* XXX */\n\t}\nout:\n\tif (rup)\n\t\t*rup = ruid;\n\tif (ttp)\n\t\t*ttp = ttyp;\n\tif (tdp)\n\t\t*tdp = ttyd;\n}\n"
  },
  {
    "path": "sys/kern/kern_time.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/kernel.h>\n#include <sys/systm.h>\n\nstatic void\nsetthetime (tv)\n    register struct timeval *tv;\n{\n    int s;\n\n    if (! suser())\n        return;\n#ifdef  NOTNOW\n/*\n * If the system is secure, we do not allow the time to be set to an\n * earlier value.  The time may be slowed (using adjtime) but not set back.\n *\n * NOTE:  Can not do this until ntpd is updated to deal with the coarse (50, 60\n *    hz) clocks.  Ntpd wants to adjust time system clock a few microseconds\n *    at a time (which gets rounded to 0 in adjtime below). If that fails\n *    ntpd uses settimeofday to step the time backwards which obviously\n *    will fail if the next 'if' is enabled - all that does is fill up the\n *    logfiles with \"can't set time\" messages and the time keeps drifting.\n*/\n    if (securelevel > 0 && timercmp(tv, &time, <)) {\n        u.u_error = EPERM;  /* XXX */\n        return;\n    }\n#endif\n/* WHAT DO WE DO ABOUT PENDING REAL-TIME TIMEOUTS??? */\n    boottime.tv_sec += tv->tv_sec - time.tv_sec;\n    s = splhigh();\n    time = *tv;\n    lbolt = time.tv_usec / usechz;\n    splx(s);\n#ifdef  notyet\n    /*\n     * if you have a time of day board, use it here\n     */\n    resettodr();\n#endif\n}\n\n/*\n * Time of day and interval timer support.\n *\n * These routines provide the kernel entry points to get and set\n * the time-of-day.\n */\nvoid\ngettimeofday()\n{\n    register struct a {\n        struct  timeval *tp;\n        struct  timezone *tzp;\n    } *uap = (struct a *)u.u_arg;\n    struct timeval atv;\n    int s;\n    register u_int  ms;\n\n    if (uap->tp) {\n        /*\n         * We don't resolve the milliseconds on every clock tick; it's\n         * easier to do it here.  Long casts are out of paranoia.\n         */\n        s = splhigh();\n        atv = time;\n        ms = lbolt;\n        splx(s);\n        atv.tv_usec = (long)ms * usechz;\n        u.u_error = copyout ((caddr_t) &atv, (caddr_t) uap->tp,\n            sizeof(atv));\n        if (u.u_error)\n            return;\n    }\n    if (uap->tzp)\n        u.u_error = copyout ((caddr_t) &tz, (caddr_t) uap->tzp,\n            sizeof (tz));\n}\n\nvoid\nsettimeofday()\n{\n    register struct a {\n        struct  timeval *tv;\n        struct  timezone *tzp;\n    } *uap = (struct a *)u.u_arg;\n    struct timeval atv;\n    struct timezone atz;\n\n    if (uap->tv) {\n        u.u_error = copyin((caddr_t)uap->tv, (caddr_t)&atv,\n            sizeof (struct timeval));\n        if (u.u_error)\n            return;\n        setthetime(&atv);\n        if (u.u_error)\n            return;\n    }\n    if (uap->tzp && suser()) {\n        u.u_error = copyin((caddr_t)uap->tzp, (caddr_t)&atz,\n            sizeof (atz));\n        if (u.u_error == 0)\n            tz = atz;\n    }\n}\n\nvoid\nadjtime()\n{\n    register struct a {\n        struct timeval *delta;\n        struct timeval *olddelta;\n    } *uap = (struct a *)u.u_arg;\n    struct timeval atv;\n    register int s;\n    long adjust;\n\n    if (!suser())\n        return;\n    u.u_error = copyin((caddr_t)uap->delta, (caddr_t)&atv,\n        sizeof (struct timeval));\n    if (u.u_error)\n        return;\n    adjust = (atv.tv_sec * hz) + (atv.tv_usec / usechz);\n    /* if unstoreable values, just set the clock */\n    if (adjust > 0x7fff || adjust < 0x8000) {\n        s = splclock();\n        time.tv_sec += atv.tv_sec;\n        lbolt += atv.tv_usec / usechz;\n        while (lbolt >= hz) {\n            lbolt -= hz;\n            ++time.tv_sec;\n        }\n        splx(s);\n        if (!uap->olddelta)\n            return;\n        atv.tv_sec = atv.tv_usec = 0;\n    } else {\n        if (!uap->olddelta) {\n            adjdelta = adjust;\n            return;\n        }\n        atv.tv_sec = adjdelta / hz;\n        atv.tv_usec = (adjdelta % hz) * usechz;\n        adjdelta = adjust;\n    }\n    u.u_error = copyout ((caddr_t) &atv, (caddr_t) uap->olddelta,\n        sizeof (struct timeval));\n}\n\nvoid\ngetitimer()\n{\n    register struct a {\n        u_int   which;\n        struct  itimerval *itv;\n    } *uap = (struct a *)u.u_arg;\n    struct itimerval aitv;\n    register int s;\n\n    if (uap->which > ITIMER_PROF) {\n        u.u_error = EINVAL;\n        return;\n    }\n    aitv.it_interval.tv_usec = 0;\n    aitv.it_value.tv_usec = 0;\n    s = splclock();\n    if (uap->which == ITIMER_REAL) {\n        register struct proc *p = u.u_procp;\n\n        aitv.it_interval.tv_sec = p->p_realtimer.it_interval;\n        aitv.it_value.tv_sec = p->p_realtimer.it_value;\n    } else {\n        register struct k_itimerval *t = &u.u_timer[uap->which - 1];\n\n        aitv.it_interval.tv_sec = t->it_interval / hz;\n        aitv.it_value.tv_sec = t->it_value / hz;\n    }\n    splx(s);\n    u.u_error = copyout ((caddr_t)&aitv, (caddr_t)uap->itv,\n        sizeof (struct itimerval));\n}\n\nvoid\nsetitimer()\n{\n    register struct a {\n        u_int   which;\n        struct  itimerval *itv, *oitv;\n    } *uap = (struct a *)u.u_arg;\n    struct itimerval aitv;\n    register struct itimerval *aitvp;\n    int s;\n\n    if (uap->which > ITIMER_PROF) {\n        u.u_error = EINVAL;\n        return;\n    }\n    aitvp = uap->itv;\n    if (uap->oitv) {\n        uap->itv = uap->oitv;\n        getitimer();\n    }\n    if (aitvp == 0)\n        return;\n    u.u_error = copyin((caddr_t)aitvp, (caddr_t)&aitv,\n        sizeof (struct itimerval));\n    if (u.u_error)\n        return;\n    s = splclock();\n    if (uap->which == ITIMER_REAL) {\n        register struct proc *p = u.u_procp;\n\n        p->p_realtimer.it_value = aitv.it_value.tv_sec;\n        if (aitv.it_value.tv_usec)\n            ++p->p_realtimer.it_value;\n        p->p_realtimer.it_interval = aitv.it_interval.tv_sec;\n        if (aitv.it_interval.tv_usec)\n            ++p->p_realtimer.it_interval;\n    } else {\n        register struct k_itimerval *t = &u.u_timer[uap->which - 1];\n\n        t->it_value = aitv.it_value.tv_sec * hz;\n        if (aitv.it_value.tv_usec)\n            t->it_value += hz;\n        t->it_interval = aitv.it_interval.tv_sec * hz;\n        if (aitv.it_interval.tv_usec)\n            t->it_interval += hz;\n    }\n    splx(s);\n}\n\n/*\n * Check that a proposed value to load into the .it_value or\n * .it_interval part of an interval timer is acceptable, and\n * fix it to have at least minimal value (i.e. if it is less\n * than the resolution of the clock, round it up.)\n */\nint\nitimerfix(tv)\n    struct timeval *tv;\n{\n    if (tv->tv_sec < 0 || tv->tv_sec > 100000000L ||\n        tv->tv_usec < 0 || tv->tv_usec >= 1000000L)\n        return (EINVAL);\n    if (tv->tv_sec == 0 && tv->tv_usec != 0 && tv->tv_usec < (1000/hz))\n        tv->tv_usec = 1000/hz;\n    return (0);\n}\n\n#ifdef NOT_CURRENTLY_IN_USE\n/*\n * Decrement an interval timer by a specified number\n * of microseconds, which must be less than a second,\n * i.e. < 1000000.  If the timer expires, then reload\n * it.  In this case, carry over (usec - old value) to\n * reducint the value reloaded into the timer so that\n * the timer does not drift.  This routine assumes\n * that it is called in a context where the timers\n * on which it is operating cannot change in value.\n */\nitimerdecr(itp, usec)\n    register struct itimerval *itp;\n    int usec;\n{\n\n    if (itp->it_value.tv_usec < usec) {\n        if (itp->it_value.tv_sec == 0) {\n            /* expired, and already in next interval */\n            usec -= itp->it_value.tv_usec;\n            goto expire;\n        }\n        itp->it_value.tv_usec += 1000000L;\n        itp->it_value.tv_sec--;\n    }\n    itp->it_value.tv_usec -= usec;\n    usec = 0;\n    if (timerisset(&itp->it_value))\n        return (1);\n    /* expired, exactly at end of interval */\nexpire:\n    if (timerisset(&itp->it_interval)) {\n        itp->it_value = itp->it_interval;\n        itp->it_value.tv_usec -= usec;\n        if (itp->it_value.tv_usec < 0) {\n            itp->it_value.tv_usec += 1000000L;\n            itp->it_value.tv_sec--;\n        }\n    } else\n        itp->it_value.tv_usec = 0;      /* sec is already 0 */\n    return (0);\n}\n#endif /* NOT_CURRENTLY_IN_USE */\n\nstatic void\ntvfix(t1)\n    struct timeval *t1;\n{\n    if (t1->tv_usec < 0) {\n        t1->tv_sec--;\n        t1->tv_usec += 1000000L;\n    }\n    if (t1->tv_usec >= 1000000L) {\n        t1->tv_sec++;\n        t1->tv_usec -= 1000000L;\n    }\n}\n\n/*\n * Add and subtract routines for timevals.\n * N.B.: subtract routine doesn't deal with\n * results which are before the beginning,\n * it just gets very confused in this case.\n * Caveat emptor.\n */\nvoid\ntimevaladd(t1, t2)\n    struct timeval *t1, *t2;\n{\n    t1->tv_sec += t2->tv_sec;\n    t1->tv_usec += t2->tv_usec;\n    tvfix(t1);\n}\n\n#ifdef NOT_CURRENTLY_IN_USE\nvoid\ntimevalsub(t1, t2)\n    struct timeval *t1, *t2;\n{\n    t1->tv_sec -= t2->tv_sec;\n    t1->tv_usec -= t2->tv_usec;\n    tvfix(t1);\n}\n#endif\n"
  },
  {
    "path": "sys/kern/subr_log.c",
    "content": "/*\n * Copyright (c) 1982, 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * logioctl() had the wrong number of arguments.  Argh!  Apparently this\n * driver was overlooked when 'dev' was added to ioctl entry points.\n *\n * logclose() returned garbage.  this went unnoticed because most programs\n * don't check status when doing a close.\n\n * Add support for multiple log devices.  Minor device 0 is the traditional\n * kernel logger (/dev/klog), minor device 1 is reserved for the future device\n * error logging daemon.\n */\n\n#define NLOG    1\nint nlog = 1;\n\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/ioctl.h>\n#include <sys/msgbuf.h>\n#include <sys/file.h>\n#include <sys/inode.h>\n#include <sys/errno.h>\n#include <sys/uio.h>\n#include <sys/map.h>\n#include <sys/systm.h>\n#include <sys/conf.h>\n\nconst struct devspec logdevs[] = {\n    { 0, \"klog\" },\n    { 0, 0 }\n};\n\n#define LOG_RDPRI   (PZERO + 1)\n\n#define LOG_OPEN    0x01\n#define LOG_ASYNC   0x04\n#define LOG_RDWAIT  0x08\n\nstruct  msgbuf  msgbuf[NLOG];\n\nstatic struct logsoftc {\n    int     sc_state;       /* see above for possibilities */\n    struct  proc *sc_selp;  /* process waiting on select call */\n    int     sc_pgid;        /* process/group for async I/O */\n    int     sc_overrun;     /* full buffer count */\n} logsoftc[NLOG];\n\n/*ARGSUSED*/\nint\nlogopen(dev, mode, unused)\n    dev_t dev;\n    int mode;\n{\n    register int    unit = minor(dev);\n\n    if (unit >= NLOG)\n        return(ENODEV);\n    if (logisopen(unit))\n        return(EBUSY);\n    if (msgbuf[unit].msg_bufc == 0)             /* no buffer allocated */\n        return(ENOMEM);\n    logsoftc[unit].sc_state |= LOG_OPEN;\n    logsoftc[unit].sc_pgid = u.u_procp->p_pid;  /* signal process only */\n    logsoftc[unit].sc_overrun = 0;\n    return(0);\n}\n\n/*ARGSUSED*/\nint\nlogclose(dev, flag, unused)\n    dev_t   dev;\n    int flag;\n{\n    register int unit = minor(dev);\n\n    logsoftc[unit].sc_state = 0;\n    return(0);\n}\n\n/*\n * This is a helper function to keep knowledge of this driver's data\n * structures away from the rest of the kernel.\n */\nint\nlogisopen(unit)\n    int unit;\n{\n    if (logsoftc[unit].sc_state & LOG_OPEN)\n        return(1);\n    return(0);\n}\n\n/*ARGSUSED*/\nint\nlogread(dev, uio, flag)\n    dev_t dev;\n    struct uio *uio;\n    int flag;\n{\n    register int l;\n    register struct logsoftc *lp;\n    register struct msgbuf *mp;\n    int s, error = 0;\n    char    buf [128];\n\n    l = minor(dev);\n    lp = &logsoftc[l];\n    mp = &msgbuf[l];\n    s = splhigh();\n    while (mp->msg_bufr == mp->msg_bufx) {\n        if (flag & IO_NDELAY) {\n            splx(s);\n            return(EWOULDBLOCK);\n        }\n        lp->sc_state |= LOG_RDWAIT;\n        sleep((caddr_t)mp, LOG_RDPRI);\n    }\n    lp->sc_state &= ~LOG_RDWAIT;\n\n    while (uio->uio_resid) {\n        l = mp->msg_bufx - mp->msg_bufr;\n        /*\n         * If the reader and writer are equal then we have caught up and there\n         * is nothing more to transfer.\n         */\n        if (l == 0)\n            break;\n        /*\n         * If the write pointer is behind the reader then only consider as\n         * available for now the bytes from the read pointer thru the end of\n         * the buffer.\n         */\n        if (l < 0) {\n            l = MSG_BSIZE - mp->msg_bufr;\n            /*\n             * If the reader is exactly at the end of the buffer it is\n             * time to wrap it around to the beginning and recalculate the\n             * amount of data to transfer.\n             */\n            if (l == 0) {\n                mp->msg_bufr = 0;\n                continue;\n            }\n        }\n        l = MIN (l, uio->uio_resid);\n        l = MIN (l, sizeof buf);\n        bcopy (&mp->msg_bufc[mp->msg_bufr], buf, l);\n        error = uiomove (buf, l, uio);\n        if (error)\n            break;\n        mp->msg_bufr += l;\n    }\n    splx(s);\n    return(error);\n}\n\n/*ARGSUSED*/\nint\nlogselect(dev, rw)\n    dev_t dev;\n    int rw;\n{\n    register int s = splhigh();\n    int unit = minor(dev);\n\n    switch (rw) {\n    case FREAD:\n        if (msgbuf[unit].msg_bufr != msgbuf[unit].msg_bufx) {\n            splx(s);\n            return(1);\n        }\n        logsoftc[unit].sc_selp = u.u_procp;\n        break;\n    }\n    splx(s);\n    return(0);\n}\n\nvoid\nlogwakeup(unit)\n    int unit;\n{\n    register struct proc *p;\n    register struct logsoftc *lp;\n    register struct msgbuf *mp;\n\n    if (! logisopen(unit))\n        return;\n    lp = &logsoftc[unit];\n    mp = &msgbuf[unit];\n    if (lp->sc_selp) {\n        selwakeup(lp->sc_selp, (long) 0);\n        lp->sc_selp = 0;\n    }\n    if (lp->sc_state & LOG_ASYNC && (mp->msg_bufx != mp->msg_bufr)) {\n        if (lp->sc_pgid < 0)\n            gsignal(-lp->sc_pgid, SIGIO);\n        else if ((p = pfind(lp->sc_pgid)))\n            psignal(p, SIGIO);\n    }\n    if (lp->sc_state & LOG_RDWAIT) {\n        wakeup((caddr_t)mp);\n        lp->sc_state &= ~LOG_RDWAIT;\n    }\n}\n\n/*ARGSUSED*/\nint\nlogioctl(dev, com, data, flag)\n    dev_t   dev;\n    u_int   com;\n    caddr_t data;\n    int flag;\n{\n    long l;\n    register int s;\n    int unit;\n    register struct logsoftc *lp;\n    register struct msgbuf *mp;\n\n    unit = minor(dev);\n    lp = &logsoftc[unit];\n    mp = &msgbuf[unit];\n\n    switch (com) {\n    case FIONREAD:\n        s = splhigh();\n        l = mp->msg_bufx - mp->msg_bufr;\n        splx(s);\n        if (l < 0)\n            l += MSG_BSIZE;\n        *(off_t *)data = l;\n        break;\n    case FIONBIO:\n        break;\n    case FIOASYNC:\n        if (*(int *)data)\n            lp->sc_state |= LOG_ASYNC;\n        else\n            lp->sc_state &= ~LOG_ASYNC;\n        break;\n    case TIOCSPGRP:\n        lp->sc_pgid = *(int *)data;\n        break;\n    case TIOCGPGRP:\n        *(int *)data = lp->sc_pgid;\n        break;\n    default:\n        return(-1);\n    }\n    return(0);\n}\n\n/*\n * This is inefficient for single character writes.  Alas, changing this\n * to be buffered would affect the networking code's use of printf.\n*/\nint\nlogwrt (buf, len, log)\n    char    *buf;\n    int len;\n    int log;\n{\n    register struct msgbuf *mp = &msgbuf[log];\n    struct  logsoftc *lp = &logsoftc[log];\n    register int    infront;\n    int  s, n, writer, err = 0;\n\n    if (mp->msg_magic != MSG_MAGIC || (len > MSG_BSIZE))\n        return(-1);\n    /*\n     * Hate to do this but since this can be called from anywhere in the kernel\n     * we have to hold off any interrupt service routines so they don't change\n     * things.  This looks like a lot of code but it isn't really.\n     */\n    s = splhigh();\n    while (len) {\nagain:      infront = MSG_BSIZE - mp->msg_bufx;\n        if (infront <= 0) {\n            mp->msg_bufx = 0;\n            infront = MSG_BSIZE - mp->msg_bufr;\n        }\n        n = mp->msg_bufr - mp->msg_bufx;\n        if (n < 0)      /* bufr < bufx */\n            writer = (MSG_BSIZE - mp->msg_bufx) + mp->msg_bufr;\n        else if (n == 0)\n            writer = MSG_BSIZE;\n        else {\n            writer = n;\n            infront = n;\n        }\n        if (len > writer) {\n            /*\n             * won't fit.  the total number of bytes to be written is\n             * greater than the number available.  the buffer is full.\n             * throw away the old data and keep the current data by resetting\n             * the 'writer' pointer to the current 'reader' position.  Bump the\n             * overrun counter in case anyone wants to look at it for debugging.\n             */\n            lp->sc_overrun++;\n            mp->msg_bufx = mp->msg_bufr;\n            goto again;\n        }\n        if (infront > len)\n            infront = len;\n        bcopy(buf, &mp->msg_bufc[mp->msg_bufx], infront);\n        mp->msg_bufx += infront;\n        len -= infront;\n        buf += infront;\n    }\n    splx(s);\n    return(err);\n}\n\n/*\n * Initialize the log driver.  Called from the system startup code (machdep2.c).\n * All buffers are the same (MSG_BSIZE) size.\n */\nint\nloginit()\n{\n    register struct msgbuf *mp;\n\n    for (mp = &msgbuf[0]; mp < &msgbuf[NLOG]; mp++) {\n        mp->msg_magic = MSG_MAGIC;\n        mp->msg_bufx = mp->msg_bufr = 0;\n    }\n    return(0);\n}\n"
  },
  {
    "path": "sys/kern/subr_prf.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/buf.h>\n#include <sys/msgbuf.h>\n#include <sys/conf.h>\n#include <sys/ioctl.h>\n#include <sys/tty.h>\n#include <sys/reboot.h>\n#include <sys/systm.h>\n#include <sys/syslog.h>\n\n#define TOCONS  0x1\n#define TOTTY   0x2\n#define TOLOG   0x4\n\n/*\n * In case console is off,\n * panicstr contains argument to last\n * call to panic.\n */\nchar    *panicstr;\n\n/*\n * Print a character on console or users terminal.\n * If destination is console then the last MSGBUFS characters\n * are saved in msgbuf for inspection later.\n */\nstatic void\nputchar (c, flags, tp)\n    int c, flags;\n    register struct tty *tp;\n{\n    if (flags & TOTTY) {\n        register int s = spltty();\n\n        if (tp && (tp->t_state & (TS_CARR_ON | TS_ISOPEN)) ==\n            (TS_CARR_ON | TS_ISOPEN)) {\n            if (c == '\\n')\n                (void) ttyoutput('\\r', tp);\n            (void) ttyoutput(c, tp);\n            ttstart(tp);\n        }\n        splx(s);\n    }\n#ifdef LOG_ENABLED\n    if ((flags & TOLOG) && c != '\\0' && c != '\\r' && c != 0177) {\n        char sym = c;\n        logwrt (&sym, 1, logMSG);\n    }\n#endif\n    if ((flags & TOCONS) && c != '\\0')\n        cnputc(c);\n}\n\nstatic unsigned\nmkhex (unsigned ch)\n{\n    ch &= 15;\n    if (ch > 9)\n        return ch + 'a' - 10;\n    return ch + '0';\n}\n\n/*\n * Put a NUL-terminated ASCII number (base <= 16) in a buffer in reverse\n * order; return an optional length and a pointer to the last character\n * written in the buffer (i.e., the first character of the string).\n * The buffer pointed to by `nbuf' must have length >= MAXNBUF.\n */\nstatic char *\nksprintn (char *nbuf, unsigned long ul, int base, int width, int *lenp)\n{\n    char *p;\n\n    p = nbuf;\n    *p = 0;\n    for (;;) {\n        *++p = mkhex (ul % base);\n        ul /= base;\n        if (--width > 0)\n            continue;\n        if (! ul)\n            break;\n    }\n    if (lenp)\n        *lenp = p - nbuf;\n    return (p);\n}\n\nvoid puts(char *s, int flags, struct tty *ttyp)\n{\n    while(*s)\n    putchar(*(s++), flags, ttyp);\n}\n\n/*\n * Scaled down version of printf(3).\n * Two additional formats: %b anf %D.\n * Based on FreeBSD sources.\n * Heavily rewritten by Serge Vakulenko.\n *\n * The format %b is supported to decode error registers.\n * Its usage is:\n *\n *  printf(\"reg=%b\\n\", regval, \"<base><arg>*\");\n *\n * where <base> is the output base expressed as a control character, e.g.\n * \\10 gives octal; \\20 gives hex.  Each arg is a sequence of characters,\n * the first of which gives the bit number to be inspected (origin 1), and\n * the next characters (up to a control character, i.e. a character <= 32),\n * give the name of the register.  Thus:\n *\n *  kvprintf(\"reg=%b\\n\", 3, \"\\10\\2BITTWO\\1BITONE\\n\");\n *\n * would produce output:\n *\n *  reg=3<BITTWO,BITONE>\n *\n * The format %D -- Hexdump, takes a pointer. Sharp flag - use `:' as\n * a separator, instead of a space. For example:\n *\n *  (\"%6D\", ptr)       -> XX XX XX XX XX XX\n *  (\"%#*D\", len, ptr) -> XX:XX:XX:XX ...\n */\n\n#define PUTC(C) putchar(C,flags,ttyp)\n\n#define HION \"\\e[1m\"\n#define HIOFF \"\\e[0m\"\nstatic void\nprf (fmt, ap, flags, ttyp)\n    register char *fmt;\n    register u_int *ap;\n    int flags;\n    struct tty *ttyp;\n{\n#define va_arg(ap,type) *(type*) (void*) (ap++)\n\n    char *q, nbuf [sizeof(long) * 8 + 1];\n    const char *s;\n    int c, padding, base, lflag, ladjust, sharpflag, neg, dot, size;\n    int n, width, dwidth, uppercase, extrazeros, sign;\n    unsigned long ul;\n\n#ifdef KERNEL_HIGHLIGHT\n    puts(HION, flags, ttyp);\n#endif\n\n    if (! fmt)\n        fmt = \"(null)\\n\";\n\n    for (;;) {\n        while ((c = *fmt++) != '%') {\n            if (! c) {\n#ifdef KERNEL_HIGHLIGHT\n                puts(HIOFF, flags, ttyp);\n#endif\n                return;\n            }\n            PUTC (c);\n        }\n        padding = ' ';\n        width = 0; extrazeros = 0;\n        lflag = 0; ladjust = 0; sharpflag = 0; neg = 0;\n        sign = 0; dot = 0; uppercase = 0; dwidth = -1;\nreswitch:\n        c = *fmt++;\n        switch (c) {\n        case '.':\n            dot = 1;\n            padding = ' ';\n            dwidth = 0;\n            goto reswitch;\n\n        case '#':\n            sharpflag = 1;\n            goto reswitch;\n\n        case '+':\n            sign = -1;\n            goto reswitch;\n\n        case '-':\n            ladjust = 1;\n            goto reswitch;\n\n        case '%':\n            PUTC (c);\n            break;\n\n        case '*':\n            if (! dot) {\n                width = va_arg (ap, int);\n                if (width < 0) {\n                    ladjust = !ladjust;\n                    width = -width;\n                }\n            } else {\n                dwidth = va_arg (ap, int);\n            }\n            goto reswitch;\n\n        case '0':\n            if (! dot) {\n                padding = '0';\n                goto reswitch;\n            }\n        case '1': case '2': case '3': case '4':\n        case '5': case '6': case '7': case '8': case '9':\n            for (n=0; ; ++fmt) {\n                n = n * 10 + c - '0';\n                c = *fmt;\n                if (c < '0' || c > '9')\n                    break;\n            }\n            if (dot)\n                dwidth = n;\n            else\n                width = n;\n            goto reswitch;\n\n        case 'b':\n            ul = va_arg (ap, int);\n            s = va_arg (ap, const char*);\n            q = ksprintn (nbuf, ul, *s++, -1, 0);\n            while (*q)\n                PUTC (*q--);\n\n            if (! ul)\n                break;\n            size = 0;\n            while (*s) {\n                n = *s++;\n                if ((char) (ul >> (n-1)) & 1) {\n                    PUTC (size ? ',' : '<');\n                    for (; (n = *s) > ' '; ++s)\n                        PUTC (n);\n                    size = 1;\n                } else {\n                    while (*s > ' ')\n                        ++s;\n                }\n            }\n            if (size)\n                PUTC ('>');\n            break;\n\n        case 'c':\n            if (! ladjust && width > 0) {\n                while (width--)\n                    PUTC (' ');\n            }\n\n            PUTC (va_arg (ap, int));\n\n            if (ladjust && width > 0) {\n                while (width--)\n                    PUTC (' ');\n            }\n            break;\n\n        case 'D':\n            s = va_arg (ap, const char*);\n            if (! width)\n                width = 16;\n            if (sharpflag)\n                padding = ':';\n            while (width--) {\n                c = *s++;\n                PUTC (mkhex (c >> 4));\n                PUTC (mkhex (c));\n                if (width)\n                    PUTC (padding);\n            }\n            break;\n\n        case 'd':\n            ul = lflag ? va_arg (ap, long) : va_arg (ap, int);\n            if (! sign) sign = 1;\n            base = 10;\n            goto number;\n\n        case 'l':\n            lflag = 1;\n            goto reswitch;\n\n        case 'o':\n            ul = lflag ? va_arg (ap, unsigned long) :\n                va_arg (ap, unsigned int);\n            base = 8;\n            goto nosign;\n\n        case 'p':\n            ul = (size_t) va_arg (ap, void*);\n            if (! ul) {\n                s = \"(nil)\";\n                goto const_string;\n            }\n            base = 16;\n            sharpflag = (width == 0);\n            goto nosign;\n\n        case 'n':\n            ul = lflag ? va_arg (ap, unsigned long) :\n                sign ? (unsigned long) va_arg (ap, int) :\n                va_arg (ap, unsigned int);\n            base = 10;\n            goto number;\n\n        case 's':\n            s = va_arg (ap, char*);\n            if (! s)\n                s = (const char*) \"(null)\";\nconst_string:\n            if (! dot)\n                n = strlen (s);\n            else\n                for (n=0; n<dwidth && s[n]; n++)\n                    continue;\n\n            width -= n;\n\n            if (! ladjust && width > 0) {\n                while (width--)\n                    PUTC (' ');\n            }\n            while (n--)\n                PUTC (*s++);\n            if (ladjust && width > 0) {\n                while (width--)\n                    PUTC (' ');\n            }\n            break;\n\n        case 'u':\n            ul = lflag ? va_arg (ap, unsigned long) :\n                va_arg (ap, unsigned int);\n            base = 10;\n            goto nosign;\n\n        case 'x':\n        case 'X':\n            ul = lflag ? va_arg (ap, unsigned long) :\n                va_arg (ap, unsigned int);\n            base = 16;\n            uppercase = (c == 'X');\n            goto nosign;\n        case 'z':\n        case 'Z':\n            ul = lflag ? va_arg (ap, unsigned long) :\n                sign ? (unsigned long) va_arg (ap, int) :\n                va_arg (ap, unsigned int);\n            base = 16;\n            uppercase = (c == 'Z');\n            goto number;\nnosign:\n            sign = 0;\nnumber:\n            if (sign && ((long) ul != 0L)) {\n                if ((long) ul < 0L) {\n                    neg = '-';\n                    ul = -(long) ul;\n                } else if (sign < 0)\n                    neg = '+';\n            }\n            if (dwidth >= (int) sizeof(nbuf)) {\n                extrazeros = dwidth - sizeof(nbuf) + 1;\n                dwidth = sizeof(nbuf) - 1;\n            }\n            s = ksprintn (nbuf, ul, base, dwidth, &size);\n            if (sharpflag && ul != 0) {\n                if (base == 8)\n                    size++;\n                else if (base == 16)\n                    size += 2;\n            }\n            if (neg)\n                size++;\n\n            if (! ladjust && width && padding == ' ' &&\n                (width -= size) > 0) {\n                do {\n                    PUTC (' ');\n                } while (--width > 0);\n            }\n\n            if (neg)\n                PUTC (neg);\n\n            if (sharpflag && ul != 0) {\n                if (base == 8) {\n                    PUTC ('0');\n                } else if (base == 16) {\n                    PUTC ('0');\n                    PUTC (uppercase ? 'X' : 'x');\n                }\n            }\n\n            if (extrazeros) {\n                do {\n                    PUTC ('0');\n                } while (--extrazeros > 0);\n            }\n\n            if (! ladjust && width && (width -= size) > 0) {\n                do {\n                    PUTC (padding);\n                } while (--width > 0);\n            }\n\n            for (; *s; --s) {\n                if (uppercase && *s>='a' && *s<='z') {\n                    PUTC (*s + 'A' - 'a');\n                } else {\n                    PUTC (*s);\n                }\n            }\n\n            if (ladjust && width && (width -= size) > 0) {\n                do {\n                    PUTC (' ');\n                } while (--width > 0);\n            }\n            break;\n        default:\n            PUTC ('%');\n            if (lflag)\n                PUTC ('l');\n            PUTC (c);\n            break;\n        }\n    }\n#ifdef KERNEL_HIGHLIGHT\n    puts(HIOFF,flags,ttyp);\n#endif\n}\n\nstatic void\nlogpri (level)\n    int level;\n{\n    putchar ('<', TOLOG, (struct tty*) 0);\n    prf (\"%u\", &level, TOLOG, (struct tty*) 0);\n    putchar ('>', TOLOG, (struct tty*) 0);\n}\n\n/*\n * Scaled down version of C Library printf.\n * Used to print diagnostic information directly on console tty.\n * Since it is not interrupt driven, all system activities are\n * suspended.  Printf should not be used for chit-chat.\n *\n * One additional format: %b is supported to decode error registers.\n * Usage is:\n *  printf(\"reg=%b\\n\", regval, \"<base><arg>*\");\n * Where <base> is the output base expressed as a control character,\n * e.g. \\10 gives octal; \\20 gives hex.  Each arg is a sequence of\n * characters, the first of which gives the bit number to be inspected\n * (origin 1), and the next characters (up to a control character, i.e.\n * a character <= 32), give the name of the register.  Thus\n *  printf(\"reg=%b\\n\", 3, \"\\10\\2BITTWO\\1BITONE\\n\");\n * would produce output:\n *  reg=3<BITTWO,BITONE>\n */\nvoid\nprintf(char *fmt, ...)\n{\n    prf(fmt, &fmt + 1, TOCONS | TOLOG, (struct tty *)0);\n}\n\n/*\n * Microchip MPLABX C32 compiler generates calls to _printf_s()\n * and other strange names.\n */\n#ifdef __MPLABX__\nvoid _printf_s(char *fmt, ...)\n    __attribute__((alias (\"printf\")));\nvoid _printf_cdnopuxX(char *fmt, ...)\n    __attribute__((alias (\"printf\")));\nvoid _printf_cdnopsuxX(char *fmt, ...)\n    __attribute__((alias (\"printf\")));\n#endif\n\n/*\n * Uprintf prints to the current user's terminal,\n * guarantees not to sleep (so could be called by interrupt routines;\n * but prints on the tty of the current process)\n * and does no watermark checking - (so no verbose messages).\n * NOTE: with current kernel mapping scheme, the user structure is\n * not guaranteed to be accessible at interrupt level (see seg.h);\n * a savemap/restormap would be needed here or in putchar if uprintf\n * was to be used at interrupt time.\n */\nvoid\nuprintf (char *fmt, ...)\n{\n    register struct tty *tp;\n\n    tp = u.u_ttyp;\n    if (tp == NULL)\n        return;\n\n    if (ttycheckoutq (tp, 1))\n        prf (fmt, &fmt+1, TOTTY, tp);\n}\n\n/*\n * tprintf prints on the specified terminal (console if none)\n * and logs the message.  It is designed for error messages from\n * single-open devices, and may be called from interrupt level\n * (does not sleep).\n */\nvoid\ntprintf (register struct tty *tp, char *fmt, ...)\n{\n    int flags = TOTTY | TOLOG;\n\n    logpri (LOG_INFO);\n    if (tp == (struct tty*) NULL)\n        tp = &cnttys[0];\n    if (ttycheckoutq (tp, 0) == 0)\n        flags = TOLOG;\n    prf (fmt, &fmt + 1, flags, tp);\n#ifdef LOG_ENABLED\n    logwakeup (logMSG);\n#endif\n}\n\n/*\n * Log writes to the log buffer,\n * and guarantees not to sleep (so can be called by interrupt routines).\n * If there is no process reading the log yet, it writes to the console also.\n */\n/*VARARGS2*/\nvoid\nlog (int level, char *fmt, ...)\n{\n    register int s = splhigh();\n\n    logpri(level);\n    prf(fmt, &fmt + 1, TOLOG, (struct tty *)0);\n    splx(s);\n#ifdef LOG_ENABLED\n    if (! logisopen(logMSG))\n#endif\n        prf(fmt, &fmt + 1, TOCONS, (struct tty *)0);\n#ifdef LOG_ENABLED\n    logwakeup(logMSG);\n#endif\n}\n\n/*\n * Panic is called on unresolvable fatal errors.\n * It prints \"panic: mesg\", and then reboots.\n * If we are called twice, then we avoid trying to\n * sync the disks as this often leads to recursive panics.\n */\nvoid\npanic(s)\n    char *s;\n{\n    int bootopt = RB_HALT | RB_DUMP;\n\n    if (panicstr) {\n        bootopt |= RB_NOSYNC;\n    } else {\n        panicstr = s;\n    }\n    printf (\"panic: %s\\n\", s);\n    boot (rootdev, bootopt);\n}\n"
  },
  {
    "path": "sys/kern/subr_rmap.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/map.h>\n#include <sys/vm.h>\n\n/*\n * Resource map handling routines.\n *\n * A resource map is an array of structures each of which describes a\n * segment of the address space of an available resource.  The segments\n * are described by their base address and length, and sorted in address\n * order.  Each resource map has a fixed maximum number of segments\n * allowed.  Resources are allocated by taking part or all of one of the\n * segments of the map.\n *\n * Returning of resources will require another segment if the returned\n * resources are not adjacent in the address space to an existing segment.\n * If the return of a segment would require a slot which is not available,\n * then one of the resource map segments is discarded after a warning is\n * printed.\n *\n * Returning of resources may also cause the map to collapse by coalescing\n * two existing segments and the returned space into a single segment.  In\n * this case the resource map is made smaller by copying together to fill\n * the resultant gap.\n *\n * N.B.: the current implementation uses a dense array and does not admit\n * the value ``0'' as a legal address or size, since that is used as a\n * delimiter.\n */\n\n/*\n * Allocate 'size' units from the given map.  Return the base of the\n * allocated space.  In a map, the addresses are increasing and the\n * list is terminated by a 0 size.\n *\n * Algorithm is first-fit.\n */\nsize_t\nmalloc (mp, size)\n    struct map *mp;\n    register size_t size;\n{\n    register struct mapent *bp, *ep;\n    size_t addr;\n\n    if (! size)\n        panic (\"malloc: size = 0\");\n    /*\n     * Search for a piece of the resource map which has enough\n     * free space to accomodate the request.\n     */\n    for (bp = mp->m_map; bp->m_size; ++bp)\n        if (bp->m_size >= size) {\n            /*\n             * Allocate from the map.  If we allocated the entire\n             * piece, move the rest of the map to the left.\n             */\n            addr = bp->m_addr;\n            bp->m_size -= size;\n            if (bp->m_size)\n                bp->m_addr += size;\n            else for (ep = bp;; ++ep) {\n                *ep = *++bp;\n                if (!bp->m_size)\n                    break;\n            }\n            return(addr);\n        }\n    /* no entries big enough */\n    return 0;\n}\n\n/*\n * Free the previously allocated size units at addr into the specified\n * map.  Sort addr into map and combine on one or both ends if possible.\n */\nvoid\nmfree (mp, size, addr)\n    struct map *mp;\n    size_t size;\n    register size_t addr;\n{\n    register struct mapent *bp, *ep;\n    struct mapent *start;\n\n    if (! size)\n        return;\n    /* the address must not be 0, or the protocol has broken down. */\n    if (! addr)\n        panic (\"mfree: addr = 0\");\n\n    /*\n     * locate the piece of the map which starts after the\n     * returned space (or the end of the map).\n     */\n    bp = mp->m_map;\n    /* printf (\"mfree (size=%u, addr=%u) m_map = %08x\\n\", size, addr, bp); */\n\n    while (bp->m_size && bp->m_addr <= addr) {\n        /*printf (\"skip m_map[%d]: m_addr %u <= addr %u\\n\", bp - mp->m_map, bp->m_addr, addr);*/\n        ++bp;\n    }\n\n    /* if there is a piece on the left abutting us, combine with it. */\n    ep = bp - 1;\n    if (bp != mp->m_map && ep->m_addr + ep->m_size >= addr) {\n#ifdef DIAGNOSTIC\n        /* any overlap is an internal error */\n        if (ep->m_addr + ep->m_size > addr)\n            panic(\"mfree overlap #1\");\n#endif\n        /* add into piece on the left by increasing its size. */\n        ep->m_size += size;\n\n        /*\n         * if the combined piece abuts the piece on the right now,\n         * compress it in also, by shifting the remaining pieces\n         * of the map over.\n         */\n        if (bp->m_size && addr + size >= bp->m_addr) {\n#ifdef DIAGNOSTIC\n            if (addr + size > bp->m_addr)\n                panic(\"mfree overlap #2\");\n#endif\n            ep->m_size += bp->m_size;\n            do {\n                *++ep = *++bp;\n            } while (bp->m_size);\n        }\n        return;\n    }\n\n    /* if doesn't abut on the left, check for abutting on the right. */\n    if (bp->m_size && addr + size >= bp->m_addr) {\n#ifdef DIAGNOSTIC\n        if (addr + size > bp->m_addr)\n            panic(\"mfree overlap #3\");\n#endif\n        bp->m_addr = addr;\n        bp->m_size += size;\n        return;\n    }\n\n    /* doesn't abut.  Make a new entry and check for map overflow. */\n    for (start = bp; bp->m_size; ++bp);\n    if (++bp > mp->m_limit)\n        /*\n         * too many segments; if this happens, the correct fix\n         * is to make the map bigger; you can't afford to lose\n         * chunks of the map.  If you need to implement recovery,\n         * use the above \"for\" loop to find the smallest entry\n         * and toss it.\n         */\n        printf(\"%s: overflow, lost %u clicks at 0%o\\n\",\n            mp->m_name, size, addr);\n    else {\n        for (ep = bp - 1; ep >= start; *bp-- = *ep--);\n        start->m_addr = addr;\n        start->m_size = size;\n    }\n}\n\n/*\n * Allocate resources for the three segments of a process (data, stack\n * and u.), attempting to minimize the cost of failure part-way through.\n * Since the segments are located successively, it is best for the sizes\n * to be in decreasing order; generally, data, stack, then u. will be\n * best.  Returns NULL on failure, address of u. on success.\n */\nsize_t\nmalloc3 (mp, d_size, s_size, u_size, a)\n    struct map *mp;\n    size_t d_size, s_size, u_size;\n    size_t a[3];\n{\n    register struct mapent *bp, *remap;\n    register int next;\n    struct mapent *madd[3];\n    size_t sizes[3];\n    int found;\n\n    sizes[0] = d_size;\n    sizes[1] = s_size;\n    sizes[2] = u_size;\n    /*\n     * note, this has to work for d_size and s_size of zero,\n     * since init() comes in that way.\n     */\n    madd[0] = madd[1] = madd[2] = remap = NULL;\n    for (found = 0, bp = mp->m_map; bp->m_size; ++bp)\n        for (next = 0; next < 3; ++next)\n            if (!madd[next] && sizes[next] <= bp->m_size) {\n                madd[next] = bp;\n                bp->m_size -= sizes[next];\n                if (!bp->m_size && !remap)\n                    remap = bp;\n                if (++found == 3)\n                    goto resolve;\n            }\n\n    /* couldn't get it all; restore the old sizes, try again */\n    for (next = 0; next < 3; ++next)\n        if (madd[next])\n            madd[next]->m_size += sizes[next];\n    return 0;\n\nresolve:\n    /* got it all, update the addresses. */\n    for (next = 0; next < 3; ++next) {\n        bp = madd[next];\n        a[next] = bp->m_addr;\n        bp->m_addr += sizes[next];\n    }\n\n    /* remove any entries of size 0; addr of 0 terminates */\n    if (remap) {\n        for (bp = remap + 1;; ++bp) {\n            if (bp->m_size || !bp->m_addr) {\n                *remap++ = *bp;\n                if (!bp->m_addr)\n                    break;\n            }\n        }\n    }\n    return(a[2]);\n}\n"
  },
  {
    "path": "sys/kern/sys_generic.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/signalvar.h>\n#include <sys/inode.h>\n#include <sys/file.h>\n#include <sys/ioctl.h>\n#include <sys/conf.h>\n#include <sys/uio.h>\n#include <sys/kernel.h>\n#include <sys/systm.h>\n\nint selwait;\n\nstatic void\nrwuio (uio)\n    register struct uio *uio;\n{\n    struct a {\n        int     fdes;\n    };\n    register struct file *fp;\n    register struct iovec *iov;\n    u_int i, count;\n    off_t   total;\n\n    GETF(fp, ((struct a *)u.u_arg)->fdes);\n    if ((fp->f_flag & (uio->uio_rw == UIO_READ ? FREAD : FWRITE)) == 0) {\n        u.u_error = EBADF;\n        return;\n    }\n    total = 0;\n    uio->uio_resid = 0;\n    for (iov = uio->uio_iov, i = 0; i < uio->uio_iovcnt; i++, iov++)\n        total += iov->iov_len;\n\n    uio->uio_resid = total;\n    if (uio->uio_resid != total) {      /* check wraparound */\n        u.u_error = EINVAL;\n        return;\n    }\n    count = uio->uio_resid;\n    if (setjmp (&u.u_qsave)) {\n        /*\n         * The ONLY way we can get here is via the longjump in sleep.  Thus signals\n         * have been checked and u_error set accordingly.  If no bytes have been\n         * transferred then all that needs to be done now is 'return'; the system\n         * call will either be restarted or reported as interrupted.  If bytes have\n         * been transferred then we need to calculate the number of bytes transferred.\n         */\n        if (uio->uio_resid == count)\n            return;\n        u.u_error = 0;\n    } else\n        u.u_error = (*Fops[fp->f_type]->fo_rw) (fp, uio);\n\n    u.u_rval = count - uio->uio_resid;\n}\n\n/*\n * Read system call.\n */\nvoid\nread()\n{\n    register struct a {\n        int     fdes;\n        char    *cbuf;\n        unsigned count;\n    } *uap = (struct a *)u.u_arg;\n    struct uio auio;\n    struct iovec aiov;\n\n    aiov.iov_base = (caddr_t)uap->cbuf;\n    aiov.iov_len = uap->count;\n    auio.uio_iov = &aiov;\n    auio.uio_iovcnt = 1;\n    auio.uio_rw = UIO_READ;\n    rwuio (&auio);\n}\n\nvoid\nreadv()\n{\n    register struct a {\n        int     fdes;\n        struct  iovec *iovp;\n        unsigned iovcnt;\n    } *uap = (struct a *)u.u_arg;\n    struct uio auio;\n    struct iovec aiov[16];      /* XXX */\n\n    if (uap->iovcnt > sizeof(aiov)/sizeof(aiov[0])) {\n        u.u_error = EINVAL;\n        return;\n    }\n    auio.uio_iov = aiov;\n    auio.uio_iovcnt = uap->iovcnt;\n    auio.uio_rw = UIO_READ;\n    u.u_error = copyin ((caddr_t)uap->iovp, (caddr_t)aiov,\n        uap->iovcnt * sizeof (struct iovec));\n    if (u.u_error)\n        return;\n    rwuio (&auio);\n}\n\n/*\n * Write system call\n */\nvoid\nwrite()\n{\n    register struct a {\n        int     fdes;\n        char    *cbuf;\n        unsigned count;\n    } *uap = (struct a *)u.u_arg;\n    struct uio auio;\n    struct iovec aiov;\n\n    auio.uio_iov = &aiov;\n    auio.uio_iovcnt = 1;\n    auio.uio_rw = UIO_WRITE;\n    aiov.iov_base = uap->cbuf;\n    aiov.iov_len = uap->count;\n    rwuio (&auio);\n}\n\nvoid\nwritev()\n{\n    register struct a {\n        int     fdes;\n        struct  iovec *iovp;\n        unsigned iovcnt;\n    } *uap = (struct a *)u.u_arg;\n    struct uio auio;\n    struct iovec aiov[16];      /* XXX */\n\n    if (uap->iovcnt > sizeof(aiov)/sizeof(aiov[0])) {\n        u.u_error = EINVAL;\n        return;\n    }\n    auio.uio_iov = aiov;\n    auio.uio_iovcnt = uap->iovcnt;\n    auio.uio_rw = UIO_WRITE;\n    u.u_error = copyin ((caddr_t)uap->iovp, (caddr_t)aiov,\n        uap->iovcnt * sizeof (struct iovec));\n    if (u.u_error)\n        return;\n    rwuio (&auio);\n}\n\n/*\n * Ioctl system call\n */\nvoid\nioctl()\n{\n    register struct file *fp;\n    register struct a {\n        int     fdes;\n        long    cmd;\n        caddr_t cmarg;\n    } *uap;\n    u_int com;\n\n    uap = (struct a *)u.u_arg;\n    fp = getf(uap->fdes);\n    if (! fp)\n        return;\n    if (! (fp->f_flag & (FREAD | FWRITE))) {\n        u.u_error = EBADF;\n        return;\n    }\n    com = (u_int) uap->cmd;\n    if (com & (IOC_IN | IOC_OUT)) {\n        /* Check user address. */\n        u_int nbytes = (com & ~(IOC_INOUT | IOC_VOID)) >> 16;\n        if (baduaddr (uap->cmarg) ||\n            baduaddr (uap->cmarg + nbytes - 1)) {\n            u.u_error = EFAULT;\n            return;\n        }\n    }\n\n    switch (com) {\n    case FIOCLEX:\n        u.u_pofile[uap->fdes] |= UF_EXCLOSE;\n        return;\n    case FIONCLEX:\n        u.u_pofile[uap->fdes] &= ~UF_EXCLOSE;\n        return;\n    case FIONBIO:\n        u.u_error = fset (fp, FNONBLOCK, *(int*) uap->cmarg);\n        return;\n    case FIOASYNC:\n        u.u_error = fset (fp, FASYNC, *(int*) uap->cmarg);\n        return;\n    case FIOSETOWN:\n        u.u_error = fsetown (fp, *(int*) uap->cmarg);\n        return;\n    case FIOGETOWN:\n        u.u_error = fgetown (fp, (int*) uap->cmarg);\n        return;\n    }\n    u.u_error = (*Fops[fp->f_type]->fo_ioctl) (fp, com, uap->cmarg);\n}\n\nint nselcoll;\n\nstruct pselect_args {\n    int         nd;\n    fd_set      *in;\n    fd_set      *ou;\n    fd_set      *ex;\n    struct  timespec *ts;\n    sigset_t    *maskp;\n};\n\nint\nselscan(ibits, obits, nfd, retval)\n    fd_set *ibits, *obits;\n    int nfd, *retval;\n{\n    register int i, j, flag = 0;\n    fd_mask bits;\n    struct file *fp;\n    int which, n = 0;\n\n    for (which = 0; which < 3; which++) {\n        switch (which) {\n        case 0:\n            flag = FREAD; break;\n        case 1:\n            flag = FWRITE; break;\n        case 2:\n            flag = 0; break;\n        }\n        for (i = 0; i < nfd; i += NFDBITS) {\n            bits = ibits[which].fds_bits[i/NFDBITS];\n            while ((j = ffs(bits)) && i + --j < nfd) {\n                bits &= ~(1L << j);\n                fp = u.u_ofile[i + j];\n                if (fp == NULL)\n                    return(EBADF);\n                if ((*Fops[fp->f_type]->fo_select) (fp, flag)) {\n                    FD_SET(i + j, &obits[which]);\n                    n++;\n                }\n            }\n        }\n    }\n    *retval = n;\n    return(0);\n}\n\n/*\n * Select helper function common to both select() and pselect()\n */\nstatic int\nselect1(uap, is_pselect)\n    register struct pselect_args *uap;\n    int is_pselect;\n{\n    fd_set ibits[3], obits[3];\n    struct timeval atv;\n    sigset_t sigmsk;\n    unsigned int timo = 0;\n    register int error, ni;\n    int ncoll, s;\n\n    bzero((caddr_t)ibits, sizeof(ibits));\n    bzero((caddr_t)obits, sizeof(obits));\n    if (uap->nd > NOFILE)\n        uap->nd = NOFILE;   /* forgiving, if slightly wrong */\n    ni = howmany(uap->nd, NFDBITS);\n\n#define getbits(name, x) \\\n    if (uap->name) { \\\n        error = copyin((caddr_t)uap->name, (caddr_t)&ibits[x], \\\n            (unsigned)(ni * sizeof(fd_mask))); \\\n        if (error) \\\n            goto done; \\\n    }\n    getbits(in, 0);\n    getbits(ou, 1);\n    getbits(ex, 2);\n#undef  getbits\n\n    if (uap->maskp) {\n        error = copyin ((caddr_t) uap->maskp, (caddr_t) &sigmsk, sizeof(sigmsk));\n        sigmsk &= ~sigcantmask;\n        if (error)\n            goto done;\n    }\n    if (uap->ts) {\n        error = copyin ((caddr_t) uap->ts, (caddr_t) &atv, sizeof (atv));\n        if (error)\n            goto done;\n        /*\n         * nanoseconds ('struct timespec') on a PDP-11 are stupid since a 50 or 60 hz\n         * clock is all we have.   Keeping the names and logic made porting easier\n         * though.\n         */\n        if (is_pselect) {\n            struct  timespec *ts = (struct timespec *)&atv;\n\n            if (ts->tv_sec == 0 && ts->tv_nsec < 1000)\n                atv.tv_usec = 1;\n            else\n                atv.tv_usec = ts->tv_nsec / 1000;\n        }\n        if (itimerfix(&atv)) {\n            error = EINVAL;\n            goto done;\n        }\n        s = splhigh();\n        time.tv_usec = lbolt * usechz;\n        timevaladd(&atv, &time);\n        splx(s);\n    }\nretry:\n    ncoll = nselcoll;\n    u.u_procp->p_flag |= P_SELECT;\n    error = selscan(ibits, obits, uap->nd, &u.u_rval);\n    if (error || u.u_rval)\n        goto done;\n    s = splhigh();\n    if (uap->ts) {\n        /* this should be timercmp(&time, &atv, >=) */\n        if ((time.tv_sec > atv.tv_sec || (time.tv_sec == atv.tv_sec\n            && lbolt * usechz >= atv.tv_usec))) {\n            splx(s);\n            goto done;\n        }\n        timo = hzto(&atv);\n        if (timo == 0)\n            timo = 1;\n    }\n    if ((u.u_procp->p_flag & P_SELECT) == 0 || nselcoll != ncoll) {\n        u.u_procp->p_flag &= ~P_SELECT;\n        splx(s);\n        goto retry;\n    }\n    u.u_procp->p_flag &= ~P_SELECT;\n    /*\n     * If doing a pselect() need to set a temporary mask while in tsleep.\n     * Returning from pselect after catching a signal the old mask has to be\n     * restored.  Save it here and set the appropriate flag.\n     */\n    if (uap->maskp) {\n        u.u_oldmask = u.u_procp->p_sigmask;\n        u.u_psflags |= SAS_OLDMASK;\n        u.u_procp->p_sigmask = sigmsk;\n    }\n    error = tsleep ((caddr_t) &selwait, PSOCK | PCATCH, timo);\n    if (uap->maskp)\n        u.u_procp->p_sigmask = u.u_oldmask;\n    splx(s);\n    if (error == 0)\n        goto retry;\ndone:\n    u.u_procp->p_flag &= ~P_SELECT;\n    /* select is not restarted after signals... */\n    if (error == ERESTART)\n        error = EINTR;\n    if (error == EWOULDBLOCK)\n        error = 0;\n#define putbits(name, x) \\\n    if (uap->name && \\\n        (error2 = copyout ((caddr_t) &obits[x], (caddr_t) uap->name, ni*sizeof(fd_mask)))) \\\n            error = error2;\n\n    if (error == 0) {\n        int error2;\n\n        putbits(in, 0);\n        putbits(ou, 1);\n        putbits(ex, 2);\n#undef putbits\n    }\n    return(error);\n}\n\n/*\n * Select system call.\n */\nvoid\nselect()\n{\n    struct uap {\n        int     nd;\n        fd_set  *in, *ou, *ex;\n        struct  timeval *tv;\n    } *uap = (struct uap *)u.u_arg;\n    register struct pselect_args *pselargs = (struct pselect_args *)uap;\n\n    /*\n     * Fake the 6th parameter of pselect.  See the comment below about the\n     * number of parameters!\n    */\n    pselargs->maskp = 0;\n    u.u_error = select1 (pselargs, 0);\n}\n\n/*\n * pselect (posix select)\n *\n * N.B.  There is only room for 6 arguments - see user.h - so pselect() is\n *       at the maximum!  See user.h\n */\nvoid\npselect()\n{\n    register struct pselect_args *uap = (struct pselect_args *)u.u_arg;\n\n    u.u_error = select1(uap, 1);\n}\n\n/*ARGSUSED*/\nint\nseltrue(dev, flag)\n    dev_t dev;\n    int flag;\n{\n    return (1);\n}\n\nvoid\nselwakeup (p, coll)\n    register struct proc *p;\n    long coll;\n{\n    if (coll) {\n        nselcoll++;\n        wakeup ((caddr_t)&selwait);\n    }\n    if (p) {\n        register int s = splhigh();\n        if (p->p_wchan == (caddr_t)&selwait) {\n            if (p->p_stat == SSLEEP)\n                setrun(p);\n            else\n                unsleep(p);\n        } else if (p->p_flag & P_SELECT)\n            p->p_flag &= ~P_SELECT;\n        splx(s);\n    }\n}\n\nint\nsorw(fp, uio)\n    register struct file *fp;\n    register struct uio *uio;\n{\n#ifdef  INET\n    if (uio->uio_rw == UIO_READ)\n        return(SORECEIVE((struct socket *)fp->f_socket, 0, uio, 0, 0));\n    return(SOSEND((struct socket *)fp->f_socket, 0, uio, 0, 0));\n#else\n    return (EOPNOTSUPP);\n#endif\n}\n\nint\nsoctl(fp, com, data)\n    struct file *fp;\n    u_int   com;\n    char    *data;\n{\n#ifdef  INET\n    return (SOO_IOCTL(fp, com, data));\n#else\n    return (EOPNOTSUPP);\n#endif\n}\n\nint\nsosel(fp, flag)\n    struct file *fp;\n    int     flag;\n{\n#ifdef  INET\n    return (SOO_SELECT(fp, flag));\n#else\n    return (EOPNOTSUPP);\n#endif\n}\n\nint\nsocls(fp)\n    register struct file *fp;\n{\n    register int error = 0;\n\n#ifdef  INET\n    if (fp->f_data)\n        error = SOCLOSE((struct socket *)fp->f_data);\n    fp->f_data = 0;\n#else\n    error = EOPNOTSUPP;\n#endif\n    return(error);\n}\n\n/*\n * this is consolidated here rather than being scattered all over the\n * place.  the socketops table has to be in kernel space, but since\n * networking might not be defined an appropriate error has to be set\n */\nconst struct fileops socketops = {\n    sorw, soctl, sosel, socls\n};\n\nconst struct fileops *const Fops[] = {\n    NULL, &inodeops, &socketops, &pipeops\n};\n\n/*\n * Routine placed in illegal entries in the bdevsw and cdevsw tables.\n */\nvoid\nnostrategy (bp)\n    struct buf *bp;\n{\n    /* Empty. */\n}\n\n#ifndef INET\n/*\n * socket(2) and socketpair(2) if networking not available.\n */\nvoid\nnonet()\n{\n    u.u_error = EPROTONOSUPPORT;\n}\n#endif\n"
  },
  {
    "path": "sys/kern/sys_inode.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/signalvar.h>\n#include <sys/inode.h>\n#include <sys/buf.h>\n#include <sys/fs.h>\n#include <sys/file.h>\n#include <sys/stat.h>\n#include <sys/mount.h>\n#include <sys/conf.h>\n#include <sys/uio.h>\n#include <sys/ioctl.h>\n#include <sys/tty.h>\n#include <sys/kernel.h>\n#include <sys/systm.h>\n#include <sys/syslog.h>\n\ndaddr_t rablock;        /* block to be read ahead */\n\nint\nino_rw(fp, uio)\n    struct file *fp;\n    register struct uio *uio;\n{\n    register struct inode *ip = (struct inode *)fp->f_data;\n    u_int count, error;\n    int ioflag;\n\n    if ((ip->i_mode&IFMT) != IFCHR)\n        ILOCK(ip);\n    uio->uio_offset = fp->f_offset;\n    count = uio->uio_resid;\n    if (uio->uio_rw == UIO_READ) {\n        error = rwip(ip, uio, fp->f_flag & FNONBLOCK ? IO_NDELAY : 0);\n        fp->f_offset += (count - uio->uio_resid);\n    } else {\n        ioflag = 0;\n        if ((ip->i_mode&IFMT) == IFREG && (fp->f_flag & FAPPEND))\n            ioflag |= IO_APPEND;\n        if (fp->f_flag & FNONBLOCK)\n            ioflag |= IO_NDELAY;\n        if (fp->f_flag & FFSYNC ||\n            (ip->i_fs->fs_flags & MNT_SYNCHRONOUS))\n            ioflag |= IO_SYNC;\n        error = rwip(ip, uio, ioflag);\n        if (ioflag & IO_APPEND)\n            fp->f_offset = uio->uio_offset;\n        else\n            fp->f_offset += (count - uio->uio_resid);\n    }\n    if ((ip->i_mode&IFMT) != IFCHR)\n        IUNLOCK(ip);\n    return (error);\n}\n\nint\nino_ioctl(fp, com, data)\n    register struct file *fp;\n    register u_int com;\n    caddr_t data;\n{\n    register struct inode *ip = ((struct inode *)fp->f_data);\n    dev_t dev;\n\n    switch (ip->i_mode & IFMT) {\n\n    case IFREG:\n    case IFDIR:\n        if (com == FIONREAD) {\n            if (fp->f_type==DTYPE_PIPE && !(fp->f_flag&FREAD))\n                *(off_t *)data = 0;\n            else\n                *(off_t *)data = ip->i_size - fp->f_offset;\n            return (0);\n        }\n        if (com == FIONBIO || com == FIOASYNC)  /* XXX */\n            return (0);         /* XXX */\n        /* fall into ... */\n\n    default:\n        return (ENOTTY);\n\n    case IFCHR:\n        dev = ip->i_rdev;\n        u.u_rval = 0;\n        if (setjmp(&u.u_qsave)) {\n            /*\n             * The ONLY way we can get here is via the longjump in sleep.  Signals have\n             * been checked for and u_error set accordingly.  All that remains to do\n             * is 'return'.\n             */\n            return(u.u_error);\n        }\n        return((*cdevsw[major(dev)].d_ioctl)(dev,com,data,fp->f_flag));\n    case IFBLK:\n        dev = ip->i_rdev;\n        u.u_rval = 0;\n        if (setjmp(&u.u_qsave)) {\n            /*\n             * The ONLY way we can get here is via the longjump in sleep.  Signals have\n             * been checked for and u_error set accordingly.  All that remains to do\n             * is 'return'.\n             */\n            return(u.u_error);\n        }\n        return((*bdevsw[major(dev)].d_ioctl)(dev,com,data,fp->f_flag));\n    }\n}\n\nint\nino_select(fp, which)\n    struct file *fp;\n    int which;\n{\n    register struct inode *ip = (struct inode *)fp->f_data;\n    register dev_t dev;\n\n    switch (ip->i_mode & IFMT) {\n\n    default:\n        return (1);     /* XXX */\n\n    case IFCHR:\n        dev = ip->i_rdev;\n        return (*cdevsw[major(dev)].d_select)(dev, which);\n    }\n}\n\nconst struct fileops inodeops = {\n    ino_rw, ino_ioctl, ino_select, vn_closefile\n};\n\nint\nrdwri (rw, ip, base, len, offset, ioflg, aresid)\n    enum uio_rw rw;\n    struct inode *ip;\n    caddr_t base;\n    int len;\n    off_t offset;\n    int ioflg;\n    register int *aresid;\n{\n    struct uio auio;\n    struct iovec aiov;\n    register int error;\n\n    auio.uio_iov = &aiov;\n    auio.uio_iovcnt = 1;\n    aiov.iov_base = base;\n    aiov.iov_len = len;\n    auio.uio_rw = rw;\n    auio.uio_resid = len;\n    auio.uio_offset = offset;\n    error = rwip(ip, &auio, ioflg);\n    if (aresid)\n        *aresid = auio.uio_resid;\n    else\n        if (auio.uio_resid)\n            error = EIO;\n    return (error);\n}\n\nint\nrwip (ip, uio, ioflag)\n    register struct inode *ip;\n    register struct uio *uio;\n    int ioflag;\n{\n    dev_t dev = (dev_t)ip->i_rdev;\n    register struct buf *bp;\n    off_t osize;\n    daddr_t lbn, bn;\n    int n, on, type, resid;\n    int error = 0;\n    int flags;\n\n    //if (uio->uio_offset < 0)\n        //return (EINVAL);\n    type = ip->i_mode & IFMT;\n    /*\n     * The write case below checks that i/o is done synchronously to directories\n     * and that i/o to append only files takes place at the end of file.\n     * We do not panic on non-sync directory i/o - the sync bit is forced on.\n     */\n    if (uio->uio_rw == UIO_READ) {\n        if (! (ip->i_fs->fs_flags & MNT_NOATIME))\n            ip->i_flag |= IACC;\n    } else {\n        switch (type) {\n        case IFREG:\n            if (ioflag & IO_APPEND)\n                uio->uio_offset = ip->i_size;\n            if (ip->i_flags & APPEND && uio->uio_offset != ip->i_size)\n                return(EPERM);\n            break;\n        case IFDIR:\n            if  ((ioflag & IO_SYNC) == 0)\n                ioflag |= IO_SYNC;\n            break;\n        case IFLNK:\n        case IFBLK:\n        case IFCHR:\n            break;\n        default:\n            return (EFTYPE);\n        }\n    }\n\n    /*\n     * The IO_SYNC flag is turned off here if the 'async' mount flag is on.\n     * Otherwise directory I/O (which is done by the kernel) would still\n     * synchronous (because the kernel carefully passes IO_SYNC for all directory\n     * I/O) even if the fs was mounted with \"-o async\".\n     *\n     * A side effect of this is that if the system administrator mounts a filesystem\n     * 'async' then the O_FSYNC flag to open() is ignored.\n     *\n     * This behaviour should probably be selectable via \"sysctl fs.async.dirs\" and\n     * \"fs.async.ofsync\".  A project for a rainy day.\n     */\n    if (type == IFREG || (type == IFDIR && (ip->i_fs->fs_flags & MNT_ASYNC)))\n        ioflag &= ~IO_SYNC;\n\n    if (type == IFCHR) {\n        if (uio->uio_rw == UIO_READ) {\n            if (! (ip->i_fs->fs_flags & MNT_NOATIME))\n                ip->i_flag |= IACC;\n            error = (*cdevsw[major(dev)].d_read)(dev, uio, ioflag);\n        } else {\n            ip->i_flag |= IUPD|ICHG;\n            error = (*cdevsw[major(dev)].d_write)(dev, uio, ioflag);\n        }\n        return (error);\n    }\n    if (uio->uio_resid == 0)\n        return (0);\n    if (uio->uio_rw == UIO_WRITE && type == IFREG &&\n        uio->uio_offset + uio->uio_resid >\n          u.u_rlimit[RLIMIT_FSIZE].rlim_cur) {\n        psignal(u.u_procp, SIGXFSZ);\n        return (EFBIG);\n    }\n    if (type != IFBLK)\n        dev = ip->i_dev;\n    resid = uio->uio_resid;\n    osize = ip->i_size;\n\n    flags = ioflag & IO_SYNC ? B_SYNC : 0;\n\n    do {\n        lbn = lblkno(uio->uio_offset);\n        on = blkoff(uio->uio_offset);\n        n = MIN((u_int)(DEV_BSIZE - on), uio->uio_resid);\n        if (type != IFBLK) {\n            if (uio->uio_rw == UIO_READ) {\n                off_t diff = ip->i_size - uio->uio_offset;\n                if (diff <= 0)\n                    return (0);\n                if (diff < n)\n                    n = diff;\n                bn = bmap(ip, lbn, B_READ, flags);\n            } else\n                bn = bmap(ip,lbn,B_WRITE,\n                       n == DEV_BSIZE ? flags : flags|B_CLRBUF);\n            if (u.u_error || (uio->uio_rw == UIO_WRITE && (long)bn < 0))\n                return (u.u_error);\n            if (uio->uio_rw == UIO_WRITE && uio->uio_offset + n > ip->i_size &&\n               (type == IFDIR || type == IFREG || type == IFLNK))\n                ip->i_size = uio->uio_offset + n;\n        } else {\n            bn = lbn;\n            rablock = bn + 1;\n        }\n        if (uio->uio_rw == UIO_READ) {\n            if ((long)bn < 0) {\n                bp = geteblk();\n                bzero (bp->b_addr, MAXBSIZE);\n            } else if (ip->i_lastr + 1 == lbn)\n                bp = breada (dev, bn, rablock);\n            else\n                bp = bread (dev, bn);\n            ip->i_lastr = lbn;\n        } else {\n            if (n == DEV_BSIZE)\n                bp = getblk (dev, bn);\n            else\n                bp = bread (dev, bn);\n            /*\n             * 4.3 didn't do this, but 2.10 did.  not sure why.\n             * something about tape drivers don't clear buffers on end-of-tape\n             * any longer (clrbuf can't be called from interrupt).\n             */\n            if (bp->b_resid == DEV_BSIZE) {\n                bp->b_resid = 0;\n                bzero (bp->b_addr, MAXBSIZE);\n            }\n        }\n        n = MIN(n, DEV_BSIZE - bp->b_resid);\n        if (bp->b_flags & B_ERROR) {\n            error = EIO;\n            brelse(bp);\n            break;\n        }\n        u.u_error = uiomove (bp->b_addr + on, n, uio);\n        if (uio->uio_rw == UIO_READ) {\n            if (n + on == DEV_BSIZE || uio->uio_offset == ip->i_size) {\n                bp->b_flags |= B_AGE;\n                if (ip->i_flag & IPIPE)\n                    bp->b_flags &= ~B_DELWRI;\n            }\n            brelse(bp);\n        } else {\n            if (ioflag & IO_SYNC)\n                bwrite(bp);\n            /*\n             * The check below interacts _very_ badly with virtual memory tmp files\n             * such as those used by 'ld'.   These files tend to be small and repeatedly\n             * rewritten in 1kb chunks.  The check below causes the device driver to be\n             * called (and I/O initiated)  constantly.  Not sure what to do about this yet\n             * but this comment is being placed here as a reminder.\n             */\n            else if (n + on == DEV_BSIZE && !(ip->i_flag & IPIPE)) {\n                bp->b_flags |= B_AGE;\n                bawrite(bp);\n            } else\n                bdwrite(bp);\n            ip->i_flag |= IUPD|ICHG;\n            if (u.u_ruid != 0)\n                ip->i_mode &= ~(ISUID|ISGID);\n        }\n    } while (u.u_error == 0 && uio->uio_resid && n != 0);\n    if (error == 0)             /* XXX */\n        error = u.u_error;      /* XXX */\n    if (error && (uio->uio_rw == UIO_WRITE) && (ioflag & IO_UNIT) &&\n        (type != IFBLK)) {\n        itrunc(ip, osize, ioflag & IO_SYNC);\n        uio->uio_offset -= (resid - uio->uio_resid);\n        uio->uio_resid = resid;\n        /*\n         * Should back out the change to the quota here but that would be a lot\n         * of work for little benefit.  Besides we've already made the assumption\n         * that the entire write would succeed and users can't turn on the IO_UNIT\n         * bit for their writes anyways.\n         */\n    }\n#ifdef whybother\n    if (! error && (ioflag & IO_SYNC))\n        IUPDAT(ip, &time, &time, 1);\n#endif\n    return (error);\n}\n\nint\nino_stat(ip, sb)\n    register struct inode *ip;\n    register struct stat *sb;\n{\n    register struct icommon2 *ic2;\n\n    ic2 = &ip->i_ic2;\n\n    /*\n     * inlined ITIMES which takes advantage of the common times pointer.\n     */\n    if (ip->i_flag & (IUPD|IACC|ICHG)) {\n        ip->i_flag |= IMOD;\n        if (ip->i_flag & IACC)\n            ic2->ic_atime = time.tv_sec;\n        if (ip->i_flag & IUPD)\n            ic2->ic_mtime = time.tv_sec;\n        if (ip->i_flag & ICHG)\n            ic2->ic_ctime = time.tv_sec;\n        ip->i_flag &= ~(IUPD|IACC|ICHG);\n    }\n    sb->st_dev = ip->i_dev;\n    sb->st_ino = ip->i_number;\n    sb->st_mode = ip->i_mode;\n    sb->st_nlink = ip->i_nlink;\n    sb->st_uid = ip->i_uid;\n    sb->st_gid = ip->i_gid;\n    sb->st_rdev = (dev_t)ip->i_rdev;\n    sb->st_size = ip->i_size;\n    sb->st_atime = ic2->ic_atime;\n    sb->st_mtime = ic2->ic_mtime;\n    sb->st_ctime = ic2->ic_ctime;\n    sb->st_blksize = MAXBSIZE;\n    /*\n     * blocks are too tough to do; it's not worth the effort.\n     */\n    sb->st_blocks = btod (ip->i_size);\n    sb->st_flags = ip->i_flags;\n    return (0);\n}\n\n/*\n * This routine, like its counterpart openi(), calls the device driver for\n * special (IBLK, ICHR) files.  Normal files simply return early (the default\n * case in the switch statement).  Pipes and sockets do NOT come here because\n * they have their own close routines.\n*/\nint\nclosei (ip, flag)\n    register struct inode *ip;\n    int flag;\n{\n    register struct mount *mp;\n    register struct file *fp;\n    int mode, error;\n    dev_t   dev;\n    int (*cfunc)();\n\n    mode = ip->i_mode & IFMT;\n    dev = ip->i_rdev;\n\n    switch (mode) {\n    case IFCHR:\n        cfunc = cdevsw[major(dev)].d_close;\n        break;\n    case IFBLK:\n        /*\n         * We don't want to really close the device if it is mounted\n         */\n        /* MOUNT TABLE SHOULD HOLD INODE */\n        for (mp = mount; mp < &mount[NMOUNT]; mp++)\n            if (mp->m_inodp != NULL && mp->m_dev == dev)\n                return(0);\n        cfunc = bdevsw[major(dev)].d_close;\n        break;\n    default:\n        return(0);\n    }\n    /*\n     * Check that another inode for the same device isn't active.\n     * This is because the same device can be referenced by two\n     * different inodes.\n     */\n    for (fp = file; fp < file+NFILE; fp++) {\n        if (fp->f_type != DTYPE_INODE)\n            continue;\n        if (fp->f_count && (ip = (struct inode *)fp->f_data) &&\n            ip->i_rdev == dev && (ip->i_mode&IFMT) == mode)\n            return(0);\n    }\n    if (mode == IFBLK) {\n        /*\n         * On last close of a block device (that isn't mounted)\n         * we must invalidate any in core blocks, so that\n         * we can, for instance, change floppy disks.\n         */\n        bflush(dev);\n        binval(dev);\n    }\n    /*\n     * NOTE:  none of the device drivers appear to either set u_error OR return\n     *    anything meaningful from their close routines.  It's a good thing\n     *    programs don't bother checking the error status on close() calls.\n     *    Apparently the only time \"errno\" is meaningful after a \"close\" is\n     *    when the process is interrupted.\n     */\n    if (setjmp (&u.u_qsave)) {\n        /*\n         * If device close routine is interrupted,\n         * must return so closef can clean up.\n         */\n        if ((error = u.u_error) == 0)\n            error = EINTR;\n    } else\n        error = (*cfunc)(dev, flag, mode);\n    return (error);\n}\n\n/*\n * Place an advisory lock on an inode.\n * NOTE: callers of this routine must be prepared to deal with the pseudo\n *       error return ERESTART.\n */\nint\nino_lock(fp, cmd)\n    register struct file *fp;\n    int cmd;\n{\n    register int priority = PLOCK;\n    register struct inode *ip = (struct inode *)fp->f_data;\n    int error;\n\n    if ((cmd & LOCK_EX) == 0)\n        priority += 4;\n/*\n * If there's a exclusive lock currently applied to the file then we've\n * gotta wait for the lock with everyone else.\n *\n * NOTE:  We can NOT sleep on i_exlockc because it is on an odd byte boundary\n *    and the low (oddness) bit is reserved for networking/supervisor mode\n *    sleep channels.  Thus we always sleep on i_shlockc and simply check\n *    the proper bits to see if the lock we want is granted.  This may\n *    mean an extra wakeup/sleep event is done once in a while but\n *    everything will work correctly.\n*/\nagain:\n    while (ip->i_flag & IEXLOCK) {\n        /*\n         * If we're holding an exclusive\n         * lock, then release it.\n         */\n        if (fp->f_flag & FEXLOCK) {\n            ino_unlock(fp, FEXLOCK);\n            continue;\n        }\n        if (cmd & LOCK_NB)\n            return (EWOULDBLOCK);\n        ip->i_flag |= ILWAIT;\n        error = tsleep((caddr_t)&ip->i_shlockc, priority | PCATCH, 0);\n        if (error)\n            return(error);\n    }\n    if ((cmd & LOCK_EX) && (ip->i_flag & ISHLOCK)) {\n        /*\n         * Must wait for any shared locks to finish\n         * before we try to apply a exclusive lock.\n         *\n         * If we're holding a shared\n         * lock, then release it.\n         */\n        if (fp->f_flag & FSHLOCK) {\n            ino_unlock(fp, FSHLOCK);\n            goto again;\n        }\n        if (cmd & LOCK_NB)\n            return (EWOULDBLOCK);\n        ip->i_flag |= ILWAIT;\n        error = tsleep((caddr_t)&ip->i_shlockc, PLOCK | PCATCH, 0);\n        if  (error)\n            return(error);\n        goto again;\n    }\n    if (cmd & LOCK_EX) {\n        cmd &= ~LOCK_SH;\n        ip->i_exlockc++;\n        ip->i_flag |= IEXLOCK;\n        fp->f_flag |= FEXLOCK;\n    }\n    if ((cmd & LOCK_SH) && (fp->f_flag & FSHLOCK) == 0) {\n        ip->i_shlockc++;\n        ip->i_flag |= ISHLOCK;\n        fp->f_flag |= FSHLOCK;\n    }\n    return (0);\n}\n\n/*\n * Unlock a file.\n */\nvoid\nino_unlock(fp, kind)\n    register struct file *fp;\n    int kind;\n{\n    register struct inode *ip = (struct inode *)fp->f_data;\n    register int flags;\n\n    kind &= fp->f_flag;\n    if (ip == NULL || kind == 0)\n        return;\n    flags = ip->i_flag;\n    if (kind & FSHLOCK) {\n        if (--ip->i_shlockc == 0) {\n            ip->i_flag &= ~ISHLOCK;\n            if (flags & ILWAIT)\n                wakeup((caddr_t)&ip->i_shlockc);\n        }\n        fp->f_flag &= ~FSHLOCK;\n    }\n    if (kind & FEXLOCK) {\n        if (--ip->i_exlockc == 0) {\n            ip->i_flag &= ~(IEXLOCK|ILWAIT);\n            if (flags & ILWAIT)\n                wakeup((caddr_t)&ip->i_shlockc);\n        }\n        fp->f_flag &= ~FEXLOCK;\n    }\n}\n\n/*\n * Openi called to allow handler of special files to initialize and\n * validate before actual IO.\n */\nint\nopeni (ip, mode)\n    register struct inode *ip;\n    int mode;\n{\n    register dev_t dev = ip->i_rdev;\n    register int maj = major(dev);\n    dev_t bdev;\n    int error;\n\n    switch (ip->i_mode&IFMT) {\n\n    case IFCHR:\n        if (ip->i_fs->fs_flags & MNT_NODEV)\n            return(ENXIO);\n        if ((u_int)maj >= nchrdev)\n            return (ENXIO);\n        if (mode & FWRITE) {\n            /*\n             * When running in very secure mode, do not allow\n             * opens for writing of any disk character devices.\n             */\n            if (securelevel >= 2 && isdisk(dev, IFCHR))\n                return(EPERM);\n            /*\n             * When running in secure mode, do not allow opens\n             * for writing of /dev/mem, /dev/kmem, or character\n             * devices whose corresponding block devices are\n             * currently mounted.\n             */\n            if (securelevel >= 1) {\n                if ((bdev = chrtoblk(dev)) != NODEV &&\n                    (error = ufs_mountedon(bdev)))\n                        return(error);\n                if (iskmemdev(dev))\n                    return(EPERM);\n            }\n        }\n        return ((*cdevsw[maj].d_open)(dev, mode, S_IFCHR));\n\n    case IFBLK:\n        if (ip->i_fs->fs_flags & MNT_NODEV)\n            return(ENXIO);\n        if ((u_int)maj >= nblkdev)\n            return (ENXIO);\n        /*\n         * When running in very secure mode, do not allow\n         * opens for writing of any disk block devices.\n         */\n        if (securelevel >= 2 && (mode & FWRITE) && isdisk(dev, IFBLK))\n            return(EPERM);\n        /*\n         * Do not allow opens of block devices that are\n         * currently mounted.\n         *\n         * 2.11BSD must relax this restriction to allow 'fsck' to\n         * open the root filesystem (which is always mounted) during\n         * a reboot.  Once in secure or very secure mode the\n         * above restriction is fully effective.  On the otherhand\n         * fsck should 1) use the raw device, 2) not do sync calls...\n         */\n        if (securelevel > 0 && (error = ufs_mountedon(dev)))\n            return(error);\n        return ((*bdevsw[maj].d_open)(dev, mode, S_IFBLK));\n    }\n    return (0);\n}\n\nstatic void\nforceclose(dev)\n    register dev_t dev;\n{\n    register struct file *fp;\n    register struct inode *ip;\n\n    for (fp = file; fp < file+NFILE; fp++) {\n        if (fp->f_count == 0)\n            continue;\n        if (fp->f_type != DTYPE_INODE)\n            continue;\n        ip = (struct inode *)fp->f_data;\n        if (ip == 0)\n            continue;\n        if ((ip->i_mode & IFMT) != IFCHR)\n            continue;\n        if (ip->i_rdev != dev)\n            continue;\n        fp->f_flag &= ~(FREAD | FWRITE);\n    }\n}\n\n/*\n * Revoke access the current tty by all processes.\n * Used only by the super-user in init\n * to give ``clean'' terminals at login.\n */\nvoid\nvhangup()\n{\n    if (! suser())\n        return;\n    if (u.u_ttyp == NULL)\n        return;\n    forceclose(u.u_ttyd);\n    if ((u.u_ttyp->t_state) & TS_ISOPEN)\n        gsignal(u.u_ttyp->t_pgrp, SIGHUP);\n}\n"
  },
  {
    "path": "sys/kern/sys_pipe.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/inode.h>\n#include <sys/file.h>\n#include <sys/fs.h>\n#include <sys/mount.h>\n#include <sys/uio.h>\n#include <machine/frame.h>\n\nint\nreadp (fp, uio, flag)\n    register struct file *fp;\n    register struct uio *uio;\n    int flag;\n{\n    register struct inode *ip;\n    int error;\n\n    ip = (struct inode *)fp->f_data;\nloop:\n    /* Very conservative locking. */\n    ILOCK(ip);\n\n    /* If nothing in the pipe, wait (unless FNONBLOCK is set). */\n    if (ip->i_size == 0) {\n        /*\n         * If there are not both reader and writer active,\n         * return without satisfying read.\n         */\n        IUNLOCK(ip);\n        if (ip->i_count != 2)\n            return (0);\n        if (fp->f_flag & FNONBLOCK)\n            return (EWOULDBLOCK);\n        ip->i_mode |= IREAD;\n        sleep((caddr_t)ip+4, PPIPE);\n        goto loop;\n    }\n\n    uio->uio_offset = fp->f_offset;\n    error = rwip(ip, uio, flag);\n    fp->f_offset = uio->uio_offset;\n\n    /*\n     * If reader has caught up with writer, reset\n     * offset and size to 0.\n     */\n    if (fp->f_offset == ip->i_size) {\n        fp->f_offset = 0;\n        ip->i_size = 0;\n        if (ip->i_mode & IWRITE) {\n            ip->i_mode &= ~IWRITE;\n            wakeup((caddr_t)ip+2);\n        }\n        if (ip->i_wsel) {\n            selwakeup(ip->i_wsel, (long)(ip->i_flag & IWCOLL));\n            ip->i_wsel = 0;\n            ip->i_flag &= ~IWCOLL;\n        }\n    }\n    IUNLOCK(ip);\n    return (error);\n}\n\nint\nwritep (fp, uio, flag)\n    struct file *fp;\n    register struct uio *uio;\n    int flag;\n{\n    register struct inode *ip;\n    register int c;\n    int error = 0;\n\n    ip = (struct inode *)fp->f_data;\n    c = uio->uio_resid;\n    ILOCK(ip);\n    if ((fp->f_flag & FNONBLOCK) && ip->i_size + c >= MAXPIPSIZ) {\n        error = EWOULDBLOCK;\n        goto done;\n    }\nloop:\n    /* If all done, return. */\n    if (c == 0) {\n        uio->uio_resid = 0;\n        goto done;\n    }\n\n    /*\n     * If there are not both read and write sides of the pipe active,\n     * return error and signal too.\n     */\n    if (ip->i_count != 2) {\n        psignal(u.u_procp, SIGPIPE);\n        error = EPIPE;\ndone:       IUNLOCK(ip);\n        return (error);\n    }\n\n    /*\n     * If the pipe is full, wait for reads to deplete\n     * and truncate it.\n     */\n    if (ip->i_size >= MAXPIPSIZ) {\n        ip->i_mode |= IWRITE;\n        IUNLOCK(ip);\n        sleep((caddr_t)ip+2, PPIPE);\n        ILOCK(ip);\n        goto loop;\n    }\n\n    /*\n     * Write what is possible and loop back.\n     * If writing less than MAXPIPSIZ, it always goes.\n     * One can therefore get a file > MAXPIPSIZ if write\n     * sizes do not divide MAXPIPSIZ.\n     */\n    uio->uio_offset = ip->i_size;\n    uio->uio_resid = MIN((u_int)c, (u_int)MAXPIPSIZ);\n    c -= uio->uio_resid;\n    error = rwip(ip, uio, flag);\n    if (ip->i_mode&IREAD) {\n        ip->i_mode &= ~IREAD;\n        wakeup((caddr_t)ip+4);\n    }\n    if (ip->i_rsel) {\n        selwakeup(ip->i_rsel, (long)(ip->i_flag & IRCOLL));\n        ip->i_rsel = 0;\n        ip->i_flag &= ~IRCOLL;\n    }\n    goto loop;\n}\n\nint\npipe_rw (fp, uio, flag)\n    register struct file *fp;\n    register struct uio *uio;\n    int flag;\n{\n    if (uio->uio_rw == UIO_READ)\n        return (readp(fp, uio, flag));\n    return (writep(fp, uio, flag));\n}\n\nint\npipe_select (fp, which)\n    struct file *fp;\n    int which;\n{\n    register struct inode *ip = (struct inode *)fp->f_data;\n    register struct proc *p;\n    register int retval = 0;\n    extern int selwait;\n\n    ILOCK(ip);\n    if (ip->i_count != 2)\n        retval = 1;\n\n    else switch (which) {\n    case FREAD:\n        if (ip->i_size) {\n            retval = 1;\n            break;\n        }\n        if ((p = ip->i_rsel) && p->p_wchan == (caddr_t)&selwait)\n            ip->i_flag |= IRCOLL;\n        else\n            ip->i_rsel = u.u_procp;\n        break;\n\n    case FWRITE:\n        if (ip->i_size < MAXPIPSIZ) {\n            retval = 1;\n            break;\n        }\n        if ((p = ip->i_wsel) && p->p_wchan == (caddr_t)&selwait)\n            ip->i_flag |= IWCOLL;\n        else\n            ip->i_wsel = u.u_procp;\n        break;\n    }\n    IUNLOCK(ip);\n    return(retval);\n}\n\n/*\n * This routine was pulled out of what used to be called 'ino_close'.  Doing\n * so saved a test of the inode belonging to a pipe.   We know this is a pipe\n * because the inode type was DTYPE_PIPE.  The dispatch in closef() can come\n * directly here instead of the general inode close routine.\n *\n * This routine frees the inode by calling 'iput'.  The inode must be\n * unlocked prior to calling this routine because an 'ilock' is done prior\n * to the select wakeup processing.\n */\nint\npipe_close(fp)\n    struct  file *fp;\n{\n    register struct inode *ip = (struct inode *)fp->f_data;\n\n    ilock(ip);\n#ifdef  DIAGNOSTIC\n    if ((ip->i_flag & IPIPE) == 0)\n        panic(\"pipe_close !IPIPE\");\n#endif\n    if (ip->i_rsel) {\n        selwakeup(ip->i_rsel, (long)(ip->i_flag & IRCOLL));\n        ip->i_rsel = 0;\n        ip->i_flag &= ~IRCOLL;\n    }\n    if (ip->i_wsel) {\n        selwakeup(ip->i_wsel, (long)(ip->i_flag & IWCOLL));\n        ip->i_wsel = 0;\n        ip->i_flag &= ~IWCOLL;\n    }\n    ip->i_mode &= ~(IREAD|IWRITE);\n    wakeup((caddr_t)ip+2);\n    wakeup((caddr_t)ip+4);\n\n    /*\n     * And finally decrement the reference count and (likely) release the inode.\n     */\n    iput(ip);\n    return(0);\n}\n\nconst struct fileops pipeops = {\n    pipe_rw, ino_ioctl, pipe_select, pipe_close\n};\n\n/*\n * The sys-pipe entry.\n * Allocate an inode on the root device.  Allocate 2\n * file structures.  Put it all together with flags.\n */\nvoid\npipe()\n{\n    register struct inode *ip;\n    register struct file *rf, *wf;\n    static struct mount *mp;\n    struct inode itmp;\n    int r;\n\n    /*\n     * if pipedev not yet found, or not available, get it; if can't\n     * find it, use rootdev.  It would be cleaner to wander around\n     * and fix it so that this and getfs() only check m_dev OR\n     * m_inodp, but hopefully the mount table isn't scanned enough\n     * to make it a problem.  Besides, 4.3's is just as bad.  Basic\n     * fantasy is that if m_inodp is set, m_dev *will* be okay.\n     */\n    if (! mp || ! mp->m_inodp || mp->m_dev != pipedev) {\n        for (mp = &mount[0]; ; ++mp) {\n            if (mp == &mount[NMOUNT]) {\n                mp = &mount[0];     /* use root */\n                break;\n            }\n            if (mp->m_inodp == NULL || mp->m_dev != pipedev)\n                continue;\n            break;\n        }\n        if (mp->m_filsys.fs_ronly) {\n            u.u_error = EROFS;\n            return;\n        }\n    }\n    itmp.i_fs = &mp->m_filsys;\n    itmp.i_dev = mp->m_dev;\n    ip = ialloc (&itmp);\n    if (ip == NULL)\n        return;\n    rf = falloc();\n    if (rf == NULL) {\n        iput (ip);\n        return;\n    }\n    r = u.u_rval;\n    wf = falloc();\n    if (wf == NULL) {\n        rf->f_count = 0;\n        u.u_ofile[r] = NULL;\n        iput (ip);\n        return;\n    }\n\n    /* 'Write' end of pipe (for filedes[1]). */\n#ifdef __mips__\n    /* Move a secondary return value to register $v1. */\n    u.u_frame->tf_r3 = u.u_rval;\n#elif __thumb2__ || __thumb__\n    /* Move a secondary return value to register $a2. */\n    u.u_frame->tf_r1 = u.u_rval;\n#else\n#error \"pipe return value for unknown architecture\"\n#endif\n\n    /* 'Read' end of pipe (for filedes[0]). */\n    u.u_rval = r;\n\n    wf->f_flag = FWRITE;\n    rf->f_flag = FREAD;\n    rf->f_type = wf->f_type = DTYPE_PIPE;\n    rf->f_data = wf->f_data = (caddr_t) ip;\n    ip->i_count = 2;\n    ip->i_mode = IFREG;\n    ip->i_flag = IACC | IUPD | ICHG | IPIPE;\n}\n"
  },
  {
    "path": "sys/kern/sys_process.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/inode.h>\n#include <sys/vm.h>\n#include <sys/ptrace.h>\n#include <machine/frame.h>\n\n/*\n * sys-trace system call.\n */\nvoid\nptrace()\n{\n    register struct proc *p;\n    register struct a {\n        int req;\n        int pid;\n        int *addr;\n        int data;\n    } *uap;\n\n    uap = (struct a *)u.u_arg;\n    if (uap->req <= 0) {\n        u.u_procp->p_flag |= P_TRACED;\n        return;\n    }\n    p = pfind(uap->pid);\n    if (p == 0 || p->p_stat != SSTOP || p->p_ppid != u.u_procp->p_pid ||\n        !(p->p_flag & P_TRACED)) {\n        u.u_error = ESRCH;\n        return;\n    }\n    while (ipc.ip_lock)\n        sleep((caddr_t)&ipc, PZERO);\n    ipc.ip_lock = p->p_pid;\n    ipc.ip_data = uap->data;\n    ipc.ip_addr = uap->addr;\n    ipc.ip_req = uap->req;\n    p->p_flag &= ~P_WAITED;\n    setrun(p);\n    while (ipc.ip_req > 0)\n        sleep((caddr_t)&ipc, PZERO);\n    u.u_rval = ipc.ip_data;\n    if (ipc.ip_req < 0)\n        u.u_error = EIO;\n    ipc.ip_lock = 0;\n    wakeup((caddr_t)&ipc);\n}\n\n/*\n * Code that the child process\n * executes to implement the command\n * of the parent process in tracing.\n */\nint\nprocxmt()\n{\n    register int i, *p;\n\n    if (ipc.ip_lock != u.u_procp->p_pid)\n        return(0);\n    u.u_procp->p_slptime = 0;\n    i = ipc.ip_req;\n    ipc.ip_req = 0;\n    wakeup ((caddr_t)&ipc);\n    switch (i) {\n\n    /* read user I */\n    case PT_READ_I:\n\n    /* read user D */\n    case PT_READ_D:\n        if (baduaddr ((caddr_t) ipc.ip_addr))\n            goto error;\n        ipc.ip_data = *(int*) ipc.ip_addr;\n        break;\n\n    /* read u */\n    case PT_READ_U:\n        i = (int) ipc.ip_addr;\n        if (i < 0 || i >= USIZE)\n            goto error;\n        ipc.ip_data = ((unsigned*)&u) [i/sizeof(int)];\n        break;\n\n    /* write user I */\n    case PT_WRITE_I:\n    /* write user D */\n    case PT_WRITE_D:\n        if (baduaddr ((caddr_t) ipc.ip_addr))\n            goto error;\n        *(int*) ipc.ip_addr = ipc.ip_data;\n        break;\n\n    /* write u */\n    case PT_WRITE_U:\n        i = (int)ipc.ip_addr;\n        p = (int*)&u + i/sizeof(int);\n#ifdef __mips__\n        for (i=0; i<FRAME_WORDS; i++)\n            if (p == (int *)&u.u_frame[i]) /* XXX FRAME */\n                goto ok;\n        goto error;\nok:\n#elif __thumb2__ || __thumb__\n        /* XXX FRAME */\n#else\n#error \"user frame for unknown architecture\"\n#endif\n        *p = ipc.ip_data;\n        break;\n\n    /* set signal and continue */\n    /* one version causes a trace-trap */\n    case PT_STEP:\n        /* Use Status.RP bit to indicate a single-step request. */\n#ifdef __mips__\n        u.u_frame->tf_status |= ST_RP;\n#elif __thumb2__ || __thumb__\n        /* XXX FRAME */\n#else\n#error \"single step process status for unknown architecture\"\n#endif\n        /* FALL THROUGH TO ... */\n    case PT_CONTINUE:\n        if ((int)ipc.ip_addr != 1)\n            u.u_frame->tf_pc = (int)ipc.ip_addr; /* XXX FRAME */\n        if (ipc.ip_data > NSIG)\n            goto error;\n        u.u_procp->p_ptracesig = ipc.ip_data;\n        return(1);\n\n    /* force exit */\n    case PT_KILL:\n        exit(u.u_procp->p_ptracesig);\n        /*NOTREACHED*/\n\n    default:\nerror:\n        ipc.ip_req = -1;\n    }\n    return(0);\n}\n"
  },
  {
    "path": "sys/kern/syscalls.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * System call names.\n */\n#ifndef pdp11\nconst char *const syscallnames[] = {\n    \"indir\",            /*   0 = indir */\n    \"exit\",             /*   1 = exit */\n    \"fork\",             /*   2 = fork */\n    \"read\",             /*   3 = read */\n    \"write\",            /*   4 = write */\n    \"open\",             /*   5 = open */\n    \"close\",            /*   6 = close */\n    \"wait4\",            /*   7 = wait4 */\n    \"#8\",               /*   8 = (old creat) */\n    \"link\",             /*   9 = link */\n    \"unlink\",           /*  10 = unlink */\n    \"execv\",            /*  11 = execv */\n    \"chdir\",            /*  12 = chdir */\n    \"fchdir\",           /*  13 = fchdir */\n    \"mknod\",            /*  14 = mknod */\n    \"chmod\",            /*  15 = chmod */\n    \"chown\",            /*  16 = chown; now 3 args */\n    \"chflags\",          /*  17 = chflags */\n    \"fchflags\",         /*  18 = fchflags */\n    \"lseek\",            /*  19 = lseek */\n    \"getpid\",           /*  20 = getpid */\n    \"mount\",            /*  21 = mount */\n    \"umount\",           /*  22 = umount */\n    \"__sysctl\",         /*  23 = __sysctl */\n    \"getuid\",           /*  24 = getuid */\n    \"geteuid\",          /*  25 = geteuid */\n    \"ptrace\",           /*  26 = ptrace */\n    \"getppid\",          /*  27 = getppid */\n    \"statfs\",           /*  28 = statfs */\n    \"fstatfs\",          /*  29 = fstatfs */\n    \"getfsstat\",        /*  30 = getfsstat */\n    \"sigaction\",        /*  31 = sigaction */\n    \"sigprocmask\",      /*  32 = sigprocmask */\n    \"access\",           /*  33 = access */\n    \"sigpending\",       /*  34 = sigpending */\n    \"sigaltstack\",      /*  35 = sigaltstack */\n    \"sync\",             /*  36 = sync */\n    \"kill\",             /*  37 = kill */\n    \"stat\",             /*  38 = stat */\n    \"getlogin\",         /*  39 = getlogin */\n    \"lstat\",            /*  40 = lstat */\n    \"dup\",              /*  41 = dup */\n    \"pipe\",             /*  42 = pipe */\n    \"setlogin\",         /*  43 = setlogin */\n    \"profil\",           /*  44 = profil */\n    \"setuid\",           /*  45 = setuid */\n    \"seteuid\",          /*  46 = seteuid */\n    \"getgid\",           /*  47 = getgid */\n    \"getegid\",          /*  48 = getegid */\n    \"setgid\",           /*  49 = setgid */\n    \"setegid\",          /*  50 = setegid */\n    \"kmemdev\",          /*  51 = kmemdev  */\n    \"phys\",             /*  52 = (2.9) set phys addr */\n    \"lock\",             /*  53 = (2.9) lock in core */\n    \"ioctl\",            /*  54 = ioctl */\n    \"reboot\",           /*  55 = reboot */\n    \"sigwait\",          /*  56 = sigwait */\n    \"symlink\",          /*  57 = symlink */\n    \"readlink\",         /*  58 = readlink */\n    \"execve\",           /*  59 = execve */\n    \"umask\",            /*  60 = umask */\n    \"chroot\",           /*  61 = chroot */\n    \"fstat\",            /*  62 = fstat */\n    \"#63\",              /*  63 = unused */\n    \"#64\",              /*  64 = (old getpagesize) */\n    \"pselect\",          /*  65 = pselect */\n    \"vfork\",            /*  66 = vfork */\n    \"#67\",              /*  67 = unused */\n    \"#68\",              /*  68 = unused */\n    \"brk\",              /*  69 = brk */\n    \"rdglob\",           /*  70 = read from global space */\n    \"wrglob\",           /*  71 = write to global space */\n    \"msec\",             /*  72 = kticks */\n    \"#73\",              /*  73 = unused */\n    \"#74\",              /*  74 = unused */\n    \"#75\",              /*  75 = unused */\n    \"vhangup\",          /*  76 = vhangup */\n    \"#77\",              /*  77 = unused */\n    \"#78\",              /*  78 = unused */\n    \"getgroups\",        /*  79 = getgroups */\n    \"setgroups\",        /*  80 = setgroups */\n    \"getpgrp\",          /*  81 = getpgrp */\n    \"setpgrp\",          /*  82 = setpgrp */\n    \"setitimer\",        /*  83 = setitimer */\n    \"old wait\",         /*  84 = wait,wait3 COMPAT*/\n    \"#85\",              /*  85 = unused */\n    \"getitimer\",        /*  86 = getitimer */\n    \"#87\",              /*  87 = (old gethostname) */\n    \"#88\",              /*  88 = (old sethostname) */\n    \"getdtablesize\",    /*  89 = getdtablesize */\n    \"dup2\",             /*  90 = dup2 */\n    \"#91\",              /*  91 = unused */\n    \"fcntl\",            /*  92 = fcntl */\n    \"select\",           /*  93 = select */\n    \"#94\",              /*  94 = unused */\n    \"fsync\",            /*  95 = fsync */\n    \"setpriority\",      /*  96 = setpriority */\n    \"socket\",           /*  97 = socket */\n    \"connect\",          /*  98 = connect */\n    \"accept\",           /*  99 = accept */\n    \"getpriority\",      /* 100 = getpriority */\n    \"send\",             /* 101 = send */\n    \"recv\",             /* 102 = recv */\n    \"sigreturn\",        /* 103 = sigreturn */\n    \"bind\",             /* 104 = bind */\n    \"setsockopt\",       /* 105 = setsockopt */\n    \"listen\",           /* 106 = listen */\n    \"sigsuspend\",       /* 107 = sigsuspend */\n    \"#108\",             /* 108 = (old sigvec) */\n    \"#109\",             /* 109 = (old sigblock) */\n    \"#110\",             /* 110 = (old sigsetmask) */\n    \"#111\",             /* 111 = (old sigpause)  */\n    \"sigstack\",         /* 112 = sigstack COMPAT-43 */\n    \"recvmsg\",          /* 113 = recvmsg */\n    \"sendmsg\",          /* 114 = sendmsg */\n    \"#115\",             /* 115 = unused */\n    \"gettimeofday\",     /* 116 = gettimeofday */\n    \"getrusage\",        /* 117 = getrusage */\n    \"getsockopt\",       /* 118 = getsockopt */\n    \"#119\",             /* 119 = unused */\n    \"readv\",            /* 120 = readv */\n    \"writev\",           /* 121 = writev */\n    \"settimeofday\",     /* 122 = settimeofday */\n    \"fchown\",           /* 123 = fchown */\n    \"fchmod\",           /* 124 = fchmod */\n    \"recvfrom\",         /* 125 = recvfrom */\n    \"#126\",             /* 126 = (old setreuid) */\n    \"#127\",             /* 127 = (old setregid) */\n    \"rename\",           /* 128 = rename */\n    \"truncate\",         /* 129 = truncate */\n    \"ftruncate\",        /* 130 = ftruncate */\n    \"flock\",            /* 131 = flock */\n    \"#132\",             /* 132 = unused */\n    \"sendto\",           /* 133 = sendto */\n    \"shutdown\",         /* 134 = shutdown */\n    \"socketpair\",       /* 135 = socketpair */\n    \"mkdir\",            /* 136 = mkdir */\n    \"rmdir\",            /* 137 = rmdir */\n    \"utimes\",           /* 138 = utimes */\n    \"#139\",             /* 139 = unused */\n    \"adjtime\",          /* 140 = adjtime */\n    \"getpeername\",      /* 141 = getpeername */\n    \"#142\",             /* 142 = (old gethostid) */\n    \"#143\",             /* 143 = (old sethostid) */\n    \"getrlimit\",        /* 144 = getrlimit */\n    \"setrlimit\",        /* 145 = setrlimit */\n    \"killpg\",           /* 146 = killpg */\n    \"#147\",             /* 147 = unused */\n    \"setquota\",         /* 148 = setquota */\n    \"quota\",            /* 149 = quota */\n    \"getsockname\",      /* 150 = getsockname */\n    \"#151\",             /* 151 = unused */\n    \"ustore\",           /* 152 = ustore */\n    \"ufetch\",           /* 153 = ufetch */\n    \"ucall\",            /* 154 = ucall */\n    \"#155\",             /* 155 = unused */\n};\n#endif\n"
  },
  {
    "path": "sys/kern/tty.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/ioctl.h>\n#include <sys/tty.h>\n#include <sys/proc.h>\n#include <sys/file.h>\n#include <sys/conf.h>\n#include <sys/dk.h>\n#include <sys/uio.h>\n#include <sys/kernel.h>\n#include <sys/systm.h>\n#include <sys/inode.h>\n#include <sys/syslog.h>\n\nstatic  int rts = TIOCM_RTS;\n\n/*\n * These were moved here from tty.h so that they could be easily modified\n * and/or patched instead of recompiling the kernel.  There is only 1 other\n * place which references these - see tty_pty.c\n *\n * The block and unblock numbers may look low but certain devices (the DHV-11\n * for example) have poor silo handling and at high data rates (19200) the\n * raw queue overflows even though we've stopped the sending device.  At 192\n * characters for the 'block' point c-kermit would regularily see dropped data\n * during interactive mode at 19200.\n *\n * It would be nice to have a larger than 8kb clist area and raise these limits\n * but that would require 2 mapping registers and/or a rewrite of the entire\n * clist handling.\n */\nint TTYHOG = 255;\nint TTYBLOCK = 128;\nint TTYUNBLOCK = 64;\n\n/*\n * Table giving parity for characters and indicating\n * character classes to tty driver.  In particular,\n * if the low 6 bits are 0, then the character needs\n * no special processing on output.\n */\nconst char partab[] = {\n    0001,0201,0201,0001,0201,0001,0001,0201,\n    0202,0004,0003,0201,0005,0206,0201,0001,\n    0201,0001,0001,0201,0001,0201,0201,0001,\n    0001,0201,0201,0001,0201,0001,0001,0201,\n    0200,0000,0000,0200,0000,0200,0200,0000,\n    0000,0200,0200,0000,0200,0000,0000,0200,\n    0000,0200,0200,0000,0200,0000,0000,0200,\n    0200,0000,0000,0200,0000,0200,0200,0000,\n    0200,0000,0000,0200,0000,0200,0200,0000,\n    0000,0200,0200,0000,0200,0000,0000,0200,\n    0000,0200,0200,0000,0200,0000,0000,0200,\n    0200,0000,0000,0200,0000,0200,0200,0000,\n    0000,0200,0200,0000,0200,0000,0000,0200,\n    0200,0000,0000,0200,0000,0200,0200,0000,\n    0200,0000,0000,0200,0000,0200,0200,0000,\n    0000,0200,0200,0000,0200,0000,0000,0201,\n\n    /*\n     * 7 bit ascii ends with the last character above,\n     * but we contine through all 256 codes for the sake\n     * of the tty output routines which use special vax\n     * instructions which need a 256 character trt table.\n     */\n\n    0007,0007,0007,0007,0007,0007,0007,0007,\n    0007,0007,0007,0007,0007,0007,0007,0007,\n    0007,0007,0007,0007,0007,0007,0007,0007,\n    0007,0007,0007,0007,0007,0007,0007,0007,\n    0007,0007,0007,0007,0007,0007,0007,0007,\n    0007,0007,0007,0007,0007,0007,0007,0007,\n    0007,0007,0007,0007,0007,0007,0007,0007,\n    0007,0007,0007,0007,0007,0007,0007,0007,\n    0007,0007,0007,0007,0007,0007,0007,0007,\n    0007,0007,0007,0007,0007,0007,0007,0007,\n    0007,0007,0007,0007,0007,0007,0007,0007,\n    0007,0007,0007,0007,0007,0007,0007,0007,\n    0007,0007,0007,0007,0007,0007,0007,0007,\n    0007,0007,0007,0007,0007,0007,0007,0007,\n    0007,0007,0007,0007,0007,0007,0007,0007,\n    0007,0007,0007,0007,0007,0007,0007,0007\n};\n\nconst int tthiwat[NSPEEDS] = {\n    100,    /* 0 baud */\n    100,    /* 50 baud */\n    100,    /* 75 baud */\n    100,    /* 150 baud */\n    100,    /* 200 baud */\n    100,    /* 300 baud */\n    100,    /* 600 baud */\n    200,    /* 1200 baud */\n    200,    /* 1800 baud */\n    400,    /* 2400 baud */\n    400,    /* 4800 baud */\n    400,    /* 9600 baud */\n    650,    /* 19200 baud */\n    650,    /* 38400 baud */\n    1300,   /* 57600 baud */\n    2000,   /* 115.2 kbaud */\n    2000,   /* 230.4 kbaud */\n    2000,   /* 460.8 kbaud */\n    2000,   /* 500 kbaud */\n    2000,   /* 576 kbaud */\n    2000,   /* 921.6 kbaud */\n    2000,   /* 1000 kbaud */\n    2000,   /* 1152 kbaud */\n    2000,   /* 1500 kbaud */\n    2000,   /* 2000 kbaud */\n    2000,   /* 2500 kbaud */\n    2000,   /* 3000 kbaud */\n    2000,   /* 3500 kbaud */\n    2000,   /* 4000 kbaud */\n};\n\nconst int ttlowat[NSPEEDS] = {\n    30,     /* 0 baud */\n    30,     /* 50 baud */\n    30,     /* 75 baud */\n    30,     /* 150 baud */\n    30,     /* 200 baud */\n    30,     /* 300 baud */\n    30,     /* 600 baud */\n    50,     /* 1200 baud */\n    50,     /* 1800 baud */\n    120,    /* 2400 baud */\n    120,    /* 4800 baud */\n    120,    /* 9600 baud */\n    125,    /* 19200 baud */\n    125,    /* 38400 baud */\n    125,    /* 57600 baud */\n    125,    /* 115.2 kbaud */\n    125,    /* 230.4 kbaud */\n    125,    /* 460.8 kbaud */\n    125,    /* 500 kbaud */\n    125,    /* 576 kbaud */\n    125,    /* 921.6 kbaud */\n    125,    /* 1000 kbaud */\n    125,    /* 1152 kbaud */\n    125,    /* 1500 kbaud */\n    125,    /* 2000 kbaud */\n    125,    /* 2500 kbaud */\n    125,    /* 3000 kbaud */\n    125,    /* 3500 kbaud */\n    125,    /* 4000 kbaud */\n};\n\n#define SET(t,f)    (t) |= (f)\n#define CLR(t,f)    (t) &= ~(f)\n#define ISSET(t,f)  ((t) & (f))\n\n/*\n * Set t_chars to default values.\n */\nvoid\nttychars(tp)\n    struct tty *tp;\n{\n    static const struct ttychars ttydefaults = {\n        CERASE, CKILL,  CINTR,  CQUIT,  CSTART, CSTOP,  CEOF,\n        CBRK,   CSUSP,  CDSUSP, CRPRNT, CFLUSH, CWERASE,CLNEXT\n    };\n\n    tp->t_chars = ttydefaults;\n}\n\n/*\n * Wakeup processes waiting on output flow control (TS_ASLEEP).  Normally\n * called from driver start routine (dhvstart, etc) after a transmit done\n * interrupt.  If t_outq.c_cc <= t_lowat then do the wakeup.\n */\nvoid\nttyowake(tp)\n    register struct tty *tp;\n{\n    if (tp->t_outq.c_cc <= TTLOWAT(tp)) {\n        if (ISSET(tp->t_state,TS_ASLEEP)) {\n            CLR(tp->t_state,TS_ASLEEP);\n            wakeup ((caddr_t)&tp->t_outq);\n        }\n        if (tp->t_wsel) {\n            selwakeup (tp->t_wsel, tp->t_state & TS_WCOLL);\n            tp->t_wsel = 0;\n            CLR(tp->t_state,TS_WCOLL);\n        }\n    }\n}\n\nstatic void\nttywait(tp)\n    register struct tty *tp;\n{\n    register int s = spltty();\n\n    while ((tp->t_outq.c_cc || tp->t_state & TS_BUSY) &&\n        tp->t_state & TS_CARR_ON && tp->t_oproc) {\n        (*tp->t_oproc)(tp);\n        /*\n         * If the output routine drains the queue and the device is no longer busy\n         * then don't wait for something that's already happened.\n         */\n        if (tp->t_outq.c_cc == 0 && !ISSET(tp->t_state,TS_BUSY))\n            break;\n        tp->t_state |= TS_ASLEEP;\n        sleep((caddr_t)&tp->t_outq, TTOPRI);\n        splx(s);    /* drop priority, give interrupts a chance */\n        s = spltty();\n    }\n    splx(s);\n}\n\n/*\n * Wait for output to drain, then flush input waiting.\n */\nvoid\nttywflush(tp)\n    register struct tty *tp;\n{\n    ttywait(tp);\n    ttyflush(tp, FREAD);\n}\n\nstatic void\nttyunblock (tp)\n    register struct tty *tp;\n{\n    if (ISSET(tp->t_flags,TANDEM) &&\n        tp->t_startc != _POSIX_VDISABLE &&\n        putc(tp->t_startc, &tp->t_outq) == 0) {\n        CLR(tp->t_state,TS_TBLOCK);\n        ttstart(tp);\n    }\n    if (ISSET(tp->t_flags, RTSCTS) &&\n        (*cdevsw[major(tp->t_dev)].d_ioctl) (tp->t_dev, TIOCMBIS,\n        (caddr_t) &rts, 0) == 0) {\n        CLR(tp->t_state, TS_TBLOCK);\n    }\n}\n\n/*\n * Flush all TTY queues.\n */\nvoid ttyflush (tp, rw)\n    register struct tty *tp;\n    int rw;\n{\n    register int s;\n\n    s = spltty();\n    if (rw & FREAD) {\n        while (getc(&tp->t_canq) >= 0)\n            ;\n        while (getc(&tp->t_rawq) >= 0)\n            ;\n        tp->t_rocount = 0;\n        tp->t_rocol = 0;\n        tp->t_state &= ~TS_LOCAL;\n        ttwakeup (tp);\n    }\n    if (rw & FWRITE) {\n        tp->t_state &= ~TS_TTSTOP;\n        (*cdevsw[major(tp->t_dev)].d_stop)(tp, rw);\n        wakeup ((caddr_t)&tp->t_outq);\n        while (getc(&tp->t_outq) >= 0)\n            ;\n        selwakeup (tp->t_wsel, tp->t_state & TS_WCOLL);\n        CLR(tp->t_state, TS_WCOLL);\n        tp->t_wsel = 0;\n    }\n    if (rw & FREAD && ISSET(tp->t_state,TS_TBLOCK))\n        ttyunblock(tp);\n    splx(s);\n}\n\n/*\n * Send stop character on input overflow.\n */\nvoid\nttyblock(tp)\n    register struct tty *tp;\n{\n    register int total;\n\n    total = tp->t_rawq.c_cc + tp->t_canq.c_cc;\n    /*\n     * Block further input iff:\n     * Current input > threshold AND input is available to user program\n     */\n    if (total >= TTYBLOCK &&\n        ((tp->t_flags & (RAW|CBREAK)) || (tp->t_canq.c_cc > 0)) &&\n        (tp->t_state & TS_TBLOCK) == 0) {\n        /*\n         * TANDEM is the same as IXOFF for all intents and purposes.  Since we could\n         * get called for either software or hardware flow control we need to check\n         * the IXOFF bit.\n         */\n        if (ISSET(tp->t_flags,TANDEM) &&\n            tp->t_stopc != _POSIX_VDISABLE &&\n            putc(tp->t_stopc, &tp->t_outq) == 0) {\n            SET(tp->t_state, TS_TBLOCK);\n            ttstart(tp);\n        }\n        /*\n         * If queue is full, drop RTS to tell modem to stop sending us stuff\n         */\n        if (ISSET(tp->t_flags, RTSCTS) &&\n            (*cdevsw[major(tp->t_dev)].d_ioctl) (tp->t_dev, TIOCMBIC,\n            (caddr_t) &rts, 0) == 0) {\n            SET(tp->t_state, TS_TBLOCK);\n        }\n    }\n}\n\n/*\n * Restart typewriter output following a delay timeout.\n * The name of the routine is passed to the timeout\n * subroutine and it is called during a clock interrupt.\n */\nvoid\nttrstrt(tp)\n    register struct tty *tp;\n{\n    tp->t_state &= ~TS_TIMEOUT;\n    ttstart(tp);\n}\n\n/*\n * Start output on the typewriter. It is used from the top half\n * after some characters have been put on the output queue,\n * from the interrupt routine to transmit the next\n * character, and after a timeout has finished.\n *\n * The spl calls were removed because the priority should already be spltty.\n */\nvoid\nttstart(tp)\n    register struct tty *tp;\n{\n    if (tp->t_oproc)        /* kludge for pty */\n        (*tp->t_oproc) (tp);\n}\n\n/*\n * reinput pending characters after state switch\n * call at spltty().\n */\nstatic void\nttypend (tp)\n    register struct tty *tp;\n{\n    struct clist tq;\n    register int c;\n\n    tp->t_flags &= ~PENDIN;\n    tp->t_state |= TS_TYPEN;\n    tq = tp->t_rawq;\n    tp->t_rawq.c_cc = 0;\n    tp->t_rawq.c_cf = tp->t_rawq.c_cl = 0;\n    while ((c = getc(&tq)) >= 0)\n        ttyinput(c, tp);\n    tp->t_state &= ~TS_TYPEN;\n}\n\nstatic int\nttnread (tp)\n    register struct tty *tp;\n{\n    register int nread = 0;\n\n    if (tp->t_flags & PENDIN)\n        ttypend(tp);\n    nread = tp->t_canq.c_cc;\n    if (tp->t_flags & (RAW|CBREAK))\n        nread += tp->t_rawq.c_cc;\n    return (nread);\n}\n\n/*\n * Common code for tty ioctls.\n */\n/*ARGSUSED*/\nint\nttioctl(tp, com, data, flag)\n    register struct tty *tp;\n    u_int com;\n    caddr_t data;\n    int flag;\n{\n    int s;\n    long newflags;\n\n//printf (\"ttioctl (com=%08x, data=%08x, flag=%d)\\n\", com, data, flag);\n    /*\n     * If the ioctl involves modification,\n     * hang if in the background.\n     */\n    switch (com) {\n\n    case TIOCSETD:\n    case TIOCSETP:\n    case TIOCSETN:\n    case TIOCFLUSH:\n    case TIOCSETC:\n    case TIOCSLTC:\n    case TIOCSPGRP:\n    case TIOCLBIS:\n    case TIOCLBIC:\n    case TIOCLSET:\n    case TIOCSTI:\n    case TIOCSWINSZ:\n        while (u.u_procp->p_pgrp != tp->t_pgrp && tp == u.u_ttyp &&\n           (u.u_procp->p_flag & SVFORK) == 0 &&\n           !(u.u_procp->p_sigignore & sigmask(SIGTTOU)) &&\n           !(u.u_procp->p_sigmask & sigmask(SIGTTOU))) {\n            gsignal(u.u_procp->p_pgrp, SIGTTOU);\n            sleep((caddr_t)&lbolt, TTOPRI);\n        }\n        break;\n    }\n\n    /*\n     * Process the ioctl.\n     */\n    switch (com) {\n\n    /* get discipline number */\n    case TIOCGETD:\n        *(int *)data = 0;\n        break;\n\n    /* set line discipline */\n    case TIOCSETD: {\n        register int t = *(int *)data;\n        if (t != 0)\n            return (ENXIO);\n        break;\n    }\n\n    /* prevent more opens on channel */\n    case TIOCEXCL:\n        tp->t_state |= TS_XCLUDE;\n        break;\n\n    case TIOCNXCL:\n        tp->t_state &= ~TS_XCLUDE;\n        break;\n\n    /* hang up line on last close */\n    case TIOCHPCL:\n        tp->t_state |= TS_HUPCLS;\n        break;\n\n    case TIOCFLUSH: {\n        register int flags = *(int *)data;\n\n        if (flags == 0)\n            flags = FREAD|FWRITE;\n        else\n            flags &= FREAD|FWRITE;\n        ttyflush(tp, flags);\n        break;\n    }\n\n    /* return number of characters immediately available */\n    case FIONREAD:\n        *(off_t *)data = ttnread(tp);\n        break;\n\n    case TIOCOUTQ:\n        *(int *)data = tp->t_outq.c_cc;\n        break;\n\n    case TIOCSTOP:\n        s = spltty();\n        if ((tp->t_state & TS_TTSTOP) == 0) {\n            tp->t_state |= TS_TTSTOP;\n            (*cdevsw[major(tp->t_dev)].d_stop)(tp, 0);\n        }\n        splx(s);\n        break;\n\n    case TIOCSTART:\n        s = spltty();\n        if ((tp->t_state & TS_TTSTOP) || (tp->t_flags & FLUSHO)) {\n            tp->t_state &= ~TS_TTSTOP;\n            tp->t_flags &= ~FLUSHO;\n            ttstart(tp);\n        }\n        splx(s);\n        break;\n\n    /*\n     * Simulate typing of a character at the terminal.\n     */\n    case TIOCSTI:\n        if (u.u_uid && (flag & FREAD) == 0)\n            return (EPERM);\n        if (u.u_uid && u.u_ttyp != tp)\n            return (EACCES);\n        ttyinput (*(char *)data, tp);\n        break;\n\n    case TIOCSETP:\n    case TIOCSETN: {\n        register struct sgttyb *sg = (struct sgttyb *)data;\n\n        tp->t_erase = sg->sg_erase;\n        tp->t_kill = sg->sg_kill;\n        tp->t_ispeed = sg->sg_ispeed;\n        tp->t_ospeed = sg->sg_ospeed;\n        newflags = (tp->t_flags&0xffff0000) | (sg->sg_flags&0xffffL);\n        s = spltty();\n        if (tp->t_flags & RAW || newflags & RAW || com == TIOCSETP) {\n            ttywait(tp);\n            ttyflush(tp, FREAD);\n        } else if ((tp->t_flags & CBREAK) != (newflags & CBREAK)) {\n            if (newflags & CBREAK) {\n                struct clist tq;\n\n                catq(&tp->t_rawq, &tp->t_canq);\n                tq = tp->t_rawq;\n                tp->t_rawq = tp->t_canq;\n                tp->t_canq = tq;\n            } else {\n                tp->t_flags |= PENDIN;\n                newflags |= PENDIN;\n                ttwakeup (tp);\n            }\n        }\n        tp->t_flags = newflags;\n        if (tp->t_flags & RAW) {\n            tp->t_state &= ~TS_TTSTOP;\n            ttstart(tp);\n        }\n        splx(s);\n        break;\n    }\n\n    /* send current parameters to user */\n    case TIOCGETP: {\n        register struct sgttyb *sg = (struct sgttyb *)data;\n\n        sg->sg_ispeed = tp->t_ispeed;\n        sg->sg_ospeed = tp->t_ospeed;\n        sg->sg_erase = tp->t_erase;\n        sg->sg_kill = tp->t_kill;\n        sg->sg_flags = tp->t_flags;\n        break;\n    }\n\n    case FIONBIO:\n        break;  /* XXX remove */\n\n    case FIOASYNC:\n        if (*(int *)data)\n            tp->t_state |= TS_ASYNC;\n        else\n            tp->t_state &= ~TS_ASYNC;\n        break;\n\n    case TIOCGETC:\n        bcopy((caddr_t)&tp->t_intrc, data, sizeof (struct tchars));\n        break;\n\n    case TIOCSETC:\n        bcopy(data, (caddr_t)&tp->t_intrc, sizeof (struct tchars));\n        break;\n\n    /* set/get local special characters */\n    case TIOCSLTC:\n        bcopy(data, (caddr_t)&tp->t_suspc, sizeof (struct ltchars));\n        break;\n\n    case TIOCGLTC:\n        bcopy((caddr_t)&tp->t_suspc, data, sizeof (struct ltchars));\n        break;\n\n    /*\n     * Modify local mode word.\n     */\n    case TIOCLBIS:\n        tp->t_flags |= (long)*(u_int *)data << 16;\n        break;\n\n    case TIOCLBIC:\n        tp->t_flags &= ~((long)*(u_int *)data << 16);\n        break;\n\n    case TIOCLSET:\n        tp->t_flags &= 0xffffL;\n        tp->t_flags |= (long)*(u_int *)data << 16;\n        break;\n\n    case TIOCLGET:\n        *(int *)data = tp->t_flags >> 16;\n        break;\n\n    /*\n     * Allow SPGRP only if tty is open for reading.\n     * Quick check: if we can find a process in the new pgrp,\n     * this user must own that process.\n     * SHOULD VERIFY THAT PGRP IS IN USE AND IS THIS USER'S.\n     */\n    case TIOCSPGRP: {\n        struct proc *p;\n        short pgrp = *(int *)data;\n\n        if (u.u_uid && (flag & FREAD) == 0)\n            return (EPERM);\n        p = pfind(pgrp);\n        if (p && p->p_pgrp == pgrp &&\n            p->p_uid != u.u_uid && u.u_uid && !inferior(p))\n            return (EPERM);\n        tp->t_pgrp = pgrp;\n        break;\n    }\n\n    case TIOCGPGRP:\n        *(int *)data = tp->t_pgrp;\n        break;\n\n    case TIOCSWINSZ:\n        if (bcmp((caddr_t)&tp->t_winsize, data,\n            sizeof (struct winsize))) {\n            tp->t_winsize = *(struct winsize *)data;\n            gsignal(tp->t_pgrp, SIGWINCH);\n        }\n        break;\n\n    case TIOCGWINSZ:\n        *(struct winsize *)data = tp->t_winsize;\n        break;\n\n    default:\n        return (-1);\n    }\n    return (0);\n}\n\n/*\n * Check that input or output is possible on a terminal.\n */\nint\nttyselect (tp, rw)\n    register struct tty *tp;\n    int rw;\n{\n    int nread;\n    register int s = spltty();\n\n    switch (rw) {\n\n    case FREAD:\n        nread = ttnread(tp);\n        if ((nread > 0) || ((tp->t_state & TS_CARR_ON) == 0))\n            goto win;\n        if (tp->t_rsel && tp->t_rsel->p_wchan == (caddr_t)&selwait)\n            tp->t_state |= TS_RCOLL;\n        else\n            tp->t_rsel = u.u_procp;\n        break;\n\n    case FWRITE:\n        if (tp->t_outq.c_cc <= TTLOWAT(tp))\n            goto win;\n        if (tp->t_wsel && tp->t_wsel->p_wchan == (caddr_t)&selwait)\n            tp->t_state |= TS_WCOLL;\n        else\n            tp->t_wsel = u.u_procp;\n        break;\n    }\n    splx(s);\n    return (0);\nwin:\n    splx(s);\n    return (1);\n}\n\n/*\n * Initial open of tty, or (re)entry to line discipline.\n * Establish a process group for distribution of\n * quits and interrupts from the tty.\n */\nint\nttyopen(dev, tp)\n    dev_t dev;\n    register struct tty *tp;\n{\n    register struct proc *pp;\n\n    pp = u.u_procp;\n    tp->t_dev = dev;\n    if (pp->p_pgrp == 0) {\n        u.u_ttyp = tp;\n        u.u_ttyd = dev;\n        if (tp->t_pgrp == 0)\n            tp->t_pgrp = pp->p_pid;\n        pp->p_pgrp = tp->t_pgrp;\n    }\n    tp->t_state &= ~TS_WOPEN;\n    if ((tp->t_state & TS_ISOPEN) == 0) {\n        tp->t_state |= TS_ISOPEN;\n        bzero((caddr_t)&tp->t_winsize, sizeof(tp->t_winsize));\n    }\n    return (0);\n}\n\n/*\n * \"close\" a line discipline\n */\nint\nttylclose (tp, flag)\n    register struct tty *tp;\n    int flag;\n{\n    /*\n     * 4.4 has IO_NDELAY but I think that is a mistake because the upper level\n     * 'close' routines all pass 'fp->f_flags' down.  This was verified with a\n     * printf here - the F* flags are received rather than the IO_* flags!\n     */\n    if (flag & FNDELAY)\n        ttyflush(tp, FREAD|FWRITE);\n    else\n        ttywflush(tp);\n    return (0);\n}\n\n/*\n * Clean terminal on last close.\n */\nvoid\nttyclose(tp)\n    register struct tty *tp;\n{\n    ttyflush(tp, FREAD|FWRITE);\n    tp->t_pgrp = 0;\n    tp->t_state = 0;\n}\n\n/*\n * Handle modem control transition on a tty.\n * Flag indicates new state of carrier.\n * Returns 0 if the line should be turned off, otherwise 1.\n */\nint\nttymodem(tp, flag)\n    register struct tty *tp;\n    int flag;\n{\n    if ((tp->t_state & TS_WOPEN) == 0 && (tp->t_flags & MDMBUF)) {\n        /*\n         * MDMBUF: do flow control according to carrier flag\n         */\n        if (flag) {\n            tp->t_state &= ~TS_TTSTOP;\n            ttstart(tp);\n        } else if ((tp->t_state & TS_TTSTOP) == 0) {\n            tp->t_state |= TS_TTSTOP;\n            (*cdevsw[major(tp->t_dev)].d_stop)(tp, 0);\n        }\n    } else if (flag == 0) {\n        /*\n         * Lost carrier.\n         */\n        tp->t_state &= ~TS_CARR_ON;\n        if (tp->t_state & TS_ISOPEN) {\n            if ((tp->t_flags & NOHANG) == 0) {\n                gsignal(tp->t_pgrp, SIGHUP);\n                gsignal(tp->t_pgrp, SIGCONT);\n                ttyflush(tp, FREAD|FWRITE);\n                return (0);\n            }\n        }\n    } else {\n        /*\n         * Carrier now on.\n         */\n        tp->t_state |= TS_CARR_ON;\n        wakeup ((caddr_t) &tp->t_rawq);\n    }\n    return (1);\n}\n\n/*\n * Default modem control routine (for other line disciplines).\n * Return argument flag, to turn off device on carrier drop.\n */\nint\nnullmodem(tp, flag)\n    register struct tty *tp;\n    int flag;\n{\n    if (flag)\n        tp->t_state |= TS_CARR_ON;\n    else\n        tp->t_state &= ~TS_CARR_ON;\n    return (flag);\n}\n\n/*\n * send string cp to tp\n */\nstatic void\nttyout (cp, tp)\n    register char *cp;\n    register struct tty *tp;\n{\n    register int c;\n\n    while ((c = *cp++))\n        (void) ttyoutput (c, tp);\n}\n\n/*\n * Crt back over cnt chars perhaps\n * erasing them.\n */\nstatic void\nttyrubo(tp, cnt)\n    register struct tty *tp;\n    register int cnt;\n{\n    register char *rubostring = (tp->t_flags & CRTERA) ? \"\\b \\b\" : \"\\b\";\n\n    while (--cnt >= 0)\n        ttyout(rubostring, tp);\n}\n\n/*\n * Echo a typed character to the terminal\n */\nstatic void\nttyecho(c, tp)\n    register int c;\n    register struct tty *tp;\n{\n    register int c7;\n\n    if ((tp->t_state & TS_CNTTB) == 0)\n        tp->t_flags &= ~FLUSHO;\n    if ((tp->t_flags & ECHO) == 0)\n        return;\n    c &= 0377;\n\n    if (tp->t_flags & RAW) {\n        (void) ttyoutput(c, tp);\n        return;\n    }\n    if (c == '\\r' && tp->t_flags & CRMOD)\n        c = '\\n';\n    c7 = c & 0177;\n    if (tp->t_flags & CTLECH) {\n        if ((c7 <= 037 && c != '\\t' && c != '\\n') || c7 == 0177) {\n            (void) ttyoutput('^', tp);\n            if (c7 == 0177)\n                c7 = '?';\n            else\n                c7 += 'A' - 1;\n        }\n    }\n    (void) ttyoutput(c7, tp);\n}\n\n/*\n * Reprint the rawq line.\n * We assume c_cc has already been checked.\n */\nstatic void\nttyretype(tp)\n    register struct tty *tp;\n{\n    register char *cp;\n    int s;\n\n    if (tp->t_rprntc != _POSIX_VDISABLE)\n        ttyecho(tp->t_rprntc, tp);\n    (void) ttyoutput('\\n', tp);\n    s = spltty();\n    for (cp = tp->t_canq.c_cf; cp; cp = nextc(&tp->t_canq, cp))\n        ttyecho(*cp, tp);\n    for (cp = tp->t_rawq.c_cf; cp; cp = nextc(&tp->t_rawq, cp))\n        ttyecho(*cp, tp);\n    tp->t_state &= ~TS_ERASE;\n    splx(s);\n    tp->t_rocount = tp->t_rawq.c_cc;\n    tp->t_rocol = 0;\n}\n\n/*\n * Rubout one character from the rawq of tp\n * as cleanly as possible.\n */\nstatic void\nttyrub(c, tp)\n    register int c;\n    register struct tty *tp;\n{\n    register char *cp;\n    int savecol;\n    int s;\n\n    if ((tp->t_flags & ECHO) == 0)\n        return;\n    tp->t_flags &= ~FLUSHO;\n    c &= 0377;\n    if (tp->t_flags & CRTBS) {\n        if (tp->t_rocount == 0) {\n            /*\n             * Screwed by ttwrite; retype\n             */\n            ttyretype(tp);\n            return;\n        }\n        /*\n         * Out of the ENTIRE tty subsystem would believe this is the ONLY place\n         * that the \"9th\" bit (quoted chars) is tested?\n         */\n        if (c == ('\\t' | 0200) || c == ('\\n' | 0200))\n            ttyrubo (tp, 2);\n        else switch (partab [c &= 0177] & 0177) {\n\n        case ORDINARY:\n            ttyrubo(tp, 1);\n            break;\n\n        case VTAB:\n        case BACKSPACE:\n        case CONTROL:\n        case RETURN:\n            if (tp->t_flags & CTLECH)\n                ttyrubo(tp, 2);\n            break;\n\n        case TAB:\n            if (tp->t_rocount < tp->t_rawq.c_cc) {\n                ttyretype(tp);\n                return;\n            }\n            s = spltty();\n            savecol = tp->t_col;\n            tp->t_state |= TS_CNTTB;\n            tp->t_flags |= FLUSHO;\n            tp->t_col = tp->t_rocol;\n            cp = tp->t_rawq.c_cf;\n            for (; cp; cp = nextc (&tp->t_rawq, cp))\n                ttyecho(*cp, tp);\n            tp->t_flags &= ~FLUSHO;\n            tp->t_state &= ~TS_CNTTB;\n            splx(s);\n            /*\n             * savecol will now be length of the tab\n             */\n            savecol -= tp->t_col;\n            tp->t_col += savecol;\n            if (savecol > 8)\n                savecol = 8;        /* overflow screw */\n            while (--savecol >= 0)\n                (void) ttyoutput('\\b', tp);\n            break;\n\n        default:\n            panic(\"ttyrub\");\n        }\n    } else if (tp->t_flags & PRTERA) {\n        if ((tp->t_state & TS_ERASE) == 0) {\n            (void) ttyoutput('\\\\', tp);\n            tp->t_state |= TS_ERASE;\n        }\n        ttyecho(c, tp);\n    } else\n        ttyecho(tp->t_erase, tp);\n    tp->t_rocount--;\n}\n\n/*\n * Is c a break char for tp?\n */\nint\nttbreakc (c, tp)\n    register int c;\n    register struct tty *tp;\n{\n    return (c == '\\n' || CCEQ (tp->t_eofc, c) || CCEQ (tp->t_brkc, c) ||\n        (c == '\\r' && (tp->t_flags & CRMOD)));\n}\n\n/*\n * Place a character on raw TTY input queue,\n * putting in delimiters and waking up top\n * half as needed.  Also echo if required.\n * The arguments are the character and the\n * appropriate tty structure.\n */\nvoid\nttyinput (c, tp)\n    register int c;\n    register struct tty *tp;\n{\n    long t_flags = tp->t_flags;\n    int i;\n\n    /*\n     * If input is pending take it first.\n     */\n    if (t_flags & PENDIN)\n        ttypend(tp);\n#ifdef UCB_METER\n    tk_nin++;\n#endif\n    c &= 0377;\n\n    /*\n     * In tandem mode, check high water mark.\n     */\n    if (t_flags & (TANDEM | RTSCTS))\n        ttyblock(tp);\n\n    if (t_flags & RAW) {\n        /*\n         * Raw mode, just put character\n         * in input q w/o interpretation.\n         */\n        if (tp->t_rawq.c_cc > TTYHOG)\n            ttyflush(tp, FREAD | FWRITE);\n        else {\n            if (putc(c, &tp->t_rawq) == 0)\n                ttwakeup (tp);\n            ttyecho(c, tp);\n        }\n        goto endcase;\n    }\n\n    /*\n     * Ignore any high bit added during\n     * previous ttyinput processing.\n     */\n    if ((tp->t_state & TS_TYPEN) == 0 && (t_flags & PASS8) == 0)\n        c &= 0177;\n\n    /*\n     * Check for literal nexting very first.  This is the _ONLY_ place\n     * left which ORs in 0200.  Handling literal nexting this way is\n     * what keeps the tty subsystem from being 8 bit clean.  The fix is\n     * horrendous though and is put off for now.  And to think that ALL\n     * of this is made necessary by ttyrubout() - it's the only place that\n     * actually _checks_ the 0200 bit and only for newline and tab chars\n     * at that!\n     *\n     * If we had 9 bit bytes life would be a lot simpler ;)\n     *\n     * The basic idea is to flag the character as \"special\" and also\n     * modify it so that the character does not match any of the special\n     * editing or control characters.  We could just as simply jump directly\n     * to the test for 'cbreak' below.\n     */\n    if (tp->t_state & TS_LNCH) {\n        c |= 0200;\n        tp->t_state &= ~TS_LNCH;\n    }\n\n    /*\n     * Scan for special characters.  This code\n     * is really just a big case statement with\n     * non-constant cases.  The bottom of the\n     * case statement is labeled ``endcase'', so goto\n     * it after a case match, or similar.\n     */\n    if (CCEQ(tp->t_lnextc, c)) {\n        if (t_flags & ECHO)\n            ttyout(\"^\\b\", tp);\n        tp->t_state |= TS_LNCH;\n        goto endcase;\n    }\n    if (CCEQ(tp->t_flushc, c)) {\n        if (t_flags & FLUSHO)\n            tp->t_flags &= ~FLUSHO;\n        else {\n            ttyflush(tp, FWRITE);\n            ttyecho(c, tp);\n            if (tp->t_rawq.c_cc + tp->t_canq.c_cc)\n                ttyretype(tp);\n            tp->t_flags |= FLUSHO;\n        }\n        goto startoutput;\n    }\n    if (CCEQ(tp->t_suspc, c)) {\n        if ((t_flags & NOFLSH) == 0)\n            ttyflush(tp, FREAD);\n        ttyecho(c, tp);\n        gsignal(tp->t_pgrp, SIGTSTP);\n        goto endcase;\n    }\n\n    /*\n     * Handle start/stop characters.\n     */\n    if (CCEQ(tp->t_stopc, c)) {\n        if ((tp->t_state & TS_TTSTOP) == 0) {\n            tp->t_state |= TS_TTSTOP;\n            (*cdevsw[major(tp->t_dev)].d_stop)(tp, 0);\n            return;\n        }\n        if (CCEQ(tp->t_startc, c))\n            return;\n        goto endcase;\n    }\n    if (CCEQ(tp->t_startc, c))\n        goto restartoutput;\n\n    /*\n     * Look for interrupt/quit chars.\n     */\n    if (CCEQ(tp->t_intrc, c) || CCEQ(tp->t_quitc, c)) {\n        if ((t_flags & NOFLSH) == 0)\n            ttyflush(tp, FREAD|FWRITE);\n        ttyecho(c, tp);\n        gsignal(tp->t_pgrp, CCEQ(tp->t_intrc, c) ? SIGINT : SIGQUIT);\n        goto endcase;\n    }\n\n    /*\n     * Cbreak mode, don't process line editing\n     * characters; check high water mark for wakeup.\n     */\n    if (t_flags & CBREAK) {\n        if (tp->t_rawq.c_cc > TTYHOG) {\n            if (tp->t_outq.c_cc < TTHIWAT(tp))\n                (void) ttyoutput(CTRL('g'), tp);\n        } else if (putc(c, &tp->t_rawq) == 0) {\n            ttwakeup (tp);\n            ttyecho (c, tp);\n        }\n        goto endcase;\n    }\n\n    /*\n     * From here on down cooked mode character\n     * processing takes place.\n     */\n    if (CCEQ(tp->t_erase, c) || CCEQ(CTRL('h'), c)) {\n        if (tp->t_rawq.c_cc)\n            ttyrub(unputc(&tp->t_rawq), tp);\n        goto endcase;\n    }\n    if (CCEQ(tp->t_kill, c)) {\n        if (t_flags & CRTKIL &&\n            tp->t_rawq.c_cc == tp->t_rocount) {\n            while (tp->t_rawq.c_cc)\n                ttyrub(unputc(&tp->t_rawq), tp);\n        } else {\n            ttyecho(c, tp);\n            ttyecho('\\n', tp);\n            while (getc(&tp->t_rawq) > 0)\n                ;\n            tp->t_rocount = 0;\n        }\n        tp->t_state &= ~TS_LOCAL;\n        goto endcase;\n    }\n\n    /*\n     * Check word erase/reprint line.\n     */\n    if (CCEQ(tp->t_werasc, c)) {\n        if (tp->t_rawq.c_cc == 0)\n            goto endcase;\n        do {\n            c = unputc(&tp->t_rawq);\n            if (c != ' ' && c != '\\t')\n                goto erasenb;\n            ttyrub(c, tp);\n        } while (tp->t_rawq.c_cc);\n        goto endcase;\nerasenb:\n        do {\n            ttyrub(c, tp);\n            if (tp->t_rawq.c_cc == 0)\n                goto endcase;\n            c = unputc(&tp->t_rawq);\n        } while (c != ' ' && c != '\\t');\n        (void) putc(c, &tp->t_rawq);\n        goto endcase;\n    }\n    if (CCEQ(tp->t_rprntc, c)) {\n        ttyretype(tp);\n        goto endcase;\n    }\n\n    /*\n     * Check for input buffer overflow\n     */\n    if (tp->t_rawq.c_cc+tp->t_canq.c_cc >= TTYHOG) {\n        (void) ttyoutput(CTRL('g'), tp);\n        goto endcase;\n    }\n\n    /*\n     * Put data char in q for user and\n     * wakeup on seeing a line delimiter.\n     */\n    if (putc(c, &tp->t_rawq) == 0) {\n        if (ttbreakc (c, tp)) {\n            tp->t_rocount = 0;\n            catq(&tp->t_rawq, &tp->t_canq);\n            ttwakeup (tp);\n        } else if (tp->t_rocount++ == 0)\n            tp->t_rocol = tp->t_col;\n        if (tp->t_state & TS_ERASE) {\n            tp->t_state &= ~TS_ERASE;\n            (void) ttyoutput('/', tp);\n        }\n        i = tp->t_col;\n        ttyecho(c, tp);\n        if (CCEQ(tp->t_eofc, c) && t_flags & ECHO) {\n            i = MIN(2, tp->t_col - i);\n            while (i > 0) {\n                (void) ttyoutput('\\b', tp);\n                i--;\n            }\n        }\n    }\nendcase:\n    /*\n     * If DEC-style start/stop is enabled don't restart\n     * output until seeing the start character.\n     */\n    if (t_flags & DECCTQ && tp->t_state & TS_TTSTOP &&\n        tp->t_startc != tp->t_stopc)\n        return;\nrestartoutput:\n    tp->t_state &= ~TS_TTSTOP;\n    tp->t_flags &= ~FLUSHO;\nstartoutput:\n    ttstart(tp);\n}\n\n/*\n * Put character on TTY output queue, adding delays,\n * expanding tabs, and handling the CR/NL bit.\n * This is called both from the top half for output,\n * and from interrupt level for echoing.\n * The arguments are the character and the tty structure.\n * Returns < 0 if putc succeeds, otherwise returns char to resend\n */\nint\nttyoutput(c, tp)\n    register int c;\n    register struct tty *tp;\n{\n    register int col;\n\n    if (tp->t_flags & (RAW|LITOUT)) {\n        if (tp->t_flags & FLUSHO)\n            return (-1);\n        if (putc(c, &tp->t_outq))\n            return(c);\n#ifdef UCB_METER\n        tk_nout++;\n#endif\n        return(-1);\n    }\n\n    c &= 0177;\n#ifdef  whybother\n    /*\n     * Ignore EOT in normal mode to avoid\n     * hanging up certain terminals.\n     */\n    if (c == CEOT && (tp->t_flags & CBREAK) == 0)\n        return(-1);\n#endif\n    /*\n     * Turn tabs to spaces as required\n     */\n    if (c == '\\t' && (tp->t_flags & XTABS)) {\n        register int s;\n\n        c = 8 - (tp->t_col&7);\n        if ((tp->t_flags & FLUSHO) == 0) {\n            s = spltty();       /* don't interrupt tabs */\n            c -= b_to_q(\"        \", c, &tp->t_outq);\n#ifdef UCB_METER\n            tk_nout += c;\n#endif\n            splx(s);\n        }\n        tp->t_col += c;\n        return (c ? -1 : '\\t');\n    }\n#ifdef UCB_METER\n    tk_nout++;\n#endif\n    /*\n     * turn <nl> to <cr><lf> if desired.\n     */\n    if (c == '\\n' && tp->t_flags & CRMOD) {\n        if (putc('\\r', &tp->t_outq))\n            return(c);\n#ifdef UCB_METER\n        tk_nout++;\n#endif\n    }\n    if ((tp->t_flags & FLUSHO) == 0 && putc(c, &tp->t_outq))\n        return (c);\n\n    col = tp->t_col;\n    switch (partab[c] & 077) {\n\n    case ORDINARY:\n        col++;\n    case CONTROL:\n        break;\n    case BACKSPACE:\n        if (col)\n            col--;\n        break;\n    case NEWLINE:\n    case RETURN:\n        col = 0;\n        break;\n    case TAB:\n        col = (col | 07) + 1;\n        break;\n    }\n    tp->t_col = col;\n    return(-1);\n}\n\n/*\n * Called from device's read routine after it has\n * calculated the tty-structure given as argument.\n */\nint\nttread (tp, uio, flag)\n    register struct tty *tp;\n    struct uio *uio;\n    int flag;\n{\n    register struct clist *qp;\n    register int c;\n    long t_flags;\n    int s, first, error = 0, carrier;\n\nloop:\n    /*\n     * Take any pending input first.\n     */\n    s = spltty();\n    if (tp->t_flags & PENDIN)\n        ttypend(tp);\n    splx(s);\n\n    /*\n     * Hang process if it's in the background.\n     */\n    if (tp == u.u_ttyp && u.u_procp->p_pgrp != tp->t_pgrp) {\n        if ((u.u_procp->p_sigignore & sigmask(SIGTTIN)) ||\n           (u.u_procp->p_sigmask & sigmask(SIGTTIN)) ||\n            u.u_procp->p_flag & SVFORK)\n            return (EIO);\n        gsignal(u.u_procp->p_pgrp, SIGTTIN);\n        sleep((caddr_t)&lbolt, TTIPRI);\n        goto loop;\n    }\n    t_flags = tp->t_flags;\n\n    /*\n     * In raw mode take characters directly from the\n     * raw queue w/o processing.  Interlock against\n     * device interrupts when interrogating rawq.\n     */\n    if (t_flags & RAW) {\n        s = spltty();\n        if (tp->t_rawq.c_cc <= 0) {\n            carrier = ISSET(tp->t_state, TS_CARR_ON);\n            if (!carrier && ISSET(tp->t_state, TS_ISOPEN)) {\n                splx(s);\n                return(0);  /* EOF */\n            }\n            if (flag & IO_NDELAY) {\n                splx(s);\n                return(EWOULDBLOCK);\n            }\n            sleep((caddr_t)&tp->t_rawq, TTIPRI);\n            splx(s);\n            goto loop;\n        }\n        splx(s);\n        while (!error && tp->t_rawq.c_cc && uio->uio_resid)\n            error = ureadc(getc(&tp->t_rawq), uio);\n        goto checktandem;\n    }\n\n    /*\n     * In cbreak mode use the rawq, otherwise\n     * take characters from the canonicalized q.\n     */\n    qp = t_flags & CBREAK ? &tp->t_rawq : &tp->t_canq;\n\n    /*\n     * No input, sleep on rawq awaiting hardware\n     * receipt and notification.\n     */\n    s = spltty();\n    if (qp->c_cc <= 0) {\n        carrier = ISSET(tp->t_state, TS_CARR_ON);\n        if (!carrier && ISSET(tp->t_state,TS_ISOPEN))\n            {\n            splx(s);\n            return(0);  /* EOF */\n            }\n        if (flag & IO_NDELAY)\n            {\n            splx(s);\n            return(EWOULDBLOCK);\n            }\n        sleep((caddr_t)&tp->t_rawq, TTIPRI);\n        splx(s);\n        goto loop;\n    }\n    splx(s);\n\n    /*\n     * Input present, perform input mapping\n     * and processing (we're not in raw mode).\n     */\n    first = 1;\n    while ((c = getc(qp)) >= 0) {\n        if (t_flags & CRMOD && c == '\\r')\n            c = '\\n';\n        /*\n         * Check for delayed suspend character.\n         */\n        if (CCEQ(tp->t_dsuspc, c)) {\n            gsignal(tp->t_pgrp, SIGTSTP);\n            if (first) {\n                sleep((caddr_t)&lbolt, TTIPRI);\n                goto loop;\n            }\n            break;\n        }\n        /*\n         * Interpret EOF only in cooked mode.\n         */\n        if (CCEQ(tp->t_eofc, c) && (t_flags & CBREAK) == 0)\n            break;\n        /*\n         * Give user character.\n         */\n        error = ureadc(t_flags & PASS8 ? c : c & 0177, uio);\n        if (error)\n            break;\n        if (uio->uio_resid == 0)\n            break;\n        /*\n         * In cooked mode check for a \"break character\"\n         * marking the end of a \"line of input\".\n         */\n        if ((t_flags & CBREAK) == 0 && ttbreakc (c, tp))\n            break;\n        first = 0;\n    }\n\nchecktandem:\n    /*\n     * Look to unblock output now that (presumably)\n     * the input queue has gone down.\n     */\n    s = spltty();\n    if (ISSET(tp->t_state,TS_TBLOCK) && tp->t_rawq.c_cc < TTYUNBLOCK)\n        ttyunblock(tp);\n    splx(s);\n    return(error);\n}\n\n/*\n * Check the output queue on tp for space for a kernel message\n * (from uprintf/tprintf).  Allow some space over the normal\n * hiwater mark so we don't lose messages due to normal flow\n * control, but don't let the tty run amok.\n * Sleeps here are not interruptible, but we return prematurely\n * if new signals come in.\n */\nint\nttycheckoutq (tp, wait)\n    register struct tty *tp;\n    int wait;\n{\n    int hiwat, s, oldsig;\n\n    hiwat = TTHIWAT(tp);\n    s = spltty();\n    oldsig = u.u_procp->p_sig;\n    if (tp->t_outq.c_cc > hiwat + 200)\n        while (tp->t_outq.c_cc > hiwat) {\n        ttstart(tp);\n        if (wait == 0 || u.u_procp->p_sig != oldsig) {\n            splx(s);\n            return(0);\n        }\n        timeout (wakeup, (caddr_t)&tp->t_outq, hz);\n        tp->t_state |= TS_ASLEEP;\n        sleep ((caddr_t) &tp->t_outq, PZERO - 1);\n    }\n    splx(s);\n    return(1);\n}\n\n/*\n * Scan through str up to (but not including str[size]) stopping when a\n * character who's entry in table has mask bits set.  Return number of\n * characters left in str.\n */\nstatic int\nscanc (size, str)\n    unsigned size;\n    const char *str;\n{\n    if (size == 0 || str == 0)\n        return 0;\n    do {\n        if (partab [(u_char) *str++] & 077)\n            return size;\n    } while (--size > 0);\n    return 0;\n}\n\n/*\n * Called from the device's write routine after it has\n * calculated the tty-structure given as argument.\n */\nint\nttwrite (tp, uio, flag)\n    register struct tty *tp;\n    register struct uio *uio;\n    int flag;\n{\n    char *cp;\n    register int cc, ce;\n    int i, hiwat, cnt, error, s;\n    char obuf[OBUFSIZ];\n\n    hiwat = TTHIWAT(tp);\n    cnt = uio->uio_resid;\n    error = 0;\n    cc = 0;\n    cp = 0;\nloop:\n    s = spltty();\n    if (! (tp->t_state & TS_CARR_ON)) {\n        if (tp->t_state & TS_ISOPEN) {\n            splx(s);\n            return(EIO);\n        } else if (flag & IO_NDELAY) {\n            splx(s);\n            error = EWOULDBLOCK;\n            goto out;\n        } else {\n            /* Sleep awaiting carrier. */\n            sleep((caddr_t)&tp->t_rawq, TTIPRI);\n            splx(s);\n            goto loop;\n        }\n    }\n    splx(s);\n    /*\n     * Hang the process if it's in the background.\n     */\n    if (u.u_procp->p_pgrp != tp->t_pgrp && tp == u.u_ttyp &&\n        (tp->t_flags & TOSTOP) && (u.u_procp->p_flag & SVFORK)==0 &&\n        ! (u.u_procp->p_sigignore & sigmask(SIGTTOU)) &&\n        ! (u.u_procp->p_sigmask & sigmask(SIGTTOU))) {\n        gsignal(u.u_procp->p_pgrp, SIGTTOU);\n        sleep((caddr_t)&lbolt, TTIPRI);\n        goto loop;\n    }\n\n    /*\n     * Process the user's data in at most OBUFSIZ\n     * chunks.  Perform lower case simulation and\n     * similar hacks.  Keep track of high water\n     * mark, sleep on overflow awaiting device aid\n     * in acquiring new space.\n     */\n    while (uio->uio_resid || cc > 0) {\n        if (tp->t_flags & FLUSHO) {\n            uio->uio_resid = 0;\n            return(0);\n        }\n        if (tp->t_outq.c_cc > hiwat)\n            goto ovhiwat;\n        /*\n         * Grab a hunk of data from the user, unless we have some\n         * leftover from last time.\n         */\n        if (cc == 0) {\n            cc = MIN(uio->uio_resid, OBUFSIZ);\n            cp = obuf;\n            error = uiomove(cp, cc, uio);\n            if (error) {\n                cc = 0;\n                break;\n            }\n        }\n        /*\n         * If nothing fancy need be done, grab those characters we\n         * can handle without any of ttyoutput's processing and\n         * just transfer them to the output q.  For those chars\n         * which require special processing (as indicated by the\n         * bits in partab), call ttyoutput.  After processing\n         * a hunk of data, look for FLUSHO so ^O's will take effect\n         * immediately.\n         */\n        while (cc > 0) {\n            if (tp->t_flags & (RAW|LITOUT))\n                ce = cc;\n            else {\n                ce = cc - scanc((unsigned)cc, (caddr_t)cp);\n                /*\n                 * If ce is zero, then we're processing\n                 * a special character through ttyoutput.\n                 */\n                if (ce == 0) {\n                    tp->t_rocount = 0;\n                    if (ttyoutput(*cp, tp) >= 0) {\noverflow:                                       /* out of c-lists */\n                        s = spltty();\n                        ttstart(tp);\n                        if (flag & IO_NDELAY) {\n                            splx(s);\n                            uio->uio_resid += cc;\n                            return (uio->uio_resid == cnt ?\n                                EWOULDBLOCK : 0);\n                        }\n                        tp->t_state |= TS_ASLEEP;\n                        sleep((caddr_t)&tp->t_outq, TTOPRI);\n                        splx(s);\n                        goto loop;\n                    }\n                    cp++, cc--;\n                    if (tp->t_flags & FLUSHO ||\n                        tp->t_outq.c_cc > hiwat)\n                        goto ovhiwat;\n                    continue;\n                }\n            }\n            /*\n             * A bunch of normal characters have been found,\n             * transfer them en masse to the output queue and\n             * continue processing at the top of the loop.\n             * If there are any further characters in this\n             * <= OBUFSIZ chunk, the first should be a character\n             * requiring special handling by ttyoutput.\n             */\n            tp->t_rocount = 0;\n            i = b_to_q(cp, ce, &tp->t_outq);\n            ce -= i;\n            tp->t_col += ce;\n            cp += ce, cc -= ce;\n#ifdef UCB_METER\n            tk_nout += ce;\n#endif\n            if (i > 0) {\n                /* out of c-lists */\n                goto overflow;\n            }\n            if (tp->t_flags & FLUSHO || tp->t_outq.c_cc > hiwat)\n                break;\n        }   /* while (cc > 0) */\n        ttstart(tp);\n    }   /* while (uio->uio_resid || cc > 0) */\nout:\n    /*\n     * If cc is nonzero, we leave the uio structure inconsistent, as the\n     * offset and iov pointers have moved forward, but it doesn't matter\n     * (the call will either return short or restart with a new uio).\n     */\n    uio->uio_resid += cc;\n    return (error);\n\novhiwat:\n    s = spltty();\n    /*\n     * This can only occur if FLUSHO is also set in t_flags,\n     * or if ttstart/oproc is synchronous (or very fast).\n     */\n    if (tp->t_outq.c_cc <= hiwat) {\n        splx(s);\n        goto loop;\n    }\n    ttstart(tp);\n    if (flag & IO_NDELAY) {\n        splx(s);\n        uio->uio_resid += cc;\n        return (uio->uio_resid == cnt ? EWOULDBLOCK : 0);\n    }\n    tp->t_state |= TS_ASLEEP;\n    sleep((caddr_t)&tp->t_outq, TTOPRI);\n    splx(s);\n    goto loop;\n}\n\nvoid\nttwakeup (tp)\n    register struct tty *tp;\n{\n    if (tp->t_rsel) {\n        selwakeup (tp->t_rsel, tp->t_state & TS_RCOLL);\n        tp->t_state &= ~TS_RCOLL;\n        tp->t_rsel = 0;\n    }\n    if (tp->t_state & TS_ASYNC)\n        gsignal (tp->t_pgrp, SIGIO);\n    wakeup ((caddr_t) &tp->t_rawq);\n}\n"
  },
  {
    "path": "sys/kern/tty_pty.c",
    "content": "/*\n * Pseudo-teletype Driver\n * (Actually two drivers, requiring two entries in 'cdevsw')\n *\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/pty.h>\n\n#ifdef PTY_ENABLED\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/ioctl.h>\n#include <sys/tty.h>\n#include <sys/user.h>\n#include <sys/conf.h>\n#include <sys/file.h>\n#include <sys/proc.h>\n#include <sys/uio.h>\n#include <sys/kernel.h>\n#include <sys/inode.h>\n#include <sys/types.h>\n#include <sys/ttydev.h>\n\nconst struct devspec ptsdevs[] = {\n    { 0, \"ttyp0\" }, { 1, \"ttyp1\" }, { 2, \"ttyp2\" }, { 3, \"ttyp3\" },\n    { 0, 0 }\n};\n\nconst struct devspec ptcdevs[] = {\n    { 0, \"ptyp0\" }, { 1, \"ptyp1\" }, { 2, \"ptyp2\" }, { 3, \"ptyp3\" },\n    { 0, 0 }\n};\n\nextern  int TTYHOG;     /* see tty.c */\n\n#define BUFSIZ 100      /* Chunk size iomoved to/from user */\n\n/*\n * pts == /dev/tty[pqrs]?\n * ptc == /dev/pty[pqrs]?\n */\nstruct  tty pt_tty[PTY_NUNITS];\n\nstruct  pt_ioctl {\n    int     pt_flags;\n    struct  proc *pt_selr, *pt_selw;\n    u_char  pt_send;\n    u_char  pt_ucntl;\n} pt_ioctl[PTY_NUNITS];\n\nint npty = PTY_NUNITS;          /* for pstat -t */\n\n#define PF_RCOLL    0x01\n#define PF_WCOLL    0x02\n#define PF_PKT      0x08        /* packet mode */\n#define PF_STOPPED  0x10        /* user told stopped */\n#define PF_REMOTE   0x20        /* remote and flow controlled input */\n#define PF_NOSTOP   0x40\n#define PF_UCNTL    0x80        /* user control mode */\n\n/*ARGSUSED*/\nint ptsopen(dev_t dev, int flag, int mode)\n{\n    register struct tty *tp;\n    int error;\n\n#ifdef lint\n    npty = npty;\n#endif\n    if (minor(dev) >= PTY_NUNITS)\n        return (ENXIO);\n    tp = &pt_tty[minor(dev)];\n    if ((tp->t_state & TS_ISOPEN) == 0) {\n        ttychars(tp);       /* Set up default chars */\n        tp->t_ispeed = tp->t_ospeed = B115200;\n        tp->t_flags = 0;    /* No features (nor raw mode) */\n    } else if (tp->t_state&TS_XCLUDE && u.u_uid != 0)\n        return (EBUSY);\n    if (tp->t_oproc)            /* Ctrlr still around. */\n        tp->t_state |= TS_CARR_ON;\n    while ((tp->t_state & TS_CARR_ON) == 0) {\n        tp->t_state |= TS_WOPEN;\n        sleep((caddr_t)&tp->t_rawq, TTIPRI);\n    }\n    error = ttyopen(dev, tp);\n    ptcwakeup (tp, FREAD | FWRITE);\n    return (error);\n}\n\nint ptsclose(dev_t dev, int flag, int mode)\n{\n    register struct tty *tp;\n\n    tp = &pt_tty[minor(dev)];\n    ttyclose(tp);\n    ptcwakeup(tp, FREAD|FWRITE);\n    return 0;\n}\n\nint ptsread(dev_t dev, register struct uio *uio, int flag)\n{\n    register struct tty *tp = &pt_tty[minor(dev)];\n    register struct pt_ioctl *pti = &pt_ioctl[minor(dev)];\n    int error = 0;\n\nagain:\n    if (pti->pt_flags & PF_REMOTE) {\n        while (tp == u.u_ttyp && u.u_procp->p_pgrp != tp->t_pgrp) {\n            if ((u.u_procp->p_sigignore & sigmask(SIGTTIN)) ||\n                (u.u_procp->p_sigmask & sigmask(SIGTTIN)) ||\n                u.u_procp->p_flag&SVFORK)\n                return (EIO);\n            gsignal(u.u_procp->p_pgrp, SIGTTIN);\n            sleep((caddr_t)&lbolt, TTIPRI);\n        }\n        if (tp->t_canq.c_cc == 0) {\n            if (flag & IO_NDELAY)\n                return (EWOULDBLOCK);\n            sleep((caddr_t)&tp->t_canq, TTIPRI);\n            goto again;\n        }\n        while (tp->t_canq.c_cc > 1 && uio->uio_resid)\n            if (ureadc(getc(&tp->t_canq), uio) < 0) {\n                error = EFAULT;\n                break;\n            }\n        if (tp->t_canq.c_cc == 1)\n            (void) getc(&tp->t_canq);\n        if (tp->t_canq.c_cc)\n            return (error);\n    } else\n        if (tp->t_oproc)\n            error = ttread(tp, uio, flag);\n    ptcwakeup(tp, FWRITE);\n    return (error);\n}\n\n/*\n * Write to pseudo-tty.\n * Wakeups of controlling tty will happen\n * indirectly, when tty driver calls ptsstart.\n */\nint ptswrite(dev_t dev, register struct uio *uio, int flag)\n{\n    register struct tty *tp;\n\n    tp = &pt_tty[minor(dev)];\n    if (tp->t_oproc == 0)\n        return (EIO);\n    return ttwrite(tp, uio, flag);\n}\n\n/*\n * Start output on pseudo-tty.\n * Wake up process selecting or sleeping for input from controlling tty.\n */\nvoid ptsstart(struct tty *tp)\n{\n    register struct pt_ioctl *pti = &pt_ioctl[minor(tp->t_dev)];\n\n    if (tp->t_state & TS_TTSTOP)\n        return;\n    if (pti->pt_flags & PF_STOPPED) {\n        pti->pt_flags &= ~PF_STOPPED;\n        pti->pt_send = TIOCPKT_START;\n    }\n    ptcwakeup(tp, FREAD);\n}\n\nvoid ptcwakeup(struct tty *tp, int flag)\n{\n    struct pt_ioctl *pti = &pt_ioctl[minor(tp->t_dev)];\n\n    if (flag & FREAD) {\n        if (pti->pt_selr) {\n            selwakeup(pti->pt_selr, (long)(pti->pt_flags & PF_RCOLL));\n            pti->pt_selr = 0;\n            pti->pt_flags &= ~PF_RCOLL;\n        }\n        wakeup((caddr_t)&tp->t_outq.c_cf);\n    }\n    if (flag & FWRITE) {\n        if (pti->pt_selw) {\n            selwakeup(pti->pt_selw, (long)(pti->pt_flags & PF_WCOLL));\n            pti->pt_selw = 0;\n            pti->pt_flags &= ~PF_WCOLL;\n        }\n        wakeup((caddr_t)&tp->t_rawq.c_cf);\n    }\n}\n\n/*ARGSUSED*/\nint ptcopen(dev_t dev, int flag, int mode)\n{\n    register struct tty *tp;\n    struct pt_ioctl *pti;\n\n    if (minor(dev) >= PTY_NUNITS)\n        return (ENXIO);\n    tp = &pt_tty[minor(dev)];\n    if (tp->t_oproc)\n        return (EIO);\n    tp->t_oproc = ptsstart;\n    ttymodem(tp, 1);\n    pti = &pt_ioctl[minor(dev)];\n    pti->pt_flags = 0;\n    pti->pt_send = 0;\n    pti->pt_ucntl = 0;\n    return (0);\n}\n\nint ptcclose(dev_t dev, int flag, int mode)\n{\n    register struct tty *tp;\n\n    tp = &pt_tty[minor(dev)];\n    ttymodem(tp, 0);\n    tp->t_state &= ~TS_CARR_ON;\n    tp->t_oproc = 0;        /* mark closed */\n    return 0;\n}\n\nint ptcread(dev_t dev, register struct uio *uio, int flag)\n{\n    register struct tty *tp = &pt_tty[minor(dev)];\n    struct pt_ioctl *pti = &pt_ioctl[minor(dev)];\n    char buf[BUFSIZ];\n    int error = 0, cc;\n\n    /*\n     * We want to block until the slave\n     * is open, and there's something to read;\n     * but if we lost the slave or we're NBIO,\n     * then return the appropriate error instead.\n     */\n    for (;;) {\n        if (tp->t_state&TS_ISOPEN) {\n            if (pti->pt_flags&PF_PKT && pti->pt_send) {\n                error = ureadc((int)pti->pt_send, uio);\n                if (error)\n                    return (error);\n                pti->pt_send = 0;\n                return (0);\n            }\n            if (pti->pt_flags&PF_UCNTL && pti->pt_ucntl) {\n                error = ureadc((int)pti->pt_ucntl, uio);\n                if (error)\n                    return (error);\n                pti->pt_ucntl = 0;\n                return (0);\n            }\n            if (tp->t_outq.c_cc && (tp->t_state&TS_TTSTOP) == 0)\n                break;\n        }\n        if ((tp->t_state&TS_CARR_ON) == 0)\n            return (0); /* EOF */\n        if (flag & IO_NDELAY)\n            return (EWOULDBLOCK);\n        sleep((caddr_t)&tp->t_outq.c_cf, TTIPRI);\n    }\n    if (pti->pt_flags & (PF_PKT|PF_UCNTL))\n        error = ureadc(0, uio);\n    while (uio->uio_resid && error == 0) {\n        cc = q_to_b(&tp->t_outq, buf, MIN(uio->uio_resid, BUFSIZ));\n        if (cc <= 0)\n            break;\n        error = uiomove(buf, cc, uio);\n    }\n    if (tp->t_outq.c_cc <= TTLOWAT(tp)) {\n        if (tp->t_state&TS_ASLEEP) {\n            tp->t_state &= ~TS_ASLEEP;\n            wakeup((caddr_t)&tp->t_outq);\n        }\n        if (tp->t_wsel) {\n            selwakeup(tp->t_wsel, tp->t_state & TS_WCOLL);\n            tp->t_wsel = 0;\n            tp->t_state &= ~TS_WCOLL;\n        }\n    }\n    return (error);\n}\n\nvoid ptsstop(register struct tty *tp, int flush)\n{\n    struct pt_ioctl *pti = &pt_ioctl[minor(tp->t_dev)];\n    int flag;\n\n    /* note: FLUSHREAD and FLUSHWRITE already ok */\n    if (flush == 0) {\n        flush = TIOCPKT_STOP;\n        pti->pt_flags |= PF_STOPPED;\n    } else\n        pti->pt_flags &= ~PF_STOPPED;\n    pti->pt_send |= flush;\n    /* change of perspective */\n    flag = 0;\n    if (flush & FREAD)\n        flag |= FWRITE;\n    if (flush & FWRITE)\n        flag |= FREAD;\n    ptcwakeup(tp, flag);\n}\n\nint ptcselect(dev_t dev, int rw)\n{\n    register struct tty *tp = &pt_tty[minor(dev)];\n    struct pt_ioctl *pti = &pt_ioctl[minor(dev)];\n    struct proc *p;\n    int s;\n\n    if ((tp->t_state&TS_CARR_ON) == 0)\n        return (1);\n    switch (rw) {\n\n    case FREAD:\n        /*\n         * Need to block timeouts (ttrstart).\n         */\n        s = spltty();\n        if ((tp->t_state&TS_ISOPEN) &&\n             tp->t_outq.c_cc && (tp->t_state&TS_TTSTOP) == 0) {\n            splx(s);\n            return (1);\n        }\n        splx(s);\n        /* FALLTHROUGH */\n\n    case 0:                 /* exceptional */\n        if ((tp->t_state&TS_ISOPEN) &&\n            ((pti->pt_flags&PF_PKT && pti->pt_send) ||\n             (pti->pt_flags&PF_UCNTL && pti->pt_ucntl)))\n            return (1);\n        if ((p = pti->pt_selr) && p->p_wchan == (caddr_t)&selwait)\n            pti->pt_flags |= PF_RCOLL;\n        else\n            pti->pt_selr = u.u_procp;\n        break;\n\n\n    case FWRITE:\n        if (tp->t_state&TS_ISOPEN) {\n            if (pti->pt_flags & PF_REMOTE) {\n                if (tp->t_canq.c_cc == 0)\n                return (1);\n            } else {\n                if (tp->t_rawq.c_cc + tp->t_canq.c_cc < TTYHOG-2)\n                    return (1);\n                if (tp->t_canq.c_cc == 0 &&\n                (tp->t_flags & (RAW|CBREAK)) == 0)\n                    return (1);\n            }\n        }\n        if ((p = pti->pt_selw) && p->p_wchan == (caddr_t)&selwait)\n            pti->pt_flags |= PF_WCOLL;\n        else\n            pti->pt_selw = u.u_procp;\n        break;\n\n    }\n    return (0);\n}\n\nint ptcwrite(dev_t dev, register struct uio *uio, int flag)\n{\n    register struct tty *tp = &pt_tty[minor(dev)];\n    register char *cp = NULL;\n    register int cc = 0;\n    char locbuf[BUFSIZ];\n    int cnt = 0;\n    struct pt_ioctl *pti = &pt_ioctl[minor(dev)];\n    int error = 0;\n\nagain:\n    if ((tp->t_state&TS_ISOPEN) == 0)\n        goto block;\n    if (pti->pt_flags & PF_REMOTE) {\n        if (tp->t_canq.c_cc)\n            goto block;\n        while (uio->uio_resid && tp->t_canq.c_cc < TTYHOG - 1) {\n            if (cc == 0) {\n                cc = MIN(uio->uio_resid, BUFSIZ);\n                cc = MIN(cc, TTYHOG - 1 - tp->t_canq.c_cc);\n                cp = locbuf;\n                error = uiomove(cp, cc, uio);\n                if (error)\n                    return (error);\n                /* check again for safety */\n                if ((tp->t_state&TS_ISOPEN) == 0)\n                    return (EIO);\n            }\n            if (cc)\n                (void) b_to_q(cp, cc, &tp->t_canq);\n            cc = 0;\n        }\n        (void) putc(0, &tp->t_canq);\n        ttwakeup(tp);\n        wakeup((caddr_t)&tp->t_canq);\n        return (0);\n    }\n    while (uio->uio_resid > 0) {\n        if (cc == 0) {\n            cc = MIN(uio->uio_resid, BUFSIZ);\n            cp = locbuf;\n            error = uiomove(cp, cc, uio);\n            if (error)\n                return (error);\n            /* check again for safety */\n            if ((tp->t_state&TS_ISOPEN) == 0)\n                return (EIO);\n        }\n        while (cc > 0) {\n            if ((tp->t_rawq.c_cc + tp->t_canq.c_cc) >= TTYHOG - 2 &&\n               (tp->t_canq.c_cc > 0 ||\n                  tp->t_flags & (RAW|CBREAK))) {\n                wakeup((caddr_t)&tp->t_rawq);\n                goto block;\n            }\n            ttyinput(*cp++, tp);\n            cnt++;\n            cc--;\n        }\n        cc = 0;\n    }\n    return (0);\nblock:\n    /*\n     * Come here to wait for slave to open, for space\n     * in outq, or space in rawq.\n     */\n    if ((tp->t_state&TS_CARR_ON) == 0)\n        return (EIO);\n    if (flag & IO_NDELAY) {\n        /* adjust for data copied in but not written */\n        uio->uio_resid += cc;\n        if (cnt == 0)\n            return (EWOULDBLOCK);\n        return (0);\n    }\n    sleep((caddr_t)&tp->t_rawq.c_cf, TTOPRI);\n    goto again;\n}\n\nint ptyioctl(dev_t dev, u_int cmd, caddr_t data, int flag)\n{\n    register struct tty *tp = &pt_tty[minor(dev)];\n    register struct pt_ioctl *pti = &pt_ioctl[minor(dev)];\n    int stop, error;\n\n    /*\n     * IF CONTROLLER STTY THEN MUST FLUSH TO PREVENT A HANG.\n     * ttywflush(tp) will hang if there are characters in the outq.\n     */\n    if (cdevsw[major(dev)].d_open == ptcopen)\n        switch (cmd) {\n\n        case TIOCPKT:\n            if (*(int *)data) {\n                if (pti->pt_flags & PF_UCNTL)\n                    return (EINVAL);\n                pti->pt_flags |= PF_PKT;\n            } else\n                pti->pt_flags &= ~PF_PKT;\n            return (0);\n\n        case TIOCUCNTL:\n            if (*(int *)data) {\n                if (pti->pt_flags & PF_PKT)\n                    return (EINVAL);\n                pti->pt_flags |= PF_UCNTL;\n            } else\n                pti->pt_flags &= ~PF_UCNTL;\n            return (0);\n\n        case TIOCREMOTE:\n            if (*(int *)data)\n                pti->pt_flags |= PF_REMOTE;\n            else\n                pti->pt_flags &= ~PF_REMOTE;\n            ttyflush(tp, FREAD|FWRITE);\n            return (0);\n\n        case TIOCSETP:\n        case TIOCSETN:\n        case TIOCSETD:\n            while (getc(&tp->t_outq) >= 0)\n                ;\n            break;\n        }\n    error = ttioctl (tp, cmd, data, flag);\n    if (error < 0) {\n        if (pti->pt_flags & PF_UCNTL &&\n            (cmd & ~0xff) == UIOCCMD(0)) {\n            if (cmd & 0xff) {\n                pti->pt_ucntl = (u_char)cmd;\n                ptcwakeup(tp, FREAD);\n            }\n            return (0);\n        }\n        error = ENOTTY;\n    }\n    stop = (tp->t_flags & RAW) == 0 &&\n        tp->t_stopc == CTRL('s') && tp->t_startc == CTRL('q');\n    if (pti->pt_flags & PF_NOSTOP) {\n        if (stop) {\n            pti->pt_send &= ~TIOCPKT_NOSTOP;\n            pti->pt_send |= TIOCPKT_DOSTOP;\n            pti->pt_flags &= ~PF_NOSTOP;\n            ptcwakeup(tp, FREAD);\n        }\n    } else {\n        if (!stop) {\n            pti->pt_send &= ~TIOCPKT_DOSTOP;\n            pti->pt_send |= TIOCPKT_NOSTOP;\n            pti->pt_flags |= PF_NOSTOP;\n            ptcwakeup(tp, FREAD);\n        }\n    }\n    return (error);\n}\n\nvoid ptyattach()\n{\n    printf(\"pty: %d units\\n\", PTY_NUNITS);\n}\n#endif\n"
  },
  {
    "path": "sys/kern/tty_subr.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/clist.h>\n#include <sys/ioctl.h>\n#include <sys/tty.h>\n#include <sys/systm.h>\n\nchar    cwaiting;\n\n/*\n * Character list get/put\n */\nint\ngetc(p)\n    register struct clist *p;\n{\n    register struct cblock *bp;\n    register int c, s;\n\n    s = spltty();\n    if (p->c_cc <= 0) {\n        c = -1;\n        p->c_cc = 0;\n        p->c_cf = p->c_cl = NULL;\n    } else {\n        c = *p->c_cf++ & 0377;\n        if (--p->c_cc<=0) {\n            bp = (struct cblock *)(p->c_cf-1);\n            bp = (struct cblock *)((int)bp & ~CROUND);\n            p->c_cf = NULL;\n            p->c_cl = NULL;\n            bp->c_next = cfreelist;\n            cfreelist = bp;\n            cfreecount += CBSIZE;\n            if (cwaiting) {\n                wakeup (&cwaiting);\n                cwaiting = 0;\n            }\n        } else if (((int)p->c_cf & CROUND) == 0){\n            bp = (struct cblock *)(p->c_cf);\n            bp--;\n            p->c_cf = bp->c_next->c_info;\n            bp->c_next = cfreelist;\n            cfreelist = bp;\n            cfreecount += CBSIZE;\n            if (cwaiting) {\n                wakeup (&cwaiting);\n                cwaiting = 0;\n            }\n        }\n    }\n    splx(s);\n    return (c);\n}\n\n/*\n * Copy clist to buffer.\n * Return number of bytes moved.\n */\nint\nq_to_b (q, cp, cc)\n    register struct clist *q;\n    char *cp;\n    int cc;\n{\n    register struct cblock *bp;\n    register int nc;\n    int s;\n    char *acp;\n\n    if (cc <= 0)\n        return (0);\n    s = spltty();\n    if (q->c_cc <= 0) {\n        q->c_cc = 0;\n        q->c_cf = q->c_cl = NULL;\n        splx(s);\n        return (0);\n    }\n    acp = cp;\n\n    while (cc) {\n        nc = sizeof (struct cblock) - ((int)q->c_cf & CROUND);\n        nc = MIN(nc, cc);\n        nc = MIN(nc, q->c_cc);\n        (void) bcopy(q->c_cf, cp, (unsigned)nc);\n        q->c_cf += nc;\n        q->c_cc -= nc;\n        cc -= nc;\n        cp += nc;\n        if (q->c_cc <= 0) {\n            bp = (struct cblock *)(q->c_cf - 1);\n            bp = (struct cblock *)((int)bp & ~CROUND);\n            q->c_cf = q->c_cl = NULL;\n            bp->c_next = cfreelist;\n            cfreelist = bp;\n            cfreecount += CBSIZE;\n            if (cwaiting) {\n                wakeup (&cwaiting);\n                cwaiting = 0;\n            }\n            break;\n        }\n        if (((int)q->c_cf & CROUND) == 0) {\n            bp = (struct cblock *)(q->c_cf);\n            bp--;\n            q->c_cf = bp->c_next->c_info;\n            bp->c_next = cfreelist;\n            cfreelist = bp;\n            cfreecount += CBSIZE;\n            if (cwaiting) {\n                wakeup (&cwaiting);\n                cwaiting = 0;\n            }\n        }\n    }\n    splx(s);\n    return (cp - acp);\n}\n\n/*\n * Return count of contiguous characters\n * in clist starting at q->c_cf.\n * Stop counting if flag&character is non-null.\n */\nint ndqb (q, flag)\n    register struct clist *q;\n    int flag;\n{\n    int cc;\n    int s;\n\n    s = spltty();\n    if (q->c_cc <= 0) {\n        cc = -q->c_cc;\n        goto out;\n    }\n    cc = ((int)q->c_cf + CBSIZE) & ~CROUND;\n    cc -= (int)q->c_cf;\n    if (q->c_cc < cc)\n        cc = q->c_cc;\n    if (flag) {\n        register char *p, *end;\n\n        p = q->c_cf;\n        end = p;\n        end += cc;\n        while (p < end) {\n            if (*p & flag) {\n                cc = (int)p;\n                cc -= (int)q->c_cf;\n                break;\n            }\n            p++;\n        }\n    }\nout:\n    splx(s);\n    return (cc);\n}\n\n/*\n * Flush cc bytes from q.\n */\nvoid\nndflush (q, cc)\n    register struct clist *q;\n    register int cc;\n{\n    register struct cblock *bp;\n    char *end;\n    int rem, s;\n\n    s = spltty();\n    if (q->c_cc <= 0)\n        goto out;\n    while (cc>0 && q->c_cc) {\n        bp = (struct cblock *)((int)q->c_cf & ~CROUND);\n        if ((int)bp == (((int)q->c_cl-1) & ~CROUND)) {\n            end = q->c_cl;\n        } else {\n            end = (char *)((int)bp + sizeof (struct cblock));\n        }\n        rem = end - q->c_cf;\n        if (cc >= rem) {\n            cc -= rem;\n            q->c_cc -= rem;\n            q->c_cf = bp->c_next->c_info;\n            bp->c_next = cfreelist;\n            cfreelist = bp;\n            cfreecount += CBSIZE;\n            if (cwaiting) {\n                wakeup (&cwaiting);\n                cwaiting = 0;\n            }\n        } else {\n            q->c_cc -= cc;\n            q->c_cf += cc;\n            if (q->c_cc <= 0) {\n                bp->c_next = cfreelist;\n                cfreelist = bp;\n                cfreecount += CBSIZE;\n                if (cwaiting) {\n                    wakeup (&cwaiting);\n                    cwaiting = 0;\n                }\n            }\n            break;\n        }\n    }\n    if (q->c_cc <= 0) {\n        q->c_cf = q->c_cl = NULL;\n        q->c_cc = 0;\n    }\nout:\n    splx(s);\n}\n\n/*\n * Put a symbol to a character list.\n */\nint\nputc (c, p)\n    int c;\n    register struct clist *p;\n{\n    register struct cblock *bp;\n    register char *cp;\n    register int s;\n\n    s = spltty();\n    if ((cp = p->c_cl) == NULL || p->c_cc < 0 ) {\n        if ((bp = cfreelist) == NULL) {\n            splx(s);\n            return (-1);\n        }\n        cfreelist = bp->c_next;\n        cfreecount -= CBSIZE;\n        bp->c_next = NULL;\n        p->c_cf = cp = bp->c_info;\n    } else if (((int)cp & CROUND) == 0) {\n        bp = (struct cblock *)cp - 1;\n        if ((bp->c_next = cfreelist) == NULL) {\n            splx(s);\n            return (-1);\n        }\n        bp = bp->c_next;\n        cfreelist = bp->c_next;\n        cfreecount -= CBSIZE;\n        bp->c_next = NULL;\n        cp = bp->c_info;\n    }\n    *cp++ = c;\n    p->c_cc++;\n    p->c_cl = cp;\n    splx(s);\n    return (0);\n}\n\n/*\n * Copy buffer to clist.\n * Return number of bytes not transfered.\n */\nint\nb_to_q (cp, cc, q)\n    register char *cp;\n    struct clist *q;\n    register int cc;\n{\n    register char *cq;\n    register struct cblock *bp;\n    register int s, nc;\n    int acc;\n\n    if (cc <= 0)\n        return (0);\n    acc = cc;\n    s = spltty();\n    if ((cq = q->c_cl) == NULL || q->c_cc < 0) {\n        if ((bp = cfreelist) == NULL)\n            goto out;\n        cfreelist = bp->c_next;\n        cfreecount -= CBSIZE;\n        bp->c_next = NULL;\n        q->c_cf = cq = bp->c_info;\n    }\n\n    while (cc) {\n        if (((int)cq & CROUND) == 0) {\n            bp = (struct cblock *)cq - 1;\n            if ((bp->c_next = cfreelist) == NULL)\n                goto out;\n            bp = bp->c_next;\n            cfreelist = bp->c_next;\n            cfreecount -= CBSIZE;\n            bp->c_next = NULL;\n            cq = bp->c_info;\n        }\n        nc = MIN(cc, sizeof (struct cblock) - ((int)cq & CROUND));\n        (void) bcopy(cp, cq, (unsigned)nc);\n        cp += nc;\n        cq += nc;\n        cc -= nc;\n    }\nout:\n    q->c_cl = cq;\n    q->c_cc += acc - cc;\n    splx(s);\n    return (cc);\n}\n\n/*\n * Given a non-NULL pointter into the list (like c_cf which\n * always points to a real character if non-NULL) return the pointer\n * to the next character in the list or return NULL if no more chars.\n *\n * Callers must not allow getc's to happen between nextc's so that the\n * pointer becomes invalid.  Note that interrupts are NOT masked.\n */\nchar *\nnextc (p, cp)\n    register struct clist *p;\n    register char *cp;\n{\n    register char *rcp;\n\n    if (p->c_cc && ++cp != p->c_cl) {\n        if (((int)cp & CROUND) == 0)\n            rcp = ((struct cblock *)cp)[-1].c_next->c_info;\n        else\n            rcp = cp;\n    } else\n        rcp = (char *)NULL;\n    return (rcp);\n}\n\n/*\n * Remove the last character in the list and return it.\n */\nint\nunputc (p)\n    register struct clist *p;\n{\n    register struct cblock *bp;\n    register int c, s;\n    struct cblock *obp;\n\n    s = spltty();\n    if (p->c_cc <= 0)\n        c = -1;\n    else {\n        c = *--p->c_cl;\n        if (--p->c_cc <= 0) {\n            bp = (struct cblock *)p->c_cl;\n            bp = (struct cblock *)((int)bp & ~CROUND);\n            p->c_cl = p->c_cf = NULL;\n            bp->c_next = cfreelist;\n            cfreelist = bp;\n            cfreecount += CBSIZE;\n        } else if (((int)p->c_cl & CROUND) == sizeof(bp->c_next)) {\n            p->c_cl = (char *)((int)p->c_cl & ~CROUND);\n            bp = (struct cblock *)p->c_cf;\n            bp = (struct cblock *)((int)bp & ~CROUND);\n            while (bp->c_next != (struct cblock *)p->c_cl)\n                bp = bp->c_next;\n            obp = bp;\n            p->c_cl = (char *)(bp + 1);\n            bp = bp->c_next;\n            bp->c_next = cfreelist;\n            cfreelist = bp;\n            cfreecount += CBSIZE;\n            obp->c_next = NULL;\n        }\n    }\n    splx(s);\n    return (c);\n}\n\n/*\n * Put the chars in the from que\n * on the end of the to que.\n */\nvoid\ncatq (from, to)\n    register struct clist *from, *to;\n{\n    char bbuf [CBSIZE*4];\n    register int c;\n    int s;\n\n    s = spltty();\n    if (to->c_cc == 0) {\n        *to = *from;\n        from->c_cc = 0;\n        from->c_cf = NULL;\n        from->c_cl = NULL;\n        splx(s);\n        return;\n    }\n    splx(s);\n    while (from->c_cc > 0) {\n        c = q_to_b(from, bbuf, sizeof bbuf);\n        (void) b_to_q(bbuf, c, to);\n    }\n}\n"
  },
  {
    "path": "sys/kern/tty_tty.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *  @(#)tty_tty.c   1.2 (2.11BSD GTE) 11/29/94\n */\n\n/*\n * Indirect driver for controlling tty.\n *\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/ioctl.h>\n#include <sys/tty.h>\n#include <sys/conf.h>\n\n/*ARGSUSED*/\nint\nsyopen (dev, flag)\n    dev_t dev;\n    int flag;\n{\n    if (u.u_ttyp == NULL)\n        return (ENXIO);\n    return((*cdevsw[major(u.u_ttyd)].d_open)(u.u_ttyd, flag, 0));\n}\n\n/*ARGSUSED*/\nint\nsyread (dev, uio, flag)\n    dev_t dev;\n    struct uio *uio;\n    int flag;\n{\n    if (u.u_ttyp == NULL)\n        return (ENXIO);\n    return ((*cdevsw[major(u.u_ttyd)].d_read)(u.u_ttyd, uio, flag));\n}\n\n/*ARGSUSED*/\nint\nsywrite (dev, uio, flag)\n    dev_t dev;\n    struct uio *uio;\n    int flag;\n{\n    if (u.u_ttyp == NULL)\n        return (ENXIO);\n    return ((*cdevsw[major(u.u_ttyd)].d_write)(u.u_ttyd, uio, flag));\n}\n\n/*ARGSUSED*/\nint\nsyioctl (dev, cmd, addr, flag)\n    dev_t dev;\n    u_int cmd;\n    caddr_t addr;\n    int flag;\n{\n    if (cmd == TIOCNOTTY) {\n        u.u_ttyp = 0;\n        u.u_ttyd = 0;\n        u.u_procp->p_pgrp = 0;\n        return (0);\n    }\n    if (u.u_ttyp == NULL)\n        return (ENXIO);\n    return ((*cdevsw[major(u.u_ttyd)].d_ioctl)(u.u_ttyd, cmd, addr, flag));\n}\n\n/*ARGSUSED*/\nint\nsyselect (dev, flag)\n    dev_t dev;\n    int flag;\n{\n\n    if (u.u_ttyp == NULL) {\n        u.u_error = ENXIO;\n        return (0);\n    }\n    return ((*cdevsw[major(u.u_ttyd)].d_select)(u.u_ttyd, flag));\n}\n"
  },
  {
    "path": "sys/kern/ufs_alloc.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/fs.h>\n#include <sys/dir.h>\n#include <sys/inode.h>\n#include <sys/buf.h>\n#include <sys/user.h>\n#include <sys/kernel.h>\n#include <sys/mount.h>\n#include <sys/proc.h>\n#include <sys/systm.h>\n\ntypedef struct fblk *FBLKP;\n\n/*\n * Allocate a block in the file system.\n *\n * alloc will obtain the next available free disk block from the\n * free list of the specified device.  The super block has up to\n * NICFREE remembered free blocks; the last of these is read to\n * obtain NICFREE more...\n */\nstruct buf *\nballoc(ip, flags)\n    struct inode *ip;\n    int flags;\n{\n    register struct fs *fs;\n    register struct buf *bp;\n    int async;\n    daddr_t bno;\n\n    fs = ip->i_fs;\n    async = fs->fs_flags & MNT_ASYNC;\n\n    while (fs->fs_flock)\n        sleep((caddr_t)&fs->fs_flock, PINOD);\n    do {\n        if (fs->fs_nfree <= 0)\n            goto nospace;\n        if (fs->fs_nfree > NICFREE) {\n            fserr (fs, \"bad free count\");\n            goto nospace;\n        }\n        bno = fs->fs_free[--fs->fs_nfree];\n        if (bno == 0)\n            goto nospace;\n    } while (badblock(fs, bno));\n    if (fs->fs_nfree <= 0) {\n        fs->fs_flock++;\n        bp = bread(ip->i_dev, bno);\n        if (((bp->b_flags&B_ERROR) == 0) && (bp->b_resid==0)) {\n            register struct fblk *fbp;\n\n            fbp = (FBLKP) bp->b_addr;\n            *((FBLKP)&fs->fs_nfree) = *fbp;\n        }\n        brelse(bp);\n        /*\n         * Write the superblock back, synchronously if requested,\n         * so that the free list pointer won't point at garbage.\n         * We can still end up with dups in free if we then\n         * use some of the blocks in this freeblock, then crash\n         * without a sync.\n         */\n        bp = getblk(ip->i_dev, SUPERB);\n        fs->fs_fmod = 0;\n        fs->fs_time = time.tv_sec;\n        {\n            register struct fs *fps;\n\n            fps = (struct fs*) bp->b_addr;\n            *fps = *fs;\n        }\n        if (!async)\n            bwrite(bp);\n        else\n            bdwrite(bp);\n        fs->fs_flock = 0;\n        wakeup((caddr_t)&fs->fs_flock);\n        if (fs->fs_nfree <=0)\n            goto nospace;\n    }\n    bp = getblk(ip->i_dev, bno);\n    bp->b_resid = 0;\n    if (flags & B_CLRBUF)\n        bzero (bp->b_addr, MAXBSIZE);\n    fs->fs_fmod = 1;\n    fs->fs_tfree--;\n    return(bp);\n\nnospace:\n    fs->fs_nfree = 0;\n    fs->fs_tfree = 0;\n    fserr (fs, \"file system full\");\n    /*\n     * THIS IS A KLUDGE...\n     * SHOULD RATHER SEND A SIGNAL AND SUSPEND THE PROCESS IN A\n     * STATE FROM WHICH THE SYSTEM CALL WILL RESTART\n     */\n    uprintf(\"\\n%s: write failed, file system full\\n\", fs->fs_fsmnt);\n    {\n        register int i;\n\n        for (i = 0; i < 5; i++)\n            sleep((caddr_t)&lbolt, PRIBIO);\n    }\n    u.u_error = ENOSPC;\n    return(NULL);\n}\n\n/*\n * Allocate an inode in the file system.\n *\n * Allocate an unused I node on the specified device.  Used with file\n * creation.  The algorithm keeps up to NICINOD spare I nodes in the\n * super block.  When this runs out, a linear search through the I list\n * is instituted to pick up NICINOD more.\n */\nstruct inode *\nialloc (pip)\n    struct inode *pip;\n{\n    register struct fs *fs;\n    register struct buf *bp;\n    register struct inode *ip;\n    int i;\n    struct dinode *dp;\n    ino_t ino;\n    daddr_t adr;\n    ino_t inobas;\n    int first;\n    struct inode *ifind();\n    char    *emsg = \"no inodes free\";\n\n    fs = pip->i_fs;\n    while (fs->fs_ilock)\n        sleep((caddr_t)&fs->fs_ilock, PINOD);\nloop:\n    if (fs->fs_ninode > 0) {\n        ino = fs->fs_inode[--fs->fs_ninode];\n        if (ino <= ROOTINO)\n            goto loop;\n        ip = iget(pip->i_dev, fs, ino);\n        if (ip == NULL)\n            return(NULL);\n        if (ip->i_mode == 0) {\n            bzero((caddr_t)ip->i_addr,sizeof(ip->i_addr));\n            ip->i_flags = 0;\n            fs->fs_fmod = 1;\n            fs->fs_tinode--;\n            return(ip);\n        }\n        /*\n         * Inode was allocated after all.\n         * Look some more.\n         */\n        iput(ip);\n        goto loop;\n    }\n    fs->fs_ilock++;\n    if (fs->fs_nbehind < 4 * NICINOD) {\n        first = 1;\n        ino = fs->fs_lasti;\n#ifdef DIAGNOSTIC\n        if (itoo(ino))\n            panic(\"ialloc\");\n#endif\n        adr = itod(ino);\n    } else {\nfromtop:\n        first = 0;\n        ino = 1;\n        adr = SUPERB+1;\n        fs->fs_nbehind = 0;\n    }\n    inobas = 0;\n    for (; adr < fs->fs_isize; adr++) {\n        inobas = ino;\n        bp = bread(pip->i_dev, adr);\n        if ((bp->b_flags & B_ERROR) || bp->b_resid) {\n            brelse(bp);\n            ino += INOPB;\n            continue;\n        }\n        dp = (struct dinode*) bp->b_addr;\n        for (i = 0;i < INOPB;i++) {\n            if (dp->di_mode != 0)\n                goto cont;\n            if (ifind(pip->i_dev, ino))\n                goto cont;\n            fs->fs_inode[fs->fs_ninode++] = ino;\n            if (fs->fs_ninode >= NICINOD)\n                break;\n        cont:\n            ino++;\n            dp++;\n        }\n        brelse(bp);\n        if (fs->fs_ninode >= NICINOD)\n            break;\n    }\n    if (fs->fs_ninode < NICINOD && first)\n        goto fromtop;\n    fs->fs_lasti = inobas;\n    fs->fs_ilock = 0;\n    wakeup((caddr_t)&fs->fs_ilock);\n    if (fs->fs_ninode > 0)\n        goto loop;\n    fserr (fs, emsg);\n    uprintf(\"\\n%s: %s\\n\", fs->fs_fsmnt, emsg);\n    u.u_error = ENOSPC;\n    return(NULL);\n}\n\n/*\n * Free a block or fragment.\n *\n * Place the specified disk block back on the free list of the\n * specified device.\n */\nvoid\nfree (ip, bno)\n    struct inode *ip;\n    daddr_t bno;\n{\n    register struct fs *fs;\n    register struct buf *bp;\n    struct fblk *fbp;\n\n    fs = ip->i_fs;\n    if (badblock (fs, bno)) {\n        printf(\"bad block %D, ino %d\\n\", bno, ip->i_number);\n        return;\n    }\n    while (fs->fs_flock)\n        sleep((caddr_t)&fs->fs_flock, PINOD);\n    if (fs->fs_nfree <= 0) {\n        fs->fs_nfree = 1;\n        fs->fs_free[0] = 0;\n    }\n    if (fs->fs_nfree >= NICFREE) {\n        fs->fs_flock++;\n        bp = getblk(ip->i_dev, bno);\n        fbp = (FBLKP) bp->b_addr;\n        *fbp = *((FBLKP)&fs->fs_nfree);\n        fs->fs_nfree = 0;\n        if (fs->fs_flags & MNT_ASYNC)\n            bdwrite(bp);\n        else\n            bwrite(bp);\n        fs->fs_flock = 0;\n        wakeup((caddr_t)&fs->fs_flock);\n    }\n    fs->fs_free[fs->fs_nfree++] = bno;\n    fs->fs_tfree++;\n    fs->fs_fmod = 1;\n}\n\n/*\n * Free an inode.\n *\n * Free the specified I node on the specified device.  The algorithm\n * stores up to NICINOD I nodes in the super block and throws away any more.\n */\nvoid\nifree (ip, ino)\n    struct inode *ip;\n    ino_t ino;\n{\n    register struct fs *fs;\n\n    fs = ip->i_fs;\n    fs->fs_tinode++;\n    if (fs->fs_ilock)\n        return;\n    if (fs->fs_ninode >= NICINOD) {\n        if (fs->fs_lasti > ino)\n            fs->fs_nbehind++;\n        return;\n    }\n    fs->fs_inode[fs->fs_ninode++] = ino;\n    fs->fs_fmod = 1;\n}\n\n/*\n * Fserr prints the name of a file system with an error diagnostic.\n *\n * The form of the error message is:\n *  fs: error message\n */\nvoid\nfserr (fp, cp)\n    struct fs *fp;\n    char *cp;\n{\n    printf (\"%s: %s\\n\", fp->fs_fsmnt, cp);\n}\n"
  },
  {
    "path": "sys/kern/ufs_bio.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/buf.h>\n#include <sys/user.h>\n#include <sys/conf.h>\n#include <sys/fs.h>\n#include <sys/dk.h>\n#include <sys/systm.h>\n#include <sys/map.h>\n#include <sys/proc.h>\n\n/*\n * Read in (if necessary) the block and return a buffer pointer.\n */\nstruct buf *\nbread (dev, blkno)\n    dev_t dev;\n    daddr_t blkno;\n{\n    register struct buf *bp;\n\n    bp = getblk(dev, blkno);\n    if (bp->b_flags&(B_DONE|B_DELWRI)) {\n        return (bp);\n    }\n    bp->b_flags |= B_READ;\n    bp->b_bcount = DEV_BSIZE;           /* XXX? KB */\n    (*bdevsw[major(dev)].d_strategy)(bp);\n    u.u_ru.ru_inblock++;                /* pay for read */\n    biowait(bp);\n    return(bp);\n}\n\n/*\n * Read in the block, like bread, but also start I/O on the\n * read-ahead block (which is not allocated to the caller)\n */\nstruct buf *\nbreada(dev, blkno, rablkno)\n    register dev_t dev;\n    daddr_t blkno;\n    daddr_t rablkno;\n{\n    register struct buf *bp, *rabp;\n\n    bp = NULL;\n    /*\n     * If the block isn't in core, then allocate\n     * a buffer and initiate i/o (getblk checks\n     * for a cache hit).\n     */\n    if (! incore (dev, blkno)) {\n        bp = getblk(dev, blkno);\n        if ((bp->b_flags&(B_DONE|B_DELWRI)) == 0) {\n            bp->b_flags |= B_READ;\n            bp->b_bcount = DEV_BSIZE;           /* XXX? KB */\n            (*bdevsw[major(dev)].d_strategy)(bp);\n            u.u_ru.ru_inblock++;                /* pay for read */\n        }\n    }\n\n    /*\n     * If there's a read-ahead block, start i/o\n     * on it also (as above).\n     */\n    if (rablkno) {\n        if (! incore (dev, rablkno)) {\n            rabp = getblk(dev, rablkno);\n            if (rabp->b_flags & (B_DONE|B_DELWRI)) {\n                brelse(rabp);\n            } else {\n                rabp->b_flags |= B_READ|B_ASYNC;\n                rabp->b_bcount = DEV_BSIZE;     /* XXX? KB */\n                (*bdevsw[major(dev)].d_strategy)(rabp);\n                u.u_ru.ru_inblock++;            /* pay in advance */\n            }\n        }\n    }\n\n    /*\n     * If block was in core, let bread get it.\n     * If block wasn't in core, then the read was started\n     * above, and just wait for it.\n     */\n    if (bp == NULL)\n        return (bread(dev, blkno));\n    biowait(bp);\n    return (bp);\n}\n\n/*\n * Write the buffer, waiting for completion.\n * Then release the buffer.\n */\nvoid\nbwrite(bp)\n    register struct buf *bp;\n{\n    register int flag;\n\n    flag = bp->b_flags;\n    bp->b_flags &= ~(B_READ | B_DONE | B_ERROR | B_DELWRI);\n    if ((flag&B_DELWRI) == 0)\n        u.u_ru.ru_oublock++;                /* noone paid yet */\n    bp->b_bcount = DEV_BSIZE;               /* XXX? KB */\n    (*bdevsw[major(bp->b_dev)].d_strategy)(bp);\n\n    /*\n     * If the write was synchronous, then await i/o completion.\n     * If the write was \"delayed\", then we put the buffer on\n     * the q of blocks awaiting i/o completion status.\n     */\n    if ((flag&B_ASYNC) == 0) {\n        biowait(bp);\n        brelse(bp);\n    } else if (flag & B_DELWRI)\n        bp->b_flags |= B_AGE;\n}\n\n/*\n * Release the buffer, marking it so that if it is grabbed\n * for another purpose it will be written out before being\n * given up (e.g. when writing a partial block where it is\n * assumed that another write for the same block will soon follow).\n * This can't be done for magtape, since writes must be done\n * in the same order as requested.\n */\nvoid\nbdwrite (bp)\n    register struct buf *bp;\n{\n\n    if ((bp->b_flags&B_DELWRI) == 0)\n        u.u_ru.ru_oublock++;        /* noone paid yet */\n    if (bdevsw[major(bp->b_dev)].d_flags & B_TAPE) {\n        bawrite(bp);\n    }\n    else {\n        bp->b_flags |= B_DELWRI | B_DONE;\n        brelse(bp);\n    }\n}\n\n/*\n * Release the buffer, with no I/O implied.\n */\nvoid\nbrelse (bp)\n    register struct buf *bp;\n{\n    register struct buf *flist;\n    register int s;\n\n    /*\n     * If someone's waiting for the buffer, or\n     * is waiting for a buffer, wake 'em up.\n     */\n    if (bp->b_flags&B_WANTED)\n        wakeup((caddr_t)bp);\n    if (bfreelist[0].b_flags&B_WANTED) {\n        bfreelist[0].b_flags &= ~B_WANTED;\n        wakeup((caddr_t)bfreelist);\n    }\n    if (bp->b_flags&B_ERROR) {\n        if (bp->b_flags & B_LOCKED)\n            bp->b_flags &= ~B_ERROR;    /* try again later */\n        else\n            bp->b_dev = NODEV;          /* no assoc */\n    }\n    /*\n     * Stick the buffer back on a free list.\n     */\n    s = splbio();\n    if (bp->b_flags & (B_ERROR|B_INVAL)) {\n        /* block has no info ... put at front of most free list */\n        flist = &bfreelist[BQ_AGE];\n        binsheadfree(bp, flist);\n    } else {\n        if (bp->b_flags & B_LOCKED)\n            flist = &bfreelist[BQ_LOCKED];\n        else if (bp->b_flags & B_AGE)\n            flist = &bfreelist[BQ_AGE];\n        else\n            flist = &bfreelist[BQ_LRU];\n        binstailfree(bp, flist);\n    }\n    bp->b_flags &= ~(B_WANTED|B_BUSY|B_ASYNC|B_AGE);\n    splx(s);\n}\n\n/*\n * See if the block is associated with some buffer\n * (mainly to avoid getting hung up on a wait in breada)\n */\nint\nincore (dev, blkno)\n    register dev_t dev;\n    daddr_t blkno;\n{\n    register struct buf *bp;\n    register struct buf *dp;\n\n    dp = BUFHASH(dev, blkno);\n    blkno = fsbtodb(blkno);\n    for (bp = dp->b_forw; bp != dp; bp = bp->b_forw)\n        if (bp->b_blkno == blkno && bp->b_dev == dev &&\n            (bp->b_flags & B_INVAL) == 0)\n            return (1);\n    return (0);\n}\n\n/*\n * Find a buffer which is available for use.\n * Select something from a free list.\n * Preference is to AGE list, then LRU list.\n */\nstruct buf *\ngetnewbuf(void)\n{\n    register struct buf *bp, *dp;\n    int s;\n\nloop:\n    s = splbio();\n    for (dp = &bfreelist[BQ_AGE]; dp > bfreelist; dp--)\n        if (dp->av_forw != dp)\n            break;\n    if (dp == bfreelist) {      /* no free blocks */\n        dp->b_flags |= B_WANTED;\n        sleep((caddr_t)dp, PRIBIO+1);\n        splx(s);\n        goto loop;\n    }\n    splx(s);\n    bp = dp->av_forw;\n    notavail(bp);\n    if (bp->b_flags & B_DELWRI) {\n        bawrite(bp);\n        goto loop;\n    }\n    if(bp->b_flags & (B_RAMREMAP|B_PHYS)) {\n#ifdef DIAGNOSTIC\n        if ((bp < &buf[0]) || (bp >= &buf[NBUF]))\n            panic(\"getnewbuf: RAMREMAP bp addr\");\n#endif\n        bp->b_addr = bufdata + DEV_BSIZE * (bp - buf);\n    }\n    bp->b_flags = B_BUSY;\n    return (bp);\n}\n\n/*\n * Assign a buffer for the given block.  If the appropriate\n * block is already associated, return it; otherwise search\n * for the oldest non-busy buffer and reassign it.\n *\n * We use splx here because this routine may be called\n * on the interrupt stack during a dump, and we don't\n * want to lower the ipl back to 0.\n */\nstruct buf *\ngetblk(dev, blkno)\n    register dev_t dev;\n    daddr_t blkno;\n{\n    register struct buf *bp, *dp;\n    daddr_t dblkno;\n    int s;\n\n#ifdef DIAGNOSTIC\n    if (major(dev) >= nblkdev)\n        panic(\"blkdev\");\n#endif\n    /*\n     * Search the cache for the block.  If we hit, but\n     * the buffer is in use for i/o, then we wait until\n     * the i/o has completed.\n     */\n    dp = BUFHASH(dev, blkno);\n    dblkno = fsbtodb(blkno);\nloop:\n    for (bp = dp->b_forw; bp != dp; bp = bp->b_forw) {\n        if (bp->b_blkno != dblkno || bp->b_dev != dev ||\n            bp->b_flags&B_INVAL)\n            continue;\n        s = splbio();\n        if (bp->b_flags&B_BUSY) {\n            bp->b_flags |= B_WANTED;\n            sleep((caddr_t)bp, PRIBIO+1);\n            splx(s);\n            goto loop;\n        }\n        splx(s);\n        notavail(bp);\n        return (bp);\n    }\n    bp = getnewbuf();\n    bfree(bp);\n    bremhash(bp);\n    binshash(bp, dp);\n    bp->b_dev = dev;\n    bp->b_blkno = dblkno;\n    bp->b_error = 0;\n    return (bp);\n}\n\n/*\n * get an empty block,\n * not assigned to any particular device\n */\nstruct buf *\ngeteblk()\n{\n    register struct buf *bp, *flist;\n\n    bp = getnewbuf();\n    bp->b_flags |= B_INVAL;\n    bfree(bp);\n    bremhash(bp);\n    flist = &bfreelist[BQ_AGE];\n    binshash(bp, flist);\n    bp->b_dev = (dev_t)NODEV;\n    bp->b_error = 0;\n    return (bp);\n}\n\n/*\n * Wait for I/O completion on the buffer; return errors\n * to the user.\n */\nvoid\nbiowait(bp)\n    register struct buf *bp;\n{\n    register int s;\n\n    s = splbio();\n    while ((bp->b_flags & B_DONE) == 0)\n        sleep((caddr_t)bp, PRIBIO);\n    splx(s);\n    if (! u.u_error)            /* XXX */\n        u.u_error = geterror(bp);\n}\n\n/*\n * Mark I/O complete on a buffer.\n * Wake up anyone waiting for it.\n */\nvoid\nbiodone(bp)\n    register struct buf *bp;\n{\n    if (bp->b_flags & B_DONE)\n        panic(\"dup biodone\");\n    bp->b_flags |= B_DONE;\n    if (bp->b_flags & B_ASYNC)\n        brelse(bp);\n    else {\n        bp->b_flags &= ~B_WANTED;\n        wakeup((caddr_t)bp);\n    }\n}\n\n/*\n * Insure that no part of a specified block is in an incore buffer.\n */\nvoid\nblkflush (dev, blkno)\n    register dev_t dev;\n    daddr_t blkno;\n{\n    register struct buf *ep;\n    struct buf *dp;\n    register int s;\n\n    dp = BUFHASH(dev, blkno);\n    blkno = fsbtodb(blkno);\nloop:\n    for (ep = dp->b_forw; ep != dp; ep = ep->b_forw) {\n        if (ep->b_blkno != blkno || ep->b_dev != dev ||\n            (ep->b_flags&B_INVAL))\n            continue;\n        s = splbio();\n        if (ep->b_flags&B_BUSY) {\n            ep->b_flags |= B_WANTED;\n            sleep((caddr_t)ep, PRIBIO+1);\n            splx(s);\n            goto loop;\n        }\n        if (ep->b_flags & B_DELWRI) {\n            splx(s);\n            notavail(ep);\n            bwrite(ep);\n            goto loop;\n        }\n        splx(s);\n    }\n}\n\n/*\n * Make sure all write-behind blocks on dev are flushed out.\n * (from umount and sync)\n */\nvoid\nbflush(dev)\n    register dev_t dev;\n{\n    register struct buf *bp;\n    register struct buf *flist;\n    int s;\n\nloop:\n    s = splbio();\n    for (flist = bfreelist; flist < &bfreelist[BQ_EMPTY]; flist++) {\n        for (bp = flist->av_forw; bp != flist; bp = bp->av_forw) {\n            if ((bp->b_flags & B_DELWRI) == 0)\n                continue;\n            if (dev == bp->b_dev) {\n                bp->b_flags |= B_ASYNC;\n                notavail(bp);\n                bwrite(bp);\n                splx(s);\n                goto loop;\n            }\n        }\n    }\n    splx(s);\n}\n\n/*\n * Pick up the device's error number and pass it to the user;\n * if there is an error but the number is 0 set a generalized code.\n */\nint\ngeterror (bp)\n    register struct buf *bp;\n{\n    register int error = 0;\n\n    if (bp->b_flags&B_ERROR)\n        if ((error = bp->b_error)==0)\n            return(EIO);\n    return (error);\n}\n\n/*\n * Invalidate in core blocks belonging to closed or umounted filesystem\n *\n * This is not nicely done at all - the buffer ought to be removed from the\n * hash chains & have its dev/blkno fields clobbered, but unfortunately we\n * can't do that here, as it is quite possible that the block is still\n * being used for i/o. Eventually, all disc drivers should be forced to\n * have a close routine, which ought ensure that the queue is empty, then\n * properly flush the queues. Until that happy day, this suffices for\n * correctness.                     ... kre\n */\nvoid\nbinval(dev)\n    register dev_t dev;\n{\n    register struct buf *bp;\n    register struct bufhd *hp;\n#define dp ((struct buf *)hp)\n\n    for (hp = bufhash; hp < &bufhash[BUFHSZ]; hp++)\n        for (bp = dp->b_forw; bp != dp; bp = bp->b_forw)\n            if (bp->b_dev == dev)\n                bp->b_flags |= B_INVAL;\n}\n"
  },
  {
    "path": "sys/kern/ufs_bmap.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/conf.h>\n#include <sys/dir.h>\n#include <sys/inode.h>\n#include <sys/user.h>\n#include <sys/buf.h>\n#include <sys/fs.h>\n#include <sys/mount.h>\n#include <sys/uio.h>\n\n/*\n * Bmap defines the structure of file system storage\n * by returning the physical block number on a device given the\n * inode and the logical block number in a file.\n * When convenient, it also leaves the physical\n * block number of the next block of the file in rablock\n * for use in read-ahead.\n */\ndaddr_t\nbmap(ip, bn, rwflg, flags)\n    register struct inode *ip;\n    daddr_t bn;\n    int rwflg, flags;\n{\n    register int i;\n    register struct buf *bp;\n    struct buf *nbp;\n    int j, sh;\n    daddr_t nb, *bap, ra;\n    int async = ip->i_fs->fs_flags & MNT_ASYNC;\n\n    if (bn < 0) {\n        u.u_error = EFBIG;\n        return((daddr_t)0);\n    }\n    ra = rablock = 0;\n\n    /*\n     * blocks 0..NADDR-4 are direct blocks\n     */\n    if (bn < NADDR-3) {\n        i = bn;\n        nb = ip->i_addr[i];\n        if (nb == 0) {\n            if (rwflg == B_READ || (bp = balloc(ip, flags)) == NULL)\n                return((daddr_t)-1);\n            nb = dbtofsb(bp->b_blkno);\n/*\n * directory blocks are usually the only thing written synchronously at this\n * point (so they never appear with garbage in them on the disk).  This is\n * overridden if the filesystem was mounted 'async'.\n*/\n            if (flags & B_SYNC)\n                bwrite(bp);\n            else\n                bdwrite(bp);\n            ip->i_addr[i] = nb;\n            ip->i_flag |= IUPD|ICHG;\n        }\n        if (i < NADDR-4)\n            rablock = ip->i_addr[i+1];\n        return(nb);\n    }\n\n    /*\n     * addresses NADDR-3, NADDR-2, and NADDR-1\n     * have single, double, triple indirect blocks.\n     * the first step is to determine\n     * how many levels of indirection.\n     */\n    sh = 0;\n    nb = 1;\n    bn -= NADDR-3;\n    for (j = 3;j > 0;j--) {\n        sh += NSHIFT;\n        nb <<= NSHIFT;\n        if (bn < nb)\n            break;\n        bn -= nb;\n    }\n    if (j == 0) {\n        u.u_error = EFBIG;\n        return((daddr_t)0);\n    }\n\n    /*\n     * fetch the first indirect block\n     */\n    nb = ip->i_addr[NADDR-j];\n    if (nb == 0) {\n        if (rwflg == B_READ || (bp = balloc(ip, flags | B_CLRBUF)) == NULL)\n            return((daddr_t) -1);\n        nb = dbtofsb(bp->b_blkno);\n        /*\n         * Write synchronously if requested so that indirect blocks\n         * never point at garbage.\n         */\n        if (async)\n            bdwrite(bp);\n        else\n            bwrite(bp);\n        ip->i_addr[NADDR-j] = nb;\n        ip->i_flag |= IUPD|ICHG;\n    }\n\n    /*\n     * fetch through the indirect blocks\n     */\n    for(;j <= 3;j++) {\n        bp = bread(ip->i_dev, nb);\n        if ((bp->b_flags & B_ERROR) || bp->b_resid) {\n            brelse(bp);\n            return((daddr_t)0);\n        }\n        bap = (daddr_t*) bp->b_addr;\n        sh -= NSHIFT;\n        i = (bn>>sh) & NMASK;\n        nb = bap[i];\n        /*\n         * calculate read-ahead\n         */\n        if (i < NINDIR-1)\n            ra = bap[i+1];\n        if (nb == 0) {\n            if (rwflg == B_READ || (nbp = balloc(ip, flags | B_CLRBUF)) == NULL) {\n                brelse(bp);\n                return((daddr_t) -1);\n            }\n            nb = dbtofsb(nbp->b_blkno);\n/*\n * Write synchronously so indirect blocks never point at garbage and blocks\n * in directories never contain garbage.  This check used to be based on the\n * type of inode, if it was a directory then 'sync' writes were done.  See the\n * comments earlier about filesystems being mounted 'async'.\n*/\n            if (!async && (j < 3 || (flags & B_SYNC)))\n                bwrite(nbp);\n            else\n                bdwrite(nbp);\n            bap = (daddr_t*) bp->b_addr;\n            bap[i] = nb;\n            bdwrite(bp);\n        } else\n            brelse(bp);\n    }\n    rablock = ra;\n    return(nb);\n}\n"
  },
  {
    "path": "sys/kern/ufs_dsort.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *  @(#)ufs_dsort.c 1.1 (2.10BSD Berkeley) 12/1/86\n */\n\n/*\n * generalized seek sort for disk\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/buf.h>\n#include <sys/dk.h>\n\nvoid\ndisksort (dp, bp)\n    register struct buf *dp, *bp;\n{\n    register struct buf *ap;\n    struct buf *tp;\n\n    ap = dp->b_actf;\n    if (ap == NULL) {\n        dp->b_actf = bp;\n        dp->b_actl = bp;\n        bp->av_forw = NULL;\n        return;\n    }\n    tp = NULL;\n    for (; ap != NULL; ap = ap->av_forw) {\n        if ((bp->b_flags&B_READ) && (ap->b_flags&B_READ) == 0) {\n            if (tp == NULL)\n                tp = ap;\n            break;\n        }\n        if ((bp->b_flags&B_READ) == 0 && (ap->b_flags&B_READ))\n            continue;\n        if (ap->b_cylin <= bp->b_cylin)\n            if (tp == NULL || ap->b_cylin >= tp->b_cylin)\n                tp = ap;\n    }\n    if (tp == NULL)\n        tp = dp->b_actl;\n    bp->av_forw = tp->av_forw;\n    tp->av_forw = bp;\n    if (tp == dp->b_actl)\n        dp->b_actl = bp;\n}\n\n#ifdef UCB_METER\n/*\n * Allocate iostat disk monitoring slots for a driver.  If slots already\n * allocated (*dkn >= 0) or not enough slots left to satisfy request simply\n * ignore it.\n */\nvoid\ndk_alloc (dkn, slots, name)\n    int *dkn;   /* pointer to number for iostat */\n    int slots;  /* number of iostat slots requested */\n    char *name; /* name of device */\n{\n    int i;\n    register char **np;\n    register int *up;\n\n    if (*dkn < 0 && dk_n + slots <= DK_NDRIVE) {\n        /*\n         * Allocate and initialize the slots\n         */\n        *dkn = dk_n;\n        np = &dk_name[dk_n];\n        up = &dk_unit[dk_n];\n        dk_n += slots;\n\n        for (i = 0; i < slots; i++) {\n            *np++ = name;\n            *up++ = i;\n        }\n    }\n}\n#endif /* UCB_METER */\n"
  },
  {
    "path": "sys/kern/ufs_fio.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/fs.h>\n#include <sys/inode.h>\n#include <sys/mount.h>\n#include <sys/namei.h>\n#include <sys/systm.h>\n#include <sys/stat.h>\n\n/*\n * Check mode permission on inode pointer.\n * Mode is READ, WRITE or EXEC.\n * In the case of WRITE, the\n * read-only status of the file\n * system is checked.\n * Also in WRITE, prototype text\n * segments cannot be written.\n * The mode is shifted to select\n * the owner/group/other fields.\n * The super user is granted all\n * permissions.\n */\nint\naccess (ip, mode)\n    register struct inode *ip;\n    int mode;\n{\n    register int m;\n    register gid_t *gp;\n\n    m = mode;\n    if (m == IWRITE) {\n        if (ip->i_flags & IMMUTABLE) {\n            u.u_error = EPERM;\n            return(1);\n        }\n        /*\n         * Disallow write attempts on read-only\n         * file systems; unless the file is a block\n         * or character device resident on the\n         * file system.\n         */\n        if (ip->i_fs->fs_ronly != 0) {\n            if ((ip->i_mode & IFMT) != IFCHR &&\n                (ip->i_mode & IFMT) != IFBLK) {\n                u.u_error = EROFS;\n                return (1);\n            }\n        }\n    }\n    /*\n     * If you're the super-user,\n     * you always get access.\n     */\n    if (u.u_uid == 0)\n        return (0);\n    /*\n     * Access check is based on only\n     * one of owner, group, public.\n     * If not owner, then check group.\n     * If not a member of the group, then\n     * check public access.\n     */\n    if (u.u_uid != ip->i_uid) {\n        m >>= 3;\n        gp = u.u_groups;\n        for (; gp < &u.u_groups[NGROUPS] && *gp != NOGROUP; gp++)\n            if (ip->i_gid == *gp)\n                goto found;\n        m >>= 3;\nfound:\n        ;\n    }\n    if ((ip->i_mode&m) != 0)\n        return (0);\n    u.u_error = EACCES;\n    return (1);\n}\n\n/* copied, for supervisory networking, to sys_net.c */\n/*\n * Test if the current user is the\n * super user.\n */\nint\nsuser()\n{\n    if (u.u_uid == 0) {\n        return (1);\n    }\n    u.u_error = EPERM;\n    return (0);\n}\n\n/*\n * Set the attributes on a file.  This was placed here because ufs_syscalls\n * is too large already (it will probably be split into two files eventually).\n */\nint\nufs_setattr (ip, vap)\n    register struct inode *ip;\n    register struct vattr *vap;\n{\n    int error;\n    struct  timeval atimeval, mtimeval;\n\n    if (ip->i_fs->fs_ronly) /* can't change anything on a RO fs */\n        return(EROFS);\n    if (vap->va_flags != VNOVAL) {\n        if (u.u_uid != ip->i_uid && !suser())\n            return(u.u_error);\n        if (u.u_uid == 0) {\n            if ((ip->i_flags &\n                (SF_IMMUTABLE|SF_APPEND)) && securelevel > 0)\n                return(EPERM);\n            ip->i_flags = vap->va_flags;\n        } else {\n            if (ip->i_flags & (SF_IMMUTABLE|SF_APPEND))\n                return(EPERM);\n            ip->i_flags &= SF_SETTABLE;\n            ip->i_flags |= (vap->va_flags & UF_SETTABLE);\n        }\n        ip->i_flag |= ICHG;\n        if (vap->va_flags & (IMMUTABLE|APPEND))\n            return(0);\n    }\n    if (ip->i_flags & (IMMUTABLE|APPEND))\n        return(EPERM);\n    /*\n     * Go thru the fields (other than 'flags') and update iff not VNOVAL.\n     */\n    if (vap->va_uid != (uid_t)VNOVAL || vap->va_gid != (gid_t)VNOVAL) {\n        error = chown1 (ip, vap->va_uid, vap->va_gid);\n        if (error)\n            return(error);\n    }\n    if (vap->va_size != (off_t)VNOVAL) {\n        if ((ip->i_mode & IFMT) == IFDIR)\n            return(EISDIR);\n        itrunc(ip, vap->va_size, 0);\n        if (u.u_error)\n            return(u.u_error);\n    }\n    if (vap->va_atime != (time_t)VNOVAL ||\n        vap->va_mtime != (time_t)VNOVAL) {\n        if (u.u_uid != ip->i_uid && !suser() &&\n            ((vap->va_vaflags & VA_UTIMES_NULL) == 0 ||\n             access(ip, IWRITE)))\n            return(u.u_error);\n        if (vap->va_atime != (time_t)VNOVAL &&\n            ! (ip->i_fs->fs_flags & MNT_NOATIME))\n            ip->i_flag |= IACC;\n        if (vap->va_mtime != (time_t)VNOVAL)\n            ip->i_flag |= (IUPD|ICHG);\n        atimeval.tv_sec = vap->va_atime;\n        mtimeval.tv_sec = vap->va_mtime;\n        iupdat(ip, &atimeval, &mtimeval, 1);\n    }\n    if (vap->va_mode != (mode_t)VNOVAL)\n        return(chmod1(ip, vap->va_mode));\n    return(0);\n}\n\n/*\n * Check that device is mounted somewhere.\n * Return EBUSY if mounted, 0 otherwise.\n */\nint\nufs_mountedon (dev)\n    dev_t dev;\n{\n    register struct mount *mp;\n\n    for (mp = mount; mp < &mount[NMOUNT]; mp++) {\n        if (mp->m_inodp == NULL)\n            continue;\n        if (mp->m_dev == dev)\n            return(EBUSY);\n    }\n    return(0);\n}\n"
  },
  {
    "path": "sys/kern/ufs_inode.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/inode.h>\n#include <sys/fs.h>\n#include <sys/mount.h>\n#include <sys/kernel.h>\n#include <sys/buf.h>\n#include <sys/systm.h>\n#include <sys/syslog.h>\n\n#define INOHSZ              16      /* must be power of two */\n#define INOHASH(dev,ino)    (((dev)+(ino))&(INOHSZ-1))\n\nunion ihead {                       /* inode LRU cache, stolen */\n    union  ihead *ih_head[2];\n    struct inode *ih_chain[2];\n} ihead[INOHSZ];\n\nstruct inode *ifreeh, **ifreet;\n\n/*\n * Initialize hash links for inodes\n * and build inode free list.\n */\nvoid\nihinit()\n{\n    register int i;\n    register struct inode *ip = inode;\n    register union  ihead *ih = ihead;\n\n    for (i = INOHSZ; --i >= 0; ih++) {\n        ih->ih_head[0] = ih;\n        ih->ih_head[1] = ih;\n    }\n    ifreeh = ip;\n    ifreet = &ip->i_freef;\n    ip->i_freeb = &ifreeh;\n    ip->i_forw = ip;\n    ip->i_back = ip;\n    for (i = NINODE; --i > 0; ) {\n        ++ip;\n        ip->i_forw = ip;\n        ip->i_back = ip;\n        *ifreet = ip;\n        ip->i_freeb = ifreet;\n        ifreet = &ip->i_freef;\n    }\n    ip->i_freef = NULL;\n}\n\n/*\n * Find an inode if it is incore.\n */\nstruct inode *\nifind(dev, ino)\n    register dev_t dev;\n    register ino_t ino;\n{\n    register struct inode *ip;\n    union ihead *ih;\n\n    ih = &ihead[INOHASH(dev, ino)];\n    for (ip = ih->ih_chain[0]; ip != (struct inode *)ih; ip = ip->i_forw)\n        if (ino == ip->i_number && dev == ip->i_dev)\n            return(ip);\n    return((struct inode *)NULL);\n}\n\n/*\n * Look up an inode by device,inumber.\n * If it is in core (in the inode structure),\n * honor the locking protocol.\n * If it is not in core, read it in from the\n * specified device.\n * If the inode is mounted on, perform\n * the indicated indirection.\n * In all cases, a pointer to a locked\n * inode structure is returned.\n *\n * panic: no imt -- if the mounted file\n *  system is not in the mount table.\n *  \"cannot happen\"\n */\nstruct inode *\niget(dev, fs, ino)\n    dev_t dev;\n    register struct fs *fs;\n    ino_t ino;\n{\n    register struct inode *ip;\n    union ihead *ih;\n    struct buf *bp;\n    struct dinode *dp;\nloop:\n    ih = &ihead[INOHASH(dev, ino)];\n    for (ip = ih->ih_chain[0]; ip != (struct inode *)ih; ip = ip->i_forw)\n        if (ino == ip->i_number && dev == ip->i_dev) {\n            /*\n             * Following is essentially an inline expanded\n             * copy of igrab(), expanded inline for speed,\n             * and so that the test for a mounted on inode\n             * can be deferred until after we are sure that\n             * the inode isn't busy.\n             */\n            if ((ip->i_flag&ILOCKED) != 0) {\n                ip->i_flag |= IWANT;\n                sleep((caddr_t)ip, PINOD);\n                goto loop;\n            }\n            if ((ip->i_flag&IMOUNT) != 0) {\n                register struct mount *mp;\n\n                for (mp = &mount[0]; mp < &mount[NMOUNT]; mp++)\n                    if(mp->m_inodp == ip) {\n                        dev = mp->m_dev;\n                        fs = &mp->m_filsys;\n                        ino = ROOTINO;\n                        goto loop;\n                    }\n                panic(\"no imt\");\n            }\n            if (ip->i_count == 0) {     /* ino on free list */\n                register struct inode *iq;\n\n                iq = ip->i_freef;\n                if (iq)\n                    iq->i_freeb = ip->i_freeb;\n                else\n                    ifreet = ip->i_freeb;\n                *ip->i_freeb = iq;\n                ip->i_freef = NULL;\n                ip->i_freeb = NULL;\n            }\n            ip->i_count++;\n            ip->i_flag |= ILOCKED;\n            return(ip);\n        }\n\n    ip = ifreeh;\n    if (ip == NULL) {\n        log(LOG_ERR, \"inode: table full\\n\");\n        u.u_error = ENFILE;\n        return(NULL);\n    }\n    if (ip->i_count)\n        panic(\"free inode isn't\");\n    {\n    register struct inode *iq;\n\n    iq = ip->i_freef;\n    if (iq)\n        iq->i_freeb = &ifreeh;\n    ifreeh = iq;\n    }\n    ip->i_freef = NULL;\n    ip->i_freeb = NULL;\n    /*\n     * Now to take inode off the hash chain it was on\n     * (initially, or after an iflush, it is on a \"hash chain\"\n     * consisting entirely of itself, and pointed to by no-one,\n     * but that doesn't matter), and put it on the chain for\n     * its new (ino, dev) pair\n     */\n    remque(ip);\n    insque(ip, ih);\n    ip->i_dev = dev;\n    ip->i_fs = fs;\n    ip->i_number = ino;\n    cacheinval(ip);\n    ip->i_flag = ILOCKED;\n    ip->i_count++;\n    ip->i_lastr = 0;\n    bp = bread(dev, itod(ino));\n    /*\n     * Check I/O errors\n     */\n    if ((bp->b_flags&B_ERROR) != 0) {\n        brelse(bp);\n        /*\n         * the inode doesn't contain anything useful, so it would\n         * be misleading to leave it on its hash chain.\n         * 'iput' will take care of putting it back on the free list.\n         */\n        remque(ip);\n        ip->i_forw = ip;\n        ip->i_back = ip;\n        /*\n         * we also loose its inumber, just in case (as iput\n         * doesn't do that any more) - but as it isn't on its\n         * hash chain, I doubt if this is really necessary .. kre\n         * (probably the two methods are interchangable)\n         */\n        ip->i_number = 0;\n        iput(ip);\n        return(NULL);\n    }\n    dp = (struct dinode*) bp->b_addr;\n    dp += itoo(ino);\n    ip->i_ic1 = dp->di_ic1;\n    ip->i_flags = dp->di_flags;\n    ip->i_ic2 = dp->di_ic2;\n    bcopy(dp->di_addr, ip->i_addr, NADDR * sizeof (daddr_t));\n    brelse(bp);\n    return (ip);\n}\n\n/*\n * Convert a pointer to an inode into a reference to an inode.\n *\n * This is basically the internal piece of iget (after the\n * inode pointer is located) but without the test for mounted\n * filesystems.  It is caller's responsibility to check that\n * the inode pointer is valid.\n */\nvoid\nigrab (ip)\n    register struct inode *ip;\n{\n    while ((ip->i_flag&ILOCKED) != 0) {\n        ip->i_flag |= IWANT;\n        sleep((caddr_t)ip, PINOD);\n    }\n    if (ip->i_count == 0) {     /* ino on free list */\n        register struct inode *iq;\n\n        iq = ip->i_freef;\n        if (iq)\n            iq->i_freeb = ip->i_freeb;\n        else\n            ifreet = ip->i_freeb;\n        *ip->i_freeb = iq;\n        ip->i_freef = NULL;\n        ip->i_freeb = NULL;\n    }\n    ip->i_count++;\n    ip->i_flag |= ILOCKED;\n}\n\n/*\n * Decrement reference count of\n * an inode structure.\n * On the last reference,\n * write the inode out and if necessary,\n * truncate and deallocate the file.\n */\nvoid\niput (ip)\n    register struct inode *ip;\n{\n#ifdef notnow\n    /*\n     * This code requires a lot of workarounds, you have to change\n     * lots of places to gratuitously lock just so we can unlock it.\n     * Not worth it.  -- KB\n     */\n    if ((ip->i_flag & ILOCKED) == 0)\n        panic(\"iput\");\n#endif\n    IUNLOCK(ip);\n    irele(ip);\n}\n\nvoid\nirele (ip)\n    register struct inode *ip;\n{\n    if (ip->i_count == 1) {\n        ip->i_flag |= ILOCKED;\n        if (ip->i_nlink <= 0 && ip->i_fs->fs_ronly == 0) {\n            itrunc (ip, (u_long) 0, 0);\n            ip->i_mode = 0;\n            ip->i_rdev = 0;\n            ip->i_flag |= IUPD|ICHG;\n            ifree(ip, ip->i_number);\n        }\n        IUPDAT(ip, &time, &time, 0);\n        IUNLOCK(ip);\n        ip->i_flag = 0;\n        /*\n         * Put the inode on the end of the free list.\n         * Possibly in some cases it would be better to\n         * put the inode at the head of the free list,\n         * (eg: where i_mode == 0 || i_number == 0)\n         * but I will think about that later .. kre\n         * (i_number is rarely 0 - only after an i/o error in iget,\n         * where i_mode == 0, the inode will probably be wanted\n         * again soon for an ialloc, so possibly we should keep it)\n         */\n        if (ifreeh) {\n            *ifreet = ip;\n            ip->i_freeb = ifreet;\n        } else {\n            ifreeh = ip;\n            ip->i_freeb = &ifreeh;\n        }\n        ip->i_freef = NULL;\n        ifreet = &ip->i_freef;\n    } else if (!(ip->i_flag & ILOCKED))\n        ITIMES(ip, &time, &time);\n    ip->i_count--;\n}\n\n/*\n * Check accessed and update flags on\n * an inode structure.\n * If any are on, update the inode\n * with the current time.\n * If waitfor set, then must insure\n * i/o order so wait for the write to complete.\n */\nvoid\niupdat (ip, ta, tm, waitfor)\n    struct inode *ip;\n    struct timeval *ta, *tm;\n    int waitfor;\n{\n    register struct buf *bp;\n    register struct dinode *dp;\n    register struct inode *tip = ip;\n\n    if ((tip->i_flag & (IUPD|IACC|ICHG|IMOD)) == 0)\n        return;\n    if (tip->i_fs->fs_ronly)\n        return;\n    bp = bread(tip->i_dev, itod(tip->i_number));\n    if (bp->b_flags & B_ERROR) {\n        brelse(bp);\n        return;\n    }\n    if (tip->i_flag&IACC)\n        tip->i_atime = ta->tv_sec;\n    if (tip->i_flag&IUPD)\n        tip->i_mtime = tm->tv_sec;\n    if (tip->i_flag&ICHG)\n        tip->i_ctime = time.tv_sec;\n    tip->i_flag &= ~(IUPD|IACC|ICHG|IMOD);\n    dp = (struct dinode*) bp->b_addr + itoo (tip->i_number);\n    dp->di_ic1 = tip->i_ic1;\n    dp->di_flags = tip->i_flags;\n    dp->di_ic2 = tip->i_ic2;\n    bcopy(ip->i_addr, dp->di_addr, NADDR * sizeof (daddr_t));\n    if (waitfor && ((ip->i_fs->fs_flags & MNT_ASYNC) == 0))\n        bwrite(bp);\n    else\n        bdwrite(bp);\n}\n\n#define SINGLE  0   /* index of single indirect block */\n#define DOUBLE  1   /* index of double indirect block */\n#define TRIPLE  2   /* index of triple indirect block */\n\nstatic void\ntrsingle (ip, bp, last, aflags)\n    register struct inode *ip;\n    struct buf *bp;\n    daddr_t last;\n    int aflags;\n{\n    register const daddr_t *bstart, *bstop;\n    const daddr_t *blarray = (const daddr_t*) bp->b_addr;\n\n    bstart = &blarray[NINDIR - 1];\n    bstop = &blarray[last];\n    for (; bstart > bstop; --bstart)\n        if (*bstart)\n            free (ip, *bstart);\n}\n\n/*\n * Release blocks associated with the inode ip and\n * stored in the indirect block bn.  Blocks are free'd\n * in LIFO order up to (but not including) lastbn.  If\n * level is greater than SINGLE, the block is an indirect\n * block and recursive calls to indirtrunc must be used to\n * cleanse other indirect blocks.\n *\n * NB: triple indirect blocks are untested.\n */\nvoid\nindirtrunc (ip, bn, lastbn, level, aflags)\n    struct inode *ip;\n    daddr_t bn, lastbn;\n    int level;\n    int aflags;\n{\n    register struct buf *bp;\n    daddr_t nb, last;\n    long factor;\n\n    /*\n     * Calculate index in current block of last\n     * block to be kept.  -1 indicates the entire\n     * block so we need not calculate the index.\n     */\n    switch (level) {\n    default:\n    case SINGLE:\n        factor = 1;\n        break;\n    case DOUBLE:\n        factor = NINDIR;\n        break;\n    case TRIPLE:\n        factor = NINDIR * NINDIR;\n        break;\n    }\n    last = lastbn;\n    if (lastbn > 0)\n        last = last / factor;\n    /*\n     * Get buffer of block pointers, zero those\n     * entries corresponding to blocks to be free'd,\n     * and update on disk copy first.\n     */\n    {\n        register daddr_t *bap;\n        register struct buf *cpy;\n\n        bp = bread(ip->i_dev, bn);\n        if (bp->b_flags&B_ERROR) {\n            brelse(bp);\n            return;\n        }\n        cpy = geteblk();\n        bcopy (bp->b_addr, cpy->b_addr, DEV_BSIZE);\n        bap = (daddr_t*) bp->b_addr;\n        bzero((caddr_t)&bap[last + 1],\n            (u_int)(NINDIR - (last + 1)) * sizeof(daddr_t));\n        if (aflags & B_SYNC)\n            bwrite(bp);\n        else\n            bawrite(bp);\n        bp = cpy;\n    }\n\n    /*\n     * Optimized for single indirect blocks, i.e. until a file is\n     * greater than 4K + 256K you don't have to do a mapin/mapout\n     * for every entry.  The mapin/mapout is required since free()\n     * may have to map an item in.  Have to use another routine\n     * since it requires 1K of kernel stack to get around the problem\n     * and that doesn't work well with recursion.\n     */\n    if (level == SINGLE)\n        trsingle (ip, bp, last, aflags);\n    else {\n        register daddr_t *bstart, *bstop;\n\n        bstart = (daddr_t*) bp->b_addr;\n        bstop = &bstart[last];\n        bstart += NINDIR - 1;\n        /*\n         * Recursively free totally unused blocks.\n         */\n        for (;bstart > bstop;--bstart) {\n            nb = *bstart;\n            if (nb) {\n                indirtrunc(ip,nb,(daddr_t)-1, level-1, aflags);\n                free(ip, nb);\n            }\n        }\n\n        /*\n         * Recursively free last partial block.\n         */\n        if (lastbn >= 0) {\n            nb = *bstop;\n            last = lastbn % factor;\n            if (nb != 0)\n                indirtrunc(ip, nb, last, level - 1, aflags);\n        }\n    }\n    brelse(bp);\n}\n\n/*\n * Truncate the inode ip to at most\n * length size.  Free affected disk\n * blocks -- the blocks of the file\n * are removed in reverse order.\n *\n * NB: triple indirect blocks are untested.\n */\nvoid\nitrunc (oip, length, ioflags)\n    register struct inode *oip;\n    u_long length;\n    int ioflags;\n{\n    daddr_t lastblock;\n    register int i;\n    register struct inode *ip;\n    daddr_t bn, lastiblock[NIADDR];\n    struct buf *bp;\n    int offset, level;\n    struct inode tip;\n    int aflags;\n\n    aflags = B_CLRBUF;\n    if (ioflags & IO_SYNC)\n        aflags |= B_SYNC;\n\n    /*\n     * special hack for pipes, since size for them isn't the size of\n     * the file, it's the amount currently waiting for transfer.  It's\n     * unclear that this will work, though, because pipes can (although\n     * rarely do) get bigger than MAXPIPSIZ.  Don't think it worked\n     * in V7 either, I don't really understand what's going on.\n     */\n    if (oip->i_flag & IPIPE)\n        oip->i_size = MAXPIPSIZ;\n    else if (oip->i_size == length)\n        goto updret;\n\n    /*\n     * Lengthen the size of the file. We must ensure that the\n     * last byte of the file is allocated. Since the smallest\n     * value of osize is 0, length will be at least 1.\n     */\n    if (oip->i_size < length) {\n        bn = bmap(oip, lblkno(length - 1), B_WRITE, aflags);\n        if (u.u_error || bn < 0)\n            return;\n        oip->i_size = length;\n        goto doquotaupd;\n    }\n\n    /*\n     * Calculate index into inode's block list of\n     * last direct and indirect blocks (if any)\n     * which we want to keep.  Lastblock is -1 when\n     * the file is truncated to 0.\n     */\n    lastblock = lblkno(length + DEV_BSIZE - 1) - 1;\n    lastiblock[SINGLE] = lastblock - NDADDR;\n    lastiblock[DOUBLE] = lastiblock[SINGLE] - NINDIR;\n    lastiblock[TRIPLE] = lastiblock[DOUBLE] - NINDIR * NINDIR;\n    /*\n     * Update the size of the file. If the file is not being\n     * truncated to a block boundry, the contents of the\n     * partial block following the end of the file must be\n     * zero'ed in case it ever become accessable again because\n     * of subsequent file growth.\n     */\n    offset = blkoff(length);\n    if (offset) {\n        bn = bmap(oip, lblkno(length), B_WRITE, aflags);\n        if (u.u_error || bn < 0)\n            return;\n        bp = bread(oip->i_dev, bn);\n        if (bp->b_flags & B_ERROR) {\n            u.u_error = EIO;\n            brelse(bp);\n            return;\n        }\n        bzero (bp->b_addr + offset, (u_int) (DEV_BSIZE - offset));\n        bdwrite(bp);\n    }\n    /*\n     * Update file and block pointers\n     * on disk before we start freeing blocks.\n     * If we crash before free'ing blocks below,\n     * the blocks will be returned to the free list.\n     * lastiblock values are also normalized to -1\n     * for calls to indirtrunc below.\n     */\n    tip = *oip;\n    oip->i_size = length;\n    for (level = TRIPLE; level >= SINGLE; level--)\n        if (lastiblock[level] < 0) {\n            oip->i_ib[level] = 0;\n            lastiblock[level] = -1;\n        }\n    for (i = NDADDR - 1; i > lastblock; i--)\n        oip->i_db[i] = 0;\n\n    /*\n     * Indirect blocks first.\n     */\n    ip = &tip;\n    for (level = TRIPLE; level >= SINGLE; level--) {\n        bn = ip->i_ib[level];\n        if (bn != 0) {\n            indirtrunc(ip, bn, lastiblock[level], level, aflags);\n            if (lastiblock[level] < 0) {\n                ip->i_ib[level] = 0;\n                free(ip, bn);\n            }\n        }\n        if (lastiblock[level] >= 0)\n            goto done;\n    }\n\n    /*\n     * All whole direct blocks.\n     */\n    for (i = NDADDR - 1; i > lastblock; i--) {\n        bn = ip->i_db[i];\n        if (bn == 0)\n            continue;\n        ip->i_db[i] = 0;\n        free(ip, bn);\n    }\n    if (lastblock < 0)\n        goto done;\n\ndone:\n#ifdef DIAGNOSTIC\n/* BEGIN PARANOIA */\n    for (level = SINGLE; level <= TRIPLE; level++)\n        if (ip->i_ib[level] != oip->i_ib[level])\n            panic(\"itrunc1\");\n    for (i = 0; i < NDADDR; i++)\n        if (ip->i_db[i] != oip->i_db[i])\n            panic(\"itrunc2\");\n/* END PARANOIA */\n#endif\n\ndoquotaupd:\nupdret:\n    oip->i_flag |= ICHG|IUPD;\n    iupdat(oip, &time, &time, 1);\n}\n\n/*\n * Remove any inodes in the inode cache belonging to dev.\n *\n * There should not be any active ones, return error if any are found\n * (nb: this is a user error, not a system err)\n *\n * Also, count the references to dev by block devices - this really\n * has nothing to do with the object of the procedure, but as we have\n * to scan the inode table here anyway, we might as well get the\n * extra benefit.\n *\n * this is called from sumount() when dev is being unmounted\n */\nint\niflush (dev)\n    dev_t dev;\n{\n    register struct inode *ip;\n    register int open = 0;\n\n    for (ip = inode; ip < inode+NINODE; ip++) {\n        if (ip->i_dev == dev)\n            if (ip->i_count)\n                return(-1);\n            else {\n                remque(ip);\n                ip->i_forw = ip;\n                ip->i_back = ip;\n                /*\n                 * as i_count == 0, the inode was on the free\n                 * list already, just leave it there, it will\n                 * fall off the bottom eventually. We could\n                 * perhaps move it to the head of the free\n                 * list, but as umounts are done so\n                 * infrequently, we would gain very little,\n                 * while making the code bigger.\n                 */\n            }\n        else if (ip->i_count && (ip->i_mode&IFMT)==IFBLK &&\n            ip->i_rdev == dev)\n            open++;\n    }\n    return (open);\n}\n\n/*\n * Lock an inode. If its already locked, set the WANT bit and sleep.\n */\nvoid\nilock(ip)\n    register struct inode *ip;\n{\n    ILOCK(ip);\n}\n\n/*\n * Unlock an inode.  If WANT bit is on, wakeup.\n */\nvoid\niunlock(ip)\n    register struct inode *ip;\n{\n    IUNLOCK(ip);\n}\n"
  },
  {
    "path": "sys/kern/ufs_mount.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/user.h>\n#include <sys/inode.h>\n#include <sys/fs.h>\n#include <sys/buf.h>\n#include <sys/mount.h>\n#include <sys/file.h>\n#include <sys/namei.h>\n#include <sys/conf.h>\n#include <sys/stat.h>\n#include <sys/ioctl.h>\n#include <sys/proc.h>\n\n/*\n * Common code for mount and umount.\n * Check that the user's argument is a reasonable\n * thing on which to mount, otherwise return error.\n */\nstatic int\ngetmdev (pdev, fname)\n    caddr_t fname;\n    dev_t *pdev;\n{\n    register dev_t dev;\n    register struct inode *ip;\n    struct  nameidata nd;\n    register struct nameidata *ndp = &nd;\n\n    if (!suser())\n        return (u.u_error);\n    NDINIT (ndp, LOOKUP, FOLLOW, fname);\n    ip = namei(ndp);\n    if (ip == NULL) {\n        if (u.u_error == ENOENT)\n            return (ENODEV); /* needs translation */\n        return (u.u_error);\n    }\n    if ((ip->i_mode&IFMT) != IFBLK) {\n        iput(ip);\n        return (ENOTBLK);\n    }\n    dev = (dev_t)ip->i_rdev;\n    iput(ip);\n    if (major(dev) >= nblkdev)\n        return (ENXIO);\n    *pdev = dev;\n    return (0);\n}\n\nvoid\nmount_updname (fs, on, from, lenon, lenfrom)\n    struct  fs  *fs;\n    char    *on, *from;\n    int lenon, lenfrom;\n{\n    struct  mount   *mp;\n\n    bzero (fs->fs_fsmnt, sizeof (fs->fs_fsmnt));\n    bcopy (on, fs->fs_fsmnt, sizeof (fs->fs_fsmnt) - 1);\n    mp = (struct mount*) ((int) fs - offsetof (struct mount, m_filsys));\n    bzero (mp->m_mnton, sizeof (mp->m_mnton));\n    bzero (mp->m_mntfrom, sizeof (mp->m_mntfrom));\n    bcopy (on, mp->m_mnton, lenon);\n    bcopy (from, mp->m_mntfrom, lenfrom);\n}\n\nvoid\nsmount()\n{\n    register struct a {\n        char    *fspec;\n        char    *freg;\n        int flags;\n    } *uap = (struct a *)u.u_arg;\n    dev_t dev = 0;\n    register struct inode *ip;\n    register struct fs *fs;\n    struct  nameidata nd;\n    struct  nameidata *ndp = &nd;\n    struct  mount   *mp;\n    u_int lenon, lenfrom;\n    int error = 0;\n    char    mnton[MNAMELEN], mntfrom[MNAMELEN];\n\n    u.u_error = getmdev (&dev, uap->fspec);\n    if (u.u_error)\n        return;\n    NDINIT (ndp, LOOKUP, FOLLOW, uap->freg);\n    if ((ip = namei(ndp)) == NULL)\n        return;\n    if ((ip->i_mode&IFMT) != IFDIR) {\n        error = ENOTDIR;\n        goto    cmnout;\n    }\n    copystr (uap->freg, mnton, sizeof (mnton) - 1, &lenon);\n    copystr (uap->fspec, mntfrom, sizeof (mntfrom) - 1, &lenfrom);\n\n    if (uap->flags & MNT_UPDATE) {\n        fs = ip->i_fs;\n        mp = (struct mount *)\n            ((int)fs - offsetof(struct mount, m_filsys));\n        if (ip->i_number != ROOTINO) {\n            error = EINVAL;     /* Not a mount point */\n            goto cmnout;\n        }\n        /*\n         * Check that the device passed in is the same one that is in the mount\n         * table entry for this mount point.\n         */\n        if (dev != mp->m_dev) {\n            error = EINVAL;     /* not right mount point */\n            goto cmnout;\n        }\n        /*\n         * This is where the RW to RO transformation would be done.  It is, for now,\n         * too much work to port pages of code to do (besides which most\n         * programs get very upset at having access yanked out from under them).\n         */\n        if (fs->fs_ronly == 0 && (uap->flags & MNT_RDONLY)) {\n            error = EPERM;      /* ! RW to RO updates */\n            goto cmnout;\n        }\n        /*\n         * However, going from RO to RW is easy.  Then merge in the new\n         * flags (async, sync, nodev, etc) passed in from the program.\n         */\n        if (fs->fs_ronly && ((uap->flags & MNT_RDONLY) == 0)) {\n            fs->fs_ronly = 0;\n            mp->m_flags &= ~MNT_RDONLY;\n        }\n#define _MF (MNT_NOSUID | MNT_NODEV | MNT_NOEXEC | MNT_ASYNC | MNT_SYNCHRONOUS | MNT_NOATIME)\n        mp->m_flags &= ~_MF;\n        mp->m_flags |= (uap->flags & _MF);\n#undef _MF\n        iput(ip);\n        u.u_error = 0;\n        goto updname;\n    } else {\n        /*\n         * This is where a new mount (not an update of an existing mount point) is\n         * done.\n         *\n         * The directory being mounted on can have no other references AND can not\n         * currently be a mount point.  Mount points have an inode number of (you\n         * guessed it) ROOTINO which is 2.\n         */\n        if (ip->i_count != 1 || (ip->i_number == ROOTINO)) {\n            error = EBUSY;\n            goto cmnout;\n        }\n        fs = mountfs (dev, uap->flags, ip);\n        if (fs == 0)\n            return;\n    }\n    /*\n     * Lastly, both for new mounts and updates of existing mounts, update the\n     * mounted-on and mounted-from fields.\n     */\nupdname:\n    mount_updname(fs, mnton, mntfrom, lenon, lenfrom);\n    return;\ncmnout:\n    iput(ip);\n    u.u_error = error;\n}\n\n/*\n * Mount a filesystem on the given directory inode.\n *\n * this routine has races if running twice\n */\nstruct fs *\nmountfs (dev, flags, ip)\n    dev_t dev;\n    int flags;\n    struct inode *ip;\n{\n    register struct mount *mp = 0;\n    struct buf *tp = 0;\n    register struct fs *fs;\n    register int error;\n    int ronly = flags & MNT_RDONLY;\n    int needclose = 0;\n\n    error = (*bdevsw[major(dev)].d_open) (dev,\n        ronly ? FREAD : (FREAD | FWRITE), S_IFBLK);\n    if (error)\n        goto out;\n\n    needclose = 1;\n    tp = bread (dev, SUPERB);\n    if (tp->b_flags & B_ERROR)\n        goto out;\n    for (mp = &mount[0]; mp < &mount[NMOUNT]; mp++)\n        if (mp->m_inodp != 0 && dev == mp->m_dev) {\n            mp = 0;\n            error = EBUSY;\n            needclose = 0;\n            goto out;\n        }\n    for (mp = &mount[0]; mp < &mount[NMOUNT]; mp++)\n        if (mp->m_inodp == 0)\n            goto found;\n    mp = 0;\n    error = EMFILE;     /* needs translation */\n    goto out;\nfound:\n    mp->m_inodp = ip;   /* reserve slot */\n    mp->m_dev = dev;\n    fs = &mp->m_filsys;\n    bcopy (tp->b_addr, (caddr_t)fs, sizeof(struct fs));\n    brelse (tp);\n    tp = 0;\n    if (fs->fs_magic1 != FSMAGIC1 || fs->fs_magic2 != FSMAGIC2) {\n        error = EINVAL;\n        goto out;\n    }\n    fs->fs_ronly = (ronly != 0);\n    if (ronly == 0)\n        fs->fs_fmod = 1;\n    fs->fs_ilock = 0;\n    fs->fs_flock = 0;\n    fs->fs_nbehind = 0;\n    fs->fs_lasti = 1;\n    fs->fs_flags = flags;\n    if (ip) {\n        ip->i_flag |= IMOUNT;\n        cacheinval(ip);\n        IUNLOCK(ip);\n    }\n    return (fs);\nout:\n    if (error == 0)\n        error = EIO;\n    if (ip)\n        iput(ip);\n    if (mp)\n        mp->m_inodp = 0;\n    if (tp)\n        brelse(tp);\n    if (needclose) {\n        (*bdevsw[major(dev)].d_close)(dev,\n            ronly? FREAD : FREAD|FWRITE, S_IFBLK);\n        binval(dev);\n    }\n    u.u_error = error;\n    return (0);\n}\n\nstatic int\nunmount1 (fname)\n    caddr_t fname;\n{\n    dev_t dev = 0;\n    register struct mount *mp;\n    register struct inode *ip;\n    register int error;\n    int aflag;\n\n    error = getmdev(&dev, fname);\n    if (error)\n        return (error);\n    for (mp = &mount[0]; mp < &mount[NMOUNT]; mp++)\n        if (mp->m_inodp != NULL && dev == mp->m_dev)\n            goto found;\n    return (EINVAL);\nfound:\n    nchinval (dev); /* flush the name cache */\n    aflag = mp->m_flags & MNT_ASYNC;\n    mp->m_flags &= ~MNT_ASYNC;  /* Don't want async when unmounting */\n    ufs_sync(mp);\n\n    if (iflush(dev) < 0) {\n        mp->m_flags |= aflag;\n        return (EBUSY);\n    }\n    ip = mp->m_inodp;\n    ip->i_flag &= ~IMOUNT;\n    irele(ip);\n    mp->m_inodp = 0;\n    mp->m_dev = 0;\n    (*bdevsw[major(dev)].d_close)(dev, 0, S_IFBLK);\n    binval(dev);\n    return (0);\n}\n\nvoid\numount()\n{\n    struct a {\n        char    *fspec;\n    } *uap = (struct a *)u.u_arg;\n\n    u.u_error = unmount1 (uap->fspec);\n}\n"
  },
  {
    "path": "sys/kern/ufs_namei.c",
    "content": "/*\n * Copyright (c) 1982 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/dir.h>\n#include <sys/inode.h>\n#include <sys/fs.h>\n#include <sys/mount.h>\n#include <sys/user.h>\n#include <sys/buf.h>\n#include <sys/namei.h>\n#include <sys/proc.h>\n\nint dirchk = 0;\n\n/*\n * Structures associated with name cacheing.\n */\n#define NCHHASH         16  /* size of hash table */\n\n#if ((NCHHASH)&((NCHHASH)-1)) != 0\n#define NHASH(h, i, d)  ((unsigned)((h) + (i) + 13 * (int)(d)) % (NCHHASH))\n#else\n#define NHASH(h, i, d)  ((unsigned)((h) + (i) + 13 * (int)(d)) & ((NCHHASH)-1))\n#endif\n\nunion nchash {\n    union   nchash *nch_head[2];\n    struct  namecache *nch_chain[2];\n} nchash[NCHHASH];\n\n#define nch_forw    nch_chain[0]\n#define nch_back    nch_chain[1]\n\nstruct  namecache *nchhead, **nchtail;  /* LRU chain pointers */\n\nstatic void\ndirbad (ip, offset, how)\n    struct inode *ip;\n    off_t offset;\n    char *how;\n{\n    printf (\"%s: bad dir I=%u off %ld: %s\\n\",\n        ip->i_fs->fs_fsmnt, ip->i_number, offset, how);\n}\n\n/*\n * Return buffer with contents of block \"offset\"\n * from the beginning of directory \"ip\".  If \"res\"\n * is non-zero, fill it in with a pointer to the\n * remaining space in the directory.\n */\nstatic struct buf *\nblkatoff(ip, offset, res)\n    struct inode *ip;\n    off_t offset;\n    char **res;\n{\n    daddr_t lbn = lblkno(offset);\n    register struct buf *bp;\n    daddr_t bn;\n    char *junk;\n\n    bn = bmap(ip, lbn, B_READ, 0);\n    if (u.u_error)\n        return (0);\n    if (bn == (daddr_t)-1) {\n        dirbad(ip, offset, \"hole in dir\");\n        return (0);\n    }\n    bp = bread(ip->i_dev, bn);\n    if (bp->b_flags & B_ERROR) {\n        brelse(bp);\n        return (0);\n    }\n    junk = (caddr_t) bp->b_addr;\n    if (res)\n        *res = junk + (u_int)blkoff(offset);\n    return (bp);\n}\n\n/*\n * Do consistency checking on a directory entry:\n *  record length must be multiple of 4\n *  entry must fit in rest of its DIRBLKSIZ block\n *  record must be large enough to contain entry\n *  name is not longer than MAXNAMLEN\n *  name must be as long as advertised, and null terminated\n */\nstatic int\ndirbadentry (ep, entryoffsetinblock)\n    register struct direct *ep;\n    int entryoffsetinblock;\n{\n    register int i;\n\n    if ((ep->d_reclen & 0x3) != 0 ||\n        ep->d_reclen > DIRBLKSIZ - (entryoffsetinblock & (DIRBLKSIZ - 1)) ||\n        ep->d_reclen < DIRSIZ(ep) || ep->d_namlen > MAXNAMLEN)\n        return (1);\n    for (i = 0; i < ep->d_namlen; i++)\n        if (ep->d_name[i] == '\\0')\n            return (1);\n    return (ep->d_name[i]);\n}\n\n/*\n * Convert a pathname into a pointer to a locked inode.\n * This is a very central and rather complicated routine.\n * If the file system is not maintained in a strict tree hierarchy,\n * this can result in a deadlock situation (see comments in code below).\n *\n * The flag argument is LOOKUP, CREATE, or DELETE depending on whether\n * the name is to be looked up, created, or deleted. When CREATE or\n * DELETE is specified, information usable in creating or deleteing a\n * directory entry is also calculated. If flag has LOCKPARENT or'ed\n * into it and the target of the pathname exists, namei returns both\n * the target and its parent directory locked. When creating and\n * LOCKPARENT is specified, the target may not be \".\".  When deleting\n * and LOCKPARENT is specified, the target may be \".\", but the caller\n * must check to insure it does an irele and iput instead of two iputs.\n *\n * The FOLLOW flag is set when symbolic links are to be followed\n * when they occur at the end of the name translation process.\n * Symbolic links are always followed for all other pathname\n * components other than the last.\n *\n * Name caching works as follows:\n *\n * Names found by directory scans are retained in a cache\n * for future reference.  It is managed LRU, so frequently\n * used names will hang around.  Cache is indexed by hash value\n * obtained from (ino,dev,name) where ino & dev refer to the\n * directory containing name.\n *\n * For simplicity (and economy of storage), names longer than\n * a maximum length of NCHNAMLEN are not cached; they occur\n * infrequently in any case, and are almost never of interest.\n *\n * Upon reaching the last segment of a path, if the reference\n * is for DELETE, or NOCACHE is set (rewrite), and the\n * name is located in the cache, it will be dropped.\n *\n * Overall outline of namei:\n *\n *  copy in name\n *  get starting directory\n * dirloop:\n *  check accessibility of directory\n * dirloop2:\n *  copy next component of name to ndp->ni_dent\n *  handle degenerate case where name is null string\n *  look for name in cache, if found, then if at end of path\n *    and deleting or creating, drop it, else to haveino\n *  search for name in directory, to found or notfound\n * notfound:\n *  if creating, return locked directory, leaving info on avail. slots\n *  else return error\n * found:\n *  if at end of path and deleting, return information to allow delete\n *  if at end of path and rewriting (CREATE and LOCKPARENT), lock target\n *    inode and return info to allow rewrite\n *  if .. and on mounted filesys, look in mount table for parent\n *  if not at end, add name to cache; if at end and neither creating\n *    nor deleting, add name to cache\n * haveino:\n *  if symbolic link, massage name in buffer and continue at dirloop\n *  if more components of name, do next level at dirloop\n *  return the answer as locked inode\n *\n * NOTE: (LOOKUP | LOCKPARENT) currently returns the parent inode,\n *   but unlocked.\n */\nstruct inode *\nnamei (ndp)\n    register struct nameidata *ndp;\n{\n    register char *cp;          /* pointer into pathname argument */\n/* these variables refer to things which must be freed or unlocked */\n    struct inode *dp = 0;       /* the directory we are searching */\n    struct namecache *ncp = 0;  /* cache slot for entry */\n    struct fs *fs;              /* file system that directory is in */\n    struct buf *bp = 0;         /* a buffer of directory entries */\n    struct direct *ep;          /* the current directory entry */\n    int entryoffsetinblock = 0; /* offset of ep in bp's buffer */\n/* these variables hold information about the search for a slot */\n    enum {NONE, COMPACT, FOUND} slotstatus;\n    off_t slotoffset = -1;      /* offset of area with free space */\n    int slotsize = 0;           /* size of area at slotoffset */\n    int slotfreespace = 0;      /* amount of space free in slot */\n    int slotneeded = 0;         /* size of the entry we're seeking */\n/* */\n    int numdirpasses;           /* strategy for directory search */\n    off_t endsearch;            /* offset to end directory search */\n    off_t prevoff = 0;          /* ndp->ni_offset of previous entry */\n    int nlink = 0;              /* number of symbolic links taken */\n    struct inode *pdp;          /* saved dp during symlink work */\n    register int i;\n    int error;\n    int lockparent;\n    int docache;                /* == 0 do not cache last component */\n    int makeentry;              /* != 0 if name to be added to cache */\n    unsigned hash;              /* value of name hash for entry */\n    union nchash *nhp = 0;      /* cache chain head for entry */\n    int isdotdot;               /* != 0 if current name is \"..\" */\n    int flag;                   /* op ie, LOOKUP, CREATE, or DELETE */\n    off_t enduseful;            /* pointer past last used dir slot */\n    char    path[MAXPATHLEN];   /* current path */\n\n    lockparent = ndp->ni_nameiop & LOCKPARENT;\n    docache = (ndp->ni_nameiop & NOCACHE) ^ NOCACHE;\n    flag = ndp->ni_nameiop &~ (LOCKPARENT|NOCACHE|FOLLOW);\n    if (flag == DELETE || lockparent)\n        docache = 0;\n    /*\n     * Copy the name into the buffer.\n     */\n    error = copystr (ndp->ni_dirp, path, MAXPATHLEN, (u_int*) 0);\n    if (error) {\n        u.u_error = error;\n        goto retNULL;\n    }\n\n    /*\n     * Get starting directory.\n     */\n    cp = path;\n    if (*cp == '/') {\n        while (*cp == '/')\n            cp++;\n        if ((dp = u.u_rdir) == NULL)\n            dp = rootdir;\n    } else\n        dp = u.u_cdir;\n    fs = dp->i_fs;\n    ILOCK(dp);\n    dp->i_count++;\n    ndp->ni_endoff = 0;\n\n    /*\n     * We come to dirloop to search a new directory.\n     * The directory must be locked so that it can be\n     * iput, and fs must be already set to dp->i_fs.\n     */\ndirloop:\n    /*\n     * Check accessibility of directory.\n     */\n    if ((dp->i_mode&IFMT) != IFDIR) {\n        u.u_error = ENOTDIR;\n        goto bad;\n    }\n    if (access(dp, IEXEC))\n        goto bad;\n\ndirloop2:\n    /*\n     * Copy next component of name to ndp->ni_dent.\n     */\n    hash = 0;\n    for (i = 0; *cp != 0 && *cp != '/'; cp++) {\n        if (i >= MAXNAMLEN) {\n            u.u_error = ENAMETOOLONG;\n            goto bad;\n        }\n        if (*cp & 0200)\n            if ((*cp&0377) == ('/'|0200) || flag != DELETE) {\n                u.u_error = EINVAL;\n                goto bad;\n            }\n        ndp->ni_dent.d_name[i++] = *cp;\n        hash += (unsigned char)*cp * i;\n    }\n    ndp->ni_dent.d_namlen = i;\n    ndp->ni_dent.d_name[i] = '\\0';\n    isdotdot = (i == 2 &&\n        ndp->ni_dent.d_name[0] == '.' && ndp->ni_dent.d_name[1] == '.');\n    makeentry = 1;\n    if (*cp == '\\0' && docache == 0)\n        makeentry = 0;\n\n    /*\n     * Check for degenerate name (e.g. / or \"\")\n     * which is a way of talking about a directory,\n     * e.g. like \"/.\" or \".\".\n     */\n    if (ndp->ni_dent.d_name[0] == '\\0') {\n        if (flag != LOOKUP || lockparent) {\n            u.u_error = EISDIR;\n            goto bad;\n        }\n        goto retDP;\n     }\n\n    /*\n     * We now have a segment name to search for, and a directory to search.\n     *\n     * Before tediously performing a linear scan of the directory,\n     * check the name cache to see if the directory/name pair\n     * we are looking for is known already.  We don't do this\n     * if the segment name is long, simply so the cache can avoid\n     * holding long names (which would either waste space, or\n     * add greatly to the complexity).\n     */\n    if (ndp->ni_dent.d_namlen > NCHNAMLEN) {\n        nchstats.ncs_long++;\n        makeentry = 0;\n    } else {\n        nhp = &nchash[NHASH(hash, dp->i_number, dp->i_dev)];\n        for (ncp = nhp->nch_forw; ncp != (struct namecache *)nhp;\n            ncp = ncp->nc_forw) {\n            if (ncp->nc_ino == dp->i_number &&\n                ncp->nc_dev == dp->i_dev &&\n                ncp->nc_nlen == ndp->ni_dent.d_namlen &&\n                !bcmp(ncp->nc_name, ndp->ni_dent.d_name,\n                (unsigned)ncp->nc_nlen))\n                break;\n        }\n        if (ncp == (struct namecache *)nhp) {\n            nchstats.ncs_miss++;\n            ncp = NULL;\n        } else {\n            if (ncp->nc_id != ncp->nc_ip->i_id)\n                nchstats.ncs_falsehits++;\n            else if (!makeentry)\n                nchstats.ncs_badhits++;\n            else {\n                /*\n                 * move this slot to end of LRU\n                 * chain, if not already there\n                 */\n                if (ncp->nc_nxt) {\n                    /* remove from LRU chain */\n                    *ncp->nc_prev = ncp->nc_nxt;\n                    ncp->nc_nxt->nc_prev = ncp->nc_prev;\n\n                    /* and replace at end of it */\n                    ncp->nc_nxt = NULL;\n                    ncp->nc_prev = nchtail;\n                    *nchtail = ncp;\n                    nchtail = &ncp->nc_nxt;\n                }\n\n                /*\n                 * Get the next inode in the path.\n                 * See comment above other `IUNLOCK' code for\n                 * an explaination of the locking protocol.\n                 */\n                pdp = dp;\n                if (!isdotdot || dp != u.u_rdir)\n                    dp = ncp->nc_ip;\n                if (dp == NULL)\n                    panic(\"namei: null cache ino\");\n                if (pdp == dp)\n                    dp->i_count++;\n                else if (isdotdot) {\n                    IUNLOCK(pdp);\n                    igrab(dp);\n                } else {\n                    igrab(dp);\n                    IUNLOCK(pdp);\n                }\n\n                /*\n                 * Verify that the inode that we got\n                 * did not change while we were waiting\n                 * for it to be locked.\n                 */\n                if (ncp->nc_id != ncp->nc_ip->i_id) {\n                    iput(dp);\n                    ILOCK(pdp);\n                    dp = pdp;\n                    nchstats.ncs_falsehits++;\n                } else {\n                    ndp->ni_dent.d_ino = dp->i_number;\n                    /* ni_dent.d_reclen is garbage ... */\n                    nchstats.ncs_goodhits++;\n                    goto haveino;\n                }\n            }\n\n            /*\n             * Last component and we are renaming or deleting,\n             * the cache entry is invalid, or otherwise don't\n             * want cache entry to exist.\n             */\n            /* remove from LRU chain */\n            *ncp->nc_prev = ncp->nc_nxt;\n            if (ncp->nc_nxt)\n                ncp->nc_nxt->nc_prev = ncp->nc_prev;\n            else\n                nchtail = ncp->nc_prev;\n            remque(ncp);        /* remove from hash chain */\n            /* insert at head of LRU list (first to grab) */\n            ncp->nc_nxt = nchhead;\n            ncp->nc_prev = &nchhead;\n            nchhead->nc_prev = &ncp->nc_nxt;\n            nchhead = ncp;\n            /* and make a dummy hash chain */\n            ncp->nc_forw = ncp;\n            ncp->nc_back = ncp;\n            ncp = NULL;\n        }\n    }\n\n    /*\n     * Suppress search for slots unless creating\n     * file and at end of pathname, in which case\n     * we watch for a place to put the new file in\n     * case it doesn't already exist.\n     */\n    slotstatus = FOUND;\n    if (flag == CREATE && *cp == 0) {\n        slotstatus = NONE;\n        slotfreespace = 0;\n        slotneeded = DIRSIZ(&ndp->ni_dent);\n    }\n    /*\n     * If this is the same directory that this process\n     * previously searched, pick up where we last left off.\n     * We cache only lookups as these are the most common\n     * and have the greatest payoff. Caching CREATE has little\n     * benefit as it usually must search the entire directory\n     * to determine that the entry does not exist. Caching the\n     * location of the last DELETE has not reduced profiling time\n     * and hence has been removed in the interest of simplicity.\n     */\n    if (flag != LOOKUP || dp->i_number != u.u_ncache.nc_inumber ||\n        dp->i_dev != u.u_ncache.nc_dev) {\n            ndp->ni_offset = 0;\n            numdirpasses = 1;\n    } else {\n        if (u.u_ncache.nc_prevoffset > dp->i_size)\n            u.u_ncache.nc_prevoffset = 0;\n        ndp->ni_offset = u.u_ncache.nc_prevoffset;\n        entryoffsetinblock = blkoff(ndp->ni_offset);\n        if (entryoffsetinblock != 0) {\n            bp = blkatoff(dp, ndp->ni_offset, (char **)0);\n            if (bp == 0)\n                goto bad;\n        }\n        numdirpasses = 2;\n        nchstats.ncs_2passes++;\n    }\n    endsearch = roundup(dp->i_size, DIRBLKSIZ);\n    enduseful = 0;\n\nsearchloop:\n    while (ndp->ni_offset < endsearch) {\n        /*\n         * If offset is on a block boundary,\n         * read the next directory block.\n         * Release previous if it exists.\n         */\n        if (blkoff(ndp->ni_offset) == 0) {\n            if (bp != NULL) {\n                brelse(bp);\n            }\n            bp = blkatoff(dp, ndp->ni_offset, (char **)0);\n            if (bp == 0)\n                goto bad;\n            entryoffsetinblock = 0;\n        }\n        /*\n         * If still looking for a slot, and at a DIRBLKSIZE\n         * boundary, have to start looking for free space again.\n         */\n        if (slotstatus == NONE &&\n            (entryoffsetinblock&(DIRBLKSIZ-1)) == 0) {\n            slotoffset = -1;\n            slotfreespace = 0;\n        }\n        /*\n         * Get pointer to next entry.\n         * Full validation checks are slow, so we only check\n         * enough to insure forward progress through the\n         * directory. Complete checks can be run by patching\n         * \"dirchk\" to be true.\n         */\n        ep = (struct direct*) ((caddr_t) bp->b_addr + entryoffsetinblock);\n        if (ep->d_reclen == 0 ||\n            (dirchk && dirbadentry (ep, entryoffsetinblock))) {\n            dirbad(dp, ndp->ni_offset, \"mangled entry\");\n            i = DIRBLKSIZ - (entryoffsetinblock & (DIRBLKSIZ - 1));\n            ndp->ni_offset += i;\n            entryoffsetinblock += i;\n            continue;\n        }\n\n        /*\n         * If an appropriate sized slot has not yet been found,\n         * check to see if one is available. Also accumulate space\n         * in the current block so that we can determine if\n         * compaction is viable.\n         */\n        if (slotstatus != FOUND) {\n            int size = ep->d_reclen;\n\n            if (ep->d_ino != 0)\n                size -= DIRSIZ(ep);\n            if (size > 0) {\n                if (size >= slotneeded) {\n                    slotstatus = FOUND;\n                    slotoffset = ndp->ni_offset;\n                    slotsize = ep->d_reclen;\n                } else if (slotstatus == NONE) {\n                    slotfreespace += size;\n                    if (slotoffset == -1)\n                        slotoffset = ndp->ni_offset;\n                    if (slotfreespace >= slotneeded) {\n                        slotstatus = COMPACT;\n                        slotsize = ndp->ni_offset +\n                              ep->d_reclen - slotoffset;\n                    }\n                }\n            }\n        }\n\n        /*\n         * Check for a name match.\n         */\n        if (ep->d_ino) {\n            if (ep->d_namlen == ndp->ni_dent.d_namlen &&\n                !bcmp(ndp->ni_dent.d_name, ep->d_name,\n                (unsigned)ep->d_namlen))\n                goto found;\n        }\n        prevoff = ndp->ni_offset;\n        ndp->ni_offset += ep->d_reclen;\n        entryoffsetinblock += ep->d_reclen;\n        if (ep->d_ino)\n            enduseful = ndp->ni_offset;\n    }\n/* notfound: */\n    /*\n     * If we started in the middle of the directory and failed\n     * to find our target, we must check the beginning as well.\n     */\n    if (numdirpasses == 2) {\n        numdirpasses--;\n        ndp->ni_offset = 0;\n        endsearch = u.u_ncache.nc_prevoffset;\n        goto searchloop;\n    }\n    /*\n     * If creating, and at end of pathname and current\n     * directory has not been removed, then can consider\n     * allowing file to be created.\n     */\n    if (flag == CREATE && *cp == 0 && dp->i_nlink != 0) {\n        /*\n         * Access for write is interpreted as allowing\n         * creation of files in the directory.\n         */\n        if (access(dp, IWRITE))\n            goto bad;\n        /*\n         * Return an indication of where the new directory\n         * entry should be put.  If we didn't find a slot,\n         * then set ndp->ni_count to 0 indicating that the new\n         * slot belongs at the end of the directory. If we found\n         * a slot, then the new entry can be put in the range\n         * [ndp->ni_offset .. ndp->ni_offset + ndp->ni_count)\n         */\n        if (slotstatus == NONE) {\n            ndp->ni_offset = roundup(dp->i_size, DIRBLKSIZ);\n            ndp->ni_count = 0;\n            enduseful = ndp->ni_offset;\n        } else {\n            ndp->ni_offset = slotoffset;\n            ndp->ni_count = slotsize;\n            if (enduseful < slotoffset + slotsize)\n                enduseful = slotoffset + slotsize;\n        }\n        ndp->ni_endoff = roundup(enduseful, DIRBLKSIZ);\n        dp->i_flag |= IUPD|ICHG;\n        if (bp) {\n            brelse(bp);\n        }\n        /*\n         * We return with the directory locked, so that\n         * the parameters we set up above will still be\n         * valid if we actually decide to do a direnter().\n         * We return NULL to indicate that the entry doesn't\n         * currently exist, leaving a pointer to the (locked)\n         * directory inode in ndp->ni_pdir.\n         */\n        ndp->ni_pdir = dp;\n        goto retNULL;\n    }\n    u.u_error = ENOENT;\n    goto bad;\nfound:\n    if (numdirpasses == 2)\n        nchstats.ncs_pass2++;\n    /*\n     * Check that directory length properly reflects presence\n     * of this entry.\n     */\n    if (entryoffsetinblock + DIRSIZ(ep) > dp->i_size) {\n        dirbad(dp, ndp->ni_offset, \"i_size too small\");\n        dp->i_size = entryoffsetinblock + DIRSIZ(ep);\n        dp->i_flag |= IUPD|ICHG;\n    }\n\n    /*\n     * Found component in pathname.\n     * If the final component of path name, save information\n     * in the cache as to where the entry was found.\n     */\n    if (*cp == '\\0' && flag == LOOKUP) {\n        u.u_ncache.nc_prevoffset = ndp->ni_offset &~ (DIRBLKSIZ - 1);\n        u.u_ncache.nc_inumber = dp->i_number;\n        u.u_ncache.nc_dev = dp->i_dev;\n    }\n    /*\n     * Save directory entry's inode number and reclen in ndp->ni_dent,\n     * and release directory buffer.\n     */\n    ndp->ni_dent.d_ino = ep->d_ino;\n    ndp->ni_dent.d_reclen = ep->d_reclen;\n    brelse(bp);\n    bp = NULL;\n\n    /*\n     * If deleting, and at end of pathname, return\n     * parameters which can be used to remove file.\n     * If the lockparent flag isn't set, we return only\n     * the directory (in ndp->ni_pdir), otherwise we go\n     * on and lock the inode, being careful with \".\".\n     */\n    if (flag == DELETE && *cp == 0) {\n        /*\n         * Write access to directory required to delete files.\n         */\n        if (access(dp, IWRITE))\n            goto bad;\n        ndp->ni_pdir = dp;      /* for dirremove() */\n        /*\n         * Return pointer to current entry in ndp->ni_offset,\n         * and distance past previous entry (if there\n         * is a previous entry in this block) in ndp->ni_count.\n         * Save directory inode pointer in ndp->ni_pdir for dirremove().\n         */\n        if ((ndp->ni_offset&(DIRBLKSIZ-1)) == 0)\n            ndp->ni_count = 0;\n        else\n            ndp->ni_count = ndp->ni_offset - prevoff;\n        if (lockparent) {\n            if (dp->i_number == ndp->ni_dent.d_ino)\n                dp->i_count++;\n            else {\n                dp = iget(dp->i_dev, fs, ndp->ni_dent.d_ino);\n                if (dp == NULL) {\n                    iput(ndp->ni_pdir);\n                    goto bad;\n                }\n                /*\n                 * If directory is \"sticky\", then user must own\n                 * the directory, or the file in it, else he\n                 * may not delete it (unless he's root). This\n                 * implements append-only directories.\n                 */\n                if ((ndp->ni_pdir->i_mode & ISVTX) &&\n                    u.u_uid != 0 &&\n                    u.u_uid != ndp->ni_pdir->i_uid &&\n                    dp->i_uid != u.u_uid) {\n                    iput(ndp->ni_pdir);\n                    u.u_error = EPERM;\n                    goto bad;\n                }\n            }\n        }\n        goto retDP;\n    }\n\n    /*\n     * Special handling for \"..\" allowing chdir out of mounted\n     * file system: indirect .. in root inode to reevaluate\n     * in directory file system was mounted on.\n     */\n    if (isdotdot) {\n        if (dp == u.u_rdir) {\n            ndp->ni_dent.d_ino = dp->i_number;\n            makeentry = 0;\n        } else if (ndp->ni_dent.d_ino == ROOTINO &&\n            dp->i_number == ROOTINO) {\n            register struct mount *mp;\n            register dev_t d;\n\n            d = dp->i_dev;\n            for (mp = &mount[1]; mp < &mount[NMOUNT]; mp++)\n                if (mp->m_inodp && mp->m_dev == d) {\n                    iput(dp);\n                    dp = mp->m_inodp;\n                    ILOCK(dp);\n                    dp->i_count++;\n                    fs = dp->i_fs;\n                    cp -= 2;    /* back over .. */\n                    goto dirloop2;\n                }\n        }\n    }\n\n    /*\n     * If rewriting (rename), return the inode and the\n     * information required to rewrite the present directory\n     * Must get inode of directory entry to verify it's a\n     * regular file, or empty directory.\n     */\n    if ((flag == CREATE && lockparent) && *cp == 0) {\n        if (access(dp, IWRITE))\n            goto bad;\n        ndp->ni_pdir = dp;      /* for dirrewrite() */\n        /*\n         * Careful about locking second inode.\n         * This can only occur if the target is \".\".\n         */\n        if (dp->i_number == ndp->ni_dent.d_ino) {\n            u.u_error = EISDIR;     /* XXX */\n            goto bad;\n        }\n        dp = iget(dp->i_dev, fs, ndp->ni_dent.d_ino);\n        if (dp == NULL) {\n            iput(ndp->ni_pdir);\n            goto bad;\n        }\n        goto retDP;\n    }\n\n    /*\n     * Check for symbolic link, which may require us to massage the\n     * name before we continue translation.  We do not `iput' the\n     * directory because we may need it again if the symbolic link\n     * is relative to the current directory.  Instead we save it\n     * unlocked as \"pdp\".  We must get the target inode before unlocking\n     * the directory to insure that the inode will not be removed\n     * before we get it.  We prevent deadlock by always fetching\n     * inodes from the root, moving down the directory tree. Thus\n     * when following backward pointers \"..\" we must unlock the\n     * parent directory before getting the requested directory.\n     * There is a potential race condition here if both the current\n     * and parent directories are removed before the `iget' for the\n     * inode associated with \"..\" returns.  We hope that this occurs\n     * infrequently since we cannot avoid this race condition without\n     * implementing a sophisticated deadlock detection algorithm.\n     * Note also that this simple deadlock detection scheme will not\n     * work if the file system has any hard links other than \"..\"\n     * that point backwards in the directory structure.\n     */\n    pdp = dp;\n    if (isdotdot) {\n        IUNLOCK(pdp);   /* race to get the inode */\n        dp = iget(dp->i_dev, fs, ndp->ni_dent.d_ino);\n        if (dp == NULL)\n            goto bad2;\n    } else if (dp->i_number == ndp->ni_dent.d_ino) {\n        dp->i_count++;  /* we want ourself, ie \".\" */\n    } else {\n        dp = iget(dp->i_dev, fs, ndp->ni_dent.d_ino);\n        IUNLOCK(pdp);\n        if (dp == NULL)\n            goto bad2;\n    }\n\n    /*\n     * Insert name into cache if appropriate.\n     */\n    if (makeentry) {\n        if (ncp != NULL)\n            panic(\"namei: duplicating cache\");\n        /*\n         * Free the cache slot at head of lru chain.\n         */\n        ncp = nchhead;\n        if (ncp) {\n            /* remove from lru chain */\n            *ncp->nc_prev = ncp->nc_nxt;\n            if (ncp->nc_nxt)\n                ncp->nc_nxt->nc_prev = ncp->nc_prev;\n            else\n                nchtail = ncp->nc_prev;\n            remque(ncp);        /* remove from old hash chain */\n            /* grab the inode we just found */\n            ncp->nc_ip = dp;\n            /* fill in cache info */\n            ncp->nc_ino = pdp->i_number;    /* parents inum */\n            ncp->nc_dev = pdp->i_dev;   /* & device */\n            ncp->nc_idev = dp->i_dev;   /* our device */\n            ncp->nc_id = dp->i_id;      /* identifier */\n            ncp->nc_nlen = ndp->ni_dent.d_namlen;\n            bcopy(ndp->ni_dent.d_name, ncp->nc_name,\n                (unsigned)ncp->nc_nlen);\n            /* link at end of lru chain */\n            ncp->nc_nxt = NULL;\n            ncp->nc_prev = nchtail;\n            *nchtail = ncp;\n            nchtail = &ncp->nc_nxt;\n            /* and insert on hash chain */\n            insque(ncp, nhp);\n        }\n    }\n\nhaveino:\n    fs = dp->i_fs;\n\n    /*\n     * Check for symbolic link\n     */\n    if ((dp->i_mode & IFMT) == IFLNK &&\n        ((ndp->ni_nameiop & FOLLOW) || *cp == '/')) {\n        u_int pathlen = strlen(cp) + 1;\n\n        if (dp->i_size + pathlen >= MAXPATHLEN - 1) {\n            u.u_error = ENAMETOOLONG;\n            goto bad2;\n        }\n        if (++nlink > MAXSYMLINKS) {\n            u.u_error = ELOOP;\n            goto bad2;\n        }\n\n        bp = bread(dp->i_dev, bmap(dp, (daddr_t)0, B_READ, 0));\n        if (bp->b_flags & B_ERROR) {\n            brelse(bp);\n            bp = NULL;\n            goto bad2;\n        }\n        /*\n         * Shift the rest of path further down the buffer, then\n         * copy link path into the first part of the buffer.\n         */\n        bcopy(cp, path + (u_int)dp->i_size, pathlen);\n        bcopy(bp->b_addr, path, (u_int)dp->i_size);\n        brelse(bp);\n        bp = NULL;\n        cp = path;\n        iput(dp);\n        if (*cp == '/') {\n            irele(pdp);\n            while (*cp == '/')\n                cp++;\n            if ((dp = u.u_rdir) == NULL)\n                dp = rootdir;\n            ILOCK(dp);\n            dp->i_count++;\n        } else {\n            dp = pdp;\n            ILOCK(dp);\n        }\n        fs = dp->i_fs;\n        goto dirloop;\n    }\n\n    /*\n     * Not a symbolic link.  If more pathname,\n     * continue at next component, else return.\n     */\n    if (*cp == '/') {\n        while (*cp == '/')\n            cp++;\n        irele(pdp);\n        goto dirloop;\n    }\n    if (lockparent)\n        ndp->ni_pdir = pdp;\n    else\n        irele(pdp);\nretDP:\n    ndp->ni_ip = dp;\n    return (dp);\n\nbad2:\n    irele(pdp);\nbad:\n    if (bp) {\n        brelse(bp);\n    }\n    if (dp)\n        iput(dp);\nretNULL:\n    ndp->ni_ip = NULL;\n    return (NULL);\n}\n\n/*\n * Write a directory entry after a call to namei, using the parameters\n * which it left in the u. area.  The argument ip is the inode which\n * the new directory entry will refer to.  The u. area field ndp->ni_pdir is\n * a pointer to the directory to be written, which was left locked by\n * namei.  Remaining parameters (ndp->ni_offset, ndp->ni_count) indicate\n * how the space for the new entry is to be gotten.\n */\nint\ndirenter(ip, ndp)\n    struct inode *ip;\n    register struct nameidata *ndp;\n{\n    register struct direct *ep, *nep;\n    register struct inode *dp = ndp->ni_pdir;\n    struct buf *bp;\n    int loc, spacefree, error = 0;\n    u_int dsize;\n    int newentrysize;\n    char *dirbuf;\n\n    ndp->ni_dent.d_ino = ip->i_number;\n    newentrysize = DIRSIZ(&ndp->ni_dent);\n    if (ndp->ni_count == 0) {\n        /*\n         * If ndp->ni_count is 0, then namei could find no space in the\n         * directory. In this case ndp->ni_offset will be on a directory\n         * block boundary and we will write the new entry into a fresh\n         * block.\n         */\n        if (ndp->ni_offset&(DIRBLKSIZ-1))\n            panic(\"wdir: newblk\");\n        ndp->ni_dent.d_reclen = DIRBLKSIZ;\n        error = rdwri (UIO_WRITE, dp, (caddr_t)&ndp->ni_dent,\n                newentrysize, ndp->ni_offset,\n                IO_UNIT|IO_SYNC, (int *)0);\n        dp->i_size = roundup(dp->i_size, DIRBLKSIZ);\n        iput(dp);\n        return (error);\n    }\n\n    /*\n     * If ndp->ni_count is non-zero, then namei found space for the new\n     * entry in the range ndp->ni_offset to ndp->ni_offset + ndp->ni_count.\n     * in the directory.  To use this space, we may have to compact\n     * the entries located there, by copying them together towards\n     * the beginning of the block, leaving the free space in\n     * one usable chunk at the end.\n     */\n\n    /*\n     * Increase size of directory if entry eats into new space.\n     * This should never push the size past a new multiple of\n     * DIRBLKSIZE.\n     *\n     * N.B. - THIS IS AN ARTIFACT OF 4.2 AND SHOULD NEVER HAPPEN.\n     */\n    if (ndp->ni_offset + ndp->ni_count > dp->i_size)\n        dp->i_size = ndp->ni_offset + ndp->ni_count;\n    /*\n     * Get the block containing the space for the new directory\n     * entry.  Should return error by result instead of u.u_error.\n     */\n    bp = blkatoff(dp, ndp->ni_offset, (char **)&dirbuf);\n    if (bp == 0) {\n        iput(dp);\n        return (u.u_error);\n    }\n    /*\n     * Find space for the new entry.  In the simple case, the\n     * entry at offset base will have the space.  If it does\n     * not, then namei arranged that compacting the region\n     * ndp->ni_offset to ndp->ni_offset+ndp->ni_count would yield the space.\n     */\n    ep = (struct direct *)dirbuf;\n    dsize = DIRSIZ(ep);\n    spacefree = ep->d_reclen - dsize;\n    for (loc = ep->d_reclen; loc < ndp->ni_count; ) {\n        nep = (struct direct *)(dirbuf + loc);\n        if (ep->d_ino) {\n            /* trim the existing slot */\n            ep->d_reclen = dsize;\n            ep = (struct direct *)((char *)ep + dsize);\n        } else {\n            /* overwrite; nothing there; header is ours */\n            spacefree += dsize;\n        }\n        dsize = DIRSIZ(nep);\n        spacefree += nep->d_reclen - dsize;\n        loc += nep->d_reclen;\n        bcopy((caddr_t)nep, (caddr_t)ep, dsize);\n    }\n    /*\n     * Update the pointer fields in the previous entry (if any),\n     * copy in the new entry, and write out the block.\n     */\n    if (ep->d_ino == 0) {\n        if (spacefree + dsize < newentrysize)\n            panic(\"wdir: compact1\");\n        ndp->ni_dent.d_reclen = spacefree + dsize;\n    } else {\n        if (spacefree < newentrysize)\n            panic(\"wdir: compact2\");\n        ndp->ni_dent.d_reclen = spacefree;\n        ep->d_reclen = dsize;\n        ep = (struct direct *)((char *)ep + dsize);\n    }\n    bcopy((caddr_t)&ndp->ni_dent, (caddr_t)ep, (u_int)newentrysize);\n    bwrite(bp);\n    dp->i_flag |= IUPD|ICHG;\n    if (ndp->ni_endoff && ndp->ni_endoff < dp->i_size)\n        itrunc(dp, (u_long)ndp->ni_endoff, 0);\n    iput(dp);\n    return (error);\n}\n\n/*\n * Remove a directory entry after a call to namei, using the\n * parameters which it left in the u. area.  The u. entry\n * ni_offset contains the offset into the directory of the\n * entry to be eliminated.  The ni_count field contains the\n * size of the previous record in the directory.  If this\n * is 0, the first entry is being deleted, so we need only\n * zero the inode number to mark the entry as free.  If the\n * entry isn't the first in the directory, we must reclaim\n * the space of the now empty record by adding the record size\n * to the size of the previous entry.\n */\nint\ndirremove (ndp)\n    register struct nameidata *ndp;\n{\n    register struct inode *dp = ndp->ni_pdir;\n    register struct buf *bp;\n    struct direct *ep;\n\n    if (ndp->ni_count == 0) {\n        /*\n         * First entry in block: set d_ino to zero.\n         */\n        ndp->ni_dent.d_ino = 0;\n        (void) rdwri (UIO_WRITE, dp, (caddr_t) &ndp->ni_dent,\n                (int) DIRSIZ(&ndp->ni_dent), ndp->ni_offset,\n                IO_UNIT | IO_SYNC, (int*) 0);\n    } else {\n        /*\n         * Collapse new free space into previous entry.\n         */\n        bp = blkatoff(dp, ndp->ni_offset - ndp->ni_count, (char **)&ep);\n        if (bp == 0)\n            return (0);\n        ep->d_reclen += ndp->ni_dent.d_reclen;\n        bwrite(bp);\n        dp->i_flag |= IUPD|ICHG;\n    }\n    return (1);\n}\n\n/*\n * Rewrite an existing directory entry to point at the inode\n * supplied.  The parameters describing the directory entry are\n * set up by a call to namei.\n */\nvoid\ndirrewrite(dp, ip, ndp)\n    register struct inode *dp;\n    struct inode *ip;\n    register struct nameidata *ndp;\n{\n    ndp->ni_dent.d_ino = ip->i_number;\n    u.u_error = rdwri (UIO_WRITE, dp, (caddr_t) &ndp->ni_dent,\n            (int) DIRSIZ(&ndp->ni_dent), ndp->ni_offset,\n            IO_UNIT | IO_SYNC, (int*) 0);\n    iput(dp);\n}\n\n/*\n * Check if a directory is empty or not.\n * Inode supplied must be locked.\n *\n * Using a struct dirtemplate here is not precisely\n * what we want, but better than using a struct direct.\n *\n * NB: does not handle corrupted directories.\n */\nint\ndirempty (ip, parentino)\n    register struct inode *ip;\n    ino_t parentino;\n{\n    register off_t off;\n    struct dirtemplate dbuf;\n    register struct direct *dp = (struct direct *)&dbuf;\n    int error, count;\n#define MINDIRSIZ (sizeof (struct dirtemplate) / 2)\n\n    for (off = 0; off < ip->i_size; off += dp->d_reclen) {\n        error = rdwri (UIO_READ, ip, (caddr_t) dp, MINDIRSIZ,\n            off, IO_UNIT, &count);\n        /*\n         * Since we read MINDIRSIZ, residual must\n         * be 0 unless we're at end of file.\n         */\n        if (error || count != 0)\n            return (0);\n        /* avoid infinite loops */\n        if (dp->d_reclen == 0)\n            return (0);\n        /* skip empty entries */\n        if (dp->d_ino == 0)\n            continue;\n        /* accept only \".\" and \"..\" */\n        if (dp->d_namlen > 2)\n            return (0);\n        if (dp->d_name[0] != '.')\n            return (0);\n        /*\n         * At this point d_namlen must be 1 or 2.\n         * 1 implies \".\", 2 implies \"..\" if second\n         * char is also \".\"\n         */\n        if (dp->d_namlen == 1)\n            continue;\n        if (dp->d_name[1] == '.' && dp->d_ino == parentino)\n            continue;\n        return (0);\n    }\n    return (1);\n}\n\n/*\n * Check if source directory is in the path of the target directory.\n * Target is supplied locked, source is unlocked.\n * The target is always iput() before returning.\n */\nint\ncheckpath (source, target)\n    struct inode *source, *target;\n{\n    struct dirtemplate dirbuf;\n    register struct inode *ip;\n    register int error = 0;\n\n    ip = target;\n    if (ip->i_number == source->i_number) {\n        error = EEXIST;\n        goto out;\n    }\n    if (ip->i_number == ROOTINO)\n        goto out;\n\n    for (;;) {\n        if ((ip->i_mode&IFMT) != IFDIR) {\n            error = ENOTDIR;\n            break;\n        }\n        error = rdwri (UIO_READ, ip, (caddr_t) &dirbuf,\n                sizeof(struct dirtemplate), (off_t) 0,\n                IO_UNIT, (int*) 0);\n        if (error != 0)\n            break;\n        if (dirbuf.dotdot_namlen != 2 ||\n            dirbuf.dotdot_name[0] != '.' ||\n            dirbuf.dotdot_name[1] != '.') {\n            error = ENOTDIR;\n            break;\n        }\n        if (dirbuf.dotdot_ino == source->i_number) {\n            error = EINVAL;\n            break;\n        }\n        if (dirbuf.dotdot_ino == ROOTINO)\n            break;\n        iput(ip);\n        ip = iget(ip->i_dev, ip->i_fs, dirbuf.dotdot_ino);\n        if (ip == NULL) {\n            error = u.u_error;\n            break;\n        }\n    }\n\nout:\n    if (error == ENOTDIR)\n        printf(\"checkpath: .. !dir\\n\");\n    if (ip != NULL)\n        iput(ip);\n    return (error);\n}\n\n/*\n * Name cache initialization, from main() when we are booting\n */\nvoid\nnchinit()\n{\n    register union nchash *nchp;\n    register struct namecache *ncp;\n\n    nchhead = 0;\n    nchtail = &nchhead;\n    for (ncp = namecache; ncp < &namecache[NNAMECACHE]; ncp++) {\n        ncp->nc_forw = ncp;         /* hash chain */\n        ncp->nc_back = ncp;\n        ncp->nc_nxt = NULL;         /* lru chain */\n        *nchtail = ncp;\n        ncp->nc_prev = nchtail;\n        nchtail = &ncp->nc_nxt;\n        /* all else is zero already */\n    }\n    for (nchp = nchash; nchp < &nchash[NCHHASH]; nchp++) {\n        nchp->nch_head[0] = nchp;\n        nchp->nch_head[1] = nchp;\n    }\n}\n\n/*\n * Cache flush, called when filesys is umounted to\n * remove entries that would now be invalid\n *\n * The line \"nxtcp = nchhead\" near the end is to avoid potential problems\n * if the cache lru chain is modified while we are dumping the\n * inode.  This makes the algorithm O(n^2), but do you think I care?\n */\nvoid\nnchinval (dev)\n    register dev_t dev;\n{\n    register struct namecache *ncp, *nxtcp;\n\n    for (ncp = nchhead; ncp; ncp = nxtcp) {\n        nxtcp = ncp->nc_nxt;\n        if (ncp->nc_ip == NULL ||\n            (ncp->nc_idev != dev && ncp->nc_dev != dev))\n            continue;\n        /* free the resources we had */\n        ncp->nc_idev = NODEV;\n        ncp->nc_dev = NODEV;\n        ncp->nc_id = NULL;\n        ncp->nc_ino = 0;\n        ncp->nc_ip = NULL;\n        remque(ncp);            /* remove entry from its hash chain */\n        ncp->nc_forw = ncp;     /* and make a dummy one */\n        ncp->nc_back = ncp;\n        /* delete this entry from LRU chain */\n        *ncp->nc_prev = nxtcp;\n        if (nxtcp)\n            nxtcp->nc_prev = ncp->nc_prev;\n        else\n            nchtail = ncp->nc_prev;\n        /* cause rescan of list, it may have altered */\n        nxtcp = nchhead;\n        /* put the now-free entry at head of LRU */\n        ncp->nc_nxt = nxtcp;\n        ncp->nc_prev = &nchhead;\n        nxtcp->nc_prev = &ncp->nc_nxt;\n        nchhead = ncp;\n    }\n}\n\n/*\n * Name cache invalidation of all entries.\n */\nvoid\ncinvalall()\n{\n    register struct namecache *ncp, *encp = &namecache[NNAMECACHE];\n\n    for (ncp = namecache; ncp < encp; ncp++)\n        ncp->nc_id = 0;\n}\n"
  },
  {
    "path": "sys/kern/ufs_subr.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/fs.h>\n#include <sys/inode.h>\n#include <sys/buf.h>\n#include <sys/mount.h>\n#include <sys/kernel.h>\n#include <sys/systm.h>\n\nint updlock;        /* lock for sync */\n\n/*\n * Go through the mount table looking for filesystems which have been modified.\n * For each \"dirty\" filesystem call 'ufs_sync' to flush changed inodes, data\n * blocks and the superblock to disc.\n */\nvoid\nsync()\n{\n    register struct mount *mp;\n    register struct fs *fs;\n    int async;\n\n    if (updlock)\n        return;\n    updlock++;\n    for (mp = &mount[0]; mp < &mount[NMOUNT]; mp++) {\n        if (mp->m_inodp == NULL || mp->m_dev == NODEV)\n            continue;\n        fs = &mp->m_filsys;\n        if (fs->fs_fmod == 0 || fs->fs_ilock || fs->fs_flock)\n            continue;\n        async = mp->m_flags & MNT_ASYNC;\n        mp->m_flags &= ~MNT_ASYNC;\n        ufs_sync(mp);\n        mp->m_flags |= async;\n    }\n    updlock = 0;\n}\n\n/*\n * Flush all the blocks associated with an inode.\n * There are two strategies based on the size of the file;\n * large files are those with more than NBUF/2 blocks.\n * Large files\n *  Walk through the buffer pool and push any dirty pages\n *  associated with the device on which the file resides.\n * Small files\n *  Look up each block in the file to see if it is in the\n *  buffer pool writing any that are found to disk.\n *  Note that we make a more stringent check of\n *  writing out any block in the buffer pool that may\n *  overlap the inode. This brings the inode up to\n *  date with recent mods to the cooked device.\n */\nvoid\nsyncip(ip)\n    struct inode *ip;\n{\n    register struct buf *bp;\n    register struct buf *lastbufp;\n    long lbn, lastlbn;\n    register int s;\n    daddr_t blkno;\n\n    lastlbn = howmany(ip->i_size, DEV_BSIZE);\n    if (lastlbn < NBUF / 2) {\n        for (lbn = 0; lbn < lastlbn; lbn++) {\n            blkno = fsbtodb(bmap(ip, lbn, B_READ, 0));\n            blkflush(ip->i_dev, blkno);\n        }\n    } else {\n        lastbufp = &buf[NBUF];\n        for (bp = buf; bp < lastbufp; bp++) {\n            if (bp->b_dev != ip->i_dev ||\n                (bp->b_flags & B_DELWRI) == 0)\n                continue;\n            s = splbio();\n            if (bp->b_flags & B_BUSY) {\n                bp->b_flags |= B_WANTED;\n                sleep((caddr_t)bp, PRIBIO+1);\n                splx(s);\n                bp--;\n                continue;\n            }\n            splx(s);\n            notavail(bp);\n            bwrite(bp);\n        }\n    }\n    ip->i_flag |= ICHG;\n    iupdat(ip, &time, &time, 1);\n}\n\n/*\n * Check that a specified block number is in range.\n */\nint\nbadblock (fp, bn)\n    register struct fs *fp;\n    daddr_t bn;\n{\n    if (bn < fp->fs_isize || bn >= fp->fs_fsize) {\n        printf(\"bad block %D, \",bn);\n        fserr(fp, \"bad block\");\n        return (1);\n    }\n    return (0);\n}\n\n/*\n * Getfs maps a device number into a pointer to the incore super block.\n *\n * The algorithm is a linear search through the mount table. A\n * consistency check of the super block magic number is performed.\n *\n * panic: no fs -- the device is not mounted.\n *  this \"cannot happen\"\n */\nstruct fs *\ngetfs(dev)\n    dev_t dev;\n{\n    register struct mount *mp;\n    register struct fs *fs;\n\n    for (mp = &mount[0]; mp < &mount[NMOUNT]; mp++) {\n        if (mp->m_inodp == NULL || mp->m_dev != dev)\n            continue;\n        fs = &mp->m_filsys;\n        if (fs->fs_nfree > NICFREE || fs->fs_ninode > NICINOD) {\n            fserr(fs, \"bad count\");\n            fs->fs_nfree = fs->fs_ninode = 0;\n        }\n        return(fs);\n    }\n    printf(\"no fs on dev (%u,%u)\\n\", major(dev), minor(dev));\n    return((struct fs *) NULL);\n}\n"
  },
  {
    "path": "sys/kern/ufs_syscalls.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/systm.h>\n#include <sys/user.h>\n#include <sys/inode.h>\n#include <sys/namei.h>\n#include <sys/fs.h>\n#include <sys/file.h>\n#include <sys/stat.h>\n#include <sys/kernel.h>\n#include <sys/proc.h>\n\n/*\n * Common routine for chroot and chdir.\n */\nstatic void\nchdirec(ipp)\n    register struct inode **ipp;\n{\n    register struct inode *ip;\n    struct a {\n        char    *fname;\n    } *uap = (struct a *)u.u_arg;\n    struct  nameidata nd;\n    register struct nameidata *ndp = &nd;\n\n    NDINIT (ndp, LOOKUP, FOLLOW, uap->fname);\n    ip = namei(ndp);\n    if (ip == NULL)\n        return;\n    if ((ip->i_mode&IFMT) != IFDIR) {\n        u.u_error = ENOTDIR;\n        goto bad;\n    }\n    if (access(ip, IEXEC))\n        goto bad;\n    iunlock(ip);\n    if (*ipp)\n        irele(*ipp);\n    *ipp = ip;\n    return;\n\nbad:\n    iput(ip);\n}\n\n/*\n * Change current working directory (``.'').\n */\nvoid\nchdir()\n{\n    chdirec (&u.u_cdir);\n}\n\nvoid\nfchdir()\n{\n    register struct a {\n        int     fd;\n    } *uap = (struct a *)u.u_arg;\n    register struct inode *ip;\n\n    ip = getinode (uap->fd);\n    if (ip == NULL)\n        return;\n    ilock(ip);\n    if ((ip->i_mode & IFMT) != IFDIR) {\n        u.u_error = ENOTDIR;\n        goto bad;\n    }\n    if (access (ip, IEXEC))\n        goto bad;\n    iunlock(ip);\n    ip->i_count++;\n    irele(u.u_cdir);\n    u.u_cdir = ip;\n    return;\nbad:\n    iunlock(ip);\n    return;\n}\n\n/*\n * Change notion of root (``/'') directory.\n */\nvoid\nchroot()\n{\n    if (suser())\n        chdirec (&u.u_rdir);\n}\n\n/*\n * Check permissions, allocate an open file structure,\n * and call the device open routine if any.\n */\nstatic int\ncopen (mode, cmode, fname)\n    int mode;\n    int cmode;\n    caddr_t fname;\n{\n    register struct inode *ip;\n    register struct file *fp;\n    struct  nameidata nd;\n    register struct nameidata *ndp = &nd;\n    int indx, type, flags, error;\n\n    if (! fname)\n        fname = \"\";\n//printf (\"copen (mode=%#o, cmode=%#o, fname=%#x '%s')\\n\", mode, cmode, fname, fname);\n    fp = falloc();\n    if (fp == NULL) {\n//printf (\"copen: falloc failed, errno=%d\\n\", u.u_error);\n        return(u.u_error);  /* XXX */\n    }\n    flags = FFLAGS(mode);   /* convert from open to kernel flags */\n    fp->f_flag = flags & FMASK;\n    fp->f_type = DTYPE_INODE;\n    cmode &= 077777 & ~ISVTX;\n    indx = u.u_rval;\n    u.u_dupfd = -indx - 1;\n    NDINIT (ndp, LOOKUP, FOLLOW, fname);\n\n    /*\n     * ENODEV is returned by the 'fdopen()' routine - see the comments in that\n     * routine for details about the hack being used.\n     *\n     * ENXIO only comes out of the 'portal fs' code (which 2.11BSD does not have).\n     * It probably should have been removed during the port of the 'file descriptor\n     * driver' since it's a \"can not happen\" event.\n     *\n     * u.u_dupfd is used because there the space in the proc structure is at a\n     * premium in 2.11 while space in the u structure is relatively free.  Also\n     * there were more unused (pad) fields available in 'u' as compared to 'proc'.\n     */\n    error = vn_open(ndp, flags, cmode);\n    if (error) {\n//printf (\"copen: vn_open failed, errno=%d\\n\", error);\n        fp->f_count = 0;\n        if ((error == ENODEV || error == ENXIO) &&\n            u.u_dupfd >= 0 &&\n            (error = dupfdopen(indx,u.u_dupfd,flags,error) == 0)) {\n            u.u_rval = indx;\n            return(0);\n        }\n        u.u_ofile[indx] = NULL;\n        return(error);\n    }\n    ip = ndp->ni_ip;\n    u.u_dupfd = 0;\n\n    fp->f_data = (caddr_t)ip;\n\n    if (flags & (O_EXLOCK | O_SHLOCK)) {\n        if (flags & O_EXLOCK)\n            type = LOCK_EX;\n        else\n            type = LOCK_SH;\n        if (flags & FNONBLOCK)\n            type |= LOCK_NB;\n        error = ino_lock(fp, type);\n        if (error) {\n//printf (\"copen: ino_lock failed, errno=%d\\n\", error);\n            closef(fp);\n            u.u_ofile[indx] = NULL;\n        }\n    }\n//printf (\"copen returned errno=%d\\n\", error);\n    return(error);\n}\n\n/*\n * Open system call.\n */\nvoid\nopen()\n{\n    register struct a {\n        char    *fname;\n        int     mode;\n        int     crtmode;\n    } *uap = (struct a *) u.u_arg;\n\n    u.u_error = copen (uap->mode, uap->crtmode, uap->fname);\n}\n\n/*\n * Mknod system call\n */\nvoid\nmknod()\n{\n    register struct inode *ip;\n    register struct a {\n        char    *fname;\n        int     fmode;\n        int     dev;\n    } *uap = (struct a *)u.u_arg;\n    struct  nameidata nd;\n    register struct nameidata *ndp = &nd;\n\n    if (! suser())\n        return;\n    NDINIT (ndp, CREATE, NOFOLLOW, uap->fname);\n    ip = namei(ndp);\n    if (ip != NULL) {\n        u.u_error = EEXIST;\n        goto out;\n    }\n    if (u.u_error)\n        return;\n    ip = maknode (uap->fmode, ndp);\n    if (ip == NULL)\n        return;\n    switch (ip->i_mode & IFMT) {\n\n    case IFMT:  /* used by badsect to flag bad sectors */\n    case IFCHR:\n    case IFBLK:\n        if (uap->dev) {\n            /*\n             * Want to be able to use this to make badblock\n             * inodes, so don't truncate the dev number.\n             */\n            ip->i_rdev = uap->dev;\n            ip->i_dummy = 0;\n            ip->i_flag |= IACC|IUPD|ICHG;\n        }\n    }\nout:\n    iput(ip);\n}\n\n/*\n * link system call\n */\nvoid\nlink()\n{\n    register struct inode *ip, *xp;\n    register struct a {\n        char    *target;\n        char    *linkname;\n    } *uap = (struct a *)u.u_arg;\n    struct  nameidata nd;\n    register struct nameidata *ndp = &nd;\n\n    NDINIT (ndp, LOOKUP, FOLLOW, uap->target);\n    ip = namei(ndp);    /* well, this routine is doomed anyhow */\n    if (ip == NULL)\n        return;\n    if ((ip->i_mode&IFMT) == IFDIR && !suser()) {\n        iput(ip);\n        return;\n    }\n    if (ip->i_flags & (IMMUTABLE|APPEND)) {\n        u.u_error = EPERM;\n        iput(ip);\n        return;\n    }\n    ip->i_nlink++;\n    ip->i_flag |= ICHG;\n    iupdat(ip, &time, &time, 1);\n    iunlock(ip);\n    ndp->ni_nameiop = CREATE;\n    ndp->ni_dirp = (caddr_t)uap->linkname;\n    xp = namei(ndp);\n    if (xp != NULL) {\n        u.u_error = EEXIST;\n        iput(xp);\n        goto out;\n    }\n    if (u.u_error)\n        goto out;\n    if (ndp->ni_pdir->i_dev != ip->i_dev) {\n        iput(ndp->ni_pdir);\n        u.u_error = EXDEV;\n        goto out;\n    }\n    u.u_error = direnter(ip, ndp);\nout:\n    if (u.u_error) {\n        ip->i_nlink--;\n        ip->i_flag |= ICHG;\n    }\n    irele(ip);\n}\n\n/*\n * symlink -- make a symbolic link\n */\nvoid\nsymlink()\n{\n    register struct a {\n        char    *target;\n        char    *linkname;\n    } *uap = (struct a *)u.u_arg;\n    register struct inode *ip;\n    char *tp;\n    int c, nc;\n    struct  nameidata nd;\n    register struct nameidata *ndp = &nd;\n\n    tp = uap->target;\n    nc = 0;\n    for (;;) {\n        if (baduaddr (tp)) {\n            u.u_error = EFAULT;\n            return;\n        }\n        c = (u_char) *tp;\n        if (c == 0)\n            break;\n        tp++;\n        nc++;\n    }\n    NDINIT (ndp, CREATE, NOFOLLOW, uap->linkname);\n    ip = namei(ndp);\n    if (ip) {\n        iput(ip);\n        u.u_error = EEXIST;\n        return;\n    }\n    if (u.u_error)\n        return;\n    ip = maknode (IFLNK | 0777, ndp);\n    if (ip == NULL)\n        return;\n    u.u_error = rdwri (UIO_WRITE, ip, uap->target, nc, (off_t) 0,\n                IO_UNIT, (int*) 0);\n    /* handle u.u_error != 0 */\n    iput(ip);\n}\n\n/*\n * Unlink system call.\n * Hard to avoid races here, especially\n * in unlinking directories.\n */\nvoid\nunlink()\n{\n    register struct a {\n        char    *fname;\n    } *uap = (struct a *)u.u_arg;\n    register struct inode *ip, *dp;\n    struct  nameidata nd;\n    register struct nameidata *ndp = &nd;\n\n    NDINIT (ndp, DELETE, LOCKPARENT, uap->fname);\n    ip = namei(ndp);\n    if (ip == NULL)\n        return;\n    dp = ndp->ni_pdir;\n    if ((ip->i_mode&IFMT) == IFDIR && !suser())\n        goto out;\n    /*\n     * Don't unlink a mounted file.\n     */\n    if (ip->i_dev != dp->i_dev) {\n        u.u_error = EBUSY;\n        goto out;\n    }\n    if ((ip->i_flags & (IMMUTABLE|APPEND)) || (dp->i_flags & APPEND)) {\n        u.u_error = EPERM;\n        goto out;\n    }\n    if (dirremove(ndp)) {\n        ip->i_nlink--;\n        ip->i_flag |= ICHG;\n    }\nout:\n    if (dp == ip)\n        irele(ip);\n    else\n        iput(ip);\n    iput(dp);\n}\n\n/*\n * Access system call\n */\nvoid\nsaccess()\n{\n    uid_t t_uid;\n    gid_t t_gid;\n    register struct inode *ip;\n    register struct a {\n        char    *fname;\n        int     fmode;\n    } *uap = (struct a *)u.u_arg;\n    struct  nameidata nd;\n    register struct nameidata *ndp = &nd;\n\n    t_uid = u.u_uid;\n    t_gid = u.u_groups[0];\n    u.u_uid = u.u_ruid;\n    u.u_groups[0] = u.u_rgid;\n    NDINIT (ndp, LOOKUP, FOLLOW, uap->fname);\n    ip = namei(ndp);\n    if (ip != NULL) {\n        if ((uap->fmode&R_OK) && access(ip, IREAD))\n            goto done;\n        if ((uap->fmode&W_OK) && access(ip, IWRITE))\n            goto done;\n        if ((uap->fmode&X_OK) && access(ip, IEXEC))\n            goto done;\ndone:\n        iput(ip);\n    }\n    u.u_uid = t_uid;\n    u.u_groups[0] = t_gid;\n}\n\nstatic void\nstat1 (follow)\n    int follow;\n{\n    register struct inode *ip;\n    register struct a {\n        char    *fname;\n        struct stat *ub;\n    } *uap = (struct a *)u.u_arg;\n    struct stat sb;\n    struct  nameidata nd;\n    register struct nameidata *ndp = &nd;\n\n    NDINIT (ndp, LOOKUP, follow, uap->fname);\n    ip = namei(ndp);\n    if (ip == NULL)\n        return;\n    (void) ino_stat(ip, &sb);\n    iput(ip);\n    u.u_error = copyout((caddr_t)&sb, (caddr_t)uap->ub, sizeof (sb));\n}\n\n/*\n * Stat system call.  This version follows links.\n */\nvoid\nstat()\n{\n    stat1 (FOLLOW);\n}\n\n/*\n * Lstat system call.  This version does not follow links.\n */\nvoid\nlstat()\n{\n    stat1 (NOFOLLOW);\n}\n\n/*\n * Return target name of a symbolic link\n */\nvoid\nreadlink()\n{\n    register struct inode *ip;\n    register struct a {\n        char    *name;\n        char    *buf;\n        int     count;\n    } *uap = (struct a *)u.u_arg;\n    struct  nameidata nd;\n    register struct nameidata *ndp = &nd;\n    int resid;\n\n    NDINIT (ndp, LOOKUP, NOFOLLOW, uap->name);\n    ip = namei(ndp);\n    if (ip == NULL)\n        return;\n    if ((ip->i_mode&IFMT) != IFLNK) {\n        u.u_error = EINVAL;\n        goto out;\n    }\n    u.u_error = rdwri (UIO_READ, ip, uap->buf, uap->count, (off_t) 0,\n                IO_UNIT, &resid);\nout:\n    iput(ip);\n    u.u_rval = uap->count - resid;\n}\n\nstatic int\nchflags1 (ip, flags)\n    register struct inode *ip;\n    u_short flags;\n{\n    struct  vattr   vattr;\n\n    VATTR_NULL(&vattr);\n    vattr.va_flags = flags;\n    return(ufs_setattr(ip, &vattr));\n}\n\n/*\n * change flags of a file given pathname.\n */\nvoid\nchflags()\n{\n    register struct inode *ip;\n    register struct a {\n        char    *fname;\n        u_int   flags;\n    } *uap = (struct a *)u.u_arg;\n    struct  nameidata nd;\n    register struct nameidata *ndp = &nd;\n\n    NDINIT (ndp, LOOKUP, FOLLOW, uap->fname);\n    if ((ip = namei(ndp)) == NULL)\n        return;\n    u.u_error = chflags1 (ip, uap->flags);\n    iput(ip);\n}\n\n/*\n * change flags of a file given file descriptor.\n */\nvoid\nfchflags()\n{\n    register struct a {\n        int     fd;\n        u_int   flags;\n    } *uap = (struct a *)u.u_arg;\n    register struct inode *ip;\n\n    ip = getinode (uap->fd);\n    if (ip == NULL)\n        return;\n    ilock(ip);\n    u.u_error = chflags1 (ip, uap->flags);\n    iunlock(ip);\n}\n\n/*\n * Change mode of a file given path name.\n */\nvoid\nchmod()\n{\n    register struct inode *ip;\n    register struct a {\n        char    *fname;\n        int     fmode;\n    } *uap = (struct a *)u.u_arg;\n    struct  vattr   vattr;\n    struct  nameidata nd;\n    register struct nameidata *ndp = &nd;\n\n    NDINIT (ndp, LOOKUP, FOLLOW, uap->fname);\n    ip = namei(ndp);\n    if (!ip)\n        return;\n    VATTR_NULL(&vattr);\n    vattr.va_mode = uap->fmode & 07777;\n    u.u_error = ufs_setattr(ip, &vattr);\n    iput(ip);\n}\n\n/*\n * Change mode of a file given a file descriptor.\n */\nvoid\nfchmod()\n{\n    register struct a {\n        int     fd;\n        int     fmode;\n    } *uap = (struct a *)u.u_arg;\n    register struct inode *ip;\n    struct  vattr   vattr;\n\n    if ((ip = getinode(uap->fd)) == NULL)\n        return;\n    ilock(ip);\n    VATTR_NULL(&vattr);\n    vattr.va_mode = uap->fmode & 07777;\n    u.u_error = ufs_setattr(ip, &vattr);\n    iunlock(ip);\n}\n\n/*\n * Change the mode on a file.  This routine is called from ufs_setattr.\n * Inode must be locked before calling.\n */\nint\nchmod1(ip, mode)\n    register struct inode *ip;\n    register int mode;\n{\n    if (u.u_uid != ip->i_uid && !suser())\n        return(u.u_error);\n    if (u.u_uid) {\n        if ((ip->i_mode & IFMT) != IFDIR && (mode & ISVTX))\n            return(EFTYPE);\n        if (!groupmember(ip->i_gid) && (mode & ISGID))\n            return(EPERM);\n    }\n    ip->i_mode &= ~07777;       /* why? */\n    ip->i_mode |= mode&07777;\n    ip->i_flag |= ICHG;\n    return (0);\n}\n\n/*\n * Set ownership given a path name.\n */\nvoid\nchown()\n{\n    register struct inode *ip;\n    register struct a {\n        char    *fname;\n        int     uid;\n        int     gid;\n    } *uap = (struct a *)u.u_arg;\n    struct  nameidata nd;\n    register struct nameidata *ndp = &nd;\n    struct  vattr   vattr;\n\n    NDINIT (ndp, LOOKUP, NOFOLLOW, uap->fname);\n    ip = namei(ndp);\n    if (ip == NULL)\n        return;\n    VATTR_NULL(&vattr);\n    vattr.va_uid = uap->uid;\n    vattr.va_gid = uap->gid;\n    u.u_error = ufs_setattr(ip, &vattr);\n    iput(ip);\n}\n\n/*\n * Set ownership given a file descriptor.\n */\nvoid\nfchown()\n{\n    register struct a {\n        int     fd;\n        int     uid;\n        int     gid;\n    } *uap = (struct a *)u.u_arg;\n    register struct inode *ip;\n    struct  vattr   vattr;\n\n    if ((ip = getinode(uap->fd)) == NULL)\n        return;\n    ilock(ip);\n    VATTR_NULL(&vattr);\n    vattr.va_uid = uap->uid;\n    vattr.va_gid = uap->gid;\n    u.u_error = ufs_setattr(ip, &vattr);\n    iunlock(ip);\n}\n\n/*\n * Perform chown operation on inode ip.  This routine called from ufs_setattr.\n * inode must be locked prior to call.\n */\nint\nchown1 (ip, uid, gid)\n    register struct inode *ip;\n    register int uid, gid;\n{\n    int ouid, ogid;\n\n    if (uid == -1)\n        uid = ip->i_uid;\n    if (gid == -1)\n        gid = ip->i_gid;\n    /*\n     * If we don't own the file, are trying to change the owner\n     * of the file, or are not a member of the target group,\n     * the caller must be superuser or the call fails.\n     */\n    if ((u.u_uid != ip->i_uid || uid != ip->i_uid ||\n        !groupmember((gid_t)gid)) && !suser())\n        return (u.u_error);\n    ouid = ip->i_uid;\n    ogid = ip->i_gid;\n    ip->i_uid = uid;\n    ip->i_gid = gid;\n    if (ouid != uid || ogid != gid)\n        ip->i_flag |= ICHG;\n    if (ouid != uid && u.u_uid != 0)\n        ip->i_mode &= ~ISUID;\n    if (ogid != gid && u.u_uid != 0)\n        ip->i_mode &= ~ISGID;\n    return (0);\n}\n\n/*\n * Truncate a file given its path name.\n */\nvoid\ntruncate()\n{\n    register struct a {\n        char    *fname;\n        off_t   length;\n    } *uap = (struct a *)u.u_arg;\n    register struct inode *ip;\n    struct  nameidata nd;\n    register struct nameidata *ndp = &nd;\n    struct  vattr   vattr;\n\n    NDINIT (ndp, LOOKUP, FOLLOW, uap->fname);\n    ip = namei(ndp);\n    if (ip == NULL)\n        return;\n    if (access(ip, IWRITE))\n        goto bad;\n    VATTR_NULL(&vattr);\n    vattr.va_size = uap->length;\n    u.u_error = ufs_setattr(ip, &vattr);\nbad:\n    iput(ip);\n}\n\n/*\n * Truncate a file given a file descriptor.\n */\nvoid\nftruncate()\n{\n    register struct a {\n        int     fd;\n        off_t   length;\n    } *uap = (struct a *)u.u_arg;\n    register struct inode *ip;\n    register struct file *fp;\n    struct  vattr   vattr;\n\n    if ((fp = getf(uap->fd)) == NULL)\n        return;\n    if (!(fp->f_flag&FWRITE) || (fp->f_type != DTYPE_INODE)) {\n        u.u_error = EINVAL;\n        return;\n    }\n    ip = (struct inode *)fp->f_data;\n    ilock(ip);\n    VATTR_NULL(&vattr);\n    vattr.va_size = uap->length;\n    u.u_error = ufs_setattr(ip, &vattr);\n    iunlock(ip);\n}\n\n/*\n * Rename system call.\n *  rename(\"foo\", \"bar\");\n * is essentially\n *  unlink(\"bar\");\n *  link(\"foo\", \"bar\");\n *  unlink(\"foo\");\n * but ``atomically''.  Can't do full commit without saving state in the\n * inode on disk which isn't feasible at this time.  Best we can do is\n * always guarantee the target exists.\n *\n * Basic algorithm is:\n *\n * 1) Bump link count on source while we're linking it to the\n *    target.  This also insure the inode won't be deleted out\n *    from underneath us while we work (it may be truncated by\n *    a concurrent `trunc' or `open' for creation).\n * 2) Link source to destination.  If destination already exists,\n *    delete it first.\n * 3) Unlink source reference to inode if still around. If a\n *    directory was moved and the parent of the destination\n *    is different from the source, patch the \"..\" entry in the\n *    directory.\n *\n * Source and destination must either both be directories, or both\n * not be directories.  If target is a directory, it must be empty.\n */\nvoid\nrename()\n{\n    struct a {\n        char    *from;\n        char    *to;\n    } *uap = (struct a *)u.u_arg;\n    register struct inode *ip, *xp, *dp;\n    struct dirtemplate dirbuf;\n    int doingdirectory = 0, oldparent = 0, newparent = 0;\n    struct  nameidata nd;\n    register struct nameidata *ndp = &nd;\n    int error = 0;\n\n    NDINIT (ndp, DELETE, LOCKPARENT, uap->from);\n    ip = namei(ndp);\n    if (ip == NULL)\n        return;\n    dp = ndp->ni_pdir;\n    /*\n     * 'from' file can not be renamed if it is immutable/appendonly or if its\n     * parent directory is append only.\n     */\n    if ((ip->i_flags & (IMMUTABLE|APPEND)) || (dp->i_flags & APPEND)) {\n        iput(dp);\n        if (dp == ip)\n            irele(ip);\n        else\n            iput(ip);\n        u.u_error = EPERM;\n        return;\n    }\n\n    if ((ip->i_mode&IFMT) == IFDIR) {\n        register struct direct *d;\n\n        d = &ndp->ni_dent;\n        /*\n         * Avoid \".\", \"..\", and aliases of \".\" for obvious reasons.\n         */\n        if ((d->d_namlen == 1 && d->d_name[0] == '.') ||\n            (d->d_namlen == 2 && bcmp(d->d_name, \"..\", 2) == 0) ||\n            (dp == ip) || (ip->i_flag & IRENAME)) {\n            iput(dp);\n            if (dp == ip)\n                irele(ip);\n            else\n                iput(ip);\n            u.u_error = EINVAL;\n            return;\n        }\n        ip->i_flag |= IRENAME;\n        oldparent = dp->i_number;\n        doingdirectory++;\n    }\n    iput(dp);\n\n    /*\n     * 1) Bump link count while we're moving stuff\n     *    around.  If we crash somewhere before\n     *    completing our work, the link count\n     *    may be wrong, but correctable.\n     */\n    ip->i_nlink++;\n    ip->i_flag |= ICHG;\n    iupdat(ip, &time, &time, 1);\n    iunlock(ip);\n\n    /*\n     * When the target exists, both the directory\n     * and target inodes are returned locked.\n     */\n    ndp->ni_nameiop = CREATE | LOCKPARENT | NOCACHE;\n    ndp->ni_dirp = (caddr_t)uap->to;\n    xp = namei(ndp);\n    if (u.u_error) {\n        error = u.u_error;\n        goto out;\n    }\n    dp = ndp->ni_pdir;\n    /*\n     * rename can not be done if 'to' file exists and is immutable/appendonly\n     * or if the directory is append only (this is because an existing 'to'\n     * has to be deleted first and that is illegal in an appendonly directory).\n     */\n    if (xp && ((xp->i_flags & (IMMUTABLE|APPEND)) || (dp->i_flags & APPEND))) {\n        error = EPERM;\n        goto bad;\n    }\n\n    /*\n     * If \"..\" must be changed (ie the directory gets a new\n     * parent) then the source directory must not be in the\n     * directory heirarchy above the target, as this would\n     * orphan everything below the source directory. Also\n     * the user must have write permission in the source so\n     * as to be able to change \"..\". We must repeat the call\n     * to namei, as the parent directory is unlocked by the\n     * call to checkpath().\n     */\n    if (oldparent != dp->i_number)\n        newparent = dp->i_number;\n    if (doingdirectory && newparent) {\n        if (access(ip, IWRITE))\n            goto bad;\n        do {\n            dp = ndp->ni_pdir;\n            if (xp != NULL)\n                iput(xp);\n            u.u_error = checkpath(ip, dp);\n            if (u.u_error)\n                goto out;\n            xp = namei(ndp);\n            if (u.u_error) {\n                error = u.u_error;\n                goto out;\n            }\n        } while (dp != ndp->ni_pdir);\n    }\n    /*\n     * 2) If target doesn't exist, link the target\n     *    to the source and unlink the source.\n     *    Otherwise, rewrite the target directory\n     *    entry to reference the source inode and\n     *    expunge the original entry's existence.\n     */\n    if (xp == NULL) {\n        if (dp->i_dev != ip->i_dev) {\n            error = EXDEV;\n            goto bad;\n        }\n        /*\n         * Account for \"..\" in new directory.\n         * When source and destination have the same\n         * parent we don't fool with the link count.\n         */\n        if (doingdirectory && newparent) {\n            dp->i_nlink++;\n            dp->i_flag |= ICHG;\n            iupdat(dp, &time, &time, 1);\n        }\n        error = direnter(ip, ndp);\n        if (error)\n            goto out;\n    } else {\n        if (xp->i_dev != dp->i_dev || xp->i_dev != ip->i_dev) {\n            error = EXDEV;\n            goto bad;\n        }\n        /*\n         * Short circuit rename(foo, foo).\n         */\n        if (xp->i_number == ip->i_number)\n            goto bad;\n        /*\n         * If the parent directory is \"sticky\", then the user must\n         * own the parent directory, or the destination of the rename,\n         * otherwise the destination may not be changed (except by\n         * root). This implements append-only directories.\n         */\n        if ((dp->i_mode & ISVTX) && u.u_uid != 0 &&\n            u.u_uid != dp->i_uid && xp->i_uid != u.u_uid) {\n            error = EPERM;\n            goto bad;\n        }\n        /*\n         * Target must be empty if a directory\n         * and have no links to it.\n         * Also, insure source and target are\n         * compatible (both directories, or both\n         * not directories).\n         */\n        if ((xp->i_mode&IFMT) == IFDIR) {\n            if (!dirempty(xp, dp->i_number) || xp->i_nlink > 2) {\n                error = ENOTEMPTY;\n                goto bad;\n            }\n            if (!doingdirectory) {\n                error = ENOTDIR;\n                goto bad;\n            }\n            cacheinval(dp);\n        } else if (doingdirectory) {\n            error = EISDIR;\n            goto bad;\n        }\n        dirrewrite(dp, ip, ndp);\n        if (u.u_error) {\n            error = u.u_error;\n            goto bad1;\n        }\n        /*\n         * Adjust the link count of the target to\n         * reflect the dirrewrite above.  If this is\n         * a directory it is empty and there are\n         * no links to it, so we can squash the inode and\n         * any space associated with it.  We disallowed\n         * renaming over top of a directory with links to\n         * it above, as the remaining link would point to\n         * a directory without \".\" or \"..\" entries.\n         */\n        xp->i_nlink--;\n        if (doingdirectory) {\n            if (--xp->i_nlink != 0)\n                panic(\"rename: lnk dir\");\n            itrunc(xp, (u_long)0, 0);   /* IO_SYNC? */\n        }\n        xp->i_flag |= ICHG;\n        iput(xp);\n        xp = NULL;\n    }\n\n    /*\n     * 3) Unlink the source.\n     */\n    NDINIT (ndp, DELETE, LOCKPARENT, uap->from);\n    xp = namei(ndp);\n    if (xp != NULL)\n        dp = ndp->ni_pdir;\n    else\n        dp = NULL;\n    /*\n     * Insure that the directory entry still exists and has not\n     * changed while the new name has been entered. If the source is\n     * a file then the entry may have been unlinked or renamed. In\n     * either case there is no further work to be done. If the source\n     * is a directory then it cannot have been rmdir'ed; its link\n     * count of three would cause a rmdir to fail with ENOTEMPTY.\n     * The IRENAME flag insures that it cannot be moved by another\n     * rename.\n     */\n    if (xp != ip) {\n        if (doingdirectory)\n            panic(\"rename: lost dir entry\");\n    } else {\n        /*\n         * If the source is a directory with a\n         * new parent, the link count of the old\n         * parent directory must be decremented\n         * and \"..\" set to point to the new parent.\n         */\n        if (doingdirectory && newparent) {\n            dp->i_nlink--;\n            dp->i_flag |= ICHG;\n            error = rdwri (UIO_READ, xp, (caddr_t) &dirbuf,\n                    sizeof(struct dirtemplate), (off_t) 0,\n                    IO_UNIT, (int*) 0);\n\n            if (error == 0) {\n                if (dirbuf.dotdot_namlen != 2 ||\n                    dirbuf.dotdot_name[0] != '.' ||\n                    dirbuf.dotdot_name[1] != '.') {\n                    printf(\"rename: mangled dir\\n\");\n                } else {\n                    dirbuf.dotdot_ino = newparent;\n                    (void) rdwri (UIO_WRITE, xp,\n                        (caddr_t) &dirbuf,\n                        sizeof(struct dirtemplate),\n                        (off_t) 0,\n                        IO_UNIT | IO_SYNC, (int*) 0);\n                    cacheinval(dp);\n                }\n            }\n        }\n        if (dirremove(ndp)) {\n            xp->i_nlink--;\n            xp->i_flag |= ICHG;\n        }\n        xp->i_flag &= ~IRENAME;\n        if (error == 0)     /* XXX conservative */\n            error = u.u_error;\n    }\n    if (dp)\n        iput(dp);\n    if (xp)\n        iput(xp);\n    irele(ip);\n    if (error)\n        u.u_error = error;\n    return;\n\nbad:\n    iput(dp);\nbad1:\n    if (xp)\n        iput(xp);\nout:\n    ip->i_nlink--;\n    ip->i_flag |= ICHG;\n    irele(ip);\n    if (error)\n        u.u_error = error;\n}\n\n/*\n * Make a new file.\n */\nstruct inode *\nmaknode (mode, ndp)\n    int mode;\n    register struct nameidata *ndp;\n{\n    register struct inode *ip;\n    register struct inode *pdir = ndp->ni_pdir;\n\n    ip = ialloc(pdir);\n    if (ip == NULL) {\n        iput(pdir);\n        return (NULL);\n    }\n    ip->i_flag |= IACC|IUPD|ICHG;\n    if ((mode & IFMT) == 0)\n        mode |= IFREG;\n    ip->i_mode = mode & ~u.u_cmask;\n    ip->i_nlink = 1;\n    ip->i_uid = u.u_uid;\n    ip->i_gid = pdir->i_gid;\n    if (ip->i_mode & ISGID && !groupmember(ip->i_gid))\n        ip->i_mode &= ~ISGID;\n    /*\n     * Make sure inode goes to disk before directory entry.\n     */\n    iupdat(ip, &time, &time, 1);\n    u.u_error = direnter(ip, ndp);\n    if (u.u_error) {\n        /*\n         * Write error occurred trying to update directory\n         * so must deallocate the inode.\n         */\n        ip->i_nlink = 0;\n        ip->i_flag |= ICHG;\n        iput(ip);\n        return (NULL);\n    }\n    ndp->ni_ip = ip;\n    return (ip);\n}\n\n/*\n * A virgin directory (no blushing please).\n */\nconst struct dirtemplate mastertemplate = {\n    0, 12,              1, \".\",\n    0, DIRBLKSIZ - 12,  2, \"..\",\n};\n\n/*\n * Mkdir system call\n */\nvoid\nmkdir()\n{\n    register struct a {\n        char    *name;\n        int     dmode;\n    } *uap = (struct a *)u.u_arg;\n    register struct inode *ip, *dp;\n    struct dirtemplate dirtemplate;\n    struct  nameidata nd;\n    register struct nameidata *ndp = &nd;\n\n    NDINIT (ndp, CREATE, NOFOLLOW, uap->name);\n    ip = namei(ndp);\n    if (u.u_error)\n        return;\n    if (ip != NULL) {\n        iput(ip);\n        u.u_error = EEXIST;\n        return;\n    }\n    dp = ndp->ni_pdir;\n    uap->dmode &= 0777;\n    uap->dmode |= IFDIR;\n    /*\n     * Must simulate part of maknode here\n     * in order to acquire the inode, but\n     * not have it entered in the parent\n     * directory.  The entry is made later\n     * after writing \".\" and \"..\" entries out.\n     */\n    ip = ialloc(dp);\n    if (ip == NULL) {\n        iput(dp);\n        return;\n    }\n    ip->i_flag |= IACC|IUPD|ICHG;\n    ip->i_mode = uap->dmode & ~u.u_cmask;\n    ip->i_nlink = 2;\n    ip->i_uid = u.u_uid;\n    ip->i_gid = dp->i_gid;\n    iupdat(ip, &time, &time, 1);\n\n    /*\n     * Bump link count in parent directory\n     * to reflect work done below.  Should\n     * be done before reference is created\n     * so reparation is possible if we crash.\n     */\n    dp->i_nlink++;\n    dp->i_flag |= ICHG;\n    iupdat(dp, &time, &time, 1);\n\n    /*\n     * Initialize directory with \".\"\n     * and \"..\" from static template.\n     */\n    dirtemplate = mastertemplate;\n    dirtemplate.dot_ino = ip->i_number;\n    dirtemplate.dotdot_ino = dp->i_number;\n    u.u_error = rdwri (UIO_WRITE, ip, (caddr_t) &dirtemplate,\n        sizeof (dirtemplate), (off_t) 0, IO_UNIT | IO_SYNC, (int*) 0);\n    if (u.u_error) {\n        dp->i_nlink--;\n        dp->i_flag |= ICHG;\n        goto bad;\n    }\n    ip->i_size = DIRBLKSIZ;\n    /*\n     * Directory all set up, now\n     * install the entry for it in\n     * the parent directory.\n     */\n    u.u_error = direnter(ip, ndp);\n    dp = NULL;\n    if (u.u_error) {\n        NDINIT (ndp, LOOKUP, NOCACHE, uap->name);\n        dp = namei(ndp);\n        if (dp) {\n            dp->i_nlink--;\n            dp->i_flag |= ICHG;\n        }\n    }\nbad:\n    /*\n     * No need to do an explicit itrunc here,\n     * irele will do this for us because we set\n     * the link count to 0.\n     */\n    if (u.u_error) {\n        ip->i_nlink = 0;\n        ip->i_flag |= ICHG;\n    }\n    if (dp)\n        iput(dp);\n    iput(ip);\n}\n\n/*\n * Rmdir system call.\n */\nvoid\nrmdir()\n{\n    struct a {\n        char    *name;\n    } *uap = (struct a *)u.u_arg;\n    register struct inode *ip, *dp;\n    struct  nameidata nd;\n    register struct nameidata *ndp = &nd;\n\n    NDINIT (ndp, DELETE, LOCKPARENT, uap->name);\n    ip = namei(ndp);\n    if (ip == NULL)\n        return;\n    dp = ndp->ni_pdir;\n    /*\n     * No rmdir \".\" please.\n     */\n    if (dp == ip) {\n        irele(dp);\n        iput(ip);\n        u.u_error = EINVAL;\n        return;\n    }\n    if ((ip->i_mode&IFMT) != IFDIR) {\n        u.u_error = ENOTDIR;\n        goto out;\n    }\n    /*\n     * Don't remove a mounted on directory.\n     */\n    if (ip->i_dev != dp->i_dev) {\n        u.u_error = EBUSY;\n        goto out;\n    }\n    /*\n     * Verify the directory is empty (and valid).\n     * (Rmdir \"..\" won't be valid since\n     *  \"..\" will contain a reference to\n     *  the current directory and thus be\n     *  non-empty.)\n     */\n    if (ip->i_nlink != 2 || !dirempty(ip, dp->i_number)) {\n        u.u_error = ENOTEMPTY;\n        goto out;\n    }\n    if ((dp->i_flags & APPEND) || (ip->i_flags & (IMMUTABLE|APPEND))) {\n        u.u_error = EPERM;\n        goto out;\n    }\n    /*\n     * Delete reference to directory before purging\n     * inode.  If we crash in between, the directory\n     * will be reattached to lost+found,\n     */\n    if (dirremove(ndp) == 0)\n        goto out;\n    dp->i_nlink--;\n    dp->i_flag |= ICHG;\n    cacheinval(dp);\n    iput(dp);\n    dp = NULL;\n    /*\n     * Truncate inode.  The only stuff left\n     * in the directory is \".\" and \"..\".  The\n     * \".\" reference is inconsequential since\n     * we're quashing it.  The \"..\" reference\n     * has already been adjusted above.  We've\n     * removed the \".\" reference and the reference\n     * in the parent directory, but there may be\n     * other hard links so decrement by 2 and\n     * worry about them later.\n     */\n    ip->i_nlink -= 2;\n    itrunc(ip, (u_long)0, 0);   /* IO_SYNC? */\n    cacheinval(ip);\nout:\n    if (dp)\n        iput(dp);\n    iput(ip);\n}\n\n/*\n * Get an inode pointer of a file descriptor.\n */\nstruct inode *\ngetinode(fdes)\n    int fdes;\n{\n    register struct file *fp;\n\n    if ((unsigned)fdes >= NOFILE || (fp = u.u_ofile[fdes]) == NULL) {\n        u.u_error = EBADF;\n        return ((struct inode *)0);\n    }\n    if (fp->f_type != DTYPE_INODE) {\n        u.u_error = EINVAL;\n        return ((struct inode *)0);\n    }\n    return((struct inode *)fp->f_data);\n}\n"
  },
  {
    "path": "sys/kern/ufs_syscalls2.c",
    "content": "/*\n * ufs_syscalls was getting too large.  Various UFS related system calls were\n * relocated to this file.\n */\n#include <sys/param.h>\n#include <sys/file.h>\n#include <sys/user.h>\n#include <sys/inode.h>\n#include <sys/buf.h>\n#include <sys/fs.h>\n#include <sys/namei.h>\n#include <sys/mount.h>\n#include <sys/kernel.h>\n#include <sys/systm.h>\n#include <sys/proc.h>\n\nstatic int\nstatfs1 (mp, sbp)\n    struct  mount   *mp;\n    struct  statfs  *sbp;\n{\n    struct  statfs  sfs;\n    register struct statfs  *sfsp;\n    struct  fs  *fs = &mp->m_filsys;\n\n    sfsp = &sfs;\n    sfsp->f_type = MOUNT_UFS;\n    sfsp->f_bsize = MAXBSIZE;\n    sfsp->f_iosize = MAXBSIZE;\n    sfsp->f_blocks = fs->fs_fsize - fs->fs_isize;\n    sfsp->f_bfree = fs->fs_tfree;\n    sfsp->f_bavail = fs->fs_tfree;\n    sfsp->f_files = (fs->fs_isize - 1) * INOPB;\n    sfsp->f_ffree = fs->fs_tinode;\n\n    bcopy (mp->m_mnton, sfsp->f_mntonname, MNAMELEN);\n    bcopy (mp->m_mntfrom, sfsp->f_mntfromname, MNAMELEN);\n    sfsp->f_flags = mp->m_flags & MNT_VISFLAGMASK;\n    return copyout ((caddr_t) sfsp, (caddr_t) sbp, sizeof (struct statfs));\n}\n\nvoid\nstatfs()\n{\n    register struct a {\n        char    *path;\n        struct  statfs  *buf;\n    } *uap = (struct a *)u.u_arg;\n    register struct inode   *ip;\n    struct  nameidata nd;\n    register struct nameidata *ndp = &nd;\n    struct  mount   *mp;\n\n    NDINIT (ndp, LOOKUP, FOLLOW, uap->path);\n    ip = namei(ndp);\n    if (! ip)\n        return;\n    mp = (struct mount *)((int)ip->i_fs - offsetof(struct mount, m_filsys));\n    iput(ip);\n    u.u_error = statfs1 (mp, uap->buf);\n}\n\nvoid\nfstatfs()\n{\n    register struct a {\n        int     fd;\n        struct  statfs *buf;\n    } *uap = (struct a *)u.u_arg;\n    register struct inode *ip;\n    struct  mount *mp;\n\n    ip = getinode(uap->fd);\n    if (! ip)\n        return;\n    mp = (struct mount *)((int)ip->i_fs - offsetof(struct mount, m_filsys));\n    u.u_error = statfs1 (mp, uap->buf);\n}\n\nvoid\ngetfsstat()\n{\n    register struct a {\n        struct  statfs  *buf;\n        int     bufsize;\n        u_int   flags;\n    } *uap = (struct a *)u.u_arg;\n    register struct mount *mp;\n    caddr_t sfsp;\n    int count, maxcount, error;\n\n    maxcount = uap->bufsize / sizeof (struct statfs);\n    sfsp = (caddr_t)uap->buf;\n    count = 0;\n    for (mp = mount; mp < &mount[NMOUNT]; mp++) {\n        if (mp->m_inodp == NULL)\n            continue;\n        if (count < maxcount) {\n            error = statfs1 (mp, sfsp);\n            if (error) {\n                u.u_error = error;\n                return;\n            }\n            sfsp += sizeof (struct statfs);\n        }\n        count++;\n    }\n    if (sfsp && count > maxcount)\n        u.u_rval = maxcount;\n    else\n        u.u_rval = count;\n}\n\n/*\n * This is somewhat inefficient in that the inode table is scanned for each\n * filesystem but it didn't seem worth a page or two of code on something\n * which only happens every 30 seconds.\n */\nstatic void\nsyncinodes(fs)\n    struct  fs *fs;\n{\n    register struct inode *ip;\n\n    /*\n     * Write back each (modified) inode.\n     */\n    for (ip = inode; ip < inode+NINODE; ip++) {\n        /*\n         * Attempt to reduce the overhead by short circuiting the scan if the\n         * inode is not for the filesystem being processed.\n         */\n        if (ip->i_fs != fs)\n            continue;\n        if ((ip->i_flag & ILOCKED) != 0 || ip->i_count == 0 ||\n               (ip->i_flag & (IMOD|IACC|IUPD|ICHG)) == 0)\n            continue;\n        ip->i_flag |= ILOCKED;\n        ip->i_count++;\n        iupdat(ip, &time, &time, 0);\n        iput(ip);\n    }\n}\n\n/*\n * 'ufs_sync' is the routine which syncs a single filesystem.  This was\n * created to replace 'update' which 'unmount' called.  It seemed silly to\n * sync _every_ filesystem when unmounting just one filesystem.\n */\nint\nufs_sync(mp)\n    register struct mount *mp;\n{\n    register struct fs *fs;\n    struct  buf *bp;\n    int error = 0;\n\n    fs = &mp->m_filsys;\n    if (fs->fs_fmod && (mp->m_flags & MNT_RDONLY)) {\n        printf(\"fs = %s\\n\", fs->fs_fsmnt);\n        panic(\"sync: rofs\");\n    }\n    syncinodes(fs);     /* sync the inodes for this filesystem */\n    bflush(mp->m_dev);  /* flush dirty data blocks */\n    /*\n     * And lastly the superblock, if the filesystem was modified.\n     * Write back modified superblocks. Consistency check that the superblock\n     * of each file system is still in the buffer cache.\n     */\n    if (fs->fs_fmod) {\n        bp = getblk(mp->m_dev, SUPERB);\n        fs->fs_fmod = 0;\n        fs->fs_time = time.tv_sec;\n        bcopy(fs, bp->b_addr, sizeof (struct fs));\n        bwrite(bp);\n        error = geterror(bp);\n    }\n    return(error);\n}\n\n/*\n * mode mask for creation of files\n */\nvoid\numask()\n{\n    register struct a {\n        int     mask;\n    } *uap = (struct a *)u.u_arg;\n\n    u.u_rval = u.u_cmask;\n    u.u_cmask = uap->mask & 07777;\n}\n\n/*\n * Seek system call\n */\nvoid\nlseek()\n{\n    register struct file *fp;\n    register struct a {\n        int     fd;\n        off_t   off;\n        int     sbase;\n    } *uap = (struct a *)u.u_arg;\n\n    if ((fp = getf(uap->fd)) == NULL)\n        return;\n    if (fp->f_type != DTYPE_INODE) {\n        u.u_error = ESPIPE;\n        return;\n    }\n    switch (uap->sbase) {\n\n    case L_INCR:\n        fp->f_offset += uap->off;\n        break;\n    case L_XTND:\n        fp->f_offset = uap->off + ((struct inode *)fp->f_data)->i_size;\n        break;\n    case L_SET:\n        fp->f_offset = uap->off;\n        break;\n    default:\n        u.u_error = EINVAL;\n        return;\n    }\n    u.u_rval = fp->f_offset;\n}\n\n/*\n * Synch an open file.\n */\nvoid\nfsync()\n{\n    register struct a {\n        int     fd;\n    } *uap = (struct a *)u.u_arg;\n    register struct inode *ip;\n\n    if ((ip = getinode(uap->fd)) == NULL)\n        return;\n    ilock(ip);\n    syncip(ip);\n    iunlock(ip);\n}\n\nvoid\nutimes()\n{\n    register struct a {\n        char    *fname;\n        struct  timeval *tptr;\n    } *uap = (struct a *)u.u_arg;\n    register struct inode *ip;\n    struct  nameidata nd;\n    register struct nameidata *ndp = &nd;\n    struct timeval tv[2];\n    struct vattr vattr;\n\n    VATTR_NULL(&vattr);\n    if (uap->tptr == NULL) {\n        tv[0].tv_sec = tv[1].tv_sec = time.tv_sec;\n        vattr.va_vaflags |= VA_UTIMES_NULL;\n    } else {\n        u.u_error = copyin ((caddr_t)uap->tptr,(caddr_t)tv,sizeof(tv));\n        if (u.u_error)\n            return;\n    }\n    NDINIT (ndp, LOOKUP, FOLLOW, uap->fname);\n    if ((ip = namei(ndp)) == NULL)\n        return;\n    vattr.va_atime = tv[0].tv_sec;\n    vattr.va_mtime = tv[1].tv_sec;\n    u.u_error = ufs_setattr(ip, &vattr);\n    iput(ip);\n}\n"
  },
  {
    "path": "sys/kern/vfs_vnops.c",
    "content": "/*\n * Copyright (c) 1982, 1986, 1989, 1993\n *  The Regents of the University of California.  All rights reserved.\n * (c) UNIX System Laboratories, Inc.\n * All or some portions of this file are derived from material licensed\n * to the University of California by American Telephone and Telegraph\n * Co. or Unix System Laboratories, Inc. and are reproduced herein with\n * the permission of UNIX System Laboratories, Inc.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *  This product includes software developed by the University of\n *  California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#include <sys/param.h>\n#include <sys/file.h>\n#include <sys/user.h>\n#include <sys/namei.h>\n#include <sys/inode.h>\n#include <sys/stat.h>\n#include <sys/systm.h>\n\n/*\n * 2.11BSD does not have \"vnodes\", having instead only old fashioned \"inodes\".\n * The routine names (i.e. vn_open) were retained since the functions them-\n * selves were ported over with minimal change.  Retaining the 4.4 function\n * names also makes it easier to follow the logic flow when reading the 4.4\n * sources.  Also, changing the names from vn_* to in_* could have caused\n * confusion with the networking routines since 'in_' and 'ip_' are frequently\n * used in the networking code.\n *\n * The tab spacing has been altered to be (to me) more readable.\n*/\n\n/*\n * Common code for vnode open operations.\n * Check permissions, and call the VOP_OPEN (openi for 2.11) or VOP_CREATE\n * (maknode) routine.\n */\nint\nvn_open (ndp, fmode, cmode)\n    register struct nameidata *ndp;\n    int fmode, cmode;\n{\n    register struct inode *ip;\n    register int error;\n\n    if (fmode & O_CREAT) {\n        if ((fmode & O_EXCL) == 0)\n            ndp->ni_nameiop |= (CREATE|FOLLOW);\n        else\n            ndp->ni_nameiop = CREATE;\n        ip = namei(ndp);\n        if (ip == NULL) {\n            if (u.u_error) {\n                goto retuerr;\n            }\n            ip = maknode(cmode, ndp);\n            if (ip == NULL) {\n                goto retuerr;\n            }\n            fmode &= ~O_TRUNC;\n        } else {\n            if (fmode & O_EXCL) {\n                error = EEXIST;\n                goto bad;\n            }\n            fmode &= ~O_CREAT;\n        }\n    } else {\n        ndp->ni_nameiop = LOOKUP | FOLLOW;\n        ip = namei(ndp);\n        if (ip == NULL) {\n            goto retuerr;\n        }\n    }\n    if ((ip->i_mode & IFMT) == IFSOCK) {\n        error = EOPNOTSUPP;\n        goto bad;\n    }\n    if ((ip->i_flags & APPEND) && (fmode&(FWRITE|O_APPEND)) == FWRITE) {\n        error = EPERM;\n        goto bad;\n    }\n    if ((fmode & O_CREAT) == 0) {\n        if (fmode & FREAD) {\n            if (access(ip, IREAD)) {\n                error = u.u_error;  /* XXX */\n                goto bad;\n            }\n        }\n        if (fmode & (FWRITE | O_TRUNC)) {\n            if ((ip->i_mode & IFMT) == IFDIR) {\n                error = EISDIR;\n                goto bad;\n            }\n            if (access(ip, IWRITE)) {\n                error = u.u_error;\n                goto bad;\n            }\n        }\n    }\n    if (fmode & O_TRUNC)\n        itrunc(ip, (off_t)0, fmode & O_FSYNC ? IO_SYNC : 0);\n    /*\n     * 4.4 returns the vnode locked from vn_open which means that each caller\n     * has to go and unlock it.\n     *\n     * 2.11 returns the inode unlocked (for now).\n     */\n    iunlock(ip);        /* because namei returns a locked inode */\n    if (setjmp(&u.u_qsave)) {\n        error = EINTR;  /* opens are not restarted after signals */\n        goto lbad;\n    }\n    error = openi (ip, fmode);\n    if (error) {\n        goto lbad;\n    }\n    return(0);\n\n    /*\n     * Gratuitous lock but it does (correctly) implement the earlier behaviour of\n     * copen (it also avoids a panic in iput).\n     */\nlbad:\n    ilock(ip);\n\nbad:\n    /*\n     * Do NOT do an 'ilock' here - this tag is to be used only when the inode is\n     * locked (i.e. from namei).\n     */\n    iput(ip);\n    return(error);\n\nretuerr:\n    return(u.u_error);  /* XXX - Bletch */\n}\n\n/*\n * Inode close call.  Pipes and sockets do NOT enter here.  This routine is\n * used by the kernel to close files it opened for itself.\n * The kernel does not create sockets or pipes on its own behalf.\n *\n * The difference between this routine and vn_closefile below is that vn_close\n * takes an \"inode *\" as a first argument and is passed the flags by the caller\n * while vn_closefile (called from the closef routine for DTYPE_INODE inodes)\n * takes a \"file *\" and extracts the flags from the file structure.\n */\nint\nvn_close(ip, flags)\n    register struct inode *ip;\n    int flags;\n{\n    register int error;\n\n    error = closei(ip, flags);\n    irele(ip);          /* assumes inode is unlocked */\n    return(error);\n}\n\n/*\n * File table inode close routine.  This is called from 'closef()' via the\n * \"Fops\" table (the 'inodeops' entry).\n *\n * NOTE: pipes are a special case of inode and have their own 'pipe_close'\n * entry in the 'pipeops' table. See sys_pipe.c for pipe_close().\n *\n * In 4.4BSD this routine called vn_close() but since 2.11 does not do the\n * writecheck counting we can skip the overhead of nesting another level down\n * and call closei() and irele() ourself.\n */\nint\nvn_closefile(fp)\n    register struct file *fp;\n{\n    register struct inode *ip = (struct inode *)fp->f_data;\n\n    /*\n     * Need to clear the inode pointer in the file structure so that the\n     * inode is not seen during the scan for aliases of character or block\n     * devices in closei().\n     */\n    fp->f_data = (caddr_t)0;    /* XXX */\n    irele(ip);\n    return (closei(ip, fp->f_flag));\n}\n"
  },
  {
    "path": "sys/kern/vm_sched.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/vm.h>\n#include <sys/kernel.h>\n#include <sys/systm.h>\n#include <machine/debug.h>\n\n#define MINFINITY   -32767      /* minus infinity */\n\nint     maxslp = MAXSLP;\nchar    runin;                  /* scheduling flag */\nchar    runout;                 /* scheduling flag */\n\n/*\n * The main loop of the scheduling (swapping) process.\n * The basic idea is:\n *  see if anyone wants to be swapped in\n *  swap out processes until there is room\n *  swap him in\n *  repeat\n * The runout flag is set whenever someone is swapped out.  Sched sleeps on\n * it awaiting work.  Sched sleeps on runin whenever it cannot find enough\n * core (by swapping out or otherwise) to fit the selected swapped process.\n * It is awakened when the core situation changes and in any case once per\n * second.\n */\nvoid\nsched()\n{\n    register struct proc *rp;\n    struct proc *swapped_out = 0, *in_core = 0;\n    register int out_time, rptime;\n\n    for (;;) {\n        /* Perform swap-out/swap-in action. */\n        spl0();\n        if (in_core)\n            swapout (in_core, X_FREECORE, X_OLDSIZE, X_OLDSIZE);\n        if (swapped_out)\n            swapin (swapped_out);\n        splhigh();\n        in_core = 0;\n        swapped_out = 0;\n\n        /* Find user to swap in; of users ready,\n         * select one out longest. */\n        out_time = -20000;\n        for (rp = allproc; rp; rp = rp->p_nxt) {\n            if (rp->p_stat != SRUN || (rp->p_flag & SLOAD))\n                continue;\n            rptime = rp->p_time - rp->p_nice * 8;\n\n            /*\n             * Always bring in parents ending a vfork,\n             * to avoid deadlock\n             */\n            if (rptime > out_time || (rp->p_flag & SVFPRNT)) {\n                swapped_out = rp;\n                out_time = rptime;\n                if (rp->p_flag & SVFPRNT)\n                    break;\n            }\n        }\n\n        /* If there is no one there, wait. */\n        if (! swapped_out) {\n            ++runout;\n            sleep ((caddr_t) &runout, PSWP);\n            continue;\n        }\n\n        /*\n         * Look around for somebody to swap out.\n         * There may be only one non-system loaded process.\n         */\n        for (rp = allproc; rp != NULL; rp = rp->p_nxt) {\n            if (rp->p_stat != SZOMB &&\n                (rp->p_flag & (SSYS | SLOAD)) == SLOAD) {\n                in_core = rp;\n                break;\n            }\n        }\n        if (! in_core) {\n            /* In-core memory is empty. */\n            continue;\n        }\n\n        /*\n         * Swap found user out if sleeping interruptibly, or if he has spent at\n         * least 1 second in core and the swapped-out process has spent at\n         * least 2 seconds out.  Otherwise wait a bit and try again.\n         */\n        if (! (in_core->p_flag & SLOCK) &&\n            (in_core->p_stat == SSTOP ||\n             (in_core->p_stat == SSLEEP && (in_core->p_flag & P_SINTR)) ||\n             ((in_core->p_stat == SRUN || in_core->p_stat == SSLEEP) &&\n              out_time >= 2 &&\n              in_core->p_time + in_core->p_nice >= 1)))\n        {\n            /* Swap out in-core process. */\n            in_core->p_flag &= ~SLOAD;\n            if (in_core->p_stat == SRUN)\n                remrq (in_core);\n        } else {\n            /* Nothing to swap in/out. */\n            in_core = 0;\n            swapped_out = 0;\n            ++runin;\n            sleep ((caddr_t) &runin, PSWP);\n        }\n    }\n}\n\n/*\n * Count up various things once a second\n */\nvoid\nvmmeter()\n{\n#ifdef UCB_METER\n    register u_short *cp, *rp;\n    register long *sp;\n\n    ave(avefree, freemem, 5);\n    ave(avefree30, freemem, 30);\n    cp = &cnt.v_first;\n    rp = &rate.v_first;\n    sp = &sum.v_first;\n    while (cp <= &cnt.v_last) {\n        ave(*rp, *cp, 5);\n        *sp += *cp;\n        *cp = 0;\n        rp++, cp++, sp++;\n    }\n#endif\n\n    if (time.tv_sec % 5 == 0) {\n        vmtotal();\n#ifdef UCB_METER\n        rate.v_swpin = cnt.v_swpin;\n        sum.v_swpin += cnt.v_swpin;\n        cnt.v_swpin = 0;\n        rate.v_swpout = cnt.v_swpout;\n        sum.v_swpout += cnt.v_swpout;\n        cnt.v_swpout = 0;\n#endif\n    }\n}\n\n/*\n * Compute Tenex style load average.  This code is adapted from similar code\n * by Bill Joy on the Vax system.  The major change is that we avoid floating\n * point since not all pdp-11's have it.  This makes the code quite hard to\n * read - it was derived with some algebra.\n *\n * \"floating point\" numbers here are stored in a 16 bit short, with 8 bits on\n * each side of the decimal point.  Some partial products will have 16 bits to\n * the right.\n */\nstatic void\nloadav (avg, n)\n    register short  *avg;\n    register int    n;\n{\n    register int    i;\n    static const long cexp[3] = {\n        0353,   /* 256 * exp(-1/12)  */\n        0373,   /* 256 * exp(-1/60)  */\n        0376,   /* 256 * exp(-1/180) */\n    };\n\n    for (i = 0; i < 3; i++)\n        avg[i] = (cexp[i] * (avg[i]-(n<<8)) + (((long)n)<<16)) >> 8;\n}\n\nvoid\nvmtotal()\n{\n    register struct proc *p;\n    register int nrun = 0;\n#ifdef UCB_METER\n    total.t_vmtxt = 0;\n    total.t_avmtxt = 0;\n    total.t_rmtxt = 0;\n    total.t_armtxt = 0;\n    total.t_vm = 0;\n    total.t_avm = 0;\n    total.t_rm = 0;\n    total.t_arm = 0;\n    total.t_rq = 0;\n    total.t_dw = 0;\n    total.t_sl = 0;\n    total.t_sw = 0;\n#endif\n    for (p = allproc; p != NULL; p = p->p_nxt) {\n        if (p->p_flag & SSYS)\n            continue;\n        if (p->p_stat) {\n#ifdef UCB_METER\n            if (p->p_stat != SZOMB) {\n                total.t_vm += p->p_dsize + p->p_ssize + USIZE;\n                if (p->p_flag & SLOAD)\n                    total.t_rm += p->p_dsize + p->p_ssize\n                        + USIZE;\n            }\n#endif\n            switch (p->p_stat) {\n\n            case SSLEEP:\n            case SSTOP:\n                if (!(p->p_flag & P_SINTR) && p->p_stat == SSLEEP)\n                    nrun++;\n#ifdef UCB_METER\n                if (p->p_flag & SLOAD) {\n                    if  (!(p->p_flag & P_SINTR))\n                        total.t_dw++;\n                    else if (p->p_slptime < maxslp)\n                        total.t_sl++;\n                } else if (p->p_slptime < maxslp)\n                    total.t_sw++;\n                if (p->p_slptime < maxslp)\n                    goto active;\n#endif\n                break;\n\n            case SRUN:\n            case SIDL:\n                nrun++;\n#ifdef UCB_METER\n                if (p->p_flag & SLOAD)\n                    total.t_rq++;\n                else\n                    total.t_sw++;\nactive:\n                total.t_avm += p->p_dsize + p->p_ssize + USIZE;\n                if (p->p_flag & SLOAD)\n                    total.t_arm += p->p_dsize + p->p_ssize\n                        + USIZE;\n#endif\n                break;\n            }\n        }\n    }\n#ifdef UCB_METER\n    total.t_vm += total.t_vmtxt;\n    total.t_avm += total.t_avmtxt;\n    total.t_rm += total.t_rmtxt;\n    total.t_arm += total.t_armtxt;\n    total.t_free = avefree;\n#endif\n    loadav (avenrun, nrun);\n}\n"
  },
  {
    "path": "sys/kern/vm_swap.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/map.h>\n#include <sys/buf.h>\n#include <sys/systm.h>\n#include <sys/vm.h>\n\n/*\n * Swap a process in.\n * Allocate data and possible text separately.  It would be better\n * to do largest first.  Text, data, and stack are allocated in\n * that order, as that is likely to be in order of size.\n * U area goes into u0 buffer.\n */\nvoid\nswapin (p)\n    register struct proc *p;\n{\n    size_t daddr = (size_t)__user_data_start;\n    size_t saddr = (size_t)__user_data_end - p->p_ssize;\n    size_t uaddr = (size_t) &u0;\n\n    if (p->p_dsize) {\n        swap (p->p_daddr, daddr, p->p_dsize, B_READ);\n        mfree (swapmap, btod (p->p_dsize), p->p_daddr);\n    }\n    if (p->p_ssize) {\n        swap (p->p_saddr, saddr, p->p_ssize, B_READ);\n        mfree (swapmap, btod (p->p_ssize), p->p_saddr);\n    }\n    swap (p->p_addr, uaddr, USIZE, B_READ);\n    mfree (swapmap, btod (USIZE), p->p_addr);\n\n    p->p_daddr = daddr;\n    p->p_saddr = saddr;\n    p->p_addr = uaddr;\n    if (p->p_stat == SRUN)\n        setrq (p);\n    p->p_flag |= SLOAD;\n    p->p_time = 0;\n#ifdef UCB_METER\n    cnt.v_swpin++;\n#endif\n}\n\n/*\n * Swap out process p.\n * odata and ostack are the old data size and the stack size\n * of the process, and are supplied during core expansion swaps.\n * The freecore flag causes its core to be freed -- it may be\n * off when called to create an image for a child process\n * in newproc.\n *\n * panic: out of swap space\n */\nvoid\nswapout (p, freecore, odata, ostack)\n    register struct proc *p;\n    int freecore;\n    register u_int odata, ostack;\n{\n    size_t a[3];\n\n    if (odata == (u_int) X_OLDSIZE)\n        odata = p->p_dsize;\n    if (ostack == (u_int) X_OLDSIZE)\n        ostack = p->p_ssize;\n    if (malloc3 (swapmap, btod (p->p_dsize), btod (p->p_ssize),\n        btod (USIZE), a) == NULL)\n        panic (\"out of swap space\");\n    p->p_flag |= SLOCK;\n    if (odata) {\n        swap (a[0], p->p_daddr, odata, B_WRITE);\n    }\n    if (ostack) {\n        swap (a[1], p->p_saddr, ostack, B_WRITE);\n    }\n    /*\n     * Increment u_ru.ru_nswap for process being tossed out of core.\n     * We can be called to swap out a process other than the current\n     * process, so we have to map in the victim's u structure briefly.\n     * Note, savekdsa6 *must* be a static, because we remove the stack\n     * in the next instruction.  The splclock is to prevent the clock\n     * from coming in and doing accounting for the wrong process, plus\n     * we don't want to come through here twice.  Why are we doing\n     * this, anyway?\n     */\n    {\n        int s;\n\n        s = splclock();\n        u.u_ru.ru_nswap++;\n        splx (s);\n    }\n    swap (a[2], p->p_addr, USIZE, B_WRITE);\n    p->p_daddr = a[0];\n    p->p_saddr = a[1];\n    p->p_addr = a[2];\n    p->p_flag &= ~(SLOAD|SLOCK);\n    p->p_time = 0;\n\n#ifdef UCB_METER\n    cnt.v_swpout++;\n#endif\n    if (runout) {\n        runout = 0;\n        wakeup ((caddr_t)&runout);\n    }\n}\n"
  },
  {
    "path": "sys/kern/vm_swp.c",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/param.h>\n#include <sys/user.h>\n#include <sys/proc.h>\n#include <sys/buf.h>\n#include <sys/conf.h>\n#include <sys/systm.h>\n#include <sys/vm.h>\n#include <sys/uio.h>\n\n/*\n * swap I/O\n */\nvoid\nswap (blkno, coreaddr, count, rdflg)\n    size_t blkno, coreaddr;\n    register int count;\n    int rdflg;\n{\n    register struct buf *bp;\n    int s;\n\n//printf (\"swap (%u, %08x, %d, %s)\\n\", blkno, coreaddr, count, rdflg ? \"R\" : \"W\");\n#ifdef UCB_METER\n    if (rdflg) {\n        cnt.v_kbin += (count + 1023) / 1024;\n    } else {\n        cnt.v_kbout += (count + 1023) / 1024;\n    }\n#endif\n    bp = geteblk();         /* allocate a buffer header */\n\n    while (count) {\n        bp->b_flags = B_BUSY | B_PHYS | B_INVAL | rdflg;\n        bp->b_dev = swapdev;\n        bp->b_bcount = count;\n        bp->b_blkno = blkno;\n        bp->b_addr = (caddr_t) coreaddr;\n        (*bdevsw[major(swapdev)].d_strategy) (bp);\n        s = splbio();\n        while ((bp->b_flags & B_DONE) == 0)\n            sleep ((caddr_t)bp, PSWP);\n        splx (s);\n        if ((bp->b_flags & B_ERROR) || bp->b_resid)\n            panic (\"hard err: swap\");\n        count -= count;\n        coreaddr += count;\n        blkno += btod (count);\n    }\n    brelse(bp);\n}\n\n/*\n * Raw I/O. The arguments are\n *  The strategy routine for the device\n *  A buffer, which may be a special buffer header\n *    owned exclusively by the device for this purpose or\n *    NULL if one is to be allocated.\n *  The device number\n *  Read/write flag\n * Essentially all the work is computing physical addresses and\n * validating them.\n *\n * rewritten to use the iov/uio mechanism from 4.3bsd.  the physbuf routine\n * was inlined.  essentially the chkphys routine performs the same task\n * as the useracc routine on a 4.3 system. 3/90 sms\n *\n * If the buffer pointer is NULL then one is allocated \"dynamically\" from\n * the system cache.  the 'invalid' flag is turned on so that the brelse()\n * done later doesn't place the buffer back in the cache.  the 'phys' flag\n * is left on so that the address of the buffer is recalcuated in getnewbuf().\n * The BYTE/WORD stuff began to be removed after testing proved that either\n * 1) the underlying hardware gives an error or 2) nothing bad happens.\n * besides, 4.3BSD doesn't do the byte/word check and noone could remember\n * why the byte/word check was added in the first place - likely historical\n * paranoia.  chkphys() inlined.  5/91 sms\n *\n * Refined (and streamlined) the flow by using a 'for' construct\n * (a la 4.3Reno).  Avoid allocating/freeing the buffer for each iovec\n * element (i must have been confused at the time).  6/91-sms\n *\n * Finished removing the BYTE/WORD code as part of implementing the common\n * raw read&write routines , systems had been running fine for several\n * months with it ifdef'd out.  9/91-sms\n */\nint\nphysio(strat, bp, dev, rw, uio)\n    void (*strat) (struct buf*);\n    register struct buf *bp;\n    dev_t dev;\n    int rw;\n    register struct uio *uio;\n{\n    int error = 0, s, c, allocbuf = 0;\n    register struct iovec *iov;\n\n    if (! bp) {\n        allocbuf++;\n        bp = geteblk();\n    }\n    u.u_procp->p_flag |= SLOCK;\n    for ( ; uio->uio_iovcnt; uio->uio_iov++, uio->uio_iovcnt--) {\n        iov = uio->uio_iov;\n        if (iov->iov_base >= iov->iov_base + iov->iov_len) {\n            error = EFAULT;\n            break;\n        }\n        /*\n         * Check that transfer is either entirely in the\n         * data or in the stack: that is, either\n         * the end is in the data or the start is in the stack\n         * (remember wraparound was already checked).\n         */\n        if (baduaddr (iov->iov_base) ||\n            baduaddr (iov->iov_base + iov->iov_len - 1)) {\n            error = EFAULT;\n            break;\n        }\n        if (! allocbuf) {\n            s = splbio();\n            while (bp->b_flags & B_BUSY) {\n                bp->b_flags |= B_WANTED;\n                sleep((caddr_t)bp, PRIBIO+1);\n            }\n            splx(s);\n        }\n        bp->b_error = 0;\n        while (iov->iov_len) {\n            bp->b_flags = B_BUSY | B_PHYS | B_INVAL | rw;\n            bp->b_dev = dev;\n            bp->b_addr = iov->iov_base;\n            bp->b_blkno = (unsigned) uio->uio_offset >> DEV_BSHIFT;\n            bp->b_bcount = iov->iov_len;\n            c = bp->b_bcount;\n            (*strat)(bp);\n            s = splbio();\n            while ((bp->b_flags & B_DONE) == 0)\n                sleep((caddr_t)bp, PRIBIO);\n            if (bp->b_flags & B_WANTED) /* rare */\n                wakeup((caddr_t)bp);\n            splx(s);\n            c -= bp->b_resid;\n            iov->iov_base += c;\n            iov->iov_len -= c;\n            uio->uio_resid -= c;\n            uio->uio_offset += c;\n            /* temp kludge for tape drives */\n            if (bp->b_resid || (bp->b_flags & B_ERROR))\n                break;\n        }\n        bp->b_flags &= ~(B_BUSY | B_WANTED);\n        error = geterror(bp);\n        /* temp kludge for tape drives */\n        if (bp->b_resid || error)\n            break;\n    }\n    if (allocbuf)\n        brelse(bp);\n    u.u_procp->p_flag &= ~SLOCK;\n    return(error);\n}\n\nint\nrawrw (dev, uio, flag)\n    dev_t dev;\n    register struct uio *uio;\n    int flag;\n{\n    return (physio(cdevsw[major(dev)].d_strategy, (struct buf *)NULL, dev,\n        uio->uio_rw == UIO_READ ? B_READ : B_WRITE, uio));\n}\n"
  },
  {
    "path": "sys/sys/buf.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * The header for buffers in the buffer pool and otherwise used\n * to describe a block i/o request is given here.\n *\n * Each buffer in the pool is usually doubly linked into 2 lists:\n * hashed into a chain by <dev,blkno> so it can be located in the cache,\n * and (usually) on (one of several) queues.  These lists are circular and\n * doubly linked for easy removal.\n *\n * There are currently two queues for buffers:\n *  one for buffers containing ``useful'' information (the cache)\n *  one for buffers containing ``non-useful'' information\n *      (and empty buffers, pushed onto the front)\n * These queues contain the buffers which are available for\n * reallocation, are kept in lru order.  When not on one of these queues,\n * the buffers are ``checked out'' to drivers which use the available list\n * pointers to keep track of them in their i/o active queues.\n */\n\n/*\n * Bufhd structures used at the head of the hashed buffer queues.\n * We only need three words for these, so this abbreviated\n * definition saves some space.\n */\nstruct bufhd\n{\n    int     b_flags;                /* see defines below */\n    struct  buf *b_forw, *b_back;   /* fwd/bkwd pointer in chain */\n};\n\nstruct buf\n{\n    int     b_flags;                /* see defines below */\n    struct  buf *b_forw, *b_back;   /* hash chain (2 way street) */\n    struct  buf *av_forw, *av_back; /* position on free list if not BUSY */\n#define b_actf  av_forw             /* alternate names for driver queue */\n#define b_actl  av_back             /* head - isn't history wonderful */\n    u_int   b_bcount;               /* transfer count */\n#define b_active b_bcount           /* driver queue head: drive active */\n    int     b_error;                /* returned after I/O */\n    dev_t   b_dev;                  /* major+minor device name */\n    caddr_t b_addr;                 /* core address */\n    daddr_t b_blkno;                /* block # on device */\n    u_int   b_resid;                /* words not transferred after error */\n#define b_cylin b_resid             /* disksort */\n#define b_errcnt b_resid            /* while i/o in progress: # retries */\n};\n\n/*\n * We never use BQ_LOCKED or BQ_EMPTY, but if you want the 4.X block I/O\n * code to drop in, you have to have BQ_AGE and BQ_LRU *after* the first\n * queue, and it only costs 6 bytes of data space.\n */\n#define BQUEUES     3               /* number of free buffer queues */\n\n#define BQ_LOCKED   0               /* super-blocks &c */\n#define BQ_LRU      1               /* lru, useful buffers */\n#define BQ_AGE      2               /* rubbish */\n#define BQ_EMPTY    3               /* buffer headers with no memory */\n\n/* Flags to low-level allocation routines. */\n#define B_CLRBUF    0x01            /* Request allocated buffer be cleared. */\n#define B_SYNC      0x02            /* Do all allocations synchronously. */\n\n#define bawrite(bp) { (bp)->b_flags |= B_ASYNC; bwrite(bp); }\n#define bfree(bp)   (bp)->b_bcount = 0\n\n#ifdef KERNEL\nstruct inode;\n\n#define BUFHSZ      16              /* must be power of 2 */\n#define BUFHASH(dev,bn) ((struct buf*) &bufhash [((dev) + bn) & (BUFHSZ - 1)])\n\nextern struct   buf buf[];          /* the buffer pool itself */\nextern char     bufdata[];          /* core data */\nextern struct   bufhd bufhash[];    /* heads of hash lists */\nextern struct   buf bfreelist[];    /* heads of available lists */\n\n/*\n * Assign a buffer for the given block.  If the appropriate\n */\nstruct buf *getblk (dev_t dev, daddr_t blkno);\n\n/*\n * Allocate a block in the file system.\n */\nstruct buf *balloc (struct inode *ip, int flags);\n\n/*\n * Get an empty block.\n */\nstruct buf *geteblk (void);\n\n/*\n * Read in (if necessary) the block and return a buffer pointer.\n */\nstruct buf *bread (dev_t dev, daddr_t blkno);\n\n/*\n * Read in the block, like bread, but also start I/O on the\n * read-ahead block.\n */\nstruct buf *breada (dev_t dev, daddr_t blkno, daddr_t rablkno);\n\n/*\n * Write the buffer, waiting for completion. Then release the buffer.\n */\nvoid bwrite (struct buf *bp);\n\n/*\n * Release the buffer, with delayed write.\n */\nvoid bdwrite (struct buf *bp);\n\n/*\n * Mark I/O complete on a buffer.\n */\nvoid biodone (struct buf *bp);\n\n/*\n * Release the buffer, with no I/O implied.\n */\nvoid brelse (struct buf *bp);\n\n/*\n * Wait for I/O completion on the buffer.\n */\nvoid biowait (struct buf *bp);\n\n/*\n * See if the block is associated with some buffer.\n */\nint incore (dev_t dev, daddr_t blkno);\n\n/*\n * Make sure all write-behind blocks on dev are flushed out.\n */\nvoid bflush (dev_t dev);\n\n/*\n * Insure that no part of a specified block is in an incore buffer.\n */\nvoid blkflush (dev_t dev, daddr_t blkno);\n\n/*\n * Invalidate in core blocks belonging to closed or umounted filesystem.\n */\nvoid binval (dev_t dev);\n\n/*\n * Pick up the device's error number and pass it to the user.\n */\nint geterror (struct buf *bp);\n\n#endif /* KERNEL */\n\n/*\n * These flags are kept in b_flags.\n */\n#define B_WRITE     0x00000     /* non-read pseudo-flag */\n#define B_READ      0x00001     /* read when I/O occurs */\n#define B_DONE      0x00002     /* transaction finished */\n#define B_ERROR     0x00004     /* transaction aborted */\n#define B_BUSY      0x00008     /* not on av_forw/back list */\n#define B_PHYS      0x00010     /* physical IO */\n#define B_MAP       0x00020     /* alloc UNIBUS */\n#define B_WANTED    0x00040     /* issue wakeup when BUSY goes off */\n#define B_AGE       0x00080     /* delayed write for correct aging */\n#define B_ASYNC     0x00100     /* don't wait for I/O completion */\n#define B_DELWRI    0x00200     /* write at exit of avail list */\n#define B_TAPE      0x00400     /* this is a magtape (no bdwrite) */\n#define B_INVAL     0x00800     /* does not contain valid info */\n#define B_BAD       0x01000     /* bad block revectoring in progress */\n#define B_LOCKED    0x02000     /* locked in core (not reusable) */\n#define B_UBAREMAP  0x04000     /* addr UNIBUS virtual, not physical */\n#define B_RAMREMAP  0x08000     /* remapped into ramdisk */\n\n/*\n * Insq/Remq for the buffer hash lists.\n */\n#define bremhash(bp) { \\\n    (bp)->b_back->b_forw = (bp)->b_forw; \\\n    (bp)->b_forw->b_back = (bp)->b_back; \\\n}\n#define binshash(bp, dp) { \\\n    (bp)->b_forw = (dp)->b_forw; \\\n    (bp)->b_back = (dp); \\\n    (dp)->b_forw->b_back = (bp); \\\n    (dp)->b_forw = (bp); \\\n}\n\n/*\n * Insq/Remq for the buffer free lists.\n */\n#define bremfree(bp) { \\\n    (bp)->av_back->av_forw = (bp)->av_forw; \\\n    (bp)->av_forw->av_back = (bp)->av_back; \\\n}\n#define binsheadfree(bp, dp) { \\\n    (dp)->av_forw->av_back = (bp); \\\n    (bp)->av_forw = (dp)->av_forw; \\\n    (dp)->av_forw = (bp); \\\n    (bp)->av_back = (dp); \\\n}\n#define binstailfree(bp, dp) { \\\n    (dp)->av_back->av_forw = (bp); \\\n    (bp)->av_back = (dp)->av_back; \\\n    (dp)->av_back = (bp); \\\n    (bp)->av_forw = (dp); \\\n}\n\n/*\n * Take a buffer off the free list it's on and\n * mark it as being use (B_BUSY) by a device.\n */\n#define notavail(bp) { \\\n    register int x = splbio(); \\\n    bremfree(bp); \\\n    (bp)->b_flags |= B_BUSY; \\\n    splx(x); \\\n}\n"
  },
  {
    "path": "sys/sys/callout.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * The callout structure is for\n * a routine arranging\n * to be called by the clock interrupt\n * (clock.c) with a specified argument,\n * in a specified amount of time.\n * Used, for example, to time tab\n * delays on typewriters.\n *\n * The c_time field is stored in terms of ticks.  Therefore, no callout\n * may be scheduled past around 8 minutes on a 60 HZ machine.  This is\n * good as it avoids long operations on clock ticks.  If you are ever\n * forced to use a long, you might as well start doing the real-time\n * timer as a timeout like 4.3BSD.\n */\nstruct  callout {\n    int     c_time;                 /* incremental time */\n    caddr_t c_arg;                  /* argument to routine */\n    void    (*c_func) (caddr_t);    /* routine */\n    struct  callout *c_next;\n};\n\n#ifdef KERNEL\nextern struct   callout *callfree, callout[], calltodo;\n#endif\n"
  },
  {
    "path": "sys/sys/clist.h",
    "content": "/*\n * Raw structures for the character list routines.\n *\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\nstruct cblock {\n    struct  cblock *c_next;\n    char    c_info [CBSIZE];\n};\n\n#ifdef KERNEL\nextern struct cblock cfree[];\nstruct  cblock *cfreelist;\nint cfreecount;\n#endif\n"
  },
  {
    "path": "sys/sys/conf.h",
    "content": "#ifndef _CONF_H\n#define _CONF_H\n/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\nstruct uio;\nstruct buf;\nstruct tty;\n\n/*\n * Declaration of block device\n * switch. Each entry (row) is\n * the only link between the\n * main unix code and the driver.\n * The initialization of the\n * device switches is in the\n * file conf.c.\n */\nstruct bdevsw\n{\n    int     (*d_open) (dev_t, int, int);\n    int     (*d_close) (dev_t, int, int);\n    void    (*d_strategy) (struct buf*);\n    daddr_t (*d_psize) (dev_t);                     /* query partition size */\n    int     (*d_ioctl) (dev_t, u_int, caddr_t, int);\n    int     d_flags;                                /* tape flag */\n};\n\n#define MEM_MAJOR       1\n\n/*\n * Character device switch.\n */\nstruct cdevsw\n{\n    int     (*d_open) (dev_t, int, int);\n    int     (*d_close) (dev_t, int, int);\n    int     (*d_read) (dev_t, struct uio*, int);\n    int     (*d_write) (dev_t, struct uio*, int);\n    int     (*d_ioctl) (dev_t, u_int, caddr_t, int);\n    int     (*d_stop) (struct tty*, int);\n    struct tty *d_ttys;\n    int     (*d_select) (dev_t, int);\n    void    (*d_strategy) (struct buf*);\n    char    (*r_read) (dev_t);\n    void    (*r_write) (dev_t, char);\n};\n\n#define UART_MAJOR      6\n#define UARTUSB_MAJOR   7\n#define GPANEL_MAJOR    16\n\n#ifdef KERNEL\n#ifndef CONS_MINOR\n#define CONS_MINOR      0\n#endif\n\nextern const struct bdevsw bdevsw[];\nextern const struct cdevsw cdevsw[];\n\nint rawrw (dev_t dev, struct uio *uio, int flag);\n#endif\n\n#endif\n"
  },
  {
    "path": "sys/sys/config.h",
    "content": "/*\n * Copyright (c) 1992, 1993\n *      The Regents of the University of California.  All rights reserved.\n * Copyright (c) 2015 Serge Vakulenko\n *\n * This code is derived from software contributed to Berkeley by\n * Ralph Campbell.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *      This product includes software developed by the University of\n *      California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n/*\n * This structure is used to encapsulate the routines for a device driver.\n * This allows an \"object oriented\" approach so a controller device driver\n * can support multiple attached devices or a device can be attached to\n * different types of controllers.\n */\nstruct driver {\n    const char  *d_name;        /* driver name for vmstat and iostat */\n    int         (*d_init)();    /* routine to probe & initialize device */\n};\n\n/*\n * This structure describes controllers directly connected to CPU\n * and is partially initialized in \"ioconf.c\" by the 'config' program.\n */\nstruct conf_ctlr {\n    struct driver   *ctlr_driver;   /* controller driver routines */\n    int             ctlr_unit;      /* controller number */\n    char            *ctlr_addr;     /* address of controller */\n    int             ctlr_pri;       /* interrupt priority */\n    int             ctlr_flags;     /* flags */\n\n    int             ctlr_alive;     /* true if init routine succeeded */\n};\n\n/*\n * This structure describes devices connected to an interface\n * and is partially initialized in \"ioconf.c\" by the 'config' program.\n */\nstruct conf_device {\n    struct driver   *dev_driver;    /* device driver routines */\n    struct driver   *dev_cdriver;   /* interface driver routines */\n    int             dev_unit;       /* device unit number */\n    int             dev_ctlr;       /* device interface number */\n    int             dev_drive;      /* device address number */\n    int             dev_flags;      /* flags */\n\n    /* assignment of signals to physical pins */\n#define KCONF_MAXPINS 16\n    char            dev_pins[KCONF_MAXPINS];\n\n    int             dev_alive;      /* true if init routine succeeded */\n};\n\n/*\n * This structure describes optional software services.\n */\nstruct conf_service {\n    void        (*svc_attach)();    /* routine to initialize service */\n};\n\n/* Define special unit types used by the config program */\n#define QUES    -1      /* -1 means '?' */\n#define UNKNOWN -2      /* -2 means not set yet */\n\n#ifdef KERNEL\nextern struct conf_ctlr conf_ctlr_init[];\nextern struct conf_device conf_device_init[];\nextern struct conf_service conf_service_init[];\n#endif\n"
  },
  {
    "path": "sys/sys/dir.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#ifndef _DIR_\n#define _DIR_\n\n#ifndef MAXNAMLEN\n#define MAXNAMLEN   63\n#endif\n\n#define DIRBLKSIZ   1024\n\n/*\n * inode numbers are ino_t rather than u_long now.  before, when v7direct\n * was used for the kernel, inode numbers were u_short/ino_t anyways, and since\n * everything had to be recompiled when the fs structure was changed it seemed\n * like a good idea to change the \"real direct structure\".  SMS\n*/\n\nstruct  direct {\n    ino_t   d_ino;                  /* inode number of entry */\n    u_short d_reclen;               /* length of this record */\n    u_short d_namlen;               /* length of string in d_name */\n    char    d_name[MAXNAMLEN+1];    /* name must be no longer than this */\n};\n\n/*\n * A directory consists of some number of blocks of DIRBLKSIZ\n * bytes, where DIRBLKSIZ is chosen such that it can be transferred\n * to disk in a single atomic operation (e.g. 512 bytes on most machines).\n *\n * Each DIRBLKSIZ byte block contains some number of directory entry\n * structures, which are of variable length.  Each directory entry has\n * a struct direct at the front of it, containing its inode number,\n * the length of the entry, and the length of the name contained in\n * the entry.  These are followed by the name padded to a 4 byte boundary\n * with null bytes.  All names are guaranteed null terminated.\n * The maximum length of a name in a directory is MAXNAMLEN.\n *\n * The macro DIRSIZ(dp) gives the amount of space required to represent\n * a directory entry.  Free space in a directory is represented by\n * entries which have dp->d_reclen > DIRSIZ(dp).  All DIRBLKSIZ bytes\n * in a directory block are claimed by the directory entries.  This\n * usually results in the last entry in a directory having a large\n * dp->d_reclen.  When entries are deleted from a directory, the\n * space is returned to the previous entry in the same directory\n * block by increasing its dp->d_reclen.  If the first entry of\n * a directory block is free, then its dp->d_ino is set to 0.\n * Entries other than the first in a directory do not normally have\n * dp->d_ino set to 0.\n */\n\n#undef DIRSIZ\n#define DIRSIZ(dp) \\\n    ((((sizeof (struct direct) - (MAXNAMLEN+1)) + (dp)->d_namlen+1) + 3) &~ 3)\n\n/*\n * Definitions for library routines operating on directories.\n */\ntypedef struct _dirdesc {\n    int     dd_fd;\n    long    dd_loc;\n    long    dd_size;\n    char    dd_buf[DIRBLKSIZ];\n    struct  direct dd_cur;\n} DIR;\n\n#ifndef NULL\n#define NULL 0\n#endif\n\n#ifndef KERNEL\n\nextern  DIR *opendir (const char *);\nextern  struct direct *readdir (DIR *);\nextern  long telldir (DIR *);\nextern  void seekdir (DIR *, long);\nextern  void closedir (DIR *);\n\n#define rewinddir(dirp) seekdir ((dirp), (long)0)\n#define dirfd(dirp) ((dirp)->dd_fd)\n\n#endif /* !KERNEL */\n\n/*\n * Template for manipulating directories.\n * Should use struct direct's, but the name field\n * is MAXNAMLEN - 1, and this just won't do.\n */\n#define dotdot_ino  dtdt_ino\n#define dotdot_reclen   dtdt_rec\n#define dotdot_name dtdt_name\nstruct dirtemplate {\n    ino_t   dot_ino;\n    u_short dot_reclen;\n    u_short dot_namlen;\n    char    dot_name[4];        /* must be multiple of 4 */\n    ino_t   dotdot_ino;\n    u_short dotdot_reclen;\n    u_short dotdot_namlen;\n    char    dotdot_name[4];     /* ditto */\n};\n#endif /* _DIR_ */\n"
  },
  {
    "path": "sys/sys/disk.h",
    "content": "/*\n * Ioctl definitions for skeleton driver.\n *\n * Copyright (C) 2015 Serge Vakulenko\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#ifndef _SYS_DISK_H_\n#define _SYS_DISK_H_\n\n#include <sys/ioctl.h>\n\n/*\n * IBM PC compatible partition table.\n */\n#define MAXPARTITIONS   4\n#define MBR_MAGIC       0xAA55\n\nstruct diskpart {                   /* the partition table */\n    u_char      dp_status;          /* active (bootable) flag */\n#define DP_ACTIVE 0x80\n    u_char      dp_start_chs[3];    /* ignored */\n    u_char      dp_type;            /* type of partition */\n    u_char      dp_end_chs[3];      /* ignored */\n    u_int       dp_offset;          /* starting sector */\n    u_int       dp_nsectors;        /* number of sectors in partition */\n};\n\n/*\n * Partition types.\n */\n#define PTYPE_UNUSED    0           /* unused */\n#define PTYPE_BSDFFS    0xb7        /* 4.2BSD fast file system */\n#define PTYPE_SWAP      0xb8        /* swap */\n\n/*\n * Disk-specific ioctls.\n */\n#define DIOCGETMEDIASIZE _IOR('d', 1, int)              /* get size in kbytes */\n#define DIOCREINIT       _IO ('d', 2)                   /* re-initialize device */\n#define DIOCGETPART      _IOR('d', 3, struct diskpart)  /* get partition */\n\n#endif /* _SYS_DISK_H_ */\n"
  },
  {
    "path": "sys/sys/dk.h",
    "content": "/*\n * Copyright (c) 1982, 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * Instrumentation\n */\n#define CPUSTATES   4\n\n#define CP_USER     0\n#define CP_NICE     1\n#define CP_SYS      2\n#define CP_IDLE     3\n\n#define DK_NDRIVE   4\n\n#if defined(KERNEL) && defined(UCB_METER)\nlong    cp_time[CPUSTATES];     /* number of ticks spent in each cpu state */\nint     dk_ndrive;              /* number of drives being monitored */\nint     dk_busy;                /* bit array of drive busy flags */\nlong    dk_xfer[DK_NDRIVE];     /* number of transfers */\nlong    dk_bytes[DK_NDRIVE];    /* number of bytes transfered */\nchar    *dk_name[DK_NDRIVE];    /* names of monitored drives */\nint     dk_unit[DK_NDRIVE];     /* unit numbers of monitored drives */\nint     dk_n;                   /* number of dk numbers assigned so far */\n\nlong    tk_nin;                 /* number of tty characters input */\nlong    tk_nout;                /* number of tty characters output */\n#endif\n"
  },
  {
    "path": "sys/sys/dkbad.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *  @(#)dkbad.h 1.1 (2.10BSD Berkeley) 12/1/86\n */\n\n/*\n * Definitions needed to perform bad sector\n * revectoring ala DEC STD 144.\n *\n * The bad sector information is located in the\n * first 5 even numbered sectors of the last\n * track of the disk pack.  There are five\n * identical copies of the information, described\n * by the dkbad structure.\n *\n * Replacement sectors are allocated starting with\n * the first sector before the bad sector information\n * and working backwards towards the beginning of\n * the disk.  A maximum of 126 bad sectors are supported.\n * The position of the bad sector in the bad sector table\n * determines which replacement sector it corresponds to.\n *\n * The bad sector information and replacement sectors\n * are conventionally only accessible through the\n * 'c' file system partition of the disk.  If that\n * partition is used for a file system, the user is\n * responsible for making sure that it does not overlap\n * the bad sector information or any replacement sector.s\n */\n\n/*\n * The 2.10BSD system defines MAXBAD as 32, not 126, although there\n * should be no problem with increasing that value.  It's your basic\n * space tradeoff.  Also, 2.10 drivers tend to have the bad sector\n * information available through the 'h' file system partition, although\n * there are exceptions to this rule.  Note, this value is also present\n * in the bad144 program.\n */\n#define MAXBAD  32          /* Maximum bad sectors supported */\n\nstruct dkbad {\n    long        bt_csn;     /* cartridge serial number */\n    u_short     bt_mbz;     /* unused; should be 0 */\n    u_short     bt_flag;    /* -1 => alignment cartridge */\n    struct bt_bad {\n        u_short bt_cyl;     /* cylinder number of bad sector */\n        u_short bt_trksec;  /* track and sector number */\n    } bt_bad[MAXBAD];\n};\n\n#define ECC     0\n#define SSE     1\n#define BSE     2\n#define CONT    3\n"
  },
  {
    "path": "sys/sys/errno.h",
    "content": "/*\n * Copyright (c) 1982, 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *  @(#)errno.h 7.1.3 (2.11BSD) 1999/9/6\n */\n\n#ifndef KERNEL\nextern  int errno;              /* global error number */\n#endif\n\n#define EPERM           1       /* Not owner */\n#define ENOENT          2       /* No such file or directory */\n#define ESRCH           3       /* No such process */\n#define EINTR           4       /* Interrupted system call */\n#define EIO             5       /* I/O error */\n#define ENXIO           6       /* No such device or address */\n#define E2BIG           7       /* Arg list too long */\n#define ENOEXEC         8       /* Exec format error */\n#define EBADF           9       /* Bad file number */\n#define ECHILD          10      /* No children */\n#define EAGAIN          11      /* No more processes */\n#define ENOMEM          12      /* Not enough core */\n#define EACCES          13      /* Permission denied */\n#define EFAULT          14      /* Bad address */\n#define ENOTBLK         15      /* Block device required */\n#define EBUSY           16      /* Mount device busy */\n#define EEXIST          17      /* File exists */\n#define EXDEV           18      /* Cross-device link */\n#define ENODEV          19      /* No such device */\n#define ENOTDIR         20      /* Not a directory*/\n#define EISDIR          21      /* Is a directory */\n#define EINVAL          22      /* Invalid argument */\n#define ENFILE          23      /* File table overflow */\n#define EMFILE          24      /* Too many open files */\n#define ENOTTY          25      /* Not a typewriter */\n#define ETXTBSY         26      /* Text file busy */\n#define EFBIG           27      /* File too large */\n#define ENOSPC          28      /* No space left on device */\n#define ESPIPE          29      /* Illegal seek */\n#define EROFS           30      /* Read-only file system */\n#define EMLINK          31      /* Too many links */\n#define EPIPE           32      /* Broken pipe */\n\n/* math software */\n#define EDOM            33      /* Argument too large */\n#define ERANGE          34      /* Result too large */\n\n/* non-blocking and interrupt i/o */\n#define EWOULDBLOCK     35      /* Operation would block */\n#define EDEADLK         EWOULDBLOCK /* ditto */\n#define EINPROGRESS     36      /* Operation now in progress */\n#define EALREADY        37      /* Operation already in progress */\n\n/* ipc/network software */\n\n    /* argument errors */\n#define ENOTSOCK        38      /* Socket operation on non-socket */\n#define EDESTADDRREQ    39      /* Destination address required */\n#define EMSGSIZE        40      /* Message too long */\n#define EPROTOTYPE      41      /* Protocol wrong type for socket */\n#define ENOPROTOOPT     42      /* Protocol not available */\n#define EPROTONOSUPPORT 43      /* Protocol not supported */\n#define ESOCKTNOSUPPORT 44      /* Socket type not supported */\n#define EOPNOTSUPP      45      /* Operation not supported on socket */\n#define EPFNOSUPPORT    46      /* Protocol family not supported */\n#define EAFNOSUPPORT    47      /* Address family not supported by protocol family */\n#define EADDRINUSE      48      /* Address already in use */\n#define EADDRNOTAVAIL   49      /* Can't assign requested address */\n\n    /* operational errors */\n#define ENETDOWN        50      /* Network is down */\n#define ENETUNREACH     51      /* Network is unreachable */\n#define ENETRESET       52      /* Network dropped connection on reset */\n#define ECONNABORTED    53      /* Software caused connection abort */\n#define ECONNRESET      54      /* Connection reset by peer */\n#define ENOBUFS         55      /* No buffer space available */\n#define EISCONN         56      /* Socket is already connected */\n#define ENOTCONN        57      /* Socket is not connected */\n#define ESHUTDOWN       58      /* Can't send after socket shutdown */\n#define ETOOMANYREFS    59      /* Too many references: can't splice */\n#define ETIMEDOUT       60      /* Connection timed out */\n#define ECONNREFUSED    61      /* Connection refused */\n\n    /* */\n#define ELOOP           62      /* Too many levels of symbolic links */\n#define ENAMETOOLONG    63      /* File name too long */\n\n/* should be rearranged */\n#define EHOSTDOWN       64      /* Host is down */\n#define EHOSTUNREACH    65      /* No route to host */\n#define ENOTEMPTY       66      /* Directory not empty */\n\n/* quotas & mush */\n#define EPROCLIM        67      /* Too many processes */\n#define EUSERS          68      /* Too many users */\n#define EDQUOT          69      /* Disc quota exceeded */\n\n/* Network File System */\n#define ESTALE          70      /* Stale NFS file handle */\n#define EREMOTE         71      /* Too many levels of remote in path */\n#define EBADRPC         72      /* RPC struct is bad */\n#define ERPCMISMATCH    73      /* RPC version wrong */\n#define EPROGUNAVAIL    74      /* RPC prog. not avail */\n#define EPROGMISMATCH   75      /* Program version wrong */\n#define EPROCUNAVAIL    76      /* Bad procedure for program */\n\n#define ENOLCK          77      /* No locks available */\n#define ENOSYS          78      /* Function not implemented */\n\n#define EFTYPE          79      /* Inappropriate file type or format */\n#define EAUTH           80      /* Authentication error */\n#define ENEEDAUTH       81      /* Need authenticator */\n#define ELAST           81      /* Must be equal largest errno */\n\n#ifdef  KERNEL\n/* pseudo-errors returned inside kernel to modify return back to user mode */\n#define ERESTART        -1      /* restart syscall */\n#define EJUSTRETURN     -2      /* don't modify regs, just return */\n#endif\n"
  },
  {
    "path": "sys/sys/exec.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#ifndef _SYS_EXEC_H_\n#define _SYS_EXEC_H_\n#ifdef KERNEL\n\n#define SHSIZE      64\n#define SHPATHLEN   64\n#define STRLEN      32\n#include \"exec_aout.h\"\n#include \"exec_elf.h\"\n\n#define NO_ADDR     ((caddr_t)(~0U)) /* Indicates addr. not yet filled in */\n\nstruct memsect {\n    caddr_t vaddr;\n    unsigned len;\n};\n\nstruct exec_params {\n    char *userfname;            /* The arguments to the exec() call */\n    char **userargp;\n    char **userenvp;\n    union {\n        char sh[SHSIZE];\n        struct exec aout;\n        struct elf_ehdr elf;\n    } hdr;                      /* head of file to exec */\n    int hdr_len;                /* number of bytes valid in image_header */\n    char **argp, **envp;\n    u_short argc, envc;         /* count of argument and environment strings */\n    u_short argbc, envbc;       /* total number of chars in argc and envc string pool */\n    union {\n        struct {\n            char interpname[20];        /* real name of the script interpreter */\n            char interparg[SHPATHLEN];  /* interpreter arg */\n            char interpreted;           /* flag - this executable is interpreted */\n        } sh;\n        struct {\n            struct buf *stbp;   /* String table buffer pointer */\n            int stbpos;         /* String table pos in buffer */\n            int stsize;         /* String table size */\n            int stoffset;       /* String table file pos */\n            char str[STRLEN];\n        } elf;\n        struct {\n        } aout;\n    };\n\n    gid_t gid;\n    uid_t uid;\n#define MAXALLOCBUF 6\n    struct {\n        struct buf *bp;         /* Memory allocator buffer */\n        u_short fill;           /* Memory allocator \"free\" pointer */\n    } alloc[MAXALLOCBUF];\n    u_long ep_taddr, ep_tsize, ep_daddr, ep_dsize;\n    struct inode *ip;           /* executable file ip */\n    struct memsect text, data, bss, heap, stack;\n};\n\nstruct execsw {\n    int (*es_check)(struct exec_params *epp);\n    const char* es_name;\n};\nextern const struct execsw execsw[];\nextern int nexecs, exec_maxhdrsz;\n\n\nstruct buf *exec_copy_args(char **argp, struct exec_params *epp, int isargv, int *argc, int *argbc);\nint exec_check(struct exec_params *epp);\nvoid exec_setupstack(unsigned entryaddr, struct exec_params *epp);\nvoid exec_alloc_freeall(struct exec_params *epp);\nvoid *exec_alloc(int size, int ru, struct exec_params *epp);\nint exec_estab(struct exec_params *epp);\nvoid exec_save_args(struct exec_params *epp);\nvoid exec_clear(struct exec_params *epp);\n\n#else /* KERNEL */\n#include <sys/exec_aout.h>\n#endif\n#endif\n"
  },
  {
    "path": "sys/sys/exec_aout.h",
    "content": "#ifndef _SYS_EXEC_AOUT_H_\n#define _SYS_EXEC_AOUT_H_\n\n/*\n * Header prepended to each a.out file.\n */\nstruct  exec {\n    unsigned a_midmag;      /* magic number */\n    unsigned a_text;        /* size of text segment */\n    unsigned a_data;        /* size of initialized data */\n    unsigned a_bss;         /* size of uninitialized data */\n    unsigned a_reltext;     /* size of text relocation info */\n    unsigned a_reldata;     /* size of data relocation info */\n    unsigned a_syms;        /* size of symbol table */\n    unsigned a_entry;       /* entry point */\n};\n\n#define a_magic a_midmag & 0xffff\n\n/* a_magic (a_midmag & 0x0000ffff) */\n#define RMAGIC      0406    /* relocatable object file */\n#define OMAGIC      0407    /* old impure format */\n#define NMAGIC      0410    /* read-only text */\n\n/*\n * a_mid ((a_midmag & 0x03ff0000) >> 16)\n */\n#define MID_ZERO    0       /* unknown - implementation dependent */\n#define MID_SUN010  1       /* sun 68010/68020 binary */\n#define MID_SUN020  2       /* sun 68020-only binary */\n#define MID_PC386   100     /* 386 PC binary. (so quoth BFD) */\n#define MID_HP200   200     /* hp200 (68010) BSD binary */\n#define MID_I386    134     /* i386 BSD binary */\n#define MID_M68K    135     /* m68k BSD binary with 8K page sizes */\n#define MID_M68K4K  136     /* m68k BSD binary with 4K page sizes */\n#define MID_NS32532 137     /* ns32532 */\n#define MID_SPARC   138     /* sparc */\n#define MID_PMAX    139     /* pmax */\n#define MID_VAX1K   140     /* vax 1K page size binaries */\n#define MID_ALPHA   141     /* Alpha BSD binary */\n#define MID_MIPS    142     /* big-endian MIPS */\n#define MID_ARM6    143     /* ARM6 */\n#define MID_SH3     145     /* SH3 */\n#define MID_POWERPC 149     /* big-endian PowerPC */\n#define MID_VAX     150     /* vax */\n#define MID_SPARC64 151     /* LP64 sparc */\n#define MID_HP300   300     /* hp300 (68020+68881) BSD binary */\n#define MID_HPUX    0x20C   /* hp200/300 HP-UX binary */\n#define MID_HPUX800 0x20B   /* hp800 HP-UX binary */\n\n/*\n * a_flags ((a_midmag & 0xfc000000 ) << 26)\n */\n#define EX_PIC      0x10\n#define EX_DYNAMIC  0x20\n#define EX_DPMASK   0x30\n/*\n * Interpretation of the (a_flags & EX_DPMASK) bits:\n *\n *  00      traditional executable or object file\n *  01      object file contains PIC code (set by `as -k')\n *  10      dynamic executable\n *  11      position independent executable image\n *          (eg. a shared library)\n */\n\n/*\n * The a.out structure's a_midmag field is a network-byteorder encoding\n * of this int\n *  FFFFFFmmmmmmmmmmMMMMMMMMMMMMMMMM\n * Where `F' is 6 bits of flag like EX_DYNAMIC,\n *       `m' is 10 bits of machine-id like MID_I386, and\n *       `M' is 16 bits worth of magic number, ie. ZMAGIC.\n * The macros below will set/get the needed fields.\n */\n#define N_GETMAGIC(ex)  (((ex).a_midmag)&0x0000ffff)\n#define N_GETMID(ex)    ((((ex).a_midmag)&0x03ff0000) >> 16)\n#define N_GETFLAG(ex)   ((((ex).a_midmag)&0xfc000000 ) << 26)\n\n/* Valid magic number check. */\n#define N_BADMAG(x)     (N_GETMAGIC(x) != RMAGIC && \\\n                         N_GETMAGIC(x) != OMAGIC && \\\n                         N_GETMAGIC(x) != NMAGIC)\n\n/* Text segment offset. */\n#define N_TXTOFF(x)     sizeof(struct exec)\n\n/* Data segment offset. */\n#define N_DATOFF(x)     (N_TXTOFF(x) + (x).a_text)\n\n/* Text relocation table offset. */\n#define N_TRELOFF(x)    (N_DATOFF(x) + (x).a_data)\n\n/* Data relocation table offset. */\n#define N_DRELOFF(x)    (N_TRELOFF(x) + (x).a_reltext)\n\n/* Symbol table offset. */\n#define N_SYMOFF(x)     (N_GETMAGIC(x) == RMAGIC ? \\\n                         N_DRELOFF(x) + (x).a_reldata : \\\n                         N_DATOFF(x) + (x).a_data)\n#endif\n"
  },
  {
    "path": "sys/sys/exec_elf.h",
    "content": "/*  $NetBSD: exec_elf.h,v 1.37.4.1 2000/07/26 23:57:06 mycroft Exp $    */\n\n/*-\n * Copyright (c) 1994 The NetBSD Foundation, Inc.\n * All rights reserved.\n *\n * This code is derived from software contributed to The NetBSD Foundation\n * by Christos Zoulas.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *  This product includes software developed by the NetBSD\n *  Foundation, Inc. and its contributors.\n * 4. Neither the name of The NetBSD Foundation nor the names of its\n *    contributors may be used to endorse or promote products derived\n *    from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS\n * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\n * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n*/\n\n#ifndef _SYS_EXEC_ELF_H_\n#define _SYS_EXEC_ELF_H_\n\n#ifndef _SYS_TYPES_H_\n#include <machine/types.h>\n#endif\n\n/*\n * ELF Header\n */\n#define ELF_NIDENT  16\n\nstruct elf_ehdr {\n    unsigned char   e_ident[ELF_NIDENT];    /* Id bytes */\n    unsigned short  e_type;         /* file type */\n    unsigned short  e_machine;      /* machine type */\n    unsigned int    e_version;      /* version number */\n    unsigned int    e_entry;        /* entry point */\n    unsigned int    e_phoff;        /* Program header table offset */\n    unsigned int    e_shoff;        /* Section header table offset */\n    unsigned int    e_flags;        /* Processor flags (currently unused, should be 0) */\n    unsigned short  e_ehsize;       /* sizeof elf_ehdr */\n    unsigned short  e_phentsize;    /* Program header entry size */\n    unsigned short  e_phnum;        /* Number of program headers */\n    unsigned short  e_shentsize;    /* Section header entry size */\n    unsigned short  e_shnum;        /* Number of section headers */\n    unsigned short  e_shstrndx;     /* String table index */\n};\n\n/* e_ident offsets */\n#define EI_MAG0         0       /* first byte of magic number */\n#define ELFMAG0         0x7f\n#define EI_MAG1         1       /* second byte of magic number */\n#define ELFMAG1         'E'\n#define EI_MAG2         2       /* third byte of magic number */\n#define ELFMAG2         'L'\n#define EI_MAG3         3       /* fourth byte of magic number */\n#define ELFMAG3         'F'\n\n#define EI_CLASS        4       /* 5:th byte: File class */\n#define     ELFCLASSNONE 0      /* Invalid class */\n#define     ELFCLASS32  1       /* 32-bit objects */\n#define     ELFCLASS64  2       /* 64-bit objects */\n#define     ELFCLASSNUM 3\n\n#define EI_DATA         5       /* 6:th byte: Data encoding */\n#define     ELFDATANONE 0       /* Unknown data format */\n#define     ELFDATA2LSB 1       /* two's complement, little-endian */\n#define     ELFDATA2MSB 2       /* two's complement, big-endian */\n\n#define EI_VERSION      6       /* Version number of the ELF specification */\n#define     EV_NONE     0       /* Invalid version */\n#define     EV_CURRENT  1       /* Current version */\n#define     EV_NUM      2\n\n#define EI_OSABI        7       /* Operating system/ABI identification */\n#define     ELFOSABI_SYSV   0   /* UNIX System V ABI */\n#define     ELFOSABI_HPUX   1   /* HP-UX operating system */\n#define     ELFOSABI_NETBSD     /* NetBSD ABI */\n#define     ELFOSABI_LINUX      /* Linux ABI */\n#define     ELFOSABI_SOLARIS    /* Solaris ABI */\n#define     ELFOSABI_FREEBSD    /* FreeBSD ABI */\n#define     ELFOSABI_ARM        /* ARM architecture ABI */\n#define     ELFOSABI_STANDALONE 255 /* Stand-alone (embedded) application */\n\n#define EI_ABIVERSION   8       /* ABI version */\n\n#define EI_PAD          9       /* Start of padding bytes up to EI_NIDENT*/\n\n#define ELFMAG          \"\\177ELF\"\n#define SELFMAG         4\n\n/* e_type */\n#define ET_NONE         0       /* Unknown file type */\n#define ET_REL          1       /* A Relocatable file */\n#define ET_EXEC         2       /* An Executable file */\n#define ET_DYN          3       /* A Shared object file */\n#define ET_CORE         4       /* A Core file */\n#define ET_NUM          5\n\n#define ET_LOOS         0xfe00  /* Operating system specific range */\n#define ET_HIOS         0xfeff\n#define ET_LOPROC       0xff00  /* Processor-specific range */\n#define ET_HIPROC       0xffff\n\n/* e_machine */\n#define EM_NONE         0       /* No machine */\n#define EM_M32          1       /* AT&T WE 32100 */\n#define EM_SPARC        2       /* SPARC */\n#define EM_386          3       /* Intel 80386 */\n#define EM_68K          4       /* Motorola 68000 */\n#define EM_88K          5       /* Motorola 88000 */\n#define EM_486          6       /* Intel 80486 */\n#define EM_860          7       /* Intel 80860 */\n#define EM_MIPS         8       /* MIPS I Architecture */\n#define EM_S370         9       /* Amdahl UTS on System/370 */\n#define EM_MIPS_RS3_LE  10      /* MIPS RS3000 Little-endian */\n#define EM_RS6000       11      /* IBM RS/6000 XXX reserved */\n#define EM_PARISC       15      /* Hewlett-Packard PA-RISC */\n#define EM_NCUBE        16      /* NCube XXX reserved */\n#define EM_VPP500       17      /* Fujitsu VPP500 */\n#define EM_SPARC32PLUS  18      /* Enhanced instruction set SPARC */\n#define EM_960          19      /* Intel 80960 */\n#define EM_PPC          20      /* PowerPC */\n#define EM_V800         36      /* NEC V800 */\n#define EM_FR20         37      /* Fujitsu FR20 */\n#define EM_RH32         38      /* TRW RH-32 */\n#define EM_RCE          39      /* Motorola RCE */\n#define EM_ARM          40      /* Advanced RISC Machines ARM */\n#define EM_ALPHA        41      /* DIGITAL Alpha */\n#define EM_SH           42      /* Hitachi Super-H */\n#define EM_SPARCV9      43      /* SPARC Version 9 */\n#define EM_TRICORE      44      /* Siemens Tricore */\n#define EM_ARC          45      /* Argonaut RISC Core */\n#define EM_H8_300       46      /* Hitachi H8/300 */\n#define EM_H8_300H      47      /* Hitachi H8/300H */\n#define EM_H8S          48      /* Hitachi H8S */\n#define EM_H8_500       49      /* Hitachi H8/500 */\n#define EM_IA_64        50      /* Intel Merced Processor */\n#define EM_MIPS_X       51      /* Stanford MIPS-X */\n#define EM_COLDFIRE     52      /* Motorola Coldfire */\n#define EM_68HC12       53      /* Motorola MC68HC12 */\n#define EM_VAX          75      /* DIGITAL VAX */\n#define EM_ALPHA_EXP    36902   /* used by NetBSD/alpha; obsolete */\n#define EM_NUM          36903\n\n/*\n * ELF Program Header\n */\nstruct elf_phdr {\n    unsigned int    p_type;     /* entry type */\n    unsigned int    p_offset;   /* file offset */\n    unsigned int    p_vaddr;    /* virtual address */\n    unsigned int    p_paddr;    /* physical address (reserved, 0) */\n    unsigned int    p_filesz;   /* file size of segment (may be 0) */\n    unsigned int    p_memsz;    /* memory size of segment (may be 0) */\n    unsigned int    p_flags;    /* flags */\n    unsigned int    p_align;    /* memory & file alignment */\n};\n\n/* p_type */\n#define PT_NULL         0       /* Program header table entry unused */\n#define PT_LOAD         1       /* Loadable program segment */\n#define PT_DYNAMIC      2       /* Dynamic linking information */\n#define PT_INTERP       3       /* Program interpreter */\n#define PT_NOTE         4       /* Auxiliary information */\n#define PT_SHLIB        5       /* Reserved, unspecified semantics */\n#define PT_PHDR         6       /* Entry for header table itself */\n#define PT_NUM          7\n#define PT_LOPROC       0x70000000  /* Start of processor-specific semantics */\n#define PT_HIPROC       0x7fffffff  /* end of processor-specific semantics */\n#define PT_GNU_STACK            /* GNU stack extension */\n\n/* p_flags */\n#define PF_R            0x4     /* Segment is readable */\n#define PF_W            0x2     /* Segment is writable */\n#define PF_X            0x1     /* Segment is executable */\n/* A text segment commonly have PF_X|PF_R, a data segment PF_X|PF_W and PF_R */\n\n#define PF_MASKOS       0x0ff00000  /* Opersting system specific values */\n#define PF_MASKPROC     0xf0000000  /* Processor-specific values */\n\n\n#define PT_MIPS_REGINFO 0x70000000\n\n/*\n * Section Headers\n */\nstruct elf_shdr {\n    unsigned int    sh_name;        /* section name (.shstrtab index) */\n    unsigned int    sh_type;        /* section type */\n    unsigned int    sh_flags;       /* section flags */\n    unsigned int    sh_addr;        /* virtual address */\n    unsigned int    sh_offset;      /* file offset */\n    unsigned int    sh_size;        /* section size */\n    unsigned int    sh_link;        /* link to another */\n    unsigned int    sh_info;        /* misc info */\n    unsigned int    sh_addralign;   /* memory alignment */\n    unsigned int    sh_entsize;     /* table entry size */\n};\n\n/* sh_type */\n#define SHT_NULL        0       /* inactive */\n#define SHT_PROGBITS    1       /* program defined contents */\n#define SHT_SYMTAB      2       /* holds symbol table */\n#define SHT_STRTAB      3       /* holds string table */\n#define SHT_RELA        4       /* holds relocation info with explicit addends */\n#define SHT_HASH        5       /* holds symbol hash table */\n#define SHT_DYNAMIC     6       /* holds dynamic linking information */\n#define SHT_NOTE        7       /* holds information marking */\n#define SHT_NOBITS      8       /* holds a section that does not occupy space */\n#define SHT_REL         9       /* holds relocation info without explicit addends */\n#define SHT_SHLIB       10      /* reserved with unspecified semantics */\n#define SHT_DYNSYM      11      /* holds a minimal set of dynamic linking symbols */\n#define SHT_NUM         12\n\n#define SHT_LOOS        0x60000000  /* Operating system specific range */\n#define SHT_HIOS        0x6fffffff\n#define SHT_LOPROC      0x70000000  /* Processor-specific range */\n#define SHT_HIPROC      0x7fffffff\n#define SHT_LOUSER      0x80000000  /* Application-specific range */\n#define SHT_HIUSER      0xffffffff\n\n/* sh_flags */\n#define SHF_WRITE       0x1         /* Section contains writable data */\n#define SHF_ALLOC       0x2         /* Section occupies memory */\n#define SHF_EXECINSTR   0x4         /* Section contains executable insns */\n\n#define SHF_MASKOS      0x0f000000  /* Operating system specific values */\n#define SHF_MASKPROC    0xf0000000  /* Processor-specific values */\n\n/*\n * Symbol Table\n */\nstruct elf_sym {\n    unsigned int    st_name;    /* Symbol name (.symtab index) */\n    unsigned int    st_value;   /* value of symbol */\n    unsigned int    st_size;    /* size of symbol */\n    unsigned char   st_info;    /* type / binding attrs */\n    unsigned char   st_other;   /* unused */\n    unsigned short  st_shndx;   /* section index of symbol */\n};\n\n/* Symbol Table index of the undefined symbol */\n#define ELF_SYM_UNDEFINED   0\n\n/* st_info: Symbol Bindings */\n#define STB_LOCAL       0   /* local symbol */\n#define STB_GLOBAL      1   /* global symbol */\n#define STB_WEAK        2   /* weakly defined global symbol */\n#define STB_NUM         3\n\n#define STB_LOOS        10  /* Operating system specific range */\n#define STB_HIOS        12\n#define STB_LOPROC      13  /* Processor-specific range */\n#define STB_HIPROC      15\n\n/* st_info: Symbol Types */\n#define STT_NOTYPE      0   /* Type not specified */\n#define STT_OBJECT      1   /* Associated with a data object */\n#define STT_FUNC        2   /* Associated with a function */\n#define STT_SECTION     3   /* Associated with a section */\n#define STT_FILE        4   /* Associated with a file name */\n#define STT_NUM         5\n\n#define STT_LOOS        10  /* Operating system specific range */\n#define STT_HIOS        12\n#define STT_LOPROC      13  /* Processor-specific range */\n#define STT_HIPROC      15\n\n/* st_info utility macros */\n#define ELF_ST_BIND(info)       ((unsigned int)(info) >> 4)\n#define ELF_ST_TYPE(info)       ((unsigned int)(info) & 0xf)\n#define ELF_ST_INFO(bind,type)  ((unsigned char)(((bind) << 4) | ((type) & 0xf)))\n\n/*\n * Special section indexes\n */\n#define SHN_UNDEF       0       /* Undefined section */\n\n#define SHN_LORESERVE   0xff00  /* Start of Reserved range */\n#define SHN_ABS         0xfff1  /*  Absolute symbols */\n#define SHN_COMMON      0xfff2  /*  Common symbols */\n#define SHN_HIRESERVE   0xffff\n\n#define SHN_LOPROC      0xff00  /* Start of Processor-specific range */\n#define SHN_HIPROC      0xff1f\n#define SHN_LOOS        0xff20  /* Operating system specific range */\n#define SHN_HIOS        0xff3f\n\n#define SHN_MIPS_ACOMMON 0xff00\n#define SHN_MIPS_TEXT   0xff01\n#define SHN_MIPS_DATA   0xff02\n#define SHN_MIPS_SCOMMON 0xff03\n\n/*\n * Relocation Entries\n */\nstruct elf_rel {\n    unsigned int    r_offset;   /* where to do it */\n    unsigned int    r_info;     /* index & type of relocation */\n};\n\nstruct elf_rela {\n    unsigned int    r_offset;   /* where to do it */\n    unsigned int    r_info;     /* index & type of relocation */\n    int             r_addend;   /* adjustment value */\n};\n\n/* r_info utility macros */\n#define ELF_R_SYM(info)         ((info) >> 8)\n#define ELF_R_TYPE(info)        ((info) & 0xff)\n#define ELF_R_INFO(sym, type)   (((sym) << 8) + (unsigned char)(type))\n\n/*\n * Dynamic Section structure array\n */\nstruct elf_dyn {\n    unsigned int        d_tag;  /* entry tag value */\n    union {\n        unsigned int    d_ptr;\n        unsigned int    d_val;\n    } d_un;\n};\n\n/* d_tag */\n#define DT_NULL         0   /* Marks end of dynamic array */\n#define DT_NEEDED       1   /* Name of needed library (DT_STRTAB offset) */\n#define DT_PLTRELSZ     2   /* Size, in bytes, of relocations in PLT */\n#define DT_PLTGOT       3   /* Address of PLT and/or GOT */\n#define DT_HASH         4   /* Address of symbol hash table */\n#define DT_STRTAB       5   /* Address of string table */\n#define DT_SYMTAB       6   /* Address of symbol table */\n#define DT_RELA         7   /* Address of Rela relocation table */\n#define DT_RELASZ       8   /* Size, in bytes, of DT_RELA table */\n#define DT_RELAENT      9   /* Size, in bytes, of one DT_RELA entry */\n#define DT_STRSZ        10  /* Size, in bytes, of DT_STRTAB table */\n#define DT_SYMENT       11  /* Size, in bytes, of one DT_SYMTAB entry */\n#define DT_INIT         12  /* Address of initialization function */\n#define DT_FINI         13  /* Address of termination function */\n#define DT_SONAME       14  /* Shared object name (DT_STRTAB offset) */\n#define DT_RPATH        15  /* Library search path (DT_STRTAB offset) */\n#define DT_SYMBOLIC     16  /* Start symbol search within local object */\n#define DT_REL          17  /* Address of Rel relocation table */\n#define DT_RELSZ        18  /* Size, in bytes, of DT_REL table */\n#define DT_RELENT       19  /* Size, in bytes, of one DT_REL entry */\n#define DT_PLTREL       20  /* Type of PLT relocation entries */\n#define DT_DEBUG        21  /* Used for debugging; unspecified */\n#define DT_TEXTREL      22  /* Relocations might modify non-writable seg */\n#define DT_JMPREL       23  /* Address of relocations associated with PLT */\n#define DT_BIND_NOW     24  /* Process all relocations at load-time */\n#define DT_INIT_ARRAY   25  /* Address of initialization function array */\n#define DT_FINI_ARRAY   26  /* Size, in bytes, of DT_INIT_ARRAY array */\n#define DT_INIT_ARRAYSZ 27  /* Address of termination function array */\n#define DT_FINI_ARRAYSZ 28  /* Size, in bytes, of DT_FINI_ARRAY array*/\n#define DT_NUM          29\n\n#define DT_LOOS     0x60000000  /* Operating system specific range */\n#define DT_HIOS     0x6fffffff\n#define DT_LOPROC   0x70000000  /* Processor-specific range */\n#define DT_HIPROC   0x7fffffff\n\n/*\n * Auxiliary Vectors\n */\nstruct elf_auxinfo {\n    unsigned int    a_type;     /* 32-bit id */\n    unsigned int    a_v;        /* 32-bit id */\n};\n\n/* a_type */\n#define AT_NULL         0       /* Marks end of array */\n#define AT_IGNORE       1       /* No meaning, a_un is undefined */\n#define AT_EXECFD       2       /* Open file descriptor of object file */\n#define AT_PHDR         3       /* &phdr[0] */\n#define AT_PHENT        4       /* sizeof(phdr[0]) */\n#define AT_PHNUM        5       /* # phdr entries */\n#define AT_PAGESZ       6       /* PAGESIZE */\n#define AT_BASE         7       /* Interpreter base addr */\n#define AT_FLAGS        8       /* Processor flags */\n#define AT_ENTRY        9       /* Entry address of executable */\n#define AT_DCACHEBSIZE  10      /* Data cache block size */\n#define AT_ICACHEBSIZE  11      /* Instruction cache block size */\n#define AT_UCACHEBSIZE  12      /* Unified cache block size */\n\n    /* Vendor specific */\n#define AT_MIPS_NOTELF  10      /* XXX a_val != 0 -> MIPS XCOFF executable */\n\n#define AT_SUN_UID      2000    /* euid */\n#define AT_SUN_RUID     2001    /* ruid */\n#define AT_SUN_GID      2002    /* egid */\n#define AT_SUN_RGID     2003    /* rgid */\n\n    /* Solaris kernel specific */\n#define AT_SUN_LDELF    2004    /* dynamic linker's ELF header */\n#define AT_SUN_LDSHDR   2005    /* dynamic linker's section header */\n#define AT_SUN_LDNAME   2006    /* dynamic linker's name */\n#define AT_SUN_LPGSIZE  2007    /* large pagesize */\n\n    /* Other information */\n#define AT_SUN_PLATFORM 2008    /* sysinfo(SI_PLATFORM) */\n#define AT_SUN_HWCAP    2009    /* process hardware capabilities */\n#define AT_SUN_IFLUSH   2010    /* do we need to flush the instruction cache? */\n#define AT_SUN_CPU      2011    /* cpu name */\n    /* ibcs2 emulation band aid */\n#define AT_SUN_EMUL_ENTRY 2012  /* coff entry point */\n#define AT_SUN_EMUL_EXECFD 2013 /* coff file descriptor */\n    /* Executable's fully resolved name */\n#define AT_SUN_EXECNAME 2014\n\n/*\n * Note Headers\n */\nstruct elf_nhdr {\n\n    unsigned int    n_namesz;\n    unsigned int    n_descsz;\n    unsigned int    n_type;\n};\n\n#define ELF_NOTE_TYPE_OSVERSION     1\n\n/* NetBSD-specific note type: Emulation name.  desc is emul name string. */\n#define ELF_NOTE_NETBSD_TYPE_EMULNAME 2\n\n/* NetBSD-specific note name and description sizes */\n#define ELF_NOTE_NETBSD_NAMESZ      7\n#define ELF_NOTE_NETBSD_DESCSZ      4\n/* NetBSD-specific note name */\n#define ELF_NOTE_NETBSD_NAME        \"NetBSD\\0\\0\"\n\n/* GNU-specific note name and description sizes */\n#define ELF_NOTE_GNU_NAMESZ         4\n#define ELF_NOTE_GNU_DESCSZ         4\n/* GNU-specific note name */\n#define ELF_NOTE_GNU_NAME           \"GNU\\0\"\n\n/* GNU-specific OS/version value stuff */\n#define ELF_NOTE_GNU_OSMASK         (unsigned int)0xff000000\n#define ELF_NOTE_GNU_OSLINUX        (unsigned int)0x01000000\n#define ELF_NOTE_GNU_OSMACH         (unsigned int)0x00000000\n\n#include <machine/elf_machdep.h>\n\n#ifdef _KERNEL\n\n#define ELF_AUX_ENTRIES     8       /* Size of aux array passed to loader */\n\nstruct elf_args {\n    unsigned int    arg_entry;      /* program entry point */\n    unsigned int    arg_interp;     /* Interpreter load address */\n    unsigned int    arg_phaddr;     /* program header address */\n    unsigned int    arg_phentsize;  /* Size of program header */\n    unsigned int    arg_phnum;      /* Number of program headers */\n};\n\n#ifndef _LKM\n#include \"opt_execfmt.h\"\n#endif\n\nint exec_elf_makecmds __P((struct proc *, struct exec_package *));\nint elf_read_from __P((struct proc *, struct vnode *, u_long,\n        caddr_t, int));\nvoid    *elf_copyargs __P((struct exec_package *, struct ps_strings *,\n        void *, void *));\n\n/* common */\nint exec_elf_setup_stack __P((struct proc *, struct exec_package *));\n\n#endif /* _KERNEL */\n\n#endif /* !_SYS_EXEC_ELF_H_ */\n"
  },
  {
    "path": "sys/sys/fcntl.h",
    "content": "/*-\n * Copyright (c) 1983, 1990, 1993\n *  The Regents of the University of California.  All rights reserved.\n * (c) UNIX System Laboratories, Inc.\n * All or some portions of this file are derived from material licensed\n * to the University of California by American Telephone and Telegraph\n * Co. or Unix System Laboratories, Inc. and are reproduced herein with\n * the permission of UNIX System Laboratories, Inc.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *  This product includes software developed by the University of\n *  California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n *  @(#)fcntl.h 8.3.1 (2.11BSD GTE) 11/25/94\n *\n * Copied from 4.4-Lite and modified for 2.11BSD.  The modifications consisted\n * of removing: function prototypes (I don't like them, the compiler does not\n * support them, and it would mean dragging in cdefs.h to leave them in here),\n * #ifndef _POSIX_SOURCE lines (silly) and record locking related definitions\n * If anyone adds any of the above it will be easy enough to modify this file.\n * In the meantime why bog down (or blow up) cpp any further?\n */\n\n#ifndef _FCNTL_H_\n#define _FCNTL_H_\n\n/*\n * This file includes the definitions for open and fcntl\n * described by POSIX for <fcntl.h>; it also includes\n * related kernel definitions.\n */\n\n#ifndef KERNEL\n#include <sys/types.h>\n#endif\n\n/*\n * File status flags: these are used by open(2), fcntl(2).\n * They are also used (indirectly) in the kernel file structure f_flags,\n * which is a superset of the open/fcntl flags.  Open flags and f_flags\n * are inter-convertible using OFLAGS(fflags) and FFLAGS(oflags).\n * Open/fcntl flags begin with O_; kernel-internal flags begin with F.\n */\n/* open-only flags */\n#define O_RDONLY    0x0000      /* open for reading only */\n#define O_WRONLY    0x0001      /* open for writing only */\n#define O_RDWR      0x0002      /* open for reading and writing */\n#define O_ACCMODE   0x0003      /* mask for above modes */\n\n/*\n * Kernel encoding of open mode; separate read and write bits that are\n * independently testable: 1 greater than the above.\n *\n * XXX\n * FREAD and FWRITE are excluded from the #ifdef KERNEL so that TIOCFLUSH,\n * which was documented to use FREAD/FWRITE, continues to work.\n */\n#define FREAD       0x0001\n#define FWRITE      0x0002\n#define O_NONBLOCK  0x0004      /* no delay */\n#define O_APPEND    0x0008      /* set append mode */\n#define O_SHLOCK    0x0010      /* open with shared file lock */\n#define O_EXLOCK    0x0020      /* open with exclusive file lock */\n#define O_ASYNC     0x0040      /* signal pgrp when data ready */\n#define O_FSYNC     0x0080      /* synchronous writes */\n#define O_CREAT     0x0200      /* create if nonexistant */\n#define O_TRUNC     0x0400      /* truncate to zero length */\n#define O_EXCL      0x0800      /* error if already exists */\n#ifdef KERNEL\n#define FMARK       0x1000      /* mark during gc() */\n#define FDEFER      0x2000      /* defer for next gc pass */\n#endif\n\n/* defined by POSIX 1003.1; not 2.11BSD default, so bit is required */\n/* Not currently implemented but it may be placed on the TODO list shortly */\n#define O_NOCTTY    0x4000      /* don't assign controlling terminal */\n\n#ifdef KERNEL\n/* convert from open() flags to/from fflags; convert O_RD/WR to FREAD/FWRITE */\n#define FFLAGS(oflags)  ((oflags) + 1)\n#define OFLAGS(fflags)  ((fflags) - 1)\n\n/* bits to save after open */\n#define FMASK       (FREAD|FWRITE|FAPPEND|FASYNC|FFSYNC|FNONBLOCK)\n/* bits settable by fcntl(F_SETFL, ...) */\n#define FCNTLFLAGS  (FAPPEND|FASYNC|FFSYNC|FNONBLOCK)\n#endif\n\n/*\n * The O_* flags used to have only F* names, which were used in the kernel\n * and by fcntl.  We retain the F* names for the kernel f_flags field\n * and for backward compatibility for fcntl.\n */\n#define FAPPEND     O_APPEND    /* kernel/compat */\n#define FASYNC      O_ASYNC     /* kernel/compat */\n#define FFSYNC      O_FSYNC     /* kernel */\n#define FEXLOCK     O_EXLOCK    /* kernel */\n#define FSHLOCK     O_SHLOCK    /* kernel */\n#define FNONBLOCK   O_NONBLOCK  /* kernel */\n#define FNDELAY     O_NONBLOCK  /* compat */\n#define O_NDELAY    O_NONBLOCK  /* compat */\n\n/*\n * Constants used for fcntl(2)\n */\n\n/* command values */\n#define F_DUPFD     0       /* duplicate file descriptor */\n#define F_GETFD     1       /* get file descriptor flags */\n#define F_SETFD     2       /* set file descriptor flags */\n#define F_GETFL     3       /* get file status flags */\n#define F_SETFL     4       /* set file status flags */\n#define F_GETOWN    5       /* get SIGIO/SIGURG proc/pgrp */\n#define F_SETOWN    6       /* set SIGIO/SIGURG proc/pgrp */\n\n/* file descriptor flags (F_GETFD, F_SETFD) */\n#define FD_CLOEXEC  1       /* close-on-exec flag */\n\n/* lock operations for flock(2) */\n#define LOCK_SH     0x01    /* shared file lock */\n#define LOCK_EX     0x02    /* exclusive file lock */\n#define LOCK_NB     0x04    /* don't block when locking */\n#define LOCK_UN     0x08    /* unlock file */\n\n#endif /* !_FCNTL_H_ */\n"
  },
  {
    "path": "sys/sys/file.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#include <sys/fcntl.h>\n\n#ifndef _SYS_FILE_H_\n#define _SYS_FILE_H_\n\n/*\n * Descriptor table entry.\n * One for each kernel object.\n */\nstruct  file {\n    int     f_flag;         /* see below */\n    int     f_type;         /* descriptor type */\n    u_int   f_count;        /* reference count */\n    int     f_msgcount;     /* references from message queue */\n    union {\n        caddr_t f_Data;\n        struct socket *f_Socket;\n    } f_un;\n    off_t   f_offset;\n};\n\n#ifdef KERNEL\nstruct uio;\n\nstruct  fileops {\n    int (*fo_rw) (struct file *fp, struct uio *uio);\n    int (*fo_ioctl) (struct file *fp, u_int com, char *data);\n    int (*fo_select) (struct file *fp, int flag);\n    int (*fo_close) (struct file *fp);\n};\n\n#define f_data      f_un.f_Data\n#define f_socket    f_un.f_Socket\n\nextern struct file file[];\nextern const struct fileops *const Fops[];\nextern const struct fileops inodeops;\nextern const struct fileops pipeops;\n\n/*\n * Convert a user supplied file descriptor into a pointer to a file structure.\n */\nstruct file *getf (int f);\n\n/*\n * Allocate a user file descriptor and a file structure.\n */\nstruct file *falloc (void);\n\n/*\n * Internal form of close.\n */\nint closef (struct file *fp);\n\n/*\n * Set/clear file flags: nonblock and async.\n */\nint fset (struct file *fp, int bit, int value);\n\n/*\n * Get/set process group id for a file.\n */\nint fgetown (struct file *fp, int *valuep);\nint fsetown (struct file *fp, int value);\n\n/*\n * File table inode close routine.\n */\nint vn_closefile (struct file *fp);\n\n/*\n * Place an advisory lock on an inode.\n */\nint ino_lock (struct file *fp, int cmd);\n\n/*\n * Unlock a file.\n */\nvoid ino_unlock (struct file *fp, int kind);\n\nint ino_ioctl (struct file *fp, u_int com, caddr_t data);\n\n#else /* KERNEL */\n\nint flock(int fd, int operation);\n\n#endif /* KERNEL */\n\n/*\n * Access call.\n */\n#define F_OK    0   /* does file exist */\n#define X_OK    1   /* is it executable by caller */\n#define W_OK    2   /* writable by caller */\n#define R_OK    4   /* readable by caller */\n\n/*\n * Lseek call.\n */\n#define L_SET   0   /* absolute offset */\n#define L_INCR  1   /* relative to current offset */\n#define L_XTND  2   /* relative to end of file */\n\n#ifdef KERNEL\n#define GETF(fp, fd) { \\\n    if ((unsigned)(fd) >= NOFILE || ((fp) = u.u_ofile[fd]) == NULL) { \\\n        u.u_error = EBADF; \\\n        return; \\\n    } \\\n}\n#define DTYPE_INODE     1   /* file */\n#define DTYPE_SOCKET    2   /* communications endpoint */\n#define DTYPE_PIPE      3   /* I don't want to hear it, okay? */\n#endif\n#endif  /* _SYS_FILE_H_ */\n"
  },
  {
    "path": "sys/sys/fs.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#ifndef _SYS_FS_H_\n#define _SYS_FS_H_\n\n/*\n * The root inode is the root of the file system.\n * Inode 0 can't be used for normal purposes and\n * historically bad blocks were linked to inode 1,\n * thus the root inode is 2. (inode 1 is no longer used for\n * this purpose, however numerous dump tapes make this\n * assumption, so we are stuck with it)\n * The lost+found directory is given the next available\n * inode when it is created by ``mkfs''.\n */\n#define SBSIZE          DEV_BSIZE\n#define SUPERB          ((daddr_t)0)    /* block number of the super block */\n\n#define ROOTINO         ((ino_t)2)      /* i number of all roots */\n#define LOSTFOUNDINO    (ROOTINO + 1)\n\n#define NICINOD         32      /* number of superblock inodes */\n#define NICFREE         200     /* number of superblock free blocks */\n\n/*\n * The path name on which the file system is mounted is maintained\n * in fs_fsmnt. MAXMNTLEN defines the amount of space allocated in\n * the super block for this name.\n */\n#define MAXMNTLEN       28\n\n/*\n * Super block for a file system.  NOTE:  The 'fs_flock' and 'fs_ilock'\n * fields MUST be on an even byte boundary because they are used as sleep()\n * channels and odd values specify a network sleep().\n */\nstruct  fs\n{\n    u_int   fs_magic1;              /* magic word */\n    u_int   fs_isize;               /* first block after i-list */\n    u_int   fs_fsize;               /* size in blocks of entire volume */\n    u_int   fs_swapsz;              /* size in blocks of swap area */\n    int fs_nfree;                   /* number of addresses in fs_free */\n    daddr_t fs_free [NICFREE];      /* free block list */\n    int fs_ninode;                  /* number of inodes in fs_inode */\n    ino_t   fs_inode [NICINOD];     /* free inode list */\n    int     fs_flock;               /* lock during free list manipulation */\n    int     fs_fmod;                /* super block modified flag */\n    int     fs_ilock;               /* lock during i-list manipulation */\n    int     fs_ronly;               /* mounted read-only flag */\n    time_t  fs_time;                /* last super block update */\n    u_int   fs_tfree;               /* total free blocks */\n    ino_t   fs_tinode;              /* total free inodes */\n    char    fs_fsmnt [MAXMNTLEN];   /* ordinary file mounted on */\n    ino_t   fs_lasti;               /* start place for circular search */\n    ino_t   fs_nbehind;             /* est # free inodes before s_lasti */\n    u_int   fs_flags;               /* mount time flags */\n    u_int   fs_magic2;              /* magic word */\n/* actually longer */\n};\n\nstruct  fblk {\n    int     df_nfree;               /* number of addresses in df_free */\n    daddr_t df_free [NICFREE];      /* free block list */\n};\n\n#define FSMAGIC1    ('F' | 'S'<<8 | '<'<<16 | '<'<<24)\n#define FSMAGIC2    ('>' | '>'<<8 | 'F'<<16 | 'S'<<24)\n\n/*\n * Turn file system block numbers into disk block addresses.\n * This maps file system blocks to device size blocks.\n */\n#define fsbtodb(b)  ((daddr_t) (b))\n#define dbtofsb(b)  ((daddr_t) (b))\n\n/*\n * Macros for handling inode numbers:\n *     inode number to file system block offset.\n *     inode number to file system block address.\n */\n#define itoo(x)     ((int)(((x) + INOPB - 1) % INOPB))\n#define itod(x)     ((daddr_t)((((u_int)(x) + INOPB - 1) / INOPB)))\n\n/*\n * The following macros optimize certain frequently calculated\n * quantities by using shifts and masks in place of divisions\n * modulos and multiplications.\n */\n#define blkoff(loc)             /* calculates (loc % fs->fs_bsize) */ \\\n                    ((loc) & DEV_BMASK)\n#define lblkno(loc)             /* calculates (loc / fs->fs_bsize) */ \\\n                    ((unsigned) (loc) >> DEV_BSHIFT)\n\n/*\n * Determine the number of available blocks given a\n * percentage to hold in reserve\n */\n#define freespace(fs, percentreserved) \\\n    ((fs)->fs_tfree - ((fs)->fs_fsize - \\\n    (fs)->fs_isize) * (percentreserved) / 100)\n\n/*\n * INOPB is the number of inodes in a secondary storage block.\n */\n#define INOPB       16          /* MAXBSIZE / sizeof(dinode) */\n\n/*\n * NINDIR is the number of indirects in a file system block.\n */\n#define NINDIR      (DEV_BSIZE / sizeof(daddr_t))\n#define NSHIFT      8           /* log2(NINDIR) */\n#define NMASK       0377L       /* NINDIR - 1 */\n\n/*\n * We continue to implement pipes within the file system because it would\n * be pretty tough for us to handle 10 4K blocked pipes on a 1M machine.\n *\n * 4K is the allowable buffering per write on a pipe.  This is also roughly\n * the max size of the file created to implement the pipe.  If this size is\n * bigger than 4096, pipes will be implemented with large files, which is\n * probably not good.\n */\n#define MAXPIPSIZ   (NDADDR * MAXBSIZE)\n\n#ifdef KERNEL\nstruct inode;\n\n/*\n * Map a device number into a pointer to the incore super block.\n */\nstruct fs *getfs (dev_t dev);\n\n/*\n * Mount a filesystem on the given directory inode.\n */\nstruct fs *mountfs (dev_t dev, int flags, struct inode *ip);\n\nvoid mount_updname (struct fs *fs, char *on, char *from,\n    int lenon, int lenfrom);\n\n/*\n * Sync a single filesystem.\n */\nstruct mount;\nint ufs_sync (struct mount *mp);\n\n/*\n * Check that a specified block number is in range.\n */\nint badblock (struct fs *fp, daddr_t bn);\n\n/*\n * Print the name of a file system with an error diagnostic.\n */\nvoid fserr (struct fs *fp, char *message);\n\n#endif /* KERNEL */\n\n#endif /* _SYS_FS_H_ */\n"
  },
  {
    "path": "sys/sys/glcd.h",
    "content": "#ifndef _GLCD_H\n#define _GLCD_H\n\n#include <sys/ioctl.h>\n#include <sys/uio.h>\n\n/* G13 */\n#define TRIS_DI\t\t\tTRISG\n#define LAT_DI\t\t\tLATG\n#define PORT_DI\t\t\tPORTG\n#define PIN_DI\t\t\t13\n\n/* G12 */\n#define TRIS_RW\t\t\tTRISG\n#define LAT_RW\t\t\tLATG\n#define PORT_RW\t\t\tPORTG\n#define PIN_RW\t\t\t12\n\n/* G14 */\n#define TRIS_E\t\t\tTRISG\n#define LAT_E\t\t\tLATG\n#define PORT_E\t\t\tPORTG\n#define PIN_E\t\t\t14\n\n/* E1 */\n#define TRIS_DB0\t\tTRISE\n#define LAT_DB0\t\t\tLATE\n#define PORT_DB0\t\tPORTE\n#define PIN_DB0\t\t\t1\n\n/* E0 */\n#define TRIS_DB1\t\tTRISE\n#define LAT_DB1\t\t\tLATE\n#define PORT_DB1\t\tPORTE\n#define PIN_DB1\t\t\t0\n\n/* A7 */\n#define TRIS_DB2\t\tTRISA\n#define LAT_DB2\t\t\tLATA\n#define PORT_DB2\t\tPORTA\n#define PIN_DB2\t\t\t7\n\n/* A6 */\n#define TRIS_DB3\t\tTRISA\n#define LAT_DB3\t\t\tLATA\n#define PORT_DB3\t\tPORTA\n#define PIN_DB3\t\t\t6\n\n/* G0 */\n#define TRIS_DB4\t\tTRISG\n#define LAT_DB4\t\t\tLATG\n#define PORT_DB4\t\tPORTG\n#define PIN_DB4\t\t\t0\n\n/* G1 */\n#define TRIS_DB5\t\tTRISG\n#define LAT_DB5\t\t\tLATG\n#define PORT_DB5\t\tPORTG\n#define PIN_DB5\t\t\t1\n\n/* F1 */\n#define TRIS_DB6\t\tTRISF\n#define LAT_DB6\t\t\tLATF\n#define PORT_DB6\t\tPORTF\n#define PIN_DB6\t\t\t1\n\n/* F0 */\n#define TRIS_DB7\t\tTRISF\n#define LAT_DB7\t\t\tLATF\n#define PORT_DB7\t\tPORTF\n#define PIN_DB7\t\t\t0\n\n/* D7 */\n#define TRIS_CS1\t\tTRISD\n#define LAT_CS1\t\t\tLATD\n#define PORT_CS1\t\tPORTD\n#define PIN_CS1\t\t\t7\n\n/* D6 */\n#define TRIS_CS2\t\tTRISD\n#define LAT_CS2\t\t\tLATD\n#define PORT_CS2\t\tPORTD\n#define PIN_CS2\t\t\t6\n\n/* D5 */\n#define TRIS_RES\t\tTRISD\n#define LAT_RES\t\t\tLATD\n#define PORT_RES\t\tPORTD\n#define PIN_RES\t\t\t5\n\n#define GLCD_CMD_OFF\t\t0b00111110\n#define GLCD_CMD_ON\t\t0b00111111\n#define GLCD_CMD_SET_Y\t\t0b01000000\n#define GLCD_CMD_SET_PAGE\t0b10111000\n#define GLCD_CMD_START\t\t0b11000000\n\n#define INPUT\t\t\t1\n#define OUTPUT\t\t\t0\n\n#define HIGH\t\t\t1\n#define LOW\t\t\t0\n\n#define DATA\t\t\t1\n#define INSTRUCTION\t\t0\n\n#define READ\t\t\t1\n#define WRITE\t\t\t0\n\n#define ENABLE\t\t\t1\n#define DISABLE\t\t\t0\n\n#define GLCD_STAT_BUSY\t\t0b10000000\n#define GLCD_STAT_ONOFF\t\t0b00100000\n#define GLCD_STAT_RESET\t\t0b00010000\n\n/* glcd interface */\n\nstruct glcd_command {\n\tu_char x1;\n\tu_char y1;\n\tu_char x2;\n\tu_char y2;\n\tu_char ink;\n};\n\n#define GLCD_RESET\t\t_IOW('i', 1, struct glcd_command)\n#define GLCD_CLS\t\t_IOW('i', 2, struct glcd_command)\n#define GLCD_LOAD_PAGE\t\t_IOW('i', 3, struct glcd_command)\n#define GLCD_UPDATE\t\t_IOW('i', 4, struct glcd_command)\n#define GLCD_SET_PIXEL\t\t_IOW('i', 5, struct glcd_command)\n#define GLCD_CLEAR_PIXEL\t_IOW('i', 6, struct glcd_command)\n#define GLCD_LINE\t\t_IOW('i', 7, struct glcd_command)\n#define GLCD_BOX\t\t_IOW('i', 8, struct glcd_command)\n#define GLCD_FILLED_BOX\t\t_IOW('i', 9, struct glcd_command)\n#define GLCD_GOTO_XY\t\t_IOW('i', 10, struct glcd_command)\n\n#ifdef KERNEL\n#include \"conf.h\"\n\nextern int glcd_open(dev_t dev, int flag, int mode);\nextern int glcd_close(dev_t dev, int flag, int mode);\nextern int glcd_read(dev_t dev, struct uio *uio, int flag);\nextern int glcd_write(dev_t dev, struct uio *uio, int flag);\nextern int glcd_ioctl(dev_t dev, u_int cmd, caddr_t addr, int flag);\n#endif\n\n#endif\n"
  },
  {
    "path": "sys/sys/glob.h",
    "content": "#ifndef _GLOB_H\n#define _GLOB_H\n\n#ifdef KERNEL\nextern void rdglob();\nextern void wrglob();\n#else\nextern int rdglob(int);\nextern int wrglob(int,int);\n#endif\n\n#endif\n"
  },
  {
    "path": "sys/sys/gpanel.h",
    "content": "/*\n * Generic interface to a graphics panel device (TFT LCD, OLED and others).\n *\n * Copyright (C) 2015 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#ifndef _GPANEL_H\n#define _GPANEL_H\n\n/*\n * Proportional/fixed font structure.\n */\nstruct gpanel_font_t {\n    const char *    name;           /* font name */\n    int             maxwidth;       /* max width in pixels */\n    unsigned int    height;         /* height in pixels */\n    int             ascent;         /* ascent (baseline) height */\n    int             firstchar;      /* first character in bitmap */\n    int             size;           /* font size in characters */\n    const unsigned short *bits;     /* 16-bit right-padded bitmap data */\n    const unsigned short *offset;   /* offsets into bitmap data */\n    const unsigned char *width;     /* character widths or 0 if fixed */\n    int             defaultchar;    /* default char (not glyph index) */\n    long            bits_size;      /* # words of bits */\n};\n\nstruct gpanel_pixel_t {\n    int             color;          /* pixel color */\n    int             x, y;           /* pixel position */\n};\n\nstruct gpanel_clear_t {\n    int             color;          /* pixel color */\n    int             xsize, ysize;   /* screen size */\n};\n\nstruct gpanel_line_t {\n    int             color;          /* line color */\n    int             x0, y0;         /* start point */\n    int             x1, y1;         /* end point */\n};\n\nstruct gpanel_rect_t {\n    int             color;          /* border or fill color */\n    int             x0, y0;         /* start point */\n    int             x1, y1;         /* end point */\n};\n\nstruct gpanel_circle_t {\n    int             color;          /* border color */\n    int             x, y;           /* center point */\n    int             radius;         /* circle radius */\n};\n\nstruct gpanel_image_t {\n    int             x, y;           /* start point */\n    int             width, height;  /* image size radius */\n    const unsigned short *image;    /* array of pixels */\n};\n\nstruct gpanel_char_t {\n    const struct gpanel_font_t *font; /* font data */\n    int             color;          /* text color */\n    int             background;     /* background color or -1 for transparent */\n    int             x, y;           /* position */\n    int             sym;            /* unicode symbol index */\n};\n\nstruct gpanel_text_t {\n    const struct gpanel_font_t *font; /* font data */\n    int             color;          /* text color */\n    int             background;     /* background color or -1 for transparent */\n    int             x, y;           /* position */\n    const char      *text;          /* UTF-8 text */\n};\n\n#define GPANEL_CLEAR       _IOW('g', 1, struct gpanel_clear_t)\n#define GPANEL_PIXEL       _IOW('g', 2, struct gpanel_pixel_t)\n#define GPANEL_LINE        _IOW('g', 3, struct gpanel_line_t)\n#define GPANEL_RECT        _IOW('g', 4, struct gpanel_rect_t)\n#define GPANEL_FILL        _IOW('g', 5, struct gpanel_rect_t)\n#define GPANEL_CIRCLE      _IOW('g', 6, struct gpanel_circle_t)\n#define GPANEL_IMAGE       _IOW('g', 7, struct gpanel_image_t)\n#define GPANEL_CHAR        _IOW('g', 8, struct gpanel_char_t)\n#define GPANEL_TEXT        _IOW('g', 9, struct gpanel_text_t)\n\n#ifndef KERNEL\n/*\n * User-level library.\n */\nint gpanel_open(const char *devname);\nvoid gpanel_close(void);\nvoid gpanel_clear(int color, int *xsize, int *ysize);\nvoid gpanel_pixel(int color, int x, int y);\nvoid gpanel_line(int color, int x0, int y0, int x1, int y1);\nvoid gpanel_rect(int color, int x0, int y0, int x1, int y1);\nvoid gpanel_fill(int color, int x0, int y0, int x1, int y1);\nvoid gpanel_fill_triangle(int color, int x0, int y0, int x1, int y1, int x2, int y2);\nvoid gpanel_circle(int color, int x, int y, int radius);\nvoid gpanel_image(int x, int y, int width, int height, const unsigned short *data);\nvoid gpanel_char(const struct gpanel_font_t *font, int color, int background, int x, int y, int sym);\nvoid gpanel_text(const struct gpanel_font_t *font, int color, int background, int x, int y, const char *text);\nint gpanel_text_width(const struct gpanel_font_t *font, const char *text, int nchars);\n\nextern int _gpanel_fd;\n\n#else /* KERNEL */\n/*\n * Kernel driver routines.\n */\nstruct uio;\nextern int gpanel_open(dev_t dev, int flag, int mode);\nextern int gpanel_close(dev_t dev, int flag, int mode);\nextern int gpanel_read(dev_t dev, struct uio *uio, int flag);\nextern int gpanel_write(dev_t dev, struct uio *uio, int flag);\nextern int gpanel_ioctl(dev_t dev, u_int cmd, caddr_t addr, int flag);\n\nextern int gpanel_read_byte(void);\nextern void gpanel_write_byte(int value);\nextern void gpanel_cs_active(void);\nextern void gpanel_cs_idle(void);\nextern void gpanel_rs_command(void);\nextern void gpanel_rs_data(void);\nextern void gpanel_wr_strobe(void);\nextern void gpanel_read_dir(void);\nextern void gpanel_write_dir(void);\nextern int gpanel_send_command(int value);\nextern int gpanel_send_data(int value);\n\n/*\n * Descriptor for access to the hardware-level driver.\n */\nstruct gpanel_hw {\n    const char *name;\n    void (*resize)(struct gpanel_hw *hw, int width, int height);\n    void (*set_pixel)(int x, int y, int color);\n    void (*fill_rectangle)(int x0, int y0, int x1, int y1, int color);\n    void (*draw_image)(int x, int y, int width, int height,\n        const unsigned short *data);\n    void (*draw_glyph)(const struct gpanel_font_t *font,\n        int color, int background, int x, int y, int width,\n        const unsigned short *bits);\n};\nextern int gpanel_width;\nextern int gpanel_height;\nextern void st7781_init_display(struct gpanel_hw *hw);\nextern void nt35702_init_display(struct gpanel_hw *hw);\nextern void ili9341_init_display(struct gpanel_hw *hw);\nextern void ili9481_init_display(struct gpanel_hw *hw);\nextern void s6d04h0_init_display(struct gpanel_hw *hw);\n\n#endif /* KERNEL */\n\n#endif /* _GPANEL_H */\n"
  },
  {
    "path": "sys/sys/gpio.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *  @(#)gpio.h  1.4 (2.11BSD GTE) 1997/3/28\n */\n\n/*\n * Ioctl definitions\n */\n#ifndef _GPIO_H\n#define _GPIO_H\n\n#include <sys/ioctl.h>\n#include <sys/uio.h>\n\n/* control general-purpose i/o pins */\n#define GPIO_PORT(n)    ((n) & 0xff)                    /* port number */\n#define GPIO_PORTA      GPIO_PORT(0)\n#define GPIO_PORTB      GPIO_PORT(1)\n#define GPIO_PORTC      GPIO_PORT(2)\n#define GPIO_PORTD      GPIO_PORT(3)\n#define GPIO_PORTE      GPIO_PORT(4)\n#define GPIO_PORTF      GPIO_PORT(5)\n#define GPIO_PORTG      GPIO_PORT(6)\n#define GPIO_COMMAND    0x1fff0000                      /* command mask */\n#define GPIO_CONFIN     (IOC_VOID | 1 << 16 | 'g'<<8)   /* configure as input */\n#define GPIO_CONFOUT    (IOC_VOID | 1 << 17 | 'g'<<8)   /* configure as output */\n#define GPIO_CONFOD     (IOC_VOID | 1 << 18 | 'g'<<8)   /* configure as open drain */\n#define GPIO_DECONF     (IOC_VOID | 1 << 19 | 'g'<<8)   /* deconfigure */\n#define GPIO_STORE      (IOC_VOID | 1 << 20 | 'g'<<8)   /* store all outputs */\n#define GPIO_SET        (IOC_VOID | 1 << 21 | 'g'<<8)   /* set to 1 by mask */\n#define GPIO_CLEAR      (IOC_VOID | 1 << 22 | 'g'<<8)   /* set to 0 by mask */\n#define GPIO_INVERT     (IOC_VOID | 1 << 23 | 'g'<<8)   /* invert by mask */\n#define GPIO_POLL       (IOC_VOID | 1 << 24 | 'g'<<8)   /* poll */\n#define GPIO_LOL        (IOC_IN   | 1 << 25 | 'g'<<8)   /* display lol picture */\n\n#ifdef KERNEL\n\n#include \"conf.h\"\n\nint gpioopen (dev_t dev, int flag, int mode);\nint gpioclose (dev_t dev, int flag, int mode);\nint gpioread (dev_t dev, struct uio *uio, int flag);\nint gpiowrite (dev_t dev, struct uio *uio, int flag);\nint gpioioctl (dev_t dev, u_int cmd, caddr_t addr, int flag);\n#endif\n\n#endif\n"
  },
  {
    "path": "sys/sys/inode.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * The I node is the focus of all file activity in UNIX.\n * There is a unique inode allocated for each active file,\n * each current directory, each mounted-on file, text file, and the root.\n * An inode is 'named' by its dev/inumber pair. (iget/iget.c)\n * Data in icommon1 and icommon2 is read in from permanent inode on volume.\n */\n\n/*\n * 28 of the di_addr address bytes are used; 7 addresses of 4\n * bytes each: 4 direct (4Kb directly accessible) and 3 indirect.\n */\n#define NDADDR      4                   /* direct addresses in inode */\n#define NIADDR      3                   /* indirect addresses in inode */\n#define NADDR       (NDADDR + NIADDR)   /* total addresses in inode */\n\nstruct icommon1 {\n    u_short ic_mode;        /* mode and type of file */\n    u_short ic_nlink;       /* number of links to file */\n    uid_t   ic_uid;         /* owner's user id */\n    gid_t   ic_gid;         /* owner's group id */\n    off_t   ic_size;        /* number of bytes in file */\n};\n\nstruct icommon2 {\n    time_t  ic_atime;       /* time last accessed */\n    time_t  ic_mtime;       /* time last modified */\n    time_t  ic_ctime;       /* time created */\n};\n\nstruct inode {\n    struct inode    *i_chain[2];    /* must be first */\n    u_int           i_flag;\n    u_int           i_count;        /* reference count */\n    dev_t           i_dev;          /* device where inode resides */\n    ino_t           i_number;       /* i number, 1-to-1 with device address */\n    u_int           i_id;           /* unique identifier */\n    struct fs       *i_fs;          /* file sys associated with this inode */\n    union {\n        struct {\n            u_short I_shlockc;      /* count of shared locks */\n            u_short I_exlockc;      /* count of exclusive locks */\n        } i_l;\n        struct proc *I_rsel;        /* pipe read select */\n    } i_un0;\n    union {\n        struct proc *I_wsel;        /* pipe write select */\n    } i_un1;\n    union {\n        daddr_t I_addr[NADDR];      /* normal file/directory */\n        struct {\n            daddr_t I_db[NDADDR];   /* normal file/directory */\n            daddr_t I_ib[NIADDR];\n        } i_f;\n        struct {\n            /*\n             * the dummy field is here so that the de/compression\n             * part of the iget/iput routines works for special\n             * files.\n             */\n            u_int   I_dummy;\n            dev_t   I_rdev;         /* dev type */\n        } i_d;\n    } i_un2;\n    union {\n        daddr_t     if_lastr;       /* last read (read-ahead) */\n        struct  {\n            struct inode  *if_freef; /* free list forward */\n            struct inode **if_freeb; /* free list back */\n        } i_fr;\n    } i_un3;\n    struct icommon1 i_ic1;\n    u_int           i_flags;        /* user changeable flags */\n    struct icommon2 i_ic2;\n};\n\n/*\n * Inode structure as it appears on\n * a disk block.\n */\nstruct dinode {\n    struct  icommon1 di_icom1;\n    daddr_t di_addr[NADDR];         /* 7 block addresses 4 bytes each */\n    u_int   di_reserved[1];         /* pad of 4 to make total size 64 */\n    u_int   di_flags;\n    struct  icommon2 di_icom2;\n};\n\n#define i_mode      i_ic1.ic_mode\n#define i_nlink     i_ic1.ic_nlink\n#define i_uid       i_ic1.ic_uid\n#define i_gid       i_ic1.ic_gid\n#define i_size      i_ic1.ic_size\n#define i_shlockc   i_un0.i_l.I_shlockc\n#define i_exlockc   i_un0.i_l.I_exlockc\n#define i_rsel      i_un0.I_rsel\n#define i_wsel      i_un1.I_wsel\n#define i_db        i_un2.i_f.I_db\n#define i_ib        i_un2.i_f.I_ib\n#define i_atime     i_ic2.ic_atime\n#define i_mtime     i_ic2.ic_mtime\n#define i_ctime     i_ic2.ic_ctime\n#define i_rdev      i_un2.i_d.I_rdev\n#define i_addr      i_un2.I_addr\n#define i_dummy     i_un2.i_d.I_dummy\n#define i_lastr     i_un3.if_lastr\n#define i_forw      i_chain[0]\n#define i_back      i_chain[1]\n#define i_freef     i_un3.i_fr.if_freef\n#define i_freeb     i_un3.i_fr.if_freeb\n\n#define di_ic1      di_icom1\n#define di_ic2      di_icom2\n#define di_mode     di_ic1.ic_mode\n#define di_nlink    di_ic1.ic_nlink\n#define di_uid      di_ic1.ic_uid\n#define di_gid      di_ic1.ic_gid\n#define di_size     di_ic1.ic_size\n#define di_atime    di_ic2.ic_atime\n#define di_mtime    di_ic2.ic_mtime\n#define di_ctime    di_ic2.ic_ctime\n\n#ifdef KERNEL\nstruct stat;\n\n/*\n * Invalidate an inode. Used by the namei cache to detect stale\n * information. In order to save space and also reduce somewhat the\n * overhead - the i_id field is made into a u_short.  If a pdp-11 can\n * invalidate 100 inodes per second, the cache will have to be invalidated\n * in about 11 minutes.  Ha!\n * Assumes the cacheinvalall routine will map the namei cache.\n */\nvoid cinvalall (void);\n\n#define cacheinval(ip) \\\n    (ip)->i_id = ++nextinodeid; \\\n    if (nextinodeid == 0) \\\n        cinvalall();\n\nu_int nextinodeid;              /* unique id generator */\n\nextern struct inode inode[];    /* the inode table itself */\nstruct inode *rootdir;          /* pointer to inode of root directory */\n\n/*\n * Initialize hash links for inodes and build inode free list.\n */\nvoid ihinit (void);\n\n/*\n * Get an inode pointer of a file descriptor.\n */\nstruct inode *getinode (int fdes);\n\n/*\n * Allocate an inode in the file system.\n */\nstruct inode *ialloc (struct inode *pip);\n\n/*\n * Look up an inode by device, inumber.\n */\nstruct inode *iget (dev_t dev, struct fs *fs, ino_t ino);\n\n/*\n * Dereference an inode structure. On the last reference,\n * write the inode out and deallocate the file.\n */\nvoid iput (struct inode *ip);\n\n/*\n * Make a new file.\n */\nstruct nameidata;\nstruct inode *maknode (int mode, struct nameidata *ndp);\n\n/*\n * Open inode: initialize and validate special files.\n */\nint openi (struct inode *ip, int mode);\n\n/*\n * Close inode: call the device driver for special (IBLK, ICHR) files.\n*/\nint closei (struct inode *ip, int flag);\n\n/*\n * Convert a pathname into a pointer to a locked inode.\n */\nstruct inode *namei (struct nameidata *ndp);\n\nenum uio_rw;\nint rdwri (enum uio_rw rw, struct inode *ip, caddr_t base, int len,\n    off_t offset, int ioflg, int *aresid);\n\nstruct uio;\nint rwip (struct inode *ip, struct uio *uio, int ioflag);\n\n/*\n * Check mode permission on inode pointer.\n */\nint access (struct inode *ip, int mode);\n\n/*\n * Change the mode on a file.\n */\nint chmod1 (struct inode *ip, int mode);\n\n/*\n * Change an owner of a file.\n */\nint chown1 (struct inode *ip, int uid, int gid);\n\n/*\n * Lock/unlock an inode.\n */\nvoid ilock (struct inode *ip);\nvoid iunlock (struct inode *ip);\n\n/*\n * Get inode statistics.\n */\nint ino_stat (struct inode *ip, struct stat *sb);\n\n/*\n * Truncate the inode ip to at most length size.\n */\nvoid itrunc (struct inode *oip, u_long length, int ioflags);\n\n/*\n * Update the inode with the current time.\n */\nstruct timeval;\nvoid iupdat (struct inode *ip, struct timeval *ta, struct timeval *tm,\n    int waitfor);\n\nvoid irele (struct inode *ip);\n\n/*\n * Free an inode.\n */\nvoid ifree (struct inode *ip, ino_t ino);\n\n/*\n * Free a block or fragment.\n */\nvoid free (struct inode *ip, daddr_t bno);\n\n/*\n * Flush all the blocks associated with an inode.\n */\nvoid syncip (struct inode *ip);\n\n/*\n * Remove any inodes in the inode cache belonging to dev.\n */\nint iflush (dev_t dev);\n\n/*\n * Convert a pointer to an inode into a reference to an inode.\n */\nvoid igrab (struct inode *ip);\n\n/*\n * Check if source directory is in the path of the target directory.\n */\nint checkpath (struct inode *source, struct inode *target);\n\n/*\n * Check if a directory is empty or not.\n */\nint dirempty (struct inode *ip, ino_t parentino);\n\n/*\n * Rewrite an existing directory entry to point at the inode supplied.\n */\nvoid dirrewrite (struct inode *dp, struct inode *ip, struct nameidata *ndp);\n\n/*\n * Check that device is mounted somewhere.\n */\nint ufs_mountedon (dev_t dev);\n\n/*\n * Set the attributes on a file.  This was placed here because ufs_syscalls\n * is too large already (it will probably be split into two files eventually).\n */\nstruct vattr;\nint ufs_setattr (struct inode *ip, struct vattr *vap);\n\n/*\n * Cache flush, called when filesys is umounted.\n */\nvoid nchinval (dev_t dev);\n\n#endif /* KERNEL */\n\n/* i_flag */\n#define ILOCKED     0x1         /* inode is locked */\n#define IUPD        0x2         /* file has been modified */\n#define IACC        0x4         /* inode access time to be updated */\n#define IMOUNT      0x8         /* inode is mounted on */\n#define IWANT       0x10        /* some process waiting on lock */\n#define ITEXT       0x20        /* inode is pure text prototype */\n#define ICHG        0x40        /* inode has been changed */\n#define ISHLOCK     0x80        /* file has shared lock */\n#define IEXLOCK     0x100       /* file has exclusive lock */\n#define ILWAIT      0x200       /* someone waiting on file lock */\n#define IMOD        0x400       /* inode has been modified */\n#define IRENAME     0x800       /* inode is being renamed */\n#define IPIPE       0x1000      /* inode is a pipe */\n#define IRCOLL      0x2000      /* read select collision on pipe */\n#define IWCOLL      0x4000      /* write select collision on pipe */\n#define IXMOD       0x8000      /* inode is text, but impure (XXX) */\n\n/* i_mode */\n#define IFMT        0170000     /* type of file */\n#define IFCHR       0020000     /* character special */\n#define IFDIR       0040000     /* directory */\n#define IFBLK       0060000     /* block special */\n#define IFREG       0100000     /* regular */\n#define IFLNK       0120000     /* symbolic link */\n#define IFSOCK      0140000     /* socket */\n#define ISUID       04000       /* set user id on execution */\n#define ISGID       02000       /* set group id on execution */\n#define ISVTX       01000       /* save swapped text even after use */\n#define IREAD       0400        /* read, write, execute permissions */\n#define IWRITE      0200\n#define IEXEC       0100\n\n#ifdef KERNEL\n/*\n * Flags for va_cflags.\n */\n#define VA_UTIMES_NULL  0x01    /* utimes argument was NULL */\n\n/*\n * Flags for ioflag.\n */\n#define IO_UNIT         0x01    /* do I/O as atomic unit */\n#define IO_APPEND       0x02    /* append write to end */\n#define IO_SYNC         0x04    /* do I/O synchronously */\n/*#define IO_NODELOCKED 0x08       not implemented */\n#define IO_NDELAY       0x10    /* FNDELAY flag set in file table */\n\n\n/*\n * This is a bit of a misnomer.  2.11BSD does not have 'vnodes' but it was\n * easier/simpler to keep the name 'vattr' than changing the name to something\n * like 'iattr'.\n *\n * This structure is a _subset_ of 4.4BSD's vnode attribute structure.  ONLY\n * those attributes which can be *changed by the user* are present.  Since we\n * do not have vnodes why initialize (and carry around) un-used members.\n */\nstruct vattr {\n    mode_t  va_mode;\n    uid_t   va_uid;\n    gid_t   va_gid;\n    off_t   va_size;\n    time_t  va_atime;\n    time_t  va_mtime;\n    u_int   va_flags;\n    u_int   va_vaflags;\n};\n\n/*\n * Token indicating no attribute value yet assigned.\n */\n#define VNOVAL  (-1)\n\n/*\n * Initialize a inode attribute structure.\n */\n#define VATTR_NULL(vp) { \\\n    (vp)->va_mode = VNOVAL; \\\n    (vp)->va_uid = VNOVAL; \\\n    (vp)->va_gid = VNOVAL; \\\n    (vp)->va_size = VNOVAL; \\\n    (vp)->va_atime = VNOVAL; \\\n    (vp)->va_mtime = VNOVAL; \\\n    (vp)->va_flags = VNOVAL; \\\n    (vp)->va_vaflags = VNOVAL; }\n\n/*\n * N.B:  If the above structure changes be sure to modify the function\n * vattr_null in pdp/mch_xxx.s!\n */\n#endif\n\n#define ILOCK(ip) { \\\n    while ((ip)->i_flag & ILOCKED) { \\\n        (ip)->i_flag |= IWANT; \\\n        sleep((caddr_t)(ip), PINOD); \\\n    } \\\n    (ip)->i_flag |= ILOCKED; \\\n}\n\n#define IUNLOCK(ip) { \\\n    (ip)->i_flag &= ~ILOCKED; \\\n    if ((ip)->i_flag&IWANT) { \\\n        (ip)->i_flag &= ~IWANT; \\\n        wakeup((caddr_t)(ip)); \\\n    } \\\n}\n\n#define IUPDAT(ip, t1, t2, waitfor) { \\\n    if (ip->i_flag&(IUPD|IACC|ICHG|IMOD)) \\\n        iupdat(ip, t1, t2, waitfor); \\\n}\n\n#define ITIMES(ip, t1, t2) { \\\n    if ((ip)->i_flag&(IUPD|IACC|ICHG)) { \\\n        (ip)->i_flag |= IMOD; \\\n        if ((ip)->i_flag&IACC) \\\n            (ip)->i_atime = (t1)->tv_sec; \\\n        if ((ip)->i_flag&IUPD) \\\n            (ip)->i_mtime = (t2)->tv_sec; \\\n        if ((ip)->i_flag&ICHG) \\\n            (ip)->i_ctime = time.tv_sec; \\\n        (ip)->i_flag &= ~(IACC|IUPD|ICHG); \\\n    } \\\n}\n"
  },
  {
    "path": "sys/sys/ioctl.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *  @(#)ioctl.h 1.4 (2.11BSD GTE) 1997/3/28\n */\n\n/*\n * Ioctl definitions\n */\n#ifndef _IOCTL_\n#define _IOCTL_\n#ifdef KERNEL\n#include \"ttychars.h\"\n#include \"ttydev.h\"\n#else\n#include <sys/ttychars.h>\n#include <sys/ttydev.h>\n\nint     ioctl (int d, int request, ...);\n\n#endif\n\nstruct tchars {\n    char    t_intrc;        /* interrupt */\n    char    t_quitc;        /* quit */\n    char    t_startc;       /* start output */\n    char    t_stopc;        /* stop output */\n    char    t_eofc;         /* end-of-file */\n    char    t_brkc;         /* input delimiter (like nl) */\n};\nstruct ltchars {\n    char    t_suspc;        /* stop process signal */\n    char    t_dsuspc;       /* delayed stop process signal */\n    char    t_rprntc;       /* reprint line */\n    char    t_flushc;       /* flush output (toggles) */\n    char    t_werasc;       /* word erase */\n    char    t_lnextc;       /* literal next character */\n};\n\n/*\n * Structure for TIOCGETP and TIOCSETP ioctls.\n */\n\n#ifndef _SGTTYB_\n#define _SGTTYB_\nstruct sgttyb {\n    char    sg_ispeed;      /* input speed */\n    char    sg_ospeed;      /* output speed */\n    char    sg_erase;       /* erase character */\n    char    sg_kill;        /* kill character */\n    short   sg_flags;       /* mode flags */\n};\n#endif\n\n/*\n * Window/terminal size structure.\n * This information is stored by the kernel\n * in order to provide a consistent interface,\n * but is not used by the kernel.\n *\n * Type must be \"unsigned short\" so that types.h not required.\n */\nstruct winsize {\n    unsigned short  ws_row;     /* rows, in characters */\n    unsigned short  ws_col;     /* columns, in characters */\n    unsigned short  ws_xpixel;  /* horizontal size, pixels */\n    unsigned short  ws_ypixel;  /* vertical size, pixels */\n};\n\n/*\n * Pun for SUN.\n */\nstruct ttysize {\n    unsigned short  ts_lines;\n    unsigned short  ts_cols;\n    unsigned short  ts_xxx;\n    unsigned short  ts_yyy;\n};\n#define TIOCGSIZE   TIOCGWINSZ\n#define TIOCSSIZE   TIOCSWINSZ\n\n#ifndef _IO\n/*\n * Ioctl's have the command encoded in the lower word,\n * and the size of any in or out parameters in the upper\n * word.  The high 2 bits of the upper word are used\n * to encode the in/out status of the parameter; for now\n * we restrict parameters to at most 256 bytes (disklabels are 216 bytes).\n */\n#define IOCPARM_MASK    0xff            /* parameters must be < 256 bytes */\n#define IOC_VOID        0x20000000      /* no parameters */\n#define IOC_OUT         0x40000000      /* copy out parameters */\n#define IOC_IN          0x80000000      /* copy in parameters */\n#define IOC_INOUT       (IOC_IN|IOC_OUT)\n\n#define _IO(x,y)        (IOC_VOID |                               ((x)<<8)|y)\n#define _IOR(x,y,t)     (IOC_OUT  |((sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|y)\n#define _IOW(x,y,t)     (IOC_IN   |((sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|y)\n/* this should be _IORW, but stdio got there first */\n#define _IOWR(x,y,t)    (IOC_INOUT|((sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|y)\n#define _ION(x,y,n)     (IOC_INOUT|      (((n)&IOCPARM_MASK)<<16)|((x)<<8)|y)\n#endif\n\n/*\n * tty ioctl commands\n */\n#define TIOCGETD        _IOR('t', 0, int)   /* get line discipline */\n#define TIOCSETD        _IOW('t', 1, int)   /* set line discipline */\n#define TIOCHPCL        _IO ('t', 2)        /* hang up on last close */\n#define TIOCMODG        _IOR('t', 3, int)   /* get modem control state */\n#define TIOCMODS        _IOW('t', 4, int)   /* set modem control state */\n#define     TIOCM_LE    0001                /* line enable */\n#define     TIOCM_DTR   0002                /* data terminal ready */\n#define     TIOCM_RTS   0004                /* request to send */\n#define     TIOCM_ST    0010                /* secondary transmit */\n#define     TIOCM_SR    0020                /* secondary receive */\n#define     TIOCM_CTS   0040                /* clear to send */\n#define     TIOCM_CAR   0100                /* carrier detect */\n#define     TIOCM_CD    TIOCM_CAR\n#define     TIOCM_RNG   0200                /* ring */\n#define     TIOCM_RI    TIOCM_RNG\n#define     TIOCM_DSR   0400                /* data set ready */\n#define TIOCGETP        _IOR('t', 8,struct sgttyb)/* get parameters -- gtty */\n#define TIOCSETP        _IOW('t', 9,struct sgttyb)/* set parameters -- stty */\n#define TIOCSETN        _IOW('t', 10,struct sgttyb)/* as above, but no flushtty */\n#define TIOCEXCL        _IO ('t', 13)       /* set exclusive use of tty */\n#define TIOCNXCL        _IO ('t', 14)       /* reset exclusive use of tty */\n#define TIOCFLUSH       _IOW('t', 16, int)  /* flush buffers */\n#define TIOCSETC        _IOW('t', 17,struct tchars)/* set special characters */\n#define TIOCGETC        _IOR('t', 18,struct tchars)/* get special characters */\n#define     TANDEM      0x00000001          /* send stopc on out q full */\n#define     CBREAK      0x00000002          /* half-cooked mode */\n                            /* 0x4             (old LCASE) */\n#define     ECHO        0x00000008          /* echo input */\n#define     CRMOD       0x00000010          /* map \\r to \\r\\n on output */\n#define     RAW         0x00000020          /* no i/o processing */\n#define     ODDP        0x00000040          /* get/send odd parity */\n#define     EVENP       0x00000080          /* get/send even parity */\n#define     ANYP        0x000000c0          /* get any parity/send none */\n                          /* 0x100             (old NLDELAY) */\n                          /* 0x200 */\n#define     XTABS       0x00000400          /* expand tabs on output */\n                         /* 0x0800             (part of old XTABS) */\n                         /* 0x1000             (old CRDELAY) */\n                         /* 0x2000 */\n                         /* 0x4000             (old VTDELAY) */\n                         /* 0x8000             (old BSDELAY) */\n#define     CRTBS       0x00010000          /* do backspacing for crt */\n#define     PRTERA      0x00020000          /* \\ ... / erase */\n#define     CRTERA      0x00040000          /* \" \\b \" to wipe out char */\n                     /* 0x00080000             (old TILDE) */\n#define     MDMBUF      0x00100000          /* start/stop output on carrier intr */\n#define     LITOUT      0x00200000          /* literal output */\n#define     TOSTOP      0x00400000          /* SIGSTOP on background output */\n#define     FLUSHO      0x00800000          /* flush output to terminal */\n#define     NOHANG      0x01000000          /* no SIGHUP on carrier drop */\n#define     RTSCTS      0x02000000          /* use RTS/CTS flow control */\n#define     CRTKIL      0x04000000          /* kill line with \" \\b \" */\n#define     PASS8       0x08000000\n#define     CTLECH      0x10000000          /* echo control chars as ^X */\n#define     PENDIN      0x20000000          /* tp->t_rawq needs reread */\n#define     DECCTQ      0x40000000          /* only ^Q starts after ^S */\n#define     NOFLSH      0x80000000          /* no output flush on signal */\n/* locals, from 127 down */\n#define TIOCLBIS        _IOW('t', 127, int) /* bis local mode bits */\n#define TIOCLBIC        _IOW('t', 126, int) /* bic local mode bits */\n#define TIOCLSET        _IOW('t', 125, int) /* set entire local mode word */\n#define TIOCLGET        _IOR('t', 124, int) /* get local modes */\n#define     LCRTBS      ((int)(CRTBS>>16))\n#define     LPRTERA     ((int)(PRTERA>>16))\n#define     LCRTERA     ((int)(CRTERA>>16))\n#define     LMDMBUF     ((int)(MDMBUF>>16))\n#define     LLITOUT     ((int)(LITOUT>>16))\n#define     LTOSTOP     ((int)(TOSTOP>>16))\n#define     LFLUSHO     ((int)(FLUSHO>>16))\n#define     LNOHANG     ((int)(NOHANG>>16))\n#define     LRTSCTS     ((int)(RTSCTS>>16))\n#define     LCRTKIL     ((int)(CRTKIL>>16))\n#define     LPASS8      ((int)(PASS8>>16))\n#define     LCTLECH     ((int)(CTLECH>>16))\n#define     LPENDIN     ((int)(PENDIN>>16))\n#define     LDECCTQ     ((int)(DECCTQ>>16))\n#define     LNOFLSH     ((int)(NOFLSH>>16))\n#define TIOCSBRK        _IO ('t', 123)      /* set break bit */\n#define TIOCCBRK        _IO ('t', 122)      /* clear break bit */\n#define TIOCSDTR        _IO ('t', 121)      /* set data terminal ready */\n#define TIOCCDTR        _IO ('t', 120)      /* clear data terminal ready */\n#define TIOCGPGRP       _IOR('t', 119, int) /* get pgrp of tty */\n#define TIOCSPGRP       _IOW('t', 118, int) /* set pgrp of tty */\n#define TIOCSLTC        _IOW('t', 117,struct ltchars)/* set local special chars */\n#define TIOCGLTC        _IOR('t', 116,struct ltchars)/* get local special chars */\n#define TIOCOUTQ        _IOR('t', 115, int) /* output queue size */\n#define TIOCSTI         _IOW('t', 114, char)/* simulate terminal input */\n#define TIOCNOTTY       _IO ('t', 113)      /* void tty association */\n#define TIOCPKT         _IOW('t', 112, int) /* pty: set/clear packet mode */\n#define     TIOCPKT_DATA        0x00        /* data packet */\n#define     TIOCPKT_FLUSHREAD   0x01        /* flush packet */\n#define     TIOCPKT_FLUSHWRITE  0x02        /* flush packet */\n#define     TIOCPKT_STOP        0x04        /* stop output */\n#define     TIOCPKT_START       0x08        /* start output */\n#define     TIOCPKT_NOSTOP      0x10        /* no more ^S, ^Q */\n#define     TIOCPKT_DOSTOP      0x20        /* now do ^S ^Q */\n#define TIOCSTOP        _IO ('t', 111)      /* stop output, like ^S */\n#define TIOCSTART       _IO ('t', 110)      /* start output, like ^Q */\n#define TIOCMSET        _IOW('t', 109, int) /* set all modem bits */\n#define TIOCMBIS        _IOW('t', 108, int) /* bis modem bits */\n#define TIOCMBIC        _IOW('t', 107, int) /* bic modem bits */\n#define TIOCMGET        _IOR('t', 106, int) /* get all modem bits */\n#define TIOCREMOTE      _IOW('t', 105, int) /* remote input editing */\n#define TIOCGWINSZ      _IOR('t', 104, struct winsize)  /* get window size */\n#define TIOCSWINSZ      _IOW('t', 103, struct winsize)  /* set window size */\n#define TIOCUCNTL       _IOW('t', 102, int) /* pty: set/clr usr cntl mode */\n#define UIOCCMD(n)      _IO ('u', n)        /* usr cntl op \"n\" */\n\n#define NTTYDISC        0                   /* new tty discipline */\n\n#define FIOCLEX         _IO('f', 1)         /* set exclusive use on fd */\n#define FIONCLEX        _IO('f', 2)         /* remove exclusive use */\n/* another local */\n/* should use off_t for FIONREAD but that would require types.h */\n#define FIONREAD        _IOR('f', 97, long) /* get # bytes to read */\n#define FIONBIO         _IOW('f', 96, int)  /* set/clear non-blocking i/o */\n#define FIOASYNC        _IOW('f', 95, int)  /* set/clear async i/o */\n#define FIOSETOWN       _IOW('f', 94, int)  /* set owner */\n#define FIOGETOWN       _IOR('f', 93, int)  /* get owner */\n\n/* socket i/o controls */\n#define SIOCSHIWAT      _IOW('s', 0, int)   /* set high watermark */\n#define SIOCGHIWAT      _IOR('s', 1, int)   /* get high watermark */\n#define SIOCSLOWAT      _IOW('s', 2, int)   /* set low watermark */\n#define SIOCGLOWAT      _IOR('s', 3, int)   /* get low watermark */\n#define SIOCATMARK      _IOR('s', 7, int)   /* at oob mark? */\n#define SIOCSPGRP       _IOW('s', 8, int)   /* set process group */\n#define SIOCGPGRP       _IOR('s', 9, int)   /* get process group */\n\n#define SIOCADDRT       _IOW('r', 10, struct rtentry)   /* add route */\n#define SIOCDELRT       _IOW('r', 11, struct rtentry)   /* delete route */\n\n#define SIOCSIFADDR     _IOW ('i',12, struct ifreq)     /* set ifnet address */\n#define SIOCGIFADDR     _IOWR('i',13, struct ifreq)     /* get ifnet address */\n#define SIOCSIFDSTADDR  _IOW ('i',14, struct ifreq)     /* set p-p address */\n#define SIOCGIFDSTADDR  _IOWR('i',15, struct ifreq)     /* get p-p address */\n#define SIOCSIFFLAGS    _IOW ('i',16, struct ifreq)     /* set ifnet flags */\n#define SIOCGIFFLAGS    _IOWR('i',17, struct ifreq)     /* get ifnet flags */\n#define SIOCGIFBRDADDR  _IOWR('i',18, struct ifreq)     /* get broadcast addr */\n#define SIOCSIFBRDADDR  _IOW ('i',19, struct ifreq)     /* set broadcast addr */\n#define SIOCGIFCONF     _IOWR('i',20, struct ifconf)    /* get ifnet list */\n#define SIOCGIFNETMASK  _IOWR('i',21, struct ifreq)     /* get net addr mask */\n#define SIOCSIFNETMASK  _IOW ('i',22, struct ifreq)     /* set net addr mask */\n#define SIOCGIFMETRIC   _IOWR('i',23, struct ifreq)     /* get IF metric */\n#define SIOCSIFMETRIC   _IOW ('i',24, struct ifreq)     /* set IF metric */\n\n#define SIOCSARP        _IOW ('i',30, struct arpreq)    /* set arp entry */\n#define SIOCGARP        _IOWR('i',31, struct arpreq)    /* get arp entry */\n#define SIOCDARP        _IOW ('i',32, struct arpreq)    /* delete arp entry */\n\n#endif\n"
  },
  {
    "path": "sys/sys/kernel.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * Global variables for the kernel\n */\n\n/* 1.1 */\nlong    hostid;\nchar    hostname[MAXHOSTNAMELEN];\nint hostnamelen;\n\n/* 1.2 */\n#include <sys/time.h>\n\nstruct  timeval boottime;\nstruct  timeval time;\nstruct  timezone tz;        /* XXX */\nint     adjdelta;\nint     hz;\nint     usechz;             /* # microseconds per hz */\nint     lbolt;              /* awoken once a second */\n\nshort   avenrun[3];\n"
  },
  {
    "path": "sys/sys/map.h",
    "content": "/*\n * Resource Allocation Maps.\n *\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * Associated routines manage allocation of an address space using\n * an array of segment descriptors.\n *\n * Malloc and mfree allocate and free the resource described\n * by the resource map.  If the resource map becomes too fragmented\n * to be described in the available space, then some of the resource\n * is discarded.  This may lead to critical shortages,\n * but is better than not checking (as the previous versions of\n * these routines did) or giving up and calling panic().\n *\n * N.B.: The address 0 in the resource address space is not available\n * as it is used internally by the resource map routines.\n */\nstruct map {\n    struct mapent   *m_map;     /* start of the map */\n    struct mapent   *m_limit;   /* address of last slot in map */\n    char            *m_name;    /* name of resource */\n/* we use m_name when the map overflows, in warning messages */\n};\n\nstruct mapent {\n    size_t  m_size;             /* size of this segment of the map */\n    size_t  m_addr;             /* resource-space addr of start of segment */\n};\n\n#ifdef KERNEL\nextern struct map swapmap[];    /* space for swap allocation */\n\n/*\n * Allocate units from the given map.\n */\nsize_t malloc (struct map *mp, size_t nbytes);\n\n/*\n * Free the previously allocated units at addr into the specified map.\n */\nvoid mfree (struct map *mp, size_t nbytes, size_t addr);\n\n/*\n * Allocate resources for the three segments of a process.\n */\nsize_t malloc3 (struct map *mp, size_t d_size, size_t s_size, size_t u_size, size_t a[3]);\n\n#endif\n"
  },
  {
    "path": "sys/sys/mount.h",
    "content": "/*\n * Copyright (c) 1982, 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * file system statistics\n */\n#include <sys/fs.h>\n\n#define MNAMELEN 90 /* length of buffer for returned name */\n\nstruct statfs {\n    short   f_type;         /* type of filesystem (see below) */\n    u_short f_flags;        /* copy of mount flags */\n    short   f_bsize;        /* fundamental file system block size */\n    short   f_iosize;       /* optimal transfer block size */\n    daddr_t f_blocks;       /* total data blocks in file system */\n    daddr_t f_bfree;        /* free blocks in fs */\n    daddr_t f_bavail;       /* free blocks avail to non-superuser */\n    ino_t   f_files;        /* total file nodes in file system */\n    ino_t   f_ffree;        /* free file nodes in fs */\n    long    f_fsid[2];      /* file system id */\n    long    f_spare[5];     /* spare for later */\n    char    f_mntonname[MNAMELEN];  /* directory on which mounted */\n    char    f_mntfromname[MNAMELEN];/* mounted filesystem */\n};\n\n/*\n * File system types.  Since only UFS is supported the others are not\n * specified at this time.\n */\n#define MOUNT_NONE      0\n#define MOUNT_UFS       1   /* Fast Filesystem */\n#define MOUNT_MAXTYPE   1\n\n#define INITMOUNTNAMES { \\\n    \"none\",     /* 0 MOUNT_NONE */ \\\n    \"ufs\",      /* 1 MOUNT_UFS */ \\\n    0, \\\n}\n\n/*\n * Mount structure.\n * One allocated on every mount.\n * Used to find the super block.\n */\nstruct  mount\n{\n    dev_t   m_dev;                  /* device mounted */\n    struct  fs m_filsys;            /* superblock data */\n#define m_flags m_filsys.fs_flags\n    struct  inode *m_inodp;         /* pointer to mounted on inode */\n    struct  inode *m_qinod;         /* QUOTA: pointer to quota file */\n    char    m_mntfrom [MNAMELEN];   /* /dev/xxxx mounted from */\n    char    m_mnton [MNAMELEN];     /* directory mounted on - this is the\n                                     * full(er) version of fs_fsmnt. */\n};\n\n/*\n * Mount flags.\n */\n#define MNT_RDONLY      0x0001      /* read only filesystem */\n#define MNT_SYNCHRONOUS 0x0002      /* file system written synchronously */\n#define MNT_NOEXEC      0x0004      /* can't exec from filesystem */\n#define MNT_NOSUID      0x0008      /* don't honor setuid bits on fs */\n#define MNT_NODEV       0x0010      /* don't interpret special files */\n#define MNT_QUOTA       0x0020      /* quotas are enabled on filesystem */\n#define MNT_ASYNC       0x0040      /* file system written asynchronously */\n#define MNT_NOATIME     0x0080      /* don't update access times */\n\n/*\n * Mask of flags that are visible to statfs().\n*/\n#define MNT_VISFLAGMASK 0x0fff\n\n/*\n * filesystem control flags.  The high 4 bits are used for this.  Since NFS\n * support will never be a problem we can avoid making the flags into a 'long.\n*/\n#define MNT_UPDATE      0x1000      /* not a real mount, just an update */\n\n/*\n * Flags for various system call interfaces.\n *\n * These aren't used for anything in the system and are present only\n * for source code compatibility reasons.\n*/\n#define MNT_WAIT        1\n#define MNT_NOWAIT      2\n\n#ifdef KERNEL\n\nstruct  mount mount[NMOUNT];\n\n#else\n\nint     getfsstat (struct statfs *buf, int bufsize, unsigned flags);\nint     getmntinfo (struct statfs **mntbufp, int flags);\nint     statfs (const char *path, struct statfs *buf);\nint     mount (const char *special, const char *name, int flags);\nint     umount (const char *special);\n\n#endif\n"
  },
  {
    "path": "sys/sys/msgbuf.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#define MSG_MAGIC   0x063061\n#define MSG_BSIZE   2048\n\nstruct  msgbuf {\n    long    msg_magic;\n    int     msg_bufx;\n    int     msg_bufr;\n    char    msg_bufc [MSG_BSIZE];\n};\n\n#define logMSG      0       /* /dev/klog */\n\n#ifdef KERNEL\n/*\n * Check that log is open by a user program.\n */\nint logisopen (int unit);\n#endif\n"
  },
  {
    "path": "sys/sys/mtio.h",
    "content": "/*\n * Copyright (c) 1982, 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *  @(#)mtio.h  7.1.2 (2.11BSD) 1998/3/7\n */\n\n/*\n * Structures and definitions for mag tape io control commands\n */\n\n/* structure for MTIOCTOP - mag tape op command */\nstruct  mtop    {\n    short   mt_op;      /* operations defined below */\n    daddr_t mt_count;   /* how many of them */\n};\n\n/* operations */\n#define MTWEOF      0   /* write an end-of-file record */\n#define MTFSF       1   /* forward space file */\n#define MTBSF       2   /* backward space file */\n#define MTFSR       3   /* forward space record */\n#define MTBSR       4   /* backward space record */\n#define MTREW       5   /* rewind */\n#define MTOFFL      6   /* rewind and put the drive offline */\n#define MTNOP       7   /* no operation, sets status only */\n#define MTCACHE     8   /* enable controller cache */\n#define MTNOCACHE   9 /* disable controller cache */\n#define MTFLUSH     10  /* flush cache */\n\n/* structure for MTIOCGET - mag tape get status command */\n\nstruct  mtget   {\n    short   mt_type;    /* type of magtape device */\n/* the following two registers are grossly device dependent */\n    short   mt_dsreg;   /* ``drive status'' register */\n    short   mt_erreg;   /* ``error'' register */\n/* end device-dependent registers */\n    short   mt_resid;   /* residual count */\n/* the following two are not yet implemented */\n    daddr_t mt_fileno;  /* file number of current position */\n    daddr_t mt_blkno;   /* block number of current position */\n/* end not yet implemented */\n};\n\n/*\n * Constants for mt_type byte.  These are the same\n * for other controllers compatible with the types listed.\n */\n#define MT_ISTS     0x01        /* TS-11 */\n#define MT_ISHT     0x02        /* TM03 Massbus: TE16, TU45, TU77 */\n#define MT_ISTM     0x03        /* TM11/TE10 Unibus */\n#define MT_ISMT     0x04        /* TM78/TU78 Massbus */\n#define MT_ISUT     0x05        /* SI TU-45 emulation on Unibus */\n#define MT_ISCPC    0x06        /* SUN */\n#define MT_ISAR     0x07        /* SUN */\n#define MT_ISTMSCP  0x08        /* DEC TMSCP protocol (TU81, TK50) */\n\n/*\n * At present only the TMSCP driver reports this information in the\n * high byte of the 'drive status' word.  Other drives will (hopefully)\n * be updated in the future.\n*/\n#define MTF_BOM     0x01        /* At beginning of media */\n#define MTF_EOM     0x02        /* At the end of media */\n#define MTF_OFFLINE 0x04        /* Drive is offline */\n#define MTF_WRTLCK  0x08        /* Drive is write protected */\n#define MTF_WRITTEN 0x10        /* Tape has been written */\n\n/* mag tape io control commands */\n#define MTIOCTOP    _IOW('m', 1, struct mtop)   /* do a mag tape op */\n#define MTIOCGET    _IOR('m', 2, struct mtget)  /* get tape status */\n#define MTIOCIEOT   _IO ('m', 3)                /* ignore EOT error */\n#define MTIOCEEOT   _IO ('m', 4)                /* enable EOT error */\n"
  },
  {
    "path": "sys/sys/namei.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#ifndef _NAMEI_\n#define _NAMEI_\n\n#ifdef KERNEL\n#include \"uio.h\"\n#else\n#include <sys/uio.h>\n#endif\n\n/*\n * Encapsulation of namei parameters.\n * One of these is located in the u. area to\n * minimize space allocated on the kernel stack.\n */\nstruct nameidata {\n    caddr_t ni_dirp;        /* pathname pointer */\n    short   ni_nameiop;     /* see below */\n    short   ni_error;       /* error return if any */\n    off_t   ni_endoff;      /* end of useful stuff in directory */\n    struct  inode *ni_pdir; /* inode of parent directory of dirp */\n    struct  inode *ni_ip;   /* inode of dirp */\n    off_t   ni_offset;      /* offset in directory */\n    u_short ni_count;       /* offset of open slot (off_t?) */\n    struct  direct ni_dent; /* current directory entry */\n};\n\n/*\n * namei operations and modifiers\n */\n#define LOOKUP      0       /* perform name lookup only */\n#define CREATE      1       /* setup for file creation */\n#define DELETE      2       /* setup for file deletion */\n#define LOCKPARENT  0x10    /* see the top of namei */\n#define NOCACHE     0x20    /* name must not be left in cache */\n#define FOLLOW      0x40    /* follow symbolic links */\n#define NOFOLLOW    0x0     /* don't follow symbolic links (pseudo) */\n\n#define NDINIT(ndp,op,flags,namep) {\\\n    (ndp)->ni_nameiop = op | flags; \\\n    (ndp)->ni_dirp = namep; }\n\n/*\n * This structure describes the elements in the cache of recent\n * names looked up by namei.\n */\nstruct  namecache {\n    struct  namecache *nc_forw; /* hash chain, MUST BE FIRST */\n    struct  namecache *nc_back; /* hash chain, MUST BE FIRST */\n    struct  namecache *nc_nxt;  /* LRU chain */\n    struct  namecache **nc_prev; /* LRU chain */\n    struct  inode *nc_ip;       /* inode the name refers to */\n    ino_t   nc_ino;             /* ino of parent of name */\n    dev_t   nc_dev;             /* dev of parent of name */\n    dev_t   nc_idev;            /* dev of the name ref'd */\n    u_short nc_id;              /* referenced inode's id */\n    char    nc_nlen;            /* length of name */\n#define NCHNAMLEN   15          /* maximum name segment length we bother with */\n    char    nc_name[NCHNAMLEN]; /* segment name */\n};\n\n#ifdef KERNEL\nextern struct   namecache namecache [];\nstruct  nchstats nchstats;      /* cache effectiveness statistics */\n\n/*\n * Name cache initialization.\n */\nvoid nchinit (void);\n\n/*\n * Common code for vnode open operations.\n */\nint vn_open (struct nameidata *ndp, int fmode, int cmode);\n\n/*\n * Write a directory entry after a call to namei.\n */\nint direnter (struct inode *ip, struct nameidata *ndp);\n\n/*\n * Remove a directory entry after a call to namei.\n */\nint dirremove (struct nameidata *ndp);\n\n#endif /* KERNEL */\n\n/*\n * Stats on usefulness of namei caches.\n */\nstruct  nchstats {\n    long    ncs_goodhits;       /* hits that we can reall use */\n    long    ncs_badhits;        /* hits we must drop */\n    long    ncs_falsehits;      /* hits with id mismatch */\n    long    ncs_miss;           /* misses */\n    long    ncs_long;           /* long names that ignore cache */\n    long    ncs_pass2;          /* names found with passes == 2 */\n    long    ncs_2passes;        /* number of times we attempt it */\n};\n#endif\n"
  },
  {
    "path": "sys/sys/param.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#define BSD\t\t211\t/* 2.11 * 100, as cpp doesn't do floats */\n\n#define DiscoBSD\t202602\t/* DiscoBSD version (year & month). */\n#define DiscoBSD_2_6\t1\t/* DiscoBSD 2.6 */\n\n#if !defined(offsetof) && defined(KERNEL)\n#define offsetof(type, member)  ((size_t)(&((type *)0)->member))\n#endif\n\n/*\n * Machine type dependent parameters.\n */\n#include <machine/machparam.h>\n\n/*\n * Machine-independent constants\n */\n#include <sys/syslimits.h>\n\n#ifndef NMOUNT\n#define NMOUNT      2       /* number of mountable file systems */\n#endif\n\n#define MAXUPRC     20      /* max processes per user */\n#define NOFILE      30      /* max open files per process */\n#define NCARGS      5120    /* # characters in exec arglist */\n#define NGROUPS     16      /* max number groups */\n\n#define NOGROUP     65535   /* marker for empty group set member */\n\n/*\n * Priorities\n */\n#define PSWP        0\n#define PINOD       10\n#define PRIBIO      20\n#define PRIUBA      24\n#define PZERO       25\n#define PPIPE       26\n#define PSOCK       26\n#define PWAIT       30\n#define PLOCK       35\n#define PPAUSE      40\n#define PUSER       50\n\n#define NZERO       0\n\n#define PRIMASK     0xff\n#define PCATCH      0x100\n\n/*\n * Signals\n */\n#include <sys/signal.h>\n\n#define NBPW        sizeof(int) /* number of bytes in an integer */\n\n#ifndef NULL\n#define NULL        0\n#endif\n#define CMASK       026     /* default mask for file creation */\n#define NODEV       (dev_t)(-1)\n\n/* CBLOCK is the size of a clist block, must be power of 2 */\n#define CBLOCK      32\n#define CBSIZE      (CBLOCK - sizeof(struct cblock *))  /* data chars/clist */\n#define CROUND      (CBLOCK - 1)                        /* clist rounding */\n\n#include <sys/types.h>\n\n/*\n * File system parameters and macros.\n *\n * The file system is made out of blocks of most MAXBSIZE units.\n */\n#define MAXBSIZE    1024\n\n/*\n * MAXPATHLEN defines the longest permissible path length\n * after expanding symbolic links. It is used to allocate\n * a temporary buffer from the buffer pool in which to do the\n * name expansion, hence should be a power of two, and must\n * be less than or equal to MAXBSIZE.\n * MAXSYMLINKS defines the maximum number of symbolic links\n * that may be expanded in a path name. It should be set high\n * enough to allow all legitimate uses, but halt infinite loops\n * reasonably quickly.\n */\n#define MAXPATHLEN  PATH_MAX\n#define MAXSYMLINKS 8\n\n/*\n * Macros for fast min/max.\n */\n#define MIN(a,b)    (((a)<(b))?(a):(b))\n#ifndef MAX\n#define MAX(a,b)    (((a)>(b))?(a):(b))\n#endif\n\n/*\n * Macros for counting and rounding.\n */\n#ifndef howmany\n#   define howmany(x,y) (((x)+((y)-1))/(y))\n#endif\n#define roundup(x,y)    ((((x)+((y)-1))/(y))*(y))\n\n/*\n * Maximum size of hostname recognized and stored in the kernel.\n */\n#define MAXHOSTNAMELEN  64\n\n#if defined(KERNEL) && defined(INET)\n#   include <machine/net_mac.h>\n#endif\n\n/*\n * MAXMEM is the maximum core per process is allowed.  First number is Kb.\n*/\n#ifndef MAXMEM\n#define MAXMEM      (96*1024)\n#endif\n\n/*\n * Max length of a user login name.\n */\n#define MAXLOGNAME  16\n"
  },
  {
    "path": "sys/sys/picga.h",
    "content": "#ifndef _PICGA_H\n#define _PICGA_H\n\n#define SPI_IDLE        0x00\n\n/* System control */\n#define SPI_CLS         0x01\n#define SPI_CLUT        0x02\n#define SPI_ENCOPPER    0x03\n#define SPI_DISCOPPER   0x04\n#define SPI_COPPERFILL  0x05\n#define SPI_SCROLL      0x06\n#define SPI_COPY        0x07\n\n/* Basic drawing */\n#define SPI_PLOT        0x11\n#define SPI_DRAW        0x12\n#define SPI_COLOR       0x13\n#define SPI_RECTANGLE   0x14\n#define SPI_CIRCLE      0x15\n\n/* Text commands */\n#define SPI_LOCATE      0x80\n#define SPI_FONT        0x81\n#define SPI_PRINT       0x82\n#define SPI_PRINTAT     0x83\n#define SPI_PUTCH       0x84\n#define SPI_PUTCHAR     0x85\n#define SPI_FGCOLOR     0x86\n#define SPI_BGCOLOR     0x87\n\n#define FONT_SINCLAIR   0x00\n#define FONT_TOPAZ      0x01\n\n#define UP              0\n#define DOWN            1\n#define LEFT            2\n#define RIGHT           3\n\nstruct coord2 {\n\tu_short x;\n\tu_short y;\n} __attribute__((packed));\n\nstruct coord4 {\n\tu_short x1;\n\tu_short y1;\n\tu_short x2;\n\tu_short y2;\n} __attribute__((packed));\n\nstruct coord6 {\n\tu_short x1;\n\tu_short y1;\n\tu_short x2;\n\tu_short y2;\n\tu_short x3;\n\tu_short y3;\n} __attribute__((packed));\n\nstruct intval {\n\tu_short value;\n} __attribute__((packed));\n\nstruct rectangle {\n\tu_short x1;\n\tu_short y1;\n\tu_short x2;\n\tu_short y2;\n\tu_int fill:1;\n\tu_char dither;\n} __attribute__((packed));\n\nstruct circle {\n\tu_short x;\n\tu_short y;\n\tu_short radius;\n\tu_int fill:1;\n} __attribute__((packed));\n\nstruct charval {\n\tu_char value;\n} __attribute__((packed));\n\n#ifdef KERNEL\n#include \"conf.h\"\n\nextern void picga_command(u_char cmd, u_char len, void *data);\nextern int picga_open(dev_t dev, int flag, int mode);\nextern int picga_close(dev_t dev, int flag, int mode);\nextern int picga_read(dev_t dev, struct uio *uio, int flag);\nextern int picga_write(dev_t dev, struct uio *uio, int flag);\nextern int picga_ioctl(dev_t dev, u_int cmd, caddr_t addr, int flag);\n#endif\n\n#define PICGA_CLS       _IO('g', 1)\n\n#endif\n"
  },
  {
    "path": "sys/sys/proc.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#ifndef _SYS_PROC_H_\n#define _SYS_PROC_H_\n\n/*\n * One structure allocated per active\n * process. It contains all data needed\n * about the process while the\n * process may be swapped out.\n * Other per process data (user.h)\n * is swapped with the process.\n */\nstruct  proc {\n    struct  proc *p_nxt;            /* linked list of allocated proc slots */\n    struct  proc **p_prev;          /* also zombies, and free proc's */\n    struct  proc *p_pptr;           /* pointer to process structure of parent */\n    short   p_flag;\n    short   p_uid;                  /* user id, used to direct tty signals */\n    short   p_pid;                  /* unique process id */\n    short   p_ppid;                 /* process id of parent */\n    long    p_sig;                  /* signals pending to this process */\n    int     p_stat;\n\n    /*\n     * Union to overwrite information no longer needed by ZOMBIED\n     * process with exit information for the parent process.  The\n     * two structures have been carefully set up to use the same\n     * amount of memory.  Must be very careful that any values in\n     * p_alive are not used for zombies (zombproc).\n     */\n    union {\n        struct {\n            char    P_pri;          /* priority, negative is high */\n            char    P_cpu;          /* cpu usage for scheduling */\n            char    P_time;         /* resident time for scheduling */\n            char    P_nice;         /* nice for cpu usage */\n            char    P_slptime;      /* secs sleeping */\n            char    P_ptracesig;    /* used between parent & traced child */\n            struct proc *P_hash;    /* hashed based on p_pid */\n            long    P_sigmask;      /* current signal mask */\n            long    P_sigignore;    /* signals being ignored */\n            long    P_sigcatch;     /* signals being caught by user */\n            short   P_pgrp;         /* name of process group leader */\n            struct  proc *P_link;   /* linked list of running processes */\n            size_t  P_addr;         /* address of u. area */\n            size_t  P_daddr;        /* address of data area */\n            size_t  P_saddr;        /* address of stack area */\n            size_t  P_dsize;        /* size of data area (clicks) */\n            size_t  P_ssize;        /* size of stack segment (clicks) */\n            caddr_t P_wchan;        /* event process is awaiting */\n            struct  k_itimerval P_realtimer;\n        } p_alive;\n        struct {\n            int P_xstat;            /* exit status for wait */\n            struct k_rusage P_ru;   /* exit information */\n        } p_dead;\n    } p_un;\n};\n#define p_pri           p_un.p_alive.P_pri\n#define p_cpu           p_un.p_alive.P_cpu\n#define p_time          p_un.p_alive.P_time\n#define p_nice          p_un.p_alive.P_nice\n#define p_slptime       p_un.p_alive.P_slptime\n#define p_hash          p_un.p_alive.P_hash\n#define p_ptracesig     p_un.p_alive.P_ptracesig\n#define p_sigmask       p_un.p_alive.P_sigmask\n#define p_sigignore     p_un.p_alive.P_sigignore\n#define p_sigcatch      p_un.p_alive.P_sigcatch\n#define p_pgrp          p_un.p_alive.P_pgrp\n#define p_link          p_un.p_alive.P_link\n#define p_addr          p_un.p_alive.P_addr\n#define p_daddr         p_un.p_alive.P_daddr\n#define p_saddr         p_un.p_alive.P_saddr\n#define p_dsize         p_un.p_alive.P_dsize\n#define p_ssize         p_un.p_alive.P_ssize\n#define p_wchan         p_un.p_alive.P_wchan\n#define p_realtimer     p_un.p_alive.P_realtimer\n#define p_clktim        p_realtimer.it_value\n\n#define p_xstat         p_un.p_dead.P_xstat\n#define p_ru            p_un.p_dead.P_ru\n\n#define PIDHSZ          16\n#define PIDHASH(pid)    ((pid) & (PIDHSZ - 1))\n\n/* arguments to swapout: */\n#define X_OLDSIZE       (-1)    /* the old size is the same as current */\n#define X_DONTFREE      0       /* save core image (for parent in newproc) */\n#define X_FREECORE      1       /* free core space after swap */\n\n#ifdef KERNEL\nstruct  proc *pidhash [PIDHSZ];\nextern struct   proc proc[];    /* the proc table itself */\nstruct  proc *freeproc, *zombproc, *allproc, *qs;\n                                /* lists of procs in various states */\nextern int nproc;\n\n/*\n * Init the process queues.\n */\nvoid pqinit (void);\n\n/*\n * Find a process by pid.\n */\nstruct proc *pfind (int pid);\n\n/*\n * Set user priority.\n */\nint setpri (struct proc *pp);\n\n/*\n * Send the specified signal to the specified process.\n */\nvoid psignal (struct proc *p, int sig);\n\n/*\n * Send the specified signal to a process group.\n */\nvoid gsignal (int pgrp, int sig);\n\n/*\n * Take the action for the specified signal.\n */\nvoid postsig (int sig);\n\n/*\n * If the current process has received a signal, return the signal number.\n */\nint issignal (struct proc *p);\n\n/*\n * Initialize signal state for process 0;\n * set to ignore signals that are ignored by default.\n */\nvoid siginit (struct proc *p);\n\n/*\n * Remove a process from its wait queue\n */\nvoid unsleep (struct proc *p);\n\nvoid selwakeup (struct proc *p, long coll);\n\n/*\n * Set the process running;\n * arrange for it to be swapped in if necessary.\n */\nvoid setrun (struct proc *p);\n\n/*\n * Reschedule the CPU.\n */\nvoid swtch (void);\n\n/*\n * Recompute process priorities, once a second.\n */\nvoid schedcpu (caddr_t arg);\n\n/*\n * The main loop of the scheduling process. No return.\n */\nvoid sched (void);\n\n/*\n * Create a new process -- the internal version of system call fork.\n */\nint newproc (int isvfork);\n\n/*\n * Notify parent that vfork child is finished with parent's data.\n */\nvoid endvfork (void);\n\n/*\n * Put the process into the run queue.\n */\nvoid setrq (struct proc *p);\n\n/*\n * Remove runnable job from run queue.\n */\nvoid remrq (struct proc *p);\n\n/*\n * Exit the process.\n */\nvoid exit (int rv);\n\n/*\n * Swap I/O.\n */\nvoid swap (size_t blkno, size_t coreaddr, int count, int rdflg);\n\n/*\n * Kill a process when ran out of swap space.\n */\nvoid swkill (struct proc *p, char *name);\n\n/*\n * Give up the processor till a wakeup occurs on chan, at which time the\n * process enters the scheduling queue at priority pri.\n */\nvoid sleep (caddr_t chan, int pri);\n\n/*\n * Give up the processor till a wakeup occurs on ident or a timeout expires.\n * Then the process enters the scheduling queue at given priority.\n */\nint tsleep (caddr_t ident, int priority, u_int timo);\n\n/*\n * Arrange that given function is called in t/hz seconds.\n */\nvoid timeout (void (*fun) (caddr_t), caddr_t arg, int t);\n\n/*\n * Remove a function timeout call from the callout structure.\n */\nvoid untimeout (void (*fun) (caddr_t), caddr_t arg);\n\n/*\n * Handler for hardware clock interrupt.\n */\nvoid hardclock (caddr_t pc, int ps);\n\n/*\n * Swap out a process.\n */\nvoid swapout (struct proc *p, int freecore, u_int odata, u_int ostack);\n\n/*\n * Swap a process in.\n */\nvoid swapin (struct proc *p);\n\n/*\n * Is p an inferior of the current process?\n */\nint inferior (struct proc *p);\n\n/*\n * Test if the current user is the super user.\n */\nint suser (void);\n\n/*\n * Load from user area (probably swapped out): real uid,\n * controlling terminal device, and controlling terminal pointer.\n */\nstruct tty;\nvoid fill_from_u (struct proc *p, uid_t *rup, struct tty **ttp, dev_t *tdp);\n\n/*\n * Grow the stack to include the SP.\n */\nint grow (unsigned sp);\n\n/*\n * Kill current process with the specified signal in an uncatchable manner.\n */\nvoid fatalsig (int signum);\n\n/*\n * Parent controlled tracing.\n */\nint procxmt (void);\n\nvoid execsigs(register struct proc *p);\nvoid userret(int, time_t);\n\n#endif /* KERNEL */\n\n/* stat codes */\n#define SSLEEP      1       /* awaiting an event */\n#define SWAIT       2       /* (abandoned state) */\n#define SRUN        3       /* running */\n#define SIDL        4       /* intermediate state in process creation */\n#define SZOMB       5       /* intermediate state in process termination */\n#define SSTOP       6       /* process being traced */\n\n/* flag codes */\n#define SLOAD       0x0001  /* in core */\n#define SSYS        0x0002  /* swapper or pager process */\n#define SLOCK       0x0004  /* process being swapped out */\n#define SSWAP       0x0008  /* save area flag */\n#define P_TRACED    0x0010  /* process is being traced */\n#define P_WAITED    0x0020  /* another tracing flag */\n                 /* 0x0040     unused */\n#define P_SINTR     0x0080  /* sleeping interruptibly */\n#define SVFORK      0x0100  /* process resulted from vfork() */\n#define SVFPRNT     0x0200  /* parent in vfork, waiting for child */\n#define SVFDONE     0x0400  /* parent has released child in vfork */\n                 /* 0x0800     unused */\n#define P_TIMEOUT   0x1000  /* tsleep timeout expired */\n#define P_NOCLDSTOP 0x2000  /* no SIGCHLD signal to parent */\n#define P_SELECT    0x4000  /* selecting; wakeup/waiting danger */\n                 /* 0x8000     unused */\n\n#define S_DATA      0       /* specified segment */\n#define S_STACK     1\n\n#endif  /* !_SYS_PROC_H_ */\n"
  },
  {
    "path": "sys/sys/ptrace.h",
    "content": "/*\n * Copyright (c) 1980, 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#ifndef _PTRACE_\n#define _PTRACE_\n\n#define PT_TRACE_ME     0   /* child declares it's being traced */\n#define PT_READ_I       1   /* read word in child's I space */\n#define PT_READ_D       2   /* read word in child's D space */\n#define PT_READ_U       3   /* read word in child's user structure */\n#define PT_WRITE_I      4   /* write word in child's I space */\n#define PT_WRITE_D      5   /* write word in child's D space */\n#define PT_WRITE_U      6   /* write word in child's user structure */\n#define PT_CONTINUE     7   /* continue the child */\n#define PT_KILL         8   /* kill the child process */\n#define PT_STEP         9   /* single step the child */\n\n/*\n * Tracing variables.\n * Used to pass trace command from\n * parent to child being traced.\n * This data base cannot be\n * shared and is locked\n * per user.\n */\nstruct ipc {\n    int ip_lock;\n    int ip_req;\n    int *ip_addr;\n    int ip_data;\n};\n\n#ifdef KERNEL\n\nstruct ipc ipc;\n\n#else\n\nint ptrace (int request, pid_t pid, void *addr, int data);\n\n#endif\n\n#endif\n"
  },
  {
    "path": "sys/sys/pty.h",
    "content": "#ifndef _PTY_H\n#define _PTY_H\n\n#define PF_RCOLL    0x01\n#define PF_WCOLL    0x02\n#define PF_PKT      0x08        /* packet mode */\n#define PF_STOPPED  0x10        /* user told stopped */\n#define PF_REMOTE   0x20        /* remote and flow controlled input */\n#define PF_NOSTOP   0x40\n#define PF_UCNTL    0x80        /* user control mode */\n\n#ifdef KERNEL\n\n#include \"uio.h\"\n#include \"tty.h\"\n#include \"conf.h\"\n\n#ifndef PTY_NUNITS\n#define PTY_NUNITS 4            /* 4 units by default */\n#endif\n\nextern struct tty pt_tty[];\nextern int npty;\n\nextern int ptsopen(dev_t dev, int flag, int mode);\nextern int ptsclose(dev_t dev, int flag, int mode);\nextern int ptsread(dev_t dev, register struct uio *uio, int flag);\nextern int ptswrite(dev_t dev, register struct uio *uio, int flag);\nextern void ptsstart(struct tty *tp);\nextern void ptcwakeup(struct tty *tp, int flag);\nextern int ptcopen(dev_t dev, int flag, int mode);\nextern int ptcclose(dev_t dev, int flag, int mode);\nextern int ptcread(dev_t dev, register struct uio *uio, int flag);\nextern void ptsstop(register struct tty *tp, int flush);\nextern int ptcselect(dev_t dev, int rw);\nextern int ptcwrite(dev_t dev, register struct uio *uio, int flag);\nextern int ptyioctl(dev_t dev, u_int cmd, caddr_t data, int flag);\n\n#endif\n\n#endif\n"
  },
  {
    "path": "sys/sys/pwm.h",
    "content": "#ifndef _PWM_H\n#define _PWM_H\n\n#include <sys/ioctl.h>\n\nstruct pwm_state {\n    int     mode;\n    int     pwm_duty;\n};\n\n#define PWM_MAX_DEV     5\n\n#define PWM_MODE_PWM    0x0001\n\n#define PWM_SET_MODE    _IOW('i',1,int)\n#define PWM_DUTY        _IOW('i',2,int)\n\n#ifdef KERNEL\n#include \"conf.h\"\n\nextern int pwm_open (dev_t dev, int flag, int mode);\nextern int pwm_close (dev_t dev, int flag, int mode);\nextern int pwm_read (dev_t dev, struct uio *uio, int flag);\nextern int pwm_write (dev_t dev, struct uio *uio, int flag);\nextern int pwm_ioctl (dev_t dev, u_int cmd, caddr_t addr, int flag);\n#endif\n\n#define OC2CON          PIC32_R (0x03200)\n#define OC3CON          PIC32_R (0x03400)\n#define OC5CON          PIC32_R (0x03800)\n\n#define OC2RS           PIC32_R (0x03220)\n#define OC3RS           PIC32_R (0x03420)\n#define OC5RS           PIC32_R (0x03820)\n\n#endif\n"
  },
  {
    "path": "sys/sys/reboot.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *  @(#)reboot.h    1.2 (2.11BSD GTE) 1996/5/9\n */\n\n/*\n * Arguments to reboot system call.\n * These are passed to boot program in r4,\n * and on to init.\n */\n#define RB_AUTOBOOT     0       /* flags for system auto-booting itself */\n\n#define RB_ASKNAME      0x001   /* ask for file name to reboot from */\n#define RB_SINGLE       0x002   /* reboot to single user only */\n#define RB_NOSYNC       0x004   /* dont sync before reboot */\n#define RB_HALT         0x008   /* don't reboot, just halt */\n#define RB_INITNAME     0x010   /* name given for /etc/init */\n#define RB_DFLTROOT     0x020   /* use compiled-in rootdev */\n#define RB_DUMP         0x040   /* take a dump before rebooting */\n#define RB_NOFSCK       0x080   /* don't perform fsck's on reboot */\n#define RB_POWRFAIL     0x100   /* reboot caused by power failure */\n#define RB_RDONLY       0x200   /* mount root fs read-only */\n#define RB_AUTODEBUG    0x400   /* init runs autoconfig with \"-d\" (debug) */\n#define RB_POWEROFF     0x800   /* signal PSU to switch off power */\n#define RB_BOOTLOADER   0x1000  /* reboot into the bootloader */\n\n#define RB_PANIC        0       /* reboot due to panic */\n#define RB_BOOT         1       /* reboot due to boot() */\n"
  },
  {
    "path": "sys/sys/resource.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *  @(#)resource.h  1.3 (2.11BSD GTE) 1997/2/14\n */\n\n#ifndef _SYS_RESOURCE_H_\n#define _SYS_RESOURCE_H_\n\n#include <sys/time.h>\n\n/*\n * Process priority specifications to get/setpriority.\n */\n#define PRIO_MIN        (-20)\n#define PRIO_MAX        20\n\n#define PRIO_PROCESS    0\n#define PRIO_PGRP       1\n#define PRIO_USER       2\n\n/*\n * Resource utilization information.\n */\n\n#define RUSAGE_SELF     0\n#define RUSAGE_CHILDREN (-1)\n\nstruct  rusage {\n    struct timeval  ru_utime;       /* user time used */\n    struct timeval  ru_stime;       /* system time used */\n    long            ru_maxrss;\n#define ru_first    ru_ixrss\n    long            ru_ixrss;       /* integral shared memory size */\n    long            ru_idrss;       /* integral unshared data \" */\n    long            ru_isrss;       /* integral unshared stack \" */\n    long            ru_minflt;      /* page reclaims */\n    long            ru_majflt;      /* page faults */\n    long            ru_nswap;       /* swaps */\n    long            ru_inblock;     /* block input operations */\n    long            ru_oublock;     /* block output operations */\n    long            ru_msgsnd;      /* messages sent */\n    long            ru_msgrcv;      /* messages received */\n    long            ru_nsignals;    /* signals received */\n    long            ru_nvcsw;       /* voluntary context switches */\n    long            ru_nivcsw;      /* involuntary \" */\n#define ru_last     ru_nivcsw\n};\n\nstruct  k_rusage {                  /* KERNEL RUSAGE STRUCTURE */\n#define k_ru_first  ru_utime\n    long            ru_utime;       /* user time used ('hz' ticks) */\n    long            ru_stime;       /* system time used ('hz' ticks) */\n    long            ru_nswap;       /* swaps */\n    long            ru_inblock;     /* block input operations */\n    long            ru_oublock;     /* block output operations */\n    long            ru_msgsnd;      /* messages sent */\n    long            ru_msgrcv;      /* messages received */\n    long            ru_nsignals;    /* signals received */\n    long            ru_nvcsw;       /* voluntary context switches */\n    long            ru_nivcsw;      /* involuntary \" */\n#define k_ru_last   ru_nivcsw\n};\n\n/*\n * Resource limits\n */\n#define RLIMIT_CPU      0       /* cpu time in milliseconds */\n#define RLIMIT_FSIZE    1       /* maximum file size */\n#define RLIMIT_DATA     2       /* data size */\n#define RLIMIT_STACK    3       /* stack size */\n#define RLIMIT_CORE     4       /* core file size */\n#define RLIMIT_RSS      5       /* resident set size */\n\n#define RLIM_NLIMITS    6       /* number of resource limits */\n\n#define RLIM_INFINITY   0x7fffffff\n\nstruct rlimit {\n    long    rlim_cur;           /* current (soft) limit */\n    long    rlim_max;           /* maximum value for rlim_cur */\n};\n\n/* Load average structure. */\nstruct loadavg {\n    short   ldavg[3];\n    int     fscale;\n};\n\n#ifdef KERNEL\n/*\n * Convert an internal kernel rusage structure into a `real' rusage structure.\n */\nvoid rucvt (struct rusage *rup, struct k_rusage *krup);\n\n/*\n * Add resource usage data.\n */\nvoid ruadd (struct k_rusage *ru, struct k_rusage *ru2);\n\n#else\n\nint getpriority (int which, int who);\nint getrlimit (int resource, struct rlimit *rlp);\nint getrusage (int who, struct rusage *usage);\nint setpriority (int which, int who, int prio);\nint setrlimit (int resource, struct rlimit *rlp);\n\n#endif\n\n#endif  /* !_SYS_RESOURCE_H_ */\n"
  },
  {
    "path": "sys/sys/select.h",
    "content": "/*-\n * Copyright (c) 1992, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n *\t@(#)select.h\t8.2.1 (2.11BSD) 2000/2/28\n */\n\n#ifndef\t_SYS_SELECT_H_\n#define\t_SYS_SELECT_H_\n\n#include <sys/types.h>\n\n/*\n * Select uses bit masks of file descriptors in longs.\n * These macros manipulate such bit fields (the filesystem macros use chars).\n * FD_SETSIZE may be defined by the user, but the default here\n * should be >= NOFILE (param.h).\n */\n#ifndef\tFD_SETSIZE\n#define\tFD_SETSIZE\t32\n#endif\n\ntypedef long\tfd_mask;\n#define\tNFDBITS\t(sizeof(fd_mask) * NBBY)\t/* bits per mask */\n\ntypedef struct fd_set {\n\tfd_mask\tfds_bits[1];\n} fd_set;\n\n#define\tFD_SET(n, p)\t((p)->fds_bits[(n)/NFDBITS] |= (1L << ((n) % NFDBITS)))\n#define\tFD_CLR(n, p)\t((p)->fds_bits[(n)/NFDBITS] &= ~(1L << ((n) % NFDBITS)))\n#define\tFD_ISSET(n, p)\t((p)->fds_bits[(n)/NFDBITS] & (1L << ((n) % NFDBITS)))\n#ifdef\tKERNEL\n#define\tFD_ZERO(p)\tbzero((char *)(p), sizeof(*(p)))\n#else\n#define\tFD_ZERO(p)\tmemset((char *)(p), 0, sizeof(*(p)))\n#endif\n\n#ifndef\tKERNEL\n\n/* According to POSIX.1-2001 */\nstruct timeval;\nint\tselect(int, fd_set *, fd_set *, fd_set *, struct timeval *);\n\n#endif\t/* !KERNEL */\n\n#endif\t/* !_SYS_SELECT_H_ */\n"
  },
  {
    "path": "sys/sys/signal.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#ifndef NSIG\n#include <sys/types.h>\n\n#include <machine/signal.h>     /* sigcontext */\n\n#define NSIG        32\n\n#define SIGHUP      1       /* hangup */\n#define SIGINT      2       /* interrupt */\n#define SIGQUIT     3       /* quit */\n#define SIGILL      4       /* illegal instruction (not reset when caught) */\n#define SIGTRAP     5       /* trace trap (not reset when caught) */\n#define SIGIOT      6       /* IOT instruction */\n#define SIGABRT     SIGIOT  /* compatibility */\n#define SIGEMT      7       /* EMT instruction */\n#define SIGFPE      8       /* floating point exception */\n#define SIGKILL     9       /* kill (cannot be caught or ignored) */\n#define SIGBUS      10      /* bus error */\n#define SIGSEGV     11      /* segmentation violation */\n#define SIGSYS      12      /* bad argument to system call */\n#define SIGPIPE     13      /* write on a pipe with no one to read it */\n#define SIGALRM     14      /* alarm clock */\n#define SIGTERM     15      /* software termination signal from kill */\n#define SIGURG      16      /* urgent condition on IO channel */\n#define SIGSTOP     17      /* sendable stop signal not from tty */\n#define SIGTSTP     18      /* stop signal from tty */\n#define SIGCONT     19      /* continue a stopped process */\n#define SIGCHLD     20      /* to parent on child stop or exit */\n#define SIGCLD      SIGCHLD /* compatibility */\n#define SIGTTIN     21      /* to readers pgrp upon background tty read */\n#define SIGTTOU     22      /* like TTIN for output if (tp->t_local&LTOSTOP) */\n#define SIGIO       23      /* input/output possible signal */\n#define SIGXCPU     24      /* exceeded CPU time limit */\n#define SIGXFSZ     25      /* exceeded file size limit */\n#define SIGVTALRM   26      /* virtual time alarm */\n#define SIGPROF     27      /* profiling time alarm */\n#define SIGWINCH    28      /* window size changes */\n#define SIGUSR1     30      /* user defined signal 1 */\n#define SIGUSR2     31      /* user defined signal 2 */\n\ntypedef void (*sig_t) (int); /* type of signal function */\n\n#define SIG_ERR     (sig_t) -1\n#define SIG_DFL     (sig_t) 0\n#define SIG_IGN     (sig_t) 1\n\ntypedef unsigned long sigset_t;\n\n/*\n * Signal vector \"template\" used in sigaction call.\n */\nstruct  sigaction {\n    sig_t   sa_handler;         /* signal handler */\n    sigset_t sa_mask;           /* signal mask to apply */\n    int     sa_flags;           /* see signal options below */\n};\n\n#define SA_ONSTACK      0x0001  /* take signal on signal stack */\n#define SA_RESTART      0x0002  /* restart system on signal return */\n#define SA_DISABLE      0x0004  /* disable taking signals on alternate stack */\n#define SA_NOCLDSTOP    0x0008  /* do not generate SIGCHLD on child stop */\n\n/*\n * Flags for sigprocmask:\n */\n#define SIG_BLOCK       1       /* block specified signal set */\n#define SIG_UNBLOCK     2       /* unblock specified signal set */\n#define SIG_SETMASK     3       /* set specified signal set */\n\n/*\n * Structure used in sigaltstack call.\n */\nstruct  sigaltstack {\n    char    *ss_base;           /* signal stack base */\n    int     ss_size;            /* signal stack length */\n    int     ss_flags;           /* SA_DISABLE and/or SA_ONSTACK */\n};\n#define MINSIGSTKSZ     128                 /* minimum allowable stack */\n#define SIGSTKSZ        (MINSIGSTKSZ + 384) /* recommended stack size */\n\n/*\n * 4.3 compatibility:\n * Signal vector \"template\" used in sigvec call.\n */\nstruct  sigvec {\n    sig_t   sv_handler;         /* signal handler */\n    long    sv_mask;            /* signal mask to apply */\n    int     sv_flags;           /* see signal options below */\n};\n#define SV_ONSTACK      SA_ONSTACK  /* take signal on signal stack */\n#define SV_INTERRUPT    SA_RESTART  /* same bit, opposite sense */\n#define sv_onstack      sv_flags    /* isn't compatibility wonderful! */\n\n/*\n * 4.3 compatibility:\n * Structure used in sigstack call.\n */\nstruct  sigstack {\n    char    *ss_sp;             /* signal stack pointer */\n    int     ss_onstack;         /* current status */\n};\n\n/*\n * Macro for converting signal number to a mask suitable for\n * sigblock().\n */\n#define sigmask(m)              (1L << ((m)-1))\n#define sigaddset(set, signo)   (*(set) |= 1L << ((signo) - 1), 0)\n#define sigdelset(set, signo)   (*(set) &= ~(1L << ((signo) - 1)), 0)\n#define sigemptyset(set)        (*(set) = (sigset_t)0, (int)0)\n#define sigfillset(set)         (*(set) = ~(sigset_t)0, (int)0)\n#define sigismember(set, signo) ((*(set) & (1L << ((signo) - 1))) != 0)\n\n#ifdef KERNEL\n\n/* Table of signal properties. */\nextern const char sigprop [NSIG + 1];\n\n/*\n * Send an interrupt to process.\n */\nvoid sendsig (sig_t p, int sig, long mask);\n\n#else /* KERNEL */\n\nsig_t   signal (int, sig_t);\nint     sigaction (int signum, const struct sigaction *act,\n                   struct sigaction *oldact);\nint     sigvec (int sig, struct sigvec *vec, struct sigvec *ovec);\nint     kill (pid_t pid, int sig);\nint     sigpause (int mask);\nint     sigblock (int mask);\nint     sigsetmask (int mask);\nint     sigprocmask (int how, const sigset_t *set, sigset_t *oldset);\nint     siginterrupt (int sig, int flag);\nint     sigsuspend (const sigset_t *mask);\n\n#endif /* KERNEL */\n\n#endif /* NSIG */\n"
  },
  {
    "path": "sys/sys/signalvar.h",
    "content": "/*\n * Copyright (c) 1991, 1993\n *  The Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *  This product includes software developed by the University of\n *  California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#ifndef _SYS_SIGNALVAR_H_       /* tmp for user.h */\n#define _SYS_SIGNALVAR_H_\n\n/*\n * Kernel signal definitions and data structures,\n * not exported to user programs.\n *\n * For 2BSD the parts that did not apply were cut out.\n */\n\n/* signal flags */\n#define SAS_OLDMASK     0x01    /* need to restore mask before pause */\n#define SAS_ALTSTACK    0x02    /* have alternate signal stack */\n\n/* additional signal action values, used only temporarily/internally */\n#define SIG_CATCH       (sig_t) 2\n#define SIG_HOLD        (sig_t) 3\n\n/*\n * Determine signal that should be delivered to process p, the current\n * process, 0 if none.  If there is a pending stop signal with default\n * action, the process stops in issignal().\n *\n * This probably should be a routine (assembly) instead of a macro due\n * to the voluminous code generated by all of the 'long' operations.\n */\n#define CURSIG(p)   (((p)->p_sig == 0 || \\\n                        (((p)->p_flag & P_TRACED) == 0 && \\\n                        ((p)->p_sig & ~(p)->p_sigmask) == 0)) ? \\\n                        0 : issignal(p))\n\n/*\n * Signal properties and actions.\n * The array below categorizes the signals and their default actions\n * according to the following properties:\n */\n#define SA_KILL         0x01    /* terminates process by default */\n#define SA_CORE         0x02    /* ditto and coredumps */\n#define SA_STOP         0x04    /* suspend process */\n#define SA_TTYSTOP      0x08    /* ditto, from tty */\n#define SA_IGNORE       0x10    /* ignore by default */\n#define SA_CONT         0x20    /* continue if suspended */\n\n#ifdef  SIGPROP\nconst char sigprop [NSIG + 1] = {\n    0,                      /* unused */\n    SA_KILL,                /* SIGHUP */\n    SA_KILL,                /* SIGINT */\n    SA_KILL | SA_CORE,      /* SIGQUIT */\n    SA_KILL | SA_CORE,      /* SIGILL */\n    SA_KILL | SA_CORE,      /* SIGTRAP */\n    SA_KILL | SA_CORE,      /* SIGABRT */\n    SA_KILL | SA_CORE,      /* SIGEMT */\n    SA_KILL | SA_CORE,      /* SIGFPE */\n    SA_KILL,                /* SIGKILL */\n    SA_KILL | SA_CORE,      /* SIGBUS */\n    SA_KILL | SA_CORE,      /* SIGSEGV */\n    SA_KILL | SA_CORE,      /* SIGSYS */\n    SA_KILL,                /* SIGPIPE */\n    SA_KILL,                /* SIGALRM */\n    SA_KILL,                /* SIGTERM */\n    SA_IGNORE,              /* SIGURG */\n    SA_STOP,                /* SIGSTOP */\n    SA_STOP | SA_TTYSTOP,   /* SIGTSTP */\n    SA_IGNORE | SA_CONT,    /* SIGCONT */\n    SA_IGNORE,              /* SIGCHLD */\n    SA_STOP | SA_TTYSTOP,   /* SIGTTIN */\n    SA_STOP | SA_TTYSTOP,   /* SIGTTOU */\n    SA_IGNORE,              /* SIGIO */\n    SA_KILL,                /* SIGXCPU */\n    SA_KILL,                /* SIGXFSZ */\n    SA_KILL,                /* SIGVTALRM */\n    SA_KILL,                /* SIGPROF */\n    SA_IGNORE,              /* SIGWINCH  */\n    SA_IGNORE,              /* SIGINFO */\n    SA_KILL,                /* SIGUSR1 */\n    SA_KILL,                /* SIGUSR2 */\n};\n#endif /* SIGPROP */\n\n#ifdef  KERNEL\n#define contsigmask (sigmask(SIGCONT))\n#define stopsigmask (sigmask(SIGSTOP) | sigmask(SIGTSTP) | \\\n                     sigmask(SIGTTIN) | sigmask(SIGTTOU))\n#define sigcantmask (sigmask(SIGKILL) | sigmask(SIGSTOP))\n#endif\n#endif  /* !_SYS_SIGNALVAR_H_ */\n"
  },
  {
    "path": "sys/sys/skel.h",
    "content": "/*\n * Ioctl definitions for skeleton driver.\n *\n * Copyright (C) 2015 Serge Vakulenko\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#ifndef _SKEL_H\n#define _SKEL_H\n\n#include <sys/ioctl.h>\n\n#define SKELCTL_SETMODE     _IO ('?', 0)        /* set driver mode mode */\n\n#define SKELCTL_IO(n)       _ION('?', 3, n)     /* transfer n bytes */\n\n#ifdef KERNEL\n#include \"conf.h\"\n\nint skeldev_open (dev_t dev, int flag, int mode);\nint skeldev_close (dev_t dev, int flag, int mode);\nint skeldev_read (dev_t dev, struct uio *uio, int flag);\nint skeldev_write (dev_t dev, struct uio *uio, int flag);\nint skeldev_ioctl (dev_t dev, u_int cmd, caddr_t addr, int flag);\n#endif\n\n#endif\n"
  },
  {
    "path": "sys/sys/spi.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * Ioctl definitions for SPI driver.\n */\n#ifndef _SPI_H\n#define _SPI_H\n\n#include <sys/ioctl.h>\n\n/*\n * User-level interface to the SPI port.\n */\n#define SPICTL_SETMODE      _IO ('p', 0)        /* set SPI mode */\n#define SPICTL_SETRATE      _IO ('p', 1)        /* set clock rate, kHz */\n#define SPICTL_SETSELPIN    _IO ('p', 2)        /* set select pin */\n\n#define SPICTL_IO8(n)       _ION('p', 3, n)     /* transfer n*8 bits */\n#define SPICTL_IO16(n)      _ION('p', 4, n)     /* transfer n*16 bits */\n#define SPICTL_IO32(n)      _ION('p', 5, n)     /* transfer n*32 bits */\n\n#define SPICTL_IO8R(n)      _ION('p', 6, n)     /* transfer R n*8 bits */\n#define SPICTL_IO16R(n)     _ION('p', 7, n)     /* transfer R n*16 bits */\n#define SPICTL_IO32R(n)     _ION('p', 8, n)     /* transfer R n*32 bits */\n\n#define SPICTL_IO8W(n)      _ION('p', 9, n)     /* transfer W n*8 bits */\n#define SPICTL_IO16W(n)     _ION('p', 10, n)    /* transfer W n*16 bits */\n#define SPICTL_IO32W(n)     _ION('p', 11, n)    /* transfer W n*32 bits */\n\n#define SPICTL_IO32B(n)     _ION('p', 12, n)    /* transfer BE n*32 bits */\n#define SPICTL_IO32RB(n)    _ION('p', 13, n)    /* transfer RBE n*32 bits */\n#define SPICTL_IO32WB(n)    _ION('p', 14, n)    /* transfer WBE n*32 bits */\n\n#ifdef KERNEL\n#include \"conf.h\"\n\n/*\n * Kernel-level interface to the SPI port.\n */\nstruct spiio {\n    struct spireg   *bus;\n    unsigned int    *cs_tris;\n    unsigned int    cs_pin;\n    unsigned int    baud;\n    unsigned int    mode;\n};\n\nextern int spi_setup(struct spiio *io, int channel, int cs);\nextern void spi_set_cspin(struct spiio *io, unsigned int *tris, unsigned int pin);\nextern void spi_select(struct spiio *io);\nextern void spi_deselect(struct spiio *io);\nextern void spi_set(struct spiio *io, unsigned int set);\nextern void spi_clr(struct spiio *io, unsigned int set);\nextern unsigned int spi_status(struct spiio *io);\nextern unsigned char spi_transfer(struct spiio *io, unsigned char data);\nextern void spi_bulk_write_32_be(struct spiio *io, unsigned int len, char *data);\nextern void spi_bulk_write_32(struct spiio *io, unsigned int len, char *data);\nextern void spi_bulk_write_16(struct spiio *io, unsigned int len, char *data);\nextern void spi_bulk_write(struct spiio *io, unsigned int len, unsigned char *data);\nextern void spi_bulk_read_32_be(struct spiio *io, unsigned int len, char *data);\nextern void spi_bulk_read_32(struct spiio *io, unsigned int len, char *data);\nextern void spi_bulk_read_16(struct spiio *io, unsigned int len, char *data);\nextern void spi_bulk_read(struct spiio *io, unsigned int len, unsigned char *data);\nextern void spi_bulk_rw_32_be(struct spiio *io, unsigned int len, char *data);\nextern void spi_bulk_rw_32(struct spiio *io, unsigned int len, char *data);\nextern void spi_bulk_rw_16(struct spiio *io, unsigned int len, char *data);\nextern void spi_bulk_rw(struct spiio *io, unsigned int len, unsigned char *data);\nextern void spi_brg(struct spiio *io, unsigned int baud);\nextern char *spi_name(struct spiio *io);\nextern char spi_csname(struct spiio *io);\nextern int spi_cspin(struct spiio *io);\nextern unsigned int spi_get_brg(struct spiio *io);\n\n/*\n * Routines of the SPI device driver.\n */\nint spidev_open (dev_t dev, int flag, int mode);\nint spidev_close (dev_t dev, int flag, int mode);\nint spidev_read (dev_t dev, struct uio *uio, int flag);\nint spidev_write (dev_t dev, struct uio *uio, int flag);\nint spidev_ioctl (dev_t dev, u_int cmd, caddr_t addr, int flag);\n\n#endif\n\n#endif\n"
  },
  {
    "path": "sys/sys/stat.h",
    "content": "/*\n * Copyright (c) 1982, 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#ifndef _STAT_H_\n#define _STAT_H_\n\n#include <sys/time.h>\n\nstruct  stat\n{\n    dev_t   st_dev;\n    ino_t   st_ino;\n    u_int   st_mode;\n    int     st_nlink;\n    uid_t   st_uid;\n    gid_t   st_gid;\n    dev_t   st_rdev;\n    off_t   st_size;\n    time_t  st_atime;\n    time_t  st_mtime;\n    time_t  st_ctime;\n    long    st_blksize;\n    long    st_blocks;\n    u_int   st_flags;\n};\n\n#define S_IFMT  0170000         /* type of file */\n#define     S_IFDIR 0040000     /* directory */\n#define     S_IFCHR 0020000     /* character special */\n#define     S_IFBLK 0060000     /* block special */\n#define     S_IFREG 0100000     /* regular */\n#define     S_IFLNK 0120000     /* symbolic link */\n#define     S_IFSOCK 0140000    /* socket */\n#define S_ISUID 0004000         /* set user id on execution */\n#define S_ISGID 0002000         /* set group id on execution */\n#define S_ISVTX 0001000         /* save swapped text even after use */\n#define S_IREAD 0000400         /* read permission, owner */\n#define S_IWRITE 0000200        /* write permission, owner */\n#define S_IEXEC 0000100         /* execute/search permission, owner */\n\n/*\n * Definitions of flags in mode that are 4.4 compatible.\n */\n\n#define S_IFIFO 0010000         /* named pipe (fifo) - Not used by 2.11BSD */\n\n#define S_IRWXU 0000700         /* RWX mask for owner */\n#define S_IRUSR 0000400         /* R for owner */\n#define S_IWUSR 0000200         /* W for owner */\n#define S_IXUSR 0000100         /* X for owner */\n\n#define S_IRWXG 0000070         /* RWX mask for group */\n#define S_IRGRP 0000040         /* R for group */\n#define S_IWGRP 0000020         /* W for group */\n#define S_IXGRP 0000010         /* X for group */\n\n#define S_IRWXO 0000007         /* RWX mask for other */\n#define S_IROTH 0000004         /* R for other */\n#define S_IWOTH 0000002         /* W for other */\n#define S_IXOTH 0000001         /* X for other */\n\n#define S_ISDIR(m)  ((m & S_IFMT) == S_IFDIR)   /* directory */\n#define S_ISCHR(m)  ((m & S_IFMT) == S_IFCHR)   /* character special */\n#define S_ISBLK(m)  ((m & S_IFMT) == S_IFBLK)   /* block special */\n#define S_ISREG(m)  ((m & S_IFMT) == S_IFREG)   /* regular */\n#define S_ISLNK(m)  ((m & S_IFMT) == S_IFLNK)   /* symbolic link */\n#define S_ISSOCK(m) ((m & S_IFMT) == S_IFSOCK)  /* socket */\n\n/*\n * Definitions of flags stored in file flags word.  Different from 4.4 because\n * 2.11BSD only could afford a u_short for the flags.  It is not a great\n * inconvenience since there are still 5 bits in each byte available for\n * future use.\n *\n * Super-user and owner changeable flags.\n */\n#define UF_SETTABLE     0x00ff      /* mask of owner changeable flags */\n#define UF_NODUMP       0x0001      /* do not dump file */\n#define UF_IMMUTABLE    0x0002      /* file may not be changed */\n#define UF_APPEND       0x0004      /* writes to file may only append */\n/*\n * Super-user changeable flags.\n */\n#define SF_SETTABLE     0xff00      /* mask of superuser changeable flags */\n#define SF_ARCHIVED     0x0100      /* file is archived */\n#define SF_IMMUTABLE    0x0200      /* file may not be changed */\n#define SF_APPEND       0x0400      /* writes to file may only append */\n\n#ifdef KERNEL\n/*\n * Shorthand abbreviations of above.\n */\n#define APPEND          (UF_APPEND | SF_APPEND)\n#define IMMUTABLE       (UF_IMMUTABLE | SF_IMMUTABLE)\n#else\n\nint     chmod (const char *path, mode_t mode);\nint     fchmod (int fd, mode_t mode);\nint     mknod (const char *path, mode_t mode, dev_t dev);\nint     mkdir (const char *path, mode_t mode);\nint     stat (const char *path, struct stat *sb);\nmode_t  umask (mode_t cmask);\n\n#endif\n\n#endif /* !_STAT_H_ */\n"
  },
  {
    "path": "sys/sys/stdint.h",
    "content": "#ifndef _STDINT_H\n#define _STDINT_H\n\ntypedef signed char         int8_t;\ntypedef short int           int16_t;\ntypedef int                 int32_t;\ntypedef long long           int64_t;\n\ntypedef unsigned char       uint8_t;\ntypedef unsigned short int  uint16_t;\ntypedef unsigned int        uint32_t;\ntypedef unsigned long long  uint64_t;\n\n#define UINT32_C(x)         (x##U)\n#define UINT64_C(x)         (x##ULL)\n\n#endif /* _STDINT_H */\n"
  },
  {
    "path": "sys/sys/swap.h",
    "content": "#ifndef _SWAP_H\n#define _SWAP_H\n\n#ifdef KERNEL\n#include \"ioctl.h\"\n#else\n#include <sys/ioctl.h>\n#endif\n\n#define TFALLOC _IOWR('s', 1, off_t)\n\n#ifdef KERNEL\n\nextern int\tswopen(dev_t dev, int mode, int flag);\nextern int\tswclose(dev_t dev, int mode, int flag);\nextern void\tswstrategy(struct buf *bp);\nextern daddr_t\tswsize(dev_t dev);\nextern int\tswcread(dev_t dev, struct uio *uio, int flag);\nextern int\tswcwrite(dev_t dev, struct uio *uio, int flag);\nextern int\tswcioctl(dev_t dev, u_int cmd, caddr_t addr, int flag);\nextern int\tswcopen(dev_t dev, int mode, int flag);\nextern int\tswcclose(dev_t dev, int mode, int flag);\n\n#endif /* KERNEL */\n\n#endif /* !_SWAP_H */\n"
  },
  {
    "path": "sys/sys/sysctl.h",
    "content": "/*\n * Copyright (c) 1989, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Mike Karels at Berkeley Software Design, Inc.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *\tThis product includes software developed by the University of\n *\tCalifornia, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n *\t@(#)sysctl.h\t8.1.3 (2.11BSD) 1999/4/29\n */\n\n#ifndef\t_SYS_SYSCTL_H_\n#define\t_SYS_SYSCTL_H_\n\n/*\n * These are for the eproc, etext, einode, efile and map structures.\n */\n#ifndef\tKERNEL\n#include <sys/time.h>\n#include <sys/resource.h>\n#include <sys/file.h>\n#include <sys/inode.h>\n#include <sys/proc.h>\n#include <sys/vm.h>\n#include <sys/map.h>\n#endif\n\n/*\n * Definitions for sysctl call.  The sysctl call uses a hierarchical name\n * for objects that can be examined or modified.  The name is expressed as\n * a sequence of integers.  Like a file path name, the meaning of each\n * component depends on its place in the hierarchy.  The top-level and kern\n * identifiers are defined here, and other identifiers are defined in the\n * respective subsystem header files.\n */\n\n#define\tCTL_MAXNAME\t12\t/* largest number of components supported */\n\n/*\n * Each subsystem defined by sysctl defines a list of variables\n * for that subsystem.  Each name is either a node with further\n * levels defined below it, or it is a leaf of some particular\n * type given below.  Each sysctl level defines a set of name/type\n * pairs to be used by sysctl(1) in manipulating the subsystem.\n */\nstruct ctlname {\n\tchar\t*ctl_name;\t/* subsystem name */\n\tint\t ctl_type;\t/* type of name */\n};\n#define\tCTLTYPE_NODE\t1\t/* name is a node */\n#define\tCTLTYPE_INT\t2\t/* name describes a 16-bit integer */\n#define\tCTLTYPE_STRING\t3\t/* name describes a string */\n#define\tCTLTYPE_LONG\t4\t/* name describes a 32-bit number */\n#define\tCTLTYPE_STRUCT\t5\t/* name describes a structure */\n\n/*\n * Top-level identifiers\n */\n#define\tCTL_UNSPEC\t0\t/* unused */\n#define\tCTL_KERN\t1\t/* \"high kernel\": proc, limits */\n#define\tCTL_VM\t\t2\t/* virtual memory */\n#define\tCTL_FS\t\t3\t/* file system, mount type is next */\n#define\tCTL_NET\t\t4\t/* network, see socket.h */\n#define\tCTL_DEBUG\t5\t/* debugging parameters */\n#define\tCTL_HW\t\t6\t/* generic cpu/io */\n#define\tCTL_MACHDEP\t7\t/* machine dependent */\n#define\tCTL_USER\t8\t/* user-level */\n#define\tCTL_MAXID\t9\t/* number of valid top-level ids */\n\n#ifndef\tKERNEL\n#define\tCTL_NAMES { \\\n\t{ 0, 0 }, \\\n\t{ \"kern\", CTLTYPE_NODE }, \\\n\t{ \"vm\", CTLTYPE_NODE }, \\\n\t{ \"fs\", CTLTYPE_NODE }, \\\n\t{ \"net\", CTLTYPE_NODE }, \\\n\t{ \"debug\", CTLTYPE_NODE }, \\\n\t{ \"hw\", CTLTYPE_NODE }, \\\n\t{ \"machdep\", CTLTYPE_NODE }, \\\n\t{ \"user\", CTLTYPE_NODE }, \\\n}\n#endif\n\n/*\n * CTL_KERN identifiers\n */\n#define\tKERN_OSTYPE\t\t1\t/* string: system version */\n#define\tKERN_OSRELEASE\t\t2\t/* string: system release */\n#define\tKERN_OSREV\t\t3\t/* int: system revision */\n#define\tKERN_VERSION\t\t4\t/* string: compile time info */\n#define\tKERN_MAXINODES\t\t5\t/* int: max inodes */\n#define\tKERN_MAXPROC\t\t6\t/* int: max processes */\n#define\tKERN_MAXFILES\t\t7\t/* int: max open files */\n#define\tKERN_ARGMAX\t\t8\t/* int: max arguments to exec */\n#define\tKERN_SECURELVL\t\t9\t/* int: system security level */\n#define\tKERN_HOSTNAME\t\t10\t/* string: hostname */\n#define\tKERN_HOSTID\t\t11\t/* int: host identifier */\n#define\tKERN_CLOCKRATE\t\t12\t/* struct: struct clockinfo */\n#define\tKERN_INODE\t\t13\t/* struct: inode structures */\n#define\tKERN_PROC\t\t14\t/* struct: process entries */\n#define\tKERN_FILE\t\t15\t/* struct: file entries */\n#define\tKERN_PROF\t\t16\t/* node: kernel profiling info */\n#define\tKERN_POSIX1\t\t17\t/* int: POSIX.1 version */\n#define\tKERN_NGROUPS\t\t18\t/* int: # of supplemental group ids */\n#define\tKERN_JOB_CONTROL\t19\t/* int: is job control available */\n#define\tKERN_SAVED_IDS\t\t20\t/* int: saved set-user/group-ID */\n#define\tKERN_BOOTTIME\t\t21\t/* struct: time kernel was booted */\n#define\tKERN_MAXTEXTS\t\t22\t/* int: # of text entries */\n#define\tKERN_TEXT\t\t23\t/* struct: text entries */\n#define\tKERN_ACCTTHRESH\t\t24\t/* int: accounting daemon threshold */\n#define\tKERN_OSVERSION\t\t25\t/* string: kernel build version */\n#define\tKERN_MAXID\t\t26\t/* number of valid kern ids */\n\n#ifndef\tKERNEL\n#define\tCTL_KERN_NAMES { \\\n\t{ 0, 0 }, \\\n\t{ \"ostype\", CTLTYPE_STRING }, \\\n\t{ \"osrelease\", CTLTYPE_STRING }, \\\n\t{ \"osrevision\", CTLTYPE_LONG }, \\\n\t{ \"version\", CTLTYPE_STRING }, \\\n\t{ \"maxinodes\", CTLTYPE_INT }, \\\n\t{ \"maxproc\", CTLTYPE_INT }, \\\n\t{ \"maxfiles\", CTLTYPE_INT }, \\\n\t{ \"argmax\", CTLTYPE_INT }, \\\n\t{ \"securelevel\", CTLTYPE_INT }, \\\n\t{ \"hostname\", CTLTYPE_STRING }, \\\n\t{ \"hostid\", CTLTYPE_LONG }, \\\n\t{ \"clockrate\", CTLTYPE_STRUCT }, \\\n\t{ \"inode\", CTLTYPE_STRUCT }, \\\n\t{ \"proc\", CTLTYPE_STRUCT }, \\\n\t{ \"file\", CTLTYPE_STRUCT }, \\\n\t{ \"profiling\", CTLTYPE_NODE }, \\\n\t{ \"posix1version\", CTLTYPE_INT }, \\\n\t{ \"ngroups\", CTLTYPE_INT }, \\\n\t{ \"job_control\", CTLTYPE_INT }, \\\n\t{ \"saved_ids\", CTLTYPE_INT }, \\\n\t{ \"boottime\", CTLTYPE_STRUCT }, \\\n\t{ \"maxtexts\", CTLTYPE_INT }, \\\n\t{ \"text\", CTLTYPE_STRUCT }, \\\n\t{ \"acctthresh\", CTLTYPE_INT }, \\\n\t{ \"osversion\", CTLTYPE_STRING }, \\\n}\n#endif\n\n/*\n * KERN_PROC subtypes\n */\n#define\tKERN_PROC_ALL\t\t0\t/* everything */\n#define\tKERN_PROC_PID\t\t1\t/* by process id */\n#define\tKERN_PROC_PGRP\t\t2\t/* by process group id */\n#define\tKERN_PROC_SESSION\t3\t/* by session of pid - NOT IN 2.11 */\n#define\tKERN_PROC_TTY\t\t4\t/* by controlling tty */\n#define\tKERN_PROC_UID\t\t5\t/* by effective uid */\n#define\tKERN_PROC_RUID\t\t6\t/* by real uid */\n\n/*\n * KERN_PROC subtype ops return arrays of augmented proc structures:\n */\nstruct kinfo_proc {\n\tstruct proc kp_proc;\t\t/* proc structure */\n\tstruct eproc {\n\t\tstruct proc\t*e_paddr;\t/* address of proc */\n\t\tdev_t\t\t e_tdev;\t/* controlling tty dev */\n\t\tpid_t\t\t e_tpgid;\t/* tty process group id */\n\t\tuid_t\t\t e_ruid;\t/* real uid */\n\t} kp_eproc;\n};\n\n/*\n * KERN_INODE returns an array of augmented inode structures:\n*/\nstruct kinfo_inode {\n\tstruct inode\t*kp_inodep;\t/* address of inode */\n\tstruct inode\t kp_inode;\t/* inode structure */\n};\n\n/*\n * KERN_FILE returns an array of augmented file structures:\n*/\nstruct kinfo_file {\n\tstruct file\t*kp_filep;\t/* address of file */\n\tstruct file\t kp_file;\t/* file structure */\n};\n\n/*\n * CTL_HW identifiers\n */\n#define\tHW_MACHINE\t\t1\t/* string: machine class */\n#define\tHW_MODEL\t\t2\t/* string: specific machine model */\n#define\tHW_NCPU\t\t\t3\t/* int: number of cpus */\n#define\tHW_BYTEORDER\t\t4\t/* int: machine byte order */\n#define\tHW_PHYSMEM\t\t5\t/* int: total memory */\n#define\tHW_USERMEM\t\t6\t/* int: non-kernel memory */\n#define\tHW_PAGESIZE\t\t7\t/* int: software page size */\n#define\tHW_DISKNAMES\t\t8\t/* strings: disk drive names */\n#define\tHW_DISKSTATS\t\t9\t/* struct: diskstats[] */\n#define\tHW_MACHINE_ARCH\t\t10\t/* string: machine architecture */\n#define\tHW_MAXID\t\t11\t/* number of valid hw ids */\n\n#ifndef\tKERNEL\n#define\tCTL_HW_NAMES { \\\n\t{ 0, 0 }, \\\n\t{ \"machine\", CTLTYPE_STRING }, \\\n\t{ \"model\", CTLTYPE_STRING }, \\\n\t{ \"ncpu\", CTLTYPE_INT }, \\\n\t{ \"byteorder\", CTLTYPE_INT }, \\\n\t{ \"physmem\", CTLTYPE_LONG }, \\\n\t{ \"usermem\", CTLTYPE_LONG }, \\\n\t{ \"pagesize\", CTLTYPE_INT }, \\\n\t{ \"disknames\", CTLTYPE_STRUCT }, \\\n\t{ \"diskstats\", CTLTYPE_STRUCT }, \\\n\t{ \"machine_arch\", CTLTYPE_STRING }, \\\n}\n#endif\n\n#ifndef\tKERNEL\n/*\n * CTL_USER definitions\n */\n#define\tUSER_CS_PATH\t\t1\t/* string: _CS_PATH */\n#define\tUSER_BC_BASE_MAX\t2\t/* int: BC_BASE_MAX */\n#define\tUSER_BC_DIM_MAX\t\t3\t/* int: BC_DIM_MAX */\n#define\tUSER_BC_SCALE_MAX\t4\t/* int: BC_SCALE_MAX */\n#define\tUSER_BC_STRING_MAX\t5\t/* int: BC_STRING_MAX */\n#define\tUSER_COLL_WEIGHTS_MAX\t6\t/* int: COLL_WEIGHTS_MAX */\n#define\tUSER_EXPR_NEST_MAX\t7\t/* int: EXPR_NEST_MAX */\n#define\tUSER_LINE_MAX\t\t8\t/* int: LINE_MAX */\n#define\tUSER_RE_DUP_MAX\t\t9\t/* int: RE_DUP_MAX */\n#define\tUSER_POSIX2_VERSION\t10\t/* int: POSIX2_VERSION */\n#define\tUSER_POSIX2_C_BIND\t11\t/* int: POSIX2_C_BIND */\n#define\tUSER_POSIX2_C_DEV\t12\t/* int: POSIX2_C_DEV */\n#define\tUSER_POSIX2_CHAR_TERM\t13\t/* int: POSIX2_CHAR_TERM */\n#define\tUSER_POSIX2_FORT_DEV\t14\t/* int: POSIX2_FORT_DEV */\n#define\tUSER_POSIX2_FORT_RUN\t15\t/* int: POSIX2_FORT_RUN */\n#define\tUSER_POSIX2_LOCALEDEF\t16\t/* int: POSIX2_LOCALEDEF */\n#define\tUSER_POSIX2_SW_DEV\t17\t/* int: POSIX2_SW_DEV */\n#define\tUSER_POSIX2_UPE\t\t18\t/* int: POSIX2_UPE */\n#define\tUSER_STREAM_MAX\t\t19\t/* int: POSIX2_STREAM_MAX */\n#define\tUSER_TZNAME_MAX\t\t20\t/* int: POSIX2_TZNAME_MAX */\n#define\tUSER_MAXID\t\t21\t/* number of valid user ids */\n\n#define\tCTL_USER_NAMES { \\\n\t{ 0, 0 }, \\\n\t{ \"cs_path\", CTLTYPE_STRING }, \\\n\t{ \"bc_base_max\", CTLTYPE_INT }, \\\n\t{ \"bc_dim_max\", CTLTYPE_INT }, \\\n\t{ \"bc_scale_max\", CTLTYPE_INT }, \\\n\t{ \"bc_string_max\", CTLTYPE_INT }, \\\n\t{ \"coll_weights_max\", CTLTYPE_INT }, \\\n\t{ \"expr_nest_max\", CTLTYPE_INT }, \\\n\t{ \"line_max\", CTLTYPE_INT }, \\\n\t{ \"re_dup_max\", CTLTYPE_INT }, \\\n\t{ \"posix2_version\", CTLTYPE_INT }, \\\n\t{ \"posix2_c_bind\", CTLTYPE_INT }, \\\n\t{ \"posix2_c_dev\", CTLTYPE_INT }, \\\n\t{ \"posix2_char_term\", CTLTYPE_INT }, \\\n\t{ \"posix2_fort_dev\", CTLTYPE_INT }, \\\n\t{ \"posix2_fort_run\", CTLTYPE_INT }, \\\n\t{ \"posix2_localedef\", CTLTYPE_INT }, \\\n\t{ \"posix2_sw_dev\", CTLTYPE_INT }, \\\n\t{ \"posix2_upe\", CTLTYPE_INT }, \\\n\t{ \"stream_max\", CTLTYPE_INT }, \\\n\t{ \"tzname_max\", CTLTYPE_INT }, \\\n}\n#endif\n\n/*\n * CTL_DEBUG definitions\n *\n * Second level identifier specifies which debug variable.\n * Third level identifier specifies which structure component.\n */\n#define\tCTL_DEBUG_NAME\t\t0\t/* string: variable name */\n#define\tCTL_DEBUG_VALUE\t\t1\t/* int: variable value */\n#define\tCTL_DEBUG_MAXID\t\t20\n\n/*\n * Locking and stats\n */\nstruct sysctl_lock {\n\tint sl_lock;\n\tint sl_want;\n\tint sl_locked;\n};\n\n#ifdef\tKERNEL\n\n#ifdef\tDEBUG\n/*\n * CTL_DEBUG variables.\n *\n * These are declared as separate variables so that they can be\n * individually initialized at the location of their associated\n * variable.  The loader prevents multiple use by issuing errors\n * if a variable is initialized in more than one place.  They are\n * aggregated into an array in debug_sysctl(), so that it can\n * conveniently locate them when queried.  If more debugging\n * variables are added, they must also be declared here and also\n * entered into the array.\n */\nstruct ctldebug {\n\tchar\t*debugname;\t\t/* name of debugging variable */\n\tint\t*debugvar;\t\t/* pointer to debugging variable */\n};\nextern struct ctldebug debug0, debug1, debug2, debug3, debug4;\nextern struct ctldebug debug5, debug6, debug7, debug8, debug9;\nextern struct ctldebug debug10, debug11, debug12, debug13, debug14;\nextern struct ctldebug debug15, debug16, debug17, debug18, debug19;\n#endif\t/* DEBUG */\n\nstruct sysctl_lock memlock;\n\n/*\n * Internal sysctl function calling convention:\n *\n *\t(*sysctlfn)(name, namelen, oldval, oldlenp, newval, newlen);\n *\n * The name parameter points at the next component of the name to be\n * interpreted.  The namelen parameter is the number of integers in\n * the name.\n */\ntypedef int (sysctlfn)(int *, u_int, void *, size_t *, void *, size_t);\n\nint\tsysctl_int(void *, size_t *, void *, size_t, int *);\nint\tsysctl_rdint(void *, size_t *, void *, int);\nint\tsysctl_long(void *, size_t *, void *, size_t, long *);\nint\tsysctl_rdlong(void *, size_t *, void *, long);\nint\tsysctl_string(void *, size_t *, void *, size_t, char *, int);\nint\tsysctl_rdstring(void *, size_t *, void *, const char *);\nint\tsysctl_struct(void *, size_t *, void *, size_t, void *, int);\nint\tsysctl_rdstruct(void *, size_t *, void *, void *, int);\n\nint\tsysctl_file(char *, size_t *);\nint\tsysctl_clockrate(char *, size_t *);\nint\tsysctl_inode(char *, size_t *);\nint\tsysctl_doproc(int *, u_int, char *, size_t *);\nvoid\tfill_eproc(struct proc *p, struct eproc *ep);\nvoid\tfill_from_u(struct proc *, uid_t *, struct tty **, dev_t *);\n\n#else\t/* !KERNEL */\n\nint\tsysctl(int *, u_int, void *, size_t *, void *, size_t);\nint\t__sysctl(int *, u_int, void *, size_t *, void *, size_t);\n\n#endif\t/* KERNEL */\n#endif\t/* !_SYS_SYSCTL_H_ */\n"
  },
  {
    "path": "sys/sys/syslimits.h",
    "content": "/*\t$OpenBSD: syslimits.h,v 1.14 2020/04/02 18:00:00 deraadt Exp $\t*/\n/*\t$NetBSD: syslimits.h,v 1.12 1995/10/05 05:26:19 thorpej Exp $\t*/\n\n/*\n * Copyright (c) 1988, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n *\t@(#)syslimits.h\t8.1 (Berkeley) 6/2/93\n */\n\n#define\tPATH_MAX\t\t 256\t/* max bytes in pathname */\n"
  },
  {
    "path": "sys/sys/syslog.h",
    "content": "/*\n * Copyright (c) 1982, 1986, 1988, 1993\n *  The Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *  This product includes software developed by the University of\n *  California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n *  @(#)syslog.h    8.1.2 (2.11BSD) 1999/06/18\n * $Id: syslog.h,v 1.4 1994/08/21 04:42:00 paul Exp $\n */\n\n#ifndef _SYS_SYSLOG_H_\n#define _SYS_SYSLOG_H_\n\n/*\n * priorities/facilities are encoded into a single 16-bit quantity, where the\n * bottom 3 bits are the priority (0-7) and the top 13 bits are the facility\n * (0-big number).  Both the priorities and the facilities map roughly\n * one-to-one to strings in the syslogd(8) source code.  This mapping is\n * included in this file.\n *\n * priorities (these are ordered)\n */\n#define LOG_EMERG       0   /* system is unusable */\n#define LOG_ALERT       1   /* action must be taken immediately */\n#define LOG_CRIT        2   /* critical conditions */\n#define LOG_ERR         3   /* error conditions */\n#define LOG_WARNING     4   /* warning conditions */\n#define LOG_NOTICE      5   /* normal but significant condition */\n#define LOG_INFO        6   /* informational */\n#define LOG_DEBUG       7   /* debug-level messages */\n\n#define LOG_PRIMASK     0x07    /* mask to extract priority part (internal) */\n                                /* extract priority */\n#define LOG_PRI(p)              ((p) & LOG_PRIMASK)\n#define LOG_MAKEPRI(fac, pri)   (((fac) << 3) | (pri))\n\n#ifdef SYSLOG_NAMES\n#define INTERNAL_NOPRI  0x10    /* the \"no priority\" priority */\n                                /* mark \"facility\" */\n#define INTERNAL_MARK   LOG_MAKEPRI(LOG_NFACILITIES, 0)\ntypedef struct _code {\n    char    *c_name;\n    int     c_val;\n} CODE;\n\nCODE prioritynames[] = {\n    \"alert\",    LOG_ALERT,\n    \"crit\",     LOG_CRIT,\n    \"debug\",    LOG_DEBUG,\n    \"emerg\",    LOG_EMERG,\n    \"err\",      LOG_ERR,\n    \"info\",     LOG_INFO,\n    \"none\",     INTERNAL_NOPRI,     /* INTERNAL */\n    \"notice\",   LOG_NOTICE,\n    \"warning\",  LOG_WARNING,\n    NULL,       -1,\n};\n#endif\n\n/* facility codes */\n#define LOG_KERN        (0<<3)  /* kernel messages */\n#define LOG_USER        (1<<3)  /* random user-level messages */\n#define LOG_MAIL        (2<<3)  /* mail system */\n#define LOG_DAEMON      (3<<3)  /* system daemons */\n#define LOG_AUTH        (4<<3)  /* security/authorization messages */\n#define LOG_SYSLOG      (5<<3)  /* messages generated internally by syslogd */\n#define LOG_LPR         (6<<3)  /* line printer subsystem */\n#define LOG_NEWS        (7<<3)  /* network news subsystem */\n#define LOG_UUCP        (8<<3)  /* UUCP subsystem */\n#define LOG_CRON        (9<<3)  /* clock daemon */\n#define LOG_AUTHPRIV    (10<<3) /* security/authorization messages (private) */\n#define LOG_FTP         (11<<3) /* ftp daemon */\n\n    /* other codes through 15 reserved for system use */\n#define LOG_LOCAL0      (16<<3) /* reserved for local use */\n#define LOG_LOCAL1      (17<<3) /* reserved for local use */\n#define LOG_LOCAL2      (18<<3) /* reserved for local use */\n#define LOG_LOCAL3      (19<<3) /* reserved for local use */\n#define LOG_LOCAL4      (20<<3) /* reserved for local use */\n#define LOG_LOCAL5      (21<<3) /* reserved for local use */\n#define LOG_LOCAL6      (22<<3) /* reserved for local use */\n#define LOG_LOCAL7      (23<<3) /* reserved for local use */\n\n#define LOG_NFACILITIES 24      /* current number of facilities */\n#define LOG_FACMASK     0x03f8  /* mask to extract facility part */\n                                /* facility of pri */\n#define LOG_FAC(p)      (((p) & LOG_FACMASK) >> 3)\n\n#ifdef SYSLOG_NAMES\nCODE facilitynames[] = {\n    \"auth\",     LOG_AUTH,\n    \"authpriv\", LOG_AUTHPRIV,\n    \"cron\",     LOG_CRON,\n    \"daemon\",   LOG_DAEMON,\n    \"ftp\",      LOG_FTP,\n    \"kern\",     LOG_KERN,\n    \"lpr\",      LOG_LPR,\n    \"mail\",     LOG_MAIL,\n    \"mark\",     INTERNAL_MARK,      /* INTERNAL */\n    \"news\",     LOG_NEWS,\n    \"syslog\",   LOG_SYSLOG,\n    \"user\",     LOG_USER,\n    \"uucp\",     LOG_UUCP,\n    \"local0\",   LOG_LOCAL0,\n    \"local1\",   LOG_LOCAL1,\n    \"local2\",   LOG_LOCAL2,\n    \"local3\",   LOG_LOCAL3,\n    \"local4\",   LOG_LOCAL4,\n    \"local5\",   LOG_LOCAL5,\n    \"local6\",   LOG_LOCAL6,\n    \"local7\",   LOG_LOCAL7,\n    NULL,       -1,\n};\n#endif\n\n#ifdef KERNEL\n#define LOG_PRINTF      -1  /* pseudo-priority to indicate use of printf */\n#else\nvoid syslog (int pri, const char *fmt, ...);\nvoid openlog (const char *ident, int logstat, int logfac);\nvoid closelog (void);\n#endif\n\n/*\n * arguments to setlogmask.\n */\n#define LOG_MASK(pri)   (1 << (pri))            /* mask for one priority */\n#define LOG_UPTO(pri)   ((1 << ((pri)+1)) - 1)  /* all priorities through pri */\n\n/*\n * Option flags for openlog.\n *\n * LOG_ODELAY no longer does anything.\n * LOG_NDELAY is the inverse of what it used to be.\n */\n#define LOG_PID         0x01    /* log the pid with each message */\n#define LOG_CONS        0x02    /* log on the console if errors in sending */\n#define LOG_ODELAY      0x04    /* delay open until first syslog() (default) */\n#define LOG_NDELAY      0x08    /* don't delay open */\n#define LOG_NOWAIT      0x10    /* don't wait for console forks: DEPRECATED */\n#define LOG_PERROR      0x20    /* log to stderr as well */\n\n#endif\n"
  },
  {
    "path": "sys/sys/systm.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * The `securelevel' variable controls the security level of the system.\n * It can only be decreased by process 1 (/sbin/init).\n *\n * Security levels are as follows:\n *   -1 permannently insecure mode - always run system in level 0 mode.\n *    0 insecure mode - immutable and append-only flags make be turned off.\n *  All devices may be read or written subject to permission modes.\n *    1 secure mode - immutable and append-only flags may not be changed;\n *  raw disks of mounted filesystems, /dev/mem, and /dev/kmem are\n *  read-only.\n *    2 highly secure mode - same as (1) plus raw disks are always\n *  read-only whether mounted or not. This level precludes tampering\n *  with filesystems by unmounting them, but also inhibits running\n *  newfs while the system is secured.\n *\n * In normal operation, the system runs in level 0 mode while single user\n * and in level 1 mode while multiuser. If level 2 mode is desired while\n * running multiuser, it can be set in the multiuser startup script\n * (/etc/rc.local) using sysctl(8). If it is desired to run the system\n * in level 0 mode while multiuser, initialize the variable securelevel\n * in /sys/kern/kern_sysctl.c to -1. Note that it is NOT initialized to\n * zero as that would allow the vmunix binary to be patched to -1.\n * Without initialization, securelevel loads in the BSS area which only\n * comes into existence when the kernel is loaded and hence cannot be\n * patched by a stalking hacker.\n */\n#include \"conf.h\"\n\nextern int securelevel;         /* system security level */\n\nextern const char version[];    /* system version */\nextern const char ostype[];     /* operating system name */\nextern const char osversion[];  /* operating system version */\nextern const char osrelease[];  /* operating system release */\n\n/*\n * Nblkdev is the number of entries (rows) in the block switch.\n * Used in bounds checking on major device numbers.\n */\nextern const int nblkdev;\n\n/*\n * Number of character switch entries.\n */\nextern const int nchrdev;\n\n/*\n * Number of system call entries.\n */\nextern const int nsysent;\n\nextern int  mpid;                   /* generic for unique process id's */\nextern char runin;                  /* scheduling flag */\nextern char runout;                 /* scheduling flag */\nextern int  runrun;                 /* scheduling flag */\nextern char curpri;                 /* more scheduling */\n\nextern u_int    swapstart, nswap;   /* start and size of swap space */\nextern int      updlock;            /* lock for sync */\nextern daddr_t  rablock;            /* block to be read ahead */\nextern dev_t    rootdev;            /* device of the root */\nextern dev_t    dumpdev;            /* device to take dumps on */\nextern long     dumplo;             /* offset into dumpdev */\nextern dev_t    swapdev;            /* swapping device */\nextern dev_t    pipedev;            /* pipe device */\n\nextern  const char icode[];         /* user init code */\nextern  const char icodeend[];      /* its end */\nextern  const char initflags[];     /* init flags string */\n\n#ifdef PIC32MX7 /* XXX PIC32 */\n#define __kernel_flash_start        KERNEL_FLASH_START\n#define __kernel_flash_end          KERNEL_FLASH_END\n#define __kernel_data_start         KERNEL_DATA_START\n#define __kernel_data_end           KERNEL_DATA_END\n#define __user_data_start           USER_DATA_START\n#define __user_data_end             USER_DATA_END\n#else\n/* Memory address symbols defined in kernel linker script. */\nextern char     __kernel_flash_start[];\nextern char     __kernel_flash_end[];\nextern char     __kernel_data_start[];\nextern char     __kernel_data_end[];\nextern char     __user_data_start[];\nextern char     __user_data_end[];\n#endif /* XXX PIC32 */\n\nstruct inode;\ndaddr_t bmap (struct inode *ip, daddr_t bn, int rwflg, int flags);\n\nextern void kmemdev();\n\n/*\n * Structure of the system-entry table\n */\nextern const struct sysent\n{\n    int     sy_narg;                /* total number of arguments */\n    void    (*sy_call) (void);      /* handler */\n} sysent[];\n\nextern const char *syscallnames[];\n\nextern int  noproc;                 /* no one is running just now */\nextern char *panicstr;\nextern int  boothowto;              /* reboot flags, from boot */\nextern int  selwait;\nextern size_t   physmem;            /* total amount of physical memory */\n\nextern dev_t get_cdev_by_name(char *);\nextern char *cdevname(dev_t dev);\n\nvoid panic (char *msg);\nvoid printf (char *fmt, ...);\nvoid uprintf (char *fmt, ...);      /* print to the current user's terminal */\nstruct tty;\nvoid tprintf (struct tty *tp, char *fmt, ...);  /* print to the specified terminal */\nint loginit (void);\nvoid log (int level, char *fmt, ...);\nint logwrt (char *buf, int len, int log);\nvoid logwakeup (int unit);\nvoid config (void);\nvoid cninit (void);\nvoid cnidentify (void);\nvoid cnputc (char c);\nint cngetc (void);\nint baduaddr (caddr_t addr);        /* detect bad user address */\nint badkaddr (caddr_t addr);        /* detect bad kernel address */\n\nint strncmp (const char *s1, const char *s2, size_t n);\nvoid bzero (void *s, size_t nbytes);\nvoid bcopy (const void *src, void *dest, size_t nbytes);\nint bcmp (const void *a, const void *b, size_t nbytes);\nint copystr (caddr_t src, caddr_t dest, u_int maxlen, u_int *copied);\nsize_t strlen (const char *s);\nint ffs (u_long i);         /* find the index of the lsb set bit */\nvoid insque (void *element, void *pred);\nvoid remque (void *element);\n\nvoid startup (void);                /* machine-dependent startup code */\nint chrtoblk (dev_t dev);           /* convert from character to block device number */\nint isdisk (dev_t dev, int type);   /* determine if a device is a disk */\nint iskmemdev (dev_t dev);          /* identify /dev/mem and /dev/kmem */\nvoid boot (dev_t dev, int howto);\n\n/*\n * Copy data from kernel space fromaddr to user space address toaddr.\n * Fromaddr and toaddr must be word aligned.  Returns zero on success,\n * EFAULT on failure.\n */\nint copyout (const caddr_t from, caddr_t to, u_int nbytes);\n\n/*\n * Copy data from user space fromaddr to kernel space address toaddr.\n * Fromaddr and toaddr must be word aligned.  Returns zero on success,\n * EFAULT on failure.\n */\nint copyin (const caddr_t from, caddr_t to, u_int nbytes);\n\n/*\n * Check if gid is a member of the group set.\n */\nint groupmember (gid_t gid);\n\n/*\n * Wake up all processes sleeping on chan.\n */\nvoid wakeup (caddr_t chan);\n\n/*\n * Allocate iostat disk monitoring slots for a driver.\n */\nvoid dk_alloc (int *dkn, int slots, char *name);\n\n/*\n * Initialize callouts.\n */\nvoid coutinit (void);\n\n/*\n * Syscalls.\n */\nvoid    nosys (void);\n\n/* 1.1 processes and protection */\nvoid    getpid (void);\nvoid    getppid (void), fork (void), rexit (void), execv (void), execve (void);\nvoid    wait4 (void), getuid (void), getgid (void), getgroups (void), setgroups (void);\nvoid    geteuid (void), getegid (void);\nvoid    getpgrp (void), setpgrp (void);\nvoid    setgid (void), setegid (void), setuid (void), seteuid (void);\nvoid    ucall (void);                   /* 2BSD calls */\n\n/* 1.2 memory management */\nvoid    brk (void);\nvoid    ustore (void);                                  /* 2BSD calls */\nvoid    ufetch (void);                                  /* 2BSD calls */\n\n/* 1.3 signals */\nvoid    sigstack (void), sigreturn (void);\nvoid    sigaction (void), sigprocmask (void), sigpending (void), sigaltstack (void), sigsuspend (void);\nvoid    sigwait (void), kill (void), killpg (void);\n\n/* 1.4 timing and statistics */\nvoid    gettimeofday (void), settimeofday (void);\nvoid    getitimer (void), setitimer (void);\nvoid    adjtime (void);\n\n/* 1.5 descriptors */\nvoid    getdtablesize (void), dup (void), dup2 (void), close (void);\nvoid    pselect (void), select (void), fcntl (void), flock (void);\n\n/* 1.6 resource controls */\nvoid    getpriority (void), setpriority (void), getrusage (void), getrlimit (void), setrlimit (void);\n\n/* 1.7 system operation support */\nvoid    umount (void), smount (void);\nvoid    sync (void), reboot (void), __sysctl (void);\n\n/* 2.1 generic operations */\nvoid    read (void), write (void), readv (void), writev (void), ioctl (void);\n\n/* 2.2 file system */\nvoid    chdir (void), fchdir (void), chroot (void);\nvoid    mkdir (void), rmdir (void), chflags (void), fchflags (void);\nvoid    open (void), mknod (void), unlink (void), stat (void), fstat (void), lstat (void);\nvoid    chown (void), fchown (void), chmod (void), fchmod (void), utimes (void);\nvoid    link (void), symlink (void), readlink (void), rename (void);\nvoid    lseek (void), truncate (void), ftruncate (void), saccess (void), fsync (void);\nvoid    statfs (void), fstatfs (void), getfsstat (void);\n\n/* 2.3 communications */\nvoid    socket (void), bind (void), listen (void), accept (void), connect (void);\nvoid    socketpair (void), sendto (void), send (void), recvfrom (void), recv (void);\nvoid    sendmsg (void), recvmsg (void), shutdown (void), setsockopt (void), getsockopt (void);\nvoid    getsockname (void), getpeername (void), pipe (void);\n\nvoid    umask (void);           /* XXX */\n\n/* 2.4 processes */\nvoid    ptrace (void);\n\nvoid    profil (void);          /* 'cuz sys calls are interruptible */\nvoid    vhangup (void);         /* should just do in exit (void) */\nvoid    vfork (void);           /* awaiting fork w/ copy on write */\n\n/*\n * Drivers.\n */\nstruct buf;\nstruct uio;\n\nvoid cninit();\nint cnopen (dev_t dev, int flag, int mode);\nint cnclose (dev_t dev, int flag, int mode);\nint cnread (dev_t dev, struct uio *uio, int flag);\nint cnwrite (dev_t dev, struct uio *uio, int flag);\nint cnioctl (dev_t dev, u_int cmd, caddr_t addr, int flag);\nint cnselect (dev_t dev, int rw);\n\n#ifdef TS_ISOPEN\nextern struct tty cnttys[];\n#endif\n\nint mmrw (dev_t dev, struct uio *uio, int flag);\nint seltrue (dev_t dev, int rw);\nvoid nostrategy (struct buf *bp);\nvoid nonet (void);\n\nint syopen (dev_t dev, int flag, int mode);\nint syread (dev_t dev, struct uio *uio, int flag);\nint sywrite (dev_t dev, struct uio *uio, int flag);\nint syioctl (dev_t dev, u_int cmd, caddr_t addr, int flag);\nint syselect (dev_t dev, int rw);\n\nint logopen (dev_t dev, int flag, int mode);\nint logclose (dev_t dev, int flag, int mode);\nint logread (dev_t dev, struct uio *uio, int flag);\nint logioctl (dev_t dev, u_int cmd, caddr_t addr, int flag);\nint logselect (dev_t dev, int rw);\n\nint fdopen (dev_t dev, int flag, int mode);\nint dupfdopen (int indx, int dfd, int mode, int error);\n"
  },
  {
    "path": "sys/sys/time.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#ifndef _SYS_TIME_H_\n#define _SYS_TIME_H_\n\n#include <sys/types.h>\n\n/*\n * Structure returned by gettimeofday(2) system call,\n * and used in other calls.\n */\nstruct timeval {\n    long    tv_sec;         /* seconds */\n    long    tv_usec;        /* and microseconds */\n};\n\n/*\n * Structure defined by POSIX.4 to be like a timeval but with nanoseconds\n * instead of microseconds.  Silly on a PDP-11 but keeping the names the\n * same makes life simpler than changing the names.\n*/\nstruct timespec {\n    time_t tv_sec;          /* seconds */\n    long   tv_nsec;         /* and nanoseconds */\n};\n\nstruct timezone {\n    int     tz_minuteswest; /* minutes west of Greenwich */\n    int     tz_dsttime;     /* type of dst correction */\n};\n#define DST_NONE    0       /* not on dst */\n#define DST_USA     1       /* USA style dst */\n#define DST_AUST    2       /* Australian style dst */\n#define DST_WET     3       /* Western European dst */\n#define DST_MET     4       /* Middle European dst */\n#define DST_EET     5       /* Eastern European dst */\n#define DST_CAN     6       /* Canada */\n\n/*\n * Operations on timevals.\n *\n * NB: timercmp does not work for >= or <=.\n */\n#define timerisset(tvp)     ((tvp)->tv_sec || (tvp)->tv_usec)\n#define timercmp(tvp, uvp, cmp) \\\n                            ((tvp)->tv_sec cmp (uvp)->tv_sec || \\\n                             (tvp)->tv_sec == (uvp)->tv_sec && \\\n                             (tvp)->tv_usec cmp (uvp)->tv_usec)\n#define timerclear(tvp)     (tvp)->tv_sec = (tvp)->tv_usec = 0\n\n/*\n * Names of the interval timers, and structure\n * defining a timer setting.\n */\n#define ITIMER_REAL     0\n#define ITIMER_VIRTUAL  1\n#define ITIMER_PROF     2\n\nstruct  k_itimerval {\n    long    it_interval;            /* timer interval */\n    long    it_value;               /* current value */\n};\n\nstruct  itimerval {\n    struct  timeval it_interval;    /* timer interval */\n    struct  timeval it_value;       /* current value */\n};\n\n#ifdef KERNEL\n/*\n * Round up a proposed time value to a minimal resolution of the clock.\n */\nint itimerfix (struct timeval *tv);\n\n/*\n * Add and subtract routines for timevals.\n */\nvoid timevaladd (struct timeval *t1, struct timeval *t2);\nvoid timevalsub (struct timeval *t1, struct timeval *t2);\n\n/*\n * Compute number of hz until specified time.\n */\nint hzto (struct timeval *tv);\n\n#else\n#include <time.h>\n\nint gettimeofday (struct timeval *tv, struct timezone *tz);\nint settimeofday (const struct timeval *tv, const struct timezone *tz);\nint utimes (const char *filename, const struct timeval times[2]);\nint getitimer (int which, struct itimerval *curr_value);\nint setitimer (int which, const struct itimerval *new_value,\n           struct itimerval *old_value);\nchar *tztab (int zone, int dst);\n\n#endif\n\n/*\n * KERN_CLOCKRATE clock information structure\n */\nstruct clockinfo {\n    int     tick;       /* micro-seconds per hz tick */\n    int     hz;         /* clock frequency */\n    int     stathz;     /* statistics clock frequency */\n    int     profhz;     /* profiling clock frequency */\n};\n\nextern unsigned int msec();\n#endif  /* !_SYS_TIME_H_ */\n"
  },
  {
    "path": "sys/sys/times.h",
    "content": "/*\n * Copyright (c) 1982, 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *  @(#)times.h 7.1 (Berkeley) 6/4/86\n */\n\n/*\n * Structure returned by times()\n */\nstruct tms {\n    time_t  tms_utime;      /* user time */\n    time_t  tms_stime;      /* system time */\n    time_t  tms_cutime;     /* user time, children */\n    time_t  tms_cstime;     /* system time, children */\n};\n"
  },
  {
    "path": "sys/sys/tty.h",
    "content": "#ifndef _TTY_H\n#define _TTY_H\n/*\n * Copyright (c) 1982, 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#ifdef KERNEL\n#include \"types.h\"\n#include \"ttychars.h\"\n#include \"ttydev.h\"\n#include \"ioctl.h\"\n#else\n#include <sys/types.h>\n#include <sys/ttychars.h>\n#include <sys/ttydev.h>\n#include <sys/ioctl.h>\n#endif\n\n/*\n * A clist structure is the head of a linked list queue\n * of characters.  The characters are stored in blocks\n * containing a link and CBSIZE (param.h) characters.\n * The routines in tty_subr.c manipulate these structures.\n */\nstruct clist {\n    int     c_cc;       /* character count */\n    char    *c_cf;      /* pointer to first char */\n    char    *c_cl;      /* pointer to last char */\n};\n\n/*\n * Per-tty structure.\n *\n * Should be split in two, into device and tty drivers.\n * Glue could be masks of what to echo and circular buffer\n * (low, high, timeout).\n */\nstruct tty {\n    union {\n        struct {\n            struct  clist T_rawq;\n            struct  clist T_canq;\n        } t_t;\n#define t_rawq      t_nu.t_t.T_rawq     /* raw characters or partial line */\n#define t_canq      t_nu.t_t.T_canq     /* raw characters or partial line */\n        struct {\n            struct  buf *T_bufp;\n            char    *T_cp;\n            int     T_inbuf;\n            int     T_rec;\n        } t_n;\n#define t_bufp      t_nu.t_n.T_bufp     /* buffer allocated to protocol */\n#define t_cp        t_nu.t_n.T_cp       /* pointer into the ripped off buffer */\n#define t_inbuf     t_nu.t_n.T_inbuf    /* number chars in the buffer */\n#define t_rec       t_nu.t_n.T_rec      /* have a complete record */\n    } t_nu;\n    struct  clist   t_outq;             /* device */\n    void    (*t_oproc) (struct tty*);\n    struct  proc    *t_rsel;            /* tty */\n    struct  proc    *t_wsel;\n    caddr_t         T_LINEP;            /* ### */\n    caddr_t         t_addr;             /* ??? */\n    dev_t           t_dev;              /* device */\n    long            t_flags;            /* some of both */\n    long            t_state;            /* some of both */\n    int             t_pgrp;             /* tty */\n    int             t_delct;            /* tty */\n    int             t_col;              /* tty */\n    int             t_ispeed, t_ospeed; /* device */\n    int             t_rocount, t_rocol; /* tty */\n    struct  ttychars t_chars;           /* tty */\n    struct  winsize t_winsize;          /* window size */\n/* be careful of tchars & co. */\n#define t_erase     t_chars.tc_erase\n#define t_kill      t_chars.tc_kill\n#define t_intrc     t_chars.tc_intrc\n#define t_quitc     t_chars.tc_quitc\n#define t_startc    t_chars.tc_startc\n#define t_stopc     t_chars.tc_stopc\n#define t_eofc      t_chars.tc_eofc\n#define t_brkc      t_chars.tc_brkc\n#define t_suspc     t_chars.tc_suspc\n#define t_dsuspc    t_chars.tc_dsuspc\n#define t_rprntc    t_chars.tc_rprntc\n#define t_flushc    t_chars.tc_flushc\n#define t_werasc    t_chars.tc_werasc\n#define t_lnextc    t_chars.tc_lnextc\n};\n\n#define TTIPRI      28\n#define TTOPRI      29\n\n/* limits */\n#define NSPEEDS     29\n#define TTMASK      15\n#define OBUFSIZ     100\n\n#ifdef KERNEL\n\nextern const int tthiwat[NSPEEDS], ttlowat[NSPEEDS];\nextern int q_to_b(register struct clist *q, char *cp, int cc);\n\n#define TTHIWAT(tp) tthiwat[(tp)->t_ospeed&TTMASK]\n#define TTLOWAT(tp) ttlowat[(tp)->t_ospeed&TTMASK]\n\nextern int nldisp;      /* number of line disciplines */\n\n/*\n * Set t_chars to default values.\n */\nvoid ttychars (struct tty *tp);\n\n/*\n * Clean terminal on last close.\n */\nvoid ttyclose (struct tty *tp);\n\n/*\n * Wakeup processes waiting on output flow control.\n */\nvoid ttyowake (struct tty *tp);\n\n/*\n * Get a symbol from a character list.\n */\nint getc (struct clist *p);\n\n/*\n * Get the pointer to the next character in the list.\n */\nchar *nextc (struct clist *p, char *cp);\n\n/*\n * Put a symbol to a character list.\n */\nint putc (int c, struct clist *p);\n\n/*\n * Remove the last character in the list and return it.\n */\nint unputc (struct clist *p);\n\n/*\n * Put the chars in the from que on the end of the to que.\n */\nvoid catq (struct clist *from, struct clist *to);\n\n/*\n * Copy buffer to clist.\n */\nint b_to_q (char *cp, int nbytes, struct clist *q);\n\n/*\n * Common code for tty ioctls.\n */\nint ttioctl (struct tty *tp, u_int com, caddr_t data, int flag);\n\n/*\n * Start output on the typewriter.\n */\nvoid ttstart (struct tty *tp);\n\nvoid ttwakeup (struct tty *tp);\n\n/*\n * Place a character on raw TTY input queue,\n */\nvoid ttyinput (int c, struct tty *tp);\n\n/*\n * Put character on TTY output queue.\n */\nint ttyoutput (int c, struct tty *tp);\n\n/*\n * Initial open of tty, or (re)entry to line discipline.\n */\nint ttyopen (dev_t dev, struct tty *tp);\n\n/*\n * Close a line discipline.\n */\nint ttylclose (struct tty *tp, int flag);\n\n/*\n * Check the output queue for space.\n */\nint ttycheckoutq (struct tty *tp, int wait);\n\n/*\n * Called from device's read routine after it has\n * calculated the tty-structure given as argument.\n */\nstruct uio;\nint ttread (struct tty *tp, struct uio *uio, int flag);\nint ttwrite (struct tty *tp, struct uio *uio, int flag);\n\n/*\n * Handle modem control transition on a tty.\n */\nint ttymodem (struct tty *tp, int flag);\n\n/*\n * Check that input or output is possible on a terminal.\n */\nint ttyselect (struct tty *tp, int rw);\n\n/*\n * Flush all TTY queues.\n */\nvoid ttyflush (struct tty *tp, int rw);\n\n/*\n * Wait for output to drain, and flush input.\n */\nvoid ttywflush (struct tty *tp);\n\n#endif /* KERNEL */\n\n/* internal state bits */\n#define TS_TIMEOUT  0x000001L   /* delay timeout in progress */\n#define TS_WOPEN    0x000002L   /* waiting for open to complete */\n#define TS_ISOPEN   0x000004L   /* device is open */\n#define TS_FLUSH    0x000008L   /* outq has been flushed during DMA */\n#define TS_CARR_ON  0x000010L   /* software copy of carrier-present */\n#define TS_BUSY     0x000020L   /* output in progress */\n#define TS_ASLEEP   0x000040L   /* wakeup when output done */\n#define TS_XCLUDE   0x000080L   /* exclusive-use flag against open */\n#define TS_TTSTOP   0x000100L   /* output stopped by ctl-s */\n#define TS_HUPCLS   0x000200L   /* hang up upon last close */\n#define TS_TBLOCK   0x000400L   /* tandem queue blocked */\n#define TS_RCOLL    0x000800L   /* collision in read select */\n#define TS_WCOLL    0x001000L   /* collision in write select */\n#define TS_ASYNC    0x004000L   /* tty in async i/o mode */\n/* state for intra-line fancy editing work */\n#define TS_ERASE    0x040000L   /* within a \\.../ for PRTRUB */\n#define TS_LNCH     0x080000L   /* next character is literal */\n#define TS_TYPEN    0x100000L   /* retyping suspended input (PENDIN) */\n#define TS_CNTTB    0x200000L   /* counting tab width; leave FLUSHO alone */\n\n#define TS_LOCAL    (TS_ERASE|TS_LNCH|TS_TYPEN|TS_CNTTB)\n\n/* define partab character types */\n#define ORDINARY    0\n#define CONTROL     1\n#define BACKSPACE   2\n#define NEWLINE     3\n#define TAB         4\n#define VTAB        5\n#define RETURN      6\n#endif\n"
  },
  {
    "path": "sys/sys/ttychars.h",
    "content": "/*\n * Copyright (c) 1982, 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *  @(#)ttychars.h  7.2 (2.11BSD) 1997/4/15\n */\n\n/*\n * User visible structures and constants\n * related to terminal handling.\n */\n#ifndef _TTYCHARS_\n#define _TTYCHARS_\nstruct ttychars {\n    char    tc_erase;   /* erase last character */\n    char    tc_kill;    /* erase entire line */\n    char    tc_intrc;   /* interrupt */\n    char    tc_quitc;   /* quit */\n    char    tc_startc;  /* start output */\n    char    tc_stopc;   /* stop output */\n    char    tc_eofc;    /* end-of-file */\n    char    tc_brkc;    /* input delimiter (like nl) */\n    char    tc_suspc;   /* stop process signal */\n    char    tc_dsuspc;  /* delayed stop process signal */\n    char    tc_rprntc;  /* reprint line */\n    char    tc_flushc;  /* flush output (toggles) */\n    char    tc_werasc;  /* word erase */\n    char    tc_lnextc;  /* literal next character */\n};\n\n#define CTRL(c)         (c & 037)\n#define _POSIX_VDISABLE ((unsigned char)'\\377')\n#define CCEQ(val,c)     (c == val ? val != _POSIX_VDISABLE : 0)\n\n/* default special characters */\n#define CERASE  0177\n#define CKILL   CTRL('u')\n#define CINTR   CTRL('c')\n#define CQUIT   CTRL('\\\\')\n#define CSTART  CTRL('q')\n#define CSTOP   CTRL('s')\n#define CEOF    CTRL('d')\n#define CEOT    CEOF\n#define CBRK    _POSIX_VDISABLE\n#define CSUSP   CTRL('z')\n#define CDSUSP  CTRL('y')\n#define CRPRNT  CTRL('r')\n#define CFLUSH  CTRL('o')\n#define CWERASE CTRL('w')\n#define CLNEXT  CTRL('v')\n#endif /* _TTYCHARS_ */\n"
  },
  {
    "path": "sys/sys/ttydev.h",
    "content": "/*\n * Copyright (c) 1982, 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *  @(#)ttydev.h    7.1 (Berkeley) 6/4/86\n */\n\n/*\n * Terminal definitions related to underlying hardware.\n */\n#ifndef _TTYDEV_\n#define _TTYDEV_\n\n/*\n * Speeds\n */\n#define B0          0\n#define B50         1\n#define B75         2\n#define B150        3\n#define B200        4\n#define B300        5\n#define B600        6\n#define B1200       7\n#define B1800       8\n#define B2400       9\n#define B4800       10\n#define B9600       11\n#define B19200      12\n#define B38400      13\n#define B57600      14\n#define B115200     15\n#define B230400     16\n#define B460800     17\n#define B500000     18\n#define B576000     19\n#define B921600     20\n#define B1000000    21\n#define B1152000    22\n#define B1500000    23\n#define B2000000    24\n#define B2500000    25\n#define B3000000    26\n#define B3500000    27\n#define B4000000    28\n\n#ifdef KERNEL\n/*\n * Modem control commands.\n */\n#define DMSET       0\n#define DMBIS       1\n#define DMBIC       2\n#define DMGET       3\n#endif\n#endif\n"
  },
  {
    "path": "sys/sys/types.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n#ifndef _SYS_TYPES_H_\n#define _SYS_TYPES_H_\n\n#include <machine/types.h>\n\n/*\n * Basic system types and major/minor device constructing/busting macros.\n */\n\n/* major part of a device */\n#define major(x)        ((int)(((int)(x)>>8)&0377))\n\n/* minor part of a device */\n#define minor(x)        ((int)((x)&0377))\n\n/* make a device number */\n#define makedev(x,y)    ((dev_t)(((x)<<8) | (y)))\n\ntypedef unsigned char   u_char;\ntypedef unsigned short  u_short;\ntypedef unsigned int    u_int;\ntypedef unsigned long   u_long;     /* see this! unsigned longs at last! */\ntypedef unsigned short  ushort;     /* sys III compat */\n\n#ifdef pdp11\ntypedef struct  label_t {\n    int     val[7];                 /* regs 2-7 and super SP */\n} label_t;\n#endif\n\ntypedef long    daddr_t;\ntypedef char *  caddr_t;\ntypedef u_int   ino_t;\n#ifndef _SIZE_T\n#define _SIZE_T\ntypedef u_int   size_t;\n#endif\n#ifndef __ssize_t_defined\n#ifndef _SSIZE_T\ntypedef int     ssize_t;\n#define __ssize_t_defined\n#define _SSIZE_T\n#endif\n#endif\n#ifndef _TIME_T\n#define _TIME_T\ntypedef long    time_t;\n#endif\ntypedef int     dev_t;\n#ifndef _OFF_T\n#define _OFF_T\ntypedef long    off_t;\n#endif\ntypedef u_int   uid_t;\ntypedef u_int   gid_t;\ntypedef int     pid_t;\ntypedef u_int   mode_t;\ntypedef int     bool_t;             /* boolean */\n#define _PID_T\n#define _UID_T\n#define _GID_T\n#define _INO_T\n#define _DEV_T\n#define _TIME_T\n#define _MODE_T\n\n#define NBBY            8           /* number of bits in a byte */\n\n#ifndef howmany\n#define howmany(x, y)   (((x)+((y)-1))/(y))\n#endif\n\n#include <sys/select.h>\n\n#ifdef KERNEL\n/*\n * Save the process' current register context.\n */\nint setjmp (label_t *env);\n\n/*\n * Map in a user structure and jump to a saved context.\n */\nvoid longjmp (size_t unew, label_t *env);\n\n#endif /* KERNEL */\n\n#endif\n"
  },
  {
    "path": "sys/sys/uio.h",
    "content": "/*\n * Copyright (c) 1982, 1986, 1993, 1994\n *  The Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *  This product includes software developed by the University of\n *  California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n * Copied from 4.4-Lite and modified for 2.11BSD.  Modifications were removal\n * of prototypes, limits for dynamic allocation of iovec structs and changing\n * uio_resid to u_int from int.\n */\n\n#ifndef _SYS_UIO_H_\n#define _SYS_UIO_H_\n\n#include \"types.h\"\n\n/*\n * XXX\n * iov_base should be a void *.\n */\nstruct iovec {\n    char    *iov_base;  /* Base address. */\n    size_t   iov_len;   /* Length. */\n};\n\nenum    uio_rw { UIO_READ, UIO_WRITE };\n\nstruct uio {\n    struct  iovec *uio_iov;\n    int     uio_iovcnt;\n    off_t   uio_offset;\n    u_int   uio_resid;\n    enum    uio_rw uio_rw;\n};\n\n#ifdef KERNEL\n/*\n * Move data to/from user space.\n */\nint uiomove (caddr_t cp, u_int n, struct uio *uio);\n\n/*\n * Give next character to user as result of read.\n */\nint ureadc (int c, struct uio *uio);\n\n#else /* !KERNEL */\n\nssize_t readv (int fd, const struct iovec *iov, int iovcnt);\n\nssize_t writev (int fd, const struct iovec *iov, int iovcnt);\n\n#endif /* KERNEL */\n#endif /* !_SYS_UIO_H_ */\n"
  },
  {
    "path": "sys/sys/user.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#ifdef KERNEL\n#include \"dir.h\"\n#include \"exec.h\"\n#include \"time.h\"\n#include \"resource.h\"\n#else\n#include <sys/dir.h>\n#include <sys/exec.h>\n#include <sys/time.h>\n#include <sys/resource.h>\n#endif\n\n/*\n * data that doesn't need to be referenced while the process is swapped.\n * For PIC32, the user block is USIZE bytes long; resides at virtual kernel loc\n * 0x80007400; contains the system stack (and possibly network stack) per\n * user; is cross referenced with the proc structure for the same process.\n */\n#define MAXCOMLEN   MAXNAMLEN   /* <= MAXNAMLEN, >= sizeof(ac_comm) */\n\nstruct user {\n    struct  proc *u_procp;          /* pointer to proc structure */\n    struct  trapframe *u_frame;     /* address of users saved frame */\n    char    u_comm[MAXCOMLEN + 1];  /* command file name */\n    label_t u_qsave;                /* for non-local gotos on interrupts */\n    label_t u_rsave;                /* save info when exchanging stacks */\n    label_t u_ssave;                /* label variable for swapping */\n\n/* syscall parameters and results */\n    int     u_arg[6];               /* arguments to current system call */\n    int     u_rval;                 /* return value */\n    int     u_error;                /* return error code */\n\n/* 1.1 - processes and protection */\n    uid_t   u_uid;                  /* effective user id */\n    uid_t   u_svuid;                /* saved user id */\n    uid_t   u_ruid;                 /* real user id */\n    gid_t   u_svgid;                /* saved group id */\n    gid_t   u_rgid;                 /* real group id */\n    gid_t   u_groups[NGROUPS];      /* groups, 0 terminated */\n\n/* 1.2 - memory management */\n    size_t  u_tsize;                /* text size (clicks) */\n    size_t  u_dsize;                /* data size (clicks) */\n    size_t  u_ssize;                /* stack size (clicks) */\n\n/* 1.3 - signal management */\n    sig_t   u_signal[NSIG];         /* disposition of signals */\n    long    u_sigmask[NSIG];        /* signals to be blocked */\n    long    u_sigonstack;           /* signals to take on sigstack */\n    long    u_sigintr;              /* signals that interrupt syscalls */\n    long    u_oldmask;              /* saved mask from before sigpause */\n    int     u_code;                 /* ``code'' to trap */\n    int     u_psflags;              /* Process Signal flags */\n    struct  sigaltstack u_sigstk;   /* signal stack info */\n    u_int   u_sigtramp;             /* pointer to trampoline code in user space */\n\n/* 1.4 - descriptor management */\n    struct  file *u_ofile[NOFILE];  /* file structures for open files */\n    char    u_pofile[NOFILE];       /* per-process flags of open files */\n    int u_lastfile;                 /* high-water mark of u_ofile */\n#define UF_EXCLOSE  0x1             /* auto-close on exec */\n#define UF_MAPPED   0x2             /* mapped from device */\n    struct  inode *u_cdir;          /* current directory */\n    struct  inode *u_rdir;          /* root directory of current process */\n    struct  tty *u_ttyp;            /* controlling tty pointer */\n    dev_t   u_ttyd;                 /* controlling tty dev */\n    int     u_cmask;                /* mask for file creation */\n\n/* 1.5 - timing and statistics */\n    struct  k_rusage u_ru;          /* stats for this proc */\n    struct  k_rusage u_cru;         /* sum of stats for reaped children */\n    struct  k_itimerval u_timer[2]; /* profile/virtual timers */\n    long    u_start;\n    int     u_dupfd;                /* XXX - see kern_descrip.c/fdopen */\n\n    struct uprof {                  /* profile arguments */\n        unsigned *pr_base;          /* buffer base */\n        unsigned pr_size;           /* buffer size */\n        unsigned pr_off;            /* pc offset */\n        unsigned pr_scale;          /* pc scaling */\n    } u_prof;\n\n/* 1.6 - resource controls */\n    struct  rlimit u_rlimit[RLIM_NLIMITS];\n\n/* namei & co. */\n    struct  nameicache {            /* last successful directory search */\n        off_t nc_prevoffset;        /* offset at which last entry found */\n        ino_t nc_inumber;           /* inum of cached directory */\n        dev_t nc_dev;               /* dev of cached directory */\n    } u_ncache;\n    int     u_stack[1];             /* kernel stack per user\n                                     * extends from u + USIZE\n                                     * backward not to reach here */\n};\n\n#include <sys/errno.h>\n\n#ifdef KERNEL\nextern  struct user u, u0;\n\n/*\n * Increment user profiling counters.\n */\nvoid addupc (caddr_t pc, struct uprof *pbuf, int ticks);\n\n#endif\n"
  },
  {
    "path": "sys/sys/utsname.h",
    "content": "/*-\n * Copyright (c) 1994\n *  The Regents of the University of California.  All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Chuck Karish of Mindcraft, Inc.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *  This product includes software developed by the University of\n *  California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#ifndef _SYS_UTSNAME_H\n#define _SYS_UTSNAME_H\n\n#define SYS_NMLN\t256\n\nstruct utsname {\n\tchar\tsysname[SYS_NMLN];\t/* Name of this OS. */\n\tchar\tnodename[SYS_NMLN];\t/* Name of this network node. */\n\tchar\trelease[SYS_NMLN];\t/* Release level. */\n\tchar\tversion[SYS_NMLN];\t/* Version level. */\n\tchar\tmachine[SYS_NMLN];\t/* Hardware type. */\n};\n\nint\tuname(struct utsname *name);\n\n#endif  /* !_SYS_UTSNAME_H */\n"
  },
  {
    "path": "sys/sys/vm.h",
    "content": "/*\n * Copyright (c) 1982, 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n#ifdef KERNEL\n#include \"vmparam.h\"\n#include \"vmmac.h\"\n#include \"vmmeter.h\"\n#include \"vmsystm.h\"\n#else\n#include <sys/vmparam.h>\n#include <sys/vmmac.h>\n#include <sys/vmmeter.h>\n#include <sys/vmsystm.h>\n#endif\n"
  },
  {
    "path": "sys/sys/vmmac.h",
    "content": "/*\n * Copyright (c) 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *  @(#)vmmac.h 1.1 (2.10 Berkeley) 12/1/86\n */\n\n/* Average new into old with aging factor time */\n#define ave(smooth, cnt, time) \\\n    smooth = ((time - 1) * (smooth) + (cnt)) / (time)\n"
  },
  {
    "path": "sys/sys/vmmeter.h",
    "content": "/*\n * Copyright (c) 1982, 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * Virtual memory related instrumentation\n */\nstruct vmrate\n{\n#define v_first v_swtch\n    u_short     v_swtch;    /* context switches */\n    u_short     v_trap;     /* calls to trap */\n    u_short     v_syscall;  /* calls to syscall() */\n    u_short     v_intr;     /* device interrupts */\n    u_short     v_soft;     /* software interrupts */\n    u_short     v_fpsim;    /* floating point simulator faults */\n    u_short     v_kbin;     /* kbytes swapped in */\n    u_short     v_kbout;    /* kbytes swapped out */\n    u_short     v_swpin;    /* swapins */\n    u_short     v_swpout;   /* swapouts */\n#define v_last  v_swpout\n};\n\nstruct vmsum\n{\n    long        v_swtch;    /* context switches */\n    long        v_trap;     /* calls to trap */\n    long        v_syscall;  /* calls to syscall() */\n    long        v_intr;     /* device interrupts */\n    long        v_soft;     /* software interrupts */\n    long        v_fpsim;    /* floating point simulator faults */\n    long        v_kbin;     /* kbytes swapped in */\n    long        v_kbout;    /* kbytes swapped out */\n    long        v_swpin;    /* swapins */\n    long        v_swpout;   /* swapouts */\n};\n#if defined(KERNEL) && defined(UCB_METER)\nstruct vmrate   cnt, rate;\nstruct vmsum    sum;\n#endif\n\n/* systemwide totals computed every five seconds */\nstruct vmtotal\n{\n    short       t_rq;       /* length of the run queue */\n    short       t_dw;       /* jobs in ``disk wait'' (neg priority) */\n    short       t_sl;       /* jobs sleeping in core */\n    short       t_sw;       /* swapped out runnable/short block jobs */\n    long        t_vm;       /* total virtual memory, clicks */\n    long        t_avm;      /* active virtual memory, clicks */\n    size_t      t_rm;       /* total real memory, clicks */\n    size_t      t_arm;      /* active real memory, clicks */\n    long        t_vmtxt;    /* virtual memory used by text, clicks */\n    long        t_avmtxt;   /* active virtual memory used by text, clicks */\n    size_t      t_rmtxt;    /* real memory used by text, clicks */\n    size_t      t_armtxt;   /* active real memory used by text, clicks */\n    size_t      t_free;     /* free memory, kb */\n};\n#ifdef KERNEL\nstruct  vmtotal total;\n\n/*\n * Count up various things once a second\n */\nvoid vmmeter (void);\n\nvoid vmtotal (void);\n\n#endif\n"
  },
  {
    "path": "sys/sys/vmparam.h",
    "content": "/*\n * Copyright (c) 1982, 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n */\n\n/*\n * CTL_VM identifiers\n */\n#define VM_METER    1       /* struct vmmeter */\n#define VM_LOADAVG  2       /* struct loadavg */\n#define VM_SWAPMAP  3       /* struct mapent _swapmap[] */\n#define VM_MAXID    5       /* number of valid vm ids */\n\n#ifndef KERNEL\n#define CTL_VM_NAMES { \\\n    { 0, 0 }, \\\n    { \"vmmeter\", CTLTYPE_STRUCT }, \\\n    { \"loadavg\", CTLTYPE_STRUCT }, \\\n    { \"swapmap\", CTLTYPE_STRUCT }, \\\n}\n#endif\n"
  },
  {
    "path": "sys/sys/vmsystm.h",
    "content": "/*\n * Miscellaneous virtual memory subsystem variables and structures.\n *\n * Copyright (c) 1982, 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *  @(#)vmsystm.h   7.2.1 (2.11BSD GTE) 1/15/95\n */\n\n/*\n * Fork/vfork accounting.\n */\nstruct  forkstat\n{\n    long    cntfork;\n    long    cntvfork;\n    long    sizfork;\n    long    sizvfork;\n};\n\n#if defined(KERNEL) && defined(UCB_METER)\nsize_t  freemem;        /* remaining clicks of free memory */\n\nu_short avefree;        /* moving average of remaining free clicks */\nu_short avefree30;      /* 30 sec (avefree is 5 sec) moving average */\n\n/*\n * writable copies of tunables\n */\nint     maxslp;         /* max sleep time before very swappable */\n\nstruct  forkstat forkstat;\n#endif\n"
  },
  {
    "path": "sys/sys/wait.h",
    "content": "/*\n * Copyright (c) 1982, 1986 Regents of the University of California.\n * All rights reserved.  The Berkeley software License Agreement\n * specifies the terms and conditions for redistribution.\n *\n *  @(#)wait.h  7.2.1 (2.11BSD GTE) 1995/06/23\n */\n\n/*\n * This file holds definitions relevent to the wait system call.\n * Some of the options here are available only through the ``wait3''\n * entry point; the old entry point with one argument has more fixed\n * semantics, never returning status of unstopped children, hanging until\n * a process terminates if any are outstanding, and never returns\n * detailed information about process resource utilization (<vtimes.h>).\n */\n\n/*\n * Structure of the information in the first word returned by both\n * wait and wait3.  If w_stopval==WSTOPPED, then the second structure\n * describes the information returned, else the first.  See WUNTRACED below.\n */\nunion wait  {\n    int     w_status;           /* used in syscall */\n    /*\n     * Terminated process status.\n     */\n    struct {\n        unsigned w_Termsig :7;  /* termination signal */\n        unsigned w_Coredump :1; /* core dump indicator */\n        unsigned w_Retcode :8;  /* exit code if w_termsig==0 */\n    } w_T;\n    /*\n     * Stopped process status.  Returned\n     * only for traced children unless requested\n     * with the WUNTRACED option bit.\n     */\n    struct {\n        unsigned w_Stopval :8;  /* == W_STOPPED if stopped */\n        unsigned w_Stopsig :8;  /* signal that stopped us */\n    } w_S;\n};\n#define w_termsig   w_T.w_Termsig\n#define w_coredump  w_T.w_Coredump\n#define w_retcode   w_T.w_Retcode\n#define w_stopval   w_S.w_Stopval\n#define w_stopsig   w_S.w_Stopsig\n\n#define WSTOPPED    0177        /* value of s.stopval if process is stopped */\n\n/*\n * Option bits for the second argument of wait3.  WNOHANG causes the\n * wait to not hang if there are no stopped or terminated processes, rather\n * returning an error indication in this case (pid==0).  WUNTRACED\n * indicates that the caller should receive status about untraced children\n * which stop due to signals.  If children are stopped and a wait without\n * this option is done, it is as though they were still running... nothing\n * about them is returned.\n */\n#define WNOHANG     1           /* dont hang in wait */\n#define WUNTRACED   2           /* tell about stopped, untraced children */\n\n#define WIFSTOPPED(x)   (((union wait*)&(x))->w_stopval == WSTOPPED)\n#define WIFSIGNALED(x)  (((union wait*)&(x))->w_stopval != WSTOPPED &&\\\n                        (((union wait*)&(x))->w_termsig != 0))\n#define WIFEXITED(x)    (((union wait*)&(x))->w_stopval != WSTOPPED &&\\\n                        (((union wait*)&(x))->w_termsig == 0))\n#define WEXITSTATUS(x)  (((union wait*)&(x))->w_retcode)\n#define WTERMSIG(x)     (((union wait*)&(x))->w_termsig)\n#define WCOREDUMP(x)    (((union wait*)&(x))->w_coredump)\n#define WSTOPSIG(x)     (((union wait*)&(x))->w_stopsig)\n\n#define W_STOPCODE(sig)     ((sig << 8) | WSTOPPED)\n#define W_EXITCODE(ret,sig) ((ret << 8) | (sig))\n\n#define WAIT_ANY    (-1)\n#define WAIT_MYPGRP 0\n\n#ifndef KERNEL\n#include <sys/time.h>\n#include <sys/resource.h>\n\nint wait (int *istat);\nint wait3 (int *istat, int options, struct rusage *rup);\nint waitpid (int pid, int *istat, int options);\nint wait4 (int pid, int *istat, int options, struct rusage *rup);\n#endif\n"
  },
  {
    "path": "tools/Makefile",
    "content": "SUBDIR!=if [ x\"${MACHINE}\" = x\"pic32\" ] ; then \\\n\t\techo \"binstall aoututils elf2aout fsutil config icache mkrd virtualmips\" ; \\\n\telse \\\n\t\techo \"binstall aoututils elf2aout fsutil config\" ; \\\n\tfi\n\nall install depend: ${SUBDIR}\n\t\t-for i in ${SUBDIR}; do ${MAKE} -C $$i ${MFLAGS} $@; done\n\nclean:\n\t\trm -f *~ bin/*\n\t\tfor i in ${SUBDIR}; do ${MAKE} -C $$i ${MFLAGS} clean; done\n"
  },
  {
    "path": "tools/Makefile.inc",
    "content": "# Common defines and tools to support cross-hosting platforms.\n\n_HOST_OSNAME!=\tuname -s\n\nTOOLDIR?=\t${TOPSRC}/tools\nTOOLBINDIR?=\t${TOOLDIR}/bin\n\nHOST_CC?=\tcc\n\nCC=\t\t${HOST_CC}\n\n# libbsd-dev package on Linux in overlay mode.\n_LIBBSD_CFLAGS!=if [ x\"${_HOST_OSNAME}\" = x\"Linux\" ] ; then \\\n\t\t\tpkg-config libbsd-overlay --cflags ; \\\n\t\telse \\\n\t\t\techo \"\" ; \\\n\t\tfi\n\n_LIBBSD_LIBS!=\tif [ x\"${_HOST_OSNAME}\" = x\"Linux\" ] ; then \\\n\t\t\tpkg-config libbsd-overlay --libs ; \\\n\t\telse \\\n\t\t\techo \"\" ; \\\n\t\tfi\n\nINSTALL=\t${TOOLBINDIR}/binstall -U\n\nYACC!=\t\tif [ x\"${_HOST_OSNAME}\" = x\"Linux\" ] ; then \\\n\t\t\techo \"byacc\" ; \\\n\t\telse \\\n\t\t\techo \"yacc\" ; \\\n\t\tfi\n\nYFLAGS=\t\t-d\n\n#MANROFF=\tnroff -man -h -Tascii\nMANROFF=\tmandoc -Tascii\n"
  },
  {
    "path": "tools/aoututils/Makefile",
    "content": "#\n# aoututils - utilities for building and maintaining a.out executables\n#\n# Must be kept in sync with utilities in usr.bin\n#\n\nSUBDIR=\taout ar as ld nm ranlib size strip\n\nall install clean:\n\tfor i in ${SUBDIR}; do ${MAKE} -C $$i ${MFLAGS} $@; done\n"
  },
  {
    "path": "tools/aoututils/Makefile.inc",
    "content": "TOPSRC!=cd ../../..; pwd\n\n-include ${TOPSRC}/tools/Makefile.inc\n\nCFLAGS=\t-Os -Wall -std=gnu89 -fno-builtin -DCROSS \\\n\t-I. -I../include \\\n\t-idirafter ${TOPSRC}/include \\\n\t-idirafter ../ar\n\n# libbsd-dev package on Linux in overlay mode.\nCFLAGS+=${_LIBBSD_CFLAGS}\nLIBS+=\t${_LIBBSD_LIBS}\n\nall:\t${PROG}\n\n${PROG}: ${OBJS}\n\t${CC} ${CFLAGS} ${LDFLAGS} -o $@ ${OBJS} ${LIBS}\n\ninstall: all\n\t${INSTALL} ${PROG} ${TOOLBINDIR}/${PROG}\n\nclean:\n\trm -f *.o ${PROG} *~\n\n.PHONY:\tall install clean\n"
  },
  {
    "path": "tools/aoututils/include/a.out.h",
    "content": "/*-\n * Copyright (c) 1991 The Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *      This product includes software developed by the University of\n *      California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#ifndef _AOUT_H_\n#define _AOUT_H_\n\n#include <sys/exec_aout.h>\n\n#define _AOUT_INCLUDE_\n#include <nlist.h>\n\n/* Relocations */\nstruct reloc {\n    unsigned flags;\n#define RSMASK  0x70            /* bitmask for segments */\n#define RABS        0\n#define RTEXT       0x20\n#define RDATA       0x30\n#define RBSS        0x40\n#define RSTRNG      0x60        /* for assembler */\n#define REXT        0x70        /* externals and bitmask */\n\n#define RGPREL  0x08            /* gp relative */\n\n#define RFMASK  0x07            /* bitmask for format */\n#define RBYTE16     0x00        /* low part of byte address: bits 15:0 */\n#define RBYTE32     0x01        /* 32-bit byte address */\n#define RHIGH16     0x02        /* upper part of byte address: bits 31:16 */\n#define RHIGH16S    0x03        /* upper part of address with signed offset */\n#define RWORD16     0x04        /* word address: bits 17:2 */\n#define RWORD26     0x05        /* word address: bits 27:2 */\n\n    unsigned index;             /* 24-bit index in symbol table,\n                                 * for REXT */\n    unsigned offset;            /* 16-bit offset,\n                                 * for RIGH16 and RIGH16S */\n};\n\n#endif /* !_AOUT_H_ */\n"
  },
  {
    "path": "tools/aoututils/include/ar.h",
    "content": "/*-\n * Copyright (c) 1991 The Regents of the University of California.\n * All rights reserved.\n *\n * This code is derived from software contributed to Berkeley by\n * Hugh Smith at The University of Guelph.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *  This product includes software developed by the University of\n *  California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n#ifndef _AR_H_\n#define _AR_H_\n\n#define ARMAG       \"!<arch>\\n\" /* ar \"magic number\" */\n#define SARMAG      8           /* strlen(ARMAG); */\n\n#define AR_EFMT1    \"#1/\"       /* extended format #1 */\n\nstruct ar_hdr {\n    char ar_name[16];           /* name */\n    char ar_date[12];           /* modification time */\n    char ar_uid[6];             /* user id */\n    char ar_gid[6];             /* group id */\n    char ar_mode[8];            /* octal file permissions */\n    char ar_size[10];           /* size in bytes */\n#define ARFMAG      \"`\\n\"\n    char ar_fmag[2];            /* consistency check */\n};\n\n#define ARHDRSZ     60\n\n#endif /* !_AR_H_ */\n"
  },
  {
    "path": "tools/aoututils/include/nlist.h",
    "content": "/*-\n * Copyright (c) 1991 The Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *  This product includes software developed by the University of\n *  California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n#ifndef _NLIST_H_\n#define _NLIST_H_\n#include <sys/types.h>\n\n/*\n * Symbol table entry format.\n */\nstruct  nlist {\n    char    *n_name;        /* In memory address of symbol name,\n                             * or string table offset (file) */\n    u_short n_len;          /* Length of name in bytes */\n    u_short n_type;         /* Type of symbol - see below */\n    u_int   n_value;        /* Symbol value */\n};\n\n/*\n * Simple values for n_type.\n */\n#define N_UNDF  0x00        /* undefined */\n#define N_ABS   0x01        /* absolute */\n#define N_TEXT  0x02        /* text segment */\n#define N_DATA  0x03        /* data segment */\n#define N_BSS   0x04        /* bss segment */\n#define N_STRNG 0x05        /* string segment (for assembler) */\n#define N_COMM  0x06        /* .comm segment (for assembler) */\n#define N_FN    0x1f        /* file name */\n\n#define N_TYPE  0x1f        /* mask for all the type bits */\n#define N_EXT   0x20        /* external (global) bit, OR'ed in */\n#define N_WEAK  0x40        /* weak reference bit, OR'ed in */\n#define N_LOC   0x80        /* local, for assembler */\n\n/*\n * Get symbols from a file.\n */\nint nlist (char *name, struct nlist *list);\n\n/*\n * Get kernel symbols.\n */\nint knlist (struct nlist *list);\n\n#endif  /* !_NLIST_H_ */\n"
  },
  {
    "path": "tools/aoututils/include/ranlib.h",
    "content": "/*-\n * Copyright (c) 1990 The Regents of the University of California.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *  This product includes software developed by the University of\n *  California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n#ifndef _RANLIB_H_\n#define _RANLIB_H_\n\n#define RANLIBMAG   \"__.SYMDEF\" /* archive file name */\n#define RANLIBSKEW  3           /* creation time offset */\n\nstruct ranlib {\n    int     ran_len;            /* 1 byte - name length in bytes */\n    unsigned ran_off;           /* 4 bytes - file offset */\n    char    *ran_name;          /* in memory symbol name */\n};\n\n#endif /* !_RANLIB_H_ */\n"
  },
  {
    "path": "tools/binstall/.gitignore",
    "content": "xinstall\n"
  },
  {
    "path": "tools/binstall/Makefile",
    "content": "TOPSRC!=cd ../..; pwd\n\n-include ../Makefile.inc\n\nPROG=\txinstall\nOBJS=\txinstall.o\n\n# Use uninstalled copy of the install program.\nINSTALL=./xinstall\n\n# libbsd-dev package on Linux in overlay mode.\nCFLAGS+=${_LIBBSD_CFLAGS}\nLIBS+=\t${_LIBBSD_LIBS}\n\nall:\t${PROG}\n\n${PROG}: ${OBJS}\n\t${CC} ${LDFLAGS} -o $@ ${OBJS} ${LIBS}\n\ninstall: all\n\t${INSTALL} ${PROG} ${TOOLBINDIR}/binstall\n\nclean:\n\trm -f *~ *.o ${PROG}\n\n.PHONY: all install clean\n"
  },
  {
    "path": "tools/binstall/install.1",
    "content": ".\\\"\t$OpenBSD: install.1,v 1.31 2019/02/08 12:53:44 schwarze Exp $\n.\\\"\t$NetBSD: install.1,v 1.4 1994/11/14 04:57:17 jtc Exp $\n.\\\"\n.\\\" Copyright (c) 1987, 1990, 1993\n.\\\"\tThe Regents of the University of California.  All rights reserved.\n.\\\"\n.\\\" Redistribution and use in source and binary forms, with or without\n.\\\" modification, are permitted provided that the following conditions\n.\\\" are met:\n.\\\" 1. Redistributions of source code must retain the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer.\n.\\\" 2. Redistributions in binary form must reproduce the above copyright\n.\\\"    notice, this list of conditions and the following disclaimer in the\n.\\\"    documentation and/or other materials provided with the distribution.\n.\\\" 3. Neither the name of the University nor the names of its contributors\n.\\\"    may be used to endorse or promote products derived from this software\n.\\\"    without specific prior written permission.\n.\\\"\n.\\\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n.\\\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n.\\\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n.\\\" ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n.\\\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n.\\\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n.\\\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n.\\\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n.\\\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n.\\\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n.\\\" SUCH DAMAGE.\n.\\\"\n.\\\"     @(#)install.1\t8.1 (Berkeley) 6/6/93\n.\\\"\n.Dd $Mdocdate: February 10 2024 $\n.Dt INSTALL 1\n.Os\n.Sh NAME\n.Nm install\n.Nd install binaries\n.Sh SYNOPSIS\n.Nm install\n.Op Fl bCcDdFpSsU\n.Op Fl B Ar suffix\n.Op Fl f Ar flags\n.Op Fl g Ar group\n.Op Fl m Ar mode\n.Op Fl o Ar owner\n.Ar source ... target ...\n.Sh DESCRIPTION\nThe\n.Ar source\nfile(s) are copied to the\n.Ar target\nfile or directory.\nIf the\n.Ar target\nfile already exists, it is either renamed to\n.Ar file.old\nif the\n.Fl b\noption is given\nor overwritten\nif permissions allow.\nAn alternate backup suffix may be specified via the\n.Fl B\noption's argument.\nIf the\n.Fl d\noption is given,\n.Ar target\ndirectories are created, and no files are copied.\n.Pp\nThe options are as follows:\n.Bl -tag -width \"-B suffix\"\n.It Fl B Ar suffix\nUse\n.Ar suffix\nas the backup suffix if\n.Fl b\nis given.\n.It Fl b\nBackup any existing files before overwriting them by renaming\nthem to\n.Ar file.old .\nSee\n.Fl B\nfor specifying a different backup suffix.\n.It Fl C\nCopy the file.\nIf the target file already exists and the files are the same,\nthen don't change the modification time of the target.\n.It Fl c\nCopy the file.\nThis is actually the default.\nThe\n.Fl c\noption is only included for backwards compatibility.\n.It Fl D\nCreate all leading components of the target before installing into it.\n.It Fl d\nCreate directories.\nMissing parent directories are created as required.\nThis option cannot be used with the\n.Fl B , b , C , c ,\n.Fl f , p ,\nor\n.Fl s\noptions.\n.It Fl F\nFlush the file's contents to disk.\nWhen copying a file, use the\n.Xr fsync 2\nfunction to synchronize the installed file's contents with the\non-disk version.\n.It Fl f Ar flags\nSpecify the target's file\n.Ar flags .\n(See\n.Xr chflags 1\nfor a list of possible flags and their meanings.)\n.It Fl g Ar group\nSpecify a\n.Ar group .\nA numeric GID is allowed.\n.It Fl m Ar mode\nSpecify an alternate\n.Ar mode .\nThe default mode is set to rwxr-xr-x (0755).\nThe specified mode may be either an octal or symbolic value; see\n.Xr chmod 1\nfor a description of possible mode values.\n.It Fl o Ar owner\nSpecify an\n.Ar owner .\nA numeric UID is allowed.\n.It Fl p\nPreserve the modification time.\nCopy the file, as if the\n.Fl C\n(compare and copy) option is specified,\nexcept if the target file doesn't already exist or is different,\nthen preserve the modification time of the file.\n.It Fl S\nSafe copy.\nThis option has no effect and is supported only for compatibility.\nWhen installing a file, a temporary file is created and written first\nin the destination directory, then atomically renamed.\nThis avoids both race conditions and the destruction of existing\nfiles in case of write failures.\n.It Fl s\n.Nm\nexec's the command\n.Pa /usr/bin/strip\nto strip binaries so that install can be portable over a large\nnumber of systems and binary types.\nIf the environment variable\n.Ev STRIP\nis set, it is used instead.\n.It Fl U\nUnprivileged mode.\nDo not attempt to modify the default\n.Ar owner ,\n.Ar group ,\nand file\n.Ar flags\nof the target.\n.El\n.Pp\nBy default,\n.Nm\npreserves all file flags, with the exception of the\n.Dq nodump\nflag.\n.Pp\nThe\n.Nm\nutility attempts to prevent moving a file onto itself.\n.Pp\nInstalling\n.Pa /dev/null\ncreates an empty file.\n.Sh ENVIRONMENT\n.Bl -tag -width \"STRIP\"\n.It Ev STRIP\nFor an alternate\n.Xr strip 1\nprogram to run.\nDefault is\n.Pa /usr/bin/strip .\n.El\n.Sh FILES\n.Bl -tag -width INS@XXXXXXXXXX -compact\n.It Pa INS@XXXXXXXXXX\nTemporary files created in the target directory by\n.Xr mkstemp 3 .\n.El\n.Sh EXIT STATUS\n.Ex -std install\n.Sh SEE ALSO\n.Xr chflags 1 ,\n.Xr chgrp 1 ,\n.Xr chmod 1 ,\n.Xr cp 1 ,\n.Xr mv 1 ,\n.Xr strip 1 ,\n.Xr chown 8\n.Sh HISTORY\nThe\n.Nm\nutility appeared in\n.Bx 4.2 .\n.Sh CAVEATS\nThe\n.Fl C ,\n.Fl D ,\n.Fl F ,\n.Fl p ,\n.Fl S ,\nand\n.Fl U\nflags are non-standard and should not be relied upon for portability.\n.Pp\nTemporary files may be left in the target directory if\n.Nm\nexits abnormally.\n"
  },
  {
    "path": "tools/binstall/pathnames.h",
    "content": "/*\t$OpenBSD: pathnames.h,v 1.3 2003/06/03 02:56:24 millert Exp $\t*/\n/*\t$NetBSD: pathnames.h,v 1.3 1994/11/14 04:57:18 jtc Exp $\t*/\n\n/*\n * Copyright (c) 1989, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n *\t@(#)pathnames.h\t8.1 (Berkeley) 6/6/93\n *\t$NetBSD: pathnames.h,v 1.3 1994/11/14 04:57:18 jtc Exp $\n */\n\n#define\t_PATH_STRIP\t\"/usr/bin/strip\"\n"
  },
  {
    "path": "tools/binstall/xinstall.c",
    "content": "/*\t$OpenBSD: xinstall.c,v 1.77 2022/12/04 23:50:50 cheloha Exp $\t*/\n/*\t$NetBSD: xinstall.c,v 1.9 1995/12/20 10:25:17 jonathan Exp $\t*/\n\n/*\n * Copyright (c) 1987, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n#include <sys/types.h>\n#include <sys/wait.h>\n#include <sys/mman.h>\n#include <sys/stat.h>\n\n#include <ctype.h>\n#include <err.h>\n#include <errno.h>\n#include <fcntl.h>\n#include <grp.h>\n#include <paths.h>\n#include <pwd.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n#include <limits.h>\n#include <libgen.h>\n\n#include \"pathnames.h\"\n\n#define\tHAVE_CHFLAGS\t1\n#define\tHAVE_ISSETUGID\t1\n#ifdef\t__linux__\n#undef\tHAVE_CHFLAGS\n#undef\tHAVE_ISSETUGID\n#endif\n\n#ifndef\tUID_MAX\n#define\tUID_MAX\t\tUINT_MAX\n#endif\n#ifndef\tGID_MAX\n#define\tGID_MAX\t\tUINT_MAX\n#endif\n\n#define _MAXBSIZE (64 * 1024)\n\n#define MINIMUM(a, b)\t(((a) < (b)) ? (a) : (b))\n\n#define\tDIRECTORY\t0x01\t\t/* Tell install it's a directory. */\n#define\tSETFLAGS\t0x02\t\t/* Tell install to set flags. */\n#define\tUSEFSYNC\t0x04\t\t/* Tell install to use fsync(2). */\n#define BACKUP_SUFFIX\t\".old\"\n\nint dobackup, docompare, dodest, dodir, dopreserve, dostrip, dounpriv;\nint mode = S_IRWXU|S_IRGRP|S_IXGRP|S_IROTH|S_IXOTH;\nchar pathbuf[PATH_MAX], tempfile[PATH_MAX];\nchar *suffix = BACKUP_SUFFIX;\nuid_t uid = (uid_t)-1;\ngid_t gid = (gid_t)-1;\n\nvoid\tcopy(int, char *, int, char *, off_t, int);\nint\tcompare(int, const char *, off_t, int, const char *, off_t);\nvoid\tinstall(char *, char *, u_long, u_int);\nvoid\tinstall_dir(char *, int);\nvoid\tstrip(char *);\nvoid\tusage(void);\nint\tcreate_tempfile(char *, char *, size_t);\nint\tfile_write(int, char *, size_t, int *, int *, int);\nvoid\tfile_flush(int, int);\n\nint\nmain(int argc, char *argv[])\n{\n\tstruct stat from_sb, to_sb;\n\tvoid *set;\n#ifdef __FreeBSD__\n\tu_long fset = 0;\n#else\n\tu_int32_t fset = 0;\n#endif\n\tu_int iflags;\n\tint ch, no_target;\n\tchar *flags, *to_name, *group = NULL, *owner = NULL;\n\tconst char *errstr;\n\n\tiflags = 0;\n\twhile ((ch = getopt(argc, argv, \"B:bCcDdFf:g:m:o:pSsU\")) != -1)\n\t\tswitch(ch) {\n\t\tcase 'C':\n\t\t\tdocompare = 1;\n\t\t\tbreak;\n\t\tcase 'B':\n\t\t\tsuffix = optarg;\n\t\t\t/* fall through; -B implies -b */\n\t\tcase 'b':\n\t\t\tdobackup = 1;\n\t\t\tbreak;\n\t\tcase 'c':\n\t\t\t/* For backwards compatibility. */\n\t\t\tbreak;\n\t\tcase 'F':\n\t\t\tiflags |= USEFSYNC;\n\t\t\tbreak;\n\t\tcase 'f':\n\t\t\tflags = optarg;\n#if HAVE_CHFLAGS\n\t\t\tif (strtofflags(&flags, &fset, NULL))\n\t\t\t\terrx(1, \"%s: invalid flag\", flags);\n\t\t\tiflags |= SETFLAGS;\n#endif\n\t\t\tbreak;\n\t\tcase 'g':\n\t\t\tgroup = optarg;\n\t\t\tbreak;\n\t\tcase 'm':\n\t\t\tif (!(set = setmode(optarg)))\n\t\t\t\terrx(1, \"%s: invalid file mode\", optarg);\n\t\t\tmode = getmode(set, 0);\n\t\t\tfree(set);\n\t\t\tbreak;\n\t\tcase 'o':\n\t\t\towner = optarg;\n\t\t\tbreak;\n\t\tcase 'p':\n\t\t\tdocompare = dopreserve = 1;\n\t\t\tbreak;\n\t\tcase 'S':\n\t\t\t/* For backwards compatibility. */\n\t\t\tbreak;\n\t\tcase 's':\n\t\t\tdostrip = 1;\n\t\t\tbreak;\n\t\tcase 'D':\n\t\t\tdodest = 1;\n\t\t\tbreak;\n\t\tcase 'd':\n\t\t\tdodir = 1;\n\t\t\tbreak;\n\t\tcase 'U':\n\t\t\tdounpriv = 1;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tusage();\n\t\t}\n\targc -= optind;\n\targv += optind;\n\n\t/* some options make no sense when creating directories */\n\tif ((docompare || dostrip) && dodir)\n\t\tusage();\n\n\t/* must have at least two arguments, except when creating directories */\n\tif (argc == 0 || (argc == 1 && !dodir))\n\t\tusage();\n\n\t/* get group and owner id's */\n\tif (group != NULL && !dounpriv && gid_from_group(group, &gid) == -1) {\n\t\tgid = strtonum(group, 0, GID_MAX, &errstr);\n\t\tif (errstr != NULL)\n\t\t\terrx(1, \"unknown group %s\", group);\n\t}\n\tif (owner != NULL && !dounpriv && uid_from_user(owner, &uid) == -1) {\n\t\tuid = strtonum(owner, 0, UID_MAX, &errstr);\n\t\tif (errstr != NULL)\n\t\t\terrx(1, \"unknown user %s\", owner);\n\t}\n\n\tif (dodir) {\n\t\tfor (; *argv != NULL; ++argv)\n\t\t\tinstall_dir(*argv, mode);\n\t\texit(0);\n\t\t/* NOTREACHED */\n\t}\n\n\tif (dodest) {\n\t\tchar *dest = dirname(argv[argc - 1]);\n\t\tif (dest == NULL)\n\t\t\terrx(1, \"cannot determine dirname\");\n\t\t/*\n\t\t * When -D is passed, do not chmod the directory with the mode set for\n\t\t * the target file. If more restrictive permissions are required then\n\t\t * '-d -m' ought to be used instead.\n\t\t */\n\t\tinstall_dir(dest, 0755);\n\t}\n\n\tno_target = stat(to_name = argv[argc - 1], &to_sb);\n\tif (!no_target && S_ISDIR(to_sb.st_mode)) {\n\t\tfor (; *argv != to_name; ++argv)\n\t\t\tinstall(*argv, to_name, fset, iflags | DIRECTORY);\n\t\texit(0);\n\t\t/* NOTREACHED */\n\t}\n\n\t/* can't do file1 file2 directory/file */\n\tif (argc != 2)\n\t\terrx(1, \"Target: %s\", argv[argc-1]);\n\n\tif (!no_target) {\n\t\tif (stat(*argv, &from_sb))\n\t\t\terr(1, \"%s\", *argv);\n\t\tif (!S_ISREG(to_sb.st_mode))\n\t\t\terrx(1, \"%s: not a regular file\", to_name);\n\t\tif (to_sb.st_dev == from_sb.st_dev &&\n\t\t    to_sb.st_ino == from_sb.st_ino)\n\t\t\terrx(1, \"%s and %s are the same file\", *argv, to_name);\n\t}\n\tinstall(*argv, to_name, fset, iflags);\n\texit(0);\n\t/* NOTREACHED */\n}\n\n/*\n * install --\n *\tbuild a path name and install the file\n */\nvoid\ninstall(char *from_name, char *to_name, u_long fset, u_int flags)\n{\n\tstruct stat from_sb, to_sb;\n\tstruct timespec ts[2];\n\tint devnull, from_fd, to_fd, serrno, tmpmode, files_match = 0;\n\tchar *p;\n\tchar *target_name = tempfile;\n\n\t(void)memset((void *)&from_sb, 0, sizeof(from_sb));\n\t(void)memset((void *)&to_sb, 0, sizeof(to_sb));\n\n\t/* If try to install NULL file to a directory, fails. */\n\tif (flags & DIRECTORY || strcmp(from_name, _PATH_DEVNULL)) {\n\t\tif (stat(from_name, &from_sb))\n\t\t\terr(1, \"%s\", from_name);\n\t\tif (!S_ISREG(from_sb.st_mode))\n\t\t\terrx(1, \"%s: not a regular file\", from_name);\n\t\t/* Build the target path. */\n\t\tif (flags & DIRECTORY) {\n\t\t\t(void)snprintf(pathbuf, sizeof(pathbuf), \"%s/%s\",\n\t\t\t    to_name,\n\t\t\t    (p = strrchr(from_name, '/')) ? ++p : from_name);\n\t\t\tto_name = pathbuf;\n\t\t}\n\t\tdevnull = 0;\n\t} else {\n\t\tdevnull = 1;\n\t}\n\n\tif (stat(to_name, &to_sb) == 0) {\n\t\t/* Only compare against regular files. */\n\t\tif (docompare && !S_ISREG(to_sb.st_mode)) {\n\t\t\tdocompare = 0;\n\t\t\twarnx(\"%s: not a regular file\", to_name);\n\t\t}\n\t} else if (docompare) {\n\t\t/* File does not exist so silently ignore compare flag. */\n\t\tdocompare = 0;\n\t}\n\n\tif (!devnull) {\n\t\tif ((from_fd = open(from_name, O_RDONLY)) == -1)\n\t\t\terr(1, \"%s\", from_name);\n\t}\n\n\tto_fd = create_tempfile(to_name, tempfile, sizeof(tempfile));\n\tif (to_fd < 0)\n\t\terr(1, \"%s\", tempfile);\n\n\tif (!devnull)\n\t\tcopy(from_fd, from_name, to_fd, tempfile, from_sb.st_size,\n\t\t    ((off_t)from_sb.st_blocks * S_BLKSIZE < from_sb.st_size));\n\n\tif (dostrip) {\n\t\tstrip(tempfile);\n\n\t\t/*\n\t\t * Re-open our fd on the target, in case we used a strip\n\t\t *  that does not work in-place -- like gnu binutils strip.\n\t\t */\n\t\tclose(to_fd);\n\t\tif ((to_fd = open(tempfile, O_RDONLY)) == -1)\n\t\t\terr(1, \"stripping %s\", to_name);\n\t}\n\n\t/*\n\t * Compare the (possibly stripped) temp file to the target.\n\t */\n\tif (docompare) {\n\t\tint temp_fd = to_fd;\n\t\tstruct stat temp_sb;\n\n\t\t/* Re-open to_fd using the real target name. */\n\t\tif ((to_fd = open(to_name, O_RDONLY)) == -1)\n\t\t\terr(1, \"%s\", to_name);\n\n\t\tif (fstat(temp_fd, &temp_sb)) {\n\t\t\tserrno = errno;\n\t\t\t(void)unlink(tempfile);\n\t\t\terrc(1, serrno, \"%s\", tempfile);\n\t\t}\n\n\t\tif (compare(temp_fd, tempfile, temp_sb.st_size, to_fd,\n\t\t\t    to_name, to_sb.st_size) == 0) {\n\t\t\t/*\n\t\t\t * If target has more than one link we need to\n\t\t\t * replace it in order to snap the extra links.\n\t\t\t * Need to preserve target file times, though.\n\t\t\t */\n\t\t\tif (to_sb.st_nlink != 1) {\n\t\t\t\tts[0] = to_sb.st_atim;\n\t\t\t\tts[1] = to_sb.st_mtim;\n\t\t\t\tfutimens(temp_fd, ts);\n\t\t\t} else {\n\t\t\t\tfiles_match = 1;\n\t\t\t\t(void)unlink(tempfile);\n\t\t\t\ttarget_name = to_name;\n\t\t\t\t(void)close(temp_fd);\n\t\t\t}\n\t\t}\n\t\tif (!files_match) {\n\t\t\t(void)close(to_fd);\n\t\t\tto_fd = temp_fd;\n\t\t}\n\t}\n\n\t/*\n\t * Preserve the timestamp of the source file if necessary.\n\t */\n\tif (dopreserve && !dounpriv && !files_match) {\n\t\tts[0] = from_sb.st_atim;\n\t\tts[1] = from_sb.st_mtim;\n\t\tfutimens(to_fd, ts);\n\t}\n\n\t/*\n\t * Set owner, group, mode for target; do the chown first,\n\t * chown may lose the setuid bits.\n\t */\n\tif (!dounpriv && (gid != (gid_t)-1 || uid != (uid_t)-1) &&\n\t    fchown(to_fd, uid, gid)) {\n\t\tserrno = errno;\n\t\tif (target_name == tempfile)\n\t\t\t(void)unlink(target_name);\n\t\terrx(1, \"%s: chown/chgrp: %s\", target_name, strerror(serrno));\n\t}\n\n\t/* If unprivileged, still do a chmod of the lower 0777 bits. */\n\ttmpmode = mode;\n\tif (dounpriv)\n\t\ttmpmode &= S_IRWXU|S_IRWXG|S_IRWXO;\n\tif (fchmod(to_fd, tmpmode)) {\n\t\tserrno = errno;\n\t\tif (target_name == tempfile)\n\t\t\t(void)unlink(target_name);\n\t\terrx(1, \"%s: chmod: %s\", target_name, strerror(serrno));\n\t}\n\n#if HAVE_CHFLAGS\n\t/*\n\t * If provided a set of flags, set them, otherwise, preserve the\n\t * flags, except for the dump flag.\n\t */\n\tif (!dounpriv && fchflags(to_fd,\n\t    flags & SETFLAGS ? fset : from_sb.st_flags & ~UF_NODUMP)) {\n\t\tif (errno != EOPNOTSUPP || (from_sb.st_flags & ~UF_NODUMP) != 0)\n\t\t\twarnx(\"%s: chflags: %s\", target_name, strerror(errno));\n\t}\n#endif\n\n\tif (flags & USEFSYNC)\n\t\tfsync(to_fd);\n\t(void)close(to_fd);\n\tif (!devnull)\n\t\t(void)close(from_fd);\n\n\t/*\n\t * Move the new file into place if the files are different\n\t * or were not compared.\n\t */\n\tif (!files_match) {\n#if HAVE_CHFLAGS\n#define NOCHANGEBITS\t(UF_IMMUTABLE | UF_APPEND | SF_IMMUTABLE | SF_APPEND)\n\t\t/* Try to turn off the immutable bits. */\n\t\tif (to_sb.st_flags & (NOCHANGEBITS))\n\t\t\t(void)chflags(to_name, to_sb.st_flags & ~(NOCHANGEBITS));\n#endif\n\t\tif (dobackup) {\n\t\t\tchar backup[PATH_MAX];\n\t\t\t(void)snprintf(backup, PATH_MAX, \"%s%s\", to_name,\n\t\t\t    suffix);\n\t\t\t/* It is ok for the target file not to exist. */\n\t\t\tif (rename(to_name, backup) == -1 && errno != ENOENT) {\n\t\t\t\tserrno = errno;\n\t\t\t\tunlink(tempfile);\n\t\t\t\terrx(1, \"rename: %s to %s: %s\", to_name,\n\t\t\t\t     backup, strerror(serrno));\n\t\t\t}\n\t\t}\n\t\tif (rename(tempfile, to_name) == -1 ) {\n\t\t\tserrno = errno;\n\t\t\tunlink(tempfile);\n\t\t\terrx(1, \"rename: %s to %s: %s\", tempfile,\n\t\t\t     to_name, strerror(serrno));\n\t\t}\n\t}\n}\n\n/*\n * copy --\n *\tcopy from one file to another\n */\nvoid\ncopy(int from_fd, char *from_name, int to_fd, char *to_name, off_t size,\n    int sparse)\n{\n\tssize_t nr, nw;\n\tint serrno;\n\tchar *p, buf[_MAXBSIZE];\n\n\tif (size == 0)\n\t\treturn;\n\n\t/* Rewind file descriptors. */\n\tif (lseek(from_fd, (off_t)0, SEEK_SET) == (off_t)-1)\n\t\terr(1, \"lseek: %s\", from_name);\n\tif (lseek(to_fd, (off_t)0, SEEK_SET) == (off_t)-1)\n\t\terr(1, \"lseek: %s\", to_name);\n\n\t/*\n\t * Mmap and write if less than 8M (the limit is so we don't totally\n\t * trash memory on big files.  This is really a minor hack, but it\n\t * wins some CPU back.  Sparse files need special treatment.\n\t */\n\tif (!sparse && size <= 8 * 1048576) {\n\t\tsize_t siz;\n\n\t\tif ((p = mmap(NULL, (size_t)size, PROT_READ, MAP_PRIVATE,\n\t\t    from_fd, (off_t)0)) == MAP_FAILED) {\n\t\t\tserrno = errno;\n\t\t\t(void)unlink(to_name);\n\t\t\terrc(1, serrno, \"%s\", from_name);\n\t\t}\n\t\tmadvise(p, size, MADV_SEQUENTIAL);\n\t\tsiz = (size_t)size;\n\t\tif ((nw = write(to_fd, p, siz)) != siz) {\n\t\t\tserrno = errno;\n\t\t\t(void)unlink(to_name);\n\t\t\terrx(1, \"%s: %s\",\n\t\t\t    to_name, strerror(nw > 0 ? EIO : serrno));\n\t\t}\n\t\t(void) munmap(p, (size_t)size);\n\t} else {\n\t\tint sz, rem, isem = 1;\n\t\tstruct stat sb;\n\n\t\t/*\n\t\t * Pass the blocksize of the file being written to the write\n\t\t * routine.  if the size is zero, use the default S_BLKSIZE.\n\t\t */\n\t\tif (fstat(to_fd, &sb) != 0 || sb.st_blksize == 0)\n\t\t\tsz = S_BLKSIZE;\n\t\telse\n\t\t\tsz = sb.st_blksize;\n\t\trem = sz;\n\n\t\twhile ((nr = read(from_fd, buf, sizeof(buf))) > 0) {\n\t\t\tif (sparse)\n\t\t\t\tnw = file_write(to_fd, buf, nr, &rem, &isem, sz);\n\t\t\telse\n\t\t\t\tnw = write(to_fd, buf, nr);\n\t\t\tif (nw != nr) {\n\t\t\t\tserrno = errno;\n\t\t\t\t(void)unlink(to_name);\n\t\t\t\terrx(1, \"%s: %s\",\n\t\t\t\t    to_name, strerror(nw > 0 ? EIO : serrno));\n\t\t\t}\n\t\t}\n\t\tif (sparse)\n\t\t\tfile_flush(to_fd, isem);\n\t\tif (nr != 0) {\n\t\t\tserrno = errno;\n\t\t\t(void)unlink(to_name);\n\t\t\terrc(1, serrno, \"%s\", from_name);\n\t\t}\n\t}\n}\n\n/*\n * compare --\n *\tcompare two files; non-zero means files differ\n */\nint\ncompare(int from_fd, const char *from_name, off_t from_len, int to_fd,\n    const char *to_name, off_t to_len)\n{\n\tcaddr_t p1, p2;\n\tsize_t length;\n\toff_t from_off, to_off, remainder;\n\tint dfound;\n\n\tif (from_len == 0 && from_len == to_len)\n\t\treturn (0);\n\n\tif (from_len != to_len)\n\t\treturn (1);\n\n\t/*\n\t * Compare the two files being careful not to mmap\n\t * more than 8M at a time.\n\t */\n\tfrom_off = to_off = (off_t)0;\n\tremainder = from_len;\n\tdo {\n\t\tlength = MINIMUM(remainder, 8 * 1048576);\n\t\tremainder -= length;\n\n\t\tif ((p1 = mmap(NULL, length, PROT_READ, MAP_PRIVATE,\n\t\t    from_fd, from_off)) == MAP_FAILED)\n\t\t\terr(1, \"%s\", from_name);\n\t\tif ((p2 = mmap(NULL, length, PROT_READ, MAP_PRIVATE,\n\t\t    to_fd, to_off)) == MAP_FAILED)\n\t\t\terr(1, \"%s\", to_name);\n\t\tif (length) {\n\t\t\tmadvise(p1, length, MADV_SEQUENTIAL);\n\t\t\tmadvise(p2, length, MADV_SEQUENTIAL);\n\t\t}\n\n\t\tdfound = memcmp(p1, p2, length);\n\n\t\t(void) munmap(p1, length);\n\t\t(void) munmap(p2, length);\n\n\t\tfrom_off += length;\n\t\tto_off += length;\n\n\t} while (!dfound && remainder > 0);\n\n\treturn(dfound);\n}\n\n/*\n * strip --\n *\tuse strip(1) to strip the target file\n */\nvoid\nstrip(char *to_name)\n{\n\tint serrno, status;\n\tchar * volatile path_strip;\n\tpid_t pid;\n\n#if HAVE_ISSETUGID\n\tif (issetugid() || (path_strip = getenv(\"STRIP\")) == NULL)\n#endif\n\t\tpath_strip = _PATH_STRIP;\n\n\tswitch ((pid = vfork())) {\n\tcase -1:\n\t\tserrno = errno;\n\t\t(void)unlink(to_name);\n\t\terrc(1, serrno, \"forks\");\n\tcase 0:\n\t\texecl(path_strip, \"strip\", \"--\", to_name, (char *)NULL);\n\t\twarn(\"%s\", path_strip);\n\t\t_exit(1);\n\tdefault:\n\t\twhile (waitpid(pid, &status, 0) == -1) {\n\t\t\tif (errno != EINTR)\n\t\t\t\tbreak;\n\t\t}\n\t\tif (!WIFEXITED(status))\n\t\t\t(void)unlink(to_name);\n\t}\n}\n\n/*\n * install_dir --\n *\tbuild directory hierarchy\n */\nvoid\ninstall_dir(char *path, int mode)\n{\n\tchar *p;\n\tstruct stat sb;\n\tint ch;\n\n\tfor (p = path;; ++p)\n\t\tif (!*p || (p != path && *p  == '/')) {\n\t\t\tch = *p;\n\t\t\t*p = '\\0';\n\t\t\tif (mkdir(path, 0777)) {\n\t\t\t\tint mkdir_errno = errno;\n\t\t\t\tif (stat(path, &sb)) {\n\t\t\t\t\t/* Not there; use mkdir()s errno */\n\t\t\t\t\terrc(1, mkdir_errno, \"%s\",\n\t\t\t\t\t    path);\n\t\t\t\t\t/* NOTREACHED */\n\t\t\t\t}\n\t\t\t\tif (!S_ISDIR(sb.st_mode)) {\n\t\t\t\t\t/* Is there, but isn't a directory */\n\t\t\t\t\terrc(1, ENOTDIR, \"%s\", path);\n\t\t\t\t\t/* NOTREACHED */\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (!(*p = ch))\n\t\t\t\tbreak;\n\t\t}\n\n\tif (!dounpriv && (((gid != (gid_t)-1 || uid != (uid_t)-1) &&\n\t    chown(path, uid, gid)) || chmod(path, mode))) {\n\t\twarn(\"%s\", path);\n\t}\n}\n\n/*\n * usage --\n *\tprint a usage message and die\n */\nvoid\nusage(void)\n{\n\t(void)fprintf(stderr, \"usage: install [-bCcDdFpSsU] [-B suffix] \");\n\t(void)fprintf(stderr, \"[-f flags] [-g group] [-m mode]\\n\");\n\t(void)fprintf(stderr, \"\\t       [-o owner] source ... target ...\\n\");\n\texit(1);\n\t/* NOTREACHED */\n}\n\n/*\n * create_tempfile --\n *\tcreate a temporary file based on path and open it\n */\nint\ncreate_tempfile(char *path, char *temp, size_t tsize)\n{\n\tchar *p;\n\n\tstrlcpy(temp, path, tsize);\n\tif ((p = strrchr(temp, '/')) != NULL)\n\t\tp++;\n\telse\n\t\tp = temp;\n\t*p = '\\0';\n\tstrlcat(p, \"INS@XXXXXXXXXX\", tsize);\n\n\treturn(mkstemp(temp));\n}\n\n/*\n * file_write()\n *\tWrite/copy a file (during copy or archive extract). This routine knows\n *\thow to copy files with lseek holes in it. (Which are read as file\n *\tblocks containing all 0's but do not have any file blocks associated\n *\twith the data). Typical examples of these are files created by dbm\n *\tvariants (.pag files). While the file size of these files are huge, the\n *\tactual storage is quite small (the files are sparse). The problem is\n *\tthe holes read as all zeros so are probably stored on the archive that\n *\tway (there is no way to determine if the file block is really a hole,\n *\twe only know that a file block of all zero's can be a hole).\n *\tAt this writing, no major archive format knows how to archive files\n *\twith holes. However, on extraction (or during copy, -rw) we have to\n *\tdeal with these files. Without detecting the holes, the files can\n *\tconsume a lot of file space if just written to disk. This replacement\n *\tfor write when passed the basic allocation size of a file system block,\n *\tuses lseek whenever it detects the input data is all 0 within that\n *\tfile block. In more detail, the strategy is as follows:\n *\tWhile the input is all zero keep doing an lseek. Keep track of when we\n *\tpass over file block boundaries. Only write when we hit a non zero\n *\tinput. once we have written a file block, we continue to write it to\n *\tthe end (we stop looking at the input). When we reach the start of the\n *\tnext file block, start checking for zero blocks again. Working on file\n *\tblock boundaries significantly reduces the overhead when copying files\n *\tthat are NOT very sparse. This overhead (when compared to a write) is\n *\talmost below the measurement resolution on many systems. Without it,\n *\tfiles with holes cannot be safely copied. It does has a side effect as\n *\tit can put holes into files that did not have them before, but that is\n *\tnot a problem since the file contents are unchanged (in fact it saves\n *\tfile space). (Except on paging files for diskless clients. But since we\n *\tcannot determine one of those file from here, we ignore them). If this\n *\tever ends up on a system where CTG files are supported and the holes\n *\tare not desired, just do a conditional test in those routines that\n *\tcall file_write() and have it call write() instead. BEFORE CLOSING THE\n *\tFILE, make sure to call file_flush() when the last write finishes with\n *\tan empty block. A lot of file systems will not create an lseek hole at\n *\tthe end. In this case we drop a single 0 at the end to force the\n *\ttrailing 0's in the file.\n *\t---Parameters---\n *\trem: how many bytes left in this file system block\n *\tisempt: have we written to the file block yet (is it empty)\n *\tsz: basic file block allocation size\n *\tcnt: number of bytes on this write\n *\tstr: buffer to write\n * Return:\n *\tnumber of bytes written, -1 on write (or lseek) error.\n */\n\nint\nfile_write(int fd, char *str, size_t cnt, int *rem, int *isempt, int sz)\n{\n\tchar *pt;\n\tchar *end;\n\tsize_t wcnt;\n\tchar *st = str;\n\n\t/*\n\t * while we have data to process\n\t */\n\twhile (cnt) {\n\t\tif (!*rem) {\n\t\t\t/*\n\t\t\t * We are now at the start of file system block again\n\t\t\t * (or what we think one is...). start looking for\n\t\t\t * empty blocks again\n\t\t\t */\n\t\t\t*isempt = 1;\n\t\t\t*rem = sz;\n\t\t}\n\n\t\t/*\n\t\t * only examine up to the end of the current file block or\n\t\t * remaining characters to write, whatever is smaller\n\t\t */\n\t\twcnt = MINIMUM(cnt, *rem);\n\t\tcnt -= wcnt;\n\t\t*rem -= wcnt;\n\t\tif (*isempt) {\n\t\t\t/*\n\t\t\t * have not written to this block yet, so we keep\n\t\t\t * looking for zero's\n\t\t\t */\n\t\t\tpt = st;\n\t\t\tend = st + wcnt;\n\n\t\t\t/*\n\t\t\t * look for a zero filled buffer\n\t\t\t */\n\t\t\twhile ((pt < end) && (*pt == '\\0'))\n\t\t\t\t++pt;\n\n\t\t\tif (pt == end) {\n\t\t\t\t/*\n\t\t\t\t * skip, buf is empty so far\n\t\t\t\t */\n\t\t\t\tif (lseek(fd, (off_t)wcnt, SEEK_CUR) == -1) {\n\t\t\t\t\twarn(\"lseek\");\n\t\t\t\t\treturn(-1);\n\t\t\t\t}\n\t\t\t\tst = pt;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/*\n\t\t\t * drat, the buf is not zero filled\n\t\t\t */\n\t\t\t*isempt = 0;\n\t\t}\n\n\t\t/*\n\t\t * have non-zero data in this file system block, have to write\n\t\t */\n\t\tif (write(fd, st, wcnt) != wcnt) {\n\t\t\twarn(\"write\");\n\t\t\treturn(-1);\n\t\t}\n\t\tst += wcnt;\n\t}\n\treturn(st - str);\n}\n\n/*\n * file_flush()\n *\twhen the last file block in a file is zero, many file systems will not\n *\tlet us create a hole at the end. To get the last block with zeros, we\n *\twrite the last BYTE with a zero (back up one byte and write a zero).\n */\nvoid\nfile_flush(int fd, int isempt)\n{\n\tstatic char blnk[] = \"\\0\";\n\n\t/*\n\t * silly test, but make sure we are only called when the last block is\n\t * filled with all zeros.\n\t */\n\tif (!isempt)\n\t\treturn;\n\n\t/*\n\t * move back one byte and write a zero\n\t */\n\tif (lseek(fd, (off_t)-1, SEEK_CUR) == -1) {\n\t\twarn(\"Failed seek on file\");\n\t\treturn;\n\t}\n\n\tif (write(fd, blnk, 1) == -1)\n\t\twarn(\"Failed write to file\");\n\treturn;\n}\n"
  },
  {
    "path": "tools/icache/.gitignore",
    "content": "ice2aout\n"
  },
  {
    "path": "tools/icache/Makefile",
    "content": "TOPSRC!=cd ../..; pwd\n\n-include ../Makefile.inc\n\nCFLAGS\t\t= -O -Wall\nOBJS\t\t= ice2aout.o\nPROG\t\t= ice2aout\n\n# For Mac OS X\n#LIBS\t\t= -largp\n\nall:\t\t$(PROG)\n\ninstall:\tall\n\t\t${INSTALL} ${PROG} ${TOOLBINDIR}/${PROG}\n\nclean:\n\t\trm -f *~ *.o ${PROG}\n\n$(PROG):\t$(OBJS)\n\t\t$(CC) $(LDFLAGS) -o $@ $(OBJS) $(LIBS)\n"
  },
  {
    "path": "tools/icache/ice2aout.c",
    "content": "/*                                                                             \nCopyright (c) 2013, Alexey Frunze                                              \nAll rights reserved.                                                           \n                                                                               \nRedistribution and use in source and binary forms, with or without             \nmodification, are permitted provided that the following conditions are met:    \n                                                                               \n1. Redistributions of source code must retain the above copyright notice, this \n   list of conditions and the following disclaimer.                            \n2. Redistributions in binary form must reproduce the above copyright notice,   \n   this list of conditions and the following disclaimer in the documentation   \n   and/or other materials provided with the distribution.                      \n                                                                               \nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\nANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED  \nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE         \nDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\nANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES \n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;   \nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND    \nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT     \n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS  \nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                   \n                                                                               \nThe views and conclusions contained in the software and documentation are those\nof the authors and should not be interpreted as representing official policies,\neither expressed or implied, of the FreeBSD Project.                           \n*/                                                                             \n                                                                               \n/*****************************************************************************/\n/*                                                                           */\n/*     MIPS ELF to RetroBSD a.out convertor with support for MIPS icache     */\n/*                                                                           */\n/*****************************************************************************/\n\n#include <limits.h>\n#include <stdarg.h>\n#include <ctype.h>\n#include <string.h>\n#include <stdio.h>\n#include <stdlib.h>\n\ntypedef unsigned char uchar, uint8;\ntypedef signed char schar, int8;\ntypedef unsigned short ushort, uint16;\ntypedef short int16;\n#if UINT_MAX >= 0xFFFFFFFF\ntypedef unsigned uint32;\ntypedef int int32;\n#else\ntypedef unsigned long uint32;\ntypedef long int32;\n#endif\ntypedef unsigned uint;\ntypedef unsigned long ulong;\ntypedef long long longlong;\ntypedef unsigned long long ulonglong;\n#if ULONG_MAX >= 0xFFFFFFFFFFFFFFFFULL\ntypedef unsigned long uint64;\ntypedef long int64;\n#else\ntypedef unsigned long long uint64;\ntypedef long long int64;\n#endif\n\n#define C_ASSERT(expr) extern char CAssertExtern[(expr)?1:-1]\n\nC_ASSERT(CHAR_BIT == 8);\nC_ASSERT(sizeof(uint16) == 2);\nC_ASSERT(sizeof(uint32) == 4);\nC_ASSERT(sizeof(uint64) == 8);\nC_ASSERT(sizeof(size_t) >= 4);\n\n#pragma pack(push,1)\n\ntypedef struct\n{\n  uint8  e_ident[16];\n  uint16 e_type;\n  uint16 e_machine;\n  uint32 e_version;\n  uint32 e_entry;\n  uint32 e_phoff;\n  uint32 e_shoff;\n  uint32 e_flags;\n  uint16 e_ehsize;\n  uint16 e_phentsize;\n  uint16 e_phnum;\n  uint16 e_shentsize;\n  uint16 e_shnum;\n  uint16 e_shstrndx;\n} Elf32Hdr;\n\ntypedef struct\n{\n  uint32 sh_name;\n  uint32 sh_type;\n  uint32 sh_flags;\n  uint32 sh_addr;\n  uint32 sh_offset;\n  uint32 sh_size;\n  uint32 sh_link;\n  uint32 sh_info;\n  uint32 sh_addralign;\n  uint32 sh_entsize;\n} Elf32SectHdr;\n\ntypedef struct\n{\n  uint32 a_magic;   /* magic number */\n#define OMAGIC 0407 /* old impure format */\n\n  uint32 a_text;    /* size of text segment */\n  uint32 a_data;    /* size of initialized data */\n  uint32 a_bss;     /* size of uninitialized data */\n  uint32 a_reltext; /* size of text relocation info */\n  uint32 a_reldata; /* size of data relocation info */\n  uint32 a_syms;    /* size of symbol table */\n  uint32 a_entry;   /* entry point */\n} AoutHdr;\n\n#pragma pack(pop)\n\nC_ASSERT(sizeof(Elf32Hdr) == 52);\nC_ASSERT(sizeof(Elf32SectHdr) == 40);\nC_ASSERT(sizeof(AoutHdr) == 32);\n\ntypedef struct\n{\n  const char* Name;\n  uint32 FileOffs;\n  uint32 Addr;\n  uint32 Size;\n  uint32 Flags;\n  uint32 Flags2;\n} tSection;\n\ntSection* Sections = NULL;\nuint SectionCnt = 0;\nchar* SectNames = NULL;\nuint32 EntryPointAddr = 0;\n\nFILE* ElfFile = NULL;\nFILE* AoutFile = NULL;\nconst char* AoutName = NULL;\n\nvoid error(char* format, ...)\n{\n  va_list vl;\n  va_start(vl, format);\n\n  if (ElfFile)\n    fclose(ElfFile);\n  if (AoutFile)\n    fclose(AoutFile);\n  if (AoutName != NULL)\n    remove(AoutName);\n\n  puts(\"\");\n  vprintf(format, vl);\n\n  va_end(vl);\n  exit(-1);\n}\n\nint SectAddrCompare(const void* pa, const void* pb)\n{\n  const tSection *p1 = pa, *p2 = pb;\n  if (p1->Addr < p2->Addr)\n    return -1;\n  else if (p1->Addr > p2->Addr)\n    return +1;\n  return 0;\n}\n\nvoid WriteZeroes(FILE* f, uint32 size)\n{\n  static const char zeroes[1024];\n  while (size)\n  {\n    uint32 sz;\n\n    if (size > sizeof zeroes)\n      sz = sizeof zeroes;\n    else\n      sz = size;\n\n    if (fwrite(zeroes, 1, sz, f) != sz)\n      error(\"Can't write file\\n\");\n\n    size -= sz;\n  }\n}\n\nvoid CopyFileData(FILE* fto, FILE* ffrom, uint32 size)\n{\n  char buf[1024];\n  while (size)\n  {\n    uint32 sz;\n\n    if (size > sizeof buf)\n      sz = sizeof buf;\n    else\n      sz = size;\n\n    if (fread(buf, 1, sz, ffrom) != sz)\n      error(\"Can't read file\\n\");\n\n    if (fwrite(buf, 1, sz, fto) != sz)\n      error(\"Can't write file\\n\");\n\n    size -= sz;\n  }\n}\n\nint main(int argc, char** argv)\n{\n  Elf32Hdr elfHdr;\n  Elf32SectHdr sectHdr;\n  uint idx;\n  int unsupported = 0;\n  int verbose = 0;\n  AoutHdr aoutHdr;\n  uint32 addr;\n  uint32 endAddr = 0, codeEndAddr, bssStartAddr;\n\n  if (argc > 1 && !strcmp(argv[1], \"-v\"))\n  {\n    verbose = 1;\n    argc--;\n    argv++;\n  }\n\n  if (argc != 3 ||\n      !(ElfFile = fopen(argv[1], \"rb\")) ||\n      !(AoutFile = fopen(AoutName = argv[2], \"wb\")))\n    error(\"Usage:\\n  ice2aout [-v] <mips32 elf executable> <RetroBSD mips32 a.out executable>\\n\");\n\n  if (fread(&elfHdr, 1, sizeof elfHdr, ElfFile) != sizeof elfHdr)\n    error(\"Can't read file\\n\");\n\n  if (memcmp(elfHdr.e_ident, \"\\x7F\"\"ELF\", 4))\n    error(\"Not an ELF file\\n\");\n  if (elfHdr.e_ident[6] != 1)\n    error(\"Not a v1 ELF file\\n\");\n  if (elfHdr.e_ehsize != sizeof elfHdr)\n    error(\"Unexpected ELF header size\\n\");\n  if (elfHdr.e_shentsize != sizeof sectHdr)\n    error(\"Unexpected ELF section size\\n\");\n\n  if (elfHdr.e_ident[4] != 1)\n    error(\"Not a 32-bit file\\n\");\n  if (elfHdr.e_ident[5] != 1)\n    error(\"Not a little-endian file\\n\");\n  if (elfHdr.e_type != 2)\n    error(\"Not an executable file\\n\");\n  if (elfHdr.e_machine != 8)\n    error(\"Not a MIPS executable\\n\");\n\n  if (fseek(ElfFile, elfHdr.e_shoff + elfHdr.e_shstrndx * sizeof sectHdr, SEEK_SET))\n    error(\"Can't read file\\n\");\n  if (fread(&sectHdr, 1, sizeof sectHdr, ElfFile) != sizeof sectHdr)\n    error(\"Can't read file\\n\");\n\n  if ((SectNames = malloc(sectHdr.sh_size)) == NULL)\n    error(\"Out of memory\\n\");\n\n  if (fseek(ElfFile, sectHdr.sh_offset, SEEK_SET))\n    error(\"Can't read file\\n\");\n  if (fread(SectNames, 1, sectHdr.sh_size, ElfFile) != sectHdr.sh_size)\n    error(\"Can't read file\\n\");\n\n  if ((Sections = calloc(1, (elfHdr.e_shnum + 1) * sizeof(tSection))) == NULL)\n    error(\"Out of memory\\n\");\n\n  for (idx = 0; idx < elfHdr.e_shnum; idx++)\n  {\n    const char* name = \"\";\n\n    if (fseek(ElfFile, elfHdr.e_shoff + idx * sizeof sectHdr, SEEK_SET))\n      error(\"Can't read file\\n\");\n    if (fread(&sectHdr, 1, sizeof sectHdr, ElfFile) != sizeof sectHdr)\n      error(\"Can't read file\\n\");\n    if (sectHdr.sh_type == 0)\n      memset(&sectHdr, 0, sizeof sectHdr);\n\n    if (sectHdr.sh_name)\n      name = SectNames + sectHdr.sh_name;\n\n    unsupported |=\n      (!strcmp(name, \".dynsym\") ||\n       !strcmp(name, \".dynstr\") ||\n       !strcmp(name, \".dynamic\") ||\n       !strcmp(name, \".hash\") ||\n       !strcmp(name, \".got\") ||\n       !strcmp(name, \".plt\") ||\n       sectHdr.sh_type == 5 || // SHT_HASH\n       sectHdr.sh_type == 6 || // SHT_DYNAMIC\n       sectHdr.sh_type == 11); // SHT_DYNSYM\n\n    // Keep only allocatable sections of non-zero size\n    if ((sectHdr.sh_flags & 2) && sectHdr.sh_size) // SHF_ALLOC and size > 0\n    {\n      Sections[SectionCnt].FileOffs = 0;\n      Sections[SectionCnt].Name = name;\n      Sections[SectionCnt].Addr = sectHdr.sh_addr;\n      Sections[SectionCnt].Size = sectHdr.sh_size;\n      Sections[SectionCnt].Flags = (sectHdr.sh_flags & 1) | ((sectHdr.sh_flags & 4) >> 1); // bit0=Writable,bit1=eXecutable\n\n      if (sectHdr.sh_type == 1) // SHT_PROGBITS\n      {\n        Sections[SectionCnt].FileOffs = sectHdr.sh_offset;\n      }\n\n      SectionCnt++;\n    }\n  }\n\n  EntryPointAddr = elfHdr.e_entry;\n\n  // Sort sections by address as we'll need them in order\n  // and without gaps inbetween\n  qsort(Sections, SectionCnt, sizeof Sections[0], &SectAddrCompare);\n\n  if (verbose)\n  {\n    printf(\" # XAW   VirtAddr   FileOffs       Size Name\\n\");\n    for (idx = 0; idx < SectionCnt; idx++)\n    {\n      tSection* p = &Sections[idx];\n      printf(\"%2u %c%c%c 0x%08lX 0x%08lX %10lu %s\\n\",\n             idx,\n             \"-X\"[(p->Flags / 2) & 1],\n             \"-A\"[1],\n             \"-W\"[(p->Flags / 1) & 1],\n             (ulong)p->Addr,\n             (ulong)p->FileOffs,\n             (ulong)p->Size,\n             p->Name);\n    }\n    printf(\"Entry: 0x%08lX\\n\", (ulong)EntryPointAddr);\n    puts(\"\");\n  }\n\n  if (unsupported)\n    error(\"Dynamically linked or unsupported type of executable\\n\");\n\n  // Write an empty a.out header at first, it will be updated later\n  memset(&aoutHdr, 0, sizeof aoutHdr);\n  if (fwrite(&aoutHdr, 1, sizeof aoutHdr, AoutFile) != sizeof aoutHdr)\n    error(\"Can't write file\\n\");\n\n#define USER_DATA_START 0x7F008000\n#define MAXMEM (96*1024)\n#define USER_DATA_END (USER_DATA_START + MAXMEM)\n\n  if (verbose)\n    printf(\"Phase 1: Processing sections in the range 0x%08lX ... 0x%08lX ...\\n\",\n           (ulong)USER_DATA_START, (ulong)USER_DATA_END - 1);\n\n  addr = USER_DATA_START;\n\n  // Copy non-cached sections\n  for (idx = 0; idx < SectionCnt; idx++)\n  {\n    tSection* p = &Sections[idx];\n\n    if (p->Addr + p->Size >= p->Addr &&\n        p->Addr >= USER_DATA_START &&\n        p->Addr + p->Size <= USER_DATA_END)\n    {\n      if (verbose)\n        printf(\"Copying %s ...\\n\", p->Name);\n\n      if (idx && (Sections[idx - 1].Flags2 & 1))\n      {\n        if (p->Addr < Sections[idx - 1].Addr + Sections[idx - 1].Size)\n          error(\"Sections must not intersect in memory\\n\");\n        if ((p->Flags & 2) && !(Sections[idx - 1].Flags & 2)) // executable after non-executable\n          error(\"Code sections must precede data sections in memory\\n\");\n      }\n      if ((p->Flags & 2) && !p->FileOffs) // executable and initialized to all zeroes\n        error(\"Code sections must not be initialized to all zeroes\\n\");\n\n      // If this section has code/data in it, if it's not initialized to all zeroes...\n      if (p->FileOffs)\n      {\n        // Fill inter-section gaps (and .bss-like sections that aren't at the end)\n        // with zeroes. This lets me order sections more flexibly and yet make\n        // sure they all are properly initialized.\n        if (addr < p->Addr)\n        {\n          WriteZeroes(AoutFile, p->Addr - addr);\n          addr = p->Addr;\n        }\n\n        // Copy section\n        if (fseek(ElfFile, p->FileOffs, SEEK_SET))\n          error(\"Can't read file\\n\");\n        CopyFileData(AoutFile, ElfFile, p->Size);\n        addr += p->Size;\n      }\n\n      p->Flags2 |= 1; // section has been processed\n\n      endAddr = p->Addr + p->Size;\n    }\n    else\n    {\n      if (verbose)\n        printf(\"Skipping %s ...\\n\", p->Name);\n    }\n  }\n\n  if (endAddr == 0)\n    error(\"There are no copiable sections in this range\\n\");\n\n  if (verbose)\n    printf(\"Phase 2: Processing sections outside the range 0x%08lX ... 0x%08lX ...\\n\",\n           (ulong)USER_DATA_START, (ulong)USER_DATA_END - 1);\n\n  // Append cached section(s)\n  for (idx = 0; idx < SectionCnt; idx++)\n  {\n    tSection* p = &Sections[idx];\n\n    if (p->Addr + p->Size >= p->Addr &&\n        (p->Addr >= USER_DATA_END ||\n         p->Addr + p->Size <= USER_DATA_START))\n    {\n      if (verbose)\n        printf(\"Copying %s ...\\n\", p->Name);\n\n      // Copy section\n      if (p->FileOffs)\n      {\n        if (fseek(ElfFile, p->FileOffs, SEEK_SET))\n          error(\"Can't read file\\n\");\n        CopyFileData(AoutFile, ElfFile, p->Size);\n      }\n\n      p->Flags2 |= 1; // section has been processed\n    }\n  }\n\n  // Make sure no section has been left unprocessed\n  for (idx = 0; idx < SectionCnt; idx++)\n  {\n    tSection* p = &Sections[idx];\n    if (!(p->Flags2 & 1))\n      error(\"Not all sections have been processed, e.g. %s hasn't\\n\", p->Name);\n  }\n\n  // Update a.out header\n  aoutHdr.a_magic = OMAGIC;\n  aoutHdr.a_entry = EntryPointAddr;\n\n  codeEndAddr = endAddr;\n\n  for (idx = SectionCnt - 1; idx != (uint)-1; idx--)\n  {\n    tSection* p = &Sections[idx];\n\n    if (p->Addr + p->Size >= p->Addr &&\n        p->Addr >= USER_DATA_START &&\n        p->Addr + p->Size <= USER_DATA_END)\n    {\n      // While not executable, keep going, executable sections are first\n      if (!(p->Flags & 2))\n        codeEndAddr = p->Addr;\n      else\n        break;\n    }\n  }\n\n  bssStartAddr = endAddr;\n\n  for (idx = SectionCnt - 1; idx != (uint)-1; idx--)\n  {\n    tSection* p = &Sections[idx];\n\n    if (p->Addr + p->Size >= p->Addr &&\n        p->Addr >= USER_DATA_START &&\n        p->Addr + p->Size <= USER_DATA_END)\n    {\n      // While initialized to all zeroes, keep going\n      if (!p->FileOffs)\n        bssStartAddr = p->Addr;\n      else\n        break;\n    }\n  }\n\n  aoutHdr.a_text = codeEndAddr - USER_DATA_START;\n  aoutHdr.a_data = bssStartAddr - codeEndAddr;\n  aoutHdr.a_bss = endAddr - bssStartAddr;\n\n  if (fseek(AoutFile, 0, SEEK_SET))\n    error(\"Can't write file\\n\");\n  if (fwrite(&aoutHdr, 1, sizeof aoutHdr, AoutFile) != sizeof aoutHdr)\n    error(\"Can't write file\\n\");\n\n  if (fclose(AoutFile))\n    error(\"Can't write file\\n\");\n  fclose(ElfFile);\n\n  if (verbose)\n  {\n    printf(\"a.out header:\\n\"\n           \"  text size: %lu\\n\"\n           \"  data size: %lu\\n\"\n           \"  bss  size: %lu\\n\",\n           (ulong)aoutHdr.a_text,\n           (ulong)aoutHdr.a_data,\n           (ulong)aoutHdr.a_bss);\n    printf(\"Done\\n\");\n  }\n\n  return 0;\n}\n"
  },
  {
    "path": "tools/icache/license.txt",
    "content": "Copyright (c) 2013, Alexey Frunze\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met: \n\n1. Redistributions of source code must retain the above copyright notice, this\n   list of conditions and the following disclaimer. \n2. Redistributions in binary form must reproduce the above copyright notice,\n   this list of conditions and the following disclaimer in the documentation\n   and/or other materials provided with the distribution. \n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\nANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\nDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\nANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nThe views and conclusions contained in the software and documentation are those\nof the authors and should not be interpreted as representing official policies, \neither expressed or implied, of the FreeBSD Project.\n"
  },
  {
    "path": "tools/icache/readme.txt",
    "content": "icache is a MIPS emulator + software instruction cache.\n\nWith it one may be able to run large programs on MIPS32 processors\nthat would otherwise not fit into small on-chip RAMs of ~128KB.\n\nSupported platform: RetroBSD.\nhttp://www.retrobsd.org/\n\nSee the Wiki for more up-to-date details:\nhttp://github.com/alexfru/icacheMips/wiki\n"
  },
  {
    "path": "tools/libufs/Makefile",
    "content": "TOPSRC!=cd ../..; pwd\n\n-include ../Makefile.inc\n\nLOBJS=fs.o util.o fops.o set.o\nCFLAGS=-Wall -ggdb3\nPROGS=umkfs umkdir uls uchmod uchown uchgrp ulogin ucd ucat\nPOBJS=umkfs.o umkdir.o uls.o uchmod.o uchown.o uchgrp.o ulogin.o ucd.o ucat.o\nLDFLAGS=-L. -lufs -ggdb3\nARFLAGS=-cr\n\nLIB=libufs.a\n\nall: $(LIB) $(PROGS)\n\n$(LIB): $(LOBJS)\n\t$(AR) $(ARFLAGS) $(LIB) $(LOBJS)\n\n$(PROGS): $(POBJS) $(LIB)\n\t$(CC) -o $@ $@.o $(LDFLAGS)\n\nclean:\n\trm -f $(LIB) $(LOBJS) $(PROGS) $(POBJS)\n"
  },
  {
    "path": "tools/libufs/fops.c",
    "content": "#include <stdio.h>\n#include <strings.h>\n#include <stdlib.h>\n#include <string.h>\n#include <errno.h>\n#include <fcntl.h>\n#include <time.h>\n#include \"libufs.h\"\n\n// Split a path into an array of char pointers, each\n// one containing an element of the path,\nchar **splitpath(char *path, int *ndir)\n{\n    char *p,*q;\n    int dn = 0;\n    char **dirs;\n    *ndir = 0;\n\n    p = path;\n    while (*p == '/')\n        p++;\n\n    while (*(p+strlen(p)-1) == '/') {\n        *(p+strlen(p)-1) = '\\0';\n    }\n\n    // First count the number of entries we have\n    q = p;\n    for ( ; *p; p++) {\n        if (*p == '/') {\n            (*ndir)++;\n        }\n    }\n\n    if(*q)\n        (*ndir)++;\n    p = q;\n\n    // Then allocate enough space for them\n    dirs = malloc(*ndir * sizeof(char *));\n\n    // Now do the actual splitting.\n    for ( ; *p; p++) {\n        if ((*p) == '/') {\n            *p = 0;\n            dirs[dn] = q;\n            p++;\n            dn++;\n            q = p;\n        }\n    }\n\n    if (*q) {\n        dirs[dn] = q;\n        dn++;\n    }\n    if (dn != *ndir) {\n        printf(\"Something odd happened to the path\\n\");\n    }\n    \n    return dirs;\n}\n\nunsigned int getfileinode(struct filesystem *f, struct inode *in, char *fn)\n{\n    unsigned int ino = 0;\n    char *buf;\n    char *d;\n    struct direct *de;\n\n    buf = fsreadblock(f, in->i_db[0]);\n    if (!buf) {\n        printf(\"Bad read\\n\");\n        return 0;\n    } \n\n    d = buf;\n    de = (struct direct *)d;\n    while ((de < (struct direct *)(buf+DEV_BSIZE)) && (de->d_ino != 0)) {\n        if (!strcmp(de->d_name, fn)) {\n            ino = de->d_ino;\n            break;\n        }\n        d += de->d_reclen;\n        de = (struct direct *)d;\n    }\n\n    free(buf);\n    \n    return ino;\n}\n\nstruct inode *inodebypath(struct filesystem *f, char *path)\n{\n    char **dirs = NULL;\n    int ndir = 0;\n    int i;\n    struct inode *in = f->root;\n    char *p = strdup(path);\n    int ino __attribute__((unused));\n\n    dirs = splitpath(p, &ndir);\n\n    if (ndir == 0) {\n        free(dirs);\n        free(p); \n        return f->root;\n    }\n\n    for (i = 0; i < ndir; i++) {\n        ino = getfileinode(f, in, dirs[i]);\n        if (ino != 0) {\n            if (in != f->root) {\n                free(in);\n            }\n            in = fsreadinode(f, ino);\n        } else {\n            free(p);\n            free(dirs);\n            if (in != f->root) {\n                free(in);\n            }\n            return 0;\n        }\n    }\n    free(p);\n    free(dirs);\n    return in;\n}\n\nstruct inode *inodebypartpath(struct filesystem *f, char *path, int *depth)\n{\n    char **dirs = NULL;\n    int ndir = 0;\n    int i;\n    struct inode *in = f->root;\n    char *p = strdup(path);\n    int ino __attribute__((unused));\n\n    if(depth)\n        *depth = 0;\n\n    dirs = splitpath(p, &ndir);\n\n    for (i = 0; i < ndir; i++) {\n        ino = getfileinode(f, in, dirs[i]);\n        if (ino != 0) {\n            if (in != f->root) {\n                free(in);\n            }\n            in = fsreadinode(f, ino);\n            if(depth)\n                (*depth)++;\n        } else {\n            printf(\"Not found\\n\");\n            free(p);\n            free(dirs);\n            return in;\n        }\n    }\n    free(p);\n    free(dirs);\n    return in;\n}\n\nvoid listdir(struct filesystem *f, ino_t ino)\n{\n    struct inode *in;\n    struct inode *ip;\n    char *buf;\n    int i;\n    char c;\n    char *d;\n    struct direct *dp;\n    struct tm *tmp;\n    char tbuf[22];\n\n    in = fsreadinode(f, ino);\n\n    for (i = 0; i < NADDR; i++) {\n        if (in->i_db[i] > 0) {\n            buf = fsreadblock(f, in->i_db[i]);\n\n            d = buf;\n            while ((d - buf) < DEV_BSIZE) {\n                dp = (struct direct *)d;\n                ip = fsreadinode(f, dp->d_ino);\n\n                switch (ip->i_mode & IFMT) {\n                case IFBLK:\n                    printf(\"b\");\n                    break;\n                case IFCHR:\n                    printf(\"c\");\n                    break;\n                case IFDIR:\n                    printf(\"d\");\n                    break;\n                case IFLNK:\n                    printf(\"l\");\n                    break;\n                default:\n                    printf(\"-\");\n                    break;\n                }\n\n                c = '-';\n                if (ip->i_mode & 0400)\n                    c = 'r';\n                printf(\"%c\", c);\n\n                c = '-';\n                if (ip->i_mode & 0200)\n                    c = 'w';\n                printf(\"%c\", c);\n\n                c = '-';\n                if (ip->i_mode & 0100)\n                    c = 'x';\n                if (ip->i_mode & 04000)\n                    c = 's';\n                printf(\"%c\", c);\n\n                c = '-';\n                if (ip->i_mode & 0040)\n                    c = 'r';\n                printf(\"%c\", c);\n\n                c = '-';\n                if (ip->i_mode & 0020)\n                    c = 'w';\n                printf(\"%c\", c);\n\n                c = '-';\n                if (ip->i_mode & 0010)\n                    c = 'x';\n                if (ip->i_mode & 02000)\n                    c = 's';\n                printf(\"%c\", c);\n\n                c = '-';\n                if (ip->i_mode & 0004)\n                    c = 'r';\n                printf(\"%c\", c);\n\n                c = '-';\n                if (ip->i_mode & 0002)\n                    c = 'w';\n                printf(\"%c\", c);\n\n                c = '-';\n                if (ip->i_mode & 0001)\n                    c = 'x';\n                if (ip->i_mode & 01000)\n                    c = 't';\n                printf(\"%c\", c);\n\n                printf(\" %5u\", ip->i_number);\n                printf(\" %8lu\", ip->i_size);\n\n                tmp = localtime(&ip->i_mtime);\n                strftime(tbuf, 20, \"%Y-%m-%d %H:%M\", tmp);\n\n                printf(\" %s\", tbuf);\n                printf(\" %s\", dp->d_name);\n#if 0\n                printf(\"\\n    \");\n\n                for (i=0; i<NADDR; i++) {\n                    printf(\"%d \", ip->i_addr[i]);\n                }\n#endif\n                printf(\"\\n\");\n\n\n                d += dp->d_reclen;\n                free(ip);\n            }\n            free(buf);\n        }\n    }\n    free(in);\n}\n\nstruct inode *adddirectory(struct filesystem *f, struct inode *in, char *name)\n{\n    char *buf;\n    char *d;\n    struct direct *dp;\n    int bno;\n    struct inode *ip;\n    ino_t ino = fsinodealloc(f);\n    int rem;\n\n    int i = 0;\n\n    if (!(in->i_mode & IFDIR)) {\n        errno = ENOTDIR;\n        return NULL;\n    }\n\n    if (ino == 0) {\n        printf(\"Could not allocate inode\\n\");\n        errno = ENOSPC;\n        return NULL;\n    }\n\n    // Create the new directory\n\n    bno = fsblockalloc(f);\n\n    if (bno == 0) {\n        errno = ENOSPC;\n        return NULL;\n    }\n\n    rem = DEV_BSIZE;\n    buf = malloc(DEV_BSIZE);\n    d = buf;\n\n    dp = (struct direct *)d;\n    dp->d_ino = ino;\n    dp->d_namlen = 1;\n    dp->d_name[0] = '.'; dp->d_name[1] = '\\0';\n    dp->d_reclen = DIRSIZ(dp);\n    rem -= dp->d_reclen;\n    d += dp->d_reclen;\n    dp = (struct direct *)d;\n    dp->d_ino = in->i_number;\n    dp->d_namlen = 2;\n    dp->d_name[0] = '.'; dp->d_name[1] = '.'; dp->d_name[2] = '\\0';\n    dp->d_reclen = rem;\n\n    fswriteblock(f, bno, buf);\n    free(buf);\n\n    ip = malloc(sizeof(struct inode));\n\n    for (i = 0; i < NADDR; i++)\n        ip->i_db[i] = 0;\n\n    ip->i_number = ino;\n    ip->i_db[0] = bno;\n    ip->i_mode = IFDIR | 0755;\n    ip->i_uid = 0;\n    ip->i_gid = 0;\n    ip->i_nlink = 2;\n    ip->i_size = DEV_BSIZE;\n    ip->i_atime = time(NULL);\n    ip->i_ctime = time(NULL);\n    ip->i_mtime = time(NULL);\n    fswriteinode(f, ip);\n\n    // insert the new directory into the parent\n\n    buf = fsreadblock(f, in->i_db[0]);\n    if (!buf) {\n        printf(\"Bad read\\n\");\n        errno = EIO;\n        return NULL;\n    } \n    \n    d = buf;\n    rem = DEV_BSIZE;\n    while ((d - buf) < DEV_BSIZE) {\n        dp = (struct direct *)d;\n        printf(\"inode %d (%d %d)\\n\", (int)dp->d_ino, (int)dp->d_reclen, sizeof(struct direct));\n        if (dp->d_reclen != DIRSIZ(dp)) {\n            if (dp->d_ino != 0) {\n                dp->d_reclen = DIRSIZ(dp);\n                rem -= dp->d_reclen;\n                d += dp->d_reclen;\n                dp = (struct direct *)d;\n            }\n            dp->d_ino = ino;\n            dp->d_namlen = strlen(name);\n            bcopy(name, dp->d_name, strlen(name));\n            dp->d_reclen = rem;\n            if (!fswriteblock(f, in->i_db[0], buf)) {\n                errno = EIO;\n                free(ip);\n                free(buf);\n                return NULL;\n            }\n            in->i_nlink++;\n            fswriteinode(f, in);\n            free(buf);\n            return ip;\n        }\n        i++;\n        rem -= dp->d_reclen;\n        d += dp->d_reclen;\n    }\n    free(ip);\n    free(buf);\n    errno = ENOSPC;\n    return NULL;\n}\n\nint umkdir(struct filesystem *f, char *path)\n{\n    struct inode *in;\n    struct inode *ip;\n    int sd;\n    int i;\n    char *p = strdup(path);\n    int ndir;\n    char **dirs = splitpath(p, &ndir);\n\n    in = inodebypartpath(f, path, &sd);\n\n    if (sd == ndir) {\n        if (in != f->root) {\n            free(in);\n        }\n        free(p);\n        free(dirs);\n        errno = EEXIST;\n        return 0;\n    }\n        \n    for (i = sd; i < ndir; i++)\n    {\n        ip = adddirectory(f, in, dirs[i]);\n        if (in != f->root) {\n            free(in);\n        }\n        if (!ip) {\n            free(p);\n            free(dirs);\n            return 0;\n        }\n        in = ip;\n    }\n    if (in != f->root) {\n        free(in);\n    }\n    free(p);\n    free(dirs);\n\n    return 1;\n}\n\nint uls(struct filesystem *f, char *path)\n{\n    struct inode *in;\n\n    in = inodebypath(f, path);\n    if (!in) {\n        errno = ENOENT;\n        return 0;\n    }\n    listdir(f, in->i_number);\n    if (in != f->root)\n        free(in);\n    return 1;\n}\n\nint uchmod(struct filesystem *f, char *path, int mode)\n{\n    struct inode *in;\n    char *p = strdup(path);\n    int ndir;\n    char **dirs = splitpath(p, &ndir);\n    free(p);\n    free(dirs);\n\n    in = inodebypath(f, path);\n\n    if (!in) {\n        errno = ENOENT;\n        return 0;\n    }\n\n    in->i_mode &= ~07777;\n    in->i_mode |= (mode & 07777);\n    fswriteinode(f, in);\n    free(in);\n    return 1;\n}\n        \nint uchown(struct filesystem *f, char *path, int uid)\n{\n    struct inode *in;\n    char *p = strdup(path);\n    int ndir;\n    char **dirs = splitpath(p, &ndir);\n    free(p);\n    free(dirs);\n\n    in = inodebypath(f, path);\n\n    if (!in) {\n        errno = ENOENT;\n        return 0;\n    }\n\n    in->i_uid = uid;\n    fswriteinode(f, in);\n    free(in);\n    return 1;\n}\n        \nint uchgrp(struct filesystem *f, char *path, int gid)\n{\n    struct inode *in;\n    char *p = strdup(path);\n    int ndir;\n    char **dirs = splitpath(p, &ndir);\n    free(p);\n    free(dirs);\n\n    in = inodebypath(f, path);\n\n    if (!in) {\n        errno = ENOENT;\n        return 0;\n    }\n\n    in->i_mode = gid;\n    fswriteinode(f, in);\n    free(in);\n    return 1;\n}\n\nint uftruncate(UFILE *file)\n{\n    return 1;\n}\n\nstruct inode *fscreatefile(struct filesystem *f, char *path)\n{\n    return NULL;\n}\n        \nUFILE *ufopen(struct filesystem *f, char *path, char *mode)\n{\n    UFILE *file = malloc(sizeof(UFILE));\n    file->f = f;\n    file->in = inodebypath(f, path);    \n    file->readoffset = 0;\n    file->writeoffset = 0;\n    file->perm = 0;\n\n    if (!strcmp(mode, \"r\")) {\n        if (!file->in) {\n            return 0;\n        }\n        file->readoffset = 0;\n        file->writeoffset = 0;\n        file->perm = O_RDONLY;\n    }\n\n    if (!strcmp(mode, \"r+\")) {\n        if (!file->in) {\n            return 0;\n        }\n        file->readoffset = 0;\n        file->writeoffset = 0;\n        file->perm = O_RDWR;\n    }\n\n    if (!strcmp(mode, \"w\")) {\n        if (!file->in) {\n            return 0;\n        }\n        uftruncate(file);\n        file->readoffset = 0;\n        file->writeoffset = 0;\n        file->perm = O_WRONLY;\n    }\n\n    if (!strcmp(mode, \"w+\")) {\n        if (!file->in) {\n            file->in = fscreatefile(f, path);\n        } else {\n            uftruncate(file);\n        }\n        file->readoffset = 0;\n        file->writeoffset = 0;\n        file->perm = O_RDWR;\n    }\n\n    if (!strcmp(mode, \"a\")) {\n        if (!file->in) {\n            file->in = fscreatefile(f, path);\n        }\n        file->readoffset = file->in->i_size;\n        file->writeoffset = file->in->i_size;\n        file->perm = O_WRONLY;\n    }\n\n    if (!strcmp(mode, \"a+\")) {\n        if (!file->in) {\n            file->in = fscreatefile(f, path);\n        }\n        file->readoffset = 0;\n        file->writeoffset = file->in->i_size;\n        file->perm = O_RDWR;\n    }\n\n    return file;\n}\n\nvoid ufclose(UFILE *f)\n{\n    if (f->in) {\n        free(f->in);\n    }\n    free(f);\n}\n\nint ufgetc(UFILE *f)\n{\n    unsigned char *buf;\n    int bno;\n    int offset;\n    unsigned int addr;\n    int c;\n    int *ib;\n\n    if (f->readoffset >= f->in->i_size) {\n        return EOF;\n    }\n    bno = f->readoffset / DEV_BSIZE;\n    offset = f->readoffset - (bno * DEV_BSIZE); \n\n    \n    if (bno < NADDR-3) {\n        addr = f->in->i_db[bno];\n    } else {\n        bno -= NADDR-3;\n        // First level indirect\n        if (bno < DEV_BSIZE / 4) {\n            buf = fsreadblock(f->f, f->in->i_db[NADDR-3]);\n            ib = (daddr_t *)buf;\n            addr = ib[bno];\n            free(buf);\n        } else {\n            bno -= (DEV_BSIZE / 4);\n            // Double indirect\n            if (bno < ((DEV_BSIZE / 4) * (DEV_BSIZE / 4))) {\n                buf = fsreadblock(f->f, f->in->i_db[NADDR-2]);\n                ib = (daddr_t *)buf;\n                addr = ib[bno / (DEV_BSIZE / 4)];\n                free(buf);\n                buf = fsreadblock(f->f, addr);\n                ib = (daddr_t *)buf;\n                addr = ib[bno - ((bno / (DEV_BSIZE / 4)) * (DEV_BSIZE / 4))];\n                free(buf);\n            } else {\n                // It gets horrible now - triple indirect.\n            }\n        }\n    }\n\n    buf = fsreadblock(f->f, addr);\n    if (!buf) {\n        return -EIO;\n    }\n    f->readoffset++;\n    c = buf[offset];\n    free(buf);\n    return c;\n}\n"
  },
  {
    "path": "tools/libufs/fs.c",
    "content": "#include <stdio.h>\n#include <fcntl.h>\n#include <unistd.h>\n#include <sys/types.h>\n#include <stdlib.h>\n#include <strings.h>\n#include <time.h>\n\n#include \"libufs.h\"\n\nvoid inodemap(void *buf)\n{\n    int i;\n    struct inode *in;\n\n    for (i = 0; i < INOPB; i++) {\n        in = (struct inode *)(buf + (i * sizeof(struct inode)));\n        printf(\"%lu\\n\", (unsigned long)in->i_number);\n    }\n}\n\n// Convert an array of direct structures into a filesysem block\n// representing a directory structure containing those direct\n// structures as the content\nint32_t makedir(struct direct *protodir, int entries, void *buf)\n{\n    char *cp;\n    int i, spcleft;\n\n    spcleft = DIRBLKSIZ;\n    for (cp = buf, i = 0; i < entries - 1; i++) {\n        protodir[i].d_reclen = DIRSIZ(&protodir[i]);\n        bcopy(&protodir[i], cp, protodir[i].d_reclen);\n        cp += protodir[i].d_reclen;\n        spcleft -= protodir[i].d_reclen;\n    }\n    protodir[i].d_reclen = spcleft;\n    bcopy(&protodir[i], cp, DIRSIZ(&protodir[i]));\n    for (i=0; i<entries; i++) {\n        printf(\"%d: %s inode %d namlen %d recsize %d\\n\",\n            i, protodir[i].d_name, protodir[i].d_ino, protodir[i].d_namlen, protodir[i].d_reclen);\n    }\n\n    return (DIRBLKSIZ);\n}\n\nvoid fssync(struct filesystem *f)\n{\n    fswriteblock(f, SUPERB, f->fs);\n}\n\nu_int32_t fsinodealloc(struct filesystem *f)\n{\n    u_int32_t ino;\n    // are there any known free inodes?\n    struct inode *in;\n    u_int32_t ninode = 0;\n\nbadino:\n    if (f->fs->fs_ninode > 0) {\n        ino = f->fs->fs_inode[--f->fs->fs_ninode];\n        // An inode number below ROOTINO is not valid.\n        if (ino <= ROOTINO) {\n            goto badino;\n        }\n\n        in = malloc(sizeof(struct inode));\n        bzero(in, sizeof(struct inode));\n        in->i_number = ino;\n        fswriteinode(f, in);\n        free(in);\n        f->fs->fs_tinode--;\n        fssync(f);\n        return ino;\n    }\n    // We couldn't get an inode, so we need to scrape the filesystem\n    // for more.\n\n    printf(\"Not able to get an inode - scraping\\n\");\n\n\n    // First, let's find a good inode for ourselves...\n    for (ino = ROOTINO+1; itod(ino) < f->fs->fs_isize; ino++) {\n        in = fsreadinode(f, ino);\n        if (in->i_mode == 0) {\n            bzero(in, sizeof(struct inode));\n            in->i_number = ino;\n            fswriteinode(f, in);\n            ninode = ino;\n            f->fs->fs_tinode--;\n            fssync(f);\n            free(in);\n            break;\n        }\n        free(in);\n    }\n\n    printf(\"Got inode %lu\\n\", (unsigned long)ninode);\n\n    // Did it work?\n    if (ninode == 0) {\n        printf(\"Error: out of inodes\\n\");\n        return 0;\n    }\n\n    // Now to find a free one.\n    for (ino = ninode+1; itod(ino) < f->fs->fs_isize; ino++) {\n        in = fsreadinode(f, ino);\n        if (in->i_mode == 0) {\n            f->fs->fs_inode[f->fs->fs_ninode++] = ino;\n            if (f->fs->fs_ninode == NICINOD)\n                break;\n        }\n    }\n\n    fssync(f);\n\n    return ninode;\n}\n\nint64_t fsblockalloc(struct filesystem *f)\n{\n    int64_t bno;\n\n    if (f->fs->fs_tfree == 0) {\n        printf(\"disk full\\n\");\n        return 0;\n    }\n \n    if (f->fs->fs_nfree == 0) {\n        printf(\"no free space and no scraping yet\\n\");\n        return 0;\n    }\n\n    f->fs->fs_tfree--;\n    bno = f->fs->fs_free[--f->fs->fs_nfree];\n    fssync(f);\n    return (bno);\n}\n\nvoid *fsreadblock(struct filesystem *f, int64_t bno)\n{\n    int n;\n    int64_t offset;\n\n    char *buf = malloc(DEV_BSIZE);\n    if (!buf) {\n        printf(\"Unable to allocate buffer!!!!!\\n\");\n        return NULL;\n    }\n\n    offset = (int64_t) bno*DEV_BSIZE;\n    if (lseek(f->fd, offset, 0) != offset) {\n        printf(\"lseek read error: %lu\\n\", (unsigned long)bno);\n        free(buf);\n        return NULL;\n    }\n    n = read(f->fd, buf, DEV_BSIZE);\n    if (n != DEV_BSIZE) {\n        printf(\"read error: %ld\\n\", (long)bno);\n        free(buf);\n        return NULL;\n    }\n    return buf;\n}\n\nint fswriteblock(struct filesystem *f, int64_t bno, void *buf)\n{\n    int n;\n    int64_t offset;\n\n    offset = (int64_t) bno*DEV_BSIZE;\n    if (lseek(f->fd, offset, 0) != offset) {\n        printf (\"lseek failed on block number %lu, offset=%lu\\n\", (unsigned long)bno, (unsigned long)offset);\n        return 0;\n    }\n    n = write(f->fd, buf, DEV_BSIZE);\n    if (n != DEV_BSIZE) {\n        printf(\"write error: %ld\\n\", (long)bno);\n        return 0;\n    }\n    return 1;\n}\n\nstruct inode *fsreadinode(struct filesystem *f, int64_t ino)\n{\n    char *buf;\n    struct inode *i;\n    int64_t off;\n    struct dinode *dp;\n    int n;\n\n    buf = fsreadblock(f, itod(ino));\n    if (!buf) {\n        printf(\"Failed reading inode block\\n\");\n        return NULL;\n    }\n\n    i = malloc(sizeof(struct inode));\n    off = itoo(ino);\n\n    dp = (struct dinode *)(buf + (sizeof(struct dinode) * off)); \n    i->i_number = ino;\n    i->i_ic1 = dp->di_icom1;\n    i->i_flags = dp->di_flags;\n    i->i_ic2 = dp->di_icom2;\n    for (n = 0; n < NADDR; n++)\n        i->i_addr[n] = dp->di_addr[n];\n    \n    free(buf);\n\n    return i;\n}\n\nint fswriteinode(struct filesystem *f, struct inode *ip)\n{\n    char *buf;\n    struct dinode *dp;\n    int64_t d;\n    int n;\n\n    d = itod(ip->i_number);\n    if (d >= f->fs->fs_isize) {\n        printf(\"ilist too small\\n\");\n        return 0;\n    }\n    buf = fsreadblock(f, d);\n    if (!buf) {\n        return 0;\n    }\n\n    dp = (struct dinode *)(buf + (itoo(ip->i_number) * sizeof(struct dinode)));\n\n    dp->di_icom1 = ip->i_ic1;\n    dp->di_flags = ip->i_flags;\n    dp->di_icom2 = ip->i_ic2;\n    for (n = 0; n < NADDR; n++)\n        dp->di_addr[n] = ip->i_addr[n];\n\n    if (!fswriteblock(f, d, buf)) {\n        free(buf);\n        return 0;\n    }\n    free(buf);\n    return 1;\n}\n\n\nvoid fsfreeblock(struct filesystem *f, int64_t bno)\n{\n    if (bno != 0)\n        f->fs->fs_tfree++;\n    if (f->fs->fs_nfree < NICFREE) {\n        f->fs->fs_free[f->fs->fs_nfree++] = bno;\n    }\n    fssync(f);\n}\n\nstruct filesystem *fsopen(char *filename)\n{\n    struct filesystem *f;\n    f = malloc(sizeof(struct filesystem));\n\n    f->fd = open(filename, O_RDWR);\n    if (!f->fd) {\n        free(f);\n        return NULL;\n    }\n\n    f->fs = (struct fs *)fsreadblock(f, SUPERB);\n    if (!f->fs) {\n        printf(\"%s: Bad superblock\\n\", filename);\n        free(f);\n        return NULL;\n    }\n      \n    f->root = fsreadinode(f, ROOTINO);\n    if (!f->root) {\n        printf(\"%s: Bad root directory\\n\", filename);\n        free(f->fs);\n        free(f);\n        return NULL;\n    }\n    return f;\n}\n\nvoid fsclose(struct filesystem *f)\n{\n    if (!f) \n        return;\n\n    if (f->fd) {\n        if (f->fs) {\n            fswriteblock(f, SUPERB, f->fs);\n        }\n        close(f->fd);\n    }\n\n    if (f->root)\n        free(f->root);\n\n    if (f->fs)\n        free(f->fs);\n    free(f);\n}\n\nvoid bfree(struct filesystem *f, int64_t bno)\n{\n    register int i;\n    struct fblk *fb = malloc(DEV_BSIZE);\n\n    if (bno != 0)\n        f->fs->fs_tfree++;\n    if (f->fs->fs_nfree >= NICFREE) {\n        fb->df_nfree = f->fs->fs_nfree;\n        for (i=0; i<NICFREE; i++)\n            fb->df_free[i] = f->fs->fs_free[i];\n        fswriteblock(f, bno, fb);\n        printf(\"Writing free list to %d\\n\", (int)bno);\n        f->fs->fs_nfree = 0;\n    }\n    f->fs->fs_free[f->fs->fs_nfree++] = bno;\n}\n\nvoid bflist(struct filesystem *f)\n{\n    struct inode in;\n    int64_t d;\n\n    bzero(&in, sizeof (in));\n    in.i_number = 1;        /* inode 1 is a historical hack */\n    in.i_mode = IFREG;\n    fswriteinode(f, &in);\n\n    bfree(f, (int64_t)0);\n        d = f->fs->fs_fsize;\n    while (--d >= f->fs->fs_isize + f->fs->fs_swapsz) {\n        bfree(f, d);\n    }\n    printf(\"Resultant free list size %d\\n\", f->fs->fs_nfree);\n}\n\nstruct filesystem *fsnew(char *filename, unsigned int blocks, unsigned int bpi)\n{\n    struct filesystem *f;\n    unsigned int i;\n    char *buffer;\n\n    f = malloc(sizeof(DEV_BSIZE));\n    \n    f->fd = open(filename, O_RDWR | O_TRUNC | O_CREAT, 0644);\n    if (!f->fd) {\n        free(f);\n        return NULL;\n    }\n\n    buffer = malloc(DEV_BSIZE);\n    bzero(buffer, DEV_BSIZE);\n\n    for (i=0; i<blocks; i++) {\n        fswriteblock(f, i, buffer);\n    }\n\n    free(buffer);\n\n    f->fs = malloc(DEV_BSIZE);\n    f->fs->fs_fsize = blocks;\n\n    fsformat(f, bpi);\n    return f;\n}\n\nint fsformat(struct filesystem *f, int bpi)\n{\n    unsigned int nino;\n    char *buffer = malloc(DEV_BSIZE);\n    unsigned int i;\n\n    nino = (f->fs->fs_fsize * DEV_BSIZE / bpi) / INOPB;\n    if (nino <= 0) {\n        nino = 1;\n    }\n\n    f->fs->fs_isize = nino+1;\n    f->fs->fs_swapsz = 0;\n    f->fs->fs_time = time(NULL);\n    f->fs->fs_magic1 = FSMAGIC1;\n    f->fs->fs_magic2 = FSMAGIC2;\n    f->fs->fs_tfree = 0;\n    f->fs->fs_tinode = 0;\n    f->fs->fs_ninode = 0;\n    f->fs->fs_nfree = 0;\n\n    bzero(buffer, DEV_BSIZE);\n\n    for (i = SUPERB+1; i != f->fs->fs_isize; i++) {\n        if (!fswriteblock(f, i, buffer)) {\n            close(f->fd);\n            free(f->fs);\n            free(buffer);\n            return 0;\n        }\n        f->fs->fs_tinode += INOPB;\n    }\n\n    bflist(f);\n\n    fsinit(f);\n\n    free(buffer);\n    return 1;\n}\n\nvoid fsinit(struct filesystem *f)\n{\n    int i;\n    struct inode node;\n    char *buf = malloc(DEV_BSIZE);\n    time_t utime;\n\n    struct direct lost_found_dir[] = {\n        { LOSTFOUNDINO, sizeof(struct direct), 1, \".\" },\n        { ROOTINO,      sizeof(struct direct), 2, \"..\" },\n        { 0,            DIRBLKSIZ,             0, \"\" },\n    };\n\n    struct direct root_dir[] = {\n        { ROOTINO,      sizeof(struct direct), 1,  \".\" },\n        { ROOTINO,      sizeof(struct direct), 2,  \"..\" },\n        { LOSTFOUNDINO, sizeof(struct direct), 10, \"lost+found\" },\n        { 0,            DIRBLKSIZ,             0, \"\" },\n    };\n\n    utime = time(NULL);\n\n    node.i_atime = utime;\n    node.i_mtime = utime;\n    node.i_ctime = utime;\n\n    makedir(lost_found_dir, 2, buf);\n    for (i = DIRBLKSIZ; i < DEV_BSIZE; i += DIRBLKSIZ)\n        bcopy(&lost_found_dir[2], &buf[i], DIRSIZ(&lost_found_dir[2]));\n\n    node.i_number = LOSTFOUNDINO;\n    node.i_mode = IFDIR | 0755;\n    node.i_nlink = 2;\n    node.i_size = DEV_BSIZE;\n    node.i_db[0] = fsblockalloc(f);\n\n    fswriteblock(f, node.i_db[0], buf);\n    fswriteinode(f, &node);\n\n    node.i_number = ROOTINO;\n    node.i_mode = IFDIR | 0755;\n    node.i_nlink = 3;\n    node.i_size = makedir(root_dir, 3, buf);\n    node.i_db[0] = fsblockalloc(f);\n\n    fswriteblock(f, node.i_db[0], buf);\n    fswriteinode(f, &node);\n\n    free(buf);\n}\n \n"
  },
  {
    "path": "tools/libufs/libufs.h",
    "content": "#ifndef _LIBUFS_H\n#define _LIBUFS_H\n\n#include <sys/types.h>\n\n#define dev_t int\n#define ino_t u_int\n#define time_t long\n\n#define DEV_BSIZE       1024                // Block size\n#define BPI             (16 * DEV_BSIZE)    // Bytes per inode\n#define ROOTINO         ((u_int)2)          // i number of all roots\n#define LOSTFOUNDINO    (ROOTINO + 1)       // i number of lost+found\n#define NICINOD         32      // number of superblock inodes \n#define NICFREE         200     // number of superblock free blocks \n#define MAXMNTLEN   28\n#define NSHIFT      8\n#define NMASK       0377L   \n#define MAXNAMLEN   63\n#define MAXSYMLINKS 8\n#define DEV_BMASK   (DEV_BSIZE-1)\n#define B_CLRBUF    0x01\n#define DEV_BSHIFT  10  \n#define DIRBLKSIZ   1024\n#define NINDIR      (DEV_BSIZE / sizeof(long))\n#define INOPB       16\n#define MAXPATHLEN  256\n#define FSMAGIC1    ('F' | 'S'<<8 | '<'<<16 | '<'<<24)\n#define FSMAGIC2    ('>' | '>'<<8 | 'F'<<16 | 'S'<<24)\n#define SUPERB      ((long)0)    /* block number of the super block */\n#define PINOD       10\n\n#define   dbtofsb(b)  ((long) (b))\n#define itod(x)     ((long)((((u_int)(x) + INOPB - 1) / INOPB)))\n#define itoo(x)     ((int)(((x) + INOPB - 1) % INOPB))\n#define DIRSIZ(dp) \\\n    ((((sizeof (struct direct) - (MAXNAMLEN+1)) + (dp)->d_namlen+1) + 3) &~ 3)\n#define blkoff(loc)     /* calculates (loc % fs->fs_bsize) */ \\\n    ((loc) & DEV_BMASK)\n#define lblkno(loc)     /* calculates (loc / fs->fs_bsize) */ \\\n    ((unsigned) (loc) >> DEV_BSHIFT)\n\n#define NDINIT(ndp,op,flags,namep) {\\\n    (ndp)->ni_nameiop = op | flags; \\\n    (ndp)->ni_dirp = namep; }\n\n\n#define roundup(x,y)    ((((x)+((y)-1))/(y))*(y))\n#define LOOKUP      0   /* perform name lookup only */\n#define CREATE      1   /* setup for file creation */\n#define DELETE      2   /* setup for file deletion */\n#define LOCKPARENT  0x10    /* see the top of namei */\n#define NOCACHE     0x20    /* name must not be left in cache */\n#define FOLLOW      0x40    /* follow symbolic links */\n#define NOFOLLOW    0x0 /* don't follow symbolic links (pseudo) */\n\n#define B_READ      0x00001     /* read when I/O occurs */\n#define B_ERROR     0x00004     /* transaction aborted */\n\n\nstruct  fs\n{\n    u_int   fs_magic1;      /* magic word */\n    u_int   fs_isize;       /* first block after i-list */\n    u_int   fs_fsize;       /* size in blocks of entire volume */\n    u_int   fs_swapsz;      /* size in blocks of swap area */\n    int fs_nfree;       /* number of addresses in fs_free */\n    daddr_t fs_free [NICFREE];  /* free block list */\n    int fs_ninode;      /* number of inodes in fs_inode */\n    ino_t   fs_inode [NICINOD]; /* free inode list */\n    int     fs_flock;       /* lock during free list manipulation */\n    int     fs_fmod;        /* super block modified flag */\n    int     fs_ilock;       /* lock during i-list manipulation */\n    int     fs_ronly;       /* mounted read-only flag */\n    time_t  fs_time;        /* last super block update */\n    u_int   fs_tfree;       /* total free blocks */\n    ino_t   fs_tinode;      /* total free inodes */\n    char    fs_fsmnt [MAXMNTLEN];   /* ordinary file mounted on */\n    ino_t   fs_lasti;       /* start place for circular search */\n    ino_t   fs_nbehind;     /* est # free inodes before s_lasti */\n    u_int   fs_flags;       /* mount time flags */\n    u_int   fs_magic2;      /* magic word */\n/* actually longer */\n};\n\n\nstruct  fblk {\n    int df_nfree;       /* number of addresses in df_free */\n    daddr_t df_free [NICFREE];  /* free block list */\n};\n\nstruct  direct {\n    ino_t   d_ino;          /* inode number of entry */\n    u_short d_reclen;       /* length of this record */\n    u_short d_namlen;       /* length of string in d_name */\n    char    d_name[MAXNAMLEN+1];    /* name must be no longer than this */\n};\n\n#define NDADDR  4           /* direct addresses in inode */\n#define NIADDR  3           /* indirect addresses in inode */\n#define NADDR   (NDADDR + NIADDR)   /* total addresses in inode */\n\nstruct icommon1 {\n    u_short ic_mode;        /* mode and type of file */\n    u_short ic_nlink;       /* number of links to file */\n    uid_t   ic_uid;         /* owner's user id */\n    gid_t   ic_gid;         /* owner's group id */\n    off_t   ic_size;        /* number of bytes in file */\n};\n\nstruct icommon2 {\n    time_t  ic_atime;       /* time last accessed */\n    time_t  ic_mtime;       /* time last modified */\n    time_t  ic_ctime;       /* time created */\n};\n\nstruct inode {\n    struct inode    *i_chain[2];    /* must be first */\n    u_int       i_flag;\n    u_int       i_count;    /* reference count */\n    dev_t       i_dev;      /* device where inode resides */\n    ino_t       i_number;   /* i number, 1-to-1 with device address */\n    u_int       i_id;       /* unique identifier */\n    struct fs       *i_fs;      /* file sys associated with this inode */\n    union {\n        struct {\n            u_short I_shlockc;  /* count of shared locks */\n            u_short I_exlockc;  /* count of exclusive locks */\n        } i_l;\n        struct  proc *I_rsel;   /* pipe read select */\n    } i_un0;\n    union {\n        struct  proc *I_wsel;   /* pipe write select */\n    } i_un1;\n    union {\n        daddr_t I_addr[NADDR];      /* normal file/directory */\n        struct {\n            daddr_t I_db[NDADDR];   /* normal file/directory */\n            daddr_t I_ib[NIADDR];\n        } i_f;\n        struct {\n            /*\n             * the dummy field is here so that the de/compression\n             * part of the iget/iput routines works for special\n             * files.\n             */\n            u_int   I_dummy;\n            dev_t   I_rdev;     /* dev type */\n        } i_d;\n    } i_un2;\n    union {\n        daddr_t if_lastr;       /* last read (read-ahead) */\n        struct  {\n            struct inode  *if_freef; /* free list forward */\n            struct inode **if_freeb; /* free list back */\n        } i_fr;\n    } i_un3;\n    struct icommon1 i_ic1;\n    u_int   i_flags;            /* user changeable flags */\n    struct icommon2 i_ic2;\n};\n\nstruct dinode {\n    struct  icommon1 di_icom1;\n    daddr_t di_addr[NADDR];     /* 7 block addresses 4 bytes each */\n    u_int   di_reserved[1];     /* pad of 4 to make total size 64 */\n    u_int   di_flags;\n    struct  icommon2 di_icom2;\n};\n\nstruct nameidata {\n    caddr_t ni_dirp;        /* pathname pointer */\n    short   ni_nameiop;     /* see below */\n    short   ni_error;       /* error return if any */\n    off_t   ni_endoff;      /* end of useful stuff in directory */\n    struct  inode *ni_pdir;     /* inode of parent directory of dirp */\n    struct  inode *ni_ip;       /* inode of dirp */\n    off_t   ni_offset;      /* offset in directory */\n    u_short ni_count;       /* offset of open slot (off_t?) */\n    struct  direct ni_dent;     /* current directory entry */\n};\n\n#define i_mode      i_ic1.ic_mode\n#define i_nlink     i_ic1.ic_nlink\n#define i_uid       i_ic1.ic_uid\n#define i_gid       i_ic1.ic_gid\n#define i_size      i_ic1.ic_size\n#define i_shlockc   i_un0.i_l.I_shlockc\n#define i_exlockc   i_un0.i_l.I_exlockc\n#define i_rsel      i_un0.I_rsel\n#define i_wsel      i_un1.I_wsel\n#define i_db        i_un2.i_f.I_db\n#define i_ib        i_un2.i_f.I_ib\n#define i_atime     i_ic2.ic_atime\n#define i_mtime     i_ic2.ic_mtime\n#define i_ctime     i_ic2.ic_ctime\n#define i_rdev      i_un2.i_d.I_rdev\n#define i_addr      i_un2.I_addr\n#define i_dummy     i_un2.i_d.I_dummy\n#define i_lastr     i_un3.if_lastr\n#define i_forw      i_chain[0]\n#define i_back      i_chain[1]\n#define i_freef     i_un3.i_fr.if_freef\n#define i_freeb     i_un3.i_fr.if_freeb\n\n#define di_ic1      di_icom1\n#define di_ic2      di_icom2\n#define di_mode     di_ic1.ic_mode\n#define di_nlink    di_ic1.ic_nlink\n#define di_uid      di_ic1.ic_uid\n#define di_gid      di_ic1.ic_gid\n#define di_size     di_ic1.ic_size\n#define di_atime    di_ic2.ic_atime\n#define di_mtime    di_ic2.ic_mtime\n#define di_ctime    di_ic2.ic_ctime\n/* i_flag */\n#define ILOCKED     0x1     /* inode is locked */\n#define IUPD        0x2     /* file has been modified */\n#define IACC        0x4     /* inode access time to be updated */\n#define IMOUNT      0x8     /* inode is mounted on */\n#define IWANT       0x10        /* some process waiting on lock */\n#define ITEXT       0x20        /* inode is pure text prototype */\n#define ICHG        0x40        /* inode has been changed */\n#define ISHLOCK     0x80        /* file has shared lock */\n#define IEXLOCK     0x100       /* file has exclusive lock */\n#define ILWAIT      0x200       /* someone waiting on file lock */\n#define IMOD        0x400       /* inode has been modified */\n#define IRENAME     0x800       /* inode is being renamed */\n#define IPIPE       0x1000      /* inode is a pipe */\n#define IRCOLL      0x2000      /* read select collision on pipe */\n#define IWCOLL      0x4000      /* write select collision on pipe */\n#define IXMOD       0x8000      /* inode is text, but impure (XXX) */\n\n/* i_mode */\n#define IFMT        0170000     /* type of file */\n#define IFCHR       0020000     /* character special */\n#define IFDIR       0040000     /* directory */\n#define IFBLK       0060000     /* block special */\n#define IFREG       0100000     /* regular */\n#define IFLNK       0120000     /* symbolic link */\n#define IFSOCK      0140000     /* socket */\n#define ISUID       04000       /* set user id on execution */\n#define ISGID       02000       /* set group id on execution */\n#define ISVTX       01000       /* save swapped text even after use */\n#define IREAD       0400        /* read, write, execute permissions */\n#define IWRITE      0200\n#define IEXEC       0100\n\n#define IUPDAT(ip, t1, t2, waitfor) { \\\n    if (ip->i_flag&(IUPD|IACC|ICHG|IMOD)) \\\n        iupdat(ip, t1, t2, waitfor); \\\n}\n\n#define ITIMES(ip, t1, t2) { \\\n    if ((ip)->i_flag&(IUPD|IACC|ICHG)) { \\\n        (ip)->i_flag |= IMOD; \\\n        if ((ip)->i_flag&IACC) \\\n            (ip)->i_atime = (t1)->tv_sec; \\\n        if ((ip)->i_flag&IUPD) \\\n            (ip)->i_mtime = (t2)->tv_sec; \\\n        if ((ip)->i_flag&ICHG) \\\n            (ip)->i_ctime = time.tv_sec; \\\n        (ip)->i_flag &= ~(IACC|IUPD|ICHG); \\\n    } \\\n}\n\nstruct bufhd\n{\n    int32_t b_flags;        /* see defines below */\n    struct  buf *b_forw, *b_back;   /* fwd/bkwd pointer in chain */\n};\n\nstruct buf\n{\n    int32_t b_flags;        /* see defines below */\n    struct  buf *b_forw, *b_back;   /* hash chain (2 way street) */\n    struct  buf *av_forw, *av_back; /* position on free list if not BUSY */\n#define b_actf  av_forw         /* alternate names for driver queue */\n#define b_actl  av_back         /*    head - isn't history wonderful */\n    u_int32_t   b_bcount;       /* transfer count */\n#define b_active b_bcount       /* driver queue head: drive active */\n    int32_t b_error;        /* returned after I/O */\n    dev_t   b_dev;          /* major+minor device name */\n    caddr_t b_addr;         /* core address */\n    long b_blkno;        /* block # on device */\n    u_int32_t   b_resid;        /* words not transferred after error */\n#define b_cylin b_resid         /* disksort */\n#define b_errcnt b_resid        /* while i/o in progress: # retries */\n};\n\n#define dotdot_ino  dtdt_ino\n#define dotdot_reclen   dtdt_rec\n#define dotdot_name dtdt_name\nstruct dirtemplate {\n    u_int   dot_ino;\n    u_short dot_reclen;\n    u_short dot_namlen;\n    char    dot_name[4];        /* must be multiple of 4 */\n    u_int   dotdot_ino;\n    u_short dotdot_reclen;\n    u_short dotdot_namlen;\n    char    dotdot_name[4];     /* ditto */\n};\n\nstruct filesystem {\n    int32_t fd;\n    struct fs *fs;\n    struct inode *root;\n};\n\n\nextern int32_t makedir(struct direct *protodir, int32_t entries, void *buf);\nextern void *fsreadblock(struct filesystem *f, int64_t bno);\nextern int32_t fsformat(struct filesystem *f, int32_t bpi);\nextern void fsinit(struct filesystem *f);\nextern struct filesystem *fsopen(char *filename);\nextern void fsclose(struct filesystem *f);\nextern struct filesystem *fsnew(char *filename, u_int32_t blocks, u_int32_t bpi);\nextern int32_t fsformat(struct filesystem *f, int32_t bpi);\nextern struct inode *fsreadinode(struct filesystem *f, int64_t ino);\nextern int32_t fswriteblock(struct filesystem *f, int64_t bno, void *buf);\nextern int32_t fswriteinode(struct filesystem *f, struct inode *ip);\nextern u_int32_t fsinodealloc(struct filesystem *f);\nextern int64_t fsblockalloc(struct filesystem *f);\nextern int32_t umkdir(struct filesystem *f, char *path);\nextern int uls(struct filesystem *f, char *path);\nextern int uchmod(struct filesystem *f, char *path, int mode);\nextern int uchown(struct filesystem *f, char *path, int uid);\nextern int uchgrp(struct filesystem *f, char *path, int gid);\nextern struct inode *inodebypath(struct filesystem *f, char *path);\n\n\ntypedef struct {\n    struct filesystem *f;\n    struct inode *in;\n    off_t readoffset;\n    off_t writeoffset;\n    int perm;\n} UFILE;\n\nextern char *getsetting(char *setting);\nextern void storesetting(char *setting, char *value);\nextern char **splitpath(char *path, int *ndir);\nextern void compresspath(char *path);\n\nextern UFILE *ufopen(struct filesystem *f, char *path, char *mode);\nextern void ufclose(UFILE *f);\nextern int ufgetc(UFILE *f);\n\n#endif\n"
  },
  {
    "path": "tools/libufs/set.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <string.h>\n\n#include \"libufs.h\"\n\nchar *getsetting(char *setting)\n{\n    FILE *f;\n    char *s = NULL;\n    char *home;\n    char temp[1024];\n    char sub[1024];\n    char fmt[1024];\n\n    home = getenv(\"HOME\");\n\n    sprintf(temp, \"%s/.libufs\", home);\n\n    f = fopen(temp, \"r\");\n    if (!f) {\n        return s;\n    }\n\n    sprintf(fmt, \"%s=%%s\", setting);\n\n    while (fgets(temp, 1024, f)) {\n        bzero(sub, 800);\n        if (sscanf(temp, fmt, sub)) {\n            s = strdup(sub);\n        }\n    }\n\n    fclose(f);\n    return s;\n}\n\nvoid storesetting(char *setting, char *value)\n{\n    FILE *f1;\n    FILE *f2;\n    char *home;\n    char temp1[1024];\n    char temp2[1024];\n\n    if (!setting) {\n        return;\n    }\n\n    home = getenv(\"HOME\");\n\n    sprintf(temp1, \"%s/.libufs.bak\", home);\n    sprintf(temp2, \"%s/.libufs\", home);\n    \n    rename(temp2, temp1);\n\n    f1 = fopen(temp1, \"r\");\n    if (!f1) {\n        return;\n    }\n    f2 = fopen(temp2, \"w\");\n    if (!f2) {\n        fclose(f2);\n        return;\n    }\n\n    sprintf(temp2, \"%s=\", setting);\n\n    while (fgets(temp1, 1024, f1)) {\n        if (strncmp(temp1, temp2, strlen(temp2)) != 0) {\n            if (strlen(temp1) > 2) {\n                fprintf(f2, \"%s\", temp1);\n            }\n        }\n    }    \n\n    if (value) {\n        fprintf(f2, \"%s=%s\\n\", setting, value);\n    }\n    fclose(f1);\n    fclose(f2);\n}\n\n"
  },
  {
    "path": "tools/libufs/ucat.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n\n#include \"libufs.h\"\n\nint main(int argc, char *argv[])\n{\n    struct filesystem *f;\n    char path[1024];\n    char *image = getsetting(\"imagefile\");\n    UFILE *file;\n    int c;\n\n    if (!image) {\n        printf(\"Have you run ulogin?\\n\");\n        return 10;\n    }\n\n    char *cwd = getsetting(\"cwd\");\n    if (argc == 2) {\n        if (argv[1][0] == '/') {\n            sprintf(path, \"%s\", argv[1]);\n        } else {\n            sprintf(path, \"%s/%s\", cwd, argv[1]);\n        }\n    } else {\n        sprintf(path, \"%s\", cwd);\n    }\n    free(cwd);\n        \n    f = fsopen(image);\n    if (!f) {\n        printf(\"Unable to open %s\\n\", image);\n            fsclose(f);\n            free(image);\n            return(10);\n    }\n\n    file = ufopen(f, path, \"r\");\n    if (!file) {\n        printf(\"%s: not found\\n\", path);\n        fsclose(f);\n        free(image);\n        return(10);\n    }\n\n    while ((c = ufgetc(file)) != EOF) {\n        printf(\"%c\", c);\n    }\n\n    ufclose(file);\n\n    fsclose(f);\n    free(image);\n    return 0;\n}\n"
  },
  {
    "path": "tools/libufs/ucd.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n\n#include \"libufs.h\"\n\nint main(int argc, char *argv[])\n{\n    struct filesystem *f;\n    char *temp = malloc(1024);\n    char *image;\n\n    image = getsetting(\"imagefile\");\n\n    if (!image) {\n        printf(\"Have you run ulogin?\\n\");\n        return 10;\n    }\n\n    if (argc != 2) {\n        printf(\"Usage: %s <dir>\\n\", argv[0]);\n        free(image);\n        return 10;\n    }\n\n    f = fsopen(image);\n    if (!f) {\n        if(image) free(image);\n        return 10;\n    }\n\n    if (argv[1][0] == '/') {\n        if (!inodebypath(f, argv[1])) {\n            printf(\"%s not found\\n\", argv[1]);\n        } else {\n            storesetting(\"cwd\", argv[1]);\n        }\n        fsclose(f);\n        free(image);\n        return 0;\n    } else {\n        char *cwd = getsetting(\"cwd\");\n        if (!cwd) {\n            sprintf(temp, \"/%s\", argv[1]);\n        } else {\n            sprintf(temp, \"%s/%s\", cwd, argv[1]);\n            compresspath(temp);\n            free(cwd);\n        }\n        if (!inodebypath(f, temp)) {\n            printf(\"%s not found\\n\", temp);\n        } else {\n            storesetting(\"cwd\", temp);\n        }\n        free(image);\n        fsclose(f);\n        return 0;\n    }\n    return 0;\n}\n"
  },
  {
    "path": "tools/libufs/uchgrp.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n\n#include \"libufs.h\"\n\nint main(int argc, char *argv[])\n{\n    struct filesystem *f;\n    int i;\n    int mode;\n    char temp[1024];\n    char *cwd;\n    char *fsname = getsetting(\"imagefile\");;\n\n    if (!fsname) {\n        printf(\"Have you run ulogin?\\n\");\n        return 10;\n    }\n\n    if (argc < 3) {\n        printf(\"Usage: %s <gid> <file> ...\\n\", argv[0]);\n        return 10;\n    }\n\n    sscanf(argv[1], \"%o\", &mode);\n        \n    f = fsopen(fsname);\n    if (!f) {\n        printf(\"Unable to open %s\\n\", fsname);\n        return 10;\n    }\n    cwd = getsetting(\"cwd\");\n    for (i = 2; i < argc; i++) {\n        if (argv[i][0] == '/') {\n            uchgrp(f, argv[i], mode);\n        } else {\n            if (!cwd) {\n                sprintf(temp, \"/%s\", argv[i]);\n            } else {\n                sprintf(temp, \"%s/%s\", cwd, argv[i]);\n            }\n            compresspath(temp);\n            uchgrp(f, temp, mode);\n        }\n    }\n    fsclose(f);\n    if (cwd)\n        free(cwd);\n    free(fsname);\n    return 0;\n}\n"
  },
  {
    "path": "tools/libufs/uchmod.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n\n#include \"libufs.h\"\n\nint main(int argc, char *argv[])\n{\n    struct filesystem *f;\n    int i;\n    int mode;\n    char temp[1024];\n    char *cwd;\n    char *fsname = getsetting(\"imagefile\");;\n\n    if (!fsname) {\n        printf(\"Have you run ulogin?\\n\");\n        return 10;\n    }\n\n    if (argc < 3) {\n        printf(\"Usage: %s <mode> <file> ...\\n\", argv[0]);\n        return 10;\n    }\n\n    sscanf(argv[1], \"%o\", &mode);\n        \n    f = fsopen(fsname);\n    if (!f) {\n        printf(\"Unable to open %s\\n\", fsname);\n        return 10;\n    }\n    cwd = getsetting(\"cwd\");\n    for (i = 2; i < argc; i++) {\n        if (argv[i][0] == '/') {\n            uchmod(f, argv[i], mode);\n        } else {\n            if (!cwd) {\n                sprintf(temp, \"/%s\", argv[i]);\n            } else {\n                sprintf(temp, \"%s/%s\", cwd, argv[i]);\n            }\n            compresspath(temp);\n            uchmod(f, temp, mode);\n        }\n    }\n    fsclose(f);\n    if (cwd)\n        free(cwd);\n    free(fsname);\n    return 0;\n}\n"
  },
  {
    "path": "tools/libufs/uchown.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n\n#include \"libufs.h\"\n\nint main(int argc, char *argv[])\n{\n    struct filesystem *f;\n    int i;\n    int mode;\n    char temp[1024];\n    char *cwd;\n    char *fsname = getsetting(\"imagefile\");;\n\n    if (!fsname) {\n        printf(\"Have you run ulogin?\\n\");\n        return 10;\n    }\n\n    if (argc < 3) {\n        printf(\"Usage: %s <uid> <file> ...\\n\", argv[0]);\n        return 10;\n    }\n\n    sscanf(argv[1], \"%o\", &mode);\n        \n    f = fsopen(fsname);\n    if (!f) {\n        printf(\"Unable to open %s\\n\", fsname);\n        return 10;\n    }\n    cwd = getsetting(\"cwd\");\n    for (i = 2; i < argc; i++) {\n        if (argv[i][0] == '/') {\n            uchown(f, argv[i], mode);\n        } else {\n            if (!cwd) {\n                sprintf(temp, \"/%s\", argv[i]);\n            } else {\n                sprintf(temp, \"%s/%s\", cwd, argv[i]);\n            }\n            compresspath(temp);\n            uchown(f, temp, mode);\n        }\n    }\n    fsclose(f);\n    if (cwd)\n        free(cwd);\n    free(fsname);\n    return 0;\n}\n"
  },
  {
    "path": "tools/libufs/ulogin.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include \"libufs.h\"\n\nint main(int argc, char *argv[])\n{\n    char *filename;\n    struct filesystem *f;\n    char fullpath[1024];\n    char cwd[800];\n\n    if (argc != 2) {\n        printf(\"Usage: %s <filename>\\n\", argv[0]);\n        return 10;\n    }\n\n    filename = argv[1];\n\n    f = fsopen(filename);\n    if (!f) {\n        printf(\"Unable to open %s\\n\", filename);\n        return 10;\n    }\n\n    if (filename[0] == '/') {\n        storesetting(\"imagefile\", filename);\n    } else {\n        getcwd(cwd,800);\n        sprintf(fullpath, \"%s/%s\", cwd, filename);\n        storesetting(\"imagefile\", fullpath);\n    }\n\n    storesetting(\"cwd\",\"/\");\n\n    return 0;\n}\n"
  },
  {
    "path": "tools/libufs/uls.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n\n#include \"libufs.h\"\n\nint main(int argc, char *argv[])\n{\n    struct filesystem *f;\n    char path[1024];\n    char *image = getsetting(\"imagefile\");\n\n    if (!image) {\n        printf(\"Have you run ulogin?\\n\");\n        return 10;\n    }\n\n    char *cwd = getsetting(\"cwd\");\n    if (argc == 2) {\n        if (argv[1][0] == '/') {\n            sprintf(path, \"%s\", argv[1]);\n        } else {\n            sprintf(path, \"%s/%s\", cwd, argv[1]);\n        }\n    } else {\n        sprintf(path, \"%s\", cwd);\n    }\n    free(cwd);\n        \n    f = fsopen(image);\n    if (!f) {\n        printf(\"Unable to open %s\\n\", image);\n    } else {\n        if (!uls(f, path)) {\n            printf(\"%s not found\\n\", path);\n        }\n    }\n    fsclose(f);\n    free(image);\n    return 0;\n}\n"
  },
  {
    "path": "tools/libufs/umkdir.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n\n#include \"libufs.h\"\n\nint main(int argc, char *argv[])\n{\n    struct filesystem *f;\n    int i;\n    char *image = getsetting(\"imagefile\");\n    char temp[1024];\n    char *cwd;\n\n    if (argc < 2) {\n        printf(\"Usage: %s <directory> ...\\n\", argv[0]);\n        return 10;\n    }\n        \n    f = fsopen(image);\n    if (!f) {\n        return 10;\n    }\n    cwd = getsetting(\"cwd\");\n    for (i = 1; i < argc; i++) {\n        if (argv[i][0] == '/') {\n            umkdir(f, argv[i]);\n        } else {\n            if (!cwd) {\n                sprintf(temp, \"/%s\", argv[i]);\n            } else {\n                sprintf(temp, \"%s/%s\", cwd, argv[i]);\n            }\n            compresspath(temp);\n            umkdir(f, temp);\n        }\n    }\n    if (cwd)\n        free(cwd);\n    free(image);\n    fsclose(f);\n    return 0;\n}\n"
  },
  {
    "path": "tools/libufs/umkfs.c",
    "content": "#include <stdio.h>\n#include <unistd.h>\n#include <stdlib.h>\n#include <sys/stat.h>\n\n#include \"libufs.h\"\n\nint main(int argc, char *argv[])\n{\n    struct stat sb;\n    int opt;\n    int blocks = 0;\n    int bpi = BPI;\n    struct filesystem *f;\n\n    while ((opt = getopt(argc, argv, \"i:b:\")) != -1) {\n        switch (opt) {\n        case 'i':\n            bpi = atoi(optarg);\n            break;\n        case 'b':\n            blocks = atoi(optarg);\n            break;\n        }\n    }\n\n    if (argc <= optind) {\n        printf(\"Usage: %s [-i bpi] [-b blocks] file\\n\", argv[0]);\n        printf(\"  Format an file image with a UFS filesystem\\n\");\n        return 10;\n    }\n\n    if (stat(argv[optind], &sb) != -1) {\n        f = fsopen(argv[optind]);\n        if (!f) {\n            printf(\"Error opening image file\\n\");\n            return 10;\n        }\n        f->fs->fs_fsize = sb.st_size / DEV_BSIZE;\n        fsformat(f, bpi);\n    } else {\n        f = fsnew(argv[optind], blocks, bpi);\n    }\n\n    fsclose(f);\n\n    return 0;\n}\n"
  },
  {
    "path": "tools/libufs/util.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <errno.h>\n#include <string.h>\n#include \"libufs.h\"\n\nvoid compresspath(char *path)\n{\n    char *work;\n    char *p, *q;\n    char **dirs;\n    int ndir;\n    int i,j;\n\n    // First, remove any double slashes\n\n    for (p = path; *(p+1); p++) {\n        while ((*p == '/') && (*(p+1) == '/')) {\n            for (q = p+1; *q; q++) {\n                *q = *(q+1);\n            }\n        }\n    }\n\n    // Now we need to split it all up and remove any single dots, and\n    // cd up any double dots.\n\n    work = strdup(path);\n\n    dirs = splitpath(work, &ndir);\n\n    for (i = 0; i < ndir; i++) {\n        if (!strcmp(dirs[i], \".\")) {\n            for (j = i; j < ndir-1; j++) {\n                dirs[j] = dirs[j+1];\n            }\n            ndir--;\n        }\n        if (!strcmp(dirs[i], \"..\")) {\n            for (j = i-1; j < ndir-1; j++) {\n                dirs[j] = dirs[j+1];\n            }\n            ndir--;\n            for (j = i-1; j < ndir-1; j++) {\n                dirs[j] = dirs[j+1];\n            }\n            ndir--;\n        }\n    }\n\n    sprintf(path, \"%s\", \"\");\n    for (i=0; i<ndir; i++) {\n        sprintf(path, \"%s/%s\", path, dirs[i]);\n    }\n\n    if (path[0] == '\\0') {\n        path[0] = '/';\n        path[1] = '\\0';\n    }\n    free(work);\n    free(dirs);\n}\n"
  },
  {
    "path": "tools/linux/README.md",
    "content": "# Linux Development Environment\n\nNote: These instructions are current as of Ubuntu 24.04.\n\nThis is the directory that maintains the development environment on Linux.\n\nRequired programs to build a complete DiscoBSD distribution are:\n  - Version control:        git\n  - Native compiler:        clang or gcc\n  - Utilities:              awk, bison, bmake, byacc, flex, gettext, groff\n  - Utilities:              mandoc, pkg-config, sed, sudo, unzip, zip\n  - Libraries:              libbsd, libelf, libfuse\n  - Cross compiler (ARM):   binutils and gcc arm-none-eabi rmprofile\n  - Cross debugger (ARM):   gdb arm-none-eabi or gdb multiarch\n  - Firmware loader (ARM):  dfu-util, openocd, stlink\n  - Cross compiler (MIPS):  binutils and gcc mips-elf\n  - Cross debugger (MIPS):  gdb mips-elf or gdb multiarch\n  - Firmware loader (MIPS): pic32prog\n\n## Setting up the Development Environment for Arm target\n\nAll components of the development environment are available as Packages.\n\nInformation about APT-based Package Management on Linux can be found at:\nhttps://wiki.debian.org/PackageManagement\n\nThese required utilities can be installed as Packages:\n  ```sh\n    $ apt install build-essential {binutils,gcc}-arm-none-eabi git sudo\n    $ apt install gdb-multiarch dfu-util openocd stlink-tools pkg-config\n    $ apt install bison bmake byacc flex gawk gettext-base gsed mandoc\n    $ apt install libbsd-dev libelf-dev libfuse-dev groff-base unzip zip\n  ```\n\nNote: So that `make gdb-ocd` works, create the following symlink on the host\n      system if `gdb-multiarch` is installed instead of `gdb-arm-none-eabi`:\n  ```sh\n    $ ln -s /usr/bin/gdb-multiarch /usr/bin/arm-none-eabi-gdb\n  ```\n\n## Setting up the Development Environment for MIPS target\n\nNote: These steps assume that all previous steps have been completed.\n\n### Toolchain: mips-elf-{binutils,gcc,gdb} GCC V4.8.1, Binutils V2.23.2\n\nBuild the MIPS toolchain from source, as described on page:\nhttps://web.archive.org/web/20200126100825/http://retrobsd.org/wiki/doku.php/doc/toolchain-mips\n\n### Binary Flash Downloader: pic32prog V2.1.57\n\nAvailable from:\nhttps://github.com/majenkotech/pic32prog-autotools/archive/refs/tags/2.1.57.zip\n"
  },
  {
    "path": "tools/openbsd/README.md",
    "content": "# OpenBSD Development Environment\n\nNote: These instructions are current as of OpenBSD 7.6.\n\nThis is the directory that maintains the development environment on OpenBSD.\n\nRequired programs to build a complete DiscoBSD distribution are:\n  - Version control:        git\n  - Native compiler:        clang or gcc\n  - Utilities:              awk, bison, bmake, byacc, flex, gettext, groff\n  - Utilities:              mandoc, pkg-config, sed, sudo, unzip, zip\n  - Libraries:              libbsd, libelf, libfuse\n  - Cross compiler (ARM):   binutils and gcc arm-none-eabi rmprofile\n  - Cross debugger (ARM):   gdb arm-none-eabi or gdb multiarch\n  - Firmware loader (ARM):  dfu-util, openocd, stlink\n  - Cross compiler (MIPS):  binutils and gcc mips-elf\n  - Cross debugger (MIPS):  gdb mips-elf or gdb multiarch\n  - Firmware loader (MIPS): pic32prog\n\n## Setting up the Development Environment for Arm target\n\nAll components of the development environment are available from the\nOpenBSD base system, the OpenBSD package system, or as a user-compiled\nOpenBSD port in the `mystuff` directory subtree.\n\nInformation about the OpenBSD Package System can be found at:\nhttps://www.openbsd.org/faq/faq15.html\n\nPackages need no setup.\n\nThese required utilities can be installed as Packages:\n  ```sh\n    $ pkg_add bison dfu-util elftoolchain gettext-runtime\n    $ pkg_add git groff openocd sudo unzip zip\n  ```\n\nThe remaining required utilities must be built as Ports.\n\nInformation about the OpenBSD Ports System can be found at:\nhttps://www.openbsd.org/faq/ports/ports.html\n\n1. Fetch and Install the Ports Collection:\n  ```sh\n    $ cd /tmp\n    $ ftp https://cdn.openbsd.org/pub/OpenBSD/$(uname -r)/ports.tar.gz\n    $ cd /usr\n    $ tar xzvf /tmp/ports.tar.gz\n  ```\n\n2. Add the Ports from this repo to the `/usr/ports/mystuff` directory:\n  ```sh\n    $ cd {where this repo is cloned}/tools/openbsd/ports\n    $ cp -R mystuff /usr/ports/\n  ```\n\n### Binary Flash Downloader, Port: STLink V1.8.0 (Optional)\n```sh\n  $ cd /usr/ports/mystuff/devel/stlink\n  $ sudo make\n  $ sudo make install\n```\n\n### Circuit Board Emulator, Port: QEMU (Cortex-M) V2.8.0-6-20190517 (Optional)\n```sh\n  $ cd /usr/ports/mystuff/emulators/qemu-arm\n  $ sudo make\n  $ sudo make install\n```\n\n### Meta-package Toolchain: arm-none-eabi-{binutils,gcc,gdb}\n\n#### Assembler, Package: Binutils V2.40, Configured for arm-none-eabi\n```sh\n  $ sudo pkg_add arm-none-eabi-binutils\n```\nNote: __DO NOT__ install the default OpenBSD `arm-none-eabi-gcc` Package.\n  It does not enable the `rmprofile` multilib, missing critical library files.\n  Instead, compile the custom-configured GCC port as outlined below.\n\n#### Compiler, Port: GCC, V12.2.0, Configured for arm-none-eabi rmprofile\n```sh\n  $ cd /usr/ports/mystuff/devel/arm-none-eabi/gcc\n  $ sudo make\n  $ sudo make install\n```\n\n#### Debugger, Port: GNU Debugger V12.1, Configured for arm-none-eabi\n```sh\n  $ cd /usr/ports/mystuff/devel/arm-none-eabi/gdb\n  $ sudo make\n  $ sudo make install\n```\n\nNote: The whole meta-package can be compiled and installed by one command:\n```sh\n  $ cd /usr/ports/mystuff/devel/arm-none-eabi\n  $ sudo make\n  $ sudo make install\n```\n\n## Setting up the Development Environment for MIPS target\n\nNote: These steps assume that all previous steps have been completed.\n\n### Meta-package Toolchain: mips-elf-{binutils,gcc}\n\n#### Assembler, Port: Binutils V2.40, Configured for mips-elf\n```sh\n  $ cd /usr/ports/mystuff/devel/mips-elf/binutils\n  $ sudo make\n  $ sudo make install\n```\n\n#### Compiler, Port: GCC V12.2.0, Configured for mips-elf\n```sh\n  $ cd /usr/ports/mystuff/devel/mips-elf/gcc\n  $ sudo make\n  $ sudo make install\n```\n\nNote: The whole meta-package can be compiled and installed by one command:\n```sh\n  $ cd /usr/ports/mystuff/devel/mips-elf\n  $ sudo make\n  $ sudo make install\n```\n"
  },
  {
    "path": "tools/openbsd/ports/devel/openocd/Makefile",
    "content": "COMMENT =\tOpen On-Chip Debugging\n\nDISTNAME =\topenocd-0.11.0\nCATEGORIES =\tdevel\nREVISION =\t0\n\nHOMEPAGE =\thttps://openocd.sourceforge.net/\n\n# GPLv2\nPERMIT_PACKAGE =\tYes\n\nWANTLIB += c ftdi1 hidapi-libusb iconv jim m pthread usb usb-1.0 util\n\nSITES =\t\t${SITE_SOURCEFORGE:=openocd/}\nEXTRACT_SUFX =\t.tar.bz2\n\nCONFIGURE_STYLE = gnu\nCONFIGURE_ARGS = --disable-werror \\\n\t\t--disable-wextra \\\n\t\t--enable-armjtagew \\\n\t\t--enable-at91rm9200 \\\n\t\t--enable-ep93xx \\\n\t\t--enable-ftdi \\\n\t\t--enable-jlink \\\n\t\t--enable-presto_libftdi \\\n\t\t--enable-rlink \\\n\t\t--enable-usbprog \\\n\t\t--enable-vsllink \\\n\t\t--enable-ulink \\\n\t\t--enable-stlink \\\n\t\t--enable-ti-icdi \\\n\t\t--enable-usb-blaster-2 \\\n\t\t--enable-usb-blaster \\\n\t\t--enable-osbdm \\\n\t\t--enable-opendous \\\n\t\t--enable-openjtag \\\n\t\t--enable-cmsis-dap \\\n\t\t--enable-presto \\\n\t\t--enable-aice \\\n\t\t--enable-buspirate \\\n\t\t--disable-internal-jimtcl \\\n\t\t--without-capstone\n\nCONFIGURE_ENV =\tCPPFLAGS=\"-I${LOCALBASE}/include -I${LOCALBASE}/include/jim\" \\\n\t\tLDFLAGS=\"-L${LOCALBASE}/lib -pthread\"\n\nLIB_DEPENDS =\tcomms/libhidapi \\\n\t\tdevel/libftdi1 \\\n\t\tdevel/libusb-compat \\\n\t\tlang/jimtcl>=0.75\n\nUSE_GMAKE =\tYes\n# Fails to link main.o and libopenocd.a properly resulting in undefined reference in the gdb_server.o\nUSE_LIBTOOL =\tgnu\n\n.include <bsd.port.mk>\n"
  },
  {
    "path": "tools/openbsd/ports/devel/openocd/distinfo",
    "content": "SHA256 (openocd-0.11.0.tar.bz2) = Q6POc0r/HTcGrYd5Op86U3HLDjV/D/0KFRZWsGs9Hn0=\nSIZE (openocd-0.11.0.tar.bz2) = 5699972\n"
  },
  {
    "path": "tools/openbsd/ports/devel/openocd/patches/patch-src_jtag_drivers_cmsis_dap_usb_hid_c",
    "content": "Index: src/jtag/drivers/cmsis_dap_usb_hid.c\n--- src/jtag/drivers/cmsis_dap_usb_hid.c.orig\n+++ src/jtag/drivers/cmsis_dap_usb_hid.c\n@@ -56,7 +56,7 @@ static int cmsis_dap_hid_open(struct cmsis_dap *dap, u\n \ttarget_vid = 0;\n \ttarget_pid = 0;\n \n-\tif (hid_init() != 0) {\n+\tif (hidapi_hid_init() != 0) {\n \t\tLOG_ERROR(\"unable to open HIDAPI\");\n \t\treturn ERROR_FAIL;\n \t}\n"
  },
  {
    "path": "tools/openbsd/ports/devel/openocd/patches/patch-src_jtag_drivers_nulink_usb_c",
    "content": "Index: src/jtag/drivers/nulink_usb.c\n--- src/jtag/drivers/nulink_usb.c.orig\n+++ src/jtag/drivers/nulink_usb.c\n@@ -1043,7 +1043,7 @@ static int nulink_usb_open(struct hl_interface_param_s\n \t\treturn ERROR_FAIL;\n \t}\n \n-\tif (hid_init() != 0) {\n+\tif (hidapi_hid_init() != 0) {\n \t\tLOG_ERROR(\"unable to open HIDAPI\");\n \t\treturn ERROR_FAIL;\n \t}\n"
  },
  {
    "path": "tools/openbsd/ports/devel/openocd/pkg/DESCR",
    "content": "OpenOCD is a Free and Open On-Chip Debugging, In-System Programming\nand Boundary-Scan Testing.\n"
  },
  {
    "path": "tools/openbsd/ports/devel/openocd/pkg/PLIST",
    "content": "@bin bin/openocd\n@info info/openocd.info\n@man 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ripts/target/sim3x.cfg\nshare/openocd/scripts/target/smp8634.cfg\nshare/openocd/scripts/target/snps_em_sk_fpga.cfg\nshare/openocd/scripts/target/snps_hsdk.cfg\nshare/openocd/scripts/target/spear3xx.cfg\nshare/openocd/scripts/target/stellaris.cfg\nshare/openocd/scripts/target/stm32f0x.cfg\nshare/openocd/scripts/target/stm32f1x.cfg\nshare/openocd/scripts/target/stm32f2x.cfg\nshare/openocd/scripts/target/stm32f3x.cfg\nshare/openocd/scripts/target/stm32f4x.cfg\nshare/openocd/scripts/target/stm32f7x.cfg\nshare/openocd/scripts/target/stm32g0x.cfg\nshare/openocd/scripts/target/stm32g4x.cfg\nshare/openocd/scripts/target/stm32h7x.cfg\nshare/openocd/scripts/target/stm32h7x_dual_bank.cfg\nshare/openocd/scripts/target/stm32l0.cfg\nshare/openocd/scripts/target/stm32l0_dual_bank.cfg\nshare/openocd/scripts/target/stm32l1.cfg\nshare/openocd/scripts/target/stm32l1x_dual_bank.cfg\nshare/openocd/scripts/target/stm32l4x.cfg\nshare/openocd/scripts/target/stm32l5x.cfg\nshare/openocd/scripts/target/stm32mp15x.cfg\nshare/openocd/scripts/target/stm32w108xx.cfg\nshare/openocd/scripts/target/stm32wbx.cfg\nshare/openocd/scripts/target/stm32wlx.cfg\nshare/openocd/scripts/target/stm32xl.cfg\nshare/openocd/scripts/target/stm8l.cfg\nshare/openocd/scripts/target/stm8l152.cfg\nshare/openocd/scripts/target/stm8s.cfg\nshare/openocd/scripts/target/stm8s003.cfg\nshare/openocd/scripts/target/stm8s103.cfg\nshare/openocd/scripts/target/stm8s105.cfg\nshare/openocd/scripts/target/str710.cfg\nshare/openocd/scripts/target/str730.cfg\nshare/openocd/scripts/target/str750.cfg\nshare/openocd/scripts/target/str912.cfg\nshare/openocd/scripts/target/swj-dp.tcl\nshare/openocd/scripts/target/swm050.cfg\nshare/openocd/scripts/target/test_reset_syntax_error.cfg\nshare/openocd/scripts/target/test_syntax_error.cfg\nshare/openocd/scripts/target/ti-ar7.cfg\nshare/openocd/scripts/target/ti-cjtag.cfg\nshare/openocd/scripts/target/ti_calypso.cfg\nshare/openocd/scripts/target/ti_cc13x0.cfg\nshare/openocd/scripts/target/ti_cc13x2.cfg\nshare/openocd/scripts/target/ti_cc26x0.cfg\nshare/openocd/scripts/target/ti_cc26x2.cfg\nshare/openocd/scripts/target/ti_cc3220sf.cfg\nshare/openocd/scripts/target/ti_cc32xx.cfg\nshare/openocd/scripts/target/ti_dm355.cfg\nshare/openocd/scripts/target/ti_dm365.cfg\nshare/openocd/scripts/target/ti_dm6446.cfg\nshare/openocd/scripts/target/ti_msp432.cfg\nshare/openocd/scripts/target/ti_rm4x.cfg\nshare/openocd/scripts/target/ti_tms570.cfg\nshare/openocd/scripts/target/ti_tms570ls20xxx.cfg\nshare/openocd/scripts/target/ti_tms570ls3137.cfg\nshare/openocd/scripts/target/tmpa900.cfg\nshare/openocd/scripts/target/tmpa910.cfg\nshare/openocd/scripts/target/tnetc4401.cfg\nshare/openocd/scripts/target/u8500.cfg\nshare/openocd/scripts/target/vybrid_vf6xx.cfg\nshare/openocd/scripts/target/xilinx_zynqmp.cfg\nshare/openocd/scripts/target/xmc1xxx.cfg\nshare/openocd/scripts/target/xmc4xxx.cfg\nshare/openocd/scripts/target/xmos_xs1-xau8a-10_arm.cfg\nshare/openocd/scripts/target/zynq_7000.cfg\nshare/openocd/scripts/target/к1879xб1я.cfg\nshare/openocd/scripts/test/\nshare/openocd/scripts/test/selftest.cfg\nshare/openocd/scripts/test/syntax1.cfg\nshare/openocd/scripts/tools/\nshare/openocd/scripts/tools/firmware-recovery.tcl\nshare/openocd/scripts/tools/memtest.tcl\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/Makefile",
    "content": "SUBDIR =\nSUBDIR += binutils\nSUBDIR += binutils,aarch64\nSUBDIR += gcc\nSUBDIR += gcc,aarch64\nSUBDIR += gdb\nSUBDIR += newlib\n\n.include <bsd.port.subdir.mk>\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/Makefile.inc",
    "content": "CONFIG?=\tarm-none-eabi\nPKGNAME?=\t${CONFIG}-${DISTNAME}\nFULLPKGNAME?=\t${PKGNAME}\nCATEGORIES+=\tdevel\n\n# GPLv3\n# For newlib: multiple copyrights, but basically BSD.\n#   See: ${PREFIX}/share/doc/newlib\nPERMIT_PACKAGE=\tYes\n\nCONFIGURE_STYLE=gnu\nCONFIGURE_ARGS+=--target=${CONFIG}  \\\n\t\t--disable-shared    \\\n\t\t--disable-nls\t    \\\n\t\t--disable-werror\n\nEXTRACT_SUFX?=\t.tar.xz\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/binutils/Makefile",
    "content": "COMMENT=\tbinutils for ${CONFIG} cross-development\n\nVERSION=\t\t2.40\nDISTNAME=\tbinutils-${VERSION}\n\nFLAVORS=\taarch64 arm\nFLAVOR?=\tarm\n\n.if \"${FLAVOR}\" == \"aarch64\"\nCONFIG=\t\taarch64-none-elf\n.elif \"${FLAVOR}\" == \"arm\"\nCONFIG=\t\tarm-none-eabi\n.else\nERRORS+=\t\"either aarch64 or arm FLAVOR should be set\"\n.endif\n\nHOMEPAGE=\thttps://www.gnu.org/software/binutils/\n\nWANTLIB=\tc z\n\nSITES=\t\t${SITE_GNU:=binutils/}\nDIST_SUBDIR=\tbinutils\n\nUSE_GMAKE=\tYes\nUSE_LIBTOOL=\tNo\n\nCONFIGURE_ARGS+=--enable-commonbfdlib=no \\\n\t\t--enable-interwork\t \\\n\t\t--enable-multilib\t\\\n\t\t--without-zstd\n\nSUBST_VARS +=\tCONFIG\n\n.include <bsd.port.mk>\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/binutils/distinfo",
    "content": "SHA256 (binutils/binutils-2.40.tar.xz) = D4pMJy1/F/Np3tEKSsoouOMEgo6VUm2kgrDMxN/J2OE=\nSIZE (binutils/binutils-2.40.tar.xz) = 25241484\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/binutils/patches/patch-bfd_Makefile_in",
    "content": "Index: bfd/Makefile.in\n--- bfd/Makefile.in.orig\n+++ bfd/Makefile.in\n@@ -266,7 +266,7 @@ am__v_texidevnull_ = $(am__v_texidevnull_@AM_DEFAULT_V\n am__v_texidevnull_0 = > /dev/null\n am__v_texidevnull_1 = \n am__dirstamp = $(am__leading_dot)dirstamp\n-INFO_DEPS = doc/bfd.info\n+INFO_DEPS =\n am__TEXINFO_TEX_DIR = $(srcdir)\n DVIS = doc/bfd.dvi\n PDFS = doc/bfd.pdf\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/binutils/patches/patch-binutils_Makefile_in",
    "content": "Index: binutils/Makefile.in\n--- binutils/Makefile.in.orig\n+++ binutils/Makefile.in\n@@ -404,7 +404,7 @@ AM_V_texidevnull = $(am__v_texidevnull_@AM_V@)\n am__v_texidevnull_ = $(am__v_texidevnull_@AM_DEFAULT_V@)\n am__v_texidevnull_0 = > /dev/null\n am__v_texidevnull_1 = \n-INFO_DEPS = doc/binutils.info\n+INFO_DEPS =\n am__TEXINFO_TEX_DIR = $(srcdir)\n DVIS = doc/binutils.dvi\n PDFS = doc/binutils.pdf\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/binutils/patches/patch-gas_Makefile_in",
    "content": "Index: gas/Makefile.in\n--- gas/Makefile.in.orig\n+++ gas/Makefile.in\n@@ -270,7 +270,7 @@ AM_V_texidevnull = $(am__v_texidevnull_@AM_V@)\n am__v_texidevnull_ = $(am__v_texidevnull_@AM_DEFAULT_V@)\n am__v_texidevnull_0 = > /dev/null\n am__v_texidevnull_1 = \n-INFO_DEPS = doc/as.info\n+INFO_DEPS =\n TEXINFO_TEX = $(top_srcdir)/../texinfo.tex\n am__TEXINFO_TEX_DIR = $(top_srcdir)/..\n DVIS = doc/as.dvi\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/binutils/patches/patch-gprof_Makefile_in",
    "content": "Index: gprof/Makefile.in\n--- gprof/Makefile.in.orig\n+++ gprof/Makefile.in\n@@ -217,7 +217,7 @@ AM_V_texidevnull = $(am__v_texidevnull_@AM_V@)\n am__v_texidevnull_ = $(am__v_texidevnull_@AM_DEFAULT_V@)\n am__v_texidevnull_0 = > /dev/null\n am__v_texidevnull_1 = \n-INFO_DEPS = gprof.info\n+INFO_DEPS =\n am__TEXINFO_TEX_DIR = $(srcdir)/../texinfo\n DVIS = gprof.dvi\n PDFS = gprof.pdf\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/binutils/patches/patch-ld_Makefile_in",
    "content": "Index: ld/Makefile.in\n--- ld/Makefile.in.orig\n+++ ld/Makefile.in\n@@ -301,7 +301,7 @@ AM_V_texidevnull = $(am__v_texidevnull_@AM_V@)\n am__v_texidevnull_ = $(am__v_texidevnull_@AM_DEFAULT_V@)\n am__v_texidevnull_0 = > /dev/null\n am__v_texidevnull_1 = \n-INFO_DEPS = ld.info\n+INFO_DEPS =\n am__TEXINFO_TEX_DIR = $(srcdir)/../texinfo\n DVIS = ld.dvi\n PDFS = ld.pdf\n@@ -1042,7 +1042,7 @@ libldtestplug4_la_SOURCES = testplug4.c\n libldtestplug4_la_CFLAGS = -g -O2\n libldtestplug4_la_LDFLAGS = -no-undefined -rpath /nowhere\n bfdplugindir = $(libdir)/bfd-plugins\n-bfdplugin_LTLIBRARIES = libdep.la\n+bfdplugin_LTLIBRARIES =\n libdep_la_SOURCES = libdep_plugin.c\n libdep_la_LDFLAGS = -no-undefined -rpath /nowhere -module -avoid-version\n libdep_la_LINK = $(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) \\\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/binutils/patches/patch-libctf_Makefile_in",
    "content": "Index: libctf/Makefile.in\n--- libctf/Makefile.in.orig\n+++ libctf/Makefile.in\n@@ -306,7 +306,7 @@ am__v_texidevnull_ = $(am__v_texidevnull_@AM_DEFAULT_V\n am__v_texidevnull_0 = > /dev/null\n am__v_texidevnull_1 = \n am__dirstamp = $(am__leading_dot)dirstamp\n-INFO_DEPS = doc/ctf-spec.info\n+INFO_DEPS =\n am__TEXINFO_TEX_DIR = $(srcdir)\n DVIS = doc/ctf-spec.dvi\n PDFS = doc/ctf-spec.pdf\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/binutils/patches/patch-libiberty_Makefile_in",
    "content": "Index: libiberty/Makefile.in\n--- libiberty/Makefile.in.orig\n+++ libiberty/Makefile.in\n@@ -376,7 +376,7 @@ libiberty.html : $(srcdir)/libiberty.texi $(TEXISRC)\n @MAINT@\techo stamp > stamp-functions\n \n INSTALL_DEST = @INSTALL_DEST@\n-install: install_to_$(INSTALL_DEST) install-subdir\n+install:\n install-strip: install\n \n .PHONY: install install-strip\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/binutils/patches/patch-libsframe_Makefile_in",
    "content": "Index: libsframe/Makefile.in\n--- libsframe/Makefile.in.orig\n+++ libsframe/Makefile.in\n@@ -276,7 +276,7 @@ AM_V_texidevnull = $(am__v_texidevnull_@AM_V@)\n am__v_texidevnull_ = $(am__v_texidevnull_@AM_DEFAULT_V@)\n am__v_texidevnull_0 = > /dev/null\n am__v_texidevnull_1 = \n-INFO_DEPS = doc/sframe-spec.info\n+INFO_DEPS =\n am__TEXINFO_TEX_DIR = $(srcdir)\n DVIS = doc/sframe-spec.dvi\n PDFS = doc/sframe-spec.pdf\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/binutils/pkg/DESCR",
    "content": "GNU Binutils collection, configured for the ${CONFIG} target.\n  * ld - the GNU linker.\n  * as - the GNU assembler.\n\nBut they also include:\n  * addr2line - Converts addresses into filenames and line numbers.\n  * ar - A utility for creating, modifying and extracting from\n    archives.\n  * c++filt - Filter to demangle encoded C++ symbols.\n  * gprof - Displays profiling information.\n  * nlmconv - Converts object code into an NLM.\n  * nm - Lists symbols from object files.\n  * objcopy - Copys and translates object files.\n  * objdump - Displays information from object files.\n  * ranlib - Generates an index to the contents of an archive.\n  * readelf - Displays information from any ELF format object file.\n  * size - Lists the section sizes of an object or archive file.\n  * strings - Lists printable strings from files.\n  * strip - Discards symbols.\n  * windres - A compiler for Windows resource files.\n\nMost of these programs use BFD, the Binary File Descriptor library, to\ndo low-level manipulation. Many of them also use the opcodes library\nto assemble and disassemble machine instructions.\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/binutils/pkg/PFRAG.aarch64",
    "content": "${CONFIG}/lib/\n${CONFIG}/lib/ldscripts/\n${CONFIG}/lib/ldscripts/aarch64elf.x\n${CONFIG}/lib/ldscripts/aarch64elf.xbn\n${CONFIG}/lib/ldscripts/aarch64elf.xc\n${CONFIG}/lib/ldscripts/aarch64elf.xce\n${CONFIG}/lib/ldscripts/aarch64elf.xd\n${CONFIG}/lib/ldscripts/aarch64elf.xdc\n${CONFIG}/lib/ldscripts/aarch64elf.xdce\n${CONFIG}/lib/ldscripts/aarch64elf.xde\n${CONFIG}/lib/ldscripts/aarch64elf.xdw\n${CONFIG}/lib/ldscripts/aarch64elf.xdwe\n${CONFIG}/lib/ldscripts/aarch64elf.xe\n${CONFIG}/lib/ldscripts/aarch64elf.xn\n${CONFIG}/lib/ldscripts/aarch64elf.xr\n${CONFIG}/lib/ldscripts/aarch64elf.xs\n${CONFIG}/lib/ldscripts/aarch64elf.xsc\n${CONFIG}/lib/ldscripts/aarch64elf.xsce\n${CONFIG}/lib/ldscripts/aarch64elf.xse\n${CONFIG}/lib/ldscripts/aarch64elf.xsw\n${CONFIG}/lib/ldscripts/aarch64elf.xswe\n${CONFIG}/lib/ldscripts/aarch64elf.xu\n${CONFIG}/lib/ldscripts/aarch64elf.xw\n${CONFIG}/lib/ldscripts/aarch64elf.xwe\n${CONFIG}/lib/ldscripts/aarch64elf32.x\n${CONFIG}/lib/ldscripts/aarch64elf32.xbn\n${CONFIG}/lib/ldscripts/aarch64elf32.xc\n${CONFIG}/lib/ldscripts/aarch64elf32.xce\n${CONFIG}/lib/ldscripts/aarch64elf32.xd\n${CONFIG}/lib/ldscripts/aarch64elf32.xdc\n${CONFIG}/lib/ldscripts/aarch64elf32.xdce\n${CONFIG}/lib/ldscripts/aarch64elf32.xde\n${CONFIG}/lib/ldscripts/aarch64elf32.xdw\n${CONFIG}/lib/ldscripts/aarch64elf32.xdwe\n${CONFIG}/lib/ldscripts/aarch64elf32.xe\n${CONFIG}/lib/ldscripts/aarch64elf32.xn\n${CONFIG}/lib/ldscripts/aarch64elf32.xr\n${CONFIG}/lib/ldscripts/aarch64elf32.xs\n${CONFIG}/lib/ldscripts/aarch64elf32.xsc\n${CONFIG}/lib/ldscripts/aarch64elf32.xsce\n${CONFIG}/lib/ldscripts/aarch64elf32.xse\n${CONFIG}/lib/ldscripts/aarch64elf32.xsw\n${CONFIG}/lib/ldscripts/aarch64elf32.xswe\n${CONFIG}/lib/ldscripts/aarch64elf32.xu\n${CONFIG}/lib/ldscripts/aarch64elf32.xw\n${CONFIG}/lib/ldscripts/aarch64elf32.xwe\n${CONFIG}/lib/ldscripts/aarch64elf32b.x\n${CONFIG}/lib/ldscripts/aarch64elf32b.xbn\n${CONFIG}/lib/ldscripts/aarch64elf32b.xc\n${CONFIG}/lib/ldscripts/aarch64elf32b.xce\n${CONFIG}/lib/ldscripts/aarch64elf32b.xd\n${CONFIG}/lib/ldscripts/aarch64elf32b.xdc\n${CONFIG}/lib/ldscripts/aarch64elf32b.xdce\n${CONFIG}/lib/ldscripts/aarch64elf32b.xde\n${CONFIG}/lib/ldscripts/aarch64elf32b.xdw\n${CONFIG}/lib/ldscripts/aarch64elf32b.xdwe\n${CONFIG}/lib/ldscripts/aarch64elf32b.xe\n${CONFIG}/lib/ldscripts/aarch64elf32b.xn\n${CONFIG}/lib/ldscripts/aarch64elf32b.xr\n${CONFIG}/lib/ldscripts/aarch64elf32b.xs\n${CONFIG}/lib/ldscripts/aarch64elf32b.xsc\n${CONFIG}/lib/ldscripts/aarch64elf32b.xsce\n${CONFIG}/lib/ldscripts/aarch64elf32b.xse\n${CONFIG}/lib/ldscripts/aarch64elf32b.xsw\n${CONFIG}/lib/ldscripts/aarch64elf32b.xswe\n${CONFIG}/lib/ldscripts/aarch64elf32b.xu\n${CONFIG}/lib/ldscripts/aarch64elf32b.xw\n${CONFIG}/lib/ldscripts/aarch64elf32b.xwe\n${CONFIG}/lib/ldscripts/aarch64elfb.x\n${CONFIG}/lib/ldscripts/aarch64elfb.xbn\n${CONFIG}/lib/ldscripts/aarch64elfb.xc\n${CONFIG}/lib/ldscripts/aarch64elfb.xce\n${CONFIG}/lib/ldscripts/aarch64elfb.xd\n${CONFIG}/lib/ldscripts/aarch64elfb.xdc\n${CONFIG}/lib/ldscripts/aarch64elfb.xdce\n${CONFIG}/lib/ldscripts/aarch64elfb.xde\n${CONFIG}/lib/ldscripts/aarch64elfb.xdw\n${CONFIG}/lib/ldscripts/aarch64elfb.xdwe\n${CONFIG}/lib/ldscripts/aarch64elfb.xe\n${CONFIG}/lib/ldscripts/aarch64elfb.xn\n${CONFIG}/lib/ldscripts/aarch64elfb.xr\n${CONFIG}/lib/ldscripts/aarch64elfb.xs\n${CONFIG}/lib/ldscripts/aarch64elfb.xsc\n${CONFIG}/lib/ldscripts/aarch64elfb.xsce\n${CONFIG}/lib/ldscripts/aarch64elfb.xse\n${CONFIG}/lib/ldscripts/aarch64elfb.xsw\n${CONFIG}/lib/ldscripts/aarch64elfb.xswe\n${CONFIG}/lib/ldscripts/aarch64elfb.xu\n${CONFIG}/lib/ldscripts/aarch64elfb.xw\n${CONFIG}/lib/ldscripts/aarch64elfb.xwe\n${CONFIG}/lib/ldscripts/armelf.x\n${CONFIG}/lib/ldscripts/armelf.xbn\n${CONFIG}/lib/ldscripts/armelf.xc\n${CONFIG}/lib/ldscripts/armelf.xce\n${CONFIG}/lib/ldscripts/armelf.xd\n${CONFIG}/lib/ldscripts/armelf.xdc\n${CONFIG}/lib/ldscripts/armelf.xdce\n${CONFIG}/lib/ldscripts/armelf.xde\n${CONFIG}/lib/ldscripts/armelf.xdw\n${CONFIG}/lib/ldscripts/armelf.xdwe\n${CONFIG}/lib/ldscripts/armelf.xe\n${CONFIG}/lib/ldscripts/armelf.xn\n${CONFIG}/lib/ldscripts/armelf.xr\n${CONFIG}/lib/ldscripts/armelf.xs\n${CONFIG}/lib/ldscripts/armelf.xsc\n${CONFIG}/lib/ldscripts/armelf.xsce\n${CONFIG}/lib/ldscripts/armelf.xse\n${CONFIG}/lib/ldscripts/armelf.xsw\n${CONFIG}/lib/ldscripts/armelf.xswe\n${CONFIG}/lib/ldscripts/armelf.xu\n${CONFIG}/lib/ldscripts/armelf.xw\n${CONFIG}/lib/ldscripts/armelf.xwe\n${CONFIG}/lib/ldscripts/armelfb.x\n${CONFIG}/lib/ldscripts/armelfb.xbn\n${CONFIG}/lib/ldscripts/armelfb.xc\n${CONFIG}/lib/ldscripts/armelfb.xce\n${CONFIG}/lib/ldscripts/armelfb.xd\n${CONFIG}/lib/ldscripts/armelfb.xdc\n${CONFIG}/lib/ldscripts/armelfb.xdce\n${CONFIG}/lib/ldscripts/armelfb.xde\n${CONFIG}/lib/ldscripts/armelfb.xdw\n${CONFIG}/lib/ldscripts/armelfb.xdwe\n${CONFIG}/lib/ldscripts/armelfb.xe\n${CONFIG}/lib/ldscripts/armelfb.xn\n${CONFIG}/lib/ldscripts/armelfb.xr\n${CONFIG}/lib/ldscripts/armelfb.xs\n${CONFIG}/lib/ldscripts/armelfb.xsc\n${CONFIG}/lib/ldscripts/armelfb.xsce\n${CONFIG}/lib/ldscripts/armelfb.xse\n${CONFIG}/lib/ldscripts/armelfb.xsw\n${CONFIG}/lib/ldscripts/armelfb.xswe\n${CONFIG}/lib/ldscripts/armelfb.xu\n${CONFIG}/lib/ldscripts/armelfb.xw\n${CONFIG}/lib/ldscripts/armelfb.xwe\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/binutils/pkg/PFRAG.arm",
    "content": "@pkgpath devel/arm-none-eabi/binutils,\n${CONFIG}/lib/\n${CONFIG}/lib/ldscripts/\n${CONFIG}/lib/ldscripts/armelf.x\n${CONFIG}/lib/ldscripts/armelf.xbn\n${CONFIG}/lib/ldscripts/armelf.xc\n${CONFIG}/lib/ldscripts/armelf.xce\n${CONFIG}/lib/ldscripts/armelf.xd\n${CONFIG}/lib/ldscripts/armelf.xdc\n${CONFIG}/lib/ldscripts/armelf.xdce\n${CONFIG}/lib/ldscripts/armelf.xde\n${CONFIG}/lib/ldscripts/armelf.xdw\n${CONFIG}/lib/ldscripts/armelf.xdwe\n${CONFIG}/lib/ldscripts/armelf.xe\n${CONFIG}/lib/ldscripts/armelf.xn\n${CONFIG}/lib/ldscripts/armelf.xr\n${CONFIG}/lib/ldscripts/armelf.xs\n${CONFIG}/lib/ldscripts/armelf.xsc\n${CONFIG}/lib/ldscripts/armelf.xsce\n${CONFIG}/lib/ldscripts/armelf.xse\n${CONFIG}/lib/ldscripts/armelf.xsw\n${CONFIG}/lib/ldscripts/armelf.xswe\n${CONFIG}/lib/ldscripts/armelf.xu\n${CONFIG}/lib/ldscripts/armelf.xw\n${CONFIG}/lib/ldscripts/armelf.xwe\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/binutils/pkg/PLIST",
    "content": "%%aarch64%%\n%%arm%%\n${CONFIG}/\n${CONFIG}/bin/\n@bin ${CONFIG}/bin/ar\n@bin ${CONFIG}/bin/as\n@bin ${CONFIG}/bin/ld\n@bin ${CONFIG}/bin/ld.bfd\n@bin ${CONFIG}/bin/nm\n@bin ${CONFIG}/bin/objcopy\n@bin ${CONFIG}/bin/objdump\n@bin ${CONFIG}/bin/ranlib\n@bin ${CONFIG}/bin/readelf\n@bin ${CONFIG}/bin/strip\n@bin bin/${CONFIG}-addr2line\n@bin bin/${CONFIG}-ar\n@bin bin/${CONFIG}-as\n@bin bin/${CONFIG}-c++filt\n@bin bin/${CONFIG}-elfedit\n@bin bin/${CONFIG}-gprof\n@bin bin/${CONFIG}-ld\n@bin bin/${CONFIG}-ld.bfd\n@bin bin/${CONFIG}-nm\n@bin bin/${CONFIG}-objcopy\n@bin bin/${CONFIG}-objdump\n@bin bin/${CONFIG}-ranlib\n@bin bin/${CONFIG}-readelf\n@bin bin/${CONFIG}-size\n@bin bin/${CONFIG}-strings\n@bin bin/${CONFIG}-strip\n@man man/man1/${CONFIG}-addr2line.1\n@man man/man1/${CONFIG}-ar.1\n@man man/man1/${CONFIG}-as.1\n@man man/man1/${CONFIG}-c++filt.1\n@man man/man1/${CONFIG}-dlltool.1\n@man man/man1/${CONFIG}-elfedit.1\n@man man/man1/${CONFIG}-gprof.1\n@man man/man1/${CONFIG}-ld.1\n@man man/man1/${CONFIG}-nm.1\n@man man/man1/${CONFIG}-objcopy.1\n@man man/man1/${CONFIG}-objdump.1\n@man man/man1/${CONFIG}-ranlib.1\n@man man/man1/${CONFIG}-readelf.1\n@man man/man1/${CONFIG}-size.1\n@man man/man1/${CONFIG}-strings.1\n@man man/man1/${CONFIG}-strip.1\n@man man/man1/${CONFIG}-windmc.1\n@man man/man1/${CONFIG}-windres.1\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gcc/Makefile",
    "content": "BROKEN-powerpc64 = fails to apply patches/vecstep-*\nBROKEN-arm =\tspins CPU more than 12h building gcc-12.2.0/libgcc/libgcc2.c\n\nCOMMENT=\tgcc for ${CONFIG} cross-development\n\nVERSION=\t12.2.0\nDISTNAME=\tgcc-${VERSION}\nPKGNAME=\t${CONFIG}-gcc-${VERSION}\nREVISION=\t2\n\nUSE_NOEXECONLY=\tYes\n\nFLAVORS=\taarch64 arm\nFLAVOR?=\tarm\n\n.if \"${FLAVOR}\" == \"aarch64\"\nCONFIG=\t\taarch64-none-elf\nMULTILIB=\tdefault\n.elif \"${FLAVOR}\" == \"arm\"\nCONFIG=\t\tarm-none-eabi\nMULTILIB=\trmprofile\n.else\nERRORS+=\t\"either aarch64 or arm FLAVOR should be set\"\n.endif\n\nSUBST_VARS+=\tVERSION CONFIG\n\nWANTLIB=\tc m ${COMPILER_LIBCXX} gmp mpfr mpc pthread\nDIST_SUBDIR=\tgcc\n\nCOMPILER =\tbase-clang ports-gcc base-gcc\n\nSITES=\t\t${SITE_GCC:=releases/gcc-$(VERSION)/}\n\n.if ${MACHINE_ARCH} == \"powerpc64\"\nPATCH_LIST =\tpatch-* vecstep-*\n.endif\n\nBUILD_DEPENDS+=\tdevel/bison\t\t\\\n\t\t${RUN_DEPENDS}\nLIB_DEPENDS=\tdevel/mpfr devel/libmpc\n\n.if ${FLAVOR:Maarch64}\nBUILD_DEPENDS+=\tdevel/arm-none-eabi/binutils,aarch64\nRUN_DEPENDS=\tdevel/arm-none-eabi/binutils,aarch64\n.elif ${FLAVOR:Marm}\nBUILD_DEPENDS+=\tdevel/arm-none-eabi/binutils,arm\nRUN_DEPENDS=\tdevel/arm-none-eabi/binutils,arm\n.else\nERRORS+=\t\"either aarch64 or arm FLAVOR should be set\"\n.endif\n\nLANGS=\t\tc,c++\n\nCONFIGURE_ARGS+=--enable-languages=${LANGS}\t\\\n\t\t--enable-multilib\t\t\\\n\t\t--with-multilib-list=${MULTILIB}\\\n\t\t--enable-interwork\t\t\\\n\t\t--with-gmp=${LOCALBASE}\t\t\\\n\t\t--with-newlib\t\t\t\\\n\t\t--disable-libcc1\t\t\\\n\t\t--enable-cpp\t\t\t\\\n\t\t--without-isl\t\t\t\\\n\t\t--without-zstd\nCONFIGURE_ENV=\tCPPFLAGS=\"${CPPFLAGS} -I${LOCALBASE}/include\" \\\n\t\tLDFLAGS=\"-L${LOCALBASE}/lib\"\n\n# Avoid build failure when lang/gcc/8 is installed whose ansidecl.h misses these\nCPPFLAGS +=\t-DATTRIBUTE_NONSTRING= -DATTRIBUTE_RESULT_SIZE_1=\nCPPFLAGS +=\t-DATTRIBUTE_RESULT_SIZE_2= -DATTRIBUTE_RESULT_SIZE_1_2=\nCPPFLAGS +=\t-DATTRIBUTE_WARN_UNUSED_RESULT=\n\nSEPARATE_BUILD=\tYes\nUSE_GMAKE=\tYes\nYACC=\t\tbison\n\npost-install:\n\tchown -R ${SHAREOWN}:${SHAREGRP} \\\n\t\t${PREFIX}/lib/gcc/${CONFIG}/${VERSION}/\n\n.include <bsd.port.mk>\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gcc/distinfo",
    "content": "SHA256 (gcc/gcc-12.2.0.tar.xz) = 5UnPnPNZSgDie2WJ1DItcOByDN0hPzm+tBgeBpJiMP8=\nSIZE (gcc/gcc-12.2.0.tar.xz) = 84645292\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gcc/patches/patch-Makefile_in",
    "content": "Index: Makefile.in\n--- Makefile.in.orig\n+++ Makefile.in\n@@ -1116,29 +1116,8 @@ configure-host:  \\\n     maybe-configure-libctf\n .PHONY: configure-target\n configure-target:  \\\n-    maybe-configure-target-libstdc++-v3 \\\n-    maybe-configure-target-libsanitizer \\\n-    maybe-configure-target-libvtv \\\n-    maybe-configure-target-liboffloadmic \\\n-    maybe-configure-target-libssp \\\n     maybe-configure-target-newlib \\\n-    maybe-configure-target-libgcc \\\n-    maybe-configure-target-libbacktrace \\\n-    maybe-configure-target-libquadmath \\\n-    maybe-configure-target-libgfortran \\\n-    maybe-configure-target-libobjc \\\n-    maybe-configure-target-libgo \\\n-    maybe-configure-target-libphobos \\\n-    maybe-configure-target-libtermcap \\\n-    maybe-configure-target-winsup \\\n-    maybe-configure-target-libgloss \\\n-    maybe-configure-target-libffi \\\n-    maybe-configure-target-zlib \\\n-    maybe-configure-target-rda \\\n-    maybe-configure-target-libada \\\n-    maybe-configure-target-libgomp \\\n-    maybe-configure-target-libitm \\\n-    maybe-configure-target-libatomic\n+    maybe-configure-target-libgcc\n \n # The target built for a native non-bootstrap build.\n .PHONY: all\n@@ -1296,47 +1275,10 @@ all-host: maybe-all-libctf\n \n .PHONY: all-target\n \n-@if target-libstdc++-v3-no-bootstrap\n-all-target: maybe-all-target-libstdc++-v3\n-@endif target-libstdc++-v3-no-bootstrap\n-@if target-libsanitizer-no-bootstrap\n-all-target: maybe-all-target-libsanitizer\n-@endif target-libsanitizer-no-bootstrap\n-@if target-libvtv-no-bootstrap\n-all-target: maybe-all-target-libvtv\n-@endif target-libvtv-no-bootstrap\n-all-target: maybe-all-target-liboffloadmic\n-all-target: maybe-all-target-libssp\n all-target: maybe-all-target-newlib\n @if target-libgcc-no-bootstrap\n all-target: maybe-all-target-libgcc\n @endif target-libgcc-no-bootstrap\n-@if target-libbacktrace-no-bootstrap\n-all-target: maybe-all-target-libbacktrace\n-@endif target-libbacktrace-no-bootstrap\n-all-target: maybe-all-target-libquadmath\n-all-target: maybe-all-target-libgfortran\n-all-target: maybe-all-target-libobjc\n-all-target: maybe-all-target-libgo\n-@if target-libphobos-no-bootstrap\n-all-target: maybe-all-target-libphobos\n-@endif target-libphobos-no-bootstrap\n-all-target: maybe-all-target-libtermcap\n-all-target: maybe-all-target-winsup\n-all-target: maybe-all-target-libgloss\n-all-target: maybe-all-target-libffi\n-@if target-zlib-no-bootstrap\n-all-target: maybe-all-target-zlib\n-@endif target-zlib-no-bootstrap\n-all-target: maybe-all-target-rda\n-all-target: maybe-all-target-libada\n-@if target-libgomp-no-bootstrap\n-all-target: maybe-all-target-libgomp\n-@endif target-libgomp-no-bootstrap\n-all-target: maybe-all-target-libitm\n-@if target-libatomic-no-bootstrap\n-all-target: maybe-all-target-libatomic\n-@endif target-libatomic-no-bootstrap\n \n # Do a target for all the subdirectories.  A ``make do-X'' will do a\n # ``make X'' in all subdirectories (because, in general, there is a\n@@ -1409,29 +1351,8 @@ info-host: maybe-info-libctf\n \n .PHONY: info-target\n \n-info-target: maybe-info-target-libstdc++-v3\n-info-target: maybe-info-target-libsanitizer\n-info-target: maybe-info-target-libvtv\n-info-target: maybe-info-target-liboffloadmic\n-info-target: maybe-info-target-libssp\n info-target: maybe-info-target-newlib\n info-target: maybe-info-target-libgcc\n-info-target: maybe-info-target-libbacktrace\n-info-target: maybe-info-target-libquadmath\n-info-target: maybe-info-target-libgfortran\n-info-target: maybe-info-target-libobjc\n-info-target: maybe-info-target-libgo\n-info-target: maybe-info-target-libphobos\n-info-target: maybe-info-target-libtermcap\n-info-target: maybe-info-target-winsup\n-info-target: maybe-info-target-libgloss\n-info-target: maybe-info-target-libffi\n-info-target: maybe-info-target-zlib\n-info-target: maybe-info-target-rda\n-info-target: maybe-info-target-libada\n-info-target: maybe-info-target-libgomp\n-info-target: maybe-info-target-libitm\n-info-target: maybe-info-target-libatomic\n \n .PHONY: do-dvi\n do-dvi:\n@@ -1499,29 +1420,8 @@ dvi-host: maybe-dvi-libctf\n \n .PHONY: dvi-target\n \n-dvi-target: maybe-dvi-target-libstdc++-v3\n-dvi-target: maybe-dvi-target-libsanitizer\n-dvi-target: maybe-dvi-target-libvtv\n-dvi-target: maybe-dvi-target-liboffloadmic\n-dvi-target: maybe-dvi-target-libssp\n dvi-target: maybe-dvi-target-newlib\n dvi-target: maybe-dvi-target-libgcc\n-dvi-target: maybe-dvi-target-libbacktrace\n-dvi-target: maybe-dvi-target-libquadmath\n-dvi-target: maybe-dvi-target-libgfortran\n-dvi-target: maybe-dvi-target-libobjc\n-dvi-target: maybe-dvi-target-libgo\n-dvi-target: maybe-dvi-target-libphobos\n-dvi-target: maybe-dvi-target-libtermcap\n-dvi-target: maybe-dvi-target-winsup\n-dvi-target: maybe-dvi-target-libgloss\n-dvi-target: maybe-dvi-target-libffi\n-dvi-target: maybe-dvi-target-zlib\n-dvi-target: maybe-dvi-target-rda\n-dvi-target: maybe-dvi-target-libada\n-dvi-target: maybe-dvi-target-libgomp\n-dvi-target: maybe-dvi-target-libitm\n-dvi-target: maybe-dvi-target-libatomic\n \n .PHONY: do-pdf\n do-pdf:\n@@ -1589,29 +1489,8 @@ pdf-host: maybe-pdf-libctf\n \n .PHONY: pdf-target\n \n-pdf-target: maybe-pdf-target-libstdc++-v3\n-pdf-target: maybe-pdf-target-libsanitizer\n-pdf-target: maybe-pdf-target-libvtv\n-pdf-target: maybe-pdf-target-liboffloadmic\n-pdf-target: maybe-pdf-target-libssp\n pdf-target: maybe-pdf-target-newlib\n pdf-target: maybe-pdf-target-libgcc\n-pdf-target: maybe-pdf-target-libbacktrace\n-pdf-target: maybe-pdf-target-libquadmath\n-pdf-target: maybe-pdf-target-libgfortran\n-pdf-target: maybe-pdf-target-libobjc\n-pdf-target: maybe-pdf-target-libgo\n-pdf-target: maybe-pdf-target-libphobos\n-pdf-target: maybe-pdf-target-libtermcap\n-pdf-target: maybe-pdf-target-winsup\n-pdf-target: maybe-pdf-target-libgloss\n-pdf-target: maybe-pdf-target-libffi\n-pdf-target: maybe-pdf-target-zlib\n-pdf-target: maybe-pdf-target-rda\n-pdf-target: maybe-pdf-target-libada\n-pdf-target: maybe-pdf-target-libgomp\n-pdf-target: maybe-pdf-target-libitm\n-pdf-target: maybe-pdf-target-libatomic\n \n .PHONY: do-html\n do-html:\n@@ -1679,29 +1558,8 @@ html-host: maybe-html-libctf\n \n .PHONY: html-target\n \n-html-target: maybe-html-target-libstdc++-v3\n-html-target: maybe-html-target-libsanitizer\n-html-target: maybe-html-target-libvtv\n-html-target: maybe-html-target-liboffloadmic\n-html-target: maybe-html-target-libssp\n html-target: maybe-html-target-newlib\n html-target: maybe-html-target-libgcc\n-html-target: maybe-html-target-libbacktrace\n-html-target: maybe-html-target-libquadmath\n-html-target: maybe-html-target-libgfortran\n-html-target: maybe-html-target-libobjc\n-html-target: maybe-html-target-libgo\n-html-target: maybe-html-target-libphobos\n-html-target: maybe-html-target-libtermcap\n-html-target: maybe-html-target-winsup\n-html-target: maybe-html-target-libgloss\n-html-target: maybe-html-target-libffi\n-html-target: maybe-html-target-zlib\n-html-target: maybe-html-target-rda\n-html-target: maybe-html-target-libada\n-html-target: maybe-html-target-libgomp\n-html-target: maybe-html-target-libitm\n-html-target: maybe-html-target-libatomic\n \n .PHONY: do-TAGS\n do-TAGS:\n@@ -1769,29 +1627,8 @@ TAGS-host: maybe-TAGS-libctf\n \n .PHONY: TAGS-target\n \n-TAGS-target: maybe-TAGS-target-libstdc++-v3\n-TAGS-target: maybe-TAGS-target-libsanitizer\n-TAGS-target: maybe-TAGS-target-libvtv\n-TAGS-target: maybe-TAGS-target-liboffloadmic\n-TAGS-target: maybe-TAGS-target-libssp\n TAGS-target: maybe-TAGS-target-newlib\n TAGS-target: maybe-TAGS-target-libgcc\n-TAGS-target: maybe-TAGS-target-libbacktrace\n-TAGS-target: maybe-TAGS-target-libquadmath\n-TAGS-target: maybe-TAGS-target-libgfortran\n-TAGS-target: maybe-TAGS-target-libobjc\n-TAGS-target: maybe-TAGS-target-libgo\n-TAGS-target: maybe-TAGS-target-libphobos\n-TAGS-target: maybe-TAGS-target-libtermcap\n-TAGS-target: maybe-TAGS-target-winsup\n-TAGS-target: maybe-TAGS-target-libgloss\n-TAGS-target: maybe-TAGS-target-libffi\n-TAGS-target: maybe-TAGS-target-zlib\n-TAGS-target: maybe-TAGS-target-rda\n-TAGS-target: maybe-TAGS-target-libada\n-TAGS-target: maybe-TAGS-target-libgomp\n-TAGS-target: maybe-TAGS-target-libitm\n-TAGS-target: maybe-TAGS-target-libatomic\n \n .PHONY: do-install-info\n do-install-info:\n@@ -1859,29 +1696,8 @@ install-info-host: maybe-install-info-libctf\n \n .PHONY: install-info-target\n \n-install-info-target: maybe-install-info-target-libstdc++-v3\n-install-info-target: maybe-install-info-target-libsanitizer\n-install-info-target: maybe-install-info-target-libvtv\n-install-info-target: maybe-install-info-target-liboffloadmic\n-install-info-target: maybe-install-info-target-libssp\n install-info-target: maybe-install-info-target-newlib\n install-info-target: maybe-install-info-target-libgcc\n-install-info-target: maybe-install-info-target-libbacktrace\n-install-info-target: maybe-install-info-target-libquadmath\n-install-info-target: maybe-install-info-target-libgfortran\n-install-info-target: maybe-install-info-target-libobjc\n-install-info-target: maybe-install-info-target-libgo\n-install-info-target: maybe-install-info-target-libphobos\n-install-info-target: maybe-install-info-target-libtermcap\n-install-info-target: maybe-install-info-target-winsup\n-install-info-target: maybe-install-info-target-libgloss\n-install-info-target: maybe-install-info-target-libffi\n-install-info-target: maybe-install-info-target-zlib\n-install-info-target: maybe-install-info-target-rda\n-install-info-target: maybe-install-info-target-libada\n-install-info-target: maybe-install-info-target-libgomp\n-install-info-target: maybe-install-info-target-libitm\n-install-info-target: maybe-install-info-target-libatomic\n \n .PHONY: do-install-dvi\n do-install-dvi:\n@@ -2039,29 +1855,8 @@ install-pdf-host: maybe-install-pdf-libctf\n \n .PHONY: install-pdf-target\n \n-install-pdf-target: maybe-install-pdf-target-libstdc++-v3\n-install-pdf-target: maybe-install-pdf-target-libsanitizer\n-install-pdf-target: maybe-install-pdf-target-libvtv\n-install-pdf-target: maybe-install-pdf-target-liboffloadmic\n-install-pdf-target: maybe-install-pdf-target-libssp\n install-pdf-target: maybe-install-pdf-target-newlib\n install-pdf-target: maybe-install-pdf-target-libgcc\n-install-pdf-target: maybe-install-pdf-target-libbacktrace\n-install-pdf-target: maybe-install-pdf-target-libquadmath\n-install-pdf-target: maybe-install-pdf-target-libgfortran\n-install-pdf-target: maybe-install-pdf-target-libobjc\n-install-pdf-target: maybe-install-pdf-target-libgo\n-install-pdf-target: maybe-install-pdf-target-libphobos\n-install-pdf-target: maybe-install-pdf-target-libtermcap\n-install-pdf-target: maybe-install-pdf-target-winsup\n-install-pdf-target: maybe-install-pdf-target-libgloss\n-install-pdf-target: maybe-install-pdf-target-libffi\n-install-pdf-target: maybe-install-pdf-target-zlib\n-install-pdf-target: maybe-install-pdf-target-rda\n-install-pdf-target: maybe-install-pdf-target-libada\n-install-pdf-target: maybe-install-pdf-target-libgomp\n-install-pdf-target: maybe-install-pdf-target-libitm\n-install-pdf-target: maybe-install-pdf-target-libatomic\n \n .PHONY: do-install-html\n do-install-html:\n@@ -2129,29 +1924,8 @@ install-html-host: maybe-install-html-libctf\n \n .PHONY: install-html-target\n \n-install-html-target: maybe-install-html-target-libstdc++-v3\n-install-html-target: maybe-install-html-target-libsanitizer\n-install-html-target: maybe-install-html-target-libvtv\n-install-html-target: maybe-install-html-target-liboffloadmic\n-install-html-target: maybe-install-html-target-libssp\n install-html-target: maybe-install-html-target-newlib\n install-html-target: maybe-install-html-target-libgcc\n-install-html-target: maybe-install-html-target-libbacktrace\n-install-html-target: maybe-install-html-target-libquadmath\n-install-html-target: maybe-install-html-target-libgfortran\n-install-html-target: maybe-install-html-target-libobjc\n-install-html-target: maybe-install-html-target-libgo\n-install-html-target: maybe-install-html-target-libphobos\n-install-html-target: maybe-install-html-target-libtermcap\n-install-html-target: maybe-install-html-target-winsup\n-install-html-target: maybe-install-html-target-libgloss\n-install-html-target: maybe-install-html-target-libffi\n-install-html-target: maybe-install-html-target-zlib\n-install-html-target: maybe-install-html-target-rda\n-install-html-target: maybe-install-html-target-libada\n-install-html-target: maybe-install-html-target-libgomp\n-install-html-target: maybe-install-html-target-libitm\n-install-html-target: maybe-install-html-target-libatomic\n \n .PHONY: do-installcheck\n do-installcheck:\n@@ -2219,29 +1993,8 @@ installcheck-host: maybe-installcheck-libctf\n \n .PHONY: installcheck-target\n \n-installcheck-target: maybe-installcheck-target-libstdc++-v3\n-installcheck-target: maybe-installcheck-target-libsanitizer\n-installcheck-target: maybe-installcheck-target-libvtv\n-installcheck-target: maybe-installcheck-target-liboffloadmic\n-installcheck-target: maybe-installcheck-target-libssp\n installcheck-target: maybe-installcheck-target-newlib\n installcheck-target: maybe-installcheck-target-libgcc\n-installcheck-target: maybe-installcheck-target-libbacktrace\n-installcheck-target: maybe-installcheck-target-libquadmath\n-installcheck-target: maybe-installcheck-target-libgfortran\n-installcheck-target: maybe-installcheck-target-libobjc\n-installcheck-target: maybe-installcheck-target-libgo\n-installcheck-target: maybe-installcheck-target-libphobos\n-installcheck-target: maybe-installcheck-target-libtermcap\n-installcheck-target: maybe-installcheck-target-winsup\n-installcheck-target: maybe-installcheck-target-libgloss\n-installcheck-target: maybe-installcheck-target-libffi\n-installcheck-target: maybe-installcheck-target-zlib\n-installcheck-target: maybe-installcheck-target-rda\n-installcheck-target: maybe-installcheck-target-libada\n-installcheck-target: maybe-installcheck-target-libgomp\n-installcheck-target: maybe-installcheck-target-libitm\n-installcheck-target: maybe-installcheck-target-libatomic\n \n .PHONY: do-mostlyclean\n do-mostlyclean:\n@@ -2309,29 +2062,8 @@ mostlyclean-host: maybe-mostlyclean-libctf\n \n .PHONY: mostlyclean-target\n \n-mostlyclean-target: maybe-mostlyclean-target-libstdc++-v3\n-mostlyclean-target: maybe-mostlyclean-target-libsanitizer\n-mostlyclean-target: maybe-mostlyclean-target-libvtv\n-mostlyclean-target: maybe-mostlyclean-target-liboffloadmic\n-mostlyclean-target: maybe-mostlyclean-target-libssp\n mostlyclean-target: maybe-mostlyclean-target-newlib\n mostlyclean-target: maybe-mostlyclean-target-libgcc\n-mostlyclean-target: maybe-mostlyclean-target-libbacktrace\n-mostlyclean-target: maybe-mostlyclean-target-libquadmath\n-mostlyclean-target: maybe-mostlyclean-target-libgfortran\n-mostlyclean-target: maybe-mostlyclean-target-libobjc\n-mostlyclean-target: maybe-mostlyclean-target-libgo\n-mostlyclean-target: maybe-mostlyclean-target-libphobos\n-mostlyclean-target: maybe-mostlyclean-target-libtermcap\n-mostlyclean-target: maybe-mostlyclean-target-winsup\n-mostlyclean-target: maybe-mostlyclean-target-libgloss\n-mostlyclean-target: maybe-mostlyclean-target-libffi\n-mostlyclean-target: maybe-mostlyclean-target-zlib\n-mostlyclean-target: maybe-mostlyclean-target-rda\n-mostlyclean-target: maybe-mostlyclean-target-libada\n-mostlyclean-target: maybe-mostlyclean-target-libgomp\n-mostlyclean-target: maybe-mostlyclean-target-libitm\n-mostlyclean-target: maybe-mostlyclean-target-libatomic\n \n .PHONY: do-clean\n do-clean:\n@@ -2399,29 +2131,8 @@ clean-host: maybe-clean-libctf\n \n .PHONY: clean-target\n \n-clean-target: maybe-clean-target-libstdc++-v3\n-clean-target: maybe-clean-target-libsanitizer\n-clean-target: maybe-clean-target-libvtv\n-clean-target: maybe-clean-target-liboffloadmic\n-clean-target: maybe-clean-target-libssp\n clean-target: maybe-clean-target-newlib\n clean-target: maybe-clean-target-libgcc\n-clean-target: maybe-clean-target-libbacktrace\n-clean-target: maybe-clean-target-libquadmath\n-clean-target: maybe-clean-target-libgfortran\n-clean-target: maybe-clean-target-libobjc\n-clean-target: maybe-clean-target-libgo\n-clean-target: maybe-clean-target-libphobos\n-clean-target: maybe-clean-target-libtermcap\n-clean-target: maybe-clean-target-winsup\n-clean-target: maybe-clean-target-libgloss\n-clean-target: maybe-clean-target-libffi\n-clean-target: maybe-clean-target-zlib\n-clean-target: maybe-clean-target-rda\n-clean-target: maybe-clean-target-libada\n-clean-target: maybe-clean-target-libgomp\n-clean-target: maybe-clean-target-libitm\n-clean-target: maybe-clean-target-libatomic\n \n .PHONY: do-distclean\n do-distclean:\n@@ -2489,29 +2200,8 @@ distclean-host: maybe-distclean-libctf\n \n .PHONY: distclean-target\n \n-distclean-target: maybe-distclean-target-libstdc++-v3\n-distclean-target: maybe-distclean-target-libsanitizer\n-distclean-target: maybe-distclean-target-libvtv\n-distclean-target: maybe-distclean-target-liboffloadmic\n-distclean-target: maybe-distclean-target-libssp\n distclean-target: maybe-distclean-target-newlib\n distclean-target: maybe-distclean-target-libgcc\n-distclean-target: maybe-distclean-target-libbacktrace\n-distclean-target: maybe-distclean-target-libquadmath\n-distclean-target: maybe-distclean-target-libgfortran\n-distclean-target: maybe-distclean-target-libobjc\n-distclean-target: maybe-distclean-target-libgo\n-distclean-target: maybe-distclean-target-libphobos\n-distclean-target: maybe-distclean-target-libtermcap\n-distclean-target: maybe-distclean-target-winsup\n-distclean-target: maybe-distclean-target-libgloss\n-distclean-target: maybe-distclean-target-libffi\n-distclean-target: maybe-distclean-target-zlib\n-distclean-target: maybe-distclean-target-rda\n-distclean-target: maybe-distclean-target-libada\n-distclean-target: maybe-distclean-target-libgomp\n-distclean-target: maybe-distclean-target-libitm\n-distclean-target: maybe-distclean-target-libatomic\n \n .PHONY: do-maintainer-clean\n do-maintainer-clean:\n@@ -2579,29 +2269,8 @@ maintainer-clean-host: maybe-maintainer-clean-libctf\n \n .PHONY: maintainer-clean-target\n \n-maintainer-clean-target: maybe-maintainer-clean-target-libstdc++-v3\n-maintainer-clean-target: maybe-maintainer-clean-target-libsanitizer\n-maintainer-clean-target: maybe-maintainer-clean-target-libvtv\n-maintainer-clean-target: maybe-maintainer-clean-target-liboffloadmic\n-maintainer-clean-target: maybe-maintainer-clean-target-libssp\n maintainer-clean-target: maybe-maintainer-clean-target-newlib\n maintainer-clean-target: maybe-maintainer-clean-target-libgcc\n-maintainer-clean-target: maybe-maintainer-clean-target-libbacktrace\n-maintainer-clean-target: maybe-maintainer-clean-target-libquadmath\n-maintainer-clean-target: maybe-maintainer-clean-target-libgfortran\n-maintainer-clean-target: maybe-maintainer-clean-target-libobjc\n-maintainer-clean-target: maybe-maintainer-clean-target-libgo\n-maintainer-clean-target: maybe-maintainer-clean-target-libphobos\n-maintainer-clean-target: maybe-maintainer-clean-target-libtermcap\n-maintainer-clean-target: maybe-maintainer-clean-target-winsup\n-maintainer-clean-target: maybe-maintainer-clean-target-libgloss\n-maintainer-clean-target: maybe-maintainer-clean-target-libffi\n-maintainer-clean-target: maybe-maintainer-clean-target-zlib\n-maintainer-clean-target: maybe-maintainer-clean-target-rda\n-maintainer-clean-target: maybe-maintainer-clean-target-libada\n-maintainer-clean-target: maybe-maintainer-clean-target-libgomp\n-maintainer-clean-target: maybe-maintainer-clean-target-libitm\n-maintainer-clean-target: maybe-maintainer-clean-target-libatomic\n \n \n # Here are the targets which correspond to the do-X targets.\n@@ -2727,29 +2396,8 @@ check-host:  \\\n \n .PHONY: check-target\n check-target:  \\\n-    maybe-check-target-libstdc++-v3 \\\n-    maybe-check-target-libsanitizer \\\n-    maybe-check-target-libvtv \\\n-    maybe-check-target-liboffloadmic \\\n-    maybe-check-target-libssp \\\n     maybe-check-target-newlib \\\n-    maybe-check-target-libgcc \\\n-    maybe-check-target-libbacktrace \\\n-    maybe-check-target-libquadmath \\\n-    maybe-check-target-libgfortran \\\n-    maybe-check-target-libobjc \\\n-    maybe-check-target-libgo \\\n-    maybe-check-target-libphobos \\\n-    maybe-check-target-libtermcap \\\n-    maybe-check-target-winsup \\\n-    maybe-check-target-libgloss \\\n-    maybe-check-target-libffi \\\n-    maybe-check-target-zlib \\\n-    maybe-check-target-rda \\\n-    maybe-check-target-libada \\\n-    maybe-check-target-libgomp \\\n-    maybe-check-target-libitm \\\n-    maybe-check-target-libatomic\n+    maybe-check-target-libgcc\n \n do-check:\n \t@: $(MAKE); $(unstage)\n@@ -2919,29 +2567,8 @@ install-host:  \\\n \n .PHONY: install-target\n install-target:  \\\n-    maybe-install-target-libstdc++-v3 \\\n-    maybe-install-target-libsanitizer \\\n-    maybe-install-target-libvtv \\\n-    maybe-install-target-liboffloadmic \\\n-    maybe-install-target-libssp \\\n     maybe-install-target-newlib \\\n-    maybe-install-target-libgcc \\\n-    maybe-install-target-libbacktrace \\\n-    maybe-install-target-libquadmath \\\n-    maybe-install-target-libgfortran \\\n-    maybe-install-target-libobjc \\\n-    maybe-install-target-libgo \\\n-    maybe-install-target-libphobos \\\n-    maybe-install-target-libtermcap \\\n-    maybe-install-target-winsup \\\n-    maybe-install-target-libgloss \\\n-    maybe-install-target-libffi \\\n-    maybe-install-target-zlib \\\n-    maybe-install-target-rda \\\n-    maybe-install-target-libada \\\n-    maybe-install-target-libgomp \\\n-    maybe-install-target-libitm \\\n-    maybe-install-target-libatomic\n+    maybe-install-target-libgcc\n \n uninstall:\n \t@echo \"the uninstall target is not supported in this tree\"\n@@ -3029,30 +2656,8 @@ install-strip-host:  \\\n \n .PHONY: install-strip-target\n install-strip-target:  \\\n-    maybe-install-strip-target-libstdc++-v3 \\\n-    maybe-install-strip-target-libsanitizer \\\n-    maybe-install-strip-target-libvtv \\\n-    maybe-install-strip-target-liboffloadmic \\\n-    maybe-install-strip-target-libssp \\\n     maybe-install-strip-target-newlib \\\n-    maybe-install-strip-target-libgcc \\\n-    maybe-install-strip-target-libbacktrace \\\n-    maybe-install-strip-target-libquadmath \\\n-    maybe-install-strip-target-libgfortran \\\n-    maybe-install-strip-target-libobjc \\\n-    maybe-install-strip-target-libgo \\\n-    maybe-install-strip-target-libphobos \\\n-    maybe-install-strip-target-libtermcap \\\n-    maybe-install-strip-target-winsup \\\n-    maybe-install-strip-target-libgloss \\\n-    maybe-install-strip-target-libffi \\\n-    maybe-install-strip-target-zlib \\\n-    maybe-install-strip-target-rda \\\n-    maybe-install-strip-target-libada \\\n-    maybe-install-strip-target-libgomp \\\n-    maybe-install-strip-target-libitm \\\n-    maybe-install-strip-target-libatomic\n-\n+    maybe-install-strip-target-libgcc\n \n ### other supporting targets\n \n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gcc/patches/patch-gcc_Makefile_in",
    "content": "Index: gcc/Makefile.in\n--- gcc/Makefile.in.orig\n+++ gcc/Makefile.in\n@@ -3784,13 +3784,7 @@ install-driver: installdirs xgcc$(exeext)\n # Install the info files.\n # $(INSTALL_DATA) might be a relative pathname, so we can't cd into srcdir\n # to do the install.\n-install-info:: doc installdirs \\\n-\t$(DESTDIR)$(infodir)/cpp.info \\\n-\t$(DESTDIR)$(infodir)/gcc.info \\\n-\t$(DESTDIR)$(infodir)/cppinternals.info \\\n-\t$(DESTDIR)$(infodir)/gccinstall.info \\\n-\t$(DESTDIR)$(infodir)/gccint.info \\\n-\tlang.install-info\n+install-info::\n \n $(DESTDIR)$(infodir)/%.info: doc/%.info installdirs\n \trm -f $@\n@@ -3857,10 +3851,7 @@ install-man: lang.install-man \\\n \t$(DESTDIR)$(man1dir)/$(GCOV_INSTALL_NAME)$(man1ext) \\\n \t$(DESTDIR)$(man1dir)/$(GCOV_TOOL_INSTALL_NAME)$(man1ext) \\\n \t$(DESTDIR)$(man1dir)/$(GCOV_DUMP_INSTALL_NAME)$(man1ext) \\\n-\t$(if $(filter yes,@enable_lto@),$(DESTDIR)$(man1dir)/$(LTO_DUMP_INSTALL_NAME)$(man1ext)) \\\n-\t$(DESTDIR)$(man7dir)/fsf-funding$(man7ext) \\\n-\t$(DESTDIR)$(man7dir)/gfdl$(man7ext) \\\n-\t$(DESTDIR)$(man7dir)/gpl$(man7ext)\n+\t$(if $(filter yes,@enable_lto@),$(DESTDIR)$(man1dir)/$(LTO_DUMP_INSTALL_NAME)$(man1ext))\n \n $(DESTDIR)$(man7dir)/%$(man7ext): doc/%.7 installdirs\n \t-rm -f $@\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gcc/patches/patch-gcc_common_opt",
    "content": "Index: gcc/common.opt\n--- gcc/common.opt.orig\n+++ gcc/common.opt\n@@ -2017,7 +2017,7 @@ Common Var(flag_ivopts) Init(1) Optimization\n Optimize induction variables on trees.\n \n fjump-tables\n-Common Var(flag_jump_tables) Init(1) Optimization\n+Common Var(flag_jump_tables) Init(0) Optimization\n Use jump tables for sufficiently large switch statements.\n \n fbit-tests\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gcc/patches/patch-gcc_config_arm_elf_h",
    "content": "Index: gcc/config/arm/elf.h\n--- gcc/config/arm/elf.h.orig\n+++ gcc/config/arm/elf.h\n@@ -50,7 +50,7 @@\n \n #ifndef SUBTARGET_ASM_FLOAT_SPEC\n #define SUBTARGET_ASM_FLOAT_SPEC \"\\\n-%{mapcs-float:-mfloat}\"\n+%{mapcs-float:-mfloat} %{!mhard-float:-mfpu=softfpa} %{mhard-float:-mfpu=fpa}\"\n #endif\n \n #undef SUBSUBTARGET_EXTRA_SPECS\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gcc/patches/patch-gcc_config_host",
    "content": "Index: gcc/config.host\n--- gcc/config.host.orig\n+++ gcc/config.host\n@@ -99,8 +99,7 @@ case ${host} in\n esac\n \n case ${host} in\n-  aarch64*-*-freebsd* | aarch64*-*-linux* | aarch64*-*-fuchsia* |\\\n-  aarch64*-*-darwin*)\n+  aarch64*-*-*)\n     case ${target} in\n       aarch64*-*-*)\n \thost_extra_gcc_objs=\"driver-aarch64.o\"\n@@ -108,7 +107,7 @@ case ${host} in\n \t;;\n     esac\n     ;;\n-  arm*-*-freebsd* | arm*-*-netbsd* | arm*-*-linux* | arm*-*-fuchsia*)\n+  arm*-*-*)\n     case ${target} in\n       arm*-*-*)\n \thost_extra_gcc_objs=\"driver-arm.o\"\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gcc/patches/patch-gcc_configure",
    "content": "Index: gcc/configure\n--- gcc/configure.orig\n+++ gcc/configure\n@@ -32456,14 +32456,14 @@ if test \"$gcc_cv_c_no_fpie\" = \"yes\"; then\n fi\n \n \n-# Check if -no-pie works.\n-{ $as_echo \"$as_me:${as_lineno-$LINENO}: checking for -no-pie option\" >&5\n-$as_echo_n \"checking for -no-pie option... \" >&6; }\n+# Check if -nopie works.\n+{ $as_echo \"$as_me:${as_lineno-$LINENO}: checking for -nopie option\" >&5\n+$as_echo_n \"checking for -nopie option... \" >&6; }\n if ${gcc_cv_no_pie+:} false; then :\n   $as_echo_n \"(cached) \" >&6\n else\n   saved_LDFLAGS=\"$LDFLAGS\"\n-   LDFLAGS=\"$LDFLAGS -no-pie\"\n+   LDFLAGS=\"$LDFLAGS -nopie\"\n    cat confdefs.h - <<_ACEOF >conftest.$ac_ext\n /* end confdefs.h.  */\n int main(void) {return 0;}\n@@ -32480,7 +32480,7 @@ fi\n { $as_echo \"$as_me:${as_lineno-$LINENO}: result: $gcc_cv_no_pie\" >&5\n $as_echo \"$gcc_cv_no_pie\" >&6; }\n if test \"$gcc_cv_no_pie\" = \"yes\"; then\n-  NO_PIE_FLAG=\"-no-pie\"\n+  NO_PIE_FLAG=\"-nopie\"\n fi\n \n \n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gcc/patches/patch-libcc1_connection_cc",
    "content": "Index: libcc1/connection.cc\n--- libcc1/connection.cc.orig\n+++ libcc1/connection.cc\n@@ -20,6 +20,7 @@ along with GCC; see the file COPYING3.  If not see\n #include <cc1plugin-config.h>\n #include <string>\n #include <unistd.h>\n+#include <sys/select.h>\n #include <sys/types.h>\n #include <string.h>\n #include <errno.h>\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gcc/patches/patch-libgcc_Makefile_in",
    "content": "Index: libgcc/Makefile.in\n--- libgcc/Makefile.in.orig\n+++ libgcc/Makefile.in\n@@ -1093,7 +1093,7 @@ libgcc-extra-parts: $(EXTRA_PARTS)\n \tparts=\"$(EXTRA_PARTS)\";\t\t\t\t\t\\\n \tfor file in $$parts; do\t\t\t\t\t\\\n \t  rm -f $(gcc_objdir)$(MULTISUBDIR)/$$file;\t\t\\\n-\t  $(INSTALL_DATA) $$file $(gcc_objdir)$(MULTISUBDIR)/;\t\\\n+\t  install -c $$file $(gcc_objdir)$(MULTISUBDIR)/;\t\\\n \t  case $$file in \t\t\t\t\t\\\n \t    *.a)\t\t\t\t\t\t\\\n \t      $(RANLIB) $(gcc_objdir)$(MULTISUBDIR)/$$file ;;\t\\\n@@ -1123,7 +1123,7 @@ install-unwind_h-forbuild: unwind.h\n # internal headers are copied by gcc's install.\n install-unwind_h:\n \t$(mkinstalldirs) $(DESTDIR)$(libsubdir)/include\n-\t$(INSTALL_DATA) unwind.h $(DESTDIR)$(libsubdir)/include\n+\tinstall -c unwind.h $(DESTDIR)$(libsubdir)/include\n \n all: install-unwind_h-forbuild\n \n@@ -1149,7 +1149,7 @@ install-libunwind:\n \n \t# NOTE: Maybe this should go into $(inst_libdir), but this\n \t# is where the old mklibgcc.in put it.\n-\t$(INSTALL_DATA) libunwind.a $(DESTDIR)$(inst_slibdir)/\n+\tinstall -c libunwind.a $(DESTDIR)$(inst_slibdir)/\n \tchmod 644 $(DESTDIR)$(inst_slibdir)/libunwind.a\n \t$(RANLIB) $(DESTDIR)$(inst_slibdir)/libunwind.a\n \n@@ -1160,7 +1160,7 @@ install-libunwind:\n install-shared:\n \t$(mkinstalldirs) $(DESTDIR)$(inst_libdir)\n \n-\t$(INSTALL_DATA) libgcc_eh.a $(DESTDIR)$(inst_libdir)/\n+\tinstall -c libgcc_eh.a $(DESTDIR)$(inst_libdir)/\n \tchmod 644 $(DESTDIR)$(inst_libdir)/libgcc_eh.a\n \t$(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_eh.a\n \n@@ -1171,19 +1171,17 @@ install-shared:\n install-leaf: $(install-shared) $(install-libunwind)\n \t$(mkinstalldirs) $(DESTDIR)$(inst_libdir)\n \n-\t$(INSTALL_DATA) libgcc.a $(DESTDIR)$(inst_libdir)/\n-\tchmod 644 $(DESTDIR)$(inst_libdir)/libgcc.a\n+\tinstall -c libgcc.a $(DESTDIR)$(inst_libdir)\n \t$(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc.a\n ifeq ($(enable_gcov),yes)\n-\t$(INSTALL_DATA) libgcov.a $(DESTDIR)$(inst_libdir)/\n-\tchmod 644 $(DESTDIR)$(inst_libdir)/libgcov.a\n+\tinstall -c libgcov.a $(DESTDIR)$(inst_libdir)\n \t$(RANLIB) $(DESTDIR)$(inst_libdir)/libgcov.a\n endif\n \n \tparts=\"$(INSTALL_PARTS)\";\t\t\t\t\\\n \tfor file in $$parts; do\t\t\t\t\t\\\n \t  rm -f $(DESTDIR)$(inst_libdir)/$$file;\t\t\\\n-\t  $(INSTALL_DATA) $$file $(DESTDIR)$(inst_libdir)/;\t\\\n+\t  install -c $$file $(DESTDIR)$(inst_libdir)/;\t\t\\\n \t  case $$file in \t\t\t\t\t\\\n \t    *.a)\t\t\t\t\t\t\\\n \t      $(RANLIB) $(gcc_objdir)$(MULTISUBDIR)/$$file ;;\t\\\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gcc/patches/patch-libiberty_Makefile_in",
    "content": "Index: libiberty/Makefile.in\n--- libiberty/Makefile.in.orig\n+++ libiberty/Makefile.in\n@@ -376,7 +376,7 @@ libiberty.html : $(srcdir)/libiberty.texi $(TEXISRC)\n @MAINT@\techo stamp > stamp-functions\n \n INSTALL_DEST = @INSTALL_DEST@\n-install: install_to_$(INSTALL_DEST) install-subdir\n+install:\n install-strip: install\n \n .PHONY: install install-strip\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gcc/patches/vecstep-gcc_tree-vect-loop_c",
    "content": "clang on powerpc64 defines vec_step already which collides with the\nsymbol in gcc, see https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=239266#c23\nrenaming suggested at https://gcc.gnu.org/legacy-ml/gcc/2019-07/msg00131.html\n\nIndex: gcc/tree-vect-loop.c\n--- gcc/tree-vect-loop.c.orig\n+++ gcc/tree-vect-loop.c\n@@ -55,6 +55,8 @@ along with GCC; see the file COPYING3.  If not see\n #include \"vec-perm-indices.h\"\n #include \"tree-eh.h\"\n \n+#define vec_step vec_step_\n+\n /* Loop Vectorization Pass.\n \n    This pass tries to vectorize loops.\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gcc/pkg/DESCR",
    "content": "GNU cross compiler suite, configured for the ${CONFIG} target.\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gcc/pkg/PFRAG.aarch64",
    "content": "@conflict aarch64-none-elf-gcc-linaro-*\n@pkgpath devel/arm-none-eabi/gcc-linaro,aarch64\nlib/gcc/\nlib/gcc/${CONFIG}/\nlib/gcc/${CONFIG}/${VERSION}/\nlib/gcc/${CONFIG}/${VERSION}/crtbegin.o\nlib/gcc/${CONFIG}/${VERSION}/crtend.o\nlib/gcc/${CONFIG}/${VERSION}/crtfastmath.o\nlib/gcc/${CONFIG}/${VERSION}/crti.o\nlib/gcc/${CONFIG}/${VERSION}/crtn.o\nlib/gcc/${CONFIG}/${VERSION}/ilp32/\nlib/gcc/${CONFIG}/${VERSION}/ilp32/crtbegin.o\nlib/gcc/${CONFIG}/${VERSION}/ilp32/crtend.o\nlib/gcc/${CONFIG}/${VERSION}/ilp32/crtfastmath.o\nlib/gcc/${CONFIG}/${VERSION}/ilp32/crti.o\nlib/gcc/${CONFIG}/${VERSION}/ilp32/crtn.o\n@static-lib lib/gcc/${CONFIG}/${VERSION}/ilp32/libgcc.a\n@static-lib lib/gcc/${CONFIG}/${VERSION}/ilp32/libgcov.a\nlib/gcc/${CONFIG}/${VERSION}/include/\nlib/gcc/${CONFIG}/${VERSION}/include-fixed/\nlib/gcc/${CONFIG}/${VERSION}/include-fixed/README\nlib/gcc/${CONFIG}/${VERSION}/include-fixed/limits.h\nlib/gcc/${CONFIG}/${VERSION}/include-fixed/syslimits.h\nlib/gcc/${CONFIG}/${VERSION}/include/arm_acle.h\nlib/gcc/${CONFIG}/${VERSION}/include/arm_bf16.h\nlib/gcc/${CONFIG}/${VERSION}/include/arm_fp16.h\nlib/gcc/${CONFIG}/${VERSION}/include/arm_neon.h\nlib/gcc/${CONFIG}/${VERSION}/include/arm_sve.h\nlib/gcc/${CONFIG}/${VERSION}/include/float.h\nlib/gcc/${CONFIG}/${VERSION}/include/gcov.h\nlib/gcc/${CONFIG}/${VERSION}/include/iso646.h\nlib/gcc/${CONFIG}/${VERSION}/include/stdalign.h\nlib/gcc/${CONFIG}/${VERSION}/include/stdarg.h\nlib/gcc/${CONFIG}/${VERSION}/include/stdatomic.h\nlib/gcc/${CONFIG}/${VERSION}/include/stdbool.h\nlib/gcc/${CONFIG}/${VERSION}/include/stddef.h\nlib/gcc/${CONFIG}/${VERSION}/include/stdfix.h\nlib/gcc/${CONFIG}/${VERSION}/include/stdint-gcc.h\nlib/gcc/${CONFIG}/${VERSION}/include/stdint.h\nlib/gcc/${CONFIG}/${VERSION}/include/stdnoreturn.h\nlib/gcc/${CONFIG}/${VERSION}/include/tgmath.h\nlib/gcc/${CONFIG}/${VERSION}/include/unwind.h\nlib/gcc/${CONFIG}/${VERSION}/include/varargs.h\nlib/gcc/${CONFIG}/${VERSION}/install-tools/\nlib/gcc/${CONFIG}/${VERSION}/install-tools/fixinc_list\nlib/gcc/${CONFIG}/${VERSION}/install-tools/gsyslimits.h\nlib/gcc/${CONFIG}/${VERSION}/install-tools/include/\nlib/gcc/${CONFIG}/${VERSION}/install-tools/include/README\nlib/gcc/${CONFIG}/${VERSION}/install-tools/include/limits.h\nlib/gcc/${CONFIG}/${VERSION}/install-tools/macro_list\nlib/gcc/${CONFIG}/${VERSION}/install-tools/mkheaders.conf\n@static-lib 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  },
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    "content": "@conflict arm-none-eabi-gcc-linaro-*\n@pkgpath devel/arm-none-eabi/gcc-linaro,\n@pkgpath devel/arm-none-eabi/gcc-linaro,arm\nlib/gcc/\nlib/gcc/${CONFIG}/\nlib/gcc/${CONFIG}/${VERSION}/\nlib/gcc/${CONFIG}/${VERSION}/arm/\nlib/gcc/${CONFIG}/${VERSION}/arm/v5te/\nlib/gcc/${CONFIG}/${VERSION}/arm/v5te/hard/\nlib/gcc/${CONFIG}/${VERSION}/arm/v5te/hard/crtbegin.o\nlib/gcc/${CONFIG}/${VERSION}/arm/v5te/hard/crtend.o\nlib/gcc/${CONFIG}/${VERSION}/arm/v5te/hard/crtfastmath.o\nlib/gcc/${CONFIG}/${VERSION}/arm/v5te/hard/crti.o\nlib/gcc/${CONFIG}/${VERSION}/arm/v5te/hard/crtn.o\n@static-lib lib/gcc/${CONFIG}/${VERSION}/arm/v5te/hard/libgcc.a\n@static-lib lib/gcc/${CONFIG}/${VERSION}/arm/v5te/hard/libgcov.a\nlib/gcc/${CONFIG}/${VERSION}/arm/v5te/softfp/\nlib/gcc/${CONFIG}/${VERSION}/arm/v5te/softfp/crtbegin.o\nlib/gcc/${CONFIG}/${VERSION}/arm/v5te/softfp/crtend.o\nlib/gcc/${CONFIG}/${VERSION}/arm/v5te/softfp/crtfastmath.o\nlib/gcc/${CONFIG}/${VERSION}/arm/v5te/softfp/crti.o\nlib/gcc/${CONFIG}/${VERSION}/arm/v5te/softfp/crtn.o\n@static-lib lib/gcc/${CONFIG}/${VERSION}/arm/v5te/softfp/libgcc.a\n@static-lib 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lib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.base/nofp/libgcov.a\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main/\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+dp/\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+dp/hard/\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+dp/hard/crtbegin.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+dp/hard/crtend.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+dp/hard/crtfastmath.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+dp/hard/crti.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+dp/hard/crtn.o\n@static-lib lib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+dp/hard/libgcc.a\n@static-lib lib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+dp/hard/libgcov.a\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+dp/softfp/\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+dp/softfp/crtbegin.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+dp/softfp/crtend.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+dp/softfp/crtfastmath.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+dp/softfp/crti.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+dp/softfp/crtn.o\n@static-lib lib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+dp/softfp/libgcc.a\n@static-lib lib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+dp/softfp/libgcov.a\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+fp/\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+fp/hard/\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+fp/hard/crtbegin.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+fp/hard/crtend.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+fp/hard/crtfastmath.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+fp/hard/crti.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+fp/hard/crtn.o\n@static-lib lib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+fp/hard/libgcc.a\n@static-lib lib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+fp/hard/libgcov.a\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+fp/softfp/\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+fp/softfp/crtbegin.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+fp/softfp/crtend.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+fp/softfp/crtfastmath.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+fp/softfp/crti.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+fp/softfp/crtn.o\n@static-lib lib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+fp/softfp/libgcc.a\n@static-lib lib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main+fp/softfp/libgcov.a\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main/nofp/\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main/nofp/crtbegin.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main/nofp/crtend.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main/nofp/crtfastmath.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main/nofp/crti.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main/nofp/crtn.o\n@static-lib lib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main/nofp/libgcc.a\n@static-lib lib/gcc/${CONFIG}/${VERSION}/thumb/v8-m.main/nofp/libgcov.a\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8.1-m.main+mve/\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8.1-m.main+mve/hard/\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8.1-m.main+mve/hard/crtbegin.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8.1-m.main+mve/hard/crtend.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8.1-m.main+mve/hard/crtfastmath.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8.1-m.main+mve/hard/crti.o\nlib/gcc/${CONFIG}/${VERSION}/thumb/v8.1-m.main+mve/hard/crtn.o\n@static-lib lib/gcc/${CONFIG}/${VERSION}/thumb/v8.1-m.main+mve/hard/libgcc.a\n@static-lib lib/gcc/${CONFIG}/${VERSION}/thumb/v8.1-m.main+mve/hard/libgcov.a\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gcc/pkg/PLIST",
    "content": "%%aarch64%%\n%%arm%%\n@bin bin/${CONFIG}-c++\n@bin bin/${CONFIG}-cpp\n@bin bin/${CONFIG}-g++\n@bin bin/${CONFIG}-gcc\n@bin bin/${CONFIG}-gcc-${VERSION}\n@bin bin/${CONFIG}-gcc-ar\n@bin bin/${CONFIG}-gcc-nm\n@bin bin/${CONFIG}-gcc-ranlib\n@bin bin/${CONFIG}-gcov\n@bin bin/${CONFIG}-gcov-dump\n@bin bin/${CONFIG}-gcov-tool\n@bin bin/${CONFIG}-lto-dump\nlibexec/gcc/\nlibexec/gcc/${CONFIG}/\nlibexec/gcc/${CONFIG}/${VERSION}/\n@bin libexec/gcc/${CONFIG}/${VERSION}/cc1\n@bin libexec/gcc/${CONFIG}/${VERSION}/cc1plus\n@bin libexec/gcc/${CONFIG}/${VERSION}/collect2\n@bin libexec/gcc/${CONFIG}/${VERSION}/g++-mapper-server\nlibexec/gcc/${CONFIG}/${VERSION}/install-tools/\nlibexec/gcc/${CONFIG}/${VERSION}/install-tools/fixinc.sh\n@bin libexec/gcc/${CONFIG}/${VERSION}/install-tools/fixincl\nlibexec/gcc/${CONFIG}/${VERSION}/install-tools/mkheaders\nlibexec/gcc/${CONFIG}/${VERSION}/install-tools/mkinstalldirs\nlibexec/gcc/${CONFIG}/${VERSION}/liblto_plugin.la\n@so libexec/gcc/${CONFIG}/${VERSION}/liblto_plugin.so\n@bin libexec/gcc/${CONFIG}/${VERSION}/lto-wrapper\n@bin libexec/gcc/${CONFIG}/${VERSION}/lto1\nlibexec/gcc/${CONFIG}/${VERSION}/plugin/\n@bin libexec/gcc/${CONFIG}/${VERSION}/plugin/gengtype\n@man man/man1/${CONFIG}-cpp.1\n@man man/man1/${CONFIG}-g++.1\n@man man/man1/${CONFIG}-gcc.1\n@man man/man1/${CONFIG}-gcov-dump.1\n@man man/man1/${CONFIG}-gcov-tool.1\n@man man/man1/${CONFIG}-gcov.1\n@comment @man man/man7/fsf-funding.7\n@comment @man man/man7/gfdl.7\n@comment @man man/man7/gpl.7\n@man man/man1/${CONFIG}-lto-dump.1\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gdb/Makefile",
    "content": "COMMENT=\tgdb for arm-none-eabi cross-development\n\nDISTNAME=\tgdb-12.1\n\nHOMEPAGE=\thttps://www.gnu.org/software/gdb/\n\nWANTLIB+=\t${COMPILER_LIBCXX}\nWANTLIB+=\tc curses expat m pthread\n\nSITES=\t\t${SITE_GNU:=gdb/}\nDIST_SUBDIR=\tgdb\n\nUSE_GMAKE=\tYes\n\nMODGNU_CONFIG_GUESS_DIRS=\t${WRKSRC} ${WRKSRC}/gdb\n\n# C++11\nCOMPILER=\tbase-clang ports-gcc\n\nSEPARATE_BUILD=\tYes\n\nCONFIGURE_ARGS+=\t\t\t\t\\\n\t\t--disable-install-libbfd\t\\\n\t\t--disable-sim\t\t\t\\\n\t\t--enable-interwork\t\t\\\n\t\t--enable-multilib\t\t\\\n\t\t--enable-thumb\t\t\t\\\n\t\t--with-system-zlib\t\t\\\n\t\t--without-guile\t\t\t\\\n\t\t--without-isl\t\t\t\\\n\t\t--without-lzma\t\t\t\\\n\t\t--without-mpc\t\t\t\\\n\t\t--without-mpfr\t\t\t\\\n\t\t--without-python\n\nMAKE_FLAGS=\tV=1 LDFLAGS=\"-L${LOCALBASE}/lib ${LDFLAGS}\"\n# Avoid using malloc replacement for no good reason\nMAKE_ENV=\tgl_cv_malloc_ptrdiff=yes\n\nMODULES+=\tlang/python\n\nTEST_DEPENDS=\tdevel/dejagnu\n\n.include <bsd.port.mk>\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gdb/distinfo",
    "content": "SHA256 (gdb/gdb-12.1.tar.xz) = DheTv48rVNU/Rt6oTM/URvSPgbKXsoxPf8AXuBjWn+0=\nSIZE (gdb/gdb-12.1.tar.xz) = 22470332\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gdb/patches/patch-gdb_data-directory_Makefile_in",
    "content": "Index: gdb/data-directory/Makefile.in\n--- gdb/data-directory/Makefile.in.orig\n+++ gdb/data-directory/Makefile.in\n@@ -199,7 +199,7 @@ stamp-syscalls: Makefile $(SYSCALLS_FILES)\n \tfor file in $$files ; do \\\n \t  f=$(SYSCALLS_SRCDIR)/$$file ; \\\n \t  if test -f $$f ; then \\\n-\t    $(INSTALL_DATA) $$f ./$(SYSCALLS_DIR) ; \\\n+\t    cp $$f ./$(SYSCALLS_DIR) ; \\\n \t  fi ; \\\n \tdone\n \ttouch $@\n@@ -241,8 +241,8 @@ stamp-python: Makefile $(PYTHON_FILES)\n \tif test \"x$$files\" != x ; then \\\n \t  for file in $$files ; do \\\n \t    dir=`echo \"$$file\" | sed 's,/[^/]*$$,,'` ; \\\n-\t    $(INSTALL_DIR) ./$(PYTHON_DIR)/$$dir ; \\\n-\t    $(INSTALL_DATA) $(PYTHON_SRCDIR)/$$file ./$(PYTHON_DIR)/$$dir ; \\\n+\t    mkdir -p ./$(PYTHON_DIR)/$$dir ; \\\n+\t    cp $(PYTHON_SRCDIR)/$$file ./$(PYTHON_DIR)/$$dir ; \\\n \t  done ; \\\n \tfi\n \ttouch $@\n@@ -335,7 +335,7 @@ stamp-system-gdbinit: Makefile $(SYSTEM_GDBINIT_FILES)\n \tfor file in $$files ; do \\\n \t  f=$(SYSTEM_GDBINIT_SRCDIR)/$$file ; \\\n \t  if test -f $$f ; then \\\n-\t    $(INSTALL_DATA) $$f ./$(SYSTEM_GDBINIT_DIR) ; \\\n+\t    cp $$f ./$(SYSTEM_GDBINIT_DIR) ; \\\n \t  fi ; \\\n \tdone\n \ttouch $@\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gdb/patches/patch-gdb_i386-obsd-nat_c",
    "content": "Bogus variable name.\n\nIndex: gdb/i386-obsd-nat.c\n--- gdb/i386-obsd-nat.c.orig\n+++ gdb/i386-obsd-nat.c\n@@ -94,7 +94,7 @@ void _initialize_i386obsd_nat ();\n void\n _initialize_i386obsd_nat ()\n {\n-  add_inf_child_target (&i386_obsd_nat_target);\n+  add_inf_child_target (&the_i386_obsd_nat_target);\n \n   /* Support debugging kernel virtual memory images.  */\n   bsd_kvm_add_target (i386obsd_supply_pcb);\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gdb/patches/patch-gdbsupport_enum-flags_h",
    "content": "Index: gdbsupport/enum-flags.h\n--- gdbsupport/enum-flags.h.orig\n+++ gdbsupport/enum-flags.h\n@@ -91,9 +91,12 @@ template<> struct integer_for_size<8, 1> { typedef int\n template<typename T>\n struct enum_underlying_type\n {\n+  DIAGNOSTIC_PUSH\n+  DIAGNOSTIC_IGNORE_ENUM_CONSTEXPR_CONVERSION\n   typedef typename\n     integer_for_size<sizeof (T), static_cast<bool>(T (-1) < T (0))>::type\n     type;\n+  DIAGNOSTIC_POP\n };\n \n namespace enum_flags_detail\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gdb/patches/patch-include_diagnostics_h",
    "content": "From 12e3f3bc6ec74eb50e04675f5bcf962482d3ff25 Mon Sep 17 00:00:00 2001\nFrom: Simon Marchi <simon.marchi@efficios.com>\nDate: Thu, 23 Feb 2023 12:35:40 -0500\nSubject: [PATCH] gdbsupport: ignore -Wenum-constexpr-conversion in\n enum-flags.h\n\nIndex: include/diagnostics.h\n--- include/diagnostics.h.orig\n+++ include/diagnostics.h\n@@ -66,6 +66,11 @@\n # define DIAGNOSTIC_ERROR_SWITCH \\\n   DIAGNOSTIC_ERROR (\"-Wswitch\")\n \n+# if __has_warning (\"-Wenum-constexpr-conversion\")\n+#  define DIAGNOSTIC_IGNORE_ENUM_CONSTEXPR_CONVERSION \\\n+   DIAGNOSTIC_IGNORE (\"-Wenum-constexpr-conversion\")\n+# endif\n+\n #elif defined (__GNUC__) /* GCC */\n \n # if __GNUC__ >= 7\n@@ -110,6 +115,10 @@\n \n #ifndef DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL\n # define DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL\n+#endif\n+\n+#ifndef DIAGNOSTIC_IGNORE_ENUM_CONSTEXPR_CONVERSION\n+# define DIAGNOSTIC_IGNORE_ENUM_CONSTEXPR_CONVERSION\n #endif\n \n #ifndef DIAGNOSTIC_ERROR_SWITCH\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gdb/patches/patch-include_filenames_h",
    "content": "Our libiberty does not have filename_cmp(), but since it would simply\ncall strcmp(), use a macro when building gdb and most of all libbfd.\n\nFixes linking against libbfd with our system libiberty.\n\nIndex: include/filenames.h\n--- include/filenames.h.orig\n+++ include/filenames.h\n@@ -81,11 +81,10 @@ extern \"C\" {\n   (IS_DIR_SEPARATOR_1 (dos_based, (f)[0])\t\t \\\n    || HAS_DRIVE_SPEC_1 (dos_based, f))\n \n-extern int filename_cmp (const char *s1, const char *s2);\n-#define FILENAME_CMP(s1, s2)\tfilename_cmp(s1, s2)\n+#define FILENAME_CMP(s1, s2)\t\tstrcmp(s1, s2)\n+#define filename_cmp(s1, s2)\t\tstrcmp(s1, s2)\n \n-extern int filename_ncmp (const char *s1, const char *s2,\n-\t\t\t  size_t n);\n+#define filename_ncmp(s1, s2, n)\tstrncmp(s1, s2, n)\n \n extern hashval_t filename_hash (const void *s);\n \n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gdb/patches/patch-libiberty_Makefile_in",
    "content": "Index: libiberty/Makefile.in\n--- libiberty/Makefile.in.orig\n+++ libiberty/Makefile.in\n@@ -376,7 +376,7 @@ libiberty.html : $(srcdir)/libiberty.texi $(TEXISRC)\n @MAINT@\techo stamp > stamp-functions\n \n INSTALL_DEST = @INSTALL_DEST@\n-install: install_to_$(INSTALL_DEST) install-subdir\n+install:\n install-strip: install\n \n .PHONY: install install-strip\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gdb/patches/patch-libiberty_filename_cmp_c",
    "content": "Our libiberty does not have filename_cmp(), but since it would simply\ncall strcmp(), use a macro when building gdb and most of all libbfd.\n\nFixes linking against libbfd with our system libiberty.\n\n--- libiberty/filename_cmp.c.orig\tThu Feb 19 12:58:08 2015\n+++ libiberty/filename_cmp.c\tFri Feb 20 22:12:26 2015\n@@ -52,6 +52,7 @@ and backward slashes are equal.\n \n */\n \n+#if 0\n int\n filename_cmp (const char *s1, const char *s2)\n {\n@@ -146,6 +147,7 @@ filename_ncmp (const char *s1, const char *s2, size_t \n   return 0;\n #endif\n }\n+#endif\n \n /*\n \n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gdb/pkg/DESCR",
    "content": "This is the GNU debugger, configured for the arm-none-eabi target.\n\nFor more information, type \"help\" from within GDB, or consult the\nGDB manual (available as on-line info or a printed manual).\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/gdb/pkg/PLIST",
    "content": "@bin bin/arm-none-eabi-gdb\nbin/arm-none-eabi-gdb-add-index\n@comment lib/charset.alias\n@comment include/gdb/\n@comment include/gdb/jit-reader.h\n@comment @info info/annotate.info\n@comment @info info/bfd.info\n@comment @info info/ctf-spec.info\n@comment @info info/gdb.info\n@comment @info info/stabs.info\n@man man/man1/arm-none-eabi-gdb-add-index.1\n@man man/man1/arm-none-eabi-gdb.1\n@man man/man1/arm-none-eabi-gdbserver.1\n@man man/man5/arm-none-eabi-gdbinit.5\n@comment share/gdb/syscalls/\n@comment share/gdb/syscalls/aarch64-linux.xml\n@comment share/gdb/syscalls/amd64-linux.xml\n@comment share/gdb/syscalls/arm-linux.xml\n@comment share/gdb/syscalls/freebsd.xml\n@comment share/gdb/syscalls/gdb-syscalls.dtd\n@comment share/gdb/syscalls/i386-linux.xml\n@comment share/gdb/syscalls/mips-n32-linux.xml\n@comment share/gdb/syscalls/mips-n64-linux.xml\n@comment share/gdb/syscalls/mips-o32-linux.xml\n@comment share/gdb/syscalls/netbsd.xml\n@comment share/gdb/syscalls/ppc-linux.xml\n@comment share/gdb/syscalls/ppc64-linux.xml\n@comment share/gdb/syscalls/s390-linux.xml\n@comment share/gdb/syscalls/s390x-linux.xml\n@comment share/gdb/syscalls/sparc-linux.xml\n@comment share/gdb/syscalls/sparc64-linux.xml\n@comment share/gdb/system-gdbinit/\n@comment share/gdb/system-gdbinit/elinos.py\n@comment share/gdb/system-gdbinit/wrs-linux.py\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/Makefile",
    "content": "COMMENT=\tnewlib for arm-none-eabi cross-development\n\nDISTNAME=\tnewlib-2.2.0-1\nVERSION=\t2.2.0.1\nPKGNAME=\t${CONFIG}-newlib-${VERSION}\nREVISION=\t3\n\nMAKE_ENV+=\t${CONFIGURE_ENV}\n\nHOMEPAGE=\thttp://sourceware.org/newlib/\n\nSITES=\t\tftp://sourceware.org/pub/newlib/\n#SITES=\t\tftp://sources.redhat.com/pub/newlib/\n\nEXTRACT_SUFX=\t.tar.gz\n\nBUILD_DEPENDS=\tdevel/arm-none-eabi/binutils,arm \\\n\t\t${RUN_DEPENDS}\nRUN_DEPENDS=\tdevel/arm-none-eabi/gcc,arm\n\n# cope with user settings in /etc/mk.conf\nMAKE_FLAGS=\tCFLAGS=\"-I${LOCALBASE}/include\"\nUSE_GMAKE=\tYes\nCONFIGURE_ARGS+=--enable-interwork \\\n\t\t--enable-multilib\n\npost-install:\n\t${INSTALL_DATA_DIR} ${PREFIX}/share/doc/arm-none-eabi/newlib\n\t${INSTALL_DATA} ${WRKDIST}/COPYING.NEWLIB \\\n\t\t${PREFIX}/share/doc/arm-none-eabi/newlib\n\n.include <bsd.port.mk>\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/distinfo",
    "content": "SHA256 (newlib-2.2.0-1.tar.gz) = wdU/0XZdlVrFE6puL1dkVe51BwctQAMUSVyKiibryOw=\nSIZE (newlib-2.2.0-1.tar.gz) = 16597844\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-etc_Makefile_in",
    "content": "--- etc/Makefile.in.orig\tFri Jul 31 00:44:48 2009\n+++ etc/Makefile.in\tThu Oct 14 14:17:07 2010\n@@ -58,7 +58,7 @@ TEXIDIR = $(srcdir)/../texinfo\n #### Host, target, and site specific Makefile fragments come in here.\n ###\n \n-INFOFILES = standards.info configure.info\n+INFOFILES =\n DVIFILES = standards.dvi configure.dvi\n PDFFILES = standards.pdf configure.pdf\n HTMLFILES = standards.html configure.html\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-libgloss_arm_Makefile_in",
    "content": "Make macro checks ARMv8-M baseline proof.\nAdd newlib/libc/machine/arm to the include path if newlib is present.\n\nIndex: libgloss/arm/Makefile.in\n--- libgloss/arm/Makefile.in.orig\n+++ libgloss/arm/Makefile.in\n@@ -94,6 +94,8 @@ IQ80310_INSTALL\t= install-iq80310\n # Host specific makefile fragment comes in here.\n @host_makefile_frag@\n \n+INCLUDES += `if [ -d ${objroot}/newlib ]; then echo -I$(srcroot)/newlib/libc/machine/arm; fi`\n+\n #\n # build a test program for each target board. Just trying to get\n # it to link is a good test, so we ignore all the errors for now.\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-libgloss_arm_arm_h",
    "content": "Include acle-compat.h.\n(THUMB_V7_V6M): Rename to ...\n(PREFER_THUMB): This.  Use ACLE macros __ARM_ARCH_ISA_ARM instead of\n__ARM_ARCH_6M__ to decide whether to define it.\n(THUMB1_ONLY): Define for Thumb-1 only targets.\n(THUMB_V7M_V6M): Rename to ...\n(THUMB_VXM): This.  Defined based on __ARM_ARCH_ISA_ARM, excluding\nARMv7.\n\nIndex: libgloss/arm/arm.h\n--- libgloss/arm/arm.h.orig\n+++ libgloss/arm/arm.h\n@@ -29,25 +29,27 @@\n #ifndef _LIBGLOSS_ARM_H\n #define _LIBGLOSS_ARM_H\n \n-/* __thumb2__ stands for thumb on armva7(A/R/M/EM) architectures,\n-   __ARM_ARCH_6M__ stands for armv6-M(thumb only) architecture,\n-   __ARM_ARCH_7M__ stands for armv7-M(thumb only) architecture.\n-   __ARM_ARCH_7EM__ stands for armv7e-M(thumb only) architecture.\n-   There are some macro combinations used many times in libgloss/arm,\n-   like (__thumb2__ || (__thumb__ && __ARM_ARCH_6M__)), so factor\n-   it out and use THUMB_V7_V6M instead, which stands for thumb on\n-   v6-m/v7 arch as the combination does.  */\n-#if defined(__thumb2__) || (defined(__thumb__) && defined(__ARM_ARCH_6M__))\n-# define THUMB_V7_V6M\n+#include \"acle-compat.h\"\n+\n+/* Checking for targets supporting only Thumb instructions (eg. ARMv6-M) or\n+   supporting Thumb-2 instructions, whether ARM instructions are available or\n+   not, is done many times in libgloss/arm.  So factor it out and use\n+   PREFER_THUMB instead.  */\n+#if __thumb2__ || (__thumb__ && !__ARM_ARCH_ISA_ARM)\n+# define PREFER_THUMB\n #endif\n \n-/* The (__ARM_ARCH_7EM__ || __ARM_ARCH_7M__ || __ARM_ARCH_6M__) combination\n-   stands for cortex-M profile architectures, which don't support ARM state.\n-   Factor it out and use THUMB_V7M_V6M instead.  */\n-#if defined(__ARM_ARCH_7M__)     \\\n-    || defined(__ARM_ARCH_7EM__) \\\n-    || defined(__ARM_ARCH_6M__)\n-# define THUMB_V7M_V6M\n+/* Processor only capable of executing Thumb-1 instructions.  */\n+#if __ARM_ARCH_ISA_THUMB == 1 && !__ARM_ARCH_ISA_ARM\n+# define THUMB1_ONLY\n+#endif\n+\n+/* M profile architectures.  This is a different set of architectures than\n+   those not having ARM ISA because it does not contain ARMv7.  This macro is\n+   necessary to test which architectures use bkpt as semihosting interface from\n+   architectures using svc.  */\n+#if !__ARM_ARCH_ISA_ARM && !__ARM_ARCH_7__\n+# define THUMB_VXM\n #endif\n \n /* Defined if this target supports the BLX Rm instruction.  */\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-libgloss_arm_crt0_S",
    "content": "Make macro checks ARMv8-M baseline proof.\n\nIndex: libgloss/arm/crt0.S\n--- libgloss/arm/crt0.S.orig\n+++ libgloss/arm/crt0.S\n@@ -44,7 +44,7 @@\n /* .text is used instead of .section .text so it works with arm-aout too.  */\n \t.text\n \t.syntax unified\n-#ifdef THUMB_V7_V6M\n+#ifdef PREFER_THUMB\n \t.thumb\n .macro FUNC_START name\n \t.global \\name\n@@ -98,7 +98,7 @@\n \n \t/*  stack limit is at end of data */\n \t/*  allow slop for stack overflow handling and small frames */\n-#ifdef __ARM_ARCH_6M__\n+#ifdef THUMB1_ONLY\n \tldr\tr0, .LC2\n \tadds\tr0, #128\n \tadds\tr0, #128\n@@ -112,7 +112,7 @@\n \t/*  Issue Angel SWI to read stack info */\n \tmovs\tr0, #AngelSWI_Reason_HeapInfo\n \tadr\tr1, .LC0\t/*  point at ptr to 4 words to receive data */\n-#ifdef THUMB_V7M_V6M\n+#ifdef THUMB_VXM\n \tbkpt\tAngelSWI\n #elif defined(__thumb2__)\n \t/*  We are in thumb mode for startup on armv7 architectures. */\n@@ -149,7 +149,7 @@\n \tcmp\tr2, #0\n \tbeq\t.LC27\n \t/*  allow slop for stack overflow handling and small frames */\n-#ifdef __ARM_ARCH_6M__\n+#ifdef THUMB1_ONLY\n \tadds\tr2, #128\n \tadds\tr2, #128\n \tmov\tsl, r2\n@@ -175,7 +175,7 @@\n #ifdef __thumb2__\n \tit\teq\n #endif\t\n-#ifdef __ARM_ARCH_6M__\n+#ifdef THUMB1_ONLY\n \tbne\t.LC28\n \tldr\tr3, .LC0\n .LC28:\n@@ -187,7 +187,7 @@\n \t\t have somehow missed it below (in which case it gets the same\n \t\t value as FIQ - not ideal, but better than nothing.) */\n \tmov\tsp, r3\n-#ifdef THUMB_V7_V6M\n+#ifdef PREFER_THUMB\n \t/* XXX Fill in stack assignments for interrupt modes.  */\n #else\n \tmrs\tr2, CPSR\n@@ -230,7 +230,7 @@\n \t   this default 64k is enough for the program being executed.\n \t   However, it ensures that this simple crt0 world will not\n \t   immediately cause an overflow event:  */\n-#ifdef __ARM_ARCH_6M__\n+#ifdef THUMB1_ONLY\n \tmovs\tr2, #64\n \tlsls\tr2, r2, #10\n \tsubs\tr2, r3, r2\n@@ -250,7 +250,7 @@\n \tsubs\ta3, a3, a1\t\t/* Third arg: length of block */\n \t\n \n-#if defined(__thumb__) && !defined(THUMB_V7_V6M)\n+#if __thumb__ && !defined(PREFER_THUMB)\n \t/* Enter Thumb mode.... */\n \tadd\ta4, pc, #1\t/* Get the address of the Thumb block */\n \tbx\ta4\t\t/* Go there and start Thumb decoding  */\n@@ -421,7 +421,7 @@ __change_mode:\t\n \n \tbl\tFUNCTION (exit)\t\t/* Should not return.  */\n \n-#if defined(__thumb__) && !defined(THUMB_V7_V6M)\n+#if __thumb__ && !defined(PREFER_THUMB)\n \t/* Come out of Thumb mode.  This code should be redundant.  */\n \n \tmov\ta4, pc\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-libgloss_arm_linux-crt0_c",
    "content": "Make macro checks ARMv8-M baseline proof.\n\nIndex: libgloss/arm/linux-crt0.c\n--- libgloss/arm/linux-crt0.c.orig\n+++ libgloss/arm/linux-crt0.c\n@@ -12,7 +12,7 @@\n \n static int _main(int argc, char *argv[]) __attribute__((noreturn));\n \n-#if defined(__thumb__) && !defined(THUMB_V7_V6M)\n+#if __thumb__ && !defined(PREFER_THUMB)\n asm(\"\\n\"\n \t\".code 32\\n\"\n \t\".global _start\\n\"\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-libgloss_arm_redboot-crt0_S",
    "content": "Make macro checks ARMv8-M baseline proof.\n\nIndex: libgloss/arm/redboot-crt0.S\n--- libgloss/arm/redboot-crt0.S.orig\n+++ libgloss/arm/redboot-crt0.S\n@@ -14,7 +14,7 @@\n     .text\n \t.syntax unified\n      /* Setup the assembly entry point.  */\n-#ifdef THUMB_V7_V6M\n+#ifdef PREFER_THUMB\n .macro FUNC_START name\n \t.global \\name\n \t.thumb_func\n@@ -31,13 +31,13 @@\n \tFUNC_START SYM_NAME(_start)\n     /* Unnecessary to set fp for v6-m/v7-m, which don't support\n        ARM state.  */\n-#ifndef THUMB_V7M_V6M\n+#if __ARM_ARCH_ISA_ARM\n \tmov\tfp, #0\t/* Null frame pointer.  */\n #endif\n \tmovs\tr7, #0\t/* Null frame pointer for Thumb.  */\n \n \t/* Enable interrupts for gdb debugging.  */\n-#ifdef THUMB_V7_V6M\n+#ifdef PREFER_THUMB\n \tcpsie if\n #else\n \tmrs    r0, cpsr\n@@ -66,7 +66,7 @@\n \t/* Nothing to left to clear.  */\n #endif\n \n-#if defined(__thumb__) && !defined(THUMB_V7_V6M)\n+#if __thumb__ && !defined(PREFER_THUMB)\n \t/* Enter Thumb mode. */\n \tadd\ta4, pc, #1\t/* Get the address of the Thumb block.  */\n \tbx\ta4\t\t/* Go there and start Thumb decoding.   */\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-libgloss_arm_swi_h",
    "content": "Make macro checks ARMv8-M baseline proof.\n\nIndex: libgloss/arm/swi.h\n--- libgloss/arm/swi.h.orig\n+++ libgloss/arm/swi.h\n@@ -36,7 +36,7 @@\n #define AngelSWI \t\t\tAngelSWI_ARM\n #endif\n /* For thumb only architectures use the BKPT instruction instead of SWI.  */\n-#ifdef THUMB_V7M_V6M\n+#ifdef THUMB_VXM\n #define AngelSWIInsn\t\t\t\"bkpt\"\n #define AngelSWIAsm\t\t\tbkpt\n #else\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-libgloss_arm_trap_S",
    "content": "Include code in trap.S for APCS only.\n\nIndex: libgloss/arm/trap.S\n--- libgloss/arm/trap.S.orig\n+++ libgloss/arm/trap.S\n@@ -1,6 +1,6 @@\n #include \"arm.h\"\n         /* Run-time exception support */\n-#ifndef THUMB_V7_V6M\n+#ifndef __ARM_EABI__\n #include \"swi.h\"\n \n /* .text is used instead of .section .text so it works with arm-aout too.  */\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-newlib_doc_makedoc_c",
    "content": "Index: newlib/doc/makedoc.c\n--- newlib/doc/makedoc.c.orig\n+++ newlib/doc/makedoc.c\n@@ -1314,11 +1314,11 @@ DEFUN(compile, (string), \n \t\t     /* Got a number, embedd the magic push number\n \t\t\tfunction */\n \t\t     add_to_definition(ptr, push_number);\n-\t\t     add_to_definition(ptr, atol(word));\n+\t\t     add_to_definition(ptr, (stinst_type)atol(word));\n \t\t     break;\n \t\t   default:\n \t\t     add_to_definition(ptr, call);\n-\t\t     add_to_definition(ptr, lookup_word(word));\n+\t\t     add_to_definition(ptr, (stinst_type)lookup_word(word));\n \t\t }\n \n \t\tstring = nextword(string, &word);\t\t     \n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-newlib_libc_machine_arm_setjmp_S",
    "content": "Make macro checks ARMv8-M baseline proof.\n\nUse ACLE macros __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM to check for\nThumb-2 only targets rather than __ARM_ARCH and __ARM_ARCH_PROFILE.\nLikewise for Thumb-1 only target and include acle-compat.h.\n\nIndex: newlib/libc/machine/arm/setjmp.S\n--- newlib/libc/machine/arm/setjmp.S.orig\n+++ newlib/libc/machine/arm/setjmp.S\n@@ -2,6 +2,8 @@\n \n    Nick Clifton, Cygnus Solutions, 13 June 1997.  */\n \n+#include \"acle-compat.h\"\n+\n /* ANSI concatenation macros.  */\n #define CONCAT(a, b)  CONCAT2(a, b)\n #define CONCAT2(a, b) a##b\n@@ -55,8 +57,8 @@\n    \n    For Thumb-2 do everything in Thumb mode.  */\n \n-#if defined(__ARM_ARCH_6M__)\n-/* ARMv6-M has to be implemented in Thumb mode.  */\n+#if __ARM_ARCH_ISA_THUMB == 1 && !__ARM_ARCH_ISA_ARM\n+/* ARMv6-M-like has to be implemented in Thumb mode.  */\n \n .thumb\n .thumb_func\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-newlib_libc_machine_arm_strcmp_S",
    "content": "Make macro checks ARMv8-M baseline proof.\n\nLikewise for Thumb-1 and Thumb-2 only target and include acle-compat.h.\n\nIndex: newlib/libc/machine/arm/strcmp.S\n--- newlib/libc/machine/arm/strcmp.S.orig\n+++ newlib/libc/machine/arm/strcmp.S\n@@ -29,6 +29,7 @@\n /* Wrapper for the various implementations of strcmp.  */\n \n #include \"arm_asm.h\"\n+#include \"acle-compat.h\"\n \n #ifdef __ARM_BIG_ENDIAN\n #define S2LO lsl\n@@ -61,7 +62,7 @@\n \t.endm\n \n #if defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED) \\\n-\t|| (__ARM_ARCH == 6 && __ARM_ARCH_PROFILE == 'M')\n+\t|| (__ARM_ARCH_ISA_THUMB == 1 && !__ARM_ARCH_ISA_ARM)\n \n # if defined (__thumb__) && !defined (__thumb2__)\n /* Thumb1 only variant.  If size is preferred, use strcmp-armv4t.S.\n@@ -78,7 +79,7 @@\n #  include \"strcmp-arm-tiny.S\"\n # endif\n \n-#elif __ARM_ARCH >= 7\n+#elif __ARM_ARCH_ISA_THUMB == 2\n \n # ifdef __ARM_FEATURE_SIMD32\n #  include \"strcmp-armv7.S\"\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-newlib_libc_sys_arm_Makefile_am",
    "content": "Fix build with newlib supplied syscalls enabled.\nacle-compat.h is libc/machine/arm.\n\nIndex: newlib/libc/sys/arm/Makefile.am\n--- newlib/libc/sys/arm/Makefile.am.orig\n+++ newlib/libc/sys/arm/Makefile.am\n@@ -2,7 +2,7 @@\n \n AUTOMAKE_OPTIONS = cygnus\n \n-INCLUDES = $(NEWLIB_CFLAGS) $(CROSS_CFLAGS) $(TARGET_CFLAGS)\n+INCLUDES = $(NEWLIB_CFLAGS) $(CROSS_CFLAGS) $(TARGET_CFLAGS) -I$(newlib_basedir)/libc/machine/arm\n \n AM_CCASFLAGS = $(INCLUDES)\n \n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-newlib_libc_sys_arm_Makefile_in",
    "content": "Fix build with newlib supplied syscalls enabled.\nacle-compat.h is libc/machine/arm.\n\nIndex: newlib/libc/sys/arm/Makefile.in\n--- newlib/libc/sys/arm/Makefile.in.orig\n+++ newlib/libc/sys/arm/Makefile.in\n@@ -193,7 +193,7 @@ top_build_prefix = @top_build_prefix@\n top_builddir = @top_builddir@\n top_srcdir = @top_srcdir@\n AUTOMAKE_OPTIONS = cygnus\n-INCLUDES = $(NEWLIB_CFLAGS) $(CROSS_CFLAGS) $(TARGET_CFLAGS)\n+INCLUDES = $(NEWLIB_CFLAGS) $(CROSS_CFLAGS) $(TARGET_CFLAGS) -I$(newlib_basedir)/libc/machine/arm\n AM_CCASFLAGS = $(INCLUDES)\n noinst_LIBRARIES = lib.a\n @MAY_SUPPLY_SYSCALLS_FALSE@extra_objs = \n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-newlib_libc_sys_arm_arm_h",
    "content": "Include acle-compat.h.\n(THUMB_V7_V6M): Rename to ...\n(PREFER_THUMB): This.  Use ACLE macros __ARM_ARCH_ISA_ARM instead of\n__ARM_ARCH_6M__ to decide whether to define it.\n(THUMB1_ONLY): Define for Thumb-1 only targets.\n(THUMB_V7M_V6M): Rename to ...\n(THUMB_VXM): This.  Defined based on __ARM_ARCH_ISA_ARM, excluding\nARMv7.\n\nIndex: newlib/libc/sys/arm/arm.h\n--- newlib/libc/sys/arm/arm.h.orig\n+++ newlib/libc/sys/arm/arm.h\n@@ -29,25 +29,27 @@\n #ifndef _LIBGLOSS_ARM_H\n #define _LIBGLOSS_ARM_H\n \n-/* __thumb2__ stands for thumb on armva7(A/R/M/EM) architectures,\n-   __ARM_ARCH_6M__ stands for armv6-M(thumb only) architecture,\n-   __ARM_ARCH_7M__ stands for armv7-M(thumb only) architecture.\n-   __ARM_ARCH_7EM__ stands for armv7e-M(thumb only) architecture.\n-   There are some macro combinations used many times in libgloss/arm,\n-   like (__thumb2__ || (__thumb__ && __ARM_ARCH_6M__)), so factor\n-   it out and use THUMB_V7_V6M instead, which stands for thumb on\n-   v6-m/v7 arch as the combination does.  */\n-#if defined(__thumb2__) || (defined(__thumb__) && defined(__ARM_ARCH_6M__))\n-# define THUMB_V7_V6M\n+#include \"acle-compat.h\"\n+\n+/* Checking for targets supporting only Thumb instructions (eg. ARMv6-M) or\n+   supporting Thumb-2 instructions, whether ARM instructions are available or\n+   not, is done many times in libgloss/arm.  So factor it out and use\n+   PREFER_THUMB instead.  */\n+#if __thumb2__ || (__thumb__ && !__ARM_ARCH_ISA_ARM)\n+# define PREFER_THUMB\n #endif\n \n-/* The (__ARM_ARCH_7EM__ || __ARM_ARCH_7M__ || __ARM_ARCH_6M__) combination\n-   stands for cortex-M profile architectures, which don't support ARM state.\n-   Factor it out and use THUMB_V7M_V6M instead.  */\n-#if defined(__ARM_ARCH_7M__)     \\\n-    || defined(__ARM_ARCH_7EM__) \\\n-    || defined(__ARM_ARCH_6M__)\n-# define THUMB_V7M_V6M\n+/* Processor only capable of executing Thumb-1 instructions.  */\n+#if __ARM_ARCH_ISA_THUMB == 1 && !__ARM_ARCH_ISA_ARM\n+# define THUMB1_ONLY\n+#endif\n+\n+/* M profile architectures.  This is a different set of architectures than\n+   those not having ARM ISA because it does not contain ARMv7.  This macro is\n+   necessary to test which architectures use bkpt as semihosting interface from\n+   architectures using svc.  */\n+#if !__ARM_ARCH_ISA_ARM && !__ARM_ARCH_7__\n+# define THUMB_VXM\n #endif\n \n /* Defined if this target supports the BLX Rm instruction.  */\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-newlib_libc_sys_arm_crt0_S",
    "content": "Make macro checks ARMv8-M baseline proof.\n\nIndex: newlib/libc/sys/arm/crt0.S\n--- newlib/libc/sys/arm/crt0.S.orig\n+++ newlib/libc/sys/arm/crt0.S\n@@ -44,7 +44,7 @@\n /* .text is used instead of .section .text so it works with arm-aout too.  */\n \t.text\n \t.syntax unified\n-#ifdef THUMB_V7_V6M\n+#ifdef PREFER_THUMB\n \t.thumb\n .macro FUNC_START name\n \t.global \\name\n@@ -85,7 +85,7 @@\n \n \t/*  Stack limit is at end of data.  */\n \t/*  Allow slop for stack overflow handling and small frames.  */\n-#ifdef __ARM_ARCH_6M__\n+#ifdef THUMB1_ONLY\n \tldr\tr0, .LC2\n \tadds\tr0, #128\n \tadds\tr0, #128\n@@ -99,7 +99,7 @@\n \t/*  Issue Angel SWI to read stack info.  */\n \tmovs\tr0, #AngelSWI_Reason_HeapInfo\n \tadr\tr1, .LC0\t/*  Point at ptr to 4 words to receive data.  */\n-#ifdef THUMB_V7M_V6M\n+#ifdef THUMB_VXM\n \tbkpt\tAngelSWI\n #elif defined(__thumb2__)\n \t/*  We are in thumb mode for startup on armv7 architectures.  */\n@@ -137,7 +137,7 @@\n \tbeq\t.LC27\n \n \t/*  Allow slop for stack overflow handling and small frames.  */\n-#ifdef __ARM_ARCH_6M__\n+#ifdef THUMB1_ONLY\n \tadds\tr2, #128\n \tadds\tr2, #128\n \tmov\tsl, r2\n@@ -164,7 +164,7 @@\n #ifdef __thumb2__\n \tit\teq\n #endif\t\n-#ifdef __ARM_ARCH_6M__\n+#ifdef THUMB1_ONLY\n \tbne\t.LC28\n \tldr\tr3, .LC0\n .LC28:\n@@ -176,7 +176,7 @@\n \t\t have somehow missed it below (in which case it gets the same\n \t\t value as FIQ - not ideal, but better than nothing).  */\n \tmov\tsp, r3\n-#ifdef THUMB_V7_V6M\n+#ifdef PREFER_THUMB\n \t/* XXX Fill in stack assignments for interrupt modes.  */\n #else\n \tmrs\tr2, CPSR\n@@ -219,7 +219,7 @@\n \t   this default 64k is enough for the program being executed.\n \t   However, it ensures that this simple crt0 world will not\n \t   immediately cause an overflow event:  */\n-#ifdef __ARM_ARCH_6M__\n+#ifdef THUMB1_ONLY\n \tmovs\tr2, #64\n \tlsls\tr2, r2, #10\n \tsubs\tr2, r3, r2\n@@ -239,7 +239,7 @@\n \tsubs\ta3, a3, a1\t\t/* Third arg: length of block.  */\n \t\n \n-#if defined(__thumb__) && !defined(THUMB_V7_V6M)\n+#if __thumb__ && !defined(PREFER_THUMB)\n \t/* Enter Thumb mode...  */\n \tadd\ta4, pc, #1\t/* Get the address of the Thumb block.  */\n \tbx\ta4\t\t/* Go there and start Thumb decoding.  */\n@@ -278,7 +278,7 @@ __change_mode:\t\n #else\n \tmovs\tr0, #AngelSWI_Reason_GetCmdLine\n \tadr\tr1, .LC30\t/* Space for command line.  */\n-#ifdef THUMB_V7M_V6M\n+#ifdef THUMB_VXM\n \tbkpt\tAngelSWI\n #else\n  \tAngelSWIAsm\tAngelSWI\n@@ -404,7 +404,7 @@ __change_mode:\t\n \n \tbl\tFUNCTION (exit)\t\t/* Should not return.  */\n \n-#if defined(__thumb__) && !defined(THUMB_V7_V6M)\n+#if __thumb__ && !defined(PREFER_THUMB)\n \t/* Come out of Thumb mode.  This code should be redundant.  */\n \tmov\ta4, pc\n \tbx\ta4\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-newlib_libc_sys_arm_swi_h",
    "content": "Make macro checks ARMv8-M baseline proof.\n\nIndex: newlib/libc/sys/arm/swi.h\n--- newlib/libc/sys/arm/swi.h.orig\n+++ newlib/libc/sys/arm/swi.h\n@@ -36,7 +36,7 @@\n #define AngelSWI \t\t\tAngelSWI_ARM\n #endif\n /* For thumb only architectures use the BKPT instruction instead of SWI.  */\n-#ifdef THUMB_V7M_V6M\n+#ifdef THUMB_VXM\n #define AngelSWIInsn\t\t\t\"bkpt\"\n #define AngelSWIAsm\t\t\tbkpt\n #else\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-newlib_libc_sys_arm_trap_S",
    "content": "Include code in trap.S for APCS only.\n\nIndex: newlib/libc/sys/arm/trap.S\n--- newlib/libc/sys/arm/trap.S.orig\n+++ newlib/libc/sys/arm/trap.S\n@@ -1,5 +1,5 @@\n         /* Run-time exception support */\n-#if !defined(__thumb2__)\n+#ifndef __ARM_EABI__\n #include \"swi.h\"\n \n /* .text is used instead of .section .text so it works with arm-aout too.  */\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-newlib_libm_machine_arm_s_ceil_c",
    "content": "Check for 64bit FP instructions availability in libm before using them.\n\nIndex: newlib/libm/machine/arm/s_ceil.c\n--- newlib/libm/machine/arm/s_ceil.c.orig\n+++ newlib/libm/machine/arm/s_ceil.c\n@@ -24,7 +24,7 @@\n    NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\n \n-#if __ARM_ARCH >= 8 && !defined (__SOFTFP__)\n+#if __ARM_ARCH >= 8 && (__ARM_FP & 0x8) && !defined (__SOFTFP__)\n #include <math.h>\n \n double\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-newlib_libm_machine_arm_s_floor_c",
    "content": "Check for 64bit FP instructions availability in libm before using them.\n\nIndex: newlib/libm/machine/arm/s_floor.c\n--- newlib/libm/machine/arm/s_floor.c.orig\n+++ newlib/libm/machine/arm/s_floor.c\n@@ -24,7 +24,7 @@\n    NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\n \n-#if __ARM_ARCH >= 8 && !defined (__SOFTFP__)\n+#if __ARM_ARCH >= 8 && (__ARM_FP & 0x8) && !defined (__SOFTFP__)\n #include <math.h>\n \n double\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-newlib_libm_machine_arm_s_nearbyint_c",
    "content": "Check for 64bit FP instructions availability in libm before using them.\n\nIndex: newlib/libm/machine/arm/s_nearbyint.c\n--- newlib/libm/machine/arm/s_nearbyint.c.orig\n+++ newlib/libm/machine/arm/s_nearbyint.c\n@@ -24,7 +24,7 @@\n    NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\n \n-#if __ARM_ARCH >= 8 && !defined (__SOFTFP__)\n+#if __ARM_ARCH >= 8 && (__ARM_FP & 0x8) && !defined (__SOFTFP__)\n #include <math.h>\n \n double\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-newlib_libm_machine_arm_s_rint_c",
    "content": "Check for 64bit FP instructions availability in libm before using them.\n\nIndex: newlib/libm/machine/arm/s_rint.c\n--- newlib/libm/machine/arm/s_rint.c.orig\n+++ newlib/libm/machine/arm/s_rint.c\n@@ -24,7 +24,7 @@\n    NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\n \n-#if __ARM_ARCH >= 8 && !defined (__SOFTFP__)\n+#if __ARM_ARCH >= 8 && (__ARM_FP & 0x8) && !defined (__SOFTFP__)\n #include <math.h>\n \n double\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-newlib_libm_machine_arm_s_round_c",
    "content": "Check for 64bit FP instructions availability in libm before using them.\n\nIndex: newlib/libm/machine/arm/s_round.c\n--- newlib/libm/machine/arm/s_round.c.orig\n+++ newlib/libm/machine/arm/s_round.c\n@@ -24,7 +24,7 @@\n    NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\n \n-#if __ARM_ARCH >= 8 && !defined (__SOFTFP__)\n+#if __ARM_ARCH >= 8 && (__ARM_FP & 0x8) && !defined (__SOFTFP__)\n #include <math.h>\n \n double\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/patches/patch-newlib_libm_machine_arm_s_trunc_c",
    "content": "Check for 64bit FP instructions availability in libm before using them.\n\nIndex: newlib/libm/machine/arm/s_trunc.c\n--- newlib/libm/machine/arm/s_trunc.c.orig\n+++ newlib/libm/machine/arm/s_trunc.c\n@@ -24,7 +24,7 @@\n    NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\n \n-#if __ARM_ARCH >= 8 && !defined (__SOFTFP__)\n+#if __ARM_ARCH >= 8 && (__ARM_FP & 0x8) && !defined (__SOFTFP__)\n #include <math.h>\n \n double\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/pkg/DESCR",
    "content": "Newlib is a C library intended for use on embedded systems. It is a\nconglomeration of several library parts, all under free software\nlicenses that make them easily usable on embedded products.\n\nThis port has been created to support development on embedded ARM\nsystems but in theory, additional targets should be possible.\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/arm-none-eabi/newlib/pkg/PLIST",
    "content": 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arm-none-eabi/lib/arm/v5te/hard/libc.a\n@static-lib arm-none-eabi/lib/arm/v5te/hard/libg.a\n@static-lib arm-none-eabi/lib/arm/v5te/hard/libgloss-linux.a\n@static-lib arm-none-eabi/lib/arm/v5te/hard/libm.a\n@static-lib arm-none-eabi/lib/arm/v5te/hard/libnosys.a\n@static-lib arm-none-eabi/lib/arm/v5te/hard/librdimon.a\n@static-lib arm-none-eabi/lib/arm/v5te/hard/librdpmon.a\narm-none-eabi/lib/arm/v5te/hard/linux-crt0.o\narm-none-eabi/lib/arm/v5te/hard/linux.specs\narm-none-eabi/lib/arm/v5te/hard/nano.specs\narm-none-eabi/lib/arm/v5te/hard/nosys.specs\narm-none-eabi/lib/arm/v5te/hard/pid.specs\narm-none-eabi/lib/arm/v5te/hard/rdimon-crt0.o\narm-none-eabi/lib/arm/v5te/hard/rdimon.specs\narm-none-eabi/lib/arm/v5te/hard/rdpmon-crt0.o\narm-none-eabi/lib/arm/v5te/hard/rdpmon.specs\narm-none-eabi/lib/arm/v5te/hard/redboot-crt0.o\narm-none-eabi/lib/arm/v5te/hard/redboot-syscalls.o\narm-none-eabi/lib/arm/v5te/hard/redboot.ld\narm-none-eabi/lib/arm/v5te/hard/redboot.specs\narm-none-eabi/lib/arm/v5te/softfp/\narm-none-eabi/lib/arm/v5te/softfp/aprofile-validation.specs\narm-none-eabi/lib/arm/v5te/softfp/aprofile-ve.specs\narm-none-eabi/lib/arm/v5te/softfp/cpu-init/\narm-none-eabi/lib/arm/v5te/softfp/cpu-init/rdimon-aem.o\narm-none-eabi/lib/arm/v5te/softfp/crt0.o\narm-none-eabi/lib/arm/v5te/softfp/iq80310.specs\n@static-lib arm-none-eabi/lib/arm/v5te/softfp/libc.a\n@static-lib arm-none-eabi/lib/arm/v5te/softfp/libg.a\n@static-lib arm-none-eabi/lib/arm/v5te/softfp/libgloss-linux.a\n@static-lib arm-none-eabi/lib/arm/v5te/softfp/libm.a\n@static-lib arm-none-eabi/lib/arm/v5te/softfp/libnosys.a\n@static-lib arm-none-eabi/lib/arm/v5te/softfp/librdimon.a\n@static-lib arm-none-eabi/lib/arm/v5te/softfp/librdpmon.a\narm-none-eabi/lib/arm/v5te/softfp/linux-crt0.o\narm-none-eabi/lib/arm/v5te/softfp/linux.specs\narm-none-eabi/lib/arm/v5te/softfp/nano.specs\narm-none-eabi/lib/arm/v5te/softfp/nosys.specs\narm-none-eabi/lib/arm/v5te/softfp/pid.specs\narm-none-eabi/lib/arm/v5te/softfp/rdimon-crt0.o\narm-none-eabi/lib/arm/v5te/softfp/rdimon.specs\narm-none-eabi/lib/arm/v5te/softfp/rdpmon-crt0.o\narm-none-eabi/lib/arm/v5te/softfp/rdpmon.specs\narm-none-eabi/lib/arm/v5te/softfp/redboot-crt0.o\narm-none-eabi/lib/arm/v5te/softfp/redboot-syscalls.o\narm-none-eabi/lib/arm/v5te/softfp/redboot.ld\narm-none-eabi/lib/arm/v5te/softfp/redboot.specs\narm-none-eabi/lib/cpu-init/\narm-none-eabi/lib/cpu-init/rdimon-aem.o\narm-none-eabi/lib/crt0.o\narm-none-eabi/lib/iq80310.specs\n@static-lib arm-none-eabi/lib/libc.a\n@static-lib arm-none-eabi/lib/libg.a\n@static-lib arm-none-eabi/lib/libgloss-linux.a\n@static-lib arm-none-eabi/lib/libm.a\n@static-lib arm-none-eabi/lib/libnosys.a\n@static-lib arm-none-eabi/lib/librdimon.a\n@static-lib arm-none-eabi/lib/librdpmon.a\narm-none-eabi/lib/linux-crt0.o\narm-none-eabi/lib/linux.specs\narm-none-eabi/lib/nano.specs\narm-none-eabi/lib/nosys.specs\narm-none-eabi/lib/pid.specs\narm-none-eabi/lib/rdimon-crt0.o\narm-none-eabi/lib/rdimon.specs\narm-none-eabi/lib/rdpmon-crt0.o\narm-none-eabi/lib/rdpmon.specs\narm-none-eabi/lib/redboot-crt0.o\narm-none-eabi/lib/redboot-syscalls.o\narm-none-eabi/lib/redboot.ld\narm-none-eabi/lib/redboot.specs\narm-none-eabi/lib/thumb/\narm-none-eabi/lib/thumb/nofp/\narm-none-eabi/lib/thumb/nofp/aprofile-validation.specs\narm-none-eabi/lib/thumb/nofp/aprofile-ve.specs\narm-none-eabi/lib/thumb/nofp/cpu-init/\narm-none-eabi/lib/thumb/nofp/cpu-init/rdimon-aem.o\narm-none-eabi/lib/thumb/nofp/crt0.o\narm-none-eabi/lib/thumb/nofp/iq80310.specs\n@static-lib arm-none-eabi/lib/thumb/nofp/libc.a\n@static-lib arm-none-eabi/lib/thumb/nofp/libg.a\n@static-lib arm-none-eabi/lib/thumb/nofp/libgloss-linux.a\n@static-lib arm-none-eabi/lib/thumb/nofp/libm.a\n@static-lib arm-none-eabi/lib/thumb/nofp/libnosys.a\n@static-lib arm-none-eabi/lib/thumb/nofp/librdimon.a\n@static-lib arm-none-eabi/lib/thumb/nofp/librdpmon.a\narm-none-eabi/lib/thumb/nofp/linux-crt0.o\narm-none-eabi/lib/thumb/nofp/linux.specs\narm-none-eabi/lib/thumb/nofp/nano.specs\narm-none-eabi/lib/thumb/nofp/nosys.specs\narm-none-eabi/lib/thumb/nofp/pid.specs\narm-none-eabi/lib/thumb/nofp/rdimon-crt0.o\narm-none-eabi/lib/thumb/nofp/rdimon.specs\narm-none-eabi/lib/thumb/nofp/rdpmon-crt0.o\narm-none-eabi/lib/thumb/nofp/rdpmon.specs\narm-none-eabi/lib/thumb/nofp/redboot-crt0.o\narm-none-eabi/lib/thumb/nofp/redboot-syscalls.o\narm-none-eabi/lib/thumb/nofp/redboot.ld\narm-none-eabi/lib/thumb/nofp/redboot.specs\narm-none-eabi/lib/thumb/v6-m/\narm-none-eabi/lib/thumb/v6-m/nofp/\narm-none-eabi/lib/thumb/v6-m/nofp/aprofile-validation.specs\narm-none-eabi/lib/thumb/v6-m/nofp/aprofile-ve.specs\narm-none-eabi/lib/thumb/v6-m/nofp/cpu-init/\narm-none-eabi/lib/thumb/v6-m/nofp/cpu-init/rdimon-aem.o\narm-none-eabi/lib/thumb/v6-m/nofp/crt0.o\narm-none-eabi/lib/thumb/v6-m/nofp/iq80310.specs\n@static-lib arm-none-eabi/lib/thumb/v6-m/nofp/libc.a\n@static-lib arm-none-eabi/lib/thumb/v6-m/nofp/libg.a\n@static-lib arm-none-eabi/lib/thumb/v6-m/nofp/libgloss-linux.a\n@static-lib arm-none-eabi/lib/thumb/v6-m/nofp/libm.a\n@static-lib arm-none-eabi/lib/thumb/v6-m/nofp/libnosys.a\n@static-lib arm-none-eabi/lib/thumb/v6-m/nofp/librdimon.a\n@static-lib arm-none-eabi/lib/thumb/v6-m/nofp/librdpmon.a\narm-none-eabi/lib/thumb/v6-m/nofp/linux-crt0.o\narm-none-eabi/lib/thumb/v6-m/nofp/linux.specs\narm-none-eabi/lib/thumb/v6-m/nofp/nano.specs\narm-none-eabi/lib/thumb/v6-m/nofp/nosys.specs\narm-none-eabi/lib/thumb/v6-m/nofp/pid.specs\narm-none-eabi/lib/thumb/v6-m/nofp/rdimon-crt0.o\narm-none-eabi/lib/thumb/v6-m/nofp/rdimon.specs\narm-none-eabi/lib/thumb/v6-m/nofp/rdpmon-crt0.o\narm-none-eabi/lib/thumb/v6-m/nofp/rdpmon.specs\narm-none-eabi/lib/thumb/v6-m/nofp/redboot-crt0.o\narm-none-eabi/lib/thumb/v6-m/nofp/redboot-syscalls.o\narm-none-eabi/lib/thumb/v6-m/nofp/redboot.ld\narm-none-eabi/lib/thumb/v6-m/nofp/redboot.specs\narm-none-eabi/lib/thumb/v7/\narm-none-eabi/lib/thumb/v7+fp/\narm-none-eabi/lib/thumb/v7+fp/hard/\narm-none-eabi/lib/thumb/v7+fp/hard/aprofile-validation.specs\narm-none-eabi/lib/thumb/v7+fp/hard/aprofile-ve.specs\narm-none-eabi/lib/thumb/v7+fp/hard/cpu-init/\narm-none-eabi/lib/thumb/v7+fp/hard/cpu-init/rdimon-aem.o\narm-none-eabi/lib/thumb/v7+fp/hard/crt0.o\narm-none-eabi/lib/thumb/v7+fp/hard/iq80310.specs\n@static-lib arm-none-eabi/lib/thumb/v7+fp/hard/libc.a\n@static-lib arm-none-eabi/lib/thumb/v7+fp/hard/libg.a\n@static-lib arm-none-eabi/lib/thumb/v7+fp/hard/libgloss-linux.a\n@static-lib arm-none-eabi/lib/thumb/v7+fp/hard/libm.a\n@static-lib arm-none-eabi/lib/thumb/v7+fp/hard/libnosys.a\n@static-lib arm-none-eabi/lib/thumb/v7+fp/hard/librdimon.a\n@static-lib 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arm-none-eabi/lib/thumb/v8-m.main+fp/softfp/libc.a\n@static-lib arm-none-eabi/lib/thumb/v8-m.main+fp/softfp/libg.a\n@static-lib arm-none-eabi/lib/thumb/v8-m.main+fp/softfp/libgloss-linux.a\n@static-lib arm-none-eabi/lib/thumb/v8-m.main+fp/softfp/libm.a\n@static-lib arm-none-eabi/lib/thumb/v8-m.main+fp/softfp/libnosys.a\n@static-lib arm-none-eabi/lib/thumb/v8-m.main+fp/softfp/librdimon.a\n@static-lib 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arm-none-eabi/lib/thumb/v8-m.main/nofp/libc.a\n@static-lib arm-none-eabi/lib/thumb/v8-m.main/nofp/libg.a\n@static-lib arm-none-eabi/lib/thumb/v8-m.main/nofp/libgloss-linux.a\n@static-lib arm-none-eabi/lib/thumb/v8-m.main/nofp/libm.a\n@static-lib arm-none-eabi/lib/thumb/v8-m.main/nofp/libnosys.a\n@static-lib arm-none-eabi/lib/thumb/v8-m.main/nofp/librdimon.a\n@static-lib arm-none-eabi/lib/thumb/v8-m.main/nofp/librdpmon.a\narm-none-eabi/lib/thumb/v8-m.main/nofp/linux-crt0.o\narm-none-eabi/lib/thumb/v8-m.main/nofp/linux.specs\narm-none-eabi/lib/thumb/v8-m.main/nofp/nano.specs\narm-none-eabi/lib/thumb/v8-m.main/nofp/nosys.specs\narm-none-eabi/lib/thumb/v8-m.main/nofp/pid.specs\narm-none-eabi/lib/thumb/v8-m.main/nofp/rdimon-crt0.o\narm-none-eabi/lib/thumb/v8-m.main/nofp/rdimon.specs\narm-none-eabi/lib/thumb/v8-m.main/nofp/rdpmon-crt0.o\narm-none-eabi/lib/thumb/v8-m.main/nofp/rdpmon.specs\narm-none-eabi/lib/thumb/v8-m.main/nofp/redboot-crt0.o\narm-none-eabi/lib/thumb/v8-m.main/nofp/redboot-syscalls.o\narm-none-eabi/lib/thumb/v8-m.main/nofp/redboot.ld\narm-none-eabi/lib/thumb/v8-m.main/nofp/redboot.specs\narm-none-eabi/lib/thumb/v8.1-m.main+mve/\narm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/\narm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/aprofile-validation.specs\narm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/aprofile-ve.specs\narm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/cpu-init/\narm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/cpu-init/rdimon-aem.o\narm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/crt0.o\narm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/iq80310.specs\n@static-lib arm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/libc.a\n@static-lib arm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/libg.a\n@static-lib arm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/libgloss-linux.a\n@static-lib arm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/libm.a\n@static-lib arm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/libnosys.a\n@static-lib arm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/librdimon.a\n@static-lib arm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/librdpmon.a\narm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/linux-crt0.o\narm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/linux.specs\narm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/nano.specs\narm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/nosys.specs\narm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/pid.specs\narm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/rdimon-crt0.o\narm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/rdimon.specs\narm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/rdpmon-crt0.o\narm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/rdpmon.specs\narm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/redboot-crt0.o\narm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/redboot-syscalls.o\narm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/redboot.ld\narm-none-eabi/lib/thumb/v8.1-m.main+mve/hard/redboot.specs\nshare/doc/arm-none-eabi/\nshare/doc/arm-none-eabi/newlib/\nshare/doc/arm-none-eabi/newlib/COPYING.NEWLIB\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/Makefile",
    "content": "SUBDIR =\nSUBDIR += binutils\nSUBDIR += gcc\n\n.include <bsd.port.subdir.mk>\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/Makefile.inc",
    "content": "CONFIG=\t\tmips-elf\nPKGNAME?=\t${CONFIG}-${DISTNAME}\nFULLPKGNAME?=\t${PKGNAME}\nCATEGORIES+=\tdevel\n\n# GPLv3\n# For newlib: multiple copyrights, but basically BSD.\n#   See: ${PREFIX}/share/doc/newlib\nPERMIT_PACKAGE=\tYes\n\n# XXX at least gmkdir gets picked up if present\nBUILD_DEPENDS +=\tsysutils/coreutils\n\nCONFIGURE_STYLE=gnu\nCONFIGURE_ARGS+=--target=${CONFIG}  \\\n\t\t--disable-shared    \\\n\t\t--disable-nls\t    \\\n\t\t--disable-werror\n\nEXTRACT_SUFX?=\t.tar.xz\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/binutils/Makefile",
    "content": "COMMENT=\tbinutils for ${CONFIG} cross-development\n\nVERSION=\t2.40\nDISTNAME=\tbinutils-${VERSION}\n\nHOMEPAGE=\thttps://www.gnu.org/software/binutils/\n\nWANTLIB=\tc\n\nSITES=\t\t${SITE_GNU:=binutils/}\nDIST_SUBDIR=\tbinutils\n\nUSE_GMAKE=\tYes\nUSE_LIBTOOL=\tNo\n\nCONFIGURE_ARGS+=--enable-commonbfdlib=no\t\\\n\t\t--enable-interwork\t\t\\\n\t\t--enable-multilib\t\t\\\n\t\t--without-zstd\n\nSUBST_VARS+=\tCONFIG\n\n.include <bsd.port.mk>\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/binutils/distinfo",
    "content": "SHA256 (binutils/binutils-2.40.tar.xz) = D4pMJy1/F/Np3tEKSsoouOMEgo6VUm2kgrDMxN/J2OE=\nSIZE (binutils/binutils-2.40.tar.xz) = 25241484\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/binutils/patches/patch-bfd_Makefile_in",
    "content": "Index: bfd/Makefile.in\n--- bfd/Makefile.in.orig\n+++ bfd/Makefile.in\n@@ -266,7 +266,7 @@ am__v_texidevnull_ = $(am__v_texidevnull_@AM_DEFAULT_V\n am__v_texidevnull_0 = > /dev/null\n am__v_texidevnull_1 = \n am__dirstamp = $(am__leading_dot)dirstamp\n-INFO_DEPS = doc/bfd.info\n+INFO_DEPS =\n am__TEXINFO_TEX_DIR = $(srcdir)\n DVIS = doc/bfd.dvi\n PDFS = doc/bfd.pdf\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/binutils/patches/patch-binutils_Makefile_in",
    "content": "Index: binutils/Makefile.in\n--- binutils/Makefile.in.orig\n+++ binutils/Makefile.in\n@@ -404,7 +404,7 @@ AM_V_texidevnull = $(am__v_texidevnull_@AM_V@)\n am__v_texidevnull_ = $(am__v_texidevnull_@AM_DEFAULT_V@)\n am__v_texidevnull_0 = > /dev/null\n am__v_texidevnull_1 = \n-INFO_DEPS = doc/binutils.info\n+INFO_DEPS =\n am__TEXINFO_TEX_DIR = $(srcdir)\n DVIS = doc/binutils.dvi\n PDFS = doc/binutils.pdf\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/binutils/patches/patch-gas_Makefile_in",
    "content": "Index: gas/Makefile.in\n--- gas/Makefile.in.orig\n+++ gas/Makefile.in\n@@ -270,7 +270,7 @@ AM_V_texidevnull = $(am__v_texidevnull_@AM_V@)\n am__v_texidevnull_ = $(am__v_texidevnull_@AM_DEFAULT_V@)\n am__v_texidevnull_0 = > /dev/null\n am__v_texidevnull_1 = \n-INFO_DEPS = doc/as.info\n+INFO_DEPS =\n TEXINFO_TEX = $(top_srcdir)/../texinfo.tex\n am__TEXINFO_TEX_DIR = $(top_srcdir)/..\n DVIS = doc/as.dvi\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/binutils/patches/patch-gprof_Makefile_in",
    "content": "Index: gprof/Makefile.in\n--- gprof/Makefile.in.orig\n+++ gprof/Makefile.in\n@@ -217,7 +217,7 @@ AM_V_texidevnull = $(am__v_texidevnull_@AM_V@)\n am__v_texidevnull_ = $(am__v_texidevnull_@AM_DEFAULT_V@)\n am__v_texidevnull_0 = > /dev/null\n am__v_texidevnull_1 = \n-INFO_DEPS = gprof.info\n+INFO_DEPS =\n am__TEXINFO_TEX_DIR = $(srcdir)/../texinfo\n DVIS = gprof.dvi\n PDFS = gprof.pdf\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/binutils/patches/patch-ld_Makefile_in",
    "content": "Index: ld/Makefile.in\n--- ld/Makefile.in.orig\n+++ ld/Makefile.in\n@@ -301,7 +301,7 @@ AM_V_texidevnull = $(am__v_texidevnull_@AM_V@)\n am__v_texidevnull_ = $(am__v_texidevnull_@AM_DEFAULT_V@)\n am__v_texidevnull_0 = > /dev/null\n am__v_texidevnull_1 = \n-INFO_DEPS = ld.info\n+INFO_DEPS =\n am__TEXINFO_TEX_DIR = $(srcdir)/../texinfo\n DVIS = ld.dvi\n PDFS = ld.pdf\n@@ -1042,7 +1042,7 @@ libldtestplug4_la_SOURCES = testplug4.c\n libldtestplug4_la_CFLAGS = -g -O2\n libldtestplug4_la_LDFLAGS = -no-undefined -rpath /nowhere\n bfdplugindir = $(libdir)/bfd-plugins\n-bfdplugin_LTLIBRARIES = libdep.la\n+bfdplugin_LTLIBRARIES =\n libdep_la_SOURCES = libdep_plugin.c\n libdep_la_LDFLAGS = -no-undefined -rpath /nowhere -module -avoid-version\n libdep_la_LINK = $(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) \\\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/binutils/patches/patch-libctf_Makefile_in",
    "content": "Index: libctf/Makefile.in\n--- libctf/Makefile.in.orig\n+++ libctf/Makefile.in\n@@ -306,7 +306,7 @@ am__v_texidevnull_ = $(am__v_texidevnull_@AM_DEFAULT_V\n am__v_texidevnull_0 = > /dev/null\n am__v_texidevnull_1 = \n am__dirstamp = $(am__leading_dot)dirstamp\n-INFO_DEPS = doc/ctf-spec.info\n+INFO_DEPS =\n am__TEXINFO_TEX_DIR = $(srcdir)\n DVIS = doc/ctf-spec.dvi\n PDFS = doc/ctf-spec.pdf\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/binutils/patches/patch-libiberty_Makefile_in",
    "content": "Index: libiberty/Makefile.in\n--- libiberty/Makefile.in.orig\n+++ libiberty/Makefile.in\n@@ -376,7 +376,7 @@ libiberty.html : $(srcdir)/libiberty.texi $(TEXISRC)\n @MAINT@\techo stamp > stamp-functions\n \n INSTALL_DEST = @INSTALL_DEST@\n-install: install_to_$(INSTALL_DEST) install-subdir\n+install:\n install-strip: install\n \n .PHONY: install install-strip\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/binutils/patches/patch-libsframe_Makefile_in",
    "content": "Index: libsframe/Makefile.in\n--- libsframe/Makefile.in.orig\n+++ libsframe/Makefile.in\n@@ -276,7 +276,7 @@ AM_V_texidevnull = $(am__v_texidevnull_@AM_V@)\n am__v_texidevnull_ = $(am__v_texidevnull_@AM_DEFAULT_V@)\n am__v_texidevnull_0 = > /dev/null\n am__v_texidevnull_1 = \n-INFO_DEPS = doc/sframe-spec.info\n+INFO_DEPS =\n am__TEXINFO_TEX_DIR = $(srcdir)\n DVIS = doc/sframe-spec.dvi\n PDFS = doc/sframe-spec.pdf\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/binutils/pkg/DESCR",
    "content": "GNU Binutils collection, configured for the ${CONFIG} target.\n  * ld - the GNU linker.\n  * as - the GNU assembler.\n\nBut they also include:\n  * addr2line - Converts addresses into filenames and line numbers.\n  * ar - A utility for creating, modifying and extracting from\n    archives.\n  * c++filt - Filter to demangle encoded C++ symbols.\n  * gprof - Displays profiling information.\n  * nlmconv - Converts object code into an NLM.\n  * nm - Lists symbols from object files.\n  * objcopy - Copys and translates object files.\n  * objdump - Displays information from object files.\n  * ranlib - Generates an index to the contents of an archive.\n  * readelf - Displays information from any ELF format object file.\n  * size - Lists the section sizes of an object or archive file.\n  * strings - Lists printable strings from files.\n  * strip - Discards symbols.\n  * windres - A compiler for Windows resource files.\n\nMost of these programs use BFD, the Binary File Descriptor library, to\ndo low-level manipulation. Many of them also use the opcodes library\nto assemble and disassemble machine instructions.\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/binutils/pkg/PLIST",
    "content": "@comment @info info/bfd.info\n@comment @info info/binutils.info\n@comment @info info/gprof.info\n@comment @info info/ld.info\n@bin bin/${CONFIG}-addr2line\n@bin bin/${CONFIG}-ar\n@bin bin/${CONFIG}-as\n@bin bin/${CONFIG}-c++filt\n@bin bin/${CONFIG}-elfedit\n@bin bin/${CONFIG}-ld\n@bin bin/${CONFIG}-ld.bfd\n@bin bin/${CONFIG}-nm\n@bin bin/${CONFIG}-objcopy\n@bin bin/${CONFIG}-objdump\n@bin bin/${CONFIG}-ranlib\n@bin bin/${CONFIG}-readelf\n@bin bin/${CONFIG}-size\n@bin bin/${CONFIG}-strings\n@bin bin/${CONFIG}-strip\n@man man/man1/${CONFIG}-addr2line.1\n@man man/man1/${CONFIG}-ar.1\n@man man/man1/${CONFIG}-as.1\n@man man/man1/${CONFIG}-c++filt.1\n@man man/man1/${CONFIG}-dlltool.1\n@man man/man1/${CONFIG}-elfedit.1\n@man man/man1/${CONFIG}-ld.1\n@man man/man1/${CONFIG}-nm.1\n@man man/man1/${CONFIG}-objcopy.1\n@man man/man1/${CONFIG}-objdump.1\n@man man/man1/${CONFIG}-ranlib.1\n@man man/man1/${CONFIG}-readelf.1\n@man man/man1/${CONFIG}-size.1\n@man man/man1/${CONFIG}-strings.1\n@man man/man1/${CONFIG}-strip.1\n@man man/man1/${CONFIG}-windmc.1\n@man man/man1/${CONFIG}-windres.1\n${CONFIG}/\n${CONFIG}/bin/\n@bin ${CONFIG}/bin/ar\n@bin ${CONFIG}/bin/as\n@bin ${CONFIG}/bin/ld\n@bin ${CONFIG}/bin/ld.bfd\n@bin ${CONFIG}/bin/nm\n@bin ${CONFIG}/bin/objcopy\n@bin ${CONFIG}/bin/objdump\n@bin ${CONFIG}/bin/ranlib\n@bin ${CONFIG}/bin/readelf\n@bin ${CONFIG}/bin/strip\n${CONFIG}/lib/\n${CONFIG}/lib/ldscripts/\n${CONFIG}/lib/ldscripts/elf32ebmip.x\n${CONFIG}/lib/ldscripts/elf32ebmip.xbn\n${CONFIG}/lib/ldscripts/elf32ebmip.xc\n${CONFIG}/lib/ldscripts/elf32ebmip.xce\n${CONFIG}/lib/ldscripts/elf32ebmip.xd\n${CONFIG}/lib/ldscripts/elf32ebmip.xdc\n${CONFIG}/lib/ldscripts/elf32ebmip.xdce\n${CONFIG}/lib/ldscripts/elf32ebmip.xde\n${CONFIG}/lib/ldscripts/elf32ebmip.xdw\n${CONFIG}/lib/ldscripts/elf32ebmip.xdwe\n${CONFIG}/lib/ldscripts/elf32ebmip.xe\n${CONFIG}/lib/ldscripts/elf32ebmip.xn\n${CONFIG}/lib/ldscripts/elf32ebmip.xr\n${CONFIG}/lib/ldscripts/elf32ebmip.xs\n${CONFIG}/lib/ldscripts/elf32ebmip.xsc\n${CONFIG}/lib/ldscripts/elf32ebmip.xsce\n${CONFIG}/lib/ldscripts/elf32ebmip.xse\n${CONFIG}/lib/ldscripts/elf32ebmip.xsw\n${CONFIG}/lib/ldscripts/elf32ebmip.xswe\n${CONFIG}/lib/ldscripts/elf32ebmip.xu\n${CONFIG}/lib/ldscripts/elf32ebmip.xw\n${CONFIG}/lib/ldscripts/elf32ebmip.xwe\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/gcc/Makefile",
    "content": "COMMENT=\tgcc for ${CONFIG} cross-development\n\nVERSION=\t12.2.0\nDISTNAME=\tgcc-${VERSION}\nPKGNAME=\t${CONFIG}-gcc-${VERSION}\n\nSHARED_LIBS+=\tlto_plugin                0.0 # 0.0\n\nSUBST_VARS+=\tVERSION\n\nWANTLIB=\t${COMPILER_LIBCXX} c gmp m mpc mpfr pthread\nDIST_SUBDIR=\tgcc\n\nCOMPILER=\tbase-clang ports-gcc base-gcc\n\nMAKE_GXX=\tNo\nMAKE_FORTRAN=\tNo\nMAKE_OBJC=\tNo\nMAKE_JAVA=\tNo\nMAKE_ADA=\tNo\n\nSITES=\t\t${SITE_GCC:=releases/gcc-${VERSION}/}\n\nBUILD_DEPENDS+=\t${RUN_DEPENDS} \\\n\t\tdevel/bison\n\nLIB_DEPENDS=\tdevel/mpfr \\\n\t\tdevel/libmpc\n\nRUN_DEPENDS=\tdevel/${CONFIG}/binutils\n\n#LANGS=\t\tc,c++\nLANGS=\t\tc\nCFLAGS=\t\t-O2 -g\n\nCONFIGURE_ARGS+=--enable-languages=${LANGS} \\\n\t\t--with-arch-32=mips32r2 \\\n\t\t--with-gmp=\"${LOCALBASE}\" \\\n\t\t--with-mpc=\"${LOCALBASE}\" \\\n\t\t--with-mpfr=\"${LOCALBASE}\" \\\n\t\t--without-isl \\\n\t\t--without-zstd \\\n\t\t--disable-libssp \\\n\t\t--with-newlib \\\n\t\t--disable-libstdc___v3 \\\n\t\t--disable-libcc1 \\\n\t\t--disable-nls \\\n\t\t--disable-shared \\\n\t\t--disable-decimal-float \\\n\t\t--disable-threads \\\n\t\t--disable-libmudflap \\\n\t\t--disable-libgomp \\\n\t\t--disable-libquadmath \\\n\t\t--enable-multilib \\\n\t\t--enable-cpp \\\n\t\t--enable-lto\nCONFIGURE_ENV=\tCPPFLAGS=\"${CPPFLAGS} -I${LOCALBASE}/include\" \\\n\t\tLDFLAGS=\"-L${LOCALBASE}/lib\"\n\n# Avoid build failure when lang/gcc/8 is installed whose ansidecl.h misses these\nCPPFLAGS+=\t-DATTRIBUTE_NONSTRING= -DATTRIBUTE_RESULT_SIZE_1=\nCPPFLAGS+=\t-DATTRIBUTE_RESULT_SIZE_2= -DATTRIBUTE_RESULT_SIZE_1_2=\nCPPFLAGS+=\t-DATTRIBUTE_WARN_UNUSED_RESULT=\n\nSEPARATE_BUILD=\tYes\nUSE_GMAKE=\tYes\nYACC=\t\tbison\n\npost-install:\n\tchown -R ${SHAREOWN}:${SHAREGRP} \\\n\t\t${PREFIX}/lib/gcc/${CONFIG}/${VERSION}/\n\n.include <bsd.port.mk>\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/gcc/distinfo",
    "content": "SHA256 (gcc/gcc-12.2.0.tar.xz) = 5UnPnPNZSgDie2WJ1DItcOByDN0hPzm+tBgeBpJiMP8=\nSIZE (gcc/gcc-12.2.0.tar.xz) = 84645292\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/gcc/patches/patch-Makefile_in",
    "content": "Index: Makefile.in\n--- Makefile.in.orig\n+++ Makefile.in\n@@ -1116,29 +1116,8 @@ configure-host:  \\\n     maybe-configure-libctf\n .PHONY: configure-target\n configure-target:  \\\n-    maybe-configure-target-libstdc++-v3 \\\n-    maybe-configure-target-libsanitizer \\\n-    maybe-configure-target-libvtv \\\n-    maybe-configure-target-liboffloadmic \\\n-    maybe-configure-target-libssp \\\n     maybe-configure-target-newlib \\\n-    maybe-configure-target-libgcc \\\n-    maybe-configure-target-libbacktrace \\\n-    maybe-configure-target-libquadmath \\\n-    maybe-configure-target-libgfortran \\\n-    maybe-configure-target-libobjc \\\n-    maybe-configure-target-libgo \\\n-    maybe-configure-target-libphobos \\\n-    maybe-configure-target-libtermcap \\\n-    maybe-configure-target-winsup \\\n-    maybe-configure-target-libgloss \\\n-    maybe-configure-target-libffi \\\n-    maybe-configure-target-zlib \\\n-    maybe-configure-target-rda \\\n-    maybe-configure-target-libada \\\n-    maybe-configure-target-libgomp \\\n-    maybe-configure-target-libitm \\\n-    maybe-configure-target-libatomic\n+    maybe-configure-target-libgcc\n \n # The target built for a native non-bootstrap build.\n .PHONY: all\n@@ -1296,47 +1275,10 @@ all-host: maybe-all-libctf\n \n .PHONY: all-target\n \n-@if target-libstdc++-v3-no-bootstrap\n-all-target: maybe-all-target-libstdc++-v3\n-@endif target-libstdc++-v3-no-bootstrap\n-@if target-libsanitizer-no-bootstrap\n-all-target: maybe-all-target-libsanitizer\n-@endif target-libsanitizer-no-bootstrap\n-@if target-libvtv-no-bootstrap\n-all-target: maybe-all-target-libvtv\n-@endif target-libvtv-no-bootstrap\n-all-target: maybe-all-target-liboffloadmic\n-all-target: maybe-all-target-libssp\n all-target: maybe-all-target-newlib\n @if target-libgcc-no-bootstrap\n all-target: maybe-all-target-libgcc\n @endif target-libgcc-no-bootstrap\n-@if target-libbacktrace-no-bootstrap\n-all-target: maybe-all-target-libbacktrace\n-@endif target-libbacktrace-no-bootstrap\n-all-target: maybe-all-target-libquadmath\n-all-target: maybe-all-target-libgfortran\n-all-target: maybe-all-target-libobjc\n-all-target: maybe-all-target-libgo\n-@if target-libphobos-no-bootstrap\n-all-target: maybe-all-target-libphobos\n-@endif target-libphobos-no-bootstrap\n-all-target: maybe-all-target-libtermcap\n-all-target: maybe-all-target-winsup\n-all-target: maybe-all-target-libgloss\n-all-target: maybe-all-target-libffi\n-@if target-zlib-no-bootstrap\n-all-target: maybe-all-target-zlib\n-@endif target-zlib-no-bootstrap\n-all-target: maybe-all-target-rda\n-all-target: maybe-all-target-libada\n-@if target-libgomp-no-bootstrap\n-all-target: maybe-all-target-libgomp\n-@endif target-libgomp-no-bootstrap\n-all-target: maybe-all-target-libitm\n-@if target-libatomic-no-bootstrap\n-all-target: maybe-all-target-libatomic\n-@endif target-libatomic-no-bootstrap\n \n # Do a target for all the subdirectories.  A ``make do-X'' will do a\n # ``make X'' in all subdirectories (because, in general, there is a\n@@ -1409,29 +1351,8 @@ info-host: maybe-info-libctf\n \n .PHONY: info-target\n \n-info-target: maybe-info-target-libstdc++-v3\n-info-target: maybe-info-target-libsanitizer\n-info-target: maybe-info-target-libvtv\n-info-target: maybe-info-target-liboffloadmic\n-info-target: maybe-info-target-libssp\n info-target: maybe-info-target-newlib\n info-target: maybe-info-target-libgcc\n-info-target: maybe-info-target-libbacktrace\n-info-target: maybe-info-target-libquadmath\n-info-target: maybe-info-target-libgfortran\n-info-target: maybe-info-target-libobjc\n-info-target: maybe-info-target-libgo\n-info-target: maybe-info-target-libphobos\n-info-target: maybe-info-target-libtermcap\n-info-target: maybe-info-target-winsup\n-info-target: maybe-info-target-libgloss\n-info-target: maybe-info-target-libffi\n-info-target: maybe-info-target-zlib\n-info-target: maybe-info-target-rda\n-info-target: maybe-info-target-libada\n-info-target: maybe-info-target-libgomp\n-info-target: maybe-info-target-libitm\n-info-target: maybe-info-target-libatomic\n \n .PHONY: do-dvi\n do-dvi:\n@@ -1499,29 +1420,8 @@ dvi-host: maybe-dvi-libctf\n \n .PHONY: dvi-target\n \n-dvi-target: maybe-dvi-target-libstdc++-v3\n-dvi-target: maybe-dvi-target-libsanitizer\n-dvi-target: maybe-dvi-target-libvtv\n-dvi-target: maybe-dvi-target-liboffloadmic\n-dvi-target: maybe-dvi-target-libssp\n dvi-target: maybe-dvi-target-newlib\n dvi-target: maybe-dvi-target-libgcc\n-dvi-target: maybe-dvi-target-libbacktrace\n-dvi-target: maybe-dvi-target-libquadmath\n-dvi-target: maybe-dvi-target-libgfortran\n-dvi-target: maybe-dvi-target-libobjc\n-dvi-target: maybe-dvi-target-libgo\n-dvi-target: maybe-dvi-target-libphobos\n-dvi-target: maybe-dvi-target-libtermcap\n-dvi-target: maybe-dvi-target-winsup\n-dvi-target: maybe-dvi-target-libgloss\n-dvi-target: maybe-dvi-target-libffi\n-dvi-target: maybe-dvi-target-zlib\n-dvi-target: maybe-dvi-target-rda\n-dvi-target: maybe-dvi-target-libada\n-dvi-target: maybe-dvi-target-libgomp\n-dvi-target: maybe-dvi-target-libitm\n-dvi-target: maybe-dvi-target-libatomic\n \n .PHONY: do-pdf\n do-pdf:\n@@ -1589,29 +1489,8 @@ pdf-host: maybe-pdf-libctf\n \n .PHONY: pdf-target\n \n-pdf-target: maybe-pdf-target-libstdc++-v3\n-pdf-target: maybe-pdf-target-libsanitizer\n-pdf-target: maybe-pdf-target-libvtv\n-pdf-target: maybe-pdf-target-liboffloadmic\n-pdf-target: maybe-pdf-target-libssp\n pdf-target: maybe-pdf-target-newlib\n pdf-target: maybe-pdf-target-libgcc\n-pdf-target: maybe-pdf-target-libbacktrace\n-pdf-target: maybe-pdf-target-libquadmath\n-pdf-target: maybe-pdf-target-libgfortran\n-pdf-target: maybe-pdf-target-libobjc\n-pdf-target: maybe-pdf-target-libgo\n-pdf-target: maybe-pdf-target-libphobos\n-pdf-target: maybe-pdf-target-libtermcap\n-pdf-target: maybe-pdf-target-winsup\n-pdf-target: maybe-pdf-target-libgloss\n-pdf-target: maybe-pdf-target-libffi\n-pdf-target: maybe-pdf-target-zlib\n-pdf-target: maybe-pdf-target-rda\n-pdf-target: maybe-pdf-target-libada\n-pdf-target: maybe-pdf-target-libgomp\n-pdf-target: maybe-pdf-target-libitm\n-pdf-target: maybe-pdf-target-libatomic\n \n .PHONY: do-html\n do-html:\n@@ -1679,29 +1558,8 @@ html-host: maybe-html-libctf\n \n .PHONY: html-target\n \n-html-target: maybe-html-target-libstdc++-v3\n-html-target: maybe-html-target-libsanitizer\n-html-target: maybe-html-target-libvtv\n-html-target: maybe-html-target-liboffloadmic\n-html-target: maybe-html-target-libssp\n html-target: maybe-html-target-newlib\n html-target: maybe-html-target-libgcc\n-html-target: maybe-html-target-libbacktrace\n-html-target: maybe-html-target-libquadmath\n-html-target: maybe-html-target-libgfortran\n-html-target: maybe-html-target-libobjc\n-html-target: maybe-html-target-libgo\n-html-target: maybe-html-target-libphobos\n-html-target: maybe-html-target-libtermcap\n-html-target: maybe-html-target-winsup\n-html-target: maybe-html-target-libgloss\n-html-target: maybe-html-target-libffi\n-html-target: maybe-html-target-zlib\n-html-target: maybe-html-target-rda\n-html-target: maybe-html-target-libada\n-html-target: maybe-html-target-libgomp\n-html-target: maybe-html-target-libitm\n-html-target: maybe-html-target-libatomic\n \n .PHONY: do-TAGS\n do-TAGS:\n@@ -1769,29 +1627,8 @@ TAGS-host: maybe-TAGS-libctf\n \n .PHONY: TAGS-target\n \n-TAGS-target: maybe-TAGS-target-libstdc++-v3\n-TAGS-target: maybe-TAGS-target-libsanitizer\n-TAGS-target: maybe-TAGS-target-libvtv\n-TAGS-target: maybe-TAGS-target-liboffloadmic\n-TAGS-target: maybe-TAGS-target-libssp\n TAGS-target: maybe-TAGS-target-newlib\n TAGS-target: maybe-TAGS-target-libgcc\n-TAGS-target: maybe-TAGS-target-libbacktrace\n-TAGS-target: maybe-TAGS-target-libquadmath\n-TAGS-target: maybe-TAGS-target-libgfortran\n-TAGS-target: maybe-TAGS-target-libobjc\n-TAGS-target: maybe-TAGS-target-libgo\n-TAGS-target: maybe-TAGS-target-libphobos\n-TAGS-target: maybe-TAGS-target-libtermcap\n-TAGS-target: maybe-TAGS-target-winsup\n-TAGS-target: maybe-TAGS-target-libgloss\n-TAGS-target: maybe-TAGS-target-libffi\n-TAGS-target: maybe-TAGS-target-zlib\n-TAGS-target: maybe-TAGS-target-rda\n-TAGS-target: maybe-TAGS-target-libada\n-TAGS-target: maybe-TAGS-target-libgomp\n-TAGS-target: maybe-TAGS-target-libitm\n-TAGS-target: maybe-TAGS-target-libatomic\n \n .PHONY: do-install-info\n do-install-info:\n@@ -1859,29 +1696,8 @@ install-info-host: maybe-install-info-libctf\n \n .PHONY: install-info-target\n \n-install-info-target: maybe-install-info-target-libstdc++-v3\n-install-info-target: maybe-install-info-target-libsanitizer\n-install-info-target: maybe-install-info-target-libvtv\n-install-info-target: maybe-install-info-target-liboffloadmic\n-install-info-target: maybe-install-info-target-libssp\n install-info-target: maybe-install-info-target-newlib\n install-info-target: maybe-install-info-target-libgcc\n-install-info-target: maybe-install-info-target-libbacktrace\n-install-info-target: maybe-install-info-target-libquadmath\n-install-info-target: maybe-install-info-target-libgfortran\n-install-info-target: maybe-install-info-target-libobjc\n-install-info-target: maybe-install-info-target-libgo\n-install-info-target: maybe-install-info-target-libphobos\n-install-info-target: maybe-install-info-target-libtermcap\n-install-info-target: maybe-install-info-target-winsup\n-install-info-target: maybe-install-info-target-libgloss\n-install-info-target: maybe-install-info-target-libffi\n-install-info-target: maybe-install-info-target-zlib\n-install-info-target: maybe-install-info-target-rda\n-install-info-target: maybe-install-info-target-libada\n-install-info-target: maybe-install-info-target-libgomp\n-install-info-target: maybe-install-info-target-libitm\n-install-info-target: maybe-install-info-target-libatomic\n \n .PHONY: do-install-dvi\n do-install-dvi:\n@@ -2039,29 +1855,8 @@ install-pdf-host: maybe-install-pdf-libctf\n \n .PHONY: install-pdf-target\n \n-install-pdf-target: maybe-install-pdf-target-libstdc++-v3\n-install-pdf-target: maybe-install-pdf-target-libsanitizer\n-install-pdf-target: maybe-install-pdf-target-libvtv\n-install-pdf-target: maybe-install-pdf-target-liboffloadmic\n-install-pdf-target: maybe-install-pdf-target-libssp\n install-pdf-target: maybe-install-pdf-target-newlib\n install-pdf-target: maybe-install-pdf-target-libgcc\n-install-pdf-target: maybe-install-pdf-target-libbacktrace\n-install-pdf-target: maybe-install-pdf-target-libquadmath\n-install-pdf-target: maybe-install-pdf-target-libgfortran\n-install-pdf-target: maybe-install-pdf-target-libobjc\n-install-pdf-target: maybe-install-pdf-target-libgo\n-install-pdf-target: maybe-install-pdf-target-libphobos\n-install-pdf-target: maybe-install-pdf-target-libtermcap\n-install-pdf-target: maybe-install-pdf-target-winsup\n-install-pdf-target: maybe-install-pdf-target-libgloss\n-install-pdf-target: maybe-install-pdf-target-libffi\n-install-pdf-target: maybe-install-pdf-target-zlib\n-install-pdf-target: maybe-install-pdf-target-rda\n-install-pdf-target: maybe-install-pdf-target-libada\n-install-pdf-target: maybe-install-pdf-target-libgomp\n-install-pdf-target: maybe-install-pdf-target-libitm\n-install-pdf-target: maybe-install-pdf-target-libatomic\n \n .PHONY: do-install-html\n do-install-html:\n@@ -2129,29 +1924,8 @@ install-html-host: maybe-install-html-libctf\n \n .PHONY: install-html-target\n \n-install-html-target: maybe-install-html-target-libstdc++-v3\n-install-html-target: maybe-install-html-target-libsanitizer\n-install-html-target: maybe-install-html-target-libvtv\n-install-html-target: maybe-install-html-target-liboffloadmic\n-install-html-target: maybe-install-html-target-libssp\n install-html-target: maybe-install-html-target-newlib\n install-html-target: maybe-install-html-target-libgcc\n-install-html-target: maybe-install-html-target-libbacktrace\n-install-html-target: maybe-install-html-target-libquadmath\n-install-html-target: maybe-install-html-target-libgfortran\n-install-html-target: maybe-install-html-target-libobjc\n-install-html-target: maybe-install-html-target-libgo\n-install-html-target: maybe-install-html-target-libphobos\n-install-html-target: maybe-install-html-target-libtermcap\n-install-html-target: maybe-install-html-target-winsup\n-install-html-target: maybe-install-html-target-libgloss\n-install-html-target: maybe-install-html-target-libffi\n-install-html-target: maybe-install-html-target-zlib\n-install-html-target: maybe-install-html-target-rda\n-install-html-target: maybe-install-html-target-libada\n-install-html-target: maybe-install-html-target-libgomp\n-install-html-target: maybe-install-html-target-libitm\n-install-html-target: maybe-install-html-target-libatomic\n \n .PHONY: do-installcheck\n do-installcheck:\n@@ -2219,29 +1993,8 @@ installcheck-host: maybe-installcheck-libctf\n \n .PHONY: installcheck-target\n \n-installcheck-target: maybe-installcheck-target-libstdc++-v3\n-installcheck-target: maybe-installcheck-target-libsanitizer\n-installcheck-target: maybe-installcheck-target-libvtv\n-installcheck-target: maybe-installcheck-target-liboffloadmic\n-installcheck-target: maybe-installcheck-target-libssp\n installcheck-target: maybe-installcheck-target-newlib\n installcheck-target: maybe-installcheck-target-libgcc\n-installcheck-target: maybe-installcheck-target-libbacktrace\n-installcheck-target: maybe-installcheck-target-libquadmath\n-installcheck-target: maybe-installcheck-target-libgfortran\n-installcheck-target: maybe-installcheck-target-libobjc\n-installcheck-target: maybe-installcheck-target-libgo\n-installcheck-target: maybe-installcheck-target-libphobos\n-installcheck-target: maybe-installcheck-target-libtermcap\n-installcheck-target: maybe-installcheck-target-winsup\n-installcheck-target: maybe-installcheck-target-libgloss\n-installcheck-target: maybe-installcheck-target-libffi\n-installcheck-target: maybe-installcheck-target-zlib\n-installcheck-target: maybe-installcheck-target-rda\n-installcheck-target: maybe-installcheck-target-libada\n-installcheck-target: maybe-installcheck-target-libgomp\n-installcheck-target: maybe-installcheck-target-libitm\n-installcheck-target: maybe-installcheck-target-libatomic\n \n .PHONY: do-mostlyclean\n do-mostlyclean:\n@@ -2309,29 +2062,8 @@ mostlyclean-host: maybe-mostlyclean-libctf\n \n .PHONY: mostlyclean-target\n \n-mostlyclean-target: maybe-mostlyclean-target-libstdc++-v3\n-mostlyclean-target: maybe-mostlyclean-target-libsanitizer\n-mostlyclean-target: maybe-mostlyclean-target-libvtv\n-mostlyclean-target: maybe-mostlyclean-target-liboffloadmic\n-mostlyclean-target: maybe-mostlyclean-target-libssp\n mostlyclean-target: maybe-mostlyclean-target-newlib\n mostlyclean-target: maybe-mostlyclean-target-libgcc\n-mostlyclean-target: maybe-mostlyclean-target-libbacktrace\n-mostlyclean-target: maybe-mostlyclean-target-libquadmath\n-mostlyclean-target: maybe-mostlyclean-target-libgfortran\n-mostlyclean-target: maybe-mostlyclean-target-libobjc\n-mostlyclean-target: maybe-mostlyclean-target-libgo\n-mostlyclean-target: maybe-mostlyclean-target-libphobos\n-mostlyclean-target: maybe-mostlyclean-target-libtermcap\n-mostlyclean-target: maybe-mostlyclean-target-winsup\n-mostlyclean-target: maybe-mostlyclean-target-libgloss\n-mostlyclean-target: maybe-mostlyclean-target-libffi\n-mostlyclean-target: maybe-mostlyclean-target-zlib\n-mostlyclean-target: maybe-mostlyclean-target-rda\n-mostlyclean-target: maybe-mostlyclean-target-libada\n-mostlyclean-target: maybe-mostlyclean-target-libgomp\n-mostlyclean-target: maybe-mostlyclean-target-libitm\n-mostlyclean-target: maybe-mostlyclean-target-libatomic\n \n .PHONY: do-clean\n do-clean:\n@@ -2399,29 +2131,8 @@ clean-host: maybe-clean-libctf\n \n .PHONY: clean-target\n \n-clean-target: maybe-clean-target-libstdc++-v3\n-clean-target: maybe-clean-target-libsanitizer\n-clean-target: maybe-clean-target-libvtv\n-clean-target: maybe-clean-target-liboffloadmic\n-clean-target: maybe-clean-target-libssp\n clean-target: maybe-clean-target-newlib\n clean-target: maybe-clean-target-libgcc\n-clean-target: maybe-clean-target-libbacktrace\n-clean-target: maybe-clean-target-libquadmath\n-clean-target: maybe-clean-target-libgfortran\n-clean-target: maybe-clean-target-libobjc\n-clean-target: maybe-clean-target-libgo\n-clean-target: maybe-clean-target-libphobos\n-clean-target: maybe-clean-target-libtermcap\n-clean-target: maybe-clean-target-winsup\n-clean-target: maybe-clean-target-libgloss\n-clean-target: maybe-clean-target-libffi\n-clean-target: maybe-clean-target-zlib\n-clean-target: maybe-clean-target-rda\n-clean-target: maybe-clean-target-libada\n-clean-target: maybe-clean-target-libgomp\n-clean-target: maybe-clean-target-libitm\n-clean-target: maybe-clean-target-libatomic\n \n .PHONY: do-distclean\n do-distclean:\n@@ -2489,29 +2200,8 @@ distclean-host: maybe-distclean-libctf\n \n .PHONY: distclean-target\n \n-distclean-target: maybe-distclean-target-libstdc++-v3\n-distclean-target: maybe-distclean-target-libsanitizer\n-distclean-target: maybe-distclean-target-libvtv\n-distclean-target: maybe-distclean-target-liboffloadmic\n-distclean-target: maybe-distclean-target-libssp\n distclean-target: maybe-distclean-target-newlib\n distclean-target: maybe-distclean-target-libgcc\n-distclean-target: maybe-distclean-target-libbacktrace\n-distclean-target: maybe-distclean-target-libquadmath\n-distclean-target: maybe-distclean-target-libgfortran\n-distclean-target: maybe-distclean-target-libobjc\n-distclean-target: maybe-distclean-target-libgo\n-distclean-target: maybe-distclean-target-libphobos\n-distclean-target: maybe-distclean-target-libtermcap\n-distclean-target: maybe-distclean-target-winsup\n-distclean-target: maybe-distclean-target-libgloss\n-distclean-target: maybe-distclean-target-libffi\n-distclean-target: maybe-distclean-target-zlib\n-distclean-target: maybe-distclean-target-rda\n-distclean-target: maybe-distclean-target-libada\n-distclean-target: maybe-distclean-target-libgomp\n-distclean-target: maybe-distclean-target-libitm\n-distclean-target: maybe-distclean-target-libatomic\n \n .PHONY: do-maintainer-clean\n do-maintainer-clean:\n@@ -2579,29 +2269,8 @@ maintainer-clean-host: maybe-maintainer-clean-libctf\n \n .PHONY: maintainer-clean-target\n \n-maintainer-clean-target: maybe-maintainer-clean-target-libstdc++-v3\n-maintainer-clean-target: maybe-maintainer-clean-target-libsanitizer\n-maintainer-clean-target: maybe-maintainer-clean-target-libvtv\n-maintainer-clean-target: maybe-maintainer-clean-target-liboffloadmic\n-maintainer-clean-target: maybe-maintainer-clean-target-libssp\n maintainer-clean-target: maybe-maintainer-clean-target-newlib\n maintainer-clean-target: maybe-maintainer-clean-target-libgcc\n-maintainer-clean-target: maybe-maintainer-clean-target-libbacktrace\n-maintainer-clean-target: maybe-maintainer-clean-target-libquadmath\n-maintainer-clean-target: maybe-maintainer-clean-target-libgfortran\n-maintainer-clean-target: maybe-maintainer-clean-target-libobjc\n-maintainer-clean-target: maybe-maintainer-clean-target-libgo\n-maintainer-clean-target: maybe-maintainer-clean-target-libphobos\n-maintainer-clean-target: maybe-maintainer-clean-target-libtermcap\n-maintainer-clean-target: maybe-maintainer-clean-target-winsup\n-maintainer-clean-target: maybe-maintainer-clean-target-libgloss\n-maintainer-clean-target: maybe-maintainer-clean-target-libffi\n-maintainer-clean-target: maybe-maintainer-clean-target-zlib\n-maintainer-clean-target: maybe-maintainer-clean-target-rda\n-maintainer-clean-target: maybe-maintainer-clean-target-libada\n-maintainer-clean-target: maybe-maintainer-clean-target-libgomp\n-maintainer-clean-target: maybe-maintainer-clean-target-libitm\n-maintainer-clean-target: maybe-maintainer-clean-target-libatomic\n \n \n # Here are the targets which correspond to the do-X targets.\n@@ -2727,29 +2396,8 @@ check-host:  \\\n \n .PHONY: check-target\n check-target:  \\\n-    maybe-check-target-libstdc++-v3 \\\n-    maybe-check-target-libsanitizer \\\n-    maybe-check-target-libvtv \\\n-    maybe-check-target-liboffloadmic \\\n-    maybe-check-target-libssp \\\n     maybe-check-target-newlib \\\n-    maybe-check-target-libgcc \\\n-    maybe-check-target-libbacktrace \\\n-    maybe-check-target-libquadmath \\\n-    maybe-check-target-libgfortran \\\n-    maybe-check-target-libobjc \\\n-    maybe-check-target-libgo \\\n-    maybe-check-target-libphobos \\\n-    maybe-check-target-libtermcap \\\n-    maybe-check-target-winsup \\\n-    maybe-check-target-libgloss \\\n-    maybe-check-target-libffi \\\n-    maybe-check-target-zlib \\\n-    maybe-check-target-rda \\\n-    maybe-check-target-libada \\\n-    maybe-check-target-libgomp \\\n-    maybe-check-target-libitm \\\n-    maybe-check-target-libatomic\n+    maybe-check-target-libgcc\n \n do-check:\n \t@: $(MAKE); $(unstage)\n@@ -2919,29 +2567,8 @@ install-host:  \\\n \n .PHONY: install-target\n install-target:  \\\n-    maybe-install-target-libstdc++-v3 \\\n-    maybe-install-target-libsanitizer \\\n-    maybe-install-target-libvtv \\\n-    maybe-install-target-liboffloadmic \\\n-    maybe-install-target-libssp \\\n     maybe-install-target-newlib \\\n-    maybe-install-target-libgcc \\\n-    maybe-install-target-libbacktrace \\\n-    maybe-install-target-libquadmath \\\n-    maybe-install-target-libgfortran \\\n-    maybe-install-target-libobjc \\\n-    maybe-install-target-libgo \\\n-    maybe-install-target-libphobos \\\n-    maybe-install-target-libtermcap \\\n-    maybe-install-target-winsup \\\n-    maybe-install-target-libgloss \\\n-    maybe-install-target-libffi \\\n-    maybe-install-target-zlib \\\n-    maybe-install-target-rda \\\n-    maybe-install-target-libada \\\n-    maybe-install-target-libgomp \\\n-    maybe-install-target-libitm \\\n-    maybe-install-target-libatomic\n+    maybe-install-target-libgcc\n \n uninstall:\n \t@echo \"the uninstall target is not supported in this tree\"\n@@ -3029,30 +2656,8 @@ install-strip-host:  \\\n \n .PHONY: install-strip-target\n install-strip-target:  \\\n-    maybe-install-strip-target-libstdc++-v3 \\\n-    maybe-install-strip-target-libsanitizer \\\n-    maybe-install-strip-target-libvtv \\\n-    maybe-install-strip-target-liboffloadmic \\\n-    maybe-install-strip-target-libssp \\\n     maybe-install-strip-target-newlib \\\n-    maybe-install-strip-target-libgcc \\\n-    maybe-install-strip-target-libbacktrace \\\n-    maybe-install-strip-target-libquadmath \\\n-    maybe-install-strip-target-libgfortran \\\n-    maybe-install-strip-target-libobjc \\\n-    maybe-install-strip-target-libgo \\\n-    maybe-install-strip-target-libphobos \\\n-    maybe-install-strip-target-libtermcap \\\n-    maybe-install-strip-target-winsup \\\n-    maybe-install-strip-target-libgloss \\\n-    maybe-install-strip-target-libffi \\\n-    maybe-install-strip-target-zlib \\\n-    maybe-install-strip-target-rda \\\n-    maybe-install-strip-target-libada \\\n-    maybe-install-strip-target-libgomp \\\n-    maybe-install-strip-target-libitm \\\n-    maybe-install-strip-target-libatomic\n-\n+    maybe-install-strip-target-libgcc\n \n ### other supporting targets\n \n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/gcc/patches/patch-gcc_Makefile_in",
    "content": "Index: gcc/Makefile.in\n--- gcc/Makefile.in.orig\n+++ gcc/Makefile.in\n@@ -3784,13 +3784,7 @@ install-driver: installdirs xgcc$(exeext)\n # Install the info files.\n # $(INSTALL_DATA) might be a relative pathname, so we can't cd into srcdir\n # to do the install.\n-install-info:: doc installdirs \\\n-\t$(DESTDIR)$(infodir)/cpp.info \\\n-\t$(DESTDIR)$(infodir)/gcc.info \\\n-\t$(DESTDIR)$(infodir)/cppinternals.info \\\n-\t$(DESTDIR)$(infodir)/gccinstall.info \\\n-\t$(DESTDIR)$(infodir)/gccint.info \\\n-\tlang.install-info\n+install-info::\n \n $(DESTDIR)$(infodir)/%.info: doc/%.info installdirs\n \trm -f $@\n@@ -3857,10 +3851,7 @@ install-man: lang.install-man \\\n \t$(DESTDIR)$(man1dir)/$(GCOV_INSTALL_NAME)$(man1ext) \\\n \t$(DESTDIR)$(man1dir)/$(GCOV_TOOL_INSTALL_NAME)$(man1ext) \\\n \t$(DESTDIR)$(man1dir)/$(GCOV_DUMP_INSTALL_NAME)$(man1ext) \\\n-\t$(if $(filter yes,@enable_lto@),$(DESTDIR)$(man1dir)/$(LTO_DUMP_INSTALL_NAME)$(man1ext)) \\\n-\t$(DESTDIR)$(man7dir)/fsf-funding$(man7ext) \\\n-\t$(DESTDIR)$(man7dir)/gfdl$(man7ext) \\\n-\t$(DESTDIR)$(man7dir)/gpl$(man7ext)\n+\t$(if $(filter yes,@enable_lto@),$(DESTDIR)$(man1dir)/$(LTO_DUMP_INSTALL_NAME)$(man1ext))\n \n $(DESTDIR)$(man7dir)/%$(man7ext): doc/%.7 installdirs\n \t-rm -f $@\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/gcc/patches/patch-gcc_common_opt",
    "content": "Index: gcc/common.opt\n--- gcc/common.opt.orig\n+++ gcc/common.opt\n@@ -2017,7 +2017,7 @@ Common Var(flag_ivopts) Init(1) Optimization\n Optimize induction variables on trees.\n \n fjump-tables\n-Common Var(flag_jump_tables) Init(1) Optimization\n+Common Var(flag_jump_tables) Init(0) Optimization\n Use jump tables for sufficiently large switch statements.\n \n fbit-tests\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/gcc/patches/patch-gcc_config_host",
    "content": "Index: gcc/config.host\n--- gcc/config.host.orig\n+++ gcc/config.host\n@@ -99,8 +99,7 @@ case ${host} in\n esac\n \n case ${host} in\n-  aarch64*-*-freebsd* | aarch64*-*-linux* | aarch64*-*-fuchsia* |\\\n-  aarch64*-*-darwin*)\n+  aarch64*-*-*)\n     case ${target} in\n       aarch64*-*-*)\n \thost_extra_gcc_objs=\"driver-aarch64.o\"\n@@ -108,7 +107,7 @@ case ${host} in\n \t;;\n     esac\n     ;;\n-  arm*-*-freebsd* | arm*-*-netbsd* | arm*-*-linux* | arm*-*-fuchsia*)\n+  arm*-*-*)\n     case ${target} in\n       arm*-*-*)\n \thost_extra_gcc_objs=\"driver-arm.o\"\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/gcc/patches/patch-gcc_configure",
    "content": "Index: gcc/configure\n--- gcc/configure.orig\n+++ gcc/configure\n@@ -32456,14 +32456,14 @@ if test \"$gcc_cv_c_no_fpie\" = \"yes\"; then\n fi\n \n \n-# Check if -no-pie works.\n-{ $as_echo \"$as_me:${as_lineno-$LINENO}: checking for -no-pie option\" >&5\n-$as_echo_n \"checking for -no-pie option... \" >&6; }\n+# Check if -nopie works.\n+{ $as_echo \"$as_me:${as_lineno-$LINENO}: checking for -nopie option\" >&5\n+$as_echo_n \"checking for -nopie option... \" >&6; }\n if ${gcc_cv_no_pie+:} false; then :\n   $as_echo_n \"(cached) \" >&6\n else\n   saved_LDFLAGS=\"$LDFLAGS\"\n-   LDFLAGS=\"$LDFLAGS -no-pie\"\n+   LDFLAGS=\"$LDFLAGS -nopie\"\n    cat confdefs.h - <<_ACEOF >conftest.$ac_ext\n /* end confdefs.h.  */\n int main(void) {return 0;}\n@@ -32480,7 +32480,7 @@ fi\n { $as_echo \"$as_me:${as_lineno-$LINENO}: result: $gcc_cv_no_pie\" >&5\n $as_echo \"$gcc_cv_no_pie\" >&6; }\n if test \"$gcc_cv_no_pie\" = \"yes\"; then\n-  NO_PIE_FLAG=\"-no-pie\"\n+  NO_PIE_FLAG=\"-nopie\"\n fi\n \n \n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/gcc/patches/patch-libcc1_connection_cc",
    "content": "Index: libcc1/connection.cc\n--- libcc1/connection.cc.orig\n+++ libcc1/connection.cc\n@@ -20,6 +20,7 @@ along with GCC; see the file COPYING3.  If not see\n #include <cc1plugin-config.h>\n #include <string>\n #include <unistd.h>\n+#include <sys/select.h>\n #include <sys/types.h>\n #include <string.h>\n #include <errno.h>\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/gcc/patches/patch-libgcc_Makefile_in",
    "content": "Index: libgcc/Makefile.in\n--- libgcc/Makefile.in.orig\n+++ libgcc/Makefile.in\n@@ -1093,7 +1093,7 @@ libgcc-extra-parts: $(EXTRA_PARTS)\n \tparts=\"$(EXTRA_PARTS)\";\t\t\t\t\t\\\n \tfor file in $$parts; do\t\t\t\t\t\\\n \t  rm -f $(gcc_objdir)$(MULTISUBDIR)/$$file;\t\t\\\n-\t  $(INSTALL_DATA) $$file $(gcc_objdir)$(MULTISUBDIR)/;\t\\\n+\t  install -c $$file $(gcc_objdir)$(MULTISUBDIR)/;\t\\\n \t  case $$file in \t\t\t\t\t\\\n \t    *.a)\t\t\t\t\t\t\\\n \t      $(RANLIB) $(gcc_objdir)$(MULTISUBDIR)/$$file ;;\t\\\n@@ -1123,7 +1123,7 @@ install-unwind_h-forbuild: unwind.h\n # internal headers are copied by gcc's install.\n install-unwind_h:\n \t$(mkinstalldirs) $(DESTDIR)$(libsubdir)/include\n-\t$(INSTALL_DATA) unwind.h $(DESTDIR)$(libsubdir)/include\n+\tinstall -c unwind.h $(DESTDIR)$(libsubdir)/include\n \n all: install-unwind_h-forbuild\n \n@@ -1149,7 +1149,7 @@ install-libunwind:\n \n \t# NOTE: Maybe this should go into $(inst_libdir), but this\n \t# is where the old mklibgcc.in put it.\n-\t$(INSTALL_DATA) libunwind.a $(DESTDIR)$(inst_slibdir)/\n+\tinstall -c libunwind.a $(DESTDIR)$(inst_slibdir)/\n \tchmod 644 $(DESTDIR)$(inst_slibdir)/libunwind.a\n \t$(RANLIB) $(DESTDIR)$(inst_slibdir)/libunwind.a\n \n@@ -1160,7 +1160,7 @@ install-libunwind:\n install-shared:\n \t$(mkinstalldirs) $(DESTDIR)$(inst_libdir)\n \n-\t$(INSTALL_DATA) libgcc_eh.a $(DESTDIR)$(inst_libdir)/\n+\tinstall -c libgcc_eh.a $(DESTDIR)$(inst_libdir)/\n \tchmod 644 $(DESTDIR)$(inst_libdir)/libgcc_eh.a\n \t$(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_eh.a\n \n@@ -1171,19 +1171,17 @@ install-shared:\n install-leaf: $(install-shared) $(install-libunwind)\n \t$(mkinstalldirs) $(DESTDIR)$(inst_libdir)\n \n-\t$(INSTALL_DATA) libgcc.a $(DESTDIR)$(inst_libdir)/\n-\tchmod 644 $(DESTDIR)$(inst_libdir)/libgcc.a\n+\tinstall -c libgcc.a $(DESTDIR)$(inst_libdir)\n \t$(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc.a\n ifeq ($(enable_gcov),yes)\n-\t$(INSTALL_DATA) libgcov.a $(DESTDIR)$(inst_libdir)/\n-\tchmod 644 $(DESTDIR)$(inst_libdir)/libgcov.a\n+\tinstall -c libgcov.a $(DESTDIR)$(inst_libdir)\n \t$(RANLIB) $(DESTDIR)$(inst_libdir)/libgcov.a\n endif\n \n \tparts=\"$(INSTALL_PARTS)\";\t\t\t\t\\\n \tfor file in $$parts; do\t\t\t\t\t\\\n \t  rm -f $(DESTDIR)$(inst_libdir)/$$file;\t\t\\\n-\t  $(INSTALL_DATA) $$file $(DESTDIR)$(inst_libdir)/;\t\\\n+\t  install -c $$file $(DESTDIR)$(inst_libdir)/;\t\t\\\n \t  case $$file in \t\t\t\t\t\\\n \t    *.a)\t\t\t\t\t\t\\\n \t      $(RANLIB) $(gcc_objdir)$(MULTISUBDIR)/$$file ;;\t\\\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/gcc/patches/patch-libgcc_config_host",
    "content": "Index: libgcc/config.host\n--- libgcc/config.host.orig\n+++ libgcc/config.host\n@@ -166,11 +166,11 @@ mips*-*-*)\n \t# All MIPS targets provide a full set of FP routines.\n \tcpu_type=mips\n \ttmake_file=\"mips/t-mips\"\n-\tif test \"${libgcc_cv_mips_hard_float}\" = yes; then\n-\t\ttmake_file=\"${tmake_file} t-hardfp-sfdf t-hardfp\"\n-\telse\n+# XXX\tif test \"${libgcc_cv_mips_hard_float}\" = yes; then\n+# XXX\t\ttmake_file=\"${tmake_file} t-hardfp-sfdf t-hardfp\"\n+# XXX\telse\n \t\ttmake_file=\"${tmake_file} t-softfp-sfdf\"\n-\tfi\n+# XXX\tfi\n \tif test \"${ac_cv_sizeof_long_double}\" = 16; then\n \t\ttmake_file=\"${tmake_file} mips/t-softfp-tf\"\n \tfi\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/gcc/patches/patch-libiberty_Makefile_in",
    "content": "Index: libiberty/Makefile.in\n--- libiberty/Makefile.in.orig\n+++ libiberty/Makefile.in\n@@ -376,7 +376,7 @@ libiberty.html : $(srcdir)/libiberty.texi $(TEXISRC)\n @MAINT@\techo stamp > stamp-functions\n \n INSTALL_DEST = @INSTALL_DEST@\n-install: install_to_$(INSTALL_DEST) install-subdir\n+install:\n install-strip: install\n \n .PHONY: install install-strip\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/gcc/pkg/DESCR",
    "content": "GNU cross compiler suite, configured for the mips-elf target.\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/mips-elf/gcc/pkg/PLIST",
    "content": "@bin bin/mips-elf-cpp\n@bin bin/mips-elf-gcc\n@bin bin/mips-elf-gcc-${VERSION}\n@bin bin/mips-elf-gcc-ar\n@bin bin/mips-elf-gcc-nm\n@bin bin/mips-elf-gcc-ranlib\n@bin bin/mips-elf-gcov\n@comment @info info/cpp.info\n@comment @info info/cppinternals.info\n@comment @info info/gcc.info\n@comment @info info/gccinstall.info\n@comment @info info/gccint.info\n@comment @info info/libquadmath.info\n@bin bin/mips-elf-gcov-dump\n@bin bin/mips-elf-gcov-tool\n@bin bin/mips-elf-lto-dump\nlib/gcc/\nlib/gcc/mips-elf/\nlib/gcc/mips-elf/${VERSION}/\nlib/gcc/mips-elf/${VERSION}/crtbegin.o\nlib/gcc/mips-elf/${VERSION}/crtend.o\nlib/gcc/mips-elf/${VERSION}/crti.o\nlib/gcc/mips-elf/${VERSION}/crtn.o\nlib/gcc/mips-elf/${VERSION}/el/\nlib/gcc/mips-elf/${VERSION}/el/crtbegin.o\nlib/gcc/mips-elf/${VERSION}/el/crtend.o\nlib/gcc/mips-elf/${VERSION}/el/crti.o\nlib/gcc/mips-elf/${VERSION}/el/crtn.o\n@static-lib lib/gcc/mips-elf/${VERSION}/el/libgcc.a\n@static-lib lib/gcc/mips-elf/${VERSION}/el/libgcov.a\nlib/gcc/mips-elf/${VERSION}/include/\nlib/gcc/mips-elf/${VERSION}/include-fixed/\nlib/gcc/mips-elf/${VERSION}/include-fixed/README\nlib/gcc/mips-elf/${VERSION}/include-fixed/limits.h\nlib/gcc/mips-elf/${VERSION}/include-fixed/syslimits.h\nlib/gcc/mips-elf/${VERSION}/include/float.h\nlib/gcc/mips-elf/${VERSION}/include/gcov.h\nlib/gcc/mips-elf/${VERSION}/include/iso646.h\nlib/gcc/mips-elf/${VERSION}/include/loongson-mmiintrin.h\nlib/gcc/mips-elf/${VERSION}/include/loongson.h\nlib/gcc/mips-elf/${VERSION}/include/msa.h\nlib/gcc/mips-elf/${VERSION}/include/stdalign.h\nlib/gcc/mips-elf/${VERSION}/include/stdarg.h\nlib/gcc/mips-elf/${VERSION}/include/stdatomic.h\nlib/gcc/mips-elf/${VERSION}/include/stdbool.h\nlib/gcc/mips-elf/${VERSION}/include/stddef.h\nlib/gcc/mips-elf/${VERSION}/include/stdfix.h\nlib/gcc/mips-elf/${VERSION}/include/stdint-gcc.h\nlib/gcc/mips-elf/${VERSION}/include/stdint.h\nlib/gcc/mips-elf/${VERSION}/include/stdnoreturn.h\nlib/gcc/mips-elf/${VERSION}/include/tgmath.h\nlib/gcc/mips-elf/${VERSION}/include/unwind.h\nlib/gcc/mips-elf/${VERSION}/include/varargs.h\nlib/gcc/mips-elf/${VERSION}/install-tools/\nlib/gcc/mips-elf/${VERSION}/install-tools/fixinc_list\nlib/gcc/mips-elf/${VERSION}/install-tools/gsyslimits.h\nlib/gcc/mips-elf/${VERSION}/install-tools/include/\nlib/gcc/mips-elf/${VERSION}/install-tools/include/README\nlib/gcc/mips-elf/${VERSION}/install-tools/include/limits.h\nlib/gcc/mips-elf/${VERSION}/install-tools/macro_list\nlib/gcc/mips-elf/${VERSION}/install-tools/mkheaders.conf\n@static-lib lib/gcc/mips-elf/${VERSION}/libgcc.a\n@static-lib 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libexec/gcc/mips-elf/${VERSION}/install-tools/fixincl\nlibexec/gcc/mips-elf/${VERSION}/install-tools/mkheaders\nlibexec/gcc/mips-elf/${VERSION}/install-tools/mkinstalldirs\nlibexec/gcc/mips-elf/${VERSION}/liblto_plugin.la\n@so libexec/gcc/mips-elf/${VERSION}/liblto_plugin.so\n@bin libexec/gcc/mips-elf/${VERSION}/lto-wrapper\n@bin libexec/gcc/mips-elf/${VERSION}/lto1\nlibexec/gcc/mips-elf/${VERSION}/plugin/\n@bin libexec/gcc/mips-elf/${VERSION}/plugin/gengtype\n@man man/man1/mips-elf-cpp.1\n@man man/man1/mips-elf-gcc.1\n@man man/man1/mips-elf-gcov-dump.1\n@man man/man1/mips-elf-gcov-tool.1\n@man man/man1/mips-elf-gcov.1\n@comment @man man/man7/fsf-funding.7\n@comment @man man/man7/gfdl.7\n@comment @man man/man7/gpl.7\n@man man/man1/mips-elf-lto-dump.1\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/stlink/Makefile",
    "content": "COMMENT=\t\ttoolset for ST Microelectronics ST-Link V1/V2/V2-1/V3\n\nV=\t\t\t1.8.0\nDISTNAME=\t\tstlink-${V}\n\nSHARED_LIBS+=\t\tstlink\t\t\t0.0\t# 0.0\n\nCATEGORIES=\t\tdevel\n\nHOMEPAGE=\t\thttps://github.com/stlink-org/stlink\n\n# BSD\nPERMIT_PACKAGE=\t\tYes\n\nWANTLIB=\t\tc usb-1.0\n\nGH_ACCOUNT=\t\tstlink-org\nGH_PROJECT=\t\tstlink\nGH_TAGNAME=\t\tv${V}\n\nLIB_DEPENDS=\t\tdevel/libusb1\n\nMODULES=\t\tdevel/cmake\n\n.include <bsd.port.mk>\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/stlink/distinfo",
    "content": "SHA256 (stlink-1.8.0.tar.gz) = z/dgtcISwsxID3BbnKfzgo1rnCZ5UMalRwAs0KH19qw=\nSIZE (stlink-1.8.0.tar.gz) = 257240\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/stlink/patches/patch-CMakeLists_txt",
    "content": "Index: CMakeLists.txt\n--- CMakeLists.txt.orig\n+++ CMakeLists.txt\n@@ -392,7 +392,6 @@ install(FILES ${CHIP_FILES} DESTINATION ${CMAKE_CHIPS_\n option(STLINK_GENERATE_MANPAGES \"Generate manpages with pandoc\" OFF)\n add_subdirectory(doc/man)         # contains subordinate CMakeLists to generate manpages\n \n-add_subdirectory(src/stlink-gui)  # contains subordinate CMakeLists to build GUI\n add_subdirectory(tests)           # contains subordinate CMakeLists to build test executables\n add_subdirectory(cmake/packaging) # contains subordinate CMakeLists to build packages\n \n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/stlink/patches/patch-cmake_modules_c_flags_cmake",
    "content": "Index: cmake/modules/c_flags.cmake\n--- cmake/modules/c_flags.cmake.orig\n+++ cmake/modules/c_flags.cmake\n@@ -28,7 +28,6 @@ add_cflag_if_supported(\"-Wformat\")\n add_cflag_if_supported(\"-Wformat-security\")\n add_cflag_if_supported(\"-Wmaybe-uninitialized\")\n add_cflag_if_supported(\"-Wmissing-variable-declarations\")\n-add_cflag_if_supported(\"-Wshorten-64-to-32\")\n add_cflag_if_supported(\"-Wimplicit-function-declaration\")\n \n ##\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/stlink/patches/patch-doc_man_CMakeLists_txt",
    "content": "Index: doc/man/CMakeLists.txt\n--- doc/man/CMakeLists.txt.orig\n+++ doc/man/CMakeLists.txt\n@@ -30,7 +30,7 @@ foreach (manpage ${MANPAGES})\n     endif()\n \n     if (f AND NOT WIN32)\n-        install(FILES ${f} DESTINATION ${CMAKE_INSTALL_DATADIR}/man/man1)\n+        install(FILES ${f} DESTINATION ${CMAKE_INSTALL_MANDIR}/man1)\n         unset(f)\n     endif()\n endforeach ()\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/stlink/pkg/DESCR",
    "content": "Programming toolset for ST Microelectronics ST-Link V1/V2/V2-1/V3\n\nExample command to load firmware into target:\n\n\t$ st-flash --reset write file.bin 0x08000000\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/devel/stlink/pkg/PLIST",
    "content": "@bin bin/st-flash\n@bin bin/st-info\n@bin bin/st-trace\n@bin bin/st-util\ninclude/stlink/\ninclude/stlink/backend.h\ninclude/stlink/calculate.h\ninclude/stlink/chipid.h\ninclude/stlink/commands.h\ninclude/stlink/common_flash.h\ninclude/stlink/flash_loader.h\ninclude/stlink/helper.h\ninclude/stlink/lib_md5.h\ninclude/stlink/libusb_settings.h\ninclude/stlink/logging.h\ninclude/stlink/map_file.h\ninclude/stlink/md5.h\ninclude/stlink/option_bytes.h\ninclude/stlink/read_write.h\ninclude/stlink/register.h\ninclude/stlink/sg.h\ninclude/stlink/spdlog_wrapper.h\ninclude/stlink/stlink.h\ninclude/stlink/stm32.h\ninclude/stlink/stm32flash.h\ninclude/stlink/usb.h\ninclude/stlink/version.h\n@static-lib lib/libstlink.a\n@lib lib/libstlink.so.${LIBstlink_VERSION}\n@man man/man1/st-flash.1\n@man man/man1/st-info.1\n@man man/man1/st-util.1\nshare/stlink/\nshare/stlink/chips/\nshare/stlink/chips/C011xx.chip\nshare/stlink/chips/C031xx.chip\nshare/stlink/chips/F03x.chip\nshare/stlink/chips/F04x.chip\nshare/stlink/chips/F05x.chip\nshare/stlink/chips/F07x.chip\nshare/stlink/chips/F09x.chip\nshare/stlink/chips/F1xx_CL.chip\nshare/stlink/chips/F1xx_HD.chip\nshare/stlink/chips/F1xx_LD.chip\nshare/stlink/chips/F1xx_MD.chip\nshare/stlink/chips/F1xx_VL_HD.chip\nshare/stlink/chips/F1xx_VL_MD_LD.chip\nshare/stlink/chips/F1xx_XLD.chip\nshare/stlink/chips/F2xx.chip\nshare/stlink/chips/F301_F302_F318.chip\nshare/stlink/chips/F302_F303_F358.chip\nshare/stlink/chips/F302_F303_F398_HD.chip\nshare/stlink/chips/F303_F328_F334.chip\nshare/stlink/chips/F37x.chip\nshare/stlink/chips/F401xB_xC.chip\nshare/stlink/chips/F401xD_xE.chip\nshare/stlink/chips/F410.chip\nshare/stlink/chips/F411xC_xE.chip\nshare/stlink/chips/F412.chip\nshare/stlink/chips/F413_F423.chip\nshare/stlink/chips/F42x_F43x.chip\nshare/stlink/chips/F446.chip\nshare/stlink/chips/F46x_F47x.chip\nshare/stlink/chips/F4x5_F4x7.chip\nshare/stlink/chips/F72x_F73x.chip\nshare/stlink/chips/F74x_F75x.chip\nshare/stlink/chips/F76x_F77x.chip\nshare/stlink/chips/G03x_G04x.chip\nshare/stlink/chips/G05x_G06x.chip\nshare/stlink/chips/G07x_G08x.chip\nshare/stlink/chips/G0Bx_G0Cx.chip\nshare/stlink/chips/G43x_G44x.chip\nshare/stlink/chips/G47x_G48x.chip\nshare/stlink/chips/G49x_G4Ax.chip\nshare/stlink/chips/H5xx.chip\nshare/stlink/chips/H72x_H73x.chip\nshare/stlink/chips/H74x_H75x.chip\nshare/stlink/chips/H7Ax_H7Bx.chip\nshare/stlink/chips/L0xxx_Cat_1.chip\nshare/stlink/chips/L0xxx_Cat_2.chip\nshare/stlink/chips/L0xxx_Cat_3.chip\nshare/stlink/chips/L0xxx_Cat_5.chip\nshare/stlink/chips/L1xx_Cat_1.chip\nshare/stlink/chips/L1xx_Cat_2.chip\nshare/stlink/chips/L1xx_Cat_3.chip\nshare/stlink/chips/L1xx_Cat_4.chip\nshare/stlink/chips/L1xx_Cat_5.chip\nshare/stlink/chips/L41x_L42x.chip\nshare/stlink/chips/L43x_L44x.chip\nshare/stlink/chips/L45x_L46x.chip\nshare/stlink/chips/L47x_L48x.chip\nshare/stlink/chips/L496x_L4A6x.chip\nshare/stlink/chips/L4Px_L4Qx.chip\nshare/stlink/chips/L4Rx.chip\nshare/stlink/chips/L5x5xx.chip\nshare/stlink/chips/U535_U545.chip\nshare/stlink/chips/U55Fx_U5Gx.chip\nshare/stlink/chips/U575_U585.chip\nshare/stlink/chips/U59x_U5Ax.chip\nshare/stlink/chips/WBx0_WBx5.chip\nshare/stlink/chips/WLEx.chip\nshare/stlink/chips/unknown_device.chip\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/emulators/qemu-arm/Makefile",
    "content": "ONLY_FOR_ARCHS=\tamd64 i386 powerpc sparc64\n\nUSE_WXNEEDED=\tYes\n\nCOMMENT=\tmulti system emulator, Arm Cortex-M version\n\nDISTNAME=\tqemu-arm-2.8.0.6.20190517\nREVISION=\t0\n\nCATEGORIES=\temulators\n\nHOMEPAGE=\thttps://github.com/ilg-archived/qemu\n\n# GPLv2, LGPLv2 and BSD\nPERMIT_PACKAGE=\tYes\n\nGH_ACCOUNT=\tilg-archived\nGH_PROJECT=\tqemu\nGH_TAGNAME=\tv2.8.0-6-20190517\n\nWANTLIB=\tSDL2 SDL2_image X11 c drm epoxy fdt \\\n\t\tgbm glib-2.0 gthread-2.0 intl iscsi m \\\n\t\tatk-1.0 cairo cairo-gobject gdk-3 \\\n\t\tgdk_pixbuf-2.0 gio-2.0 gobject-2.0 gtk-3 \\\n\t\tharfbuzz pango-1.0 pangocairo-1.0 vte-2.91 \\\n\t\tpixman-1 util z ${COMPILER_LIBCXX}\n\n# Using TLS emulation layer\nCOMPILER=\tbase-clang ports-gcc\n\nMODULES=\tlang/python\nMODPY_VERSION=\t${MODPY_DEFAULT_VERSION_2}\n\nBUILD_DEPENDS=\tdevel/gettext,-tools \\\n\t\ttextproc/py-sphinx${MODPY_FLAVOR} \\\n\t\ttextproc/texi2html\n\nLIB_DEPENDS=\tdevel/dtc \\\n\t\tdevel/glib2 \\\n\t\tdevel/libiscsi \\\n\t\tdevel/pango \\\n\t\tdevel/sdl2 \\\n\t\tdevel/sdl2-image \\\n\t\tdevel/vte3 \\\n\t\tgraphics/cairo\n\nMODPY_RUNDEP=\tNo\n\nMAKE_ENV=\tV=1\nFAKE_FLAGS=\tqemu_confdir=${PREFIX}/share/examples/qemu\n\nEXTRA_CFLAGS=\t-I${LOCALBASE}/include -I${X11BASE}/include\nEXTRA_LDFLAGS=\t-L${LOCALBASE}/lib -L${X11BASE}/lib\n\n# fix build with ancient ncurses. ncurses needs to be updated to 5.9 or newer.\nEXTRA_CFLAGS+=\t-D_XOPEN_SOURCE_EXTENDED\n\n# until the system headers are fixed properly.\nEXTRA_CFLAGS+=\t-Wno-redundant-decls\n\nSEPARATE_BUILD=\tYes\n\nUSE_GMAKE=\tYes\nCONFIGURE_STYLE=simple\nCONFIGURE_ARGS=\t--prefix=${PREFIX} \\\n\t\t--sysconfdir=${SYSCONFDIR} \\\n\t\t--mandir=${PREFIX}/man \\\n\t\t--python=${MODPY_BIN} \\\n\t\t--cc=\"${CC}\" \\\n\t\t--cxx=\"${CXX}\" \\\n\t\t--host-cc=\"${CC}\" \\\n\t\t--extra-cflags=\"${EXTRA_CFLAGS}\" \\\n\t\t--extra-ldflags=\"${EXTRA_LDFLAGS}\" \\\n\t\t--target-list=\"gnuarmeclipse-softmmu\" \\\n\t\t--with-sdlabi=\"2.0\" \\\n\t\t--disable-bsd-user \\\n\t\t--disable-werror \\\n\t\t--disable-bluez \\\n\t\t--disable-gcrypt \\\n\t\t--disable-gnutls \\\n\t\t--disable-libnfs \\\n\t\t--disable-libssh2 \\\n\t\t--disable-linux-aio \\\n\t\t--disable-lzo \\\n\t\t--disable-nettle \\\n\t\t--disable-seccomp \\\n\t\t--disable-smartcard \\\n\t\t--disable-snappy \\\n\t\t--disable-spice \\\n\t\t--disable-usb-redir \\\n\t\t--disable-vnc-sasl\n\nFLAVORS=\tdebug\nFLAVOR?=\n\n.if ${FLAVOR:Mdebug}\nCFLAGS+=\t-O0\nCONFIGURE_ARGS+=--enable-debug\nINSTALL_STRIP=\n.else\nCONFIGURE_ARGS+=--disable-debug-info\n.endif\n\nTEST_TARGET=\tcheck\n\n# Install the json scripts and board graphics.\npost-install:\n\t${INSTALL_DATA_DIR} ${PREFIX}/share/qemu/devices\n\t${INSTALL_DATA} ${WRKSRC}/gnu-mcu-eclipse/devices/*.json \\\n\t    ${PREFIX}/share/qemu/devices\n\t${INSTALL_DATA} ${WRKSRC}/gnu-mcu-eclipse/devices/README.md \\\n\t    ${PREFIX}/share/qemu/devices\n\t${INSTALL_DATA_DIR} ${PREFIX}/share/qemu/graphics\n\t${INSTALL_DATA} ${WRKSRC}/gnu-mcu-eclipse/graphics/*.jpg \\\n\t    ${PREFIX}/share/qemu/graphics\n\n.include <bsd.port.mk>\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/emulators/qemu-arm/distinfo",
    "content": "SHA256 (qemu-arm-2.8.0.6.20190517.tar.gz) = DXr9KwFXGUp3IjXwA3lSda67LyDqEfvzt+H7MeDMAfw=\nSIZE (qemu-arm-2.8.0.6.20190517.tar.gz) = 17989504\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/emulators/qemu-arm/patches/patch-include_ui_egl-helpers_h",
    "content": "From fbd57c754f32804a63295f70f271d1ef128ee590 Mon Sep 17 00:00:00 2001\nFrom: Alexander Kanavin <alex.kanavin@gmail.com>\nDate: Wed, 16 Jan 2019 12:37:51 +0100\nSubject: [PATCH] egl-helpers.h: do not depend on X11 Window type, use\n EGLNativeWindowType\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nIt was assumed that mesa provides the necessary X11 includes,\nbut it is not always the case, as it can be configured without x11 support.\n\nSigned-off-by: Alexander Kanavin <alex.kanavin@gmail.com>\nReviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>\nMessage-id: 20190116113751.17177-1-alex.kanavin@gmail.com\n\n[ kraxel: codestyle fix (long line) ]\n\nSigned-off-by: Gerd Hoffmann <kraxel@redhat.com>\n\nIndex: include/ui/egl-helpers.h\n--- include/ui/egl-helpers.h.orig\n+++ include/ui/egl-helpers.h\n@@ -20,7 +20,7 @@ int egl_get_fd_for_texture(uint32_t tex_id, EGLint *st\n \n #endif\n \n-EGLSurface qemu_egl_init_surface_x11(EGLContext ectx, Window win);\n+EGLSurface qemu_egl_init_surface_x11(EGLContext ectx, EGLNativeWindowType win);\n \n int qemu_egl_init_dpy(EGLNativeDisplayType dpy, bool gles, bool debug);\n EGLContext qemu_egl_init_ctx(void);\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/emulators/qemu-arm/patches/patch-ui_egl-helpers_c",
    "content": "From fbd57c754f32804a63295f70f271d1ef128ee590 Mon Sep 17 00:00:00 2001\nFrom: Alexander Kanavin <alex.kanavin@gmail.com>\nDate: Wed, 16 Jan 2019 12:37:51 +0100\nSubject: [PATCH] egl-helpers.h: do not depend on X11 Window type, use\n EGLNativeWindowType\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nIt was assumed that mesa provides the necessary X11 includes,\nbut it is not always the case, as it can be configured without x11 support.\n\nSigned-off-by: Alexander Kanavin <alex.kanavin@gmail.com>\nReviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>\nMessage-id: 20190116113751.17177-1-alex.kanavin@gmail.com\n\n[ kraxel: codestyle fix (long line) ]\n\nSigned-off-by: Gerd Hoffmann <kraxel@redhat.com>\n\nIndex: ui/egl-helpers.c\n--- ui/egl-helpers.c.orig\n+++ ui/egl-helpers.c\n@@ -146,7 +146,7 @@ int egl_get_fd_for_texture(uint32_t tex_id, EGLint *st\n \n /* ---------------------------------------------------------------------- */\n \n-EGLSurface qemu_egl_init_surface_x11(EGLContext ectx, Window win)\n+EGLSurface qemu_egl_init_surface_x11(EGLContext ectx, EGLNativeWindowType win)\n {\n     EGLSurface esurface;\n     EGLBoolean b;\n@@ -155,7 +155,7 @@ EGLSurface qemu_egl_init_surface_x11(EGLContext ectx, \n             (unsigned long) win);\n     esurface = eglCreateWindowSurface(qemu_egl_display,\n                                       qemu_egl_config,\n-                                      (EGLNativeWindowType)win, NULL);\n+                                      win, NULL);\n     if (esurface == EGL_NO_SURFACE) {\n         error_report(\"egl: eglCreateWindowSurface failed\");\n         return NULL;\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/emulators/qemu-arm/patches/patch-ui_gtk-egl_c",
    "content": "From fbd57c754f32804a63295f70f271d1ef128ee590 Mon Sep 17 00:00:00 2001\nFrom: Alexander Kanavin <alex.kanavin@gmail.com>\nDate: Wed, 16 Jan 2019 12:37:51 +0100\nSubject: [PATCH] egl-helpers.h: do not depend on X11 Window type, use\n EGLNativeWindowType\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nIt was assumed that mesa provides the necessary X11 includes,\nbut it is not always the case, as it can be configured without x11 support.\n\nSigned-off-by: Alexander Kanavin <alex.kanavin@gmail.com>\nReviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>\nMessage-id: 20190116113751.17177-1-alex.kanavin@gmail.com\n\n[ kraxel: codestyle fix (long line) ]\n\nSigned-off-by: Gerd Hoffmann <kraxel@redhat.com>\n\nIndex: ui/gtk-egl.c\n--- ui/gtk-egl.c.orig\n+++ ui/gtk-egl.c\n@@ -64,7 +64,8 @@ void gd_egl_init(VirtualConsole *vc)\n     }\n \n     vc->gfx.ectx = qemu_egl_init_ctx();\n-    vc->gfx.esurface = qemu_egl_init_surface_x11(vc->gfx.ectx, x11_window);\n+    vc->gfx.esurface = qemu_egl_init_surface_x11\n+        (vc->gfx.ectx, (EGLNativeWindowType)x11_window);\n \n     assert(vc->gfx.esurface);\n }\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/emulators/qemu-arm/pkg/DESCR",
    "content": "QEMU is an open source machine emulator. It can run OSes and programs\nmade for one machine (e.g. an ARM board) on a different machine\n(e.g. your own PC). By using dynamic translation, it achieves very\ngood performance.\n"
  },
  {
    "path": "tools/openbsd/ports/mystuff/emulators/qemu-arm/pkg/PLIST",
    "content": "@conflict kqemu-*\n@conflict qemu-*\n@pkgpath emulators/kqemu\n@pkgpath emulators/qemu,kqemu\n@pkgpath emulators/qemu-old[,no_x11]\n@bin bin/qemu-system-gnuarmeclipse\n@man man/man1/qemu.1\nshare/doc/qemu/\nshare/doc/qemu/qemu-doc.html\nshare/doc/qemu/qmp-commands.txt\nshare/qemu/\nshare/qemu/devices/\nshare/qemu/devices/README.md\nshare/qemu/devices/STM32F0x1-qemu.json\nshare/qemu/devices/STM32F0x2-qemu.json\nshare/qemu/devices/STM32F103xx-qemu.json\nshare/qemu/devices/STM32F107xx-qemu.json\nshare/qemu/devices/STM32F40x-qemu.json\nshare/qemu/devices/STM32F411xx-qemu.json\nshare/qemu/devices/STM32F429x-qemu.json\nshare/qemu/graphics/\nshare/qemu/graphics/Maple.jpg\nshare/qemu/graphics/NUCLEO-F072RB.jpg\nshare/qemu/graphics/NUCLEO-F103RB.jpg\nshare/qemu/graphics/NUCLEO-F411RE.jpg\nshare/qemu/graphics/NetduinoGo.jpg\nshare/qemu/graphics/NetduinoPlus2.jpg\nshare/qemu/graphics/OLIMEXINO-STM32.jpg\nshare/qemu/graphics/STM32-E407.jpg\nshare/qemu/graphics/STM32-H103.jpg\nshare/qemu/graphics/STM32-P103.jpg\nshare/qemu/graphics/STM32-P107.jpg\nshare/qemu/graphics/STM32F0-Discovery.jpg\nshare/qemu/graphics/STM32F4-Discovery.jpg\nshare/qemu/graphics/STM32F429I-Discovery.jpg\nshare/qemu/keymaps/\nshare/qemu/keymaps/ar\nshare/qemu/keymaps/bepo\nshare/qemu/keymaps/common\nshare/qemu/keymaps/cz\nshare/qemu/keymaps/da\nshare/qemu/keymaps/de\nshare/qemu/keymaps/de-ch\nshare/qemu/keymaps/en-gb\nshare/qemu/keymaps/en-us\nshare/qemu/keymaps/es\nshare/qemu/keymaps/et\nshare/qemu/keymaps/fi\nshare/qemu/keymaps/fo\nshare/qemu/keymaps/fr\nshare/qemu/keymaps/fr-be\nshare/qemu/keymaps/fr-ca\nshare/qemu/keymaps/fr-ch\nshare/qemu/keymaps/hr\nshare/qemu/keymaps/hu\nshare/qemu/keymaps/is\nshare/qemu/keymaps/it\nshare/qemu/keymaps/ja\nshare/qemu/keymaps/lt\nshare/qemu/keymaps/lv\nshare/qemu/keymaps/mk\nshare/qemu/keymaps/modifiers\nshare/qemu/keymaps/nl\nshare/qemu/keymaps/nl-be\nshare/qemu/keymaps/no\nshare/qemu/keymaps/pl\nshare/qemu/keymaps/pt\nshare/qemu/keymaps/pt-br\nshare/qemu/keymaps/ru\nshare/qemu/keymaps/sl\nshare/qemu/keymaps/sv\nshare/qemu/keymaps/th\nshare/qemu/keymaps/tr\nshare/qemu/trace-events-all\n"
  },
  {
    "path": "tools/virtualmips/.gitignore",
    "content": ".deps\npic32\nm4k\n*~\n"
  },
  {
    "path": "tools/virtualmips/LICENSE",
    "content": "The following points clarify the virtualmips license:\n\nvirtualmips as a whole is released under the GNU General Public License\n\n"
  },
  {
    "path": "tools/virtualmips/Makefile",
    "content": "TOPSRC!=cd ../..; pwd\n\n-include ../Makefile.inc\n\n#\n# Build VirtualMIPS simulator.\n#\n\n# Select target board:\n# chipKIT Max32\nCFLAGS\t\t= -DSIM_PIC32 -DPIC32MX7 -DMAX32\n\n# Maximite\n#CFLAGS\t\t= -DSIM_PIC32 -DPIC32MX7 -DMAXIMITE\n\n# Microchip Explorer 16\n#CFLAGS\t\t= -DSIM_PIC32 -DPIC32MX7 -DEXPLORER16\n\n# UBW32 with UART console\n#CFLAGS\t\t= -DSIM_PIC32 -DPIC32MX7 -DUBW32\n\n#CFLAGS\t\t+= -Wall -MT $@ -MD -MP -MF .deps/$*.dep -I/opt/local/include -I/opt/local/include/libelf\nCFLAGS\t\t+= -Wall -MT $@ -MD -MP -MF .deps/$*.dep -I/usr/local/include -I/usr/local/include/elftoolchain\nLIBS\t\t= -lpthread -lelf\n\nLIBS\t\t+= -L/usr/local/lib/elftoolchain\n\n# libbsd-dev package on Linux in overlay mode.\nCFLAGS+=\t${_LIBBSD_CFLAGS}\nLIBS+=\t\t${_LIBBSD_LIBS}\n\nADDLIBS!=if [ x\"${_HOST_OSNAME}\" = x\"OpenBSD\" ] ; then \\\n\t\techo \"-L/usr/local/lib -lintl\" ; \\\n\telif [ x\"${_HOST_OSNAME}\" = x\"Darwin\" ] ; then \\\n\t\techo \"-L/opt/local/lib -lintl\" ; \\\n\telif [ x\"${_HOST_OSNAME}\" = x\"Linux\" ] ; then \\\n\t\techo \"-lrt\" ; \\\n\telse \\\n\t\techo \"\" ; \\\n\tfi\n\nLIBS\t\t+= ${ADDLIBS}\n\n# Optimization.\nCFLAGS\t\t+= -O\n#CFLAGS\t\t+= -O3 -fomit-frame-pointer\n\n# Microchip PIC32MX\nPROG\t\t= pic32\nOBJS\t\t= pic32.o pic32_dev_flash.o pic32_dev_uart.o pic32_dev_intcon.o \\\n              pic32_dev_spi.o pic32_dev_gpio.o dev_sdcard.o dev_swap.o \\\n              pic32_dev_bmxcon.o pic32_dev_dmacon.o pic32_dev_syscon.o \\\n              pic32_dev_prefetch.o pic32_dev_adc.o pic32_dev_devcfg.o \\\n              pic32_dev_rtcc.o pic32_dev_timer.o\n\n# Generic M4K core\n#PROG\t\t= m4k\n#OBJS\t\t= m4k.o\n\n# Ingenic JZ4740.\n#CFLAGS\t\t+= -DSIM_PAVO -D_USE_FDD_\n#PROG\t\t= pavo\n#OBJS\t\t= pavo.o jz4740.o jz4740_dev_cpm.o jz4740_dev_dma.o \\\n#              jz4740_dev_emc.o jz4740_dev_gpio.o jz4740_dev_int.o \\\n#              jz4740_dev_rtc.o jz4740_dev_ts.o \\\n#              jz4740_dev_uart.o jz4740_dev_wdt_tcu.o\n\n# Implement LCD.\n#CFLAGS\t\t+= -DSIM_LCD\n#LIBS\t\t+= -lSDL\n#OBJS\t\t+= jz4740_dev_lcd.o vp_sdl.o\n\n# Use JIT compiler.\n#CFLAGS\t\t+= -D_USE_JIT_\n#OBJS\t\t+= mips_jit.o x86_trans.o\n\n# Common files.\nOBJS\t\t+= dev_cs8900.o dev_nand_flash_1g.o dev_ram.o \\\n               dev_vtty.o device.o vm.o cpu.o mips.o mips_cp0.o \\\n               mips_exec.o mips_fdd.o crc.o mips_hostalarm.o \\\n               mempool.o sbox.o utils.o vp_clock.o vp_timer.o net_io.o \\\n               mips_memory.o debug.o gdb_interface.o main.o \\\n               mips-dis.o config.o\n\nall:\t\t.deps $(PROG)\n\n$(PROG):\t$(OBJS)\n\t\t\t$(CC) $(LDFLAGS) -o $@ $(OBJS) $(LIBS)\n\n.deps:\n\t\t\t@mkdir .deps\n\ninstall:\tall\n\nclean:\n\t\trm -rf *.o *~ *_log.txt .deps pavo m4k pic32 pic32-log.txt *.core\n\n-include .deps/*.dep\n"
  },
  {
    "path": "tools/virtualmips/README",
    "content": "Please visit http://code.google.com/p/virtualmips/ to get the information of how to use VirtualMIPS."
  },
  {
    "path": "tools/virtualmips/SConstruct",
    "content": "#Build script of virtualmips.\n#Scons is really an excellent tool to build software!\n\nimport os,platform,SCons,glob,re,sys\n\n#########################\n#   Global Environment  #\n#########################\nbaseEnv=Environment()\n\nif ARGUMENTS.get('debug',0):\n\tbaseEnv.Append(CCFLAGS = \"-g\")\n     \n\nhelpString = \"\"\"\nUsage:\n        scons [target] [compile options]\nTargets:\n        pavo:                   Build VirtualMIPS for pavo emulation\n        mknandflash:            Build mknandflash tool\n\nCompile Options:\n        jit:                    Set to 0 to compile VirtualMIPS *without* JIT support(pavo only). Default 1.\n        lcd:                    Set to 0 to compile VirtualMIPS *without* LCD support(pavo only). Default 1.\n        mhz:                    Set to 1 to test emulator's speed. Default 0.\n        debug:                  Set to 1 to compile with -g. Default 0.\n        o:                      Set optimization level.Default 3.\n        cc:                     Set compiler.Default \"gcc\". You can set cc=gcc-3.4 to use gcc 3.4.\n\n\"\"\"\n\n\n#########################\n#  Project Environment  #\n#########################\n\n\nbaseEnv.Append(INCDIR = [os.path.join(os.path.abspath('.'),'../emulator')])\nbaseEnv.Append(INCDIR = [os.path.join(os.path.abspath('.'),'../emulator','device')])\nbaseEnv.Append(INCDIR = [os.path.join(os.path.abspath('.'),'../emulator','system')])\nbaseEnv.Append(INCDIR = [os.path.join(os.path.abspath('.'),'../emulator','mips')])\nbaseEnv.Append(INCDIR = [os.path.join(os.path.abspath('.'),'../emulator','utils')])\nbaseEnv.Append(INCDIR = [os.path.join(os.path.abspath('.'),'../emulator','utils','net')])\nbaseEnv.Append(INCDIR = [os.path.join(os.path.abspath('.'),'../emulator','memory')])\nbaseEnv.Append(INCDIR = [os.path.join(os.path.abspath('.'),'../emulator','gdb')])\n\t\n\t\nbaseEnv.Append(CPPPATH = baseEnv['INCDIR'])\nbaseEnv.Append(LIBS = ['confuse','pthread','rt','elf'] )  \nbaseEnv.Append(LIBPATH =  ['/usr/lib', '/usr/local/lib'] )  \n \nbaseEnv.Append(CCFLAGS=  \"-Wall  -fomit-frame-pointer\" ) \n\nmhz = ARGUMENTS.get('mhz', 0)\nif int(mhz):\n\t#test emulator's MHZ\n\tbaseEnv.Append(CCFLAGS = \"-DDEBUG_MHZ\")\n\n\no = ARGUMENTS.get('o', 3)\nif int(o)==3:\n\tbaseEnv.Append(CCFLAGS=  \"-O3\" ) \n\tbaseEnv.Append(LINKFLAGS =  \"-O3\" ) \nelif int(o)==2:\n\tbaseEnv.Append(CCFLAGS=  \"-O2\" ) \n\tbaseEnv.Append(LINKFLAGS =  \"-O2\" )\nelif int(o)==1:\n\tbaseEnv.Append(CCFLAGS=  \"-O1\" ) \n\tbaseEnv.Append(LINKFLAGS =  \"-O1\" ) \n\ncc1 = ARGUMENTS.get('cc', \"gcc\")\nif (cc1):\n\tbaseEnv.Replace(CC = cc1)   \n\n   \n\nHelp(helpString)\n \ndef listFiles(dirs,srcexts):\n\tallFiles = []\n\tfor dir in (dirs):\n\t\tpath= os.path.join(os.path.abspath(dir),srcexts)\n\t\tnewFiles = glob.glob(path)\n\t\tfor newFile in newFiles:\n\t\t\tallFiles.append(newFile)\n\treturn allFiles\n\n\n\n\nif 'pavo' in COMMAND_LINE_TARGETS:\n\tpavo = baseEnv.Clone() \t\t\n\tpavo.Append(CPPPATH = [os.path.join(os.path.abspath('.'),'../emulator','system','jz','soc')])\n\tpavo.Append(CPPPATH = [os.path.join(os.path.abspath('.'),'../emulator','system','jz','pavo')])\n\tpavo.Append(CPPPATH = [os.path.join(os.path.abspath('.'),'../emulator','utils','sdl')])\n\tpavo.Append(CCFLAGS = \"-DSIM_PAVO\")\n\tlcd = ARGUMENTS.get('lcd', 1)\n\tif int(lcd):\n\t\t#check libsdl\n\t\tconf = Configure(pavo)\n\t\tif not conf.CheckLib('SDL'):\n\t\t\tprint 'Did not find libSDL, exiting!'\n\t\t\tExit(1)\n\t\tif not conf.CheckCHeader('SDL/SDL.h'):\n\t\t\tprint 'SDL/SDL.h must be installed!'\n\t\t\tExit(1)\n\t\tpavo = conf.Finish()\n\t\tpavo.Append(CCFLAGS = \"-DSIM_LCD\")\n\t\tpavo.Append(LINKFLAGS  = \"-lSDL\")\n\t\n\tpavo.Program('pavo',listFiles(pavo['CPPPATH'],'*.c'))\n\t\n\t\t\t\nif 'mknandflash' in COMMAND_LINE_TARGETS:\n\tmknandflash=Environment()\n\tmknandflash.Program('mknandflash','../tool/mknandflash.c',LIBS = ['confuse'] )\t\n\n\n\n\n\n\n"
  },
  {
    "path": "tools/virtualmips/adm5120/adm5120.c",
    "content": " /*\n  * Copyright (C) yajin 2008<yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#define _GNU_SOURCE\n#include<string.h>\n#include <assert.h>\n#include<stdlib.h>\n#include <confuse.h>\n\n#include \"utils.h\"\n#include \"adm5120.h\"\n#include \"mips.h\"\n#include \"vm.h\"\n#include \"cpu.h\"\n#include \"mips_exec.h\"\n#include \"debug.h\"\n#include \"vp_lock.h\"\n\nint dev_sw_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len);\nint dev_rom_init (vm_instance_t * vm, char *name);\nint dev_nor_flash_4m_init (vm_instance_t * vm, char *name);\nint dev_mpmc_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len);\nint dev_intctrl_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len);\nint dev_uart_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len, vtty_t * vtty, int uart_index);\nint dev_pci_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len);\n\n/* Initialize default parameters for a adm5120 */\nstatic void adm5120_init_defaults (adm5120_t * adm5120)\n{\n    vm_instance_t *vm = adm5120->vm;\n\n    if (vm->configure_filename == NULL)\n        vm->configure_filename = strdup (ADM5120_DEFAULT_CONFIG_FILE);\n    vm->ram_size = ADM5120_DEFAULT_RAM_SIZE;\n    vm->boot_method = ADM5120_DEFAULT_BOOT_METHOD;\n    vm->kernel_filename = strdup (ADM5120_DEFAULT_KERNEL_FILENAME);\n}\n\n/* Initialize the adm5120 Platform (MIPS) */\nstatic int adm5120_init_platform (adm5120_t * adm5120)\n{\n    struct vm_instance *vm = adm5120->vm;\n    cpu_mips_t *cpu0;\n    void *(*cpu_run_fn) (void *);\n\n    vm_init_vtty (vm);\n\n    /* Create a CPU group */\n    vm->cpu_group = cpu_group_create (\"System CPU\");\n\n    /* Initialize the virtual MIPS processor */\n    if (!(cpu0 = cpu_create (vm, CPU_TYPE_MIPS32, 0))) {\n        vm_error (vm, \"unable to create CPU0!\\n\");\n        return (-1);\n    }\n    /* Add this CPU to the system CPU group */\n    cpu_group_add (vm->cpu_group, cpu0);\n    vm->boot_cpu = cpu0;\n\n    cpu_run_fn = (void *) mips_exec_run_cpu;\n    /* create the CPU thread execution */\n    if (pthread_create (&cpu0->cpu_thread, NULL, cpu_run_fn, cpu0) != 0) {\n        fprintf (stderr, \"cpu_create: unable to create thread for CPU%u\\n\",\n            0);\n        free (cpu0);\n        return (-1);\n    }\n    cpu0->addr_bus_mask = ADM5120_ADDR_BUS_MASK;\n\n    /* Initialize RAM */\n    vm_ram_init (vm, 0x00000000ULL);\n\n    /* Initialize ROM */\n    /*if (vm->rom_size!=0)\n     * {\n     * if (dev_rom_init(vm, \"ROM\")==-1)\n     * return (-1);\n     * } */\n\n    /* Initialize FLASH */\n    if ((vm->flash_size != 0) && (vm->flash_type == FLASH_TYPE_NOR_FLASH))\n        if (dev_nor_flash_4m_init (vm, \"NORFLASH4M\") == -1)\n            return (-1);\n\n    if (dev_sw_init (vm, \"SW\", ADM5120_SWCTRL_BASE, SW_INDEX_MAX * 4) == -1)\n        return (-1);\n    if (dev_mpmc_init (vm, \"MPMC\", ADM5120_MPMC_BASE,\n            MPMC_INDEX_MAX * 4) == -1)\n        return (-1);\n    if (dev_intctrl_init (vm, \"INT CTRL\", ADM5120_INTC_BASE,\n            INTCTRL_INDEX_MAX * 4) == -1)\n        return (-1);\n    if (dev_uart_init (vm, \"UART 0\", ADM5120_UART0_BASE, 0x24, vm->vtty_con1,\n            0) == -1)\n        return (-1);\n    if (dev_uart_init (vm, \"UART 1\", ADM5120_UART1_BASE, 0x24, vm->vtty_con2,\n            0) == -1)\n        return (-1);\n    if (dev_pci_init (vm, \"PCI\", ADM5120_PCI_BASE, PCI_INDEX_MAX * 4) == -1)\n        return (-1);\n\n    return (0);\n}\n\nextern m_uint32_t sw_table[SW_INDEX_MAX];\n/*set adm5120 reg default value. Only needed if boot from linux elf image.\nLinux will query sw_table[0x7] to get sdram size.\n */\nstatic void adm5120_reg_default_value (adm5120_t * adm5120)\n{\n    if (adm5120->vm->ram_size == 128)\n        sw_table[0x7] = 0x50405;        //  128M\n    else if (adm5120->vm->ram_size == 64)\n        sw_table[0x7] = 0x50404;        //  64m\n    else if (adm5120->vm->ram_size == 32)\n        sw_table[0x7] = 0x50423;        //16M *2\n    else if (adm5120->vm->ram_size == 16)\n        sw_table[0x7] = 0x50403;        //16M\n    else if (adm5120->vm->ram_size == 8)\n        sw_table[0x7] = 0x50402;        // 8M\n    else if (adm5120->vm->ram_size == 4)\n        sw_table[0x7] = 0x50401;        //  4M\n    else\n        ASSERT (0, \"Invalid ram_size.\\n Valid value:4,8,16,32,64,128\\n\");\n}\n\nstatic int adm5120_boot (adm5120_t * adm5120)\n{\n    vm_instance_t *vm = adm5120->vm;\n    cpu_mips_t *cpu;\n    m_va_t kernel_entry_point;\n\n    if (!vm->boot_cpu)\n        return (-1);\n\n    vm_suspend (vm);\n\n    /* Check that CPU activity is really suspended */\n    if (cpu_group_sync_state (vm->cpu_group) == -1) {\n        vm_error (vm, \"unable to sync with system CPUs.\\n\");\n        return (-1);\n    }\n\n    /* Reset the boot CPU */\n    cpu = (vm->boot_cpu);\n    mips_reset (cpu);\n\n    /*set configure register */\n    cpu->cp0.config_usable = 0x3;       /*only configure sel 0 and 1 is valid */\n    cpu->cp0.config_reg[0] = ADM5120_CONFIG0;\n    cpu->cp0.config_reg[1] = ADM5120_CONFIG1;\n\n    /*set PC and PRID */\n    cpu->cp0.reg[MIPS_CP0_PRID] = ADM5120_PRID;\n    cpu->cp0.tlb_entries = ADM5120_DEFAULT_TLB_ENTRYNO;\n    cpu->pc = ADM5120_ROM_PC;\n    /*If we boot from elf kernel image, load the image and set pc to elf entry */\n    if (vm->boot_method == BOOT_ELF) {\n        if (mips_load_elf_image (cpu, vm->kernel_filename,\n                &kernel_entry_point) == -1)\n            return (-1);\n        adm5120_reg_default_value (adm5120);\n        cpu->pc = kernel_entry_point;\n    }\n\n    /* Launch the simulation */\n    printf (\"\\nADM5120 '%s': starting simulation (CPU0 PC=0x%\" LL \"x), \"\n        \"JIT %sabled.\\n\", vm->name, cpu->pc, vm->jit_use ? \"en\" : \"dis\");\n\n    vm->status = VM_STATUS_RUNNING;\n    cpu_start (vm->boot_cpu);\n    return (0);\n\n}\n\nextern m_uint32_t intctrl_table[INTCTRL_INDEX_MAX];\n\n/*\nMapping adm irq to mips irq.\n\nSo why we need a mapping of interrupts?\n\nIN ADM5120,there are 10 interrupts\n0\t Timer\n1\tUart 0\n2\t Uart 1\n3\t USB Host\n4\t External I/O 0\n5\t External I/O 1\n6\t PCI 0\n7\t PCI 1\n8\t PCI 2\n9\t Switch\n\nADM5120 will triger INTERRUPT 2 and 3 to MIPS.\nINT_M(0X14) register control the interrupt releation of ADM5120 and iqr/firq.\n\n */\nint adm_irq2mips_irq (vm_instance_t * vm, u_int irq)\n{\n    m_uint32_t int_bit_mask = 0;\n\n    int_bit_mask = 1 << irq;\n    if ((intctrl_table[IRQ_MODE_REG / 4] & int_bit_mask) == int_bit_mask) {\n        return ADM5120_MIPSINT_FIQ;\n    } else\n        return ADM5120_MIPSINT_IRQ;\n\n}\n\nint whether_irq_enable (vm_instance_t * vm, u_int irq)\n{\n    m_uint32_t int_bit_mask = 0;\n\n    int_bit_mask = 1 << irq;\n    if ((intctrl_table[IRQ_ENABLE_REG / 4] & int_bit_mask) == int_bit_mask) {\n        return TRUE;\n    } else\n        return FALSE;\n\n}\n\nvoid adm5120_clear_irq (vm_instance_t * vm, u_int irq)\n{\n    assert (irq <= INT_LVL_MAX);\n    int mips_irq_no;\n    m_uint32_t int_bit_mask = 0;\n\n    int_bit_mask = 1 << irq;\n\n    /*clear raw status */\n    intctrl_table[IRQ_RAW_STATUS_REG / 4] &= ~int_bit_mask;\n\n    mips_irq_no = adm_irq2mips_irq (vm, irq);\n\n    if (ADM5120_MIPSINT_FIQ == mips_irq_no) {\n        intctrl_table[FIQ_STATUS_REG / 4] &= ~int_bit_mask;\n    } else {\n        intctrl_table[IRQ_STATUS_REG / 4] &= ~int_bit_mask;\n    }\n    irq = mips_irq_no;\n    mips_clear_irq (vm->boot_cpu, irq);\n\n}\n\n/*We must map adm irq to mips irq before setting irq*/\nvoid adm5120_set_irq (vm_instance_t * vm, u_int irq)\n{\n    assert (irq <= INT_LVL_MAX);\n\n    int mips_irq_no;\n    m_uint32_t int_bit_mask = 0;\n\n    int_bit_mask = 1 << irq;\n\n    /*set raw status */\n    intctrl_table[IRQ_RAW_STATUS_REG / 4] |= int_bit_mask;\n\n    /*check whether irq is enabled */\n    if (whether_irq_enable (vm, irq) == FALSE)\n        return;\n\n    mips_irq_no = adm_irq2mips_irq (vm, irq);\n\n    if (ADM5120_MIPSINT_FIQ == mips_irq_no) {\n        intctrl_table[FIQ_STATUS_REG / 4] |= int_bit_mask;\n    } else {\n        intctrl_table[IRQ_STATUS_REG / 4] |= int_bit_mask;\n    }\n\n    irq = mips_irq_no;\n    mips_set_irq (vm->boot_cpu, irq);\n    mips_update_irq_flag (vm->boot_cpu);\n\n}\n\nCOMMON_CONFIG_INFO_ARRAY static void printf_configure (adm5120_t * adm5120)\n{\n    vm_instance_t *vm = adm5120->vm;\n    PRINT_COMMON_CONFIG_OPTION;\n}\n\nstatic void adm5120_parse_configure (adm5120_t * adm5120)\n{\n    vm_instance_t *vm = adm5120->vm;\n    cfg_opt_t opts[] = {\n        COMMON_CONFIG_OPTION CFG_END ()\n    };\n    cfg_t *cfg;\n\n    cfg = cfg_init (opts, 0);\n    cfg_parse (cfg, vm->configure_filename);\n    cfg_free (cfg);\n\n    VALID_COMMON_CONFIG_OPTION;\n\n    if (vm->boot_method == BOOT_BINARY) {\n        ASSERT (vm->boot_from == 1,\n            \"boot_from must be 1(NOR Flash)\\n ADM5120 only can boot from NOR Flash.\\n\");\n    }\n\n    /*Print the configure information */\n    printf_configure (adm5120);\n\n}\n\n/* Create a router instance */\nvm_instance_t *create_instance (char *configure_filename)\n{\n    adm5120_t *adm5120;\n    char *name;\n    if (!(adm5120 = malloc (sizeof (*adm5120)))) {\n        fprintf (stderr, \"ADM5120': Unable to create new instance!\\n\");\n        return NULL;\n    }\n\n    memset (adm5120, 0, sizeof (*adm5120));\n    name = strdup (\"adm5120\");\n\n    if (!(adm5120->vm = vm_create (name, VM_TYPE_ADM5120))) {\n        fprintf (stderr, \"ADM5120 : unable to create VM instance!\\n\");\n        goto err_vm;\n    }\n    free (name);\n    if (configure_filename != NULL)\n        adm5120->vm->configure_filename = strdup (configure_filename);\n    adm5120_init_defaults (adm5120);\n    adm5120_parse_configure (adm5120);\n    /*init gdb debug */\n    vm_debug_init (adm5120->vm);\n\n    adm5120->vm->hw_data = adm5120;\n\n    return (adm5120->vm);\n\n  err_vm:\n    free (adm5120);\n    return NULL;\n\n}\n\nint init_instance (vm_instance_t * vm)\n{\n    adm5120_t *adm5120 = VM_ADM5120 (vm);\n\n    if (adm5120_init_platform (adm5120) == -1) {\n        vm_error (vm, \"unable to initialize the platform hardware.\\n\");\n        return (-1);\n    }\n    /* IRQ routing */\n    vm->set_irq = adm5120_set_irq;\n    vm->clear_irq = adm5120_clear_irq;\n\n    return (adm5120_boot (adm5120));\n\n}\n"
  },
  {
    "path": "tools/virtualmips/adm5120/adm5120.conf",
    "content": "#configure file for adm5120\n\n# RAM size in kbytes. If not set, default value is 16384.\nram_size = 16384\n\n#There are two methods for virtualmips to boot the image.\n#Binary. It means virtualmips direct boots the image from ROM or flash. The entry pc is 0x1fc00000. The image contains bootloader and kernel/rootfs.\n#ELF. It means virtualmips reads an elf image(setten by kernel_file_name) into sdram and then boots from elf entry point. The elf image contains kernel and rootfs.\n#Default boot method is ELF.\n#1:Binary 2:elf\nboot_method = 2\n\n\n#boot_from MUST be set if boot_method=1.\n#1:NOR_FLASH  2 NAND FLASH\nboot_from = 1\n\n#If boot_method is elf, that means boot the elf image.kernel_file_name gives the elf image path.\n#kernel_file_name MUST be set if  boot_method=2.\nkernel_file_name = \"vmlinux-adm5120\"\n\n#1 NOR 2 NAND\nflash_type = 1\n#Flash size. 4 and 0 is valid for NOR type flash. 0 means no flash emulation. 4 means 4M bytes flash(device id=22F9h) emulation.\nflash_size = 4\n#Flash file path. If this file does not exist, virtualmips will create it.\nflash_file_name = \"run.bin\"\n#flash physical address. for nor flash only\nflash_phy_address = 0x1fc00000\n\n#set to 1 to enable gdb debug\ngdb_debug = 0\n#the port for remote gdb connection\ngdb_port = 5555\n"
  },
  {
    "path": "tools/virtualmips/adm5120/adm5120.h",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *     \n  * This file is part of the virtualmips distribution. \n  * See LICENSE file for terms of the license. \n  *\n  */\n\n#ifndef __ADM5120_H__\n#define __ADM5120_H__\n\n#include \"types.h\"\n\n/*virtual address and physical address*/\ntypedef m_uint32_t m_va_t;\ntypedef m_uint32_t m_pa_t;\ntypedef m_uint32_t m_reg_t;\ntypedef m_int32_t m_ireg_t;\ntypedef m_uint32_t m_cp0_reg_t;\n\n#define  DATA_WIDTH 32          /*64 */\n#define LL\n\n/*ADM5120 use soft fpu*/\n#define SOFT_FPU   1\n\n/*Guest endian*/\n#define GUEST_BYTE_ORDER  ARCH_LITTLE_ENDIAN\n#ifndef GUEST_BYTE_ORDER\n#error Please define guest architecture in utils.h!\n#endif\n\n/* Host to VM conversion functions */\n#if HOST_BYTE_ORDER == GUEST_BYTE_ORDER\n#define htovm16(x) (x)\n#define htovm32(x) (x)\n#define htovm64(x) (x)\n\n#define vmtoh16(x) (x)\n#define vmtoh32(x) (x)\n#define vmtoh64(x) (x)\n#elif HOST_BYTE_ORDER==ARCH_LITTLE_ENDIAN       //host:little guest:big\n#define htovm16(x) (htons(x))\n#define htovm32(x) (htonl(x))\n#define htovm64(x) (swap64(x))\n\n#define vmtoh16(x) (ntohs(x))\n#define vmtoh32(x) (ntohl(x))\n#define vmtoh64(x) (swap64(x))\n#else //host:big guest:little\n\n#define htovm16(x) (ntohs(x))\n#define htovm32(x) (ntohl(x))\n#define htovm64(x) (swap64(x))\n\n#define vmtoh16(x) (htons(x))\n#define vmtoh32(x) (htonl(x))\n#define vmtoh64(x) (swap64(x))\n#endif\n\n#define ADM5120_DEFAULT_CONFIG_FILE     \"adm5120.conf\"\n#define ADM5120_DEFAULT_RAM_SIZE     16\n#define ADM5120_DEFAULT_BOOT_METHOD     BOOT_ELF\n#define ADM5120_DEFAULT_KERNEL_FILENAME     \"vmlinux\"\n#define ADM5120_ADDR_BUS_MASK   0xffffffff      /*32bit phy address */\n\n#define ADM5120_CONFIG0  0x80000082\n#define ADM5120_CONFIG1 0x3E613080      /*CACHE (128SET*32 BYTES*2 WAY)= 8K */\n//#define ADM5120_CONFIG7 0x0  \n\n//#define SOC_CONFIG0 ADM5120_CONFIG0\n//#define SOC_CONFIG1 ADM5120_CONFIG1\n//#define SOC_CONFIG7 ADM5120_CONFIG7\n\n#define ADM5120_ROM_PC  0xbfc00000UL\n#define ADM5120_PRID    0x0001800b\n#define ADM5120_DEFAULT_TLB_ENTRYNO   16\n\nstruct adm5120_system {\n    /* Associated VM instance */\n    vm_instance_t *vm;\n};\n\ntypedef struct adm5120_system adm5120_t;\n\n#define VM_ADM5120(vm) ((adm5120_t *)vm->hw_data)\n\nvm_instance_t *create_instance (char *conf);\nint init_instance (vm_instance_t * vm);\n\n//void virtual_timer(cpu_mips_t *cpu);\n\n/*---------ADM5120 SOC releated--------------------*/\n\n/*=========================  Physical Memory Map  ============================*/\n#define ADM5120_SDRAM_BASE\t\t\t\t\t\t0\n#define ADM5120_SMEM1_BASE\t\t\t\t\t\t0x10000000\n\n#define ADM5120_EXTIO0_BASE\t\t\t\t\t\t0x10C00000\n#define ADM5120_EXTIO1_BASE\t\t\t\t\t\t0x10E00000\n#define ADM5120_MPMC_BASE\t\t\t\t\t\t0x11000000\n#define ADM5120_USBHOST_BASE\t\t\t\t\t0x11200000\n#define ADM5120_PCIMEM_BASE\t\t\t\t\t\t0x11400000\n#define ADM5120_PCIIO_BASE\t\t\t\t\t\t0x11500000\n#define ADM5120_PCICFG_BASE\t\t\t\t\t\t0x115FFFF0\n#define ADM5120_MIPS_BASE\t\t\t\t\t\t0x11A00000\n#define ADM5120_SWCTRL_BASE\t\t\t\t\t\t0x12000000\n\n#define ADM5120_INTC_BASE\t\t\t\t\t\t0x12200000\n#define ADM5120_SYSC_BASE\t\t\t\t\t\t0x12400000\n\n#define ADM5120_UART0_BASE\t\t\t\t\t\t0x12600000\n#define ADM5120_UART1_BASE\t\t\t\t\t\t0x12800000\n\n#define ADM5120_SMEM0_BASE\t\t\t\t\t\t0x1FC00000\n\n/*=========================  Switch Control Register  ========================*/\n/* Control Register */\n#define CODE_REG\t\t\t\t\t\t\t\t0x0000\n#define SftRest_REG\t\t\t\t\t\t\t\t0x0004\n#define Boot_done_REG\t\t\t\t\t\t\t0x0008\n#define SWReset_REG\t\t\t\t\t\t\t\t0x000C\n#define Global_St_REG\t\t\t\t\t\t\t0x0010\n#define PHY_st_REG\t\t\t\t\t\t\t\t0x0014\n#define Port_st_REG\t\t\t\t\t\t\t\t0x0018\n#define Mem_control_REG\t\t\t\t\t\t\t0x001C\n#define SW_conf_REG\t\t\t\t\t\t\t\t0x0020\n#define CPUp_conf_REG\t\t\t\t\t\t\t0x0024\n#define Port_conf0_REG\t\t\t\t\t\t\t0x0028\n#define Port_conf1_REG\t\t\t\t\t\t\t0x002C\n#define Port_conf2_REG\t\t\t\t\t\t\t0x0030\n\n#define VLAN_G1_REG\t\t\t\t\t\t\t\t0x0040\n#define VLAN_G2_REG\t\t\t\t\t\t\t\t0x0044\n#define Send_trig_REG\t\t\t\t\t\t\t0x0048\n#define Srch_cmd_REG\t\t\t\t\t\t\t0x004C\n#define ADDR_st0_REG\t\t\t\t\t\t\t0x0050\n#define ADDR_st1_REG\t\t\t\t\t\t\t0x0054\n#define MAC_wt0_REG\t\t\t\t\t\t\t\t0x0058\n#define MAC_wt1_REG\t\t\t\t\t\t\t\t0x005C\n#define BW_cntl0_REG\t\t\t\t\t\t\t0x0060\n#define BW_cntl1_REG\t\t\t\t\t\t\t0x0064\n#define PHY_cntl0_REG\t\t\t\t\t\t\t0x0068\n#define PHY_cntl1_REG\t\t\t\t\t\t\t0x006C\n#define FC_th_REG\t\t\t\t\t\t\t\t0x0070\n#define Adj_port_th_REG\t\t\t\t\t\t\t0x0074\n#define Port_th_REG\t\t\t\t\t\t\t\t0x0078\n#define PHY_cntl2_REG\t\t\t\t\t\t\t0x007C\n#define PHY_cntl3_REG\t\t\t\t\t\t\t0x0080\n#define Pri_cntl_REG\t\t\t\t\t\t\t0x0084\n#define VLAN_pri_REG\t\t\t\t\t\t\t0x0088\n#define TOS_en_REG\t\t\t\t\t\t\t\t0x008C\n#define TOS_map0_REG\t\t\t\t\t\t\t0x0090\n#define TOS_map1_REG\t\t\t\t\t\t\t0x0094\n#define Custom_pri1_REG\t\t\t\t\t\t\t0x0098\n#define Custom_pri2_REG\t\t\t\t\t\t\t0x009C\n#define PHY_cntl4_REG\t\t\t\t\t\t\t0x00A0\n#define Empty_cnt_REG\t\t\t\t\t\t\t0x00A4\n#define Port_cnt_sel_REG\t\t\t\t\t\t0x00A8\n#define Port_cnt_REG\t\t\t\t\t\t\t0x00AC\n#define SW_Int_st_REG\t\t\t\t\t\t\t0x00B0\n#define SW_Int_mask_REG\t\t\t\t\t\t\t0x00B4\n\n// GPIO config\n#define GPIO_conf0_REG\t\t\t\t\t\t\t0x00B8\n#define GPIO_conf2_REG\t\t\t\t\t\t\t0x00BC\n\n// Watch dog\n#define Watchdog0_REG\t\t\t\t\t\t\t0x00C0\n#define Watchdog1_REG\t\t\t\t\t\t\t0x00C4\n\n#define Swap_in_REG\t\t\t\t\t\t\t\t0x00C8\n#define Swap_out_REG\t\t\t\t\t\t\t0x00CC\n\n// Tx/Rx Descriptors\n#define Send_HBaddr_REG\t\t\t\t\t\t\t0x00D0\n#define Send_LBaddr_REG\t\t\t\t\t\t\t0x00D4\n#define Recv_HBaddr_REG\t\t\t\t\t\t\t0x00D8\n#define Recv_LBaddr_REG\t\t\t\t\t\t\t0x00DC\n#define Send_HWaddr_REG\t\t\t\t\t\t\t0x00E0\n#define Send_LWaddr_REG\t\t\t\t\t\t\t0x00E4\n#define Recv_HWaddr_REG\t\t\t\t\t\t\t0x00E8\n#define Recv_LWaddr_REG\t\t\t\t\t\t\t0x00EC\n\n// Timer Control \n#define Timer_int_REG\t\t\t\t\t\t\t0x00F0\n#define Timer_REG\t\t\t\t\t\t\t\t0x00F4\n\n// LED control\n#define Port0_LED_REG\t\t\t\t\t\t\t0x0100\n#define Port1_LED_REG\t\t\t\t\t\t\t0x0104\n#define Port2_LED_REG\t\t\t\t\t\t\t0x0108\n#define Port3_LED_REG\t\t\t\t\t\t\t0x010c\n#define Port4_LED_REG\t\t\t\t\t\t\t0x0110\n\n#define SW_INDEX_MAX\t\t\t\t\t\t\t0x45    //0x0114/4\n\n/* Timer_int_REG */\n#define SW_TIMER_INT_DISABLE\t\t\t\t\t0x10000\n#define SW_TIMER_INT\t\t\t\t\t\t\t0x1\n\n/* Timer_REG */\n#define SW_TIMER_EN\t\t\t\t\t\t\t\t0x10000\n#define SW_TIMER_MASK\t\t\t\t\t\t\t0xffff\n#define SW_TIMER_10MS_TICKS\t\t\t\t\t\t0x3D09\n#define SW_TIMER_1MS_TICKS\t\t\t\t\t\t0x61A\n#define SW_TIMER_100US_TICKS\t\t\t\t\t0x9D\n\n/*====================  MultiPort Memory Controller (MPMC) ==================*/\n/* registers offset */\n#define MPMC_CONTROL_REG\t\t\t\t\t\t0x0000\n#define MPMC_STATUS_REG\t\t\t\t\t\t\t0x0004\n#define MPMC_CONFIG_REG\t\t\t\t\t\t\t0x0008\n\n#define MPMC_DM_CONTROL_REG\t\t\t\t\t\t0x0020\n#define MPMC_DM_REFRESH_REG\t\t\t\t\t\t0x0024\n\n#define MPMC_DM_TRP_REG\t\t\t\t\t\t\t0x0030\n#define MPMC_DM_TRAS_REG\t\t\t\t\t\t0x0034\n#define MPMC_DM_TSREX_REG\t\t\t\t\t\t0x0038\n#define MPMC_DM_TAPR_REG\t\t\t\t\t\t0x003C\n#define MPMC_DM_TDAL_REG\t\t\t\t\t\t0x0040\n#define MPMC_DM_TWR_REG\t\t\t\t\t\t\t0x0044\n#define MPMC_DM_TRC_REG\t\t\t\t\t\t\t0x0048\n#define MPMC_DM_TRFC_REG\t\t\t\t\t\t0x004C\n#define MPMC_DM_TXSR_REG\t\t\t\t\t\t0x0050\n#define MPMC_DM_TRRD_REG\t\t\t\t\t\t0x0054\n#define MPMC_DM_TMRD_REG\t\t\t\t\t\t0x0058\n\n#define MPMC_SM_EXTWAIT_REG\t\t\t\t\t\t0x0080\n\n#define MPMC_DM_CONFIG0_REG\t\t\t\t\t\t0x0100\n#define MPMC_DM_RASCAS0_REG\t\t\t\t\t\t0x0104\n\n#define MPMC_DM_CONFIG1_REG\t\t\t\t\t\t0x0120\n#define MPMC_DM_RASCAS1_REG\t\t\t\t\t\t0x0124\n\n#define MPMC_SM_CONFIG0_REG\t\t\t\t\t\t0x0200\n#define MPMC_SM_WAITWEN0_REG\t\t\t\t\t0x0204\n#define MPMC_SM_WAITOEN0_REG\t\t\t\t\t0x0208\n#define MPMC_SM_WAITRD0_REG\t\t\t\t\t\t0x020C\n#define MPMC_SM_WAITPAGE0_REG\t\t\t\t\t0x0210\n#define MPMC_SM_WAITWR0_REG\t\t\t\t\t\t0x0214\n#define MPMC_SM_WAITTURN0_REG\t\t\t\t\t0x0218\n\n#define MPMC_SM_CONFIG1_REG\t\t\t\t\t\t0x0220\n#define MPMC_SM_WAITWEN1_REG\t\t\t\t\t0x0224\n#define MPMC_SM_WAITOEN1_REG\t\t\t\t\t0x0228\n#define MPMC_SM_WAITRD1_REG\t\t\t\t\t\t0x022C\n#define MPMC_SM_WAITPAGE1_REG\t\t\t\t\t0x0230\n#define MPMC_SM_WAITWR1_REG\t\t\t\t\t\t0x0234\n#define MPMC_SM_WAITTURN1_REG\t\t\t\t\t0x0238\n\n#define MPMC_SM_CONFIG2_REG\t\t\t\t\t\t0x0240\n#define MPMC_SM_WAITWEN2_REG\t\t\t\t\t0x0244\n#define MPMC_SM_WAITOEN2_REG\t\t\t\t\t0x0248\n#define MPMC_SM_WAITRD2_REG\t\t\t\t\t\t0x024C\n#define MPMC_SM_WAITPAGE2_REG\t\t\t\t\t0x0250\n#define MPMC_SM_WAITWR2_REG\t\t\t\t\t\t0x0254\n#define MPMC_SM_WAITTURN2_REG\t\t\t\t\t0x0258\n\n#define MPMC_SM_CONFIG3_REG\t\t\t\t\t\t0x0260\n#define MPMC_SM_WAITWEN3_REG\t\t\t\t\t0x0264\n#define MPMC_SM_WAITOEN3_REG\t\t\t\t\t0x0268\n#define MPMC_SM_WAITRD3_REG\t\t\t\t\t\t0x026C\n#define MPMC_SM_WAITPAGE3_REG\t\t\t\t\t0x0270\n#define MPMC_SM_WAITWR3_REG\t\t\t\t\t\t0x0274\n#define MPMC_SM_WAITTURN3_REG\t\t\t\t\t0x0278\n\n#define MPMC_INDEX_MAX\t\t\t\t\t\t\t0x9f    //0x027C/4\n\n/*===========================  UART Control Register  \n========================*/\n#define UART_DR_REG\t\t\t\t\t\t\t\t0x00\n#define UART_RSR_REG\t\t\t\t\t\t\t0x04\n#define UART_ECR_REG\t\t\t\t\t\t\t0x04\n#define UART_LCR_H_REG\t\t\t\t\t\t\t0x08\n#define UART_LCR_M_REG\t\t\t\t\t\t\t0x0c\n#define UART_LCR_L_REG\t\t\t\t\t\t\t0x10\n#define UART_CR_REG\t\t\t\t\t\t\t\t0x14\n#define UART_FR_REG\t\t\t\t\t\t\t\t0x18\n#define UART_IIR_REG\t\t\t\t\t\t\t0x1c\n#define UART_ICR_REG\t\t\t\t\t\t\t0x1C\n#define UART_ILPR_REG\t\t\t\t\t\t\t0x20\n\n/*  rsr/ecr reg  */\n#define UART_OVERRUN_ERR\t\t\t\t\t\t0x08\n#define UART_BREAK_ERR\t\t\t\t\t\t\t0x04\n#define UART_PARITY_ERR\t\t\t\t\t\t\t0x02\n#define UART_FRAMING_ERR\t\t\t\t\t\t0x01\n#define UART_RX_STATUS_MASK\t\t\t\t\t\t0x0f\n#define UART_RX_ERROR\t\t\t\t\t\t\t( UART_BREAK_ERR\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t| UART_PARITY_ERR\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t| UART_FRAMING_ERR)\n\n/*  lcr_h reg  */\n#define UART_SEND_BREAK\t\t\t\t\t\t\t0x01\n#define UART_PARITY_EN\t\t\t\t\t\t\t0x02\n#define UART_EVEN_PARITY\t\t\t\t\t\t0x04\n#define UART_TWO_STOP_BITS\t\t\t\t\t\t0x08\n#define UART_ENABLE_FIFO\t\t\t\t\t\t0x10\n\n#define UART_WLEN_5BITS\t\t\t\t\t\t\t0x00\n#define UART_WLEN_6BITS\t\t\t\t\t\t\t0x20\n#define UART_WLEN_7BITS\t\t\t\t\t\t\t0x40\n#define UART_WLEN_8BITS\t\t\t\t\t\t\t0x60\n#define UART_WLEN_MASK\t\t\t\t\t\t\t0x60\n\n/*  cr reg  */\n#define UART_PORT_EN\t\t\t\t\t\t\t0x01\n#define UART_SIREN\t\t\t\t\t\t\t\t0x02\n#define UART_SIRLP\t\t\t\t\t\t\t\t0x04\n#define UART_MODEM_STATUS_INT_EN\t\t\t\t0x08\n#define UART_RX_INT_EN\t\t\t\t\t\t\t0x10\n#define UART_TX_INT_EN\t\t\t\t\t\t\t0x20\n#define UART_RX_TIMEOUT_INT_EN\t\t\t\t\t0x40\n#define UART_LOOPBACK_EN\t\t\t\t\t\t0x80\n\n/*  fr reg  */\n#define UART_CTS\t\t\t\t\t\t\t\t0x01\n#define UART_DSR\t\t\t\t\t\t\t\t0x02\n#define UART_DCD\t\t\t\t\t\t\t\t0x04\n#define UART_BUSY\t\t\t\t\t\t\t\t0x08\n#define UART_RX_FIFO_EMPTY\t\t\t\t\t\t0x10\n#define UART_TX_FIFO_FULL\t\t\t\t\t\t0x20\n#define UART_RX_FIFO_FULL\t\t\t\t\t\t0x40\n#define UART_TX_FIFO_EMPTY\t\t\t\t\t\t0x80\n\n/*  iir/icr reg  */\n#define UART_MODEM_STATUS_INT\t\t\t\t\t0x01\n#define UART_RX_INT\t\t\t\t\t\t\t\t0x02\n#define UART_TX_INT\t\t\t\t\t\t\t\t0x04\n#define UART_RX_TIMEOUT_INT\t\t\t\t\t\t0x08\n\n#define UART_INT_MASK\t\t\t\t\t\t\t0x0f\n\n#define ADM5120_UARTCLK_FREQ\t\t\t\t\t62500000\n\n/*  uart_baudrate  */\n#define UART_230400bps_DIVISOR\t\t\t\t\tUART_BAUDDIV(230400)\n// #define UART_115200bps_DIVISOR                                       UART_BAUDDIV(115200)\n#define UART_115200bps_DIVISOR\t\t\t\t\t33\n// #define UART_76800bps_DIVISOR                                        UART_BAUDDIV(76800)\n#define UART_76800bps_DIVISOR\t\t\t\t\t50\n// #define UART_57600bps_DIVISOR                                        UART_BAUDDIV(57600)\n#define UART_57600bps_DIVISOR\t\t\t\t\t67\n//#define UART_38400bps_DIVISOR                                 UART_BAUDDIV(38400)\n#define UART_38400bps_DIVISOR\t\t\t\t\t102\n//#define UART_19200bps_DIVISOR                                 UART_BAUDDIV(19200)\n#define UART_19200bps_DIVISOR\t\t\t\t\t202\n//#define UART_14400bps_DIVISOR                                 UART_BAUDDIV(14400)\n#define UART_14400bps_DIVISOR\t\t\t\t\t270\n//#define UART_9600bps_DIVISOR                                  UART_BAUDDIV(9600)\n#define UART_9600bps_DIVISOR\t\t\t\t\t406\n//#define UART_2400bps_DIVISOR                                  UART_BAUDDIV(2400)\n#define UART_2400bps_DIVISOR\t\t\t\t\t1627\n//#define UART_1200bps_DIVISOR                                  UART_BAUDDIV(1200)\n\n#define UART_INDEX_MAX\t\t\t\t\t\t\t0x9     //0x024/4\n\n/* pci space \npci memory  0x1140 0000- 0x114f ffff\npci io            0x1150 0000 - 0x 115f ffef\npci configuration address port  0x115ffff0\npci configuration data port       0x115ffff8\n\n*/\n#define ADM5120_PCI_BASE\t\t\t\t\t\t0x11400000\n#define PCI_INDEX_MAX                         0X80000   //0X200000/4\n\n/*==========================  Interrupt Controller  ==========================*/\n/* registers offset */\n#define IRQ_STATUS_REG\t\t\t\t\t\t\t0x00    /* Read */\n#define IRQ_RAW_STATUS_REG\t\t\t\t\t\t0x04    /* Read */\n#define IRQ_ENABLE_REG\t\t\t\t\t\t\t0x08    /* Read/Write */\n#define IRQ_DISABLE_REG\t\t\t\t\t\t\t0x0C    /* Write */\n#define IRQ_SOFT_REG\t\t\t\t\t\t\t0x10    /* Write */\n\n#define IRQ_MODE_REG\t\t\t\t\t\t\t0x14    /* Read/Write */\n#define FIQ_STATUS_REG\t\t\t\t\t\t\t0x18    /* Read */\n\n/* test registers */\n#define IRQ_TESTSRC_REG\t\t\t\t\t\t\t0x1c    /* Read/Write */\n#define IRQ_SRCSEL_REG\t\t\t\t\t\t\t0x20    /* Read/Write */\n#define IRQ_LEVEL_REG\t\t\t\t\t\t\t0x24    /* Read/Write */\n\n#define INTCTRL_INDEX_MAX\t\t\t\t\t\t\t0xa     //0x028/4\n\n/* interrupt levels */\n#define INT_LVL_TIMER\t\t\t\t\t\t\t0       /* Timer */\n#define INT_LVL_UART0\t\t\t\t\t\t\t1       /* Uart 0 */\n#define INT_LVL_UART1\t\t\t\t\t\t\t2       /* Uart 1 */\n#define INT_LVL_USBHOST\t\t\t\t\t\t\t3       /* USB Host */\n#define INT_LVL_EXTIO_0\t\t\t\t\t\t\t4       /* External I/O 0 */\n#define INT_LVL_EXTIO_1\t\t\t\t\t\t\t5       /* External I/O 1 */\n#define INT_LVL_PCI_0\t\t\t\t\t\t\t6       /* PCI 0 */\n#define INT_LVL_PCI_1\t\t\t\t\t\t\t7       /* PCI 1 */\n#define INT_LVL_PCI_2\t\t\t\t\t\t\t8       /* PCI 2 */\n#define INT_LVL_SWITCH\t\t\t\t\t\t\t9       /* Switch */\n#define INT_LVL_MAX\t\t\t\t\t\t\t\tINT_LVL_SWITCH\n\n/* interrupts */\n#define IRQ_TIMER\t\t\t\t\t\t\t\t(0x1 << INT_LVL_TIMER)\n#define IRQ_UART0\t\t\t\t\t\t\t\t(0x1 << INT_LVL_UART0)\n#define IRQ_UART1\t\t\t\t\t\t\t\t(0x1 << INT_LVL_UART1)\n#define IRQ_USBHOST\t\t\t\t\t\t\t\t(0x1 << INT_LVL_USBHOST)\n#define IRQ_EXTIO_0\t\t\t\t\t\t\t\t(0x1 << INT_LVL_EXTIO_0)\n#define IRQ_EXTIO_1\t\t\t\t\t\t\t\t(0x1 << INT_LVL_EXTIO_1)\n#define IRQ_PCI_INT0\t\t\t\t\t\t\t(0x1 << INT_LVL_PCI_0)\n#define IRQ_PCI_INT1\t\t\t\t\t\t\t(0x1 << INT_LVL_PCI_1)\n#define IRQ_PCI_INT2\t\t\t\t\t\t\t(0x1 << INT_LVL_PCI_2)\n#define IRQ_SWITCH\t\t\t\t\t\t\t\t(0x1 << INT_LVL_SWITCH)\n\n#define IRQ_MASK\t\t\t\t\t\t\t\t0x3ff\n\n#define ADM5120_MIPSINT_SOFT0\t\t\t\t\t0\n#define ADM5120_MIPSINT_SOFT1\t\t\t\t\t1\n#define ADM5120_MIPSINT_IRQ\t\t\t\t\t\t2\n#define ADM5120_MIPSINT_FIQ\t\t\t\t\t\t3\n#define ADM5120_MIPSINT_REV0\t\t\t\t\t4\n#define ADM5120_MIPSINT_REV1\t\t\t\t\t5\n#define ADM5120_MIPSINT_REV2\t\t\t\t\t6\n#define ADM5120_MIPSINT_TIMER\t\t\t\t\t7\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/adm5120/adm5120_dev_intctrl.c",
    "content": " /*\n  * Copyright (C) yajin 2008<yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include<sys/types.h>\n#include<sys/stat.h>\n#include<string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"adm5120.h\"\n#include \"cpu.h\"\n\nm_uint32_t intctrl_table[INTCTRL_INDEX_MAX];\n\nstruct intctrl_data {\n    struct vdevice *dev;\n    m_uint8_t *intctrl_ptr;\n    m_uint32_t intctrl_size;\n};\n\nvoid *dev_intctrl_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t * data,\n    m_uint8_t * has_set_value)\n{\n\n    struct intctrl_data *d = dev->priv_data;\n\n    if (offset >= d->intctrl_size) {\n        *data = 0;\n        return NULL;\n    }\n\n    switch (offset) {\n    case IRQ_DISABLE_REG:\n        if (MTS_WRITE == op_type) {\n            intctrl_table[IRQ_ENABLE_REG / 4] = *data & 0x3ff;\n            *has_set_value = TRUE;\n            return NULL;\n        }\n        break;\n    }\n\n    return ((void *) (d->intctrl_ptr + offset));\n}\n\nvoid dev_intctrl_init_defaultvalue ()\n{\n\n}\n\nint dev_intctrl_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len)\n{\n    struct intctrl_data *d;\n\n    /* allocate the private data structure */\n    if (!(d = malloc (sizeof (*d)))) {\n        fprintf (stderr, \"INTCTRL: unable to create device.\\n\");\n        return (-1);\n    }\n\n    memset (d, 0, sizeof (*d));\n    if (!(d->dev = dev_create (name)))\n        goto err_dev_create;\n    d->dev->priv_data = d;\n    d->dev->phys_addr = paddr;\n    d->dev->phys_len = len;\n    d->intctrl_ptr = (m_uint8_t *) (m_iptr_t) (&intctrl_table[0]);\n    d->intctrl_size = len;\n    d->dev->handler = dev_intctrl_access;\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n\n    vm_bind_device (vm, d->dev);\n    dev_intctrl_init_defaultvalue ();\n    return (0);\n\n  err_dev_create:\n    free (d);\n    return (-1);\n}\n"
  },
  {
    "path": "tools/virtualmips/adm5120/adm5120_dev_mpmc.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *     \n  * This file is part of the virtualmips distribution. \n  * See LICENSE file for terms of the license. \n  *\n  */\n\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include<sys/types.h>\n#include<sys/stat.h>\n#include<string.h>\n\n#include \"device.h\"\n#include \"memory.h\"\n#include \"adm5120.h\"\n#include \"cpu.h\"\n\nm_uint32_t mpmc_table[MPMC_INDEX_MAX];\n\nstruct mpmc_data {\n    struct vdevice *dev;\n    m_uint8_t *mpmc_ptr;\n    m_uint32_t mpmc_size;\n};\n\nvoid *dev_mpmc_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t * data,\n    m_uint8_t * has_set_value)\n{\n    struct mpmc_data *d = dev->priv_data;\n\n    if (offset >= d->mpmc_size) {\n        *data = 0;\n        return NULL;\n    }\n    return ((void *) (d->mpmc_ptr + offset));\n}\n\nvoid dev_mpmc_init_defaultvalue ()\n{\n\n}\n\nint dev_mpmc_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len)\n{\n    struct mpmc_data *d;\n\n    /* allocate the private data structure */\n    if (!(d = malloc (sizeof (*d)))) {\n        fprintf (stderr, \"MPMC: unable to create device.\\n\");\n        return (-1);\n    }\n\n    memset (d, 0, sizeof (*d));\n    if (!(d->dev = dev_create (name)))\n        goto err_dev_create;\n    d->dev->priv_data = d;\n    d->dev->phys_addr = paddr;\n    d->dev->phys_len = len;\n    d->mpmc_ptr = (m_uint8_t *) (m_iptr_t) (&mpmc_table[0]);\n    d->mpmc_size = len;\n    d->dev->handler = dev_mpmc_access;\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n    vm_bind_device (vm, d->dev);\n    dev_mpmc_init_defaultvalue ();\n    return (0);\n\n  err_dev_create:\n    free (d);\n    return (-1);\n}\n"
  },
  {
    "path": "tools/virtualmips/adm5120/adm5120_dev_pci.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *     \n  * This file is part of the virtualmips distribution. \n  * See LICENSE file for terms of the license. \n  *\n  */\n\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include<sys/types.h>\n#include<sys/stat.h>\n#include<string.h>\n\n#include \"device.h\"\n#include \"memory.h\"\n#include \"adm5120.h\"\n#include \"cpu.h\"\n\nm_uint32_t pci_table[PCI_INDEX_MAX];\n\nstruct pci_data {\n    struct vdevice *dev;\n    m_uint8_t *pci_ptr;\n    m_uint32_t pci_size;\n};\n\nvoid *dev_pci_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t * data,\n    m_uint8_t * has_set_value)\n{\n\n    struct pci_data *d = dev->priv_data;\n\n    if (offset >= d->pci_size) {\n        *data = 0;\n        return NULL;\n    }\n\n    return ((void *) (d->pci_ptr + offset));\n}\n\nvoid dev_pci_init_defaultvalue ()\n{\n\n}\n\nint dev_pci_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len)\n{\n    struct pci_data *d;\n\n    /* allocate the private data structure */\n    if (!(d = malloc (sizeof (*d)))) {\n        fprintf (stderr, \"PCI: unable to create device.\\n\");\n        return (-1);\n    }\n\n    memset (d, 0, sizeof (*d));\n    if (!(d->dev = dev_create (name)))\n        goto err_dev_create;\n    d->dev->priv_data = d;\n    d->dev->phys_addr = paddr;\n    d->dev->phys_len = len;\n    d->pci_ptr = (m_uint8_t *) (m_iptr_t) (&pci_table[0]);\n    d->pci_size = len;\n    d->dev->handler = dev_pci_access;\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n\n    vm_bind_device (vm, d->dev);\n    dev_pci_init_defaultvalue ();\n    return (0);\n\n  err_dev_create:\n    free (d);\n    return (-1);\n}\n"
  },
  {
    "path": "tools/virtualmips/adm5120/adm5120_dev_sw.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include<sys/types.h>\n#include<sys/stat.h>\n#include<string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"adm5120.h\"\n#include \"cpu.h\"\n\nm_uint32_t sw_table[SW_INDEX_MAX];\n\nstruct sw_data {\n    struct vdevice *dev;\n    m_uint8_t *sw_ptr;\n    m_uint32_t sw_size;\n};\nextern int timeout;\nextern m_uint32_t time_reload;\nvoid *dev_sw_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t * data,\n    m_uint8_t * has_set_value)\n{\n    struct sw_data *d = dev->priv_data;\n    if (offset >= d->sw_size) {\n        *data = 0;\n        return NULL;\n    }\n\n    switch (offset) {\n    case Timer_int_REG:\n        if (op_type == MTS_WRITE) {\n            if (*data & SW_TIMER_INT) {\n                timeout = 0;\n            }\n        } else if (op_type == MTS_READ) {\n\n            *data = sw_table[Timer_int_REG / 4] & (~SW_TIMER_INT);\n            *data |= timeout;\n            *has_set_value = TRUE;\n            return NULL;\n        } else\n            assert (0);\n        break;\n    case Timer_REG:\n        if (op_type == MTS_WRITE) {\n\n            time_reload = *data & SW_TIMER_MASK;\n        }\n        break;\n    }\n    return ((void *) (d->sw_ptr + offset));\n}\n\nvoid dev_sw_init_defaultvalue ()\n{\n    sw_table[CODE_REG / 4] = 0x34085120;\n    sw_table[Timer_int_REG / 4] = 0x10000;\n    sw_table[Timer_REG / 4] = 0xffff;\n}\n\nint dev_sw_init (vm_instance_t * vm, char *name, m_pa_t paddr, m_uint32_t len)\n{\n    struct sw_data *d;\n\n    /* allocate the private data structure */\n    if (!(d = malloc (sizeof (*d)))) {\n        fprintf (stderr, \"SW: unable to create device.\\n\");\n        return (-1);\n    }\n\n    memset (d, 0, sizeof (*d));\n    if (!(d->dev = dev_create (name)))\n        goto err_dev_create;\n    d->dev->priv_data = d;\n    d->dev->phys_addr = paddr;\n    d->dev->phys_len = len;\n    d->sw_ptr = (m_uint8_t *) (m_iptr_t) (&sw_table[0]);\n    d->sw_size = len;\n    d->dev->handler = dev_sw_access;\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n\n    vm_bind_device (vm, d->dev);\n    dev_sw_init_defaultvalue ();\n    return (0);\n\n  err_dev_create:\n    free (d);\n    return (-1);\n}\n"
  },
  {
    "path": "tools/virtualmips/adm5120/adm5120_dev_uart.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include<sys/types.h>\n#include<sys/stat.h>\n#include<string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"adm5120.h\"\n#include \"cpu.h\"\n\nm_uint32_t uart_table[2][UART_INDEX_MAX];\n\nstruct uart_data {\n    struct vdevice *dev;\n    m_uint8_t *uart_ptr;\n    m_uint32_t uart_size;\n    vtty_t *vtty[2];\n\n};\n#define ADM5120_UART_IRQ0\t\t1\n#define ADM5120_UART_IRQ1\t\t2\n\nvoid uart_set_interrupt (cpu_mips_t * cpu, int channel)\n{\n    if (channel == 0)\n        cpu->vm->set_irq (cpu->vm, INT_LVL_UART0);\n    else if (channel == 1)\n        cpu->vm->set_irq (cpu->vm, INT_LVL_UART1);\n    return;\n    assert (0);\n}\n\nvoid uart_clear_interrupt (cpu_mips_t * cpu, int channel)\n{\n    if (channel == 0)\n        cpu->vm->clear_irq (cpu->vm, INT_LVL_UART0);\n    else if (channel == 1)\n        cpu->vm->clear_irq (cpu->vm, INT_LVL_UART1);\n    return;\n    assert (0);\n}\n\n/* Console port input */\nstatic void tty_con0_input (vtty_t * vtty)\n{\n\n    uart_table[0][UART_FR_REG / 4] &= ~UART_RX_FIFO_EMPTY;\n    if (vtty_is_full (vtty))\n        uart_table[0][UART_FR_REG / 4] |= UART_RX_FIFO_FULL;\n    if ((uart_table[0][UART_CR_REG / 4] & UART_RX_INT_EN)\n        && (uart_table[0][UART_CR_REG / 4] & UART_PORT_EN)) {\n        uart_table[0][UART_ICR_REG / 4] |= UART_RX_INT;\n        uart_set_interrupt (vtty->vm->boot_cpu, 0);\n    }\n\n}\n\n/* Console port input */\nstatic void tty_con1_input (vtty_t * vtty)\n{\n\n    uart_table[1][UART_FR_REG / 4] &= ~UART_RX_FIFO_EMPTY;\n    if (vtty_is_full (vtty))\n        uart_table[1][UART_FR_REG / 4] |= UART_RX_FIFO_FULL;\n    if ((uart_table[1][UART_CR_REG / 4] & UART_RX_INT_EN)\n        && (uart_table[1][UART_CR_REG / 4] & UART_PORT_EN)) {\n        uart_set_interrupt (vtty->vm->boot_cpu, 1);\n        uart_table[1][UART_ICR_REG / 4] |= UART_RX_INT;\n    }\n\n}\n\nvoid *dev_uart_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type,\n    m_reg_t * data, m_uint8_t * has_set_value, m_uint8_t channel)\n{\n\n    struct uart_data *d = dev->priv_data;\n\n    if (offset >= d->uart_size) {\n        *data = 0;\n        return NULL;\n    }\n    switch (offset) {\n    case (UART_DR_REG):\n        if (!(uart_table[channel][UART_CR_REG / 4] & UART_PORT_EN)) {\n            //uart port is disabled.\n            if (op_type == MTS_READ) {\n                *data = vmtoh32 (0xffffffff);\n            }\n            *has_set_value = TRUE;\n            return NULL;\n        }\n\n        if (op_type == MTS_READ) {\n\n            if (vtty_is_char_avail (d->vtty[channel])) {\n                *data = vtty_get_char (d->vtty[channel]);\n\n                uart_table[channel][UART_RSR_REG / 4] = 0;\n\n            } else\n                *data = vmtoh32 (0xffffffff);\n            if (vtty_is_char_avail (d->vtty[channel])) {\n                uart_table[channel][UART_FR_REG / 4] &= ~UART_RX_FIFO_EMPTY;\n                uart_table[channel][UART_FR_REG / 4] |= UART_RX_FIFO_FULL;\n                if ((uart_table[channel][UART_CR_REG / 4] & UART_RX_INT_EN)\n                    && (uart_table[channel][UART_CR_REG / 4] & UART_PORT_EN)) {\n                    uart_table[channel][UART_ICR_REG / 4] |= UART_RX_INT;\n                    uart_set_interrupt (cpu, channel);\n                }\n\n            } else {\n                uart_table[channel][UART_FR_REG / 4] |= UART_RX_FIFO_EMPTY;\n                uart_table[channel][UART_FR_REG / 4] &= ~UART_RX_FIFO_FULL;\n                if ((uart_table[channel][UART_CR_REG / 4] & UART_RX_INT_EN)\n                    && (uart_table[channel][UART_CR_REG / 4] & UART_PORT_EN)) {\n                    uart_table[channel][UART_ICR_REG / 4] &= ~UART_RX_INT;\n                    uart_clear_interrupt (cpu, channel);\n                }\n\n            }\n\n            *has_set_value = TRUE;\n\n        } else if (op_type == MTS_WRITE) {\n\n            vtty_put_char (d->vtty[channel], (char) *data);\n            *has_set_value = TRUE;\n        } else {\n            assert (0);\n        }\n        return NULL;\n        break;\n    case UART_RSR_REG:\n        if (op_type == MTS_WRITE) {\n            uart_table[channel][UART_RSR_REG / 4] = 0;\n            *has_set_value = TRUE;\n        }\n        break;\n    case UART_CR_REG:\n        if (op_type == MTS_WRITE) {\n            //enable UART\n            if ((*data) & UART_PORT_EN) {\n\n                if (*data & UART_TX_INT_EN) {\n                    //START TX\n                    uart_table[channel][UART_ICR_REG / 4] |= UART_TX_INT;\n                    uart_set_interrupt (cpu, channel);\n\n                } else {\n                    //TX interrupt dissabled\n                    uart_table[channel][UART_ICR_REG / 4] &= ~UART_TX_INT;\n                    uart_clear_interrupt (cpu, channel);\n                }\n                if (*data & UART_RX_INT_EN) {\n                    if (vtty_is_char_avail (d->vtty[channel])) {\n                        //set RX interrupt\n                        uart_table[channel][UART_ICR_REG / 4] |= UART_RX_INT;\n                        uart_set_interrupt (cpu, channel);\n                    }\n\n                } else {\n                    //disable RX interrupt\n                    uart_table[channel][UART_ICR_REG / 4] &= ~UART_RX_INT;\n                    uart_clear_interrupt (cpu, channel);\n                }\n            } else {\n                //disable UART\n                //clear rx and tx interrupt\n                uart_table[channel][UART_ICR_REG / 4] &= ~UART_TX_INT;\n                uart_clear_interrupt (cpu, channel);\n                uart_table[channel][UART_ICR_REG / 4] &= ~UART_RX_INT;\n                uart_clear_interrupt (cpu, channel);\n            }\n        }\n\n        break;\n\n    }\n    return ((void *) (d->uart_ptr + offset));\n\n}\n\nvoid dev_uart_init_defaultvalue (int uart_index)\n{\n    uart_table[uart_index][UART_FR_REG / 4] = 0x90;\n    uart_table[uart_index][UART_RSR_REG / 4] = 0;\n\n}\n\nvoid *dev_uart_access0 (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t * data,\n    m_uint8_t * has_set_value)\n{\n    return dev_uart_access (cpu, dev, offset, op_size, op_type, data,\n        has_set_value, 0);\n}\n\nvoid *dev_uart_access1 (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t * data,\n    m_uint8_t * has_set_value)\n{\n    return dev_uart_access (cpu, dev, offset, op_size, op_type, data,\n        has_set_value, 1);\n}\n\nint dev_uart_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len, vtty_t * vtty, int uart_index)\n{\n    struct uart_data *d;\n\n    /* allocate the private data structure */\n    if (!(d = malloc (sizeof (*d)))) {\n        fprintf (stderr, \"UART: unable to create device.\\n\");\n        return (-1);\n    }\n    memset (d, 0, sizeof (*d));\n    if (!(d->dev = dev_create (name)))\n        goto err_dev_create;\n    d->dev->priv_data = d;\n    d->dev->phys_addr = paddr;\n    d->dev->phys_len = len;\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n\n    (*d).vtty[uart_index] = vtty;\n    d->uart_size = len;\n    if (uart_index == 0) {\n        d->dev->handler = dev_uart_access0;\n        (*d).vtty[uart_index]->read_notifier = tty_con0_input;\n\n    } else {\n        d->dev->handler = dev_uart_access1;\n        (*d).vtty[uart_index]->read_notifier = tty_con1_input;\n    }\n\n    d->uart_ptr = (m_uint8_t *) (m_iptr_t) (&uart_table[uart_index]);\n\n    vm_bind_device (vm, d->dev);\n    dev_uart_init_defaultvalue (uart_index);\n    return (0);\n\n  err_dev_create:\n    free (d);\n    return (-1);\n}\n"
  },
  {
    "path": "tools/virtualmips/adm5120/adm5120_host_alarm.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include<sys/types.h>\n#include<sys/stat.h>\n#include<string.h>\n\n#include \"device.h\"\n#include \"adm5120.h\"\n#include \"mips.h\"\n\n#define ADM_FREQ  175000000     /*175MHZ */\n\nint instructions = 0;\nextern m_uint32_t sw_table[SW_INDEX_MAX];\n#define MAX_INSTRUCTIONS  1\nint timeout = 0;\nm_uint32_t time_reload;\nextern m_uint32_t uart_table[2][UART_INDEX_MAX];\nextern cpu_mips_t *current_cpu;\n\nvoid uart_set_interrupt (cpu_mips_t * cpu, int channel);\n/*ADM5120 use host_alarm_handler to process all the things,\nThis method is deprecated.\nJZ4740 uses a timer method, which is more flexible.\nSee jz4740_host_alam.c */\n\nvoid host_alarm_handler (int host_signum)\n{\n\n    m_uint32_t tim;\n    if (unlikely (current_cpu->state != CPU_STATE_RUNNING))\n        return;\n    if ((uart_table[0][UART_CR_REG / 4] & UART_RX_INT_EN)\n        && (uart_table[0][UART_CR_REG / 4] & UART_PORT_EN)) {\n        if (vtty_is_char_avail (current_cpu->vm->vtty_con1)) {\n            uart_set_interrupt (current_cpu, 0);\n            uart_table[0][UART_ICR_REG / 4] |= UART_RX_INT;\n            return;\n        }\n\n    }\n\n    if (uart_table[0][UART_CR_REG / 4] & UART_PORT_EN) {\n\n        if (uart_table[0][UART_CR_REG / 4] & UART_TX_INT_EN) {\n            uart_table[0][UART_ICR_REG / 4] |= UART_TX_INT;\n            uart_set_interrupt (current_cpu, 0);\n            return;\n        }\n\n    }\n\n    /*check count and compare */\n    /*Why 2*1000? CPU is 175MHZ, we assume CPI(cycle per instruction)=2\n     * see arch/mips/adm5120/setup.c for more information\n     * 49 void __init mips_time_init(void)\n     */\n    current_cpu->cp0.reg[MIPS_CP0_COUNT] += ADM_FREQ / (2 * 1000);\n    if (current_cpu->cp0.reg[MIPS_CP0_COMPARE] != 0) {\n        if (current_cpu->cp0.reg[MIPS_CP0_COUNT] >=\n            current_cpu->cp0.reg[MIPS_CP0_COMPARE]) {\n            mips_set_irq (current_cpu, MIPS_TIMER_INTERRUPT);\n            mips_update_irq_flag (current_cpu);\n        }\n    }\n\n    /*Linux kernel does not use this timer. It use mips count */\n    if (sw_table[Timer_REG / 4] & SW_TIMER_EN) {\n        tim = sw_table[Timer_REG / 4] & SW_TIMER_MASK;\n        if (tim == 0) {\n            tim = time_reload;\n            timeout = 1;\n        } else\n            tim -= 0x2000;      /*1ms=2000*640ns.but 2000 is too slow. I set it to 0x2000 */\n        if ((m_int32_t) tim < 0x2000)\n            tim = 0;\n        sw_table[Timer_REG / 4] &= ~SW_TIMER_MASK;\n        sw_table[Timer_REG / 4] += tim;\n\n    }\n\n}\n"
  },
  {
    "path": "tools/virtualmips/bsd_syscalls.h",
    "content": "/*\n * System call switch table.\n */\nstatic const struct {\n    int narg;\n    const char *name;\n} bsd_syscalls[] = {\n\t{ 0, \"#0\"            },     /*   0 = out-of-range */\n\t{ 1, \"exit\",         },\t\t/*   1 = exit */\n\t{ 0, \"fork\",         },\t\t/*   2 = fork */\n\t{ 3, \"read\",         },\t\t/*   3 = read */\n\t{ 3, \"write\",        },\t\t/*   4 = write */\n\t{ 3, \"open\",         },\t\t/*   5 = open */\n\t{ 1, \"close\",        },\t\t/*   6 = close */\n\t{ 4, \"wait4\",        },\t\t/*   7 = wait4 */\n\t{ 0, \"#8\",           },\t\t/*   8 = (old creat) */\n\t{ 2, \"link\",         },\t\t/*   9 = link */\n\t{ 1, \"unlink\",       },\t\t/*  10 = unlink */\n\t{ 2, \"execv\",        },\t\t/*  11 = execv */\n\t{ 1, \"chdir\",        },\t\t/*  12 = chdir */\n\t{ 1, \"fchdir\",       },\t\t/*  13 = fchdir */\n\t{ 3, \"mknod\",        },\t\t/*  14 = mknod */\n\t{ 2, \"chmod\",        },\t\t/*  15 = chmod */\n\t{ 3, \"chown\",        },\t\t/*  16 = chown; now 3 args */\n\t{ 2, \"chflags\",      },\t\t/*  17 = chflags */\n\t{ 2, \"fchflags\",     },     /*  18 = fchflags */\n\t{ 4, \"lseek\",        },\t\t/*  19 = lseek */\n\t{ 0, \"getpid\",       },\t\t/*  20 = getpid */\n\t{ 3, \"mount\",        },\t\t/*  21 = mount */\n\t{ 1, \"umount\",       },\t\t/*  22 = umount */\n\t{ 6, \"__sysctl\",     },     /*  23 = __sysctl */\n\t{ 0, \"getuid\",       },\t\t/*  24 = getuid */\n\t{ 0, \"geteuid\",      },\t\t/*  25 = geteuid */\n\t{ 4, \"ptrace\",       },\t\t/*  26 = ptrace */\n\t{ 0, \"getppid\",      },\t\t/*  27 = getppid */\n\t{ 2, \"statfs\",       },\t\t/*  28 = statfs */\n\t{ 2, \"fstatfs\",      },\t\t/*  29 = fstatfs */\n\t{ 3, \"getfsstat\",    },     /*  30 = getfsstat */\n\t{ 4, \"sigaction\",    },     /*  31 = sigaction */\n\t{ 3, \"sigprocmask\",  },     /*  32 = sigprocmask */\n\t{ 2, \"access\",       },\t\t/*  33 = access */\n\t{ 1, \"sigpending\",   },     /*  34 = sigpending */\n\t{ 2, \"sigaltstack\",  },     /*  35 = sigaltstack */\n\t{ 0, \"sync\",         },\t\t/*  36 = sync */\n\t{ 2, \"kill\",         },\t\t/*  37 = kill */\n\t{ 2, \"stat\",         },\t\t/*  38 = stat */\n\t{ 2, \"getlogin\",     },\t\t/*  39 = getlogin */\n\t{ 2, \"lstat\",        },\t\t/*  40 = lstat */\n\t{ 1, \"dup\",          },     /*  41 = dup */\n\t{ 0, \"pipe\",         },\t\t/*  42 = pipe */\n\t{ 1, \"setlogin\",     },\t\t/*  43 = setlogin */\n\t{ 4, \"profil\",       },\t\t/*  44 = profil */\n\t{ 1, \"setuid\",       },\t\t/*  45 = setuid */\n\t{ 1, \"seteuid\",      },\t\t/*  46 = seteuid */\n\t{ 0, \"getgid\",       },\t\t/*  47 = getgid */\n\t{ 0, \"getegid\",      },\t\t/*  48 = getegid */\n\t{ 1, \"setgid\",       },\t\t/*  49 = setgid */\n\t{ 1, \"setegid\",      },\t\t/*  50 = setegid */\n\t{ 0, \"#51\",          },\t\t/*  51 = unused */\n\t{ 3, \"phys\",         },\t\t/*  52 = (2.9) set phys addr */\n\t{ 1, \"lock\",         },\t\t/*  53 = (2.9) lock in core */\n\t{ 4, \"ioctl\",        },\t\t/*  54 = ioctl */\n\t{ 1, \"reboot\",       },\t\t/*  55 = reboot */\n\t{ 2, \"sigwait\",      },\t\t/*  56 = sigwait */\n\t{ 2, \"symlink\",      },\t\t/*  57 = symlink */\n\t{ 3, \"readlink\",     },     /*  58 = readlink */\n\t{ 3, \"execve\",       },\t\t/*  59 = execve */\n\t{ 1, \"umask\",        },\t\t/*  60 = umask */\n\t{ 1, \"chroot\",       },\t\t/*  61 = chroot */\n\t{ 2, \"fstat\",        },\t\t/*  62 = fstat */\n\t{ 0, \"#63\",          },\t\t/*  63 = reserved */\n\t{ 0, \"#64\",          },\t\t/*  64 = (old getpagesize) */\n\t{ 6, \"pselect\",      },\t\t/*  65 = pselect */\n\t{ 0, \"vfork\",        },\t\t/*  66 = vfork */\n\t{ 0, \"#67\",          },\t\t/*  67 = unused */\n\t{ 0, \"#68\",          },\t\t/*  68 = unused */\n\t{ 1, \"brk\",          },\t\t/*  69 = brk */\n\t{ 0, \"#70\",          },\t\t/*  70 = unused */\n\t{ 0, \"#71\",          },\t\t/*  71 = unused */\n\t{ 0, \"#72\",          },\t\t/*  72 = unused */\n\t{ 0, \"#73\",          },\t\t/*  73 = unused */\n\t{ 0, \"#74\",          },\t\t/*  74 = unused */\n\t{ 0, \"#75\",          },\t\t/*  75 = unused */\n\t{ 0, \"vhangup\",      },\t\t/*  76 = vhangup */\n\t{ 0, \"#77\",          },\t\t/*  77 = unused */\n\t{ 0, \"#78\",          },\t\t/*  78 = unused */\n\t{ 2, \"getgroups\",    },     /*  79 = getgroups */\n\t{ 2, \"setgroups\",    },     /*  80 = setgroups */\n\t{ 1, \"getpgrp\",      },\t\t/*  81 = getpgrp */\n\t{ 2, \"setpgrp\",      },\t\t/*  82 = setpgrp */\n\t{ 3, \"setitimer\",    },     /*  83 = setitimer */\n\t{ 0, \"old wait\",     },\t\t/*  84 = (old wait,wait3) */\n\t{ 0, \"#85\",          },\t\t/*  85 = unused */\n\t{ 2, \"getitimer\",    },     /*  86 = getitimer */\n\t{ 0, \"#87\",          },\t\t/*  87 = (old gethostname) */\n\t{ 0, \"#88\",          },\t\t/*  88 = (old sethostname) */\n\t{ 0, \"getdtablesize\",},     /*  89 = getdtablesize */\n\t{ 2, \"dup2\",         },\t\t/*  90 = dup2 */\n\t{ 0, \"#91\",          },\t\t/*  91 = unused */\n\t{ 3, \"fcntl\",        },\t\t/*  92 = fcntl */\n\t{ 5, \"select\",       },\t\t/*  93 = select */\n\t{ 0, \"#94\",          },\t\t/*  94 = unused */\n\t{ 1, \"fsync\",        },\t\t/*  95 = fsync */\n\t{ 3, \"setpriority\",  },     /*  96 = setpriority */\n\t{ 3, \"socket\",       },     /*  97 = socket */\n\t{ 3, \"connect\",      },     /*  98 = connect */\n\t{ 3, \"accept\",       },     /*  99 = accept */\n\t{ 2, \"getpriority\",  },     /* 100 = getpriority */\n\t{ 4, \"send\",         },     /* 101 = send */\n\t{ 4, \"recv\",         },     /* 102 = recv */\n\t{ 1, \"sigreturn\",    },     /* 103 = sigreturn */\n\t{ 3, \"bind\",         },     /* 104 = bind */\n\t{ 5, \"setsockopt\",   },     /* 105 = setsockopt */\n\t{ 2, \"listen\",       },     /* 106 = listen */\n\t{ 1, \"sigsuspend\",   },     /* 107 = sigsuspend */\n\t{ 0, \"#108\",         },\t\t/* 108 = (old sigvec) */\n\t{ 0, \"#109\",         },\t\t/* 109 = (old sigblock) */\n\t{ 0, \"#110\",         },\t\t/* 110 = (old sigsetmask) */\n\t{ 0, \"#111\",         },\t\t/* 111 = (old sigpause)  */\n\t{ 2, \"sigstack\",     },     /* 112 = sigstack COMPAT-43 */\n\t{ 3, \"recvmsg\",      },     /* 113 = recvmsg */\n\t{ 3, \"sendmsg\",      },     /* 114 = sendmsg */\n\t{ 0, \"#115\",         },\t\t/* 115 = unused */\n\t{ 2, \"gettimeofday\", },     /* 116 = gettimeofday */\n\t{ 2, \"getrusage\",    },     /* 117 = getrusage */\n\t{ 5, \"getsockopt\",   },     /* 118 = getsockopt */\n\t{ 0, \"#119\",         },\t\t/* 119 = unused */\n\t{ 3, \"readv\",        },\t\t/* 120 = readv */\n\t{ 3, \"writev\",       },\t\t/* 121 = writev */\n\t{ 2, \"settimeofday\", },     /* 122 = settimeofday */\n\t{ 3, \"fchown\",       },\t\t/* 123 = fchown */\n\t{ 2, \"fchmod\",       },\t\t/* 124 = fchmod */\n\t{ 6, \"recvfrom\",     },     /* 125 = recvfrom */\n\t{ 0, \"#126\",         },\t\t/* 126 = (old setreuid) */\n\t{ 0, \"#127\",         },\t\t/* 127 = (old setregid) */\n\t{ 2, \"rename\",       },\t\t/* 128 = rename */\n\t{ 3, \"truncate\",     },     /* 129 = truncate */\n\t{ 3, \"ftruncate\",    },     /* 130 = ftruncate */\n\t{ 2, \"flock\",        },\t\t/* 131 = flock */\n\t{ 0, \"#132\",         },\t\t/* 132 = nosys */\n\t{ 6, \"sendto\",       },     /* 133 = sendto */\n\t{ 2, \"shutdown\",     },     /* 134 = shutdown */\n\t{ 4, \"socketpair\",   },     /* 135 = socketpair */\n\t{ 2, \"mkdir\",        },\t\t/* 136 = mkdir */\n\t{ 1, \"rmdir\",        },\t\t/* 137 = rmdir */\n\t{ 2, \"utimes\",       },\t\t/* 138 = utimes */\n\t{ 0, \"#139\",         },\t\t/* 139 = unused */\n\t{ 2, \"adjtime\",      },\t\t/* 140 = adjtime */\n\t{ 3, \"getpeername\",  },     /* 141 = getpeername */\n\t{ 0, \"#142\",         },\t\t/* 142 = (old gethostid) */\n\t{ 0, \"#143\",         },\t\t/* 143 = (old sethostid) */\n\t{ 2, \"getrlimit\",    },     /* 144 = getrlimit */\n\t{ 2, \"setrlimit\",    },     /* 145 = setrlimit */\n\t{ 2, \"killpg\",       },\t\t/* 146 = killpg */\n\t{ 0, \"#147\",         },\t\t/* 147 = nosys */\n\t{ 2, \"setquota\",     },\t\t/* 148 = quota */\n\t{ 4, \"quota\",        },\t\t/* 149 = qquota */\n\t{ 3, \"getsockname\",  },     /* 150 = getsockname */\n\t{ 0, \"#151\",         },\t\t/* 151 = unused */\n\t{ 0, \"nostk\",        },\t\t/* 152 = nostk */\n\t{ 1, \"fetchi\",       },\t\t/* 153 = fetchi */\n\t{ 4, \"ucall\",        },\t\t/* 154 = ucall */\n\t{ 0, \"fperr\",        },\t\t/* 155 = fperr */\n};\n"
  },
  {
    "path": "tools/virtualmips/config.c",
    "content": "/*\n * Parsing INI-style configuration files. The routines are taken and\n * modified from SMB source code (http://samba.anu.edu.au/cifs).\n *\n * Copyright (C) 2009-2012 Serge Vakulenko <serge@vak.ru>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n *   1. Redistributions of source code must retain the above copyright notice,\n *      this list of conditions and the following disclaimer.\n *   2. Redistributions in binary form must reproduce the above copyright\n *      notice, this list of conditions and the following disclaimer in the\n *      documentation and/or other materials provided with the distribution.\n *   3. The name of the author may not be used to endorse or promote products\n *      derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED\n * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO\n * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF\n * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include <stdlib.h>\n#include <stdio.h>\n#include <string.h>\n#include <ctype.h>\n#include \"config.h\"\n\nstatic const char *confname;\nstatic char *bufr;\nstatic int bsize;\nstatic char *cursec;\n\n/*\n * Scan to the end of a comment.\n */\nstatic int eat_comment (FILE *fp)\n{\n    int c;\n\n    c = getc (fp);\n    while (c > 0 && c != '\\n')\n        c = getc (fp);\n    return c;\n}\n\n/*\n * Skip whitespaces to end of line.\n */\nstatic int eat_whitespace (FILE *fp)\n{\n    int c;\n\n    c = getc (fp);\n    while (isspace(c) && c != '\\n')\n        c = getc (fp);\n    return c;\n}\n\n/*\n * Search for continuation backshash, starting from line end,\n * When found, return it's index.\n * When no continuation, return -1.\n */\nstatic int find_continuation (char *line, int pos)\n{\n    pos--;\n    while (pos >= 0 && isspace (line [pos]))\n        pos--;\n    if (pos >= 0 && line[pos] == '\\\\')\n        return pos;\n    /* No continuation. */\n    return -1;\n}\n\n/*\n * Scan a parameter name (or name and value pair) and pass the value (or\n * values) to function pfunc().\n */\nstatic void parse_parameter (FILE *fp,\n    void (*pfunc) (void*, char*, char*, char*),\n    void *arg,\n    int c)\n{\n    int i = 0;      /* position withing bufr */\n    int end = 0;        /* bufr[end] is current end-of-string */\n    int vstart = 0;     /* starting position of the parameter */\n\n    /* Loop until we found the start of the value */\n    while (vstart == 0) {\n        /* Ensure there's space for next char */\n        if (i > (bsize-2)) {\n            bsize += 1024;\n            bufr = realloc (bufr, bsize);\n            if (! bufr) {\n                fprintf (stderr, \"%s: malloc failed\\n\", confname);\n                exit (-1);\n            }\n        }\n        switch (c) {\n        case '=':\n            if (end == 0) {\n                fprintf (stderr, \"%s: invalid parameter name\\n\", confname);\n                exit (-1);\n            }\n            bufr[end++] = '\\0';\n            i = end;\n            vstart = end;\n            bufr[i] = '\\0';\n            break;\n\n        case ';':           /* comment line */\n        case '#':\n            c = eat_comment (fp);\n        case '\\n':\n            i = find_continuation (bufr, i);\n            if (i < 0) {\n                /* End of line, but no assignment symbol. */\n                bufr[end]='\\0';\n                fprintf (stderr, \"%s: bad line, ignored: `%s'\\n\",\n                    confname, bufr);\n                return;\n            }\n            end = ((i > 0) && (bufr[i-1] == ' ')) ? (i-1) : (i);\n            c = getc (fp);\n            break;\n\n        case '\\0':\n        case EOF:\n            bufr[i] = '\\0';\n            fprintf (stderr, \"%s: unexpected end-of-file at %s: func\\n\",\n                confname, bufr);\n            exit (-1);\n\n        default:\n            if (isspace (c)) {\n                bufr[end] = ' ';\n                i = end + 1;\n                c = eat_whitespace (fp);\n            } else {\n                bufr[i++] = c;\n                end = i;\n                c = getc (fp);\n            }\n            break;\n        }\n    }\n\n    /* Now parse the value */\n    c = eat_whitespace (fp);\n    while (c > 0) {\n        if (i > (bsize-2)) {\n            bsize += 1024;\n            bufr = realloc (bufr, bsize);\n            if (! bufr) {\n                fprintf (stderr, \"%s: malloc failed\\n\", confname);\n                exit (-1);\n            }\n        }\n        switch(c) {\n        case '\\r':\n            c = getc (fp);\n            break;\n\n        case ';':           /* comment line */\n        case '#':\n            c = eat_comment (fp);\n        case '\\n':\n            i = find_continuation (bufr, i);\n            if (i < 0)\n                c = 0;\n            else {\n                for (end=i; (end >= 0) && isspace (bufr[end]); end--)\n                    ;\n                c = getc (fp);\n            }\n            break;\n\n        default:\n            bufr[i++] = c;\n            if (! isspace (c))\n                end = i;\n            c = getc (fp);\n            break;\n        }\n    }\n    bufr[end] = '\\0';\n    pfunc (arg, cursec, bufr, &bufr [vstart]);\n}\n\n/*\n * Scan a section name and remember it in `cursec'.\n */\nstatic void parse_section (FILE *fp)\n{\n    int c, i, end;\n\n    /* We've already got the '['. Scan past initial white space. */\n    c = eat_whitespace (fp);\n    i = 0;\n    end = 0;\n    while (c > 0) {\n        if (i > (bsize-2)) {\n            bsize += 1024;\n            bufr = realloc (bufr, bsize);\n            if (! bufr) {\n                fprintf (stderr, \"%s: malloc failed\\n\", confname);\n                exit (-1);\n            }\n        }\n        switch (c) {\n        case ']':       /* found the closing bracked */\n            bufr[end] = '\\0';\n            if (end == 0) {\n                fprintf (stderr, \"%s: empty section name\\n\", confname);\n                exit (-1);\n            }\n            /* Register a section. */\n            if (cursec)\n                free (cursec);\n            cursec = strdup (bufr);\n\n            eat_comment (fp);\n            return;\n\n        case '\\n':\n            i = find_continuation (bufr, i);\n            if (i < 0) {\n                bufr [end] = 0;\n                fprintf (stderr, \"%s: invalid line: '%s'\\n\",\n                    confname, bufr);\n                exit (-1);\n            }\n            end = ((i > 0) && (bufr[i-1] == ' ')) ? (i-1) : (i);\n            c = getc (fp);\n            break;\n\n        default:\n            if (isspace (c)) {\n                bufr[end] = ' ';\n                i = end + 1;\n                c = eat_whitespace (fp);\n            } else {\n                bufr[i++] = c;\n                end = i;\n                c = getc (fp);\n            }\n            break;\n        }\n    }\n}\n\n/*\n * Process the named parameter file\n */\nvoid conf_parse (const char *filename,\n    void (*pfunc) (void*, char*, char*, char*),\n    void *arg)\n{\n    FILE *fp;\n    int c;\n\n    confname = filename;\n    fp = fopen (filename, \"r\");\n    if (! fp) {\n        fprintf (stderr, \"%s: unable to open config file\\n\", filename);\n        exit (-1);\n    }\n    bsize = 1024;\n    bufr = (char*) malloc (bsize);\n    if (! bufr) {\n        fprintf (stderr, \"%s: malloc failed\\n\", confname);\n        fclose (fp);\n        exit (-1);\n    }\n\n    /* Parse file. */\n    c = eat_whitespace (fp);\n    while (c > 0) {\n        switch (c) {\n        case '\\n':          /* blank line */\n            c = eat_whitespace (fp);\n            break;\n        case ';':           /* comment line */\n        case '#':\n            c = eat_comment (fp);\n            break;\n        case '[':           /* section header */\n            parse_section (fp);\n            c = eat_whitespace (fp);\n            break;\n        case '\\\\':          /* bogus backslash */\n            c = eat_whitespace (fp);\n            break;\n        default:            /* parameter line */\n            parse_parameter (fp, pfunc, arg, c);\n            c = eat_whitespace (fp);\n            break;\n        }\n    }\n    fclose (fp);\n    if (cursec) {\n        free (cursec);\n        cursec = 0;\n    }\n    free (bufr);\n    bufr = 0;\n    bsize = 0;\n}\n"
  },
  {
    "path": "tools/virtualmips/config.h",
    "content": "/*\n * Parsing INI-style configuration files. The routines are taken and\n * modified from SMB source code (http://samba.anu.edu.au/cifs).\n *\n * Copyright (C) 2009-2012 Serge Vakulenko <serge@vak.ru>\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n *   1. Redistributions of source code must retain the above copyright notice,\n *      this list of conditions and the following disclaimer.\n *   2. Redistributions in binary form must reproduce the above copyright\n *      notice, this list of conditions and the following disclaimer in the\n *      documentation and/or other materials provided with the distribution.\n *   3. The name of the author may not be used to endorse or promote products\n *      derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED\n * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO\n * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF\n * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\nvoid conf_parse (const char *filename,\n    void (*pfunc) (void*, char*, char*, char*),\n    void *arg);\n"
  },
  {
    "path": "tools/virtualmips/cpu.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  */\n#define _GNU_SOURCE\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <string.h>\n#include <stdarg.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <sys/mman.h>\n#include <fcntl.h>\n#include <pthread.h>\n\n#include \"cpu.h\"\n#include \"mips_memory.h\"\n#include \"device.h\"\n#include \"mips.h\"\n#include \"mips_cp0.h\"\n#include \"mips_exec.h\"\n#include \"vm.h\"\n\n#define LOG_ENABLE 0\n\n/*\n * Log a message for a CPU\n */\nvoid cpu_log (cpu_mips_t * cpu, char *module, char *format, ...)\n{\n#if LOG_ENABLE\n    char buffer[256];\n    va_list ap;\n\n    va_start (ap, format);\n    snprintf (buffer, sizeof (buffer), \"CPU%u: %s\", cpu->id, module);\n    vm_flog (cpu->vm, buffer, format, ap);\n    va_end (ap);\n#endif\n}\n\n/*\n * Start a CPU\n */\nvoid cpu_start (cpu_mips_t * cpu)\n{\n    if (cpu) {\n        cpu->state = CPU_STATE_RUNNING;\n    }\n}\n\n/*\n * Stop a CPU\n */\nvoid cpu_stop (cpu_mips_t * cpu)\n{\n    if (cpu) {\n        cpu_log (cpu, \"CPU_STATE\", \"Halting CPU (old state=%u)...\\n\",\n            cpu->state);\n        cpu->state = CPU_STATE_HALTED;\n    }\n}\n\nvoid cpu_restart (cpu_mips_t * cpu)\n{\n    if (cpu) {\n        cpu_log (cpu, \"CPU_STATE\", \"Restartting CPU (old state=%u)...\\n\",\n            cpu->state);\n        cpu->state = CPU_STATE_RESTARTING;\n    }\n}\n\n/*\n * Create a new CPU\n */\ncpu_mips_t *cpu_create (vm_instance_t * vm, u_int type, u_int id)\n{\n    cpu_mips_t *cpu;\n\n    cpu = malloc (sizeof (*cpu));\n    if (!cpu)\n        return NULL;\n\n    memset (cpu, 0, sizeof (*cpu));\n    cpu->vm = vm;\n    cpu->id = id;\n    cpu->type = type;\n    cpu->state = CPU_STATE_SUSPENDED;\n    cpu->vm = vm;\n    mips_init (cpu);\n    return cpu;\n}\n\n/*\n * Delete a CPU\n */\nvoid cpu_delete (cpu_mips_t * cpu)\n{\n    if (cpu) {\n        /* Stop activity of this CPU */\n        cpu_stop (cpu);\n        pthread_join (cpu->cpu_thread, NULL);\n        mips_delete (cpu);\n        free (cpu);\n    }\n}\n\n/*\n * Find a CPU in a group given its ID\n */\ncpu_mips_t *cpu_group_find_id (cpu_group_t * group, u_int id)\n{\n    cpu_mips_t *cpu;\n\n    if (!group)\n        return NULL;\n\n    for (cpu = group->cpu_list; cpu; cpu = cpu->next)\n        if (cpu->id == id)\n            return cpu;\n\n    return NULL;\n}\n\n/*\n * Find the highest CPU ID in a CPU group\n */\nint cpu_group_find_highest_id (cpu_group_t * group, u_int * highest_id)\n{\n    cpu_mips_t *cpu;\n    u_int max_id = 0;\n\n    if (!group || group->cpu_list)\n        return (-1);\n\n    for (cpu = group->cpu_list; cpu; cpu = cpu->next)\n        if (cpu->id >= max_id)\n            max_id = cpu->id;\n\n    *highest_id = max_id;\n    return (0);\n}\n\n/*\n * Add a CPU in a CPU group\n */\nint cpu_group_add (cpu_group_t * group, cpu_mips_t * cpu)\n{\n    if (!group)\n        return (-1);\n\n    /* check that we don't already have a CPU with this id */\n    if (cpu_group_find_id (group, cpu->id) != NULL) {\n        fprintf (stderr, \"cpu_group_add: CPU%u already present in group.\\n\",\n            cpu->id);\n        return (-1);\n    }\n    cpu->next = group->cpu_list;\n    group->cpu_list = cpu;\n    return (0);\n}\n\n/*\n * Create a new CPU group\n */\ncpu_group_t *cpu_group_create (char *name)\n{\n    cpu_group_t *group;\n\n    if (!(group = malloc (sizeof (*group))))\n        return NULL;\n\n    group->name = name;\n    group->cpu_list = NULL;\n    return group;\n}\n\n/*\n * Delete a CPU group\n */\nvoid cpu_group_delete (cpu_group_t * group)\n{\n    cpu_mips_t *cpu, *next;\n\n    if (group != NULL) {\n        for (cpu = group->cpu_list; cpu; cpu = next) {\n            next = cpu->next;\n            cpu_delete (cpu);\n        }\n        free (group);\n    }\n}\n\n/*\n * Rebuild the MTS subsystem for a CPU group\n */\nint cpu_group_rebuild_mts (cpu_group_t * group)\n{\n    cpu_mips_t *cpu;\n\n    for (cpu = group->cpu_list; cpu; cpu = cpu->next)\n        cpu->mts_rebuild (cpu);\n\n    return (0);\n}\n\n/*\n * Start all CPUs of a CPU group\n */\nvoid cpu_group_start_all_cpu (cpu_group_t * group)\n{\n    cpu_mips_t *cpu;\n\n    for (cpu = group->cpu_list; cpu; cpu = cpu->next)\n        cpu_start (cpu);\n}\n\n/*\n * Stop all CPUs of a CPU group\n */\nvoid cpu_group_stop_all_cpu (cpu_group_t * group)\n{\n    cpu_mips_t *cpu;\n\n    for (cpu = group->cpu_list; cpu; cpu = cpu->next)\n        cpu_stop (cpu);\n}\n\n/*\n * Set a state of all CPUs of a CPU group\n */\nvoid cpu_group_set_state (cpu_group_t * group, u_int state)\n{\n    cpu_mips_t *cpu;\n\n    for (cpu = group->cpu_list; cpu; cpu = cpu->next)\n        cpu->state = state;\n}\n\n/*\n * Returns TRUE if all CPUs in a CPU group are inactive\n */\nstatic int cpu_group_check_activity (cpu_group_t * group)\n{\n    cpu_mips_t *cpu;\n\n    for (cpu = group->cpu_list; cpu; cpu = cpu->next) {\n        if (!cpu->cpu_thread_running)\n            continue;\n        if (cpu->state == CPU_STATE_RUNNING)\n            return (FALSE);\n    }\n    return (TRUE);\n}\n\n/*\n * Synchronize on CPUs (all CPUs must be inactive)\n */\nint cpu_group_sync_state (cpu_group_t * group)\n{\n    m_tmcnt_t t1, t2;\n\n    /* Check that CPU activity is really suspended */\n    t1 = m_gettime ();\n\n    while (!cpu_group_check_activity (group)) {\n        t2 = m_gettime ();\n\n        if (t2 > (t1 + 10000))\n            return (-1);\n\n        usleep (50000);\n    }\n    return (0);\n}\n\n/*\n * Save state of all CPUs\n */\nint cpu_group_save_state (cpu_group_t * group)\n{\n    cpu_mips_t *cpu;\n\n    for (cpu = group->cpu_list; cpu; cpu = cpu->next)\n        cpu->prev_state = cpu->state;\n\n    return (TRUE);\n}\n\n/*\n * Restore state of all CPUs\n */\nint cpu_group_restore_state (cpu_group_t * group)\n{\n    cpu_mips_t *cpu;\n\n    for (cpu = group->cpu_list; cpu; cpu = cpu->next)\n        cpu->state = cpu->prev_state;\n\n    return (TRUE);\n}\n"
  },
  {
    "path": "tools/virtualmips/cpu.h",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#ifndef __CPU_H__\n#define __CPU_H__\n\n#include <pthread.h>\n\n#include \"utils.h\"\n#include \"mips.h\"\n#include \"system.h\"\n\n/* Possible CPU types */\nenum {\n    CPU_TYPE_MIPS64 = 1,\n    CPU_TYPE_MIPS32,\n};\n\n/* Virtual CPU states */\nenum {\n    CPU_STATE_RUNNING = 0,      /*cpu is running */\n    CPU_STATE_HALTED,\n    CPU_STATE_SUSPENDED,        /*CPU is SUSPENDED */\n    CPU_STATE_RESTARTING,       /*cpu is restarting */\n    CPU_STATE_PAUSING,          /*cpu is pausing for timer */\n};\n\n/* CPU group definition */\ntypedef struct cpu_group cpu_group_t;\nstruct cpu_group {\n    char *name;\n    cpu_mips_t *cpu_list;\n    void *priv_data;\n};\n\nvoid cpu_log (cpu_mips_t * cpu, char *module, char *format, ...);\nvoid cpu_start (cpu_mips_t * cpu);\nvoid cpu_stop (cpu_mips_t * cpu);\nvoid cpu_restart (cpu_mips_t * cpu);\ncpu_mips_t *cpu_create (vm_instance_t * vm, u_int type, u_int id);\nvoid cpu_delete (cpu_mips_t * cpu);\ncpu_mips_t *cpu_group_find_id (cpu_group_t * group, u_int id);\nint cpu_group_find_highest_id (cpu_group_t * group, u_int * highest_id);\nint cpu_group_add (cpu_group_t * group, cpu_mips_t * cpu);\ncpu_group_t *cpu_group_create (char *name);\nvoid cpu_group_delete (cpu_group_t * group);\nint cpu_group_rebuild_mts (cpu_group_t * group);\nvoid cpu_group_start_all_cpu (cpu_group_t * group);\nvoid cpu_group_stop_all_cpu (cpu_group_t * group);\nvoid cpu_group_set_state (cpu_group_t * group, u_int state);\nint cpu_group_sync_state (cpu_group_t * group);\nint cpu_group_save_state (cpu_group_t * group);\nint cpu_group_restore_state (cpu_group_t * group);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/crc.c",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2006 Christophe Fillot (cf@utc.fr)\n *\n * CRC functions.\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <string.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <sys/mman.h>\n#include <signal.h>\n#include <fcntl.h>\n#include <assert.h>\n\n#include \"utils.h\"\n#include \"crc.h\"\n\n#define CRC12_POLY  0x0f01\n#define CRC16_POLY  0xa001\n#define CRC32_POLY  0xedb88320L\n\n/* CRC tables */\nm_uint16_t crc12_array[256], crc16_array[256];\nm_uint32_t crc32_array[256];\n\n/* Initialize CRC-12 algorithm */\nstatic void crc12_init (void)\n{\n    m_uint16_t crc, c;\n    int i, j;\n\n    for (i = 0; i < 256; i++) {\n        crc = 0;\n        c = (m_uint16_t) i;\n\n        for (j = 0; j < 8; j++) {\n            if ((crc ^ c) & 0x0001)\n                crc = (crc >> 1) ^ CRC12_POLY;\n            else\n                crc = crc >> 1;\n\n            c = c >> 1;\n        }\n\n        crc12_array[i] = crc;\n    }\n}\n\n/* Initialize CRC-16 algorithm */\nstatic void crc16_init (void)\n{\n    m_uint16_t crc, c;\n    int i, j;\n\n    for (i = 0; i < 256; i++) {\n        crc = 0;\n        c = (m_uint16_t) i;\n\n        for (j = 0; j < 8; j++) {\n            if ((crc ^ c) & 0x0001)\n                crc = (crc >> 1) ^ CRC16_POLY;\n            else\n                crc = crc >> 1;\n\n            c = c >> 1;\n        }\n\n        crc16_array[i] = crc;\n    }\n}\n\n/* Initialize CRC-32 algorithm */\nstatic void crc32_init (void)\n{\n    unsigned long c;\n    int n, k;\n\n    for (n = 0; n < 256; n++) {\n        c = (unsigned long) n;\n        for (k = 0; k < 8; k++) {\n            if (c & 1)\n                c = CRC32_POLY ^ (c >> 1);\n            else\n                c = c >> 1;\n        }\n        crc32_array[n] = c;\n    }\n}\n\n/* Initialize CRC algorithms */\nvoid crc_init (void)\n{\n    crc12_init ();\n    crc16_init ();\n    crc32_init ();\n}\n"
  },
  {
    "path": "tools/virtualmips/crc.h",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2006 Christophe Fillot (cf@utc.fr)\n *\n * CRC functions.\n */\n\n#ifndef __CRC_H__\n#define __CRC_H__\n\n#include <sys/types.h>\n#include \"utils.h\"\n\nextern m_uint16_t crc12_array[], crc16_array[];\nextern m_uint32_t crc32_array[];\n\n/* Compute a CRC-12 hash on a 32-bit integer */\nstatic forced_inline m_uint32_t crc12_hash_u32 (m_uint32_t val)\n{\n    register m_uint32_t crc = 0;\n    register int i;\n\n    for (i = 0; i < 4; i++) {\n        crc = (crc >> 8) ^ crc12_array[(crc ^ val) & 0xff];\n        val >>= 8;\n    }\n\n    return (crc);\n}\n\n/* Compute a CRC-16 hash on a 32-bit integer */\nstatic forced_inline m_uint32_t crc16_hash_u32 (m_uint32_t val)\n{\n    register m_uint32_t crc = 0;\n    register int i;\n\n    for (i = 0; i < 4; i++) {\n        crc = (crc >> 8) ^ crc16_array[(crc ^ val) & 0xff];\n        val >>= 8;\n    }\n\n    return (crc);\n}\n\n/* Compute a CRC-32 on the specified block */\nstatic forced_inline m_uint32_t crc32_compute (m_uint32_t crc_accum,\n    m_uint8_t * ptr, int len)\n{\n    unsigned long c = crc_accum;\n    int n;\n\n    for (n = 0; n < len; n++) {\n        c = crc32_array[(c ^ ptr[n]) & 0xff] ^ (c >> 8);\n    }\n\n    return (~c);\n}\n\n/* Initialize CRC algorithms */\nvoid crc_init (void);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/debug.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n/*\n\tA simple interface for GDB.\n\tBased on SimOS.\n */\n\n#define _GNU_SOURCE\n#include <sys/signal.h>\n#include <sys/socket.h>\n#include <string.h>\n\n#include \"vm.h\"\n#include \"mips.h\"\n#include \"utils.h\"\n#include \"debug.h\"\n\nint forced_inline mips_debug (vm_instance_t * vm, int is_break)\n{\n    Simdebug_result res;\n\n    res = Simdebug_run (vm, is_break ? SIGTRAP : SIGUSR2);\n\n    switch (res) {\n    case SD_CONTINUE:\n        vm->mipsy_break_nexti = MIPS_NOBREAK;\n        vm->mipsy_debug_mode = 1;\n        break;\n    case SD_NEXTI_ANYCPU:\n        vm->mipsy_break_nexti = MIPS_BREAKANYCPU;\n        vm->mipsy_debug_mode = 1;\n        break;\n    default:\n        vm->mipsy_break_nexti = res;\n        vm->mipsy_debug_mode = 1;\n        break;\n    }\n\n    return 0;\n\n}\n\nvoid vm_debug_init (vm_instance_t * vm)\n{\n    struct sockaddr_in sockaddr;\n    int tmp;\n\n    if (vm->gdb_debug != 1)\n        return;\n    vm->mipsy_debug_mode = 1;\n    vm->mipsy_break_nexti = -1;\n    vm->gdb_interact_sock = -1;\n    vm->gdb_debug_from_poll = 0;\n\n    vm->gdb_listen_sock = socket (PF_INET, SOCK_STREAM, 0);\n    if (vm->gdb_listen_sock < 0) {\n        fprintf (stderr, \"Can't open debug socket. Run without gdb debug\\n\");\n        vm->gdb_debug = 0;\n        return;\n    }\n\n    /* Allow rapid reuse of this port. */\n    tmp = 1;\n    if (setsockopt (vm->gdb_listen_sock, SOL_SOCKET, SO_REUSEADDR,\n            (char *) &tmp, sizeof (tmp)) < 0) {\n        printf (\"simdebug setsockopt SO_REUSEADDR\");\n        /* Not fatal */\n    }\n    bzero ((char *) &sockaddr, sizeof (struct sockaddr_in));\n\n    sockaddr.sin_family = PF_INET;\n    sockaddr.sin_port = htons (vm->gdb_port);\n    sockaddr.sin_addr.s_addr = INADDR_ANY;\n\n    while (bind (vm->gdb_listen_sock, (struct sockaddr *) &sockaddr,\n            sizeof (sockaddr)) || listen (vm->gdb_listen_sock, 1)) {\n        vm->gdb_port++;\n        sockaddr.sin_port = htons (vm->gdb_port);\n    }\n\n    vm->breakpoint_head = 0;\n    vm->breakpoint_tail = 0;\n\n}\n"
  },
  {
    "path": "tools/virtualmips/debug.h",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *     \n  * This file is part of the virtualmips distribution. \n  * See LICENSE file for terms of the license. \n  *\n  */\n\n#ifndef __DEBUG_H__\n#define  __DEBUG_H__\n\n#include \"vm.h\"\n\n#define MIPS_NOBREAK      (-2)\n#define MIPS_BREAKANYCPU  (-1)\n\nvoid vm_debug_init (vm_instance_t * vm);\nint mips_debug (vm_instance_t * vm, int is_break);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/dev_cs8900.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n /*\n  * cs8900 net card emulation.\n  * (jz4740 driver).\n  * Only works in linux 2.6.24/2.6.22/2.4.20\n  * uboot can not use it.\n  *\n  * Please use TCP instead of UDP when using NFS.\n  * Throughput is about 50k-100k bytes per second when downloading a file from host using http.\n  * Maybe improved when JIT is implemented in the future.\n  *\n  */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdarg.h>\n#include <unistd.h>\n#include <time.h>\n#include <errno.h>\n#include <assert.h>\n\n#include \"crc.h\"\n#include \"utils.h\"\n#include \"cpu.h\"\n#include \"vm.h\"\n#include \"mips_memory.h\"\n#include \"device.h\"\n#include \"net.h\"\n#include \"net_io.h\"\n#include \"dev_cs8900.h\"\n\n/*#define QUEUE_SIZE  128\n#define PACKET_LEN   1600\nm_uint8_t recv_buffer[QUEUE_SIZE][PACKET_LEN];\nm_uint8_t packet_len[QUEUE_SIZE];\n\nm_uint8_t read_index=0;\nm_uint8_t write_index=0;\n*/\n\n/*00:62:9c:61:cf:16*/\nstatic uint8_t cs8900a_default_mac[6] =\n    { 0x00, 0x62, 0x9c, 0x61, 0xcf, 0x16 };\n\n#define CS8900_DEFAULT_RX_TIMEOUT  40\n#define CS8900_MIN_RX_TIMEOUT  20\n#define CS8900_MAX_RX_TIMEOUT  100\n#define CS8900_RX_TIMEOUT_STEP 5\n\nstatic m_uint32_t cs8900a_rx_timeout = CS8900_DEFAULT_RX_TIMEOUT;\n\n/* Maximum packet size */\n#define CS8900_MAX_PKT_SIZE     1518\n#define CS8900_MIN_PKT_SIZE     8\n#define CS8900_RUN_PKT_SIZE     64\n\n#define CS8900A_PRODUCT_ID  0x630e      /*little endian */\n\n#define PP_RT_DATA0              0x00\n#define PP_RT_DATA1              0x02\n#define PP_TX_CMD              0X04\n#define PP_TX_LEN              0X06\n#define PP_IO_ISQ              0X08\n#define PP_ADDRESS              0x0a    /* PacketPage Pointer Port (Section 4.10.10) */\n#define PP_DATA0                 0x0c   /* PacketPage Data Port (Section 4.10.10) */\n#define PP_DATA1               0X0e\n\n#define PP_ProductID            0x0000  /* Section 4.3.1   Product Identification Code */\n#define PP_ISAIOB \t\t\t\t\t0x0020  /*  IO base address */\n#define PP_IntNum                       0x0022  /* Section 3.2.3   Interrupt Number */\n#define PP_ISASOF\t\t\t\t\t\t 0x0026 /*  ISA DMA offset */\n#define PP_DmaFrameCnt \t\t\t\t0x0028  /*  ISA DMA Frame count */\n#define PP_DmaByteCnt \t\t\t\t\t0x002A  /*  ISA DMA Byte count */\n#define PP_MemBase                      0x002c  /* Section 4.9.2   Memory Base Address Register */\n#define PP_EEPROMCommand        0x0040  /* Section 4.3.11  EEPROM Command */\n#define PP_EEPROMData           0x0042  /* Section 4.3.12  EEPROM Data */\n\n#define PP_RxCFG                        0x0102  /* Section 4.4.6   Receiver Configuration */\n#define PP_RxCTL                        0x0104  /* Section 4.4.8   Receiver Control */\n#define PP_TxCFG                        0x0106  /* Section 4.4.9   Transmit Configuration */\n#define PP_BufCFG                       0x010a  /* Section 4.4.12  Buffer Configuration */\n#define PP_LineCTL                      0x0112  /* Section 4.4.16  Line Control */\n#define PP_SelfCTL                      0x0114  /* Section 4.4.18  Self Control */\n#define PP_BusCTL                       0x0116  /* Section 4.4.20  Bus Control */\n#define PP_TestCTL                      0x0118  /* Section 4.4.22  Test Control */\n#define PP_AutoNegCTL \t\t\t\t0x011C  /*  Auto Negotiation Ctrl */\n#define PP_ISQ                            0x0120        /* Section 4.4.5   Interrupt Status Queue */\n#define PP_RxEvent \t\t\t\t\t\t\t0x0124  /*  Rx Event Register */\n#define PP_TxEvent                      0x0128  /* Section 4.4.10  Transmitter Event */\n#define PP_BufEvent                     0x012c  /* Section 4.4.13  Buffer Event */\n#define PP_RxMISS                       0x0130  /* Section 4.4.14  Receiver Miss Counter */\n#define PP_TxCOL                        0x0132  /* Section 4.4.15  Transmit Collision Counter */\n#define PP_LineST\t\t\t\t\t\t\t 0x0134 /*  Line State Register */\n#define PP_SelfST                       0x0136  /* Section 4.4.19  Self Status */\n#define PP_BusST                        0x0138  /* Section 4.4.21  Bus Status */\n#define PP_TDR \t\t\t\t\t\t\t\t0x013C  /*  Time Domain Reflectometry */\n#define PP_AutoNegST \t\t\t\t0x013E  /*  Auto Neg Status */\n#define PP_TxCMD                        0x0144  /* Section 4.4.11  Transmit Command */\n#define PP_TxLength                     0x0146  /* Section 4.5.2   Transmit Length */\n#define PP_LAF\t\t\t\t\t\t\t\t 0x0150 /*  Hash Table */\n#define PP_IA                           \t 0x0158 /* Section 4.6.2   Individual Address (IEEE Address) */\n\n#define PP_RxStatus                     0x0400  /* Section 4.7.1   Receive Status */\n#define PP_RxLength                     0x0402  /* Section 4.7.1   Receive Length (in bytes) */\n#define PP_RxFrame                      0x0404  /* Section 4.7.2   Receive Frame Location */\n#define PP_TxFrame                      0x0a00  /* Section 4.7.2   Transmit Frame Location */\n\n/* PP_RxCFG */\n#define Skip_1                  0x0040\n#define StreamE                 0x0080\n#define RxOKiE                  0x0100\n#define RxDMAonly               0x0200\n#define AutoRxDMAE              0x0400\n#define BufferCRC               0x0800\n#define CRCerroriE              0x1000\n#define RuntiE                  0x2000\n#define ExtradataiE             0x4000\n\n /* PP_TxCFG */\n#define Loss_of_CRSiE   0x0040\n#define SQErroriE               0x0080\n#define TxOKiE                  0x0100\n#define Out_of_windowiE 0x0200\n#define JabberiE                0x0400\n#define AnycolliE               0x0800\n#define T16colliE               0x8000\n\n/* PP_BufCFG */\n#define SWint_X                 0x0040\n#define RxDMAiE                 0x0080\n#define Rdy4TxiE                0x0100\n#define TxUnderruniE    0x0200\n#define RxMissiE                0x0400\n#define Rx128iE                 0x0800\n#define TxColOvfiE              0x1000\n#define MissOvfloiE             0x2000\n#define RxDestiE                0x8000\n\n /* PP_RxCTL */\n#define IAHashA                 0x0040\n#define PromiscuousA    0x0080\n#define RxOKA                   0x0100\n#define MulticastA              0x0200\n#define IndividualA             0x0400\n#define BroadcastA              0x0800\n#define CRCerrorA               0x1000\n#define RuntA                   0x2000\n#define ExtradataA              0x4000\n\n /* PP_SelfCTL */\n#define RESET                   0x0040\n#define SWSuspend               0x0100\n#define HWSleepE                0x0200\n#define HWStandbyE              0x0400\n#define HC0E                    0x1000\n#define HC1E                    0x2000\n#define HCB0                    0x4000\n#define HCB1                    0x8000\n\n/* PP_LineCTL */\n#define SerRxON                 0x0040\n#define SerTxON                 0x0080\n#define AUIonly                 0x0100\n#define AutoAUI_10BT    0x0200\n#define ModBackoffE             0x0800\n#define PolarityDis             0x1000\n#define L2_partDefDis   0x2000\n#define LoRxSquelch             0x4000\n\n/* PP_TxEvent */\n#define Loss_of_CRS             0x0040\n#define SQEerror                0x0080\n#define TxOK                    0x0100\n#define Out_of_window   0x0200\n#define Jabber                  0x0400\n#define T16coll                 0x8000\n\n#define RxEvent                 0x0004\n#define TxEvent                 0x0008\n#define BufEvent                0x000c\n#define RxMISS                  0x0010\n#define TxCOL                   0x0012\n\n/* PP_BufEvent */\n#define SWint                   0x0040\n#define RxDMAFrame              0x0080\n#define Rdy4Tx                  0x0100\n#define TxUnderrun              0x0200\n#define RxMiss                  0x0400\n#define Rx128                   0x0800\n#define RxDest                  0x8000\n\n /* PP_TxCMD */\n#define After5                  0\n#define After381                1\n#define After1021               2\n#define AfterAll                3\n#define TxStart(x) ((x) << 6)\n\n#define Force                   0x0100\n#define Onecoll                 0x0200\n#define InhibitCRC              0x1000\n#define TxPadDis                0x2000\n\n /* PP_BusST */\n#define TxBidErr                0x0080\n#define Rdy4TxNOW               0x0100\n\nextern cpu_mips_t *current_cpu;\nstatic void dev_cs8900_gen_interrupt (struct cs8900_data *d)\n{\n    vm_instance_t *vm;\n    vm = d->vm;\n\n    /*must check RQ bit in 0x116 */\n    m_uint8_t *ram_base;\n    ram_base = (m_uint8_t *) (&(d->internal_ram[0]));\n    if ((*(m_uint16_t *) (ram_base + PP_BusCTL)) & (0x8000)) {\n        /*generate IRQ */\n        vm->set_irq (vm, d->irq_no);\n    }\n}\n\nstatic void dev_cs8900_init_defaultvalue (struct cs8900_data *d)\n{\n    m_uint8_t *ram_base;\n\n    ram_base = (m_uint8_t *) (&(d->internal_ram[0]));\n\n    *(m_uint32_t *) (ram_base + PP_ProductID) = CS8900A_PRODUCT_ID;\n    *(m_uint16_t *) (ram_base + PP_ISAIOB) = 0x300;\n    *(m_uint16_t *) (ram_base + PP_IntNum) = 0x4;\n    *(m_uint16_t *) (ram_base + PP_IntNum) = 0x4;\n\n    *(m_uint16_t *) (ram_base + PP_RxCFG) = 0x3;\n    *(m_uint16_t *) (ram_base + PP_RxEvent) = 0x4;\n\n    *(m_uint16_t *) (ram_base + PP_RxCTL) = 0x5;\n    *(m_uint16_t *) (ram_base + PP_TxCFG) = 0x7;\n    *(m_uint16_t *) (ram_base + PP_TxEvent) = 0x8;\n    *(m_uint16_t *) (ram_base + 0x108) = 0x9;\n\n    *(m_uint16_t *) (ram_base + PP_BufCFG) = 0xb;\n    *(m_uint16_t *) (ram_base + PP_BufEvent) = 0xc;\n\n    *(m_uint16_t *) (ram_base + PP_RxMISS) = 0x10;\n\n    *(m_uint16_t *) (ram_base + PP_TxCOL) = 0x12;\n    *(m_uint16_t *) (ram_base + PP_LineCTL) = 0x13;\n    *(m_uint16_t *) (ram_base + PP_LineST) = 0x14;\n    *(m_uint16_t *) (ram_base + PP_SelfCTL) = 0x15;\n\n    *(m_uint16_t *) (ram_base + PP_SelfST) = 0x16;\n    *(m_uint16_t *) (ram_base + PP_BusCTL) = 0x17;\n\n    *(m_uint16_t *) (ram_base + PP_BusST) = 0x18;\n    *(m_uint16_t *) (ram_base + PP_TestCTL) = 0x19;\n\n    *(m_uint16_t *) (ram_base + PP_TDR) = 0x1c;\n\n    *(m_uint16_t *) (ram_base + PP_TxCMD) = 0x9;\n\n    *(ram_base + PP_IA) = cs8900a_default_mac[0];\n    *(ram_base + PP_IA + 1) = cs8900a_default_mac[1];\n    *(ram_base + PP_IA + 2) = cs8900a_default_mac[2];\n    *(ram_base + PP_IA + 3) = cs8900a_default_mac[3];\n    *(ram_base + PP_IA + 4) = cs8900a_default_mac[4];\n    *(ram_base + PP_IA + 5) = cs8900a_default_mac[5];\n\n}\n\nstatic void dev_cs8900_reset (cpu_mips_t * cpu, struct vdevice *dev)\n{\n    struct cs8900_data *d = dev->priv_data;\n    memset (d->internal_ram, 0, sizeof (d->internal_ram));\n    dev_cs8900_init_defaultvalue (d);\n}\n\n/* Check if a packet must be delivered to the emulated chip based on length*/\nstatic inline int cs8900_handle_len (struct cs8900_data *d, m_uint8_t * pkt,\n    ssize_t pkt_len)\n{\n    /*we do not check CRC !!!! */\n    if (pkt_len < CS8900_MIN_PKT_SIZE)\n        return FALSE;\n\n    ASSERT ((pkt_len >= CS8900_RUN_PKT_SIZE)\n        && (pkt_len <= CS8900_MAX_PKT_SIZE), \"not valid pktlen 0x%x\\n\",\n        (unsigned) pkt_len);\n    /*64<LEN<1518 */\n\n    return TRUE;\n}\n\n/* Check if a packet must be delivered to the emulated chip */\nstatic inline int cs8900_handle_mac_addr (struct cs8900_data *d,\n    m_uint8_t * pkt)\n{\n    n_eth_hdr_t *hdr = (n_eth_hdr_t *) pkt;\n\n    m_uint8_t *ram_base;\n    ram_base = (m_uint8_t *) (&(d->internal_ram[0]));\n\n    if ((*(m_uint16_t *) (ram_base + PP_RxCTL)) & PromiscuousA) {\n        goto rx_dest_int;\n    }\n    if (eth_addr_is_bcast (&hdr->daddr)) {\n        if ((*(m_uint16_t *) (ram_base + PP_RxCTL)) & BroadcastA) {\n            *(m_uint16_t *) (ram_base + PP_RxEvent) |= BroadcastA;\n            *(m_uint16_t *) (ram_base + PP_RxStatus) |= BroadcastA;\n            goto rx_dest_int;\n        } else\n            return FALSE;\n    }\n    if (eth_addr_is_mcast (&hdr->daddr)) {\n        if ((*(m_uint16_t *) (ram_base + PP_RxCTL)) & MulticastA) {\n            *(m_uint16_t *) (ram_base + PP_RxEvent) |= MulticastA;\n            *(m_uint16_t *) (ram_base + PP_RxStatus) |= MulticastA;\n            goto rx_dest_int;\n        } else\n            return FALSE;\n    }\n\n    if ((*(m_uint16_t *) (ram_base + PP_RxCTL)) & IndividualA) {\n        /* Accept frames directly for us, discard others */\n        if (!memcmp ((ram_base + PP_IA), &hdr->daddr, N_ETH_ALEN)) {\n            *(m_uint16_t *) (ram_base + PP_RxEvent) |= IndividualA;\n            *(m_uint16_t *) (ram_base + PP_RxStatus) |= IndividualA;\n            goto rx_dest_int;\n        } else\n            return FALSE;\n\n    }\n\n  rx_dest_int:\n    return (TRUE);\n}\n\nstatic int dev_cs8900_receive_pkt (struct cs8900_data *d, u_char * pkt,\n    ssize_t pkt_len)\n{\n    m_uint8_t *ram_base;\n    ram_base = (m_uint8_t *) (&(d->internal_ram[0]));\n\n    /* Truncate the packet if it is too big */\n    pkt_len = m_min (pkt_len, CS8900_MAX_PKT_SIZE);\n    /*set RX len */\n    *(m_uint16_t *) (ram_base + PP_RxLength) = pkt_len;\n    /*Rx status has been set */\n    /*just copy frame to internal ram */\n    memcpy (ram_base + PP_RxFrame, pkt, pkt_len);\n    /*generate interrupt */\n\n    *(m_uint16_t *) (ram_base + PP_RxEvent) |= RxOKA;\n    *(m_uint16_t *) (ram_base + PP_RxStatus) |= RxOKA;\n    if ((*(m_uint16_t *) (ram_base + PP_RxCFG)) & RxOKiE) {\n        //*(m_uint16_t*)(ram_base+PP_ISQ) &= ~0x3f;\n        *(m_uint16_t *) (ram_base + PP_ISQ) |= RxEvent;\n        dev_cs8900_gen_interrupt (d);\n    }\n\n    return TRUE;\n\n}\n\nstatic int dev_cs8900_rx (netio_desc_t * nio, u_char * pkt, ssize_t pkt_len,\n    struct cs8900_data *d)\n{\n    m_uint8_t *ram_base;\n    m_uint16_t real_len;\n    int i;\n    m_uint32_t ifcs;\n\n    ram_base = (m_uint8_t *) (&(d->internal_ram[0]));\n\n    if (!((*(m_uint16_t *) (ram_base + PP_LineCTL)) & SerRxON))\n        return FALSE;\n    real_len = pkt_len;\n\n    /*FIXME: yajin\n     * jzdriver discard <64 bytes packet. But arp packet has 40 bytes. Pad it to 64 bytes to meet jz driver's requirement\n     */\n    if (unlikely (pkt_len < 64)) {\n        /*pad to 60 bytes */\n        for (i = pkt_len; i < 60; i++) {\n            *(pkt + i) = 0x0;\n        }\n        /*add crc */\n        ifcs = crc32_compute (0xFFFFFFFF, pkt, 60);\n        *(pkt + 60) = ifcs & 0xff;\n        *(pkt + 61) = (ifcs >> 8) & 0xff;\n        *(pkt + 62) = (ifcs >> 16) & 0xff;\n        *(pkt + 63) = ifcs >> 24;\n        real_len = 64;\n    }\n\n    /*check MAC address */\n    if (!(cs8900_handle_mac_addr (d, pkt)))\n        return FALSE;\n\n    /*check frame len */\n    if (!(cs8900_handle_len (d, pkt, real_len)))\n        return FALSE;\n\n    return (dev_cs8900_receive_pkt (d, pkt, real_len));\n\n}\n\nstatic int dev_cs8900_tx (struct cs8900_data *d)\n{\n\n    m_uint8_t *ram_base;\n    ram_base = (m_uint8_t *) (&(d->internal_ram[0]));\n    m_uint16_t send_len;\n    int i;\n    m_uint32_t ifcs;\n\n    send_len = *(m_uint16_t *) (ram_base + PP_TxLength);\n    /*check if tx is enabled */\n    if ((*(m_uint16_t *) (ram_base + PP_LineCTL)) & SerTxON) {\n        /*pad if len<60 */\n        if (send_len <= (CS8900_RUN_PKT_SIZE - 4)) {\n            if (!((*(m_uint16_t *) (ram_base + PP_TxCMD)) & TxPadDis)) {\n                /*pad to 60 bytes */\n                for (i = send_len; i < 60; i++) {\n                    *(ram_base + PP_TxFrame + i) = 0x0;\n                }\n                send_len = 60;\n                if (!((*(m_uint16_t *) (ram_base + PP_TxCMD)) & InhibitCRC)) {\n                    /*append crc */\n                    ifcs =\n                        crc32_compute (0xFFFFFFFF, ram_base + PP_TxFrame,\n                        send_len);\n                    *(ram_base + PP_TxFrame + send_len) = ifcs & 0xff;\n                    *(ram_base + PP_TxFrame + send_len + 1) =\n                        (ifcs >> 8) & 0xff;\n                    *(ram_base + PP_TxFrame + send_len + 2) =\n                        (ifcs >> 16) & 0xff;\n                    *(ram_base + PP_TxFrame + send_len + 3) = ifcs >> 24;\n                    send_len += 4;\n\n                }\n            }\n        }\n        *(m_uint16_t *) (ram_base + PP_TxLength) = send_len;\n        netio_send (d->nio, ram_base + PP_TxFrame, send_len);\n        *(m_uint16_t *) (ram_base + PP_TxEvent) = TxOK | 0x8;   /*is = not |.  all other bits must be cleared */\n        if ((*(m_uint16_t *) (ram_base + PP_TxCFG)) & TxOKiE) {\n            /*if TXOKIE, generate an interrupt */\n            /*set ISQ (regno=TX Event) */\n            //*(m_uint16_t*)(ram_base+PP_ISQ) &= ~0x3f;\n            *(m_uint16_t *) (ram_base + PP_ISQ) |= TxEvent;\n            dev_cs8900_gen_interrupt (d);\n        }\n\n    }\n\n    return TRUE;\n}\n\n/*\nhow to determinte the timeout value???\n*/\nvoid dev_cs8900_active_timer (struct cs8900_data *d)\n{\n    vp_mod_timer (d->cs8900_timer,\n        vp_get_clock (rt_clock) + cs8900a_rx_timeout);\n}\n\nvoid dev_cs8900_unactive_timer (struct cs8900_data *d)\n{\n    vp_del_timer (d->cs8900_timer);\n}\n\nvoid dev_cs8900_cb (void *opaque)\n{\n    struct cs8900_data *d = opaque;\n\n    int fd;\n    ssize_t pkt_len;\n\n    static m_uint8_t status = 0;\n\n    ASSERT (d->nio != NULL, \"set nio first\\n\");\n\n    if ((fd = netio_get_fd (d->nio)) == -1) {\n        ASSERT (0, \"can not get nio fd. init cs8900 nio first.\\n\");\n    }\n\n    pkt_len = netio_recv (d->nio, d->nio->rx_pkt, sizeof (d->nio->rx_pkt));\n\n    if (pkt_len > 0) {\n        /*rx packet */\n        dev_cs8900_rx (d->nio, d->nio->rx_pkt, pkt_len, d);\n\n        /*Why we need to adjust CS8900_MAX_RX_TIMEOUT? yajin\n         * If CS8900_MAX_RX_TIMEOUT is small, that means rx packets quickly. Tx can not get enough time to tell cpu\n         * that tx ok.\n         * If CS8900_MAX_RX_TIMEOUT is big, that means rx packets slow. This will decrease network throughtput and\n         * some applications will complain about rx timeout.\n         * So I adjut the CS8900_MAX_RX_TIMEOUT dynamicly when receiving a packet .\n         *\n         * Please use TCP protocol instead of UDP when mounting directory using nfs.\n         *\n         */\n        if (cs8900a_rx_timeout >= CS8900_MAX_RX_TIMEOUT)\n            status = 1;\n        else if (cs8900a_rx_timeout <= CS8900_MIN_RX_TIMEOUT)\n            status = 2;\n\n        if (status == 0)\n            cs8900a_rx_timeout -= CS8900_RX_TIMEOUT_STEP;\n        if (status == 1)\n            cs8900a_rx_timeout -= CS8900_RX_TIMEOUT_STEP;\n        else if (status == 2)\n            cs8900a_rx_timeout += CS8900_RX_TIMEOUT_STEP;\n\n    }\n\n    cs8900a_rx_timeout = CS8900_DEFAULT_RX_TIMEOUT;\n    dev_cs8900_active_timer (d);\n\n}\n\nstatic void *dev_cs8900_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type,\n    m_uint32_t * data, m_uint8_t * has_set_value)\n{\n    struct cs8900_data *d = dev->priv_data;\n    void *ret;\n    m_uint8_t *ram_base;\n    m_uint16_t io_address;\n    m_uint16_t isq;\n\n    ram_base = (m_uint8_t *) (&(d->internal_ram[0]));\n\n    if (offset >= d->cs8900_size) {\n        *data = 0;\n        return NULL;\n    }\n#if  VALIDE_CS8900_OPERATION\n    if (op_type == MTS_WRITE) {\n        ASSERT (offset != PP_IO_ISQ,\n            \"Write to read only register in CS8900. offset %x\\n\", offset);\n    } else if (op_type == MTS_READ) {\n        ASSERT (offset != PP_TX_CMD,\n            \"Read write only register in CS8900. offset %x\\n\", offset);\n        ASSERT (offset != PP_TX_LEN,\n            \"Read write only register in CS8900. offset %x\\n\", offset);\n    }\n#endif\n\n    switch (offset) {\n    case PP_RT_DATA0:\n    case PP_RT_DATA0 + 1:\n    case PP_RT_DATA1:\n    case PP_RT_DATA1 + 1:\n        if (op_type == MTS_READ) {\n            ASSERT (d->rx_read_index <\n                (*(m_uint16_t *) (ram_base + PP_RxLength)),\n                \"read out of data rx_read_index %x data len %x \\n\",\n                d->rx_read_index, (*(m_uint16_t *) (ram_base + PP_RxLength)));\n            ret = (void *) (ram_base + PP_RxFrame + d->rx_read_index);\n            d->rx_read_index += op_size;\n                        /****if read all data,set d->rx_read_index=0*/\n            if (d->rx_read_index >= *(m_uint16_t *) (ram_base + PP_RxLength))\n                d->rx_read_index = 0;\n            return ret;\n        } else if (op_type == MTS_WRITE) {\n            ret = (void *) (ram_base + PP_TxFrame + d->tx_send_index);\n            if (op_size == MTS_BYTE)\n                *(m_uint8_t *) ret = *data;\n            if (op_size == MTS_HALF_WORD)\n                *(m_uint16_t *) ret = *data;\n            else\n                *(m_uint32_t *) ret = *data;\n            *has_set_value = TRUE;\n            d->tx_send_index += op_size;\n            /*if write all data into tx buffer, set d->tx_send_index=0 */\n            if (d->tx_send_index >= *(m_uint16_t *) (ram_base + PP_TxLength)) {\n                d->tx_send_index = 0;\n                /*start tx a frame */\n                dev_cs8900_tx (d);\n            }\n            return NULL;\n        }\n        break;\n    case PP_TX_CMD:\n\n        ret = (void *) (ram_base + PP_TxCMD);\n        return ret;\n    case PP_TX_LEN:\n        ret = (void *) (ram_base + PP_TxLength);\n        return ret;\n    case PP_IO_ISQ:\n        ASSERT (0, \"not support PP_IO_ISQ \\n\");\n    case PP_ADDRESS:\n        return (void *) (ram_base + PP_ADDRESS);\n    case PP_DATA0:\n    case PP_DATA1:\n        if (offset == PP_DATA0)\n            ASSERT (op_size == MTS_HALF_WORD,\n                \"op_size must be 2. op_size %x\\n\", op_size);\n        else if (offset == PP_DATA1)\n            ASSERT (0, \"cs8900 only support 16 bit IO operation\");\n        io_address = *(m_uint16_t *) (ram_base + PP_ADDRESS);\n        switch (io_address) {\n        case PP_ProductID:\n            ASSERT (op_type == MTS_READ, \"write to read only register %x\\n\",\n                *(m_uint16_t *) (ram_base + PP_ADDRESS));\n            *data = CS8900A_PRODUCT_ID;\n            *has_set_value = TRUE;\n            return NULL;\n        case PP_ProductID + 2: /*16 bit */\n            *data = 0;\n            *has_set_value = TRUE;\n            return NULL;\n        case PP_ISAIOB:\n        case PP_IntNum:\n            return (void *) (ram_base + io_address);\n        case PP_ISASOF:\n        case PP_DmaFrameCnt:\n        case PP_DmaByteCnt:\n        case PP_MemBase:\n        case PP_EEPROMCommand:\n        case PP_EEPROMData:\n            ASSERT (0, \"Not support yet offset %x \\n\", io_address);\n            break;\n        case PP_RxCFG:\n            if (op_type == MTS_WRITE) {\n                if (*data & Skip_1) {\n                    memset (ram_base + PP_RxFrame, 0x0,\n                        PP_TxFrame - 1 - PP_RxFrame);\n                }\n                *(m_uint16_t *) (ram_base + PP_RxCFG) = *data | 0x3;\n                *has_set_value = TRUE;\n                return NULL;\n            } else              /*read */\n                return (void *) (ram_base + io_address);\n        case PP_RxCTL:\n            if (op_type == MTS_WRITE) {\n                *(m_uint16_t *) (ram_base + PP_RxCTL) = *data | 0x5;\n                *has_set_value = TRUE;\n                if (*data & IAHashA)\n                    ASSERT (0, \"Hash dest address is not support yet \\n\");\n                return NULL;\n            } else\n                return (void *) (ram_base + io_address);\n\n        case PP_TxCFG:\n            if (op_type == MTS_WRITE) {\n                *(m_uint16_t *) (ram_base + PP_TxCFG) = *data | 0x7;\n                *has_set_value = TRUE;\n                return NULL;\n            } else\n                return (void *) (ram_base + io_address);\n        case 0x108:\n            /*read 0x108 actually read 0x144 TXcmd */\n            ASSERT (op_type == MTS_READ,\n                \"CS8900 write to read only register. IO address 0x108 \\n\");\n            return (void *) (ram_base + 0x144);\n        case PP_BufCFG:\n            if (op_type == MTS_WRITE) {\n                if (*data & SWint_X) {\n                    *(m_uint16_t *) (ram_base + PP_BufEvent) |= SWint;\n                    //*(m_uint16_t*)(ram_base+PP_ISQ) &= ~0x3f;\n                    *(m_uint16_t *) (ram_base + PP_ISQ) |= BufEvent;\n                    dev_cs8900_gen_interrupt (d);\n                }\n                if (*data & Rdy4TxiE) {\n                    /*if host set rdy4tx, we are always ready for tx */\n                    *(m_uint16_t *) (ram_base + PP_BufEvent) |= Rdy4Tx;\n                    //*(m_uint16_t*)(ram_base+PP_ISQ) &= ~0x3f;\n                    *(m_uint16_t *) (ram_base + PP_ISQ) |= BufEvent;\n                    dev_cs8900_gen_interrupt (d);\n                }\n                *(m_uint16_t *) (ram_base + PP_BufCFG) = *data | 0xb;\n                *has_set_value = TRUE;\n                return NULL;\n            } else\n                return (void *) (ram_base + io_address);\n\n        case PP_LineCTL:\n            if (op_type == MTS_WRITE) {\n                *(m_uint16_t *) (ram_base + PP_LineCTL) = *data | 0x13;\n                if ((*data & SerRxON) || (*data & SerTxON))\n                    dev_cs8900_active_timer (d);\n                *has_set_value = TRUE;\n                return NULL;\n            } else\n                return (void *) (ram_base + io_address);\n        case PP_SelfCTL:\n            if (op_type == MTS_WRITE) {\n                if (*data & RESET) {\n                    dev_cs8900_reset (cpu, dev);\n                }\n                *(m_uint16_t *) (ram_base + PP_SelfCTL) = *data | 0x15;\n                *has_set_value = TRUE;\n                return NULL;\n            } else\n                return (void *) (ram_base + io_address);\n        case PP_BusCTL:\n            if (op_type == MTS_WRITE) {\n                *(m_uint16_t *) (ram_base + PP_BusCTL) = *data | 0x17;\n                *has_set_value = TRUE;\n                return NULL;\n            } else\n                return (void *) (ram_base + io_address);\n\n        case PP_TestCTL:\n            if (op_type == MTS_WRITE) {\n                *(m_uint16_t *) (ram_base + PP_TestCTL) = *data | 0x19;\n                *has_set_value = TRUE;\n                return NULL;\n            } else\n                return (void *) (ram_base + io_address);\n\n        case PP_ISQ:\n            isq = *(m_uint16_t *) (ram_base + PP_ISQ);\n            if (op_type == MTS_WRITE) {\n                *(m_uint16_t *) (ram_base + PP_ISQ) = 0;\n                *has_set_value = TRUE;\n                return NULL;\n            }\n            /*Readonly? But sometimes, kernel will write to this register. */\n            //ASSERT(op_type == MTS_READ, \"wirte to read only register io_address %x.\", io_address);\n            /*SHOULD be read */\n            if (isq & TxEvent) {\n                *(m_uint16_t *) (ram_base + PP_ISQ) &= ~TxEvent;\n                *(m_uint16_t *) data =\n                    *(m_uint16_t *) (ram_base + PP_TxEvent);\n                *(m_uint16_t *) (ram_base + PP_TxEvent) = 0X8;\n                //return (void*)(ram_base+PP_TxEvent);\n            } else if (isq & RxEvent) {\n                *(m_uint16_t *) (ram_base + PP_ISQ) &= ~RxEvent;\n                *(m_uint16_t *) data =\n                    *(m_uint16_t *) (ram_base + PP_RxEvent);\n                *(m_uint16_t *) (ram_base + PP_RxEvent) = 0X4;\n\n                //return (void*)(ram_base+PP_RxEvent);\n            } else if (isq & BufEvent) {\n                *(m_uint16_t *) (ram_base + PP_ISQ) &= ~BufEvent;\n                *(m_uint16_t *) data =\n                    *(m_uint16_t *) (ram_base + PP_BufEvent);\n                *(m_uint16_t *) (ram_base + PP_BufEvent) = 0Xc;\n\n                //return (void*)(ram_base+PP_BufEvent);\n            }\n\n            else if (isq & RxMISS) {\n                *(m_uint16_t *) (ram_base + PP_ISQ) &= ~RxMISS;\n                *(m_uint16_t *) data = *(m_uint16_t *) (ram_base + PP_RxMISS);\n                *(m_uint16_t *) (ram_base + PP_RxMISS) = 0x10;\n                //return (void*)(ram_base+PP_RxMISS);\n            } else if (isq & TxCOL) {\n                *(m_uint16_t *) (ram_base + PP_ISQ) &= ~TxCOL;\n                *(m_uint16_t *) data = *(m_uint16_t *) (ram_base + PP_TxCOL);\n                *(m_uint16_t *) (ram_base + PP_TxCOL) = 0x12;\n                //return (void*)(ram_base+PP_TxCOL);\n            } else {\n                return (void *) (ram_base + PP_ISQ);\n            }\n            *has_set_value = TRUE;\n            return NULL;\n            break;\n        case PP_RxEvent:\n            /*read rx event will clear it */\n            ASSERT (op_type == MTS_READ,\n                \"CS8900 write to read only register. IO address %x \\n\",\n                io_address);\n            *(m_uint16_t *) data = *(m_uint16_t *) (ram_base + PP_RxEvent);\n            *has_set_value = TRUE;\n            *(m_uint16_t *) (ram_base + PP_RxEvent) = 0X4;\n            return NULL;\n        case PP_TxEvent:\n            /*read tx event will clear it */\n            ASSERT (op_type == MTS_READ,\n                \"CS8900 write to read only register. IO address %x \\n\",\n                io_address);\n            *(m_uint16_t *) data = *(m_uint16_t *) (ram_base + PP_TxEvent);\n            *has_set_value = TRUE;\n            *(m_uint16_t *) (ram_base + PP_TxEvent) = 0X8;\n            return NULL;\n        case PP_BufEvent:\n            /*read BufEvent event will clear it */\n            ASSERT (op_type == MTS_READ,\n                \"CS8900 write to read only register. IO address %x \\n\",\n                io_address);\n            *(m_uint16_t *) data = *(m_uint16_t *) (ram_base + PP_BufEvent);\n            *has_set_value = TRUE;\n            *(m_uint16_t *) (ram_base + PP_BufEvent) = 0Xc;\n            return NULL;\n\n        case PP_RxMISS:\n        case PP_TxCOL:\n        case PP_LineST:\n        case PP_SelfST:\n        case PP_TDR:\n            ASSERT (op_type == MTS_READ,\n                \"CS8900 write to read only register. IO address %x \\n\",\n                io_address);\n            return (void *) (ram_base + io_address);\n        case PP_BusST:\n            *(m_uint16_t *) (ram_base + PP_BusST) |= Rdy4TxNOW;\n            //else\n            //{\n            //      *(m_uint16_t*)(ram_base+PP_BusST) &= ~Rdy4TxNOW;\n            //}\n            return (void *) (ram_base + io_address);\n        case PP_TxCMD:\n            ASSERT (op_type == MTS_WRITE,\n                \"CS8900 read write only register. IO address %x \\n\",\n                PP_TxCMD);\n            *(m_uint16_t *) (ram_base + PP_TxCMD) = *data | 0x9;\n            *has_set_value = TRUE;\n            return NULL;\n\n        case PP_TxLength:\n            ASSERT (op_type == MTS_WRITE,\n                \"CS8900 read write only register. IO address %x \\n\",\n                PP_TxLength);\n            *(m_uint16_t *) (ram_base + PP_TxLength) = *data;\n            *has_set_value = TRUE;\n            if (*(m_uint16_t *) (ram_base + PP_TxLength) > 1518) {\n                *(m_uint16_t *) (ram_base + PP_BusST) |= TxBidErr;\n            } else if (*(m_uint16_t *) (ram_base + PP_TxLength) > 1514) {\n                if (!((*(m_uint16_t *) (ram_base + PP_TxCMD)) & InhibitCRC))\n                    *(m_uint16_t *) (ram_base + PP_BusST) |= TxBidErr;\n                else\n                    *(m_uint16_t *) (ram_base + PP_BusST) &= ~TxBidErr;\n            } else\n                *(m_uint16_t *) (ram_base + PP_BusST) &= ~TxBidErr;\n            return NULL;\n        case PP_LAF:\n        case PP_LAF + 1:\n        case PP_LAF + 2:\n        case PP_LAF + 3:\n        case PP_LAF + 4:\n        case PP_LAF + 5:\n        case PP_LAF + 6:\n        case PP_LAF + 7:\n        case PP_IA:\n        case PP_IA + 1:\n        case PP_IA + 2:\n        case PP_IA + 3:\n        case PP_IA + 4:\n        case PP_IA + 5:\n        case PP_RxStatus:\n        case PP_RxLength:\n            return (void *) (ram_base + io_address);\n\n        default:\n            ASSERT (0, \"error io address %x\\n\", io_address);\n\n        }\n\n    }\n\n    return NULL;\n}\n\nstruct cs8900_data *dev_cs8900_init (vm_instance_t * vm, char *name,\n    m_pa_t phys_addr, m_uint32_t phys_len, int irq)\n{\n    struct cs8900_data *d;\n\n    /* Allocate the private data structure for DEC21140 */\n    if (!(d = malloc (sizeof (*d)))) {\n        fprintf (stderr, \"%s (cs8900_data): out of memory\\n\", name);\n        return NULL;\n    }\n    memset (d, 0, sizeof (*d));\n\n    /* Create the device itself */\n    if (!(d->dev = dev_create (name))) {\n        fprintf (stderr, \"%s (DEC21140): unable to create device.\\n\", name);\n        goto err_dev;\n    }\n    d->irq_no = irq;\n    d->vm = vm;\n    d->dev->priv_data = d;\n    d->dev->phys_addr = phys_addr;\n    d->dev->phys_len = phys_len;\n    d->cs8900_size = phys_len;\n\n    d->dev->handler = dev_cs8900_access;\n    d->dev->reset_handler = dev_cs8900_reset;\n\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n    d->cs8900_timer = vp_new_timer (rt_clock, dev_cs8900_cb, d);\n    vm_bind_device (vm, d->dev);\n    return (d);\n\n  err_dev:\n    free (d);\n    return NULL;\n}\n\nint dev_cs8900_set_nio (struct cs8900_data *d, netio_desc_t * nio)\n{\n\n    /* check that a NIO is not already bound */\n    if (d->nio != NULL)\n        return (-1);\n\n    d->nio = nio;\n\n    return (0);\n}\n"
  },
  {
    "path": "tools/virtualmips/dev_cs8900.h",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#ifndef __DEV_CS8900_H__\n#define __DEV_CS8900_H__\n\n#include \"utils.h\"\n#include \"cpu.h\"\n#include \"vm.h\"\n#include \"mips_memory.h\"\n#include \"device.h\"\n#include \"net.h\"\n#include \"net_io.h\"\n#include \"vp_timer.h\"\n\n#define CS8900_INTERNAL_RAM_SIZE   0x1000       /*4K */\n/* CS8900 Data */\nstruct cs8900_data {\n    char *name;\n    m_uint32_t cs8900_size;\n\n    /* Device information */\n    struct vdevice *dev;\n\n    /* Virtual machine */\n    vm_instance_t *vm;\n\n    /* NetIO descriptor */\n    netio_desc_t *nio;          /*one nio can have multi listener */\n\n    /*internal RAM 4K bytes */\n    m_uint32_t internal_ram[CS8900_INTERNAL_RAM_SIZE / 4];\n    m_uint32_t irq_no;\n\n    m_uint16_t rx_read_index;\n    m_uint16_t tx_send_index;\n\n    vp_timer_t *cs8900_timer;\n\n    //  m_uint8_t want_tx;\n//    m_uint8_t want_rx;\n\n};\n\nint dev_cs8900_set_nio (struct cs8900_data *d, netio_desc_t * nio);\nstruct cs8900_data *dev_cs8900_init (vm_instance_t * vm, char *name,\n    m_pa_t phys_addr, m_uint32_t phys_len, int irq);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/dev_nand_flash_1g.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n/*\n1G bytes nand flash emulation. Samsung K9F8G08 1GB\n1G bytes nand flash are stored in file nandflash8g.0-nandflash8g.8191 (8192 blocks).\nThe flash file only be created when writing to block (copy on write).\nPlease use tool/mknandflash to create init nand file of u-boot image.\n*/\n\n/*\n\nsupported operation:\n  READ\n  Read for copy back\n  Read ID\n  Reset\n  Page program\n  Copy-back\n  Block erase\n  Random data input\n  Random data output\n\n*/\n\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n\n#include <unistd.h>\n#include <string.h>\n#include <sys/stat.h>\n#include <sys/types.h>\n#include <sys/mman.h>\n#include <errno.h>\n#include <fcntl.h>\n#include <dirent.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"dev_nand_flash_1g.h\"\n\nm_uint8_t id_info[5] = { 0xec, 0xd3, 0x51, 0x95, 0x58 };\n\n#define NAND_STATUS_READY       0x40\n#define NAND_STATUS_WP            0x80\n\n/*status ready & not write protected*/\n/*I am always ready. haha. Better than real nand flash :)*/\nm_uint8_t nand_status = NAND_STATUS_READY | NAND_STATUS_WP;\n\n#ifdef CPU_LOG\n#undef CPU_LOG\n#endif\n\n//#define DEBUG_FLASH_ACCESS\n#ifdef DEBUG_FLASH_ACCESS\n#define CPU_LOG(arg1) cpu_log arg1\n#else\n#define CPU_LOG(arg1)\n#endif\n\n/*Create nand flash file. 1 block 1 file.*/\nstatic unsigned char *create_nand_flash_file (m_uint32_t block_no)\n{\n    char file_path[512];\n    char page[NAND_FLASH_1G_PAGE_SIZE];\n    int i, n;\n    int fd;\n    unsigned char *ret;\n\n    /*create nand flash file when writing */\n    snprintf (file_path, sizeof (file_path), \"%s/%s.%d\",\n        NAND_FLASH_1G_FILE_DIR, NAND_FLASH_1G_FILE_PREFIX, block_no);\n    fd = open (file_path, O_RDWR | O_CREAT,\n        S_IREAD | S_IWRITE | S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH);\n    assert (fd >= 0);\n\n    for (i = 0; i < NAND_FLASH_1G_PAGES_PER_BLOCK; i++) {\n        memset (page, 0xff, NAND_FLASH_1G_PAGE_SIZE);\n        n = write (fd, page, NAND_FLASH_1G_PAGE_SIZE);\n        assert (n == NAND_FLASH_1G_PAGE_SIZE);\n    }\n    ret = memzone_map_file (fd, NAND_FLASH_1G_BLOCK_SIZE);\n    assert (ret != NULL);\n    return ret;\n}\n\n/*get the page pointer given row addr and block start address*/\nunsigned char *get_nand_flash_page_ptr (m_uint32_t row_addr,\n    unsigned char *block_start)\n{\n\n    m_uint32_t block_no = row_addr >> NAND_FLASH_1G_BLOCK_PAGE_OFFSET;\n    m_uint32_t page_no = row_addr & NAND_FLASH_1G_BLOCK_PAGE_MASK;\n    assert (block_no < NAND_FLASH_1G_TOTAL_BLOCKS);\n    assert (block_start != NULL);\n    return (block_start + page_no * NAND_FLASH_1G_PAGE_SIZE);\n\n}\n\nstatic void nand_flash_erase_block (unsigned char *block_start)\n{\n    memset (block_start, 0xff, NAND_FLASH_1G_BLOCK_SIZE);\n}\n\n/*write data to nand file (1 page)*/\nstatic void write_nand_flash_page_file (m_uint32_t row_addr,\n    unsigned char *block_start, unsigned char *write_data)\n{\n    unsigned char *page_ptr;\n    int i;\n\n    page_ptr = get_nand_flash_page_ptr (row_addr, block_start);\n    /*we only copy different data into page */\n    for (i = 0; i < NAND_FLASH_1G_PAGE_SIZE; i++) {\n        if (*(write_data + i) == 0XFF)\n            continue;\n        if ((*(page_ptr + i)) != (*(write_data + i))) {\n            *(page_ptr + i) = *(write_data + i);\n        }\n    }\n\n}\n\nchar *state_string[8] = { \"STATE_INIT\",\n    \"STATE_READ_START\",\n    \"STATE_RANDOM_READ_START\",\n    \"STATE_WRITE_START\",\n    \"STATE_RANDOM_WRITE_START\",\n    \"STATE_READ_PAGE_FOR_COPY_WRITE\",\n    \"STATE_COPY_START\",\n    \"STATE_ERASE_START\",\n};\n\nvoid *dev_nand_flash_1g_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type,\n    m_uint32_t * data, m_uint8_t * has_set_value)\n{\n    nand_flash_1g_data_t *d = dev->priv_data;\n    m_uint32_t block_no;\n    void *ret;\n    /*COMMAND PORT */\n    if (offset == NAND_COMMPORT_OFFSET) {\n        /*clear addr offset */\n        d->addr_offset = 0;\n        switch (d->state) {\n        case STATE_INIT:\n            if (((*data) & 0xff) == 0x00)\n                d->state = STATE_READ_START;\n            else if (((*data) & 0xff) == 0x80) {\n                memset (d->write_buffer, 0xff, NAND_FLASH_1G_PAGE_SIZE);\n                d->state = STATE_WRITE_START;\n            } else if (((*data) & 0xff) == 0x05) {\n                assert (d->has_issue_30h == 1);\n                d->state = STATE_RANDOM_READ_START;\n                d->has_issue_30h = 0;\n            } else if (((*data) & 0xff) == 0xFF) {\n                /*reset */\n                d->state = STATE_INIT;\n            } else if (((*data) & 0xff) == 0x90) {\n                /*read ID */\n                d->data_port_ipr = id_info;\n                d->state = STATE_INIT;\n                d->read_offset = 0;\n            } else if (((*data) & 0xff) == 0x60) {\n                /*ERASE */\n                d->state = STATE_ERASE_START;\n                /*erase only need row address. adjust addr_offset */\n                d->addr_offset = 2;\n            } else if (((*data) & 0xff) == 0x70) {\n                /*READ STATUS */\n                d->state = STATE_INIT;\n                d->read_offset = 0;\n                d->data_port_ipr = &nand_status;\n            } else\n                ASSERT (0, \"*data %x\\n\", *data);\n            break;\n\n        case STATE_ERASE_START:\n            if (((*data) & 0xff) == 0xd0) {\n                //erase blcok\n                block_no = (d->row_addr) >> NAND_FLASH_1G_BLOCK_PAGE_OFFSET;\n                if (d->flash_map[block_no] == NULL)\n                    d->flash_map[block_no] =\n                        create_nand_flash_file (block_no);\n                nand_flash_erase_block (d->flash_map[block_no]);\n                d->state = STATE_INIT;\n            } else\n                assert (0);\n            break;\n        case STATE_READ_START:\n            if (((*data) & 0xff) == 0x30) {\n                d->has_issue_30h = 1;\n                d->state = STATE_INIT;\n                block_no = (d->row_addr) >> NAND_FLASH_1G_BLOCK_PAGE_OFFSET;\n                if (d->flash_map[block_no] == NULL) {\n                    CPU_LOG ((cpu, \"\",\n                            \"block_no %x is null. redirect to fake page.\",\n                            block_no));\n                    d->data_port_ipr =\n                        get_nand_flash_page_ptr (d->row_addr, d->fake_block);\n                } else\n                    d->data_port_ipr =\n                        get_nand_flash_page_ptr (d->row_addr,\n                        d->flash_map[block_no]);\n\n                d->read_offset = d->col_addr;\n                CPU_LOG ((cpu, \"\", \"d->read_offset %x d->col_addr %x.\",\n                        d->read_offset, d->col_addr));\n            } else if (((*data) & 0xff) == 0x35) {\n                d->state = STATE_READ_PAGE_FOR_COPY_WRITE;\n                block_no = (d->row_addr) >> NAND_FLASH_1G_BLOCK_PAGE_OFFSET;\n                memset (d->write_buffer, 0xff, NAND_FLASH_1G_PAGE_SIZE);\n            } else if (((*data) & 0xff) == 0xFF) {\n                /*reset */\n                d->state = STATE_INIT;\n\n            } else\n                assert (0);\n            break;\n\n        case STATE_RANDOM_READ_START:\n            if (((*data) & 0xff) == 0xe0) {\n                d->state = STATE_INIT;\n                block_no = (d->row_addr) >> NAND_FLASH_1G_BLOCK_PAGE_OFFSET;\n                if (d->flash_map[block_no] == NULL) {\n                    CPU_LOG ((cpu, \"\",\n                            \"block_no %x is null. redirect to fake page.\",\n                            block_no));\n                    d->data_port_ipr =\n                        get_nand_flash_page_ptr (d->row_addr, d->fake_block);\n                } else\n                    d->data_port_ipr =\n                        get_nand_flash_page_ptr (d->row_addr,\n                        d->flash_map[block_no]);\n                d->read_offset = d->col_addr;\n            } else if (((*data) & 0xff) == 0x05) {\n                d->state = STATE_RANDOM_READ_START;\n            } else\n                assert (0);\n            break;\n\n        case STATE_WRITE_START:\n            if (((*data) & 0xff) == 0x10) {\n                d->state = STATE_INIT;\n                block_no = (d->row_addr) >> NAND_FLASH_1G_BLOCK_PAGE_OFFSET;\n                if (d->flash_map[block_no] == NULL)\n                    d->flash_map[block_no] =\n                        create_nand_flash_file (block_no);\n\n                write_nand_flash_page_file (d->row_addr,\n                    d->flash_map[block_no], d->write_buffer);\n                d->write_offset = 0;\n            } else if (((*data) & 0xff) == 0x85) {\n                d->write_offset = 0;\n                d->state = STATE_RANDOM_WRITE_START;\n            } else\n                assert (0);\n            break;\n\n        case STATE_RANDOM_WRITE_START:\n            if (((*data) & 0xff) == 0x10) {\n                d->state = STATE_INIT;\n                block_no = (d->row_addr) >> NAND_FLASH_1G_BLOCK_PAGE_OFFSET;\n                if (d->flash_map[block_no] == NULL)\n                    d->flash_map[block_no] =\n                        create_nand_flash_file (block_no);\n                write_nand_flash_page_file (d->row_addr,\n                    d->flash_map[block_no], d->write_buffer);\n                d->write_offset = 0;\n            } else if (((*data) & 0xff) == 0x85) {\n                d->write_offset = 0;\n                d->state = STATE_RANDOM_WRITE_START;\n            } else\n                assert (0);\n            break;\n\n        case STATE_READ_PAGE_FOR_COPY_WRITE:\n            if (((*data) & 0xff) == 0x85) {\n                d->write_offset = 0;\n\n                d->state = STATE_COPY_START;\n            } else\n                assert (0);\n            break;\n\n        case STATE_COPY_START:\n            if (((*data) & 0xff) == 0x10) {\n                d->state = STATE_INIT;\n                block_no = (d->row_addr) >> NAND_FLASH_1G_BLOCK_PAGE_OFFSET;\n                if (d->flash_map[block_no] == NULL)\n                    d->flash_map[block_no] =\n                        create_nand_flash_file (block_no);\n                write_nand_flash_page_file (d->row_addr,\n                    d->flash_map[block_no], d->write_buffer);\n                d->write_offset = 0;\n            } else if (((*data) & 0xff) == 0x85) {\n                d->write_offset = 0;\n                d->state = STATE_RANDOM_WRITE_START;\n            } else\n                assert (0);\n            break;\n\n        default:\n            assert (0);\n        }\n\n        CPU_LOG ((cpu, \"\", \" state %s\\n\", state_string[d->state]));\n\n    } else if (offset == NAND_DATAPORT_OFFSET) {\n        *has_set_value = FALSE;\n        if (op_type == MTS_READ) {\n            /*data port */\n            CPU_LOG ((cpu, \"\",\n                    \"pc %x data %x d->read_offset %x d->data_port_ipr %x \\n\",\n                    cpu->pc, *(d->data_port_ipr + d->read_offset),\n                    d->read_offset, d->data_port_ipr));\n            ret = (void *) (d->data_port_ipr + d->read_offset);\n            d->read_offset++;\n            return ret;\n\n        } else if (op_type == MTS_WRITE) {\n            ret = (void *) (d->write_buffer + d->col_addr + d->write_offset);\n            d->write_offset++;\n\n            return ret;\n        }\n        assert (0);\n\n    } else if (offset == NAND_ADDRPORT_OFFSET) {\n        CPU_LOG ((cpu, \"\", \"ADDRESS  pc %x d->addr_offset %x *data %x \\n\",\n                cpu->pc, d->addr_offset, *data));\n        /*ADDRESS PORT */\n        assert (op_type == MTS_WRITE);\n        *has_set_value = TRUE;\n        switch (d->addr_offset) {\n        case 0x0:\n            d->col_addr = (*data) & 0xff;\n            break;\n        case 0x01:\n            d->col_addr += ((*data) & 0xff) << 8;\n            break;\n        case 0x2:\n            d->row_addr = (*data) & 0xff;\n            break;\n        case 0x03:\n            d->row_addr += ((*data) & 0xff) << 8;\n            break;\n        case 0x04:\n            d->row_addr += ((*data) & 0xff) << 16;\n            break;\n        default:\n            assert (0);\n        }\n        CPU_LOG ((cpu, \"\", \"col_addr  %x row_addr %x\\n\", d->col_addr,\n                d->row_addr));\n        d->addr_offset++;\n    }\n\n    *has_set_value = TRUE;\n    return NULL;\n\n}\n\nstatic int load_nand_flash_file (nand_flash_1g_data_t * d)\n{\n    int i, j = 0;\n    struct dirent *ent = NULL;\n    DIR *p_dir;\n    char file_path[512];\n    char *file_name;\n    char block_number[16];\n    int fd;\n    //nand_flash_1g_data_t *d=*nand_flash;\n\n    memset (d->flash_map, 0x0,\n        NAND_FLASH_1G_TOTAL_BLOCKS * sizeof (d->flash_map[0]));\n    p_dir = opendir (NAND_FLASH_1G_FILE_DIR);\n    if (NULL == p_dir) {\n        fprintf (stderr,\n            \"NAND FLASH: Can not open nand flash file directory \\\"%s\\\".\\n\",\n            NAND_FLASH_1G_FILE_DIR);\n        goto err_flash_map_create;\n    }\n    while (NULL != (ent = readdir (p_dir))) {\n        //we only take care file\n        if (ent->d_type == DT_DIR)\n            continue;\n        snprintf (file_path, sizeof (file_path), \"%s/%s\",\n            NAND_FLASH_1G_FILE_DIR, ent->d_name);\n        if (get_file_size (file_path) != NAND_FLASH_1G_BLOCK_SIZE)\n            continue;\n        file_name = strdup (ent->d_name);\n        for (i = strlen (file_name) - 1; i >= 0; i--) {\n            if (file_name[i] == '.')\n                break;\n        }\n        if (i == -1) {\n            //not a valid flash file\n            continue;\n        }\n        file_name[i] = '\\0';\n        if (strcmp (file_name, NAND_FLASH_1G_FILE_PREFIX) != 0) {\n            continue;\n        }\n        free (file_name);\n        file_name = strdup (ent->d_name);\n        //get the block number\n        strncpy (block_number, file_name + i + 1, strlen (file_name) - i - 1);\n        block_number[strlen (file_name) - i - 1] = '\\0';\n        i = atoi (block_number);\n        fd = open (file_path, O_RDWR);\n        if (fd < 0)\n            goto err_open_flash_file;\n        d->flash_map[i] = memzone_map_file (fd, NAND_FLASH_1G_BLOCK_SIZE);\n        if (d->flash_map[i] == NULL)\n            goto err_map_flash_file;\n        close (fd);\n        free (file_name);\n        j++;\n\n    }\n    closedir (p_dir);\n    printf (\"\\nloaded %d nand flash file from directory \\\"%s\\\". \\n\", j,\n        NAND_FLASH_1G_FILE_DIR);\n    return (0);\n  err_map_flash_file:\n    close (fd);\n  err_open_flash_file:\n    free (file_name);\n  err_flash_map_create:\n    return (-1);\n\n}\n\nvoid dev_nand_flash_1g_reset (cpu_mips_t * cpu, struct vdevice *dev)\n{\n    nand_flash_1g_data_t *d = dev->priv_data;\n    memset (d->fake_block, 0xff, NAND_FLASH_1G_BLOCK_SIZE);\n    d->state = STATE_INIT;\n    memset (d->write_buffer, 0xff, NAND_FLASH_1G_PAGE_SIZE);\n\n}\n\nint dev_nand_flash_1g_init (vm_instance_t * vm, char *name, m_pa_t phys_addr,\n    m_uint32_t phys_len, nand_flash_1g_data_t ** nand_flash)\n{\n\n    nand_flash_1g_data_t *d;\n\n    /* allocate the private data structure */\n    if (!(d = malloc (sizeof (*d)))) {\n        fprintf (stderr, \"NAND FLASH: unable to create device.\\n\");\n        return (-1);\n    }\n    memset (d, 0, sizeof (*d));\n\n    /*load all flash data to d->flash_map */\n    if (load_nand_flash_file (d) == -1)\n        return (-1);\n    /*set fake_page\n     * We only create nand flash file when writing to a blcok.\n     * When reading from a block which has not been written, give it the fake_page.\n     */\n    memset (d->fake_block, 0xff, NAND_FLASH_1G_BLOCK_SIZE);\n\n    d->state = STATE_INIT;\n    memset (d->write_buffer, 0xff, NAND_FLASH_1G_PAGE_SIZE);\n\n    if (!(d->dev = dev_create (name)))\n        goto err_dev_create;\n    d->dev->priv_data = d;\n    d->dev->handler = dev_nand_flash_1g_access;\n    d->dev->reset_handler = dev_nand_flash_1g_reset;\n    /*NAND COMMPORT AND DATA PORT ADDRESS */\n    d->dev->phys_addr = phys_addr;\n    d->dev->phys_len = phys_len;\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n    /* Map this device to the VM */\n    vm_bind_device (vm, d->dev);\n\n    *nand_flash = d;\n\n    return (0);\n  err_dev_create:\n    free (d);\n    return (-1);\n}\n"
  },
  {
    "path": "tools/virtualmips/dev_nand_flash_1g.h",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *     \n  * This file is part of the virtualmips distribution. \n  * See LICENSE file for terms of the license. \n  *\n  */\n\n#ifndef __DEV_NAND_FLASH_1G_H__\n#define __DEV_NAND_FLASH_1G_H__\n\n#include \"utils.h\"\n\n#define NAND_FLASH_1G_BLOCK_PAGE_OFFSET  0x6    /*64 page in a blcok */\n#define NAND_FLASH_1G_BLOCK_PAGE_MASK    0x3f\n#define NAND_FLASH_1G_TOTAL_SIZE  0x42000000    /*1G data BYTES +32M bytes SPARE BYTES */\n#define NAND_FLASH_1G_TOTAL_PLANE 4\n#define NAND_FLASH_1G_TOTAL_PAGES 0x80000\n#define NAND_FLASH_1G_TOTAL_BLOCKS 0x2000\n#define NAND_FLASH_1G_PAGES_PER_BLOCK  0x40\n\n#define NAND_FLASH_1G_PAGE_SIZE   0x840 /*2k bytes date size+64 bytes spare size */\n#define NAND_FLASH_1G_SPARE_SIZE  0x40  /*64 bytes */\n#define NAND_FLASH_1G_BLOCK_SIZE  0x21000       /*132k bytes */\n#define NAND_FLASH_1G_PAGE_DATA_SIZE 0x800      /*2k bytes */\n#define NAND_FLASH_1G_BLOCK_DATA_SIZE 0x20000   /*128k bytes */\n\n#define NAND_FLASH_1G_BLOCK_OFFSET(x)    (NAND_FLASH_1G_BLOCK_SIZE*x)\n#define NAND_FLASH_1G_PAGE_OFFSET(x)     (NAND_FLASH_1G_PAGE_SIZE*x)\n\n#define NAND_FLASH_1G_FILE_PREFIX   \t    \"nandflash1GB\"\n#define NAND_FLASH_1G_FILE_DIR                  \"nandflash1GB\"\n\n/*NAND_FLASH_STATE*/\n\n#define STATE_INIT                                   0x0\n#define STATE_READ_START                         0x1\n#define STATE_RANDOM_READ_START         0x2\n#define STATE_WRITE_START                       0x3\n#define STATE_RANDOM_WRITE_START       0x4\n\n#define STATE_READ_PAGE_FOR_COPY_WRITE       0x5\n#define STATE_COPY_START                  0x6\n\n#define STATE_ERASE_START                  0x7\n\n#define NAND_DATAPORT_OFFSET\t0x00000000\n#define NAND_ADDRPORT_OFFSET\t0x00010000\n#define NAND_COMMPORT_OFFSET\t0x00008000\n\n/* nand flash private data */\nstruct nand_flash_1g_data {\n    struct vdevice *dev;\n    int state;\n    unsigned char *flash_map[NAND_FLASH_1G_TOTAL_BLOCKS];\n\n    unsigned char fake_block[NAND_FLASH_1G_BLOCK_SIZE];\n\n    m_uint32_t row_addr;\n    m_uint32_t col_addr;\n\n    unsigned char write_buffer[NAND_FLASH_1G_PAGE_SIZE];        //for copy back\n    m_uint32_t read_offset;\n    m_uint32_t write_offset;\n    m_uint32_t addr_offset;\n    m_uint8_t has_issue_30h;\n    /*for nand flash read */\n    unsigned char *data_port_ipr;\n\n};\ntypedef struct nand_flash_1g_data nand_flash_1g_data_t;\n\nunsigned char *get_nand_flash_page_ptr (m_uint32_t row_addr,\n    unsigned char *block_start);\nint dev_nand_flash_1g_init (vm_instance_t * vm, char *name, m_pa_t phys_addr,\n    m_uint32_t phys_len, nand_flash_1g_data_t ** nand_flash);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/dev_nor_flash_4m.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  */\n\n/*\n4M *byte* FLASH device simulation (device id=22F9h).\nMost important part of flash simulation is CFI interface.\nSee flash datasheet for details.\n */\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n\n#include <unistd.h>\n#include <string.h>\n#include <sys/stat.h>\n#include <sys/types.h>\n#include <sys/mman.h>\n#include <errno.h>\n#include<fcntl.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n\n#define ROM_INIT_STATE              0\n\n/* flash private data */\nstruct flash_data {\n    struct vdevice *dev;\n    m_uint8_t *flash_ptr;\n    m_uint32_t flash_size;\n    m_uint8_t *flash_file_name;\n    m_uint32_t state;\n    int flash_fd;\n};\ntypedef struct flash_data flash_data_t;\n\n#define BPTR(d,offset) (((char *)d->flash_ptr) + offset)\n\nm_uint16_t vendorID = 0x01;     // target is little end   0x0001\nm_uint16_t deviceID = 0x22f9;   // target is little end   0x22F9\nm_uint16_t earse_ready = 0x80;  //  target is little end    0X0080\nm_uint32_t last_offset = 0;\n\nm_uint32_t dump_data;\nm_uint32_t cfi_data[] =\n    { 0x51, 0x52, 0x59, 0x2, 0x0, 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, 0x27, 0x36,\n        0x0, 0x0, 0x4,\n    0x0, 0xa, 0x0, 0x5, 0x0, 0x4, 0x0, 0x16, 0x2, 0x0, 0x0, 0x0, 0x2, 0x7,\n        0x0, 0x20,\n    0x0, 0x3e, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\n        0x0, 0x0,\n    0x50, 0x52, 0x49, 0x31, 0x31, 0x0, 0x2, 0x4, 0x1, 0x4, 0x0, 0x0, 0x0, 0xb5, 0xc5, 0x2,      //02 BOTTOM\n};\n\nstatic void secotor_info (m_uint32_t offset, m_uint32_t * sector_start,\n    m_uint32_t * sector_size)\n{\n    if (offset <= 0x00FFF) {\n        *sector_start = offset & 0xFFFFFE00;\n        *sector_size = 0x2000;\n        return;\n    }\n    *sector_start = offset & (0xffff0000);\n    *sector_size = 0x10000;\n}\n\nvoid *dev_flash_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_uint32_t * data,\n    m_uint8_t * has_set_value)\n{\n    flash_data_t *d = dev->priv_data;\n    m_uint32_t r_offset, sector_size, sector_start;\n    m_uint32_t last_sector_start, last_sector_size;\n\n    if (offset >= d->flash_size) {\n        *data = 0;\n        return NULL;\n    }\n    if (op_type == MTS_READ) {\n        switch (d->state) {\n        case 0:\n            return (BPTR (d, offset));\n        case 99:               /*cfi query */\n            if ((offset >= 0x20) && (offset <= 0x9e)) {\n                *data = (cfi_data[(offset - 0x20) / 2]);        //always littleend\n                *has_set_value = TRUE;\n            } else {\n                d->state = 0;\n                return (BPTR (d, offset));\n            }\n\n            break;\n        case 0x6:\n            d->state = 0;\n            if (offset == 0X0)\n                return &vendorID;\n            if (offset == 0X2)\n                return &deviceID;\n            break;\n        case 10:\n            //last cycle is chip erase or sector erase\n            secotor_info (offset, &sector_start, &sector_size);\n            secotor_info (last_offset, &last_sector_start, &last_sector_size);\n            d->state = 0;\n            if (last_sector_start == sector_start)\n                return &earse_ready;\n            else\n                return (BPTR (d, offset));\n            break;\n\n        default:\n            cpu_log (cpu, dev->name, \"read: unhandled state %d\\n\", d->state);\n        }\n        return NULL;\n    }\n    if (op_type == MTS_WRITE) {\n        r_offset = offset;\n        if ((op_size == MTS_HALF_WORD) && (offset == 0X554))\n            offset = 0X555;\n\n        switch (d->state) {\n        case ROM_INIT_STATE:\n            switch (offset) {\n            case 0xAAA:\n                if (((*data) & 0xff) == 0xAA)\n                    d->state = 1;\n                break;\n            case 0XAA:\n                if (((*data) & 0xff) == 0x98) {\n                    d->state = 99;      //CFI QUERY\n                }\n                break;\n            default:\n                switch ((*data) & 0xff) {\n                case 0xB0:\n                    /* Erase/Program Suspend */\n                    d->state = 0;\n                    break;\n                case 0x30:\n                    /* Erase/Program Resume */\n                    d->state = 0;\n                    break;\n                case 0xF0:\n                case 0xFF:\n                    /*Read/Reset */\n                    d->state = 0;\n                    break;\n                default:\n                    return ((void *) (d->flash_ptr + r_offset));\n                }\n\n            }\n            break;\n\n        case 99:\n            if (((*data & 0xff) == 0xff) || ((*data & 0xff) == 0xf0))\n                d->state = 0;\n            else\n                return ((void *) (d->flash_ptr + r_offset));\n            break;\n        case 1:\n            if ((offset != 0x555) && ((*data & 0xff) != 0x55))\n                d->state = 0;\n            else\n                d->state = 2;\n            break;\n\n        case 2:\n            d->state = 0;\n\n            if (offset == 0xAAA) {\n                switch ((*data) & 0xff) {\n                case 0x80:\n                    d->state = 3;\n                    break;\n                case 0xA0:\n                    /* Byte/Word program */\n                    d->state = 4;\n                    break;\n                case 0x90:\n                    /* Product ID Entry / Status of Block B protection */\n                    d->state = 6;\n                    break;\n                }\n            }\n            break;\n\n        case 3:\n            if ((offset != 0xAAA) && (*data != 0xAA))\n                d->state = 0;\n            else\n                d->state = 8;\n            break;\n\n        case 8:\n            if ((offset != 0x555) && (*data != 0x55))\n                d->state = 0;\n            else\n                d->state = 9;\n            break;\n\n        case 9:\n            d->state = 10;\n            last_offset = r_offset;\n\n            switch ((*data) & 0xff) {\n            case 0x10:\n                /* Chip Erase */\n                memset (BPTR (d, 0), 0, d->dev->phys_len);\n                break;\n\n            case 0x30:\n                /* Sector Erase */\n                secotor_info (r_offset, &sector_start, &sector_size);\n                break;\n\n            }\n            break;\n\n            /* Byte/Word Program */\n        case 4:\n            d->state = 0;\n            return ((void *) (d->flash_ptr + r_offset));\n            break;\n\n        default:\n            cpu_log (cpu, dev->name, \"write: unhandled state %d\\n\", d->state);\n        }\n        return &dump_data;\n    }\n    assert (0);\n}\n\nstatic int dev_flash_load (char *flash_file_name, m_uint32_t flash_len,\n    unsigned char **flash_data_hp, u_int create)\n{\n    int fd;\n    struct stat sb;\n    unsigned char *temp;\n\n    fd = open (flash_file_name, O_RDWR);\n    if ((fd < 0) && (create == 1)) {\n        fprintf (stderr, \"Can not open flash file. name %s\\n\",\n            flash_file_name);\n        fprintf (stderr, \"creating flash file. name %s\\n\", flash_file_name);\n        fd = open (flash_file_name, O_RDWR | O_CREAT,\n            S_IREAD | S_IWRITE | S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH);\n        if (fd < 0) {\n            fprintf (stderr, \"Can not create flash file. name %s\\n\",\n                flash_file_name);\n            return (-1);\n        }\n        temp = malloc (flash_len);\n        assert (temp != NULL);\n        memset (temp, 0xff, flash_len);\n        lseek (fd, 0, SEEK_SET);\n        write (fd, (void *) temp, flash_len);\n        free (temp);\n        fprintf (stderr, \"create flash file success. name %s\\n\",\n            flash_file_name);\n        lseek (fd, 0, SEEK_SET);\n    } else if (fd < 0) {\n        fprintf (stderr, \"%s does not exist and not allowed to create.\\n\",\n            flash_file_name);\n        return (-1);\n    }\n    assert (fd >= 0);\n    fstat (fd, &sb);\n    if (flash_len < sb.st_size) {\n        fprintf (stderr,\n            \"Too large flash file. flash len:%d M, flash file name %s,\"\n            \"flash file legth: %d bytes.\\n\", flash_len, flash_file_name,\n            (int) sb.st_size);\n        return (-1);\n    }\n    *flash_data_hp =\n        mmap (NULL, sb.st_size, PROT_WRITE | PROT_READ, MAP_SHARED, fd, 0);\n    if (*flash_data_hp == MAP_FAILED) {\n        fprintf (stderr, \"errno %d\\n\", errno);\n        fprintf (stderr, \"failed\\n\");\n        return (-1);\n    }\n    return 0;\n}\n\n/* Initialize a NOR Flash zone */\nint dev_nor_flash_4m_init (vm_instance_t * vm, char *name)\n{\n    flash_data_t *d;\n    unsigned char *flash_data_hp;\n\n    /*load rom data */\n    if (dev_flash_load (vm->flash_filename, vm->flash_size * 1048576,\n            &flash_data_hp, 1) < 0)\n        return (-1);\n\n    /* allocate the private data structure */\n    if (!(d = malloc (sizeof (*d)))) {\n        fprintf (stderr, \"FLASH: unable to create device.\\n\");\n        return (-1);\n    }\n\n    memset (d, 0, sizeof (*d));\n    d->flash_ptr = flash_data_hp;\n    d->flash_size = vm->flash_size * 1048576;\n    d->state = ROM_INIT_STATE;\n\n    if (!(d->dev = dev_create (name)))\n        goto err_dev_create;\n    d->dev->priv_data = d;\n    d->dev->phys_addr = vm->flash_address;\n    d->dev->phys_len = vm->flash_size * 1048576;\n    d->dev->handler = dev_flash_access;\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n    /* Map this device to the VM */\n    vm_bind_device (vm, d->dev);\n    return (0);\n  err_dev_create:\n    free (d);\n    return (-1);\n}\n"
  },
  {
    "path": "tools/virtualmips/dev_ram.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include<sys/types.h>\n#include<sys/stat.h>\n#include<string.h>\n\n#include \"vm.h\"\n#include \"mips_memory.h\"\n#include \"device.h\"\n\n/* RAM private data */\nstruct ram_data {\n    struct vdevice *dev;\n};\n\nvoid dev_ram_reset (cpu_mips_t * cpu, struct vdevice *dev)\n{\n    assert (dev->host_addr != 0);\n    /*reset ram */\n    //memset ((unsigned char *) dev->host_addr, 0x0, dev->phys_len);\n\n}\n\n/* Initialize a RAM zone */\nint dev_ram_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len)\n{\n    struct ram_data *d;\n\n    /* allocate the private data structure */\n    if (!(d = malloc (sizeof (*d)))) {\n        fprintf (stderr, \"RAM: unable to create device.\\n\");\n        return (-1);\n    }\n\n    memset (d, 0, sizeof (*d));\n\n    if (!(d->dev = dev_create_ram (vm, name, paddr, len))) {\n        fprintf (stderr, \"RAM: unable to create device.\\n\");\n        goto err_dev_create;\n    }\n    d->dev->priv_data = d;\n    d->dev->reset_handler = dev_ram_reset;\n    return (0);\n\nerr_dev_create:\n    free (d);\n    return (-1);\n}\n"
  },
  {
    "path": "tools/virtualmips/dev_sdcard.c",
    "content": "/*\n * SD/MMC card emulation.\n *\n * Copyright (C) 2011 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n *\n */\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <string.h>\n#include <fcntl.h>\n#include <unistd.h>\n\n#include \"vm.h\"\n#include \"mips_memory.h\"\n#include \"device.h\"\n#include \"dev_sdcard.h\"\n\n//#define TRACE       printf\n#ifndef TRACE\n#define TRACE(...)  /*empty*/\n#endif\n\n/*\n * Definitions for MMC/SDC commands.\n */\n#define CMD_GO_IDLE         (0x40+0)    /* CMD0 */\n#define\tCMD_SEND_OP_SDC     (0x40+41)   /* ACMD41 (SDC) */\n#define CMD_SET_BLEN        (0x40+16)\n#define CMD_SEND_IF_COND    (0x40+8)\n#define CMD_SEND_CSD        (0x40+9)\n#define CMD_STOP            (0x40+12)\n#define CMD_READ_SINGLE     (0x40+17)\n#define CMD_READ_MULTIPLE   (0x40+18)\n#define CMD_SET_WBECNT      (0x40+23)   /* ACMD23 */\n#define CMD_WRITE_SINGLE    (0x40+24)\n#define CMD_WRITE_MULTIPLE  (0x40+25)\n#define CMD_APP             (0x40+55)   /* CMD55 */\n\n#define DATA_START_BLOCK        0xFE    /* start data for single block */\n#define STOP_TRAN_TOKEN         0xFD    /* stop token for write multiple */\n#define WRITE_MULTIPLE_TOKEN    0xFC    /* start data for write multiple */\n\nstatic void sdcard_read_data (int fd, unsigned offset,\n    unsigned char *buf, unsigned blen)\n{\n    /* Fill uninitialized blocks by FF: simulate real flash media. */\n    memset (buf, 0xFF, blen);\n\n    if (lseek (fd, offset, 0) != offset) {\n        printf (\"sdcard: seek failed, offset %#x\\n\", offset);\n        return;\n    }\n    if (read (fd, buf, blen) < 0) {\n        printf (\"sdcard: read failed, offset %#x\\n\", offset);\n        return;\n    }\n}\n\nstatic void sdcard_write_data (int fd, unsigned offset,\n    unsigned char *buf, unsigned blen)\n{\n    if (lseek (fd, offset, 0) != offset) {\n        printf (\"sdcard: seek failed, offset %#x\\n\", offset);\n        return;\n    }\n    if (write (fd, buf, blen) != blen) {\n        printf (\"sdcard: write failed, offset %#x\\n\", offset);\n        return;\n    }\n}\n\nstatic void sdcard_reset (sdcard_t *d)\n{\n    d->select = 0;\n    d->blen = 512;\n    d->count = 0;\n}\n\n/*\n * Reset sdcard.\n */\nvoid dev_sdcard_reset (cpu_mips_t *cpu)\n{\n    pic32_t *pic32 = (pic32_t*) cpu->vm->hw_data;\n\n    sdcard_reset (&pic32->sdcard[0]);\n    sdcard_reset (&pic32->sdcard[1]);\n}\n\n/*\n * Initialize SD card.\n */\nint dev_sdcard_init (sdcard_t *d, char *name, unsigned mbytes, char *filename)\n{\n    memset (d, 0, sizeof (*d));\n    d->name = name;\n    if (mbytes == 0 || ! filename) {\n        /* No SD card installed. */\n        return (0);\n    }\n    d->kbytes = mbytes * 1024;\n    d->fd = open (filename, O_RDWR);\n    if (d->fd < 0) {\n        /* Fatal: no image available. */\n        perror (filename);\n        return (-1);\n    }\n    return (0);\n}\n\nvoid dev_sdcard_select (cpu_mips_t *cpu, int unit, int on)\n{\n    pic32_t *pic32 = (pic32_t*) cpu->vm->hw_data;\n    sdcard_t *d = &pic32->sdcard[unit];\n\n    if (on) {\n        //TRACE (\"sdcard%d: (((\\n\", unit);\n        d->select = 1;\n        d->count = 0;\n    } else {\n        //TRACE (\"sdcard%d: )))\\n\", unit);\n        d->select = 0;\n    }\n}\n\n/*\n * Data i/o: send byte to device.\n * Return received byte.\n */\nunsigned dev_sdcard_io (cpu_mips_t *cpu, unsigned data)\n{\n    pic32_t *pic32 = (pic32_t*) cpu->vm->hw_data;\n    sdcard_t *d = pic32->sdcard[0].select ? &pic32->sdcard[0] :\n                  pic32->sdcard[1].select ? &pic32->sdcard[1] : 0;\n    unsigned reply;\n\n    if (! d || ! d->fd) {\n        //TRACE (\"sdcard: unselected i/o\\n\");\n        return 0xFF;\n    }\n    data = (unsigned char) data;\n    reply = 0xFF;\n    if (d->count == 0) {\n        d->buf[0] = data;\n        if (data != 0xFF)\n            d->count++;\n    } else {\n        switch (d->buf[0]) {\n        case CMD_GO_IDLE:               /* CMD0: reset */\n            if (d->count >= 7)\n                break;\n            d->buf [d->count++] = data;\n            if (d->count == 7)\n                reply = 0x01;\n            break;\n        case CMD_APP:                   /* CMD55: application prefix */\n            if (d->count >= 7)\n                break;\n            d->buf [d->count++] = data;\n            if (d->count == 7) {\n                reply = 0;\n                d->count = 0;\n            }\n            break;\n        case CMD_SEND_OP_SDC:           /* ACMD41: initialization */\n            if (d->count >= 7)\n                break;\n            d->buf [d->count++] = data;\n            if (d->count == 7)\n                reply = 0;\n            break;\n        case CMD_SET_BLEN:              /* Set block length */\n            if (d->count >= 7)\n                break;\n            d->buf [d->count++] = data;\n            if (d->count == 7) {\n                d->blen = d->buf[1] << 24 | d->buf[2] << 16 |\n                    d->buf[3] << 8 | d->buf[4];\n                TRACE (\"sdcard%d: set block length %u bytes\\n\", d->unit, d->blen);\n                reply = (d->blen > 0 && d->blen <= 1024) ? 0 : 4;\n            }\n            break;\n        case CMD_SET_WBECNT:            /* Set write block erase count */\n            if (d->count >= 7)\n                break;\n            d->buf [d->count++] = data;\n            if (d->count == 7) {\n                d->wbecnt = d->buf[1] << 24 | d->buf[2] << 16 |\n                    d->buf[3] << 8 | d->buf[4];\n                TRACE (\"sdcard%d: set write block erase count %u\\n\", d->unit, d->wbecnt);\n                reply = 0;\n                d->count = 0;\n            }\n            break;\n        case CMD_SEND_CSD:              /* Get card data */\n            if (d->count >= 7)\n                break;\n            d->buf [d->count++] = data;\n            if (d->count == 7) {\n                /* Send reply */\n                TRACE (\"sdcard%d: send media size %u sectors\\n\",\n                    d->unit, d->kbytes * 2);\n                reply = 0;\n                d->limit = 16 + 3;\n                d->count = 1;\n                d->buf[0] = 0;\n                d->buf[1] = DATA_START_BLOCK;\n                d->buf[2+0] = 1 << 6;     /* SDC ver 2.00 */\n                d->buf[2+1] = 0;\n                d->buf[2+2] = 0;\n                d->buf[2+3] = 0;\n                d->buf[2+4] = 0;\n                d->buf[2+5] = 0;\n                d->buf[2+6] = 0;\n                d->buf[2+7] = 0;\n                d->buf[2+8] = (d->kbytes / 512 - 1) >> 8;\n                d->buf[2+9] = d->kbytes / 512 - 1;\n                d->buf[2+10] = 0;\n                d->buf[2+11] = 0;\n                d->buf[2+12] = 0;\n                d->buf[2+13] = 0;\n                d->buf[2+14] = 0;\n                d->buf[2+15] = 0;\n                d->buf[d->limit - 1] = 0xFF;\n                d->buf[d->limit] = 0xFF;\n            }\n            break;\n        case CMD_READ_SINGLE:           /* Read block */\n            if (d->count >= 7)\n                break;\n            d->buf [d->count++] = data;\n            if (d->count == 7) {\n                /* Send reply */\n                reply = 0;\n                d->offset = d->buf[1] << 24 | d->buf[2] << 16 |\n                    d->buf[3] << 8 | d->buf[4];\n                TRACE (\"sdcard%d: read offset %#x, length %u kbytes\\n\",\n                    d->unit, d->offset, d->blen);\n                d->limit = d->blen + 3;\n                d->count = 1;\n                d->buf[0] = 0;\n                d->buf[1] = DATA_START_BLOCK;\n                sdcard_read_data (d->fd, d->offset, &d->buf[2], d->blen);\n                d->buf[d->limit - 1] = 0xFF;\n                d->buf[d->limit] = 0xFF;\n            }\n            break;\n        case CMD_READ_MULTIPLE:         /* Read multiple blocks */\n            if (d->count >= 7)\n                break;\n            d->buf [d->count++] = data;\n            if (d->count == 7) {\n                /* Send reply */\n                reply = 0;\n                d->read_multiple = 1;\n                d->offset = d->buf[1] << 24 | d->buf[2] << 16 |\n                    d->buf[3] << 8 | d->buf[4];\n                TRACE (\"sdcard%d: read offset %#x, length %u kbytes\\n\",\n                    d->unit, d->offset, d->blen);\n                d->limit = d->blen + 3;\n                d->count = 1;\n                d->buf[0] = 0;\n                d->buf[1] = DATA_START_BLOCK;\n                sdcard_read_data (d->fd, d->offset, &d->buf[2], d->blen);\n                d->buf[d->limit - 1] = 0xFF;\n                d->buf[d->limit] = 0xFF;\n            }\n            break;\n        case CMD_WRITE_SINGLE:          /* Write block */\n            if (d->count >= sizeof (d->buf))\n                break;\n            d->buf [d->count++] = data;\n            if (d->count == 7) {\n                /* Accept command */\n                reply = 0;\n                d->offset = d->buf[1] << 24 | d->buf[2] << 16 |\n                    d->buf[3] << 8 | d->buf[4];\n                TRACE (\"sdcard%d: write offset %#x\\n\", d->unit, d->offset);\n            } else if (d->count == 7 + d->blen + 2 + 2) {\n                if (d->buf[7] == DATA_START_BLOCK) {\n                    /* Accept data */\n                    reply = 0x05;\n                    d->offset = d->buf[1] << 24 | d->buf[2] << 16 |\n                        d->buf[3] << 8 | d->buf[4];\n                    sdcard_write_data (d->fd, d->offset, &d->buf[8], d->blen);\n                    TRACE (\"sdcard%d: write data, length %u kbytes\\n\", d->unit, d->blen);\n                } else {\n                    /* Reject data */\n                    reply = 4;\n                    TRACE (\"sdcard%d: reject write data, tag=%02x\\n\", d->unit, d->buf[7]);\n                }\n            }\n            break;\n        case CMD_WRITE_MULTIPLE:        /* Write multiple blocks */\n            if (d->count >= 7)\n                break;\n            d->buf [d->count++] = data;\n            if (d->count == 7) {\n                /* Accept command */\n                reply = 0;\n                d->offset = d->buf[1] << 24 | d->buf[2] << 16 |\n                    d->buf[3] << 8 | d->buf[4];\n                TRACE (\"sdcard%d: write multiple offset %#x\\n\", d->unit, d->offset);\n                d->count = 0;\n            }\n            break;\n        case WRITE_MULTIPLE_TOKEN:      /* Data for write-miltiple */\n            if (d->count >= sizeof (d->buf))\n                break;\n            d->buf [d->count++] = data;\n            if (d->count == 2 + d->blen + 2) {\n                /* Accept data */\n                reply = 0x05;\n                sdcard_write_data (d->fd, d->offset, &d->buf[1], d->blen);\n                TRACE (\"sdcard%d: write sector %u, length %u kbytes\\n\",\n                    d->unit, d->offset / 512, d->blen);\n                d->offset += 512;\n                d->count = 0;\n            }\n            break;\n        case CMD_STOP:                  /* Stop read-multiple sequence */\n            if (d->count > 1)\n                break;\n            d->read_multiple = 0;\n            reply = 0;\n            break;\n        case CMD_SEND_IF_COND:          /* Stop read-multiple sequence */\n            if (d->count > 1)\n                break;\n            d->read_multiple = 0;\n            reply = 4;                  /* Unknown command */\n            break;\n        case 0:                         /* Reply */\n            if (d->count <= d->limit) {\n                reply = d->buf [d->count++];\n                break;\n            }\n            if (d->read_multiple) {\n                /* Next read-multiple block. */\n                d->offset += d->blen;\n                d->count = 1;\n                sdcard_read_data (d->fd, d->offset, &d->buf[2], d->blen);\n                reply = 0;\n            }\n            break;\n        default:                        /* Ignore */\n            break;\n        }\n    }\n    //TRACE (\"sdcard%d: send %02x, reply %02x\\n\", d->unit, data, reply);\n    return reply;\n}\n"
  },
  {
    "path": "tools/virtualmips/dev_sdcard.h",
    "content": "/*\n * SecureDigital flash card.\n *\n * Copyright (C) 2011 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#ifndef __DEV_SD__\n#define __DEV_SD__\n\n/* SD card private data */\nstruct sdcard {\n    char *name;                         /* Device name */\n    unsigned kbytes;                    /* Disk size */\n    int unit;                           /* Index (sd0 or sd1) */\n    int fd;                             /* Image file */\n    int select;                         /* Selected */\n    int read_multiple;                  /* Read-multiple mode */\n    unsigned blen;                      /* Block length */\n    unsigned wbecnt;                    /* Write block erase count */\n    unsigned offset;                    /* Read/write offset */\n    unsigned count;                     /* Byte count */\n    unsigned limit;                     /* Reply length */\n    unsigned char buf [1024 + 16];\n};\ntypedef struct sdcard sdcard_t;\n\nint dev_sdcard_init (sdcard_t *d, char *devname, unsigned mbytes, char *filename);\nvoid dev_sdcard_reset (cpu_mips_t *cpu);\nvoid dev_sdcard_select (cpu_mips_t *cpu, int unit, int on);\nunsigned dev_sdcard_io (cpu_mips_t *cpu, unsigned data);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/dev_swap.c",
    "content": "/*\n * RAM-based disk for swap.\n *\n * Copyright (C) 2011 Igor Mokos\n * Copyright (C) 2011 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n *\n */\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <string.h>\n#include <fcntl.h>\n#include <unistd.h>\n\n#include \"vm.h\"\n#include \"mips_memory.h\"\n#include \"device.h\"\n#include \"dev_swap.h\"\n\n//#define TRACE       printf\n#ifndef TRACE\n#define TRACE(...)  /*empty*/\n#endif\n\n/*\n * Reset swap.\n */\nvoid dev_swap_reset (cpu_mips_t *cpu)\n{\n    pic32_t *pic32 = (pic32_t*) cpu->vm->hw_data;\n\n    pic32->swap.rd = 0;\n    pic32->swap.wr = 0;\n    pic32->swap.ldaddr = 0;\n    pic32->swap.offset = 0;\n}\n\n/*\n * Initialize SD card.\n */\nint dev_swap_init (swap_t *d, char *name)\n{\n    memset (d, 0, sizeof (*d));\n    d->name = name;\n    return (0);\n}\n\nvoid dev_swap_rd (cpu_mips_t *cpu, int on)\n{\n    pic32_t *pic32 = (pic32_t*) cpu->vm->hw_data;\n    swap_t *d = &pic32->swap;\n\n    if (on && ! d->rd) {\n        d->rd = 1;\n        d->offset %= SWAP_BYTES;\n        d->data = d->buf [d->offset];\n        TRACE (\"swap: RD on, %06X -> %02X\\n\", d->offset, d->data);\n    } else if (! on && d->rd) {\n        d->rd = 0;\n        d->offset++;\n        TRACE (\"swap: RD off, offset = %06X\\n\", d->offset);\n    }\n}\n\nvoid dev_swap_wr (cpu_mips_t *cpu, int on)\n{\n    pic32_t *pic32 = (pic32_t*) cpu->vm->hw_data;\n    swap_t *d = &pic32->swap;\n\n    if (on && ! d->wr) {\n        d->wr = 1;\n        d->offset %= SWAP_BYTES;\n        d->buf [d->offset] = d->data;\n        TRACE (\"swap: WR on, %06X := %02X\\n\", d->offset, d->data);\n    } else if (! on && d->wr) {\n        d->wr = 0;\n        d->offset++;\n        TRACE (\"swap: WR off, offset = %06X\\n\", d->offset);\n    }\n}\n\nvoid dev_swap_ldaddr (cpu_mips_t *cpu, int on)\n{\n    pic32_t *pic32 = (pic32_t*) cpu->vm->hw_data;\n    swap_t *d = &pic32->swap;\n\n    if (on && ! d->ldaddr) {\n        d->ldaddr = 1;\n        d->offset >>= 4;\n        d->offset |= d->data << 20;\n        TRACE (\"swap: LDADDR on, offset = %06X\\n\", d->offset);\n    } else if (! on && d->ldaddr) {\n        TRACE (\"swap: LDADDR off\\n\");\n        d->ldaddr = 0;\n    }\n}\n\n/*\n * Data i/o: send byte to device.\n * Return received byte.\n */\nunsigned dev_swap_io (cpu_mips_t *cpu, unsigned char newval, unsigned char rmask)\n{\n    pic32_t *pic32 = (pic32_t*) cpu->vm->hw_data;\n    swap_t *d = &pic32->swap;\n\n    if (rmask == 0) {\n        /* Write mode. */\n        //TRACE (\"swap: send %02x\\n\", newval);\n        d->data = newval;\n    } else {\n        //TRACE (\"swap: receive %02x\\n\", d->data);\n    }\n\n    /* Read mode. */\n    return d->data;\n}\n"
  },
  {
    "path": "tools/virtualmips/dev_swap.h",
    "content": "/*\n * RAM-based disk for swap.\n *\n * Copyright (C) 2011 Igor Mokos\n * Copyright (C) 2011 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#ifndef __DEV_SWAP__\n#define __DEV_SWAP__\n\n#define SWAP_BYTES  (2*1024*1024)       /* Disk size */\n\n/* Swap device private data */\nstruct swap {\n    char *name;                         /* Device name */\n    int rd;                             /* RD signal */\n    int wr;                             /* WR signal */\n    int ldaddr;                         /* LDADDR signal */\n    unsigned char data;                 /* Latched byte */\n    unsigned offset;                    /* Read/write offset */\n    unsigned char buf [SWAP_BYTES];     /* Stored data */\n};\ntypedef struct swap swap_t;\n\nint dev_swap_init (swap_t *d, char *devname);\nvoid dev_swap_reset (cpu_mips_t *cpu);\nvoid dev_swap_rd (cpu_mips_t *cpu, int on);\nvoid dev_swap_wr (cpu_mips_t *cpu, int on);\nvoid dev_swap_ldaddr (cpu_mips_t *cpu, int on);\nunsigned dev_swap_io (cpu_mips_t *cpu, unsigned char data, unsigned char mask);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/dev_vtty.c",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)\n *\n * Virtual console TTY.\n *\n * \"Interactive\" part idea by Mtve.\n * TCP console added by Mtve.\n * Serial console by Peter Ross (suxen_drol@hotmail.com)\n */\n\n/* By default, Cygwin supports only 64 FDs with select()! */\n\n /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#ifdef __CYGWIN__\n#define FD_SETSIZE 1024\n#endif\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <termios.h>\n#include <fcntl.h>\n#include <errno.h>\n#include <assert.h>\n\n#include <arpa/telnet.h>\n\n#include \"utils.h\"\n#include \"mips.h\"\n#include \"vm.h\"\n\n#include \"mips_exec.h\"\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"dev_vtty.h\"\n\n/* VTTY list */\nstatic pthread_mutex_t vtty_list_mutex = PTHREAD_MUTEX_INITIALIZER;\nstatic vtty_t *vtty_list = NULL;\nstatic pthread_t vtty_thread;\n\n#define VTTY_LIST_LOCK()   pthread_mutex_lock(&vtty_list_mutex);\n#define VTTY_LIST_UNLOCK() pthread_mutex_unlock(&vtty_list_mutex);\n\nstatic struct termios tios, tios_orig;\n\n/* Send Telnet command: WILL TELOPT_ECHO */\nstatic void vtty_telnet_will_echo (vtty_t * vtty)\n{\n    u_char cmd[] = { IAC, WILL, TELOPT_ECHO };\n    if (write (vtty->fd, cmd, sizeof (cmd)) < 0)\n        perror (\"vtty_telnet_will_echo\");\n}\n\n/* Send Telnet command: Suppress Go-Ahead */\nstatic void vtty_telnet_will_suppress_go_ahead (vtty_t * vtty)\n{\n    u_char cmd[] = { IAC, WILL, TELOPT_SGA };\n    if (write (vtty->fd, cmd, sizeof (cmd)) < 0)\n        perror (\"vtty_telnet_will_suppress_go_ahead\");\n}\n\n/* Send Telnet command: Don't use linemode */\nstatic void vtty_telnet_dont_linemode (vtty_t * vtty)\n{\n    u_char cmd[] = { IAC, DONT, TELOPT_LINEMODE };\n    if (write (vtty->fd, cmd, sizeof (cmd)) < 0)\n        perror (\"vtty_telnet_dont_linemode\");\n}\n\n/* Send Telnet command: does the client support terminal type message? */\nstatic void vtty_telnet_do_ttype (vtty_t * vtty)\n{\n    u_char cmd[] = { IAC, DO, TELOPT_TTYPE };\n    if (write (vtty->fd, cmd, sizeof (cmd)) < 0)\n        perror (\"vtty_telnet_do_ttype\");\n}\n\n/* Restore TTY original settings */\nstatic void vtty_term_reset (void)\n{\n    tcsetattr (STDIN_FILENO, TCSANOW, &tios_orig);\n}\n\n/* Initialize real TTY */\nstatic void vtty_term_init (void)\n{\n    tcgetattr (STDIN_FILENO, &tios);\n\n    memcpy (&tios_orig, &tios, sizeof (struct termios));\n    atexit (vtty_term_reset);\n\n    tios.c_cc[VTIME] = 0;\n    tios.c_cc[VMIN] = 1;\n\n    /* Disable Ctrl-C, Ctrl-S, Ctrl-Q and Ctrl-Z */\n    tios.c_cc[VINTR] = 0;\n    tios.c_cc[VSTART] = 0;\n    tios.c_cc[VSTOP] = 0;\n    tios.c_cc[VSUSP] = 0;\n\n    tios.c_lflag &= ~(ICANON | ECHO);\n    tios.c_iflag &= ~ICRNL;\n    tcsetattr (STDIN_FILENO, TCSANOW, &tios);\n    tcflush (STDIN_FILENO, TCIFLUSH);\n}\n\n/* Wait for a TCP connection */\nstatic int vtty_tcp_conn_wait (vtty_t * vtty)\n{\n    struct sockaddr_in serv;\n    int one = 1;\n\n    vtty->state = VTTY_STATE_TCP_INVALID;\n\n    if ((vtty->accept_fd = socket (PF_INET, SOCK_STREAM, 0)) < 0) {\n        perror (\"vtty_tcp_waitcon: socket\");\n        return (-1);\n    }\n\n    if (setsockopt (vtty->accept_fd, SOL_SOCKET, SO_REUSEADDR, &one,\n            sizeof (one)) < 0) {\n        perror (\"vtty_tcp_waitcon: setsockopt(SO_REUSEADDR)\");\n        goto error;\n    }\n\n    memset (&serv, 0, sizeof (serv));\n    serv.sin_family = AF_INET;\n    serv.sin_addr.s_addr = htonl (INADDR_ANY);\n    serv.sin_port = htons (vtty->tcp_port);\n\n    if (bind (vtty->accept_fd, (struct sockaddr *) &serv, sizeof (serv)) < 0) {\n        perror (\"vtty_tcp_waitcon: bind\");\n        goto error;\n    }\n\n    if (listen (vtty->accept_fd, 1) < 0) {\n        perror (\"vtty_tcp_waitcon: listen\");\n        goto error;\n    }\n\n    vm_log (vtty->vm, \"VTTY\",\n        \"%s: waiting connection on tcp port %d (FD %d)\\n\", vtty->name,\n        vtty->tcp_port, vtty->accept_fd);\n\n    vtty->select_fd = &vtty->accept_fd;\n    vtty->state = VTTY_STATE_TCP_WAITING;\n    return (0);\n\n  error:\n    close (vtty->accept_fd);\n    vtty->accept_fd = -1;\n    vtty->select_fd = NULL;\n    return (-1);\n}\n\n/* Accept a TCP connection */\nstatic int vtty_tcp_conn_accept (vtty_t * vtty)\n{\n    if ((vtty->fd = accept (vtty->accept_fd, NULL, NULL)) < 0) {\n        fprintf (stderr,\n            \"vtty_tcp_conn_accept: accept on port %d failed %s\\n\",\n            vtty->tcp_port, strerror (errno));\n        return (-1);\n    }\n\n    vm_log (vtty->vm, \"VTTY\",\n        \"%s is now connected (accept_fd=%d,conn_fd=%d)\\n\", vtty->name,\n        vtty->accept_fd, vtty->fd);\n\n    /* Adapt Telnet settings */\n    if (vtty->terminal_support) {\n        vtty_telnet_do_ttype (vtty);\n        vtty_telnet_will_echo (vtty);\n        vtty_telnet_will_suppress_go_ahead (vtty);\n        vtty_telnet_dont_linemode (vtty);\n        vtty->input_state = VTTY_INPUT_TELNET;\n    }\n\n    if (!(vtty->fstream = fdopen (vtty->fd, \"wb\"))) {\n        close (vtty->fd);\n        vtty->fd = -1;\n        return (-1);\n    }\n\n    fprintf (vtty->fstream,\n        \"Connected to Dynamips VM \\\"%s\\\" ( type %s) - %s\\r\\n\\r\\n\",\n        vtty->vm->name, vm_get_type (vtty->vm), vtty->name);\n\n    vtty->select_fd = &vtty->fd;\n    vtty->state = VTTY_STATE_TCP_RUNNING;\n    return (0);\n}\n\n/*\n * Parse serial interface descriptor string, return 0 if success\n * string takes the form \"device:baudrate:databits:parity:stopbits:hwflow\"\n * device is mandatory, other options are optional (default=9600,8,N,1,0).\n */\nint vtty_parse_serial_option (vtty_serial_option_t * option, char *optarg)\n{\n    char *array[6];\n    int count;\n\n    if ((count = m_strtok (optarg, ':', array, 6)) < 1) {\n        fprintf (stderr, \"vtty_parse_serial_option: invalid string\\n\");\n        return (-1);\n    }\n\n    if (!(option->device = strdup (array[0]))) {\n        fprintf (stderr, \"vtty_parse_serial_option: unable to copy string\\n\");\n        return (-1);\n    }\n\n    option->baudrate = (count > 1) ? atoi (array[1]) : 9600;\n    option->databits = (count > 2) ? atoi (array[2]) : 8;\n\n    if (count > 3) {\n        switch (*array[3]) {\n        case 'o':\n        case 'O':\n            option->parity = 1; /* odd */\n        case 'e':\n        case 'E':\n            option->parity = 2; /* even */\n        default:\n            option->parity = 0; /* none */\n        }\n    } else {\n        option->parity = 0;\n    }\n\n    option->stopbits = (count > 4) ? atoi (array[4]) : 1;\n    option->hwflow = (count > 5) ? atoi (array[5]) : 0;\n    return (0);\n}\n\n#if defined(__CYGWIN__) || defined(SUNOS)\nvoid cfmakeraw (struct termios *termios_p)\n{\n    termios_p->c_iflag &=\n        ~(IGNBRK | BRKINT | PARMRK | ISTRIP | INLCR | IGNCR | ICRNL | IXON);\n    termios_p->c_oflag &= ~OPOST;\n    termios_p->c_lflag &= ~(ECHO | ECHONL | ICANON | ISIG | IEXTEN);\n    termios_p->c_cflag &= ~(CSIZE | PARENB);\n    termios_p->c_cflag |= CS8;\n}\n#endif\n\n/*\n * Setup serial port, return 0 if success.\n */\nstatic int vtty_serial_setup (vtty_t * vtty,\n    const vtty_serial_option_t * option)\n{\n    struct termios tio;\n    int tio_baudrate;\n\n    if (tcgetattr (vtty->fd, &tio) != 0) {\n        fprintf (stderr, \"error: tcgetattr failed\\n\");\n        return (-1);\n    }\n\n    cfmakeraw (&tio);\n\n    tio.c_cflag = 0 | CLOCAL    // ignore modem control lines\n        ;\n\n    tio.c_cflag &= ~CREAD;\n    tio.c_cflag |= CREAD;\n\n    switch (option->baudrate) {\n    case 50:\n        tio_baudrate = B50;\n        break;\n    case 75:\n        tio_baudrate = B75;\n        break;\n    case 110:\n        tio_baudrate = B110;\n        break;\n    case 134:\n        tio_baudrate = B134;\n        break;\n    case 150:\n        tio_baudrate = B150;\n        break;\n    case 200:\n        tio_baudrate = B200;\n        break;\n    case 300:\n        tio_baudrate = B300;\n        break;\n    case 600:\n        tio_baudrate = B600;\n        break;\n    case 1200:\n        tio_baudrate = B1200;\n        break;\n    case 1800:\n        tio_baudrate = B1800;\n        break;\n    case 2400:\n        tio_baudrate = B2400;\n        break;\n    case 4800:\n        tio_baudrate = B4800;\n        break;\n    case 9600:\n        tio_baudrate = B9600;\n        break;\n    case 19200:\n        tio_baudrate = B19200;\n        break;\n    case 38400:\n        tio_baudrate = B38400;\n        break;\n    case 57600:\n        tio_baudrate = B57600;\n        break;\n#if defined(B76800)\n    case 76800:\n        tio_baudrate = B76800;\n        break;\n#endif\n    case 115200:\n        tio_baudrate = B115200;\n        break;\n#if defined(B230400)\n    case 230400:\n        tio_baudrate = B230400;\n        break;\n#endif\n    default:\n        fprintf (stderr, \"error: unsupported baudrate\\n\");\n        return (-1);\n    }\n\n    cfsetospeed (&tio, tio_baudrate);\n    cfsetispeed (&tio, tio_baudrate);\n\n    tio.c_cflag &= ~CSIZE;      /* clear size flag */\n    switch (option->databits) {\n    case 5:\n        tio.c_cflag |= CS5;\n        break;\n    case 6:\n        tio.c_cflag |= CS6;\n        break;\n    case 7:\n        tio.c_cflag |= CS7;\n        break;\n    case 8:\n        tio.c_cflag |= CS8;\n        break;\n    default:\n        fprintf (stderr, \"error: unsupported databits\\n\");\n        return (-1);\n    }\n\n    tio.c_iflag &= ~INPCK;      /* clear parity flag */\n    tio.c_cflag &= ~(PARENB | PARODD);\n    switch (option->parity) {\n    case 0:\n        break;\n    case 2:\n        tio.c_iflag |= INPCK;\n        tio.c_cflag |= PARENB;\n        break;                  /* even */\n    case 1:\n        tio.c_iflag |= INPCK;\n        tio.c_cflag |= PARENB | PARODD;\n        break;                  /* odd */\n    default:\n        fprintf (stderr, \"error: unsupported parity\\n\");\n        return (-1);\n    }\n\n    tio.c_cflag &= ~CSTOPB;     /* clear stop flag */\n    switch (option->stopbits) {\n    case 1:\n        break;\n    case 2:\n        tio.c_cflag |= CSTOPB;\n        break;\n    default:\n        fprintf (stderr, \"error: unsupported stopbits\\n\");\n        return (-1);\n    }\n\n#if defined(CRTSCTS)\n    tio.c_cflag &= ~CRTSCTS;\n#endif\n#if defined(CNEW_RTSCTS)\n    tio.c_cflag &= ~CNEW_RTSCTS;\n#endif\n    if (option->hwflow) {\n#if defined(CRTSCTS)\n        tio.c_cflag |= CRTSCTS;\n#else\n        tio.c_cflag |= CNEW_RTSCTS;\n#endif\n    }\n\n    tio.c_cc[VTIME] = 0;\n    tio.c_cc[VMIN] = 1;         /* block read() until one character is available */\n\n#if 0\n    /* not neccessary unless O_NONBLOCK used */\n    if (fcntl (vtty->fd, F_SETFL, 0) != 0) {    /* enable blocking mode */\n        fprintf (stderr, \"error: fnctl F_SETFL failed\\n\");\n        return (-1);\n    }\n#endif\n\n    if (tcflush (vtty->fd, TCIOFLUSH) != 0) {\n        fprintf (stderr, \"error: tcflush failed\\n\");\n        return (-1);\n    }\n\n    if (tcsetattr (vtty->fd, TCSANOW, &tio) != 0) {\n        fprintf (stderr, \"error: tcsetattr failed\\n\");\n        return (-1);\n    }\n\n    return (0);\n}\n\n/* Create a virtual tty */\nvtty_t *vtty_create (vm_instance_t * vm, char *name, int type, int tcp_port,\n    const vtty_serial_option_t * option)\n{\n    vtty_t *vtty;\n\n    if (!(vtty = malloc (sizeof (*vtty)))) {\n        fprintf (stderr, \"VTTY: unable to create new virtual tty.\\n\");\n        return NULL;\n    }\n\n    memset (vtty, 0, sizeof (*vtty));\n    vtty->name = name;\n    vtty->type = type;\n    vtty->vm = vm;\n    vtty->fd = -1;\n    vtty->fstream = NULL;\n    vtty->accept_fd = -1;\n    pthread_mutex_init (&vtty->lock, NULL);\n    vtty->terminal_support = 0; // was 1 (vak)\n    vtty->input_state = VTTY_INPUT_TEXT;\n\n    switch (vtty->type) {\n    case VTTY_TYPE_NONE:\n        vtty->select_fd = NULL;\n        break;\n\n    case VTTY_TYPE_TERM:\n        vtty_term_init ();\n        vtty->fd = STDIN_FILENO;\n        vtty->select_fd = &vtty->fd;\n        vtty->fstream = stdout;\n        break;\n\n    case VTTY_TYPE_TCP:\n        vtty->tcp_port = tcp_port;\n        vtty_tcp_conn_wait (vtty);\n        break;\n\n    case VTTY_TYPE_SERIAL:\n        vtty->fd = open (option->device, O_RDWR);\n        if (vtty->fd < 0) {\n            fprintf (stderr, \"VTTY: open failed\\n\");\n            free (vtty);\n            return NULL;\n        }\n        if (vtty_serial_setup (vtty, option)) {\n            fprintf (stderr, \"VTTY: setup failed\\n\");\n            close (vtty->fd);\n            free (vtty);\n            return NULL;\n        }\n        vtty->select_fd = &vtty->fd;\n        vtty->terminal_support = 0;\n        break;\n\n    default:\n        fprintf (stderr, \"tty_create: bad vtty type %d\\n\", vtty->type);\n        return NULL;\n    }\n\n    /* Add this new VTTY to the list */\n    VTTY_LIST_LOCK ();\n    vtty->next = vtty_list;\n    vtty->pprev = &vtty_list;\n\n    if (vtty_list != NULL)\n        vtty_list->pprev = &vtty->next;\n\n    vtty_list = vtty;\n    VTTY_LIST_UNLOCK ();\n    return vtty;\n}\n\n/* Delete a virtual tty */\nvoid vtty_delete (vtty_t * vtty)\n{\n    if (vtty != NULL) {\n        if (vtty->pprev != NULL) {\n            VTTY_LIST_LOCK ();\n            if (vtty->next)\n                vtty->next->pprev = vtty->pprev;\n            *(vtty->pprev) = vtty->next;\n            VTTY_LIST_UNLOCK ();\n        }\n\n        if ((vtty->fstream) && (vtty->fstream != stdout))\n            fclose (vtty->fstream);\n\n        /* We don't close FD 0 since it is stdin */\n        if (vtty->fd > 0) {\n            vm_log (vtty->vm, \"VTTY\", \"%s: closing FD %d\\n\", vtty->name,\n                vtty->fd);\n            close (vtty->fd);\n        }\n\n        if (vtty->accept_fd != -1) {\n            vm_log (vtty->vm, \"VTTY\", \"%s: closing accept FD %d\\n\",\n                vtty->name, vtty->accept_fd);\n            close (vtty->accept_fd);\n        }\n\n        free (vtty);\n    }\n}\n\n/* Store a character in the FIFO buffer */\nstatic int vtty_store (vtty_t * vtty, u_char c)\n{\n    u_int nwptr;\n\n    VTTY_LOCK (vtty);\n    nwptr = vtty->write_ptr + 1;\n    if (nwptr == VTTY_BUFFER_SIZE)\n        nwptr = 0;\n\n    if (nwptr == vtty->read_ptr) {\n        VTTY_UNLOCK (vtty);\n        return (-1);\n    }\n\n    vtty->buffer[vtty->write_ptr] = c;\n    vtty->write_ptr = nwptr;\n    VTTY_UNLOCK (vtty);\n    return (0);\n}\n\n/* Store a string in the FIFO buffer */\nint vtty_store_str (vtty_t * vtty, char *str)\n{\n    if (!vtty)\n        return (0);\n\n    while (*str != 0) {\n        if (vtty_store (vtty, *str) == -1)\n            return (-1);\n\n        str++;\n    }\n\n    vtty->input_pending = TRUE;\n    return (0);\n}\n\n/* Store CTRL+C in buffer */\nint vtty_store_ctrlc (vtty_t * vtty)\n{\n    if (vtty)\n        vtty_store (vtty, 0x03);\n    return (0);\n}\n\n/*\n * Read a character from the terminal.\n */\nstatic int vtty_term_read (vtty_t * vtty)\n{\n    u_char c;\n\n    if (read (vtty->fd, &c, 1) == 1)\n        return (c);\n\n    perror (\"read from vtty failed\");\n    return (-1);\n}\n\n/*\n * Read a character from the TCP connection.\n */\nstatic int vtty_tcp_read (vtty_t * vtty)\n{\n    u_char c;\n\n    switch (vtty->state) {\n    case VTTY_STATE_TCP_RUNNING:\n        if (read (vtty->fd, &c, 1) == 1)\n            return (c);\n\n        /* Problem with the connection: Re-enter wait mode */\n        shutdown (vtty->fd, 2);\n        fclose (vtty->fstream);\n        close (vtty->fd);\n        vtty->fstream = NULL;\n        vtty->fd = -1;\n        vtty->select_fd = &vtty->accept_fd;\n        vtty->state = VTTY_STATE_TCP_WAITING;\n        return (-1);\n\n    case VTTY_STATE_TCP_WAITING:\n        /* A new connection has arrived */\n        vtty_tcp_conn_accept (vtty);\n        return (-1);\n    }\n\n    /* Shouldn't happen... */\n    return (-1);\n}\n\n/*\n * Read a character from the USB connection.\n */\nstatic int vtty_usb_read (vtty_t * vtty)\n{\n    // stub\n    perror(\"VTTY not yet implemented on USB\\n\");\n    return (-1);\n}\n\n/*\n * Read a character from the virtual TTY.\n *\n * If the VTTY is a TCP connection, restart it in case of error.\n */\nstatic int vtty_read (vtty_t * vtty)\n{\n    switch (vtty->type) {\n    case VTTY_TYPE_TERM:\n    case VTTY_TYPE_SERIAL:\n        return (vtty_term_read (vtty));\n    case VTTY_TYPE_TCP:\n        return (vtty_tcp_read (vtty));\n    case VTTY_TYPE_USB:\n        return (vtty_usb_read (vtty));\n    default:\n        fprintf (stderr, \"vtty_read: bad vtty type %d\\n\", vtty->type);\n        return (-1);\n    }\n\n    /* NOTREACHED */\n    return (-1);\n}\n\n#if 0\n/* Remote control for MIPS64 processors */\nstatic int remote_control_mips (vtty_t * vtty, char c, cpu_mips_t * cpu)\n{\n    switch (c) {\n        /* Show information about JIT compiled pages */\n    case 'b':\n        //   printf(\"\\nCPU0: %u JIT compiled pages [Exec Area Pages: %lu/%lu]\\n\",\n        //        cpu->compiled_pages,\n        //       (u_long)cpu->exec_page_alloc,\n        //         (u_long)cpu->exec_page_count);\n        break;\n\n        /* Non-JIT mode statistics */\n    case 'j':\n        // mips_dump_stats(cpu);\n        break;\n\n    default:\n        return (FALSE);\n    }\n\n    return (TRUE);\n}\n#endif\n\n/* Read a character (until one is available) and store it in buffer */\nstatic void vtty_read_and_store (vtty_t * vtty)\n{\n    int c;\n\n    /* wait until we get a character input */\n    c = vtty_read (vtty);\n\n    /* if read error, do nothing */\n    if (c < 0)\n        return;\n\n    if (!vtty->terminal_support) {\n        vtty_store (vtty, c);\n        return;\n    }\n\n    switch (vtty->input_state) {\n    case VTTY_INPUT_TEXT:\n        switch (c) {\n        case 0x1b:\n            vtty->input_state = VTTY_INPUT_VT1;\n            return;\n\n            /* Ctrl + ']' (0x1d, 29), or Alt-Gr + '*' (0xb3, 179) */\n        case 0x1d:\n        case 0xb3:\n            vtty->input_state = VTTY_INPUT_REMOTE;\n            return;\n        case IAC:\n            vtty->input_state = VTTY_INPUT_TELNET;\n            return;\n        case 0:                /* NULL - Must be ignored - generated by Linux telnet */\n        case 10:               /* LF (Line Feed) - Must be ignored on Windows platform */\n            return;\n        default:\n            /* Store a standard character */\n            vtty_store (vtty, c);\n            return;\n        }\n\n    case VTTY_INPUT_VT1:\n        switch (c) {\n        case 0x5b:\n            vtty->input_state = VTTY_INPUT_VT2;\n            return;\n        default:\n            vtty_store (vtty, 0x1b);\n            vtty_store (vtty, c);\n        }\n        vtty->input_state = VTTY_INPUT_TEXT;\n        return;\n\n    case VTTY_INPUT_VT2:\n        switch (c) {\n        case 0x41:             /* Up Arrow */\n            vtty_store (vtty, 16);\n            break;\n        case 0x42:             /* Down Arrow */\n            vtty_store (vtty, 14);\n            break;\n        case 0x43:             /* Right Arrow */\n            vtty_store (vtty, 6);\n            break;\n        case 0x44:             /* Left Arrow */\n            vtty_store (vtty, 2);\n            break;\n        default:\n            vtty_store (vtty, 0x5b);\n            vtty_store (vtty, 0x1b);\n            vtty_store (vtty, c);\n            break;\n        }\n        vtty->input_state = VTTY_INPUT_TEXT;\n        return;\n\n    case VTTY_INPUT_REMOTE:\n        //remote_control(vtty, c);\n        vtty->input_state = VTTY_INPUT_TEXT;\n        return;\n\n    case VTTY_INPUT_TELNET:\n        vtty->telnet_cmd = c;\n        switch (c) {\n        case WILL:\n        case WONT:\n        case DO:\n        case DONT:\n            vtty->input_state = VTTY_INPUT_TELNET_IYOU;\n            return;\n        case SB:\n            vtty->telnet_cmd = c;\n            vtty->input_state = VTTY_INPUT_TELNET_SB1;\n            return;\n        case SE:\n            break;\n        case IAC:\n            vtty_store (vtty, IAC);\n            break;\n        }\n        vtty->input_state = VTTY_INPUT_TEXT;\n        return;\n\n    case VTTY_INPUT_TELNET_IYOU:\n        vtty->telnet_opt = c;\n        /* if telnet client can support ttype, ask it to send ttype string */\n        if ((vtty->telnet_cmd == WILL) && (vtty->telnet_opt == TELOPT_TTYPE)) {\n            vtty_put_char (vtty, IAC);\n            vtty_put_char (vtty, SB);\n            vtty_put_char (vtty, TELOPT_TTYPE);\n            vtty_put_char (vtty, TELQUAL_SEND);\n            vtty_put_char (vtty, IAC);\n            vtty_put_char (vtty, SE);\n        }\n        vtty->input_state = VTTY_INPUT_TEXT;\n        return;\n\n    case VTTY_INPUT_TELNET_SB1:\n        vtty->telnet_opt = c;\n        vtty->input_state = VTTY_INPUT_TELNET_SB2;\n        return;\n\n    case VTTY_INPUT_TELNET_SB2:\n        vtty->telnet_qual = c;\n        if ((vtty->telnet_opt == TELOPT_TTYPE)\n            && (vtty->telnet_qual == TELQUAL_IS))\n            vtty->input_state = VTTY_INPUT_TELNET_SB_TTYPE;\n        else\n            vtty->input_state = VTTY_INPUT_TELNET_NEXT;\n        return;\n\n    case VTTY_INPUT_TELNET_SB_TTYPE:\n        /* parse ttype string: first char is sufficient */\n        /* if client is xterm or vt, set the title bar */\n        if ((c == 'x') || (c == 'X') || (c == 'v') || (c == 'V')) {\n            // fprintf(vtty->fstream, \"\\033]0;Dynamips(%i): %s, %s\\07\",\n            //         vtty->vm->instance_id, vtty->vm->name, vtty->name);\n        }\n        vtty->input_state = VTTY_INPUT_TELNET_NEXT;\n        return;\n\n    case VTTY_INPUT_TELNET_NEXT:\n        /* ignore all chars until next IAC */\n        if (c == IAC)\n            vtty->input_state = VTTY_INPUT_TELNET;\n        return;\n    }\n}\n\nint vtty_bytes (vtty_t * vtty)\n{\n    if (vtty->read_ptr < vtty->write_ptr)\n        return vtty->write_ptr - vtty->read_ptr;\n    else if (vtty->read_ptr == vtty->write_ptr) {\n        return VTTY_BUFFER_SIZE;\n    } else\n        return VTTY_BUFFER_SIZE - (vtty->read_ptr - vtty->write_ptr);\n}\n\nint vtty_is_full (vtty_t * vtty)\n{\n    return (vtty->read_ptr == vtty->write_ptr);\n}\n\n/* Read a character from the buffer (-1 if the buffer is empty) */\nint vtty_get_char (vtty_t * vtty)\n{\n    u_char c;\n\n    VTTY_LOCK (vtty);\n\n    if (vtty->read_ptr == vtty->write_ptr) {\n        VTTY_UNLOCK (vtty);\n        return (-1);\n    }\n\n    c = vtty->buffer[vtty->read_ptr++];\n\n    if (vtty->read_ptr == VTTY_BUFFER_SIZE)\n        vtty->read_ptr = 0;\n\n    VTTY_UNLOCK (vtty);\n    return (c);\n}\n\n/* Returns TRUE if a character is available in buffer */\nint vtty_is_char_avail (vtty_t * vtty)\n{\n    int res;\n\n    VTTY_LOCK (vtty);\n    res = (vtty->read_ptr != vtty->write_ptr);\n    VTTY_UNLOCK (vtty);\n    return (res);\n}\n\n/* Put char to vtty */\n// XXX void vtty_put_char (vtty_t * vtty, char ch)\nvoid vtty_put_char (vtty_t * vtty, int ch)\n{\n    switch (vtty->type) {\n    case VTTY_TYPE_NONE:\n        break;\n\n    case VTTY_TYPE_TERM:\n        //printf(\"put char  %c\\n\",ch);\n        fwrite (&ch, 1, 1, vtty->fstream);\n        break;\n\n    case VTTY_TYPE_TCP:\n        if ((vtty->state == VTTY_STATE_TCP_RUNNING)\n            && (fwrite (&ch, 1, 1, vtty->fstream) != 1)) {\n            vm_log (vtty->vm, \"VTTY\", \"%s: put char %d failed (%s)\\n\",\n                vtty->name, (int) ch, strerror (errno));\n        }\n        break;\n\n    case VTTY_TYPE_SERIAL:\n        if (write (vtty->fd, &ch, 1) != 1) {\n            vm_log (vtty->vm, \"VTTY\", \"%s: put char 0x%x failed (%s)\\n\",\n                vtty->name, (int) ch, strerror (errno));\n        }\n        break;\n\n    default:\n        fprintf (stderr, \"vtty_put_char: bad vtty type %d\\n\", vtty->type);\n        exit (1);\n    }\n}\n\n/* Put a buffer to vtty */\nvoid vtty_put_buffer (vtty_t * vtty, char *buf, size_t len)\n{\n    size_t i;\n\n    for (i = 0; i < len; i++)\n        vtty_put_char (vtty, buf[i]);\n}\n\n/* Flush VTTY output */\nvoid vtty_flush (vtty_t * vtty)\n{\n    switch (vtty->type) {\n    case VTTY_TYPE_TERM:\n    case VTTY_TYPE_TCP:\n        if (vtty->fstream)\n            fflush (vtty->fstream);\n        break;\n\n    case VTTY_TYPE_SERIAL:\n        fsync (vtty->fd);\n        break;\n    }\n}\n\n/* VTTY thread */\nstatic void *vtty_thread_main (void *arg)\n{\n    vtty_t *vtty;\n    struct timeval tv;\n    int fd, fd_max, res;\n    fd_set rfds;\n\n    for (;;) {\n        VTTY_LIST_LOCK ();\n\n        /* Build the FD set */\n        FD_ZERO (&rfds);\n        fd_max = -1;\n        for (vtty = vtty_list; vtty; vtty = vtty->next) {\n            if (!vtty->select_fd)\n                continue;\n\n            if ((fd = *vtty->select_fd) < 0)\n                continue;\n\n            if (fd > fd_max)\n                fd_max = fd;\n            FD_SET (fd, &rfds);\n        }\n        VTTY_LIST_UNLOCK ();\n\n        /* Wait for incoming data */\n        tv.tv_sec = 0;\n        tv.tv_usec = 50 * 1000; /* 50 ms */\n        res = select (fd_max + 1, &rfds, NULL, NULL, &tv);\n\n        if (res == -1) {\n            if (errno != EINTR) {\n                perror (\"vtty_thread: select\");\n\n                for (vtty = vtty_list; vtty; vtty = vtty->next) {\n                    fprintf (stderr, \"   %-15s: %s, FD %d\\n\", vtty->vm->name,\n                        vtty->name, vtty->fd);\n                }\n            }\n            continue;\n        }\n\n        /* Examine active FDs and call user handlers */\n        VTTY_LIST_LOCK ();\n        for (vtty = vtty_list; vtty; vtty = vtty->next) {\n            if (!vtty->select_fd)\n                continue;\n\n            if ((fd = *vtty->select_fd) < 0)\n                continue;\n\n            if (FD_ISSET (fd, &rfds)) {\n                vtty_read_and_store (vtty);\n                vtty->input_pending = TRUE;\n            }\n\n            if (vtty->input_pending) {\n                if (vtty->read_notifier != NULL)\n                    vtty->read_notifier (vtty);\n\n                vtty->input_pending = FALSE;\n            }\n\n            /* Flush any pending output */\n            if (!vtty->managed_flush)\n                vtty_flush (vtty);\n        }\n        VTTY_LIST_UNLOCK ();\n    }\n\n    return NULL;\n}\n\n/* Initialize the VTTY thread */\nint vtty_init (void)\n{\n    if (pthread_create (&vtty_thread, NULL, vtty_thread_main, NULL)) {\n        perror (\"vtty: pthread_create\");\n        return (-1);\n    }\n\n    return (0);\n}\n"
  },
  {
    "path": "tools/virtualmips/dev_vtty.h",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)\n *\n * Virtual console TTY.\n */\n\n /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *     \n  * This file is part of the virtualmips distribution. \n  * See LICENSE file for terms of the license. \n  *\n  */\n\n#ifndef __DEV_VTTY_H__\n#define __DEV_VTTY_H__\n\n#include <sys/types.h>\n#include <pthread.h>\n\n#include \"vm.h\"\n#include <stdio.h>\n\n/* 4 Kb should be enough for a keyboard buffer */\n#define VTTY_BUFFER_SIZE  4096\n\n/* VTTY connection types */\nenum {\n    VTTY_TYPE_NONE = 0,\n    VTTY_TYPE_TERM,\n    VTTY_TYPE_TCP,\n    VTTY_TYPE_SERIAL,\n    VTTY_TYPE_USB,\n};\n\n/* VTTY connection states (for TCP) */\nenum {\n    VTTY_STATE_TCP_INVALID,     /* connection is not working */\n    VTTY_STATE_TCP_WAITING,     /* waiting for incoming connection */\n    VTTY_STATE_TCP_RUNNING,     /* character reading/writing ok */\n};\n\n/* VTTY input states */\nenum {\n    VTTY_INPUT_TEXT,\n    VTTY_INPUT_VT1,\n    VTTY_INPUT_VT2,\n    VTTY_INPUT_REMOTE,\n    VTTY_INPUT_TELNET,\n    VTTY_INPUT_TELNET_IYOU,\n    VTTY_INPUT_TELNET_SB1,\n    VTTY_INPUT_TELNET_SB2,\n    VTTY_INPUT_TELNET_SB_TTYPE,\n    VTTY_INPUT_TELNET_NEXT\n};\n\n/* Commmand line support utility */\ntypedef struct vtty_serial_option vtty_serial_option_t;\nstruct vtty_serial_option {\n    char *device;\n    int baudrate, databits, parity, stopbits, hwflow;\n};\n\nint vtty_parse_serial_option (vtty_serial_option_t * params, char *optarg);\n\n/* Virtual TTY structure */\ntypedef struct virtual_tty vtty_t;\nstruct virtual_tty {\n    vm_instance_t *vm;\n    char *name;\n    int type, state;\n    int tcp_port;\n    int terminal_support;\n    int input_state;\n    int input_pending;\n    int telnet_cmd, telnet_opt, telnet_qual;\n    int fd, accept_fd, *select_fd;\n    int managed_flush;\n    FILE *fstream;\n    u_char buffer[VTTY_BUFFER_SIZE];\n    u_int read_ptr, write_ptr;\n    pthread_mutex_t lock;\n    vtty_t *next, **pprev;\n    void *priv_data;\n\n    /* Read notification */\n    void (*read_notifier) (vtty_t *);\n};\n\n#define VTTY_LOCK(tty) pthread_mutex_lock(&(tty)->lock);\n#define VTTY_UNLOCK(tty) pthread_mutex_unlock(&(tty)->lock);\n\n/* create a virtual tty */\nvtty_t *vtty_create (vm_instance_t * vm, char *name, int type, int tcp_port,\n    const vtty_serial_option_t * option);\n\n/* delete a virtual tty */\nvoid vtty_delete (vtty_t * vtty);\n\n/* Store a string in the FIFO buffer */\nint vtty_store_str (vtty_t * vtty, char *str);\n\n/* read a character from the buffer (-1 if the buffer is empty) */\nint vtty_get_char (vtty_t * vtty);\n\n/* print a character to vtty */\n// XXX void vtty_put_char (vtty_t * vtty, char ch);\nvoid vtty_put_char (vtty_t * vtty, int ch);\n\n/* Put a buffer to vtty */\nvoid vtty_put_buffer (vtty_t * vtty, char *buf, size_t len);\n\n/* Flush VTTY output */\nvoid vtty_flush (vtty_t * vtty);\n\n/* returns TRUE if a character is available in buffer */\nint vtty_is_char_avail (vtty_t * vtty);\n\n/* write CTRL+C to buffer */\nint vtty_store_ctrlc (vtty_t *);\n\n/* Initialize the VTTY thread */\nint vtty_init (void);\n\nint vtty_is_full (vtty_t * vtty);\n\nint vtty_bytes (vtty_t * vtty);\n#endif\n"
  },
  {
    "path": "tools/virtualmips/device.c",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)\n */\n\n  /*\n   * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n   *\n   * This file is part of the virtualmips distribution.\n   * See LICENSE file for terms of the license.\n   *\n   */\n\n#define _GNU_SOURCE\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <string.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <sys/mman.h>\n#include <fcntl.h>\n#include <assert.h>\n\n#include \"cpu.h\"\n#include \"vm.h\"\n#include \"mips_memory.h\"\n#include \"device.h\"\n\n#define DEBUG_DEV_ACCESS  0\n\n/* Get device by ID */\nstruct vdevice *dev_get_by_id (vm_instance_t * vm, u_int dev_id)\n{\n    if (!vm || (dev_id >= VM_DEVICE_MAX))\n        return NULL;\n\n    return (vm->dev_array[dev_id]);\n}\n\n/* Get device by name */\nstruct vdevice *dev_get_by_name (vm_instance_t * vm, char *name)\n{\n    struct vdevice *dev;\n\n    if (!vm)\n        return NULL;\n\n    for (dev = vm->dev_list; dev; dev = dev->next)\n        if (!strcmp (dev->name, name))\n            return dev;\n\n    return NULL;\n}\n\n/* Device lookup by physical address */\n//struct vdevice *dev_lookup(vm_instance_t *vm,m_pa_t phys_addr,int cached)\nstruct vdevice *dev_lookup (vm_instance_t * vm, m_pa_t phys_addr)\n{\n    struct vdevice *dev;\n\n    if (!vm)\n        return NULL;\n\n    for (dev = vm->dev_list; dev; dev = dev->next) {\n        // if (cached && !(dev->flags & VDEVICE_FLAG_CACHING))\n        //    continue;\n\n        if ((phys_addr >= dev->phys_addr)\n            && ((phys_addr - dev->phys_addr) < dev->phys_len))\n            return dev;\n    }\n\n    return NULL;\n}\n\n/* Find the next device after the specified address */\n//struct vdevice *dev_lookup_next(vm_instance_t *vm,m_pa_t phys_addr,\n//                                struct vdevice *dev_start,int cached)\nstruct vdevice *dev_lookup_next (vm_instance_t * vm, m_pa_t phys_addr,\n    struct vdevice *dev_start)\n{\n    struct vdevice *dev;\n\n    if (!vm)\n        return NULL;\n\n    dev = (dev_start != NULL) ? dev_start : vm->dev_list;\n    for (; dev; dev = dev->next) {\n        //if (cached && !(dev->flags & VDEVICE_FLAG_CACHING))\n        //   continue;\n\n        if (dev->phys_addr > phys_addr)\n            return dev;\n    }\n\n    return NULL;\n}\n\n/* Initialize a device */\nvoid dev_init (struct vdevice *dev)\n{\n    memset (dev, 0, sizeof (*dev));\n    dev->fd = -1;\n}\n\n/* reset all devices */\nvoid dev_reset_all (vm_instance_t * vm)\n{\n    struct vdevice *dev;\n    for (dev = vm->dev_list; dev; dev = dev->next) {\n        ASSERT (dev->reset_handler != NULL,\n            \"reset_handler is NULL. name %s\\n\", dev->name);\n        dev->reset_handler (vm->boot_cpu, dev);\n    }\n}\n\n/* Allocate a device */\nstruct vdevice *dev_create (char *name)\n{\n    struct vdevice *dev;\n\n    if (!(dev = malloc (sizeof (*dev)))) {\n        fprintf (stderr,\n            \"dev_create: insufficient memory to \" \"create device '%s'.\\n\",\n            name);\n        return NULL;\n    }\n\n    dev_init (dev);\n    dev->name = name;\n    return dev;\n}\n\n/* Remove a device */\nvoid dev_remove (vm_instance_t * vm, struct vdevice *dev)\n{\n    if (dev == NULL)\n        return;\n\n    vm_unbind_device (vm, dev);\n\n    vm_log (vm, \"DEVICE\",\n        \"Removal of device %s, fd=%d, host_addr=0x%\" LL \"x, flags=%d\\n\",\n        dev->name, dev->fd, (m_uint64_t) dev->host_addr, dev->flags);\n\n    if (dev->flags & VDEVICE_FLAG_REMAP) {\n        dev_init (dev);\n        return;\n    }\n\n    if (dev->fd != -1) {\n        /* Unmap memory mapped file */\n        if (dev->host_addr) {\n\n            vm_log (vm, \"MMAP\", \"unmapping of device '%s', \"\n                \"fd=%d, host_addr=0x%\" LL \"x, len=0x%x\\n\",\n                dev->name, dev->fd, (m_uint64_t) dev->host_addr,\n                dev->phys_len);\n            munmap ((void *) dev->host_addr, dev->phys_len);\n        }\n\n        close (dev->fd);\n    } else {\n        /* Use of malloc'ed host memory: free it */\n        if (dev->host_addr)\n            free ((void *) dev->host_addr);\n    }\n\n    /* reinitialize the device to a clean state */\n    dev_init (dev);\n}\n\n/* Show properties of a device */\nvoid dev_show (struct vdevice *dev)\n{\n    if (!dev)\n        return;\n\n    printf (\"   %-18s: 0x%12.12\" LL \"x (0x%8.8x)\\n\", dev->name,\n        dev->phys_addr, dev->phys_len);\n}\n\n/* Show the device list */\nvoid dev_show_list (vm_instance_t * vm)\n{\n    struct vdevice *dev;\n\n    printf (\"\\nVM \\\"%s\\\" () Device list:\\n\", vm->name);\n\n    for (dev = vm->dev_list; dev; dev = dev->next)\n        dev_show (dev);\n\n    printf (\"\\n\");\n}\n\n/* Remap a device at specified physical address */\nstruct vdevice *dev_remap (char *name, struct vdevice *orig, m_pa_t paddr,\n    m_uint32_t len)\n{\n    struct vdevice *dev;\n\n    if (!(dev = dev_create (name)))\n        return NULL;\n\n    dev->phys_addr = paddr;\n    dev->phys_len = len;\n    dev->flags = orig->flags | VDEVICE_FLAG_REMAP;\n    dev->fd = orig->fd;\n    dev->host_addr = orig->host_addr;\n    dev->handler = orig->handler;\n    //dev->sparse_map = orig->sparse_map;\n    return dev;\n}\n\n/* Create a RAM device */\nstruct vdevice *dev_create_ram (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len)\n{\n    struct vdevice *dev;\n\n    if (!(dev = dev_create (name)))\n        return NULL;\n\n    dev->phys_addr = paddr;\n    dev->phys_len = len;\n    //dev->flags = VDEVICE_FLAG_CACHING;\n    dev->host_addr = (m_iptr_t) m_memalign (4096, dev->phys_len);\n    memset ((void*) dev->host_addr, 0, dev->phys_len);\n\n    if (!dev->host_addr) {\n        free (dev);\n        return NULL;\n    }\n\n    vm_bind_device (vm, dev);\n    return dev;\n}\n"
  },
  {
    "path": "tools/virtualmips/device.h",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)\n */\n\n /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#ifndef __DEVICE_H__\n#define __DEVICE_H__\n\n#include <sys/types.h>\n\n#include \"utils.h\"\n#include \"mips.h\"\n#include \"vm.h\"\n#include \"cpu.h\"\n/* Device Flags */\n#define VDEVICE_FLAG_NO_MTS_MMAP  0x01  /* Prevent MMAPed access by MTS */\n#define VDEVICE_FLAG_CACHING      0x02  /* Device does support caching */\n#define VDEVICE_FLAG_REMAP        0x04  /* Physical address remapping */\n//#define VDEVICE_FLAG_COW        0x08  /* Copy on write device  */\n\n#define VDEVICE_PTE_DIRTY  0x01\n\n/*device handler */\ntypedef void *(*dev_handler_t) (cpu_mips_t * cpu, vdevice_t * dev,\n    m_uint32_t offset, u_int op_size, u_int op_type,\n    m_reg_t * data, m_uint8_t * has_set_value);\n\ntypedef void (*dev_reset_handler_t) (cpu_mips_t * cpu, vdevice_t * dev);\n\n/* Virtual Device */\nstruct vdevice {\n    char *name;\n    u_int id;\n    m_pa_t phys_addr;\n    m_uint32_t phys_len;\n    m_iptr_t host_addr;\n    void *priv_data;\n    int flags;\n    int fd;\n    dev_handler_t handler;\n    dev_reset_handler_t reset_handler;\n    struct vdevice *next, **pprev;\n};\n\n/* device access function */\nstatic forced_inline\n    void *dev_access_fast (cpu_mips_t * cpu, u_int dev_id, m_uint32_t offset,\n    u_int op_size, u_int op_type, m_reg_t * data, m_uint8_t * has_set_value)\n{\n    struct vdevice *dev = cpu->vm->dev_array[dev_id];\n\n    if (unlikely (!dev)) {\n        cpu_log (cpu, \"dev_access_fast\",\n            \"null  handler (dev_id=%u,offset=0x%x)\\n\", dev_id, offset);\n        return NULL;\n    }\n    return (dev->handler (cpu, dev, offset, op_size, op_type, data,\n            has_set_value));\n}\n\nstruct vdevice *dev_lookup (vm_instance_t * vm, m_pa_t phys_addr);\nvoid dev_init (struct vdevice *dev);\nint dev_ram_init (vm_instance_t * vm, char *name, m_pa_t paddr, m_uint32_t len);\nstruct vdevice *dev_create (char *name);\nstruct vdevice *dev_create_ram (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len);\nvoid dev_reset_all (vm_instance_t * vm);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/gdb_interface.c",
    "content": "/*\n * Copyright (C) 1996-1998 by the Board of Trustees\n *    of Leland Stanford Junior University.\n *\n * This file is part of the SimOS distribution.\n * See LICENSE file for terms of the license.\n *\n */\n\n /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n/*GDB interface for virtualmips based on simos*/\n\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <memory.h>\n#include <string.h>\n#include <unistd.h>\n#include <sys/socket.h>\n#include <netinet/in.h>\n#include <netinet/tcp.h>\n#include <sys/signal.h>\n#include <sys/types.h>\n#include <assert.h>\n\n#include \"vm.h\"\n#include \"mips.h\"\n#include \"gdb_interface.h\"\n#include \"utils.h\"\n#include \"debug.h\"\n\n#define GDB_NUM_REGS 72         //general cpu register and cp0 reegister\n#define VCONT \"vCont\"\n#define QSYMBOL \"qSymbol\"\n#define QC \"qC\"\n#define QOFFSETS \"qOffsets\"\n\nint delete_breakpoint (vm_instance_t * vm, m_uint32_t addr, int len)\n{\n    virtual_breakpoint_t *tmp, *prev = 0;\n\n    tmp = vm->breakpoint_head;\n\n    // addr = SIGN_EXTEND(32,addr);\n    while (tmp) {\n        if (tmp->addr == addr) {\n            /*find it */\n            if (prev)\n                prev->next = tmp->next;\n\n            if (vm->breakpoint_head == tmp)\n                vm->breakpoint_head = tmp->next;\n\n            if (vm->breakpoint_tail == tmp)\n                vm->breakpoint_tail = prev;\n\n            if (tmp->save)\n                free (tmp->save);\n            free (tmp);\n\n            goto exit;\n        }\n\n        prev = tmp;\n        tmp = tmp->next;\n    }\n\n  exit:\n    return SUCCESS;\n}\n\nvirtual_breakpoint_t *alloc_breakpoint (vm_instance_t * vm, m_uint32_t addr,\n    char *save, int len)\n{\n    virtual_breakpoint_t *tmp;\n\n    tmp = malloc (sizeof (virtual_breakpoint_t));\n    if (!tmp)\n        return NULL;\n\n    memset (tmp, 0, sizeof (*tmp));\n    tmp->addr = (addr);\n\n    if (save) {\n        tmp->save = malloc (strlen (save) + 1);\n        strlcpy (tmp->save, save, sizeof(tmp->save));\n    }\n    //tmp->cpuno = cpuno;\n    tmp->len = len;\n    tmp->next = 0;\n\n    return tmp;\n}\n\nint insert_breakpoint (vm_instance_t * vm, virtual_breakpoint_t * new)\n{\n    virtual_breakpoint_t *tmp;\n\n    if (vm->breakpoint_head == 0) {\n        vm->breakpoint_tail = vm->breakpoint_head = new;\n    } else {\n        tmp = vm->breakpoint_head;\n\n        while (tmp) {\n            if (tmp->addr == new->addr) {\n                /*the same one */\n                if (new->save)\n                    free (new->save);\n                free (new);\n                goto exit;\n            }\n\n            tmp = tmp->next;\n        }\n\n        vm->breakpoint_tail->next = new;\n        vm->breakpoint_tail = new;\n    }\n\n  exit:\n    return SUCCESS;\n}\n\nstatic int fromhex (int a)\n{\n    if (a >= '0' && a <= '9')\n        return a - '0';\n    else if (a >= 'a' && a <= 'f')\n        return a - 'a' + 10;\n    else {\n        fprintf (stderr, \"Request contains invalid hex digit : %s %d\\n\",\n            __FILE__, __LINE__);\n        return 0;\n    }\n}\n\n/* Convert number NIB to a hex digit.  */\n\nstatic int tohex (int nib)\n{\n    if (nib < 10)\n        return '0' + nib;\n    else\n        return 'a' + nib - 10;\n}\n\n#if 0\nstatic int bin2hex (const char *bin, char *hex, int count)\n{\n    int i;\n    /* May use a length, or a nul-terminated string as input. */\n    if (count == 0)\n        count = strlen (bin);\n\n    for (i = 0; i < count; i++) {\n        *hex++ = tohex ((*bin >> 4) & 0xf);\n        *hex++ = tohex (*bin++ & 0xf);\n    }\n    *hex = 0;\n    return i;\n}\n\n#endif\n\nstatic void convert_int_to_ascii (char *from, char *to, int n)\n{\n    int nib;\n    char ch;\n    while (n--) {\n        ch = *from++;\n        nib = ((ch & 0xf0) >> 4) & 0x0f;\n        *to++ = tohex (nib);\n        nib = ch & 0x0f;\n        *to++ = tohex (nib);\n    }\n    *to++ = 0;\n}\n\n/*****************************************************************\n * readchar\n * Returns next char from remote GDB.  -1 if error.\n *****************************************************************/\nstatic int readchar (int fd)\n{\n    static char buf[BUFSIZ];\n    static int bufcnt = 0;\n    static char *bufp;\n\n    if (bufcnt-- > 0)\n        return *bufp++ & 0x7f;\n\n    bufcnt = read (fd, buf, BUFSIZ);\n    if (bufcnt <= 0) {\n        printf (\"Simdebug readchar\");\n        return -1;\n    }\n\n    bufp = buf;\n    bufcnt--;\n    return *bufp++ & 0x7f;\n}\n\n/*****************************************************************\n * getpkt\n *\n * Read a packet from the remote machine, with error checking,\n * and store it in BUF.  Returns length of packet, or negative if error.\n *****************************************************************/\nstatic int getpkt (int fd, char *buf)\n{\n    char *bp;\n    unsigned char csum, c1, c2;\n    int c;\n\n    bp = buf;\n    while (1) {\n        csum = 0;\n\n        while (1) {\n            c = readchar (fd);\n            if (c == '$')\n                break;\n            if (c < 0)\n                goto errout;\n        }\n\n        bp = buf;\n        while (1) {\n            c = readchar (fd);\n            if (c < 0)\n                goto errout;\n\n            if (c == '#')\n                break;\n\n            *bp++ = c;\n            csum += c;\n        }\n        *bp = 0;\n\n        c = readchar (fd);\n        if (c < 0)\n            goto errout;\n        c1 = fromhex (c);\n\n        c = readchar (fd);\n        if (c < 0)\n            goto errout;\n        c2 = fromhex (c);\n\n        if (csum == (c1 << 4) + c2)\n            break;\n\n        if (write (fd, \"-\", 1) < 0)\n            return -1;\n    }\n\n    if (write (fd, \"+\", 1) < 0)\n        return -1;\n    return bp - buf;\n\n  errout:\n    return -1;\n}\n\nstatic void write_ok (char *buf)\n{\n    buf[0] = 'O';\n    buf[1] = 'K';\n    buf[2] = '\\0';\n}\n\nstatic void write_enn (char *buf)\n{\n    buf[0] = 'E';\n#if 0\n    buf[1] = 'N';\n    buf[2] = 'N';\n#endif\n\n    buf[1] = '0';\n    buf[2] = '1';\n    buf[3] = '\\0';\n}\n\n/* Send a packet to the remote machine, with error checking.\n   The data of the packet is in BUF.  Returns >= 0 on success, -1 otherwise. */\n\nstatic int putpkt (int fd, char *buf)\n{\n    //printf(\"putpkt\\n\");\n    int i;\n    unsigned char csum = 0;\n    char buf2[2000];\n    char buf3[1];\n    int cnt = strlen (buf);\n    char *p;\n\n    /* Copy the packet into buffer BUF2, encapsulating it\n     * and giving it a checksum.  */\n\n    p = buf2;\n    *p++ = '$';\n\n    for (i = 0; i < cnt; i++) {\n        csum += buf[i];\n        *p++ = buf[i];\n    }\n\n    *p++ = '#';\n    *p++ = tohex ((csum >> 4) & 0xf);\n    *p++ = tohex (csum & 0xf);\n\n    /* Send it over and over\u0011\u001b[A until we get a positive ack.  */\n\n    do {\n        int cc;\n\n        if (write (fd, buf2, p - buf2) != p - buf2) {\n            printf (\"putpkt(write)\\n\");\n            goto errout;\n        }\n\n        cc = read (fd, buf3, 1);\n        if (cc <= 0) {\n            printf (\"putpkt(read)\\n\");\n            goto errout;\n        }\n    }\n    while (buf3[0] != '+');\n\n    return 1;                   /* Success! */\n\n  errout:\n    return -1;\n}\n\nstatic void attach_gdb (vm_instance_t * vm)\n{\n    struct sockaddr_in sockaddr1;\n    unsigned int tmp;\n    int gdb_fd;\n\n    if (!vm->gdb_debug_from_poll)\n        printf (\"Waiting for gdb on port %d.\\n\", vm->gdb_port);\n\n    tmp = sizeof (sockaddr1);\n    gdb_fd =\n        accept (vm->gdb_listen_sock, (struct sockaddr *) &sockaddr1, &tmp);\n    vm->gdb_interact_sock = gdb_fd;\n    if (gdb_fd == -1) {\n        printf (\"Debugger accept failed\\n\");\n        return;\n    }\n\n    if (!vm->gdb_debug_from_poll)\n        printf (\"GDB attached. Enjoy yourself!\\n\");\n\n    /* Tell TCP not to delay small packets.  This greatly speeds up\n     * interactive response. */\n\n    tmp = 1;\n    setsockopt (gdb_fd, SOL_SOCKET, SO_KEEPALIVE, (char *) &tmp,\n        sizeof (tmp));\n\n    tmp = 1;\n    setsockopt (gdb_fd, IPPROTO_TCP, TCP_NODELAY, (char *) &tmp,\n        sizeof (tmp));\n\n    // int save_fcntl_flags;\n#if defined(F_SETFL) && defined (FASYNC)\n    save_fcntl_flags = fcntl (gdb_fd, F_GETFL, 0);\n    fcntl (gdb_fd, F_SETFL, save_fcntl_flags | FASYNC);\n#if defined (F_SETOWN)\n    fcntl (gdb_fd, F_SETOWN, getpid ());\n#endif\n#endif\n\n    signal (SIGIO, SIG_IGN);\n\n    // return gdb_fd;\n}\n\n#define MAX_XFER (8*1024)\n#define WORD_SZ  4\n#define BYTE_SZ   1\n\nint debug_read_memory (cpu_mips_t * cpu, m_uint32_t vaddr, unsigned int len,\n    char *buf)\n{\n    //void *haddr=NULL;\n    //m_uint32_t exc;\n    //m_uint32_t data;\n    //m_uint8_t has_set_value=FALSE;\n\n    char readout_buf[MAX_XFER];\n    if (len > MAX_XFER) {\n        fprintf (stderr, \"read_memory: too many bytes requested\");\n    }\n    assert (len <= MAX_XFER);\n\n    int reallen = len;\n    char *cur = readout_buf;\n    int i = 0;\n\n    //We read one byte once to avoid align problem\n    for (i = 0; i < (reallen / BYTE_SZ); i++) {\n        cpu->mips_mts_gdb_lb (cpu, vaddr, cur);\n\n        cur += BYTE_SZ;\n        vaddr += BYTE_SZ;\n    }\n\n    convert_int_to_ascii (readout_buf, buf, len);\n    return SUCCESS;\n\n}\n\nint forced_inline cpu_hit_breakpoint (vm_instance_t * vm, m_uint32_t vaddr)\n{\n    virtual_breakpoint_t *tmp = vm->breakpoint_head;\n    static char cmd_buf[BUFSIZ + 1];\n\n    while (tmp) {\n        if (tmp->addr == vaddr) {\n            snprintf (cmd_buf, sizeof(cmd_buf), \"S%02x\", SIGTRAP);\n            if (putpkt (vm->gdb_interact_sock, cmd_buf) < 0) {\n                /* the connection was terminated prematurely.  Reset */\n                close (vm->gdb_interact_sock);\n                vm->gdb_interact_sock = -1;\n                vm->mipsy_debug_mode = 0;       //we do not debug anymore\n                printf (\"Remote debugger connection lost, continuing...\\n\");\n                return FAILURE;\n            }\n            return SUCCESS;\n        }\n        tmp = tmp->next;\n    }\n    return FAILURE;\n}\n\n/* Convert hex digit A to a number.  */\n\nSimdebug_result Simdebug_run (vm_instance_t * vm, int sig)\n{\n    static char cmd_buf[BUFSIZ + 1];\n    char *b;\n    int i = 0;\n    Simdebug_result ret = SD_CONTINUE;\n\n    if (vm->gdb_interact_sock <= 0) {\n        attach_gdb (vm);\n        if (vm->gdb_interact_sock < 0) {\n            return SD_CONTINUE; /* could not get debugger */\n        }\n        vm->gdb_debug_from_poll = 0;    /* whether or not we entered from poll doesn't\n                                         * matter this time, but we'd better reset it\n                                         * before next time this function runs\n                                         */\n    } else {\n        /* reestablish an old connection.  We might get here either\n         * for internal reasons (hitting a breakpoint) or for external\n         * reasons (gdb sent us a ^C).  If external, we need to swallow\n         * the break packet.  Then in either case, let GDB know why\n         * we stopped.\n         */\n\n        if (vm->gdb_debug_from_poll) {\n            vm->gdb_debug_from_poll = 0;\n            int cc;\n            char c;\n\n            cc = read (vm->gdb_interact_sock, &c, 1);\n\n            if (cc != 1 || c != '\\003') {\n                fprintf (stderr, \"input_interrupt, cc = %d c = %d\\n\", cc, c);\n                goto errout;\n            }\n\n            sig = SIGINT;\n            /* Inform the remote debugger we have entered debugging mode. */\n            // snprintf (cmd_buf, sizeof(cmd_buf), \"S%02x%02x\", sig, debug_cpuno);\n            snprintf (cmd_buf, sizeof(cmd_buf), \"S%02x\", sig);\n            if (putpkt (vm->gdb_interact_sock, cmd_buf) < 0)\n                goto errout;\n\n        }\n    }\n\n    while (1) {\n        char ch;\n        i = 0;\n        int pkg_len = 0;\n\n        if ((pkg_len = getpkt (vm->gdb_interact_sock, cmd_buf)) <= 0)\n            goto errout;\n        ch = cmd_buf[i++];\n        SIM_DEBUG (('g', \"gdb command %c \\n\", ch));\n        //printf(\"---\\n gdb command %s\\n\",cmd_buf);\n\n        switch (ch) {\n        case 'c':\n            ret = SD_CONTINUE;\n            goto out;\n        case 'g':              //read register\n            {\n                m_uint32_t r = 0;\n                b = cmd_buf;\n                for (i = 0; i < GDB_NUM_REGS; i++) {\n                    //FIXME: find the mapping from register index to register of cpu and cpu0 of gdb\n                    if (vm->boot_cpu->reg_get (vm->boot_cpu, i,\n                            &r) == FAILURE)\n                        r = 0;\n                    /*\n                     * flip the bytes around\n                     */\n                    r = htovm32 (r);    //gdb likes the data of target machine format\n                    convert_int_to_ascii ((char *) &r, b, 4);\n\n                    b += 8;\n                }\n                *b = 0;\n                break;\n            }\n\n        case 'H':\n            write_ok (cmd_buf);\n            break;\n        case 'm':\n            {\n                m_uint32_t memaddr;\n                unsigned int len;\n\n                if (sscanf (cmd_buf + 1, \"%x,%x\", &memaddr, &len) != 2) {\n                    write_enn (cmd_buf);\n                } else {\n\n                    if (debug_read_memory (vm->boot_cpu, memaddr, len,\n                            cmd_buf) != SUCCESS)\n                        write_enn (cmd_buf);\n                }\n                break;\n            }\n\n        case 'p':\n            {\n                m_uint32_t r, index = 0;\n                b = cmd_buf;\n                if (sscanf (cmd_buf + 1, \"%x\", &index) != 1)\n                    write_enn (cmd_buf);\n                else {\n                    // index=vmtoh32(index);\n                    if (vm->boot_cpu->reg_get (vm->boot_cpu, index,\n                            &r) == FAILURE)\n                        r = 0;\n                    /*\n                     * flip the bytes around\n                     */\n                    r = htovm32 (r);    //gdb likes the data of target machine format\n                    convert_int_to_ascii ((char *) &r, b, 4);\n                    //*(r+4)=0;\n                    //*(r+5)=0;\n                    //*(r+6)=0;\n                    //*(r+7)=0;\n\n                }\n\n            }\n            break;\n\n        case 'v':\n            {\n                char *cmd_tmp;\n\n                cmd_tmp = cmd_buf;\n\n                if (strncmp (cmd_buf, VCONT, strlen (VCONT)) != 0)\n                    write_enn (cmd_buf);\n                else {\n                    cmd_tmp += strlen (VCONT);\n                    if (';' == cmd_tmp[0]) {\n                        cmd_tmp++;\n                        if ('c' == cmd_tmp[0]) {\n                            ret = SD_CONTINUE;\n                            goto out;\n                        } else if ('s' == cmd_tmp[0]) {\n                            /*single step */\n                            int cpuno;\n                            cpuno = 0;\n\n                            ret = cpuno;\n\n                            goto out;\n                        } else\n                            write_enn (cmd_buf);\n                    } else if ('?' == (cmd_tmp)[0]) {\n                        /*query */\n                        strlcpy (cmd_buf, VCONT \";c\", sizeof(cmd_buf));\n                    } else\n                        write_enn (cmd_buf);\n                }\n            }\n            break;\n\n        case 'q':\n            {\n                if (strncmp (cmd_buf, QSYMBOL, strlen (QSYMBOL)) == 0)\n                    write_ok (cmd_buf);\n                else if (strncmp (cmd_buf, QC, strlen (QC)) == 0) {\n                    strlcpy (cmd_buf, \"QC0\", sizeof(cmd_buf));\n                } else if (strncmp (cmd_buf, QOFFSETS,\n                        strlen (QOFFSETS)) == 0) {\n                    strlcpy (cmd_buf, \"Text=0;Data=0;Bss=0\", sizeof(cmd_buf));\n                } else {\n                    write_enn (cmd_buf);\n                }\n\n            }\n            break;\n\n        case 's':\n        case 'S':\n            ret = SD_NEXTI_ANYCPU;\n            goto out;\n\n        case 'z':\n            {\n                m_uint32_t addr;\n                int len;\n                if ('0' == (cmd_buf + 1)[0]) {\n                    //memory breakpoint\n                    if (sscanf (cmd_buf + 3, \"%x,%x\", &addr, &len) != 2) {\n\n                        write_enn (cmd_buf);\n                    }\n\n                    else {\n                        if (delete_breakpoint (vm, addr, len) != SUCCESS)\n                            write_enn (cmd_buf);\n                        else {\n\n                            write_ok (cmd_buf);\n                        }\n\n                    }\n\n                }\n\n                else\n                    write_enn (cmd_buf);\n\n            }\n            break;\n\n        case 'Z':\n            {\n                m_uint32_t addr;\n                int len;\n                if ('0' == (cmd_buf + 1)[0]) {\n                    //memory breakpoint\n                    if (sscanf (cmd_buf + 3, \"%x,%x\", &addr, &len) != 2) {\n\n                        write_enn (cmd_buf);\n\n                    }\n\n                    else {\n\n                        virtual_breakpoint_t *tmp =\n                            alloc_breakpoint (vm, addr, 0, len);\n                        insert_breakpoint (vm, tmp);\n                        write_ok (cmd_buf);\n\n                    }\n                } else\n                    write_enn (cmd_buf);\n\n            }\n            break;\n        case '?':\n            snprintf (cmd_buf, sizeof(cmd_buf), \"S%02x\", sig);\n            break;\n        default:\n            write_enn (cmd_buf);\n            break;\n\n        }\n        //printf(\"send %s\\n\",cmd_buf);\n        if (putpkt (vm->gdb_interact_sock, cmd_buf) < 0)\n            goto errout;\n\n    }\nout:\n    return ret;\nerrout:\n    /* the connection was terminated prematurely.  Reset */\n    close (vm->gdb_interact_sock);\n    vm->gdb_interact_sock = -1;\n    printf (\"Remote debugger connection lost, continuing...\\n\");\n    return SD_CONTINUE;\n}\n\nvoid bad_memory_access_gdb (vm_instance_t * vm)\n{\n    static char cmd_buf[BUFSIZ + 1];\n\n    vm->mipsy_break_nexti = MIPS_BREAKANYCPU;\n    snprintf (cmd_buf, sizeof(cmd_buf), \"S%02x\", SIGTRAP);\n    if (putpkt (vm->gdb_interact_sock, cmd_buf) < 0) {\n        /* the connection was terminated prematurely.  Reset */\n        close (vm->gdb_interact_sock);\n        vm->gdb_interact_sock = -1;\n        vm->mipsy_debug_mode = 0;       //we do not debug anymore\n        printf (\"Remote debugger connection lost, continuing...\\n\");\n    }\n}\n"
  },
  {
    "path": "tools/virtualmips/gdb_interface.h",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#ifndef  __GDB_INTERFACE_H__\n#define  __GDB_INTERFACE_H__\n#include \"utils.h\"\n#include \"mips.h\"\n\ntypedef enum Simdebug_result {\n    SD_CONTINUE = -2,\n    SD_NEXTI_ANYCPU = -1\n} Simdebug_result;\n\ntypedef struct virtualBreakpoint {\n    m_uint32_t addr;\n    char *save;\n    //int cpuno;\n    int len;                    /*break point instruction len */\n    struct virtualBreakpoint *next;\n} virtual_breakpoint_t;\n\nint cpu_hit_breakpoint (vm_instance_t * vm, m_uint32_t vaddr);\n\nSimdebug_result Simdebug_run (vm_instance_t * vm, int sig);\nvoid bad_memory_access_gdb (vm_instance_t * vm);\n#endif\n"
  },
  {
    "path": "tools/virtualmips/jz4740/jz4740.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#include<string.h>\n#include <assert.h>\n#include<stdlib.h>\n#include <confuse.h>\n\n#include \"utils.h\"\n#include \"mips.h\"\n#include \"vm.h\"\n#include \"cpu.h\"\n#include \"mips_exec.h\"\n#include \"debug.h\"\n\n#include \"jz4740.h\"\n#include \"pavo.h\"\n#include \"device.h\"\n\nint jz4740_boot_from_nandflash (vm_instance_t * vm)\n{\n    struct vdevice *dev;\n    unsigned char *page_addr;\n    int i;\n\n    pavo_t *pavo;\n    if (vm->type == VM_TYPE_PAVO) {\n        pavo = VM_PAVO (vm);\n    } else\n        ASSERT (0, \"Error vm type\\n\");\n\n    /*get ram device */\n    dev = dev_lookup (vm, 0x0);\n    assert (dev != NULL);\n    assert (dev->host_addr != 0);\n    /*copy 8K nand flash data to 8K RAM */\n    for (i = 0; i < (0x2000 / NAND_FLASH_1G_PAGE_DATA_SIZE); i++) {\n        page_addr =\n            get_nand_flash_page_ptr (i, pavo->nand_flash->flash_map[0]);\n        memcpy ((unsigned char *) dev->host_addr +\n            NAND_FLASH_1G_PAGE_DATA_SIZE * i, page_addr,\n            NAND_FLASH_1G_PAGE_DATA_SIZE);\n    }\n\n    return (0);\n\n}\n\nint jz4740_reset (vm_instance_t * vm)\n{\n    cpu_mips_t *cpu;\n    m_va_t kernel_entry_point;\n    vm_suspend (vm);\n    /* Check that CPU activity is really suspended */\n    if (cpu_group_sync_state (vm->cpu_group) == -1) {\n        vm_error (vm, \"unable to sync with system CPUs.\\n\");\n        return (-1);\n    }\n\n    /* Reset the boot CPU */\n    cpu = (vm->boot_cpu);\n    mips_reset (cpu);\n\n    /*set configure register */\n    cpu->cp0.config_usable = 0x83;      /* configure sel 0 1 7 is valid */\n    cpu->cp0.config_reg[0] = JZ4740_CONFIG0;\n    cpu->cp0.config_reg[1] = JZ4740_CONFIG1;\n    cpu->cp0.config_reg[7] = JZ4740_CONFIG7;\n\n    /*set PC and PRID */\n    cpu->cp0.reg[MIPS_CP0_PRID] = JZ4740_PRID;\n    cpu->cp0.tlb_entries = JZ4740_DEFAULT_TLB_ENTRYNO;\n    cpu->pc = JZ4740_ROM_PC;\n    /*reset all devices */\n    dev_reset_all (vm);\n\n#ifdef _USE_JIT_\n    /*if jit is used. flush all jit buffer */\n    if (vm->jit_use)\n        mips_jit_flush (cpu, 0);\n#endif\n    /*If we boot from elf kernel image, load the image and set pc to elf entry */\n    if (vm->boot_method == BOOT_ELF) {\n        if (mips_load_elf_image (cpu, vm->kernel_filename,\n                &kernel_entry_point) == -1)\n            return (-1);\n        cpu->pc = kernel_entry_point;\n    } else if (vm->boot_method == BOOT_BINARY) {\n        if (jz4740_boot_from_nandflash (vm) == -1)\n            return (-1);\n    }\n\n/* Launch the simulation */\n    printf (\"VM '%s': starting simulation (CPU0 PC=0x%\" LL\n        \"x), JIT %sabled.\\n\", vm->name, cpu->pc, vm->jit_use ? \"en\" : \"dis\");\n    vm->status = VM_STATUS_RUNNING;\n    cpu_start (vm->boot_cpu);\n    return (0);\n\n}\n"
  },
  {
    "path": "tools/virtualmips/jz4740/jz4740.h",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *     \n  * This file is part of the virtualmips distribution. \n  * See LICENSE file for terms of the license. \n  *\n  */\n\n /*JZ4740 Header file */\n\n#ifndef __JZ4740_H__\n#define __JZ4740_H__\n\n#include \"types.h\"\n\n/*virtual address and physical address*/\ntypedef m_uint32_t m_va_t;\ntypedef m_uint32_t m_pa_t;\ntypedef m_uint32_t m_reg_t;\ntypedef m_int32_t m_ireg_t;\ntypedef m_uint32_t m_cp0_reg_t;\n\n#define  DATA_WIDTH 32          /*64 */\n#define LL\n\n/*JZ4740 use soft fpu*/\n#define SOFT_FPU   1\n\n/*Guest endian*/\n#define GUEST_BYTE_ORDER  ARCH_LITTLE_ENDIAN\n#ifndef GUEST_BYTE_ORDER\n#error Please define guest architecture in utils.h!\n#endif\n\n/* Host to VM conversion functions */\n#if HOST_BYTE_ORDER == GUEST_BYTE_ORDER\n#define htovm16(x) (x)\n#define htovm32(x) (x)\n#define htovm64(x) (x)\n\n#define vmtoh16(x) (x)\n#define vmtoh32(x) (x)\n#define vmtoh64(x) (x)\n#elif HOST_BYTE_ORDER==ARCH_LITTLE_ENDIAN       //host:little guest:big\n#define htovm16(x) (htons(x))\n#define htovm32(x) (htonl(x))\n#define htovm64(x) (swap64(x))\n\n#define vmtoh16(x) (ntohs(x))\n#define vmtoh32(x) (ntohl(x))\n#define vmtoh64(x) (swap64(x))\n#else //host:big guest:little\n\n#define htovm16(x) (ntohs(x))\n#define htovm32(x) (ntohl(x))\n#define htovm64(x) (swap64(x))\n\n#define vmtoh16(x) (htons(x))\n#define vmtoh32(x) (htonl(x))\n#define vmtoh64(x) (swap64(x))\n#endif\n\n#define JZ4740_CONFIG0  0x80000082\n#define JZ4740_CONFIG1 0x3E613080       /*CACHE (128SET*32 BYTES*2 WAY)= 8K */\n#define JZ4740_CONFIG7 0x0\n\n#define JZ4740_ROM_PC  0x80000004\n#define JZ4740_PRID    0x0ad0024f       /*jz4740 prid */\n#define JZ4740_DEFAULT_TLB_ENTRYNO   32 /*32 pairs */\n\n/*------------------------REG DEFINE---------------------------------*/\n#define NAND_DATAPORT\t0x18000000\n#define NAND_ADDRPORT\t0x18010000\n#define NAND_COMMPORT\t0x18008000\n\n/*FOR CS8900*/\n#define CS8900_IO_BASE  0x8000000\n#define CS8900_SIZE         0x10\n#define CS8900_DEFAULT_IRQ      107\n#define CS8900_GPIO_GROUP      1\n/* GPIO is in 4 groups. 32 per group*/\n/*\n\n48-79      0\n80-111    1\n112-143  2\n144-175  3\n\nso irq 107 is in gpio group 1\n*/\n\n/*---------------------GPIO----------------------------------*/\n#define JZ4740_GPIO_BASE       0x10010000\n#define JZ4740_GPIO_SIZE       0x388\n//n = 0,1,2,3\n#define GPIO_PXPIN(n)\t( (0x00 + (n)*0x100))   /* PIN Level Register */\n#define GPIO_PXDAT(n)\t((0x10 + (n)*0x100))    /* Port Data Register */\n#define GPIO_PXDATS(n)\t( (0x14 + (n)*0x100))   /* Port Data Set Register */\n#define GPIO_PXDATC(n)\t( (0x18 + (n)*0x100))   /* Port Data Clear Register */\n#define GPIO_PXIM(n)\t( (0x20 + (n)*0x100))   /* Interrupt Mask Register */\n#define GPIO_PXIMS(n)\t( (0x24 + (n)*0x100))   /* Interrupt Mask Set Reg */\n#define GPIO_PXIMC(n)\t( (0x28 + (n)*0x100))   /* Interrupt Mask Clear Reg */\n#define GPIO_PXPE(n)\t((0x30 + (n)*0x100))    /* Pull Enable Register */\n#define GPIO_PXPES(n)\t( (0x34 + (n)*0x100))   /* Pull Enable Set Reg. */\n#define GPIO_PXPEC(n)\t( (0x38 + (n)*0x100))   /* Pull Enable Clear Reg. */\n#define GPIO_PXFUN(n)\t( (0x40 + (n)*0x100))   /* Function Register */\n#define GPIO_PXFUNS(n)\t( (0x44 + (n)*0x100))   /* Function Set Register */\n#define GPIO_PXFUNC(n)\t( (0x48 + (n)*0x100))   /* Function Clear Register */\n#define GPIO_PXSEL(n)\t( (0x50 + (n)*0x100))   /* Select Register */\n#define GPIO_PXSELS(n)\t( (0x54 + (n)*0x100))   /* Select Set Register */\n#define GPIO_PXSELC(n)\t( (0x58 + (n)*0x100))   /* Select Clear Register */\n#define GPIO_PXDIR(n)\t( (0x60 + (n)*0x100))   /* Direction Register */\n#define GPIO_PXDIRS(n)\t( (0x64 + (n)*0x100))   /* Direction Set Register */\n#define GPIO_PXDIRC(n)\t( (0x68 + (n)*0x100))   /* Direction Clear Register */\n#define GPIO_PXTRG(n)\t( (0x70 + (n)*0x100))   /* Trigger Register */\n#define GPIO_PXTRGS(n)\t( (0x74 + (n)*0x100))   /* Trigger Set Register */\n#define GPIO_PXTRGC(n)\t( (0x78 + (n)*0x100))   /* Trigger Set Register */\n#define GPIO_PXFLG(n)\t( (0x80 + (n)*0x100))   /* Port Flag Register */\n/* According to datasheet, it is 0x14. I think it shoud be 0x84*/\n#define GPIO_PXFLGC(n)\t( (0x84 + (n)*0x100))   /* Port Flag clear Register */\n\n#define JZ4740_GPIO_INDEX_MAX  0xe2     /*0x388/4 */\n\n/*---------------------UART----------------------------------*/\n\n#define JZ4740_UART_SIZE       0x302c\n\n#define JZ4740_UART0_BASE       0x10030000\n#define JZ4740_UART0_SIZE       0x2c\n\n#define JZ4740_UART1_BASE       0x10031000\n#define JZ4740_UART1_SIZE       0x2c\n#define JZ4740_UART2_BASE       0x10032000\n#define JZ4740_UART2_SIZE       0x2c\n#define JZ4740_UART3_BASE       0x10033000\n#define JZ4740_UART3_SIZE       0x2c\n\n#define JZ4740_UART_BASE       JZ4740_UART0_BASE\n\n#define UART_RBR         (0x00)\n#define UART_THR         (0x00)\n#define UART_DLLR        (0x00)\n#define UART_DLHR        (0x04)\n#define UART_IER         (0x04)\n#define UART_IIR         (0x08)\n#define UART_FCR         (0x08)\n#define UART_LCR         (0x0C)\n#define UART_MCR         (0x10)\n#define UART_LSR         (0x14)\n#define UART_MSR         (0x18)\n#define UART_SPR         (0x1C)\n#define UART_ISR         (0x20)\n#define UART_UMR         (0x24)\n#define UART_UACR        (0x28)\n\n#define JZ4740_UART_INDEX_MAX\t\t\t\t\t\t\t0xb     //0x02c/4\n#define JZ4740_UART_NUMBER                            2 //we emulates two uarts\n\n#define UART_IER_RDRIE      0x01\n#define UART_IER_TDRIE      0x02\n#define UART_IER_RLSIE      0x04\n#define UART_IER_MSIE      0x08\n#define UART_IER_RTOIE      0x10\n\n#define UART_FCR_FME   0x1\n#define UART_FCR_RFRT   0x2\n#define UART_FCR_TFRT   0x4\n#define UART_FCR_DME   0x8\n#define UART_FCR_UME   0x10\n#define UART_FCR_RDTR   0xC0\n#define UART_FCR_RDTR_SHIFT   0x6\n\n#define UART_LSR_DRY   0x1\n#define UART_LSR_OVER   0x2\n#define UART_LSR_PARER   0x4\n#define UART_LSR_FMER   0x8\n#define UART_LSR_BI   0x10\n#define UART_LSR_TDRQ   0x20\n#define UART_LSR_TEMP   0x40\n#define UART_LSR_FIFOE   0x80\n\n/*-------------------PLL----------------------*/\n\n#define JZ4740_CPM_BASE 0x10000000\n#define JZ4740_CPM_SIZE 0X70\n\n#define CPM_CPCCR       (0x00)\n#define CPM_CPPCR       (0x10)\n#define CPM_I2SCDR      (0x60)\n#define CPM_LPCDR       (0x64)\n#define CPM_MSCCDR      (0x68)\n#define CPM_UHCCDR      (0x6C)\n\n#define CPM_LCR         (0x04)\n#define CPM_CLKGR       (0x20)\n#define CPM_SCR         (0x24)\n\n#define CPM_HCR         (0x30)\n#define CPM_HWFCR       (0x34)\n#define CPM_HRCR        (0x38)\n#define CPM_HWCR        (0x3c)\n#define CPM_HWSR        (0x40)\n#define CPM_HSPR        (0x44)\n\n#define JZ4740_CPM_INDEX_MAX 0X1c       /*0X70/4 */\n\n/*-------------------EMC----------------------*/\n#define JZ4740_EMC_BASE 0x13010000\n#define JZ4740_EMC_SIZE 0xa400  /*FROM A000-A3FF is mode register */\n\n#define EMC_BCR         ( 0x0)  /* BCR */\n#define EMC_SMCR0       ( 0x10) /* Static Memory Control Register 0 */\n#define EMC_SMCR1       ( 0x14) /* Static Memory Control Register 1 */\n#define EMC_SMCR2       ( 0x18) /* Static Memory Control Register 2 */\n#define EMC_SMCR3       ( 0x1c) /* Static Memory Control Register 3 */\n#define EMC_SMCR4       ( 0x20) /* Static Memory Control Register 4 */\n#define EMC_SACR0       ( 0x30) /* Static Memory Bank 0 Addr Config Reg */\n#define EMC_SACR1       ( 0x34) /* Static Memory Bank 1 Addr Config Reg */\n#define EMC_SACR2       ( 0x38) /* Static Memory Bank 2 Addr Config Reg */\n#define EMC_SACR3       ( 0x3c) /* Static Memory Bank 3 Addr Config Reg */\n#define EMC_SACR4       ( 0x40) /* Static Memory Bank 4 Addr Config Reg */\n\n#define EMC_NFCSR       ( 0x050)        /* NAND Flash Control/Status Register */\n#define EMC_NFECR       ( 0x100)        /* NAND Flash ECC Control Register */\n#define EMC_NFECC       ( 0x104)        /* NAND Flash ECC Data Register */\n#define EMC_NFPAR0      ( 0x108)        /* NAND Flash RS Parity 0 Register */\n#define EMC_NFPAR1      ( 0x10c)        /* NAND Flash RS Parity 1 Register */\n#define EMC_NFPAR2      ( 0x110)        /* NAND Flash RS Parity 2 Register */\n#define EMC_NFINTS      ( 0x114)        /* NAND Flash Interrupt Status Register */\n#define EMC_NFINTE      ( 0x118)        /* NAND Flash Interrupt Enable Register */\n#define EMC_NFERR0      ( 0x11c)        /* NAND Flash RS Error Report 0 Register */\n#define EMC_NFERR1      ( 0x120)        /* NAND Flash RS Error Report 1 Register */\n#define EMC_NFERR2      ( 0x124)        /* NAND Flash RS Error Report 2 Register */\n#define EMC_NFERR3      ( 0x128)        /* NAND Flash RS Error Report 3 Register */\n\n#define EMC_DMCR        ( 0x80) /* DRAM Control Register */\n#define EMC_RTCSR       ( 0x84) /* Refresh Time Control/Status Register */\n#define EMC_RTCNT       ( 0x88) /* Refresh Timer Counter */\n#define EMC_RTCOR       ( 0x8c) /* Refresh Time Constant Register */\n#define EMC_DMAR0       ( 0x90) /* SDRAM Bank 0 Addr Config Register */\n\n#define EMC_SDMR0       ( 0xa000)       /* Mode Register of SDRAM bank 0 */\n/*has other register*/\n\n#define JZ4740_EMC_INDEX_MAX 0x4b       /*0x12c/4 */\n\n/*-----------------------RTC-------------------------------------*/\n\n#define JZ4740_RTC_BASE 0x10003000\n#define JZ4740_RTC_SIZE  0x38\n#define RTC_RCR         ( 0x00) /* RTC Control Register */\n#define RTC_RSR         ( 0x04) /* RTC Second Register */\n#define RTC_RSAR        ( 0x08) /* RTC Second Alarm Register */\n#define RTC_RGR         ( 0x0c) /* RTC Regulator Register */\n\n#define RTC_HCR         ( 0x20) /* Hibernate Control Register */\n#define RTC_HWFCR       ( 0x24) /* Hibernate Wakeup Filter Counter Reg */\n#define RTC_HRCR        ( 0x28) /* Hibernate Reset Counter Register */\n#define RTC_HWCR        ( 0x2c) /* Hibernate Wakeup Control Register */\n#define RTC_HWRSR       ( 0x30) /* Hibernate Wakeup Status Register */\n#define RTC_HSPR        ( 0x34) /* Hibernate Scratch Pattern Register */\n\n#define RTC_RCR_WRDY_BIT 7\n#define RTC_RCR_WRDY    (1 << 7)        /* Write Ready Flag */\n#define RTC_RCR_1HZ_BIT 6\n#define RTC_RCR_1HZ     (1 << RTC_RCR_1HZ_BIT)  /* 1Hz Flag */\n#define RTC_RCR_1HZIE   (1 << 5)        /* 1Hz Interrupt Enable */\n#define RTC_RCR_AF_BIT  4\n#define RTC_RCR_AF      (1 << RTC_RCR_AF_BIT)   /* Alarm Flag */\n#define RTC_RCR_AIE     (1 << 3)        /* Alarm Interrupt Enable */\n#define RTC_RCR_AE      (1 << 2)        /* Alarm Enable */\n#define RTC_RCR_RTCE    (1 << 0)        /* RTC Enable */\n\n /* RTC Regulator Register */\n#define RTC_RGR_LOCK            (1 << 31)       /* Lock Bit */\n#define RTC_RGR_ADJC_BIT        16\n#define RTC_RGR_ADJC_MASK       (0x3ff << RTC_RGR_ADJC_BIT)\n#define RTC_RGR_NC1HZ_BIT       0\n#define RTC_RGR_NC1HZ_MASK      (0xffff << RTC_RGR_NC1HZ_BIT)\n\n /* Hibernate Control Register */\n#define RTC_HCR_PD              (1 << 0)        /* Power Down */\n\n /* Hibernate Wakeup Filter Counter Register */\n#define RTC_HWFCR_BIT           5\n#define RTC_HWFCR_MASK          (0x7ff << RTC_HWFCR_BIT)\n\n /* Hibernate Reset Counter Register */\n#define RTC_HRCR_BIT            5\n#define RTC_HRCR_MASK           (0x7f << RTC_HRCR_BIT)\n\n /* Hibernate Wakeup Control Register */\n#define RTC_HWCR_EALM           (1 << 0)        /* RTC alarm wakeup enable */\n\n /* Hibernate Wakeup Status Register */\n#define RTC_HWRSR_HR            (1 << 5)        /* Hibernate reset */\n#define RTC_HWRSR_PPR           (1 << 4)        /* PPR reset */\n#define RTC_HWRSR_PIN           (1 << 1)        /* Wakeup pin status bit */\n#define RTC_HWRSR_ALM           (1 << 0)        /* RTC alarm status bit */\n\n#define JZ4740_RTC_INDEX_MAX 0xe        /*0x38/4 */\n\n/*----------------------WDT&TCU--------------------------------*/\n#define JZ4740_WDT_TCU_BASE 0x10002000\n#define JZ4740_WDT_TCU_SIZE  0xa0\n\n#define WDT_TDR         ( 0x00)\n#define WDT_TCER        ( 0x04)\n#define WDT_TCNT        ( 0x08)\n#define WDT_TCSR        ( 0x0C)\n\n#define TCU_CLOCK_EXT  0x4\n#define TCU_CLOCK_RTC  0x2\n#define TCU_CLOCK_PCK  0x0\n#define TCU_CLOCK_SOUCE_MASK  0x7\n\n#define TCU_CLOCK_PRESCALE_MASK  0x38\n#define TCU_CLOCK_PRESCALE_OFFSET  0x3\n\n#define WDT_CLOCK_EXT  0x4\n#define WDT_CLOCK_RTC  0x2\n#define WDT_CLOCK_PCK  0x0\n#define WDT_CLOCK_SOUCE_MASK  0x7\n\n#define WDT_CLOCK_PRESCALE_MASK  0x38\n#define WDT_CLOCK_PRESCALE_OFFSET  0x3\n\n#define EXT_CLOCK  12000000     /*12M */\n#define RTC_CLOCK       32768\n\n/*************************************************************************\n * TCU (Timer Counter Unit)\n *************************************************************************/\n#define TCU_TSR\t\t( 0x1C) /* Timer Stop Register */\n#define TCU_TSSR\t( 0x2C) /* Timer Stop Set Register */\n#define TCU_TSCR\t( 0x3C) /* Timer Stop Clear Register */\n#define TCU_TER\t\t( 0x10) /* Timer Counter Enable Register */\n#define TCU_TESR\t( 0x14) /* Timer Counter Enable Set Register */\n#define TCU_TECR\t( 0x18) /* Timer Counter Enable Clear Register */\n#define TCU_TFR\t\t( 0x20) /* Timer Flag Register */\n#define TCU_TFSR\t( 0x24) /* Timer Flag Set Register */\n#define TCU_TFCR\t( 0x28) /* Timer Flag Clear Register */\n#define TCU_TMR\t\t( 0x30) /* Timer Mask Register */\n#define TCU_TMSR\t( 0x34) /* Timer Mask Set Register */\n#define TCU_TMCR\t( 0x38) /* Timer Mask Clear Register */\n#define TCU_TDFR0\t( 0x40) /* Timer Data Full Register */\n#define TCU_TDHR0\t( 0x44) /* Timer Data Half Register */\n#define TCU_TCNT0\t( 0x48) /* Timer Counter Register */\n#define TCU_TCSR0\t( 0x4C) /* Timer Control Register */\n#define TCU_TDFR1\t( 0x50)\n#define TCU_TDHR1\t( 0x54)\n#define TCU_TCNT1\t( 0x58)\n#define TCU_TCSR1\t( 0x5C)\n#define TCU_TDFR2\t (0x60)\n#define TCU_TDHR2\t( 0x64)\n#define TCU_TCNT2\t( 0x68)\n#define TCU_TCSR2\t( 0x6C)\n#define TCU_TDFR3\t( 0x70)\n#define TCU_TDHR3\t( 0x74)\n#define TCU_TCNT3\t( 0x78)\n#define TCU_TCSR3\t( 0x7C)\n#define TCU_TDFR4\t( 0x80)\n#define TCU_TDHR4\t( 0x84)\n#define TCU_TCNT4\t( 0x88)\n#define TCU_TCSR4\t( 0x8C)\n#define TCU_TDFR5\t( 0x90)\n#define TCU_TDHR5\t( 0x94)\n#define TCU_TCNT5\t( 0x98)\n#define TCU_TCSR5\t( 0x9C)\n\n#define TCU_TDFR(n)   (TCU_TDFR0+n*0x10)\n#define TCU_TDHR(n)   (TCU_TDHR0+n*0x10)\n#define TCU_TCNT(n)   (TCU_TCNT0+n*0x10)\n#define TCU_TCSR(n)   (TCU_TCSR0+n*0x10)\n\n#define  WDT_TIMER_STOP  0x10000\n#define JZ4740_WDT_INDEX_MAX 0x28       /*0xa0/4 */\n\n/*-------------------LCD---------------------*/\n#define JZ4740_LCD_BASE 0x13050000\n#define JZ4740_LCD_SIZE  0x60\n\n#define LCD_CFG         ( 0x00) /* LCD Configure Register */\n#define LCD_VSYNC       ( 0x04) /* Vertical Synchronize Register */\n#define LCD_HSYNC       ( 0x08) /* Horizontal Synchronize Register */\n#define LCD_VAT         ( 0x0c) /* Virtual Area Setting Register */\n#define LCD_DAH         ( 0x10) /* Display Area Horizontal Start/End Point */\n#define LCD_DAV         ( 0x14) /* Display Area Vertical Start/End Point */\n#define LCD_PS          ( 0x18) /* PS Signal Setting */\n#define LCD_CLS         ( 0x1c) /* CLS Signal Setting */\n#define LCD_SPL         ( 0x20) /* SPL Signal Setting */\n#define LCD_REV         ( 0x24) /* REV Signal Setting */\n#define LCD_CTRL        ( 0x30) /* LCD Control Register */\n#define LCD_STATE       ( 0x34) /* LCD Status Register */\n#define LCD_IID         ( 0x38) /* Interrupt ID Register */\n#define LCD_DA0         ( 0x40) /* Descriptor Address Register 0 */\n#define LCD_SA0         ( 0x44) /* Source Address Register 0 */\n#define LCD_FID0        ( 0x48) /* Frame ID Register 0 */\n#define LCD_CMD0        ( 0x4c) /* DMA Command Register 0 */\n#define LCD_DA1         ( 0x50) /* Descriptor Address Register 1 */\n#define LCD_SA1         ( 0x54) /* Source Address Register 1 */\n#define LCD_FID1        ( 0x58) /* Frame ID Register 1 */\n#define LCD_CMD1        ( 0x5c) /* DMA Command Register 1 */\n\n#define LCD_CTRL_BST_BIT        28      /* Burst Length Selection */\n#define LCD_CTRL_BST_MASK       (0x03 << LCD_CTRL_BST_BIT)\n#define LCD_CTRL_BST_4        (0 << LCD_CTRL_BST_BIT)   /* 4-word */\n#define LCD_CTRL_BST_8        (1 << LCD_CTRL_BST_BIT)   /* 8-word */\n#define LCD_CTRL_BST_16       (2 << LCD_CTRL_BST_BIT)   /* 16-word */\n#define LCD_CTRL_RGB565         (0 << 27)       /* RGB565 mode */\n#define LCD_CTRL_RGB555         (1 << 27)       /* RGB555 mode */\n#define LCD_CTRL_OFUP           (1 << 26)       /* Output FIFO underrun protection enable */\n#define LCD_CTRL_FRC_BIT        24      /* STN FRC Algorithm Selection */\n#define LCD_CTRL_FRC_MASK       (0x03 << LCD_CTRL_FRC_BIT)\n#define LCD_CTRL_FRC_16       (0 << LCD_CTRL_FRC_BIT)   /* 16 grayscale */\n#define LCD_CTRL_FRC_4        (1 << LCD_CTRL_FRC_BIT)   /* 4 grayscale */\n#define LCD_CTRL_FRC_2        (2 << LCD_CTRL_FRC_BIT)   /* 2 grayscale */\n#define LCD_CTRL_PDD_BIT        16      /* Load Palette Delay Counter */\n#define LCD_CTRL_PDD_MASK       (0xff << LCD_CTRL_PDD_BIT)\n#define LCD_CTRL_EOFM           (1 << 13)       /* EOF interrupt mask */\n#define LCD_CTRL_SOFM           (1 << 12)       /* SOF interrupt mask */\n#define LCD_CTRL_OFUM           (1 << 11)       /* Output FIFO underrun interrupt mask */\n#define LCD_CTRL_IFUM0          (1 << 10)       /* Input FIFO 0 underrun interrupt mask */\n#define LCD_CTRL_IFUM1          (1 << 9)        /* Input FIFO 1 underrun interrupt mask */\n#define LCD_CTRL_LDDM           (1 << 8)        /* LCD disable done interrupt mask */\n#define LCD_CTRL_QDM            (1 << 7)        /* LCD quick disable done interrupt mask */\n#define LCD_CTRL_BEDN           (1 << 6)        /* Endian selection */\n#define LCD_CTRL_PEDN           (1 << 5)        /* Endian in byte:0-msb first, 1-lsb first */\n#define LCD_CTRL_DIS            (1 << 4)        /* Disable indicate bit */\n#define LCD_CTRL_ENA            (1 << 3)        /* LCD enable bit */\n#define LCD_CTRL_BPP_BIT        0       /* Bits Per Pixel */\n#define LCD_CTRL_BPP_MASK       (0x07 << LCD_CTRL_BPP_BIT)\n#define LCD_CTRL_BPP_1        (0 << LCD_CTRL_BPP_BIT)   /* 1 bpp */\n#define LCD_CTRL_BPP_2        (1 << LCD_CTRL_BPP_BIT)   /* 2 bpp */\n#define LCD_CTRL_BPP_4        (2 << LCD_CTRL_BPP_BIT)   /* 4 bpp */\n#define LCD_CTRL_BPP_8        (3 << LCD_CTRL_BPP_BIT)   /* 8 bpp */\n#define LCD_CTRL_BPP_16       (4 << LCD_CTRL_BPP_BIT)   /* 15/16 bpp */\n#define LCD_CTRL_BPP_18_24    (5 << LCD_CTRL_BPP_BIT)   /* 18/24/32 bpp */\n\n /* Display Area Horizontal Start/End Point Register */\n#define LCD_DAH_HDS_BIT         16      /* Horizontal display area start in dot clock */\n#define LCD_DAH_HDS_MASK        (0xffff << LCD_DAH_HDS_BIT)\n#define LCD_DAH_HDE_BIT         0       /* Horizontal display area end in dot clock */\n#define LCD_DAH_HDE_MASK        (0xffff << LCD_DAH_HDE_BIT)\n\n /* Display Area Vertical Start/End Point Register */\n#define LCD_DAV_VDS_BIT         16      /* Vertical display area start in line clock */\n#define LCD_DAV_VDS_MASK        (0xffff << LCD_DAV_VDS_BIT)\n#define LCD_DAV_VDE_BIT         0       /* Vertical display area end in line clock */\n#define LCD_DAV_VDE_MASK        (0xffff << LCD_DAV_VDE_BIT)\n\n#define LCD_STATE_QD            (1 << 7)        /* Quick Disable Done */\n#define LCD_STATE_EOF           (1 << 5)        /* EOF Flag */\n#define LCD_STATE_SOF           (1 << 4)        /* SOF Flag */\n#define LCD_STATE_OFU           (1 << 3)        /* Output FIFO Underrun */\n#define LCD_STATE_IFU0          (1 << 2)        /* Input FIFO 0 Underrun */\n#define LCD_STATE_IFU1          (1 << 1)        /* Input FIFO 1 Underrun */\n#define LCD_STATE_LDD           (1 << 0)        /* LCD Disabled */\n\n#define LCD_CMD_SOFINT          (1 << 31)\n#define LCD_CMD_EOFINT          (1 << 30)\n#define LCD_CMD_PAL             (1 << 28)\n#define LCD_CMD_LEN_BIT         0\n#define LCD_CMD_LEN_MASK        (0xffffff << LCD_CMD_LEN_BIT)\n\n#define JZ4740_LCD_INDEX_MAX 0x18       /*0x60/4 */\n\n/*---------------------touch screen------------------*/\n#define JZ4740_TS_BASE 0x10070000\n#define JZ4740_TS_SIZE  0x28\n\n#define SADC_ENA        ( 0x00) /* ADC Enable Register */\n#define SADC_CFG        ( 0x04) /* ADC Configure Register */\n#define SADC_CTRL       ( 0x08) /* ADC Control Register */\n#define SADC_STATE      ( 0x0C) /* ADC Status Register */\n#define SADC_SAMETIME   ( 0x10) /* ADC Same Point Time Register */\n#define SADC_WAITTIME   ( 0x14) /* ADC Wait Time Register */\n#define SADC_TSDAT      ( 0x18) /* ADC Touch Screen Data Register */\n#define SADC_BATDAT     ( 0x1C) /* ADC PBAT Data Register */\n#define SADC_SADDAT     ( 0x20) /* ADC SADCIN Data Register */\n\n /* ADC Enable Register */\n#define SADC_ENA_ADEN           (1 << 7)        /* Touch Screen Enable */\n#define SADC_ENA_TSEN           (1 << 2)        /* Touch Screen Enable */\n#define SADC_ENA_PBATEN         (1 << 1)        /* PBAT Enable */\n#define SADC_ENA_SADCINEN       (1 << 0)        /* SADCIN Enable */\n\n /* ADC Configure Register */\n#define SADC_CFG_EXIN           (1 << 30)\n#define SADC_CFG_CLKOUT_NUM_BIT 16\n#define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT)\n#define SADC_CFG_TS_DMA         (1 << 15)       /* Touch Screen DMA Enable */\n#define SADC_CFG_XYZ_BIT        13      /* XYZ selection */\n#define SADC_CFG_XYZ_MASK       (0x3 << SADC_CFG_XYZ_BIT)\n#define SADC_CFG_XY           (0 << SADC_CFG_XYZ_BIT)\n#define SADC_CFG_XYZ          (1 << SADC_CFG_XYZ_BIT)\n#define SADC_CFG_XYZ1Z2       (2 << SADC_CFG_XYZ_BIT)\n#define SADC_CFG_SNUM_BIT       10      /* Sample Number */\n#define SADC_CFG_SNUM_MASK      (0x7 << SADC_CFG_SNUM_BIT)\n#define SADC_CFG_SNUM_1       (0x0 << SADC_CFG_SNUM_BIT)\n#define SADC_CFG_SNUM_2       (0x1 << SADC_CFG_SNUM_BIT)\n#define SADC_CFG_SNUM_3       (0x2 << SADC_CFG_SNUM_BIT)\n#define SADC_CFG_SNUM_4       (0x3 << SADC_CFG_SNUM_BIT)\n#define SADC_CFG_SNUM_5       (0x4 << SADC_CFG_SNUM_BIT)\n#define SADC_CFG_SNUM_6       (0x5 << SADC_CFG_SNUM_BIT)\n#define SADC_CFG_SNUM_8       (0x6 << SADC_CFG_SNUM_BIT)\n#define SADC_CFG_SNUM_9       (0x7 << SADC_CFG_SNUM_BIT)\n#define SADC_CFG_CLKDIV_BIT     5       /* AD Converter frequency clock divider */\n#define SADC_CFG_CLKDIV_MASK    (0x1f << SADC_CFG_CLKDIV_BIT)\n#define SADC_CFG_PBAT_HIGH      (0 << 4)        /* PBAT >= 2.5V */\n#define SADC_CFG_PBAT_LOW       (1 << 4)        /* PBAT < 2.5V */\n#define SADC_CFG_CMD_BIT        0       /* ADC Command */\n#define SADC_CFG_CMD_MASK       (0xf << SADC_CFG_CMD_BIT)\n#define SADC_CFG_CMD_X_SE     (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */\n#define SADC_CFG_CMD_Y_SE     (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */\n#define SADC_CFG_CMD_X_DIFF   (0x2 << SADC_CFG_CMD_BIT) /* X Differential */\n#define SADC_CFG_CMD_Y_DIFF   (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */\n#define SADC_CFG_CMD_Z1_DIFF  (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */\n#define SADC_CFG_CMD_Z2_DIFF  (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */\n#define SADC_CFG_CMD_Z3_DIFF  (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */\n#define SADC_CFG_CMD_Z4_DIFF  (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */\n#define SADC_CFG_CMD_TP_SE    (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */\n#define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */\n#define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */\n#define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT)        /* Measure SADCIN */\n#define SADC_CFG_CMD_INT_PEN  (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */\n\n /* ADC Control Register */\n#define SADC_CTRL_PENDM         (1 << 4)        /* Pen Down Interrupt Mask */\n#define SADC_CTRL_PENUM         (1 << 3)        /* Pen Up Interrupt Mask */\n#define SADC_CTRL_TSRDYM        (1 << 2)        /* Touch Screen Data Ready Interrupt Mask */\n#define SADC_CTRL_PBATRDYM      (1 << 1)        /* PBAT Data Ready Interrupt Mask */\n#define SADC_CTRL_SRDYM         (1 << 0)        /* SADCIN Data Ready Interrupt Mask */\n\n /* ADC Status Register */\n#define SADC_STATE_TSBUSY       (1 << 7)        /* TS A/D is working */\n#define SADC_STATE_PBATBUSY     (1 << 6)        /* PBAT A/D is working */\n#define SADC_STATE_SBUSY        (1 << 5)        /* SADCIN A/D is working */\n#define SADC_STATE_PEND         (1 << 4)        /* Pen Down Interrupt Flag */\n#define SADC_STATE_PENU         (1 << 3)        /* Pen Up Interrupt Flag */\n#define SADC_STATE_TSRDY        (1 << 2)        /* Touch Screen Data Ready Interrupt Flag */\n#define SADC_STATE_PBATRDY      (1 << 1)        /* PBAT Data Ready Interrupt Flag */\n#define SADC_STATE_SRDY         (1 << 0)        /* SADCIN Data Ready Interrupt Flag */\n\n /* ADC Touch Screen Data Register */\n#define SADC_TSDAT_DATA0_BIT    0\n#define SADC_TSDAT_DATA0_MASK   (0xfff << SADC_TSDAT_DATA0_BIT)\n#define SADC_TSDAT_TYPE0        (1 << 15)\n#define SADC_TSDAT_DATA1_BIT    16\n#define SADC_TSDAT_DATA1_MASK   (0xfff << SADC_TSDAT_DATA1_BIT)\n#define SADC_TSDAT_TYPE1        (1 << 31)\n\n#define JZ4740_TS_INDEX_MAX 0xA /*0x28/4 */\n\n/*--------------DMA--------------------*/\n#define JZ4740_DMA_BASE 0x13020000\n#define JZ4740_DMA_SIZE  0x310\n#define MAX_DMA_NUM\t6       /* max 6 channels */\n\n#define DMAC_DSAR(n)\t( (0x00 + (n) * 0x20))  /* DMA source address */\n#define DMAC_DTAR(n)\t( (0x04 + (n) * 0x20))  /* DMA target address */\n#define DMAC_DTCR(n)\t( (0x08 + (n) * 0x20))  /* DMA transfer count */\n#define DMAC_DRSR(n)\t( (0x0c + (n) * 0x20))  /* DMA request source */\n#define DMAC_DCCSR(n)\t( (0x10 + (n) * 0x20))  /* DMA control/status */\n#define DMAC_DCMD(n)\t( (0x14 + (n) * 0x20))  /* DMA command */\n#define DMAC_DDA(n)\t( (0x18 + (n) * 0x20))  /* DMA descriptor address */\n#define DMAC_DMACR\t( 0x0300)       /* DMA control register */\n#define DMAC_DMAIPR\t( 0x0304)       /* DMA interrupt pending */\n#define DMAC_DMADBR\t( 0x0308)       /* DMA doorbell */\n#define DMAC_DMADBSR\t( 0x030C)       /* DMA doorbell set */\n\n// channel 0\n#define DMAC_DSAR0      DMAC_DSAR(0)\n#define DMAC_DTAR0      DMAC_DTAR(0)\n#define DMAC_DTCR0      DMAC_DTCR(0)\n#define DMAC_DRSR0      DMAC_DRSR(0)\n#define DMAC_DCCSR0     DMAC_DCCSR(0)\n#define DMAC_DCMD0\tDMAC_DCMD(0)\n#define DMAC_DDA0\tDMAC_DDA(0)\n\n// channel 1\n#define DMAC_DSAR1      DMAC_DSAR(1)\n#define DMAC_DTAR1      DMAC_DTAR(1)\n#define DMAC_DTCR1      DMAC_DTCR(1)\n#define DMAC_DRSR1      DMAC_DRSR(1)\n#define DMAC_DCCSR1     DMAC_DCCSR(1)\n#define DMAC_DCMD1\tDMAC_DCMD(1)\n#define DMAC_DDA1\tDMAC_DDA(1)\n\n// channel 2\n#define DMAC_DSAR2      DMAC_DSAR(2)\n#define DMAC_DTAR2      DMAC_DTAR(2)\n#define DMAC_DTCR2      DMAC_DTCR(2)\n#define DMAC_DRSR2      DMAC_DRSR(2)\n#define DMAC_DCCSR2     DMAC_DCCSR(2)\n#define DMAC_DCMD2\tDMAC_DCMD(2)\n#define DMAC_DDA2\tDMAC_DDA(2)\n\n// channel 3\n#define DMAC_DSAR3      DMAC_DSAR(3)\n#define DMAC_DTAR3      DMAC_DTAR(3)\n#define DMAC_DTCR3      DMAC_DTCR(3)\n#define DMAC_DRSR3      DMAC_DRSR(3)\n#define DMAC_DCCSR3     DMAC_DCCSR(3)\n#define DMAC_DCMD3\tDMAC_DCMD(3)\n#define DMAC_DDA3\tDMAC_DDA(3)\n\n// channel 4\n#define DMAC_DSAR4      DMAC_DSAR(4)\n#define DMAC_DTAR4      DMAC_DTAR(4)\n#define DMAC_DTCR4      DMAC_DTCR(4)\n#define DMAC_DRSR4      DMAC_DRSR(4)\n#define DMAC_DCCSR4     DMAC_DCCSR(4)\n#define DMAC_DCMD4\tDMAC_DCMD(4)\n#define DMAC_DDA4\tDMAC_DDA(4)\n\n// channel 5\n#define DMAC_DSAR5      DMAC_DSAR(5)\n#define DMAC_DTAR5      DMAC_DTAR(5)\n#define DMAC_DTCR5      DMAC_DTCR(5)\n#define DMAC_DRSR5      DMAC_DRSR(5)\n#define DMAC_DCCSR5     DMAC_DCCSR(5)\n#define DMAC_DCMD5\tDMAC_DCMD(5)\n#define DMAC_DDA5\tDMAC_DDA(5)\n\n#define JZ4740_DMA_INDEX_MAX 0xC4       /*0x310/4 */\n\n// DMA request source register\n#define DMAC_DRSR_RS_BIT\t0\n#define DMAC_DRSR_RS_MASK\t(0x1f << DMAC_DRSR_RS_BIT)\n#define DMAC_DRSR_RS_AUTO\t(8 << DMAC_DRSR_RS_BIT)\n#define DMAC_DRSR_RS_UART0OUT\t(20 << DMAC_DRSR_RS_BIT)\n#define DMAC_DRSR_RS_UART0IN\t(21 << DMAC_DRSR_RS_BIT)\n#define DMAC_DRSR_RS_SSIOUT\t(22 << DMAC_DRSR_RS_BIT)\n#define DMAC_DRSR_RS_SSIIN\t(23 << DMAC_DRSR_RS_BIT)\n#define DMAC_DRSR_RS_AICOUT\t(24 << DMAC_DRSR_RS_BIT)\n#define DMAC_DRSR_RS_AICIN\t(25 << DMAC_DRSR_RS_BIT)\n#define DMAC_DRSR_RS_MSCOUT\t(26 << DMAC_DRSR_RS_BIT)\n#define DMAC_DRSR_RS_MSCIN\t(27 << DMAC_DRSR_RS_BIT)\n#define DMAC_DRSR_RS_TCU\t(28 << DMAC_DRSR_RS_BIT)\n#define DMAC_DRSR_RS_SADC\t(29 << DMAC_DRSR_RS_BIT)\n#define DMAC_DRSR_RS_SLCD\t(30 << DMAC_DRSR_RS_BIT)\n\n// DMA channel control/status register\n#define DMAC_DCCSR_NDES\t\t(1 << 31)       /* descriptor (0) or not (1) ? */\n#define DMAC_DCCSR_CDOA_BIT\t16      /* copy of DMA offset address */\n#define DMAC_DCCSR_CDOA_MASK\t(0xff << DMAC_DCCSR_CDOA_BIT)\n#define DMAC_DCCSR_INV\t\t(1 << 6)        /* descriptor invalid */\n#define DMAC_DCCSR_AR\t\t(1 << 4)        /* address error */\n#define DMAC_DCCSR_TT\t\t(1 << 3)        /* transfer terminated */\n#define DMAC_DCCSR_HLT\t\t(1 << 2)        /* DMA halted */\n#define DMAC_DCCSR_CT\t\t(1 << 1)        /* count terminated */\n#define DMAC_DCCSR_EN\t\t(1 << 0)        /* channel enable bit */\n\n// DMA channel command register \n#define DMAC_DCMD_SAI\t\t(1 << 23)       /* source address increment */\n#define DMAC_DCMD_DAI\t\t(1 << 22)       /* dest address increment */\n#define DMAC_DCMD_RDIL_BIT\t16      /* request detection interval length */\n#define DMAC_DCMD_RDIL_MASK\t(0x0f << DMAC_DCMD_RDIL_BIT)\n#define DMAC_DCMD_RDIL_IGN\t(0 << DMAC_DCMD_RDIL_BIT)\n#define DMAC_DCMD_RDIL_2\t(1 << DMAC_DCMD_RDIL_BIT)\n#define DMAC_DCMD_RDIL_4\t(2 << DMAC_DCMD_RDIL_BIT)\n#define DMAC_DCMD_RDIL_8\t(3 << DMAC_DCMD_RDIL_BIT)\n#define DMAC_DCMD_RDIL_12\t(4 << DMAC_DCMD_RDIL_BIT)\n#define DMAC_DCMD_RDIL_16\t(5 << DMAC_DCMD_RDIL_BIT)\n#define DMAC_DCMD_RDIL_20\t(6 << DMAC_DCMD_RDIL_BIT)\n#define DMAC_DCMD_RDIL_24\t(7 << DMAC_DCMD_RDIL_BIT)\n#define DMAC_DCMD_RDIL_28\t(8 << DMAC_DCMD_RDIL_BIT)\n#define DMAC_DCMD_RDIL_32\t(9 << DMAC_DCMD_RDIL_BIT)\n#define DMAC_DCMD_RDIL_48\t(10 << DMAC_DCMD_RDIL_BIT)\n#define DMAC_DCMD_RDIL_60\t(11 << DMAC_DCMD_RDIL_BIT)\n#define DMAC_DCMD_RDIL_64\t(12 << DMAC_DCMD_RDIL_BIT)\n#define DMAC_DCMD_RDIL_124\t(13 << DMAC_DCMD_RDIL_BIT)\n#define DMAC_DCMD_RDIL_128\t(14 << DMAC_DCMD_RDIL_BIT)\n#define DMAC_DCMD_RDIL_200\t(15 << DMAC_DCMD_RDIL_BIT)\n#define DMAC_DCMD_SWDH_BIT\t14      /* source port width */\n#define DMAC_DCMD_SWDH_MASK\t(0x03 << DMAC_DCMD_SWDH_BIT)\n#define DMAC_DCMD_SWDH_32\t(0 << DMAC_DCMD_SWDH_BIT)\n#define DMAC_DCMD_SWDH_8\t(1 << DMAC_DCMD_SWDH_BIT)\n#define DMAC_DCMD_SWDH_16\t(2 << DMAC_DCMD_SWDH_BIT)\n#define DMAC_DCMD_DWDH_BIT\t12      /* dest port width */\n#define DMAC_DCMD_DWDH_MASK\t(0x03 << DMAC_DCMD_DWDH_BIT)\n#define DMAC_DCMD_DWDH_32\t(0 << DMAC_DCMD_DWDH_BIT)\n#define DMAC_DCMD_DWDH_8\t(1 << DMAC_DCMD_DWDH_BIT)\n#define DMAC_DCMD_DWDH_16\t(2 << DMAC_DCMD_DWDH_BIT)\n#define DMAC_DCMD_DS_BIT\t8       /* transfer data size of a data unit */\n#define DMAC_DCMD_DS_MASK\t(0x07 << DMAC_DCMD_DS_BIT)\n#define DMAC_DCMD_DS_32BIT\t(0 << DMAC_DCMD_DS_BIT)\n#define DMAC_DCMD_DS_8BIT\t(1 << DMAC_DCMD_DS_BIT)\n#define DMAC_DCMD_DS_16BIT\t(2 << DMAC_DCMD_DS_BIT)\n#define DMAC_DCMD_DS_16BYTE\t(3 << DMAC_DCMD_DS_BIT)\n#define DMAC_DCMD_DS_32BYTE\t(4 << DMAC_DCMD_DS_BIT)\n#define DMAC_DCMD_TM\t\t(1 << 7)        /* transfer mode: 0-single 1-block */\n#define DMAC_DCMD_DES_V\t\t(1 << 4)        /* descriptor valid flag */\n#define DMAC_DCMD_DES_VM\t(1 << 3)        /* descriptor valid mask: 1:support V-bit */\n#define DMAC_DCMD_DES_VIE\t(1 << 2)        /* DMA valid error interrupt enable */\n#define DMAC_DCMD_TIE\t\t(1 << 1)        /* DMA transfer interrupt enable */\n#define DMAC_DCMD_LINK\t\t(1 << 0)        /* descriptor link enable */\n\n// DMA descriptor address register\n#define DMAC_DDA_BASE_BIT\t12      /* descriptor base address */\n#define DMAC_DDA_BASE_MASK\t(0x0fffff << DMAC_DDA_BASE_BIT)\n#define DMAC_DDA_OFFSET_BIT\t4       /* descriptor offset address */\n#define DMAC_DDA_OFFSET_MASK\t(0x0ff << DMAC_DDA_OFFSET_BIT)\n\n// DMA control register\n#define DMAC_DMACR_PR_BIT\t8       /* channel priority mode */\n#define DMAC_DMACR_PR_MASK\t(0x03 << DMAC_DMACR_PR_BIT)\n#define DMAC_DMACR_PR_012345\t(0 << DMAC_DMACR_PR_BIT)\n#define DMAC_DMACR_PR_023145\t(1 << DMAC_DMACR_PR_BIT)\n#define DMAC_DMACR_PR_201345\t(2 << DMAC_DMACR_PR_BIT)\n#define DMAC_DMACR_PR_RR\t(3 << DMAC_DMACR_PR_BIT)        /* round robin */\n#define DMAC_DMACR_HLT\t\t(1 << 3)        /* DMA halt flag */\n#define DMAC_DMACR_AR\t\t(1 << 2)        /* address error flag */\n#define DMAC_DMACR_DMAE\t\t(1 << 0)        /* DMA enable bit */\n\n/*------------INT CONTROLLER------------------------*/\n#define JZ4740_INT_BASE 0x10001000\n#define JZ4740_INT_SIZE  0x1C\n\n#define INTC_ISR\t( 0x00)\n#define INTC_IMR\t( 0x04)\n#define INTC_IMSR\t( 0x08)\n#define INTC_IMCR\t( 0x0c)\n#define INTC_IPR\t( 0x10)\n\n// 1st-level interrupts\n#define IRQ_I2C\t\t1\n#define IRQ_UHC\t\t3\n#define IRQ_UART0\t9\n#define IRQ_SADC\t12\n#define IRQ_MSC\t\t14\n#define IRQ_RTC\t\t15\n#define IRQ_SSI\t\t16\n#define IRQ_CIM\t\t17\n#define IRQ_AIC\t\t18\n#define IRQ_ETH\t\t19\n#define IRQ_DMAC\t20\n#define IRQ_TCU2\t21\n#define IRQ_TCU1\t22\n#define IRQ_TCU0\t23\n#define IRQ_UDC \t24\n#define IRQ_GPIO3\t25\n#define IRQ_GPIO2\t26\n#define IRQ_GPIO1\t27\n#define IRQ_GPIO0\t28\n#define IRQ_IPU\t\t29\n#define IRQ_LCD\t\t30\n\n// 2nd-level interrupts\n#define IRQ_DMA_0\t32      /* 32 to 37 for DMAC channel 0 to 5 */\n#define IRQ_GPIO_0\t48      /* 48 to 175 for GPIO pin 0 to 127 */\n\n#define JZ4740_INT_INDEX_MAX 0x7        /*0x1C/4 */\n#define JZ4740_INT_TO_MIPS   0x2        /*jz4740 intc will issue int 2 to mips cpu */\n\nint jz4740_boot_from_nandflash (vm_instance_t * vm);\nint jz4740_reset (vm_instance_t * vm);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/jz4740/jz4740_dev_cpm.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n/*Just a dummy cpm for JZ4740\nI need document!!!\n*/\n\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include<sys/types.h>\n#include<sys/stat.h>\n#include<string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"cpu.h\"\n#include \"jz4740.h\"\n\nm_uint32_t jz4740_cpm_table[JZ4740_CPM_INDEX_MAX];\n\nstruct jz4740_cpm_data {\n    struct vdevice *dev;\n    m_uint8_t *jz4740_cpm_ptr;\n    m_uint32_t jz4740_cpm_size;\n};\n\nvoid *dev_jz4740_cpm_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t * data,\n    m_uint8_t * has_set_value)\n{\n\n    struct jz4740_cpm_data *d = dev->priv_data;\n\n    if (offset >= d->jz4740_cpm_size) {\n        *data = 0;\n        return NULL;\n    }\n    return ((void *) (d->jz4740_cpm_ptr + offset));\n\n}\n\nvoid dev_jz4740_cpm_init_defaultvalue ()\n{\n    memset (jz4740_cpm_table, 0x0, sizeof (jz4740_cpm_table));\n}\n\nvoid dev_jz4740_cpm_reset (cpu_mips_t * cpu, struct vdevice *dev)\n{\n    dev_jz4740_cpm_init_defaultvalue ();\n}\n\nint dev_jz4740_cpm_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len)\n{\n    struct jz4740_cpm_data *d;\n\n    /* allocate the private data structure */\n    if (!(d = malloc (sizeof (*d)))) {\n        fprintf (stderr, \"jz4740_cpm: unable to create device.\\n\");\n        return (-1);\n    }\n\n    memset (d, 0, sizeof (*d));\n    if (!(d->dev = dev_create (name)))\n        goto err_dev_create;\n    d->dev->priv_data = d;\n    d->dev->phys_addr = paddr;\n    d->dev->phys_len = len;\n    d->jz4740_cpm_ptr = (m_uint8_t *) (&jz4740_cpm_table[0]);\n    d->jz4740_cpm_size = len;\n    d->dev->handler = dev_jz4740_cpm_access;\n    d->dev->reset_handler = dev_jz4740_cpm_reset;\n\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n\n    vm_bind_device (vm, d->dev);\n    //dev_jz4740_cpm_init_defaultvalue();\n\n    return (0);\n\n  err_dev_create:\n    free (d);\n    return (-1);\n}\n"
  },
  {
    "path": "tools/virtualmips/jz4740/jz4740_dev_dma.c",
    "content": " /*\n  * Copyright (C) yajin 2008<yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n/*DMA Controller\nOnly support AUTO Request.\n\nTODO:\n*/\n\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include<sys/types.h>\n#include<sys/stat.h>\n#include<string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"cpu.h\"\n#include \"jz4740.h\"\n\nm_uint32_t jz4740_dma_table[JZ4740_DMA_INDEX_MAX];\n\nstruct jz4740_dma_data {\n    struct vdevice *dev;\n    m_uint8_t *jz4740_dma_ptr;\n    m_uint32_t jz4740_dma_size;\n};\n\ntypedef struct {\n    m_uint32_t dcmd;            /* DCMD value for the current transfer */\n    m_uint32_t dsadr;           /* DSAR value for the current transfer */\n    m_uint32_t dtadr;           /* DTAR value for the current transfer */\n    m_uint32_t ddadr;           /* Points to the next descriptor + transfer count */\n} jz_dma_desc;\n\nstatic int get_dma_unit_size (int channel, m_uint32_t cmd_value)\n{\n    //switch (jz4740_dma_table[DMAC_DCMD(channel)/4]&DMAC_DCMD_DS_MASK)\n    switch (cmd_value & DMAC_DCMD_DS_MASK) {\n    case DMAC_DCMD_DS_32BIT:\n        return 4;\n    case DMAC_DCMD_DS_16BIT:\n        return 2;\n    case DMAC_DCMD_DS_8BIT:\n        return 1;\n    case DMAC_DCMD_DS_16BYTE:\n        return 16;\n    case DMAC_DCMD_DS_32BYTE:\n        return 32;\n    default:\n        assert (0);\n    }\n\n}\n\nvoid dma_non_descriptor_trans (cpu_mips_t * cpu, struct jz4740_dma_data *d,\n    int channel)\n{\n\n    physmem_dma_transfer (cpu->vm, jz4740_dma_table[DMAC_DSAR (channel) / 4],\n        jz4740_dma_table[DMAC_DTAR (channel) / 4],\n        get_dma_unit_size (channel,\n            jz4740_dma_table[DMAC_DCMD (channel) / 4]) *\n        jz4740_dma_table[DMAC_DTCR (channel) / 4]);\n    /*we have finished dma */\n    jz4740_dma_table[DMAC_DTCR (channel) / 4] = 0;\n\n    /*set DIR QP */\n    jz4740_dma_table[DMAC_DMAIPR / 4] |= 1 << channel;\n    /*some cleanup work */\n    /*clean AR TT GLOBAL AR */\n    jz4740_dma_table[DMAC_DCCSR (channel) / 4] |= ~DMAC_DCCSR_AR;\n    jz4740_dma_table[DMAC_DCCSR (channel) / 4] |= ~DMAC_DCCSR_TT;\n    jz4740_dma_table[DMAC_DMACR / 4] |= ~DMAC_DMACR_AR;\n\n    if (jz4740_dma_table[DMAC_DCMD (channel) / 4] & DMAC_DCMD_TIE) {\n        cpu->vm->set_irq (cpu->vm, IRQ_DMAC);\n    }\n\n}\n\nvoid dma_descriptor_trans (cpu_mips_t * cpu, struct jz4740_dma_data *d,\n    int channel)\n{\n    jz_dma_desc *desc;\n    m_pa_t desc_phy;\n    m_uint32_t dummy_data;\n\n    /*fetch the first descritpor */\n    desc_phy = jz4740_dma_table[DMAC_DDA (channel) / 4];\n    ASSERT ((desc_phy & 0xf) == 0, \"DDA%d should be 16 bytes aligned\\n\",\n        channel);\n    desc = physmem_get_hptr (cpu->vm, desc_phy, 4, MTS_READ, &dummy_data);\n    ASSERT (desc != NULL, \"error descriptor phyaddress %x\\n\", desc_phy);\n    while (1) {\n        if (((desc->dcmd) & DMAC_DCMD_DES_VM)\n            && (!((desc->dcmd) & DMAC_DCMD_DES_V))) {\n            /*STOP DMA SET DCSN.INV=1 */\n            jz4740_dma_table[DMAC_DCCSR (channel) / 4] |= DMAC_DCCSR_INV;\n            return;\n        }\n        physmem_dma_transfer (cpu->vm, desc->dsadr,\n            desc->dtadr,\n            (desc->ddadr & 0xffffff) * get_dma_unit_size (channel,\n                desc->dcmd));\n\n        if ((desc->dcmd) & DMAC_DCMD_DES_VM) {\n            /*clear v */\n            desc->dcmd |= ~DMAC_DCMD_DES_V;\n        }\n        if ((desc->dcmd) & DMAC_DCMD_LINK) {\n            /*set DCSN.CT=1 */\n            jz4740_dma_table[DMAC_DCCSR (channel) / 4] |= DMAC_DCCSR_CT;\n        } else {\n            /*set DCSN.TT=1 */\n            jz4740_dma_table[DMAC_DCCSR (channel) / 4] |= DMAC_DCCSR_TT;\n        }\n\n        if (desc->dcmd & DMAC_DCMD_TIE) {\n            cpu->vm->set_irq (cpu->vm, IRQ_DMAC);\n        }\n\n        if ((desc->dcmd) & DMAC_DCMD_LINK) {\n            /*fetch next descriptor */\n            desc_phy = jz4740_dma_table[DMAC_DDA (channel) / 4] & 0xfffff000;\n            desc_phy += (desc->dtadr & 0xff000000) >> 24;\n            desc =\n                physmem_get_hptr (cpu->vm, desc_phy, 4, MTS_READ,\n                &dummy_data);\n            ASSERT (desc != NULL, \"error descriptor phyaddress %x\\n\",\n                desc_phy);\n        } else\n            break;\n\n    }\n\n}\n\nvoid enable_dma_channel (cpu_mips_t * cpu, struct jz4740_dma_data *d,\n    int channel)\n{\n    if (jz4740_dma_table[DMAC_DMACR / 4] & DMAC_DMACR_DMAE) {\n        if ((jz4740_dma_table[DMAC_DCCSR (channel) / 4] & DMAC_DCCSR_NDES)) {\n            /*NON DESCRIPTOR */\n            dma_non_descriptor_trans (cpu, d, channel);\n        }\n    }\n}\n\nvoid enable_global_dma (cpu_mips_t * cpu, struct jz4740_dma_data *d)\n{\n    int channel;\n    for (channel = 0; channel < MAX_DMA_NUM; channel++) {\n        if ((jz4740_dma_table[DMAC_DCCSR (channel) / 4] & DMAC_DCCSR_NDES)) {\n            if ((jz4740_dma_table[DMAC_DCCSR (channel) /\n                        4] & DMAC_DCCSR_NDES))\n                dma_non_descriptor_trans (cpu, d, channel);     /*NON DESCRIPTOR */\n        }\n    }\n\n}\n\nvoid enable_dma_dbn (cpu_mips_t * cpu, struct jz4740_dma_data *d, int channel)\n{\n    /*DESCRIPTOR trans */\n    if ((jz4740_dma_table[DMAC_DMACR / 4] & DMAC_DMACR_DMAE)\n        && (jz4740_dma_table[DMAC_DCCSR (channel) / 4] & DMAC_DCCSR_NDES)) {\n        dma_descriptor_trans (cpu, d, channel);\n    }\n}\n\nvoid *dev_jz4740_dma_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t * data,\n    m_uint8_t * has_set_value)\n{\n\n    struct jz4740_dma_data *d = dev->priv_data;\n    int channel;\n\n    if (offset >= d->jz4740_dma_size) {\n        *data = 0;\n        return NULL;\n    }\n\n    if (op_type == MTS_WRITE) {\n        switch (offset) {\n        case DMAC_DRSR0:\n        case DMAC_DRSR1:\n        case DMAC_DRSR2:\n        case DMAC_DRSR3:\n        case DMAC_DRSR4:\n        case DMAC_DRSR5:\n            /*only support AUTO request */\n            ASSERT (((*data) & DMAC_DRSR_RS_MASK) == DMAC_DRSR_RS_AUTO,\n                \"only support AUTO request\\n\");\n            return ((void *) (d->jz4740_dma_ptr + offset));\n\n        case DMAC_DCCSR0:\n        case DMAC_DCCSR1:\n        case DMAC_DCCSR2:\n        case DMAC_DCCSR3:\n        case DMAC_DCCSR4:\n        case DMAC_DCCSR5:\n            channel = (offset - 0x10) / 0x20;\n            jz4740_dma_table[DMAC_DCCSR (channel) / 4] = *data;\n            *has_set_value = TRUE;\n            if ((*data) & DMAC_DCCSR_EN) {\n                enable_dma_channel (cpu, d, channel);\n            }\n            return NULL;\n\n        case DMAC_DMACR:\n            /*DMA Control register */\n            jz4740_dma_table[DMAC_DMACR / 4] = *data;\n            *has_set_value = TRUE;\n            if ((*data) & DMAC_DMACR_DMAE) {\n                enable_global_dma (cpu, d);\n            }\n            return NULL;\n\n        case DMAC_DMADBR:\n        case DMAC_DMADBSR:\n            jz4740_dma_table[DMAC_DMADBR / 4] = *data;\n            *has_set_value = TRUE;\n            for (channel = 0; channel < 6; channel++) {\n                if ((*data) & (1 << channel)) {\n                    enable_dma_dbn (cpu, d, channel);\n                    break;\n                }\n\n            }\n            return NULL;\n        default:\n            return ((void *) (d->jz4740_dma_ptr + offset));\n        }\n\n    } else if (op_type == MTS_READ)\n        return ((void *) (d->jz4740_dma_ptr + offset));\n    else\n        assert (0);\n\n    return NULL;\n\n}\n\nvoid dev_jz4740_dma_init_defaultvalue ()\n{\n    memset (jz4740_dma_table, 0x0, sizeof (jz4740_dma_table));\n}\n\nvoid dev_jz4740_dma_reset (cpu_mips_t * cpu, struct vdevice *dev)\n{\n    dev_jz4740_dma_init_defaultvalue ();\n}\n\nint dev_jz4740_dma_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len)\n{\n    struct jz4740_dma_data *d;\n\n    /* allocate the private data structure */\n    if (!(d = malloc (sizeof (*d)))) {\n        fprintf (stderr, \"jz4740_dma: unable to create device.\\n\");\n        return (-1);\n    }\n\n    memset (d, 0, sizeof (*d));\n    if (!(d->dev = dev_create (name)))\n        goto err_dev_create;\n    d->dev->priv_data = d;\n    d->dev->phys_addr = paddr;\n    d->dev->phys_len = len;\n    d->jz4740_dma_ptr = (m_uint8_t *) (&jz4740_dma_table[0]);\n    d->jz4740_dma_size = len;\n    d->dev->handler = dev_jz4740_dma_access;\n    d->dev->reset_handler = dev_jz4740_dma_reset;\n\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n\n    vm_bind_device (vm, d->dev);\n\n    return (0);\n\n  err_dev_create:\n    free (d);\n    return (-1);\n}\n"
  },
  {
    "path": "tools/virtualmips/jz4740/jz4740_dev_emc.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n/*EMC. */\n\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include<sys/types.h>\n#include<sys/stat.h>\n#include<string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"cpu.h\"\n#include \"jz4740.h\"\n\nm_uint32_t jz4740_emc_table[JZ4740_EMC_INDEX_MAX];\nm_uint32_t emc_sdram0[256];\n/*configure register for sdram0*/\n/*In order to save space, set emc sdram0  seperately.*/\n\nstruct jz4740_emc_data {\n    struct vdevice *dev;\n    m_uint8_t *jz4740_emc_ptr;\n    m_uint32_t jz4740_emc_size;\n};\n\nvoid *dev_jz4740_emc_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type,\n    m_reg_t * data, m_uint8_t * has_set_value)\n{\n\n    struct jz4740_emc_data *d = dev->priv_data;\n    /*TODO: SDRAM MODE. Now just set dummy value. */\n    /*EMC SDRAM0 is in seperate space */\n    if ((offset >= EMC_SDMR0) && (offset <= (EMC_SDMR0 + 0x3ff))) {\n        return (void *) (((m_uint8_t *) & emc_sdram0[0]) + offset -\n            EMC_SDMR0);\n    }\n\n    if ((offset >= d->jz4740_emc_size)) {\n        *data = 0;\n        return NULL;\n    }\n    /*FIXME:\n     * currently we do not support nand flash rc check. just set\n     * EMC_NFINTS_DECF(bit 3) and EMC_NFINTS_ENCF(bit 2). to tell uboot and decoding and Encoding finished\n     * set EMC_NFINTS_ERR(bit 0)=0 : no error */\n    if (offset == EMC_NFINTS) {\n        jz4740_emc_table[EMC_NFINTS / 4] |= 0xc;\n    }\n\n    return ((void *) (d->jz4740_emc_ptr + offset));\n\n}\n\nvoid dev_jz4740_emc_init_defaultvalue ()\n{\n    memset (jz4740_emc_table, 0x0, sizeof (jz4740_emc_table));\n#ifdef SIM_PAVO\n    /*EMC BCR(31:30):Boot sel\n     * 11:2k page nand flash */\n    jz4740_emc_table[EMC_BCR / 4] |= 0xc0000000;\n#endif\n\n}\n\nvoid dev_jz4740_emc_reset (cpu_mips_t * cpu, struct vdevice *dev)\n{\n    dev_jz4740_emc_init_defaultvalue ();\n}\n\nint dev_jz4740_emc_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len)\n{\n    struct jz4740_emc_data *d;\n\n    /* allocate the private data structure */\n    if (!(d = malloc (sizeof (*d)))) {\n        fprintf (stderr, \"jz4740_emc: unable to create device.\\n\");\n        return (-1);\n    }\n\n    memset (d, 0, sizeof (*d));\n    if (!(d->dev = dev_create (name)))\n        goto err_dev_create;\n    d->dev->priv_data = d;\n    d->dev->phys_addr = paddr;\n    d->dev->phys_len = len;\n    d->jz4740_emc_ptr = (m_uint8_t *) (&jz4740_emc_table[0]);\n    d->jz4740_emc_size = len;\n    d->dev->handler = dev_jz4740_emc_access;\n    d->dev->reset_handler = dev_jz4740_emc_reset;\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n\n    vm_bind_device (vm, d->dev);\n    //dev_jz4740_emc_init_defaultvalue();\n\n    return (0);\n\n  err_dev_create:\n    free (d);\n    return (-1);\n}\n"
  },
  {
    "path": "tools/virtualmips/jz4740/jz4740_dev_gpio.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include<sys/types.h>\n#include<sys/stat.h>\n#include<string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"cpu.h\"\n#include \"jz4740.h\"\n\n/*set to 0 to improve performance. set to 1 to debug gpio*/\n#define VALIDE_GPIO_OPERATION 0\n\nm_uint32_t jz4740_gpio_table[JZ4740_GPIO_INDEX_MAX];\n\nstruct jz4740_gpio_data {\n    struct vdevice *dev;\n    m_uint8_t *jz4740_gpio_ptr;\n    m_uint32_t jz4740_gpio_size;\n};\n\n/* GPIO is in 4 groups. 32 per group*/\n/*\n\n48-79      0\n80-111    1\n112-143  2\n144-175  3\n\n#define IRQ_GPIO3\t25\n#define IRQ_GPIO2\t26\n#define IRQ_GPIO1\t27\n#define IRQ_GPIO0\t28\n#define IRQ_GPIO_0\t48   48 to 175 for GPIO pin 0 to 127 */\n\nvoid dev_jz4740_gpio_setirq (int irq)\n{\n    int group_no;\n    int pin_no;\n\n    ASSERT ((irq >= IRQ_GPIO_0)\n        && (irq < IRQ_GPIO_0 + 128), \"wrong gpio irq 0x%x\\n\", irq);\n\n    group_no = (irq - IRQ_GPIO_0) / 32;\n    pin_no = (irq - IRQ_GPIO_0) % 32;\n    jz4740_gpio_table[GPIO_PXFLG (group_no) / 4] |= 1 << pin_no;\n}\n\nvoid dev_jz4740_gpio_clearirq (int irq)\n{\n    int group_no;\n    int pin_no;\n\n    ASSERT ((irq >= IRQ_GPIO_0)\n        && (irq < IRQ_GPIO_0 + 128), \"wrong gpio irq 0x%x\\n\", irq);\n\n    group_no = (irq - IRQ_GPIO_0) / 32;\n    pin_no = (irq - IRQ_GPIO_0) % 32;\n    jz4740_gpio_table[GPIO_PXFLG (group_no) / 4] &= ~(1 << pin_no);\n}\n\nvoid *dev_jz4740_gpio_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t * data,\n    m_uint8_t * has_set_value)\n{\n\n    struct jz4740_gpio_data *d = dev->priv_data;\n\n    m_uint8_t group;\n    m_uint32_t mask, mask_data, temp;\n\n    if (offset >= d->jz4740_gpio_size) {\n        *data = 0;\n        return NULL;\n    }\n#if  VALIDE_GPIO_OPERATION\n    if (op_type == MTS_WRITE) {\n        ASSERT (offset != GPIO_PXPIN (0),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXPIN (1),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXPIN (2),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXPIN (3),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n\n        ASSERT (offset != GPIO_PXDAT (0),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXDAT (1),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXDAT (2),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXDAT (3),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n\n        ASSERT (offset != GPIO_PXIM (0),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXIM (1),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXIM (2),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXIM (3),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n\n        ASSERT (offset != GPIO_PXPE (0),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXPE (1),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXPE (2),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXPE (3),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n\n        ASSERT (offset != GPIO_PXFUN (0),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXFUN (1),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXFUN (2),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXFUN (3),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n\n        ASSERT (offset != GPIO_PXSEL (0),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXSEL (1),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXSEL (2),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXSEL (3),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n\n        ASSERT (offset != GPIO_PXDIR (0),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXDIR (1),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXDIR (2),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXDIR (3),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n\n        ASSERT (offset != GPIO_PXTRG (0),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXTRG (1),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXTRG (2),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXTRG (3),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n\n        ASSERT (offset != GPIO_PXFLG (0),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXFLG (1),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXFLG (2),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXFLG (3),\n            \"Write to read only register in GPIO. offset %x\\n\", offset);\n\n    }\n    if (op_type == MTS_READ) {\n        ASSERT (offset != GPIO_PXDATS (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXDATS (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXDATS (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXDATS (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n\n        ASSERT (offset != GPIO_PXDATC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXDATC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXDATC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXDATC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n\n        ASSERT (offset != GPIO_PXIMS (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXIMS (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXIMS (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXIMS (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n\n        ASSERT (offset != GPIO_PXIMC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXIMC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXIMC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXIMC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n\n        ASSERT (offset != GPIO_PXPES (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXPES (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXPES (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXPES (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n\n        ASSERT (offset != GPIO_PXPEC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXPEC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXPEC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXPEC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n\n        ASSERT (offset != GPIO_PXFUNS (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXFUNS (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXFUNS (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXFUNS (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n\n        ASSERT (offset != GPIO_PXFUNC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXFUNC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXFUNC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXFUNC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n\n        ASSERT (offset != GPIO_PXDIRS (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXDIRS (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXDIRS (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXDIRS (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n\n        ASSERT (offset != GPIO_PXDIRC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXDIRC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXDIRC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXDIRC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n\n        ASSERT (offset != GPIO_PXTRGS (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXTRGS (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXTRGS (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXTRGS (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n\n        ASSERT (offset != GPIO_PXTRGC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXTRGC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXTRGC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXTRGC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n\n        ASSERT (offset != GPIO_PXFLGC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXFLGC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXFLGC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n        ASSERT (offset != GPIO_PXFLGC (0),\n            \"Read write only register in GPIO. offset %x\\n\", offset);\n\n    }\n#endif\n\n    if (op_type == MTS_READ) {\n\n#ifdef SIM_PAVO\n/*PAVO GPIO(C) PIN 30  -> NAND FLASH R/B. */\n        if (offset == GPIO_PXPIN (2)) {\n            /*FOR NAND FLASH.PIN 30 ----|_____|------ */\n            temp = jz4740_gpio_table[GPIO_PXPIN (2) / 4];\n            temp &= 0x40000000;\n            if (temp)\n                temp &= ~0x40000000;\n            else\n                temp |= 0x40000000;\n            jz4740_gpio_table[GPIO_PXPIN (2) / 4] = temp;\n        }\n#endif\n\n        return ((void *) (d->jz4740_gpio_ptr + offset));\n    } else if (op_type == MTS_WRITE) {\n        switch (op_size) {\n        case 1:\n            mask = 0xff;\n            break;\n        case 2:\n            mask = 0xffff;\n            break;\n        case 4:\n            mask = 0xffffffff;\n            break;\n        default:\n            assert (0);\n        }\n\n        switch (offset) {\n        case GPIO_PXDATS (0):\n        case GPIO_PXDATS (1):\n        case GPIO_PXDATS (2):\n        case GPIO_PXDATS (3):\n            group = offset / 0x100;\n            mask_data = (*data) & mask;\n            jz4740_gpio_table[GPIO_PXDAT (group) / 4] |= mask_data;\n            break;\n\n        case GPIO_PXDATC (0):\n        case GPIO_PXDATC (1):\n        case GPIO_PXDATC (2):\n        case GPIO_PXDATC (3):\n            group = offset / 0x100;\n            mask_data = (*data) & mask;\n            mask_data = ~(mask_data);\n            jz4740_gpio_table[GPIO_PXDAT (group) / 4] &= mask_data;\n            break;\n\n        case GPIO_PXIMS (0):\n        case GPIO_PXIMS (1):\n        case GPIO_PXIMS (2):\n        case GPIO_PXIMS (3):\n            group = offset / 0x100;\n            mask_data = (*data) & mask;\n            jz4740_gpio_table[GPIO_PXIM (group) / 4] |= mask_data;\n            break;\n\n        case GPIO_PXIMC (0):\n        case GPIO_PXIMC (1):\n        case GPIO_PXIMC (2):\n        case GPIO_PXIMC (3):\n            group = offset / 0x100;\n            mask_data = (*data) & mask;\n            mask_data = ~(mask_data);\n            jz4740_gpio_table[GPIO_PXIM (group) / 4] &= mask_data;\n            break;\n\n        case GPIO_PXPES (0):\n        case GPIO_PXPES (1):\n        case GPIO_PXPES (2):\n        case GPIO_PXPES (3):\n            group = offset / 0x100;\n            mask_data = (*data) & mask;\n            jz4740_gpio_table[GPIO_PXPE (group) / 4] |= mask_data;\n            break;\n\n        case GPIO_PXPEC (0):\n        case GPIO_PXPEC (1):\n        case GPIO_PXPEC (2):\n        case GPIO_PXPEC (3):\n            group = offset / 0x100;\n            mask_data = (*data) & mask;\n            mask_data = ~(mask_data);\n            jz4740_gpio_table[GPIO_PXPE (group) / 4] &= mask_data;\n            break;\n\n        case GPIO_PXFUNS (0):\n        case GPIO_PXFUNS (1):\n        case GPIO_PXFUNS (2):\n        case GPIO_PXFUNS (3):\n            group = offset / 0x100;\n            mask_data = (*data) & mask;\n            jz4740_gpio_table[GPIO_PXFUN (group) / 4] |= mask_data;\n            break;\n\n        case GPIO_PXFUNC (0):\n        case GPIO_PXFUNC (1):\n        case GPIO_PXFUNC (2):\n        case GPIO_PXFUNC (3):\n            group = offset / 0x100;\n            mask_data = (*data) & mask;\n            mask_data = ~(mask_data);\n            jz4740_gpio_table[GPIO_PXFUN (group) / 4] &= mask_data;\n            break;\n\n        case GPIO_PXSELS (0):\n        case GPIO_PXSELS (1):\n        case GPIO_PXSELS (2):\n        case GPIO_PXSELS (3):\n            group = offset / 0x100;\n            mask_data = (*data) & mask;\n            jz4740_gpio_table[GPIO_PXSEL (group) / 4] |= mask_data;\n            break;\n\n        case GPIO_PXSELC (0):\n        case GPIO_PXSELC (1):\n        case GPIO_PXSELC (2):\n        case GPIO_PXSELC (3):\n            group = offset / 0x100;\n            mask_data = (*data) & mask;\n            mask_data = ~(mask_data);\n            jz4740_gpio_table[GPIO_PXSEL (group) / 4] &= mask_data;\n            break;\n\n        case GPIO_PXDIRS (0):\n        case GPIO_PXDIRS (1):\n        case GPIO_PXDIRS (2):\n        case GPIO_PXDIRS (3):\n            group = offset / 0x100;\n            mask_data = (*data) & mask;\n            jz4740_gpio_table[GPIO_PXDIR (group) / 4] |= mask_data;\n            break;\n\n        case GPIO_PXDIRC (0):\n        case GPIO_PXDIRC (1):\n        case GPIO_PXDIRC (2):\n        case GPIO_PXDIRC (3):\n            group = offset / 0x100;\n            mask_data = (*data) & mask;\n            mask_data = ~(mask_data);\n            jz4740_gpio_table[GPIO_PXDIR (group) / 4] &= mask_data;\n            break;\n\n        case GPIO_PXTRGS (0):\n        case GPIO_PXTRGS (1):\n        case GPIO_PXTRGS (2):\n        case GPIO_PXTRGS (3):\n            group = offset / 0x100;\n            mask_data = (*data) & mask;\n            jz4740_gpio_table[GPIO_PXTRG (group) / 4] |= mask_data;\n            break;\n\n        case GPIO_PXTRGC (0):\n        case GPIO_PXTRGC (1):\n        case GPIO_PXTRGC (2):\n        case GPIO_PXTRGC (3):\n            group = offset / 0x100;\n            mask_data = (*data) & mask;\n            mask_data = ~(mask_data);\n            jz4740_gpio_table[GPIO_PXTRG (group) / 4] &= mask_data;\n            break;\n\n        case GPIO_PXFLGC (0):\n        case GPIO_PXFLGC (1):\n        case GPIO_PXFLGC (2):\n        case GPIO_PXFLGC (3):\n            group = offset / 0x100;\n            mask_data = (*data) & mask;\n            mask_data = ~(mask_data);\n            jz4740_gpio_table[GPIO_PXFLG (group) / 4] &= mask_data;\n            break;\n\n        default:\n            cpu_log (cpu, \"\", \"invalid offset in GPIO. offset %x\\n\", offset);\n            return NULL;\n\n        }\n        *has_set_value = TRUE;\n        return NULL;\n    }\n\n    return NULL;\n}\n\nvoid dev_jz4740_gpio_init_defaultvalue ()\n{\n    memset (jz4740_gpio_table, 0x0, sizeof (jz4740_gpio_table));\n\n    jz4740_gpio_table[GPIO_PXIM (0) / 4] = 0xffffffff;\n    jz4740_gpio_table[GPIO_PXIM (1) / 4] = 0xffffffff;\n    jz4740_gpio_table[GPIO_PXIM (2) / 4] = 0xffffffff;\n    jz4740_gpio_table[GPIO_PXIM (3) / 4] = 0xffffffff;\n\n    //jz4740_gpio_table[GPIO_PXPIN(2)/4]=0x40000000;\n\n}\n\nvoid dev_jz4740_gpio_reset (cpu_mips_t * cpu, struct vdevice *dev)\n{\n    dev_jz4740_gpio_init_defaultvalue ();\n}\n\nint dev_jz4740_gpio_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len)\n{\n    struct jz4740_gpio_data *d;\n\n    /* allocate the private data structure */\n    if (!(d = malloc (sizeof (*d)))) {\n        fprintf (stderr, \"jz4740_gpio: unable to create device.\\n\");\n        return (-1);\n    }\n\n    memset (d, 0, sizeof (*d));\n    if (!(d->dev = dev_create (name)))\n        goto err_dev_create;\n    d->dev->priv_data = d;\n    d->dev->phys_addr = paddr;\n    d->dev->phys_len = len;\n    d->jz4740_gpio_ptr = (m_uint8_t *) (&jz4740_gpio_table[0]);\n    d->jz4740_gpio_size = len;\n    d->dev->handler = dev_jz4740_gpio_access;\n    d->dev->reset_handler = dev_jz4740_gpio_reset;\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n\n    vm_bind_device (vm, d->dev);\n    //dev_jz4740_gpio_init_defaultvalue();\n\n    return (0);\n\n  err_dev_create:\n    free (d);\n    return (-1);\n}\n"
  },
  {
    "path": "tools/virtualmips/jz4740/jz4740_dev_int.c",
    "content": " /*\n  * Copyright (C) yajin 2008<yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n/*jz4740 Interrupt controller*/\n\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include<sys/types.h>\n#include<sys/stat.h>\n#include<string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"cpu.h\"\n#include \"jz4740.h\"\n\n#define VALIDE_INT_OPERATION 0\n\nextern cpu_mips_t *current_cpu;\nm_uint32_t jz4740_int_table[JZ4740_INT_INDEX_MAX];\n\nstruct jz4740_int_data {\n    struct vdevice *dev;\n    m_uint8_t *jz4740_int_ptr;\n    m_uint32_t jz4740_int_size;\n};\n\nvoid *dev_jz4740_int_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t * data,\n    m_uint8_t * has_set_value)\n{\n\n    struct jz4740_int_data *d = dev->priv_data;\n    m_uint32_t mask_data, mask;\n\n    if (offset >= d->jz4740_int_size) {\n        *data = 0;\n        return NULL;\n    }\n#if  VALIDE_INT_OPERATION\n    if (op_type == MTS_WRITE) {\n        ASSERT (offset != INTC_ISR,\n            \"Write to read only register in INT. offset %x\\n\", offset);\n        ASSERT (offset != INTC_IPR,\n            \"Write to read only register in INT. offset %x\\n\", offset);\n    } else if (op_type == MTS_READ) {\n        ASSERT (offset != INTC_IMSR,\n            \"Read write only register in INT. offset %x\\n\", offset);\n        ASSERT (offset != INTC_IMCR,\n            \"Read write only register in INT. offset %x\\n\", offset);\n\n    }\n#endif\n\n    switch (op_size) {\n    case 1:\n        mask = 0xff;\n        break;\n    case 2:\n        mask = 0xffff;\n        break;\n    case 4:\n        mask = 0xffffffff;\n        break;\n    default:\n        assert (0);\n    }\n\n    switch (offset) {\n    case INTC_IMSR:            /*set */\n        assert (op_type == MTS_WRITE);\n        mask_data = (*data) & mask;\n        jz4740_int_table[INTC_IMR / 4] |= mask_data;\n        *has_set_value = TRUE;\n        break;\n    case INTC_IMCR:            /*clear */\n        assert (op_type == MTS_WRITE);\n        mask_data = (*data) & mask;\n        mask_data = ~(mask_data);\n        jz4740_int_table[INTC_IMR / 4] &= mask_data;\n        *has_set_value = TRUE;\n        break;\n    case INTC_IPR:             /*clear */\n        *data = jz4740_int_table[INTC_IPR / 4];\n        jz4740_int_table[INTC_IPR / 4] = 0;\n        *has_set_value = TRUE;\n        return NULL;\n    default:\n        return ((void *) (d->jz4740_int_ptr + offset));\n    }\n    return NULL;\n}\n\nvoid dev_jz4740_int_init_defaultvalue ()\n{\n    memset (jz4740_int_table, 0x0, sizeof (jz4740_int_table));\n    jz4740_int_table[INTC_IMR / 4] = 0xffffffff;\n}\n\nvoid dev_jz4740_int_reset (cpu_mips_t * cpu, struct vdevice *dev)\n{\n    dev_jz4740_int_init_defaultvalue ();\n}\n\nint dev_jz4740_int_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len)\n{\n    struct jz4740_int_data *d;\n\n    /* allocate the private data structure */\n    if (!(d = malloc (sizeof (*d)))) {\n        fprintf (stderr, \"jz4740_dma: unable to create device.\\n\");\n        return (-1);\n    }\n\n    memset (d, 0, sizeof (*d));\n    if (!(d->dev = dev_create (name)))\n        goto err_dev_create;\n    d->dev->priv_data = d;\n    d->dev->phys_addr = paddr;\n    d->dev->phys_len = len;\n    d->jz4740_int_ptr = (m_uint8_t *) (&jz4740_int_table[0]);\n    d->jz4740_int_size = len;\n    d->dev->handler = dev_jz4740_int_access;\n    d->dev->reset_handler = dev_jz4740_int_reset;\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n\n    vm_bind_device (vm, d->dev);\n    return (0);\n\n  err_dev_create:\n    free (d);\n    return (-1);\n}\n"
  },
  {
    "path": "tools/virtualmips/jz4740/jz4740_dev_lcd.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#ifdef SIM_LCD\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include<sys/types.h>\n#include<sys/stat.h>\n#include<string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"cpu.h\"\n#include \"jz4740.h\"\n#include \"vp_sdl.h\"\n#include \"vp_timer.h\"\n#include \"utils.h\"\n\nint dev_jz4740_ts_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len, struct DisplayState *ds);\n\n#define LCD_TIMEOUT  500        //MS\n\n#define LCD_WIDTH  480\n#define LCD_HEIGHT  272\n#define LCD_BPP  32             /*32 bit per pixel */\n\nextern cpu_mips_t *current_cpu;\n\nm_uint32_t jz4740_lcd_table[JZ4740_LCD_INDEX_MAX];\nstruct jz_fb_dma_descriptor {\n    m_uint32_t fdadr;           /* Frame descriptor address register */\n    m_uint32_t fsadr;           /* Frame source address register */\n    m_uint32_t fidr;            /* Frame ID register */\n    m_uint32_t ldcmd;           /* Command register */\n\n};\n\nstruct jz4740_lcd_data {\n    struct vdevice *dev;\n    m_uint8_t *jz4740_lcd_ptr;\n    m_uint32_t jz4740_lcd_size;\n    vp_timer_t *lcd_timer;\n    struct DisplayState *ds;\n    m_uint16_t vde, vds, hds, hde;\n};\n\nvoid dev_jz4740_lcd_init_defaultvalue ()\n{\n    memset (jz4740_lcd_table, 0x0, sizeof (jz4740_lcd_table));\n\n}\n\nvoid dev_jz4740_active_lcd (struct jz4740_lcd_data *d)\n{\n    vp_mod_timer (d->lcd_timer, vp_get_clock (rt_clock) + LCD_TIMEOUT);\n}\n\nvoid dev_jz4740_unactive_lcd (struct jz4740_lcd_data *d)\n{\n    vp_del_timer (d->lcd_timer);\n}\n\nvoid dev_jz4740_lcd_reset (cpu_mips_t * cpu, struct vdevice *dev)\n{\n    struct jz4740_lcd_data *d = dev->priv_data;\n    dev_jz4740_lcd_init_defaultvalue ();\n    dev_jz4740_unactive_lcd (d);\n}\n\nvoid *dev_jz4740_lcd_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t * data,\n    m_uint8_t * has_set_value)\n{\n\n    struct jz4740_lcd_data *d = dev->priv_data;\n\n    if ((offset >= d->jz4740_lcd_size)) {\n        *data = 0;\n        return NULL;\n    }\n\n    switch (offset) {\n    case LCD_CTRL:\n        if (op_type == MTS_WRITE) {\n            if (*data & LCD_CTRL_ENA) {\n                dev_jz4740_active_lcd (d);\n            } else {\n                dev_jz4740_unactive_lcd (d);\n                jz4740_lcd_table[LCD_STATE / 4] |= LCD_STATE_QD;\n                 /*INTERRUPT*/ if ((jz4740_lcd_table[LCD_CTRL /\n                            4] & LCD_CTRL_QDM) == 0x0) {\n                    current_cpu->vm->set_irq (current_cpu->vm, IRQ_LCD);\n                }\n\n            }\n\n            if (*data & LCD_CTRL_DIS) {\n                dev_jz4740_unactive_lcd (d);\n                jz4740_lcd_table[LCD_STATE / 4] |= LCD_STATE_LDD;\n                 /*INTERRUPT*/ if ((jz4740_lcd_table[LCD_CTRL /\n                            4] & LCD_CTRL_LDDM) == 0x0) {\n                    current_cpu->vm->set_irq (current_cpu->vm, IRQ_LCD);\n                }\n\n            }\n\n            if ((*data & LCD_CTRL_BPP_MASK) == LCD_CTRL_BPP_16) {\n                d->ds->depth = 16;\n                dpy_resize (d->ds, d->ds->width, d->ds->height);\n\n            } else if ((*data & LCD_CTRL_BPP_MASK) == LCD_CTRL_BPP_18_24) {\n                d->ds->depth = 32;\n                dpy_resize (d->ds, d->ds->width, d->ds->height);\n            } else {\n                ASSERT (0, \"errror bpp \\n\");\n            }\n\n        }\n        break;\n    case LCD_DAH:\n        if (op_type == MTS_WRITE) {\n            d->hde = (*data & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT;\n            d->hds = (*data & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT;\n            ASSERT (d->hde > d->hds, \"hde < hds hde %x hds %x \\n\", d->hde,\n                d->hds);\n            d->ds->width = d->hde - d->hds;\n            ASSERT (d->ds->width > 0, \"d->ds->width<=0  %x  \\n\",\n                d->ds->width);\n            ASSERT (d->ds->height > 0, \"d->ds->height<=0  %x  \\n\",\n                d->ds->height);\n            dpy_resize (d->ds, d->ds->width, d->ds->height);\n\n        }\n        break;\n    case LCD_DAV:\n        if (op_type == MTS_WRITE) {\n            d->vde = (*data & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT;\n            d->vds = (*data & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT;\n            ASSERT (d->vde > d->vds, \"vde < vds vde %x vds %x \\n\", d->vde,\n                d->vds);\n            d->ds->height = d->vde - d->vds;\n            ASSERT (d->ds->width > 0, \"d->ds->width<=0  %x  \\n\",\n                d->ds->width);\n            ASSERT (d->ds->height > 0, \"d->ds->height<=0  %x  \\n\",\n                d->ds->height);\n            dpy_resize (d->ds, d->ds->width, d->ds->height);\n        }\n        break;\n\n    }\n\n    return ((void *) (d->jz4740_lcd_ptr + offset));\n\n}\n\nvoid dev_jz4740_lcd_cb (void *opaque)\n{\n    struct jz4740_lcd_data *d = opaque;\n    struct jz_fb_dma_descriptor *lcda0_desc = NULL;\n    m_uint8_t *src_data;\n    m_uint32_t dummy;\n\n    lcda0_desc =\n        (struct jz_fb_dma_descriptor *) physmem_get_hptr (current_cpu->vm,\n        jz4740_lcd_table[LCD_DA0 / 4], 0, MTS_READ, &dummy);\n    src_data =\n        physmem_get_hptr (current_cpu->vm, lcda0_desc->fsadr, 0, MTS_READ,\n        &dummy);\n\n    ASSERT (src_data != NULL,\n        \"dev_jz4740_lcd_cb can not get framebuffer src data\\n\");\n    jz4740_lcd_table[LCD_SA0 / 4] = lcda0_desc->fsadr;\n    jz4740_lcd_table[LCD_FID0 / 4] = lcda0_desc->fidr;\n    jz4740_lcd_table[LCD_CMD0 / 4] = lcda0_desc->ldcmd;\n\n    ASSERT ((((jz4740_lcd_table[LCD_CTRL / 4] & LCD_CTRL_BPP_MASK) ==\n                LCD_CTRL_BPP_16)\n            || ((jz4740_lcd_table[LCD_CTRL / 4] & LCD_CTRL_BPP_MASK) ==\n                LCD_CTRL_BPP_18_24)), \"Only 15/16/18/24 bpp supproted\\n\");\n    memcpy (d->ds->data, src_data,\n        d->ds->height * d->ds->width * d->ds->depth / 8);\n    dpy_update (d->ds, 0, 0, 0, 0);\n    jz4740_lcd_table[LCD_STATE / 4] |= LCD_STATE_EOF;\n    if ((jz4740_lcd_table[LCD_CMD0 / 4] & LCD_CMD_EOFINT)\n        && ((jz4740_lcd_table[LCD_CTRL / 4] & LCD_CTRL_EOFM) == 0x0)) {\n        current_cpu->vm->set_irq (current_cpu->vm, IRQ_LCD);\n    }\n    dev_jz4740_active_lcd (d);\n\n}\n\nint dev_jz4740_lcd_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len)\n{\n    struct jz4740_lcd_data *d;\n\n    /* allocate the private data structure */\n    if (!(d = malloc (sizeof (*d)))) {\n        fprintf (stderr, \"jz4740_lcd: unable to create device.\\n\");\n        return (-1);\n    }\n\n    memset (d, 0, sizeof (*d));\n    if (!(d->dev = dev_create (name)))\n        goto err_dev_create;\n    d->dev->priv_data = d;\n    d->dev->phys_addr = paddr;\n    d->dev->phys_len = len;\n    d->jz4740_lcd_ptr = (m_uint8_t *) (&jz4740_lcd_table[0]);\n    d->jz4740_lcd_size = len;\n    d->dev->handler = dev_jz4740_lcd_access;\n    d->dev->reset_handler = dev_jz4740_lcd_reset;\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n    d->lcd_timer = vp_new_timer (rt_clock, dev_jz4740_lcd_cb, d);\n\n    d->ds = malloc (sizeof (*d->ds));\n    if (d->ds == NULL)\n        goto err_dev_create;\n    d->ds->width = LCD_WIDTH;\n    d->ds->height = LCD_HEIGHT;\n    d->ds->depth = 32;\n    sdl_display_init (d->ds, 0);\n\n    vm_bind_device (vm, d->dev);\n\n    /*Init jz4740 internal TS */\n    if (dev_jz4740_ts_init (vm, \"JZ4740 TS\", JZ4740_TS_BASE, JZ4740_TS_SIZE,\n            d->ds) == -1)\n        goto err_dev_create;\n\n    return (0);\n\n  err_dev_create:\n    free (d);\n    return (-1);\n}\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/jz4740/jz4740_dev_rtc.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n/*RTC. */\n\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include<sys/types.h>\n#include<sys/stat.h>\n#include<string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"cpu.h\"\n#include \"jz4740.h\"\n#include \"vp_timer.h\"\n\n#define RTC_TIMEOUT  1000       //1000MS=1S\nextern cpu_mips_t *current_cpu;\nm_uint32_t jz4740_rtc_table[JZ4740_RTC_INDEX_MAX];\n\nstruct jz4740_rtc_data {\n    struct vdevice *dev;\n    m_uint8_t *jz4740_rtc_ptr;\n    m_uint32_t jz4740_rtc_size;\n    vp_timer_t *rtc_timer;\n\n};\nstatic const unsigned int sum_monthday[13] = {\n    0,\n    31,\n    31 + 28,\n    31 + 28 + 31,\n    31 + 28 + 31 + 30,\n    31 + 28 + 31 + 30 + 31,\n    31 + 28 + 31 + 30 + 31 + 30,\n    31 + 28 + 31 + 30 + 31 + 30 + 31,\n    31 + 28 + 31 + 30 + 31 + 30 + 31 + 31,\n    31 + 28 + 31 + 30 + 31 + 30 + 31 + 31 + 30,\n    31 + 28 + 31 + 30 + 31 + 30 + 31 + 31 + 30 + 31,\n    31 + 28 + 31 + 30 + 31 + 30 + 31 + 31 + 30 + 31 + 30,\n    365\n};\nstatic const unsigned int yearday[5] =\n    { 0, 366, 366 + 365, 366 + 365 * 2, 366 + 365 * 3 };\nstatic const unsigned int sweekday = 6;\nunsigned int forced_inline jz_mktime (int year, int mon, int day, int hour,\n    int min, int sec)\n{\n    unsigned int seccounter;\n\n    if (year < 2000)\n        year = 2000;\n    year -= 2000;\n    seccounter = (year / 4) * (365 * 3 + 366);\n    seccounter += yearday[year % 4];\n    if (year % 4)\n        seccounter += sum_monthday[mon - 1];\n    else if (mon >= 3)\n        seccounter += sum_monthday[mon - 1] + 1;        /* Feb is 29 days. */\n    else\n        seccounter += sum_monthday[mon - 1];\n    seccounter += day - 1;\n    seccounter *= 24;\n    seccounter += hour;\n    seccounter *= 60;\n    seccounter += min;\n    seccounter *= 60;\n    seccounter += sec;\n\n    return seccounter;\n}\n\n/*Set RTC Time. From Year 2000.*/\nvoid dev_jz4740_rtc_init_defaultvalue ()\n{\n    time_t timep;\n    struct tm *p;\n\n    memset (jz4740_rtc_table, 0x0, sizeof (jz4740_rtc_table));\n    /*Set RTC value to current time */\n    time (&timep);\n    p = localtime (&timep);\n    jz4740_rtc_table[RTC_RSR / 4] =\n        jz_mktime ((1900 + p->tm_year), (1 + p->tm_mon), p->tm_mday,\n        p->tm_hour, p->tm_min, p->tm_sec);\n\n}\n\nvoid dev_jz4740_rtc_reset (cpu_mips_t * cpu, struct vdevice *dev)\n{\n    dev_jz4740_rtc_init_defaultvalue ();\n}\n\nvoid dev_jz4740_active_rtc (struct jz4740_rtc_data *d)\n{\n    vp_mod_timer (d->rtc_timer, vp_get_clock (rt_clock) + RTC_TIMEOUT);\n}\n\nvoid dev_jz4740_unactive_rtc (struct jz4740_rtc_data *d)\n{\n    vp_del_timer (d->rtc_timer);\n}\n\nvoid *dev_jz4740_rtc_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t * data,\n    m_uint8_t * has_set_value)\n{\n\n    struct jz4740_rtc_data *d = dev->priv_data;\n    if (offset >= d->jz4740_rtc_size) {\n        *data = 0;\n        return NULL;\n    }\n\n    switch (offset) {\n    case RTC_RCR:\n        if (op_type == MTS_READ) {\n            /*RTC_RCR (RTC_RCR_WRDY )=1 bit 7 */\n            jz4740_rtc_table[RTC_RCR / 4] |= RTC_RCR_WRDY;\n        } else if (op_type == MTS_WRITE) {\n            if (*data & RTC_RCR_RTCE) {\n                dev_jz4740_active_rtc (d);\n            } else {\n                dev_jz4740_unactive_rtc (d);\n            }\n        }\n        break;\n\n    }\n\n    return ((void *) (d->jz4740_rtc_ptr + offset));\n\n}\n\nvoid dev_jz4740_rtc_cb (void *opaque)\n{\n    struct jz4740_rtc_data *d = opaque;\n    time_t timep;\n    struct tm *p;\n\n    if (jz4740_rtc_table[RTC_RCR / 4] & RTC_RCR_RTCE) {\n        //rtc enable\n        jz4740_rtc_table[RTC_RCR / 4] |= RTC_RCR_1HZ;\n        if (jz4740_rtc_table[RTC_RCR / 4] & RTC_RCR_1HZIE) {\n            current_cpu->vm->set_irq (current_cpu->vm, IRQ_RTC);\n        }\n\n        time (&timep);\n        p = localtime (&timep);\n        /*always get the current time from host */\n        jz4740_rtc_table[RTC_RSR / 4] =\n            jz_mktime ((1900 + p->tm_year), (1 + p->tm_mon), p->tm_mday,\n            p->tm_hour, p->tm_min, p->tm_sec);\n        if (jz4740_rtc_table[RTC_RSR / 4] == jz4740_rtc_table[RTC_RSAR / 4]) {\n            if (jz4740_rtc_table[RTC_RCR / 4] & RTC_RCR_AE) {\n                jz4740_rtc_table[RTC_RCR / 4] |= RTC_RCR_AF;\n                if (jz4740_rtc_table[RTC_RCR / 4] & RTC_RCR_AIE) {\n                    current_cpu->vm->set_irq (current_cpu->vm, IRQ_RTC);\n                }\n            }\n        }\n    }\n    dev_jz4740_active_rtc (d);\n\n}\n\nint dev_jz4740_rtc_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len)\n{\n    struct jz4740_rtc_data *d;\n\n    /* allocate the private data structure */\n    if (!(d = malloc (sizeof (*d)))) {\n        fprintf (stderr, \"jz4740_rtc: unable to create device.\\n\");\n        return (-1);\n    }\n\n    memset (d, 0, sizeof (*d));\n    if (!(d->dev = dev_create (name)))\n        goto err_dev_create;\n    d->dev->priv_data = d;\n    d->dev->phys_addr = paddr;\n    d->dev->phys_len = len;\n    d->jz4740_rtc_ptr = (m_uint8_t *) (&jz4740_rtc_table[0]);\n    d->jz4740_rtc_size = len;\n    d->dev->handler = dev_jz4740_rtc_access;\n    d->dev->reset_handler = dev_jz4740_rtc_reset;\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n    d->rtc_timer = vp_new_timer (rt_clock, dev_jz4740_rtc_cb, d);\n\n    vm_bind_device (vm, d->dev);\n    dev_jz4740_rtc_init_defaultvalue ();\n\n    return (0);\n\n  err_dev_create:\n    free (d);\n    return (-1);\n}\n"
  },
  {
    "path": "tools/virtualmips/jz4740/jz4740_dev_ts.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#ifdef SIM_LCD\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include<sys/types.h>\n#include<sys/stat.h>\n#include<string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"cpu.h\"\n#include \"jz4740.h\"\n#include \"vp_sdl.h\"\n#include \"vp_timer.h\"\n#include \"utils.h\"\n\nextern cpu_mips_t *current_cpu;\n\n#define TSMAXX 4096\n#define TSMAXY 4096\n#define TSMINX  0\n#define TSMINY  0\n\n#define TS_TIMEOUT  15          //MS\nm_uint32_t jz4740_ts_table[JZ4740_TS_INDEX_MAX];\n\n#define MOUSE_DOWN  1\n#define MOUSE_UP       2\n#define MOUSE_MOVE   3\nstruct jz4740_ts_data {\n    struct vdevice *dev;\n    m_uint8_t *jz4740_ts_ptr;\n    m_uint32_t jz4740_ts_size;\n    vp_timer_t *ts_timer;\n\n    m_uint8_t xyz;              /*xyz of cfg */\n    m_uint8_t snum;             /*snum of cfg */\n\n    m_uint8_t read_index;\n    m_uint32_t x, y;\n\n    /*mouse status */\n    m_uint8_t mouse_status;\n\n    struct DisplayState *ds;\n};\n\nvoid dev_jz4740_active_ts (struct jz4740_ts_data *d)\n{\n    vp_mod_timer (d->ts_timer, vp_get_clock (rt_clock) + TS_TIMEOUT);\n}\n\nvoid dev_jz4740_unactive_ts (struct jz4740_ts_data *d)\n{\n    vp_del_timer (d->ts_timer);\n}\n\nvoid dev_jz4740_ts_cb (void *opaque)\n{\n    struct jz4740_ts_data *d = opaque;\n    SDL_Event *ts_ev;\n    if ((jz4740_ts_table[SADC_ENA / 4] & SADC_ENA_TSEN)) {\n        if ((jz4740_ts_table[SADC_CTRL / 4] & SADC_CTRL_PENDM) == 0) {\n            ts_ev = sdl_getmouse_down ();\n            /*Pen down interrupt */\n            if (ts_ev != NULL) {\n                d->x =\n                    ((ts_ev->button.x) * (TSMAXX - TSMINX) / d->ds->width) +\n                    TSMINX;\n                d->y =\n                    ((ts_ev->button.y) * (TSMAXY - TSMINY) / d->ds->height) +\n                    TSMINY;\n                if (d->x > TSMAXX)\n                    d->x = TSMAXX;\n                if (d->y > TSMAXY)\n                    d->y = TSMAXY;\n\n                /*Interrupt */\n                current_cpu->vm->set_irq (current_cpu->vm, IRQ_SADC);\n                jz4740_ts_table[SADC_STATE / 4] |=\n                    (SADC_STATE_PEND | SADC_STATE_TSRDY);\n            }\n        }\n\n        if ((jz4740_ts_table[SADC_CTRL / 4] & SADC_CTRL_PENUM) == 0) {\n            /*Pen UP interrupt */\n            if (d->read_index == 0) {\n                /*\n                 * TODO: Mouse up checking.\n                 * We do not check whether mouse up. JUST assume when clicked, it is always mouseup.\n                 * Can not use hand writing in qtopia.\n                 */\n                /*Interrupt */\n                current_cpu->vm->set_irq (current_cpu->vm, IRQ_SADC);\n                jz4740_ts_table[SADC_STATE / 4] |=\n                    (SADC_STATE_PENU | SADC_STATE_TSRDY);\n\n            }\n        }\n\n    }\n\n    dev_jz4740_active_ts (d);\n\n}\n\nvoid dev_jz4740_ts_init_defaultvalue ()\n{\n    memset (jz4740_ts_table, 0x0, sizeof (jz4740_ts_table));\n\n}\n\nvoid dev_jz4740_ts_reset (cpu_mips_t * cpu, struct vdevice *dev)\n{\n    dev_jz4740_ts_init_defaultvalue ();\n}\n\nvoid *dev_jz4740_ts_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t * data,\n    m_uint8_t * has_set_value)\n{\n\n    struct jz4740_ts_data *d = dev->priv_data;\n\n    if ((offset >= d->jz4740_ts_size)) {\n        *data = 0;\n        return NULL;\n    }\n    switch (offset) {\n    case SADC_ENA:\n        if (op_type == MTS_WRITE) {\n            ASSERT ((*data & SADC_ENA_TSEN),\n                \"Only touche screen model is support in SADC \\n\");\n            if (*data & SADC_ENA_TSEN)\n                dev_jz4740_active_ts (d);\n            else\n                dev_jz4740_unactive_ts (d);\n        }\n        break;\n    case SADC_CFG:\n        if (op_type == MTS_WRITE) {\n            ASSERT ((*data & SADC_CFG_TS_DMA) == 0x0,\n                \"Only touche screen model is support in SADC \\n\");\n            ASSERT ((*data & SADC_CFG_XYZ_MASK) != (3 << SADC_CFG_XYZ_BIT),\n                \"XYZ =3 is not support \\n\");\n            ASSERT ((*data & SADC_CFG_XYZ_MASK) != (2 << SADC_CFG_XYZ_BIT),\n                \"XYZ =2 is not support \\n\");\n\n            d->xyz = (*data & SADC_CFG_XYZ_MASK) >> SADC_CFG_XYZ_BIT;\n            d->snum = ((*data & SADC_CFG_SNUM_MASK) >> SADC_CFG_SNUM_BIT) + 1;\n            /*need read twice */\n            if (d->xyz == 0x1)\n                d->snum *= 2;\n\n            d->read_index = 0;\n\n        }\n        break;\n    case SADC_STATE:\n        if (op_type == MTS_WRITE) {\n            jz4740_ts_table[SADC_STATE / 4] = ~(*data);\n            *has_set_value = TRUE;\n            return NULL;\n        } else {\n            *data = jz4740_ts_table[SADC_STATE / 4] & 0x1f;\n            *data |= SADC_CTRL_TSRDYM;\n            *has_set_value = TRUE;\n            return NULL;\n        }\n        break;\n\n    case SADC_TSDAT:\n        if (op_type == MTS_READ) {\n\n            if ((d->read_index % 2) == 0) {\n                *data = ((d->x) & 0x7fff) | ((d->y & 0x7ffff) << 16);\n            } else {\n                *data = ((500) & 0x7fff);\n            }\n            *has_set_value = TRUE;\n            d->read_index++;\n            if (d->read_index == d->snum)\n                d->read_index = 0;\n            return NULL;\n        }\n        break;\n\n    }\n    return ((void *) (d->jz4740_ts_ptr + offset));\n}\n\nint dev_jz4740_ts_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len, struct DisplayState *ds)\n{\n    struct jz4740_ts_data *d;\n\n    /* allocate the private data structure */\n    if (!(d = malloc (sizeof (*d)))) {\n        fprintf (stderr, \"jz4740_lcd: unable to create device.\\n\");\n        return (-1);\n    }\n\n    memset (d, 0, sizeof (*d));\n    if (!(d->dev = dev_create (name)))\n        goto err_dev_create;\n    d->dev->priv_data = d;\n    d->dev->phys_addr = paddr;\n    d->dev->phys_len = len;\n    d->jz4740_ts_ptr = (m_uint8_t *) (&jz4740_ts_table[0]);\n    d->jz4740_ts_size = len;\n    d->dev->handler = dev_jz4740_ts_access;\n    d->dev->reset_handler = dev_jz4740_ts_reset;\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n    d->ts_timer = vp_new_timer (rt_clock, dev_jz4740_ts_cb, d);\n    d->ds = ds;\n\n    vm_bind_device (vm, d->dev);\n\n    return (0);\n\n  err_dev_create:\n    free (d);\n    return (-1);\n}\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/jz4740/jz4740_dev_uart.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n /*JZ4740 UART Emulation.\n  *\n  * JZ4740 UART is compatible with 16c550 .\n  *\n  * Linux use uart interrupt to receive and send data.\n  *\n  * For simulator, it is a bad idea for os to use interrupt to send data .\n  * Because simulator is always READY for sending, so interrupt is slow than polling.\n  *\n  *\n  * receive:\n  * 1.set IER\n  * 2. Wating interrupt (read IIR and LSR)\n  * 3. if IIR says an interrupt and LSR says that data ready. read RBR.\n  *\n  * send:\n  * 1. set IER to enable transmit request interrupt\n  * 2. if UART can send data, generate an interrupt and set IIR LSR\n  * 3. linux receives the interrupt ,read IIR and LSR\n  * 4. send data.\n  *\n  */\n\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include<sys/types.h>\n#include<sys/stat.h>\n#include<string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"jz4740.h\"\n#include \"cpu.h\"\n#include \"vp_timer.h\"\n\n/* Interrupt Identification Register */\n#define IIR_NPENDING  0x01      /* 0: irq pending, 1: no irq pending */\n#define\tIIR_TXRDY     0x02\n#define\tIIR_RXRDY     0x04\n\nstruct jz4740_uart_data {\n    struct vdevice *dev;\n\n    u_int irq, duart_irq_seq;\n    u_int output;\n\n    vtty_t *vtty;\n    vm_instance_t *vm;\n\n    m_uint32_t ier;             /*0x04 */\n    m_uint32_t iir;             /*0x08 */\n    m_uint32_t fcr;             /*0x08 */\n    m_uint32_t lcr;             /*0x0c */\n    m_uint32_t mcr;             /*0x10 */\n    m_uint32_t lsr;             /*0x14 */\n    m_uint32_t msr;             /*0x18 */\n    m_uint32_t spr;             /*0x1c */\n    m_uint32_t isr;             /*0x20 */\n    m_uint32_t umr;             /*0x24 */\n    m_uint32_t uacr;            /*0x28 */\n\n    m_uint32_t jz4740_uart_size;\n\n    vp_timer_t *uart_timer;\n\n};\n\nstatic void jz4740_tty_con_input (vtty_t * vtty)\n{\n    struct jz4740_uart_data *d = vtty->priv_data;\n\n    if (d->ier & UART_IER_RDRIE) {\n        d->vm->set_irq (d->vm, d->irq);\n    }\n    d->lsr |= UART_LSR_DRY;\n\n}\n\nvoid *dev_jz4740_uart_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t * data,\n    m_uint8_t * has_set_value)\n{\n    struct jz4740_uart_data *d = dev->priv_data;\n\n    u_char odata;\n\n    if (offset >= d->jz4740_uart_size) {\n        *data = 0;\n        return NULL;\n    }\n\n    switch (offset) {\n    case UART_RBR:             /*0x0 RBR THR */\n        if (op_type == MTS_READ) {\n\n            *data = vtty_get_char (d->vtty);\n            if (vtty_is_char_avail (d->vtty))\n                d->lsr |= UART_LSR_DRY;\n            else\n                d->lsr &= ~UART_LSR_DRY;\n        } else {\n            vtty_put_char (d->vtty, (char) (*data));\n            if ((d->ier & UART_IER_TDRIE) && (d->output == 0)\n                && (d->fcr & 0x10)) {\n                /*yajin.\n                 *\n                 * In order to put the next data more quickly, just set irq not waiting for host_alarm_handler to set irq.\n                 * Sorry uart, too much work for you.\n                 *\n                 * Sometimes, linux kernel prints \"serial8250: too much work for irq9\" if we print large data on screen.\n                 * Please patch the kernel. comment \"printk(KERN_ERR \"serial8250: too much work for \"\n                 * \"irq%d\\n\", irq);\"\n                 * qemu has some question.\n                 * http://lkml.org/lkml/2008/1/12/135\n                 * http://kerneltrap.org/mailarchive/linux-kernel/2008/2/7/769924\n                 *\n                 * If jit is used in future, we may not need to set irq here because simulation is quick enough. Then we have\n                 * no \"too much work for irq9\" problem.\n                 *\n                 *\n                 */\n                d->output = TRUE;\n                d->vm->set_irq (d->vm, d->irq);\n            }\n\n        }\n\n        *has_set_value = TRUE;\n        break;\n\n    case UART_IER:             /*0x4 */\n        if (op_type == MTS_READ) {\n            *data = d->ier;\n        } else {\n            d->ier = *data & 0xFF;\n        }\n\n        *has_set_value = TRUE;\n        break;\n\n    case UART_IIR:             /*0x08 */\n        d->vm->clear_irq (d->vm, d->irq);\n        if (op_type == MTS_READ) {\n            odata = IIR_NPENDING;\n\n            if (vtty_is_char_avail (d->vtty)) {\n                odata = IIR_RXRDY;\n            } else {\n                if (d->output) {\n                    odata = IIR_TXRDY;\n                    d->output = 0;\n                }\n\n            }\n            *data = odata;\n        } else {\n            d->fcr = *data;\n            if (d->fcr & 0x20)\n                d->lsr &= ~UART_LSR_DRY;\n        }\n\n        *has_set_value = TRUE;\n        break;\n\n    case UART_LSR:             /*0x14 */\n        if (op_type == MTS_READ) {\n            d->lsr |= UART_LSR_TDRQ | UART_LSR_TEMP;\n            if (vtty_is_char_avail (d->vtty))\n                d->lsr |= UART_LSR_DRY;\n            return &(d->lsr);\n        } else\n            ASSERT (0, \"WRITE TO LSR\\n\");\n        *has_set_value = TRUE;\n        break;\n\n    case UART_LCR:\n        return &(d->lcr);\n    case UART_MCR:\n        return &(d->mcr);\n    case UART_MSR:\n        return &(d->msr);\n    case UART_SPR:\n        return &(d->spr);\n    case UART_ISR:\n        return &(d->isr);\n    case UART_UMR:\n        return &(d->umr);\n    case UART_UACR:\n        return &(d->uacr);\n\n    default:\n        ASSERT (0, \"invalid uart offset %x\\n\", offset);\n\n    }\n\n    return NULL;\n\n}\n\nvoid dev_jz4740_uart_reset (cpu_mips_t * cpu, struct vdevice *dev)\n{\n\n    struct jz4740_uart_data *d = dev->priv_data;\n    d->fcr = 0x0;\n    d->lcr = 0x0;\n    d->mcr = 0x0;\n    d->lsr |= UART_LSR_TDRQ | UART_LSR_TEMP;\n    d->msr = 0x0;\n    d->spr = 0x0;\n    d->isr = 0x0;\n    d->umr = 0x0;\n    d->uacr = 0x0;\n\n}\n\nextern cpu_mips_t *current_cpu;\n\n#define UART_TIME_OUT     25\nvoid dev_jz4740_uart_cb (void *opaque)\n{\n\n    struct jz4740_uart_data *d = (struct jz4740_uart_data *) opaque;\n\n    d->output = 0;\n    if (vtty_is_char_avail (d->vtty)) {\n        d->lsr |= UART_LSR_DRY;\n        if (d->ier & UART_IER_RDRIE) {\n            d->vm->set_irq (d->vm, d->irq);\n            vp_mod_timer (d->uart_timer,\n                vp_get_clock (rt_clock) + UART_TIME_OUT);\n            return;\n        }\n\n    }\n    if ((d->ier & UART_IER_TDRIE) && (d->output == 0) && (d->fcr & 0x10)) {\n        d->output = TRUE;\n        d->vm->set_irq (d->vm, d->irq);\n        vp_mod_timer (d->uart_timer, vp_get_clock (rt_clock) + UART_TIME_OUT);\n        return;\n    }\n    // d->uart_timer->set_time=vp_get_clock(rt_clock);\n    vp_mod_timer (d->uart_timer, vp_get_clock (rt_clock) + UART_TIME_OUT);\n\n}\n\nint dev_jz4740_uart_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len, u_int irq, vtty_t * vtty)\n{\n    struct jz4740_uart_data *d;\n\n    /* allocate the private data structure */\n    if (!(d = malloc (sizeof (*d)))) {\n        fprintf (stderr, \"JZ4740 UART: unable to create device.\\n\");\n        return (-1);\n    }\n    memset (d, 0, sizeof (*d));\n    if (!(d->dev = dev_create (name)))\n        goto err_dev_create;\n    d->dev->priv_data = d;\n    d->dev->phys_addr = paddr;\n    d->dev->phys_len = len;\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n    d->vm = vm;\n    (*d).vtty = vtty;\n    d->irq = irq;\n    vtty->priv_data = d;\n    d->jz4740_uart_size = len;\n    d->dev->handler = dev_jz4740_uart_access;\n    d->dev->reset_handler = dev_jz4740_uart_reset;\n    (*d).vtty->read_notifier = jz4740_tty_con_input;\n    d->uart_timer = vp_new_timer (rt_clock, dev_jz4740_uart_cb, d);\n\n    //d->uart_timer->set_time=vp_get_clock(rt_clock);\n    vp_mod_timer (d->uart_timer, vp_get_clock (rt_clock) + UART_TIME_OUT);\n\n    vm_bind_device (vm, d->dev);\n\n    return (0);\n\n  err_dev_create:\n    free (d);\n    return (-1);\n}\n"
  },
  {
    "path": "tools/virtualmips/jz4740/jz4740_dev_wdt_tcu.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n /* Watch dog and timer of JZ4740.\n  * TODO:\n  * 2. timer1-5\n  */\n\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include<sys/types.h>\n#include<sys/stat.h>\n#include<string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"cpu.h\"\n#include \"jz4740.h\"\n#include \"vp_timer.h\"\n#include \"vp_clock.h\"\n\n#define  VALIDE_WDT_TCU_OPERATION 0\nextern cpu_mips_t *current_cpu;\nm_uint32_t jz4740_wdt_tcu_table[JZ4740_WDT_INDEX_MAX];\n\n/*4:EXT 2:RTC 1:PCK*/\n//m_uint8_t jz4740_tcu_clock_source[JZ4740_WDT_INDEX_MAX];\n//m_uint32_t jz4740_tcu_clock_prescale[JZ4740_WDT_INDEX_MAX];\n\n/*clocksource/prescale*/\nm_uint64_t jz4740_tcu_clock[JZ4740_WDT_INDEX_MAX];\nm_uint64_t jz4740_wdt_clock;\n\nstruct jz4740_wdt_tcu_data {\n    struct vdevice *dev;\n    m_uint8_t *jz4740_wdt_tcu_ptr;\n    m_uint32_t jz4740_wdt_tcu_size;\n    vp_timer_t *tcu_timer[JZ4740_WDT_INDEX_MAX];\n    vp_timer_t *wdt_timer;\n};\n\n/*fire timer0 every 10ms*/\nvoid dev_jz4740_tcu_active_timer0 (struct jz4740_wdt_tcu_data *d)\n{\n    d->tcu_timer[0]->set_time = vp_get_clock (rt_clock);\n    vp_mod_timer (d->tcu_timer[0], vp_get_clock (rt_clock) + 10);\n}\n\nvoid dev_jz4740_tcu_unactive_timer0 (struct jz4740_wdt_tcu_data *d)\n{\n    vp_del_timer (d->tcu_timer[0]);\n}\n\nvoid dev_jz4740_active_wdt (struct jz4740_wdt_tcu_data *d)\n{\n    d->wdt_timer->set_time = vp_get_clock (rt_clock);\n    vp_mod_timer (d->wdt_timer, vp_get_clock (rt_clock) + 10);\n}\n\nvoid dev_jz4740_unactive_wdt (struct jz4740_wdt_tcu_data *d)\n{\n    vp_del_timer (d->wdt_timer);\n}\n\nvoid *dev_jz4740_wdt_tcu_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type,\n    m_reg_t * data, m_uint8_t * has_set_value)\n{\n\n    struct jz4740_wdt_tcu_data *d = dev->priv_data;\n    m_uint32_t mask_data, mask;\n    int clock_index;\n    //m_uint64_t clock;\n\n    if (offset >= d->jz4740_wdt_tcu_size) {\n        *data = 0;\n        return NULL;\n    }\n#if  VALIDE_WDT_TCU_OPERATION\n    if (op_type == MTS_WRITE) {\n        ASSERT (offset != TCU_TSR,\n            \"Write to read only register in TCU. offset %x\\n\", offset);\n        ASSERT (offset != TCU_TER,\n            \"Write to read only register in TCU. offset %x\\n\", offset);\n        ASSERT (offset != TCU_TFR,\n            \"Write to read only register in TCU. offset %x\\n\", offset);\n        ASSERT (offset != TCU_TMR,\n            \"Write to read only register in TCU. offset %x\\n\", offset);\n    } else if (op_type == MTS_READ) {\n        ASSERT (offset != TCU_TSSR,\n            \"Read write only register in TCU. offset %x\\n\", offset);\n        ASSERT (offset != TCU_TSCR,\n            \"Read write only register in TCU. offset %x\\n\", offset);\n        ASSERT (offset != TCU_TESR,\n            \"Read write only register in TCU. offset %x\\n\", offset);\n        ASSERT (offset != TCU_TECR,\n            \"Read write only register in TCU. offset %x\\n\", offset);\n        ASSERT (offset != TCU_TFSR,\n            \"Read write only register in TCU. offset %x\\n\", offset);\n        ASSERT (offset != TCU_TFCR,\n            \"Read write only register in TCU. offset %x\\n\", offset);\n        ASSERT (offset != TCU_TMSR,\n            \"Read write only register in TCU. offset %x\\n\", offset);\n        ASSERT (offset != TCU_TMCR,\n            \"Read write only register in TCU. offset %x\\n\", offset);\n    } else\n        assert (0);\n#endif\n    switch (op_size) {\n    case 1:\n        mask = 0xff;\n        break;\n    case 2:\n        mask = 0xffff;\n        break;\n    case 4:\n        mask = 0xffffffff;\n        break;\n    default:\n        assert (0);\n    }\n\n    switch (offset) {\n    case TCU_TSSR:             /*set */\n\n        assert (op_type == MTS_WRITE);\n        mask_data = (*data) & mask;\n        jz4740_wdt_tcu_table[TCU_TSR / 4] |= mask_data;\n        *has_set_value = TRUE;\n        if (jz4740_wdt_tcu_table[TCU_TSR / 4] & 0x01)\n            dev_jz4740_tcu_unactive_timer0 (d);\n        if (jz4740_wdt_tcu_table[TCU_TSR / 4] & WDT_TIMER_STOP)\n            dev_jz4740_unactive_wdt (d);\n\n        break;\n    case TCU_TSCR:             /*clear */\n        assert (op_type == MTS_WRITE);\n        mask_data = (*data) & mask;\n        mask_data = ~(mask_data);\n        jz4740_wdt_tcu_table[TCU_TSR / 4] &= mask_data;\n        *has_set_value = TRUE;\n        if ((!jz4740_wdt_tcu_table[TCU_TSR / 4] & 0x01)\n            && (jz4740_wdt_tcu_table[TCU_TER / 4] & 0x01))\n            dev_jz4740_tcu_active_timer0 (d);\n        if (unlikely (jz4740_wdt_tcu_table[WDT_TCER / 4] & 0x01)\n            && (!(jz4740_wdt_tcu_table[TCU_TSR / 4] & WDT_TIMER_STOP)))\n            dev_jz4740_active_wdt (d);\n        break;\n\n    case TCU_TESR:             /*set */\n        assert (op_type == MTS_WRITE);\n        mask_data = (*data) & mask;\n        jz4740_wdt_tcu_table[TCU_TER / 4] |= mask_data;\n        *has_set_value = TRUE;\n        if ((!jz4740_wdt_tcu_table[TCU_TSR / 4] & 0x01)\n            && (jz4740_wdt_tcu_table[TCU_TER / 4] & 0x01))\n            dev_jz4740_tcu_active_timer0 (d);\n        break;\n    case TCU_TECR:             /*clear */\n        assert (op_type == MTS_WRITE);\n        mask_data = (*data) & mask;\n        mask_data = ~(mask_data);\n        jz4740_wdt_tcu_table[TCU_TER / 4] &= mask_data;\n        *has_set_value = TRUE;\n        if (!(jz4740_wdt_tcu_table[TCU_TER / 4] & 0x01))\n            dev_jz4740_tcu_unactive_timer0 (d);\n        break;\n\n    case TCU_TFSR:             /*set */\n        assert (op_type == MTS_WRITE);\n        mask_data = (*data) & mask;\n        jz4740_wdt_tcu_table[TCU_TFR / 4] |= mask_data;\n        *has_set_value = TRUE;\n        break;\n    case TCU_TFCR:             /*clear */\n        assert (op_type == MTS_WRITE);\n        mask_data = (*data) & mask;\n        mask_data = ~(mask_data);\n        jz4740_wdt_tcu_table[TCU_TFR / 4] &= mask_data;\n        *has_set_value = TRUE;\n        break;\n\n    case TCU_TMSR:             /*set */\n        assert (op_type == MTS_WRITE);\n        mask_data = (*data) & mask;\n        jz4740_wdt_tcu_table[TCU_TMR / 4] |= mask_data;\n        *has_set_value = TRUE;\n        break;\n    case TCU_TMCR:             /*clear */\n        assert (op_type == MTS_WRITE);\n        mask_data = (*data) & mask;\n        mask_data = ~(mask_data);\n        jz4740_wdt_tcu_table[TCU_TMR / 4] &= mask_data;\n        *has_set_value = TRUE;\n        break;\n    case TCU_TCSR0:\n    case TCU_TCSR1:\n    case TCU_TCSR2:\n    case TCU_TCSR3:\n    case TCU_TCSR4:\n    case TCU_TCSR5:\n        if (op_type == MTS_WRITE) {\n            clock_index = (offset - TCU_TCSR0) / 0x10;\n            if (((*data) & TCU_CLOCK_SOUCE_MASK) == TCU_CLOCK_EXT) {\n                jz4740_tcu_clock[clock_index] = EXT_CLOCK;\n\n            } else if (((*data) & TCU_CLOCK_SOUCE_MASK) == TCU_CLOCK_RTC) {\n                jz4740_tcu_clock[clock_index] = RTC_CLOCK;\n            } else\n                ASSERT (0, \"RTC and EXT clock is supported \\n\");\n\n            if ((((*data) & TCU_CLOCK_PRESCALE_MASK) >>\n                    TCU_CLOCK_PRESCALE_OFFSET) == 0x1)\n                jz4740_tcu_clock[clock_index] =\n                    jz4740_tcu_clock[clock_index] / 4;\n            else if ((((*data) & TCU_CLOCK_PRESCALE_MASK) >>\n                    TCU_CLOCK_PRESCALE_OFFSET) == 0x2)\n                jz4740_tcu_clock[clock_index] =\n                    jz4740_tcu_clock[clock_index] / 16;\n            else if ((((*data) & TCU_CLOCK_PRESCALE_MASK) >>\n                    TCU_CLOCK_PRESCALE_OFFSET) == 0x3)\n                jz4740_tcu_clock[clock_index] =\n                    jz4740_tcu_clock[clock_index] / 64;\n            else if ((((*data) & TCU_CLOCK_PRESCALE_MASK) >>\n                    TCU_CLOCK_PRESCALE_OFFSET) == 0x4)\n                jz4740_tcu_clock[clock_index] =\n                    jz4740_tcu_clock[clock_index] / 256;\n            else if ((((*data) & TCU_CLOCK_PRESCALE_MASK) >>\n                    TCU_CLOCK_PRESCALE_OFFSET) == 0x5)\n                jz4740_tcu_clock[clock_index] =\n                    jz4740_tcu_clock[clock_index] / 1024;\n            else if ((((*data) & TCU_CLOCK_PRESCALE_MASK) >>\n                    TCU_CLOCK_PRESCALE_OFFSET) != 0x0)\n                ASSERT (0, \"INVALID PRESCALE\\n\");\n\n        }\n        return ((void *) (d->jz4740_wdt_tcu_ptr + offset));\n\n    case WDT_TCSR:\n        if (op_type == MTS_WRITE) {\n            if (((*data) & WDT_CLOCK_SOUCE_MASK) == WDT_CLOCK_EXT) {\n                jz4740_wdt_clock = EXT_CLOCK;\n            } else if (((*data) & WDT_CLOCK_SOUCE_MASK) == WDT_CLOCK_RTC)\n                jz4740_wdt_clock = RTC_CLOCK;\n            else\n                ASSERT (0, \"RTC and EXT clock is supported \\n\");\n\n            if ((((*data) & WDT_CLOCK_PRESCALE_MASK) >>\n                    WDT_CLOCK_PRESCALE_OFFSET) == 0x1)\n                jz4740_wdt_clock = jz4740_wdt_clock / 4;\n            else if ((((*data) & WDT_CLOCK_PRESCALE_MASK) >>\n                    WDT_CLOCK_PRESCALE_OFFSET) == 0x2)\n                jz4740_wdt_clock = jz4740_wdt_clock / 16;\n            else if ((((*data) & WDT_CLOCK_PRESCALE_MASK) >>\n                    WDT_CLOCK_PRESCALE_OFFSET) == 0x3)\n                jz4740_wdt_clock = jz4740_wdt_clock / 64;\n            else if ((((*data) & WDT_CLOCK_PRESCALE_MASK) >>\n                    WDT_CLOCK_PRESCALE_OFFSET) == 0x4)\n                jz4740_wdt_clock = jz4740_wdt_clock / 256;\n            else if ((((*data) & WDT_CLOCK_PRESCALE_MASK) >>\n                    WDT_CLOCK_PRESCALE_OFFSET) == 0x5)\n                jz4740_wdt_clock = jz4740_wdt_clock / 1024;\n            else if ((((*data) & WDT_CLOCK_PRESCALE_MASK) >>\n                    WDT_CLOCK_PRESCALE_OFFSET) != 0x0)\n                ASSERT (0, \"INVALID PRESCALE %x \\n\", *data);\n\n        }\n        return ((void *) (d->jz4740_wdt_tcu_ptr + offset));\n\n    case WDT_TCER:\n        if (op_type == MTS_WRITE) {\n            jz4740_wdt_tcu_table[WDT_TCER / 4] = (*data) & 0x1;\n            *has_set_value = TRUE;\n            if (unlikely (jz4740_wdt_tcu_table[WDT_TCER / 4] & 0x01)\n                && (!(jz4740_wdt_tcu_table[TCU_TSR / 4] & WDT_TIMER_STOP)))\n                dev_jz4740_active_wdt (d);\n            else\n                dev_jz4740_unactive_wdt (d);\n        } else\n            return ((void *) (d->jz4740_wdt_tcu_ptr + offset));\n\n    default:\n        return ((void *) (d->jz4740_wdt_tcu_ptr + offset));\n\n    }\n\n    return NULL;\n\n}\n\nvoid dev_jz4740_wdt_tcu_init_defaultvalue ()\n{\n\n    memset (jz4740_wdt_tcu_table, 0x0, sizeof (jz4740_wdt_tcu_table));\n\n    jz4740_wdt_tcu_table[TCU_TDFR0 / 4] = 0X7FF8;\n    jz4740_wdt_tcu_table[TCU_TDHR0 / 4] = 0X7FF7;\n    jz4740_wdt_tcu_table[TCU_TCNT0 / 4] = 0X7FF7;\n\n    jz4740_wdt_tcu_table[TCU_TDFR1 / 4] = 0X7FF8;\n    jz4740_wdt_tcu_table[TCU_TDHR1 / 4] = 0X7FF7;\n    jz4740_wdt_tcu_table[TCU_TCNT1 / 4] = 0X7FF7;\n\n    jz4740_wdt_tcu_table[TCU_TDFR2 / 4] = 0X7FF8;\n    jz4740_wdt_tcu_table[TCU_TDHR2 / 4] = 0X7FF7;\n    jz4740_wdt_tcu_table[TCU_TCNT2 / 4] = 0X7FF7;\n\n    jz4740_wdt_tcu_table[TCU_TDFR3 / 4] = 0X7FF8;\n    jz4740_wdt_tcu_table[TCU_TDHR3 / 4] = 0X7FF7;\n    jz4740_wdt_tcu_table[TCU_TCNT3 / 4] = 0X7FF7;\n\n    jz4740_wdt_tcu_table[TCU_TDFR4 / 4] = 0X7FF8;\n    jz4740_wdt_tcu_table[TCU_TDHR4 / 4] = 0X7FF7;\n    jz4740_wdt_tcu_table[TCU_TCNT4 / 4] = 0X7FF7;\n\n    jz4740_wdt_tcu_table[TCU_TDFR5 / 4] = 0X7FF8;\n    jz4740_wdt_tcu_table[TCU_TDHR5 / 4] = 0X7FF7;\n    jz4740_wdt_tcu_table[TCU_TCNT5 / 4] = 0X7FF7;\n}\n\nvoid dev_jz4740_wdt_tcu_reset (cpu_mips_t * cpu, struct vdevice *dev)\n{\n    dev_jz4740_wdt_tcu_init_defaultvalue ();\n}\n\nint gasdf;\nint reset_request = 0;\n\n/*10ms*/\nvoid dev_jz4740_wdt_cb (void *opaque)\n{\n    m_int64_t current;\n    m_uint32_t past_time;\n\n    struct jz4740_wdt_tcu_data *d = (struct jz4740_wdt_tcu_data *) opaque;\n    if (unlikely (jz4740_wdt_tcu_table[WDT_TCER / 4] & 0x01)\n        && (!(jz4740_wdt_tcu_table[TCU_TSR / 4] & WDT_TIMER_STOP))) {\n        current = vp_get_clock (rt_clock);\n        past_time = current - d->tcu_timer[0]->set_time;\n\n        {\n            jz4740_wdt_tcu_table[WDT_TCNT / 4] += (jz4740_wdt_clock) / 100;\n\n            if (jz4740_wdt_tcu_table[WDT_TCNT / 4] >=\n                jz4740_wdt_tcu_table[WDT_TDR / 4]) {\n                /*RESET soc */\n                cpu_restart (current_cpu);\n                jz4740_reset (current_cpu->vm);\n            }\n        }\n    }\n    dev_jz4740_active_wdt (d);\n\n}\n\n/*10ms\nLinux uses 100HZ timer, so we fire tcu every 10 ms.\n1ms ->  jz4740_wdt_tcu_table[TCU_TCNT0/4]+= jz4740_tcu_clock[0])/1000; */\nvoid dev_jz4740_tcu_cb (void *opaque)\n{\n    struct jz4740_wdt_tcu_data *d = (struct jz4740_wdt_tcu_data *) opaque;\n\n    m_int64_t current;\n    m_uint32_t past_time;\n    current = vp_get_clock (rt_clock);\n    past_time = current - d->tcu_timer[0]->set_time;\n\n    jz4740_wdt_tcu_table[TCU_TCNT0 / 4] +=\n        (past_time * jz4740_tcu_clock[0]) / 1000;\n    jz4740_wdt_tcu_table[TCU_TCNT0 / 4] &= 0xffff;\n\n    if (jz4740_wdt_tcu_table[TCU_TCNT0 / 4] >=\n        jz4740_wdt_tcu_table[TCU_TDHR0 / 4]) {\n        /*set TFR */\n        jz4740_wdt_tcu_table[TCU_TFR / 4] |= 1 << 16;\n        if (!(jz4740_wdt_tcu_table[TCU_TMR / 4] & (1 << 16)))\n            current_cpu->vm->set_irq (current_cpu->vm, IRQ_TCU0);\n    }\n    if (jz4740_wdt_tcu_table[TCU_TCNT0 / 4] >=\n        jz4740_wdt_tcu_table[TCU_TDFR0 / 4]) {\n        jz4740_wdt_tcu_table[TCU_TFR / 4] |= 1;\n        if (!(jz4740_wdt_tcu_table[TCU_TMR / 4] & (0x1))) {\n            current_cpu->vm->set_irq (current_cpu->vm, IRQ_TCU0);\n        }\n        jz4740_wdt_tcu_table[TCU_TCNT0 / 4] = 0;\n    }\n\n    dev_jz4740_tcu_active_timer0 (d);\n\n}\n\nint dev_jz4740_wdt_tcu_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len)\n{\n    struct jz4740_wdt_tcu_data *d;\n\n    /* allocate the private data structure */\n    if (!(d = malloc (sizeof (*d)))) {\n        fprintf (stderr, \"jz4740_wdt_tcu: unable to create device.\\n\");\n        return (-1);\n    }\n\n    memset (d, 0, sizeof (*d));\n    if (!(d->dev = dev_create (name)))\n        goto err_dev_create;\n    d->dev->priv_data = d;\n    d->dev->phys_addr = paddr;\n    d->dev->phys_len = len;\n    d->jz4740_wdt_tcu_ptr = (m_uint8_t *) (&jz4740_wdt_tcu_table[0]);\n    d->jz4740_wdt_tcu_size = len;\n    d->dev->handler = dev_jz4740_wdt_tcu_access;\n    d->dev->reset_handler = dev_jz4740_wdt_tcu_reset;\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n\n    /*only emulate timer0 */\n    d->tcu_timer[0] = vp_new_timer (rt_clock, dev_jz4740_tcu_cb, d);\n    d->wdt_timer = vp_new_timer (rt_clock, dev_jz4740_wdt_cb, d);\n\n    vm_bind_device (vm, d->dev);\n\n    return (0);\n\n  err_dev_create:\n    free (d);\n    return (-1);\n}\n\n#if 0\n\n/*-------------Virtual Timer and WDT Timer----------------------*/\nm_uint32_t past_instructions = 0;\n//m_uint32_t   past_instructions[6];\n/*TODO:need to adjust*/\n#define COUNT_PER_INSTRUCTION   0x80    //0X180\n\n/*JUST TIMER 0*/\nvoid forced_inline virtual_jz4740_timer (cpu_mips_t * cpu)\n{\n\n    if (unlikely (jz4740_wdt_tcu_table[TCU_TSR / 4] & 0x01)) {\n        return;\n    }\n    if (likely (jz4740_wdt_tcu_table[TCU_TER / 4] & 0x01)) {\n        //allow counter\n        past_instructions++;\n        if (past_instructions == COUNT_PER_INSTRUCTION) {\n            jz4740_wdt_tcu_table[TCU_TCNT0 / 4] += 1;\n            if (jz4740_wdt_tcu_table[TCU_TCNT0 / 4] ==\n                jz4740_wdt_tcu_table[TCU_TDHR0 / 4]) {\n                /*set TFR */\n                jz4740_wdt_tcu_table[TCU_TFR / 4] |= 1 << 16;\n                if (!(jz4740_wdt_tcu_table[TCU_TMR / 4] & (1 << 16)))\n                    cpu->vm->set_irq (cpu->vm, IRQ_TCU0);\n            }\n            if (jz4740_wdt_tcu_table[TCU_TCNT0 / 4] ==\n                jz4740_wdt_tcu_table[TCU_TDFR0 / 4]) {\n                jz4740_wdt_tcu_table[TCU_TFR / 4] |= 1;\n                if (!(jz4740_wdt_tcu_table[TCU_TMR / 4] & (0x1))) {\n                    cpu->vm->set_irq (cpu->vm, IRQ_TCU0);\n                }\n\n                jz4740_wdt_tcu_table[TCU_TCNT0 / 4] = 0;\n            }\n            past_instructions = 0;\n\n        }\n    }\n\n}\n\nm_uint32_t wdt_past_instructions = 0;\n\nvoid forced_inline virtual_jz4740_wdt (cpu_mips_t * cpu)\n{\n\n    if (likely (jz4740_wdt_tcu_table[TCU_TSR / 4] & WDT_TIMER_STOP)) {\n        return;\n    }\n\n    if (unlikely (jz4740_wdt_tcu_table[WDT_TCER / 4] & 0x01)) {\n\n        wdt_past_instructions++;\n        if (wdt_past_instructions >= COUNT_PER_INSTRUCTION) {\n            jz4740_wdt_tcu_table[WDT_TCNT / 4] += 1;\n            wdt_past_instructions = 0;\n            if (jz4740_wdt_tcu_table[WDT_TCNT / 4] & 0xffff0000)\n                jz4740_wdt_tcu_table[WDT_TCNT / 4] = 0;\n\n            if (jz4740_wdt_tcu_table[WDT_TCNT / 4] >=\n                jz4740_wdt_tcu_table[WDT_TDR / 4]) {\n                /*RESET soc */\n                cpu_stop (cpu);\n                cpu->cpu_thread_running = FALSE;\n                jz4740_reset (cpu->vm);\n\n            }\n        }\n\n    }\n\n}\n\nvoid forced_inline virtual_timer (cpu_mips_t * cpu)\n{\n    virtual_jz4740_timer (cpu);\n    virtual_jz4740_wdt (cpu);\n}\n#endif\n"
  },
  {
    "path": "tools/virtualmips/m4k.c",
    "content": "/*\n * Simulation of generic M4K core.\n *\n * Copyright (C) 2015 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#define _GNU_SOURCE\n#include <string.h>\n#include <assert.h>\n#include <stdlib.h>\n\n#include \"vp_lock.h\"\n#include \"utils.h\"\n#include \"mips.h\"\n#include \"vm.h\"\n#include \"cpu.h\"\n#include \"mips_exec.h\"\n#include \"debug.h\"\n\n#include \"m4k.h\"\n#include \"device.h\"\n#include \"mips_jit.h\"\n\n#define BOOT_RAM_KBYTES 64      /* Size of boot RAM area */\n\n/*\n * Store a word to the physical memory.\n */\nint store_word (vm_instance_t *vm, m_pa_t paddr, unsigned data)\n{\n    struct vdevice *dev = dev_lookup (vm, paddr);\n    char *ptr;\n\n    if (! dev)\n        return -1;\n\n    /* Only for RAM */\n    ptr = (char *) dev->host_addr + (paddr - dev->phys_addr);\n    *(m_uint32_t*) ptr = data;\n    return 0;\n}\n\n/*\n * Load MIPS hex file into memory.\n */\nstatic void load_hex_file (struct vm_instance *vm, const char *filename)\n{\n    FILE *fp;\n    char buf [64], *p, *ep;\n    unsigned address, end_address, data, big_endian = 0;\n\n    fp = fopen (filename, \"r\");\n    if (! fp) {\n        fprintf (stderr, \"%s: Cannot open\\n\", filename);\n        exit (-1);\n    }\n    while (fgets (buf, sizeof(buf), fp) != 0) {\n        /* Check header for endian */\n        if (buf[0] == '#') {\n            if (strncmp (buf, \"# Endian Big\", 12) == 0) {\n                big_endian = 1;\n            }\n            continue;\n        }\n        address = strtoul (buf, &ep, 16);\n        if (ep == buf || *ep == 0) {\n            continue;\n        }\n        if (*ep == '-') {\n            p = ep+1;\n            end_address = strtoul (p, &ep, 16);\n            if (ep == p || *ep != ' ') {\n                continue;\n            }\n        } else\n            end_address = address;\n        p = ep;\n        data = strtoul (p, &ep, 16);\n        if (ep == p) {\n            continue;\n        }\n\n        /* Byte swap. */\n        if (big_endian) {\n            data = (data & 0x000000ff) << 24 |\n                   (data & 0x0000ff00) <<  8 |\n                   (data & 0x00ff0000) >>  8 |\n                   (data & 0xff000000) >> 24 ;\n        }\n\n        do {\n            if (store_word (vm, address << 2, data) < 0) {\n                fprintf (stderr, \"%s: No memory at physical address %08x\\n\",\n                    filename, address << 2);\n                exit (-1);\n            }\n            //printf (\"  %08x <= %08x\\n\", address << 2, data);\n        } while (address++ < end_address);\n    }\n    fclose (fp);\n}\n\n/*\n * Initialize the M4K platform.\n */\nstatic int m4k_init_platform (m4k_t *m4k)\n{\n    struct vm_instance *vm = m4k->vm;\n    cpu_mips_t *cpu0;\n    void *(*cpu_run_fn) (void *);\n\n    //vm_init_vtty (vm);\n\n    /* Create a CPU group */\n    vm->cpu_group = cpu_group_create (\"System CPU\");\n\n    /* Initialize the virtual MIPS processor */\n    cpu0 = cpu_create (vm, CPU_TYPE_MIPS32, 0);\n    if (! cpu0) {\n        vm_error (vm, \"unable to create CPU0!\\n\");\n        return (-1);\n    }\n    /* Add this CPU to the system CPU group */\n    cpu_group_add (vm->cpu_group, cpu0);\n    vm->boot_cpu = cpu0;\n\n    /* create the CPU thread execution */\n    cpu_run_fn = (void *) mips_exec_run_cpu;\n    if (pthread_create (&cpu0->cpu_thread, NULL, cpu_run_fn, cpu0) != 0) {\n        fprintf (stderr, \"cpu_create: unable to create thread for CPU%u\\n\",\n            0);\n        free (cpu0);\n        return (-1);\n    }\n    /* 32-bit address */\n    cpu0->addr_bus_mask = 0xffffffff;\n\n    /* Initialize main RAM */\n    vm_ram_init (vm, 0x00000000ULL);\n\n    /* Initialize boot RAM area */\n    dev_ram_init (vm, \"boot\", 0x1fc00000, BOOT_RAM_KBYTES*1024);\n\n    load_hex_file (vm, m4k->boot_file_name);\n    return (0);\n}\n\n/*\n * Find pending interrupt with the biggest priority.\n * Setup INTSTAT and cause registers.\n * Update irq_pending flag for CPU.\n */\nvoid m4k_update_irq_flag (m4k_t *m4k)\n{\n    cpu_mips_t *cpu = m4k->vm->boot_cpu;\n\n    /* Assume no interrupts pending. */\n    cpu->irq_cause = 0;\n    cpu->irq_pending = 0;\n\n    //TODO\n    cpu->irq_cause = 0;\n/*printf (\"-- vector = %d, level = %d\\n\", vector, level);*/\n\n    mips_update_irq_flag (cpu);\n}\n\nvoid m4k_clear_irq (vm_instance_t *vm, u_int irq)\n{\n    m4k_t *m4k = (m4k_t*) vm->hw_data;\n\n    /* Clear interrupt flag status */\n    //TODO\n\n    m4k_update_irq_flag (m4k);\n}\n\nvoid m4k_set_irq (vm_instance_t *vm, u_int irq)\n{\n    m4k_t *m4k = (m4k_t*) vm->hw_data;\n\n    /* Set interrupt flag status */\n    //TODO\n\n    m4k_update_irq_flag (m4k);\n}\n\n/*\n * Activate core timer interrupt\n */\nvoid set_timer_irq (cpu_mips_t *cpu)\n{\n    //TODO\n}\n\n/*\n * Clear core timer interrupt\n */\nvoid clear_timer_irq (cpu_mips_t *cpu)\n{\n    //TODO\n}\n\n/*\n * Increment timers.\n */\nvoid host_alarm (cpu_mips_t *cpu, int nclocks)\n{\n    //m4k_t *m4k = (m4k_t*) cpu->vm->hw_data;\n    //TODO\n}\n\n/*\n * Create an instance of virtual machine.\n */\nvm_instance_t *create_instance (char *filename)\n{\n    vm_instance_t *vm;\n    m4k_t *m4k;\n    const char *name = \"m4k\";\n\n    m4k = malloc (sizeof (*m4k));\n    if (! m4k) {\n        fprintf (stderr, \"M4K: unable to create new instance!\\n\");\n        return NULL;\n    }\n    memset (m4k, 0, sizeof (*m4k));\n\n    vm = vm_create (name, VM_TYPE_PIC32);\n    if (! vm) {\n        fprintf (stderr, \"M4K: unable to create VM instance!\\n\");\n        free (m4k);\n        return NULL;\n    }\n    vm->hw_data = m4k;\n    m4k->vm = vm;\n\n    /* Initialize default parameters for  m4k */\n    vm->ram_size = 4*1024;          /* kilobytes */\n    vm->debug_level = 3;            /* trace all instructions */\n\n    m4k->boot_file_name = filename ? filename : \"test.hex\";\n    m4k->start_address = 0xbfc00000;\n\n    const char *output_file_name = \"m4k.trace\";\n    printf (\"Redirect output to %s\\n\", output_file_name);\n    if (freopen(output_file_name, \"w\", stdout) != stdout) {\n        fprintf (stderr, \"M4K: Unable to redirect output!\\n\");\n        exit(-1);\n    }\n\n    /* Print the configure information */\n    printf(\"ram_size: %dk bytes \\n\", vm->ram_size);\n    printf(\"start_address: 0x%x\\n\", m4k->start_address);\n\n    /* init gdb debug */\n    vm_debug_init (m4k->vm);\n\n    return m4k->vm;\n}\n\nint init_instance (vm_instance_t * vm)\n{\n    m4k_t *m4k = (m4k_t *) vm->hw_data;\n    cpu_mips_t *cpu;\n\n    if (m4k_init_platform (m4k) == -1) {\n        vm_error (vm, \"unable to initialize the platform hardware.\\n\");\n        return (-1);\n    }\n    if (! vm->boot_cpu) {\n        vm_error (vm, \"unable to boot cpu.\\n\");\n        return (-1);\n    }\n\n    /* IRQ routing */\n    vm->set_irq = m4k_set_irq;\n    vm->clear_irq = m4k_clear_irq;\n\n    vm_suspend (vm);\n\n    /* Check that CPU activity is really suspended */\n    if (cpu_group_sync_state (vm->cpu_group) == -1) {\n        vm_error (vm, \"unable to sync with system CPUs.\\n\");\n        return (-1);\n    }\n\n    /* Reset the boot CPU */\n    cpu = vm->boot_cpu;\n    mips_reset (cpu);\n\n    /* Set config0-config3 registers. */\n    cpu->cp0.config_usable = 0x0f;\n    cpu->cp0.config_reg[0] = 0xa4000582;\n    cpu->cp0.config_reg[1] = 0x80000006;\n    cpu->cp0.config_reg[2] = 0x80000000;\n    cpu->cp0.config_reg[3] = 0x00000020;\n\n    /* set PC and PRID */\n    cpu->pc = m4k->start_address;\n    cpu->cp0.tlb_entries = 0;\n    cpu->cp0.reg[MIPS_CP0_PRID]  = 0x00018700;\n    cpu->cp0.reg[MIPS_CP0_DEBUG] = 0x00010000;\n\n    /* Enable magic opcodes. */\n    cpu->magic_opcodes = 1;\n\n    /* reset all devices */\n    dev_reset_all (vm);\n\n#ifdef _USE_JIT_\n    /* if jit is used. flush all jit buffer */\n    if (vm->jit_use)\n        mips_jit_flush (cpu, 0);\n#endif\n\n    /* Launch the simulation */\n    printf (\"--- Start simulation: PC=0x%\" LL \"x, JIT %sabled\\n\",\n            cpu->pc, vm->jit_use ? \"en\" : \"dis\");\n    vm->status = VM_STATUS_RUNNING;\n    cpu_start (vm->boot_cpu);\n    return (0);\n}\n"
  },
  {
    "path": "tools/virtualmips/m4k.h",
    "content": "/*\n * Copyright (C) 2015 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#ifndef __M4K_H__\n#define __M4K_H__\n\n#include \"types.h\"\n\n#define DATA_WIDTH          32          /* MIPS32 architecture */\n#define LL                              /* empty - printf format for machine word */\n\n/*\n * Data types\n */\ntypedef m_uint32_t m_va_t;\ntypedef m_uint32_t m_pa_t;\ntypedef m_uint32_t m_reg_t;\ntypedef m_int32_t m_ireg_t;\ntypedef m_uint32_t m_cp0_reg_t;\n\n/*Guest endian*/\n#define GUEST_BYTE_ORDER  ARCH_LITTLE_ENDIAN\n\n/* Host to VM conversion functions */\n#if HOST_BYTE_ORDER == GUEST_BYTE_ORDER\n#define htovm16(x) (x)\n#define htovm32(x) (x)\n#define htovm64(x) (x)\n\n#define vmtoh16(x) (x)\n#define vmtoh32(x) (x)\n#define vmtoh64(x) (x)\n#else //host:big guest:little\n\n#define htovm16(x) (ntohs(x))\n#define htovm32(x) (ntohl(x))\n#define htovm64(x) (swap64(x))\n\n#define vmtoh16(x) (htons(x))\n#define vmtoh32(x) (htonl(x))\n#define vmtoh64(x) (swap64(x))\n#endif\n\nstruct m4k_system {\n    /* Associated VM instance */\n    vm_instance_t *vm;\n\n    unsigned start_address;         /* jump here on reset */\n    char *boot_file_name;           /* image of boot flash */\n};\n\ntypedef struct m4k_system m4k_t;\nstruct virtual_tty;\n\nvm_instance_t *create_instance (char *conf);\nint init_instance (vm_instance_t *vm);\nint m4k_reset (vm_instance_t *vm);\nvoid m4k_update_irq_flag (m4k_t *m4k);\nvoid m4k_set_irq (vm_instance_t *vm, unsigned irq);\nvoid m4k_clear_irq (vm_instance_t *vm, unsigned irq);\nvoid dumpregs (cpu_mips_t *cpu);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/main.c",
    "content": "/*\n * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#define _GNU_SOURCE\n#include <stdio.h>\n#include <string.h>\n#include <stdlib.h>\n#include <time.h>\n#include <signal.h>\n\n#include \"utils.h\"\n#include \"mips.h\"\n#include \"device.h\"\n#include \"vm.h\"\n#include \"mips_exec.h\"\n#include \"vp_timer.h\"\n#include \"crc.h\"\n#include \"net_io.h\"\n\n#define VERSION  \"0.06-retrobsd\"\n\nvoid signal_gen_handler (int sig)\n{\n    switch (sig) {\n    case SIGHUP:\n        /* For future use */\n        break;\n\n    case SIGQUIT:\n        printf (\"\\n--- Stop simulation\\n\");\n        /*do not worry, exit will release all resource */\n        exit (EXIT_SUCCESS);\n        break;\n\n    case SIGINT:\n        /* In theory, this shouldn't happen thanks to VTTY settings */\n        break;\n\n    default:\n        fprintf (stderr, \"Unhandled signal %d\\n\", sig);\n    }\n}\n\n/* Setups signals */\nstatic void setup_signals (void)\n{\n    struct sigaction act;\n\n    memset (&act, 0, sizeof (act));\n    act.sa_handler = signal_gen_handler;\n    act.sa_flags = SA_RESTART;\n    sigaction (SIGHUP, &act, NULL);\n    sigaction (SIGQUIT, &act, NULL);\n    sigaction (SIGINT, &act, NULL);\n}\n\nint main (int argc, char *argv[])\n{\n    vm_instance_t *vm;\n    char *configure_filename = NULL;\n\n    printf (\"\\nVirtualMIPS (version %s)\\n\", VERSION);\n    printf (\"Copyright (c) 2008 yajin, 2011-2015 vak.\\n\");\n    printf (\"Build date: %s %s\\n\\n\", __DATE__, __TIME__);\n\n    /* Initialize CRC functions */\n    crc_init ();\n\n    /* Initialize VTTY code */\n    vtty_init ();\n\n    /* Create the default instance */\n    if (argc > 1)\n        configure_filename = argv[1];\n    vm = create_instance (configure_filename);\n    if (!vm)\n        return EXIT_FAILURE;\n\n    /* Set seed for random value. */\n    srand ((int) time (0));\n\n    setup_signals ();\n    init_timers ();\n    if (init_instance (vm) < 0) {\n        fprintf (stderr, \"Unable to initialize instance.\\n\");\n        return EXIT_FAILURE;\n    }\n\n    /* We get here, because the cpu is not running now. */\n    vm_monitor (vm);\n\n    printf (\"VM shut down\\n\");\n    return (0);\n}\n"
  },
  {
    "path": "tools/virtualmips/mempool.c",
    "content": "/*\n * Copyright (c) 1999-2006 Christophe Fillot.\n * E-mail: cf@utc.fr\n *\n * mempool.c: Simple Memory Pools.\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdarg.h>\n#include <unistd.h>\n#include <errno.h>\n#include <signal.h>\n#include <fcntl.h>\n#include <ctype.h>\n#include <time.h>\n#include <sys/time.h>\n#include <sys/stat.h>\n#include <sys/types.h>\n#include <assert.h>\n\n#include \"utils.h\"\n#include \"mempool.h\"\n\n/* \n * Internal function used to allocate a memory block, and do basic operations\n * on it. It does not manipulate pools, so no mutex is needed.\n */\nstatic inline memblock_t *memblock_alloc (size_t size, int zeroed)\n{\n    memblock_t *block;\n    size_t total_size;\n\n    total_size = size + sizeof (memblock_t);\n    if (!(block = malloc (total_size)))\n        return NULL;\n\n    if (zeroed)\n        memset (block, 0, total_size);\n\n    block->tag = MEMBLOCK_TAG;\n    block->block_size = size;\n    block->prev = block->next = NULL;\n    return block;\n}\n\n/* Insert block in linked list */\nstatic inline void memblock_insert (mempool_t * pool, memblock_t * block)\n{\n    MEMPOOL_LOCK (pool);\n\n    pool->nr_blocks++;\n    pool->total_size += block->block_size;\n\n    block->prev = NULL;\n    block->next = pool->block_list;\n\n    if (block->next)\n        block->next->prev = block;\n\n    pool->block_list = block;\n\n    MEMPOOL_UNLOCK (pool);\n}\n\n/* Remove block from linked list */\nstatic inline void memblock_delete (mempool_t * pool, memblock_t * block)\n{\n    MEMPOOL_LOCK (pool);\n\n    pool->nr_blocks--;\n    pool->total_size -= block->block_size;\n\n    if (!block->prev)\n        pool->block_list = block->next;\n    else\n        block->prev->next = block->next;\n\n    if (block->next)\n        block->next->prev = block->prev;\n\n    block->next = block->prev = NULL;\n    MEMPOOL_UNLOCK (pool);\n}\n\n/* Allocate a new block in specified pool (internal function) */\nstatic inline void *mp_alloc_inline (mempool_t * pool, size_t size,\n    int zeroed)\n{\n    memblock_t *block;\n\n    if (!(block = memblock_alloc (size, zeroed)))\n        return NULL;\n\n    block->pool = pool;\n    memblock_insert (pool, block);\n    return (block->data);\n}\n\n/* Allocate a new block in specified pool */\nvoid *mp_alloc (mempool_t * pool, size_t size)\n{\n    return (mp_alloc_inline (pool, size, TRUE));\n}\n\n/* Allocate a new block which will not be zeroed */\nvoid *mp_alloc_n0 (mempool_t * pool, size_t size)\n{\n    return (mp_alloc_inline (pool, size, FALSE));\n}\n\n/* Reallocate a block */\nvoid *mp_realloc (void *addr, size_t new_size)\n{\n    memblock_t *ptr, *block = (memblock_t *) addr - 1;\n    mempool_t *pool;\n    size_t total_size;\n\n    assert (block->tag == MEMBLOCK_TAG);\n    pool = block->pool;\n\n    /* remove this block from list */\n    memblock_delete (pool, block);\n\n    /* reallocate block with specified size */\n    total_size = new_size + sizeof (memblock_t);\n\n    if (!(ptr = realloc (block, total_size))) {\n        memblock_insert (pool, block);\n        return NULL;\n    }\n\n    ptr->block_size = new_size;\n    memblock_insert (pool, ptr);\n    return ptr->data;\n}\n\n/* Allocate a new memory block and copy data into it */\nvoid *mp_dup (mempool_t * pool, void *data, size_t size)\n{\n    void *p;\n\n    if ((p = mp_alloc_n0 (pool, size)))\n        memcpy (p, data, size);\n\n    return p;\n}\n\n/* Duplicate specified string and insert it in a memory pool */\nchar *mp_strdup (mempool_t * pool, char *str)\n{\n    char *new_str;\n\n    if ((new_str = mp_alloc (pool, strlen (str) + 1)) == NULL)\n        return NULL;\n\n    strlcpy (new_str, str, sizeof(new_str));\n    return new_str;\n}\n\n/* Free block at specified address */\nint mp_free (void *addr)\n{\n    memblock_t *block = (memblock_t *) addr - 1;\n    mempool_t *pool;\n\n    if (addr != NULL) {\n        assert (block->tag == MEMBLOCK_TAG);\n        pool = block->pool;\n\n        memblock_delete (pool, block);\n        memset (block, 0, sizeof (memblock_t));\n        free (block);\n    }\n\n    return (0);\n}\n\n/* Free block at specified address and clean pointer */\nint mp_free_ptr (void *addr)\n{\n    void *p;\n\n    assert (addr != NULL);\n    p = *(void **) addr;\n    *(void **) addr = NULL;\n    mp_free (p);\n    return (0);\n}\n\n/* Free all blocks of specified pool */\nvoid mp_free_all_blocks (mempool_t * pool)\n{\n    memblock_t *block, *next;\n\n    MEMPOOL_LOCK (pool);\n\n    for (block = pool->block_list; block; block = next) {\n        next = block->next;\n        free (block);\n    }\n\n    pool->block_list = NULL;\n    pool->nr_blocks = 0;\n    pool->total_size = 0;\n\n    MEMPOOL_UNLOCK (pool);\n}\n\n/* Free specified memory pool */\nvoid mp_free_pool (mempool_t * pool)\n{\n    mp_free_all_blocks (pool);\n\n    if (!(pool->flags & MEMPOOL_FIXED))\n        free (pool);\n}\n\n/* Create a new pool in a fixed memory area */\nmempool_t *mp_create_fixed_pool (mempool_t * mp, char *name)\n{\n    memset (mp, 0, sizeof (*mp));\n\n    if (pthread_mutex_init (&mp->lock, NULL) != 0)\n        return NULL;\n\n    mp->name = name;\n    mp->block_list = NULL;\n    mp->flags = MEMPOOL_FIXED;\n    return mp;\n}\n\n/* Create a new pool */\nmempool_t *mp_create_pool (char *name)\n{\n    mempool_t *mp = malloc (sizeof (*mp));\n\n    if (!mp || !mp_create_fixed_pool (mp, name)) {\n        free (mp);\n        return NULL;\n    }\n\n    mp->flags = 0;              /* clear \"FIXED\" flag */\n    return mp;\n}\n"
  },
  {
    "path": "tools/virtualmips/mempool.h",
    "content": "/*\n * Copyright (c) 1999-2006 Christophe Fillot.\n * E-mail: cf@utc.fr\n *\n * mempool.h: Simple Memory Pools.\n */\n\n#ifndef __MEMPOOL_H__\n#define __MEMPOOL_H__  1\n\n#include <sys/types.h>\n#include <sys/time.h>\n#include <pthread.h>\n\n#include \"utils.h\"\n\n/* Memory Pool \"Fixed\" Flag */\n#define MEMPOOL_FIXED  1\n\n/* Dummy value used to check if a memory block is invalid */\n#define MEMBLOCK_TAG  0xdeadbeef\n\ntypedef struct memblock memblock_t;\ntypedef struct mempool mempool_t;\n\n/* Memory block */\nstruct memblock {\n    int tag;                    /* MEMBLOCK_TAG if block is valid */\n    size_t block_size;          /* Block size (without header) */\n    memblock_t *next, *prev;    /* Double linked list pointers */\n    mempool_t *pool;            /* Pool which contains this block */\n    m_uint64_t data[0];         /* Memory block itself */\n};\n\n/* Memory Pool */\nstruct mempool {\n    memblock_t *block_list;     /* Double-linked block list */\n    pthread_mutex_t lock;       /* Mutex for managing pool */\n    char *name;                 /* Name of this pool */\n    int flags;                  /* Flags */\n    int nr_blocks;              /* Number of blocks in this pool */\n    size_t total_size;          /* Total bytes allocated */\n    size_t max_size;            /* Maximum memory */\n};\n\n/* Lock and unlock access to a memory pool */\n#define MEMPOOL_LOCK(mp)    pthread_mutex_lock(&(mp)->lock)\n#define MEMPOOL_UNLOCK(mp)  pthread_mutex_unlock(&(mp)->lock)\n\n/* Callback function for use with mp_foreach */\ntypedef void (*mp_foreach_cbk) (memblock_t * block, void *user_arg);\n\n/* Execute an action for each block in specified pool */\nstatic inline void mp_foreach (mempool_t * pool, mp_foreach_cbk cbk,\n    void *arg)\n{\n    memblock_t *mb;\n\n    for (mb = pool->block_list; mb; mb = mb->next)\n        cbk (mb, arg);\n}\n\n/* Allocate a new block in specified pool */\nvoid *mp_alloc (mempool_t * pool, size_t size);\n\n/* Allocate a new block which will not be zeroed */\nvoid *mp_alloc_n0 (mempool_t * pool, size_t size);\n\n/* Reallocate a block */\nvoid *mp_realloc (void *addr, size_t new_size);\n\n/* Allocate a new memory block and copy data into it */\nvoid *mp_dup (mempool_t * pool, void *data, size_t size);\n\n/* Duplicate specified string and insert it in a memory pool */\nchar *mp_strdup (mempool_t * pool, char *str);\n\n/* Free block at specified address */\nint mp_free (void *addr);\n\n/* Free block at specified address and clean pointer */\nint mp_free_ptr (void *addr);\n\n/* Free all blocks of specified pool */\nvoid mp_free_all_blocks (mempool_t * pool);\n\n/* Free specified memory pool */\nvoid mp_free_pool (mempool_t * pool);\n\n/* Create a new pool in a fixed memory area */\nmempool_t *mp_create_fixed_pool (mempool_t * mp, char *name);\n\n/* Create a new pool */\nmempool_t *mp_create_pool (char *name);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/mips-dis.c",
    "content": "/*\n * Print mips instructions.\n *\n * Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,\n * 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009\n * Free Software Foundation, Inc.\n * Contributed by Nobuyuki Hikichi (hikichi@sra.co.jp).\n * Rewritten for VirtualMIPS by Serge Vakulenko.\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#include <stdlib.h>\n#include <stdio.h>\n#include <string.h>\n#include \"mips-opcode.h\"\n#include \"mips-opc.c\"\n#include \"mips16-opc.c\"\n\n/* FIXME: These are needed to figure out if the code is mips16 or\n   not. The low bit of the address is often a good indicator.  No\n   symbol table is available when this code runs out in an embedded\n   system as when it is used for disassembler support in a monitor.  */\n\n/* Mips instructions are at maximum this many bytes long.  */\n#define INSNLEN 4\n\nstruct mips_cp0sel_name {\n    unsigned int cp0reg;\n    unsigned int sel;\n    const char *const name;\n};\n\n/* The mips16 registers.  */\nstatic const unsigned int mips16_to_32_reg_map[] = {\n    16, 17, 2, 3, 4, 5, 6, 7\n};\n\n#define mips16_reg_names(rn)\tmips_gpr_names[mips16_to_32_reg_map[rn]]\n\nstatic const char *const mips_gpr_names[32] = {\n    \"zero\", \"at\", \"v0\", \"v1\", \"a0\", \"a1\", \"a2\", \"a3\",\n    \"t0\", \"t1\", \"t2\", \"t3\", \"t4\", \"t5\", \"t6\", \"t7\",\n    \"s0\", \"s1\", \"s2\", \"s3\", \"s4\", \"s5\", \"s6\", \"s7\",\n    \"t8\", \"t9\", \"k0\", \"k1\", \"gp\", \"sp\", \"s8\", \"ra\"\n};\n\nstatic const char *const mips_fpr_names[32] = {\n    \"$f0\", \"$f1\", \"$f2\", \"$f3\", \"$f4\", \"$f5\", \"$f6\", \"$f7\",\n    \"$f8\", \"$f9\", \"$f10\", \"$f11\", \"$f12\", \"$f13\", \"$f14\", \"$f15\",\n    \"$f16\", \"$f17\", \"$f18\", \"$f19\", \"$f20\", \"$f21\", \"$f22\", \"$f23\",\n    \"$f24\", \"$f25\", \"$f26\", \"$f27\", \"$f28\", \"$f29\", \"$f30\", \"$f31\"\n};\n\nstatic const char *const mips_cp0_names[32] = {\n    \"c0_index\", \"c0_random\", \"c0_entrylo0\", \"c0_entrylo1\",\n    \"c0_context\", \"c0_pagemask\", \"c0_wired\", \"c0_hwrena\",\n    \"c0_badvaddr\", \"c0_count\", \"c0_entryhi\", \"c0_compare\",\n    \"c0_status\", \"c0_cause\", \"c0_epc\", \"c0_prid\",\n    \"c0_config\", \"c0_lladdr\", \"c0_watchlo\", \"c0_watchhi\",\n    \"c0_xcontext\", \"$21\", \"$22\", \"c0_debug\",\n    \"c0_depc\", \"c0_perfcnt\", \"c0_errctl\", \"c0_cacheerr\",\n    \"c0_taglo\", \"c0_taghi\", \"c0_errorepc\", \"c0_desave\",\n};\n\nstatic const struct mips_cp0sel_name mips_cp0sel_names[] = {\n    {4, 1, \"c0_contextconfig\"},\n    {0, 1, \"c0_mvpcontrol\"},\n    {0, 2, \"c0_mvpconf0\"},\n    {0, 3, \"c0_mvpconf1\"},\n    {1, 1, \"c0_vpecontrol\"},\n    {1, 2, \"c0_vpeconf0\"},\n    {1, 3, \"c0_vpeconf1\"},\n    {1, 4, \"c0_yqmask\"},\n    {1, 5, \"c0_vpeschedule\"},\n    {1, 6, \"c0_vpeschefback\"},\n    {2, 1, \"c0_tcstatus\"},\n    {2, 2, \"c0_tcbind\"},\n    {2, 3, \"c0_tcrestart\"},\n    {2, 4, \"c0_tchalt\"},\n    {2, 5, \"c0_tccontext\"},\n    {2, 6, \"c0_tcschedule\"},\n    {2, 7, \"c0_tcschefback\"},\n    {5, 1, \"c0_pagegrain\"},\n    {6, 1, \"c0_srsconf0\"},\n    {6, 2, \"c0_srsconf1\"},\n    {6, 3, \"c0_srsconf2\"},\n    {6, 4, \"c0_srsconf3\"},\n    {6, 5, \"c0_srsconf4\"},\n    {12, 1, \"c0_intctl\"},\n    {12, 2, \"c0_srsctl\"},\n    {12, 3, \"c0_srsmap\"},\n    {15, 1, \"c0_ebase\"},\n    {16, 1, \"c0_config1\"},\n    {16, 2, \"c0_config2\"},\n    {16, 3, \"c0_config3\"},\n    {18, 1, \"c0_watchlo,1\"},\n    {18, 2, \"c0_watchlo,2\"},\n    {18, 3, \"c0_watchlo,3\"},\n    {18, 4, \"c0_watchlo,4\"},\n    {18, 5, \"c0_watchlo,5\"},\n    {18, 6, \"c0_watchlo,6\"},\n    {18, 7, \"c0_watchlo,7\"},\n    {19, 1, \"c0_watchhi,1\"},\n    {19, 2, \"c0_watchhi,2\"},\n    {19, 3, \"c0_watchhi,3\"},\n    {19, 4, \"c0_watchhi,4\"},\n    {19, 5, \"c0_watchhi,5\"},\n    {19, 6, \"c0_watchhi,6\"},\n    {19, 7, \"c0_watchhi,7\"},\n    {23, 1, \"c0_tracecontrol\"},\n    {23, 2, \"c0_tracecontrol2\"},\n    {23, 3, \"c0_usertracedata\"},\n    {23, 4, \"c0_tracebpc\"},\n    {25, 1, \"c0_perfcnt,1\"},\n    {25, 2, \"c0_perfcnt,2\"},\n    {25, 3, \"c0_perfcnt,3\"},\n    {25, 4, \"c0_perfcnt,4\"},\n    {25, 5, \"c0_perfcnt,5\"},\n    {25, 6, \"c0_perfcnt,6\"},\n    {25, 7, \"c0_perfcnt,7\"},\n    {27, 1, \"c0_cacheerr,1\"},\n    {27, 2, \"c0_cacheerr,2\"},\n    {27, 3, \"c0_cacheerr,3\"},\n    {28, 1, \"c0_datalo\"},\n    {28, 2, \"c0_taglo1\"},\n    {28, 3, \"c0_datalo1\"},\n    {28, 4, \"c0_taglo2\"},\n    {28, 5, \"c0_datalo2\"},\n    {28, 6, \"c0_taglo3\"},\n    {28, 7, \"c0_datalo3\"},\n    {29, 1, \"c0_datahi\"},\n    {29, 2, \"c0_taghi1\"},\n    {29, 3, \"c0_datahi1\"},\n    {29, 4, \"c0_taghi2\"},\n    {29, 5, \"c0_datahi2\"},\n    {29, 6, \"c0_taghi3\"},\n    {29, 7, \"c0_datahi3\"},\n};\nstatic const int mips_cp0sel_names_len = sizeof (mips_cp0sel_names) / sizeof (*mips_cp0sel_names);\n\nstatic const char *const mips_hwr_names[32] = {\n    \"$0\", \"$1\", \"$2\", \"$3\", \"$4\", \"$5\", \"$6\", \"$7\",\n    \"$8\", \"$9\", \"$10\", \"$11\", \"$12\", \"$13\", \"$14\", \"$15\",\n    \"$16\", \"$17\", \"$18\", \"$19\", \"$20\", \"$21\", \"$22\", \"$23\",\n    \"$24\", \"$25\", \"$26\", \"$27\", \"$28\", \"$29\", \"$30\", \"$31\"\n};\n\n/*\n * If set disassemble as most general inst.\n */\nstatic int no_aliases = 0;\n\nstatic unsigned target;\n\nstatic void\nprint_address (unsigned address, FILE *stream)\n{\n    if (address < 16)\n        fprintf (stream, \"%d\", address);\n    else\n        fprintf (stream, \"0x%x\", address);\n}\n\nstatic const struct mips_cp0sel_name *\nlookup_mips_cp0sel_name (const struct\n    mips_cp0sel_name *names, unsigned int len, unsigned int cp0reg,\n    unsigned int sel)\n{\n    unsigned int i;\n\n    for (i = 0; i < len; i++)\n        if (names[i].cp0reg == cp0reg && names[i].sel == sel)\n            return &names[i];\n    return NULL;\n}\n\n/*\n * CP0 register including 'sel' code for mftc0, to be\n * printed textually if known.  If not known, print both\n * CP0 register name and sel numerically since CP0 register\n * with sel 0 may have a name unrelated to register being\n * printed.\n */\nconst char *cp0reg_name (unsigned cp0reg, unsigned sel)\n{\n    const struct mips_cp0sel_name *n;\n    static char name [32];\n\n    if (sel == 0)\n        return mips_cp0_names[cp0reg];\n\n    n = lookup_mips_cp0sel_name (mips_cp0sel_names,\n        mips_cp0sel_names_len, cp0reg, sel);\n    if (n != NULL)\n        return n->name;\n\n    snprintf (name, sizeof(name), \"CP0_R[%d,%d]\", cp0reg, sel);\n    return name;\n}\n\n/* Print insn arguments for 32/64-bit code.  */\n\nstatic void\nprint_insn_args (const char *d,\n    register unsigned long int l,\n    unsigned pc, FILE *stream, const struct mips_opcode *opp)\n{\n    int op, delta;\n    unsigned int lsb, msb, msbd;\n\n    lsb = 0;\n\n    for (; *d != '\\0'; d++) {\n        switch (*d) {\n        case ',':\n        case '(':\n        case ')':\n        case '[':\n        case ']':\n            fprintf (stream, \"%c\", *d);\n            break;\n\n        case '+':\n            /* Extension character; switch for second char.  */\n            d++;\n            switch (*d) {\n            case '\\0':\n                /* xgettext:c-format */\n                fprintf (stream,\n                    \"# internal error, incomplete extension sequence (+)\");\n                return;\n\n            case 'A':\n                lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;\n                fprintf (stream, \"0x%x\", lsb);\n                break;\n\n            case 'B':\n                msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;\n                fprintf (stream, \"0x%x\", msb - lsb + 1);\n                break;\n\n            case '1':\n                fprintf (stream, \"0x%lx\",\n                    (l >> OP_SH_UDI1) & OP_MASK_UDI1);\n                break;\n\n            case '2':\n                fprintf (stream, \"0x%lx\",\n                    (l >> OP_SH_UDI2) & OP_MASK_UDI2);\n                break;\n\n            case '3':\n                fprintf (stream, \"0x%lx\",\n                    (l >> OP_SH_UDI3) & OP_MASK_UDI3);\n                break;\n\n            case '4':\n                fprintf (stream, \"0x%lx\",\n                    (l >> OP_SH_UDI4) & OP_MASK_UDI4);\n                break;\n\n            case 'C':\n            case 'H':\n                msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;\n                fprintf (stream, \"0x%x\", msbd + 1);\n                break;\n\n            case 'D':\n                {\n                    const struct mips_cp0sel_name *n;\n                    unsigned int cp0reg, sel;\n\n                    cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;\n                    sel = (l >> OP_SH_SEL) & OP_MASK_SEL;\n\n                    /* CP0 register including 'sel' code for mtcN (et al.), to be\n                     * printed textually if known.  If not known, print both\n                     * CP0 register name and sel numerically since CP0 register\n                     * with sel 0 may have a name unrelated to register being\n                     * printed.  */\n                    n = lookup_mips_cp0sel_name (mips_cp0sel_names,\n                        mips_cp0sel_names_len, cp0reg, sel);\n                    if (n != NULL)\n                        fprintf (stream, \"%s\", n->name);\n                    else\n                        fprintf (stream, \"$%d,%d\", cp0reg,\n                            sel);\n                    break;\n                }\n\n            case 'E':\n                lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;\n                fprintf (stream, \"0x%x\", lsb);\n                break;\n\n            case 'F':\n                msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;\n                fprintf (stream, \"0x%x\", msb - lsb + 1);\n                break;\n\n            case 'G':\n                msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;\n                fprintf (stream, \"0x%x\", msbd + 1);\n                break;\n\n            case 't':          /* Coprocessor 0 reg name */\n                fprintf (stream, \"%s\",\n                    mips_cp0_names[(l >> OP_SH_RT) & OP_MASK_RT]);\n                break;\n\n            case 'T':          /* Coprocessor 0 reg name */\n                {\n                    const struct mips_cp0sel_name *n;\n                    unsigned int cp0reg, sel;\n\n                    cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;\n                    sel = (l >> OP_SH_SEL) & OP_MASK_SEL;\n\n                    /* CP0 register including 'sel' code for mftc0, to be\n                     * printed textually if known.  If not known, print both\n                     * CP0 register name and sel numerically since CP0 register\n                     * with sel 0 may have a name unrelated to register being\n                     * printed.  */\n                    n = lookup_mips_cp0sel_name (mips_cp0sel_names,\n                        mips_cp0sel_names_len, cp0reg, sel);\n                    if (n != NULL)\n                        fprintf (stream, \"%s\", n->name);\n                    else\n                        fprintf (stream, \"$%d,%d\", cp0reg,\n                            sel);\n                    break;\n                }\n\n            case 'x':          /* bbit bit index */\n                fprintf (stream, \"0x%lx\",\n                    (l >> OP_SH_BBITIND) & OP_MASK_BBITIND);\n                break;\n\n            case 'p':          /* cins, cins32, exts and exts32 position */\n                fprintf (stream, \"0x%lx\",\n                    (l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS);\n                break;\n\n            case 's':          /* cins and exts length-minus-one */\n                fprintf (stream, \"0x%lx\",\n                    (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);\n                break;\n\n            case 'S':          /* cins32 and exts32 length-minus-one field */\n                fprintf (stream, \"0x%lx\",\n                    (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1);\n                break;\n\n            case 'Q':          /* seqi/snei immediate field */\n                op = (l >> OP_SH_SEQI) & OP_MASK_SEQI;\n                /* Sign-extend it.  */\n                op = (op ^ 512) - 512;\n                fprintf (stream, \"%d\", op);\n                break;\n\n            default:\n                /* xgettext:c-format */\n                fprintf (stream, \"# internal error, undefined extension sequence (+%c)\", *d);\n                return;\n            }\n            break;\n\n        case '2':\n            fprintf (stream, \"0x%lx\",\n                (l >> OP_SH_BP) & OP_MASK_BP);\n            break;\n\n        case '3':\n            fprintf (stream, \"0x%lx\",\n                (l >> OP_SH_SA3) & OP_MASK_SA3);\n            break;\n\n        case '4':\n            fprintf (stream, \"0x%lx\",\n                (l >> OP_SH_SA4) & OP_MASK_SA4);\n            break;\n\n        case '5':\n            fprintf (stream, \"0x%lx\",\n                (l >> OP_SH_IMM8) & OP_MASK_IMM8);\n            break;\n\n        case '6':\n            fprintf (stream, \"0x%lx\",\n                (l >> OP_SH_RS) & OP_MASK_RS);\n            break;\n\n        case '7':\n            fprintf (stream, \"$ac%ld\",\n                (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);\n            break;\n\n        case '8':\n            fprintf (stream, \"0x%lx\",\n                (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);\n            break;\n\n        case '9':\n            fprintf (stream, \"$ac%ld\",\n                (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);\n            break;\n\n        case '0':              /* dsp 6-bit signed immediate in bit 20 */\n            delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);\n            if (delta & 0x20)   /* test sign bit */\n                delta |= ~OP_MASK_DSPSFT;\n            fprintf (stream, \"%d\", delta);\n            break;\n\n        case ':':              /* dsp 7-bit signed immediate in bit 19 */\n            delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);\n            if (delta & 0x40)   /* test sign bit */\n                delta |= ~OP_MASK_DSPSFT_7;\n            fprintf (stream, \"%d\", delta);\n            break;\n\n        case '\\'':\n            fprintf (stream, \"0x%lx\",\n                (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);\n            break;\n\n        case '@':              /* dsp 10-bit signed immediate in bit 16 */\n            delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);\n            if (delta & 0x200)  /* test sign bit */\n                delta |= ~OP_MASK_IMM10;\n            fprintf (stream, \"%d\", delta);\n            break;\n\n        case '!':\n            fprintf (stream, \"%ld\",\n                (l >> OP_SH_MT_U) & OP_MASK_MT_U);\n            break;\n\n        case '$':\n            fprintf (stream, \"%ld\",\n                (l >> OP_SH_MT_H) & OP_MASK_MT_H);\n            break;\n\n        case '*':\n            fprintf (stream, \"$ac%ld\",\n                (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);\n            break;\n\n        case '&':\n            fprintf (stream, \"$ac%ld\",\n                (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);\n            break;\n\n        case 'g':\n            /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2.  */\n            fprintf (stream, \"$%ld\",\n                (l >> OP_SH_RD) & OP_MASK_RD);\n            break;\n\n        case 's':\n        case 'b':\n        case 'r':\n        case 'v':\n            fprintf (stream, \"%s\",\n                mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);\n            break;\n\n        case 't':\n        case 'w':\n            fprintf (stream, \"%s\",\n                mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);\n            break;\n\n        case 'i':\n        case 'u':\n            fprintf (stream, \"0x%lx\",\n                (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);\n            break;\n\n        case 'j':              /* Same as i, but sign-extended.  */\n        case 'o':\n            delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;\n            if (delta & 0x8000)\n                delta |= ~0xffff;\n            fprintf (stream, \"%d\", delta);\n            break;\n\n        case 'h':\n            fprintf (stream, \"0x%x\",\n                (unsigned int) ((l >> OP_SH_PREFX)\n                    & OP_MASK_PREFX));\n            break;\n\n        case 'k':\n            fprintf (stream, \"0x%x\",\n                (unsigned int) ((l >> OP_SH_CACHE)\n                    & OP_MASK_CACHE));\n            break;\n\n        case 'a':\n            target = (((pc + 4) & ~(unsigned) 0x0fffffff)\n                | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));\n            /* For gdb disassembler, force odd address on jalx.  */\n            if (strcmp (opp->name, \"jalx\") == 0)\n                target |= 1;\n            print_address (target, stream);\n            break;\n\n        case 'p':\n            /* Sign extend the displacement.  */\n            delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;\n            if (delta & 0x8000)\n                delta |= ~0xffff;\n            target = (delta << 2) + pc + INSNLEN;\n            print_address (target, stream);\n            break;\n\n        case 'd':\n            fprintf (stream, \"%s\",\n                mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);\n            break;\n\n        case 'U':\n            {\n                /* First check for both rd and rt being equal.  */\n                unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;\n                if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))\n                    fprintf (stream, \"%s\",\n                        mips_gpr_names[reg]);\n                else {\n                    /* If one is zero use the other.  */\n                    if (reg == 0)\n                        fprintf (stream, \"%s\",\n                            mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);\n                    else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)\n                        fprintf (stream, \"%s\",\n                            mips_gpr_names[reg]);\n                    else        /* Bogus, result depends on processor.  */\n                        fprintf (stream, \"%s or %s\",\n                            mips_gpr_names[reg],\n                            mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);\n                }\n            }\n            break;\n\n        case 'z':\n            fprintf (stream, \"%s\", mips_gpr_names[0]);\n            break;\n\n        case '<':\n        case '1':\n            fprintf (stream, \"0x%lx\",\n                (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);\n            break;\n\n        case 'c':\n            fprintf (stream, \"0x%lx\",\n                (l >> OP_SH_CODE) & OP_MASK_CODE);\n            break;\n\n        case 'q':\n            fprintf (stream, \"0x%lx\",\n                (l >> OP_SH_CODE2) & OP_MASK_CODE2);\n            break;\n\n        case 'C':\n            fprintf (stream, \"0x%lx\",\n                (l >> OP_SH_COPZ) & OP_MASK_COPZ);\n            break;\n\n        case 'B':\n            fprintf (stream, \"0x%lx\",\n                (l >> OP_SH_CODE20) & OP_MASK_CODE20);\n            break;\n\n        case 'J':\n            fprintf (stream, \"0x%lx\",\n                (l >> OP_SH_CODE19) & OP_MASK_CODE19);\n            break;\n\n        case 'S':\n        case 'V':\n            fprintf (stream, \"%s\",\n                mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);\n            break;\n\n        case 'T':\n        case 'W':\n            fprintf (stream, \"%s\",\n                mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);\n            break;\n\n        case 'D':\n            fprintf (stream, \"%s\",\n                mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);\n            break;\n\n        case 'R':\n            fprintf (stream, \"%s\",\n                mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);\n            break;\n\n        case 'E':\n            /* Coprocessor register for lwcN instructions, et al.\n             *\n             * Note that there is no load/store cp0 instructions, and\n             * that FPU (cp1) instructions disassemble this field using\n             * 'T' format.  Therefore, until we gain understanding of\n             * cp2 register names, we can simply print the register\n             * numbers.  */\n            fprintf (stream, \"$%ld\",\n                (l >> OP_SH_RT) & OP_MASK_RT);\n            break;\n\n        case 'G':\n            /* Coprocessor register for mtcN instructions, et al.  Note\n             * that FPU (cp1) instructions disassemble this field using\n             * 'S' format.  Therefore, we only need to worry about cp0,\n             * cp2, and cp3.  */\n            op = (l >> OP_SH_OP) & OP_MASK_OP;\n            if (op == OP_OP_COP0)\n                fprintf (stream, \"%s\",\n                    mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);\n            else\n                fprintf (stream, \"$%ld\",\n                    (l >> OP_SH_RD) & OP_MASK_RD);\n            break;\n\n        case 'K':\n            fprintf (stream, \"%s\",\n                mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);\n            break;\n\n        case 'N':\n            fprintf (stream,\n                ((opp->pinfo & (FP_D | FP_S)) != 0\n                    ? \"$fcc%ld\" : \"$cc%ld\"), (l >> OP_SH_BCC) & OP_MASK_BCC);\n            break;\n\n        case 'M':\n            fprintf (stream, \"$fcc%ld\",\n                (l >> OP_SH_CCC) & OP_MASK_CCC);\n            break;\n\n        case 'P':\n            fprintf (stream, \"%ld\",\n                (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);\n            break;\n\n        case 'e':\n            fprintf (stream, \"%ld\",\n                (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);\n            break;\n\n        case '%':\n            fprintf (stream, \"%ld\",\n                (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);\n            break;\n\n        case 'H':\n            fprintf (stream, \"%ld\",\n                (l >> OP_SH_SEL) & OP_MASK_SEL);\n            break;\n\n        case 'O':\n            fprintf (stream, \"%ld\",\n                (l >> OP_SH_ALN) & OP_MASK_ALN);\n            break;\n\n        case 'Q':\n            {\n                unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;\n\n                if ((vsel & 0x10) == 0) {\n                    int fmt;\n\n                    vsel &= 0x0f;\n                    for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)\n                        if ((vsel & 1) == 0)\n                            break;\n                    fprintf (stream, \"$v%ld[%d]\",\n                        (l >> OP_SH_FT) & OP_MASK_FT, vsel >> 1);\n                } else if ((vsel & 0x08) == 0) {\n                    fprintf (stream, \"$v%ld\",\n                        (l >> OP_SH_FT) & OP_MASK_FT);\n                } else {\n                    fprintf (stream, \"0x%lx\",\n                        (l >> OP_SH_FT) & OP_MASK_FT);\n                }\n            }\n            break;\n\n        case 'X':\n            fprintf (stream, \"$v%ld\",\n                (l >> OP_SH_FD) & OP_MASK_FD);\n            break;\n\n        case 'Y':\n            fprintf (stream, \"$v%ld\",\n                (l >> OP_SH_FS) & OP_MASK_FS);\n            break;\n\n        case 'Z':\n            fprintf (stream, \"$v%ld\",\n                (l >> OP_SH_FT) & OP_MASK_FT);\n            break;\n\n        default:\n            /* xgettext:c-format */\n            fprintf (stream, \"# internal error, undefined modifier (%c)\\n\", *d);\n            return;\n        }\n    }\n}\n\n/*\n * Print the mips instruction at address MEMADDR.\n */\nstatic void\nprint_insn_mips (unsigned memaddr,\n    unsigned long int word, FILE *stream)\n{\n    const struct mips_opcode *op;\n    static int init = 0;\n    static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];\n\n    /* Build a hash table to shorten the search time.  */\n    if (! init) {\n        unsigned int i;\n\n        for (i = 0; i <= OP_MASK_OP; i++) {\n            for (op = mips_opcodes; op < &mips_opcodes[mips_num_opcodes]; op++) {\n                if (op->pinfo == INSN_MACRO\n                    || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))\n                    continue;\n                if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) {\n                    mips_hash[i] = op;\n                    break;\n                }\n            }\n        }\n\n        init = 1;\n    }\n\n    target = 0;\n\n    op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];\n    if (op != NULL) {\n        for (; op < &mips_opcodes[mips_num_opcodes]; op++) {\n            if (op->pinfo != INSN_MACRO\n                && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))\n                && (word & op->mask) == op->match) {\n                const char *d;\n\n                fprintf (stream, \"%s\", op->name);\n\n                d = op->args;\n                if (d != NULL && *d != '\\0') {\n                    fprintf (stream, \"\\t\");\n                    print_insn_args (d, word, memaddr, stream, op);\n                }\n                return;\n            }\n        }\n    }\n\n    /* Handle undefined instructions.  */\n    fprintf (stream, \"0x%lx\", word);\n}\n\n/*\n * Disassemble an operand for a mips16 instruction.\n */\nstatic void\nprint_mips16_insn_arg (char type,\n    const struct mips_opcode *op,\n    int l,\n    int use_extend,\n    int extend, unsigned memaddr, FILE *stream)\n{\n    switch (type) {\n    case ',':\n    case '(':\n    case ')':\n        fprintf (stream, \"%c\", type);\n        break;\n\n    case 'y':\n    case 'w':\n        fprintf (stream, \"%s\",\n            mips16_reg_names (((l >> MIPS16OP_SH_RY)\n                    & MIPS16OP_MASK_RY)));\n        break;\n\n    case 'x':\n    case 'v':\n        fprintf (stream, \"%s\",\n            mips16_reg_names (((l >> MIPS16OP_SH_RX)\n                    & MIPS16OP_MASK_RX)));\n        break;\n\n    case 'z':\n        fprintf (stream, \"%s\",\n            mips16_reg_names (((l >> MIPS16OP_SH_RZ)\n                    & MIPS16OP_MASK_RZ)));\n        break;\n\n    case 'Z':\n        fprintf (stream, \"%s\",\n            mips16_reg_names (((l >> MIPS16OP_SH_MOVE32Z)\n                    & MIPS16OP_MASK_MOVE32Z)));\n        break;\n\n    case '0':\n        fprintf (stream, \"%s\", mips_gpr_names[0]);\n        break;\n\n    case 'S':\n        fprintf (stream, \"%s\", mips_gpr_names[29]);\n        break;\n\n    case 'P':\n        fprintf (stream, \"$pc\");\n        break;\n\n    case 'R':\n        fprintf (stream, \"%s\", mips_gpr_names[31]);\n        break;\n\n    case 'X':\n        fprintf (stream, \"%s\",\n            mips_gpr_names[((l >> MIPS16OP_SH_REGR32)\n                    & MIPS16OP_MASK_REGR32)]);\n        break;\n\n    case 'Y':\n        fprintf (stream, \"%s\",\n            mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);\n        break;\n\n    case '<':\n    case '>':\n    case '[':\n    case ']':\n    case '4':\n    case '5':\n    case 'H':\n    case 'W':\n    case 'D':\n    case 'j':\n    case '6':\n    case '8':\n    case 'V':\n    case 'C':\n    case 'U':\n    case 'k':\n    case 'K':\n    case 'p':\n    case 'q':\n    case 'A':\n    case 'B':\n    case 'E':\n        {\n            int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;\n\n            shift = 0;\n            signedp = 0;\n            extbits = 16;\n            pcrel = 0;\n            extu = 0;\n            branch = 0;\n            switch (type) {\n            case '<':\n                nbits = 3;\n                immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;\n                extbits = 5;\n                extu = 1;\n                break;\n            case '>':\n                nbits = 3;\n                immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;\n                extbits = 5;\n                extu = 1;\n                break;\n            case '[':\n                nbits = 3;\n                immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;\n                extbits = 6;\n                extu = 1;\n                break;\n            case ']':\n                nbits = 3;\n                immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;\n                extbits = 6;\n                extu = 1;\n                break;\n            case '4':\n                nbits = 4;\n                immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;\n                signedp = 1;\n                extbits = 15;\n                break;\n            case '5':\n                nbits = 5;\n                immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;\n                break;\n            case 'H':\n                nbits = 5;\n                shift = 1;\n                immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;\n                break;\n            case 'W':\n                nbits = 5;\n                shift = 2;\n                immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;\n                break;\n            case 'D':\n                nbits = 5;\n                shift = 3;\n                immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;\n                break;\n            case 'j':\n                nbits = 5;\n                immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;\n                signedp = 1;\n                break;\n            case '6':\n                nbits = 6;\n                immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;\n                break;\n            case '8':\n                nbits = 8;\n                immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;\n                break;\n            case 'V':\n                nbits = 8;\n                shift = 2;\n                immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;\n                /* FIXME: This might be lw, or it might be addiu to $sp or\n                 * $pc.  We assume it's load.  */\n                break;\n            case 'C':\n                nbits = 8;\n                shift = 3;\n                immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;\n                break;\n            case 'U':\n                nbits = 8;\n                immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;\n                extu = 1;\n                break;\n            case 'k':\n                nbits = 8;\n                immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;\n                signedp = 1;\n                break;\n            case 'K':\n                nbits = 8;\n                shift = 3;\n                immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;\n                signedp = 1;\n                break;\n            case 'p':\n                nbits = 8;\n                immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;\n                signedp = 1;\n                pcrel = 1;\n                branch = 1;\n                break;\n            case 'q':\n                nbits = 11;\n                immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;\n                signedp = 1;\n                pcrel = 1;\n                branch = 1;\n                break;\n            case 'A':\n                nbits = 8;\n                shift = 2;\n                immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;\n                pcrel = 1;\n                /* FIXME: This can be lw or la.  We assume it is lw.  */\n                break;\n            case 'B':\n                nbits = 5;\n                shift = 3;\n                immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;\n                pcrel = 1;\n                break;\n            case 'E':\n                nbits = 5;\n                shift = 2;\n                immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;\n                pcrel = 1;\n                break;\n            default:\n                fprintf (stream, \"# internal disassembler error, unrecognised mips16 type (%c)\", type);\n                abort ();\n            }\n\n            if (!use_extend) {\n                if (signedp && immed >= (1 << (nbits - 1)))\n                    immed -= 1 << nbits;\n                immed <<= shift;\n                if ((type == '<' || type == '>' || type == '[' || type == ']')\n                    && immed == 0)\n                    immed = 8;\n            } else {\n                if (extbits == 16)\n                    immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);\n                else if (extbits == 15)\n                    immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);\n                else\n                    immed = ((extend >> 6) & 0x1f) | (extend & 0x20);\n                immed &= (1 << extbits) - 1;\n                if (!extu && immed >= (1 << (extbits - 1)))\n                    immed -= 1 << extbits;\n            }\n\n            if (!pcrel)\n                fprintf (stream, \"%d\", immed);\n            else {\n                unsigned baseaddr;\n\n                if (branch) {\n                    immed *= 2;\n                    baseaddr = memaddr + 2;\n                } else if (use_extend) {\n                    baseaddr = memaddr - 2;\n                } else {\n                    baseaddr = memaddr;\n                }\n                target = (baseaddr & ~((1 << shift) - 1)) + immed;\n                if (pcrel && branch)\n                    /* For gdb disassembler, maintain odd address.  */\n                    target |= 1;\n                print_address (target, stream);\n            }\n        }\n        break;\n\n    case 'a':\n        {\n            int jalx = l & 0x400;\n\n            if (!use_extend)\n                extend = 0;\n            l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);\n            if (! jalx)\n                /* For gdb disassembler, maintain odd address.  */\n                l |= 1;\n        }\n        target = ((memaddr + 4) & ~(unsigned) 0x0fffffff) | l;\n        print_address (target, stream);\n        break;\n\n    case 'l':\n    case 'L':\n        {\n            int need_comma, amask, smask;\n\n            need_comma = 0;\n\n            l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;\n\n            amask = (l >> 3) & 7;\n\n            if (amask > 0 && amask < 5) {\n                fprintf (stream, \"%s\", mips_gpr_names[4]);\n                if (amask > 1)\n                    fprintf (stream, \"-%s\",\n                        mips_gpr_names[amask + 3]);\n                need_comma = 1;\n            }\n\n            smask = (l >> 1) & 3;\n            if (smask == 3) {\n                fprintf (stream, \"%s??\",\n                    need_comma ? \",\" : \"\");\n                need_comma = 1;\n            } else if (smask > 0) {\n                fprintf (stream, \"%s%s\",\n                    need_comma ? \",\" : \"\", mips_gpr_names[16]);\n                if (smask > 1)\n                    fprintf (stream, \"-%s\",\n                        mips_gpr_names[smask + 15]);\n                need_comma = 1;\n            }\n\n            if (l & 1) {\n                fprintf (stream, \"%s%s\",\n                    need_comma ? \",\" : \"\", mips_gpr_names[31]);\n                need_comma = 1;\n            }\n\n            if (amask == 5 || amask == 6) {\n                fprintf (stream, \"%s$f0\",\n                    need_comma ? \",\" : \"\");\n                if (amask == 6)\n                    fprintf (stream, \"-$f1\");\n            }\n        }\n        break;\n\n    case 'm':\n    case 'M':\n        /* MIPS16e save/restore.  */\n        {\n            int need_comma = 0;\n            int amask, args, statics;\n            int nsreg, smask;\n            int framesz;\n            int i, j;\n\n            l = l & 0x7f;\n            if (use_extend)\n                l |= extend << 16;\n\n            amask = (l >> 16) & 0xf;\n            if (amask == MIPS16_ALL_ARGS) {\n                args = 4;\n                statics = 0;\n            } else if (amask == MIPS16_ALL_STATICS) {\n                args = 0;\n                statics = 4;\n            } else {\n                args = amask >> 2;\n                statics = amask & 3;\n            }\n\n            if (args > 0) {\n                fprintf (stream, \"%s\", mips_gpr_names[4]);\n                if (args > 1)\n                    fprintf (stream, \"-%s\",\n                        mips_gpr_names[4 + args - 1]);\n                need_comma = 1;\n            }\n\n            framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;\n            if (framesz == 0 && !use_extend)\n                framesz = 128;\n\n            fprintf (stream, \"%s%d\",\n                need_comma ? \",\" : \"\", framesz);\n\n            if (l & 0x40)       /* $ra */\n                fprintf (stream, \",%s\",\n                    mips_gpr_names[31]);\n\n            nsreg = (l >> 24) & 0x7;\n            smask = 0;\n            if (l & 0x20)       /* $s0 */\n                smask |= 1 << 0;\n            if (l & 0x10)       /* $s1 */\n                smask |= 1 << 1;\n            if (nsreg > 0)      /* $s2-$s8 */\n                smask |= ((1 << nsreg) - 1) << 2;\n\n            /* Find first set static reg bit.  */\n            for (i = 0; i < 9; i++) {\n                if (smask & (1 << i)) {\n                    fprintf (stream, \",%s\",\n                        mips_gpr_names[i == 8 ? 30 : (16 + i)]);\n                    /* Skip over string of set bits.  */\n                    for (j = i; smask & (2 << j); j++)\n                        continue;\n                    if (j > i)\n                        fprintf (stream, \"-%s\",\n                            mips_gpr_names[j == 8 ? 30 : (16 + j)]);\n                    i = j + 1;\n                }\n            }\n\n            /* Statics $ax - $a3.  */\n            if (statics == 1)\n                fprintf (stream, \",%s\",\n                    mips_gpr_names[7]);\n            else if (statics > 0)\n                fprintf (stream, \",%s-%s\",\n                    mips_gpr_names[7 - statics + 1], mips_gpr_names[7]);\n        }\n        break;\n\n    default:\n        /* xgettext:c-format */\n        fprintf (stream, \"# internal disassembler error, unrecognised modifier (%c)\\n\", type);\n        abort ();\n    }\n}\n\n/*\n * Disassemble mips16 instructions.\n */\nstatic void print_insn_mips16 (unsigned memaddr,\n    unsigned int opcode, int nbytes, FILE *stream)\n{\n    int insn, use_extend, extend;\n    const struct mips_opcode *op, *opend;\n\n    insn = opcode;\n    if (nbytes == 2) {\n        use_extend = 0;\n        extend = 0;\n        insn = opcode;\n    } else {\n        if ((opcode & 0xf8000000) == 0xf0000000) {\n            /* Handle the extend opcode specially.  */\n            use_extend = 1;\n            insn = opcode & 0xffff;\n            extend = (opcode >> 16) & 0x7ff;\n        } else {\n            /* jal, jalx */\n            use_extend = 0;\n            insn = opcode >> 16;\n            extend = opcode & 0xffff;\n        }\n    }\n\n    /* FIXME: Should probably use a hash table on the major opcode here.  */\n\n    opend = mips16_opcodes + mips16_num_opcodes;\n    for (op = mips16_opcodes; op < opend; op++) {\n        if (op->pinfo != INSN_MACRO\n            && (insn & op->mask) == op->match) {\n            const char *s;\n\n            fprintf (stream, \"%s\", op->name);\n            if (op->args[0] != '\\0')\n                fprintf (stream, \"\\t\");\n\n            for (s = op->args; *s != '\\0'; s++) {\n                if (*s == ','\n                    && s[1] == 'w'\n                    && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)\n                        == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) {\n                    /* Skip the register and the comma.  */\n                    ++s;\n                    continue;\n                }\n                if (*s == ','\n                    && s[1] == 'v'\n                    && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)\n                        == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) {\n                    /* Skip the register and the comma.  */\n                    ++s;\n                    continue;\n                }\n                print_mips16_insn_arg (*s, op, insn,\n                    use_extend, extend, memaddr, stream);\n            }\n            return;\n        }\n    }\n\n    fprintf (stream, \"0x\");\n    if (use_extend)\n        fprintf (stream, \"%04x\", extend | 0xf000);\n    fprintf (stream, \"%04x\", insn);\n}\n\n/*\n * Disassemble and print the instruction mnemonics.\n * Opcode size can be 4 or 2 bytes.\n * Parameter `isa' defines an instruction set architecture:\n *      0 - mips32 encoding\n *      1 - mips16e encoding\n *      2 - micromips encoding (someday)\n */\nvoid print_mips (unsigned memaddr, unsigned int opcode, int nbytes,\n    int isa, FILE *stream)\n{\n    switch (isa) {\n    default:\n    case 0:\n        print_insn_mips (memaddr, opcode, stream);\n        break;\n    case 1:\n        print_insn_mips16 (memaddr, opcode, nbytes, stream);\n        break;\n    case 2:\n        /* TODO: micromips encoding */\n        break;\n    }\n}\n"
  },
  {
    "path": "tools/virtualmips/mips-opc.c",
    "content": "/*\n * MIPS opcode list.\n *\n * Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002\n * 2003, 2004, 2005, 2006, 2007, 2008, 2009  Free Software Foundation, Inc.\n * Contributed by Ralph Campbell and OSF\n * Commented and modified by Ian Lance Taylor, Cygnus Support\n * Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.\n * MIPS-3D, MDMX, and MIPS32 Release 2 support added by Broadcom\n * Corporation (SiByte).\n * Adapted for VirtualMIPS by Serge Vakulenko.\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n\n/* Short hand so the lines aren't too long.  */\n\n#define LDD     INSN_LOAD_MEMORY_DELAY\n#define LCD     INSN_LOAD_COPROC_DELAY\n#define UBD     INSN_UNCOND_BRANCH_DELAY\n#define CBD     INSN_COND_BRANCH_DELAY\n#define COD     INSN_COPROC_MOVE_DELAY\n#define CLD     INSN_COPROC_MEMORY_DELAY\n#define CBL     INSN_COND_BRANCH_LIKELY\n#define TRAP    INSN_TRAP\n#define SM      INSN_STORE_MEMORY\n\n#define WR_d    INSN_WRITE_GPR_D\n#define WR_t    INSN_WRITE_GPR_T\n#define WR_31   INSN_WRITE_GPR_31\n#define WR_D    INSN_WRITE_FPR_D\n#define WR_T    INSN_WRITE_FPR_T\n#define WR_S    INSN_WRITE_FPR_S\n#define RD_s    INSN_READ_GPR_S\n#define RD_b    INSN_READ_GPR_S\n#define RD_t    INSN_READ_GPR_T\n#define RD_S    INSN_READ_FPR_S\n#define RD_T    INSN_READ_FPR_T\n#define RD_R    INSN_READ_FPR_R\n#define WR_CC   INSN_WRITE_COND_CODE\n#define RD_CC   INSN_READ_COND_CODE\n#define RD_C0   INSN_COP\n#define RD_C1   INSN_COP\n#define RD_C2   INSN_COP\n#define RD_C3   INSN_COP\n#define WR_C0   INSN_COP\n#define WR_C1   INSN_COP\n#define WR_C2   INSN_COP\n#define WR_C3   INSN_COP\n#define CP      INSN_COP\n\n#define WR_HI   INSN_WRITE_HI\n#define RD_HI   INSN_READ_HI\n#define MOD_HI  WR_HI|RD_HI\n\n#define WR_LO   INSN_WRITE_LO\n#define RD_LO   INSN_READ_LO\n#define MOD_LO  WR_LO|RD_LO\n\n#define WR_HILO WR_HI|WR_LO\n#define RD_HILO RD_HI|RD_LO\n#define MOD_HILO WR_HILO|RD_HILO\n\n#define IS_M    INSN_MULT\n\n#define WR_MACC INSN2_WRITE_MDMX_ACC\n#define RD_MACC INSN2_READ_MDMX_ACC\n\n/* MIPS DSP ASE support.\n   NOTE:\n   1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3).  $ac0 is the pair\n   of original HI and LO.  $ac1, $ac2 and $ac3 are new registers, and have\n   the same structure as $ac0 (HI + LO).  For DSP instructions that write or\n   read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a\n   (RD_HILO) attributes, such that HILO dependencies are maintained\n   conservatively.\n\n   2. For some mul. instructions that use integer registers as destinations\n   but destroy HI+LO as side-effect, we add WR_HILO to their attributes.\n\n   3. MIPS DSP ASE includes a new DSP control register, which has 6 fields\n   (ccond, outflag, EFI, c, scount, pos).  Many DSP instructions read or write\n   certain fields of the DSP control register.  For simplicity, we decide not\n   to track dependencies of these fields.\n   However, \"bposge32\" is a branch instruction that depends on the \"pos\"\n   field.  In order to make sure that GAS does not reorder DSP instructions\n   that writes the \"pos\" field and \"bposge32\", we add DSP_VOLA (INSN_TRAP)\n   attribute to those instructions that write the \"pos\" field.  */\n\n#define WR_a        WR_HILO /* Write dsp accumulators (reuse WR_HILO)  */\n#define RD_a        RD_HILO /* Read dsp accumulators (reuse RD_HILO)  */\n#define MOD_a       WR_a|RD_a\n#define DSP_VOLA    INSN_TRAP\n\n/* The order of overloaded instructions matters.  Label arguments and\n   register arguments look the same. Instructions that can have either\n   for arguments must apear in the correct order in this table for the\n   assembler to pick the right one. In other words, entries with\n   immediate operands must apear after the same instruction with\n   registers.\n\n   Because of the lookup algorithm used, entries with the same opcode\n   name must be contiguous.\n\n   Many instructions are short hand for other instructions (i.e., The\n   jal <register> instruction is short for jalr <register>).  */\n\nstatic const struct mips_opcode mips_opcodes[] =\n{\n/* These instructions appear first so that the disassembler will find\n   them first.  The assemblers uses a hash table based on the\n   instruction name anyhow.  */\n/* name,    args,       match,      mask,       pinfo,                  pinfo2 */\n{\"pref\",    \"k,o(b)\",   0xcc000000, 0xfc000000, RD_b, },\n{\"prefx\",   \"h,t(b)\",   0x4c00000f, 0xfc0007ff, RD_b|RD_t|FP_S, },\n{\"nop\",     \"\",         0x00000000, 0xffffffff, 0,                      INSN2_ALIAS, }, /* sll */\n{\"ssnop\",   \"\",         0x00000040, 0xffffffff, 0,                      INSN2_ALIAS, }, /* sll */\n{\"ehb\",     \"\",         0x000000c0, 0xffffffff, 0,                      INSN2_ALIAS, }, /* sll */\n{\"li\",      \"t,j\",      0x24000000, 0xffe00000, WR_t,                   INSN2_ALIAS, }, /* addiu */\n{\"li\",      \"t,i\",      0x34000000, 0xffe00000, WR_t,                   INSN2_ALIAS, }, /* ori */\n{\"li\",      \"t,I\",      0,    (int) M_LI,       INSN_MACRO, },\n{\"move\",    \"d,s\",      0,    (int) M_MOVE,     INSN_MACRO, },\n{\"move\",    \"d,s\",      0x0000002d, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS, },/* daddu */\n{\"move\",    \"d,s\",      0x00000021, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS, },/* addu */\n{\"move\",    \"d,s\",      0x00000025, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS, },/* or */\n{\"b\",       \"p\",        0x10000000, 0xffff0000, UBD,                    INSN2_ALIAS, },/* beq 0,0 */\n{\"b\",       \"p\",        0x04010000, 0xffff0000, UBD,                    INSN2_ALIAS, },/* bgez 0 */\n{\"bal\",     \"p\",        0x04110000, 0xffff0000, UBD|WR_31,              INSN2_ALIAS, },/* bgezal 0*/\n\n{\"abs\",     \"d,v\",      0,    (int) M_ABS,      INSN_MACRO, },\n{\"abs.s\",   \"D,V\",      0x46000005, 0xffff003f, WR_D|RD_S|FP_S, },\n{\"abs.d\",   \"D,V\",      0x46200005, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"abs.ps\",  \"D,V\",      0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"abs.ps\",  \"D,V\",      0x45600005, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"add\",     \"d,v,t\",    0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"add\",     \"t,r,I\",    0,    (int) M_ADD_I,    INSN_MACRO, },\n{\"add\",     \"D,S,T\",    0x45c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, },\n{\"add\",     \"D,S,T\",    0x4b40000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, },\n{\"add.s\",   \"D,V,T\",    0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, },\n{\"add.d\",   \"D,V,T\",    0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"add.ob\",  \"X,Y,Q\",    0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"add.ob\",  \"D,S,T\",    0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"add.ob\",  \"D,S,T[e]\", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, },\n{\"add.ob\",  \"D,S,k\",    0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"add.ps\",  \"D,V,T\",    0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"add.ps\",  \"D,V,T\",    0x45600000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"add.qh\",  \"X,Y,Q\",    0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"adda.ob\", \"Y,Q\",      0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC, },\n{\"adda.qh\", \"Y,Q\",      0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC, },\n{\"addi\",    \"t,r,j\",    0x20000000, 0xfc000000, WR_t|RD_s, },\n{\"addiu\",   \"t,r,j\",    0x24000000, 0xfc000000, WR_t|RD_s, },\n{\"addl.ob\", \"Y,Q\",      0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC, },\n{\"addl.qh\", \"Y,Q\",      0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC, },\n{\"addr.ps\", \"D,S,T\",    0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"addu\",    \"d,v,t\",    0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"addu\",    \"t,r,I\",    0,    (int) M_ADDU_I,   INSN_MACRO, },\n{\"addu\",    \"D,S,T\",    0x45800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, },\n{\"addu\",    \"D,S,T\",    0x4b00000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, },\n{\"alni.ob\", \"X,Y,Z,O\",  0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, },\n{\"alni.ob\", \"D,S,T,%\",  0x48000018, 0xff00003f, WR_D|RD_S|RD_T, },\n{\"alni.qh\", \"X,Y,Z,O\",  0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, },\n{\"alnv.ps\", \"D,V,T,s\",  0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, },\n{\"alnv.ob\", \"X,Y,Z,s\",  0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, },\n{\"alnv.qh\", \"X,Y,Z,s\",  0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, },\n{\"and\",     \"d,v,t\",    0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"and\",     \"t,r,I\",    0,    (int) M_AND_I,    INSN_MACRO, },\n{\"and\", \"D,S,T\",        0x47c00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D, },\n{\"and\", \"D,S,T\",        0x4bc00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D, },\n{\"and.ob\",  \"X,Y,Q\",    0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"and.ob\",  \"D,S,T\",    0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"and.ob\",  \"D,S,T[e]\", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, },\n{\"and.ob\",  \"D,S,k\",    0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"and.qh\",  \"X,Y,Q\",    0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"andi\",    \"t,r,i\",    0x30000000, 0xfc000000, WR_t|RD_s, },\n{\"baddu\",   \"d,v,t\",    0x70000028, 0xfc0007ff, WR_d|RD_s|RD_t, },\n/* b is at the top of the table.  */\n/* bal is at the top of the table.  */\n{\"bbit032\", \"s,+x,p\",   0xd8000000, 0xfc000000, RD_s|CBD, },\n{\"bbit0\",   \"s,+X,p\",   0xd8000000, 0xfc000000, RD_s|CBD, }, /* bbit032 */\n{\"bbit0\",   \"s,+x,p\",   0xc8000000, 0xfc000000, RD_s|CBD, },\n{\"bbit132\", \"s,+x,p\",   0xf8000000, 0xfc000000, RD_s|CBD, },\n{\"bbit1\",   \"s,+X,p\",   0xf8000000, 0xfc000000, RD_s|CBD, }, /* bbit132 */\n{\"bbit1\",   \"s,+x,p\",   0xe8000000, 0xfc000000, RD_s|CBD, },\n/* bc0[tf]l? are at the bottom of the table.  */\n{\"bc1any2f\", \"N,p\",     0x45200000, 0xffe30000, CBD|RD_CC|FP_S, },\n{\"bc1any2t\", \"N,p\",     0x45210000, 0xffe30000, CBD|RD_CC|FP_S, },\n{\"bc1any4f\", \"N,p\",     0x45400000, 0xffe30000, CBD|RD_CC|FP_S, },\n{\"bc1any4t\", \"N,p\",     0x45410000, 0xffe30000, CBD|RD_CC|FP_S, },\n{\"bc1f\",    \"p\",        0x45000000, 0xffff0000, CBD|RD_CC|FP_S, },\n{\"bc1f\",    \"N,p\",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S, },\n{\"bc1fl\",   \"p\",        0x45020000, 0xffff0000, CBL|RD_CC|FP_S, },\n{\"bc1fl\",   \"N,p\",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S, },\n{\"bc1t\",    \"p\",        0x45010000, 0xffff0000, CBD|RD_CC|FP_S, },\n{\"bc1t\",    \"N,p\",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S, },\n{\"bc1tl\",   \"p\",        0x45030000, 0xffff0000, CBL|RD_CC|FP_S, },\n{\"bc1tl\",   \"N,p\",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S, },\n/* bc2* are at the bottom of the table.  */\n/* bc3* are at the bottom of the table.  */\n{\"beqz\",    \"s,p\",      0x10000000, 0xfc1f0000, CBD|RD_s, },\n{\"beqzl\",   \"s,p\",      0x50000000, 0xfc1f0000, CBL|RD_s, },\n{\"beq\",     \"s,t,p\",    0x10000000, 0xfc000000, CBD|RD_s|RD_t, },\n{\"beq\",     \"s,I,p\",    0,    (int) M_BEQ_I,    INSN_MACRO, },\n{\"beql\",    \"s,t,p\",    0x50000000, 0xfc000000, CBL|RD_s|RD_t, },\n{\"beql\",    \"s,I,p\",    0,    (int) M_BEQL_I,   INSN_MACRO, },\n{\"bge\",     \"s,t,p\",    0,    (int) M_BGE,      INSN_MACRO, },\n{\"bge\",     \"s,I,p\",    0,    (int) M_BGE_I,    INSN_MACRO, },\n{\"bgel\",    \"s,t,p\",    0,    (int) M_BGEL,     INSN_MACRO, },\n{\"bgel\",    \"s,I,p\",    0,    (int) M_BGEL_I,   INSN_MACRO, },\n{\"bgeu\",    \"s,t,p\",    0,    (int) M_BGEU,     INSN_MACRO, },\n{\"bgeu\",    \"s,I,p\",    0,    (int) M_BGEU_I,   INSN_MACRO, },\n{\"bgeul\",   \"s,t,p\",    0,    (int) M_BGEUL,    INSN_MACRO, },\n{\"bgeul\",   \"s,I,p\",    0,    (int) M_BGEUL_I,  INSN_MACRO, },\n{\"bgez\",    \"s,p\",      0x04010000, 0xfc1f0000, CBD|RD_s, },\n{\"bgezl\",   \"s,p\",      0x04030000, 0xfc1f0000, CBL|RD_s, },\n{\"bgezal\",  \"s,p\",      0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, },\n{\"bgezall\", \"s,p\",      0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, },\n{\"bgt\",     \"s,t,p\",    0,    (int) M_BGT,      INSN_MACRO, },\n{\"bgt\",     \"s,I,p\",    0,    (int) M_BGT_I,    INSN_MACRO, },\n{\"bgtl\",    \"s,t,p\",    0,    (int) M_BGTL,     INSN_MACRO, },\n{\"bgtl\",    \"s,I,p\",    0,    (int) M_BGTL_I,   INSN_MACRO, },\n{\"bgtu\",    \"s,t,p\",    0,    (int) M_BGTU,     INSN_MACRO, },\n{\"bgtu\",    \"s,I,p\",    0,    (int) M_BGTU_I,   INSN_MACRO, },\n{\"bgtul\",   \"s,t,p\",    0,    (int) M_BGTUL,    INSN_MACRO, },\n{\"bgtul\",   \"s,I,p\",    0,    (int) M_BGTUL_I,  INSN_MACRO, },\n{\"bgtz\",    \"s,p\",      0x1c000000, 0xfc1f0000, CBD|RD_s, },\n{\"bgtzl\",   \"s,p\",      0x5c000000, 0xfc1f0000, CBL|RD_s, },\n{\"ble\",     \"s,t,p\",    0,    (int) M_BLE,      INSN_MACRO, },\n{\"ble\",     \"s,I,p\",    0,    (int) M_BLE_I,    INSN_MACRO, },\n{\"blel\",    \"s,t,p\",    0,    (int) M_BLEL,     INSN_MACRO, },\n{\"blel\",    \"s,I,p\",    0,    (int) M_BLEL_I,   INSN_MACRO, },\n{\"bleu\",    \"s,t,p\",    0,    (int) M_BLEU,     INSN_MACRO, },\n{\"bleu\",    \"s,I,p\",    0,    (int) M_BLEU_I,   INSN_MACRO, },\n{\"bleul\",   \"s,t,p\",    0,    (int) M_BLEUL,    INSN_MACRO, },\n{\"bleul\",   \"s,I,p\",    0,    (int) M_BLEUL_I,  INSN_MACRO, },\n{\"blez\",    \"s,p\",      0x18000000, 0xfc1f0000, CBD|RD_s, },\n{\"blezl\",   \"s,p\",      0x58000000, 0xfc1f0000, CBL|RD_s, },\n{\"blt\",     \"s,t,p\",    0,    (int) M_BLT,      INSN_MACRO, },\n{\"blt\",     \"s,I,p\",    0,    (int) M_BLT_I,    INSN_MACRO, },\n{\"bltl\",    \"s,t,p\",    0,    (int) M_BLTL,     INSN_MACRO, },\n{\"bltl\",    \"s,I,p\",    0,    (int) M_BLTL_I,   INSN_MACRO, },\n{\"bltu\",    \"s,t,p\",    0,    (int) M_BLTU,     INSN_MACRO, },\n{\"bltu\",    \"s,I,p\",    0,    (int) M_BLTU_I,   INSN_MACRO, },\n{\"bltul\",   \"s,t,p\",    0,    (int) M_BLTUL,    INSN_MACRO, },\n{\"bltul\",   \"s,I,p\",    0,    (int) M_BLTUL_I,  INSN_MACRO, },\n{\"bltz\",    \"s,p\",      0x04000000, 0xfc1f0000, CBD|RD_s, },\n{\"bltzl\",   \"s,p\",      0x04020000, 0xfc1f0000, CBL|RD_s, },\n{\"bltzal\",  \"s,p\",      0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, },\n{\"bltzall\", \"s,p\",      0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, },\n{\"bnez\",    \"s,p\",      0x14000000, 0xfc1f0000, CBD|RD_s, },\n{\"bnezl\",   \"s,p\",      0x54000000, 0xfc1f0000, CBL|RD_s, },\n{\"bne\",     \"s,t,p\",    0x14000000, 0xfc000000, CBD|RD_s|RD_t, },\n{\"bne\",     \"s,I,p\",    0,    (int) M_BNE_I,    INSN_MACRO, },\n{\"bnel\",    \"s,t,p\",    0x54000000, 0xfc000000, CBL|RD_s|RD_t, },\n{\"bnel\",    \"s,I,p\",    0,    (int) M_BNEL_I,   INSN_MACRO, },\n{\"break\",   \"\",         0x0000000d, 0xffffffff, TRAP, },\n{\"break\",   \"c\",        0x0000000d, 0xfc00ffff, TRAP, },\n{\"break\",   \"c,q\",      0x0000000d, 0xfc00003f, TRAP, },\n{\"c.f.d\",   \"S,T\",      0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.f.d\",   \"M,S,T\",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.f.s\",   \"S,T\",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.f.s\",   \"M,S,T\",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.f.ps\",  \"S,T\",      0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.f.ps\",  \"S,T\",      0x45600030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.f.ps\",  \"M,S,T\",    0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.un.d\",  \"S,T\",      0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.un.d\",  \"M,S,T\",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.un.s\",  \"S,T\",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.un.s\",  \"M,S,T\",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.un.ps\", \"S,T\",      0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.un.ps\", \"S,T\",      0x45600031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.un.ps\", \"M,S,T\",    0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.eq.d\",  \"S,T\",      0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.eq.d\",  \"M,S,T\",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.eq.s\",  \"S,T\",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.eq.s\",  \"M,S,T\",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.eq.ob\", \"Y,Q\",      0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, },\n{\"c.eq.ob\", \"S,T\",      0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, },\n{\"c.eq.ob\", \"S,T[e]\",   0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, },\n{\"c.eq.ob\", \"S,k\",      0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, },\n{\"c.eq.ps\", \"S,T\",      0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.eq.ps\", \"S,T\",      0x45600032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.eq.ps\", \"M,S,T\",    0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.eq.qh\", \"Y,Q\",      0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, },\n{\"c.ueq.d\", \"S,T\",      0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ueq.d\", \"M,S,T\",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ueq.s\", \"S,T\",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.ueq.s\", \"M,S,T\",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.ueq.ps\",\"S,T\",      0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ueq.ps\",\"S,T\",      0x45600033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ueq.ps\",\"M,S,T\",    0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.olt.d\", \"S,T\",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.olt.d\", \"M,S,T\",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.olt.s\", \"S,T\",      0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.olt.s\", \"M,S,T\",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.olt.ps\",\"S,T\",      0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.olt.ps\",\"S,T\",      0x45600034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.olt.ps\",\"M,S,T\",    0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ult.d\", \"S,T\",      0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ult.d\", \"M,S,T\",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ult.s\", \"S,T\",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.ult.s\", \"M,S,T\",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.ult.ps\",\"S,T\",      0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ult.ps\",\"S,T\",      0x45600035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ult.ps\",\"M,S,T\",    0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ole.d\", \"S,T\",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ole.d\", \"M,S,T\",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ole.s\", \"S,T\",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.ole.s\", \"M,S,T\",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.ole.ps\",\"S,T\",      0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ole.ps\",\"S,T\",      0x45600036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ole.ps\",\"M,S,T\",    0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ule.d\", \"S,T\",      0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ule.d\", \"M,S,T\",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ule.s\", \"S,T\",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.ule.s\", \"M,S,T\",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.ule.ps\",\"S,T\",      0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ule.ps\",\"S,T\",      0x45600037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ule.ps\",\"M,S,T\",    0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.sf.d\",  \"S,T\",      0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.sf.d\",  \"M,S,T\",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.sf.s\",  \"S,T\",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.sf.s\",  \"M,S,T\",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.sf.ps\", \"S,T\",      0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.sf.ps\", \"S,T\",      0x45600038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.sf.ps\", \"M,S,T\",    0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ngle.d\",\"S,T\",      0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ngle.d\",\"M,S,T\",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ngle.s\",\"S,T\",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.ngle.s\",\"M,S,T\",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.ngle.ps\",\"S,T\",     0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ngle.ps\",\"S,T\",     0x45600039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ngle.ps\",\"M,S,T\",   0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.seq.d\", \"S,T\",      0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.seq.d\", \"M,S,T\",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.seq.s\", \"S,T\",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.seq.s\", \"M,S,T\",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.seq.ps\",\"S,T\",      0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.seq.ps\",\"S,T\",      0x4560003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.seq.ps\",\"M,S,T\",    0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ngl.d\", \"S,T\",      0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ngl.d\", \"M,S,T\",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ngl.s\", \"S,T\",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.ngl.s\", \"M,S,T\",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.ngl.ps\",\"S,T\",      0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ngl.ps\",\"S,T\",      0x4560003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ngl.ps\",\"M,S,T\",    0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.lt.d\",  \"S,T\",      0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.lt.d\",  \"M,S,T\",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.lt.s\",  \"S,T\",      0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.lt.s\",  \"M,S,T\",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.lt.ob\", \"Y,Q\",      0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, },\n{\"c.lt.ob\", \"S,T\",      0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, },\n{\"c.lt.ob\", \"S,T[e]\",   0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, },\n{\"c.lt.ob\", \"S,k\",      0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, },\n{\"c.lt.ps\", \"S,T\",      0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.lt.ps\", \"S,T\",      0x4560003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.lt.ps\", \"M,S,T\",    0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.lt.qh\", \"Y,Q\",      0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, },\n{\"c.nge.d\", \"S,T\",      0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.nge.d\", \"M,S,T\",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.nge.s\", \"S,T\",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.nge.s\", \"M,S,T\",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.nge.ps\",\"S,T\",      0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.nge.ps\",\"S,T\",      0x4560003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.nge.ps\",\"M,S,T\",    0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.le.d\",  \"S,T\",      0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.le.d\",  \"M,S,T\",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.le.s\",  \"S,T\",      0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.le.s\",  \"M,S,T\",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.le.ob\", \"Y,Q\",      0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, },\n{\"c.le.ob\", \"S,T\",      0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, },\n{\"c.le.ob\", \"S,T[e]\",   0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, },\n{\"c.le.ob\", \"S,k\",      0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, },\n{\"c.le.ps\", \"S,T\",      0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.le.ps\", \"S,T\",      0x4560003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.le.ps\", \"M,S,T\",    0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.le.qh\", \"Y,Q\",      0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, },\n{\"c.ngt.d\", \"S,T\",      0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ngt.d\", \"M,S,T\",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ngt.s\", \"S,T\",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.ngt.s\", \"M,S,T\",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"c.ngt.ps\",\"S,T\",      0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ngt.ps\",\"S,T\",      0x4560003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"c.ngt.ps\",\"M,S,T\",    0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.eq.d\",  \"M,S,T\", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.eq.ps\", \"M,S,T\", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.eq.s\",  \"M,S,T\", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"cabs.f.d\",   \"M,S,T\", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.f.ps\",  \"M,S,T\", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.f.s\",   \"M,S,T\", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"cabs.le.d\",  \"M,S,T\", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.le.ps\", \"M,S,T\", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.le.s\",  \"M,S,T\", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"cabs.lt.d\",  \"M,S,T\", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.lt.ps\", \"M,S,T\", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.lt.s\",  \"M,S,T\", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"cabs.nge.d\", \"M,S,T\", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.nge.ps\",\"M,S,T\", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.nge.s\", \"M,S,T\", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"cabs.ngl.d\", \"M,S,T\", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.ngl.ps\",\"M,S,T\", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.ngl.s\", \"M,S,T\", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"cabs.ngle.d\",\"M,S,T\", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.ngle.ps\",\"M,S,T\",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.ngle.s\",\"M,S,T\", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"cabs.ngt.d\", \"M,S,T\", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.ngt.ps\",\"M,S,T\", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.ngt.s\", \"M,S,T\", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"cabs.ole.d\", \"M,S,T\", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.ole.ps\",\"M,S,T\", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.ole.s\", \"M,S,T\", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"cabs.olt.d\", \"M,S,T\", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.olt.ps\",\"M,S,T\", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.olt.s\", \"M,S,T\", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"cabs.seq.d\", \"M,S,T\", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.seq.ps\",\"M,S,T\", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.seq.s\", \"M,S,T\", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"cabs.sf.d\",  \"M,S,T\", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.sf.ps\", \"M,S,T\", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.sf.s\",  \"M,S,T\", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"cabs.ueq.d\", \"M,S,T\", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.ueq.ps\",\"M,S,T\", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.ueq.s\", \"M,S,T\", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"cabs.ule.d\", \"M,S,T\", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.ule.ps\",\"M,S,T\", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.ule.s\", \"M,S,T\", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"cabs.ult.d\", \"M,S,T\", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.ult.ps\",\"M,S,T\", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.ult.s\", \"M,S,T\", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n{\"cabs.un.d\",  \"M,S,T\", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.un.ps\", \"M,S,T\", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"cabs.un.s\",  \"M,S,T\", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, },\n/* CW4010 instructions which are aliases for the cache instruction.  */\n{\"flushi\",  \"\",         0xbc010000, 0xffffffff, 0, },\n{\"flushd\",  \"\",         0xbc020000, 0xffffffff, 0, },\n{\"flushid\", \"\",         0xbc030000, 0xffffffff, 0, },\n{\"wb\",      \"o(b)\",     0xbc040000, 0xfc1f0000, SM|RD_b, },\n{\"cache\",   \"k,o(b)\",   0xbc000000, 0xfc000000, RD_b, },\n{\"cache\",   \"k,A(b)\",   0,    (int) M_CACHE_AB, INSN_MACRO, },\n{\"ceil.l.d\", \"D,S\",     0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"ceil.l.s\", \"D,S\",     0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, },\n{\"ceil.w.d\", \"D,S\",     0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, },\n{\"ceil.w.s\", \"D,S\",     0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, },\n{\"cfc0\",    \"t,G\",      0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, },\n{\"cfc1\",    \"t,G\",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, },\n{\"cfc1\",    \"t,S\",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, },\n/* cfc2 is at the bottom of the table.  */\n/* cfc3 is at the bottom of the table.  */\n{\"cftc1\",   \"d,E\",      0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, },\n{\"cftc1\",   \"d,T\",      0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, },\n{\"cftc2\",   \"d,E\",      0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, },\n{\"cins32\",  \"t,r,+p,+S\",0x70000033, 0xfc00003f, WR_t|RD_s, },\n{\"cins\",    \"t,r,+P,+S\",0x70000033, 0xfc00003f, WR_t|RD_s, }, /* cins32 */\n{\"cins\",    \"t,r,+p,+s\",0x70000032, 0xfc00003f, WR_t|RD_s, },\n{\"clo\",     \"U,s\",      0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, },\n{\"clz\",     \"U,s\",      0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, },\n{\"ctc0\",    \"t,G\",      0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, },\n{\"ctc1\",    \"t,G\",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, },\n{\"ctc1\",    \"t,S\",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, },\n/* ctc2 is at the bottom of the table.  */\n/* ctc3 is at the bottom of the table.  */\n{\"cttc1\",   \"t,g\",      0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, },\n{\"cttc1\",   \"t,S\",      0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, },\n{\"cttc2\",   \"t,g\",      0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, },\n{\"cvt.d.l\", \"D,S\",      0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"cvt.d.s\", \"D,S\",      0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, },\n{\"cvt.d.w\", \"D,S\",      0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, },\n{\"cvt.l.d\", \"D,S\",      0x46200025, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"cvt.l.s\", \"D,S\",      0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D, },\n{\"cvt.s.l\", \"D,S\",      0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, },\n{\"cvt.s.d\", \"D,S\",      0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, },\n{\"cvt.s.w\", \"D,S\",      0x46800020, 0xffff003f, WR_D|RD_S|FP_S, },\n{\"cvt.s.pl\",\"D,S\",      0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, },\n{\"cvt.s.pu\",\"D,S\",      0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, },\n{\"cvt.w.d\", \"D,S\",      0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, },\n{\"cvt.w.s\", \"D,S\",      0x46000024, 0xffff003f, WR_D|RD_S|FP_S, },\n{\"cvt.ps.pw\", \"D,S\",    0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, },\n{\"cvt.ps.s\",\"D,V,T\",    0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, },\n{\"cvt.pw.ps\", \"D,S\",    0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, },\n{\"dabs\",    \"d,v\",      0,    (int) M_DABS,     INSN_MACRO, },\n{\"dadd\",    \"d,v,t\",    0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"dadd\",    \"t,r,I\",    0,    (int) M_DADD_I,   INSN_MACRO, },\n{\"dadd\",    \"D,S,T\",    0x45e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"dadd\",    \"D,S,T\",    0x4b60000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"daddi\",   \"t,r,j\",    0x60000000, 0xfc000000, WR_t|RD_s, },\n{\"daddiu\",  \"t,r,j\",    0x64000000, 0xfc000000, WR_t|RD_s, },\n{\"daddu\",   \"d,v,t\",    0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"daddu\",   \"t,r,I\",    0,    (int) M_DADDU_I,  INSN_MACRO, },\n{\"daddwc\",  \"d,s,t\",    0x70000038, 0xfc0007ff, WR_d|RD_s|RD_t|WR_C0|RD_C0, },\n{\"sdbbp\",   \"\",         0x7000003f, 0xffffffff, 0, },\n{\"dclo\",    \"U,s\",      0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, },\n{\"dclz\",    \"U,s\",      0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, },\n/* dctr and dctw are used on the r5000.  */\n{\"dctr\",    \"o(b)\",     0xbc050000, 0xfc1f0000, RD_b, },\n{\"dctw\",    \"o(b)\",     0xbc090000, 0xfc1f0000, RD_b, },\n{\"deret\",   \"\",         0x4200001f, 0xffffffff, 0, },\n{\"dext\",    \"t,r,I,+I\", 0,    (int) M_DEXT,     INSN_MACRO, },\n{\"dext\",    \"t,r,+A,+C\", 0x7c000003, 0xfc00003f, WR_t|RD_s, },\n{\"dextm\",   \"t,r,+A,+G\", 0x7c000001, 0xfc00003f, WR_t|RD_s, },\n{\"dextu\",   \"t,r,+E,+H\", 0x7c000002, 0xfc00003f, WR_t|RD_s, },\n/* For ddiv, see the comments about div.  */\n{\"ddiv\",    \"z,s,t\",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, },\n{\"ddiv\",    \"d,v,t\",    0,    (int) M_DDIV_3,   INSN_MACRO, },\n{\"ddiv\",    \"d,v,I\",    0,    (int) M_DDIV_3I,  INSN_MACRO, },\n/* For ddivu, see the comments about div.  */\n{\"ddivu\",   \"z,s,t\",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, },\n{\"ddivu\",   \"d,v,t\",    0,    (int) M_DDIVU_3,  INSN_MACRO, },\n{\"ddivu\",   \"d,v,I\",    0,    (int) M_DDIVU_3I, INSN_MACRO, },\n{\"di\",      \"\",         0x41606000, 0xffffffff, WR_t|WR_C0, },\n{\"di\",      \"t\",        0x41606000, 0xffe0ffff, WR_t|WR_C0, },\n{\"dins\",    \"t,r,I,+I\", 0,    (int) M_DINS,     INSN_MACRO, },\n{\"dins\",    \"t,r,+A,+B\", 0x7c000007, 0xfc00003f, WR_t|RD_s, },\n{\"dinsm\",   \"t,r,+A,+F\", 0x7c000005, 0xfc00003f, WR_t|RD_s, },\n{\"dinsu\",   \"t,r,+E,+F\", 0x7c000006, 0xfc00003f, WR_t|RD_s, },\n/* The MIPS assembler treats the div opcode with two operands as\n   though the first operand appeared twice (the first operand is both\n   a source and a destination).  To get the div machine instruction,\n   you must use an explicit destination of $0.  */\n{\"div\",     \"z,s,t\",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, },\n{\"div\",     \"z,t\",      0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, },\n{\"div\",     \"d,v,t\",    0,    (int) M_DIV_3,    INSN_MACRO, },\n{\"div\",     \"d,v,I\",    0,    (int) M_DIV_3I,   INSN_MACRO, },\n{\"div.d\",   \"D,V,T\",    0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"div.s\",   \"D,V,T\",    0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, },\n{\"div.ps\",  \"D,V,T\",    0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n/* For divu, see the comments about div.  */\n{\"divu\",    \"z,s,t\",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, },\n{\"divu\",    \"z,t\",      0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, },\n{\"divu\",    \"d,v,t\",    0,    (int) M_DIVU_3,   INSN_MACRO, },\n{\"divu\",    \"d,v,I\",    0,    (int) M_DIVU_3I,  INSN_MACRO, },\n{\"dla\",     \"t,A(b)\",   0,    (int) M_DLA_AB,   INSN_MACRO, },\n{\"dlca\",    \"t,A(b)\",   0,    (int) M_DLCA_AB,  INSN_MACRO, },\n{\"dli\",     \"t,j\",      0x24000000, 0xffe00000, WR_t, }, /* addiu */\n{\"dli\",     \"t,i\",      0x34000000, 0xffe00000, WR_t, }, /* ori */\n{\"dli\",     \"t,I\",      0,    (int) M_DLI,      INSN_MACRO, },\n{\"dmacc\",   \"d,s,t\",    0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, },\n{\"dmacchi\", \"d,s,t\",    0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, },\n{\"dmacchis\", \"d,s,t\",   0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, },\n{\"dmacchiu\", \"d,s,t\",   0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, },\n{\"dmacchius\", \"d,s,t\",  0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, },\n{\"dmaccs\",  \"d,s,t\",    0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, },\n{\"dmaccu\",  \"d,s,t\",    0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, },\n{\"dmaccus\", \"d,s,t\",    0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, },\n{\"dmadd16\", \"s,t\",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, },\n{\"dmfc0\",   \"t,G\",      0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, },\n{\"dmfc0\",   \"t,+D\",     0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, },\n{\"dmfc0\",   \"t,G,H\",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, },\n{\"dmt\",     \"\",         0x41600bc1, 0xffffffff, TRAP, },\n{\"dmt\",     \"t\",        0x41600bc1, 0xffe0ffff, TRAP|WR_t, },\n{\"dmtc0\",   \"t,G\",      0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, },\n{\"dmtc0\",   \"t,+D\",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, },\n{\"dmtc0\",   \"t,G,H\",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, },\n{\"dmfc1\",   \"t,S\",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, },\n{\"dmfc1\",   \"t,G\",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, },\n{\"dmtc1\",   \"t,S\",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, },\n{\"dmtc1\",   \"t,G\",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, },\n/* dmfc2 is at the bottom of the table.  */\n/* dmtc2 is at the bottom of the table.  */\n/* dmfc3 is at the bottom of the table.  */\n/* dmtc3 is at the bottom of the table.  */\n{\"dmul\",    \"d,v,t\",    0x70000003, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, },\n{\"dmul\",    \"d,v,t\",    0,    (int) M_DMUL,     INSN_MACRO, },\n{\"dmul\",    \"d,v,I\",    0,    (int) M_DMUL_I,   INSN_MACRO, },\n{\"dmulo\",   \"d,v,t\",    0,    (int) M_DMULO,    INSN_MACRO, },\n{\"dmulo\",   \"d,v,I\",    0,    (int) M_DMULO_I,  INSN_MACRO, },\n{\"dmulou\",  \"d,v,t\",    0,    (int) M_DMULOU,   INSN_MACRO, },\n{\"dmulou\",  \"d,v,I\",    0,    (int) M_DMULOU_I, INSN_MACRO, },\n{\"dmult\",   \"s,t\",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, },\n{\"dmultu\",  \"s,t\",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, },\n{\"dneg\",    \"d,w\",      0x0000002e, 0xffe007ff, WR_d|RD_t, }, /* dsub 0 */\n{\"dnegu\",   \"d,w\",      0x0000002f, 0xffe007ff, WR_d|RD_t, }, /* dsubu 0*/\n{\"dpop\",    \"d,v\",      0x7000002d, 0xfc1f07ff, WR_d|RD_s, },\n{\"drem\",    \"z,s,t\",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, },\n{\"drem\",    \"d,v,t\",    0,    (int) M_DREM_3,   INSN_MACRO, },\n{\"drem\",    \"d,v,I\",    0,    (int) M_DREM_3I,  INSN_MACRO, },\n{\"dremu\",   \"z,s,t\",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, },\n{\"dremu\",   \"d,v,t\",    0,    (int) M_DREMU_3,  INSN_MACRO, },\n{\"dremu\",   \"d,v,I\",    0,    (int) M_DREMU_3I, INSN_MACRO, },\n{\"dret\",    \"\",         0x7000003e, 0xffffffff, 0, },\n{\"drol\",    \"d,v,t\",    0,    (int) M_DROL,     INSN_MACRO, },\n{\"drol\",    \"d,v,I\",    0,    (int) M_DROL_I,   INSN_MACRO, },\n{\"dror\",    \"d,v,t\",    0,    (int) M_DROR,     INSN_MACRO, },\n{\"dror\",    \"d,v,I\",    0,    (int) M_DROR_I,   INSN_MACRO, },\n{\"dror\",    \"d,w,<\",    0x0020003a, 0xffe0003f, WR_d|RD_t, },\n{\"drorv\",   \"d,t,s\",    0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, },\n{\"dror32\",  \"d,w,<\",    0x0020003e, 0xffe0003f, WR_d|RD_t, },\n{\"drotl\",   \"d,v,t\",    0,    (int) M_DROL,     INSN_MACRO, },\n{\"drotl\",   \"d,v,I\",    0,    (int) M_DROL_I,   INSN_MACRO, },\n{\"dror\",    \"d,v,t\",    0,    (int) M_DROR,     INSN_MACRO, },\n{\"dror\",    \"d,v,I\",    0,    (int) M_DROR_I,   INSN_MACRO, },\n{\"drorv\",   \"d,t,s\",    0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, },\n{\"dror32\",  \"d,w,<\",    0x0020003e, 0xffe0003f, WR_d|RD_t, },\n{\"dsbh\",    \"d,w\",      0x7c0000a4, 0xffe007ff, WR_d|RD_t, },\n{\"dshd\",    \"d,w\",      0x7c000164, 0xffe007ff, WR_d|RD_t, },\n{\"dsllv\",   \"d,t,s\",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, },\n{\"dsll32\",  \"d,w,<\",    0x0000003c, 0xffe0003f, WR_d|RD_t, },\n{\"dsll\",    \"d,w,s\",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, }, /* dsllv */\n{\"dsll\",    \"d,w,>\",    0x0000003c, 0xffe0003f, WR_d|RD_t, }, /* dsll32 */\n{\"dsll\",    \"d,w,<\",    0x00000038, 0xffe0003f, WR_d|RD_t, },\n{\"dsll\",    \"D,S,T\",    0x45a00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D, },\n{\"dsll\",    \"D,S,T\",    0x4b20000e,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D, },\n{\"dsrav\",   \"d,t,s\",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, },\n{\"dsra32\",  \"d,w,<\",    0x0000003f, 0xffe0003f, WR_d|RD_t, },\n{\"dsra\",    \"d,w,s\",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, }, /* dsrav */\n{\"dsra\",    \"d,w,>\",    0x0000003f, 0xffe0003f, WR_d|RD_t, }, /* dsra32 */\n{\"dsra\",    \"d,w,<\",    0x0000003b, 0xffe0003f, WR_d|RD_t, },\n{\"dsra\",    \"D,S,T\",    0x45e00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D, },\n{\"dsra\",    \"D,S,T\",    0x4b60000f,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D, },\n{\"dsrlv\",   \"d,t,s\",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, },\n{\"dsrl32\",  \"d,w,<\",    0x0000003e, 0xffe0003f, WR_d|RD_t, },\n{\"dsrl\",    \"d,w,s\",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, }, /* dsrlv */\n{\"dsrl\",    \"d,w,>\",    0x0000003e, 0xffe0003f, WR_d|RD_t, }, /* dsrl32 */\n{\"dsrl\",    \"d,w,<\",    0x0000003a, 0xffe0003f, WR_d|RD_t, },\n{\"dsrl\",    \"D,S,T\",    0x45a00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D, },\n{\"dsrl\",    \"D,S,T\",    0x4b20000f,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D, },\n{\"dsub\",    \"d,v,t\",    0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"dsub\",    \"d,v,I\",    0,    (int) M_DSUB_I,   INSN_MACRO, },\n{\"dsub\",    \"D,S,T\",    0x45e00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D, },\n{\"dsub\",    \"D,S,T\",    0x4b60000d,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D, },\n{\"dsubu\",   \"d,v,t\",    0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"dsubu\",   \"d,v,I\",    0,    (int) M_DSUBU_I,  INSN_MACRO, },\n{\"dvpe\",    \"\",         0x41600001, 0xffffffff, TRAP, },\n{\"dvpe\",    \"t\",        0x41600001, 0xffe0ffff, TRAP|WR_t, },\n{\"ei\",      \"\",         0x41606020, 0xffffffff, WR_t|WR_C0, },\n{\"ei\",      \"t\",        0x41606020, 0xffe0ffff, WR_t|WR_C0, },\n{\"emt\",     \"\",         0x41600be1, 0xffffffff, TRAP, },\n{\"emt\",     \"t\",        0x41600be1, 0xffe0ffff, TRAP|WR_t, },\n{\"eret\",    \"\",         0x42000018, 0xffffffff, 0, },\n{\"evpe\",    \"\",         0x41600021, 0xffffffff, TRAP, },\n{\"evpe\",    \"t\",        0x41600021, 0xffe0ffff, TRAP|WR_t, },\n{\"ext\",     \"t,r,+A,+C\", 0x7c000000, 0xfc00003f, WR_t|RD_s, },\n{\"exts32\",  \"t,r,+p,+S\",0x7000003b, 0xfc00003f, WR_t|RD_s, },\n{\"exts\",    \"t,r,+P,+S\",0x7000003b, 0xfc00003f, WR_t|RD_s, }, /* exts32 */\n{\"exts\",    \"t,r,+p,+s\",0x7000003a, 0xfc00003f, WR_t|RD_s, },\n{\"floor.l.d\", \"D,S\",    0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"floor.l.s\", \"D,S\",    0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, },\n{\"floor.w.d\", \"D,S\",    0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, },\n{\"floor.w.s\", \"D,S\",    0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, },\n{\"hibernate\",\"\",        0x42000023, 0xffffffff, 0, },\n{\"ins\",     \"t,r,+A,+B\", 0x7c000004, 0xfc00003f, WR_t|RD_s, },\n{\"jr\",      \"s\",        0x00000008, 0xfc1fffff, UBD|RD_s, },\n/* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with\n   the same hazard barrier effect.  */\n{\"jr.hb\",   \"s\",        0x00000408, 0xfc1fffff, UBD|RD_s, },\n{\"j\",       \"s\",        0x00000008, 0xfc1fffff, UBD|RD_s, }, /* jr */\n/* SVR4 PIC code requires special handling for j, so it must be a\n   macro.  */\n{\"j\",       \"a\",        0,     (int) M_J_A,     INSN_MACRO, },\n/* This form of j is used by the disassembler and internally by the\n   assembler, but will never match user input (because the line above\n   will match first).  */\n{\"j\",       \"a\",        0x08000000, 0xfc000000, UBD, },\n{\"jalr\",    \"s\",        0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, },\n{\"jalr\",    \"d,s\",      0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, },\n/* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr\n   with the same hazard barrier effect.  */\n{\"jalr.hb\", \"s\",        0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, },\n{\"jalr.hb\", \"d,s\",      0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, },\n/* SVR4 PIC code requires special handling for jal, so it must be a\n   macro.  */\n{\"jal\",     \"d,s\",      0,     (int) M_JAL_2,   INSN_MACRO, },\n{\"jal\",     \"s\",        0,     (int) M_JAL_1,   INSN_MACRO, },\n{\"jal\",     \"a\",        0,     (int) M_JAL_A,   INSN_MACRO, },\n/* This form of jal is used by the disassembler and internally by the\n   assembler, but will never match user input (because the line above\n   will match first).  */\n{\"jal\",     \"a\",        0x0c000000, 0xfc000000, UBD|WR_31, },\n{\"jalx\",    \"a\",        0x74000000, 0xfc000000, UBD|WR_31, },\n{\"la\",      \"t,A(b)\",   0,    (int) M_LA_AB,    INSN_MACRO, },\n{\"lb\",      \"t,o(b)\",   0x80000000, 0xfc000000, LDD|RD_b|WR_t, },\n{\"lb\",      \"t,A(b)\",   0,    (int) M_LB_AB,    INSN_MACRO, },\n{\"lbu\",     \"t,o(b)\",   0x90000000, 0xfc000000, LDD|RD_b|WR_t, },\n{\"lbu\",     \"t,A(b)\",   0,    (int) M_LBU_AB,   INSN_MACRO, },\n{\"lca\",     \"t,A(b)\",   0,    (int) M_LCA_AB,   INSN_MACRO, },\n/* The macro has to be first to handle o32 correctly.  */\n{\"ld\",      \"t,o(b)\",   0,    (int) M_LD_OB,    INSN_MACRO, },\n{\"ld\",      \"t,o(b)\",   0xdc000000, 0xfc000000, WR_t|RD_b, },\n{\"ld\",      \"t,A(b)\",   0,    (int) M_LD_AB,    INSN_MACRO, },\n{\"ldaddw\",  \"t,b\",      0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b, },\n{\"ldaddwu\", \"t,b\",      0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b, },\n{\"ldaddd\",  \"t,b\",      0x70000012, 0xfc00ffff, SM|RD_t|WR_t|RD_b, },\n{\"ldc1\",    \"T,o(b)\",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, },\n{\"ldc1\",    \"E,o(b)\",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, },\n{\"ldc1\",    \"T,A(b)\",   0,    (int) M_LDC1_AB,  INSN_MACRO,             INSN2_M_FP_D, },\n{\"ldc1\",    \"E,A(b)\",   0,    (int) M_LDC1_AB,  INSN_MACRO,             INSN2_M_FP_D, },\n{\"l.d\",     \"T,o(b)\",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, }, /* ldc1 */\n{\"l.d\",     \"T,o(b)\",   0,    (int) M_L_DOB,    INSN_MACRO,             INSN2_M_FP_D, },\n{\"l.d\",     \"T,A(b)\",   0,    (int) M_L_DAB,    INSN_MACRO,             INSN2_M_FP_D, },\n{\"ldc2\",    \"E,o(b)\",   0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, },\n{\"ldc2\",    \"E,A(b)\",   0,    (int) M_LDC2_AB,  INSN_MACRO, },\n{\"ldc3\",    \"E,o(b)\",   0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, },\n{\"ldc3\",    \"E,A(b)\",   0,    (int) M_LDC3_AB,  INSN_MACRO, },\n{\"ldl\",     \"t,o(b)\",   0x68000000, 0xfc000000, LDD|WR_t|RD_b, },\n{\"ldl\",     \"t,A(b)\",   0,    (int) M_LDL_AB,   INSN_MACRO, },\n{\"ldr\",     \"t,o(b)\",   0x6c000000, 0xfc000000, LDD|WR_t|RD_b, },\n{\"ldr\",     \"t,A(b)\",   0,    (int) M_LDR_AB,   INSN_MACRO, },\n{\"ldxc1\",   \"D,t(b)\",   0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, },\n{\"lh\",      \"t,o(b)\",   0x84000000, 0xfc000000, LDD|RD_b|WR_t, },\n{\"lh\",      \"t,A(b)\",   0,    (int) M_LH_AB,    INSN_MACRO, },\n{\"lhu\",     \"t,o(b)\",   0x94000000, 0xfc000000, LDD|RD_b|WR_t, },\n{\"lhu\",     \"t,A(b)\",   0,    (int) M_LHU_AB,   INSN_MACRO, },\n/* li is at the start of the table.  */\n{\"li.d\",    \"t,F\",      0,    (int) M_LI_D,     INSN_MACRO,             INSN2_M_FP_D, },\n{\"li.d\",    \"T,L\",      0,    (int) M_LI_DD,    INSN_MACRO,             INSN2_M_FP_D, },\n{\"li.s\",    \"t,f\",      0,    (int) M_LI_S,     INSN_MACRO,             INSN2_M_FP_S, },\n{\"li.s\",    \"T,l\",      0,    (int) M_LI_SS,    INSN_MACRO,             INSN2_M_FP_S, },\n{\"ll\",      \"t,o(b)\",   0xc0000000, 0xfc000000, LDD|RD_b|WR_t, },\n{\"ll\",      \"t,A(b)\",   0,    (int) M_LL_AB,    INSN_MACRO, },\n{\"lld\",     \"t,o(b)\",   0xd0000000, 0xfc000000, LDD|RD_b|WR_t, },\n{\"lld\",     \"t,A(b)\",   0,    (int) M_LLD_AB,   INSN_MACRO, },\n{\"lui\",     \"t,u\",      0x3c000000, 0xffe00000, WR_t, },\n{\"luxc1\",   \"D,t(b)\",   0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, },\n{\"lw\",      \"t,o(b)\",   0x8c000000, 0xfc000000, LDD|RD_b|WR_t, },\n{\"lw\",      \"t,A(b)\",   0,    (int) M_LW_AB,    INSN_MACRO, },\n{\"lwc0\",    \"E,o(b)\",   0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, },\n{\"lwc0\",    \"E,A(b)\",   0,    (int) M_LWC0_AB,  INSN_MACRO, },\n{\"lwc1\",    \"T,o(b)\",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, },\n{\"lwc1\",    \"E,o(b)\",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, },\n{\"lwc1\",    \"T,A(b)\",   0,    (int) M_LWC1_AB,  INSN_MACRO,             INSN2_M_FP_S, },\n{\"lwc1\",    \"E,A(b)\",   0,    (int) M_LWC1_AB,  INSN_MACRO,             INSN2_M_FP_S, },\n{\"l.s\",     \"T,o(b)\",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, }, /* lwc1 */\n{\"l.s\",     \"T,A(b)\",   0,    (int) M_LWC1_AB,  INSN_MACRO,             INSN2_M_FP_S, },\n{\"lwc2\",    \"E,o(b)\",   0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, },\n{\"lwc2\",    \"E,A(b)\",   0,    (int) M_LWC2_AB,  INSN_MACRO, },\n{\"lwc3\",    \"E,o(b)\",   0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, },\n{\"lwc3\",    \"E,A(b)\",   0,    (int) M_LWC3_AB,  INSN_MACRO, },\n{\"lwl\",     \"t,o(b)\",   0x88000000, 0xfc000000, LDD|RD_b|WR_t, },\n{\"lwl\",     \"t,A(b)\",   0,    (int) M_LWL_AB,   INSN_MACRO, },\n{\"lcache\",  \"t,o(b)\",   0x88000000, 0xfc000000, LDD|RD_b|WR_t, }, /* same */\n{\"lcache\",  \"t,A(b)\",   0,    (int) M_LWL_AB,   INSN_MACRO, }, /* as lwl */\n{\"lwr\",     \"t,o(b)\",   0x98000000, 0xfc000000, LDD|RD_b|WR_t, },\n{\"lwr\",     \"t,A(b)\",   0,    (int) M_LWR_AB,   INSN_MACRO, },\n{\"flush\",   \"t,o(b)\",   0x98000000, 0xfc000000, LDD|RD_b|WR_t, }, /* same */\n{\"flush\",   \"t,A(b)\",   0,    (int) M_LWR_AB,   INSN_MACRO, }, /* as lwr */\n{\"fork\",    \"d,s,t\",    0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, },\n{\"lwu\",     \"t,o(b)\",   0x9c000000, 0xfc000000, LDD|RD_b|WR_t, },\n{\"lwu\",     \"t,A(b)\",   0,    (int) M_LWU_AB,   INSN_MACRO, },\n{\"lwxc1\",   \"D,t(b)\",   0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_S, },\n{\"lwxs\",    \"d,t(b)\",   0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d, },\n{\"macc\",    \"d,s,t\",    0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"macc\",    \"d,s,t\",    0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"maccs\",   \"d,s,t\",    0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"macchi\",  \"d,s,t\",    0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"macchi\",  \"d,s,t\",    0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"macchis\", \"d,s,t\",    0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"macchiu\", \"d,s,t\",    0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"macchiu\", \"d,s,t\",    0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"macchius\",\"d,s,t\",    0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"maccu\",   \"d,s,t\",    0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"maccu\",   \"d,s,t\",    0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"maccus\",  \"d,s,t\",    0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"mad\",     \"s,t\",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, },\n{\"madu\",    \"s,t\",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, },\n{\"madd.d\",  \"D,R,S,T\",  0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, },\n{\"madd.d\",  \"D,S,T\",    0x46200018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"madd.d\",  \"D,S,T\",    0x72200018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"madd.s\",  \"D,R,S,T\",  0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, },\n{\"madd.s\",  \"D,S,T\",    0x46000018, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, },\n{\"madd.s\",  \"D,S,T\",    0x72000018, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, },\n{\"madd.ps\", \"D,R,S,T\",  0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, },\n{\"madd.ps\", \"D,S,T\",    0x45600018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"madd.ps\", \"D,S,T\",    0x71600018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"madd\",    \"s,t\",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, },\n{\"madd\",    \"s,t\",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, },\n{\"madd\",    \"s,t\",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, },\n{\"madd\",    \"7,s,t\",    0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"madd\",    \"d,s,t\",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, },\n{\"maddp\",   \"s,t\",      0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, },\n{\"maddu\",   \"s,t\",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, },\n{\"maddu\",   \"s,t\",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, },\n{\"maddu\",   \"s,t\",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, },\n{\"maddu\",   \"7,s,t\",    0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"maddu\",   \"d,s,t\",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, },\n{\"madd16\",  \"s,t\",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, },\n{\"max.ob\",  \"X,Y,Q\",    0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"max.ob\",  \"D,S,T\",    0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"max.ob\",  \"D,S,T[e]\", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, },\n{\"max.ob\",  \"D,S,k\",    0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"max.qh\",  \"X,Y,Q\",    0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"mfpc\",    \"t,P\",      0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, },\n{\"mfps\",    \"t,P\",      0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, },\n{\"mftacx\",  \"d\",        0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, },\n{\"mftacx\",  \"d,*\",      0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, },\n{\"mftc0\",   \"d,+t\",     0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, },\n{\"mftc0\",   \"d,+T\",     0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, },\n{\"mftc0\",   \"d,E,H\",    0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, },\n{\"mftc1\",   \"d,T\",      0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, },\n{\"mftc1\",   \"d,E\",      0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, },\n{\"mftc2\",   \"d,E\",      0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, },\n{\"mftdsp\",  \"d\",        0x41100021, 0xffff07ff, TRAP|WR_d, },\n{\"mftgpr\",  \"d,t\",      0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, },\n{\"mfthc1\",  \"d,T\",      0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, },\n{\"mfthc1\",  \"d,E\",      0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, },\n{\"mfthc2\",  \"d,E\",      0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, },\n{\"mfthi\",   \"d\",        0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, },\n{\"mfthi\",   \"d,*\",      0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, },\n{\"mftlo\",   \"d\",        0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, },\n{\"mftlo\",   \"d,*\",      0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, },\n{\"mftr\",    \"d,t,!,H,$\", 0x41000000, 0xffe007c8, TRAP|WR_d, },\n{\"mfc0\",    \"t,G\",      0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, },\n{\"mfc0\",    \"t,+D\",     0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, },\n{\"mfc0\",    \"t,G,H\",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, },\n{\"mfc1\",    \"t,S\",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, },\n{\"mfc1\",    \"t,G\",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, },\n{\"mfhc1\",   \"t,S\",      0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, },\n{\"mfhc1\",   \"t,G\",      0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, },\n/* mfc2 is at the bottom of the table.  */\n/* mfhc2 is at the bottom of the table.  */\n/* mfc3 is at the bottom of the table.  */\n{\"mfdr\",    \"t,G\",      0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, },\n{\"mfhi\",    \"d\",        0x00000010, 0xffff07ff, WR_d|RD_HI, },\n{\"mfhi\",    \"d,9\",      0x00000010, 0xff9f07ff, WR_d|RD_HI, },\n{\"mflo\",    \"d\",        0x00000012, 0xffff07ff, WR_d|RD_LO, },\n{\"mflo\",    \"d,9\",      0x00000012, 0xff9f07ff, WR_d|RD_LO, },\n{\"mflhxu\",  \"d\",        0x00000052, 0xffff07ff, WR_d|MOD_HILO, },\n{\"mfcr\",    \"t,s\",      0x70000018, 0xfc00ffff, WR_t, },\n{\"min.ob\",  \"X,Y,Q\",    0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"min.ob\",  \"D,S,T\",    0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"min.ob\",  \"D,S,T[e]\", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, },\n{\"min.ob\",  \"D,S,k\",    0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"min.qh\",  \"X,Y,Q\",    0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"mov.d\",   \"D,S\",      0x46200006, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"mov.s\",   \"D,S\",      0x46000006, 0xffff003f, WR_D|RD_S|FP_S, },\n{\"mov.ps\",  \"D,S\",      0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"mov.ps\",  \"D,S\",      0x45600006, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"movf\",    \"d,s,N\",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, },\n{\"movf.d\",  \"D,S,N\",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, },\n{\"movf.l\",  \"D,S,N\",    0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, },\n{\"movf.l\",  \"X,Y,N\",    0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, },\n{\"movf.s\",  \"D,S,N\",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, },\n{\"movf.ps\", \"D,S,N\",    0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, },\n{\"movn\",    \"d,v,t\",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"movnz\",   \"d,v,t\",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"ffc\",     \"d,v\",      0x0000000b, 0xfc1f07ff, WR_d|RD_s, },\n{\"movn.d\",  \"D,S,t\",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, },\n{\"movn.l\",  \"D,S,t\",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, },\n{\"movn.l\",  \"X,Y,t\",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, },\n{\"movn.s\",  \"D,S,t\",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, },\n{\"movn.ps\", \"D,S,t\",    0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, },\n{\"movt\",    \"d,s,N\",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, },\n{\"movt.d\",  \"D,S,N\",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, },\n{\"movt.l\",  \"D,S,N\",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, },\n{\"movt.l\",  \"X,Y,N\",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, },\n{\"movt.s\",  \"D,S,N\",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, },\n{\"movt.ps\", \"D,S,N\",    0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, },\n{\"movz\",    \"d,v,t\",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"ffs\",     \"d,v\",      0x0000000a, 0xfc1f07ff, WR_d|RD_s, },\n{\"movz.d\",  \"D,S,t\",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, },\n{\"movz.l\",  \"D,S,t\",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, },\n{\"movz.l\",  \"X,Y,t\",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, },\n{\"movz.s\",  \"D,S,t\",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, },\n{\"movz.ps\", \"D,S,t\",    0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, },\n{\"msac\",    \"d,s,t\",    0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"msacu\",   \"d,s,t\",    0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"msachi\",  \"d,s,t\",    0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"msachiu\", \"d,s,t\",    0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n/* move is at the top of the table.  */\n{\"msgn.qh\", \"X,Y,Q\",    0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"msgsnd\",  \"t\",        0,    (int) M_MSGSND,   INSN_MACRO, },\n{\"msgld\",   \"\",         0,    (int) M_MSGLD,    INSN_MACRO, },\n{\"msgld\",   \"t\",        0,    (int) M_MSGLD_T,  INSN_MACRO, },\n{\"msgwait\", \"\",         0,    (int) M_MSGWAIT,  INSN_MACRO, },\n{\"msgwait\", \"t\",        0,    (int) M_MSGWAIT_T,INSN_MACRO, },\n{\"msub.d\",  \"D,R,S,T\",  0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, },\n{\"msub.d\",  \"D,S,T\",    0x46200019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"msub.d\",  \"D,S,T\",    0x72200019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"msub.s\",  \"D,R,S,T\",  0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, },\n{\"msub.s\",  \"D,S,T\",    0x46000019, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, },\n{\"msub.s\",  \"D,S,T\",    0x72000019, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, },\n{\"msub.ps\", \"D,R,S,T\",  0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, },\n{\"msub.ps\", \"D,S,T\",    0x45600019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"msub.ps\", \"D,S,T\",    0x71600019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"msub\",    \"s,t\",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, },\n{\"msub\",    \"s,t\",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, },\n{\"msub\",    \"7,s,t\",    0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"msubu\",   \"s,t\",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, },\n{\"msubu\",   \"s,t\",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, },\n{\"msubu\",   \"7,s,t\",    0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"mtpc\",    \"t,P\",      0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, },\n{\"mtps\",    \"t,P\",      0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, },\n{\"mtc0\",    \"t,G\",      0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, },\n{\"mtc0\",    \"t,+D\",     0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, },\n{\"mtc0\",    \"t,G,H\",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, },\n{\"mtc1\",    \"t,S\",      0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, },\n{\"mtc1\",    \"t,G\",      0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, },\n{\"mthc1\",   \"t,S\",      0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, },\n{\"mthc1\",   \"t,G\",      0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, },\n/* mtc2 is at the bottom of the table.  */\n/* mthc2 is at the bottom of the table.  */\n/* mtc3 is at the bottom of the table.  */\n{\"mtdr\",    \"t,G\",      0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, },\n{\"mthi\",    \"s\",        0x00000011, 0xfc1fffff, RD_s|WR_HI, },\n{\"mthi\",    \"s,7\",      0x00000011, 0xfc1fe7ff, RD_s|WR_HI, },\n{\"mtlo\",    \"s\",        0x00000013, 0xfc1fffff, RD_s|WR_LO, },\n{\"mtlo\",    \"s,7\",      0x00000013, 0xfc1fe7ff, RD_s|WR_LO, },\n{\"mtlhx\",   \"s\",        0x00000053, 0xfc1fffff, RD_s|MOD_HILO, },\n{\"mtcr\",    \"t,s\",      0x70000019, 0xfc00ffff, RD_t, },\n{\"mtm0\",    \"s\",        0x70000008, 0xfc1fffff, RD_s, },\n{\"mtm1\",    \"s\",        0x7000000c, 0xfc1fffff, RD_s, },\n{\"mtm2\",    \"s\",        0x7000000d, 0xfc1fffff, RD_s, },\n{\"mtp0\",    \"s\",        0x70000009, 0xfc1fffff, RD_s, },\n{\"mtp1\",    \"s\",        0x7000000a, 0xfc1fffff, RD_s, },\n{\"mtp2\",    \"s\",        0x7000000b, 0xfc1fffff, RD_s, },\n{\"mttc0\",   \"t,G\",      0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, },\n{\"mttc0\",   \"t,+D\",     0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, },\n{\"mttc0\",   \"t,G,H\",    0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, },\n{\"mttc1\",   \"t,S\",      0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, },\n{\"mttc1\",   \"t,G\",      0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, },\n{\"mttc2\",   \"t,g\",      0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, },\n{\"mttacx\",  \"t\",        0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, },\n{\"mttacx\",  \"t,&\",      0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, },\n{\"mttdsp\",  \"t\",        0x41808021, 0xffe0ffff, TRAP|RD_t, },\n{\"mttgpr\",  \"t,d\",      0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, },\n{\"mtthc1\",  \"t,S\",      0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, },\n{\"mtthc1\",  \"t,G\",      0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, },\n{\"mtthc2\",  \"t,g\",      0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, },\n{\"mtthi\",   \"t\",        0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, },\n{\"mtthi\",   \"t,&\",      0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, },\n{\"mttlo\",   \"t\",        0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, },\n{\"mttlo\",   \"t,&\",      0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, },\n{\"mttr\",    \"t,d,!,H,$\", 0x41800000, 0xffe007c8, TRAP|RD_t, },\n{\"mul.d\",   \"D,V,T\",    0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"mul.s\",   \"D,V,T\",    0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, },\n{\"mul.ob\",  \"X,Y,Q\",    0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"mul.ob\",  \"D,S,T\",    0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"mul.ob\",  \"D,S,T[e]\", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, },\n{\"mul.ob\",  \"D,S,k\",    0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"mul.ps\",  \"D,V,T\",    0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"mul.ps\",  \"D,V,T\",    0x45600002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"mul.qh\",  \"X,Y,Q\",    0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"mul\",     \"d,v,t\",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, },\n{\"mul\",     \"d,s,t\",    0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"mul\",     \"d,v,t\",    0,    (int) M_MUL,      INSN_MACRO, },\n{\"mul\",     \"d,v,I\",    0,    (int) M_MUL_I,    INSN_MACRO, },\n{\"mula.ob\", \"Y,Q\",      0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC, },\n{\"mula.ob\", \"S,T\",      0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, },\n{\"mula.ob\", \"S,T[e]\",   0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, },\n{\"mula.ob\", \"S,k\",      0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, },\n{\"mula.qh\", \"Y,Q\",      0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC, },\n{\"mulhi\",   \"d,s,t\",    0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"mulhiu\",  \"d,s,t\",    0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"mull.ob\", \"Y,Q\",      0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC, },\n{\"mull.ob\", \"S,T\",      0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, },\n{\"mull.ob\", \"S,T[e]\",   0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, },\n{\"mull.ob\", \"S,k\",      0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, },\n{\"mull.qh\", \"Y,Q\",      0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC, },\n{\"mulo\",    \"d,v,t\",    0,    (int) M_MULO,     INSN_MACRO, },\n{\"mulo\",    \"d,v,I\",    0,    (int) M_MULO_I,   INSN_MACRO, },\n{\"mulou\",   \"d,v,t\",    0,    (int) M_MULOU,    INSN_MACRO, },\n{\"mulou\",   \"d,v,I\",    0,    (int) M_MULOU_I,  INSN_MACRO, },\n{\"mulr.ps\", \"D,S,T\",    0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"muls\",    \"d,s,t\",    0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"mulsu\",   \"d,s,t\",    0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"mulshi\",  \"d,s,t\",    0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"mulshiu\", \"d,s,t\",    0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"muls.ob\", \"Y,Q\",      0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC, },\n{\"muls.ob\", \"S,T\",      0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, },\n{\"muls.ob\", \"S,T[e]\",   0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, },\n{\"muls.ob\", \"S,k\",      0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, },\n{\"muls.qh\", \"Y,Q\",      0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC, },\n{\"mulsl.ob\", \"Y,Q\",     0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC, },\n{\"mulsl.ob\", \"S,T\",     0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, },\n{\"mulsl.ob\", \"S,T[e]\",  0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, },\n{\"mulsl.ob\", \"S,k\",     0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, },\n{\"mulsl.qh\", \"Y,Q\",     0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC, },\n{\"mult\",    \"s,t\",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, },\n{\"mult\",    \"7,s,t\",    0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, },\n{\"mult\",    \"d,s,t\",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, },\n{\"multp\",   \"s,t\",      0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, },\n{\"multu\",   \"s,t\",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, },\n{\"multu\",   \"7,s,t\",    0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, },\n{\"multu\",   \"d,s,t\",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, },\n{\"mulu\",    \"d,s,t\",    0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, },\n{\"neg\",     \"d,w\",      0x00000022, 0xffe007ff, WR_d|RD_t, }, /* sub 0 */\n{\"negu\",    \"d,w\",      0x00000023, 0xffe007ff, WR_d|RD_t, }, /* subu 0 */\n{\"neg.d\",   \"D,V\",      0x46200007, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"neg.s\",   \"D,V\",      0x46000007, 0xffff003f, WR_D|RD_S|FP_S, },\n{\"neg.ps\",  \"D,V\",      0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"neg.ps\",  \"D,V\",      0x45600007, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"nmadd.d\", \"D,R,S,T\",  0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, },\n{\"nmadd.d\", \"D,S,T\",    0x4620001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"nmadd.d\", \"D,S,T\",    0x7220001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"nmadd.s\", \"D,R,S,T\",  0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, },\n{\"nmadd.s\", \"D,S,T\",    0x4600001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, },\n{\"nmadd.s\", \"D,S,T\",    0x7200001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, },\n{\"nmadd.ps\",\"D,R,S,T\",  0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, },\n{\"nmadd.ps\",\"D,S,T\",    0x4560001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"nmadd.ps\",\"D,S,T\",    0x7160001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"nmsub.d\", \"D,R,S,T\",  0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, },\n{\"nmsub.d\", \"D,S,T\",    0x4620001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"nmsub.d\", \"D,S,T\",    0x7220001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"nmsub.s\", \"D,R,S,T\",  0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, },\n{\"nmsub.s\", \"D,S,T\",    0x4600001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, },\n{\"nmsub.s\", \"D,S,T\",    0x7200001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, },\n{\"nmsub.ps\",\"D,R,S,T\",  0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, },\n{\"nmsub.ps\",\"D,S,T\",    0x4560001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"nmsub.ps\",\"D,S,T\",    0x7160001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n/* nop is at the start of the table.  */\n{\"nor\",     \"d,v,t\",    0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"nor\",     \"t,r,I\",    0,    (int) M_NOR_I,    INSN_MACRO, },\n{\"nor\",     \"D,S,T\",    0x47a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"nor\",     \"D,S,T\",    0x4ba00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"nor.ob\",  \"X,Y,Q\",    0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"nor.ob\",  \"D,S,T\",    0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"nor.ob\",  \"D,S,T[e]\", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, },\n{\"nor.ob\",  \"D,S,k\",    0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"nor.qh\",  \"X,Y,Q\",    0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"not\",     \"d,v\",      0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, },/*nor d,s,0*/\n{\"or\",      \"d,v,t\",    0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"or\",      \"t,r,I\",    0,    (int) M_OR_I,     INSN_MACRO, },\n{\"or\",      \"D,S,T\",    0x45a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"or\",      \"D,S,T\",    0x4b20000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"or.ob\",   \"X,Y,Q\",    0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"or.ob\",   \"D,S,T\",    0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"or.ob\",   \"D,S,T[e]\", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, },\n{\"or.ob\",   \"D,S,k\",    0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"or.qh\",   \"X,Y,Q\",    0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"ori\",     \"t,r,i\",    0x34000000, 0xfc000000, WR_t|RD_s, },\n{\"pabsdiff.ob\", \"X,Y,Q\",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"pabsdiffc.ob\", \"Y,Q\", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC, },\n{\"pavg.ob\", \"X,Y,Q\",    0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"pickf.ob\", \"X,Y,Q\",   0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"pickf.ob\", \"D,S,T\",   0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"pickf.ob\", \"D,S,T[e]\",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, },\n{\"pickf.ob\", \"D,S,k\",   0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"pickf.qh\", \"X,Y,Q\",   0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"pickt.ob\", \"X,Y,Q\",   0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"pickt.ob\", \"D,S,T\",   0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"pickt.ob\", \"D,S,T[e]\",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, },\n{\"pickt.ob\", \"D,S,k\",   0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"pickt.qh\", \"X,Y,Q\",   0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"pll.ps\",  \"D,V,T\",    0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"plu.ps\",  \"D,V,T\",    0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"pop\",     \"d,v\",      0x7000002c, 0xfc1f07ff, WR_d|RD_s, },\n  /* pref and prefx are at the start of the table.  */\n{\"pul.ps\",  \"D,V,T\",    0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"puu.ps\",  \"D,V,T\",    0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"pperm\",   \"s,t\",      0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t, },\n{\"rach.ob\", \"X\",        0x7a00003f, 0xfffff83f, WR_D|FP_D,              RD_MACC, },\n{\"rach.ob\", \"D\",        0x4a00003f, 0xfffff83f, WR_D, },\n{\"rach.qh\", \"X\",        0x7a20003f, 0xfffff83f, WR_D|FP_D,              RD_MACC, },\n{\"racl.ob\", \"X\",        0x7800003f, 0xfffff83f, WR_D|FP_D,              RD_MACC, },\n{\"racl.ob\", \"D\",        0x4800003f, 0xfffff83f, WR_D, },\n{\"racl.qh\", \"X\",        0x7820003f, 0xfffff83f, WR_D|FP_D,              RD_MACC, },\n{\"racm.ob\", \"X\",        0x7900003f, 0xfffff83f, WR_D|FP_D,              RD_MACC, },\n{\"racm.ob\", \"D\",        0x4900003f, 0xfffff83f, WR_D, },\n{\"racm.qh\", \"X\",        0x7920003f, 0xfffff83f, WR_D|FP_D,              RD_MACC, },\n{\"recip.d\", \"D,S\",      0x46200015, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"recip.ps\",\"D,S\",      0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"recip.s\", \"D,S\",      0x46000015, 0xffff003f, WR_D|RD_S|FP_S, },\n{\"recip1.d\",  \"D,S\",    0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"recip1.ps\", \"D,S\",    0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, },\n{\"recip1.s\",  \"D,S\",    0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, },\n{\"recip2.d\",  \"D,S,T\",  0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"recip2.ps\", \"D,S,T\",  0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, },\n{\"recip2.s\",  \"D,S,T\",  0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, },\n{\"rem\",     \"z,s,t\",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, },\n{\"rem\",     \"d,v,t\",    0,    (int) M_REM_3,    INSN_MACRO, },\n{\"rem\",     \"d,v,I\",    0,    (int) M_REM_3I,   INSN_MACRO, },\n{\"remu\",    \"z,s,t\",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, },\n{\"remu\",    \"d,v,t\",    0,    (int) M_REMU_3,   INSN_MACRO, },\n{\"remu\",    \"d,v,I\",    0,    (int) M_REMU_3I,  INSN_MACRO, },\n{\"rdhwr\",   \"t,K\",      0x7c00003b, 0xffe007ff, WR_t, },\n{\"rdpgpr\",  \"d,w\",      0x41400000, 0xffe007ff, WR_d, },\n{\"rfe\",     \"\",         0x42000010, 0xffffffff, 0, },\n{\"rnas.qh\", \"X,Q\",      0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC, },\n{\"rnau.ob\", \"X,Q\",      0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC, },\n{\"rnau.qh\", \"X,Q\",      0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC, },\n{\"rnes.qh\", \"X,Q\",      0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC, },\n{\"rneu.ob\", \"X,Q\",      0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC, },\n{\"rneu.qh\", \"X,Q\",      0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC, },\n{\"rol\",     \"d,v,t\",    0,    (int) M_ROL,      INSN_MACRO, },\n{\"rol\",     \"d,v,I\",    0,    (int) M_ROL_I,    INSN_MACRO, },\n{\"ror\",     \"d,v,t\",    0,    (int) M_ROR,      INSN_MACRO, },\n{\"ror\",     \"d,v,I\",    0,    (int) M_ROR_I,    INSN_MACRO, },\n{\"ror\",     \"d,w,<\",    0x00200002, 0xffe0003f, WR_d|RD_t, },\n{\"rorv\",    \"d,t,s\",    0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, },\n{\"rotl\",    \"d,v,t\",    0,    (int) M_ROL,      INSN_MACRO, },\n{\"rotl\",    \"d,v,I\",    0,    (int) M_ROL_I,    INSN_MACRO, },\n{\"ror\",     \"d,v,t\",    0,    (int) M_ROR,      INSN_MACRO, },\n{\"ror\",     \"d,v,I\",    0,    (int) M_ROR_I,    INSN_MACRO, },\n{\"rorv\",    \"d,t,s\",    0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, },\n{\"round.l.d\", \"D,S\",    0x46200008, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"round.l.s\", \"D,S\",    0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, },\n{\"round.w.d\", \"D,S\",    0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, },\n{\"round.w.s\", \"D,S\",    0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, },\n{\"rsqrt.d\", \"D,S\",      0x46200016, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"rsqrt.ps\",\"D,S\",      0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"rsqrt.s\", \"D,S\",      0x46000016, 0xffff003f, WR_D|RD_S|FP_S, },\n{\"rsqrt1.d\",  \"D,S\",    0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"rsqrt1.ps\", \"D,S\",    0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, },\n{\"rsqrt1.s\",  \"D,S\",    0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, },\n{\"rsqrt2.d\",  \"D,S,T\",  0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"rsqrt2.ps\", \"D,S,T\",  0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, },\n{\"rsqrt2.s\",  \"D,S,T\",  0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, },\n{\"rzs.qh\",  \"X,Q\",      0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC, },\n{\"rzu.ob\",  \"X,Q\",      0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC, },\n{\"rzu.ob\",  \"D,k\",      0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, },\n{\"rzu.qh\",  \"X,Q\",      0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC, },\n{\"sb\",      \"t,o(b)\",   0xa0000000, 0xfc000000, SM|RD_t|RD_b, },\n{\"sb\",      \"t,A(b)\",   0,    (int) M_SB_AB,    INSN_MACRO, },\n{\"sc\",      \"t,o(b)\",   0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, },\n{\"sc\",      \"t,A(b)\",   0,    (int) M_SC_AB,    INSN_MACRO, },\n{\"scd\",     \"t,o(b)\",   0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, },\n{\"scd\",     \"t,A(b)\",   0,    (int) M_SCD_AB,   INSN_MACRO, },\n/* The macro has to be first to handle o32 correctly.  */\n{\"sd\",      \"t,o(b)\",   0,    (int) M_SD_OB,    INSN_MACRO, },\n{\"sd\",      \"t,o(b)\",   0xfc000000, 0xfc000000, SM|RD_t|RD_b, },\n{\"sd\",      \"t,A(b)\",   0,    (int) M_SD_AB,    INSN_MACRO, },\n{\"sdbbp\",   \"\",         0x0000000e, 0xffffffff, TRAP, },\n{\"sdbbp\",   \"c\",        0x0000000e, 0xfc00ffff, TRAP, },\n{\"sdbbp\",   \"c,q\",      0x0000000e, 0xfc00003f, TRAP, },\n{\"sdbbp\",   \"\",         0x7000003f, 0xffffffff, TRAP, },\n{\"sdbbp\",   \"B\",        0x7000003f, 0xfc00003f, TRAP, },\n{\"sdc1\",    \"T,o(b)\",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, },\n{\"sdc1\",    \"E,o(b)\",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, },\n{\"sdc1\",    \"T,A(b)\",   0,    (int) M_SDC1_AB,  INSN_MACRO,             INSN2_M_FP_D, },\n{\"sdc1\",    \"E,A(b)\",   0,    (int) M_SDC1_AB,  INSN_MACRO,             INSN2_M_FP_D, },\n{\"sdc2\",    \"E,o(b)\",   0xf8000000, 0xfc000000, SM|RD_C2|RD_b, },\n{\"sdc2\",    \"E,A(b)\",   0,    (int) M_SDC2_AB,  INSN_MACRO, },\n{\"sdc3\",    \"E,o(b)\",   0xfc000000, 0xfc000000, SM|RD_C3|RD_b, },\n{\"sdc3\",    \"E,A(b)\",   0,    (int) M_SDC3_AB,  INSN_MACRO, },\n{\"s.d\",     \"T,o(b)\",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, },\n{\"s.d\",     \"T,o(b)\",   0,    (int) M_S_DOB,    INSN_MACRO,             INSN2_M_FP_D, },\n{\"s.d\",     \"T,A(b)\",   0,    (int) M_S_DAB,    INSN_MACRO,             INSN2_M_FP_D, },\n{\"sdl\",     \"t,o(b)\",   0xb0000000, 0xfc000000, SM|RD_t|RD_b, },\n{\"sdl\",     \"t,A(b)\",   0,    (int) M_SDL_AB,   INSN_MACRO, },\n{\"sdr\",     \"t,o(b)\",   0xb4000000, 0xfc000000, SM|RD_t|RD_b, },\n{\"sdr\",     \"t,A(b)\",   0,    (int) M_SDR_AB,   INSN_MACRO, },\n{\"sdxc1\",   \"S,t(b)\",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, },\n{\"seb\",     \"d,w\",      0x7c000420, 0xffe007ff, WR_d|RD_t, },\n{\"seh\",     \"d,w\",      0x7c000620, 0xffe007ff, WR_d|RD_t, },\n{\"selsl\",   \"d,v,t\",    0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"selsr\",   \"d,v,t\",    0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"seq\",     \"d,v,t\",    0x7000002a, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"seq\",     \"d,v,t\",    0,    (int) M_SEQ,      INSN_MACRO, },\n{\"seq\",     \"d,v,I\",    0,    (int) M_SEQ_I,    INSN_MACRO, },\n{\"seq\",     \"S,T\",      0x46a00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"seq\",     \"S,T\",      0x4ba0000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"seqi\",    \"t,r,+Q\",   0x7000002e, 0xfc00003f, WR_t|RD_s, },\n{\"sge\",     \"d,v,t\",    0,    (int) M_SGE,      INSN_MACRO, },\n{\"sge\",     \"d,v,I\",    0,    (int) M_SGE_I,    INSN_MACRO, },\n{\"sgeu\",    \"d,v,t\",    0,    (int) M_SGEU,     INSN_MACRO, },\n{\"sgeu\",    \"d,v,I\",    0,    (int) M_SGEU_I,   INSN_MACRO, },\n{\"sgt\",     \"d,v,t\",    0,    (int) M_SGT,      INSN_MACRO, },\n{\"sgt\",     \"d,v,I\",    0,    (int) M_SGT_I,    INSN_MACRO, },\n{\"sgtu\",    \"d,v,t\",    0,    (int) M_SGTU,     INSN_MACRO, },\n{\"sgtu\",    \"d,v,I\",    0,    (int) M_SGTU_I,   INSN_MACRO, },\n{\"sh\",      \"t,o(b)\",   0xa4000000, 0xfc000000, SM|RD_t|RD_b, },\n{\"sh\",      \"t,A(b)\",   0,    (int) M_SH_AB,    INSN_MACRO, },\n{\"shfl.bfla.qh\", \"X,Y,Z\", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"shfl.mixh.ob\", \"X,Y,Z\", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"shfl.mixh.ob\", \"D,S,T\", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"shfl.mixh.qh\", \"X,Y,Z\", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"shfl.mixl.ob\", \"X,Y,Z\", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"shfl.mixl.ob\", \"D,S,T\", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"shfl.mixl.qh\", \"X,Y,Z\", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"shfl.pach.ob\", \"X,Y,Z\", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"shfl.pach.ob\", \"D,S,T\", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"shfl.pach.qh\", \"X,Y,Z\", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"shfl.pacl.ob\", \"D,S,T\", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"shfl.repa.qh\", \"X,Y,Z\", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"shfl.repb.qh\", \"X,Y,Z\", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"shfl.upsl.ob\", \"X,Y,Z\", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"sle\",     \"d,v,t\",    0,    (int) M_SLE,      INSN_MACRO, },\n{\"sle\",     \"d,v,I\",    0,    (int) M_SLE_I,    INSN_MACRO, },\n{\"sle\",     \"S,T\",      0x46a0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"sle\",     \"S,T\",      0x4ba0000e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"sleu\",    \"d,v,t\",    0,    (int) M_SLEU,     INSN_MACRO, },\n{\"sleu\",    \"d,v,I\",    0,    (int) M_SLEU_I,   INSN_MACRO, },\n{\"sleu\",    \"S,T\",      0x4680003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"sleu\",    \"S,T\",      0x4b80000e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"sllv\",    \"d,t,s\",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, },\n{\"sll\",     \"d,w,s\",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, }, /* sllv */\n{\"sll\",     \"d,w,<\",    0x00000000, 0xffe0003f, WR_d|RD_t, },\n{\"sll\",     \"D,S,T\",    0x45800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"sll\",     \"D,S,T\",    0x4b00000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"sll.ob\",  \"X,Y,Q\",    0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"sll.ob\",  \"D,S,T[e]\", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, },\n{\"sll.ob\",  \"D,S,k\",    0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"sll.qh\",  \"X,Y,Q\",    0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"slt\",     \"d,v,t\",    0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"slt\",     \"d,v,I\",    0,    (int) M_SLT_I,    INSN_MACRO, },\n{\"slt\",     \"S,T\",      0x46a0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"slt\",     \"S,T\",      0x4ba0000d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"slti\",    \"t,r,j\",    0x28000000, 0xfc000000, WR_t|RD_s, },\n{\"sltiu\",   \"t,r,j\",    0x2c000000, 0xfc000000, WR_t|RD_s, },\n{\"sltu\",    \"d,v,t\",    0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"sltu\",    \"d,v,I\",    0,    (int) M_SLTU_I,   INSN_MACRO, },\n{\"sltu\",    \"S,T\",      0x4680003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"sltu\",    \"S,T\",      0x4b80000d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"sne\",     \"d,v,t\",    0x7000002b, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"sne\",     \"d,v,t\",    0,    (int) M_SNE,      INSN_MACRO, },\n{\"sne\",     \"d,v,I\",    0,    (int) M_SNE_I,    INSN_MACRO, },\n{\"snei\",    \"t,r,+Q\",   0x7000002f, 0xfc00003f, WR_t|RD_s, },\n{\"sqrt.d\",  \"D,S\",      0x46200004, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"sqrt.s\",  \"D,S\",      0x46000004, 0xffff003f, WR_D|RD_S|FP_S, },\n{\"sqrt.ps\", \"D,S\",      0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"srav\",    \"d,t,s\",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, },\n{\"sra\",     \"d,w,s\",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, }, /* srav */\n{\"sra\",     \"d,w,<\",    0x00000003, 0xffe0003f, WR_d|RD_t, },\n{\"sra\",     \"D,S,T\",    0x45c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"sra\",     \"D,S,T\",    0x4b40000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"sra.qh\",  \"X,Y,Q\",    0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"srlv\",    \"d,t,s\",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, },\n{\"srl\",     \"d,w,s\",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, }, /* srlv */\n{\"srl\",     \"d,w,<\",    0x00000002, 0xffe0003f, WR_d|RD_t, },\n{\"srl\",     \"D,S,T\",    0x45800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"srl\",     \"D,S,T\",    0x4b00000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"srl.ob\",  \"X,Y,Q\",    0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"srl.ob\",  \"D,S,T[e]\", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, },\n{\"srl.ob\",  \"D,S,k\",    0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"srl.qh\",  \"X,Y,Q\",    0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n/* ssnop is at the start of the table.  */\n{\"standby\", \"\",         0x42000021, 0xffffffff, 0, },\n{\"sub\",     \"d,v,t\",    0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"sub\",     \"d,v,I\",    0,    (int) M_SUB_I,    INSN_MACRO, },\n{\"sub\",     \"D,S,T\",    0x45c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, },\n{\"sub\",     \"D,S,T\",    0x4b40000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, },\n{\"sub.d\",   \"D,V,T\",    0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"sub.s\",   \"D,V,T\",    0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, },\n{\"sub.ob\",  \"X,Y,Q\",    0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"sub.ob\",  \"D,S,T\",    0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"sub.ob\",  \"D,S,T[e]\", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, },\n{\"sub.ob\",  \"D,S,k\",    0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"sub.ps\",  \"D,V,T\",    0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"sub.ps\",  \"D,V,T\",    0x45600001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, },\n{\"sub.qh\",  \"X,Y,Q\",    0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"suba.ob\", \"Y,Q\",      0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC, },\n{\"suba.qh\", \"Y,Q\",      0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC, },\n{\"subl.ob\", \"Y,Q\",      0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC, },\n{\"subl.qh\", \"Y,Q\",      0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC, },\n{\"subu\",    \"d,v,t\",    0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"subu\",    \"d,v,I\",    0,    (int) M_SUBU_I,   INSN_MACRO, },\n{\"subu\",    \"D,S,T\",    0x45800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, },\n{\"subu\",    \"D,S,T\",    0x4b00000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, },\n{\"suspend\", \"\",         0x42000022, 0xffffffff, 0, },\n{\"suxc1\",   \"S,t(b)\",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, },\n{\"sw\",      \"t,o(b)\",   0xac000000, 0xfc000000, SM|RD_t|RD_b, },\n{\"sw\",      \"t,A(b)\",   0,    (int) M_SW_AB,    INSN_MACRO, },\n{\"swapw\",   \"t,b\",      0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b, },\n{\"swapwu\",  \"t,b\",      0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b, },\n{\"swapd\",   \"t,b\",      0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b, },\n{\"swc0\",    \"E,o(b)\",   0xe0000000, 0xfc000000, SM|RD_C0|RD_b, },\n{\"swc0\",    \"E,A(b)\",   0,    (int) M_SWC0_AB,  INSN_MACRO, },\n{\"swc1\",    \"T,o(b)\",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, },\n{\"swc1\",    \"E,o(b)\",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, },\n{\"swc1\",    \"T,A(b)\",   0,    (int) M_SWC1_AB,  INSN_MACRO,             INSN2_M_FP_S, },\n{\"swc1\",    \"E,A(b)\",   0,    (int) M_SWC1_AB,  INSN_MACRO,             INSN2_M_FP_S, },\n{\"s.s\",     \"T,o(b)\",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, }, /* swc1 */\n{\"s.s\",     \"T,A(b)\",   0,    (int) M_SWC1_AB,  INSN_MACRO,             INSN2_M_FP_S, },\n{\"swc2\",    \"E,o(b)\",   0xe8000000, 0xfc000000, SM|RD_C2|RD_b, },\n{\"swc2\",    \"E,A(b)\",   0,    (int) M_SWC2_AB,  INSN_MACRO, },\n{\"swc3\",    \"E,o(b)\",   0xec000000, 0xfc000000, SM|RD_C3|RD_b, },\n{\"swc3\",    \"E,A(b)\",   0,    (int) M_SWC3_AB,  INSN_MACRO, },\n{\"swl\",     \"t,o(b)\",   0xa8000000, 0xfc000000, SM|RD_t|RD_b, },\n{\"swl\",     \"t,A(b)\",   0,    (int) M_SWL_AB,   INSN_MACRO, },\n{\"scache\",  \"t,o(b)\",   0xa8000000, 0xfc000000, RD_t|RD_b, }, /* same */\n{\"scache\",  \"t,A(b)\",   0,    (int) M_SWL_AB,   INSN_MACRO, }, /* as swl */\n{\"swr\",     \"t,o(b)\",   0xb8000000, 0xfc000000, SM|RD_t|RD_b, },\n{\"swr\",     \"t,A(b)\",   0,    (int) M_SWR_AB,   INSN_MACRO, },\n{\"invalidate\", \"t,o(b)\",0xb8000000, 0xfc000000, RD_t|RD_b, }, /* same */\n{\"invalidate\", \"t,A(b)\",0,    (int) M_SWR_AB,   INSN_MACRO, }, /* as swr */\n{\"swxc1\",   \"S,t(b)\",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, },\n{\"synciobdma\", \"\",      0x0000008f, 0xffffffff, INSN_SYNC, },\n{\"syncs\",   \"\",         0x0000018f, 0xffffffff, INSN_SYNC, },\n{\"syncw\",   \"\",         0x0000010f, 0xffffffff, INSN_SYNC, },\n{\"syncws\",  \"\",         0x0000014f, 0xffffffff, INSN_SYNC, },\n{\"sync_acquire\", \"\",    0x0000044f, 0xffffffff, INSN_SYNC, },\n{\"sync_mb\", \"\",         0x0000040f, 0xffffffff, INSN_SYNC, },\n{\"sync_release\", \"\",    0x0000048f, 0xffffffff, INSN_SYNC, },\n{\"sync_rmb\", \"\",        0x000004cf, 0xffffffff, INSN_SYNC, },\n{\"sync_wmb\", \"\",        0x0000010f, 0xffffffff, INSN_SYNC, },\n{\"sync\",    \"\",         0x0000000f, 0xffffffff, INSN_SYNC, },\n{\"sync\",    \"1\",        0x0000000f, 0xfffff83f, INSN_SYNC, },\n{\"sync.p\",  \"\",         0x0000040f, 0xffffffff, INSN_SYNC, },\n{\"sync.l\",  \"\",         0x0000000f, 0xffffffff, INSN_SYNC, },\n{\"synci\",   \"o(b)\",     0x041f0000, 0xfc1f0000, SM|RD_b, },\n{\"syscall\", \"\",         0x0000000c, 0xffffffff, TRAP, },\n{\"syscall\", \"B\",        0x0000000c, 0xfc00003f, TRAP, },\n{\"teqi\",    \"s,j\",      0x040c0000, 0xfc1f0000, RD_s|TRAP, },\n{\"teq\",     \"s,t\",      0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, },\n{\"teq\",     \"s,t,q\",    0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, },\n{\"teq\",     \"s,j\",      0x040c0000, 0xfc1f0000, RD_s|TRAP, }, /* teqi */\n{\"teq\",     \"s,I\",      0,    (int) M_TEQ_I,    INSN_MACRO, },\n{\"tgei\",    \"s,j\",      0x04080000, 0xfc1f0000, RD_s|TRAP, },\n{\"tge\",     \"s,t\",      0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, },\n{\"tge\",     \"s,t,q\",    0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, },\n{\"tge\",     \"s,j\",      0x04080000, 0xfc1f0000, RD_s|TRAP, }, /* tgei */\n{\"tge\",     \"s,I\",      0,    (int) M_TGE_I,    INSN_MACRO, },\n{\"tgeiu\",   \"s,j\",      0x04090000, 0xfc1f0000, RD_s|TRAP, },\n{\"tgeu\",    \"s,t\",      0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, },\n{\"tgeu\",    \"s,t,q\",    0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, },\n{\"tgeu\",    \"s,j\",      0x04090000, 0xfc1f0000, RD_s|TRAP, }, /* tgeiu */\n{\"tgeu\",    \"s,I\",      0,    (int) M_TGEU_I,   INSN_MACRO, },\n{\"tlbp\",    \"\",         0x42000008, 0xffffffff, INSN_TLB, },\n{\"tlbr\",    \"\",         0x42000001, 0xffffffff, INSN_TLB, },\n{\"tlbwi\",   \"\",         0x42000002, 0xffffffff, INSN_TLB, },\n{\"tlbwr\",   \"\",         0x42000006, 0xffffffff, INSN_TLB, },\n{\"tlti\",    \"s,j\",      0x040a0000, 0xfc1f0000, RD_s|TRAP, },\n{\"tlt\",     \"s,t\",      0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, },\n{\"tlt\",     \"s,t,q\",    0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, },\n{\"tlt\",     \"s,j\",      0x040a0000, 0xfc1f0000, RD_s|TRAP, }, /* tlti */\n{\"tlt\",     \"s,I\",      0,    (int) M_TLT_I,    INSN_MACRO, },\n{\"tltiu\",   \"s,j\",      0x040b0000, 0xfc1f0000, RD_s|TRAP, },\n{\"tltu\",    \"s,t\",      0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, },\n{\"tltu\",    \"s,t,q\",    0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, },\n{\"tltu\",    \"s,j\",      0x040b0000, 0xfc1f0000, RD_s|TRAP, }, /* tltiu */\n{\"tltu\",    \"s,I\",      0,    (int) M_TLTU_I,   INSN_MACRO, },\n{\"tnei\",    \"s,j\",      0x040e0000, 0xfc1f0000, RD_s|TRAP, },\n{\"tne\",     \"s,t\",      0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, },\n{\"tne\",     \"s,t,q\",    0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, },\n{\"tne\",     \"s,j\",      0x040e0000, 0xfc1f0000, RD_s|TRAP, }, /* tnei */\n{\"tne\",     \"s,I\",      0,    (int) M_TNE_I,    INSN_MACRO, },\n{\"trunc.l.d\", \"D,S\",    0x46200009, 0xffff003f, WR_D|RD_S|FP_D, },\n{\"trunc.l.s\", \"D,S\",    0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D, },\n{\"trunc.w.d\", \"D,S\",    0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, },\n{\"trunc.w.d\", \"D,S,x\",  0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, },\n{\"trunc.w.d\", \"D,S,t\",  0,    (int) M_TRUNCWD,  INSN_MACRO, INSN2_M_FP_S|INSN2_M_FP_D, },\n{\"trunc.w.s\", \"D,S\",    0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, },\n{\"trunc.w.s\", \"D,S,x\",  0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, },\n{\"trunc.w.s\", \"D,S,t\",  0,    (int) M_TRUNCWS,  INSN_MACRO,             INSN2_M_FP_S, },\n{\"uld\",     \"t,o(b)\",   0,    (int) M_ULD,      INSN_MACRO, },\n{\"uld\",     \"t,A(b)\",   0,    (int) M_ULD_A,    INSN_MACRO, },\n{\"ulh\",     \"t,o(b)\",   0,    (int) M_ULH,      INSN_MACRO, },\n{\"ulh\",     \"t,A(b)\",   0,    (int) M_ULH_A,    INSN_MACRO, },\n{\"ulhu\",    \"t,o(b)\",   0,    (int) M_ULHU,     INSN_MACRO, },\n{\"ulhu\",    \"t,A(b)\",   0,    (int) M_ULHU_A,   INSN_MACRO, },\n{\"ulw\",     \"t,o(b)\",   0,    (int) M_ULW,      INSN_MACRO, },\n{\"ulw\",     \"t,A(b)\",   0,    (int) M_ULW_A,    INSN_MACRO, },\n{\"usd\",     \"t,o(b)\",   0,    (int) M_USD,      INSN_MACRO, },\n{\"usd\",     \"t,A(b)\",   0,    (int) M_USD_A,    INSN_MACRO, },\n{\"ush\",     \"t,o(b)\",   0,    (int) M_USH,      INSN_MACRO, },\n{\"ush\",     \"t,A(b)\",   0,    (int) M_USH_A,    INSN_MACRO, },\n{\"usw\",     \"t,o(b)\",   0,    (int) M_USW,      INSN_MACRO, },\n{\"usw\",     \"t,A(b)\",   0,    (int) M_USW_A,    INSN_MACRO, },\n{\"v3mulu\",  \"d,v,t\",    0x70000011, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"vmm0\",    \"d,v,t\",    0x70000010, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"vmulu\",   \"d,v,t\",    0x7000000f, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"wach.ob\", \"Y\",        0x7a00003e, 0xffff07ff, RD_S|FP_D,              WR_MACC, },\n{\"wach.ob\", \"S\",        0x4a00003e, 0xffff07ff, RD_S, },\n{\"wach.qh\", \"Y\",        0x7a20003e, 0xffff07ff, RD_S|FP_D,              WR_MACC, },\n{\"wacl.ob\", \"Y,Z\",      0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC, },\n{\"wacl.ob\", \"S,T\",      0x4800003e, 0xffe007ff, RD_S|RD_T, },\n{\"wacl.qh\", \"Y,Z\",      0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC, },\n{\"wait\",    \"\",         0x42000020, 0xffffffff, TRAP, },\n{\"wait\",    \"J\",        0x42000020, 0xfe00003f, TRAP, },\n{\"waiti\",   \"\",         0x42000020, 0xffffffff, TRAP, },\n{\"wrpgpr\",  \"d,w\",      0x41c00000, 0xffe007ff, RD_t, },\n{\"wsbh\",    \"d,w\",      0x7c0000a0, 0xffe007ff, WR_d|RD_t, },\n{\"xor\",     \"d,v,t\",    0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"xor\",     \"t,r,I\",    0,    (int) M_XOR_I,    INSN_MACRO, },\n{\"xor\", \"D,S,T\",        0x47800002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D, },\n{\"xor\", \"D,S,T\",        0x4b800002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D, },\n{\"xor.ob\",  \"X,Y,Q\",    0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"xor.ob\",  \"D,S,T\",    0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"xor.ob\",  \"D,S,T[e]\", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, },\n{\"xor.ob\",  \"D,S,k\",    0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, },\n{\"xor.qh\",  \"X,Y,Q\",    0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, },\n{\"xori\",    \"t,r,i\",    0x38000000, 0xfc000000, WR_t|RD_s, },\n{\"yield\",   \"s\",        0x7c000009, 0xfc1fffff, TRAP|RD_s, },\n{\"yield\",   \"d,s\",      0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, },\n\n/* User Defined Instruction.  */\n{\"udi0\",     \"s,t,d,+1\",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi0\",     \"s,t,+2\",  0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi0\",     \"s,+3\",    0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi0\",     \"+4\",      0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi1\",     \"s,t,d,+1\",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi1\",     \"s,t,+2\",  0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi1\",     \"s,+3\",    0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi1\",     \"+4\",      0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi2\",     \"s,t,d,+1\",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi2\",     \"s,t,+2\",  0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi2\",     \"s,+3\",    0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi2\",     \"+4\",      0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi3\",     \"s,t,d,+1\",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi3\",     \"s,t,+2\",  0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi3\",     \"s,+3\",    0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi3\",     \"+4\",      0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi4\",     \"s,t,d,+1\",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi4\",     \"s,t,+2\",  0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi4\",     \"s,+3\",    0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi4\",     \"+4\",      0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi5\",     \"s,t,d,+1\",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi5\",     \"s,t,+2\",  0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi5\",     \"s,+3\",    0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi5\",     \"+4\",      0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi6\",     \"s,t,d,+1\",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi6\",     \"s,t,+2\",  0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi6\",     \"s,+3\",    0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi6\",     \"+4\",      0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi7\",     \"s,t,d,+1\",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi7\",     \"s,t,+2\",  0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi7\",     \"s,+3\",    0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi7\",     \"+4\",      0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi8\",     \"s,t,d,+1\",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi8\",     \"s,t,+2\",  0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi8\",     \"s,+3\",    0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi8\",     \"+4\",      0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi9\",     \"s,t,d,+1\",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi9\",      \"s,t,+2\", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi9\",     \"s,+3\",    0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi9\",     \"+4\",      0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi10\",    \"s,t,d,+1\",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi10\",    \"s,t,+2\",  0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi10\",    \"s,+3\",    0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi10\",    \"+4\",      0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi11\",    \"s,t,d,+1\",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi11\",    \"s,t,+2\",  0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi11\",    \"s,+3\",    0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi11\",    \"+4\",      0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi12\",    \"s,t,d,+1\",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi12\",    \"s,t,+2\",  0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi12\",    \"s,+3\",    0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi12\",    \"+4\",      0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi13\",    \"s,t,d,+1\",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi13\",    \"s,t,+2\",  0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi13\",    \"s,+3\",    0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi13\",    \"+4\",      0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi14\",    \"s,t,d,+1\",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi14\",    \"s,t,+2\",  0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi14\",    \"s,+3\",    0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi14\",    \"+4\",      0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi15\",    \"s,t,d,+1\",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi15\",    \"s,t,+2\",  0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi15\",    \"s,+3\",    0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, },\n{\"udi15\",    \"+4\",      0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, },\n\n/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format\n   instructions so they are here for the latters to take precedence.  */\n{\"bc2f\",    \"p\",        0x49000000, 0xffff0000, CBD|RD_CC, },\n{\"bc2f\",    \"N,p\",      0x49000000, 0xffe30000, CBD|RD_CC, },\n{\"bc2fl\",   \"p\",        0x49020000, 0xffff0000, CBL|RD_CC, },\n{\"bc2fl\",   \"N,p\",      0x49020000, 0xffe30000, CBL|RD_CC, },\n{\"bc2t\",    \"p\",        0x49010000, 0xffff0000, CBD|RD_CC, },\n{\"bc2t\",    \"N,p\",      0x49010000, 0xffe30000, CBD|RD_CC, },\n{\"bc2tl\",   \"p\",        0x49030000, 0xffff0000, CBL|RD_CC, },\n{\"bc2tl\",   \"N,p\",      0x49030000, 0xffe30000, CBL|RD_CC, },\n{\"cfc2\",    \"t,G\",      0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, },\n{\"ctc2\",    \"t,G\",      0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, },\n{\"dmfc2\",   \"t,i\",      0x48200000, 0xffe00000, LCD|WR_t|RD_C2, },\n{\"dmfc2\",   \"t,G\",      0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, },\n{\"dmfc2\",   \"t,G,H\",    0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, },\n{\"dmtc2\",   \"t,i\",      0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, },\n{\"dmtc2\",   \"t,G\",      0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, },\n{\"dmtc2\",   \"t,G,H\",    0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, },\n{\"mfc2\",    \"t,G\",      0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, },\n{\"mfc2\",    \"t,G,H\",    0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, },\n{\"mfhc2\",   \"t,G\",      0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, },\n{\"mfhc2\",   \"t,G,H\",    0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, },\n{\"mfhc2\",   \"t,i\",      0x48600000, 0xffe00000, LCD|WR_t|RD_C2, },\n{\"mtc2\",    \"t,G\",      0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, },\n{\"mtc2\",    \"t,G,H\",    0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, },\n{\"mthc2\",   \"t,G\",      0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, },\n{\"mthc2\",   \"t,G,H\",    0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, },\n{\"mthc2\",   \"t,i\",      0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, },\n\n/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X\n   instructions, so they are here for the latters to take precedence.  */\n{\"bc3f\",    \"p\",        0x4d000000, 0xffff0000, CBD|RD_CC, },\n{\"bc3fl\",   \"p\",        0x4d020000, 0xffff0000, CBL|RD_CC, },\n{\"bc3t\",    \"p\",        0x4d010000, 0xffff0000, CBD|RD_CC, },\n{\"bc3tl\",   \"p\",        0x4d030000, 0xffff0000, CBL|RD_CC, },\n{\"cfc3\",    \"t,G\",      0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, },\n{\"ctc3\",    \"t,G\",      0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, },\n{\"dmfc3\",   \"t,G\",      0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, },\n{\"dmtc3\",   \"t,G\",      0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, },\n{\"mfc3\",    \"t,G\",      0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, },\n{\"mfc3\",    \"t,G,H\",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, },\n{\"mtc3\",    \"t,G\",      0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, },\n{\"mtc3\",    \"t,G,H\",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, },\n\n  /* Conflicts with the 4650's \"mul\" instruction.  Nobody's using the\n     4010 any more, so move this insn out of the way.  If the object\n     format gave us more info, we could do this right.  */\n{\"addciu\",  \"t,r,j\",    0x70000000, 0xfc000000, WR_t|RD_s, },\n/* MIPS DSP ASE */\n{\"absq_s.ph\", \"d,t\",    0x7c000252, 0xffe007ff, WR_d|RD_t, },\n{\"absq_s.pw\", \"d,t\",    0x7c000456, 0xffe007ff, WR_d|RD_t, },\n{\"absq_s.qh\", \"d,t\",    0x7c000256, 0xffe007ff, WR_d|RD_t, },\n{\"absq_s.w\", \"d,t\",     0x7c000452, 0xffe007ff, WR_d|RD_t, },\n{\"addq.ph\", \"d,s,t\",    0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"addq.pw\", \"d,s,t\",    0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"addq.qh\", \"d,s,t\",    0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"addq_s.ph\", \"d,s,t\",  0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"addq_s.pw\", \"d,s,t\",  0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"addq_s.qh\", \"d,s,t\",  0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"addq_s.w\", \"d,s,t\",   0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"addsc\",   \"d,s,t\",    0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"addu.ob\", \"d,s,t\",    0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"addu.qb\", \"d,s,t\",    0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"addu_s.ob\", \"d,s,t\",  0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"addu_s.qb\", \"d,s,t\",  0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"addwc\",   \"d,s,t\",    0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"bitrev\",  \"d,t\",      0x7c0006d2, 0xffe007ff, WR_d|RD_t, },\n{\"bposge32\", \"p\",       0x041c0000, 0xffff0000, CBD, },\n{\"bposge64\", \"p\",       0x041d0000, 0xffff0000, CBD, },\n{\"cmp.eq.ph\", \"s,t\",    0x7c000211, 0xfc00ffff, RD_s|RD_t, },\n{\"cmp.eq.pw\", \"s,t\",    0x7c000415, 0xfc00ffff, RD_s|RD_t, },\n{\"cmp.eq.qh\", \"s,t\",    0x7c000215, 0xfc00ffff, RD_s|RD_t, },\n{\"cmpgu.eq.ob\", \"d,s,t\", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"cmpgu.eq.qb\", \"d,s,t\", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"cmpgu.le.ob\", \"d,s,t\", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"cmpgu.le.qb\", \"d,s,t\", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"cmpgu.lt.ob\", \"d,s,t\", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"cmpgu.lt.qb\", \"d,s,t\", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"cmp.le.ph\", \"s,t\",    0x7c000291, 0xfc00ffff, RD_s|RD_t, },\n{\"cmp.le.pw\", \"s,t\",    0x7c000495, 0xfc00ffff, RD_s|RD_t, },\n{\"cmp.le.qh\", \"s,t\",    0x7c000295, 0xfc00ffff, RD_s|RD_t, },\n{\"cmp.lt.ph\", \"s,t\",    0x7c000251, 0xfc00ffff, RD_s|RD_t, },\n{\"cmp.lt.pw\", \"s,t\",    0x7c000455, 0xfc00ffff, RD_s|RD_t, },\n{\"cmp.lt.qh\", \"s,t\",    0x7c000255, 0xfc00ffff, RD_s|RD_t, },\n{\"cmpu.eq.ob\", \"s,t\",   0x7c000015, 0xfc00ffff, RD_s|RD_t, },\n{\"cmpu.eq.qb\", \"s,t\",   0x7c000011, 0xfc00ffff, RD_s|RD_t, },\n{\"cmpu.le.ob\", \"s,t\",   0x7c000095, 0xfc00ffff, RD_s|RD_t, },\n{\"cmpu.le.qb\", \"s,t\",   0x7c000091, 0xfc00ffff, RD_s|RD_t, },\n{\"cmpu.lt.ob\", \"s,t\",   0x7c000055, 0xfc00ffff, RD_s|RD_t, },\n{\"cmpu.lt.qb\", \"s,t\",   0x7c000051, 0xfc00ffff, RD_s|RD_t, },\n{\"dextpdp\", \"t,7,6\",    0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, },\n{\"dextpdpv\", \"t,7,s\",   0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, },\n{\"dextp\",   \"t,7,6\",    0x7c0000bc, 0xfc00e7ff, WR_t|RD_a, },\n{\"dextpv\",  \"t,7,s\",    0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s, },\n{\"dextr.l\", \"t,7,6\",    0x7c00043c, 0xfc00e7ff, WR_t|RD_a, },\n{\"dextr_r.l\", \"t,7,6\",  0x7c00053c, 0xfc00e7ff, WR_t|RD_a, },\n{\"dextr_rs.l\", \"t,7,6\", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a, },\n{\"dextr_rs.w\", \"t,7,6\", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a, },\n{\"dextr_r.w\", \"t,7,6\",  0x7c00013c, 0xfc00e7ff, WR_t|RD_a, },\n{\"dextr_s.h\", \"t,7,6\",  0x7c0003bc, 0xfc00e7ff, WR_t|RD_a, },\n{\"dextrv.l\", \"t,7,s\",   0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s, },\n{\"dextrv_r.l\", \"t,7,s\", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s, },\n{\"dextrv_rs.l\", \"t,7,s\", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s, },\n{\"dextrv_rs.w\", \"t,7,s\", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s, },\n{\"dextrv_r.w\", \"t,7,s\", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s, },\n{\"dextrv_s.h\", \"t,7,s\", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s, },\n{\"dextrv.w\", \"t,7,s\",   0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s, },\n{\"dextr.w\", \"t,7,6\",    0x7c00003c, 0xfc00e7ff, WR_t|RD_a, },\n{\"dinsv\",   \"t,s\",      0x7c00000d, 0xfc00ffff, WR_t|RD_s, },\n{\"dmadd\",   \"7,s,t\",    0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dmaddu\",  \"7,s,t\",    0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dmsub\",   \"7,s,t\",    0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dmsubu\",  \"7,s,t\",    0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dmthlip\", \"s,7\",      0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, },\n{\"dpaq_sa.l.pw\", \"7,s,t\", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dpaq_sa.l.w\", \"7,s,t\", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dpaq_s.w.ph\", \"7,s,t\", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dpaq_s.w.qh\", \"7,s,t\", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dpau.h.obl\", \"7,s,t\", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dpau.h.obr\", \"7,s,t\", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dpau.h.qbl\", \"7,s,t\", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dpau.h.qbr\", \"7,s,t\", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dpsq_sa.l.pw\", \"7,s,t\", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dpsq_sa.l.w\", \"7,s,t\", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dpsq_s.w.ph\", \"7,s,t\", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dpsq_s.w.qh\", \"7,s,t\", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dpsu.h.obl\", \"7,s,t\", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dpsu.h.obr\", \"7,s,t\", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dpsu.h.qbl\", \"7,s,t\", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dpsu.h.qbr\", \"7,s,t\", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dshilo\",  \"7,:\",      0x7c0006bc, 0xfc07e7ff, MOD_a, },\n{\"dshilov\", \"7,s\",      0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s, },\n{\"extpdp\",  \"t,7,6\",    0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, },\n{\"extpdpv\", \"t,7,s\",    0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, },\n{\"extp\",    \"t,7,6\",    0x7c0000b8, 0xfc00e7ff, WR_t|RD_a, },\n{\"extpv\",   \"t,7,s\",    0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s, },\n{\"extr_rs.w\", \"t,7,6\",  0x7c0001b8, 0xfc00e7ff, WR_t|RD_a, },\n{\"extr_r.w\", \"t,7,6\",   0x7c000138, 0xfc00e7ff, WR_t|RD_a, },\n{\"extr_s.h\", \"t,7,6\",   0x7c0003b8, 0xfc00e7ff, WR_t|RD_a, },\n{\"extrv_rs.w\", \"t,7,s\", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s, },\n{\"extrv_r.w\", \"t,7,s\",  0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s, },\n{\"extrv_s.h\", \"t,7,s\",  0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s, },\n{\"extrv.w\", \"t,7,s\",    0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s, },\n{\"extr.w\",  \"t,7,6\",    0x7c000038, 0xfc00e7ff, WR_t|RD_a, },\n{\"insv\",    \"t,s\",      0x7c00000c, 0xfc00ffff, WR_t|RD_s, },\n{\"lbux\",    \"d,t(b)\",   0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, },\n{\"ldx\",     \"d,t(b)\",   0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, },\n{\"lhx\",     \"d,t(b)\",   0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, },\n{\"lwx\",     \"d,t(b)\",   0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, },\n{\"maq_sa.w.phl\", \"7,s,t\", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"maq_sa.w.phr\", \"7,s,t\", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"maq_sa.w.qhll\", \"7,s,t\", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"maq_sa.w.qhlr\", \"7,s,t\", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"maq_sa.w.qhrl\", \"7,s,t\", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"maq_sa.w.qhrr\", \"7,s,t\", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"maq_s.l.pwl\", \"7,s,t\", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"maq_s.l.pwr\", \"7,s,t\", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"maq_s.w.phl\", \"7,s,t\", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"maq_s.w.phr\", \"7,s,t\", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"maq_s.w.qhll\", \"7,s,t\", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"maq_s.w.qhlr\", \"7,s,t\", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"maq_s.w.qhrl\", \"7,s,t\", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"maq_s.w.qhrr\", \"7,s,t\", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"modsub\",  \"d,s,t\",    0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"mthlip\",  \"s,7\",      0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, },\n{\"muleq_s.pw.qhl\", \"d,s,t\", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, },\n{\"muleq_s.pw.qhr\", \"d,s,t\", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, },\n{\"muleq_s.w.phl\", \"d,s,t\", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, },\n{\"muleq_s.w.phr\", \"d,s,t\", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, },\n{\"muleu_s.ph.qbl\", \"d,s,t\", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, },\n{\"muleu_s.ph.qbr\", \"d,s,t\", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, },\n{\"muleu_s.qh.obl\", \"d,s,t\", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, },\n{\"muleu_s.qh.obr\", \"d,s,t\", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, },\n{\"mulq_rs.ph\", \"d,s,t\", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, },\n{\"mulq_rs.qh\", \"d,s,t\", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, },\n{\"mulsaq_s.l.pw\", \"7,s,t\", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"mulsaq_s.w.ph\", \"7,s,t\", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"mulsaq_s.w.qh\", \"7,s,t\", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"packrl.ph\", \"d,s,t\",  0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"packrl.pw\", \"d,s,t\",  0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"pick.ob\", \"d,s,t\",    0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"pick.ph\", \"d,s,t\",    0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"pick.pw\", \"d,s,t\",    0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"pick.qb\", \"d,s,t\",    0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"pick.qh\", \"d,s,t\",    0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"preceq.pw.qhla\", \"d,t\", 0x7c000396, 0xffe007ff, WR_d|RD_t, },\n{\"preceq.pw.qhl\", \"d,t\", 0x7c000316, 0xffe007ff, WR_d|RD_t, },\n{\"preceq.pw.qhra\", \"d,t\", 0x7c0003d6, 0xffe007ff, WR_d|RD_t, },\n{\"preceq.pw.qhr\", \"d,t\", 0x7c000356, 0xffe007ff, WR_d|RD_t, },\n{\"preceq.s.l.pwl\", \"d,t\", 0x7c000516, 0xffe007ff, WR_d|RD_t, },\n{\"preceq.s.l.pwr\", \"d,t\", 0x7c000556, 0xffe007ff, WR_d|RD_t, },\n{\"precequ.ph.qbla\", \"d,t\", 0x7c000192, 0xffe007ff, WR_d|RD_t, },\n{\"precequ.ph.qbl\", \"d,t\", 0x7c000112, 0xffe007ff, WR_d|RD_t, },\n{\"precequ.ph.qbra\", \"d,t\", 0x7c0001d2, 0xffe007ff, WR_d|RD_t, },\n{\"precequ.ph.qbr\", \"d,t\", 0x7c000152, 0xffe007ff, WR_d|RD_t, },\n{\"precequ.pw.qhla\", \"d,t\", 0x7c000196, 0xffe007ff, WR_d|RD_t, },\n{\"precequ.pw.qhl\", \"d,t\", 0x7c000116, 0xffe007ff, WR_d|RD_t, },\n{\"precequ.pw.qhra\", \"d,t\", 0x7c0001d6, 0xffe007ff, WR_d|RD_t, },\n{\"precequ.pw.qhr\", \"d,t\", 0x7c000156, 0xffe007ff, WR_d|RD_t, },\n{\"preceq.w.phl\", \"d,t\", 0x7c000312, 0xffe007ff, WR_d|RD_t, },\n{\"preceq.w.phr\", \"d,t\", 0x7c000352, 0xffe007ff, WR_d|RD_t, },\n{\"preceu.ph.qbla\", \"d,t\", 0x7c000792, 0xffe007ff, WR_d|RD_t, },\n{\"preceu.ph.qbl\", \"d,t\", 0x7c000712, 0xffe007ff, WR_d|RD_t, },\n{\"preceu.ph.qbra\", \"d,t\", 0x7c0007d2, 0xffe007ff, WR_d|RD_t, },\n{\"preceu.ph.qbr\", \"d,t\", 0x7c000752, 0xffe007ff, WR_d|RD_t, },\n{\"preceu.qh.obla\", \"d,t\", 0x7c000796, 0xffe007ff, WR_d|RD_t, },\n{\"preceu.qh.obl\", \"d,t\", 0x7c000716, 0xffe007ff, WR_d|RD_t, },\n{\"preceu.qh.obra\", \"d,t\", 0x7c0007d6, 0xffe007ff, WR_d|RD_t, },\n{\"preceu.qh.obr\", \"d,t\", 0x7c000756, 0xffe007ff, WR_d|RD_t, },\n{\"precrq.ob.qh\", \"d,s,t\", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"precrq.ph.w\", \"d,s,t\", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"precrq.pw.l\", \"d,s,t\", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"precrq.qb.ph\", \"d,s,t\", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"precrq.qh.pw\", \"d,s,t\", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"precrq_rs.ph.w\", \"d,s,t\", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"precrq_rs.qh.pw\", \"d,s,t\", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"precrqu_s.ob.qh\", \"d,s,t\", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"precrqu_s.qb.ph\", \"d,s,t\", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"raddu.l.ob\", \"d,s\",   0x7c000514, 0xfc1f07ff, WR_d|RD_s, },\n{\"raddu.w.qb\", \"d,s\",   0x7c000510, 0xfc1f07ff, WR_d|RD_s, },\n{\"rddsp\",   \"d\",        0x7fff04b8, 0xffff07ff, WR_d, },\n{\"rddsp\",   \"d,'\",      0x7c0004b8, 0xffc007ff, WR_d, },\n{\"repl.ob\", \"d,5\",      0x7c000096, 0xff0007ff, WR_d, },\n{\"repl.ph\", \"d,@\",      0x7c000292, 0xfc0007ff, WR_d, },\n{\"repl.pw\", \"d,@\",      0x7c000496, 0xfc0007ff, WR_d, },\n{\"repl.qb\", \"d,5\",      0x7c000092, 0xff0007ff, WR_d, },\n{\"repl.qh\", \"d,@\",      0x7c000296, 0xfc0007ff, WR_d, },\n{\"replv.ob\", \"d,t\",     0x7c0000d6, 0xffe007ff, WR_d|RD_t, },\n{\"replv.ph\", \"d,t\",     0x7c0002d2, 0xffe007ff, WR_d|RD_t, },\n{\"replv.pw\", \"d,t\",     0x7c0004d6, 0xffe007ff, WR_d|RD_t, },\n{\"replv.qb\", \"d,t\",     0x7c0000d2, 0xffe007ff, WR_d|RD_t, },\n{\"replv.qh\", \"d,t\",     0x7c0002d6, 0xffe007ff, WR_d|RD_t, },\n{\"shilo\",   \"7,0\",      0x7c0006b8, 0xfc0fe7ff, MOD_a, },\n{\"shilov\",  \"7,s\",      0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s, },\n{\"shll.ob\", \"d,t,3\",    0x7c000017, 0xff0007ff, WR_d|RD_t, },\n{\"shll.ph\", \"d,t,4\",    0x7c000213, 0xfe0007ff, WR_d|RD_t, },\n{\"shll.pw\", \"d,t,6\",    0x7c000417, 0xfc0007ff, WR_d|RD_t, },\n{\"shll.qb\", \"d,t,3\",    0x7c000013, 0xff0007ff, WR_d|RD_t, },\n{\"shll.qh\", \"d,t,4\",    0x7c000217, 0xfe0007ff, WR_d|RD_t, },\n{\"shll_s.ph\", \"d,t,4\",  0x7c000313, 0xfe0007ff, WR_d|RD_t, },\n{\"shll_s.pw\", \"d,t,6\",  0x7c000517, 0xfc0007ff, WR_d|RD_t, },\n{\"shll_s.qh\", \"d,t,4\",  0x7c000317, 0xfe0007ff, WR_d|RD_t, },\n{\"shll_s.w\", \"d,t,6\",   0x7c000513, 0xfc0007ff, WR_d|RD_t, },\n{\"shllv.ob\", \"d,t,s\",   0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"shllv.ph\", \"d,t,s\",   0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"shllv.pw\", \"d,t,s\",   0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"shllv.qb\", \"d,t,s\",   0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"shllv.qh\", \"d,t,s\",   0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"shllv_s.ph\", \"d,t,s\", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"shllv_s.pw\", \"d,t,s\", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"shllv_s.qh\", \"d,t,s\", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"shllv_s.w\", \"d,t,s\",  0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"shra.ph\", \"d,t,4\",    0x7c000253, 0xfe0007ff, WR_d|RD_t, },\n{\"shra.pw\", \"d,t,6\",    0x7c000457, 0xfc0007ff, WR_d|RD_t, },\n{\"shra.qh\", \"d,t,4\",    0x7c000257, 0xfe0007ff, WR_d|RD_t, },\n{\"shra_r.ph\", \"d,t,4\",  0x7c000353, 0xfe0007ff, WR_d|RD_t, },\n{\"shra_r.pw\", \"d,t,6\",  0x7c000557, 0xfc0007ff, WR_d|RD_t, },\n{\"shra_r.qh\", \"d,t,4\",  0x7c000357, 0xfe0007ff, WR_d|RD_t, },\n{\"shra_r.w\", \"d,t,6\",   0x7c000553, 0xfc0007ff, WR_d|RD_t, },\n{\"shrav.ph\", \"d,t,s\",   0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"shrav.pw\", \"d,t,s\",   0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"shrav.qh\", \"d,t,s\",   0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"shrav_r.ph\", \"d,t,s\", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"shrav_r.pw\", \"d,t,s\", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"shrav_r.qh\", \"d,t,s\", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"shrav_r.w\", \"d,t,s\",  0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"shrl.ob\", \"d,t,3\",    0x7c000057, 0xff0007ff, WR_d|RD_t, },\n{\"shrl.qb\", \"d,t,3\",    0x7c000053, 0xff0007ff, WR_d|RD_t, },\n{\"shrlv.ob\", \"d,t,s\",   0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"shrlv.qb\", \"d,t,s\",   0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"subq.ph\", \"d,s,t\",    0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"subq.pw\", \"d,s,t\",    0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"subq.qh\", \"d,s,t\",    0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"subq_s.ph\", \"d,s,t\",  0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"subq_s.pw\", \"d,s,t\",  0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"subq_s.qh\", \"d,s,t\",  0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"subq_s.w\", \"d,s,t\",   0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"subu.ob\", \"d,s,t\",    0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"subu.qb\", \"d,s,t\",    0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"subu_s.ob\", \"d,s,t\",  0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"subu_s.qb\", \"d,s,t\",  0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"wrdsp\",   \"s\",        0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, },\n{\"wrdsp\",   \"s,8\",      0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, },\n/* MIPS DSP ASE Rev2 */\n{\"absq_s.qb\", \"d,t\",    0x7c000052, 0xffe007ff, WR_d|RD_t, },\n{\"addu.ph\", \"d,s,t\",    0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"addu_s.ph\", \"d,s,t\",  0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"adduh.qb\", \"d,s,t\",   0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"adduh_r.qb\", \"d,s,t\", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"append\",  \"t,s,h\",    0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s, },\n{\"balign\",  \"t,s,I\",    0,    (int) M_BALIGN,   INSN_MACRO, },\n{\"balign\",  \"t,s,2\",    0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s, },\n{\"cmpgdu.eq.qb\", \"d,s,t\", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"cmpgdu.lt.qb\", \"d,s,t\", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"cmpgdu.le.qb\", \"d,s,t\", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"dpa.w.ph\", \"7,s,t\",   0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dps.w.ph\", \"7,s,t\",   0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"mul.ph\",  \"d,s,t\",    0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, },\n{\"mul_s.ph\", \"d,s,t\",   0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, },\n{\"mulq_rs.w\", \"d,s,t\",  0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, },\n{\"mulq_s.ph\", \"d,s,t\",  0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, },\n{\"mulq_s.w\", \"d,s,t\",   0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, },\n{\"mulsa.w.ph\", \"7,s,t\", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"precr.qb.ph\", \"d,s,t\", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"precr_sra.ph.w\", \"t,s,h\", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s, },\n{\"precr_sra_r.ph.w\", \"t,s,h\", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s, },\n{\"prepend\", \"t,s,h\",    0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s, },\n{\"shra.qb\", \"d,t,3\",    0x7c000113, 0xff0007ff, WR_d|RD_t, },\n{\"shra_r.qb\", \"d,t,3\",  0x7c000153, 0xff0007ff, WR_d|RD_t, },\n{\"shrav.qb\", \"d,t,s\",   0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"shrav_r.qb\", \"d,t,s\", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"shrl.ph\", \"d,t,4\",    0x7c000653, 0xfe0007ff, WR_d|RD_t, },\n{\"shrlv.ph\", \"d,t,s\",   0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"subu.ph\", \"d,s,t\",    0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"subu_s.ph\", \"d,s,t\",  0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"subuh.qb\", \"d,s,t\",   0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"subuh_r.qb\", \"d,s,t\", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"addqh.ph\", \"d,s,t\",   0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"addqh_r.ph\", \"d,s,t\", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"addqh.w\", \"d,s,t\",    0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"addqh_r.w\", \"d,s,t\",  0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"subqh.ph\", \"d,s,t\",   0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"subqh_r.ph\", \"d,s,t\", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"subqh.w\", \"d,s,t\",    0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"subqh_r.w\", \"d,s,t\",  0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t, },\n{\"dpax.w.ph\", \"7,s,t\",  0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dpsx.w.ph\", \"7,s,t\",  0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dpaqx_s.w.ph\", \"7,s,t\", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dpaqx_sa.w.ph\", \"7,s,t\", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dpsqx_s.w.ph\", \"7,s,t\", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n{\"dpsqx_sa.w.ph\", \"7,s,t\", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, },\n/* Move bc0* after mftr and mttr to avoid opcode collision.  */\n{\"bc0f\",    \"p\",        0x41000000, 0xffff0000, CBD|RD_CC, },\n{\"bc0fl\",   \"p\",        0x41020000, 0xffff0000, CBL|RD_CC, },\n{\"bc0t\",    \"p\",        0x41010000, 0xffff0000, CBD|RD_CC, },\n{\"bc0tl\",   \"p\",        0x41030000, 0xffff0000, CBL|RD_CC, },\n/* ST Microelectronics Loongson-2E and -2F.  */\n{\"mult.g\",    \"d,s,t\",  0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"mult.g\",    \"d,s,t\",  0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"multu.g\",   \"d,s,t\",  0x7c000019, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"multu.g\",   \"d,s,t\",  0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"dmult.g\",   \"d,s,t\",  0x7c00001c, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"dmult.g\",   \"d,s,t\",  0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"dmultu.g\",  \"d,s,t\",  0x7c00001d, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"dmultu.g\",  \"d,s,t\",  0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"div.g\",     \"d,s,t\",  0x7c00001a, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"div.g\",     \"d,s,t\",  0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"divu.g\",    \"d,s,t\",  0x7c00001b, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"divu.g\",    \"d,s,t\",  0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"ddiv.g\",    \"d,s,t\",  0x7c00001e, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"ddiv.g\",    \"d,s,t\",  0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"ddivu.g\",   \"d,s,t\",  0x7c00001f, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"ddivu.g\",   \"d,s,t\",  0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"mod.g\",     \"d,s,t\",  0x7c000022, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"mod.g\",     \"d,s,t\",  0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"modu.g\",    \"d,s,t\",  0x7c000023, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"modu.g\",    \"d,s,t\",  0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"dmod.g\",    \"d,s,t\",  0x7c000026, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"dmod.g\",    \"d,s,t\",  0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"dmodu.g\",   \"d,s,t\",  0x7c000027, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"dmodu.g\",   \"d,s,t\",  0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, },\n{\"packsshb\",  \"D,S,T\",  0x47400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"packsshb\",  \"D,S,T\",  0x4b400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"packsswh\",  \"D,S,T\",  0x47200002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"packsswh\",  \"D,S,T\",  0x4b200002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"packushb\",  \"D,S,T\",  0x47600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"packushb\",  \"D,S,T\",  0x4b600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"paddb\",     \"D,S,T\",  0x47c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"paddb\",     \"D,S,T\",  0x4bc00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"paddh\",     \"D,S,T\",  0x47400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"paddh\",     \"D,S,T\",  0x4b400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"paddw\",     \"D,S,T\",  0x47600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"paddw\",     \"D,S,T\",  0x4b600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"paddd\",     \"D,S,T\",  0x47e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"paddd\",     \"D,S,T\",  0x4be00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"paddsb\",    \"D,S,T\",  0x47800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"paddsb\",    \"D,S,T\",  0x4b800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"paddsh\",    \"D,S,T\",  0x47000000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"paddsh\",    \"D,S,T\",  0x4b000000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"paddusb\",   \"D,S,T\",  0x47a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"paddusb\",   \"D,S,T\",  0x4ba00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"paddush\",   \"D,S,T\",  0x47200000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"paddush\",   \"D,S,T\",  0x4b200000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pandn\",     \"D,S,T\",  0x47e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pandn\",     \"D,S,T\",  0x4be00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pavgb\",     \"D,S,T\",  0x46600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pavgb\",     \"D,S,T\",  0x4b200008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pavgh\",     \"D,S,T\",  0x46400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pavgh\",     \"D,S,T\",  0x4b000008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pcmpeqb\",   \"D,S,T\",  0x46c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pcmpeqb\",   \"D,S,T\",  0x4b800009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pcmpeqh\",   \"D,S,T\",  0x46800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pcmpeqh\",   \"D,S,T\",  0x4b400009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pcmpeqw\",   \"D,S,T\",  0x46400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pcmpeqw\",   \"D,S,T\",  0x4b000009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pcmpgtb\",   \"D,S,T\",  0x46e00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pcmpgtb\",   \"D,S,T\",  0x4ba00009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pcmpgth\",   \"D,S,T\",  0x46a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pcmpgth\",   \"D,S,T\",  0x4b600009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pcmpgtw\",   \"D,S,T\",  0x46600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pcmpgtw\",   \"D,S,T\",  0x4b200009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pextrh\",    \"D,S,T\",  0x45c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pextrh\",    \"D,S,T\",  0x4b40000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pinsrh_0\",  \"D,S,T\",  0x47800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pinsrh_0\",  \"D,S,T\",  0x4b800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pinsrh_1\",  \"D,S,T\",  0x47a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pinsrh_1\",  \"D,S,T\",  0x4ba00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pinsrh_2\",  \"D,S,T\",  0x47c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pinsrh_2\",  \"D,S,T\",  0x4bc00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pinsrh_3\",  \"D,S,T\",  0x47e00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pinsrh_3\",  \"D,S,T\",  0x4be00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pmaddhw\",   \"D,S,T\",  0x45e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pmaddhw\",   \"D,S,T\",  0x4b60000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pmaxsh\",    \"D,S,T\",  0x46800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pmaxsh\",    \"D,S,T\",  0x4b400008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pmaxub\",    \"D,S,T\",  0x46c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pmaxub\",    \"D,S,T\",  0x4b800008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pminsh\",    \"D,S,T\",  0x46a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pminsh\",    \"D,S,T\",  0x4b600008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pminub\",    \"D,S,T\",  0x46e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pminub\",    \"D,S,T\",  0x4ba00008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pmovmskb\",  \"D,S\",    0x46a00005, 0xffff003f, RD_S|WR_D|FP_D, },\n{\"pmovmskb\",  \"D,S\",    0x4ba0000f, 0xffff003f, RD_S|WR_D|FP_D, },\n{\"pmulhuh\",   \"D,S,T\",  0x46e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pmulhuh\",   \"D,S,T\",  0x4ba0000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pmulhh\",    \"D,S,T\",  0x46a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pmulhh\",    \"D,S,T\",  0x4b60000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pmullh\",    \"D,S,T\",  0x46800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pmullh\",    \"D,S,T\",  0x4b40000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pmuluw\",    \"D,S,T\",  0x46c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pmuluw\",    \"D,S,T\",  0x4b80000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pasubub\",   \"D,S,T\",  0x45a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pasubub\",   \"D,S,T\",  0x4b20000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"biadd\",     \"D,S\",    0x46800005, 0xffff003f, RD_S|WR_D|FP_D, },\n{\"biadd\",     \"D,S\",    0x4b80000f, 0xffff003f, RD_S|WR_D|FP_D, },\n{\"pshufh\",    \"D,S,T\",  0x47000002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"pshufh\",    \"D,S,T\",  0x4b000002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psllh\",     \"D,S,T\",  0x46600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psllh\",     \"D,S,T\",  0x4b20000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psllw\",     \"D,S,T\",  0x46400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psllw\",     \"D,S,T\",  0x4b00000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psrah\",     \"D,S,T\",  0x46a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psrah\",     \"D,S,T\",  0x4b60000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psraw\",     \"D,S,T\",  0x46800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psraw\",     \"D,S,T\",  0x4b40000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psrlh\",     \"D,S,T\",  0x46600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psrlh\",     \"D,S,T\",  0x4b20000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psrlw\",     \"D,S,T\",  0x46400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psrlw\",     \"D,S,T\",  0x4b00000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psubb\",     \"D,S,T\",  0x47c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psubb\",     \"D,S,T\",  0x4bc00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psubh\",     \"D,S,T\",  0x47400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psubh\",     \"D,S,T\",  0x4b400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psubw\",     \"D,S,T\",  0x47600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psubw\",     \"D,S,T\",  0x4b600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psubd\",     \"D,S,T\",  0x47e00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psubd\",     \"D,S,T\",  0x4be00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psubsb\",    \"D,S,T\",  0x47800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psubsb\",    \"D,S,T\",  0x4b800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psubsh\",    \"D,S,T\",  0x47000001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psubsh\",    \"D,S,T\",  0x4b000001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psubusb\",   \"D,S,T\",  0x47a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psubusb\",   \"D,S,T\",  0x4ba00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psubush\",   \"D,S,T\",  0x47200001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"psubush\",   \"D,S,T\",  0x4b200001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"punpckhbh\", \"D,S,T\",  0x47600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"punpckhbh\", \"D,S,T\",  0x4b600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"punpckhhw\", \"D,S,T\",  0x47200003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"punpckhhw\", \"D,S,T\",  0x4b200003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"punpckhwd\", \"D,S,T\",  0x46e00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"punpckhwd\", \"D,S,T\",  0x4ba0000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"punpcklbh\", \"D,S,T\",  0x47400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"punpcklbh\", \"D,S,T\",  0x4b400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"punpcklhw\", \"D,S,T\",  0x47000003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"punpcklhw\", \"D,S,T\",  0x4b000003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"punpcklwd\", \"D,S,T\",  0x46c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"punpcklwd\", \"D,S,T\",  0x4b80000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, },\n{\"sequ\",      \"S,T\",    0x46800032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n{\"sequ\",      \"S,T\",    0x4b80000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, },\n/* No hazard protection on coprocessor instructions--they shouldn't\n   change the state of the processor and if they do it's up to the\n   user to put in nops as necessary.  These are at the end so that the\n   disassembler recognizes more specific versions first.  */\n{\"c0\",      \"C\",        0x42000000, 0xfe000000, CP, },\n{\"c1\",      \"C\",        0x46000000, 0xfe000000, FP_S, },\n{\"c2\",      \"C\",        0x4a000000, 0xfe000000, CP, },\n{\"c3\",      \"C\",        0x4e000000, 0xfe000000, CP, },\n{\"cop0\",    \"C\",        0,    (int) M_COP0,     INSN_MACRO, },\n{\"cop1\",    \"C\",        0,    (int) M_COP1,     INSN_MACRO,             INSN2_M_FP_S, },\n{\"cop2\",    \"C\",        0,    (int) M_COP2,     INSN_MACRO, },\n{\"cop3\",    \"C\",        0,    (int) M_COP3,     INSN_MACRO, }\n};\n\nstatic const int mips_num_opcodes = sizeof (mips_opcodes) / sizeof (mips_opcodes[0]);\n\n#undef LDD\n#undef LCD\n#undef UBD\n#undef CBD\n#undef COD\n#undef CLD\n#undef CBL\n#undef TRAP\n#undef SM\n\n#undef WR_d\n#undef WR_t\n#undef WR_31\n#undef WR_D\n#undef WR_T\n#undef WR_S\n#undef RD_s\n#undef RD_b\n#undef RD_t\n#undef RD_S\n#undef RD_T\n#undef RD_R\n#undef WR_CC\n#undef RD_CC\n#undef RD_C0\n#undef RD_C1\n#undef RD_C2\n#undef RD_C3\n#undef WR_C0\n#undef WR_C1\n#undef WR_C2\n#undef WR_C3\n#undef CP\n\n#undef WR_HI\n#undef RD_HI\n#undef MOD_HI\n\n#undef WR_LO\n#undef RD_LO\n#undef MOD_LO\n\n#undef WR_HILO\n#undef RD_HILO\n#undef MOD_HILO\n\n#undef IS_M\n\n#undef WR_MACC\n#undef RD_MACC\n\n#undef WR_a\n#undef RD_a\n#undef MOD_a\n#undef DSP_VOLA\n"
  },
  {
    "path": "tools/virtualmips/mips-opcode.h",
    "content": "/*\n * Mips opcode list.\n *\n * Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,\n * 2003, 2004, 2005, 2008, 2009, 2010\n * Free Software Foundation, Inc.\n * Contributed by Ralph Campbell and OSF\n * Commented and modified by Ian Lance Taylor, Cygnus Support\n * Adapted for VirtualMIPS by Serge Vakulenko.\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n\n#ifndef _MIPS_H_\n#define _MIPS_H_\n\n/* These are bit masks and shift counts to use to access the various\n   fields of an instruction.  To retrieve the X field of an\n   instruction, use the expression\n\t(i >> OP_SH_X) & OP_MASK_X\n   To set the same field (to j), use\n\ti = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)\n\n   Make sure you use fields that are appropriate for the instruction,\n   of course.\n\n   The 'i' format uses OP, RS, RT and IMMEDIATE.\n\n   The 'j' format uses OP and TARGET.\n\n   The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.\n\n   The 'b' format uses OP, RS, RT and DELTA.\n\n   The floating point 'i' format uses OP, RS, RT and IMMEDIATE.\n\n   The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.\n\n   A breakpoint instruction uses OP, CODE and SPEC (10 bits of the\n   breakpoint instruction are not defined; Kane says the breakpoint\n   code field in BREAK is 20 bits; yet MIPS assemblers and debuggers\n   only use ten bits).  An optional two-operand form of break/sdbbp\n   allows the lower ten bits to be set too, and MIPS32 and later\n   architectures allow 20 bits to be set with a signal operand\n   (using CODE20).\n\n   The syscall instruction uses CODE20.\n\n   The general coprocessor instructions use COPZ.  */\n\n#define OP_MASK_OP\t\t0x3f\n#define OP_SH_OP\t\t26\n#define OP_MASK_RS\t\t0x1f\n#define OP_SH_RS\t\t21\n#define OP_MASK_FR\t\t0x1f\n#define OP_SH_FR\t\t21\n#define OP_MASK_FMT\t\t0x1f\n#define OP_SH_FMT\t\t21\n#define OP_MASK_BCC\t\t0x7\n#define OP_SH_BCC\t\t18\n#define OP_MASK_CODE\t\t0x3ff\n#define OP_SH_CODE\t\t16\n#define OP_MASK_CODE2\t\t0x3ff\n#define OP_SH_CODE2\t\t6\n#define OP_MASK_RT\t\t0x1f\n#define OP_SH_RT\t\t16\n#define OP_MASK_FT\t\t0x1f\n#define OP_SH_FT\t\t16\n#define OP_MASK_CACHE\t\t0x1f\n#define OP_SH_CACHE\t\t16\n#define OP_MASK_RD\t\t0x1f\n#define OP_SH_RD\t\t11\n#define OP_MASK_FS\t\t0x1f\n#define OP_SH_FS\t\t11\n#define OP_MASK_PREFX\t\t0x1f\n#define OP_SH_PREFX\t\t11\n#define OP_MASK_CCC\t\t0x7\n#define OP_SH_CCC\t\t8\n#define OP_MASK_CODE20\t\t0xfffff /* 20 bit syscall/breakpoint code.  */\n#define OP_SH_CODE20\t\t6\n#define OP_MASK_SHAMT\t\t0x1f\n#define OP_SH_SHAMT\t\t6\n#define OP_MASK_FD\t\t0x1f\n#define OP_SH_FD\t\t6\n#define OP_MASK_TARGET\t\t0x3ffffff\n#define OP_SH_TARGET\t\t0\n#define OP_MASK_COPZ\t\t0x1ffffff\n#define OP_SH_COPZ\t\t0\n#define OP_MASK_IMMEDIATE\t0xffff\n#define OP_SH_IMMEDIATE\t\t0\n#define OP_MASK_DELTA\t\t0xffff\n#define OP_SH_DELTA\t\t0\n#define OP_MASK_FUNCT\t\t0x3f\n#define OP_SH_FUNCT\t\t0\n#define OP_MASK_SPEC\t\t0x3f\n#define OP_SH_SPEC\t\t0\n#define OP_SH_LOCC              8       /* FP condition code.  */\n#define OP_SH_HICC              18      /* FP condition code.  */\n#define OP_MASK_CC              0x7\n#define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */\n#define OP_MASK_COP1NORM        0x1     /* a single bit.  */\n#define OP_SH_COP1SPEC          21      /* COP1 encodings.  */\n#define OP_MASK_COP1SPEC        0xf\n#define OP_MASK_COP1SCLR        0x4\n#define OP_MASK_COP1CMP         0x3\n#define OP_SH_COP1CMP           4\n#define OP_SH_FORMAT            21      /* FP short format field.  */\n#define OP_MASK_FORMAT          0x7\n#define OP_SH_TRUE              16\n#define OP_MASK_TRUE            0x1\n#define OP_SH_GE                17\n#define OP_MASK_GE              0x01\n#define OP_SH_UNSIGNED          16\n#define OP_MASK_UNSIGNED        0x1\n#define OP_SH_HINT              16\n#define OP_MASK_HINT            0x1f\n#define OP_SH_MMI               0       /* Multimedia (parallel) op.  */\n#define OP_MASK_MMI             0x3f\n#define OP_SH_MMISUB            6\n#define OP_MASK_MMISUB          0x1f\n#define OP_MASK_PERFREG\t\t0x1f\t/* Performance monitoring.  */\n#define OP_SH_PERFREG\t\t1\n#define OP_SH_SEL\t\t0\t/* Coprocessor select field.  */\n#define OP_MASK_SEL\t\t0x7\t/* The sel field of mfcZ and mtcZ.  */\n#define OP_SH_CODE19\t\t6       /* 19 bit wait code.  */\n#define OP_MASK_CODE19\t\t0x7ffff\n#define OP_SH_ALN\t\t21\n#define OP_MASK_ALN\t\t0x7\n#define OP_SH_VSEL\t\t21\n#define OP_MASK_VSEL\t\t0x1f\n#define OP_MASK_VECBYTE\t\t0x7\t/* Selector field is really 4 bits,\n\t\t\t\t\t   but 0x8-0xf don't select bytes.  */\n#define OP_SH_VECBYTE\t\t22\n#define OP_MASK_VECALIGN\t0x7\t/* Vector byte-align (alni.ob) op.  */\n#define OP_SH_VECALIGN\t\t21\n#define OP_MASK_INSMSB\t\t0x1f\t/* \"ins\" MSB.  */\n#define OP_SH_INSMSB\t\t11\n#define OP_MASK_EXTMSBD\t\t0x1f\t/* \"ext\" MSBD.  */\n#define OP_SH_EXTMSBD\t\t11\n\n/* MIPS DSP ASE */\n#define OP_SH_DSPACC\t\t11\n#define OP_MASK_DSPACC  \t0x3\n#define OP_SH_DSPACC_S  \t21\n#define OP_MASK_DSPACC_S\t0x3\n#define OP_SH_DSPSFT\t\t20\n#define OP_MASK_DSPSFT  \t0x3f\n#define OP_SH_DSPSFT_7  \t19\n#define OP_MASK_DSPSFT_7\t0x7f\n#define OP_SH_SA3\t\t21\n#define OP_MASK_SA3\t\t0x7\n#define OP_SH_SA4\t\t21\n#define OP_MASK_SA4\t\t0xf\n#define OP_SH_IMM8\t\t16\n#define OP_MASK_IMM8\t\t0xff\n#define OP_SH_IMM10\t\t16\n#define OP_MASK_IMM10\t\t0x3ff\n#define OP_SH_WRDSP\t\t11\n#define OP_MASK_WRDSP\t\t0x3f\n#define OP_SH_RDDSP\t\t16\n#define OP_MASK_RDDSP\t\t0x3f\n#define OP_SH_BP\t\t11\n#define OP_MASK_BP\t\t0x3\n\n/* MIPS MT ASE */\n#define OP_SH_MT_U\t\t5\n#define OP_MASK_MT_U\t\t0x1\n#define OP_SH_MT_H\t\t4\n#define OP_MASK_MT_H\t\t0x1\n#define OP_SH_MTACC_T\t\t18\n#define OP_MASK_MTACC_T\t\t0x3\n#define OP_SH_MTACC_D\t\t13\n#define OP_MASK_MTACC_D\t\t0x3\n\n#define\tOP_OP_COP0\t\t0x10\n#define\tOP_OP_COP1\t\t0x11\n#define\tOP_OP_COP2\t\t0x12\n#define\tOP_OP_COP3\t\t0x13\n#define\tOP_OP_LWC1\t\t0x31\n#define\tOP_OP_LWC2\t\t0x32\n#define\tOP_OP_LWC3\t\t0x33\t/* a.k.a. pref */\n#define\tOP_OP_LDC1\t\t0x35\n#define\tOP_OP_LDC2\t\t0x36\n#define\tOP_OP_LDC3\t\t0x37\t/* a.k.a. ld */\n#define\tOP_OP_SWC1\t\t0x39\n#define\tOP_OP_SWC2\t\t0x3a\n#define\tOP_OP_SWC3\t\t0x3b\n#define\tOP_OP_SDC1\t\t0x3d\n#define\tOP_OP_SDC2\t\t0x3e\n#define\tOP_OP_SDC3\t\t0x3f\t/* a.k.a. sd */\n\n/* Values in the 'VSEL' field.  */\n#define MDMX_FMTSEL_IMM_QH\t0x1d\n#define MDMX_FMTSEL_IMM_OB\t0x1e\n#define MDMX_FMTSEL_VEC_QH\t0x15\n#define MDMX_FMTSEL_VEC_OB\t0x16\n\n/* UDI */\n#define OP_SH_UDI1\t\t6\n#define OP_MASK_UDI1\t\t0x1f\n#define OP_SH_UDI2\t\t6\n#define OP_MASK_UDI2\t\t0x3ff\n#define OP_SH_UDI3\t\t6\n#define OP_MASK_UDI3\t\t0x7fff\n#define OP_SH_UDI4\t\t6\n#define OP_MASK_UDI4\t\t0xfffff\n\n/* Octeon */\n#define OP_SH_BBITIND\t\t16\n#define OP_MASK_BBITIND\t\t0x1f\n#define OP_SH_CINSPOS\t\t6\n#define OP_MASK_CINSPOS\t\t0x1f\n#define OP_SH_CINSLM1\t\t11\n#define OP_MASK_CINSLM1\t\t0x1f\n#define OP_SH_SEQI\t\t6\n#define OP_MASK_SEQI\t\t0x3ff\n\n/* This structure holds information for a particular instruction.  */\n\nstruct mips_opcode\n{\n  /* The name of the instruction.  */\n  const char *name;\n  /* A string describing the arguments for this instruction.  */\n  const char *args;\n  /* The basic opcode for the instruction.  When assembling, this\n     opcode is modified by the arguments to produce the actual opcode\n     that is used.  If pinfo is INSN_MACRO, then this is 0.  */\n  unsigned long match;\n  /* If pinfo is not INSN_MACRO, then this is a bit mask for the\n     relevant portions of the opcode when disassembling.  If the\n     actual opcode anded with the match field equals the opcode field,\n     then we have found the correct instruction.  If pinfo is\n     INSN_MACRO, then this field is the macro identifier.  */\n  unsigned long mask;\n  /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection\n     of bits describing the instruction, notably any relevant hazard\n     information.  */\n  unsigned long pinfo;\n  /* A collection of additional bits describing the instruction. */\n  unsigned long pinfo2;\n};\n\n/* These are the characters which may appear in the args field of an\n   instruction.  They appear in the order in which the fields appear\n   when the instruction is used.  Commas and parentheses in the args\n   string are ignored when assembling, and written into the output\n   when disassembling.\n\n   Each of these characters corresponds to a mask field defined above.\n\n   \"1\" 5 bit sync type (OP_*_SHAMT)\n   \"<\" 5 bit shift amount (OP_*_SHAMT)\n   \">\" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)\n   \"a\" 26 bit target address (OP_*_TARGET)\n   \"b\" 5 bit base register (OP_*_RS)\n   \"c\" 10 bit breakpoint code (OP_*_CODE)\n   \"d\" 5 bit destination register specifier (OP_*_RD)\n   \"h\" 5 bit prefx hint (OP_*_PREFX)\n   \"i\" 16 bit unsigned immediate (OP_*_IMMEDIATE)\n   \"j\" 16 bit signed immediate (OP_*_DELTA)\n   \"k\" 5 bit cache opcode in target register position (OP_*_CACHE)\n       Also used for immediate operands in vr5400 vector insns.\n   \"o\" 16 bit signed offset (OP_*_DELTA)\n   \"p\" 16 bit PC relative branch target address (OP_*_DELTA)\n   \"q\" 10 bit extra breakpoint code (OP_*_CODE2)\n   \"r\" 5 bit same register used as both source and target (OP_*_RS)\n   \"s\" 5 bit source register specifier (OP_*_RS)\n   \"t\" 5 bit target register (OP_*_RT)\n   \"u\" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)\n   \"v\" 5 bit same register used as both source and destination (OP_*_RS)\n   \"w\" 5 bit same register used as both target and destination (OP_*_RT)\n   \"U\" 5 bit same destination register in both OP_*_RD and OP_*_RT\n       (used by clo and clz)\n   \"C\" 25 bit coprocessor function code (OP_*_COPZ)\n   \"B\" 20 bit syscall/breakpoint function code (OP_*_CODE20)\n   \"J\" 19 bit wait function code (OP_*_CODE19)\n   \"x\" accept and ignore register name\n   \"z\" must be zero register\n   \"K\" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)\n   \"+A\" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes\n        LSB (OP_*_SHAMT).\n\tEnforces: 0 <= pos < 32.\n   \"+B\" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).\n\tRequires that \"+A\" or \"+E\" occur first to set position.\n\tEnforces: 0 < (pos+size) <= 32.\n   \"+C\" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).\n\tRequires that \"+A\" or \"+E\" occur first to set position.\n\tEnforces: 0 < (pos+size) <= 32.\n\t(Also used by \"dext\" w/ different limits, but limits for\n\tthat are checked by the M_DEXT macro.)\n   \"+E\" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).\n\tEnforces: 32 <= pos < 64.\n   \"+F\" 5 bit \"dinsm/dinsu\" size, which becomes MSB-32 (OP_*_INSMSB).\n\tRequires that \"+A\" or \"+E\" occur first to set position.\n\tEnforces: 32 < (pos+size) <= 64.\n   \"+G\" 5 bit \"dextm\" size, which becomes MSBD-32 (OP_*_EXTMSBD).\n\tRequires that \"+A\" or \"+E\" occur first to set position.\n\tEnforces: 32 < (pos+size) <= 64.\n   \"+H\" 5 bit \"dextu\" size, which becomes MSBD (OP_*_EXTMSBD).\n\tRequires that \"+A\" or \"+E\" occur first to set position.\n\tEnforces: 32 < (pos+size) <= 64.\n\n   Floating point instructions:\n   \"D\" 5 bit destination register (OP_*_FD)\n   \"M\" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)\n   \"N\" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)\n   \"S\" 5 bit fs source 1 register (OP_*_FS)\n   \"T\" 5 bit ft source 2 register (OP_*_FT)\n   \"R\" 5 bit fr source 3 register (OP_*_FR)\n   \"V\" 5 bit same register used as floating source and destination (OP_*_FS)\n   \"W\" 5 bit same register used as floating target and destination (OP_*_FT)\n\n   Coprocessor instructions:\n   \"E\" 5 bit target register (OP_*_RT)\n   \"G\" 5 bit destination register (OP_*_RD)\n   \"H\" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)\n   \"P\" 5 bit performance-monitor register (OP_*_PERFREG)\n   \"e\" 5 bit vector register byte specifier (OP_*_VECBYTE)\n   \"%\" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)\n   see also \"k\" above\n   \"+D\" Combined destination register (\"G\") and sel (\"H\") for CP0 ops,\n\tfor pretty-printing in disassembly only.\n\n   Macro instructions:\n   \"A\" General 32 bit expression\n   \"I\" 32 bit immediate (value placed in imm_expr).\n   \"+I\" 32 bit immediate (value placed in imm2_expr).\n   \"F\" 64 bit floating point constant in .rdata\n   \"L\" 64 bit floating point constant in .lit8\n   \"f\" 32 bit floating point constant\n   \"l\" 32 bit floating point constant in .lit4\n\n   MDMX instruction operands (note that while these use the FP register\n   fields, they accept both $fN and $vN names for the registers):\n   \"O\"\tMDMX alignment offset (OP_*_ALN)\n   \"Q\"\tMDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)\n   \"X\"\tMDMX destination register (OP_*_FD)\n   \"Y\"\tMDMX source register (OP_*_FS)\n   \"Z\"\tMDMX source register (OP_*_FT)\n\n   DSP ASE usage:\n   \"2\" 2 bit unsigned immediate for byte align (OP_*_BP)\n   \"3\" 3 bit unsigned immediate (OP_*_SA3)\n   \"4\" 4 bit unsigned immediate (OP_*_SA4)\n   \"5\" 8 bit unsigned immediate (OP_*_IMM8)\n   \"6\" 5 bit unsigned immediate (OP_*_RS)\n   \"7\" 2 bit dsp accumulator register (OP_*_DSPACC)\n   \"8\" 6 bit unsigned immediate (OP_*_WRDSP)\n   \"9\" 2 bit dsp accumulator register (OP_*_DSPACC_S)\n   \"0\" 6 bit signed immediate (OP_*_DSPSFT)\n   \":\" 7 bit signed immediate (OP_*_DSPSFT_7)\n   \"'\" 6 bit unsigned immediate (OP_*_RDDSP)\n   \"@\" 10 bit signed immediate (OP_*_IMM10)\n\n   MT ASE usage:\n   \"!\" 1 bit usermode flag (OP_*_MT_U)\n   \"$\" 1 bit load high flag (OP_*_MT_H)\n   \"*\" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)\n   \"&\" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)\n   \"g\" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)\n   \"+t\" 5 bit coprocessor 0 destination register (OP_*_RT)\n   \"+T\" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only\n\n   UDI immediates:\n   \"+1\" UDI immediate bits 6-10\n   \"+2\" UDI immediate bits 6-15\n   \"+3\" UDI immediate bits 6-20\n   \"+4\" UDI immediate bits 6-25\n\n   Octeon:\n   \"+x\" Bit index field of bbit.  Enforces: 0 <= index < 32.\n   \"+X\" Bit index field of bbit aliasing bbit32.  Matches if 32 <= index < 64,\n\totherwise skips to next candidate.\n   \"+p\" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.\n   \"+P\" Position field of cins/exts aliasing cins32/exts32.  Matches if\n\t32 <= pos < 64, otherwise skips to next candidate.\n   \"+Q\" Immediate field of seqi/snei.  Enforces -512 <= imm < 512.\n   \"+s\" Length-minus-one field of cins/exts.  Enforces: 0 <= lenm1 < 32.\n   \"+S\" Length-minus-one field of cins32/exts32 or cins/exts aliasing\n\tcint32/exts32.  Enforces non-negative value and that\n\tpos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous\n\tposition field is \"+p\" or \"+P\".\n\n   Other:\n   \"()\" parens surrounding optional value\n   \",\"  separates operands\n   \"[]\" brackets around index for vector-op scalar operand specifier (vr5400)\n   \"+\"  Start of extension sequence.\n\n   Characters used so far, for quick reference when adding more:\n   \"1234567890\"\n   \"%[]<>(),+:'@!$*&\"\n   \"ABCDEFGHIJKLMNOPQRSTUVWXYZ\"\n   \"abcdefghijklopqrstuvwxz\"\n\n   Extension character sequences used so far (\"+\" followed by the\n   following), for quick reference when adding more:\n   \"1234\"\n   \"ABCDEFGHIPQSTX\"\n   \"pstx\"\n*/\n\n/* These are the bits which may be set in the pinfo field of an\n   instructions, if it is not equal to INSN_MACRO.  */\n\n/* Modifies the general purpose register in OP_*_RD.  */\n#define INSN_WRITE_GPR_D            0x00000001\n/* Modifies the general purpose register in OP_*_RT.  */\n#define INSN_WRITE_GPR_T            0x00000002\n/* Modifies general purpose register 31.  */\n#define INSN_WRITE_GPR_31           0x00000004\n/* Modifies the floating point register in OP_*_FD.  */\n#define INSN_WRITE_FPR_D            0x00000008\n/* Modifies the floating point register in OP_*_FS.  */\n#define INSN_WRITE_FPR_S            0x00000010\n/* Modifies the floating point register in OP_*_FT.  */\n#define INSN_WRITE_FPR_T            0x00000020\n/* Reads the general purpose register in OP_*_RS.  */\n#define INSN_READ_GPR_S             0x00000040\n/* Reads the general purpose register in OP_*_RT.  */\n#define INSN_READ_GPR_T             0x00000080\n/* Reads the floating point register in OP_*_FS.  */\n#define INSN_READ_FPR_S             0x00000100\n/* Reads the floating point register in OP_*_FT.  */\n#define INSN_READ_FPR_T             0x00000200\n/* Reads the floating point register in OP_*_FR.  */\n#define INSN_READ_FPR_R\t\t    0x00000400\n/* Modifies coprocessor condition code.  */\n#define INSN_WRITE_COND_CODE        0x00000800\n/* Reads coprocessor condition code.  */\n#define INSN_READ_COND_CODE         0x00001000\n/* TLB operation.  */\n#define INSN_TLB                    0x00002000\n/* Reads coprocessor register other than floating point register.  */\n#define INSN_COP                    0x00004000\n/* Instruction loads value from memory, requiring delay.  */\n#define INSN_LOAD_MEMORY_DELAY      0x00008000\n/* Instruction loads value from coprocessor, requiring delay.  */\n#define INSN_LOAD_COPROC_DELAY\t    0x00010000\n/* Instruction has unconditional branch delay slot.  */\n#define INSN_UNCOND_BRANCH_DELAY    0x00020000\n/* Instruction has conditional branch delay slot.  */\n#define INSN_COND_BRANCH_DELAY      0x00040000\n/* Conditional branch likely: if branch not taken, insn nullified.  */\n#define INSN_COND_BRANCH_LIKELY\t    0x00080000\n/* Moves to coprocessor register, requiring delay.  */\n#define INSN_COPROC_MOVE_DELAY      0x00100000\n/* Loads coprocessor register from memory, requiring delay.  */\n#define INSN_COPROC_MEMORY_DELAY    0x00200000\n/* Reads the HI register.  */\n#define INSN_READ_HI\t\t    0x00400000\n/* Reads the LO register.  */\n#define INSN_READ_LO\t\t    0x00800000\n/* Modifies the HI register.  */\n#define INSN_WRITE_HI\t\t    0x01000000\n/* Modifies the LO register.  */\n#define INSN_WRITE_LO\t\t    0x02000000\n/* Takes a trap (easier to keep out of delay slot).  */\n#define INSN_TRAP                   0x04000000\n/* Instruction stores value into memory.  */\n#define INSN_STORE_MEMORY\t    0x08000000\n/* Instruction uses single precision floating point.  */\n#define FP_S\t\t\t    0x10000000\n/* Instruction uses double precision floating point.  */\n#define FP_D\t\t\t    0x20000000\n/* Instruction is part of the tx39's integer multiply family.    */\n#define INSN_MULT                   0x40000000\n/* Instruction synchronize shared memory.  */\n#define INSN_SYNC\t\t    0x80000000\n/* Instruction is actually a macro.  It should be ignored by the\n   disassembler, and requires special treatment by the assembler.  */\n#define INSN_MACRO                  0xffffffff\n\n/* These are the bits which may be set in the pinfo2 field of an\n   instruction. */\n\n/* Instruction is a simple alias (I.E. \"move\" for daddu/addu/or) */\n#define\tINSN2_ALIAS\t\t    0x00000001\n/* Instruction reads MDMX accumulator. */\n#define INSN2_READ_MDMX_ACC\t    0x00000002\n/* Instruction writes MDMX accumulator. */\n#define INSN2_WRITE_MDMX_ACC\t    0x00000004\n/* Macro uses single-precision floating-point instructions.  This should\n   only be set for macros.  For instructions, FP_S in pinfo carries the\n   same information.  */\n#define INSN2_M_FP_S\t\t    0x00000008\n/* Macro uses double-precision floating-point instructions.  This should\n   only be set for macros.  For instructions, FP_D in pinfo carries the\n   same information.  */\n#define INSN2_M_FP_D\t\t    0x00000010\n\n/* Masks used for Chip specific instructions.  */\n#define INSN_CHIP_MASK\t\t  0xc3ff0820\n\n/* Cavium Networks Octeon instructions.  */\n#define INSN_OCTEON\t\t  0x00000800\n\n/* Masks used for MIPS-defined ASEs.  */\n#define INSN_ASE_MASK\t\t  0x3c00f000\n\n/* DSP ASE */\n#define INSN_DSP                  0x00001000\n#define INSN_DSP64                0x00002000\n\n/* 0x00004000 is unused.  */\n\n/* MIPS-3D ASE */\n#define INSN_MIPS3D               0x00008000\n\n/* MIPS R4650 instruction.  */\n#define INSN_4650                 0x00010000\n/* LSI R4010 instruction.  */\n#define INSN_4010                 0x00020000\n/* NEC VR4100 instruction.  */\n#define INSN_4100                 0x00040000\n/* Toshiba R3900 instruction.  */\n#define INSN_3900                 0x00080000\n/* MIPS R10000 instruction.  */\n#define INSN_10000                0x00100000\n/* Broadcom SB-1 instruction.  */\n#define INSN_SB1                  0x00200000\n/* NEC VR4111/VR4181 instruction.  */\n#define INSN_4111                 0x00400000\n/* NEC VR4120 instruction.  */\n#define INSN_4120                 0x00800000\n/* NEC VR5400 instruction.  */\n#define INSN_5400\t\t  0x01000000\n/* NEC VR5500 instruction.  */\n#define INSN_5500\t\t  0x02000000\n\n/* MDMX ASE */\n#define INSN_MDMX                 0x04000000\n/* MT ASE */\n#define INSN_MT                   0x08000000\n/* SmartMIPS ASE  */\n#define INSN_SMARTMIPS            0x10000000\n/* DSP R2 ASE  */\n#define INSN_DSPR2                0x20000000\n/* ST Microelectronics Loongson 2E.  */\n#define INSN_LOONGSON_2E          0x40000000\n/* ST Microelectronics Loongson 2F.  */\n#define INSN_LOONGSON_2F          0x80000000\n/* RMI Xlr instruction */\n#define INSN_XLR              \t  0x00000020\n\n/* MIPS ISA defines, use instead of hardcoding ISA level.  */\n\n#define       ISA_UNKNOWN     0               /* Gas internal use.  */\n#define       ISA_MIPS1       INSN_ISA1\n#define       ISA_MIPS2       INSN_ISA2\n#define       ISA_MIPS3       INSN_ISA3\n#define       ISA_MIPS4       INSN_ISA4\n#define       ISA_MIPS5       INSN_ISA5\n\n#define       ISA_MIPS32      INSN_ISA32\n#define       ISA_MIPS64      INSN_ISA64\n\n#define       ISA_MIPS32R2    INSN_ISA32R2\n#define       ISA_MIPS64R2    INSN_ISA64R2\n\n\n/* CPU defines, use instead of hardcoding processor number. Keep this\n   in sync with bfd/archures.c in order for machine selection to work.  */\n#define CPU_UNKNOWN\t0               /* Gas internal use.  */\n#define CPU_R3000\t3000\n#define CPU_R3900\t3900\n#define CPU_R4000\t4000\n#define CPU_R4010\t4010\n#define CPU_VR4100\t4100\n#define CPU_R4111\t4111\n#define CPU_VR4120\t4120\n#define CPU_R4300\t4300\n#define CPU_R4400\t4400\n#define CPU_R4600\t4600\n#define CPU_R4650\t4650\n#define CPU_R5000\t5000\n#define CPU_VR5400\t5400\n#define CPU_VR5500\t5500\n#define CPU_R6000\t6000\n#define CPU_RM7000\t7000\n#define CPU_R8000\t8000\n#define CPU_RM9000\t9000\n#define CPU_R10000\t10000\n#define CPU_R12000\t12000\n#define CPU_R14000\t14000\n#define CPU_R16000\t16000\n#define CPU_MIPS16\t16\n#define CPU_MIPS32\t32\n#define CPU_MIPS32R2\t33\n#define CPU_MIPS5       5\n#define CPU_MIPS64      64\n#define CPU_MIPS64R2\t65\n#define CPU_SB1         12310201        /* octal 'SB', 01.  */\n#define CPU_LOONGSON_2E 3001\n#define CPU_LOONGSON_2F 3002\n#define CPU_OCTEON\t6501\n#define CPU_XLR     \t887682   \t/* decimal 'XLR'   */\n\n/* This is a list of macro expanded instructions.\n\n   _I appended means immediate\n   _A appended means address\n   _AB appended means address with base register\n   _D appended means 64 bit floating point constant\n   _S appended means 32 bit floating point constant.  */\n\nenum\n{\n  M_ABS,\n  M_ADD_I,\n  M_ADDU_I,\n  M_AND_I,\n  M_BALIGN,\n  M_BEQ,\n  M_BEQ_I,\n  M_BEQL_I,\n  M_BGE,\n  M_BGEL,\n  M_BGE_I,\n  M_BGEL_I,\n  M_BGEU,\n  M_BGEUL,\n  M_BGEU_I,\n  M_BGEUL_I,\n  M_BGT,\n  M_BGTL,\n  M_BGT_I,\n  M_BGTL_I,\n  M_BGTU,\n  M_BGTUL,\n  M_BGTU_I,\n  M_BGTUL_I,\n  M_BLE,\n  M_BLEL,\n  M_BLE_I,\n  M_BLEL_I,\n  M_BLEU,\n  M_BLEUL,\n  M_BLEU_I,\n  M_BLEUL_I,\n  M_BLT,\n  M_BLTL,\n  M_BLT_I,\n  M_BLTL_I,\n  M_BLTU,\n  M_BLTUL,\n  M_BLTU_I,\n  M_BLTUL_I,\n  M_BNE,\n  M_BNE_I,\n  M_BNEL_I,\n  M_CACHE_AB,\n  M_DABS,\n  M_DADD_I,\n  M_DADDU_I,\n  M_DDIV_3,\n  M_DDIV_3I,\n  M_DDIVU_3,\n  M_DDIVU_3I,\n  M_DEXT,\n  M_DINS,\n  M_DIV_3,\n  M_DIV_3I,\n  M_DIVU_3,\n  M_DIVU_3I,\n  M_DLA_AB,\n  M_DLCA_AB,\n  M_DLI,\n  M_DMUL,\n  M_DMUL_I,\n  M_DMULO,\n  M_DMULO_I,\n  M_DMULOU,\n  M_DMULOU_I,\n  M_DREM_3,\n  M_DREM_3I,\n  M_DREMU_3,\n  M_DREMU_3I,\n  M_DSUB_I,\n  M_DSUBU_I,\n  M_DSUBU_I_2,\n  M_J_A,\n  M_JAL_1,\n  M_JAL_2,\n  M_JAL_A,\n  M_L_DOB,\n  M_L_DAB,\n  M_LA_AB,\n  M_LB_A,\n  M_LB_AB,\n  M_LBU_A,\n  M_LBU_AB,\n  M_LCA_AB,\n  M_LD_A,\n  M_LD_OB,\n  M_LD_AB,\n  M_LDC1_AB,\n  M_LDC2_AB,\n  M_LDC3_AB,\n  M_LDL_AB,\n  M_LDR_AB,\n  M_LH_A,\n  M_LH_AB,\n  M_LHU_A,\n  M_LHU_AB,\n  M_LI,\n  M_LI_D,\n  M_LI_DD,\n  M_LI_S,\n  M_LI_SS,\n  M_LL_AB,\n  M_LLD_AB,\n  M_LS_A,\n  M_LW_A,\n  M_LW_AB,\n  M_LWC0_A,\n  M_LWC0_AB,\n  M_LWC1_A,\n  M_LWC1_AB,\n  M_LWC2_A,\n  M_LWC2_AB,\n  M_LWC3_A,\n  M_LWC3_AB,\n  M_LWL_A,\n  M_LWL_AB,\n  M_LWR_A,\n  M_LWR_AB,\n  M_LWU_AB,\n  M_MSGSND,\n  M_MSGLD,\n  M_MSGLD_T,\n  M_MSGWAIT,\n  M_MSGWAIT_T,\n  M_MOVE,\n  M_MUL,\n  M_MUL_I,\n  M_MULO,\n  M_MULO_I,\n  M_MULOU,\n  M_MULOU_I,\n  M_NOR_I,\n  M_OR_I,\n  M_REM_3,\n  M_REM_3I,\n  M_REMU_3,\n  M_REMU_3I,\n  M_DROL,\n  M_ROL,\n  M_DROL_I,\n  M_ROL_I,\n  M_DROR,\n  M_ROR,\n  M_DROR_I,\n  M_ROR_I,\n  M_S_DA,\n  M_S_DOB,\n  M_S_DAB,\n  M_S_S,\n  M_SC_AB,\n  M_SCD_AB,\n  M_SD_A,\n  M_SD_OB,\n  M_SD_AB,\n  M_SDC1_AB,\n  M_SDC2_AB,\n  M_SDC3_AB,\n  M_SDL_AB,\n  M_SDR_AB,\n  M_SEQ,\n  M_SEQ_I,\n  M_SGE,\n  M_SGE_I,\n  M_SGEU,\n  M_SGEU_I,\n  M_SGT,\n  M_SGT_I,\n  M_SGTU,\n  M_SGTU_I,\n  M_SLE,\n  M_SLE_I,\n  M_SLEU,\n  M_SLEU_I,\n  M_SLT_I,\n  M_SLTU_I,\n  M_SNE,\n  M_SNE_I,\n  M_SB_A,\n  M_SB_AB,\n  M_SH_A,\n  M_SH_AB,\n  M_SW_A,\n  M_SW_AB,\n  M_SWC0_A,\n  M_SWC0_AB,\n  M_SWC1_A,\n  M_SWC1_AB,\n  M_SWC2_A,\n  M_SWC2_AB,\n  M_SWC3_A,\n  M_SWC3_AB,\n  M_SWL_A,\n  M_SWL_AB,\n  M_SWR_A,\n  M_SWR_AB,\n  M_SUB_I,\n  M_SUBU_I,\n  M_SUBU_I_2,\n  M_TEQ_I,\n  M_TGE_I,\n  M_TGEU_I,\n  M_TLT_I,\n  M_TLTU_I,\n  M_TNE_I,\n  M_TRUNCWD,\n  M_TRUNCWS,\n  M_ULD,\n  M_ULD_A,\n  M_ULH,\n  M_ULH_A,\n  M_ULHU,\n  M_ULHU_A,\n  M_ULW,\n  M_ULW_A,\n  M_USH,\n  M_USH_A,\n  M_USW,\n  M_USW_A,\n  M_USD,\n  M_USD_A,\n  M_XOR_I,\n  M_COP0,\n  M_COP1,\n  M_COP2,\n  M_COP3,\n  M_NUM_MACROS\n};\n\n\n/* The order of overloaded instructions matters.  Label arguments and\n   register arguments look the same. Instructions that can have either\n   for arguments must apear in the correct order in this table for the\n   assembler to pick the right one. In other words, entries with\n   immediate operands must apear after the same instruction with\n   registers.\n\n   Many instructions are short hand for other instructions (i.e., The\n   jal <register> instruction is short for jalr <register>).  */\n\n/* The rest of this file adds definitions for the mips16 TinyRISC\n   processor.  */\n\n/* These are the bitmasks and shift counts used for the different\n   fields in the instruction formats.  Other than OP, no masks are\n   provided for the fixed portions of an instruction, since they are\n   not needed.\n\n   The I format uses IMM11.\n\n   The RI format uses RX and IMM8.\n\n   The RR format uses RX, and RY.\n\n   The RRI format uses RX, RY, and IMM5.\n\n   The RRR format uses RX, RY, and RZ.\n\n   The RRI_A format uses RX, RY, and IMM4.\n\n   The SHIFT format uses RX, RY, and SHAMT.\n\n   The I8 format uses IMM8.\n\n   The I8_MOVR32 format uses RY and REGR32.\n\n   The IR_MOV32R format uses REG32R and MOV32Z.\n\n   The I64 format uses IMM8.\n\n   The RI64 format uses RY and IMM5.\n   */\n\n#define MIPS16OP_MASK_OP\t0x1f\n#define MIPS16OP_SH_OP\t\t11\n#define MIPS16OP_MASK_IMM11\t0x7ff\n#define MIPS16OP_SH_IMM11\t0\n#define MIPS16OP_MASK_RX\t0x7\n#define MIPS16OP_SH_RX\t\t8\n#define MIPS16OP_MASK_IMM8\t0xff\n#define MIPS16OP_SH_IMM8\t0\n#define MIPS16OP_MASK_RY\t0x7\n#define MIPS16OP_SH_RY\t\t5\n#define MIPS16OP_MASK_IMM5\t0x1f\n#define MIPS16OP_SH_IMM5\t0\n#define MIPS16OP_MASK_RZ\t0x7\n#define MIPS16OP_SH_RZ\t\t2\n#define MIPS16OP_MASK_IMM4\t0xf\n#define MIPS16OP_SH_IMM4\t0\n#define MIPS16OP_MASK_REGR32\t0x1f\n#define MIPS16OP_SH_REGR32\t0\n#define MIPS16OP_MASK_REG32R\t0x1f\n#define MIPS16OP_SH_REG32R\t3\n#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))\n#define MIPS16OP_MASK_MOVE32Z\t0x7\n#define MIPS16OP_SH_MOVE32Z\t0\n#define MIPS16OP_MASK_IMM6\t0x3f\n#define MIPS16OP_SH_IMM6\t5\n\n/* These are the characters which may appears in the args field of a MIPS16\n   instruction.  They appear in the order in which the fields appear when the\n   instruction is used.  Commas and parentheses in the args string are ignored\n   when assembling, and written into the output when disassembling.\n\n   \"y\" 3 bit register (MIPS16OP_*_RY)\n   \"x\" 3 bit register (MIPS16OP_*_RX)\n   \"z\" 3 bit register (MIPS16OP_*_RZ)\n   \"Z\" 3 bit register (MIPS16OP_*_MOVE32Z)\n   \"v\" 3 bit same register as source and destination (MIPS16OP_*_RX)\n   \"w\" 3 bit same register as source and destination (MIPS16OP_*_RY)\n   \"0\" zero register ($0)\n   \"S\" stack pointer ($sp or $29)\n   \"P\" program counter\n   \"R\" return address register ($ra or $31)\n   \"X\" 5 bit MIPS register (MIPS16OP_*_REGR32)\n   \"Y\" 5 bit MIPS register (MIPS16OP_*_REG32R)\n   \"6\" 6 bit unsigned break code (MIPS16OP_*_IMM6)\n   \"a\" 26 bit jump address\n   \"e\" 11 bit extension value\n   \"l\" register list for entry instruction\n   \"L\" register list for exit instruction\n\n   The remaining codes may be extended.  Except as otherwise noted,\n   the full extended operand is a 16 bit signed value.\n   \"<\" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)\n   \">\" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)\n   \"[\" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)\n   \"]\" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)\n   \"4\" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)\n   \"5\" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)\n   \"H\" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)\n   \"W\" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)\n   \"D\" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)\n   \"j\" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)\n   \"8\" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)\n   \"V\" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)\n   \"C\" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)\n   \"U\" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)\n   \"k\" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)\n   \"K\" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)\n   \"p\" 8 bit conditional branch address (MIPS16OP_*_IMM8)\n   \"q\" 11 bit branch address (MIPS16OP_*_IMM11)\n   \"A\" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)\n   \"B\" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)\n   \"E\" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)\n   \"m\" 7 bit register list for save instruction (18 bit extended)\n   \"M\" 7 bit register list for restore instruction (18 bit extended)\n  */\n\n/* Save/restore encoding for the args field when all 4 registers are\n   either saved as arguments or saved/restored as statics.  */\n#define MIPS16_ALL_ARGS    0xe\n#define MIPS16_ALL_STATICS 0xb\n\n/* For the mips16, we use the same opcode table format and a few of\n   the same flags.  However, most of the flags are different.  */\n\n/* Modifies the register in MIPS16OP_*_RX.  */\n#define MIPS16_INSN_WRITE_X\t\t    0x00000001\n/* Modifies the register in MIPS16OP_*_RY.  */\n#define MIPS16_INSN_WRITE_Y\t\t    0x00000002\n/* Modifies the register in MIPS16OP_*_RZ.  */\n#define MIPS16_INSN_WRITE_Z\t\t    0x00000004\n/* Modifies the T ($24) register.  */\n#define MIPS16_INSN_WRITE_T\t\t    0x00000008\n/* Modifies the SP ($29) register.  */\n#define MIPS16_INSN_WRITE_SP\t\t    0x00000010\n/* Modifies the RA ($31) register.  */\n#define MIPS16_INSN_WRITE_31\t\t    0x00000020\n/* Modifies the general purpose register in MIPS16OP_*_REG32R.  */\n#define MIPS16_INSN_WRITE_GPR_Y\t\t    0x00000040\n/* Reads the register in MIPS16OP_*_RX.  */\n#define MIPS16_INSN_READ_X\t\t    0x00000080\n/* Reads the register in MIPS16OP_*_RY.  */\n#define MIPS16_INSN_READ_Y\t\t    0x00000100\n/* Reads the register in MIPS16OP_*_MOVE32Z.  */\n#define MIPS16_INSN_READ_Z\t\t    0x00000200\n/* Reads the T ($24) register.  */\n#define MIPS16_INSN_READ_T\t\t    0x00000400\n/* Reads the SP ($29) register.  */\n#define MIPS16_INSN_READ_SP\t\t    0x00000800\n/* Reads the RA ($31) register.  */\n#define MIPS16_INSN_READ_31\t\t    0x00001000\n/* Reads the program counter.  */\n#define MIPS16_INSN_READ_PC\t\t    0x00002000\n/* Reads the general purpose register in MIPS16OP_*_REGR32.  */\n#define MIPS16_INSN_READ_GPR_X\t\t    0x00004000\n/* Is an unconditional branch insn. */\n#define MIPS16_INSN_UNCOND_BRANCH\t    0x00008000\n/* Is a conditional branch insn. */\n#define MIPS16_INSN_COND_BRANCH\t\t    0x00010000\n\n/* The following flags have the same value for the mips16 opcode\n   table:\n   INSN_UNCOND_BRANCH_DELAY\n   INSN_COND_BRANCH_DELAY\n   INSN_COND_BRANCH_LIKELY (never used)\n   INSN_READ_HI\n   INSN_READ_LO\n   INSN_WRITE_HI\n   INSN_WRITE_LO\n   INSN_TRAP\n   INSN_ISA3\n   */\n\n/* A NOP insn impemented as \"or at,at,zero\".\n   Used to implement -mfix-loongson2f.  */\n#define LOONGSON2F_NOP_INSN\t0x00200825\n\n#endif /* _MIPS_H_ */\n"
  },
  {
    "path": "tools/virtualmips/mips.c",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)\n *\n */\n\n /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <string.h>\n#include <libelf.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <fcntl.h>\n\n#include \"mips_memory.h\"\n#include \"mips_exec.h\"\n#include \"mips.h\"\n#include \"vm.h\"\n#include \"utils.h\"\n#include \"system.h\"\n#include \"mips_cp0.h\"\n#include \"mips_jit.h\"\n\n#define GDB_SR      32\n#define GDB_LO      33\n#define GDB_HI      34\n#define GDB_BAD     35\n#define GDB_CAUSE   36\n#define GDB_PC      37\n\n/* MIPS general purpose registers names */\nchar *mips_gpr_reg_names[MIPS64_GPR_NR] = {\n    \"zr\", \"at\", \"v0\", \"v1\", \"a0\", \"a1\", \"a2\", \"a3\",\n    \"t0\", \"t1\", \"t2\", \"t3\", \"t4\", \"t5\", \"t6\", \"t7\",\n    \"s0\", \"s1\", \"s2\", \"s3\", \"s4\", \"s5\", \"s6\", \"s7\",\n    \"t8\", \"t9\", \"k0\", \"k1\", \"gp\", \"sp\", \"fp\", \"ra\",\n};\n\n/* Cacheability and Coherency Attribute */\nstatic int cca_cache_status[8] = {\n    1, 1, 0, 1, 0, 1, 0, 0,\n};\n\n/* Exception vectors. */\n#define VECTOR_TLB_REFILL   0x000\n#define VECTOR_GENERIC      0x180\n#define VECTOR_INTERRUPT    0x200\n\n/* Get register index given its name */\nint mips_get_reg_index (char *name)\n{\n    int i;\n\n    for (i = 0; i < MIPS64_GPR_NR; i++)\n        if (!strcmp (mips_gpr_reg_names[i], name))\n            return (i);\n\n    return (-1);\n}\n\n/* Get cacheability info */\nint mips_cca_cached (m_uint8_t val)\n{\n    return (cca_cache_status[val & 0x03]);\n}\n\n/* Set a register */\nvoid mips_reg_set (cpu_mips_t * cpu, u_int reg, m_reg_t val)\n{\n    if (reg == 0 || reg >= MIPS64_GPR_NR)\n        return;\n    cpu->gpr[reg] = val;\n\n    if (cpu->vm->debug_level > 2 || (cpu->vm->debug_level > 1 &&\n        (cpu->cp0.reg[MIPS_CP0_STATUS] & MIPS_CP0_STATUS_UM) &&\n        ! (cpu->cp0.reg[MIPS_CP0_STATUS] & MIPS_CP0_STATUS_EXL)))\n    {\n        /* Print GPR values in user mode. */\n        printf (\"        $%d := %08x \\n\", reg, val);\n    }\n}\n\n/*get register value giving index. For GDB*/\nint mips_reg_get (cpu_mips_t * cpu, u_int reg, m_reg_t * val)\n{\n    if (reg < MIPS64_GPR_NR) {\n        *val = cpu->gpr[reg];\n        return SUCCESS;\n    } else {\n        switch (reg) {\n        case GDB_SR:\n            *val = cpu->cp0.reg[MIPS_CP0_STATUS];\n            break;\n        case GDB_LO:\n            *val = cpu->lo;\n            break;\n        case GDB_HI:\n            *val = cpu->hi;\n            break;\n        case GDB_BAD:\n            *val = cpu->cp0.reg[MIPS_CP0_BADVADDR];\n            break;\n        case GDB_CAUSE:\n            *val = cpu->cp0.reg[MIPS_CP0_CAUSE];\n            break;\n        case GDB_PC:\n            *val = cpu->pc;\n            break;\n        default:\n            return FAILURE;\n        }\n\n    }\n\n    return SUCCESS;\n\n}\n\n/* Delete a MIPS64 processor */\nvoid mips_delete (cpu_mips_t * cpu)\n{\n    if (cpu) {\n        mips_mem_shutdown (cpu);\n    }\n}\n\n/* Reset a MIPS64 CPU */\nint mips_reset (cpu_mips_t * cpu)\n{\n    cpu->cp0.reg[MIPS_CP0_STATUS] = MIPS_CP0_STATUS_BEV;\n    cpu->cp0.reg[MIPS_CP0_CAUSE] = 0;\n    cpu->cp0.ebase_reg = 0x80000000;\n\n    /* Clear the complete TLB */\n    memset (&cpu->cp0.tlb, 0, MIPS64_TLB_MAX_ENTRIES * sizeof (tlb_entry_t));\n\n    /* Restart the MTS subsystem */\n    mips_set_addr_mode (cpu, 32 /*64 */ );      /* zzz */\n    cpu->mts_rebuild (cpu);\n\n    /* Flush JIT structures */\n    //mips_jit_flush(cpu,0);\n    return (0);\n}\n\n/* Initialize a MIPS64 processor */\nint mips_init (cpu_mips_t * cpu)\n{\n    /* Set the CPU methods */\n    cpu->reg_get = (void *) mips_reg_get;\n    cpu->reg_set = (void *) mips_reg_set;\n\n    /* Set the startup parameters */\n    mips_reset (cpu);\n    return (0);\n}\n\n/* Load an ELF image into the simulated memory. Using libelf*/\nint mips_load_elf_image (cpu_mips_t * cpu, char *filename,\n    m_va_t * entry_point)\n{\n    m_va_t vaddr;\n    m_uint32_t remain;\n    void *haddr;\n    Elf32_Ehdr *ehdr;\n    Elf32_Shdr *shdr;\n    Elf_Scn *scn;\n    Elf *img_elf;\n    size_t len, clen;\n    int i, fd;\n    FILE *bfd;\n\n    if (! filename)\n        return (-1);\n\n#ifdef __CYGWIN__\n    fd = open (filename, O_RDONLY | O_BINARY);\n#else\n    fd = open (filename, O_RDONLY);\n#endif\n    printf (\"Loading ELF file '%s'...\\n\", filename);\n    if (fd == -1) {\n        perror (\"load_elf_image: open\");\n        return (-1);\n    }\n\n    if (elf_version (EV_CURRENT) == EV_NONE) {\n        fprintf (stderr, \"load_elf_image: library out of date\\n\");\n        return (-1);\n    }\n\n    if (!(img_elf = elf_begin (fd, ELF_C_READ, NULL))) {\n        fprintf (stderr, \"load_elf_image: elf_begin: %s\\n\",\n            elf_errmsg (elf_errno ()));\n        return (-1);\n    }\n\n    if (!(ehdr = elf32_getehdr (img_elf))) {\n        fprintf (stderr, \"load_elf_image: invalid ELF file\\n\");\n        return (-1);\n    }\n\n    bfd = fdopen (fd, \"rb\");\n\n    if (!bfd) {\n        perror (\"load_elf_image: fdopen\");\n        return (-1);\n    }\n// if (!skip_load) {\n    for (i = 0; i < ehdr->e_shnum; i++) {\n        scn = elf_getscn (img_elf, i);\n\n        shdr = elf32_getshdr (scn);\n        len = shdr->sh_size;\n\n        if (!(shdr->sh_flags & SHF_ALLOC) || !len)\n            continue;\n\n        fseek (bfd, shdr->sh_offset, SEEK_SET);\n        vaddr = sign_extend (shdr->sh_addr, 32);\n\n        if (cpu->vm->debug_level > 0) {\n            printf (\"   * Adding section at virtual address 0x%8.8\" LL \"x \"\n                \"(len=0x%8.8lx)\\n\", vaddr & 0xFFFFFFFF, (u_long) len);\n        }\n\n        while (len > 0) {\n            haddr = cpu->mem_op_lookup (cpu, vaddr);\n\n            if (!haddr) {\n                fprintf (stderr,\n                    \"load_elf_image: invalid load address 0x%\" LL \"x\\n\",\n                    vaddr);\n                return (-1);\n            }\n\n            if (len > MIPS_MIN_PAGE_SIZE)\n                clen = MIPS_MIN_PAGE_SIZE;\n            else\n                clen = len;\n\n            remain = MIPS_MIN_PAGE_SIZE;\n            remain -= (vaddr - (vaddr & MIPS_MIN_PAGE_SIZE));\n\n            clen = m_min (clen, remain);\n\n            if (fread ((u_char *) haddr, clen, 1, bfd) < 1)\n                break;\n\n            vaddr += clen;\n            len -= clen;\n        }\n    }\n\n    printf (\"ELF entry point: 0x%x\\n\", ehdr->e_entry);\n\n    if (entry_point)\n        *entry_point = ehdr->e_entry;\n\n    elf_end (img_elf);\n    fclose (bfd);\n    return (0);\n}\n\n/* Update the IRQ flag (inline) */\nstatic forced_inline fastcall int mips_update_irq_flag_fast (cpu_mips_t *\n    cpu)\n{\n    mips_cp0_t *cp0 = &cpu->cp0;\n    m_uint32_t cause;\n    cpu->irq_pending = FALSE;\n\n    cause = cp0->reg[MIPS_CP0_CAUSE] & ~MIPS_CP0_CAUSE_IMASK;\n    cp0->reg[MIPS_CP0_CAUSE] = cause | cpu->irq_cause;\n\n/*printf (\"(%08x-%08x) \", cpu->pc, cp0->reg[MIPS_CP0_STATUS]); fflush (stdout);*/\n    if ((cp0->reg[MIPS_CP0_STATUS] & (MIPS_CP0_STATUS_IE |\n        MIPS_CP0_STATUS_EXL | MIPS_CP0_STATUS_ERL)) == MIPS_CP0_STATUS_IE) {\n#ifdef SIM_PIC32\n        m_uint32_t current_ipl = cp0->reg[MIPS_CP0_STATUS] >> 10 & 63;\n        m_uint32_t requested_ipl = cp0->reg[MIPS_CP0_CAUSE] >> 10 & 63;\n/*printf (\"(%d-%d) \", requested_ipl, current_ipl); fflush (stdout);*/\n        if (unlikely (requested_ipl > current_ipl)) {\n            cpu->irq_pending = TRUE;\n            return (TRUE);\n        }\n#else\n        m_uint32_t imask = cp0->reg[MIPS_CP0_STATUS] & MIPS_CP0_STATUS_IMASK;\n        if (unlikely (cp0->reg[MIPS_CP0_CAUSE] & imask)) {\n            cpu->irq_pending = TRUE;\n            return (TRUE);\n        }\n#endif\n    }\n    return (FALSE);\n}\n\n/* Update the IRQ flag */\nint fastcall mips_update_irq_flag (cpu_mips_t * cpu)\n{\n    return mips_update_irq_flag_fast (cpu);\n}\n\n#if SIM_PIC32\nstatic void print_arg (int val) {\n    if (val & 0xff000000)\n        printf (\"%08x\", val);\n    else\n        printf (\"%u\", val);\n}\n\nstatic void print_args (int narg, int arg0, int arg1, int arg2, int arg3, int arg4, int arg5)\n{\n    print_arg (arg0);\n    if (narg > 1) { printf (\", \"); print_arg (arg1); }\n    if (narg > 2) { printf (\", \"); print_arg (arg2); }\n    if (narg > 3) { printf (\", \"); print_arg (arg3); }\n    if (narg > 4) { printf (\", \"); print_arg (arg4); }\n    if (narg > 5) { printf (\", \"); print_arg (arg5); }\n}\n\n/*\n * Print trace information for exception.\n * For syscalls, display name and arguments.\n */\nstatic void print_exception (cpu_mips_t * cpu, u_int exc_code)\n{\n\tconst char *code = 0;\n#include \"bsd_syscalls.h\"\n\n\tif (exc_code == MIPS_CP0_CAUSE_SYSCALL) {\n\t    mips_insn_t code;\n\n        if (mips_fetch_instruction (cpu, cpu->pc, &code) != 0) {\n            printf (\"--- syscall at %08x: cannot fetch instruction opcode\\n\", cpu->pc);\n            return;\n        }\n        /* bottom 8 bits are index */\n\t\tcode = (code >> 6) & 0377;\nif (code == 97) cpu->vm->debug_level = 2;\nif (code == 1) cpu->vm->debug_level = 1;\n        cpu->trace_syscall = code;\n\t\tif (code >= sizeof (bsd_syscalls) / sizeof (bsd_syscalls[0])) {\n            printf (\"--- syscall: #%d at %08x\\n\", (int)code, cpu->pc);\n            return;\n\t\t}\n        printf (\"--- syscall: %s (\", bsd_syscalls[code].name);\n        if (bsd_syscalls[code].narg > 0) {\n            m_reg_t arg4 = 0, arg5 = 0;\n            void *haddr;\n            u_int exc;\n            m_uint8_t has_set_value;\n\n            if (bsd_syscalls[code].narg >= 4) {\n                has_set_value = FALSE;\n                haddr = mips_mts32_access (cpu, cpu->gpr[MIPS_GPR_SP] + 16,\n                    MIPS_MEMOP_LW, 4, MTS_READ, &arg4, &exc, &has_set_value, 0);\n                if (exc || (! haddr && ! has_set_value))\n                    arg4 = 0;\n                else if (! has_set_value)\n                    arg4 = vmtoh32 (*(m_uint32_t *) haddr);\n            }\n            if (bsd_syscalls[code].narg >= 5) {\n                has_set_value = FALSE;\n                haddr = mips_mts32_access (cpu, cpu->gpr[MIPS_GPR_SP] + 20,\n                    MIPS_MEMOP_LW, 4, MTS_READ, &arg5, &exc, &has_set_value, 0);\n                if (exc || (! haddr && ! has_set_value))\n                    arg5 = 0;\n                else if (! has_set_value)\n                    arg5 = vmtoh32 (*(m_uint32_t *) haddr);\n            }\n            print_args (bsd_syscalls[code].narg,\n                cpu->gpr[MIPS_GPR_A0], cpu->gpr[MIPS_GPR_A1],\n                cpu->gpr[MIPS_GPR_A2], cpu->gpr[MIPS_GPR_A3], arg4, arg5);\n        }\n        printf (\") at %08x\\n\", cpu->pc);\n\t    return;\n\t}\n    printf (\"--- %08x: exception \", cpu->pc);\n\n\tswitch (exc_code) {\n\tcase MIPS_CP0_CAUSE_INTERRUPT:\tcode = \"Interrupt\"; break;\n\tcase MIPS_CP0_CAUSE_ADDR_LOAD:\tcode = \"Address Load\"; break;\n\tcase MIPS_CP0_CAUSE_ADDR_SAVE:\tcode = \"Address Save\"; break;\n\tcase MIPS_CP0_CAUSE_BUS_INSTR:\tcode = \"Bus fetch\"; break;\n\tcase MIPS_CP0_CAUSE_BUS_DATA:\tcode = \"Bus load/store\"; break;\n\tcase MIPS_CP0_CAUSE_SYSCALL:\tcode = \"Syscall\"; break;\n\tcase MIPS_CP0_CAUSE_BP:         code = \"Breakpoint\"; break;\n\tcase MIPS_CP0_CAUSE_ILLOP:      code = \"Reserved Instruction\"; break;\n\tcase MIPS_CP0_CAUSE_CP_UNUSABLE:code = \"Coprocessor Unusable\"; break;\n\tcase MIPS_CP0_CAUSE_OVFLW:      code = \"Arithmetic Overflow\"; break;\n\tcase MIPS_CP0_CAUSE_TRAP:       code = \"Trap\"; break;\n\t}\n\tif (code)\n\t\tprintf (\"'%s'\\n\", code);\n\telse\n\t\tprintf (\"%d\\n\", exc_code);\n\n\tprintf (\"        c0_status = %08x\\n\", cpu->cp0.reg[MIPS_CP0_STATUS]);\n\tprintf (\"        c0_cause = %08x\\n\", cpu->cp0.reg[MIPS_CP0_CAUSE]);\n\tprintf (\"        c0_epc = %08x\\n\", cpu->cp0.reg[MIPS_CP0_EPC]);\n\tswitch (exc_code) {\n    case MIPS_CP0_CAUSE_TLB_MOD:\n    case MIPS_CP0_CAUSE_TLB_LOAD:\n    case MIPS_CP0_CAUSE_TLB_SAVE:\n\tcase MIPS_CP0_CAUSE_ADDR_LOAD:\n\tcase MIPS_CP0_CAUSE_ADDR_SAVE:\n        printf (\"        c0_badvaddr = %08x\\n\", cpu->cp0.reg[MIPS_CP0_BADVADDR]);\n        break;\n    }\n}\n#endif\n\n/* Generate an exception */\nvoid mips_trigger_exception (cpu_mips_t * cpu, u_int exc_code, int bd_slot)\n{\n    mips_cp0_t *cp0 = &cpu->cp0;\n    m_uint64_t new_pc;\n    m_uint32_t old_status = cp0->reg[MIPS_CP0_STATUS];\n    m_reg_t cause;\n\n    /* keep IM, set exception code and bd slot */\n    cause = cp0->reg[MIPS_CP0_CAUSE];\n\n    /* If EXL is set, neither EPC nor Cause.BD are modified. */\n    if (! (old_status & MIPS_CP0_STATUS_EXL)) {\n        cp0->reg[MIPS_CP0_EPC] = cpu->pc | cpu->is_mips16e;\n\n        /* Update Cause.BD */\n        if (bd_slot)\n            cause |= MIPS_CP0_CAUSE_BD_SLOT;\n        else\n            cause &= ~MIPS_CP0_CAUSE_BD_SLOT;\n    }\n\n    cpu->is_mips16e = 0;\n    cause &= ~MIPS_CP0_CAUSE_EXC_MASK;  //clear exec-code\n    cause |= (exc_code << 2);\n    cp0->reg[MIPS_CP0_CAUSE] = cause;\n    if (exc_code == MIPS_CP0_CAUSE_INTERRUPT)\n        cpu->irq_cause = 0;\n\n    /* Set EXL bit in status register */\n    /*TODO: RESET SOFT RESET AND NMI EXCEPTION */\n    cp0->reg[MIPS_CP0_STATUS] |= MIPS_CP0_STATUS_EXL;\n\n    /* clear ERL bit in status register */\n    /*TODO: RESET SOFT RESET AND NMI EXCEPTION */\n    cp0->reg[MIPS_CP0_STATUS] &= ~MIPS_CP0_STATUS_ERL;\n\n    /* Compute the vector address. */\n    if (cp0->reg[MIPS_CP0_STATUS] & MIPS_CP0_STATUS_BEV) {\n        /* Boot exception vector. */\n        new_pc = 0xffffffffbfc00200ULL + VECTOR_GENERIC;\n    } else {\n        /* Use EBase register value. */\n        new_pc = cp0->ebase_reg + VECTOR_GENERIC;\n    }\n    if (! (old_status & MIPS_CP0_STATUS_EXL)) {\n        if (exc_code == MIPS_CP0_CAUSE_TLB_LOAD ||\n            exc_code == MIPS_CP0_CAUSE_TLB_SAVE)\n        {\n            /* TBL refill: use offset 0. */\n            new_pc += VECTOR_TLB_REFILL - VECTOR_GENERIC;\n\n        } else if (exc_code == MIPS_CP0_CAUSE_INTERRUPT &&\n                   (cp0->reg[MIPS_CP0_CAUSE] & MIPS_CP0_CAUSE_IV))\n        {\n            /* Interrupt: use offset 0x200. */\n            new_pc += VECTOR_INTERRUPT - VECTOR_GENERIC;\n        }\n    }\n\n    if (cpu->vm->debug_level > 2 ||\n        (exc_code != MIPS_CP0_CAUSE_INTERRUPT &&\n         (exc_code != MIPS_CP0_CAUSE_SYSCALL ||\n          cpu->vm->debug_level > 0))) {\n        print_exception (cpu, exc_code);\n    }\n\n    cpu->pc = (m_va_t) new_pc;\n\n    /* Clear the pending IRQ flag */\n    cpu->irq_pending = 0;\n}\n\n/*\n * Generate a Debug exception\n */\nvoid mips_trigger_debug_exception (cpu_mips_t *cpu, u_int dexc_type)\n{\n    mips_cp0_t *cp0 = &cpu->cp0;\n    int old_dm = cpu->cp0.reg[MIPS_CP0_DEBUG] & MIPS_CP0_DEBUG_DM;\n\n    /* Update exception type bits. */\n    cpu->cp0.reg[MIPS_CP0_DEBUG] &= ~(MIPS_CP0_DEBUG_DSS |\n        MIPS_CP0_DEBUG_DBP | MIPS_CP0_DEBUG_DDBL |\n        MIPS_CP0_DEBUG_DDBS | MIPS_CP0_DEBUG_DIB |\n        MIPS_CP0_DEBUG_DINT | MIPS_CP0_DEBUG_DDBLIMPR |\n        MIPS_CP0_DEBUG_DDBSIMPR | MIPS_CP0_DEBUG_DEXCCODE);\n    cpu->cp0.reg[MIPS_CP0_DEBUG] |= dexc_type;\n\n    /* Update delay slot flag. */\n    if (cpu->is_in_bdslot)\n        cpu->cp0.reg[MIPS_CP0_DEBUG] |= MIPS_CP0_DEBUG_DBD;\n    else\n        cpu->cp0.reg[MIPS_CP0_DEBUG] &= ~MIPS_CP0_DEBUG_DBD;\n\n    /* Set Debug mode. */\n    cpu->cp0.reg[MIPS_CP0_DEBUG] |= MIPS_CP0_DEBUG_DM;\n    cpu->cp0.reg[MIPS_CP0_DEBUG] |= MIPS_CP0_DEBUG_IEXI;\n\n    /* Set DEPC. */\n    cp0->reg[MIPS_CP0_DEPC] = cpu->pc | cpu->is_mips16e;\n\n    if (cpu->vm->debug_level > 2) {\n        char *type = 0;\n        printf (\"--- 0x%08x: \", cpu->pc);\n\n        if (old_dm)\n            type = \" Debug exception in Debug mode\";\n        else\n            switch (dexc_type) {\n            case MIPS_CP0_DEBUG_DSS:      type = \"Debug Single Step exception\"; break;\n            case MIPS_CP0_DEBUG_DBP:      type = \"Debug Breakpoint exception\"; break;\n            case MIPS_CP0_DEBUG_DDBL:     type = \"Debug Data Break Load exception\"; break;\n            case MIPS_CP0_DEBUG_DDBS:     type = \"Debug Data Break Store exception\"; break;\n            case MIPS_CP0_DEBUG_DIB:      type = \"Debug Instruction Break exception\"; break;\n            case MIPS_CP0_DEBUG_DINT:     type = \"Debug Interrupt exception\"; break;\n            case MIPS_CP0_DEBUG_DDBLIMPR: type = \"Debug Data Break Load Impresize exception\"; break;\n            case MIPS_CP0_DEBUG_DDBSIMPR: type = \"Debug Data Break Store Impresize exception\"; break;\n            }\n        if (type)\n            printf (\"%s\\n\", type);\n        else\n            printf (\"Debug exception %#x\\n\", dexc_type);\n\n        printf (\"        c0_debug := %08x\\n\", cpu->cp0.reg[MIPS_CP0_DEBUG]);\n        printf (\"        c0_depc := %08x\\n\", cpu->cp0.reg[MIPS_CP0_DEPC]);\n    }\n\n    /* Jump to Debug exception vector. */\n    cpu->pc = (m_va_t) 0xffffffffbfc00480ULL;\n    cpu->is_mips16e = 0;\n\n    /* Clear the pending IRQ flag */\n    cpu->irq_pending = 0;\n}\n\n/* Execute fpu instruction */\nvoid fastcall mips_exec_soft_fpu (cpu_mips_t * cpu)\n{\n    mips_cp0_t *cp0 = &cpu->cp0;\n    cp0->reg[MIPS_CP0_CAUSE] |= 0x10000000;     //CE=1\n    mips_trigger_exception (cpu, MIPS_CP0_CAUSE_CP_UNUSABLE,\n        cpu->is_in_bdslot);\n}\n\n/* Execute ERET instruction */\nvoid fastcall mips_exec_eret (cpu_mips_t * cpu)\n{\n    mips_cp0_t *cp0 = &cpu->cp0;\n\n    if (cp0->reg[MIPS_CP0_STATUS] & MIPS_CP0_STATUS_ERL) {\n        cp0->reg[MIPS_CP0_STATUS] &= ~MIPS_CP0_STATUS_ERL;\n        cpu->pc = cp0->reg[MIPS_CP0_ERR_EPC];\n    } else {\n        cp0->reg[MIPS_CP0_STATUS] &= ~MIPS_CP0_STATUS_EXL;\n        cpu->pc = cp0->reg[MIPS_CP0_EPC];\n    }\n    if (cpu->vm->debug_level > 2) {\n        printf (\"        c0_status := %08x\\n\", cpu->cp0.reg[MIPS_CP0_STATUS]);\n    }\n\n    /* We have to clear the LLbit */\n    cpu->ll_bit = 0;\n\n    cpu->is_mips16e = cpu->pc & 1;\n    cpu->pc &= ~1;\n}\n\n/* Execute DERET instruction */\nvoid fastcall mips_exec_deret (cpu_mips_t *cpu)\n{\n    mips_cp0_t *cp0 = &cpu->cp0;\n\n    /* Clear Debug mode. */\n    cpu->cp0.reg[MIPS_CP0_DEBUG] &= ~MIPS_CP0_DEBUG_DM;\n    cpu->cp0.reg[MIPS_CP0_DEBUG] &= ~MIPS_CP0_DEBUG_IEXI;\n\n    /* Restore PC. */\n    cpu->pc = cp0->reg[MIPS_CP0_DEPC];\n\n    cpu->is_mips16e = cpu->pc & 1;\n    cpu->pc &= ~1;\n\n    if (cpu->vm->debug_level > 2) {\n        printf (\"        c0_debug := %08x\\n\", cpu->cp0.reg[MIPS_CP0_DEBUG]);\n    }\n}\n\n/* Execute BREAK instruction */\nvoid fastcall mips_exec_break (cpu_mips_t * cpu, u_int code)\n{\n    mips_trigger_exception (cpu, MIPS_CP0_CAUSE_BP, cpu->is_in_bdslot);\n}\n\n/* Trigger a Trap Exception */\nvoid fastcall mips_trigger_trap_exception (cpu_mips_t * cpu)\n{\n    //printf (\"MIPS64: TRAP exception, CPU=%p\\n\", cpu);\n    mips_trigger_exception (cpu, MIPS_CP0_CAUSE_TRAP, cpu->is_in_bdslot);\n}\n\n/* Execute SYSCALL instruction */\nvoid fastcall mips_exec_syscall (cpu_mips_t * cpu)\n{\n#if DEBUG_SYSCALL\n    printf (\"MIPS: SYSCALL at PC=0x%\" LL \"x (RA=0x%\" LL \"x)\\n\"\n        \"   a0=0x%\" LL \"x, a1=0x%\" LL \"x, a2=0x%\" LL \"x, a3=0x%\" LL \"x\\n\",\n        cpu->pc, cpu->gpr[MIPS_GPR_RA],\n        cpu->gpr[MIPS_GPR_A0], cpu->gpr[MIPS_GPR_A1], cpu->gpr[MIPS_GPR_A2],\n        cpu->gpr[MIPS_GPR_A3]);\n#endif\n\n    if (cpu->is_in_bdslot == 0)\n        mips_trigger_exception (cpu, MIPS_CP0_CAUSE_SYSCALL, 0);\n    else\n        mips_trigger_exception (cpu, MIPS_CP0_CAUSE_SYSCALL, 1);\n}\n\n/* Trigger IRQs */\nvoid forced_inline fastcall mips_trigger_irq (cpu_mips_t * cpu)\n{\n    if (mips_update_irq_flag (cpu))\n        mips_trigger_exception (cpu, MIPS_CP0_CAUSE_INTERRUPT, 0);\n}\n\n/* Set an IRQ */\nvoid mips_set_irq (cpu_mips_t * cpu, m_uint8_t irq)\n{\n    m_uint32_t m;\n    m = (1 << (irq + MIPS_CP0_CAUSE_ISHIFT)) & MIPS_CP0_CAUSE_IMASK;\n    //atomic_or(&cpu->irq_cause,m);\n    cpu->irq_cause |= m;\n}\n\n/* Clear an IRQ */\nvoid mips_clear_irq (cpu_mips_t * cpu, m_uint8_t irq)\n{\n    m_uint32_t m;\n\n    m = (1 << (irq + MIPS_CP0_CAUSE_ISHIFT)) & MIPS_CP0_CAUSE_IMASK;\n    cpu->irq_cause &= ~m;\n    //atomic_and(&cpu->irq_cause,~m);\n\n    if (! cpu->irq_cause)\n        cpu->irq_pending = 0;\n}\n"
  },
  {
    "path": "tools/virtualmips/mips.h",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)\n *\n */\n /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#ifndef __MIPS_H__\n#define __MIPS_H__\n\n#include <pthread.h>\n\n#include \"system.h\"\n#include \"utils.h\"\n\n/*\n * MIPS General Purpose Registers\n */\n#define MIPS_GPR_ZERO        0  /*  zero  */\n#define MIPS_GPR_AT          1  /*  at  */\n#define MIPS_GPR_V0          2  /*  v0  */\n#define MIPS_GPR_V1          3  /*  v1  */\n#define MIPS_GPR_A0          4  /*  a0  */\n#define MIPS_GPR_A1          5  /*  a1  */\n#define MIPS_GPR_A2          6  /*  a2  */\n#define MIPS_GPR_A3          7  /*  a3  */\n#define MIPS_GPR_T0          8  /*  t0  */\n#define MIPS_GPR_T1          9  /*  t1  */\n#define MIPS_GPR_T2          10 /*  t2  */\n#define MIPS_GPR_T3          11 /*  t3  */\n#define MIPS_GPR_T4          12 /*  t4  */\n#define MIPS_GPR_T5          13 /*  t5  */\n#define MIPS_GPR_T6          14 /*  t6  */\n#define MIPS_GPR_T7          15 /*  t7  */\n#define MIPS_GPR_S0          16 /*  s0  */\n#define MIPS_GPR_S1          17 /*  s1  */\n#define MIPS_GPR_S2          18 /*  s2  */\n#define MIPS_GPR_S3          19 /*  s3  */\n#define MIPS_GPR_S4          20 /*  s4  */\n#define MIPS_GPR_S5          21 /*  s5  */\n#define MIPS_GPR_S6          22 /*  s6  */\n#define MIPS_GPR_S7          23 /*  s7  */\n#define MIPS_GPR_T8          24 /*  t8  */\n#define MIPS_GPR_T9          25 /*  t9  */\n#define MIPS_GPR_K0          26 /*  k0  */\n#define MIPS_GPR_K1          27 /*  k1  */\n#define MIPS_GPR_GP          28 /*  gp  */\n#define MIPS_GPR_SP          29 /*  sp  */\n#define MIPS_GPR_FP          30 /*  fp  */\n#define MIPS_GPR_RA          31 /*  ra  */\n\n/*\n * Coprocessor 0 (System Coprocessor) Register definitions\n */\n#define MIPS_CP0_INDEX       0  /* TLB Index           */\n#define MIPS_CP0_RANDOM      1  /* TLB Random          */\n#define MIPS_CP0_TLB_LO_0    2  /* TLB Entry Lo0       */\n#define MIPS_CP0_TLB_LO_1    3  /* TLB Entry Lo1       */\n#define MIPS_CP0_CONTEXT     4  /* Kernel PTE pointer  */\n#define MIPS_CP0_PAGEMASK    5  /* TLB Page Mask       */\n#define MIPS_CP0_WIRED       6  /* TLB Wired           */\n#define MIPS_CP0_INFO        7  /* Info (RM7000)       */\n#define MIPS_CP0_BADVADDR    8  /* Bad Virtual Address */\n#define MIPS_CP0_COUNT       9  /* Count               */\n#define MIPS_CP0_TLB_HI      10 /* TLB Entry Hi        */\n#define MIPS_CP0_COMPARE     11 /* Timer Compare       */\n#define MIPS_CP0_STATUS      12 /* Status              */\n#define MIPS_CP0_CAUSE       13 /* Cause               */\n#define MIPS_CP0_EPC         14 /* Exception PC        */\n#define MIPS_CP0_PRID        15 /* Proc Rev ID         */\n#define MIPS_CP0_CONFIG      16 /* Configuration       */\n#define MIPS_CP0_LLADDR      17 /* Load/Link address   */\n#define MIPS_CP0_WATCHLO     18 /* Low Watch address   */\n#define MIPS_CP0_WATCHHI     19 /* High Watch address  */\n#define MIPS_CP0_XCONTEXT    20 /* Extended context    */\n#define MIPS_CP0_DEBUG       23 /* Debug               */\n#define MIPS_CP0_DEPC        24 /* DEPC                */\n#define MIPS_CP0_ECC         26 /* ECC and parity      */\n#define MIPS_CP0_CACHERR     27 /* Cache Err/Status    */\n#define MIPS_CP0_TAGLO       28 /* Cache Tag Lo        */\n#define MIPS_CP0_TAGHI       29 /* Cache Tag Hi        */\n#define MIPS_CP0_ERR_EPC     30 /* Error exception PC  */\n\n/*\n * CP0 Status Register\n */\n#define MIPS_CP0_STATUS_CU0         0x10000000\n#define MIPS_CP0_STATUS_CU1         0x20000000\n#define MIPS_CP0_STATUS_CU2         0x40000000\n#define MIPS_CP0_STATUS_BEV         0x00400000\n#define MIPS_CP0_STATUS_TS          0x00200000\n#define MIPS_CP0_STATUS_SR          0x00100000\n#define MIPS_CP0_STATUS_CH          0x00040000\n#define MIPS_CP0_STATUS_CE          0x00020000\n#define MIPS_CP0_STATUS_DE          0x00010000\n#define MIPS_CP0_STATUS_RP          0x08000000\n#define MIPS_CP0_STATUS_FR          0x04000000\n#define MIPS_CP0_STATUS_RE          0x02000000\n#define MIPS_CP0_STATUS_KX          0x00000080\n#define MIPS_CP0_STATUS_SX          0x00000040\n#define MIPS_CP0_STATUS_UX          0x00000020\n#define MIPS_CP0_STATUS_KSU         0x00000018\n#define MIPS_CP0_STATUS_ERL         0x00000004\n#define MIPS_CP0_STATUS_EXL         0x00000002\n#define MIPS_CP0_STATUS_IE          0x00000001\n#define MIPS_CP0_STATUS_IMASK7      0x00008000\n#define MIPS_CP0_STATUS_IMASK6      0x00004000\n#define MIPS_CP0_STATUS_IMASK5      0x00002000\n#define MIPS_CP0_STATUS_IMASK4      0x00001000\n#define MIPS_CP0_STATUS_IMASK3      0x00000800\n#define MIPS_CP0_STATUS_IMASK2      0x00000400\n#define MIPS_CP0_STATUS_IMASK1      0x00000200\n#define MIPS_CP0_STATUS_IMASK0      0x00000100\n\n#define MIPS_CP0_STATUS_DS_MASK     0x00770000\n#define MIPS_CP0_STATUS_CU_MASK     0xF0000000\n#define MIPS_CP0_STATUS_IMASK       0x0000FF00\n\n/* Addressing mode: Kernel, Supervisor and User */\n#define MIPS_CP0_STATUS_KSU_SHIFT   0x03\n#define MIPS_CP0_STATUS_KSU_MASK    0x03\n\n#define MIPS_CP0_STATUS_KM          0x00\n#define MIPS_CP0_STATUS_SM          0x01\n#define MIPS_CP0_STATUS_UM          0x10\n\n/*\n * CP0 Cause register\n */\n#define MIPS_CP0_CAUSE_BD_SLOT      0x80000000\n\n#define MIPS_CP0_CAUSE_MASK         0x0000007C\n#define MIPS_CP0_CAUSE_CEMASK       0x30000000\n#define MIPS_CP0_CAUSE_CESHIFT      28\n#ifdef SIM_PIC32\n#define MIPS_CP0_CAUSE_IMASK        0x0000FC00  /* mips r2 */\n#else\n#define MIPS_CP0_CAUSE_IMASK        0x0000FF00  /* mips r1 */\n#endif\n#define MIPS_CP0_CAUSE_IV           0x00800000\n#define MIPS_CP0_CAUSE_SHIFT        2\n#define MIPS_CP0_CAUSE_CESHIFT      28\n#define MIPS_CP0_CAUSE_ISHIFT       8\n#define MIPS_CP0_CAUSE_EXC_MASK     0x0000007C\n\n#define MIPS_CP0_CAUSE_INTERRUPT    0\n#define MIPS_CP0_CAUSE_TLB_MOD      1\n#define MIPS_CP0_CAUSE_TLB_LOAD     2\n#define MIPS_CP0_CAUSE_TLB_SAVE     3\n#define MIPS_CP0_CAUSE_ADDR_LOAD    4 /* ADEL */\n#define MIPS_CP0_CAUSE_ADDR_SAVE    5 /* ADES */\n#define MIPS_CP0_CAUSE_BUS_INSTR    6\n#define MIPS_CP0_CAUSE_BUS_DATA     7\n#define MIPS_CP0_CAUSE_SYSCALL      8\n#define MIPS_CP0_CAUSE_BP           9\n#define MIPS_CP0_CAUSE_ILLOP        10\n#define MIPS_CP0_CAUSE_CP_UNUSABLE  11\n#define MIPS_CP0_CAUSE_OVFLW        12\n#define MIPS_CP0_CAUSE_TRAP         13\n#define MIPS_CP0_CAUSE_FPE          15\n#define MIPS_CP0_CAUSE_WATCH        23\n\n#define MIPS_CP0_CAUSE_IBIT7        0x00008000\n#define MIPS_CP0_CAUSE_IBIT6        0x00004000\n#define MIPS_CP0_CAUSE_IBIT5        0x00002000\n#define MIPS_CP0_CAUSE_IBIT4        0x00001000\n#define MIPS_CP0_CAUSE_IBIT3        0x00000800\n#define MIPS_CP0_CAUSE_IBIT2        0x00000400\n#define MIPS_CP0_CAUSE_IBIT1        0x00000200\n#define MIPS_CP0_CAUSE_IBIT0        0x00000100\n\n/* cp0 context */\n#define MIPS_CP0_CONTEXT_PTEBASE_MASK  0xff800000\n#define MIPS_CP0_CONTEXT_BADVPN2_MASK  0x0007ffff0\n\n/*\n * CP0 Debug register\n */\n#define MIPS_CP0_DEBUG_DBD          0x80000000  /* Debug exception on delay slot */\n#define MIPS_CP0_DEBUG_DM           0x40000000  /* Debug mode */\n#define MIPS_CP0_DEBUG_IEXI         0x00100000  /* Imprecise Error eXception Inhibit */\n#define MIPS_CP0_DEBUG_DDBSIMPR     0x00080000  /* Debug Data Break Store Impresize exception */\n#define MIPS_CP0_DEBUG_DDBLIMPR     0x00040000  /* Debug Data Break Load Impresize exception */\n#define MIPS_CP0_DEBUG_DEXCCODE     0x00003c00  /* Debug exception code */\n#define MIPS_CP0_DEBUG_DEXCCODE_SHIFT   10\n#define MIPS_CP0_DEBUG_DINT         0x00000020  /* Debug Interrupt exception */\n#define MIPS_CP0_DEBUG_DIB          0x00000010  /* Debug Instruction Break exception */\n#define MIPS_CP0_DEBUG_DDBS         0x00000008  /* Debug Data Break Store exception */\n#define MIPS_CP0_DEBUG_DDBL         0x00000004  /* Debug Data Break Load exception */\n#define MIPS_CP0_DEBUG_DBP          0x00000002  /* Debug Breakpoint exception */\n#define MIPS_CP0_DEBUG_DSS          0x00000001  /* Debug Single Step exception */\n\n#define MIPS_CP0_DEBUG_WMASK        0x10700180  /* Writable bits */\n\n/* TLB masks and shifts */\n#define MIPS_TLB_PAGE_MASK     0x01ffe000\n#define MIPS_TLB_PAGE_SHIFT    13\n//#define MIPS_TLB_VPN2_MASK        0xffffe000\n#define MIPS_TLB_VPN2_MASK_32  0xffffe000\n#define MIPS_TLB_VPN2_MASK_64  0xc00000ffffffe000ULL\n#define MIPS_TLB_PFN_MASK      0x3fffffc0\n#define MIPS_TLB_ASID_MASK     0x000000ff       /* \"asid\" in EntryHi */\n#define MIPS_TLB_G_MASK        0x00001000       /* \"Global\" in EntryHi */\n#define MIPS_TLB_V_MASK        0x2      /* \"Valid\" in EntryLo */\n#define MIPS_TLB_D_MASK        0x4      /* \"Dirty\" in EntryLo */\n#define MIPS_TLB_C_MASK        0x38     /* Page Coherency Attribute */\n#define MIPS_TLB_C_SHIFT       3\n#define MIPS_TLB_V_SHIT          1\n#define MIPS_TLB_D_SHIT          2\n\n#define MIPS_CP0_LO_G_MASK     0x00000001       /* \"Global\" in Lo0/1 reg */\n#define MIPS_CP0_HI_SAFE_MASK  0xffffe0ff       /* Safety mask for Hi reg */\n#define MIPS_CP0_LO_SAFE_MASK  0x7fffffff       /* Safety mask for Lo reg */\n\n/* MIPS \"jr ra\" instruction */\n#define MIPS_INSN_JR_RA        0x03e00008\n\n#ifdef SIM_PIC32\n#define MIPS_MIN_PAGE_SHIFT    8\n#define MIPS_MIN_PAGE_SIZE     (1 << MIPS_MIN_PAGE_SHIFT)\n#define MIPS_MIN_PAGE_IMASK    (MIPS_MIN_PAGE_SIZE - 1)\n#define MIPS_MIN_PAGE_MASK     0xffffffffffffff00ULL\n#else\n/* Minimum page size: 4 Kb */\n#define MIPS_MIN_PAGE_SHIFT    12\n#define MIPS_MIN_PAGE_SIZE     (1 << MIPS_MIN_PAGE_SHIFT)\n#define MIPS_MIN_PAGE_IMASK    (MIPS_MIN_PAGE_SIZE - 1)\n#define MIPS_MIN_PAGE_MASK     0xfffffffffffff000ULL\n#endif\n\n/* Addressing mode: Kernel, Supervisor and User */\n#define MIPS_MODE_KERNEL  00\n\n/* Segments in 32-bit User mode */\n#define MIPS_USEG_BASE    0x00000000\n#define MIPS_USEG_SIZE    0x80000000\n\n/* Segments in 32-bit Supervisor mode */\n#define MIPS_SUSEG_BASE   0x00000000\n#define MIPS_SUSEG_SIZE   0x80000000\n#define MIPS_SSEG_BASE    0xc0000000\n#define MIPS_SSEG_SIZE    0x20000000\n\n/* Segments in 32-bit Kernel mode */\n#define MIPS_KUSEG_BASE   0x00000000\n#define MIPS_KUSEG_SIZE   0x80000000\n\n#define MIPS_KSEG0_BASE   0x80000000\n#define MIPS_KSEG0_SIZE   0x20000000\n\n#define MIPS_KSEG1_BASE   0xa0000000\n#define MIPS_KSEG1_SIZE   0x20000000\n\n#define MIPS_KSSEG_BASE   0xc0000000\n#define MIPS_KSSEG_SIZE   0x20000000\n\n#define MIPS_KSEG3_BASE   0xe0000000\n#define MIPS_KSEG3_SIZE   0x20000000\n\n/* xkphys mask (36-bit physical address) */\n#define MIPS64_XKPHYS_ZONE_MASK    0xF800000000000000ULL\n#define MIPS64_XKPHYS_PHYS_SIZE    (1ULL << 36)\n#define MIPS64_XKPHYS_PHYS_MASK    (MIPS64_XKPHYS_PHYS_SIZE - 1)\n#define MIPS64_XKPHYS_CCA_SHIFT    59\n\n/* Number of GPR (general purpose registers) */\n#define MIPS64_GPR_NR  32\n\n/* Number of registers in CP0 */\n#define MIPS64_CP0_REG_NR   32\n\n/*8 configure register in cp0. sel:0-7*/\n#define MIPS64_CP0_CONFIG_REG_NR  8\n\n/* Number of registers in CP1 */\n#define MIPS64_CP1_REG_NR   32\n\n/* Number of TLB entries */\n#define MIPS64_TLB_STD_ENTRIES  48\n#define MIPS64_TLB_MAX_ENTRIES  64\n#define MIPS64_TLB_IDX_MASK     0x3f    /* 6 bits */\n\n/* Enable the 64 TLB entries for R7000 CPU */\n#define MIPS64_R7000_TLB64_ENABLE   0x20000000\n\n/* Number of instructions per page */\n#define MIPS_INSN_PER_PAGE (MIPS_MIN_PAGE_SIZE/sizeof(mips_insn_t))\n\n/* MIPS CPU Identifiers */\n#define MIPS_PRID_R4600    0x00002012\n#define MIPS_PRID_R4700    0x00002112\n#define MIPS_PRID_R5000    0x00002312\n#define MIPS_PRID_R7000    0x00002721\n#define MIPS_PRID_R527x    0x00002812\n#define MIPS_PRID_BCM1250  0x00040102\n\nenum {\n    MIPS_KUSEG = 0,\n    MIPS_KSEG0,\n    MIPS_KSEG1,\n    MIPS_KSEG2,\n};\n\n/* Memory operations */\nenum {\n    MIPS_MEMOP_LOOKUP = 0,\n\n    MIPS_MEMOP_LB,\n    MIPS_MEMOP_LBU,\n    MIPS_MEMOP_LH,\n    MIPS_MEMOP_LHU,\n    MIPS_MEMOP_LW,\n    MIPS_MEMOP_LWU,\n    MIPS_MEMOP_LD,\n    MIPS_MEMOP_SB,\n    MIPS_MEMOP_SH,\n    MIPS_MEMOP_SW,\n    MIPS_MEMOP_SD,\n\n    MIPS_MEMOP_LWL,\n    MIPS_MEMOP_LWR,\n    MIPS_MEMOP_LDL,\n    MIPS_MEMOP_LDR,\n    MIPS_MEMOP_SWL,\n    MIPS_MEMOP_SWR,\n    MIPS_MEMOP_SDL,\n    MIPS_MEMOP_SDR,\n\n    MIPS_MEMOP_LL,\n    MIPS_MEMOP_SC,\n\n    MIPS_MEMOP_LDC1,\n    MIPS_MEMOP_SDC1,\n\n    MIPS_MEMOP_CACHE,\n\n    MIPS_MEMOP_MAX,\n};\n\n/* Maximum number of breakpoints */\n#define MIPS64_MAX_BREAKPOINTS  8\n\n#define CPU_INTERRUPT_EXIT   0x01       /* wants exit from main loop */\n#define CPU_INTERRUPT_HARD   0x02       /* hardware interrupt pending */\n#define CPU_INTERRUPT_EXITTB 0x04       /* exit the current TB (use for x86 a20 case) */\n#define CPU_INTERRUPT_TIMER  0x08       /* internal timer exception pending */\n#define CPU_INTERRUPT_FIQ    0x10       /* Fast interrupt pending.  */\n#define CPU_INTERRUPT_HALT   0x20       /* CPU halt wanted */\n#define CPU_INTERRUPT_SMI    0x40       /* (x86 only) SMI interrupt pending */\n\n/* MIPS CPU type */\n//typedef struct cpu_mips cpu_mips_t;\n\n/* Memory operation function prototype */\ntypedef u_int fastcall (*mips_memop_fn) (cpu_mips_t * cpu, m_va_t vaddr,\n    u_int reg);\n\n/* TLB entry definition */\ntypedef struct {\n    m_va_t mask;\n    m_va_t hi;\n    m_va_t lo0;\n    m_va_t lo1;\n} tlb_entry_t;\n\n/* System Coprocessor (CP0) definition */\ntypedef struct {\n    m_cp0_reg_t reg[MIPS64_CP0_REG_NR];\n    /*because configure has sel 0-7, seperate it to reg */\n    m_cp0_reg_t config_reg[MIPS64_CP0_CONFIG_REG_NR];\n    m_cp0_reg_t intctl_reg;\n    m_cp0_reg_t ebase_reg;\n    m_uint8_t config_usable;    /*if configure register sel N is useable, set the bit in config_usable to 1 */\n\n    tlb_entry_t tlb[MIPS64_TLB_MAX_ENTRIES];\n\n    /* Number of TLB entries */\n    u_int tlb_entries;\n\n} mips_cp0_t;\n\n/* mips CPU definition */\nstruct cpu_mips {\n    /* CPU identifier for MP systems */\n    u_int id;\n    u_int type;\n\n    m_va_t pc, ret_pc;\n    m_va_t jit_pc;\n    m_reg_t gpr[MIPS64_GPR_NR];\n    m_reg_t lo, hi;\n    /* VM instance */\n    vm_instance_t *vm;\n    /* Next CPU in group */\n    cpu_mips_t *next;\n    /* System coprocessor (CP0) */\n    mips_cp0_t cp0;\n\n    /* CPU states */\n    volatile m_uint32_t state, prev_state;\n\n    /* Thread running this CPU */\n    pthread_t cpu_thread;\n    int cpu_thread_running;\n\n    /*pause request. INTERRUPT will pause cpu */\n    m_uint32_t pause_request;\n\n    /* Methods */\n    int (*reg_get) (cpu_mips_t * cpu, u_int reg, m_reg_t * val);\n    void (*reg_set) (cpu_mips_t * cpu, u_int reg_index, m_reg_t val);\n    void (*mts_rebuild) (cpu_mips_t * cpu);\n         u_int (*mips_mts_gdb_lb) (cpu_mips_t * cpu, m_va_t vaddr, void *cur);\n\n    /* MTS32/MTS64 caches */\n    union {\n        mts32_entry_t *mts32_cache;\n        mts64_entry_t *mts64_cache;\n    } mts_u;\n\n    /* General Purpose Registers, Pointer Counter, LO/HI, IRQ */\n    m_uint32_t irq_pending, irq_cause, ll_bit;\n\n    /* Virtual address to physical page translation */\n    int (*translate) (cpu_mips_t * cpu, m_va_t vaddr, m_uint32_t * phys_page);\n    /* Memory access functions */\n    mips_memop_fn mem_op_fn[MIPS_MEMOP_MAX];\n    /* Memory lookup function (to load ELF image,...) */\n    void *fastcall (*mem_op_lookup) (cpu_mips_t * cpu, m_va_t vaddr);\n\n    /* Address bus mask for physical addresses */\n    m_va_t addr_bus_mask;\n\n    /* MTS map/unmap/rebuild operations */\n    void (*mts_map) (cpu_mips_t * cpu, m_va_t vaddr, m_pa_t paddr,\n        m_uint32_t len, int cache_access, int tlb_index);\n    void (*mts_unmap) (cpu_mips_t * cpu, m_va_t vaddr, m_uint32_t len,\n        m_uint32_t val, int tlb_index);\n    void (*mts_shutdown) (cpu_mips_t * cpu);\n    /* MTS cache statistics */\n    m_uint64_t mts_misses, mts_lookups;\n\n    /* Address mode (32 or 64 bits) */\n    u_int addr_mode;\n\n    int is_in_bdslot;\n    int insn_len; /* length of last fetched instruction in bytes */\n    int is_mips16e; /* 1 if ISA Mode is MIPS16e, 0 if MIPS32 */\n\n    int trace_syscall;\n    int magic_opcodes;\n\n    /* Current exec page (non-JIT) info */\n    m_va_t njm_exec_page;\n    mips_insn_t *njm_exec_ptr;\n\n#ifdef _USE_JIT_\n    /* JIT flush method */\n    u_int jit_flush_method;\n\n    /* Number of compiled pages */\n    u_int compiled_pages;\n\n    /* Code page translation cache */\n    mips_jit_tcb_t **exec_blk_map;\n    void *exec_page_area;\n    size_t exec_page_area_size; /*M bytes */\n    size_t exec_page_count, exec_page_alloc;\n    insn_exec_page_t *exec_page_free_list;\n    insn_exec_page_t *exec_page_array;\n    /* Current and free lists of translated code blocks */\n    mips_jit_tcb_t *tcb_list, *tcb_last, *tcb_free_list;\n    /* Direct block jump.Optimization */\n    u_int exec_blk_direct_jump;\n\n#endif\n\n};\n\n/* Register names */\nextern char *mips_gpr_reg_names[];\n\n#define MAJOR_OP(_inst) (((uint)_inst >> 26) & 0x3f )\n\nint mips_load_elf_image (cpu_mips_t * cpu, char *filename,\n    m_va_t * entry_point);\n\nint mips_get_reg_index (char *name);\nint mips_cca_cached (m_uint8_t val);\nvoid mips_dump_regs (cpu_mips_t * cpu);\nvoid mips_delete (cpu_mips_t * cpu);\nint mips_reset (cpu_mips_t * cpu);\nint mips_init (cpu_mips_t * cpu);\nint mips_load_elf_image (cpu_mips_t * cpu, char *filename,\n    m_va_t * entry_point);\nvoid mips_delete (cpu_mips_t * cpu);\nint fastcall mips_update_irq_flag (cpu_mips_t * cpu);\nvoid mips_trigger_exception (cpu_mips_t * cpu, u_int exc_code, int bd_slot);\nvoid mips_trigger_debug_exception (cpu_mips_t * cpu, u_int dexc_type);\nvoid fastcall mips_exec_soft_fpu (cpu_mips_t * cpu);\nvoid fastcall mips_exec_eret (cpu_mips_t * cpu);\nvoid fastcall mips_exec_deret (cpu_mips_t * cpu);\nvoid fastcall mips_exec_break (cpu_mips_t * cpu, u_int code);\nvoid fastcall mips_trigger_trap_exception (cpu_mips_t * cpu);\nvoid fastcall mips_exec_syscall (cpu_mips_t * cpu);\nvoid fastcall mips_trigger_irq (cpu_mips_t * cpu);\nvoid mips_set_irq (cpu_mips_t * cpu, m_uint8_t irq);\nvoid mips_clear_irq (cpu_mips_t * cpu, m_uint8_t irq);\n\n/* Control timer interrupt */\nvoid set_timer_irq (cpu_mips_t *cpu);\nvoid clear_timer_irq (cpu_mips_t *cpu);\n\n/*\n * Disassemble and print the instruction mnemonics.\n * Opcode size can be 4 or 2 bytes.\n * Parameter `isa' defines an instruction set architecture:\n *      0 - mips32 encoding\n *      1 - mips16e encoding\n *      2 - micromips encoding (someday)\n */\nvoid print_mips (unsigned memaddr, unsigned int opcode, int nbytes,\n    int isa, FILE *stream);\n\nconst char *cp0reg_name (unsigned cp0reg, unsigned sel);\n\nint mips_fetch_instruction (cpu_mips_t * cpu,\n    m_va_t pc, mips_insn_t * insn);\nvoid *mips_mts32_access (cpu_mips_t * cpu, m_va_t vaddr,\n    u_int op_code, u_int op_size,\n    u_int op_type, m_reg_t * data, u_int * exc, m_uint8_t * has_set_value,\n    u_int is_fromgdb);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/mips16-opc.c",
    "content": "/*\n * This is the opcodes table for the mips16 processor.  The format of\n * this table is intentionally identical to the one in mips-opc.c.\n * However, the special letters that appear in the argument string are\n * different, and the table uses some different flags.\n *\n * Copyright 1996, 1997, 1998, 2000, 2005, 2006, 2007\n * Free Software Foundation, Inc.\n * Contributed by Ian Lance Taylor, Cygnus Support\n * Adapted for VirtualMIPS by Serge Vakulenko.\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n\n/* Use some short hand macros to keep down the length of the lines in\n   the opcodes table.  */\n\n#define UBD     INSN_UNCOND_BRANCH_DELAY\n#define UBR     MIPS16_INSN_UNCOND_BRANCH\n#define CBR     MIPS16_INSN_COND_BRANCH\n\n#define WR_x    MIPS16_INSN_WRITE_X\n#define WR_y    MIPS16_INSN_WRITE_Y\n#define WR_z    MIPS16_INSN_WRITE_Z\n#define WR_T    MIPS16_INSN_WRITE_T\n#define WR_SP   MIPS16_INSN_WRITE_SP\n#define WR_31   MIPS16_INSN_WRITE_31\n#define WR_Y    MIPS16_INSN_WRITE_GPR_Y\n\n#define RD_x    MIPS16_INSN_READ_X\n#define RD_y    MIPS16_INSN_READ_Y\n#define RD_Z    MIPS16_INSN_READ_Z\n#define RD_T    MIPS16_INSN_READ_T\n#define RD_SP   MIPS16_INSN_READ_SP\n#define RD_31   MIPS16_INSN_READ_31\n#define RD_PC   MIPS16_INSN_READ_PC\n#define RD_X    MIPS16_INSN_READ_GPR_X\n\n#define WR_HI   INSN_WRITE_HI\n#define WR_LO   INSN_WRITE_LO\n#define RD_HI   INSN_READ_HI\n#define RD_LO   INSN_READ_LO\n\n#define TRAP    INSN_TRAP\n\nstatic const struct mips_opcode mips16_opcodes[] =\n{\n/* name,    args,       match,  mask,       pinfo */\n{\"nop\",     \"\",         0x6500, 0xffff,     RD_Z, },        /* move $0,$Z */\n{\"la\",      \"x,A\",      0x0800, 0xf800,     WR_x|RD_PC, },\n{\"abs\",     \"x,w\",      0, (int) M_ABS,     INSN_MACRO, },\n{\"addiu\",   \"y,x,4\",    0x4000, 0xf810,     WR_y|RD_x, },\n{\"addiu\",   \"x,k\",      0x4800, 0xf800,     WR_x|RD_x, },\n{\"addiu\",   \"S,K\",      0x6300, 0xff00,     WR_SP|RD_SP, },\n{\"addiu\",   \"S,S,K\",    0x6300, 0xff00,     WR_SP|RD_SP, },\n{\"addiu\",   \"x,P,V\",    0x0800, 0xf800,     WR_x|RD_PC, },\n{\"addiu\",   \"x,S,V\",    0x0000, 0xf800,     WR_x|RD_SP, },\n{\"addu\",    \"z,v,y\",    0xe001, 0xf803,     WR_z|RD_x|RD_y, },\n{\"addu\",    \"y,x,4\",    0x4000, 0xf810,     WR_y|RD_x, },\n{\"addu\",    \"x,k\",      0x4800, 0xf800,     WR_x|RD_x, },\n{\"addu\",    \"S,K\",      0x6300, 0xff00,     WR_SP|RD_SP, },\n{\"addu\",    \"S,S,K\",    0x6300, 0xff00,     WR_SP|RD_SP, },\n{\"addu\",    \"x,P,V\",    0x0800, 0xf800,     WR_x|RD_PC, },\n{\"addu\",    \"x,S,V\",    0x0000, 0xf800,     WR_x|RD_SP, },\n{\"and\",     \"x,y\",      0xe80c, 0xf81f,     WR_x|RD_x|RD_y, },\n{\"b\",       \"q\",        0x1000, 0xf800,     UBR, },\n{\"beq\",     \"x,y,p\",    0, (int) M_BEQ,     INSN_MACRO, },\n{\"beq\",     \"x,U,p\",    0, (int) M_BEQ_I,   INSN_MACRO, },\n{\"beqz\",    \"x,p\",      0x2000, 0xf800,     CBR|RD_x, },\n{\"bge\",     \"x,y,p\",    0, (int) M_BGE,     INSN_MACRO, },\n{\"bge\",     \"x,8,p\",    0, (int) M_BGE_I,   INSN_MACRO, },\n{\"bgeu\",    \"x,y,p\",    0, (int) M_BGEU,    INSN_MACRO, },\n{\"bgeu\",    \"x,8,p\",    0, (int) M_BGEU_I,  INSN_MACRO, },\n{\"bgt\",     \"x,y,p\",    0, (int) M_BGT,     INSN_MACRO, },\n{\"bgt\",     \"x,8,p\",    0, (int) M_BGT_I,   INSN_MACRO, },\n{\"bgtu\",    \"x,y,p\",    0, (int) M_BGTU,    INSN_MACRO, },\n{\"bgtu\",    \"x,8,p\",    0, (int) M_BGTU_I,  INSN_MACRO, },\n{\"ble\",     \"x,y,p\",    0, (int) M_BLE,     INSN_MACRO, },\n{\"ble\",     \"x,8,p\",    0, (int) M_BLE_I,   INSN_MACRO, },\n{\"bleu\",    \"x,y,p\",    0, (int) M_BLEU,    INSN_MACRO, },\n{\"bleu\",    \"x,8,p\",    0, (int) M_BLEU_I,  INSN_MACRO, },\n{\"blt\",     \"x,y,p\",    0, (int) M_BLT,     INSN_MACRO, },\n{\"blt\",     \"x,8,p\",    0, (int) M_BLT_I,   INSN_MACRO, },\n{\"bltu\",    \"x,y,p\",    0, (int) M_BLTU,    INSN_MACRO, },\n{\"bltu\",    \"x,8,p\",    0, (int) M_BLTU_I,  INSN_MACRO, },\n{\"bne\",     \"x,y,p\",    0, (int) M_BNE,     INSN_MACRO, },\n{\"bne\",     \"x,U,p\",    0, (int) M_BNE_I,   INSN_MACRO, },\n{\"bnez\",    \"x,p\",      0x2800, 0xf800,     CBR|RD_x, },\n{\"break\",   \"6\",        0xe805, 0xf81f,     TRAP, },\n{\"bteqz\",   \"p\",        0x6000, 0xff00,     CBR|RD_T, },\n{\"btnez\",   \"p\",        0x6100, 0xff00,     CBR|RD_T, },\n{\"cmpi\",    \"x,U\",      0x7000, 0xf800,     WR_T|RD_x, },\n{\"cmp\",     \"x,y\",      0xe80a, 0xf81f,     WR_T|RD_x|RD_y, },\n{\"cmp\",     \"x,U\",      0x7000, 0xf800,     WR_T|RD_x, },\n{\"dla\",     \"y,E\",      0xfe00, 0xff00,     WR_y|RD_PC, },\n{\"daddiu\",  \"y,x,4\",    0x4010, 0xf810,     WR_y|RD_x, },\n{\"daddiu\",  \"y,j\",      0xfd00, 0xff00,     WR_y|RD_y, },\n{\"daddiu\",  \"S,K\",      0xfb00, 0xff00,     WR_SP|RD_SP, },\n{\"daddiu\",  \"S,S,K\",    0xfb00, 0xff00,     WR_SP|RD_SP, },\n{\"daddiu\",  \"y,P,W\",    0xfe00, 0xff00,     WR_y|RD_PC, },\n{\"daddiu\",  \"y,S,W\",    0xff00, 0xff00,     WR_y|RD_SP, },\n{\"daddu\",   \"z,v,y\",    0xe000, 0xf803,     WR_z|RD_x|RD_y, },\n{\"daddu\",   \"y,x,4\",    0x4010, 0xf810,     WR_y|RD_x, },\n{\"daddu\",   \"y,j\",      0xfd00, 0xff00,     WR_y|RD_y, },\n{\"daddu\",   \"S,K\",      0xfb00, 0xff00,     WR_SP|RD_SP, },\n{\"daddu\",   \"S,S,K\",    0xfb00, 0xff00,     WR_SP|RD_SP, },\n{\"daddu\",   \"y,P,W\",    0xfe00, 0xff00,     WR_y|RD_PC, },\n{\"daddu\",   \"y,S,W\",    0xff00, 0xff00,     WR_y|RD_SP, },\n{\"ddiv\",    \"0,x,y\",    0xe81e, 0xf81f,     RD_x|RD_y|WR_HI|WR_LO,  },\n{\"ddiv\",    \"z,v,y\",    0, (int) M_DDIV_3,  INSN_MACRO, },\n{\"ddivu\",   \"0,x,y\",    0xe81f, 0xf81f,     RD_x|RD_y|WR_HI|WR_LO,  },\n{\"ddivu\",   \"z,v,y\",    0, (int) M_DDIVU_3, INSN_MACRO, },\n{\"div\",     \"0,x,y\",    0xe81a, 0xf81f,     RD_x|RD_y|WR_HI|WR_LO,  },\n{\"div\",     \"z,v,y\",    0, (int) M_DIV_3,   INSN_MACRO, },\n{\"divu\",    \"0,x,y\",    0xe81b, 0xf81f,     RD_x|RD_y|WR_HI|WR_LO,  },\n{\"divu\",    \"z,v,y\",    0, (int) M_DIVU_3,  INSN_MACRO, },\n{\"dmul\",    \"z,v,y\",    0, (int) M_DMUL,    INSN_MACRO, },\n{\"dmult\",   \"x,y\",      0xe81c, 0xf81f,     RD_x|RD_y|WR_HI|WR_LO,  },\n{\"dmultu\",  \"x,y\",      0xe81d, 0xf81f,     RD_x|RD_y|WR_HI|WR_LO,  },\n{\"drem\",    \"0,x,y\",    0xe81e, 0xf81f,     RD_x|RD_y|WR_HI|WR_LO,  },\n{\"drem\",    \"z,v,y\",    0, (int) M_DREM_3,  INSN_MACRO, },\n{\"dremu\",   \"0,x,y\",    0xe81f, 0xf81f,     RD_x|RD_y|WR_HI|WR_LO,  },\n{\"dremu\",   \"z,v,y\",    0, (int) M_DREMU_3, INSN_MACRO, },\n{\"dsllv\",   \"y,x\",      0xe814, 0xf81f,     WR_y|RD_y|RD_x, },\n{\"dsll\",    \"x,w,[\",    0x3001, 0xf803,     WR_x|RD_y, },\n{\"dsll\",    \"y,x\",      0xe814, 0xf81f,     WR_y|RD_y|RD_x, },\n{\"dsrav\",   \"y,x\",      0xe817, 0xf81f,     WR_y|RD_y|RD_x, },\n{\"dsra\",    \"y,]\",      0xe813, 0xf81f,     WR_y|RD_y, },\n{\"dsra\",    \"y,x\",      0xe817, 0xf81f,     WR_y|RD_y|RD_x, },\n{\"dsrlv\",   \"y,x\",      0xe816, 0xf81f,     WR_y|RD_y|RD_x, },\n{\"dsrl\",    \"y,]\",      0xe808, 0xf81f,     WR_y|RD_y, },\n{\"dsrl\",    \"y,x\",      0xe816, 0xf81f,     WR_y|RD_y|RD_x, },\n{\"dsubu\",   \"z,v,y\",    0xe002, 0xf803,     WR_z|RD_x|RD_y, },\n{\"dsubu\",   \"y,x,4\",    0, (int) M_DSUBU_I, INSN_MACRO, },\n{\"dsubu\",   \"y,j\",      0, (int) M_DSUBU_I_2, INSN_MACRO, },\n{\"exit\",    \"L\",        0xed09, 0xff1f,     TRAP, },\n{\"exit\",    \"L\",        0xee09, 0xff1f,     TRAP, },\n{\"exit\",    \"L\",        0xef09, 0xff1f,     TRAP, },\n{\"entry\",   \"l\",        0xe809, 0xf81f,     TRAP, },\n{\"jalr\",    \"x\",        0xe840, 0xf8ff,     UBD|WR_31|RD_x, },\n{\"jalr\",    \"R,x\",      0xe840, 0xf8ff,     UBD|WR_31|RD_x, },\n{\"jal\",     \"x\",        0xe840, 0xf8ff,     UBD|WR_31|RD_x, },\n{\"jal\",     \"R,x\",      0xe840, 0xf8ff,     UBD|WR_31|RD_x, },\n{\"jal\",     \"a\",        0x1800, 0xfc00,     UBD|WR_31, },\n{\"jalx\",    \"a\",        0x1c00, 0xfc00,     UBD|WR_31, },\n{\"jr\",      \"x\",        0xe800, 0xf8ff,     UBD|RD_x, },\n{\"jr\",      \"R\",        0xe820, 0xffff,     UBD|RD_31, },\n{\"j\",       \"x\",        0xe800, 0xf8ff,     UBD|RD_x, },\n{\"j\",       \"R\",        0xe820, 0xffff,     UBD|RD_31, },\n{\"lb\",      \"y,5(x)\",   0x8000, 0xf800,     WR_y|RD_x, },\n{\"lbu\",     \"y,5(x)\",   0xa000, 0xf800,     WR_y|RD_x, },\n{\"ld\",      \"y,D(x)\",   0x3800, 0xf800,     WR_y|RD_x, },\n{\"ld\",      \"y,B\",      0xfc00, 0xff00,     WR_y|RD_PC, },\n{\"ld\",      \"y,D(P)\",   0xfc00, 0xff00,     WR_y|RD_PC, },\n{\"ld\",      \"y,D(S)\",   0xf800, 0xff00,     WR_y|RD_SP, },\n{\"lh\",      \"y,H(x)\",   0x8800, 0xf800,     WR_y|RD_x, },\n{\"lhu\",     \"y,H(x)\",   0xa800, 0xf800,     WR_y|RD_x, },\n{\"li\",      \"x,U\",      0x6800, 0xf800,     WR_x, },\n{\"lw\",      \"y,W(x)\",   0x9800, 0xf800,     WR_y|RD_x, },\n{\"lw\",      \"x,A\",      0xb000, 0xf800,     WR_x|RD_PC, },\n{\"lw\",      \"x,V(P)\",   0xb000, 0xf800,     WR_x|RD_PC, },\n{\"lw\",      \"x,V(S)\",   0x9000, 0xf800,     WR_x|RD_SP, },\n{\"lwu\",     \"y,W(x)\",   0xb800, 0xf800,     WR_y|RD_x, },\n{\"mfhi\",    \"x\",        0xe810, 0xf8ff,     WR_x|RD_HI, },\n{\"mflo\",    \"x\",        0xe812, 0xf8ff,     WR_x|RD_LO, },\n{\"move\",    \"y,X\",      0x6700, 0xff00,     WR_y|RD_X, },\n{\"move\",    \"Y,Z\",      0x6500, 0xff00,     WR_Y|RD_Z, },\n{\"mul\",     \"z,v,y\",    0, (int) M_MUL,     INSN_MACRO, },\n{\"mult\",    \"x,y\",      0xe818, 0xf81f,     RD_x|RD_y|WR_HI|WR_LO,  },\n{\"multu\",   \"x,y\",      0xe819, 0xf81f,     RD_x|RD_y|WR_HI|WR_LO,  },\n{\"neg\",     \"x,w\",      0xe80b, 0xf81f,     WR_x|RD_y, },\n{\"not\",     \"x,w\",      0xe80f, 0xf81f,     WR_x|RD_y, },\n{\"or\",      \"x,y\",      0xe80d, 0xf81f,     WR_x|RD_x|RD_y, },\n{\"rem\",     \"0,x,y\",    0xe81a, 0xf81f,     RD_x|RD_y|WR_HI|WR_LO,  },\n{\"rem\",     \"z,v,y\",    0, (int) M_REM_3,   INSN_MACRO, },\n{\"remu\",    \"0,x,y\",    0xe81b, 0xf81f,     RD_x|RD_y|WR_HI|WR_LO,  },\n{\"remu\",    \"z,v,y\",    0, (int) M_REMU_3,  INSN_MACRO, },\n{\"sb\",      \"y,5(x)\",   0xc000, 0xf800,     RD_y|RD_x, },\n{\"sd\",      \"y,D(x)\",   0x7800, 0xf800,     RD_y|RD_x, },\n{\"sd\",      \"y,D(S)\",   0xf900, 0xff00,     RD_y|RD_PC, },\n{\"sd\",      \"R,C(S)\",   0xfa00, 0xff00,     RD_31|RD_PC, },\n{\"sh\",      \"y,H(x)\",   0xc800, 0xf800,     RD_y|RD_x, },\n{\"sllv\",    \"y,x\",      0xe804, 0xf81f,     WR_y|RD_y|RD_x, },\n{\"sll\",     \"x,w,<\",    0x3000, 0xf803,     WR_x|RD_y, },\n{\"sll\",     \"y,x\",      0xe804, 0xf81f,     WR_y|RD_y|RD_x, },\n{\"slti\",    \"x,8\",      0x5000, 0xf800,     WR_T|RD_x, },\n{\"slt\",     \"x,y\",      0xe802, 0xf81f,     WR_T|RD_x|RD_y, },\n{\"slt\",     \"x,8\",      0x5000, 0xf800,     WR_T|RD_x, },\n{\"sltiu\",   \"x,8\",      0x5800, 0xf800,     WR_T|RD_x, },\n{\"sltu\",    \"x,y\",      0xe803, 0xf81f,     WR_T|RD_x|RD_y, },\n{\"sltu\",    \"x,8\",      0x5800, 0xf800,     WR_T|RD_x, },\n{\"srav\",    \"y,x\",      0xe807, 0xf81f,     WR_y|RD_y|RD_x, },\n{\"sra\",     \"x,w,<\",    0x3003, 0xf803,     WR_x|RD_y, },\n{\"sra\",     \"y,x\",      0xe807, 0xf81f,     WR_y|RD_y|RD_x, },\n{\"srlv\",    \"y,x\",      0xe806, 0xf81f,     WR_y|RD_y|RD_x, },\n{\"srl\",     \"x,w,<\",    0x3002, 0xf803,     WR_x|RD_y, },\n{\"srl\",     \"y,x\",      0xe806, 0xf81f,     WR_y|RD_y|RD_x, },\n{\"subu\",    \"z,v,y\",    0xe003, 0xf803,     WR_z|RD_x|RD_y, },\n{\"subu\",    \"y,x,4\",    0, (int) M_SUBU_I,  INSN_MACRO, },\n{\"subu\",    \"x,k\",      0, (int) M_SUBU_I_2, INSN_MACRO, },\n{\"sw\",      \"y,W(x)\",   0xd800, 0xf800,     RD_y|RD_x, },\n{\"sw\",      \"x,V(S)\",   0xd000, 0xf800,     RD_x|RD_SP, },\n{\"sw\",      \"R,V(S)\",   0x6200, 0xff00,     RD_31|RD_SP, },\n{\"xor\",     \"x,y\",      0xe80e, 0xf81f,     WR_x|RD_x|RD_y, },\n  /* MIPS16e additions */\n{\"jalrc\",   \"x\",        0xe8c0, 0xf8ff,     UBR|WR_31|RD_x|TRAP,    },\n{\"jalrc\",   \"R,x\",      0xe8c0, 0xf8ff,     UBR|WR_31|RD_x|TRAP,    },\n{\"jrc\",     \"x\",        0xe880, 0xf8ff,     UBR|RD_x|TRAP, },\n{\"jrc\",     \"R\",        0xe8a0, 0xffff,     UBR|RD_31|TRAP, },\n{\"restore\", \"M\",        0x6400, 0xff80,     WR_31|RD_SP|WR_SP|TRAP, },\n{\"save\",    \"m\",        0x6480, 0xff80,     RD_31|RD_SP|WR_SP|TRAP, },\n{\"sdbbp\",   \"6\",        0xe801, 0xf81f,     TRAP, },\n{\"seb\",     \"x\",        0xe891, 0xf8ff,     WR_x|RD_x, },\n{\"seh\",     \"x\",        0xe8b1, 0xf8ff,     WR_x|RD_x, },\n{\"sew\",     \"x\",        0xe8d1, 0xf8ff,     WR_x|RD_x, },\n{\"zeb\",     \"x\",        0xe811, 0xf8ff,     WR_x|RD_x, },\n{\"zeh\",     \"x\",        0xe831, 0xf8ff,     WR_x|RD_x, },\n{\"zew\",     \"x\",        0xe851, 0xf8ff,     WR_x|RD_x, },\n};\n\nstatic const int mips16_num_opcodes =\n  ((sizeof mips16_opcodes) / (sizeof (mips16_opcodes[0])));\n\n#undef UBD\n#undef UBR\n#undef CBR\n#undef WR_x\n#undef WR_y\n#undef WR_z\n#undef WR_T\n#undef WR_SP\n#undef WR_31\n#undef WR_Y\n#undef RD_x\n#undef RD_y\n#undef RD_Z\n#undef RD_T\n#undef RD_SP\n#undef RD_31\n#undef RD_PC\n#undef RD_X\n#undef WR_HI\n#undef WR_LO\n#undef RD_HI\n#undef RD_LO\n#undef TRAP\n"
  },
  {
    "path": "tools/virtualmips/mips_codetable.c",
    "content": "/*\n * Code dispatch table.\n *\n * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n\n/*\n * Take the 'reserved instruction' exception.\n */\nstatic int unknown_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n#if 0\n    printf (\"--- Unknown instruction:\\n\");\n    printf (\"%08x:       %08x        \", cpu->pc, insn);\n    print_mips (cpu->pc, insn, cpu->insn_len, cpu->is_mips16e, stdout);\n    printf (\"\\n\");\n#endif\n    mips_trigger_exception (cpu, MIPS_CP0_CAUSE_ILLOP, cpu->is_in_bdslot);\n    return 1;\n}\n\n/*\n * Take the 'coprocessor unusable' exception.\n */\nstatic int cop_unusable(cpu_mips_t * cpu, int cop_index)\n{\n    if (cpu->cp0.reg[MIPS_CP0_DEBUG] & MIPS_CP0_DEBUG_DM) {\n        /* Coprocessor unusable in Debug mode. */\n        mips_trigger_debug_exception (cpu, 0);\n        cpu->cp0.reg[MIPS_CP0_DEBUG] |=\n            MIPS_CP0_CAUSE_CP_UNUSABLE << MIPS_CP0_DEBUG_DEXCCODE_SHIFT;\n    } else {\n        /* Set Cause.CE field. */\n        cpu->cp0.reg[MIPS_CP0_CAUSE] &= ~MIPS_CP0_CAUSE_CEMASK;\n        cpu->cp0.reg[MIPS_CP0_CAUSE] |= cop_index << MIPS_CP0_CAUSE_CESHIFT;\n\n        mips_trigger_exception (cpu, MIPS_CP0_CAUSE_CP_UNUSABLE, cpu->is_in_bdslot);\n    }\n    return 1;\n}\n\nstatic int add_op (cpu_mips_t *cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    m_ireg_t a = cpu->gpr[rs];\n    m_ireg_t b = cpu->gpr[rt];\n    m_ireg_t res = a + b;\n\n    if ((a > 0 && b > 0 && res < 0) ||\n        (a < 0 && b < 0 && res >= 0)) {\n        /* Take overflow exception. */\n        mips_trigger_exception (cpu, MIPS_CP0_CAUSE_OVFLW, cpu->is_in_bdslot);\n        return 1;\n    }\n    cpu->reg_set (cpu, rd, sign_extend (res, 32));\n    return (0);\n}\n\nstatic int addi_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int imm = bits (insn, 0, 15);\n    m_ireg_t a = cpu->gpr[rs];\n    m_ireg_t b = sign_extend (imm, 16);\n    m_ireg_t res = a + b;\n\n    if ((a > 0 && b > 0 && res < 0) ||\n        (a < 0 && b < 0 && res >= 0)) {\n        /* Take overflow exception. */\n        mips_trigger_exception (cpu, MIPS_CP0_CAUSE_OVFLW, cpu->is_in_bdslot);\n        return 1;\n    }\n    cpu->reg_set (cpu, rt, sign_extend (res, 32));\n    return (0);\n}\n\nstatic int addiu_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int imm = bits (insn, 0, 15);\n    m_uint32_t res, val = sign_extend (imm, 16);\n\n    res = (m_uint32_t) cpu->gpr[rs] + val;\n    cpu->reg_set (cpu, rt, sign_extend (res, 32));\n    return (0);\n}\n\nstatic int addu_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    m_uint32_t res;\n\n    res = (m_uint32_t) cpu->gpr[rs] + (m_uint32_t) cpu->gpr[rt];\n    cpu->reg_set (cpu, rd, sign_extend (res, 32));\n    return (0);\n}\n\nstatic int and_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n\n    cpu->reg_set (cpu, rd, cpu->gpr[rs] & cpu->gpr[rt]);\n    return (0);\n}\n\nstatic int andi_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int imm = bits (insn, 0, 15);\n\n    cpu->reg_set (cpu, rt, cpu->gpr[rs] & imm);\n    return (0);\n}\n\nstatic int bcond_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    uint16_t special_func = bits (insn, 16, 20);\n    return mips_bcond_opcodes[special_func].func (cpu, insn);\n}\n\nstatic int beq_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n    m_va_t new_pc;\n    int res;\n\n    /* compute the new pc */\n    new_pc = (cpu->pc + 4) + sign_extend (offset << 2, 18);\n\n    /* take the branch if gpr[rs] == gpr[rt] */\n    res = (cpu->gpr[rs] == cpu->gpr[rt]);\n\n    /* exec the instruction in the delay slot */\n    int ins_res = mips_exec_bdslot (cpu);\n    if (likely (!ins_res)) {\n        if (res)\n            cpu->pc = new_pc;\n        else\n            cpu->pc += 8;\n    }\n\n    return (1);\n}\n\nstatic int beql_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n    m_va_t new_pc;\n    int res;\n\n    /* compute the new pc */\n    new_pc = (cpu->pc + 4) + sign_extend (offset << 2, 18);\n\n    /* take the branch if gpr[rs] == gpr[rt] */\n    res = (cpu->gpr[rs] == cpu->gpr[rt]);\n\n    /* take the branch if the test result is true */\n    if (res) {\n        int ins_res = mips_exec_bdslot (cpu);\n        if (likely (!ins_res))\n            cpu->pc = new_pc;\n    } else\n        cpu->pc += 8;\n\n    return (1);\n}\n\nstatic int bgez_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    m_va_t new_pc;\n    int res;\n\n    /* compute the new pc */\n    new_pc = (cpu->pc + 4) + sign_extend (offset << 2, 18);\n\n    /* take the branch if gpr[rs] >= 0 */\n    res = ((m_ireg_t) cpu->gpr[rs] >= 0);\n\n    /* exec the instruction in the delay slot */\n    /* exec the instruction in the delay slot */\n    int ins_res = mips_exec_bdslot (cpu);\n\n    if (likely (!ins_res)) {\n        /* take the branch if the test result is true */\n        if (res)\n            cpu->pc = new_pc;\n        else\n            cpu->pc += 8;\n    }\n    return (1);\n}\n\nstatic int bgezal_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    m_va_t new_pc;\n    int res;\n\n    /* compute the new pc */\n    new_pc = (cpu->pc + 4) + sign_extend (offset << 2, 18);\n\n    /* set the return address (instruction after the delay slot) */\n    cpu->reg_set (cpu, MIPS_GPR_RA, cpu->pc + 8);\n\n    /* take the branch if gpr[rs] >= 0 */\n    res = ((m_ireg_t) cpu->gpr[rs] >= 0);\n\n    /* exec the instruction in the delay slot */\n    int ins_res = mips_exec_bdslot (cpu);\n\n    if (likely (!ins_res)) {\n        /* take the branch if the test result is true */\n        if (res)\n            cpu->pc = new_pc;\n        else\n            cpu->pc += 8;\n    }\n    return (1);\n}\n\nstatic int bgezall_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    m_va_t new_pc;\n    int res;\n\n    /* compute the new pc */\n    new_pc = (cpu->pc + 4) + sign_extend (offset << 2, 18);\n\n    /* set the return address (instruction after the delay slot) */\n    cpu->reg_set (cpu, MIPS_GPR_RA, cpu->pc + 8);\n\n    /* take the branch if gpr[rs] >= 0 */\n    res = ((m_ireg_t) cpu->gpr[rs] >= 0);\n\n    /* take the branch if the test result is true */\n    if (res) {\n        mips_exec_bdslot (cpu);\n        cpu->pc = new_pc;\n    } else\n        cpu->pc += 8;\n\n    return (1);\n\n}\n\nstatic int bgezl_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    m_va_t new_pc;\n    int res;\n\n    /* compute the new pc */\n    new_pc = (cpu->pc + 4) + sign_extend (offset << 2, 18);\n\n    /* take the branch if gpr[rs] >= 0 */\n    res = ((m_ireg_t) cpu->gpr[rs] >= 0);\n\n    /* take the branch if the test result is true */\n    if (res) {\n        mips_exec_bdslot (cpu);\n        cpu->pc = new_pc;\n    } else\n        cpu->pc += 8;\n\n    return (1);\n\n}\n\nstatic int bgtz_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    m_va_t new_pc;\n    int res;\n\n    /* compute the new pc */\n    new_pc = (cpu->pc + 4) + sign_extend (offset << 2, 18);\n\n    /* take the branch if gpr[rs] > 0 */\n    res = ((m_ireg_t) cpu->gpr[rs] > 0);\n\n    /* exec the instruction in the delay slot */\n    int ins_res = mips_exec_bdslot (cpu);\n\n    if (likely (!ins_res)) {\n        /* take the branch if the test result is true */\n        if (res)\n            cpu->pc = new_pc;\n        else\n            cpu->pc += 8;\n    }\n    return (1);\n}\n\nstatic int bgtzl_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    m_va_t new_pc;\n    int res;\n\n    /* compute the new pc */\n    new_pc = (cpu->pc + 4) + sign_extend (offset << 2, 18);\n\n    /* take the branch if gpr[rs] > 0 */\n    res = ((m_ireg_t) cpu->gpr[rs] > 0);\n\n    /* take the branch if the test result is true */\n    if (res) {\n        mips_exec_bdslot (cpu);\n        cpu->pc = new_pc;\n    } else\n        cpu->pc += 8;\n\n    return (1);\n}\n\nstatic int blez_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    m_va_t new_pc;\n    int res;\n\n    /* compute the new pc */\n    new_pc = (cpu->pc + 4) + sign_extend (offset << 2, 18);\n\n    /* take the branch if gpr[rs] <= 0 */\n    res = ((m_ireg_t) cpu->gpr[rs] <= 0);\n\n    /* exec the instruction in the delay slot */\n    int ins_res = mips_exec_bdslot (cpu);\n\n    if (likely (!ins_res)) {\n        /* take the branch if the test result is true */\n        if (res)\n            cpu->pc = new_pc;\n        else\n            cpu->pc += 8;\n    }\n    return (1);\n}\n\nstatic int blezl_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    m_va_t new_pc;\n    int res;\n\n    /* compute the new pc */\n    new_pc = (cpu->pc + 4) + sign_extend (offset << 2, 18);\n\n    /* take the branch if gpr[rs] <= 0 */\n    res = ((m_ireg_t) cpu->gpr[rs] <= 0);\n\n    /* take the branch if the test result is true */\n    if (res) {\n        mips_exec_bdslot (cpu);\n        cpu->pc = new_pc;\n    } else\n        cpu->pc += 8;\n\n    return (1);\n}\n\nstatic int bltz_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    m_va_t new_pc;\n    int res;\n\n    /* compute the new pc */\n    new_pc = (cpu->pc + 4) + sign_extend (offset << 2, 18);\n\n    /* take the branch if gpr[rs] < 0 */\n    res = ((m_ireg_t) cpu->gpr[rs] < 0);\n\n    /* exec the instruction in the delay slot */\n    int ins_res = mips_exec_bdslot (cpu);\n\n    if (likely (!ins_res)) {\n        /* take the branch if the test result is true */\n        if (res)\n            cpu->pc = new_pc;\n        else\n            cpu->pc += 8;\n    }\n    return (1);\n}\n\nstatic int bltzal_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    m_va_t new_pc;\n    int res;\n\n    /* compute the new pc */\n    new_pc = (cpu->pc + 4) + sign_extend (offset << 2, 18);\n\n    /* set the return address (instruction after the delay slot) */\n    cpu->reg_set (cpu, MIPS_GPR_RA, cpu->pc + 8);\n\n    /* take the branch if gpr[rs] < 0 */\n    res = ((m_ireg_t) cpu->gpr[rs] < 0);\n\n    /* exec the instruction in the delay slot */\n    int ins_res = mips_exec_bdslot (cpu);\n\n    if (likely (!ins_res)) {\n        /* take the branch if the test result is true */\n        if (res)\n            cpu->pc = new_pc;\n        else\n            cpu->pc += 8;\n    }\n    return (1);\n}\n\nstatic int bltzall_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    m_va_t new_pc;\n    int res;\n\n    /* compute the new pc */\n    new_pc = (cpu->pc + 4) + sign_extend (offset << 2, 18);\n\n    /* set the return address (instruction after the delay slot) */\n    cpu->reg_set (cpu, MIPS_GPR_RA, cpu->pc + 8);\n\n    /* take the branch if gpr[rs] < 0 */\n    res = ((m_ireg_t) cpu->gpr[rs] < 0);\n\n    /* take the branch if the test result is true */\n    if (res) {\n        mips_exec_bdslot (cpu);\n        cpu->pc = new_pc;\n    } else\n        cpu->pc += 8;\n\n    return (1);\n}\n\nstatic int bltzl_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    m_va_t new_pc;\n    int res;\n\n    /* compute the new pc */\n    new_pc = (cpu->pc + 4) + sign_extend (offset << 2, 18);\n\n    /* take the branch if gpr[rs] < 0 */\n    res = ((m_ireg_t) cpu->gpr[rs] < 0);\n\n    /* take the branch if the test result is true */\n    if (res) {\n        mips_exec_bdslot (cpu);\n        cpu->pc = new_pc;\n    } else\n        cpu->pc += 8;\n\n    return (1);\n}\n\nstatic int bne_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n    m_va_t new_pc;\n    int res;\n\n    /* compute the new pc */\n    new_pc = (cpu->pc + 4) + sign_extend (offset << 2, 18);\n\n    /* take the branch if gpr[rs] != gpr[rt] */\n    res = (cpu->gpr[rs] != cpu->gpr[rt]);\n\n    /* exec the instruction in the delay slot */\n    int ins_res = mips_exec_bdslot (cpu);\n\n    if (likely (!ins_res)) {\n        /* take the branch if the test result is true */\n        if (res)\n            cpu->pc = new_pc;\n        else\n            cpu->pc += 8;\n    }\n\n    return (1);\n}\n\nstatic int bnel_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n    m_va_t new_pc;\n    int res;\n\n    /* compute the new pc */\n    new_pc = (cpu->pc + 4) + sign_extend (offset << 2, 18);\n\n    /* take the branch if gpr[rs] != gpr[rt] */\n    res = (cpu->gpr[rs] != cpu->gpr[rt]);\n\n    /* take the branch if the test result is true */\n    if (res) {\n        mips_exec_bdslot (cpu);\n        cpu->pc = new_pc;\n    } else\n        cpu->pc += 8;\n    return (1);\n}\n\nstatic int break_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    u_int code = bits (insn, 6, 25);\n\n    mips_exec_break (cpu, code);\n    return (1);\n}\n\nstatic int cache_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int base = bits (insn, 21, 25);\n    int op = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    return (mips_exec_memop2 (cpu, MIPS_MEMOP_CACHE, base, offset, op,\n            FALSE));\n}\n\nstatic int cfc0_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    return unknown_op (cpu, insn);\n}\n\nstatic int clz_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rd = bits (insn, 11, 15);\n    int i;\n    m_uint32_t val;\n    val = 32;\n    for (i = 31; i >= 0; i--) {\n        if (cpu->gpr[rs] & (1 << i)) {\n            val = 31 - i;\n            break;\n        }\n    }\n    cpu->reg_set (cpu, rd, val);\n    return (0);\n}\n\nstatic int clo_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rd = bits (insn, 11, 15);\n    int i;\n    m_uint32_t val;\n    val = 32;\n    for (i = 31; i >= 0; i--) {\n        if (! (cpu->gpr[rs] & (1 << i))) {\n            val = 31 - i;\n            break;\n        }\n    }\n    cpu->reg_set (cpu, rd, val);\n    return (0);\n}\n\nstatic int cop0_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    uint16_t special_func = bits (insn, 21, 25);\n//printf (\"cop0 instruction. func %x\\n\", special_func);\n    return mips_cop0_opcodes[special_func].func (cpu, insn);\n}\n\nstatic int cop1_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n#if SOFT_FPU\n    mips_exec_soft_fpu (cpu);\n    return (1);\n#else\n    if (! (cpu->cp0.reg [MIPS_CP0_STATUS] & MIPS_CP0_STATUS_CU1)) {\n        return cop_unusable (cpu, 1);\n    }\n    return unknown_op (cpu, insn);\n#endif\n}\n\nstatic int cop2_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    if (! (cpu->cp0.reg [MIPS_CP0_STATUS] & MIPS_CP0_STATUS_CU2)) {\n        return cop_unusable (cpu, 2);\n    }\n    return unknown_op (cpu, insn);\n}\n\nstatic int div_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n\n    if (cpu->gpr[rt] == 0)\n        return (0);\n\n    if (cpu->gpr[rs] == 0x80000000 && cpu->gpr[rt] == 0xFFFFFFFF) {\n        cpu->lo = 0x80000000;\n        cpu->hi = 0;\n        return (0);\n    }\n\n    cpu->lo = (m_int32_t) cpu->gpr[rs] / (m_int32_t) cpu->gpr[rt];\n    cpu->hi = (m_int32_t) cpu->gpr[rs] % (m_int32_t) cpu->gpr[rt];\n\n    cpu->lo = sign_extend (cpu->lo, 32);\n    cpu->hi = sign_extend (cpu->hi, 32);\n    return (0);\n}\n\nstatic int divu_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n\n    if (cpu->gpr[rt] == 0)\n        return (0);\n\n    cpu->lo = (m_uint32_t) cpu->gpr[rs] / (m_uint32_t) cpu->gpr[rt];\n    cpu->hi = (m_uint32_t) cpu->gpr[rs] % (m_uint32_t) cpu->gpr[rt];\n\n    cpu->lo = sign_extend (cpu->lo, 32);\n    cpu->hi = sign_extend (cpu->hi, 32);\n    return (0);\n\n}\n\nstatic int eret_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n#if 1\n    if (cpu->trace_syscall &&\n        (cpu->cp0.reg[MIPS_CP0_STATUS] & MIPS_CP0_STATUS_UM))\n    {\n        if (cpu->gpr[2] == 0xffffffff)\n            printf (\"    syscall failed, errno %u\\n\", cpu->gpr[8]);\n        else {\n            if (cpu->gpr[2] & ~0xffff)\n                printf (\"    syscall returned %08x\\n\", cpu->gpr[2]);\n            else\n                printf (\"    syscall returned %u\\n\", cpu->gpr[2]);\n        }\n        cpu->trace_syscall = 0;\n    }\n#endif\n    mips_exec_eret (cpu);\n    return (1);\n}\n\nstatic int deret_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    mips_exec_deret (cpu);\n    return (1);\n}\n\nstatic int j_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    u_int instr_index = bits (insn, 0, 25);\n    m_va_t new_pc;\n\n    /* compute the new pc */\n    new_pc = cpu->pc & ~((1 << 28) - 1);\n    new_pc |= instr_index << 2;\n\n    /* exec the instruction in the delay slot */\n    int ins_res = mips_exec_bdslot (cpu);\n    if (likely (!ins_res))\n        cpu->pc = new_pc;\n    return (1);\n}\n\nstatic int jal_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    u_int instr_index = bits (insn, 0, 25);\n    m_va_t new_pc;\n\n    /* compute the new pc */\n    new_pc = (cpu->pc + 4) & ~((1 << 28) - 1);\n    new_pc |= instr_index << 2;\n\n    /* set the return address (instruction after the delay slot) */\n    cpu->reg_set (cpu, MIPS_GPR_RA, cpu->pc + 8);\n\n    int ins_res = mips_exec_bdslot (cpu);\n    if (likely (!ins_res))\n        cpu->pc = new_pc;\n\n    return (1);\n}\n\nstatic int jalx_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    u_int instr_index = bits (insn, 0, 25);\n    m_va_t new_pc;\n\n    /* compute the new pc */\n    new_pc = (cpu->pc + 4) & ~((1 << 28) - 1);\n    new_pc |= instr_index << 2;\n\n    /* set the return address (instruction after the delay slot) */\n    cpu->reg_set (cpu, MIPS_GPR_RA, cpu->pc + 8);\n\n    int ins_res = mips_exec_bdslot (cpu);\n    if (likely (!ins_res)) {\n        cpu->is_mips16e = 1;\n        cpu->pc = new_pc;\n    }\n\n    return (1);\n}\n\nstatic int jalr_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rd = bits (insn, 11, 15);\n    m_va_t new_pc;\n\n    /* set the return pc (instruction after the delay slot) in GPR[rd] */\n    cpu->reg_set (cpu, rd, cpu->pc + 8);\n\n    /* get the new pc */\n    new_pc = cpu->gpr[rs];\n\n    int ins_res = mips_exec_bdslot (cpu);\n    if (likely (!ins_res)) {\n        cpu->is_mips16e = new_pc & 1;\n        cpu->pc = new_pc & 0xFFFFFFFE;\n    }\n    return (1);\n\n}\n\nstatic int jr_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    m_va_t new_pc;\n\n    /* get the new pc */\n    new_pc = cpu->gpr[rs];\n\n    int ins_res = mips_exec_bdslot (cpu);\n    if (likely (!ins_res)) {\n        cpu->is_mips16e = new_pc & 1;\n        cpu->pc = new_pc & 0xFFFFFFFE;\n    }\n    return (1);\n\n}\n\nstatic int lb_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    return (mips_exec_memop2 (cpu, MIPS_MEMOP_LB, base, offset, rt, TRUE));\n}\n\nstatic int lbu_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    return (mips_exec_memop2 (cpu, MIPS_MEMOP_LBU, base, offset, rt, TRUE));\n}\n\nstatic int lh_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    return (mips_exec_memop2 (cpu, MIPS_MEMOP_LH, base, offset, rt, TRUE));\n}\n\nstatic int lhu_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    return (mips_exec_memop2 (cpu, MIPS_MEMOP_LHU, base, offset, rt, TRUE));\n}\n\nstatic int ll_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    return (mips_exec_memop2 (cpu, MIPS_MEMOP_LL, base, offset, rt, TRUE));\n}\n\nstatic int lui_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rt = bits (insn, 16, 20);\n    int imm = bits (insn, 0, 15);\n\n    cpu->reg_set (cpu, rt, sign_extend (imm, 16) << 16);\n    return (0);\n}\n\nstatic int lw_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    return (mips_exec_memop2 (cpu, MIPS_MEMOP_LW, base, offset, rt, TRUE));\n\n}\n\nstatic int lwl_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    return (mips_exec_memop2 (cpu, MIPS_MEMOP_LWL, base, offset, rt, TRUE));\n\n}\n\nstatic int lwr_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    return (mips_exec_memop2 (cpu, MIPS_MEMOP_LWR, base, offset, rt, TRUE));\n}\n\nstatic int spec3_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int index = bits (insn, 0, 5);\n    return mips_spec3_opcodes[index].func (cpu, insn);\n}\n\nstatic int bshfl_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    int sa = bits (insn, 6, 10);\n//printf (\"seh rt=%d, rd=%d, sa=%x\\n\", rt, rd, sa);\n    switch (sa) {\n    case 0x02:\n        /* wsbh - word swap bytes within halfwords */\n        cpu->reg_set (cpu, rd, bits (cpu->gpr[rt], 16, 23) << 24 |\n                       bits (cpu->gpr[rt], 24, 31) << 16 |\n                       bits (cpu->gpr[rt], 0,  7)  << 8 |\n                       bits (cpu->gpr[rt], 8, 15));\n        return (0);\n    case 0x10:\n        /* seb - sign extend byte */\n        cpu->reg_set (cpu, rd, sign_extend (cpu->gpr[rt], 8));\n        return (0);\n    case 0x18:\n        /* seh - sign extend halfword */\n        cpu->reg_set (cpu, rd, sign_extend (cpu->gpr[rt], 16));\n        return (0);\n    }\n    return unknown_op (cpu, insn);\n}\n\nstatic int ext_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int msbd = bits (insn, 11, 15);\n    int lsb = bits (insn, 6, 10);\n\n    /* Extract bit field */\n    cpu->reg_set (cpu, rt, (cpu->gpr[rs] >> lsb) & (~0U >> (31 - msbd)));\n    return (0);\n}\n\nstatic int ins_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int msb = bits (insn, 11, 15);\n    int lsb = bits (insn, 6, 10);\n\n    /* Insert bit field */\n    int mask = ~0U >> (31-msb+lsb) << lsb;\n    cpu->gpr[rt] &= ~mask;\n    cpu->gpr[rt] |= (cpu->gpr[rs] << lsb) & mask;\n    return (0);\n}\n\nstatic int spec2_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int index = bits (insn, 0, 5);\n    return mips_spec2_opcodes[index].func (cpu, insn);\n}\n\nstatic int madd_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    m_int64_t val, temp;\n\n    val = (m_int32_t) (m_int32_t) cpu->gpr[rs];\n    val *= (m_int32_t) (m_int32_t) cpu->gpr[rt];\n\n    temp = cpu->hi;\n    temp = temp << 32;\n    temp += cpu->lo;\n    val += temp;\n\n    cpu->lo = sign_extend (val, 32);\n    cpu->hi = sign_extend (val >> 32, 32);\n    return (0);\n}\n\nstatic int maddu_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    m_int64_t val, temp;\n\n    val = (m_uint32_t) (m_uint32_t) cpu->gpr[rs];\n    val *= (m_uint32_t) (m_uint32_t) cpu->gpr[rt];\n\n    temp = cpu->hi;\n    temp = temp << 32;\n    temp += cpu->lo;\n    val += temp;\n\n    cpu->lo = sign_extend (val, 32);\n    cpu->hi = sign_extend (val >> 32, 32);\n    return (0);\n}\n\nstatic int mfc0_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    int sel = bits (insn, 0, 2);\n    //mfc rt,rd\n\n    mips_cp0_exec_mfc0 (cpu, rt, rd, sel);\n    return (0);\n}\n\nstatic int mfhi_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rd = bits (insn, 11, 15);\n\n    if (rd)\n        cpu->reg_set (cpu, rd, cpu->hi);\n    return (0);\n}\n\nstatic int mflo_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rd = bits (insn, 11, 15);\n\n    if (rd)\n        cpu->reg_set (cpu, rd, cpu->lo);\n    return (0);\n}\n\nstatic int movc_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    if (! (cpu->cp0.reg [MIPS_CP0_STATUS] & MIPS_CP0_STATUS_CU1)) {\n        return cop_unusable (cpu, 1);\n    }\n    return unknown_op (cpu, insn);\n}\n\nstatic int movz_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rd = bits (insn, 11, 15);\n    int rt = bits (insn, 16, 20);\n\n    if ((cpu->gpr[rt]) == 0)\n        cpu->reg_set (cpu, rd, sign_extend (cpu->gpr[rs], 32));\n    return (0);\n}\n\nstatic int movn_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rd = bits (insn, 11, 15);\n    int rt = bits (insn, 16, 20);\n\n    // printf(\"pc %x rs %x rd %x rt %x\\n\",cpu->pc,rs,rd,rt);\n    if ((cpu->gpr[rt]) != 0)\n        cpu->reg_set (cpu, rd, sign_extend (cpu->gpr[rs], 32));\n    return (0);\n}\n\nstatic int msub_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    m_int64_t val, temp;\n\n    val = (m_int32_t) (m_int32_t) cpu->gpr[rs];\n    val *= (m_int32_t) (m_int32_t) cpu->gpr[rt];\n\n    temp = cpu->hi;\n    temp = temp << 32;\n    temp += cpu->lo;\n\n    temp -= val;\n    //val += temp;\n\n    cpu->lo = sign_extend (temp, 32);\n    cpu->hi = sign_extend (temp >> 32, 32);\n    return (0);\n}\n\nstatic int msubu_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    m_int64_t val, temp;\n\n    val = (m_uint32_t) (m_uint32_t) cpu->gpr[rs];\n    val *= (m_uint32_t) (m_uint32_t) cpu->gpr[rt];\n\n    temp = cpu->hi;\n    temp = temp << 32;\n    temp += cpu->lo;\n\n    temp -= val;\n    //val += temp;\n\n    cpu->lo = sign_extend (temp, 32);\n    cpu->hi = sign_extend (temp >> 32, 32);\n    return (0);\n}\n\nstatic int mtc0_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    int sel = bits (insn, 0, 2);\n\n    //printf(\"cpu->pc %x insn %x\\n\",cpu->pc,insn);\n    mips_cp0_exec_mtc0 (cpu, rt, rd, sel);\n    return (0);\n}\n\nstatic int mthi_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n\n    cpu->hi = cpu->gpr[rs];\n    return (0);\n}\n\nstatic int mtlo_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n\n    cpu->lo = cpu->gpr[rs];\n    return (0);\n}\n\nstatic int mul_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    m_int32_t val;\n\n    /* note: after this instruction, HI/LO regs are undefined */\n    val = (m_int32_t) cpu->gpr[rs] * (m_int32_t) cpu->gpr[rt];\n    cpu->reg_set (cpu, rd, sign_extend (val, 32));\n    return (0);\n}\n\nstatic int mult_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    m_int64_t val;\n\n    val = (m_int64_t) (m_int32_t) cpu->gpr[rs];\n    val *= (m_int64_t) (m_int32_t) cpu->gpr[rt];\n\n    cpu->lo = sign_extend (val, 32);\n    cpu->hi = sign_extend (val >> 32, 32);\n    return (0);\n}\n\nstatic int multu_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    m_int64_t val;              //must be 64 bit. not m_reg_t !!!\n\n    val = (m_reg_t) (m_uint32_t) cpu->gpr[rs];\n    val *= (m_reg_t) (m_uint32_t) cpu->gpr[rt];\n    cpu->lo = sign_extend (val, 32);\n    cpu->hi = sign_extend (val >> 32, 32);\n    return (0);\n}\n\nstatic int nor_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n\n    cpu->reg_set (cpu, rd, ~(cpu->gpr[rs] | cpu->gpr[rt]));\n    return (0);\n}\n\nstatic int or_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n\n    cpu->reg_set (cpu, rd, cpu->gpr[rs] | cpu->gpr[rt]);\n    return (0);\n}\n\nstatic int ori_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int imm = bits (insn, 0, 15);\n\n    cpu->reg_set (cpu, rt, cpu->gpr[rs] | imm);\n    return (0);\n}\n\nstatic int pref_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    return (0);\n}\n\nstatic int sb_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n    return (mips_exec_memop2 (cpu, MIPS_MEMOP_SB, base, offset, rt, FALSE));\n}\n\nstatic int sc_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    return (mips_exec_memop2 (cpu, MIPS_MEMOP_SC, base, offset, rt, TRUE));\n}\n\nstatic int sh_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    return (mips_exec_memop2 (cpu, MIPS_MEMOP_SH, base, offset, rt, FALSE));\n}\n\nstatic int sll_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    int sa = bits (insn, 6, 10);\n    m_uint32_t res;\n\n    res = (m_uint32_t) cpu->gpr[rt] << sa;\n    cpu->reg_set (cpu, rd, sign_extend (res, 32));\n    return (0);\n}\n\nstatic int sllv_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    m_uint32_t res;\n\n    res = (m_uint32_t) cpu->gpr[rt] << (cpu->gpr[rs] & 0x1f);\n    cpu->reg_set (cpu, rd, sign_extend (res, 32));\n    return (0);\n}\n\nstatic int slt_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n\n    if ((m_ireg_t) cpu->gpr[rs] < (m_ireg_t) cpu->gpr[rt])\n        cpu->reg_set (cpu, rd, 1);\n    else\n        cpu->reg_set (cpu, rd, 0);\n    return (0);\n}\n\nstatic int slti_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int imm = bits (insn, 0, 15);\n    m_ireg_t val = sign_extend (imm, 16);\n\n    if ((m_ireg_t) cpu->gpr[rs] < val)\n        cpu->reg_set (cpu, rt, 1);\n    else\n        cpu->reg_set (cpu, rt, 0);\n    return (0);\n}\n\nstatic int sltiu_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int imm = bits (insn, 0, 15);\n    m_reg_t val = sign_extend (imm, 16);\n\n    if (rs == 0 && rt == 0 && cpu->magic_opcodes) {\n        if (imm == 0xabc1) {\n            printf (\"%08x: Test FAIL\\n\", cpu->pc);\n            printf (\"\\n--- Stop simulation\\n\");\n            fprintf (stderr, \"Test FAIL\\n\");\n            exit (EXIT_SUCCESS);\n        }\n        if (imm == 0xabc2) {\n            printf (\"%08x: Test PASS\\n\", cpu->pc);\n            printf (\"\\n--- Stop simulation\\n\");\n            fprintf (stderr, \"Test PASS\\n\");\n            exit (EXIT_SUCCESS);\n        }\n    }\n\n    if (cpu->gpr[rs] < val)\n        cpu->reg_set (cpu, rt, 1);\n    else\n        cpu->reg_set (cpu, rt, 0);\n    return (0);\n}\n\nstatic int sltu_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n\n    if (cpu->gpr[rs] < cpu->gpr[rt])\n        cpu->reg_set (cpu, rd, 1);\n    else\n        cpu->reg_set (cpu, rd, 0);\n    return (0);\n}\n\nstatic int spec_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    uint16_t special_func = bits (insn, 0, 5);\n    return mips_spec_opcodes[special_func].func (cpu, insn);\n}\n\nstatic int sra_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    int sa = bits (insn, 6, 10);\n    m_int32_t res;\n\n    res = (m_int32_t) cpu->gpr[rt] >> sa;\n    cpu->reg_set (cpu, rd, sign_extend (res, 32));\n    return (0);\n}\n\nstatic int srav_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    m_int32_t res;\n\n    res = (m_int32_t) cpu->gpr[rt] >> (cpu->gpr[rs] & 0x1f);\n    cpu->reg_set (cpu, rd, sign_extend (res, 32));\n    return (0);\n}\n\nstatic int srl_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    int sa = bits (insn, 6, 10);\n    m_uint32_t res;\n\n    /* srl */\n    res = (m_uint32_t) cpu->gpr[rt] >> sa;\n    if ((insn >> 21) & 1) {\n        /* rotr */\n        res |= (m_uint32_t) cpu->gpr[rt] << (32 - sa);\n    }\n    cpu->reg_set (cpu, rd, sign_extend (res, 32));\n    return (0);\n}\n\nstatic int srlv_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    m_uint32_t res, sa;\n\n    /* srlv */\n    sa = cpu->gpr[rs] & 0x1f;\n    res = (m_uint32_t) cpu->gpr[rt] >> sa;\n    if ((insn >> 6) & 1) {\n        /* rotrv */\n        res |= (m_uint32_t) cpu->gpr[rt] << (32 - sa);\n    }\n    cpu->reg_set (cpu, rd, sign_extend (res, 32));\n    return (0);\n}\n\nstatic int sub_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    m_ireg_t a = cpu->gpr[rs];\n    m_ireg_t b = cpu->gpr[rt];\n    m_ireg_t res = a - b;\n\n    if ((a > 0 && b < 0 && res < 0) ||\n        (a < 0 && b > 0 && res >= 0)) {\n        /* Take overflow exception. */\n        mips_trigger_exception (cpu, MIPS_CP0_CAUSE_OVFLW, cpu->is_in_bdslot);\n        return 1;\n    }\n    cpu->reg_set (cpu, rd, sign_extend (res, 32));\n    return (0);\n}\n\nstatic int subu_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    m_uint32_t res;\n    res = (m_uint32_t) cpu->gpr[rs] - (m_uint32_t) cpu->gpr[rt];\n    cpu->reg_set (cpu, rd, sign_extend (res, 32));\n    return (0);\n}\n\nstatic int sw_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    return (mips_exec_memop2 (cpu, MIPS_MEMOP_SW, base, offset, rt, FALSE));\n}\n\nstatic int swl_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    return (mips_exec_memop2 (cpu, MIPS_MEMOP_SWL, base, offset, rt,\n            FALSE));\n}\n\nstatic int swr_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    return (mips_exec_memop2 (cpu, MIPS_MEMOP_SWR, base, offset, rt,\n            FALSE));\n}\n\nstatic int sync_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    return (0);\n}\n\nstatic int syscall_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    mips_exec_syscall (cpu);\n    return (1);\n}\n\nstatic int teq_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n\n    if (unlikely (cpu->gpr[rs] == cpu->gpr[rt])) {\n        mips_trigger_trap_exception (cpu);\n        return (1);\n    }\n    return (0);\n}\n\nstatic int teqi_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int imm = bits (insn, 0, 15);\n    m_reg_t val = sign_extend (imm, 16);\n\n    if (unlikely (cpu->gpr[rs] == val)) {\n        mips_trigger_trap_exception (cpu);\n        return (1);\n    }\n    return (0);\n}\n\n/*\n * DI and EI instructions\n */\nstatic int mfmc0_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    int func = bits (insn, 0, 10);\n\n    if (rd == 12) {\n        switch (func) {\n        case 0x020:\n            /* ei - enable interrupts */\n            cpu->reg_set (cpu, rt, cpu->cp0.reg [MIPS_CP0_STATUS]);\n            cpu->cp0.reg [MIPS_CP0_STATUS] |= MIPS_CP0_STATUS_IE;\n            return 0;\n        case 0x000:\n            /* di - disable interrupts */\n            cpu->reg_set (cpu, rt, cpu->cp0.reg [MIPS_CP0_STATUS]);\n            cpu->cp0.reg [MIPS_CP0_STATUS] &= ~MIPS_CP0_STATUS_IE;\n            return 0;\n        }\n    }\n    return unknown_op (cpu, insn);\n}\n\nstatic int tlb_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    uint16_t func = bits (insn, 0, 5);\n    return mips_tlb_opcodes[func].func (cpu, insn);\n}\n\nstatic int tlbp_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    mips_cp0_exec_tlbp (cpu);\n    return (0);\n}\n\nstatic int tlbr_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    mips_cp0_exec_tlbr (cpu);\n    return (0);\n}\n\nstatic int tlbwi_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    mips_cp0_exec_tlbwi (cpu);\n    return (0);\n}\n\nstatic int tlbwr_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    mips_cp0_exec_tlbwr (cpu);\n    return (0);\n}\n\nstatic int tge_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n\n    if ((m_ireg_t) cpu->gpr[rs] >= (m_ireg_t) cpu->gpr[rt]) {\n        mips_trigger_trap_exception (cpu);\n        return (1);\n    }\n    return (0);\n}\n\nstatic int tgei_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    m_ireg_t val = sign_extend (bits (insn, 0, 15), 16);\n\n    if (unlikely ((m_ireg_t) cpu->gpr[rs] >= val)) {\n        mips_trigger_trap_exception (cpu);\n        return (1);\n    }\n    return (0);\n}\n\nstatic int tgeiu_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    m_reg_t val = sign_extend (bits (insn, 0, 15), 16);\n\n    if (unlikely ((m_reg_t) cpu->gpr[rs] >= val)) {\n        mips_trigger_trap_exception (cpu);\n        return (1);\n    }\n    return (0);\n}\n\nstatic int tgeu_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n\n    if ((m_reg_t) cpu->gpr[rs] >= (m_reg_t) cpu->gpr[rt]) {\n        mips_trigger_trap_exception (cpu);\n        return (1);\n    }\n    return (0);\n}\n\nstatic int tlt_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n\n    if ((m_ireg_t) cpu->gpr[rs] < (m_ireg_t) cpu->gpr[rt]) {\n        mips_trigger_trap_exception (cpu);\n        return (1);\n    }\n    return (0);\n}\n\nstatic int tlti_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    m_ireg_t val = sign_extend (bits (insn, 0, 15), 16);\n\n    if (unlikely ((m_ireg_t) cpu->gpr[rs] < val)) {\n        mips_trigger_trap_exception (cpu);\n        return (1);\n    }\n    return (0);\n}\n\nstatic int tltiu_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    m_reg_t val = sign_extend (bits (insn, 0, 15), 16);\n\n    if (unlikely ((m_reg_t) cpu->gpr[rs] < val)) {\n        mips_trigger_trap_exception (cpu);\n        return (1);\n    }\n    return (0);\n}\n\nstatic int tltu_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n\n    if ((m_reg_t) cpu->gpr[rs] < (m_reg_t) cpu->gpr[rt]) {\n        mips_trigger_trap_exception (cpu);\n        return (1);\n    }\n    return (0);\n}\n\nstatic int tne_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n\n    if ((m_ireg_t) cpu->gpr[rs] != (m_ireg_t) cpu->gpr[rt]) {\n        mips_trigger_trap_exception (cpu);\n        return (1);\n    }\n    return (0);\n}\n\nstatic int tnei_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    m_reg_t val = sign_extend (bits (insn, 0, 15), 16);\n\n    if (unlikely (cpu->gpr[rs] != val)) {\n        mips_trigger_trap_exception (cpu);\n        return (1);\n    }\n    return (0);\n}\n\nstatic int wait_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    if (! (cpu->cp0.reg [MIPS_CP0_STATUS] & MIPS_CP0_STATUS_IE)) {\n        /* Wait instruction with interrupts disabled - stop the simulator. */\n        printf (\"%08x: wait instruction with interrupts disabled - stop the simulator.\\n\",\n            cpu->pc);\n        kill (0, SIGQUIT);\n    }\n    usleep (1000);\n    return (0);\n}\n\nstatic int xor_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n\n    cpu->reg_set (cpu, rd, cpu->gpr[rs] ^ cpu->gpr[rt]);\n    return (0);\n}\n\nstatic int rdpgpr_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n\n    printf (\"%08x: unsupported RDPGPR $%u,$%u instruction.\\n\", cpu->pc, rd, rt);\n    return (0);\n}\n\nstatic int wrpgpr_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n\n    printf (\"%08x: unsupported WRPGPR $%u,$%u instruction.\\n\", cpu->pc, rd, rt);\n    return (0);\n}\n\nstatic int xori_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int imm = bits (insn, 0, 15);\n\n    cpu->reg_set (cpu, rt, cpu->gpr[rs] ^ imm);\n    return (0);\n}\n\nstatic int sdbbp_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    /* Clear status of previos Debug exception. */\n    cpu->cp0.reg[MIPS_CP0_DEBUG] &= ~MIPS_CP0_DEBUG_DEXCCODE;\n\n    if (cpu->cp0.reg[MIPS_CP0_DEBUG] & MIPS_CP0_DEBUG_DM) {\n        /* Already in Debug mode: take nested debug exception. */\n        mips_trigger_debug_exception (cpu, 0);\n\n        /* Set nested exception type. */\n        cpu->cp0.reg[MIPS_CP0_DEBUG] |=\n            MIPS_CP0_CAUSE_BP << MIPS_CP0_DEBUG_DEXCCODE_SHIFT;\n\n    } else {\n        /* Take a Breakpoint exception. */\n        mips_trigger_debug_exception (cpu, MIPS_CP0_DEBUG_DBP);\n    }\n    return 1;\n}\n\nstatic int undef_op (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    return unknown_op (cpu, insn);\n}\n\nstatic int undef_bcond (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    return unknown_op (cpu, insn);\n}\n\nstatic int undef_cop0 (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    return unknown_op (cpu, insn);\n}\n\nstatic int undef_spec2 (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    return unknown_op (cpu, insn);\n}\n\nstatic int undef_spec3 (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    return unknown_op (cpu, insn);\n}\n\nstatic int undef_spec (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    return unknown_op (cpu, insn);\n}\n\nstatic int undef_tlb (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    return unknown_op (cpu, insn);\n}\n\n/*\n * Main instruction table, indexed by bits 31:26 of opcode.\n */\nstatic const struct mips_op_desc mips_opcodes[] = {\n    {\"spec\",    spec_op,    0x00},      /* indexed by FUNC field */\n    {\"bcond\",   bcond_op,   0x01},      /* indexed by RT field */\n    {\"j\",       j_op,       0x02},\n    {\"jal\",     jal_op,     0x03},\n    {\"beq\",     beq_op,     0x04},\n    {\"bne\",     bne_op,     0x05},\n    {\"blez\",    blez_op,    0x06},\n    {\"bgtz\",    bgtz_op,    0x07},\n    {\"addi\",    addi_op,    0x08},\n    {\"addiu\",   addiu_op,   0x09},\n    {\"slti\",    slti_op,    0x0A},\n    {\"sltiu\",   sltiu_op,   0x0B},\n    {\"andi\",    andi_op,    0x0C},\n    {\"ori\",     ori_op,     0x0D},\n    {\"xori\",    xori_op,    0x0E},\n    {\"lui\",     lui_op,     0x0F},\n    {\"cop0\",    cop0_op,    0x10},      /* indexed by RS field */\n    {\"cop1\",    cop1_op,    0x11},\n    {\"cop2\",    cop2_op,    0x12},\n    {\"cop1x\",   cop1_op,    0x13},\n    {\"beql\",    beql_op,    0x14},\n    {\"bnel\",    bnel_op,    0x15},\n    {\"blezl\",   blezl_op,   0x16},\n    {\"bgtzl\",   bgtzl_op,   0x17},\n    {\"daddi\",   unknown_op, 0x18},\n    {\"daddiu\",  unknown_op, 0x19},\n    {\"ldl\",     unknown_op, 0x1A},\n    {\"ldr\",     unknown_op, 0x1B},\n    {\"spec2\",   spec2_op,   0x1C},      /* indexed by FUNC field */\n    {\"jalx\",    jalx_op,    0x1D},\n    {\"undef\",   undef_op,   0x1E},\n    {\"spec3\",   spec3_op,   0x1F},      /* indexed by FUNC field */\n    {\"lb\",      lb_op,      0x20},\n    {\"lh\",      lh_op,      0x21},\n    {\"lwl\",     lwl_op,     0x22},\n    {\"lw\",      lw_op,      0x23},\n    {\"lbu\",     lbu_op,     0x24},\n    {\"lhu\",     lhu_op,     0x25},\n    {\"lwr\",     lwr_op,     0x26},\n    {\"lwu\",     unknown_op, 0x27},\n    {\"sb\",      sb_op,      0x28},\n    {\"sh\",      sh_op,      0x29},\n    {\"swl\",     swl_op,     0x2A},\n    {\"sw\",      sw_op,      0x2B},\n    {\"sdl\",     unknown_op, 0x2C},\n    {\"sdr\",     unknown_op, 0x2D},\n    {\"swr\",     swr_op,     0x2E},\n    {\"cache\",   cache_op,   0x2F},\n    {\"ll\",      ll_op,      0x30},\n    {\"lwc1\",    cop1_op,    0x31},\n    {\"lwc2\",    cop2_op,    0x32},\n    {\"pref\",    pref_op,    0x33},\n    {\"lld\",     unknown_op, 0x34},\n    {\"ldc1\",    cop1_op,    0x35},\n    {\"ldc2\",    cop2_op,    0x36},\n    {\"ld\",      unknown_op, 0x37},\n    {\"sc\",      sc_op,      0x38},\n    {\"swc1\",    cop1_op,    0x39},\n    {\"swc2\",    cop2_op,    0x3A},\n    {\"undef\",   undef_op,   0x3B},\n    {\"scd\",     unknown_op, 0x3C},\n    {\"sdc1\",    cop1_op,    0x3D},\n    {\"sdc2\",    cop2_op,    0x3E},\n    {\"sd\",      unknown_op, 0x3F},\n};\n\n/*\n * SPEC opcode: indexed by FUNC field.\n */\nstatic const struct mips_op_desc mips_spec_opcodes[] = {\n    {\"sll\",     sll_op,     0x00},\n    {\"movc\",\tmovc_op,\t0x01},\n    {\"srl\",\t\tsrl_op,\t\t0x02},\n    {\"sra\",\t\tsra_op,\t\t0x03},\n    {\"sllv\",\tsllv_op,\t0x04},\n    {\"?spec\",   undef_spec,\t0x05},\n    {\"srlv\",\tsrlv_op,\t0x06},\n    {\"srav\",\tsrav_op,\t0x07},\n    {\"jr\",\t\tjr_op,\t\t0x08},\n    {\"jalr\",\tjalr_op,\t0x09},\n    {\"movz\",\tmovz_op,\t0x0A},\n    {\"movn\",\tmovn_op,\t0x0B},\n    {\"syscall\",\tsyscall_op,\t0x0C},\n    {\"break\",\tbreak_op,\t0x0D},\n    {\"spim\",\tundef_spec,\t0x0E},\n    {\"sync\",\tsync_op,\t0x0F},\n    {\"mfhi\",\tmfhi_op,\t0x10},\n    {\"mthi\",\tmthi_op,\t0x11},\n    {\"mflo\",\tmflo_op,\t0x12},\n    {\"mtlo\",\tmtlo_op,\t0x13},\n    {\"dsllv\",\tunknown_op,\t0x14},\n    {\"?spec\",   undef_spec,\t0x15},\n    {\"dsrlv\",\tunknown_op,\t0x16},\n    {\"dsrav\",\tunknown_op,\t0x17},\n    {\"mult\",\tmult_op,\t0x18},\n    {\"multu\",\tmultu_op,\t0x19},\n    {\"div\",\t\tdiv_op,\t\t0x1A},\n    {\"divu\",\tdivu_op,\t0x1B},\n    {\"dmult\",\tunknown_op,\t0x1C},\n    {\"dmultu\",\tunknown_op,\t0x1D},\n    {\"ddiv\",\tunknown_op,\t0x1E},\n    {\"ddivu\",\tunknown_op,\t0x1F},\n    {\"add\",\t\tadd_op,\t\t0x20},\n    {\"addu\",\taddu_op,\t0x21},\n    {\"sub\",\t\tsub_op,\t\t0x22},\n    {\"subu\",\tsubu_op,\t0x23},\n    {\"and\",\t\tand_op,\t\t0x24},\n    {\"or\",\t\tor_op,\t\t0x25},\n    {\"xor\",\t\txor_op,\t\t0x26},\n    {\"nor\",\t\tnor_op,\t\t0x27},\n    {\"?spec\",   undef_spec,\t0x28},\n    {\"?spec\",   undef_spec,\t0x29},\n    {\"slt\",\t\tslt_op,\t\t0x2A},\n    {\"sltu\",\tsltu_op,\t0x2B},\n    {\"dadd\",\tunknown_op,\t0x2C},\n    {\"daddu\",\tunknown_op,\t0x2D},\n    {\"dsub\",\tunknown_op,\t0x2E},\n    {\"dsubu\",\tunknown_op,\t0x2F},\n    {\"tge\",\t\ttge_op,\t\t0x30},\n    {\"tgeu\",\ttgeu_op,\t0x31},\n    {\"tlt\",\t\ttlt_op,\t\t0x32},\n    {\"tltu\",\ttltu_op,\t0x33},\n    {\"teq\",\t\tteq_op,\t\t0x34},\n    {\"?spec\",   undef_spec,\t0x35},\n    {\"tne\",\t\ttne_op,\t\t0x36},\n    {\"?spec\",   undef_spec,\t0x37},\n    {\"dsll\",\tunknown_op,\t0x38},\n    {\"?spec\",   undef_spec,\t0x39},\n    {\"dsrl\",\tunknown_op,\t0x3A},\n    {\"dsra\",\tunknown_op,\t0x3B},\n    {\"dsll32\",\tunknown_op,\t0x3C},\n    {\"?spec\",   undef_spec,\t0x3D},\n    {\"dsrl32\",\tunknown_op,\t0x3E},\n    {\"dsra32\",\tunknown_op,\t0x3F}\n};\n\n/*\n * BCOND opcode: indexed by RT field.\n */\nstatic const struct mips_op_desc mips_bcond_opcodes[] = {\n    {\"bltz\",\tbltz_op,\t0x00},\n    {\"bgez\",\tbgez_op,\t0x01},\n    {\"bltzl\",\tbltzl_op,\t0x02},\n    {\"bgezl\",\tbgezl_op,\t0x03},\n    {\"spimi\",\tundef_bcond,0x04},\n    {\"?bcond\",  undef_bcond,0x05},\n    {\"?bcond\",  undef_bcond,0x06},\n    {\"?bcond\",  undef_bcond,0x07},\n    {\"tgei\",\ttgei_op,\t0x08},\n    {\"tgeiu\",\ttgeiu_op,\t0x09},\n    {\"tlti\",\ttlti_op,\t0x0A},\n    {\"tltiu\",\ttltiu_op,\t0x0B},\n    {\"teqi\",\tteqi_op,\t0x0C},\n    {\"?bcond\",  undef_bcond,0x0D},\n    {\"tnei\",\ttnei_op,\t0x0E},\n    {\"?bcond\",  undef_bcond,0x0F},\n    {\"bltzal\",\tbltzal_op,\t0x10},\n    {\"bgezal\",\tbgezal_op,\t0x11},\n    {\"bltzall\",\tbltzall_op,\t0x12},\n    {\"bgezall\",\tbgezall_op,\t0x13},\n    {\"?bcond\",  undef_bcond,0x14},\n    {\"?bcond\",  undef_bcond,0x15},\n    {\"?bcond\",  undef_bcond,0x16},\n    {\"?bcond\",  undef_bcond,0x17},\n    {\"?bcond\",  undef_bcond,0x18},\n    {\"?bcond\",  undef_bcond,0x19},\n    {\"?bcond\",  undef_bcond,0x1A},\n    {\"?bcond\",  undef_bcond,0x1B},\n    {\"?bcond\",  undef_bcond,0x1C},\n    {\"?bcond\",  undef_bcond,0x1D},\n    {\"?bcond\",  undef_bcond,0x1E},\n    {\"?bcond\",  undef_bcond,0x1F}\n};\n\n/*\n * COP0 opcode: indexed by RS field.\n */\nstatic const struct mips_op_desc mips_cop0_opcodes[] = {\n    {\"mfc0\",\tmfc0_op,\t0x0},\n    {\"dmfc0\",\tunknown_op,\t0x1},\n    {\"cfc0\",\tcfc0_op,\t0x2},\n    {\"?cop0\",   undef_cop0,\t0x3},\n    {\"mtc0\",\tmtc0_op,\t0x4},\n    {\"dmtc0\",\tunknown_op,\t0x5},\n    {\"?cop0\",   undef_cop0,\t0x6},\n    {\"?cop0\",   undef_cop0,\t0x7},\n    {\"?cop0\",   undef_cop0,\t0x8},\n    {\"?cop0\",   undef_cop0,\t0x9},\n    {\"?cop0\",   rdpgpr_op,\t0xa},\n    {\"?cop0\",   mfmc0_op,   0xb},\n    {\"?cop0\",   undef_cop0,\t0xc},\n    {\"?cop0\",   undef_cop0,\t0xd},\n    {\"wrpgpr\",  wrpgpr_op,\t0xe},\n    {\"?cop0\",   undef_cop0,\t0xf},\n    {\"tlb\",\t\ttlb_op,\t\t0x10},      /* indexed by FUNC field */\n    {\"?cop0\",   undef_cop0,\t0x11},\n    {\"?cop0\",   undef_cop0,\t0x12},\n    {\"?cop0\",   undef_cop0,\t0x13},\n    {\"?cop0\",   undef_cop0,\t0x14},\n    {\"?cop0\",   undef_cop0,\t0x15},\n    {\"?cop0\",   undef_cop0,\t0x16},\n    {\"?cop0\",   undef_cop0,\t0x17},\n    {\"?cop0\",   undef_cop0,\t0x18},\n    {\"?cop0\",   undef_cop0,\t0x19},\n    {\"?cop0\",   undef_cop0,\t0x1a},\n    {\"?cop0\",   undef_cop0,\t0x1b},\n    {\"?cop0\",   undef_cop0,\t0x1c},\n    {\"?cop0\",   undef_cop0,\t0x1d},\n    {\"?cop0\",   undef_cop0,\t0x1e},\n    {\"?cop0\",   undef_cop0,\t0x1f},\n};\n\n/*\n * SPEC2 opcode: indexed by FUNC field.\n */\nstatic const struct mips_op_desc mips_spec2_opcodes[] = {\n    {\"madd\",\tmadd_op,\t0x0},\n    {\"maddu\",\tmaddu_op,\t0x1},\n    {\"mul\",\t\tmul_op,\t\t0x2},\n    {\"?spec2\",\tundef_spec2,0x3},\n    {\"msub\",\tmsub_op,\t0x4},\n    {\"msubu\",\tmsubu_op,\t0x5},\n    {\"?spec2\",\tundef_spec2,0x6},\n    {\"?spec2\",\tundef_spec2,0x7},\n    {\"?spec2\",\tundef_spec2,0x8},\n    {\"?spec2\",\tundef_spec2,0x9},\n    {\"?spec2\",\tundef_spec2,0xa},\n    {\"?spec2\",\tundef_spec2,0xb},\n    {\"?spec2\",\tundef_spec2,0xc},\n    {\"?spec2\",\tundef_spec2,0xd},\n    {\"?spec2\",\tundef_spec2,0xe},\n    {\"?spec2\",\tundef_spec2,0xf},\n    {\"?spec2\",\tundef_spec2,0x10},\n    {\"?spec2\",\tundef_spec2,0x11},\n    {\"?spec2\",\tundef_spec2,0x12},\n    {\"?spec2\",\tundef_spec2,0x13},\n    {\"?spec2\",\tundef_spec2,0x14},\n    {\"?spec2\",\tundef_spec2,0x15},\n    {\"?spec2\",\tundef_spec2,0x16},\n    {\"?spec2\",\tundef_spec2,0x17},\n    {\"?spec2\",\tundef_spec2,0x18},\n    {\"?spec2\",\tundef_spec2,0x19},\n    {\"?spec2\",\tundef_spec2,0x1a},\n    {\"?spec2\",\tundef_spec2,0x1b},\n    {\"?spec2\",\tundef_spec2,0x1c},\n    {\"?spec2\",\tundef_spec2,0x1d},\n    {\"?spec2\",\tundef_spec2,0x1e},\n    {\"?spec2\",\tundef_spec2,0x1f},\n    {\"clz\",     clz_op,     0x20},\n    {\"clo\",     clo_op,     0x21},\n    {\"?spec2\",\tundef_spec2,0x22},\n    {\"?spec2\",\tundef_spec2,0x23},\n    {\"?spec2\",\tundef_spec2,0x24},\n    {\"?spec2\",\tundef_spec2,0x25},\n    {\"?spec2\",\tundef_spec2,0x26},\n    {\"?spec2\",\tundef_spec2,0x27},\n    {\"?spec2\",\tundef_spec2,0x28},\n    {\"?spec2\",\tundef_spec2,0x29},\n    {\"?spec2\",\tundef_spec2,0x2a},\n    {\"?spec2\",\tundef_spec2,0x2b},\n    {\"?spec2\",\tundef_spec2,0x2c},\n    {\"?spec2\",\tundef_spec2,0x2d},\n    {\"?spec2\",\tundef_spec2,0x2e},\n    {\"?spec2\",\tundef_spec2,0x2f},\n    {\"?spec2\",\tundef_spec2,0x30},\n    {\"?spec2\",\tundef_spec2,0x31},\n    {\"?spec2\",\tundef_spec2,0x32},\n    {\"?spec2\",\tundef_spec2,0x33},\n    {\"?spec2\",\tundef_spec2,0x34},\n    {\"?spec2\",\tundef_spec2,0x35},\n    {\"?spec2\",\tundef_spec2,0x36},\n    {\"?spec2\",\tundef_spec2,0x37},\n    {\"?spec2\",\tundef_spec2,0x38},\n    {\"?spec2\",\tundef_spec2,0x39},\n    {\"?spec2\",\tundef_spec2,0x3a},\n    {\"?spec2\",\tundef_spec2,0x3b},\n    {\"?spec2\",\tundef_spec2,0x3c},\n    {\"?spec2\",\tundef_spec2,0x3d},\n    {\"?spec2\",\tundef_spec2,0x3e},\n    {\"sdbbp\",\tsdbbp_op,   0x3f},\n};\n\n/*\n * SPEC3 opcode: indexed by FUNC field.\n */\nstatic const struct mips_op_desc mips_spec3_opcodes[] = {\n    {\"ext\",\t\text_op,     0x0},\n    {\"?spec3\",\tundef_spec3,0x1},\n    {\"?spec3\",\tundef_spec3,0x2},\n    {\"?spec3\",\tundef_spec3,0x3},\n    {\"ins\",     ins_op,     0x4},\n    {\"?spec3\",\tundef_spec3,0x5},\n    {\"?spec3\",\tundef_spec3,0x6},\n    {\"?spec3\",\tundef_spec3,0x7},\n    {\"?spec3\",\tundef_spec3,0x8},\n    {\"?spec3\",\tundef_spec3,0x9},\n    {\"?spec3\",\tundef_spec3,0xa},\n    {\"?spec3\",\tundef_spec3,0xb},\n    {\"?spec3\",\tundef_spec3,0xc},\n    {\"?spec3\",\tundef_spec3,0xd},\n    {\"?spec3\",\tundef_spec3,0xe},\n    {\"?spec3\",\tundef_spec3,0xf},\n    {\"?spec3\",\tundef_spec3,0x10},\n    {\"?spec3\",\tundef_spec3,0x11},\n    {\"?spec3\",\tundef_spec3,0x12},\n    {\"?spec3\",\tundef_spec3,0x13},\n    {\"?spec3\",\tundef_spec3,0x14},\n    {\"?spec3\",\tundef_spec3,0x15},\n    {\"?spec3\",\tundef_spec3,0x16},\n    {\"?spec3\",\tundef_spec3,0x17},\n    {\"?spec3\",\tundef_spec3,0x18},\n    {\"?spec3\",\tundef_spec3,0x19},\n    {\"?spec3\",\tundef_spec3,0x1a},\n    {\"?spec3\",\tundef_spec3,0x1b},\n    {\"?spec3\",\tundef_spec3,0x1c},\n    {\"?spec3\",\tundef_spec3,0x1d},\n    {\"?spec3\",\tundef_spec3,0x1e},\n    {\"?spec3\",\tundef_spec3,0x1f},\n    {\"bshfl\",\tbshfl_op,\t0x20},\n    {\"?spec3\",\tundef_spec3,0x21},\n    {\"?spec3\",\tundef_spec3,0x22},\n    {\"?spec3\",\tundef_spec3,0x23},\n    {\"?spec3\",\tundef_spec3,0x24},\n    {\"?spec3\",\tundef_spec3,0x25},\n    {\"?spec3\",\tundef_spec3,0x26},\n    {\"?spec3\",\tundef_spec3,0x27},\n    {\"?spec3\",\tundef_spec3,0x28},\n    {\"?spec3\",\tundef_spec3,0x29},\n    {\"?spec3\",\tundef_spec3,0x2a},\n    {\"?spec3\",\tundef_spec3,0x2b},\n    {\"?spec3\",\tundef_spec3,0x2c},\n    {\"?spec3\",\tundef_spec3,0x2d},\n    {\"?spec3\",\tundef_spec3,0x2e},\n    {\"?spec3\",\tundef_spec3,0x2f},\n    {\"?spec3\",\tundef_spec3,0x30},\n    {\"?spec3\",\tundef_spec3,0x31},\n    {\"?spec3\",\tundef_spec3,0x32},\n    {\"?spec3\",\tundef_spec3,0x33},\n    {\"?spec3\",\tundef_spec3,0x34},\n    {\"?spec3\",\tundef_spec3,0x35},\n    {\"?spec3\",\tundef_spec3,0x36},\n    {\"?spec3\",\tundef_spec3,0x37},\n    {\"?spec3\",\tundef_spec3,0x38},\n    {\"?spec3\",\tundef_spec3,0x39},\n    {\"?spec3\",\tundef_spec3,0x3a},\n    {\"?spec3\",\tundef_spec3,0x3b},\n    {\"?spec3\",\tundef_spec3,0x3c},\n    {\"?spec3\",\tundef_spec3,0x3d},\n    {\"?spec3\",\tundef_spec3,0x3e},\n    {\"?spec3\",\tundef_spec3,0x3f},\n};\n\n/*\n * TLB opcode: indexed by FUNC field.\n */\nstatic const struct mips_op_desc mips_tlb_opcodes[] = {\n    {\"?tlb\",\tundef_tlb,\t0x0},\n    {\"tlbr\",\ttlbr_op,\t0x1},\n    {\"tlbwi\",\ttlbwi_op,\t0x2},\n    {\"?tlb\",\tundef_tlb,\t0x3},\n    {\"?tlb\",\tundef_tlb,\t0x4},\n    {\"?tlb\",\tundef_tlb,\t0x5},\n    {\"tlbwi\",\ttlbwr_op,\t0x6},\n    {\"?tlb\",\tundef_tlb,\t0x7},\n    {\"tlbp\",\ttlbp_op,\t0x8},\n    {\"?tlb\",\tundef_tlb,\t0x9},\n    {\"?tlb\",\tundef_tlb,\t0xa},\n    {\"?tlb\",\tundef_tlb,\t0xb},\n    {\"?tlb\",\tundef_tlb,\t0xc},\n    {\"?tlb\",\tundef_tlb,\t0xd},\n    {\"?tlb\",\tundef_tlb,\t0xe},\n    {\"?tlb\",\tundef_tlb,\t0xf},\n    {\"?tlb\",\tundef_tlb,\t0x10},\n    {\"?tlb\",\tundef_tlb,\t0x11},\n    {\"?tlb\",\tundef_tlb,\t0x12},\n    {\"?tlb\",\tundef_tlb,\t0x13},\n    {\"?tlb\",\tundef_tlb,\t0x14},\n    {\"?tlb\",\tundef_tlb,\t0x15},\n    {\"?tlb\",\tundef_tlb,\t0x16},\n    {\"?tlb\",\tundef_tlb,\t0x17},\n    {\"eret\",\teret_op,\t0x18},\n    {\"?tlb\",\tundef_tlb,\t0x19},\n    {\"?tlb\",\tundef_tlb,\t0x1a},\n    {\"?tlb\",\tundef_tlb,\t0x1b},\n    {\"?tlb\",\tundef_tlb,\t0x1c},\n    {\"?tlb\",\tundef_tlb,\t0x1d},\n    {\"?tlb\",\tundef_tlb,\t0x1e},\n    {\"deret\",\tderet_op,\t0x1f},\n    {\"wait\",\twait_op,\t0x20},\n    {\"?tlb\",\tundef_tlb,\t0x21},\n    {\"?tlb\",\tundef_tlb,\t0x22},\n    {\"?tlb\",\tundef_tlb,\t0x23},\n    {\"?tlb\",\tundef_tlb,\t0x24},\n    {\"?tlb\",\tundef_tlb,\t0x25},\n    {\"?tlb\",\tundef_tlb,\t0x26},\n    {\"?tlb\",\tundef_tlb,\t0x27},\n    {\"?tlb\",\tundef_tlb,\t0x28},\n    {\"?tlb\",\tundef_tlb,\t0x29},\n    {\"?tlb\",\tundef_tlb,\t0x2a},\n    {\"?tlb\",\tundef_tlb,\t0x2b},\n    {\"?tlb\",\tundef_tlb,\t0x2c},\n    {\"?tlb\",\tundef_tlb,\t0x2d},\n    {\"?tlb\",\tundef_tlb,\t0x2e},\n    {\"?tlb\",\tundef_tlb,\t0x2f},\n    {\"?tlb\",\tundef_tlb,\t0x30},\n    {\"?tlb\",\tundef_tlb,\t0x31},\n    {\"?tlb\",\tundef_tlb,\t0x32},\n    {\"?tlb\",\tundef_tlb,\t0x33},\n    {\"?tlb\",\tundef_tlb,\t0x34},\n    {\"?tlb\",\tundef_tlb,\t0x35},\n    {\"?tlb\",\tundef_tlb,\t0x36},\n    {\"?tlb\",\tundef_tlb,\t0x37},\n    {\"?tlb\",\tundef_tlb,\t0x38},\n    {\"?tlb\",\tundef_tlb,\t0x39},\n    {\"?tlb\",\tundef_tlb,\t0x3a},\n    {\"?tlb\",\tundef_tlb,\t0x3b},\n    {\"?tlb\",\tundef_tlb,\t0x3c},\n    {\"?tlb\",\tundef_tlb,\t0x3d},\n    {\"?tlb\",\tundef_tlb,\t0x3e},\n    {\"?tlb\",\tundef_tlb,\t0x3f},\n};\n\nstatic int mips_exec_mips16e(cpu_mips_t* cpu, mips_insn_t instr)\n{\n    mips_insn_t extend = instr >> 16;\n    const m_va_t pc = cpu->pc;\n    m_va_t nextPc = pc + cpu->insn_len;\n    int res = 0;\n\n    instr &= 0xFFFF;\n\n#define xlat(r) ((r) | (((r) - 2) & 16))\n#define op      (instr >> 11)\n#define imm2    (instr & 0x3) // RRR/SHIFT-funct\n#define imm3    (instr & 0x7) // MOV32R rz\n#define imm4    (instr & 0xF) // SVRS framesize\n#define simm4   (imm4 - ((instr & 0x8) << 1))\n#define imm5    (instr & 0x1F) // MOVR32 r32\n#define imm8    ((uint8_t)instr)\n#define simm8   ((int8_t)instr)\n#define imm11   (instr & 0x7FF)\n#define simm11  (imm11 - ((instr & 0x400) << 1))\n#define imm15   (((extend & 0xF) << 11) | (extend & 0x7F0) | imm4) // EXT-RRI-A addiu\n#define simm15  (imm15 - ((extend & 0x8) << 12))\n#define imm16   (((extend & 0x1F) << 11) | (extend & 0x7E0) | imm5)\n#define simm16  ((int16_t)imm16)\n#define imm26   (((extend & 0x1F) << 21) | ((extend & 0x3E0) << 11) | (uint16_t)instr) // jal(x)\n#define rx      ((instr >> 8) & 0x7) // funct/SVRS\n#define ry      ((instr >> 5) & 0x7) // RR-funct\n#define rz      ((instr >> 2) & 0x7) // sa\n#define r32s    ((instr & 0x18) | ((instr >> 5) & 0x7)) // MOV32R split/swapped r32\n#define sa5     ((extend >> 6) & 0x1F) // EXT-SHIFT\n#define fmsz8   ((extend & 0xF0) | imm4) // EXT-SVRS\n#define aregs   (extend & 0xF) // EXT-SVRS\n#define xsregs  ((extend >> 8) & 0x7) // EXT-SVRS\n#define code6   ((instr >> 5) & 0x3F) // break, sdbbp\n\n    if ((extend >> 11) == 3) {\n        // jal(x) adr26<<2 (32-bit instruction; delay slot)\n        cpu->reg_set(cpu, MIPS_GPR_RA, nextPc + 3); // 2 for non-extended instruction in delay slot + 1 for ISA Mode\n        if (mips_exec_bdslot(cpu) == 0) {\n            nextPc = (nextPc & 0xF0000000) | (imm26 << 2);\n            cpu->pc = nextPc;\n            cpu->is_mips16e = (extend & 0x400) == 0; // jalx switches to MIPS32\n        }\n        res = 1;\n    } else if (!extend) {\n        switch (op) {\n        case 0: // addiu[sp] rx, sp, imm8<<2\n            cpu->reg_set(cpu, xlat(rx), cpu->gpr[MIPS_GPR_SP] + (imm8 << 2));\n            break;\n        case 1: // addiu[pc] rx, pc, imm8<<2\n            cpu->reg_set(cpu, xlat(rx), (pc + (imm8 << 2)) & 0xFFFFFFFC);\n            break;\n        case 2: // b ofs11<<1 (no delay slot)\n            nextPc += simm11 << 1;\n            cpu->pc = nextPc;\n            res = 1;\n            break;\n        case 4: // beqz rx, ofs8<<1 (no delay slot)\n            if (cpu->gpr[xlat(rx)] == 0)\n                nextPc += simm8 << 1;\n            cpu->pc = nextPc;\n            res = 1;\n            break;\n        case 5: // bnez rx, ofs8<<1 (no delay slot)\n            if (cpu->gpr[xlat(rx)] != 0)\n                nextPc += simm8 << 1;\n            cpu->pc = nextPc;\n            res = 1;\n            break;\n        case 6: // SHIFT\n            switch (imm2) {\n            case 0: // sll rx, ry, imm3\n                cpu->reg_set(cpu, xlat(rx), cpu->gpr[xlat(ry)] << (rz | ((rz - 1) & 8)));\n                break;\n            case 2: // srl rx, ry, imm3\n                cpu->reg_set(cpu, xlat(rx), cpu->gpr[xlat(ry)] >> (rz | ((rz - 1) & 8)));\n                break;\n            case 3: // sra rx, ry, imm3\n                cpu->reg_set(cpu, xlat(rx), (int32_t)cpu->gpr[xlat(ry)] >> (rz | ((rz - 1) & 8)));\n                break;\n            default:\n                goto lInvalidInstruction;\n            }\n            break;\n        case 8: // RRI-A addiu ry, rx, simm4\n            if (unlikely(instr & 0x10))\n                goto lInvalidInstruction;\n            cpu->reg_set(cpu, xlat(ry), cpu->gpr[xlat(rx)] + simm4);\n            break;\n        case 9: // addiu[8] rx, simm8\n            cpu->reg_set(cpu, xlat(rx), cpu->gpr[xlat(rx)] + simm8);\n            break;\n        case 10: // slti rx, imm8\n            cpu->reg_set(cpu, MIPS_GPR_T8, (int32_t)cpu->gpr[xlat(rx)] < (int32_t)imm8);\n            break;\n        case 11: // sltiu rx, imm8\n            cpu->reg_set(cpu, MIPS_GPR_T8, cpu->gpr[xlat(rx)] < imm8);\n            break;\n        case 12: // I8\n            switch (rx) {\n            case 0: // bteqz ofs8<<1 (no delay slot)\n                if (cpu->gpr[MIPS_GPR_T8] == 0)\n                    nextPc += simm8 << 1;\n                cpu->pc = nextPc;\n                res = 1;\n                break;\n            case 1: // btnez ofs8<<1 (no delay slot)\n                if (cpu->gpr[MIPS_GPR_T8] != 0)\n                    nextPc += simm8 << 1;\n                cpu->pc = nextPc;\n                res = 1;\n                break;\n            case 2: // sw[rasp] ra, ofs8<<2(sp)\n                res = mips_exec_memop2(cpu, MIPS_MEMOP_SW, MIPS_GPR_SP, imm8 << 2, MIPS_GPR_RA, FALSE);\n                break;\n            case 3: // ADJSP AKA addiu sp, simm8<<3\n                cpu->reg_set(cpu, MIPS_GPR_SP, cpu->gpr[MIPS_GPR_SP] + (simm8 << 3));\n                break;\n            case 4: // SVRS\n                if (instr & 0x80) { // save\n                    uint32_t temp = cpu->gpr[MIPS_GPR_SP], temp2 = temp - (imm4 ? imm4 * 8 : 128);\n                    if (instr & 0x40) // ra\n                        res = mips_exec_memop(cpu, MIPS_MEMOP_SW, temp -= 4, MIPS_GPR_RA, FALSE);\n                    if ((instr & 0x10) && !res) // s1\n                        res = mips_exec_memop(cpu, MIPS_MEMOP_SW, temp -= 4, MIPS_GPR_S1, FALSE);\n                    if ((instr & 0x20) && !res) // s0\n                        res = mips_exec_memop(cpu, MIPS_MEMOP_SW, temp -= 4, MIPS_GPR_S0, FALSE);\n                    if (!res)\n                        cpu->reg_set(cpu, MIPS_GPR_SP, temp2);\n                } else { // restore\n                    uint32_t temp = cpu->gpr[MIPS_GPR_SP] + (imm4 ? imm4 * 8 : 128), temp2 = temp;\n                    if (instr & 0x40) // ra\n                        res = mips_exec_memop(cpu, MIPS_MEMOP_LW, temp -= 4, MIPS_GPR_RA, TRUE);\n                    if ((instr & 0x10) && !res) // s1\n                        res = mips_exec_memop(cpu, MIPS_MEMOP_LW, temp -= 4, MIPS_GPR_S1, TRUE);\n                    if ((instr & 0x20) && !res) // s0\n                        res = mips_exec_memop(cpu, MIPS_MEMOP_LW, temp -= 4, MIPS_GPR_S0, TRUE);\n                    if (!res)\n                        cpu->reg_set(cpu, MIPS_GPR_SP, temp2);\n                }\n                break;\n            case 5: // move r32, rz (nop = move $0, $16)\n                cpu->reg_set(cpu, r32s, cpu->gpr[xlat(imm3)]);\n                cpu->gpr[0] = 0;\n                break;\n            case 7: // move ry, r32\n                cpu->reg_set(cpu, xlat(ry), cpu->gpr[imm5]);\n                break;\n            default:\n                goto lInvalidInstruction;\n            }\n            break;\n        case 13: // li rx, imm8\n            cpu->reg_set(cpu, xlat(rx), imm8);\n            break;\n        case 14: // cmpi rx, imm8\n            cpu->reg_set(cpu, MIPS_GPR_T8, cpu->gpr[xlat(rx)] ^ imm8);\n            break;\n        case 16: // lb ry, ofs5(rx)\n            res = mips_exec_memop2(cpu, MIPS_MEMOP_LB, xlat(rx), imm5, xlat(ry), TRUE);\n            break;\n        case 17: // lh ry, ofs5<<1(rx)\n            res = mips_exec_memop2(cpu, MIPS_MEMOP_LH, xlat(rx), imm5 << 1, xlat(ry), TRUE);\n            break;\n        case 18: // lw[sp] rx, ofs8<<2(sp)\n            res = mips_exec_memop2(cpu, MIPS_MEMOP_LW, MIPS_GPR_SP, imm8 << 2, xlat(rx), TRUE);\n            break;\n        case 19: // lw ry, ofs5<<2(rx)\n            res = mips_exec_memop2(cpu, MIPS_MEMOP_LW, xlat(rx), imm5 << 2, xlat(ry), TRUE);\n            break;\n        case 20: // lbu ry, ofs5(rx)\n            res = mips_exec_memop2(cpu, MIPS_MEMOP_LBU, xlat(rx), imm5, xlat(ry), TRUE);\n            break;\n        case 21: // lhu ry, ofs5<<1(rx)\n            res = mips_exec_memop2(cpu, MIPS_MEMOP_LHU, xlat(rx), imm5 << 1, xlat(ry), TRUE);\n            break;\n        case 22: // lw[pc] rx, ofs8<<2(pc)\n            res = mips_exec_memop(cpu, MIPS_MEMOP_LW, (pc + (imm8 << 2)) & 0xFFFFFFFC, xlat(rx), TRUE);\n            break;\n        case 24: // sb ry, ofs5(rx)\n            res = mips_exec_memop2(cpu, MIPS_MEMOP_SB, xlat(rx), imm5, xlat(ry), FALSE);\n            break;\n        case 25: // sh ry, ofs5<<1(rx)\n            res = mips_exec_memop2(cpu, MIPS_MEMOP_SH, xlat(rx), imm5 << 1, xlat(ry), FALSE);\n            break;\n        case 26: // sw[sp] rx, ofs8<<2(sp)\n            res = mips_exec_memop2(cpu, MIPS_MEMOP_SW, MIPS_GPR_SP, imm8 << 2, xlat(rx), FALSE);\n            break;\n        case 27: // sw ry, ofs5<<2(rx)\n            res = mips_exec_memop2(cpu, MIPS_MEMOP_SW, xlat(rx), imm5 << 2, xlat(ry), FALSE);\n            break;\n        case 28: // RRR\n            switch (imm2) {\n            case 1: // addu rz, rx, ry\n                cpu->reg_set(cpu, xlat(rz), cpu->gpr[xlat(rx)] + cpu->gpr[xlat(ry)]);\n                break;\n            case 3: // subu rz, rx, ry\n                cpu->reg_set(cpu, xlat(rz), cpu->gpr[xlat(rx)] - cpu->gpr[xlat(ry)]);\n                break;\n            default:\n                goto lInvalidInstruction;\n            }\n            break;\n        case 29: // RR\n            switch (imm5) {\n            case 0: // J(AL)R(C)\n                switch (ry) {\n                case 0: // jr rx (delay slot)\n                    nextPc = cpu->gpr[xlat(rx)];\n                    if (mips_exec_bdslot(cpu) == 0) {\n                        cpu->pc = nextPc & 0xFFFFFFFE;\n                        cpu->is_mips16e = nextPc & 1; // may switch to MIPS32\n                    }\n                    res = 1;\n                    break;\n                case 1: // jr ra (delay slot)\n                    if (unlikely(rx))\n                        goto lInvalidInstruction;\n                    nextPc = cpu->gpr[MIPS_GPR_RA];\n                    if (mips_exec_bdslot(cpu) == 0) {\n                        cpu->pc = nextPc & 0xFFFFFFFE;\n                        cpu->is_mips16e = nextPc & 1; // may switch to MIPS32\n                    }\n                    res = 1;\n                    break;\n                case 2: // jalr (delay slot)\n                    cpu->reg_set(cpu, MIPS_GPR_RA, nextPc + 3); // 2 for non-extended instruction in delay slot + 1 for ISA Mode\n                    nextPc = cpu->gpr[xlat(rx)];\n                    if (mips_exec_bdslot(cpu) == 0) {\n                        cpu->pc = nextPc & 0xFFFFFFFE;\n                        cpu->is_mips16e = nextPc & 1; // may switch to MIPS32\n                    }\n                    res = 1;\n                    break;\n                case 4: // jrc rx (no delay slot)\n                    nextPc = cpu->gpr[xlat(rx)];\n                    cpu->pc = nextPc & 0xFFFFFFFE;\n                    cpu->is_mips16e = nextPc & 1; // may switch to MIPS32\n                    res = 1;\n                    break;\n                case 5: // jrc ra (no delay slot)\n                    if (unlikely(rx))\n                        goto lInvalidInstruction;\n                    nextPc = cpu->gpr[MIPS_GPR_RA];\n                    cpu->pc = nextPc & 0xFFFFFFFE;\n                    cpu->is_mips16e = nextPc & 1; // may switch to MIPS32\n                    res = 1;\n                    break;\n                case 6: // jalrc (no delay slot)\n                    cpu->reg_set(cpu, MIPS_GPR_RA, nextPc + 1); // 1 for ISA Mode\n                    nextPc = cpu->gpr[xlat(rx)];\n                    cpu->pc = nextPc & 0xFFFFFFFE;\n                    cpu->is_mips16e = nextPc & 1; // may switch to MIPS32\n                    res = 1;\n                    break;\n                default:\n                    goto lInvalidInstruction;\n                }\n                break;\n            case 1: // sdbbp imm6\n                res = sdbbp_op(cpu, instr);\n                break;\n            case 2: // slt rx, ry\n                cpu->reg_set(cpu, MIPS_GPR_T8, (int32_t)cpu->gpr[xlat(rx)] < (int32_t)cpu->gpr[xlat(ry)]);\n                break;\n            case 3: // sltu rx, ry\n                cpu->reg_set(cpu, MIPS_GPR_T8, cpu->gpr[xlat(rx)] < cpu->gpr[xlat(ry)]);\n                break;\n            case 4: // sllv ry, rx\n                cpu->reg_set(cpu, xlat(ry), cpu->gpr[xlat(ry)] << (cpu->gpr[xlat(rx)] & 31));\n                break;\n            case 5: // break imm6\n                mips_exec_break(cpu, code6);\n                res = 1;\n                break;\n            case 6: // srlv ry, rx\n                cpu->reg_set(cpu, xlat(ry), cpu->gpr[xlat(ry)] >> (cpu->gpr[xlat(rx)] & 31));\n                break;\n            case 7: // srav ry, rx\n                cpu->reg_set(cpu, xlat(ry), (int32_t)cpu->gpr[xlat(ry)] >> (cpu->gpr[xlat(rx)] & 31));\n                break;\n            case 10: // cmp rx, ry\n                cpu->reg_set(cpu, MIPS_GPR_T8, cpu->gpr[xlat(rx)] ^ cpu->gpr[xlat(ry)]);\n                break;\n            case 11: // neg rx, ry\n                cpu->reg_set(cpu, xlat(rx), -cpu->gpr[xlat(ry)]);\n                break;\n            case 12: // and rx, ry\n                cpu->reg_set(cpu, xlat(rx), cpu->gpr[xlat(rx)] & cpu->gpr[xlat(ry)]);\n                break;\n            case 13: // or rx, ry\n                cpu->reg_set(cpu, xlat(rx), cpu->gpr[xlat(rx)] | cpu->gpr[xlat(ry)]);\n                break;\n            case 14: // xor rx, ry\n                cpu->reg_set(cpu, xlat(rx), cpu->gpr[xlat(rx)] ^ cpu->gpr[xlat(ry)]);\n                break;\n            case 15: // not rx, ry\n                cpu->reg_set(cpu, xlat(rx), ~cpu->gpr[xlat(ry)]);\n                break;\n            case 16: // mfhi rx\n                if (unlikely(ry))\n                    goto lInvalidInstruction;\n                cpu->reg_set(cpu, xlat(rx), cpu->hi);\n                break;\n            case 17: // CNVT\n                switch (ry) {\n                case 0: // zeb rx\n                    cpu->reg_set(cpu, xlat(rx), cpu->gpr[xlat(rx)] & 0xFF);\n                    break;\n                case 1: // zeh rx\n                    cpu->reg_set(cpu, xlat(rx), cpu->gpr[xlat(rx)] & 0xFFFF);\n                    break;\n                case 4: // seb rx\n                    cpu->reg_set(cpu, xlat(rx), (int8_t)cpu->gpr[xlat(rx)]);\n                    break;\n                case 5: // seh rx\n                    cpu->reg_set(cpu, xlat(rx), (int16_t)cpu->gpr[xlat(rx)]);\n                    break;\n                default:\n                    goto lInvalidInstruction;\n                }\n                break;\n            case 18: // mflo rx\n                if (unlikely(ry))\n                    goto lInvalidInstruction;\n                cpu->reg_set(cpu, xlat(rx), cpu->lo);\n                break;\n            case 24: { // mult rx, ry\n                int64_t p = (int64_t)(int32_t)cpu->gpr[xlat(rx)] * (int32_t)cpu->gpr[xlat(ry)];\n                cpu->lo = (uint32_t)p;\n                cpu->hi = (uint32_t)(p >> 32);\n                }\n                break;\n            case 25: { // multu rx, ry\n                uint64_t p = (uint64_t)cpu->gpr[xlat(rx)] * cpu->gpr[xlat(ry)];\n                cpu->lo = (uint32_t)p;\n                cpu->hi = (uint32_t)(p >> 32);\n                }\n                break;\n            case 26: // div rx, ry\n                if (!(cpu->gpr[xlat(ry)] == 0 ||\n                      (cpu->gpr[xlat(rx)] == 0x80000000 && cpu->gpr[xlat(ry)] == 0xFFFFFFFF))) {\n                    cpu->lo = (int32_t)cpu->gpr[xlat(rx)] / (int32_t)cpu->gpr[xlat(ry)];\n                    cpu->hi = (int32_t)cpu->gpr[xlat(rx)] % (int32_t)cpu->gpr[xlat(ry)];\n                }\n                break;\n            case 27: // divu rx, ry\n                if (cpu->gpr[xlat(ry)]) {\n                    cpu->lo = cpu->gpr[xlat(rx)] / cpu->gpr[xlat(ry)];\n                    cpu->hi = cpu->gpr[xlat(rx)] % cpu->gpr[xlat(ry)];\n                }\n                break;\n            default:\n                goto lInvalidInstruction;\n            }\n            break;\n        default:\n            goto lInvalidInstruction;\n        }\n        // ^^^ NON-EXTENDED ^^^\n    } else {\n        // vvv EXTENDED vvv\n        if (unlikely(cpu->is_in_bdslot))\n            goto lInvalidInstruction;\n        switch (op) {\n        case 0: // addiu[sp] rx, sp, simm16\n            if (unlikely(ry))\n                goto lInvalidInstruction;\n            cpu->reg_set(cpu, xlat(rx), cpu->gpr[MIPS_GPR_SP] + simm16);\n            break;\n        case 1: // addiu[pc] rx, pc, simm16\n            if (unlikely(ry))\n                goto lInvalidInstruction;\n            cpu->reg_set(cpu, xlat(rx), (pc & 0xFFFFFFFC) + simm16);\n            break;\n        case 2: // b ofs16<<1 (no delay slot)\n            if (unlikely(instr & 0x7E0))\n                goto lInvalidInstruction;\n            nextPc += simm16 << 1;\n            cpu->pc = nextPc;\n            res = 1;\n            break;\n        case 4: // beqz rx, ofs16<<1 (no delay slot)\n            if (unlikely(ry))\n                goto lInvalidInstruction;\n            if (cpu->gpr[xlat(rx)] == 0)\n                nextPc += simm16 << 1;\n            cpu->pc = nextPc;\n            res = 1;\n            break;\n        case 5: // bnez rx, ofs16<<1 (no delay slot)\n            if (unlikely(ry))\n                goto lInvalidInstruction;\n            if (cpu->gpr[xlat(rx)] != 0)\n                nextPc += simm16 << 1;\n            cpu->pc = nextPc;\n            res = 1;\n            break;\n        case 6: // SHIFT\n            switch (imm2) {\n            case 0: // sll rx, ry, imm5\n                if (unlikely((extend & 0x3F) | rz))\n                    goto lInvalidInstruction;\n                cpu->reg_set(cpu, xlat(rx), cpu->gpr[xlat(ry)] << sa5);\n                break;\n            case 2: // srl rx, ry, imm5\n                if (unlikely((extend & 0x3F) | rz))\n                    goto lInvalidInstruction;\n                cpu->reg_set(cpu, xlat(rx), cpu->gpr[xlat(ry)] >> sa5);\n                break;\n            case 3: // sra rx, ry, imm5\n                if (unlikely((extend & 0x3F) | rz))\n                    goto lInvalidInstruction;\n                cpu->reg_set(cpu, xlat(rx), (int32_t)cpu->gpr[xlat(ry)] >> sa5);\n                break;\n            default:\n                goto lInvalidInstruction;\n            }\n            break;\n        case 8: // RRI-A addiu ry, rx, simm15\n            if (unlikely(instr & 0x10))\n                goto lInvalidInstruction;\n            cpu->reg_set(cpu, xlat(ry), cpu->gpr[xlat(rx)] + simm15);\n            break;\n        case 9: // addiu rx, simm16\n            if (unlikely(ry))\n                goto lInvalidInstruction;\n            cpu->reg_set(cpu, xlat(rx), cpu->gpr[xlat(rx)] + simm16);\n            break;\n        case 10: // slti rx, simm16\n            if (unlikely(ry))\n                goto lInvalidInstruction;\n            cpu->reg_set(cpu, MIPS_GPR_T8, (int32_t)cpu->gpr[xlat(rx)] < simm16);\n            break;\n        case 11: // sltiu rx, simm16\n            if (unlikely(ry))\n                goto lInvalidInstruction;\n            cpu->reg_set(cpu, MIPS_GPR_T8, cpu->gpr[xlat(rx)] < (uint32_t)simm16);\n            break;\n        case 12: // I8\n            switch (rx) {\n            case 0: // bteqz ofs16<<1 (no delay slot)\n                if (unlikely(ry))\n                    goto lInvalidInstruction;\n                if (cpu->gpr[MIPS_GPR_T8] == 0)\n                    nextPc += simm16 << 1;\n                cpu->pc = nextPc;\n                res = 1;\n                break;\n            case 1: // btnez ofs16<<1 (no delay slot)\n                if (unlikely(ry))\n                    goto lInvalidInstruction;\n                if (cpu->gpr[MIPS_GPR_T8] != 0)\n                    nextPc += simm16 << 1;\n                cpu->pc = nextPc;\n                res = 1;\n                break;\n            case 2: // sw[rasp] ra, ofs16(sp)\n                if (unlikely(ry))\n                    goto lInvalidInstruction;\n                res = mips_exec_memop2(cpu, MIPS_MEMOP_SW, MIPS_GPR_SP, simm16, MIPS_GPR_RA, FALSE);\n                break;\n            case 3: // ADJSP AKA addiu sp, simm16\n                if (unlikely(ry))\n                    goto lInvalidInstruction;\n                cpu->reg_set(cpu, MIPS_GPR_SP, cpu->gpr[MIPS_GPR_SP] + simm16);\n                break;\n            case 4: { // SVRS\n                uint32_t astatic = 0;\n                uint32_t i;\n                switch (aregs) {\n                case 1: case 5: case 9: case 13: astatic = 1; break;\n                case 2: case 6: case 10: astatic = 2; break;\n                case 3: case 7: astatic = 3; break;\n                case 11: astatic = 4; break;\n                case 15:\n                    goto lInvalidInstruction; // TBD!!! or address error???\n                }\n                if (instr & 0x80) { // save\n                    uint32_t temp = cpu->gpr[MIPS_GPR_SP], temp2 = temp - fmsz8 * 8;\n                    uint32_t args = 0;\n                    switch (aregs) {\n                    case 4: case 5: case 6: case 7: args = 1; break;\n                    case 8: case 9: case 10: args = 2; break;\n                    case 12: case 13: args = 3; break;\n                    case 14: args = 4; break;\n                    case 15:\n                        goto lInvalidInstruction; // TBD!!! or address error???\n                    }\n                    for (i = 0; i < args && !res; i++)\n                        res = mips_exec_memop(cpu, MIPS_MEMOP_SW, temp + i * 4, 4 + i, FALSE);\n                    if ((instr & 0x40) && !res) // ra\n                        res = mips_exec_memop(cpu, MIPS_MEMOP_SW, temp -= 4, MIPS_GPR_RA, FALSE);\n                    for (i = xsregs; i && !res; i--)\n                        res = mips_exec_memop(cpu, MIPS_MEMOP_SW, temp -= 4, (i == 7) ? 30 : 17 + i, FALSE);\n                    if ((instr & 0x10) && !res) // s1\n                        res = mips_exec_memop(cpu, MIPS_MEMOP_SW, temp -= 4, MIPS_GPR_S1, FALSE);\n                    if ((instr & 0x20) && !res) // s0\n                        res = mips_exec_memop(cpu, MIPS_MEMOP_SW, temp -= 4, MIPS_GPR_S0, FALSE);\n                    for (i = 0; i < astatic && !res; i++)\n                        res = mips_exec_memop(cpu, MIPS_MEMOP_SW, temp -= 4, 7 - i, FALSE);\n                    if (!res)\n                        cpu->reg_set(cpu, MIPS_GPR_SP, temp2);\n                } else { // restore\n                    uint32_t temp2 = cpu->gpr[MIPS_GPR_SP] + fmsz8 * 8, temp = temp2;\n                    if (instr & 0x40) // ra\n                        res = mips_exec_memop(cpu, MIPS_MEMOP_LW, temp -= 4, MIPS_GPR_RA, TRUE);\n                    for (i = xsregs; i && !res; i--)\n                        res = mips_exec_memop(cpu, MIPS_MEMOP_LW, temp -= 4, (i == 7) ? 30 : 17 + i, TRUE);\n                    if ((instr & 0x10) && !res) // s1\n                        res = mips_exec_memop(cpu, MIPS_MEMOP_LW, temp -= 4, MIPS_GPR_S1, TRUE);\n                    if ((instr & 0x20) && !res) // s0\n                        res = mips_exec_memop(cpu, MIPS_MEMOP_LW, temp -= 4, MIPS_GPR_S0, TRUE);\n                    for (i = 0; i < astatic && !res; i++)\n                        res = mips_exec_memop(cpu, MIPS_MEMOP_LW, temp -= 4, 7 - i, TRUE);\n                    if (!res)\n                        cpu->reg_set(cpu, MIPS_GPR_SP, temp2);\n                }\n                }\n                break;\n            default:\n                goto lInvalidInstruction;\n            }\n            break;\n        case 13: // li rx, imm16\n            if (unlikely(ry))\n                goto lInvalidInstruction;\n            cpu->reg_set(cpu, xlat(rx), imm16);\n            break;\n        case 14: // cmpi rx, imm16\n            if (unlikely(ry))\n                goto lInvalidInstruction;\n            cpu->reg_set(cpu, MIPS_GPR_T8, cpu->gpr[xlat(rx)] ^ imm16);\n            break;\n        case 16: // lb ry, ofs16(rx)\n            res = mips_exec_memop2(cpu, MIPS_MEMOP_LB, xlat(rx), simm16, xlat(ry), TRUE);\n            break;\n        case 17: // lh ry, ofs16(rx)\n            res = mips_exec_memop2(cpu, MIPS_MEMOP_LH, xlat(rx), simm16, xlat(ry), TRUE);\n            break;\n        case 18: // lw[sp] rx, ofs16(sp)\n            if (unlikely(ry))\n                goto lInvalidInstruction;\n            res = mips_exec_memop2(cpu, MIPS_MEMOP_LW, MIPS_GPR_SP, simm16, xlat(rx), TRUE);\n            break;\n        case 19: // lw ry, ofs16(rx)\n            res = mips_exec_memop2(cpu, MIPS_MEMOP_LW, xlat(rx), simm16, xlat(ry), TRUE);\n            break;\n        case 20: // lbu ry, ofs16(rx)\n            res = mips_exec_memop2(cpu, MIPS_MEMOP_LBU, xlat(rx), simm16, xlat(ry), TRUE);\n            break;\n        case 21: // lhu ry, ofs16(rx)\n            res = mips_exec_memop2(cpu, MIPS_MEMOP_LHU, xlat(rx), simm16, xlat(ry), TRUE);\n            break;\n        case 22: // lw[pc] rx, ofs16(pc)\n            if (unlikely(ry))\n                goto lInvalidInstruction;\n            res = mips_exec_memop(cpu, MIPS_MEMOP_LW, (pc & 0xFFFFFFFC) + simm16, xlat(rx), TRUE);\n            break;\n        case 24: // sb ry, ofs16(rx)\n            res = mips_exec_memop2(cpu, MIPS_MEMOP_SB, xlat(rx), simm16, xlat(ry), FALSE);\n            break;\n        case 25: // sh ry, ofs16(rx)\n            res = mips_exec_memop2(cpu, MIPS_MEMOP_SH, xlat(rx), simm16, xlat(ry), FALSE);\n            break;\n        case 26: // sw[sp] rx, ofs16(sp)\n            if (unlikely(ry))\n                goto lInvalidInstruction;\n            res = mips_exec_memop2(cpu, MIPS_MEMOP_SW, MIPS_GPR_SP, simm16, xlat(rx), FALSE);\n            break;\n        case 27: // sw ry, ofs16(rx)\n            res = mips_exec_memop2(cpu, MIPS_MEMOP_SW, xlat(rx), simm16, xlat(ry), FALSE);\n            break;\n        default:\n            goto lInvalidInstruction;\n        }\n    }\n\n    return res;\n\nlInvalidInstruction:\n    unknown_op(cpu, (extend << 16) | instr);\n    return 1;\n#undef xlat\n#undef op\n#undef imm2\n#undef imm3\n#undef imm4\n#undef simm4\n#undef imm5\n#undef imm8\n#undef simm8\n#undef imm11\n#undef simm11\n#undef imm15\n#undef simm15\n#undef imm16\n#undef simm16\n#undef imm26\n#undef rx\n#undef ry\n#undef rz\n#undef r32s\n#undef sa5\n#undef fmsz8\n#undef aregs\n#undef xsregs\n#undef code6\n}\n"
  },
  {
    "path": "tools/virtualmips/mips_cp0.c",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)\n *\n * MIPS Coprocessor 0 (System Coprocessor) implementation.\n * We don't use the JIT here, since there is no high performance needed.\n */\n\n  /*\n   * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n   *\n   * This file is part of the virtualmips distribution.\n   * See LICENSE file for terms of the license.\n   *\n   */\n\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <assert.h>\n\n#include \"mips.h\"\n#include \"mips_memory.h\"\n#include \"mips_cp0.h\"\n#include \"cpu.h\"\n#include \"vm.h\"\n\n/* MIPS cp0 registers names */\nchar *mips_cp0_reg_names[MIPS64_CP0_REG_NR] = {\n    \"index\",\n    \"random\",\n    \"entry_lo\",\n    \"cp0_r3\",\n    \"context\",\n    \"cp0_r5\",\n    \"wired\",\n    \"cp0_r7\",\n    \"badvaddr\",\n    \"cp0_r9\",\n    \"entry_hi\",\n    \"cp0_r11\",\n    \"status\",\n    \"cause\",\n    \"epc\",\n    \"prid\",\n    \"dreg\",\n    \"depc\",\n    \"cp0_r18\",\n    \"cp0_r19\",\n    \"cctl\",\n    \"cp0_r21\",\n    \"cp0_r22\",\n    \"cp0_r23\",\n    \"cp0_r24\",\n    \"cp0_r25\",\n    \"cp0_r26\",\n    \"cp0_r27\",\n    \"cp0_r28\",\n    \"cp0_r29\",\n    \"cp0_r30\",\n    \"desave\",\n};\n\n/* Get value of random register */\nstatic inline u_int mips_cp0_get_random_reg (cpu_mips_t * cpu)\n{\n    int random_value;\n    random_value =\n        (int) ((double) (cpu->cp0.tlb_entries) * arc4random () / (RAND_MAX + 1.0));\n    return random_value;\n}\n\n/* Get a cp0 register (fast version) */\nstatic inline m_cp0_reg_t mips_cp0_get_reg_fast (cpu_mips_t * cpu,\n    u_int cp0_reg, u_int sel)\n{\n    mips_cp0_t *cp0 = &cpu->cp0;\n    switch (cp0_reg) {\n\n    case MIPS_CP0_RANDOM:\n        return (mips_cp0_get_random_reg (cpu));\n\n    case MIPS_CP0_CONFIG:\n        if (! ((1 << sel) & cp0->config_usable)) {\nunimpl:     fprintf (stderr,\n                \"Read from unimplemented CP0 register %s\\n\",\n                cp0reg_name (cp0_reg, sel));\n            return 0;\n        }\n        return cp0->config_reg[sel];\n\n    case MIPS_CP0_STATUS:\n        switch (sel) {\n        case 0:                         /* Status */\n            return cp0->reg[cp0_reg];\n        case 1:                         /* IntCtl */\n            return cp0->intctl_reg;\n        case 2:                         /* SRSCtl */\n            return 0;\n        }\n        goto unimpl;\n\n    case MIPS_CP0_PRID:\n        switch (sel) {\n        case 0:                         /* PRId */\n            return cp0->reg[cp0_reg];\n        case 1:                         /* EBase */\n            return cp0->ebase_reg;\n        }\n        goto unimpl;\n\n    default:\n        if (sel != 0)\n            goto unimpl;\n        return cp0->reg[cp0_reg];\n    }\n}\n\n/* Get a cp0 register */\nm_cp0_reg_t mips_cp0_get_reg (cpu_mips_t * cpu, u_int cp0_reg)\n{\n    return (mips_cp0_get_reg_fast (cpu, cp0_reg, 0));\n}\n\nvoid fastcall mips_cp0_exec_mfc0_fastcall (cpu_mips_t * cpu,\n    mips_insn_t insn)\n{\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    int sel = bits (insn, 0, 2);\n\n    cpu->reg_set (cpu, rt, sign_extend (mips_cp0_get_reg_fast (cpu, rd, sel), 32));\n}\n\n/* MFC0 */\nvoid mips_cp0_exec_mfc0 (cpu_mips_t * cpu, u_int gp_reg, u_int cp0_reg,\n    u_int sel)\n{\n    cpu->reg_set (cpu, gp_reg,\n        sign_extend (mips_cp0_get_reg_fast (cpu, cp0_reg, sel), 32));\n}\n\nvoid fastcall mips_cp0_exec_mtc0_fastcall (cpu_mips_t * cpu,\n    mips_insn_t insn)\n{\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    int sel = bits (insn, 0, 2);\n\n    mips_cp0_set_reg (cpu, rd, sel, cpu->gpr[rt] & 0xffffffff);\n}\n\nvoid mips_cp0_exec_mtc0 (cpu_mips_t * cpu, u_int gp_reg, u_int cp0_reg,\n    u_int sel)\n{\n    mips_cp0_set_reg (cpu, cp0_reg, sel, cpu->gpr[gp_reg] & 0xffffffff);\n}\n\n/* Set a cp0 register */\nvoid mips_cp0_set_reg (cpu_mips_t * cpu, u_int cp0_reg, u_int sel,\n    m_uint32_t val)\n{\n    mips_cp0_t *cp0 = &cpu->cp0;\n\n    if (cpu->vm->debug_level > 2) {\n        extern const char *cp0reg_name (unsigned cp0reg, unsigned sel);\n        printf (\"        %s := %08x\\n\", cp0reg_name (cp0_reg, sel), val);\n        fflush (stdout);\n    }\n    switch (cp0_reg) {\n    case MIPS_CP0_STATUS:\n        switch (sel) {\n        case 0:                         /* Status */\n            cp0->reg[cp0_reg] = val;\n            break;\n        case 1:                         /* IntCtl */\n            cp0->intctl_reg = val;\n            break;\n        case 2:                         /* SRSCtl */\n            /* Read-only */\n            break;\n        default:\n            goto unimpl;\n        }\n        break;\n\n    case MIPS_CP0_PRID:\n        switch (sel) {\n        case 0:                         /* PRId */\n            /* read only register */\n            break;\n        case 1:                         /* EBase */\n            cp0->ebase_reg = (val & 0x3ffff000) | 0x80000000;\n            break;\n        default:\n            goto unimpl;\n        }\n        break;\n\n    case MIPS_CP0_RANDOM:\n    case MIPS_CP0_WIRED:\n        /* read only registers */\n        if (sel != 0)\n            goto unimpl;\n        break;\n\n    case MIPS_CP0_COMPARE:\n        // Write to compare will clear timer interrupt\n        if (sel != 0)\n            goto unimpl;\n        clear_timer_irq (cpu);\n        cp0->reg[cp0_reg] = val;\n        break;\n\n    case MIPS_CP0_CONFIG:\n        if (! ((1 << sel) & cp0->config_usable))\n            goto unimpl;\n        switch (sel) {\n        case 0:                         /* Config */\n            /* only bits 0:2 are writable */\n            val &= 3;\n            cp0->config_reg[sel] &= 0xfffffffc;\n            cp0->config_reg[sel] |= val;\n            break;\n        default:\n            /* Config1-Config7 registers are read-only. */\n            break;\n        }\n        break;\n\n    case MIPS_CP0_DEBUG:\n        /* Only some bits of Debug register are writable. */\n        if (sel != 0)\n            goto unimpl;\n        cp0->reg[cp0_reg] &= ~MIPS_CP0_DEBUG_WMASK;\n        cp0->reg[cp0_reg] |= val & MIPS_CP0_DEBUG_WMASK;\n        break;\n\n    default:\n        if (sel != 0) {\nunimpl:     fprintf (stderr,\n                \"Write to unimplemented register %s\\n\",\n                cp0reg_name (cp0_reg, sel));\n            break;\n        }\n        cp0->reg[cp0_reg] = val;\n    }\n}\n\n/* Get the VPN2 mask */\nm_cp0_reg_t mips_cp0_get_vpn2_mask (cpu_mips_t * cpu)\n{\n    if (cpu->addr_mode == 64)\n        return ((m_cp0_reg_t) MIPS_TLB_VPN2_MASK_64);\n    else\n        return ((m_cp0_reg_t) MIPS_TLB_VPN2_MASK_32);\n}\n\n/* TLBP: Probe a TLB entry */\nvoid fastcall mips_cp0_exec_tlbp (cpu_mips_t * cpu)\n{\n    mips_cp0_t *cp0 = &cpu->cp0;\n\n    m_uint32_t vpn2, hi_reg, vpn2_mask, page_mask, hi_addr;\n    tlb_entry_t *entry;\n    u_int asid;\n    int i;\n    vpn2_mask = mips_cp0_get_vpn2_mask (cpu);\n    hi_reg = cp0->reg[MIPS_CP0_TLB_HI];\n    asid = hi_reg & MIPS_TLB_ASID_MASK;\n    vpn2 = hi_reg & vpn2_mask;\n\n    cp0->reg[MIPS_CP0_INDEX] = 0x80000000;\n    for (i = 0; i < cp0->tlb_entries; i++) {\n        entry = &cp0->tlb[i];\n        page_mask = ~(entry->mask + 0x1FFF);\n        hi_addr = entry->hi & mips_cp0_get_vpn2_mask (cpu);\n        if (((vpn2 & page_mask) == (hi_addr & page_mask)) &&\n            (((entry->hi & MIPS_TLB_G_MASK))\n                || ((entry->hi & MIPS_TLB_ASID_MASK) == asid))) {\n            cp0->reg[MIPS_CP0_INDEX] = i;\n            cp0->reg[MIPS_CP0_INDEX] &= ~0x80000000ULL;\n            return;\n#if DEBUG_TLB_ACTIVITY\n            cpu_log (cpu, \"\", \"CPU: CP0_TLBP returned %x\\n\", i);\n#endif\n        }\n    }\n}\n\n/* Get the page size corresponding to a page mask */\nstatic inline m_uint32_t get_page_size (m_uint32_t page_mask)\n{\n    return ((page_mask + 0x2000) >> 1);\n}\n\nvoid mips_cp0_unmap_tlb_to_mts (cpu_mips_t * cpu, int index)\n{\n    m_va_t v0_addr, v1_addr;\n    m_uint32_t page_size;\n    tlb_entry_t *entry;\n\n    entry = &cpu->cp0.tlb[index];\n\n    page_size = get_page_size (entry->mask);\n    v0_addr = entry->hi & mips_cp0_get_vpn2_mask (cpu);\n    v1_addr = v0_addr + page_size;\n\n    if (entry->lo0 & MIPS_TLB_V_MASK)\n        cpu->mts_unmap (cpu, v0_addr, page_size, MTS_ACC_T, index);\n\n    if (entry->lo1 & MIPS_TLB_V_MASK)\n        cpu->mts_unmap (cpu, v1_addr, page_size, MTS_ACC_T, index);\n}\n\n/* TLBW: Write a TLB entry */\nstatic forced_inline void mips_cp0_exec_tlbw (cpu_mips_t * cpu, u_int index)\n{\n    mips_cp0_t *cp0 = &cpu->cp0;\n    tlb_entry_t *entry;\n\n    if (index < cp0->tlb_entries) {\n        entry = &cp0->tlb[index];\n\n        /* Unmap the old entry if it was valid */\n        mips_cp0_unmap_tlb_to_mts (cpu, index);\n\n        entry->mask = cp0->reg[MIPS_CP0_PAGEMASK];\n        entry->hi = cp0->reg[MIPS_CP0_TLB_HI];\n        entry->lo0 = cp0->reg[MIPS_CP0_TLB_LO_0];\n        entry->lo1 = cp0->reg[MIPS_CP0_TLB_LO_1];\n        /* if G bit is set in lo0 and lo1, set it in hi */\n        if ((entry->lo0 & entry->lo1) & MIPS_CP0_LO_G_MASK)\n            entry->hi |= MIPS_TLB_G_MASK;\n\n        /* Clear G bit in TLB lo0 and lo1 */\n        entry->lo0 &= ~MIPS_CP0_LO_G_MASK;\n        entry->lo1 &= ~MIPS_CP0_LO_G_MASK;\n    }\n}\n\n/* TLBWI: Write Indexed TLB entry */\nvoid fastcall mips_cp0_exec_tlbwi (cpu_mips_t * cpu)\n{\n    m_uint32_t index;\n\n/*FIX ME:\n  May be a bug in tlblhandler of 2.6.11.  by yajin.\n\n IN kernel, TLBL exception handler run a tlbp and then tlbw without checking tlbp is successful.\n assume\n 2aaa8a9c  lw  t0,(s0)\n 1.First we need to load instruction in 2aaa8a9c. A tlbl exception occurs. tlbp failed and tlbw\n write tlb entry into entry x.\n 2. And then exceute the instruction. load a data from a memory. A tlbl exception occurs. tlbp failed\n and tlbw write tlb entry into entry x.  and return to pc=2aaa8a9c and do the process 1.\n This will cause a infinate loop.\n\n In fact, we need to check whether is successfully. If success, tlbw. otherwise tlbwr.\n\n So I first check whether last tlbp failed(check highest bit of index register). If tlbp failed, write\n tlbwr instead tlbw. It works well.\n\t */\n\n    if (cpu->cp0.reg[MIPS_CP0_INDEX] & 0x80000000) {\n        mips_cp0_exec_tlbwr (cpu);\n    } else {\n\n        index = cpu->cp0.reg[MIPS_CP0_INDEX];\n        mips_cp0_exec_tlbw (cpu, index);\n    }\n\n}\n\n/* TLBWR: Write Random TLB entry */\nvoid fastcall mips_cp0_exec_tlbwr (cpu_mips_t * cpu)\n{\n    mips_cp0_exec_tlbw (cpu, mips_cp0_get_random_reg (cpu));\n}\n\n/* TLBR: Read Indexed TLB entry */\nvoid fastcall mips_cp0_exec_tlbr (cpu_mips_t * cpu)\n{\n    mips_cp0_t *cp0 = &cpu->cp0;\n    tlb_entry_t *entry;\n    u_int index;\n\n    index = cp0->reg[MIPS_CP0_INDEX];\n\n#if DEBUG_TLB_ACTIVITY\n    cpu_log (cpu, \"TLB\", \"CP0_TLBR: Read entry %u.\\n\", index);\n#endif\n\n    if (index < cp0->tlb_entries) {\n        entry = &cp0->tlb[index];\n\n        cp0->reg[MIPS_CP0_PAGEMASK] = entry->mask;\n        cp0->reg[MIPS_CP0_TLB_HI] = entry->hi;\n        cp0->reg[MIPS_CP0_TLB_LO_0] = entry->lo0;\n        cp0->reg[MIPS_CP0_TLB_LO_1] = entry->lo1;\n        if (entry->hi & MIPS_TLB_G_MASK) {\n            cp0->reg[MIPS_CP0_TLB_LO_0] |= MIPS_CP0_LO_G_MASK;\n            cp0->reg[MIPS_CP0_TLB_LO_1] |= MIPS_CP0_LO_G_MASK;\n            cp0->reg[MIPS_CP0_TLB_HI] &= ~MIPS_TLB_G_MASK;\n        }\n\n    }\n}\n\n#ifndef SIM_PIC32\nint mips_cp0_tlb_lookup (cpu_mips_t *cpu, m_va_t vaddr, mts_map_t *res)\n{\n    mips_cp0_t *cp0 = &cpu->cp0;\n\n    m_va_t vpn_addr, hi_addr, page_mask, page_size;\n    tlb_entry_t *entry;\n    u_int asid;\n    int i;\n\n    vpn_addr = vaddr & mips_cp0_get_vpn2_mask (cpu);\n\n    asid = cp0->reg[MIPS_CP0_TLB_HI] & MIPS_TLB_ASID_MASK;\n    for (i = 0; i < cp0->tlb_entries; i++) {\n        entry = &cp0->tlb[i];\n        page_mask = ~(entry->mask + 0x1FFF);\n        hi_addr = entry->hi & mips_cp0_get_vpn2_mask (cpu);\n\n        if (((vpn_addr & page_mask) == (hi_addr & page_mask)) &&\n            ((entry->hi & MIPS_TLB_G_MASK)\n                || ((entry->hi & MIPS_TLB_ASID_MASK) == asid))) {\n            page_size = get_page_size (entry->mask);\n            if ((vaddr & page_size) == 0) {\n                res->tlb_index = i;\n\n                res->vaddr = vaddr & MIPS_MIN_PAGE_MASK;\n                res->paddr = (entry->lo0 & MIPS_TLB_PFN_MASK) << 6;\n                res->paddr += ((res->vaddr) & (page_size - 1));\n                //res->paddr += ( (vaddr  )& (page_size-1));\n\n                res->paddr &= cpu->addr_bus_mask;\n\n                res->dirty =\n                    (entry->lo0 & MIPS_TLB_D_MASK) >> MIPS_TLB_D_SHIT;\n                res->valid =\n                    (entry->lo0 & MIPS_TLB_V_MASK) >> MIPS_TLB_V_SHIT;\n                res->asid = asid;\n                res->g_bit = entry->hi & MIPS_TLB_G_MASK;\n\n                return (TRUE);\n            } else {\n                res->tlb_index = i;\n                res->vaddr = vaddr & MIPS_MIN_PAGE_MASK;\n                res->paddr = (entry->lo1 & MIPS_TLB_PFN_MASK) << 6;\n                res->paddr += ((res->vaddr) & (page_size - 1));\n                //res->paddr += ( (vaddr  )& (page_size-1));\n                res->paddr &= cpu->addr_bus_mask;\n\n                res->dirty =\n                    (entry->lo1 & MIPS_TLB_D_MASK) >> MIPS_TLB_D_SHIT;\n                res->valid =\n                    (entry->lo1 & MIPS_TLB_V_MASK) >> MIPS_TLB_V_SHIT;\n\n                res->asid = asid;\n                res->g_bit = entry->hi & MIPS_TLB_G_MASK;\n\n                return (TRUE);\n            }\n        }\n    }\n    return FALSE;\n}\n#endif\n\n#if 0\n/* Write page size in buffer */\nstatic char *get_page_size_str (char *buffer, size_t len,\n    m_uint32_t page_mask)\n{\n    m_uint32_t page_size;\n\n    page_size = get_page_size (page_mask);\n\n    /* Mb ? */\n    if (page_size >= (1024 * 1024))\n        snprintf (buffer, len, \"%uMB\", page_size >> 20);\n    else\n        snprintf (buffer, len, \"%uKB\", page_size >> 10);\n\n    return buffer;\n}\n\n/* Dump the specified TLB entry */\nvoid mips_tlb_dump_entry (cpu_mips_t * cpu, u_int index)\n{\n    tlb_entry_t *entry;\n    char buffer[256];\n\n    entry = &cpu->cp0.tlb[index];\n\n    /* virtual Address */\n    printf (\" %2d: vaddr=0x%8.8\" LL \"x \", index,\n        entry->hi & mips_cp0_get_vpn2_mask (cpu));\n\n    /* global or ASID */\n    if ((entry->lo0 & MIPS_TLB_G_MASK) && ((entry->lo1 & MIPS_TLB_G_MASK)))\n        printf (\"(global)    \");\n    else\n        printf (\"(asid 0x%2.2\" LL \"x) \", entry->hi & MIPS_TLB_ASID_MASK);\n\n    /* 1st page: Lo0 */\n    printf (\"p0=\");\n\n    if (entry->lo0 & MIPS_TLB_V_MASK)\n        printf (\"0x%9.9\" LL \"x\", (entry->lo0 & MIPS_TLB_PFN_MASK) << 6);\n    else\n        printf (\"(invalid)  \");\n\n    printf (\" %c \", (entry->lo0 & MIPS_TLB_D_MASK) ? 'D' : ' ');\n\n    /* 2nd page: Lo1 */\n    printf (\"p1=\");\n\n    if (entry->lo1 & MIPS_TLB_V_MASK)\n        printf (\"0x%9.9\" LL \"x\", (entry->lo1 & MIPS_TLB_PFN_MASK) << 6);\n    else\n        printf (\"(invalid)  \");\n\n    printf (\" %c \", (entry->lo1 & MIPS_TLB_D_MASK) ? 'D' : ' ');\n\n    /* page size */\n    printf (\" (%s)\\n\", get_page_size_str (buffer, sizeof (buffer),\n            entry->mask));\n\n}\n\n/* Human-Readable dump of the TLB */\nvoid mips_tlb_dump (cpu_mips_t * cpu)\n{\n    cpu_mips_t *mcpu = (cpu);\n    u_int i;\n\n    printf (\"TLB dump:\\n\");\n    for (i = 0; i < mcpu->cp0.tlb_entries; i++)\n        mips_tlb_dump_entry (mcpu, i);\n\n    printf (\"\\n\");\n}\n\n/* Raw dump of the TLB */\nvoid mips_tlb_raw_dump (cpu_mips_t * cpu)\n{\n    cpu_mips_t *mcpu = (cpu);\n    tlb_entry_t *entry;\n    u_int i;\n\n    printf (\"TLB dump:\\n\");\n\n    for (i = 0; i < mcpu->cp0.tlb_entries; i++) {\n        entry = &mcpu->cp0.tlb[i];\n        printf (\" %2d: mask=0x%16.16\" LL \"x hi=0x%16.16\" LL \"x \"\n            \"lo0=0x%16.16\" LL \"x lo1=0x%16.16\" LL \"x\\n\", i, entry->mask,\n            entry->hi, entry->lo0, entry->lo1);\n    }\n    printf (\"\\n\");\n}\n#endif\n"
  },
  {
    "path": "tools/virtualmips/mips_cp0.h",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)\n */\n /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#ifndef __CP0_H__\n#define __CP0_H__\n\n#include \"utils.h\"\n#include \"system.h\"\n\n/* CP0 register names */\nextern char *mips_cp0_reg_names[];\n\nm_cp0_reg_t mips_cp0_get_reg (cpu_mips_t * cpu, u_int cp0_reg);\nvoid fastcall mips_cp0_exec_mfc0_fastcall (cpu_mips_t * cpu,\n    mips_insn_t insn);\nvoid mips_cp0_exec_mfc0 (cpu_mips_t * cpu, u_int gp_reg, u_int cp0_reg,\n    u_int sel);\nvoid mips_cp0_exec_mtc0 (cpu_mips_t * cpu, u_int gp_reg, u_int cp0_reg,\n    u_int sel);\nvoid fastcall mips_cp0_exec_mtc0_fastcall (cpu_mips_t * cpu,\n    mips_insn_t insn);\nvoid mips_cp0_set_reg (cpu_mips_t * cpu, u_int cp0_reg, u_int sel,\n    m_uint32_t val);\nm_cp0_reg_t mips_cp0_get_vpn2_mask (cpu_mips_t * cpu);\nvoid fastcall mips_cp0_exec_tlbp (cpu_mips_t * cpu);\nvoid fastcall mips_cp0_exec_tlbwi (cpu_mips_t * cpu);\nvoid fastcall mips_cp0_exec_tlbwr (cpu_mips_t * cpu);\nvoid fastcall mips_cp0_exec_tlbr (cpu_mips_t * cpu);\nint mips_cp0_tlb_lookup (cpu_mips_t * cpu, m_va_t vaddr, mts_map_t * res);\nvoid mips_tlb_dump (cpu_mips_t * cpu);\nvoid mips_tlb_raw_dump (cpu_mips_t * cpu);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/mips_exec.c",
    "content": "/*\n * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#include \"cpu.h\"\n#include \"vm.h\"\n#include \"mips_exec.h\"\n#include \"mips_fdd.h\"\n#include \"vp_timer.h\"\n\ncpu_mips_t *current_cpu;\n\n/*select different main loop*/\nvoid *mips_exec_run_cpu (cpu_mips_t * cpu)\n{\n#ifdef _USE_JIT_\n    if (cpu->vm->jit_use) {\n        mips_jit_init (cpu);\n        return mips_jit_run_cpu (cpu);\n    } else\n#endif\n        return mips_cpu_fdd (cpu);\n}\n"
  },
  {
    "path": "tools/virtualmips/mips_exec.h",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)\n */\n /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#ifndef __MIPS64_EXEC_H__\n#define __MIPS64_EXEC_H__\n\n#include \"utils.h\"\n#include \"system.h\"\n\n#include \"mips_jit.h\"\n\nstruct mips_op_desc {\n    char *opname;\n    int (*func) (cpu_mips_t *, mips_insn_t);\n    m_uint16_t num;\n};\n\nstruct mips_jit_desc {\n    char *opname;\n    int (*emit_func) (cpu_mips_t *, mips_jit_tcb_t *, mips_insn_t);\n    m_uint16_t num;\n    int delay_slot;             /*can this instruction in delay slot. 1:can. 0: can not */\n};\n\n/* Run MIPS code in step-by-step mode */\nvoid *mips_exec_run_cpu (cpu_mips_t * cpu);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/mips_fdd.c",
    "content": "/*\n * This is the basic fetch-decode-dispatch(fdd) routine.\n * Emulation speed is slow but easy to debug.\n *\n * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <string.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <sys/mman.h>\n#include <fcntl.h>\n#include <signal.h>\n#include <sys/ioctl.h>\n#include <time.h>\n\n#include \"cpu.h\"\n#include \"vm.h\"\n#include \"mips_exec.h\"\n#include \"mips_memory.h\"\n#include \"mips.h\"\n#include \"mips_cp0.h\"\n#include \"debug.h\"\n#include \"vp_timer.h\"\n#include \"mips_hostalarm.h\"\n\n//#ifdef  _USE_FDD_\n\nstatic const struct mips_op_desc mips_opcodes[];\nstatic const struct mips_op_desc mips_spec_opcodes[];\nstatic const struct mips_op_desc mips_bcond_opcodes[];\nstatic const struct mips_op_desc mips_cop0_opcodes[];\nstatic const struct mips_op_desc mips_spec2_opcodes[];\nstatic const struct mips_op_desc mips_spec3_opcodes[];\nstatic const struct mips_op_desc mips_tlb_opcodes[];\n\nstatic int mips_exec_mips16e (cpu_mips_t * cpu,\n    mips_insn_t instruction);\n\nextern cpu_mips_t *current_cpu;\n\n/*for emulation performance check*/\n#ifdef DEBUG_MHZ\n#define C_1000MHZ 1000000000\nstruct timeval pstart, pend;\nfloat timeuse, performance;\nm_uint64_t instructions_executed = 0;\n#endif\n\nstatic void forced_inline mips_main_loop_wait (cpu_mips_t * cpu,\n    int timeout)\n{\n    vp_run_timers (&active_timers[VP_TIMER_REALTIME],\n        vp_get_clock (rt_clock));\n}\n\nstatic int forced_inline mips_exec_memop (cpu_mips_t * cpu, int memop,\n    m_va_t vaddr, u_int dst_reg, int keep_ll_bit)\n{\n    mips_memop_fn fn;\n\n    if (!keep_ll_bit)\n        cpu->ll_bit = 0;\n    fn = cpu->mem_op_fn[memop];\n    return (fn (cpu, vaddr, dst_reg));\n}\n\n/* Execute a memory operation (2) */\nstatic int forced_inline mips_exec_memop2 (cpu_mips_t * cpu, int memop,\n    u_int base_reg, int offset, u_int dst_reg, int keep_ll_bit)\n{\n    m_va_t vaddr = cpu->gpr[base_reg] + sign_extend (offset, 16);\n    return mips_exec_memop (cpu, memop, vaddr, dst_reg, keep_ll_bit);\n}\n\nextern void mips_access_special (cpu_mips_t * cpu, m_va_t vaddr, m_uint32_t mask,\n    u_int op_code, u_int op_type, u_int op_size, m_reg_t * data, u_int * exc);\n\n/* Fetch an instruction */\nstatic int mips_fetch_instruction_inner (cpu_mips_t * cpu,\n    m_va_t pc, mips_insn_t * insn, u_int size)\n{\n    m_va_t exec_page;\n    m_uint32_t offset;\n\n    if (unlikely (pc & (size - 1))) {\n        u_int exc = 0;\n        mips_access_special(cpu, pc, MTS_ACC_AE, MIPS_MEMOP_LOOKUP, MTS_READ, size, NULL, &exc);\n        return (1);\n    }\n\n    exec_page = pc & ~(m_va_t) MIPS_MIN_PAGE_IMASK;\n    if (unlikely (exec_page != cpu->njm_exec_page)) {\n        cpu->njm_exec_ptr = cpu->mem_op_lookup (cpu, exec_page);\n    }\n\n    if (cpu->njm_exec_ptr == NULL) {\n        //exception when fetching instruction\n        return (1);\n    }\n    cpu->njm_exec_page = exec_page;\n    offset = (pc & MIPS_MIN_PAGE_IMASK) >> 2;\n    *insn = vmtoh32 (cpu->njm_exec_ptr[offset]);\n    if (unlikely (size == 2)) {\n        if (pc & 2) {\n            *insn >>= 16;\n        } else {\n            *insn &= 0xFFFF;\n        }\n    }\n//  printf (\"(%08x) %08x\\n\", pc, *insn);\n    return (0);\n}\n\nint mips_fetch_instruction (cpu_mips_t * cpu,\n    m_va_t pc, mips_insn_t * insn)\n{\n    int res;\n    if (unlikely(cpu->is_mips16e)) {\n        res = mips_fetch_instruction_inner(cpu, pc, insn, 2);\n        if (unlikely(res)) {\n            return res;\n        }\n        if (unlikely((*insn >> 11) == 0x1E || (*insn >> 11) == 3)) {\n            /* 4-byte extended instruction or jal(x): 2 more bytes needed */\n            mips_insn_t i;\n            res = mips_fetch_instruction_inner(cpu, pc + 2, &i, 2);\n            if (unlikely(res)) {\n                return res;\n            }\n            *insn = (*insn << 16) | i;\n            cpu->insn_len = 4;\n        } else {\n            /* 2-byte instruction */\n            cpu->insn_len = 2;\n        }\n    } else {\n        res = mips_fetch_instruction_inner(cpu, pc, insn, 4);\n        cpu->insn_len = 4;\n    }\n    return res;\n}\n\n/* Execute a single instruction */\nstatic forced_inline int mips_exec_single_instruction (cpu_mips_t * cpu,\n    mips_insn_t instruction)\n{\n#ifdef DEBUG_MHZ\n    if (unlikely (instructions_executed == 0)) {\n        gettimeofday (&pstart, NULL);\n    }\n    instructions_executed++;\n    if (unlikely (instructions_executed == C_1000MHZ)) {\n        gettimeofday (&pend, NULL);\n        timeuse =\n            1000000 * (pend.tv_sec - pstart.tv_sec) + pend.tv_usec -\n            pstart.tv_usec;\n        timeuse /= 1000000;\n        performance = 1000 / timeuse;\n        printf (\"Used Time:%f seconds.  %f MHZ\\n\", timeuse, performance);\n        exit (1);\n    }\n#endif\n    if (unlikely(cpu->is_mips16e)) {\n        return mips_exec_mips16e (cpu, instruction);\n    } else {\n        register uint op;\n        op = MAJOR_OP (instruction);\n        return mips_opcodes[op].func (cpu, instruction);\n    }\n}\n\n/* Single-step execution */\nvoid fastcall mips_exec_single_step (cpu_mips_t * cpu,\n    mips_insn_t instruction)\n{\n    int res;\n    int insn_len = cpu->insn_len;\n\n    res = mips_exec_single_instruction (cpu, instruction);\n    /* Normal flow ? */\n    if (likely (!res))\n        cpu->pc += insn_len;\n}\n\nvoid dumpregs (cpu_mips_t *cpu)\n{\n\tprintf (\"                t0 = %8x   s0 = %8x   t8 = %8x   lo = %8x\\n\",\n\t\tcpu->gpr[8], cpu->gpr[16], cpu->gpr[24], cpu->lo);\n\tprintf (\"at = %8x   t1 = %8x   s1 = %8x   t9 = %8x   hi = %8x\\n\",\n\t\tcpu->gpr[1], cpu->gpr[9], cpu->gpr[17], cpu->gpr[25], cpu->hi);\n\tprintf (\"v0 = %8x   t2 = %8x   s2 = %8x               status = %8x\\n\",\n\t\tcpu->gpr[2], cpu->gpr[10], cpu->gpr[18], cpu->cp0.reg[MIPS_CP0_STATUS]);\n\tprintf (\"v1 = %8x   t3 = %8x   s3 = %8x\\n\",\n\t\tcpu->gpr[3], cpu->gpr[11], cpu->gpr[19]);\n\tprintf (\"a0 = %8x   t4 = %8x   s4 = %8x   gp = %8x   pc = %8x\\n\",\n\t\tcpu->gpr[4], cpu->gpr[12], cpu->gpr[20], cpu->gpr[28], cpu->pc);\n\tprintf (\"a1 = %8x   t5 = %8x   s5 = %8x   sp = %8x\\n\",\n\t\tcpu->gpr[5], cpu->gpr[13], cpu->gpr[21], cpu->gpr[29]);\n\tprintf (\"a2 = %8x   t6 = %8x   s6 = %8x   fp = %8x\\n\",\n\t\tcpu->gpr[6], cpu->gpr[14], cpu->gpr[22], cpu->gpr[30]);\n\tprintf (\"a3 = %8x   t7 = %8x   s7 = %8x   ra = %8x\\n\",\n\t\tcpu->gpr[7], cpu->gpr[15], cpu->gpr[23], cpu->gpr[31]);\n}\n\n\n/*\n * MIPS64 fetch->decode->dispatch main loop\n */\nvoid *mips_cpu_fdd (cpu_mips_t * cpu)\n{\n    mips_insn_t insn = 0;\n    int res;\n\n    cpu->cpu_thread_running = TRUE;\n    current_cpu = cpu;\n\n    mips_init_host_alarm ();\n\nstart_cpu:\n    for (;;) {\n        int insn_len;\n\n        if (unlikely (cpu->state != CPU_STATE_RUNNING))\n            break;\n\n        if (unlikely ((cpu->pause_request) & CPU_INTERRUPT_EXIT)) {\n            cpu->state = CPU_STATE_PAUSING;\n            break;\n        }\n\n        /* Reset \"zero register\" (for safety) */\n        cpu->gpr[0] = 0;\n\n        /* Check IRQ */\n        if (unlikely (cpu->irq_pending)) {\n            mips_trigger_irq (cpu);\n            continue;\n        }\n        /* Fetch  the instruction */\n        res = mips_fetch_instruction (cpu, cpu->pc, &insn);\n        insn_len = cpu->insn_len;\n\n        if (cpu->vm->trace_address == cpu->pc) {\n            /* Trace address. */\n            printf (\"*** %08x: %08x \", cpu->pc, insn);\n            print_mips (cpu->pc, insn, cpu->insn_len, cpu->is_mips16e, stdout);\n            printf (\"\\n\");\n            dumpregs (cpu);\n        }\n\n        if (unlikely (res == 1)) {\n            /*exception when fetching instruction */\n            printf (\"%08x: exception when fetching instruction\\n\", cpu->pc);\n            if (cpu->pc == 0)\n                exit(-1);\n            continue;\n        }\n        if (unlikely ((cpu->vm->mipsy_debug_mode)\n                && ((cpu_hit_breakpoint (cpu->vm, cpu->pc) == SUCCESS)\n                    || (cpu->vm->gdb_interact_sock == -1)\n                    || (cpu->vm->mipsy_break_nexti == MIPS_BREAKANYCPU)))) {\n            if (mips_debug (cpu->vm, 1)) {\n                continue;\n            }\n        }\n        if (cpu->vm->debug_level > 2 || (cpu->vm->debug_level > 1 &&\n            (cpu->cp0.reg[MIPS_CP0_STATUS] & MIPS_CP0_STATUS_UM) &&\n            ! (cpu->cp0.reg[MIPS_CP0_STATUS] & MIPS_CP0_STATUS_EXL)))\n        {\n            /* Print instructions in user mode. */\n            printf (\"%08x:       \", cpu->pc);\n            if (insn_len == 2)\n                printf (\"    %04x        \", insn);\n            else\n                printf (\"%08x        \", insn);\n\n            print_mips (cpu->pc, insn, insn_len, cpu->is_mips16e, stdout);\n            printf (\"\\n\");\n            fflush (stdout);\n#if 0\n            m_uint32_t dummy;\n            unsigned char *p = physmem_get_hptr (cpu->vm, 0x00010000, 0, MTS_READ, &dummy);\n            if (p) {\n                unsigned nbytes;\n                for (nbytes=0x40; nbytes>0; p+=16, nbytes-=16) {\n                    printf (\"%08x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\\n\",\n                        (unsigned) p, p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],\n                        p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]);\n                }\n            }\n#endif\n        }\n\n        res = mips_exec_single_instruction (cpu, insn);\n\n        /* Normal flow ? */\n        if (likely (!res))\n            cpu->pc += insn_len;\n    }\n\n    while (cpu->cpu_thread_running) {\n        switch (cpu->state) {\n        case CPU_STATE_RUNNING:\n            cpu->state = CPU_STATE_RUNNING;\n            goto start_cpu;\n\n        case CPU_STATE_HALTED:\n            cpu->cpu_thread_running = FALSE;\n            break;\n        case CPU_STATE_RESTARTING:\n            cpu->state = CPU_STATE_RESTARTING;\n            /*Just waiting for cpu restart. */\n            break;\n        case CPU_STATE_PAUSING:\n            /*main loop must wait for me. heihei :) */\n            mips_main_loop_wait (cpu, 0);\n            cpu->state = CPU_STATE_RUNNING;\n            cpu->pause_request &= ~CPU_INTERRUPT_EXIT;\n            /*start cpu again */\n            goto start_cpu;\n\n        }\n    }\n    return NULL;\n}\n\n/* Execute the instruction in delay slot */\nstatic forced_inline int mips_exec_bdslot (cpu_mips_t * cpu)\n{\n    mips_insn_t insn;\n    int res = 0;\n    int insn_len = cpu->insn_len;\n\n    cpu->is_in_bdslot = 1;\n\n    /* Fetch the instruction in delay slot */\n    res = mips_fetch_instruction (cpu, cpu->pc + insn_len, &insn);\n    if (res == 1) {\n        /*exception when fetching instruction */\n        cpu->is_in_bdslot = 0;\n        return (1);\n    }\n\n    cpu->is_in_bdslot = 1;\n\n    if (cpu->vm->debug_level > 2 || (cpu->vm->debug_level > 1 &&\n        (cpu->cp0.reg[MIPS_CP0_STATUS] & MIPS_CP0_STATUS_UM) &&\n        ! (cpu->cp0.reg[MIPS_CP0_STATUS] & MIPS_CP0_STATUS_EXL)))\n    {\n        /* Print instructions in user mode. */\n        printf (\"%08x:       %08x        \", cpu->pc + insn_len, insn);\n        print_mips (cpu->pc, insn, insn_len, cpu->is_mips16e, stdout);\n        printf (\"\\n\");\n        fflush (stdout);\n    }\n\n    /* Execute the instruction */\n    res = mips_exec_single_instruction (cpu, insn);\n\n    cpu->is_in_bdslot = 0;\n    return res;\n}\n\n#include \"mips_codetable.c\"\n\n//#endif\n"
  },
  {
    "path": "tools/virtualmips/mips_fdd.h",
    "content": "/*\n * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n *\n */\n\n#ifndef __MIPS64_FDD_H__\n#define __MIPS64_FDD_H__\n\n#include \"utils.h\"\n#include \"system.h\"\n\nvoid *mips_cpu_fdd (cpu_mips_t * cpu);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/mips_hostalarm.c",
    "content": "#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <string.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <sys/mman.h>\n#include <fcntl.h>\n#include <signal.h>\n#include <sys/ioctl.h>\n#include <time.h>\n#include <errno.h>\n#ifdef __linux__\n#include <linux/rtc.h>\n#endif\n\n#include \"cpu.h\"\n#include \"vm.h\"\n#include \"mips_exec.h\"\n#include \"mips_memory.h\"\n#include \"mips.h\"\n#include \"mips_cp0.h\"\n#include \"debug.h\"\n#include \"vp_timer.h\"\n#include \"mips_hostalarm.h\"\n\n/*code from qemu*/\n\n#define TFR(expr) do { if ((expr) != -1) break; } while (errno == EINTR)\nstatic struct qemu_alarm_timer *alarm_timer;\n\nextern cpu_mips_t *current_cpu;\n\n#define RTC_FREQ 1024\n\n#define ALARM_FLAG_DYNTICKS  0x1\n#define ALARM_FLAG_EXPIRED   0x2\n\n/* TODO: MIN_TIMER_REARM_US should be optimized */\n#define MIN_TIMER_REARM_US 250\n\nstruct hpet_info {\n    unsigned long hi_ireqfreq;  /* Hz */\n    unsigned long hi_flags;     /* information */\n    unsigned short hi_hpet;\n    unsigned short hi_timer;\n};\n\n#define\tHPET_INFO_PERIODIC\t0x0001  /* timer is periodic */\n\n#define\tHPET_IE_ON\t_IO('h', 0x01)  /* interrupt on */\n#define\tHPET_IE_OFF\t_IO('h', 0x02)  /* interrupt off */\n#define\tHPET_INFO\t_IOR('h', 0x03, struct hpet_info)\n#define\tHPET_EPI\t_IO('h', 0x04)  /* enable periodic */\n#define\tHPET_DPI\t_IO('h', 0x05)  /* disable periodic */\n#define\tHPET_IRQFREQ\t_IOW('h', 0x6, unsigned long)   /* IRQFREQ usec */\n\n/*\n * Host alarm, fired once 1 ms.\n * It will find whether a timer has been expired.\n * If so, run timers.\n */\nvoid host_alarm_handler (int host_signum)\n{\n    if (unlikely (current_cpu->state != CPU_STATE_RUNNING))\n        return;\n\n    if (vp_timer_expired (active_timers[VP_TIMER_REALTIME],\n            vp_get_clock (rt_clock))) {\n        /* Tell cpu we need to pause because timer out */\n        current_cpu->pause_request |= CPU_INTERRUPT_EXIT;\n    }\n\n    /* Check count and compare */\n#define KHZ 80000\n    current_cpu->cp0.reg[MIPS_CP0_COUNT] += KHZ / 2;\n    if (current_cpu->cp0.reg[MIPS_CP0_COMPARE] != 0) {\n        if (current_cpu->cp0.reg[MIPS_CP0_COUNT] >=\n            current_cpu->cp0.reg[MIPS_CP0_COMPARE]) {\n                set_timer_irq (current_cpu);\n        }\n    }\n/*printf (\"-- count = %u, compare = %u\\n\", current_cpu->cp0.reg[MIPS_CP0_COUNT], current_cpu->cp0.reg[MIPS_CP0_COMPARE]);*/\n\n    host_alarm (current_cpu, KHZ);\n}\n\n#ifdef __linux__\n\nstatic void enable_sigio_timer (int fd)\n{\n    struct sigaction act;\n\n    /* timer signal */\n    sigfillset (&act.sa_mask);\n    act.sa_flags = 0;\n    act.sa_handler = host_alarm_handler;\n\n    sigaction (SIGIO, &act, NULL);\n    fcntl (fd, F_SETFL, O_ASYNC);\n    fcntl (fd, F_SETOWN, getpid ());\n}\n\nstatic int hpet_start_timer (struct qemu_alarm_timer *t)\n{\n    struct hpet_info info;\n    int r, fd;\n\n    fd = open (\"/dev/hpet\", O_RDONLY);\n    if (fd < 0)\n        return -1;\n\n    /* Set frequency */\n    r = ioctl (fd, HPET_IRQFREQ, RTC_FREQ);\n    if (r < 0) {\n        fprintf (stderr,\n            \"Could not configure '/dev/hpet' to have a 1024Hz timer. This is not a fatal\\n\"\n            \"error, but for better emulation accuracy type:\\n\"\n            \"'echo 1024 > /proc/sys/dev/hpet/max-user-freq' as root.\\n\");\n        goto fail;\n    }\n\n    /* Check capabilities */\n    r = ioctl (fd, HPET_INFO, &info);\n    if (r < 0)\n        goto fail;\n\n    /* Enable periodic mode */\n    r = ioctl (fd, HPET_EPI, 0);\n    if (info.hi_flags && (r < 0))\n        goto fail;\n\n    /* Enable interrupt */\n    r = ioctl (fd, HPET_IE_ON, 0);\n    if (r < 0)\n        goto fail;\n\n    enable_sigio_timer (fd);\n    t->priv = (void *) (long) fd;\n\n    return 0;\n  fail:\n    close (fd);\n    return -1;\n}\n\nstatic void hpet_stop_timer (struct qemu_alarm_timer *t)\n{\n    int fd = (long) t->priv;\n\n    close (fd);\n}\n\nstatic int rtc_start_timer (struct qemu_alarm_timer *t)\n{\n    int rtc_fd;\n\n    TFR (rtc_fd = open (\"/dev/rtc\", O_RDONLY));\n    if (rtc_fd < 0)\n        return -1;\n    if (ioctl (rtc_fd, RTC_IRQP_SET, RTC_FREQ) < 0) {\n        fprintf (stderr,\n            \"Could not configure '/dev/rtc' to have a 1024 Hz timer. This is not a fatal\\n\"\n            \"error, but for better emulation accuracy either use a 2.6 host Linux kernel or\\n\"\n            \"type 'echo 1024 > /proc/sys/dev/rtc/max-user-freq' as root.\\n\");\n        goto fail;\n    }\n    if (ioctl (rtc_fd, RTC_PIE_ON, 0) < 0) {\n      fail:\n        close (rtc_fd);\n        return -1;\n    }\n\n    enable_sigio_timer (rtc_fd);\n\n    t->priv = (void *) (long) rtc_fd;\n\n    return 0;\n}\n\nstatic void rtc_stop_timer (struct qemu_alarm_timer *t)\n{\n    int rtc_fd = (long) t->priv;\n\n    close (rtc_fd);\n}\n\n#endif /* __linux__ */\n\nstatic int unix_start_timer (struct qemu_alarm_timer *t)\n{\n    struct sigaction act;\n    struct itimerval itv;\n    int err;\n\n    /* timer signal */\n    sigfillset (&act.sa_mask);\n    act.sa_flags = 0;\n    act.sa_handler = host_alarm_handler;\n\n    sigaction (SIGALRM, &act, NULL);\n\n    itv.it_interval.tv_sec = 0;\n    /* for i386 kernel 2.6 to get 1 ms */\n    itv.it_interval.tv_usec = 999;\n    itv.it_value.tv_sec = 0;\n    itv.it_value.tv_usec = 10 * 1000;\n\n    err = setitimer (ITIMER_REAL, &itv, NULL);\n    if (err)\n        return -1;\n\n    return 0;\n}\n\nstatic void unix_stop_timer (struct qemu_alarm_timer *t)\n{\n    struct itimerval itv;\n\n    memset (&itv, 0, sizeof (itv));\n    setitimer (ITIMER_REAL, &itv, NULL);\n}\n\nstatic struct qemu_alarm_timer alarm_timers[] = {\n#ifdef __linux__\n    /* HPET - if available - is preferred */\n    {\"hpet\", 0, hpet_start_timer, hpet_stop_timer, NULL, NULL},\n    /* ...otherwise try RTC */\n    {\"rtc\", 0, rtc_start_timer, rtc_stop_timer, NULL, NULL},\n#endif\n    {\"unix\", 0, unix_start_timer, unix_stop_timer, NULL, NULL},\n    {NULL,}\n};\n\n/*host alarm*/\nvoid mips_init_host_alarm (void)\n{\n    struct qemu_alarm_timer *t;\n    int i, err = -1;\n\n    for (i = 0; alarm_timers[i].name; i++) {\n        t = &alarm_timers[i];\n        err = t->start (t);\n        if (! err)\n            break;\n    }\n/*#define DEBUG_HOST_ALARM*/\n#ifdef DEBUG_HOST_ALARM\n    printf (\"--- Using %s timer\\n\", alarm_timers[i].name);\n#endif\n    if (err) {\n        fprintf (stderr, \"Unable to find any suitable alarm timer.\\n\");\n        fprintf (stderr, \"Terminating\\n\");\n        exit (1);\n    }\n    alarm_timer = t;\n}\n"
  },
  {
    "path": "tools/virtualmips/mips_hostalarm.h",
    "content": "#ifndef __MIPS64_HOSTALARM_H__\n#define __MIPS64_HOSTALARM_H__\n\nstruct qemu_alarm_timer {\n    char const *name;\n    unsigned int flags;\n\n    int (*start) (struct qemu_alarm_timer * t);\n    void (*stop) (struct qemu_alarm_timer * t);\n    void (*rearm) (struct qemu_alarm_timer * t);\n    void *priv;\n};\n\nvoid mips_init_host_alarm (void);\nvoid host_alarm (cpu_mips_t *cpu, int nclocks);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/mips_jit.c",
    "content": "/*\n * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n *\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <string.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <sys/mman.h>\n#include <signal.h>\n#include <fcntl.h>\n#include <assert.h>\n#include <setjmp.h>\n#include <sys/mman.h>\n#include <errno.h>\n\n#include \"cpu.h\"\n#include \"vm.h\"\n#include \"mips_exec.h\"\n#include \"mips_memory.h\"\n#include \"mips.h\"\n#include \"mips_cp0.h\"\n#include \"debug.h\"\n#include \"vp_timer.h\"\n#include \"mips_hostalarm.h\"\n#include \"x86_trans.h\"\n\n#ifdef _USE_JIT_\n\nextern struct mips_jit_desc mips_jit[];\nextern cpu_mips_t *current_cpu;\n\njmp_buf run_jmp;\nstatic void forced_inline mips_main_loop_wait (cpu_mips_t * cpu,\n    int timeout)\n{\n    vp_run_timers (&active_timers[VP_TIMER_REALTIME],\n        vp_get_clock (rt_clock));\n}\n\n/* Initialize the JIT structure */\nint mips_jit_init (cpu_mips_t * cpu)\n{\n    insn_exec_page_t *cp;\n    u_char *cp_addr;\n    u_int area_size;\n    size_t len;\n    int i;\n\n    /* Physical mapping for executable pages */\n    len = MIPS_JIT_PC_HASH_SIZE * sizeof (void *);\n    cpu->exec_blk_map = m_memalign (4096, len);\n    memset (cpu->exec_blk_map, 0, len);\n\n    /* Get area size */\n    area_size = MIPS_EXEC_AREA_SIZE;\n\n    /* Create executable page area */\n    cpu->exec_page_area_size = area_size * 1048576;\n    cpu->exec_page_area = mmap (NULL, cpu->exec_page_area_size,\n        PROT_EXEC | PROT_READ | PROT_WRITE,\n        MAP_SHARED | MAP_ANON, -1, (off_t) 0);\n\n    if (!cpu->exec_page_area) {\n        fprintf (stderr,\n            \"mips_jit_init: unable to create exec area (size %lu)\\n\",\n            (u_long) cpu->exec_page_area_size);\n        return (-1);\n    }\n\n    /* Carve the executable page area */\n    cpu->exec_page_count = cpu->exec_page_area_size / MIPS_JIT_BUFSIZE;\n\n    cpu->exec_page_array = calloc (cpu->exec_page_count,\n        sizeof (insn_exec_page_t));\n\n    if (!cpu->exec_page_array) {\n        fprintf (stderr,\n            \"mips_jit_init: unable to create exec page array\\n\");\n        return (-1);\n    }\n\n    for (i = 0, cp_addr = cpu->exec_page_area; i < cpu->exec_page_count; i++) {\n        cp = &cpu->exec_page_array[i];\n\n        cp->ptr = cp_addr;\n        cp_addr += MIPS_JIT_BUFSIZE;\n\n        cp->next = cpu->exec_page_free_list;\n        cpu->exec_page_free_list = cp;\n    }\n\n    printf\n        (\"CPU%u: carved JIT exec zone of %lu Mb into %lu pages of %u Kb.\\n\",\n        cpu->id, (u_long) (cpu->exec_page_area_size / 1048576),\n        (u_long) cpu->exec_page_count, MIPS_JIT_BUFSIZE / 1024);\n    return (0);\n}\n\n/* Flush the JIT */\nint mips_jit_flush (cpu_mips_t * cpu, m_uint32_t threshold)\n{\n    mips_jit_tcb_t *p, *next;\n    m_uint32_t pc_hash;\n    u_int count = 0;\n    m_uint32_t flush_threadhold = 0;\n\n    if (threshold == 0)\n        flush_threadhold = (m_uint32_t) (0xffffffff);\n    for (p = cpu->tcb_list; p; p = next) {\n        next = p->next;\n        if ((m_uint32_t) p->acc_count <= flush_threadhold) {\n            pc_hash = mips_jit_get_pc_hash (cpu, p->start_pc);\n            cpu->exec_blk_map[pc_hash] = NULL;\n            mips_jit_tcb_free (cpu, p, TRUE);\n            count++;\n        }\n    }\n\n    cpu->compiled_pages -= count;\n    return (count);\n}\n\n/* Shutdown the JIT */\nvoid mips_jit_shutdown (cpu_mips_t * cpu)\n{\n    mips_jit_tcb_t *p, *next;\n\n    /* Flush the JIT */\n    mips_jit_flush (cpu, 0);\n\n    /* Free the instruction blocks */\n    for (p = cpu->tcb_free_list; p; p = next) {\n        next = p->next;\n        free (p);\n    }\n\n    /* Unmap the executable page area */\n    if (cpu->exec_page_area)\n        munmap (cpu->exec_page_area, cpu->exec_page_area_size);\n\n    /* Free the exec page array */\n    free (cpu->exec_page_array);\n\n    /* Free physical mapping for executable pages */\n    free (cpu->exec_blk_map);\n}\n\n/* Allocate an exec page */\nstatic forced_inline insn_exec_page_t *exec_page_alloc (cpu_mips_t * cpu)\n{\n    insn_exec_page_t *p;\n    u_int count;\n\n    /* If the free list is empty, flush JIT */\n    if (unlikely (!cpu->exec_page_free_list)) {\n        if (cpu->jit_flush_method) {\n            mips_jit_flush (cpu, 0);\n        } else {\n            count = mips_jit_flush (cpu, 100);\n            if (!cpu->exec_page_free_list)\n                mips_jit_flush (cpu, 0);\n        }\n\n        /* Use both methods alternatively */\n        cpu->jit_flush_method = 1 - cpu->jit_flush_method;\n    }\n\n    if (unlikely (!(p = cpu->exec_page_free_list))) {\n        return NULL;\n    }\n\n    cpu->exec_page_free_list = p->next;\n    cpu->exec_page_alloc++;\n    return p;\n}\n\n/* Free an exec page and returns it to the pool */\nstatic forced_inline void exec_page_free (cpu_mips_t * cpu,\n    insn_exec_page_t * p)\n{\n    if (p) {\n        p->next = cpu->exec_page_free_list;\n        cpu->exec_page_free_list = p;\n        cpu->exec_page_alloc--;\n    }\n\n}\n\n/* Fetch a MIPS instruction */\nstatic forced_inline mips_insn_t insn_fetch (mips_jit_tcb_t * b)\n{\n    return (vmtoh32 (b->mips_code[b->mips_trans_pos]));\n}\n\n#ifdef DEBUG_JIT\nvoid fastcall jit_debug (cpu_mips_t * cpu, mips_jit_tcb_t * block)\n{\n    /*Put the debug code here. */\n}\n\n#endif\n\n/*What is the meaning of delay_slot?\nSearch the whole project and you will find delay_slot can be 0/1/2.\n\n0: we are translating the instruction not in delay slot.\n1: we are translating the instruction in delay and update mips_trans_pos.\n2: we are translating the instruction in delay and NOT update mips_trans_pos.\n\n*/\n\n/* Fetch a MIPS instruction and emit corresponding translated code */\nint mips_jit_fetch_and_emit (cpu_mips_t * cpu,\n    mips_jit_tcb_t * block, int delay_slot)\n{\n    mips_insn_t code;\n    register uint op;\n\n    code = insn_fetch (block);\n    op = MAJOR_OP (code);\n\n    /* Branch-delay slot is in another page: slow exec */\n    if ((block->mips_trans_pos == (MIPS_INSN_PER_PAGE - 1))\n        && (insn_is_jmp (code))) {\n        block->jit_insn_ptr[block->mips_trans_pos] = block->jit_ptr;\n        mips_set_pc (block, block->start_pc + (block->mips_trans_pos << 2));\n        mips_emit_single_step (block, code);\n        mips_jit_tcb_push_epilog (block);\n        block->mips_trans_pos++;\n        return (0);\n    }\n\n    if (!delay_slot)\n        block->jit_insn_ptr[block->mips_trans_pos] = block->jit_ptr;\n\n    if (delay_slot == 0)\n        block->mips_trans_pos++;\n\n#ifdef DEBUG_JIT\n    m_uint32_t jit_pc;\n    if (delay_slot == 0)\n        jit_pc = block->start_pc + ((block->mips_trans_pos - 1) << 2);\n    else\n        jit_pc = block->start_pc + ((block->mips_trans_pos) << 2);\n    x86_mov_membase_imm (block->jit_ptr, X86_EDI, OFFSET (cpu_mips_t, jit_pc),\n        jit_pc, 4);\n    x86_mov_reg_reg (block->jit_ptr, X86_EAX, X86_EDI, 4);\n    x86_mov_reg_imm (block->jit_ptr, X86_EDX, block);\n    mips_emit_basic_c_call (block, jit_debug);\n#endif\n\n    if (delay_slot && insn_is_jmp (code)) {\n        /*why a jump instruction in a delay slot???   yajin\n         *\n         * ---------\n         * |CODE    |\n         * |-------|\n         * | DATA   |\n         * ---------\n         *\n         * When data and code is in one page and we translate a page once.\n         * Emulator does not know where is data and where is code. So it just translate the whole\n         * page.\n         * data : 504f4e4d     (jmp)\n         * data : 54535251    (jmp TOO)\n         * So 54535251 is in delay slot of 504f4e4d.\n         * We just  add mips_trans_pos and return.\n         * TODO: a better method is to stop tranlating the page.\n         *\n         */\n        if (delay_slot == 1)\n            block->mips_trans_pos++;\n        return (0);\n    }\n\n    if (!delay_slot) {\n        /* Check for IRQs and cpu pausing before jumps */\n        if (insn_is_jmp (code)) {\n            mips_check_cpu_pausing (block);\n            mips_check_pending_irq (block);\n        }\n    }\n/*set is_in_bdslot*/\n    if ((delay_slot == 1) || (delay_slot == 2))\n        x86_mov_membase_imm (block->jit_ptr, X86_EDI, OFFSET (cpu_mips_t,\n                is_in_bdslot), 0x1, 4);\n\n    mips_jit[op].emit_func (cpu, block, code);\n/*clear is_in_bdslot*/\n    if ((delay_slot == 1) || (delay_slot == 2))\n        x86_mov_membase_imm (block->jit_ptr, X86_EDI, OFFSET (cpu_mips_t,\n                is_in_bdslot), 0x0, 4);\n    if (delay_slot == 1)\n        block->mips_trans_pos++;\n\n    return (0);\n}\n\n/* Add end of JIT block */\nstatic forced_inline void mips_jit_tcb_add_end (mips_jit_tcb_t * b)\n{\n    mips_set_pc (b, b->start_pc + (b->mips_trans_pos << 2));\n    mips_jit_tcb_push_epilog (b);\n}\n\n/* Record a patch to apply in a compiled block */\nint mips_jit_tcb_record_patch (mips_jit_tcb_t * block, u_char * jit_ptr,\n    m_va_t vaddr)\n{\n    struct mips_jit_patch_table *ipt = block->patch_table;\n    struct mips_insn_patch *patch;\n\n    /* pc must be 32-bit aligned */\n    if (vaddr & 0x03) {\n        fprintf (stderr,\n            \"Block 0x%8.8\" LL \"x: trying to record an invalid PC \" \"(0x%8.8\"\n            LL \"x) - mips_trans_pos=%d.\\n\", block->start_pc, vaddr,\n            block->mips_trans_pos);\n        return (-1);\n    }\n\n    if (!ipt || (ipt->cur_patch >= MIPS64_INSN_PATCH_TABLE_SIZE)) {\n        /* full table or no table, create a new one */\n        ipt = malloc (sizeof (*ipt));\n        if (!ipt) {\n            fprintf (stderr,\n                \"Block 0x%8.8\" LL \"x: unable to create patch table.\\n\",\n                block->start_pc);\n            return (-1);\n        }\n\n        memset (ipt, 0, sizeof (*ipt));\n        ipt->next = block->patch_table;\n        block->patch_table = ipt;\n    }\n#if DEBUG_BLOCK_PATCH\n    printf (\"Block 0x%8.8llx: recording patch [JIT:%p->mips:0x%8.8llx], \"\n        \"MTP=%d\\n\", block->start_pc, jit_ptr, vaddr, block->mips_trans_pos);\n#endif\n\n    patch = &ipt->patches[ipt->cur_patch];\n    patch->jit_insn = jit_ptr;\n    patch->mips_pc = vaddr;\n    ipt->cur_patch++;\n    return (0);\n}\n\n/* Apply all patches */\nstatic int mips_jit_tcb_apply_patches (cpu_mips_t * cpu,\n    mips_jit_tcb_t * block)\n{\n    struct mips_jit_patch_table *ipt;\n    struct mips_insn_patch *patch;\n    u_char *jit_dst;\n    int i;\n\n    for (ipt = block->patch_table; ipt; ipt = ipt->next)\n        for (i = 0; i < ipt->cur_patch; i++) {\n            patch = &ipt->patches[i];\n            jit_dst = mips_jit_tcb_get_host_ptr (block, patch->mips_pc);\n\n            if (jit_dst) {\n#if DEBUG_BLOCK_PATCH\n                printf (\"Block 0x%8.8llx: applying patch \"\n                    \"[JIT:%p->mips:0x%8.8llx=JIT:%p]\\n\",\n                    block->start_pc, patch->jit_insn, patch->mips_pc,\n                    jit_dst);\n#endif\n                mips_jit_tcb_set_patch (patch->jit_insn, jit_dst);\n            }\n        }\n\n    return (0);\n}\n\n/* Free the patch table */\nstatic void mips_jit_tcb_free_patches (mips_jit_tcb_t * block)\n{\n    struct mips_jit_patch_table *p, *next;\n\n    for (p = block->patch_table; p; p = next) {\n        next = p->next;\n        free (p);\n    }\n\n    block->patch_table = NULL;\n}\n\n/* Adjust the JIT buffer if its size is not sufficient */\nstatic int mips_jit_tcb_adjust_buffer (cpu_mips_t * cpu,\n    mips_jit_tcb_t * block)\n{\n    insn_exec_page_t *new_buffer;\n\n    if ((block->jit_ptr - block->jit_buffer->ptr) <= (MIPS_JIT_BUFSIZE - 512))\n        return (0);\n\n#if DEBUG_BLOCK_CHUNK\n    printf (\"Block 0x%\" LL \"x: adjusting JIT buffer...\\n\", block->start_pc);\n#endif\n\n    if (block->jit_chunk_pos >= MIPS_JIT_MAX_CHUNKS) {\n        fprintf (stderr, \"Block 0x%\" LL \"x: too many JIT chunks.\\n\",\n            block->start_pc);\n        return (-1);\n    }\n\n    if (!(new_buffer = exec_page_alloc (cpu)))\n        return (-1);\n\n    /* record the new exec page */\n    block->jit_chunks[block->jit_chunk_pos++] = block->jit_buffer;\n    block->jit_buffer = new_buffer;\n\n    /* jump to the new exec page (link) */\n    mips_jit_tcb_set_jump (block->jit_ptr, new_buffer->ptr);\n    block->jit_ptr = new_buffer->ptr;\n\n    return (0);\n}\n\n/* Allocate an instruction block */\nstatic inline mips_jit_tcb_t *mips_jit_tcb_alloc (cpu_mips_t * cpu)\n{\n    mips_jit_tcb_t *p;\n\n    if (cpu->tcb_free_list) {\n        p = cpu->tcb_free_list;\n        cpu->tcb_free_list = p->next;\n    } else {\n        if (!(p = malloc (sizeof (*p)))) {\n            return NULL;\n        }\n\n    }\n\n    memset (p, 0, sizeof (*p));\n    return p;\n}\n\n/* Free an instruction block */\nvoid mips_jit_tcb_free (cpu_mips_t * cpu, mips_jit_tcb_t * block,\n    int list_removal)\n{\n    int i;\n\n    if (block) {\n        if (list_removal) {\n            /* Remove the block from the linked list */\n            if (block->next)\n                block->next->prev = block->prev;\n            else\n                cpu->tcb_last = block->prev;\n\n            if (block->prev)\n                block->prev->next = block->next;\n            else\n                cpu->tcb_list = block->next;\n        }\n\n        /* Free the patch tables */\n        mips_jit_tcb_free_patches (block);\n\n        /* Free code pages */\n        for (i = 0; i < MIPS_JIT_MAX_CHUNKS; i++)\n            exec_page_free (cpu, block->jit_chunks[i]);\n\n        /* Free the current JIT buffer */\n        exec_page_free (cpu, block->jit_buffer);\n\n        /* Free the MIPS-to-native code mapping */\n        free (block->jit_insn_ptr);\n\n        /* Make the block return to the free list */\n        block->next = cpu->tcb_free_list;\n        cpu->tcb_free_list = block;\n    }\n}\n\n#ifdef DEBUG_JIT\n/*get the tcb count*/\nstatic void mips_jit_count_tcb (cpu_mips_t * cpu)\n{\n\n    unsigned int i = 0;\n    insn_exec_page_t *p1;\n    p1 = cpu->exec_page_free_list;\n    while (p1 != NULL) {\n        p1 = p1->next;\n        i++;\n    }\n    printf (\"FREE PAGES %x  \\n\", i);\n\n    i = 0;\n    mips_jit_tcb_t *tcb1;\n    tcb1 = cpu->tcb_list;\n    while (tcb1 != NULL) {\n        tcb1 = tcb1->next;\n        i++;\n    }\n    printf (\"tcb list  %x  \\n\", i);\n\n    i = 0;\n    tcb1 = cpu->tcb_free_list;\n    while (tcb1 != NULL) {\n        tcb1 = tcb1->next;\n        i++;\n    }\n    printf (\"tcb free list  %x  \\n\", i);\n\n}\n#endif\n/* Create an instruction block */\nstatic mips_jit_tcb_t *mips_jit_tcb_create (cpu_mips_t * cpu,\n    m_va_t vaddr)\n{\n    mips_jit_tcb_t *block = NULL;\n    m_uint32_t asid;\n\n    if (!(block = mips_jit_tcb_alloc (cpu)))\n        goto err_block_alloc;\n\n    block->start_pc = vaddr;\n\n    int zone = (vaddr >> 29) & 0x7;\n    if ((zone == 0x4) || (zone == 0x5)) {\n\n    } else {\n        mips_cp0_t *cp0 = &cpu->cp0;\n        asid = cp0->reg[MIPS_CP0_TLB_HI] & MIPS_TLB_ASID_MASK;\n        block->asid = asid;\n    }\n\n    /* Allocate the first JIT buffer */\n    if (!(block->jit_buffer = exec_page_alloc (cpu)))\n        goto err_jit_alloc;\n\n    block->jit_ptr = block->jit_buffer->ptr;\n    block->mips_code = cpu->mem_op_lookup (cpu, block->start_pc);\n\n    if (!block->mips_code) {\n        /*TLB Exception */\n        int zone = (block->start_pc >> 29) & 0x7;\n        switch (zone) {\n        case 0x0:\n        case 0x1:\n        case 0x2:\n        case 0x3:\n        case 0x6:\n        case 0x7:\n            /*Return the tcb to tcb free list */\n            cpu->exec_blk_map[mips_jit_get_pc_hash (cpu, block->start_pc)] =\n                NULL;\n            mips_jit_tcb_free (cpu, block, FALSE);\n            longjmp (run_jmp, 1);\n            break;\n        default:\n            fprintf (stderr,\n                \"No memory map for code execution at 0x%\" LL \"x\\n\",\n                block->start_pc);\n            goto err_lookup;\n        }\n\n    }\n\n    return block;\n\n  err_lookup:\n  err_jit_alloc:\n    mips_jit_tcb_free (cpu, block, FALSE);\n  err_block_alloc:\n    fprintf (stderr,\n        \"%% Unable to create instruction block for vaddr=0x%\" LL \"x\\n\",\n        vaddr);\n    return NULL;\n}\n\n/* Compile a MIPS instruction page */\nstatic inline\n    mips_jit_tcb_t * mips_jit_tcb_compile (cpu_mips_t * cpu, m_va_t vaddr)\n{\n    mips_jit_tcb_t *block;\n    m_uint64_t page_addr;\n    size_t len;\n\n    page_addr = vaddr & ~(m_uint64_t) MIPS_MIN_PAGE_IMASK;\n\n    if (unlikely (!(block = mips_jit_tcb_create (cpu, page_addr)))) {\n        fprintf (stderr, \"insn_page_compile: unable to create JIT block.\\n\");\n        return NULL;\n    }\n\n    /* Allocate the array used to convert MIPS code ptr to native code ptr */\n    len = MIPS_MIN_PAGE_SIZE / sizeof (mips_insn_t);\n\n    if (!(block->jit_insn_ptr = calloc (len, sizeof (u_char *)))) {\n        fprintf (stderr,\n            \"insn_page_compile: unable to create JIT mappings.\\n\");\n        goto error;\n    }\n\n    /* Emit native code for each instruction */\n    block->mips_trans_pos = 0;\n\n    while (block->mips_trans_pos < MIPS_INSN_PER_PAGE) {\n        if (unlikely ((mips_jit_fetch_and_emit (cpu, block, 0) == -1))) {\n            fprintf (stderr,\n                \"insn_page_compile: unable to fetch instruction.\\n\");\n            goto error;\n        }\n#if DEBUG_BLOCK_COMPILE\n        printf (\"Page 0x%8.8\" LL \"x: emitted tag 0x%8.8x/0x%8.8x\\n\",\n            block->start_pc, tag->mask, tag->value);\n#endif\n\n        mips_jit_tcb_adjust_buffer (cpu, block);\n    }\n\n    mips_jit_tcb_add_end (block);\n    mips_jit_tcb_apply_patches (cpu, block);\n    mips_jit_tcb_free_patches (block);\n\n    /* Add the block to the linked list */\n    block->next = cpu->tcb_list;\n    block->prev = NULL;\n\n    if (cpu->tcb_list)\n        cpu->tcb_list->prev = block;\n    else\n        cpu->tcb_last = block;\n\n    cpu->tcb_list = block;\n\n    cpu->compiled_pages++;\n    return block;\n\n  error:\n    mips_jit_tcb_free (cpu, block, FALSE);\n    return NULL;\n}\n\n/* Run a compiled MIPS instruction block */\nstatic forced_inline\n    void mips_jit_tcb_run (cpu_mips_t * cpu, mips_jit_tcb_t * block)\n{\n\n    if (unlikely (cpu->pc & 0x03)) {\n        fprintf (stderr, \"mips_jit_tcb_run: Invalid PC 0x%\" LL \"x.\\n\",\n            cpu->pc);\n        cpu_stop (cpu);\n        return;\n    }\n    /* Execute JIT compiled code */\n    mips_jit_tcb_exec (cpu, block);\n}\n\nvoid *mips_jit_run_cpu (cpu_mips_t * cpu)\n{\n\n    m_uint32_t pc_hash;\n    mips_jit_tcb_t *block;\n\n    cpu->cpu_thread_running = TRUE;\n    current_cpu = cpu;\n\n    mips_init_host_alarm ();\n\n    setjmp (run_jmp);\n\n  start_cpu:\n    for (;;) {\n        if (unlikely (cpu->state != CPU_STATE_RUNNING))\n            break;\n\n        if (unlikely ((cpu->pause_request) & CPU_INTERRUPT_EXIT)) {\n            cpu->state = CPU_STATE_PAUSING;\n            break;\n        }\n\n        /* Reset \"zero register\" (for safety) */\n        cpu->gpr[0] = 0;\n\n        /* Check IRQ */\n        if (unlikely (cpu->irq_pending)) {\n            mips_trigger_irq (cpu);\n            //continue;\n        }\n\n        pc_hash = mips_jit_get_pc_hash (cpu, cpu->pc);\n        block = cpu->exec_blk_map[pc_hash];\n\n        /* No block found, compile the page */\n        if (unlikely (!block)\n            || unlikely (!mips_jit_tcb_match (cpu, block, cpu->pc))) {\n\n            if (block != NULL) {\n                mips_jit_tcb_free (cpu, block, TRUE);\n                cpu->exec_blk_map[pc_hash] = NULL;\n            }\n\n            block = mips_jit_tcb_compile (cpu, cpu->pc);\n            if (unlikely (!block)) {\n                fprintf (stderr,\n                    \"VM '%s': unable to compile block for CPU%u PC=0x%\" LL\n                    \"x\\n\", cpu->vm->name, cpu->id, cpu->pc);\n                cpu_stop (cpu);\n                break;\n            }\n            block->acc_count++;\n            cpu->exec_blk_map[pc_hash] = block;\n        }\n        mips_jit_tcb_run (cpu, block);\n\n    }\n\n    while (cpu->cpu_thread_running) {\n        switch (cpu->state) {\n        case CPU_STATE_RUNNING:\n            cpu->state = CPU_STATE_RUNNING;\n            goto start_cpu;\n\n        case CPU_STATE_HALTED:\n            cpu->cpu_thread_running = FALSE;\n            break;\n        case CPU_STATE_RESTARTING:\n            cpu->state = CPU_STATE_RESTARTING;\n            /*Just waiting for cpu restart. */\n            break;\n        case CPU_STATE_PAUSING:\n            /*main loop must wait for me. heihei :) */\n            mips_main_loop_wait (cpu, 0);\n            cpu->state = CPU_STATE_RUNNING;\n            cpu->pause_request &= ~CPU_INTERRUPT_EXIT;\n            /*start cpu again */\n            goto start_cpu;\n\n        }\n    }\n    return NULL;\n}\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/mips_jit.h",
    "content": "/*\n * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n *\n */\n\n/*\nJIT Support.\nIn order to improve the simulation speed, JIT is always used in simulators.\nUnlike the JIT of high language, virtualmips does not have basic block.\nIt translates one page(4K) code one time and then run it.\n\nProblems:\n\n1. code fetch exception\n2. delay slot\n3. interrupt emulation\n4. Self-modify code\n5. debug JIT\n\nHow to debug JIT is the most tricky problem.\nI do not have better method, but just logging and comparing with\ninterpreter. Thanks to the file diff tools.\n\nIf you know how to debug JIT, please tell me.\n\nMost of the code is stripped from Dynamips.  Thanks Christophe Fillot.\n\nMany optimation chances exist.\n1. add asid as a hash key of translated block so that translated block is not fushed too often.\n2. A better way to find translated block. red-block tree??\n3. peephole optimation???\n4. Use profile tools such as vtune to find the hot path and then optimize it.\n\n\n*/\n\n#ifndef __MIPS64_JIT_H__\n#define __MIPS64_JIT_H__\n\n#include \"system.h\"\n#include \"utils.h\"\n#include \"sbox.h\"\n#include \"mips.h\"\n#include \"mips_memory.h\"\n\n#ifndef _USE_JIT_\n#define JIT_SUPPORT 0\n#endif\n\n#ifdef _USE_JIT_\n\n#define JIT_SUPPORT 1\n\n/* Size of executable page area (in Mb) */\n#ifndef __CYGWIN__\n#define MIPS_EXEC_AREA_SIZE  64\n#else\n#define MIPS_EXEC_AREA_SIZE  16\n#endif\n\n/* Buffer size for JIT code generation */\n#define MIPS_JIT_BUFSIZE     32768\n\n/* Maximum number of X86 chunks */\n#define MIPS_JIT_MAX_CHUNKS  32\n\n/* Size of hash for PC lookup */\n#define MIPS_JIT_PC_HASH_BITS   16\n#define MIPS_JIT_PC_HASH_MASK   ((1 << MIPS_JIT_PC_HASH_BITS) - 1)\n#define MIPS_JIT_PC_HASH_SIZE   (1 << MIPS_JIT_PC_HASH_BITS)\n\n/* Instruction jump patch */\nstruct mips_insn_patch {\n    u_char *jit_insn;\n    m_uint64_t mips_pc;\n};\n\n/* Instruction patch table */\n#define MIPS64_INSN_PATCH_TABLE_SIZE  32\n\nstruct mips_jit_patch_table {\n    struct mips_insn_patch patches[MIPS64_INSN_PATCH_TABLE_SIZE];\n    u_int cur_patch;\n    struct mips_jit_patch_table *next;\n};\n\n/* Host executable page */\nstruct insn_exec_page {\n    u_char *ptr;\n    insn_exec_page_t *next;\n};\n\n/* MIPS64 translated code block */\nstruct mips_jit_tcb {\n    /*start pc in tcb */\n    m_va_t start_pc;\n    m_uint32_t asid;\n    m_uint32_t acc_count;\n    /*guest pc to host pc mapping table */\n    u_char **jit_insn_ptr;\n    /*guest code of this tcb */\n    mips_insn_t *mips_code;\n    u_int mips_trans_pos;\n    u_int jit_chunk_pos;\n    /*used in translating */\n    u_char *jit_ptr;\n    insn_exec_page_t *jit_buffer;\n    insn_exec_page_t *jit_chunks[MIPS_JIT_MAX_CHUNKS];\n    struct mips_jit_patch_table *patch_table;\n    mips_jit_tcb_t *prev, *next;\n};\n\nint mips_jit_init (cpu_mips_t * cpu);\nint mips_jit_flush (cpu_mips_t * cpu, m_uint32_t threshold);\nvoid mips_jit_shutdown (cpu_mips_t * cpu);\nint mips_jit_fetch_and_emit (cpu_mips_t * cpu,\n    mips_jit_tcb_t * block, int delay_slot);\n\nint mips_jit_tcb_record_patch (mips_jit_tcb_t * block, u_char * jit_ptr,\n    m_va_t vaddr);\nvoid mips_jit_tcb_free (cpu_mips_t * cpu, mips_jit_tcb_t * block,\n    int list_removal);\n\nvoid *mips_jit_run_cpu (cpu_mips_t * cpu);\n\n/*-----------inline functions-----------------------------*/\n/* Get the JIT instruction pointer in a translated block */\nstatic forced_inline\n    u_char * mips_jit_tcb_get_host_ptr (mips_jit_tcb_t * b, m_va_t vaddr)\n{\n    m_uint32_t offset;\n\n    offset = ((m_uint32_t) vaddr & MIPS_MIN_PAGE_IMASK) >> 2;\n    return (b->jit_insn_ptr[offset]);\n}\n\n/* Check if the specified address belongs to the specified block */\nstatic forced_inline\n    int mips_jit_tcb_local_addr (mips_jit_tcb_t * block, m_va_t vaddr,\n    u_char ** jit_addr)\n{\n    if ((vaddr & MIPS_MIN_PAGE_MASK) == block->start_pc) {\n        *jit_addr = mips_jit_tcb_get_host_ptr (block, vaddr);\n        return (1);\n    }\n\n    return (0);\n}\n\nextern int test33;\n\n/* Check if PC register matches the compiled block virtual address */\nstatic forced_inline\n    int mips_jit_tcb_match (cpu_mips_t * cpu, mips_jit_tcb_t * block,\n    m_va_t vaddr)\n{\n    m_va_t vpage;\n\n    // vpage = cpu->pc & ~(m_va_t)MIPS_MIN_PAGE_IMASK;\n    vpage = vaddr & ~(m_va_t) MIPS_MIN_PAGE_IMASK;\n    if (block->start_pc != vpage)\n        return 0;\n    /*block->start_pc == vpage */\n    if (!vaddr_mapped (vaddr))\n        return 1;\n    /*block->start_pc == vpage and mapped.check asid */\n    int asid = cpu->cp0.reg[MIPS_CP0_TLB_HI] & MIPS_TLB_ASID_MASK;\n\n    return (block->asid == asid);\n}\n\n/* Compute the hash index for the specified PC value */\n/*TODO: Add asid as a hash key.\nCurrently same pc of different asid will get the same hash value.\n*/\nstatic forced_inline m_uint32_t mips_jit_get_pc_hash (cpu_mips_t * cpu,\n    m_va_t pc)\n{\n    m_uint32_t page_hash;\n\n    page_hash = sbox_u32 (pc >> MIPS_MIN_PAGE_SHIFT);\n    return ((page_hash ^ (page_hash >> 12)) & MIPS_JIT_PC_HASH_MASK);\n\n}\n\n/*if the code write to code region, flush the translated page*/\nstatic forced_inline void jit_handle_self_write (cpu_mips_t * cpu,\n    m_va_t vaddr)\n{\n    m_uint32_t pc_hash;\n    mips_jit_tcb_t *block;\n\n    pc_hash = mips_jit_get_pc_hash (cpu, vaddr);\n    block = cpu->exec_blk_map[pc_hash];\n    if (block != NULL) {\n        if (unlikely (mips_jit_tcb_match (cpu, block, vaddr))) {\n            mips_jit_tcb_free (cpu, block, TRUE);\n            cpu->exec_blk_map[pc_hash] = NULL;\n        }\n    }\n}\n\n/*whether instruction is a jump instruction*/\nstatic forced_inline int insn_is_jmp (unsigned int insn)\n{\n    /*can insn be in delay slot */\n    int op = MAJOR_OP (insn);\n    uint16_t special_func;\n    switch (op) {\n    case 0x0:\n        {\n            special_func = bits (insn, 0, 5);\n            switch (special_func) {\n            case 0x8:\n            case 0x9:\n                return 1;\n            default:\n                return 0;\n            }\n\n        }\n    case 0x1:\n        {\n            special_func = bits (insn, 16, 20);\n            switch (special_func) {\n            case 0x0:\n            case 0x1:\n            case 0x2:\n            case 0x3:\n            case 0x4:\n            case 0x10:\n            case 0x11:\n            case 0x12:\n            case 0x13:\n                return 1;\n            default:\n                return 0;\n            }\n\n        }\n    case 0x2:\n    case 0x3:\n    case 0x4:\n    case 0x5:\n    case 0x6:\n    case 0x7:\n    case 0x14:\n    case 0x15:\n    case 0x16:\n    case 0x17:\n        return 1;\n    default:\n        return 0;\n\n    }\n\n}\n\n/* Check if an instruction is in a delay slot or not */\nstatic forced_inline int mips_jit_is_delay_slot (mips_jit_tcb_t * b,\n    m_va_t pc)\n{\n    m_uint32_t offset, insn;\n\n    offset = (pc - b->start_pc) >> 2;\n\n    if (!offset)\n        return (FALSE);\n    ASSERT (b->mips_code != NULL, \"b->mips_code can not be NULL\\n\");\n    /* Fetch the previous instruction to determine if it is a jump */\n    insn = vmtoh32 (b->mips_code[offset - 1]);\n    return insn_is_jmp (insn);\n}\n#endif\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/mips_memory.c",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)\n * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <string.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <sys/mman.h>\n#include <fcntl.h>\n#include <assert.h>\n\n#include \"cpu.h\"\n#include \"vm.h\"\n#include \"mips_memory.h\"\n#include \"device.h\"\n#include \"utils.h\"\n#include \"mips_cp0.h\"\n#include \"gdb_interface.h\"\n#include \"mips_jit.h\"\n\nvoid bad_memory_access (cpu_mips_t * cpu, m_va_t vaddr)\n{\n    mips_insn_t insn;\n\n    printf (\"*** %08x: bad memory reference\\n\", vaddr);\n    if (mips_fetch_instruction (cpu, cpu->pc, &insn) == 0) {\n        printf (\"*** %08x: %08x \", cpu->pc, insn);\n        print_mips (cpu->pc, insn, cpu->insn_len, cpu->is_mips16e, stdout);\n        printf (\"\\n\");\n    }\n    if (mips_fetch_instruction (cpu, cpu->pc + 4, &insn) == 0) {\n        printf (\"*** %08x: %08x \", cpu->pc + 4, insn);\n        print_mips (cpu->pc, insn, cpu->insn_len, cpu->is_mips16e, stdout);\n        printf (\"\\n\");\n    }\n    dumpregs (cpu);\n    if (cpu->vm->mipsy_debug_mode)\n        bad_memory_access_gdb (cpu->vm);\n    else\n        assert (0);\n}\n\n/*\n * MTS access with special access mask\n */\nvoid mips_access_special (cpu_mips_t * cpu, m_va_t vaddr, m_uint32_t mask,\n    u_int op_code, u_int op_type, u_int op_size, m_reg_t * data, u_int * exc)\n{\n    m_reg_t vpn;\n    m_uint8_t exc_code;\n\n    switch (mask) {\n    case MTS_ACC_U:\n        if (op_type == MTS_READ)\n            *data = 0;\n        break;\n\n    case MTS_ACC_T:\n    case MTS_ACC_M:\n    case MTS_ACC_AE:\n        //if (op_code != MIPS_MEMOP_LOOKUP)\n        //lookup also raise exception\n        {\n            cpu->cp0.reg[MIPS_CP0_BADVADDR] = vaddr;\n            //clear vpn of entry hi\n            cpu->cp0.reg[MIPS_CP0_TLB_HI] &=\n                ~(mips_cp0_get_vpn2_mask (cpu));\n            //set VPN of entryhi\n            vpn = vaddr & mips_cp0_get_vpn2_mask (cpu);\n            cpu->cp0.reg[MIPS_CP0_TLB_HI] |= vpn;\n\n            //set context register\n            cpu->cp0.reg[MIPS_CP0_CONTEXT] &= ~MIPS_CP0_CONTEXT_BADVPN2_MASK;\n            vaddr = (vaddr >> 13) << 4;\n            vaddr = vaddr & MIPS_CP0_CONTEXT_BADVPN2_MASK;\n            cpu->cp0.reg[MIPS_CP0_CONTEXT] |= vaddr;\n#ifdef SIM_PIC32\n            if (op_type == MTS_READ)\n                exc_code = MIPS_CP0_CAUSE_ADDR_LOAD;\n            else\n                exc_code = MIPS_CP0_CAUSE_ADDR_SAVE;\n#else\n            if (mask == MTS_ACC_M)\n                exc_code = MIPS_CP0_CAUSE_TLB_MOD;\n            else if (mask == MTS_ACC_T) {\n                if (op_type == MTS_READ)\n                    exc_code = MIPS_CP0_CAUSE_TLB_LOAD;\n                else\n                    exc_code = MIPS_CP0_CAUSE_TLB_SAVE;\n            } else if (mask == MTS_ACC_AE) {\n                if (op_type == MTS_READ)\n                    exc_code = MIPS_CP0_CAUSE_ADDR_LOAD;\n                else\n                    exc_code = MIPS_CP0_CAUSE_ADDR_SAVE;\n            } else\n                assert (0);\n#endif\n            mips_trigger_exception (cpu, exc_code, cpu->is_in_bdslot);\n        }\n        *exc = 1;\n        break;\n    }\n}\n\n/* === MTS for 32-bit address space ======================================= */\n#ifdef MTS_ADDR_SIZE\n#undef MTS_ADDR_SIZE\n#endif\n\n#define MTS_ADDR_SIZE      32\n\nstatic int mips_mts32_translate (cpu_mips_t * cpu, m_va_t vaddr,\n    m_uint32_t * phys_page);\n\n/*\n *  Initialize the MTS subsystem for the specified CPU\n */\nint mips_mts32_init (cpu_mips_t * cpu)\n{\n    size_t len;\n\n    /* Initialize the cache entries to 0 (empty) */\n    len = MTS32_HASH_SIZE * sizeof (mts32_entry_t);\n    cpu->mts_u.mts32_cache = malloc (len);\n    if (! cpu->mts_u.mts32_cache)\n        return (-1);\n\n    memset (cpu->mts_u.mts32_cache, 0xFF, len);\n    cpu->mts_lookups = 0;\n    cpu->mts_misses = 0;\n    return (0);\n}\n\n/* Free memory used by MTS */\nvoid mips_mts32_shutdown (cpu_mips_t * cpu)\n{\n    /* Free the cache itself */\n    free (cpu->mts_u.mts32_cache);\n    cpu->mts_u.mts32_cache = NULL;\n}\n\n/* Show MTS detailed information (debugging only!) */\nvoid mips_mts32_show_stats (cpu_mips_t * cpu)\n{\n#if DEBUG_MTS_MAP_VIRT\n    mts32_entry_t *entry;\n    u_int i, count;\n#endif\n\n    printf (\"\\nCPU%u: MTS%d statistics:\\n\", cpu->id, MTS_ADDR_SIZE);\n\n#if DEBUG_MTS_MAP_VIRT\n    /* Valid hash entries */\n    for (count = 0, i = 0; i < MTS32_HASH_SIZE; i++) {\n        entry = &(cpu->mts_u.mts32_cache[i]);\n\n        if (!(entry->gvpa & MTS_INV_ENTRY_MASK)) {\n            printf (\"    %4u: vaddr=0x%8.8llx, paddr=0x%8.8llx, hpa=%p\\n\",\n                i, (m_uint64_t) entry->gvpa, (m_uint64_t) entry->gppa,\n                (void *) entry->hpa);\n            count++;\n        }\n    }\n\n    printf (\"   %u/%u valid hash entries.\\n\", count, MTS32_HASH_SIZE);\n#endif\n\n    printf (\"   Total lookups: %llu, misses: %llu, efficiency: %g%%\\n\",\n        (unsigned long long)cpu->mts_lookups, (unsigned long long)cpu->mts_misses,\n        100 - ((double) (cpu->mts_misses * 100) / (double) cpu->mts_lookups));\n}\n\n/* Invalidate the complete MTS cache */\nvoid mips_mts32_invalidate_cache (cpu_mips_t * cpu)\n{\n    size_t len;\n\n    len = MTS32_HASH_SIZE * sizeof (mts32_entry_t);\n    memset (cpu->mts_u.mts32_cache, 0xFF, len);\n}\n\n/* Invalidate partially the MTS cache, given a TLB entry index */\nvoid mips_mts32_invalidate_tlb_entry (cpu_mips_t * cpu, m_va_t vaddr)\n{\n    mts32_entry_t *entry;\n    m_uint32_t hash_bucket;\n\n    hash_bucket = MTS32_HASH (vaddr);\n    entry = &cpu->mts_u.mts32_cache[hash_bucket];\n    memset (entry, 0xFF, sizeof (mts32_entry_t));\n}\n\n/*\n * MTS mapping.\n *\n * It is NOT inlined since it triggers a GCC bug on my config (x86, GCC 3.3.5)\n */\nstatic no_inline mts32_entry_t *mips_mts32_map (cpu_mips_t * cpu,\n    u_int op_type, mts_map_t * map, mts32_entry_t * entry,\n    mts32_entry_t * alt_entry, u_int is_fromgdb)\n{\n    struct vdevice *dev;\n    m_uint32_t offset;\n\n    dev = dev_lookup (cpu->vm, map->paddr);\n    if (! dev) {\n        if (! is_fromgdb) {\n            printf (\"no device!\\n\");\n            printf (\"cpu->pc %x vaddr %x paddr %x \\n\", cpu->pc, map->vaddr,\n                map->paddr);\n            exit (-1);\n        }\n        return NULL;\n    }\n\n    if (! dev->host_addr || (dev->flags & VDEVICE_FLAG_NO_MTS_MMAP)) {\n        offset = map->paddr - dev->phys_addr;\n\n        alt_entry->gvpa = map->vaddr;\n        alt_entry->gppa = map->paddr;\n        alt_entry->hpa = (dev->id << MTS_DEVID_SHIFT) + offset;\n        alt_entry->flags = MTS_FLAG_DEV;\n        alt_entry->mapped = map->mapped;\n        return alt_entry;\n    }\n    ASSERT (dev->host_addr != 0, \"dev->host_addr can not be null\\n\");\n    entry->gvpa = map->vaddr;\n    entry->gppa = map->paddr;\n    entry->hpa = dev->host_addr + (map->paddr - dev->phys_addr);\n    entry->flags = 0;\n    entry->asid = map->asid;\n    entry->g_bit = map->g_bit;\n    entry->dirty_bit = map->dirty;\n    entry->mapped = map->mapped;\n    return entry;\n}\n\n/* MTS lookup */\nstatic fastcall void *mips_mts32_lookup (cpu_mips_t * cpu, m_va_t vaddr)\n{\n    m_reg_t data;\n    u_int exc;\n    m_uint8_t has_set_value = FALSE;\n    return (mips_mts32_access (cpu, vaddr, MIPS_MEMOP_LOOKUP, 4, MTS_READ,\n            &data, &exc, &has_set_value, 0));\n}\n\n/* === MIPS Memory Operations ============================================= */\n\nu_int mips_mts32_gdb_lb (cpu_mips_t * cpu, m_va_t vaddr, void *cur)\n{\n    // m_reg_t data;\n    void *haddr;\n    u_int exc;\n    m_uint8_t has_set_value = FALSE;\n\n    haddr = mips_mts32_access (cpu, vaddr, MIPS_MEMOP_LB, 1, MTS_READ,\n        (m_reg_t *) cur, &exc, &has_set_value, 1);\n\n    if ((exc) || (haddr == NULL))\n        *(m_uint8_t *) cur = 0x0;\n    else\n        *(m_uint8_t *) cur = (*(m_uint8_t *) haddr);\n\n    return (0);\n}\n\n/* LB: Load Byte */\nu_int fastcall mips_mts32_lb (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    m_reg_t data;\n    void *haddr;\n    u_int exc;\n    m_uint8_t has_set_value = FALSE;\n\n    haddr =\n        mips_mts32_access (cpu, vaddr, MIPS_MEMOP_LB, 1, MTS_READ, &data,\n        &exc, &has_set_value, 0);\n    if (exc)\n        return exc;\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n\n    if (likely (has_set_value == FALSE))\n        data = *(m_uint8_t *) haddr;\n    if (likely (!exc))\n        cpu->reg_set (cpu, reg, sign_extend (data, 8));\n    return (exc);\n}\n\n/* LBU: Load Byte Unsigned */\nu_int fastcall mips_mts32_lbu (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    m_reg_t data;\n    void *haddr;\n    u_int exc;\n    m_uint8_t has_set_value = FALSE;\n\n    haddr =\n        mips_mts32_access (cpu, vaddr, MIPS_MEMOP_LBU, 1, MTS_READ, &data,\n        &exc, &has_set_value, 0);\n    if (exc)\n        return exc;\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n    if (likely (has_set_value == FALSE))\n        data = *(m_uint8_t *) haddr;\n    if (likely (!exc))\n        cpu->reg_set (cpu, reg, data & 0xff);\n    return (exc);\n}\n\n/* LH: Load Half-Word */\nu_int fastcall mips_mts32_lh (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    m_reg_t data;\n    void *haddr;\n    u_int exc;\n    m_uint8_t has_set_value = FALSE;\n\n    haddr =\n        mips_mts32_access (cpu, vaddr, MIPS_MEMOP_LH, 2, MTS_READ, &data,\n        &exc, &has_set_value, 0);\n    if (exc)\n        return exc;\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n    if (likely (has_set_value == FALSE))\n        data = vmtoh16 (*(m_uint16_t *) haddr);\n    if (likely (!exc))\n        cpu->reg_set (cpu, reg, sign_extend (data, 16));\n    return (exc);\n}\n\n/* LHU: Load Half-Word Unsigned */\nu_int fastcall mips_mts32_lhu (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    m_reg_t data;\n    void *haddr;\n    u_int exc;\n    m_uint8_t has_set_value = FALSE;\n\n    haddr =\n        mips_mts32_access (cpu, vaddr, MIPS_MEMOP_LHU, 2, MTS_READ, &data,\n        &exc, &has_set_value, 0);\n    if (exc)\n        return exc;\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n    if (likely (has_set_value == FALSE))\n        data = vmtoh16 (*(m_uint16_t *) haddr);\n    if (likely (!exc))\n        cpu->reg_set (cpu, reg, data & 0xffff);\n    return (exc);\n}\n\n/* LW: Load Word */\nu_int fastcall mips_mts32_lw (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    m_reg_t data;\n    void *haddr;\n    u_int exc;\n    m_uint8_t has_set_value = FALSE;\n    haddr =\n        mips_mts32_access (cpu, vaddr, MIPS_MEMOP_LW, 4, MTS_READ, &data,\n        &exc, &has_set_value, 0);\n    if (exc)\n        return exc;\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n\n    if (likely (has_set_value == FALSE)) {\n        data = vmtoh32 (*(m_uint32_t *) haddr);\n    }\n    if (likely (!exc)) {\n        if (cpu->vm->debug_level > 2 || (cpu->vm->debug_level > 1 &&\n            (cpu->cp0.reg[MIPS_CP0_STATUS] & MIPS_CP0_STATUS_UM) &&\n            ! (cpu->cp0.reg[MIPS_CP0_STATUS] & MIPS_CP0_STATUS_EXL) &&\n            vaddr >= 0x7f008000 && vaddr < 0x7f020000))\n        {\n            /* Print memory accesses in user mode. */\n            printf (\"        read %08x -> %08x \\n\", vaddr, data);\n        }\n        cpu->reg_set (cpu, reg, sign_extend (data, 32));\n    }\n    return (exc);\n}\n\n/* LWU: Load Word Unsigned */\nu_int fastcall mips_mts32_lwu (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    m_reg_t data;\n    void *haddr;\n    u_int exc;\n    m_uint8_t has_set_value = FALSE;\n\n    haddr =\n        mips_mts32_access (cpu, vaddr, MIPS_MEMOP_LWU, 4, MTS_READ, &data,\n        &exc, &has_set_value, 0);\n    if (exc)\n        return exc;\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n    if (likely (has_set_value == FALSE))\n        data = vmtoh32 (*(m_uint32_t *) haddr);\n    if (likely (!exc))\n        cpu->reg_set (cpu, reg, data & 0xffffffff);\n    return (exc);\n}\n\n/* LD: Load Double-Word */\nu_int fastcall mips_mts32_ld (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    m_reg_t data;\n    void *haddr;\n    u_int exc;\n    m_uint8_t has_set_value = FALSE;\n\n    haddr =\n        mips_mts32_access (cpu, vaddr, MIPS_MEMOP_LD, 8, MTS_READ, &data,\n        &exc, &has_set_value, 0);\n    if (exc)\n        return exc;\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n    if (likely (has_set_value == FALSE))\n        data = vmtoh64 (*(m_uint64_t *) haddr);\n    if (likely (!exc))\n        cpu->reg_set (cpu, reg, data);\n    return (exc);\n}\n\n/* SB: Store Byte */\nu_int fastcall mips_mts32_sb (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    m_reg_t data;\n    void *haddr = NULL;\n    u_int exc;\n    m_uint8_t has_set_value = FALSE;\n\n    data = cpu->gpr[reg] & 0xff;\n    haddr =\n        mips_mts32_access (cpu, vaddr, MIPS_MEMOP_SB, 1, MTS_WRITE, &data,\n        &exc, &has_set_value, 0);\n    if (exc)\n        return exc;\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n    if (likely (has_set_value == FALSE)) {\n#ifdef _USE_JIT_\n        if (cpu->vm->jit_use)\n            jit_handle_self_write (cpu, vaddr);\n#endif\n        *(m_uint8_t *) haddr = data;\n    }\n\n    return (exc);\n}\n\n/* SH: Store Half-Word */\nu_int fastcall mips_mts32_sh (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    m_reg_t data;\n    void *haddr;\n    u_int exc;\n    m_uint8_t has_set_value = FALSE;\n\n    data = cpu->gpr[reg] & 0xffff;\n    haddr =\n        mips_mts32_access (cpu, vaddr, MIPS_MEMOP_SH, 2, MTS_WRITE, &data,\n        &exc, &has_set_value, 0);\n    if (exc)\n        return exc;\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n    if (likely (has_set_value == FALSE)) {\n#ifdef _USE_JIT_\n        if (cpu->vm->jit_use)\n            jit_handle_self_write (cpu, vaddr);\n#endif\n        *(m_uint16_t *) haddr = htovm16 (data);\n    }\n\n    return (exc);\n}\n\n/* SW: Store Word */\nu_int fastcall mips_mts32_sw (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    m_reg_t data;\n    void *haddr;\n    u_int exc;\n    m_uint8_t has_set_value = FALSE;\n\n    data = cpu->gpr[reg] & 0xffffffff;\n\n    haddr =\n        mips_mts32_access (cpu, vaddr, MIPS_MEMOP_SW, 4, MTS_WRITE, &data,\n        &exc, &has_set_value, 0);\n    if (exc)\n        return exc;\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n    if (likely (has_set_value == FALSE)) {\n#ifdef _USE_JIT_\n        if (cpu->vm->jit_use)\n            jit_handle_self_write (cpu, vaddr);\n#endif\n        *(m_uint32_t *) haddr = htovm32 (data);\n        if (cpu->vm->debug_level > 2 || (cpu->vm->debug_level > 1 &&\n            (cpu->cp0.reg[MIPS_CP0_STATUS] & MIPS_CP0_STATUS_UM) &&\n            ! (cpu->cp0.reg[MIPS_CP0_STATUS] & MIPS_CP0_STATUS_EXL) &&\n            vaddr >= 0x7f008000 && vaddr < 0x7f020000))\n        {\n            /* Print memory accesses in user mode. */\n            printf (\"        write %08x := %08x \\n\", vaddr, data);\n        }\n    }\n    return (exc);\n}\n\n/* SD: Store Double-Word */\nu_int fastcall mips_mts32_sd (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    m_reg_t data;\n    void *haddr;\n    u_int exc;\n    m_uint8_t has_set_value = FALSE;\n\n    data = cpu->gpr[reg];\n    haddr =\n        mips_mts32_access (cpu, vaddr, MIPS_MEMOP_SD, 8, MTS_WRITE, &data,\n        &exc, &has_set_value, 0);\n    if (exc)\n        return exc;\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n    if (likely (has_set_value == FALSE))\n        *(m_uint64_t *) haddr = htovm64 (data);\n    return (exc);\n}\n\n/* LDC1: Load Double-Word To Coprocessor 1 */\nu_int fastcall mips_mts32_ldc1 (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    printf (\"mips_mts32_ldc1 pc %x\\n\", cpu->pc);\n    exit (-1);\n    return 0;\n}\n\nu_int fastcall mips_mts32_lwl (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    void *haddr = NULL;\n    u_int exc;\n    m_uint32_t data, naddr, shift = 0, mask1 = 0, mask2 = 0;\n    m_uint8_t has_set_value = FALSE;\n\n    naddr = vaddr & ~(0x03);\n    haddr =\n        mips_mts32_access (cpu, naddr, MIPS_MEMOP_LWL, 4, MTS_READ, &data,\n        &exc, &has_set_value, 0);\n\n    if (exc)\n        return exc;\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n    if (has_set_value == FALSE) {\n        data = vmtoh32 (*(m_reg_t *) haddr);\n\n        switch (vaddr & 0x3) {\n#if\tGUEST_BYTE_ORDER==ARCH_LITTLE_ENDIAN\n        case 0x0:\n#elif GUEST_BYTE_ORDER==ARCH_BIG_ENDIAN\n        case 0x3:\n#endif\n            mask1 = 0xff;\n            mask2 = 0xff000000;\n            shift = 24;\n            break;\n#if\tGUEST_BYTE_ORDER==ARCH_LITTLE_ENDIAN\n        case 0x1:\n#elif GUEST_BYTE_ORDER==ARCH_BIG_ENDIAN\n        case 0x2:\n#endif\n            mask1 = 0xffff;\n            mask2 = 0xffff0000;\n            shift = 16;\n            break;\n#if\tGUEST_BYTE_ORDER==ARCH_LITTLE_ENDIAN\n        case 0x2:\n#elif GUEST_BYTE_ORDER==ARCH_BIG_ENDIAN\n        case 0x1:\n#endif\n            mask1 = 0xffffff;\n            mask2 = 0xffffff00;\n            shift = 8;\n            break;\n#if\tGUEST_BYTE_ORDER==ARCH_LITTLE_ENDIAN\n        case 0x3:\n#elif GUEST_BYTE_ORDER==ARCH_BIG_ENDIAN\n        case 0x0:\n#endif\n            mask1 = 0xffffffff;\n            mask2 = 0xffffffff;\n            shift = 0;\n            break;\n        }\n\n        data = (data & mask1) << shift;\n        data &= mask2;\n        cpu->gpr[reg] &= ~mask2;\n        cpu->gpr[reg] |= data;\n        cpu->reg_set (cpu, reg, sign_extend (cpu->gpr[reg], 32));\n    }\n    return 0;\n}\n\nu_int fastcall mips_mts32_lwr (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    void *haddr = NULL;\n    u_int exc;\n    m_uint32_t data, naddr, shift = 0, mask1 = 0, mask2 = 0;\n    m_uint8_t has_set_value = FALSE;\n\n    naddr = vaddr & ~(0x03);\n    haddr =\n        mips_mts32_access (cpu, naddr, MIPS_MEMOP_LWR, 4, MTS_READ, &data,\n        &exc, &has_set_value, 0);\n\n    if (exc)\n        return exc;\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n\n    if (has_set_value == FALSE) {\n\n        data = vmtoh32 (*(m_reg_t *) haddr);\n\n        switch (vaddr & 0x3) {\n#if\tGUEST_BYTE_ORDER==ARCH_LITTLE_ENDIAN\n        case 0x3:\n#elif GUEST_BYTE_ORDER==ARCH_BIG_ENDIAN\n        case 0x0:\n#endif\n            mask1 = 0xff;\n            mask2 = 0xff000000;\n            shift = 24;\n            break;\n#if\tGUEST_BYTE_ORDER==ARCH_LITTLE_ENDIAN\n        case 0x2:\n#elif GUEST_BYTE_ORDER==ARCH_BIG_ENDIAN\n        case 0x1:\n#endif\n            mask1 = 0xffff;\n            mask2 = 0xffff0000;\n            shift = 16;\n            break;\n#if\tGUEST_BYTE_ORDER==ARCH_LITTLE_ENDIAN\n        case 0x1:\n#elif GUEST_BYTE_ORDER==ARCH_BIG_ENDIAN\n        case 0x2:\n#endif\n\n            mask1 = 0xffffff;\n            mask2 = 0xffffff00;\n            shift = 8;\n            break;\n#if\tGUEST_BYTE_ORDER==ARCH_LITTLE_ENDIAN\n        case 0x0:\n#elif GUEST_BYTE_ORDER==ARCH_BIG_ENDIAN\n        case 0x3:\n#endif\n            mask1 = 0xffffffff;\n            mask2 = 0xffffffff;\n            shift = 0;\n            break;\n        }\n\n        data = (data & mask2) >> shift;\n        data &= mask1;\n        cpu->gpr[reg] &= ~mask1;\n        cpu->gpr[reg] |= data;\n        cpu->reg_set (cpu, reg, sign_extend (cpu->gpr[reg], 32));\n    }\n    return 0;\n}\n\n/* LDL: Load Double-Word Left */\nu_int fastcall mips_mts32_ldl (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    m_reg_t r_mask, naddr;\n    m_reg_t data;\n    u_int m_shift;\n    void *haddr;\n    u_int exc;\n    m_uint8_t has_set_value = FALSE;\n\n    naddr = vaddr & ~(0x07);\n    haddr =\n        mips_mts32_access (cpu, naddr, MIPS_MEMOP_LDL, 8, MTS_READ, &data,\n        &exc, &has_set_value, 0);\n    if (exc)\n        return exc;\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n\n    if (likely (haddr != NULL))\n        data = (m_reg_t) (vmtoh64 (*(m_uint64_t *) haddr));\n\n    if (likely (!exc)) {\n        m_shift = (vaddr & 0x07) << 3;\n        r_mask = (1ULL << m_shift) - 1;\n        data <<= m_shift;\n\n        cpu->gpr[reg] &= r_mask;\n        cpu->gpr[reg] |= data;\n    }\n    return (exc);\n}\n\n/* LDR: Load Double-Word Right */\nu_int fastcall mips_mts32_ldr (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    m_reg_t r_mask, naddr;\n    m_reg_t data;\n    u_int m_shift;\n    void *haddr;\n    u_int exc;\n    m_uint8_t has_set_value = FALSE;\n\n    naddr = vaddr & ~(0x07);\n    haddr =\n        mips_mts32_access (cpu, naddr, MIPS_MEMOP_LDR, 8, MTS_READ, &data,\n        &exc, &has_set_value, 0);\n    if (exc)\n        return exc;\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n\n    if (likely (haddr != NULL))\n        data = (m_reg_t) (vmtoh64 (*(m_uint64_t *) haddr));\n\n    if (likely (!exc)) {\n        m_shift = ((vaddr & 0x07) + 1) << 3;\n        r_mask = (1ULL << m_shift) - 1;\n        data >>= (64 - m_shift);\n\n        cpu->gpr[reg] &= ~r_mask;\n        cpu->gpr[reg] |= data;\n    }\n    return (exc);\n}\n\nu_int fastcall mips_mts32_swl (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    void *haddr = NULL;\n    u_int exc;\n    m_uint32_t data, naddr, temp, mask1 = 0, mask2 = 0, shift = 0;\n    m_uint8_t has_set_value = FALSE;\n\n    naddr = vaddr & ~(0x03ULL);\n    data = cpu->gpr[reg] & 0xffffffff;\n    haddr =\n        mips_mts32_access (cpu, naddr, MIPS_MEMOP_SWL, 4, MTS_WRITE, &data,\n        &exc, &has_set_value, 0);\n    if (exc)\n        return exc;\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n\n    if (has_set_value == FALSE) {\n        switch (vaddr & 0x3) {\n#if\tGUEST_BYTE_ORDER==ARCH_LITTLE_ENDIAN\n        case 0x0:\n#elif GUEST_BYTE_ORDER==ARCH_BIG_ENDIAN\n        case 0x3:\n#endif\n            mask1 = 0xff;\n            mask2 = 0xff000000;\n            shift = 24;\n            break;\n#if\tGUEST_BYTE_ORDER==ARCH_LITTLE_ENDIAN\n        case 0x1:\n#elif GUEST_BYTE_ORDER==ARCH_BIG_ENDIAN\n        case 0x2:\n#endif\n            mask1 = 0xffff;\n            mask2 = 0xffff0000;\n            shift = 16;\n            break;\n#if\tGUEST_BYTE_ORDER==ARCH_LITTLE_ENDIAN\n        case 0x2:\n#elif GUEST_BYTE_ORDER==ARCH_BIG_ENDIAN\n        case 0x1:\n#endif\n            mask1 = 0xffffff;\n            mask2 = 0xffffff00;\n            shift = 8;\n            break;\n#if\tGUEST_BYTE_ORDER==ARCH_LITTLE_ENDIAN\n        case 0x3:\n#elif GUEST_BYTE_ORDER==ARCH_BIG_ENDIAN\n        case 0x0:\n#endif\n            mask1 = 0xffffffff;\n            mask2 = 0xffffffff;\n            shift = 0;\n            break;\n        }\n\n        data = (data & mask2) >> shift;\n        data &= mask1;\n        temp = vmtoh32 (*(m_uint32_t *) haddr);\n\n        temp &= ~mask1;\n        temp = temp | data;\n        *(m_uint32_t *) haddr = htovm32 (temp);\n\n    }\n\n    return 0;\n}\n\nu_int fastcall mips_mts32_swr (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    void *haddr = NULL;\n    u_int exc;\n    m_uint32_t data, naddr, temp, mask1 = 0, mask2 = 0, shift = 0;\n    m_uint8_t has_set_value = FALSE;\n\n    naddr = vaddr & ~(0x03ULL);\n    data = cpu->gpr[reg] & 0xffffffff;\n    haddr =\n        mips_mts32_access (cpu, naddr, MIPS_MEMOP_SWR, 4, MTS_WRITE, &data,\n        &exc, &has_set_value, 0);\n    if (exc)\n        return exc;\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n    if (has_set_value == FALSE) {\n        switch (vaddr & 0x3) {\n#if\tGUEST_BYTE_ORDER==ARCH_LITTLE_ENDIAN\n        case 0x3:\n#elif GUEST_BYTE_ORDER==ARCH_BIG_ENDIAN\n        case 0x0:\n#endif\n            mask1 = 0xff;\n            mask2 = 0xff000000;\n            shift = 24;\n            break;\n#if\tGUEST_BYTE_ORDER==ARCH_LITTLE_ENDIAN\n        case 0x2:\n#elif GUEST_BYTE_ORDER==ARCH_BIG_ENDIAN\n        case 0x1:\n#endif\n            mask1 = 0xffff;\n            mask2 = 0xffff0000;\n            shift = 16;\n            break;\n#if\tGUEST_BYTE_ORDER==ARCH_LITTLE_ENDIAN\n        case 0x1:\n#elif GUEST_BYTE_ORDER==ARCH_BIG_ENDIAN\n        case 0x2:\n#endif\n            mask1 = 0xffffff;\n            mask2 = 0xffffff00;\n            shift = 8;\n            break;\n#if\tGUEST_BYTE_ORDER==ARCH_LITTLE_ENDIAN\n        case 0x0:\n#elif GUEST_BYTE_ORDER==ARCH_BIG_ENDIAN\n        case 0x3:\n#endif\n            mask1 = 0xffffffff;\n            mask2 = 0xffffffff;\n            shift = 0;\n            break;\n        }\n\n        data = (data & mask1) << shift;\n        data &= mask2;\n        temp = vmtoh32 (*(m_uint32_t *) haddr);\n\n        temp &= ~mask2;\n        temp = temp | data;\n        *(m_uint32_t *) haddr = htovm32 (temp);\n    }\n\n    return 0;\n}\n\n/* SDL: Store Double-Word Left */\nu_int fastcall mips_mts32_sdl (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    m_reg_t d_mask, naddr;\n    m_reg_t data;\n    u_int r_shift;\n    void *haddr;\n    u_int exc;\n    m_uint8_t has_set_value = FALSE;\n\n    naddr = vaddr & ~(0x07);\n    haddr =\n        mips_mts32_access (cpu, naddr, MIPS_MEMOP_SDL, 8, MTS_READ, &data,\n        &exc, &has_set_value, 0);\n    if (exc)\n        return exc;\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n    if (unlikely (exc))\n        return (exc);\n\n    if (likely (haddr != NULL))\n        data = (m_reg_t) (vmtoh64 (*(m_uint64_t *) haddr));\n\n    r_shift = (vaddr & 0x07) << 3;\n    d_mask = 0xffffffffffffffffULL >> r_shift;\n\n    data &= ~d_mask;\n    data |= cpu->gpr[reg] >> r_shift;\n\n    haddr =\n        mips_mts32_access (cpu, naddr, MIPS_MEMOP_SDL, 8, MTS_WRITE, &data,\n        &exc, &has_set_value, 0);\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n    if (likely (haddr != NULL))\n        *(m_reg_t *) (m_uint64_t *) haddr = (m_reg_t) (htovm64 (data));\n    return (exc);\n}\n\n/* SDR: Store Double-Word Right */\nu_int fastcall mips_mts32_sdr (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    m_reg_t d_mask, naddr;\n    m_reg_t data;\n    u_int r_shift;\n    void *haddr;\n    u_int exc;\n\n    m_uint8_t has_set_value = FALSE;\n\n    naddr = vaddr & ~(0x07);\n    haddr =\n        mips_mts32_access (cpu, naddr, MIPS_MEMOP_SDR, 8, MTS_READ, &data,\n        &exc, &has_set_value, 0);\n    if (exc)\n        return exc;\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n    if (unlikely (exc))\n        return (exc);\n\n    if (likely (haddr != NULL))\n        data = vmtoh64 (*(m_uint64_t *) haddr);\n\n    r_shift = ((vaddr & 0x07) + 1) << 3;\n    d_mask = 0xffffffffffffffffULL >> r_shift;\n\n    data &= d_mask;\n    data |= cpu->gpr[reg] << (64 - r_shift);\n\n    haddr =\n        mips_mts32_access (cpu, naddr, MIPS_MEMOP_SDR, 8, MTS_WRITE, &data,\n        &exc, &has_set_value, 0);\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n    if (likely (haddr != NULL))\n        *(m_reg_t *) (m_uint64_t *) haddr = (m_reg_t) (htovm64 (data));\n    return (exc);\n}\n\n/* LL: Load Linked */\nu_int fastcall mips_mts32_ll (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    m_reg_t data;\n    void *haddr;\n    u_int exc;\n    m_uint8_t has_set_value = FALSE;\n\n    haddr =\n        mips_mts32_access (cpu, vaddr, MIPS_MEMOP_LL, 4, MTS_READ, &data,\n        &exc, &has_set_value, 0);\n    if (exc)\n        return exc;\n    if ((haddr == NULL) && (has_set_value == FALSE)) {\n        bad_memory_access (cpu, vaddr);\n    }\n    if (likely (haddr != NULL))\n        data = vmtoh32 (*(m_uint32_t *) haddr);\n\n    if (likely (!exc)) {\n        cpu->reg_set (cpu, reg, sign_extend (data, 32));\n        cpu->ll_bit = 1;\n    }\n    return (exc);\n}\n\n/* SC: Store Conditional */\nu_int fastcall mips_mts32_sc (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    m_reg_t data;\n    void *haddr;\n    u_int exc = 0;\n    m_uint8_t has_set_value = FALSE;\n\n    data = cpu->gpr[reg] & 0xffffffff;\n    haddr =\n        mips_mts32_access (cpu, vaddr, MIPS_MEMOP_SC, 4, MTS_WRITE, &data,\n        &exc, &has_set_value, 0);\n    if (exc)\n        return exc;\n\n    if (cpu->ll_bit) {\n        if ((haddr == NULL) && (has_set_value == FALSE)) {\n            bad_memory_access (cpu, vaddr);\n        }\n        if (likely (haddr != NULL))\n            *(m_uint32_t *) haddr = htovm32 (data);\n    }\n\n    if (likely (!exc))\n        cpu->reg_set (cpu, reg, cpu->ll_bit);\n    return (exc);\n}\n\n/* SDC1: Store Double-Word from Coprocessor 1 */\nu_int fastcall mips_mts32_sdc1 (cpu_mips_t * cpu, m_va_t vaddr, u_int reg)\n{\n    /* m_uint64_t data;\n     * void *haddr;\n     * u_int exc;\n     * m_uint8_t has_set_value=FALSE;\n     *\n     *\n     * data = cpu->fpu.reg[reg];\n     * haddr = mips_mts32_access(cpu,vaddr,MIPS_MEMOP_SDC1,8,MTS_WRITE,\n     * &data,&exc,&has_set_value);\n     * if ((haddr==NULL)&&(has_set_value==FALSE))\n     * {\n     * bad_memory_access(cpu,vaddr);\n     * }\n     * if (likely(haddr != NULL)) *(m_uint64_t *)haddr = htovm64(data);\n     * return(exc); */\n    printf (\"mips_mts32_sdc1 pc %x\\n\", cpu->pc);\n    exit (-1);\n    return 0;\n}\n\n/* CACHE: Cache operation */\nu_int fastcall mips_mts32_cache (cpu_mips_t * cpu, m_va_t vaddr, u_int op)\n{\n    return (0);\n}\n\n/* === MTS Cache Management ============================================= */\n\n/* MTS map/unmap/rebuild \"API\" functions */\nvoid mips_mts32_api_map (cpu_mips_t * cpu, m_va_t vaddr, m_pa_t paddr,\n    m_uint32_t len, int cache_access, int tlb_index)\n{\n    /* nothing to do, the cache will be filled on-the-fly */\n}\n\nvoid mips_mts32_api_unmap (cpu_mips_t * cpu, m_va_t vaddr, m_uint32_t len,\n    m_uint32_t val, int tlb_index)\n{\n    /* Invalidate the TLB entry or the full cache if no index is specified */\n    if (tlb_index != -1)\n        mips_mts32_invalidate_tlb_entry (cpu, vaddr);\n    else\n        mips_mts32_invalidate_cache (cpu);\n}\n\nvoid mips_mts32_api_rebuild (cpu_mips_t * cpu)\n{\n    mips_mts32_invalidate_cache ((cpu));\n}\n\n/* ======================================================================== */\n\n/* Initialize memory access vectors */\nvoid mips_mts32_init_memop_vectors (cpu_mips_t * cpu)\n{\n    /* XXX TODO:\n     *  - LD/SD forbidden in Supervisor/User modes with 32-bit addresses.\n     */\n\n    cpu->addr_mode = 32;\n\n    /* API vectors */\n    cpu->mts_map = mips_mts32_api_map;\n    cpu->mts_unmap = mips_mts32_api_unmap;\n\n    /* Memory lookup operation */\n    cpu->mem_op_lookup = mips_mts32_lookup;\n\n    /* Translation operation */\n    cpu->translate = mips_mts32_translate;\n\n    /* Shutdown operation */\n    cpu->mts_shutdown = mips_mts32_shutdown;\n\n    /* Rebuild MTS data structures */\n    cpu->mts_rebuild = mips_mts32_api_rebuild;\n\n    /* Show statistics */\n    //cpu->mts_show_stats = mips_mts32_show_stats;\n\n    cpu->mips_mts_gdb_lb = mips_mts32_gdb_lb;\n\n    /* Load Operations */\n    cpu->mem_op_fn[MIPS_MEMOP_LB] = mips_mts32_lb;\n    cpu->mem_op_fn[MIPS_MEMOP_LBU] = mips_mts32_lbu;\n    cpu->mem_op_fn[MIPS_MEMOP_LH] = mips_mts32_lh;\n    cpu->mem_op_fn[MIPS_MEMOP_LHU] = mips_mts32_lhu;\n    cpu->mem_op_fn[MIPS_MEMOP_LW] = mips_mts32_lw;\n    cpu->mem_op_fn[MIPS_MEMOP_LWU] = mips_mts32_lwu;\n    cpu->mem_op_fn[MIPS_MEMOP_LD] = mips_mts32_ld;\n    cpu->mem_op_fn[MIPS_MEMOP_LDL] = mips_mts32_ldl;\n    cpu->mem_op_fn[MIPS_MEMOP_LDR] = mips_mts32_ldr;\n\n    /* Store Operations */\n    cpu->mem_op_fn[MIPS_MEMOP_SB] = mips_mts32_sb;\n    cpu->mem_op_fn[MIPS_MEMOP_SH] = mips_mts32_sh;\n    cpu->mem_op_fn[MIPS_MEMOP_SW] = mips_mts32_sw;\n    cpu->mem_op_fn[MIPS_MEMOP_SD] = mips_mts32_sd;\n\n    /* Load Left/Right operations */\n    cpu->mem_op_fn[MIPS_MEMOP_LWL] = mips_mts32_lwl;\n    cpu->mem_op_fn[MIPS_MEMOP_LWR] = mips_mts32_lwr;\n    cpu->mem_op_fn[MIPS_MEMOP_LDL] = mips_mts32_ldl;\n    cpu->mem_op_fn[MIPS_MEMOP_LDR] = mips_mts32_ldr;\n\n    /* Store Left/Right operations */\n    cpu->mem_op_fn[MIPS_MEMOP_SWL] = mips_mts32_swl;\n    cpu->mem_op_fn[MIPS_MEMOP_SWR] = mips_mts32_swr;\n    cpu->mem_op_fn[MIPS_MEMOP_SDL] = mips_mts32_sdl;\n    cpu->mem_op_fn[MIPS_MEMOP_SDR] = mips_mts32_sdr;\n\n    /* LL/SC - Load Linked / Store Conditional */\n    cpu->mem_op_fn[MIPS_MEMOP_LL] = mips_mts32_ll;\n    cpu->mem_op_fn[MIPS_MEMOP_SC] = mips_mts32_sc;\n\n    /* Coprocessor 1 memory access functions */\n    cpu->mem_op_fn[MIPS_MEMOP_LDC1] = mips_mts32_ldc1;\n    cpu->mem_op_fn[MIPS_MEMOP_SDC1] = mips_mts32_sdc1;\n\n    /* Cache Operation */\n    cpu->mem_op_fn[MIPS_MEMOP_CACHE] = mips_mts32_cache;\n}\n\n/* === Specific operations for MTS32 ====================================== */\n\n/*\n * MTS32 slow lookup\n */\nstatic mts32_entry_t *mips_mts32_slow_lookup (cpu_mips_t * cpu,\n    m_uint64_t vaddr, u_int op_code, u_int op_size, u_int op_type,\n    m_reg_t * data, u_int * exc, mts32_entry_t * alt_entry, u_int is_fromgdb)\n{\n    m_uint32_t hash_bucket, zone;\n    mts32_entry_t *entry;\n    mts_map_t map;\n\n    map.tlb_index = -1;\n    hash_bucket = MTS32_HASH (vaddr);\n    entry = &cpu->mts_u.mts32_cache[hash_bucket];\n    zone = (vaddr >> 29) & 0x7;\n\n#if DEBUG_MTS_STATS\n    cpu->mts_misses++;\n#endif\n\n    switch (zone) {\n    case 0x00:\n    case 0x01:\n    case 0x02:\n    case 0x03:                 /* kuseg */\n#ifdef SIM_PIC32\n        if (vaddr == 0)\n            goto err_undef;\n        map.vaddr = vaddr & MIPS_MIN_PAGE_MASK;\n        map.paddr = map.vaddr & 0x1ffff;\n        map.mapped = FALSE;\n#else\n        /* trigger TLB exception if no matching entry found */\n        if (! mips_cp0_tlb_lookup (cpu, vaddr, &map))\n            goto err_tlb;\n\n        if ((map.valid & 0x1) != 0x1)\n            goto err_tlb;\n        if ((MTS_WRITE == op_type) && ((map.dirty & 0x1) != 0x1))\n            goto err_mod;\n\n        map.mapped = TRUE;\n#endif\n        entry = mips_mts32_map (cpu, op_type, &map, entry, alt_entry,\n                                is_fromgdb);\n        if (! entry)\n            goto err_undef;\n        return (entry);\n\n    case 0x04:                 /* kseg0 */\n        map.vaddr = vaddr & MIPS_MIN_PAGE_MASK;\n        map.paddr = map.vaddr - (m_pa_t) 0xFFFFFFFF80000000ULL;\n        map.mapped = FALSE;\n\n        entry = mips_mts32_map (cpu, op_type, &map, entry, alt_entry,\n                                is_fromgdb);\n        if (! entry)\n            goto err_undef;\n        return (entry);\n\n    case 0x05:                 /* kseg1 */\n        map.vaddr = vaddr & MIPS_MIN_PAGE_MASK;\n        map.paddr = map.vaddr - (m_pa_t) 0xFFFFFFFFA0000000ULL;\n        map.mapped = FALSE;\n\n        entry = mips_mts32_map (cpu, op_type, &map, entry, alt_entry,\n                                is_fromgdb);\n        if (! entry)\n            goto err_undef;\n        return (entry);\n\n    case 0x06:                 /* ksseg */\n    case 0x07:                 /* kseg3 */\n#ifdef SIM_PIC32\n        map.vaddr = vaddr & MIPS_MIN_PAGE_MASK;\n        map.paddr = map.vaddr & 0x1ffff;\n        map.mapped = FALSE;\n#else\n        //ASSERT(0,\"not implemented upper 1G memory space \\n\");\n        /* trigger TLB exception if no matching entry found */\n        if (! mips_cp0_tlb_lookup (cpu, vaddr, &map))\n            goto err_tlb;\n        if ((map.valid & 0x1) != 0x1)\n            goto err_tlb;\n        if ((MTS_WRITE == op_type) && ((map.dirty & 0x1) != 0x1))\n            goto err_mod;\n        map.mapped = TRUE;\n#endif\n        entry = mips_mts32_map (cpu, op_type, &map, entry, alt_entry,\n                                is_fromgdb);\n        if (! entry)\n            goto err_undef;\n        return (entry);\n    }\n#ifndef SIM_PIC32\nerr_mod:\n    if (is_fromgdb)\n        return NULL;\n    mips_access_special (cpu, vaddr, MTS_ACC_M, op_code, op_type, op_size,\n        data, exc);\n    return NULL;\nerr_tlb:\n    if (is_fromgdb)\n        return NULL;\n    mips_access_special (cpu, vaddr, MTS_ACC_T, op_code, op_type, op_size,\n        data, exc);\n    return NULL;\n#endif\nerr_undef:\n    if (is_fromgdb)\n        return NULL;\n    mips_access_special (cpu, vaddr, MTS_ACC_U, op_code, op_type, op_size,\n        data, exc);\n    return NULL;\n}\n\nstatic forced_inline int mips_mts32_check_tlbcache (cpu_mips_t * cpu,\n    m_va_t vaddr, u_int op_type, mts32_entry_t * entry)\n{\n    m_uint32_t asid;\n    mips_cp0_t *cp0 = &cpu->cp0;\n    asid = cp0->reg[MIPS_CP0_TLB_HI] & MIPS_TLB_ASID_MASK;\n    if (((m_uint32_t) vaddr & MIPS_MIN_PAGE_MASK) != entry->gvpa)\n        return 0;\n    if (entry->mapped == TRUE) {\n        if ((op_type == MTS_WRITE) && (!entry->dirty_bit))\n            return 0;\n        if ((!entry->g_bit) && (asid != entry->asid))\n            return 0;\n    }\n    return 1;\n}\n\n/* MTS32 access */\nvoid *mips_mts32_access (cpu_mips_t * cpu, m_va_t vaddr,\n    u_int op_code, u_int op_size, u_int op_type, m_reg_t * data,\n    u_int * exc, m_uint8_t * has_set_value, u_int is_fromgdb)\n{\n    mts32_entry_t *entry, alt_entry;\n    m_uint32_t hash_bucket;\n    m_iptr_t haddr;\n    u_int dev_id;\n\n/*\nA job need to be done first: check whether access is aligned!!!\nMIPS FPU Emulator use a unaligned lw access to cause exception and then handle it.\n 72\n 73          * The strategy is to push the instruction onto the user stack\n 74          * and put a trap after it which we can catch and jump to\n 75          * the required address any alternative apart from full\n 76          * instruction simulation!!.\n 77          *\n 78          * Algorithmics used a system call instruction, and\n 79          * borrowed that vector.  MIPS/Linux version is a bit\n 80          * more heavyweight in the interests of portability and\n 81          * multiprocessor support.  For Linux we generate a\n 82          * an unaligned access and force an address error exception.\n 83          *\n 84          * For embedded systems (stand-alone) we prefer to use a\n 85          * non-existing CP1 instruction. This prevents us from emulating\n 86          * branches, but gives us a cleaner interface to the exception\n 87          * handler (single entry point).\n 88\n\nI did not check it before version 0.04 and hwclock/qtopia always segment fault.\nVery hard to debug this problem!!!!\nyajin\n*/\n//if (vaddr == 0x7f010020)\n//printf (\"%08x: %s address %08x\\n\", cpu->pc,\n//(op_type == MTS_WRITE) ? \"write\" : \"read\", (unsigned) vaddr);\n\n    if (MTS_HALF_WORD == op_size) {\n        if (unlikely ((vaddr & 0x00000001UL) != 0x0)) {\nerr_addr:   if (is_fromgdb)\n                return NULL;\n            mips_access_special (cpu, vaddr, MTS_ACC_AE, op_code, op_type,\n                op_size, data, exc);\n            return NULL;\n        }\n    } else if (MTS_WORD == op_size) {\n        if ((op_code != MIPS_MEMOP_LWL) && (op_code != MIPS_MEMOP_LWR)\n            && (op_code != MIPS_MEMOP_SWL) && (op_code != MIPS_MEMOP_SWR)) {\n            if (unlikely ((vaddr & 0x00000003UL) != 0x0))\n                goto err_addr;\n        }\n    }\n\n    *exc = 0;\n    hash_bucket = MTS32_HASH (vaddr);\n    entry = &cpu->mts_u.mts32_cache [hash_bucket];\n\n    if (unlikely (mips_mts32_check_tlbcache (cpu, vaddr, op_type,\n                entry) == 0)) {\n        entry = mips_mts32_slow_lookup (cpu, vaddr, op_code, op_size, op_type,\n            data, exc, &alt_entry, is_fromgdb);\n        if (! entry)\n            return NULL;\n        if (entry->flags & MTS_FLAG_DEV) {\n            dev_id = (entry->hpa & MTS_DEVID_MASK) >> MTS_DEVID_SHIFT;\n            haddr = entry->hpa & MTS_DEVOFF_MASK;\n            haddr += vaddr - entry->gvpa;\n\n            void *addr = dev_access_fast (cpu, dev_id, haddr, op_size, op_type,\n                    data, has_set_value);\n/*printf (\"%08x: mts32_access fast returned %p\\n\", cpu->pc, addr);*/\n            return addr;\n        }\n    }\n\n    /* Raw memory access */\n    haddr = entry->hpa + (vaddr & MIPS_MIN_PAGE_IMASK);\n    return ((void *) haddr);\n}\n\n/* MTS32 virtual address to physical address translation */\nstatic int mips_mts32_translate (cpu_mips_t * cpu, m_va_t vaddr,\n    m_pa_t * phys_page)\n{\n    mts32_entry_t *entry, alt_entry;\n    m_uint32_t hash_bucket;\n    m_reg_t data = 0;\n    u_int exc = 0;\n\n    hash_bucket = MTS32_HASH (vaddr);\n    entry = &cpu->mts_u.mts32_cache[hash_bucket];\n\n    if (unlikely (mips_mts32_check_tlbcache (cpu, vaddr, MTS_READ,\n                entry) == 0)) {\n        entry =\n            mips_mts32_slow_lookup (cpu, vaddr, MIPS_MEMOP_LOOKUP, 4,\n            MTS_READ, &data, &exc, &alt_entry, 0);\n        if (! entry)\n            return (-1);\n\n        ASSERT (! (entry->flags & MTS_FLAG_DEV),\n            \"error when translating virtual address to phyaddrss \\n\");\n    }\n    *phys_page = entry->gppa >> MIPS_MIN_PAGE_SHIFT;\n    return (0);\n\n}\n\n/* ======================================================================== */\n\n/* Shutdown MTS subsystem */\nvoid mips_mem_shutdown (cpu_mips_t * cpu)\n{\n    if (cpu->mts_shutdown != NULL)\n        cpu->mts_shutdown (cpu);\n}\n\n/* Set the address mode */\nint mips_set_addr_mode (cpu_mips_t * cpu, u_int addr_mode)\n{\n    if (cpu->addr_mode != addr_mode) {\n        mips_mem_shutdown (cpu);\n\n        switch (addr_mode) {\n        case 32:\n            mips_mts32_init (cpu);\n            mips_mts32_init_memop_vectors (cpu);\n            break;\n            /*case 64:\n             * TODO: 64 bit memory operation\n             * mips_mts64_init(cpu);\n             * mips_mts64_init_memop_vectors(cpu);\n             * break; */\n        default:\n            fprintf (stderr,\n                \"mts_set_addr_mode: internal error (addr_mode=%u)\\n\",\n                addr_mode);\n            exit (EXIT_FAILURE);\n        }\n    }\n\n    return (0);\n}\n\n/*------------------DMA------------------------*/\n\n/* Get host pointer for the physical ram address */\nvoid *physmem_get_hptr (vm_instance_t * vm, m_pa_t paddr, u_int op_size,\n    u_int op_type, m_uint32_t * data)\n{\n\n    struct vdevice *dev;\n    m_uint32_t offset;\n\n    m_uint8_t has_set_value;\n\n    if (!(dev = dev_lookup (vm, paddr)))\n        return NULL;\n\n    /*Only for RAM */\n    if ((dev->host_addr != 0) && !(dev->flags & VDEVICE_FLAG_NO_MTS_MMAP))\n        return ((void *) dev->host_addr + (paddr - dev->phys_addr));\n\n    if (op_size == 0)\n        return NULL;\n\n    ASSERT (0, \"physmem_get_hptr error\\n\");\n    offset = paddr - dev->phys_addr;\n    return (dev->handler (vm->boot_cpu, dev, offset, op_size, op_type, data,\n            &has_set_value));\n}\n\n/* DMA transfer operation */\nvoid physmem_dma_transfer (vm_instance_t * vm, m_pa_t src, m_pa_t dst,\n    size_t len)\n{\n    m_uint32_t dummy;\n    u_char *sptr, *dptr;\n    size_t clen, sl, dl;\n\n    while (len > 0) {\n        sptr = physmem_get_hptr (vm, src, 0, MTS_READ, &dummy);\n        dptr = physmem_get_hptr (vm, dst, 0, MTS_WRITE, &dummy);\n\n        if (!sptr || !dptr) {\n            vm_log (vm, \"DMA\",\n                \"unable to transfer from 0x%\" LL \"x to 0x%\" LL \"x\\n\", src,\n                dst);\n            ASSERT (0, \"physmem_dma_transfer src %x dst %x\\n\", src, dst);\n            return;\n        }\n\n        sl = VM_PAGE_SIZE - (src & VM_PAGE_IMASK);\n        dl = VM_PAGE_SIZE - (dst & VM_PAGE_IMASK);\n        clen = m_min (sl, dl);\n        clen = m_min (clen, len);\n\n        memcpy (dptr, sptr, clen);\n\n        src += clen;\n        dst += clen;\n        len -= clen;\n    }\n}\n"
  },
  {
    "path": "tools/virtualmips/mips_memory.h",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2006 Christophe Fillot (cf@utc.fr)\n */\n\n /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#ifndef __MIPS64_MEM_H__\n#define __MIPS64_MEM_H__\n\n#include <sys/types.h>\n#include \"utils.h\"\n#include \"system.h\"\n/* MTS operation */\n#define MTS_READ        0\n#define MTS_WRITE       1\n\n#define MTS_BYTE        1\n#define MTS_HALF_WORD   2\n#define MTS_WORD        4\n\n/* 0.5GB value */\n#define MTS_SIZE_512M   0x20000000\n\n/* MTS flag bits: D (device), ACC (memory access), C (chain) */\n#define MTS_FLAG_BITS   4\n#define MTS_FLAG_MASK   0x0000000fUL\n\n/* Masks for MTS entries */\n#define MTS_CHAIN_MASK  0x00000001\n#define MTS_ACC_MASK    0x00000006\n#define MTS_DEV_MASK    0x00000008\n#define MTS_ADDR_MASK   (~MTS_FLAG_MASK)\n\n/* Device ID mask and shift, device offset mask */\n#define MTS_DEVID_MASK  0xfc000000\n#define MTS_DEVID_SHIFT 26\n#define MTS_DEVOFF_MASK 0x03fffff0\n\n/* Memory access flags */\n#define MTS_ACC_OK      0x00000000  /* Access OK */\n#define MTS_ACC_AE      0x00000002  /* Address Error */\n#define MTS_ACC_T       0x00000004  /* TLB Exception */\n#define MTS_ACC_U       0x00000006  /* Unexistent */\n#define MTS_ACC_M       0x00000008  /* TLB MODE */\n\n/* Hash table size for MTS64 (default: [shift:16,bits:12]) */\n#define MTS64_HASH_SHIFT        12\n#define MTS64_HASH_BITS         14\n#define MTS64_HASH_SIZE         (1 << MTS64_HASH_BITS)\n#define MTS64_HASH_MASK         (MTS64_HASH_SIZE - 1)\n\n/* MTS64 hash on virtual addresses */\n#define MTS64_HASH(vaddr)       (((vaddr) >> MTS64_HASH_SHIFT) & MTS64_HASH_MASK)\n\n/* Hash table size for MTS32 (default: [shift:15,bits:15]) */\n#define MTS32_HASH_SHIFT        12\n#define MTS32_HASH_BITS         14\n#define MTS32_HASH_SIZE         (1 << MTS32_HASH_BITS)\n#define MTS32_HASH_MASK         (MTS32_HASH_SIZE - 1)\n\n/* MTS32 hash on virtual addresses */\n#define MTS32_HASH(vaddr)       (((vaddr) >> MTS32_HASH_SHIFT) & MTS32_HASH_MASK)\n\n/* Number of entries per chunk */\n#define MTS64_CHUNK_SIZE        256\n#define MTS32_CHUNK_SIZE        256\n\n/* MTS64: chunk definition */\nstruct mts64_chunk {\n    mts64_entry_t entry[MTS64_CHUNK_SIZE];\n    struct mts64_chunk *next;\n    u_int count;\n};\n\n/* MTS32: chunk definition */\nstruct mts32_chunk {\n    mts32_entry_t entry[MTS32_CHUNK_SIZE];\n    struct mts32_chunk *next;\n    u_int count;\n};\n\n/*check whether vaddr need map*/\nstatic int forced_inline vaddr_mapped (m_va_t vaddr)\n{\n    int zone = (vaddr >> 29) & 0x7;\n    if ((zone == 0x4) || (zone == 0x5)) {\n        return 0;\n    } else {\n        return 1;\n    }\n}\n\n/* Shutdown the MTS subsystem */\nvoid mips_mem_shutdown (cpu_mips_t * cpu);\n\n/* Set the address mode */\nint mips_set_addr_mode (cpu_mips_t * cpu, u_int addr_mode);\n\nvoid physmem_dma_transfer (vm_instance_t * vm, m_pa_t src, m_pa_t dst,\n    size_t len);\nvoid *physmem_get_hptr (vm_instance_t * vm, m_pa_t paddr, u_int op_size,\n    u_int op_type, m_uint32_t * data);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/net.h",
    "content": "#ifndef __NET_H__\n#define __NET_H__\n\n#include \"utils.h\"\n\n/* Ethernet Constants */\n#define N_ETH_ALEN  6\n#define N_ETH_HLEN  sizeof(n_eth_hdr_t)\n\n/* Ethernet Address */\ntypedef struct {\n    m_uint8_t eth_addr_byte[N_ETH_ALEN];\n} __attribute__ ((__packed__)) n_eth_addr_t;\n/* Ethernet Header */\ntypedef struct {\n    n_eth_addr_t daddr;         /* destination eth addr */\n    n_eth_addr_t saddr;         /* source ether addr    */\n    m_uint16_t type;            /* packet type ID field */\n} __attribute__ ((__packed__)) n_eth_hdr_t;\n\n/* Check for a broadcast/multicast ethernet address */\nstatic inline int eth_addr_is_bcast (n_eth_addr_t * addr)\n{\n    return ((addr->eth_addr_byte[0] == 0xff)\n        && (addr->eth_addr_byte[1] == 0xff)\n        && (addr->eth_addr_byte[2] == 0xff)\n        && (addr->eth_addr_byte[3] == 0xff)\n        && (addr->eth_addr_byte[4] == 0xff)\n        && (addr->eth_addr_byte[5] == 0xff));\n}\n\nstatic inline int eth_addr_is_mcast (n_eth_addr_t * addr)\n{\n    return ((!eth_addr_is_bcast (addr)) && (addr->eth_addr_byte[0] & 1));\n\n}\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/net_io.c",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)\n *\n * Network Input/Output Abstraction Layer.\n */\n\n/* By default, Cygwin supports only 64 FDs with select()! */\n#ifdef __CYGWIN__\n#define FD_SETSIZE 1024\n#endif\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdarg.h>\n#include <unistd.h>\n#include <errno.h>\n#include <signal.h>\n#include <fcntl.h>\n#include <ctype.h>\n#include <time.h>\n#include <sys/time.h>\n#include <sys/stat.h>\n#include <sys/types.h>\n#include <sys/ioctl.h>\n#include <sys/socket.h>\n#include <sys/un.h>\n#include <sys/wait.h>\n#include <netinet/in.h>\n#include <arpa/inet.h>\n#include <netdb.h>\n#include <pthread.h>\n\n#ifdef __linux__\n#include <net/if.h>\n#include <linux/if_tun.h>\n#endif\n\n#include \"net.h\"\n#include \"net_io.h\"\n\n/* Free a NetIO descriptor */\nstatic int netio_free (void *data, void *arg);\n#if 0\n/* NIO RX listener */\nstatic pthread_mutex_t netio_rxl_mutex = PTHREAD_MUTEX_INITIALIZER;\nstatic pthread_mutex_t netio_rxq_mutex = PTHREAD_MUTEX_INITIALIZER;\nstatic struct netio_rx_listener *netio_rxl_list = NULL;\nstatic struct netio_rx_listener *netio_rxl_add_list = NULL;\nstatic netio_desc_t *netio_rxl_remove_list = NULL;\nstatic pthread_t netio_rxl_thread;\nstatic pthread_cond_t netio_rxl_cond;\n\n#define NETIO_RXL_LOCK()   pthread_mutex_lock(&netio_rxl_mutex);\n#define NETIO_RXL_UNLOCK() pthread_mutex_unlock(&netio_rxl_mutex);\n\n#define NETIO_RXQ_LOCK()   pthread_mutex_lock(&netio_rxq_mutex);\n#define NETIO_RXQ_UNLOCK() pthread_mutex_unlock(&netio_rxq_mutex);\n#endif\n\n/* NetIO type */\ntypedef struct {\n    char *name;\n    char *desc;\n} netio_type_t;\n\n/* NETIO types (must follow the enum definition) */\nstatic netio_type_t netio_types[NETIO_TYPE_MAX] = {\n    {\"unix\", \"UNIX local sockets\"},\n    {\"vde\", \"Virtual Distributed Ethernet / UML switch\"},\n    {\"tap\", \"Linux/FreeBSD TAP device\"},\n    {\"udp\", \"UDP sockets\"},\n    {\"tcp_cli\", \"TCP client\"},\n    {\"tcp_ser\", \"TCP server\"},\n#ifdef LINUX_ETH\n    {\"linux_eth\", \"Linux Ethernet device\"},\n#endif\n#ifdef GEN_ETH\n    {\"gen_eth\", \"Generic Ethernet device (PCAP)\"},\n#endif\n    {\"fifo\", \"FIFO (intra-hypervisor)\"},\n    {\"null\", \"Null device\"},\n};\n\n/* Get NETIO type given a description */\nint netio_get_type (char *type)\n{\n    int i;\n\n    for (i = 0; i < NETIO_TYPE_MAX; i++)\n        if (!strcmp (type, netio_types[i].name))\n            return (i);\n\n    return (-1);\n}\n\n/* Show the NETIO types */\nvoid netio_show_types (void)\n{\n    int i;\n\n    printf (\"Available NETIO types:\\n\");\n\n    for (i = 0; i < NETIO_TYPE_MAX; i++)\n        printf (\"  * %-10s : %s\\n\", netio_types[i].name, netio_types[i].desc);\n\n    printf (\"\\n\");\n}\n\n/* Create a new NetIO descriptor */\nstatic netio_desc_t *netio_create (char *name)\n{\n    netio_desc_t *nio;\n\n    if (!(nio = malloc (sizeof (*nio))))\n        return NULL;\n\n    /* setup as a NULL descriptor */\n    memset (nio, 0, sizeof (*nio));\n    nio->type = NETIO_TYPE_NULL;\n\n    /* save name for registry */\n    if (!(nio->name = strdup (name))) {\n        free (nio);\n        return NULL;\n    }\n\n    return nio;\n}\n\n/* Send a packet through a NetIO descriptor */\nssize_t netio_send (netio_desc_t * nio, void *pkt, size_t len)\n{\n\n    if (!nio)\n        return (-1);\n\n    if (nio->debug) {\n        printf (\"NIO %s: sending a packet of %lu bytes:\\n\", nio->name,\n            (u_long) len);\n        mem_dump (stdout, pkt, len);\n    }\n\n    return (nio->send (nio->dptr, pkt, len));\n}\n\n/* Receive a packet through a NetIO descriptor */\nssize_t netio_recv (netio_desc_t * nio, void *pkt, size_t max_len)\n{\n    ssize_t len;\n\n    if (!nio)\n        return (-1);\n\n    /* Receive the packet */\n    if ((len = nio->recv (nio->dptr, pkt, max_len)) <= 0)\n        return (-1);\n\n    if (nio->debug) {\n        printf (\"NIO %s: receiving a packet of %ld bytes:\\n\", nio->name,\n            (long) len);\n        mem_dump (stdout, pkt, len);\n    }\n\n    return (len);\n}\n\n/* Get a NetIO FD */\nint netio_get_fd (netio_desc_t * nio)\n{\n    int fd = -1;\n\n    switch (nio->type) {\n        //case NETIO_TYPE_UNIX:\n        //   fd = nio->u.nud.fd;\n        //   break;\n        //case NETIO_TYPE_VDE:\n        //   fd = nio->u.nvd.data_fd;\n        //    break;\n    case NETIO_TYPE_TAP:\n        fd = nio->u.ntd.fd;\n        break;\n        //case NETIO_TYPE_TCP_CLI:\n        //case NETIO_TYPE_TCP_SER:\n        //case NETIO_TYPE_UDP:\n        //   fd = nio->u.nid.fd;\n        //   break;\n//#ifdef LINUX_ETH\n//      case NETIO_TYPE_LINUX_ETH:\n//         fd = nio->u.nled.fd;\n//         break;\n//#endif\n    }\n\n    return (fd);\n}\n\n#if 0\n/*\n * =========================================================================\n * UNIX sockets\n * =========================================================================\n */\n\n/* Create an UNIX socket */\nstatic int netio_unix_create_socket (netio_unix_desc_t * nud)\n{\n    struct sockaddr_un local_sock;\n\n    if ((nud->fd = socket (AF_UNIX, SOCK_DGRAM, 0)) == -1) {\n        perror (\"netio_unix: socket\");\n        return (-1);\n    }\n\n    memset (&local_sock, 0, sizeof (local_sock));\n    local_sock.sun_family = AF_UNIX;\n    strlcpy (local_sock.sun_path, nud->local_filename,\n        sizeof(local_sock.sun_path));\n\n    if (bind (nud->fd, (struct sockaddr *) &local_sock,\n            sizeof (local_sock)) == -1) {\n        perror (\"netio_unix: bind\");\n        return (-1);\n    }\n\n    return (nud->fd);\n}\n\n/* Free a NetIO unix descriptor */\nstatic void netio_unix_free (netio_unix_desc_t * nud)\n{\n    if (nud->fd != -1)\n        close (nud->fd);\n\n    if (nud->local_filename) {\n        unlink (nud->local_filename);\n        free (nud->local_filename);\n    }\n}\n\n/* Allocate a new NetIO UNIX descriptor */\nstatic int netio_unix_create (netio_unix_desc_t * nud, char *local,\n    char *remote)\n{\n    memset (nud, 0, sizeof (*nud));\n    nud->fd = -1;\n\n    /* check lengths */\n    if ((strlen (local) >= sizeof (nud->remote_sock.sun_path))\n        || (strlen (remote) >= sizeof (nud->remote_sock.sun_path)))\n        goto nomem_error;\n\n    if (!(nud->local_filename = strdup (local)))\n        goto nomem_error;\n\n    if (netio_unix_create_socket (nud) == -1)\n        return (-1);\n\n    /* prepare the remote info */\n    nud->remote_sock.sun_family = AF_UNIX;\n    strlcpy (nud->remote_sock.sun_path, remote,\n        sizeof(nud->remote_sock.sun_path));\n    return (0);\n\n  nomem_error:\n    fprintf (stderr,\n        \"netio_unix_create: \" \"invalid file size or insufficient memory\\n\");\n    return (-1);\n}\n\n/* Write a packet to an UNIX socket */\nstatic ssize_t netio_unix_send (netio_unix_desc_t * nud, void *pkt,\n    size_t pkt_len)\n{\n    return (sendto (nud->fd, pkt, pkt_len, 0,\n            (struct sockaddr *) &nud->remote_sock,\n            sizeof (&nud->remote_sock)));\n}\n\n/* Receive a packet from an UNIX socket */\nstatic ssize_t netio_unix_recv (netio_unix_desc_t * nud, void *pkt,\n    size_t max_len)\n{\n    return (recvfrom (nud->fd, pkt, max_len, 0, NULL, NULL));\n}\n\n/* Save the NIO configuration */\nstatic void netio_unix_save_cfg (netio_desc_t * nio, FILE * fd)\n{\n    netio_unix_desc_t *nud = nio->dptr;\n    fprintf (fd, \"nio create_unix %s %s %s\\n\", nio->name, nud->local_filename,\n        nud->remote_sock.sun_path);\n}\n\n/* Create a new NetIO descriptor with UNIX method */\nnetio_desc_t *netio_desc_create_unix (char *nio_name, char *local,\n    char *remote)\n{\n    netio_desc_t *nio;\n\n    if (!(nio = netio_create (nio_name)))\n        return NULL;\n\n    if (netio_unix_create (&nio->u.nud, local, remote) == -1) {\n        netio_free (nio, NULL);\n        return NULL;\n    }\n\n    nio->type = NETIO_TYPE_UNIX;\n    nio->send = (void *) netio_unix_send;\n    nio->recv = (void *) netio_unix_recv;\n    nio->save_cfg = netio_unix_save_cfg;\n    nio->dptr = &nio->u.nud;\n\n    if (netio_record (nio) == -1) {\n        netio_free (nio, NULL);\n        return NULL;\n    }\n\n    return nio;\n}\n\n/*\n * =========================================================================\n * VDE (Virtual Distributed Ethernet) interface\n * =========================================================================\n */\n\n/* Free a NetIO VDE descriptor */\nstatic void netio_vde_free (netio_vde_desc_t * nvd)\n{\n    if (nvd->data_fd != -1)\n        close (nvd->data_fd);\n\n    if (nvd->ctrl_fd != -1)\n        close (nvd->ctrl_fd);\n\n    if (nvd->local_filename) {\n        unlink (nvd->local_filename);\n        free (nvd->local_filename);\n    }\n}\n\n/* Create a new NetIO VDE descriptor */\nstatic int netio_vde_create (netio_vde_desc_t * nvd, char *control,\n    char *local)\n{\n    struct sockaddr_un ctrl_sock, tst;\n    struct vde_request_v3 req;\n    ssize_t len;\n    int res;\n\n    memset (nvd, 0, sizeof (*nvd));\n    nvd->ctrl_fd = nvd->data_fd = -1;\n\n    if ((strlen (control) >= sizeof (ctrl_sock.sun_path))\n        || (strlen (local) >= sizeof (nvd->remote_sock.sun_path))) {\n        fprintf (stderr, \"netio_vde_create: bad filenames specified\\n\");\n        return (-1);\n    }\n\n    /* Copy the local filename */\n    if (!(nvd->local_filename = strdup (local))) {\n        fprintf (stderr, \"netio_vde_create: insufficient memory\\n\");\n        return (-1);\n    }\n\n    /* Connect to the VDE switch controller */\n    nvd->ctrl_fd = socket (AF_UNIX, SOCK_STREAM, 0);\n    if (nvd->ctrl_fd < 0) {\n        perror (\"netio_vde_create: socket(control)\");\n        return (-1);\n    }\n\n    memset (&ctrl_sock, 0, sizeof (ctrl_sock));\n    ctrl_sock.sun_family = AF_UNIX;\n    strlcpy (ctrl_sock.sun_path, control, sizeof(ctrl_sock.sun_path));\n\n    res =\n        connect (nvd->ctrl_fd, (struct sockaddr *) &ctrl_sock,\n        sizeof (ctrl_sock));\n\n    if (res < 0) {\n        perror (\"netio_vde_create: connect(control)\");\n        return (-1);\n    }\n\n    tst.sun_family = AF_UNIX;\n    strlcpy (tst.sun_path, local, sizeof(tst.sun_path));\n\n    /* Create the data connection */\n    nvd->data_fd = socket (AF_UNIX, SOCK_DGRAM, 0);\n    if (nvd->data_fd < 0) {\n        perror (\"netio_vde_create: socket(data)\");\n        return (-1);\n    }\n\n    if (bind (nvd->data_fd, (struct sockaddr *) &tst, sizeof (tst)) < 0) {\n        perror (\"netio_vde_create: bind(data)\");\n        return (-1);\n    }\n\n    /* Now, process to registration */\n    memset (&req, 0, sizeof (req));\n    req.sock.sun_family = AF_UNIX;\n    strlcpy (req.sock.sun_path, local, sizeof(req.sock.sun_path));\n    req.magic = VDE_SWITCH_MAGIC;\n    req.version = VDE_SWITCH_VERSION;\n    req.type = VDE_REQ_NEW_CONTROL;\n\n    len = write (nvd->ctrl_fd, &req, sizeof (req));\n    if (len != sizeof (req)) {\n        perror (\"netio_vde_create: write(req)\");\n        return (-1);\n    }\n\n    /* Read the remote socket descriptor */\n    len = read (nvd->ctrl_fd, &nvd->remote_sock, sizeof (nvd->remote_sock));\n    if (len != sizeof (nvd->remote_sock)) {\n        perror (\"netio_vde_create: read(req)\");\n        return (-1);\n    }\n\n    return (0);\n}\n\n/* Write a packet to a VDE data socket */\nstatic ssize_t netio_vde_send (netio_vde_desc_t * nvd, void *pkt,\n    size_t pkt_len)\n{\n    return (sendto (nvd->data_fd, pkt, pkt_len, 0,\n            (struct sockaddr *) &nvd->remote_sock,\n            sizeof (nvd->remote_sock)));\n}\n\n/* Receive a packet from a VDE socket */\nstatic ssize_t netio_vde_recv (netio_vde_desc_t * nvd, void *pkt,\n    size_t max_len)\n{\n    return (recvfrom (nvd->data_fd, pkt, max_len, 0, NULL, NULL));\n}\n\n/* Save the NIO configuration */\nstatic void netio_vde_save_cfg (netio_desc_t * nio, FILE * fd)\n{\n    netio_vde_desc_t *nvd = nio->dptr;\n    fprintf (fd, \"nio create_vde %s %s %s\\n\", nio->name,\n        nvd->remote_sock.sun_path, nvd->local_filename);\n}\n\n/* Create a new NetIO descriptor with VDE method */\nnetio_desc_t *netio_desc_create_vde (char *nio_name, char *control,\n    char *local)\n{\n    netio_vde_desc_t *nvd;\n    netio_desc_t *nio;\n\n    if (!(nio = netio_create (nio_name)))\n        return NULL;\n\n    nvd = &nio->u.nvd;\n\n    if (netio_vde_create (nvd, control, local) == -1) {\n        netio_free (nio, NULL);\n        return NULL;\n    }\n\n    nio->type = NETIO_TYPE_VDE;\n    nio->send = (void *) netio_vde_send;\n    nio->recv = (void *) netio_vde_recv;\n    nio->save_cfg = netio_vde_save_cfg;\n    nio->dptr = &nio->u.nvd;\n\n    if (netio_record (nio) == -1) {\n        netio_free (nio, NULL);\n        return NULL;\n    }\n\n    return nio;\n}\n#endif\n/*\n * =========================================================================\n * TAP devices\n * =========================================================================\n */\n\n/* Free a NetIO TAP descriptor */\nstatic void netio_tap_free (netio_tap_desc_t * ntd)\n{\n    if (ntd->fd != -1)\n        close (ntd->fd);\n}\n\n/* Open a TAP device */\nstatic int netio_tap_open (char *tap_devname)\n{\n#ifdef __linux__\n    struct ifreq ifr;\n    int fd, err;\n\n    if ((fd = open (\"/dev/net/tun\", O_RDWR)) < 0)\n        return (-1);\n\n    memset (&ifr, 0, sizeof (ifr));\n\n    /* Flags: IFF_TUN   - TUN device (no Ethernet headers)\n     *        IFF_TAP   - TAP device\n     *\n     *        IFF_NO_PI - Do not provide packet information\n     */\n    ifr.ifr_flags = IFF_TAP | IFF_NO_PI;\n    if (*tap_devname)\n        strncpy (ifr.ifr_name, tap_devname, IFNAMSIZ);\n\n    if ((err = ioctl (fd, TUNSETIFF, (void *) &ifr)) < 0) {\n        close (fd);\n        return err;\n    }\n\n    strlcpy (tap_devname, ifr.ifr_name, NETIO_DEV_MAXLEN);\n    return (fd);\n#else\n    int i, fd = -1;\n\n    if (*tap_devname) {\n        fd = open (tap_devname, O_RDWR);\n    } else {\n        for (i = 0; i < 16; i++) {\n            snprintf (tap_devname, NETIO_DEV_MAXLEN, \"/dev/tap%d\", i);\n\n            if ((fd = open (tap_devname, O_RDWR)) >= 0)\n                break;\n        }\n    }\n\n    return (fd);\n#endif\n}\n\n/* Allocate a new NetIO TAP descriptor */\nstatic int netio_tap_create (netio_tap_desc_t * ntd, char *tap_name)\n{\n    if (strlen (tap_name) >= NETIO_DEV_MAXLEN) {\n        fprintf (stderr,\n            \"netio_tap_create: bad TAP device string specified.\\n\");\n        return (-1);\n    }\n\n    memset (ntd, 0, sizeof (*ntd));\n    strlcpy (ntd->filename, tap_name, NETIO_DEV_MAXLEN);\n    ntd->fd = netio_tap_open (ntd->filename);\n\n    if (ntd->fd == -1) {\n        fprintf (stderr,\n            \"netio_tap_create: unable to open TAP device %s (%s)\\n\", tap_name,\n            strerror (errno));\n        return (-1);\n    }\n    /*SET NO BLOCKING */\n    if (fcntl (ntd->fd, F_SETFL, O_NONBLOCK) == -1)\n        printf (\"Set file descriptor to non-blocking mode failed\\n\");\n\n    return (0);\n}\n\n/* Write a packet to a TAP device */\nstatic ssize_t netio_tap_send (netio_tap_desc_t * ntd, void *pkt,\n    size_t pkt_len)\n{\n    return (write (ntd->fd, pkt, pkt_len));\n}\n\n/* Receive a packet through a TAP device */\nstatic ssize_t netio_tap_recv (netio_tap_desc_t * ntd, void *pkt,\n    size_t max_len)\n{\n    return (read (ntd->fd, pkt, max_len));\n}\n\n/* Create a new NetIO descriptor with TAP method */\nnetio_desc_t *netio_desc_create_tap (char *nio_name, char *tap_name)\n{\n    netio_tap_desc_t *ntd;\n    netio_desc_t *nio;\n\n    if (!(nio = netio_create (nio_name)))\n        return NULL;\n\n    ntd = &nio->u.ntd;\n\n    if (netio_tap_create (ntd, tap_name) == -1) {\n        netio_free (nio, NULL);\n        return NULL;\n    }\n\n    nio->type = NETIO_TYPE_TAP;\n    nio->send = (void *) netio_tap_send;\n    nio->recv = (void *) netio_tap_recv;\n    nio->dptr = &nio->u.ntd;\n\n    return nio;\n}\n\n#if 0\n/*\n * =========================================================================\n * TCP sockets\n * =========================================================================\n */\n\n/* Free a NetIO TCP descriptor */\nstatic void netio_tcp_free (netio_inet_desc_t * nid)\n{\n    if (nid->fd != -1)\n        close (nid->fd);\n}\n\n/*\n * very simple protocol to send packets over tcp\n * 32 bits in network format - size of packet, then packet itself and so on.\n */\nstatic ssize_t netio_tcp_send (netio_inet_desc_t * nid, void *pkt,\n    size_t pkt_len)\n{\n    u_long l = htonl (pkt_len);\n\n    if (write (nid->fd, &l, sizeof (l)) == -1)\n        return (-1);\n\n    return (write (nid->fd, pkt, pkt_len));\n}\n\nstatic ssize_t netio_tcp_recv (netio_inet_desc_t * nid, void *pkt,\n    size_t max_len)\n{\n    u_long l;\n\n    if (read (nid->fd, &l, sizeof (l)) != sizeof (l))\n        return (-1);\n\n    if (ntohl (l) > max_len)\n        return (-1);\n\n    return (read (nid->fd, pkt, ntohl (l)));\n}\n\nstatic int netio_tcp_cli_create (netio_inet_desc_t * nid, char *host,\n    char *port)\n{\n    struct sockaddr_in serv;\n    struct servent *sp;\n    struct hostent *hp;\n\n    if ((nid->fd = socket (PF_INET, SOCK_STREAM, 0)) < 0) {\n        perror (\"netio_tcp_cli_create: socket\");\n        return (-1);\n    }\n\n    memset (&serv, 0, sizeof (serv));\n    serv.sin_family = AF_INET;\n\n    if (atoi (port) == 0) {\n        if (!(sp = getservbyname (port, \"tcp\"))) {\n            fprintf (stderr,\n                \"netio_tcp_cli_create: port %s is neither \"\n                \"number not service %s\\n\", port, strerror (errno));\n            close (nid->fd);\n            return (-1);\n        }\n        serv.sin_port = sp->s_port;\n    } else\n        serv.sin_port = htons (atoi (port));\n\n    if (inet_addr (host) == INADDR_NONE) {\n        if (!(hp = gethostbyname (host))) {\n            fprintf (stderr, \"netio_tcp_cli_create: no host %s\\n\", host);\n            close (nid->fd);\n            return (-1);\n        }\n        serv.sin_addr.s_addr = *hp->h_addr;\n    } else\n        serv.sin_addr.s_addr = inet_addr (host);\n\n    if (connect (nid->fd, (struct sockaddr *) &serv, sizeof (serv)) < 0) {\n        fprintf (stderr, \"netio_tcp_cli_create: connect to %s:%s failed %s\\n\",\n            host, port, strerror (errno));\n        close (nid->fd);\n        return (-1);\n    }\n    return (0);\n}\n\n/* Create a new NetIO descriptor with TCP_CLI method */\nnetio_desc_t *netio_desc_create_tcp_cli (char *nio_name, char *host,\n    char *port)\n{\n    netio_desc_t *nio;\n\n    if (!(nio = netio_create (nio_name)))\n        return NULL;\n\n    if (netio_tcp_cli_create (&nio->u.nid, host, port) < 0) {\n        netio_free (nio, NULL);\n        return NULL;\n    }\n\n    nio->type = NETIO_TYPE_TCP_CLI;\n    nio->send = (void *) netio_tcp_send;\n    nio->recv = (void *) netio_tcp_recv;\n    nio->dptr = &nio->u.nid;\n\n    if (netio_record (nio) == -1) {\n        netio_free (nio, NULL);\n        return NULL;\n    }\n\n    return nio;\n}\n\nstatic int netio_tcp_ser_create (netio_inet_desc_t * nid, char *port)\n{\n    struct sockaddr_in serv;\n    struct servent *sp;\n    int sock_fd;\n\n    if ((sock_fd = socket (PF_INET, SOCK_STREAM, 0)) < 0) {\n        perror (\"netio_tcp_cli_create: socket\\n\");\n        return (-1);\n    }\n\n    memset (&serv, 0, sizeof (serv));\n    serv.sin_family = AF_INET;\n    serv.sin_addr.s_addr = htonl (INADDR_ANY);\n\n    if (atoi (port) == 0) {\n        if (!(sp = getservbyname (port, \"tcp\"))) {\n            fprintf (stderr,\n                \"netio_tcp_ser_create: port %s is neither \"\n                \"number not service %s\\n\", port, strerror (errno));\n            close (sock_fd);\n            return (-1);\n        }\n        serv.sin_port = sp->s_port;\n    } else\n        serv.sin_port = htons (atoi (port));\n\n    if (bind (sock_fd, (struct sockaddr *) &serv, sizeof (serv)) < 0) {\n        fprintf (stderr, \"netio_tcp_ser_create: bind %s failed %s\\n\", port,\n            strerror (errno));\n        close (sock_fd);\n        return (-1);\n    }\n\n    if (listen (sock_fd, 1) < 0) {\n        fprintf (stderr, \"netio_tcp_ser_create: listen %s failed %s\\n\", port,\n            strerror (errno));\n        close (sock_fd);\n        return (-1);\n    }\n\n    fprintf (stderr, \"Waiting connection on port %s...\\n\", port);\n\n    if ((nid->fd = accept (sock_fd, NULL, NULL)) < 0) {\n        fprintf (stderr, \"netio_tcp_ser_create: accept %s failed %s\\n\", port,\n            strerror (errno));\n        close (sock_fd);\n        return (-1);\n    }\n\n    fprintf (stderr, \"Connected\\n\");\n\n    close (sock_fd);\n    return (0);\n}\n\n/* Create a new NetIO descriptor with TCP_SER method */\nnetio_desc_t *netio_desc_create_tcp_ser (char *nio_name, char *port)\n{\n    netio_desc_t *nio;\n\n    if (!(nio = netio_create (nio_name)))\n        return NULL;\n\n    if (netio_tcp_ser_create (&nio->u.nid, port) == -1) {\n        netio_free (nio, NULL);\n        return NULL;\n    }\n\n    nio->type = NETIO_TYPE_TCP_SER;\n    nio->send = (void *) netio_tcp_send;\n    nio->recv = (void *) netio_tcp_recv;\n    nio->dptr = &nio->u.nid;\n\n    if (netio_record (nio) == -1) {\n        netio_free (nio, NULL);\n        return NULL;\n    }\n\n    return nio;\n}\n\n/*\n * =========================================================================\n * UDP sockets\n * =========================================================================\n */\n\n/* Free a NetIO UDP descriptor */\nstatic void netio_udp_free (netio_inet_desc_t * nid)\n{\n    if (nid->remote_host) {\n        free (nid->remote_host);\n        nid->remote_host = NULL;\n    }\n\n    if (nid->fd != -1)\n        close (nid->fd);\n}\n\n/* Write a packet to an UDP socket */\nstatic ssize_t netio_udp_send (netio_inet_desc_t * nid, void *pkt,\n    size_t pkt_len)\n{\n    return (send (nid->fd, pkt, pkt_len, 0));\n}\n\n/* Receive a packet from an UDP socket */\nstatic ssize_t netio_udp_recv (netio_inet_desc_t * nid, void *pkt,\n    size_t max_len)\n{\n    return (recvfrom (nid->fd, pkt, max_len, 0, NULL, NULL));\n}\n\n/* Save the NIO configuration */\nstatic void netio_udp_save_cfg (netio_desc_t * nio, FILE * fd)\n{\n    netio_inet_desc_t *nid = nio->dptr;\n    fprintf (fd, \"nio create_udp %s %d %s %d\\n\", nio->name, nid->local_port,\n        nid->remote_host, nid->remote_port);\n}\n\n/* Create a new NetIO descriptor with UDP method */\nnetio_desc_t *netio_desc_create_udp (char *nio_name, int local_port,\n    char *remote_host, int remote_port)\n{\n    netio_inet_desc_t *nid;\n    netio_desc_t *nio;\n\n    if (!(nio = netio_create (nio_name)))\n        return NULL;\n\n    nid = &nio->u.nid;\n    nid->local_port = local_port;\n    nid->remote_port = remote_port;\n\n    if (!(nid->remote_host = strdup (remote_host))) {\n        fprintf (stderr, \"netio_desc_create_udp: insufficient memory\\n\");\n        goto error;\n    }\n\n    if ((nid->fd = udp_connect (local_port, remote_host, remote_port)) < 0) {\n        fprintf (stderr,\n            \"netio_desc_create_udp: unable to connect to %s:%d\\n\",\n            remote_host, remote_port);\n        goto error;\n    }\n\n    nio->type = NETIO_TYPE_UDP;\n    nio->send = (void *) netio_udp_send;\n    nio->recv = (void *) netio_udp_recv;\n    nio->save_cfg = netio_udp_save_cfg;\n    nio->dptr = &nio->u.nid;\n\n    if (netio_record (nio) == -1)\n        goto error;\n\n    return nio;\n\n  error:\n    netio_free (nio, NULL);\n    return NULL;\n}\n\n/*\n * =========================================================================\n * Linux RAW Ethernet driver\n * =========================================================================\n */\n#ifdef LINUX_ETH\n/* Free a NetIO raw ethernet descriptor */\nstatic void netio_lnxeth_free (netio_lnxeth_desc_t * nled)\n{\n    if (nled->fd != -1)\n        close (nled->fd);\n}\n\n/* Write a packet to a raw Ethernet socket */\nstatic ssize_t netio_lnxeth_send (netio_lnxeth_desc_t * nled, void *pkt,\n    size_t pkt_len)\n{\n    return (lnx_eth_send (nled->fd, nled->dev_id, pkt, pkt_len));\n}\n\n/* Receive a packet from an raw Ethernet socket */\nstatic ssize_t netio_lnxeth_recv (netio_lnxeth_desc_t * nled, void *pkt,\n    size_t max_len)\n{\n    return (lnx_eth_recv (nled->fd, pkt, max_len));\n}\n\n/* Save the NIO configuration */\nstatic void netio_lnxeth_save_cfg (netio_desc_t * nio, FILE * fd)\n{\n    netio_lnxeth_desc_t *nled = nio->dptr;\n    fprintf (fd, \"nio create_linux_eth %s %s\\n\", nio->name, nled->dev_name);\n}\n\n/* Create a new NetIO descriptor with raw Ethernet method */\nnetio_desc_t *netio_desc_create_lnxeth (char *nio_name, char *dev_name)\n{\n    netio_lnxeth_desc_t *nled;\n    netio_desc_t *nio;\n\n    if (!(nio = netio_create (nio_name)))\n        return NULL;\n\n    nled = &nio->u.nled;\n\n    if (strlen (dev_name) >= NETIO_DEV_MAXLEN) {\n        fprintf (stderr,\n            \"netio_desc_create_lnxeth: bad Ethernet device string \"\n            \"specified.\\n\");\n        netio_free (nio, NULL);\n        return NULL;\n    }\n\n    strlcpy (nled->dev_name, dev_name, NETIO_DEV_MAXLEN);\n\n    nled->fd = lnx_eth_init_socket (dev_name);\n    nled->dev_id = lnx_eth_get_dev_index (dev_name);\n\n    if (nled->fd < 0) {\n        netio_free (nio, NULL);\n        return NULL;\n    }\n\n    nio->type = NETIO_TYPE_LINUX_ETH;\n    nio->send = (void *) netio_lnxeth_send;\n    nio->recv = (void *) netio_lnxeth_recv;\n    nio->save_cfg = netio_lnxeth_save_cfg;\n    nio->dptr = &nio->u.nled;\n\n    if (netio_record (nio) == -1) {\n        netio_free (nio, NULL);\n        return NULL;\n    }\n\n    return nio;\n}\n#endif /* LINUX_ETH */\n\n/*\n * =========================================================================\n * Generic RAW Ethernet driver\n * =========================================================================\n */\n#ifdef GEN_ETH\n/* Free a NetIO raw ethernet descriptor */\nstatic void netio_geneth_free (netio_geneth_desc_t * nged)\n{\n    gen_eth_close (nged->pcap_dev);\n}\n\n/* Write a packet to an Ethernet device */\nstatic ssize_t netio_geneth_send (netio_geneth_desc_t * nged, void *pkt,\n    size_t pkt_len)\n{\n    return (gen_eth_send (nged->pcap_dev, pkt, pkt_len));\n}\n\n/* Receive a packet from an Ethernet device */\nstatic ssize_t netio_geneth_recv (netio_geneth_desc_t * nged, void *pkt,\n    size_t max_len)\n{\n    return (gen_eth_recv (nged->pcap_dev, pkt, max_len));\n}\n\n/* Save the NIO configuration */\nstatic void netio_geneth_save_cfg (netio_desc_t * nio, FILE * fd)\n{\n    netio_geneth_desc_t *nged = nio->dptr;\n    fprintf (fd, \"nio create_gen_eth %s %s\\n\", nio->name, nged->dev_name);\n}\n\n/* Create a new NetIO descriptor with generic raw Ethernet method */\nnetio_desc_t *netio_desc_create_geneth (char *nio_name, char *dev_name)\n{\n    netio_geneth_desc_t *nged;\n    netio_desc_t *nio;\n\n    if (!(nio = netio_create (nio_name)))\n        return NULL;\n\n    nged = &nio->u.nged;\n\n    if (strlen (dev_name) >= NETIO_DEV_MAXLEN) {\n        fprintf (stderr,\n            \"netio_desc_create_geneth: bad Ethernet device string \"\n            \"specified.\\n\");\n        netio_free (nio, NULL);\n        return NULL;\n    }\n\n    strlcpy (nged->dev_name, dev_name, NETIO_DEV_MAXLEN);\n\n    if (!(nged->pcap_dev = gen_eth_init (dev_name))) {\n        netio_free (nio, NULL);\n        return NULL;\n    }\n\n    nio->type = NETIO_TYPE_GEN_ETH;\n    nio->send = (void *) netio_geneth_send;\n    nio->recv = (void *) netio_geneth_recv;\n    nio->save_cfg = netio_geneth_save_cfg;\n    nio->dptr = &nio->u.nged;\n\n    if (netio_record (nio) == -1) {\n        netio_free (nio, NULL);\n        return NULL;\n    }\n\n    return nio;\n}\n#endif /* GEN_ETH */\n\n/*\n * =========================================================================\n * FIFO Driver (intra-hypervisor communications)\n * =========================================================================\n */\n\n/* Extract the first packet of the FIFO */\nstatic netio_fifo_pkt_t *netio_fifo_extract_pkt (netio_fifo_desc_t * nfd)\n{\n    netio_fifo_pkt_t *p;\n\n    if (!(p = nfd->head))\n        return NULL;\n\n    nfd->pkt_count--;\n    nfd->head = p->next;\n\n    if (!nfd->head)\n        nfd->last = NULL;\n\n    return p;\n}\n\n/* Insert a packet into the FIFO (in tail) */\nstatic void netio_fifo_insert_pkt (netio_fifo_desc_t * nfd,\n    netio_fifo_pkt_t * p)\n{\n    pthread_mutex_lock (&nfd->lock);\n\n    nfd->pkt_count++;\n    p->next = NULL;\n\n    if (nfd->last) {\n        nfd->last->next = p;\n    } else {\n        nfd->head = p;\n    }\n\n    nfd->last = p;\n    pthread_mutex_unlock (&nfd->lock);\n}\n\n/* Free the packet list */\nstatic void netio_fifo_free_pkt_list (netio_fifo_desc_t * nfd)\n{\n    netio_fifo_pkt_t *p, *next;\n\n    for (p = nfd->head; p; p = next) {\n        next = p->next;\n        free (p);\n    }\n\n    nfd->head = nfd->last = NULL;\n    nfd->pkt_count = 0;\n}\n\n/* Establish a cross-connect between two FIFO NetIO */\nint netio_fifo_crossconnect (netio_desc_t * a, netio_desc_t * b)\n{\n    netio_fifo_desc_t *pa, *pb;\n\n    if ((a->type != NETIO_TYPE_FIFO) || (b->type != NETIO_TYPE_FIFO))\n        return (-1);\n\n    pa = &a->u.nfd;\n    pb = &b->u.nfd;\n\n    /* A => B */\n    pthread_mutex_lock (&pa->endpoint_lock);\n    pthread_mutex_lock (&pa->lock);\n    pa->endpoint = pb;\n    netio_fifo_free_pkt_list (pa);\n    pthread_mutex_unlock (&pa->lock);\n    pthread_mutex_unlock (&pa->endpoint_lock);\n\n    /* B => A */\n    pthread_mutex_lock (&pb->endpoint_lock);\n    pthread_mutex_lock (&pb->lock);\n    pb->endpoint = pa;\n    netio_fifo_free_pkt_list (pb);\n    pthread_mutex_unlock (&pb->lock);\n    pthread_mutex_unlock (&pb->endpoint_lock);\n    return (0);\n}\n\n/* Unbind an endpoint */\nstatic void netio_fifo_unbind_endpoint (netio_fifo_desc_t * nfd)\n{\n    pthread_mutex_lock (&nfd->endpoint_lock);\n    nfd->endpoint = NULL;\n    pthread_mutex_unlock (&nfd->endpoint_lock);\n}\n\n/* Free a NetIO FIFO descriptor */\nstatic void netio_fifo_free (netio_fifo_desc_t * nfd)\n{\n    if (nfd->endpoint)\n        netio_fifo_unbind_endpoint (nfd->endpoint);\n\n    netio_fifo_free_pkt_list (nfd);\n    pthread_mutex_destroy (&nfd->lock);\n    pthread_cond_destroy (&nfd->cond);\n}\n\n/* Send a packet (to the endpoint FIFO) */\nstatic ssize_t netio_fifo_send (netio_fifo_desc_t * nfd, void *pkt,\n    size_t pkt_len)\n{\n    netio_fifo_pkt_t *p;\n    size_t len;\n\n    pthread_mutex_lock (&nfd->endpoint_lock);\n\n    /* The cross-connect must have been established before */\n    if (!nfd->endpoint)\n        goto error;\n\n    /* Allocate a a new packet and insert it into the endpoint FIFO */\n    len = sizeof (netio_fifo_pkt_t) + pkt_len;\n    if (!(p = malloc (len)))\n        goto error;\n\n    memcpy (p->pkt, pkt, pkt_len);\n    p->pkt_len = pkt_len;\n    netio_fifo_insert_pkt (nfd->endpoint, p);\n    pthread_cond_signal (&nfd->endpoint->cond);\n    pthread_mutex_unlock (&nfd->endpoint_lock);\n    return (pkt_len);\n\n  error:\n    pthread_mutex_unlock (&nfd->endpoint_lock);\n    return (-1);\n}\n\n/* Read a packet from the local FIFO queue */\nstatic ssize_t netio_fifo_recv (netio_fifo_desc_t * nfd, void *pkt,\n    size_t max_len)\n{\n    struct timespec ts;\n    m_tmcnt_t expire;\n    netio_fifo_pkt_t *p;\n    size_t len = -1;\n\n    /* Wait for the endpoint to signal a new arriving packet */\n    expire = m_gettime_usec () + 50000;\n    ts.tv_sec = expire / 1000000;\n    ts.tv_nsec = (expire % 1000000) * 1000;\n\n    pthread_mutex_lock (&nfd->lock);\n    pthread_cond_timedwait (&nfd->cond, &nfd->lock, &ts);\n\n    /* Extract a packet from the list */\n    p = netio_fifo_extract_pkt (nfd);\n    pthread_mutex_unlock (&nfd->lock);\n\n    if (p) {\n        len = m_min (p->pkt_len, max_len);\n        memcpy (pkt, p->pkt, len);\n        free (p);\n    }\n\n    return (len);\n}\n\n/* Create a new NetIO descriptor with FIFO method */\nnetio_desc_t *netio_desc_create_fifo (char *nio_name)\n{\n    netio_fifo_desc_t *nfd;\n    netio_desc_t *nio;\n\n    if (!(nio = netio_create (nio_name)))\n        return NULL;\n\n    nfd = &nio->u.nfd;\n    pthread_mutex_init (&nfd->lock, NULL);\n    pthread_mutex_init (&nfd->endpoint_lock, NULL);\n    pthread_cond_init (&nfd->cond, NULL);\n\n    nio->type = NETIO_TYPE_FIFO;\n    nio->send = (void *) netio_fifo_send;\n    nio->recv = (void *) netio_fifo_recv;\n    nio->dptr = nfd;\n\n    if (netio_record (nio) == -1) {\n        netio_free (nio, NULL);\n        return NULL;\n    }\n\n    return nio;\n}\n\n/*\n * =========================================================================\n * NULL Driver (does nothing, used for debugging)\n * =========================================================================\n */\nstatic ssize_t netio_null_send (void *null_ptr, void *pkt, size_t pkt_len)\n{\n    return (pkt_len);\n}\n\nstatic ssize_t netio_null_recv (void *null_ptr, void *pkt, size_t max_len)\n{\n    usleep (200000);\n    return (-1);\n}\n\nstatic void netio_null_save_cfg (netio_desc_t * nio, FILE * fd)\n{\n    fprintf (fd, \"nio create_null %s\\n\", nio->name);\n}\n\n/* Create a new NetIO descriptor with NULL method */\nnetio_desc_t *netio_desc_create_null (char *nio_name)\n{\n    netio_desc_t *nio;\n\n    if (!(nio = netio_create (nio_name)))\n        return NULL;\n\n    nio->type = NETIO_TYPE_NULL;\n    nio->send = (void *) netio_null_send;\n    nio->recv = (void *) netio_null_recv;\n    nio->save_cfg = netio_null_save_cfg;\n    nio->dptr = NULL;\n\n    if (netio_record (nio) == -1) {\n        netio_free (nio, NULL);\n        return NULL;\n    }\n\n    return nio;\n}\n#endif\n\n/* Free a NetIO descriptor */\nstatic int netio_free (void *data, void *arg)\n{\n    netio_desc_t *nio = data;\n\n    if (nio) {\n\n        switch (nio->type) {\n        case NETIO_TYPE_TAP:\n            netio_tap_free (&nio->u.ntd);\n            break;\n        case NETIO_TYPE_NULL:\n            break;\n        default:\n            fprintf (stderr, \"NETIO: unknown descriptor type %u\\n\",\n                nio->type);\n        }\n        free (nio->name);\n        free (nio);\n    }\n\n    return (TRUE);\n}\n\n#if 0\n/*\n * =========================================================================\n * RX Listeners\n * =========================================================================\n */\n\n/* Find a RX listener */\nstatic inline struct netio_rx_listener *netio_rxl_find (netio_desc_t * nio)\n{\n    struct netio_rx_listener *rxl;\n\n    for (rxl = netio_rxl_list; rxl; rxl = rxl->next)\n        if (rxl->nio == nio)\n            return rxl;\n\n    return NULL;\n}\n\n/* Remove a NIO from the listener list */\nstatic int netio_rxl_remove_internal (netio_desc_t * nio)\n{\n    struct netio_rx_listener *rxl;\n    int res = -1;\n\n    if ((rxl = netio_rxl_find (nio))) {\n        /* we suppress this NIO only when the ref count hits 0 */\n        rxl->ref_count--;\n\n        if (!rxl->ref_count) {\n            /* remove this listener from the double linked list */\n            if (rxl->next)\n                rxl->next->prev = rxl->prev;\n\n            if (rxl->prev)\n                rxl->prev->next = rxl->next;\n            else\n                netio_rxl_list = rxl->next;\n\n            /* if this is non-FD NIO, wait for thread to terminate */\n            if (netio_get_fd (rxl->nio) == -1) {\n                rxl->running = FALSE;\n                pthread_join (rxl->spec_thread, NULL);\n            }\n\n            free (rxl);\n        }\n\n        res = 0;\n    }\n\n    return (res);\n}\n\n/* Add a RXL listener to the listener list */\nstatic void netio_rxl_add_internal (struct netio_rx_listener *rxl)\n{\n    struct netio_rx_listener *tmp;\n\n    if ((tmp = netio_rxl_find (rxl->nio))) {\n        tmp->ref_count++;\n        free (rxl);\n    } else {\n        rxl->prev = NULL;\n        rxl->next = netio_rxl_list;\n        if (rxl->next)\n            rxl->next->prev = rxl;\n        netio_rxl_list = rxl;\n    }\n}\n\n/* RX Listener dedicated thread (for non-FD NIO) */\nstatic void *netio_rxl_spec_thread (void *arg)\n{\n    struct netio_rx_listener *rxl = arg;\n    netio_desc_t *nio = rxl->nio;\n    ssize_t pkt_len;\n    while (rxl->running) {\n\n        pkt_len = netio_recv (nio, nio->rx_pkt, sizeof (nio->rx_pkt));\n        if (pkt_len > 0) {\n            rxl->rx_handler (nio, nio->rx_pkt, pkt_len, rxl->arg1, rxl->arg2);\n        }\n    }\n\n    return NULL;\n}\n\n/* RX Listener General Thread */\nvoid *netio_rxl_gen_thread (void *arg)\n{\n    struct netio_rx_listener *rxl;\n    ssize_t pkt_len;\n    netio_desc_t *nio;\n    struct timeval tv;\n    int fd, fd_max, res;\n    fd_set rfds;\n\n    for (;;) {\n        NETIO_RXL_LOCK ();\n\n        NETIO_RXQ_LOCK ();\n        /* Add the new waiting NIO to the active list */\n        while (netio_rxl_add_list != NULL) {\n            rxl = netio_rxl_add_list;\n            netio_rxl_add_list = netio_rxl_add_list->next;\n            netio_rxl_add_internal (rxl);\n        }\n\n        /* Delete the NIO present in the remove list */\n        while (netio_rxl_remove_list != NULL) {\n            nio = netio_rxl_remove_list;\n            netio_rxl_remove_list = netio_rxl_remove_list->rxl_next;\n            netio_rxl_remove_internal (nio);\n        }\n\n        pthread_cond_broadcast (&netio_rxl_cond);\n        NETIO_RXQ_UNLOCK ();\n\n        /* Build the FD set */\n        FD_ZERO (&rfds);\n        fd_max = -1;\n        for (rxl = netio_rxl_list; rxl; rxl = rxl->next) {\n            if ((fd = netio_get_fd (rxl->nio)) == -1)\n                continue;\n\n            if (fd > fd_max)\n                fd_max = fd;\n            FD_SET (fd, &rfds);\n        }\n        NETIO_RXL_UNLOCK ();\n\n        /* Wait for incoming packets */\n        tv.tv_sec = 0;\n        tv.tv_usec = 2 * 1000;  /* 2 ms */\n        res = select (fd_max + 1, &rfds, NULL, NULL, &tv);\n\n        if (res == -1) {\n            if (errno != EINTR)\n                perror (\"netio_rxl_thread: select\");\n            continue;\n        }\n\n        /* Examine active FDs and call user handlers */\n        NETIO_RXL_LOCK ();\n\n        for (rxl = netio_rxl_list; rxl; rxl = rxl->next) {\n            nio = rxl->nio;\n\n            if ((fd = netio_get_fd (nio)) == -1)\n                continue;\n\n            if (FD_ISSET (fd, &rfds)) {\n                {\n                    pkt_len =\n                        netio_recv (nio, nio->rx_pkt, sizeof (nio->rx_pkt));\n\n                    if (pkt_len > 0) {\n                        rxl->rx_handler (nio, nio->rx_pkt, pkt_len, rxl->arg1,\n                            rxl->arg2);\n                    }\n                }\n            }\n        }\n    }\n    NETIO_RXL_UNLOCK ();\n}\n\nreturn NULL;\n}\n\n/* Add a RX listener in the listener list */\nint netio_rxl_add (netio_desc_t * nio, netio_rx_handler_t rx_handler,\n    void *arg1, void *arg2)\n{\n    struct netio_rx_listener *rxl;\n\n    NETIO_RXQ_LOCK ();\n\n    if (!(rxl = malloc (sizeof (*rxl)))) {\n        NETIO_RXQ_UNLOCK ();\n        fprintf (stderr, \"netio_rxl_add: unable to create structure.\\n\");\n        return (-1);\n    }\n\n    memset (rxl, 0, sizeof (*rxl));\n    rxl->nio = nio;\n    rxl->ref_count = 1;\n    rxl->rx_handler = rx_handler;\n    rxl->arg1 = arg1;\n    rxl->arg2 = arg2;\n    rxl->running = TRUE;\n\n    if ((netio_get_fd (rxl->nio) == -1) &&\n        pthread_create (&rxl->spec_thread, NULL, netio_rxl_spec_thread, rxl)) {\n        NETIO_RXQ_UNLOCK ();\n        fprintf (stderr,\n            \"netio_rxl_add: unable to create specific thread.\\n\");\n        free (rxl);\n        return (-1);\n    }\n\n    rxl->next = netio_rxl_add_list;\n    netio_rxl_add_list = rxl;\n\n    pthread_cond_wait (&netio_rxl_cond, &netio_rxq_mutex);\n    NETIO_RXQ_UNLOCK ();\n    return (0);\n}\n\n/* Remove a NIO from the listener list */\nint netio_rxl_remove (netio_desc_t * nio)\n{\n    NETIO_RXQ_LOCK ();\n    nio->rxl_next = netio_rxl_remove_list;\n    netio_rxl_remove_list = nio;\n    pthread_cond_wait (&netio_rxl_cond, &netio_rxq_mutex);\n    NETIO_RXQ_UNLOCK ();\n    return (0);\n}\n\n/* Initialize the RXL thread */\nint netio_rxl_init (void)\n{\n    pthread_cond_init (&netio_rxl_cond, NULL);\n\n    if (pthread_create (&netio_rxl_thread, NULL, netio_rxl_gen_thread, NULL)) {\n        perror (\"netio_rxl_init: pthread_create\");\n        return (-1);\n    }\n\n    return (0);\n}\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/net_io.h",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)\n *\n * Network I/O Layer.\n */\n\n#ifndef __NET_IO_H__\n#define __NET_IO_H__\n\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <sys/un.h>\n#include <pthread.h>\n#include \"utils.h\"\n\n/* Maximum packet size */\n#define NETIO_MAX_PKT_SIZE  32768\n\n/* Maximum device length */\n#define NETIO_DEV_MAXLEN    64\n\nenum {\n    NETIO_TYPE_UNIX = 0,\n    NETIO_TYPE_VDE,\n    NETIO_TYPE_TAP,\n    NETIO_TYPE_UDP,\n    NETIO_TYPE_TCP_CLI,\n    NETIO_TYPE_TCP_SER,\n#ifdef LINUX_ETH\n    NETIO_TYPE_LINUX_ETH,\n#endif\n#ifdef GEN_ETH\n    NETIO_TYPE_GEN_ETH,\n#endif\n    NETIO_TYPE_FIFO,\n    NETIO_TYPE_NULL,\n    NETIO_TYPE_MAX,\n};\n\nenum {\n    NETIO_FILTER_ACTION_DROP = 0,\n    NETIO_FILTER_ACTION_PASS,\n    NETIO_FILTER_ACTION_ALTER,\n    NETIO_FILTER_ACTION_DUPLICATE,\n};\n\ntypedef struct netio_desc netio_desc_t;\n\n/* VDE switch definitions */\nenum vde_request_type { VDE_REQ_NEW_CONTROL };\n\n#define VDE_SWITCH_MAGIC   0xfeedface\n#define VDE_SWITCH_VERSION 3\n\nstruct vde_request_v3 {\n    m_uint32_t magic;\n    m_uint32_t version;\n    enum vde_request_type type;\n    struct sockaddr_un sock;\n};\n\n/* netio unix descriptor */\ntypedef struct netio_unix_desc netio_unix_desc_t;\nstruct netio_unix_desc {\n    char *local_filename;\n    struct sockaddr_un remote_sock;\n    int fd;\n};\n\n/* netio vde descriptor */\ntypedef struct netio_vde_desc netio_vde_desc_t;\nstruct netio_vde_desc {\n    char *local_filename;\n    struct sockaddr_un remote_sock;\n    int ctrl_fd, data_fd;\n};\n\n/* netio tap descriptor */\ntypedef struct netio_tap_desc netio_tap_desc_t;\nstruct netio_tap_desc {\n    char filename[NETIO_DEV_MAXLEN];\n    int fd;\n};\n\n/* netio udp/tcp descriptor */\ntypedef struct netio_inet_desc netio_inet_desc_t;\nstruct netio_inet_desc {\n    int local_port, remote_port;\n    char *remote_host;\n    int fd;\n};\n\n#ifdef LINUX_ETH\n/* netio linux raw ethernet descriptor */\ntypedef struct netio_lnxeth_desc netio_lnxeth_desc_t;\nstruct netio_lnxeth_desc {\n    char dev_name[NETIO_DEV_MAXLEN];\n    int dev_id, fd;\n};\n#endif\n\n#ifdef GEN_ETH\n/* netio generic raw ethernet descriptor */\ntypedef struct netio_geneth_desc netio_geneth_desc_t;\nstruct netio_geneth_desc {\n    char dev_name[NETIO_DEV_MAXLEN];\n    pcap_t *pcap_dev;\n};\n#endif\n\n/* FIFO packet */\ntypedef struct netio_fifo_pkt netio_fifo_pkt_t;\nstruct netio_fifo_pkt {\n    netio_fifo_pkt_t *next;\n    size_t pkt_len;\n    char pkt[0];\n};\n\n/* Netio FIFO */\ntypedef struct netio_fifo_desc netio_fifo_desc_t;\nstruct netio_fifo_desc {\n    pthread_cond_t cond;\n    pthread_mutex_t lock, endpoint_lock;\n    netio_fifo_desc_t *endpoint;\n    netio_fifo_pkt_t *head, *last;\n    u_int pkt_count;\n};\n\n/* Packet filter */\ntypedef struct netio_pktfilter netio_pktfilter_t;\nstruct netio_pktfilter {\n    char *name;\n    int (*setup) (netio_desc_t * nio, void **opt, int argc, char *argv[]);\n    void (*free) (netio_desc_t * nio, void **opt);\n    int (*pkt_handler) (netio_desc_t * nio, void *pkt, size_t len, void *opt);\n    netio_pktfilter_t *next;\n};\n\n/* Generic netio descriptor */\nstruct netio_desc {\n    u_int type;\n    void *dptr;\n    char *name;\n    int debug;\n\n    /*can nio recv packet now? */\n    //u_int can_recv;\n\n    /* Frame Relay specific information */\n    //m_uint8_t fr_lmi_seq;\n    //void *fr_conn_list;\n\n    /* Ethernet specific information */\n    //u_int vlan_port_type;\n    //m_uint16_t vlan_id;\n    //void *vlan_input_vector;\n\n    union {\n        //netio_unix_desc_t nud;\n        //netio_vde_desc_t nvd;\n        netio_tap_desc_t ntd;\n        //netio_inet_desc_t nid;\n#ifdef LINUX_ETH\n        //netio_lnxeth_desc_t nled;\n#endif\n#ifdef GEN_ETH\n        //netio_geneth_desc_t nged;\n#endif\n        //netio_fifo_desc_t nfd;\n    } u;\n\n    /* Send and receive prototypes */\n          ssize_t (*send) (void *desc, void *pkt, size_t len);\n          ssize_t (*recv) (void *desc, void *pkt, size_t len);\n\n    /* Configuration saving */\n    //void (*save_cfg)(netio_desc_t *nio,FILE *fd);\n\n    /* Packet filters */\n    //netio_pktfilter_t *rx_filter,*tx_filter,*both_filter;\n    //void *rx_filter_data,*tx_filter_data,*both_filter_data;\n\n    /* Next pointer (for RX listener) */\n    netio_desc_t *rxl_next;\n\n    /* Packet data */\n    u_char rx_pkt[NETIO_MAX_PKT_SIZE];\n};\n\n/* RX listener */\ntypedef int (*netio_rx_handler_t) (netio_desc_t * nio, u_char * pkt,\n    ssize_t pkt_len, void *arg1, void *arg2);\n\nstruct netio_rx_listener {\n    netio_desc_t *nio;\n    u_int ref_count;\n    volatile int running;\n    netio_rx_handler_t rx_handler;\n    void *arg1, *arg2;\n    pthread_t spec_thread;\n    struct netio_rx_listener *prev, *next;\n\n};\n\n/* Get NETIO type given a description */\nint netio_get_type (char *type);\n\n/* Show the NETIO types */\nvoid netio_show_types (void);\n\n/* Create a new NetIO descriptor */\nnetio_desc_t *netio_desc_create_unix (char *nio_name, char *local,\n    char *remote);\n\n/* Create a new NetIO descriptor with VDE method */\nnetio_desc_t *netio_desc_create_vde (char *nio_name, char *control,\n    char *local);\n\n/* Create a new NetIO descriptor with TAP method */\nnetio_desc_t *netio_desc_create_tap (char *nio_name, char *tap_name);\n\n/* Create a new NetIO descriptor with TCP_CLI method */\nnetio_desc_t *netio_desc_create_tcp_cli (char *nio_name, char *addr,\n    char *port);\n\n/* Create a new NetIO descriptor with TCP_SER method */\nnetio_desc_t *netio_desc_create_tcp_ser (char *nio_name, char *port);\n\n/* Create a new NetIO descriptor with UDP method */\nnetio_desc_t *netio_desc_create_udp (char *nio_name, int local_port,\n    char *remote_host, int remote_port);\n\n#ifdef LINUX_ETH\n/* Create a new NetIO descriptor with raw Ethernet method */\nnetio_desc_t *netio_desc_create_lnxeth (char *nio_name, char *dev_name);\n#endif\n\n#ifdef GEN_ETH\n/* Create a new NetIO descriptor with generic raw Ethernet method */\nnetio_desc_t *netio_desc_create_geneth (char *nio_name, char *dev_name);\n#endif\n\n/* Establish a cross-connect between two FIFO NetIO */\nint netio_fifo_crossconnect (netio_desc_t * a, netio_desc_t * b);\n\n/* Create a new NetIO descriptor with FIFO method */\nnetio_desc_t *netio_desc_create_fifo (char *nio_name);\n\n/* Create a new NetIO descriptor with NULL method */\nnetio_desc_t *netio_desc_create_null (char *nio_name);\n\n/* Acquire a reference to NIO from registry (increment reference count) */\nnetio_desc_t *netio_acquire (char *name);\n\n/* Release an NIO (decrement reference count) */\nint netio_release (char *name);\n\n/* Delete a NetIO descriptor */\nint netio_delete (char *name);\n\n/* Delete all NetIO descriptors */\nint netio_delete_all (void);\n\n/* Save the configuration of a NetIO descriptor */\nvoid netio_save_config (netio_desc_t * nio, FILE * fd);\n\n/* Save configurations of all NetIO descriptors */\nvoid netio_save_config_all (FILE * fd);\n\n/* Send a packet through a NetIO descriptor */\nssize_t netio_send (netio_desc_t * nio, void *pkt, size_t len);\n\n/* Receive a packet through a NetIO descriptor */\nssize_t netio_recv (netio_desc_t * nio, void *pkt, size_t max_len);\n\n/* Get a NetIO FD */\nint netio_get_fd (netio_desc_t * nio);\n\n/* Enable a RX listener */\nint netio_rxl_enable (netio_desc_t * nio);\n\n/* Add an RX listener in the listener list */\nint netio_rxl_add (netio_desc_t * nio, netio_rx_handler_t rx_handler,\n    void *arg1, void *arg2);\n\n/* Remove a NIO from the listener list */\nint netio_rxl_remove (netio_desc_t * nio);\n\n/* Initialize the RXL thread */\nint netio_rxl_init (void);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/pavo.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  */\n\n#define _GNU_SOURCE\n#include<string.h>\n#include <assert.h>\n#include<stdlib.h>\n#include <confuse.h>\n\n#include \"vp_lock.h\"\n#include \"utils.h\"\n#include \"mips.h\"\n#include \"vm.h\"\n#include \"cpu.h\"\n#include \"mips_exec.h\"\n#include \"debug.h\"\n\n#include \"pavo.h\"\n#include \"device.h\"\n#include \"dev_cs8900.h\"\n#include \"mips_jit.h\"\n\n#define MIPS_TIMER_INTERRUPT    7\n\nextern m_uint32_t jz4740_int_table[JZ4740_INT_INDEX_MAX];\nint dev_jz4740_gpio_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len);\nint dev_jz4740_uart_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len, u_int irq, vtty_t * vtty);\nint dev_jz4740_cpm_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len);\nint dev_jz4740_emc_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len);\nint dev_jz4740_rtc_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len);\nint dev_jz4740_wdt_tcu_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len);\nint dev_jz4740_int_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len);\nint dev_jz4740_dma_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len);\nint dev_jz4740_lcd_init (vm_instance_t * vm, char *name, m_pa_t paddr,\n    m_uint32_t len);\n\nvoid dev_jz4740_gpio_setirq (int irq);\nvoid dev_jz4740_gpio_clearirq (int irq);\n\n/* Initialize default parameters for pavo */\nstatic void pavo_init_defaults (pavo_t * pavo)\n{\n    vm_instance_t *vm = pavo->vm;\n\n    if (vm->configure_filename == NULL)\n        vm->configure_filename = strdup (PAVO_DEFAULT_CONFIG_FILE);\n    vm->ram_size = PAVO_DEFAULT_RAM_SIZE;\n    vm->boot_method = PAVO_DEFAULT_BOOT_METHOD;\n    vm->kernel_filename = strdup (PAVO_DEFAULT_KERNEL_FILENAME);\n}\n\nint pavo_init_cs8900 (pavo_t * pavo, char *name, m_pa_t paddr, m_uint32_t len,\n    int irq_no)\n{\n\n    struct vm_instance *vm = pavo->vm;\n\n    int nio_type = -1;\n    netio_desc_t *nio;\n    int count;\n    char *tokens[10];\n    struct cs8900_data *d;\n\n    if ((count = m_strsplit (pavo->cs8900_iotype, ':', tokens, 10)) < 2) {\n        vm_error (vm, \"unable to parse NIO description '%s'.\\n\",\n            pavo->cs8900_iotype);\n        return (-1);\n    }\n    nio_type = netio_get_type (tokens[0]);\n\n    switch (nio_type) {\n    case NETIO_TYPE_TAP:\n        nio = netio_desc_create_tap (name, tokens[1]);\n        break;\n        //case NETIO_TYPE_LINUX_ETH:\n        //      nio=netio_desc_create_lnxeth(name,tokens[1]);\n        //      break;\n    default:\n        return (-1);\n    }\n    if (!nio) {\n        vm_error (vm, \"unable to create NETIO  descriptor %s\\n\", tokens[0]);\n        return (-1);\n    }\n    d = dev_cs8900_init (vm, name, paddr, len, irq_no);\n    if (!d) {\n        vm_error (vm, \"unable to int cs8900\\n\");\n        return (-1);\n    }\n    if (dev_cs8900_set_nio (d, nio) == -1) {\n        vm_error (vm, \"unable to set cs8900 nio \\n\");\n        return (-1);\n    }\n\n    return 0;\n\n}\n\n/* Initialize the PAVO Platform (MIPS) */\nstatic int pavo_init_platform (pavo_t * pavo)\n{\n    struct vm_instance *vm = pavo->vm;\n    cpu_mips_t *cpu0;\n    void *(*cpu_run_fn) (void *);\n\n    vm_init_vtty (vm);\n\n    /* Create a CPU group */\n    vm->cpu_group = cpu_group_create (\"System CPU\");\n\n    /* Initialize the virtual MIPS processor */\n    if (!(cpu0 = cpu_create (vm, CPU_TYPE_MIPS32, 0))) {\n        vm_error (vm, \"unable to create CPU0!\\n\");\n        return (-1);\n    }\n    /* Add this CPU to the system CPU group */\n    cpu_group_add (vm->cpu_group, cpu0);\n    vm->boot_cpu = cpu0;\n\n    cpu_run_fn = (void *) mips_exec_run_cpu;\n    /* create the CPU thread execution */\n    if (pthread_create (&cpu0->cpu_thread, NULL, cpu_run_fn, cpu0) != 0) {\n        fprintf (stderr, \"cpu_create: unable to create thread for CPU%u\\n\",\n            0);\n        free (cpu0);\n        return (-1);\n    }\n    cpu0->addr_bus_mask = PAVO_ADDR_BUS_MASK;\n\n    /* Initialize RAM */\n    vm_ram_init (vm, 0x00000000ULL);\n\n    /*create 1GB nand flash */\n    if ((vm->flash_size == 0x400) && (vm->flash_type = FLASH_TYPE_NAND_FLASH))\n        if (dev_nand_flash_1g_init (vm, \"NAND FLASH 1G\", NAND_DATAPORT,\n                0x10004, &(pavo->nand_flash)) == -1)\n            return (-1);\n    if (dev_jz4740_gpio_init (vm, \"JZ4740 GPIO\", JZ4740_GPIO_BASE,\n            JZ4740_GPIO_SIZE) == -1)\n        return (-1);\n    if (dev_jz4740_uart_init (vm, \"JZ4740 UART0\", JZ4740_UART0_BASE,\n            JZ4740_UART0_SIZE, 9, vm->vtty_con1) == -1)\n        return (-1);\n    if (dev_jz4740_uart_init (vm, \"JZ4740 UART1\", JZ4740_UART1_BASE,\n            JZ4740_UART1_SIZE, 8, vm->vtty_con2) == -1)\n        return (-1);\n\n    if (dev_jz4740_cpm_init (vm, \"JZ4740 CPM\", JZ4740_CPM_BASE,\n            JZ4740_CPM_SIZE) == -1)\n        return (-1);\n    if (dev_jz4740_emc_init (vm, \"JZ4740 EMC\", JZ4740_EMC_BASE,\n            JZ4740_EMC_SIZE) == -1)\n        return (-1);\n    if (dev_jz4740_rtc_init (vm, \"JZ4740 RTC\", JZ4740_RTC_BASE,\n            JZ4740_RTC_SIZE) == -1)\n        return (-1);\n    if (dev_jz4740_wdt_tcu_init (vm, \"JZ4740 WDT/TCU\", JZ4740_WDT_TCU_BASE,\n            JZ4740_WDT_TCU_SIZE) == -1)\n        return (-1);\n    if (dev_jz4740_int_init (vm, \"JZ4740 INT\", JZ4740_INT_BASE,\n            JZ4740_INT_SIZE) == -1)\n        return (-1);\n    if (dev_jz4740_dma_init (vm, \"JZ4740 DMA\", JZ4740_DMA_BASE,\n            JZ4740_DMA_SIZE) == -1)\n        return (-1);\n\n    if (pavo->cs8900_enable == 1) {\n        if (pavo_init_cs8900 (pavo, \"CS8900A\", CS8900_IO_BASE, CS8900_SIZE,\n                CS8900_DEFAULT_IRQ) == -1)\n            return (-1);\n    }\n\n    /*LCD*/\n#ifdef SIM_LCD\n        if (dev_jz4740_lcd_init (vm, \"JZ4740 LCD\", JZ4740_LCD_BASE,\n            JZ4740_LCD_SIZE) == -1)\n        return (-1);\n\n#endif\n\n    return (0);\n}\n\nstatic int pavo_boot (pavo_t * pavo)\n{\n    vm_instance_t *vm = pavo->vm;\n\n    if (!vm->boot_cpu)\n        return (-1);\n\n    return jz4740_reset (vm);\n\n}\n\nvoid pavo_clear_irq (vm_instance_t * vm, u_int irq)\n{\n    m_uint32_t irq_mask;\n\n    irq_mask = 1 << irq;\n\n    /*clear ISR and IPR */\n    jz4740_int_table[INTC_ISR / 4] &= ~irq_mask;\n    jz4740_int_table[INTC_IPR / 4] &= ~irq_mask;\n\n}\n\n/*map irq to soc irq*/\nint forced_inline plat_soc_irq (u_int irq)\n{\n    if ((irq >= 48) && (irq <= 175)) {\n        dev_jz4740_gpio_setirq (irq);\n        /*GPIO IRQ */\n        if ((irq >= 48) && (irq <= 79))\n            irq = IRQ_GPIO0;\n        else if ((irq >= 80) && (irq <= 111))\n            irq = IRQ_GPIO1;\n        else if ((irq >= 112) && (irq <= 143))\n            irq = IRQ_GPIO2;\n        else if ((irq >= 144) && (irq <= 175))\n            irq = IRQ_GPIO3;\n    }\n    return irq;\n}\n\nvoid pavo_set_irq (vm_instance_t * vm, u_int irq)\n{\n    m_uint32_t irq_mask;\n\n    irq = plat_soc_irq (irq);\n\n    irq_mask = 1 << irq;\n    jz4740_int_table[INTC_ISR / 4] |= irq_mask;\n    /*first check ICMR. masked interrupt is **invisible** to cpu */\n    if (unlikely (jz4740_int_table[INTC_IMR / 4] & irq_mask)) {\n        /*the irq is masked. clear IPR */\n        jz4740_int_table[INTC_IPR / 4] &= ~irq_mask;\n    } else {\n        /*the irq is not masked */\n\n        /*set IPR */\n        /*\n         * we set IPR, not *or* . yajin\n         *\n         * JZ Kernel 'plat_irq_dispatch' determine which is the highest priority interrupt\n         * and handle.\n         * It uses a function ffs to find first set irq from least bit to highest bit.\n         * 260         irq = ffs(intc_ipr) - 1;\n         *\n         * That means when tcu0 irq and gpio1 irq occurs at the same time ,INTC_IPR=0x8800000\n         * and irq handler will handle tcu0 irq(bit 23) not gpio1 irq(bit 27).\n         *\n         * In pavo gpio1->cs8900 int\n         *\n         * TCU0 irq occurs every 10 ms and gpio1 occurs about 10ms (cs8900 has received a packet\n         * or has txed a packet), jz kernel always handle tcu0 irq. gpio1 irq is hungry. So I just set\n         * jz4740_int_table[INTC_IPR/4]= irq_mask not or(|) irq_mask. TCU0 irq may be lost. However,\n         * gpio1 irq is not so ofen so it is not a big problem.\n         *\n         * In emulator, irq is not a good method for hardware to tell kernel something has happened.\n         * Emulator likes polling more than interrupt :) .\n         *\n         */\n        jz4740_int_table[INTC_IPR / 4] = irq_mask;\n\n        mips_set_irq (vm->boot_cpu, JZ4740_INT_TO_MIPS);\n        mips_update_irq_flag (vm->boot_cpu);\n    }\n}\n\nCOMMON_CONFIG_INFO_ARRAY;\nstatic void printf_configure (pavo_t * pavo)\n{\n\n    vm_instance_t *vm = pavo->vm;\n    PRINT_COMMON_CONFIG_OPTION;\n\n    /*print other configure information here */\n    if (pavo->cs8900_enable == 1) {\n        printf (\"CS8900 net card enabled\\n\");\n        printf (\"CS8900 iotype %s \\n\", pavo->cs8900_iotype);\n    } else\n        printf (\"CS8900 net card disenabled\\n\");\n}\n\nstatic void pavo_parse_configure (pavo_t * pavo)\n{\n    vm_instance_t *vm = pavo->vm;\n    cfg_opt_t opts[] = {\n        COMMON_CONFIG_OPTION\n            /*add other configure information here */\n            CFG_SIMPLE_INT (\"cs8900_enable\", &(pavo->cs8900_enable)),\n        CFG_SIMPLE_STR (\"cs8900_iotype\", &(pavo->cs8900_iotype)),\n        CFG_SIMPLE_INT (\"jit_use\", &(vm->jit_use)),\n\n        CFG_END ()\n    };\n    cfg_t *cfg;\n\n    cfg = cfg_init (opts, 0);\n    cfg_parse (cfg, vm->configure_filename);\n    cfg_free (cfg);\n\n    VALID_COMMON_CONFIG_OPTION;\n\n    /*add other configure information validation here */\n    if (vm->boot_method == BOOT_BINARY) {\n        ASSERT (vm->boot_from == 2,\n            \"boot_from must be 2(NAND Flash)\\n pavo only can boot from NAND Flash.\\n\");\n    }\n    if (vm->flash_size != 0) {\n        ASSERT (vm->flash_size == 4,\n            \"flash_size should be 4.\\n We only support 4MB NOR flash emulation\\n\");\n    }\n    if (pavo->cs8900_enable == 1) {\n        ASSERT (pavo->cs8900_iotype != NULL, \"You must set cs8900_enable \\n\");\n    }\n    if (vm->jit_use == 1) {\n        ASSERT (JIT_SUPPORT == 1,\n            \"You must compile with JIT Support to use jit. \\n\");\n    }\n\n    /*Print the configure information */\n    printf_configure (pavo);\n\n}\n\n/* Clear timer interrupt */\nvoid clear_timer_irq (cpu_mips_t *cpu)\n{\n    mips_clear_irq (cpu, MIPS_TIMER_INTERRUPT);\n    mips_update_irq_flag (cpu);\n}\n\n/* Create a router instance */\nvm_instance_t *create_instance (char *configure_filename)\n{\n    pavo_t *pavo;\n    char *name;\n    if (!(pavo = malloc (sizeof (*pavo)))) {\n        fprintf (stderr, \"ADM5120': Unable to create new instance!\\n\");\n        return NULL;\n    }\n\n    memset (pavo, 0, sizeof (*pavo));\n    name = strdup (\"pavo\");\n\n    if (!(pavo->vm = vm_create (name, VM_TYPE_PAVO))) {\n        fprintf (stderr, \"PAVO : unable to create VM instance!\\n\");\n        goto err_vm;\n    }\n    free (name);\n\n    if (configure_filename != NULL)\n        pavo->vm->configure_filename = strdup (configure_filename);\n    pavo_init_defaults (pavo);\n    pavo_parse_configure (pavo);\n    /*init gdb debug */\n    vm_debug_init (pavo->vm);\n\n    pavo->vm->hw_data = pavo;\n\n    return (pavo->vm);\n\n  err_vm:\n    free (name);\n    free (pavo);\n    return NULL;\n\n}\n\nint init_instance (vm_instance_t * vm)\n{\n    pavo_t *pavo = VM_PAVO (vm);\n\n    if (pavo_init_platform (pavo) == -1) {\n        vm_error (vm, \"unable to initialize the platform hardware.\\n\");\n        return (-1);\n    }\n    /* IRQ routing */\n    vm->set_irq = pavo_set_irq;\n    vm->clear_irq = pavo_clear_irq;\n\n    return (pavo_boot (pavo));\n\n}\n"
  },
  {
    "path": "tools/virtualmips/pavo.conf",
    "content": "#configure file for pavo\n\n# RAM size in kbytes. If not set, default value is 65536.\nram_size = 65536\n\n#1:Binary 2:elf\nboot_method = 1\n\n#1:NOR FLASH 2 NAND FLASH\nboot_from = 2\n\n\nkernel_file_name = \"vmlinux-pavo\"\n\n#1 NOR 2 NAND\nflash_type = 2\nflash_size = 0x400   /*Mbytes*/\n#flash_file_name = \"flash.bin\"  only need for nor flash\n#flash_phy_address = 0x1fc00000  only need for nor flash\n\n\n\ngdb_debug = 0\ngdb_port = 5555\n\n\ncs8900_enable = 1\ncs8900_iotype = \"tap:tap0\"\n\n#JIT. MUST compile with JIT support if you set jit_use=1\n#JIT is only supported on X86_32 host. AMD64 is not supported.\n#jit_use = 1\n"
  },
  {
    "path": "tools/virtualmips/pavo.h",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *     \n  * This file is part of the virtualmips distribution. \n  * See LICENSE file for terms of the license. \n  *\n  */\n\n#ifndef __PAVO_H__\n#define __PAVO_H__\n\n#include \"jz4740.h\"\n#include \"dev_nand_flash_1g.h\"\n\n#ifdef SIM_LCD\n#include \"vp_sdl.h\"\n#endif\n\n#define PAVO_DEFAULT_CONFIG_FILE     \"pavo.conf\"\n#define PAVO_DEFAULT_RAM_SIZE           16\n#define PAVO_DEFAULT_BOOT_METHOD     BOOT_BINARY\n#define PAVO_DEFAULT_KERNEL_FILENAME     \"vmlinux\"\n#define PAVO_ADDR_BUS_MASK   0xffffffff /*32bit phy address */\n\nstruct pavo_system {\n    /* Associated VM instance */\n    vm_instance_t *vm;\n    nand_flash_1g_data_t *nand_flash;\n\n    m_uint32_t cs8900_enable;\n    char *cs8900_iotype;\n\n    /*For LCD */\n//#ifdef SIM_LCD \n//struct DisplayState *ds;\n//#endif\n\n};\n\ntypedef struct pavo_system pavo_t;\n\n#define VM_PAVO(vm) ((pavo_t *)vm->hw_data)\n\nvm_instance_t *create_instance (char *conf);\nint init_instance (vm_instance_t * vm);\n//void  virtual_timer(cpu_mips_t *cpu);\nint pavo_reset (vm_instance_t * vm);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/pic32.c",
    "content": "/*\n * PIC32 emulation.\n *\n * Copyright (C) 2011 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#define _GNU_SOURCE\n#include <string.h>\n#include <assert.h>\n#include <stdlib.h>\n\n#include \"vp_lock.h\"\n#include \"utils.h\"\n#include \"mips.h\"\n#include \"vm.h\"\n#include \"cpu.h\"\n#include \"mips_exec.h\"\n#include \"debug.h\"\n\n#include \"pic32.h\"\n#include \"device.h\"\n#include \"mips_jit.h\"\n\n/*\n * Translate IRQ number to interrupt vector.\n */\nstatic const int irq_to_vector[] = {\n    PIC32_VECT_CT,      /* 0  - Core Timer Interrupt */\n    PIC32_VECT_CS0,     /* 1  - Core Software Interrupt 0 */\n    PIC32_VECT_CS1,     /* 2  - Core Software Interrupt 1 */\n    PIC32_VECT_INT0,    /* 3  - External Interrupt 0 */\n    PIC32_VECT_T1,      /* 4  - Timer1 */\n    PIC32_VECT_IC1,     /* 5  - Input Capture 1 */\n    PIC32_VECT_OC1,     /* 6  - Output Compare 1 */\n    PIC32_VECT_INT1,    /* 7  - External Interrupt 1 */\n    PIC32_VECT_T2,      /* 8  - Timer2 */\n    PIC32_VECT_IC2,     /* 9  - Input Capture 2 */\n    PIC32_VECT_OC2,     /* 10 - Output Compare 2 */\n    PIC32_VECT_INT2,    /* 11 - External Interrupt 2 */\n    PIC32_VECT_T3,      /* 12 - Timer3 */\n    PIC32_VECT_IC3,     /* 13 - Input Capture 3 */\n    PIC32_VECT_OC3,     /* 14 - Output Compare 3 */\n    PIC32_VECT_INT3,    /* 15 - External Interrupt 3 */\n    PIC32_VECT_T4,      /* 16 - Timer4 */\n    PIC32_VECT_IC4,     /* 17 - Input Capture 4 */\n    PIC32_VECT_OC4,     /* 18 - Output Compare 4 */\n    PIC32_VECT_INT4,    /* 19 - External Interrupt 4 */\n    PIC32_VECT_T5,      /* 20 - Timer5 */\n    PIC32_VECT_IC5,     /* 21 - Input Capture 5 */\n    PIC32_VECT_OC5,     /* 22 - Output Compare 5 */\n    PIC32_VECT_SPI1,    /* 23 - SPI1 Fault */\n    PIC32_VECT_SPI1,    /* 24 - SPI1 Transfer Done */\n    PIC32_VECT_SPI1,    /* 25 - SPI1 Receive Done */\n\n    PIC32_VECT_U1     | /* 26 - UART1 Error */\n    PIC32_VECT_SPI3   | /* 26 - SPI3 Fault */\n    PIC32_VECT_I2C3,    /* 26 - I2C3 Bus Collision Event */\n\n    PIC32_VECT_U1     | /* 27 - UART1 Receiver */\n    PIC32_VECT_SPI3   | /* 27 - SPI3 Transfer Done */\n    PIC32_VECT_I2C3,    /* 27 - I2C3 Slave Event */\n\n    PIC32_VECT_U1     | /* 28 - UART1 Transmitter */\n    PIC32_VECT_SPI3   | /* 28 - SPI3 Receive Done */\n    PIC32_VECT_I2C3,    /* 28 - I2C3 Master Event */\n\n    PIC32_VECT_I2C1,    /* 29 - I2C1 Bus Collision Event */\n    PIC32_VECT_I2C1,    /* 30 - I2C1 Slave Event */\n    PIC32_VECT_I2C1,    /* 31 - I2C1 Master Event */\n    PIC32_VECT_CN,      /* 32 - Input Change Interrupt */\n    PIC32_VECT_AD1,     /* 33 - ADC1 Convert Done */\n    PIC32_VECT_PMP,     /* 34 - Parallel Master Port */\n    PIC32_VECT_CMP1,    /* 35 - Comparator Interrupt */\n    PIC32_VECT_CMP2,    /* 36 - Comparator Interrupt */\n\n    PIC32_VECT_U3     | /* 37 - UART3 Error */\n    PIC32_VECT_SPI2   | /* 37 - SPI2 Fault */\n    PIC32_VECT_I2C4,    /* 37 - I2C4 Bus Collision Event */\n\n    PIC32_VECT_U3     | /* 38 - UART3 Receiver */\n    PIC32_VECT_SPI2   | /* 38 - SPI2 Transfer Done */\n    PIC32_VECT_I2C4,    /* 38 - I2C4 Slave Event */\n\n    PIC32_VECT_U3     | /* 39 - UART3 Transmitter */\n    PIC32_VECT_SPI2   | /* 39 - SPI2 Receive Done */\n    PIC32_VECT_I2C4,    /* 39 - I2C4 Master Event */\n\n    PIC32_VECT_U2     | /* 40 - UART2 Error */\n    PIC32_VECT_SPI4   | /* 40 - SPI4 Fault */\n    PIC32_VECT_I2C5,    /* 40 - I2C5 Bus Collision Event */\n\n    PIC32_VECT_U2     | /* 41 - UART2 Receiver */\n    PIC32_VECT_SPI4   | /* 41 - SPI4 Transfer Done */\n    PIC32_VECT_I2C5,    /* 41 - I2C5 Slave Event */\n\n    PIC32_VECT_U2     | /* 42 - UART2 Transmitter */\n    PIC32_VECT_SPI4   | /* 42 - SPI4 Receive Done */\n    PIC32_VECT_I2C5,    /* 42 - I2C5 Master Event */\n\n    PIC32_VECT_I2C2,    /* 43 - I2C2 Bus Collision Event */\n    PIC32_VECT_I2C2,    /* 44 - I2C2 Slave Event */\n    PIC32_VECT_I2C2,    /* 45 - I2C2 Master Event */\n    PIC32_VECT_FSCM,    /* 46 - Fail-Safe Clock Monitor */\n    PIC32_VECT_RTCC,    /* 47 - Real-Time Clock and Calendar */\n    PIC32_VECT_DMA0,    /* 48 - DMA Channel 0 */\n    PIC32_VECT_DMA1,    /* 49 - DMA Channel 1 */\n    PIC32_VECT_DMA2,    /* 50 - DMA Channel 2 */\n    PIC32_VECT_DMA3,    /* 51 - DMA Channel 3 */\n    PIC32_VECT_DMA4,    /* 52 - DMA Channel 4 */\n    PIC32_VECT_DMA5,    /* 53 - DMA Channel 5 */\n    PIC32_VECT_DMA6,    /* 54 - DMA Channel 6 */\n    PIC32_VECT_DMA7,    /* 55 - DMA Channel 7 */\n    PIC32_VECT_FCE,     /* 56 - Flash Control Event */\n    PIC32_VECT_USB,     /* 57 - USB */\n    PIC32_VECT_CAN1,    /* 58 - Control Area Network 1 */\n    PIC32_VECT_CAN2,    /* 59 - Control Area Network 2 */\n    PIC32_VECT_ETH,     /* 60 - Ethernet Interrupt */\n    PIC32_VECT_IC1,     /* 61 - Input Capture 1 Error */\n    PIC32_VECT_IC2,     /* 62 - Input Capture 2 Error */\n    PIC32_VECT_IC3,     /* 63 - Input Capture 3 Error */\n    PIC32_VECT_IC4,     /* 64 - Input Capture 4 Error */\n    PIC32_VECT_IC5,     /* 65 - Input Capture 5 Error */\n    PIC32_VECT_PMP,     /* 66 - Parallel Master Port Error */\n    PIC32_VECT_U4,      /* 67 - UART4 Error */\n    PIC32_VECT_U4,      /* 68 - UART4 Receiver */\n    PIC32_VECT_U4,      /* 69 - UART4 Transmitter */\n    PIC32_VECT_U6,      /* 70 - UART6 Error */\n    PIC32_VECT_U6,      /* 71 - UART6 Receiver */\n    PIC32_VECT_U6,      /* 72 - UART6 Transmitter */\n    PIC32_VECT_U5,      /* 73 - UART5 Error */\n    PIC32_VECT_U5,      /* 74 - UART5 Receiver */\n    PIC32_VECT_U5,      /* 75 - UART5 Transmitter */\n};\n\n/* Initialize the PIC32 Platform (MIPS) */\nstatic int pic32_init_platform (pic32_t *pic32)\n{\n    struct vm_instance *vm = pic32->vm;\n    cpu_mips_t *cpu0;\n    void *(*cpu_run_fn) (void *);\n\n    vm_init_vtty (vm);\n\n    /* Create a CPU group */\n    vm->cpu_group = cpu_group_create (\"System CPU\");\n\n    /* Initialize the virtual MIPS processor */\n    cpu0 = cpu_create (vm, CPU_TYPE_MIPS32, 0);\n    if (! cpu0) {\n        vm_error (vm, \"unable to create CPU0!\\n\");\n        return (-1);\n    }\n    /* Add this CPU to the system CPU group */\n    cpu_group_add (vm->cpu_group, cpu0);\n    vm->boot_cpu = cpu0;\n\n    /* create the CPU thread execution */\n    cpu_run_fn = (void *) mips_exec_run_cpu;\n    if (pthread_create (&cpu0->cpu_thread, NULL, cpu_run_fn, cpu0) != 0) {\n        fprintf (stderr, \"cpu_create: unable to create thread for CPU%u\\n\",\n            0);\n        free (cpu0);\n        return (-1);\n    }\n    /* 32-bit address */\n    cpu0->addr_bus_mask = 0xffffffff;\n\n    /* Initialize RAM */\n    vm_ram_init (vm, 0x00000000ULL);\n\n    /* Initialize two flash areas */\n    if (vm->flash_size != 0)\n        if (dev_pic32_flash_init (vm, \"Program flash\", vm->flash_size,\n                vm->flash_address, vm->flash_filename) == -1)\n            return (-1);\n    if (pic32->boot_flash_size != 0)\n        if (dev_pic32_flash_init (vm, \"Boot flash\", pic32->boot_flash_size,\n                pic32->boot_flash_address, pic32->boot_file_name) == -1)\n            return (-1);\n\n    /* Initialize peripherals */\n    if (dev_pic32_uart_init (vm, \"UART1\", PIC32_U1MODE,\n            PIC32_IRQ_U1E, vm->vtty_con[0]) == -1)\n        return (-1);\n    if (dev_pic32_uart_init (vm, \"UART2\", PIC32_U2MODE,\n            PIC32_IRQ_U2E, vm->vtty_con[1]) == -1)\n        return (-1);\n#if NVTTY >= 3\n    if (dev_pic32_uart_init (vm, \"UART3\", PIC32_U3MODE,\n            PIC32_IRQ_U3E, vm->vtty_con[2]) == -1)\n        return (-1);\n#endif\n#if NVTTY >= 4\n    if (dev_pic32_uart_init (vm, \"UART4\", PIC32_U4MODE,\n            PIC32_IRQ_U4E, vm->vtty_con[3]) == -1)\n        return (-1);\n#endif\n#if NVTTY >= 5\n    if (dev_pic32_uart_init (vm, \"UART5\", PIC32_U5MODE,\n            PIC32_IRQ_U5E, vm->vtty_con[4]) == -1)\n        return (-1);\n#endif\n#if NVTTY >= 6\n    if (dev_pic32_uart_init (vm, \"UART6\", PIC32_U6MODE,\n            PIC32_IRQ_U6E, vm->vtty_con[5]) == -1)\n        return (-1);\n#endif\n    if (dev_pic32_intcon_init (vm, \"INTCON\", PIC32_INTCON) == -1)\n        return (-1);\n    if (dev_pic32_dmacon_init (vm, \"DMACON\", PIC32_DMACON) == -1)\n        return (-1);\n    if (dev_pic32_syscon_init (vm, \"SYSCON\", PIC32_OSCCON) == -1)\n        return (-1);\n    if (dev_pic32_adc_init (vm, \"ADC\", PIC32_AD1CON1) == -1)\n        return (-1);\n    if (dev_pic32_prefetch_init (vm, \"Prefetch\", PIC32_CHECON) == -1)\n        return (-1);\n    if (dev_pic32_bmxcon_init (vm, \"BMX\", PIC32_BMXCON) == -1)\n        return (-1);\n    if (dev_pic32_rtcc_init (vm, \"RTCC\", PIC32_RTCCON) == -1)\n        return (-1);\n    if (dev_pic32_gpio_init (vm, \"GPIO\", PIC32_TRISA) == -1)\n        return (-1);\n    if (dev_pic32_spi_init (vm, \"SPI1\", PIC32_SPI1CON,\n            PIC32_IRQ_SPI1E) == -1)\n        return (-1);\n    if (dev_pic32_spi_init (vm, \"SPI2\", PIC32_SPI2CON,\n            PIC32_IRQ_SPI2E) == -1)\n        return (-1);\n    if (dev_pic32_spi_init (vm, \"SPI3\", PIC32_SPI3CON,\n            PIC32_IRQ_SPI3E) == -1)\n        return (-1);\n    if (dev_pic32_spi_init (vm, \"SPI4\", PIC32_SPI4CON,\n            PIC32_IRQ_SPI4E) == -1)\n        return (-1);\n    pic32->timer1 = dev_pic32_timer_init (vm, \"Timer1\", PIC32_T1CON, PIC32_IRQ_T1);\n    pic32->timer2 = dev_pic32_timer_init (vm, \"Timer2\", PIC32_T2CON, PIC32_IRQ_T2);\n    pic32->timer3 = dev_pic32_timer_init (vm, \"Timer3\", PIC32_T3CON, PIC32_IRQ_T3);\n    pic32->timer4 = dev_pic32_timer_init (vm, \"Timer4\", PIC32_T4CON, PIC32_IRQ_T4);\n    pic32->timer5 = dev_pic32_timer_init (vm, \"Timer5\", PIC32_T5CON, PIC32_IRQ_T5);\n    if (! pic32->timer1 || ! pic32->timer2 || ! pic32->timer3 ||\n        ! pic32->timer4 || ! pic32->timer5)\n        return (-1);\n    if (dev_sdcard_init (&pic32->sdcard[0], \"SD0\", pic32->sdcard0_size,\n            pic32->sdcard0_file_name) < 0)\n        return (-1);\n    if (dev_sdcard_init (&pic32->sdcard[1], \"SD1\", pic32->sdcard1_size,\n            pic32->sdcard1_file_name) < 0)\n        return (-1);\n    if (dev_swap_init (&pic32->swap, \"Swap\") < 0)\n        return (-1);\n\n    /* Initialize DEVCFG area */\n    if (dev_pic32_devcfg_init (vm, \"DEVCFG\", 0x1fc02f00) < 0)\n        return (-1);\n\n    pic32->sdcard[1].unit = 1;\n    return (0);\n}\n\n/*\n * Find pending interrupt with the biggest priority.\n * Setup INTSTAT and cause registers.\n * Update irq_pending flag for CPU.\n */\nvoid pic32_update_irq_flag (pic32_t *pic32)\n{\n    cpu_mips_t *cpu = pic32->vm->boot_cpu;\n    int vector, level, irq, n, v;\n\n    /* Assume no interrupts pending. */\n    cpu->irq_cause = 0;\n    cpu->irq_pending = 0;\n    pic32->intstat = 0;\n\n    if ((pic32->ifs[0] & pic32->iec[0]) ||\n        (pic32->ifs[1] & pic32->iec[1]) ||\n        (pic32->ifs[2] & pic32->iec[2]))\n    {\n        /* Find the most prioritive pending interrupt,\n         * it's vector and level. */\n        vector = 0;\n        level = 0;\n        for (irq=0; irq<sizeof(irq_to_vector)/sizeof(int); irq++) {\n            n = irq >> 5;\n            if ((pic32->ifs[n] & pic32->iec[n]) >> (irq & 31) & 1) {\n                /* Interrupt is pending. */\n                v = irq_to_vector [irq];\n                if (v < 0)\n                    continue;\n                if (pic32->ivprio[v] > level) {\n                    vector = v;\n                    level = pic32->ivprio[v];\n                }\n            }\n        }\n        pic32->intstat = vector | (level << 8);\n\n        cpu->irq_cause = level << 10;\n/*printf (\"-- vector = %d, level = %d\\n\", vector, level);*/\n    }\n/*else printf (\"-- no irq pending\\n\");*/\n\n    mips_update_irq_flag (cpu);\n}\n\nvoid pic32_clear_irq (vm_instance_t *vm, u_int irq)\n{\n    pic32_t *pic32 = (pic32_t*) vm->hw_data;\n\n    /* Clear interrupt flag status */\n    pic32->ifs [irq >> 5] &= ~(1 << (irq & 31));\n\n    pic32_update_irq_flag (pic32);\n}\n\nvoid pic32_set_irq (vm_instance_t *vm, u_int irq)\n{\n    pic32_t *pic32 = (pic32_t*) vm->hw_data;\n\n    /* Set interrupt flag status */\n    pic32->ifs [irq >> 5] |= 1 << (irq & 31);\n\n    pic32_update_irq_flag (pic32);\n}\n\n/*\n * Activate core timer interrupt\n */\nvoid set_timer_irq (cpu_mips_t *cpu)\n{\n    pic32_set_irq (cpu->vm, PIC32_VECT_CT);\n}\n\n/*\n * Clear core timer interrupt\n */\nvoid clear_timer_irq (cpu_mips_t *cpu)\n{\n    pic32_clear_irq (cpu->vm, PIC32_VECT_CT);\n}\n\n/*\n * Increment timers.\n */\nvoid host_alarm (cpu_mips_t *cpu, int nclocks)\n{\n    pic32_t *pic32 = (pic32_t*) cpu->vm->hw_data;\n\n    dev_pic32_timer_tick (cpu, pic32->timer1, nclocks);\n    dev_pic32_timer_tick (cpu, pic32->timer2, nclocks);\n    dev_pic32_timer_tick (cpu, pic32->timer3, nclocks);\n    dev_pic32_timer_tick (cpu, pic32->timer4, nclocks);\n    dev_pic32_timer_tick (cpu, pic32->timer5, nclocks);\n}\n\n/*\n * Configuration information.\n */\nstatic char *boot_method_string[2] = {\"Binary\", \"ELF\"};\nstatic char *boot_from_string[2] = {\"NOR FLASH\", \"NAND FLASH\"};\nstatic char *flash_type_string[2] = {\"NOR FLASH\", \"NAND FLASH\"};\n\nstatic char *start_address = 0;\nstatic char *trace_address = 0;\nstatic char *uart_type[NVTTY] = {0};\nstatic char *uart_port[NVTTY] = {0};\n\nstatic void configure_parameter (void *arg, char *section, char *param, char *value)\n{\n    pic32_t *pic32 = arg;\n    vm_instance_t *vm = pic32->vm;\n\n    if (strcmp (param, \"ram_size\") == 0)\n        vm->ram_size = strtoul (value, 0, 0);\n    else if (strcmp (param, \"gdb_debug\") == 0)\n        vm->gdb_debug = strtoul (value, 0, 0);\n    else if (strcmp (param, \"gdb_port\") == 0)\n        vm->gdb_port = strtoul (value, 0, 0);\n    else if (strcmp (param, \"flash_size\") == 0)\n        vm->flash_size = strtoul (value, 0, 0);\n    else if (strcmp (param, \"flash_type\") == 0)\n        vm->flash_type = strtoul (value, 0, 0);\n    else if (strcmp (param, \"flash_file_name\") == 0)\n        vm->flash_filename = strdup (value);\n    else if (strcmp (param, \"flash_phy_address\") == 0)\n        vm->flash_address = strtoul (value, 0, 0);\n    else if (strcmp (param, \"boot_method\") == 0)\n        vm->boot_method = strtoul (value, 0, 0);\n    else if (strcmp (param, \"boot_from\") == 0)\n        vm->boot_from = strtoul (value, 0, 0);\n    else if (strcmp (param, \"kernel_file_name\") == 0)\n        vm->kernel_filename = strdup (value);\n    else if (strcmp (param, \"jit_use\") == 0)\n        vm->jit_use = strtoul (value, 0, 0);\n    else if (strcmp (param, \"debug_level\") == 0)\n        vm->debug_level = strtoul (value, 0, 0);\n    else if (strcmp (param, \"boot_flash_size\") == 0)\n        pic32->boot_flash_size = strtoul (value, 0, 0);\n    else if (strcmp (param, \"boot_flash_address\")== 0)\n        pic32->boot_flash_address = strtoul (value, 0, 0);\n    else if (strcmp (param, \"boot_file_name\") == 0)\n        pic32->boot_file_name = strdup (value);\n    else if (strcmp (param, \"start_address\") == 0)\n        start_address = strdup (value);\n    else if (strcmp (param, \"trace_address\") == 0)\n        trace_address = strdup (value);\n    else if (strcmp (param, \"sdcard_port\") == 0)\n        pic32->sdcard_port = strtoul (value, 0, 0);\n    else if (strcmp (param, \"sdcard0_size\") == 0)\n        pic32->sdcard0_size = strtoul (value, 0, 0);\n    else if (strcmp (param, \"sdcard1_size\") == 0)\n        pic32->sdcard1_size = strtoul (value, 0, 0);\n    else if (strcmp (param, \"sdcard0_file_name\") == 0)\n        pic32->sdcard0_file_name = strdup (value);\n    else if (strcmp (param, \"sdcard1_file_name\") == 0)\n        pic32->sdcard1_file_name = strdup (value);\n    else if (strcmp (param, \"uart1_type\") == 0)\n        uart_type[0] = strdup (value);\n    else if (strcmp (param, \"uart2_type\") == 0)\n        uart_type[1] = strdup (value);\n    else if (strcmp (param, \"uart3_type\") == 0)\n        uart_type[2] = strdup (value);\n    else if (strcmp (param, \"uart4_type\") == 0)\n        uart_type[3] = strdup (value);\n    else if (strcmp (param, \"uart5_type\") == 0)\n        uart_type[4] = strdup (value);\n    else if (strcmp (param, \"uart6_type\") == 0)\n        uart_type[5] = strdup (value);\n    else if (strcmp (param, \"uart1_port\") == 0)\n        uart_port[0] = strdup (value);\n    else if (strcmp (param, \"uart2_port\") == 0)\n        uart_port[1] = strdup (value);\n    else if (strcmp (param, \"uart3_port\") == 0)\n        uart_port[2] = strdup (value);\n    else if (strcmp (param, \"uart4_port\") == 0)\n        uart_port[3] = strdup (value);\n    else if (strcmp (param, \"uart5_port\") == 0)\n        uart_port[4] = strdup (value);\n    else if (strcmp (param, \"uart6_port\") == 0)\n        uart_port[5] = strdup (value);\n    else {\n        fprintf (stderr, \"%s: unknown parameter `%s'\\n\", vm->configure_filename, param);\n        exit (-1);\n    }\n    //printf (\"Configure: %s = '%s'\\n\", param, value);\n}\n\nstatic void pic32_parse_configure (pic32_t *pic32)\n{\n    vm_instance_t *vm = pic32->vm;\n    int i;\n\n    conf_parse (vm->configure_filename, configure_parameter, pic32);\n    if (start_address)\n        pic32->start_address = strtoul (start_address, 0, 0);\n    if (trace_address)\n        vm->trace_address = strtoul (trace_address, 0, 0);\n    for (i=0; i<NVTTY; i++)\n        if (uart_type[i]) {\n            if (strcmp (uart_type[i], \"console\") == 0)\n                vm->vtty_type[i] = VTTY_TYPE_TERM;\n            else if (strcmp (uart_type[i], \"tcp\") == 0)\n                vm->vtty_type[i] = VTTY_TYPE_TCP;\n            else if (strcmp (uart_type[i], \"none\") == 0)\n                vm->vtty_type[i] = VTTY_TYPE_NONE;\n            else {\n                printf (\"Unknown option: uart%d_type = %s\\n\",\n                    i+1, uart_type[i]);\n                continue;\n            }\n            if (uart_port[i]) {\n                vm->vtty_tcp_port[i] = strtoul (uart_port[i], 0, 0);\n            } else if (vm->vtty_type[i] == VTTY_TYPE_TCP) {\n                vm->vtty_tcp_port[i] = 2300 + i;\n            }\n        }\n\n    ASSERT(vm->ram_size != 0, \"ram_size can not be 0\\n\");\n    if (vm->flash_type == FLASH_TYPE_NOR_FLASH) {\n        if (vm->flash_size != 0) {\n            /*ASSERT(vm->flash_filename!=NULL, \"flash_file_name can not be NULL\\n\");*/\n            /* flash_filename can be null. virtualmips will create it. */\n            ASSERT(vm->flash_address != 0, \"flash_address can not be 0\\n\");\n        }\n    } else if (vm->flash_type == FLASH_TYPE_NAND_FLASH) {\n        ASSERT(vm->flash_size == 0x400, \"flash_size should be 0x400.\\n We only support 1G byte NAND flash emulation\\n\");\n        assert(1);\n    } else\n        ASSERT(0, \"error flash_type. valid value: 1:NOR FLASH 2:NAND FLASH\\n\");\n\n    ASSERT(vm->boot_method != 0, \"boot_method can not be 0\\n 1:binary  2:elf \\n\");\n\n    if (vm->boot_method == BOOT_BINARY) {\n        /* boot from binary image */\n        ASSERT(vm->boot_from != 0, \"boot_from can not be 0\\n 1:NOR FLASH 2:NAND FLASH\\n\");\n        if (vm->boot_from==BOOT_FROM_NOR_FLASH) {\n            ASSERT(vm->flash_type == FLASH_TYPE_NOR_FLASH, \"flash_type must be 1(NOR FLASH)\\n\");\n            ASSERT(vm->flash_size != 0, \"flash_size can not be 0\\n\");\n            ASSERT(vm->flash_filename != NULL, \"flash_filename can not be NULL\\n\");\n            ASSERT(vm->flash_address != 0, \"flash_address can not be 0\\n\");\n        } else if (vm->boot_from == BOOT_FROM_NAND_FLASH) {\n            ASSERT(vm->flash_type == FLASH_TYPE_NAND_FLASH, \"flash_type must be 2(NAND FLASH)\\n\");\n            ASSERT(vm->flash_size != 0, \"flash_size can not be 0\\n\");\n            /*ASSERT(vm->flash_filename!=NULL,\"flash_filename can not be NULL\\n\");*/\n        } else\n            ASSERT(0, \"error boot_from. valid value: 1:NOR FLASH 2:NAND FLASH\\n\");\n    } else if (vm->boot_method == BOOT_ELF) {\n        ASSERT(vm->kernel_filename!=0,\"kernel_file_name can not be NULL\\n \");\n    } else\n        ASSERT(0, \"error boot_method. valid value: 1:binary  2:elf \\n\");\n\n    /* Add other configure information validation here */\n    if (vm->jit_use) {\n        ASSERT (JIT_SUPPORT == 1,\n            \"You must compile with JIT Support to use jit.\\n\");\n    }\n\n    /* Print the configure information */\n    printf(\"Using configure file: %s\\n\", vm->configure_filename);\n    printf(\"ram_size: %dk bytes \\n\", vm->ram_size);\n    printf(\"boot_method: %s \\n\", boot_method_string[vm->boot_method-1]);\n    if (vm->flash_size != 0) {\n        printf(\"flash_type: %s \\n\",flash_type_string[vm->flash_type-1]);\n    \tprintf(\"flash_size: %dk bytes \\n\",vm->flash_size);\n    \tif (vm->flash_type == FLASH_TYPE_NOR_FLASH) {\n    \t  printf(\"flash_file_name: %s \\n\",vm->flash_filename);\n    \t  printf(\"flash_phy_address: 0x%x \\n\",vm->flash_address);\n    \t}\n    }\n    if (vm->boot_method == BOOT_BINARY) {\n    \tprintf(\"boot_from: %s \\n\",boot_from_string[vm->boot_from-1]);\n    }\n    if (vm->boot_method == BOOT_ELF) {\n    \tprintf(\"kernel_file_name: %s \\n\",vm->kernel_filename);\n    }\n\n    if (vm->gdb_debug != 0) {\n    \tprintf(\"GDB debug enable\\n\");\n    \tprintf(\"GDB port: %d \\n\",vm->gdb_port);\n    }\n\n    /* print other configure information here */\n    if (pic32->boot_flash_size > 0) {\n        printf (\"boot_flash_size: %dk bytes\\n\", pic32->boot_flash_size);\n        printf (\"boot_flash_address: 0x%x\\n\", pic32->boot_flash_address);\n        printf (\"boot_file_name: %s\\n\", pic32->boot_file_name);\n    }\n    if (pic32->sdcard_port) {\n        printf (\"sdcard_port: SPI%d\\n\", pic32->sdcard_port);\n    }\n    if (pic32->sdcard0_size > 0) {\n        printf (\"sdcard0_size: %dM bytes\\n\", pic32->sdcard0_size);\n        printf (\"sdcard0_file_name: %s\\n\", pic32->sdcard0_file_name);\n    }\n    if (pic32->sdcard1_size > 0) {\n        printf (\"sdcard1_size: %dM bytes\\n\", pic32->sdcard1_size);\n        printf (\"sdcard1_file_name: %s\\n\", pic32->sdcard1_file_name);\n    }\n\n    printf (\"start_address: 0x%x\\n\", pic32->start_address);\n    if (vm->trace_address != 0)\n        printf (\"trace_address: 0x%x\\n\", vm->trace_address);\n    for (i=0; i<NVTTY; i++) {\n        if (vm->vtty_type[i] != VTTY_TYPE_NONE)\n            printf (\"uart%d_type = %s\\n\", i+1,\n                vm->vtty_type[i] == VTTY_TYPE_TERM ? \"console\" :\n                vm->vtty_type[i] == VTTY_TYPE_TCP  ? \"tcp\" : \"???\");\n        if (vm->vtty_tcp_port[i])\n            printf (\"uart%d_type = %u\\n\", i+1,\n                vm->vtty_tcp_port[i]);\n    }\n}\n\n/*\n * Create an instance of virtual machine.\n */\nvm_instance_t *create_instance (char *configure_filename)\n{\n    vm_instance_t *vm;\n    pic32_t *pic32;\n    const char *name = \"pic32\";\n    int i;\n\n    pic32 = malloc (sizeof (*pic32));\n    if (! pic32) {\n        fprintf (stderr, \"PIC32: unable to create new instance!\\n\");\n        return NULL;\n    }\n    memset (pic32, 0, sizeof (*pic32));\n\n    vm = vm_create (name, VM_TYPE_PIC32);\n    if (! vm) {\n        fprintf (stderr, \"PIC32: unable to create VM instance!\\n\");\n        free (pic32);\n        return NULL;\n    }\n    vm->hw_data = pic32;\n    pic32->vm = vm;\n    vm->vtty_type[0] = VTTY_TYPE_TERM;\n    for (i=1; i<NVTTY; i++)\n        vm->vtty_type[i] = VTTY_TYPE_NONE;\n\n    /* Initialize default parameters for  pic32 */\n    if (configure_filename == NULL)\n#ifdef UBW32\n        configure_filename = \"pic32_ubw32.conf\";\n#elif defined EXPLORER16\n        configure_filename = \"pic32_explorer16.conf\";\n#elif defined MAXIMITE\n        configure_filename = \"pic32_maximite.conf\";\n#elif defined MAX32\n        configure_filename = \"pic32_max32.conf\";\n#endif\n    vm->configure_filename = strdup (configure_filename);\n    vm->ram_size = 128;         /* kilobytes */\n    vm->boot_method = BOOT_BINARY;\n    vm->boot_from = BOOT_FROM_NOR_FLASH;\n    vm->flash_type = FLASH_TYPE_NOR_FLASH;\n\n    pic32_parse_configure (pic32);\n\n    /* init gdb debug */\n    vm_debug_init (pic32->vm);\n\n    return pic32->vm;\n}\n\nint init_instance (vm_instance_t * vm)\n{\n    pic32_t *pic32 = (pic32_t *) vm->hw_data;\n    cpu_mips_t *cpu;\n\n    if (pic32_init_platform (pic32) == -1) {\n        vm_error (vm, \"unable to initialize the platform hardware.\\n\");\n        return (-1);\n    }\n    if (! vm->boot_cpu) {\n        vm_error (vm, \"unable to boot cpu.\\n\");\n        return (-1);\n    }\n\n    /* IRQ routing */\n    vm->set_irq = pic32_set_irq;\n    vm->clear_irq = pic32_clear_irq;\n\n    vm_suspend (vm);\n\n    /* Check that CPU activity is really suspended */\n    if (cpu_group_sync_state (vm->cpu_group) == -1) {\n        vm_error (vm, \"unable to sync with system CPUs.\\n\");\n        return (-1);\n    }\n\n    /* Reset the boot CPU */\n    cpu = vm->boot_cpu;\n    mips_reset (cpu);\n\n    /* Set config0-config3 registers. */\n    cpu->cp0.config_usable = 0x0f;\n    cpu->cp0.config_reg[0] = 0xa4010582;\n    cpu->cp0.config_reg[1] = 0x80000004;\n    cpu->cp0.config_reg[2] = 0x80000000;\n    cpu->cp0.config_reg[3] = 0x00000060;\n\n    /* set PC and PRID */\n    cpu->cp0.reg[MIPS_CP0_PRID] = 0x00ff8700;   /* TODO */\n    cpu->cp0.tlb_entries = 0;\n    cpu->pc = pic32->start_address;\n\n    /* reset all devices */\n    dev_reset_all (vm);\n    dev_sdcard_reset (cpu);\n\n#ifdef _USE_JIT_\n    /* if jit is used. flush all jit buffer */\n    if (vm->jit_use)\n        mips_jit_flush (cpu, 0);\n#endif\n\n    /* Launch the simulation */\n    printf (\"--- Start simulation: PC=0x%\" LL \"x, JIT %sabled\\n\",\n            cpu->pc, vm->jit_use ? \"en\" : \"dis\");\n    vm->status = VM_STATUS_RUNNING;\n    cpu_start (vm->boot_cpu);\n    return (0);\n}\n"
  },
  {
    "path": "tools/virtualmips/pic32.h",
    "content": "/*\n * Copyright (C) 2011 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#ifndef __PIC32_H__\n#define __PIC32_H__\n\n#include \"types.h\"\n#include \"pic32mx.h\"\n#include \"dev_sdcard.h\"\n#include \"dev_swap.h\"\n\n#define DATA_WIDTH          32          /* MIPS32 architecture */\n#define LL                              /* empty - printf format for machine word */\n\n/*\n * Data types\n */\ntypedef m_uint32_t m_va_t;\ntypedef m_uint32_t m_pa_t;\ntypedef m_uint32_t m_reg_t;\ntypedef m_int32_t m_ireg_t;\ntypedef m_uint32_t m_cp0_reg_t;\n\n/*Guest endian*/\n#define GUEST_BYTE_ORDER  ARCH_LITTLE_ENDIAN\n\n/* Host to VM conversion functions */\n#if HOST_BYTE_ORDER == GUEST_BYTE_ORDER\n#define htovm16(x) (x)\n#define htovm32(x) (x)\n#define htovm64(x) (x)\n\n#define vmtoh16(x) (x)\n#define vmtoh32(x) (x)\n#define vmtoh64(x) (x)\n#else //host:big guest:little\n\n#define htovm16(x) (ntohs(x))\n#define htovm32(x) (ntohl(x))\n#define htovm64(x) (swap64(x))\n\n#define vmtoh16(x) (htons(x))\n#define vmtoh32(x) (htonl(x))\n#define vmtoh64(x) (swap64(x))\n#endif\n\nstruct pic32_system {\n    /* Associated VM instance */\n    vm_instance_t *vm;\n\n    unsigned start_address;         /* jump here on reset */\n    unsigned boot_flash_size;       /* size of boot flash in kbytes */\n    unsigned boot_flash_address;    /* physical address of boot flash */\n    char *boot_file_name;           /* image of boot flash */\n\n    unsigned sdcard_port;           /* SPI port number */\n    unsigned sdcard0_size;          /* size of SD card 0 in Mbytes */\n    unsigned sdcard1_size;          /* size of SD card 1 in Mbytes */\n    char *sdcard0_file_name;        /* image of SD card 0 */\n    char *sdcard1_file_name;        /* image of SD card 1 */\n    sdcard_t sdcard [2];            /* max number of sdcards */\n\n    swap_t swap;                    /* swap device */\n\n    struct vdevice *intdev;         /* interrupt controller */\n    unsigned intcon;                /* interrupt control */\n    unsigned intstat;               /* interrupt status */\n    unsigned iptmr;                 /* temporal proximity */\n    unsigned ifs[3];                /* interrupt flag status */\n    unsigned iec[3];                /* interrupt enable control */\n    unsigned ipc[12];               /* interrupt priority control */\n    unsigned ivprio[64];            /* priority of interrupt vectors */\n\n    struct vdevice *timer1;         /* timer 1 */\n    struct vdevice *timer2;         /* timer 2 */\n    struct vdevice *timer3;         /* timer 3 */\n    struct vdevice *timer4;         /* timer 4 */\n    struct vdevice *timer5;         /* timer 5 */\n\n    struct vdevice *bmxdev;         /* memory controller */\n    unsigned bmxcon;                /* memory control */\n    unsigned bmx_ram_kpba;          /* RAM kernel program base address */\n    unsigned bmx_ram_udba;          /* RAM user data base address */\n    unsigned bmx_ram_upba;          /* RAM user program base address */\n    unsigned bmx_flash_upba;        /* Flash user program base address */\n\n    struct vdevice *rtcdev;         /* RTCC controller */\n    unsigned rtccon;                /* RTC control */\n\n    struct vdevice *dmadev;         /* DMA controller */\n    unsigned dmacon;                /* DMA control */\n    unsigned dmastat;               /* DMA status */\n    unsigned dmaaddr;               /* DMA address */\n\n    struct vdevice *sysdev;         /* System controller */\n    unsigned osccon;\n    unsigned osctun;\n    unsigned ddpcon;                /* Debug data port control */\n    unsigned devid;                 /* Device identifier */\n    unsigned syskey;\n    unsigned rcon;\n    unsigned rswrst;\n\n    unsigned ad1con1;               /* Analog to digital converter */\n    unsigned ad1con2;\n    unsigned ad1con3;\n    unsigned ad1chs;\n    unsigned ad1cssl;\n    unsigned ad1pcfg;\n\n    struct vdevice *cfgdev;         /* Device configuration */\n    unsigned devcfg3;\n    unsigned devcfg2;\n    unsigned devcfg1;\n    unsigned devcfg0;\n\n    struct vdevice *prefetch;       /* Prefetch cache controller */\n    unsigned checon;\n};\n\ntypedef struct pic32_system pic32_t;\nstruct virtual_tty;\n\nvm_instance_t *create_instance (char *conf);\nint init_instance (vm_instance_t *vm);\nint pic32_reset (vm_instance_t *vm);\nvoid pic32_update_irq_flag (pic32_t *pic32);\nvoid pic32_set_irq (vm_instance_t *vm, unsigned irq);\nvoid pic32_clear_irq (vm_instance_t *vm, unsigned irq);\nint dev_pic32_flash_init (vm_instance_t *vm, char *name,\n    unsigned flash_kbytes, unsigned flash_address, char *filename);\nint dev_pic32_uart_init (vm_instance_t *vm, char *name, unsigned paddr,\n    unsigned irq, struct virtual_tty *vtty);\nint dev_pic32_intcon_init (vm_instance_t *vm, char *name, unsigned paddr);\nint dev_pic32_dmacon_init (vm_instance_t *vm, char *name, unsigned paddr);\nint dev_pic32_syscon_init (vm_instance_t *vm, char *name, unsigned paddr);\nint dev_pic32_adc_init (vm_instance_t *vm, char *name, unsigned paddr);\nint dev_pic32_prefetch_init (vm_instance_t *vm, char *name, unsigned paddr);\nint dev_pic32_bmxcon_init (vm_instance_t *vm, char *name, unsigned paddr);\nint dev_pic32_rtcc_init (vm_instance_t *vm, char *name, unsigned paddr);\nint dev_pic32_spi_init (vm_instance_t *vm, char *name, unsigned paddr,\n    unsigned irq);\nstruct vdevice *dev_pic32_timer_init (vm_instance_t *vm, char *name,\n    unsigned paddr, unsigned irq);\nint dev_pic32_gpio_init (vm_instance_t *vm, char *name, unsigned paddr);\nint dev_pic32_devcfg_init (vm_instance_t *vm, char *name, unsigned paddr);\nvoid dev_pic32_timer_tick (cpu_mips_t *cpu, struct vdevice *dev, unsigned nclocks);\nvoid dumpregs (cpu_mips_t *cpu);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/pic32_dev_adc.c",
    "content": "/*\n * System controller for PIC32.\n *\n * Copyright (C) 2011 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"cpu.h\"\n#include \"pic32.h\"\n\n#define ADC_REG_SIZE     0x170\n\nextern cpu_mips_t *current_cpu;\n\n/*\n * Perform an assign/clear/set/invert operation.\n */\nstatic inline unsigned write_op (int a, int b, int op)\n{\n    switch (op & 0xc) {\n    case 0x0:           /* Assign */\n        a = b;\n        break;\n    case 0x4:           /* Clear */\n        a &= ~b;\n        break;\n    case 0x8:           /* Set */\n        a |= b;\n        break;\n    case 0xc:           /* Invert */\n        a ^= b;\n        break;\n    }\n    return a;\n}\n\nvoid *dev_pic32_adc_access (cpu_mips_t *cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t *data,\n    m_uint8_t *has_set_value)\n{\n    pic32_t *pic32 = dev->priv_data;\n\n    if (offset >= ADC_REG_SIZE) {\n        *data = 0;\n        return NULL;\n    }\n    if (op_type == MTS_READ)\n        *data = 0;\n    switch (offset & 0xff0) {\n    case PIC32_AD1CON1 & 0xff0:         /* Control register 1 */\n        if (op_type == MTS_READ) {\n            *data = pic32->ad1con1;\n        } else {\n            pic32->ad1con1 = write_op (pic32->ad1con1, *data, offset);\n        }\n        break;\n\n    case PIC32_AD1CON2 & 0xff0:         /* Control register 2 */\n        if (op_type == MTS_READ) {\n            *data = pic32->ad1con2;\n        } else {\n            pic32->ad1con2 = write_op (pic32->ad1con2, *data, offset);\n        }\n        break;\n\n    case PIC32_AD1CON3 & 0xff0:         /* Control register 3 */\n        if (op_type == MTS_READ) {\n            *data = pic32->ad1con3;\n        } else {\n            pic32->ad1con3 = write_op (pic32->ad1con3, *data, offset);\n        }\n        break;\n\n    case PIC32_AD1CHS & 0xff0:          /* Channel select */\n        if (op_type == MTS_READ) {\n            *data = pic32->ad1chs;\n        } else {\n            pic32->ad1chs = write_op (pic32->ad1chs, *data, offset);\n        }\n        break;\n\n    case PIC32_AD1CSSL & 0xff0:         /* Input scan selection */\n        if (op_type == MTS_READ) {\n            *data = pic32->ad1cssl;\n        } else {\n            pic32->ad1cssl = write_op (pic32->ad1cssl, *data, offset);\n        }\n        break;\n\n    case PIC32_AD1PCFG & 0xff0:         /* Port configuration */\n        if (op_type == MTS_READ) {\n            *data = pic32->ad1pcfg;\n        } else {\n            pic32->ad1pcfg = write_op (pic32->ad1pcfg, *data, offset);\n        }\n        break;\n\n    case PIC32_ADC1BUF0 & 0xff0: case PIC32_ADC1BUF1 & 0xff0:\n    case PIC32_ADC1BUF2 & 0xff0: case PIC32_ADC1BUF3 & 0xff0:\n    case PIC32_ADC1BUF4 & 0xff0: case PIC32_ADC1BUF5 & 0xff0:\n    case PIC32_ADC1BUF6 & 0xff0: case PIC32_ADC1BUF7 & 0xff0:\n    case PIC32_ADC1BUF8 & 0xff0: case PIC32_ADC1BUF9 & 0xff0:\n    case PIC32_ADC1BUFA & 0xff0: case PIC32_ADC1BUFB & 0xff0:\n    case PIC32_ADC1BUFC & 0xff0: case PIC32_ADC1BUFD & 0xff0:\n    case PIC32_ADC1BUFE & 0xff0: case PIC32_ADC1BUFF & 0xff0:\n        if (op_type == MTS_READ) {      /* Result words */\n            *data = 0; // TODO\n        }\n        break;\n\n    default:\n        ASSERT (0, \"unknown adc offset %x\\n\", offset);\n    }\n    *has_set_value = TRUE;\n    return NULL;\n}\n\nvoid dev_pic32_adc_reset (cpu_mips_t *cpu, struct vdevice *dev)\n{\n    pic32_t *pic32 = dev->priv_data;\n\n    pic32->ad1con1 = 0;\n    pic32->ad1con2 = 0;\n    pic32->ad1con3 = 0;\n    pic32->ad1chs = 0;\n    pic32->ad1cssl = 0;\n    pic32->ad1pcfg = 0;\n}\n\nint dev_pic32_adc_init (vm_instance_t *vm, char *name, unsigned paddr)\n{\n    pic32_t *pic32 = (pic32_t *) vm->hw_data;\n\n    pic32->sysdev = dev_create (name);\n    if (! pic32->sysdev)\n        return (-1);\n    pic32->sysdev->priv_data = pic32;\n    pic32->sysdev->phys_addr = paddr;\n    pic32->sysdev->phys_len = ADC_REG_SIZE;\n    pic32->sysdev->handler = dev_pic32_adc_access;\n    pic32->sysdev->reset_handler = dev_pic32_adc_reset;\n    pic32->sysdev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n\n    vm_bind_device (vm, pic32->sysdev);\n    return (0);\n}\n"
  },
  {
    "path": "tools/virtualmips/pic32_dev_bmxcon.c",
    "content": "/*\n * Interrupt controller for PIC32.\n *\n * Copyright (C) 2011 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"cpu.h\"\n#include \"pic32.h\"\n\n#define BMXCON_REG_SIZE     0x80\n\nextern cpu_mips_t *current_cpu;\n\n/*\n * Perform an assign/clear/set/invert operation.\n */\nstatic inline unsigned write_op (int a, int b, int op)\n{\n    switch (op & 0xc) {\n    case 0x0:           /* Assign */\n        a = b;\n        break;\n    case 0x4:           /* Clear */\n        a &= ~b;\n        break;\n    case 0x8:           /* Set */\n        a |= b;\n        break;\n    case 0xc:           /* Invert */\n        a ^= b;\n        break;\n    }\n    return a;\n}\n\nvoid *dev_pic32_bmxcon_access (cpu_mips_t *cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t *data,\n    m_uint8_t *has_set_value)\n{\n    pic32_t *pic32 = dev->priv_data;\n\n    if (offset >= BMXCON_REG_SIZE) {\n        *data = 0;\n        return NULL;\n    }\n    if (op_type == MTS_READ)\n        *data = 0;\n    switch (offset & 0x1f0) {\n    case PIC32_BMXCON & 0x1f0:      /* Interrupt Control */\n        if (op_type == MTS_READ) {\n            *data = pic32->bmxcon;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        read BMXCON -> %08x\\n\", *data);\n        } else {\n            pic32->bmxcon = write_op (pic32->bmxcon, *data, offset);\n            if (cpu->vm->debug_level > 2)\n                printf (\"        BMXCON := %08x\\n\", pic32->bmxcon);\n        }\n        break;\n\n    case PIC32_BMXDKPBA & 0x1f0:    /* Data RAM kernel program base address */\n        if (op_type == MTS_READ) {\n            *data = pic32->bmx_ram_kpba;\n        } else {\n            pic32->bmx_ram_kpba = write_op (pic32->bmx_ram_kpba, *data, offset);\n        }\n        break;\n\n    case PIC32_BMXDUDBA & 0x1f0:    /* Data RAM user data base address */\n        if (op_type == MTS_READ) {\n            *data = pic32->bmx_ram_udba;\n        } else {\n            pic32->bmx_ram_udba = write_op (pic32->bmx_ram_udba, *data, offset);\n        }\n        break;\n\n    case PIC32_BMXDUPBA & 0x1f0:    /* Data RAM user program base address */\n        if (op_type == MTS_READ) {\n            *data = pic32->bmx_ram_upba;\n        } else {\n            pic32->bmx_ram_upba = write_op (pic32->bmx_ram_upba, *data, offset);\n        }\n        break;\n\n    case PIC32_BMXPUPBA & 0x1f0:    /* Program Flash user program base address */\n        if (op_type == MTS_READ) {\n            *data = pic32->bmx_flash_upba;\n        } else {\n            pic32->bmx_flash_upba = write_op (pic32->bmx_flash_upba, *data, offset);\n        }\n        break;\n\n    case PIC32_BMXDRMSZ & 0x1f0:    /* Data RAM memory size */\n        if (op_type == MTS_READ) {\n            *data = cpu->vm->ram_size * 1024;\n        }\n        break;\n\n    case PIC32_BMXPFMSZ & 0x1f0:    /* Program Flash memory size */\n        if (op_type == MTS_READ) {\n            *data = cpu->vm->flash_size * 1024;\n        }\n        break;\n\n    case PIC32_BMXBOOTSZ & 0x1f0:   /* Boot Flash size */\n        if (op_type == MTS_READ) {\n            *data = pic32->boot_flash_size * 1024;\n        }\n        break;\n\n    default:\n        ASSERT (0, \"unknown bmxcon offset %x\\n\", offset);\n    }\n    *has_set_value = TRUE;\n    return NULL;\n}\n\nvoid dev_pic32_bmxcon_reset (cpu_mips_t *cpu, struct vdevice *dev)\n{\n    pic32_t *pic32 = dev->priv_data;\n\n    pic32->bmxcon = 0x001f0041;\n    pic32->bmx_ram_kpba = 0;\n    pic32->bmx_ram_udba = 0;\n    pic32->bmx_ram_upba = 0;\n    pic32->bmx_flash_upba = 0;\n}\n\nint dev_pic32_bmxcon_init (vm_instance_t *vm, char *name, unsigned paddr)\n{\n    pic32_t *pic32 = (pic32_t *) vm->hw_data;\n\n    pic32->bmxdev = dev_create (name);\n    if (! pic32->bmxdev)\n        return (-1);\n    pic32->bmxdev->priv_data = pic32;\n    pic32->bmxdev->phys_addr = paddr;\n    pic32->bmxdev->phys_len = BMXCON_REG_SIZE;\n    pic32->bmxdev->handler = dev_pic32_bmxcon_access;\n    pic32->bmxdev->reset_handler = dev_pic32_bmxcon_reset;\n    pic32->bmxdev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n\n    vm_bind_device (vm, pic32->bmxdev);\n    return (0);\n}\n"
  },
  {
    "path": "tools/virtualmips/pic32_dev_devcfg.c",
    "content": "/*\n * Device configuration registers for PIC32.\n *\n * Copyright (C) 2012 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"cpu.h\"\n#include \"pic32.h\"\n\n#define DEVCFG_REG_SIZE     0x100\n\nvoid *dev_pic32_devcfg_access (cpu_mips_t *cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t *data,\n    m_uint8_t *has_set_value)\n{\n    pic32_t *pic32 = dev->priv_data;\n\n    if (offset >= DEVCFG_REG_SIZE) {\n        *data = 0;\n        return NULL;\n    }\n    if (op_type == MTS_READ)\n        *data = 0;\n    switch (offset & 0xfc) {\n    case 0xf0:                          /* DEVCFG3 */\n        if (op_type == MTS_READ) {\n            *data = pic32->devcfg3;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        read DEVCFG3 -> %08x\\n\", *data);\n        }\n        break;\n    case 0xf4:                          /* DEVCFG2 */\n        if (op_type == MTS_READ) {\n            *data = pic32->devcfg2;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        read DEVCFG3 -> %08x\\n\", *data);\n        }\n        break;\n    case 0xf8:                          /* DEVCFG1 */\n        if (op_type == MTS_READ) {\n            *data = pic32->devcfg1;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        read DEVCFG3 -> %08x\\n\", *data);\n        }\n        break;\n    case 0xfc:                          /* DEVCFG0 */\n        if (op_type == MTS_READ) {\n            *data = pic32->devcfg0;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        read DEVCFG3 -> %08x\\n\", *data);\n        }\n        break;\n\n    // TODO: other registers.\n\n    default:\n        ASSERT (0, \"unknown devcfg offset %x\\n\", offset);\n    }\n    *has_set_value = TRUE;\n    return NULL;\n}\n\nvoid dev_pic32_devcfg_reset (cpu_mips_t *cpu, struct vdevice *dev)\n{\n    pic32_t *pic32 = dev->priv_data;\n\n    pic32->devcfg3 = 0xffff0722;    // From Max32 bootloader\n    pic32->devcfg2 = 0xd979f8f9;\n    pic32->devcfg1 = 0x5bfd6aff;\n    pic32->devcfg0 = 0xffffff7f;\n}\n\nint dev_pic32_devcfg_init (vm_instance_t *vm, char *name, unsigned paddr)\n{\n    pic32_t *pic32 = (pic32_t *) vm->hw_data;\n\n    pic32->cfgdev = dev_create (name);\n    if (! pic32->cfgdev)\n        return (-1);\n    pic32->cfgdev->priv_data = pic32;\n    pic32->cfgdev->phys_addr = paddr;\n    pic32->cfgdev->phys_len = DEVCFG_REG_SIZE;\n    pic32->cfgdev->handler = dev_pic32_devcfg_access;\n    pic32->cfgdev->reset_handler = dev_pic32_devcfg_reset;\n    pic32->cfgdev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n\n    vm_bind_device (vm, pic32->cfgdev);\n    return (0);\n}\n"
  },
  {
    "path": "tools/virtualmips/pic32_dev_dmacon.c",
    "content": "/*\n * DMA controller for PIC32.\n *\n * Copyright (C) 2011 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"cpu.h\"\n#include \"pic32.h\"\n\n#define DMACON_REG_SIZE     0x660\n\nextern cpu_mips_t *current_cpu;\n\n/*\n * Perform an assign/clear/set/invert operation.\n */\nstatic inline unsigned write_op (int a, int b, int op)\n{\n    switch (op & 0xc) {\n    case 0x0:           /* Assign */\n        a = b;\n        break;\n    case 0x4:           /* Clear */\n        a &= ~b;\n        break;\n    case 0x8:           /* Set */\n        a |= b;\n        break;\n    case 0xc:           /* Invert */\n        a ^= b;\n        break;\n    }\n    return a;\n}\n\nvoid *dev_pic32_dmacon_access (cpu_mips_t *cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t *data,\n    m_uint8_t *has_set_value)\n{\n    pic32_t *pic32 = dev->priv_data;\n\n    if (offset >= DMACON_REG_SIZE) {\n        *data = 0;\n        return NULL;\n    }\n    if (op_type == MTS_READ)\n        *data = 0;\n    switch (offset & 0x1f0) {\n    case PIC32_DMACON & 0x1f0:      /* DMA Control */\n        if (op_type == MTS_READ) {\n            *data = pic32->dmacon;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        read DMACON -> %08x\\n\", *data);\n        } else {\n            pic32->dmacon = write_op (pic32->dmacon, *data, offset);\n            if (cpu->vm->debug_level > 2)\n                printf (\"        DMACON := %08x\\n\", pic32->dmacon);\n        }\n        break;\n\n    case PIC32_DMASTAT:             /* DMA Status */\n        if (op_type == MTS_READ) {\n            *data = pic32->dmastat;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        read DMASTAT -> %08x\\n\", *data);\n        }\n        break;\n\n    case PIC32_DMAADDR:             /* DMA address */\n        if (op_type == MTS_READ) {\n            *data = pic32->dmaaddr;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        read DMAADDR -> %08x\\n\", *data);\n        } else {\n            pic32->dmaaddr = *data;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        DMAADDR := %08x\\n\", *data);\n        }\n        break;\n\n    // TODO: other registers.\n\n    default:\n        ASSERT (0, \"unknown dmacon offset %x\\n\", offset);\n    }\n    *has_set_value = TRUE;\n    return NULL;\n}\n\nvoid dev_pic32_dmacon_reset (cpu_mips_t *cpu, struct vdevice *dev)\n{\n    pic32_t *pic32 = dev->priv_data;\n\n    pic32->dmacon = 0;\n    pic32->dmastat = 0;\n    pic32->dmaaddr = 0;\n}\n\nint dev_pic32_dmacon_init (vm_instance_t *vm, char *name, unsigned paddr)\n{\n    pic32_t *pic32 = (pic32_t *) vm->hw_data;\n\n    pic32->dmadev = dev_create (name);\n    if (! pic32->dmadev)\n        return (-1);\n    pic32->dmadev->priv_data = pic32;\n    pic32->dmadev->phys_addr = paddr;\n    pic32->dmadev->phys_len = DMACON_REG_SIZE;\n    pic32->dmadev->handler = dev_pic32_dmacon_access;\n    pic32->dmadev->reset_handler = dev_pic32_dmacon_reset;\n    pic32->dmadev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n\n    vm_bind_device (vm, pic32->dmadev);\n    return (0);\n}\n"
  },
  {
    "path": "tools/virtualmips/pic32_dev_flash.c",
    "content": "/*\n * Internal Flash memory of PIC32 microcontroller.\n\n * Copyright (C) 2011 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include <unistd.h>\n#include <string.h>\n#include <sys/stat.h>\n#include <sys/types.h>\n#include <sys/mman.h>\n#include <errno.h>\n#include <fcntl.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"pic32.h\"\n\n/* flash private data */\ntypedef struct flash_data {\n    struct vdevice *dev;\n    m_uint8_t *flash_ptr;\n    m_uint32_t flash_size;\n    m_uint8_t *flash_file_name;\n} flash_data_t;\n\nvoid *dev_flash_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type,\n    m_uint32_t * data, m_uint8_t * has_set_value)\n{\n    flash_data_t *d = dev->priv_data;\n\n    if (offset >= d->flash_size) {\n        printf (\"-- flash: access %08x -- out of memory\\n\", dev->phys_addr + offset);\n        *data = 0xff;\n        *has_set_value = TRUE;\n        return NULL;\n    }\n    if (op_type == MTS_READ) {\n#if 0\n        printf (\"-- flash: read %08x -> %08x\\n\", dev->phys_addr + offset,\n                *(unsigned *) (d->flash_ptr + offset));\n#endif\n        return d->flash_ptr + offset;\n    }\n    if (op_type == MTS_WRITE) {\n        printf (\"-- flash: write %08x ***\\n\", dev->phys_addr + offset);\n        return NULL;\n    }\n    assert (0);\n}\n\nstatic int dev_flash_load (char *flash_file_name, unsigned flash_len,\n    unsigned char **flash_data_hp)\n{\n    int fd;\n    struct stat sb;\n\n    fd = open (flash_file_name, O_RDONLY);\n    if (fd < 0) {\n        fprintf (stderr, \"%s does not exist.\\n\", flash_file_name);\n        return (-1);\n    }\n    fstat (fd, &sb);\n    if (flash_len < sb.st_size) {\n        fprintf (stderr,\n            \"Too large flash file.\\nFlash len: %d kbytes, file name %s, \"\n            \"file legth: %d bytes.\\n\", flash_len / 1024, flash_file_name,\n            (int) sb.st_size);\n        return (-1);\n    }\n    if (sb.st_size <= 0) {\n        fprintf (stderr, \"%s: empty flash file.\\n\", flash_file_name);\n        return (-1);\n    }\n    *flash_data_hp = mmap (NULL, sb.st_size, PROT_READ, MAP_SHARED, fd, 0);\n    if (*flash_data_hp == MAP_FAILED) {\n        fprintf (stderr, \"%s: \", flash_file_name);\n        perror (\"mmap\");\n        return (-1);\n    }\n    return 0;\n}\n\nstatic void dev_flash_reset (cpu_mips_t * cpu, struct vdevice *dev)\n{\n    //flash_data_t *d = dev->priv_data;\n\n    //d->state = 0;\n}\n\n/*\n * Initialize a NOR Flash zone\n */\nint dev_pic32_flash_init (vm_instance_t * vm, char *name,\n    unsigned flash_kbytes, unsigned flash_address, char *filename)\n{\n    flash_data_t *d;\n    unsigned char *flash_data_hp;\n\n    /* load rom data */\n    if (dev_flash_load (filename, flash_kbytes * 1024, &flash_data_hp) < 0)\n        return (-1);\n\n    /* allocate the private data structure */\n    d = malloc (sizeof (*d));\n    if (!d) {\n        fprintf (stderr, \"FLASH: unable to create device.\\n\");\n        return (-1);\n    }\n\n    memset (d, 0, sizeof (*d));\n    d->flash_ptr = flash_data_hp;\n    d->flash_size = flash_kbytes * 1024;\n\n    d->dev = dev_create (name);\n    if (!d->dev) {\n        free (d);\n        return (-1);\n    }\n    d->dev->priv_data = d;\n    d->dev->phys_addr = flash_address;\n    d->dev->phys_len = flash_kbytes * 1024;\n    d->dev->handler = dev_flash_access;\n    d->dev->reset_handler = dev_flash_reset;\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n\n    /* Map this device to the VM */\n    vm_bind_device (vm, d->dev);\n    return (0);\n}\n"
  },
  {
    "path": "tools/virtualmips/pic32_dev_gpio.c",
    "content": "/*\n * GPIO emulation for PIC32.\n *\n * Copyright (C) 2011 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"pic32.h\"\n#include \"cpu.h\"\n#include \"vp_timer.h\"\n\n#define GPIO_REG_SIZE   0x1F0\n\n#ifdef UBW32\n#define MASKA_CS0       (1 << 9)            // A9: sd0 on SPI1\n#define MASKA_CS1       (1 << 10)           // A10: sd1 on SPI1\n#define MASKC_LDADDR    (1 << 1)            // C1: swap LDADDR\n#define MASKE_WR        (1 << 9)            // E8: swap WR\n#define MASKE_RD        (1 << 8)            // E8: swap RD\n#define MASKE_DATA      (0xff << 0)         // E0-E7: swap DATA\n#define SHIFTE_DATA     0\n\n#elif defined MAXIMITE\n#define MASKE_CS0       (1 << 0)            // E0: sd0 on SPI4\n#define MASKE_CS1                           // reserved\n#define MASKD_PS2C      (1 << 6)            // PS2 keyboard\n#define MASKD_PS2D      (1 << 7)\n\n#elif defined MAX32\n#define MASKC_CS0       (1 << 14)           // C14: sd0 on SPI2\n#define MASKD_CS1       (1 << 1)            // D1:  sd1 on SPI2\n\n#elif defined EXPLORER16\n#define MASKB_CS0       (1 << 1)            // B1: sd0 on SPI1\n#define MASKB_CS1       (1 << 2)            // B2: sd1 on SPI1\n#endif\n\nstruct pic32_gpio_data {\n    struct vdevice  *dev;\n    vtty_t          *vtty;\n    vm_instance_t   *vm;\n    pic32_t         *pic32;\n\n    unsigned        tris_a;         /* 0x00 - port A mask of inputs */\n    unsigned        port_a;         /* 0x10 - port A pins */\n    unsigned        lat_a;          /* 0x20 - port A latched outputs */\n    unsigned        odc_a;          /* 0x30 - port A open drain configuration */\n\n    unsigned        tris_b;         /* 0x40 - port B mask of inputs */\n    unsigned        port_b;         /* 0x50 - port B pins */\n    unsigned        lat_b;          /* 0x60 - port B latched outputs */\n    unsigned        odc_b;          /* 0x70 - port B open drain configuration */\n\n    unsigned        tris_c;         /* 0x80 - port C mask of inputs */\n    unsigned        port_c;         /* 0x90 - port C pins */\n    unsigned        lat_c;          /* 0xA0 - port C latched outputs */\n    unsigned        odc_c;          /* 0xB0 - port C open drain configuration */\n\n    unsigned        tris_d;         /* 0xC0 - port D mask of inputs */\n    unsigned        port_d;         /* 0xD0 - port D pins */\n    unsigned        lat_d;          /* 0xE0 - port D latched outputs */\n    unsigned        odc_d;          /* 0xF0 - port D open drain configuration */\n\n    unsigned        tris_e;         /* 0x00 - port E mask of inputs */\n    unsigned        port_e;         /* 0x10 - port E pins */\n    unsigned        lat_e;          /* 0x20 - port E latched outputs */\n    unsigned        odc_e;          /* 0x30 - port E open drain configuration */\n\n    unsigned        tris_f;         /* 0x40 - port F mask of inputs */\n    unsigned        port_f;         /* 0x50 - port F pins */\n    unsigned        lat_f;          /* 0x60 - port F latched outputs */\n    unsigned        odc_f;          /* 0x70 - port F open drain configuration */\n\n    unsigned        tris_g;         /* 0x80 - port G mask of inputs */\n    unsigned        port_g;         /* 0x90 - port G pins */\n    unsigned        lat_g;          /* 0xA0 - port G latched outputs */\n    unsigned        odc_g;          /* 0xB0 - port G open drain configuration */\n\n    unsigned        cncon;          /* 0xC0 - interrupt-on-change control */\n    unsigned        cnen;           /* 0xD0 - input change interrupt enable */\n    unsigned        cnpue;          /* 0xE0 - input pin pull-up enable */\n};\n\nextern cpu_mips_t *current_cpu;\n\n/*\n * Perform an assign/clear/set/invert operation.\n */\nstatic inline unsigned write_op (int a, int b, int op)\n{\n    switch (op & 0xc) {\n    case 0x0:           /* Assign */\n        a = b;\n        break;\n    case 0x4:           /* Clear */\n        a &= ~b;\n        break;\n    case 0x8:           /* Set */\n        a |= b;\n        break;\n    case 0xc:           /* Invert */\n        a ^= b;\n        break;\n    }\n    return a;\n}\n\nvoid *dev_pic32_gpio_access (cpu_mips_t *cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type,\n    m_reg_t * data, m_uint8_t * has_set_value)\n{\n    struct pic32_gpio_data *d = dev->priv_data;\n\n    if (offset >= GPIO_REG_SIZE) {\n        printf (\"gpio: overhit\\n\");\n        *data = 0;\n        return NULL;\n    }\n    //printf (\"gpio: %s offset %#x\\n\", (op_type == MTS_READ) ? \"read\" : \"write\", offset);\n    if (op_type == MTS_READ)\n        *data = 0;\n    switch (offset & 0x1f0) {\n    /*\n     * Port A\n     */\n    case PIC32_TRISA & 0x1f0:             /* Port A: mask of inputs */\n        if (op_type == MTS_READ) {\n            *data = d->tris_a;\n        } else {\n            d->tris_a = write_op (d->tris_a, *data, offset);\n        }\n        break;\n\n    case PIC32_PORTA & 0x1f0:             /* Port A: read inputs, write outputs */\n        if (op_type == MTS_READ) {\n            *data = d->port_a;\n        } else {\n            goto lat_a;\n        }\n        break;\n\n    case PIC32_LATA & 0x1f0:              /* Port A: read/write outputs */\n        if (op_type == MTS_READ) {\n            *data = d->lat_a;\n        } else {\nlat_a:      d->lat_a = write_op (d->lat_a, *data, offset);\n#ifdef UBW32\n            /* Control SD card 0 */\n            if (d->lat_a & MASKA_CS0)\n                dev_sdcard_select (cpu, 0, 0);\n            else\n                dev_sdcard_select (cpu, 0, 1);\n\n            /* Control SD card 1 */\n            if (d->lat_a & MASKA_CS1)\n                dev_sdcard_select (cpu, 1, 0);\n            else\n                dev_sdcard_select (cpu, 1, 1);\n#endif\n        }\n        break;\n\n    case PIC32_ODCA & 0x1f0:              /* Port A: open drain configuration */\n        if (op_type == MTS_READ) {\n            *data = d->odc_a;\n        } else {\n            d->odc_a = write_op (d->odc_a, *data, offset);\n        }\n        break;\n\n    /*\n     * Port B\n     */\n    case PIC32_TRISB & 0x1f0:             /* Port B: mask of inputs */\n        if (op_type == MTS_READ) {\n            *data = d->tris_b;\n        } else {\n            d->tris_b = write_op (d->tris_b, *data, offset);\n        }\n        break;\n\n    case PIC32_PORTB & 0x1f0:             /* Port B: read inputs, write outputs */\n        if (op_type == MTS_READ) {\n            *data = d->port_b;\n        } else {\n            goto lat_b;\n        }\n        break;\n\n    case PIC32_LATB & 0x1f0:              /* Port B: read/write outputs */\n        if (op_type == MTS_READ) {\n            *data = d->lat_b;\n        } else {\nlat_b:      d->lat_b = write_op (d->lat_b, *data, offset);\n#ifdef EXPLORER16\n            /* Control SD card 0 */\n            if (d->lat_b & MASKB_CS0)\n                dev_sdcard_select (cpu, 0, 0);\n            else\n                dev_sdcard_select (cpu, 0, 1);\n\n            /* Control SD card 1 */\n            if (d->lat_b & MASKB_CS1)\n                dev_sdcard_select (cpu, 1, 0);\n            else\n                dev_sdcard_select (cpu, 1, 1);\n#endif\n        }\n        break;\n\n    case PIC32_ODCB & 0x1f0:              /* Port B: open drain configuration */\n        if (op_type == MTS_READ) {\n            *data = d->odc_b;\n        } else {\n            d->odc_b = write_op (d->odc_b, *data, offset);\n        }\n        break;\n\n    /*\n     * Port C\n     */\n    case PIC32_TRISC & 0x1f0:             /* Port C: mask of inputs */\n        if (op_type == MTS_READ) {\n            *data = d->tris_c;\n        } else {\n            d->tris_c = write_op (d->tris_c, *data, offset);\n        }\n        break;\n\n    case PIC32_PORTC & 0x1f0:             /* Port C: read inputs, write outputs */\n        if (op_type == MTS_READ) {\n            *data = d->port_c;\n        } else {\n            goto lat_c;\n        }\n        break;\n\n    case PIC32_LATC & 0x1f0:              /* Port C: read/write outputs */\n        if (op_type == MTS_READ) {\n            *data = d->lat_c;\n        } else {\nlat_c:      d->lat_c = write_op (d->lat_c, *data, offset);\n#ifdef UBW32\n            if (d->lat_c & MASKC_LDADDR)  /* Swap disk: LDADDR */\n                dev_swap_ldaddr (cpu, 0);\n            else\n                dev_swap_ldaddr (cpu, 1);\n#endif\n#ifdef MAX32\n            /* Control SD card 0 */\n            if (d->lat_c & MASKC_CS0)\n                dev_sdcard_select (cpu, 0, 0);\n            else\n                dev_sdcard_select (cpu, 0, 1);\n#endif\n        }\n        break;\n\n    case PIC32_ODCC & 0x1f0:              /* Port C: open drain configuration */\n        if (op_type == MTS_READ) {\n            *data = d->odc_c;\n        } else {\n            d->odc_c = write_op (d->odc_c, *data, offset);\n        }\n        break;\n\n    /*\n     * Port D\n     */\n    case PIC32_TRISD & 0x1f0:             /* Port D: mask of inputs */\n        if (op_type == MTS_READ) {\n            *data = d->tris_d;\n        } else {\n            d->tris_d = write_op (d->tris_d, *data, offset);\n        }\n        break;\n\n    case PIC32_PORTD & 0x1f0:             /* Port D: read inputs, write outputs */\n#ifndef MAXIMITE\n        if (op_type == MTS_READ) {\n            *data = d->port_d;\n        } else {\n            goto lat_d;\n        }\n#else\n        if (op_type == MTS_READ) {\n#if 0\n            /* Poll PS2 keyboard */\n            if (dev_keyboard_clock (cpu))\n                d->port_d &= ~MASKD_PS2C;\n            else\n                d->port_d |= MASKD_PS2C;\n            if (dev_keyboard_data (cpu))\n                d->port_d &= ~MASKD_PS2D;\n            else\n                d->port_d |= MASKD_PS2D;\n#endif\n            *data = d->port_d;\n        } else {\n            goto lat_d;\n        }\n#endif\n        break;\n\n    case PIC32_LATD & 0x1f0:              /* Port D: read/write outputs */\n        if (op_type == MTS_READ) {\n            *data = d->lat_d;\n        } else {\nlat_d:      d->lat_d = write_op (d->lat_d, *data, offset);\n#ifdef MAX32\n            /* Control SD card 1 */\n            if (d->lat_d & MASKD_CS1)\n                dev_sdcard_select (cpu, 1, 0);\n            else\n                dev_sdcard_select (cpu, 1, 1);\n#endif\n        }\n        break;\n\n    case PIC32_ODCD & 0x1f0:              /* Port D: open drain configuration */\n        if (op_type == MTS_READ) {\n            *data = d->odc_d;\n        } else {\n            d->odc_d = write_op (d->odc_d, *data, offset);\n        }\n        break;\n\n    /*\n     * Port E\n     */\n    case PIC32_TRISE & 0x1f0:             /* Port E: mask of inputs */\n        if (op_type == MTS_READ) {\n            *data = d->tris_e;\n        } else {\n            d->tris_e = write_op (d->tris_e, *data, offset);\n        }\n        break;\n\n    case PIC32_PORTE & 0x1f0:             /* Port E: read inputs, write outputs */\n        if (op_type == MTS_READ) {\n#ifdef UBW32\n            /* Swap disk: DATA */\n            d->port_e &= ~MASKE_DATA;\n            d->port_e |= dev_swap_io (cpu, 0, 0xff);\n#endif\n            *data = d->port_e;\n        } else {\n            goto lat_e;\n        }\n        break;\n\n    case PIC32_LATE & 0x1f0:              /* Port E: read/write outputs */\n        if (op_type == MTS_READ) {\n            *data = d->lat_e;\n        } else {\nlat_e:      d->lat_e = write_op (d->lat_e, *data, offset);\n#ifdef MAXIMITE\n            /* Control SD card 0 */\n            if (d->lat_e & MASKE_CS0)\n                dev_sdcard_select (cpu, 0, 0);\n            else\n                dev_sdcard_select (cpu, 0, 1);\n#if 0\n            /* Control SD card 1 */\n            if (d->lat_e & MASKE_CS1)\n                dev_sdcard_select (cpu, 1, 0);\n            else\n                dev_sdcard_select (cpu, 1, 1);\n#endif\n#endif\n#ifdef UBW32\n            if (d->lat_e & MASKE_RD)        /* Swap disk: RD */\n                dev_swap_rd (cpu, 0);\n            else\n                dev_swap_rd (cpu, 1);\n\n            if (d->lat_e & MASKE_WR)        /* Swap disk: WR */\n                dev_swap_wr (cpu, 0);\n            else\n                dev_swap_wr (cpu, 1);\n\n            /* Swap disk: DATA */\n            dev_swap_io (cpu, d->lat_e >> SHIFTE_DATA,\n                d->tris_e >> SHIFTE_DATA);\n#endif\n        }\n        break;\n\n    case PIC32_ODCE & 0x1f0:              /* Port E: open drain configuration */\n        if (op_type == MTS_READ) {\n            *data = d->odc_e;\n        } else {\n            d->odc_e = write_op (d->odc_e, *data, offset);\n        }\n        break;\n\n    /*\n     * Port F\n     */\n    case PIC32_TRISF & 0x1f0:             /* Port F: mask of inputs */\n        if (op_type == MTS_READ) {\n            *data = d->tris_f;\n        } else {\n            d->tris_f = write_op (d->tris_f, *data, offset);\n        }\n        break;\n\n    case PIC32_PORTF & 0x1f0:             /* Port F: read inputs, write outputs */\n        if (op_type == MTS_READ) {\n            *data = d->port_f;\n        } else {\n            goto lat_f;\n        }\n        break;\n\n    case PIC32_LATF & 0x1f0:              /* Port F: read/write outputs */\n        if (op_type == MTS_READ) {\n            *data = d->lat_f;\n        } else {\nlat_f:      d->lat_f = write_op (d->lat_f, *data, offset);\n        }\n        break;\n\n    case PIC32_ODCF & 0x1f0:              /* Port F: open drain configuration */\n        if (op_type == MTS_READ) {\n            *data = d->odc_f;\n        } else {\n            d->odc_f = write_op (d->odc_f, *data, offset);\n        }\n        break;\n\n    /*\n     * Port G\n     */\n    case PIC32_TRISG & 0x1f0:             /* Port G: mask of inputs */\n        if (op_type == MTS_READ) {\n            *data = d->tris_g;\n        } else {\n            d->tris_g = write_op (d->tris_g, *data, offset);\n        }\n        break;\n\n    case PIC32_PORTG & 0x1f0:             /* Port G: read inputs, write outputs */\n        if (op_type == MTS_READ) {\n            *data = d->port_g;\n        } else {\n            goto lat_g;\n        }\n        break;\n\n    case PIC32_LATG & 0x1f0:              /* Port G: read/write outputs */\n        if (op_type == MTS_READ) {\n            *data = d->lat_g;\n        } else {\nlat_g:      d->lat_g = write_op (d->lat_g, *data, offset);\n        }\n        break;\n\n    case PIC32_ODCG & 0x1f0:              /* Port G: open drain configuration */\n        if (op_type == MTS_READ) {\n            *data = d->odc_g;\n        } else {\n            d->odc_g = write_op (d->odc_g, *data, offset);\n        }\n        break;\n\n    /*\n     * Change notifier\n     */\n    case PIC32_CNCON & 0x1f0:             /* Interrupt-on-change control */\n        if (op_type == MTS_READ) {\n            *data = d->cncon;\n        } else {\n            d->cncon = write_op (d->cncon, *data, offset);\n        }\n        break;\n\n    case PIC32_CNEN & 0x1f0:              /* Input change interrupt enable */\n        if (op_type == MTS_READ) {\n            *data = d->cnen;\n        } else {\n            d->cnen = write_op (d->cnen, *data, offset);\n        }\n        break;\n\n    case PIC32_CNPUE & 0x1f0:             /* Input pin pull-up enable */\n        if (op_type == MTS_READ) {\n            *data = d->cnpue;\n        } else {\n            d->cnpue = write_op (d->cnpue, *data, offset);\n        }\n        break;\n/* TODO */\n//printf (\"%s: read data.\\n\", dev->name);\n/* TODO */\n//printf (\"%s: write %02x.\\n\", dev->name, d->buf);\n    default:\n        ASSERT (0, \"%s: unknown offset 0x%x\\n\", dev->name, offset);\n    }\n    *has_set_value = TRUE;\n    return NULL;\n}\n\nvoid dev_pic32_gpio_reset (cpu_mips_t * cpu, struct vdevice *dev)\n{\n    struct pic32_gpio_data *d = dev->priv_data;\n\n    /* All pins are inputs. */\n    d->tris_a = d->tris_b = d->tris_c = d->tris_d =\n                d->tris_e = d->tris_f = d->tris_g = 0xFFFF;\n\n    /* All inputs are high. */\n    d->port_a = d->port_b = d->port_c = d->port_d =\n                d->port_e = d->port_f = d->port_g = 0xFFFF;\n\n    /* All outputs are high. */\n    d->lat_a = d->lat_b = d->lat_c = d->lat_d =\n                d->lat_e = d->lat_f = d->lat_g = 0xFFFF;\n\n    /* All open drains are disabled. */\n    d->odc_a = d->odc_b = d->odc_c = d->odc_d =\n                d->odc_e = d->odc_f = d->odc_g = 0;\n\n    /* No interrupts, no pullups. */\n    d->cncon = 0;\n    d->cnen = 0;\n    d->cnpue = 0;\n}\n\nint dev_pic32_gpio_init (vm_instance_t *vm, char *name, unsigned paddr)\n{\n    struct pic32_gpio_data *d;\n    pic32_t *pic32 = (pic32_t *) vm->hw_data;\n\n    /* allocate the private data structure */\n    d = malloc (sizeof (*d));\n    if (!d) {\n        fprintf (stderr, \"PIC32 GPIO: unable to create device.\\n\");\n        return (-1);\n    }\n    memset (d, 0, sizeof (*d));\n    d->dev = dev_create (name);\n    if (!d->dev) {\n        free (d);\n        return (-1);\n    }\n    d->dev->priv_data = d;\n    d->dev->phys_addr = paddr;\n    d->dev->phys_len = GPIO_REG_SIZE;\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n    d->vm = vm;\n    d->pic32 = pic32;\n    d->dev->handler = dev_pic32_gpio_access;\n    d->dev->reset_handler = dev_pic32_gpio_reset;\n\n    vm_bind_device (vm, d->dev);\n    return (0);\n}\n"
  },
  {
    "path": "tools/virtualmips/pic32_dev_intcon.c",
    "content": "/*\n * Interrupt controller for PIC32.\n *\n * Copyright (C) 2011 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"cpu.h\"\n#include \"pic32.h\"\n\n#define INTCON_REG_SIZE     0x190\n\nextern cpu_mips_t *current_cpu;\n\n/*\n * Perform an assign/clear/set/invert operation.\n */\nstatic inline unsigned write_op (int a, int b, int op)\n{\n    switch (op & 0xc) {\n    case 0x0:           /* Assign */\n        a = b;\n        break;\n    case 0x4:           /* Clear */\n        a &= ~b;\n        break;\n    case 0x8:           /* Set */\n        a |= b;\n        break;\n    case 0xc:           /* Invert */\n        a ^= b;\n        break;\n    }\n    return a;\n}\n\nvoid *dev_pic32_intcon_access (cpu_mips_t *cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t *data,\n    m_uint8_t *has_set_value)\n{\n    pic32_t *pic32 = dev->priv_data;\n    unsigned n, v;\n\n    if (offset >= INTCON_REG_SIZE) {\n        *data = 0;\n        return NULL;\n    }\n    if (op_type == MTS_READ)\n        *data = 0;\n    switch (offset & 0x1f0) {\n    case PIC32_INTCON & 0x1f0:      /* Interrupt Control */\n        if (op_type == MTS_READ) {\n            *data = pic32->intcon;\n        } else {\n            pic32->intcon = write_op (pic32->intcon, *data, offset);\n        }\n        break;\n\n    case PIC32_INTSTAT & 0x1f0:     /* Interrupt Status */\n        if (op_type == MTS_READ) {\n            *data = pic32->intstat;\n        }\n        break;\n\n    case PIC32_IPTMR & 0x1f0:\t\t/* Temporal Proximity Timer */\n        if (op_type == MTS_READ) {\n            *data = pic32->iptmr;\n        } else {\n            pic32->iptmr = write_op (pic32->iptmr, *data, offset);\n        }\n        break;\n\n    case PIC32_IFS(0) & 0x1f0:      /* IFS(0..2) - Interrupt Flag Status */\n    case PIC32_IFS(1) & 0x1f0:\n    case PIC32_IFS(2) & 0x1f0:\n        n = (offset - (PIC32_IFS(0) & 0x1f0)) >> 4;\n        if (op_type == MTS_READ) {\n            *data = pic32->ifs[n];\n        } else {\n            pic32->ifs[n] = write_op (pic32->ifs[n], *data, offset);\n            pic32_update_irq_flag (pic32);\n        }\n        break;\n\n    case PIC32_IEC(0) & 0x1f0:      /* IEC(0..2) - Interrupt Enable Control */\n    case PIC32_IEC(1) & 0x1f0:\n    case PIC32_IEC(2) & 0x1f0:\n        n = (offset - (PIC32_IEC(0) & 0x1f0)) >> 4;\n        if (op_type == MTS_READ) {\n            *data = pic32->iec[n];\n        } else {\n            pic32->iec[n] = write_op (pic32->iec[n], *data, offset);\n            pic32_update_irq_flag (pic32);\n        }\n        break;\n\n    case PIC32_IPC(0) & 0x1f0:      /* IPC(0..11) - Interrupt Priority Control */\n    case PIC32_IPC(1) & 0x1f0:\n    case PIC32_IPC(2) & 0x1f0:\n    case PIC32_IPC(3) & 0x1f0:\n    case PIC32_IPC(4) & 0x1f0:\n    case PIC32_IPC(5) & 0x1f0:\n    case PIC32_IPC(6) & 0x1f0:\n    case PIC32_IPC(7) & 0x1f0:\n    case PIC32_IPC(8) & 0x1f0:\n    case PIC32_IPC(9) & 0x1f0:\n    case PIC32_IPC(10) & 0x1f0:\n    case PIC32_IPC(11) & 0x1f0:\n    case PIC32_IPC(12) & 0x1f0:\n        n = (offset - (PIC32_IPC(0) & 0x1f0)) >> 4;\n        if (op_type == MTS_READ) {\n            *data = pic32->ipc[n];\n        } else {\n            pic32->ipc[n] = write_op (pic32->ipc[n], *data, offset);\n            v = n << 2;\n            pic32->ivprio[v]   = pic32->ipc[n] >> 2 & 63;\n            pic32->ivprio[v+1] = pic32->ipc[n] >> 10 & 63;\n            pic32->ivprio[v+2] = pic32->ipc[n] >> 18 & 63;\n            pic32->ivprio[v+3] = pic32->ipc[n] >> 26 & 63;\n            pic32_update_irq_flag (pic32);\n        }\n        break;\n\n    default:\n        ASSERT (0, \"unknown intcon offset %x\\n\", offset);\n    }\n    *has_set_value = TRUE;\n    return NULL;\n}\n\nvoid dev_pic32_intcon_reset (cpu_mips_t *cpu, struct vdevice *dev)\n{\n    pic32_t *pic32 = dev->priv_data;\n\n    pic32->intcon = 0;\n    pic32->intstat = 0;\n    pic32->iptmr = 0;\n    memset (pic32->ifs, 0, sizeof (pic32->ifs));\n    memset (pic32->iec, 0, sizeof (pic32->iec));\n    memset (pic32->ipc, 0, sizeof (pic32->ipc));\n    memset (pic32->ivprio, 0, sizeof (pic32->ivprio));\n\n    cpu->irq_cause = 0;\n    cpu->irq_pending = 0;\n}\n\nint dev_pic32_intcon_init (vm_instance_t *vm, char *name, unsigned paddr)\n{\n    pic32_t *pic32 = (pic32_t *) vm->hw_data;\n\n    pic32->intdev = dev_create (name);\n    if (! pic32->intdev)\n        return (-1);\n    pic32->intdev->priv_data = pic32;\n    pic32->intdev->phys_addr = paddr;\n    pic32->intdev->phys_len = INTCON_REG_SIZE;\n    pic32->intdev->handler = dev_pic32_intcon_access;\n    pic32->intdev->reset_handler = dev_pic32_intcon_reset;\n    pic32->intdev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n\n    vm_bind_device (vm, pic32->intdev);\n    return (0);\n}\n"
  },
  {
    "path": "tools/virtualmips/pic32_dev_prefetch.c",
    "content": "/*\n * Prefetch controller for PIC32.\n *\n * Copyright (C) 2011 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"cpu.h\"\n#include \"pic32.h\"\n\n#define PREFETCH_REG_SIZE     0xd0\n\nextern cpu_mips_t *current_cpu;\n\n/*\n * Perform an assign/clear/set/invert operation.\n */\nstatic inline unsigned write_op (int a, int b, int op)\n{\n    switch (op & 0xc) {\n    case 0x0:           /* Assign */\n        a = b;\n        break;\n    case 0x4:           /* Clear */\n        a &= ~b;\n        break;\n    case 0x8:           /* Set */\n        a |= b;\n        break;\n    case 0xc:           /* Invert */\n        a ^= b;\n        break;\n    }\n    return a;\n}\n\nvoid *dev_pic32_prefetch_access (cpu_mips_t *cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t *data,\n    m_uint8_t *has_set_value)\n{\n    pic32_t *pic32 = dev->priv_data;\n\n    if (offset >= PREFETCH_REG_SIZE) {\n        *data = 0;\n        return NULL;\n    }\n    if (op_type == MTS_READ)\n        *data = 0;\n    switch (offset & 0x1f0) {\n    case PIC32_CHECON & 0xf0:       /* Prefetch Control */\n        if (op_type == MTS_READ) {\n            *data = pic32->checon;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        read CHECON -> %08x\\n\", *data);\n        } else {\n            pic32->checon = write_op (pic32->checon, *data, offset);\n            if (cpu->vm->debug_level > 2)\n                printf (\"        CHECON := %08x\\n\", pic32->checon);\n        }\n        break;\n\n    // TODO: other registers.\n\n    default:\n        ASSERT (0, \"unknown prefetch offset %x\\n\", offset);\n    }\n    *has_set_value = TRUE;\n    return NULL;\n}\n\nvoid dev_pic32_prefetch_reset (cpu_mips_t *cpu, struct vdevice *dev)\n{\n    pic32_t *pic32 = dev->priv_data;\n\n    pic32->checon = 0x00000007;\n}\n\nint dev_pic32_prefetch_init (vm_instance_t *vm, char *name, unsigned paddr)\n{\n    pic32_t *pic32 = (pic32_t *) vm->hw_data;\n\n    pic32->prefetch = dev_create (name);\n    if (! pic32->prefetch)\n        return (-1);\n    pic32->prefetch->priv_data = pic32;\n    pic32->prefetch->phys_addr = paddr;\n    pic32->prefetch->phys_len = PREFETCH_REG_SIZE;\n    pic32->prefetch->handler = dev_pic32_prefetch_access;\n    pic32->prefetch->reset_handler = dev_pic32_prefetch_reset;\n    pic32->prefetch->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n\n    vm_bind_device (vm, pic32->prefetch);\n    return (0);\n}\n"
  },
  {
    "path": "tools/virtualmips/pic32_dev_rtcc.c",
    "content": "/*\n * Interrupt controller for PIC32.\n *\n * Copyright (C) 2011 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"cpu.h\"\n#include \"pic32.h\"\n\n#define RTCC_REG_SIZE     0x80\n\nextern cpu_mips_t *current_cpu;\n\n/*\n * Perform an assign/clear/set/invert operation.\n */\nstatic inline unsigned write_op (int a, int b, int op)\n{\n    switch (op & 0xc) {\n    case 0x0:           /* Assign */\n        a = b;\n        break;\n    case 0x4:           /* Clear */\n        a &= ~b;\n        break;\n    case 0x8:           /* Set */\n        a |= b;\n        break;\n    case 0xc:           /* Invert */\n        a ^= b;\n        break;\n    }\n    return a;\n}\n\nvoid *dev_pic32_rtcc_access (cpu_mips_t *cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t *data,\n    m_uint8_t *has_set_value)\n{\n    pic32_t *pic32 = dev->priv_data;\n\n    if (offset >= RTCC_REG_SIZE) {\n        *data = 0;\n        return NULL;\n    }\n    if (op_type == MTS_READ)\n        *data = 0;\n    switch (offset & 0x1f0) {\n    case PIC32_RTCCON & 0x1f0:      /* RTC Control */\n        if (op_type == MTS_READ) {\n            *data = pic32->rtccon;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        read RTCCON -> %08x\\n\", *data);\n        } else {\n            pic32->rtccon = write_op (pic32->rtccon, *data, offset);\n            if (cpu->vm->debug_level > 2)\n                printf (\"        RTCCON := %08x\\n\", pic32->rtccon);\n        }\n        break;\n\n    case PIC32_RTCALRM & 0x1f0:     /* RTC alarm control */\n        if (op_type == MTS_READ) {\n            *data = 0;\n        } else {\n            //pic32->rtcalrm = write_op (pic32->rtcalrm, *data, offset);\n        }\n        break;\n\n    case PIC32_RTCTIME & 0x1f0:     /* RTC time value */\n        if (op_type == MTS_READ) {\n            *data = 0;\n        } else {\n            //pic32->rtctime = write_op (pic32->rtctime, *data, offset);\n        }\n        break;\n\n    case PIC32_RTCDATE & 0x1f0:     /* RTC date value */\n        if (op_type == MTS_READ) {\n            *data = 0;\n        } else {\n            //pic32->rtcdate = write_op (pic32->rtcdate, *data, offset);\n        }\n        break;\n\n    case PIC32_ALRMTIME & 0x1f0:    /* Alarm time value */\n        if (op_type == MTS_READ) {\n            *data = 0;\n        } else {\n            //pic32->alrmtime = write_op (pic32->alrmtime, *data, offset);\n        }\n        break;\n\n    case PIC32_ALRMDATE & 0x1f0:    /* Alarm date value */\n        if (op_type == MTS_READ) {\n            *data = 0;\n        } else {\n            //pic32->alrmdate = write_op (pic32->alrmdate, *data, offset);\n        }\n        break;\n\n    default:\n        ASSERT (0, \"unknown rtcc offset %x\\n\", offset);\n    }\n    *has_set_value = TRUE;\n    return NULL;\n}\n\nvoid dev_pic32_rtcc_reset (cpu_mips_t *cpu, struct vdevice *dev)\n{\n    pic32_t *pic32 = dev->priv_data;\n\n    pic32->rtccon = 0;\n}\n\nint dev_pic32_rtcc_init (vm_instance_t *vm, char *name, unsigned paddr)\n{\n    pic32_t *pic32 = (pic32_t *) vm->hw_data;\n\n    pic32->rtcdev = dev_create (name);\n    if (! pic32->rtcdev)\n        return (-1);\n    pic32->rtcdev->priv_data = pic32;\n    pic32->rtcdev->phys_addr = paddr;\n    pic32->rtcdev->phys_len = RTCC_REG_SIZE;\n    pic32->rtcdev->handler = dev_pic32_rtcc_access;\n    pic32->rtcdev->reset_handler = dev_pic32_rtcc_reset;\n    pic32->rtcdev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n\n    vm_bind_device (vm, pic32->rtcdev);\n    return (0);\n}\n"
  },
  {
    "path": "tools/virtualmips/pic32_dev_spi.c",
    "content": "/*\n * SPI emulation for PIC32.\n * Two SD/MMC disks attached to SPI1.\n *\n * Copyright (C) 2011 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"pic32.h\"\n#include \"cpu.h\"\n#include \"vp_timer.h\"\n#include \"dev_sdcard.h\"\n\n#define SPI_REG_SIZE    0x40\n\nstruct pic32_spi_data {\n    struct vdevice  *dev;\n    vm_instance_t   *vm;\n    pic32_t         *pic32;\n\n    u_int           irq;            /* base irq number */\n#define IRQ_FAULT   0               /* error interrupt */\n#define IRQ_TX      1               /* transmitter interrupt */\n#define IRQ_RX      2               /* receiver interrupt */\n\n    unsigned        con;            /* 0x00 - Control */\n    unsigned        stat;           /* 0x10 - Status */\n    unsigned        buf [4];        /* 0x20 - Transmit and receive buffer */\n    unsigned        brg;            /* 0x40 - Baud rate generator */\n\n    unsigned        rfifo;          /* read fifo counter */\n    unsigned        wfifo;          /* write fifo counter */\n};\n\nextern cpu_mips_t *current_cpu;\n\n/*\n * Perform an assign/clear/set/invert operation.\n */\nstatic inline unsigned write_op (int a, int b, int op)\n{\n    switch (op & 0xc) {\n    case 0x0:           /* Assign */\n        a = b;\n        break;\n    case 0x4:           /* Clear */\n        a &= ~b;\n        break;\n    case 0x8:           /* Set */\n        a |= b;\n        break;\n    case 0xc:           /* Invert */\n        a ^= b;\n        break;\n    }\n    return a;\n}\n\nvoid *dev_pic32_spi_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type,\n    m_reg_t * data, m_uint8_t * has_set_value)\n{\n    struct pic32_spi_data *d = dev->priv_data;\n    unsigned newval;\n\n    if (offset >= SPI_REG_SIZE) {\n        *data = 0;\n        return NULL;\n    }\n    if (op_type == MTS_READ)\n        *data = 0;\n    switch (offset & 0x1f0) {\n    case PIC32_SPI1CON & 0x1f0:         /* SPIx Control */\n         if (op_type == MTS_READ) {\n            *data = d->con;\n        } else {\n            d->con = write_op (d->con, *data, offset);\n            if (! (d->con & PIC32_SPICON_ON)) {\n                d->vm->clear_irq (d->vm, d->irq + IRQ_FAULT);\n                d->vm->clear_irq (d->vm, d->irq + IRQ_RX);\n                d->vm->clear_irq (d->vm, d->irq + IRQ_TX);\n                d->stat = PIC32_SPISTAT_SPITBE;\n            } else if (! (d->con & PIC32_SPICON_ENHBUF)) {\n                d->rfifo = 0;\n                d->wfifo = 0;\n            }\n        }\n        break;\n\n    case PIC32_SPI1STAT & 0x1f0:        /* SPIx Status */\n        if (op_type == MTS_READ) {\n            *data = d->stat;\n        } else {\n            /* Only ROV bit is writable. */\n            newval = write_op (d->stat, *data, offset);\n            d->stat = (d->stat & ~PIC32_SPISTAT_SPIROV) |\n                (newval & PIC32_SPISTAT_SPIROV);\n        }\n        break;\n\n    case PIC32_SPI1BUF & 0x1ff:         /* SPIx SPIx Buffer */\n        if (op_type == MTS_READ) {\n            *data = d->buf [d->rfifo];\n            if (d->con & PIC32_SPICON_ENHBUF) {\n                d->rfifo++;\n                d->rfifo &= 3;\n            }\n            if (d->stat & PIC32_SPISTAT_SPIRBF) {\n                d->stat &= ~PIC32_SPISTAT_SPIRBF;\n                //d->vm->clear_irq (d->vm, d->irq + IRQ_RX);\n            }\n        } else {\n            unsigned sdcard_port = d->pic32->sdcard_port;\n\n            /* Perform SD card i/o on configured SPI port. */\n            if ((dev->phys_addr == PIC32_SPI1CON && sdcard_port == 1) ||\n                (dev->phys_addr == PIC32_SPI2CON && sdcard_port == 2) ||\n                (dev->phys_addr == PIC32_SPI3CON && sdcard_port == 3) ||\n                (dev->phys_addr == PIC32_SPI4CON && sdcard_port == 4))\n            {\n                unsigned val = *data;\n\n                if (d->con & PIC32_SPICON_MODE32) {\n                    /* 32-bit data width */\n                    d->buf [d->wfifo] = (unsigned char) dev_sdcard_io (cpu, val >> 24) << 24;\n                    d->buf [d->wfifo] |= (unsigned char) dev_sdcard_io (cpu, val >> 16) << 16;\n                    d->buf [d->wfifo] |= (unsigned char) dev_sdcard_io (cpu, val >> 8) << 8;\n                    d->buf [d->wfifo] |= (unsigned char) dev_sdcard_io (cpu, val);\n\n                } else if (d->con & PIC32_SPICON_MODE16) {\n                    /* 16-bit data width */\n                    d->buf [d->wfifo] = (unsigned char) dev_sdcard_io (cpu, val >> 8) << 8;\n                    d->buf [d->wfifo] |= (unsigned char) dev_sdcard_io (cpu, val);\n\n                } else {\n                    /* 8-bit data width */\n                    d->buf [d->wfifo] = (unsigned char) dev_sdcard_io (cpu, val);\n                }\n            } else {\n                /* No device */\n                d->buf [d->wfifo] = ~0;\n            }\n            if (d->stat & PIC32_SPISTAT_SPIRBF) {\n                d->stat |= PIC32_SPISTAT_SPIROV;\n                //d->vm->set_irq (d->vm, d->irq + IRQ_FAULT);\n            } else if (d->con & PIC32_SPICON_ENHBUF) {\n                d->wfifo++;\n                d->wfifo &= 3;\n                if (d->wfifo == d->rfifo) {\n                    d->stat |= PIC32_SPISTAT_SPIRBF;\n                    //d->vm->set_irq (d->vm, d->irq + IRQ_RX);\n                }\n            } else {\n                d->stat |= PIC32_SPISTAT_SPIRBF;\n                //d->vm->set_irq (d->vm, d->irq + IRQ_RX);\n            }\n        }\n        break;\n\n    case PIC32_SPI1BRG & 0x1f0:         /* SPIx Baud rate */\n        if (op_type == MTS_READ) {\n            *data = d->brg;\n        } else {\n            d->brg = write_op (d->brg, *data, offset);\n        }\n        break;\n\n    default:\n        ASSERT (0, \"unknown spi offset %x\\n\", offset);\n    }\n    *has_set_value = TRUE;\n    return NULL;\n}\n\nvoid dev_pic32_spi_reset (cpu_mips_t *cpu, struct vdevice *dev)\n{\n    struct pic32_spi_data *d = dev->priv_data;\n\n    d->con = 0;\n    d->stat = PIC32_SPISTAT_SPITBE;             /* Transmit buffer is empty */\n    d->wfifo = 0;\n    d->rfifo = 0;\n    d->brg = 0;\n}\n\nint dev_pic32_spi_init (vm_instance_t *vm, char *name, unsigned paddr,\n    unsigned irq)\n{\n    struct pic32_spi_data *d;\n    pic32_t *pic32 = (pic32_t *) vm->hw_data;\n\n    /* allocate the private data structure */\n    d = malloc (sizeof (*d));\n    if (!d) {\n        fprintf (stderr, \"PIC32 SPI: unable to create device.\\n\");\n        return (-1);\n    }\n    memset (d, 0, sizeof (*d));\n    d->dev = dev_create (name);\n    if (! d->dev) {\n        free (d);\n        return (-1);\n    }\n    d->dev->priv_data = d;\n    d->dev->phys_addr = paddr;\n    d->dev->phys_len = SPI_REG_SIZE;\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n    d->vm = vm;\n    d->irq = irq;\n    d->pic32 = pic32;\n    d->dev->handler = dev_pic32_spi_access;\n    d->dev->reset_handler = dev_pic32_spi_reset;\n\n    vm_bind_device (vm, d->dev);\n    return (0);\n}\n"
  },
  {
    "path": "tools/virtualmips/pic32_dev_syscon.c",
    "content": "/*\n * System controller for PIC32.\n *\n * Copyright (C) 2011 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"cpu.h\"\n#include \"pic32.h\"\n\n#define SYSCON_REG_SIZE     0x1000\n\nextern cpu_mips_t *current_cpu;\n\nstatic int syskey_unlock;\n\nstatic void soft_reset (cpu_mips_t *cpu)\n{\n    pic32_t *pic32 = (pic32_t*) cpu->vm->hw_data;\n\n    mips_reset (cpu);\n    cpu->pc = pic32->start_address;\n\n    /* reset all devices */\n    dev_reset_all (cpu->vm);\n    dev_sdcard_reset (cpu);\n}\n\nvoid *dev_pic32_syscon_access (cpu_mips_t *cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type, m_reg_t *data,\n    m_uint8_t *has_set_value)\n{\n    pic32_t *pic32 = dev->priv_data;\n\n    if (offset >= SYSCON_REG_SIZE) {\n        *data = 0;\n        return NULL;\n    }\n    if (op_type == MTS_READ)\n        *data = 0;\n    switch (offset & 0xff0) {\n    case PIC32_OSCCON & 0xff0:\n        if (op_type == MTS_READ) {\n            *data = pic32->osccon;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        read OSCCON -> %08x\\n\", *data);\n        } else {\n            pic32->osccon = *data;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        OSCCON := %08x\\n\", *data);\n        }\n        break;\n\n    case PIC32_OSCTUN & 0xff0:\n        if (op_type == MTS_READ) {\n            *data = pic32->osctun;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        read OSCTUN -> %08x\\n\", *data);\n        } else {\n            pic32->osctun = *data;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        OSCTUN := %08x\\n\", *data);\n        }\n        break;\n\n    case PIC32_DDPCON & 0xff0:          /* Debug Data Port Control */\n        if (op_type == MTS_READ) {\n            *data = pic32->ddpcon;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        read DDPCON -> %08x\\n\", *data);\n        } else {\n            pic32->ddpcon = *data;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        DDPCON := %08x\\n\", *data);\n        }\n        break;\n\n    case PIC32_DEVID & 0xff0:           /* Device identifier */\n        /* read-only register */\n        if (op_type == MTS_READ) {\n            *data = pic32->devid;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        read DEVID -> %08x\\n\", *data);\n        }\n        break;\n\n    case PIC32_SYSKEY & 0xff0:\n        if (op_type == MTS_READ) {\n            *data = pic32->syskey;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        read SYSKEY -> %08x\\n\", *data);\n        } else {\n            pic32->syskey = *data;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        SYSKEY := %08x\\n\", *data);\n\n            /* Unlock state machine. */\n            switch (syskey_unlock) {\n            case 0:\n                if (pic32->syskey == 0xaa996655)\n                    syskey_unlock = 1;\n                else\n                    syskey_unlock = 0;\n                break;\n            case 1:\n                if (pic32->syskey == 0x556699aa)\n                    syskey_unlock = 2;\n                else\n                    syskey_unlock = 0;\n                break;\n            default:\n                syskey_unlock = 0;\n                break;\n            }\n        }\n        break;\n    case PIC32_RCON & 0xff0:\n        if (op_type == MTS_READ) {\n            *data = pic32->rcon;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        read RCON -> %08x\\n\", *data);\n        } else {\n            pic32->rcon = *data;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        RCON := %08x\\n\", *data);\n        }\n        break;\n    case PIC32_RSWRST & 0xff0:\n        if (op_type == MTS_READ) {\n            *data = pic32->rswrst;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        read RSWRST -> %08x\\n\", *data);\n        } else {\n            pic32->rswrst = *data;\n            if (cpu->vm->debug_level > 2)\n                printf (\"        RSWRST := %08x\\n\", *data);\n\n            if (syskey_unlock == 2 && (pic32->rswrst & 1))\n                soft_reset (cpu);\n        }\n        break;\n\n    default:\n        ASSERT (0, \"unknown syscon offset %x\\n\", offset);\n    }\n    *has_set_value = TRUE;\n    return NULL;\n}\n\nvoid dev_pic32_syscon_reset (cpu_mips_t *cpu, struct vdevice *dev)\n{\n    pic32_t *pic32 = dev->priv_data;\n\n    pic32->osccon = 0x01453320; /* from ubw32 board */\n    pic32->osctun = 0;\n    pic32->ddpcon = 0;\n    pic32->devid = 0x04307053;  /* 795F512L */\n    pic32->syskey = 0;\n    pic32->rcon = 0;\n    pic32->rswrst = 0;\n    syskey_unlock = 0;\n}\n\nint dev_pic32_syscon_init (vm_instance_t *vm, char *name, unsigned paddr)\n{\n    pic32_t *pic32 = (pic32_t *) vm->hw_data;\n\n    pic32->sysdev = dev_create (name);\n    if (! pic32->sysdev)\n        return (-1);\n    pic32->sysdev->priv_data = pic32;\n    pic32->sysdev->phys_addr = paddr;\n    pic32->sysdev->phys_len = SYSCON_REG_SIZE;\n    pic32->sysdev->handler = dev_pic32_syscon_access;\n    pic32->sysdev->reset_handler = dev_pic32_syscon_reset;\n    pic32->sysdev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n\n    vm_bind_device (vm, pic32->sysdev);\n    return (0);\n}\n"
  },
  {
    "path": "tools/virtualmips/pic32_dev_timer.c",
    "content": "/*\n * Timer emulation for PIC32.\n *\n * Copyright (C) 2012 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"pic32.h\"\n#include \"cpu.h\"\n#include \"vp_timer.h\"\n#include \"dev_sdcard.h\"\n\n#define TIMER_REG_SIZE    0x30\n\nstruct pic32_timer_data {\n    struct vdevice  *dev;\n    vm_instance_t   *vm;\n    pic32_t         *pic32;\n\n    unsigned        irq;            /* irq number */\n    unsigned        con;            /* 0x00 - Control */\n    unsigned        count;          /* 0x10 - Count */\n    unsigned        period;         /* 0x20 - Period */\n    unsigned        scale;          /* prescale value */\n};\n\nextern cpu_mips_t *current_cpu;\n\nstatic const int timer_scale[8] = {\n    1,  2,  4,  8,  16, 32, 64, 256,\n};\n\n/*\n * Perform an assign/clear/set/invert operation.\n */\nstatic inline unsigned write_op (int a, int b, int op)\n{\n    switch (op & 0xc) {\n    case 0x0:           /* Assign */\n        a = b;\n        break;\n    case 0x4:           /* Clear */\n        a &= ~b;\n        break;\n    case 0x8:           /* Set */\n        a |= b;\n        break;\n    case 0xc:           /* Invert */\n        a ^= b;\n        break;\n    }\n    return a;\n}\n\nvoid *dev_pic32_timer_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type,\n    m_reg_t * data, m_uint8_t * has_set_value)\n{\n    struct pic32_timer_data *d = dev->priv_data;\n    unsigned newval;\n\n    if (offset >= TIMER_REG_SIZE) {\n        *data = 0;\n        return NULL;\n    }\n    if (op_type == MTS_READ)\n        *data = 0;\n    switch (offset & 0x1f0) {\n    case PIC32_T1CON & 0x1f0:           /* Timer control */\n         if (op_type == MTS_READ) {\n            *data = d->con;\nfprintf (stderr, \"%s read TCON -> %04x\\n\", dev->name, d->con);\n        } else {\n            d->con = write_op (d->con, *data, offset);\n            d->scale = timer_scale [(d->con >> 4) & 7];\nfprintf (stderr, \"%s write TCON %04x\\n\", dev->name, d->con);\n            if (! (d->con & PIC32_TCON_ON)) {\n                d->vm->clear_irq (d->vm, d->irq);\n                d->count = 0;\n            }\n        }\n        break;\n\n    case PIC32_TMR1 & 0x1f0:            /* Timer count */\n        if (op_type == MTS_READ) {\n            *data = d->count / d->scale;\nfprintf (stderr, \"%s read TMR -> %04x\\n\", dev->name, d->count / d->scale);\n        } else {\n            newval = write_op (d->count / d->scale, *data, offset);\nfprintf (stderr, \"%s write TMR %04x\\n\", dev->name, newval);\n            d->count = newval * d->scale;\n        }\n        break;\n\n    case PIC32_PR1 & 0x1ff:             /* Timer period */\n        if (op_type == MTS_READ) {\n            *data = d->period;\nfprintf (stderr, \"%s read PR -> %04x\\n\", dev->name, d->period);\n            //d->vm->clear_irq (d->vm, d->irq);\n        } else {\n            newval = write_op (d->period, *data, offset);\nfprintf (stderr, \"%s write PR %04x\\n\", dev->name, newval);\n            d->period = newval;\n            //d->vm->set_irq (d->vm, d->irq);\n        }\n        break;\n\n    default:\n        ASSERT (0, \"unknown timer offset %x\\n\", offset);\n    }\n    *has_set_value = TRUE;\n    return NULL;\n}\n\n/*\n * Increment timer counter.\n * Fire periodic interrupt.\n */\nvoid dev_pic32_timer_tick (cpu_mips_t *cpu, struct vdevice *dev, unsigned nclocks)\n{\n    struct pic32_timer_data *d = dev->priv_data;\n\n    /* Check that timer is enabled. */\n    if (! (d->con & PIC32_TCON_ON) || d->period == 0)\n        return;\n\n    /* Update counter and check overflow. */\n    d->count += nclocks;\n    if (d->count < d->period * d->scale)\n        return;\n\n    /* Counter matched. */\n    d->count %= d->period * d->scale;\n    pic32_set_irq (cpu->vm, d->irq);\nfprintf (stderr, \"%s irq %u\\n\", dev->name, d->irq);\n}\n\nvoid dev_pic32_timer_reset (cpu_mips_t *cpu, struct vdevice *dev)\n{\n    struct pic32_timer_data *d = dev->priv_data;\n\n    d->con = 0;\n    d->count = 0;\n    d->period = 0;\n    d->scale = 1;\n    pic32_clear_irq (cpu->vm, d->irq);\n}\n\nstruct vdevice *dev_pic32_timer_init (vm_instance_t *vm, char *name,\n    unsigned paddr, unsigned irq)\n{\n    struct pic32_timer_data *d;\n    pic32_t *pic32 = (pic32_t *) vm->hw_data;\n\n    /* allocate the private data structure */\n    d = malloc (sizeof (*d));\n    if (!d) {\n        fprintf (stderr, \"PIC32 timer: unable to create device.\\n\");\n        return 0;\n    }\n    memset (d, 0, sizeof (*d));\n    d->dev = dev_create (name);\n    if (! d->dev) {\n        free (d);\n        return 0;\n    }\n    d->dev->priv_data = d;\n    d->dev->phys_addr = paddr;\n    d->dev->phys_len = TIMER_REG_SIZE;\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n    d->vm = vm;\n    d->irq = irq;\n    d->pic32 = pic32;\n    d->dev->handler = dev_pic32_timer_access;\n    d->dev->reset_handler = dev_pic32_timer_reset;\n\n    vm_bind_device (vm, d->dev);\n    return d->dev;\n}\n"
  },
  {
    "path": "tools/virtualmips/pic32_dev_uart.c",
    "content": "/*\n * UART emulation for PIC32.\n *\n * Copyright (C) 2011 Serge Vakulenko <serge@vak.ru>\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n */\n#define _GNU_SOURCE\n#include <stdlib.h>\n#include <stdio.h>\n#include <assert.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <string.h>\n\n#include \"device.h\"\n#include \"mips_memory.h\"\n#include \"pic32.h\"\n#include \"cpu.h\"\n#include \"vp_timer.h\"\n\n#define UART_REG_SIZE     0x50\n#define UART_TIME_OUT     1\n\nstruct pic32_uart_data {\n    struct vdevice  *dev;\n    vtty_t          *vtty;\n    vm_instance_t   *vm;\n    vp_timer_t      *uart_timer;\n\n    u_int           output;\n    u_int           irq;            /* base irq number */\n#define IRQ_ERR     0               /* error interrupt */\n#define IRQ_RX      1               /* receiver interrupt */\n#define IRQ_TX      2               /* transmitter interrupt */\n\n    m_uint32_t      mode;           /* 0x00 - mode */\n    m_uint32_t      sta;            /* 0x10 - status and control */\n    m_uint32_t      txreg;          /* 0x20 - transmit */\n    m_uint32_t      rxreg;          /* 0x30 - receive */\n    m_uint32_t      brg;            /* 0x40 - baud rate */\n};\n\nextern cpu_mips_t *current_cpu;\n\nstatic void pic32_tty_con_input (vtty_t * vtty)\n{\n    struct pic32_uart_data *d = vtty->priv_data;\n\n    if (d->mode & PIC32_UMODE_ON) {\n        /* UART enabled. */\n        if (d->sta & PIC32_USTA_URXEN) {\n            /* Receiver enabled - activate interrupt. */\n            d->vm->set_irq (d->vm, d->irq + IRQ_RX);\n\n            /* Receive data available */\n            d->sta |= PIC32_USTA_URXDA;\n        }\n    }\n}\n\nvoid *dev_pic32_uart_access (cpu_mips_t * cpu, struct vdevice *dev,\n    m_uint32_t offset, u_int op_size, u_int op_type,\n    m_reg_t * data, m_uint8_t * has_set_value)\n{\n    struct pic32_uart_data *d = dev->priv_data;\n    unsigned newval;\n\n    if (offset >= UART_REG_SIZE) {\n        *data = 0;\n        return NULL;\n    }\n    if (op_type == MTS_READ) {\n        /*\n         * Reading UART registers.\n         */\n        switch (offset) {\n        case PIC32_U1RXREG & 0xff:              /* Receive data */\n            *data = vtty_get_char (d->vtty);\n            if (vtty_is_char_avail (d->vtty)) {\n                d->sta |= PIC32_USTA_URXDA;\n            } else {\n                d->sta &= ~PIC32_USTA_URXDA;\n                d->vm->clear_irq (d->vm, d->irq + IRQ_RX);\n            }\n            break;\n\n        case PIC32_U1BRG & 0xff:                /* Baud rate */\n            *data = d->brg;\n            break;\n\n        case PIC32_U1MODE & 0xff:               /* Mode */\n            *data = d->mode;\n            break;\n\n        case PIC32_U1STA & 0xff:                /* Status and control */\n            d->sta |= PIC32_USTA_RIDLE |        /* Receiver is idle */\n                PIC32_USTA_TRMT;                /* Transmit shift register is empty */\n            if (vtty_is_char_avail (d->vtty))\n                d->sta |= PIC32_USTA_URXDA;\n            *data = d->sta;\n#if 0\n            printf (\"<%x>\", d->sta);\n            fflush (stdout);\n#endif\n            break;\n\n        case PIC32_U1TXREG & 0xff:              /* Transmit */\n        case PIC32_U1MODECLR & 0xff:\n        case PIC32_U1MODESET & 0xff:\n        case PIC32_U1MODEINV & 0xff:\n        case PIC32_U1STACLR & 0xff:\n        case PIC32_U1STASET & 0xff:\n        case PIC32_U1STAINV & 0xff:\n        case PIC32_U1BRGCLR & 0xff:\n        case PIC32_U1BRGSET & 0xff:\n        case PIC32_U1BRGINV & 0xff:\n            *data = 0;\n            break;\n\n        default:\n            ASSERT (0, \"reading unknown uart offset %x\\n\", offset);\n        }\n        *has_set_value = TRUE;\n#if 0\n        printf (\"--- uart: read %02x -> %08x\\n\", offset, *data);\n        fflush (stdout);\n#endif\n    } else {\n        /*\n         * Writing UART registers.\n         */\n#if 0\n        printf (\"--- uart: write %02x := %08x\\n\", offset, *data);\n        fflush (stdout);\n#endif\n        switch (offset) {\n        case PIC32_U1TXREG & 0xff:              /* Transmit */\n            /* Don't skip ^M. */\n            vtty_put_char (d->vtty, (char) (*data));\n\n            if ((d->mode & PIC32_UMODE_ON) &&\n                (d->sta & PIC32_USTA_UTXEN) && (d->output == 0)) {\n                /*\n                 * yajin.\n                 *\n                 * In order to put the next data more quickly,\n                 * just set irq not waiting for\n                 * host_alarm_handler to set irq. Sorry uart,\n                 * too much work for you.\n                 *\n                 * Sometimes, linux kernel prints \"serial8250:\n                 * too much work for irq9\" if we print large\n                 * data on screen. Please patch the kernel.\n                 * comment \"printk(KERN_ERR \"serial8250: too\n                 * much work for \" \"irq%d\\n\", irq);\" qemu has\n                 * some question.\n                 * http://lkml.org/lkml/2008/1/12/135\n                 * http://kerneltrap.org/mailarchive/linux-ker\n                 * nel/2008/2/7/769924\n                 *\n                 * If jit is used in future, we may not need to\n                 * set irq here because simulation is quick\n                 * enough. Then we have no \"too much work for\n                 * irq9\" problem.\n                 */\n                d->output = TRUE;\n                d->vm->set_irq (d->vm, d->irq + IRQ_TX);\n            }\n            break;\n\n        case PIC32_U1MODE & 0xff:               /* Mode */\n            newval = *data;\nwrite_mode:\n            d->mode = newval;\n            if (!(d->mode & PIC32_UMODE_ON)) {\n                d->vm->clear_irq (d->vm, d->irq + IRQ_RX);\n                d->vm->clear_irq (d->vm, d->irq + IRQ_TX);\n                d->sta &= ~PIC32_USTA_URXDA;\n                d->sta &= ~(PIC32_USTA_URXDA | PIC32_USTA_FERR |\n                    PIC32_USTA_PERR | PIC32_USTA_UTXBF);\n                d->sta |= PIC32_USTA_RIDLE | PIC32_USTA_TRMT;\n            }\n            break;\n        case PIC32_U1MODECLR & 0xff:\n            newval = d->mode & ~*data;\n            goto write_mode;\n        case PIC32_U1MODESET & 0xff:\n            newval = d->mode | *data;\n            goto write_mode;\n        case PIC32_U1MODEINV & 0xff:\n            newval = d->mode ^ *data;\n            goto write_mode;\n\n        case PIC32_U1STA & 0xff:                /* Status and control */\n            newval = *data;\nwrite_sta:\n            d->sta &= PIC32_USTA_URXDA | PIC32_USTA_FERR |\n                PIC32_USTA_PERR | PIC32_USTA_RIDLE |\n                PIC32_USTA_TRMT | PIC32_USTA_UTXBF;\n            d->sta |= newval & ~(PIC32_USTA_URXDA | PIC32_USTA_FERR |\n                PIC32_USTA_PERR | PIC32_USTA_RIDLE |\n                PIC32_USTA_TRMT | PIC32_USTA_UTXBF);\n            if (!(d->sta & PIC32_USTA_URXEN)) {\n                d->vm->clear_irq (d->vm, d->irq + IRQ_RX);\n                d->sta &= ~(PIC32_USTA_URXDA | PIC32_USTA_FERR |\n                    PIC32_USTA_PERR);\n            }\n            if (!(d->sta & PIC32_USTA_UTXEN)) {\n                d->vm->clear_irq (d->vm, d->irq + IRQ_TX);\n                d->sta &= ~PIC32_USTA_UTXBF;\n                d->sta |= PIC32_USTA_TRMT;\n            }\n            break;\n        case PIC32_U1STACLR & 0xff:\n            newval = d->sta & ~*data;\n            goto write_sta;\n        case PIC32_U1STASET & 0xff:\n            newval = d->sta | *data;\n            goto write_sta;\n        case PIC32_U1STAINV & 0xff:\n            newval = d->sta ^ *data;\n            goto write_sta;\n\n        case PIC32_U1BRG & 0xff:                /* Baud rate */\n            newval = *data;\nwrite_brg:\n            d->brg = newval;\n            break;\n        case PIC32_U1BRGCLR & 0xff:\n            newval = d->brg & ~*data;\n            goto write_brg;\n        case PIC32_U1BRGSET & 0xff:\n            newval = d->brg | *data;\n            goto write_brg;\n        case PIC32_U1BRGINV & 0xff:\n            newval = d->brg ^ *data;\n            goto write_brg;\n\n        case PIC32_U1RXREG & 0xff:              /* Receive */\n            /* Ignore */\n            break;\n\n        default:\n            ASSERT (0, \"writing unknown uart offset %x\\n\", offset);\n        }\n        *has_set_value = TRUE;\n    }\n    return NULL;\n}\n\nvoid dev_pic32_uart_reset (cpu_mips_t * cpu, struct vdevice *dev)\n{\n    struct pic32_uart_data *d = dev->priv_data;\n\n    d->mode = 0;\n    d->sta = PIC32_USTA_RIDLE |         /* Receiver is idle */\n        PIC32_USTA_TRMT;                /* Transmit shift register is empty */\n    d->txreg = 0;\n    d->rxreg = 0;\n    d->brg = 0;\n}\n\nvoid dev_pic32_uart_cb (void *opaque)\n{\n    struct pic32_uart_data *d = (struct pic32_uart_data *) opaque;\n\n    d->output = 0;\n    if (d->mode & PIC32_UMODE_ON) {\n        /* UART enabled. */\n        if ((d->sta & PIC32_USTA_URXEN) && vtty_is_char_avail (d->vtty)) {\n            /* Receive data available */\n            d->sta |= PIC32_USTA_URXDA;\n\n            /* Activate receive interrupt. */\n            d->vm->set_irq (d->vm, d->irq + IRQ_RX);\n            vp_mod_timer (d->uart_timer,\n                vp_get_clock (rt_clock) + UART_TIME_OUT);\n            return;\n        }\n        if ((d->sta & PIC32_USTA_UTXEN) && (d->output == 0)) {\n            /* Activate transmit interrupt. */\n            d->output = TRUE;\n            d->vm->set_irq (d->vm, d->irq + IRQ_TX);\n            vp_mod_timer (d->uart_timer,\n                vp_get_clock (rt_clock) + UART_TIME_OUT);\n            return;\n        }\n    }\n    vp_mod_timer (d->uart_timer, vp_get_clock (rt_clock) + UART_TIME_OUT);\n}\n\nint dev_pic32_uart_init (vm_instance_t *vm, char *name, unsigned paddr,\n    unsigned irq, vtty_t *vtty)\n{\n    struct pic32_uart_data *d;\n\n    /* allocate the private data structure */\n    d = malloc (sizeof (*d));\n    if (!d) {\n        fprintf (stderr, \"PIC32 UART: unable to create device.\\n\");\n        return (-1);\n    }\n    memset (d, 0, sizeof (*d));\n    d->dev = dev_create (name);\n    if (!d->dev) {\n        free (d);\n        return (-1);\n    }\n    d->dev->priv_data = d;\n    d->dev->phys_addr = paddr;\n    d->dev->phys_len = UART_REG_SIZE;\n    d->dev->flags = VDEVICE_FLAG_NO_MTS_MMAP;\n    d->vm = vm;\n    (*d).vtty = vtty;\n    d->irq = irq;\n    vtty->priv_data = d;\n    d->dev->handler = dev_pic32_uart_access;\n    d->dev->reset_handler = dev_pic32_uart_reset;\n    (*d).vtty->read_notifier = pic32_tty_con_input;\n    d->uart_timer = vp_new_timer (rt_clock, dev_pic32_uart_cb, d);\n\n    vp_mod_timer (d->uart_timer, vp_get_clock (rt_clock) + UART_TIME_OUT);\n\n    vm_bind_device (vm, d->dev);\n    return (0);\n}\n"
  },
  {
    "path": "tools/virtualmips/pic32_explorer16.conf",
    "content": "#\n# Configure file for Explorer16 board\n#\ngdb_debug           = 0\ngdb_port            = 5555\n\n#\n# Data memory\n#\nram_size            = 128               # kbytes\n\n#\n# Program flash\n#\nflash_size          = 492               # kbytes\nflash_phy_address   = 0x1d000000\nflash_file_name     = ../../sys/arch/pic32/compile/EXPLORER16/unix.bin\n\n#\n# Boot flash\n#\nboot_flash_size     = 12                # kbytes\nboot_flash_address  = 0x1fc00000\nboot_file_name     = ../../sys/arch/pic32/compile/EXPLORER16/boot.bin\n\nstart_address       = 0x9fc00000        # user program\n\n#\n# SD/MMC cards\n#\nsdcard_port         = 1                 # SPI1\nsdcard0_size        = 512               # Mbytes\nsdcard0_file_name   = ../../distrib/pic32/sdcard.img\n\n#\n# UARTs 1..6\n#\nuart1_type          = none\nuart2_type          = console\n\n#\n# Debug level:\n# 0 - quiet\n# 1 - trace system calls and exceptions\n# 2 - trace inctructions in user mode\n# 3 - trace all inctructions\n#\ndebug_level         = 0\n#trace_address      = 0x9d00720c\n"
  },
  {
    "path": "tools/virtualmips/pic32_max32.conf",
    "content": "#\n# Configure file for MAX32\n#\ngdb_debug           = 0\ngdb_port            = 5555\n\n#\n# Data memory\n#\nram_size            = 128               # kbytes\n\n#\n# Program flash\n#\nflash_size          = 492               # kbytes\nflash_phy_address   = 0x1d000000\nflash_file_name     = ../../sys/arch/pic32/compile/MAX32/unix.bin\n\nstart_address       = 0x9d001000        # user program\n\n#\n# SD/MMC cards\n#\nsdcard_port         = 2                 # SPI2\nsdcard0_size        = 512               # Mbytes\nsdcard0_file_name   = ../../distrib/pic32/sdcard.img\n\n#\n# UARTs 1..6\n#\nuart1_type          = console\n\n#\n# Debug level:\n# 0 - quiet\n# 1 - trace system calls and exceptions\n# 2 - trace inctructions in user mode\n# 3 - trace all inctructions\n#\ndebug_level         = 0\n#trace_address      = 0x9d00720c\n"
  },
  {
    "path": "tools/virtualmips/pic32_maximite.conf",
    "content": "#\n# Configure file for Maximite\n#\ngdb_debug           = 0\ngdb_port            = 5555\n\n#\n# Data memory\n#\nram_size            = 128               # kbytes\n\n#\n# Program flash\n#\nflash_size          = 492               # kbytes\nflash_phy_address   = 0x1d005000\nflash_file_name     = ../../sys/arch/pic32/compile/MAXIMITE/unix.bin\n\nstart_address       = 0x9d006000        # user program\n\n#\n# SD/MMC cards\n#\nsdcard_port         = 4                 # SPI4\nsdcard0_size        = 512               # Mbytes\nsdcard0_file_name   = ../../distrib/pic32/sdcard.img\n\n#\n# UARTs 1..6\n#\nuart1_type          = none\nuart4_type          = console\n\n#\n# Debug level:\n# 0 - quiet\n# 1 - trace system calls and exceptions\n# 2 - trace inctructions in user mode\n# 3 - trace all inctructions\n#\ndebug_level         = 0\n#trace_address      = 0x9d00720c\n"
  },
  {
    "path": "tools/virtualmips/pic32_ubw32.conf",
    "content": "#\n# Configure file for UBW32\n#\ngdb_debug           = 0\ngdb_port            = 5555\n\n#\n# Data memory\n#\nram_size            = 128               # kbytes\n\n#\n# Program flash\n#\nflash_size          = 492               # kbytes\nflash_phy_address   = 0x1d005000\nflash_file_name     = ../../sys/arch/pic32/compile/UBW32/unix.bin\n\nstart_address       = 0x9d006000        # user program\n\n#\n# SD/MMC cards\n#\nsdcard_port         = 1                 # SPI1\nsdcard0_size        = 512               # Mbytes\nsdcard0_file_name   = ../../distrib/pic32/sdcard.img\n#sdcard1_size       = 2                 # Mbytes\n#sdcard1_file_name  = ../../home.img\n\n#\n# UARTs 1..6\n#\nuart1_type           = console\n\n#uart1_type          = tcp\n#uart1_port          = 2302\n#uart2_type          = tcp\n#uart2_port          = 2302\n#uart3_type          = tcp\n#uart3_port          = 2303\n#uart4_type          = tcp\n#uart4_port          = 2304\n#uart5_type          = tcp\n#uart5_port          = 2305\n#uart6_type          = tcp\n#uart6_port          = 2306\n\n#\n# Debug level:\n# 0 - quiet\n# 1 - trace system calls and exceptions\n# 2 - trace inctructions in user mode\n# 3 - trace all inctructions\n#\ndebug_level         = 0\n#trace_address       = 0x9d00720c\n"
  },
  {
    "path": "tools/virtualmips/pic32mx.h",
    "content": "/*\n * Hardware register defines for Microchip PIC32MX microcontrollers.\n *\n * Copyright (C) 2010 Serge Vakulenko, <serge@vak.ru>\n *\n * Permission to use, copy, modify, and distribute this software\n * and its documentation for any purpose and without fee is hereby\n * granted, provided that the above copyright notice appear in all\n * copies and that both that the copyright notice and this\n * permission notice and warranty disclaimer appear in supporting\n * documentation, and that the name of the author not be used in\n * advertising or publicity pertaining to distribution of the\n * software without specific, written prior permission.\n *\n * The author disclaim all warranties with regard to this\n * software, including all implied warranties of merchantability\n * and fitness.  In no event shall the author be liable for any\n * special, indirect or consequential damages or any damages\n * whatsoever resulting from loss of use, data or profits, whether\n * in an action of contract, negligence or other tortious action,\n * arising out of or in connection with the use or performance of\n * this software.\n */\n#ifndef _IO_PIC32MX_H\n#define _IO_PIC32MX_H\n\n/*--------------------------------------\n * Peripheral registers.\n */\n#define PIC32_R(a)              (0x1F800000 + (a))\n\n/*--------------------------------------\n * Interrupt controller registers.\n */\n#define PIC32_INTCON\tPIC32_R (0x81000)           /* Interrupt Control */\n#define PIC32_INTCONCLR\tPIC32_R (0x81004)\n#define PIC32_INTCONSET\tPIC32_R (0x81008)\n#define PIC32_INTCONINV\tPIC32_R (0x8100C)\n#define PIC32_INTSTAT\tPIC32_R (0x81010)           /* Interrupt Status */\n#define PIC32_IPTMR\t\tPIC32_R (0x81020)           /* Temporal Proximity Timer */\n#define PIC32_IPTMRCLR\tPIC32_R (0x81024)\n#define PIC32_IPTMRSET\tPIC32_R (0x81028)\n#define PIC32_IPTMRINV\tPIC32_R (0x8102C)\n#define PIC32_IFS(n)\tPIC32_R (0x81030+((n)<<4))  /* IFS(0..2) - Interrupt Flag Status */\n#define PIC32_IFSCLR(n)\tPIC32_R (0x81034+((n)<<4))\n#define PIC32_IFSSET(n)\tPIC32_R (0x81038+((n)<<4))\n#define PIC32_IFSINV(n)\tPIC32_R (0x8103C+((n)<<4))\n#define PIC32_IEC(n)\tPIC32_R (0x81060+((n)<<4))  /* IEC(0..2) - Interrupt Enable Control */\n#define PIC32_IECCLR(n)\tPIC32_R (0x81064+((n)<<4))\n#define PIC32_IECSET(n)\tPIC32_R (0x81068+((n)<<4))\n#define PIC32_IECINV(n)\tPIC32_R (0x8106C+((n)<<4))\n#define PIC32_IPC(n)\tPIC32_R (0x81090+((n)<<4))  /* IPC(0..12) - Interrupt Priority Control */\n#define PIC32_IPCCLR(n)\tPIC32_R (0x81094+((n)<<4))\n#define PIC32_IPCSET(n)\tPIC32_R (0x81098+((n)<<4))\n#define PIC32_IPCINV(n)\tPIC32_R (0x8109C+((n)<<4))\n\n/*\n * Interrupt Control register.\n */\n#define PIC32_INTCON_INT0EP\t0x0001      /* External interrupt 0 polarity rising edge */\n#define PIC32_INTCON_INT1EP\t0x0002      /* External interrupt 1 polarity rising edge */\n#define PIC32_INTCON_INT2EP\t0x0004      /* External interrupt 2 polarity rising edge */\n#define PIC32_INTCON_INT3EP\t0x0008      /* External interrupt 3 polarity rising edge */\n#define PIC32_INTCON_INT4EP\t0x0010      /* External interrupt 4 polarity rising edge */\n#define PIC32_INTCON_TPC(x)\t((x)<<8)    /* Temporal proximity group priority */\n#define PIC32_INTCON_MVEC\t0x1000      /* Multi-vectored mode */\n#define PIC32_INTCON_FRZ\t0x4000      /* Freeze in debug mode */\n#define PIC32_INTCON_SS0\t0x8000      /* Single vector has a shadow register set */\n\n/*\n * Interrupt Status register.\n */\n#define PIC32_INTSTAT_VEC(s)\t((s) & 0xFF)\t/* Interrupt vector */\n#define PIC32_INTSTAT_SRIPL(s)\t((s) >> 8 & 7)\t/* Requested priority level */\n\n/*\n * Interrupt Prority Control register.\n */\n#define PIC32_IPC_IS0(x)\t(x)         /* Interrupt 0 subpriority */\n#define PIC32_IPC_IP0(x)\t((x)<<2)\t/* Interrupt 0 priority */\n#define PIC32_IPC_IS1(x)\t((x)<<8)\t/* Interrupt 1 subpriority */\n#define PIC32_IPC_IP1(x)\t((x)<<10)\t/* Interrupt 1 priority */\n#define PIC32_IPC_IS2(x)\t((x)<<16)\t/* Interrupt 2 subpriority */\n#define PIC32_IPC_IP2(x)\t((x)<<18)\t/* Interrupt 2 priority */\n#define PIC32_IPC_IS3(x)\t((x)<<24)\t/* Interrupt 3 subpriority */\n#define PIC32_IPC_IP3(x)\t((x)<<26)\t/* Interrupt 3 priority */\n\n/*\n * IRQ numbers for PIC32MX3xx/4xx/5xx/6xx/7xx.\n */\n#define PIC32_IRQ_CT        0   /* Core Timer Interrupt */\n#define PIC32_IRQ_CS0       1   /* Core Software Interrupt 0 */\n#define PIC32_IRQ_CS1       2   /* Core Software Interrupt 1 */\n#define PIC32_IRQ_INT0      3   /* External Interrupt 0 */\n#define PIC32_IRQ_T1        4   /* Timer1 */\n#define PIC32_IRQ_IC1       5   /* Input Capture 1 */\n#define PIC32_IRQ_OC1       6   /* Output Compare 1 */\n#define PIC32_IRQ_INT1      7   /* External Interrupt 1 */\n#define PIC32_IRQ_T2        8   /* Timer2 */\n#define PIC32_IRQ_IC2       9   /* Input Capture 2 */\n#define PIC32_IRQ_OC2       10  /* Output Compare 2 */\n#define PIC32_IRQ_INT2      11  /* External Interrupt 2 */\n#define PIC32_IRQ_T3        12  /* Timer3 */\n#define PIC32_IRQ_IC3       13  /* Input Capture 3 */\n#define PIC32_IRQ_OC3       14  /* Output Compare 3 */\n#define PIC32_IRQ_INT3      15  /* External Interrupt 3 */\n#define PIC32_IRQ_T4        16  /* Timer4 */\n#define PIC32_IRQ_IC4       17  /* Input Capture 4 */\n#define PIC32_IRQ_OC4       18  /* Output Compare 4 */\n#define PIC32_IRQ_INT4      19  /* External Interrupt 4 */\n#define PIC32_IRQ_T5        20  /* Timer5 */\n#define PIC32_IRQ_IC5       21  /* Input Capture 5 */\n#define PIC32_IRQ_OC5       22  /* Output Compare 5 */\n#define PIC32_IRQ_SPI1E     23  /* SPI1 Fault */\n#define PIC32_IRQ_SPI1TX    24  /* SPI1 Transfer Done */\n#define PIC32_IRQ_SPI1RX    25  /* SPI1 Receive Done */\n\n#define PIC32_IRQ_SPI3E     26  /* SPI3 Fault */\n#define PIC32_IRQ_SPI3TX    27  /* SPI3 Transfer Done */\n#define PIC32_IRQ_SPI3RX    28  /* SPI3 Receive Done */\n#define PIC32_IRQ_U1E       26  /* UART1 Error */\n#define PIC32_IRQ_U1RX      27  /* UART1 Receiver */\n#define PIC32_IRQ_U1TX      28  /* UART1 Transmitter */\n#define PIC32_IRQ_I2C3B     26  /* I2C3 Bus Collision Event */\n#define PIC32_IRQ_I2C3S     27  /* I2C3 Slave Event */\n#define PIC32_IRQ_I2C3M     28  /* I2C3 Master Event */\n\n#define PIC32_IRQ_I2C1B     29  /* I2C1 Bus Collision Event */\n#define PIC32_IRQ_I2C1S     30  /* I2C1 Slave Event */\n#define PIC32_IRQ_I2C1M     31  /* I2C1 Master Event */\n#define PIC32_IRQ_CN        32  /* Input Change Interrupt */\n#define PIC32_IRQ_AD1       33  /* ADC1 Convert Done */\n#define PIC32_IRQ_PMP       34  /* Parallel Master Port */\n#define PIC32_IRQ_CMP1      35  /* Comparator Interrupt */\n#define PIC32_IRQ_CMP2      36  /* Comparator Interrupt */\n\n#define PIC32_IRQ_SPI2E     37  /* SPI2 Fault */\n#define PIC32_IRQ_SPI2TX    38  /* SPI2 Transfer Done */\n#define PIC32_IRQ_SPI2RX    39  /* SPI2 Receive Done */\n#define PIC32_IRQ_U3E       37  /* UART3 Error */\n#define PIC32_IRQ_U3RX      38  /* UART3 Receiver */\n#define PIC32_IRQ_U3TX      39  /* UART3 Transmitter */\n#define PIC32_IRQ_I2C4B     37  /* I2C4 Bus Collision Event */\n#define PIC32_IRQ_I2C4S     38  /* I2C4 Slave Event */\n#define PIC32_IRQ_I2C4M     39  /* I2C4 Master Event */\n\n#define PIC32_IRQ_SPI4E     40  /* SPI4 Fault */\n#define PIC32_IRQ_SPI4TX    41  /* SPI4 Transfer Done */\n#define PIC32_IRQ_SPI4RX    42  /* SPI4 Receive Done */\n#define PIC32_IRQ_U2E       40  /* UART2 Error */\n#define PIC32_IRQ_U2RX      41  /* UART2 Receiver */\n#define PIC32_IRQ_U2TX      42  /* UART2 Transmitter */\n#define PIC32_IRQ_I2C5B     40  /* I2C5 Bus Collision Event */\n#define PIC32_IRQ_I2C5S     41  /* I2C5 Slave Event */\n#define PIC32_IRQ_I2C5M     42  /* I2C5 Master Event */\n\n#define PIC32_IRQ_I2C2B     43  /* I2C2 Bus Collision Event */\n#define PIC32_IRQ_I2C2S     44  /* I2C2 Slave Event */\n#define PIC32_IRQ_I2C2M     45  /* I2C2 Master Event */\n#define PIC32_IRQ_FSCM      46  /* Fail-Safe Clock Monitor */\n#define PIC32_IRQ_RTCC      47  /* Real-Time Clock and Calendar */\n#define PIC32_IRQ_DMA0      48  /* DMA Channel 0 */\n#define PIC32_IRQ_DMA1      49  /* DMA Channel 1 */\n#define PIC32_IRQ_DMA2      50  /* DMA Channel 2 */\n#define PIC32_IRQ_DMA3      51  /* DMA Channel 3 */\n#define PIC32_IRQ_DMA4      52  /* DMA Channel 4 */\n#define PIC32_IRQ_DMA5      53  /* DMA Channel 5 */\n#define PIC32_IRQ_DMA6      54  /* DMA Channel 6 */\n#define PIC32_IRQ_DMA7      55  /* DMA Channel 7 */\n#define PIC32_IRQ_FCE       56  /* Flash Control Event */\n#define PIC32_IRQ_USB       57  /* USB */\n#define PIC32_IRQ_CAN1      58  /* Control Area Network 1 */\n#define PIC32_IRQ_CAN2      59  /* Control Area Network 2 */\n#define PIC32_IRQ_ETH       60  /* Ethernet Interrupt */\n#define PIC32_IRQ_IC1E      61  /* Input Capture 1 Error */\n#define PIC32_IRQ_IC2E      62  /* Input Capture 2 Error */\n#define PIC32_IRQ_IC3E      63  /* Input Capture 3 Error */\n#define PIC32_IRQ_IC4E      64  /* Input Capture 4 Error */\n#define PIC32_IRQ_IC5E      65  /* Input Capture 5 Error */\n#define PIC32_IRQ_PMPE      66  /* Parallel Master Port Error */\n#define PIC32_IRQ_U4E       67  /* UART4 Error */\n#define PIC32_IRQ_U4RX      68  /* UART4 Receiver */\n#define PIC32_IRQ_U4TX      69  /* UART4 Transmitter */\n#define PIC32_IRQ_U6E       70  /* UART6 Error */\n#define PIC32_IRQ_U6RX      71  /* UART6 Receiver */\n#define PIC32_IRQ_U6TX      72  /* UART6 Transmitter */\n#define PIC32_IRQ_U5E       73  /* UART5 Error */\n#define PIC32_IRQ_U5RX      74  /* UART5 Receiver */\n#define PIC32_IRQ_U5TX      75  /* UART5 Transmitter */\n\n/*\n * Interrupt vector numbers for PIC32MX3xx/4xx/5xx/6xx/7xx.\n */\n#define PIC32_VECT_CT       0   /* Core Timer Interrupt */\n#define PIC32_VECT_CS0      1   /* Core Software Interrupt 0 */\n#define PIC32_VECT_CS1      2   /* Core Software Interrupt 1 */\n#define PIC32_VECT_INT0     3   /* External Interrupt 0 */\n#define PIC32_VECT_T1       4   /* Timer1 */\n#define PIC32_VECT_IC1      5   /* Input Capture 1 */\n#define PIC32_VECT_OC1      6   /* Output Compare 1 */\n#define PIC32_VECT_INT1     7   /* External Interrupt 1 */\n#define PIC32_VECT_T2       8   /* Timer2 */\n#define PIC32_VECT_IC2      9   /* Input Capture 2 */\n#define PIC32_VECT_OC2      10  /* Output Compare 2 */\n#define PIC32_VECT_INT2     11  /* External Interrupt 2 */\n#define PIC32_VECT_T3       12  /* Timer3 */\n#define PIC32_VECT_IC3      13  /* Input Capture 3 */\n#define PIC32_VECT_OC3      14  /* Output Compare 3 */\n#define PIC32_VECT_INT3     15  /* External Interrupt 3 */\n#define PIC32_VECT_T4       16  /* Timer4 */\n#define PIC32_VECT_IC4      17  /* Input Capture 4 */\n#define PIC32_VECT_OC4      18  /* Output Compare 4 */\n#define PIC32_VECT_INT4     19  /* External Interrupt 4 */\n#define PIC32_VECT_T5       20  /* Timer5 */\n#define PIC32_VECT_IC5      21  /* Input Capture 5 */\n#define PIC32_VECT_OC5      22  /* Output Compare 5 */\n#define PIC32_VECT_SPI1     23  /* SPI1 */\n\n#define PIC32_VECT_SPI3     24  /* SPI3 */\n#define PIC32_VECT_U1       24  /* UART1 */\n#define PIC32_VECT_I2C3     24  /* I2C3 */\n\n#define PIC32_VECT_I2C1     25  /* I2C1 */\n#define PIC32_VECT_CN       26  /* Input Change Interrupt */\n#define PIC32_VECT_AD1      27  /* ADC1 Convert Done */\n#define PIC32_VECT_PMP      28  /* Parallel Master Port */\n#define PIC32_VECT_CMP1     29  /* Comparator Interrupt */\n#define PIC32_VECT_CMP2     30  /* Comparator Interrupt */\n\n#define PIC32_VECT_SPI2     31  /* SPI2 */\n#define PIC32_VECT_U3       31  /* UART3 */\n#define PIC32_VECT_I2C4     31  /* I2C4 */\n\n#define PIC32_VECT_SPI4     32  /* SPI4 */\n#define PIC32_VECT_U2       32  /* UART2 */\n#define PIC32_VECT_I2C5     32  /* I2C5 */\n\n#define PIC32_VECT_I2C2     33  /* I2C2 */\n#define PIC32_VECT_FSCM     34  /* Fail-Safe Clock Monitor */\n#define PIC32_VECT_RTCC     35  /* Real-Time Clock and Calendar */\n#define PIC32_VECT_DMA0     36  /* DMA Channel 0 */\n#define PIC32_VECT_DMA1     37  /* DMA Channel 1 */\n#define PIC32_VECT_DMA2     38  /* DMA Channel 2 */\n#define PIC32_VECT_DMA3     39  /* DMA Channel 3 */\n#define PIC32_VECT_DMA4     40  /* DMA Channel 4 */\n#define PIC32_VECT_DMA5     41  /* DMA Channel 5 */\n#define PIC32_VECT_DMA6     42  /* DMA Channel 6 */\n#define PIC32_VECT_DMA7     43  /* DMA Channel 7 */\n#define PIC32_VECT_FCE      44  /* Flash Control Event */\n#define PIC32_VECT_USB      45  /* USB */\n#define PIC32_VECT_CAN1     46  /* Control Area Network 1 */\n#define PIC32_VECT_CAN2     47  /* Control Area Network 2 */\n#define PIC32_VECT_ETH      48  /* Ethernet Interrupt */\n#define PIC32_VECT_U4       49  /* UART4 */\n#define PIC32_VECT_U6       50  /* UART6 */\n#define PIC32_VECT_U5       51  /* UART5 */\n\n/*--------------------------------------\n * DMA controller registers.\n */\n#define PIC32_DMACON\tPIC32_R (0x83000) /* DMA Control */\n#define PIC32_DMACONCLR\tPIC32_R (0x83004)\n#define PIC32_DMACONSET\tPIC32_R (0x83008)\n#define PIC32_DMACONINV\tPIC32_R (0x8300C)\n#define PIC32_DMASTAT\tPIC32_R (0x83010) /* DMA Status */\n#define PIC32_DMAADDR\tPIC32_R (0x83020) /* DMA Address */\n// TODO: other DMA registers.\n\n/*--------------------------------------\n * System controller registers.\n */\n#define PIC32_OSCCON\tPIC32_R (0xf000)\n#define PIC32_OSCTUN\tPIC32_R (0xf010)\n#define PIC32_DDPCON\tPIC32_R (0xf200)  /* Debug Data Port Control */\n#define PIC32_DEVID     PIC32_R (0xf220)\n#define PIC32_SYSKEY\tPIC32_R (0xf230)\n#define PIC32_RCON      PIC32_R (0xf600)\n#define PIC32_RSWRST\tPIC32_R (0xf610)\n\n/*--------------------------------------\n * Prefetch cache controller registers.\n */\n#define PIC32_CHECON\tPIC32_R (0x84000)   /* Prefetch cache control */\n// TODO: other prefetech registers\n\n/*--------------------------------------\n * Bus matrix control registers.\n */\n#define PIC32_BMXCON    PIC32_R (0x82000) /* Memory configuration */\n#define PIC32_BMXDKPBA  PIC32_R (0x82010) /* Data RAM kernel program base address */\n#define PIC32_BMXDUDBA  PIC32_R (0x82020) /* Data RAM user data base address */\n#define PIC32_BMXDUPBA  PIC32_R (0x82030) /* Data RAM user program base address */\n#define PIC32_BMXDRMSZ  PIC32_R (0x82040) /* Data RAM size */\n#define PIC32_BMXPUPBA  PIC32_R (0x82050) /* Program Flash user program base address */\n#define PIC32_BMXPFMSZ  PIC32_R (0x82060) /* Program Flash size */\n#define PIC32_BMXBOOTSZ PIC32_R (0x82070) /* Boot Flash size */\n\n/*--------------------------------------\n * Real time clock and calendar.\n */\n#define PIC32_RTCCON    PIC32_R (0x0200)  /* RTC control */\n#define PIC32_RTCALRM   PIC32_R (0x0210)  /* RTC alarm control */\n#define PIC32_RTCTIME   PIC32_R (0x0220)  /* RTC time value */\n#define PIC32_RTCDATE   PIC32_R (0x0230)  /* RTC date value */\n#define PIC32_ALRMTIME  PIC32_R (0x0240)  /* Alarm time value */\n#define PIC32_ALRMDATE  PIC32_R (0x0250)  /* Alarm date value */\n\n/*--------------------------------------\n * Timer registers.\n */\n#define PIC32_T1CON     PIC32_R (0x0600)  /* Timer 1 control */\n#define PIC32_TMR1      PIC32_R (0x0610)  /* Timer 1 count */\n#define PIC32_PR1       PIC32_R (0x0620)  /* Timer 1 period */\n#define PIC32_T2CON     PIC32_R (0x0800)  /* Timer 2 control */\n#define PIC32_TMR2      PIC32_R (0x0810)  /* Timer 2 count */\n#define PIC32_PR2       PIC32_R (0x0820)  /* Timer 2 period */\n#define PIC32_T3CON     PIC32_R (0x0A00)  /* Timer 3 control */\n#define PIC32_TMR3      PIC32_R (0x0A10)  /* Timer 3 count */\n#define PIC32_PR3       PIC32_R (0x0A20)  /* Timer 3 period */\n#define PIC32_T4CON     PIC32_R (0x0C00)  /* Timer 4 control */\n#define PIC32_TMR4      PIC32_R (0x0C10)  /* Timer 4 count */\n#define PIC32_PR4       PIC32_R (0x0C20)  /* Timer 4 period */\n#define PIC32_T5CON     PIC32_R (0x0E00)  /* Timer 5 control */\n#define PIC32_TMR5      PIC32_R (0x0E10)  /* Timer 5 count */\n#define PIC32_PR5       PIC32_R (0x0E20)  /* Timer 5 period */\n\n/*\n * Timer Control register.\n */\n#define PIC32_TCON_ON           0x8000  /* Timer is enabled */\n#define PIC32_TCON_FRZ          0x4000  /* Freeze when CPU is in Debug mode */\n#define PIC32_TCON_SIDL         0x2000  /* Stop in Idle mode */\n#define PIC32_TCON_TWDIS        0x1000  /* (Timer A) Asynchronous Timer Write Disable */\n#define PIC32_TCON_TWIP         0x0800  /* (Timer A) Asynchronous Timer Write in Progress */\n#define PIC32_TCON_TGATE        0x0080  /* Enable gated time accumulation (only when TCS=0) */\n#define PIC32_TCON_TCKPS_MASK   0x0070  /* Timer Input Clock Prescale Select */\n#define PIC32_TCON_TCKPS_256    0x0070  /* 1:256 */\n#define PIC32_TCON_TCKPS_64     0x0060  /* 1:64 */\n#define PIC32_TCON_TCKPS_32     0x0050  /* 1:32 */\n#define PIC32_TCON_TCKPS_16     0x0040  /* 1:16 */\n#define PIC32_TCON_TCKPS_8      0x0030  /* 1:8 */\n#define PIC32_TCON_TCKPS_4      0x0020  /* 1:4 */\n#define PIC32_TCON_TCKPS_2      0x0010  /* 1:2 */\n#define PIC32_TCON_TCKPS_1      0x0000  /* 1:1 */\n#define PIC32_TCON_T32          0x0008  /* (Timer B) TMRx and TMRy form a 32-bit timer */\n#define PIC32_TCON_TSYNC        0x0004  /* (Timer A) External clock input is synchronized */\n#define PIC32_TCON_TCS          0x0002  /* External clock from TxCKI pin */\n\n/*--------------------------------------\n * UART registers.\n */\n#define PIC32_U1MODE            PIC32_R (0x6000) /* Mode */\n#define PIC32_U1MODECLR         PIC32_R (0x6004)\n#define PIC32_U1MODESET         PIC32_R (0x6008)\n#define PIC32_U1MODEINV         PIC32_R (0x600C)\n#define PIC32_U1STA             PIC32_R (0x6010) /* Status and control */\n#define PIC32_U1STACLR          PIC32_R (0x6014)\n#define PIC32_U1STASET          PIC32_R (0x6018)\n#define PIC32_U1STAINV          PIC32_R (0x601C)\n#define PIC32_U1TXREG           PIC32_R (0x6020) /* Transmit */\n#define PIC32_U1RXREG           PIC32_R (0x6030) /* Receive */\n#define PIC32_U1BRG             PIC32_R (0x6040) /* Baud rate */\n#define PIC32_U1BRGCLR          PIC32_R (0x6044)\n#define PIC32_U1BRGSET          PIC32_R (0x6048)\n#define PIC32_U1BRGINV          PIC32_R (0x604C)\n\n#ifdef PIC32MX4\n#define PIC32_U2MODE            PIC32_R (0x6200) /* Mode */\n#define PIC32_U2MODECLR         PIC32_R (0x6204)\n#define PIC32_U2MODESET         PIC32_R (0x6208)\n#define PIC32_U2MODEINV         PIC32_R (0x620C)\n#define PIC32_U2STA\t\t        PIC32_R (0x6210) /* Status and control */\n#define PIC32_U2STACLR\t        PIC32_R (0x6214)\n#define PIC32_U2STASET\t        PIC32_R (0x6218)\n#define PIC32_U2STAINV\t        PIC32_R (0x621C)\n#define PIC32_U2TXREG\t\t    PIC32_R (0x6220) /* Transmit */\n#define PIC32_U2RXREG\t\t    PIC32_R (0x6230) /* Receive */\n#define PIC32_U2BRG\t\t        PIC32_R (0x6240) /* Baud rate */\n#define PIC32_U2BRGCLR\t        PIC32_R (0x6244)\n#define PIC32_U2BRGSET\t        PIC32_R (0x6248)\n#define PIC32_U2BRGINV\t        PIC32_R (0x624C)\n#endif\n#ifdef PIC32MX7\n#define PIC32_U4MODE\t\t    PIC32_R (0x6200) /* Mode */\n#define PIC32_U4MODECLR\t        PIC32_R (0x6204)\n#define PIC32_U4MODESET\t        PIC32_R (0x6208)\n#define PIC32_U4MODEINV\t        PIC32_R (0x620C)\n#define PIC32_U4STA\t\t        PIC32_R (0x6210) /* Status and control */\n#define PIC32_U4STACLR\t        PIC32_R (0x6214)\n#define PIC32_U4STASET\t        PIC32_R (0x6218)\n#define PIC32_U4STAINV\t        PIC32_R (0x621C)\n#define PIC32_U4TXREG\t\t    PIC32_R (0x6220) /* Transmit */\n#define PIC32_U4RXREG\t\t    PIC32_R (0x6230) /* Receive */\n#define PIC32_U4BRG\t\t        PIC32_R (0x6240) /* Baud rate */\n#define PIC32_U4BRGCLR\t        PIC32_R (0x6244)\n#define PIC32_U4BRGSET\t        PIC32_R (0x6248)\n#define PIC32_U4BRGINV\t        PIC32_R (0x624C)\n\n#define PIC32_U3MODE\t\t    PIC32_R (0x6400) /* Mode */\n#define PIC32_U3MODECLR\t        PIC32_R (0x6404)\n#define PIC32_U3MODESET\t        PIC32_R (0x6408)\n#define PIC32_U3MODEINV\t        PIC32_R (0x640C)\n#define PIC32_U3STA\t\t        PIC32_R (0x6410) /* Status and control */\n#define PIC32_U3STACLR\t        PIC32_R (0x6414)\n#define PIC32_U3STASET\t        PIC32_R (0x6418)\n#define PIC32_U3STAINV\t        PIC32_R (0x641C)\n#define PIC32_U3TXREG\t\t    PIC32_R (0x6420) /* Transmit */\n#define PIC32_U3RXREG\t\t    PIC32_R (0x6430) /* Receive */\n#define PIC32_U3BRG\t\t        PIC32_R (0x6440) /* Baud rate */\n#define PIC32_U3BRGCLR\t        PIC32_R (0x6444)\n#define PIC32_U3BRGSET\t        PIC32_R (0x6448)\n#define PIC32_U3BRGINV\t        PIC32_R (0x644C)\n\n#define PIC32_U6MODE\t\t    PIC32_R (0x6600) /* Mode */\n#define PIC32_U6MODECLR\t        PIC32_R (0x6604)\n#define PIC32_U6MODESET\t        PIC32_R (0x6608)\n#define PIC32_U6MODEINV\t        PIC32_R (0x660C)\n#define PIC32_U6STA\t\t        PIC32_R (0x6610) /* Status and control */\n#define PIC32_U6STACLR\t        PIC32_R (0x6614)\n#define PIC32_U6STASET\t        PIC32_R (0x6618)\n#define PIC32_U6STAINV\t        PIC32_R (0x661C)\n#define PIC32_U6TXREG\t\t    PIC32_R (0x6620) /* Transmit */\n#define PIC32_U6RXREG\t\t    PIC32_R (0x6630) /* Receive */\n#define PIC32_U6BRG\t\t        PIC32_R (0x6640) /* Baud rate */\n#define PIC32_U6BRGCLR\t        PIC32_R (0x6644)\n#define PIC32_U6BRGSET\t        PIC32_R (0x6648)\n#define PIC32_U6BRGINV\t        PIC32_R (0x664C)\n\n#define PIC32_U2MODE\t\t    PIC32_R (0x6800) /* Mode */\n#define PIC32_U2MODECLR\t        PIC32_R (0x6804)\n#define PIC32_U2MODESET\t        PIC32_R (0x6808)\n#define PIC32_U2MODEINV\t        PIC32_R (0x680C)\n#define PIC32_U2STA\t\t        PIC32_R (0x6810) /* Status and control */\n#define PIC32_U2STACLR\t        PIC32_R (0x6814)\n#define PIC32_U2STASET\t        PIC32_R (0x6818)\n#define PIC32_U2STAINV\t        PIC32_R (0x681C)\n#define PIC32_U2TXREG\t\t    PIC32_R (0x6820) /* Transmit */\n#define PIC32_U2RXREG\t\t    PIC32_R (0x6830) /* Receive */\n#define PIC32_U2BRG\t\t        PIC32_R (0x6840) /* Baud rate */\n#define PIC32_U2BRGCLR\t        PIC32_R (0x6844)\n#define PIC32_U2BRGSET\t        PIC32_R (0x6848)\n#define PIC32_U2BRGINV\t        PIC32_R (0x684C)\n\n#define PIC32_U5MODE\t\t    PIC32_R (0x6A00) /* Mode */\n#define PIC32_U5MODECLR\t        PIC32_R (0x6A04)\n#define PIC32_U5MODESET\t        PIC32_R (0x6A08)\n#define PIC32_U5MODEINV\t        PIC32_R (0x6A0C)\n#define PIC32_U5STA\t\t        PIC32_R (0x6A10) /* Status and control */\n#define PIC32_U5STACLR\t        PIC32_R (0x6A14)\n#define PIC32_U5STASET\t        PIC32_R (0x6A18)\n#define PIC32_U5STAINV\t        PIC32_R (0x6A1C)\n#define PIC32_U5TXREG\t\t    PIC32_R (0x6A20) /* Transmit */\n#define PIC32_U5RXREG\t\t    PIC32_R (0x6A30) /* Receive */\n#define PIC32_U5BRG\t\t        PIC32_R (0x6A40) /* Baud rate */\n#define PIC32_U5BRGCLR\t        PIC32_R (0x6A44)\n#define PIC32_U5BRGSET\t        PIC32_R (0x6A48)\n#define PIC32_U5BRGINV\t        PIC32_R (0x6A4C)\n#endif\n\n/*\n * UART Mode register.\n */\n#define PIC32_UMODE_STSEL       0x0001  /* 2 Stop bits */\n#define PIC32_UMODE_PDSEL       0x0006  /* Bitmask: */\n#define PIC32_UMODE_PDSEL_8NPAR 0x0000  /* 8-bit data, no parity */\n#define PIC32_UMODE_PDSEL_8EVEN 0x0002  /* 8-bit data, even parity */\n#define PIC32_UMODE_PDSEL_8ODD  0x0004  /* 8-bit data, odd parity */\n#define PIC32_UMODE_PDSEL_9NPAR 0x0006  /* 9-bit data, no parity */\n#define PIC32_UMODE_BRGH        0x0008  /* High Baud Rate Enable */\n#define PIC32_UMODE_RXINV       0x0010  /* Receive Polarity Inversion */\n#define PIC32_UMODE_ABAUD       0x0020  /* Auto-Baud Enable */\n#define PIC32_UMODE_LPBACK      0x0040  /* UARTx Loopback Mode */\n#define PIC32_UMODE_WAKE        0x0080  /* Wake-up on start bit during Sleep Mode */\n#define PIC32_UMODE_UEN         0x0300  /* Bitmask: */\n#define PIC32_UMODE_UEN_RTS     0x0100  /* Using UxRTS pin */\n#define PIC32_UMODE_UEN_RTSCTS  0x0200  /* Using UxCTS and UxRTS pins */\n#define PIC32_UMODE_UEN_BCLK    0x0300  /* Using UxBCLK pin */\n#define PIC32_UMODE_RTSMD       0x0800  /* UxRTS Pin Simplex mode */\n#define PIC32_UMODE_IREN        0x1000  /* IrDA Encoder and Decoder Enable bit */\n#define PIC32_UMODE_SIDL        0x2000  /* Stop in Idle Mode */\n#define PIC32_UMODE_FRZ         0x4000  /* Freeze in Debug Exception Mode */\n#define PIC32_UMODE_ON          0x8000  /* UART Enable */\n\n/*\n * UART Control and status register.\n */\n#define PIC32_USTA_URXDA        0x00000001      /* Receive Data Available (read-only) */\n#define PIC32_USTA_OERR         0x00000002      /* Receive Buffer Overrun */\n#define PIC32_USTA_FERR         0x00000004      /* Framing error detected (read-only) */\n#define PIC32_USTA_PERR         0x00000008      /* Parity error detected (read-only) */\n#define PIC32_USTA_RIDLE        0x00000010      /* Receiver is idle (read-only) */\n#define PIC32_USTA_ADDEN        0x00000020      /* Address Detect mode */\n#define PIC32_USTA_URXISEL      0x000000C0      /* Bitmask: receive interrupt is set when... */\n#define PIC32_USTA_URXISEL_NEMP 0x00000000      /* ...receive buffer is not empty */\n#define PIC32_USTA_URXISEL_HALF 0x00000040      /* ...receive buffer becomes 1/2 full */\n#define PIC32_USTA_URXISEL_3_4  0x00000080      /* ...receive buffer becomes 3/4 full */\n#define PIC32_USTA_TRMT         0x00000100      /* Transmit shift register is empty (read-only) */\n#define PIC32_USTA_UTXBF        0x00000200      /* Transmit buffer is full (read-only) */\n#define PIC32_USTA_UTXEN        0x00000400      /* Transmit Enable */\n#define PIC32_USTA_UTXBRK       0x00000800      /* Transmit Break */\n#define PIC32_USTA_URXEN        0x00001000      /* Receiver Enable */\n#define PIC32_USTA_UTXINV       0x00002000      /* Transmit Polarity Inversion */\n#define PIC32_USTA_UTXISEL      0x0000C000      /* Bitmask: TX interrupt is generated when... */\n#define PIC32_USTA_UTXISEL_1    0x00000000      /* ...the transmit buffer contains at least one empty space */\n#define PIC32_USTA_UTXISEL_ALL  0x00004000      /* ...all characters have been transmitted */\n#define PIC32_USTA_UTXISEL_EMP  0x00008000      /* ...the transmit buffer becomes empty */\n#define PIC32_USTA_ADDR         0x00FF0000      /* Automatic Address Mask */\n#define PIC32_USTA_ADM_EN       0x01000000      /* Automatic Address Detect */\n\n/*\n * Compute the 16-bit baud rate divisor, given\n * the oscillator frequency and baud rate.\n * Round to the nearest integer.\n */\n#define PIC32_BRG_BAUD(fr,bd)   ((((fr)/8 + (bd)) / (bd) / 2) - 1)\n\n/*--------------------------------------\n * SPI registers.\n */\n#ifdef PIC32MX4\n#define PIC32_SPI1CON           PIC32_R (0x5800) /* Control */\n#define PIC32_SPI1CONCLR\t    PIC32_R (0x5804)\n#define PIC32_SPI1CONSET\t    PIC32_R (0x5808)\n#define PIC32_SPI1CONINV\t    PIC32_R (0x580C)\n#define PIC32_SPI1STAT\t        PIC32_R (0x5810) /* Status */\n#define PIC32_SPI1STATCLR\t    PIC32_R (0x5814)\n#define PIC32_SPI1STATSET\t    PIC32_R (0x5818)\n#define PIC32_SPI1STATINV\t    PIC32_R (0x581C)\n#define PIC32_SPI1BUF\t\t    PIC32_R (0x5820) /* Transmit and receive buffer */\n#define PIC32_SPI1BRG\t\t    PIC32_R (0x5830) /* Baud rate generator */\n#define PIC32_SPI1BRGCLR\t    PIC32_R (0x5834)\n#define PIC32_SPI1BRGSET\t    PIC32_R (0x5838)\n#define PIC32_SPI1BRGINV\t    PIC32_R (0x583C)\n#endif\n#ifdef PIC32MX7\n#define PIC32_SPI3CON\t\t    PIC32_R (0x5800) /* Control */\n#define PIC32_SPI3CONCLR\t    PIC32_R (0x5804)\n#define PIC32_SPI3CONSET\t    PIC32_R (0x5808)\n#define PIC32_SPI3CONINV\t    PIC32_R (0x580C)\n#define PIC32_SPI3STAT\t        PIC32_R (0x5810) /* Status */\n#define PIC32_SPI3STATCLR\t    PIC32_R (0x5814)\n#define PIC32_SPI3STATSET\t    PIC32_R (0x5818)\n#define PIC32_SPI3STATINV\t    PIC32_R (0x581C)\n#define PIC32_SPI3BUF\t\t    PIC32_R (0x5820) /* Transmit and receive buffer */\n#define PIC32_SPI3BRG\t\t    PIC32_R (0x5830) /* Baud rate generator */\n#define PIC32_SPI3BRGCLR\t    PIC32_R (0x5834)\n#define PIC32_SPI3BRGSET\t    PIC32_R (0x5838)\n#define PIC32_SPI3BRGINV\t    PIC32_R (0x583C)\n\n#define PIC32_SPI4CON\t\t    PIC32_R (0x5C00) /* Control */\n#define PIC32_SPI4CONCLR\t    PIC32_R (0x5C04)\n#define PIC32_SPI4CONSET\t    PIC32_R (0x5C08)\n#define PIC32_SPI4CONINV\t    PIC32_R (0x5C0C)\n#define PIC32_SPI4STAT\t        PIC32_R (0x5C10) /* Status */\n#define PIC32_SPI4STATCLR\t    PIC32_R (0x5C14)\n#define PIC32_SPI4STATSET\t    PIC32_R (0x5C18)\n#define PIC32_SPI4STATINV\t    PIC32_R (0x5C1C)\n#define PIC32_SPI4BUF\t\t    PIC32_R (0x5C20) /* Transmit and receive buffer */\n#define PIC32_SPI4BRG\t\t    PIC32_R (0x5C30) /* Baud rate generator */\n#define PIC32_SPI4BRGCLR\t    PIC32_R (0x5C34)\n#define PIC32_SPI4BRGSET\t    PIC32_R (0x5C38)\n#define PIC32_SPI4BRGINV\t    PIC32_R (0x5C3C)\n\n#define PIC32_SPI1CON\t\t    PIC32_R (0x5E00) /* Control */\n#define PIC32_SPI1CONCLR\t    PIC32_R (0x5E04)\n#define PIC32_SPI1CONSET\t    PIC32_R (0x5E08)\n#define PIC32_SPI1CONINV\t    PIC32_R (0x5E0C)\n#define PIC32_SPI1STAT\t        PIC32_R (0x5E10) /* Status */\n#define PIC32_SPI1STATCLR\t    PIC32_R (0x5E14)\n#define PIC32_SPI1STATSET\t    PIC32_R (0x5E18)\n#define PIC32_SPI1STATINV\t    PIC32_R (0x5E1C)\n#define PIC32_SPI1BUF\t\t    PIC32_R (0x5E20) /* Transmit and receive buffer */\n#define PIC32_SPI1BRG\t\t    PIC32_R (0x5E30) /* Baud rate generator */\n#define PIC32_SPI1BRGCLR\t    PIC32_R (0x5E34)\n#define PIC32_SPI1BRGSET\t    PIC32_R (0x5E38)\n#define PIC32_SPI1BRGINV\t    PIC32_R (0x5E3C)\n#endif\n\n#define PIC32_SPI2CON           PIC32_R (0x5A00) /* Control */\n#define PIC32_SPI2CONCLR        PIC32_R (0x5A04)\n#define PIC32_SPI2CONSET        PIC32_R (0x5A08)\n#define PIC32_SPI2CONINV        PIC32_R (0x5A0C)\n#define PIC32_SPI2STAT          PIC32_R (0x5A10) /* Status */\n#define PIC32_SPI2STATCLR       PIC32_R (0x5A14)\n#define PIC32_SPI2STATSET       PIC32_R (0x5A18)\n#define PIC32_SPI2STATINV       PIC32_R (0x5A1C)\n#define PIC32_SPI2BUF           PIC32_R (0x5A20) /* Transmit and receive buffer */\n#define PIC32_SPI2BRG           PIC32_R (0x5A30) /* Baud rate generator */\n#define PIC32_SPI2BRGCLR        PIC32_R (0x5A34)\n#define PIC32_SPI2BRGSET        PIC32_R (0x5A38)\n#define PIC32_SPI2BRGINV        PIC32_R (0x5A3C)\n\n/*\n * SPI Control register.\n */\n#define PIC32_SPICON_MSTEN      0x00000020      /* Master mode */\n#define PIC32_SPICON_CKP        0x00000040      /* Idle clock is high level */\n#define PIC32_SPICON_SSEN       0x00000080      /* Slave mode: SSx pin enable */\n#define PIC32_SPICON_CKE        0x00000100      /* Output data changes on\n                                                 * transition from active clock\n                                                 * state to Idle clock state */\n#define PIC32_SPICON_SMP        0x00000200      /* Master mode: input data sampled\n                                                 * at end of data output time. */\n#define PIC32_SPICON_MODE16     0x00000400      /* 16-bit data width */\n#define PIC32_SPICON_MODE32     0x00000800      /* 32-bit data width */\n#define PIC32_SPICON_DISSDO     0x00001000      /* SDOx pin is not used */\n#define PIC32_SPICON_SIDL       0x00002000      /* Stop in Idle mode */\n#define PIC32_SPICON_FRZ        0x00004000      /* Freeze in Debug mode */\n#define PIC32_SPICON_ON         0x00008000      /* SPI Peripheral is enabled */\n#define PIC32_SPICON_ENHBUF     0x00010000      /* Enhanced buffer enable */\n#define PIC32_SPICON_SPIFE      0x00020000      /* Frame synchronization pulse\n                                                 * coincides with the first bit clock */\n#define PIC32_SPICON_FRMPOL     0x20000000      /* Frame pulse is active-high */\n#define PIC32_SPICON_FRMSYNC\t0x40000000      /* Frame sync pulse input (Slave mode) */\n#define PIC32_SPICON_FRMEN      0x80000000      /* Framed SPI support */\n\n/*\n * SPI Status register.\n */\n#define PIC32_SPISTAT_SPIRBF\t0x00000001      /* Receive buffer is full */\n#define PIC32_SPISTAT_SPITBE\t0x00000008      /* Transmit buffer is empty */\n#define PIC32_SPISTAT_SPIROV\t0x00000040      /* Receive overflow flag */\n#define PIC32_SPISTAT_SPIBUSY\t0x00000800      /* SPI is busy */\n\n/*--------------------------------------\n * Port A-G registers.\n */\n#define PIC32_TRISA             PIC32_R (0x86000)       /* Port A: mask of inputs */\n#define PIC32_TRISACLR          PIC32_R (0x86004)\n#define PIC32_TRISASET          PIC32_R (0x86008)\n#define PIC32_TRISAINV          PIC32_R (0x8600C)\n#define PIC32_PORTA             PIC32_R (0x86010)       /* Port A: read inputs, write outputs */\n#define PIC32_PORTACLR          PIC32_R (0x86014)\n#define PIC32_PORTASET          PIC32_R (0x86018)\n#define PIC32_PORTAINV          PIC32_R (0x8601C)\n#define PIC32_LATA              PIC32_R (0x86020)       /* Port A: read/write outputs */\n#define PIC32_LATACLR           PIC32_R (0x86024)\n#define PIC32_LATASET           PIC32_R (0x86028)\n#define PIC32_LATAINV           PIC32_R (0x8602C)\n#define PIC32_ODCA              PIC32_R (0x86030)       /* Port A: open drain configuration */\n#define PIC32_ODCACLR           PIC32_R (0x86034)\n#define PIC32_ODCASET           PIC32_R (0x86038)\n#define PIC32_ODCAINV           PIC32_R (0x8603C)\n\n#define PIC32_TRISB             PIC32_R (0x86040)       /* Port B: mask of inputs */\n#define PIC32_TRISBCLR          PIC32_R (0x86044)\n#define PIC32_TRISBSET          PIC32_R (0x86048)\n#define PIC32_TRISBINV          PIC32_R (0x8604C)\n#define PIC32_PORTB             PIC32_R (0x86050)       /* Port B: read inputs, write outputs */\n#define PIC32_PORTBCLR          PIC32_R (0x86054)\n#define PIC32_PORTBSET          PIC32_R (0x86058)\n#define PIC32_PORTBINV          PIC32_R (0x8605C)\n#define PIC32_LATB              PIC32_R (0x86060)       /* Port B: read/write outputs */\n#define PIC32_LATBCLR           PIC32_R (0x86064)\n#define PIC32_LATBSET           PIC32_R (0x86068)\n#define PIC32_LATBINV           PIC32_R (0x8606C)\n#define PIC32_ODCB              PIC32_R (0x86070)       /* Port B: open drain configuration */\n#define PIC32_ODCBCLR           PIC32_R (0x86074)\n#define PIC32_ODCBSET           PIC32_R (0x86078)\n#define PIC32_ODCBINV           PIC32_R (0x8607C)\n\n#define PIC32_TRISC             PIC32_R (0x86080)       /* Port C: mask of inputs */\n#define PIC32_TRISCCLR          PIC32_R (0x86084)\n#define PIC32_TRISCSET          PIC32_R (0x86088)\n#define PIC32_TRISCINV          PIC32_R (0x8608C)\n#define PIC32_PORTC             PIC32_R (0x86090)       /* Port C: read inputs, write outputs */\n#define PIC32_PORTCCLR          PIC32_R (0x86094)\n#define PIC32_PORTCSET          PIC32_R (0x86098)\n#define PIC32_PORTCINV          PIC32_R (0x8609C)\n#define PIC32_LATC              PIC32_R (0x860A0)       /* Port C: read/write outputs */\n#define PIC32_LATCCLR           PIC32_R (0x860A4)\n#define PIC32_LATCSET           PIC32_R (0x860A8)\n#define PIC32_LATCINV           PIC32_R (0x860AC)\n#define PIC32_ODCC              PIC32_R (0x860B0)       /* Port C: open drain configuration */\n#define PIC32_ODCCCLR           PIC32_R (0x860B4)\n#define PIC32_ODCCSET           PIC32_R (0x860B8)\n#define PIC32_ODCCINV           PIC32_R (0x860BC)\n\n#define PIC32_TRISD             PIC32_R (0x860C0)       /* Port D: mask of inputs */\n#define PIC32_TRISDCLR          PIC32_R (0x860C4)\n#define PIC32_TRISDSET          PIC32_R (0x860C8)\n#define PIC32_TRISDINV          PIC32_R (0x860CC)\n#define PIC32_PORTD             PIC32_R (0x860D0)       /* Port D: read inputs, write outputs */\n#define PIC32_PORTDCLR          PIC32_R (0x860D4)\n#define PIC32_PORTDSET          PIC32_R (0x860D8)\n#define PIC32_PORTDINV          PIC32_R (0x860DC)\n#define PIC32_LATD              PIC32_R (0x860E0)       /* Port D: read/write outputs */\n#define PIC32_LATDCLR           PIC32_R (0x860E4)\n#define PIC32_LATDSET           PIC32_R (0x860E8)\n#define PIC32_LATDINV           PIC32_R (0x860EC)\n#define PIC32_ODCD              PIC32_R (0x860F0)       /* Port D: open drain configuration */\n#define PIC32_ODCDCLR           PIC32_R (0x860F4)\n#define PIC32_ODCDSET           PIC32_R (0x860F8)\n#define PIC32_ODCDINV           PIC32_R (0x860FC)\n\n#define PIC32_TRISE             PIC32_R (0x86100)       /* Port E: mask of inputs */\n#define PIC32_TRISECLR          PIC32_R (0x86104)\n#define PIC32_TRISESET          PIC32_R (0x86108)\n#define PIC32_TRISEINV          PIC32_R (0x8610C)\n#define PIC32_PORTE             PIC32_R (0x86110)       /* Port E: read inputs, write outputs */\n#define PIC32_PORTECLR          PIC32_R (0x86114)\n#define PIC32_PORTESET          PIC32_R (0x86118)\n#define PIC32_PORTEINV          PIC32_R (0x8611C)\n#define PIC32_LATE              PIC32_R (0x86120)       /* Port E: read/write outputs */\n#define PIC32_LATECLR           PIC32_R (0x86124)\n#define PIC32_LATESET           PIC32_R (0x86128)\n#define PIC32_LATEINV           PIC32_R (0x8612C)\n#define PIC32_ODCE              PIC32_R (0x86130)       /* Port E: open drain configuration */\n#define PIC32_ODCECLR           PIC32_R (0x86134)\n#define PIC32_ODCESET           PIC32_R (0x86138)\n#define PIC32_ODCEINV           PIC32_R (0x8613C)\n\n#define PIC32_TRISF             PIC32_R (0x86140)       /* Port F: mask of inputs */\n#define PIC32_TRISFCLR          PIC32_R (0x86144)\n#define PIC32_TRISFSET          PIC32_R (0x86148)\n#define PIC32_TRISFINV          PIC32_R (0x8614C)\n#define PIC32_PORTF             PIC32_R (0x86150)       /* Port F: read inputs, write outputs */\n#define PIC32_PORTFCLR          PIC32_R (0x86154)\n#define PIC32_PORTFSET          PIC32_R (0x86158)\n#define PIC32_PORTFINV          PIC32_R (0x8615C)\n#define PIC32_LATF              PIC32_R (0x86160)       /* Port F: read/write outputs */\n#define PIC32_LATFCLR           PIC32_R (0x86164)\n#define PIC32_LATFSET           PIC32_R (0x86168)\n#define PIC32_LATFINV           PIC32_R (0x8616C)\n#define PIC32_ODCF              PIC32_R (0x86170)       /* Port F: open drain configuration */\n#define PIC32_ODCFCLR           PIC32_R (0x86174)\n#define PIC32_ODCFSET           PIC32_R (0x86178)\n#define PIC32_ODCFINV           PIC32_R (0x8617C)\n\n#define PIC32_TRISG             PIC32_R (0x86180)       /* Port G: mask of inputs */\n#define PIC32_TRISGCLR          PIC32_R (0x86184)\n#define PIC32_TRISGSET          PIC32_R (0x86188)\n#define PIC32_TRISGINV          PIC32_R (0x8618C)\n#define PIC32_PORTG             PIC32_R (0x86190)       /* Port G: read inputs, write outputs */\n#define PIC32_PORTGCLR          PIC32_R (0x86194)\n#define PIC32_PORTGSET          PIC32_R (0x86198)\n#define PIC32_PORTGINV          PIC32_R (0x8619C)\n#define PIC32_LATG              PIC32_R (0x861A0)       /* Port G: read/write outputs */\n#define PIC32_LATGCLR           PIC32_R (0x861A4)\n#define PIC32_LATGSET           PIC32_R (0x861A8)\n#define PIC32_LATGINV           PIC32_R (0x861AC)\n#define PIC32_ODCG              PIC32_R (0x861B0)       /* Port G: open drain configuration */\n#define PIC32_ODCGCLR           PIC32_R (0x861B4)\n#define PIC32_ODCGSET           PIC32_R (0x861B8)\n#define PIC32_ODCGINV           PIC32_R (0x861BC)\n\n#define PIC32_CNCON             PIC32_R (0x861C0)       /* Interrupt-on-change control */\n#define PIC32_CNCONCLR          PIC32_R (0x861C4)\n#define PIC32_CNCONSET          PIC32_R (0x861C8)\n#define PIC32_CNCONINV          PIC32_R (0x861CC)\n#define PIC32_CNEN              PIC32_R (0x861D0)       /* Input change interrupt enable */\n#define PIC32_CNENCLR           PIC32_R (0x861D4)\n#define PIC32_CNENSET           PIC32_R (0x861D8)\n#define PIC32_CNENINV           PIC32_R (0x861DC)\n#define PIC32_CNPUE             PIC32_R (0x861E0)       /* Input pin pull-up enable */\n#define PIC32_CNPUECLR          PIC32_R (0x861E4)\n#define PIC32_CNPUESET          PIC32_R (0x861E8)\n#define PIC32_CNPUEINV          PIC32_R (0x861EC)\n\n/*--------------------------------------\n * A/D Converter registers.\n */\n#define PIC32_AD1CON1           PIC32_R (0x9000)        /* Control register 1 */\n#define PIC32_AD1CON1CLR        PIC32_R (0x9004)\n#define PIC32_AD1CON1SET        PIC32_R (0x9008)\n#define PIC32_AD1CON1INV        PIC32_R (0x900C)\n#define PIC32_AD1CON2           PIC32_R (0x9010)        /* Control register 2 */\n#define PIC32_AD1CON2CLR        PIC32_R (0x9014)\n#define PIC32_AD1CON2SET        PIC32_R (0x9018)\n#define PIC32_AD1CON2INV        PIC32_R (0x901C)\n#define PIC32_AD1CON3           PIC32_R (0x9020)        /* Control register 3 */\n#define PIC32_AD1CON3CLR        PIC32_R (0x9024)\n#define PIC32_AD1CON3SET        PIC32_R (0x9028)\n#define PIC32_AD1CON3INV        PIC32_R (0x902C)\n#define PIC32_AD1CHS            PIC32_R (0x9040)        /* Channel select */\n#define PIC32_AD1CHSCLR         PIC32_R (0x9044)\n#define PIC32_AD1CHSSET         PIC32_R (0x9048)\n#define PIC32_AD1CHSINV         PIC32_R (0x904C)\n#define PIC32_AD1CSSL           PIC32_R (0x9050)        /* Input scan selection */\n#define PIC32_AD1CSSLCLR        PIC32_R (0x9054)\n#define PIC32_AD1CSSLSET        PIC32_R (0x9058)\n#define PIC32_AD1CSSLINV        PIC32_R (0x905C)\n#define PIC32_AD1PCFG           PIC32_R (0x9060)        /* Port configuration */\n#define PIC32_AD1PCFGCLR        PIC32_R (0x9064)\n#define PIC32_AD1PCFGSET        PIC32_R (0x9068)\n#define PIC32_AD1PCFGINV        PIC32_R (0x906C)\n#define PIC32_ADC1BUF0          PIC32_R (0x9070)        /* Result words */\n#define PIC32_ADC1BUF1          PIC32_R (0x9080)\n#define PIC32_ADC1BUF2          PIC32_R (0x9090)\n#define PIC32_ADC1BUF3          PIC32_R (0x90A0)\n#define PIC32_ADC1BUF4          PIC32_R (0x90B0)\n#define PIC32_ADC1BUF5          PIC32_R (0x90C0)\n#define PIC32_ADC1BUF6          PIC32_R (0x90D0)\n#define PIC32_ADC1BUF7          PIC32_R (0x90E0)\n#define PIC32_ADC1BUF8          PIC32_R (0x90F0)\n#define PIC32_ADC1BUF9          PIC32_R (0x9100)\n#define PIC32_ADC1BUFA          PIC32_R (0x9110)\n#define PIC32_ADC1BUFB          PIC32_R (0x9120)\n#define PIC32_ADC1BUFC          PIC32_R (0x9130)\n#define PIC32_ADC1BUFD          PIC32_R (0x9140)\n#define PIC32_ADC1BUFE          PIC32_R (0x9150)\n#define PIC32_ADC1BUFF          PIC32_R (0x9160)\n\n/*--------------------------------------\n * Parallel master port registers.\n */\n#define PIC32_PMCON             PIC32_R (0x7000)        /* Control */\n#define PIC32_PMCONCLR          PIC32_R (0x7004)\n#define PIC32_PMCONSET          PIC32_R (0x7008)\n#define PIC32_PMCONINV          PIC32_R (0x700C)\n#define PIC32_PMMODE            PIC32_R (0x7010)        /* Mode */\n#define PIC32_PMMODECLR         PIC32_R (0x7014)\n#define PIC32_PMMODESET         PIC32_R (0x7018)\n#define PIC32_PMMODEINV         PIC32_R (0x701C)\n#define PIC32_PMADDR            PIC32_R (0x7020)        /* Address */\n#define PIC32_PMADDRCLR         PIC32_R (0x7024)\n#define PIC32_PMADDRSET         PIC32_R (0x7028)\n#define PIC32_PMADDRINV         PIC32_R (0x702C)\n#define PIC32_PMDOUT            PIC32_R (0x7030)        /* Data output */\n#define PIC32_PMDOUTCLR         PIC32_R (0x7034)\n#define PIC32_PMDOUTSET         PIC32_R (0x7038)\n#define PIC32_PMDOUTINV         PIC32_R (0x703C)\n#define PIC32_PMDIN             PIC32_R (0x7040)        /* Data input */\n#define PIC32_PMDINCLR          PIC32_R (0x7044)\n#define PIC32_PMDINSET          PIC32_R (0x7048)\n#define PIC32_PMDININV          PIC32_R (0x704C)\n#define PIC32_PMAEN             PIC32_R (0x7050)        /* Pin enable */\n#define PIC32_PMAENCLR          PIC32_R (0x7054)\n#define PIC32_PMAENSET          PIC32_R (0x7058)\n#define PIC32_PMAENINV          PIC32_R (0x705C)\n#define PIC32_PMSTAT            PIC32_R (0x7060)        /* Status (slave only) */\n#define PIC32_PMSTATCLR         PIC32_R (0x7064)\n#define PIC32_PMSTATSET         PIC32_R (0x7068)\n#define PIC32_PMSTATINV         PIC32_R (0x706C)\n\n/*\n * PMP Control register.\n */\n#define PIC32_PMCON_RDSP        0x0001  /* Read strobe polarity active-high */\n#define PIC32_PMCON_WRSP        0x0002  /* Write strobe polarity active-high */\n#define PIC32_PMCON_CS1P        0x0008  /* Chip select 0 polarity active-high */\n#define PIC32_PMCON_CS2P        0x0010  /* Chip select 1 polarity active-high */\n#define PIC32_PMCON_ALP         0x0020  /* Address latch polarity active-high */\n#define PIC32_PMCON_CSF         0x00C0  /* Chip select function bitmask: */\n#define PIC32_PMCON_CSF_NONE    0x0000  /* PMCS2 and PMCS1 as A[15:14] */\n#define PIC32_PMCON_CSF_CS2     0x0040  /* PMCS2 as chip select */\n#define PIC32_PMCON_CSF_CS21    0x0080  /* PMCS2 and PMCS1 as chip select */\n#define PIC32_PMCON_PTRDEN      0x0100  /* Read/write strobe port enable */\n#define PIC32_PMCON_PTWREN      0x0200  /* Write enable strobe port enable */\n#define PIC32_PMCON_PMPTTL      0x0400  /* TTL input buffer select */\n#define PIC32_PMCON_ADRMUX      0x1800  /* Address/data mux selection bitmask: */\n#define PIC32_PMCON_ADRMUX_NONE 0x0000  /* Address and data separate */\n#define PIC32_PMCON_ADRMUX_AD   0x0800  /* Lower address on PMD[7:0], high on PMA[15:8] */\n#define PIC32_PMCON_ADRMUX_D8   0x1000  /* All address on PMD[7:0] */\n#define PIC32_PMCON_ADRMUX_D16  0x1800  /* All address on PMD[15:0] */\n#define PIC32_PMCON_SIDL        0x2000  /* Stop in idle */\n#define PIC32_PMCON_FRZ         0x4000  /* Freeze in debug exception */\n#define PIC32_PMCON_ON          0x8000  /* Parallel master port enable */\n\n/*\n * PMP Mode register.\n */\n#define PIC32_PMMODE_WAITE(x)   ((x)<<0)        /* Wait states: data hold after RW strobe */\n#define PIC32_PMMODE_WAITM(x)   ((x)<<2)        /* Wait states: data RW strobe */\n#define PIC32_PMMODE_WAITB(x)   ((x)<<6)        /* Wait states: data setup to RW strobe */\n#define PIC32_PMMODE_MODE       0x0300  /* Mode select bitmask: */\n#define PIC32_PMMODE_MODE_SLAVE 0x0000  /* Legacy slave */\n#define PIC32_PMMODE_MODE_SLENH 0x0100  /* Enhanced slave */\n#define PIC32_PMMODE_MODE_MAST2 0x0200  /* Master mode 2 */\n#define PIC32_PMMODE_MODE_MAST1 0x0300  /* Master mode 1 */\n#define PIC32_PMMODE_MODE16     0x0400  /* 16-bit mode */\n#define PIC32_PMMODE_INCM       0x1800  /* Address increment mode bitmask: */\n#define PIC32_PMMODE_INCM_NONE  0x0000  /* No increment/decrement */\n#define PIC32_PMMODE_INCM_INC   0x0800  /* Increment address */\n#define PIC32_PMMODE_INCM_DEC   0x1000  /* Decrement address */\n#define PIC32_PMMODE_INCM_SLAVE 0x1800  /* Slave auto-increment */\n#define PIC32_PMMODE_IRQM       0x6000  /* Interrupt request bitmask: */\n#define PIC32_PMMODE_IRQM_DIS   0x0000  /* No interrupt generated */\n#define PIC32_PMMODE_IRQM_END   0x2000  /* Interrupt at end of read/write cycle */\n#define PIC32_PMMODE_IRQM_A3    0x4000  /* Interrupt on address 3 */\n#define PIC32_PMMODE_BUSY       0x8000  /* Port is busy */\n\n/*\n * PMP Address register.\n */\n#define PIC32_PMADDR_PADDR      0x3FFF  /* Destination address */\n#define PIC32_PMADDR_CS1        0x4000  /* Chip select 1 is active */\n#define PIC32_PMADDR_CS2        0x8000  /* Chip select 2 is active */\n\n/*\n * PMP status register (slave only).\n */\n#define PIC32_PMSTAT_OB0E       0x0001  /* Output buffer 0 empty */\n#define PIC32_PMSTAT_OB1E       0x0002  /* Output buffer 1 empty */\n#define PIC32_PMSTAT_OB2E       0x0004  /* Output buffer 2 empty */\n#define PIC32_PMSTAT_OB3E       0x0008  /* Output buffer 3 empty */\n#define PIC32_PMSTAT_OBUF       0x0040  /* Output buffer underflow */\n#define PIC32_PMSTAT_OBE        0x0080  /* Output buffer empty */\n#define PIC32_PMSTAT_IB0F       0x0100  /* Input buffer 0 full */\n#define PIC32_PMSTAT_IB1F       0x0200  /* Input buffer 1 full */\n#define PIC32_PMSTAT_IB2F       0x0400  /* Input buffer 2 full */\n#define PIC32_PMSTAT_IB3F       0x0800  /* Input buffer 3 full */\n#define PIC32_PMSTAT_IBOV       0x4000  /* Input buffer overflow */\n#define PIC32_PMSTAT_IBF        0x8000  /* Input buffer full */\n\n#endif /* _IO_PIC32MX_H */\n"
  },
  {
    "path": "tools/virtualmips/sbox.c",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2007 Christophe Fillot (cf@utc.fr)\n *\n * S-Box: http://bretm.home.comcast.net/hash/10.html\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <string.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <sys/mman.h>\n#include <signal.h>\n#include <fcntl.h>\n#include <assert.h>\n\n#include \"utils.h\"\n#include \"sbox.h\"\n\nm_uint32_t sbox_array[] = {\n    0xF53E1837, 0x5F14C86B, 0x9EE3964C, 0xFA796D53,\n    0x32223FC3, 0x4D82BC98, 0xA0C7FA62, 0x63E2C982,\n    0x24994A5B, 0x1ECE7BEE, 0x292B38EF, 0xD5CD4E56,\n    0x514F4303, 0x7BE12B83, 0x7192F195, 0x82DC7300,\n    0x084380B4, 0x480B55D3, 0x5F430471, 0x13F75991,\n    0x3F9CF22C, 0x2FE0907A, 0xFD8E1E69, 0x7B1D5DE8,\n    0xD575A85C, 0xAD01C50A, 0x7EE00737, 0x3CE981E8,\n    0x0E447EFA, 0x23089DD6, 0xB59F149F, 0x13600EC7,\n    0xE802C8E6, 0x670921E4, 0x7207EFF0, 0xE74761B0,\n    0x69035234, 0xBFA40F19, 0xF63651A0, 0x29E64C26,\n    0x1F98CCA7, 0xD957007E, 0xE71DDC75, 0x3E729595,\n    0x7580B7CC, 0xD7FAF60B, 0x92484323, 0xA44113EB,\n    0xE4CBDE08, 0x346827C9, 0x3CF32AFA, 0x0B29BCF1,\n    0x6E29F7DF, 0xB01E71CB, 0x3BFBC0D1, 0x62EDC5B8,\n    0xB7DE789A, 0xA4748EC9, 0xE17A4C4F, 0x67E5BD03,\n    0xF3B33D1A, 0x97D8D3E9, 0x09121BC0, 0x347B2D2C,\n    0x79A1913C, 0x504172DE, 0x7F1F8483, 0x13AC3CF6,\n    0x7A2094DB, 0xC778FA12, 0xADF7469F, 0x21786B7B,\n    0x71A445D0, 0xA8896C1B, 0x656F62FB, 0x83A059B3,\n    0x972DFE6E, 0x4122000C, 0x97D9DA19, 0x17D5947B,\n    0xB1AFFD0C, 0x6EF83B97, 0xAF7F780B, 0x4613138A,\n    0x7C3E73A6, 0xCF15E03D, 0x41576322, 0x672DF292,\n    0xB658588D, 0x33EBEFA9, 0x938CBF06, 0x06B67381,\n    0x07F192C6, 0x2BDA5855, 0x348EE0E8, 0x19DBB6E3,\n    0x3222184B, 0xB69D5DBA, 0x7E760B88, 0xAF4D8154,\n    0x007A51AD, 0x35112500, 0xC9CD2D7D, 0x4F4FB761,\n    0x694772E3, 0x694C8351, 0x4A7E3AF5, 0x67D65CE1,\n    0x9287DE92, 0x2518DB3C, 0x8CB4EC06, 0xD154D38F,\n    0xE19A26BB, 0x295EE439, 0xC50A1104, 0x2153C6A7,\n    0x82366656, 0x0713BC2F, 0x6462215A, 0x21D9BFCE,\n    0xBA8EACE6, 0xAE2DF4C1, 0x2A8D5E80, 0x3F7E52D1,\n    0x29359399, 0xFEA1D19C, 0x18879313, 0x455AFA81,\n    0xFADFE838, 0x62609838, 0xD1028839, 0x0736E92F,\n    0x3BCA22A3, 0x1485B08A, 0x2DA7900B, 0x852C156D,\n    0xE8F24803, 0x00078472, 0x13F0D332, 0x2ACFD0CF,\n    0x5F747F5C, 0x87BB1E2F, 0xA7EFCB63, 0x23F432F0,\n    0xE6CE7C5C, 0x1F954EF6, 0xB609C91B, 0x3B4571BF,\n    0xEED17DC0, 0xE556CDA0, 0xA7846A8D, 0xFF105F94,\n    0x52B7CCDE, 0x0E33E801, 0x664455EA, 0xF2C70414,\n    0x73E7B486, 0x8F830661, 0x8B59E826, 0xBB8AEDCA,\n    0xF3D70AB9, 0xD739F2B9, 0x4A04C34A, 0x88D0F089,\n    0xE02191A2, 0xD89D9C78, 0x192C2749, 0xFC43A78F,\n    0x0AAC88CB, 0x9438D42D, 0x9E280F7A, 0x36063802,\n    0x38E8D018, 0x1C42A9CB, 0x92AAFF6C, 0xA24820C5,\n    0x007F077F, 0xCE5BC543, 0x69668D58, 0x10D6FF74,\n    0xBE00F621, 0x21300BBE, 0x2E9E8F46, 0x5ACEA629,\n    0xFA1F86C7, 0x52F206B8, 0x3EDF1A75, 0x6DA8D843,\n    0xCF719928, 0x73E3891F, 0xB4B95DD6, 0xB2A42D27,\n    0xEDA20BBF, 0x1A58DBDF, 0xA449AD03, 0x6DDEF22B,\n    0x900531E6, 0x3D3BFF35, 0x5B24ABA2, 0x472B3E4C,\n    0x387F2D75, 0x4D8DBA36, 0x71CB5641, 0xE3473F3F,\n    0xF6CD4B7F, 0xBF7D1428, 0x344B64D0, 0xC5CDFCB6,\n    0xFE2E0182, 0x2C37A673, 0xDE4EB7A3, 0x63FDC933,\n    0x01DC4063, 0x611F3571, 0xD167BFAF, 0x4496596F,\n    0x3DEE0689, 0xD8704910, 0x7052A114, 0x068C9EC5,\n    0x75D0E766, 0x4D54CC20, 0xB44ECDE2, 0x4ABC653E,\n    0x2C550A21, 0x1A52C0DB, 0xCFED03D0, 0x119BAFE2,\n    0x876A6133, 0xBC232088, 0x435BA1B2, 0xAE99BBFA,\n    0xBB4F08E4, 0xA62B5F49, 0x1DA4B695, 0x336B84DE,\n    0xDC813D31, 0x00C134FB, 0x397A98E6, 0x151F0E64,\n    0xD9EB3E69, 0xD3C7DF60, 0xD2F2C336, 0x2DDD067B,\n    0xBD122835, 0xB0B3BD3A, 0xB0D54E46, 0x8641F1E4,\n    0xA0B38F96, 0x51D39199, 0x37A6AD75, 0xDF84EE41,\n    0x3C034CBA, 0xACDA62FC, 0x11923B8B, 0x45EF170A,\n};\n"
  },
  {
    "path": "tools/virtualmips/sbox.h",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2007 Christophe Fillot (cf@utc.fr)\n *\n * S-box functions.\n */\n\n#ifndef __SBOX_H__\n#define __SBOX_H__\n\n#include <sys/types.h>\n#include \"utils.h\"\n\nextern m_uint32_t sbox_array[];\n\nstatic inline m_uint32_t sbox_compute (m_uint8_t * data, int len)\n{\n    m_uint32_t hash = 0;\n\n    while (len > 0) {\n        hash ^= sbox_array[*data];\n        hash *= 3;\n        data++;\n    }\n\n    return (hash);\n}\n\nstatic forced_inline m_uint32_t sbox_u32 (m_uint32_t val)\n{\n    m_uint32_t hash = 0;\n\n    hash ^= sbox_array[(m_uint8_t) val];\n    hash *= 3;\n    val >>= 8;\n\n    hash ^= sbox_array[(m_uint8_t) val];\n    hash *= 3;\n    val >>= 8;\n\n    hash ^= sbox_array[(m_uint8_t) val];\n    hash *= 3;\n    val >>= 8;\n\n    hash ^= sbox_array[(m_uint8_t) val];\n    return (hash);\n}\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/system.h",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#ifndef __SYSTEM_H__\n#define __SYSTEM_H__\n\n#ifdef SIM_ADM5120\n#include \"adm5120.h\"\n#endif\n\n#ifdef SIM_PAVO\n#include \"pavo.h\"\n#endif\n\n#ifdef SIM_PIC32\n#include \"pic32.h\"\n#endif\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/types.h",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#ifndef __TYPES_H__\n#define __TYPES_H__\n\n#include <sys/types.h>\n\n/*types from qemu*/\ntypedef unsigned char uint8_t;\ntypedef unsigned short uint16_t;\ntypedef unsigned int uint32_t;\n\n#if defined(__linux__) || defined(__APPLE__)\ntypedef u_int64_t uint64_t;\n#endif\n\n#ifndef __sun__\ntypedef signed char int8_t;\n#endif\ntypedef signed short int16_t;\ntypedef signed int int32_t;\n\n/*used in dynamips. so just typedef again*/\n/* Common types */\ntypedef uint8_t m_uint8_t;\ntypedef int8_t m_int8_t;\n\ntypedef uint16_t m_uint16_t;\ntypedef int16_t m_int16_t;\n\ntypedef uint32_t m_uint32_t;\ntypedef int32_t m_int32_t;\n\ntypedef uint64_t m_uint64_t;\ntypedef int64_t m_int64_t;\n\ntypedef unsigned long m_iptr_t;\ntypedef m_uint64_t m_tmcnt_t;\n\n#if defined (__x86_64__) || defined(__ia64)\n/*function label address*/\ntypedef m_uint64_t m_hiptr_t;\n#else\ntypedef m_uint32_t m_hiptr_t;\n#endif\n\ntypedef void (*pvoid) (void);\n\n/* MIPS instruction */\ntypedef m_uint32_t mips_insn_t;\n\n/* True/False definitions */\n#ifndef FALSE\n#define FALSE 0\n#endif\n\n#ifndef TRUE\n#define TRUE  1\n#endif\n\n//for gdb interface\n/* Used for functions which can fail */\nenum result_t { SUCCESS, FAILURE, STALL, BUSERROR, SCFAILURE };\n\n/* Forward declarations */\ntypedef struct cpu_mips cpu_mips_t;\ntypedef struct vm_instance vm_instance_t;\ntypedef struct vdevice vdevice_t;\ntypedef struct mips_jit_tcb mips_jit_tcb_t;\ntypedef struct insn_exec_page insn_exec_page_t;\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/utils.c",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2005,2006 Christophe Fillot.  All rights reserved.\n *\n * Utility functions.\n */\n /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#define _GNU_SOURCE\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdarg.h>\n#include <unistd.h>\n#include <time.h>\n#include <signal.h>\n#include <sys/time.h>\n#include <sys/ioctl.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <sys/socket.h>\n#include <arpa/inet.h>\n#include <netdb.h>\n#include <fcntl.h>\n#include <errno.h>\n#include <assert.h>\n#ifdef __CYGWIN__\n#include <malloc.h>\n#endif\n\n#include \"utils.h\"\n\nextern FILE *log_file;\n\nunsigned int get_file_size (const char *file_path)\n{\n    struct stat statbuf;\n    if (stat (file_path, &statbuf) == -1) {\n        printf (\"Get stat on %s Error:%s\\n\", file_path, strerror (errno));\n        return (0);\n    }\n    if (S_ISDIR (statbuf.st_mode))\n        return (0);\n    if (S_ISREG (statbuf.st_mode))\n        return (statbuf.st_size);\n\n    return 0;\n}\n\n/* Dynamic sprintf */\nchar *dyn_sprintf (const char *fmt, ...)\n{\n    int n, size = 512;\n    va_list ap;\n    char *p, *p2;\n\n    if ((p = malloc (size)) == NULL) {\n        perror (\"dyn_sprintf: malloc\");\n        return NULL;\n    }\n\n    for (;;) {\n        /* Try to print in the allocated space */\n        va_start (ap, fmt);\n        n = vsnprintf (p, size, fmt, ap);\n        va_end (ap);\n\n        /* If that worked, return the string */\n        if ((n > -1) && (n < size))\n            return p;\n\n        /* Else try again with more space. */\n        if (n > -1)\n            size = n + 1;\n        else\n            size *= 2;\n        free (p);\n        if ((p2 = malloc (size)) == NULL) {\n            perror (\"dyn_sprintf: realloc\");\n            return NULL;\n        }\n\n        p = p2;\n    }\n    free (p2);\n}\n\n/* Split a string */\nint m_strsplit (char *str, char delim, char **array, int max_count)\n{\n    int i, pos = 0;\n    size_t len;\n    char *ptr;\n\n    for (i = 0; i < max_count; i++)\n        array[i] = NULL;\n\n    do {\n        if (pos == max_count)\n            goto error;\n\n        ptr = strchr (str, delim);\n        if (!ptr)\n            ptr = str + strlen (str);\n\n        len = ptr - str;\n\n        if (!(array[pos] = malloc (len + 1)))\n            goto error;\n\n        memcpy (array[pos], str, len);\n        array[pos][len] = 0;\n\n        str = ptr + 1;\n        pos++;\n    }\n    while (*ptr);\n    return (pos);\n\n  error:\n    for (i = 0; i < max_count; i++)\n        free (array[i]);\n    return (-1);\n}\n\n/* Tokenize a string */\nint m_strtok (char *str, char delim, char **array, int max_count)\n{\n    int i, pos = 0;\n    size_t len;\n    char *ptr;\n\n    for (i = 0; i < max_count; i++)\n        array[i] = NULL;\n\n    do {\n        if (pos == max_count)\n            goto error;\n\n        ptr = strchr (str, delim);\n        if (!ptr)\n            ptr = str + strlen (str);\n\n        len = ptr - str;\n\n        if (!(array[pos] = malloc (len + 1)))\n            goto error;\n\n        memcpy (array[pos], str, len);\n        array[pos][len] = 0;\n\n        while (*ptr == delim)\n            ptr++;\n\n        str = ptr;\n        pos++;\n    }\n    while (*ptr);\n\n    return (pos);\n\n  error:\n    for (i = 0; i < max_count; i++)\n        free (array[i]);\n    return (-1);\n}\n\n/* Quote a string */\nchar *m_strquote (char *buffer, size_t buf_len, char *str)\n{\n    char *p;\n\n    if (!(p = strpbrk (str, \" \\t\\\"'\")))\n        return str;\n\n    snprintf (buffer, buf_len, \"\\\"%s\\\"\", str);\n    return buffer;\n}\n\n/* Ugly function that dumps a structure in hexa and ascii. */\nvoid mem_dump (FILE * f_output, u_char * pkt, u_int len)\n{\n    u_int x, i = 0, tmp;\n\n    while (i < len) {\n        if ((len - i) > 16)\n            x = 16;\n        else\n            x = len - i;\n\n        fprintf (f_output, \"%4.4x: \", i);\n\n        for (tmp = 0; tmp < x; tmp++)\n            fprintf (f_output, \"%2.2x \", pkt[i + tmp]);\n        for (tmp = x; tmp < 16; tmp++)\n            fprintf (f_output, \"   \");\n\n        for (tmp = 0; tmp < x; tmp++) {\n            char c = pkt[i + tmp];\n\n            if (((c >= 'A') && (c <= 'Z')) || ((c >= 'a') && (c <= 'z'))\n                || ((c >= '0') && (c <= '9')))\n                fprintf (f_output, \"%c\", c);\n            else\n                fputs (\".\", f_output);\n        }\n\n        i += x;\n        fprintf (f_output, \"\\n\");\n    }\n\n    fprintf (f_output, \"\\n\");\n}\n\n/* Logging function */\nvoid m_flog (FILE * fd, char *module, char *fmt, va_list ap)\n{\n    struct timeval now;\n    static char buf[256];\n    time_t ct;\n\n    gettimeofday (&now, 0);\n    ct = now.tv_sec;\n    strftime (buf, sizeof (buf), \"%b %d %H:%M:%S\", localtime (&ct));\n    if (fd) {\n        fprintf (fd, \"%s.%03ld %s: \", buf, (long) now.tv_usec / 1000, module);\n        vfprintf (fd, fmt, ap);\n        fflush (fd);\n    }\n}\n\n#if 0\n/* Logging function */\nvoid m_log (char *module, char *fmt, ...)\n{\n    va_list ap;\n\n    va_start (ap, fmt);\n    m_flog (log_file, module, fmt, ap);\n    va_end (ap);\n}\n#endif\n\n/* Returns a line from specified file (remove trailing '\\n') */\nchar *m_fgets (char *buffer, int size, FILE * fd)\n{\n    int len;\n\n    buffer[0] = '\\0';\n    if (fgets (buffer, size, fd) == NULL)\n        return NULL;\n\n    len = strlen (buffer);\n    if (len == 0)\n        return NULL;\n\n    /* remove trailing '\\n' */\n    if (buffer[len - 1] == '\\n')\n        buffer[len - 1] = '\\0';\n\n    return buffer;\n}\n\n/* Read a file and returns it in a buffer */\nssize_t m_read_file (char *filename, char **buffer)\n{\n    char tmp[256], *ptr, *nptr;\n    size_t len, tot_len;\n    FILE *fd;\n\n    *buffer = ptr = NULL;\n    tot_len = 0;\n\n    /* Open file for reading */\n    if ((fd = fopen (filename, \"r\")) == NULL)\n        return (-1);\n\n    while ((len = fread (tmp, 1, sizeof (tmp), fd)) > 0) {\n        /* Reallocate memory */\n        nptr = realloc (ptr, tot_len + len + 1);\n        if (nptr == NULL) {\n            if (ptr)\n                free (ptr);\n            fclose (fd);\n            return (-1);\n        }\n\n        ptr = nptr;\n\n        /* Ok, memory could be allocated */\n        memcpy (&ptr[tot_len], tmp, len);\n        tot_len += len;\n    }\n\n    fclose (fd);\n    *buffer = ptr;\n    return (tot_len);\n}\n\n/* Allocate aligned memory */\nvoid *m_memalign (size_t boundary, size_t size)\n{\n    void *p;\n\n#if defined(__linux__) || defined(__APPLE__) || defined(__FreeBSD__)\n    if (posix_memalign ((void *) &p, boundary, size))\n#else\n#if defined(__CYGWIN__) || defined(SUNOS)\n    if (!(p = memalign (boundary, size)))\n#else\n    if (!(p = malloc (size)))\n#endif\n#endif\n        return NULL;\n\n    assert (((m_iptr_t) p & (boundary - 1)) == 0);\n    return p;\n}\n\n/* Block specified signal for calling thread */\nint m_signal_block (int sig)\n{\n    sigset_t sig_mask;\n    sigemptyset (&sig_mask);\n    sigaddset (&sig_mask, sig);\n    return (pthread_sigmask (SIG_BLOCK, &sig_mask, NULL));\n}\n\n/* Unblock specified signal for calling thread */\nint m_signal_unblock (int sig)\n{\n    sigset_t sig_mask;\n    sigemptyset (&sig_mask);\n    sigaddset (&sig_mask, sig);\n    return (pthread_sigmask (SIG_UNBLOCK, &sig_mask, NULL));\n}\n\n/* Set non-blocking mode on a file descriptor */\nint m_fd_set_non_block (int fd)\n{\n    int flags;\n\n    if ((flags = fcntl (fd, F_GETFL, 0)) < 1)\n        return (-1);\n\n    return (fcntl (fd, F_SETFL, flags | O_NONBLOCK));\n}\n\n/* Map a memory zone from a file */\nu_char *memzone_map_file (int fd, size_t len)\n{\n    return (mmap (NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd,\n            (off_t) 0));\n}\n\n/* Map a memory zone from a file, with copy-on-write (COW) */\nu_char *memzone_map_cow_file (int fd, size_t len)\n{\n    return (mmap (NULL, len, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd,\n            (off_t) 0));\n}\n\n/* Create a file to serve as a memory zone */\nint memzone_create_file (char *filename, size_t len, u_char ** ptr)\n{\n    int fd;\n\n    if ((fd = open (filename, O_CREAT | O_RDWR, S_IRWXU)) == -1) {\n        perror (\"memzone_create_file: open\");\n        return (-1);\n    }\n\n    if (ftruncate (fd, len) == -1) {\n        perror (\"memzone_create_file: ftruncate\");\n        close (fd);\n        return (-1);\n    }\n\n    *ptr = memzone_map_file (fd, len);\n\n    if (!*ptr) {\n        close (fd);\n        fd = -1;\n    }\n\n    return (fd);\n}\n\n/* Open a file to serve as a COW memory zone */\nint memzone_open_cow_file (char *filename, size_t len, u_char ** ptr)\n{\n    int fd;\n\n    if ((fd = open (filename, O_RDWR, S_IRWXU)) == -1) {\n        perror (\"memzone_open_file: open\");\n        return (-1);\n    }\n\n    *ptr = memzone_map_cow_file (fd, len);\n\n    if (!*ptr) {\n        close (fd);\n        fd = -1;\n    }\n\n    return (fd);\n}\n\n/* Open a file and map it in memory */\nint memzone_open_file (char *filename, u_char ** ptr, off_t * fsize)\n{\n    struct stat fprop;\n    int fd;\n\n    if ((fd = open (filename, O_RDWR, S_IRWXU)) == -1)\n        return (-1);\n\n    if (fstat (fd, &fprop) == -1)\n        goto err_fstat;\n\n    *fsize = fprop.st_size;\n    if (!(*ptr = memzone_map_file (fd, *fsize)))\n        goto err_mmap;\n\n    return (fd);\n\n  err_mmap:\n  err_fstat:\n    close (fd);\n    return (-1);\n}\n\n/* Compute NVRAM checksum */\nm_uint16_t nvram_cksum (m_uint16_t * ptr, size_t count)\n{\n    m_uint32_t sum = 0;\n\n    while (count > 1) {\n        sum = sum + ntohs (*ptr);\n        ptr++;\n        count -= sizeof (m_uint16_t);\n    }\n\n    if (count > 0)\n        sum = sum + ((ntohs (*ptr) & 0xFF) << 8);\n\n    while (sum >> 16)\n        sum = (sum & 0xffff) + (sum >> 16);\n\n    return (~sum);\n}\n\n/* Byte-swap a memory block */\nvoid mem_bswap32 (void *ptr, size_t len)\n{\n    m_uint32_t *p = ptr;\n    size_t count = len >> 2;\n    int i;\n\n    for (i = 0; i < count; i++, p++)\n        *p = swap32 (*p);\n}\n\n/* Reverse a byte */\nm_uint8_t m_reverse_u8 (m_uint8_t val)\n{\n    m_uint8_t res = 0;\n    int i;\n\n    for (i = 0; i < 8; i++)\n        if (val & (1 << i))\n            res |= 1 << (7 - i);\n\n    return (res);\n}\n\nvoid SubstituteLLx (char *out, const char *text, int maxlen)\n{\n    int i;\n    for (i = 0; i < maxlen && text[i]; i++) {\n        out[i] = text[i];\n    }\n    out[i] = text[i];\n}\n\n/*****************************************************************\n * Debug\n * Print a debug message, if flag is enabled.  Like printf,\n * only with an extra argument on the front.\n * to output debug infomation , you should excute \"simos -d [flag]\"\n ****************************************************************/\nvoid Debug (char flag, char *format, ...)\n{\n    // if (DebugIsEnabled(flag)) {\n    char llformat[1024];\n    va_list ap;\n    va_start (ap, format);\n\n    SubstituteLLx (llformat, format, 1024);\n\n    /* Make this go to stderr also...  */\n    vfprintf (stderr, llformat, ap);\n\n    //vCPUPrint(llformat, ap);\n    fprintf (stderr, \"\\r\");\n    fflush (stderr);\n    va_end (ap);\n\n    //}\n}\n"
  },
  {
    "path": "tools/virtualmips/utils.h",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#ifndef __UTILS_H__\n#define __UTILS_H__\n\n#include <stdarg.h>\n#include <sys/types.h>\n#include <sys/mman.h>\n#include <sys/time.h>\n#include <time.h>\n#include <netinet/in.h>\n#include <stdio.h>\n#include <assert.h>\n\n#include \"config.h\"\n#include \"types.h\"\n#include \"system.h\"\n\n/* Endianness */\n#define ARCH_BIG_ENDIAN     0x4321\n#define ARCH_LITTLE_ENDIAN  0x1234\n\n#if defined(PPC) || defined(__powerpc__) || defined(__ppc__)\n#define HOST_BYTE_ORDER ARCH_BIG_ENDIAN\n#elif defined(__sparc) || defined(__sparc__)\n#define HOST_BYTE_ORDER ARCH_BIG_ENDIAN\n#elif defined(__alpha) || defined(__alpha__)\n#define HOST_BYTE_ORDER ARCH_LITTLE_ENDIAN\n#elif defined(__i386) || defined(__i386__) || defined(i386)\n#define HOST_BYTE_ORDER ARCH_LITTLE_ENDIAN\n#elif defined(__x86_64__)\n#define HOST_BYTE_ORDER ARCH_LITTLE_ENDIAN\n#endif\n\n#ifndef HOST_BYTE_ORDER\n#error Please define your architecture in utils.h!\n#endif\n\n#if __GNUC__ > 2\n#define forced_inline inline __attribute__((always_inline))\n#define no_inline __attribute__ ((noinline))\n/* http://kerneltrap.org/node/4705 */\n#define likely(x)    __builtin_expect((x),1)\n#define unlikely(x)  __builtin_expect((x),0)\n#else\n#define forced_inline inline\n#define no_inline\n#define likely(x)    (x)\n#define unlikely(x)  (x)\n#endif\n\n#define fastcall   __attribute__((regparm(3)))\n#define asmlinkage __attribute__((regparm(0)))\n\n#define ASSERT(a,format,args...)  do{ if ((format!=NULL)&&(!(a)))   fprintf(stderr,format, ##args); assert((a));} while(0)\n\n/* BOOT METHOD */\nenum {\n    BOOT_BINARY = 1,\n    BOOT_ELF = 2,\n};\n/* BOOT FROM */\nenum {\n    BOOT_FROM_NOR_FLASH = 1,\n    BOOT_FROM_NAND_FLASH = 2,\n};\n/* FLASH TYPE */\nenum {\n    FLASH_TYPE_NOR_FLASH = 1,\n    FLASH_TYPE_NAND_FLASH = 2,\n};\n\n/* Size of a field in a structure */\n#define SIZEOF(st,field) (sizeof(((st *)NULL)->field))\n\n/* Compute offset of a field in a structure */\n#define OFFSET(st,f)     ((long)&((st *)(NULL))->f)\n/* Max and min macro */\n#define m_max(a,b) (((a) > (b)) ? (a) : (b))\n#define m_min(a,b) (((a) < (b)) ? (a) : (b))\n\n/* MTS mapping info */\ntypedef struct {\n    m_va_t vaddr;\n    m_pa_t paddr;\n    m_uint64_t len;\n\n    // m_uint32_t cached;\n    m_uint32_t tlb_index;\n    m_uint8_t mapped;\n    m_uint8_t dirty;\n    m_uint8_t valid;\n    m_uint32_t asid;\n    m_uint8_t g_bit;\n\n} mts_map_t;\n\n/* Invalid VTLB entry */\n#define MTS_INV_ENTRY_MASK  0x00000001\n\n/* MTS entry flags */\n#define MTS_FLAG_DEV   0x000000001      /* Virtual device used */\n#define MTS_FLAG_COW   0x000000002      /* Copy-On-Write */\n#define MTS_FLAG_EXEC  0x000000004      /* Exec page */\n\n/* Virtual TLB entry (32-bit MMU) */\n\nstruct mts32_entry {\n    m_uint32_t gvpa;            /* Guest Virtual Page Address */\n    m_uint32_t gppa;            /* Guest Physical Page Address */\n    m_iptr_t hpa;               /* Host Page Address */\n    m_uint32_t asid;\n    m_uint8_t g_bit;\n    m_uint8_t dirty_bit;\n    m_uint8_t mapped;\n    m_uint32_t flags;           /* Flags */\n} __attribute__ ((aligned (16)));\ntypedef struct mts32_entry mts32_entry_t;\n\n/* Virtual TLB entry (64-bit MMU) */\n\nstruct mts64_entry {\n    m_va_t gvpa;                /* Guest Virtual Page Address */\n    m_pa_t gppa;                /* Guest Physical Page Address */\n    m_iptr_t hpa;               /* Host Page Address */\n    m_uint32_t flags;           /* Flags */\n} __attribute__ ((aligned (16)));\ntypedef struct mts64_entry mts64_entry_t;\n\n/* Host register allocation */\n#define HREG_FLAG_ALLOC_LOCKED  1\n#define HREG_FLAG_ALLOC_FORCED  2\n\nstruct hreg_map {\n    int hreg, vreg;\n    int flags;\n    struct hreg_map *prev, *next;\n};\n\n/* Global logfile */\nextern FILE *log_file;\n\n/* Check status of a bit */\nstatic inline int check_bit (u_int old, u_int new, u_int bit)\n{\n    int mask = 1 << bit;\n\n    if ((old & mask) && !(new & mask))\n        return (1);             /* bit unset */\n\n    if (!(old & mask) && (new & mask))\n        return (2);             /* bit set */\n\n    /* no change */\n    return (0);\n}\n\n/* Sign-extension */\n#if DATA_WIDTH==64\nstatic forced_inline m_int64_t sign_extend (m_int64_t x, int len)\n#elif DATA_WIDTH==32\nstatic forced_inline m_int32_t sign_extend (m_int32_t x, int len)\n#else\n#error Undefined DATA_WIDTH\n#endif\n{\n    len = DATA_WIDTH - len;\n    return (x << len) >> len;\n}\n\n/* Sign-extension (32-bit) */\nstatic forced_inline m_int32_t sign_extend_32 (m_int32_t x, int len)\n{\n    len = 32 - len;\n    return (x << len) >> len;\n}\n\n/* Extract bits from a 32-bit values */\nstatic inline int bits (m_uint32_t val, int start, int end)\n{\n    return ((val >> start) & ((1 << (end - start + 1)) - 1));\n}\n\n/* Normalize a size */\nstatic inline u_int normalize_size (u_int val, u_int nb, int shift)\n{\n    return (((val + nb - 1) & ~(nb - 1)) >> shift);\n}\n\n/* Use builtin swapxx() on OS other than Linux and FreeBSD. */\n#if defined(__linux__) || defined(__FreeBSD__)\n/* Convert a 16-bit number between little and big endian */\nstatic forced_inline m_uint16_t swap16 (m_uint16_t value)\n{\n    return ((value >> 8) | ((value & 0xFF) << 8));\n}\n\n/* Convert a 32-bit number between little and big endian */\nstatic forced_inline m_uint32_t swap32 (m_uint32_t value)\n{\n    m_uint32_t result;\n\n    result = value >> 24;\n    result |= ((value >> 16) & 0xff) << 8;\n    result |= ((value >> 8) & 0xff) << 16;\n    result |= (value & 0xff) << 24;\n    return (result);\n}\n\n/* Convert a 64-bit number between little and big endian */\nstatic forced_inline m_uint64_t swap64 (m_uint64_t value)\n{\n    m_uint64_t result;\n\n    result = (m_uint64_t) swap32 (value & 0xffffffff) << 32;\n    result |= swap32 (value >> 32);\n    return (result);\n}\n#endif /* __linux__ || __FreeBSD__ */\n\n/* Get current time in number of msec since epoch */\nstatic inline m_tmcnt_t m_gettime (void)\n{\n    struct timeval tvp;\n\n    gettimeofday (&tvp, NULL);\n    return (((m_tmcnt_t) tvp.tv_sec * 1000) +\n        ((m_tmcnt_t) tvp.tv_usec / 1000));\n}\n\n/* Get current time in number of usec since epoch */\nstatic inline m_tmcnt_t m_gettime_usec (void)\n{\n    struct timeval tvp;\n\n    gettimeofday (&tvp, NULL);\n    return (((m_tmcnt_t) tvp.tv_sec * 1000000) + (m_tmcnt_t) tvp.tv_usec);\n}\n\n#ifdef __CYGWIN__\n#define GET_TIMEZONE _timezone\n#else\n#define GET_TIMEZONE timezone\n#endif\n\n/* Get current time in number of ms (localtime) */\nstatic inline m_tmcnt_t m_gettime_adj (void)\n{\n    struct timeval tvp;\n    struct tm tmx;\n    time_t gmt_adjust;\n    time_t ct;\n\n    gettimeofday (&tvp, NULL);\n    ct = tvp.tv_sec;\n    localtime_r (&ct, &tmx);\n\n#if defined(__CYGWIN__) || defined(SUNOS)\n    gmt_adjust = -(tmx.tm_isdst ? GET_TIMEZONE - 3600 : GET_TIMEZONE);\n#else\n    gmt_adjust = tmx.tm_gmtoff;\n#endif\n\n    tvp.tv_sec += gmt_adjust;\n    return (((m_tmcnt_t) tvp.tv_sec * 1000) +\n        ((m_tmcnt_t) tvp.tv_usec / 1000));\n}\n\n//#if 0\n#define DEBUGGING_DISABLED\n//#endif\n#ifndef DEBUGGING_DISABLED\n#define SIM_DEBUG(arg1) Debug arg1\n#else\n#define SIM_DEBUG(arg1)\n#endif\n\n/*return a file size*/\nunsigned int get_file_size (const char *filename);\n\n/* Dynamic sprintf */\nchar *dyn_sprintf (const char *fmt, ...);\n\n/* Split a string */\nint m_strsplit (char *str, char delim, char **array, int max_count);\n\n/* Tokenize a string */\nint m_strtok (char *str, char delim, char **array, int max_count);\n\n/* Quote a string */\nchar *m_strquote (char *buffer, size_t buf_len, char *str);\n\n/* Ugly function that dumps a structure in hexa and ascii. */\nvoid mem_dump (FILE * f_output, u_char * pkt, u_int len);\n\n/* Logging function */\nvoid m_flog (FILE * fd, char *module, char *fmt, va_list ap);\n\n/* Logging function */\n//void m_log(char *module,char *fmt,...);\n\n/* Returns a line from specified file (remove trailing '\\n') */\nchar *m_fgets (char *buffer, int size, FILE * fd);\n\n/* Read a file and returns it in a buffer */\nssize_t m_read_file (char *filename, char **buffer);\n\n/* Allocate aligned memory */\nvoid *m_memalign (size_t boundary, size_t size);\n\n/* Block specified signal for calling thread */\nint m_signal_block (int sig);\n\n/* Unblock specified signal for calling thread */\nint m_signal_unblock (int sig);\n\n/* Set non-blocking mode on a file descriptor */\nint m_fd_set_non_block (int fd);\n\n/* Map a memory zone from a file */\nu_char *memzone_map_file (int fd, size_t len);\n\n/* Map a memory zone from a file, with copy-on-write (COW) */\nu_char *memzone_map_cow_file (int fd, size_t len);\n\n/* Create a file to serve as a memory zone */\nint memzone_create_file (char *filename, size_t len, u_char ** ptr);\n\n/* Open a file to serve as a COW memory zone */\nint memzone_open_cow_file (char *filename, size_t len, u_char ** ptr);\n\n/* Open a file and map it in memory */\nint memzone_open_file (char *filename, u_char ** ptr, off_t * fsize);\n\n/* Compute NVRAM checksum */\nm_uint16_t nvram_cksum (m_uint16_t * ptr, size_t count);\n\n/* Byte-swap a memory block */\nvoid mem_bswap32 (void *ptr, size_t len);\n\n/* Reverse a byte */\nm_uint8_t m_reverse_u8 (m_uint8_t val);\nvoid Debug (char flag, char *format, ...);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/vm.c",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)\n *\n * Virtual machine abstraction.\n */\n /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#define _GNU_SOURCE\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n#include <errno.h>\n#include <fcntl.h>\n#include <sys/types.h>\n#include <assert.h>\n\n#include \"device.h\"\n#include \"cpu.h\"\n#include \"vm.h\"\n#include \"dev_vtty.h\"\n#include \"debug.h\"\n\n/* Get VM type */\nchar *vm_get_type (vm_instance_t * vm)\n{\n    char *machine;\n\n    switch (vm->type) {\n    case VM_TYPE_SWARM:\n        machine = \"swarm\";\n        break;\n    case VM_TYPE_ADM5120:\n        machine = \"ADM5120\";\n        break;\n    case VM_TYPE_PAVO:\n        machine = \"PAVO\";\n        break;\n    case VM_TYPE_PIC32:\n        machine = \"PIC32\";\n        break;\n    default:\n        machine = \"unknown\";\n        break;\n    }\n    return machine;\n}\n\n/* Get platform type */\nchar *vm_get_platform_type (vm_instance_t * vm)\n{\n    char *machine;\n\n    switch (vm->type) {\n    case VM_TYPE_SWARM:\n        machine = \"swarm\";\n        break;\n    case VM_TYPE_ADM5120:\n        machine = \"ADM5120\";\n        break;\n    case VM_TYPE_PIC32:\n        machine = \"PIC32\";\n        break;\n    default:\n        machine = \"VM\";\n        break;\n    }\n\n    return machine;\n}\n\n/* Generate a filename for use by the instance */\nstatic char *vm_build_filename (vm_instance_t * vm, char *name)\n{\n    char *filename;\n\n    filename = dyn_sprintf (\"%s-%s\", vm->name, name);\n\n    assert (filename != NULL);\n    return filename;\n}\n\n/* Log a message */\nvoid vm_flog (vm_instance_t * vm, char *module, char *format, va_list ap)\n{\n    if (vm->log_fd)\n        m_flog (vm->log_fd, module, format, ap);\n}\n\n/* Log a message */\nvoid vm_log (vm_instance_t * vm, char *module, char *format, ...)\n{\n    va_list ap;\n\n    if (vm->log_fd) {\n        va_start (ap, format);\n        vm_flog (vm, module, format, ap);\n        va_end (ap);\n    }\n}\n\n/* Close the log file */\nint vm_close_log (vm_instance_t * vm)\n{\n    if (vm->log_fd)\n        fclose (vm->log_fd);\n\n    free (vm->log_file);\n\n    vm->log_file = NULL;\n    vm->log_fd = NULL;\n    return (0);\n}\n\n/* Create the log file */\nint vm_create_log (vm_instance_t * vm)\n{\n    if (vm->log_file_enabled) {\n        vm_close_log (vm);\n\n        vm->log_file = vm_build_filename (vm, \"log.txt\");\n        if (! vm->log_file)\n            return (-1);\n\n        vm->log_fd = fopen (vm->log_file, \"w\");\n        if (! vm->log_fd) {\n            fprintf (stderr, \"VM %s: unable to create log file '%s'\\n\",\n                vm->name, vm->log_file);\n            free (vm->log_file);\n            vm->log_file = NULL;\n            return (-1);\n        }\n    }\n\n    return (0);\n}\n\n/* Error message */\nvoid vm_error (vm_instance_t * vm, char *format, ...)\n{\n    char buffer[2048];\n    va_list ap;\n\n    va_start (ap, format);\n    vsnprintf (buffer, sizeof (buffer), format, ap);\n    va_end (ap);\n\n    fprintf (stderr, \"%s '%s': %s\", vm_get_platform_type (vm), vm->name,\n        buffer);\n}\n\n/* Create a new VM instance */\nvm_instance_t *vm_create (const char *name, int machine_type)\n{\n    vm_instance_t *vm;\n    int i;\n\n    vm = malloc (sizeof (*vm));\n    if (!vm) {\n        fprintf (stderr, \"VM %s: unable to create new instance!\\n\", name);\n        return NULL;\n    }\n\n    memset (vm, 0, sizeof (*vm));\n    vm->type = machine_type;\n    vm->status = VM_STATUS_HALTED;\n    vm->jit_use = 0;\n    vm->vtty_type[0] = VTTY_TYPE_TERM;\n    for (i=1; i<NVTTY; i++)\n        vm->vtty_type[i] = VTTY_TYPE_NONE;\n    //vm->timer_irq_check_itv = VM_TIMER_IRQ_CHECK_ITV;\n    //vm->log_file_enabled = TRUE;\n\n    vm->name = strdup (name);\n    if (!name) {\n        fprintf (stderr, \"VM %s: unable to store instance name!\\n\", name);\n        goto err_name;\n    }\n\n    /* create log file */\n    if (vm_create_log (vm) == -1) {\n        free (vm->name);\n      err_name:\n        free (vm);\n        return NULL;\n    }\n    return vm;\n}\n\n/*\n * Shutdown hardware resources used by a VM.\n * The CPU must have been stopped.\n */\nstatic int vm_hardware_shutdown (vm_instance_t * vm)\n{\n    //int i;\n\n    if ((vm->status == VM_STATUS_HALTED) || !vm->cpu_group) {\n        vm_log (vm, \"VM\", \"trying to shutdown an inactive VM.\\n\");\n        return (-1);\n    }\n\n    vm_log (vm, \"VM\", \"shutdown procedure engaged.\\n\");\n\n    /* Mark the VM as halted */\n    vm->status = VM_STATUS_HALTED;\n\n    /* Disable NVRAM operations */\n    // vm->nvram_extract_config = NULL;\n    //  vm->nvram_push_config = NULL;\n\n    /* Free the object list */\n    // vm_object_free_list(vm);\n\n    /* Free resources used by PCI busses */\n    //  vm_log(vm,\"VM\",\"removing PCI busses.\\n\");\n    //  pci_io_data_remove(vm,vm->pci_io_space);\n    //  pci_bus_remove(vm->pci_bus[0]);\n    //  pci_bus_remove(vm->pci_bus[1]);\n    //  vm->pci_bus[0] = vm->pci_bus[1] = NULL;\n\n    /* Free the PCI bus pool */\n    /* for(i=0;i<VM_PCI_POOL_SIZE;i++) {\n     * if (vm->pci_bus_pool[i] != NULL) {\n     * pci_bus_remove(vm->pci_bus_pool[i]);\n     * vm->pci_bus_pool[i] = NULL;\n     * }\n     * }     */\n\n    /* Remove the IRQ routing vectors */\n    vm->set_irq = NULL;\n    vm->clear_irq = NULL;\n\n    /* Delete the VTTY for Console and AUX ports */\n    vm_log (vm, \"VM\", \"deleting VTTY.\\n\");\n    vm_delete_vtty (vm);\n\n    /* Delete system CPU group */\n    vm_log (vm, \"VM\", \"deleting system CPUs.\\n\");\n    cpu_group_delete (vm->cpu_group);\n    vm->cpu_group = NULL;\n    vm->boot_cpu = NULL;\n\n    vm_log (vm, \"VM\", \"shutdown procedure completed.\\n\");\n    return (0);\n}\n\n/* Free resources used by a VM */\nvoid vm_free (vm_instance_t * vm)\n{\n    if (vm != NULL) {\n        /* Free hardware resources */\n        vm_hardware_shutdown (vm);\n\n        /* Close log file */\n        vm_close_log (vm);\n\n        /* Remove the lock file */\n        // vm_release_lock(vm,TRUE);\n\n        /* Free all chunks */\n        // vm_chunk_free_all(vm);\n\n        /* Free various elements */\n        // free(vm->ghost_ram_filename);\n        //   free(vm->sym_filename);\n        //free(vm->ios_image);\n        // free(vm->ios_config);\n        //free(vm->rom_filename);\n        free (vm->name);\n        free (vm);\n    }\n}\n\n/*\n * Initialize RAM\n */\nint vm_ram_init (vm_instance_t * vm, m_pa_t paddr)\n{\n    m_uint32_t len;\n\n    len = vm->ram_size * 1024;\n\n#ifdef SIM_PAVO\n/*\nWhy plus 0x2000 (8k) for PAVO??\nIt seems that jz4740 has an extra 8k boot memory.\nI am not sure. But uboot use the extra memory space beyond 64M memory space.\nSo I just add 0x2000 to ram.\n*/\n    len += 0x2000;\n#endif\n    return (dev_ram_init (vm, \"ram\", paddr, len));\n}\n\n/* Initialize VTTY */\nint vm_init_vtty (vm_instance_t * vm)\n{\n    int i;\n\n    /* Create Console and AUX ports */\n    vm->vtty_con[0] = vtty_create (vm, \"Console port\",\n        vm->vtty_type[0], vm->vtty_tcp_port[0],\n        &vm->vtty_serial_option[0]);\n\n    for (i=1; i<NVTTY; i++)\n        vm->vtty_con[i] = vtty_create (vm, \"UART port\",\n            vm->vtty_type[i], vm->vtty_tcp_port[i],\n            &vm->vtty_serial_option[i]);\n    return (0);\n}\n\n/* Delete VTTY */\nvoid vm_delete_vtty (vm_instance_t * vm)\n{\n    int i;\n\n    for (i=0; i<NVTTY; i++) {\n        vtty_delete (vm->vtty_con[i]);\n        vm->vtty_con[i] = NULL;\n    }\n}\n\n/* Bind a device to a virtual machine */\nint vm_bind_device (vm_instance_t * vm, struct vdevice *dev)\n{\n    struct vdevice **cur;\n    u_int i;\n\n    /*\n     * Add this device to the device array. The index in the device array\n     * is used by the MTS subsystem.\n     */\n    for (i = 0; i < VM_DEVICE_MAX; i++)\n        if (!vm->dev_array[i])\n            break;\n\n    if (i == VM_DEVICE_MAX) {\n        fprintf (stderr, \"VM: vm_bind_device: device table full.\\n\");\n        return (-1);\n    }\n\n    vm->dev_array[i] = dev;\n    dev->id = i;\n\n    /*\n     * Add it to the linked-list (devices are ordered by physical addresses).\n     */\n    for (cur = &vm->dev_list; *cur; cur = &(*cur)->next)\n        if ((*cur)->phys_addr > dev->phys_addr)\n            break;\n\n    dev->next = *cur;\n    if (*cur)\n        (*cur)->pprev = &dev->next;\n    dev->pprev = cur;\n    *cur = dev;\n    return (0);\n}\n\n/* Unbind a device from a virtual machine */\nint vm_unbind_device (vm_instance_t * vm, struct vdevice *dev)\n{\n    u_int i;\n\n    if (!dev || !dev->pprev)\n        return (-1);\n\n    /* Remove the device from the linked list */\n    if (dev->next)\n        dev->next->pprev = dev->pprev;\n\n    *(dev->pprev) = dev->next;\n\n    /* Remove the device from the device array */\n    for (i = 0; i < VM_DEVICE_MAX; i++)\n        if (vm->dev_array[i] == dev) {\n            vm->dev_array[i] = NULL;\n            break;\n        }\n\n    /* Clear device list info */\n    dev->next = NULL;\n    dev->pprev = NULL;\n    return (0);\n}\n\n/* Map a device at the specified physical address */\nint vm_map_device (vm_instance_t * vm, struct vdevice *dev, m_pa_t base_addr)\n{\n#if 0\n    /* Suspend VM activity */\n    vm_suspend (vm);\n\n    if (cpu_group_sync_state (vm->cpu_group) == -1) {\n        fprintf (stderr, \"VM%u: unable to sync with system CPUs.\\n\",\n            vm->instance_id);\n        return (-1);\n    }\n#endif\n\n    /* Unbind the device if it was already active */\n    vm_unbind_device (vm, dev);\n\n    /* Map the device at the new base address and rebuild MTS */\n    dev->phys_addr = base_addr;\n    vm_bind_device (vm, dev);\n    cpu_group_rebuild_mts (vm->cpu_group);\n\n#if 0\n    vm_resume (vm);\n#endif\n    return (0);\n}\n\n/* Suspend a VM instance */\nint vm_suspend (vm_instance_t * vm)\n{\n    if (vm->status == VM_STATUS_RUNNING) {\n        cpu_group_save_state (vm->cpu_group);\n        cpu_group_set_state (vm->cpu_group, CPU_STATE_SUSPENDED);\n        vm->status = VM_STATUS_SUSPENDED;\n    }\n    return (0);\n}\n\n/* Resume a VM instance */\nint vm_resume (vm_instance_t * vm)\n{\n    if (vm->status == VM_STATUS_SUSPENDED) {\n        cpu_group_restore_state (vm->cpu_group);\n        vm->status = VM_STATUS_RUNNING;\n    }\n    return (0);\n}\n\n/* Stop an instance */\nint vm_stop (vm_instance_t * vm)\n{\n    cpu_group_stop_all_cpu (vm->cpu_group);\n    vm->status = VM_STATUS_SHUTDOWN;\n    return (0);\n}\n\n/* Monitor an instance periodically */\nvoid vm_monitor (vm_instance_t * vm)\n{\n    while (vm->status != VM_STATUS_SHUTDOWN)\n        usleep (1000);\n}\n"
  },
  {
    "path": "tools/virtualmips/vm.h",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)\n *\n * Virtual machine abstraction.\n */\n /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *\n  * This file is part of the virtualmips distribution.\n  * See LICENSE file for terms of the license.\n  *\n  */\n\n#ifndef __VM_H__\n#define __VM_H__\n\n#include <pthread.h>\n\n#include \"cpu.h\"\n#include \"dev_vtty.h\"\n#include \"system.h\"\n#include \"gdb_interface.h\"\n\n#define VM_PAGE_SHIFT  12\n#define VM_PAGE_SIZE   (1 << VM_PAGE_SHIFT)\n#define VM_PAGE_IMASK  (VM_PAGE_SIZE - 1)\n#define VM_PAGE_MASK   (~(VM_PAGE_IMASK))\n\n/* Maximum number of devices per VM */\n#define VM_DEVICE_MAX  (1 << 6)\n/* VM types */\nenum {\n    VM_TYPE_SWARM = 0,\n    VM_TYPE_ADM5120,\n    VM_TYPE_PIC32,\n    VM_TYPE_PAVO,\n};\n\n/* VM instance status */\nenum {\n    VM_STATUS_HALTED = 0,       /* VM is halted and no HW resources are used */\n    VM_STATUS_SHUTDOWN,         /* Shutdown procedure engaged */\n    VM_STATUS_RUNNING,          /* VM is running */\n    VM_STATUS_SUSPENDED,        /* VM is suspended */\n};\n\n/* VM instance */\nstruct vm_instance {\n    char *name;\n    int type;\n    int status;                 /* Instance status */\n\n    char *log_file;             /* Log filename */\n    int log_file_enabled;       /* Logging enabled */\n    u_int ram_size;             /* RAM size in Mb */\n    //u_int rom_size;           /* ROM size in Mb */\n    //char *rom_filename;       /* ROM filename */\n    //m_pa_t rom_address;       /* ROM phy address */\n\n    u_int flash_size;           /* FLASH size in Mb */\n    char *flash_filename;       /* FLASH filename */\n    m_pa_t flash_address;       /* FLASH phy address */\n    u_int flash_type;           /* NAND Flash OR NOR FLASH */\n\n    u_int boot_method;          /* binary or elf */\n    char *kernel_filename;\n    u_int boot_from;\n\n    char *configure_filename;\n\n    FILE *lock_fd, *log_fd;     /* Lock/Log file descriptors */\n    int debug_level;            /* Debugging Level */\n    u_int trace_address;        /* Trace this address */\n    int jit_use;                /* CPUs use JIT */\n\n    /* Basic hardware: system CPU */\n    cpu_group_t *cpu_group;\n    cpu_mips_t *boot_cpu;\n\n    /* Memory mapped devices */\n    struct vdevice *dev_list;\n    struct vdevice *dev_array[VM_DEVICE_MAX];\n\n    /* IRQ routing */\n    void (*set_irq) (vm_instance_t * vm, u_int irq);\n    void (*clear_irq) (vm_instance_t * vm, u_int irq);\n\n    /* Console VTTY type and parameters */\n#define NVTTY 6\n    int vtty_type [NVTTY];\n    int vtty_tcp_port[NVTTY];\n    vtty_serial_option_t vtty_serial_option[NVTTY];\n    /* Virtual TTY for Console and AUX ports */\n    vtty_t *vtty_con [NVTTY];\n\n    /* Specific hardware data */\n    void *hw_data;\n\n    /* gdb interface */\n    m_uint32_t gdb_debug, gdb_port;\n    int gdb_interact_sock;      //connect socket\n    int gdb_listen_sock;        //listen socket\n    int gdb_debug_from_poll;\n    virtual_breakpoint_t *breakpoint_head, *breakpoint_tail;\n    int mipsy_debug_mode;\n    int mipsy_break_nexti;\n};\n\nchar *vm_get_type (vm_instance_t * vm);\nchar *vm_get_platform_type (vm_instance_t * vm);\nvoid vm_flog (vm_instance_t * vm, char *module, char *format, va_list ap);\nvoid vm_log (vm_instance_t * vm, char *module, char *format, ...);\nint vm_close_log (vm_instance_t * vm);\nint vm_create_log (vm_instance_t * vm);\nvoid vm_error (vm_instance_t * vm, char *format, ...);\nvm_instance_t *vm_create (const char *name, int machine_type);\nvoid vm_free (vm_instance_t * vm);\nint vm_ram_init (vm_instance_t * vm, m_pa_t paddr);\nint vm_init_vtty (vm_instance_t * vm);\nvoid vm_delete_vtty (vm_instance_t * vm);\nint vm_bind_device (vm_instance_t * vm, struct vdevice *dev);\nint vm_unbind_device (vm_instance_t * vm, struct vdevice *dev);\nint vm_map_device (vm_instance_t * vm, struct vdevice *dev, m_pa_t base_addr);\nint vm_suspend (vm_instance_t * vm);\nint vm_resume (vm_instance_t * vm);\nint vm_stop (vm_instance_t * vm);\nvoid vm_monitor (vm_instance_t * vm);\n#endif\n"
  },
  {
    "path": "tools/virtualmips/vp_clock.c",
    "content": " /*\n  * Copyright (C) yajin 2008<yajinzhou@gmail.com >\n  *     \n  * This file is part of the virtualmips distribution. \n  * See LICENSE file for terms of the license. \n  *\n  */\n\n#include <stdlib.h>\n#include <string.h>\n#include \"utils.h\"\n#include \"vp_clock.h\"\n\nstatic int use_rt_clock;\nvp_clock_t *rt_clock;\nvp_clock_t *vm_clock;\n\nvoid init_get_clock (void)\n{\n    use_rt_clock = 0;\n#if defined(__linux__)\n    {\n        struct timespec ts;\n        if (clock_gettime (CLOCK_MONOTONIC, &ts) == 0) {\n            use_rt_clock = 1;\n        }\n    }\n#endif\n}\n\n/*ns*/\nstatic m_int64_t get_clock (void)\n{\n#if defined(__linux__)\n    if (use_rt_clock) {\n        struct timespec ts;\n        clock_gettime (CLOCK_MONOTONIC, &ts);\n        return ts.tv_sec * 1000000000LL + ts.tv_nsec;\n    } else\n#endif\n    {\n        /* XXX: using gettimeofday leads to problems if the date\n         * changes, so it should be avoided. */\n        struct timeval tv;\n        gettimeofday (&tv, NULL);\n        return tv.tv_sec * 1000000000LL + (tv.tv_usec * 1000);\n    }\n}\n\n/*ms*/\nm_int64_t vp_get_clock (vp_clock_t * clock)\n{\n    switch (clock->type) {\n    case VP_TIMER_REALTIME:\n        return get_clock () / 1000000;\n    default:\n    case VP_TIMER_VIRTUAL:\n        ASSERT (0, \"not support yet\\n\");\n    }\n    return 0;\n}\n\nvp_clock_t *vp_new_clock (int type)\n{\n    vp_clock_t *clock;\n    clock = malloc (sizeof (vp_clock_t));\n    memset (clock, 0x0, sizeof (*clock));\n    if (!clock)\n        return NULL;\n    clock->type = type;\n    return clock;\n}\n"
  },
  {
    "path": "tools/virtualmips/vp_clock.h",
    "content": " /*\n  * Copyright (C) yajin 2008<yajinzhou@gmail.com >\n  *     \n  * This file is part of the virtualmips distribution. \n  * See LICENSE file for terms of the license. \n  *\n  */\n\n#ifndef __VP_CLOCK_H__\n#define __VP_CLOCK_H__\n\n#include \"utils.h\"\n/*clock utils from qemu*/\n\n#define VP_TIMER_REALTIME 0\n#define VP_TIMER_VIRTUAL  1\n\nstruct vp_clock {\n    int type;\n    /* XXX: add frequency */\n};\ntypedef struct vp_clock vp_clock_t;\n\nextern vp_clock_t *rt_clock;\nextern vp_clock_t *vm_clock;\n\nvoid init_get_clock (void);\nvp_clock_t *vp_new_clock (int type);\nm_int64_t vp_get_clock (vp_clock_t * clock);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/vp_lock.h",
    "content": " /*\n  * Copyright (C) yajin 2008<yajinzhou@gmail.com >\n  *     \n  * This file is part of the virtualmips distribution. \n  * See LICENSE file for terms of the license. \n  *\n  */\n\n#ifndef __VP_LOCK_H__\n#define __VP_LOCK_H__\n\n/*testandset from QEMU*/\n\n#ifdef __i386__\nstatic inline int testandset (int *p)\n{\n    long int readval = 0;\n\n    __asm__ __volatile__ (\"lock; cmpxchgl %2, %0\":\"+m\" (*p),\n        \"+a\" (readval):\"r\" (1):\"cc\");\n    return readval;\n}\n#endif\n\n#ifdef __x86_64__\nstatic inline int testandset (int *p)\n{\n    long int readval = 0;\n\n    __asm__ __volatile__ (\"lock; cmpxchgl %2, %0\":\"+m\" (*p),\n        \"+a\" (readval):\"r\" (1):\"cc\");\n    return readval;\n}\n#endif\n\n#ifdef __ia64\n#include <ia64intrin.h>\n\nstatic inline int testandset (int *p)\n{\n    return __sync_lock_test_and_set (p, 1);\n}\n#endif\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/vp_sdl.c",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *     \n  * This file is part of the virtualmips distribution. \n  * See LICENSE file for terms of the license. \n  *\n  */\n\n#ifdef SIM_LCD\n#include \"vp_sdl.h\"\n#include <signal.h>\n\nSDL_Surface *screen;\nSDL_Event ev;\n\nstatic void sdl_update (DisplayState * ds, int x, int y, int w, int h)\n{\n    SDL_UpdateRect (screen, x, y, w, h);\n}\n\nstatic void sdl_resize (DisplayState * ds, int w, int h)\n{\n    int flags;\n\n    // printf(\"resizing to %d %d\\n\", w, h);\n\n    flags = SDL_HWSURFACE | SDL_ASYNCBLIT | SDL_HWACCEL;\n  again:\n    screen = SDL_SetVideoMode (w, h, ds->depth, flags);\n    if (!screen) {\n        fprintf (stderr, \"Could not open SDL display\\n\");\n        exit (1);\n    }\n    if (!screen->pixels && (flags & SDL_HWSURFACE)\n        && (flags & SDL_FULLSCREEN)) {\n        flags &= ~SDL_HWSURFACE;\n        goto again;\n    }\n\n    if (!screen->pixels) {\n        fprintf (stderr, \"Could not open SDL display\\n\");\n        exit (1);\n    }\n    ds->data = screen->pixels;\n    ds->linesize = screen->pitch;\n    //ds->depth = screen->format->BitsPerPixel;\n    if (ds->depth == 32 && screen->format->Rshift == 0) {\n        ds->bgr = 1;\n    } else {\n        ds->bgr = 0;\n    }\n}\n\nSDL_Event *sdl_getmouse_down ()\n{\n    if (SDL_PollEvent (&ev)) {\n        if (ev.type == SDL_MOUSEBUTTONDOWN) {\n            return &ev;\n        }\n    }\n    return NULL;\n}\n\nSDL_Event *sdl_getmouse_up ()\n{\n    if (SDL_PollEvent (&ev)) {\n        if (ev.type == SDL_MOUSEBUTTONUP) {\n            return &ev;\n        }\n    }\n    return NULL;\n}\n\nstatic void sdl_refresh (DisplayState * ds)\n{\n\n}\n\nstatic void sdl_update_caption (void)\n{\n    char buf[1024];\n    strlcpy (buf, \"VirtualMIPS\", sizeof(buf));\n    SDL_WM_SetCaption (buf, \"\");\n}\n\n/*\nloading VirtualMIPS logo. \nA bit ugly logo.\nSorry CNN, I have not learned how to ps pictures. Please forgive me.\n*/\nstatic void sdl_display_logo (void)\n{\n    SDL_Surface *image;\n    SDL_Rect dest;\n    image = SDL_LoadBMP (\"logo.bmp\");\n    if (image == NULL) {\n        fprintf (stderr, \"can not load logo logo.bmp: %s\\n\", SDL_GetError ());\n        return;\n    }\n    dest.x = 0;\n    dest.y = 0;\n    dest.w = image->w;\n    dest.h = image->h;\n    SDL_BlitSurface (image, NULL, screen, &dest);\n\n    SDL_UpdateRects (screen, 1, &dest);\n\n}\n\nstatic void sdl_cleanup (void)\n{\n    printf (\"SDL Clean \\n\");\n    SDL_Quit ();\n}\n\nvoid sdl_display_init (DisplayState * ds, int full_screen)\n{\n    int flags;\n\n    flags = SDL_INIT_VIDEO | SDL_INIT_NOPARACHUTE;\n    if (SDL_Init (flags)) {\n        fprintf (stderr, \"Could not initialize SDL - exiting\\n\");\n        exit (1);\n    }\n#ifndef _WIN32\n    signal (SIGINT, SIG_DFL);\n    signal (SIGQUIT, SIG_DFL);\n#endif\n\n    ds->dpy_update = sdl_update;\n    ds->dpy_resize = sdl_resize;\n    ds->dpy_refresh = sdl_refresh;\n\n    sdl_resize (ds, ds->width, ds->height);\n    sdl_update_caption ();\n    sdl_display_logo ();\n    SDL_EnableUNICODE (1);\n\n    atexit (sdl_cleanup);\n}\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/vp_sdl.h",
    "content": " /*\n  * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n  *     \n  * This file is part of the virtualmips distribution. \n  * See LICENSE file for terms of the license. \n  *\n  */\n\n#ifndef __VSDL_H__\n#define __VSDL_H__\n\n#ifdef SIM_LCD                  /*defined in Makefile */\n\n#include \"utils.h\"\n#include \"SDL/SDL.h\"\n\nstruct DisplayState {\n    uint8_t *data;\n    int linesize;\n    int depth;\n    int bgr;                    /* BGR color order instead of RGB. Only valid for depth == 32 */\n    int width;\n    int height;\n    void *opaque;\n\n    void (*dpy_update) (struct DisplayState * s, int x, int y, int w, int h);\n    void (*dpy_resize) (struct DisplayState * s, int w, int h);\n    void (*dpy_refresh) (struct DisplayState * s);\n    void (*dpy_copy) (struct DisplayState * s, int src_x, int src_y,\n        int dst_x, int dst_y, int w, int h);\n};\n\ntypedef struct DisplayState DisplayState;\n\nstatic inline void dpy_update (DisplayState * s, int x, int y, int w, int h)\n{\n    s->dpy_update (s, x, y, w, h);\n}\n\nstatic inline void dpy_resize (DisplayState * s, int w, int h)\n{\n    s->dpy_resize (s, w, h);\n}\n\n/*\nstatic inline void draw_pixel(SDL_Surface *screen, Uint8 R, Uint8 G, Uint8 B,Uint32 x,Uint32 y)\n{\n\tUint32 color = SDL_MapRGB(screen->format, R, G, B);\n\n    switch (screen->format->BytesPerPixel) {\n        case 1: {\n            Uint8 *bufp;\n\n            bufp = (Uint8 *)screen->pixels + y*screen->pitch + x;\n            *bufp = color;\n        }\n        break;\n\n        case 2: {\n            Uint16 *bufp;\n\n            bufp = (Uint16 *)screen->pixels + y*screen->pitch/2 + x;\n            *bufp = color;\n        }\n        break;\n\n        case 3: {\n            Uint8 *bufp;\n\n            bufp = (Uint8 *)screen->pixels + y*screen->pitch + x;\n            *(bufp+screen->format->Rshift/8) = R;\n            *(bufp+screen->format->Gshift/8) = G;\n            *(bufp+screen->format->Bshift/8) = B;\n        }\n        break;\n\n        case 4: {\n            Uint32 *bufp;\n\n            bufp = (Uint32 *)screen->pixels + y*screen->pitch/4 + x;\n            *bufp = color;\n        }\n        break;\n    }\n\n}\n*/\nvoid sdl_display_init (DisplayState * ds, int full_screen);\nSDL_Event *sdl_getmouse_down ();\nSDL_Event *sdl_getmouse_up ();\n#endif\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/vp_timer.c",
    "content": " /*\n  * Copyright (C) yajin 2008<yajinzhou@gmail.com >\n  *     \n  * This file is part of the virtualmips distribution. \n  * See LICENSE file for terms of the license. \n  *\n  */\n\n/*\nTimer routine.\nEmulator has many timers. Every 1ms, emulator will check \nwhether there is timer request and pause the cpu when \nprocessing timer event. \nCodes are from qemu.\nyajin\n*/\n#include <stdlib.h>\n#include <string.h>\n#include \"vp_timer.h\"\n#include \"vp_clock.h\"\n\nvp_timer_t *active_timers[2];\n\nm_int64_t ticks_per_sec;\nvp_timer_t *vp_new_timer (vp_clock_t * clock, vp_timer_cb * cb, void *opaque)\n{\n    vp_timer_t *ts;\n\n    ts = malloc (sizeof (vp_timer_t));\n    memset (ts, 0x0, sizeof (*ts));\n    if (ts == NULL)\n        return NULL;\n    ts->clock = clock;\n    ts->cb = cb;\n    ts->opaque = opaque;\n    return ts;\n}\n\nvoid vp_free_timer (vp_timer_t * ts)\n{\n    ASSERT (ts != NULL, \"ts==NULL. NULL can not be freed\\n\");\n    free (ts);\n}\n\n/* stop a timer, but do not dealloc it */\nvoid vp_del_timer (vp_timer_t * ts)\n{\n    vp_timer_t **pt, *t;\n\n    /* NOTE: this code must be signal safe because\n     * qemu_timer_expired() can be called from a signal. */\n    pt = &active_timers[ts->clock->type];\n    for (;;) {\n        t = *pt;\n        if (!t)\n            break;\n        if (t == ts) {\n            *pt = t->next;\n            break;\n        }\n        pt = &t->next;\n    }\n}\n\n/* modify the current timer so that it will be fired when current_time\n   >= expire_time. The corresponding callback will be called. */\nvoid vp_mod_timer (vp_timer_t * ts, m_int64_t expire_time)\n{\n    vp_timer_t **pt, *t;\n\n    vp_del_timer (ts);\n\n    /* add the timer in the sorted list */\n    /* NOTE: this code must be signal safe because\n     * qemu_timer_expired() can be called from a signal. */\n    pt = &active_timers[ts->clock->type];\n    for (;;) {\n        t = *pt;\n        if (!t)\n            break;\n        if (t->expire_time > expire_time)\n            break;\n        pt = &t->next;\n    }\n    ts->expire_time = expire_time;\n    ts->next = *pt;\n    *pt = ts;\n}\n\nint vp_timer_pending (vp_timer_t * ts)\n{\n    vp_timer_t *t;\n    for (t = active_timers[ts->clock->type]; t != NULL; t = t->next) {\n        if (t == ts)\n            return 1;\n    }\n    return 0;\n}\n\ninline int vp_timer_expired (vp_timer_t * timer_head, m_int64_t current_time)\n{\n    if (!timer_head)\n        return 0;\n    return (timer_head->expire_time <= current_time);\n}\n\nvoid vp_run_timers (vp_timer_t ** ptimer_head, m_int64_t current_time)\n{\n    vp_timer_t *ts;\n\n    for (;;) {\n        ts = *ptimer_head;\n        if (!ts || ts->expire_time > current_time)\n            break;\n        /* remove timer from the list before calling the callback */\n        *ptimer_head = ts->next;\n        ts->next = NULL;\n        /* run the callback (the timer list can be modified) */\n        ts->cb (ts->opaque);\n    }\n}\n\nvoid init_timers (void)\n{\n    init_get_clock ();\n    ticks_per_sec = VP_TIMER_BASE;\n    rt_clock = vp_new_clock (VP_TIMER_REALTIME);\n    vm_clock = vp_new_clock (VP_TIMER_VIRTUAL);\n}\n"
  },
  {
    "path": "tools/virtualmips/vp_timer.h",
    "content": " /*\n  * Copyright (C) yajin 2008<yajinzhou@gmail.com >\n  *     \n  * This file is part of the virtualmips distribution. \n  * See LICENSE file for terms of the license. \n  *\n  */\n\n#ifndef __VP_TIMER_H__\n#define __VP_TIMER_H__\n\n#include \"vp_clock.h\"\n#include \"utils.h\"\n\n#define VP_TIMER_BASE 1000000000LL\n\ntypedef void vp_timer_cb (void *opaque);\n\nstruct vp_timer {\n    vp_clock_t *clock;\n    m_int64_t expire_time;\n    m_int64_t set_time;\n    vp_timer_cb *cb;\n    void *opaque;\n    struct vp_timer *next;\n};\ntypedef struct vp_timer vp_timer_t;\nextern vp_timer_t *active_timers[2];\n\nvp_timer_t *vp_new_timer (vp_clock_t * clock, vp_timer_cb * cb, void *opaque);\nvoid vp_free_timer (vp_timer_t * ts);\nvoid vp_mod_timer (vp_timer_t * ts, m_int64_t expire_time);\nvoid vp_del_timer (vp_timer_t * ts);\nint vp_timer_pending (vp_timer_t * ts);\nint vp_timer_expired (vp_timer_t * timer_head, m_int64_t current_time);\nvoid vp_run_timers (vp_timer_t ** ptimer_head, m_int64_t current_time);\nvoid init_timers (void);\n\n#endif\n"
  },
  {
    "path": "tools/virtualmips/x86-codegen.h",
    "content": "/*\n * x86-codegen.h: Macros for generating x86 code\n *\n * Authors:\n *   Paolo Molaro (lupus@ximian.com)\n *   Intel Corporation (ORP Project)\n *   Sergey Chaban (serge@wildwestsoftware.com)\n *   Dietmar Maurer (dietmar@ximian.com)\n *   Patrik Torstensson\n * \n * Copyright (C)  2000 Intel Corporation.  All rights reserved.\n * Copyright (C)  2001, 2002 Ximian, Inc.\n */\n\n#ifndef X86_H\n#define X86_H\n#include <assert.h>\n/*\n// x86 register numbers\n*/\ntypedef enum {\n    X86_EAX = 0,\n    X86_ECX = 1,\n    X86_EDX = 2,\n    X86_EBX = 3,\n    X86_ESP = 4,\n    X86_EBP = 5,\n    X86_ESI = 6,\n    X86_EDI = 7,\n    X86_NREG\n} X86_Reg_No;\n/*\n// opcodes for alu instructions\n*/\ntypedef enum {\n    X86_ADD = 0,\n    X86_OR = 1,\n    X86_ADC = 2,\n    X86_SBB = 3,\n    X86_AND = 4,\n    X86_SUB = 5,\n    X86_XOR = 6,\n    X86_CMP = 7,\n    X86_NALU\n} X86_ALU_Opcode;\n/*\n// opcodes for shift instructions\n*/\ntypedef enum {\n    X86_SHLD,\n    X86_SHLR,\n    X86_ROL = 0,\n    X86_ROR = 1,\n    X86_RCL = 2,\n    X86_RCR = 3,\n    X86_SHL = 4,\n    X86_SHR = 5,\n    X86_SAR = 7,\n    X86_NSHIFT = 8\n} X86_Shift_Opcode;\n/*\n// opcodes for floating-point instructions\n*/\ntypedef enum {\n    X86_FADD = 0,\n    X86_FMUL = 1,\n    X86_FCOM = 2,\n    X86_FCOMP = 3,\n    X86_FSUB = 4,\n    X86_FSUBR = 5,\n    X86_FDIV = 6,\n    X86_FDIVR = 7,\n    X86_NFP = 8\n} X86_FP_Opcode;\n/*\n// integer conditions codes\n*/\ntypedef enum {\n    X86_CC_EQ = 0, X86_CC_E = 0, X86_CC_Z = 0,\n    X86_CC_NE = 1, X86_CC_NZ = 1,\n    X86_CC_LT = 2, X86_CC_B = 2, X86_CC_C = 2, X86_CC_NAE = 2,\n    X86_CC_LE = 3, X86_CC_BE = 3, X86_CC_NA = 3,\n    X86_CC_GT = 4, X86_CC_A = 4, X86_CC_NBE = 4,\n    X86_CC_GE = 5, X86_CC_AE = 5, X86_CC_NB = 5, X86_CC_NC = 5,\n    X86_CC_LZ = 6, X86_CC_S = 6,\n    X86_CC_GEZ = 7, X86_CC_NS = 7,\n    X86_CC_P = 8, X86_CC_PE = 8,\n    X86_CC_NP = 9, X86_CC_PO = 9,\n    X86_CC_O = 10,\n    X86_CC_NO = 11,\n    X86_NCC\n} X86_CC;\n\n/* FP status */\nenum {\n    X86_FP_C0 = 0x100,\n    X86_FP_C1 = 0x200,\n    X86_FP_C2 = 0x400,\n    X86_FP_C3 = 0x4000,\n    X86_FP_CC_MASK = 0x4500\n};\n\n/* FP control word */\nenum {\n    X86_FPCW_INVOPEX_MASK = 0x1,\n    X86_FPCW_DENOPEX_MASK = 0x2,\n    X86_FPCW_ZERODIV_MASK = 0x4,\n    X86_FPCW_OVFEX_MASK = 0x8,\n    X86_FPCW_UNDFEX_MASK = 0x10,\n    X86_FPCW_PRECEX_MASK = 0x20,\n    X86_FPCW_PRECC_MASK = 0x300,\n    X86_FPCW_ROUNDC_MASK = 0xc00,\n\n    /* values for precision control */\n    X86_FPCW_PREC_SINGLE = 0,\n    X86_FPCW_PREC_DOUBLE = 0x200,\n    X86_FPCW_PREC_EXTENDED = 0x300,\n\n    /* values for rounding control */\n    X86_FPCW_ROUND_NEAREST = 0,\n    X86_FPCW_ROUND_DOWN = 0x400,\n    X86_FPCW_ROUND_UP = 0x800,\n    X86_FPCW_ROUND_TOZERO = 0xc00\n};\n\n/*\n// prefix code\n*/\ntypedef enum {\n    X86_LOCK_PREFIX = 0xF0,\n    X86_REPNZ_PREFIX = 0xF2,\n    X86_REPZ_PREFIX = 0xF3,\n    X86_REP_PREFIX = 0xF3,\n    X86_CS_PREFIX = 0x2E,\n    X86_SS_PREFIX = 0x36,\n    X86_DS_PREFIX = 0x3E,\n    X86_ES_PREFIX = 0x26,\n    X86_FS_PREFIX = 0x64,\n    X86_GS_PREFIX = 0x65,\n    X86_UNLIKELY_PREFIX = 0x2E,\n    X86_LIKELY_PREFIX = 0x3E,\n    X86_OPERAND_PREFIX = 0x66,\n    X86_ADDRESS_PREFIX = 0x67\n} X86_Prefix;\n\nstatic const unsigned char\n     x86_cc_unsigned_map[X86_NCC] = {\n    0x74,                       /* eq  */\n    0x75,                       /* ne  */\n    0x72,                       /* lt  */\n    0x76,                       /* le  */\n    0x77,                       /* gt  */\n    0x73,                       /* ge  */\n    0x78,                       /* lz  */\n    0x79,                       /* gez */\n    0x7a,                       /* p   */\n    0x7b,                       /* np  */\n    0x70,                       /* o  */\n    0x71,                       /* no  */\n};\n\nstatic const unsigned char\n     x86_cc_signed_map[X86_NCC] = {\n    0x74,                       /* eq  */\n    0x75,                       /* ne  */\n    0x7c,                       /* lt  */\n    0x7e,                       /* le  */\n    0x7f,                       /* gt  */\n    0x7d,                       /* ge  */\n    0x78,                       /* lz  */\n    0x79,                       /* gez */\n    0x7a,                       /* p   */\n    0x7b,                       /* np  */\n    0x70,                       /* o  */\n    0x71,                       /* no  */\n};\n\ntypedef union {\n    int val;\n    unsigned char b[4];\n} x86_imm_buf;\n\n#define X86_NOBASEREG (-1)\n\n/*\n// bitvector mask for callee-saved registers\n*/\n#define X86_ESI_MASK (1<<X86_ESI)\n#define X86_EDI_MASK (1<<X86_EDI)\n#define X86_EBX_MASK (1<<X86_EBX)\n#define X86_EBP_MASK (1<<X86_EBP)\n\n#define X86_CALLEE_REGS ((1<<X86_EAX) | (1<<X86_ECX) | (1<<X86_EDX))\n#define X86_CALLER_REGS ((1<<X86_EBX) | (1<<X86_EBP) | (1<<X86_ESI) | (1<<X86_EDI))\n#define X86_BYTE_REGS   ((1<<X86_EAX) | (1<<X86_ECX) | (1<<X86_EDX) | (1<<X86_EBX))\n\n#define X86_IS_SCRATCH(reg) (X86_CALLER_REGS & (1 << (reg)))    /* X86_EAX, X86_ECX, or X86_EDX */\n#define X86_IS_CALLEE(reg)  (X86_CALLEE_REGS & (1 << (reg)))    /* X86_ESI, X86_EDI, X86_EBX, or X86_EBP */\n\n#define X86_IS_BYTE_REG(reg) ((reg) < 4)\n\n/*\n// Frame structure:\n//\n//      +--------------------------------+\n//      | in_arg[0]       = var[0]\t     |\n//      | in_arg[1]\t      = var[1]\t     |\n//      |\t      . . .\t\t\t         |\n//      | in_arg[n_arg-1] = var[n_arg-1] |\n//      +--------------------------------+\n//      |       return IP                |\n//      +--------------------------------+\n//      |       saved EBP                | <-- frame pointer (EBP)\n//      +--------------------------------+\n//      |            ...                 |  n_extra\n//      +--------------------------------+\n//      |\t    var[n_arg]\t             |\n//      |\t    var[n_arg+1]             |  local variables area\n//      |          . . .                 |\n//      |\t    var[n_var-1]             | \n//      +--------------------------------+\n//      |\t\t\t                     |\n//      |\t\t\t                     |  \n//      |\t\tspill area               | area for spilling mimic stack\n//      |\t\t\t                     |\n//      +--------------------------------|\n//      |          ebx                   |\n//      |          ebp [ESP_Frame only]  |\n//      |\t       esi                   |  0..3 callee-saved regs\n//      |          edi                   | <-- stack pointer (ESP)\n//      +--------------------------------+\n//      |\tstk0\t                     |\n//      |\tstk1\t                     |  operand stack area/\n//      |\t. . .\t                     |  out args\n//      |\tstkn-1\t                     |\n//      +--------------------------------|\n//\n//\n*/\n\n/*\n * useful building blocks\n */\n#define x86_modrm_mod(modrm) ((modrm) >> 6)\n#define x86_modrm_reg(modrm) (((modrm) >> 3) & 0x7)\n#define x86_modrm_rm(modrm) ((modrm) & 0x7)\n\n#define x86_address_byte(inst,m,o,r) do { *(inst)++ = ((((m)&0x03)<<6)|(((o)&0x07)<<3)|(((r)&0x07))); } while (0)\n#define x86_imm_emit32(inst,imm)     \\\n\tdo {\t\\\n\t\t\tx86_imm_buf imb; imb.val = (int) (imm);\t\\\n\t\t\t*(inst)++ = imb.b [0];\t\\\n\t\t\t*(inst)++ = imb.b [1];\t\\\n\t\t\t*(inst)++ = imb.b [2];\t\\\n\t\t\t*(inst)++ = imb.b [3];\t\\\n\t} while (0)\n#define x86_imm_emit16(inst,imm)     do { *(short*)(inst) = (imm); (inst) += 2; } while (0)\n#define x86_imm_emit8(inst,imm)      do { *(inst) = (unsigned char)((imm) & 0xff); ++(inst); } while (0)\n#define x86_is_imm8(imm)             (((int)(imm) >= -128 && (int)(imm) <= 127))\n#define x86_is_imm16(imm)            (((int)(imm) >= -(1<<16) && (int)(imm) <= ((1<<16)-1)))\n\n#define x86_reg_emit(inst,r,regno)   do { x86_address_byte ((inst), 3, (r), (regno)); } while (0)\n#define x86_reg8_emit(inst,r,regno,is_rh,is_rnoh)   do {x86_address_byte ((inst), 3, (is_rh)?((r)|4):(r), (is_rnoh)?((regno)|4):(regno));} while (0)\n#define x86_regp_emit(inst,r,regno)  do { x86_address_byte ((inst), 0, (r), (regno)); } while (0)\n#define x86_mem_emit(inst,r,disp)    do { x86_address_byte ((inst), 0, (r), 5); x86_imm_emit32((inst), (disp)); } while (0)\n\n#define x86_membase_emit(inst,r,basereg,disp)\tdo {\\\n\tif ((basereg) == X86_ESP) {\t\\\n\t\tif ((disp) == 0) {\t\\\n\t\t\tx86_address_byte ((inst), 0, (r), X86_ESP);\t\\\n\t\t\tx86_address_byte ((inst), 0, X86_ESP, X86_ESP);\t\\\n\t\t} else if (x86_is_imm8((disp))) {\t\\\n\t\t\tx86_address_byte ((inst), 1, (r), X86_ESP);\t\\\n\t\t\tx86_address_byte ((inst), 0, X86_ESP, X86_ESP);\t\\\n\t\t\tx86_imm_emit8 ((inst), (disp));\t\\\n\t\t} else {\t\\\n\t\t\tx86_address_byte ((inst), 2, (r), X86_ESP);\t\\\n\t\t\tx86_address_byte ((inst), 0, X86_ESP, X86_ESP);\t\\\n\t\t\tx86_imm_emit32 ((inst), (disp));\t\\\n\t\t}\t\\\n\t\tbreak;\t\\\n\t}\t\\\n\tif ((disp) == 0 && (basereg) != X86_EBP) {\t\\\n\t\tx86_address_byte ((inst), 0, (r), (basereg));\t\\\n\t\tbreak;\t\\\n\t}\t\\\n\tif (x86_is_imm8((disp))) {\t\\\n\t\tx86_address_byte ((inst), 1, (r), (basereg));\t\\\n\t\tx86_imm_emit8 ((inst), (disp));\t\\\n\t} else {\t\\\n\t\tx86_address_byte ((inst), 2, (r), (basereg));\t\\\n\t\tx86_imm_emit32 ((inst), (disp));\t\\\n\t}\t\\\n\t} while (0)\n\n#define x86_memindex_emit(inst,r,basereg,disp,indexreg,shift)\t\\\n\tdo {\t\\\n\t\tif ((basereg) == X86_NOBASEREG) {\t\\\n\t\t\tx86_address_byte ((inst), 0, (r), 4);\t\\\n\t\t\tx86_address_byte ((inst), (shift), (indexreg), 5);\t\\\n\t\t\tx86_imm_emit32 ((inst), (disp));\t\\\n\t\t} else if ((disp) == 0 && (basereg) != X86_EBP) {\t\\\n\t\t\tx86_address_byte ((inst), 0, (r), 4);\t\\\n\t\t\tx86_address_byte ((inst), (shift), (indexreg), (basereg));\t\\\n\t\t} else if (x86_is_imm8((disp))) {\t\\\n\t\t\tx86_address_byte ((inst), 1, (r), 4);\t\\\n\t\t\tx86_address_byte ((inst), (shift), (indexreg), (basereg));\t\\\n\t\t\tx86_imm_emit8 ((inst), (disp));\t\\\n\t\t} else {\t\\\n\t\t\tx86_address_byte ((inst), 2, (r), 4);\t\\\n\t\t\tx86_address_byte ((inst), (shift), (indexreg), 5);\t\\\n\t\t\tx86_imm_emit32 ((inst), (disp));\t\\\n\t\t}\t\\\n\t} while (0)\n\n/*\n * target is the position in the code where to jump to:\n * target = code;\n * .. output loop code...\n * x86_mov_reg_imm (code, X86_EAX, 0);\n * loop = code;\n * x86_loop (code, -1);\n * ... finish method\n *\n * patch displacement\n * x86_patch (loop, target);\n *\n * ins should point at the start of the instruction that encodes a target.\n * the instruction is inspected for validity and the correct displacement\n * is inserted.\n */\n#define x86_patch(ins,target)\t\\\n\tdo {\t\\\n\t\tunsigned char* pos = (ins) + 1;\t\\\n\t\tint disp, size = 0;\t\\\n\t\tswitch (*(unsigned char*)(ins)) {\t\\\n\t\tcase 0xe8: case 0xe9: ++size; break; /* call, jump32 */\t\\\n\t\tcase 0x0f: if (!(*pos >= 0x70 && *pos <= 0x8f)) assert (0);\t\\\n\t\t   ++size; ++pos; break; /* prefix for 32-bit disp */\t\\\n\t\tcase 0xe0: case 0xe1: case 0xe2: /* loop */\t\\\n\t\tcase 0xeb: /* jump8 */\t\\\n\t\t/* conditional jump opcodes */\t\\\n\t\tcase 0x70: case 0x71: case 0x72: case 0x73:\t\\\n\t\tcase 0x74: case 0x75: case 0x76: case 0x77:\t\\\n\t\tcase 0x78: case 0x79: case 0x7a: case 0x7b:\t\\\n\t\tcase 0x7c: case 0x7d: case 0x7e: case 0x7f:\t\\\n\t\t\tbreak;\t\\\n\t\tdefault: assert (0);\t\\\n\t\t}\t\\\n\t\tdisp = (target) - pos;\t\\\n\t\tif (size) x86_imm_emit32 (pos, disp - 4);\t\\\n\t\telse if (x86_is_imm8 (disp - 1)) x86_imm_emit8 (pos, disp - 1);\t\\\n\t\telse assert (0);\t\\\n\t} while (0)\n\n#define x86_breakpoint(inst) \\\n\tdo {\t\\\n\t\t*(inst)++ = 0xcc;\t\\\n\t} while (0)\n\n#define x86_clc(inst) do { *(inst)++ =(unsigned char)0xf8; } while (0)\n#define x86_cld(inst) do { *(inst)++ =(unsigned char)0xfc; } while (0)\n#define x86_stosb(inst) do { *(inst)++ =(unsigned char)0xaa; } while (0)\n#define x86_stosl(inst) do { *(inst)++ =(unsigned char)0xab; } while (0)\n#define x86_stosd(inst) x86_stosl((inst))\n#define x86_movsb(inst) do { *(inst)++ =(unsigned char)0xa4; } while (0)\n#define x86_movsl(inst) do { *(inst)++ =(unsigned char)0xa5; } while (0)\n#define x86_movsd(inst) x86_movsl((inst))\n\n#define x86_prefix(inst,p) do { *(inst)++ =(unsigned char) (p); } while (0)\n\n#define x86_bswap(inst,reg) \\\n        do {    \\\n                *(inst)++ = 0x0f;\t\\\n                *(inst)++ = (unsigned char)0xc8 + (reg); \\\n        } while (0)\n\n#define x86_rdtsc(inst) \\\n\tdo {\t\\\n\t\t*(inst)++ = 0x0f;\t\\\n\t\t*(inst)++ = 0x31;\t\\\n\t} while (0)\n\n#define x86_cmpxchg_reg_reg(inst,dreg,reg)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x0f;\t\\\n\t\t*(inst)++ = (unsigned char)0xb1;\t\\\n\t\tx86_reg_emit ((inst), (reg), (dreg));\t\\\n\t} while (0)\n\n#define x86_cmpxchg_mem_reg(inst,mem,reg)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x0f;\t\\\n\t\t*(inst)++ = (unsigned char)0xb1;\t\\\n\t\tx86_mem_emit ((inst), (reg), (mem));\t\\\n\t} while (0)\n\n#define x86_cmpxchg_membase_reg(inst,basereg,disp,reg)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x0f;\t\\\n\t\t*(inst)++ = (unsigned char)0xb1;\t\\\n\t\tx86_membase_emit ((inst), (reg), (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_xchg_reg_reg(inst,dreg,reg,size)\t\\\n\tdo {\t\\\n\t\tif ((size) == 1)\t\\\n\t\t\t*(inst)++ = (unsigned char)0x86;\t\\\n\t\telse\t\\\n\t\t\t*(inst)++ = (unsigned char)0x87;\t\\\n\t\tx86_reg_emit ((inst), (reg), (dreg));\t\\\n\t} while (0)\n\n#define x86_xchg_mem_reg(inst,mem,reg,size)\t\\\n\tdo {\t\\\n\t\tif ((size) == 1)\t\\\n\t\t\t*(inst)++ = (unsigned char)0x86;\t\\\n\t\telse\t\\\n\t\t\t*(inst)++ = (unsigned char)0x87;\t\\\n\t\tx86_mem_emit ((inst), (reg), (mem));\t\\\n\t} while (0)\n\n#define x86_xchg_membase_reg(inst,basereg,disp,reg,size)\t\\\n\tdo {\t\\\n\t\tif ((size) == 1)\t\\\n\t\t\t*(inst)++ = (unsigned char)0x86;\t\\\n\t\telse\t\\\n\t\t\t*(inst)++ = (unsigned char)0x87;\t\\\n\t\tx86_membase_emit ((inst), (reg), (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_xadd_reg_reg(inst,dreg,reg,size)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x0F;     \\\n\t\tif ((size) == 1)\t\\\n\t\t\t*(inst)++ = (unsigned char)0xC0;\t\\\n\t\telse\t\\\n\t\t\t*(inst)++ = (unsigned char)0xC1;\t\\\n\t\tx86_reg_emit ((inst), (reg), (dreg));\t\\\n\t} while (0)\n\n#define x86_xadd_mem_reg(inst,mem,reg,size)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x0F;     \\\n\t\tif ((size) == 1)\t\\\n\t\t\t*(inst)++ = (unsigned char)0xC0;\t\\\n\t\telse\t\\\n\t\t\t*(inst)++ = (unsigned char)0xC1;\t\\\n\t\tx86_mem_emit ((inst), (reg), (mem));\t\\\n\t} while (0)\n\n#define x86_xadd_membase_reg(inst,basereg,disp,reg,size)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x0F;     \\\n\t\tif ((size) == 1)\t\\\n\t\t\t*(inst)++ = (unsigned char)0xC0;\t\\\n\t\telse\t\\\n\t\t\t*(inst)++ = (unsigned char)0xC1;\t\\\n\t\tx86_membase_emit ((inst), (reg), (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_inc_mem(inst,mem)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xff;\t\\\n\t\tx86_mem_emit ((inst), 0, (mem)); \t\\\n\t} while (0)\n\n#define x86_inc_membase(inst,basereg,disp)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xff;\t\\\n\t\tx86_membase_emit ((inst), 0, (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_inc_reg(inst,reg) do { *(inst)++ = (unsigned char)0x40 + (reg); } while (0)\n\n#define x86_dec_mem(inst,mem)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xff;\t\\\n\t\tx86_mem_emit ((inst), 1, (mem));\t\\\n\t} while (0)\n\n#define x86_dec_membase(inst,basereg,disp)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xff;\t\\\n\t\tx86_membase_emit ((inst), 1, (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_dec_reg(inst,reg) do { *(inst)++ = (unsigned char)0x48 + (reg); } while (0)\n\n#define x86_not_mem(inst,mem)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xf7;\t\\\n\t\tx86_mem_emit ((inst), 2, (mem));\t\\\n\t} while (0)\n\n#define x86_not_membase(inst,basereg,disp)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xf7;\t\\\n\t\tx86_membase_emit ((inst), 2, (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_not_reg(inst,reg)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xf7;\t\\\n\t\tx86_reg_emit ((inst), 2, (reg));\t\\\n\t} while (0)\n\n#define x86_neg_mem(inst,mem)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xf7;\t\\\n\t\tx86_mem_emit ((inst), 3, (mem));\t\\\n\t} while (0)\n\n#define x86_neg_membase(inst,basereg,disp)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xf7;\t\\\n\t\tx86_membase_emit ((inst), 3, (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_neg_reg(inst,reg)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xf7;\t\\\n\t\tx86_reg_emit ((inst), 3, (reg));\t\\\n\t} while (0)\n\n#define x86_nop(inst) do { *(inst)++ = (unsigned char)0x90; } while (0)\n\n#define x86_alu_reg_imm(inst,opc,reg,imm) \t\\\n\tdo {\t\\\n\t\tif ((reg) == X86_EAX) {\t\\\n\t\t\t*(inst)++ = (((unsigned char)(opc)) << 3) + 5;\t\\\n\t\t\tx86_imm_emit32 ((inst), (imm));\t\\\n\t\t\tbreak;\t\\\n\t\t}\t\\\n\t\tif (x86_is_imm8((imm))) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0x83;\t\\\n\t\t\tx86_reg_emit ((inst), (opc), (reg));\t\\\n\t\t\tx86_imm_emit8 ((inst), (imm));\t\\\n\t\t} else {\t\\\n\t\t\t*(inst)++ = (unsigned char)0x81;\t\\\n\t\t\tx86_reg_emit ((inst), (opc), (reg));\t\\\n\t\t\tx86_imm_emit32 ((inst), (imm));\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_alu_mem_imm(inst,opc,mem,imm) \t\\\n\tdo {\t\\\n\t\tif (x86_is_imm8((imm))) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0x83;\t\\\n\t\t\tx86_mem_emit ((inst), (opc), (mem));\t\\\n\t\t\tx86_imm_emit8 ((inst), (imm));\t\\\n\t\t} else {\t\\\n\t\t\t*(inst)++ = (unsigned char)0x81;\t\\\n\t\t\tx86_mem_emit ((inst), (opc), (mem));\t\\\n\t\t\tx86_imm_emit32 ((inst), (imm));\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_alu_membase_imm(inst,opc,basereg,disp,imm) \t\\\n\tdo {\t\\\n\t\tif (x86_is_imm8((imm))) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0x83;\t\\\n\t\t\tx86_membase_emit ((inst), (opc), (basereg), (disp));\t\\\n\t\t\tx86_imm_emit8 ((inst), (imm));\t\\\n\t\t} else {\t\\\n\t\t\t*(inst)++ = (unsigned char)0x81;\t\\\n\t\t\tx86_membase_emit ((inst), (opc), (basereg), (disp));\t\\\n\t\t\tx86_imm_emit32 ((inst), (imm));\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_alu_membase8_imm(inst,opc,basereg,disp,imm) \t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x80;\t\\\n\t\tx86_membase_emit ((inst), (opc), (basereg), (disp));\t\\\n\t\tx86_imm_emit8 ((inst), (imm)); \\\n\t} while (0)\n\n#define x86_alu_mem_reg(inst,opc,mem,reg)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (((unsigned char)(opc)) << 3) + 1;\t\\\n\t\tx86_mem_emit ((inst), (reg), (mem));\t\\\n\t} while (0)\n\n#define x86_alu_membase_reg(inst,opc,basereg,disp,reg)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (((unsigned char)(opc)) << 3) + 1;\t\\\n\t\tx86_membase_emit ((inst), (reg), (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_alu_reg_reg(inst,opc,dreg,reg)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (((unsigned char)(opc)) << 3) + 3;\t\\\n\t\tx86_reg_emit ((inst), (dreg), (reg));\t\\\n\t} while (0)\n\n/**\n * @x86_alu_reg8_reg8:\n * Supports ALU operations between two 8-bit registers.\n * dreg := dreg opc reg\n * X86_Reg_No enum is used to specify the registers.\n * Additionally is_*_h flags are used to specify what part\n * of a given 32-bit register is used - high (TRUE) or low (FALSE).\n * For example: dreg = X86_EAX, is_dreg_h = TRUE -> use AH\n */\n#define x86_alu_reg8_reg8(inst,opc,dreg,reg,is_dreg_h,is_reg_h)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (((unsigned char)(opc)) << 3) + 2;\t\\\n\t\tx86_reg8_emit ((inst), (dreg), (reg), (is_dreg_h), (is_reg_h));\t\\\n\t} while (0)\n\n#define x86_alu_reg_mem(inst,opc,reg,mem)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (((unsigned char)(opc)) << 3) + 3;\t\\\n\t\tx86_mem_emit ((inst), (reg), (mem));\t\\\n\t} while (0)\n\n#define x86_alu_reg_membase(inst,opc,reg,basereg,disp)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (((unsigned char)(opc)) << 3) + 3;\t\\\n\t\tx86_membase_emit ((inst), (reg), (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_test_reg_imm(inst,reg,imm)\t\\\n\tdo {\t\\\n\t\tif ((reg) == X86_EAX) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xa9;\t\\\n\t\t} else {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xf7;\t\\\n\t\t\tx86_reg_emit ((inst), 0, (reg));\t\\\n\t\t}\t\\\n\t\tx86_imm_emit32 ((inst), (imm));\t\\\n\t} while (0)\n\n#define x86_test_mem_imm(inst,mem,imm)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xf7;\t\\\n\t\tx86_mem_emit ((inst), 0, (mem));\t\\\n\t\tx86_imm_emit32 ((inst), (imm));\t\\\n\t} while (0)\n\n#define x86_test_membase_imm(inst,basereg,disp,imm)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xf7;\t\\\n\t\tx86_membase_emit ((inst), 0, (basereg), (disp));\t\\\n\t\tx86_imm_emit32 ((inst), (imm));\t\\\n\t} while (0)\n\n#define x86_test_reg_reg(inst,dreg,reg)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x85;\t\\\n\t\tx86_reg_emit ((inst), (reg), (dreg));\t\\\n\t} while (0)\n\n#define x86_test_mem_reg(inst,mem,reg)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x85;\t\\\n\t\tx86_mem_emit ((inst), (reg), (mem));\t\\\n\t} while (0)\n\n#define x86_test_membase_reg(inst,basereg,disp,reg)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x85;\t\\\n\t\tx86_membase_emit ((inst), (reg), (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_shift_reg_imm(inst,opc,reg,imm)\t\\\n\tdo {\t\\\n\t\tif ((imm) == 1) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xd1;\t\\\n\t\t\tx86_reg_emit ((inst), (opc), (reg));\t\\\n\t\t} else {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xc1;\t\\\n\t\t\tx86_reg_emit ((inst), (opc), (reg));\t\\\n\t\t\tx86_imm_emit8 ((inst), (imm));\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_shift_mem_imm(inst,opc,mem,imm)\t\\\n\tdo {\t\\\n\t\tif ((imm) == 1) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xd1;\t\\\n\t\t\tx86_mem_emit ((inst), (opc), (mem));\t\\\n\t\t} else {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xc1;\t\\\n\t\t\tx86_mem_emit ((inst), (opc), (mem));\t\\\n\t\t\tx86_imm_emit8 ((inst), (imm));\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_shift_membase_imm(inst,opc,basereg,disp,imm)\t\\\n\tdo {\t\\\n\t\tif ((imm) == 1) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xd1;\t\\\n\t\t\tx86_membase_emit ((inst), (opc), (basereg), (disp));\t\\\n\t\t} else {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xc1;\t\\\n\t\t\tx86_membase_emit ((inst), (opc), (basereg), (disp));\t\\\n\t\t\tx86_imm_emit8 ((inst), (imm));\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_shift_reg(inst,opc,reg)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xd3;\t\\\n\t\tx86_reg_emit ((inst), (opc), (reg));\t\\\n\t} while (0)\n\n#define x86_shift_mem(inst,opc,mem)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xd3;\t\\\n\t\tx86_mem_emit ((inst), (opc), (mem));\t\\\n\t} while (0)\n\n#define x86_shift_membase(inst,opc,basereg,disp)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xd3;\t\\\n\t\tx86_membase_emit ((inst), (opc), (basereg), (disp));\t\\\n\t} while (0)\n\n/*\n * Multi op shift missing.\n */\n\n#define x86_shrd_reg(inst,dreg,reg)                     \\\n        do {                                            \\\n\t\t*(inst)++ = (unsigned char)0x0f;\t\\\n\t\t*(inst)++ = (unsigned char)0xad;\t\\\n\t\tx86_reg_emit ((inst), (reg), (dreg));\t\\\n\t} while (0)\n\n#define x86_shrd_reg_imm(inst,dreg,reg,shamt)           \\\n        do {                                            \\\n\t\t*(inst)++ = (unsigned char)0x0f;\t\\\n\t\t*(inst)++ = (unsigned char)0xac;\t\\\n\t\tx86_reg_emit ((inst), (reg), (dreg));\t\\\n\t\tx86_imm_emit8 ((inst), (shamt));\t\\\n\t} while (0)\n\n#define x86_shld_reg(inst,dreg,reg)                     \\\n        do {                                            \\\n\t\t*(inst)++ = (unsigned char)0x0f;\t\\\n\t\t*(inst)++ = (unsigned char)0xa5;\t\\\n\t\tx86_reg_emit ((inst), (reg), (dreg));\t\\\n\t} while (0)\n\n#define x86_shld_reg_imm(inst,dreg,reg,shamt)           \\\n        do {                                            \\\n\t\t*(inst)++ = (unsigned char)0x0f;\t\\\n\t\t*(inst)++ = (unsigned char)0xa4;\t\\\n\t\tx86_reg_emit ((inst), (reg), (dreg));\t\\\n\t\tx86_imm_emit8 ((inst), (shamt));\t\\\n\t} while (0)\n\n/*\n * EDX:EAX = EAX * rm\n */\n#define x86_mul_reg(inst,reg,is_signed)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xf7;\t\\\n\t\tx86_reg_emit ((inst), 4 + ((is_signed) ? 1 : 0), (reg));\t\\\n\t} while (0)\n\n#define x86_mul_mem(inst,mem,is_signed)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xf7;\t\\\n\t\tx86_mem_emit ((inst), 4 + ((is_signed) ? 1 : 0), (mem));\t\\\n\t} while (0)\n\n#define x86_mul_membase(inst,basereg,disp,is_signed)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xf7;\t\\\n\t\tx86_membase_emit ((inst), 4 + ((is_signed) ? 1 : 0), (basereg), (disp));\t\\\n\t} while (0)\n\n/*\n * r *= rm\n */\n#define x86_imul_reg_reg(inst,dreg,reg)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x0f;\t\\\n\t\t*(inst)++ = (unsigned char)0xaf;\t\\\n\t\tx86_reg_emit ((inst), (dreg), (reg));\t\\\n\t} while (0)\n\n#define x86_imul_reg_mem(inst,reg,mem)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x0f;\t\\\n\t\t*(inst)++ = (unsigned char)0xaf;\t\\\n\t\tx86_mem_emit ((inst), (reg), (mem));\t\\\n\t} while (0)\n\n#define x86_imul_reg_membase(inst,reg,basereg,disp)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x0f;\t\\\n\t\t*(inst)++ = (unsigned char)0xaf;\t\\\n\t\tx86_membase_emit ((inst), (reg), (basereg), (disp));\t\\\n\t} while (0)\n\n/*\n * dreg = rm * imm\n */\n#define x86_imul_reg_reg_imm(inst,dreg,reg,imm)\t\\\n\tdo {\t\\\n\t\tif (x86_is_imm8 ((imm))) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0x6b;\t\\\n\t\t\tx86_reg_emit ((inst), (dreg), (reg));\t\\\n\t\t\tx86_imm_emit8 ((inst), (imm));\t\\\n\t\t} else {\t\\\n\t\t\t*(inst)++ = (unsigned char)0x69;\t\\\n\t\t\tx86_reg_emit ((inst), (dreg), (reg));\t\\\n\t\t\tx86_imm_emit32 ((inst), (imm));\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_imul_reg_mem_imm(inst,reg,mem,imm)\t\\\n\tdo {\t\\\n\t\tif (x86_is_imm8 ((imm))) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0x6b;\t\\\n\t\t\tx86_mem_emit ((inst), (reg), (mem));\t\\\n\t\t\tx86_imm_emit8 ((inst), (imm));\t\\\n\t\t} else {\t\\\n\t\t\t*(inst)++ = (unsigned char)0x69;\t\\\n\t\t\tx86_reg_emit ((inst), (reg), (mem));\t\\\n\t\t\tx86_imm_emit32 ((inst), (imm));\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_imul_reg_membase_imm(inst,reg,basereg,disp,imm)\t\\\n\tdo {\t\\\n\t\tif (x86_is_imm8 ((imm))) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0x6b;\t\\\n\t\t\tx86_membase_emit ((inst), (reg), (basereg), (disp));\t\\\n\t\t\tx86_imm_emit8 ((inst), (imm));\t\\\n\t\t} else {\t\\\n\t\t\t*(inst)++ = (unsigned char)0x69;\t\\\n\t\t\tx86_membase_emit ((inst), (reg), (basereg), (disp));\t\\\n\t\t\tx86_imm_emit32 ((inst), (imm));\t\\\n\t\t}\t\\\n\t} while (0)\n\n/*\n * divide EDX:EAX by rm;\n * eax = quotient, edx = remainder\n */\n\n#define x86_div_reg(inst,reg,is_signed)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xf7;\t\\\n\t\tx86_reg_emit ((inst), 6 + ((is_signed) ? 1 : 0), (reg));\t\\\n\t} while (0)\n\n#define x86_div_mem(inst,mem,is_signed)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xf7;\t\\\n\t\tx86_mem_emit ((inst), 6 + ((is_signed) ? 1 : 0), (mem));\t\\\n\t} while (0)\n\n#define x86_div_membase(inst,basereg,disp,is_signed)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xf7;\t\\\n\t\tx86_membase_emit ((inst), 6 + ((is_signed) ? 1 : 0), (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_mov_mem_reg(inst,mem,reg,size)\t\\\n\tdo {\t\\\n\t\tswitch ((size)) {\t\\\n\t\tcase 1: *(inst)++ = (unsigned char)0x88; break;\t\\\n\t\tcase 2: *(inst)++ = (unsigned char)0x66; /* fall through */\t\\\n\t\tcase 4: *(inst)++ = (unsigned char)0x89; break;\t\\\n\t\tdefault: assert (0);\t\\\n\t\t}\t\\\n\t\tx86_mem_emit ((inst), (reg), (mem));\t\\\n\t} while (0)\n\n#define x86_mov_regp_reg(inst,regp,reg,size)\t\\\n\tdo {\t\\\n\t\tswitch ((size)) {\t\\\n\t\tcase 1: *(inst)++ = (unsigned char)0x88; break;\t\\\n\t\tcase 2: *(inst)++ = (unsigned char)0x66; /* fall through */\t\\\n\t\tcase 4: *(inst)++ = (unsigned char)0x89; break;\t\\\n\t\tdefault: assert (0);\t\\\n\t\t}\t\\\n\t\tx86_regp_emit ((inst), (reg), (regp));\t\\\n\t} while (0)\n\n#define x86_mov_membase_reg(inst,basereg,disp,reg,size)\t\\\n\tdo {\t\\\n\t\tswitch ((size)) {\t\\\n\t\tcase 1: *(inst)++ = (unsigned char)0x88; break;\t\\\n\t\tcase 2: *(inst)++ = (unsigned char)0x66; /* fall through */\t\\\n\t\tcase 4: *(inst)++ = (unsigned char)0x89; break;\t\\\n\t\tdefault: assert (0);\t\\\n\t\t}\t\\\n\t\tx86_membase_emit ((inst), (reg), (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_mov_memindex_reg(inst,basereg,disp,indexreg,shift,reg,size)\t\\\n\tdo {\t\\\n\t\tswitch ((size)) {\t\\\n\t\tcase 1: *(inst)++ = (unsigned char)0x88; break;\t\\\n\t\tcase 2: *(inst)++ = (unsigned char)0x66; /* fall through */\t\\\n\t\tcase 4: *(inst)++ = (unsigned char)0x89; break;\t\\\n\t\tdefault: assert (0);\t\\\n\t\t}\t\\\n\t\tx86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift));\t\\\n\t} while (0)\n\n#define x86_mov_reg_reg(inst,dreg,reg,size)\t\\\n\tdo {\t\\\n\t\tswitch ((size)) {\t\\\n\t\tcase 1: *(inst)++ = (unsigned char)0x8a; break;\t\\\n\t\tcase 2: *(inst)++ = (unsigned char)0x66; /* fall through */\t\\\n\t\tcase 4: *(inst)++ = (unsigned char)0x8b; break;\t\\\n\t\tdefault: assert (0);\t\\\n\t\t}\t\\\n\t\tx86_reg_emit ((inst), (dreg), (reg));\t\\\n\t} while (0)\n\n#define x86_mov_reg_mem(inst,reg,mem,size)\t\\\n\tdo {\t\\\n\t\tswitch ((size)) {\t\\\n\t\tcase 1: *(inst)++ = (unsigned char)0x8a; break;\t\\\n\t\tcase 2: *(inst)++ = (unsigned char)0x66; /* fall through */\t\\\n\t\tcase 4: *(inst)++ = (unsigned char)0x8b; break;\t\\\n\t\tdefault: assert (0);\t\\\n\t\t}\t\\\n\t\tx86_mem_emit ((inst), (reg), (mem));\t\\\n\t} while (0)\n\n#define x86_mov_reg_membase(inst,reg,basereg,disp,size)\t\\\n\tdo {\t\\\n\t\tswitch ((size)) {\t\\\n\t\tcase 1: *(inst)++ = (unsigned char)0x8a; break;\t\\\n\t\tcase 2: *(inst)++ = (unsigned char)0x66; /* fall through */\t\\\n\t\tcase 4: *(inst)++ = (unsigned char)0x8b; break;\t\\\n\t\tdefault: assert (0);\t\\\n\t\t}\t\\\n\t\tx86_membase_emit ((inst), (reg), (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_mov_reg_memindex(inst,reg,basereg,disp,indexreg,shift,size)\t\\\n\tdo {\t\\\n\t\tswitch ((size)) {\t\\\n\t\tcase 1: *(inst)++ = (unsigned char)0x8a; break;\t\\\n\t\tcase 2: *(inst)++ = (unsigned char)0x66; /* fall through */\t\\\n\t\tcase 4: *(inst)++ = (unsigned char)0x8b; break;\t\\\n\t\tdefault: assert (0);\t\\\n\t\t}\t\\\n\t\tx86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift));\t\\\n\t} while (0)\n\n/*\n * Note: x86_clear_reg () chacnges the condition code!\n */\n#define x86_clear_reg(inst,reg) x86_alu_reg_reg((inst), X86_XOR, (reg), (reg))\n\n#define x86_mov_reg_imm(inst,reg,imm)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xb8 + (reg);\t\\\n\t\tx86_imm_emit32 ((inst), (imm));\t\\\n\t} while (0)\n\n#define x86_mov_mem_imm(inst,mem,imm,size)\t\\\n\tdo {\t\\\n\t\tif ((size) == 1) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xc6;\t\\\n\t\t\tx86_mem_emit ((inst), 0, (mem));\t\\\n\t\t\tx86_imm_emit8 ((inst), (imm));\t\\\n\t\t} else if ((size) == 2) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0x66;\t\\\n\t\t\t*(inst)++ = (unsigned char)0xc7;\t\\\n\t\t\tx86_mem_emit ((inst), 0, (mem));\t\\\n\t\t\tx86_imm_emit16 ((inst), (imm));\t\\\n\t\t} else {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xc7;\t\\\n\t\t\tx86_mem_emit ((inst), 0, (mem));\t\\\n\t\t\tx86_imm_emit32 ((inst), (imm));\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_mov_membase_imm(inst,basereg,disp,imm,size)\t\\\n\tdo {\t\\\n\t\tif ((size) == 1) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xc6;\t\\\n\t\t\tx86_membase_emit ((inst), 0, (basereg), (disp));\t\\\n\t\t\tx86_imm_emit8 ((inst), (imm));\t\\\n\t\t} else if ((size) == 2) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0x66;\t\\\n\t\t\t*(inst)++ = (unsigned char)0xc7;\t\\\n\t\t\tx86_membase_emit ((inst), 0, (basereg), (disp));\t\\\n\t\t\tx86_imm_emit16 ((inst), (imm));\t\\\n\t\t} else {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xc7;\t\\\n\t\t\tx86_membase_emit ((inst), 0, (basereg), (disp));\t\\\n\t\t\tx86_imm_emit32 ((inst), (imm));\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_mov_memindex_imm(inst,basereg,disp,indexreg,shift,imm,size)\t\\\n\tdo {\t\\\n\t\tif ((size) == 1) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xc6;\t\\\n\t\t\tx86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift));\t\\\n\t\t\tx86_imm_emit8 ((inst), (imm));\t\\\n\t\t} else if ((size) == 2) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0x66;\t\\\n\t\t\t*(inst)++ = (unsigned char)0xc7;\t\\\n\t\t\tx86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift));\t\\\n\t\t\tx86_imm_emit16 ((inst), (imm));\t\\\n\t\t} else {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xc7;\t\\\n\t\t\tx86_memindex_emit ((inst), 0, (basereg), (disp), (indexreg), (shift));\t\\\n\t\t\tx86_imm_emit32 ((inst), (imm));\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_lea_mem(inst,reg,mem)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x8d;\t\\\n\t\tx86_mem_emit ((inst), (reg), (mem));\t\\\n\t} while (0)\n\n#define x86_lea_membase(inst,reg,basereg,disp)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x8d;\t\\\n\t\tx86_membase_emit ((inst), (reg), (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_lea_memindex(inst,reg,basereg,disp,indexreg,shift)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x8d;\t\\\n\t\tx86_memindex_emit ((inst), (reg), (basereg), (disp), (indexreg), (shift));\t\\\n\t} while (0)\n\n#define x86_widen_reg(inst,dreg,reg,is_signed,is_half)\t\\\n\tdo {\t\\\n\t\tunsigned char op = 0xb6;\t\\\n                assert (is_half ||  X86_IS_BYTE_REG (reg)); \\\n\t\t*(inst)++ = (unsigned char)0x0f;\t\\\n\t\tif ((is_signed)) op += 0x08;\t\\\n\t\tif ((is_half)) op += 0x01;\t\\\n\t\t*(inst)++ = op;\t\\\n\t\tx86_reg_emit ((inst), (dreg), (reg));\t\\\n\t} while (0)\n\n#define x86_widen_mem(inst,dreg,mem,is_signed,is_half)\t\\\n\tdo {\t\\\n\t\tunsigned char op = 0xb6;\t\\\n\t\t*(inst)++ = (unsigned char)0x0f;\t\\\n\t\tif ((is_signed)) op += 0x08;\t\\\n\t\tif ((is_half)) op += 0x01;\t\\\n\t\t*(inst)++ = op;\t\\\n\t\tx86_mem_emit ((inst), (dreg), (mem));\t\\\n\t} while (0)\n\n#define x86_widen_membase(inst,dreg,basereg,disp,is_signed,is_half)\t\\\n\tdo {\t\\\n\t\tunsigned char op = 0xb6;\t\\\n\t\t*(inst)++ = (unsigned char)0x0f;\t\\\n\t\tif ((is_signed)) op += 0x08;\t\\\n\t\tif ((is_half)) op += 0x01;\t\\\n\t\t*(inst)++ = op;\t\\\n\t\tx86_membase_emit ((inst), (dreg), (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_widen_memindex(inst,dreg,basereg,disp,indexreg,shift,is_signed,is_half)\t\\\n\tdo {\t\\\n\t\tunsigned char op = 0xb6;\t\\\n\t\t*(inst)++ = (unsigned char)0x0f;\t\\\n\t\tif ((is_signed)) op += 0x08;\t\\\n\t\tif ((is_half)) op += 0x01;\t\\\n\t\t*(inst)++ = op;\t\\\n\t\tx86_memindex_emit ((inst), (dreg), (basereg), (disp), (indexreg), (shift));\t\\\n\t} while (0)\n\n#define x86_lahf(inst)  do { *(inst)++ = (unsigned char)0x9f; } while (0)\n#define x86_sahf(inst)  do { *(inst)++ = (unsigned char)0x9e; } while (0)\n#define x86_xchg_ah_al(inst) \\\n       do { \\\n                *(inst)++ = (unsigned char)0x86; \\\n                *(inst)++ = (unsigned char)0xe0; \\\n       } while (0)\n\n#define x86_cdq(inst)  do { *(inst)++ = (unsigned char)0x99; } while (0)\n#define x86_wait(inst) do { *(inst)++ = (unsigned char)0x9b; } while (0)\n\n#define x86_fp_op_mem(inst,opc,mem,is_double)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (is_double) ? (unsigned char)0xdc : (unsigned char)0xd8;\t\\\n\t\tx86_mem_emit ((inst), (opc), (mem));\t\\\n\t} while (0)\n\n#define x86_fp_op_membase(inst,opc,basereg,disp,is_double)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (is_double) ? (unsigned char)0xdc : (unsigned char)0xd8;\t\\\n\t\tx86_membase_emit ((inst), (opc), (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_fp_op(inst,opc,index)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xd8;\t\\\n\t\t*(inst)++ = (unsigned char)0xc0+((opc)<<3)+((index)&0x07);\t\\\n\t} while (0)\n\n#define x86_fp_op_reg(inst,opc,index,pop_stack)\t\\\n\tdo {\t\\\n\t\tstatic const unsigned char map[] = { 0, 1, 2, 3, 5, 4, 7, 6, 8};\t\\\n\t\t*(inst)++ = (pop_stack) ? (unsigned char)0xde : (unsigned char)0xdc;\t\\\n\t\t*(inst)++ = (unsigned char)0xc0+(map[(opc)]<<3)+((index)&0x07);\t\\\n\t} while (0)\n\n/**\n * @x86_fp_int_op_membase\n * Supports FPU operations between ST(0) and integer operand in memory.\n * Operation encoded using X86_FP_Opcode enum.\n * Operand is addressed by [basereg + disp].\n * is_int specifies whether operand is int32 (TRUE) or int16 (FALSE).\n */\n#define x86_fp_int_op_membase(inst,opc,basereg,disp,is_int)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (is_int) ? (unsigned char)0xda : (unsigned char)0xde;\t\\\n\t\tx86_membase_emit ((inst), opc, (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_fstp(inst,index)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xdd;\t\\\n\t\t*(inst)++ = (unsigned char)0xd8+(index);\t\\\n\t} while (0)\n\n#define x86_fcompp(inst)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xde;\t\\\n\t\t*(inst)++ = (unsigned char)0xd9;\t\\\n\t} while (0)\n\n#define x86_fucompp(inst)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xda;\t\\\n\t\t*(inst)++ = (unsigned char)0xe9;\t\\\n\t} while (0)\n\n#define x86_fnstsw(inst)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xdf;\t\\\n\t\t*(inst)++ = (unsigned char)0xe0;\t\\\n\t} while (0)\n\n#define x86_fnstcw(inst,mem)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xd9;\t\\\n\t\tx86_mem_emit ((inst), 7, (mem));\t\\\n\t} while (0)\n\n#define x86_fnstcw_membase(inst,basereg,disp)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xd9;\t\\\n\t\tx86_membase_emit ((inst), 7, (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_fldcw(inst,mem)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xd9;\t\\\n\t\tx86_mem_emit ((inst), 5, (mem));\t\\\n\t} while (0)\n\n#define x86_fldcw_membase(inst,basereg,disp)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xd9;\t\\\n\t\tx86_membase_emit ((inst), 5, (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_fchs(inst)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xd9;\t\\\n\t\t*(inst)++ = (unsigned char)0xe0;\t\\\n\t} while (0)\n\n#define x86_frem(inst)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xd9;\t\\\n\t\t*(inst)++ = (unsigned char)0xf8;\t\\\n\t} while (0)\n\n#define x86_fxch(inst,index)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xd9;\t\\\n\t\t*(inst)++ = (unsigned char)0xc8 + ((index) & 0x07);\t\\\n\t} while (0)\n\n#define x86_fcomi(inst,index)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xdb;\t\\\n\t\t*(inst)++ = (unsigned char)0xf0 + ((index) & 0x07);\t\\\n\t} while (0)\n\n#define x86_fcomip(inst,index)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xdf;\t\\\n\t\t*(inst)++ = (unsigned char)0xf0 + ((index) & 0x07);\t\\\n\t} while (0)\n\n#define x86_fucomi(inst,index)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xdb;\t\\\n\t\t*(inst)++ = (unsigned char)0xe8 + ((index) & 0x07);\t\\\n\t} while (0)\n\n#define x86_fucomip(inst,index)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xdf;\t\\\n\t\t*(inst)++ = (unsigned char)0xe8 + ((index) & 0x07);\t\\\n\t} while (0)\n\n#define x86_fld(inst,mem,is_double)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned char)0xd9;\t\\\n\t\tx86_mem_emit ((inst), 0, (mem));\t\\\n\t} while (0)\n\n#define x86_fld_membase(inst,basereg,disp,is_double)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (is_double) ? (unsigned char)0xdd : (unsigned char)0xd9;\t\\\n\t\tx86_membase_emit ((inst), 0, (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_fld80_mem(inst,mem)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xdb;\t\\\n\t\tx86_mem_emit ((inst), 5, (mem));\t\\\n\t} while (0)\n\n#define x86_fld80_membase(inst,basereg,disp)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xdb;\t\\\n\t\tx86_membase_emit ((inst), 5, (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_fild(inst,mem,is_long)\t\\\n\tdo {\t\\\n\t\tif ((is_long)) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xdf;\t\\\n\t\t\tx86_mem_emit ((inst), 5, (mem));\t\\\n\t\t} else {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xdb;\t\\\n\t\t\tx86_mem_emit ((inst), 0, (mem));\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_fild_membase(inst,basereg,disp,is_long)\t\\\n\tdo {\t\\\n\t\tif ((is_long)) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xdf;\t\\\n\t\t\tx86_membase_emit ((inst), 5, (basereg), (disp));\t\\\n\t\t} else {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xdb;\t\\\n\t\t\tx86_membase_emit ((inst), 0, (basereg), (disp));\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_fld_reg(inst,index)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xd9;\t\\\n\t\t*(inst)++ = (unsigned char)0xc0 + ((index) & 0x07);\t\\\n\t} while (0)\n\n#define x86_fldz(inst)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xd9;\t\\\n\t\t*(inst)++ = (unsigned char)0xee;\t\\\n\t} while (0)\n\n#define x86_fld1(inst)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xd9;\t\\\n\t\t*(inst)++ = (unsigned char)0xe8;\t\\\n\t} while (0)\n\n#define x86_fldpi(inst)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xd9;\t\\\n\t\t*(inst)++ = (unsigned char)0xeb;\t\\\n\t} while (0)\n\n#define x86_fst(inst,mem,is_double,pop_stack)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9;\t\\\n\t\tx86_mem_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (mem));\t\\\n\t} while (0)\n\n#define x86_fst_membase(inst,basereg,disp,is_double,pop_stack)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (is_double) ? (unsigned char)0xdd: (unsigned char)0xd9;\t\\\n\t\tx86_membase_emit ((inst), 2 + ((pop_stack) ? 1 : 0), (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_fst80_mem(inst,mem)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xdb;\t\\\n\t\tx86_mem_emit ((inst), 7, (mem));\t\\\n\t} while (0)\n\n#define x86_fst80_membase(inst,basereg,disp)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xdb;\t\\\n\t\tx86_membase_emit ((inst), 7, (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_fist_pop(inst,mem,is_long)\t\\\n\tdo {\t\\\n\t\tif ((is_long)) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xdf;\t\\\n\t\t\tx86_mem_emit ((inst), 7, (mem));\t\\\n\t\t} else {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xdb;\t\\\n\t\t\tx86_mem_emit ((inst), 3, (mem));\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_fist_pop_membase(inst,basereg,disp,is_long)\t\\\n\tdo {\t\\\n\t\tif ((is_long)) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xdf;\t\\\n\t\t\tx86_membase_emit ((inst), 7, (basereg), (disp));\t\\\n\t\t} else {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xdb;\t\\\n\t\t\tx86_membase_emit ((inst), 3, (basereg), (disp));\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_fstsw(inst)\t\\\n\tdo {\t\\\n\t\t\t*(inst)++ = (unsigned char)0x9b;\t\\\n\t\t\t*(inst)++ = (unsigned char)0xdf;\t\\\n\t\t\t*(inst)++ = (unsigned char)0xe0;\t\\\n\t} while (0)\n\n/**\n * @x86_fist_membase\n * Converts content of ST(0) to integer and stores it at memory location\n * addressed by [basereg + disp].\n * is_int specifies whether destination is int32 (TRUE) or int16 (FALSE).\n */\n#define x86_fist_membase(inst,basereg,disp,is_int)\t\\\n\tdo {\t\\\n\t\tif ((is_int)) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xdb;\t\\\n\t\t\tx86_membase_emit ((inst), 2, (basereg), (disp));\t\\\n\t\t} else {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xdf;\t\\\n\t\t\tx86_membase_emit ((inst), 2, (basereg), (disp));\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_push_reg(inst,reg)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x50 + (reg);\t\\\n\t} while (0)\n\n#define x86_push_regp(inst,reg)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xff;\t\\\n\t\tx86_regp_emit ((inst), 6, (reg));\t\\\n\t} while (0)\n\n#define x86_push_mem(inst,mem)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xff;\t\\\n\t\tx86_mem_emit ((inst), 6, (mem));\t\\\n\t} while (0)\n\n#define x86_push_membase(inst,basereg,disp)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xff;\t\\\n\t\tx86_membase_emit ((inst), 6, (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_push_memindex(inst,basereg,disp,indexreg,shift)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xff;\t\\\n\t\tx86_memindex_emit ((inst), 6, (basereg), (disp), (indexreg), (shift));\t\\\n\t} while (0)\n\n#define x86_push_imm_template(inst) x86_push_imm (inst, 0xf0f0f0f0)\n\n#define x86_push_imm(inst,imm)\t\\\n\tdo {\t\\\n\t\tint _imm = (int) (imm);\t\\\n\t\tif (x86_is_imm8 (_imm)) {\t\\\n\t\t\t*(inst)++ = (unsigned char)0x6A;\t\\\n\t\t\tx86_imm_emit8 ((inst), (_imm));\t\\\n\t\t} else {\t\\\n\t\t\t*(inst)++ = (unsigned char)0x68;\t\\\n\t\t\tx86_imm_emit32 ((inst), (_imm));\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_pop_reg(inst,reg)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x58 + (reg);\t\\\n\t} while (0)\n\n#define x86_pop_mem(inst,mem)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x87;\t\\\n\t\tx86_mem_emit ((inst), 0, (mem));\t\\\n\t} while (0)\n\n#define x86_pop_membase(inst,basereg,disp)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x87;\t\\\n\t\tx86_membase_emit ((inst), 0, (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_pushad(inst) do { *(inst)++ = (unsigned char)0x60; } while (0)\n#define x86_pushfd(inst) do { *(inst)++ = (unsigned char)0x9c; } while (0)\n#define x86_popad(inst)  do { *(inst)++ = (unsigned char)0x61; } while (0)\n#define x86_popfd(inst)  do { *(inst)++ = (unsigned char)0x9d; } while (0)\n\n#define x86_loop(inst,imm)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xe2;\t\\\n\t\tx86_imm_emit8 ((inst), (imm));\t\\\n\t} while (0)\n\n#define x86_loope(inst,imm)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xe1;\t\\\n\t\tx86_imm_emit8 ((inst), (imm));\t\\\n\t} while (0)\n\n#define x86_loopne(inst,imm)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xe0;\t\\\n\t\tx86_imm_emit8 ((inst), (imm));\t\\\n\t} while (0)\n\n#define x86_jump32(inst,imm)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xe9;\t\\\n\t\tx86_imm_emit32 ((inst), (imm));\t\\\n\t} while (0)\n\n#define x86_jump8(inst,imm)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xeb;\t\\\n\t\tx86_imm_emit8 ((inst), (imm));\t\\\n\t} while (0)\n\n#define x86_jump_reg(inst,reg)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xff;\t\\\n\t\tx86_reg_emit ((inst), 4, (reg));\t\\\n\t} while (0)\n\n#define x86_jump_mem(inst,mem)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xff;\t\\\n\t\tx86_mem_emit ((inst), 4, (mem));\t\\\n\t} while (0)\n\n#define x86_jump_membase(inst,basereg,disp)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xff;\t\\\n\t\tx86_membase_emit ((inst), 4, (basereg), (disp));\t\\\n\t} while (0)\n\n/*\n * target is a pointer in our buffer.\n */\n#define x86_jump_code(inst,target)\t\\\n\tdo {\t\\\n\t\tint t = (unsigned char*)(target) - (inst) - 2;\t\\\n\t\tif (x86_is_imm8(t)) {\t\\\n\t\t\tx86_jump8 ((inst), t);\t\\\n\t\t} else {\t\\\n\t\t\tt -= 3;\t\\\n\t\t\tx86_jump32 ((inst), t);\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_jump_disp(inst,disp)\t\\\n\tdo {\t\\\n\t\tint t = (disp) - 2;\t\\\n\t\tif (x86_is_imm8(t)) {\t\\\n\t\t\tx86_jump8 ((inst), t);\t\\\n\t\t} else {\t\\\n\t\t\tt -= 3;\t\\\n\t\t\tx86_jump32 ((inst), t);\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_branch8(inst,cond,imm,is_signed)\t\\\n\tdo {\t\\\n\t\tif ((is_signed))\t\\\n\t\t\t*(inst)++ = x86_cc_signed_map [(cond)];\t\\\n\t\telse\t\\\n\t\t\t*(inst)++ = x86_cc_unsigned_map [(cond)];\t\\\n\t\tx86_imm_emit8 ((inst), (imm));\t\\\n\t} while (0)\n\n#define x86_branch32(inst,cond,imm,is_signed)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x0f;\t\\\n\t\tif ((is_signed))\t\\\n\t\t\t*(inst)++ = x86_cc_signed_map [(cond)] + 0x10;\t\\\n\t\telse\t\\\n\t\t\t*(inst)++ = x86_cc_unsigned_map [(cond)] + 0x10;\t\\\n\t\tx86_imm_emit32 ((inst), (imm));\t\\\n\t} while (0)\n\n#define x86_branch(inst,cond,target,is_signed)\t\\\n\tdo {\t\\\n\t\tint offset = (target) - (inst) - 2;\t\\\n\t\tif (x86_is_imm8 ((offset)))\t\\\n\t\t\tx86_branch8 ((inst), (cond), offset, (is_signed));\t\\\n\t\telse {\t\\\n\t\t\toffset -= 4;\t\\\n\t\t\tx86_branch32 ((inst), (cond), offset, (is_signed));\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_branch_disp(inst,cond,disp,is_signed)\t\\\n\tdo {\t\\\n\t\tint offset = (disp) - 2;\t\\\n\t\tif (x86_is_imm8 ((offset)))\t\\\n\t\t\tx86_branch8 ((inst), (cond), offset, (is_signed));\t\\\n\t\telse {\t\\\n\t\t\toffset -= 4;\t\\\n\t\t\tx86_branch32 ((inst), (cond), offset, (is_signed));\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_set_reg(inst,cond,reg,is_signed)\t\\\n\tdo {\t\\\n                assert (X86_IS_BYTE_REG (reg)); \\\n\t\t*(inst)++ = (unsigned char)0x0f;\t\\\n\t\tif ((is_signed))\t\\\n\t\t\t*(inst)++ = x86_cc_signed_map [(cond)] + 0x20;\t\\\n\t\telse\t\\\n\t\t\t*(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20;\t\\\n\t\tx86_reg_emit ((inst), 0, (reg));\t\\\n\t} while (0)\n\n#define x86_set_mem(inst,cond,mem,is_signed)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x0f;\t\\\n\t\tif ((is_signed))\t\\\n\t\t\t*(inst)++ = x86_cc_signed_map [(cond)] + 0x20;\t\\\n\t\telse\t\\\n\t\t\t*(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20;\t\\\n\t\tx86_mem_emit ((inst), 0, (mem));\t\\\n\t} while (0)\n\n#define x86_set_membase(inst,cond,basereg,disp,is_signed)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0x0f;\t\\\n\t\tif ((is_signed))\t\\\n\t\t\t*(inst)++ = x86_cc_signed_map [(cond)] + 0x20;\t\\\n\t\telse\t\\\n\t\t\t*(inst)++ = x86_cc_unsigned_map [(cond)] + 0x20;\t\\\n\t\tx86_membase_emit ((inst), 0, (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_call_imm(inst,disp)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xe8;\t\\\n\t\tx86_imm_emit32 ((inst), (int)(disp));\t\\\n\t} while (0)\n\n#define x86_call_reg(inst,reg)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xff;\t\\\n\t\tx86_reg_emit ((inst), 2, (reg));\t\\\n\t} while (0)\n\n#define x86_call_mem(inst,mem)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xff;\t\\\n\t\tx86_mem_emit ((inst), 2, (mem));\t\\\n\t} while (0)\n\n#define x86_call_membase(inst,basereg,disp)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xff;\t\\\n\t\tx86_membase_emit ((inst), 2, (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_call_code(inst,target)\t\\\n\tdo {\t\\\n\t\tint _x86_offset = (unsigned char*)(target) - (inst);\t\\\n\t\t_x86_offset -= 5;\t\\\n\t\tx86_call_imm ((inst), _x86_offset);\t\\\n\t} while (0)\n\n#define x86_ret(inst) do { *(inst)++ = (unsigned char)0xc3; } while (0)\n\n#define x86_ret_imm(inst,imm)\t\\\n\tdo {\t\\\n\t\tif ((imm) == 0) {\t\\\n\t\t\tx86_ret ((inst));\t\\\n\t\t} else {\t\\\n\t\t\t*(inst)++ = (unsigned char)0xc2;\t\\\n\t\t\tx86_imm_emit16 ((inst), (imm));\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_cmov_reg(inst,cond,is_signed,dreg,reg)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char) 0x0f;\t\\\n\t\tif ((is_signed))\t\\\n\t\t\t*(inst)++ = x86_cc_signed_map [(cond)] - 0x30;\t\\\n\t\telse\t\\\n\t\t\t*(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30;\t\\\n\t\tx86_reg_emit ((inst), (dreg), (reg));\t\\\n\t} while (0)\n\n#define x86_cmov_mem(inst,cond,is_signed,reg,mem)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char) 0x0f;\t\\\n\t\tif ((is_signed))\t\\\n\t\t\t*(inst)++ = x86_cc_signed_map [(cond)] - 0x30;\t\\\n\t\telse\t\\\n\t\t\t*(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30;\t\\\n\t\tx86_mem_emit ((inst), (reg), (mem));\t\\\n\t} while (0)\n\n#define x86_cmov_membase(inst,cond,is_signed,reg,basereg,disp)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char) 0x0f;\t\\\n\t\tif ((is_signed))\t\\\n\t\t\t*(inst)++ = x86_cc_signed_map [(cond)] - 0x30;\t\\\n\t\telse\t\\\n\t\t\t*(inst)++ = x86_cc_unsigned_map [(cond)] - 0x30;\t\\\n\t\tx86_membase_emit ((inst), (reg), (basereg), (disp));\t\\\n\t} while (0)\n\n#define x86_enter(inst,framesize)\t\\\n\tdo {\t\\\n\t\t*(inst)++ = (unsigned char)0xc8;\t\\\n\t\tx86_imm_emit16 ((inst), (framesize));\t\\\n\t\t*(inst)++ = 0;\t\\\n\t} while (0)\n\n#define x86_leave(inst) do { *(inst)++ = (unsigned char)0xc9; } while (0)\n#define x86_sahf(inst)  do { *(inst)++ = (unsigned char)0x9e; } while (0)\n\n#define x86_fsin(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfe; } while (0)\n#define x86_fcos(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xff; } while (0)\n#define x86_fabs(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe1; } while (0)\n#define x86_ftst(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe4; } while (0)\n#define x86_fxam(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xe5; } while (0)\n#define x86_fpatan(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf3; } while (0)\n#define x86_fprem(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf8; } while (0)\n#define x86_fprem1(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf5; } while (0)\n#define x86_frndint(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfc; } while (0)\n#define x86_fsqrt(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xfa; } while (0)\n#define x86_fptan(inst) do { *(inst)++ = (unsigned char)0xd9; *(inst)++ = (unsigned char)0xf2; } while (0)\n\n#define x86_padding(inst,size)\t\\\n\tdo {\t\\\n\t\tswitch ((size)) {\t\\\n\t\tcase 1: x86_nop ((inst)); break;\t\\\n\t\tcase 2: *(inst)++ = 0x8b;\t\\\n\t\t\t*(inst)++ = 0xc0; break;\t\\\n\t\tcase 3: *(inst)++ = 0x8d; *(inst)++ = 0x6d;\t\\\n\t\t\t*(inst)++ = 0x00; break;\t\\\n\t\tcase 4: *(inst)++ = 0x8d; *(inst)++ = 0x64;\t\\\n\t\t\t*(inst)++ = 0x24; *(inst)++ = 0x00;\t\\\n\t\t\tbreak;\t\\\n\t\tcase 5: *(inst)++ = 0x8d; *(inst)++ = 0x64;\t\\\n\t\t\t*(inst)++ = 0x24; *(inst)++ = 0x00;\t\\\n\t\t\tx86_nop ((inst)); break;\t\\\n\t\tcase 6: *(inst)++ = 0x8d; *(inst)++ = 0xad;\t\\\n\t\t\t*(inst)++ = 0x00; *(inst)++ = 0x00;\t\\\n\t\t\t*(inst)++ = 0x00; *(inst)++ = 0x00;\t\\\n\t\t\tbreak;\t\\\n\t\tcase 7: *(inst)++ = 0x8d; *(inst)++ = 0xa4;\t\\\n\t\t\t*(inst)++ = 0x24; *(inst)++ = 0x00;\t\\\n\t\t\t*(inst)++ = 0x00; *(inst)++ = 0x00;\t\\\n\t\t\t*(inst)++ = 0x00; break;\t\\\n\t\tdefault: assert (0);\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_prolog(inst,frame_size,reg_mask)\t\\\n\tdo {\t\\\n\t\tunsigned i, m = 1;\t\\\n\t\tx86_enter ((inst), (frame_size));\t\\\n\t\tfor (i = 0; i < X86_NREG; ++i, m <<= 1) {\t\\\n\t\t\tif ((reg_mask) & m)\t\\\n\t\t\t\tx86_push_reg ((inst), i);\t\\\n\t\t}\t\\\n\t} while (0)\n\n#define x86_epilog(inst,reg_mask)\t\\\n\tdo {\t\\\n\t\tunsigned i, m = 1 << X86_EDI;\t\\\n\t\tfor (i = X86_EDI; m != 0; i--, m=m>>1) {\t\\\n\t\t\tif ((reg_mask) & m)\t\\\n\t\t\t\tx86_pop_reg ((inst), i);\t\\\n\t\t}\t\\\n\t\tx86_leave ((inst));\t\\\n\t\tx86_ret ((inst));\t\\\n\t} while (0)\n\n#endif // X86_H\n"
  },
  {
    "path": "tools/virtualmips/x86_trans.c",
    "content": "/*\n * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n *\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <string.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <sys/mman.h>\n#include <signal.h>\n#include <fcntl.h>\n#include <assert.h>\n\n#include \"cpu.h\"\n#include \"vm.h\"\n#include \"mips_exec.h\"\n#include \"mips_memory.h\"\n#include \"mips.h\"\n#include \"mips_cp0.h\"\n#include \"debug.h\"\n#include \"vp_timer.h\"\n#include \"x86_trans.h\"\n\n#ifdef _USE_JIT_\nstruct mips_jit_desc mips_jit[];\nstatic struct mips_jit_desc mips_spec_jit[];\nstatic struct mips_jit_desc mips_bcond_jit[];\nstatic struct mips_jit_desc mips_cop0_jit[];\nstatic struct mips_jit_desc mips_mad_jit[];\nstatic struct mips_jit_desc mips_tlb_jit[];\nvoid fastcall mips_exec_single_step (cpu_mips_t * cpu,\n    mips_insn_t instruction);\n\n#define REG_OFFSET(reg)       (OFFSET(cpu_mips_t,gpr[(reg)]))\n#define CP0_REG_OFFSET(c0reg) (OFFSET(cpu_mips_t,cp0.reg[(c0reg)]))\n#define MEMOP_OFFSET(op)      (OFFSET(cpu_mips_t,mem_op_fn[(op)]))\n\n/* Set the Pointer Counter (PC) register */\nvoid mips_set_pc (mips_jit_tcb_t * b, m_va_t new_pc)\n{\n    x86_mov_membase_imm (b->jit_ptr, X86_EDI, OFFSET (cpu_mips_t, pc),\n        new_pc & 0xFFFFFFFF, 4);\n}\n\n/* Set the Return Address (RA) register */\nvoid mips_set_ra (mips_jit_tcb_t * b, m_va_t ret_pc)\n{\n\n    x86_mov_membase_imm (b->jit_ptr, X86_EDI, REG_OFFSET (MIPS_GPR_RA),\n        ret_pc & 0xFFFFFFFF, 4);\n\n}\n\n/*\n * Try to branch directly to the specified JIT block without returning to\n * main loop.\n */\nstatic void mips_try_direct_far_jump (cpu_mips_t * cpu,\n    mips_jit_tcb_t * b, m_va_t new_pc)\n{\n    m_va_t new_page;\n    m_uint32_t pc_hash, pc_offset;\n    u_char *test1, *test2, *test3, *test4, *test5, *test6;\n\n    new_page = new_pc & MIPS_MIN_PAGE_MASK;\n    pc_offset = (new_pc & MIPS_MIN_PAGE_IMASK) >> 2;\n    pc_hash = mips_jit_get_pc_hash (cpu, new_pc);\n\n    /* Get JIT block info in %edx */\n    x86_mov_reg_membase (b->jit_ptr, X86_EBX,\n        X86_EDI, OFFSET (cpu_mips_t, exec_blk_map), 4);\n    x86_mov_reg_membase (b->jit_ptr, X86_EDX, X86_EBX,\n        pc_hash * sizeof (void *), 4);\n\n    /* no JIT block found ? */\n    x86_test_reg_reg (b->jit_ptr, X86_EDX, X86_EDX);\n    test1 = b->jit_ptr;\n    x86_branch8 (b->jit_ptr, X86_CC_Z, 0, 1);\n\n    /* Check block PC */\n    x86_mov_reg_imm (b->jit_ptr, X86_EAX, (m_uint32_t) new_page);\n    x86_alu_reg_membase (b->jit_ptr, X86_CMP, X86_EAX, X86_EDX,\n        OFFSET (mips_jit_tcb_t, start_pc));\n    test2 = b->jit_ptr;\n    x86_branch8 (b->jit_ptr, X86_CC_NE, 0, 1);\n\n    /*whether newpc is mapped */\n    x86_shift_reg_imm (b->jit_ptr, X86_SHR, X86_EAX, 29);\n    x86_alu_reg_imm (b->jit_ptr, X86_AND, X86_EAX, 0x7);\n\n    x86_alu_reg_imm (b->jit_ptr, X86_CMP, X86_EAX, 0x4);\n    test4 = b->jit_ptr;\n    x86_branch8 (b->jit_ptr, X86_CC_E, 0, 1);\n\n    x86_alu_reg_imm (b->jit_ptr, X86_CMP, X86_EAX, 0x5);\n    test5 = b->jit_ptr;\n    x86_branch8 (b->jit_ptr, X86_CC_E, 0, 1);\n\n    /*check ASID */\n    x86_lea_membase (b->jit_ptr, X86_ESI, X86_EDI, OFFSET (cpu_mips_t, cp0));\n    //x86_mov_reg_membase(b->jit_ptr,X86_ESI,\n    //                   X86_EDI,OFFSET(cpu_mips_t,cp0),4);\n    x86_mov_reg_membase (b->jit_ptr, X86_EBX,\n        X86_ESI, OFFSET (mips_cp0_t, reg[MIPS_CP0_TLB_HI]), 4);\n    x86_alu_reg_imm (b->jit_ptr, X86_AND, X86_EBX, MIPS_TLB_ASID_MASK);\n    x86_alu_reg_membase (b->jit_ptr, X86_CMP, X86_EBX, X86_EDX,\n        OFFSET (mips_jit_tcb_t, asid));\n    test6 = b->jit_ptr;\n    x86_branch8 (b->jit_ptr, X86_CC_NE, 0, 1);\n\n    x86_patch (test4, b->jit_ptr);\n    x86_patch (test5, b->jit_ptr);\n    /* Jump to the code */\n    x86_mov_reg_membase (b->jit_ptr, X86_ESI,\n        X86_EDX, OFFSET (mips_jit_tcb_t, jit_insn_ptr), 4);\n    x86_mov_reg_membase (b->jit_ptr, X86_EBX,\n        X86_ESI, pc_offset * sizeof (void *), 4);\n\n    x86_test_reg_reg (b->jit_ptr, X86_EBX, X86_EBX);\n    test3 = b->jit_ptr;\n    x86_branch8 (b->jit_ptr, X86_CC_Z, 0, 1);\n    x86_jump_reg (b->jit_ptr, X86_EBX);\n\n    /* Returns to caller... */\n    x86_patch (test1, b->jit_ptr);\n    x86_patch (test2, b->jit_ptr);\n    x86_patch (test3, b->jit_ptr);\n    x86_patch (test6, b->jit_ptr);\n\n    mips_set_pc (b, new_pc);\n    mips_jit_tcb_push_epilog (b);\n}\n\n/* Set Jump */\nstatic void mips_set_jump (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    m_va_t new_pc, int local_jump)\n{\n    int return_to_caller = FALSE;\n    u_char *jump_ptr;\n\n    if (!local_jump)\n        return_to_caller = TRUE;\n\n    if (!return_to_caller && mips_jit_tcb_local_addr (b, new_pc, &jump_ptr)) {\n        if (jump_ptr) {\n            x86_jump_code (b->jit_ptr, jump_ptr);\n        } else {\n            /* Never jump directly to code in a delay slot. */\n            /*Hi yajin, why a delay slot can have entry point or why have to jmp\n             * to delay slot?\n             * The following is the code from celinux 2.4.\n             *\n             * 802a19d4:   1500004a        bnez    t0,802a1b00 <src_unaligned_dst_aligned>\n             *\n             * 802a19d8 <both_aligned>:\n             * 802a19d8:   00064142        srl     t0,a2,0x5\n             *\n             * if call function both_aligned(0x802a19d8), it is in delay slot of 0x802a19d4 but it is\n             * the entry of function both_aligned.\n             * Just set pc to 0x802a19d8 and return main loop.\n             */\n            if (mips_jit_is_delay_slot (b, new_pc)) {\n                mips_set_pc (b, new_pc);\n                mips_jit_tcb_push_epilog (b);\n                return;\n            }\n\n            mips_jit_tcb_record_patch (b, b->jit_ptr, new_pc);\n            x86_jump32 (b->jit_ptr, 0);\n        }\n    } else {\n        mips_try_direct_far_jump (cpu, b, new_pc);\n\n#if 0\n        if (cpu->exec_blk_direct_jump) {\n            /* Block lookup optimization */\n            mips_try_direct_far_jump (cpu, b, new_pc);\n        } else {\n            mips_set_pc (b, new_pc);\n            mips_jit_tcb_push_epilog (b);\n        }\n#endif\n    }\n\n}\n\n/* Basic C call */\nvoid mips_emit_basic_c_call (mips_jit_tcb_t * b, void *f)\n{\n    x86_mov_reg_imm (b->jit_ptr, X86_EBX, f);\n    x86_call_reg (b->jit_ptr, X86_EBX);\n}\n\n/* Emit a simple call to a C function without any parameter */\nstatic void mips_emit_c_call (mips_jit_tcb_t * b, void *f)\n{\n    mips_set_pc (b, b->start_pc + ((b->mips_trans_pos - 1) << 2));\n    mips_emit_basic_c_call (b, f);\n}\n\n/* Single-step operation */\nvoid mips_emit_single_step (mips_jit_tcb_t * b, mips_insn_t insn)\n{\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    x86_mov_reg_imm (b->jit_ptr, X86_EDX, insn);\n    mips_emit_basic_c_call (b, mips_exec_single_step);\n}\n\n/* Memory operation */\n/*we use EAX EDX ECX to transfer parameter. yajin.\nMakesure memory operation DONOT have more than 3 parameters*/\nstatic void mips_emit_memop (mips_jit_tcb_t * b, int op, int base,\n    int offset, int target, int keep_ll_bit)\n{\n    m_va_t val = sign_extend (offset, 16);\n    m_uint8_t *test1;\n\n    /* Save PC for exception handling */\n    mips_set_pc (b, b->start_pc + ((b->mips_trans_pos - 1) << 2));\n\n    if (!keep_ll_bit) {\n        x86_clear_reg (b->jit_ptr, X86_EAX);\n        x86_mov_membase_reg (b->jit_ptr, X86_EDI, OFFSET (cpu_mips_t, ll_bit),\n            X86_EAX, 4);\n    }\n\n    x86_mov_reg_imm (b->jit_ptr, X86_EDX, val);\n\n    /* EDX = GPR[base] + sign-extended offset */\n    x86_alu_reg_membase (b->jit_ptr, X86_ADD, X86_EDX, X86_EDI,\n        REG_OFFSET (base));\n\n    /* ECX = target register */\n    x86_mov_reg_imm (b->jit_ptr, X86_ECX, target);\n\n    /* EAX = CPU instance pointer */\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EBX, X86_EDI, MEMOP_OFFSET (op), 4);\n    x86_call_reg (b->jit_ptr, X86_EBX);\n\n    /*check the return value */\n    x86_alu_reg_imm (b->jit_ptr, X86_CMP, X86_EAX, 0);\n    /*IF return value==0.NO exception. */\n    test1 = b->jit_ptr;\n    x86_branch8 (b->jit_ptr, X86_CC_E, 0, 1);\n    mips_jit_tcb_push_epilog (b);\n    x86_patch (test1, b->jit_ptr);\n\n}\n\n/* Unknown opcode handler */\nstatic asmlinkage void mips_unknown_opcode (cpu_mips_t * cpu,\n    m_uint32_t opcode)\n{\n    printf (\"MIPS64: unhandled opcode 0x%8.8x at 0x%\" LL \"x (ra=0x%\" LL\n        \"x)\\n\", opcode, cpu->pc, cpu->gpr[MIPS_GPR_RA]);\n\n    //mips_dump_regs(cpu);\n}\n\n/* Emit unhandled instruction code */\nstatic int mips_emit_unknown (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    mips_insn_t opcode)\n{\n    x86_mov_reg_imm (b->jit_ptr, X86_EAX, opcode);\n    x86_alu_reg_imm (b->jit_ptr, X86_SUB, X86_ESP, 4);\n    x86_push_reg (b->jit_ptr, X86_EAX);\n    x86_push_reg (b->jit_ptr, X86_EDI);\n    mips_emit_c_call (b, mips_unknown_opcode);\n    x86_alu_reg_imm (b->jit_ptr, X86_ADD, X86_ESP, 12);\n    return (0);\n}\n\n/* Invalid delay slot handler */\nstatic fastcall void mips_invalid_delay_slot (cpu_mips_t * cpu)\n{\n    printf (\"MIPS64: invalid instruction in delay slot at 0x%\" LL \"x (ra=0x%\"\n        LL \"x)\\n\", cpu->pc, cpu->gpr[MIPS_GPR_RA]);\n\n    //mips_dump_regs(cpu);\n\n    /* Halt the virtual CPU */\n    cpu->pc = 0;\n}\n\n/* Emit unhandled instruction code */\nint mips_emit_invalid_delay_slot (mips_jit_tcb_t * b)\n{\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_c_call (b, mips_invalid_delay_slot);\n    x86_alu_reg_imm (b->jit_ptr, X86_ADD, X86_ESP, 12);\n\n    mips_jit_tcb_push_epilog (b);\n    return (0);\n}\n\nvoid mips_check_cpu_pausing (mips_jit_tcb_t * b)\n{\n    u_char *test1;\n\n    /* Check pause_request */\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX,\n        X86_EDI, OFFSET (cpu_mips_t, pause_request), 4);\n    x86_alu_reg_imm (b->jit_ptr, X86_AND, X86_EAX, CPU_INTERRUPT_EXIT);\n    x86_alu_reg_imm (b->jit_ptr, X86_CMP, X86_EAX, CPU_INTERRUPT_EXIT);\n    test1 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_NE, 0, 1);\n    /*if (cpu->pause_request)&CPU_INTERRUPT_EXIT==CPU_INTERRUPT_EXIT,\n     * set cpu->state and return to main loop */\n    mips_set_pc (b, b->start_pc + ((b->mips_trans_pos - 1) << 2));\n    x86_mov_membase_imm (b->jit_ptr, X86_EDI, OFFSET (cpu_mips_t, state),\n        CPU_STATE_PAUSING, 4);\n    mips_jit_tcb_push_epilog (b);\n    /*else do noting */\n    x86_patch (test1, b->jit_ptr);\n\n}\n\n/* Check if there are pending IRQ */\nvoid mips_check_pending_irq (mips_jit_tcb_t * b)\n{\n    u_char *test1;\n\n    /* Check the pending IRQ flag */\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX,\n        X86_EDI, OFFSET (cpu_mips_t, irq_pending), 4);\n    x86_test_reg_reg (b->jit_ptr, X86_EAX, X86_EAX);\n    test1 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_Z, 0, 1);\n\n    /* Save PC */\n    mips_set_pc (b, b->start_pc + ((b->mips_trans_pos - 1) << 2));\n\n    /* Trigger the IRQ */\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, mips_trigger_irq);\n    mips_jit_tcb_push_epilog (b);\n\n    x86_patch (test1, b->jit_ptr);\n}\n\n/* ADD */\nstatic int mips_emit_add (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    //printf(\"rs %d rt %d rd %d \\n\",rs,rt,rd);\n\n    /* TODO: Exception handling */\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_alu_reg_membase (b->jit_ptr, X86_ADD, X86_EAX, X86_EDI,\n        REG_OFFSET (rt));\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_EAX, 4);\n\n    return (0);\n}\n\n/* ADDI */\nstatic int mips_emit_addi (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int imm = bits (insn, 0, 15);\n    m_uint32_t val = sign_extend (imm, 16);\n    // printf(\"rs %d rt %d val %d \\n\",rs,rt,val);\n    /* TODO: Exception handling */\n\n    x86_mov_reg_imm (b->jit_ptr, X86_EAX, val);\n    x86_alu_reg_membase (b->jit_ptr, X86_ADD, X86_EAX, X86_EDI,\n        REG_OFFSET (rs));\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rt), X86_EAX, 4);\n    return (0);\n}\n\n/* ADDI */\nstatic int mips_emit_addiu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int imm = bits (insn, 0, 15);\n    m_uint32_t val = sign_extend (imm, 16);\n    // printf(\"rs %d rt %d val %d \\n\",rs,rt,val);\n    /* TODO: Exception handling */\n\n    x86_mov_reg_imm (b->jit_ptr, X86_EAX, val);\n    x86_alu_reg_membase (b->jit_ptr, X86_ADD, X86_EAX, X86_EDI,\n        REG_OFFSET (rs));\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rt), X86_EAX, 4);\n    return (0);\n}\n\n/* ADDu */\nstatic int mips_emit_addu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    //  printf(\"rs %d rt %d rd %d \\n\",rs,rt,rd);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_alu_reg_membase (b->jit_ptr, X86_ADD, X86_EAX, X86_EDI,\n        REG_OFFSET (rt));\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_EAX, 4);\n\n    return (0);\n}\n\n/* AND */\nstatic int mips_emit_and (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_alu_reg_membase (b->jit_ptr, X86_AND, X86_EAX, X86_EDI,\n        REG_OFFSET (rt));\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_EAX, 4);\n    return (0);\n}\n\n/* ANDI */\nstatic int mips_emit_andi (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int imm = bits (insn, 0, 15);\n\n    x86_mov_reg_imm (b->jit_ptr, X86_EAX, imm);\n    x86_alu_reg_membase (b->jit_ptr, X86_AND, X86_EAX, X86_EDI,\n        REG_OFFSET (rs));\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rt), X86_EAX, 4);\n    return (0);\n}\n\nstatic int mips_emit_bcond (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    uint16_t special_func = bits (insn, 16, 20);\n    return mips_bcond_jit[special_func].emit_func (cpu, b, insn);\n}\n\n/*\nHi yajin, why we need call mips_jit_fetch_and_emit twice?\nWhy do we translate beq like this:\n\nmips_jit_fetch_and_emit(cpu,b,1);\nx86_mov_reg_membase(b->jit_ptr,X86_EAX,X86_EDI,REG_OFFSET(rs),4);\nx86_alu_reg_membase(b->jit_ptr,X86_CMP,X86_EAX,X86_EDI,REG_OFFSET(rt));\ntest1 = b->jit_ptr;\nx86_branch32(b->jit_ptr, X86_CC_NE, 0, 1);\nmips_set_jump(cpu,b,new_pc,1);\nx86_patch(test1,b->jit_ptr);\n\nThat is fetching the delay slot code first and then jumping to new pc according to\nthe comparing result of register rs and register rt.\n\nThis seems right but it is wrong and not easy to catch this bug!!!\n\nThe instruction in delay slot may change the content of register rs and rt and the\ncomparing result can not be trusted anymore.\nWe MUST compare register rs and rt and then run the code in delay slot.\n\n*/\n/* BEQ (Branch On Equal) */\nstatic int mips_emit_beq (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n    u_char *test1;\n    m_va_t new_pc;\n\n    /* compute the new pc */\n    new_pc = b->start_pc + (b->mips_trans_pos << 2);\n    new_pc += sign_extend (offset << 2, 18);\n\n    /*\n     * compare gpr[rs] and gpr[rt].\n     * compare the low 32 bits first (higher probability).\n     */\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_alu_reg_membase (b->jit_ptr, X86_CMP, X86_EAX, X86_EDI,\n        REG_OFFSET (rt));\n    test1 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_NE, 0, 1);\n\n    /* insert the instruction in the delay slot */\n    mips_jit_fetch_and_emit (cpu, b, 2);\n\n    /* set the new pc in cpu structure */\n    mips_set_jump (cpu, b, new_pc, 1);\n\n    x86_patch (test1, b->jit_ptr);\n\n    /* if the branch is not taken, we have to execute the delay slot too */\n    mips_jit_fetch_and_emit (cpu, b, 1);\n    return (0);\n}\n\n/* BEQL (Branch On Equal Likely) */\nstatic int mips_emit_beql (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n    u_char *test1;\n    m_va_t new_pc;\n\n    /* compute the new pc */\n    new_pc = b->start_pc + (b->mips_trans_pos << 2);\n    new_pc += sign_extend (offset << 2, 18);\n\n    /*\n     * compare gpr[rs] and gpr[rt].\n     * compare the low 32 bits first (higher probability).\n     */\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_alu_reg_membase (b->jit_ptr, X86_CMP, X86_EAX, X86_EDI,\n        REG_OFFSET (rt));\n    test1 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_NE, 0, 1);\n    /* insert the instruction in the delay slot */\n    mips_jit_fetch_and_emit (cpu, b, 1);\n    /* set the new pc in cpu structure */\n    mips_set_jump (cpu, b, new_pc, 1);\n\n    x86_patch (test1, b->jit_ptr);\n    return (0);\n}\n\n/* BGEZ (Branch On Greater or Equal Than Zero) */\nstatic int mips_emit_bgez (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    u_char *test1;\n    m_va_t new_pc;\n\n    /* compute the new pc */\n    new_pc = b->start_pc + (b->mips_trans_pos << 2);\n    new_pc += sign_extend (offset << 2, 18);\n\n    /* If sign bit is set, don't take the branch */\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_test_reg_reg (b->jit_ptr, X86_EAX, X86_EAX);\n    test1 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_S, 0, 1);\n\n    /* insert the instruction in the delay slot */\n    mips_jit_fetch_and_emit (cpu, b, 2);\n\n    /* set the new pc in cpu structure */\n    mips_set_jump (cpu, b, new_pc, 1);\n\n    x86_patch (test1, b->jit_ptr);\n\n    /* if the branch is not taken, we have to execute the delay slot too */\n    mips_jit_fetch_and_emit (cpu, b, 1);\n    return (0);\n}\n\n/* BGEZAL (Branch On Greater or Equal Than Zero And Link) */\nstatic int mips_emit_bgezal (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    u_char *test1;\n    m_va_t new_pc;\n\n    /* compute the new pc */\n    new_pc = b->start_pc + (b->mips_trans_pos << 2);\n    new_pc += sign_extend (offset << 2, 18);\n\n    /* set the return address (instruction after the delay slot) */\n    mips_set_ra (b, b->start_pc + ((b->mips_trans_pos + 1) << 2));\n\n    /* If sign bit is set, don't take the branch */\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_test_reg_reg (b->jit_ptr, X86_EAX, X86_EAX);\n    test1 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_S, 0, 1);\n\n    /* insert the instruction in the delay slot */\n    mips_jit_fetch_and_emit (cpu, b, 2);\n\n    /* set the new pc in cpu structure */\n    mips_set_jump (cpu, b, new_pc, 1);\n\n    x86_patch (test1, b->jit_ptr);\n\n    /* if the branch is not taken, we have to execute the delay slot too */\n    mips_jit_fetch_and_emit (cpu, b, 1);\n    return (0);\n}\n\n/* BGEZALL (Branch On Greater or Equal Than Zero and Link Likely) */\nstatic int mips_emit_bgezall (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    u_char *test1;\n    m_va_t new_pc;\n\n    /* compute the new pc */\n    new_pc = b->start_pc + (b->mips_trans_pos << 2);\n    new_pc += sign_extend (offset << 2, 18);\n\n    /* set the return address (instruction after the delay slot) */\n    mips_set_ra (b, b->start_pc + ((b->mips_trans_pos + 1) << 2));\n\n    /* if sign bit is set, don't take the branch */\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_test_reg_reg (b->jit_ptr, X86_EAX, X86_EAX);\n    test1 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_S, 0, 1);\n\n    /* insert the instruction in the delay slot */\n    mips_jit_fetch_and_emit (cpu, b, 1);\n\n    /* set the new pc in cpu structure */\n    mips_set_jump (cpu, b, new_pc, 1);\n\n    x86_patch (test1, b->jit_ptr);\n    return (0);\n}\n\n/* BGEZL (Branch On Greater or Equal Than Zero Likely) */\nstatic int mips_emit_bgezl (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    u_char *test1;\n    m_va_t new_pc;\n\n    /* compute the new pc */\n    new_pc = b->start_pc + (b->mips_trans_pos << 2);\n    new_pc += sign_extend (offset << 2, 18);\n\n    /* if sign bit is set, don't take the branch */\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_test_reg_reg (b->jit_ptr, X86_EAX, X86_EAX);\n    test1 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_S, 0, 1);\n\n    /* insert the instruction in the delay slot */\n    mips_jit_fetch_and_emit (cpu, b, 1);\n\n    /* set the new pc in cpu structure */\n    mips_set_jump (cpu, b, new_pc, 1);\n\n    x86_patch (test1, b->jit_ptr);\n    return (0);\n}\n\n/* BGTZ (Branch On Greater Than Zero) */\nstatic int mips_emit_bgtz (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    u_char *test1, *test2;\n    m_va_t new_pc;\n\n    /* compute the new pc */\n    new_pc = b->start_pc + (b->mips_trans_pos << 2);\n    new_pc += sign_extend (offset << 2, 18);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_test_reg_reg (b->jit_ptr, X86_EAX, X86_EAX);\n    /*goto end if <0 */\n    test1 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_S, 0, 1);\n    /*goto end if =0 */\n    test2 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_Z, 0, 1);\n\n    /* here, we take the branch */\n    //x86_patch(test2,b->jit_ptr);\n\n    /* insert the instruction in the delay slot */\n    mips_jit_fetch_and_emit (cpu, b, 2);\n\n    /* set the new pc in cpu structure */\n    mips_set_jump (cpu, b, new_pc, 1);\n\n    x86_patch (test1, b->jit_ptr);\n    x86_patch (test2, b->jit_ptr);\n\n    /* if the branch is not taken, we have to execute the delay slot too */\n    mips_jit_fetch_and_emit (cpu, b, 1);\n    return (0);\n}\n\n/* BGTZL (Branch On Greater Than Zero Likely) */\nstatic int mips_emit_bgtzl (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    u_char *test1, *test2;\n    m_va_t new_pc;\n\n    /* compute the new pc */\n    new_pc = b->start_pc + (b->mips_trans_pos << 2);\n    new_pc += sign_extend (offset << 2, 18);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_test_reg_reg (b->jit_ptr, X86_EAX, X86_EAX);\n    /*goto end if <0 */\n    test1 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_S, 0, 1);\n    /*goto end if =0 */\n    test2 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_Z, 0, 1);\n\n    /* here, we take the branch */\n    // x86_patch(test2,b->jit_ptr);\n\n    /* insert the instruction in the delay slot */\n    mips_jit_fetch_and_emit (cpu, b, 1);\n\n    /* set the new pc in cpu structure */\n    mips_set_jump (cpu, b, new_pc, 1);\n\n    x86_patch (test1, b->jit_ptr);\n    x86_patch (test2, b->jit_ptr);\n    return (0);\n}\n\n/* BLEZ (Branch On Less or Equal Than Zero) */\nstatic int mips_emit_blez (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    u_char *test1, *test2;\n    m_va_t new_pc;\n\n    /* compute the new pc */\n    new_pc = b->start_pc + (b->mips_trans_pos << 2);\n    new_pc += sign_extend (offset << 2, 18);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_test_reg_reg (b->jit_ptr, X86_EAX, X86_EAX);\n    /*if <0, take the branch */\n    test1 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_S, 0, 1);\n    /*else if !=0, do not take the branch */\n    test2 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_NZ, 0, 1);\n\n    /* here, we take the branch */\n    x86_patch (test1, b->jit_ptr);\n\n    /* insert the instruction in the delay slot */\n    mips_jit_fetch_and_emit (cpu, b, 2);\n\n    /* set the new pc in cpu structure */\n    mips_set_jump (cpu, b, new_pc, 1);\n\n    x86_patch (test2, b->jit_ptr);\n\n    /* if the branch is not taken, we have to execute the delay slot too */\n    mips_jit_fetch_and_emit (cpu, b, 1);\n    return (0);\n}\n\n/* BLEZL (Branch On Less or Equal Than Zero Likely) */\nstatic int mips_emit_blezl (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    u_char *test1, *test2;\n    m_va_t new_pc;\n\n    /* compute the new pc */\n    new_pc = b->start_pc + (b->mips_trans_pos << 2);\n    new_pc += sign_extend (offset << 2, 18);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_test_reg_reg (b->jit_ptr, X86_EAX, X86_EAX);\n    /*if <0, take the branch */\n    test1 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_S, 0, 1);\n    /*else if !=0, do not take the branch */\n    test2 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_NZ, 0, 1);\n\n    /* here, we take the branch */\n    x86_patch (test1, b->jit_ptr);\n\n    /* insert the instruction in the delay slot */\n    mips_jit_fetch_and_emit (cpu, b, 1);\n\n    /* set the new pc in cpu structure */\n    mips_set_jump (cpu, b, new_pc, 1);\n\n    x86_patch (test2, b->jit_ptr);\n    return (0);\n}\n\n/* BLTZ (Branch On Less Than Zero) */\nstatic int mips_emit_bltz (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    u_char *test1;\n    m_va_t new_pc;\n\n    /* compute the new pc */\n    new_pc = b->start_pc + (b->mips_trans_pos << 2);\n    new_pc += sign_extend (offset << 2, 18);\n\n    /*\n     * test the sign bit of gpr[rs], if set, take the branch.\n     */\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_test_reg_reg (b->jit_ptr, X86_EAX, X86_EAX);\n    test1 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_NS, 0, 1);\n\n    /* insert the instruction in the delay slot */\n    mips_jit_fetch_and_emit (cpu, b, 2);\n\n    /* set the new pc in cpu structure */\n    mips_set_jump (cpu, b, new_pc, 1);\n\n    x86_patch (test1, b->jit_ptr);\n\n    /* if the branch is not taken, we have to execute the delay slot too */\n    mips_jit_fetch_and_emit (cpu, b, 1);\n    return (0);\n}\n\n/* BLTZAL (Branch On Less Than Zero And Link) */\nstatic int mips_emit_bltzal (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    u_char *test1;\n    m_va_t new_pc;\n\n    /* compute the new pc */\n    new_pc = b->start_pc + (b->mips_trans_pos << 2);\n    new_pc += sign_extend (offset << 2, 18);\n\n    /* set the return address (instruction after the delay slot) */\n    mips_set_ra (b, b->start_pc + ((b->mips_trans_pos + 1) << 2));\n\n    /*\n     * test the sign bit of gpr[rs], if set, take the branch.\n     */\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_test_reg_reg (b->jit_ptr, X86_EAX, X86_EAX);\n    test1 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_NS, 0, 1);\n\n    /* insert the instruction in the delay slot */\n    mips_jit_fetch_and_emit (cpu, b, 2);\n\n    /* set the new pc in cpu structure */\n    mips_set_jump (cpu, b, new_pc, 1);\n\n    x86_patch (test1, b->jit_ptr);\n\n    /* if the branch is not taken, we have to execute the delay slot too */\n    mips_jit_fetch_and_emit (cpu, b, 1);\n    return (0);\n}\n\n/* BLTZALL (Branch On Less Than Zero And Link Likely) */\nstatic int mips_emit_bltzall (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    u_char *test1;\n    m_va_t new_pc;\n\n    /* compute the new pc */\n    new_pc = b->start_pc + (b->mips_trans_pos << 2);\n    new_pc += sign_extend (offset << 2, 18);\n\n    /* set the return address (instruction after the delay slot) */\n    mips_set_ra (b, b->start_pc + ((b->mips_trans_pos + 1) << 2));\n\n    /*\n     * test the sign bit of gpr[rs], if set, take the branch.\n     */\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_test_reg_reg (b->jit_ptr, X86_EAX, X86_EAX);\n    test1 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_NS, 0, 1);\n\n    /* insert the instruction in the delay slot */\n    mips_jit_fetch_and_emit (cpu, b, 1);\n\n    /* set the new pc in cpu structure */\n    mips_set_jump (cpu, b, new_pc, 1);\n\n    x86_patch (test1, b->jit_ptr);\n    return (0);\n}\n\n/* BLTZL (Branch On Less Than Zero Likely) */\nstatic int mips_emit_bltzl (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int offset = bits (insn, 0, 15);\n    u_char *test1;\n    m_va_t new_pc;\n\n    /* compute the new pc */\n    new_pc = b->start_pc + (b->mips_trans_pos << 2);\n    new_pc += sign_extend (offset << 2, 18);\n\n    /*\n     * test the sign bit of gpr[rs], if set, take the branch.\n     */\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_test_reg_reg (b->jit_ptr, X86_EAX, X86_EAX);\n    test1 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_NS, 0, 1);\n\n    /* insert the instruction in the delay slot */\n    mips_jit_fetch_and_emit (cpu, b, 1);\n\n    /* set the new pc in cpu structure */\n    mips_set_jump (cpu, b, new_pc, 1);\n\n    x86_patch (test1, b->jit_ptr);\n    return (0);\n}\n\n/* BNE (Branch On Not Equal) */\nstatic int mips_emit_bne (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n    u_char *test2;\n    m_va_t new_pc;\n\n    /* compute the new pc */\n    new_pc = b->start_pc + (b->mips_trans_pos << 2);\n    new_pc += sign_extend (offset << 2, 18);\n\n    /*\n     * compare gpr[rs] and gpr[rt].\n     * compare the low 32 bits first (higher probability).\n     */\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_alu_reg_membase (b->jit_ptr, X86_CMP, X86_EAX, X86_EDI,\n        REG_OFFSET (rt));\n    test2 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_E, 0, 1);\n\n    /* insert the instruction in the delay slot */\n    mips_jit_fetch_and_emit (cpu, b, 2);\n\n    /* set the new pc in cpu structure */\n    mips_set_jump (cpu, b, new_pc, 1);\n\n    x86_patch (test2, b->jit_ptr);\n\n    /* if the branch is not taken, we have to execute the delay slot too */\n    mips_jit_fetch_and_emit (cpu, b, 1);\n    return (0);\n}\n\n/* BNEL (Branch On Not Equal Likely) */\nstatic int mips_emit_bnel (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n    u_char *test2;\n    m_va_t new_pc;\n\n    /* compute the new pc */\n    new_pc = b->start_pc + (b->mips_trans_pos << 2);\n    new_pc += sign_extend (offset << 2, 18);\n\n    /*\n     * compare gpr[rs] and gpr[rt].\n     * compare the low 32 bits first (higher probability).\n     */\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_alu_reg_membase (b->jit_ptr, X86_CMP, X86_EAX, X86_EDI,\n        REG_OFFSET (rt));\n    test2 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_E, 0, 1);\n\n    /* insert the instruction in the delay slot */\n    mips_jit_fetch_and_emit (cpu, b, 1);\n\n    /* set the new pc in cpu structure */\n    mips_set_jump (cpu, b, new_pc, 1);\n\n    x86_patch (test2, b->jit_ptr);\n\n    return (0);\n}\n\n/* BREAK */\nstatic int mips_emit_break (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    u_int code = bits (insn, 6, 25);\n\n    //x86_alu_reg_imm(b->jit_ptr,X86_SUB,X86_ESP,12);\n    x86_mov_reg_imm (b->jit_ptr, X86_EDX, code);\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, mips_exec_break);\n    x86_alu_reg_imm (b->jit_ptr, X86_ADD, X86_ESP, 12);\n\n    mips_jit_tcb_push_epilog (b);\n    return (0);\n}\n\n/* CACHE */\nstatic int mips_emit_cache (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int base = bits (insn, 21, 25);\n    int op = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    mips_emit_memop (b, MIPS_MEMOP_CACHE, base, offset, op, FALSE);\n    return (0);\n}\n\nstatic int mips_emit_cfc0 (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int fastcall clz_emu (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rd = bits (insn, 11, 15);\n    int i;\n    m_uint32_t val;\n    val = 32;\n    for (i = 31; i >= 0; i--) {\n        if (cpu->gpr[rs] & (1 << i)) {\n            val = 31 - i;\n            break;\n        }\n    }\n    cpu->gpr[rd] = val;\n    return (0);\n\n}\n\nstatic int mips_emit_clz (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    //x86_alu_reg_imm(b->jit_ptr,X86_SUB,X86_ESP,12);\n    x86_mov_reg_imm (b->jit_ptr, X86_EDX, insn);\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, clz_emu);\n    return (0);\n}\n\nstatic int mips_emit_cop0 (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    uint16_t special_func = bits (insn, 21, 25);\n    return mips_cop0_jit[special_func].emit_func (cpu, b, insn);\n}\n\nstatic int mips_emit_cop1 (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n#if SOFT_FPU\n    /* Save PC for exception handling */\n    mips_set_pc (b, b->start_pc + ((b->mips_trans_pos - 1) << 2));\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, mips_exec_soft_fpu);\n    mips_jit_tcb_push_epilog (b);\n    return (0);\n#else\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n#endif\n}\n\nstatic int mips_emit_cop1x (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n#if SOFT_FPU\n    /* Save PC for exception handling */\n    mips_set_pc (b, b->start_pc + ((b->mips_trans_pos - 1) << 2));\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, mips_exec_soft_fpu);\n    mips_jit_tcb_push_epilog (b);\n    return (0);\n#else\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n#endif\n\n}\n\nstatic int mips_emit_cop2 (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_dadd (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_daddi (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_daddiu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_daddu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_ddiv (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_ddivu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_div (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n\n    /* eax = gpr[rs] */\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_cdq (b->jit_ptr);\n    /* ebx = gpr[rt] */\n    x86_mov_reg_membase (b->jit_ptr, X86_EBX, X86_EDI, REG_OFFSET (rt), 4);\n\n    /* eax = quotient (LO), edx = remainder (HI) */\n    x86_div_reg (b->jit_ptr, X86_EBX, 1);\n\n    /* store LO */\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, OFFSET (cpu_mips_t, lo),\n        X86_EAX, 4);\n    /* store HI */\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, OFFSET (cpu_mips_t, hi),\n        X86_EDX, 4);\n\n    return (0);\n}\n\nstatic int mips_emit_divu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n\n    /* eax = gpr[rs] */\n    x86_clear_reg (b->jit_ptr, X86_EDX);\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    /* ebx = gpr[rt] */\n    x86_mov_reg_membase (b->jit_ptr, X86_EBX, X86_EDI, REG_OFFSET (rt), 4);\n\n    /* eax = quotient (LO), edx = remainder (HI) */\n    x86_div_reg (b->jit_ptr, X86_EBX, 0);\n\n    /* store LO */\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, OFFSET (cpu_mips_t, lo),\n        X86_EAX, 4);\n    /* store HI */\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, OFFSET (cpu_mips_t, hi),\n        X86_EDX, 4);\n    return (0);\n}\n\nstatic int mips_emit_dmfc0 (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_dmtc0 (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_dmult (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_dmultu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_dsll (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_dsllv (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_dsrlv (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_dsrav (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_dsub (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_dsubu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_dsrl (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_dsra (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_dsll32 (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_dsrl32 (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_dsra32 (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_eret (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_set_pc (b, b->start_pc + ((b->mips_trans_pos - 1) << 2));\n\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, mips_exec_eret);\n    mips_jit_tcb_push_epilog (b);\n    return (0);\n}\n\n/* J (Jump) */\nstatic int mips_emit_j (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    u_int instr_index = bits (insn, 0, 25);\n    m_va_t new_pc;\n\n    /* compute the new pc */\n    new_pc = b->start_pc + (b->mips_trans_pos << 2);\n    new_pc &= ~((1 << 28) - 1);\n    new_pc |= instr_index << 2;\n\n    /* insert the instruction in the delay slot */\n    mips_jit_fetch_and_emit (cpu, b, 1);\n\n    /* set the new pc in cpu structure */\n    mips_set_jump (cpu, b, new_pc, 1);\n    return (0);\n}\n\nstatic int mips_emit_jal (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    u_int instr_index = bits (insn, 0, 25);\n    m_va_t new_pc, ret_pc;\n\n    /* compute the new pc */\n    new_pc = b->start_pc + (b->mips_trans_pos << 2);\n    new_pc &= ~((1 << 28) - 1);\n    new_pc |= instr_index << 2;\n\n    /* set the return address (instruction after the delay slot) */\n    ret_pc = b->start_pc + ((b->mips_trans_pos + 1) << 2);\n    mips_set_ra (b, ret_pc);\n\n    /* insert the instruction in the delay slot */\n    mips_jit_fetch_and_emit (cpu, b, 1);\n\n    /* set the new pc in cpu structure */\n    mips_set_jump (cpu, b, new_pc, 0);\n    return (0);\n\n}\n\nstatic int mips_emit_jalr (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rd = bits (insn, 11, 15);\n    m_va_t ret_pc;\n\n    /* set the return pc (instruction after the delay slot) in GPR[rd] */\n    ret_pc = b->start_pc + ((b->mips_trans_pos + 1) << 2);\n    x86_mov_membase_imm (b->jit_ptr, X86_EDI, REG_OFFSET (rd), ret_pc, 4);\n\n    /* get the new pc */\n    x86_mov_reg_membase (b->jit_ptr, X86_ECX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, OFFSET (cpu_mips_t, ret_pc),\n        X86_ECX, 4);\n\n    /* insert the instruction in the delay slot */\n    mips_jit_fetch_and_emit (cpu, b, 1);\n\n    /* set the new pc */\n    x86_mov_reg_membase (b->jit_ptr, X86_ECX,\n        X86_EDI, OFFSET (cpu_mips_t, ret_pc), 4);\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, OFFSET (cpu_mips_t, pc),\n        X86_ECX, 4);\n\n    /* returns to the caller which will determine the next path */\n    mips_jit_tcb_push_epilog (b);\n    return (0);\n\n}\n\nstatic int mips_emit_jr (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n\n    /* get the new pc */\n    x86_mov_reg_membase (b->jit_ptr, X86_ECX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, OFFSET (cpu_mips_t, ret_pc),\n        X86_ECX, 4);\n\n    /* insert the instruction in the delay slot */\n    mips_jit_fetch_and_emit (cpu, b, 1);\n\n    /* set the new pc */\n    x86_mov_reg_membase (b->jit_ptr, X86_ECX,\n        X86_EDI, OFFSET (cpu_mips_t, ret_pc), 4);\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, OFFSET (cpu_mips_t, pc),\n        X86_ECX, 4);\n    /* returns to the caller which will determine the next path */\n    mips_jit_tcb_push_epilog (b);\n    return (0);\n\n}\n\nstatic int mips_emit_lb (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    mips_emit_memop (b, MIPS_MEMOP_LB, base, offset, rt, TRUE);\n    return (0);\n}\n\nstatic int mips_emit_lbu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    mips_emit_memop (b, MIPS_MEMOP_LBU, base, offset, rt, TRUE);\n    return (0);\n}\n\nstatic int mips_emit_ld (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_ldc1 (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_ldc2 (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_ldl (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_ldr (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_lh (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    mips_emit_memop (b, MIPS_MEMOP_LH, base, offset, rt, TRUE);\n    return (0);\n}\n\nstatic int mips_emit_lhu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    mips_emit_memop (b, MIPS_MEMOP_LHU, base, offset, rt, TRUE);\n    return (0);\n}\n\nstatic int mips_emit_ll (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    mips_emit_memop (b, MIPS_MEMOP_LL, base, offset, rt, TRUE);\n    return (0);\n}\n\nstatic int mips_emit_lld (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_lui (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rt = bits (insn, 16, 20);\n    int imm = bits (insn, 0, 15);\n    m_reg_t val = sign_extend (imm, 16) << 16;\n\n    x86_mov_membase_imm (b->jit_ptr, X86_EDI, REG_OFFSET (rt), val, 4);\n\n    return (0);\n}\n\nstatic int mips_emit_lw (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    mips_emit_memop (b, MIPS_MEMOP_LW, base, offset, rt, TRUE);\n    return (0);\n}\n\nstatic int mips_emit_lwc1 (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n#if SOFT_FPU\n    /* Save PC for exception handling */\n    mips_set_pc (b, b->start_pc + ((b->mips_trans_pos - 1) << 2));\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, mips_exec_soft_fpu);\n    mips_jit_tcb_push_epilog (b);\n    return (0);\n#else\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n#endif\n\n}\n\nstatic int mips_emit_lwc2 (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_lwl (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    mips_emit_memop (b, MIPS_MEMOP_LWL, base, offset, rt, TRUE);\n    return (0);\n}\n\nstatic int mips_emit_lwr (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    mips_emit_memop (b, MIPS_MEMOP_LWR, base, offset, rt, TRUE);\n    return (0);\n}\n\nstatic int mips_emit_lwu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    mips_emit_memop (b, MIPS_MEMOP_LWU, base, offset, rt, TRUE);\n    return (0);\n}\n\nstatic int mips_emit_mad (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int index = bits (insn, 0, 5);\n    return mips_mad_jit[index].emit_func (cpu, b, insn);\n}\n\nstatic int fastcall madd_emu (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    m_int64_t val, temp;\n\n    val = (m_int32_t) (m_int32_t) cpu->gpr[rs];\n    val *= (m_int32_t) (m_int32_t) cpu->gpr[rt];\n\n    temp = cpu->hi;\n    temp = temp << 32;\n    temp += cpu->lo;\n    val += temp;\n\n    cpu->lo = sign_extend (val, 32);\n    cpu->hi = sign_extend (val >> 32, 32);\n    return (0);\n\n}\n\nstatic int mips_emit_madd (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    //x86_alu_reg_imm(b->jit_ptr,X86_SUB,X86_ESP,12);\n    x86_mov_reg_imm (b->jit_ptr, X86_EDX, insn);\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, madd_emu);\n    return (0);\n}\n\nstatic int fastcall maddu_emu (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    m_int64_t val, temp;\n\n    val = (m_uint32_t) (m_uint32_t) cpu->gpr[rs];\n    val *= (m_uint32_t) (m_uint32_t) cpu->gpr[rt];\n\n    temp = cpu->hi;\n    temp = temp << 32;\n    temp += cpu->lo;\n    val += temp;\n\n    cpu->lo = sign_extend (val, 32);\n    cpu->hi = sign_extend (val >> 32, 32);\n    return (0);\n\n}\n\nstatic int mips_emit_maddu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    //x86_alu_reg_imm(b->jit_ptr,X86_SUB,X86_ESP,12);\n    x86_mov_reg_imm (b->jit_ptr, X86_EDX, insn);\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, maddu_emu);\n    return (0);\n}\n\nstatic int mips_emit_mfc0 (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    x86_mov_reg_imm (b->jit_ptr, X86_EDX, insn);\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, mips_cp0_exec_mfc0_fastcall);\n    return (0);\n\n}\n\nstatic int mips_emit_mfhi (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rd = bits (insn, 11, 15);\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, OFFSET (cpu_mips_t,\n            hi), 4);\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_EAX, 4);\n\n    return (0);\n}\n\nstatic int mips_emit_mflo (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rd = bits (insn, 11, 15);\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, OFFSET (cpu_mips_t,\n            lo), 4);\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_EAX, 4);\n    return (0);\n}\n\nstatic int mips_emit_movc (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_movz (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rd = bits (insn, 11, 15);\n    int rt = bits (insn, 16, 20);\n    u_char *test1;\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rt), 4);\n    x86_test_reg_reg (b->jit_ptr, X86_EAX, X86_EAX);\n    /*goto end if !=0 */\n    test1 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_NZ, 0, 1);\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_EAX, 4);\n\n    x86_patch (test1, b->jit_ptr);\n    return (0);\n\n}\n\nstatic int mips_emit_movn (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rd = bits (insn, 11, 15);\n    int rt = bits (insn, 16, 20);\n    u_char *test1;\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rt), 4);\n    x86_test_reg_reg (b->jit_ptr, X86_EAX, X86_EAX);\n    /*goto end if ==0 */\n    test1 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_Z, 0, 1);\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_EAX, 4);\n\n    x86_patch (test1, b->jit_ptr);\n    return (0);\n\n}\n\nstatic int fastcall msub_emu (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    m_int64_t val, temp;\n\n    val = (m_int32_t) (m_int32_t) cpu->gpr[rs];\n    val *= (m_int32_t) (m_int32_t) cpu->gpr[rt];\n\n    temp = cpu->hi;\n    temp = temp << 32;\n    temp += cpu->lo;\n\n    temp -= val;\n    //val += temp;\n\n    cpu->lo = sign_extend (temp, 32);\n    cpu->hi = sign_extend (temp >> 32, 32);\n    return (0);\n\n}\n\nstatic int mips_emit_msub (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    //x86_alu_reg_imm(b->jit_ptr,X86_SUB,X86_ESP,12);\n    x86_mov_reg_imm (b->jit_ptr, X86_EDX, insn);\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, msub_emu);\n    return (0);\n}\n\nstatic int fastcall msubu_emu (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    m_int64_t val, temp;\n\n    val = (m_uint32_t) (m_uint32_t) cpu->gpr[rs];\n    val *= (m_uint32_t) (m_uint32_t) cpu->gpr[rt];\n\n    temp = cpu->hi;\n    temp = temp << 32;\n    temp += cpu->lo;\n\n    temp -= val;\n\n    cpu->lo = sign_extend (temp, 32);\n    cpu->hi = sign_extend (temp >> 32, 32);\n    return (0);\n\n}\n\nstatic int mips_emit_msubu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    //x86_alu_reg_imm(b->jit_ptr,X86_SUB,X86_ESP,12);\n    x86_mov_reg_imm (b->jit_ptr, X86_EDX, insn);\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, msubu_emu);\n    return (0);\n}\n\nstatic int mips_emit_mtc0 (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    x86_mov_reg_imm (b->jit_ptr, X86_EDX, insn);\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, mips_cp0_exec_mtc0_fastcall);\n    return (0);\n\n}\n\nstatic fastcall int mthi_emu (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n\n    cpu->hi = cpu->gpr[rs];\n    return (0);\n}\n\nstatic fastcall int mtlo_emu (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n\n    cpu->lo = cpu->gpr[rs];\n    return (0);\n\n}\n\nstatic int mips_emit_mthi (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    //x86_alu_reg_imm(b->jit_ptr,X86_SUB,X86_ESP,12);\n    x86_mov_reg_imm (b->jit_ptr, X86_EDX, insn);\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, mthi_emu);\n    return (0);\n}\n\nstatic int mips_emit_mtlo (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    //x86_alu_reg_imm(b->jit_ptr,X86_SUB,X86_ESP,12);\n    x86_mov_reg_imm (b->jit_ptr, X86_EDX, insn);\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, mtlo_emu);\n    return (0);\n}\n\n/* MUL */\nstatic int mips_emit_mul (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_mov_reg_membase (b->jit_ptr, X86_EBX, X86_EDI, REG_OFFSET (rt), 4);\n\n    x86_mul_reg (b->jit_ptr, X86_EBX, 1);\n\n    /* store result in gpr[rd] */\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_EAX, 4);\n    return (0);\n}\n\nstatic int mips_emit_mult (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_mov_reg_membase (b->jit_ptr, X86_EBX, X86_EDI, REG_OFFSET (rt), 4);\n\n    x86_mul_reg (b->jit_ptr, X86_EBX, 1);\n\n    /* store LO */\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, OFFSET (cpu_mips_t, lo),\n        X86_EAX, 4);\n    /* store HI */\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, OFFSET (cpu_mips_t, hi),\n        X86_EDX, 4);\n    return (0);\n}\n\nstatic int mips_emit_multu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_mov_reg_membase (b->jit_ptr, X86_EBX, X86_EDI, REG_OFFSET (rt), 4);\n\n    x86_mul_reg (b->jit_ptr, X86_EBX, 0);\n\n    /* store LO */\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, OFFSET (cpu_mips_t, lo),\n        X86_EAX, 4);\n    /* store HI */\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, OFFSET (cpu_mips_t, hi),\n        X86_EDX, 4);\n    return (0);\n}\n\nstatic int mips_emit_nor (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_alu_reg_membase (b->jit_ptr, X86_OR, X86_EAX, X86_EDI,\n        REG_OFFSET (rt));\n    x86_not_reg (b->jit_ptr, X86_EAX);\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_EAX, 4);\n    return (0);\n\n}\n\nstatic int mips_emit_or (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_alu_reg_membase (b->jit_ptr, X86_OR, X86_EAX, X86_EDI,\n        REG_OFFSET (rt));\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_EAX, 4);\n    return (0);\n\n}\n\nstatic int mips_emit_ori (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int imm = bits (insn, 0, 15);\n\n    x86_mov_reg_imm (b->jit_ptr, X86_EAX, imm & 0xffff);\n    x86_alu_reg_membase (b->jit_ptr, X86_OR, X86_EAX, X86_EDI,\n        REG_OFFSET (rs));\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rt), X86_EAX, 4);\n    return (0);\n\n}\n\nstatic int mips_emit_pref (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    return (0);\n}\n\nstatic int mips_emit_sb (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    mips_emit_memop (b, MIPS_MEMOP_SB, base, offset, rt, TRUE);\n    return (0);\n}\n\nstatic int mips_emit_sc (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    mips_emit_memop (b, MIPS_MEMOP_SC, base, offset, rt, TRUE);\n    return (0);\n}\n\nstatic int mips_emit_scd (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_sd (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_sdc1 (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n#if SOFT_FPU\n    /* Save PC for exception handling */\n    mips_set_pc (b, b->start_pc + ((b->mips_trans_pos - 1) << 2));\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, mips_exec_soft_fpu);\n    mips_jit_tcb_push_epilog (b);\n    return (0);\n#else\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n#endif\n\n}\n\nstatic int mips_emit_sdc2 (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_sdl (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_sdr (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_sh (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    mips_emit_memop (b, MIPS_MEMOP_SH, base, offset, rt, TRUE);\n    return (0);\n}\n\nstatic int mips_emit_sll (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    int sa = bits (insn, 6, 10);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rt), 4);\n    x86_shift_reg_imm (b->jit_ptr, X86_SHL, X86_EAX, sa);\n\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_EAX, 4);\n    return (0);\n}\n\nstatic int mips_emit_sllv (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_ECX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_alu_reg_imm (b->jit_ptr, X86_AND, X86_ECX, 0x1f);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rt), 4);\n    x86_shift_reg (b->jit_ptr, X86_SHL, X86_EAX);\n\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_EAX, 4);\n    return (0);\n\n}\n\nstatic int mips_emit_slt (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    u_char *test1;\n\n    /* eax = gpr[rt] */\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rt), 4);\n    /* ecx = gpr[rs] */\n    x86_mov_reg_membase (b->jit_ptr, X86_ECX, X86_EDI, REG_OFFSET (rs), 4);\n\n    /* we set rd to 1 when gpr[rs] < gpr[rt] */\n    x86_clear_reg (b->jit_ptr, X86_ESI);\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_ESI, 4);\n\n    x86_alu_reg_reg (b->jit_ptr, X86_CMP, X86_ECX, X86_EAX);\n    /* rs >= rt => end */\n    test1 = b->jit_ptr;\n    x86_branch8 (b->jit_ptr, X86_CC_GE, 0, 1);\n    x86_inc_membase (b->jit_ptr, X86_EDI, REG_OFFSET (rd));\n    /* end */\n    x86_patch (test1, b->jit_ptr);\n    return (0);\n\n}\n\nstatic int mips_emit_slti (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int imm = bits (insn, 0, 15);\n    m_ireg_t val = sign_extend (imm, 16);\n    u_char *test1;\n\n    /* eax =val */\n    x86_mov_reg_imm (b->jit_ptr, X86_EAX, val);\n    /* ecx = gpr[rs] */\n    x86_mov_reg_membase (b->jit_ptr, X86_ECX, X86_EDI, REG_OFFSET (rs), 4);\n\n    /* we set rt to 1 when gpr[rs] < val */\n    x86_clear_reg (b->jit_ptr, X86_ESI);\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rt), X86_ESI, 4);\n\n    x86_alu_reg_reg (b->jit_ptr, X86_CMP, X86_ECX, X86_EAX);\n    /* rs >= val => end */\n    test1 = b->jit_ptr;\n    x86_branch8 (b->jit_ptr, X86_CC_GE, 0, 1);\n    x86_inc_membase (b->jit_ptr, X86_EDI, REG_OFFSET (rt));\n    /* end */\n    x86_patch (test1, b->jit_ptr);\n    return (0);\n\n}\n\nstatic int mips_emit_sltiu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int imm = bits (insn, 0, 15);\n    m_reg_t val = sign_extend (imm, 16);\n    u_char *test1;\n\n    /* eax =val */\n    x86_mov_reg_imm (b->jit_ptr, X86_EAX, val);\n    /* ecx = gpr[rs] */\n    x86_mov_reg_membase (b->jit_ptr, X86_ECX, X86_EDI, REG_OFFSET (rs), 4);\n\n    /* we set rt to 1 when gpr[rs] < val */\n    x86_clear_reg (b->jit_ptr, X86_ESI);\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rt), X86_ESI, 4);\n\n    x86_alu_reg_reg (b->jit_ptr, X86_CMP, X86_ECX, X86_EAX);\n    /* rs() >= val => end */\n    test1 = b->jit_ptr;\n    x86_branch8 (b->jit_ptr, X86_CC_GE, 0, 0);\n    x86_inc_membase (b->jit_ptr, X86_EDI, REG_OFFSET (rt));\n    /* end */\n    x86_patch (test1, b->jit_ptr);\n    return (0);\n\n}\n\nstatic int mips_emit_sltu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    u_char *test1;\n\n    /* eax = gpr[rt] */\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rt), 4);\n    /* ecx = gpr[rs] */\n    x86_mov_reg_membase (b->jit_ptr, X86_ECX, X86_EDI, REG_OFFSET (rs), 4);\n\n    /* we set rd to 1 when gpr[rs] < gpr[rt] */\n    x86_clear_reg (b->jit_ptr, X86_ESI);\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_ESI, 4);\n\n    x86_alu_reg_reg (b->jit_ptr, X86_CMP, X86_ECX, X86_EAX);\n    /* rs() >= rt(high) => end */\n    test1 = b->jit_ptr;\n    x86_branch8 (b->jit_ptr, X86_CC_GE, 0, 0);\n    x86_inc_membase (b->jit_ptr, X86_EDI, REG_OFFSET (rd));\n    /* end */\n    x86_patch (test1, b->jit_ptr);\n    return (0);\n\n}\n\nstatic int mips_emit_spec (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    uint16_t special_func = bits (insn, 0, 5);\n    return mips_spec_jit[special_func].emit_func (cpu, b, insn);\n}\n\nstatic int mips_emit_sra (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    int sa = bits (insn, 6, 10);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rt), 4);\n    x86_shift_reg_imm (b->jit_ptr, X86_SAR, X86_EAX, sa);\n\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_EAX, 4);\n    return (0);\n\n}\n\nstatic int mips_emit_srav (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_ECX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_alu_reg_imm (b->jit_ptr, X86_AND, X86_ECX, 0x1f);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rt), 4);\n    x86_shift_reg (b->jit_ptr, X86_SAR, X86_EAX);\n\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_EAX, 4);\n    return (0);\n\n}\n\nstatic int mips_emit_srl (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n    int sa = bits (insn, 6, 10);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rt), 4);\n    x86_shift_reg_imm (b->jit_ptr, X86_SHR, X86_EAX, sa);\n\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_EAX, 4);\n    return (0);\n\n}\n\nstatic int mips_emit_srlv (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_ECX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_alu_reg_imm (b->jit_ptr, X86_AND, X86_ECX, 0x1f);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rt), 4);\n    x86_shift_reg (b->jit_ptr, X86_SHR, X86_EAX);\n\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_EAX, 4);\n    return (0);\n\n}\n\nstatic int mips_emit_sub (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n\n    /* TODO: Exception handling */\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_alu_reg_membase (b->jit_ptr, X86_SUB, X86_EAX, X86_EDI,\n        REG_OFFSET (rt));\n\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_EAX, 4);\n    return (0);\n\n}\n\nstatic int mips_emit_subu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_alu_reg_membase (b->jit_ptr, X86_SUB, X86_EAX, X86_EDI,\n        REG_OFFSET (rt));\n\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_EAX, 4);\n    return (0);\n\n}\n\nstatic int mips_emit_sw (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    mips_emit_memop (b, MIPS_MEMOP_SW, base, offset, rt, TRUE);\n    return (0);\n}\n\nstatic int mips_emit_swc1 (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n#if SOFT_FPU\n    /* Save PC for exception handling */\n    mips_set_pc (b, b->start_pc + ((b->mips_trans_pos - 1) << 2));\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, mips_exec_soft_fpu);\n    mips_jit_tcb_push_epilog (b);\n    return (0);\n#else\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n#endif\n\n}\n\nstatic int mips_emit_swc2 (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_swl (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    mips_emit_memop (b, MIPS_MEMOP_SWL, base, offset, rt, TRUE);\n    return (0);\n}\n\nstatic int mips_emit_swr (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int base = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int offset = bits (insn, 0, 15);\n\n    mips_emit_memop (b, MIPS_MEMOP_SWR, base, offset, rt, TRUE);\n    return (0);\n}\n\nstatic int mips_emit_sync (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    return (0);\n}\n\nstatic int mips_emit_syscall (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_set_pc (b, b->start_pc + ((b->mips_trans_pos - 1) << 2));\n\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, mips_exec_syscall);\n\n    mips_jit_tcb_push_epilog (b);\n    return (0);\n\n}\n\nstatic int mips_emit_teq (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    u_char *test1;\n\n    /* Compare low part */\n    x86_mov_reg_membase (b->jit_ptr, X86_ECX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_alu_reg_membase (b->jit_ptr, X86_CMP, X86_ECX, X86_EDI,\n        REG_OFFSET (rt));\n    test1 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_NE, 0, 1);\n\n    /* Generate trap exception */\n    x86_alu_reg_imm (b->jit_ptr, X86_SUB, X86_ESP, 12);\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_c_call (b, mips_trigger_trap_exception);\n    x86_alu_reg_imm (b->jit_ptr, X86_ADD, X86_ESP, 12);\n\n    mips_jit_tcb_push_epilog (b);\n\n    /* end */\n    x86_patch (test1, b->jit_ptr);\n    return (0);\n\n}\n\nstatic int mips_emit_teqi (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int imm = bits (insn, 0, 15);\n    m_reg_t val = sign_extend (imm, 16);\n    u_char *test1;\n\n    /* edx:eax = val */\n    x86_mov_reg_imm (b->jit_ptr, X86_EAX, val);\n\n    /* Compare low part */\n    x86_mov_reg_membase (b->jit_ptr, X86_ECX, X86_EDI, REG_OFFSET (rs), 4);\n    x86_alu_reg_reg (b->jit_ptr, X86_CMP, X86_ECX, X86_EAX);\n    test1 = b->jit_ptr;\n    x86_branch32 (b->jit_ptr, X86_CC_NE, 0, 1);\n\n    /* Generate trap exception */\n    x86_alu_reg_imm (b->jit_ptr, X86_SUB, X86_ESP, 12);\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_c_call (b, mips_trigger_trap_exception);\n    x86_alu_reg_imm (b->jit_ptr, X86_ADD, X86_ESP, 12);\n\n    mips_jit_tcb_push_epilog (b);\n\n    /* end */\n    x86_patch (test1, b->jit_ptr);\n    return (0);\n\n}\n\nstatic int mips_emit_tlb (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    uint16_t func = bits (insn, 0, 5);\n    return mips_tlb_jit[func].emit_func (cpu, b, insn);\n}\n\nstatic int mips_emit_tlbp (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_set_pc (b, b->start_pc + ((b->mips_trans_pos - 1) << 2));\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, mips_cp0_exec_tlbp);\n    return (0);\n\n}\n\nstatic int mips_emit_tlbr (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_set_pc (b, b->start_pc + ((b->mips_trans_pos - 1) << 2));\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, mips_cp0_exec_tlbr);\n    return (0);\n\n}\n\nstatic int mips_emit_tlbwi (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_set_pc (b, b->start_pc + ((b->mips_trans_pos - 1) << 2));\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, mips_cp0_exec_tlbwi);\n    return (0);\n\n}\n\nstatic int mips_emit_tlbwr (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_set_pc (b, b->start_pc + ((b->mips_trans_pos - 1) << 2));\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, mips_cp0_exec_tlbwr);\n    return (0);\n\n}\n\nstatic int mips_emit_tge (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_tgei (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_tgeu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_tgeiu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_tlt (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_tlti (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_tltiu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_tltu (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int fastcall tne_emu (cpu_mips_t * cpu, mips_insn_t insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n\n    if ((m_ireg_t) cpu->gpr[rs] != (m_ireg_t) cpu->gpr[rt]) {\n        /*take a trap */\n        mips_trigger_trap_exception (cpu);\n        return (1);\n    } else\n        return (0);\n\n}\n\nstatic int mips_emit_tne (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    x86_mov_reg_imm (b->jit_ptr, X86_EDX, insn);\n    x86_mov_reg_reg (b->jit_ptr, X86_EAX, X86_EDI, 4);\n    mips_emit_basic_c_call (b, tne_emu);\n    return (0);\n\n}\n\nstatic int mips_emit_tnei (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_wait (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    return (0);\n}\n\nstatic int mips_emit_xor (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int rd = bits (insn, 11, 15);\n\n    x86_mov_reg_membase (b->jit_ptr, X86_EAX, X86_EDI, REG_OFFSET (rs), 4);\n\n    x86_alu_reg_membase (b->jit_ptr, X86_XOR, X86_EAX, X86_EDI,\n        REG_OFFSET (rt));\n\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rd), X86_EAX, 4);\n\n    return (0);\n\n}\n\nstatic int mips_emit_xori (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    int rs = bits (insn, 21, 25);\n    int rt = bits (insn, 16, 20);\n    int imm = bits (insn, 0, 15);\n\n    x86_mov_reg_imm (b->jit_ptr, X86_EAX, imm);\n    x86_alu_reg_membase (b->jit_ptr, X86_XOR, X86_EAX, X86_EDI,\n        REG_OFFSET (rs));\n\n    x86_mov_membase_reg (b->jit_ptr, X86_EDI, REG_OFFSET (rt), X86_EAX, 4);\n\n    return (0);\n\n}\n\nstatic int mips_emit_undef (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_unknownBcond (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_unknowncop0 (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_unknownmad (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_unknownSpec (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\nstatic int mips_emit_unknowntlb (cpu_mips_t * cpu, mips_jit_tcb_t * b,\n    unsigned int insn)\n{\n    mips_emit_unknown (cpu, b, insn);\n    return (0);\n}\n\n/*instruction table*/\n\nstruct mips_jit_desc mips_jit[] = {\n    {\"spec\", mips_emit_spec, 0x00, 0x99},\n    {\"bcond\", mips_emit_bcond, 0x01, 0x99},\n    {\"j\", mips_emit_j, 0x02, 0x0},\n    {\"jal\", mips_emit_jal, 0x03, 0x0},\n    {\"beq\", mips_emit_beq, 0x04, 0x0},\n    {\"bne\", mips_emit_bne, 0x05, 0x0},\n    {\"blez\", mips_emit_blez, 0x06, 0x0},\n    {\"bgtz\", mips_emit_bgtz, 0x07, 0x0},\n    {\"addi\", mips_emit_addi, 0x08, 0x1},\n    {\"addiu\", mips_emit_addiu, 0x09, 0x1},\n    {\"slti\", mips_emit_slti, 0x0A, 0x1},\n    {\"sltiu\", mips_emit_sltiu, 0x0B, 0x1},\n    {\"andi\", mips_emit_andi, 0x0C, 0x1},\n    {\"ori\", mips_emit_ori, 0x0D, 0x1},\n    {\"xori\", mips_emit_xori, 0x0E, 0x1},\n    {\"lui\", mips_emit_lui, 0x0F, 0x1},\n    {\"cop0\", mips_emit_cop0, 0x10, 0x99},\n    {\"cop1\", mips_emit_cop1, 0x11, 0x1},\n    {\"cop2\", mips_emit_cop2, 0x12, 0x1},\n    {\"cop1x\", mips_emit_cop1x, 0x13, 0x1},\n    {\"beql\", mips_emit_beql, 0x14, 0x0},\n    {\"bnel\", mips_emit_bnel, 0x15, 0x0},\n    {\"blezl\", mips_emit_blezl, 0x16, 0x0},\n    {\"bgtzl\", mips_emit_bgtzl, 0x17, 0x0},\n    {\"daddi\", mips_emit_daddi, 0x18, 0x1},\n    {\"daddiu\", mips_emit_daddiu, 0x19, 0x1},\n    {\"ldl\", mips_emit_ldl, 0x1A, 0x1},\n    {\"ldr\", mips_emit_ldr, 0x1B, 0x1},\n    {\"undef\", mips_emit_mad, 0x1C, 0x99},\n    {\"undef\", mips_emit_undef, 0x1D, 0x1},\n    {\"undef\", mips_emit_undef, 0x1E, 0x1},\n    {\"undef\", mips_emit_undef, 0x1F, 0x1},\n    {\"lb\", mips_emit_lb, 0x20, 0x1},\n    {\"lh\", mips_emit_lh, 0x21, 0x1},\n    {\"lwl\", mips_emit_lwl, 0x22, 0x1},\n    {\"lw\", mips_emit_lw, 0x23, 0x1},\n    {\"lbu\", mips_emit_lbu, 0x24, 0x1},\n    {\"lhu\", mips_emit_lhu, 0x25, 0x1},\n    {\"lwr\", mips_emit_lwr, 0x26, 0x1},\n    {\"lwu\", mips_emit_lwu, 0x27, 0x1},\n    {\"sb\", mips_emit_sb, 0x28, 0x1},\n    {\"sh\", mips_emit_sh, 0x29, 0x1},\n    {\"swl\", mips_emit_swl, 0x2A, 0x1},\n    {\"sw\", mips_emit_sw, 0x2B, 0x1},\n    {\"sdl\", mips_emit_sdl, 0x2C, 0x1},\n    {\"sdr\", mips_emit_sdr, 0x2D, 0x1},\n    {\"swr\", mips_emit_swr, 0x2E, 0x1},\n    {\"cache\", mips_emit_cache, 0x2F, 0x1},\n    {\"ll\", mips_emit_ll, 0x30, 0x1},\n    {\"lwc1\", mips_emit_lwc1, 0x31, 0x1},\n    {\"lwc2\", mips_emit_lwc2, 0x32, 0x1},\n    {\"pref\", mips_emit_pref, 0x33, 0x1},\n    {\"lld\", mips_emit_lld, 0x34, 0x1},\n    {\"ldc1\", mips_emit_ldc1, 0x35, 0x1},\n    {\"ldc2\", mips_emit_ldc2, 0x36, 0x1},\n    {\"ld\", mips_emit_ld, 0x37, 0x1},\n    {\"sc\", mips_emit_sc, 0x38, 0x1},\n    {\"swc1\", mips_emit_swc1, 0x39, 0x1},\n    {\"swc2\", mips_emit_swc2, 0x3A, 0x1},\n    {\"undef\", mips_emit_undef, 0x3B, 0x1},\n    {\"scd\", mips_emit_scd, 0x3C, 0x1},\n    {\"sdc1\", mips_emit_sdc1, 0x3D, 0x1},\n    {\"sdc2\", mips_emit_sdc2, 0x3E, 0x1},\n    {\"sd\", mips_emit_sd, 0x3F, 0x1},\n};\n\n/* Based on the func field of spec opcode */\nstatic struct mips_jit_desc mips_spec_jit[] = {\n    {\"sll\", mips_emit_sll, 0x00, 0x1},\n    {\"movc\", mips_emit_movc, 0x01, 0x1},\n    {\"srl\", mips_emit_srl, 0x02, 0x1},\n    {\"sra\", mips_emit_sra, 0x03, 0x1},\n    {\"sllv\", mips_emit_sllv, 0x04, 0x1},\n    {\"unknownSpec\", mips_emit_unknownSpec, 0x05, 0x1},\n    {\"srlv\", mips_emit_srlv, 0x06, 0x1},\n    {\"srav\", mips_emit_srav, 0x07, 0x1},\n    {\"jr\", mips_emit_jr, 0x08, 0x0},\n    {\"jalr\", mips_emit_jalr, 0x09, 0x0},\n    {\"movz\", mips_emit_movz, 0x0A, 0x1},\n    {\"movn\", mips_emit_movn, 0x0B, 0x1},\n    {\"syscall\", mips_emit_syscall, 0x0C, 0x1},\n    {\"break\", mips_emit_break, 0x0D, 0x1},\n    {\"spim\", mips_emit_unknownSpec, 0x0E, 0x1},\n    {\"sync\", mips_emit_sync, 0x0F, 0x1},\n    {\"mfhi\", mips_emit_mfhi, 0x10, 0x1},\n    {\"mthi\", mips_emit_mthi, 0x11, 0x1},\n    {\"mflo\", mips_emit_mflo, 0x12, 0x1},\n    {\"mtlo\", mips_emit_mtlo, 0x13, 0x1},\n    {\"dsllv\", mips_emit_dsllv, 0x14, 0x1},\n    {\"unknownSpec\", mips_emit_unknownSpec, 0x15, 0x1},\n    {\"dsrlv\", mips_emit_dsrlv, 0x16, 0x1},\n    {\"dsrav\", mips_emit_dsrav, 0x17, 0x1},\n    {\"mult\", mips_emit_mult, 0x18, 0x1},\n    {\"multu\", mips_emit_multu, 0x19, 0x1},\n    {\"div\", mips_emit_div, 0x1A, 0x1},\n    {\"divu\", mips_emit_divu, 0x1B, 0x1},\n    {\"dmult\", mips_emit_dmult, 0x1C, 0x1},\n    {\"dmultu\", mips_emit_dmultu, 0x1D, 0x1},\n    {\"ddiv\", mips_emit_ddiv, 0x1E, 0x1},\n    {\"ddivu\", mips_emit_ddivu, 0x1F, 0x1},\n    {\"add\", mips_emit_add, 0x20, 0x1},\n    {\"addu\", mips_emit_addu, 0x21, 0x1},\n    {\"sub\", mips_emit_sub, 0x22, 0x1},\n    {\"subu\", mips_emit_subu, 0x23, 0x1},\n    {\"and\", mips_emit_and, 0x24, 0x1},\n    {\"or\", mips_emit_or, 0x25, 0x1},\n    {\"xor\", mips_emit_xor, 0x26, 0x1},\n    {\"nor\", mips_emit_nor, 0x27, 0x1},\n    {\"unknownSpec\", mips_emit_unknownSpec, 0x28, 0x1},\n    {\"unknownSpec\", mips_emit_unknownSpec, 0x29, 0x1},\n    {\"slt\", mips_emit_slt, 0x2A, 0x1},\n    {\"sltu\", mips_emit_sltu, 0x2B, 0x1},\n    {\"dadd\", mips_emit_dadd, 0x2C, 0x1},\n    {\"daddu\", mips_emit_daddu, 0x2D, 0x1},\n    {\"dsub\", mips_emit_dsub, 0x2E, 0x1},\n    {\"dsubu\", mips_emit_dsubu, 0x2F, 0x1},\n    {\"tge\", mips_emit_tge, 0x30, 0x1},\n    {\"tgeu\", mips_emit_tgeu, 0x31, 0x1},\n    {\"tlt\", mips_emit_tlt, 0x32, 0x1},\n    {\"tltu\", mips_emit_tltu, 0x33, 0x1},\n    {\"teq\", mips_emit_teq, 0x34, 0x1},\n    {\"unknownSpec\", mips_emit_unknownSpec, 0x35, 0x1},\n    {\"tne\", mips_emit_tne, 0x36, 0x1},\n    {\"unknownSpec\", mips_emit_unknownSpec, 0x37, 0x1},\n    {\"dsll\", mips_emit_dsll, 0x38, 0x1},\n    {\"unknownSpec\", mips_emit_unknownSpec, 0x39, 0x1},\n    {\"dsrl\", mips_emit_dsrl, 0x3A, 0x1},\n    {\"dsra\", mips_emit_dsra, 0x3B, 0x1},\n    {\"dsll32\", mips_emit_dsll32, 0x3C, 0x1},\n    {\"unknownSpec\", mips_emit_unknownSpec, 0x3D, 0x1},\n    {\"dsrl32\", mips_emit_dsrl32, 0x3E, 0x1},\n    {\"dsra32\", mips_emit_dsra32, 0x3F, 0x1}\n};\n\n/* Based on the rt field of bcond opcodes */\nstatic struct mips_jit_desc mips_bcond_jit[] = {\n    {\"bltz\", mips_emit_bltz, 0x00, 0x0},\n    {\"bgez\", mips_emit_bgez, 0x01, 0x0},\n    {\"bltzl\", mips_emit_bltzl, 0x02, 0x0},\n    {\"bgezl\", mips_emit_bgezl, 0x03, 0x0},\n    {\"spimi\", mips_emit_unknownBcond, 0x04, 0x0},\n    {\"unknownBcond\", mips_emit_unknownBcond, 0x05, 0x1},\n    {\"unknownBcond\", mips_emit_unknownBcond, 0x06, 0x1},\n    {\"unknownBcond\", mips_emit_unknownBcond, 0x07, 0x1},\n    {\"tgei\", mips_emit_tgei, 0x08, 0x1},\n    {\"tgeiu\", mips_emit_tgeiu, 0x09, 0x1},\n    {\"tlti\", mips_emit_tlti, 0x0A, 0x1},\n    {\"tltiu\", mips_emit_tltiu, 0x0B, 0x1},\n    {\"teqi\", mips_emit_teqi, 0x0C, 0x1},\n    {\"unknownBcond\", mips_emit_unknownBcond, 0x0D, 0x1},\n    {\"tnei\", mips_emit_tnei, 0x0E, 0x1},\n    {\"unknownBcond\", mips_emit_unknownBcond, 0x0F, 0x1},\n    {\"bltzal\", mips_emit_bltzal, 0x10, 0x0},\n    {\"bgezal\", mips_emit_bgezal, 0x11, 0x0},\n    {\"bltzall\", mips_emit_bltzall, 0x12, 0x0},\n    {\"bgezall\", mips_emit_bgezall, 0x13, 0x0},\n    {\"unknownBcond\", mips_emit_unknownBcond, 0x14, 0x1},\n    {\"unknownBcond\", mips_emit_unknownBcond, 0x15, 0x1},\n    {\"unknownBcond\", mips_emit_unknownBcond, 0x16, 0x1},\n    {\"unknownBcond\", mips_emit_unknownBcond, 0x17, 0x1},\n    {\"unknownBcond\", mips_emit_unknownBcond, 0x18, 0x1},\n    {\"unknownBcond\", mips_emit_unknownBcond, 0x19, 0x1},\n    {\"unknownBcond\", mips_emit_unknownBcond, 0x1A, 0x1},\n    {\"unknownBcond\", mips_emit_unknownBcond, 0x1B, 0x1},\n    {\"unknownBcond\", mips_emit_unknownBcond, 0x1C, 0x1},\n    {\"unknownBcond\", mips_emit_unknownBcond, 0x1D, 0x1},\n    {\"unknownBcond\", mips_emit_unknownBcond, 0x1E, 0x1},\n    {\"unknownBcond\", mips_emit_unknownBcond, 0x1F, 0x1}\n};\n\nstatic struct mips_jit_desc mips_cop0_jit[] = {\n    {\"mfc0\", mips_emit_mfc0, 0x0, 0x1},\n    {\"dmfc0\", mips_emit_dmfc0, 0x1, 0x1},\n    {\"cfc0\", mips_emit_cfc0, 0x2, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0x3, 0x1},\n    {\"mtc0\", mips_emit_mtc0, 0x4, 0x1},\n    {\"dmtc0\", mips_emit_dmtc0, 0x5, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0x6, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0x7, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0x8, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0x9, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0xa, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0xb, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0xc, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0xd, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0xe, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0xf, 0x1},\n    {\"tlb\", mips_emit_tlb, 0x10, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0x11, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0x12, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0x13, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0x14, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0x15, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0x16, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0x17, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0x18, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0x19, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0x1a, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0x1b, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0x1c, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0x1d, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0x1e, 0x1},\n    {\"unknowncop0\", mips_emit_unknowncop0, 0x1f, 0x1},\n\n};\n\nstatic struct mips_jit_desc mips_mad_jit[] = {\n    {\"mad\", mips_emit_madd, 0x0, 0x1},\n    {\"maddu\", mips_emit_maddu, 0x1, 0x1},\n    {\"mul\", mips_emit_mul, 0x2, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x3, 0x1},\n    {\"msub\", mips_emit_msub, 0x4, 0x1},\n    {\"msubu\", mips_emit_msubu, 0x5, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x6, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x7, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x8, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x9, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0xa, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0xb, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0xc, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0xd, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0xe, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0xf, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x10, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x11, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x12, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x13, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x14, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x15, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x16, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x17, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x18, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x19, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x1a, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x1b, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x1c, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x1d, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x1e, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x1f, 0x1},\n    {\"clz\", mips_emit_clz, 0x20, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x21, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x22, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x23, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x24, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x25, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x26, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x27, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x28, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x29, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x2a, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x2b, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x2c, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x2d, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x2e, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x2f, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x30, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x31, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x32, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x33, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x34, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x35, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x36, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x37, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x38, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x39, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x3a, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x3b, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x3c, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x3d, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x3e, 0x1},\n    {\"unknownmad_op\", mips_emit_unknownmad, 0x3f, 0x1},\n\n};\n\nstatic struct mips_jit_desc mips_tlb_jit[] = {\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x0, 0x1},\n    {\"tlbr\", mips_emit_tlbr, 0x1, 0x1},\n    {\"tlbwi\", mips_emit_tlbwi, 0x2, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x3, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x4, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x5, 0x1},\n    {\"tlbwi\", mips_emit_tlbwr, 0x6, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x7, 0x1},\n    {\"tlbp\", mips_emit_tlbp, 0x8, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x9, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0xa, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0xb, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0xc, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0xd, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0xe, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0xf, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x10, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x11, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x12, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x13, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x14, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x15, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x16, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x17, 0x1},\n    {\"eret\", mips_emit_eret, 0x18, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x19, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x1a, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x1b, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x1c, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x1d, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x1e, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x1f, 0x1},\n    {\"wait\", mips_emit_wait, 0x20, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x21, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x22, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x23, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x24, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x25, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x26, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x27, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x28, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x29, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x2a, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x2b, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x2c, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x2d, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x2e, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x2f, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x30, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x31, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x32, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x33, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x34, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x35, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x36, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x37, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x38, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x39, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x3a, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x3b, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x3c, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x3d, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x3e, 0x1},\n    {\"unknowntlb_op\", mips_emit_unknowntlb, 0x3f, 0x1},\n\n};\n#endif\n"
  },
  {
    "path": "tools/virtualmips/x86_trans.h",
    "content": "/*\n * Cisco router simulation platform.\n * Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)\n */\n/*\n * Copyright (C) yajin 2008 <yajinzhou@gmail.com >\n *\n * This file is part of the virtualmips distribution.\n * See LICENSE file for terms of the license.\n *\n */\n\n#ifndef __MIPS64_X86_TRANS_H__\n\n#define __MIPS64_X86_TRANS_H__\n\n#include \"system.h\"\n#include \"x86-codegen.h\"\n\n#ifdef _USE_JIT_\n\n/* Manipulate bitmasks atomically */\nstatic forced_inline void x86_atomic_or (m_uint32_t * v, m_uint32_t m)\n{\n    __asm__ __volatile__ (\"lock; orl %1,%0\":\"=m\" (*v):\"ir\" (m), \"m\" (*v));\n}\n\nstatic forced_inline void x86_atomic_and (m_uint32_t * v, m_uint32_t m)\n{\n    __asm__ __volatile__ (\"lock; andl %1,%0\":\"=m\" (*v):\"ir\" (m), \"m\" (*v));\n}\n\n/* Wrappers to x86-codegen functions */\n#define mips_jit_tcb_set_patch x86_patch\n#define mips_jit_tcb_set_jump  x86_jump_code\n\n/* Push epilog for an x86 instruction block */\nstatic forced_inline void mips_jit_tcb_push_epilog (mips_jit_tcb_t *\n    block)\n{\n    x86_ret (block->jit_ptr);\n}\n\n/* Translated block function pointer */\ntypedef void (*insn_tblock_fptr) (void);\nvoid fastcall mips_exec_single_step (cpu_mips_t * cpu,\n    mips_insn_t instruction);\n\n/* Execute JIT code */\nstatic forced_inline\n    void mips_jit_tcb_exec (cpu_mips_t * cpu, mips_jit_tcb_t * block)\n{\n    insn_tblock_fptr jit_code;\n    m_uint32_t offset;\n\n    offset = (cpu->pc & MIPS_MIN_PAGE_IMASK) >> 2;\n    jit_code = (insn_tblock_fptr) block->jit_insn_ptr[offset];\n\n    if (unlikely (!jit_code)) {\n        mips_exec_single_step (cpu, vmtoh32 (block->mips_code[offset]));\n        return;\n    }\n\n    asm volatile (\"movl %0,%%edi\"::\"r\" (cpu): \"esi\", \"edi\", \"ecx\", \"edx\");\n    jit_code ();\n}\n\nvoid mips_set_pc (mips_jit_tcb_t * b, m_va_t new_pc);\nvoid mips_emit_single_step (mips_jit_tcb_t * b, mips_insn_t insn);\nvoid mips_check_cpu_pausing (mips_jit_tcb_t * b);\nvoid mips_check_pending_irq (mips_jit_tcb_t * b);\n\n#endif\n\n#endif\n"
  },
  {
    "path": "usr.sbin/Makefile",
    "content": "#\n# Public domain - 1996/10/24 - sms\n#\n#\t@(#)Makefile\t1.2 (2.11BSD) 1997/6/27\n#\nTOPSRC!=cd ..; pwd\ninclude ${TOPSRC}/share/mk/sys.mk\n\nSUBDIR=\tchroot cron disktool iostat mkpasswd pstat talloc \\\n\tupdate vipw\n\n# TODO: devupdate\n\nall:\t${SUBDIR}\n\n${SUBDIR}: FRC\n\tcd $@; ${MAKE} ${MFLAGS} all\n\nFRC:\n\ninstall: FRC\n\t-for i in ${SUBDIR}; do \\\n\t\t(cd $$i; ${MAKE} ${MFLAGS} DESTDIR=${DESTDIR} install); done\n\nclean:\n\t/bin/rm -f a.out core *.s *.o *.dis *.elf *~ errs\n\tfor i in ${SUBDIR}; do (cd $$i; ${MAKE} ${MFLAGS} clean); done\n"
  }
]